diff --git a/.gitattributes b/.gitattributes index 4821411509..deeee5e25c 100755 --- a/.gitattributes +++ b/.gitattributes @@ -1,3 +1,8 @@ +*.c linguist-language=C +*.C linguist-language=C +*.h linguist-language=C +*.H linguist-language=C + * text=auto *.S text diff --git a/.gitee/PULL_REQUEST_TEMPLATE.en.md b/.gitee/PULL_REQUEST_TEMPLATE.en.md index b621e6f035..9d72f03307 100644 --- a/.gitee/PULL_REQUEST_TEMPLATE.en.md +++ b/.gitee/PULL_REQUEST_TEMPLATE.en.md @@ -27,3 +27,4 @@ As part of this pull request, I've considered the following: - [ ] All modifications to BSP are justified and do not affect other components or BSPs. - [ ] I've commented appropriately where code is tricky. - [ ] Code in this PR is of high quality. +- [ ] This PR complies with [RT-Thread code specification](../documentation/coding_style_en.txt) diff --git a/.gitee/PULL_REQUEST_TEMPLATE.zh-CN.md b/.gitee/PULL_REQUEST_TEMPLATE.zh-CN.md index a992458ef4..b64136d96d 100644 --- a/.gitee/PULL_REQUEST_TEMPLATE.zh-CN.md +++ b/.gitee/PULL_REQUEST_TEMPLATE.zh-CN.md @@ -27,3 +27,4 @@ - [ ] 所有变更均有原因及合理的，并且不会影响到其他软件组件代码或 - [ ] 对难懂代码均提供对应的注释 - [ ] 本拉取/合并请求代码是高质量的 +- [ ] 本拉取/合并符合[RT-Thread代码规范](../documentation/coding_style_cn.md) diff --git a/.gitee/PULL_REQUEST_TEMPLATE.zh-TW.md b/.gitee/PULL_REQUEST_TEMPLATE.zh-TW.md index 9788e1a39f..2bbf94f5fc 100644 --- a/.gitee/PULL_REQUEST_TEMPLATE.zh-TW.md +++ b/.gitee/PULL_REQUEST_TEMPLATE.zh-TW.md @@ -27,3 +27,4 @@ - [ ] 所有變更均有原因及合理的，並且不會影響到其他軟件組件代碼或 - [ ] 對難懂代碼均提供對應的註釋 - [ ] 本拉取/合並請求代碼是高質量的 +- [ ] 本拉取/合並符合[RT-Thread代碼規範](../documentation/coding_style_cn.md) diff --git a/.github/PULL_REQUEST_TEMPLATE.md b/.github/PULL_REQUEST_TEMPLATE.md index 59f2b88a13..1f092851b0 100644 --- a/.github/PULL_REQUEST_TEMPLATE.md +++ b/.github/PULL_REQUEST_TEMPLATE.md @@ -31,3 +31,4 @@ The following content must not be changed in the submitted PR message. Otherwise - [ ] 所有变更均有原因及合理的，并且不会影响到其他软件组件代码或BSP All modifications are justified and not affect other components or BSP - [ ] 对难懂代码均提供对应的注释 I've commented appropriately where code is tricky - [ ] 本拉取/合并请求代码是高质量的 Code in this PR is of high quality +- [ ] 本拉取/合并符合[RT-Thread代码规范](../documentation/coding_style_cn.md) This PR complies with [RT-Thread code specification](../documentation/coding_style_en.txt) diff --git a/.github/workflows/action.yml b/.github/workflows/action.yml index c6b9930c90..2a5697964a 100644 --- a/.github/workflows/action.yml +++ b/.github/workflows/action.yml @@ -32,14 +32,14 @@ jobs: - {RTT_BSP: "CME_M7", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "apollo2", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "asm9260t", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "at91sam9260", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "allwinner_tina", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "efm32", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "gd32e230k-start", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "gd32303e-eval", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "at91sam9260", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "allwinner_tina", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "efm32", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "gd32e230k-start", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "gd32303e-eval", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "gd32450z-eval", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "imx6sx/cortex-a9", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "imxrt/imxrt1052-atk-commander", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "imx6sx/cortex-a9", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "imxrt/imxrt1052-atk-commander", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "imxrt/imxrt1052-fire-pro", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "imxrt/imxrt1052-nxp-evk", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "lm3s8962", RTT_TOOL_CHAIN: "sourcery-arm"} @@ -55,7 +55,7 @@ jobs: - {RTT_BSP: "lpc2148", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "lpc2478", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "lpc5410x", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "lpc54114-lite", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "lpc54114-lite", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "ls1bdev", RTT_TOOL_CHAIN: "sourcery-mips"} - {RTT_BSP: "ls1cdev", RTT_TOOL_CHAIN: "sourcery-mips"} - {RTT_BSP: "mb9bf500r", RTT_TOOL_CHAIN: "sourcery-arm"} @@ -63,10 +63,10 @@ jobs: - {RTT_BSP: "mb9bf618s", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "mb9bf568r", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "mini2440", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "qemu-vexpress-a9", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "qemu-vexpress-gemini", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "sam7x", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32f072-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "qemu-vexpress-a9", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "qemu-vexpress-gemini", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "sam7x", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32f072-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f091-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f103-atk-nano", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f103-atk-warshipv3", RTT_TOOL_CHAIN: "sourcery-arm"} @@ -74,14 +74,14 @@ jobs: - {RTT_BSP: "stm32/stm32f103-dofly-M3S", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f103-fire-arbitrary", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f103-hw100k-ibox", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32f103-mini-system", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32f103-blue-pill", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f103-onenet-nbiot", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f103-yf-ufun", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f107-uc-eval", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f401-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f405-smdz-breadfruit", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f407-atk-explorer", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32f407-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32f407-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f410-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f411-atk-nano", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f411-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} @@ -91,45 +91,46 @@ jobs: - {RTT_BSP: "stm32/stm32f429-armfly-v6", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f429-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32f429-fire-challenger", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32f429-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32f446-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32f469-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32f746-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32f767-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32f767-fire-challenger", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32f767-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32g070-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32g071-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32g431-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32f429-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32f446-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32f469-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32f746-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32f767-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32f767-fire-challenger", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32f767-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32g070-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32g071-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32g431-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32h743-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32h743-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32h747-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32h750-artpi-h750", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32l4r9-st-eval", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32l010-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - {RTT_BSP: "stm32/stm32l053-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32l412-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32l432-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32l433-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32l475-atk-pandora", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32l475-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32l476-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32l496-ali-developer", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32l496-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32mp157a-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32mp157a-st-ev1", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32/stm32wb55-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "stm32f20x", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "swm320-lq100", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "beaglebone", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "zynq7000", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "zynqmp-r5-axu4ev", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "frdm-k64f", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "fh8620", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "xplorer4330/M4", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "at32/at32f403a-start", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "at32/at32f407-start", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "smartfusion2", RTT_TOOL_CHAIN: "sourcery-arm"} - - {RTT_BSP: "raspberry-pico", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32l412-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32l432-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32l433-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32l475-atk-pandora", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32l475-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32l476-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32l496-ali-developer", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32l496-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32mp157a-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32mp157a-st-ev1", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32/stm32wb55-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "stm32f20x", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "swm320", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "swm320-lq100", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "beaglebone", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "zynqmp-r5-axu4ev", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "frdm-k64f", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "fh8620", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "xplorer4330/M4", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "at32/at32f403a-start", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "at32/at32f407-start", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "smartfusion2", RTT_TOOL_CHAIN: "sourcery-arm"} + - {RTT_BSP: "raspberry-pico", RTT_TOOL_CHAIN: "sourcery-arm"} steps: - uses: actions/checkout@v2 - name: Set up Python @@ -144,13 +145,13 @@ jobs: sudo apt-get -qq install gcc-multilib libsdl-dev scons echo "RTT_ROOT=${{ github.workspace }}" >> $GITHUB_ENV echo "RTT_CC=gcc" >> $GITHUB_ENV - + - name: Install Arm ToolChains if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-arm' && success() }} shell: bash run: | - wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/arm-2017q2-v6/gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 - sudo tar xjf gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 -C /opt + wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/arm-2017q2-v6/gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 + sudo tar xjf gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 -C /opt /opt/gcc-arm-none-eabi-6-2017-q2-update/bin/arm-none-eabi-gcc --version echo "RTT_EXEC_PATH=/opt/gcc-arm-none-eabi-6-2017-q2-update/bin" >> $GITHUB_ENV @@ -158,8 +159,8 @@ jobs: if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-mips' && success() }} shell: bash run: | - wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/v1.1/mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 - sudo tar xjf mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 -C /opt + wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/v1.1/mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 + sudo tar xjf mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 -C /opt /opt/mips-2016.05/bin/mips-sde-elf-gcc --version echo "RTT_EXEC_PATH=/opt/mips-2016.05/bin" >> $GITHUB_ENV diff --git a/.github/workflows/file_check.yml b/.github/workflows/file_check.yml new file mode 100644 index 0000000000..f1f1994af8 --- /dev/null +++ b/.github/workflows/file_check.yml @@ -0,0 +1,20 @@ +name: Check File Format and License + +on: [pull_request] + +jobs: + scancode_job: + runs-on: ubuntu-latest + name: Scan code format and license + steps: + - uses: actions/checkout@v2 + - name: Set up Python + uses: actions/setup-python@master + with: + python-version: 3.8 + + - name: Check Format and License + shell: bash + run: | + pip install click chardet PyYaml + python tools/file_check.py check 'https://github.com/RT-Thread/rt-thread' 'master' diff --git a/.gitignore b/.gitignore index b532495df2..4e6126542c 100644 --- a/.gitignore +++ b/.gitignore @@ -35,3 +35,6 @@ ncscope.* #ctag files tags +.idea +CMakeLists.txt +cmake-build-debug diff --git a/.ignore_format.yml b/.ignore_format.yml new file mode 100644 index 0000000000..4a0e8bbec7 --- /dev/null +++ b/.ignore_format.yml @@ -0,0 +1,9 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +file_path: +- bsp/allwinner_tina/libcpu/cpu.c + +dir_path: +- tools \ No newline at end of file diff --git a/Jenkinsfile b/Jenkinsfile index a106793bbb..0e4192003b 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -107,7 +107,6 @@ pipeline { ['stm32f20x', 'sourcery-arm'], ['swm320-lq100', 'sourcery-arm'], ['beaglebone', 'sourcery-arm'], - ['zynq7000', 'sourcery-arm'], ['frdm-k64f', 'sourcery-arm'], ['fh8620', 'sourcery-arm'], ['xplorer4330/M4', 'sourcery-arm'], diff --git a/bsp/CME_M7/applications/application.c b/bsp/CME_M7/applications/application.c index 13526c5793..c5346448c3 100644 --- a/bsp/CME_M7/applications/application.c +++ b/bsp/CME_M7/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2014, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -32,10 +28,10 @@ int rt_application_init() tid = rt_thread_create("init", rt_init_thread_entry, - RT_NULL, + RT_NULL, 2048, - RT_THREAD_PRIORITY_MAX/3, - 20); + RT_THREAD_PRIORITY_MAX/3, + 20); if (tid != RT_NULL) rt_thread_startup(tid); diff --git a/bsp/CME_M7/drivers/board.c b/bsp/CME_M7/drivers/board.c index 42ff994b4c..a9c81cdd0a 100644 --- a/bsp/CME_M7/drivers/board.c +++ b/bsp/CME_M7/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2014, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/CME_M7/drivers/board.h b/bsp/CME_M7/drivers/board.h index 8e7425674c..c622b546dd 100644 --- a/bsp/CME_M7/drivers/board.h +++ b/bsp/CME_M7/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009-2014, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -18,7 +14,7 @@ #include "cmem7_includes.h" //#include "cmem7_retarget.h" -#define SRAM_SIZE 64 // KB +#define SRAM_SIZE 64 // KB #define SRAM_END (0x20000000 + SRAM_SIZE * 1024) //#define RT_USING_UART0 diff --git a/bsp/allwinner_tina/applications/main.c b/bsp/allwinner_tina/applications/main.c index 7aaf1f8db3..e974c71ec2 100644 --- a/bsp/allwinner_tina/applications/main.c +++ b/bsp/allwinner_tina/applications/main.c @@ -1,21 +1,7 @@ /* - * File : main.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/allwinner_tina/drivers/board.c b/bsp/allwinner_tina/drivers/board.c index e3b54b3536..c9be412067 100644 --- a/bsp/allwinner_tina/drivers/board.c +++ b/bsp/allwinner_tina/drivers/board.c @@ -1,21 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/allwinner_tina/drivers/board.h b/bsp/allwinner_tina/drivers/board.h index 11c6a9a15f..7b05b21c66 100644 --- a/bsp/allwinner_tina/drivers/board.h +++ b/bsp/allwinner_tina/drivers/board.h @@ -1,21 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/allwinner_tina/drivers/drv_clock.c b/bsp/allwinner_tina/drivers/drv_clock.c index b55cd6af4c..9fec431f4b 100644 --- a/bsp/allwinner_tina/drivers/drv_clock.c +++ b/bsp/allwinner_tina/drivers/drv_clock.c @@ -1,21 +1,7 @@ /* - * File : drv_clock.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -541,7 +527,7 @@ rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz) *mmc_clk &= ~(0x1 << 31); return RT_EOK; } - + if (hz <= 24000000) { pll = (0x0 << 24); @@ -593,7 +579,7 @@ rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz) oclk_dly = 1; sclk_dly = 4; } - + *mmc_clk = (0x1 << 31) | pll | (sclk_dly << 20) | \ (n << 16) | (oclk_dly << 8) | (div - 1); diff --git a/bsp/allwinner_tina/drivers/drv_clock.h b/bsp/allwinner_tina/drivers/drv_clock.h index c1cb87af0a..1623791672 100644 --- a/bsp/allwinner_tina/drivers/drv_clock.h +++ b/bsp/allwinner_tina/drivers/drv_clock.h @@ -1,21 +1,7 @@ /* - * File : drv_clock.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -252,4 +238,4 @@ rt_err_t dram_gate_clk_enable(enum dram_gate dram_gate); rt_err_t dram_gate_clk_disable(enum dram_gate dram_gate); rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz); -#endif \ No newline at end of file +#endif diff --git a/bsp/allwinner_tina/drivers/drv_gpio.c b/bsp/allwinner_tina/drivers/drv_gpio.c index 999ab473a0..099ea7621d 100644 --- a/bsp/allwinner_tina/drivers/drv_gpio.c +++ b/bsp/allwinner_tina/drivers/drv_gpio.c @@ -1,21 +1,7 @@ /* - * File : drv_gpio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/allwinner_tina/drivers/drv_gpio.h b/bsp/allwinner_tina/drivers/drv_gpio.h index 35d368f1c8..74dd5a9be0 100644 --- a/bsp/allwinner_tina/drivers/drv_gpio.h +++ b/bsp/allwinner_tina/drivers/drv_gpio.h @@ -1,21 +1,7 @@ /* - * File : drv_gpio.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -241,4 +227,4 @@ void gpio_set_debounce(enum gpio_port port, rt_uint8_t prescaler); void gpio_set_irq_callback(enum gpio_port port, enum gpio_pin pin, void (*irq_cb)(void *), void *irq_arg); int rt_hw_gpio_init(void); -#endif /* __DRV_GPIO_H__ */ \ No newline at end of file +#endif /* __DRV_GPIO_H__ */ diff --git a/bsp/allwinner_tina/drivers/drv_sdio.c b/bsp/allwinner_tina/drivers/drv_sdio.c index 11b5a63d02..f19cd60d5c 100644 --- a/bsp/allwinner_tina/drivers/drv_sdio.c +++ b/bsp/allwinner_tina/drivers/drv_sdio.c @@ -1,21 +1,7 @@ /* - * File : drv_sdio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -34,10 +20,10 @@ #define DBG_TAG "MMC" -// #define DBG_LVL DBG_LOG -// #define DBG_LVL DBG_INFO +// #define DBG_LVL DBG_LOG +// #define DBG_LVL DBG_INFO #define DBG_LVL DBG_WARNING -// #define DBG_LVL DBG_ERROR +// #define DBG_LVL DBG_ERROR #include #ifdef RT_USING_SDIO @@ -47,12 +33,12 @@ struct mmc_xfe_des { rt_uint32_t size; /* block size */ - rt_uint32_t num; /* block num */ - rt_uint8_t *buff; /* buff addr */ - rt_uint32_t flag; /* write or read or stream */ -#define MMC_DATA_WRITE (1 << 0) -#define MMC_DATA_READ (1 << 1) -#define MMC_DATA_STREAM (1 << 2) + rt_uint32_t num; /* block num */ + rt_uint8_t *buff; /* buff addr */ + rt_uint32_t flag; /* write or read or stream */ +#define MMC_DATA_WRITE (1 << 0) +#define MMC_DATA_READ (1 << 1) +#define MMC_DATA_STREAM (1 << 2) }; struct mmc_flag @@ -71,7 +57,7 @@ struct sdio_drv tina_mmc_t mmc_des; rt_uint8_t *mmc_buf; rt_uint8_t usedma; - + }; #ifdef CONFIG_MMC_USE_DMA @@ -136,7 +122,7 @@ static int mmc_update_clk(tina_mmc_t mmc) mmc->risr_reg = mmc->risr_reg; return RT_EOK; } - + static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe) { ALIGN(32) static struct mmc_des_v4p1 pdes[128]; // mast ALIGN(32) @@ -145,7 +131,7 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe) unsigned length = xfe->size * xfe->num; unsigned buff_frag_num = length >> SDXC_DES_NUM_SHIFT; unsigned remain = length & (SDXC_DES_BUFFER_MAX_LEN - 1); - + if (remain) { buff_frag_num ++; @@ -156,7 +142,7 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe) } memset(pdes, 0, sizeof(pdes)); mmu_clean_dcache((rt_uint32_t)(xfe->buff), length); - for (i = 0, des_idx = 0; i < buff_frag_num; i++, des_idx++) + for (i = 0, des_idx = 0; i < buff_frag_num; i++, des_idx++) { // memset((void*)&pdes[des_idx], 0, sizeof(struct mmc_v4p1)); pdes[des_idx].des_chain = 1; @@ -182,8 +168,8 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe) pdes[des_idx].last_des = 1; pdes[des_idx].end_of_ring = 1; pdes[des_idx].buf_addr_ptr2 = 0; - } - else + } + else { pdes[des_idx].buf_addr_ptr2 = (unsigned long)&pdes[des_idx+1]; } @@ -217,7 +203,7 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe) mmc->dmac_reg = (1 << 1) | (1 << 7); /* idma on */ rval = mmc->idie_reg & (~3); if (xfe->flag == MMC_DATA_WRITE) - rval |= (1 << 0); + rval |= (1 << 0); else rval |= (1 << 1); mmc->idie_reg = rval; @@ -236,7 +222,7 @@ static rt_err_t mmc_trans_data_by_cpu(tina_mmc_t mmc, struct mmc_xfe_des *xfe) if (xfe->flag == MMC_DATA_WRITE) { - for (i = 0; i < (byte_cnt >> 2); i++) + for (i = 0; i < (byte_cnt >> 2); i++) { while(--timeout && (mmc->star_reg & (1 << 3))); @@ -251,7 +237,7 @@ static rt_err_t mmc_trans_data_by_cpu(tina_mmc_t mmc, struct mmc_xfe_des *xfe) } else { - for (i = 0; i < (byte_cnt >> 2); i++) + for (i = 0; i < (byte_cnt >> 2); i++) { while(--timeout && (mmc->star_reg & (1 << 2))); @@ -290,7 +276,7 @@ static rt_err_t mmc_config_clock(tina_mmc_t mmc, int clk) { mmc_set_clk(SDMMC1, clk); } - + /* Re-enable card clock */ rval = mmc->ckcr_reg; rval |= (0x1 << 16); //(3 << 16); @@ -383,7 +369,7 @@ static int mmc_send_cmd(struct rt_mmcsd_host *host, struct rt_mmcsd_cmd *cmd) cmdval |= (1 << 7); if ((resp_type(cmd) != RESP_R3) && (resp_type(cmd) != RESP_R4)) cmdval |= (1 << 8); - + if (data) { cmdval |= (1 << 9) | (1 << 13); @@ -606,7 +592,7 @@ static void sdio_request_send(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r memset(&sdio->flag, 0, sizeof(struct mmc_flag)); mmc_send_cmd(host, req->cmd); - + return; } diff --git a/bsp/allwinner_tina/drivers/drv_sdio.h b/bsp/allwinner_tina/drivers/drv_sdio.h index 742d5362e1..ef7a7c4108 100644 --- a/bsp/allwinner_tina/drivers/drv_sdio.h +++ b/bsp/allwinner_tina/drivers/drv_sdio.h @@ -1,21 +1,7 @@ /* - * File : drv_sdio.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -133,8 +119,8 @@ REG[31] : Load cmd #define SDXC_UPDATE_CLOCK_CMD BIT(21) #define SDXC_LOAD_CMD BIT(31) -/* - SD status reg +/* + SD status reg REG[0] : FIFO_RX_LEVEL REG[1] : FIFO_TX_LEVEL REG[2] : FIFO_EMPTY @@ -143,7 +129,7 @@ REG[4-7] : FSM_STA REG[8] : CARD_PRESENT REG[9] : CARD_BUSY REG[10] : FSM_BUSY -REG[11-16]: RESP_IDX +REG[11-16]: RESP_IDX REG[17-21]: FIFO_LEVEL REG[31] : DMA_REQ */ diff --git a/bsp/allwinner_tina/drivers/drv_uart.c b/bsp/allwinner_tina/drivers/drv_uart.c index ede0eee4e4..a2889c598f 100644 --- a/bsp/allwinner_tina/drivers/drv_uart.c +++ b/bsp/allwinner_tina/drivers/drv_uart.c @@ -1,21 +1,7 @@ /* - * File : drv_uart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -324,4 +310,4 @@ void uart_irq_handler(int irqno, void *param) } -#endif \ No newline at end of file +#endif diff --git a/bsp/allwinner_tina/drivers/drv_uart.h b/bsp/allwinner_tina/drivers/drv_uart.h index 25cb271c6e..d7c923d373 100644 --- a/bsp/allwinner_tina/drivers/drv_uart.h +++ b/bsp/allwinner_tina/drivers/drv_uart.h @@ -1,21 +1,7 @@ /* - * File : drv_uart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/allwinner_tina/drivers/spi/drv_spi.c b/bsp/allwinner_tina/drivers/spi/drv_spi.c index d57cc15d7c..cd1f2aa383 100644 --- a/bsp/allwinner_tina/drivers/spi/drv_spi.c +++ b/bsp/allwinner_tina/drivers/spi/drv_spi.c @@ -1,21 +1,7 @@ /* - * File : drv_spi.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/allwinner_tina/drivers/spi/drv_spi.h b/bsp/allwinner_tina/drivers/spi/drv_spi.h index e9b9981542..1384663774 100644 --- a/bsp/allwinner_tina/drivers/spi/drv_spi.h +++ b/bsp/allwinner_tina/drivers/spi/drv_spi.h @@ -1,21 +1,7 @@ /* - * File : drv_spi.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/allwinner_tina/drivers/spi/drv_spi_flash.c b/bsp/allwinner_tina/drivers/spi/drv_spi_flash.c index 7aecc5411d..5e4edc9c6b 100644 --- a/bsp/allwinner_tina/drivers/spi/drv_spi_flash.c +++ b/bsp/allwinner_tina/drivers/spi/drv_spi_flash.c @@ -1,21 +1,7 @@ /* - * File : drv_spi_flash.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -65,4 +51,4 @@ INIT_PREV_EXPORT(rt_hw_spi_flash_with_sfud_init); #endif -#endif \ No newline at end of file +#endif diff --git a/bsp/allwinner_tina/libcpu/context_gcc.S b/bsp/allwinner_tina/libcpu/context_gcc.S index 5152618d24..c874b16b4b 100644 --- a/bsp/allwinner_tina/libcpu/context_gcc.S +++ b/bsp/allwinner_tina/libcpu/context_gcc.S @@ -1,21 +1,7 @@ ;/* -; * File : context_iar.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2006, RT-Thread Development Team +; * Copyright (c) 2006-2021, RT-Thread Development Team ; * -; * This program is free software; you can redistribute it and/or modify -; * it under the terms of the GNU General Public License as published by -; * the Free Software Foundation; either version 2 of the License, or -; * (at your option) any later version. -; * -; * This program is distributed in the hope that it will be useful, -; * but WITHOUT ANY WARRANTY; without even the implied warranty of -; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; * GNU General Public License for more details. -; * -; * You should have received a copy of the GNU General Public License along -; * with this program; if not, write to the Free Software Foundation, Inc., -; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +; * SPDX-License-Identifier: Apache-2.0 ; * ; * Change Logs: ; * Date Author Notes diff --git a/bsp/allwinner_tina/libcpu/cpu.c b/bsp/allwinner_tina/libcpu/cpu.c index 23953dea42..19baa4d9fe 100644 --- a/bsp/allwinner_tina/libcpu/cpu.c +++ b/bsp/allwinner_tina/libcpu/cpu.c @@ -1,21 +1,7 @@ /* - * File : cpu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/allwinner_tina/libcpu/cpuport.c b/bsp/allwinner_tina/libcpu/cpuport.c index 5def9905f8..94f2baf415 100644 --- a/bsp/allwinner_tina/libcpu/cpuport.c +++ b/bsp/allwinner_tina/libcpu/cpuport.c @@ -1,21 +1,7 @@ /* - * File : cpuport.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/allwinner_tina/libcpu/interrupt.c b/bsp/allwinner_tina/libcpu/interrupt.c index 14f53b6881..7c4e5cda1b 100644 --- a/bsp/allwinner_tina/libcpu/interrupt.c +++ b/bsp/allwinner_tina/libcpu/interrupt.c @@ -1,25 +1,12 @@ /* - * File : interrupt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2018-02-08 RT-Thread the first version + * 2020-03-02 Howard Su Use structure to access registers */ #include @@ -38,9 +25,6 @@ static void rt_hw_interrupt_handler(int vector, void *param) rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } -#define readl(addr) (*(volatile unsigned int *)(addr)) -#define writel(value,addr) (*(volatile unsigned int *)(addr) = (value)) - /** * This function will initialize hardware interrupt */ @@ -63,20 +47,20 @@ void rt_hw_interrupt_init(void) /* set base_addr reg */ INTC->base_addr_reg = 0x00000000; /* clear enable */ - INTC->en_reg0 = 0x00000000; - INTC->en_reg1 = 0x00000000; + INTC->en_reg[0] = 0x00000000; + INTC->en_reg[1] = 0x00000000; /* mask interrupt */ - INTC->mask_reg0 = 0xFFFFFFFF; - INTC->mask_reg1 = 0xFFFFFFFF; + INTC->mask_reg[0] = 0xFFFFFFFF; + INTC->mask_reg[1] = 0xFFFFFFFF; /* clear pending */ - INTC->pend_reg0 = 0x00000000; - INTC->pend_reg1 = 0x00000000; + INTC->pend_reg[0] = 0x00000000; + INTC->pend_reg[1] = 0x00000000; /* set priority */ - INTC->resp_reg0 = 0x00000000; - INTC->resp_reg1 = 0x00000000; + INTC->resp_reg[0] = 0x00000000; + INTC->resp_reg[1] = 0x00000000; /* close fiq interrupt */ - INTC->ff_reg0 = 0x00000000; - INTC->ff_reg1 = 0x00000000; + INTC->ff_reg[0] = 0x00000000; + INTC->ff_reg[1] = 0x00000000; } /** @@ -85,20 +69,16 @@ void rt_hw_interrupt_init(void) */ void rt_hw_interrupt_mask(int vector) { - rt_uint32_t mask_addr, data; - + int index; if ((vector < 0) || (vector > INTERRUPTS_MAX)) { return; } - mask_addr = (rt_uint32_t)(&INTC->mask_reg0); - mask_addr += vector & 0xE0 ? sizeof(rt_uint32_t *) : 0; + index = (vector & 0xE0) != 0; + vector = (vector & 0x1F); - vector &= 0x1F; - data = readl(mask_addr); - data |= 0x1 << vector; - writel(data, mask_addr); + INTC->mask_reg[index] |= 1 << vector; } /** @@ -108,20 +88,16 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { - rt_uint32_t mask_addr, data; - + int index; if ((vector < 0) || (vector > INTERRUPTS_MAX)) { return; } - mask_addr = (rt_uint32_t)(&INTC->mask_reg0); - mask_addr += vector & 0xE0 ? sizeof(rt_uint32_t *) : 0; + index = (vector & 0xE0) != 0; + vector = (vector & 0x1F); - vector &= 0x1F; - data = readl(mask_addr); - data &= ~(0x1 << vector); - writel(data, mask_addr); + INTC->mask_reg[index] &= ~(1 << vector); } /** @@ -136,7 +112,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, const char *name) { rt_isr_handler_t old_handler = RT_NULL; - rt_uint32_t pend_addr, en_addr, data; + int index; if ((vector < 0) || (vector > INTERRUPTS_MAX)) { @@ -151,19 +127,11 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, isr_table[vector].handler = handler; isr_table[vector].param = param; - pend_addr = (rt_uint32_t)(&INTC->pend_reg0); - en_addr = (rt_uint32_t)(&INTC->en_reg0); - pend_addr += vector & 0xE0 ? sizeof(rt_uint32_t *) : 0; - en_addr += vector & 0xE0 ? sizeof(rt_uint32_t *) : 0; + index = (vector & 0xE0) != 0; + vector = (vector & 0x1F); - vector &= 0x1F; - data = readl(pend_addr); - data &= ~(0x1 << vector); - writel(data, pend_addr); - - data = readl(en_addr); - data |= 0x1 << vector; - writel(data, en_addr); + INTC->pend_reg[index] &= ~(0x1 << vector); + INTC->en_reg[index] |= 0x1 << vector; return old_handler; } @@ -173,7 +141,7 @@ void rt_interrupt_dispatch(rt_uint32_t fiq_irq) void *param; int vector; rt_isr_handler_t isr_func; - rt_uint32_t pend_addr, data; + int index; vector = INTC->vector_reg - INTC->base_addr_reg; vector = vector >> 2; @@ -184,13 +152,11 @@ void rt_interrupt_dispatch(rt_uint32_t fiq_irq) /* jump to fun */ isr_func(vector, param); /* clear pend bit */ - pend_addr = (rt_uint32_t)(&INTC->pend_reg0); - pend_addr += vector & 0xE0 ? sizeof(rt_uint32_t *) : 0; - vector &= 0x1F; - data = readl(pend_addr); - data &= ~(0x1 << vector); - writel(data, pend_addr); + index = (vector & 0xE0) != 0; + vector = (vector & 0x1F); + + INTC->pend_reg[index] &= ~(0x1 << vector); #ifdef RT_USING_INTERRUPT_INFO isr_table[vector].counter ++; diff --git a/bsp/allwinner_tina/libcpu/interrupt.h b/bsp/allwinner_tina/libcpu/interrupt.h index 2292b794bd..bdc0d33c39 100644 --- a/bsp/allwinner_tina/libcpu/interrupt.h +++ b/bsp/allwinner_tina/libcpu/interrupt.h @@ -1,25 +1,12 @@ /* - * File : interrupt.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2018-02-08 RT-Thread the first version + * 2020-03-2 Howard Su Define same regsiters as an array */ #ifndef __INTERRUPT_H__ #define __INTERRUPT_H__ @@ -74,34 +61,21 @@ struct tina_intc volatile rt_uint32_t base_addr_reg; /* 0x04 */ volatile rt_uint32_t reserved0; volatile rt_uint32_t nmi_ctrl_reg; /* 0x0C */ - volatile rt_uint32_t pend_reg0; /* 0x10 */ - volatile rt_uint32_t pend_reg1; /* 0x14 */ + volatile rt_uint32_t pend_reg[2]; /* 0x10, 0x14 */ volatile rt_uint32_t reserved1[2]; - volatile rt_uint32_t en_reg0; /* 0x20 */ - volatile rt_uint32_t en_reg1; /* 0x24 */ + volatile rt_uint32_t en_reg[2]; /* 0x20, 0x24 */ volatile rt_uint32_t reserved2[2]; - volatile rt_uint32_t mask_reg0; /* 0x30 */ - volatile rt_uint32_t mask_reg1; /* 0x34 */ + volatile rt_uint32_t mask_reg[2]; /* 0x30, 0x34 */ volatile rt_uint32_t reserved3[2]; - volatile rt_uint32_t resp_reg0; /* 0x40 */ - volatile rt_uint32_t resp_reg1; /* 0x44 */ + volatile rt_uint32_t resp_reg[2]; /* 0x40, 0x44 */ volatile rt_uint32_t reserved4[2]; - volatile rt_uint32_t ff_reg0; /* 0x50 */ - volatile rt_uint32_t ff_reg1; /* 0x54 */ + volatile rt_uint32_t ff_reg[2]; /* 0x50, 0x54 */ volatile rt_uint32_t reserved5[2]; - volatile rt_uint32_t prio_reg0; /* 0x60 */ - volatile rt_uint32_t prio_reg1; /* 0x64 */ - volatile rt_uint32_t prio_reg2; /* 0x68 */ - volatile rt_uint32_t prio_reg3; /* 0x6C */ + volatile rt_uint32_t prio_reg[4]; /* 0x60 - 0x6c */ } ; typedef struct tina_intc *tina_intc_t; #define INTC ((tina_intc_t)INTC_BASE_ADDR) -void rt_hw_interrupt_init(void); -void rt_hw_interrupt_mask(int vector); -void rt_hw_interrupt_umask(int vector); -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, const char *name); - #endif /* __INTERRUPT_H__ */ diff --git a/bsp/allwinner_tina/libcpu/mmu.c b/bsp/allwinner_tina/libcpu/mmu.c index 177668a23b..a30f613ca9 100644 --- a/bsp/allwinner_tina/libcpu/mmu.c +++ b/bsp/allwinner_tina/libcpu/mmu.c @@ -1,21 +1,7 @@ /* - * File : mmu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/allwinner_tina/libcpu/mmu.h b/bsp/allwinner_tina/libcpu/mmu.h index b73f59c288..63853e6d34 100644 --- a/bsp/allwinner_tina/libcpu/mmu.h +++ b/bsp/allwinner_tina/libcpu/mmu.h @@ -1,21 +1,7 @@ /* - * File : mmu.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/allwinner_tina/libcpu/rt_low_level_init.c b/bsp/allwinner_tina/libcpu/rt_low_level_init.c index 807b9b203d..eb576979c4 100644 --- a/bsp/allwinner_tina/libcpu/rt_low_level_init.c +++ b/bsp/allwinner_tina/libcpu/rt_low_level_init.c @@ -1,21 +1,7 @@ /* - * File : rt_low_level_init.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/allwinner_tina/libcpu/stack.c b/bsp/allwinner_tina/libcpu/stack.c index 8f4c218ee1..69e50a9b47 100644 --- a/bsp/allwinner_tina/libcpu/stack.c +++ b/bsp/allwinner_tina/libcpu/stack.c @@ -1,21 +1,7 @@ /* - * File : stack.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/allwinner_tina/libcpu/trap.c b/bsp/allwinner_tina/libcpu/trap.c index 84bb3e7f8a..daf3501c68 100644 --- a/bsp/allwinner_tina/libcpu/trap.c +++ b/bsp/allwinner_tina/libcpu/trap.c @@ -1,21 +1,7 @@ /* - * File : trap.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/amebaz/applications/main.c b/bsp/amebaz/applications/main.c index 381b026867..5cbf749d76 100644 --- a/bsp/amebaz/applications/main.c +++ b/bsp/amebaz/applications/main.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/amebaz/applications/smartconfig_app.c b/bsp/amebaz/applications/smartconfig_app.c index 582bbf5d98..e91f940f1b 100644 --- a/bsp/amebaz/applications/smartconfig_app.c +++ b/bsp/amebaz/applications/smartconfig_app.c @@ -1,21 +1,7 @@ /* - * File : smartconfig_demo.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/amebaz/drivers/board.c b/bsp/amebaz/drivers/board.c index ffdc9fc680..7631bd13d6 100644 --- a/bsp/amebaz/drivers/board.c +++ b/bsp/amebaz/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -44,7 +40,7 @@ void __wrap_rtl_printf(const char *fmt, ...) * length. */ length = rt_vsnprintf(rt_log_buf, sizeof(rt_log_buf) - 1, fmt, args); if (length > RT_CONSOLEBUF_SIZE - 1) - length = RT_CONSOLEBUF_SIZE - 1; + length = RT_CONSOLEBUF_SIZE - 1; rt_kprintf("%s", rt_log_buf); va_end(args); } @@ -89,11 +85,11 @@ void rt_hw_board_init(void) #ifdef RT_USING_HEAP rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END); #endif - + #ifdef RT_USING_COMPONENTS_INIT rt_components_board_init(); #endif - + #ifdef RT_USING_CONSOLE rt_hw_uart_init(); rt_console_set_device(RT_CONSOLE_DEVICE_NAME); diff --git a/bsp/amebaz/drivers/board.h b/bsp/amebaz/drivers/board.h index 3baf67a4d5..5c6b8104ed 100644 --- a/bsp/amebaz/drivers/board.h +++ b/bsp/amebaz/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/amebaz/drivers/drv_uart.c b/bsp/amebaz/drivers/drv_uart.c index 1bf659e79f..008fa3bda5 100644 --- a/bsp/amebaz/drivers/drv_uart.c +++ b/bsp/amebaz/drivers/drv_uart.c @@ -1,21 +1,7 @@ /* - * File : drv_uart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -125,7 +111,7 @@ static int ameba_uart_getc (struct rt_serial_device *serial) { struct device_uart* uart = serial->parent.user_data; - if(!serial_readable(&uart->serial)) + if(!serial_readable(&uart->serial)) return -1; /* Receive Data Available */ @@ -140,13 +126,13 @@ static rt_size_t ameba_uart_dma_transmit (struct rt_serial_device *serial, rt_ui static void ameba_uart_irq(uint32_t id, SerialIrq event) { struct rt_serial_device *serial = (struct rt_serial_device *)id; - if(event == RxIrq) + if(event == RxIrq) { rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); - } - else if(event == TxIrq) + } + else if(event == TxIrq) { - } + } } static rt_err_t dbg_configure(struct rt_serial_device *serial, struct serial_configure *cfg); @@ -155,7 +141,7 @@ static int dbg_putc(struct rt_serial_device *serial, char c); static int dbg_getc(struct rt_serial_device *serial); static struct rt_serial_device ameba_dbg_serial; -const struct rt_uart_ops _ambed_dbg_ops = +const struct rt_uart_ops _ambed_dbg_ops = { dbg_configure, dbg_control, @@ -177,7 +163,7 @@ void dbg_uart_irq_handler(void * data) DiagSetIsrEnReg(0); rt_hw_serial_isr(&ameba_dbg_serial, RT_SERIAL_EVENT_RX_IND); - + DiagSetIsrEnReg(IrqEn); } @@ -192,9 +178,9 @@ static rt_err_t dbg_control(struct rt_serial_device *serial, int cmd, void *arg) case RT_DEVICE_CTRL_SET_INT: /* install interrupt */ - DIAG_UartReInit((IRQ_FUN) dbg_uart_irq_handler); + DIAG_UartReInit((IRQ_FUN) dbg_uart_irq_handler); /* Enable the UART Interrupt */ - NVIC_SetPriority(UART_LOG_IRQ, 10); /* this is rom_code_patch */ + NVIC_SetPriority(UART_LOG_IRQ, 10); /* this is rom_code_patch */ break; } @@ -214,12 +200,12 @@ static int dbg_getc(struct rt_serial_device *serial) if(!UART_Readable(UART2_DEV)) return -1; - + c = DiagGetChar(_FALSE); return c; } - + /* * UART Initiation */ @@ -231,7 +217,7 @@ int rt_hw_uart_init(void) #ifdef BSP_USING_UART0 { struct device_uart *uart; - + serial = &serial0; uart = &uart0; @@ -256,7 +242,7 @@ int rt_hw_uart_init(void) serial->ops = &_ambed_dbg_ops; serial->config = config; - + rt_hw_serial_register(serial, RT_CONSOLE_DEVICE_NAME, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, diff --git a/bsp/amebaz/drivers/drv_uart.h b/bsp/amebaz/drivers/drv_uart.h index a4d326da58..e91cc568b0 100644 --- a/bsp/amebaz/drivers/drv_uart.h +++ b/bsp/amebaz/drivers/drv_uart.h @@ -1,21 +1,7 @@ /* - * File : drv_uart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/amebaz/drivers/wlan/drv_wifi.c b/bsp/amebaz/drivers/wlan/drv_wifi.c index 12865bfc3b..7d8cade15e 100644 --- a/bsp/amebaz/drivers/wlan/drv_wifi.c +++ b/bsp/amebaz/drivers/wlan/drv_wifi.c @@ -1,21 +1,7 @@ /* - * File : drv_wifi.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -115,7 +101,7 @@ void netif_pre_sleep_processing(void) } unsigned char *rltk_wlan_get_ip(int idx) -{ +{ struct ameba_wifi *wifi; wifi = rthw_wifi_get_dev(idx); @@ -130,7 +116,7 @@ unsigned char *rltk_wlan_get_ip(int idx) int netif_is_valid_IP(int idx, unsigned char *ip_dest) { - LOG_D("F:%s L:%d is run ip: %d:%d:%d:%d", __FUNCTION__, __LINE__, + LOG_D("F:%s L:%d is run ip: %d:%d:%d:%d", __FUNCTION__, __LINE__, ip_dest[0], ip_dest[1], ip_dest[2], ip_dest[3]); return 1; } @@ -376,9 +362,9 @@ static rt_err_t rthw_wlan_join (struct rt_wlan_device *wlan, str ssid = &sta_info->ssid.val[0]; if (sta_info->key.len > 0) key = &sta_info->key.val[0]; - LOG_D("bssid connect bssid: %02x:%02x:%02x:%02x:%02x:%02x ssid:%s ssid_len:%d key:%s key_len%d", + LOG_D("bssid connect bssid: %02x:%02x:%02x:%02x:%02x:%02x ssid:%s ssid_len:%d key:%s key_len%d", sta_info->bssid[0],sta_info->bssid[1],sta_info->bssid[2],sta_info->bssid[3],sta_info->bssid[4],sta_info->bssid[5], - ssid, + ssid, sta_info->ssid.len, key, sta_info->key.len @@ -608,7 +594,7 @@ exit: return RT_EOK; } -static const struct rt_wlan_dev_ops ops = +static const struct rt_wlan_dev_ops ops = { .wlan_init = rthw_wlan_init , .wlan_mode = rthw_wlan_mode , diff --git a/bsp/amebaz/drivers/wlan/drv_wifi.h b/bsp/amebaz/drivers/wlan/drv_wifi.h index b92658d470..2ca7c799c8 100644 --- a/bsp/amebaz/drivers/wlan/drv_wifi.h +++ b/bsp/amebaz/drivers/wlan/drv_wifi.h @@ -1,27 +1,13 @@ /* - * File : drv_wifi.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2017-5-30 Bernard the first version */ - + #ifndef __DRV_WIFI_H__ #define __DRV_WIFI_H__ diff --git a/bsp/amebaz/drivers/wlan/drv_wlan.c b/bsp/amebaz/drivers/wlan/drv_wlan.c index c414470633..1eedea54c0 100644 --- a/bsp/amebaz/drivers/wlan/drv_wlan.c +++ b/bsp/amebaz/drivers/wlan/drv_wlan.c @@ -1,21 +1,7 @@ /* - * File : drv_wlan.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -151,20 +137,20 @@ int rthw_wifi_ap_start(char *ssid, char *password, int channel) return -1; } - while(1) + while(1) { char essid[33]; if(wext_get_ssid(name, (unsigned char *) essid) > 0) { - if(strcmp((const char *) essid, (const char *)ssid) == 0) + if(strcmp((const char *) essid, (const char *)ssid) == 0) { rt_kprintf("%s started\n", ssid); break; } } - if(timeout == 0) + if(timeout == 0) { - rt_kprintf("Start AP timeout\n"); + rt_kprintf("Start AP timeout\n"); return -1; } rt_thread_delay(1 * RT_TICK_PER_SECOND); @@ -183,7 +169,7 @@ static int rthw_wifi_disconnect(char *name) if (name == RT_NULL) return -1; - if (wext_get_ssid(name, (unsigned char *) essid) < 0) + if (wext_get_ssid(name, (unsigned char *) essid) < 0) { rt_kprintf("\nWIFI disconnected!\n"); return -1; @@ -203,7 +189,7 @@ static int rthw_wifi_disconnect(char *name) break; } - if(timeout == 0) + if(timeout == 0) { rt_kprintf("ERROR: Deassoc timeout!\n"); return -1; @@ -259,7 +245,7 @@ int rthw_wifi_ap_disconnect(void) int rthw_wifi_rssi_get(void) { - int rssi = 0; + int rssi = 0; wifi_get_rssi(&rssi); return rssi; } diff --git a/bsp/amebaz/drivers/wlan/drv_wlan.h b/bsp/amebaz/drivers/wlan/drv_wlan.h index 03a8db01e8..ad300b18eb 100644 --- a/bsp/amebaz/drivers/wlan/drv_wlan.h +++ b/bsp/amebaz/drivers/wlan/drv_wlan.h @@ -1,21 +1,7 @@ /* - * File : drv_wlan.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -25,14 +11,14 @@ #ifndef __DRV_WLAN_H__ #define __DRV_WLAN_H__ -typedef enum +typedef enum { - RTHW_MODE_NONE = 0, - RTHW_MODE_STA, - RTHW_MODE_AP, - RTHW_MODE_STA_AP, - RTHW_MODE_PROMISC, - RTHW_MODE_P2P + RTHW_MODE_NONE = 0, + RTHW_MODE_STA, + RTHW_MODE_AP, + RTHW_MODE_STA_AP, + RTHW_MODE_PROMISC, + RTHW_MODE_P2P }rthw_mode_t; #define SHARED_ENABLED 0x00008000 @@ -66,7 +52,7 @@ typedef enum { typedef enum { RTHW_WIFI_EVENT_CONNECT = 0, RTHW_WIFI_EVENT_DISCONNECT = 1, - RTHW_WIFI_EVENT_FOURWAY_HANDSHAKE_DONE = 2, + RTHW_WIFI_EVENT_FOURWAY_HANDSHAKE_DONE = 2, RTHW_WIFI_EVENT_SCAN_RESULT_REPORT = 3, RTHW_WIFI_EVENT_SCAN_DONE = 4, RTHW_WIFI_EVENT_RECONNECTION_FAIL = 5, diff --git a/bsp/amebaz/libraries/smartconfig/inc/smartconfig.h b/bsp/amebaz/libraries/smartconfig/inc/smartconfig.h index b215e983c4..214c46f50f 100644 --- a/bsp/amebaz/libraries/smartconfig/inc/smartconfig.h +++ b/bsp/amebaz/libraries/smartconfig/inc/smartconfig.h @@ -1,21 +1,7 @@ /* - * File : smartconfig.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/apollo2/applications/main.c b/bsp/apollo2/applications/main.c index b058fc7711..4761cae664 100644 --- a/bsp/apollo2/applications/main.c +++ b/bsp/apollo2/applications/main.c @@ -1,21 +1,7 @@ /* - * File : main.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/apollo2/board/adc.c b/bsp/apollo2/board/adc.c index a0044bcc37..26b926a209 100644 --- a/bsp/apollo2/board/adc.c +++ b/bsp/apollo2/board/adc.c @@ -1,21 +1,7 @@ /* - * File : adc.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -32,15 +18,15 @@ struct rt_messagequeue adcbat_mq; #define BATTERY_GPIO 35 /* Battery */ -#define BATTERY_ADC_PIN AM_HAL_PIN_35_ADCSE7 -#define BATTERY_ADC_CHANNEL AM_HAL_ADC_SLOT_CHSEL_SE7 /* BATTERY ADCɼͨ */ -#define BATTERY_ADC_CHANNELNUM 7 /* BATTERY ADCɼͨ */ +#define BATTERY_ADC_PIN AM_HAL_PIN_35_ADCSE7 +#define BATTERY_ADC_CHANNEL AM_HAL_ADC_SLOT_CHSEL_SE7 /* BATTERY ADC采集通道 */ +#define BATTERY_ADC_CHANNELNUM 7 /* BATTERY ADC采集通道号 */ -#define ADC_CTIMER_NUM 3 /* ADCʹöʱ */ +#define ADC_CTIMER_NUM 3 /* ADC使用定时器 */ #define ADC_CTIMER_COUNT (2048/512 - 1) -#define ADC_CHANNEL_NUM 1 /* ADCɼͨ */ -#define ADC_SAMPLE_NUM 8 /* ADC */ +#define ADC_CHANNEL_NUM 1 /* ADC采集通道个数 */ +#define ADC_SAMPLE_NUM 8 /* ADC采样个数 */ rt_uint8_t bat_adc_cnt = 0; static rt_uint8_t am_adcbat_buffer_pool[256]; @@ -52,7 +38,7 @@ rt_uint8_t am_adc_data_get(rt_uint8_t channel, rt_int16_t *buff, rt_uint16_t siz if (channel == BATTERY_ADC_CHANNELNUM) { - /* wait adc message forever */ + /* wait adc message forever */ rt_mq_recv(&adcbat_mq, adc_bufftemp, 32, RT_WAITING_FOREVER); } diff --git a/bsp/apollo2/board/adc.h b/bsp/apollo2/board/adc.h index 4e4396bae3..552b704ab8 100644 --- a/bsp/apollo2/board/adc.h +++ b/bsp/apollo2/board/adc.h @@ -1,21 +1,7 @@ /* - * File : adc.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/apollo2/board/board.c b/bsp/apollo2/board/board.c index 23bc332af4..907455a998 100644 --- a/bsp/apollo2/board/board.c +++ b/bsp/apollo2/board/board.c @@ -1,21 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/apollo2/board/board.h b/bsp/apollo2/board/board.h index 67dfdd5e39..ef21bdb05f 100644 --- a/bsp/apollo2/board/board.h +++ b/bsp/apollo2/board/board.h @@ -1,21 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/apollo2/board/flash.c b/bsp/apollo2/board/flash.c index ae224e85a1..2d28920daf 100644 --- a/bsp/apollo2/board/flash.c +++ b/bsp/apollo2/board/flash.c @@ -1,21 +1,7 @@ /* - * File : flash.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -77,7 +63,7 @@ static rt_err_t rt_flash_control(rt_device_t dev, int cmd, void *args) ui32CurrentPage = AM_HAL_FLASH_ADDR2PAGE(erase->addrstart); ui32CurrentBlock = AM_HAL_FLASH_ADDR2INST(erase->addrstart); - am_hal_flash_page_erase(AM_HAL_FLASH_PROGRAM_KEY, ui32CurrentBlock, ui32CurrentPage); // + am_hal_flash_page_erase(AM_HAL_FLASH_PROGRAM_KEY, ui32CurrentBlock, ui32CurrentPage); //单扇区擦除命令 erase->addrstart += 8192; } } diff --git a/bsp/apollo2/board/flash.h b/bsp/apollo2/board/flash.h index c9c8f9492c..b628983ce3 100644 --- a/bsp/apollo2/board/flash.h +++ b/bsp/apollo2/board/flash.h @@ -1,21 +1,7 @@ /* - * File : flash.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/apollo2/board/gpio.c b/bsp/apollo2/board/gpio.c index c985e0f2a7..edfaef1431 100644 --- a/bsp/apollo2/board/gpio.c +++ b/bsp/apollo2/board/gpio.c @@ -1,21 +1,7 @@ /* - * File : gpio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -70,7 +56,7 @@ void am_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) else if (value == PIN_HIGH) { am_hal_gpio_out_bit_set(pin); - } + } } int am_pin_read(rt_device_t dev, rt_base_t pin) diff --git a/bsp/apollo2/board/gpio.h b/bsp/apollo2/board/gpio.h index 1ea3c42013..495fde6f6e 100644 --- a/bsp/apollo2/board/gpio.h +++ b/bsp/apollo2/board/gpio.h @@ -1,27 +1,13 @@ /* - * File : gpio.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2017-09-16 Haley the first version */ - + #ifndef __GPIO_H #define __GPIO_H diff --git a/bsp/apollo2/board/i2c.c b/bsp/apollo2/board/i2c.c index 6d1bcdc0c0..0a1311d7e6 100644 --- a/bsp/apollo2/board/i2c.c +++ b/bsp/apollo2/board/i2c.c @@ -1,21 +1,7 @@ /* - * File :_i2c.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -133,7 +119,7 @@ static const struct rt_i2c_bus_device_ops am_i2c_ops = }; #ifdef RT_USING_I2C0 -static struct am_i2c_bus am_i2c_bus_0 = +static struct am_i2c_bus am_i2c_bus_0 = { {0}, AM_I2C0_IOM_INST @@ -141,7 +127,7 @@ static struct am_i2c_bus am_i2c_bus_0 = #endif #ifdef RT_USING_I2C1 -static struct am_i2c_bus am_i2c_bus_1 = +static struct am_i2c_bus am_i2c_bus_1 = { {1}, AM_I2C1_IOM_INST @@ -149,7 +135,7 @@ static struct am_i2c_bus am_i2c_bus_1 = #endif #ifdef RT_USING_I2C2 -static struct am_i2c_bus am_i2c_bus_2 = +static struct am_i2c_bus am_i2c_bus_2 = { {2}, AM_I2C2_IOM_INST @@ -157,7 +143,7 @@ static struct am_i2c_bus am_i2c_bus_2 = #endif #ifdef RT_USING_I2C3 -static struct am_i2c_bus am_i2c_bus_3 = +static struct am_i2c_bus am_i2c_bus_3 = { {3}, AM_I2C3_IOM_INST @@ -165,7 +151,7 @@ static struct am_i2c_bus am_i2c_bus_3 = #endif #ifdef RT_USING_I2C4 -static struct am_i2c_bus am_i2c_bus_4 = +static struct am_i2c_bus am_i2c_bus_4 = { {4}, AM_I2C4_IOM_INST diff --git a/bsp/apollo2/board/i2c.h b/bsp/apollo2/board/i2c.h index 004d5eb3c1..b0a24b51cd 100644 --- a/bsp/apollo2/board/i2c.h +++ b/bsp/apollo2/board/i2c.h @@ -1,21 +1,7 @@ /* - * File : i2c.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/apollo2/board/led.c b/bsp/apollo2/board/led.c index d8eb2fb753..5364667679 100644 --- a/bsp/apollo2/board/led.c +++ b/bsp/apollo2/board/led.c @@ -1,21 +1,7 @@ /* - * File :_led.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/apollo2/board/led.h b/bsp/apollo2/board/led.h index c6f6bd8728..76832e32b9 100644 --- a/bsp/apollo2/board/led.h +++ b/bsp/apollo2/board/led.h @@ -1,21 +1,7 @@ /* - * File : led.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/apollo2/board/pdm.c b/bsp/apollo2/board/pdm.c index 3eb46f7411..f1b719c6d1 100644 --- a/bsp/apollo2/board/pdm.c +++ b/bsp/apollo2/board/pdm.c @@ -1,21 +1,7 @@ /* - * File :_pdm.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -66,7 +52,7 @@ rt_uint8_t am_pdm_data_get(rt_uint8_t *buff, rt_uint16_t size) { rt_uint8_t pdm_rbufftemp[340]; - /* wait pdm message forever */ + /* wait pdm message forever */ rt_mq_recv(&pdm_mq, pdm_rbufftemp, 340, RT_WAITING_FOREVER); /* copy the data */ diff --git a/bsp/apollo2/board/pdm.h b/bsp/apollo2/board/pdm.h index 43ed075da8..2975c8aad1 100644 --- a/bsp/apollo2/board/pdm.h +++ b/bsp/apollo2/board/pdm.h @@ -1,21 +1,7 @@ /* - * File : pdm.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/apollo2/board/pwm.c b/bsp/apollo2/board/pwm.c index 7591291eac..8b23a8c290 100644 --- a/bsp/apollo2/board/pwm.c +++ b/bsp/apollo2/board/pwm.c @@ -1,21 +1,7 @@ /* - * File :_pwm.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/apollo2/board/pwm.h b/bsp/apollo2/board/pwm.h index 53a6571264..973848c6f6 100644 --- a/bsp/apollo2/board/pwm.h +++ b/bsp/apollo2/board/pwm.h @@ -1,21 +1,7 @@ /* - * File : pwm.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/apollo2/board/rtc.c b/bsp/apollo2/board/rtc.c index dbae7cf3c1..5c8fbb13fe 100644 --- a/bsp/apollo2/board/rtc.c +++ b/bsp/apollo2/board/rtc.c @@ -1,21 +1,7 @@ /* - * File :_rtc.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -116,7 +102,7 @@ int rt_hw_rtc_init(void) /* Select LFRC for RTC clock source */ am_hal_rtc_osc_select(AM_HAL_RTC_OSC_LFRC); #endif - + #if RTC_CLK_SRC == XT /* Enable the XT for the RTC */ am_hal_clkgen_osc_start(AM_HAL_CLKGEN_OSC_XT); @@ -129,12 +115,12 @@ int rt_hw_rtc_init(void) am_hal_rtc_osc_enable(); /* register rtc device */ - rtc.type = RT_Device_Class_RTC; - rtc.init = RT_NULL; - rtc.open = rt_rtc_open; - rtc.close = RT_NULL; - rtc.read = rt_rtc_read; - rtc.write = RT_NULL; + rtc.type = RT_Device_Class_RTC; + rtc.init = RT_NULL; + rtc.open = rt_rtc_open; + rtc.close = RT_NULL; + rtc.read = rt_rtc_read; + rtc.write = RT_NULL; rtc.control = rt_rtc_control; /* no private */ diff --git a/bsp/apollo2/board/rtc.h b/bsp/apollo2/board/rtc.h index 83087bc47e..a4a7fbd5e7 100644 --- a/bsp/apollo2/board/rtc.h +++ b/bsp/apollo2/board/rtc.h @@ -1,27 +1,13 @@ /* - * File : rtc.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2017-09-14 Haley the first version */ - + #ifndef __RTC_H #define __RTC_H diff --git a/bsp/apollo2/board/smbus.c b/bsp/apollo2/board/smbus.c index ae41f9fac6..7437b68ffa 100644 --- a/bsp/apollo2/board/smbus.c +++ b/bsp/apollo2/board/smbus.c @@ -1,21 +1,7 @@ /* - * File : smbus.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -42,8 +28,8 @@ #define mSDA_OUT() am_hal_gpio_pin_config(SMBUS_GPIO_SDA, AM_HAL_GPIO_OUTPUT) /* Set SDA as Output */ #define mSCL_OUT() am_hal_gpio_pin_config(SMBUS_GPIO_SCL, AM_HAL_GPIO_OUTPUT) /* Set SCL as Output */ -#define ACK 0 -#define NACK 1 +#define ACK 0 +#define NACK 1 /* SCL keep time */ static void keep_delay(void) @@ -60,7 +46,7 @@ static void few_delay(void) } static rt_uint8_t am_smbus_send_bit(rt_uint8_t send_bit) -{ +{ mSDA_OUT(); few_delay(); @@ -128,7 +114,7 @@ static void am_smbus_stop_bit(void) static rt_uint8_t am_smbus_tx_byte(rt_uint8_t tx_byte) { - int i; + int i; rt_uint8_t ack_bit; rt_uint8_t bit_out; @@ -176,7 +162,7 @@ rt_uint8_t am_smbus_tx_then_tx(rt_uint8_t SlaveAddress, rt_uint8_t command, rt_u int i; am_smbus_start_bit(); /* Start condition */ - + if(am_smbus_tx_byte(SlaveAddress)) /* Send SlaveAddress and write */ return 1; diff --git a/bsp/apollo2/board/smbus.h b/bsp/apollo2/board/smbus.h index 6f518b8f9e..62f8afc1b9 100644 --- a/bsp/apollo2/board/smbus.h +++ b/bsp/apollo2/board/smbus.h @@ -1,21 +1,7 @@ /* - * File : smbus.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/apollo2/board/spi.c b/bsp/apollo2/board/spi.c index 783f359af0..f59610975f 100644 --- a/bsp/apollo2/board/spi.c +++ b/bsp/apollo2/board/spi.c @@ -1,21 +1,7 @@ /* - * File : spi.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -180,7 +166,7 @@ static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message* mes am_hal_gpio_out_bit_clear(am_spi_cs->chip_select); } - // + // 读数据 if (recv_ptr != RT_NULL) { while (u32BytesRemaining) @@ -213,7 +199,7 @@ static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message* mes } } - // д + // 写数据 else { while (u32BytesRemaining) @@ -225,7 +211,7 @@ static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message* mes u32TransferSize = 64; am_hal_iom_spi_write(am_spi_bus->u32Module, am_spi_cs->chip_select, (uint32_t *)send_ptr, u32TransferSize, AM_HAL_IOM_RAW); - + } else { @@ -257,7 +243,7 @@ static const struct rt_spi_ops am_spi_ops = }; #ifdef RT_USING_SPI0 -static struct am_spi_bus am_spi_bus_0 = +static struct am_spi_bus am_spi_bus_0 = { {0}, AM_SPI0_IOM_INST diff --git a/bsp/apollo2/board/spi.h b/bsp/apollo2/board/spi.h index d88bb587e9..4c23f54621 100644 --- a/bsp/apollo2/board/spi.h +++ b/bsp/apollo2/board/spi.h @@ -1,21 +1,7 @@ /* - * File : spi.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -27,7 +13,7 @@ #include -/* ƬѡźŽṹ */ +/* 片选信号结构声明 */ struct am_spi_cs { rt_uint32_t chip_select; diff --git a/bsp/apollo2/board/uart.c b/bsp/apollo2/board/uart.c index fc3884bf2d..ec97599b80 100644 --- a/bsp/apollo2/board/uart.c +++ b/bsp/apollo2/board/uart.c @@ -1,21 +1,7 @@ /* - * File : uart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -164,11 +150,11 @@ static rt_err_t am_configure(struct rt_serial_device *serial, struct serial_conf else if (cfg->stop_bits == STOP_BITS_2) uart_cfg.bTwoStopBits = true; - if (cfg->parity == PARITY_NONE) + if (cfg->parity == PARITY_NONE) uart_cfg.ui32Parity = AM_HAL_UART_PARITY_NONE; - else if (cfg->parity == PARITY_ODD) + else if (cfg->parity == PARITY_ODD) uart_cfg.ui32Parity = AM_HAL_UART_PARITY_ODD; - else if (cfg->parity == PARITY_EVEN) + else if (cfg->parity == PARITY_EVEN) uart_cfg.ui32Parity = AM_HAL_UART_PARITY_EVEN; uart_cfg.ui32FlowCtrl = AM_HAL_UART_FLOW_CTRL_NONE; diff --git a/bsp/apollo2/board/uart.h b/bsp/apollo2/board/uart.h index 8e92068d5d..d858d68b21 100644 --- a/bsp/apollo2/board/uart.h +++ b/bsp/apollo2/board/uart.h @@ -1,21 +1,7 @@ /* - * File : uart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/asm9260t/applications/application.c b/bsp/asm9260t/applications/application.c index 18a9fbdf23..d60546ca76 100644 --- a/bsp/asm9260t/applications/application.c +++ b/bsp/asm9260t/applications/application.c @@ -1,25 +1,11 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version * 2015-04-27 ArdaFu Port bsp from at91sam9260 to asm9260t */ diff --git a/bsp/asm9260t/drivers/board.c b/bsp/asm9260t/drivers/board.c index f3fc53c51a..652be94767 100644 --- a/bsp/asm9260t/drivers/board.c +++ b/bsp/asm9260t/drivers/board.c @@ -1,21 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/asm9260t/drivers/board.h b/bsp/asm9260t/drivers/board.h index 0af63a9480..9682b68326 100644 --- a/bsp/asm9260t/drivers/board.h +++ b/bsp/asm9260t/drivers/board.h @@ -1,21 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/asm9260t/drivers/led.c b/bsp/asm9260t/drivers/led.c index e2d6d7a79d..80fd98fd07 100644 --- a/bsp/asm9260t/drivers/led.c +++ b/bsp/asm9260t/drivers/led.c @@ -1,21 +1,7 @@ /* - * File : led.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2015, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/asm9260t/drivers/led.h b/bsp/asm9260t/drivers/led.h index f2967bc92d..9836eff709 100644 --- a/bsp/asm9260t/drivers/led.h +++ b/bsp/asm9260t/drivers/led.h @@ -1,21 +1,7 @@ /* - * File : led.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/asm9260t/drivers/usart.c b/bsp/asm9260t/drivers/usart.c index 617e526afc..3a17f97b38 100644 --- a/bsp/asm9260t/drivers/usart.c +++ b/bsp/asm9260t/drivers/usart.c @@ -1,21 +1,7 @@ /* - * File : usart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -72,12 +58,12 @@ static rt_err_t asm_usart_configure(struct rt_serial_device *serial, RT_ASSERT(serial != RT_NULL); RT_ASSERT(cfg != RT_NULL); uart = (asm_uart_t *)serial->parent.user_data; - + Hw_UartDisable(uart->port); Hw_UartReset(uart->port); - - Hw_UartConfig(uart->port, cfg->baud_rate, cfg->data_bits, + + Hw_UartConfig(uart->port, cfg->baud_rate, cfg->data_bits, cfg->stop_bits, cfg->parity); Hw_UartEnable(uart->port); diff --git a/bsp/asm9260t/platform/gpio.c b/bsp/asm9260t/platform/gpio.c index 2a341dcdf5..8361a59589 100644 --- a/bsp/asm9260t/platform/gpio.c +++ b/bsp/asm9260t/platform/gpio.c @@ -1,27 +1,13 @@ /* - * File : interrupt.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2015-04-14 ArdaFu first version */ - + #include "asm9260t.h" #include "rtthread.h" diff --git a/bsp/asm9260t/platform/gpio.h b/bsp/asm9260t/platform/gpio.h index 26fccff477..f5480bb4e9 100644 --- a/bsp/asm9260t/platform/gpio.h +++ b/bsp/asm9260t/platform/gpio.h @@ -1,21 +1,7 @@ /* - * File : interrupt.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/asm9260t/platform/interrupt.c b/bsp/asm9260t/platform/interrupt.c index 6121203c23..76b18bc7a0 100644 --- a/bsp/asm9260t/platform/interrupt.c +++ b/bsp/asm9260t/platform/interrupt.c @@ -1,21 +1,7 @@ /* - * File : interrupt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/asm9260t/platform/interrupt.h b/bsp/asm9260t/platform/interrupt.h index 85aa48f371..fba92d1f2c 100644 --- a/bsp/asm9260t/platform/interrupt.h +++ b/bsp/asm9260t/platform/interrupt.h @@ -1,21 +1,7 @@ /* - * File : interrupt.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -29,69 +15,69 @@ // IRQ Source -#define INT_ARM_COMMRX 0 -#define INT_ARM_COMMTX 1 -#define INT_RTC 2 -#define INT_GPIO0 3 -#define INT_GPIO1 4 -#define INT_GPIO2 5 -#define INT_GPIO3 6 -#define INT_GPIO4_IIS1 7 -#define INT_USB0 8 -#define INT_USB1 9 -#define INT_USB0_DMA 10 -#define INT_USB1_DMA 11 -#define INT_MAC 12 -#define INT_MAC_PMT 13 -#define INT_NAND 14 -#define INT_UART0 15 -#define INT_UART1 16 -#define INT_UART2 17 -#define INT_UART3 18 -#define INT_UART4 19 -#define INT_UART5 20 -#define INT_UART6 21 -#define INT_UART7 22 -#define INT_UART8 23 -#define INT_UART9 24 -#define INT_I2S0 25 -#define INT_I2C0 26 -#define INT_I2C1 27 -#define INT_CAMIF 28 -#define INT_TIMER0 29 -#define INT_TIMER1 30 -#define INT_TIMER2 31 -#define INT_TIMER3 32 -#define INT_ADC0 33 -#define INT_DAC0 34 -#define INT_USB0_RESUME_HOSTDISCONNECT 35 -#define INT_USB0_VBUSVALID 36 -#define INT_USB1_RESUME_HOSTDISCONNECT 37 -#define INT_USB1_VBUSVALID 38 -#define INT_DMA0_CH0 39 -#define INT_DMA0_CH1 40 -#define INT_DMA0_CH2 41 -#define INT_DMA0_CH3 42 -#define INT_DMA0_CH4 43 -#define INT_DMA0_CH5 44 -#define INT_DMA0_CH6 45 -#define INT_DMA0_CH7 46 -#define INT_DMA1_CH0 47 -#define INT_DMA1_CH1 48 -#define INT_DMA1_CH2 49 -#define INT_DMA1_CH3 50 -#define INT_DMA1_CH4 51 -#define INT_DMA1_CH5 52 -#define INT_DMA1_CH6 53 -#define INT_DMA1_CH7 54 -#define INT_WATCHDOG 55 -#define INT_CAN0 56 -#define INT_CAN1 57 -#define INT_QEI 58 -#define INT_MCPWM 59 -#define INT_SPI0 60 -#define INT_SPI1 61 -#define INT_QUADSPI0 62 +#define INT_ARM_COMMRX 0 +#define INT_ARM_COMMTX 1 +#define INT_RTC 2 +#define INT_GPIO0 3 +#define INT_GPIO1 4 +#define INT_GPIO2 5 +#define INT_GPIO3 6 +#define INT_GPIO4_IIS1 7 +#define INT_USB0 8 +#define INT_USB1 9 +#define INT_USB0_DMA 10 +#define INT_USB1_DMA 11 +#define INT_MAC 12 +#define INT_MAC_PMT 13 +#define INT_NAND 14 +#define INT_UART0 15 +#define INT_UART1 16 +#define INT_UART2 17 +#define INT_UART3 18 +#define INT_UART4 19 +#define INT_UART5 20 +#define INT_UART6 21 +#define INT_UART7 22 +#define INT_UART8 23 +#define INT_UART9 24 +#define INT_I2S0 25 +#define INT_I2C0 26 +#define INT_I2C1 27 +#define INT_CAMIF 28 +#define INT_TIMER0 29 +#define INT_TIMER1 30 +#define INT_TIMER2 31 +#define INT_TIMER3 32 +#define INT_ADC0 33 +#define INT_DAC0 34 +#define INT_USB0_RESUME_HOSTDISCONNECT 35 +#define INT_USB0_VBUSVALID 36 +#define INT_USB1_RESUME_HOSTDISCONNECT 37 +#define INT_USB1_VBUSVALID 38 +#define INT_DMA0_CH0 39 +#define INT_DMA0_CH1 40 +#define INT_DMA0_CH2 41 +#define INT_DMA0_CH3 42 +#define INT_DMA0_CH4 43 +#define INT_DMA0_CH5 44 +#define INT_DMA0_CH6 45 +#define INT_DMA0_CH7 46 +#define INT_DMA1_CH0 47 +#define INT_DMA1_CH1 48 +#define INT_DMA1_CH2 49 +#define INT_DMA1_CH3 50 +#define INT_DMA1_CH4 51 +#define INT_DMA1_CH5 52 +#define INT_DMA1_CH6 53 +#define INT_DMA1_CH7 54 +#define INT_WATCHDOG 55 +#define INT_CAN0 56 +#define INT_CAN1 57 +#define INT_QEI 58 +#define INT_MCPWM 59 +#define INT_SPI0 60 +#define INT_SPI1 61 +#define INT_QUADSPI0 62 #define INT_SSP0 63 #endif diff --git a/bsp/asm9260t/platform/reset.c b/bsp/asm9260t/platform/reset.c index 2f5adc6231..e2611af4a3 100644 --- a/bsp/asm9260t/platform/reset.c +++ b/bsp/asm9260t/platform/reset.c @@ -1,21 +1,7 @@ /* - * File : reset.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2015, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/asm9260t/platform/rt_low_level_init.c b/bsp/asm9260t/platform/rt_low_level_init.c index 926c1af6fa..822f8ac733 100644 --- a/bsp/asm9260t/platform/rt_low_level_init.c +++ b/bsp/asm9260t/platform/rt_low_level_init.c @@ -1,21 +1,7 @@ /* - * File : rt_low_level_init.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/asm9260t/platform/rt_low_level_init.h b/bsp/asm9260t/platform/rt_low_level_init.h index 86dcfb59dc..c79adf5284 100644 --- a/bsp/asm9260t/platform/rt_low_level_init.h +++ b/bsp/asm9260t/platform/rt_low_level_init.h @@ -1,21 +1,7 @@ /* - * File : rt_low_level_init.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -23,7 +9,7 @@ */ #ifndef __RT_LOW_LEVEL_INIT_H__ #define __RT_LOW_LEVEL_INIT_H__ - + /*-------- Stack size of CPU modes -------------------------------------------*/ #define UND_STK_SIZE 512 #define SVC_STK_SIZE 4096 diff --git a/bsp/asm9260t/platform/system_clock.c b/bsp/asm9260t/platform/system_clock.c index e51cf7c892..3a3340f48d 100644 --- a/bsp/asm9260t/platform/system_clock.c +++ b/bsp/asm9260t/platform/system_clock.c @@ -1,21 +1,7 @@ /* - * File : clock.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -28,269 +14,269 @@ static rt_list_t clocks; struct clk { - char name[32]; - rt_uint32_t rate_hz; - struct clk *parent; - rt_list_t node; + char name[32]; + rt_uint32_t rate_hz; + struct clk *parent; + rt_list_t node; }; static struct clk clk32k = { - "clk32k", - AT91_SLOW_CLOCK, - RT_NULL, - {RT_NULL, RT_NULL}, + "clk32k", + AT91_SLOW_CLOCK, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk main_clk = { - "main", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, + "main", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk plla = { - "plla", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, + "plla", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk mck = { - "mck", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, + "mck", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk uhpck = { - "uhpck", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, + "uhpck", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk pllb = { - "pllb", - 0, - &main_clk, - {RT_NULL, RT_NULL}, + "pllb", + 0, + &main_clk, + {RT_NULL, RT_NULL}, }; static struct clk udpck = { - "udpck", - 0, - &pllb, - {RT_NULL, RT_NULL}, + "udpck", + 0, + &pllb, + {RT_NULL, RT_NULL}, }; static struct clk *const standard_pmc_clocks[] = { - // four primary clocks - &clk32k, - &main_clk, - &plla, + // four primary clocks + &clk32k, + &main_clk, + &plla, - // MCK - &mck + // MCK + &mck }; // clocks cannot be de-registered no refcounting necessary struct clk *clk_get(const char *id) { - struct clk *clk; - rt_list_t *list; - - for (list = (&clocks)->next; list != &clocks; list = list->next) - { - clk = (struct clk *)rt_list_entry(list, struct clk, node); - if (rt_strcmp(id, clk->name) == 0) - return clk; - } + struct clk *clk; + rt_list_t *list; - return RT_NULL; + for (list = (&clocks)->next; list != &clocks; list = list->next) + { + clk = (struct clk *)rt_list_entry(list, struct clk, node); + if (rt_strcmp(id, clk->name) == 0) + return clk; + } + + return RT_NULL; } rt_uint32_t clk_get_rate(struct clk *clk) { - rt_uint32_t rate; + rt_uint32_t rate; - for (;;) { - rate = clk->rate_hz; - if (rate || !clk->parent) - break; - clk = clk->parent; - } - return rate; + for (;;) { + rate = clk->rate_hz; + if (rate || !clk->parent) + break; + clk = clk->parent; + } + return rate; } static rt_uint32_t at91_pll_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg) { - unsigned mul, div; + unsigned mul, div; - div = reg & 0xff; - mul = (reg >> 16) & 0x7ff; - if (div && mul) { - freq /= div; - freq *= mul + 1; - } else - freq = 0; + div = reg & 0xff; + mul = (reg >> 16) & 0x7ff; + if (div && mul) { + freq /= div; + freq *= mul + 1; + } else + freq = 0; - return freq; + return freq; } static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq) { - unsigned i, div = 0, mul = 0, diff = 1 << 30; - unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; + unsigned i, div = 0, mul = 0, diff = 1 << 30; + unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; - //PLL output max 240 MHz (or 180 MHz per errata) - if (out_freq > 240000000) - goto fail; + //PLL output max 240 MHz (or 180 MHz per errata) + if (out_freq > 240000000) + goto fail; - for (i = 1; i < 256; i++) { - int diff1; - unsigned input, mul1; + for (i = 1; i < 256; i++) { + int diff1; + unsigned input, mul1; - // - // PLL input between 1MHz and 32MHz per spec, but lower - // frequences seem necessary in some cases so allow 100K. - // Warning: some newer products need 2MHz min. - // - input = main_freq / i; - if (input < 100000) - continue; - if (input > 32000000) - continue; + // + // PLL input between 1MHz and 32MHz per spec, but lower + // frequences seem necessary in some cases so allow 100K. + // Warning: some newer products need 2MHz min. + // + input = main_freq / i; + if (input < 100000) + continue; + if (input > 32000000) + continue; - mul1 = out_freq / input; - if (mul1 > 2048) - continue; - if (mul1 < 2) - goto fail; + mul1 = out_freq / input; + if (mul1 > 2048) + continue; + if (mul1 < 2) + goto fail; - diff1 = out_freq - input * mul1; - if (diff1 < 0) - diff1 = -diff1; - if (diff > diff1) { - diff = diff1; - div = i; - mul = mul1; - if (diff == 0) - break; - } - } - if (i == 256 && diff > (out_freq >> 5)) - goto fail; - return ret | ((mul - 1) << 16) | div; + diff1 = out_freq - input * mul1; + if (diff1 < 0) + diff1 = -diff1; + if (diff > diff1) { + diff = diff1; + div = i; + mul = mul1; + if (diff == 0) + break; + } + } + if (i == 256 && diff > (out_freq >> 5)) + goto fail; + return ret | ((mul - 1) << 16) | div; fail: - return 0; + return 0; } static rt_uint32_t at91_usb_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg) { - if (pll == &pllb && (reg & AT91_PMC_USB96M)) - return freq / 2; - else - return freq; + if (pll == &pllb && (reg & AT91_PMC_USB96M)) + return freq / 2; + else + return freq; } // PLLB generated USB full speed clock init static void at91_pllb_usbfs_clock_init(rt_uint32_t main_clock) { - rt_uint32_t at91_pllb_usb_init; - // - // USB clock init: choose 48 MHz PLLB value, - // disable 48MHz clock during usb peripheral suspend. - // - // REVISIT: assumes MCK doesn't derive from PLLB! - // - uhpck.parent = &pllb; + rt_uint32_t at91_pllb_usb_init; + // + // USB clock init: choose 48 MHz PLLB value, + // disable 48MHz clock during usb peripheral suspend. + // + // REVISIT: assumes MCK doesn't derive from PLLB! + // + uhpck.parent = &pllb; - at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; - pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); - - at91_sys_write(AT91_CKGR_PLLBR, 0); + at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; + pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); - udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); - uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); + at91_sys_write(AT91_CKGR_PLLBR, 0); + + udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); + uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); } static struct clk *at91_css_to_clk(unsigned long css) { - switch (css) { - case AT91_PMC_CSS_SLOW: - return &clk32k; - case AT91_PMC_CSS_MAIN: - return &main_clk; - case AT91_PMC_CSS_PLLA: - return &plla; - case AT91_PMC_CSS_PLLB: - return &pllb; - } + switch (css) { + case AT91_PMC_CSS_SLOW: + return &clk32k; + case AT91_PMC_CSS_MAIN: + return &main_clk; + case AT91_PMC_CSS_PLLA: + return &plla; + case AT91_PMC_CSS_PLLB: + return &pllb; + } - return RT_NULL; + return RT_NULL; } #define false 0 #define true 1 int at91_clock_init(rt_uint32_t main_clock) { - unsigned tmp, freq, mckr; - int i; - int pll_overclock = false; + unsigned tmp, freq, mckr; + int i; + int pll_overclock = false; - // - // When the bootloader initialized the main oscillator correctly, - // there's no problem using the cycle counter. But if it didn't, - // or when using oscillator bypass mode, we must be told the speed - // of the main clock. - // - if (!main_clock) { - do { - tmp = at91_sys_read(AT91_CKGR_MCFR); - } while (!(tmp & AT91_PMC_MAINRDY)); - main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); - } - main_clk.rate_hz = main_clock; + // + // When the bootloader initialized the main oscillator correctly, + // there's no problem using the cycle counter. But if it didn't, + // or when using oscillator bypass mode, we must be told the speed + // of the main clock. + // + if (!main_clock) { + do { + tmp = at91_sys_read(AT91_CKGR_MCFR); + } while (!(tmp & AT91_PMC_MAINRDY)); + main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); + } + main_clk.rate_hz = main_clock; - // report if PLLA is more than mildly overclocked - plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); - if (plla.rate_hz > 209000000) - pll_overclock = true; - if (pll_overclock) - ;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); + // report if PLLA is more than mildly overclocked + plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); + if (plla.rate_hz > 209000000) + pll_overclock = true; + if (pll_overclock) + ;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); - at91_pllb_usbfs_clock_init(main_clock); + at91_pllb_usbfs_clock_init(main_clock); - // - // MCK and CPU derive from one of those primary clocks. - // For now, assume this parentage won't change. - // - mckr = at91_sys_read(AT91_PMC_MCKR); - mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); - freq = mck.parent->rate_hz; - freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); // prescale - - mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); // mdiv + // + // MCK and CPU derive from one of those primary clocks. + // For now, assume this parentage won't change. + // + mckr = at91_sys_read(AT91_PMC_MCKR); + mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); + freq = mck.parent->rate_hz; + freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); // prescale - // Register the PMC's standard clocks - rt_list_init(&clocks); - for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) - rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node); + mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); // mdiv - rt_list_insert_after(&clocks, &pllb.node); - rt_list_insert_after(&clocks, &uhpck.node); - rt_list_insert_after(&clocks, &udpck.node); + // Register the PMC's standard clocks + rt_list_init(&clocks); + for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) + rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node); - // MCK and CPU clock are "always on" - //clk_enable(&mck); + rt_list_insert_after(&clocks, &pllb.node); + rt_list_insert_after(&clocks, &uhpck.node); + rt_list_insert_after(&clocks, &udpck.node); - //rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", - // freq / 1000000, (unsigned) mck.rate_hz / 1000000, - // (unsigned) main_clock / 1000000, - // ((unsigned) main_clock % 1000000) / 1000); //cause blocked + // MCK and CPU clock are "always on" + //clk_enable(&mck); - return 0; + //rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", + // freq / 1000000, (unsigned) mck.rate_hz / 1000000, + // (unsigned) main_clock / 1000000, + // ((unsigned) main_clock % 1000000) / 1000); //cause blocked + + return 0; } */ @@ -298,6 +284,6 @@ int at91_clock_init(rt_uint32_t main_clock) void rt_hw_clock_init(void) { - //at91_clock_init(18432000); + //at91_clock_init(18432000); } diff --git a/bsp/asm9260t/platform/timer0.c b/bsp/asm9260t/platform/timer0.c index cccbed9e57..91eaa19ad6 100644 --- a/bsp/asm9260t/platform/timer0.c +++ b/bsp/asm9260t/platform/timer0.c @@ -1,21 +1,7 @@ /* - * File : timer0.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/asm9260t/platform/timer0.h b/bsp/asm9260t/platform/timer0.h index 338ef05816..85cd955f46 100644 --- a/bsp/asm9260t/platform/timer0.h +++ b/bsp/asm9260t/platform/timer0.h @@ -1,21 +1,7 @@ /* - * File : timer0.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/asm9260t/platform/uart.c b/bsp/asm9260t/platform/uart.c index 7f39ef9c11..08613200db 100644 --- a/bsp/asm9260t/platform/uart.c +++ b/bsp/asm9260t/platform/uart.c @@ -1,27 +1,13 @@ /* - * File : interrupt.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2015-04-14 ArdaFu first version */ - + #include "asm9260t.h" #include "rtthread.h" #include "uart.h" diff --git a/bsp/asm9260t/platform/uart.h b/bsp/asm9260t/platform/uart.h index b1645e2ec5..b938483882 100644 --- a/bsp/asm9260t/platform/uart.h +++ b/bsp/asm9260t/platform/uart.h @@ -1,21 +1,7 @@ /* - * File : interrupt.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -50,16 +36,16 @@ typedef struct volatile rt_uint32_t ISO7816STATUS[4]; } HW_USART_TypeDef; -#define USART0 ((HW_USART_TypeDef *)UART0_BASE) -#define USART1 ((HW_USART_TypeDef *)UART1_BASE) -#define USART2 ((HW_USART_TypeDef *)UART2_BASE) -#define USART3 ((HW_USART_TypeDef *)UART3_BASE) -#define USART4 ((HW_USART_TypeDef *)UART4_BASE) -#define USART5 ((HW_USART_TypeDef *)UART5_BASE) -#define USART6 ((HW_USART_TypeDef *)UART6_BASE) -#define USART7 ((HW_USART_TypeDef *)UART7_BASE) -#define USART8 ((HW_USART_TypeDef *)UART8_BASE) -#define USART9 ((HW_USART_TypeDef *)UART9_BASE) +#define USART0 ((HW_USART_TypeDef *)UART0_BASE) +#define USART1 ((HW_USART_TypeDef *)UART1_BASE) +#define USART2 ((HW_USART_TypeDef *)UART2_BASE) +#define USART3 ((HW_USART_TypeDef *)UART3_BASE) +#define USART4 ((HW_USART_TypeDef *)UART4_BASE) +#define USART5 ((HW_USART_TypeDef *)UART5_BASE) +#define USART6 ((HW_USART_TypeDef *)UART6_BASE) +#define USART7 ((HW_USART_TypeDef *)UART7_BASE) +#define USART8 ((HW_USART_TypeDef *)UART8_BASE) +#define USART9 ((HW_USART_TypeDef *)UART9_BASE) #define ASM_UART_INTR_RXIS (1UL << 4) @@ -105,7 +91,7 @@ typedef struct extern void Hw_UartDisable(HW_USART_TypeDef* uartBase); extern void Hw_UartEnable(HW_USART_TypeDef* uartBase); extern void Hw_UartReset(HW_USART_TypeDef* uartBase); -extern void Hw_UartConfig(HW_USART_TypeDef* uartBase, int baudRate, +extern void Hw_UartConfig(HW_USART_TypeDef* uartBase, int baudRate, int dataBits, int stopBits, int parity); extern void Hw_UartInit(int index); #endif diff --git a/bsp/at32/Libraries/rt_drivers/drv_adc.c b/bsp/at32/Libraries/rt_drivers/drv_adc.c index 02e7b602af..25760e512b 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_adc.c +++ b/bsp/at32/Libraries/rt_drivers/drv_adc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,7 +17,7 @@ #include struct at32_adc -{ +{ struct rt_adc_device at32_adc_device; ADC_Type *ADC_Handler; char *name; @@ -109,9 +109,9 @@ static rt_err_t at32_adc_enabled(struct rt_adc_device *device, rt_uint32_t chann ADC_InitType ADC_InitStructure; RT_ASSERT(device != RT_NULL); at32_adc_handler = device->parent.user_data; - + at32_msp_adc_init(at32_adc_handler); - + /* ADCx configuration ------------------------------------------------------*/ ADC_StructInit(&ADC_InitStructure); ADC_InitStructure.ADC_Mode = ADC_Mode_Independent; @@ -121,14 +121,14 @@ static rt_err_t at32_adc_enabled(struct rt_adc_device *device, rt_uint32_t chann ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; ADC_InitStructure.ADC_NumOfChannel = 1; ADC_Init(at32_adc_handler, &ADC_InitStructure); - - /* ADCx regular channels configuration */ - ADC_RegularChannelConfig(at32_adc_handler, at32_adc_get_channel(channel), 1, ADC_SampleTime_28_5); - + + /* ADCx regular channels configuration */ + ADC_RegularChannelConfig(at32_adc_handler, at32_adc_get_channel(channel), 1, ADC_SampleTime_28_5); + /* Enable ADCx */ ADC_Ctrl(at32_adc_handler, ENABLE); - - /* Enable ADCx reset calibration register */ + + /* Enable ADCx reset calibration register */ ADC_RstCalibration(at32_adc_handler); /* Check the end of ADCx reset calibration register */ while(ADC_GetResetCalibrationStatus(at32_adc_handler)); @@ -161,7 +161,7 @@ static rt_err_t at32_get_adc_value(struct rt_adc_device *device, rt_uint32_t cha at32_adc_handler = device->parent.user_data; - /* Start ADCx Software Conversion */ + /* Start ADCx Software Conversion */ ADC_SoftwareStartConvCtrl(at32_adc_handler, ENABLE); /* Wait for the ADC to convert */ diff --git a/bsp/at32/Libraries/rt_drivers/drv_adc.h b/bsp/at32/Libraries/rt_drivers/drv_adc.h index d113d1338a..0991b0fe80 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_adc.h +++ b/bsp/at32/Libraries/rt_drivers/drv_adc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -19,32 +19,32 @@ extern "C" { #endif #if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3) - + #ifndef ADC1_CONFIG #define ADC1_CONFIG \ { \ .ADC_Handler = ADC1, \ .name = "adc1", \ - } + } #endif /* ADC1_CONFIG */ - + #ifndef ADC2_CONFIG #define ADC2_CONFIG \ { \ .ADC_Handler = ADC2, \ .name = "adc2", \ - } + } #endif /* ADC2_CONFIG */ - + #ifndef ADC3_CONFIG #define ADC3_CONFIG \ { \ .ADC_Handler = ADC3, \ .name = "adc3", \ - } -#endif /* ADC3_CONFIG */ - -#endif + } +#endif /* ADC3_CONFIG */ + +#endif #ifdef __cplusplus diff --git a/bsp/at32/Libraries/rt_drivers/drv_can.c b/bsp/at32/Libraries/rt_drivers/drv_can.c index 43f5a287e3..47a4bb3667 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_can.c +++ b/bsp/at32/Libraries/rt_drivers/drv_can.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -311,8 +311,8 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg) { can_instance->CanConfig.FilterConfig.CAN_FilterNumber = filter_cfg->items[i].hdr & (0x1fU); can_instance->CanConfig.FilterConfig.CAN_FilterIdHigh = (filter_cfg->items[i].id >> 13) & 0xFFFF; - can_instance->CanConfig.FilterConfig.CAN_FilterIdLow = ((filter_cfg->items[i].id << 3) | - (filter_cfg->items[i].ide << 2) | + can_instance->CanConfig.FilterConfig.CAN_FilterIdLow = ((filter_cfg->items[i].id << 3) | + (filter_cfg->items[i].ide << 2) | (filter_cfg->items[i].rtr << 1)) & 0xFFFF; can_instance->CanConfig.FilterConfig.CAN_FilterMskIdHigh = (filter_cfg->items[i].mask >> 16) & 0xFFFF; can_instance->CanConfig.FilterConfig.CAN_FilterMskIdLow = filter_cfg->items[i].mask & 0xFFFF; @@ -499,7 +499,7 @@ static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo) else pmsg->ide = RxMessage.ExtId; pmsg->rtr = RxMessage.RTR; - + return RT_EOK; } diff --git a/bsp/at32/Libraries/rt_drivers/drv_can.h b/bsp/at32/Libraries/rt_drivers/drv_can.h index d89bacda26..19afb93040 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_can.h +++ b/bsp/at32/Libraries/rt_drivers/drv_can.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,7 +22,7 @@ extern "C" { #define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */ #define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */ #define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */ - + struct at32_baud_rate_tab { rt_uint32_t baud_rate; diff --git a/bsp/at32/Libraries/rt_drivers/drv_eth.c b/bsp/at32/Libraries/rt_drivers/drv_eth.c index 3a14d9b918..e44429e0ea 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_eth.c +++ b/bsp/at32/Libraries/rt_drivers/drv_eth.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -28,8 +28,8 @@ //#define DRV_DEBUG #define LOG_TAG "drv.emac" -#define ETH_RXBUFNB 4 -#define ETH_TXBUFNB 2 +#define ETH_RXBUFNB 4 +#define ETH_TXBUFNB 2 #define LINK_THREAD_STACK_SIZE 256 #define LINK_THREAD_PREORITY 21 @@ -131,14 +131,14 @@ void NVIC_Configuration(void) NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0); /* 2 bit for pre-emption priority, 2 bits for subpriority */ - NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); /* Enable the Ethernet global Interrupt */ NVIC_InitStructure.NVIC_IRQChannel = ETH_IRQn; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); + NVIC_Init(&NVIC_InitStructure); } /** @@ -173,7 +173,7 @@ void GPIO_Configuration(void) GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; GPIO_Init(GPIOC, &GPIO_InitStructure); - /*MII Mode GPIO configuration*/ + /*MII Mode GPIO configuration*/ #ifdef MII_MODE /**********************MII Tx Pin Define****************************/ /* @@ -193,7 +193,7 @@ void GPIO_Configuration(void) GPIO_InitStructure.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; GPIO_Init(GPIOC, &GPIO_InitStructure); - /**********************MII Rx Pin Define****************************/ + /**********************MII Rx Pin Define****************************/ #if MII_RX_REMAP /*IO PIN remaped*/ /* ETH_MII_RX_DV-->PD8 @@ -208,7 +208,7 @@ void GPIO_Configuration(void) */ GPIO_InitStructure.GPIO_Pins = GPIO_Pins_8 | GPIO_Pins_9 | GPIO_Pins_10 | GPIO_Pins_11 | GPIO_Pins_12; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_Init(GPIOD, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_3; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; @@ -233,11 +233,11 @@ void GPIO_Configuration(void) GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pins = GPIO_Pins_4 | GPIO_Pins_5; + GPIO_InitStructure.GPIO_Pins = GPIO_Pins_4 | GPIO_Pins_5; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; GPIO_Init(GPIOC, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_10; + GPIO_InitStructure.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_10; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; GPIO_Init(GPIOB, &GPIO_InitStructure); @@ -255,8 +255,8 @@ void GPIO_Configuration(void) GPIO_InitStructure.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; GPIO_Init(GPIOB, &GPIO_InitStructure); - - /**********************RMII Rx Pin Define****************************/ + + /**********************RMII Rx Pin Define****************************/ #if MII_RX_REMAP /*IO PIN remaped*/ /* ETH_RMII_RX_DV-->PD8 @@ -266,7 +266,7 @@ void GPIO_Configuration(void) */ GPIO_InitStructure.GPIO_Pins = GPIO_Pins_8 | GPIO_Pins_9 | GPIO_Pins_10; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; - GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_Init(GPIOD, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Pins = GPIO_Pins_1; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; @@ -282,7 +282,7 @@ void GPIO_Configuration(void) GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pins = GPIO_Pins_4 | GPIO_Pins_5; + GPIO_InitStructure.GPIO_Pins = GPIO_Pins_4 | GPIO_Pins_5; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; GPIO_Init(GPIOC, &GPIO_InitStructure); @@ -314,7 +314,7 @@ static rt_err_t rt_at32_eth_init(rt_device_t dev) RCC_AHBPeriphClockCmd(RCC_AHBPERIPH_ETHMAC | RCC_AHBPERIPH_ETHMACTX | RCC_AHBPERIPH_ETHMACRX, ENABLE); - + /* MII/RMII Media interface selection ------------------------------------------*/ #ifdef MII_MODE /* Mode MII with AT32F407-EVAL */ GPIO_ETH_MediaInterfaceConfig(GPIO_ETH_MediaInterface_MII); @@ -361,31 +361,31 @@ static rt_err_t rt_at32_eth_init(rt_device_t dev) ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable; #endif - /*------------------------ DMA -----------------------------------*/ + /*------------------------ DMA -----------------------------------*/ - /* When we use the Checksum offload feature, we need to enable the Store and Forward mode: - the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum, + /* When we use the Checksum offload feature, we need to enable the Store and Forward mode: + the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum, if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */ - ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;//ETH_DropTCPIPChecksumErrorFrame_Enable; - ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; - ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; + ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;//ETH_DropTCPIPChecksumErrorFrame_Enable; + ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; + ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; - ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; - ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; - ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable; - ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; - ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable; - ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat; - ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat; + ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; + ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; + ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable; + ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; + ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable; + ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat; + ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat; ETH_InitStructure.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_2_1; /* Configure Ethernet, check error */ if(ETH_Init(Ð_InitStructure, PHY_ADDRESS) == ((uint32_t)0)) { return RT_ERROR; - } + } /* Enable DMA Receive interrupt (need to enable in this case Normal interrupt) */ - ETH_DMAITConfig(ETH_DMA_INT_NIS | ETH_DMA_INT_R, ENABLE); + ETH_DMAITConfig(ETH_DMA_INT_NIS | ETH_DMA_INT_R, ENABLE); /* Initialize Tx Descriptors list: Chain Mode */ ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB); @@ -396,7 +396,7 @@ static rt_err_t rt_at32_eth_init(rt_device_t dev) ETH_MACAddressConfig(ETH_MAC_Address0, (u8*)&at32_eth_device.dev_addr[0]); /* Enable ETH transmition and recetion */ - ETH_Start(); + ETH_Start(); return RT_EOK; } @@ -581,7 +581,7 @@ struct pbuf *rt_at32_eth_rx(rt_device_t dev) { rt_uint32_t i; rt_uint8_t *ptr = (rt_uint8_t*)(DMARxDescToGet->Buffer1Addr); - + AT32_ETH_PRINTF("rx_dump, len:%d\r\n", p->tot_len); for(i=0; itot_len; i++) { diff --git a/bsp/at32/Libraries/rt_drivers/drv_eth.h b/bsp/at32/Libraries/rt_drivers/drv_eth.h index 398b4bdc0c..d5a5a05cc5 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_eth.h +++ b/bsp/at32/Libraries/rt_drivers/drv_eth.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/at32/Libraries/rt_drivers/drv_flash.c b/bsp/at32/Libraries/rt_drivers/drv_flash.c index 8104f9b612..a1b381beaa 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_flash.c +++ b/bsp/at32/Libraries/rt_drivers/drv_flash.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -160,14 +160,14 @@ int at32_flash_erase(rt_uint32_t addr, size_t size) addr += FLASH_PAGE_SIZE; } - FLASH_Lock(); - -__exit: + FLASH_Lock(); + +__exit: if(result != RT_EOK) { return result; } - + return size; } @@ -177,7 +177,7 @@ static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size); static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size); static int fal_flash_erase(long offset, size_t size); -const struct fal_flash_dev at32_onchip_flash = +const struct fal_flash_dev at32_onchip_flash = { "onchip_flash", AT32_FLASH_START_ADRESS, diff --git a/bsp/at32/Libraries/rt_drivers/drv_flash.h b/bsp/at32/Libraries/rt_drivers/drv_flash.h index 9392ff4303..7ec0a18632 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_flash.h +++ b/bsp/at32/Libraries/rt_drivers/drv_flash.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/at32/Libraries/rt_drivers/drv_gpio.c b/bsp/at32/Libraries/rt_drivers/drv_gpio.c index d6fd0594dc..bc9f6b87bb 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_gpio.c +++ b/bsp/at32/Libraries/rt_drivers/drv_gpio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,7 +13,7 @@ #ifdef RT_USING_PIN -static const struct pin_index pins[] = +static const struct pin_index pins[] = { #if defined(GPIOA) __AT32_PIN(0 , A, 0 ), @@ -414,7 +414,7 @@ static rt_err_t at32_pin_irq_enable(struct rt_device *device, rt_base_t pin, /* Configure GPIO_InitStructure */ GPIO_StructInit(&GPIO_InitStruct); EXTI_StructInit(&EXTI_InitStruct); - GPIO_InitStruct.GPIO_Pins = irqmap->pinbit; + GPIO_InitStruct.GPIO_Pins = irqmap->pinbit; GPIO_InitStruct.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz; EXTI_InitStruct.EXTI_Line = irqmap->pinbit; EXTI_InitStruct.EXTI_Mode = EXTI_Mode_Interrupt; @@ -462,24 +462,24 @@ static rt_err_t at32_pin_irq_enable(struct rt_device *device, rt_base_t pin, if (( irqmap->pinbit>=GPIO_Pins_5 )&&( irqmap->pinbit<=GPIO_Pins_9 )) { if(!(pin_irq_enable_mask&(GPIO_Pins_5|GPIO_Pins_6|GPIO_Pins_7|GPIO_Pins_8|GPIO_Pins_9))) - { + { NVIC_InitStruct.NVIC_IRQChannel = irqmap->irqno; } } else if (( irqmap->pinbit>=GPIO_Pins_10 )&&( irqmap->pinbit<=GPIO_Pins_15 )) { if(!(pin_irq_enable_mask&(GPIO_Pins_10|GPIO_Pins_11|GPIO_Pins_12|GPIO_Pins_13|GPIO_Pins_14|GPIO_Pins_15))) - { + { NVIC_InitStruct.NVIC_IRQChannel = irqmap->irqno; } } else { NVIC_InitStruct.NVIC_IRQChannel = irqmap->irqno; - } + } NVIC_Init(&NVIC_InitStruct); - rt_hw_interrupt_enable(level); + rt_hw_interrupt_enable(level); } else { diff --git a/bsp/at32/Libraries/rt_drivers/drv_gpio.h b/bsp/at32/Libraries/rt_drivers/drv_gpio.h index 63870611f5..a8f5b7474e 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_gpio.h +++ b/bsp/at32/Libraries/rt_drivers/drv_gpio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/at32/Libraries/rt_drivers/drv_hwtimer.c b/bsp/at32/Libraries/rt_drivers/drv_hwtimer.c index 97788d22c9..dede483e54 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_hwtimer.c +++ b/bsp/at32/Libraries/rt_drivers/drv_hwtimer.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2020-03-16 Leo first version */ - + #include #include "drv_hwtimer.h" @@ -20,35 +20,35 @@ enum { #ifdef BSP_USING_HWTMR1 TMR1_INDEX, -#endif - +#endif + #ifdef BSP_USING_HWTMR2 TMR2_INDEX, -#endif - +#endif + #ifdef BSP_USING_HWTMR3 TMR3_INDEX, -#endif +#endif #ifdef BSP_USING_HWTMR4 TMR4_INDEX, -#endif +#endif #ifdef BSP_USING_HWTMR5 TMR5_INDEX, -#endif +#endif #ifdef BSP_USING_HWTMR6 TMR6_INDEX, -#endif +#endif #ifdef BSP_USING_HWTMR7 TMR7_INDEX, -#endif +#endif #ifdef BSP_USING_HW_TMR8 TMR8_INDEX, -#endif +#endif #ifdef BSP_USING_HWTMR9 TMR9_INDEX, @@ -56,11 +56,11 @@ enum #ifdef BSP_USING_HWTMR10 TMR10_INDEX, -#endif +#endif #ifdef BSP_USING_HWTMR11 TMR11_INDEX, -#endif +#endif #ifdef BSP_USING_HWTMR12 TMR12_INDEX, @@ -68,11 +68,11 @@ enum #ifdef BSP_USING_HWTMR13 TMR13_INDEX, -#endif +#endif #ifdef BSP_USING_HWTMR14 TMR14_INDEX, -#endif +#endif #ifdef BSP_USING_HWTMR15 TMR15_INDEX, @@ -91,48 +91,48 @@ static struct at32_hwtimer at32_hwtimer_obj[] = { #ifdef BSP_USING_HWTMR1 TMR1_CONFIG, -#endif +#endif #ifdef BSP_USING_HWTMR2 TMR2_CONFIG, #endif - + #ifdef BSP_USING_HWTMR3 TMR3_CONFIG, #endif - + #ifdef BSP_USING_HWTMR4 TMR4_CONFIG, #endif #ifdef BSP_USING_HWTMR5 TMR5_CONFIG, -#endif +#endif #ifdef BSP_USING_HWTMR6 TMR6_CONFIG, #endif - + #ifdef BSP_USING_HWTMR7 TMR7_CONFIG, #endif - + #ifdef BSP_USING_HWTMR8 TMR8_CONFIG, #endif #ifdef BSP_USING_HWTMR9 TMR9_CONFIG, -#endif +#endif #ifdef BSP_USING_HWTMR10 TMR10_CONFIG, #endif - + #ifdef BSP_USING_HWTMR11 TMR11_CONFIG, #endif - + #ifdef BSP_USING_HWTMR12 TMR12_CONFIG, #endif @@ -164,20 +164,20 @@ static void at32_timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) { tim = (TMR_Type *)timer->parent.user_data; tim_device = (struct at32_hwtimer *)timer; - + /* timer clock enable */ at32_msp_hwtmr_init(tim); - + /* timer init */ RCC_GetClocksFreq(&RCC_ClockStruct); /* Set timer clock is 1Mhz */ prescaler_value = (uint32_t)(RCC_ClockStruct.SYSCLK_Freq / 10000) - 1; - + TMR_TMReBaseStructure.TMR_Period = 10000 - 1; TMR_TMReBaseStructure.TMR_DIV = prescaler_value; TMR_TMReBaseStructure.TMR_ClockDivision = TMR_CKD_DIV1; TMR_TMReBaseStructure.TMR_RepetitionCounter = 0; - + if (timer->info->cntmode == HWTIMER_CNTMODE_UP) { TMR_TMReBaseStructure.TMR_CounterMode = TMR_CounterDIR_Up; @@ -186,21 +186,21 @@ static void at32_timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) { TMR_TMReBaseStructure.TMR_CounterMode = TMR_CounterDIR_Down; } - + TMR_TimeBaseInit(tim, &TMR_TMReBaseStructure); - + /* Enable the TMRx global Interrupt */ NVIC_InitStructure.NVIC_IRQChannel = tim_device->tim_irqn; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); - + TMR_INTConfig(tim, TMR_INT_Overflow ,ENABLE); TMR_ClearITPendingBit(tim, TMR_INT_Overflow); - + LOG_D("%s init success", tim_device->name); - } + } } static rt_err_t at32_timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode) @@ -211,7 +211,7 @@ static rt_err_t at32_timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_ RT_ASSERT(timer != RT_NULL); tim = (TMR_Type *)timer->parent.user_data; - + /* set tim cnt */ TMR_SetCounter(tim, 0); /* set tim arr */ @@ -225,10 +225,10 @@ static rt_err_t at32_timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_ { TMR_SelectOnePulseMode(tim, TMR_OPMode_Repetitive); } - + /* start timer */ TMR_Cmd(tim, ENABLE); - + return result; } @@ -239,7 +239,7 @@ static void at32_timer_stop(rt_hwtimer_t *timer) RT_ASSERT(timer != RT_NULL); tim = (TMR_Type *)timer->parent.user_data; - + /* stop timer */ TMR_Cmd(tim, ENABLE); /* set tim cnt */ @@ -253,7 +253,7 @@ static rt_uint32_t at32_timer_counter_get(rt_hwtimer_t *timer) RT_ASSERT(timer != RT_NULL); tim = (TMR_Type *)timer->parent.user_data; - + return tim->CNT; } @@ -267,22 +267,22 @@ static rt_err_t at32_timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) RT_ASSERT(arg != RT_NULL); tim = (TMR_Type *)timer->parent.user_data; - + switch(cmd) { case HWTIMER_CTRL_FREQ_SET: { rt_uint32_t freq; rt_uint16_t val; - + /* set timer frequence */ freq = *((rt_uint32_t *)arg); - + /* time init */ RCC_GetClocksFreq(&RCC_ClockStruct); - + val = RCC_ClockStruct.SYSCLK_Freq / freq; - + TMR_DIVConfig(tim, val - 1, TMR_DIVReloadMode_Immediate); } break; @@ -292,7 +292,7 @@ static rt_err_t at32_timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg) } break; } - + return result; } @@ -311,13 +311,13 @@ void TMR2_GLOBAL_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - + if(TMR_GetINTStatus(TMR2, TMR_INT_Overflow) == SET) { - + rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR2_INDEX].time_device); TMR_ClearITPendingBit(TMR2, TMR_INT_Overflow); - + } /* leave interrupt */ rt_interrupt_leave(); @@ -329,13 +329,13 @@ void TMR3_GLOBAL_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - + if(TMR_GetINTStatus(TMR3, TMR_INT_Overflow) == SET) { - + rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR3_INDEX].time_device); TMR_ClearITPendingBit(TMR3, TMR_INT_Overflow); - + } /* leave interrupt */ rt_interrupt_leave(); @@ -347,13 +347,13 @@ void TMR4_GLOBAL_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - + if(TMR_GetINTStatus(TMR4, TMR_INT_Overflow) == SET) { - + rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR4_INDEX].time_device); TMR_ClearITPendingBit(TMR4, TMR_INT_Overflow); - + } /* leave interrupt */ rt_interrupt_leave(); @@ -365,13 +365,13 @@ void TMR5_GLOBAL_IRQHandler(void) { /* enter interrupt */ rt_interrupt_enter(); - + if(TMR_GetINTStatus(TMR5, TMR_INT_Overflow) == SET) { - + rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR5_INDEX].time_device); TMR_ClearITPendingBit(TMR5, TMR_INT_Overflow); - + } /* leave interrupt */ rt_interrupt_leave(); diff --git a/bsp/at32/Libraries/rt_drivers/drv_hwtimer.h b/bsp/at32/Libraries/rt_drivers/drv_hwtimer.h index 9ae4981e3f..9acfb8d468 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_hwtimer.h +++ b/bsp/at32/Libraries/rt_drivers/drv_hwtimer.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -26,7 +26,7 @@ extern "C" { .maxcnt = 0xFFFF, \ .cntmode = HWTIMER_CNTMODE_UP, \ } -#endif /* TIM_DEV_INFO_CONFIG */ +#endif /* TIM_DEV_INFO_CONFIG */ #ifdef BSP_USING_HWTMR2 #ifndef TMR2_CONFIG @@ -36,9 +36,9 @@ extern "C" { .tim_irqn = TMR2_GLOBAL_IRQn, \ .name = "timer2", \ } -#endif /* TMR2_CONFIG */ -#endif /* BSP_USING_HWTMR2 */ - +#endif /* TMR2_CONFIG */ +#endif /* BSP_USING_HWTMR2 */ + #ifdef BSP_USING_HWTMR3 #ifndef TMR3_CONFIG #define TMR3_CONFIG \ @@ -47,8 +47,8 @@ extern "C" { .tim_irqn = TMR3_GLOBAL_IRQn, \ .name = "timer3", \ } -#endif /* TMR3_CONFIG */ -#endif /* BSP_USING_HWTMR3 */ +#endif /* TMR3_CONFIG */ +#endif /* BSP_USING_HWTMR3 */ #ifdef BSP_USING_HWTMR4 #ifndef TMR4_CONFIG @@ -58,9 +58,9 @@ extern "C" { .tim_irqn = TMR4_GLOBAL_IRQn, \ .name = "timer4", \ } -#endif /* TMR4_CONFIG */ +#endif /* TMR4_CONFIG */ #endif /* BSP_USING_HWTMR4 */ - + #ifdef BSP_USING_HWTMR5 #ifndef TMR5_CONFIG #define TMR5_CONFIG \ @@ -69,9 +69,9 @@ extern "C" { .tim_irqn = TMR5_GLOBAL_IRQn, \ .name = "timer5", \ } -#endif /* TMR5_CONFIG */ -#endif /* BSP_USING_HWTMR5 */ - +#endif /* TMR5_CONFIG */ +#endif /* BSP_USING_HWTMR5 */ + #ifdef __cplusplus } #endif diff --git a/bsp/at32/Libraries/rt_drivers/drv_log.h b/bsp/at32/Libraries/rt_drivers/drv_log.h index a813acb0cb..d91f70d37c 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_log.h +++ b/bsp/at32/Libraries/rt_drivers/drv_log.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/at32/Libraries/rt_drivers/drv_pwm.c b/bsp/at32/Libraries/rt_drivers/drv_pwm.c index 78b1b2d7a9..9a188681ed 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_pwm.c +++ b/bsp/at32/Libraries/rt_drivers/drv_pwm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -37,52 +37,52 @@ struct at32_pwm char *name; }; -static struct at32_pwm at32_pwm_obj[] = +static struct at32_pwm at32_pwm_obj[] = { #ifdef BSP_USING_TMR1_CH1 PWM1_CONFIG, #endif - + #ifdef BSP_USING_TMR1_CH2 PWM2_CONFIG, #endif - + #ifdef BSP_USING_TMR1_CH3 PWM3_CONFIG, #endif - + #ifdef BSP_USING_TMR1_CH4 PWM4_CONFIG, #endif - + #ifdef BSP_USING_TMR2_CH1 PWM5_CONFIG, #endif - + #ifdef BSP_USING_TMR2_CH2 PWM6_CONFIG, #endif - + #ifdef BSP_USING_TMR2_CH3 PWM7_CONFIG, #endif - + #ifdef BSP_USING_TMR2_CH4 PWM8_CONFIG, #endif - + #ifdef BSP_USING_TMR3_CH1 PWM9_CONFIG, #endif - + #ifdef BSP_USING_TMR3_CH2 PWM10_CONFIG, #endif - + #ifdef BSP_USING_TMR3_CH3 PWM11_CONFIG, #endif - + #ifdef BSP_USING_TMR3_CH4 PWM12_CONFIG, #endif @@ -97,7 +97,7 @@ static struct rt_pwm_ops drv_ops = static rt_err_t drv_pwm_enable(TMR_Type* TMRx, struct rt_pwm_configuration *configuration, rt_bool_t enable) { /* Get the value of channel */ - rt_uint32_t channel = configuration->channel; + rt_uint32_t channel = configuration->channel; if (!enable) { @@ -137,7 +137,7 @@ static rt_err_t drv_pwm_enable(TMR_Type* TMRx, struct rt_pwm_configuration *conf TMR_CCxCmd(TMRx, TMR_Channel_1, TMR_CCx_Enable); } } - + /* TMRx enable counter */ TMR_Cmd(TMRx, ENABLE); @@ -173,7 +173,7 @@ static rt_err_t drv_pwm_get(TMR_Type* TMRx, struct rt_pwm_configuration *configu configuration->pulse = (cc3 + 1) * (div + 1) * 1000UL / tim_clock; if(channel == 4) configuration->pulse = (cc4 + 1) * (div + 1) * 1000UL / tim_clock; - + return RT_EOK; } @@ -185,15 +185,15 @@ static rt_err_t drv_pwm_set(TMR_Type* TMRx, struct rt_pwm_configuration *configu rt_uint64_t psc; /* Get the channel number */ rt_uint32_t channel = configuration->channel; - + /* Init timer pin and enable clock */ at32_msp_tmr_init(TMRx); - + /* Convert nanosecond to frequency and duty cycle. */ period = (unsigned long long)configuration->period ; psc = period / MAX_PERIOD + 1; period = period / psc; - + /* TMRe base configuration */ TMR_TimeBaseStructInit(&TMR_TMReBaseStructure); TMR_TMReBaseStructure.TMR_Period = period; @@ -204,14 +204,14 @@ static rt_err_t drv_pwm_set(TMR_Type* TMRx, struct rt_pwm_configuration *configu TMR_TimeBaseInit(TMRx, &TMR_TMReBaseStructure); pulse = (unsigned long long)configuration->pulse; - + /* PWM1 Mode configuration: Channel1 */ TMR_OCStructInit(&TMR_OCInitStructure); TMR_OCInitStructure.TMR_OCMode = TMR_OCMode_PWM1; TMR_OCInitStructure.TMR_OutputState = TMR_OutputState_Enable; TMR_OCInitStructure.TMR_Pulse = pulse; TMR_OCInitStructure.TMR_OCPolarity = TMR_OCPolarity_High; - + if(channel == 1) { TMR_OC1Init(TMRx, &TMR_OCInitStructure); @@ -232,7 +232,7 @@ static rt_err_t drv_pwm_set(TMR_Type* TMRx, struct rt_pwm_configuration *configu TMR_OC4Init(TMRx, &TMR_OCInitStructure); TMR_OC4PreloadConfig(TMRx, TMR_OCPreload_Enable); } - + TMR_ARPreloadConfig(TMRx, ENABLE); #if defined (SOC_SERIES_AT32F415) @@ -271,7 +271,7 @@ static int rt_hw_pwm_init(void) { int i = 0; int result = RT_EOK; - + for(i = 0; i < sizeof(at32_pwm_obj) / sizeof(at32_pwm_obj[0]); i++) { if(rt_device_pwm_register(&at32_pwm_obj[i].pwm_device, at32_pwm_obj[i].name, &drv_ops, at32_pwm_obj[i].tim_handle) == RT_EOK) @@ -280,9 +280,9 @@ static int rt_hw_pwm_init(void) } else { - LOG_D("%s register failed", at32_pwm_obj[i].name); - result = -RT_ERROR; - } + LOG_D("%s register failed", at32_pwm_obj[i].name); + result = -RT_ERROR; + } } return result; diff --git a/bsp/at32/Libraries/rt_drivers/drv_pwm.h b/bsp/at32/Libraries/rt_drivers/drv_pwm.h index 6cdcfc6415..720a810f79 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_pwm.h +++ b/bsp/at32/Libraries/rt_drivers/drv_pwm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -28,7 +28,7 @@ extern "C" { } #endif /* PWM1_CONFIG */ #endif /* BSP_USING_TMR1_CH1 */ - + #ifdef BSP_USING_TMR1_CH2 #ifndef PWM2_CONFIG #define PWM2_CONFIG \ @@ -72,7 +72,7 @@ extern "C" { } #endif /* PWM5_CONFIG */ #endif /* BSP_USING_TMR2_CH1 */ - + #ifdef BSP_USING_TMR2_CH2 #ifndef PWM6_CONFIG #define PWM6_CONFIG \ @@ -82,8 +82,8 @@ extern "C" { .channel = 2 \ } #endif /* PWM6_CONFIG */ -#endif /* BSP_USING_TMR2_CH2 */ - +#endif /* BSP_USING_TMR2_CH2 */ + #ifdef BSP_USING_TMR2_CH3 #ifndef PWM7_CONFIG #define PWM7_CONFIG \ @@ -93,7 +93,7 @@ extern "C" { .channel = 3 \ } #endif /* PWM7_CONFIG */ -#endif /* BSP_USING_TMR2_CH3 */ +#endif /* BSP_USING_TMR2_CH3 */ #ifdef BSP_USING_TMR2_CH4 #ifndef PWM8_CONFIG @@ -115,7 +115,7 @@ extern "C" { .channel = 1 \ } #endif /* PWM9_CONFIG */ -#endif /* BSP_USING_TMR3_CH1 */ +#endif /* BSP_USING_TMR3_CH1 */ #ifdef BSP_USING_TMR3_CH2 #ifndef PWM10_CONFIG @@ -149,7 +149,7 @@ extern "C" { } #endif /* PWM12_CONFIG */ #endif /* BSP_USING_TMR3_CH4 */ - + #ifdef __cplusplus } #endif diff --git a/bsp/at32/Libraries/rt_drivers/drv_rtc.c b/bsp/at32/Libraries/rt_drivers/drv_rtc.c index bd4d89a9ed..d943123e88 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_rtc.c +++ b/bsp/at32/Libraries/rt_drivers/drv_rtc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -79,10 +79,10 @@ static rt_err_t set_rtc_time_stamp(time_t time_stamp) return -RT_ERROR; } #else - /* Set the RTC counter value */ - RTC_SetCounter(time_stamp); - /* Wait until last write operation on RTC registers has finished */ - RTC_WaitForLastTask(); + /* Set the RTC counter value */ + RTC_SetCounter(time_stamp); + /* Wait until last write operation on RTC registers has finished */ + RTC_WaitForLastTask(); #endif /* SOC_SERIES_AT32F415 */ LOG_D("set rtc time."); #ifdef SOC_SERIES_AT32F415 @@ -117,7 +117,7 @@ static rt_err_t rt_rtc_config(struct rt_device *dev) ERTC_InitType ERTC_InitStructure; #endif /* Allow access to BKP Domain */ - PWR_BackupAccessCtrl(ENABLE); + PWR_BackupAccessCtrl(ENABLE); #ifdef SOC_SERIES_AT32F415 #ifdef BSP_RTC_USING_LSI @@ -148,7 +148,7 @@ static rt_err_t rt_rtc_config(struct rt_device *dev) #else if (BKP_ReadBackupReg(BKP_DT1) != BKUP_REG_DATA) #endif - { + { LOG_I("RTC hasn't been configured, please use command to config."); #ifdef SOC_SERIES_AT32F415 /* Configure the ERTC data register and ERTC prescaler */ diff --git a/bsp/at32/Libraries/rt_drivers/drv_sdio.c b/bsp/at32/Libraries/rt_drivers/drv_sdio.c index eb721033b5..9bbfa910c2 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_sdio.c +++ b/bsp/at32/Libraries/rt_drivers/drv_sdio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/at32/Libraries/rt_drivers/drv_sdio.h b/bsp/at32/Libraries/rt_drivers/drv_sdio.h index cd0f05b9fb..de993881c9 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_sdio.h +++ b/bsp/at32/Libraries/rt_drivers/drv_sdio.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/at32/Libraries/rt_drivers/drv_soft_i2c.c b/bsp/at32/Libraries/rt_drivers/drv_soft_i2c.c index 266209c245..3112da34f8 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_soft_i2c.c +++ b/bsp/at32/Libraries/rt_drivers/drv_soft_i2c.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -205,10 +205,10 @@ int rt_hw_i2c_init(void) result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c_bus, soft_i2c_config[i].bus_name); RT_ASSERT(result == RT_EOK); at32_i2c_bus_unlock(&soft_i2c_config[i]); - + LOG_D("software simulation %s init done, pin scl: %d, pin sda %d", - soft_i2c_config[i].bus_name, - soft_i2c_config[i].scl, + soft_i2c_config[i].bus_name, + soft_i2c_config[i].scl, soft_i2c_config[i].sda); } diff --git a/bsp/at32/Libraries/rt_drivers/drv_soft_i2c.h b/bsp/at32/Libraries/rt_drivers/drv_soft_i2c.h index 2743259ef6..193c8cd4aa 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_soft_i2c.h +++ b/bsp/at32/Libraries/rt_drivers/drv_soft_i2c.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -37,7 +37,7 @@ struct at32_i2c .bus_name = "i2c1", \ } #endif - + #ifdef BSP_USING_I2C2 #define i2c_bus_CONFIG \ { \ @@ -46,7 +46,7 @@ struct at32_i2c .bus_name = "i2c2", \ } #endif - + #ifdef BSP_USING_I2C3 #define I2C3_BUS_CONFIG \ { \ @@ -55,7 +55,7 @@ struct at32_i2c .bus_name = "i2c3", \ } #endif - + #ifdef BSP_USING_I2C4 #define I2C4_BUS_CONFIG \ { \ diff --git a/bsp/at32/Libraries/rt_drivers/drv_spi.c b/bsp/at32/Libraries/rt_drivers/drv_spi.c index c7821d4053..161845702f 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_spi.c +++ b/bsp/at32/Libraries/rt_drivers/drv_spi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2020-01-09 shelton first version */ - + #include #include "drv_spi.h" @@ -24,7 +24,7 @@ #ifdef DEBUG #define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__) #else -#define DEBUG_PRINTF(...) +#define DEBUG_PRINTF(...) #endif /* private rt-thread spi ops function */ @@ -81,13 +81,13 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration) { - struct rt_spi_bus * spi_bus = (struct rt_spi_bus *)device->bus; + struct rt_spi_bus * spi_bus = (struct rt_spi_bus *)device->bus; struct at32_spi *spi_instance = (struct at32_spi *)spi_bus->parent.user_data; - + SPI_InitType SPI_InitStruct; - RT_ASSERT(device != RT_NULL); - RT_ASSERT(configuration != RT_NULL); + RT_ASSERT(device != RT_NULL); + RT_ASSERT(configuration != RT_NULL); at32_msp_spi_init(spi_instance->config->spix); @@ -162,7 +162,7 @@ static rt_err_t configure(struct rt_spi_device* device, SPI_InitStruct.SPI_MCLKP = SPI_MCLKP_256; } } /* baudrate */ - + switch(configuration->mode & RT_SPI_MODE_3) { case RT_SPI_MODE_0: @@ -172,11 +172,11 @@ static rt_err_t configure(struct rt_spi_device* device, case RT_SPI_MODE_1: SPI_InitStruct.SPI_CPHA = SPI_CPHA_2EDGE; SPI_InitStruct.SPI_CPOL = SPI_CPOL_LOW; - break; + break; case RT_SPI_MODE_2: SPI_InitStruct.SPI_CPHA = SPI_CPHA_1EDGE; SPI_InitStruct.SPI_CPOL = SPI_CPOL_HIGH; - break; + break; case RT_SPI_MODE_3: SPI_InitStruct.SPI_CPHA = SPI_CPHA_2EDGE; SPI_InitStruct.SPI_CPOL = SPI_CPOL_HIGH; @@ -200,7 +200,7 @@ static rt_err_t configure(struct rt_spi_device* device, /* init SPI */ SPI_Init(spi_instance->config->spix, &SPI_InitStruct); /* Enable SPI_MASTER */ - SPI_Enable(spi_instance->config->spix, ENABLE); + SPI_Enable(spi_instance->config->spix, ENABLE); SPI_CRCEN(spi_instance->config->spix, DISABLE); return RT_EOK; @@ -213,9 +213,9 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes struct rt_spi_configuration * config = &device->config; struct at32_spi_cs * at32_spi_cs = device->parent.user_data; - RT_ASSERT(device != NULL); - RT_ASSERT(message != NULL); - + RT_ASSERT(device != NULL); + RT_ASSERT(message != NULL); + /* take CS */ if(message->cs_take) { @@ -229,7 +229,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes const rt_uint8_t * send_ptr = message->send_buf; rt_uint8_t * recv_ptr = message->recv_buf; rt_uint32_t size = message->length; - + DEBUG_PRINTF("spi poll transfer start: %d\n", size); while(size--) @@ -240,12 +240,12 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes { data = *send_ptr++; } - + // Todo: replace register read/write by at32 lib //Wait until the transmit buffer is empty while(RESET == SPI_I2S_GetFlagStatus(spi_instance->config->spix, SPI_I2S_FLAG_TE)); // Send the byte - SPI_I2S_TxData(spi_instance->config->spix, data); + SPI_I2S_TxData(spi_instance->config->spix, data); //Wait until a data is received while(RESET == SPI_I2S_GetFlagStatus(spi_instance->config->spix, SPI_I2S_FLAG_RNE)); @@ -277,7 +277,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes //Wait until the transmit buffer is empty while(RESET == SPI_I2S_GetFlagStatus(spi_instance->config->spix, SPI_I2S_FLAG_TE)); // Send the byte - SPI_I2S_TxData(spi_instance->config->spix, data); + SPI_I2S_TxData(spi_instance->config->spix, data); //Wait until a data is received while(RESET == SPI_I2S_GetFlagStatus(spi_instance->config->spix, SPI_I2S_FLAG_RNE)); @@ -295,7 +295,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes /* release CS */ if(message->cs_release) { - GPIO_SetBits(at32_spi_cs->GPIOx, at32_spi_cs->GPIO_Pin); + GPIO_SetBits(at32_spi_cs->GPIOx, at32_spi_cs->GPIO_Pin); DEBUG_PRINTF("spi release cs\n"); } @@ -306,7 +306,7 @@ static struct at32_spi_config configs[] = { #ifdef BSP_USING_SPI1 {SPI1, "spi1"}, #endif - + #ifdef BSP_USING_SPI2 {SPI2, "spi2"}, #endif diff --git a/bsp/at32/Libraries/rt_drivers/drv_spi.h b/bsp/at32/Libraries/rt_drivers/drv_spi.h index d3134b00f0..cd90c9b2b0 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_spi.h +++ b/bsp/at32/Libraries/rt_drivers/drv_spi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/at32/Libraries/rt_drivers/drv_sram.c b/bsp/at32/Libraries/rt_drivers/drv_sram.c index e601b0e1a5..d77b900728 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_sram.c +++ b/bsp/at32/Libraries/rt_drivers/drv_sram.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -38,7 +38,7 @@ static int rt_hw_sram_Init(void) /* Init XMC pin */ at32_msp_xmc_init(XMC); - + /*-- FSMC Configuration ------------------------------------------------------*/ p.XMC_AdrOpTime = 0x04; p.XMC_AdrHoldTime = 0x04; @@ -53,7 +53,7 @@ static int rt_hw_sram_Init(void) XMC_NORSRAMInitStructure.XMC_Dev = XMC_Dev_SRAM; XMC_NORSRAMInitStructure.XMC_BusType = XMC_BusType_16b; XMC_NORSRAMInitStructure.XMC_EnableBurstMode = XMC_BurstMode_Disable; - XMC_NORSRAMInitStructure.XMC_EnableAsynWait = XMC_AsynWait_Disable; + XMC_NORSRAMInitStructure.XMC_EnableAsynWait = XMC_AsynWait_Disable; XMC_NORSRAMInitStructure.XMC_WaitSignalLv = XMC_WaitSignalLv_Low; XMC_NORSRAMInitStructure.XMC_EnableBurstModeSplit = XMC_BurstModeSplit_Disable; XMC_NORSRAMInitStructure.XMC_WaitSignalConfig = XMC_WaitSignalConfig_BeforeWaitState; @@ -63,9 +63,9 @@ static int rt_hw_sram_Init(void) XMC_NORSRAMInitStructure.XMC_WriteBurstSyn = XMC_WriteBurstSyn_Disable; XMC_NORSRAMInitStructure.XMC_RWTimingStruct = &p; XMC_NORSRAMInitStructure.XMC_WTimingStruct = &p; - - XMC_NORSRAMInit(&XMC_NORSRAMInitStructure); - + + XMC_NORSRAMInit(&XMC_NORSRAMInitStructure); + /*!< Enable FSMC Bank1_SRAM Bank */ XMC_NORSRAMCmd(XMC_Bank1_NORSRAM3, ENABLE); @@ -73,7 +73,7 @@ static int rt_hw_sram_Init(void) /* If RT_USING_MEMHEAP_AS_HEAP is enabled, SRAM is initialized to the heap */ rt_memheap_init(&system_heap, "sram", (void *)EXT_SRAM_BEGIN, SRAM_LENGTH); #endif - + return result; } INIT_BOARD_EXPORT(rt_hw_sram_Init); @@ -81,11 +81,11 @@ INIT_BOARD_EXPORT(rt_hw_sram_Init); #ifdef DRV_DEBUG #ifdef FINSH_USING_MSH /** - * @brief Writes a Half-word buffer to the FSMC SRAM memory. - * @param pBuffer : pointer to buffer. - * @param WriteAddr : SRAM memory internal address from which the data will be + * @brief Writes a Half-word buffer to the FSMC SRAM memory. + * @param pBuffer : pointer to buffer. + * @param WriteAddr : SRAM memory internal address from which the data will be * written. - * @param NumHalfwordToWrite : number of half-words to write. + * @param NumHalfwordToWrite : number of half-words to write. * @retval None */ static void SRAM_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t NumHalfwordToWrite) @@ -94,15 +94,15 @@ static void SRAM_WriteBuffer(uint16_t* pBuffer, uint32_t WriteAddr, uint32_t Num { /*!< Transfer data to the memory */ *(uint16_t *) (EXT_SRAM_BEGIN + WriteAddr) = *pBuffer++; - - /*!< Increment the address*/ + + /*!< Increment the address*/ WriteAddr += 2; - } + } } /** * @brief Reads a block of data from the FSMC SRAM memory. - * @param pBuffer : pointer to the buffer that receives the data read from the + * @param pBuffer : pointer to the buffer that receives the data read from the * SRAM memory. * @param ReadAddr : SRAM memory internal address to read from. * @param NumHalfwordToRead : number of half-words to read. @@ -115,9 +115,9 @@ static void SRAM_ReadBuffer(uint16_t* pBuffer, uint32_t ReadAddr, uint32_t NumHa /*!< Read a half-word from the memory */ *pBuffer++ = *(__IO uint16_t*) (EXT_SRAM_BEGIN + ReadAddr); - /*!< Increment the address*/ + /*!< Increment the address*/ ReadAddr += 2; - } + } } /** @@ -146,9 +146,9 @@ int sram_test(void) /* Read data from XMC SRAM memory */ - SRAM_ReadBuffer(RT_RxBuffer, RT_WRITE_READ_ADDR, RT_BUFFER_SIZE); + SRAM_ReadBuffer(RT_RxBuffer, RT_WRITE_READ_ADDR, RT_BUFFER_SIZE); - /* Read back SRAM memory and check content correctness */ + /* Read back SRAM memory and check content correctness */ for (Index = 0x00; (Index < RT_BUFFER_SIZE) && (WriteReadStatus == 0); Index++) { if (RT_RxBuffer[Index] != RT_TxBuffer[Index]) @@ -156,7 +156,7 @@ int sram_test(void) WriteReadStatus = Index + 1; } } - + if(WriteReadStatus == 0) { LOG_D("SRAM test success!"); @@ -165,7 +165,7 @@ int sram_test(void) { LOG_E("SRAM test failed!"); } - + return RT_EOK; } MSH_CMD_EXPORT(sram_test, sram test) diff --git a/bsp/at32/Libraries/rt_drivers/drv_sram.h b/bsp/at32/Libraries/rt_drivers/drv_sram.h index 05b07e4155..0f83c429d8 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_sram.h +++ b/bsp/at32/Libraries/rt_drivers/drv_sram.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/at32/Libraries/rt_drivers/drv_usart.c b/bsp/at32/Libraries/rt_drivers/drv_usart.c index 226d9afeda..04838bf2ac 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_usart.c +++ b/bsp/at32/Libraries/rt_drivers/drv_usart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,7 +15,7 @@ #if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && \ !defined(BSP_USING_UART3) #error "Please define at least one BSP_USING_UARTx" - /* this driver can be disabled at menuconfig RT-Thread Components Device Drivers */ + /* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */ #endif struct at32_usart { diff --git a/bsp/at32/Libraries/rt_drivers/drv_usart.h b/bsp/at32/Libraries/rt_drivers/drv_usart.h index 1002a6fd51..fc493d42da 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_usart.h +++ b/bsp/at32/Libraries/rt_drivers/drv_usart.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/at32/Libraries/rt_drivers/drv_wdt.c b/bsp/at32/Libraries/rt_drivers/drv_wdt.c index 8ab3de703d..0b304ad1ff 100644 --- a/bsp/at32/Libraries/rt_drivers/drv_wdt.c +++ b/bsp/at32/Libraries/rt_drivers/drv_wdt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/at32/at32f403a-start/applications/main.c b/bsp/at32/at32f403a-start/applications/main.c index cb63824e27..0234d32b04 100644 --- a/bsp/at32/at32f403a-start/applications/main.c +++ b/bsp/at32/at32f403a-start/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/at32/at32f403a-start/board/board.c b/bsp/at32/at32f403a-start/board/board.c index 4ce5bb3909..27b672b4da 100644 --- a/bsp/at32/at32f403a-start/board/board.c +++ b/bsp/at32/at32f403a-start/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-06 balanceTWK first version */ - + #include #include #include diff --git a/bsp/at32/at32f403a-start/board/board.h b/bsp/at32/at32f403a-start/board/board.h index 976863d3eb..1f2a4f3f3c 100644 --- a/bsp/at32/at32f403a-start/board/board.h +++ b/bsp/at32/at32f403a-start/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/at32/at32f403a-start/board/msp/at32_msp.c b/bsp/at32/at32f403a-start/board/msp/at32_msp.c index 76a5d42313..58b18fc026 100644 --- a/bsp/at32/at32f403a-start/board/msp/at32_msp.c +++ b/bsp/at32/at32f403a-start/board/msp/at32_msp.c @@ -184,34 +184,34 @@ void at32_msp_adc_init(void *Instance) GPIO_InitType GPIO_InitStruct; ADC_Type *ADCx = (ADC_Type *)Instance; -#ifdef BSP_USING_ADC1 +#ifdef BSP_USING_ADC1 if(ADCx == ADC1) - { + { /* ADC1 & GPIO clock enable */ RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_ADC1 | RCC_APB2PERIPH_GPIOA | RCC_APB2PERIPH_GPIOB | RCC_APB2PERIPH_GPIOC,ENABLE); - - /* Configure ADC Channel as analog input */ + + /* Configure ADC Channel as analog input */ GPIO_StructInit(&GPIO_InitStruct); GPIO_InitStruct.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_2 | GPIO_Pins_3 | GPIO_Pins_4 | GPIO_Pins_5; GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_ANALOG; GPIO_Init(GPIOC, &GPIO_InitStruct); - + } #endif -#ifdef BSP_USING_ADC2 +#ifdef BSP_USING_ADC2 if(ADCx == ADC2) { /* ADC2 & GPIO clock enable */ RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_ADC2 | RCC_APB2PERIPH_GPIOA | RCC_APB2PERIPH_GPIOB | RCC_APB2PERIPH_GPIOC,ENABLE); - - /* Configure ADC Channel as analog input */ + + /* Configure ADC Channel as analog input */ GPIO_StructInit(&GPIO_InitStruct); GPIO_InitStruct.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_2 | GPIO_Pins_3 | GPIO_Pins_4 | GPIO_Pins_5; GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_ANALOG; GPIO_Init(GPIOC, &GPIO_InitStruct); } -#endif +#endif } #endif /* BSP_USING_ADC */ @@ -226,7 +226,7 @@ void at32_msp_hwtmr_init(void *Instance) /* TMR3 clock enable */ RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_TMR3, ENABLE); } -#endif +#endif #ifdef BSP_USING_HWTMR4 if(TMRx == TMR4) diff --git a/bsp/at32/at32f403a-start/board/msp/system_at32f4xx.c b/bsp/at32/at32f403a-start/board/msp/system_at32f4xx.c index af88cd0a83..3635bda3de 100644 --- a/bsp/at32/at32f403a-start/board/msp/system_at32f4xx.c +++ b/bsp/at32/at32f403a-start/board/msp/system_at32f4xx.c @@ -57,23 +57,23 @@ Clock (MHz) PLL from HSE or HSI - SYSCLK HCLK PCLK2 PCLK1 - 24 24 24 24 - 36 36 36 36 - 48 48 48 24 - 56 56 56 28 - 72 72 72 36 - 96 96 48 48 - 108 108 54 54 - 120 120 60 60 - 144 144 72 72 - 150 150 75 75 - 168 168 84 84 - 176 176 88 88 - 192 192 96 96 - 200 200 100 100 - 224 224 112 112 - 240 240 120 120 + SYSCLK HCLK PCLK2 PCLK1 + 24 24 24 24 + 36 36 36 36 + 48 48 48 24 + 56 56 56 28 + 72 72 72 36 + 96 96 48 48 + 108 108 54 54 + 120 120 60 60 + 144 144 72 72 + 150 150 75 75 + 168 168 84 84 + 176 176 88 88 + 192 192 96 96 + 200 200 100 100 + 224 224 112 112 + 240 240 120 120 */ #if defined (AT32F403xx) || defined (AT32F413xx) || \ @@ -132,7 +132,7 @@ /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ @@ -562,7 +562,7 @@ static void SetSysClock(void) /** * @brief Setup the external memory controller. * Called in startup_at32f4xx_xx.s/.c before jump to main. - * This function configures the external SRAM mounted + * This function configures the external SRAM mounted * (AT32 High density devices). This SRAM will be used as program * data memory (including heap and stack). * @param None @@ -643,7 +643,7 @@ static void SetSysClockToHSE(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -663,7 +663,7 @@ static void SetSysClockToHSE(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -714,7 +714,7 @@ static void SetSysClockTo24M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -734,7 +734,7 @@ static void SetSysClockTo24M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -800,7 +800,7 @@ static void SetSysClockTo36M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -820,7 +820,7 @@ static void SetSysClockTo36M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -886,7 +886,7 @@ static void SetSysClockTo48M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -906,7 +906,7 @@ static void SetSysClockTo48M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -973,7 +973,7 @@ static void SetSysClockTo56M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -993,7 +993,7 @@ static void SetSysClockTo56M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -1060,7 +1060,7 @@ static void SetSysClockTo72M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1080,7 +1080,7 @@ static void SetSysClockTo72M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -1147,7 +1147,7 @@ static void SetSysClockTo96M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1167,7 +1167,7 @@ static void SetSysClockTo96M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -1238,7 +1238,7 @@ static void SetSysClockTo108M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1258,7 +1258,7 @@ static void SetSysClockTo108M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -1330,7 +1330,7 @@ static void SetSysClockTo120M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1350,7 +1350,7 @@ static void SetSysClockTo120M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -1429,7 +1429,7 @@ static void SetSysClockTo144M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1449,7 +1449,7 @@ static void SetSysClockTo144M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -1464,7 +1464,7 @@ static void SetSysClockTo144M(void) /* PLL configuration: PLLCLK = HSE * 18 = 144 MHz */ RCC->CFG &= RCC_CFG_PLLCFG_MASK; - + #if defined (AT32F415xx) RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT18); #else @@ -1528,7 +1528,7 @@ static void SetSysClockTo150M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1548,7 +1548,7 @@ static void SetSysClockTo150M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -1623,7 +1623,7 @@ static void SetSysClockTo168M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1709,7 +1709,7 @@ static void SetSysClockTo176M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1795,7 +1795,7 @@ static void SetSysClockTo192M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1881,7 +1881,7 @@ static void SetSysClockTo200M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1967,7 +1967,7 @@ static void SetSysClockTo224M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -2053,7 +2053,7 @@ static void SetSysClockTo240M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -2157,7 +2157,7 @@ static void SetSysClockTo24MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2237,7 +2237,7 @@ static void SetSysClockTo36MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2317,7 +2317,7 @@ static void SetSysClockTo48MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2397,7 +2397,7 @@ static void SetSysClockTo56MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2477,7 +2477,7 @@ static void SetSysClockTo72MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2557,7 +2557,7 @@ static void SetSysClockTo96MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2642,7 +2642,7 @@ static void SetSysClockTo108MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2727,7 +2727,7 @@ static void SetSysClockTo120MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2819,7 +2819,7 @@ static void SetSysClockTo144MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2911,7 +2911,7 @@ static void SetSysClockTo150MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -3443,4 +3443,4 @@ static void SetSysClockTo240MHSI(void) * @} */ -/******************* (C) COPYRIGHT 2018 ArteryTek *****END OF FILE****/ +/******************* (C) COPYRIGHT 2018 ArteryTek *****END OF FILE****/ diff --git a/bsp/at32/at32f407-start/applications/main.c b/bsp/at32/at32f407-start/applications/main.c index cb63824e27..0234d32b04 100644 --- a/bsp/at32/at32f407-start/applications/main.c +++ b/bsp/at32/at32f407-start/applications/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/at32/at32f407-start/board/board.c b/bsp/at32/at32f407-start/board/board.c index 4ce5bb3909..27b672b4da 100644 --- a/bsp/at32/at32f407-start/board/board.c +++ b/bsp/at32/at32f407-start/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018-11-06 balanceTWK first version */ - + #include #include #include diff --git a/bsp/at32/at32f407-start/board/board.h b/bsp/at32/at32f407-start/board/board.h index 976863d3eb..1f2a4f3f3c 100644 --- a/bsp/at32/at32f407-start/board/board.h +++ b/bsp/at32/at32f407-start/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/at32/at32f407-start/board/msp/at32_msp.c b/bsp/at32/at32f407-start/board/msp/at32_msp.c index 76a5d42313..58b18fc026 100644 --- a/bsp/at32/at32f407-start/board/msp/at32_msp.c +++ b/bsp/at32/at32f407-start/board/msp/at32_msp.c @@ -184,34 +184,34 @@ void at32_msp_adc_init(void *Instance) GPIO_InitType GPIO_InitStruct; ADC_Type *ADCx = (ADC_Type *)Instance; -#ifdef BSP_USING_ADC1 +#ifdef BSP_USING_ADC1 if(ADCx == ADC1) - { + { /* ADC1 & GPIO clock enable */ RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_ADC1 | RCC_APB2PERIPH_GPIOA | RCC_APB2PERIPH_GPIOB | RCC_APB2PERIPH_GPIOC,ENABLE); - - /* Configure ADC Channel as analog input */ + + /* Configure ADC Channel as analog input */ GPIO_StructInit(&GPIO_InitStruct); GPIO_InitStruct.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_2 | GPIO_Pins_3 | GPIO_Pins_4 | GPIO_Pins_5; GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_ANALOG; GPIO_Init(GPIOC, &GPIO_InitStruct); - + } #endif -#ifdef BSP_USING_ADC2 +#ifdef BSP_USING_ADC2 if(ADCx == ADC2) { /* ADC2 & GPIO clock enable */ RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_ADC2 | RCC_APB2PERIPH_GPIOA | RCC_APB2PERIPH_GPIOB | RCC_APB2PERIPH_GPIOC,ENABLE); - - /* Configure ADC Channel as analog input */ + + /* Configure ADC Channel as analog input */ GPIO_StructInit(&GPIO_InitStruct); GPIO_InitStruct.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_2 | GPIO_Pins_3 | GPIO_Pins_4 | GPIO_Pins_5; GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_ANALOG; GPIO_Init(GPIOC, &GPIO_InitStruct); } -#endif +#endif } #endif /* BSP_USING_ADC */ @@ -226,7 +226,7 @@ void at32_msp_hwtmr_init(void *Instance) /* TMR3 clock enable */ RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_TMR3, ENABLE); } -#endif +#endif #ifdef BSP_USING_HWTMR4 if(TMRx == TMR4) diff --git a/bsp/at32/at32f407-start/board/msp/system_at32f4xx.c b/bsp/at32/at32f407-start/board/msp/system_at32f4xx.c index c767c36b58..0df49349d4 100644 --- a/bsp/at32/at32f407-start/board/msp/system_at32f4xx.c +++ b/bsp/at32/at32f407-start/board/msp/system_at32f4xx.c @@ -57,23 +57,23 @@ Clock (MHz) PLL from HSE or HSI - SYSCLK HCLK PCLK2 PCLK1 - 24 24 24 24 - 36 36 36 36 - 48 48 48 24 - 56 56 56 28 - 72 72 72 36 - 96 96 48 48 - 108 108 54 54 - 120 120 60 60 - 144 144 72 72 - 150 150 75 75 - 168 168 84 84 - 176 176 88 88 - 192 192 96 96 - 200 200 100 100 - 224 224 112 112 - 240 240 120 120 + SYSCLK HCLK PCLK2 PCLK1 + 24 24 24 24 + 36 36 36 36 + 48 48 48 24 + 56 56 56 28 + 72 72 72 36 + 96 96 48 48 + 108 108 54 54 + 120 120 60 60 + 144 144 72 72 + 150 150 75 75 + 168 168 84 84 + 176 176 88 88 + 192 192 96 96 + 200 200 100 100 + 224 224 112 112 + 240 240 120 120 */ #if defined (AT32F403xx) || defined (AT32F413xx) || \ @@ -132,7 +132,7 @@ /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ @@ -562,7 +562,7 @@ static void SetSysClock(void) /** * @brief Setup the external memory controller. * Called in startup_at32f4xx_xx.s/.c before jump to main. - * This function configures the external SRAM mounted + * This function configures the external SRAM mounted * (AT32 High density devices). This SRAM will be used as program * data memory (including heap and stack). * @param None @@ -643,7 +643,7 @@ static void SetSysClockToHSE(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -663,7 +663,7 @@ static void SetSysClockToHSE(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -714,7 +714,7 @@ static void SetSysClockTo24M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -734,7 +734,7 @@ static void SetSysClockTo24M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -800,7 +800,7 @@ static void SetSysClockTo36M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -820,7 +820,7 @@ static void SetSysClockTo36M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -886,7 +886,7 @@ static void SetSysClockTo48M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -906,7 +906,7 @@ static void SetSysClockTo48M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -973,7 +973,7 @@ static void SetSysClockTo56M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -993,7 +993,7 @@ static void SetSysClockTo56M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -1060,7 +1060,7 @@ static void SetSysClockTo72M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1080,7 +1080,7 @@ static void SetSysClockTo72M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -1147,7 +1147,7 @@ static void SetSysClockTo96M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1167,7 +1167,7 @@ static void SetSysClockTo96M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -1238,7 +1238,7 @@ static void SetSysClockTo108M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1258,7 +1258,7 @@ static void SetSysClockTo108M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -1330,7 +1330,7 @@ static void SetSysClockTo120M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1350,7 +1350,7 @@ static void SetSysClockTo120M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -1429,7 +1429,7 @@ static void SetSysClockTo144M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1449,7 +1449,7 @@ static void SetSysClockTo144M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -1464,7 +1464,7 @@ static void SetSysClockTo144M(void) /* PLL configuration: PLLCLK = HSE * 18 = 144 MHz */ RCC->CFG &= RCC_CFG_PLLCFG_MASK; - + #if defined (AT32F415xx) RCC->CFG |= (uint32_t)(RCC_CFG_PLLRC_HSE | RCC_CFG_PLLMULT18); #else @@ -1528,7 +1528,7 @@ static void SetSysClockTo150M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1548,7 +1548,7 @@ static void SetSysClockTo150M(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -1623,7 +1623,7 @@ static void SetSysClockTo168M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1709,7 +1709,7 @@ static void SetSysClockTo176M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1795,7 +1795,7 @@ static void SetSysClockTo192M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1881,7 +1881,7 @@ static void SetSysClockTo200M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -1967,7 +1967,7 @@ static void SetSysClockTo224M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -2053,7 +2053,7 @@ static void SetSysClockTo240M(void) StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); -#ifdef AT32F403xx +#ifdef AT32F403xx WaitHseStbl(HSE_STABLE_DELAY); #endif if ((RCC->CTRL & RCC_CTRL_HSESTBL) != RESET) @@ -2157,7 +2157,7 @@ static void SetSysClockTo24MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2237,7 +2237,7 @@ static void SetSysClockTo36MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2317,7 +2317,7 @@ static void SetSysClockTo48MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2397,7 +2397,7 @@ static void SetSysClockTo56MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2477,7 +2477,7 @@ static void SetSysClockTo72MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2557,7 +2557,7 @@ static void SetSysClockTo96MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2642,7 +2642,7 @@ static void SetSysClockTo108MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2727,7 +2727,7 @@ static void SetSysClockTo120MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2819,7 +2819,7 @@ static void SetSysClockTo144MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -2911,7 +2911,7 @@ static void SetSysClockTo150MHSI(void) /* Flash 1 wait state */ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4; #endif /* HCLK = SYSCLK */ RCC->CFG |= (uint32_t)RCC_CFG_AHBPSC_DIV1; @@ -3443,4 +3443,4 @@ static void SetSysClockTo240MHSI(void) * @} */ -/******************* (C) COPYRIGHT 2018 ArteryTek *****END OF FILE****/ +/******************* (C) COPYRIGHT 2018 ArteryTek *****END OF FILE****/ diff --git a/bsp/at91sam9260/applications/application.c b/bsp/at91sam9260/applications/application.c index 48c526957a..f1a377e1e9 100644 --- a/bsp/at91sam9260/applications/application.c +++ b/bsp/at91sam9260/applications/application.c @@ -1,25 +1,11 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ /** @@ -48,106 +34,106 @@ static int rt_led_app_init(void); int main(void) { - int timeout = 0; + int timeout = 0; /* Filesystem Initialization */ #ifdef RT_USING_DFS - { + { #if defined(RT_USING_DFS_ROMFS) - if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0) - { - rt_kprintf("ROM File System initialized!\n"); - } - else - rt_kprintf("ROM File System initialzation failed!\n"); + if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0) + { + rt_kprintf("ROM File System initialized!\n"); + } + else + rt_kprintf("ROM File System initialzation failed!\n"); #endif #if defined(RT_USING_DFS_UFFS) - { - /* mount flash device as flash directory */ - if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0) - rt_kprintf("UFFS File System initialized!\n"); - else - rt_kprintf("UFFS File System initialzation failed!\n"); - } + { + /* mount flash device as flash directory */ + if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0) + rt_kprintf("UFFS File System initialized!\n"); + else + rt_kprintf("UFFS File System initialzation failed!\n"); + } #endif #ifdef RT_USING_SDIO - timeout = 0; - while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2)) - { - rt_thread_delay(1); - } + timeout = 0; + while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2)) + { + rt_thread_delay(1); + } - if (timeout < RT_TICK_PER_SECOND*2) - { - /* mount sd card fat partition 1 as root directory */ - if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) - { - rt_kprintf("File System initialized!\n"); - } - else - rt_kprintf("File System initialzation failed!%d\n", rt_get_errno()); - } - else - { - rt_kprintf("No SD card found.\n"); - } + if (timeout < RT_TICK_PER_SECOND*2) + { + /* mount sd card fat partition 1 as root directory */ + if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) + { + rt_kprintf("File System initialized!\n"); + } + else + rt_kprintf("File System initialzation failed!%d\n", rt_get_errno()); + } + else + { + rt_kprintf("No SD card found.\n"); + } #endif - } + } #endif - + #ifdef RT_USING_LED - rt_led_app_init(); + rt_led_app_init(); #endif } #ifdef RT_USING_LED void rt_led_thread_entry(void* parameter) { - rt_uint8_t cnt = 0; - led_init(); - while(1) - { - /* light on leds for one second */ - rt_thread_delay(40); - cnt++; - if (cnt&0x01) - led_on(1); - else - led_off(1); - if (cnt&0x02) - led_on(2); - else - led_off(2); - if (cnt&0x04) - led_on(3); - else - led_off(3); - } + rt_uint8_t cnt = 0; + led_init(); + while(1) + { + /* light on leds for one second */ + rt_thread_delay(40); + cnt++; + if (cnt&0x01) + led_on(1); + else + led_off(1); + if (cnt&0x02) + led_on(2); + else + led_off(2); + if (cnt&0x04) + led_on(3); + else + led_off(3); + } } #endif static int rt_led_app_init(void) { #ifdef RT_USING_LED - rt_thread_t led_thread; + rt_thread_t led_thread; #if (RT_THREAD_PRIORITY_MAX == 32) - led_thread = rt_thread_create("led", - rt_led_thread_entry, RT_NULL, - 512, 20, 20); + led_thread = rt_thread_create("led", + rt_led_thread_entry, RT_NULL, + 512, 20, 20); #else - led_thread = rt_thread_create("led", - rt_led_thread_entry, RT_NULL, - 512, 200, 20); + led_thread = rt_thread_create("led", + rt_led_thread_entry, RT_NULL, + 512, 200, 20); #endif - if(led_thread != RT_NULL) - rt_thread_startup(led_thread); + if(led_thread != RT_NULL) + rt_thread_startup(led_thread); #endif - return 0; + return 0; } /* NFSv3 Initialization */ @@ -155,14 +141,14 @@ static int rt_led_app_init(void) #include void nfs_start(void) { - nfs_init(); + nfs_init(); - if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0) - { - rt_kprintf("NFSv3 File System initialized!\n"); - } - else - rt_kprintf("NFSv3 File System initialzation failed!\n"); + if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0) + { + rt_kprintf("NFSv3 File System initialized!\n"); + } + else + rt_kprintf("NFSv3 File System initialzation failed!\n"); } #include "finsh.h" diff --git a/bsp/at91sam9260/drivers/at91_i2c_gpio.c b/bsp/at91sam9260/drivers/at91_i2c_gpio.c index 1c11f4ad79..d863ffed88 100644 --- a/bsp/at91sam9260/drivers/at91_i2c_gpio.c +++ b/bsp/at91sam9260/drivers/at91_i2c_gpio.c @@ -1,25 +1,11 @@ /* - * File : at91_i2c_gpio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2012-04-25 weety first version + * Date Author Notes + * 2012-04-25 weety first version */ #include @@ -29,101 +15,101 @@ static void at91_i2c_gpio_init() { - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA); //enable PIOA clock - at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 23)); - at91_sys_write(AT91_PIOA + PIO_PER, (1 << 23)); - at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 23)); - at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 24)); - at91_sys_write(AT91_PIOA + PIO_PER, (1 << 24)); - at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 24)); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA); //enable PIOA clock + at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 23)); + at91_sys_write(AT91_PIOA + PIO_PER, (1 << 23)); + at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 23)); + at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 24)); + at91_sys_write(AT91_PIOA + PIO_PER, (1 << 24)); + at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 24)); - at91_sys_write(AT91_PIOA + PIO_OER, (1 << 23)); - at91_sys_write(AT91_PIOA + PIO_OER, (1 << 24)); + at91_sys_write(AT91_PIOA + PIO_OER, (1 << 23)); + at91_sys_write(AT91_PIOA + PIO_OER, (1 << 24)); - at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23)); - at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24)); + at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23)); + at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24)); } static void at91_set_sda(void *data, rt_int32_t state) { - if (state) - { - at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23)); - } - else - { - at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 23)); - } + if (state) + { + at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23)); + } + else + { + at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 23)); + } } static void at91_set_scl(void *data, rt_int32_t state) { - if (state) - { - at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24)); - } - else - { - at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 24)); - } + if (state) + { + at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24)); + } + else + { + at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 24)); + } } static rt_int32_t at91_get_sda(void *data) { - return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 23); + return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 23); } static rt_int32_t at91_get_scl(void *data) { - return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 24); + return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 24); } static void at91_udelay (rt_uint32_t us) { - rt_int32_t i; - for (; us > 0; us--) - { - i = 50000; - while(i > 0) - { - i--; - } - } + rt_int32_t i; + for (; us > 0; us--) + { + i = 50000; + while(i > 0) + { + i--; + } + } } static const struct rt_i2c_bit_ops bit_ops = { - RT_NULL, - at91_set_sda, - at91_set_scl, - at91_get_sda, - at91_get_scl, - - at91_udelay, + RT_NULL, + at91_set_sda, + at91_set_scl, + at91_get_sda, + at91_get_scl, - 5, - 100 + at91_udelay, + + 5, + 100 }; int at91_i2c_init(void) { - struct rt_i2c_bus_device *bus; + struct rt_i2c_bus_device *bus; - bus = rt_malloc(sizeof(struct rt_i2c_bus_device)); - if (bus == RT_NULL) - { - rt_kprintf("rt_malloc failed\n"); - return -RT_ENOMEM; - } - - rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device)); + bus = rt_malloc(sizeof(struct rt_i2c_bus_device)); + if (bus == RT_NULL) + { + rt_kprintf("rt_malloc failed\n"); + return -RT_ENOMEM; + } - bus->priv = (void *)&bit_ops; + rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device)); - at91_i2c_gpio_init(); + bus->priv = (void *)&bit_ops; - rt_i2c_bit_add_bus(bus, "i2c0"); + at91_i2c_gpio_init(); - return 0; + rt_i2c_bit_add_bus(bus, "i2c0"); + + return 0; } INIT_DEVICE_EXPORT(at91_i2c_init); diff --git a/bsp/at91sam9260/drivers/at91_mci.c b/bsp/at91sam9260/drivers/at91_mci.c index 25d408810c..92f7abdfec 100644 --- a/bsp/at91sam9260/drivers/at91_mci.c +++ b/bsp/at91sam9260/drivers/at91_mci.c @@ -1,25 +1,11 @@ /* - * File : at91_mci.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-07-25 weety first version + * Date Author Notes + * 2011-07-25 weety first version */ #include @@ -37,32 +23,32 @@ #define mci_dbg(fmt, ...) #endif -#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31)) +#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31)) extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size); extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); -#define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \ - | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \ - | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE) +#define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \ + | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \ + | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE) -#define at91_mci_read(reg) readl(AT91SAM9260_BASE_MCI + (reg)) -#define at91_mci_write(reg, val) writel((val), AT91SAM9260_BASE_MCI + (reg)) +#define at91_mci_read(reg) readl(AT91SAM9260_BASE_MCI + (reg)) +#define at91_mci_write(reg, val) writel((val), AT91SAM9260_BASE_MCI + (reg)) -#define REQ_ST_INIT (1U << 0) -#define REQ_ST_CMD (1U << 1) -#define REQ_ST_STOP (1U << 2) +#define REQ_ST_INIT (1U << 0) +#define REQ_ST_CMD (1U << 1) +#define REQ_ST_STOP (1U << 2) struct at91_mci { - struct rt_mmcsd_host *host; - struct rt_mmcsd_req *req; - struct rt_mmcsd_cmd *cmd; - struct rt_timer timer; - //struct rt_semaphore sem_ack; - rt_uint32_t *buf; - rt_uint32_t current_status; + struct rt_mmcsd_host *host; + struct rt_mmcsd_req *req; + struct rt_mmcsd_cmd *cmd; + struct rt_timer timer; + //struct rt_semaphore sem_ack; + rt_uint32_t *buf; + rt_uint32_t current_status; }; /* @@ -70,36 +56,36 @@ struct at91_mci { */ static void at91_reset_host() { - rt_uint32_t mr; - rt_uint32_t sdcr; - rt_uint32_t dtor; - rt_uint32_t imr; - rt_uint32_t level; + rt_uint32_t mr; + rt_uint32_t sdcr; + rt_uint32_t dtor; + rt_uint32_t imr; + rt_uint32_t level; - level = rt_hw_interrupt_disable(); + level = rt_hw_interrupt_disable(); - imr = at91_mci_read(AT91_MCI_IMR); + imr = at91_mci_read(AT91_MCI_IMR); - at91_mci_write(AT91_MCI_IDR, 0xffffffff); + at91_mci_write(AT91_MCI_IDR, 0xffffffff); - /* save current state */ - mr = at91_mci_read(AT91_MCI_MR) & 0x7fff; - sdcr = at91_mci_read(AT91_MCI_SDCR); - dtor = at91_mci_read(AT91_MCI_DTOR); + /* save current state */ + mr = at91_mci_read(AT91_MCI_MR) & 0x7fff; + sdcr = at91_mci_read(AT91_MCI_SDCR); + dtor = at91_mci_read(AT91_MCI_DTOR); - /* reset the controller */ - at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); + /* reset the controller */ + at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); - /* restore state */ - at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN); - at91_mci_write(AT91_MCI_MR, mr); - at91_mci_write(AT91_MCI_SDCR, sdcr); - at91_mci_write(AT91_MCI_DTOR, dtor); - at91_mci_write(AT91_MCI_IER, imr); + /* restore state */ + at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN); + at91_mci_write(AT91_MCI_MR, mr); + at91_mci_write(AT91_MCI_SDCR, sdcr); + at91_mci_write(AT91_MCI_DTOR, dtor); + at91_mci_write(AT91_MCI_IER, imr); - /* make sure sdio interrupts will fire */ - at91_mci_read(AT91_MCI_SR); - rt_hw_interrupt_enable(level); + /* make sure sdio interrupts will fire */ + at91_mci_read(AT91_MCI_SR); + rt_hw_interrupt_enable(level); } @@ -109,19 +95,19 @@ static void at91_reset_host() */ static void at91_mci_enable() { - rt_uint32_t mr; + rt_uint32_t mr; - at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN); - at91_mci_write(AT91_MCI_IDR, 0xffffffff); - at91_mci_write(AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC); - mr = AT91_MCI_PDCMODE | 0x34a; + at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN); + at91_mci_write(AT91_MCI_IDR, 0xffffffff); + at91_mci_write(AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC); + mr = AT91_MCI_PDCMODE | 0x34a; - mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF; + mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF; - at91_mci_write(AT91_MCI_MR, mr); + at91_mci_write(AT91_MCI_MR, mr); - /* use Slot A or B (only one at same time) */ - at91_mci_write(AT91_MCI_SDCR, 1); /* use slot b */ + /* use Slot A or B (only one at same time) */ + at91_mci_write(AT91_MCI_SDCR, 1); /* use slot b */ } /* @@ -129,39 +115,39 @@ static void at91_mci_enable() */ static void at91_mci_disable() { - at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); + at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST); } static void at91_timeout_timer(void *data) { - struct at91_mci *mci; + struct at91_mci *mci; - mci = (struct at91_mci *)data; + mci = (struct at91_mci *)data; - if (mci->req) - { - rt_kprintf("Timeout waiting end of packet\n"); + if (mci->req) + { + rt_kprintf("Timeout waiting end of packet\n"); - if (mci->current_status == REQ_ST_CMD) - { - if (mci->req->cmd && mci->req->data) - { - mci->req->data->err = -RT_ETIMEOUT; - } - else - { - if (mci->req->cmd) - mci->req->cmd->err = -RT_ETIMEOUT; - } - } - else if (mci->current_status == REQ_ST_STOP) - { - mci->req->stop->err = -RT_ETIMEOUT; - } + if (mci->current_status == REQ_ST_CMD) + { + if (mci->req->cmd && mci->req->data) + { + mci->req->data->err = -RT_ETIMEOUT; + } + else + { + if (mci->req->cmd) + mci->req->cmd->err = -RT_ETIMEOUT; + } + } + else if (mci->current_status == REQ_ST_STOP) + { + mci->req->stop->err = -RT_ETIMEOUT; + } - at91_reset_host(); - mmcsd_req_complete(mci->host); - } + at91_reset_host(); + mmcsd_req_complete(mci->host); + } } /* @@ -169,62 +155,62 @@ static void at91_timeout_timer(void *data) */ static void at91_mci_init_dma_read(struct at91_mci *mci) { - rt_uint8_t i; - struct rt_mmcsd_cmd *cmd; - struct rt_mmcsd_data *data; - rt_uint32_t length; + rt_uint8_t i; + struct rt_mmcsd_cmd *cmd; + struct rt_mmcsd_data *data; + rt_uint32_t length; - mci_dbg("pre dma read\n"); + mci_dbg("pre dma read\n"); - cmd = mci->cmd; - if (!cmd) - { - mci_dbg("no command\n"); - return; - } + cmd = mci->cmd; + if (!cmd) + { + mci_dbg("no command\n"); + return; + } - data = cmd->data; - if (!data) - { - mci_dbg("no data\n"); - return; - } + data = cmd->data; + if (!data) + { + mci_dbg("no data\n"); + return; + } - for (i = 0; i < 1; i++) - { - /* Check to see if this needs filling */ - if (i == 0) - { - if (at91_mci_read(AT91_PDC_RCR) != 0) - { - mci_dbg("Transfer active in current\n"); - continue; - } - } - else { - if (at91_mci_read(AT91_PDC_RNCR) != 0) - { - mci_dbg("Transfer active in next\n"); - continue; - } - } + for (i = 0; i < 1; i++) + { + /* Check to see if this needs filling */ + if (i == 0) + { + if (at91_mci_read(AT91_PDC_RCR) != 0) + { + mci_dbg("Transfer active in current\n"); + continue; + } + } + else { + if (at91_mci_read(AT91_PDC_RNCR) != 0) + { + mci_dbg("Transfer active in next\n"); + continue; + } + } - length = data->blksize * data->blks; - mci_dbg("dma address = %08X, length = %d\n", data->buf, length); + length = data->blksize * data->blks; + mci_dbg("dma address = %08X, length = %d\n", data->buf, length); - if (i == 0) - { - at91_mci_write(AT91_PDC_RPR, (rt_uint32_t)(data->buf)); - at91_mci_write(AT91_PDC_RCR, (data->blksize & 0x3) ? length : length / 4); - } - else - { - at91_mci_write(AT91_PDC_RNPR, (rt_uint32_t)(data->buf)); - at91_mci_write(AT91_PDC_RNCR, (data->blksize & 0x3) ? length : length / 4); - } - } + if (i == 0) + { + at91_mci_write(AT91_PDC_RPR, (rt_uint32_t)(data->buf)); + at91_mci_write(AT91_PDC_RCR, (data->blksize & 0x3) ? length : length / 4); + } + else + { + at91_mci_write(AT91_PDC_RNPR, (rt_uint32_t)(data->buf)); + at91_mci_write(AT91_PDC_RNCR, (data->blksize & 0x3) ? length : length / 4); + } + } - mci_dbg("pre dma read done\n"); + mci_dbg("pre dma read done\n"); } /* @@ -232,185 +218,185 @@ static void at91_mci_init_dma_read(struct at91_mci *mci) */ static void at91_mci_send_command(struct at91_mci *mci, struct rt_mmcsd_cmd *cmd) { - rt_uint32_t cmdr, mr; - rt_uint32_t block_length; - struct rt_mmcsd_data *data = cmd->data; - struct rt_mmcsd_host *host = mci->host; + rt_uint32_t cmdr, mr; + rt_uint32_t block_length; + struct rt_mmcsd_data *data = cmd->data; + struct rt_mmcsd_host *host = mci->host; - rt_uint32_t blocks; - rt_uint32_t ier = 0; - rt_uint32_t length; + rt_uint32_t blocks; + rt_uint32_t ier = 0; + rt_uint32_t length; - mci->cmd = cmd; + mci->cmd = cmd; - /* Needed for leaving busy state before CMD1 */ - if ((at91_mci_read(AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->cmd_code == 1)) - { - mci_dbg("Clearing timeout\n"); - at91_mci_write(AT91_MCI_ARGR, 0); - at91_mci_write(AT91_MCI_CMDR, AT91_MCI_OPDCMD); - while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY)) - { - /* spin */ - mci_dbg("Clearing: SR = %08X\n", at91_mci_read(AT91_MCI_SR)); - } - } + /* Needed for leaving busy state before CMD1 */ + if ((at91_mci_read(AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->cmd_code == 1)) + { + mci_dbg("Clearing timeout\n"); + at91_mci_write(AT91_MCI_ARGR, 0); + at91_mci_write(AT91_MCI_CMDR, AT91_MCI_OPDCMD); + while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY)) + { + /* spin */ + mci_dbg("Clearing: SR = %08X\n", at91_mci_read(AT91_MCI_SR)); + } + } - cmdr = cmd->cmd_code; + cmdr = cmd->cmd_code; - if (resp_type(cmd) == RESP_NONE) - cmdr |= AT91_MCI_RSPTYP_NONE; - else - { - /* if a response is expected then allow maximum response latancy */ - cmdr |= AT91_MCI_MAXLAT; - /* set 136 bit response for R2, 48 bit response otherwise */ - if (resp_type(cmd) == RESP_R2) - cmdr |= AT91_MCI_RSPTYP_136; - else - cmdr |= AT91_MCI_RSPTYP_48; - } + if (resp_type(cmd) == RESP_NONE) + cmdr |= AT91_MCI_RSPTYP_NONE; + else + { + /* if a response is expected then allow maximum response latancy */ + cmdr |= AT91_MCI_MAXLAT; + /* set 136 bit response for R2, 48 bit response otherwise */ + if (resp_type(cmd) == RESP_R2) + cmdr |= AT91_MCI_RSPTYP_136; + else + cmdr |= AT91_MCI_RSPTYP_48; + } - if (data) - { + if (data) + { - block_length = data->blksize; - blocks = data->blks; + block_length = data->blksize; + blocks = data->blks; - /* always set data start - also set direction flag for read */ - if (data->flags & DATA_DIR_READ) - cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START); - else if (data->flags & DATA_DIR_WRITE) - cmdr |= AT91_MCI_TRCMD_START; + /* always set data start - also set direction flag for read */ + if (data->flags & DATA_DIR_READ) + cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START); + else if (data->flags & DATA_DIR_WRITE) + cmdr |= AT91_MCI_TRCMD_START; - if (data->flags & DATA_STREAM) - cmdr |= AT91_MCI_TRTYP_STREAM; - if (data->blks > 1) - cmdr |= AT91_MCI_TRTYP_MULTIPLE; - } - else - { - block_length = 0; - blocks = 0; - } + if (data->flags & DATA_STREAM) + cmdr |= AT91_MCI_TRTYP_STREAM; + if (data->blks > 1) + cmdr |= AT91_MCI_TRTYP_MULTIPLE; + } + else + { + block_length = 0; + blocks = 0; + } - /*if (cmd->cmd_code == GO_IDLE_STATE) - { - cmdr |= AT91_MCI_SPCMD_INIT; - }*/ + /*if (cmd->cmd_code == GO_IDLE_STATE) + { + cmdr |= AT91_MCI_SPCMD_INIT; + }*/ - if (cmd->cmd_code == STOP_TRANSMISSION) - cmdr |= AT91_MCI_TRCMD_STOP; + if (cmd->cmd_code == STOP_TRANSMISSION) + cmdr |= AT91_MCI_TRCMD_STOP; - if (host->io_cfg.bus_mode == MMCSD_BUSMODE_OPENDRAIN) - cmdr |= AT91_MCI_OPDCMD; + if (host->io_cfg.bus_mode == MMCSD_BUSMODE_OPENDRAIN) + cmdr |= AT91_MCI_OPDCMD; - /* - * Set the arguments and send the command - */ - mci_dbg("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n", - cmd->cmd_code, cmdr, cmd->arg, blocks, block_length, at91_mci_read(AT91_MCI_MR)); + /* + * Set the arguments and send the command + */ + mci_dbg("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n", + cmd->cmd_code, cmdr, cmd->arg, blocks, block_length, at91_mci_read(AT91_MCI_MR)); - if (!data) - { - at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTDIS | AT91_PDC_RXTDIS); - at91_mci_write(AT91_PDC_RPR, 0); - at91_mci_write(AT91_PDC_RCR, 0); - at91_mci_write(AT91_PDC_RNPR, 0); - at91_mci_write(AT91_PDC_RNCR, 0); - at91_mci_write(AT91_PDC_TPR, 0); - at91_mci_write(AT91_PDC_TCR, 0); - at91_mci_write(AT91_PDC_TNPR, 0); - at91_mci_write(AT91_PDC_TNCR, 0); - ier = AT91_MCI_CMDRDY; - } - else - { - /* zero block length and PDC mode */ - mr = at91_mci_read(AT91_MCI_MR) & 0x5fff; - mr |= (data->blksize & 0x3) ? AT91_MCI_PDCFBYTE : 0; - mr |= (block_length << 16); - mr |= AT91_MCI_PDCMODE; - at91_mci_write(AT91_MCI_MR, mr); + if (!data) + { + at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTDIS | AT91_PDC_RXTDIS); + at91_mci_write(AT91_PDC_RPR, 0); + at91_mci_write(AT91_PDC_RCR, 0); + at91_mci_write(AT91_PDC_RNPR, 0); + at91_mci_write(AT91_PDC_RNCR, 0); + at91_mci_write(AT91_PDC_TPR, 0); + at91_mci_write(AT91_PDC_TCR, 0); + at91_mci_write(AT91_PDC_TNPR, 0); + at91_mci_write(AT91_PDC_TNCR, 0); + ier = AT91_MCI_CMDRDY; + } + else + { + /* zero block length and PDC mode */ + mr = at91_mci_read(AT91_MCI_MR) & 0x5fff; + mr |= (data->blksize & 0x3) ? AT91_MCI_PDCFBYTE : 0; + mr |= (block_length << 16); + mr |= AT91_MCI_PDCMODE; + at91_mci_write(AT91_MCI_MR, mr); - at91_mci_write(AT91_MCI_BLKR, - AT91_MCI_BLKR_BCNT(blocks) | - AT91_MCI_BLKR_BLKLEN(block_length)); + at91_mci_write(AT91_MCI_BLKR, + AT91_MCI_BLKR_BCNT(blocks) | + AT91_MCI_BLKR_BLKLEN(block_length)); - /* - * Disable the PDC controller - */ - at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS); + /* + * Disable the PDC controller + */ + at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS); - if (cmdr & AT91_MCI_TRCMD_START) - { - if (cmdr & AT91_MCI_TRDIR) - { - /* - * Handle a read - */ + if (cmdr & AT91_MCI_TRCMD_START) + { + if (cmdr & AT91_MCI_TRDIR) + { + /* + * Handle a read + */ - mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blksize*data->blks); - at91_mci_init_dma_read(mci); - ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */; - } - else - { - /* - * Handle a write - */ - length = block_length * blocks; - /* - * at91mci MCI1 rev2xx Data Write Operation and - * number of bytes erratum - */ - if (length < 12) - { - length = 12; - mci->buf = rt_malloc(length); - if (!mci->buf) - { - rt_kprintf("rt alloc tx buffer failed\n"); - cmd->err = -RT_ENOMEM; - mmcsd_req_complete(mci->host); - return; - } - rt_memset(mci->buf, 0, 12); - rt_memcpy(mci->buf, data->buf, length); - mmu_clean_dcache((rt_uint32_t)mci->buf, length); - at91_mci_write(AT91_PDC_TPR, (rt_uint32_t)(mci->buf)); - at91_mci_write(AT91_PDC_TCR, (data->blksize & 0x3) ? - length : length / 4); - } - else - { - mmu_clean_dcache((rt_uint32_t)data->buf, data->blksize*data->blks); - at91_mci_write(AT91_PDC_TPR, (rt_uint32_t)(data->buf)); - at91_mci_write(AT91_PDC_TCR, (data->blksize & 0x3) ? - length : length / 4); - } - mci_dbg("Transmitting %d bytes\n", length); - ier = AT91_MCI_CMDRDY; - } - } - } + mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blksize*data->blks); + at91_mci_init_dma_read(mci); + ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */; + } + else + { + /* + * Handle a write + */ + length = block_length * blocks; + /* + * at91mci MCI1 rev2xx Data Write Operation and + * number of bytes erratum + */ + if (length < 12) + { + length = 12; + mci->buf = rt_malloc(length); + if (!mci->buf) + { + rt_kprintf("rt alloc tx buffer failed\n"); + cmd->err = -RT_ENOMEM; + mmcsd_req_complete(mci->host); + return; + } + rt_memset(mci->buf, 0, 12); + rt_memcpy(mci->buf, data->buf, length); + mmu_clean_dcache((rt_uint32_t)mci->buf, length); + at91_mci_write(AT91_PDC_TPR, (rt_uint32_t)(mci->buf)); + at91_mci_write(AT91_PDC_TCR, (data->blksize & 0x3) ? + length : length / 4); + } + else + { + mmu_clean_dcache((rt_uint32_t)data->buf, data->blksize*data->blks); + at91_mci_write(AT91_PDC_TPR, (rt_uint32_t)(data->buf)); + at91_mci_write(AT91_PDC_TCR, (data->blksize & 0x3) ? + length : length / 4); + } + mci_dbg("Transmitting %d bytes\n", length); + ier = AT91_MCI_CMDRDY; + } + } + } - /* - * Send the command and then enable the PDC - not the other way round as - * the data sheet says - */ + /* + * Send the command and then enable the PDC - not the other way round as + * the data sheet says + */ - at91_mci_write(AT91_MCI_ARGR, cmd->arg); - at91_mci_write(AT91_MCI_CMDR, cmdr); + at91_mci_write(AT91_MCI_ARGR, cmd->arg); + at91_mci_write(AT91_MCI_CMDR, cmdr); - if (cmdr & AT91_MCI_TRCMD_START) - { - if (cmdr & AT91_MCI_TRDIR) - at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTEN); - } + if (cmdr & AT91_MCI_TRCMD_START) + { + if (cmdr & AT91_MCI_TRDIR) + at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTEN); + } - /* Enable selected interrupts */ - at91_mci_write(AT91_MCI_IER, AT91_MCI_ERRORS | ier); + /* Enable selected interrupts */ + at91_mci_write(AT91_MCI_IER, AT91_MCI_ERRORS | ier); } /* @@ -418,25 +404,25 @@ static void at91_mci_send_command(struct at91_mci *mci, struct rt_mmcsd_cmd *cmd */ static void at91_mci_process_next(struct at91_mci *mci) { - if (mci->current_status == REQ_ST_INIT) - { - mci->current_status = REQ_ST_CMD; - at91_mci_send_command(mci, mci->req->cmd); - } - else if ((mci->current_status == REQ_ST_CMD) && mci->req->stop) - { - mci->current_status = REQ_ST_STOP; - at91_mci_send_command(mci, mci->req->stop); - } - else - { - rt_timer_stop(&mci->timer); - /* the mci controller hangs after some transfers, - * and the workaround is to reset it after each transfer. - */ - at91_reset_host(); - mmcsd_req_complete(mci->host); - } + if (mci->current_status == REQ_ST_INIT) + { + mci->current_status = REQ_ST_CMD; + at91_mci_send_command(mci, mci->req->cmd); + } + else if ((mci->current_status == REQ_ST_CMD) && mci->req->stop) + { + mci->current_status = REQ_ST_STOP; + at91_mci_send_command(mci, mci->req->stop); + } + else + { + rt_timer_stop(&mci->timer); + /* the mci controller hangs after some transfers, + * and the workaround is to reset it after each transfer. + */ + at91_reset_host(); + mmcsd_req_complete(mci->host); + } } /* @@ -444,15 +430,15 @@ static void at91_mci_process_next(struct at91_mci *mci) */ static void at91_mci_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) { - rt_uint32_t timeout = RT_TICK_PER_SECOND; - struct at91_mci *mci = host->private_data; - mci->req = req; - mci->current_status = REQ_ST_INIT; + rt_uint32_t timeout = RT_TICK_PER_SECOND; + struct at91_mci *mci = host->private_data; + mci->req = req; + mci->current_status = REQ_ST_INIT; - rt_timer_control(&mci->timer, RT_TIMER_CTRL_SET_TIME, (void*)&timeout); - rt_timer_start(&mci->timer); + rt_timer_control(&mci->timer, RT_TIMER_CTRL_SET_TIME, (void*)&timeout); + rt_timer_start(&mci->timer); - at91_mci_process_next(mci); + at91_mci_process_next(mci); } /* @@ -460,29 +446,29 @@ static void at91_mci_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *re */ static void at91_mci_handle_transmitted(struct at91_mci *mci) { - struct rt_mmcsd_cmd *cmd; - struct rt_mmcsd_data *data; + struct rt_mmcsd_cmd *cmd; + struct rt_mmcsd_data *data; - mci_dbg("Handling the transmit\n"); + mci_dbg("Handling the transmit\n"); - /* Disable the transfer */ - at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS); + /* Disable the transfer */ + at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS); - /* Now wait for cmd ready */ - at91_mci_write(AT91_MCI_IDR, AT91_MCI_TXBUFE); + /* Now wait for cmd ready */ + at91_mci_write(AT91_MCI_IDR, AT91_MCI_TXBUFE); - cmd = mci->cmd; - if (!cmd) return; + cmd = mci->cmd; + if (!cmd) return; - data = cmd->data; - if (!data) return; + data = cmd->data; + if (!data) return; - if (data->blks > 1) - { - mci_dbg("multiple write : wait for BLKE...\n"); - at91_mci_write(AT91_MCI_IER, AT91_MCI_BLKE); - } else - at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY); + if (data->blks > 1) + { + mci_dbg("multiple write : wait for BLKE...\n"); + at91_mci_write(AT91_MCI_IER, AT91_MCI_BLKE); + } else + at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY); } @@ -491,54 +477,54 @@ static void at91_mci_handle_transmitted(struct at91_mci *mci) */ static void at91_mci_post_dma_read(struct at91_mci *mci) { - struct rt_mmcsd_cmd *cmd; - struct rt_mmcsd_data *data; + struct rt_mmcsd_cmd *cmd; + struct rt_mmcsd_data *data; - mci_dbg("post dma read\n"); + mci_dbg("post dma read\n"); - cmd = mci->cmd; - if (!cmd) - { - mci_dbg("no command\n"); - return; - } + cmd = mci->cmd; + if (!cmd) + { + mci_dbg("no command\n"); + return; + } - data = cmd->data; - if (!data) - { - mci_dbg("no data\n"); - return; - } + data = cmd->data; + if (!data) + { + mci_dbg("no data\n"); + return; + } - at91_mci_write(AT91_MCI_IDR, AT91_MCI_ENDRX); - at91_mci_write(AT91_MCI_IER, AT91_MCI_RXBUFF); + at91_mci_write(AT91_MCI_IDR, AT91_MCI_ENDRX); + at91_mci_write(AT91_MCI_IER, AT91_MCI_RXBUFF); - mci_dbg("post dma read done\n"); + mci_dbg("post dma read done\n"); } /*Handle after command sent ready*/ static int at91_mci_handle_cmdrdy(struct at91_mci *mci) { - if (!mci->cmd) - return 1; - else if (!mci->cmd->data) - { - if (mci->current_status == REQ_ST_STOP) - { - /*After multi block write, we must wait for NOTBUSY*/ - at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY); - } - else return 1; - } - else if (mci->cmd->data->flags & DATA_DIR_WRITE) - { - /*After sendding multi-block-write command, start DMA transfer*/ - at91_mci_write(AT91_MCI_IER, AT91_MCI_TXBUFE | AT91_MCI_BLKE); - at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTEN); - } + if (!mci->cmd) + return 1; + else if (!mci->cmd->data) + { + if (mci->current_status == REQ_ST_STOP) + { + /*After multi block write, we must wait for NOTBUSY*/ + at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY); + } + else return 1; + } + else if (mci->cmd->data->flags & DATA_DIR_WRITE) + { + /*After sendding multi-block-write command, start DMA transfer*/ + at91_mci_write(AT91_MCI_IER, AT91_MCI_TXBUFE | AT91_MCI_BLKE); + at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTEN); + } - /* command not completed, have to wait */ - return 0; + /* command not completed, have to wait */ + return 0; } /* @@ -546,64 +532,64 @@ static int at91_mci_handle_cmdrdy(struct at91_mci *mci) */ static void at91_mci_completed_command(struct at91_mci *mci, rt_uint32_t status) { - struct rt_mmcsd_cmd *cmd = mci->cmd; - struct rt_mmcsd_data *data = cmd->data; + struct rt_mmcsd_cmd *cmd = mci->cmd; + struct rt_mmcsd_data *data = cmd->data; - at91_mci_write(AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); + at91_mci_write(AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); - cmd->resp[0] = at91_mci_read(AT91_MCI_RSPR(0)); - cmd->resp[1] = at91_mci_read(AT91_MCI_RSPR(1)); - cmd->resp[2] = at91_mci_read(AT91_MCI_RSPR(2)); - cmd->resp[3] = at91_mci_read(AT91_MCI_RSPR(3)); + cmd->resp[0] = at91_mci_read(AT91_MCI_RSPR(0)); + cmd->resp[1] = at91_mci_read(AT91_MCI_RSPR(1)); + cmd->resp[2] = at91_mci_read(AT91_MCI_RSPR(2)); + cmd->resp[3] = at91_mci_read(AT91_MCI_RSPR(3)); - if (mci->buf) - { - //rt_memcpy(data->buf, mci->buf, data->blksize*data->blks); - rt_free(mci->buf); - mci->buf = RT_NULL; - } + if (mci->buf) + { + //rt_memcpy(data->buf, mci->buf, data->blksize*data->blks); + rt_free(mci->buf); + mci->buf = RT_NULL; + } - mci_dbg("Status = %08X/%08x [%08X %08X %08X %08X]\n", - status, at91_mci_read(AT91_MCI_SR), - cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); + mci_dbg("Status = %08X/%08x [%08X %08X %08X %08X]\n", + status, at91_mci_read(AT91_MCI_SR), + cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); - if (status & AT91_MCI_ERRORS) - { - if ((status & AT91_MCI_RCRCE) && (resp_type(cmd) & (RESP_R3|RESP_R4))) - { - cmd->err = 0; - } - else - { - if (status & (AT91_MCI_DTOE | AT91_MCI_DCRCE)) - { - if (data) - { - if (status & AT91_MCI_DTOE) - data->err = -RT_ETIMEOUT; - else if (status & AT91_MCI_DCRCE) - data->err = -RT_ERROR; - } - } - else - { - if (status & AT91_MCI_RTOE) - cmd->err = -RT_ETIMEOUT; - else if (status & AT91_MCI_RCRCE) - cmd->err = -RT_ERROR; - else - cmd->err = -RT_ERROR; - } + if (status & AT91_MCI_ERRORS) + { + if ((status & AT91_MCI_RCRCE) && (resp_type(cmd) & (RESP_R3|RESP_R4))) + { + cmd->err = 0; + } + else + { + if (status & (AT91_MCI_DTOE | AT91_MCI_DCRCE)) + { + if (data) + { + if (status & AT91_MCI_DTOE) + data->err = -RT_ETIMEOUT; + else if (status & AT91_MCI_DCRCE) + data->err = -RT_ERROR; + } + } + else + { + if (status & AT91_MCI_RTOE) + cmd->err = -RT_ETIMEOUT; + else if (status & AT91_MCI_RCRCE) + cmd->err = -RT_ERROR; + else + cmd->err = -RT_ERROR; + } - rt_kprintf("error detected and set to %d/%d (cmd = %d)\n", - cmd->err, data ? data->err : 0, - cmd->cmd_code); - } - } - else - cmd->err = 0; + rt_kprintf("error detected and set to %d/%d (cmd = %d)\n", + cmd->err, data ? data->err : 0, + cmd->cmd_code); + } + } + else + cmd->err = 0; - at91_mci_process_next(mci); + at91_mci_process_next(mci); } /* @@ -611,120 +597,120 @@ static void at91_mci_completed_command(struct at91_mci *mci, rt_uint32_t status) */ static void at91_mci_irq(int irq, void *param) { - struct at91_mci *mci = (struct at91_mci *)param; - rt_int32_t completed = 0; - rt_uint32_t int_status, int_mask; + struct at91_mci *mci = (struct at91_mci *)param; + rt_int32_t completed = 0; + rt_uint32_t int_status, int_mask; - int_status = at91_mci_read(AT91_MCI_SR); - int_mask = at91_mci_read(AT91_MCI_IMR); + int_status = at91_mci_read(AT91_MCI_SR); + int_mask = at91_mci_read(AT91_MCI_IMR); - mci_dbg("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask, - int_status & int_mask); + mci_dbg("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask, + int_status & int_mask); - int_status = int_status & int_mask; + int_status = int_status & int_mask; - if (int_status & AT91_MCI_ERRORS) - { - completed = 1; + if (int_status & AT91_MCI_ERRORS) + { + completed = 1; - if (int_status & AT91_MCI_UNRE) - mci_dbg("MMC: Underrun error\n"); - if (int_status & AT91_MCI_OVRE) - mci_dbg("MMC: Overrun error\n"); - if (int_status & AT91_MCI_DTOE) - mci_dbg("MMC: Data timeout\n"); - if (int_status & AT91_MCI_DCRCE) - mci_dbg("MMC: CRC error in data\n"); - if (int_status & AT91_MCI_RTOE) - mci_dbg("MMC: Response timeout\n"); - if (int_status & AT91_MCI_RENDE) - mci_dbg("MMC: Response end bit error\n"); - if (int_status & AT91_MCI_RCRCE) - mci_dbg("MMC: Response CRC error\n"); - if (int_status & AT91_MCI_RDIRE) - mci_dbg("MMC: Response direction error\n"); - if (int_status & AT91_MCI_RINDE) - mci_dbg("MMC: Response index error\n"); - } - else - { - /* Only continue processing if no errors */ + if (int_status & AT91_MCI_UNRE) + mci_dbg("MMC: Underrun error\n"); + if (int_status & AT91_MCI_OVRE) + mci_dbg("MMC: Overrun error\n"); + if (int_status & AT91_MCI_DTOE) + mci_dbg("MMC: Data timeout\n"); + if (int_status & AT91_MCI_DCRCE) + mci_dbg("MMC: CRC error in data\n"); + if (int_status & AT91_MCI_RTOE) + mci_dbg("MMC: Response timeout\n"); + if (int_status & AT91_MCI_RENDE) + mci_dbg("MMC: Response end bit error\n"); + if (int_status & AT91_MCI_RCRCE) + mci_dbg("MMC: Response CRC error\n"); + if (int_status & AT91_MCI_RDIRE) + mci_dbg("MMC: Response direction error\n"); + if (int_status & AT91_MCI_RINDE) + mci_dbg("MMC: Response index error\n"); + } + else + { + /* Only continue processing if no errors */ - if (int_status & AT91_MCI_TXBUFE) - { - mci_dbg("TX buffer empty\n"); - at91_mci_handle_transmitted(mci); - } + if (int_status & AT91_MCI_TXBUFE) + { + mci_dbg("TX buffer empty\n"); + at91_mci_handle_transmitted(mci); + } - if (int_status & AT91_MCI_ENDRX) - { - mci_dbg("ENDRX\n"); - at91_mci_post_dma_read(mci); - } + if (int_status & AT91_MCI_ENDRX) + { + mci_dbg("ENDRX\n"); + at91_mci_post_dma_read(mci); + } - if (int_status & AT91_MCI_RXBUFF) - { - mci_dbg("RX buffer full\n"); - at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS); - at91_mci_write(AT91_MCI_IDR, AT91_MCI_RXBUFF | AT91_MCI_ENDRX); - completed = 1; - } + if (int_status & AT91_MCI_RXBUFF) + { + mci_dbg("RX buffer full\n"); + at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS); + at91_mci_write(AT91_MCI_IDR, AT91_MCI_RXBUFF | AT91_MCI_ENDRX); + completed = 1; + } - if (int_status & AT91_MCI_ENDTX) - mci_dbg("Transmit has ended\n"); + if (int_status & AT91_MCI_ENDTX) + mci_dbg("Transmit has ended\n"); - if (int_status & AT91_MCI_NOTBUSY) - { - mci_dbg("Card is ready\n"); - //at91_mci_update_bytes_xfered(host); - completed = 1; - } + if (int_status & AT91_MCI_NOTBUSY) + { + mci_dbg("Card is ready\n"); + //at91_mci_update_bytes_xfered(host); + completed = 1; + } - if (int_status & AT91_MCI_DTIP) - mci_dbg("Data transfer in progress\n"); + if (int_status & AT91_MCI_DTIP) + mci_dbg("Data transfer in progress\n"); - if (int_status & AT91_MCI_BLKE) - { - mci_dbg("Block transfer has ended\n"); - if (mci->req->data && mci->req->data->blks > 1) - { - /* multi block write : complete multi write - * command and send stop */ - completed = 1; - } - else - { - at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY); - } - } + if (int_status & AT91_MCI_BLKE) + { + mci_dbg("Block transfer has ended\n"); + if (mci->req->data && mci->req->data->blks > 1) + { + /* multi block write : complete multi write + * command and send stop */ + completed = 1; + } + else + { + at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY); + } + } - /*if (int_status & AT91_MCI_SDIOIRQA) - rt_mmcsd_signal_sdio_irq(host->mmc);*/ + /*if (int_status & AT91_MCI_SDIOIRQA) + rt_mmcsd_signal_sdio_irq(host->mmc);*/ - if (int_status & AT91_MCI_SDIOIRQB) - sdio_irq_wakeup(mci->host); + if (int_status & AT91_MCI_SDIOIRQB) + sdio_irq_wakeup(mci->host); - if (int_status & AT91_MCI_TXRDY) - mci_dbg("Ready to transmit\n"); + if (int_status & AT91_MCI_TXRDY) + mci_dbg("Ready to transmit\n"); - if (int_status & AT91_MCI_RXRDY) - mci_dbg("Ready to receive\n"); + if (int_status & AT91_MCI_RXRDY) + mci_dbg("Ready to receive\n"); - if (int_status & AT91_MCI_CMDRDY) - { - mci_dbg("Command ready\n"); - completed = at91_mci_handle_cmdrdy(mci); - } - } + if (int_status & AT91_MCI_CMDRDY) + { + mci_dbg("Command ready\n"); + completed = at91_mci_handle_cmdrdy(mci); + } + } - if (completed) - { - mci_dbg("Completed command\n"); - at91_mci_write(AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); - at91_mci_completed_command(mci, int_status); - } - else - at91_mci_write(AT91_MCI_IDR, int_status & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); + if (completed) + { + mci_dbg("Completed command\n"); + at91_mci_write(AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); + at91_mci_completed_command(mci, int_status); + } + else + at91_mci_write(AT91_MCI_IDR, int_status & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB)); } @@ -734,173 +720,173 @@ static void at91_mci_irq(int irq, void *param) */ static void at91_mci_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) { - rt_uint32_t clkdiv; - //struct at91_mci *mci = host->private_data; - rt_uint32_t at91_master_clock = clk_get_rate(clk_get("mck")); + rt_uint32_t clkdiv; + //struct at91_mci *mci = host->private_data; + rt_uint32_t at91_master_clock = clk_get_rate(clk_get("mck")); - if (io_cfg->clock == 0) - { - /* Disable the MCI controller */ - at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS); - clkdiv = 0; - } - else - { - /* Enable the MCI controller */ - at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN); + if (io_cfg->clock == 0) + { + /* Disable the MCI controller */ + at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS); + clkdiv = 0; + } + else + { + /* Enable the MCI controller */ + at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN); - if ((at91_master_clock % (io_cfg->clock * 2)) == 0) - clkdiv = ((at91_master_clock / io_cfg->clock) / 2) - 1; - else - clkdiv = (at91_master_clock / io_cfg->clock) / 2; + if ((at91_master_clock % (io_cfg->clock * 2)) == 0) + clkdiv = ((at91_master_clock / io_cfg->clock) / 2) - 1; + else + clkdiv = (at91_master_clock / io_cfg->clock) / 2; - mci_dbg("clkdiv = %d. mcck = %ld\n", clkdiv, - at91_master_clock / (2 * (clkdiv + 1))); - } - if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4) - { - mci_dbg("MMC: Setting controller bus width to 4\n"); - at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) | AT91_MCI_SDCBUS); - } - else - { - mci_dbg("MMC: Setting controller bus width to 1\n"); - at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS); - } + mci_dbg("clkdiv = %d. mcck = %ld\n", clkdiv, + at91_master_clock / (2 * (clkdiv + 1))); + } + if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4) + { + mci_dbg("MMC: Setting controller bus width to 4\n"); + at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) | AT91_MCI_SDCBUS); + } + else + { + mci_dbg("MMC: Setting controller bus width to 1\n"); + at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS); + } - /* Set the clock divider */ - at91_mci_write(AT91_MCI_MR, (at91_mci_read(AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv); + /* Set the clock divider */ + at91_mci_write(AT91_MCI_MR, (at91_mci_read(AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv); - /* maybe switch power to the card */ - switch (io_cfg->power_mode) - { - case MMCSD_POWER_OFF: - break; - case MMCSD_POWER_UP: - break; - case MMCSD_POWER_ON: - /*at91_mci_write(AT91_MCI_ARGR, 0); - at91_mci_write(AT91_MCI_CMDR, 0|AT91_MCI_SPCMD_INIT|AT91_MCI_OPDCMD); - mci_dbg("MCI_SR=0x%08x\n", at91_mci_read(AT91_MCI_SR)); - while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY)) - { - - } - mci_dbg("at91 mci power on\n");*/ - break; - default: - rt_kprintf("unknown power_mode %d\n", io_cfg->power_mode); - break; - } + /* maybe switch power to the card */ + switch (io_cfg->power_mode) + { + case MMCSD_POWER_OFF: + break; + case MMCSD_POWER_UP: + break; + case MMCSD_POWER_ON: + /*at91_mci_write(AT91_MCI_ARGR, 0); + at91_mci_write(AT91_MCI_CMDR, 0|AT91_MCI_SPCMD_INIT|AT91_MCI_OPDCMD); + mci_dbg("MCI_SR=0x%08x\n", at91_mci_read(AT91_MCI_SR)); + while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY)) + { + + } + mci_dbg("at91 mci power on\n");*/ + break; + default: + rt_kprintf("unknown power_mode %d\n", io_cfg->power_mode); + break; + } } static void at91_mci_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t enable) { - at91_mci_write(enable ? AT91_MCI_IER : AT91_MCI_IDR, AT91_MCI_SDIOIRQB); + at91_mci_write(enable ? AT91_MCI_IER : AT91_MCI_IDR, AT91_MCI_SDIOIRQB); } static const struct rt_mmcsd_host_ops ops = { - at91_mci_request, - at91_mci_set_iocfg, + at91_mci_request, + at91_mci_set_iocfg, RT_NULL, - at91_mci_enable_sdio_irq, + at91_mci_enable_sdio_irq, }; void at91_mci_detect(int irq, void *param) { - rt_kprintf("mmcsd gpio detected\n"); + rt_kprintf("mmcsd gpio detected\n"); } static void mci_gpio_init() { #ifdef USE_SLOT_B - at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)); - at91_sys_write(AT91_PIOA + PIO_PUDR, (1 << 8)); - at91_sys_write(AT91_PIOA + PIO_BSR, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)); - at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 8)); - at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)|(1 << 8)); + at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)); + at91_sys_write(AT91_PIOA + PIO_PUDR, (1 << 8)); + at91_sys_write(AT91_PIOA + PIO_BSR, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)); + at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 8)); + at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)|(1 << 8)); - at91_sys_write(AT91_PIOA + PIO_IDR, (1 << 6)|(1 << 7)); - at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 6)|(1 << 7)); - at91_sys_write(AT91_PIOA + PIO_ODR, (1 << 6)|(1 << 7)); - at91_sys_write(AT91_PIOA + PIO_PER, (1 << 6)|(1 << 7)); + at91_sys_write(AT91_PIOA + PIO_IDR, (1 << 6)|(1 << 7)); + at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 6)|(1 << 7)); + at91_sys_write(AT91_PIOA + PIO_ODR, (1 << 6)|(1 << 7)); + at91_sys_write(AT91_PIOA + PIO_PER, (1 << 6)|(1 << 7)); #else - at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)); - at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8)); - at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8)); + at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)); + at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8)); + at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8)); #endif } int at91_mci_init(void) { - struct rt_mmcsd_host *host; - struct at91_mci *mci; + struct rt_mmcsd_host *host; + struct at91_mci *mci; - host = mmcsd_alloc_host(); - if (!host) - { - return -RT_ERROR; - } + host = mmcsd_alloc_host(); + if (!host) + { + return -RT_ERROR; + } - mci = rt_malloc(sizeof(struct at91_mci)); - if (!mci) - { - rt_kprintf("alloc mci failed\n"); - goto err; - } + mci = rt_malloc(sizeof(struct at91_mci)); + if (!mci) + { + rt_kprintf("alloc mci failed\n"); + goto err; + } - rt_memset(mci, 0, sizeof(struct at91_mci)); + rt_memset(mci, 0, sizeof(struct at91_mci)); - host->ops = &ops; - host->freq_min = 375000; - host->freq_max = 25000000; - host->valid_ocr = VDD_32_33 | VDD_33_34; - host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \ - MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ; - host->max_seg_size = 65535; - host->max_dma_segs = 2; - host->max_blk_size = 512; - host->max_blk_count = 4096; + host->ops = &ops; + host->freq_min = 375000; + host->freq_max = 25000000; + host->valid_ocr = VDD_32_33 | VDD_33_34; + host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \ + MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ; + host->max_seg_size = 65535; + host->max_dma_segs = 2; + host->max_blk_size = 512; + host->max_blk_count = 4096; - mci->host = host; + mci->host = host; - mci_gpio_init(); - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_MCI); //enable MCI clock - - at91_mci_disable(); - at91_mci_enable(); + mci_gpio_init(); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_MCI); //enable MCI clock - /* instal interrupt */ - rt_hw_interrupt_install(AT91SAM9260_ID_MCI, at91_mci_irq, - (void *)mci, "MMC"); - rt_hw_interrupt_umask(AT91SAM9260_ID_MCI); - rt_hw_interrupt_install(gpio_to_irq(AT91_PIN_PA7), - at91_mci_detect, RT_NULL, "MMC_DETECT"); - rt_hw_interrupt_umask(gpio_to_irq(AT91_PIN_PA7)); + at91_mci_disable(); + at91_mci_enable(); - rt_timer_init(&mci->timer, "mci_timer", - at91_timeout_timer, - mci, - RT_TICK_PER_SECOND, - RT_TIMER_FLAG_PERIODIC); + /* instal interrupt */ + rt_hw_interrupt_install(AT91SAM9260_ID_MCI, at91_mci_irq, + (void *)mci, "MMC"); + rt_hw_interrupt_umask(AT91SAM9260_ID_MCI); + rt_hw_interrupt_install(gpio_to_irq(AT91_PIN_PA7), + at91_mci_detect, RT_NULL, "MMC_DETECT"); + rt_hw_interrupt_umask(gpio_to_irq(AT91_PIN_PA7)); - //rt_timer_start(&mci->timer); + rt_timer_init(&mci->timer, "mci_timer", + at91_timeout_timer, + mci, + RT_TICK_PER_SECOND, + RT_TIMER_FLAG_PERIODIC); - //rt_sem_init(&mci->sem_ack, "sd_ack", 0, RT_IPC_FLAG_FIFO); + //rt_timer_start(&mci->timer); - host->private_data = mci; + //rt_sem_init(&mci->sem_ack, "sd_ack", 0, RT_IPC_FLAG_FIFO); - mmcsd_change(host); + host->private_data = mci; - return 0; + mmcsd_change(host); + + return 0; err: - mmcsd_free_host(host); + mmcsd_free_host(host); - return -RT_ENOMEM; + return -RT_ENOMEM; } INIT_DEVICE_EXPORT(at91_mci_init); @@ -910,15 +896,15 @@ FINSH_FUNCTION_EXPORT(at91_mci_init, at91sam9260 sd init); void mci_dump(void) { - rt_uint32_t i; + rt_uint32_t i; - rt_kprintf("PIOA_PSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_PSR)); - rt_kprintf("PIOA_ABSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_ABSR)); - rt_kprintf("PIOA_PUSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_PUSR)); + rt_kprintf("PIOA_PSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_PSR)); + rt_kprintf("PIOA_ABSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_ABSR)); + rt_kprintf("PIOA_PUSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_PUSR)); - for (i = 0; i <= 0x4c; i += 4) { - rt_kprintf("0x%08x:0x%08x\n", AT91SAM9260_BASE_MCI+i, at91_mci_read(i)); - } + for (i = 0; i <= 0x4c; i += 4) { + rt_kprintf("0x%08x:0x%08x\n", AT91SAM9260_BASE_MCI+i, at91_mci_read(i)); + } } FINSH_FUNCTION_EXPORT(mci_dump, dump register for mci); diff --git a/bsp/at91sam9260/drivers/at91_mci.h b/bsp/at91sam9260/drivers/at91_mci.h index 4e3bae9999..80eb07385d 100644 --- a/bsp/at91sam9260/drivers/at91_mci.h +++ b/bsp/at91sam9260/drivers/at91_mci.h @@ -1,21 +1,7 @@ /* - * File : at91_mci.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -25,99 +11,99 @@ #ifndef __AT91_MCI_H__ #define __AT91_MCI_H__ -#define AT91_MCI_CR 0x00 /* Control Register */ -#define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */ -#define AT91_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */ -#define AT91_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */ -#define AT91_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */ -#define AT91_MCI_SWRST (1 << 7) /* Software Reset */ +#define AT91_MCI_CR 0x00 /* Control Register */ +#define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */ +#define AT91_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */ +#define AT91_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */ +#define AT91_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */ +#define AT91_MCI_SWRST (1 << 7) /* Software Reset */ -#define AT91_MCI_MR 0x04 /* Mode Register */ -#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */ -#define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */ -#define AT91_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */ -#define AT91_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */ -#define AT91_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */ -#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ -#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ -#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ +#define AT91_MCI_MR 0x04 /* Mode Register */ +#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */ +#define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */ +#define AT91_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */ +#define AT91_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */ +#define AT91_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */ +#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ +#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ +#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ -#define AT91_MCI_DTOR 0x08 /* Data Timeout Register */ -#define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */ -#define AT91_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */ -#define AT91_MCI_DTOMUL_1 (0 << 4) -#define AT91_MCI_DTOMUL_16 (1 << 4) -#define AT91_MCI_DTOMUL_128 (2 << 4) -#define AT91_MCI_DTOMUL_256 (3 << 4) -#define AT91_MCI_DTOMUL_1K (4 << 4) -#define AT91_MCI_DTOMUL_4K (5 << 4) -#define AT91_MCI_DTOMUL_64K (6 << 4) -#define AT91_MCI_DTOMUL_1M (7 << 4) +#define AT91_MCI_DTOR 0x08 /* Data Timeout Register */ +#define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */ +#define AT91_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */ +#define AT91_MCI_DTOMUL_1 (0 << 4) +#define AT91_MCI_DTOMUL_16 (1 << 4) +#define AT91_MCI_DTOMUL_128 (2 << 4) +#define AT91_MCI_DTOMUL_256 (3 << 4) +#define AT91_MCI_DTOMUL_1K (4 << 4) +#define AT91_MCI_DTOMUL_4K (5 << 4) +#define AT91_MCI_DTOMUL_64K (6 << 4) +#define AT91_MCI_DTOMUL_1M (7 << 4) -#define AT91_MCI_SDCR 0x0c /* SD Card Register */ -#define AT91_MCI_SDCSEL (3 << 0) /* SD Card Selector */ -#define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */ +#define AT91_MCI_SDCR 0x0c /* SD Card Register */ +#define AT91_MCI_SDCSEL (3 << 0) /* SD Card Selector */ +#define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */ -#define AT91_MCI_ARGR 0x10 /* Argument Register */ +#define AT91_MCI_ARGR 0x10 /* Argument Register */ -#define AT91_MCI_CMDR 0x14 /* Command Register */ -#define AT91_MCI_CMDNB (0x3f << 0) /* Command Number */ -#define AT91_MCI_RSPTYP (3 << 6) /* Response Type */ -#define AT91_MCI_RSPTYP_NONE (0 << 6) -#define AT91_MCI_RSPTYP_48 (1 << 6) -#define AT91_MCI_RSPTYP_136 (2 << 6) -#define AT91_MCI_SPCMD (7 << 8) /* Special Command */ -#define AT91_MCI_SPCMD_NONE (0 << 8) -#define AT91_MCI_SPCMD_INIT (1 << 8) -#define AT91_MCI_SPCMD_SYNC (2 << 8) -#define AT91_MCI_SPCMD_ICMD (4 << 8) -#define AT91_MCI_SPCMD_IRESP (5 << 8) -#define AT91_MCI_OPDCMD (1 << 11) /* Open Drain Command */ -#define AT91_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */ -#define AT91_MCI_TRCMD (3 << 16) /* Transfer Command */ -#define AT91_MCI_TRCMD_NONE (0 << 16) -#define AT91_MCI_TRCMD_START (1 << 16) -#define AT91_MCI_TRCMD_STOP (2 << 16) -#define AT91_MCI_TRDIR (1 << 18) /* Transfer Direction */ -#define AT91_MCI_TRTYP (3 << 19) /* Transfer Type */ -#define AT91_MCI_TRTYP_BLOCK (0 << 19) -#define AT91_MCI_TRTYP_MULTIPLE (1 << 19) -#define AT91_MCI_TRTYP_STREAM (2 << 19) +#define AT91_MCI_CMDR 0x14 /* Command Register */ +#define AT91_MCI_CMDNB (0x3f << 0) /* Command Number */ +#define AT91_MCI_RSPTYP (3 << 6) /* Response Type */ +#define AT91_MCI_RSPTYP_NONE (0 << 6) +#define AT91_MCI_RSPTYP_48 (1 << 6) +#define AT91_MCI_RSPTYP_136 (2 << 6) +#define AT91_MCI_SPCMD (7 << 8) /* Special Command */ +#define AT91_MCI_SPCMD_NONE (0 << 8) +#define AT91_MCI_SPCMD_INIT (1 << 8) +#define AT91_MCI_SPCMD_SYNC (2 << 8) +#define AT91_MCI_SPCMD_ICMD (4 << 8) +#define AT91_MCI_SPCMD_IRESP (5 << 8) +#define AT91_MCI_OPDCMD (1 << 11) /* Open Drain Command */ +#define AT91_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */ +#define AT91_MCI_TRCMD (3 << 16) /* Transfer Command */ +#define AT91_MCI_TRCMD_NONE (0 << 16) +#define AT91_MCI_TRCMD_START (1 << 16) +#define AT91_MCI_TRCMD_STOP (2 << 16) +#define AT91_MCI_TRDIR (1 << 18) /* Transfer Direction */ +#define AT91_MCI_TRTYP (3 << 19) /* Transfer Type */ +#define AT91_MCI_TRTYP_BLOCK (0 << 19) +#define AT91_MCI_TRTYP_MULTIPLE (1 << 19) +#define AT91_MCI_TRTYP_STREAM (2 << 19) -#define AT91_MCI_BLKR 0x18 /* Block Register */ -#define AT91_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0) /* Block count */ -#define AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16) /* Block lenght */ +#define AT91_MCI_BLKR 0x18 /* Block Register */ +#define AT91_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0) /* Block count */ +#define AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16) /* Block lenght */ -#define AT91_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */ -#define AT91_MCR_RDR 0x30 /* Receive Data Register */ -#define AT91_MCR_TDR 0x34 /* Transmit Data Register */ +#define AT91_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */ +#define AT91_MCR_RDR 0x30 /* Receive Data Register */ +#define AT91_MCR_TDR 0x34 /* Transmit Data Register */ -#define AT91_MCI_SR 0x40 /* Status Register */ -#define AT91_MCI_CMDRDY (1U << 0) /* Command Ready */ -#define AT91_MCI_RXRDY (1U << 1) /* Receiver Ready */ -#define AT91_MCI_TXRDY (1U << 2) /* Transmit Ready */ -#define AT91_MCI_BLKE (1U << 3) /* Data Block Ended */ -#define AT91_MCI_DTIP (1U << 4) /* Data Transfer in Progress */ -#define AT91_MCI_NOTBUSY (1U << 5) /* Data Not Busy */ -#define AT91_MCI_ENDRX (1U << 6) /* End of RX Buffer */ -#define AT91_MCI_ENDTX (1U << 7) /* End fo TX Buffer */ -#define AT91_MCI_SDIOIRQA (1U << 8) /* SDIO Interrupt for Slot A */ -#define AT91_MCI_SDIOIRQB (1U << 9) /* SDIO Interrupt for Slot B */ -#define AT91_MCI_RXBUFF (1U << 14) /* RX Buffer Full */ -#define AT91_MCI_TXBUFE (1U << 15) /* TX Buffer Empty */ -#define AT91_MCI_RINDE (1U << 16) /* Response Index Error */ -#define AT91_MCI_RDIRE (1U << 17) /* Response Direction Error */ -#define AT91_MCI_RCRCE (1U << 18) /* Response CRC Error */ -#define AT91_MCI_RENDE (1U << 19) /* Response End Bit Error */ -#define AT91_MCI_RTOE (1U << 20) /* Reponse Time-out Error */ -#define AT91_MCI_DCRCE (1U << 21) /* Data CRC Error */ -#define AT91_MCI_DTOE (1U << 22) /* Data Time-out Error */ -#define AT91_MCI_OVRE (1U << 30) /* Overrun */ -#define AT91_MCI_UNRE (1U << 31) /* Underrun */ +#define AT91_MCI_SR 0x40 /* Status Register */ +#define AT91_MCI_CMDRDY (1U << 0) /* Command Ready */ +#define AT91_MCI_RXRDY (1U << 1) /* Receiver Ready */ +#define AT91_MCI_TXRDY (1U << 2) /* Transmit Ready */ +#define AT91_MCI_BLKE (1U << 3) /* Data Block Ended */ +#define AT91_MCI_DTIP (1U << 4) /* Data Transfer in Progress */ +#define AT91_MCI_NOTBUSY (1U << 5) /* Data Not Busy */ +#define AT91_MCI_ENDRX (1U << 6) /* End of RX Buffer */ +#define AT91_MCI_ENDTX (1U << 7) /* End fo TX Buffer */ +#define AT91_MCI_SDIOIRQA (1U << 8) /* SDIO Interrupt for Slot A */ +#define AT91_MCI_SDIOIRQB (1U << 9) /* SDIO Interrupt for Slot B */ +#define AT91_MCI_RXBUFF (1U << 14) /* RX Buffer Full */ +#define AT91_MCI_TXBUFE (1U << 15) /* TX Buffer Empty */ +#define AT91_MCI_RINDE (1U << 16) /* Response Index Error */ +#define AT91_MCI_RDIRE (1U << 17) /* Response Direction Error */ +#define AT91_MCI_RCRCE (1U << 18) /* Response CRC Error */ +#define AT91_MCI_RENDE (1U << 19) /* Response End Bit Error */ +#define AT91_MCI_RTOE (1U << 20) /* Reponse Time-out Error */ +#define AT91_MCI_DCRCE (1U << 21) /* Data CRC Error */ +#define AT91_MCI_DTOE (1U << 22) /* Data Time-out Error */ +#define AT91_MCI_OVRE (1U << 30) /* Overrun */ +#define AT91_MCI_UNRE (1U << 31) /* Underrun */ -#define AT91_MCI_IER 0x44 /* Interrupt Enable Register */ -#define AT91_MCI_IDR 0x48 /* Interrupt Disable Register */ -#define AT91_MCI_IMR 0x4c /* Interrupt Mask Register */ +#define AT91_MCI_IER 0x44 /* Interrupt Enable Register */ +#define AT91_MCI_IDR 0x48 /* Interrupt Disable Register */ +#define AT91_MCI_IMR 0x4c /* Interrupt Mask Register */ extern int at91_mci_init(void); diff --git a/bsp/at91sam9260/drivers/board.c b/bsp/at91sam9260/drivers/board.c index a7ec6008da..8a063cfc86 100644 --- a/bsp/at91sam9260/drivers/board.c +++ b/bsp/at91sam9260/drivers/board.c @@ -1,21 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -54,56 +40,56 @@ extern void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv); extern void rt_dbgu_isr(void); static struct mem_desc at91_mem_desc[] = { - { 0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB }, /* None cached for 4G memory */ - { 0x20000000, 0x24000000-1, 0x20000000, RW_CB }, /* 64M cached SDRAM memory */ - { 0x00000000, 0x100000, 0x20000000, RW_CB }, /* isr vector table */ - { 0x90000000, 0x90400000-1, 0x00200000, RW_NCNB }, /* 4K SRAM0@2M + 4k SRAM1@3M + 16k UHP@5M */ - { 0xA0000000, 0xA4000000-1, 0x20000000, RW_NCNB } /* 64M none-cached SDRAM memory */ + { 0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB }, /* None cached for 4G memory */ + { 0x20000000, 0x24000000-1, 0x20000000, RW_CB }, /* 64M cached SDRAM memory */ + { 0x00000000, 0x100000, 0x20000000, RW_CB }, /* isr vector table */ + { 0x90000000, 0x90400000-1, 0x00200000, RW_NCNB }, /* 4K SRAM0@2M + 4k SRAM1@3M + 16k UHP@5M */ + { 0xA0000000, 0xA4000000-1, 0x20000000, RW_NCNB } /* 64M none-cached SDRAM memory */ }; -#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV) -#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20) +#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV) +#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20) -static rt_uint32_t pit_cycle; /* write-once */ -static rt_uint32_t pit_cnt; /* access only w/system irq blocked */ +static rt_uint32_t pit_cycle; /* write-once */ +static rt_uint32_t pit_cnt; /* access only w/system irq blocked */ /** * This function will handle rtos timer */ void rt_timer_handler(int vector, void *param) { - #ifdef RT_USING_DBGU - if (at91_sys_read(AT91_DBGU + AT91_US_CSR) & 0x1) - { - rt_dbgu_isr(); - } - #endif - if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS) - { - unsigned nr_ticks; + #ifdef RT_USING_DBGU + if (at91_sys_read(AT91_DBGU + AT91_US_CSR) & 0x1) + { + rt_dbgu_isr(); + } + #endif + if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS) + { + unsigned nr_ticks; - /* Get number of ticks performed before irq, and ack it */ - nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); - rt_tick_increase(); - } + /* Get number of ticks performed before irq, and ack it */ + nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); + rt_tick_increase(); + } } static void at91sam926x_pit_reset(void) { - /* Disable timer and irqs */ - at91_sys_write(AT91_PIT_MR, 0); + /* Disable timer and irqs */ + at91_sys_write(AT91_PIT_MR, 0); - /* Clear any pending interrupts, wait for PIT to stop counting */ - while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0) - ; + /* Clear any pending interrupts, wait for PIT to stop counting */ + while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0) + ; - /* Start PIT but don't enable IRQ */ - //at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN); - pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); - at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN - | AT91_PIT_PITIEN); - rt_kprintf("PIT_MR=0x%08x\n", at91_sys_read(AT91_PIT_MR)); + /* Start PIT but don't enable IRQ */ + //at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN); + pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); + at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN + | AT91_PIT_PITIEN); + rt_kprintf("PIT_MR=0x%08x\n", at91_sys_read(AT91_PIT_MR)); } /* @@ -111,19 +97,19 @@ static void at91sam926x_pit_reset(void) */ static void at91sam926x_pit_init(void) { - rt_uint32_t pit_rate; - rt_uint32_t bits; + rt_uint32_t pit_rate; + rt_uint32_t bits; - /* - * Use our actual MCK to figure out how many MCK/16 ticks per - * 1/HZ period (instead of a compile-time constant LATCH). - */ - pit_rate = clk_get_rate(clk_get("mck")) / 16; - rt_kprintf("pit_rate=%dHZ\n", pit_rate); - pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND; + /* + * Use our actual MCK to figure out how many MCK/16 ticks per + * 1/HZ period (instead of a compile-time constant LATCH). + */ + pit_rate = clk_get_rate(clk_get("mck")) / 16; + rt_kprintf("pit_rate=%dHZ\n", pit_rate); + pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND; - /* Initialize and enable the timer */ - at91sam926x_pit_reset(); + /* Initialize and enable the timer */ + at91sam926x_pit_reset(); } @@ -132,69 +118,69 @@ static void at91sam926x_pit_init(void) */ void rt_hw_timer_init() { - at91sam926x_pit_init(); + at91sam926x_pit_init(); - /* install interrupt handler */ - rt_hw_interrupt_install(AT91_ID_SYS, rt_timer_handler, - RT_NULL, "system"); - rt_hw_interrupt_umask(AT91_ID_SYS); + /* install interrupt handler */ + rt_hw_interrupt_install(AT91_ID_SYS, rt_timer_handler, + RT_NULL, "system"); + rt_hw_interrupt_umask(AT91_ID_SYS); } - + void at91_tc1_init() { - at91_sys_write(AT91_PMC_PCER, 1<CSR & TXRDY)); - DBGU->THR = c; + DBGU->THR = c; } /** @@ -205,33 +191,33 @@ static void at91_usart_putc(char c) */ void rt_hw_console_output(const char* str) { - while (*str) - { - if (*str=='\n') - { - at91_usart_putc('\r'); - } + while (*str) + { + if (*str=='\n') + { + at91_usart_putc('\r'); + } - at91_usart_putc(*str++); - } + at91_usart_putc(*str++); + } } static void rt_hw_console_init(void) { - int div; - int mode = 0; + int div; + int mode = 0; - DBGU->CR = AT91_US_RSTTX | AT91_US_RSTRX | - AT91_US_RXDIS | AT91_US_TXDIS; - mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK | - AT91_US_CHMODE_NORMAL; - mode |= AT91_US_CHRL_8; - mode |= AT91_US_NBSTOP_1; - mode |= AT91_US_PAR_NONE; - DBGU->MR = mode; - div = (clk_get_rate(clk_get("mck")) / 16 + BPS/2) / BPS; - DBGU->BRGR = div; - DBGU->CR = AT91_US_RXEN | AT91_US_TXEN; + DBGU->CR = AT91_US_RSTTX | AT91_US_RSTRX | + AT91_US_RXDIS | AT91_US_TXDIS; + mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK | + AT91_US_CHMODE_NORMAL; + mode |= AT91_US_CHRL_8; + mode |= AT91_US_NBSTOP_1; + mode |= AT91_US_PAR_NONE; + DBGU->MR = mode; + div = (clk_get_rate(clk_get("mck")) / 16 + BPS/2) / BPS; + DBGU->BRGR = div; + DBGU->CR = AT91_US_RXEN | AT91_US_TXEN; } @@ -240,31 +226,31 @@ static void rt_hw_console_init(void) */ void rt_hw_board_init() { - /* initialize the system clock */ - rt_hw_clock_init(); + /* initialize the system clock */ + rt_hw_clock_init(); - /* initialize console */ - rt_hw_console_init(); + /* initialize console */ + rt_hw_console_init(); - /* initialize mmu */ - rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0])); + /* initialize mmu */ + rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0])); - /* initialize hardware interrupt */ - rt_hw_interrupt_init(); + /* initialize hardware interrupt */ + rt_hw_interrupt_init(); - /* initialize early device */ + /* initialize early device */ #ifdef RT_USING_COMPONENTS_INIT - rt_components_board_init(); + rt_components_board_init(); #endif #ifdef RT_USING_CONSOLE - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif - /* initialize timer0 */ - rt_hw_timer_init(); + /* initialize timer0 */ + rt_hw_timer_init(); /* initialize board */ #ifdef RT_USING_HEAP - rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); #endif } diff --git a/bsp/at91sam9260/drivers/board.h b/bsp/at91sam9260/drivers/board.h index e6c8f77865..c3f4435077 100644 --- a/bsp/at91sam9260/drivers/board.h +++ b/bsp/at91sam9260/drivers/board.h @@ -1,21 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/at91sam9260/drivers/led.c b/bsp/at91sam9260/drivers/led.c index 3791b2a568..10277813d4 100644 --- a/bsp/at91sam9260/drivers/led.c +++ b/bsp/at91sam9260/drivers/led.c @@ -1,21 +1,7 @@ /* - * File : led.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -28,59 +14,59 @@ #if 1 // GB9260 board -#define PIO_LED AT91_PIOB -#define LED1 (1 << 25) // LED_SYS -#define LED2 (0) -#define LED3 (1 << 23) // LED_USR -#define LED_ALL (LED1 | LED2 | LED3) +#define PIO_LED AT91_PIOB +#define LED1 (1 << 25) // LED_SYS +#define LED2 (0) +#define LED3 (1 << 23) // LED_USR +#define LED_ALL (LED1 | LED2 | LED3) #else -#define PIO_LED AT91_PIOC -#define LED1 (1 << 8) -#define LED2 (1 << 11) -#define LED3 (1 << 6) -#define LED_ALL (LED1 | LED2 | LED3) +#define PIO_LED AT91_PIOC +#define LED1 (1 << 8) +#define LED2 (1 << 11) +#define LED3 (1 << 6) +#define LED_ALL (LED1 | LED2 | LED3) #endif void led_init(void) { - at91_sys_write(PIO_LED+0x00, LED_ALL); - at91_sys_write(PIO_LED+0x10, LED_ALL); - at91_sys_write(PIO_LED+0x64, LED_ALL); - at91_sys_write(PIO_LED+0x30, LED_ALL); + at91_sys_write(PIO_LED+0x00, LED_ALL); + at91_sys_write(PIO_LED+0x10, LED_ALL); + at91_sys_write(PIO_LED+0x64, LED_ALL); + at91_sys_write(PIO_LED+0x30, LED_ALL); } void led_on(int num) { - switch(num) - { - case 1: - at91_sys_write(PIO_LED+0x34, LED1); - break; - case 2: - at91_sys_write(PIO_LED+0x34, LED2); - break; - case 3: - at91_sys_write(PIO_LED+0x34, LED3); - break; - default: - break; - } + switch(num) + { + case 1: + at91_sys_write(PIO_LED+0x34, LED1); + break; + case 2: + at91_sys_write(PIO_LED+0x34, LED2); + break; + case 3: + at91_sys_write(PIO_LED+0x34, LED3); + break; + default: + break; + } } void led_off(int num) { - switch(num) - { - case 1: - at91_sys_write(PIO_LED+0x30, LED1); - break; - case 2: - at91_sys_write(PIO_LED+0x30, LED2); - break; - case 3: - at91_sys_write(PIO_LED+0x30, LED3); - break; - default: - break; - } + switch(num) + { + case 1: + at91_sys_write(PIO_LED+0x30, LED1); + break; + case 2: + at91_sys_write(PIO_LED+0x30, LED2); + break; + case 3: + at91_sys_write(PIO_LED+0x30, LED3); + break; + default: + break; + } } diff --git a/bsp/at91sam9260/drivers/led.h b/bsp/at91sam9260/drivers/led.h index f2967bc92d..9836eff709 100644 --- a/bsp/at91sam9260/drivers/led.h +++ b/bsp/at91sam9260/drivers/led.h @@ -1,21 +1,7 @@ /* - * File : led.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/at91sam9260/drivers/macb.c b/bsp/at91sam9260/drivers/macb.c index 26400c62de..702d7e04a4 100644 --- a/bsp/at91sam9260/drivers/macb.c +++ b/bsp/at91sam9260/drivers/macb.c @@ -1,21 +1,7 @@ /* - * File : macb.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -28,7 +14,7 @@ #include #include "macb.h" -#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31)) +#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31)) extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size); extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); @@ -36,11 +22,11 @@ extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); /* Cache macros - Packet buffers would be from pbuf pool which is cached */ #define EMAC_VIRT_NOCACHE(addr) (addr) #define EMAC_CACHE_INVALIDATE(addr, size) \ - mmu_invalidate_dcache((rt_uint32_t)addr, size) + mmu_invalidate_dcache((rt_uint32_t)addr, size) #define EMAC_CACHE_WRITEBACK(addr, size) \ - mmu_clean_dcache((rt_uint32_t)addr, size) + mmu_clean_dcache((rt_uint32_t)addr, size) #define EMAC_CACHE_WRITEBACK_INVALIDATE(addr, size) \ - mmu_clean_invalidated_dcache((rt_uint32_t)addr, size) + mmu_clean_invalidated_dcache((rt_uint32_t)addr, size) /* EMAC has BD's in cached memory - so need cache functions */ #define BD_CACHE_INVALIDATE(addr, size) @@ -50,7 +36,7 @@ extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); /* EMAC internal utility function */ rt_inline unsigned long emac_virt_to_phys(unsigned long addr) { - return addr; + return addr; } @@ -59,112 +45,112 @@ rt_inline unsigned long emac_virt_to_phys(unsigned long addr) #define MACB_TX_SRAM #if defined(MACB_TX_SRAM) -#define MACB_TX_RING_SIZE 2 -#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE) -#define TX_RING_BYTES (sizeof(struct macb_dma_desc) * MACB_TX_RING_SIZE) +#define MACB_TX_RING_SIZE 2 +#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE) +#define TX_RING_BYTES (sizeof(struct macb_dma_desc) * MACB_TX_RING_SIZE) #else -#define MACB_TX_RING_SIZE 16 -#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE) +#define MACB_TX_RING_SIZE 16 +#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE) #endif -#define MACB_RX_BUFFER_SIZE (4096*4) -#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128) +#define MACB_RX_BUFFER_SIZE (4096*4) +#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128) -#define DEF_TX_RING_PENDING (MACB_TX_RING_SIZE) +#define DEF_TX_RING_PENDING (MACB_TX_RING_SIZE) -#define TX_RING_GAP(macb) \ - (MACB_TX_RING_SIZE - (macb)->tx_pending) +#define TX_RING_GAP(macb) \ + (MACB_TX_RING_SIZE - (macb)->tx_pending) -#define TX_BUFFS_AVAIL(macb) \ - (((macb)->tx_tail <= (macb)->tx_head) ? \ - (macb)->tx_tail + (macb)->tx_pending - (macb)->tx_head : \ - (macb)->tx_tail - (macb)->tx_head - TX_RING_GAP(macb)) +#define TX_BUFFS_AVAIL(macb) \ + (((macb)->tx_tail <= (macb)->tx_head) ? \ + (macb)->tx_tail + (macb)->tx_pending - (macb)->tx_head : \ + (macb)->tx_tail - (macb)->tx_head - TX_RING_GAP(macb)) -#define NEXT_TX(n) (((n) + 1) & (MACB_TX_RING_SIZE - 1)) +#define NEXT_TX(n) (((n) + 1) & (MACB_TX_RING_SIZE - 1)) -#define NEXT_RX(n) (((n) + 1) & (MACB_RX_RING_SIZE - 1)) +#define NEXT_RX(n) (((n) + 1) & (MACB_RX_RING_SIZE - 1)) /* minimum number of free TX descriptors before waking up TX process */ -#define MACB_TX_WAKEUP_THRESH (MACB_TX_RING_SIZE / 4) +#define MACB_TX_WAKEUP_THRESH (MACB_TX_RING_SIZE / 4) -#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \ - | MACB_BIT(ISR_ROVR)) +#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \ + | MACB_BIT(ISR_ROVR)) -#define MACB_TX_TIMEOUT 1000 -#define MACB_AUTONEG_TIMEOUT 5000000 -#define MACB_LINK_TIMEOUT 500000 +#define MACB_TX_TIMEOUT 1000 +#define MACB_AUTONEG_TIMEOUT 5000000 +#define MACB_LINK_TIMEOUT 500000 #define CONFIG_RMII struct macb_dma_desc { - rt_uint32_t addr; - rt_uint32_t ctrl; + rt_uint32_t addr; + rt_uint32_t ctrl; }; -#define RXADDR_USED 0x00000001 -#define RXADDR_WRAP 0x00000002 +#define RXADDR_USED 0x00000001 +#define RXADDR_WRAP 0x00000002 -#define RXBUF_FRMLEN_MASK 0x00000fff -#define RXBUF_FRAME_START 0x00004000 -#define RXBUF_FRAME_END 0x00008000 -#define RXBUF_TYPEID_MATCH 0x00400000 -#define RXBUF_ADDR4_MATCH 0x00800000 -#define RXBUF_ADDR3_MATCH 0x01000000 -#define RXBUF_ADDR2_MATCH 0x02000000 -#define RXBUF_ADDR1_MATCH 0x04000000 -#define RXBUF_BROADCAST 0x80000000 +#define RXBUF_FRMLEN_MASK 0x00000fff +#define RXBUF_FRAME_START 0x00004000 +#define RXBUF_FRAME_END 0x00008000 +#define RXBUF_TYPEID_MATCH 0x00400000 +#define RXBUF_ADDR4_MATCH 0x00800000 +#define RXBUF_ADDR3_MATCH 0x01000000 +#define RXBUF_ADDR2_MATCH 0x02000000 +#define RXBUF_ADDR1_MATCH 0x04000000 +#define RXBUF_BROADCAST 0x80000000 -#define TXBUF_FRMLEN_MASK 0x000007ff -#define TXBUF_FRAME_END 0x00008000 -#define TXBUF_NOCRC 0x00010000 -#define TXBUF_EXHAUSTED 0x08000000 -#define TXBUF_UNDERRUN 0x10000000 -#define TXBUF_MAXRETRY 0x20000000 -#define TXBUF_WRAP 0x40000000 -#define TXBUF_USED 0x80000000 +#define TXBUF_FRMLEN_MASK 0x000007ff +#define TXBUF_FRAME_END 0x00008000 +#define TXBUF_NOCRC 0x00010000 +#define TXBUF_EXHAUSTED 0x08000000 +#define TXBUF_UNDERRUN 0x10000000 +#define TXBUF_MAXRETRY 0x20000000 +#define TXBUF_WRAP 0x40000000 +#define TXBUF_USED 0x80000000 /* Duplex, half or full. */ -#define DUPLEX_HALF 0x00 -#define DUPLEX_FULL 0x01 +#define DUPLEX_HALF 0x00 +#define DUPLEX_FULL 0x01 #define MAX_ADDR_LEN 6 struct rt_macb_eth { - /* inherit from ethernet device */ - struct eth_device parent; + /* inherit from ethernet device */ + struct eth_device parent; - unsigned int regs; + unsigned int regs; - unsigned int rx_tail; - unsigned int tx_head; - unsigned int tx_tail; - unsigned int rx_pending; - unsigned int tx_pending; + unsigned int rx_tail; + unsigned int tx_head; + unsigned int tx_tail; + unsigned int rx_pending; + unsigned int tx_pending; - void *rx_buffer; - void *tx_buffer; - struct macb_dma_desc *rx_ring; - struct macb_dma_desc *tx_ring; + void *rx_buffer; + void *tx_buffer; + struct macb_dma_desc *rx_ring; + struct macb_dma_desc *tx_ring; - unsigned long rx_buffer_dma; - unsigned long tx_buffer_dma; - unsigned long rx_ring_dma; - unsigned long tx_ring_dma; + unsigned long rx_buffer_dma; + unsigned long tx_buffer_dma; + unsigned long rx_ring_dma; + unsigned long tx_ring_dma; - unsigned int tx_stop; + unsigned int tx_stop; - /* interface address info. */ - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ - unsigned short phy_addr; + /* interface address info. */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ + unsigned short phy_addr; - struct rt_semaphore mdio_bus_lock; - struct rt_semaphore tx_lock; - struct rt_semaphore rx_lock; - struct rt_semaphore tx_ack; - rt_uint32_t speed; - rt_uint32_t duplex; - rt_uint32_t link; - struct rt_timer timer; + struct rt_semaphore mdio_bus_lock; + struct rt_semaphore tx_lock; + struct rt_semaphore rx_lock; + struct rt_semaphore tx_ack; + rt_uint32_t speed; + rt_uint32_t duplex; + rt_uint32_t link; + struct rt_timer timer; }; static struct rt_macb_eth macb_device; @@ -179,253 +165,253 @@ static void udelay(rt_uint32_t us) static void rt_macb_isr(int irq, void *param) { - struct rt_macb_eth *macb = (struct rt_macb_eth *)param; - rt_device_t dev = &(macb->parent.parent); - rt_uint32_t status, rsr, tsr; + struct rt_macb_eth *macb = (struct rt_macb_eth *)param; + rt_device_t dev = &(macb->parent.parent); + rt_uint32_t status, rsr, tsr; - status = macb_readl(macb, ISR); + status = macb_readl(macb, ISR); - while (status) { + while (status) { - if (status & MACB_RX_INT_FLAGS) - { - rsr = macb_readl(macb, RSR); - macb_writel(macb, RSR, rsr); - /* a frame has been received */ - eth_device_ready(&(macb_device.parent)); - - } + if (status & MACB_RX_INT_FLAGS) + { + rsr = macb_readl(macb, RSR); + macb_writel(macb, RSR, rsr); + /* a frame has been received */ + eth_device_ready(&(macb_device.parent)); - if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) | - MACB_BIT(ISR_RLE))) - { - macb_tx(macb); - } + } - /* - * Link change detection isn't possible with RMII, so we'll - * add that if/when we get our hands on a full-blown MII PHY. - */ + if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) | + MACB_BIT(ISR_RLE))) + { + macb_tx(macb); + } - if (status & MACB_BIT(HRESP)) - { - /* - * TODO: Reset the hardware, and maybe move the printk - * to a lower-priority context as well (work queue?) - */ - rt_kprintf("%s: DMA bus error: HRESP not OK\n", - dev->parent.name); - } + /* + * Link change detection isn't possible with RMII, so we'll + * add that if/when we get our hands on a full-blown MII PHY. + */ - status = macb_readl(macb, ISR); - } + if (status & MACB_BIT(HRESP)) + { + /* + * TODO: Reset the hardware, and maybe move the printk + * to a lower-priority context as well (work queue?) + */ + rt_kprintf("%s: DMA bus error: HRESP not OK\n", + dev->parent.name); + } + + status = macb_readl(macb, ISR); + } } static int macb_mdio_write(struct rt_macb_eth *macb, rt_uint8_t reg, rt_uint16_t value) { - unsigned long netctl; - unsigned long netstat; - unsigned long frame; + unsigned long netctl; + unsigned long netstat; + unsigned long frame; - rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER); - netctl = macb_readl(macb, NCR); - netctl |= MACB_BIT(MPE); - macb_writel(macb, NCR, netctl); + rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER); + netctl = macb_readl(macb, NCR); + netctl |= MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); - frame = (MACB_BF(SOF, 1) - | MACB_BF(RW, 1) - | MACB_BF(PHYA, macb->phy_addr) - | MACB_BF(REGA, reg) - | MACB_BF(CODE, 2) - | MACB_BF(DATA, value)); - macb_writel(macb, MAN, frame); + frame = (MACB_BF(SOF, 1) + | MACB_BF(RW, 1) + | MACB_BF(PHYA, macb->phy_addr) + | MACB_BF(REGA, reg) + | MACB_BF(CODE, 2) + | MACB_BF(DATA, value)); + macb_writel(macb, MAN, frame); - do { - netstat = macb_readl(macb, NSR); - } while (!(netstat & MACB_BIT(IDLE))); + do { + netstat = macb_readl(macb, NSR); + } while (!(netstat & MACB_BIT(IDLE))); - netctl = macb_readl(macb, NCR); - netctl &= ~MACB_BIT(MPE); - macb_writel(macb, NCR, netctl); - rt_sem_release(&macb->mdio_bus_lock); + netctl = macb_readl(macb, NCR); + netctl &= ~MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); + rt_sem_release(&macb->mdio_bus_lock); } static int macb_mdio_read(struct rt_macb_eth *macb, rt_uint8_t reg) { - unsigned long netctl; - unsigned long netstat; - unsigned long frame; + unsigned long netctl; + unsigned long netstat; + unsigned long frame; - rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER); - netctl = macb_readl(macb, NCR); - netctl |= MACB_BIT(MPE); - macb_writel(macb, NCR, netctl); + rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER); + netctl = macb_readl(macb, NCR); + netctl |= MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); - frame = (MACB_BF(SOF, 1) - | MACB_BF(RW, 2) - | MACB_BF(PHYA, macb->phy_addr) - | MACB_BF(REGA, reg) - | MACB_BF(CODE, 2)); - macb_writel(macb, MAN, frame); + frame = (MACB_BF(SOF, 1) + | MACB_BF(RW, 2) + | MACB_BF(PHYA, macb->phy_addr) + | MACB_BF(REGA, reg) + | MACB_BF(CODE, 2)); + macb_writel(macb, MAN, frame); - do { - netstat = macb_readl(macb, NSR); - } while (!(netstat & MACB_BIT(IDLE))); + do { + netstat = macb_readl(macb, NSR); + } while (!(netstat & MACB_BIT(IDLE))); - frame = macb_readl(macb, MAN); + frame = macb_readl(macb, MAN); - netctl = macb_readl(macb, NCR); - netctl &= ~MACB_BIT(MPE); - macb_writel(macb, NCR, netctl); - rt_sem_release(&macb->mdio_bus_lock); + netctl = macb_readl(macb, NCR); + netctl &= ~MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); + rt_sem_release(&macb->mdio_bus_lock); - return MACB_BFEXT(DATA, frame); + return MACB_BFEXT(DATA, frame); } static void macb_phy_reset(rt_device_t dev) { - int i; - rt_uint16_t status, adv; - struct rt_macb_eth *macb = dev->user_data;; + int i; + rt_uint16_t status, adv; + struct rt_macb_eth *macb = dev->user_data;; - adv = ADVERTISE_CSMA | ADVERTISE_ALL; - macb_mdio_write(macb, MII_ADVERTISE, adv); - rt_kprintf("%s: Starting autonegotiation...\n", dev->parent.name); - macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE - | BMCR_ANRESTART)); + adv = ADVERTISE_CSMA | ADVERTISE_ALL; + macb_mdio_write(macb, MII_ADVERTISE, adv); + rt_kprintf("%s: Starting autonegotiation...\n", dev->parent.name); + macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE + | BMCR_ANRESTART)); - for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) - { - status = macb_mdio_read(macb, MII_BMSR); - if (status & BMSR_ANEGCOMPLETE) - break; - udelay(100); - } + for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) + { + status = macb_mdio_read(macb, MII_BMSR); + if (status & BMSR_ANEGCOMPLETE) + break; + udelay(100); + } - if (status & BMSR_ANEGCOMPLETE) - rt_kprintf("%s: Autonegotiation complete\n", dev->parent.name); - else - rt_kprintf("%s: Autonegotiation timed out (status=0x%04x)\n", - dev->parent.name, status); + if (status & BMSR_ANEGCOMPLETE) + rt_kprintf("%s: Autonegotiation complete\n", dev->parent.name); + else + rt_kprintf("%s: Autonegotiation timed out (status=0x%04x)\n", + dev->parent.name, status); } static int macb_phy_init(rt_device_t dev) { - struct rt_macb_eth *macb = dev->user_data; - rt_uint32_t ncfgr; - rt_uint16_t phy_id, status, adv, lpa; - int media, speed, duplex; - int i; + struct rt_macb_eth *macb = dev->user_data; + rt_uint32_t ncfgr; + rt_uint16_t phy_id, status, adv, lpa; + int media, speed, duplex; + int i; - /* Check if the PHY is up to snuff... */ - phy_id = macb_mdio_read(macb, MII_PHYSID1); - if (phy_id == 0xffff) - { - rt_kprintf("%s: No PHY present\n", dev->parent.name); - return 0; - } + /* Check if the PHY is up to snuff... */ + phy_id = macb_mdio_read(macb, MII_PHYSID1); + if (phy_id == 0xffff) + { + rt_kprintf("%s: No PHY present\n", dev->parent.name); + return 0; + } - status = macb_mdio_read(macb, MII_BMSR); - if (!(status & BMSR_LSTATUS)) - { - /* Try to re-negotiate if we don't have link already. */ - macb_phy_reset(dev); + status = macb_mdio_read(macb, MII_BMSR); + if (!(status & BMSR_LSTATUS)) + { + /* Try to re-negotiate if we don't have link already. */ + macb_phy_reset(dev); - for (i = 0; i < MACB_LINK_TIMEOUT / 100; i++) - { - status = macb_mdio_read(macb, MII_BMSR); - if (status & BMSR_LSTATUS) - break; - udelay(100); - } - } + for (i = 0; i < MACB_LINK_TIMEOUT / 100; i++) + { + status = macb_mdio_read(macb, MII_BMSR); + if (status & BMSR_LSTATUS) + break; + udelay(100); + } + } - if (!(status & BMSR_LSTATUS)) - { - rt_kprintf("%s: link down (status: 0x%04x)\n", - dev->parent.name, status); - return 0; - } - else - { - adv = macb_mdio_read(macb, MII_ADVERTISE); - lpa = macb_mdio_read(macb, MII_LPA); - media = mii_nway_result(lpa & adv); - speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) - ? 1 : 0); - duplex = (media & ADVERTISE_FULL) ? 1 : 0; - rt_kprintf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", - dev->parent.name, - speed ? "100" : "10", - duplex ? "full" : "half", - lpa); + if (!(status & BMSR_LSTATUS)) + { + rt_kprintf("%s: link down (status: 0x%04x)\n", + dev->parent.name, status); + return 0; + } + else + { + adv = macb_mdio_read(macb, MII_ADVERTISE); + lpa = macb_mdio_read(macb, MII_LPA); + media = mii_nway_result(lpa & adv); + speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) + ? 1 : 0); + duplex = (media & ADVERTISE_FULL) ? 1 : 0; + rt_kprintf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", + dev->parent.name, + speed ? "100" : "10", + duplex ? "full" : "half", + lpa); - ncfgr = macb_readl(macb, NCFGR); - ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); - if (speed) - ncfgr |= MACB_BIT(SPD); - if (duplex) - ncfgr |= MACB_BIT(FD); - macb_writel(macb, NCFGR, ncfgr); - return 1; - } + ncfgr = macb_readl(macb, NCFGR); + ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); + if (speed) + ncfgr |= MACB_BIT(SPD); + if (duplex) + ncfgr |= MACB_BIT(FD); + macb_writel(macb, NCFGR, ncfgr); + return 1; + } } void macb_update_link(void *param) { - struct rt_macb_eth *macb = (struct rt_macb_eth *)param; - rt_device_t dev = &macb->parent.parent; - int status, status_change = 0; - rt_uint32_t link; - rt_uint32_t media; - rt_uint16_t adv, lpa; + struct rt_macb_eth *macb = (struct rt_macb_eth *)param; + rt_device_t dev = &macb->parent.parent; + int status, status_change = 0; + rt_uint32_t link; + rt_uint32_t media; + rt_uint16_t adv, lpa; - /* Do a fake read */ - status = macb_mdio_read(macb, MII_BMSR); - if (status < 0) - return; + /* Do a fake read */ + status = macb_mdio_read(macb, MII_BMSR); + if (status < 0) + return; - /* Read link and autonegotiation status */ - status = macb_mdio_read(macb, MII_BMSR); - if (status < 0) - return; - - if ((status & BMSR_LSTATUS) == 0) - link = 0; - else - link = 1; + /* Read link and autonegotiation status */ + status = macb_mdio_read(macb, MII_BMSR); + if (status < 0) + return; - if (link != macb->link) - { - macb->link = link; - status_change = 1; - } + if ((status & BMSR_LSTATUS) == 0) + link = 0; + else + link = 1; - if (status_change) - { - if (macb->link) - { - adv = macb_mdio_read(macb, MII_ADVERTISE); - lpa = macb_mdio_read(macb, MII_LPA); - media = mii_nway_result(lpa & adv); - macb->speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) - ? 100 : 10); - macb->duplex = (media & ADVERTISE_FULL) ? 1 : 0; - rt_kprintf("%s: link up (%dMbps/%s-duplex)\n", - dev->parent.name, macb->speed, - DUPLEX_FULL == macb->duplex ? "Full":"Half"); - eth_device_linkchange(&macb->parent, RT_TRUE); - } - else - { - rt_kprintf("%s: link down\n", dev->parent.name); - eth_device_linkchange(&macb->parent, RT_FALSE); - } + if (link != macb->link) + { + macb->link = link; + status_change = 1; + } - } + if (status_change) + { + if (macb->link) + { + adv = macb_mdio_read(macb, MII_ADVERTISE); + lpa = macb_mdio_read(macb, MII_LPA); + media = mii_nway_result(lpa & adv); + macb->speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) + ? 100 : 10); + macb->duplex = (media & ADVERTISE_FULL) ? 1 : 0; + rt_kprintf("%s: link up (%dMbps/%s-duplex)\n", + dev->parent.name, macb->speed, + DUPLEX_FULL == macb->duplex ? "Full":"Half"); + eth_device_linkchange(&macb->parent, RT_TRUE); + } + else + { + rt_kprintf("%s: link down\n", dev->parent.name); + eth_device_linkchange(&macb->parent, RT_FALSE); + } + + } } @@ -434,190 +420,190 @@ void macb_update_link(void *param) static rt_err_t rt_macb_init(rt_device_t dev) { - struct rt_macb_eth *macb = dev->user_data; - unsigned long paddr; - rt_uint32_t hwaddr_bottom; - rt_uint16_t hwaddr_top; - int i; + struct rt_macb_eth *macb = dev->user_data; + unsigned long paddr; + rt_uint32_t hwaddr_bottom; + rt_uint16_t hwaddr_top; + int i; - /* - * macb_halt should have been called at some point before now, - * so we'll assume the controller is idle. - */ + /* + * macb_halt should have been called at some point before now, + * so we'll assume the controller is idle. + */ - /* initialize DMA descriptors */ - paddr = macb->rx_buffer_dma; - for (i = 0; i < MACB_RX_RING_SIZE; i++) - { - if (i == (MACB_RX_RING_SIZE - 1)) - paddr |= RXADDR_WRAP; - macb->rx_ring[i].addr = paddr; - macb->rx_ring[i].ctrl = 0; - paddr += 128; - } - paddr = macb->tx_buffer_dma; - for (i = 0; i < MACB_TX_RING_SIZE; i++) - { - macb->tx_ring[i].addr = paddr; - if (i == (MACB_TX_RING_SIZE - 1)) - macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP; - else - macb->tx_ring[i].ctrl = TXBUF_USED; - paddr += 1536; - } - macb->rx_tail = macb->tx_head = macb->tx_tail = 0; + /* initialize DMA descriptors */ + paddr = macb->rx_buffer_dma; + for (i = 0; i < MACB_RX_RING_SIZE; i++) + { + if (i == (MACB_RX_RING_SIZE - 1)) + paddr |= RXADDR_WRAP; + macb->rx_ring[i].addr = paddr; + macb->rx_ring[i].ctrl = 0; + paddr += 128; + } + paddr = macb->tx_buffer_dma; + for (i = 0; i < MACB_TX_RING_SIZE; i++) + { + macb->tx_ring[i].addr = paddr; + if (i == (MACB_TX_RING_SIZE - 1)) + macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP; + else + macb->tx_ring[i].ctrl = TXBUF_USED; + paddr += 1536; + } + macb->rx_tail = macb->tx_head = macb->tx_tail = 0; - BD_CACHE_WRITEBACK_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); - BD_CACHE_WRITEBACK_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc)); - macb_writel(macb, RBQP, macb->rx_ring_dma); - macb_writel(macb, TBQP, macb->tx_ring_dma); - - /* set hardware address */ - hwaddr_bottom = (*((rt_uint32_t *)macb->dev_addr)); - macb_writel(macb, SA1B, hwaddr_bottom); - hwaddr_top = (*((rt_uint16_t *)(macb->dev_addr + 4))); - macb_writel(macb, SA1T, hwaddr_top); + BD_CACHE_WRITEBACK_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); + BD_CACHE_WRITEBACK_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc)); + macb_writel(macb, RBQP, macb->rx_ring_dma); + macb_writel(macb, TBQP, macb->tx_ring_dma); - - /* choose RMII or MII mode. This depends on the board */ + /* set hardware address */ + hwaddr_bottom = (*((rt_uint32_t *)macb->dev_addr)); + macb_writel(macb, SA1B, hwaddr_bottom); + hwaddr_top = (*((rt_uint16_t *)(macb->dev_addr + 4))); + macb_writel(macb, SA1T, hwaddr_top); + + + /* choose RMII or MII mode. This depends on the board */ #ifdef CONFIG_RMII - macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); + macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); #else - macb_writel(macb, USRIO, MACB_BIT(CLKEN)); + macb_writel(macb, USRIO, MACB_BIT(CLKEN)); #endif /* CONFIG_RMII */ - if (!macb_phy_init(dev)) - return -RT_ERROR; + if (!macb_phy_init(dev)) + return -RT_ERROR; - /* Enable TX and RX */ - macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(MPE)); - - /* Enable interrupts */ - macb_writel(macb, IER, (MACB_BIT(RCOMP) - | MACB_BIT(RXUBR) - | MACB_BIT(ISR_TUND) - | MACB_BIT(ISR_RLE) - | MACB_BIT(TXERR) - | MACB_BIT(TCOMP) - | MACB_BIT(ISR_ROVR) - | MACB_BIT(HRESP))); - - /* instal interrupt */ - rt_hw_interrupt_install(AT91SAM9260_ID_EMAC, rt_macb_isr, - (void *)macb, "emac"); - rt_hw_interrupt_umask(AT91SAM9260_ID_EMAC); + /* Enable TX and RX */ + macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(MPE)); - rt_timer_init(&macb->timer, "link_timer", - macb_update_link, - (void *)macb, - RT_TICK_PER_SECOND, - RT_TIMER_FLAG_PERIODIC); + /* Enable interrupts */ + macb_writel(macb, IER, (MACB_BIT(RCOMP) + | MACB_BIT(RXUBR) + | MACB_BIT(ISR_TUND) + | MACB_BIT(ISR_RLE) + | MACB_BIT(TXERR) + | MACB_BIT(TCOMP) + | MACB_BIT(ISR_ROVR) + | MACB_BIT(HRESP))); - rt_timer_start(&macb->timer); - - return RT_EOK; + /* instal interrupt */ + rt_hw_interrupt_install(AT91SAM9260_ID_EMAC, rt_macb_isr, + (void *)macb, "emac"); + rt_hw_interrupt_umask(AT91SAM9260_ID_EMAC); + + rt_timer_init(&macb->timer, "link_timer", + macb_update_link, + (void *)macb, + RT_TICK_PER_SECOND, + RT_TIMER_FLAG_PERIODIC); + + rt_timer_start(&macb->timer); + + return RT_EOK; } static rt_err_t rt_macb_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } static rt_err_t rt_macb_close(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_size_t rt_macb_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_size_t rt_macb_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_err_t rt_macb_control(rt_device_t dev, int cmd, void *args) { - switch(cmd) - { - case NIOCTL_GADDR: - /* get mac address */ - if(args) rt_memcpy(args, macb_device.dev_addr, 6); - else return -RT_ERROR; - break; + switch(cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if(args) rt_memcpy(args, macb_device.dev_addr, 6); + else return -RT_ERROR; + break; - default : - break; - } + default : + break; + } - return RT_EOK; + return RT_EOK; } static void macb_tx(struct rt_macb_eth *macb) { - unsigned int tail; - unsigned int head; - rt_uint32_t status; + unsigned int tail; + unsigned int head; + rt_uint32_t status; - status = macb_readl(macb, TSR); - macb_writel(macb, TSR, status); + status = macb_readl(macb, TSR); + macb_writel(macb, TSR, status); - /*rt_kprintf("macb_tx status = %02lx\n", - (unsigned long)status);*/ + /*rt_kprintf("macb_tx status = %02lx\n", + (unsigned long)status);*/ - if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) - { - int i; - rt_kprintf("%s: TX %s, resetting buffers\n", - macb->parent.parent.parent.name, status & MACB_BIT(UND) ? - "underrun" : "retry limit exceeded"); + if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) + { + int i; + rt_kprintf("%s: TX %s, resetting buffers\n", + macb->parent.parent.parent.name, status & MACB_BIT(UND) ? + "underrun" : "retry limit exceeded"); - /* Transfer ongoing, disable transmitter, to avoid confusion */ - if (status & MACB_BIT(TGO)) - macb_writel(macb, NCR, macb_readl(macb, NCR) & ~MACB_BIT(TE)); + /* Transfer ongoing, disable transmitter, to avoid confusion */ + if (status & MACB_BIT(TGO)) + macb_writel(macb, NCR, macb_readl(macb, NCR) & ~MACB_BIT(TE)); - head = macb->tx_head; + head = macb->tx_head; - /*Mark all the buffer as used to avoid sending a lost buffer*/ - for (i = 0; i < MACB_TX_RING_SIZE; i++) - macb->tx_ring[i].ctrl = MACB_BIT(TX_USED); + /*Mark all the buffer as used to avoid sending a lost buffer*/ + for (i = 0; i < MACB_TX_RING_SIZE; i++) + macb->tx_ring[i].ctrl = MACB_BIT(TX_USED); - /* free transmit buffer in upper layer*/ + /* free transmit buffer in upper layer*/ - macb->tx_head = macb->tx_tail = 0; + macb->tx_head = macb->tx_tail = 0; - /* Enable the transmitter again */ - if (status & MACB_BIT(TGO)) - macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TE)); - } + /* Enable the transmitter again */ + if (status & MACB_BIT(TGO)) + macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TE)); + } - if (!(status & MACB_BIT(COMP))) - /* - * This may happen when a buffer becomes complete - * between reading the ISR and scanning the - * descriptors. Nothing to worry about. - */ - return; + if (!(status & MACB_BIT(COMP))) + /* + * This may happen when a buffer becomes complete + * between reading the ISR and scanning the + * descriptors. Nothing to worry about. + */ + return; - head = macb->tx_head; - for (tail = macb->tx_tail; tail != head; tail = NEXT_TX(tail)) - { - rt_uint32_t bufstat; + head = macb->tx_head; + for (tail = macb->tx_tail; tail != head; tail = NEXT_TX(tail)) + { + rt_uint32_t bufstat; - bufstat = macb->tx_ring[tail].ctrl; + bufstat = macb->tx_ring[tail].ctrl; - if (!(bufstat & MACB_BIT(TX_USED))) - break; - } + if (!(bufstat & MACB_BIT(TX_USED))) + break; + } - macb->tx_tail = tail; - if ((macb->tx_stop == 1) && - TX_BUFFS_AVAIL(macb) > MACB_TX_WAKEUP_THRESH) - rt_sem_release(&macb->tx_ack); + macb->tx_tail = tail; + if ((macb->tx_stop == 1) && + TX_BUFFS_AVAIL(macb) > MACB_TX_WAKEUP_THRESH) + rt_sem_release(&macb->tx_ack); } @@ -625,286 +611,286 @@ static void macb_tx(struct rt_macb_eth *macb) /* transmit packet. */ rt_err_t rt_macb_tx( rt_device_t dev, struct pbuf* p) { - unsigned long ctrl; - struct pbuf* q; - rt_uint8_t* bufptr; - rt_uint32_t mapping; - struct rt_macb_eth *macb = dev->user_data; - unsigned int tx_head = macb->tx_head; + unsigned long ctrl; + struct pbuf* q; + rt_uint8_t* bufptr; + rt_uint32_t mapping; + struct rt_macb_eth *macb = dev->user_data; + unsigned int tx_head = macb->tx_head; - rt_sem_take(&macb->tx_lock, RT_WAITING_FOREVER); - if (TX_BUFFS_AVAIL(macb) < 1) - { - rt_sem_release(&macb->tx_lock); - rt_kprintf("Tx Ring full!\n"); - rt_kprintf("tx_head = %u, tx_tail = %u\n", - macb->tx_head, macb->tx_tail); - return -RT_ERROR; - } + rt_sem_take(&macb->tx_lock, RT_WAITING_FOREVER); + if (TX_BUFFS_AVAIL(macb) < 1) + { + rt_sem_release(&macb->tx_lock); + rt_kprintf("Tx Ring full!\n"); + rt_kprintf("tx_head = %u, tx_tail = %u\n", + macb->tx_head, macb->tx_tail); + return -RT_ERROR; + } - macb->tx_stop = 0; + macb->tx_stop = 0; - ctrl = p->tot_len & TXBUF_FRMLEN_MASK; - ctrl |= TXBUF_FRAME_END; - if (tx_head == (MACB_TX_RING_SIZE - 1)) - { - ctrl |= TXBUF_WRAP; - } + ctrl = p->tot_len & TXBUF_FRMLEN_MASK; + ctrl |= TXBUF_FRAME_END; + if (tx_head == (MACB_TX_RING_SIZE - 1)) + { + ctrl |= TXBUF_WRAP; + } #if defined(MACB_TX_SRAM) - bufptr = macb->tx_buffer + tx_head * 1536; + bufptr = macb->tx_buffer + tx_head * 1536; #else - mapping = (unsigned long)macb->tx_buffer + tx_head * 1536; - bufptr = (rt_uint8_t *)mapping; + mapping = (unsigned long)macb->tx_buffer + tx_head * 1536; + bufptr = (rt_uint8_t *)mapping; #endif - for (q = p; q != NULL; q = q->next) - { - memcpy(bufptr, q->payload, q->len); - bufptr += q->len; - } + for (q = p; q != NULL; q = q->next) + { + memcpy(bufptr, q->payload, q->len); + bufptr += q->len; + } #if !defined(MACB_TX_SRAM) - EMAC_CACHE_WRITEBACK(mapping, p->tot_len); + EMAC_CACHE_WRITEBACK(mapping, p->tot_len); #endif - macb->tx_ring[tx_head].ctrl = ctrl; - BD_CACHE_WRITEBACK_INVALIDATE(&macb->tx_ring[tx_head], sizeof(struct macb_dma_desc)); - tx_head = NEXT_TX(tx_head); - macb->tx_head = tx_head; - macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART)); - macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART)); + macb->tx_ring[tx_head].ctrl = ctrl; + BD_CACHE_WRITEBACK_INVALIDATE(&macb->tx_ring[tx_head], sizeof(struct macb_dma_desc)); + tx_head = NEXT_TX(tx_head); + macb->tx_head = tx_head; + macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART)); + macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART)); - if (TX_BUFFS_AVAIL(macb) < 1) - { - macb->tx_stop = 1; - rt_sem_take(&macb->tx_ack, RT_WAITING_FOREVER); - } - rt_sem_release(&macb->tx_lock); + if (TX_BUFFS_AVAIL(macb) < 1) + { + macb->tx_stop = 1; + rt_sem_take(&macb->tx_ack, RT_WAITING_FOREVER); + } + rt_sem_release(&macb->tx_lock); - return RT_EOK; + return RT_EOK; } static void reclaim_rx_buffers(struct rt_macb_eth *macb, - unsigned int new_tail) + unsigned int new_tail) { - unsigned int i; + unsigned int i; - i = macb->rx_tail; - while (i > new_tail) - { - macb->rx_ring[i].addr &= ~RXADDR_USED; - i++; - if (i > MACB_RX_RING_SIZE) - i = 0; - } + i = macb->rx_tail; + while (i > new_tail) + { + macb->rx_ring[i].addr &= ~RXADDR_USED; + i++; + if (i > MACB_RX_RING_SIZE) + i = 0; + } - while (i < new_tail) - { - macb->rx_ring[i].addr &= ~RXADDR_USED; - i++; - } + while (i < new_tail) + { + macb->rx_ring[i].addr &= ~RXADDR_USED; + i++; + } - macb->rx_tail = new_tail; + macb->rx_tail = new_tail; } /* reception packet. */ struct pbuf *rt_macb_rx(rt_device_t dev) { - struct rt_macb_eth *macb = dev->user_data; - struct pbuf* p = RT_NULL; - rt_uint32_t len; - unsigned int rx_tail = macb->rx_tail; - void *buffer; - int wrapped = 0; - rt_uint32_t status; + struct rt_macb_eth *macb = dev->user_data; + struct pbuf* p = RT_NULL; + rt_uint32_t len; + unsigned int rx_tail = macb->rx_tail; + void *buffer; + int wrapped = 0; + rt_uint32_t status; - rt_sem_take(&macb->rx_lock, RT_WAITING_FOREVER); - for (;;) - { - if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED)) - break; + rt_sem_take(&macb->rx_lock, RT_WAITING_FOREVER); + for (;;) + { + if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED)) + break; - status = macb->rx_ring[rx_tail].ctrl; - if (status & RXBUF_FRAME_START) - { - if (rx_tail != macb->rx_tail) - reclaim_rx_buffers(macb, rx_tail); - wrapped = 0; - } + status = macb->rx_ring[rx_tail].ctrl; + if (status & RXBUF_FRAME_START) + { + if (rx_tail != macb->rx_tail) + reclaim_rx_buffers(macb, rx_tail); + wrapped = 0; + } - if (status & RXBUF_FRAME_END) - { - buffer = (void *)((unsigned int)macb->rx_buffer + 128 * macb->rx_tail); - len = status & RXBUF_FRMLEN_MASK; - p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM); - if (!p) - { - rt_kprintf("alloc pbuf failed\n"); - break; - } - if (wrapped) - { - unsigned int headlen, taillen; + if (status & RXBUF_FRAME_END) + { + buffer = (void *)((unsigned int)macb->rx_buffer + 128 * macb->rx_tail); + len = status & RXBUF_FRMLEN_MASK; + p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM); + if (!p) + { + rt_kprintf("alloc pbuf failed\n"); + break; + } + if (wrapped) + { + unsigned int headlen, taillen; - headlen = 128 * (MACB_RX_RING_SIZE - - macb->rx_tail); - taillen = len - headlen; - EMAC_CACHE_INVALIDATE(buffer, headlen); - EMAC_CACHE_INVALIDATE(macb->rx_buffer, taillen); - memcpy((void *)p->payload, buffer, headlen); - memcpy((void *)((unsigned int)p->payload + headlen), - macb->rx_buffer, taillen); - } - else - { - EMAC_CACHE_INVALIDATE(buffer, len); - memcpy((void *)p->payload, buffer, p->len); - } - - if (++rx_tail >= MACB_RX_RING_SIZE) - rx_tail = 0; - reclaim_rx_buffers(macb, rx_tail); - break; - } - else - { - if (++rx_tail >= MACB_RX_RING_SIZE) - { - wrapped = 1; - rx_tail = 0; - } - } - } + headlen = 128 * (MACB_RX_RING_SIZE + - macb->rx_tail); + taillen = len - headlen; + EMAC_CACHE_INVALIDATE(buffer, headlen); + EMAC_CACHE_INVALIDATE(macb->rx_buffer, taillen); + memcpy((void *)p->payload, buffer, headlen); + memcpy((void *)((unsigned int)p->payload + headlen), + macb->rx_buffer, taillen); + } + else + { + EMAC_CACHE_INVALIDATE(buffer, len); + memcpy((void *)p->payload, buffer, p->len); + } - rt_sem_release(&macb->rx_lock); + if (++rx_tail >= MACB_RX_RING_SIZE) + rx_tail = 0; + reclaim_rx_buffers(macb, rx_tail); + break; + } + else + { + if (++rx_tail >= MACB_RX_RING_SIZE) + { + wrapped = 1; + rx_tail = 0; + } + } + } - return p; + rt_sem_release(&macb->rx_lock); + + return p; } void macb_gpio_init() { - /* Pins used for MII and RMII */ - at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20)); - at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20)); + /* Pins used for MII and RMII */ + at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20)); + at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20)); #ifndef GONFIG_RMII - at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29)); - at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29)); + at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29)); + at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29)); #endif } rt_err_t macb_initialize() { - struct rt_macb_eth *macb = &macb_device; - unsigned long macb_hz; - rt_uint32_t ncfgr; - + struct rt_macb_eth *macb = &macb_device; + unsigned long macb_hz; + rt_uint32_t ncfgr; + #if defined(MACB_TX_SRAM) - macb->tx_ring_dma = AT91SAM9260_SRAM0_BASE; - macb->tx_ring = (struct macb_dma_desc *)AT91SAM9260_SRAM0_VIRT_BASE; - macb->tx_buffer = (char *) macb->tx_ring + TX_RING_BYTES; - macb->tx_buffer_dma = macb->tx_ring_dma + TX_RING_BYTES; + macb->tx_ring_dma = AT91SAM9260_SRAM0_BASE; + macb->tx_ring = (struct macb_dma_desc *)AT91SAM9260_SRAM0_VIRT_BASE; + macb->tx_buffer = (char *) macb->tx_ring + TX_RING_BYTES; + macb->tx_buffer_dma = macb->tx_ring_dma + TX_RING_BYTES; #else - macb->tx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); - if (macb->tx_ring == RT_NULL) - goto err1; - EMAC_CACHE_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc)); - macb->tx_ring_dma = emac_virt_to_phys((unsigned long)macb->tx_ring); - macb->tx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->tx_ring); - macb->tx_buffer = rt_malloc(MACB_TX_BUFFER_SIZE); - if (macb->tx_buffer == RT_NULL) - goto err2; - macb->tx_buffer_dma = emac_virt_to_phys((unsigned long)macb->tx_buffer); + macb->tx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); + if (macb->tx_ring == RT_NULL) + goto err1; + EMAC_CACHE_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc)); + macb->tx_ring_dma = emac_virt_to_phys((unsigned long)macb->tx_ring); + macb->tx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->tx_ring); + macb->tx_buffer = rt_malloc(MACB_TX_BUFFER_SIZE); + if (macb->tx_buffer == RT_NULL) + goto err2; + macb->tx_buffer_dma = emac_virt_to_phys((unsigned long)macb->tx_buffer); #endif - macb->rx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); - if (macb->rx_ring == RT_NULL) - goto err3; - EMAC_CACHE_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); - macb->rx_ring_dma = emac_virt_to_phys((unsigned long)macb->rx_ring); - macb->rx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->rx_ring); - macb->rx_buffer = rt_malloc(MACB_RX_BUFFER_SIZE); - if (macb->rx_buffer == RT_NULL) - goto err4; - macb->rx_buffer_dma = emac_virt_to_phys((unsigned long)macb->rx_buffer); + macb->rx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); + if (macb->rx_ring == RT_NULL) + goto err3; + EMAC_CACHE_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); + macb->rx_ring_dma = emac_virt_to_phys((unsigned long)macb->rx_ring); + macb->rx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->rx_ring); + macb->rx_buffer = rt_malloc(MACB_RX_BUFFER_SIZE); + if (macb->rx_buffer == RT_NULL) + goto err4; + macb->rx_buffer_dma = emac_virt_to_phys((unsigned long)macb->rx_buffer); - macb->tx_pending = DEF_TX_RING_PENDING; + macb->tx_pending = DEF_TX_RING_PENDING; - macb->regs = AT91SAM9260_BASE_EMAC; - macb->phy_addr = 0x00; - - /* - * Do some basic initialization so that we at least can talk - * to the PHY - */ - macb_hz = clk_get_rate(clk_get("mck")); - if (macb_hz < 20000000) - ncfgr = MACB_BF(CLK, MACB_CLK_DIV8); - else if (macb_hz < 40000000) - ncfgr = MACB_BF(CLK, MACB_CLK_DIV16); - else if (macb_hz < 80000000) - ncfgr = MACB_BF(CLK, MACB_CLK_DIV32); - else - ncfgr = MACB_BF(CLK, MACB_CLK_DIV64); + macb->regs = AT91SAM9260_BASE_EMAC; + macb->phy_addr = 0x00; - macb_writel(macb, NCFGR, ncfgr); + /* + * Do some basic initialization so that we at least can talk + * to the PHY + */ + macb_hz = clk_get_rate(clk_get("mck")); + if (macb_hz < 20000000) + ncfgr = MACB_BF(CLK, MACB_CLK_DIV8); + else if (macb_hz < 40000000) + ncfgr = MACB_BF(CLK, MACB_CLK_DIV16); + else if (macb_hz < 80000000) + ncfgr = MACB_BF(CLK, MACB_CLK_DIV32); + else + ncfgr = MACB_BF(CLK, MACB_CLK_DIV64); - macb->link = 0; + macb_writel(macb, NCFGR, ncfgr); - return RT_EOK; + macb->link = 0; + + return RT_EOK; err4: - rt_free(macb->rx_ring); - macb->rx_ring = RT_NULL; + rt_free(macb->rx_ring); + macb->rx_ring = RT_NULL; err3: #if !defined(MACB_TX_SRAM) - rt_free(macb->tx_buffer); - macb->tx_buffer = RT_NULL; + rt_free(macb->tx_buffer); + macb->tx_buffer = RT_NULL; err2: - rt_free(macb->tx_ring); - macb->tx_ring = RT_NULL; + rt_free(macb->tx_ring); + macb->tx_ring = RT_NULL; err1: #endif - return -RT_ENOMEM; + return -RT_ENOMEM; } int rt_hw_macb_init(void) { - rt_err_t ret; - at91_sys_write(AT91_PMC + AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); //enable macb clock - macb_gpio_init(); - rt_memset(&macb_device, 0, sizeof(macb_device)); - ret = macb_initialize(); - if (ret != RT_EOK) - { - rt_kprintf("AT91 EMAC initialized failed\n"); - return -1; - } - rt_sem_init(&macb_device.tx_ack, "tx_ack", 0, RT_IPC_FLAG_FIFO); - rt_sem_init(&macb_device.tx_lock, "tx_lock", 1, RT_IPC_FLAG_FIFO); - rt_sem_init(&macb_device.rx_lock, "rx_lock", 1, RT_IPC_FLAG_FIFO); + rt_err_t ret; + at91_sys_write(AT91_PMC + AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); //enable macb clock + macb_gpio_init(); + rt_memset(&macb_device, 0, sizeof(macb_device)); + ret = macb_initialize(); + if (ret != RT_EOK) + { + rt_kprintf("AT91 EMAC initialized failed\n"); + return -1; + } + rt_sem_init(&macb_device.tx_ack, "tx_ack", 0, RT_IPC_FLAG_FIFO); + rt_sem_init(&macb_device.tx_lock, "tx_lock", 1, RT_IPC_FLAG_FIFO); + rt_sem_init(&macb_device.rx_lock, "rx_lock", 1, RT_IPC_FLAG_FIFO); - macb_device.dev_addr[0] = 0x00; - macb_device.dev_addr[1] = 0x60; - macb_device.dev_addr[2] = 0x6E; - macb_device.dev_addr[3] = 0x11; - macb_device.dev_addr[4] = 0x22; - macb_device.dev_addr[5] = 0x33; - - macb_device.parent.parent.init = rt_macb_init; - macb_device.parent.parent.open = rt_macb_open; - macb_device.parent.parent.close = rt_macb_close; - macb_device.parent.parent.read = rt_macb_read; - macb_device.parent.parent.write = rt_macb_write; - macb_device.parent.parent.control = rt_macb_control; - macb_device.parent.parent.user_data = &macb_device; + macb_device.dev_addr[0] = 0x00; + macb_device.dev_addr[1] = 0x60; + macb_device.dev_addr[2] = 0x6E; + macb_device.dev_addr[3] = 0x11; + macb_device.dev_addr[4] = 0x22; + macb_device.dev_addr[5] = 0x33; - macb_device.parent.eth_rx = rt_macb_rx; - macb_device.parent.eth_tx = rt_macb_tx; + macb_device.parent.parent.init = rt_macb_init; + macb_device.parent.parent.open = rt_macb_open; + macb_device.parent.parent.close = rt_macb_close; + macb_device.parent.parent.read = rt_macb_read; + macb_device.parent.parent.write = rt_macb_write; + macb_device.parent.parent.control = rt_macb_control; + macb_device.parent.parent.user_data = &macb_device; - rt_sem_init(&macb_device.mdio_bus_lock, "mdio_bus_lock", 1, RT_IPC_FLAG_FIFO); + macb_device.parent.eth_rx = rt_macb_rx; + macb_device.parent.eth_tx = rt_macb_tx; - eth_device_init(&(macb_device.parent), "e0"); + rt_sem_init(&macb_device.mdio_bus_lock, "mdio_bus_lock", 1, RT_IPC_FLAG_FIFO); - return 0; + eth_device_init(&(macb_device.parent), "e0"); + + return 0; } INIT_DEVICE_EXPORT(rt_hw_macb_init); diff --git a/bsp/at91sam9260/drivers/macb.h b/bsp/at91sam9260/drivers/macb.h index 9df2883534..ed2ad390b7 100644 --- a/bsp/at91sam9260/drivers/macb.h +++ b/bsp/at91sam9260/drivers/macb.h @@ -1,21 +1,7 @@ /* - * File : macb.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -26,319 +12,319 @@ #include /* MACB register offsets */ -#define MACB_NCR 0x0000 -#define MACB_NCFGR 0x0004 -#define MACB_NSR 0x0008 -#define MACB_TSR 0x0014 -#define MACB_RBQP 0x0018 -#define MACB_TBQP 0x001c -#define MACB_RSR 0x0020 -#define MACB_ISR 0x0024 -#define MACB_IER 0x0028 -#define MACB_IDR 0x002c -#define MACB_IMR 0x0030 -#define MACB_MAN 0x0034 -#define MACB_PTR 0x0038 -#define MACB_PFR 0x003c -#define MACB_FTO 0x0040 -#define MACB_SCF 0x0044 -#define MACB_MCF 0x0048 -#define MACB_FRO 0x004c -#define MACB_FCSE 0x0050 -#define MACB_ALE 0x0054 -#define MACB_DTF 0x0058 -#define MACB_LCOL 0x005c -#define MACB_EXCOL 0x0060 -#define MACB_TUND 0x0064 -#define MACB_CSE 0x0068 -#define MACB_RRE 0x006c -#define MACB_ROVR 0x0070 -#define MACB_RSE 0x0074 -#define MACB_ELE 0x0078 -#define MACB_RJA 0x007c -#define MACB_USF 0x0080 -#define MACB_STE 0x0084 -#define MACB_RLE 0x0088 -#define MACB_TPF 0x008c -#define MACB_HRB 0x0090 -#define MACB_HRT 0x0094 -#define MACB_SA1B 0x0098 -#define MACB_SA1T 0x009c -#define MACB_SA2B 0x00a0 -#define MACB_SA2T 0x00a4 -#define MACB_SA3B 0x00a8 -#define MACB_SA3T 0x00ac -#define MACB_SA4B 0x00b0 -#define MACB_SA4T 0x00b4 -#define MACB_TID 0x00b8 -#define MACB_TPQ 0x00bc -#define MACB_USRIO 0x00c0 -#define MACB_WOL 0x00c4 +#define MACB_NCR 0x0000 +#define MACB_NCFGR 0x0004 +#define MACB_NSR 0x0008 +#define MACB_TSR 0x0014 +#define MACB_RBQP 0x0018 +#define MACB_TBQP 0x001c +#define MACB_RSR 0x0020 +#define MACB_ISR 0x0024 +#define MACB_IER 0x0028 +#define MACB_IDR 0x002c +#define MACB_IMR 0x0030 +#define MACB_MAN 0x0034 +#define MACB_PTR 0x0038 +#define MACB_PFR 0x003c +#define MACB_FTO 0x0040 +#define MACB_SCF 0x0044 +#define MACB_MCF 0x0048 +#define MACB_FRO 0x004c +#define MACB_FCSE 0x0050 +#define MACB_ALE 0x0054 +#define MACB_DTF 0x0058 +#define MACB_LCOL 0x005c +#define MACB_EXCOL 0x0060 +#define MACB_TUND 0x0064 +#define MACB_CSE 0x0068 +#define MACB_RRE 0x006c +#define MACB_ROVR 0x0070 +#define MACB_RSE 0x0074 +#define MACB_ELE 0x0078 +#define MACB_RJA 0x007c +#define MACB_USF 0x0080 +#define MACB_STE 0x0084 +#define MACB_RLE 0x0088 +#define MACB_TPF 0x008c +#define MACB_HRB 0x0090 +#define MACB_HRT 0x0094 +#define MACB_SA1B 0x0098 +#define MACB_SA1T 0x009c +#define MACB_SA2B 0x00a0 +#define MACB_SA2T 0x00a4 +#define MACB_SA3B 0x00a8 +#define MACB_SA3T 0x00ac +#define MACB_SA4B 0x00b0 +#define MACB_SA4T 0x00b4 +#define MACB_TID 0x00b8 +#define MACB_TPQ 0x00bc +#define MACB_USRIO 0x00c0 +#define MACB_WOL 0x00c4 /* Bitfields in NCR */ -#define MACB_LB_OFFSET 0 -#define MACB_LB_SIZE 1 -#define MACB_LLB_OFFSET 1 -#define MACB_LLB_SIZE 1 -#define MACB_RE_OFFSET 2 -#define MACB_RE_SIZE 1 -#define MACB_TE_OFFSET 3 -#define MACB_TE_SIZE 1 -#define MACB_MPE_OFFSET 4 -#define MACB_MPE_SIZE 1 -#define MACB_CLRSTAT_OFFSET 5 -#define MACB_CLRSTAT_SIZE 1 -#define MACB_INCSTAT_OFFSET 6 -#define MACB_INCSTAT_SIZE 1 -#define MACB_WESTAT_OFFSET 7 -#define MACB_WESTAT_SIZE 1 -#define MACB_BP_OFFSET 8 -#define MACB_BP_SIZE 1 -#define MACB_TSTART_OFFSET 9 -#define MACB_TSTART_SIZE 1 -#define MACB_THALT_OFFSET 10 -#define MACB_THALT_SIZE 1 -#define MACB_NCR_TPF_OFFSET 11 -#define MACB_NCR_TPF_SIZE 1 -#define MACB_TZQ_OFFSET 12 -#define MACB_TZQ_SIZE 1 +#define MACB_LB_OFFSET 0 +#define MACB_LB_SIZE 1 +#define MACB_LLB_OFFSET 1 +#define MACB_LLB_SIZE 1 +#define MACB_RE_OFFSET 2 +#define MACB_RE_SIZE 1 +#define MACB_TE_OFFSET 3 +#define MACB_TE_SIZE 1 +#define MACB_MPE_OFFSET 4 +#define MACB_MPE_SIZE 1 +#define MACB_CLRSTAT_OFFSET 5 +#define MACB_CLRSTAT_SIZE 1 +#define MACB_INCSTAT_OFFSET 6 +#define MACB_INCSTAT_SIZE 1 +#define MACB_WESTAT_OFFSET 7 +#define MACB_WESTAT_SIZE 1 +#define MACB_BP_OFFSET 8 +#define MACB_BP_SIZE 1 +#define MACB_TSTART_OFFSET 9 +#define MACB_TSTART_SIZE 1 +#define MACB_THALT_OFFSET 10 +#define MACB_THALT_SIZE 1 +#define MACB_NCR_TPF_OFFSET 11 +#define MACB_NCR_TPF_SIZE 1 +#define MACB_TZQ_OFFSET 12 +#define MACB_TZQ_SIZE 1 /* Bitfields in NCFGR */ -#define MACB_SPD_OFFSET 0 -#define MACB_SPD_SIZE 1 -#define MACB_FD_OFFSET 1 -#define MACB_FD_SIZE 1 -#define MACB_BIT_RATE_OFFSET 2 -#define MACB_BIT_RATE_SIZE 1 -#define MACB_JFRAME_OFFSET 3 -#define MACB_JFRAME_SIZE 1 -#define MACB_CAF_OFFSET 4 -#define MACB_CAF_SIZE 1 -#define MACB_NBC_OFFSET 5 -#define MACB_NBC_SIZE 1 -#define MACB_NCFGR_MTI_OFFSET 6 -#define MACB_NCFGR_MTI_SIZE 1 -#define MACB_UNI_OFFSET 7 -#define MACB_UNI_SIZE 1 -#define MACB_BIG_OFFSET 8 -#define MACB_BIG_SIZE 1 -#define MACB_EAE_OFFSET 9 -#define MACB_EAE_SIZE 1 -#define MACB_CLK_OFFSET 10 -#define MACB_CLK_SIZE 2 -#define MACB_RTY_OFFSET 12 -#define MACB_RTY_SIZE 1 -#define MACB_PAE_OFFSET 13 -#define MACB_PAE_SIZE 1 -#define MACB_RBOF_OFFSET 14 -#define MACB_RBOF_SIZE 2 -#define MACB_RLCE_OFFSET 16 -#define MACB_RLCE_SIZE 1 -#define MACB_DRFCS_OFFSET 17 -#define MACB_DRFCS_SIZE 1 -#define MACB_EFRHD_OFFSET 18 -#define MACB_EFRHD_SIZE 1 -#define MACB_IRXFCS_OFFSET 19 -#define MACB_IRXFCS_SIZE 1 +#define MACB_SPD_OFFSET 0 +#define MACB_SPD_SIZE 1 +#define MACB_FD_OFFSET 1 +#define MACB_FD_SIZE 1 +#define MACB_BIT_RATE_OFFSET 2 +#define MACB_BIT_RATE_SIZE 1 +#define MACB_JFRAME_OFFSET 3 +#define MACB_JFRAME_SIZE 1 +#define MACB_CAF_OFFSET 4 +#define MACB_CAF_SIZE 1 +#define MACB_NBC_OFFSET 5 +#define MACB_NBC_SIZE 1 +#define MACB_NCFGR_MTI_OFFSET 6 +#define MACB_NCFGR_MTI_SIZE 1 +#define MACB_UNI_OFFSET 7 +#define MACB_UNI_SIZE 1 +#define MACB_BIG_OFFSET 8 +#define MACB_BIG_SIZE 1 +#define MACB_EAE_OFFSET 9 +#define MACB_EAE_SIZE 1 +#define MACB_CLK_OFFSET 10 +#define MACB_CLK_SIZE 2 +#define MACB_RTY_OFFSET 12 +#define MACB_RTY_SIZE 1 +#define MACB_PAE_OFFSET 13 +#define MACB_PAE_SIZE 1 +#define MACB_RBOF_OFFSET 14 +#define MACB_RBOF_SIZE 2 +#define MACB_RLCE_OFFSET 16 +#define MACB_RLCE_SIZE 1 +#define MACB_DRFCS_OFFSET 17 +#define MACB_DRFCS_SIZE 1 +#define MACB_EFRHD_OFFSET 18 +#define MACB_EFRHD_SIZE 1 +#define MACB_IRXFCS_OFFSET 19 +#define MACB_IRXFCS_SIZE 1 /* Bitfields in NSR */ -#define MACB_NSR_LINK_OFFSET 0 -#define MACB_NSR_LINK_SIZE 1 -#define MACB_MDIO_OFFSET 1 -#define MACB_MDIO_SIZE 1 -#define MACB_IDLE_OFFSET 2 -#define MACB_IDLE_SIZE 1 +#define MACB_NSR_LINK_OFFSET 0 +#define MACB_NSR_LINK_SIZE 1 +#define MACB_MDIO_OFFSET 1 +#define MACB_MDIO_SIZE 1 +#define MACB_IDLE_OFFSET 2 +#define MACB_IDLE_SIZE 1 /* Bitfields in TSR */ -#define MACB_UBR_OFFSET 0 -#define MACB_UBR_SIZE 1 -#define MACB_COL_OFFSET 1 -#define MACB_COL_SIZE 1 -#define MACB_TSR_RLE_OFFSET 2 -#define MACB_TSR_RLE_SIZE 1 -#define MACB_TGO_OFFSET 3 -#define MACB_TGO_SIZE 1 -#define MACB_BEX_OFFSET 4 -#define MACB_BEX_SIZE 1 -#define MACB_COMP_OFFSET 5 -#define MACB_COMP_SIZE 1 -#define MACB_UND_OFFSET 6 -#define MACB_UND_SIZE 1 +#define MACB_UBR_OFFSET 0 +#define MACB_UBR_SIZE 1 +#define MACB_COL_OFFSET 1 +#define MACB_COL_SIZE 1 +#define MACB_TSR_RLE_OFFSET 2 +#define MACB_TSR_RLE_SIZE 1 +#define MACB_TGO_OFFSET 3 +#define MACB_TGO_SIZE 1 +#define MACB_BEX_OFFSET 4 +#define MACB_BEX_SIZE 1 +#define MACB_COMP_OFFSET 5 +#define MACB_COMP_SIZE 1 +#define MACB_UND_OFFSET 6 +#define MACB_UND_SIZE 1 /* Bitfields in RSR */ -#define MACB_BNA_OFFSET 0 -#define MACB_BNA_SIZE 1 -#define MACB_REC_OFFSET 1 -#define MACB_REC_SIZE 1 -#define MACB_OVR_OFFSET 2 -#define MACB_OVR_SIZE 1 +#define MACB_BNA_OFFSET 0 +#define MACB_BNA_SIZE 1 +#define MACB_REC_OFFSET 1 +#define MACB_REC_SIZE 1 +#define MACB_OVR_OFFSET 2 +#define MACB_OVR_SIZE 1 /* Bitfields in ISR/IER/IDR/IMR */ -#define MACB_MFD_OFFSET 0 -#define MACB_MFD_SIZE 1 -#define MACB_RCOMP_OFFSET 1 -#define MACB_RCOMP_SIZE 1 -#define MACB_RXUBR_OFFSET 2 -#define MACB_RXUBR_SIZE 1 -#define MACB_TXUBR_OFFSET 3 -#define MACB_TXUBR_SIZE 1 -#define MACB_ISR_TUND_OFFSET 4 -#define MACB_ISR_TUND_SIZE 1 -#define MACB_ISR_RLE_OFFSET 5 -#define MACB_ISR_RLE_SIZE 1 -#define MACB_TXERR_OFFSET 6 -#define MACB_TXERR_SIZE 1 -#define MACB_TCOMP_OFFSET 7 -#define MACB_TCOMP_SIZE 1 -#define MACB_ISR_LINK_OFFSET 9 -#define MACB_ISR_LINK_SIZE 1 -#define MACB_ISR_ROVR_OFFSET 10 -#define MACB_ISR_ROVR_SIZE 1 -#define MACB_HRESP_OFFSET 11 -#define MACB_HRESP_SIZE 1 -#define MACB_PFR_OFFSET 12 -#define MACB_PFR_SIZE 1 -#define MACB_PTZ_OFFSET 13 -#define MACB_PTZ_SIZE 1 +#define MACB_MFD_OFFSET 0 +#define MACB_MFD_SIZE 1 +#define MACB_RCOMP_OFFSET 1 +#define MACB_RCOMP_SIZE 1 +#define MACB_RXUBR_OFFSET 2 +#define MACB_RXUBR_SIZE 1 +#define MACB_TXUBR_OFFSET 3 +#define MACB_TXUBR_SIZE 1 +#define MACB_ISR_TUND_OFFSET 4 +#define MACB_ISR_TUND_SIZE 1 +#define MACB_ISR_RLE_OFFSET 5 +#define MACB_ISR_RLE_SIZE 1 +#define MACB_TXERR_OFFSET 6 +#define MACB_TXERR_SIZE 1 +#define MACB_TCOMP_OFFSET 7 +#define MACB_TCOMP_SIZE 1 +#define MACB_ISR_LINK_OFFSET 9 +#define MACB_ISR_LINK_SIZE 1 +#define MACB_ISR_ROVR_OFFSET 10 +#define MACB_ISR_ROVR_SIZE 1 +#define MACB_HRESP_OFFSET 11 +#define MACB_HRESP_SIZE 1 +#define MACB_PFR_OFFSET 12 +#define MACB_PFR_SIZE 1 +#define MACB_PTZ_OFFSET 13 +#define MACB_PTZ_SIZE 1 /* Bitfields in MAN */ -#define MACB_DATA_OFFSET 0 -#define MACB_DATA_SIZE 16 -#define MACB_CODE_OFFSET 16 -#define MACB_CODE_SIZE 2 -#define MACB_REGA_OFFSET 18 -#define MACB_REGA_SIZE 5 -#define MACB_PHYA_OFFSET 23 -#define MACB_PHYA_SIZE 5 -#define MACB_RW_OFFSET 28 -#define MACB_RW_SIZE 2 -#define MACB_SOF_OFFSET 30 -#define MACB_SOF_SIZE 2 +#define MACB_DATA_OFFSET 0 +#define MACB_DATA_SIZE 16 +#define MACB_CODE_OFFSET 16 +#define MACB_CODE_SIZE 2 +#define MACB_REGA_OFFSET 18 +#define MACB_REGA_SIZE 5 +#define MACB_PHYA_OFFSET 23 +#define MACB_PHYA_SIZE 5 +#define MACB_RW_OFFSET 28 +#define MACB_RW_SIZE 2 +#define MACB_SOF_OFFSET 30 +#define MACB_SOF_SIZE 2 /* Bitfields in USRIO (AVR32) */ -#define MACB_MII_OFFSET 0 -#define MACB_MII_SIZE 1 -#define MACB_EAM_OFFSET 1 -#define MACB_EAM_SIZE 1 -#define MACB_TX_PAUSE_OFFSET 2 -#define MACB_TX_PAUSE_SIZE 1 -#define MACB_TX_PAUSE_ZERO_OFFSET 3 -#define MACB_TX_PAUSE_ZERO_SIZE 1 +#define MACB_MII_OFFSET 0 +#define MACB_MII_SIZE 1 +#define MACB_EAM_OFFSET 1 +#define MACB_EAM_SIZE 1 +#define MACB_TX_PAUSE_OFFSET 2 +#define MACB_TX_PAUSE_SIZE 1 +#define MACB_TX_PAUSE_ZERO_OFFSET 3 +#define MACB_TX_PAUSE_ZERO_SIZE 1 /* Bitfields in USRIO (AT91) */ -#define MACB_RMII_OFFSET 0 -#define MACB_RMII_SIZE 1 -#define MACB_CLKEN_OFFSET 1 -#define MACB_CLKEN_SIZE 1 +#define MACB_RMII_OFFSET 0 +#define MACB_RMII_SIZE 1 +#define MACB_CLKEN_OFFSET 1 +#define MACB_CLKEN_SIZE 1 /* Bitfields in WOL */ -#define MACB_IP_OFFSET 0 -#define MACB_IP_SIZE 16 -#define MACB_MAG_OFFSET 16 -#define MACB_MAG_SIZE 1 -#define MACB_ARP_OFFSET 17 -#define MACB_ARP_SIZE 1 -#define MACB_SA1_OFFSET 18 -#define MACB_SA1_SIZE 1 -#define MACB_WOL_MTI_OFFSET 19 -#define MACB_WOL_MTI_SIZE 1 +#define MACB_IP_OFFSET 0 +#define MACB_IP_SIZE 16 +#define MACB_MAG_OFFSET 16 +#define MACB_MAG_SIZE 1 +#define MACB_ARP_OFFSET 17 +#define MACB_ARP_SIZE 1 +#define MACB_SA1_OFFSET 18 +#define MACB_SA1_SIZE 1 +#define MACB_WOL_MTI_OFFSET 19 +#define MACB_WOL_MTI_SIZE 1 /* Constants for CLK */ -#define MACB_CLK_DIV8 0 -#define MACB_CLK_DIV16 1 -#define MACB_CLK_DIV32 2 -#define MACB_CLK_DIV64 3 +#define MACB_CLK_DIV8 0 +#define MACB_CLK_DIV16 1 +#define MACB_CLK_DIV32 2 +#define MACB_CLK_DIV64 3 /* Constants for MAN register */ -#define MACB_MAN_SOF 1 -#define MACB_MAN_WRITE 1 -#define MACB_MAN_READ 2 -#define MACB_MAN_CODE 2 +#define MACB_MAN_SOF 1 +#define MACB_MAN_WRITE 1 +#define MACB_MAN_READ 2 +#define MACB_MAN_CODE 2 /* Bit manipulation macros */ -#define MACB_BIT(name) \ - (1 << MACB_##name##_OFFSET) -#define MACB_BF(name,value) \ - (((value) & ((1 << MACB_##name##_SIZE) - 1)) \ - << MACB_##name##_OFFSET) +#define MACB_BIT(name) \ + (1 << MACB_##name##_OFFSET) +#define MACB_BF(name,value) \ + (((value) & ((1 << MACB_##name##_SIZE) - 1)) \ + << MACB_##name##_OFFSET) #define MACB_BFEXT(name,value)\ - (((value) >> MACB_##name##_OFFSET) \ - & ((1 << MACB_##name##_SIZE) - 1)) -#define MACB_BFINS(name,value,old) \ - (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \ - << MACB_##name##_OFFSET)) \ - | MACB_BF(name,value)) + (((value) >> MACB_##name##_OFFSET) \ + & ((1 << MACB_##name##_SIZE) - 1)) +#define MACB_BFINS(name,value,old) \ + (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \ + << MACB_##name##_OFFSET)) \ + | MACB_BF(name,value)) /* Register access macros */ -#define macb_readl(port,reg) \ - readl((port)->regs + MACB_##reg) -#define macb_writel(port,reg,value) \ - writel((value), (port)->regs + MACB_##reg) +#define macb_readl(port,reg) \ + readl((port)->regs + MACB_##reg) +#define macb_writel(port,reg,value) \ + writel((value), (port)->regs + MACB_##reg) struct dma_desc { - rt_uint32_t addr; - rt_uint32_t ctrl; + rt_uint32_t addr; + rt_uint32_t ctrl; }; /* DMA descriptor bitfields */ -#define MACB_RX_USED_OFFSET 0 -#define MACB_RX_USED_SIZE 1 -#define MACB_RX_WRAP_OFFSET 1 -#define MACB_RX_WRAP_SIZE 1 -#define MACB_RX_WADDR_OFFSET 2 -#define MACB_RX_WADDR_SIZE 30 +#define MACB_RX_USED_OFFSET 0 +#define MACB_RX_USED_SIZE 1 +#define MACB_RX_WRAP_OFFSET 1 +#define MACB_RX_WRAP_SIZE 1 +#define MACB_RX_WADDR_OFFSET 2 +#define MACB_RX_WADDR_SIZE 30 -#define MACB_RX_FRMLEN_OFFSET 0 -#define MACB_RX_FRMLEN_SIZE 12 -#define MACB_RX_OFFSET_OFFSET 12 -#define MACB_RX_OFFSET_SIZE 2 -#define MACB_RX_SOF_OFFSET 14 -#define MACB_RX_SOF_SIZE 1 -#define MACB_RX_EOF_OFFSET 15 -#define MACB_RX_EOF_SIZE 1 -#define MACB_RX_CFI_OFFSET 16 -#define MACB_RX_CFI_SIZE 1 -#define MACB_RX_VLAN_PRI_OFFSET 17 -#define MACB_RX_VLAN_PRI_SIZE 3 -#define MACB_RX_PRI_TAG_OFFSET 20 -#define MACB_RX_PRI_TAG_SIZE 1 -#define MACB_RX_VLAN_TAG_OFFSET 21 -#define MACB_RX_VLAN_TAG_SIZE 1 -#define MACB_RX_TYPEID_MATCH_OFFSET 22 -#define MACB_RX_TYPEID_MATCH_SIZE 1 -#define MACB_RX_SA4_MATCH_OFFSET 23 -#define MACB_RX_SA4_MATCH_SIZE 1 -#define MACB_RX_SA3_MATCH_OFFSET 24 -#define MACB_RX_SA3_MATCH_SIZE 1 -#define MACB_RX_SA2_MATCH_OFFSET 25 -#define MACB_RX_SA2_MATCH_SIZE 1 -#define MACB_RX_SA1_MATCH_OFFSET 26 -#define MACB_RX_SA1_MATCH_SIZE 1 -#define MACB_RX_EXT_MATCH_OFFSET 28 -#define MACB_RX_EXT_MATCH_SIZE 1 -#define MACB_RX_UHASH_MATCH_OFFSET 29 -#define MACB_RX_UHASH_MATCH_SIZE 1 -#define MACB_RX_MHASH_MATCH_OFFSET 30 -#define MACB_RX_MHASH_MATCH_SIZE 1 -#define MACB_RX_BROADCAST_OFFSET 31 -#define MACB_RX_BROADCAST_SIZE 1 +#define MACB_RX_FRMLEN_OFFSET 0 +#define MACB_RX_FRMLEN_SIZE 12 +#define MACB_RX_OFFSET_OFFSET 12 +#define MACB_RX_OFFSET_SIZE 2 +#define MACB_RX_SOF_OFFSET 14 +#define MACB_RX_SOF_SIZE 1 +#define MACB_RX_EOF_OFFSET 15 +#define MACB_RX_EOF_SIZE 1 +#define MACB_RX_CFI_OFFSET 16 +#define MACB_RX_CFI_SIZE 1 +#define MACB_RX_VLAN_PRI_OFFSET 17 +#define MACB_RX_VLAN_PRI_SIZE 3 +#define MACB_RX_PRI_TAG_OFFSET 20 +#define MACB_RX_PRI_TAG_SIZE 1 +#define MACB_RX_VLAN_TAG_OFFSET 21 +#define MACB_RX_VLAN_TAG_SIZE 1 +#define MACB_RX_TYPEID_MATCH_OFFSET 22 +#define MACB_RX_TYPEID_MATCH_SIZE 1 +#define MACB_RX_SA4_MATCH_OFFSET 23 +#define MACB_RX_SA4_MATCH_SIZE 1 +#define MACB_RX_SA3_MATCH_OFFSET 24 +#define MACB_RX_SA3_MATCH_SIZE 1 +#define MACB_RX_SA2_MATCH_OFFSET 25 +#define MACB_RX_SA2_MATCH_SIZE 1 +#define MACB_RX_SA1_MATCH_OFFSET 26 +#define MACB_RX_SA1_MATCH_SIZE 1 +#define MACB_RX_EXT_MATCH_OFFSET 28 +#define MACB_RX_EXT_MATCH_SIZE 1 +#define MACB_RX_UHASH_MATCH_OFFSET 29 +#define MACB_RX_UHASH_MATCH_SIZE 1 +#define MACB_RX_MHASH_MATCH_OFFSET 30 +#define MACB_RX_MHASH_MATCH_SIZE 1 +#define MACB_RX_BROADCAST_OFFSET 31 +#define MACB_RX_BROADCAST_SIZE 1 -#define MACB_TX_FRMLEN_OFFSET 0 -#define MACB_TX_FRMLEN_SIZE 11 -#define MACB_TX_LAST_OFFSET 15 -#define MACB_TX_LAST_SIZE 1 -#define MACB_TX_NOCRC_OFFSET 16 -#define MACB_TX_NOCRC_SIZE 1 -#define MACB_TX_BUF_EXHAUSTED_OFFSET 27 -#define MACB_TX_BUF_EXHAUSTED_SIZE 1 -#define MACB_TX_UNDERRUN_OFFSET 28 -#define MACB_TX_UNDERRUN_SIZE 1 -#define MACB_TX_ERROR_OFFSET 29 -#define MACB_TX_ERROR_SIZE 1 -#define MACB_TX_WRAP_OFFSET 30 -#define MACB_TX_WRAP_SIZE 1 -#define MACB_TX_USED_OFFSET 31 -#define MACB_TX_USED_SIZE 1 +#define MACB_TX_FRMLEN_OFFSET 0 +#define MACB_TX_FRMLEN_SIZE 11 +#define MACB_TX_LAST_OFFSET 15 +#define MACB_TX_LAST_SIZE 1 +#define MACB_TX_NOCRC_OFFSET 16 +#define MACB_TX_NOCRC_SIZE 1 +#define MACB_TX_BUF_EXHAUSTED_OFFSET 27 +#define MACB_TX_BUF_EXHAUSTED_SIZE 1 +#define MACB_TX_UNDERRUN_OFFSET 28 +#define MACB_TX_UNDERRUN_SIZE 1 +#define MACB_TX_ERROR_OFFSET 29 +#define MACB_TX_ERROR_SIZE 1 +#define MACB_TX_WRAP_OFFSET 30 +#define MACB_TX_WRAP_SIZE 1 +#define MACB_TX_USED_OFFSET 31 +#define MACB_TX_USED_SIZE 1 extern int rt_hw_macb_init(); diff --git a/bsp/at91sam9260/drivers/mii.h b/bsp/at91sam9260/drivers/mii.h index 2f6dd18e71..03d914b7c3 100644 --- a/bsp/at91sam9260/drivers/mii.h +++ b/bsp/at91sam9260/drivers/mii.h @@ -1,21 +1,7 @@ /* - * File : mii.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -36,7 +22,7 @@ #define MII_EXPANSION 0x06 /* Expansion register */ #define MII_CTRL1000 0x09 /* 1000BASE-T control */ #define MII_STAT1000 0x0a /* 1000BASE-T status */ -#define MII_ESTATUS 0x0f /* Extended Status */ +#define MII_ESTATUS 0x0f /* Extended Status */ #define MII_DCOUNTER 0x12 /* Disconnect counter */ #define MII_FCSCOUNTER 0x13 /* False carrier counter */ #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ @@ -51,7 +37,7 @@ /* Basic mode control register. */ #define BMCR_RESV 0x003f /* Unused... */ -#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ #define BMCR_CTST 0x0080 /* Collision test */ #define BMCR_FULLDPLX 0x0100 /* Full duplex */ #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ @@ -70,7 +56,7 @@ #define BMSR_RFAULT 0x0010 /* Remote fault detected */ #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ #define BMSR_RESV 0x00c0 /* Unused... */ -#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ +#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */ #define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */ #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ @@ -99,7 +85,7 @@ #define ADVERTISE_NPAGE 0x8000 /* Next page bit */ #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ - ADVERTISE_CSMA) + ADVERTISE_CSMA) #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ ADVERTISE_100HALF | ADVERTISE_100FULL) @@ -121,8 +107,8 @@ #define LPA_LPACK 0x4000 /* Link partner acked us */ #define LPA_NPAGE 0x8000 /* Next page bit */ -#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) -#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) +#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) /* Expansion register for auto-negotiation. */ #define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ @@ -132,8 +118,8 @@ #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ #define EXPANSION_RESV 0xffe0 /* Unused... */ -#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ -#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ +#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ +#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ /* N-way test register. */ #define NWAYTEST_RESV1 0x00ff /* Unused... */ @@ -151,8 +137,8 @@ #define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */ /* Flow control flags */ -#define FLOW_CTRL_TX 0x01 -#define FLOW_CTRL_RX 0x02 +#define FLOW_CTRL_TX 0x01 +#define FLOW_CTRL_RX 0x02 /** * mii_nway_result diff --git a/bsp/at91sam9260/drivers/usart.c b/bsp/at91sam9260/drivers/usart.c index fb91393b3c..2d493a21bb 100644 --- a/bsp/at91sam9260/drivers/usart.c +++ b/bsp/at91sam9260/drivers/usart.c @@ -1,21 +1,7 @@ /* - * File : usart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -28,54 +14,54 @@ #include #include -#define RXRDY 0x01 -#define TXRDY (1 << 1) +#define RXRDY 0x01 +#define TXRDY (1 << 1) typedef struct uartport { - volatile rt_uint32_t CR; - volatile rt_uint32_t MR; - volatile rt_uint32_t IER; - volatile rt_uint32_t IDR; - volatile rt_uint32_t IMR; - volatile rt_uint32_t CSR; - volatile rt_uint32_t RHR; - volatile rt_uint32_t THR; - volatile rt_uint32_t BRGR; - volatile rt_uint32_t RTOR; - volatile rt_uint32_t TTGR; - volatile rt_uint32_t reserved0[5]; - volatile rt_uint32_t FIDI; - volatile rt_uint32_t NER; - volatile rt_uint32_t reserved1; - volatile rt_uint32_t IFR; - volatile rt_uint32_t reserved2[44]; - volatile rt_uint32_t RPR; - volatile rt_uint32_t RCR; - volatile rt_uint32_t TPR; - volatile rt_uint32_t TCR; - volatile rt_uint32_t RNPR; - volatile rt_uint32_t RNCR; - volatile rt_uint32_t TNPR; - volatile rt_uint32_t TNCR; - volatile rt_uint32_t PTCR; - volatile rt_uint32_t PTSR; + volatile rt_uint32_t CR; + volatile rt_uint32_t MR; + volatile rt_uint32_t IER; + volatile rt_uint32_t IDR; + volatile rt_uint32_t IMR; + volatile rt_uint32_t CSR; + volatile rt_uint32_t RHR; + volatile rt_uint32_t THR; + volatile rt_uint32_t BRGR; + volatile rt_uint32_t RTOR; + volatile rt_uint32_t TTGR; + volatile rt_uint32_t reserved0[5]; + volatile rt_uint32_t FIDI; + volatile rt_uint32_t NER; + volatile rt_uint32_t reserved1; + volatile rt_uint32_t IFR; + volatile rt_uint32_t reserved2[44]; + volatile rt_uint32_t RPR; + volatile rt_uint32_t RCR; + volatile rt_uint32_t TPR; + volatile rt_uint32_t TCR; + volatile rt_uint32_t RNPR; + volatile rt_uint32_t RNCR; + volatile rt_uint32_t TNPR; + volatile rt_uint32_t TNCR; + volatile rt_uint32_t PTCR; + volatile rt_uint32_t PTSR; }uartport; #define CIDR FIDI #define EXID NER #define FNR reserved1 -#define DBGU ((struct uartport *)AT91SAM9260_BASE_DBGU) +#define DBGU ((struct uartport *)AT91SAM9260_BASE_DBGU) -#define UART0 ((struct uartport *)AT91SAM9260_BASE_US0) -#define UART1 ((struct uartport *)AT91SAM9260_BASE_US1) -#define UART2 ((struct uartport *)AT91SAM9260_BASE_US2) -#define UART3 ((struct uartport *)AT91SAM9260_BASE_US3) +#define UART0 ((struct uartport *)AT91SAM9260_BASE_US0) +#define UART1 ((struct uartport *)AT91SAM9260_BASE_US1) +#define UART2 ((struct uartport *)AT91SAM9260_BASE_US2) +#define UART3 ((struct uartport *)AT91SAM9260_BASE_US3) struct at91_uart { - uartport *port; - int irq; + uartport *port; + int irq; }; @@ -85,18 +71,18 @@ struct at91_uart { */ void rt_at91_usart_handler(int vector, void *param) { - int status; - struct at91_uart *uart; - rt_device_t dev = (rt_device_t)param; - uart = (struct at91_uart *)dev->user_data; - status = uart->port->CSR; - if (!(status & uart->port->IMR)) - { - return; - } - rt_interrupt_enter(); - rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND); - rt_interrupt_leave(); + int status; + struct at91_uart *uart; + rt_device_t dev = (rt_device_t)param; + uart = (struct at91_uart *)dev->user_data; + status = uart->port->CSR; + if (!(status & uart->port->IMR)) + { + return; + } + rt_interrupt_enter(); + rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND); + rt_interrupt_leave(); } /** @@ -105,67 +91,67 @@ void rt_at91_usart_handler(int vector, void *param) static rt_err_t at91_usart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { - int div; - int mode = 0; - struct at91_uart *uart; + int div; + int mode = 0; + struct at91_uart *uart; - RT_ASSERT(serial != RT_NULL); + RT_ASSERT(serial != RT_NULL); RT_ASSERT(cfg != RT_NULL); - uart = (struct at91_uart *)serial->parent.user_data; + uart = (struct at91_uart *)serial->parent.user_data; - uart->port->CR = AT91_US_RSTTX | AT91_US_RSTRX | - AT91_US_RXDIS | AT91_US_TXDIS; - mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK | - AT91_US_CHMODE_NORMAL; - switch (cfg->data_bits) - { - case DATA_BITS_8: - mode |= AT91_US_CHRL_8; - break; - case DATA_BITS_7: - mode |= AT91_US_CHRL_7; - break; - case DATA_BITS_6: - mode |= AT91_US_CHRL_6; - break; - case DATA_BITS_5: - mode |= AT91_US_CHRL_5; - break; - default: - mode |= AT91_US_CHRL_8; - break; - } + uart->port->CR = AT91_US_RSTTX | AT91_US_RSTRX | + AT91_US_RXDIS | AT91_US_TXDIS; + mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK | + AT91_US_CHMODE_NORMAL; + switch (cfg->data_bits) + { + case DATA_BITS_8: + mode |= AT91_US_CHRL_8; + break; + case DATA_BITS_7: + mode |= AT91_US_CHRL_7; + break; + case DATA_BITS_6: + mode |= AT91_US_CHRL_6; + break; + case DATA_BITS_5: + mode |= AT91_US_CHRL_5; + break; + default: + mode |= AT91_US_CHRL_8; + break; + } - switch (cfg->stop_bits) - { - case STOP_BITS_2: - mode |= AT91_US_NBSTOP_2; - break; - case STOP_BITS_1: - default: - mode |= AT91_US_NBSTOP_1; - break; - } + switch (cfg->stop_bits) + { + case STOP_BITS_2: + mode |= AT91_US_NBSTOP_2; + break; + case STOP_BITS_1: + default: + mode |= AT91_US_NBSTOP_1; + break; + } - switch (cfg->parity) - { - case PARITY_ODD: - mode |= AT91_US_PAR_ODD; - break; - case PARITY_EVEN: - mode |= AT91_US_PAR_EVEN; - break; - case PARITY_NONE: - default: - mode |= AT91_US_PAR_NONE; - break; - } + switch (cfg->parity) + { + case PARITY_ODD: + mode |= AT91_US_PAR_ODD; + break; + case PARITY_EVEN: + mode |= AT91_US_PAR_EVEN; + break; + case PARITY_NONE: + default: + mode |= AT91_US_PAR_NONE; + break; + } - uart->port->MR = mode; - div = (clk_get_rate(clk_get("mck")) / 16 + cfg->baud_rate/2) / cfg->baud_rate; - uart->port->BRGR = div; - uart->port->CR = AT91_US_RXEN | AT91_US_TXEN; - uart->port->IER = 0x01; + uart->port->MR = mode; + div = (clk_get_rate(clk_get("mck")) / 16 + cfg->baud_rate/2) / cfg->baud_rate; + uart->port->BRGR = div; + uart->port->CR = AT91_US_RXEN | AT91_US_TXEN; + uart->port->IER = 0x01; return RT_EOK; } @@ -182,11 +168,11 @@ static rt_err_t at91_usart_control(struct rt_serial_device *serial, { case RT_DEVICE_CTRL_CLR_INT: /* disable rx irq */ - rt_hw_interrupt_mask(uart->irq); + rt_hw_interrupt_mask(uart->irq); break; case RT_DEVICE_CTRL_SET_INT: /* enable rx irq */ - rt_hw_interrupt_umask(uart->irq); + rt_hw_interrupt_umask(uart->irq); break; } @@ -196,10 +182,10 @@ static rt_err_t at91_usart_control(struct rt_serial_device *serial, static int at91_usart_putc(struct rt_serial_device *serial, char c) { rt_uint32_t level; - struct at91_uart *uart = serial->parent.user_data; + struct at91_uart *uart = serial->parent.user_data; while (!(uart->port->CSR & TXRDY)); - uart->port->THR = c; + uart->port->THR = c; return 1; } @@ -207,16 +193,16 @@ static int at91_usart_putc(struct rt_serial_device *serial, char c) static int at91_usart_getc(struct rt_serial_device *serial) { int result; - struct at91_uart *uart = serial->parent.user_data; + struct at91_uart *uart = serial->parent.user_data; if (uart->port->CSR & RXRDY) - { - result = uart->port->RHR & 0xff; - } - else - { - result = -1; - } + { + result = uart->port->RHR & 0xff; + } + else + { + result = -1; + } return result; } @@ -232,8 +218,8 @@ static const struct rt_uart_ops at91_usart_ops = #if defined(RT_USING_DBGU) static struct rt_serial_device serial_dbgu; struct at91_uart dbgu = { - DBGU, - AT91_ID_SYS + DBGU, + AT91_ID_SYS }; #endif @@ -241,82 +227,82 @@ struct at91_uart dbgu = { #if defined(RT_USING_UART0) static struct rt_serial_device serial0; struct at91_uart uart0 = { - UART0, - AT91SAM9260_ID_US0 + UART0, + AT91SAM9260_ID_US0 }; #endif #if defined(RT_USING_UART1) static struct rt_serial_device serial1; struct at91_uart uart1 = { - UART1, - AT91SAM9260_ID_US1 + UART1, + AT91SAM9260_ID_US1 }; #endif #if defined(RT_USING_UART2) static struct rt_serial_device serial2; struct at91_uart uart2 = { - UART2, - AT91SAM9260_ID_US2 + UART2, + AT91SAM9260_ID_US2 }; #endif #if defined(RT_USING_UART3) static struct rt_serial_device serial3; struct at91_uart uart3 = { - UART3, - AT91SAM9260_ID_US3 + UART3, + AT91SAM9260_ID_US3 }; #endif void at91_usart_gpio_init(void) { - rt_uint32_t val; + rt_uint32_t val; #ifdef RT_USING_DBGU - at91_sys_write(AT91_PIOB + PIO_IDR, (1<<14)|(1<<15)); - //at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6)); - at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<14)|(1<<15)); - at91_sys_write(AT91_PIOB + PIO_ASR, (1<<14)|(1<<15)); - at91_sys_write(AT91_PIOB + PIO_PDR, (1<<14)|(1<<15)); - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); + at91_sys_write(AT91_PIOB + PIO_IDR, (1<<14)|(1<<15)); + //at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6)); + at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<14)|(1<<15)); + at91_sys_write(AT91_PIOB + PIO_ASR, (1<<14)|(1<<15)); + at91_sys_write(AT91_PIOB + PIO_PDR, (1<<14)|(1<<15)); + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); #endif #ifdef RT_USING_UART0 - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0); - at91_sys_write(AT91_PIOB + PIO_IDR, (1<<4)|(1<<5)); - at91_sys_write(AT91_PIOB + PIO_PUER, (1<<4)); - at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<5)); - at91_sys_write(AT91_PIOB + PIO_ASR, (1<<4)|(1<<5)); - at91_sys_write(AT91_PIOB + PIO_PDR, (1<<4)|(1<<5)); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0); + at91_sys_write(AT91_PIOB + PIO_IDR, (1<<4)|(1<<5)); + at91_sys_write(AT91_PIOB + PIO_PUER, (1<<4)); + at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<5)); + at91_sys_write(AT91_PIOB + PIO_ASR, (1<<4)|(1<<5)); + at91_sys_write(AT91_PIOB + PIO_PDR, (1<<4)|(1<<5)); #endif #ifdef RT_USING_UART1 - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1); - at91_sys_write(AT91_PIOB + PIO_IDR, (1<<6)|(1<<7)); - at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6)); - at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<7)); - at91_sys_write(AT91_PIOB + PIO_ASR, (1<<6)|(1<<7)); - at91_sys_write(AT91_PIOB + PIO_PDR, (1<<6)|(1<<7)); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1); + at91_sys_write(AT91_PIOB + PIO_IDR, (1<<6)|(1<<7)); + at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6)); + at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<7)); + at91_sys_write(AT91_PIOB + PIO_ASR, (1<<6)|(1<<7)); + at91_sys_write(AT91_PIOB + PIO_PDR, (1<<6)|(1<<7)); #endif #ifdef RT_USING_UART2 - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2); - at91_sys_write(AT91_PIOB + PIO_IDR, (1<<8)|(1<<9)); - at91_sys_write(AT91_PIOB + PIO_PUER, (1<<8)); - at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<9)); - at91_sys_write(AT91_PIOB + PIO_ASR, (1<<8)|(1<<9)); - at91_sys_write(AT91_PIOB + PIO_PDR, (1<<8)|(1<<9)); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2); + at91_sys_write(AT91_PIOB + PIO_IDR, (1<<8)|(1<<9)); + at91_sys_write(AT91_PIOB + PIO_PUER, (1<<8)); + at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<9)); + at91_sys_write(AT91_PIOB + PIO_ASR, (1<<8)|(1<<9)); + at91_sys_write(AT91_PIOB + PIO_PDR, (1<<8)|(1<<9)); #endif #ifdef RT_USING_UART3 - at91_sys_write(AT91_PMC_PCER, 1< #include -#define PIN_BASE AIC_IRQS +#define PIN_BASE AIC_IRQS -#define MAX_GPIO_BANKS 3 +#define MAX_GPIO_BANKS 3 -#define PIN_IRQS (MAX_GPIO_BANKS*32) +#define PIN_IRQS (MAX_GPIO_BANKS*32) /* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */ -#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0) -#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1) -#define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2) -#define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3) -#define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4) -#define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5) -#define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6) -#define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7) -#define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8) -#define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9) -#define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10) -#define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11) -#define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12) -#define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13) -#define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14) -#define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15) -#define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16) -#define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17) -#define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18) -#define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19) -#define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20) -#define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21) -#define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22) -#define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23) -#define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24) -#define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25) -#define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26) -#define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27) -#define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28) -#define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29) -#define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30) -#define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31) +#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0) +#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1) +#define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2) +#define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3) +#define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4) +#define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5) +#define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6) +#define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7) +#define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8) +#define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9) +#define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10) +#define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11) +#define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12) +#define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13) +#define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14) +#define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15) +#define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16) +#define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17) +#define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18) +#define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19) +#define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20) +#define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21) +#define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22) +#define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23) +#define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24) +#define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25) +#define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26) +#define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27) +#define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28) +#define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29) +#define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30) +#define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31) -#define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0) -#define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1) -#define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2) -#define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3) -#define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4) -#define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5) -#define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6) -#define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7) -#define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8) -#define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9) -#define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10) -#define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11) -#define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12) -#define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13) -#define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14) -#define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15) -#define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16) -#define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17) -#define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18) -#define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19) -#define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20) -#define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21) -#define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22) -#define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23) -#define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24) -#define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25) -#define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26) -#define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27) -#define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28) -#define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29) -#define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30) -#define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31) +#define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0) +#define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1) +#define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2) +#define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3) +#define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4) +#define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5) +#define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6) +#define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7) +#define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8) +#define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9) +#define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10) +#define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11) +#define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12) +#define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13) +#define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14) +#define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15) +#define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16) +#define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17) +#define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18) +#define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19) +#define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20) +#define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21) +#define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22) +#define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23) +#define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24) +#define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25) +#define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26) +#define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27) +#define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28) +#define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29) +#define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30) +#define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31) -#define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0) -#define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1) -#define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2) -#define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3) -#define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4) -#define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5) -#define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6) -#define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7) -#define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8) -#define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9) -#define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10) -#define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11) -#define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12) -#define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13) -#define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14) -#define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15) -#define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16) -#define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17) -#define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18) -#define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19) -#define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20) -#define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21) -#define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22) -#define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23) -#define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24) -#define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25) -#define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26) -#define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27) -#define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28) -#define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29) -#define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30) -#define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31) +#define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0) +#define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1) +#define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2) +#define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3) +#define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4) +#define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5) +#define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6) +#define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7) +#define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8) +#define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9) +#define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10) +#define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11) +#define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12) +#define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13) +#define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14) +#define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15) +#define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16) +#define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17) +#define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18) +#define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19) +#define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20) +#define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21) +#define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22) +#define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23) +#define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24) +#define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25) +#define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26) +#define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27) +#define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28) +#define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29) +#define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30) +#define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31) rt_inline rt_uint32_t gpio_to_irq(rt_uint32_t gpio) { - return gpio; + return gpio; } #endif diff --git a/bsp/at91sam9260/platform/interrupt.c b/bsp/at91sam9260/platform/interrupt.c index 0708460578..7c40ffbdad 100644 --- a/bsp/at91sam9260/platform/interrupt.c +++ b/bsp/at91sam9260/platform/interrupt.c @@ -1,21 +1,7 @@ /* - * File : interrupt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -189,7 +175,7 @@ static void at91_gpio_irq_init() rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, name[i]); irq_desc[idx].counter = 0; #endif - idx++; + idx++; } rt_hw_interrupt_umask(AT91SAM9260_ID_PIOA); @@ -322,7 +308,7 @@ void rt_hw_interrupt_umask(int irq) * @param name the interrupt name * @return old handler */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, const char *name) { rt_isr_handler_t old_handler = RT_NULL; @@ -336,7 +322,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, irq_desc[vector].param = param; #ifdef RT_USING_INTERRUPT_INFO rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name); - irq_desc[vector].counter = 0; + irq_desc[vector].counter = 0; #endif } } @@ -414,16 +400,16 @@ void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id) #ifdef RT_USING_INTERRUPT_INFO void list_irq(void) { - int irq; + int irq; - rt_kprintf("number\tcount\tname\n"); - for (irq = 0; irq < MAX_HANDLERS; irq++) - { - if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default"))) - { - rt_kprintf("%02ld: %10ld %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name); - } - } + rt_kprintf("number\tcount\tname\n"); + for (irq = 0; irq < MAX_HANDLERS; irq++) + { + if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default"))) + { + rt_kprintf("%02ld: %10ld %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name); + } + } } #include diff --git a/bsp/at91sam9260/platform/interrupt.h b/bsp/at91sam9260/platform/interrupt.h index 7780e7a3a8..0375164e00 100644 --- a/bsp/at91sam9260/platform/interrupt.h +++ b/bsp/at91sam9260/platform/interrupt.h @@ -1,21 +1,7 @@ /* - * File : interrupt.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/at91sam9260/platform/io.h b/bsp/at91sam9260/platform/io.h index 5cb9cac782..3e41feee90 100644 --- a/bsp/at91sam9260/platform/io.h +++ b/bsp/at91sam9260/platform/io.h @@ -1,21 +1,7 @@ /* - * File : io.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -25,31 +11,31 @@ #ifndef __ASM_ARCH_IO_H #define __ASM_ARCH_IO_H -#define AT91_BASE_SYS 0xffffe800 +#define AT91_BASE_SYS 0xffffe800 -#define IO_SPACE_LIMIT 0xFFFFFFFF +#define IO_SPACE_LIMIT 0xFFFFFFFF -#define readb(a) (*(volatile unsigned char *)(a)) -#define readw(a) (*(volatile unsigned short *)(a)) -#define readl(a) (*(volatile unsigned int *)(a)) +#define readb(a) (*(volatile unsigned char *)(a)) +#define readw(a) (*(volatile unsigned short *)(a)) +#define readl(a) (*(volatile unsigned int *)(a)) -#define writeb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define writew(v,a) (*(volatile unsigned short *)(a) = (v)) -#define writel(v,a) (*(volatile unsigned int *)(a) = (v)) +#define writeb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define writew(v,a) (*(volatile unsigned short *)(a) = (v)) +#define writel(v,a) (*(volatile unsigned int *)(a) = (v)) rt_inline unsigned int at91_sys_read(unsigned int reg_offset) { - unsigned int addr = AT91_BASE_SYS; + unsigned int addr = AT91_BASE_SYS; - return readl(addr + reg_offset); + return readl(addr + reg_offset); } rt_inline void at91_sys_write(unsigned int reg_offset, unsigned long value) { - unsigned int addr = AT91_BASE_SYS; + unsigned int addr = AT91_BASE_SYS; - writel(value, addr + reg_offset); + writel(value, addr + reg_offset); } diff --git a/bsp/at91sam9260/platform/irq.h b/bsp/at91sam9260/platform/irq.h index fe1fea41d0..76d4200d3b 100644 --- a/bsp/at91sam9260/platform/irq.h +++ b/bsp/at91sam9260/platform/irq.h @@ -1,27 +1,13 @@ /* - * File : irq.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2011-01-13 weety first version */ - + #ifndef __IRQ_H__ #define __IRQ_H__ @@ -32,18 +18,18 @@ extern "C" { /* * IRQ line status. * - * Bits 0-7 are reserved + * Bits 0-7 are reserved * * IRQ types */ -#define IRQ_TYPE_NONE 0x00000000 /* Default, unspecified type */ -#define IRQ_TYPE_EDGE_RISING 0x00000001 /* Edge rising type */ -#define IRQ_TYPE_EDGE_FALLING 0x00000002 /* Edge falling type */ +#define IRQ_TYPE_NONE 0x00000000 /* Default, unspecified type */ +#define IRQ_TYPE_EDGE_RISING 0x00000001 /* Edge rising type */ +#define IRQ_TYPE_EDGE_FALLING 0x00000002 /* Edge falling type */ #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) -#define IRQ_TYPE_LEVEL_HIGH 0x00000004 /* Level high type */ -#define IRQ_TYPE_LEVEL_LOW 0x00000008 /* Level low type */ -#define IRQ_TYPE_SENSE_MASK 0x0000000f /* Mask of the above */ -#define IRQ_TYPE_PROBE 0x00000010 /* Probing in progress */ +#define IRQ_TYPE_LEVEL_HIGH 0x00000004 /* Level high type */ +#define IRQ_TYPE_LEVEL_LOW 0x00000008 /* Level low type */ +#define IRQ_TYPE_SENSE_MASK 0x0000000f /* Mask of the above */ +#define IRQ_TYPE_PROBE 0x00000010 /* Probing in progress */ #ifdef __cplusplus } diff --git a/bsp/at91sam9260/platform/reset.c b/bsp/at91sam9260/platform/reset.c index 699e29efd4..4b5462a9e1 100644 --- a/bsp/at91sam9260/platform/reset.c +++ b/bsp/at91sam9260/platform/reset.c @@ -1,21 +1,7 @@ /* - * File : reset.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -33,12 +19,12 @@ void machine_reset(void) { - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); + at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); } void machine_shutdown(void) { - at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); + at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); } #ifdef RT_USING_FINSH @@ -49,14 +35,14 @@ FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, reset, restart the system); #ifdef FINSH_USING_MSH int cmd_reset(int argc, char** argv) { - rt_hw_cpu_reset(); - return 0; + rt_hw_cpu_reset(); + return 0; } int cmd_shutdown(int argc, char** argv) { - rt_hw_cpu_shutdown(); - return 0; + rt_hw_cpu_shutdown(); + return 0; } FINSH_FUNCTION_EXPORT_ALIAS(cmd_reset, __cmd_reset, restart the system.); diff --git a/bsp/at91sam9260/platform/rt_low_level_init.c b/bsp/at91sam9260/platform/rt_low_level_init.c index b7bc8e0a1a..31ddf27ae6 100644 --- a/bsp/at91sam9260/platform/rt_low_level_init.c +++ b/bsp/at91sam9260/platform/rt_low_level_init.c @@ -1,29 +1,15 @@ /* - * File : rt_low_level_init.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2015-04-14 ArdaFu first version */ - + /* write register a=address, v=value */ -#define write_reg(a,v) (*(volatile unsigned int *)(a) = (v)) +#define write_reg(a,v) (*(volatile unsigned int *)(a) = (v)) /* Processor Reset */ #define AT91_RSTC_PROCRST (1 << 0) #define AT91_RSTC_PERRST (1 << 2) diff --git a/bsp/at91sam9260/platform/rt_low_level_init.h b/bsp/at91sam9260/platform/rt_low_level_init.h index 86dcfb59dc..c79adf5284 100644 --- a/bsp/at91sam9260/platform/rt_low_level_init.h +++ b/bsp/at91sam9260/platform/rt_low_level_init.h @@ -1,21 +1,7 @@ /* - * File : rt_low_level_init.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -23,7 +9,7 @@ */ #ifndef __RT_LOW_LEVEL_INIT_H__ #define __RT_LOW_LEVEL_INIT_H__ - + /*-------- Stack size of CPU modes -------------------------------------------*/ #define UND_STK_SIZE 512 #define SVC_STK_SIZE 4096 diff --git a/bsp/at91sam9260/platform/system_clock.c b/bsp/at91sam9260/platform/system_clock.c index 13f11609d2..a8f866fdd6 100644 --- a/bsp/at91sam9260/platform/system_clock.c +++ b/bsp/at91sam9260/platform/system_clock.c @@ -1,21 +1,7 @@ /* - * File : clock.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -28,270 +14,270 @@ static rt_list_t clocks; struct clk { - char name[32]; - rt_uint32_t rate_hz; - struct clk *parent; - rt_list_t node; + char name[32]; + rt_uint32_t rate_hz; + struct clk *parent; + rt_list_t node; }; static struct clk clk32k = { - "clk32k", - AT91_SLOW_CLOCK, - RT_NULL, - {RT_NULL, RT_NULL}, + "clk32k", + AT91_SLOW_CLOCK, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk main_clk = { - "main", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, + "main", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk plla = { - "plla", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, + "plla", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk mck = { - "mck", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, + "mck", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk uhpck = { - "uhpck", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, + "uhpck", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk pllb = { - "pllb", - 0, - &main_clk, - {RT_NULL, RT_NULL}, + "pllb", + 0, + &main_clk, + {RT_NULL, RT_NULL}, }; static struct clk udpck = { - "udpck", - 0, - &pllb, - {RT_NULL, RT_NULL}, + "udpck", + 0, + &pllb, + {RT_NULL, RT_NULL}, }; static struct clk *const standard_pmc_clocks[] = { - /* four primary clocks */ - &clk32k, - &main_clk, - &plla, + /* four primary clocks */ + &clk32k, + &main_clk, + &plla, - /* MCK */ - &mck + /* MCK */ + &mck }; /* clocks cannot be de-registered no refcounting necessary */ struct clk *clk_get(const char *id) { - struct clk *clk; - rt_list_t *list; - - for (list = (&clocks)->next; list != &clocks; list = list->next) - { - clk = (struct clk *)rt_list_entry(list, struct clk, node); - if (rt_strcmp(id, clk->name) == 0) - return clk; - } + struct clk *clk; + rt_list_t *list; - return RT_NULL; + for (list = (&clocks)->next; list != &clocks; list = list->next) + { + clk = (struct clk *)rt_list_entry(list, struct clk, node); + if (rt_strcmp(id, clk->name) == 0) + return clk; + } + + return RT_NULL; } rt_uint32_t clk_get_rate(struct clk *clk) { - rt_uint32_t flags; - rt_uint32_t rate; + rt_uint32_t flags; + rt_uint32_t rate; - for (;;) { - rate = clk->rate_hz; - if (rate || !clk->parent) - break; - clk = clk->parent; - } - return rate; + for (;;) { + rate = clk->rate_hz; + if (rate || !clk->parent) + break; + clk = clk->parent; + } + return rate; } static rt_uint32_t at91_pll_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg) { - unsigned mul, div; + unsigned mul, div; - div = reg & 0xff; - mul = (reg >> 16) & 0x7ff; - if (div && mul) { - freq /= div; - freq *= mul + 1; - } else - freq = 0; + div = reg & 0xff; + mul = (reg >> 16) & 0x7ff; + if (div && mul) { + freq /= div; + freq *= mul + 1; + } else + freq = 0; - return freq; + return freq; } static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq) { - unsigned i, div = 0, mul = 0, diff = 1 << 30; - unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; + unsigned i, div = 0, mul = 0, diff = 1 << 30; + unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; - /* PLL output max 240 MHz (or 180 MHz per errata) */ - if (out_freq > 240000000) - goto fail; + /* PLL output max 240 MHz (or 180 MHz per errata) */ + if (out_freq > 240000000) + goto fail; - for (i = 1; i < 256; i++) { - int diff1; - unsigned input, mul1; + for (i = 1; i < 256; i++) { + int diff1; + unsigned input, mul1; - /* - * PLL input between 1MHz and 32MHz per spec, but lower - * frequences seem necessary in some cases so allow 100K. - * Warning: some newer products need 2MHz min. - */ - input = main_freq / i; - if (input < 100000) - continue; - if (input > 32000000) - continue; + /* + * PLL input between 1MHz and 32MHz per spec, but lower + * frequences seem necessary in some cases so allow 100K. + * Warning: some newer products need 2MHz min. + */ + input = main_freq / i; + if (input < 100000) + continue; + if (input > 32000000) + continue; - mul1 = out_freq / input; - if (mul1 > 2048) - continue; - if (mul1 < 2) - goto fail; + mul1 = out_freq / input; + if (mul1 > 2048) + continue; + if (mul1 < 2) + goto fail; - diff1 = out_freq - input * mul1; - if (diff1 < 0) - diff1 = -diff1; - if (diff > diff1) { - diff = diff1; - div = i; - mul = mul1; - if (diff == 0) - break; - } - } - if (i == 256 && diff > (out_freq >> 5)) - goto fail; - return ret | ((mul - 1) << 16) | div; + diff1 = out_freq - input * mul1; + if (diff1 < 0) + diff1 = -diff1; + if (diff > diff1) { + diff = diff1; + div = i; + mul = mul1; + if (diff == 0) + break; + } + } + if (i == 256 && diff > (out_freq >> 5)) + goto fail; + return ret | ((mul - 1) << 16) | div; fail: - return 0; + return 0; } static rt_uint32_t at91_usb_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg) { - if (pll == &pllb && (reg & AT91_PMC_USB96M)) - return freq / 2; - else - return freq; + if (pll == &pllb && (reg & AT91_PMC_USB96M)) + return freq / 2; + else + return freq; } /* PLLB generated USB full speed clock init */ static void at91_pllb_usbfs_clock_init(rt_uint32_t main_clock) { - rt_uint32_t at91_pllb_usb_init; - /* - * USB clock init: choose 48 MHz PLLB value, - * disable 48MHz clock during usb peripheral suspend. - * - * REVISIT: assumes MCK doesn't derive from PLLB! - */ - uhpck.parent = &pllb; + rt_uint32_t at91_pllb_usb_init; + /* + * USB clock init: choose 48 MHz PLLB value, + * disable 48MHz clock during usb peripheral suspend. + * + * REVISIT: assumes MCK doesn't derive from PLLB! + */ + uhpck.parent = &pllb; - at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; - pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); - - at91_sys_write(AT91_CKGR_PLLBR, 0); + at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; + pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); - udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); - uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); + at91_sys_write(AT91_CKGR_PLLBR, 0); + + udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); + uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); } static struct clk *at91_css_to_clk(unsigned long css) { - switch (css) { - case AT91_PMC_CSS_SLOW: - return &clk32k; - case AT91_PMC_CSS_MAIN: - return &main_clk; - case AT91_PMC_CSS_PLLA: - return &plla; - case AT91_PMC_CSS_PLLB: - return &pllb; - } + switch (css) { + case AT91_PMC_CSS_SLOW: + return &clk32k; + case AT91_PMC_CSS_MAIN: + return &main_clk; + case AT91_PMC_CSS_PLLA: + return &plla; + case AT91_PMC_CSS_PLLB: + return &pllb; + } - return RT_NULL; + return RT_NULL; } #define false 0 #define true 1 int at91_clock_init(rt_uint32_t main_clock) { - unsigned tmp, freq, mckr; - int i; - int pll_overclock = false; + unsigned tmp, freq, mckr; + int i; + int pll_overclock = false; - /* - * When the bootloader initialized the main oscillator correctly, - * there's no problem using the cycle counter. But if it didn't, - * or when using oscillator bypass mode, we must be told the speed - * of the main clock. - */ - if (!main_clock) { - do { - tmp = at91_sys_read(AT91_CKGR_MCFR); - } while (!(tmp & AT91_PMC_MAINRDY)); - main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); - } - main_clk.rate_hz = main_clock; + /* + * When the bootloader initialized the main oscillator correctly, + * there's no problem using the cycle counter. But if it didn't, + * or when using oscillator bypass mode, we must be told the speed + * of the main clock. + */ + if (!main_clock) { + do { + tmp = at91_sys_read(AT91_CKGR_MCFR); + } while (!(tmp & AT91_PMC_MAINRDY)); + main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); + } + main_clk.rate_hz = main_clock; - /* report if PLLA is more than mildly overclocked */ - plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); - if (plla.rate_hz > 209000000) - pll_overclock = true; - if (pll_overclock) - ;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); + /* report if PLLA is more than mildly overclocked */ + plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); + if (plla.rate_hz > 209000000) + pll_overclock = true; + if (pll_overclock) + ;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); - at91_pllb_usbfs_clock_init(main_clock); + at91_pllb_usbfs_clock_init(main_clock); - /* - * MCK and CPU derive from one of those primary clocks. - * For now, assume this parentage won't change. - */ - mckr = at91_sys_read(AT91_PMC_MCKR); - mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); - freq = mck.parent->rate_hz; - freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */ - - mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ + /* + * MCK and CPU derive from one of those primary clocks. + * For now, assume this parentage won't change. + */ + mckr = at91_sys_read(AT91_PMC_MCKR); + mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); + freq = mck.parent->rate_hz; + freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */ - /* Register the PMC's standard clocks */ - rt_list_init(&clocks); - for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) - rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node); + mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ - rt_list_insert_after(&clocks, &pllb.node); - rt_list_insert_after(&clocks, &uhpck.node); - rt_list_insert_after(&clocks, &udpck.node); + /* Register the PMC's standard clocks */ + rt_list_init(&clocks); + for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) + rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node); - /* MCK and CPU clock are "always on" */ - //clk_enable(&mck); + rt_list_insert_after(&clocks, &pllb.node); + rt_list_insert_after(&clocks, &uhpck.node); + rt_list_insert_after(&clocks, &udpck.node); - /*rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", - freq / 1000000, (unsigned) mck.rate_hz / 1000000, - (unsigned) main_clock / 1000000, - ((unsigned) main_clock % 1000000) / 1000);*///cause blocked + /* MCK and CPU clock are "always on" */ + //clk_enable(&mck); - return 0; + /*rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", + freq / 1000000, (unsigned) mck.rate_hz / 1000000, + (unsigned) main_clock / 1000000, + ((unsigned) main_clock % 1000000) / 1000);*///cause blocked + + return 0; } /** @@ -299,6 +285,6 @@ int at91_clock_init(rt_uint32_t main_clock) */ void rt_hw_clock_init(void) { - at91_clock_init(18432000); + at91_clock_init(18432000); } diff --git a/bsp/at91sam9g45/applications/application.c b/bsp/at91sam9g45/applications/application.c index ec878faa85..6bc312b997 100644 --- a/bsp/at91sam9g45/applications/application.c +++ b/bsp/at91sam9g45/applications/application.c @@ -1,25 +1,11 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ /** @@ -49,106 +35,106 @@ static int rt_led_app_init(void); RT_WEAK int main(void) { #ifdef RT_USING_SDIO - int timeout = 0; + int timeout = 0; #endif /* Filesystem Initialization */ #ifdef RT_USING_DFS - { + { #if defined(RT_USING_DFS_ROMFS) - if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0) - { - rt_kprintf("ROM File System initialized!\n"); - } - else - rt_kprintf("ROM File System initialzation failed!\n"); + if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0) + { + rt_kprintf("ROM File System initialized!\n"); + } + else + rt_kprintf("ROM File System initialzation failed!\n"); #endif #if defined(RT_USING_DFS_UFFS) - { - /* mount flash device as flash directory */ - if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0) - rt_kprintf("UFFS File System initialized!\n"); - else - rt_kprintf("UFFS File System initialzation failed!\n"); - } + { + /* mount flash device as flash directory */ + if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0) + rt_kprintf("UFFS File System initialized!\n"); + else + rt_kprintf("UFFS File System initialzation failed!\n"); + } #endif #ifdef RT_USING_SDIO - timeout = 0; - while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2)) - { - rt_thread_delay(1); - } + timeout = 0; + while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2)) + { + rt_thread_delay(1); + } - if (timeout < RT_TICK_PER_SECOND*2) - { - /* mount sd card fat partition 1 as root directory */ - if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) - { - rt_kprintf("File System initialized!\n"); - } - else - rt_kprintf("File System initialzation failed!%d\n", rt_get_errno()); - } - else - { - rt_kprintf("No SD card found.\n"); - } + if (timeout < RT_TICK_PER_SECOND*2) + { + /* mount sd card fat partition 1 as root directory */ + if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) + { + rt_kprintf("File System initialized!\n"); + } + else + rt_kprintf("File System initialzation failed!%d\n", rt_get_errno()); + } + else + { + rt_kprintf("No SD card found.\n"); + } #endif - } + } #endif - rt_led_app_init(); + rt_led_app_init(); } #ifdef RT_USING_LED void rt_led_thread_entry(void* parameter) { - rt_uint8_t cnt = 0; - led_init(); - while(1) - { - /* light on leds for one second */ - rt_thread_delay(40); - cnt++; - if (cnt&0x01) - led_on(1); - else - led_off(1); - if (cnt&0x02) - led_on(2); - else - led_off(2); - if (cnt&0x04) - led_on(3); - else - led_off(3); - - } + rt_uint8_t cnt = 0; + led_init(); + while(1) + { + /* light on leds for one second */ + rt_thread_delay(40); + cnt++; + if (cnt&0x01) + led_on(1); + else + led_off(1); + if (cnt&0x02) + led_on(2); + else + led_off(2); + if (cnt&0x04) + led_on(3); + else + led_off(3); + + } } #endif static int rt_led_app_init(void) { #ifdef RT_USING_LED - rt_thread_t led_thread; + rt_thread_t led_thread; #if (RT_THREAD_PRIORITY_MAX == 32) - led_thread = rt_thread_create("led", - rt_led_thread_entry, RT_NULL, - 512, 20, 20); + led_thread = rt_thread_create("led", + rt_led_thread_entry, RT_NULL, + 512, 20, 20); #else - led_thread = rt_thread_create("led", - rt_led_thread_entry, RT_NULL, - 512, 200, 20); + led_thread = rt_thread_create("led", + rt_led_thread_entry, RT_NULL, + 512, 200, 20); #endif - if(led_thread != RT_NULL) - rt_thread_startup(led_thread); + if(led_thread != RT_NULL) + rt_thread_startup(led_thread); #endif - return 0; + return 0; } /* NFSv3 Initialization */ @@ -156,14 +142,14 @@ static int rt_led_app_init(void) #include void nfs_start(void) { - nfs_init(); + nfs_init(); - if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0) - { - rt_kprintf("NFSv3 File System initialized!\n"); - } - else - rt_kprintf("NFSv3 File System initialzation failed!\n"); + if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0) + { + rt_kprintf("NFSv3 File System initialized!\n"); + } + else + rt_kprintf("NFSv3 File System initialzation failed!\n"); } #include "finsh.h" diff --git a/bsp/at91sam9g45/drivers/at91_i2c_gpio.c b/bsp/at91sam9g45/drivers/at91_i2c_gpio.c index 91ca646c7a..d229cbd1bb 100644 --- a/bsp/at91sam9g45/drivers/at91_i2c_gpio.c +++ b/bsp/at91sam9g45/drivers/at91_i2c_gpio.c @@ -1,25 +1,11 @@ /* - * File : at91_i2c_gpio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2012-04-25 weety first version + * Date Author Notes + * 2012-04-25 weety first version */ #include @@ -29,101 +15,101 @@ static void at91_i2c_gpio_init() { - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOA; //enable PIOA clock - AT91C_BASE_PIOA->PIO_PUER = (1 << 23); - AT91C_BASE_PIOA->PIO_PER = (1 << 23); - AT91C_BASE_PIOA->PIO_MDER = (1 << 23); - AT91C_BASE_PIOA->PIO_PUER = (1 << 24); - AT91C_BASE_PIOA->PIO_PER = (1 << 24); - AT91C_BASE_PIOA->PIO_MDER = (1 << 24); + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOA; //enable PIOA clock + AT91C_BASE_PIOA->PIO_PUER = (1 << 23); + AT91C_BASE_PIOA->PIO_PER = (1 << 23); + AT91C_BASE_PIOA->PIO_MDER = (1 << 23); + AT91C_BASE_PIOA->PIO_PUER = (1 << 24); + AT91C_BASE_PIOA->PIO_PER = (1 << 24); + AT91C_BASE_PIOA->PIO_MDER = (1 << 24); - AT91C_BASE_PIOA->PIO_OER = (1 << 23); - AT91C_BASE_PIOA->PIO_OER = (1 << 24); + AT91C_BASE_PIOA->PIO_OER = (1 << 23); + AT91C_BASE_PIOA->PIO_OER = (1 << 24); - AT91C_BASE_PIOA->PIO_SODR = (1 << 23); - AT91C_BASE_PIOA->PIO_SODR = (1 << 24); + AT91C_BASE_PIOA->PIO_SODR = (1 << 23); + AT91C_BASE_PIOA->PIO_SODR = (1 << 24); } static void at91_set_sda(void *data, rt_int32_t state) { - if (state) - { - AT91C_BASE_PIOA->PIO_SODR = (1 << 23); - } - else - { - AT91C_BASE_PIOA->PIO_CODR = (1 << 23); - } + if (state) + { + AT91C_BASE_PIOA->PIO_SODR = (1 << 23); + } + else + { + AT91C_BASE_PIOA->PIO_CODR = (1 << 23); + } } static void at91_set_scl(void *data, rt_int32_t state) { - if (state) - { - AT91C_BASE_PIOA->PIO_SODR = (1 << 24); - } - else - { - AT91C_BASE_PIOA->PIO_CODR = (1 << 24); - } + if (state) + { + AT91C_BASE_PIOA->PIO_SODR = (1 << 24); + } + else + { + AT91C_BASE_PIOA->PIO_CODR = (1 << 24); + } } static rt_int32_t at91_get_sda(void *data) { - return AT91C_BASE_PIOA->PIO_PDSR & (1 << 23); + return AT91C_BASE_PIOA->PIO_PDSR & (1 << 23); } static rt_int32_t at91_get_scl(void *data) { - return AT91C_BASE_PIOA->PIO_PDSR & (1 << 24); + return AT91C_BASE_PIOA->PIO_PDSR & (1 << 24); } static void at91_udelay (rt_uint32_t us) { - rt_int32_t i; - for (; us > 0; us--) - { - i = 50000; - while(i > 0) - { - i--; - } - } + rt_int32_t i; + for (; us > 0; us--) + { + i = 50000; + while(i > 0) + { + i--; + } + } } static const struct rt_i2c_bit_ops bit_ops = { - RT_NULL, - at91_set_sda, - at91_set_scl, - at91_get_sda, - at91_get_scl, - - at91_udelay, + RT_NULL, + at91_set_sda, + at91_set_scl, + at91_get_sda, + at91_get_scl, - 5, - 100 + at91_udelay, + + 5, + 100 }; int at91_i2c_init(void) { - struct rt_i2c_bus_device *bus; + struct rt_i2c_bus_device *bus; - bus = rt_malloc(sizeof(struct rt_i2c_bus_device)); - if (bus == RT_NULL) - { - rt_kprintf("rt_malloc failed\n"); - return -RT_ENOMEM; - } - - rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device)); + bus = rt_malloc(sizeof(struct rt_i2c_bus_device)); + if (bus == RT_NULL) + { + rt_kprintf("rt_malloc failed\n"); + return -RT_ENOMEM; + } - bus->priv = (void *)&bit_ops; + rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device)); - at91_i2c_gpio_init(); + bus->priv = (void *)&bit_ops; - rt_i2c_bit_add_bus(bus, "i2c0"); + at91_i2c_gpio_init(); - return 0; + rt_i2c_bit_add_bus(bus, "i2c0"); + + return 0; } INIT_DEVICE_EXPORT(at91_i2c_init); diff --git a/bsp/at91sam9g45/drivers/at91_mci.c b/bsp/at91sam9g45/drivers/at91_mci.c index 0ad5590df6..55c698832f 100644 --- a/bsp/at91sam9g45/drivers/at91_mci.c +++ b/bsp/at91sam9g45/drivers/at91_mci.c @@ -1,25 +1,11 @@ /* - * File : at91_mci.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-07-25 weety first version + * Date Author Notes + * 2011-07-25 weety first version */ #include @@ -37,32 +23,32 @@ #define mci_dbg(fmt, ...) #endif -#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31)) +#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31)) extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size); extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); -#define AT91C_MCI_ERRORS (AT91C_MCI_RINDE | AT91C_MCI_RDIRE | AT91C_MCI_RCRCE \ - | AT91C_MCI_RENDE | AT91C_MCI_RTOE | AT91C_MCI_DCRCE \ - | AT91C_MCI_DTOE | AT91C_MCI_OVRE | AT91C_MCI_UNRE) +#define AT91C_MCI_ERRORS (AT91C_MCI_RINDE | AT91C_MCI_RDIRE | AT91C_MCI_RCRCE \ + | AT91C_MCI_RENDE | AT91C_MCI_RTOE | AT91C_MCI_DCRCE \ + | AT91C_MCI_DTOE | AT91C_MCI_OVRE | AT91C_MCI_UNRE) -#define at91_mci_read(reg) readl(AT91C_BASE_MCI + (reg)) -#define at91_mci_write(reg, val) writel((val), AT91C_BASE_MCI + (reg)) +#define at91_mci_read(reg) readl(AT91C_BASE_MCI + (reg)) +#define at91_mci_write(reg, val) writel((val), AT91C_BASE_MCI + (reg)) -#define REQ_ST_INIT (1U << 0) -#define REQ_ST_CMD (1U << 1) -#define REQ_ST_STOP (1U << 2) +#define REQ_ST_INIT (1U << 0) +#define REQ_ST_CMD (1U << 1) +#define REQ_ST_STOP (1U << 2) struct at91_mci { - struct rt_mmcsd_host *host; - struct rt_mmcsd_req *req; - struct rt_mmcsd_cmd *cmd; - struct rt_timer timer; - //struct rt_semaphore sem_ack; - rt_uint32_t *buf; - rt_uint32_t current_status; + struct rt_mmcsd_host *host; + struct rt_mmcsd_req *req; + struct rt_mmcsd_cmd *cmd; + struct rt_timer timer; + //struct rt_semaphore sem_ack; + rt_uint32_t *buf; + rt_uint32_t current_status; }; /* @@ -70,36 +56,36 @@ struct at91_mci { */ static void at91_reset_host() { - rt_uint32_t mr; - rt_uint32_t sdcr; - rt_uint32_t dtor; - rt_uint32_t imr; - rt_uint32_t level; + rt_uint32_t mr; + rt_uint32_t sdcr; + rt_uint32_t dtor; + rt_uint32_t imr; + rt_uint32_t level; - level = rt_hw_interrupt_disable(); + level = rt_hw_interrupt_disable(); - imr = at91_mci_read(AT91C_MCI_IMR); + imr = at91_mci_read(AT91C_MCI_IMR); - at91_mci_write(AT91C_MCI_IDR, 0xffffffff); + at91_mci_write(AT91C_MCI_IDR, 0xffffffff); - /* save current state */ - mr = at91_mci_read(AT91C_MCI_MR) & 0x7fff; - sdcr = at91_mci_read(AT91C_MCI_SDCR); - dtor = at91_mci_read(AT91C_MCI_DTOR); + /* save current state */ + mr = at91_mci_read(AT91C_MCI_MR) & 0x7fff; + sdcr = at91_mci_read(AT91C_MCI_SDCR); + dtor = at91_mci_read(AT91C_MCI_DTOR); - /* reset the controller */ - at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIDIS | AT91C_MCI_SWRST); + /* reset the controller */ + at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIDIS | AT91C_MCI_SWRST); - /* restore state */ - at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIEN); - at91_mci_write(AT91C_MCI_MR, mr); - at91_mci_write(AT91C_MCI_SDCR, sdcr); - at91_mci_write(AT91C_MCI_DTOR, dtor); - at91_mci_write(AT91C_MCI_IER, imr); + /* restore state */ + at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIEN); + at91_mci_write(AT91C_MCI_MR, mr); + at91_mci_write(AT91C_MCI_SDCR, sdcr); + at91_mci_write(AT91C_MCI_DTOR, dtor); + at91_mci_write(AT91C_MCI_IER, imr); - /* make sure sdio interrupts will fire */ - at91_mci_read(AT91C_MCI_SR); - rt_hw_interrupt_enable(level); + /* make sure sdio interrupts will fire */ + at91_mci_read(AT91C_MCI_SR); + rt_hw_interrupt_enable(level); } @@ -109,19 +95,19 @@ static void at91_reset_host() */ static void at91_mci_enable() { - rt_uint32_t mr; + rt_uint32_t mr; - at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIEN); - at91_mci_write(AT91C_MCI_IDR, 0xffffffff); - at91_mci_write(AT91C_MCI_DTOR, AT91C_MCI_DTOMUL_1M | AT91C_MCI_DTOCYC); - mr = AT91C_MCI_PDCMODE | 0x34a; + at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIEN); + at91_mci_write(AT91C_MCI_IDR, 0xffffffff); + at91_mci_write(AT91C_MCI_DTOR, AT91C_MCI_DTOMUL_1M | AT91C_MCI_DTOCYC); + mr = AT91C_MCI_PDCMODE | 0x34a; - mr |= AT91C_MCI_RDPROOF | AT91C_MCI_WRPROOF; + mr |= AT91C_MCI_RDPROOF | AT91C_MCI_WRPROOF; - at91_mci_write(AT91C_MCI_MR, mr); + at91_mci_write(AT91C_MCI_MR, mr); - /* use Slot A or B (only one at same time) */ - at91_mci_write(AT91C_MCI_SDCR, 1); /* use slot b */ + /* use Slot A or B (only one at same time) */ + at91_mci_write(AT91C_MCI_SDCR, 1); /* use slot b */ } /* @@ -129,39 +115,39 @@ static void at91_mci_enable() */ static void at91_mci_disable() { - at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIDIS | AT91C_MCI_SWRST); + at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIDIS | AT91C_MCI_SWRST); } static void at91_timeout_timer(void *data) { - struct at91_mci *mci; + struct at91_mci *mci; - mci = (struct at91_mci *)data; + mci = (struct at91_mci *)data; - if (mci->req) - { - rt_kprintf("Timeout waiting end of packet\n"); + if (mci->req) + { + rt_kprintf("Timeout waiting end of packet\n"); - if (mci->current_status == REQ_ST_CMD) - { - if (mci->req->cmd && mci->req->data) - { - mci->req->data->err = -RT_ETIMEOUT; - } - else - { - if (mci->req->cmd) - mci->req->cmd->err = -RT_ETIMEOUT; - } - } - else if (mci->current_status == REQ_ST_STOP) - { - mci->req->stop->err = -RT_ETIMEOUT; - } + if (mci->current_status == REQ_ST_CMD) + { + if (mci->req->cmd && mci->req->data) + { + mci->req->data->err = -RT_ETIMEOUT; + } + else + { + if (mci->req->cmd) + mci->req->cmd->err = -RT_ETIMEOUT; + } + } + else if (mci->current_status == REQ_ST_STOP) + { + mci->req->stop->err = -RT_ETIMEOUT; + } - at91_reset_host(); - mmcsd_req_complete(mci->host); - } + at91_reset_host(); + mmcsd_req_complete(mci->host); + } } /* @@ -169,62 +155,62 @@ static void at91_timeout_timer(void *data) */ static void at91_mci_init_dma_read(struct at91_mci *mci) { - rt_uint8_t i; - struct rt_mmcsd_cmd *cmd; - struct rt_mmcsd_data *data; - rt_uint32_t length; + rt_uint8_t i; + struct rt_mmcsd_cmd *cmd; + struct rt_mmcsd_data *data; + rt_uint32_t length; - mci_dbg("pre dma read\n"); + mci_dbg("pre dma read\n"); - cmd = mci->cmd; - if (!cmd) - { - mci_dbg("no command\n"); - return; - } + cmd = mci->cmd; + if (!cmd) + { + mci_dbg("no command\n"); + return; + } - data = cmd->data; - if (!data) - { - mci_dbg("no data\n"); - return; - } + data = cmd->data; + if (!data) + { + mci_dbg("no data\n"); + return; + } - for (i = 0; i < 1; i++) - { - /* Check to see if this needs filling */ - if (i == 0) - { - if (at91_mci_read(AT91C_PDC_RCR) != 0) - { - mci_dbg("Transfer active in current\n"); - continue; - } - } - else { - if (at91_mci_read(AT91C_PDC_RNCR) != 0) - { - mci_dbg("Transfer active in next\n"); - continue; - } - } + for (i = 0; i < 1; i++) + { + /* Check to see if this needs filling */ + if (i == 0) + { + if (at91_mci_read(AT91C_PDC_RCR) != 0) + { + mci_dbg("Transfer active in current\n"); + continue; + } + } + else { + if (at91_mci_read(AT91C_PDC_RNCR) != 0) + { + mci_dbg("Transfer active in next\n"); + continue; + } + } - length = data->blksize * data->blks; - mci_dbg("dma address = %08X, length = %d\n", data->buf, length); + length = data->blksize * data->blks; + mci_dbg("dma address = %08X, length = %d\n", data->buf, length); - if (i == 0) - { - at91_mci_write(AT91C_PDC_RPR, (rt_uint32_t)(data->buf)); - at91_mci_write(AT91C_PDC_RCR, (data->blksize & 0x3) ? length : length / 4); - } - else - { - at91_mci_write(AT91C_PDC_RNPR, (rt_uint32_t)(data->buf)); - at91_mci_write(AT91C_PDC_RNCR, (data->blksize & 0x3) ? length : length / 4); - } - } + if (i == 0) + { + at91_mci_write(AT91C_PDC_RPR, (rt_uint32_t)(data->buf)); + at91_mci_write(AT91C_PDC_RCR, (data->blksize & 0x3) ? length : length / 4); + } + else + { + at91_mci_write(AT91C_PDC_RNPR, (rt_uint32_t)(data->buf)); + at91_mci_write(AT91C_PDC_RNCR, (data->blksize & 0x3) ? length : length / 4); + } + } - mci_dbg("pre dma read done\n"); + mci_dbg("pre dma read done\n"); } /* @@ -232,185 +218,185 @@ static void at91_mci_init_dma_read(struct at91_mci *mci) */ static void at91_mci_send_command(struct at91_mci *mci, struct rt_mmcsd_cmd *cmd) { - rt_uint32_t cmdr, mr; - rt_uint32_t block_length; - struct rt_mmcsd_data *data = cmd->data; - struct rt_mmcsd_host *host = mci->host; + rt_uint32_t cmdr, mr; + rt_uint32_t block_length; + struct rt_mmcsd_data *data = cmd->data; + struct rt_mmcsd_host *host = mci->host; - rt_uint32_t blocks; - rt_uint32_t ier = 0; - rt_uint32_t length; + rt_uint32_t blocks; + rt_uint32_t ier = 0; + rt_uint32_t length; - mci->cmd = cmd; + mci->cmd = cmd; - /* Needed for leaving busy state before CMD1 */ - if ((at91_mci_read(AT91C_MCI_SR) & AT91C_MCI_RTOE) && (cmd->cmd_code == 1)) - { - mci_dbg("Clearing timeout\n"); - at91_mci_write(AT91C_MCI_ARGR, 0); - at91_mci_write(AT91C_MCI_CMDR, AT91C_MCI_OPDCMD); - while (!(at91_mci_read(AT91C_MCI_SR) & AT91C_MCI_CMDRDY)) - { - /* spin */ - mci_dbg("Clearing: SR = %08X\n", at91_mci_read(AT91C_MCI_SR)); - } - } + /* Needed for leaving busy state before CMD1 */ + if ((at91_mci_read(AT91C_MCI_SR) & AT91C_MCI_RTOE) && (cmd->cmd_code == 1)) + { + mci_dbg("Clearing timeout\n"); + at91_mci_write(AT91C_MCI_ARGR, 0); + at91_mci_write(AT91C_MCI_CMDR, AT91C_MCI_OPDCMD); + while (!(at91_mci_read(AT91C_MCI_SR) & AT91C_MCI_CMDRDY)) + { + /* spin */ + mci_dbg("Clearing: SR = %08X\n", at91_mci_read(AT91C_MCI_SR)); + } + } - cmdr = cmd->cmd_code; + cmdr = cmd->cmd_code; - if (resp_type(cmd) == RESP_NONE) - cmdr |= AT91C_MCI_RSPTYP_NONE; - else - { - /* if a response is expected then allow maximum response latancy */ - cmdr |= AT91C_MCI_MAXLAT; - /* set 136 bit response for R2, 48 bit response otherwise */ - if (resp_type(cmd) == RESP_R2) - cmdr |= AT91C_MCI_RSPTYP_136; - else - cmdr |= AT91C_MCI_RSPTYP_48; - } + if (resp_type(cmd) == RESP_NONE) + cmdr |= AT91C_MCI_RSPTYP_NONE; + else + { + /* if a response is expected then allow maximum response latancy */ + cmdr |= AT91C_MCI_MAXLAT; + /* set 136 bit response for R2, 48 bit response otherwise */ + if (resp_type(cmd) == RESP_R2) + cmdr |= AT91C_MCI_RSPTYP_136; + else + cmdr |= AT91C_MCI_RSPTYP_48; + } - if (data) - { + if (data) + { - block_length = data->blksize; - blocks = data->blks; + block_length = data->blksize; + blocks = data->blks; - /* always set data start - also set direction flag for read */ - if (data->flags & DATA_DIR_READ) - cmdr |= (AT91C_MCI_TRDIR | AT91C_MCI_TRCMD_START); - else if (data->flags & DATA_DIR_WRITE) - cmdr |= AT91C_MCI_TRCMD_START; + /* always set data start - also set direction flag for read */ + if (data->flags & DATA_DIR_READ) + cmdr |= (AT91C_MCI_TRDIR | AT91C_MCI_TRCMD_START); + else if (data->flags & DATA_DIR_WRITE) + cmdr |= AT91C_MCI_TRCMD_START; - if (data->flags & DATA_STREAM) - cmdr |= AT91C_MCI_TRTYP_STREAM; - if (data->blks > 1) - cmdr |= AT91C_MCI_TRTYP_MULTIPLE; - } - else - { - block_length = 0; - blocks = 0; - } + if (data->flags & DATA_STREAM) + cmdr |= AT91C_MCI_TRTYP_STREAM; + if (data->blks > 1) + cmdr |= AT91C_MCI_TRTYP_MULTIPLE; + } + else + { + block_length = 0; + blocks = 0; + } - /*if (cmd->cmd_code == GO_IDLE_STATE) - { - cmdr |= AT91C_MCI_SPCMD_INIT; - }*/ + /*if (cmd->cmd_code == GO_IDLE_STATE) + { + cmdr |= AT91C_MCI_SPCMD_INIT; + }*/ - if (cmd->cmd_code == STOP_TRANSMISSION) - cmdr |= AT91C_MCI_TRCMD_STOP; + if (cmd->cmd_code == STOP_TRANSMISSION) + cmdr |= AT91C_MCI_TRCMD_STOP; - if (host->io_cfg.bus_mode == MMCSD_BUSMODE_OPENDRAIN) - cmdr |= AT91C_MCI_OPDCMD; + if (host->io_cfg.bus_mode == MMCSD_BUSMODE_OPENDRAIN) + cmdr |= AT91C_MCI_OPDCMD; - /* - * Set the arguments and send the command - */ - mci_dbg("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n", - cmd->cmd_code, cmdr, cmd->arg, blocks, block_length, at91_mci_read(AT91C_MCI_MR)); + /* + * Set the arguments and send the command + */ + mci_dbg("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n", + cmd->cmd_code, cmdr, cmd->arg, blocks, block_length, at91_mci_read(AT91C_MCI_MR)); - if (!data) - { - at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_TXTDIS | AT91C_PDC_RXTDIS); - at91_mci_write(AT91C_PDC_RPR, 0); - at91_mci_write(AT91C_PDC_RCR, 0); - at91_mci_write(AT91C_PDC_RNPR, 0); - at91_mci_write(AT91C_PDC_RNCR, 0); - at91_mci_write(AT91C_PDC_TPR, 0); - at91_mci_write(AT91C_PDC_TCR, 0); - at91_mci_write(AT91C_PDC_TNPR, 0); - at91_mci_write(AT91C_PDC_TNCR, 0); - ier = AT91C_MCI_CMDRDY; - } - else - { - /* zero block length and PDC mode */ - mr = at91_mci_read(AT91C_MCI_MR) & 0x5fff; - mr |= (data->blksize & 0x3) ? AT91C_MCI_PDCFBYTE : 0; - mr |= (block_length << 16); - mr |= AT91C_MCI_PDCMODE; - at91_mci_write(AT91C_MCI_MR, mr); + if (!data) + { + at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_TXTDIS | AT91C_PDC_RXTDIS); + at91_mci_write(AT91C_PDC_RPR, 0); + at91_mci_write(AT91C_PDC_RCR, 0); + at91_mci_write(AT91C_PDC_RNPR, 0); + at91_mci_write(AT91C_PDC_RNCR, 0); + at91_mci_write(AT91C_PDC_TPR, 0); + at91_mci_write(AT91C_PDC_TCR, 0); + at91_mci_write(AT91C_PDC_TNPR, 0); + at91_mci_write(AT91C_PDC_TNCR, 0); + ier = AT91C_MCI_CMDRDY; + } + else + { + /* zero block length and PDC mode */ + mr = at91_mci_read(AT91C_MCI_MR) & 0x5fff; + mr |= (data->blksize & 0x3) ? AT91C_MCI_PDCFBYTE : 0; + mr |= (block_length << 16); + mr |= AT91C_MCI_PDCMODE; + at91_mci_write(AT91C_MCI_MR, mr); - at91_mci_write(AT91C_MCI_BLKR, - AT91C_MCI_BLKR_BCNT(blocks) | - AT91C_MCI_BLKR_BLKLEN(block_length)); + at91_mci_write(AT91C_MCI_BLKR, + AT91C_MCI_BLKR_BCNT(blocks) | + AT91C_MCI_BLKR_BLKLEN(block_length)); - /* - * Disable the PDC controller - */ - at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS); + /* + * Disable the PDC controller + */ + at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS); - if (cmdr & AT91C_MCI_TRCMD_START) - { - if (cmdr & AT91C_MCI_TRDIR) - { - /* - * Handle a read - */ + if (cmdr & AT91C_MCI_TRCMD_START) + { + if (cmdr & AT91C_MCI_TRDIR) + { + /* + * Handle a read + */ - mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blksize*data->blks); - at91_mci_init_dma_read(mci); - ier = AT91C_MCI_ENDRX /* | AT91C_MCI_RXBUFF */; - } - else - { - /* - * Handle a write - */ - length = block_length * blocks; - /* - * at91mci MCI1 rev2xx Data Write Operation and - * number of bytes erratum - */ - if (length < 12) - { - length = 12; - mci->buf = rt_malloc(length); - if (!mci->buf) - { - rt_kprintf("rt alloc tx buffer failed\n"); - cmd->err = -RT_ENOMEM; - mmcsd_req_complete(mci->host); - return; - } - rt_memset(mci->buf, 0, 12); - rt_memcpy(mci->buf, data->buf, length); - mmu_clean_dcache((rt_uint32_t)mci->buf, length); - at91_mci_write(AT91C_PDC_TPR, (rt_uint32_t)(mci->buf)); - at91_mci_write(AT91C_PDC_TCR, (data->blksize & 0x3) ? - length : length / 4); - } - else - { - mmu_clean_dcache((rt_uint32_t)data->buf, data->blksize*data->blks); - at91_mci_write(AT91C_PDC_TPR, (rt_uint32_t)(data->buf)); - at91_mci_write(AT91C_PDC_TCR, (data->blksize & 0x3) ? - length : length / 4); - } - mci_dbg("Transmitting %d bytes\n", length); - ier = AT91C_MCI_CMDRDY; - } - } - } + mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blksize*data->blks); + at91_mci_init_dma_read(mci); + ier = AT91C_MCI_ENDRX /* | AT91C_MCI_RXBUFF */; + } + else + { + /* + * Handle a write + */ + length = block_length * blocks; + /* + * at91mci MCI1 rev2xx Data Write Operation and + * number of bytes erratum + */ + if (length < 12) + { + length = 12; + mci->buf = rt_malloc(length); + if (!mci->buf) + { + rt_kprintf("rt alloc tx buffer failed\n"); + cmd->err = -RT_ENOMEM; + mmcsd_req_complete(mci->host); + return; + } + rt_memset(mci->buf, 0, 12); + rt_memcpy(mci->buf, data->buf, length); + mmu_clean_dcache((rt_uint32_t)mci->buf, length); + at91_mci_write(AT91C_PDC_TPR, (rt_uint32_t)(mci->buf)); + at91_mci_write(AT91C_PDC_TCR, (data->blksize & 0x3) ? + length : length / 4); + } + else + { + mmu_clean_dcache((rt_uint32_t)data->buf, data->blksize*data->blks); + at91_mci_write(AT91C_PDC_TPR, (rt_uint32_t)(data->buf)); + at91_mci_write(AT91C_PDC_TCR, (data->blksize & 0x3) ? + length : length / 4); + } + mci_dbg("Transmitting %d bytes\n", length); + ier = AT91C_MCI_CMDRDY; + } + } + } - /* - * Send the command and then enable the PDC - not the other way round as - * the data sheet says - */ + /* + * Send the command and then enable the PDC - not the other way round as + * the data sheet says + */ - at91_mci_write(AT91C_MCI_ARGR, cmd->arg); - at91_mci_write(AT91C_MCI_CMDR, cmdr); + at91_mci_write(AT91C_MCI_ARGR, cmd->arg); + at91_mci_write(AT91C_MCI_CMDR, cmdr); - if (cmdr & AT91C_MCI_TRCMD_START) - { - if (cmdr & AT91C_MCI_TRDIR) - at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_RXTEN); - } + if (cmdr & AT91C_MCI_TRCMD_START) + { + if (cmdr & AT91C_MCI_TRDIR) + at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_RXTEN); + } - /* Enable selected interrupts */ - at91_mci_write(AT91C_MCI_IER, AT91C_MCI_ERRORS | ier); + /* Enable selected interrupts */ + at91_mci_write(AT91C_MCI_IER, AT91C_MCI_ERRORS | ier); } /* @@ -418,25 +404,25 @@ static void at91_mci_send_command(struct at91_mci *mci, struct rt_mmcsd_cmd *cmd */ static void at91_mci_process_next(struct at91_mci *mci) { - if (mci->current_status == REQ_ST_INIT) - { - mci->current_status = REQ_ST_CMD; - at91_mci_send_command(mci, mci->req->cmd); - } - else if ((mci->current_status == REQ_ST_CMD) && mci->req->stop) - { - mci->current_status = REQ_ST_STOP; - at91_mci_send_command(mci, mci->req->stop); - } - else - { - rt_timer_stop(&mci->timer); - /* the mci controller hangs after some transfers, - * and the workaround is to reset it after each transfer. - */ - at91_reset_host(); - mmcsd_req_complete(mci->host); - } + if (mci->current_status == REQ_ST_INIT) + { + mci->current_status = REQ_ST_CMD; + at91_mci_send_command(mci, mci->req->cmd); + } + else if ((mci->current_status == REQ_ST_CMD) && mci->req->stop) + { + mci->current_status = REQ_ST_STOP; + at91_mci_send_command(mci, mci->req->stop); + } + else + { + rt_timer_stop(&mci->timer); + /* the mci controller hangs after some transfers, + * and the workaround is to reset it after each transfer. + */ + at91_reset_host(); + mmcsd_req_complete(mci->host); + } } /* @@ -444,15 +430,15 @@ static void at91_mci_process_next(struct at91_mci *mci) */ static void at91_mci_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) { - rt_uint32_t timeout = RT_TICK_PER_SECOND; - struct at91_mci *mci = host->private_data; - mci->req = req; - mci->current_status = REQ_ST_INIT; + rt_uint32_t timeout = RT_TICK_PER_SECOND; + struct at91_mci *mci = host->private_data; + mci->req = req; + mci->current_status = REQ_ST_INIT; - rt_timer_control(&mci->timer, RT_TIMER_CTRL_SET_TIME, (void*)&timeout); - rt_timer_start(&mci->timer); + rt_timer_control(&mci->timer, RT_TIMER_CTRL_SET_TIME, (void*)&timeout); + rt_timer_start(&mci->timer); - at91_mci_process_next(mci); + at91_mci_process_next(mci); } /* @@ -460,29 +446,29 @@ static void at91_mci_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *re */ static void at91_mci_handle_transmitted(struct at91_mci *mci) { - struct rt_mmcsd_cmd *cmd; - struct rt_mmcsd_data *data; + struct rt_mmcsd_cmd *cmd; + struct rt_mmcsd_data *data; - mci_dbg("Handling the transmit\n"); + mci_dbg("Handling the transmit\n"); - /* Disable the transfer */ - at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS); + /* Disable the transfer */ + at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS); - /* Now wait for cmd ready */ - at91_mci_write(AT91C_MCI_IDR, AT91C_MCI_TXBUFE); + /* Now wait for cmd ready */ + at91_mci_write(AT91C_MCI_IDR, AT91C_MCI_TXBUFE); - cmd = mci->cmd; - if (!cmd) return; + cmd = mci->cmd; + if (!cmd) return; - data = cmd->data; - if (!data) return; + data = cmd->data; + if (!data) return; - if (data->blks > 1) - { - mci_dbg("multiple write : wait for BLKE...\n"); - at91_mci_write(AT91C_MCI_IER, AT91C_MCI_BLKE); - } else - at91_mci_write(AT91C_MCI_IER, AT91C_MCI_NOTBUSY); + if (data->blks > 1) + { + mci_dbg("multiple write : wait for BLKE...\n"); + at91_mci_write(AT91C_MCI_IER, AT91C_MCI_BLKE); + } else + at91_mci_write(AT91C_MCI_IER, AT91C_MCI_NOTBUSY); } @@ -491,54 +477,54 @@ static void at91_mci_handle_transmitted(struct at91_mci *mci) */ static void at91_mci_post_dma_read(struct at91_mci *mci) { - struct rt_mmcsd_cmd *cmd; - struct rt_mmcsd_data *data; + struct rt_mmcsd_cmd *cmd; + struct rt_mmcsd_data *data; - mci_dbg("post dma read\n"); + mci_dbg("post dma read\n"); - cmd = mci->cmd; - if (!cmd) - { - mci_dbg("no command\n"); - return; - } + cmd = mci->cmd; + if (!cmd) + { + mci_dbg("no command\n"); + return; + } - data = cmd->data; - if (!data) - { - mci_dbg("no data\n"); - return; - } + data = cmd->data; + if (!data) + { + mci_dbg("no data\n"); + return; + } - at91_mci_write(AT91C_MCI_IDR, AT91C_MCI_ENDRX); - at91_mci_write(AT91C_MCI_IER, AT91C_MCI_RXBUFF); + at91_mci_write(AT91C_MCI_IDR, AT91C_MCI_ENDRX); + at91_mci_write(AT91C_MCI_IER, AT91C_MCI_RXBUFF); - mci_dbg("post dma read done\n"); + mci_dbg("post dma read done\n"); } /*Handle after command sent ready*/ static int at91_mci_handle_cmdrdy(struct at91_mci *mci) { - if (!mci->cmd) - return 1; - else if (!mci->cmd->data) - { - if (mci->current_status == REQ_ST_STOP) - { - /*After multi block write, we must wait for NOTBUSY*/ - at91_mci_write(AT91C_MCI_IER, AT91C_MCI_NOTBUSY); - } - else return 1; - } - else if (mci->cmd->data->flags & DATA_DIR_WRITE) - { - /*After sendding multi-block-write command, start DMA transfer*/ - at91_mci_write(AT91C_MCI_IER, AT91C_MCI_TXBUFE | AT91C_MCI_BLKE); - at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_TXTEN); - } + if (!mci->cmd) + return 1; + else if (!mci->cmd->data) + { + if (mci->current_status == REQ_ST_STOP) + { + /*After multi block write, we must wait for NOTBUSY*/ + at91_mci_write(AT91C_MCI_IER, AT91C_MCI_NOTBUSY); + } + else return 1; + } + else if (mci->cmd->data->flags & DATA_DIR_WRITE) + { + /*After sendding multi-block-write command, start DMA transfer*/ + at91_mci_write(AT91C_MCI_IER, AT91C_MCI_TXBUFE | AT91C_MCI_BLKE); + at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_TXTEN); + } - /* command not completed, have to wait */ - return 0; + /* command not completed, have to wait */ + return 0; } /* @@ -546,64 +532,64 @@ static int at91_mci_handle_cmdrdy(struct at91_mci *mci) */ static void at91_mci_completed_command(struct at91_mci *mci, rt_uint32_t status) { - struct rt_mmcsd_cmd *cmd = mci->cmd; - struct rt_mmcsd_data *data = cmd->data; + struct rt_mmcsd_cmd *cmd = mci->cmd; + struct rt_mmcsd_data *data = cmd->data; - at91_mci_write(AT91C_MCI_IDR, 0xffffffff & ~(AT91C_MCI_SDIOIRQA | AT91C_MCI_SDIOIRQB)); + at91_mci_write(AT91C_MCI_IDR, 0xffffffff & ~(AT91C_MCI_SDIOIRQA | AT91C_MCI_SDIOIRQB)); - cmd->resp[0] = at91_mci_read(AT91C_MCI_RSPR(0)); - cmd->resp[1] = at91_mci_read(AT91C_MCI_RSPR(1)); - cmd->resp[2] = at91_mci_read(AT91C_MCI_RSPR(2)); - cmd->resp[3] = at91_mci_read(AT91C_MCI_RSPR(3)); + cmd->resp[0] = at91_mci_read(AT91C_MCI_RSPR(0)); + cmd->resp[1] = at91_mci_read(AT91C_MCI_RSPR(1)); + cmd->resp[2] = at91_mci_read(AT91C_MCI_RSPR(2)); + cmd->resp[3] = at91_mci_read(AT91C_MCI_RSPR(3)); - if (mci->buf) - { - //rt_memcpy(data->buf, mci->buf, data->blksize*data->blks); - rt_free(mci->buf); - mci->buf = RT_NULL; - } + if (mci->buf) + { + //rt_memcpy(data->buf, mci->buf, data->blksize*data->blks); + rt_free(mci->buf); + mci->buf = RT_NULL; + } - mci_dbg("Status = %08X/%08x [%08X %08X %08X %08X]\n", - status, at91_mci_read(AT91C_MCI_SR), - cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); + mci_dbg("Status = %08X/%08x [%08X %08X %08X %08X]\n", + status, at91_mci_read(AT91C_MCI_SR), + cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); - if (status & AT91C_MCI_ERRORS) - { - if ((status & AT91C_MCI_RCRCE) && (resp_type(cmd) & (RESP_R3|RESP_R4))) - { - cmd->err = 0; - } - else - { - if (status & (AT91C_MCI_DTOE | AT91C_MCI_DCRCE)) - { - if (data) - { - if (status & AT91C_MCI_DTOE) - data->err = -RT_ETIMEOUT; - else if (status & AT91C_MCI_DCRCE) - data->err = -RT_ERROR; - } - } - else - { - if (status & AT91C_MCI_RTOE) - cmd->err = -RT_ETIMEOUT; - else if (status & AT91C_MCI_RCRCE) - cmd->err = -RT_ERROR; - else - cmd->err = -RT_ERROR; - } + if (status & AT91C_MCI_ERRORS) + { + if ((status & AT91C_MCI_RCRCE) && (resp_type(cmd) & (RESP_R3|RESP_R4))) + { + cmd->err = 0; + } + else + { + if (status & (AT91C_MCI_DTOE | AT91C_MCI_DCRCE)) + { + if (data) + { + if (status & AT91C_MCI_DTOE) + data->err = -RT_ETIMEOUT; + else if (status & AT91C_MCI_DCRCE) + data->err = -RT_ERROR; + } + } + else + { + if (status & AT91C_MCI_RTOE) + cmd->err = -RT_ETIMEOUT; + else if (status & AT91C_MCI_RCRCE) + cmd->err = -RT_ERROR; + else + cmd->err = -RT_ERROR; + } - rt_kprintf("error detected and set to %d/%d (cmd = %d)\n", - cmd->err, data ? data->err : 0, - cmd->cmd_code); - } - } - else - cmd->err = 0; + rt_kprintf("error detected and set to %d/%d (cmd = %d)\n", + cmd->err, data ? data->err : 0, + cmd->cmd_code); + } + } + else + cmd->err = 0; - at91_mci_process_next(mci); + at91_mci_process_next(mci); } /* @@ -611,120 +597,120 @@ static void at91_mci_completed_command(struct at91_mci *mci, rt_uint32_t status) */ static void at91_mci_irq(int irq, void *param) { - struct at91_mci *mci = (struct at91_mci *)param; - rt_int32_t completed = 0; - rt_uint32_t int_status, int_mask; + struct at91_mci *mci = (struct at91_mci *)param; + rt_int32_t completed = 0; + rt_uint32_t int_status, int_mask; - int_status = at91_mci_read(AT91C_MCI_SR); - int_mask = at91_mci_read(AT91C_MCI_IMR); + int_status = at91_mci_read(AT91C_MCI_SR); + int_mask = at91_mci_read(AT91C_MCI_IMR); - mci_dbg("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask, - int_status & int_mask); + mci_dbg("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask, + int_status & int_mask); - int_status = int_status & int_mask; + int_status = int_status & int_mask; - if (int_status & AT91C_MCI_ERRORS) - { - completed = 1; + if (int_status & AT91C_MCI_ERRORS) + { + completed = 1; - if (int_status & AT91C_MCI_UNRE) - mci_dbg("MMC: Underrun error\n"); - if (int_status & AT91C_MCI_OVRE) - mci_dbg("MMC: Overrun error\n"); - if (int_status & AT91C_MCI_DTOE) - mci_dbg("MMC: Data timeout\n"); - if (int_status & AT91C_MCI_DCRCE) - mci_dbg("MMC: CRC error in data\n"); - if (int_status & AT91C_MCI_RTOE) - mci_dbg("MMC: Response timeout\n"); - if (int_status & AT91C_MCI_RENDE) - mci_dbg("MMC: Response end bit error\n"); - if (int_status & AT91C_MCI_RCRCE) - mci_dbg("MMC: Response CRC error\n"); - if (int_status & AT91C_MCI_RDIRE) - mci_dbg("MMC: Response direction error\n"); - if (int_status & AT91C_MCI_RINDE) - mci_dbg("MMC: Response index error\n"); - } - else - { - /* Only continue processing if no errors */ + if (int_status & AT91C_MCI_UNRE) + mci_dbg("MMC: Underrun error\n"); + if (int_status & AT91C_MCI_OVRE) + mci_dbg("MMC: Overrun error\n"); + if (int_status & AT91C_MCI_DTOE) + mci_dbg("MMC: Data timeout\n"); + if (int_status & AT91C_MCI_DCRCE) + mci_dbg("MMC: CRC error in data\n"); + if (int_status & AT91C_MCI_RTOE) + mci_dbg("MMC: Response timeout\n"); + if (int_status & AT91C_MCI_RENDE) + mci_dbg("MMC: Response end bit error\n"); + if (int_status & AT91C_MCI_RCRCE) + mci_dbg("MMC: Response CRC error\n"); + if (int_status & AT91C_MCI_RDIRE) + mci_dbg("MMC: Response direction error\n"); + if (int_status & AT91C_MCI_RINDE) + mci_dbg("MMC: Response index error\n"); + } + else + { + /* Only continue processing if no errors */ - if (int_status & AT91C_MCI_TXBUFE) - { - mci_dbg("TX buffer empty\n"); - at91_mci_handle_transmitted(mci); - } + if (int_status & AT91C_MCI_TXBUFE) + { + mci_dbg("TX buffer empty\n"); + at91_mci_handle_transmitted(mci); + } - if (int_status & AT91C_MCI_ENDRX) - { - mci_dbg("ENDRX\n"); - at91_mci_post_dma_read(mci); - } + if (int_status & AT91C_MCI_ENDRX) + { + mci_dbg("ENDRX\n"); + at91_mci_post_dma_read(mci); + } - if (int_status & AT91C_MCI_RXBUFF) - { - mci_dbg("RX buffer full\n"); - at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS); - at91_mci_write(AT91C_MCI_IDR, AT91C_MCI_RXBUFF | AT91C_MCI_ENDRX); - completed = 1; - } + if (int_status & AT91C_MCI_RXBUFF) + { + mci_dbg("RX buffer full\n"); + at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS); + at91_mci_write(AT91C_MCI_IDR, AT91C_MCI_RXBUFF | AT91C_MCI_ENDRX); + completed = 1; + } - if (int_status & AT91C_MCI_ENDTX) - mci_dbg("Transmit has ended\n"); + if (int_status & AT91C_MCI_ENDTX) + mci_dbg("Transmit has ended\n"); - if (int_status & AT91C_MCI_NOTBUSY) - { - mci_dbg("Card is ready\n"); - //at91_mci_update_bytes_xfered(host); - completed = 1; - } + if (int_status & AT91C_MCI_NOTBUSY) + { + mci_dbg("Card is ready\n"); + //at91_mci_update_bytes_xfered(host); + completed = 1; + } - if (int_status & AT91C_MCI_DTIP) - mci_dbg("Data transfer in progress\n"); + if (int_status & AT91C_MCI_DTIP) + mci_dbg("Data transfer in progress\n"); - if (int_status & AT91C_MCI_BLKE) - { - mci_dbg("Block transfer has ended\n"); - if (mci->req->data && mci->req->data->blks > 1) - { - /* multi block write : complete multi write - * command and send stop */ - completed = 1; - } - else - { - at91_mci_write(AT91C_MCI_IER, AT91C_MCI_NOTBUSY); - } - } + if (int_status & AT91C_MCI_BLKE) + { + mci_dbg("Block transfer has ended\n"); + if (mci->req->data && mci->req->data->blks > 1) + { + /* multi block write : complete multi write + * command and send stop */ + completed = 1; + } + else + { + at91_mci_write(AT91C_MCI_IER, AT91C_MCI_NOTBUSY); + } + } - /*if (int_status & AT91C_MCI_SDIOIRQA) - rt_mmcsd_signal_sdio_irq(host->mmc);*/ + /*if (int_status & AT91C_MCI_SDIOIRQA) + rt_mmcsd_signal_sdio_irq(host->mmc);*/ - if (int_status & AT91C_MCI_SDIOIRQB) - sdio_irq_wakeup(mci->host); + if (int_status & AT91C_MCI_SDIOIRQB) + sdio_irq_wakeup(mci->host); - if (int_status & AT91C_MCI_TXRDY) - mci_dbg("Ready to transmit\n"); + if (int_status & AT91C_MCI_TXRDY) + mci_dbg("Ready to transmit\n"); - if (int_status & AT91C_MCI_RXRDY) - mci_dbg("Ready to receive\n"); + if (int_status & AT91C_MCI_RXRDY) + mci_dbg("Ready to receive\n"); - if (int_status & AT91C_MCI_CMDRDY) - { - mci_dbg("Command ready\n"); - completed = at91_mci_handle_cmdrdy(mci); - } - } + if (int_status & AT91C_MCI_CMDRDY) + { + mci_dbg("Command ready\n"); + completed = at91_mci_handle_cmdrdy(mci); + } + } - if (completed) - { - mci_dbg("Completed command\n"); - at91_mci_write(AT91C_MCI_IDR, 0xffffffff & ~(AT91C_MCI_SDIOIRQA | AT91C_MCI_SDIOIRQB)); - at91_mci_completed_command(mci, int_status); - } - else - at91_mci_write(AT91C_MCI_IDR, int_status & ~(AT91C_MCI_SDIOIRQA | AT91C_MCI_SDIOIRQB)); + if (completed) + { + mci_dbg("Completed command\n"); + at91_mci_write(AT91C_MCI_IDR, 0xffffffff & ~(AT91C_MCI_SDIOIRQA | AT91C_MCI_SDIOIRQB)); + at91_mci_completed_command(mci, int_status); + } + else + at91_mci_write(AT91C_MCI_IDR, int_status & ~(AT91C_MCI_SDIOIRQA | AT91C_MCI_SDIOIRQB)); } @@ -734,173 +720,173 @@ static void at91_mci_irq(int irq, void *param) */ static void at91_mci_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) { - rt_uint32_t clkdiv; - //struct at91_mci *mci = host->private_data; - rt_uint32_t at91_master_clock = clk_get_rate(clk_get("mck")); + rt_uint32_t clkdiv; + //struct at91_mci *mci = host->private_data; + rt_uint32_t at91_master_clock = clk_get_rate(clk_get("mck")); - if (io_cfg->clock == 0) - { - /* Disable the MCI controller */ - at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIDIS); - clkdiv = 0; - } - else - { - /* Enable the MCI controller */ - at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIEN); + if (io_cfg->clock == 0) + { + /* Disable the MCI controller */ + at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIDIS); + clkdiv = 0; + } + else + { + /* Enable the MCI controller */ + at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIEN); - if ((at91_master_clock % (io_cfg->clock * 2)) == 0) - clkdiv = ((at91_master_clock / io_cfg->clock) / 2) - 1; - else - clkdiv = (at91_master_clock / io_cfg->clock) / 2; + if ((at91_master_clock % (io_cfg->clock * 2)) == 0) + clkdiv = ((at91_master_clock / io_cfg->clock) / 2) - 1; + else + clkdiv = (at91_master_clock / io_cfg->clock) / 2; - mci_dbg("clkdiv = %d. mcck = %ld\n", clkdiv, - at91_master_clock / (2 * (clkdiv + 1))); - } - if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4) - { - mci_dbg("MMC: Setting controller bus width to 4\n"); - at91_mci_write(AT91C_MCI_SDCR, at91_mci_read(AT91C_MCI_SDCR) | AT91C_MCI_SDCBUS); - } - else - { - mci_dbg("MMC: Setting controller bus width to 1\n"); - at91_mci_write(AT91C_MCI_SDCR, at91_mci_read(AT91C_MCI_SDCR) & ~AT91C_MCI_SDCBUS); - } + mci_dbg("clkdiv = %d. mcck = %ld\n", clkdiv, + at91_master_clock / (2 * (clkdiv + 1))); + } + if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4) + { + mci_dbg("MMC: Setting controller bus width to 4\n"); + at91_mci_write(AT91C_MCI_SDCR, at91_mci_read(AT91C_MCI_SDCR) | AT91C_MCI_SDCBUS); + } + else + { + mci_dbg("MMC: Setting controller bus width to 1\n"); + at91_mci_write(AT91C_MCI_SDCR, at91_mci_read(AT91C_MCI_SDCR) & ~AT91C_MCI_SDCBUS); + } - /* Set the clock divider */ - at91_mci_write(AT91C_MCI_MR, (at91_mci_read(AT91C_MCI_MR) & ~AT91C_MCI_CLKDIV) | clkdiv); + /* Set the clock divider */ + at91_mci_write(AT91C_MCI_MR, (at91_mci_read(AT91C_MCI_MR) & ~AT91C_MCI_CLKDIV) | clkdiv); - /* maybe switch power to the card */ - switch (io_cfg->power_mode) - { - case MMCSD_POWER_OFF: - break; - case MMCSD_POWER_UP: - break; - case MMCSD_POWER_ON: - /*at91_mci_write(AT91C_MCI_ARGR, 0); - at91_mci_write(AT91C_MCI_CMDR, 0|AT91C_MCI_SPCMD_INIT|AT91C_MCI_OPDCMD); - mci_dbg("MCI_SR=0x%08x\n", at91_mci_read(AT91C_MCI_SR)); - while (!(at91_mci_read(AT91C_MCI_SR) & AT91C_MCI_CMDRDY)) - { - - } - mci_dbg("at91 mci power on\n");*/ - break; - default: - rt_kprintf("unknown power_mode %d\n", io_cfg->power_mode); - break; - } + /* maybe switch power to the card */ + switch (io_cfg->power_mode) + { + case MMCSD_POWER_OFF: + break; + case MMCSD_POWER_UP: + break; + case MMCSD_POWER_ON: + /*at91_mci_write(AT91C_MCI_ARGR, 0); + at91_mci_write(AT91C_MCI_CMDR, 0|AT91C_MCI_SPCMD_INIT|AT91C_MCI_OPDCMD); + mci_dbg("MCI_SR=0x%08x\n", at91_mci_read(AT91C_MCI_SR)); + while (!(at91_mci_read(AT91C_MCI_SR) & AT91C_MCI_CMDRDY)) + { + + } + mci_dbg("at91 mci power on\n");*/ + break; + default: + rt_kprintf("unknown power_mode %d\n", io_cfg->power_mode); + break; + } } static void at91_mci_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t enable) { - at91_mci_write(enable ? AT91C_MCI_IER : AT91C_MCI_IDR, AT91C_MCI_SDIOIRQB); + at91_mci_write(enable ? AT91C_MCI_IER : AT91C_MCI_IDR, AT91C_MCI_SDIOIRQB); } static const struct rt_mmcsd_host_ops ops = { - at91_mci_request, - at91_mci_set_iocfg, + at91_mci_request, + at91_mci_set_iocfg, RT_NULL, - at91_mci_enable_sdio_irq, + at91_mci_enable_sdio_irq, }; void at91_mci_detect(int irq, void *param) { - rt_kprintf("mmcsd gpio detected\n"); + rt_kprintf("mmcsd gpio detected\n"); } static void mci_gpio_init() { #ifdef USE_SLOT_B - AT91C_BASE_PIOA->PIO_PUER = (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5); - AT91C_BASE_PIOA->PIO_PUDR = (1 << 8); - AT91C_BASE_PIOA->PIO_BSR = (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5); - AT91C_BASE_PIOA->PIO_ASR = (1 << 8); - AT91C_BASE_PIOA->PIO_PDR = (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)|(1 << 8); + AT91C_BASE_PIOA->PIO_PUER = (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5); + AT91C_BASE_PIOA->PIO_PUDR = (1 << 8); + AT91C_BASE_PIOA->PIO_BSR = (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5); + AT91C_BASE_PIOA->PIO_ASR = (1 << 8); + AT91C_BASE_PIOA->PIO_PDR = (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)|(1 << 8); - AT91C_BASE_PIOA->PIO_IDR = (1 << 6)|(1 << 7); - AT91C_BASE_PIOA->PIO_PUER = (1 << 6)|(1 << 7); - AT91C_BASE_PIOA->PIO_ODR = (1 << 6)|(1 << 7); - AT91C_BASE_PIOA->PIO_PER = (1 << 6)|(1 << 7); + AT91C_BASE_PIOA->PIO_IDR = (1 << 6)|(1 << 7); + AT91C_BASE_PIOA->PIO_PUER = (1 << 6)|(1 << 7); + AT91C_BASE_PIOA->PIO_ODR = (1 << 6)|(1 << 7); + AT91C_BASE_PIOA->PIO_PER = (1 << 6)|(1 << 7); #else - AT91C_BASE_PIOA->PIO_PUER = (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11); - AT91C_BASE_PIOA->PIO_ASR = (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8); - AT91C_BASE_PIOA->PIO_PDR = (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8); + AT91C_BASE_PIOA->PIO_PUER = (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11); + AT91C_BASE_PIOA->PIO_ASR = (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8); + AT91C_BASE_PIOA->PIO_PDR = (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8); #endif } int at91_mci_init(void) { - struct rt_mmcsd_host *host; - struct at91_mci *mci; + struct rt_mmcsd_host *host; + struct at91_mci *mci; - host = mmcsd_alloc_host(); - if (!host) - { - return -RT_ERROR; - } + host = mmcsd_alloc_host(); + if (!host) + { + return -RT_ERROR; + } - mci = rt_malloc(sizeof(struct at91_mci)); - if (!mci) - { - rt_kprintf("alloc mci failed\n"); - goto err; - } + mci = rt_malloc(sizeof(struct at91_mci)); + if (!mci) + { + rt_kprintf("alloc mci failed\n"); + goto err; + } - rt_memset(mci, 0, sizeof(struct at91_mci)); + rt_memset(mci, 0, sizeof(struct at91_mci)); - host->ops = &ops; - host->freq_min = 375000; - host->freq_max = 25000000; - host->valid_ocr = VDD_32_33 | VDD_33_34; - host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \ - MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ; - host->max_seg_size = 65535; - host->max_dma_segs = 2; - host->max_blk_size = 512; - host->max_blk_count = 4096; + host->ops = &ops; + host->freq_min = 375000; + host->freq_max = 25000000; + host->valid_ocr = VDD_32_33 | VDD_33_34; + host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \ + MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ; + host->max_seg_size = 65535; + host->max_dma_segs = 2; + host->max_blk_size = 512; + host->max_blk_count = 4096; - mci->host = host; + mci->host = host; - mci_gpio_init(); - AT91C_BASE_PMC->AT91C_PMC_PCER = 1 << AT91C_ID_MCI; //enable MCI clock - - at91_mci_disable(); - at91_mci_enable(); + mci_gpio_init(); + AT91C_BASE_PMC->AT91C_PMC_PCER = 1 << AT91C_ID_MCI; //enable MCI clock - /* instal interrupt */ - rt_hw_interrupt_install(AT91SAM9260_ID_MCI, at91_mci_irq, - (void *)mci, "MMC"); - rt_hw_interrupt_umask(AT91SAM9260_ID_MCI); - rt_hw_interrupt_install(gpio_to_irq(AT91C_PIN_PA7), - at91_mci_detect, RT_NULL, "MMC_DETECT"); - rt_hw_interrupt_umask(gpio_to_irq(AT91C_PIN_PA7)); + at91_mci_disable(); + at91_mci_enable(); - rt_timer_init(&mci->timer, "mci_timer", - at91_timeout_timer, - mci, - RT_TICK_PER_SECOND, - RT_TIMER_FLAG_PERIODIC); + /* instal interrupt */ + rt_hw_interrupt_install(AT91SAM9260_ID_MCI, at91_mci_irq, + (void *)mci, "MMC"); + rt_hw_interrupt_umask(AT91SAM9260_ID_MCI); + rt_hw_interrupt_install(gpio_to_irq(AT91C_PIN_PA7), + at91_mci_detect, RT_NULL, "MMC_DETECT"); + rt_hw_interrupt_umask(gpio_to_irq(AT91C_PIN_PA7)); - //rt_timer_start(&mci->timer); + rt_timer_init(&mci->timer, "mci_timer", + at91_timeout_timer, + mci, + RT_TICK_PER_SECOND, + RT_TIMER_FLAG_PERIODIC); - //rt_sem_init(&mci->sem_ack, "sd_ack", 0, RT_IPC_FLAG_FIFO); + //rt_timer_start(&mci->timer); - host->private_data = mci; + //rt_sem_init(&mci->sem_ack, "sd_ack", 0, RT_IPC_FLAG_FIFO); - mmcsd_change(host); + host->private_data = mci; - return 0; + mmcsd_change(host); + + return 0; err: - mmcsd_free_host(host); + mmcsd_free_host(host); - return -RT_ENOMEM; + return -RT_ENOMEM; } INIT_DEVICE_EXPORT(at91_mci_init); @@ -910,15 +896,15 @@ FINSH_FUNCTION_EXPORT(at91_mci_init, at91sam9260 sd init); void mci_dump(void) { - rt_uint32_t i; + rt_uint32_t i; - rt_kprintf("PIOA_PSR=0x%08x\n", readl(AT91C_PIOA+PIO_PSR)); - rt_kprintf("PIOA_ABSR=0x%08x\n", readl(AT91C_PIOA+PIO_ABSR)); - rt_kprintf("PIOA_PUSR=0x%08x\n", readl(AT91C_PIOA+PIO_PUSR)); + rt_kprintf("PIOA_PSR=0x%08x\n", readl(AT91C_PIOA+PIO_PSR)); + rt_kprintf("PIOA_ABSR=0x%08x\n", readl(AT91C_PIOA+PIO_ABSR)); + rt_kprintf("PIOA_PUSR=0x%08x\n", readl(AT91C_PIOA+PIO_PUSR)); - for (i = 0; i <= 0x4c; i += 4) { - rt_kprintf("0x%08x:0x%08x\n", AT91SAM9260_BASE_MCI+i, at91_mci_read(i)); - } + for (i = 0; i <= 0x4c; i += 4) { + rt_kprintf("0x%08x:0x%08x\n", AT91SAM9260_BASE_MCI+i, at91_mci_read(i)); + } } FINSH_FUNCTION_EXPORT(mci_dump, dump register for mci); diff --git a/bsp/at91sam9g45/drivers/at91_mci.h b/bsp/at91sam9g45/drivers/at91_mci.h index b3bfd289b1..3a4cc1705a 100644 --- a/bsp/at91sam9g45/drivers/at91_mci.h +++ b/bsp/at91sam9g45/drivers/at91_mci.h @@ -1,21 +1,7 @@ /* - * File : at91_mci.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -25,99 +11,99 @@ #ifndef __AT91C_MCI_H__ #define __AT91C_MCI_H__ -#define AT91C_MCI_CR 0x00 /* Control Register */ -#define AT91C_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */ -#define AT91C_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */ -#define AT91C_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */ -#define AT91C_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */ -#define AT91C_MCI_SWRST (1 << 7) /* Software Reset */ +#define AT91C_MCI_CR 0x00 /* Control Register */ +#define AT91C_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */ +#define AT91C_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */ +#define AT91C_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */ +#define AT91C_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */ +#define AT91C_MCI_SWRST (1 << 7) /* Software Reset */ -#define AT91C_MCI_MR 0x04 /* Mode Register */ -#define AT91C_MCI_CLKDIV (0xff << 0) /* Clock Divider */ -#define AT91C_MCI_PWSDIV (7 << 8) /* Power Saving Divider */ -#define AT91C_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */ -#define AT91C_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */ -#define AT91C_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */ -#define AT91C_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ -#define AT91C_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ -#define AT91C_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ +#define AT91C_MCI_MR 0x04 /* Mode Register */ +#define AT91C_MCI_CLKDIV (0xff << 0) /* Clock Divider */ +#define AT91C_MCI_PWSDIV (7 << 8) /* Power Saving Divider */ +#define AT91C_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */ +#define AT91C_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */ +#define AT91C_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */ +#define AT91C_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ +#define AT91C_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ +#define AT91C_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ -#define AT91C_MCI_DTOR 0x08 /* Data Timeout Register */ -#define AT91C_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */ -#define AT91C_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */ -#define AT91C_MCI_DTOMUL_1 (0 << 4) -#define AT91C_MCI_DTOMUL_16 (1 << 4) -#define AT91C_MCI_DTOMUL_128 (2 << 4) -#define AT91C_MCI_DTOMUL_256 (3 << 4) -#define AT91C_MCI_DTOMUL_1K (4 << 4) -#define AT91C_MCI_DTOMUL_4K (5 << 4) -#define AT91C_MCI_DTOMUL_64K (6 << 4) -#define AT91C_MCI_DTOMUL_1M (7 << 4) +#define AT91C_MCI_DTOR 0x08 /* Data Timeout Register */ +#define AT91C_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */ +#define AT91C_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */ +#define AT91C_MCI_DTOMUL_1 (0 << 4) +#define AT91C_MCI_DTOMUL_16 (1 << 4) +#define AT91C_MCI_DTOMUL_128 (2 << 4) +#define AT91C_MCI_DTOMUL_256 (3 << 4) +#define AT91C_MCI_DTOMUL_1K (4 << 4) +#define AT91C_MCI_DTOMUL_4K (5 << 4) +#define AT91C_MCI_DTOMUL_64K (6 << 4) +#define AT91C_MCI_DTOMUL_1M (7 << 4) -#define AT91C_MCI_SDCR 0x0c /* SD Card Register */ -#define AT91C_MCI_SDCSEL (3 << 0) /* SD Card Selector */ -#define AT91C_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */ +#define AT91C_MCI_SDCR 0x0c /* SD Card Register */ +#define AT91C_MCI_SDCSEL (3 << 0) /* SD Card Selector */ +#define AT91C_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */ -#define AT91C_MCI_ARGR 0x10 /* Argument Register */ +#define AT91C_MCI_ARGR 0x10 /* Argument Register */ -#define AT91C_MCI_CMDR 0x14 /* Command Register */ -#define AT91C_MCI_CMDNB (0x3f << 0) /* Command Number */ -#define AT91C_MCI_RSPTYP (3 << 6) /* Response Type */ -#define AT91C_MCI_RSPTYP_NONE (0 << 6) -#define AT91C_MCI_RSPTYP_48 (1 << 6) -#define AT91C_MCI_RSPTYP_136 (2 << 6) -#define AT91C_MCI_SPCMD (7 << 8) /* Special Command */ -#define AT91C_MCI_SPCMD_NONE (0 << 8) -#define AT91C_MCI_SPCMD_INIT (1 << 8) -#define AT91C_MCI_SPCMD_SYNC (2 << 8) -#define AT91C_MCI_SPCMD_ICMD (4 << 8) -#define AT91C_MCI_SPCMD_IRESP (5 << 8) -#define AT91C_MCI_OPDCMD (1 << 11) /* Open Drain Command */ -#define AT91C_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */ -#define AT91C_MCI_TRCMD (3 << 16) /* Transfer Command */ -#define AT91C_MCI_TRCMD_NONE (0 << 16) -#define AT91C_MCI_TRCMD_START (1 << 16) -#define AT91C_MCI_TRCMD_STOP (2 << 16) -#define AT91C_MCI_TRDIR (1 << 18) /* Transfer Direction */ -#define AT91C_MCI_TRTYP (3 << 19) /* Transfer Type */ -#define AT91C_MCI_TRTYP_BLOCK (0 << 19) -#define AT91C_MCI_TRTYP_MULTIPLE (1 << 19) -#define AT91C_MCI_TRTYP_STREAM (2 << 19) +#define AT91C_MCI_CMDR 0x14 /* Command Register */ +#define AT91C_MCI_CMDNB (0x3f << 0) /* Command Number */ +#define AT91C_MCI_RSPTYP (3 << 6) /* Response Type */ +#define AT91C_MCI_RSPTYP_NONE (0 << 6) +#define AT91C_MCI_RSPTYP_48 (1 << 6) +#define AT91C_MCI_RSPTYP_136 (2 << 6) +#define AT91C_MCI_SPCMD (7 << 8) /* Special Command */ +#define AT91C_MCI_SPCMD_NONE (0 << 8) +#define AT91C_MCI_SPCMD_INIT (1 << 8) +#define AT91C_MCI_SPCMD_SYNC (2 << 8) +#define AT91C_MCI_SPCMD_ICMD (4 << 8) +#define AT91C_MCI_SPCMD_IRESP (5 << 8) +#define AT91C_MCI_OPDCMD (1 << 11) /* Open Drain Command */ +#define AT91C_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */ +#define AT91C_MCI_TRCMD (3 << 16) /* Transfer Command */ +#define AT91C_MCI_TRCMD_NONE (0 << 16) +#define AT91C_MCI_TRCMD_START (1 << 16) +#define AT91C_MCI_TRCMD_STOP (2 << 16) +#define AT91C_MCI_TRDIR (1 << 18) /* Transfer Direction */ +#define AT91C_MCI_TRTYP (3 << 19) /* Transfer Type */ +#define AT91C_MCI_TRTYP_BLOCK (0 << 19) +#define AT91C_MCI_TRTYP_MULTIPLE (1 << 19) +#define AT91C_MCI_TRTYP_STREAM (2 << 19) -#define AT91C_MCI_BLKR 0x18 /* Block Register */ -#define AT91C_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0) /* Block count */ -#define AT91C_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16) /* Block lenght */ +#define AT91C_MCI_BLKR 0x18 /* Block Register */ +#define AT91C_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0) /* Block count */ +#define AT91C_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16) /* Block lenght */ -#define AT91C_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */ -#define AT91C_MCR_RDR 0x30 /* Receive Data Register */ -#define AT91C_MCR_TDR 0x34 /* Transmit Data Register */ +#define AT91C_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */ +#define AT91C_MCR_RDR 0x30 /* Receive Data Register */ +#define AT91C_MCR_TDR 0x34 /* Transmit Data Register */ -#define AT91C_MCI_SR 0x40 /* Status Register */ -#define AT91C_MCI_CMDRDY (1U << 0) /* Command Ready */ -#define AT91C_MCI_RXRDY (1U << 1) /* Receiver Ready */ -#define AT91C_MCI_TXRDY (1U << 2) /* Transmit Ready */ -#define AT91C_MCI_BLKE (1U << 3) /* Data Block Ended */ -#define AT91C_MCI_DTIP (1U << 4) /* Data Transfer in Progress */ -#define AT91C_MCI_NOTBUSY (1U << 5) /* Data Not Busy */ -#define AT91C_MCI_ENDRX (1U << 6) /* End of RX Buffer */ -#define AT91C_MCI_ENDTX (1U << 7) /* End fo TX Buffer */ -#define AT91C_MCI_SDIOIRQA (1U << 8) /* SDIO Interrupt for Slot A */ -#define AT91C_MCI_SDIOIRQB (1U << 9) /* SDIO Interrupt for Slot B */ -#define AT91C_MCI_RXBUFF (1U << 14) /* RX Buffer Full */ -#define AT91C_MCI_TXBUFE (1U << 15) /* TX Buffer Empty */ -#define AT91C_MCI_RINDE (1U << 16) /* Response Index Error */ -#define AT91C_MCI_RDIRE (1U << 17) /* Response Direction Error */ -#define AT91C_MCI_RCRCE (1U << 18) /* Response CRC Error */ -#define AT91C_MCI_RENDE (1U << 19) /* Response End Bit Error */ -#define AT91C_MCI_RTOE (1U << 20) /* Reponse Time-out Error */ -#define AT91C_MCI_DCRCE (1U << 21) /* Data CRC Error */ -#define AT91C_MCI_DTOE (1U << 22) /* Data Time-out Error */ -#define AT91C_MCI_OVRE (1U << 30) /* Overrun */ -#define AT91C_MCI_UNRE (1U << 31) /* Underrun */ +#define AT91C_MCI_SR 0x40 /* Status Register */ +#define AT91C_MCI_CMDRDY (1U << 0) /* Command Ready */ +#define AT91C_MCI_RXRDY (1U << 1) /* Receiver Ready */ +#define AT91C_MCI_TXRDY (1U << 2) /* Transmit Ready */ +#define AT91C_MCI_BLKE (1U << 3) /* Data Block Ended */ +#define AT91C_MCI_DTIP (1U << 4) /* Data Transfer in Progress */ +#define AT91C_MCI_NOTBUSY (1U << 5) /* Data Not Busy */ +#define AT91C_MCI_ENDRX (1U << 6) /* End of RX Buffer */ +#define AT91C_MCI_ENDTX (1U << 7) /* End fo TX Buffer */ +#define AT91C_MCI_SDIOIRQA (1U << 8) /* SDIO Interrupt for Slot A */ +#define AT91C_MCI_SDIOIRQB (1U << 9) /* SDIO Interrupt for Slot B */ +#define AT91C_MCI_RXBUFF (1U << 14) /* RX Buffer Full */ +#define AT91C_MCI_TXBUFE (1U << 15) /* TX Buffer Empty */ +#define AT91C_MCI_RINDE (1U << 16) /* Response Index Error */ +#define AT91C_MCI_RDIRE (1U << 17) /* Response Direction Error */ +#define AT91C_MCI_RCRCE (1U << 18) /* Response CRC Error */ +#define AT91C_MCI_RENDE (1U << 19) /* Response End Bit Error */ +#define AT91C_MCI_RTOE (1U << 20) /* Reponse Time-out Error */ +#define AT91C_MCI_DCRCE (1U << 21) /* Data CRC Error */ +#define AT91C_MCI_DTOE (1U << 22) /* Data Time-out Error */ +#define AT91C_MCI_OVRE (1U << 30) /* Overrun */ +#define AT91C_MCI_UNRE (1U << 31) /* Underrun */ -#define AT91C_MCI_IER 0x44 /* Interrupt Enable Register */ -#define AT91C_MCI_IDR 0x48 /* Interrupt Disable Register */ -#define AT91C_MCI_IMR 0x4c /* Interrupt Mask Register */ +#define AT91C_MCI_IER 0x44 /* Interrupt Enable Register */ +#define AT91C_MCI_IDR 0x48 /* Interrupt Disable Register */ +#define AT91C_MCI_IMR 0x4c /* Interrupt Mask Register */ extern int at91_mci_init(void); diff --git a/bsp/at91sam9g45/drivers/board.c b/bsp/at91sam9g45/drivers/board.c index 59ac3f1ba4..5d97e1d115 100644 --- a/bsp/at91sam9g45/drivers/board.c +++ b/bsp/at91sam9g45/drivers/board.c @@ -1,21 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -53,36 +39,36 @@ extern void rt_hw_set_dividor(rt_uint8_t hdivn, rt_uint8_t pdivn); extern void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv); extern void rt_dbgu_isr(void); -#define SAM9G45_BLOCK_SIZE 0x10000000 // 256M -#define MMU_SECTION_SIZE 0x100000 // 1M -#define PERIPHERALS_ADDR // 1M +#define SAM9G45_BLOCK_SIZE 0x10000000 // 256M +#define MMU_SECTION_SIZE 0x100000 // 1M +#define PERIPHERALS_ADDR // 1M -#define SECTION_END(sa) ((sa) + MMU_SECTION_SIZE - 1) // sa: start address -#define BLOCK_END(ba) ((ba) + SAM9G45_BLOCK_SIZE - 1) // ba: block address +#define SECTION_END(sa) ((sa) + MMU_SECTION_SIZE - 1) // sa: start address +#define BLOCK_END(ba) ((ba) + SAM9G45_BLOCK_SIZE - 1) // ba: block address -static struct mem_desc at91_mem_desc[] = { /* FIXME, hornby, to confirm MMU and memory */ - { 0x00000000, 0xFFFFFFFF , 0x00000000, RW_NCNB }, /* None cached for 4G memory */ - //{ 0x00000000, SECTION_END(0x00000000), 0x00000000, RW_CNB }, /* TLB for ITCM, ITCM map to address zero, 32KB */ - //{ 0x00200000, SECTION_END(0x00200000), 0x00200000, RW_CNB }, /* TLB for DTCM, 32KB */ - //{ 0x00300000, SECTION_END(0x00300000), 0x00300000, RW_CNB }, /* TLB for internal RAM, 64KB, we use it as global variable area */ - //{ 0x00600000, SECTION_END(0x00600000), 0x00600000, RW_NCNB }, /* TLB for UDPHS(DMA) */ - //{ 0x00700000, SECTION_END(0x00700000), 0x00700000, RW_NCNB }, /* TLB for UHP OHCI */ - //{ 0x00800000, SECTION_END(0x00800000), 0x00800000, RW_NCNB }, /* TLB for UHP EHCI */ - //{ 0x30000000, 0x30000000+0x00100000-1, 0x30000000, RW_CB }, /* 1M external SRAM for program code and stack */ - //{ 0x40000000, BLOCK_END(0x40000000), 0x40000000, RW_NCNB }, /* 256M for nand-flash controller */ - //{ 0x60000000, BLOCK_END(0x60000000), 0x60000000, RW_NCNB }, /* 256M for FPGA */ - //{ 0x70000000, 0x70000000+0x08000000-1, 0x70000000, RW_NCNB }, /* 128M for main DDR-SDRAM for print data */ - { 0x00000000, SECTION_END(0x00000000), 0x70000000, RW_CB }, /* isr */ - { 0x70000000, 0x70000000+0x08000000-1, 0x70000000, RW_CB }, /* 128M for main DDR-SDRAM for print data */ - //{ 0xFFF00000, SECTION_END(0xFFF00000), 0xFFF00000, RW_NCNB }, /* Internal Peripherals, 1MB */ +static struct mem_desc at91_mem_desc[] = { /* FIXME, hornby, to confirm MMU and memory */ + { 0x00000000, 0xFFFFFFFF , 0x00000000, RW_NCNB }, /* None cached for 4G memory */ + //{ 0x00000000, SECTION_END(0x00000000), 0x00000000, RW_CNB }, /* TLB for ITCM, ITCM map to address zero, 32KB */ + //{ 0x00200000, SECTION_END(0x00200000), 0x00200000, RW_CNB }, /* TLB for DTCM, 32KB */ + //{ 0x00300000, SECTION_END(0x00300000), 0x00300000, RW_CNB }, /* TLB for internal RAM, 64KB, we use it as global variable area */ + //{ 0x00600000, SECTION_END(0x00600000), 0x00600000, RW_NCNB }, /* TLB for UDPHS(DMA) */ + //{ 0x00700000, SECTION_END(0x00700000), 0x00700000, RW_NCNB }, /* TLB for UHP OHCI */ + //{ 0x00800000, SECTION_END(0x00800000), 0x00800000, RW_NCNB }, /* TLB for UHP EHCI */ + //{ 0x30000000, 0x30000000+0x00100000-1, 0x30000000, RW_CB }, /* 1M external SRAM for program code and stack */ + //{ 0x40000000, BLOCK_END(0x40000000), 0x40000000, RW_NCNB }, /* 256M for nand-flash controller */ + //{ 0x60000000, BLOCK_END(0x60000000), 0x60000000, RW_NCNB }, /* 256M for FPGA */ + //{ 0x70000000, 0x70000000+0x08000000-1, 0x70000000, RW_NCNB }, /* 128M for main DDR-SDRAM for print data */ + { 0x00000000, SECTION_END(0x00000000), 0x70000000, RW_CB }, /* isr */ + { 0x70000000, 0x70000000+0x08000000-1, 0x70000000, RW_CB }, /* 128M for main DDR-SDRAM for print data */ + //{ 0xFFF00000, SECTION_END(0xFFF00000), 0xFFF00000, RW_NCNB }, /* Internal Peripherals, 1MB */ }; -#define PIT_CPIV(x) ((x) & AT91C_PITC_CPIV) -#define PIT_PICNT(x) (((x) & AT91C_PITC_PICNT) >> 20) +#define PIT_CPIV(x) ((x) & AT91C_PITC_CPIV) +#define PIT_PICNT(x) (((x) & AT91C_PITC_PICNT) >> 20) -static rt_uint32_t pit_cycle; /* write-once */ -static rt_uint32_t pit_cnt; /* access only w/system irq blocked */ +static rt_uint32_t pit_cycle; /* write-once */ +static rt_uint32_t pit_cnt; /* access only w/system irq blocked */ /** * This function will handle rtos timer @@ -90,37 +76,37 @@ static rt_uint32_t pit_cnt; /* access only w/system irq blocked */ void rt_timer_handler(int vector, void *param) { #ifdef RT_USING_DBGU - if (readl(AT91C_DBGU_CSR) & AT91C_US_RXRDY) - { - rt_dbgu_isr(); - } + if (readl(AT91C_DBGU_CSR) & AT91C_US_RXRDY) + { + rt_dbgu_isr(); + } #endif - if (readl(AT91C_PITC_PISR) & AT91C_PITC_PITS) - { - unsigned nr_ticks; + if (readl(AT91C_PITC_PISR) & AT91C_PITC_PITS) + { + unsigned nr_ticks; - /* Get number of ticks performed before irq, and ack it */ - nr_ticks = PIT_PICNT(readl(AT91C_PITC_PIVR)); + /* Get number of ticks performed before irq, and ack it */ + nr_ticks = PIT_PICNT(readl(AT91C_PITC_PIVR)); while (nr_ticks--) - rt_tick_increase(); - } + rt_tick_increase(); + } } static void at91sam9g45_pit_reset(void) { - /* Disable timer and irqs */ - AT91C_BASE_PITC->PITC_PIMR = 0; + /* Disable timer and irqs */ + AT91C_BASE_PITC->PITC_PIMR = 0; - /* Clear any pending interrupts, wait for PIT to stop counting */ - while (PIT_CPIV(readl(AT91C_PITC_PIVR)) != 0) - ; + /* Clear any pending interrupts, wait for PIT to stop counting */ + while (PIT_CPIV(readl(AT91C_PITC_PIVR)) != 0) + ; - /* Start PIT but don't enable IRQ */ - //AT91C_BASE_PITC->PITC_PIMR = (pit_cycle - 1) | AT91C_PITC_PITEN; - pit_cnt += pit_cycle * PIT_PICNT(readl(AT91C_PITC_PIVR)); - AT91C_BASE_PITC->PITC_PIMR = - (pit_cycle - 1) | AT91C_PITC_PITEN | AT91C_PITC_PITIEN; - rt_kprintf("PIT_MR=0x%08x\n", readl(AT91C_PITC_PIMR)); + /* Start PIT but don't enable IRQ */ + //AT91C_BASE_PITC->PITC_PIMR = (pit_cycle - 1) | AT91C_PITC_PITEN; + pit_cnt += pit_cycle * PIT_PICNT(readl(AT91C_PITC_PIVR)); + AT91C_BASE_PITC->PITC_PIMR = + (pit_cycle - 1) | AT91C_PITC_PITEN | AT91C_PITC_PITIEN; + rt_kprintf("PIT_MR=0x%08x\n", readl(AT91C_PITC_PIMR)); } /* @@ -128,19 +114,19 @@ static void at91sam9g45_pit_reset(void) */ static void at91sam9g45_pit_init(void) { - rt_uint32_t pit_rate; - //rt_uint32_t bits; + rt_uint32_t pit_rate; + //rt_uint32_t bits; - /* - * Use our actual MCK to figure out how many MCK/16 ticks per - * 1/HZ period (instead of a compile-time constant LATCH). - */ - pit_rate = clk_get_rate(clk_get("mck")) / 16; - rt_kprintf("pit_rate=%dHZ\n", pit_rate); - pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND; + /* + * Use our actual MCK to figure out how many MCK/16 ticks per + * 1/HZ period (instead of a compile-time constant LATCH). + */ + pit_rate = clk_get_rate(clk_get("mck")) / 16; + rt_kprintf("pit_rate=%dHZ\n", pit_rate); + pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND; - /* Initialize and enable the timer */ - at91sam9g45_pit_reset(); + /* Initialize and enable the timer */ + at91sam9g45_pit_reset(); } /** @@ -148,30 +134,30 @@ static void at91sam9g45_pit_init(void) */ void rt_hw_timer_init() { - at91sam9g45_pit_init(); + at91sam9g45_pit_init(); - /* install interrupt handler */ - rt_hw_interrupt_install(AT91C_ID_SYS, rt_timer_handler, - RT_NULL, "system"); - rt_hw_interrupt_umask(AT91C_ID_SYS); + /* install interrupt handler */ + rt_hw_interrupt_install(AT91C_ID_SYS, rt_timer_handler, + RT_NULL, "system"); + rt_hw_interrupt_umask(AT91C_ID_SYS); } void at91_tc1_init() { - AT91C_BASE_PMC->PMC_PCER = 1<PMC_PCER = 1<DBGU_CSR & AT91C_US_TXRDY)) - ; - AT91C_BASE_DBGU->DBGU_THR = c; + while (!(AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_TXRDY)) + ; + AT91C_BASE_DBGU->DBGU_THR = c; } /** @@ -182,33 +168,33 @@ static void at91_usart_putc(char c) */ void rt_hw_console_output(const char* str) { - while (*str) - { - if (*str=='\n') - { - at91_usart_putc('\r'); - } + while (*str) + { + if (*str=='\n') + { + at91_usart_putc('\r'); + } - at91_usart_putc(*str++); - } + at91_usart_putc(*str++); + } } static void rt_hw_console_init(void) { - int div; - int mode = 0; + int div; + int mode = 0; - AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RSTTX | AT91C_US_RSTRX | - AT91C_US_RXDIS | AT91C_US_TXDIS; - mode |= AT91C_US_USMODE_NORMAL | AT91C_US_CLKS_CLOCK | - AT91C_US_CHMODE_NORMAL; - mode |= AT91C_US_CHRL_8_BITS; - mode |= AT91C_US_NBSTOP_1_BIT; - mode |= AT91C_US_PAR_NONE; - AT91C_BASE_DBGU->DBGU_MR = mode; - div = (clk_get_rate(clk_get("mck")) / 16 + BPS/2) / BPS; - AT91C_BASE_DBGU->DBGU_BRGR = div; - AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RXEN | AT91C_US_TXEN; + AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RSTTX | AT91C_US_RSTRX | + AT91C_US_RXDIS | AT91C_US_TXDIS; + mode |= AT91C_US_USMODE_NORMAL | AT91C_US_CLKS_CLOCK | + AT91C_US_CHMODE_NORMAL; + mode |= AT91C_US_CHRL_8_BITS; + mode |= AT91C_US_NBSTOP_1_BIT; + mode |= AT91C_US_PAR_NONE; + AT91C_BASE_DBGU->DBGU_MR = mode; + div = (clk_get_rate(clk_get("mck")) / 16 + BPS/2) / BPS; + AT91C_BASE_DBGU->DBGU_BRGR = div; + AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RXEN | AT91C_US_TXEN; } @@ -217,31 +203,31 @@ static void rt_hw_console_init(void) */ void rt_hw_board_init() { - /* initialize the system clock */ - rt_hw_clock_init(); + /* initialize the system clock */ + rt_hw_clock_init(); - /* initialize console */ - rt_hw_console_init(); + /* initialize console */ + rt_hw_console_init(); - /* initialize mmu */ - rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0])); + /* initialize mmu */ + rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0])); - /* initialize hardware interrupt */ - rt_hw_interrupt_init(); + /* initialize hardware interrupt */ + rt_hw_interrupt_init(); - /* initialize early device */ + /* initialize early device */ #ifdef RT_USING_COMPONENTS_INIT - rt_components_board_init(); + rt_components_board_init(); #endif #ifdef RT_USING_CONSOLE - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif - /* initialize timer0 */ - rt_hw_timer_init(); + /* initialize timer0 */ + rt_hw_timer_init(); /* initialize board */ #ifdef RT_USING_HEAP - rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); #endif } diff --git a/bsp/at91sam9g45/drivers/board.h b/bsp/at91sam9g45/drivers/board.h index a6ec4e0ef7..1c3147b8f5 100644 --- a/bsp/at91sam9g45/drivers/board.h +++ b/bsp/at91sam9g45/drivers/board.h @@ -1,21 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/at91sam9g45/drivers/led.c b/bsp/at91sam9g45/drivers/led.c index fb8b417033..d4b377e629 100644 --- a/bsp/at91sam9g45/drivers/led.c +++ b/bsp/at91sam9g45/drivers/led.c @@ -1,21 +1,7 @@ /* - * File : led.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -35,10 +21,10 @@ void led_init(void) { - AT91C_BASE_PIOC->PIO_PER = LED_ALL; - AT91C_BASE_PIOC->PIO_OER = LED_ALL; - AT91C_BASE_PIOC->PIO_PPUER = LED_ALL; - AT91C_BASE_PIOC->PIO_SODR = LED_ALL; + AT91C_BASE_PIOC->PIO_PER = LED_ALL; + AT91C_BASE_PIOC->PIO_OER = LED_ALL; + AT91C_BASE_PIOC->PIO_PPUER = LED_ALL; + AT91C_BASE_PIOC->PIO_SODR = LED_ALL; } const static rt_uint32_t m_leds[] = { LED0, LED1, LED2, LED3 }; diff --git a/bsp/at91sam9g45/drivers/led.h b/bsp/at91sam9g45/drivers/led.h index f2967bc92d..9836eff709 100644 --- a/bsp/at91sam9g45/drivers/led.h +++ b/bsp/at91sam9g45/drivers/led.h @@ -1,21 +1,7 @@ /* - * File : led.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/at91sam9g45/drivers/macb.c b/bsp/at91sam9g45/drivers/macb.c index b5cffaa1d2..8a300725c3 100644 --- a/bsp/at91sam9g45/drivers/macb.c +++ b/bsp/at91sam9g45/drivers/macb.c @@ -1,21 +1,7 @@ /* - * File : macb.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -28,7 +14,7 @@ #include #include "macb.h" -#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31)) +#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31)) extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size); extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); @@ -36,11 +22,11 @@ extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); /* Cache macros - Packet buffers would be from pbuf pool which is cached */ #define EMAC_VIRT_NOCACHE(addr) (addr) #define EMAC_CACHE_INVALIDATE(addr, size) \ - mmu_invalidate_dcache((rt_uint32_t)addr, size) + mmu_invalidate_dcache((rt_uint32_t)addr, size) #define EMAC_CACHE_WRITEBACK(addr, size) \ - mmu_clean_dcache((rt_uint32_t)addr, size) + mmu_clean_dcache((rt_uint32_t)addr, size) #define EMAC_CACHE_WRITEBACK_INVALIDATE(addr, size) \ - mmu_clean_invalidated_dcache((rt_uint32_t)addr, size) + mmu_clean_invalidated_dcache((rt_uint32_t)addr, size) /* EMAC has BD's in cached memory - so need cache functions */ #define BD_CACHE_INVALIDATE(addr, size) @@ -50,7 +36,7 @@ extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); /* EMAC internal utility function */ rt_inline unsigned long emac_virt_to_phys(unsigned long addr) { - return addr; + return addr; } @@ -59,112 +45,112 @@ rt_inline unsigned long emac_virt_to_phys(unsigned long addr) #define MACB_TX_SRAM #if defined(MACB_TX_SRAM) -#define MACB_TX_RING_SIZE 2 -#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE) -#define TX_RING_BYTES (sizeof(struct macb_dma_desc) * MACB_TX_RING_SIZE) +#define MACB_TX_RING_SIZE 2 +#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE) +#define TX_RING_BYTES (sizeof(struct macb_dma_desc) * MACB_TX_RING_SIZE) #else -#define MACB_TX_RING_SIZE 16 -#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE) +#define MACB_TX_RING_SIZE 16 +#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE) #endif -#define MACB_RX_BUFFER_SIZE (4096*4) -#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128) +#define MACB_RX_BUFFER_SIZE (4096*4) +#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128) -#define DEF_TX_RING_PENDING (MACB_TX_RING_SIZE) +#define DEF_TX_RING_PENDING (MACB_TX_RING_SIZE) -#define TX_RING_GAP(macb) \ - (MACB_TX_RING_SIZE - (macb)->tx_pending) +#define TX_RING_GAP(macb) \ + (MACB_TX_RING_SIZE - (macb)->tx_pending) -#define TX_BUFFS_AVAIL(macb) \ - (((macb)->tx_tail <= (macb)->tx_head) ? \ - (macb)->tx_tail + (macb)->tx_pending - (macb)->tx_head : \ - (macb)->tx_tail - (macb)->tx_head - TX_RING_GAP(macb)) +#define TX_BUFFS_AVAIL(macb) \ + (((macb)->tx_tail <= (macb)->tx_head) ? \ + (macb)->tx_tail + (macb)->tx_pending - (macb)->tx_head : \ + (macb)->tx_tail - (macb)->tx_head - TX_RING_GAP(macb)) -#define NEXT_TX(n) (((n) + 1) & (MACB_TX_RING_SIZE - 1)) +#define NEXT_TX(n) (((n) + 1) & (MACB_TX_RING_SIZE - 1)) -#define NEXT_RX(n) (((n) + 1) & (MACB_RX_RING_SIZE - 1)) +#define NEXT_RX(n) (((n) + 1) & (MACB_RX_RING_SIZE - 1)) /* minimum number of free TX descriptors before waking up TX process */ -#define MACB_TX_WAKEUP_THRESH (MACB_TX_RING_SIZE / 4) +#define MACB_TX_WAKEUP_THRESH (MACB_TX_RING_SIZE / 4) -#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \ - | MACB_BIT(ISR_ROVR)) +#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \ + | MACB_BIT(ISR_ROVR)) -#define MACB_TX_TIMEOUT 1000 -#define MACB_AUTONEG_TIMEOUT 5000000 -#define MACB_LINK_TIMEOUT 500000 +#define MACB_TX_TIMEOUT 1000 +#define MACB_AUTONEG_TIMEOUT 5000000 +#define MACB_LINK_TIMEOUT 500000 #define CONFIG_RMII struct macb_dma_desc { - rt_uint32_t addr; - rt_uint32_t ctrl; + rt_uint32_t addr; + rt_uint32_t ctrl; }; -#define RXADDR_USED 0x00000001 -#define RXADDR_WRAP 0x00000002 +#define RXADDR_USED 0x00000001 +#define RXADDR_WRAP 0x00000002 -#define RXBUF_FRMLEN_MASK 0x00000fff -#define RXBUF_FRAME_START 0x00004000 -#define RXBUF_FRAME_END 0x00008000 -#define RXBUF_TYPEID_MATCH 0x00400000 -#define RXBUF_ADDR4_MATCH 0x00800000 -#define RXBUF_ADDR3_MATCH 0x01000000 -#define RXBUF_ADDR2_MATCH 0x02000000 -#define RXBUF_ADDR1_MATCH 0x04000000 -#define RXBUF_BROADCAST 0x80000000 +#define RXBUF_FRMLEN_MASK 0x00000fff +#define RXBUF_FRAME_START 0x00004000 +#define RXBUF_FRAME_END 0x00008000 +#define RXBUF_TYPEID_MATCH 0x00400000 +#define RXBUF_ADDR4_MATCH 0x00800000 +#define RXBUF_ADDR3_MATCH 0x01000000 +#define RXBUF_ADDR2_MATCH 0x02000000 +#define RXBUF_ADDR1_MATCH 0x04000000 +#define RXBUF_BROADCAST 0x80000000 -#define TXBUF_FRMLEN_MASK 0x000007ff -#define TXBUF_FRAME_END 0x00008000 -#define TXBUF_NOCRC 0x00010000 -#define TXBUF_EXHAUSTED 0x08000000 -#define TXBUF_UNDERRUN 0x10000000 -#define TXBUF_MAXRETRY 0x20000000 -#define TXBUF_WRAP 0x40000000 -#define TXBUF_USED 0x80000000 +#define TXBUF_FRMLEN_MASK 0x000007ff +#define TXBUF_FRAME_END 0x00008000 +#define TXBUF_NOCRC 0x00010000 +#define TXBUF_EXHAUSTED 0x08000000 +#define TXBUF_UNDERRUN 0x10000000 +#define TXBUF_MAXRETRY 0x20000000 +#define TXBUF_WRAP 0x40000000 +#define TXBUF_USED 0x80000000 /* Duplex, half or full. */ -#define DUPLEX_HALF 0x00 -#define DUPLEX_FULL 0x01 +#define DUPLEX_HALF 0x00 +#define DUPLEX_FULL 0x01 #define MAX_ADDR_LEN 6 struct rt_macb_eth { - /* inherit from ethernet device */ - struct eth_device parent; + /* inherit from ethernet device */ + struct eth_device parent; - unsigned int regs; + unsigned int regs; - unsigned int rx_tail; - unsigned int tx_head; - unsigned int tx_tail; - unsigned int rx_pending; - unsigned int tx_pending; + unsigned int rx_tail; + unsigned int tx_head; + unsigned int tx_tail; + unsigned int rx_pending; + unsigned int tx_pending; - void *rx_buffer; - void *tx_buffer; - struct macb_dma_desc *rx_ring; - struct macb_dma_desc *tx_ring; + void *rx_buffer; + void *tx_buffer; + struct macb_dma_desc *rx_ring; + struct macb_dma_desc *tx_ring; - unsigned long rx_buffer_dma; - unsigned long tx_buffer_dma; - unsigned long rx_ring_dma; - unsigned long tx_ring_dma; + unsigned long rx_buffer_dma; + unsigned long tx_buffer_dma; + unsigned long rx_ring_dma; + unsigned long tx_ring_dma; - unsigned int tx_stop; + unsigned int tx_stop; - /* interface address info. */ - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ - unsigned short phy_addr; + /* interface address info. */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ + unsigned short phy_addr; - struct rt_semaphore mdio_bus_lock; - struct rt_semaphore tx_lock; - struct rt_semaphore rx_lock; - struct rt_semaphore tx_ack; - rt_uint32_t speed; - rt_uint32_t duplex; - rt_uint32_t link; - struct rt_timer timer; + struct rt_semaphore mdio_bus_lock; + struct rt_semaphore tx_lock; + struct rt_semaphore rx_lock; + struct rt_semaphore tx_ack; + rt_uint32_t speed; + rt_uint32_t duplex; + rt_uint32_t link; + struct rt_timer timer; }; static struct rt_macb_eth macb_device; @@ -179,253 +165,253 @@ static void udelay(rt_uint32_t us) static void rt_macb_isr(int irq, void *param) { - struct rt_macb_eth *macb = (struct rt_macb_eth *)param; - rt_device_t dev = &(macb->parent.parent); - rt_uint32_t status, rsr, tsr; + struct rt_macb_eth *macb = (struct rt_macb_eth *)param; + rt_device_t dev = &(macb->parent.parent); + rt_uint32_t status, rsr, tsr; - status = macb_readl(macb, ISR); + status = macb_readl(macb, ISR); - while (status) { + while (status) { - if (status & MACB_RX_INT_FLAGS) - { - rsr = macb_readl(macb, RSR); - macb_writel(macb, RSR, rsr); - /* a frame has been received */ - eth_device_ready(&(macb_device.parent)); - - } + if (status & MACB_RX_INT_FLAGS) + { + rsr = macb_readl(macb, RSR); + macb_writel(macb, RSR, rsr); + /* a frame has been received */ + eth_device_ready(&(macb_device.parent)); - if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) | - MACB_BIT(ISR_RLE))) - { - macb_tx(macb); - } + } - /* - * Link change detection isn't possible with RMII, so we'll - * add that if/when we get our hands on a full-blown MII PHY. - */ + if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) | + MACB_BIT(ISR_RLE))) + { + macb_tx(macb); + } - if (status & MACB_BIT(HRESP)) - { - /* - * TODO: Reset the hardware, and maybe move the printk - * to a lower-priority context as well (work queue?) - */ - rt_kprintf("%s: DMA bus error: HRESP not OK\n", - dev->parent.name); - } + /* + * Link change detection isn't possible with RMII, so we'll + * add that if/when we get our hands on a full-blown MII PHY. + */ - status = macb_readl(macb, ISR); - } + if (status & MACB_BIT(HRESP)) + { + /* + * TODO: Reset the hardware, and maybe move the printk + * to a lower-priority context as well (work queue?) + */ + rt_kprintf("%s: DMA bus error: HRESP not OK\n", + dev->parent.name); + } + + status = macb_readl(macb, ISR); + } } static int macb_mdio_write(struct rt_macb_eth *macb, rt_uint8_t reg, rt_uint16_t value) { - unsigned long netctl; - unsigned long netstat; - unsigned long frame; + unsigned long netctl; + unsigned long netstat; + unsigned long frame; - rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER); - netctl = macb_readl(macb, NCR); - netctl |= MACB_BIT(MPE); - macb_writel(macb, NCR, netctl); + rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER); + netctl = macb_readl(macb, NCR); + netctl |= MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); - frame = (MACB_BF(SOF, 1) - | MACB_BF(RW, 1) - | MACB_BF(PHYA, macb->phy_addr) - | MACB_BF(REGA, reg) - | MACB_BF(CODE, 2) - | MACB_BF(DATA, value)); - macb_writel(macb, MAN, frame); + frame = (MACB_BF(SOF, 1) + | MACB_BF(RW, 1) + | MACB_BF(PHYA, macb->phy_addr) + | MACB_BF(REGA, reg) + | MACB_BF(CODE, 2) + | MACB_BF(DATA, value)); + macb_writel(macb, MAN, frame); - do { - netstat = macb_readl(macb, NSR); - } while (!(netstat & MACB_BIT(IDLE))); + do { + netstat = macb_readl(macb, NSR); + } while (!(netstat & MACB_BIT(IDLE))); - netctl = macb_readl(macb, NCR); - netctl &= ~MACB_BIT(MPE); - macb_writel(macb, NCR, netctl); - rt_sem_release(&macb->mdio_bus_lock); + netctl = macb_readl(macb, NCR); + netctl &= ~MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); + rt_sem_release(&macb->mdio_bus_lock); } static int macb_mdio_read(struct rt_macb_eth *macb, rt_uint8_t reg) { - unsigned long netctl; - unsigned long netstat; - unsigned long frame; + unsigned long netctl; + unsigned long netstat; + unsigned long frame; - rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER); - netctl = macb_readl(macb, NCR); - netctl |= MACB_BIT(MPE); - macb_writel(macb, NCR, netctl); + rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER); + netctl = macb_readl(macb, NCR); + netctl |= MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); - frame = (MACB_BF(SOF, 1) - | MACB_BF(RW, 2) - | MACB_BF(PHYA, macb->phy_addr) - | MACB_BF(REGA, reg) - | MACB_BF(CODE, 2)); - macb_writel(macb, MAN, frame); + frame = (MACB_BF(SOF, 1) + | MACB_BF(RW, 2) + | MACB_BF(PHYA, macb->phy_addr) + | MACB_BF(REGA, reg) + | MACB_BF(CODE, 2)); + macb_writel(macb, MAN, frame); - do { - netstat = macb_readl(macb, NSR); - } while (!(netstat & MACB_BIT(IDLE))); + do { + netstat = macb_readl(macb, NSR); + } while (!(netstat & MACB_BIT(IDLE))); - frame = macb_readl(macb, MAN); + frame = macb_readl(macb, MAN); - netctl = macb_readl(macb, NCR); - netctl &= ~MACB_BIT(MPE); - macb_writel(macb, NCR, netctl); - rt_sem_release(&macb->mdio_bus_lock); + netctl = macb_readl(macb, NCR); + netctl &= ~MACB_BIT(MPE); + macb_writel(macb, NCR, netctl); + rt_sem_release(&macb->mdio_bus_lock); - return MACB_BFEXT(DATA, frame); + return MACB_BFEXT(DATA, frame); } static void macb_phy_reset(rt_device_t dev) { - int i; - rt_uint16_t status, adv; - struct rt_macb_eth *macb = dev->user_data;; + int i; + rt_uint16_t status, adv; + struct rt_macb_eth *macb = dev->user_data;; - adv = ADVERTISE_CSMA | ADVERTISE_ALL; - macb_mdio_write(macb, MII_ADVERTISE, adv); - rt_kprintf("%s: Starting autonegotiation...\n", dev->parent.name); - macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE - | BMCR_ANRESTART)); + adv = ADVERTISE_CSMA | ADVERTISE_ALL; + macb_mdio_write(macb, MII_ADVERTISE, adv); + rt_kprintf("%s: Starting autonegotiation...\n", dev->parent.name); + macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE + | BMCR_ANRESTART)); - for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) - { - status = macb_mdio_read(macb, MII_BMSR); - if (status & BMSR_ANEGCOMPLETE) - break; - udelay(100); - } + for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) + { + status = macb_mdio_read(macb, MII_BMSR); + if (status & BMSR_ANEGCOMPLETE) + break; + udelay(100); + } - if (status & BMSR_ANEGCOMPLETE) - rt_kprintf("%s: Autonegotiation complete\n", dev->parent.name); - else - rt_kprintf("%s: Autonegotiation timed out (status=0x%04x)\n", - dev->parent.name, status); + if (status & BMSR_ANEGCOMPLETE) + rt_kprintf("%s: Autonegotiation complete\n", dev->parent.name); + else + rt_kprintf("%s: Autonegotiation timed out (status=0x%04x)\n", + dev->parent.name, status); } static int macb_phy_init(rt_device_t dev) { - struct rt_macb_eth *macb = dev->user_data; - rt_uint32_t ncfgr; - rt_uint16_t phy_id, status, adv, lpa; - int media, speed, duplex; - int i; + struct rt_macb_eth *macb = dev->user_data; + rt_uint32_t ncfgr; + rt_uint16_t phy_id, status, adv, lpa; + int media, speed, duplex; + int i; - /* Check if the PHY is up to snuff... */ - phy_id = macb_mdio_read(macb, MII_PHYSID1); - if (phy_id == 0xffff) - { - rt_kprintf("%s: No PHY present\n", dev->parent.name); - return 0; - } + /* Check if the PHY is up to snuff... */ + phy_id = macb_mdio_read(macb, MII_PHYSID1); + if (phy_id == 0xffff) + { + rt_kprintf("%s: No PHY present\n", dev->parent.name); + return 0; + } - status = macb_mdio_read(macb, MII_BMSR); - if (!(status & BMSR_LSTATUS)) - { - /* Try to re-negotiate if we don't have link already. */ - macb_phy_reset(dev); + status = macb_mdio_read(macb, MII_BMSR); + if (!(status & BMSR_LSTATUS)) + { + /* Try to re-negotiate if we don't have link already. */ + macb_phy_reset(dev); - for (i = 0; i < MACB_LINK_TIMEOUT / 100; i++) - { - status = macb_mdio_read(macb, MII_BMSR); - if (status & BMSR_LSTATUS) - break; - udelay(100); - } - } + for (i = 0; i < MACB_LINK_TIMEOUT / 100; i++) + { + status = macb_mdio_read(macb, MII_BMSR); + if (status & BMSR_LSTATUS) + break; + udelay(100); + } + } - if (!(status & BMSR_LSTATUS)) - { - rt_kprintf("%s: link down (status: 0x%04x)\n", - dev->parent.name, status); - return 0; - } - else - { - adv = macb_mdio_read(macb, MII_ADVERTISE); - lpa = macb_mdio_read(macb, MII_LPA); - media = mii_nway_result(lpa & adv); - speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) - ? 1 : 0); - duplex = (media & ADVERTISE_FULL) ? 1 : 0; - rt_kprintf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", - dev->parent.name, - speed ? "100" : "10", - duplex ? "full" : "half", - lpa); + if (!(status & BMSR_LSTATUS)) + { + rt_kprintf("%s: link down (status: 0x%04x)\n", + dev->parent.name, status); + return 0; + } + else + { + adv = macb_mdio_read(macb, MII_ADVERTISE); + lpa = macb_mdio_read(macb, MII_LPA); + media = mii_nway_result(lpa & adv); + speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) + ? 1 : 0); + duplex = (media & ADVERTISE_FULL) ? 1 : 0; + rt_kprintf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", + dev->parent.name, + speed ? "100" : "10", + duplex ? "full" : "half", + lpa); - ncfgr = macb_readl(macb, NCFGR); - ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); - if (speed) - ncfgr |= MACB_BIT(SPD); - if (duplex) - ncfgr |= MACB_BIT(FD); - macb_writel(macb, NCFGR, ncfgr); - return 1; - } + ncfgr = macb_readl(macb, NCFGR); + ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); + if (speed) + ncfgr |= MACB_BIT(SPD); + if (duplex) + ncfgr |= MACB_BIT(FD); + macb_writel(macb, NCFGR, ncfgr); + return 1; + } } void macb_update_link(void *param) { - struct rt_macb_eth *macb = (struct rt_macb_eth *)param; - rt_device_t dev = &macb->parent.parent; - int status, status_change = 0; - rt_uint32_t link; - rt_uint32_t media; - rt_uint16_t adv, lpa; + struct rt_macb_eth *macb = (struct rt_macb_eth *)param; + rt_device_t dev = &macb->parent.parent; + int status, status_change = 0; + rt_uint32_t link; + rt_uint32_t media; + rt_uint16_t adv, lpa; - /* Do a fake read */ - status = macb_mdio_read(macb, MII_BMSR); - if (status < 0) - return; + /* Do a fake read */ + status = macb_mdio_read(macb, MII_BMSR); + if (status < 0) + return; - /* Read link and autonegotiation status */ - status = macb_mdio_read(macb, MII_BMSR); - if (status < 0) - return; - - if ((status & BMSR_LSTATUS) == 0) - link = 0; - else - link = 1; + /* Read link and autonegotiation status */ + status = macb_mdio_read(macb, MII_BMSR); + if (status < 0) + return; - if (link != macb->link) - { - macb->link = link; - status_change = 1; - } + if ((status & BMSR_LSTATUS) == 0) + link = 0; + else + link = 1; - if (status_change) - { - if (macb->link) - { - adv = macb_mdio_read(macb, MII_ADVERTISE); - lpa = macb_mdio_read(macb, MII_LPA); - media = mii_nway_result(lpa & adv); - macb->speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) - ? 100 : 10); - macb->duplex = (media & ADVERTISE_FULL) ? 1 : 0; - rt_kprintf("%s: link up (%dMbps/%s-duplex)\n", - dev->parent.name, macb->speed, - DUPLEX_FULL == macb->duplex ? "Full":"Half"); - eth_device_linkchange(&macb->parent, RT_TRUE); - } - else - { - rt_kprintf("%s: link down\n", dev->parent.name); - eth_device_linkchange(&macb->parent, RT_FALSE); - } + if (link != macb->link) + { + macb->link = link; + status_change = 1; + } - } + if (status_change) + { + if (macb->link) + { + adv = macb_mdio_read(macb, MII_ADVERTISE); + lpa = macb_mdio_read(macb, MII_LPA); + media = mii_nway_result(lpa & adv); + macb->speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) + ? 100 : 10); + macb->duplex = (media & ADVERTISE_FULL) ? 1 : 0; + rt_kprintf("%s: link up (%dMbps/%s-duplex)\n", + dev->parent.name, macb->speed, + DUPLEX_FULL == macb->duplex ? "Full":"Half"); + eth_device_linkchange(&macb->parent, RT_TRUE); + } + else + { + rt_kprintf("%s: link down\n", dev->parent.name); + eth_device_linkchange(&macb->parent, RT_FALSE); + } + + } } @@ -434,190 +420,190 @@ void macb_update_link(void *param) static rt_err_t rt_macb_init(rt_device_t dev) { - struct rt_macb_eth *macb = dev->user_data; - unsigned long paddr; - rt_uint32_t hwaddr_bottom; - rt_uint16_t hwaddr_top; - int i; + struct rt_macb_eth *macb = dev->user_data; + unsigned long paddr; + rt_uint32_t hwaddr_bottom; + rt_uint16_t hwaddr_top; + int i; - /* - * macb_halt should have been called at some point before now, - * so we'll assume the controller is idle. - */ + /* + * macb_halt should have been called at some point before now, + * so we'll assume the controller is idle. + */ - /* initialize DMA descriptors */ - paddr = macb->rx_buffer_dma; - for (i = 0; i < MACB_RX_RING_SIZE; i++) - { - if (i == (MACB_RX_RING_SIZE - 1)) - paddr |= RXADDR_WRAP; - macb->rx_ring[i].addr = paddr; - macb->rx_ring[i].ctrl = 0; - paddr += 128; - } - paddr = macb->tx_buffer_dma; - for (i = 0; i < MACB_TX_RING_SIZE; i++) - { - macb->tx_ring[i].addr = paddr; - if (i == (MACB_TX_RING_SIZE - 1)) - macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP; - else - macb->tx_ring[i].ctrl = TXBUF_USED; - paddr += 1536; - } - macb->rx_tail = macb->tx_head = macb->tx_tail = 0; + /* initialize DMA descriptors */ + paddr = macb->rx_buffer_dma; + for (i = 0; i < MACB_RX_RING_SIZE; i++) + { + if (i == (MACB_RX_RING_SIZE - 1)) + paddr |= RXADDR_WRAP; + macb->rx_ring[i].addr = paddr; + macb->rx_ring[i].ctrl = 0; + paddr += 128; + } + paddr = macb->tx_buffer_dma; + for (i = 0; i < MACB_TX_RING_SIZE; i++) + { + macb->tx_ring[i].addr = paddr; + if (i == (MACB_TX_RING_SIZE - 1)) + macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP; + else + macb->tx_ring[i].ctrl = TXBUF_USED; + paddr += 1536; + } + macb->rx_tail = macb->tx_head = macb->tx_tail = 0; - BD_CACHE_WRITEBACK_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); - BD_CACHE_WRITEBACK_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc)); - macb_writel(macb, RBQP, macb->rx_ring_dma); - macb_writel(macb, TBQP, macb->tx_ring_dma); - - /* set hardware address */ - hwaddr_bottom = (*((rt_uint32_t *)macb->dev_addr)); - macb_writel(macb, SA1B, hwaddr_bottom); - hwaddr_top = (*((rt_uint16_t *)(macb->dev_addr + 4))); - macb_writel(macb, SA1T, hwaddr_top); + BD_CACHE_WRITEBACK_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); + BD_CACHE_WRITEBACK_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc)); + macb_writel(macb, RBQP, macb->rx_ring_dma); + macb_writel(macb, TBQP, macb->tx_ring_dma); - - /* choose RMII or MII mode. This depends on the board */ + /* set hardware address */ + hwaddr_bottom = (*((rt_uint32_t *)macb->dev_addr)); + macb_writel(macb, SA1B, hwaddr_bottom); + hwaddr_top = (*((rt_uint16_t *)(macb->dev_addr + 4))); + macb_writel(macb, SA1T, hwaddr_top); + + + /* choose RMII or MII mode. This depends on the board */ #ifdef CONFIG_RMII - macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); + macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); #else - macb_writel(macb, USRIO, MACB_BIT(CLKEN)); + macb_writel(macb, USRIO, MACB_BIT(CLKEN)); #endif /* CONFIG_RMII */ - if (!macb_phy_init(dev)) - return -RT_ERROR; + if (!macb_phy_init(dev)) + return -RT_ERROR; - /* Enable TX and RX */ - macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(MPE)); - - /* Enable interrupts */ - macb_writel(macb, IER, (MACB_BIT(RCOMP) - | MACB_BIT(RXUBR) - | MACB_BIT(ISR_TUND) - | MACB_BIT(ISR_RLE) - | MACB_BIT(TXERR) - | MACB_BIT(TCOMP) - | MACB_BIT(ISR_ROVR) - | MACB_BIT(HRESP))); - - /* instal interrupt */ - rt_hw_interrupt_install(AT91SAM9260_ID_EMAC, rt_macb_isr, - (void *)macb, "emac"); - rt_hw_interrupt_umask(AT91SAM9260_ID_EMAC); + /* Enable TX and RX */ + macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(MPE)); - rt_timer_init(&macb->timer, "link_timer", - macb_update_link, - (void *)macb, - RT_TICK_PER_SECOND, - RT_TIMER_FLAG_PERIODIC); + /* Enable interrupts */ + macb_writel(macb, IER, (MACB_BIT(RCOMP) + | MACB_BIT(RXUBR) + | MACB_BIT(ISR_TUND) + | MACB_BIT(ISR_RLE) + | MACB_BIT(TXERR) + | MACB_BIT(TCOMP) + | MACB_BIT(ISR_ROVR) + | MACB_BIT(HRESP))); - rt_timer_start(&macb->timer); - - return RT_EOK; + /* instal interrupt */ + rt_hw_interrupt_install(AT91SAM9260_ID_EMAC, rt_macb_isr, + (void *)macb, "emac"); + rt_hw_interrupt_umask(AT91SAM9260_ID_EMAC); + + rt_timer_init(&macb->timer, "link_timer", + macb_update_link, + (void *)macb, + RT_TICK_PER_SECOND, + RT_TIMER_FLAG_PERIODIC); + + rt_timer_start(&macb->timer); + + return RT_EOK; } static rt_err_t rt_macb_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } static rt_err_t rt_macb_close(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_size_t rt_macb_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_size_t rt_macb_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_err_t rt_macb_control(rt_device_t dev, int cmd, void *args) { - switch(cmd) - { - case NIOCTL_GADDR: - /* get mac address */ - if(args) rt_memcpy(args, macb_device.dev_addr, 6); - else return -RT_ERROR; - break; + switch(cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if(args) rt_memcpy(args, macb_device.dev_addr, 6); + else return -RT_ERROR; + break; - default : - break; - } + default : + break; + } - return RT_EOK; + return RT_EOK; } static void macb_tx(struct rt_macb_eth *macb) { - unsigned int tail; - unsigned int head; - rt_uint32_t status; + unsigned int tail; + unsigned int head; + rt_uint32_t status; - status = macb_readl(macb, TSR); - macb_writel(macb, TSR, status); + status = macb_readl(macb, TSR); + macb_writel(macb, TSR, status); - /*rt_kprintf("macb_tx status = %02lx\n", - (unsigned long)status);*/ + /*rt_kprintf("macb_tx status = %02lx\n", + (unsigned long)status);*/ - if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) - { - int i; - rt_kprintf("%s: TX %s, resetting buffers\n", - macb->parent.parent.parent.name, status & MACB_BIT(UND) ? - "underrun" : "retry limit exceeded"); + if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) + { + int i; + rt_kprintf("%s: TX %s, resetting buffers\n", + macb->parent.parent.parent.name, status & MACB_BIT(UND) ? + "underrun" : "retry limit exceeded"); - /* Transfer ongoing, disable transmitter, to avoid confusion */ - if (status & MACB_BIT(TGO)) - macb_writel(macb, NCR, macb_readl(macb, NCR) & ~MACB_BIT(TE)); + /* Transfer ongoing, disable transmitter, to avoid confusion */ + if (status & MACB_BIT(TGO)) + macb_writel(macb, NCR, macb_readl(macb, NCR) & ~MACB_BIT(TE)); - head = macb->tx_head; + head = macb->tx_head; - /*Mark all the buffer as used to avoid sending a lost buffer*/ - for (i = 0; i < MACB_TX_RING_SIZE; i++) - macb->tx_ring[i].ctrl = MACB_BIT(TX_USED); + /*Mark all the buffer as used to avoid sending a lost buffer*/ + for (i = 0; i < MACB_TX_RING_SIZE; i++) + macb->tx_ring[i].ctrl = MACB_BIT(TX_USED); - /* free transmit buffer in upper layer*/ + /* free transmit buffer in upper layer*/ - macb->tx_head = macb->tx_tail = 0; + macb->tx_head = macb->tx_tail = 0; - /* Enable the transmitter again */ - if (status & MACB_BIT(TGO)) - macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TE)); - } + /* Enable the transmitter again */ + if (status & MACB_BIT(TGO)) + macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TE)); + } - if (!(status & MACB_BIT(COMP))) - /* - * This may happen when a buffer becomes complete - * between reading the ISR and scanning the - * descriptors. Nothing to worry about. - */ - return; + if (!(status & MACB_BIT(COMP))) + /* + * This may happen when a buffer becomes complete + * between reading the ISR and scanning the + * descriptors. Nothing to worry about. + */ + return; - head = macb->tx_head; - for (tail = macb->tx_tail; tail != head; tail = NEXT_TX(tail)) - { - rt_uint32_t bufstat; + head = macb->tx_head; + for (tail = macb->tx_tail; tail != head; tail = NEXT_TX(tail)) + { + rt_uint32_t bufstat; - bufstat = macb->tx_ring[tail].ctrl; + bufstat = macb->tx_ring[tail].ctrl; - if (!(bufstat & MACB_BIT(TX_USED))) - break; - } + if (!(bufstat & MACB_BIT(TX_USED))) + break; + } - macb->tx_tail = tail; - if ((macb->tx_stop == 1) && - TX_BUFFS_AVAIL(macb) > MACB_TX_WAKEUP_THRESH) - rt_sem_release(&macb->tx_ack); + macb->tx_tail = tail; + if ((macb->tx_stop == 1) && + TX_BUFFS_AVAIL(macb) > MACB_TX_WAKEUP_THRESH) + rt_sem_release(&macb->tx_ack); } @@ -625,286 +611,286 @@ static void macb_tx(struct rt_macb_eth *macb) /* transmit packet. */ rt_err_t rt_macb_tx( rt_device_t dev, struct pbuf* p) { - unsigned long ctrl; - struct pbuf* q; - rt_uint8_t* bufptr; - rt_uint32_t mapping; - struct rt_macb_eth *macb = dev->user_data; - unsigned int tx_head = macb->tx_head; + unsigned long ctrl; + struct pbuf* q; + rt_uint8_t* bufptr; + rt_uint32_t mapping; + struct rt_macb_eth *macb = dev->user_data; + unsigned int tx_head = macb->tx_head; - rt_sem_take(&macb->tx_lock, RT_WAITING_FOREVER); - if (TX_BUFFS_AVAIL(macb) < 1) - { - rt_sem_release(&macb->tx_lock); - rt_kprintf("Tx Ring full!\n"); - rt_kprintf("tx_head = %u, tx_tail = %u\n", - macb->tx_head, macb->tx_tail); - return -RT_ERROR; - } + rt_sem_take(&macb->tx_lock, RT_WAITING_FOREVER); + if (TX_BUFFS_AVAIL(macb) < 1) + { + rt_sem_release(&macb->tx_lock); + rt_kprintf("Tx Ring full!\n"); + rt_kprintf("tx_head = %u, tx_tail = %u\n", + macb->tx_head, macb->tx_tail); + return -RT_ERROR; + } - macb->tx_stop = 0; + macb->tx_stop = 0; - ctrl = p->tot_len & TXBUF_FRMLEN_MASK; - ctrl |= TXBUF_FRAME_END; - if (tx_head == (MACB_TX_RING_SIZE - 1)) - { - ctrl |= TXBUF_WRAP; - } + ctrl = p->tot_len & TXBUF_FRMLEN_MASK; + ctrl |= TXBUF_FRAME_END; + if (tx_head == (MACB_TX_RING_SIZE - 1)) + { + ctrl |= TXBUF_WRAP; + } #if defined(MACB_TX_SRAM) - bufptr = macb->tx_buffer + tx_head * 1536; + bufptr = macb->tx_buffer + tx_head * 1536; #else - mapping = (unsigned long)macb->tx_buffer + tx_head * 1536; - bufptr = (rt_uint8_t *)mapping; + mapping = (unsigned long)macb->tx_buffer + tx_head * 1536; + bufptr = (rt_uint8_t *)mapping; #endif - for (q = p; q != NULL; q = q->next) - { - memcpy(bufptr, q->payload, q->len); - bufptr += q->len; - } + for (q = p; q != NULL; q = q->next) + { + memcpy(bufptr, q->payload, q->len); + bufptr += q->len; + } #if !defined(MACB_TX_SRAM) - EMAC_CACHE_WRITEBACK(mapping, p->tot_len); + EMAC_CACHE_WRITEBACK(mapping, p->tot_len); #endif - macb->tx_ring[tx_head].ctrl = ctrl; - BD_CACHE_WRITEBACK_INVALIDATE(&macb->tx_ring[tx_head], sizeof(struct macb_dma_desc)); - tx_head = NEXT_TX(tx_head); - macb->tx_head = tx_head; - macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART)); - macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART)); + macb->tx_ring[tx_head].ctrl = ctrl; + BD_CACHE_WRITEBACK_INVALIDATE(&macb->tx_ring[tx_head], sizeof(struct macb_dma_desc)); + tx_head = NEXT_TX(tx_head); + macb->tx_head = tx_head; + macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART)); + macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART)); - if (TX_BUFFS_AVAIL(macb) < 1) - { - macb->tx_stop = 1; - rt_sem_take(&macb->tx_ack, RT_WAITING_FOREVER); - } - rt_sem_release(&macb->tx_lock); + if (TX_BUFFS_AVAIL(macb) < 1) + { + macb->tx_stop = 1; + rt_sem_take(&macb->tx_ack, RT_WAITING_FOREVER); + } + rt_sem_release(&macb->tx_lock); - return RT_EOK; + return RT_EOK; } static void reclaim_rx_buffers(struct rt_macb_eth *macb, - unsigned int new_tail) + unsigned int new_tail) { - unsigned int i; + unsigned int i; - i = macb->rx_tail; - while (i > new_tail) - { - macb->rx_ring[i].addr &= ~RXADDR_USED; - i++; - if (i > MACB_RX_RING_SIZE) - i = 0; - } + i = macb->rx_tail; + while (i > new_tail) + { + macb->rx_ring[i].addr &= ~RXADDR_USED; + i++; + if (i > MACB_RX_RING_SIZE) + i = 0; + } - while (i < new_tail) - { - macb->rx_ring[i].addr &= ~RXADDR_USED; - i++; - } + while (i < new_tail) + { + macb->rx_ring[i].addr &= ~RXADDR_USED; + i++; + } - macb->rx_tail = new_tail; + macb->rx_tail = new_tail; } /* reception packet. */ struct pbuf *rt_macb_rx(rt_device_t dev) { - struct rt_macb_eth *macb = dev->user_data; - struct pbuf* p = RT_NULL; - rt_uint32_t len; - unsigned int rx_tail = macb->rx_tail; - void *buffer; - int wrapped = 0; - rt_uint32_t status; + struct rt_macb_eth *macb = dev->user_data; + struct pbuf* p = RT_NULL; + rt_uint32_t len; + unsigned int rx_tail = macb->rx_tail; + void *buffer; + int wrapped = 0; + rt_uint32_t status; - rt_sem_take(&macb->rx_lock, RT_WAITING_FOREVER); - for (;;) - { - if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED)) - break; + rt_sem_take(&macb->rx_lock, RT_WAITING_FOREVER); + for (;;) + { + if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED)) + break; - status = macb->rx_ring[rx_tail].ctrl; - if (status & RXBUF_FRAME_START) - { - if (rx_tail != macb->rx_tail) - reclaim_rx_buffers(macb, rx_tail); - wrapped = 0; - } + status = macb->rx_ring[rx_tail].ctrl; + if (status & RXBUF_FRAME_START) + { + if (rx_tail != macb->rx_tail) + reclaim_rx_buffers(macb, rx_tail); + wrapped = 0; + } - if (status & RXBUF_FRAME_END) - { - buffer = (void *)((unsigned int)macb->rx_buffer + 128 * macb->rx_tail); - len = status & RXBUF_FRMLEN_MASK; - p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM); - if (!p) - { - rt_kprintf("alloc pbuf failed\n"); - break; - } - if (wrapped) - { - unsigned int headlen, taillen; + if (status & RXBUF_FRAME_END) + { + buffer = (void *)((unsigned int)macb->rx_buffer + 128 * macb->rx_tail); + len = status & RXBUF_FRMLEN_MASK; + p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM); + if (!p) + { + rt_kprintf("alloc pbuf failed\n"); + break; + } + if (wrapped) + { + unsigned int headlen, taillen; - headlen = 128 * (MACB_RX_RING_SIZE - - macb->rx_tail); - taillen = len - headlen; - EMAC_CACHE_INVALIDATE(buffer, headlen); - EMAC_CACHE_INVALIDATE(macb->rx_buffer, taillen); - memcpy((void *)p->payload, buffer, headlen); - memcpy((void *)((unsigned int)p->payload + headlen), - macb->rx_buffer, taillen); - } - else - { - EMAC_CACHE_INVALIDATE(buffer, len); - memcpy((void *)p->payload, buffer, p->len); - } - - if (++rx_tail >= MACB_RX_RING_SIZE) - rx_tail = 0; - reclaim_rx_buffers(macb, rx_tail); - break; - } - else - { - if (++rx_tail >= MACB_RX_RING_SIZE) - { - wrapped = 1; - rx_tail = 0; - } - } - } + headlen = 128 * (MACB_RX_RING_SIZE + - macb->rx_tail); + taillen = len - headlen; + EMAC_CACHE_INVALIDATE(buffer, headlen); + EMAC_CACHE_INVALIDATE(macb->rx_buffer, taillen); + memcpy((void *)p->payload, buffer, headlen); + memcpy((void *)((unsigned int)p->payload + headlen), + macb->rx_buffer, taillen); + } + else + { + EMAC_CACHE_INVALIDATE(buffer, len); + memcpy((void *)p->payload, buffer, p->len); + } - rt_sem_release(&macb->rx_lock); + if (++rx_tail >= MACB_RX_RING_SIZE) + rx_tail = 0; + reclaim_rx_buffers(macb, rx_tail); + break; + } + else + { + if (++rx_tail >= MACB_RX_RING_SIZE) + { + wrapped = 1; + rx_tail = 0; + } + } + } - return p; + rt_sem_release(&macb->rx_lock); + + return p; } void macb_gpio_init() { - /* Pins used for MII and RMII */ - AT91C_BASE_PIOA->PIO_PDR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20); - AT91C_BASE_PIOA->PIO_ASR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20); + /* Pins used for MII and RMII */ + AT91C_BASE_PIOA->PIO_PDR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20); + AT91C_BASE_PIOA->PIO_ASR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20); #ifndef GONFIG_RMII - AT91C_BASE_PIOA->PIO_PDR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29); - AT91C_BASE_PIOA->PIO_ASR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29); + AT91C_BASE_PIOA->PIO_PDR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29); + AT91C_BASE_PIOA->PIO_ASR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29); #endif } rt_err_t macb_initialize() { - struct rt_macb_eth *macb = &macb_device; - unsigned long macb_hz; - rt_uint32_t ncfgr; - + struct rt_macb_eth *macb = &macb_device; + unsigned long macb_hz; + rt_uint32_t ncfgr; + #if defined(MACB_TX_SRAM) - macb->tx_ring_dma = AT91SAM9260_SRAM0_BASE; - macb->tx_ring = (struct macb_dma_desc *)AT91SAM9260_SRAM0_VIRT_BASE; - macb->tx_buffer = (char *) macb->tx_ring + TX_RING_BYTES; - macb->tx_buffer_dma = macb->tx_ring_dma + TX_RING_BYTES; + macb->tx_ring_dma = AT91SAM9260_SRAM0_BASE; + macb->tx_ring = (struct macb_dma_desc *)AT91SAM9260_SRAM0_VIRT_BASE; + macb->tx_buffer = (char *) macb->tx_ring + TX_RING_BYTES; + macb->tx_buffer_dma = macb->tx_ring_dma + TX_RING_BYTES; #else - macb->tx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); - if (macb->tx_ring == RT_NULL) - goto err1; - EMAC_CACHE_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc)); - macb->tx_ring_dma = emac_virt_to_phys((unsigned long)macb->tx_ring); - macb->tx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->tx_ring); - macb->tx_buffer = rt_malloc(MACB_TX_BUFFER_SIZE); - if (macb->tx_buffer == RT_NULL) - goto err2; - macb->tx_buffer_dma = emac_virt_to_phys((unsigned long)macb->tx_buffer); + macb->tx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); + if (macb->tx_ring == RT_NULL) + goto err1; + EMAC_CACHE_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc)); + macb->tx_ring_dma = emac_virt_to_phys((unsigned long)macb->tx_ring); + macb->tx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->tx_ring); + macb->tx_buffer = rt_malloc(MACB_TX_BUFFER_SIZE); + if (macb->tx_buffer == RT_NULL) + goto err2; + macb->tx_buffer_dma = emac_virt_to_phys((unsigned long)macb->tx_buffer); #endif - macb->rx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); - if (macb->rx_ring == RT_NULL) - goto err3; - EMAC_CACHE_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); - macb->rx_ring_dma = emac_virt_to_phys((unsigned long)macb->rx_ring); - macb->rx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->rx_ring); - macb->rx_buffer = rt_malloc(MACB_RX_BUFFER_SIZE); - if (macb->rx_buffer == RT_NULL) - goto err4; - macb->rx_buffer_dma = emac_virt_to_phys((unsigned long)macb->rx_buffer); + macb->rx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); + if (macb->rx_ring == RT_NULL) + goto err3; + EMAC_CACHE_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); + macb->rx_ring_dma = emac_virt_to_phys((unsigned long)macb->rx_ring); + macb->rx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->rx_ring); + macb->rx_buffer = rt_malloc(MACB_RX_BUFFER_SIZE); + if (macb->rx_buffer == RT_NULL) + goto err4; + macb->rx_buffer_dma = emac_virt_to_phys((unsigned long)macb->rx_buffer); - macb->tx_pending = DEF_TX_RING_PENDING; + macb->tx_pending = DEF_TX_RING_PENDING; - macb->regs = AT91SAM9260_BASE_EMAC; - macb->phy_addr = 0x00; - - /* - * Do some basic initialization so that we at least can talk - * to the PHY - */ - macb_hz = clk_get_rate(clk_get("mck")); - if (macb_hz < 20000000) - ncfgr = MACB_BF(CLK, MACB_CLK_DIV8); - else if (macb_hz < 40000000) - ncfgr = MACB_BF(CLK, MACB_CLK_DIV16); - else if (macb_hz < 80000000) - ncfgr = MACB_BF(CLK, MACB_CLK_DIV32); - else - ncfgr = MACB_BF(CLK, MACB_CLK_DIV64); + macb->regs = AT91SAM9260_BASE_EMAC; + macb->phy_addr = 0x00; - macb_writel(macb, NCFGR, ncfgr); + /* + * Do some basic initialization so that we at least can talk + * to the PHY + */ + macb_hz = clk_get_rate(clk_get("mck")); + if (macb_hz < 20000000) + ncfgr = MACB_BF(CLK, MACB_CLK_DIV8); + else if (macb_hz < 40000000) + ncfgr = MACB_BF(CLK, MACB_CLK_DIV16); + else if (macb_hz < 80000000) + ncfgr = MACB_BF(CLK, MACB_CLK_DIV32); + else + ncfgr = MACB_BF(CLK, MACB_CLK_DIV64); - macb->link = 0; + macb_writel(macb, NCFGR, ncfgr); - return RT_EOK; + macb->link = 0; + + return RT_EOK; err4: - rt_free(macb->rx_ring); - macb->rx_ring = RT_NULL; + rt_free(macb->rx_ring); + macb->rx_ring = RT_NULL; err3: #if !defined(MACB_TX_SRAM) - rt_free(macb->tx_buffer); - macb->tx_buffer = RT_NULL; + rt_free(macb->tx_buffer); + macb->tx_buffer = RT_NULL; err2: - rt_free(macb->tx_ring); - macb->tx_ring = RT_NULL; + rt_free(macb->tx_ring); + macb->tx_ring = RT_NULL; err1: #endif - return -RT_ENOMEM; + return -RT_ENOMEM; } int rt_hw_macb_init(void) { - rt_err_t ret; - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC; //enable macb clock - macb_gpio_init(); - rt_memset(&macb_device, 0, sizeof(macb_device)); - ret = macb_initialize(); - if (ret != RT_EOK) - { - rt_kprintf("AT91 EMAC initialized failed\n"); - return -1; - } - rt_sem_init(&macb_device.tx_ack, "tx_ack", 0, RT_IPC_FLAG_FIFO); - rt_sem_init(&macb_device.tx_lock, "tx_lock", 1, RT_IPC_FLAG_FIFO); - rt_sem_init(&macb_device.rx_lock, "rx_lock", 1, RT_IPC_FLAG_FIFO); + rt_err_t ret; + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC; //enable macb clock + macb_gpio_init(); + rt_memset(&macb_device, 0, sizeof(macb_device)); + ret = macb_initialize(); + if (ret != RT_EOK) + { + rt_kprintf("AT91 EMAC initialized failed\n"); + return -1; + } + rt_sem_init(&macb_device.tx_ack, "tx_ack", 0, RT_IPC_FLAG_FIFO); + rt_sem_init(&macb_device.tx_lock, "tx_lock", 1, RT_IPC_FLAG_FIFO); + rt_sem_init(&macb_device.rx_lock, "rx_lock", 1, RT_IPC_FLAG_FIFO); - macb_device.dev_addr[0] = 0x00; - macb_device.dev_addr[1] = 0x60; - macb_device.dev_addr[2] = 0x6E; - macb_device.dev_addr[3] = 0x11; - macb_device.dev_addr[4] = 0x22; - macb_device.dev_addr[5] = 0x33; - - macb_device.parent.parent.init = rt_macb_init; - macb_device.parent.parent.open = rt_macb_open; - macb_device.parent.parent.close = rt_macb_close; - macb_device.parent.parent.read = rt_macb_read; - macb_device.parent.parent.write = rt_macb_write; - macb_device.parent.parent.control = rt_macb_control; - macb_device.parent.parent.user_data = &macb_device; + macb_device.dev_addr[0] = 0x00; + macb_device.dev_addr[1] = 0x60; + macb_device.dev_addr[2] = 0x6E; + macb_device.dev_addr[3] = 0x11; + macb_device.dev_addr[4] = 0x22; + macb_device.dev_addr[5] = 0x33; - macb_device.parent.eth_rx = rt_macb_rx; - macb_device.parent.eth_tx = rt_macb_tx; + macb_device.parent.parent.init = rt_macb_init; + macb_device.parent.parent.open = rt_macb_open; + macb_device.parent.parent.close = rt_macb_close; + macb_device.parent.parent.read = rt_macb_read; + macb_device.parent.parent.write = rt_macb_write; + macb_device.parent.parent.control = rt_macb_control; + macb_device.parent.parent.user_data = &macb_device; - rt_sem_init(&macb_device.mdio_bus_lock, "mdio_bus_lock", 1, RT_IPC_FLAG_FIFO); + macb_device.parent.eth_rx = rt_macb_rx; + macb_device.parent.eth_tx = rt_macb_tx; - eth_device_init(&(macb_device.parent), "e0"); + rt_sem_init(&macb_device.mdio_bus_lock, "mdio_bus_lock", 1, RT_IPC_FLAG_FIFO); - return 0; + eth_device_init(&(macb_device.parent), "e0"); + + return 0; } INIT_DEVICE_EXPORT(rt_hw_macb_init); diff --git a/bsp/at91sam9g45/drivers/macb.h b/bsp/at91sam9g45/drivers/macb.h index 9df2883534..ed2ad390b7 100644 --- a/bsp/at91sam9g45/drivers/macb.h +++ b/bsp/at91sam9g45/drivers/macb.h @@ -1,21 +1,7 @@ /* - * File : macb.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -26,319 +12,319 @@ #include /* MACB register offsets */ -#define MACB_NCR 0x0000 -#define MACB_NCFGR 0x0004 -#define MACB_NSR 0x0008 -#define MACB_TSR 0x0014 -#define MACB_RBQP 0x0018 -#define MACB_TBQP 0x001c -#define MACB_RSR 0x0020 -#define MACB_ISR 0x0024 -#define MACB_IER 0x0028 -#define MACB_IDR 0x002c -#define MACB_IMR 0x0030 -#define MACB_MAN 0x0034 -#define MACB_PTR 0x0038 -#define MACB_PFR 0x003c -#define MACB_FTO 0x0040 -#define MACB_SCF 0x0044 -#define MACB_MCF 0x0048 -#define MACB_FRO 0x004c -#define MACB_FCSE 0x0050 -#define MACB_ALE 0x0054 -#define MACB_DTF 0x0058 -#define MACB_LCOL 0x005c -#define MACB_EXCOL 0x0060 -#define MACB_TUND 0x0064 -#define MACB_CSE 0x0068 -#define MACB_RRE 0x006c -#define MACB_ROVR 0x0070 -#define MACB_RSE 0x0074 -#define MACB_ELE 0x0078 -#define MACB_RJA 0x007c -#define MACB_USF 0x0080 -#define MACB_STE 0x0084 -#define MACB_RLE 0x0088 -#define MACB_TPF 0x008c -#define MACB_HRB 0x0090 -#define MACB_HRT 0x0094 -#define MACB_SA1B 0x0098 -#define MACB_SA1T 0x009c -#define MACB_SA2B 0x00a0 -#define MACB_SA2T 0x00a4 -#define MACB_SA3B 0x00a8 -#define MACB_SA3T 0x00ac -#define MACB_SA4B 0x00b0 -#define MACB_SA4T 0x00b4 -#define MACB_TID 0x00b8 -#define MACB_TPQ 0x00bc -#define MACB_USRIO 0x00c0 -#define MACB_WOL 0x00c4 +#define MACB_NCR 0x0000 +#define MACB_NCFGR 0x0004 +#define MACB_NSR 0x0008 +#define MACB_TSR 0x0014 +#define MACB_RBQP 0x0018 +#define MACB_TBQP 0x001c +#define MACB_RSR 0x0020 +#define MACB_ISR 0x0024 +#define MACB_IER 0x0028 +#define MACB_IDR 0x002c +#define MACB_IMR 0x0030 +#define MACB_MAN 0x0034 +#define MACB_PTR 0x0038 +#define MACB_PFR 0x003c +#define MACB_FTO 0x0040 +#define MACB_SCF 0x0044 +#define MACB_MCF 0x0048 +#define MACB_FRO 0x004c +#define MACB_FCSE 0x0050 +#define MACB_ALE 0x0054 +#define MACB_DTF 0x0058 +#define MACB_LCOL 0x005c +#define MACB_EXCOL 0x0060 +#define MACB_TUND 0x0064 +#define MACB_CSE 0x0068 +#define MACB_RRE 0x006c +#define MACB_ROVR 0x0070 +#define MACB_RSE 0x0074 +#define MACB_ELE 0x0078 +#define MACB_RJA 0x007c +#define MACB_USF 0x0080 +#define MACB_STE 0x0084 +#define MACB_RLE 0x0088 +#define MACB_TPF 0x008c +#define MACB_HRB 0x0090 +#define MACB_HRT 0x0094 +#define MACB_SA1B 0x0098 +#define MACB_SA1T 0x009c +#define MACB_SA2B 0x00a0 +#define MACB_SA2T 0x00a4 +#define MACB_SA3B 0x00a8 +#define MACB_SA3T 0x00ac +#define MACB_SA4B 0x00b0 +#define MACB_SA4T 0x00b4 +#define MACB_TID 0x00b8 +#define MACB_TPQ 0x00bc +#define MACB_USRIO 0x00c0 +#define MACB_WOL 0x00c4 /* Bitfields in NCR */ -#define MACB_LB_OFFSET 0 -#define MACB_LB_SIZE 1 -#define MACB_LLB_OFFSET 1 -#define MACB_LLB_SIZE 1 -#define MACB_RE_OFFSET 2 -#define MACB_RE_SIZE 1 -#define MACB_TE_OFFSET 3 -#define MACB_TE_SIZE 1 -#define MACB_MPE_OFFSET 4 -#define MACB_MPE_SIZE 1 -#define MACB_CLRSTAT_OFFSET 5 -#define MACB_CLRSTAT_SIZE 1 -#define MACB_INCSTAT_OFFSET 6 -#define MACB_INCSTAT_SIZE 1 -#define MACB_WESTAT_OFFSET 7 -#define MACB_WESTAT_SIZE 1 -#define MACB_BP_OFFSET 8 -#define MACB_BP_SIZE 1 -#define MACB_TSTART_OFFSET 9 -#define MACB_TSTART_SIZE 1 -#define MACB_THALT_OFFSET 10 -#define MACB_THALT_SIZE 1 -#define MACB_NCR_TPF_OFFSET 11 -#define MACB_NCR_TPF_SIZE 1 -#define MACB_TZQ_OFFSET 12 -#define MACB_TZQ_SIZE 1 +#define MACB_LB_OFFSET 0 +#define MACB_LB_SIZE 1 +#define MACB_LLB_OFFSET 1 +#define MACB_LLB_SIZE 1 +#define MACB_RE_OFFSET 2 +#define MACB_RE_SIZE 1 +#define MACB_TE_OFFSET 3 +#define MACB_TE_SIZE 1 +#define MACB_MPE_OFFSET 4 +#define MACB_MPE_SIZE 1 +#define MACB_CLRSTAT_OFFSET 5 +#define MACB_CLRSTAT_SIZE 1 +#define MACB_INCSTAT_OFFSET 6 +#define MACB_INCSTAT_SIZE 1 +#define MACB_WESTAT_OFFSET 7 +#define MACB_WESTAT_SIZE 1 +#define MACB_BP_OFFSET 8 +#define MACB_BP_SIZE 1 +#define MACB_TSTART_OFFSET 9 +#define MACB_TSTART_SIZE 1 +#define MACB_THALT_OFFSET 10 +#define MACB_THALT_SIZE 1 +#define MACB_NCR_TPF_OFFSET 11 +#define MACB_NCR_TPF_SIZE 1 +#define MACB_TZQ_OFFSET 12 +#define MACB_TZQ_SIZE 1 /* Bitfields in NCFGR */ -#define MACB_SPD_OFFSET 0 -#define MACB_SPD_SIZE 1 -#define MACB_FD_OFFSET 1 -#define MACB_FD_SIZE 1 -#define MACB_BIT_RATE_OFFSET 2 -#define MACB_BIT_RATE_SIZE 1 -#define MACB_JFRAME_OFFSET 3 -#define MACB_JFRAME_SIZE 1 -#define MACB_CAF_OFFSET 4 -#define MACB_CAF_SIZE 1 -#define MACB_NBC_OFFSET 5 -#define MACB_NBC_SIZE 1 -#define MACB_NCFGR_MTI_OFFSET 6 -#define MACB_NCFGR_MTI_SIZE 1 -#define MACB_UNI_OFFSET 7 -#define MACB_UNI_SIZE 1 -#define MACB_BIG_OFFSET 8 -#define MACB_BIG_SIZE 1 -#define MACB_EAE_OFFSET 9 -#define MACB_EAE_SIZE 1 -#define MACB_CLK_OFFSET 10 -#define MACB_CLK_SIZE 2 -#define MACB_RTY_OFFSET 12 -#define MACB_RTY_SIZE 1 -#define MACB_PAE_OFFSET 13 -#define MACB_PAE_SIZE 1 -#define MACB_RBOF_OFFSET 14 -#define MACB_RBOF_SIZE 2 -#define MACB_RLCE_OFFSET 16 -#define MACB_RLCE_SIZE 1 -#define MACB_DRFCS_OFFSET 17 -#define MACB_DRFCS_SIZE 1 -#define MACB_EFRHD_OFFSET 18 -#define MACB_EFRHD_SIZE 1 -#define MACB_IRXFCS_OFFSET 19 -#define MACB_IRXFCS_SIZE 1 +#define MACB_SPD_OFFSET 0 +#define MACB_SPD_SIZE 1 +#define MACB_FD_OFFSET 1 +#define MACB_FD_SIZE 1 +#define MACB_BIT_RATE_OFFSET 2 +#define MACB_BIT_RATE_SIZE 1 +#define MACB_JFRAME_OFFSET 3 +#define MACB_JFRAME_SIZE 1 +#define MACB_CAF_OFFSET 4 +#define MACB_CAF_SIZE 1 +#define MACB_NBC_OFFSET 5 +#define MACB_NBC_SIZE 1 +#define MACB_NCFGR_MTI_OFFSET 6 +#define MACB_NCFGR_MTI_SIZE 1 +#define MACB_UNI_OFFSET 7 +#define MACB_UNI_SIZE 1 +#define MACB_BIG_OFFSET 8 +#define MACB_BIG_SIZE 1 +#define MACB_EAE_OFFSET 9 +#define MACB_EAE_SIZE 1 +#define MACB_CLK_OFFSET 10 +#define MACB_CLK_SIZE 2 +#define MACB_RTY_OFFSET 12 +#define MACB_RTY_SIZE 1 +#define MACB_PAE_OFFSET 13 +#define MACB_PAE_SIZE 1 +#define MACB_RBOF_OFFSET 14 +#define MACB_RBOF_SIZE 2 +#define MACB_RLCE_OFFSET 16 +#define MACB_RLCE_SIZE 1 +#define MACB_DRFCS_OFFSET 17 +#define MACB_DRFCS_SIZE 1 +#define MACB_EFRHD_OFFSET 18 +#define MACB_EFRHD_SIZE 1 +#define MACB_IRXFCS_OFFSET 19 +#define MACB_IRXFCS_SIZE 1 /* Bitfields in NSR */ -#define MACB_NSR_LINK_OFFSET 0 -#define MACB_NSR_LINK_SIZE 1 -#define MACB_MDIO_OFFSET 1 -#define MACB_MDIO_SIZE 1 -#define MACB_IDLE_OFFSET 2 -#define MACB_IDLE_SIZE 1 +#define MACB_NSR_LINK_OFFSET 0 +#define MACB_NSR_LINK_SIZE 1 +#define MACB_MDIO_OFFSET 1 +#define MACB_MDIO_SIZE 1 +#define MACB_IDLE_OFFSET 2 +#define MACB_IDLE_SIZE 1 /* Bitfields in TSR */ -#define MACB_UBR_OFFSET 0 -#define MACB_UBR_SIZE 1 -#define MACB_COL_OFFSET 1 -#define MACB_COL_SIZE 1 -#define MACB_TSR_RLE_OFFSET 2 -#define MACB_TSR_RLE_SIZE 1 -#define MACB_TGO_OFFSET 3 -#define MACB_TGO_SIZE 1 -#define MACB_BEX_OFFSET 4 -#define MACB_BEX_SIZE 1 -#define MACB_COMP_OFFSET 5 -#define MACB_COMP_SIZE 1 -#define MACB_UND_OFFSET 6 -#define MACB_UND_SIZE 1 +#define MACB_UBR_OFFSET 0 +#define MACB_UBR_SIZE 1 +#define MACB_COL_OFFSET 1 +#define MACB_COL_SIZE 1 +#define MACB_TSR_RLE_OFFSET 2 +#define MACB_TSR_RLE_SIZE 1 +#define MACB_TGO_OFFSET 3 +#define MACB_TGO_SIZE 1 +#define MACB_BEX_OFFSET 4 +#define MACB_BEX_SIZE 1 +#define MACB_COMP_OFFSET 5 +#define MACB_COMP_SIZE 1 +#define MACB_UND_OFFSET 6 +#define MACB_UND_SIZE 1 /* Bitfields in RSR */ -#define MACB_BNA_OFFSET 0 -#define MACB_BNA_SIZE 1 -#define MACB_REC_OFFSET 1 -#define MACB_REC_SIZE 1 -#define MACB_OVR_OFFSET 2 -#define MACB_OVR_SIZE 1 +#define MACB_BNA_OFFSET 0 +#define MACB_BNA_SIZE 1 +#define MACB_REC_OFFSET 1 +#define MACB_REC_SIZE 1 +#define MACB_OVR_OFFSET 2 +#define MACB_OVR_SIZE 1 /* Bitfields in ISR/IER/IDR/IMR */ -#define MACB_MFD_OFFSET 0 -#define MACB_MFD_SIZE 1 -#define MACB_RCOMP_OFFSET 1 -#define MACB_RCOMP_SIZE 1 -#define MACB_RXUBR_OFFSET 2 -#define MACB_RXUBR_SIZE 1 -#define MACB_TXUBR_OFFSET 3 -#define MACB_TXUBR_SIZE 1 -#define MACB_ISR_TUND_OFFSET 4 -#define MACB_ISR_TUND_SIZE 1 -#define MACB_ISR_RLE_OFFSET 5 -#define MACB_ISR_RLE_SIZE 1 -#define MACB_TXERR_OFFSET 6 -#define MACB_TXERR_SIZE 1 -#define MACB_TCOMP_OFFSET 7 -#define MACB_TCOMP_SIZE 1 -#define MACB_ISR_LINK_OFFSET 9 -#define MACB_ISR_LINK_SIZE 1 -#define MACB_ISR_ROVR_OFFSET 10 -#define MACB_ISR_ROVR_SIZE 1 -#define MACB_HRESP_OFFSET 11 -#define MACB_HRESP_SIZE 1 -#define MACB_PFR_OFFSET 12 -#define MACB_PFR_SIZE 1 -#define MACB_PTZ_OFFSET 13 -#define MACB_PTZ_SIZE 1 +#define MACB_MFD_OFFSET 0 +#define MACB_MFD_SIZE 1 +#define MACB_RCOMP_OFFSET 1 +#define MACB_RCOMP_SIZE 1 +#define MACB_RXUBR_OFFSET 2 +#define MACB_RXUBR_SIZE 1 +#define MACB_TXUBR_OFFSET 3 +#define MACB_TXUBR_SIZE 1 +#define MACB_ISR_TUND_OFFSET 4 +#define MACB_ISR_TUND_SIZE 1 +#define MACB_ISR_RLE_OFFSET 5 +#define MACB_ISR_RLE_SIZE 1 +#define MACB_TXERR_OFFSET 6 +#define MACB_TXERR_SIZE 1 +#define MACB_TCOMP_OFFSET 7 +#define MACB_TCOMP_SIZE 1 +#define MACB_ISR_LINK_OFFSET 9 +#define MACB_ISR_LINK_SIZE 1 +#define MACB_ISR_ROVR_OFFSET 10 +#define MACB_ISR_ROVR_SIZE 1 +#define MACB_HRESP_OFFSET 11 +#define MACB_HRESP_SIZE 1 +#define MACB_PFR_OFFSET 12 +#define MACB_PFR_SIZE 1 +#define MACB_PTZ_OFFSET 13 +#define MACB_PTZ_SIZE 1 /* Bitfields in MAN */ -#define MACB_DATA_OFFSET 0 -#define MACB_DATA_SIZE 16 -#define MACB_CODE_OFFSET 16 -#define MACB_CODE_SIZE 2 -#define MACB_REGA_OFFSET 18 -#define MACB_REGA_SIZE 5 -#define MACB_PHYA_OFFSET 23 -#define MACB_PHYA_SIZE 5 -#define MACB_RW_OFFSET 28 -#define MACB_RW_SIZE 2 -#define MACB_SOF_OFFSET 30 -#define MACB_SOF_SIZE 2 +#define MACB_DATA_OFFSET 0 +#define MACB_DATA_SIZE 16 +#define MACB_CODE_OFFSET 16 +#define MACB_CODE_SIZE 2 +#define MACB_REGA_OFFSET 18 +#define MACB_REGA_SIZE 5 +#define MACB_PHYA_OFFSET 23 +#define MACB_PHYA_SIZE 5 +#define MACB_RW_OFFSET 28 +#define MACB_RW_SIZE 2 +#define MACB_SOF_OFFSET 30 +#define MACB_SOF_SIZE 2 /* Bitfields in USRIO (AVR32) */ -#define MACB_MII_OFFSET 0 -#define MACB_MII_SIZE 1 -#define MACB_EAM_OFFSET 1 -#define MACB_EAM_SIZE 1 -#define MACB_TX_PAUSE_OFFSET 2 -#define MACB_TX_PAUSE_SIZE 1 -#define MACB_TX_PAUSE_ZERO_OFFSET 3 -#define MACB_TX_PAUSE_ZERO_SIZE 1 +#define MACB_MII_OFFSET 0 +#define MACB_MII_SIZE 1 +#define MACB_EAM_OFFSET 1 +#define MACB_EAM_SIZE 1 +#define MACB_TX_PAUSE_OFFSET 2 +#define MACB_TX_PAUSE_SIZE 1 +#define MACB_TX_PAUSE_ZERO_OFFSET 3 +#define MACB_TX_PAUSE_ZERO_SIZE 1 /* Bitfields in USRIO (AT91) */ -#define MACB_RMII_OFFSET 0 -#define MACB_RMII_SIZE 1 -#define MACB_CLKEN_OFFSET 1 -#define MACB_CLKEN_SIZE 1 +#define MACB_RMII_OFFSET 0 +#define MACB_RMII_SIZE 1 +#define MACB_CLKEN_OFFSET 1 +#define MACB_CLKEN_SIZE 1 /* Bitfields in WOL */ -#define MACB_IP_OFFSET 0 -#define MACB_IP_SIZE 16 -#define MACB_MAG_OFFSET 16 -#define MACB_MAG_SIZE 1 -#define MACB_ARP_OFFSET 17 -#define MACB_ARP_SIZE 1 -#define MACB_SA1_OFFSET 18 -#define MACB_SA1_SIZE 1 -#define MACB_WOL_MTI_OFFSET 19 -#define MACB_WOL_MTI_SIZE 1 +#define MACB_IP_OFFSET 0 +#define MACB_IP_SIZE 16 +#define MACB_MAG_OFFSET 16 +#define MACB_MAG_SIZE 1 +#define MACB_ARP_OFFSET 17 +#define MACB_ARP_SIZE 1 +#define MACB_SA1_OFFSET 18 +#define MACB_SA1_SIZE 1 +#define MACB_WOL_MTI_OFFSET 19 +#define MACB_WOL_MTI_SIZE 1 /* Constants for CLK */ -#define MACB_CLK_DIV8 0 -#define MACB_CLK_DIV16 1 -#define MACB_CLK_DIV32 2 -#define MACB_CLK_DIV64 3 +#define MACB_CLK_DIV8 0 +#define MACB_CLK_DIV16 1 +#define MACB_CLK_DIV32 2 +#define MACB_CLK_DIV64 3 /* Constants for MAN register */ -#define MACB_MAN_SOF 1 -#define MACB_MAN_WRITE 1 -#define MACB_MAN_READ 2 -#define MACB_MAN_CODE 2 +#define MACB_MAN_SOF 1 +#define MACB_MAN_WRITE 1 +#define MACB_MAN_READ 2 +#define MACB_MAN_CODE 2 /* Bit manipulation macros */ -#define MACB_BIT(name) \ - (1 << MACB_##name##_OFFSET) -#define MACB_BF(name,value) \ - (((value) & ((1 << MACB_##name##_SIZE) - 1)) \ - << MACB_##name##_OFFSET) +#define MACB_BIT(name) \ + (1 << MACB_##name##_OFFSET) +#define MACB_BF(name,value) \ + (((value) & ((1 << MACB_##name##_SIZE) - 1)) \ + << MACB_##name##_OFFSET) #define MACB_BFEXT(name,value)\ - (((value) >> MACB_##name##_OFFSET) \ - & ((1 << MACB_##name##_SIZE) - 1)) -#define MACB_BFINS(name,value,old) \ - (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \ - << MACB_##name##_OFFSET)) \ - | MACB_BF(name,value)) + (((value) >> MACB_##name##_OFFSET) \ + & ((1 << MACB_##name##_SIZE) - 1)) +#define MACB_BFINS(name,value,old) \ + (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \ + << MACB_##name##_OFFSET)) \ + | MACB_BF(name,value)) /* Register access macros */ -#define macb_readl(port,reg) \ - readl((port)->regs + MACB_##reg) -#define macb_writel(port,reg,value) \ - writel((value), (port)->regs + MACB_##reg) +#define macb_readl(port,reg) \ + readl((port)->regs + MACB_##reg) +#define macb_writel(port,reg,value) \ + writel((value), (port)->regs + MACB_##reg) struct dma_desc { - rt_uint32_t addr; - rt_uint32_t ctrl; + rt_uint32_t addr; + rt_uint32_t ctrl; }; /* DMA descriptor bitfields */ -#define MACB_RX_USED_OFFSET 0 -#define MACB_RX_USED_SIZE 1 -#define MACB_RX_WRAP_OFFSET 1 -#define MACB_RX_WRAP_SIZE 1 -#define MACB_RX_WADDR_OFFSET 2 -#define MACB_RX_WADDR_SIZE 30 +#define MACB_RX_USED_OFFSET 0 +#define MACB_RX_USED_SIZE 1 +#define MACB_RX_WRAP_OFFSET 1 +#define MACB_RX_WRAP_SIZE 1 +#define MACB_RX_WADDR_OFFSET 2 +#define MACB_RX_WADDR_SIZE 30 -#define MACB_RX_FRMLEN_OFFSET 0 -#define MACB_RX_FRMLEN_SIZE 12 -#define MACB_RX_OFFSET_OFFSET 12 -#define MACB_RX_OFFSET_SIZE 2 -#define MACB_RX_SOF_OFFSET 14 -#define MACB_RX_SOF_SIZE 1 -#define MACB_RX_EOF_OFFSET 15 -#define MACB_RX_EOF_SIZE 1 -#define MACB_RX_CFI_OFFSET 16 -#define MACB_RX_CFI_SIZE 1 -#define MACB_RX_VLAN_PRI_OFFSET 17 -#define MACB_RX_VLAN_PRI_SIZE 3 -#define MACB_RX_PRI_TAG_OFFSET 20 -#define MACB_RX_PRI_TAG_SIZE 1 -#define MACB_RX_VLAN_TAG_OFFSET 21 -#define MACB_RX_VLAN_TAG_SIZE 1 -#define MACB_RX_TYPEID_MATCH_OFFSET 22 -#define MACB_RX_TYPEID_MATCH_SIZE 1 -#define MACB_RX_SA4_MATCH_OFFSET 23 -#define MACB_RX_SA4_MATCH_SIZE 1 -#define MACB_RX_SA3_MATCH_OFFSET 24 -#define MACB_RX_SA3_MATCH_SIZE 1 -#define MACB_RX_SA2_MATCH_OFFSET 25 -#define MACB_RX_SA2_MATCH_SIZE 1 -#define MACB_RX_SA1_MATCH_OFFSET 26 -#define MACB_RX_SA1_MATCH_SIZE 1 -#define MACB_RX_EXT_MATCH_OFFSET 28 -#define MACB_RX_EXT_MATCH_SIZE 1 -#define MACB_RX_UHASH_MATCH_OFFSET 29 -#define MACB_RX_UHASH_MATCH_SIZE 1 -#define MACB_RX_MHASH_MATCH_OFFSET 30 -#define MACB_RX_MHASH_MATCH_SIZE 1 -#define MACB_RX_BROADCAST_OFFSET 31 -#define MACB_RX_BROADCAST_SIZE 1 +#define MACB_RX_FRMLEN_OFFSET 0 +#define MACB_RX_FRMLEN_SIZE 12 +#define MACB_RX_OFFSET_OFFSET 12 +#define MACB_RX_OFFSET_SIZE 2 +#define MACB_RX_SOF_OFFSET 14 +#define MACB_RX_SOF_SIZE 1 +#define MACB_RX_EOF_OFFSET 15 +#define MACB_RX_EOF_SIZE 1 +#define MACB_RX_CFI_OFFSET 16 +#define MACB_RX_CFI_SIZE 1 +#define MACB_RX_VLAN_PRI_OFFSET 17 +#define MACB_RX_VLAN_PRI_SIZE 3 +#define MACB_RX_PRI_TAG_OFFSET 20 +#define MACB_RX_PRI_TAG_SIZE 1 +#define MACB_RX_VLAN_TAG_OFFSET 21 +#define MACB_RX_VLAN_TAG_SIZE 1 +#define MACB_RX_TYPEID_MATCH_OFFSET 22 +#define MACB_RX_TYPEID_MATCH_SIZE 1 +#define MACB_RX_SA4_MATCH_OFFSET 23 +#define MACB_RX_SA4_MATCH_SIZE 1 +#define MACB_RX_SA3_MATCH_OFFSET 24 +#define MACB_RX_SA3_MATCH_SIZE 1 +#define MACB_RX_SA2_MATCH_OFFSET 25 +#define MACB_RX_SA2_MATCH_SIZE 1 +#define MACB_RX_SA1_MATCH_OFFSET 26 +#define MACB_RX_SA1_MATCH_SIZE 1 +#define MACB_RX_EXT_MATCH_OFFSET 28 +#define MACB_RX_EXT_MATCH_SIZE 1 +#define MACB_RX_UHASH_MATCH_OFFSET 29 +#define MACB_RX_UHASH_MATCH_SIZE 1 +#define MACB_RX_MHASH_MATCH_OFFSET 30 +#define MACB_RX_MHASH_MATCH_SIZE 1 +#define MACB_RX_BROADCAST_OFFSET 31 +#define MACB_RX_BROADCAST_SIZE 1 -#define MACB_TX_FRMLEN_OFFSET 0 -#define MACB_TX_FRMLEN_SIZE 11 -#define MACB_TX_LAST_OFFSET 15 -#define MACB_TX_LAST_SIZE 1 -#define MACB_TX_NOCRC_OFFSET 16 -#define MACB_TX_NOCRC_SIZE 1 -#define MACB_TX_BUF_EXHAUSTED_OFFSET 27 -#define MACB_TX_BUF_EXHAUSTED_SIZE 1 -#define MACB_TX_UNDERRUN_OFFSET 28 -#define MACB_TX_UNDERRUN_SIZE 1 -#define MACB_TX_ERROR_OFFSET 29 -#define MACB_TX_ERROR_SIZE 1 -#define MACB_TX_WRAP_OFFSET 30 -#define MACB_TX_WRAP_SIZE 1 -#define MACB_TX_USED_OFFSET 31 -#define MACB_TX_USED_SIZE 1 +#define MACB_TX_FRMLEN_OFFSET 0 +#define MACB_TX_FRMLEN_SIZE 11 +#define MACB_TX_LAST_OFFSET 15 +#define MACB_TX_LAST_SIZE 1 +#define MACB_TX_NOCRC_OFFSET 16 +#define MACB_TX_NOCRC_SIZE 1 +#define MACB_TX_BUF_EXHAUSTED_OFFSET 27 +#define MACB_TX_BUF_EXHAUSTED_SIZE 1 +#define MACB_TX_UNDERRUN_OFFSET 28 +#define MACB_TX_UNDERRUN_SIZE 1 +#define MACB_TX_ERROR_OFFSET 29 +#define MACB_TX_ERROR_SIZE 1 +#define MACB_TX_WRAP_OFFSET 30 +#define MACB_TX_WRAP_SIZE 1 +#define MACB_TX_USED_OFFSET 31 +#define MACB_TX_USED_SIZE 1 extern int rt_hw_macb_init(); diff --git a/bsp/at91sam9g45/drivers/mii.h b/bsp/at91sam9g45/drivers/mii.h index 2f6dd18e71..03d914b7c3 100644 --- a/bsp/at91sam9g45/drivers/mii.h +++ b/bsp/at91sam9g45/drivers/mii.h @@ -1,21 +1,7 @@ /* - * File : mii.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -36,7 +22,7 @@ #define MII_EXPANSION 0x06 /* Expansion register */ #define MII_CTRL1000 0x09 /* 1000BASE-T control */ #define MII_STAT1000 0x0a /* 1000BASE-T status */ -#define MII_ESTATUS 0x0f /* Extended Status */ +#define MII_ESTATUS 0x0f /* Extended Status */ #define MII_DCOUNTER 0x12 /* Disconnect counter */ #define MII_FCSCOUNTER 0x13 /* False carrier counter */ #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ @@ -51,7 +37,7 @@ /* Basic mode control register. */ #define BMCR_RESV 0x003f /* Unused... */ -#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ #define BMCR_CTST 0x0080 /* Collision test */ #define BMCR_FULLDPLX 0x0100 /* Full duplex */ #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ @@ -70,7 +56,7 @@ #define BMSR_RFAULT 0x0010 /* Remote fault detected */ #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ #define BMSR_RESV 0x00c0 /* Unused... */ -#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ +#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */ #define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */ #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ @@ -99,7 +85,7 @@ #define ADVERTISE_NPAGE 0x8000 /* Next page bit */ #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ - ADVERTISE_CSMA) + ADVERTISE_CSMA) #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ ADVERTISE_100HALF | ADVERTISE_100FULL) @@ -121,8 +107,8 @@ #define LPA_LPACK 0x4000 /* Link partner acked us */ #define LPA_NPAGE 0x8000 /* Next page bit */ -#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) -#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) +#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) /* Expansion register for auto-negotiation. */ #define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ @@ -132,8 +118,8 @@ #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ #define EXPANSION_RESV 0xffe0 /* Unused... */ -#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ -#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ +#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ +#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ /* N-way test register. */ #define NWAYTEST_RESV1 0x00ff /* Unused... */ @@ -151,8 +137,8 @@ #define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */ /* Flow control flags */ -#define FLOW_CTRL_TX 0x01 -#define FLOW_CTRL_RX 0x02 +#define FLOW_CTRL_TX 0x01 +#define FLOW_CTRL_RX 0x02 /** * mii_nway_result diff --git a/bsp/at91sam9g45/drivers/usart.c b/bsp/at91sam9g45/drivers/usart.c index d4ba657232..fdcb2f8537 100644 --- a/bsp/at91sam9g45/drivers/usart.c +++ b/bsp/at91sam9g45/drivers/usart.c @@ -1,21 +1,7 @@ /* - * File : usart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -30,8 +16,8 @@ struct at91_uart { - AT91S_USART *port; - int irq; + AT91S_USART *port; + int irq; }; @@ -40,18 +26,18 @@ struct at91_uart { */ void rt_at91_usart_handler(int vector, void *param) { - int status; - struct at91_uart *uart; - rt_device_t dev = (rt_device_t)param; - uart = (struct at91_uart *)dev->user_data; - status = uart->port->US_CSR; - if (!(status & uart->port->US_IMR)) /* check actived and enabled interrupt */ - { - return; - } - rt_interrupt_enter(); - rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND); - rt_interrupt_leave(); + int status; + struct at91_uart *uart; + rt_device_t dev = (rt_device_t)param; + uart = (struct at91_uart *)dev->user_data; + status = uart->port->US_CSR; + if (!(status & uart->port->US_IMR)) /* check actived and enabled interrupt */ + { + return; + } + rt_interrupt_enter(); + rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND); + rt_interrupt_leave(); } /** @@ -60,68 +46,68 @@ void rt_at91_usart_handler(int vector, void *param) static rt_err_t at91_usart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { - int div; - int mode = 0; - struct at91_uart *uart; + int div; + int mode = 0; + struct at91_uart *uart; - RT_ASSERT(serial != RT_NULL); + RT_ASSERT(serial != RT_NULL); RT_ASSERT(cfg != RT_NULL); - uart = (struct at91_uart *)serial->parent.user_data; + uart = (struct at91_uart *)serial->parent.user_data; - uart->port->US_CR = AT91C_US_RSTTX | AT91C_US_RSTRX | - AT91C_US_RXDIS | AT91C_US_TXDIS; - mode |= AT91C_US_USMODE_NORMAL | AT91C_US_CLKS_CLOCK | - AT91C_US_CHMODE_NORMAL; - switch (cfg->data_bits) - { - case DATA_BITS_8: - mode |= AT91C_US_CHRL_8_BITS; - break; - case DATA_BITS_7: - mode |= AT91C_US_CHRL_7_BITS; - break; - case DATA_BITS_6: - mode |= AT91C_US_CHRL_6_BITS; - break; - case DATA_BITS_5: - mode |= AT91C_US_CHRL_5_BITS; - break; - default: - mode |= AT91C_US_CHRL_8_BITS; - break; - } + uart->port->US_CR = AT91C_US_RSTTX | AT91C_US_RSTRX | + AT91C_US_RXDIS | AT91C_US_TXDIS; + mode |= AT91C_US_USMODE_NORMAL | AT91C_US_CLKS_CLOCK | + AT91C_US_CHMODE_NORMAL; + switch (cfg->data_bits) + { + case DATA_BITS_8: + mode |= AT91C_US_CHRL_8_BITS; + break; + case DATA_BITS_7: + mode |= AT91C_US_CHRL_7_BITS; + break; + case DATA_BITS_6: + mode |= AT91C_US_CHRL_6_BITS; + break; + case DATA_BITS_5: + mode |= AT91C_US_CHRL_5_BITS; + break; + default: + mode |= AT91C_US_CHRL_8_BITS; + break; + } - switch (cfg->stop_bits) - { - case STOP_BITS_2: - mode |= AT91C_US_NBSTOP_2_BIT; - break; - case STOP_BITS_1: - default: - mode |= AT91C_US_NBSTOP_1_BIT; - break; - } + switch (cfg->stop_bits) + { + case STOP_BITS_2: + mode |= AT91C_US_NBSTOP_2_BIT; + break; + case STOP_BITS_1: + default: + mode |= AT91C_US_NBSTOP_1_BIT; + break; + } - switch (cfg->parity) - { - case PARITY_ODD: - mode |= AT91C_US_PAR_ODD; - break; - case PARITY_EVEN: - mode |= AT91C_US_PAR_EVEN; - break; - case PARITY_NONE: - default: - mode |= AT91C_US_PAR_NONE; - break; - } + switch (cfg->parity) + { + case PARITY_ODD: + mode |= AT91C_US_PAR_ODD; + break; + case PARITY_EVEN: + mode |= AT91C_US_PAR_EVEN; + break; + case PARITY_NONE: + default: + mode |= AT91C_US_PAR_NONE; + break; + } - uart->port->US_MR = mode; + uart->port->US_MR = mode; /* Assume OVER is cleared and fractional baudrate generator is disabled */ - div = (clk_get_rate(clk_get("mck")) / 16 + cfg->baud_rate/2) / cfg->baud_rate; - uart->port->US_BRGR = div; - uart->port->US_CR = AT91C_US_RXEN | AT91C_US_TXEN; - uart->port->US_IER = AT91C_US_RXRDY; + div = (clk_get_rate(clk_get("mck")) / 16 + cfg->baud_rate/2) / cfg->baud_rate; + uart->port->US_BRGR = div; + uart->port->US_CR = AT91C_US_RXEN | AT91C_US_TXEN; + uart->port->US_IER = AT91C_US_RXRDY; return RT_EOK; } @@ -138,11 +124,11 @@ static rt_err_t at91_usart_control(struct rt_serial_device *serial, { case RT_DEVICE_CTRL_CLR_INT: /* disable rx irq */ - rt_hw_interrupt_mask(uart->irq); + rt_hw_interrupt_mask(uart->irq); break; case RT_DEVICE_CTRL_SET_INT: /* enable rx irq */ - rt_hw_interrupt_umask(uart->irq); + rt_hw_interrupt_umask(uart->irq); break; } @@ -152,10 +138,10 @@ static rt_err_t at91_usart_control(struct rt_serial_device *serial, static int at91_usart_putc(struct rt_serial_device *serial, char c) { //rt_uint32_t level; - struct at91_uart *uart = serial->parent.user_data; + struct at91_uart *uart = serial->parent.user_data; while (!(uart->port->US_CSR & AT91C_US_TXRDY)); - uart->port->US_THR = c; + uart->port->US_THR = c; return 1; } @@ -163,16 +149,16 @@ static int at91_usart_putc(struct rt_serial_device *serial, char c) static int at91_usart_getc(struct rt_serial_device *serial) { int result; - struct at91_uart *uart = serial->parent.user_data; + struct at91_uart *uart = serial->parent.user_data; if (uart->port->US_CSR & AT91C_US_RXRDY) - { - result = uart->port->US_RHR & 0xff; - } - else - { - result = -1; - } + { + result = uart->port->US_RHR & 0xff; + } + else + { + result = -1; + } return result; } @@ -188,8 +174,8 @@ static const struct rt_uart_ops at91_usart_ops = #if defined(RT_USING_DBGU) static struct rt_serial_device serial_dbgu; struct at91_uart dbgu = { - (AT91PS_USART)AT91C_BASE_DBGU, - AT91C_ID_SYS + (AT91PS_USART)AT91C_BASE_DBGU, + AT91C_ID_SYS }; #endif @@ -197,32 +183,32 @@ struct at91_uart dbgu = { #if defined(RT_USING_UART0) static struct rt_serial_device serial0; struct at91_uart uart0 = { - AT91C_BASE_US0, - AT91C_ID_US0 + AT91C_BASE_US0, + AT91C_ID_US0 }; #endif #if defined(RT_USING_UART1) static struct rt_serial_device serial1; struct at91_uart uart1 = { - AT91C_BASE_US1, - AT91C_ID_US1 + AT91C_BASE_US1, + AT91C_ID_US1 }; #endif #if defined(RT_USING_UART2) static struct rt_serial_device serial2; struct at91_uart uart2 = { - AT91C_BASE_US2, - AT91C_ID_US2 + AT91C_BASE_US2, + AT91C_ID_US2 }; #endif #if defined(RT_USING_UART3) static struct rt_serial_device serial3; struct at91_uart uart3 = { - AT91C_BASE_US3, - AT91C_ID_US3 + AT91C_BASE_US3, + AT91C_ID_US3 }; #endif @@ -230,57 +216,57 @@ struct at91_uart uart3 = { void at91_usart_gpio_init(void) { #ifdef RT_USING_DBGU -#define DRXD 12 // DBGU rx as Peripheral A on PB12 -#define DTXD 13 // DBGU tx as Peripheral A on PB13 - AT91C_BASE_PIOB->PIO_IDR, (1<PIO_PPUDR, (1<PIO_ASR, (1<PIO_PDR, (1<PMC_PCER, 1 << AT91C_ID_SYS; +#define DRXD 12 // DBGU rx as Peripheral A on PB12 +#define DTXD 13 // DBGU tx as Peripheral A on PB13 + AT91C_BASE_PIOB->PIO_IDR, (1<PIO_PPUDR, (1<PIO_ASR, (1<PIO_PDR, (1<PMC_PCER, 1 << AT91C_ID_SYS; #endif #ifdef RT_USING_UART0 -#define RXD0 18 // UART0 rx as Peripheral A on PB18 -#define TXD0 19 // UART0 tx as Peripheral A on PB19 - AT91C_BASE_PMC->PMC_PCER, 1 << AT91C_ID_US0; - AT91C_BASE_PIOB->PIO_IDR, (1<PIO_PPUER, (1<PIO_PPUDR, (1<PIO_ASR, (1<PIO_PDR, (1<PMC_PCER, 1 << AT91C_ID_US0; + AT91C_BASE_PIOB->PIO_IDR, (1<PIO_PPUER, (1<PIO_PPUDR, (1<PIO_ASR, (1<PIO_PDR, (1<PMC_PCER, 1 << AT91C_ID_US1; - AT91C_BASE_PIOB->PIO_IDR, (1<PIO_PPUER, (1<PIO_PPUDR, (1<PIO_ASR, (1<PIO_PDR, (1<PMC_PCER, 1 << AT91C_ID_US1; + AT91C_BASE_PIOB->PIO_IDR, (1<PIO_PPUER, (1<PIO_PPUDR, (1<PIO_ASR, (1<PIO_PDR, (1<PMC_PCER, 1 << AT91C_ID_US2; - AT91C_BASE_PIOB->PIO_IDR, (1<PIO_PPUER, (1<PIO_PPUDR, (1<PIO_ASR, (1<PIO_PDR, (1<PMC_PCER, 1 << AT91C_ID_US2; + AT91C_BASE_PIOB->PIO_IDR, (1<PIO_PPUER, (1<PIO_PPUDR, (1<PIO_ASR, (1<PIO_PDR, (1<PMC_PCER, 1<PIO_IDR, (1<PIO_PPUER, (1<PIO_PPUDR, (1<PIO_ASR, (1<PIO_PDR, (1<PMC_PCER, 1<PIO_IDR, (1<PIO_PPUER, (1<PIO_PPUDR, (1<PIO_ASR, (1<PIO_PDR, (1< -#define PIN_BASE AIC_IRQS +#define PIN_BASE AIC_IRQS -#define MAX_GPIO_BANKS 5 +#define MAX_GPIO_BANKS 5 -#define PIN_IRQS (MAX_GPIO_BANKS*32) +#define PIN_IRQS (MAX_GPIO_BANKS*32) /* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */ -#define AT91C_PIN_PA0 (PIN_BASE + 0x00 + 0) -#define AT91C_PIN_PA1 (PIN_BASE + 0x00 + 1) -#define AT91C_PIN_PA2 (PIN_BASE + 0x00 + 2) -#define AT91C_PIN_PA3 (PIN_BASE + 0x00 + 3) -#define AT91C_PIN_PA4 (PIN_BASE + 0x00 + 4) -#define AT91C_PIN_PA5 (PIN_BASE + 0x00 + 5) -#define AT91C_PIN_PA6 (PIN_BASE + 0x00 + 6) -#define AT91C_PIN_PA7 (PIN_BASE + 0x00 + 7) -#define AT91C_PIN_PA8 (PIN_BASE + 0x00 + 8) -#define AT91C_PIN_PA9 (PIN_BASE + 0x00 + 9) -#define AT91C_PIN_PA10 (PIN_BASE + 0x00 + 10) -#define AT91C_PIN_PA11 (PIN_BASE + 0x00 + 11) -#define AT91C_PIN_PA12 (PIN_BASE + 0x00 + 12) -#define AT91C_PIN_PA13 (PIN_BASE + 0x00 + 13) -#define AT91C_PIN_PA14 (PIN_BASE + 0x00 + 14) -#define AT91C_PIN_PA15 (PIN_BASE + 0x00 + 15) -#define AT91C_PIN_PA16 (PIN_BASE + 0x00 + 16) -#define AT91C_PIN_PA17 (PIN_BASE + 0x00 + 17) -#define AT91C_PIN_PA18 (PIN_BASE + 0x00 + 18) -#define AT91C_PIN_PA19 (PIN_BASE + 0x00 + 19) -#define AT91C_PIN_PA20 (PIN_BASE + 0x00 + 20) -#define AT91C_PIN_PA21 (PIN_BASE + 0x00 + 21) -#define AT91C_PIN_PA22 (PIN_BASE + 0x00 + 22) -#define AT91C_PIN_PA23 (PIN_BASE + 0x00 + 23) -#define AT91C_PIN_PA24 (PIN_BASE + 0x00 + 24) -#define AT91C_PIN_PA25 (PIN_BASE + 0x00 + 25) -#define AT91C_PIN_PA26 (PIN_BASE + 0x00 + 26) -#define AT91C_PIN_PA27 (PIN_BASE + 0x00 + 27) -#define AT91C_PIN_PA28 (PIN_BASE + 0x00 + 28) -#define AT91C_PIN_PA29 (PIN_BASE + 0x00 + 29) -#define AT91C_PIN_PA30 (PIN_BASE + 0x00 + 30) -#define AT91C_PIN_PA31 (PIN_BASE + 0x00 + 31) +#define AT91C_PIN_PA0 (PIN_BASE + 0x00 + 0) +#define AT91C_PIN_PA1 (PIN_BASE + 0x00 + 1) +#define AT91C_PIN_PA2 (PIN_BASE + 0x00 + 2) +#define AT91C_PIN_PA3 (PIN_BASE + 0x00 + 3) +#define AT91C_PIN_PA4 (PIN_BASE + 0x00 + 4) +#define AT91C_PIN_PA5 (PIN_BASE + 0x00 + 5) +#define AT91C_PIN_PA6 (PIN_BASE + 0x00 + 6) +#define AT91C_PIN_PA7 (PIN_BASE + 0x00 + 7) +#define AT91C_PIN_PA8 (PIN_BASE + 0x00 + 8) +#define AT91C_PIN_PA9 (PIN_BASE + 0x00 + 9) +#define AT91C_PIN_PA10 (PIN_BASE + 0x00 + 10) +#define AT91C_PIN_PA11 (PIN_BASE + 0x00 + 11) +#define AT91C_PIN_PA12 (PIN_BASE + 0x00 + 12) +#define AT91C_PIN_PA13 (PIN_BASE + 0x00 + 13) +#define AT91C_PIN_PA14 (PIN_BASE + 0x00 + 14) +#define AT91C_PIN_PA15 (PIN_BASE + 0x00 + 15) +#define AT91C_PIN_PA16 (PIN_BASE + 0x00 + 16) +#define AT91C_PIN_PA17 (PIN_BASE + 0x00 + 17) +#define AT91C_PIN_PA18 (PIN_BASE + 0x00 + 18) +#define AT91C_PIN_PA19 (PIN_BASE + 0x00 + 19) +#define AT91C_PIN_PA20 (PIN_BASE + 0x00 + 20) +#define AT91C_PIN_PA21 (PIN_BASE + 0x00 + 21) +#define AT91C_PIN_PA22 (PIN_BASE + 0x00 + 22) +#define AT91C_PIN_PA23 (PIN_BASE + 0x00 + 23) +#define AT91C_PIN_PA24 (PIN_BASE + 0x00 + 24) +#define AT91C_PIN_PA25 (PIN_BASE + 0x00 + 25) +#define AT91C_PIN_PA26 (PIN_BASE + 0x00 + 26) +#define AT91C_PIN_PA27 (PIN_BASE + 0x00 + 27) +#define AT91C_PIN_PA28 (PIN_BASE + 0x00 + 28) +#define AT91C_PIN_PA29 (PIN_BASE + 0x00 + 29) +#define AT91C_PIN_PA30 (PIN_BASE + 0x00 + 30) +#define AT91C_PIN_PA31 (PIN_BASE + 0x00 + 31) -#define AT91C_PIN_PB0 (PIN_BASE + 0x20 + 0) -#define AT91C_PIN_PB1 (PIN_BASE + 0x20 + 1) -#define AT91C_PIN_PB2 (PIN_BASE + 0x20 + 2) -#define AT91C_PIN_PB3 (PIN_BASE + 0x20 + 3) -#define AT91C_PIN_PB4 (PIN_BASE + 0x20 + 4) -#define AT91C_PIN_PB5 (PIN_BASE + 0x20 + 5) -#define AT91C_PIN_PB6 (PIN_BASE + 0x20 + 6) -#define AT91C_PIN_PB7 (PIN_BASE + 0x20 + 7) -#define AT91C_PIN_PB8 (PIN_BASE + 0x20 + 8) -#define AT91C_PIN_PB9 (PIN_BASE + 0x20 + 9) -#define AT91C_PIN_PB10 (PIN_BASE + 0x20 + 10) -#define AT91C_PIN_PB11 (PIN_BASE + 0x20 + 11) -#define AT91C_PIN_PB12 (PIN_BASE + 0x20 + 12) -#define AT91C_PIN_PB13 (PIN_BASE + 0x20 + 13) -#define AT91C_PIN_PB14 (PIN_BASE + 0x20 + 14) -#define AT91C_PIN_PB15 (PIN_BASE + 0x20 + 15) -#define AT91C_PIN_PB16 (PIN_BASE + 0x20 + 16) -#define AT91C_PIN_PB17 (PIN_BASE + 0x20 + 17) -#define AT91C_PIN_PB18 (PIN_BASE + 0x20 + 18) -#define AT91C_PIN_PB19 (PIN_BASE + 0x20 + 19) -#define AT91C_PIN_PB20 (PIN_BASE + 0x20 + 20) -#define AT91C_PIN_PB21 (PIN_BASE + 0x20 + 21) -#define AT91C_PIN_PB22 (PIN_BASE + 0x20 + 22) -#define AT91C_PIN_PB23 (PIN_BASE + 0x20 + 23) -#define AT91C_PIN_PB24 (PIN_BASE + 0x20 + 24) -#define AT91C_PIN_PB25 (PIN_BASE + 0x20 + 25) -#define AT91C_PIN_PB26 (PIN_BASE + 0x20 + 26) -#define AT91C_PIN_PB27 (PIN_BASE + 0x20 + 27) -#define AT91C_PIN_PB28 (PIN_BASE + 0x20 + 28) -#define AT91C_PIN_PB29 (PIN_BASE + 0x20 + 29) -#define AT91C_PIN_PB30 (PIN_BASE + 0x20 + 30) -#define AT91C_PIN_PB31 (PIN_BASE + 0x20 + 31) +#define AT91C_PIN_PB0 (PIN_BASE + 0x20 + 0) +#define AT91C_PIN_PB1 (PIN_BASE + 0x20 + 1) +#define AT91C_PIN_PB2 (PIN_BASE + 0x20 + 2) +#define AT91C_PIN_PB3 (PIN_BASE + 0x20 + 3) +#define AT91C_PIN_PB4 (PIN_BASE + 0x20 + 4) +#define AT91C_PIN_PB5 (PIN_BASE + 0x20 + 5) +#define AT91C_PIN_PB6 (PIN_BASE + 0x20 + 6) +#define AT91C_PIN_PB7 (PIN_BASE + 0x20 + 7) +#define AT91C_PIN_PB8 (PIN_BASE + 0x20 + 8) +#define AT91C_PIN_PB9 (PIN_BASE + 0x20 + 9) +#define AT91C_PIN_PB10 (PIN_BASE + 0x20 + 10) +#define AT91C_PIN_PB11 (PIN_BASE + 0x20 + 11) +#define AT91C_PIN_PB12 (PIN_BASE + 0x20 + 12) +#define AT91C_PIN_PB13 (PIN_BASE + 0x20 + 13) +#define AT91C_PIN_PB14 (PIN_BASE + 0x20 + 14) +#define AT91C_PIN_PB15 (PIN_BASE + 0x20 + 15) +#define AT91C_PIN_PB16 (PIN_BASE + 0x20 + 16) +#define AT91C_PIN_PB17 (PIN_BASE + 0x20 + 17) +#define AT91C_PIN_PB18 (PIN_BASE + 0x20 + 18) +#define AT91C_PIN_PB19 (PIN_BASE + 0x20 + 19) +#define AT91C_PIN_PB20 (PIN_BASE + 0x20 + 20) +#define AT91C_PIN_PB21 (PIN_BASE + 0x20 + 21) +#define AT91C_PIN_PB22 (PIN_BASE + 0x20 + 22) +#define AT91C_PIN_PB23 (PIN_BASE + 0x20 + 23) +#define AT91C_PIN_PB24 (PIN_BASE + 0x20 + 24) +#define AT91C_PIN_PB25 (PIN_BASE + 0x20 + 25) +#define AT91C_PIN_PB26 (PIN_BASE + 0x20 + 26) +#define AT91C_PIN_PB27 (PIN_BASE + 0x20 + 27) +#define AT91C_PIN_PB28 (PIN_BASE + 0x20 + 28) +#define AT91C_PIN_PB29 (PIN_BASE + 0x20 + 29) +#define AT91C_PIN_PB30 (PIN_BASE + 0x20 + 30) +#define AT91C_PIN_PB31 (PIN_BASE + 0x20 + 31) -#define AT91C_PIN_PC0 (PIN_BASE + 0x40 + 0) -#define AT91C_PIN_PC1 (PIN_BASE + 0x40 + 1) -#define AT91C_PIN_PC2 (PIN_BASE + 0x40 + 2) -#define AT91C_PIN_PC3 (PIN_BASE + 0x40 + 3) -#define AT91C_PIN_PC4 (PIN_BASE + 0x40 + 4) -#define AT91C_PIN_PC5 (PIN_BASE + 0x40 + 5) -#define AT91C_PIN_PC6 (PIN_BASE + 0x40 + 6) -#define AT91C_PIN_PC7 (PIN_BASE + 0x40 + 7) -#define AT91C_PIN_PC8 (PIN_BASE + 0x40 + 8) -#define AT91C_PIN_PC9 (PIN_BASE + 0x40 + 9) -#define AT91C_PIN_PC10 (PIN_BASE + 0x40 + 10) -#define AT91C_PIN_PC11 (PIN_BASE + 0x40 + 11) -#define AT91C_PIN_PC12 (PIN_BASE + 0x40 + 12) -#define AT91C_PIN_PC13 (PIN_BASE + 0x40 + 13) -#define AT91C_PIN_PC14 (PIN_BASE + 0x40 + 14) -#define AT91C_PIN_PC15 (PIN_BASE + 0x40 + 15) -#define AT91C_PIN_PC16 (PIN_BASE + 0x40 + 16) -#define AT91C_PIN_PC17 (PIN_BASE + 0x40 + 17) -#define AT91C_PIN_PC18 (PIN_BASE + 0x40 + 18) -#define AT91C_PIN_PC19 (PIN_BASE + 0x40 + 19) -#define AT91C_PIN_PC20 (PIN_BASE + 0x40 + 20) -#define AT91C_PIN_PC21 (PIN_BASE + 0x40 + 21) -#define AT91C_PIN_PC22 (PIN_BASE + 0x40 + 22) -#define AT91C_PIN_PC23 (PIN_BASE + 0x40 + 23) -#define AT91C_PIN_PC24 (PIN_BASE + 0x40 + 24) -#define AT91C_PIN_PC25 (PIN_BASE + 0x40 + 25) -#define AT91C_PIN_PC26 (PIN_BASE + 0x40 + 26) -#define AT91C_PIN_PC27 (PIN_BASE + 0x40 + 27) -#define AT91C_PIN_PC28 (PIN_BASE + 0x40 + 28) -#define AT91C_PIN_PC29 (PIN_BASE + 0x40 + 29) -#define AT91C_PIN_PC30 (PIN_BASE + 0x40 + 30) -#define AT91C_PIN_PC31 (PIN_BASE + 0x40 + 31) +#define AT91C_PIN_PC0 (PIN_BASE + 0x40 + 0) +#define AT91C_PIN_PC1 (PIN_BASE + 0x40 + 1) +#define AT91C_PIN_PC2 (PIN_BASE + 0x40 + 2) +#define AT91C_PIN_PC3 (PIN_BASE + 0x40 + 3) +#define AT91C_PIN_PC4 (PIN_BASE + 0x40 + 4) +#define AT91C_PIN_PC5 (PIN_BASE + 0x40 + 5) +#define AT91C_PIN_PC6 (PIN_BASE + 0x40 + 6) +#define AT91C_PIN_PC7 (PIN_BASE + 0x40 + 7) +#define AT91C_PIN_PC8 (PIN_BASE + 0x40 + 8) +#define AT91C_PIN_PC9 (PIN_BASE + 0x40 + 9) +#define AT91C_PIN_PC10 (PIN_BASE + 0x40 + 10) +#define AT91C_PIN_PC11 (PIN_BASE + 0x40 + 11) +#define AT91C_PIN_PC12 (PIN_BASE + 0x40 + 12) +#define AT91C_PIN_PC13 (PIN_BASE + 0x40 + 13) +#define AT91C_PIN_PC14 (PIN_BASE + 0x40 + 14) +#define AT91C_PIN_PC15 (PIN_BASE + 0x40 + 15) +#define AT91C_PIN_PC16 (PIN_BASE + 0x40 + 16) +#define AT91C_PIN_PC17 (PIN_BASE + 0x40 + 17) +#define AT91C_PIN_PC18 (PIN_BASE + 0x40 + 18) +#define AT91C_PIN_PC19 (PIN_BASE + 0x40 + 19) +#define AT91C_PIN_PC20 (PIN_BASE + 0x40 + 20) +#define AT91C_PIN_PC21 (PIN_BASE + 0x40 + 21) +#define AT91C_PIN_PC22 (PIN_BASE + 0x40 + 22) +#define AT91C_PIN_PC23 (PIN_BASE + 0x40 + 23) +#define AT91C_PIN_PC24 (PIN_BASE + 0x40 + 24) +#define AT91C_PIN_PC25 (PIN_BASE + 0x40 + 25) +#define AT91C_PIN_PC26 (PIN_BASE + 0x40 + 26) +#define AT91C_PIN_PC27 (PIN_BASE + 0x40 + 27) +#define AT91C_PIN_PC28 (PIN_BASE + 0x40 + 28) +#define AT91C_PIN_PC29 (PIN_BASE + 0x40 + 29) +#define AT91C_PIN_PC30 (PIN_BASE + 0x40 + 30) +#define AT91C_PIN_PC31 (PIN_BASE + 0x40 + 31) -#define AT91C_PIN_PD0 (PIN_BASE + 0x60 + 0) -#define AT91C_PIN_PD1 (PIN_BASE + 0x60 + 1) -#define AT91C_PIN_PD2 (PIN_BASE + 0x60 + 2) -#define AT91C_PIN_PD3 (PIN_BASE + 0x60 + 3) -#define AT91C_PIN_PD4 (PIN_BASE + 0x60 + 4) -#define AT91C_PIN_PD5 (PIN_BASE + 0x60 + 5) -#define AT91C_PIN_PD6 (PIN_BASE + 0x60 + 6) -#define AT91C_PIN_PD7 (PIN_BASE + 0x60 + 7) -#define AT91C_PIN_PD8 (PIN_BASE + 0x60 + 8) -#define AT91C_PIN_PD9 (PIN_BASE + 0x60 + 9) -#define AT91C_PIN_PD10 (PIN_BASE + 0x60 + 10) -#define AT91C_PIN_PD11 (PIN_BASE + 0x60 + 11) -#define AT91C_PIN_PD12 (PIN_BASE + 0x60 + 12) -#define AT91C_PIN_PD13 (PIN_BASE + 0x60 + 13) -#define AT91C_PIN_PD14 (PIN_BASE + 0x60 + 14) -#define AT91C_PIN_PD15 (PIN_BASE + 0x60 + 15) -#define AT91C_PIN_PD16 (PIN_BASE + 0x60 + 16) -#define AT91C_PIN_PD17 (PIN_BASE + 0x60 + 17) -#define AT91C_PIN_PD18 (PIN_BASE + 0x60 + 18) -#define AT91C_PIN_PD19 (PIN_BASE + 0x60 + 19) -#define AT91C_PIN_PD20 (PIN_BASE + 0x60 + 20) -#define AT91C_PIN_PD21 (PIN_BASE + 0x60 + 21) -#define AT91C_PIN_PD22 (PIN_BASE + 0x60 + 22) -#define AT91C_PIN_PD23 (PIN_BASE + 0x60 + 23) -#define AT91C_PIN_PD24 (PIN_BASE + 0x60 + 24) -#define AT91C_PIN_PD25 (PIN_BASE + 0x60 + 25) -#define AT91C_PIN_PD26 (PIN_BASE + 0x60 + 26) -#define AT91C_PIN_PD27 (PIN_BASE + 0x60 + 27) -#define AT91C_PIN_PD28 (PIN_BASE + 0x60 + 28) -#define AT91C_PIN_PD29 (PIN_BASE + 0x60 + 29) -#define AT91C_PIN_PD30 (PIN_BASE + 0x60 + 30) -#define AT91C_PIN_PD31 (PIN_BASE + 0x60 + 31) +#define AT91C_PIN_PD0 (PIN_BASE + 0x60 + 0) +#define AT91C_PIN_PD1 (PIN_BASE + 0x60 + 1) +#define AT91C_PIN_PD2 (PIN_BASE + 0x60 + 2) +#define AT91C_PIN_PD3 (PIN_BASE + 0x60 + 3) +#define AT91C_PIN_PD4 (PIN_BASE + 0x60 + 4) +#define AT91C_PIN_PD5 (PIN_BASE + 0x60 + 5) +#define AT91C_PIN_PD6 (PIN_BASE + 0x60 + 6) +#define AT91C_PIN_PD7 (PIN_BASE + 0x60 + 7) +#define AT91C_PIN_PD8 (PIN_BASE + 0x60 + 8) +#define AT91C_PIN_PD9 (PIN_BASE + 0x60 + 9) +#define AT91C_PIN_PD10 (PIN_BASE + 0x60 + 10) +#define AT91C_PIN_PD11 (PIN_BASE + 0x60 + 11) +#define AT91C_PIN_PD12 (PIN_BASE + 0x60 + 12) +#define AT91C_PIN_PD13 (PIN_BASE + 0x60 + 13) +#define AT91C_PIN_PD14 (PIN_BASE + 0x60 + 14) +#define AT91C_PIN_PD15 (PIN_BASE + 0x60 + 15) +#define AT91C_PIN_PD16 (PIN_BASE + 0x60 + 16) +#define AT91C_PIN_PD17 (PIN_BASE + 0x60 + 17) +#define AT91C_PIN_PD18 (PIN_BASE + 0x60 + 18) +#define AT91C_PIN_PD19 (PIN_BASE + 0x60 + 19) +#define AT91C_PIN_PD20 (PIN_BASE + 0x60 + 20) +#define AT91C_PIN_PD21 (PIN_BASE + 0x60 + 21) +#define AT91C_PIN_PD22 (PIN_BASE + 0x60 + 22) +#define AT91C_PIN_PD23 (PIN_BASE + 0x60 + 23) +#define AT91C_PIN_PD24 (PIN_BASE + 0x60 + 24) +#define AT91C_PIN_PD25 (PIN_BASE + 0x60 + 25) +#define AT91C_PIN_PD26 (PIN_BASE + 0x60 + 26) +#define AT91C_PIN_PD27 (PIN_BASE + 0x60 + 27) +#define AT91C_PIN_PD28 (PIN_BASE + 0x60 + 28) +#define AT91C_PIN_PD29 (PIN_BASE + 0x60 + 29) +#define AT91C_PIN_PD30 (PIN_BASE + 0x60 + 30) +#define AT91C_PIN_PD31 (PIN_BASE + 0x60 + 31) -#define AT91C_PIN_PE0 (PIN_BASE + 0x80 + 0) -#define AT91C_PIN_PE1 (PIN_BASE + 0x80 + 1) -#define AT91C_PIN_PE2 (PIN_BASE + 0x80 + 2) -#define AT91C_PIN_PE3 (PIN_BASE + 0x80 + 3) -#define AT91C_PIN_PE4 (PIN_BASE + 0x80 + 4) -#define AT91C_PIN_PE5 (PIN_BASE + 0x80 + 5) -#define AT91C_PIN_PE6 (PIN_BASE + 0x80 + 6) -#define AT91C_PIN_PE7 (PIN_BASE + 0x80 + 7) -#define AT91C_PIN_PE8 (PIN_BASE + 0x80 + 8) -#define AT91C_PIN_PE9 (PIN_BASE + 0x80 + 9) -#define AT91C_PIN_PE10 (PIN_BASE + 0x80 + 10) -#define AT91C_PIN_PE11 (PIN_BASE + 0x80 + 11) -#define AT91C_PIN_PE12 (PIN_BASE + 0x80 + 12) -#define AT91C_PIN_PE13 (PIN_BASE + 0x80 + 13) -#define AT91C_PIN_PE14 (PIN_BASE + 0x80 + 14) -#define AT91C_PIN_PE15 (PIN_BASE + 0x80 + 15) -#define AT91C_PIN_PE16 (PIN_BASE + 0x80 + 16) -#define AT91C_PIN_PE17 (PIN_BASE + 0x80 + 17) -#define AT91C_PIN_PE18 (PIN_BASE + 0x80 + 18) -#define AT91C_PIN_PE19 (PIN_BASE + 0x80 + 19) -#define AT91C_PIN_PE20 (PIN_BASE + 0x80 + 20) -#define AT91C_PIN_PE21 (PIN_BASE + 0x80 + 21) -#define AT91C_PIN_PE22 (PIN_BASE + 0x80 + 22) -#define AT91C_PIN_PE23 (PIN_BASE + 0x80 + 23) -#define AT91C_PIN_PE24 (PIN_BASE + 0x80 + 24) -#define AT91C_PIN_PE25 (PIN_BASE + 0x80 + 25) -#define AT91C_PIN_PE26 (PIN_BASE + 0x80 + 26) -#define AT91C_PIN_PE27 (PIN_BASE + 0x80 + 27) -#define AT91C_PIN_PE28 (PIN_BASE + 0x80 + 28) -#define AT91C_PIN_PE29 (PIN_BASE + 0x80 + 29) -#define AT91C_PIN_PE30 (PIN_BASE + 0x80 + 30) -#define AT91C_PIN_PE31 (PIN_BASE + 0x80 + 31) +#define AT91C_PIN_PE0 (PIN_BASE + 0x80 + 0) +#define AT91C_PIN_PE1 (PIN_BASE + 0x80 + 1) +#define AT91C_PIN_PE2 (PIN_BASE + 0x80 + 2) +#define AT91C_PIN_PE3 (PIN_BASE + 0x80 + 3) +#define AT91C_PIN_PE4 (PIN_BASE + 0x80 + 4) +#define AT91C_PIN_PE5 (PIN_BASE + 0x80 + 5) +#define AT91C_PIN_PE6 (PIN_BASE + 0x80 + 6) +#define AT91C_PIN_PE7 (PIN_BASE + 0x80 + 7) +#define AT91C_PIN_PE8 (PIN_BASE + 0x80 + 8) +#define AT91C_PIN_PE9 (PIN_BASE + 0x80 + 9) +#define AT91C_PIN_PE10 (PIN_BASE + 0x80 + 10) +#define AT91C_PIN_PE11 (PIN_BASE + 0x80 + 11) +#define AT91C_PIN_PE12 (PIN_BASE + 0x80 + 12) +#define AT91C_PIN_PE13 (PIN_BASE + 0x80 + 13) +#define AT91C_PIN_PE14 (PIN_BASE + 0x80 + 14) +#define AT91C_PIN_PE15 (PIN_BASE + 0x80 + 15) +#define AT91C_PIN_PE16 (PIN_BASE + 0x80 + 16) +#define AT91C_PIN_PE17 (PIN_BASE + 0x80 + 17) +#define AT91C_PIN_PE18 (PIN_BASE + 0x80 + 18) +#define AT91C_PIN_PE19 (PIN_BASE + 0x80 + 19) +#define AT91C_PIN_PE20 (PIN_BASE + 0x80 + 20) +#define AT91C_PIN_PE21 (PIN_BASE + 0x80 + 21) +#define AT91C_PIN_PE22 (PIN_BASE + 0x80 + 22) +#define AT91C_PIN_PE23 (PIN_BASE + 0x80 + 23) +#define AT91C_PIN_PE24 (PIN_BASE + 0x80 + 24) +#define AT91C_PIN_PE25 (PIN_BASE + 0x80 + 25) +#define AT91C_PIN_PE26 (PIN_BASE + 0x80 + 26) +#define AT91C_PIN_PE27 (PIN_BASE + 0x80 + 27) +#define AT91C_PIN_PE28 (PIN_BASE + 0x80 + 28) +#define AT91C_PIN_PE29 (PIN_BASE + 0x80 + 29) +#define AT91C_PIN_PE30 (PIN_BASE + 0x80 + 30) +#define AT91C_PIN_PE31 (PIN_BASE + 0x80 + 31) rt_inline rt_uint32_t gpio_to_irq(rt_uint32_t gpio) { - return gpio; + return gpio; } #endif diff --git a/bsp/at91sam9g45/platform/interrupt.c b/bsp/at91sam9g45/platform/interrupt.c index 9f7cabf3f8..c8afc998f1 100644 --- a/bsp/at91sam9g45/platform/interrupt.c +++ b/bsp/at91sam9g45/platform/interrupt.c @@ -1,21 +1,7 @@ /* - * File : interrupt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -26,7 +12,7 @@ #include "at91sam9g45.h" #include "interrupt.h" -#define AIC_IRQS 32 +#define AIC_IRQS 32 #define MAX_HANDLERS (AIC_IRQS + PIN_IRQS) extern rt_uint32_t rt_interrupt_nest; @@ -101,17 +87,17 @@ rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector, void *param) rt_isr_handler_t at91_gpio_irq_handle(rt_uint32_t bank, void *param) { rt_uint32_t isr, irq_n; - AT91PS_PIO pio; + AT91PS_PIO pio; void *parameter; switch (bank) { - case 0: pio = AT91C_BASE_PIOA; break; - case 1: pio = AT91C_BASE_PIOB; break; - case 2: pio = AT91C_BASE_PIOC; break; - case 3: pio = AT91C_BASE_PIOD; break; - case 4: pio = AT91C_BASE_PIOE; break; - default: return RT_NULL; + case 0: pio = AT91C_BASE_PIOA; break; + case 1: pio = AT91C_BASE_PIOB; break; + case 2: pio = AT91C_BASE_PIOC; break; + case 3: pio = AT91C_BASE_PIOD; break; + case 4: pio = AT91C_BASE_PIOE; break; + default: return RT_NULL; } irq_n = AIC_IRQS + 32*bank; isr = readl(pio->PIO_ISR); @@ -133,21 +119,21 @@ rt_isr_handler_t at91_gpio_irq_handle(rt_uint32_t bank, void *param) unsigned int SpuriousCount = 0; static void DefaultSpuriousHandler( void ) { - SpuriousCount++; - rt_kprintf("Spurious interrupt %d occured!!!\n", SpuriousCount); - return ; + SpuriousCount++; + rt_kprintf("Spurious interrupt %d occured!!!\n", SpuriousCount); + return ; } static void DefaultFiqHandler(void) { - rt_kprintf("Unhandled FIQ occured!!!\n"); - while (1); + rt_kprintf("Unhandled FIQ occured!!!\n"); + while (1); } static void DefaultIrqHandler(void) { - rt_kprintf("Unhandled IRQ %d occured!!!\n", AT91C_BASE_AIC->AIC_ISR); - while (1); + rt_kprintf("Unhandled IRQ %d occured!!!\n", AT91C_BASE_AIC->AIC_ISR); + while (1); } /* @@ -345,7 +331,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, irq_desc[vector].param = param; #ifdef RT_USING_INTERRUPT_INFO rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name); - irq_desc[vector].counter = 0; + irq_desc[vector].counter = 0; #endif } } @@ -446,16 +432,16 @@ void rt_interrupt_dispatch(rt_uint32_t fiq_irq) #ifdef RT_USING_INTERRUPT_INFO void list_irq(void) { - int irq; + int irq; - rt_kprintf("number\tcount\tname\n"); - for (irq = 0; irq < MAX_HANDLERS; irq++) - { - if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default"))) - { - rt_kprintf("%02ld: %10ld %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name); - } - } + rt_kprintf("number\tcount\tname\n"); + for (irq = 0; irq < MAX_HANDLERS; irq++) + { + if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default"))) + { + rt_kprintf("%02ld: %10ld %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name); + } + } } #include diff --git a/bsp/at91sam9g45/platform/interrupt.h b/bsp/at91sam9g45/platform/interrupt.h index 7780e7a3a8..0375164e00 100644 --- a/bsp/at91sam9g45/platform/interrupt.h +++ b/bsp/at91sam9g45/platform/interrupt.h @@ -1,21 +1,7 @@ /* - * File : interrupt.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/at91sam9g45/platform/io.h b/bsp/at91sam9g45/platform/io.h index 80919c52cb..b3a9188299 100644 --- a/bsp/at91sam9g45/platform/io.h +++ b/bsp/at91sam9g45/platform/io.h @@ -1,21 +1,7 @@ /* - * File : io.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -25,15 +11,15 @@ #ifndef __ASM_ARCH_IO_H #define __ASM_ARCH_IO_H -#define IO_SPACE_LIMIT 0xFFFFFFFF +#define IO_SPACE_LIMIT 0xFFFFFFFF -#define readb(a) (*(volatile unsigned char *)(a)) -#define readw(a) (*(volatile unsigned short *)(a)) -#define readl(a) (*(volatile unsigned int *)(a)) +#define readb(a) (*(volatile unsigned char *)(a)) +#define readw(a) (*(volatile unsigned short *)(a)) +#define readl(a) (*(volatile unsigned int *)(a)) -#define writeb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define writew(v,a) (*(volatile unsigned short *)(a) = (v)) -#define writel(v,a) (*(volatile unsigned int *)(a) = (v)) +#define writeb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define writew(v,a) (*(volatile unsigned short *)(a) = (v)) +#define writel(v,a) (*(volatile unsigned int *)(a) = (v)) #endif diff --git a/bsp/at91sam9g45/platform/irq.h b/bsp/at91sam9g45/platform/irq.h index fe1fea41d0..76d4200d3b 100644 --- a/bsp/at91sam9g45/platform/irq.h +++ b/bsp/at91sam9g45/platform/irq.h @@ -1,27 +1,13 @@ /* - * File : irq.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2011-01-13 weety first version */ - + #ifndef __IRQ_H__ #define __IRQ_H__ @@ -32,18 +18,18 @@ extern "C" { /* * IRQ line status. * - * Bits 0-7 are reserved + * Bits 0-7 are reserved * * IRQ types */ -#define IRQ_TYPE_NONE 0x00000000 /* Default, unspecified type */ -#define IRQ_TYPE_EDGE_RISING 0x00000001 /* Edge rising type */ -#define IRQ_TYPE_EDGE_FALLING 0x00000002 /* Edge falling type */ +#define IRQ_TYPE_NONE 0x00000000 /* Default, unspecified type */ +#define IRQ_TYPE_EDGE_RISING 0x00000001 /* Edge rising type */ +#define IRQ_TYPE_EDGE_FALLING 0x00000002 /* Edge falling type */ #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) -#define IRQ_TYPE_LEVEL_HIGH 0x00000004 /* Level high type */ -#define IRQ_TYPE_LEVEL_LOW 0x00000008 /* Level low type */ -#define IRQ_TYPE_SENSE_MASK 0x0000000f /* Mask of the above */ -#define IRQ_TYPE_PROBE 0x00000010 /* Probing in progress */ +#define IRQ_TYPE_LEVEL_HIGH 0x00000004 /* Level high type */ +#define IRQ_TYPE_LEVEL_LOW 0x00000008 /* Level low type */ +#define IRQ_TYPE_SENSE_MASK 0x0000000f /* Mask of the above */ +#define IRQ_TYPE_PROBE 0x00000010 /* Probing in progress */ #ifdef __cplusplus } diff --git a/bsp/at91sam9g45/platform/reset.c b/bsp/at91sam9g45/platform/reset.c index 2e7bec1e5d..8abbf7a9fb 100644 --- a/bsp/at91sam9g45/platform/reset.c +++ b/bsp/at91sam9g45/platform/reset.c @@ -1,21 +1,7 @@ /* - * File : reset.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -33,12 +19,12 @@ void machine_reset(void) { - AT91C_BASE_RSTC->RSTC_RCR = AT91C_RSTC_KEY | AT91C_RSTC_PROCRST | AT91C_RSTC_PERRST; + AT91C_BASE_RSTC->RSTC_RCR = AT91C_RSTC_KEY | AT91C_RSTC_PROCRST | AT91C_RSTC_PERRST; } void machine_shutdown(void) { - AT91C_BASE_SHDWC->SHDWC_SHCR = AT91C_SHDWC_KEY | AT91C_SHDWC_SHDW; + AT91C_BASE_SHDWC->SHDWC_SHCR = AT91C_SHDWC_KEY | AT91C_SHDWC_SHDW; } #ifdef RT_USING_FINSH @@ -49,14 +35,14 @@ FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, reset, restart the system); #ifdef FINSH_USING_MSH int cmd_reset(int argc, char** argv) { - rt_hw_cpu_reset(); - return 0; + rt_hw_cpu_reset(); + return 0; } int cmd_shutdown(int argc, char** argv) { - rt_hw_cpu_shutdown(); - return 0; + rt_hw_cpu_shutdown(); + return 0; } FINSH_FUNCTION_EXPORT_ALIAS(cmd_reset, __cmd_reset, restart the system.); diff --git a/bsp/at91sam9g45/platform/rt_low_level_init.c b/bsp/at91sam9g45/platform/rt_low_level_init.c index 5df468d771..b76b84fe5c 100644 --- a/bsp/at91sam9g45/platform/rt_low_level_init.c +++ b/bsp/at91sam9g45/platform/rt_low_level_init.c @@ -1,29 +1,15 @@ /* - * File : rt_low_level_init.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2015-04-14 ArdaFu first version */ - + /* write register a=address, v=value */ -#define write_reg(a,v) (*(volatile unsigned int *)(a) = (v)) +#define write_reg(a,v) (*(volatile unsigned int *)(a) = (v)) /* Processor Reset */ #define AT91C_RSTC_PROCRST (1 << 0) #define AT91C_RSTC_PERRST (1 << 2) diff --git a/bsp/at91sam9g45/platform/rt_low_level_init.h b/bsp/at91sam9g45/platform/rt_low_level_init.h index 86dcfb59dc..c79adf5284 100644 --- a/bsp/at91sam9g45/platform/rt_low_level_init.h +++ b/bsp/at91sam9g45/platform/rt_low_level_init.h @@ -1,21 +1,7 @@ /* - * File : rt_low_level_init.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -23,7 +9,7 @@ */ #ifndef __RT_LOW_LEVEL_INIT_H__ #define __RT_LOW_LEVEL_INIT_H__ - + /*-------- Stack size of CPU modes -------------------------------------------*/ #define UND_STK_SIZE 512 #define SVC_STK_SIZE 4096 diff --git a/bsp/at91sam9g45/platform/system_clock.c b/bsp/at91sam9g45/platform/system_clock.c index 59c3c320ab..551daf31e4 100644 --- a/bsp/at91sam9g45/platform/system_clock.c +++ b/bsp/at91sam9g45/platform/system_clock.c @@ -1,21 +1,7 @@ /* - * File : clock.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -28,236 +14,236 @@ static rt_list_t clocks; struct clk { - char name[32]; - rt_uint32_t rate_hz; - struct clk *parent; - rt_list_t node; + char name[32]; + rt_uint32_t rate_hz; + struct clk *parent; + rt_list_t node; }; static struct clk clk32k = { - "clk32k", - AT91C_SLOW_CLOCK, - RT_NULL, - {RT_NULL, RT_NULL}, + "clk32k", + AT91C_SLOW_CLOCK, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk main_clk = { - "main", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, + "main", + 0, + RT_NULL, + {RT_NULL, RT_NULL}, }; static struct clk plla = { - "plla", - 0, - &main_clk, - {RT_NULL, RT_NULL}, + "plla", + 0, + &main_clk, + {RT_NULL, RT_NULL}, }; static struct clk mck = { - "mck", - 0, - NULL, - {RT_NULL, RT_NULL}, + "mck", + 0, + NULL, + {RT_NULL, RT_NULL}, }; static struct clk upllck = { - "upllck", - 480*1000*1000, - &main_clk, - {RT_NULL, RT_NULL}, + "upllck", + 480*1000*1000, + &main_clk, + {RT_NULL, RT_NULL}, }; static struct clk *const standard_pmc_clocks[] = { - /* four primary clocks */ - &clk32k, - &main_clk, - &plla, + /* four primary clocks */ + &clk32k, + &main_clk, + &plla, - /* MCK */ - &mck + /* MCK */ + &mck }; /* clocks cannot be de-registered no refcounting necessary */ struct clk *clk_get(const char *id) { - struct clk *clk; - rt_list_t *list; - - for (list = (&clocks)->next; list != &clocks; list = list->next) - { - clk = (struct clk *)rt_list_entry(list, struct clk, node); - if (rt_strcmp(id, clk->name) == 0) - return clk; - } + struct clk *clk; + rt_list_t *list; - return RT_NULL; + for (list = (&clocks)->next; list != &clocks; list = list->next) + { + clk = (struct clk *)rt_list_entry(list, struct clk, node); + if (rt_strcmp(id, clk->name) == 0) + return clk; + } + + return RT_NULL; } rt_uint32_t clk_get_rate(struct clk *clk) { - rt_uint32_t rate; + rt_uint32_t rate; - for (;;) { - rate = clk->rate_hz; - if (rate || !clk->parent) - break; - clk = clk->parent; - } - return rate; + for (;;) { + rate = clk->rate_hz; + if (rate || !clk->parent) + break; + clk = clk->parent; + } + return rate; } static void at91_upllck_init(rt_uint32_t main_clock) { - // EHCI USB use fixed 480MHz clock + // EHCI USB use fixed 480MHz clock } static struct clk *at91_css_to_clk(unsigned long css) { - switch (css) { - case AT91C_PMC_CSS_SLOW_CLK: - return &clk32k; - case AT91C_PMC_CSS_MAIN_CLK: - return &main_clk; - case AT91C_PMC_CSS_PLLA_CLK: - return &plla; - case AT91C_PMC_CSS_UPLL_CLK: - return &upllck; - } + switch (css) { + case AT91C_PMC_CSS_SLOW_CLK: + return &clk32k; + case AT91C_PMC_CSS_MAIN_CLK: + return &main_clk; + case AT91C_PMC_CSS_PLLA_CLK: + return &plla; + case AT91C_PMC_CSS_UPLL_CLK: + return &upllck; + } - return RT_NULL; + return RT_NULL; } // TODO: how to auto-set register value by OSC and MCK /* Settings at 400/133MHz */ // In datasheet, ATMEL says 12MHz main crystal startup time less than 2ms, so we // configure OSC startup timeout to 64*8/32768=15.6ms, should enough -#define BOARD_OSCOUNT (AT91C_CKGR_OSCOUNT & (64 << 8)) +#define BOARD_OSCOUNT (AT91C_CKGR_OSCOUNT & (64 << 8)) // MAINCK => Divider(DIVA) => PLLA(MULA, OUTA) => /1/2 Divider(PLLADIV2) => PLLACK -// pls. refer to doc6438G figure 24-6 on pg294. ICPLLA in reg PMC_PLLICPR +// pls. refer to doc6438G figure 24-6 on pg294. ICPLLA in reg PMC_PLLICPR // 12MHz / 3 * (199 + 1) = 800MHz // OUTA/ICPLLA can as ICPLLA:OUTA[1]:OUTA[0] = (800-PLLAOUT(MHz))/50 // PLLACOUNT field occupy bit[13:8], max value is 0x3F, then about 19.2ms -#define BOARD_CKGR_PLLA (AT91C_CKGR_SRCA | AT91C_CKGR_OUTA_0) -#define BOARD_PLLACOUNT (0x3F << 8) -#define BOARD_MULA (AT91C_CKGR_MULA & (199 << 16)) -#define BOARD_DIVA (AT91C_CKGR_DIVA & 3) +#define BOARD_CKGR_PLLA (AT91C_CKGR_SRCA | AT91C_CKGR_OUTA_0) +#define BOARD_PLLACOUNT (0x3F << 8) +#define BOARD_MULA (AT91C_CKGR_MULA & (199 << 16)) +#define BOARD_DIVA (AT91C_CKGR_DIVA & 3) // Clock Source => select(CCS) => Prescaler(PRES) => Master Clock Divider(MDIV) => MCK // => Processor Clock Divider => PCK // Master clock can refer to doc6438G figure 25-2 on pg298 // PLLADIV2=1(div 2, 400MHz), PRES=0(no div, 400MHz), // MDIV=3(Master Clock divided by 3, 133MHz), CSS=0(still Slow Clock) -#define BOARD_PRESCALER (0x00001300) //400/133MHz +#define BOARD_PRESCALER (0x00001300) //400/133MHz -#define MHz(n) ((n) * 1000 * 1000) -#define OSC_FREQ MHz(12) -#define PLLA_FREQ MHz(800) +#define MHz(n) ((n) * 1000 * 1000) +#define OSC_FREQ MHz(12) +#define PLLA_FREQ MHz(800) static void at91_plla_init(void) { - rt_uint32_t pllar, mckr; + rt_uint32_t pllar, mckr; - // Code refer to doc6438G, 25.10 Programming Sequence - /* Initialize main oscillator - ****************************/ - // enable main OSC and wait OSC startup time timeout. - AT91C_BASE_PMC->PMC_MOR = BOARD_OSCOUNT | AT91C_CKGR_MOSCEN; - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS)); + // Code refer to doc6438G, 25.10 Programming Sequence + /* Initialize main oscillator + ****************************/ + // enable main OSC and wait OSC startup time timeout. + AT91C_BASE_PMC->PMC_MOR = BOARD_OSCOUNT | AT91C_CKGR_MOSCEN; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS)); - /* Initialize PLLA, Set PLL to 800MHz and wait PLL stable */ - pllar = (MHz(800) - PLLA_FREQ) / MHz(50); // please refer to Table 46-15 of doc 6438G - AT91C_BASE_PMC->PMC_PLLICPR = (pllar >> 2) & 1; // ICPLLA - pllar = (pllar & 3) << 14; // OUTA - pllar |= BOARD_DIVA; // PLLA input clock as 4MHz - pllar |= BOARD_MULA; // PLLA output clock as 800MHz - pllar |= BOARD_PLLACOUNT; - pllar |= AT91C_CKGR_SRCA; // I don't known what means, but seems must set it - AT91C_BASE_PMC->PMC_PLLAR = pllar; + /* Initialize PLLA, Set PLL to 800MHz and wait PLL stable */ + pllar = (MHz(800) - PLLA_FREQ) / MHz(50); // please refer to Table 46-15 of doc 6438G + AT91C_BASE_PMC->PMC_PLLICPR = (pllar >> 2) & 1; // ICPLLA + pllar = (pllar & 3) << 14; // OUTA + pllar |= BOARD_DIVA; // PLLA input clock as 4MHz + pllar |= BOARD_MULA; // PLLA output clock as 800MHz + pllar |= BOARD_PLLACOUNT; + pllar |= AT91C_CKGR_SRCA; // I don't known what means, but seems must set it + AT91C_BASE_PMC->PMC_PLLAR = pllar; - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA)); + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA)); - /* Wait for the master clock if it was already initialized */ - // make sure Master clock in READY status before operate it - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)); + /* Wait for the master clock if it was already initialized */ + // make sure Master clock in READY status before operate it + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)); - /* Switch to fast clock - **********************/ - /* setup main clock divisor and prescaler, 400MHz/133MHz, but don't switch */ - mckr = AT91C_BASE_PMC->PMC_MCKR; - if ((mckr & AT91C_PMC_MDIV) != (BOARD_PRESCALER & AT91C_PMC_MDIV)) - { - mckr = (mckr & ~(unsigned int)AT91C_PMC_MDIV) | (BOARD_PRESCALER & AT91C_PMC_MDIV); - AT91C_BASE_PMC->PMC_MCKR = mckr; - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)); - } + /* Switch to fast clock + **********************/ + /* setup main clock divisor and prescaler, 400MHz/133MHz, but don't switch */ + mckr = AT91C_BASE_PMC->PMC_MCKR; + if ((mckr & AT91C_PMC_MDIV) != (BOARD_PRESCALER & AT91C_PMC_MDIV)) + { + mckr = (mckr & ~(unsigned int)AT91C_PMC_MDIV) | (BOARD_PRESCALER & AT91C_PMC_MDIV); + AT91C_BASE_PMC->PMC_MCKR = mckr; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)); + } - /* Switch to PLL + prescaler, now Switch to PLLA as source, run on the fly */ - if ((mckr & AT91C_PMC_CSS) != AT91C_PMC_CSS_PLLA_CLK) - { - mckr = (mckr & ~(unsigned int)AT91C_PMC_CSS) | AT91C_PMC_CSS_PLLA_CLK; - AT91C_BASE_PMC->PMC_MCKR = mckr; - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)); - } + /* Switch to PLL + prescaler, now Switch to PLLA as source, run on the fly */ + if ((mckr & AT91C_PMC_CSS) != AT91C_PMC_CSS_PLLA_CLK) + { + mckr = (mckr & ~(unsigned int)AT91C_PMC_CSS) | AT91C_PMC_CSS_PLLA_CLK; + AT91C_BASE_PMC->PMC_MCKR = mckr; + while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)); + } - plla.rate_hz = PLLA_FREQ; + plla.rate_hz = PLLA_FREQ; } - + #define false 0 #define true 1 int at91_clock_init(rt_uint32_t main_clock) { - unsigned tmp, freq, mckr, mdiv; - int i; + unsigned tmp, freq, mckr, mdiv; + int i; - /* - * When the bootloader initialized the main oscillator correctly, - * there's no problem using the cycle counter. But if it didn't, - * or when using oscillator bypass mode, we must be told the speed - * of the main clock. - */ - if (!main_clock) { - do { - tmp = readl(AT91C_CKGR_MCFR); - } while (!(tmp & AT91C_CKGR_MAINRDY)); - main_clock = (tmp & AT91C_CKGR_MAINF) * (AT91C_SLOW_CLOCK / 16); - } - main_clk.rate_hz = main_clock; + /* + * When the bootloader initialized the main oscillator correctly, + * there's no problem using the cycle counter. But if it didn't, + * or when using oscillator bypass mode, we must be told the speed + * of the main clock. + */ + if (!main_clock) { + do { + tmp = readl(AT91C_CKGR_MCFR); + } while (!(tmp & AT91C_CKGR_MAINRDY)); + main_clock = (tmp & AT91C_CKGR_MAINF) * (AT91C_SLOW_CLOCK / 16); + } + main_clk.rate_hz = main_clock; - at91_plla_init(); + at91_plla_init(); - at91_upllck_init(main_clock); + at91_upllck_init(main_clock); - /* - * MCK and CPU derive from one of those primary clocks. - * For now, assume this parentage won't change. - */ - mckr = readl(AT91C_PMC_MCKR); - mck.parent = at91_css_to_clk(mckr & AT91C_PMC_CSS); - freq = mck.parent->rate_hz; - freq /= (1 << ((mckr & AT91C_PMC_PRES) >> 2)); /* prescale */ - mdiv = 1 << ((mckr & AT91C_PMC_MDIV) >> 8); - if (mdiv == 8) mdiv = 3; - freq /= mdiv; /* mdiv */ - if (mckr & AT91C_PMC_PLLADIV2) freq /= 2; /* plla_div2 */ - mck.rate_hz = freq; + /* + * MCK and CPU derive from one of those primary clocks. + * For now, assume this parentage won't change. + */ + mckr = readl(AT91C_PMC_MCKR); + mck.parent = at91_css_to_clk(mckr & AT91C_PMC_CSS); + freq = mck.parent->rate_hz; + freq /= (1 << ((mckr & AT91C_PMC_PRES) >> 2)); /* prescale */ + mdiv = 1 << ((mckr & AT91C_PMC_MDIV) >> 8); + if (mdiv == 8) mdiv = 3; + freq /= mdiv; /* mdiv */ + if (mckr & AT91C_PMC_PLLADIV2) freq /= 2; /* plla_div2 */ + mck.rate_hz = freq; - /* Register the PMC's standard clocks */ - rt_list_init(&clocks); - for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) - rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node); + /* Register the PMC's standard clocks */ + rt_list_init(&clocks); + for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) + rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node); - rt_list_insert_after(&clocks, &upllck.node); + rt_list_insert_after(&clocks, &upllck.node); - /* MCK and CPU clock are "always on" */ - //clk_enable(&mck); + /* MCK and CPU clock are "always on" */ + //clk_enable(&mck); - /*rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", - freq / 1000000, (unsigned) mck.rate_hz / 1000000, - (unsigned) main_clock / 1000000, - ((unsigned) main_clock % 1000000) / 1000);*///cause blocked + /*rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", + freq / 1000000, (unsigned) mck.rate_hz / 1000000, + (unsigned) main_clock / 1000000, + ((unsigned) main_clock % 1000000) / 1000);*///cause blocked - return 0; + return 0; } /** @@ -265,6 +251,6 @@ int at91_clock_init(rt_uint32_t main_clock) */ void rt_hw_clock_init(void) { - at91_clock_init(MHz(12)); + at91_clock_init(MHz(12)); } diff --git a/bsp/avr32uc3b0/application.c b/bsp/avr32uc3b0/application.c index 4853570b19..6b87b226f4 100644 --- a/bsp/avr32uc3b0/application.c +++ b/bsp/avr32uc3b0/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -56,7 +52,7 @@ int rt_application_init() { /* create led1 thread */ rt_thread_init(&thread_led1, - "led1", + "led1", rt_thread_entry_led1, RT_NULL, &thread_led1_stack[0], diff --git a/bsp/avr32uc3b0/board.c b/bsp/avr32uc3b0/board.c index bc510b1ed5..226e59e551 100644 --- a/bsp/avr32uc3b0/board.c +++ b/bsp/avr32uc3b0/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -20,11 +16,11 @@ #include "intc.h" #include "serial.h" -#define FOSC0 12000000 -#define FCPU 60000000 -#define FHSB FCPU -#define FPBA FCPU -#define FPBB FCPU +#define FOSC0 12000000 +#define FCPU 60000000 +#define FHSB FCPU +#define FPBA FCPU +#define FPBB FCPU extern void rt_hw_serial_isr(void); extern void rt_hw_usart_init(void); @@ -34,10 +30,10 @@ extern void rt_hw_usart_init(void); */ static void rt_hw_timer_handler(void) { - // Clears the interrupt request. - Set_system_register(AVR32_COMPARE, FCPU / RT_TICK_PER_SECOND); + // Clears the interrupt request. + Set_system_register(AVR32_COMPARE, FCPU / RT_TICK_PER_SECOND); - rt_tick_increase(); + rt_tick_increase(); } /** @@ -45,35 +41,35 @@ static void rt_hw_timer_handler(void) */ static void peripherals_init(void) { - /* - * PM initialization: OSC0 = 12MHz XTAL, PLL0 = 60MHz System Clock - */ - pm_freq_param_t pm_freq_param = - { - .cpu_f = FCPU, - .pba_f = FPBA, - .osc0_f = FOSC0, - .osc0_startup = AVR32_PM_OSCCTRL0_STARTUP_2048_RCOSC - }; - pm_configure_clocks(&pm_freq_param); + /* + * PM initialization: OSC0 = 12MHz XTAL, PLL0 = 60MHz System Clock + */ + pm_freq_param_t pm_freq_param = + { + .cpu_f = FCPU, + .pba_f = FPBA, + .osc0_f = FOSC0, + .osc0_startup = AVR32_PM_OSCCTRL0_STARTUP_2048_RCOSC + }; + pm_configure_clocks(&pm_freq_param); - /* - * USART1 initialization - */ - gpio_enable_module_pin(AVR32_USART1_TXD_0_1_PIN, AVR32_USART1_TXD_0_1_FUNCTION); - gpio_enable_module_pin(AVR32_USART1_RXD_0_1_PIN, AVR32_USART1_RXD_0_1_FUNCTION); - static const usart_options_t usartOptions = { - .baudrate = 115200, - .charlength = 8, - .paritytype = USART_NO_PARITY, - .stopbits = USART_1_STOPBIT, - .channelmode = USART_NORMAL_CHMODE - }; - usart_init_rs232(&AVR32_USART1, &usartOptions, FCPU); + /* + * USART1 initialization + */ + gpio_enable_module_pin(AVR32_USART1_TXD_0_1_PIN, AVR32_USART1_TXD_0_1_FUNCTION); + gpio_enable_module_pin(AVR32_USART1_RXD_0_1_PIN, AVR32_USART1_RXD_0_1_FUNCTION); + static const usart_options_t usartOptions = { + .baudrate = 115200, + .charlength = 8, + .paritytype = USART_NO_PARITY, + .stopbits = USART_1_STOPBIT, + .channelmode = USART_NORMAL_CHMODE + }; + usart_init_rs232(&AVR32_USART1, &usartOptions, FCPU); - INTC_init_interrupts(); - INTC_register_interrupt(&rt_hw_serial_isr, AVR32_USART1_IRQ, AVR32_INTC_INT0); - AVR32_USART1.ier = AVR32_USART_IER_RXRDY_MASK; + INTC_init_interrupts(); + INTC_register_interrupt(&rt_hw_serial_isr, AVR32_USART1_IRQ, AVR32_INTC_INT0); + AVR32_USART1.ier = AVR32_USART_IER_RXRDY_MASK; } /** @@ -81,21 +77,21 @@ static void peripherals_init(void) */ static void cpu_counter_init(void) { - INTC_register_interrupt(&rt_hw_timer_handler, AVR32_CORE_COMPARE_IRQ, AVR32_INTC_INT3); - Set_system_register(AVR32_COMPARE, FCPU / RT_TICK_PER_SECOND); - Set_system_register(AVR32_COUNT, 0); + INTC_register_interrupt(&rt_hw_timer_handler, AVR32_CORE_COMPARE_IRQ, AVR32_INTC_INT3); + Set_system_register(AVR32_COMPARE, FCPU / RT_TICK_PER_SECOND); + Set_system_register(AVR32_COUNT, 0); } void rt_hw_board_init(void) { - extern struct rt_device _rt_usart_device; - extern struct avr32_serial_device uart; + extern struct rt_device _rt_usart_device; + extern struct avr32_serial_device uart; - Disable_global_interrupt(); + Disable_global_interrupt(); - peripherals_init(); - cpu_counter_init(); + peripherals_init(); + cpu_counter_init(); - rt_hw_serial_register(&_rt_usart_device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, &uart); - rt_console_set_device("uart1"); + rt_hw_serial_register(&_rt_usart_device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, &uart); + rt_console_set_device("uart1"); } diff --git a/bsp/avr32uc3b0/rtconfig.h b/bsp/avr32uc3b0/rtconfig.h index 621ffc2af0..16e8194a89 100644 --- a/bsp/avr32uc3b0/rtconfig.h +++ b/bsp/avr32uc3b0/rtconfig.h @@ -1,11 +1,7 @@ /* - * File : rtconfig.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -16,16 +12,16 @@ #define RTCONFIG_H_ /* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 8 /* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +#define RT_ALIGN_SIZE 4 /* PRIORITY_MAX*/ -#define RT_THREAD_PRIORITY_MAX 32 +#define RT_THREAD_PRIORITY_MAX 32 /* Tick per Second*/ -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 100 /* SECTION: RT_DEBUG */ /* Thread Debug*/ @@ -73,7 +69,7 @@ /* SECTION: Console options */ /* the buffer size of console*/ #define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 /* SECTION: FinSH shell options */ /* Using FinSH as Shell*/ @@ -88,21 +84,21 @@ #define RT_USING_DFS_ELMFAT #define RT_DFS_ELM_WORD_ACCESS -#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_DRIVES 2 /* SECTION: DFS options */ /* the max number of mounted filesystem */ -#define DFS_FILESYSTEMS_MAX 2 -/* the max number of opened files */ -#define DFS_FD_MAX 8 -/* the max number of cached sector */ -#define DFS_CACHE_MAX_NUM 4 +#define DFS_FILESYSTEMS_MAX 2 +/* the max number of opened files */ +#define DFS_FD_MAX 8 +/* the max number of cached sector */ +#define DFS_CACHE_MAX_NUM 4 /* SECTION: RT-Thread/GUI */ //#define RT_USING_RTGUI /* name length of RTGUI object */ -#define RTGUI_NAME_MAX 12 +#define RTGUI_NAME_MAX 12 /* support 16 weight font */ #define RTGUI_USING_FONT16 /* support Chinese font */ @@ -116,6 +112,6 @@ /* use mouse cursor */ /* #define RTGUI_USING_MOUSE_CURSOR */ /* default font size in RTGUI */ -#define RTGUI_DEFAULT_FONT_SIZE 16 +#define RTGUI_DEFAULT_FONT_SIZE 16 #endif /* RTCONFIG_H_ */ diff --git a/bsp/avr32uc3b0/startup.c b/bsp/avr32uc3b0/startup.c index 0411b5d1ce..efa76a4e27 100644 --- a/bsp/avr32uc3b0/startup.c +++ b/bsp/avr32uc3b0/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2010, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -25,19 +21,19 @@ extern void finsh_set_device(const char* device); int main(void) { #ifdef RT_USING_HEAP - extern void __heap_start__; - extern void __heap_end__; + extern void __heap_start__; + extern void __heap_end__; #endif - rt_hw_board_init(); - rt_system_timer_init(); + rt_hw_board_init(); + rt_system_timer_init(); #ifdef RT_USING_HEAP - rt_system_heap_init(&__heap_start__, &__heap_end__); + rt_system_heap_init(&__heap_start__, &__heap_end__); #endif - rt_system_scheduler_init(); - rt_application_init(); + rt_system_scheduler_init(); + rt_application_init(); #ifdef RT_USING_FINSH /* init finsh */ @@ -46,7 +42,7 @@ int main(void) #endif rt_thread_idle_init(); - rt_system_scheduler_start(); + rt_system_scheduler_start(); - return 0; + return 0; } diff --git a/bsp/beaglebone/applications/board.c b/bsp/beaglebone/applications/board.c index 7a7380c5f8..ff25dd7dd7 100644 --- a/bsp/beaglebone/applications/board.c +++ b/bsp/beaglebone/applications/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -49,7 +45,7 @@ static rt_uint32_t DMTIMER = 0; static void rt_hw_timer_isr(int vector, void* param) { - rt_tick_increase(); + rt_tick_increase(); DMTIMER_IRQSTATUS(TIMER_HW_BASE) = DMTIMER_IRQSTATUS_RAW_OVF_IT_FLAG; } @@ -71,73 +67,73 @@ static void timer_clk_init(void) while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & (1<<8))) ; - /* Select the clock source for the Timer2 instance. */ - CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) &= ~(CM_DPLL_CLKSEL_CLK_CLKSEL); - /* 32k clock source */ - CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) |= CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3; + /* Select the clock source for the Timer2 instance. */ + CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) &= ~(CM_DPLL_CLKSEL_CLK_CLKSEL); + /* 32k clock source */ + CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) |= CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3; - while ((CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) & CM_DPLL_CLKSEL_CLK_CLKSEL) != - CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3); + while ((CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) & CM_DPLL_CLKSEL_CLK_CLKSEL) != + CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3); - /* Writing to MODULEMODE field of CM_PER_TIMER7_CLKCTRL register. */ - CM_PER_TIMER7_CLKCTRL(prcm_base) |= CM_PER_CLKCTRL_MODULEMODE_ENABLE; + /* Writing to MODULEMODE field of CM_PER_TIMER7_CLKCTRL register. */ + CM_PER_TIMER7_CLKCTRL(prcm_base) |= CM_PER_CLKCTRL_MODULEMODE_ENABLE; - /* Waiting for MODULEMODE field to reflect the written value. */ - while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_MODULEMODE) != - CM_PER_CLKCTRL_MODULEMODE_ENABLE); + /* Waiting for MODULEMODE field to reflect the written value. */ + while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_MODULEMODE) != + CM_PER_CLKCTRL_MODULEMODE_ENABLE); - /* - * Waiting for IDLEST field in CM_PER_TIMER7_CLKCTRL register - * for the module is fully functional. - */ - while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_IDLEST) != - CM_PER_CLKCTRL_IDLEST_FUNC); + /* + * Waiting for IDLEST field in CM_PER_TIMER7_CLKCTRL register + * for the module is fully functional. + */ + while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_IDLEST) != + CM_PER_CLKCTRL_IDLEST_FUNC); - /* Waiting for the L4LS clock */ - while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK)); - /* Waiting for the TIMER7 clock */ - while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK)); + /* Waiting for the L4LS clock */ + while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK)); + /* Waiting for the TIMER7 clock */ + while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK)); } int rt_hw_timer_init(void) { - rt_uint32_t counter; + rt_uint32_t counter; #ifdef RT_USING_VMM DMTIMER = vmm_find_iomap("TIMER7"); #endif - timer_clk_init(); + timer_clk_init(); - /* soft reset the timer */ - DMTIMER_TIOCP_CFG(TIMER_HW_BASE) |= 1; + /* soft reset the timer */ + DMTIMER_TIOCP_CFG(TIMER_HW_BASE) |= 1; while ((DMTIMER_TIOCP_CFG(TIMER_HW_BASE) & 0x1) == 1) ; - /* calculate count */ - counter = 0xffffffff - (32768UL/RT_TICK_PER_SECOND); + /* calculate count */ + counter = 0xffffffff - (32768UL/RT_TICK_PER_SECOND); - /* set initial count */ - DMTIMER_TCRR(TIMER_HW_BASE) = counter; - /* set reload count */ - DMTIMER_TLDR(TIMER_HW_BASE) = counter; + /* set initial count */ + DMTIMER_TCRR(TIMER_HW_BASE) = counter; + /* set reload count */ + DMTIMER_TLDR(TIMER_HW_BASE) = counter; - /* set mode: auto reload */ - DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_AR; + /* set mode: auto reload */ + DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_AR; - /* interrupt enable for match */ - DMTIMER_IRQENABLE_SET(TIMER_HW_BASE) = DMTIMER_IRQENABLE_SET_OVF_EN_FLAG; + /* interrupt enable for match */ + DMTIMER_IRQENABLE_SET(TIMER_HW_BASE) = DMTIMER_IRQENABLE_SET_OVF_EN_FLAG; DMTIMER_IRQSTATUS(TIMER_HW_BASE) = DMTIMER_IRQSTATUS_RAW_OVF_IT_FLAG; - rt_hw_interrupt_install(TINT7, rt_hw_timer_isr, RT_NULL, "tick"); - rt_hw_interrupt_control(TINT7, 0, 0); - rt_hw_interrupt_umask(TINT7); + rt_hw_interrupt_install(TINT7, rt_hw_timer_isr, RT_NULL, "tick"); + rt_hw_interrupt_control(TINT7, 0, 0); + rt_hw_interrupt_umask(TINT7); while (DMTIMER_TWPS(TIMER_HW_BASE) != 0) ; - /* start timer */ - DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_ST; + /* start timer */ + DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_ST; while (DMTIMER_TWPS(TIMER_HW_BASE) != 0) ; @@ -152,7 +148,7 @@ INIT_BOARD_EXPORT(rt_hw_timer_init); void rt_hw_board_init(void) { rt_components_board_init(); - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); } void rt_hw_cpu_reset(void) diff --git a/bsp/beaglebone/applications/board.h b/bsp/beaglebone/applications/board.h index 765ab962b0..cfd794fc5b 100644 --- a/bsp/beaglebone/applications/board.h +++ b/bsp/beaglebone/applications/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/beaglebone/drivers/gpio.c b/bsp/beaglebone/drivers/gpio.c index 425fbb4f4e..9fc0280b7d 100644 --- a/bsp/beaglebone/drivers/gpio.c +++ b/bsp/beaglebone/drivers/gpio.c @@ -1,11 +1,7 @@ /* - * File : gpio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * */ diff --git a/bsp/beaglebone/drivers/gpio.h b/bsp/beaglebone/drivers/gpio.h index afe929c45e..ffc4fce780 100644 --- a/bsp/beaglebone/drivers/gpio.h +++ b/bsp/beaglebone/drivers/gpio.h @@ -1,11 +1,7 @@ /* - * File : gpio.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * */ diff --git a/bsp/beaglebone/drivers/uart.c b/bsp/beaglebone/drivers/uart.c index b623e1571f..887bf2b1cd 100644 --- a/bsp/beaglebone/drivers/uart.c +++ b/bsp/beaglebone/drivers/uart.c @@ -1,11 +1,7 @@ /* - * File : serial.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/beaglebone/drivers/uart.h b/bsp/beaglebone/drivers/uart.h index 15f7f2c399..598bbb6532 100644 --- a/bsp/beaglebone/drivers/uart.h +++ b/bsp/beaglebone/drivers/uart.h @@ -1,11 +1,7 @@ /* - * File : serial.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2013, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/bf533/application.c b/bsp/bf533/application.c index efa5ba829f..2cdc2590e3 100644 --- a/bsp/bf533/application.c +++ b/bsp/bf533/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/bf533/application.h b/bsp/bf533/application.h index 31dd155126..4972ca455e 100644 --- a/bsp/bf533/application.h +++ b/bsp/bf533/application.h @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/bf533/board.c b/bsp/bf533/board.c index d920426232..5542079435 100644 --- a/bsp/bf533/board.c +++ b/bsp/bf533/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -242,7 +238,7 @@ void rt_hw_isr_install(void) *pSIC_IAR1 &= IVG_CLR(IAR1_DMA6_UARTRX_IVG); *pSIC_IAR1 |= IVG_SET(IAR1_DMA6_UARTRX_IVG,ik_ivg9); register_handler(ik_ivg9,uart_rx_isr); - *pSIC_IMASK |= DMA6_UART_RX_INT_MASK;/* ж */ + *pSIC_IMASK |= DMA6_UART_RX_INT_MASK;/* 开中断 */ } void rt_hw_board_init(void) diff --git a/bsp/bf533/board.h b/bsp/bf533/board.h index 5867259609..8ff522c01b 100644 --- a/bsp/bf533/board.h +++ b/bsp/bf533/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -23,7 +19,7 @@ #define CLOCKS_PER_SECD CCLKSPEED #define SCLOCKS_PER_SEC SCLKSPEED -//SIC_IMASKĴ +//SIC_IMASK寄存器 #define PLL_WAKEUP_INT_MASK 0x00000001 #define DMA_ERROR_INT_MASK 0x00000002 #define PPI_ERROR_INT_MASK 0x00000004 diff --git a/bsp/bf533/startup.c b/bsp/bf533/startup.c index 7d90dd2493..a56b123035 100644 --- a/bsp/bf533/startup.c +++ b/bsp/bf533/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/.config b/bsp/bluetrum/ab32vg1-ab-prougen/.config index c5bca5ae40..5e9bfa2384 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/.config +++ b/bsp/bluetrum/ab32vg1-ab-prougen/.config @@ -23,6 +23,7 @@ CONFIG_IDLE_THREAD_STACK_SIZE=512 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=256 +# CONFIG_RT_KSERVICE_USING_STDLIB is not set CONFIG_RT_DEBUG=y # CONFIG_RT_DEBUG_COLOR is not set # CONFIG_RT_DEBUG_INIT_CONFIG is not set @@ -258,8 +259,6 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_LIBRWS is not set # CONFIG_PKG_USING_TCPSERVER is not set # CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set # CONFIG_PKG_USING_DLT645 is not set # CONFIG_PKG_USING_QXWZ is not set # CONFIG_PKG_USING_SMTP_CLIENT is not set @@ -274,6 +273,12 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_BTSTACK is not set # CONFIG_PKG_USING_LORAWAN_ED_STACK is not set # CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set # # security packages @@ -332,6 +337,13 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_VCONSOLE is not set # CONFIG_PKG_USING_KDB is not set # CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set # # system packages @@ -339,7 +351,6 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_CAIRO is not set # CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set # CONFIG_PKG_USING_FLASHDB is not set @@ -349,6 +360,9 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set # CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_THREAD_POOL is not set # CONFIG_PKG_USING_ROBOTS is not set # CONFIG_PKG_USING_EV is not set @@ -370,12 +384,13 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_UC_MODBUS is not set # CONFIG_PKG_USING_PPOOL is not set # CONFIG_PKG_USING_OPENAMP is not set -# CONFIG_PKG_USING_RT_PRINTF is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set # CONFIG_PKG_USING_RT_MEMCPY_CM is not set # CONFIG_PKG_USING_QFPLIB_M0_FULL is not set # CONFIG_PKG_USING_QFPLIB_M0_TINY is not set # CONFIG_PKG_USING_QFPLIB_M3 is not set # CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set # # peripheral libraries and drivers @@ -438,6 +453,24 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_VIRTUAL_SENSOR is not set # CONFIG_PKG_USING_VDEVICE is not set # CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set # # miscellaneous packages @@ -469,25 +502,24 @@ CONFIG_RT_USING_LIBC=y # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set # CONFIG_PKG_USING_KI is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_ELAPACK is not set # CONFIG_PKG_USING_ARMv7M_DWT is not set # CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_ULAPACK is not set # CONFIG_PKG_USING_UKAL is not set # CONFIG_PKG_USING_CRCLIB is not set # -# games: games run on RT-Thread console +# entertainment: terminal games and other interesting software packages # # CONFIG_PKG_USING_THREES is not set # CONFIG_PKG_USING_2048 is not set # CONFIG_PKG_USING_SNAKE is not set # CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_ACLOCK is not set # CONFIG_PKG_USING_LWGPS is not set -# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set # CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set # # Hardware Drivers Config @@ -496,14 +528,16 @@ CONFIG_RT_USING_LIBC=y # # Onboard Peripheral Drivers # -CONFIG_BSP_USING_USB_TO_USART=y # CONFIG_BSP_USING_AUDIO is not set # CONFIG_BSP_USING_SDCARD is not set # # On-chip Peripheral Drivers # +CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_SDIO is not set # CONFIG_BSP_USING_I2C1 is not set # CONFIG_BSP_USING_PWM is not set diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/.cproject b/bsp/bluetrum/ab32vg1-ab-prougen/.cproject index 6e4d4ca5fe..9d6c45a102 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/.cproject +++ b/bsp/bluetrum/ab32vg1-ab-prougen/.cproject @@ -1,158 +1,157 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/README.md b/bsp/bluetrum/ab32vg1-ab-prougen/README.md index 6f24c84c46..c108ff57ba 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/README.md +++ b/bsp/bluetrum/ab32vg1-ab-prougen/README.md @@ -35,19 +35,20 @@ ab32vg1-prougen 是 中科蓝讯(Bluetrum) 推出的一款基于 RISC-V 内核 | USB 转串口 | 支持 | | | SD卡 | 支持 | | | IRDA | 即将支持 | | -| 音频接口 | 支持 | | +| 音频接口 | 支持 | 支持音频输出 | | **片上外设** | **支持情况** | **备注** | | GPIO | 支持 | PA PB PE PF | | UART | 支持 | UART0/1/2 | | SDIO | 支持 | | -| ADC | 即将支持 | | +| ADC | 支持 | 10bit ADC | | SPI | 即将支持 | 软件 SPI | | I2C | 支持 | 软件 I2C | -| RTC | 即将支持 | | +| RTC | 支持 | | | WDT | 支持 | | -| FLASH | 即将支持 | | +| FLASH | 即将支持 | 对接 FAL | | TIMER | 支持 | | | PWM | 支持 | LPWM 的 G1 G2 G3 之间是互斥的，只能三选一 | +| FM receive | 即将支持 | | | USB Device | 暂不支持 | | | USB Host | 暂不支持 | | @@ -109,12 +110,26 @@ msh > 编译报错的时候，如果出现重复定义的报错，可能需要在 `cconfig.h` 中手动添加以下配置 -``` +``` c #define HAVE_SIGEVENT 1 #define HAVE_SIGINFO 1 #define HAVE_SIGVAL 1 ``` +所有在中断中使用的函数或数据需要放在 RAM 中，否则会导致系统运行报错。具体做法可以参考下面 + +``` c +RT_SECTION(".irq.example.str") +static const char example_info[] = "example 0x%x"; + +RT_SECTION(".irq.example") +void example_isr(void) +{ + rt_kprintf(example_info, 11); + ... +} +``` + ## 维护人信息 - [greedyhao](https://github.com/greedyhao) diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/applications/main.c b/bsp/bluetrum/ab32vg1-ab-prougen/applications/main.c index 4c330f0d44..dc043f56e1 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/applications/main.c +++ b/bsp/bluetrum/ab32vg1-ab-prougen/applications/main.c @@ -8,12 +8,17 @@ * 2020/12/10 greedyhao The first version */ +/** + * Notice! + * All functions or data that are called during an interrupt need to be in RAM. + * You can do it the way exception_isr() does. + */ + #include #include "board.h" int main(void) { - uint32_t cnt = 0; uint8_t pin = rt_pin_get("PE.1"); rt_pin_mode(pin, PIN_MODE_OUTPUT); @@ -21,14 +26,9 @@ int main(void) while (1) { - if (cnt % 2 == 0) { - rt_pin_write(pin, PIN_LOW); - } else { - rt_pin_write(pin, PIN_HIGH); - } - cnt++; - rt_thread_mdelay(1000); + rt_pin_write(pin, PIN_LOW); + rt_thread_mdelay(500); + rt_pin_write(pin, PIN_HIGH); + rt_thread_mdelay(500); } - - return 0; } diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/board/Kconfig b/bsp/bluetrum/ab32vg1-ab-prougen/board/Kconfig index 47adcc7b0f..89e651a996 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/board/Kconfig +++ b/bsp/bluetrum/ab32vg1-ab-prougen/board/Kconfig @@ -2,12 +2,6 @@ menu "Hardware Drivers Config" menu "Onboard Peripheral Drivers" - config BSP_USING_USB_TO_USART - bool "Enable USB TO USART (uart0)" - select BSP_USING_UART - select BSP_USING_UART0 - default y - menuconfig BSP_USING_AUDIO bool "Enable Audio Device" select RT_USING_AUDIO @@ -34,11 +28,22 @@ menu "Onboard Peripheral Drivers" endmenu menu "On-chip Peripheral Drivers" - - menuconfig BSP_USING_UART0 - bool "Enable UART0" - select RT_USING_SERIAL - default y + menuconfig BSP_USING_UART + bool "Enable UART" + if BSP_USING_UART + config BSP_USING_UART0 + bool "Enable UART0" + select RT_USING_SERIAL + default y + config BSP_USING_UART1 + bool "Enable UART1" + select RT_USING_SERIAL + default n + config BSP_USING_UART2 + bool "Enable UART2" + select RT_USING_SERIAL + default n + endif config BSP_USING_SDIO bool "Enable SDIO" @@ -85,16 +90,16 @@ menu "On-chip Peripheral Drivers" if BSP_USING_T4_PWM config BSP_USING_T4_PWM1 bool "Enable Timer4 PWM1 (PA6)(Confit with uart0 rx)" - default n + default y endif menuconfig BSP_USING_T5_PWM bool "Enable Timer5 PWM" - default n + default y if BSP_USING_T5_PWM config BSP_USING_T5_PWM0 bool "Enable Timer5 PWM2 (PE1)" - default n + default y endif menuconfig BSP_USING_LPWM0 @@ -104,7 +109,7 @@ menu "On-chip Peripheral Drivers" comment "G1, G2 and G3 are mutually exclusive" config BSP_USING_LPWM0_G1 bool "Enable LPWM0 G1 (PE4)" - default n + default y endif menuconfig BSP_USING_LPWM1 @@ -114,7 +119,7 @@ menu "On-chip Peripheral Drivers" comment "G1, G2 and G3 are mutually exclusive" config BSP_USING_LPWM1_G3 bool "Enable LPWM1 G3 (PA1)" - default n + default y endif menuconfig BSP_USING_LPWM2 @@ -124,7 +129,7 @@ menu "On-chip Peripheral Drivers" comment "G1, G2 and G3 are mutually exclusive" config BSP_USING_LPWM2_G2 bool "Enable LPWM2 G2 (PE0)" - default n + default y config BSP_USING_LPWM2_G3 bool "Enable LPWM2 G3 (PA2)" default n @@ -143,7 +148,7 @@ menu "On-chip Peripheral Drivers" if BSP_USING_TIM config BSP_USING_TIM1 bool "Enable TIM1" - default n + default y config BSP_USING_TIM2 bool "Enable TIM2" @@ -162,11 +167,20 @@ menu "On-chip Peripheral Drivers" default n endif - config BSP_USING_ONCHIP_RTC + menuconfig BSP_USING_ONCHIP_RTC bool "Enable RTC" select RT_USING_RTC select RT_USING_LIBC default n + if BSP_USING_ONCHIP_RTC + config RTC_USING_INTERNAL_CLK + bool "Using internal clock RTC" + default y + config RTC_USING_1S_INT + bool "Using 1 second interrupt" + depends on RT_USING_ALARM + default n + endif menuconfig BSP_USING_ADC bool "Enable ADC" @@ -175,7 +189,7 @@ menu "On-chip Peripheral Drivers" if BSP_USING_ADC config BSP_USING_ADC0 bool "Enable ADC0" - default n + default y endif endmenu diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/board/ab32vg1_hal_msp.c b/bsp/bluetrum/ab32vg1-ab-prougen/board/ab32vg1_hal_msp.c index 4ab3893a4c..ebda0be6ef 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/board/ab32vg1_hal_msp.c +++ b/bsp/bluetrum/ab32vg1-ab-prougen/board/ab32vg1_hal_msp.c @@ -35,6 +35,22 @@ void hal_uart_mspinit(struct uart_handle *huart) gpio_init.af_con = GPIO_AFEN | GPIO_AFCON0 | UT1RXMAP_AF; hal_gpio_init(GPIOA_BASE, &gpio_init); /* Interrupt */ + } else if (huart->instance == UART2_BASE) { + gpio_init.pin = GPIO_PIN_2; + gpio_init.dir = GPIO_DIR_OUTPUT; + gpio_init.de = GPIO_DIGITAL; + gpio_init.alternate = GPIO_AF_MAP_Gx(UT2TXMAP_AF, GPIO_AF_G2); + gpio_init.af_con = GPIO_AFEN | GPIO_AFCON1 | UT2TXMAP_AF; + hal_gpio_init(GPIOB_BASE, &gpio_init); + + gpio_init.pin = GPIO_PIN_1; + gpio_init.pull = GPIO_PULLUP; + gpio_init.dir = GPIO_DIR_INPUT; + gpio_init.de = GPIO_DIGITAL; + gpio_init.alternate = GPIO_AF_MAP_Gx(UT2RXMAP_AF, GPIO_AF_G2); + gpio_init.af_con = GPIO_AFEN | GPIO_AFCON1 | UT2RXMAP_AF; + hal_gpio_init(GPIOB_BASE, &gpio_init); + /* Interrupt */ } } diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/board/board.c b/bsp/bluetrum/ab32vg1-ab-prougen/board/board.c index 734b224377..f10ea4a6c8 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/board/board.c +++ b/bsp/bluetrum/ab32vg1-ab-prougen/board/board.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: @@ -13,10 +13,21 @@ int rt_hw_usart_init(void); void my_printf(const char *format, ...); +void my_print_r(const void *buf, uint16_t cnt); void timer0_cfg(uint32_t ticks); void rt_soft_isr(int vector, void *param); void cpu_irq_comm(void); void set_cpu_irq_comm(void (*irq_hook)(void)); +void load_cache(); +void sys_error_hook(uint8_t err_no); + +typedef void (*os_cache_setfunc_func)(void *load_cache_func, void *io_read); +typedef void (*spiflash_init_func)(uint8_t sf_read, uint8_t dummy); + +#define os_cache_setfunc ((os_cache_setfunc_func) 0x84024) + +static struct rt_mutex mutex_spiflash = {0}; +extern volatile rt_uint8_t rt_interrupt_nest; extern uint32_t __heap_start, __heap_end; void hal_printf(const char *fmt, ...) @@ -55,6 +66,7 @@ void hal_printf(const char *fmt, ...) va_end(args); } +RT_SECTION(".irq.timer") void timer0_isr(int vector, void *param) { rt_interrupt_enter(); @@ -65,16 +77,16 @@ void timer0_isr(int vector, void *param) void timer0_init(void) { - TMR0CON = BIT(7); //TIE - TMR0CNT = 0; + TMR0CON = BIT(7); //TIE + TMR0CNT = 0; - rt_hw_interrupt_install(IRQ_TMR0_VECTOR, timer0_isr, RT_NULL, "tick"); + rt_hw_interrupt_install(IRQ_TMR0_VECTOR, timer0_isr, RT_NULL, "tick"); } void timer0_cfg(uint32_t ticks) { - TMR0PR = (uint32_t)(ticks - 1UL); //1ms interrupt - TMR0CON |= BIT(0); // EN + TMR0PR = (uint32_t)(ticks - 1UL); //1ms interrupt + TMR0CON |= BIT(0); // EN } void hal_mdelay(uint32_t ms) @@ -127,3 +139,57 @@ void rt_hw_board_init(void) rt_components_board_init(); #endif } + +void rt_hw_us_delay(rt_uint32_t us) +{ + +} + +RT_SECTION(".irq.cache") +void cache_init(void) +{ + os_cache_setfunc(load_cache, NULL); + rt_mutex_init(&mutex_spiflash, "flash_mutex", RT_IPC_FLAG_FIFO); +} + +RT_SECTION(".irq.cache") +void os_spiflash_lock(void) +{ + // if (rt_thread_self()->stat == RT_THREAD_RUNNING) { + if ((rt_thread_self() != RT_NULL) && (rt_interrupt_nest == 0)) { + rt_mutex_take(&mutex_spiflash, RT_WAITING_FOREVER); + } +} + +RT_SECTION(".irq.cache") +void os_spiflash_unlock(void) +{ + // if (rt_thread_self()->stat == RT_THREAD_RUNNING) { + if ((rt_thread_self() != RT_NULL) && (rt_interrupt_nest == 0)) { + rt_mutex_release(&mutex_spiflash); + } +} + +RT_SECTION(".irq.err.str") +static const char stack_info[] = "thread sp=0x%x name=%s"; + +void rt_hw_console_output(const char *str) +{ + my_printf(str); +} + +/** + * @brief print exception error + * @note Every message needed to print, must put in .comm exction. + */ +RT_SECTION(".irq.err") +void exception_isr(void) +{ + extern long list_thread(void); + sys_error_hook(1); + + rt_console_set_device(RT_NULL); + rt_kprintf(stack_info, rt_thread_self()->sp, rt_thread_self()->name); + + while(1); +} diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/board/board.h b/bsp/bluetrum/ab32vg1-ab-prougen/board/board.h index a4ad7daed4..37383063ba 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/board/board.h +++ b/bsp/bluetrum/ab32vg1-ab-prougen/board/board.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: @@ -12,7 +12,13 @@ #define BOARD_H__ #include -#include "ab32vgx.h" -#include "drv_gpio.h" +#include +#ifdef RT_USING_PIN +#include +#endif +#ifdef RT_USING_WDT +#include +#endif + #endif diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/board/ports/audio/drv_sound.c b/bsp/bluetrum/ab32vg1-ab-prougen/board/ports/audio/drv_sound.c index 10307cb325..d250a3fc94 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/board/ports/audio/drv_sound.c +++ b/bsp/bluetrum/ab32vg1-ab-prougen/board/ports/audio/drv_sound.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Date Author Notes @@ -15,15 +15,17 @@ #define SAI_AUDIO_FREQUENCY_44K ((uint32_t)44100u) #define SAI_AUDIO_FREQUENCY_48K ((uint32_t)48000u) -#define TX_FIFO_SIZE (1024) +#define TX_FIFO_SIZE (1024) struct sound_device { struct rt_audio_device audio; struct rt_audio_configure replay_config; + rt_sem_t semaphore; + rt_thread_t thread; rt_uint8_t *tx_fifo; rt_uint8_t *rx_fifo; - rt_uint8_t volume; + rt_uint8_t volume; }; static struct sound_device snd_dev = {0}; @@ -105,6 +107,17 @@ void dac_start(void) //AUANGCON1 |= BIT(3); // pa mute } +RT_SECTION(".irq.audio") +void audio_sem_post(void) +{ + rt_sem_release(snd_dev.semaphore); +} + +void audio_sem_pend(void) +{ + rt_sem_take(snd_dev.semaphore, RT_WAITING_FOREVER); +} + void saia_frequency_set(uint32_t frequency) { if (frequency == SAI_AUDIO_FREQUENCY_48K) { @@ -139,7 +152,7 @@ void saia_volume_set(rt_uint8_t volume) { if (volume > 100) volume = 100; - + uint32_t dvol = volume * 327; // max is 0x7ffff LOG_D("dvol=0x%x", dvol); DACVOLCON = dvol | (0x02 << 16); // dac fade in @@ -155,7 +168,7 @@ static rt_err_t sound_getcaps(struct rt_audio_device *audio, struct rt_audio_cap rt_err_t result = RT_EOK; struct sound_device *snd_dev = RT_NULL; - RT_ASSERT(audio != RT_NULL); + RT_ASSERT(audio != RT_NULL); snd_dev = (struct sound_device *)audio->parent.user_data; switch (caps->main_type) @@ -231,7 +244,7 @@ static rt_err_t sound_getcaps(struct rt_audio_device *audio, struct rt_audio_cap break; } - return RT_EOK; + return RT_EOK; } static rt_err_t sound_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps) @@ -320,14 +333,14 @@ static rt_err_t sound_configure(struct rt_audio_device *audio, struct rt_audio_c break; } - return RT_EOK; + return RT_EOK; } static rt_err_t sound_init(struct rt_audio_device *audio) { struct sound_device *snd_dev = RT_NULL; - RT_ASSERT(audio != RT_NULL); + RT_ASSERT(audio != RT_NULL); snd_dev = (struct sound_device *)audio->parent.user_data; adpll_init(0); @@ -337,14 +350,14 @@ static rt_err_t sound_init(struct rt_audio_device *audio) saia_frequency_set(snd_dev->replay_config.samplerate); saia_channels_set(snd_dev->replay_config.channels); - return RT_EOK; + return RT_EOK; } static rt_err_t sound_start(struct rt_audio_device *audio, int stream) { struct sound_device *snd_dev = RT_NULL; - RT_ASSERT(audio != RT_NULL); + RT_ASSERT(audio != RT_NULL); snd_dev = (struct sound_device *)audio->parent.user_data; if (stream == AUDIO_STREAM_REPLAY) @@ -359,7 +372,7 @@ static rt_err_t sound_start(struct rt_audio_device *audio, int stream) DACVOLCON = 0x7fff; // -60DB DACVOLCON |= BIT(20); - AUBUFCON |= BIT(1) | BIT(4); + AUBUFCON |= BIT(1); } return RT_EOK; @@ -369,8 +382,8 @@ static rt_err_t sound_stop(struct rt_audio_device *audio, int stream) { struct sound_device *snd_dev = RT_NULL; - RT_ASSERT(audio != RT_NULL); - snd_dev = (struct sound_device *)audio->parent.user_data; + RT_ASSERT(audio != RT_NULL); + snd_dev = (struct sound_device *)audio->parent.user_data; if (stream == AUDIO_STREAM_REPLAY) { @@ -387,22 +400,25 @@ rt_size_t sound_transmit(struct rt_audio_device *audio, const void *writeBuf, vo rt_size_t tmp_size = size / 4; rt_size_t count = 0; - RT_ASSERT(audio != RT_NULL); + RT_ASSERT(audio != RT_NULL); snd_dev = (struct sound_device *)audio->parent.user_data; while (tmp_size-- > 0) { - while(AUBUFCON & BIT(8)); // aubuf full + if (AUBUFCON & BIT(8)) { // aubuf full + AUBUFCON |= BIT(1) | BIT(4); + audio_sem_pend(); + } AUBUFDATA = ((const uint32_t *)writeBuf)[count++]; } - return size; + return size; } static void sound_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info) { struct sound_device *snd_dev = RT_NULL; - RT_ASSERT(audio != RT_NULL); + RT_ASSERT(audio != RT_NULL); snd_dev = (struct sound_device *)audio->parent.user_data; /** @@ -425,29 +441,43 @@ static struct rt_audio_ops ops = .init = sound_init, .start = sound_start, .stop = sound_stop, - .transmit = sound_transmit, + .transmit = sound_transmit, .buffer_info = sound_buffer_info, }; -void audio_isr(int vector, void *param) +RT_SECTION(".irq.audio") +static void audio_isr(int vector, void *param) { rt_interrupt_enter(); //Audio buffer pend if (AUBUFCON & BIT(5)) { AUBUFCON |= BIT(1); //Audio Buffer Pend Clear - rt_audio_tx_complete(&snd_dev.audio); + AUBUFCON &= ~BIT(4); + audio_sem_post(); } rt_interrupt_leave(); } +static void audio_thread_entry(void *parameter) +{ + while (1) + { + if (snd_dev.audio.replay->activated == RT_TRUE) { + rt_audio_tx_complete(&snd_dev.audio); + } else { + rt_thread_mdelay(50); + } + } +} + static int rt_hw_sound_init(void) { - rt_uint8_t *tx_fifo = RT_NULL; - rt_uint8_t *rx_fifo = RT_NULL; + rt_uint8_t *tx_fifo = RT_NULL; + rt_uint8_t *rx_fifo = RT_NULL; - /* 分配 DMA 搬运 buffer */ - tx_fifo = rt_calloc(1, TX_FIFO_SIZE); + /* 分配 DMA 搬运 buffer */ + tx_fifo = rt_calloc(1, TX_FIFO_SIZE); if(tx_fifo == RT_NULL) { return -RT_ENOMEM; @@ -455,8 +485,8 @@ static int rt_hw_sound_init(void) snd_dev.tx_fifo = tx_fifo; - /* 分配 DMA 搬运 buffer */ - rx_fifo = rt_calloc(1, TX_FIFO_SIZE); + /* 分配 DMA 搬运 buffer */ + rx_fifo = rt_calloc(1, TX_FIFO_SIZE); if(rx_fifo == RT_NULL) { return -RT_ENOMEM; @@ -464,6 +494,26 @@ static int rt_hw_sound_init(void) snd_dev.rx_fifo = rx_fifo; + snd_dev.semaphore = rt_sem_create("snd", 0, RT_IPC_FLAG_FIFO); + if (snd_dev.semaphore == RT_NULL) + { + return -RT_ENOMEM; + } + + snd_dev.thread = rt_thread_create( + "audio", + audio_thread_entry, + RT_NULL, + 1024, + 20, // must equal or lower than tshell priority + 5 + ); + + if (snd_dev.thread != RT_NULL) + { + rt_thread_startup(snd_dev.thread); + } + /* init default configuration */ { snd_dev.replay_config.samplerate = 48000; diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/link.lds b/bsp/bluetrum/ab32vg1-ab-prougen/link.lds index 4f79ad883a..d785c3d92c 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/link.lds +++ b/bsp/bluetrum/ab32vg1-ab-prougen/link.lds @@ -3,8 +3,8 @@ __max_flash_size = 1024k; __data_ram_size = 8k; __stack_ram_size = 4k; -__comm_ram_size = 83k; -__heap_ram_size = 29k; +__comm_ram_size = 42k; +__heap_ram_size = 70k; __base = 0x10000000; @@ -47,26 +47,43 @@ SECTIONS PROVIDE(__ctors_end__ = .); . = ALIGN(4); - *components*drivers**.o (.text*) - *components.o (.text*) + *save-restore.o (.text* .rodata*) + *libcpu*cpu*context_gcc.o (.text* .rodata*) + *libcpu*cpu*interrupt.o (.text* .rodata*) + *libcpu**.o (.rodata*) + + *components*drivers*misc*pin.o(.text*) + *components*drivers*misc*adc.o(.text*) + + . = ALIGN(4); + *src*ipc.o (.text* .rodata*) + *src*irq.o (.text* .rodata*) + *src*object.o (.text* .rodata*) + *src*thread.o (.text* .rodata*) + *src*timer.o (.text* .rodata*) + *src*mempool.o (.text* .rodata*) + *src*scheduler.o (.text* .rodata*) + *src*clock.o (.text* .rodata*) + *src*kservice.o (.text* .rodata*) + *src*device.o (.text* .rodata*) + *src*idle.o (.text* .rodata*) + *src*components.o (.text* .rodata*) } > ram1 AT > flash .comm __comm_vma : { . = ALIGN(4); KEEP(*(.vector)) - EXCLUDE_FILE(*components*finsh**.o *components*libc**.o *dfs*filesystems**.o - *romfs.o *lib_a**.o *divdi3.o *moddi3.o *divdf3.o *muldf3.o *eqtf2.o *getf2.o - *letf2.o *multf3.o *subtf3.o *fixtfsi.o *floatsitf.o *extenddftf2.o - *trunctfdf2.o *_clzsi2.o *cp-demangle.o *unwind*.o - *fixdfsi.o *addsf3.o *divsf3.o *eqsf2.o *gesf2.o *float*.o - *lesf2.o *mulsf3.o *subsf3.o *fixsfsi.o *fixunssfsi.o) *(.text) - *finsh*shell.o (.text*) + *(.irq*) + /*applications**.o (.text .rodata)*/ + *hal_libraries*ab32vg1_hal**.o (.text .rodata) *(.text.unlikely) *(.text.startup) - EXCLUDE_FILE (*components*libc**.o *dfs*filesystems**.o *romfs.o *lib_a**.o - *cp-demangle.o *divdf3.o *muldf3.o *multf3.o *unwind*.o *_clz.o) *(.rodata) - *(.rodata.name) - EXCLUDE_FILE(*lib_a**.o *cp-demangle.o *cp-demangle.o) *(.rodata.str1.4) + *hal_drivers**.o (.rodata) + *audio*drv_sound.o (.rodata) + *system_ab32vgx.o (.rodata) + EXCLUDE_FILE(*lib_a**.o *cp-demangle.o *cp-demangle.o + *src*mem.o *src*memheap.o *dfs**.o *components.o *drivers*sdio**.o *cmd.o *msh_file.o + *drv_sdio.o *drv_wdt.o) *(.rodata.str1.4) EXCLUDE_FILE(*lib_a**.o *unwind*.o) *(.srodata) *(.rela*) *(.data*) @@ -98,7 +115,6 @@ SECTIONS } > heap .flash : { - . = ALIGN(4); __fsymtab_start = .; KEEP(*(FSymTab)) @@ -109,6 +125,7 @@ SECTIONS KEEP(*(VSymTab)) __vsymtab_end = .; + . = ALIGN(4); *(.text*) *(.rodata*) *(.srodata*) diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.h b/bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.h index 272966b74c..f2fa939c6e 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.h +++ b/bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.h @@ -145,23 +145,26 @@ /* peripheral libraries and drivers */ +/* AI packages */ + + /* miscellaneous packages */ /* samples: kernel and components samples */ -/* games: games run on RT-Thread console */ +/* entertainment: terminal games and other interesting software packages */ /* Hardware Drivers Config */ /* Onboard Peripheral Drivers */ -#define BSP_USING_USB_TO_USART /* On-chip Peripheral Drivers */ +#define BSP_USING_UART #define BSP_USING_UART0 /* Board extended module Drivers */ diff --git a/bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.py b/bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.py index b70a0dc654..5afb84e1ba 100644 --- a/bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.py +++ b/bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.py @@ -15,7 +15,7 @@ if os.getenv('RTT_CC'): if CROSS_TOOL == 'gcc': PLATFORM = 'gcc' - EXEC_PATH = r'D:/Softwares/RT-ThreadStudio/repo/Extract/ToolChain_Support_Packages/RISC-V/RISC-V-GCC/10.1.0/bin' + EXEC_PATH = r'D:/program_files/programming/RT-ThreadStudio/repo/Extract/ToolChain_Support_Packages/RISC-V/RISC-V-GCC/10.1.0/bin' else: print('Please make sure your toolchains is GNU GCC!') exit(0) @@ -39,9 +39,9 @@ if PLATFORM == 'gcc': OBJCPY = PREFIX + 'objcopy' # DEVICE = ' -mcmodel=medany -march=rv32imc -mabi=ilp32 -fsingle-precision-constant' - DEVICE = ' -mcmodel=medany -march=rv32imc -mabi=ilp32' + DEVICE = ' -mcmodel=medany -march=rv32imc -mabi=ilp32 -msave-restore' # CFLAGS = DEVICE + ' -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields' - CFLAGS = DEVICE + CFLAGS = DEVICE + ' -D_USE_LONG_TIME_T' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T link.lds' CPATH = '' diff --git a/bsp/bluetrum/libcpu/cpu/cpuport.c b/bsp/bluetrum/libcpu/cpu/cpuport.c index ec3f9cdbc9..a2d405ccdd 100644 --- a/bsp/bluetrum/libcpu/cpu/cpuport.c +++ b/bsp/bluetrum/libcpu/cpu/cpuport.c @@ -41,9 +41,9 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, stk--; *stk = (rt_uint32_t)0x10003; /* Start address */ stk--; - *stk = (rt_uint32_t)tentry; /* Start address */ + *stk = (rt_uint32_t)tentry; /* Start address */ stk -= 22; - *stk = (rt_uint32_t)parameter; /* Register a0 parameter*/ + *stk = (rt_uint32_t)parameter; /* Register a0 parameter*/ stk -= 6; *stk = (rt_uint32_t)tp; /* Register thread pointer */ stk --; diff --git a/bsp/bluetrum/libcpu/cpu/interrupt.c b/bsp/bluetrum/libcpu/cpu/interrupt.c index 3e7dbdb553..64fedde2f9 100644 --- a/bsp/bluetrum/libcpu/cpu/interrupt.c +++ b/bsp/bluetrum/libcpu/cpu/interrupt.c @@ -24,16 +24,16 @@ void set_cpu_irq_comm(void (*irq_hook)(void)) void cpu_irq_comm_do(void) { - void (*pfnct)(void); + void (*pfnct)(void); uint32_t irq_pend = PICPND & irq_mask; - for (int i = 0; i < IRQ_TOTAL_NUM; i++) { + for (int i = 0; i < IRQ_TOTAL_NUM; i++) { if (irq_pend & BIT(i)) { pfnct = tbl_irq_vector[i]; if (pfnct) { - pfnct(); /* call ISR */ + pfnct(); /* call ISR */ } } - } + } } void rt_hw_irq_enable(int vector) @@ -56,12 +56,12 @@ void rt_hw_interrupt_init(void) /** * @brief This function will install a interrupt service routine to a interrupt. - * - * @param vector - * @param handler - * @param param - * @param name - * @return rt_isr_handler_t + * + * @param vector + * @param handler + * @param param + * @param name + * @return rt_isr_handler_t */ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, diff --git a/bsp/bluetrum/libraries/hal_drivers/config/adc_config.h b/bsp/bluetrum/libraries/hal_drivers/config/adc_config.h index 9fc2df3a8a..22cd84da5b 100644 --- a/bsp/bluetrum/libraries/hal_drivers/config/adc_config.h +++ b/bsp/bluetrum/libraries/hal_drivers/config/adc_config.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: diff --git a/bsp/bluetrum/libraries/hal_drivers/config/tim_config.h b/bsp/bluetrum/libraries/hal_drivers/config/tim_config.h index c9f192a9de..b1c29ae1e8 100644 --- a/bsp/bluetrum/libraries/hal_drivers/config/tim_config.h +++ b/bsp/bluetrum/libraries/hal_drivers/config/tim_config.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_adc.c b/bsp/bluetrum/libraries/hal_drivers/drv_adc.c index 5f300ebe58..d9c5bf768d 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_adc.c +++ b/bsp/bluetrum/libraries/hal_drivers/drv_adc.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: @@ -45,7 +45,7 @@ static rt_err_t ab32_adc_enabled(struct rt_adc_device *device, rt_uint32_t chann { RT_ASSERT(device != RT_NULL); - hal_adc_enable(enabled); + hal_adc_enable(enabled); return RT_EOK; } @@ -53,7 +53,7 @@ static rt_err_t ab32_adc_enabled(struct rt_adc_device *device, rt_uint32_t chann static rt_uint32_t ab32_adc_get_channel(rt_uint32_t channel) { rt_uint32_t ab32_channel = 0; - + switch (channel) { case 0: diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_common.h b/bsp/bluetrum/libraries/hal_drivers/drv_common.h index 93c77a9d93..3af014f49a 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_common.h +++ b/bsp/bluetrum/libraries/hal_drivers/drv_common.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: @@ -15,4 +15,6 @@ #include #include +#define GET_PIN(PORTx,PIN) (uint8_t)__AB32_GET_PIN_##PORTx(PIN) + #endif // DRV_COMMON_H__ diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_gpio.c b/bsp/bluetrum/libraries/hal_drivers/drv_gpio.c index d8bc51d91e..4e0f96a794 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_gpio.c +++ b/bsp/bluetrum/libraries/hal_drivers/drv_gpio.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_gpio.h b/bsp/bluetrum/libraries/hal_drivers/drv_gpio.h index 525702e75a..55cf2efc00 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_gpio.h +++ b/bsp/bluetrum/libraries/hal_drivers/drv_gpio.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: @@ -15,6 +15,10 @@ #include "board.h" #define __AB32_PORT(port) GPIO##port +#define __AB32_GET_PIN_A(PIN) PIN +#define __AB32_GET_PIN_B(PIN) 8 + PIN +#define __AB32_GET_PIN_E(PIN) 13 + PIN +#define __AB32_GET_PIN_F(PIN) 21 + PIN int rt_hw_pin_init(void); diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_hwtimer.c b/bsp/bluetrum/libraries/hal_drivers/drv_hwtimer.c index 0015afbc5d..856307e0db 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_hwtimer.c +++ b/bsp/bluetrum/libraries/hal_drivers/drv_hwtimer.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: @@ -68,6 +68,37 @@ static struct ab32_hwtimer ab32_hwtimer_obj[] = #endif }; +RT_SECTION(".irq.timer") +static void _rt_device_hwtimer_isr(rt_hwtimer_t *timer) +{ + RT_ASSERT(timer != RT_NULL); + + timer->overflow ++; + + if (timer->cycles != 0) + { + timer->cycles --; + } + + if (timer->cycles == 0) + { + timer->cycles = timer->reload; + + if (timer->mode == HWTIMER_MODE_ONESHOT) + { + if (timer->ops->stop != RT_NULL) + { + timer->ops->stop(timer); + } + } + + if (timer->parent.rx_indicate != RT_NULL) + { + timer->parent.rx_indicate(&timer->parent, sizeof(struct rt_hwtimerval)); + } + } +} + static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) { uint32_t prescaler_value = 0; @@ -185,25 +216,26 @@ static const struct rt_hwtimer_ops _ops = }; #if defined(BSP_USING_TIM2) || defined(BSP_USING_TIM4) || defined(BSP_USING_TIM5) +RT_SECTION(".irq.timer") void timer2_4_5_isr(int vector, void *param) { rt_interrupt_enter(); #ifdef BSP_USING_TIM2 if (ab32_hwtimer_obj[TIM2_INDEX].tim_handle[TMRxCON] != 0) { ab32_hwtimer_obj[TIM2_INDEX].tim_handle[TMRxCPND] = BIT(9); - rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM2_INDEX].time_device); + _rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM2_INDEX].time_device); } #endif #ifdef BSP_USING_TIM4 if (ab32_hwtimer_obj[TIM4_INDEX].tim_handle[TMRxCON] != 0) { ab32_hwtimer_obj[TIM4_INDEX].tim_handle[TMRxCPND] = BIT(9); - rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM4_INDEX].time_device); + _rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM4_INDEX].time_device); } #endif #ifdef BSP_USING_TIM5 if (ab32_hwtimer_obj[TIM5_INDEX].tim_handle[TMRxCON] != 0) { ab32_hwtimer_obj[TIM5_INDEX].tim_handle[TMRxCPND] = BIT(9); - rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM5_INDEX].time_device); + _rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM5_INDEX].time_device); } #endif rt_interrupt_leave(); @@ -211,21 +243,23 @@ void timer2_4_5_isr(int vector, void *param) #endif #ifdef BSP_USING_TIM3 +RT_SECTION(".irq.timer") void timer3_isr(int vector, void *param) { rt_interrupt_enter(); ab32_hwtimer_obj[TIM3_INDEX].tim_handle[TMRxCPND] = BIT(9); - rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM3_INDEX].time_device); + _rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM3_INDEX].time_device); rt_interrupt_leave(); } #endif #ifdef BSP_USING_TIM1 +RT_SECTION(".irq.timer") void timer1_isr(int vector, void *param) { rt_interrupt_enter(); ab32_hwtimer_obj[TIM1_INDEX].tim_handle[TMRxCPND] = BIT(9); - rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM1_INDEX].time_device); + _rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM1_INDEX].time_device); rt_interrupt_leave(); } #endif diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_log.h b/bsp/bluetrum/libraries/hal_drivers/drv_log.h index 0491ee177e..398014a527 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_log.h +++ b/bsp/bluetrum/libraries/hal_drivers/drv_log.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_rtc.c b/bsp/bluetrum/libraries/hal_drivers/drv_rtc.c index 99483cb544..ccbaac1909 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_rtc.c +++ b/bsp/bluetrum/libraries/hal_drivers/drv_rtc.c @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2021-01-28 greedyhao first version + * 2021-03-19 iysheng modify just set time first power up + * 2021-03-26 iysheng add alarm and 1s interrupt support */ #include "board.h" @@ -95,39 +97,60 @@ uint8_t irtc_sfr_read(uint32_t cmd) IRTC_EXIT_CRITICAL(); } +static void _init_rtc_clock(void) +{ + uint8_t rtccon0; + uint8_t rtccon2; + + rtccon0 = irtc_sfr_read(RTCCON0_CMD); + rtccon2 = irtc_sfr_read(RTCCON2_CMD); +#ifdef RTC_USING_INTERNAL_CLK + rtccon0 &= ~RTC_CON0_XOSC32K_ENABLE; + rtccon0 |= RTC_CON0_INTERNAL_32K; + rtccon2 | RTC_CON2_32K_SELECT; +#else + rtccon0 |= RTC_CON0_XOSC32K_ENABLE; + rtccon0 &= ~RTC_CON0_INTERNAL_32K; + rtccon2 & ~RTC_CON2_32K_SELECT; +#endif + irtc_sfr_write(RTCCON0_CMD, rtccon0); + irtc_sfr_write(RTCCON2_CMD, rtccon2); +} + void hal_rtc_init(void) { time_t sec = 0; struct tm tm_new = {0}; + uint8_t temp; - uint8_t temp = irtc_sfr_read(RTCCON0_CMD); - temp &= ~RTC_CON0_XOSC32K_ENABLE; - temp |= RTC_CON0_EXTERNAL_32K; - irtc_sfr_write(RTCCON0_CMD, temp); - temp = irtc_sfr_read(RTCCON2_CMD); - irtc_sfr_write(RTCCON2_CMD, temp | RTC_CON2_32K_SELECT); - + _init_rtc_clock(); temp = irtc_sfr_read(RTCCON0_CMD); - if (temp & BIT(7)) { - temp &= ~BIT(7); + if (temp & RTC_CON0_PWRUP_FIRST) { + temp &= ~RTC_CON0_PWRUP_FIRST; irtc_sfr_write(RTCCON0_CMD, temp); /* First power on */ + tm_new.tm_mday = 29; + tm_new.tm_mon = 1 - 1; + tm_new.tm_year = 2021 - 1900; + sec = timegm(&tm_new); + + irtc_time_write(RTCCNT_CMD, sec); } - - tm_new.tm_mday = 29; - tm_new.tm_mon = 1 - 1; - tm_new.tm_year = 2021 - 1900; - sec = timegm(&tm_new); - - irtc_time_write(RTCCNT_CMD, sec); +#ifdef RT_USING_ALARM + RTCCON |= RTC_CON_ALM_INTERRUPT; +#ifdef RTC_USING_1S_INT + RTCCON |= RTC_CON_1S_INTERRUPT; +#endif +#endif } /************** HAL End *******************/ -static time_t get_rtc_timestamp(void) +static time_t get_rtc_time_stamp(void) { time_t sec = 0; sec = irtc_time_read(RTCCNT_CMD); LOG_D("get rtc time."); + return sec; } @@ -138,20 +161,36 @@ static rt_err_t set_rtc_time_stamp(time_t time_stamp) return RT_EOK; } +static rt_err_t set_rtc_alarm_stamp(time_t alarm_stamp) +{ + irtc_time_write(RTCALM_CMD, alarm_stamp); + + return RT_EOK; +} + +static time_t get_rtc_alarm_stamp(void) +{ + time_t sec = 0; + + sec = irtc_time_read(RTCALM_CMD); + + return sec; +} + static void rt_rtc_init(void) { hal_rtc_init(); } -static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args) +static rt_err_t ab32_rtc_control(rt_device_t dev, int cmd, void *args) { rt_err_t result = RT_EOK; RT_ASSERT(dev != RT_NULL); switch (cmd) { case RT_DEVICE_CTRL_RTC_GET_TIME: - *(rt_uint32_t *)args = get_rtc_timestamp(); - LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args); + *(rt_uint32_t *)args = get_rtc_time_stamp(); + LOG_D("RTC: get rtc_time %x", *(rt_uint32_t *)args); break; case RT_DEVICE_CTRL_RTC_SET_TIME: @@ -159,7 +198,18 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args) { result = -RT_ERROR; } - LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args); + LOG_D("RTC: set rtc_time %x", *(rt_uint32_t *)args); + break; + case RT_DEVICE_CTRL_RTC_SET_ALARM: + if (set_rtc_alarm_stamp(*(rt_uint32_t *)args)) + { + result = -RT_ERROR; + } + LOG_D("RTC: set alarm_stamp %x", *(rt_uint32_t *)args); + break; + case RT_DEVICE_CTRL_RTC_GET_ALARM: + *(rt_uint32_t *)args = get_rtc_alarm_stamp(); + LOG_D("RTC: get alarm_stamp %x", *(rt_uint32_t *)args); break; } @@ -174,7 +224,7 @@ const static struct rt_device_ops rtc_ops = RT_NULL, RT_NULL, RT_NULL, - rt_rtc_control + ab32_rtc_control }; #endif @@ -191,7 +241,7 @@ static rt_err_t rt_hw_rtc_register(rt_device_t device, const char *name, rt_uint device->close = RT_NULL; device->read = RT_NULL; device->write = RT_NULL; - device->control = rt_rtc_control; + device->control = ab32_rtc_control; #endif device->type = RT_Device_Class_RTC; device->rx_indicate = RT_NULL; @@ -202,15 +252,42 @@ static rt_err_t rt_hw_rtc_register(rt_device_t device, const char *name, rt_uint return rt_device_register(device, name, flag); } +#ifdef RT_USING_ALARM +RT_SECTION(".irq.rtc") +static void rtc_isr(int vector, void *param) +{ + rt_interrupt_enter(); + + if (RTCCON & RTC_CON_ALM_PEND) + { + RTCCPND |= RTC_CPND_ALM; + } + +#ifdef RTC_USING_1S_INT + if (RTCCON & RTC_CON_1S_PEND) + { + RTCCPND |= RTC_CPND_1S; + } +#endif + + rt_interrupt_leave(); +} +#endif + int rt_hw_rtc_init(void) { rt_err_t result; + result = rt_hw_rtc_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR); if (result != RT_EOK) { LOG_E("rtc register err code: %d", result); return result; } + +#ifdef RT_USING_ALARM + rt_hw_interrupt_install(IRQ_RTC_VECTOR, rtc_isr, RT_NULL, "rtc_isr"); +#endif LOG_D("rtc init success"); return RT_EOK; } diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_sdio.c b/bsp/bluetrum/libraries/hal_drivers/drv_sdio.c index 5fe2bf8d1e..fed9eae2d4 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_sdio.c +++ b/bsp/bluetrum/libraries/hal_drivers/drv_sdio.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: @@ -496,6 +496,7 @@ static rt_int32_t rthw_sd_detect(struct rt_mmcsd_host *host) * @param host rt_mmcsd_host * @retval None */ +RT_SECTION(".irq.sdio") void rthw_sdio_irq_process(struct rt_mmcsd_host *host) { int complete = 0; @@ -616,6 +617,7 @@ static rt_err_t _dma_rxconfig(rt_uint32_t *dst, int Size) return RT_EOK; } +RT_SECTION(".irq.sdio") void sdio_isr(int vector, void *param) { /* enter interrupt */ diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_sdio.h b/bsp/bluetrum/libraries/hal_drivers/drv_sdio.h index 0a8360db7d..09c1d04f52 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_sdio.h +++ b/bsp/bluetrum/libraries/hal_drivers/drv_sdio.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_soft_i2c.c b/bsp/bluetrum/libraries/hal_drivers/drv_soft_i2c.c index 94dfa6c5f1..d2045b863f 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_soft_i2c.c +++ b/bsp/bluetrum/libraries/hal_drivers/drv_soft_i2c.c @@ -235,8 +235,8 @@ int rt_hw_i2c_init(void) ab32_i2c_bus_unlock(&soft_i2c_config[i]); LOG_D("software simulation %s init done, pin scl: %d, pin sda %d", - soft_i2c_config[i].bus_name, - soft_i2c_config[i].scl, + soft_i2c_config[i].bus_name, + soft_i2c_config[i].scl, soft_i2c_config[i].sda); } diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_usart.c b/bsp/bluetrum/libraries/hal_drivers/drv_usart.c index ee6c5791a3..f09cffee61 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_usart.c +++ b/bsp/bluetrum/libraries/hal_drivers/drv_usart.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: @@ -10,6 +10,7 @@ #include "board.h" #include "drv_usart.h" +#include #ifdef RT_USING_SERIAL @@ -21,20 +22,40 @@ enum { +#ifdef BSP_USING_UART0 UART0_INDEX, +#endif +#ifdef BSP_USING_UART1 UART1_INDEX, +#endif +#ifdef BSP_USING_UART2 + UART2_INDEX, +#endif }; static struct ab32_uart_config uart_config[] = { +#ifdef BSP_USING_UART0 { .name = "uart0", .instance = UART0_BASE, + .mode = UART_MODE_TX_RX | UART_MODE_1LINE, }, +#endif +#ifdef BSP_USING_UART1 { .name = "uart1", .instance = UART1_BASE, + .mode = UART_MODE_TX_RX, + }, +#endif +#ifdef BSP_USING_UART2 + { + .name = "uart2", + .instance = UART2_BASE, + .mode = UART_MODE_TX_RX, } +#endif }; static struct ab32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0}; @@ -48,7 +69,7 @@ static rt_err_t ab32_configure(struct rt_serial_device *serial, struct serial_co uart = rt_container_of(serial, struct ab32_uart, serial); uart->handle.instance = uart->config->instance; uart->handle.init.baud = cfg->baud_rate; - uart->handle.init.mode = UART_MODE_TX_RX; + uart->handle.init.mode = uart->config->mode; switch (cfg->data_bits) { @@ -127,6 +148,7 @@ static int ab32_putc(struct rt_serial_device *serial, char ch) return 1; } +RT_SECTION(".irq.usart") static int ab32_getc(struct rt_serial_device *serial) { int ch; @@ -148,18 +170,94 @@ static rt_size_t ab32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t * return -1; } +extern struct finsh_shell *shell; + +RT_SECTION(".irq.usart") +static rt_err_t shell_rx_ind(void) +{ + RT_ASSERT(shell != RT_NULL); + + /* release semaphore to let finsh thread rx data */ + rt_sem_release(&shell->rx_sem); + + return RT_EOK; +} + +RT_SECTION(".irq.usart") +void uart_irq_process(struct rt_serial_device *serial) +{ + int ch = -1; + rt_base_t level; + struct rt_serial_rx_fifo* rx_fifo; + + /* interrupt mode receive */ + rx_fifo = (struct rt_serial_rx_fifo*)serial->serial_rx; + RT_ASSERT(rx_fifo != RT_NULL); + + while (1) + { + ch = serial->ops->getc(serial); + if (ch == -1) break; + + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + rx_fifo->buffer[rx_fifo->put_index] = ch; + rx_fifo->put_index += 1; + if (rx_fifo->put_index >= serial->config.bufsz) rx_fifo->put_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (rx_fifo->put_index == rx_fifo->get_index) + { + rx_fifo->get_index += 1; + rx_fifo->is_full = RT_TRUE; + if (rx_fifo->get_index >= serial->config.bufsz) rx_fifo->get_index = 0; + + // _serial_check_buffer_size(); + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + + rt_size_t rx_length; + + /* get rx length */ + level = rt_hw_interrupt_disable(); + rx_length = (rx_fifo->put_index >= rx_fifo->get_index)? (rx_fifo->put_index - rx_fifo->get_index): + (serial->config.bufsz - (rx_fifo->get_index - rx_fifo->put_index)); + rt_hw_interrupt_enable(level); + + if (rx_length) + { + shell_rx_ind(); + } +} + +RT_SECTION(".irq.usart") static void uart_isr(int vector, void *param) { rt_interrupt_enter(); +#ifdef BSP_USING_UART0 if(hal_uart_getflag(UART0_BASE, UART_FLAG_RXPND)) //RX one byte finish { - rt_hw_serial_isr(&(uart_obj[UART0_INDEX].serial), RT_SERIAL_EVENT_RX_IND); + uart_irq_process(&(uart_obj[UART0_INDEX].serial)); } - // if(hal_uart_getflag(UART1_BASE, UART_FLAG_RXPND)) //RX one byte finish - // { - // rt_hw_serial_isr(&(uart_obj[UART1_INDEX].serial), RT_SERIAL_EVENT_RX_IND); - // } +#endif +#ifdef BSP_USING_UART1 + if(hal_uart_getflag(UART1_BASE, UART_FLAG_RXPND)) //RX one byte finish + { + uart_irq_process(&(uart_obj[UART1_INDEX].serial)); + } +#endif +#ifdef BSP_USING_UART2 + if(hal_uart_getflag(UART2_BASE, UART_FLAG_RXPND)) //RX one byte finish + { + uart_irq_process(&(uart_obj[UART2_INDEX].serial)); + } +#endif rt_interrupt_leave(); } diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_usart.h b/bsp/bluetrum/libraries/hal_drivers/drv_usart.h index 8bcf9c3bcc..53635d9500 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_usart.h +++ b/bsp/bluetrum/libraries/hal_drivers/drv_usart.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: @@ -20,6 +20,8 @@ struct ab32_uart_config { const char *name; hal_sfr_t instance; + uint8_t mode; + uint8_t reserve[3]; // struct dma_config *dma_rx; // struct dma_config *dma_tx; }; diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_wdt.c b/bsp/bluetrum/libraries/hal_drivers/drv_wdt.c index fc2bc0279b..28299897d1 100644 --- a/bsp/bluetrum/libraries/hal_drivers/drv_wdt.c +++ b/bsp/bluetrum/libraries/hal_drivers/drv_wdt.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2020-2021, Bluetrum Development Team - * + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: @@ -12,6 +12,8 @@ #ifdef RT_USING_WDT +#include + // #define DRV_DEBUG #define LOG_TAG "drv.wdt" #include @@ -49,35 +51,35 @@ static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg) switch (*((rt_uint32_t *)arg)) { - case 0: + case AB32_WDT_TIMEOUT_1MS: LOG_I("The watchdog timeout is set to 1ms"); tmp |= (0xa << 24) | (0x00 << 20); break; - case 1: + case AB32_WDT_TIMEOUT_256MS: LOG_I("The watchdog timeout is set to 256ms"); tmp |= (0xa << 24) | (0x01 << 20); break; - case 2: + case AB32_WDT_TIMEOUT_512MS: LOG_I("The watchdog timeout is set to 512ms"); tmp |= (0xa << 24) | (0x02 << 20); break; - case 3: + case AB32_WDT_TIMEOUT_1024MS: LOG_I("The watchdog timeout is set to 1024ms"); tmp |= (0xa << 24) | (0x03 << 20); break; - case 4: + case AB32_WDT_TIMEOUT_2048MS: LOG_I("The watchdog timeout is set to 2048ms"); tmp |= (0xa << 24) | (0x04 << 20); break; - case 5: + case AB32_WDT_TIMEOUT_4096MS: LOG_I("The watchdog timeout is set to 4096ms"); tmp |= (0xa << 24) | (0x05 << 20); break; - case 6: + case AB32_WDT_TIMEOUT_8192MS: LOG_I("The watchdog timeout is set to 8192ms"); tmp |= (0xa << 24) | (0x06 << 20); break; - case 7: + case AB32_WDT_TIMEOUT_16384MS: LOG_I("The watchdog timeout is set to 16384ms"); tmp |= (0xa << 24) | (0x07 << 20); break; @@ -92,28 +94,28 @@ static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg) case RT_DEVICE_CTRL_WDT_GET_TIMEOUT: switch ((WDTCON >> 20) & 0x7) { - case 0: + case AB32_WDT_TIMEOUT_1MS: LOG_D("The watchdog timeout is set to 1ms"); break; - case 1: + case AB32_WDT_TIMEOUT_256MS: LOG_D("The watchdog timeout is set to 256ms"); break; - case 2: + case AB32_WDT_TIMEOUT_512MS: LOG_D("The watchdog timeout is set to 512ms"); break; - case 3: + case AB32_WDT_TIMEOUT_1024MS: LOG_D("The watchdog timeout is set to 1024ms"); break; - case 4: + case AB32_WDT_TIMEOUT_2048MS: LOG_D("The watchdog timeout is set to 2048ms"); break; - case 5: + case AB32_WDT_TIMEOUT_4096MS: LOG_D("The watchdog timeout is set to 4096ms"); break; - case 6: + case AB32_WDT_TIMEOUT_8192MS: LOG_D("The watchdog timeout is set to 8192ms"); break; - case 7: + case AB32_WDT_TIMEOUT_16384MS: LOG_D("The watchdog timeout is set to 16384ms"); break; default: diff --git a/bsp/bluetrum/libraries/hal_drivers/drv_wdt.h b/bsp/bluetrum/libraries/hal_drivers/drv_wdt.h new file mode 100644 index 0000000000..5f8d61aaff --- /dev/null +++ b/bsp/bluetrum/libraries/hal_drivers/drv_wdt.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2020-2021, Bluetrum Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-03-11 Meco Man first version + */ + +#ifndef DRV_WDT_H__ +#define DRV_WDT_H__ + +#define AB32_WDT_TIMEOUT_1MS 0 +#define AB32_WDT_TIMEOUT_256MS 1 +#define AB32_WDT_TIMEOUT_512MS 2 +#define AB32_WDT_TIMEOUT_1024MS 3 +#define AB32_WDT_TIMEOUT_2048MS 4 +#define AB32_WDT_TIMEOUT_4096MS 5 +#define AB32_WDT_TIMEOUT_8192MS 6 +#define AB32_WDT_TIMEOUT_16384MS 7 + +#endif diff --git a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_adc.h b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_adc.h index 0383558646..0329c5ff20 100644 --- a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_adc.h +++ b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_adc.h @@ -13,46 +13,46 @@ * @defgroup ADC_channels * @{ */ -#define ADC_CHANNEL_0 (1u << 0) -#define ADC_CHANNEL_1 (1u << 1) -#define ADC_CHANNEL_2 (1u << 2) -#define ADC_CHANNEL_3 (1u << 3) -#define ADC_CHANNEL_4 (1u << 4) -#define ADC_CHANNEL_5 (1u << 5) -#define ADC_CHANNEL_6 (1u << 6) -#define ADC_CHANNEL_7 (1u << 7) -#define ADC_CHANNEL_8 (1u << 8) -#define ADC_CHANNEL_9 (1u << 9) -#define ADC_CHANNEL_10 (1u << 10) -#define ADC_CHANNEL_11 (1u << 11) -#define ADC_CHANNEL_12 (1u << 12) -#define ADC_CHANNEL_13 (1u << 13) -#define ADC_CHANNEL_14 (1u << 14) -#define ADC_CHANNEL_15 (1u << 15) +#define ADC_CHANNEL_0 (1u << 0) /* PA5 */ +#define ADC_CHANNEL_1 (1u << 1) /* PA6 */ +#define ADC_CHANNEL_2 (1u << 2) /* PA7 */ +#define ADC_CHANNEL_3 (1u << 3) /* PB1 */ +#define ADC_CHANNEL_4 (1u << 4) /* PB2 */ +#define ADC_CHANNEL_5 (1u << 5) /* PB3 */ +#define ADC_CHANNEL_6 (1u << 6) /* PB4 */ +#define ADC_CHANNEL_7 (1u << 7) /* PE5 */ +#define ADC_CHANNEL_8 (1u << 8) /* PE6 */ +#define ADC_CHANNEL_9 (1u << 9) /* PE7 */ +#define ADC_CHANNEL_10 (1u << 10) /* PF2 */ +#define ADC_CHANNEL_11 (1u << 11) /* VRTC */ +#define ADC_CHANNEL_12 (1u << 12) /* WKO */ +#define ADC_CHANNEL_13 (1u << 13) /* BGOP */ +#define ADC_CHANNEL_14 (1u << 14) /* VBAT */ +#define ADC_CHANNEL_15 (1u << 15) /* VUSB */ /** * @} - * + * */ /** * @brief Enable ADC - * - * @param enable + * + * @param enable */ void hal_adc_enable(uint8_t enable); /** * @brief Starts conversion of the channels - * + * * @param channel @ref ADC_channels */ void hal_adc_start(uint32_t channel); /** * @brief Poll for conversion complete - * + * * @param timeout Timeout value in millisecond - * @return hal_error_t + * @return hal_error_t */ hal_error_t hal_adc_poll_for_conversion(uint32_t timeout); diff --git a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_gpio.h b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_gpio.h index ea039cbbd2..0202566e70 100644 --- a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_gpio.h +++ b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_gpio.h @@ -13,7 +13,7 @@ struct gpio_init { uint8_t pin; uint8_t dir; - uint8_t de; + uint8_t de; uint8_t pull; uint32_t alternate; uint32_t af_con; /*!< Alternate function control diff --git a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_gpio_ex.h b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_gpio_ex.h index f2a94d65ac..f99a34780e 100644 --- a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_gpio_ex.h +++ b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_gpio_ex.h @@ -28,13 +28,20 @@ * G5: tx:PA1 rx:PA0 * G6: tx:PE0 rx:PE1 * G7: tx:PF2 rx:map to tx - * + * * UART1: * G1: tx:PA7 rx:PA6 * G2: tx:PA4 rx:PA3 * G3: tx:PF2 rx:map to tx + * + * UART2: + * G1: tx:PE3 rx:PE2 + * G2: tx:PB2 rx:PB1 */ +#define UT2RXMAP_AF (8u) +#define UT2TXMAP_AF (4u) + #define UT1RXMAP_AF (28u) #define UT1TXMAP_AF (24u) #define HSUTRXMAP_AF (20u) @@ -52,17 +59,17 @@ * G1: PE7 * G2: PF2 * G3: PA3 - * + * * LPWM2: * G1: PE6 * G2: PE0 * G3: PA2 - * + * * LPWM1: * G1: PE5 * G2: PB4 * G3: PA1 - * + * * LPWM0: * G1: PE4 * G2: PB3 @@ -76,10 +83,10 @@ /** * TMR5: * G1: PE1 PE2 PE3 - * + * * TMR4: * G1: PA5 PA6 PA7 - * + * * TMR3: * G1: PB0 PB1 PB2 */ diff --git a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_rtc.h b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_rtc.h index 6c128567b5..3bb686e593 100644 --- a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_rtc.h +++ b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_rtc.h @@ -32,9 +32,13 @@ enum #define RTC_CON_BAUD_SELECT (0x3u << 1) /*!< Increase clock selection */ #define RTC_CON_CHIP_SELECT (0x1u << 0) /*!< RTC chip select */ +// RTCCPND +#define RTC_CPND_1S (0x1u << 18) /*!< Clear RTC 1S pending */ +#define RTC_CPND_ALM (0x1u << 17) /*!< Clear RTC alarm pendind */ + // RTCCON0 #define RTC_CON0_PWRUP_FIRST (0x01u << 7) /*!< RTC first power up flag */ -#define RTC_CON0_EXTERNAL_32K (0x01u << 6) /*!< External 32K select */ +#define RTC_CON0_INTERNAL_32K (0x01u << 6) /*!< Internal 32K select */ #define RTC_CON0_VDD_ENABLE (0x01u << 5) /*!< RTC VDD12 enable */ #define RTC_CON0_BG_ENABLE (0x01u << 4) /*!< BG enable */ #define RTC_CON0_LVD_OUTPUT_ENABLE (0x01u << 3) /*!< LVD output enable */ diff --git a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_uart.h b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_uart.h index 6802bfc61f..aae175c22f 100644 --- a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_uart.h +++ b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_uart.h @@ -39,7 +39,7 @@ struct uart_init /** * @brief UART handle struction definition - * + * */ struct uart_handle { @@ -76,8 +76,9 @@ struct uart_handle /** @defgroup UART_Mode UART Transfer Mode * @{ */ -#define UART_MODE_TX (0x00u) /*!< TX mode */ -#define UART_MODE_TX_RX (0x01u) /*!< RX and TX mode */ +#define UART_MODE_TX (0x00u) /*!< TX mode */ +#define UART_MODE_TX_RX (0x01u) /*!< RX and TX mode */ +#define UART_MODE_1LINE (0x02u) /*!< oneline mode */ /** * @} diff --git a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/source/ab32vg1_hal_gpio.c b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/source/ab32vg1_hal_gpio.c index 3e06595986..0a3fe31844 100644 --- a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/source/ab32vg1_hal_gpio.c +++ b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/source/ab32vg1_hal_gpio.c @@ -105,7 +105,7 @@ void hal_gpio_init(hal_sfr_t gpiox, gpio_init_t gpio_init) /** * @brief Read the specified input port pin. - * + * * @param port GPIO port(GPIOAN, GPIOBN, GPIOEN, GPIOFN). * @param pin This parameter can be GPIO_PIN_x where x can be (0.15). * @return uint8_t The input port pin value. @@ -117,7 +117,7 @@ uint8_t hal_gpio_read(hal_sfr_t gpiox, uint8_t pin) /** * @brief Set or clear the selected data port bit. - * + * * @param port GPIO port(GPIOAN, GPIOBN, GPIOEN, GPIOFN). * @param pin This parameter can be GPIO_PIN_x where x can be (0.15). * @param state specifies the value to be written to the selected bit. @@ -135,7 +135,7 @@ void hal_gpio_write(hal_sfr_t gpiox, uint8_t pin, uint8_t state) /** * @brief Toggle the specified GPIO pin. - * + * * @param port GPIO port(GPIOAN, GPIOBN, GPIOEN, GPIOFN). * @param pin This parameter can be GPIO_PIN_x where x can be (0.15). */ diff --git a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/source/ab32vg1_hal_sd.c b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/source/ab32vg1_hal_sd.c index 6ed02005df..e0d3a54950 100644 --- a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/source/ab32vg1_hal_sd.c +++ b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/source/ab32vg1_hal_sd.c @@ -232,7 +232,7 @@ static bool sd_go_ready_try(sd_handle_t hsd) case CARD_V1: sdmmc_acmd_op_cond(hsd, 0x00ff8000); break; - + case CARD_V2: sdmmc_acmd_op_cond(hsd, 0x40ff8000); break; @@ -389,8 +389,8 @@ bool hal_sd_read(sd_handle_t hsd, void *buf, uint32_t lba) return true; } } - hsd->sdcard.state = HAL_SD_STATE_INVAL; - + hsd->sdcard.state = HAL_SD_STATE_INVAL; + hal_mdelay(20); } diff --git a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/source/ab32vg1_hal_uart.c b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/source/ab32vg1_hal_uart.c index bef740f89f..7f1f9cd6ff 100644 --- a/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/source/ab32vg1_hal_uart.c +++ b/bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/source/ab32vg1_hal_uart.c @@ -18,7 +18,7 @@ enum /** * @brief Set the UART baud rate. - * + * * @param uartx This parameter can be UARTxN where x can be (0.2). * @param baud Baud rate. */ @@ -27,15 +27,56 @@ void hal_uart_setbaud(hal_sfr_t uartx, uint32_t baud) uint32_t baud_cfg; uartx[UARTxCON] |= UART_CLK_SRC1; - baud_cfg = (26000000/2)/baud; //1.5M + baud_cfg = (26000000/2)/baud; uartx[UARTxBAUD] = (baud_cfg << 16) | baud_cfg; } +/** + * @brief Set the UART misc paramter. + * + * @param uartx This parameter can be UARTxN where x can be (0.2). + * @param param uart config paramter pointer. + */ +void hal_uart_setparam(hal_sfr_t uartx, struct uart_init *param) +{ + switch (param->word_len) + { + case UART_WORDLENGTH_8B: + uartx[UARTxCON] &= ~UART_BIT9_ENABLE; + break; + case UART_WORDLENGTH_9B: + uartx[UARTxCON] |= UART_BIT9_ENABLE; + break; + default: + break; + } + + switch (param->stop_bits) + { + case UART_STOPBITS_1: + uartx[UARTxCON] &= ~UART_SB2_ENABLE; + break; + case UART_STOPBITS_2: + uartx[UARTxCON] |= UART_SB2_ENABLE; + break; + default: + break; + } + + if (param->mode & UART_MODE_1LINE) + { + uartx[UARTxCON] |= UART_1LINE_ENABLE; + } + else + { + uartx[UARTxCON] &= ~UART_1LINE_ENABLE; + } +} /** * @brief Initialize the UART mode. - * + * * @param huart UART handle. - * @return hal_error_t + * @return hal_error_t */ hal_error_t hal_uart_init(struct uart_handle *huart) { @@ -51,7 +92,7 @@ hal_error_t hal_uart_init(struct uart_handle *huart) /** * @brief DeInitialize the UART peripheral. - * + * * @param uartx This parameter can be UARTxN where x can be (0.2). */ void hal_uart_deinit(hal_sfr_t uartx) @@ -61,7 +102,7 @@ void hal_uart_deinit(hal_sfr_t uartx) /** * @brief Initialize the UART MSP. - * + * * @param huart UART handle. */ WEAK void HAL_UART_MspInit(struct uart_handle *huart) @@ -69,9 +110,9 @@ WEAK void HAL_UART_MspInit(struct uart_handle *huart) /** * @brief Control the UART peripheral. - * + * * @param uartx This parameter can be UARTxN where x can be (0.2). - * @param cntl + * @param cntl * @arg UART_MODULE_ENABLE * @arg UART_BIT9_ENABLE * @arg UART_RXIT_ENABLE @@ -80,7 +121,7 @@ WEAK void HAL_UART_MspInit(struct uart_handle *huart) * @arg UART_CLK_SRC1 * @arg UART_1LINE_ENABLE * @arg UART_RX_ENABLE - * @param param + * @param param * @arg HAL_DISABLE * @arg HAL_ENABLE */ @@ -95,7 +136,7 @@ void hal_uart_control(hal_sfr_t uartx, uint32_t cntl, uint32_t param) /** * @brief Send a character - * + * * @param uartx This parameter can be UARTxN where x can be (0.2). * @param data The characters that need to be sent */ @@ -106,7 +147,7 @@ void hal_uart_write(hal_sfr_t uartx, uint8_t data) /** * @brief Receive a character. - * + * * @param uartx This parameter can be UARTxN where x can be (0.2). * @return uint8_t Received character. */ @@ -117,12 +158,12 @@ uint8_t hal_uart_read(hal_sfr_t uartx) /** * @brief Get the UART flag. - * + * * @param uartx This parameter can be UARTxN where x can be (0.2). - * @param flag + * @param flag * @arg UART_FLAG_RXPND * @arg UART_FLAG_TXPND - * @return uint32_t + * @return uint32_t */ uint32_t hal_uart_getflag(hal_sfr_t uartx, uint32_t flag) { @@ -132,9 +173,9 @@ uint32_t hal_uart_getflag(hal_sfr_t uartx, uint32_t flag) /** * @brief Clear the UART flag. - * + * * @param uartx This parameter can be UARTxN where x can be (0.2). - * @param flag + * @param flag * @arg UART_FLAG_RXPND * @arg UART_FLAG_TXPND */ @@ -145,7 +186,7 @@ void hal_uart_clrflag(hal_sfr_t uartx, uint32_t flag) /** * @brief Configure the UART peripheral. - * + * * @param huart UART handle. */ void uart_config_all(struct uart_handle *huart) @@ -157,11 +198,15 @@ void uart_config_all(struct uart_handle *huart) hal_rcu_periph_clk_enable(RCU_UART0); } else if (huart->instance == UART1_BASE) { hal_rcu_periph_clk_enable(RCU_UART1); + } else if (huart->instance == UART2_BASE) { + hal_rcu_periph_clk_enable(RCU_UART2); } else { return; /* Not support! */ } + hal_uart_deinit(huart->instance); hal_uart_setbaud(huart->instance, huart->init.baud); + hal_uart_setparam(huart->instance, &huart->init); if (huart->init.mode != UART_MODE_TX) { hal_uart_control(huart->instance, UART_RX_ENABLE, HAL_ENABLE); diff --git a/bsp/bluetrum/libraries/hal_libraries/bmsis/include/ab32vg1.h b/bsp/bluetrum/libraries/hal_libraries/bmsis/include/ab32vg1.h index 9830369288..c436572b34 100644 --- a/bsp/bluetrum/libraries/hal_libraries/bmsis/include/ab32vg1.h +++ b/bsp/bluetrum/libraries/hal_libraries/bmsis/include/ab32vg1.h @@ -17,18 +17,18 @@ typedef enum IRQ_SW_VECTOR = 2, IRQ_TMR0_VECTOR = 3, IRQ_TMR1_VECTOR = 4, - IRQ_TMR2_4_5_VECTOR = 5, /*!< Timer 2, 4 and 5 Interrupt */ - IRQ_IRRX_VECTOR = 6, /*!< Timer 3 and IR receiver Interrupt */ + IRQ_TMR2_4_5_VECTOR = 5, /*!< Timer 2, 4 and 5 Interrupt */ + IRQ_IRRX_VECTOR = 6, /*!< Timer 3 and IR receiver Interrupt */ IRQ_USB_VECTOR = 7, IRQ_SD_VECTOR = 8, - IRQ_AUBUF0_1_VECTOR = 9, /*!< Audio buffer 0 and 1 Interrupt */ + IRQ_AUBUF0_1_VECTOR = 9, /*!< Audio buffer 0 and 1 Interrupt */ IRQ_SDADC_VECTOR = 10, IRQ_AUDEC_VECTOR = 11, /*!< Audio codec, SBC encode and AEC FFT Interrupt */ - IRQ_SRC_VECTOR = 12, /*!< SRC, PLC and CVSD Interrupt */ - IRQ_FM_SPDIF_VECTOR = 13, /*!< FM TX, RX and SPDIF RX Interrupt */ - IRQ_UART0_2_VECTOR = 14, /*!< UART 0 to 2 Interrupt */ + IRQ_SRC_VECTOR = 12, /*!< SRC, PLC and CVSD Interrupt */ + IRQ_FM_SPDIF_VECTOR = 13, /*!< FM TX, RX and SPDIF RX Interrupt */ + IRQ_UART0_2_VECTOR = 14, /*!< UART 0 to 2 Interrupt */ IRQ_HSUART_VECTOR = 15, - IRQ_RTC_VECTOR = 16, /*!< RTC, LVD and WDT Interrupt */ + IRQ_RTC_VECTOR = 16, /*!< RTC, LVD and WDT Interrupt */ IRQ_I2S_VECTOR = 17, IRQ_TOTAL_NUM = 23, } irq_type; diff --git a/bsp/bluetrum/libraries/hal_libraries/bmsis/source/startup.S b/bsp/bluetrum/libraries/hal_libraries/bmsis/source/startup.S index fe42435c07..3245135038 100644 --- a/bsp/bluetrum/libraries/hal_libraries/bmsis/source/startup.S +++ b/bsp/bluetrum/libraries/hal_libraries/bmsis/source/startup.S @@ -37,20 +37,22 @@ _start: la a2, __bss_size call memset + call cache_init + la a0, __comm_vma sw a0, PICADR(zero) call entry -// la ra, __exception -// jr ra + la ra, __exception + jr ra .section .vector, "ax" -// .org 0x10 -//__exception: -// li sp, 0x10600 //出错后，不破坏错误点的堆栈数据 -// jal exception_isr -// 1: j 1b -// mret + .org 0x10 +__exception: + li sp, 0x10600 //出错后，不破坏错误点的堆栈数据 + jal exception_isr + 1: j 1b + mret .org 0x40 jal x0, low_prio_irq diff --git a/bsp/ck802/applications/main.c b/bsp/ck802/applications/main.c index 65d7985e43..174a00cf97 100644 --- a/bsp/ck802/applications/main.c +++ b/bsp/ck802/applications/main.c @@ -1,22 +1,8 @@ /* - * File : clock.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ck802/drivers/board.c b/bsp/ck802/drivers/board.c index 55f0e47331..df1a263f73 100644 --- a/bsp/ck802/drivers/board.c +++ b/bsp/ck802/drivers/board.c @@ -1,21 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ck802/drivers/board.h b/bsp/ck802/drivers/board.h index 9c404a29c7..431fa6221a 100644 --- a/bsp/ck802/drivers/board.h +++ b/bsp/ck802/drivers/board.h @@ -1,21 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ck802/drivers/board_coretimer.c b/bsp/ck802/drivers/board_coretimer.c index d3275e68d8..2a0bdb0ccb 100644 --- a/bsp/ck802/drivers/board_coretimer.c +++ b/bsp/ck802/drivers/board_coretimer.c @@ -1,21 +1,7 @@ /* - * File : board_coretimer.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ck802/drivers/board_coretimer.h b/bsp/ck802/drivers/board_coretimer.h index e911c8e838..264486632c 100644 --- a/bsp/ck802/drivers/board_coretimer.h +++ b/bsp/ck802/drivers/board_coretimer.h @@ -1,21 +1,7 @@ /* - * File : board_coretimer.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ck802/drivers/board_uart.c b/bsp/ck802/drivers/board_uart.c index 5dd7018f56..3d6f20e820 100644 --- a/bsp/ck802/drivers/board_uart.c +++ b/bsp/ck802/drivers/board_uart.c @@ -1,21 +1,7 @@ /* - * File : board_uart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/ck802/libraries/startup_gcc.S b/bsp/ck802/libraries/startup_gcc.S index 07122fcf98..577d85ed5e 100644 --- a/bsp/ck802/libraries/startup_gcc.S +++ b/bsp/ck802/libraries/startup_gcc.S @@ -1,21 +1,7 @@ /* - * File : startup.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -24,10 +10,10 @@ #undef VIC_TSPR -#define VIC_TSPR 0xE000EC10 +#define VIC_TSPR 0xE000EC10 #ifndef CONFIG_SEPARATE_IRQ_SP -#define CONFIG_SEPARATE_IRQ_SP 1 +#define CONFIG_SEPARATE_IRQ_SP 1 #endif #ifndef CONFIG_ARCH_INTERRUPTSTACK @@ -37,81 +23,81 @@ .import SysTick_Handler .import PendSV_Handler - .section .vectors - .align 10 - .globl __Vectors - .type __Vectors, @object + .section .vectors + .align 10 + .globl __Vectors + .type __Vectors, @object __Vectors: - .long Reset_Handler /* 0: Reset Handler */ - - .rept 15 - .long Default_Handler /* 60 0x40 */ - .endr /* 64 0x40 */ - - .long Default_Handler /* 64 0x44 */ - - .rept 5 - .long Default_Handler /* 88 0x58 */ - .endr /* 92 0x5C */ - - .long PendSV_Handler /* 92 0x5C */ - - .rept 9 - .long Default_Handler /* 128 0x80 */ - .endr + .long Reset_Handler /* 0: Reset Handler */ - /* External interrupts */ - .long GPIOA_IRQHandler /* 32# 0: GPIOA */ /*128 0x80 */ - .long SysTick_Handler /* 1: System Tick */ - .long TIMA0_IRQHandler /* 2: TimerA0 */ - .long TIMA1_IRQHandler /* 3: TimerA1 */ - .long Default_Handler - .long WDT_IRQHandler /* 5: WDT */ - .long USART0_IRQHandler /* 6: UART0 */ - .long USART1_IRQHandler /* 0x27 39 7: UART1 */ - .long USART2_IRQHandler /* 8: UART2 */ - .long I2C0_IRQHandler /* 9: I2C0 */ - .long I2C1_IRQHandler /* 10: I2C1 */ - .long SPI1_IRQHandler /* 11: SPI1 */ - .long SPI0_IRQHandler /* 12: SPI0 */ - .long RTC_IRQHandler /* 13: RTC */ - .long Default_Handler - .long Default_Handler - .long Default_Handler - .long DMAC_IRQHandler /* 17: DMAC */ - .long Default_Handler - .long PWM_IRQHandler /* 19: PWM */ - .long Default_Handler - .long USART3_IRQHandler /* 21: UART3 */ - .long Default_Handler - .long TIMB0_IRQHandler /* 23: TimerB0 */ - .long TIMB1_IRQHandler /* 24: TimerB1 */ - .long Default_Handler - .long AES_IRQHandler /* 26: AES */ - .long GPIOB_IRQHandler /* 27: GPIOB */ - .long Default_Handler - .long SHA_IRQHandler /* 29: SHA */ + .rept 15 + .long Default_Handler /* 60 0x40 */ + .endr /* 64 0x40 */ - .size __Vectors, . - __Vectors + .long Default_Handler /* 64 0x44 */ - .text - .align 1 + .rept 5 + .long Default_Handler /* 88 0x58 */ + .endr /* 92 0x5C */ + + .long PendSV_Handler /* 92 0x5C */ + + .rept 9 + .long Default_Handler /* 128 0x80 */ + .endr + + /* External interrupts */ + .long GPIOA_IRQHandler /* 32# 0: GPIOA */ /*128 0x80 */ + .long SysTick_Handler /* 1: System Tick */ + .long TIMA0_IRQHandler /* 2: TimerA0 */ + .long TIMA1_IRQHandler /* 3: TimerA1 */ + .long Default_Handler + .long WDT_IRQHandler /* 5: WDT */ + .long USART0_IRQHandler /* 6: UART0 */ + .long USART1_IRQHandler /* 0x27 39 7: UART1 */ + .long USART2_IRQHandler /* 8: UART2 */ + .long I2C0_IRQHandler /* 9: I2C0 */ + .long I2C1_IRQHandler /* 10: I2C1 */ + .long SPI1_IRQHandler /* 11: SPI1 */ + .long SPI0_IRQHandler /* 12: SPI0 */ + .long RTC_IRQHandler /* 13: RTC */ + .long Default_Handler + .long Default_Handler + .long Default_Handler + .long DMAC_IRQHandler /* 17: DMAC */ + .long Default_Handler + .long PWM_IRQHandler /* 19: PWM */ + .long Default_Handler + .long USART3_IRQHandler /* 21: UART3 */ + .long Default_Handler + .long TIMB0_IRQHandler /* 23: TimerB0 */ + .long TIMB1_IRQHandler /* 24: TimerB1 */ + .long Default_Handler + .long AES_IRQHandler /* 26: AES */ + .long GPIOB_IRQHandler /* 27: GPIOB */ + .long Default_Handler + .long SHA_IRQHandler /* 29: SHA */ + + .size __Vectors, . - __Vectors + + .text + .align 1 _start: - .text - .align 1 - .globl Reset_Handler - .type Reset_Handler, %function + .text + .align 1 + .globl Reset_Handler + .type Reset_Handler, %function Reset_Handler: /* under normal circumstances, it should not be opened */ #ifndef CONFIG_SYSTEM_SECURE - lrw r0, 0x80000000 - mtcr r0, psr + lrw r0, 0x80000000 + mtcr r0, psr #endif /* Initialize the normal stack pointer from the linker definition. */ - lrw a1, __StackTop - mov sp, a1 + lrw a1, __StackTop + mov sp, a1 /* * The ranges of copy from/to are specified by following symbols @@ -121,22 +107,22 @@ Reset_Handler: * * All addresses must be aligned to 4 bytes boundary. */ - lrw r1, __erodata - lrw r2, __data_start__ - lrw r3, __data_end__ + lrw r1, __erodata + lrw r2, __data_start__ + lrw r3, __data_end__ - subu r3, r2 - cmpnei r3, 0 - bf .L_loop0_done + subu r3, r2 + cmpnei r3, 0 + bf .L_loop0_done .L_loop0: - ldw r0, (r1, 0) - stw r0, (r2, 0) - addi r1, 4 - addi r2, 4 - subi r3, 4 - cmpnei r3, 0 - bt .L_loop0 + ldw r0, (r1, 0) + stw r0, (r2, 0) + addi r1, 4 + addi r2, 4 + subi r3, 4 + cmpnei r3, 0 + bt .L_loop0 .L_loop0_done: @@ -147,98 +133,98 @@ Reset_Handler: * * Both addresses must be aligned to 4 bytes boundary. */ - lrw r1, __bss_start__ - lrw r2, __bss_end__ + lrw r1, __bss_start__ + lrw r2, __bss_end__ - movi r0, 0 + movi r0, 0 - subu r2, r1 - cmpnei r2, 0 - bf .L_loop1_done + subu r2, r1 + cmpnei r2, 0 + bf .L_loop1_done .L_loop1: - stw r0, (r1, 0) - addi r1, 4 - subi r2, 4 - cmpnei r2, 0 - bt .L_loop1 + stw r0, (r1, 0) + addi r1, 4 + subi r2, 4 + cmpnei r2, 0 + bt .L_loop1 .L_loop1_done: #ifdef CONFIG_SEPARATE_IRQ_SP - lrw r0, g_top_irqstack - mtcr r0, cr<15, 1> + lrw r0, g_top_irqstack + mtcr r0, cr<15, 1> - mfcr r0, cr<31, 0> - bseti r0, 14 - mtcr r0, cr<31, 0> + mfcr r0, cr<31, 0> + bseti r0, 14 + mtcr r0, cr<31, 0> #endif #ifndef __NO_SYSTEM_INIT - bsr SystemInit + bsr SystemInit #endif //#ifndef __NO_BOARD_INIT -// bsr board_init +// bsr board_init //#endif //VIC init... - lrw r0, VIC_TSPR - movi r1, 0xb00 - stw r1, (r0) + lrw r0, VIC_TSPR + movi r1, 0xb00 + stw r1, (r0) - bsr entry + bsr entry __exit: - bkpt - .size Reset_Handler, . - Reset_Handler + bkpt + .size Reset_Handler, . - Reset_Handler - .align 1 - .weak Default_Handler - .type Default_Handler, %function + .align 1 + .weak Default_Handler + .type Default_Handler, %function Default_Handler: - br Default_Handler - .size Default_Handler, . - Default_Handler + br Default_Handler + .size Default_Handler, . - Default_Handler .section .bss - .align 2 - .globl g_intstackalloc - .global g_intstackbase - .global g_top_irqstack + .align 2 + .globl g_intstackalloc + .global g_intstackbase + .global g_top_irqstack g_intstackalloc: g_intstackbase: - .space CONFIG_ARCH_INTERRUPTSTACK + .space CONFIG_ARCH_INTERRUPTSTACK g_top_irqstack: /* Macro to define default handlers. Default handler * will be weak symbol and just dead loops. They can be * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm - def_irq_handler CORET_IRQHandler - def_irq_handler TIMA0_IRQHandler - def_irq_handler TIMA1_IRQHandler - def_irq_handler TIMB0_IRQHandler - def_irq_handler TIMB1_IRQHandler - def_irq_handler USART0_IRQHandler - def_irq_handler USART1_IRQHandler - def_irq_handler USART2_IRQHandler - def_irq_handler USART3_IRQHandler - def_irq_handler GPIOA_IRQHandler - def_irq_handler GPIOB_IRQHandler - def_irq_handler I2C0_IRQHandler - def_irq_handler I2C1_IRQHandler - def_irq_handler SPI0_IRQHandler - def_irq_handler SPI1_IRQHandler - def_irq_handler RTC_IRQHandler - def_irq_handler WDT_IRQHandler - def_irq_handler PWM_IRQHandler - def_irq_handler DMAC_IRQHandler - def_irq_handler AES_IRQHandler - def_irq_handler SHA_IRQHandler + def_irq_handler CORET_IRQHandler + def_irq_handler TIMA0_IRQHandler + def_irq_handler TIMA1_IRQHandler + def_irq_handler TIMB0_IRQHandler + def_irq_handler TIMB1_IRQHandler + def_irq_handler USART0_IRQHandler + def_irq_handler USART1_IRQHandler + def_irq_handler USART2_IRQHandler + def_irq_handler USART3_IRQHandler + def_irq_handler GPIOA_IRQHandler + def_irq_handler GPIOB_IRQHandler + def_irq_handler I2C0_IRQHandler + def_irq_handler I2C1_IRQHandler + def_irq_handler SPI0_IRQHandler + def_irq_handler SPI1_IRQHandler + def_irq_handler RTC_IRQHandler + def_irq_handler WDT_IRQHandler + def_irq_handler PWM_IRQHandler + def_irq_handler DMAC_IRQHandler + def_irq_handler AES_IRQHandler + def_irq_handler SHA_IRQHandler - .end + .end diff --git a/bsp/dm365/applications/application.c b/bsp/dm365/applications/application.c index 897f5ef149..3d5207b516 100644 --- a/bsp/dm365/applications/application.c +++ b/bsp/dm365/applications/application.c @@ -1,25 +1,11 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ @@ -41,57 +27,57 @@ int main(void) { - int timeout = 0; + int timeout = 0; /* Filesystem Initialization */ #ifdef RT_USING_DFS - { + { #if defined(RT_USING_DFS_ROMFS) - if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0) - { - rt_kprintf("ROM File System initialized!\n"); - } - else - rt_kprintf("ROM File System initialzation failed!\n"); + if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0) + { + rt_kprintf("ROM File System initialized!\n"); + } + else + rt_kprintf("ROM File System initialzation failed!\n"); #endif #if defined(RT_USING_DFS_UFFS) - { - /* mount flash device as flash directory */ - if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0) - rt_kprintf("UFFS File System initialized!\n"); - else - rt_kprintf("UFFS File System initialzation failed!\n"); - } + { + /* mount flash device as flash directory */ + if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0) + rt_kprintf("UFFS File System initialized!\n"); + else + rt_kprintf("UFFS File System initialzation failed!\n"); + } #endif #ifdef RT_USING_SDIO - timeout = 0; - while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2)) - { - rt_thread_delay(1); - } + timeout = 0; + while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2)) + { + rt_thread_delay(1); + } - if (timeout < RT_TICK_PER_SECOND*2) - { - /* mount sd card fat partition 1 as root directory */ - if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) - { - rt_kprintf("File System initialized!\n"); - } - else - rt_kprintf("File System initialzation failed!%d\n", rt_get_errno()); - } - else - { - rt_kprintf("No SD card found.\n"); - } + if (timeout < RT_TICK_PER_SECOND*2) + { + /* mount sd card fat partition 1 as root directory */ + if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) + { + rt_kprintf("File System initialized!\n"); + } + else + rt_kprintf("File System initialzation failed!%d\n", rt_get_errno()); + } + else + { + rt_kprintf("No SD card found.\n"); + } #endif - } + } #endif - /* put user application code here */ + /* put user application code here */ } @@ -101,14 +87,14 @@ int main(void) #include void nfs_start(void) { - nfs_init(); + nfs_init(); - if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0) - { - rt_kprintf("NFSv3 File System initialized!\n"); - } - else - rt_kprintf("NFSv3 File System initialzation failed!\n"); + if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0) + { + rt_kprintf("NFSv3 File System initialized!\n"); + } + else + rt_kprintf("NFSv3 File System initialzation failed!\n"); } #include "finsh.h" diff --git a/bsp/dm365/applications/board.c b/bsp/dm365/applications/board.c index 53b45c875e..0a4d9596b1 100644 --- a/bsp/dm365/applications/board.c +++ b/bsp/dm365/applications/board.c @@ -1,25 +1,11 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ @@ -33,28 +19,28 @@ */ /*@{*/ #if defined(__CC_ARM) - extern int Image$$ER_ZI$$ZI$$Base; - extern int Image$$ER_ZI$$ZI$$Length; - extern int Image$$ER_ZI$$ZI$$Limit; + extern int Image$$ER_ZI$$ZI$$Base; + extern int Image$$ER_ZI$$ZI$$Length; + extern int Image$$ER_ZI$$ZI$$Limit; #elif (defined (__GNUC__)) - rt_uint8_t _irq_stack_start[1024]; - rt_uint8_t _fiq_stack_start[1024]; - rt_uint8_t _undefined_stack_start[512]; - rt_uint8_t _abort_stack_start[512]; - rt_uint8_t _svc_stack_start[1024] RT_SECTION(".nobss"); - extern unsigned char __bss_start; - extern unsigned char __bss_end; + rt_uint8_t _irq_stack_start[1024]; + rt_uint8_t _fiq_stack_start[1024]; + rt_uint8_t _undefined_stack_start[512]; + rt_uint8_t _abort_stack_start[512]; + rt_uint8_t _svc_stack_start[1024] RT_SECTION(".nobss"); + extern unsigned char __bss_start; + extern unsigned char __bss_end; #endif extern void rt_hw_clock_init(void); extern void rt_hw_uart_init(void); static struct mem_desc dm365_mem_desc[] = { - { 0x80000000, 0x88000000-1, 0x80000000, SECT_RW_CB, 0, SECT_MAPPED }, /* 128M cached SDRAM memory */ - { 0xA0000000, 0xA8000000-1, 0x80000000, SECT_RW_NCNB, 0, SECT_MAPPED }, /* 128M No cached SDRAM memory */ - { 0xFFFF0000, 0xFFFF1000-1, 0x80000000, SECT_TO_PAGE, PAGE_RO_CB, PAGE_MAPPED }, /* isr vector table */ - { 0x01C00000, 0x02000000-1, 0x01C00000, SECT_RW_NCNB, 0, SECT_MAPPED }, /* CFG BUS peripherals */ - { 0x02000000, 0x0A000000-1, 0x02000000, SECT_RW_NCNB, 0, SECT_MAPPED }, /* AEMIF */ + { 0x80000000, 0x88000000-1, 0x80000000, SECT_RW_CB, 0, SECT_MAPPED }, /* 128M cached SDRAM memory */ + { 0xA0000000, 0xA8000000-1, 0x80000000, SECT_RW_NCNB, 0, SECT_MAPPED }, /* 128M No cached SDRAM memory */ + { 0xFFFF0000, 0xFFFF1000-1, 0x80000000, SECT_TO_PAGE, PAGE_RO_CB, PAGE_MAPPED }, /* isr vector table */ + { 0x01C00000, 0x02000000-1, 0x01C00000, SECT_RW_NCNB, 0, SECT_MAPPED }, /* CFG BUS peripherals */ + { 0x02000000, 0x0A000000-1, 0x02000000, SECT_RW_NCNB, 0, SECT_MAPPED }, /* AEMIF */ }; @@ -63,7 +49,7 @@ static struct mem_desc dm365_mem_desc[] = { */ void rt_timer_handler(int vector, void *param) { - rt_tick_increase(); + rt_tick_increase(); } /** @@ -71,70 +57,70 @@ void rt_timer_handler(int vector, void *param) */ void rt_hw_timer_init() { - /* timer0, input clocks 24MHz */ - volatile timer_regs_t *regs = - (volatile timer_regs_t*)DAVINCI_TIMER1_BASE;//DAVINCI_TIMER0_BASE; + /* timer0, input clocks 24MHz */ + volatile timer_regs_t *regs = + (volatile timer_regs_t*)DAVINCI_TIMER1_BASE;//DAVINCI_TIMER0_BASE; - psc_change_state(DAVINCI_DM365_LPSC_TIMER0, 3); - psc_change_state(DAVINCI_DM365_LPSC_TIMER1, 3); + psc_change_state(DAVINCI_DM365_LPSC_TIMER0, 3); + psc_change_state(DAVINCI_DM365_LPSC_TIMER1, 3); - /*disable timer*/ - regs->tcr &= ~(0x3UL << 6); + /*disable timer*/ + regs->tcr &= ~(0x3UL << 6); - //TIMMODE 32BIT UNCHAINED MODE - regs->tgcr |=(0x1UL << 2); + //TIMMODE 32BIT UNCHAINED MODE + regs->tgcr |=(0x1UL << 2); - /*not in reset timer */ - regs->tgcr |= (0x1UL << 0); + /*not in reset timer */ + regs->tgcr |= (0x1UL << 0); - //regs->tgcr &= ~(0x1UL << 1); + //regs->tgcr &= ~(0x1UL << 1); - /* set Period Registers */ - regs->prd12 = 24000000/RT_TICK_PER_SECOND; - regs->tim12 = 0; + /* set Period Registers */ + regs->prd12 = 24000000/RT_TICK_PER_SECOND; + regs->tim12 = 0; - /* Set enable mode */ - regs->tcr |= (0x2UL << 6); //period mode - + /* Set enable mode */ + regs->tcr |= (0x2UL << 6); //period mode - /* install interrupt handler */ - rt_hw_interrupt_install(IRQ_DM365_TINT2, rt_timer_handler, - RT_NULL, "timer1_12");//IRQ_DM365_TINT0_TINT12 - rt_hw_interrupt_umask(IRQ_DM365_TINT2);//IRQ_DM365_TINT2 + + /* install interrupt handler */ + rt_hw_interrupt_install(IRQ_DM365_TINT2, rt_timer_handler, + RT_NULL, "timer1_12");//IRQ_DM365_TINT0_TINT12 + rt_hw_interrupt_umask(IRQ_DM365_TINT2);//IRQ_DM365_TINT2 } -#define LSR_DR 0x01 /* Data ready */ -#define LSR_THRE 0x20 /* Xmit holding register empty */ -#define BPS 115200 /* serial baudrate */ +#define LSR_DR 0x01 /* Data ready */ +#define LSR_THRE 0x20 /* Xmit holding register empty */ +#define BPS 115200 /* serial baudrate */ typedef struct uartport { - volatile rt_uint32_t rbr; - volatile rt_uint32_t ier; - volatile rt_uint32_t fcr; - volatile rt_uint32_t lcr; - volatile rt_uint32_t mcr; - volatile rt_uint32_t lsr; - volatile rt_uint32_t msr; - volatile rt_uint32_t scr; - volatile rt_uint32_t dll; - volatile rt_uint32_t dlh; - - volatile rt_uint32_t res[2]; - volatile rt_uint32_t pwremu_mgmt; - volatile rt_uint32_t mdr; + volatile rt_uint32_t rbr; + volatile rt_uint32_t ier; + volatile rt_uint32_t fcr; + volatile rt_uint32_t lcr; + volatile rt_uint32_t mcr; + volatile rt_uint32_t lsr; + volatile rt_uint32_t msr; + volatile rt_uint32_t scr; + volatile rt_uint32_t dll; + volatile rt_uint32_t dlh; + + volatile rt_uint32_t res[2]; + volatile rt_uint32_t pwremu_mgmt; + volatile rt_uint32_t mdr; }uartport; #define thr rbr #define iir fcr -#define UART0 ((struct uartport *)DAVINCI_UART0_BASE) +#define UART0 ((struct uartport *)DAVINCI_UART0_BASE) static void davinci_uart_putc(char c) { while (!(UART0->lsr & LSR_THRE)); - UART0->thr = c; + UART0->thr = c; } /** @@ -145,35 +131,35 @@ static void davinci_uart_putc(char c) */ void rt_hw_console_output(const char* str) { - while (*str) - { - if (*str=='\n') - { - davinci_uart_putc('\r'); - } + while (*str) + { + if (*str=='\n') + { + davinci_uart_putc('\r'); + } - davinci_uart_putc(*str++); - } + davinci_uart_putc(*str++); + } } static void rt_hw_console_init(void) { - rt_uint32_t divisor; - - divisor = (24000000 + (BPS * (16 / 2))) / (16 * BPS); - UART0->ier = 0; - UART0->lcr = 0x83; //8N1 - UART0->dll = 0; - UART0->dlh = 0; - UART0->lcr = 0x03; - UART0->mcr = 0x03; //RTS,CTS - UART0->fcr = 0x07; //FIFO - UART0->lcr = 0x83; - UART0->dll = divisor & 0xff; - UART0->dlh = (divisor >> 8) & 0xff; - UART0->lcr = 0x03; - UART0->mdr = 0; //16x over-sampling - UART0->pwremu_mgmt = 0x6000; + rt_uint32_t divisor; + + divisor = (24000000 + (BPS * (16 / 2))) / (16 * BPS); + UART0->ier = 0; + UART0->lcr = 0x83; //8N1 + UART0->dll = 0; + UART0->dlh = 0; + UART0->lcr = 0x03; + UART0->mcr = 0x03; //RTS,CTS + UART0->fcr = 0x07; //FIFO + UART0->lcr = 0x83; + UART0->dll = divisor & 0xff; + UART0->dlh = (divisor >> 8) & 0xff; + UART0->lcr = 0x03; + UART0->mdr = 0; //16x over-sampling + UART0->pwremu_mgmt = 0x6000; } /** @@ -181,35 +167,35 @@ static void rt_hw_console_init(void) */ void rt_hw_board_init() { - /* initialize console */ - rt_hw_console_init(); + /* initialize console */ + rt_hw_console_init(); - /* initialize mmu */ - rt_hw_mmu_init(dm365_mem_desc, sizeof(dm365_mem_desc)/sizeof(dm365_mem_desc[0])); + /* initialize mmu */ + rt_hw_mmu_init(dm365_mem_desc, sizeof(dm365_mem_desc)/sizeof(dm365_mem_desc[0])); - /* initialize hardware interrupt */ - rt_hw_interrupt_init(); + /* initialize hardware interrupt */ + rt_hw_interrupt_init(); - /* initialize the system clock */ - rt_hw_clock_init(); + /* initialize the system clock */ + rt_hw_clock_init(); - /* initialize heap memory system */ + /* initialize heap memory system */ #ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$ER_ZI$$ZI$$Limit, (void*)0x88000000); + rt_system_heap_init((void*)&Image$$ER_ZI$$ZI$$Limit, (void*)0x88000000); #else - rt_system_heap_init((void*)&__bss_end, (void*)0x88000000); + rt_system_heap_init((void*)&__bss_end, (void*)0x88000000); #endif - /* initialize early device */ + /* initialize early device */ #ifdef RT_USING_COMPONENTS_INIT - rt_components_board_init(); + rt_components_board_init(); #endif #ifdef RT_USING_CONSOLE - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif - /* initialize timer0 */ - rt_hw_timer_init(); + /* initialize timer0 */ + rt_hw_timer_init(); } diff --git a/bsp/dm365/applications/board.h b/bsp/dm365/applications/board.h index 9eb29d9522..b8763d9938 100644 --- a/bsp/dm365/applications/board.h +++ b/bsp/dm365/applications/board.h @@ -1,25 +1,11 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ diff --git a/bsp/dm365/drivers/davinci_emac.c b/bsp/dm365/drivers/davinci_emac.c index 67e803e3c3..7ad539fb09 100644 --- a/bsp/dm365/drivers/davinci_emac.c +++ b/bsp/dm365/drivers/davinci_emac.c @@ -1,25 +1,11 @@ /* - * File : davinci_emac.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ @@ -29,8 +15,8 @@ #include #include "davinci_emac.h" -#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<29)) -#define CACHE_LINE_SIZE 32 +#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<29)) +#define CACHE_LINE_SIZE 32 extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size); extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); @@ -38,22 +24,22 @@ extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); /* EMAC internal utility function */ static inline rt_uint32_t emac_virt_to_phys(void *addr) { - return (rt_uint32_t)addr; + return (rt_uint32_t)addr; } static inline rt_uint32_t virt_to_phys(void *addr) { - return (rt_uint32_t)addr; + return (rt_uint32_t)addr; } /* Cache macros - Packet buffers would be from pbuf pool which is cached */ #define EMAC_VIRT_NOCACHE(addr) (addr) #define EMAC_CACHE_INVALIDATE(addr, size) \ - mmu_invalidate_dcache(addr, size) + mmu_invalidate_dcache(addr, size) #define EMAC_CACHE_WRITEBACK(addr, size) \ - mmu_clean_dcache(addr, size) + mmu_clean_dcache(addr, size) #define EMAC_CACHE_WRITEBACK_INVALIDATE(addr, size) \ - mmu_clean_invalidated_dcache(addr, size) + mmu_clean_invalidated_dcache(addr, size) /* DM644x does not have BD's in cached memory - so no cache functions */ #define BD_CACHE_INVALIDATE(addr, size) @@ -67,34 +53,34 @@ static struct emac_priv davinci_emac_device; static unsigned long emac_bus_frequency; static unsigned long mdio_max_freq; -#define EMAC_AUTONEG_TIMEOUT 5000000 -#define EMAC_LINK_TIMEOUT 500000 +#define EMAC_AUTONEG_TIMEOUT 5000000 +#define EMAC_LINK_TIMEOUT 500000 /* EMAC TX Host Error description strings */ static char *emac_txhost_errcodes[16] = { - "No error", "SOP error", "Ownership bit not set in SOP buffer", - "Zero Next Buffer Descriptor Pointer Without EOP", - "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error", - "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", - "Reserved", "Reserved", "Reserved", "Reserved" + "No error", "SOP error", "Ownership bit not set in SOP buffer", + "Zero Next Buffer Descriptor Pointer Without EOP", + "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error", + "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", + "Reserved", "Reserved", "Reserved", "Reserved" }; /* EMAC RX Host Error description strings */ static char *emac_rxhost_errcodes[16] = { - "No error", "Reserved", "Ownership bit not set in input buffer", - "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved", - "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", - "Reserved", "Reserved", "Reserved", "Reserved" + "No error", "Reserved", "Ownership bit not set in input buffer", + "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved", + "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", + "Reserved", "Reserved", "Reserved", "Reserved" }; -#define emac_read(reg) davinci_readl(priv->emac_base + (reg)) +#define emac_read(reg) davinci_readl(priv->emac_base + (reg)) #define emac_write(reg, val) davinci_writel(val, priv->emac_base + (reg)) -#define emac_ctrl_read(reg) davinci_readl((priv->ctrl_base + (reg))) +#define emac_ctrl_read(reg) davinci_readl((priv->ctrl_base + (reg))) #define emac_ctrl_write(reg, val) davinci_writel(val, (priv->ctrl_base + (reg))) -#define emac_mdio_read(reg) davinci_readl(priv->mdio_base + (reg)) +#define emac_mdio_read(reg) davinci_readl(priv->mdio_base + (reg)) #define emac_mdio_write(reg, val) davinci_writel(val, (priv->mdio_base + (reg))) static void emac_int_enable(struct emac_priv *priv); @@ -105,74 +91,74 @@ static int emac_init_txch(struct emac_priv *priv, rt_uint32_t ch); /* Wait until mdio is ready for next command */ #define MDIO_WAIT_FOR_USER_ACCESS\ - while ((emac_mdio_read((MDIO_USERACCESS(0))) &\ - MDIO_USERACCESS_GO) != 0) + while ((emac_mdio_read((MDIO_USERACCESS(0))) &\ + MDIO_USERACCESS_GO) != 0) static int emac_mii_read(struct emac_priv *priv, int phy_id, int phy_reg) { - unsigned int phy_data = 0; - unsigned int phy_control; + unsigned int phy_data = 0; + unsigned int phy_control; - /* Wait until mdio is ready for next command */ - MDIO_WAIT_FOR_USER_ACCESS; + /* Wait until mdio is ready for next command */ + MDIO_WAIT_FOR_USER_ACCESS; - phy_control = (MDIO_USERACCESS_GO | - MDIO_USERACCESS_READ | - ((phy_reg << 21) & MDIO_USERACCESS_REGADR) | - ((phy_id << 16) & MDIO_USERACCESS_PHYADR) | - (phy_data & MDIO_USERACCESS_DATA)); - emac_mdio_write(MDIO_USERACCESS(0), phy_control); + phy_control = (MDIO_USERACCESS_GO | + MDIO_USERACCESS_READ | + ((phy_reg << 21) & MDIO_USERACCESS_REGADR) | + ((phy_id << 16) & MDIO_USERACCESS_PHYADR) | + (phy_data & MDIO_USERACCESS_DATA)); + emac_mdio_write(MDIO_USERACCESS(0), phy_control); - /* Wait until mdio is ready for next command */ - MDIO_WAIT_FOR_USER_ACCESS; + /* Wait until mdio is ready for next command */ + MDIO_WAIT_FOR_USER_ACCESS; - return emac_mdio_read(MDIO_USERACCESS(0)) & MDIO_USERACCESS_DATA; + return emac_mdio_read(MDIO_USERACCESS(0)) & MDIO_USERACCESS_DATA; } static int emac_mii_write(struct emac_priv *priv, int phy_id, - int phy_reg, rt_uint16_t phy_data) + int phy_reg, rt_uint16_t phy_data) { - unsigned int control; + unsigned int control; - /* until mdio is ready for next command */ - MDIO_WAIT_FOR_USER_ACCESS; + /* until mdio is ready for next command */ + MDIO_WAIT_FOR_USER_ACCESS; - control = (MDIO_USERACCESS_GO | - MDIO_USERACCESS_WRITE | - ((phy_reg << 21) & MDIO_USERACCESS_REGADR) | - ((phy_id << 16) & MDIO_USERACCESS_PHYADR) | - (phy_data & MDIO_USERACCESS_DATA)); - emac_mdio_write(MDIO_USERACCESS(0), control); + control = (MDIO_USERACCESS_GO | + MDIO_USERACCESS_WRITE | + ((phy_reg << 21) & MDIO_USERACCESS_REGADR) | + ((phy_id << 16) & MDIO_USERACCESS_PHYADR) | + (phy_data & MDIO_USERACCESS_DATA)); + emac_mdio_write(MDIO_USERACCESS(0), control); - return 0; + return 0; } static int emac_mii_reset(struct emac_priv *priv) { - unsigned int clk_div; - int mdio_bus_freq = emac_bus_frequency; + unsigned int clk_div; + int mdio_bus_freq = emac_bus_frequency; - if (mdio_max_freq && mdio_bus_freq) - clk_div = ((mdio_bus_freq / mdio_max_freq) - 1); - else - clk_div = 0xFF; + if (mdio_max_freq && mdio_bus_freq) + clk_div = ((mdio_bus_freq / mdio_max_freq) - 1); + else + clk_div = 0xFF; - clk_div &= MDIO_CONTROL_CLKDIV; + clk_div &= MDIO_CONTROL_CLKDIV; - /* Set enable and clock divider in MDIOControl */ - emac_mdio_write(MDIO_CONTROL, (clk_div | MDIO_CONTROL_ENABLE)); + /* Set enable and clock divider in MDIOControl */ + emac_mdio_write(MDIO_CONTROL, (clk_div | MDIO_CONTROL_ENABLE)); - return 0; + return 0; } /* Duplex, half or full. */ -#define DUPLEX_HALF 0x00 -#define DUPLEX_FULL 0x01 +#define DUPLEX_HALF 0x00 +#define DUPLEX_FULL 0x01 static void udelay(rt_uint32_t us) { @@ -183,83 +169,83 @@ static void udelay(rt_uint32_t us) static void davinci_emac_phy_reset(rt_device_t dev) { - int i; - rt_uint16_t status, adv; - struct emac_priv *priv = dev->user_data;; + int i; + rt_uint16_t status, adv; + struct emac_priv *priv = dev->user_data;; - adv = ADVERTISE_CSMA | ADVERTISE_ALL; - emac_mii_write(priv, priv->phy_addr, MII_ADVERTISE, adv); - rt_kprintf("%s: Starting autonegotiation...\n", dev->parent.name); - emac_mii_write(priv, priv->phy_addr, MII_BMCR, (BMCR_ANENABLE - | BMCR_ANRESTART)); + adv = ADVERTISE_CSMA | ADVERTISE_ALL; + emac_mii_write(priv, priv->phy_addr, MII_ADVERTISE, adv); + rt_kprintf("%s: Starting autonegotiation...\n", dev->parent.name); + emac_mii_write(priv, priv->phy_addr, MII_BMCR, (BMCR_ANENABLE + | BMCR_ANRESTART)); - for (i = 0; i < EMAC_AUTONEG_TIMEOUT / 100; i++) { - status = emac_mii_read(priv, priv->phy_addr, MII_BMSR); - if (status & BMSR_ANEGCOMPLETE) - break; - udelay(100); - } + for (i = 0; i < EMAC_AUTONEG_TIMEOUT / 100; i++) { + status = emac_mii_read(priv, priv->phy_addr, MII_BMSR); + if (status & BMSR_ANEGCOMPLETE) + break; + udelay(100); + } - if (status & BMSR_ANEGCOMPLETE) - rt_kprintf("%s: Autonegotiation complete\n", dev->parent.name); - else - rt_kprintf("%s: Autonegotiation timed out (status=0x%04x)\n", - dev->parent.name, status); + if (status & BMSR_ANEGCOMPLETE) + rt_kprintf("%s: Autonegotiation complete\n", dev->parent.name); + else + rt_kprintf("%s: Autonegotiation timed out (status=0x%04x)\n", + dev->parent.name, status); } static int davinci_emac_phy_init(rt_device_t dev) { - struct emac_priv *priv = dev->user_data; - rt_uint16_t phy_id, status, adv, lpa; - int media, speed, duplex; - int i; + struct emac_priv *priv = dev->user_data; + rt_uint16_t phy_id, status, adv, lpa; + int media, speed, duplex; + int i; - /* Check if the PHY is up to snuff... */ - phy_id = emac_mii_read(priv, priv->phy_addr, MII_PHYSID1); - if (phy_id == 0xffff) { - rt_kprintf("%s: No PHY present\n", dev->parent.name); - return 0; - } + /* Check if the PHY is up to snuff... */ + phy_id = emac_mii_read(priv, priv->phy_addr, MII_PHYSID1); + if (phy_id == 0xffff) { + rt_kprintf("%s: No PHY present\n", dev->parent.name); + return 0; + } - status = emac_mii_read(priv, priv->phy_addr, MII_BMSR); - if (!(status & BMSR_LSTATUS)) { - /* Try to re-negotiate if we don't have link already. */ - davinci_emac_phy_reset(dev); + status = emac_mii_read(priv, priv->phy_addr, MII_BMSR); + if (!(status & BMSR_LSTATUS)) { + /* Try to re-negotiate if we don't have link already. */ + davinci_emac_phy_reset(dev); - for (i = 0; i < EMAC_LINK_TIMEOUT / 100; i++) { - status = emac_mii_read(priv, priv->phy_addr, MII_BMSR); - if (status & BMSR_LSTATUS) - break; - udelay(100); - } - } + for (i = 0; i < EMAC_LINK_TIMEOUT / 100; i++) { + status = emac_mii_read(priv, priv->phy_addr, MII_BMSR); + if (status & BMSR_LSTATUS) + break; + udelay(100); + } + } - if (!(status & BMSR_LSTATUS)) { - rt_kprintf("%s: link down (status: 0x%04x)\n", - dev->parent.name, status); - priv->link = 0; - eth_device_linkchange(&priv->parent, RT_FALSE); - return 0; - } else { - adv = emac_mii_read(priv, priv->phy_addr, MII_ADVERTISE); - lpa = emac_mii_read(priv, priv->phy_addr, MII_LPA); - media = mii_nway_result(lpa & adv); - speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) - ? 1 : 0); - duplex = (media & ADVERTISE_FULL) ? 1 : 0; - rt_kprintf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", - dev->parent.name, - speed ? "100" : "10", - duplex ? "full" : "half", - lpa); - priv->speed = speed; - priv->duplex = duplex; - priv->link = 1; - eth_device_linkchange(&priv->parent, RT_TRUE); + if (!(status & BMSR_LSTATUS)) { + rt_kprintf("%s: link down (status: 0x%04x)\n", + dev->parent.name, status); + priv->link = 0; + eth_device_linkchange(&priv->parent, RT_FALSE); + return 0; + } else { + adv = emac_mii_read(priv, priv->phy_addr, MII_ADVERTISE); + lpa = emac_mii_read(priv, priv->phy_addr, MII_LPA); + media = mii_nway_result(lpa & adv); + speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) + ? 1 : 0); + duplex = (media & ADVERTISE_FULL) ? 1 : 0; + rt_kprintf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", + dev->parent.name, + speed ? "100" : "10", + duplex ? "full" : "half", + lpa); + priv->speed = speed; + priv->duplex = duplex; + priv->link = 1; + eth_device_linkchange(&priv->parent, RT_TRUE); - return 1; - } + return 1; + } } /** @@ -272,94 +258,94 @@ static int davinci_emac_phy_init(rt_device_t dev) */ static void emac_update_phystatus(struct emac_priv *priv) { - rt_uint32_t mac_control; - rt_uint32_t new_duplex; - rt_uint32_t cur_duplex; + rt_uint32_t mac_control; + rt_uint32_t new_duplex; + rt_uint32_t cur_duplex; - mac_control = emac_read(EMAC_MACCONTROL); - cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ? - DUPLEX_FULL : DUPLEX_HALF; - if (priv->phy_mask) - new_duplex = priv->duplex; - else - new_duplex = DUPLEX_FULL; + mac_control = emac_read(EMAC_MACCONTROL); + cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ? + DUPLEX_FULL : DUPLEX_HALF; + if (priv->phy_mask) + new_duplex = priv->duplex; + else + new_duplex = DUPLEX_FULL; - /* We get called only if link has changed (speed/duplex/status) */ - if ((priv->link) && (new_duplex != cur_duplex)) { - priv->duplex = new_duplex; - if (DUPLEX_FULL == priv->duplex) - mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN); - else - mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN); - } + /* We get called only if link has changed (speed/duplex/status) */ + if ((priv->link) && (new_duplex != cur_duplex)) { + priv->duplex = new_duplex; + if (DUPLEX_FULL == priv->duplex) + mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN); + else + mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN); + } - if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) { - mac_control = emac_read(EMAC_MACCONTROL); - mac_control |= (EMAC_DM646X_MACCONTORL_GIG | - EMAC_DM646X_MACCONTORL_GIGFORCE); - } else { - /* Clear the GIG bit and GIGFORCE bit */ - mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE | - EMAC_DM646X_MACCONTORL_GIG); + if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) { + mac_control = emac_read(EMAC_MACCONTROL); + mac_control |= (EMAC_DM646X_MACCONTORL_GIG | + EMAC_DM646X_MACCONTORL_GIGFORCE); + } else { + /* Clear the GIG bit and GIGFORCE bit */ + mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE | + EMAC_DM646X_MACCONTORL_GIG); - if (priv->rmii_en && (priv->speed == SPEED_100)) - mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK; - else - mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK; - } + if (priv->rmii_en && (priv->speed == SPEED_100)) + mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK; + else + mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK; + } - /* Update mac_control if changed */ - emac_write(EMAC_MACCONTROL, mac_control); + /* Update mac_control if changed */ + emac_write(EMAC_MACCONTROL, mac_control); #if 0 - if (priv->link) { - /* link ON */ - /* reactivate the transmit queue if it is stopped */ - } else { - /* link OFF */ - } + if (priv->link) { + /* link ON */ + /* reactivate the transmit queue if it is stopped */ + } else { + /* link OFF */ + } #endif } void davinci_emac_update_link(void *param) { - struct emac_priv *priv = param; - rt_device_t dev = &(priv->parent.parent); - rt_uint32_t status, status_change = 0; - rt_uint32_t link; - rt_uint32_t media; - rt_uint16_t adv, lpa; + struct emac_priv *priv = param; + rt_device_t dev = &(priv->parent.parent); + rt_uint32_t status, status_change = 0; + rt_uint32_t link; + rt_uint32_t media; + rt_uint16_t adv, lpa; - status = emac_mii_read(priv, priv->phy_addr, MII_BMSR); - if ((status & BMSR_LSTATUS) == 0) - link = 0; - else - link = 1; + status = emac_mii_read(priv, priv->phy_addr, MII_BMSR); + if ((status & BMSR_LSTATUS) == 0) + link = 0; + else + link = 1; - if (link != priv->link) { - priv->link = link; - status_change = 1; - } + if (link != priv->link) { + priv->link = link; + status_change = 1; + } - if (status_change) { - if (priv->link) { - adv = emac_mii_read(priv, priv->phy_addr, MII_ADVERTISE); - lpa = emac_mii_read(priv, priv->phy_addr, MII_LPA); - media = mii_nway_result(lpa & adv); - priv->speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) - ? 100 : 10); - priv->duplex = (media & ADVERTISE_FULL) ? 1 : 0; - rt_kprintf("%s: link up (%dMbps/%s-duplex)\n", - dev->parent.name, priv->speed, - DUPLEX_FULL == priv->duplex ? "Full":"Half"); - eth_device_linkchange(&priv->parent, RT_TRUE); - } else { - rt_kprintf("%s: link down\n", dev->parent.name); - eth_device_linkchange(&priv->parent, RT_FALSE); - } - emac_update_phystatus(priv); + if (status_change) { + if (priv->link) { + adv = emac_mii_read(priv, priv->phy_addr, MII_ADVERTISE); + lpa = emac_mii_read(priv, priv->phy_addr, MII_LPA); + media = mii_nway_result(lpa & adv); + priv->speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) + ? 100 : 10); + priv->duplex = (media & ADVERTISE_FULL) ? 1 : 0; + rt_kprintf("%s: link up (%dMbps/%s-duplex)\n", + dev->parent.name, priv->speed, + DUPLEX_FULL == priv->duplex ? "Full":"Half"); + eth_device_linkchange(&priv->parent, RT_TRUE); + } else { + rt_kprintf("%s: link down\n", dev->parent.name); + eth_device_linkchange(&priv->parent, RT_FALSE); + } + emac_update_phystatus(priv); - } + } } @@ -375,21 +361,21 @@ void davinci_emac_update_link(void *param) * */ static int emac_net_tx_complete(struct emac_priv *priv, - void **net_data_tokens, - int num_tokens, rt_uint32_t ch) + void **net_data_tokens, + int num_tokens, rt_uint32_t ch) { - rt_uint32_t cnt; + rt_uint32_t cnt; - for (cnt = 0; cnt < num_tokens; cnt++) { - struct pbuf *p = (struct pbuf *)net_data_tokens[cnt]; - if (p == RT_NULL) - continue; - priv->net_dev_stats.tx_packets++; - priv->net_dev_stats.tx_bytes += p->len; - //free pbuf - } + for (cnt = 0; cnt < num_tokens; cnt++) { + struct pbuf *p = (struct pbuf *)net_data_tokens[cnt]; + if (p == RT_NULL) + continue; + priv->net_dev_stats.tx_packets++; + priv->net_dev_stats.tx_bytes += p->len; + //free pbuf + } - return 0; + return 0; } /** @@ -402,36 +388,36 @@ static int emac_net_tx_complete(struct emac_priv *priv, */ static void emac_txch_teardown(struct emac_priv *priv, rt_uint32_t ch) { - rt_uint32_t teardown_cnt = 0xFFFFFFF0; /* Some high value */ - struct emac_txch *txch = priv->txch[ch]; - struct emac_tx_bd __iomem *curr_bd; + rt_uint32_t teardown_cnt = 0xFFFFFFF0; /* Some high value */ + struct emac_txch *txch = priv->txch[ch]; + struct emac_tx_bd __iomem *curr_bd; - while ((emac_read(EMAC_TXCP(ch)) & EMAC_TEARDOWN_VALUE) != - EMAC_TEARDOWN_VALUE) { - /* wait till tx teardown complete */ - --teardown_cnt; - if (0 == teardown_cnt) { - rt_kprintf("EMAC: TX teardown aborted\n"); - break; - } - } - emac_write(EMAC_TXCP(ch), EMAC_TEARDOWN_VALUE); + while ((emac_read(EMAC_TXCP(ch)) & EMAC_TEARDOWN_VALUE) != + EMAC_TEARDOWN_VALUE) { + /* wait till tx teardown complete */ + --teardown_cnt; + if (0 == teardown_cnt) { + rt_kprintf("EMAC: TX teardown aborted\n"); + break; + } + } + emac_write(EMAC_TXCP(ch), EMAC_TEARDOWN_VALUE); - /* process sent packets and return pbuf's to upper layer */ - if (1 == txch->queue_active) { - curr_bd = txch->active_queue_head; - while (curr_bd != RT_NULL) { - emac_net_tx_complete(priv, (void *) - &curr_bd->buf_token, 1, ch); - if (curr_bd != txch->active_queue_tail) - curr_bd = curr_bd->next; - else - break; - } - txch->bd_pool_head = txch->active_queue_head; - txch->active_queue_head = - txch->active_queue_tail = RT_NULL; - } + /* process sent packets and return pbuf's to upper layer */ + if (1 == txch->queue_active) { + curr_bd = txch->active_queue_head; + while (curr_bd != RT_NULL) { + emac_net_tx_complete(priv, (void *) + &curr_bd->buf_token, 1, ch); + if (curr_bd != txch->active_queue_tail) + curr_bd = curr_bd->next; + else + break; + } + txch->bd_pool_head = txch->active_queue_head; + txch->active_queue_head = + txch->active_queue_tail = RT_NULL; + } } @@ -445,15 +431,15 @@ static void emac_txch_teardown(struct emac_priv *priv, rt_uint32_t ch) */ static void emac_stop_txch(struct emac_priv *priv, rt_uint32_t ch) { - struct emac_txch *txch = priv->txch[ch]; + struct emac_txch *txch = priv->txch[ch]; - if (txch) { - txch->teardown_pending = 1; - emac_write(EMAC_TXTEARDOWN, 0); - emac_txch_teardown(priv, ch); - txch->teardown_pending = 0; - emac_write(EMAC_TXINTMASKCLEAR, BIT(ch)); - } + if (txch) { + txch->teardown_pending = 1; + emac_write(EMAC_TXTEARDOWN, 0); + emac_txch_teardown(priv, ch); + txch->teardown_pending = 0; + emac_write(EMAC_TXINTMASKCLEAR, BIT(ch)); + } } @@ -474,65 +460,65 @@ static void emac_stop_txch(struct emac_priv *priv, rt_uint32_t ch) */ static int emac_tx_bdproc(struct emac_priv *priv, rt_uint32_t ch, rt_uint32_t budget) { - unsigned long flags; - rt_uint32_t frame_status; - rt_uint32_t pkts_processed = 0; - rt_uint32_t tx_complete_cnt = 0; - struct emac_tx_bd __iomem *curr_bd; - struct emac_txch *txch = priv->txch[ch]; - rt_uint32_t *tx_complete_ptr = txch->tx_complete; + unsigned long flags; + rt_uint32_t frame_status; + rt_uint32_t pkts_processed = 0; + rt_uint32_t tx_complete_cnt = 0; + struct emac_tx_bd __iomem *curr_bd; + struct emac_txch *txch = priv->txch[ch]; + rt_uint32_t *tx_complete_ptr = txch->tx_complete; - if (1 == txch->teardown_pending) { - rt_kprintf("DaVinci EMAC:emac_tx_bdproc: "\ - "teardown pending\n"); - return 0; /* dont handle any pkt completions */ - } + if (1 == txch->teardown_pending) { + rt_kprintf("DaVinci EMAC:emac_tx_bdproc: "\ + "teardown pending\n"); + return 0; /* dont handle any pkt completions */ + } - ++txch->proc_count; - rt_sem_take(&priv->tx_lock, RT_WAITING_FOREVER); - curr_bd = txch->active_queue_head; - if (RT_NULL == curr_bd) { - emac_write(EMAC_TXCP(ch), - emac_virt_to_phys(txch->last_hw_bdprocessed)); - txch->no_active_pkts++; - rt_sem_release(&priv->tx_lock); - return 0; - } - BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); - frame_status = curr_bd->mode; - while ((curr_bd) && - ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) && - (pkts_processed < budget)) { - emac_write(EMAC_TXCP(ch), emac_virt_to_phys(curr_bd)); - txch->active_queue_head = curr_bd->next; - if (frame_status & EMAC_CPPI_EOQ_BIT) { - if (curr_bd->next) { /* misqueued packet */ - emac_write(EMAC_TXHDP(ch), curr_bd->h_next); - ++txch->mis_queued_packets; - } else { - txch->queue_active = 0; /* end of queue */ - } - } - *tx_complete_ptr = (rt_uint32_t) curr_bd->buf_token; - ++tx_complete_ptr; - ++tx_complete_cnt; - curr_bd->next = txch->bd_pool_head; - txch->bd_pool_head = curr_bd; - --txch->active_queue_count; - pkts_processed++; - txch->last_hw_bdprocessed = curr_bd; - curr_bd = txch->active_queue_head; - if (curr_bd) { - BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); - frame_status = curr_bd->mode; - } - } /* end of pkt processing loop */ + ++txch->proc_count; + rt_sem_take(&priv->tx_lock, RT_WAITING_FOREVER); + curr_bd = txch->active_queue_head; + if (RT_NULL == curr_bd) { + emac_write(EMAC_TXCP(ch), + emac_virt_to_phys(txch->last_hw_bdprocessed)); + txch->no_active_pkts++; + rt_sem_release(&priv->tx_lock); + return 0; + } + BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); + frame_status = curr_bd->mode; + while ((curr_bd) && + ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) && + (pkts_processed < budget)) { + emac_write(EMAC_TXCP(ch), emac_virt_to_phys(curr_bd)); + txch->active_queue_head = curr_bd->next; + if (frame_status & EMAC_CPPI_EOQ_BIT) { + if (curr_bd->next) { /* misqueued packet */ + emac_write(EMAC_TXHDP(ch), curr_bd->h_next); + ++txch->mis_queued_packets; + } else { + txch->queue_active = 0; /* end of queue */ + } + } + *tx_complete_ptr = (rt_uint32_t) curr_bd->buf_token; + ++tx_complete_ptr; + ++tx_complete_cnt; + curr_bd->next = txch->bd_pool_head; + txch->bd_pool_head = curr_bd; + --txch->active_queue_count; + pkts_processed++; + txch->last_hw_bdprocessed = curr_bd; + curr_bd = txch->active_queue_head; + if (curr_bd) { + BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); + frame_status = curr_bd->mode; + } + } /* end of pkt processing loop */ - emac_net_tx_complete(priv, - (void *)&txch->tx_complete[0], - tx_complete_cnt, ch); - rt_sem_release(&priv->tx_lock); - return pkts_processed; + emac_net_tx_complete(priv, + (void *)&txch->tx_complete[0], + tx_complete_cnt, ch); + rt_sem_release(&priv->tx_lock); + return pkts_processed; } @@ -550,81 +536,81 @@ static int emac_tx_bdproc(struct emac_priv *priv, rt_uint32_t ch, rt_uint32_t bu */ static int emac_send(struct emac_priv *priv, struct emac_netpktobj *pkt, rt_uint32_t ch) { - unsigned long flags; - struct emac_tx_bd __iomem *curr_bd; - struct emac_txch *txch; - struct emac_netbufobj *buf_list; - rt_uint32_t num_pkts = 0; - int retry = 0; + unsigned long flags; + struct emac_tx_bd __iomem *curr_bd; + struct emac_txch *txch; + struct emac_netbufobj *buf_list; + rt_uint32_t num_pkts = 0; + int retry = 0; - txch = priv->txch[ch]; - buf_list = pkt->buf_list; /* get handle to the buffer array */ + txch = priv->txch[ch]; + buf_list = pkt->buf_list; /* get handle to the buffer array */ - /* check packet size and pad if short */ - if (pkt->pkt_length < EMAC_DEF_MIN_ETHPKTSIZE) { - buf_list->length += (EMAC_DEF_MIN_ETHPKTSIZE - pkt->pkt_length); - pkt->pkt_length = EMAC_DEF_MIN_ETHPKTSIZE; - } + /* check packet size and pad if short */ + if (pkt->pkt_length < EMAC_DEF_MIN_ETHPKTSIZE) { + buf_list->length += (EMAC_DEF_MIN_ETHPKTSIZE - pkt->pkt_length); + pkt->pkt_length = EMAC_DEF_MIN_ETHPKTSIZE; + } try: - rt_sem_take(&priv->tx_lock, RT_WAITING_FOREVER); - curr_bd = txch->bd_pool_head; - if (curr_bd == RT_NULL) { - txch->out_of_tx_bd++; - rt_sem_release(&priv->tx_lock); - num_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH, - EMAC_DEF_TX_MAX_SERVICE); - if (!num_pkts) { - retry++; - if (retry > 5) - return EMAC_ERR_TX_OUT_OF_BD; - rt_thread_delay(1); - } - goto try; - } + rt_sem_take(&priv->tx_lock, RT_WAITING_FOREVER); + curr_bd = txch->bd_pool_head; + if (curr_bd == RT_NULL) { + txch->out_of_tx_bd++; + rt_sem_release(&priv->tx_lock); + num_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH, + EMAC_DEF_TX_MAX_SERVICE); + if (!num_pkts) { + retry++; + if (retry > 5) + return EMAC_ERR_TX_OUT_OF_BD; + rt_thread_delay(1); + } + goto try; + } - txch->bd_pool_head = curr_bd->next; - curr_bd->buf_token = buf_list->buf_token; - curr_bd->buff_ptr = virt_to_phys(buf_list->data_ptr); - curr_bd->off_b_len = buf_list->length; - curr_bd->h_next = 0; - curr_bd->next = RT_NULL; - curr_bd->mode = (EMAC_CPPI_SOP_BIT | EMAC_CPPI_OWNERSHIP_BIT | - EMAC_CPPI_EOP_BIT | pkt->pkt_length); + txch->bd_pool_head = curr_bd->next; + curr_bd->buf_token = buf_list->buf_token; + curr_bd->buff_ptr = virt_to_phys(buf_list->data_ptr); + curr_bd->off_b_len = buf_list->length; + curr_bd->h_next = 0; + curr_bd->next = RT_NULL; + curr_bd->mode = (EMAC_CPPI_SOP_BIT | EMAC_CPPI_OWNERSHIP_BIT | + EMAC_CPPI_EOP_BIT | pkt->pkt_length); - /* flush the packet from cache if write back cache is present */ - BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); + /* flush the packet from cache if write back cache is present */ + BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); - /* send the packet */ - if (txch->active_queue_head == RT_NULL) { - txch->active_queue_head = curr_bd; - txch->active_queue_tail = curr_bd; - if (1 != txch->queue_active) { - emac_write(EMAC_TXHDP(ch), - emac_virt_to_phys(curr_bd)); - txch->queue_active = 1; - } - ++txch->queue_reinit; - } else { - register struct emac_tx_bd __iomem *tail_bd; - register rt_uint32_t frame_status; + /* send the packet */ + if (txch->active_queue_head == RT_NULL) { + txch->active_queue_head = curr_bd; + txch->active_queue_tail = curr_bd; + if (1 != txch->queue_active) { + emac_write(EMAC_TXHDP(ch), + emac_virt_to_phys(curr_bd)); + txch->queue_active = 1; + } + ++txch->queue_reinit; + } else { + register struct emac_tx_bd __iomem *tail_bd; + register rt_uint32_t frame_status; - tail_bd = txch->active_queue_tail; - tail_bd->next = curr_bd; - txch->active_queue_tail = curr_bd; - tail_bd = EMAC_VIRT_NOCACHE(tail_bd); - tail_bd->h_next = (int)emac_virt_to_phys(curr_bd); - frame_status = tail_bd->mode; - if (frame_status & EMAC_CPPI_EOQ_BIT) { - emac_write(EMAC_TXHDP(ch), emac_virt_to_phys(curr_bd)); - frame_status &= ~(EMAC_CPPI_EOQ_BIT); - tail_bd->mode = frame_status; - ++txch->end_of_queue_add; - } - } - txch->active_queue_count++; - rt_sem_release(&priv->tx_lock); - return 0; + tail_bd = txch->active_queue_tail; + tail_bd->next = curr_bd; + txch->active_queue_tail = curr_bd; + tail_bd = EMAC_VIRT_NOCACHE(tail_bd); + tail_bd->h_next = (int)emac_virt_to_phys(curr_bd); + frame_status = tail_bd->mode; + if (frame_status & EMAC_CPPI_EOQ_BIT) { + emac_write(EMAC_TXHDP(ch), emac_virt_to_phys(curr_bd)); + frame_status &= ~(EMAC_CPPI_EOQ_BIT); + tail_bd->mode = frame_status; + ++txch->end_of_queue_add; + } + } + txch->active_queue_count++; + rt_sem_release(&priv->tx_lock); + return 0; } /** @@ -639,40 +625,40 @@ try: */ static int emac_dev_xmit(struct pbuf *p, struct emac_priv *priv) { - int ret_code; - struct emac_netbufobj tx_buf; /* buffer obj-only single frame support */ - struct emac_netpktobj tx_packet; /* packet object */ + int ret_code; + struct emac_netbufobj tx_buf; /* buffer obj-only single frame support */ + struct emac_netpktobj tx_packet; /* packet object */ - /* If no link, return */ - if (!priv->link) { - rt_kprintf("DaVinci EMAC: No link to transmit\n"); - return -RT_EBUSY; - } + /* If no link, return */ + if (!priv->link) { + rt_kprintf("DaVinci EMAC: No link to transmit\n"); + return -RT_EBUSY; + } - /* Build the buffer and packet objects - Since only single fragment is - * supported, need not set length and token in both packet & object. - * Doing so for completeness sake & to show that this needs to be done - * in multifragment case - */ - tx_packet.buf_list = &tx_buf; - tx_packet.num_bufs = 1; /* only single fragment supported */ - tx_packet.pkt_length = p->len; - tx_packet.pkt_token = (void *)p; - tx_buf.length = p->len; - tx_buf.buf_token = (void *)p; - tx_buf.data_ptr = p->payload; - EMAC_CACHE_WRITEBACK((unsigned long)p->payload, p->len); - ret_code = emac_send(priv, &tx_packet, EMAC_DEF_TX_CH); - if (ret_code != 0) { - if (ret_code == EMAC_ERR_TX_OUT_OF_BD) { - rt_kprintf("DaVinci EMAC: xmit() fatal"\ - " err. Out of TX BD's\n"); - } - priv->net_dev_stats.tx_dropped++; - return -RT_EBUSY; - } + /* Build the buffer and packet objects - Since only single fragment is + * supported, need not set length and token in both packet & object. + * Doing so for completeness sake & to show that this needs to be done + * in multifragment case + */ + tx_packet.buf_list = &tx_buf; + tx_packet.num_bufs = 1; /* only single fragment supported */ + tx_packet.pkt_length = p->len; + tx_packet.pkt_token = (void *)p; + tx_buf.length = p->len; + tx_buf.buf_token = (void *)p; + tx_buf.data_ptr = p->payload; + EMAC_CACHE_WRITEBACK((unsigned long)p->payload, p->len); + ret_code = emac_send(priv, &tx_packet, EMAC_DEF_TX_CH); + if (ret_code != 0) { + if (ret_code == EMAC_ERR_TX_OUT_OF_BD) { + rt_kprintf("DaVinci EMAC: xmit() fatal"\ + " err. Out of TX BD's\n"); + } + priv->net_dev_stats.tx_dropped++; + return -RT_EBUSY; + } - return RT_EOK; + return RT_EOK; } /** @@ -685,15 +671,15 @@ static int emac_dev_xmit(struct pbuf *p, struct emac_priv *priv) */ static void emac_cleanup_txch(struct emac_priv *priv, rt_uint32_t ch) { - struct emac_txch *txch = priv->txch[ch]; + struct emac_txch *txch = priv->txch[ch]; - if (txch) { - if (txch->bd_mem) - txch->bd_mem = NULL; - rt_free(txch->tx_complete); - rt_free(txch); - priv->txch[ch] = NULL; - } + if (txch) { + if (txch->bd_mem) + txch->bd_mem = NULL; + rt_free(txch->tx_complete); + rt_free(txch); + priv->txch[ch] = NULL; + } } @@ -709,15 +695,15 @@ static void emac_cleanup_txch(struct emac_priv *priv, rt_uint32_t ch) */ static void emac_dev_tx_timeout(struct emac_priv *priv) { - rt_kprintf("emac tx timeout.\n"); - priv->net_dev_stats.tx_errors++; - emac_int_disable(priv); - emac_stop_txch(priv, EMAC_DEF_TX_CH); - emac_cleanup_txch(priv, EMAC_DEF_TX_CH); - emac_init_txch(priv, EMAC_DEF_TX_CH); - emac_write(EMAC_TXHDP(0), 0); - emac_write(EMAC_TXINTMASKSET, BIT(EMAC_DEF_TX_CH)); - emac_int_enable(priv); + rt_kprintf("emac tx timeout.\n"); + priv->net_dev_stats.tx_errors++; + emac_int_disable(priv); + emac_stop_txch(priv, EMAC_DEF_TX_CH); + emac_cleanup_txch(priv, EMAC_DEF_TX_CH); + emac_init_txch(priv, EMAC_DEF_TX_CH); + emac_write(EMAC_TXHDP(0), 0); + emac_write(EMAC_TXINTMASKSET, BIT(EMAC_DEF_TX_CH)); + emac_int_enable(priv); } @@ -725,16 +711,16 @@ static void emac_dev_tx_timeout(struct emac_priv *priv) /* transmit packet. */ rt_err_t rt_davinci_emac_tx( rt_device_t dev, struct pbuf* p) { - rt_err_t err; - struct emac_priv *priv = dev->user_data; + rt_err_t err; + struct emac_priv *priv = dev->user_data; - err = emac_dev_xmit(p, priv); - if (err != RT_EOK) - { - emac_dev_tx_timeout(priv); - } + err = emac_dev_xmit(p, priv); + if (err != RT_EOK) + { + emac_dev_tx_timeout(priv); + } - return RT_EOK; + return RT_EOK; } /** @@ -751,49 +737,49 @@ rt_err_t rt_davinci_emac_tx( rt_device_t dev, struct pbuf* p) * */ static void emac_addbd_to_rx_queue(struct emac_priv *priv, rt_uint32_t ch, - struct emac_rx_bd __iomem *curr_bd, - char *buffer, void *buf_token) + struct emac_rx_bd __iomem *curr_bd, + char *buffer, void *buf_token) { - struct emac_rxch *rxch = priv->rxch[ch]; + struct emac_rxch *rxch = priv->rxch[ch]; - /* populate the hardware descriptor */ - curr_bd->h_next = 0; - curr_bd->buff_ptr = virt_to_phys(buffer); - curr_bd->off_b_len = rxch->buf_size; - curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT; - curr_bd->next = RT_NULL; - curr_bd->data_ptr = buffer; - curr_bd->buf_token = buf_token; + /* populate the hardware descriptor */ + curr_bd->h_next = 0; + curr_bd->buff_ptr = virt_to_phys(buffer); + curr_bd->off_b_len = rxch->buf_size; + curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT; + curr_bd->next = RT_NULL; + curr_bd->data_ptr = buffer; + curr_bd->buf_token = buf_token; - /* write back */ - BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); - if (rxch->active_queue_head == RT_NULL) { - rxch->active_queue_head = curr_bd; - rxch->active_queue_tail = curr_bd; - if (0 != rxch->queue_active) { - emac_write(EMAC_RXHDP(ch), - emac_virt_to_phys(rxch->active_queue_head)); - rxch->queue_active = 1; - } - } else { - struct emac_rx_bd __iomem *tail_bd; - rt_uint32_t frame_status; + /* write back */ + BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); + if (rxch->active_queue_head == RT_NULL) { + rxch->active_queue_head = curr_bd; + rxch->active_queue_tail = curr_bd; + if (0 != rxch->queue_active) { + emac_write(EMAC_RXHDP(ch), + emac_virt_to_phys(rxch->active_queue_head)); + rxch->queue_active = 1; + } + } else { + struct emac_rx_bd __iomem *tail_bd; + rt_uint32_t frame_status; - tail_bd = rxch->active_queue_tail; - rxch->active_queue_tail = curr_bd; - tail_bd->next = curr_bd; - tail_bd = EMAC_VIRT_NOCACHE(tail_bd); - tail_bd->h_next = emac_virt_to_phys(curr_bd); - frame_status = tail_bd->mode; - if (frame_status & EMAC_CPPI_EOQ_BIT) { - emac_write(EMAC_RXHDP(ch), - emac_virt_to_phys(curr_bd)); - frame_status &= ~(EMAC_CPPI_EOQ_BIT); - tail_bd->mode = frame_status; - ++rxch->end_of_queue_add; - } - } - ++rxch->recycled_bd; + tail_bd = rxch->active_queue_tail; + rxch->active_queue_tail = curr_bd; + tail_bd->next = curr_bd; + tail_bd = EMAC_VIRT_NOCACHE(tail_bd); + tail_bd->h_next = emac_virt_to_phys(curr_bd); + frame_status = tail_bd->mode; + if (frame_status & EMAC_CPPI_EOQ_BIT) { + emac_write(EMAC_RXHDP(ch), + emac_virt_to_phys(curr_bd)); + frame_status &= ~(EMAC_CPPI_EOQ_BIT); + tail_bd->mode = frame_status; + ++rxch->end_of_queue_add; + } + } + ++rxch->recycled_bd; } /** @@ -807,22 +793,22 @@ static void emac_addbd_to_rx_queue(struct emac_priv *priv, rt_uint32_t ch, * Returns success or appropriate error code (none as of now) */ static int emac_net_rx_cb(struct emac_priv *priv, - struct emac_netpktobj *net_pkt_list) + struct emac_netpktobj *net_pkt_list) { - struct eth_device *device = &priv->parent; - struct pbuf *p; - p = (struct pbuf *)net_pkt_list->pkt_token; - /* set length of packet */ - p->tot_len = net_pkt_list->pkt_length; - p->len = net_pkt_list->pkt_length; - EMAC_CACHE_INVALIDATE((unsigned long)p->payload, p->len); - if (device->netif->input(p, device->netif) != RT_EOK) - { - pbuf_free(p); - } - priv->net_dev_stats.rx_bytes += net_pkt_list->pkt_length; - priv->net_dev_stats.rx_packets++; - return 0; + struct eth_device *device = &priv->parent; + struct pbuf *p; + p = (struct pbuf *)net_pkt_list->pkt_token; + /* set length of packet */ + p->tot_len = net_pkt_list->pkt_length; + p->len = net_pkt_list->pkt_length; + EMAC_CACHE_INVALIDATE((unsigned long)p->payload, p->len); + if (device->netif->input(p, device->netif) != RT_EOK) + { + pbuf_free(p); + } + priv->net_dev_stats.rx_bytes += net_pkt_list->pkt_length; + priv->net_dev_stats.rx_packets++; + return 0; } /** @@ -838,20 +824,20 @@ static int emac_net_rx_cb(struct emac_priv *priv, * Returns pbuf data pointer or 0 on failure to alloc pbuf */ static void *emac_net_alloc_rx_buf(struct emac_priv *priv, int buf_size, - void **data_token, rt_uint32_t ch) + void **data_token, rt_uint32_t ch) { - struct pbuf* p; + struct pbuf* p; - p = pbuf_alloc(PBUF_LINK, buf_size, PBUF_RAM); - if (RT_NULL == p) { - rt_kprintf("DaVinci EMAC: failed to alloc pbuf\n"); - return RT_NULL; - } + p = pbuf_alloc(PBUF_LINK, buf_size, PBUF_RAM); + if (RT_NULL == p) { + rt_kprintf("DaVinci EMAC: failed to alloc pbuf\n"); + return RT_NULL; + } - /* set device pointer in p and reserve space for extra bytes */ - *data_token = (void *) p; - EMAC_CACHE_WRITEBACK_INVALIDATE((unsigned long)p->payload, buf_size); - return p->payload; + /* set device pointer in p and reserve space for extra bytes */ + *data_token = (void *) p; + EMAC_CACHE_WRITEBACK_INVALIDATE((unsigned long)p->payload, buf_size); + return p->payload; } @@ -871,160 +857,160 @@ static void *emac_net_alloc_rx_buf(struct emac_priv *priv, int buf_size, */ static int emac_rx_bdproc(struct emac_priv *priv, rt_uint32_t ch, rt_uint32_t budget) { - unsigned long flags; - rt_uint32_t frame_status; - rt_uint32_t pkts_processed = 0; - char *new_buffer; - struct emac_rx_bd __iomem *curr_bd; - struct emac_rx_bd __iomem *last_bd; - struct emac_netpktobj *curr_pkt, pkt_obj; - struct emac_netbufobj buf_obj; - struct emac_netbufobj *rx_buf_obj; - void *new_buf_token; - struct emac_rxch *rxch = priv->rxch[ch]; + unsigned long flags; + rt_uint32_t frame_status; + rt_uint32_t pkts_processed = 0; + char *new_buffer; + struct emac_rx_bd __iomem *curr_bd; + struct emac_rx_bd __iomem *last_bd; + struct emac_netpktobj *curr_pkt, pkt_obj; + struct emac_netbufobj buf_obj; + struct emac_netbufobj *rx_buf_obj; + void *new_buf_token; + struct emac_rxch *rxch = priv->rxch[ch]; - if (1 == rxch->teardown_pending) - return 0; - ++rxch->proc_count; - rt_sem_take(&priv->rx_lock, RT_WAITING_FOREVER); - pkt_obj.buf_list = &buf_obj; - curr_pkt = &pkt_obj; - curr_bd = rxch->active_queue_head; - BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); - frame_status = curr_bd->mode; + if (1 == rxch->teardown_pending) + return 0; + ++rxch->proc_count; + rt_sem_take(&priv->rx_lock, RT_WAITING_FOREVER); + pkt_obj.buf_list = &buf_obj; + curr_pkt = &pkt_obj; + curr_bd = rxch->active_queue_head; + BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); + frame_status = curr_bd->mode; - while ((curr_bd) && - ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) && - (pkts_processed < budget)) { + while ((curr_bd) && + ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) && + (pkts_processed < budget)) { - new_buffer = emac_net_alloc_rx_buf(priv, rxch->buf_size, - &new_buf_token, EMAC_DEF_RX_CH); - if (RT_NULL == new_buffer) { - ++rxch->out_of_rx_buffers; - goto end_emac_rx_bdproc; - } + new_buffer = emac_net_alloc_rx_buf(priv, rxch->buf_size, + &new_buf_token, EMAC_DEF_RX_CH); + if (RT_NULL == new_buffer) { + ++rxch->out_of_rx_buffers; + goto end_emac_rx_bdproc; + } - /* populate received packet data structure */ - rx_buf_obj = &curr_pkt->buf_list[0]; - rx_buf_obj->data_ptr = (char *)curr_bd->data_ptr; - rx_buf_obj->length = curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE; - rx_buf_obj->buf_token = curr_bd->buf_token; - curr_pkt->pkt_token = curr_pkt->buf_list->buf_token; - curr_pkt->num_bufs = 1; - curr_pkt->pkt_length = - (frame_status & EMAC_RX_BD_PKT_LENGTH_MASK); - emac_write(EMAC_RXCP(ch), emac_virt_to_phys(curr_bd)); - ++rxch->processed_bd; - last_bd = curr_bd; - curr_bd = last_bd->next; - rxch->active_queue_head = curr_bd; + /* populate received packet data structure */ + rx_buf_obj = &curr_pkt->buf_list[0]; + rx_buf_obj->data_ptr = (char *)curr_bd->data_ptr; + rx_buf_obj->length = curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE; + rx_buf_obj->buf_token = curr_bd->buf_token; + curr_pkt->pkt_token = curr_pkt->buf_list->buf_token; + curr_pkt->num_bufs = 1; + curr_pkt->pkt_length = + (frame_status & EMAC_RX_BD_PKT_LENGTH_MASK); + emac_write(EMAC_RXCP(ch), emac_virt_to_phys(curr_bd)); + ++rxch->processed_bd; + last_bd = curr_bd; + curr_bd = last_bd->next; + rxch->active_queue_head = curr_bd; - /* check if end of RX queue ? */ - if (frame_status & EMAC_CPPI_EOQ_BIT) { - if (curr_bd) { - ++rxch->mis_queued_packets; - emac_write(EMAC_RXHDP(ch), - emac_virt_to_phys(curr_bd)); - } else { - ++rxch->end_of_queue; - rxch->queue_active = 0; - } - } + /* check if end of RX queue ? */ + if (frame_status & EMAC_CPPI_EOQ_BIT) { + if (curr_bd) { + ++rxch->mis_queued_packets; + emac_write(EMAC_RXHDP(ch), + emac_virt_to_phys(curr_bd)); + } else { + ++rxch->end_of_queue; + rxch->queue_active = 0; + } + } - /* recycle BD */ - emac_addbd_to_rx_queue(priv, ch, last_bd, new_buffer, - new_buf_token); + /* recycle BD */ + emac_addbd_to_rx_queue(priv, ch, last_bd, new_buffer, + new_buf_token); - /* return the packet to the user - BD ptr passed in - * last parameter for potential *future* use */ - rt_sem_release(&priv->rx_lock); - emac_net_rx_cb(priv, curr_pkt);//??? - rt_sem_take(&priv->rx_lock, RT_WAITING_FOREVER); - curr_bd = rxch->active_queue_head; - if (curr_bd) { - BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); - frame_status = curr_bd->mode; - } - ++pkts_processed; - } + /* return the packet to the user - BD ptr passed in + * last parameter for potential *future* use */ + rt_sem_release(&priv->rx_lock); + emac_net_rx_cb(priv, curr_pkt);//??? + rt_sem_take(&priv->rx_lock, RT_WAITING_FOREVER); + curr_bd = rxch->active_queue_head; + if (curr_bd) { + BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE); + frame_status = curr_bd->mode; + } + ++pkts_processed; + } end_emac_rx_bdproc: - rt_sem_release(&priv->rx_lock); - return pkts_processed; + rt_sem_release(&priv->rx_lock); + return pkts_processed; } /* reception packet. */ struct pbuf *rt_davinci_emac_rx(rt_device_t dev) { - struct emac_priv *priv = dev->user_data; - struct pbuf* p = RT_NULL; - rt_uint32_t len; - void *buffer; + struct emac_priv *priv = dev->user_data; + struct pbuf* p = RT_NULL; + rt_uint32_t len; + void *buffer; - struct pbuf* q; - rt_uint8_t *buf = RT_NULL; - unsigned int mask; - rt_uint32_t status = 0; - rt_uint32_t num_pkts = 0; + struct pbuf* q; + rt_uint8_t *buf = RT_NULL; + unsigned int mask; + rt_uint32_t status = 0; + rt_uint32_t num_pkts = 0; - /* Check interrupt vectors and call packet processing */ - status = emac_read(EMAC_MACINVECTOR); + /* Check interrupt vectors and call packet processing */ + status = emac_read(EMAC_MACINVECTOR); - mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC; + mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC; - if (priv->version == EMAC_VERSION_2) - mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC; + if (priv->version == EMAC_VERSION_2) + mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC; - if (status & mask) { - num_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH, - EMAC_DEF_TX_MAX_SERVICE); - } /* TX processing */ + if (status & mask) { + num_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH, + EMAC_DEF_TX_MAX_SERVICE); + } /* TX processing */ - /*if (num_pkts) - //return budget; - return RT_NULL;*/ + /*if (num_pkts) + //return budget; + return RT_NULL;*/ - mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC; + mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC; - if (priv->version == EMAC_VERSION_2) - mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC; + if (priv->version == EMAC_VERSION_2) + mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC; - if (status & mask) { - num_pkts = emac_rx_bdproc(priv, EMAC_DEF_RX_CH, EMAC_DEF_RX_MAX_SERVICE); - } /* RX processing */ + if (status & mask) { + num_pkts = emac_rx_bdproc(priv, EMAC_DEF_RX_CH, EMAC_DEF_RX_MAX_SERVICE); + } /* RX processing */ - /*if (num_pkts < EMAC_DEF_RX_MAX_SERVICE) { - emac_int_enable(priv); - }*/ + /*if (num_pkts < EMAC_DEF_RX_MAX_SERVICE) { + emac_int_enable(priv); + }*/ - mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT; - if (priv->version == EMAC_VERSION_2) - mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT; + mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT; + if (priv->version == EMAC_VERSION_2) + mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT; - if (status & mask) { - rt_uint32_t ch, cause; - rt_kprintf("DaVinci EMAC: Fatal Hardware Error\n"); + if (status & mask) { + rt_uint32_t ch, cause; + rt_kprintf("DaVinci EMAC: Fatal Hardware Error\n"); - status = emac_read(EMAC_MACSTATUS); - cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >> - EMAC_MACSTATUS_TXERRCODE_SHIFT); - if (cause) { - ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >> - EMAC_MACSTATUS_TXERRCH_SHIFT); - } - cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >> - EMAC_MACSTATUS_RXERRCODE_SHIFT); - if (cause) { - ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >> - EMAC_MACSTATUS_RXERRCH_SHIFT); - } - } /* Host error processing */ + status = emac_read(EMAC_MACSTATUS); + cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >> + EMAC_MACSTATUS_TXERRCODE_SHIFT); + if (cause) { + ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >> + EMAC_MACSTATUS_TXERRCH_SHIFT); + } + cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >> + EMAC_MACSTATUS_RXERRCODE_SHIFT); + if (cause) { + ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >> + EMAC_MACSTATUS_RXERRCH_SHIFT); + } + } /* Host error processing */ - //return num_pkts; - //return p; - emac_int_enable(priv); - return RT_NULL; + //return num_pkts; + //return p; + emac_int_enable(priv); + return RT_NULL; } @@ -1040,19 +1026,19 @@ struct pbuf *rt_davinci_emac_rx(rt_device_t dev) */ static void emac_set_type0addr(struct emac_priv *priv, rt_uint32_t ch, char *mac_addr) { - rt_uint32_t val; - val = ((mac_addr[5] << 8) | (mac_addr[4])); - emac_write(EMAC_MACSRCADDRLO, val); + rt_uint32_t val; + val = ((mac_addr[5] << 8) | (mac_addr[4])); + emac_write(EMAC_MACSRCADDRLO, val); - val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ - (mac_addr[1] << 8) | (mac_addr[0])); - emac_write(EMAC_MACSRCADDRHI, val); - val = emac_read(EMAC_RXUNICASTSET); - val |= BIT(ch); - emac_write(EMAC_RXUNICASTSET, val); - val = emac_read(EMAC_RXUNICASTCLEAR); - val &= ~BIT(ch); - emac_write(EMAC_RXUNICASTCLEAR, val); + val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ + (mac_addr[1] << 8) | (mac_addr[0])); + emac_write(EMAC_MACSRCADDRHI, val); + val = emac_read(EMAC_RXUNICASTSET); + val |= BIT(ch); + emac_write(EMAC_RXUNICASTSET, val); + val = emac_read(EMAC_RXUNICASTCLEAR); + val &= ~BIT(ch); + emac_write(EMAC_RXUNICASTCLEAR, val); } /** @@ -1067,14 +1053,14 @@ static void emac_set_type0addr(struct emac_priv *priv, rt_uint32_t ch, char *mac */ static void emac_set_type1addr(struct emac_priv *priv, rt_uint32_t ch, char *mac_addr) { - rt_uint32_t val; - emac_write(EMAC_MACINDEX, ch); - val = ((mac_addr[5] << 8) | mac_addr[4]); - emac_write(EMAC_MACADDRLO, val); - val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ - (mac_addr[1] << 8) | (mac_addr[0])); - emac_write(EMAC_MACADDRHI, val); - emac_set_type0addr(priv, ch, mac_addr); + rt_uint32_t val; + emac_write(EMAC_MACINDEX, ch); + val = ((mac_addr[5] << 8) | mac_addr[4]); + emac_write(EMAC_MACADDRLO, val); + val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ + (mac_addr[1] << 8) | (mac_addr[0])); + emac_write(EMAC_MACADDRHI, val); + emac_set_type0addr(priv, ch, mac_addr); } /** @@ -1090,17 +1076,17 @@ static void emac_set_type1addr(struct emac_priv *priv, rt_uint32_t ch, char *mac * Returns success (0) or appropriate error code (none as of now) */ static void emac_set_type2addr(struct emac_priv *priv, rt_uint32_t ch, - char *mac_addr, int index, int match) + char *mac_addr, int index, int match) { - rt_uint32_t val; - emac_write(EMAC_MACINDEX, index); - val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ - (mac_addr[1] << 8) | (mac_addr[0])); - emac_write(EMAC_MACADDRHI, val); - val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \ - (match << 19) | BIT(20)); - emac_write(EMAC_MACADDRLO, val); - emac_set_type0addr(priv, ch, mac_addr); + rt_uint32_t val; + emac_write(EMAC_MACINDEX, index); + val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ + (mac_addr[1] << 8) | (mac_addr[0])); + emac_write(EMAC_MACADDRHI, val); + val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \ + (match << 19) | BIT(20)); + emac_write(EMAC_MACADDRLO, val); + emac_set_type0addr(priv, ch, mac_addr); } /** @@ -1115,18 +1101,18 @@ static void emac_set_type2addr(struct emac_priv *priv, rt_uint32_t ch, */ static void emac_setmac(struct emac_priv *priv, rt_uint32_t ch, char *mac_addr) { - if (priv->rx_addr_type == 0) { - emac_set_type0addr(priv, ch, mac_addr); - } else if (priv->rx_addr_type == 1) { - rt_uint32_t cnt; - for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++) - emac_set_type1addr(priv, ch, mac_addr); - } else if (priv->rx_addr_type == 2) { - emac_set_type2addr(priv, ch, mac_addr, ch, 1); - emac_set_type0addr(priv, ch, mac_addr); - } else { - rt_kprintf("DaVinci EMAC: Wrong addressing\n"); - } + if (priv->rx_addr_type == 0) { + emac_set_type0addr(priv, ch, mac_addr); + } else if (priv->rx_addr_type == 1) { + rt_uint32_t cnt; + for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++) + emac_set_type1addr(priv, ch, mac_addr); + } else if (priv->rx_addr_type == 2) { + emac_set_type2addr(priv, ch, mac_addr, ch, 1); + emac_set_type0addr(priv, ch, mac_addr); + } else { + rt_kprintf("DaVinci EMAC: Wrong addressing\n"); + } } @@ -1139,9 +1125,9 @@ static void emac_setmac(struct emac_priv *priv, rt_uint32_t ch, char *mac_addr) * pointer to the memory * */ -#define EMAC_TX_BD_MEM(priv) ((priv)->emac_ctrl_ram) -#define EMAC_RX_BD_MEM(priv) ((priv)->emac_ctrl_ram + \ - (((priv)->ctrl_ram_size) >> 1)) +#define EMAC_TX_BD_MEM(priv) ((priv)->emac_ctrl_ram) +#define EMAC_RX_BD_MEM(priv) ((priv)->emac_ctrl_ram + \ + (((priv)->ctrl_ram_size) >> 1)) /** * emac_init_txch: TX channel initialization @@ -1155,59 +1141,59 @@ static void emac_setmac(struct emac_priv *priv, rt_uint32_t ch, char *mac_addr) */ static int emac_init_txch(struct emac_priv *priv, rt_uint32_t ch) { - rt_uint32_t cnt, bd_size; - void __iomem *mem; - struct emac_tx_bd __iomem *curr_bd; - struct emac_txch *txch = RT_NULL; + rt_uint32_t cnt, bd_size; + void __iomem *mem; + struct emac_tx_bd __iomem *curr_bd; + struct emac_txch *txch = RT_NULL; - txch = rt_malloc(sizeof(struct emac_txch)); - if (RT_NULL == txch) { - rt_kprintf("DaVinci EMAC: TX Ch mem alloc failed"); - return -RT_ENOMEM; - } - rt_memset(txch, 0, sizeof(struct emac_txch)); - priv->txch[ch] = txch; - txch->service_max = EMAC_DEF_TX_MAX_SERVICE; - txch->active_queue_head = RT_NULL; - txch->active_queue_tail = RT_NULL; - txch->queue_active = 0; - txch->teardown_pending = 0; + txch = rt_malloc(sizeof(struct emac_txch)); + if (RT_NULL == txch) { + rt_kprintf("DaVinci EMAC: TX Ch mem alloc failed"); + return -RT_ENOMEM; + } + rt_memset(txch, 0, sizeof(struct emac_txch)); + priv->txch[ch] = txch; + txch->service_max = EMAC_DEF_TX_MAX_SERVICE; + txch->active_queue_head = RT_NULL; + txch->active_queue_tail = RT_NULL; + txch->queue_active = 0; + txch->teardown_pending = 0; - /* allocate memory for TX CPPI channel on a 4 byte boundry */ - txch->tx_complete = rt_malloc(txch->service_max * sizeof(rt_uint32_t)); - if (RT_NULL == txch->tx_complete) { - rt_kprintf("DaVinci EMAC: Tx service mem alloc failed"); - rt_free(txch); - return -RT_ENOMEM; - } - memset(txch->tx_complete, 0, txch->service_max * sizeof(rt_uint32_t)); + /* allocate memory for TX CPPI channel on a 4 byte boundry */ + txch->tx_complete = rt_malloc(txch->service_max * sizeof(rt_uint32_t)); + if (RT_NULL == txch->tx_complete) { + rt_kprintf("DaVinci EMAC: Tx service mem alloc failed"); + rt_free(txch); + return -RT_ENOMEM; + } + memset(txch->tx_complete, 0, txch->service_max * sizeof(rt_uint32_t)); - /* allocate buffer descriptor pool align every BD on four word - * boundry for future requirements */ - bd_size = (sizeof(struct emac_tx_bd) + 0xF) & ~0xF; - txch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size; - txch->alloc_size = (((bd_size * txch->num_bd) + 0xF) & ~0xF); + /* allocate buffer descriptor pool align every BD on four word + * boundry for future requirements */ + bd_size = (sizeof(struct emac_tx_bd) + 0xF) & ~0xF; + txch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size; + txch->alloc_size = (((bd_size * txch->num_bd) + 0xF) & ~0xF); - /* alloc TX BD memory */ - txch->bd_mem = EMAC_TX_BD_MEM(priv); - rt_memset((void *)txch->bd_mem, 0, txch->alloc_size); + /* alloc TX BD memory */ + txch->bd_mem = EMAC_TX_BD_MEM(priv); + rt_memset((void *)txch->bd_mem, 0, txch->alloc_size); - /* initialize the BD linked list */ - mem = (void __iomem *) - (((rt_uint32_t) txch->bd_mem + 0xF) & ~0xF); - txch->bd_pool_head = RT_NULL; - for (cnt = 0; cnt < txch->num_bd; cnt++) { - curr_bd = mem + (cnt * bd_size); - curr_bd->next = txch->bd_pool_head; - txch->bd_pool_head = curr_bd; - } + /* initialize the BD linked list */ + mem = (void __iomem *) + (((rt_uint32_t) txch->bd_mem + 0xF) & ~0xF); + txch->bd_pool_head = RT_NULL; + for (cnt = 0; cnt < txch->num_bd; cnt++) { + curr_bd = mem + (cnt * bd_size); + curr_bd->next = txch->bd_pool_head; + txch->bd_pool_head = curr_bd; + } - /* reset statistics counters */ - txch->out_of_tx_bd = 0; - txch->no_active_pkts = 0; - txch->active_queue_count = 0; + /* reset statistics counters */ + txch->out_of_tx_bd = 0; + txch->no_active_pkts = 0; + txch->active_queue_count = 0; - return 0; + return 0; } /** @@ -1223,74 +1209,74 @@ static int emac_init_txch(struct emac_priv *priv, rt_uint32_t ch) */ static int emac_init_rxch(struct emac_priv *priv, rt_uint32_t ch, char *param) { - rt_uint32_t cnt, bd_size; - void __iomem *mem; - struct emac_rx_bd __iomem *curr_bd; - struct emac_rxch *rxch = RT_NULL; + rt_uint32_t cnt, bd_size; + void __iomem *mem; + struct emac_rx_bd __iomem *curr_bd; + struct emac_rxch *rxch = RT_NULL; - rxch = rt_malloc(sizeof(struct emac_rxch)); - if (RT_NULL == rxch) { - rt_kprintf("DaVinci EMAC: RX Ch mem alloc failed"); - return -ENOMEM; - } - rt_memset(rxch, 0, sizeof(struct emac_rxch)); - priv->rxch[ch] = rxch; - rxch->buf_size = priv->rx_buf_size; - rxch->service_max = EMAC_DEF_RX_MAX_SERVICE; - rxch->queue_active = 0; - rxch->teardown_pending = 0; + rxch = rt_malloc(sizeof(struct emac_rxch)); + if (RT_NULL == rxch) { + rt_kprintf("DaVinci EMAC: RX Ch mem alloc failed"); + return -ENOMEM; + } + rt_memset(rxch, 0, sizeof(struct emac_rxch)); + priv->rxch[ch] = rxch; + rxch->buf_size = priv->rx_buf_size; + rxch->service_max = EMAC_DEF_RX_MAX_SERVICE; + rxch->queue_active = 0; + rxch->teardown_pending = 0; - /* save mac address */ - for (cnt = 0; cnt < 6; cnt++) - rxch->mac_addr[cnt] = param[cnt]; + /* save mac address */ + for (cnt = 0; cnt < 6; cnt++) + rxch->mac_addr[cnt] = param[cnt]; - /* allocate buffer descriptor pool align every BD on four word - * boundry for future requirements */ - bd_size = (sizeof(struct emac_rx_bd) + 0xF) & ~0xF; - rxch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size; - rxch->alloc_size = (((bd_size * rxch->num_bd) + 0xF) & ~0xF); - rxch->bd_mem = EMAC_RX_BD_MEM(priv); + /* allocate buffer descriptor pool align every BD on four word + * boundry for future requirements */ + bd_size = (sizeof(struct emac_rx_bd) + 0xF) & ~0xF; + rxch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size; + rxch->alloc_size = (((bd_size * rxch->num_bd) + 0xF) & ~0xF); + rxch->bd_mem = EMAC_RX_BD_MEM(priv); - rt_memset((void *)rxch->bd_mem, 0, rxch->alloc_size); - rxch->pkt_queue.buf_list = &rxch->buf_queue; + rt_memset((void *)rxch->bd_mem, 0, rxch->alloc_size); + rxch->pkt_queue.buf_list = &rxch->buf_queue; - /* allocate RX buffer and initialize the BD linked list */ - mem = (void __iomem *) - (((rt_uint32_t) rxch->bd_mem + 0xF) & ~0xF); - rxch->active_queue_head = RT_NULL; - rxch->active_queue_tail = mem; - for (cnt = 0; cnt < rxch->num_bd; cnt++) { - curr_bd = mem + (cnt * bd_size); - /* for future use the last parameter contains the BD ptr */ - curr_bd->data_ptr = emac_net_alloc_rx_buf(priv, - rxch->buf_size, - (void **)&curr_bd->buf_token, - EMAC_DEF_RX_CH); - if (curr_bd->data_ptr == RT_NULL) { - rt_kprintf("DaVinci EMAC: RX buf mem alloc " \ - "failed for ch %d\n", ch); - rt_free(rxch); - return -RT_ENOMEM; - } + /* allocate RX buffer and initialize the BD linked list */ + mem = (void __iomem *) + (((rt_uint32_t) rxch->bd_mem + 0xF) & ~0xF); + rxch->active_queue_head = RT_NULL; + rxch->active_queue_tail = mem; + for (cnt = 0; cnt < rxch->num_bd; cnt++) { + curr_bd = mem + (cnt * bd_size); + /* for future use the last parameter contains the BD ptr */ + curr_bd->data_ptr = emac_net_alloc_rx_buf(priv, + rxch->buf_size, + (void **)&curr_bd->buf_token, + EMAC_DEF_RX_CH); + if (curr_bd->data_ptr == RT_NULL) { + rt_kprintf("DaVinci EMAC: RX buf mem alloc " \ + "failed for ch %d\n", ch); + rt_free(rxch); + return -RT_ENOMEM; + } - /* populate the hardware descriptor */ - curr_bd->h_next = emac_virt_to_phys(rxch->active_queue_head); - curr_bd->buff_ptr = virt_to_phys(curr_bd->data_ptr); - curr_bd->off_b_len = rxch->buf_size; - curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT; + /* populate the hardware descriptor */ + curr_bd->h_next = emac_virt_to_phys(rxch->active_queue_head); + curr_bd->buff_ptr = virt_to_phys(curr_bd->data_ptr); + curr_bd->off_b_len = rxch->buf_size; + curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT; - /* write back to hardware memory */ - BD_CACHE_WRITEBACK_INVALIDATE((rt_uint32_t) curr_bd, - EMAC_BD_LENGTH_FOR_CACHE); - curr_bd->next = rxch->active_queue_head; - rxch->active_queue_head = curr_bd; - } + /* write back to hardware memory */ + BD_CACHE_WRITEBACK_INVALIDATE((rt_uint32_t) curr_bd, + EMAC_BD_LENGTH_FOR_CACHE); + curr_bd->next = rxch->active_queue_head; + rxch->active_queue_head = curr_bd; + } - /* At this point rxCppi->activeQueueHead points to the first - RX BD ready to be given to RX HDP and rxch->active_queue_tail - points to the last RX BD - */ - return 0; + /* At this point rxCppi->activeQueueHead points to the first + RX BD ready to be given to RX HDP and rxch->active_queue_tail + points to the last RX BD + */ + return 0; } @@ -1303,23 +1289,23 @@ static int emac_init_rxch(struct emac_priv *priv, rt_uint32_t ch, char *param) */ static void emac_int_disable(struct emac_priv *priv) { - if (priv->version == EMAC_VERSION_2) { - unsigned long flags; + if (priv->version == EMAC_VERSION_2) { + unsigned long flags; - rt_interrupt_enter(); + rt_interrupt_enter(); - /* Program C0_Int_En to zero to turn off - * interrupts to the CPU */ - emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0); - emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0); - /* NOTE: Rx Threshold and Misc interrupts are not disabled */ + /* Program C0_Int_En to zero to turn off + * interrupts to the CPU */ + emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0); + emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0); + /* NOTE: Rx Threshold and Misc interrupts are not disabled */ - rt_interrupt_leave(); + rt_interrupt_leave(); - } else { - /* Set DM644x control registers for interrupt control */ - emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0); - } + } else { + /* Set DM644x control registers for interrupt control */ + emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0); + } } @@ -1332,31 +1318,31 @@ static void emac_int_disable(struct emac_priv *priv) */ static void emac_int_enable(struct emac_priv *priv) { - if (priv->version == EMAC_VERSION_2) { - /*if (priv->int_enable) - priv->int_enable();*/ + if (priv->version == EMAC_VERSION_2) { + /*if (priv->int_enable) + priv->int_enable();*/ - emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff); - emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff); + emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff); + emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff); - /* In addition to turning on interrupt Enable, we need - * ack by writing appropriate values to the EOI - * register */ + /* In addition to turning on interrupt Enable, we need + * ack by writing appropriate values to the EOI + * register */ - /* NOTE: Rx Threshold and Misc interrupts are not enabled */ + /* NOTE: Rx Threshold and Misc interrupts are not enabled */ - /* ack rxen only then a new pulse will be generated */ - emac_write(EMAC_DM646X_MACEOIVECTOR, - EMAC_DM646X_MAC_EOI_C0_RXEN); + /* ack rxen only then a new pulse will be generated */ + emac_write(EMAC_DM646X_MACEOIVECTOR, + EMAC_DM646X_MAC_EOI_C0_RXEN); - /* ack txen- only then a new pulse will be generated */ - emac_write(EMAC_DM646X_MACEOIVECTOR, - EMAC_DM646X_MAC_EOI_C0_TXEN); + /* ack txen- only then a new pulse will be generated */ + emac_write(EMAC_DM646X_MACEOIVECTOR, + EMAC_DM646X_MAC_EOI_C0_TXEN); - } else { - /* Set DM644x control registers for interrupt control */ - emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1); - } + } else { + /* Set DM644x control registers for interrupt control */ + emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1); + } } @@ -1368,11 +1354,11 @@ static void emac_int_enable(struct emac_priv *priv) */ static void emac_irq(int irq, void *param) { - struct emac_priv *priv = param; + struct emac_priv *priv = param; - ++priv->isr_count; - emac_int_disable(priv); - eth_device_ready(&priv->parent); + ++priv->isr_count; + emac_int_disable(priv); + eth_device_ready(&priv->parent); } @@ -1388,77 +1374,77 @@ static void emac_irq(int irq, void *param) */ static int emac_hw_enable(struct emac_priv *priv) { - rt_uint32_t ch, val, mbp_enable, mac_control; + rt_uint32_t ch, val, mbp_enable, mac_control; - /* Soft reset */ - emac_write(EMAC_SOFTRESET, 1); - while (emac_read(EMAC_SOFTRESET)); + /* Soft reset */ + emac_write(EMAC_SOFTRESET, 1); + while (emac_read(EMAC_SOFTRESET)); - /* Disable interrupt & Set pacing for more interrupts initially */ - emac_int_disable(priv); + /* Disable interrupt & Set pacing for more interrupts initially */ + emac_int_disable(priv); - /* Full duplex enable bit set when auto negotiation happens */ - mac_control = - (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) | - ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) | - ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) | - ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0)); - emac_write(EMAC_MACCONTROL, mac_control); + /* Full duplex enable bit set when auto negotiation happens */ + mac_control = + (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) | + ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) | + ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) | + ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0)); + emac_write(EMAC_MACCONTROL, mac_control); - mbp_enable = - (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) | - ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) | - ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) | - ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) | - ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) | - ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) | - ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) | - ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \ - EMAC_RXMBP_PROMCH_SHIFT) | - ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) | - ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \ - EMAC_RXMBP_BROADCH_SHIFT) | - ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) | - ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \ - EMAC_RXMBP_MULTICH_SHIFT)); - emac_write(EMAC_RXMBPENABLE, mbp_enable); - emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE & - EMAC_RX_MAX_LEN_MASK)); - emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET & - EMAC_RX_BUFFER_OFFSET_MASK)); - emac_write(EMAC_RXFILTERLOWTHRESH, 0); - emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL); - priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF; + mbp_enable = + (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) | + ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) | + ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) | + ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) | + ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) | + ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) | + ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) | + ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \ + EMAC_RXMBP_PROMCH_SHIFT) | + ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) | + ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \ + EMAC_RXMBP_BROADCH_SHIFT) | + ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) | + ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \ + EMAC_RXMBP_MULTICH_SHIFT)); + emac_write(EMAC_RXMBPENABLE, mbp_enable); + emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE & + EMAC_RX_MAX_LEN_MASK)); + emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET & + EMAC_RX_BUFFER_OFFSET_MASK)); + emac_write(EMAC_RXFILTERLOWTHRESH, 0); + emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL); + priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF; - val = emac_read(EMAC_TXCONTROL); - val |= EMAC_TX_CONTROL_TX_ENABLE_VAL; - emac_write(EMAC_TXCONTROL, val); - val = emac_read(EMAC_RXCONTROL); - val |= EMAC_RX_CONTROL_RX_ENABLE_VAL; - emac_write(EMAC_RXCONTROL, val); - emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL); + val = emac_read(EMAC_TXCONTROL); + val |= EMAC_TX_CONTROL_TX_ENABLE_VAL; + emac_write(EMAC_TXCONTROL, val); + val = emac_read(EMAC_RXCONTROL); + val |= EMAC_RX_CONTROL_RX_ENABLE_VAL; + emac_write(EMAC_RXCONTROL, val); + emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL); - for (ch = 0; ch < EMAC_DEF_MAX_TX_CH; ch++) { - emac_write(EMAC_TXHDP(ch), 0); - emac_write(EMAC_TXINTMASKSET, BIT(ch)); - } - for (ch = 0; ch < EMAC_DEF_MAX_RX_CH; ch++) { - struct emac_rxch *rxch = priv->rxch[ch]; - emac_setmac(priv, ch, rxch->mac_addr); - emac_write(EMAC_RXINTMASKSET, BIT(ch)); - rxch->queue_active = 1; - emac_write(EMAC_RXHDP(ch), - (unsigned int)(rxch->active_queue_head)); /* physcal addr */ - } + for (ch = 0; ch < EMAC_DEF_MAX_TX_CH; ch++) { + emac_write(EMAC_TXHDP(ch), 0); + emac_write(EMAC_TXINTMASKSET, BIT(ch)); + } + for (ch = 0; ch < EMAC_DEF_MAX_RX_CH; ch++) { + struct emac_rxch *rxch = priv->rxch[ch]; + emac_setmac(priv, ch, rxch->mac_addr); + emac_write(EMAC_RXINTMASKSET, BIT(ch)); + rxch->queue_active = 1; + emac_write(EMAC_RXHDP(ch), + (unsigned int)(rxch->active_queue_head)); /* physcal addr */ + } - /* Enable MII */ - val = emac_read(EMAC_MACCONTROL); - val |= (EMAC_MACCONTROL_GMIIEN); - emac_write(EMAC_MACCONTROL, val); + /* Enable MII */ + val = emac_read(EMAC_MACCONTROL); + val |= (EMAC_MACCONTROL_GMIIEN); + emac_write(EMAC_MACCONTROL, val); - /* Enable interrupts */ - emac_int_enable(priv); - return 0; + /* Enable interrupts */ + emac_int_enable(priv); + return 0; } @@ -1472,51 +1458,51 @@ static int emac_hw_enable(struct emac_priv *priv) */ static struct net_device_stats *emac_dev_getnetstats(struct emac_priv *priv) { - rt_uint32_t mac_control; - rt_uint32_t stats_clear_mask; + rt_uint32_t mac_control; + rt_uint32_t stats_clear_mask; - /* update emac hardware stats and reset the registers*/ + /* update emac hardware stats and reset the registers*/ - mac_control = emac_read(EMAC_MACCONTROL); + mac_control = emac_read(EMAC_MACCONTROL); - if (mac_control & EMAC_MACCONTROL_GMIIEN) - stats_clear_mask = EMAC_STATS_CLR_MASK; - else - stats_clear_mask = 0; + if (mac_control & EMAC_MACCONTROL_GMIIEN) + stats_clear_mask = EMAC_STATS_CLR_MASK; + else + stats_clear_mask = 0; - priv->net_dev_stats.multicast += emac_read(EMAC_RXMCASTFRAMES); - emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask); + priv->net_dev_stats.multicast += emac_read(EMAC_RXMCASTFRAMES); + emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask); - priv->net_dev_stats.collisions += (emac_read(EMAC_TXCOLLISION) + - emac_read(EMAC_TXSINGLECOLL) + - emac_read(EMAC_TXMULTICOLL)); - emac_write(EMAC_TXCOLLISION, stats_clear_mask); - emac_write(EMAC_TXSINGLECOLL, stats_clear_mask); - emac_write(EMAC_TXMULTICOLL, stats_clear_mask); + priv->net_dev_stats.collisions += (emac_read(EMAC_TXCOLLISION) + + emac_read(EMAC_TXSINGLECOLL) + + emac_read(EMAC_TXMULTICOLL)); + emac_write(EMAC_TXCOLLISION, stats_clear_mask); + emac_write(EMAC_TXSINGLECOLL, stats_clear_mask); + emac_write(EMAC_TXMULTICOLL, stats_clear_mask); - priv->net_dev_stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) + - emac_read(EMAC_RXJABBER) + - emac_read(EMAC_RXUNDERSIZED)); - emac_write(EMAC_RXOVERSIZED, stats_clear_mask); - emac_write(EMAC_RXJABBER, stats_clear_mask); - emac_write(EMAC_RXUNDERSIZED, stats_clear_mask); + priv->net_dev_stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) + + emac_read(EMAC_RXJABBER) + + emac_read(EMAC_RXUNDERSIZED)); + emac_write(EMAC_RXOVERSIZED, stats_clear_mask); + emac_write(EMAC_RXJABBER, stats_clear_mask); + emac_write(EMAC_RXUNDERSIZED, stats_clear_mask); - priv->net_dev_stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) + - emac_read(EMAC_RXMOFOVERRUNS)); - emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask); - emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask); + priv->net_dev_stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) + + emac_read(EMAC_RXMOFOVERRUNS)); + emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask); + emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask); - priv->net_dev_stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS); - emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask); + priv->net_dev_stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS); + emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask); - priv->net_dev_stats.tx_carrier_errors += - emac_read(EMAC_TXCARRIERSENSE); - emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask); + priv->net_dev_stats.tx_carrier_errors += + emac_read(EMAC_TXCARRIERSENSE); + emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask); - priv->net_dev_stats.tx_fifo_errors = emac_read(EMAC_TXUNDERRUN); - emac_write(EMAC_TXUNDERRUN, stats_clear_mask); + priv->net_dev_stats.tx_fifo_errors = emac_read(EMAC_TXUNDERRUN); + emac_write(EMAC_TXUNDERRUN, stats_clear_mask); - return &priv->net_dev_stats; + return &priv->net_dev_stats; } @@ -1525,164 +1511,164 @@ static struct net_device_stats *emac_dev_getnetstats(struct emac_priv *priv) static rt_err_t rt_davinci_emac_init(rt_device_t dev) { - struct emac_priv *priv = dev->user_data; - unsigned long paddr; - rt_uint32_t ch, rc; - int i; + struct emac_priv *priv = dev->user_data; + unsigned long paddr; + rt_uint32_t ch, rc; + int i; - /* Configuration items */ - priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN; + /* Configuration items */ + priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN; - /* Clear basic hardware */ - for (ch = 0; ch < EMAC_MAX_TXRX_CHANNELS; ch++) { - emac_write(EMAC_TXHDP(ch), 0); - emac_write(EMAC_RXHDP(ch), 0); - emac_write(EMAC_RXHDP(ch), 0); - emac_write(EMAC_RXINTMASKCLEAR, EMAC_INT_MASK_CLEAR); - emac_write(EMAC_TXINTMASKCLEAR, EMAC_INT_MASK_CLEAR); - } - priv->mac_hash1 = 0; - priv->mac_hash2 = 0; - emac_write(EMAC_MACHASH1, 0); - emac_write(EMAC_MACHASH2, 0); + /* Clear basic hardware */ + for (ch = 0; ch < EMAC_MAX_TXRX_CHANNELS; ch++) { + emac_write(EMAC_TXHDP(ch), 0); + emac_write(EMAC_RXHDP(ch), 0); + emac_write(EMAC_RXHDP(ch), 0); + emac_write(EMAC_RXINTMASKCLEAR, EMAC_INT_MASK_CLEAR); + emac_write(EMAC_TXINTMASKCLEAR, EMAC_INT_MASK_CLEAR); + } + priv->mac_hash1 = 0; + priv->mac_hash2 = 0; + emac_write(EMAC_MACHASH1, 0); + emac_write(EMAC_MACHASH2, 0); - /* multi ch not supported - open 1 TX, 1RX ch by default */ - rc = emac_init_txch(priv, EMAC_DEF_TX_CH); - if (0 != rc) { - rt_kprintf("DaVinci EMAC: emac_init_txch() failed"); - return rc; - } - rc = emac_init_rxch(priv, EMAC_DEF_RX_CH, priv->mac_addr); - if (0 != rc) { - rt_kprintf("DaVinci EMAC: emac_init_rxch() failed"); - return rc; - } + /* multi ch not supported - open 1 TX, 1RX ch by default */ + rc = emac_init_txch(priv, EMAC_DEF_TX_CH); + if (0 != rc) { + rt_kprintf("DaVinci EMAC: emac_init_txch() failed"); + return rc; + } + rc = emac_init_rxch(priv, EMAC_DEF_RX_CH, priv->mac_addr); + if (0 != rc) { + rt_kprintf("DaVinci EMAC: emac_init_rxch() failed"); + return rc; + } - rt_hw_interrupt_install(IRQ_DM365_EMAC_RXPULSE, emac_irq, - (void *)priv, "EMAC_RXPULSE"); - rt_hw_interrupt_umask(IRQ_DM365_EMAC_RXPULSE); - rt_hw_interrupt_install(IRQ_DM365_EMAC_TXPULSE, emac_irq, - (void *)priv, "EMAC_TXPULSE"); - rt_hw_interrupt_umask(IRQ_DM365_EMAC_TXPULSE); - rt_hw_interrupt_install(IRQ_DM365_EMAC_RXTHRESH, emac_irq, - (void *)priv, "EMAC_RXTHRESH"); - rt_hw_interrupt_umask(IRQ_DM365_EMAC_RXTHRESH); - rt_hw_interrupt_install(IRQ_DM365_EMAC_MISCPULSE, emac_irq, - (void *)priv, "EMAC_MISCPULSE"); - rt_hw_interrupt_umask(IRQ_DM365_EMAC_MISCPULSE); + rt_hw_interrupt_install(IRQ_DM365_EMAC_RXPULSE, emac_irq, + (void *)priv, "EMAC_RXPULSE"); + rt_hw_interrupt_umask(IRQ_DM365_EMAC_RXPULSE); + rt_hw_interrupt_install(IRQ_DM365_EMAC_TXPULSE, emac_irq, + (void *)priv, "EMAC_TXPULSE"); + rt_hw_interrupt_umask(IRQ_DM365_EMAC_TXPULSE); + rt_hw_interrupt_install(IRQ_DM365_EMAC_RXTHRESH, emac_irq, + (void *)priv, "EMAC_RXTHRESH"); + rt_hw_interrupt_umask(IRQ_DM365_EMAC_RXTHRESH); + rt_hw_interrupt_install(IRQ_DM365_EMAC_MISCPULSE, emac_irq, + (void *)priv, "EMAC_MISCPULSE"); + rt_hw_interrupt_umask(IRQ_DM365_EMAC_MISCPULSE); - emac_mii_reset(priv); - davinci_emac_phy_init(dev); + emac_mii_reset(priv); + davinci_emac_phy_init(dev); - /* Start/Enable EMAC hardware */ - emac_hw_enable(priv); + /* Start/Enable EMAC hardware */ + emac_hw_enable(priv); - rt_timer_init(&priv->timer, "link_timer", - davinci_emac_update_link, - (void *)priv, - RT_TICK_PER_SECOND, - RT_TIMER_FLAG_PERIODIC); + rt_timer_init(&priv->timer, "link_timer", + davinci_emac_update_link, + (void *)priv, + RT_TICK_PER_SECOND, + RT_TIMER_FLAG_PERIODIC); - rt_timer_start(&priv->timer); - rt_kprintf("davinci emac initialized\n"); - - return RT_EOK; + rt_timer_start(&priv->timer); + rt_kprintf("davinci emac initialized\n"); + + return RT_EOK; } static rt_err_t rt_davinci_emac_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } static rt_err_t rt_davinci_emac_close(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_size_t rt_davinci_emac_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_size_t rt_davinci_emac_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_err_t rt_davinci_emac_control(rt_device_t dev, int cmd, void *args) { - struct emac_priv *priv = dev->user_data; - switch(cmd) - { - case NIOCTL_GADDR: - /* get mac address */ - if(args) rt_memcpy(args, priv->mac_addr, 6); - else return -RT_ERROR; - break; + struct emac_priv *priv = dev->user_data; + switch(cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if(args) rt_memcpy(args, priv->mac_addr, 6); + else return -RT_ERROR; + break; - default : - break; - } + default : + break; + } - return RT_EOK; + return RT_EOK; } void dm365_emac_gpio_init(void) { - rt_uint32_t arm_intmux; + rt_uint32_t arm_intmux; - /* - * EMAC interrupts are multiplexed with GPIO interrupts - * Details are available at the DM365 ARM - * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134 - */ - arm_intmux = davinci_readl(DM365_ARM_INTMUX); - arm_intmux |= (1 << 14)|(1 << 15)|(1 << 16)|(1 << 17); - davinci_writel(arm_intmux, DM365_ARM_INTMUX); + /* + * EMAC interrupts are multiplexed with GPIO interrupts + * Details are available at the DM365 ARM + * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134 + */ + arm_intmux = davinci_readl(DM365_ARM_INTMUX); + arm_intmux |= (1 << 14)|(1 << 15)|(1 << 16)|(1 << 17); + davinci_writel(arm_intmux, DM365_ARM_INTMUX); } int rt_hw_davinci_emac_init() { - struct emac_priv *priv = &davinci_emac_device; - struct clk *emac_clk; - emac_clk = clk_get("EMACCLK"); - emac_bus_frequency = clk_get_rate(emac_clk); - psc_change_state(DAVINCI_DM365_LPSC_CPGMAC, PSC_ENABLE); - dm365_emac_gpio_init(); - rt_memset(&davinci_emac_device, 0, sizeof(davinci_emac_device)); - davinci_emac_device.emac_base = (void __iomem *)DM365_EMAC_CNTRL_BASE; - davinci_emac_device.ctrl_base = (void __iomem *)DM365_EMAC_WRAP_CNTRL_BASE; - davinci_emac_device.ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE; - davinci_emac_device.emac_ctrl_ram = (void __iomem *)DM365_EMAC_WRAP_RAM_BASE; - davinci_emac_device.mdio_base = (void __iomem *)DM365_EMAC_MDIO_BASE; - davinci_emac_device.version = EMAC_VERSION_2; - davinci_emac_device.rmii_en = 0; - davinci_emac_device.phy_addr = 0x09; - rt_sem_init(&priv->tx_lock, "tx_lock", 1, RT_IPC_FLAG_FIFO); - rt_sem_init(&priv->rx_lock, "rx_lock", 1, RT_IPC_FLAG_FIFO); + struct emac_priv *priv = &davinci_emac_device; + struct clk *emac_clk; + emac_clk = clk_get("EMACCLK"); + emac_bus_frequency = clk_get_rate(emac_clk); + psc_change_state(DAVINCI_DM365_LPSC_CPGMAC, PSC_ENABLE); + dm365_emac_gpio_init(); + rt_memset(&davinci_emac_device, 0, sizeof(davinci_emac_device)); + davinci_emac_device.emac_base = (void __iomem *)DM365_EMAC_CNTRL_BASE; + davinci_emac_device.ctrl_base = (void __iomem *)DM365_EMAC_WRAP_CNTRL_BASE; + davinci_emac_device.ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE; + davinci_emac_device.emac_ctrl_ram = (void __iomem *)DM365_EMAC_WRAP_RAM_BASE; + davinci_emac_device.mdio_base = (void __iomem *)DM365_EMAC_MDIO_BASE; + davinci_emac_device.version = EMAC_VERSION_2; + davinci_emac_device.rmii_en = 0; + davinci_emac_device.phy_addr = 0x09; + rt_sem_init(&priv->tx_lock, "tx_lock", 1, RT_IPC_FLAG_FIFO); + rt_sem_init(&priv->rx_lock, "rx_lock", 1, RT_IPC_FLAG_FIFO); - davinci_emac_device.mac_addr[0] = 0x00; - davinci_emac_device.mac_addr[1] = 0x60; - davinci_emac_device.mac_addr[2] = 0x6E; - davinci_emac_device.mac_addr[3] = 0x11; - davinci_emac_device.mac_addr[4] = 0x22; - davinci_emac_device.mac_addr[5] = 0x33; - - davinci_emac_device.parent.parent.init = rt_davinci_emac_init; - davinci_emac_device.parent.parent.open = rt_davinci_emac_open; - davinci_emac_device.parent.parent.close = rt_davinci_emac_close; - davinci_emac_device.parent.parent.read = rt_davinci_emac_read; - davinci_emac_device.parent.parent.write = rt_davinci_emac_write; - davinci_emac_device.parent.parent.control = rt_davinci_emac_control; - davinci_emac_device.parent.parent.user_data = &davinci_emac_device; + davinci_emac_device.mac_addr[0] = 0x00; + davinci_emac_device.mac_addr[1] = 0x60; + davinci_emac_device.mac_addr[2] = 0x6E; + davinci_emac_device.mac_addr[3] = 0x11; + davinci_emac_device.mac_addr[4] = 0x22; + davinci_emac_device.mac_addr[5] = 0x33; - davinci_emac_device.parent.eth_rx = rt_davinci_emac_rx; - davinci_emac_device.parent.eth_tx = rt_davinci_emac_tx; + davinci_emac_device.parent.parent.init = rt_davinci_emac_init; + davinci_emac_device.parent.parent.open = rt_davinci_emac_open; + davinci_emac_device.parent.parent.close = rt_davinci_emac_close; + davinci_emac_device.parent.parent.read = rt_davinci_emac_read; + davinci_emac_device.parent.parent.write = rt_davinci_emac_write; + davinci_emac_device.parent.parent.control = rt_davinci_emac_control; + davinci_emac_device.parent.parent.user_data = &davinci_emac_device; + + davinci_emac_device.parent.eth_rx = rt_davinci_emac_rx; + davinci_emac_device.parent.eth_tx = rt_davinci_emac_tx; + + eth_device_init(&(davinci_emac_device.parent), "e0"); - eth_device_init(&(davinci_emac_device.parent), "e0"); - } INIT_DEVICE_EXPORT(rt_hw_davinci_emac_init); @@ -1693,68 +1679,68 @@ INIT_DEVICE_EXPORT(rt_hw_davinci_emac_init); void dump_emac_stats(void) { - int i; - struct emac_priv *emac; - struct net_device_stats *stats; - rt_device_t dev = rt_device_find("e0"); + int i; + struct emac_priv *emac; + struct net_device_stats *stats; + rt_device_t dev = rt_device_find("e0"); - if(dev == RT_NULL) - return; + if(dev == RT_NULL) + return; - emac = (struct emac_priv *)dev->user_data; + emac = (struct emac_priv *)dev->user_data; - stats = emac_dev_getnetstats(emac); - rt_kprintf("rx_packets = %d\n" - "tx_packets = %d\n" - "rx_bytes = %d\n" - "tx_bytes = %d\n" - "rx_errors = %d\n" - "tx_errors = %d\n" - "rx_dropped = %d\n" - "tx_dropped = %d\n" - "multicast = %d\n" - "collisions = %d\n", - stats->rx_packets, - stats->tx_packets, - stats->rx_bytes, - stats->tx_bytes, - stats->rx_errors, - stats->tx_errors, - stats->rx_dropped, - stats->tx_dropped, - stats->multicast, - stats->collisions); + stats = emac_dev_getnetstats(emac); + rt_kprintf("rx_packets = %d\n" + "tx_packets = %d\n" + "rx_bytes = %d\n" + "tx_bytes = %d\n" + "rx_errors = %d\n" + "tx_errors = %d\n" + "rx_dropped = %d\n" + "tx_dropped = %d\n" + "multicast = %d\n" + "collisions = %d\n", + stats->rx_packets, + stats->tx_packets, + stats->rx_bytes, + stats->tx_bytes, + stats->rx_errors, + stats->tx_errors, + stats->rx_dropped, + stats->tx_dropped, + stats->multicast, + stats->collisions); - rt_kprintf("rx_length_errors = %d\n" - "rx_over_errors = %d\n" - "rx_crc_errors = %d\n" - "rx_frame_errors = %d\n" - "rx_fifo_errors = %d\n" - "rx_missed_errors = %d\n", - stats->rx_length_errors, - stats->rx_over_errors, - stats->rx_crc_errors, - stats->rx_frame_errors, - stats->rx_fifo_errors, - stats->rx_missed_errors); + rt_kprintf("rx_length_errors = %d\n" + "rx_over_errors = %d\n" + "rx_crc_errors = %d\n" + "rx_frame_errors = %d\n" + "rx_fifo_errors = %d\n" + "rx_missed_errors = %d\n", + stats->rx_length_errors, + stats->rx_over_errors, + stats->rx_crc_errors, + stats->rx_frame_errors, + stats->rx_fifo_errors, + stats->rx_missed_errors); - rt_kprintf("tx_aborted_errors = %d\n" - "tx_carrier_errors = %d\n" - "tx_fifo_errors = %d\n" - "tx_heartbeat_errors = %d\n" - "tx_window_errors = %d\n", - stats->tx_aborted_errors, - stats->tx_carrier_errors, - stats->tx_fifo_errors, - stats->tx_heartbeat_errors, - stats->tx_window_errors); + rt_kprintf("tx_aborted_errors = %d\n" + "tx_carrier_errors = %d\n" + "tx_fifo_errors = %d\n" + "tx_heartbeat_errors = %d\n" + "tx_window_errors = %d\n", + stats->tx_aborted_errors, + stats->tx_carrier_errors, + stats->tx_fifo_errors, + stats->tx_heartbeat_errors, + stats->tx_window_errors); - rt_kprintf("rx_compressed = %d\n" - "tx_compressed = %d\n", - stats->rx_compressed, - stats->tx_compressed); + rt_kprintf("rx_compressed = %d\n" + "tx_compressed = %d\n", + stats->rx_compressed, + stats->tx_compressed); - rt_kprintf("\n"); + rt_kprintf("\n"); } FINSH_FUNCTION_EXPORT(dump_emac_stats, dump emac statistics); @@ -1762,8 +1748,8 @@ FINSH_FUNCTION_EXPORT(dump_emac_stats, dump emac statistics); #ifdef FINSH_USING_MSH int cmd_dump_emac_stats(int argc, char** argv) { - dump_emac_stats(); - return 0; + dump_emac_stats(); + return 0; } FINSH_FUNCTION_EXPORT_ALIAS(cmd_dump_emac_stats, __cmd_dump_emac_stats, dump emac statistics.); #endif diff --git a/bsp/dm365/drivers/davinci_emac.h b/bsp/dm365/drivers/davinci_emac.h index 026323c286..1d80c754c9 100644 --- a/bsp/dm365/drivers/davinci_emac.h +++ b/bsp/dm365/drivers/davinci_emac.h @@ -1,25 +1,11 @@ /* - * File : davinci_emac.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2013-01-30 weety first version + * Date Author Notes + * 2013-01-30 weety first version */ #ifndef _DAVINCI_EMAC_H @@ -31,249 +17,249 @@ #endif enum { - EMAC_VERSION_1, /* DM644x */ - EMAC_VERSION_2, /* DM646x */ + EMAC_VERSION_1, /* DM644x */ + EMAC_VERSION_2, /* DM646x */ }; #define __iomem -#define BIT(nr) (1UL << (nr)) +#define BIT(nr) (1UL << (nr)) /* Configuration items */ -#define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC upto frames */ -#define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */ -#define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */ -#define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */ -#define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */ -#define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */ -#define EMAC_DEF_PROM_EN (0) /* Promiscous disabled */ -#define EMAC_DEF_PROM_CH (0) /* Promiscous channel is 0 */ -#define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */ -#define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */ -#define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */ -#define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */ +#define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC upto frames */ +#define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */ +#define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */ +#define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */ +#define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */ +#define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */ +#define EMAC_DEF_PROM_EN (0) /* Promiscous disabled */ +#define EMAC_DEF_PROM_CH (0) /* Promiscous channel is 0 */ +#define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */ +#define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */ +#define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */ +#define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */ -#define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */ -#define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/ +#define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */ +#define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/ -#define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */ -#define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */ -#define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4) -#define EMAC_DEF_TX_CH (0) /* Default 0th channel */ -#define EMAC_DEF_RX_CH (0) /* Default 0th channel */ -#define EMAC_DEF_MDIO_TICK_MS (10) /* typically 1 tick=1 ms) */ -#define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */ -#define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */ -#define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */ +#define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */ +#define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */ +#define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4) +#define EMAC_DEF_TX_CH (0) /* Default 0th channel */ +#define EMAC_DEF_RX_CH (0) /* Default 0th channel */ +#define EMAC_DEF_MDIO_TICK_MS (10) /* typically 1 tick=1 ms) */ +#define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */ +#define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */ +#define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */ /* Buffer descriptor parameters */ -#define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */ -#define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */ +#define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */ +#define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */ /* EMAC register related defines */ -#define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF) -#define EMAC_NUM_MULTICAST_BITS (64) -#define EMAC_TEARDOWN_VALUE (0xFFFFFFFC) -#define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1) -#define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1) -#define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2) -#define EMAC_RX_UNICAST_CLEAR_ALL (0xFF) -#define EMAC_INT_MASK_CLEAR (0xFF) +#define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF) +#define EMAC_NUM_MULTICAST_BITS (64) +#define EMAC_TEARDOWN_VALUE (0xFFFFFFFC) +#define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1) +#define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1) +#define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2) +#define EMAC_RX_UNICAST_CLEAR_ALL (0xFF) +#define EMAC_INT_MASK_CLEAR (0xFF) /* RX MBP register bit positions */ -#define EMAC_RXMBP_PASSCRC_MASK BIT(30) -#define EMAC_RXMBP_QOSEN_MASK BIT(29) -#define EMAC_RXMBP_NOCHAIN_MASK BIT(28) -#define EMAC_RXMBP_CMFEN_MASK BIT(24) -#define EMAC_RXMBP_CSFEN_MASK BIT(23) -#define EMAC_RXMBP_CEFEN_MASK BIT(22) -#define EMAC_RXMBP_CAFEN_MASK BIT(21) -#define EMAC_RXMBP_PROMCH_SHIFT (16) -#define EMAC_RXMBP_PROMCH_MASK (0x7 << 16) -#define EMAC_RXMBP_BROADEN_MASK BIT(13) -#define EMAC_RXMBP_BROADCH_SHIFT (8) -#define EMAC_RXMBP_BROADCH_MASK (0x7 << 8) -#define EMAC_RXMBP_MULTIEN_MASK BIT(5) -#define EMAC_RXMBP_MULTICH_SHIFT (0) -#define EMAC_RXMBP_MULTICH_MASK (0x7) -#define EMAC_RXMBP_CHMASK (0x7) +#define EMAC_RXMBP_PASSCRC_MASK BIT(30) +#define EMAC_RXMBP_QOSEN_MASK BIT(29) +#define EMAC_RXMBP_NOCHAIN_MASK BIT(28) +#define EMAC_RXMBP_CMFEN_MASK BIT(24) +#define EMAC_RXMBP_CSFEN_MASK BIT(23) +#define EMAC_RXMBP_CEFEN_MASK BIT(22) +#define EMAC_RXMBP_CAFEN_MASK BIT(21) +#define EMAC_RXMBP_PROMCH_SHIFT (16) +#define EMAC_RXMBP_PROMCH_MASK (0x7 << 16) +#define EMAC_RXMBP_BROADEN_MASK BIT(13) +#define EMAC_RXMBP_BROADCH_SHIFT (8) +#define EMAC_RXMBP_BROADCH_MASK (0x7 << 8) +#define EMAC_RXMBP_MULTIEN_MASK BIT(5) +#define EMAC_RXMBP_MULTICH_SHIFT (0) +#define EMAC_RXMBP_MULTICH_MASK (0x7) +#define EMAC_RXMBP_CHMASK (0x7) /* EMAC register definitions/bit maps used */ -# define EMAC_MBP_RXPROMISC (0x00200000) -# define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16) -# define EMAC_MBP_RXBCAST (0x00002000) -# define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8) -# define EMAC_MBP_RXMCAST (0x00000020) -# define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7) +# define EMAC_MBP_RXPROMISC (0x00200000) +# define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16) +# define EMAC_MBP_RXBCAST (0x00002000) +# define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8) +# define EMAC_MBP_RXMCAST (0x00000020) +# define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7) /* EMAC mac_control register */ -#define EMAC_MACCONTROL_TXPTYPE BIT(9) -#define EMAC_MACCONTROL_TXPACEEN BIT(6) -#define EMAC_MACCONTROL_GMIIEN BIT(5) -#define EMAC_MACCONTROL_GIGABITEN BIT(7) -#define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0) -#define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15) +#define EMAC_MACCONTROL_TXPTYPE BIT(9) +#define EMAC_MACCONTROL_TXPACEEN BIT(6) +#define EMAC_MACCONTROL_GMIIEN BIT(5) +#define EMAC_MACCONTROL_GIGABITEN BIT(7) +#define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0) +#define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15) /* GIGABIT MODE related bits */ -#define EMAC_DM646X_MACCONTORL_GIG BIT(7) -#define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17) +#define EMAC_DM646X_MACCONTORL_GIG BIT(7) +#define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17) /* EMAC mac_status register */ -#define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000) -#define EMAC_MACSTATUS_TXERRCODE_SHIFT (20) -#define EMAC_MACSTATUS_TXERRCH_MASK (0x7) -#define EMAC_MACSTATUS_TXERRCH_SHIFT (16) -#define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000) -#define EMAC_MACSTATUS_RXERRCODE_SHIFT (12) -#define EMAC_MACSTATUS_RXERRCH_MASK (0x7) -#define EMAC_MACSTATUS_RXERRCH_SHIFT (8) +#define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000) +#define EMAC_MACSTATUS_TXERRCODE_SHIFT (20) +#define EMAC_MACSTATUS_TXERRCH_MASK (0x7) +#define EMAC_MACSTATUS_TXERRCH_SHIFT (16) +#define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000) +#define EMAC_MACSTATUS_RXERRCODE_SHIFT (12) +#define EMAC_MACSTATUS_RXERRCH_MASK (0x7) +#define EMAC_MACSTATUS_RXERRCH_SHIFT (8) /* EMAC RX register masks */ -#define EMAC_RX_MAX_LEN_MASK (0xFFFF) -#define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF) +#define EMAC_RX_MAX_LEN_MASK (0xFFFF) +#define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF) /* MAC_IN_VECTOR (0x180) register bit fields */ -#define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17) -#define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16) -#define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8) -#define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0) +#define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17) +#define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16) +#define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8) +#define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0) /** NOTE:: For DM646x the IN_VECTOR has changed */ -#define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH) -#define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH) -#define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26) -#define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27) +#define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH) +#define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH) +#define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26) +#define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27) /* CPPI bit positions */ -#define EMAC_CPPI_SOP_BIT BIT(31) -#define EMAC_CPPI_EOP_BIT BIT(30) -#define EMAC_CPPI_OWNERSHIP_BIT BIT(29) -#define EMAC_CPPI_EOQ_BIT BIT(28) +#define EMAC_CPPI_SOP_BIT BIT(31) +#define EMAC_CPPI_EOP_BIT BIT(30) +#define EMAC_CPPI_OWNERSHIP_BIT BIT(29) +#define EMAC_CPPI_EOQ_BIT BIT(28) #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27) -#define EMAC_CPPI_PASS_CRC_BIT BIT(26) -#define EMAC_RX_BD_BUF_SIZE (0xFFFF) -#define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */ -#define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF) +#define EMAC_CPPI_PASS_CRC_BIT BIT(26) +#define EMAC_RX_BD_BUF_SIZE (0xFFFF) +#define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */ +#define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF) /* Max hardware defines */ -#define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */ +#define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */ #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */ /* EMAC Peripheral Device Register Memory Layout structure */ -#define EMAC_TXIDVER 0x0 -#define EMAC_TXCONTROL 0x4 -#define EMAC_TXTEARDOWN 0x8 -#define EMAC_RXIDVER 0x10 -#define EMAC_RXCONTROL 0x14 -#define EMAC_RXTEARDOWN 0x18 -#define EMAC_TXINTSTATRAW 0x80 -#define EMAC_TXINTSTATMASKED 0x84 -#define EMAC_TXINTMASKSET 0x88 -#define EMAC_TXINTMASKCLEAR 0x8C -#define EMAC_MACINVECTOR 0x90 +#define EMAC_TXIDVER 0x0 +#define EMAC_TXCONTROL 0x4 +#define EMAC_TXTEARDOWN 0x8 +#define EMAC_RXIDVER 0x10 +#define EMAC_RXCONTROL 0x14 +#define EMAC_RXTEARDOWN 0x18 +#define EMAC_TXINTSTATRAW 0x80 +#define EMAC_TXINTSTATMASKED 0x84 +#define EMAC_TXINTMASKSET 0x88 +#define EMAC_TXINTMASKCLEAR 0x8C +#define EMAC_MACINVECTOR 0x90 -#define EMAC_DM646X_MACEOIVECTOR 0x94 +#define EMAC_DM646X_MACEOIVECTOR 0x94 -#define EMAC_RXINTSTATRAW 0xA0 -#define EMAC_RXINTSTATMASKED 0xA4 -#define EMAC_RXINTMASKSET 0xA8 -#define EMAC_RXINTMASKCLEAR 0xAC -#define EMAC_MACINTSTATRAW 0xB0 -#define EMAC_MACINTSTATMASKED 0xB4 -#define EMAC_MACINTMASKSET 0xB8 -#define EMAC_MACINTMASKCLEAR 0xBC +#define EMAC_RXINTSTATRAW 0xA0 +#define EMAC_RXINTSTATMASKED 0xA4 +#define EMAC_RXINTMASKSET 0xA8 +#define EMAC_RXINTMASKCLEAR 0xAC +#define EMAC_MACINTSTATRAW 0xB0 +#define EMAC_MACINTSTATMASKED 0xB4 +#define EMAC_MACINTMASKSET 0xB8 +#define EMAC_MACINTMASKCLEAR 0xBC -#define EMAC_RXMBPENABLE 0x100 -#define EMAC_RXUNICASTSET 0x104 -#define EMAC_RXUNICASTCLEAR 0x108 -#define EMAC_RXMAXLEN 0x10C -#define EMAC_RXBUFFEROFFSET 0x110 -#define EMAC_RXFILTERLOWTHRESH 0x114 +#define EMAC_RXMBPENABLE 0x100 +#define EMAC_RXUNICASTSET 0x104 +#define EMAC_RXUNICASTCLEAR 0x108 +#define EMAC_RXMAXLEN 0x10C +#define EMAC_RXBUFFEROFFSET 0x110 +#define EMAC_RXFILTERLOWTHRESH 0x114 -#define EMAC_MACCONTROL 0x160 -#define EMAC_MACSTATUS 0x164 -#define EMAC_EMCONTROL 0x168 -#define EMAC_FIFOCONTROL 0x16C -#define EMAC_MACCONFIG 0x170 -#define EMAC_SOFTRESET 0x174 -#define EMAC_MACSRCADDRLO 0x1D0 -#define EMAC_MACSRCADDRHI 0x1D4 -#define EMAC_MACHASH1 0x1D8 -#define EMAC_MACHASH2 0x1DC -#define EMAC_MACADDRLO 0x500 -#define EMAC_MACADDRHI 0x504 -#define EMAC_MACINDEX 0x508 +#define EMAC_MACCONTROL 0x160 +#define EMAC_MACSTATUS 0x164 +#define EMAC_EMCONTROL 0x168 +#define EMAC_FIFOCONTROL 0x16C +#define EMAC_MACCONFIG 0x170 +#define EMAC_SOFTRESET 0x174 +#define EMAC_MACSRCADDRLO 0x1D0 +#define EMAC_MACSRCADDRHI 0x1D4 +#define EMAC_MACHASH1 0x1D8 +#define EMAC_MACHASH2 0x1DC +#define EMAC_MACADDRLO 0x500 +#define EMAC_MACADDRHI 0x504 +#define EMAC_MACINDEX 0x508 /* EMAC HDP and Completion registors */ -#define EMAC_TXHDP(ch) (0x600 + (ch * 4)) -#define EMAC_RXHDP(ch) (0x620 + (ch * 4)) -#define EMAC_TXCP(ch) (0x640 + (ch * 4)) -#define EMAC_RXCP(ch) (0x660 + (ch * 4)) +#define EMAC_TXHDP(ch) (0x600 + (ch * 4)) +#define EMAC_RXHDP(ch) (0x620 + (ch * 4)) +#define EMAC_TXCP(ch) (0x640 + (ch * 4)) +#define EMAC_RXCP(ch) (0x660 + (ch * 4)) /* EMAC statistics registers */ -#define EMAC_RXGOODFRAMES 0x200 -#define EMAC_RXBCASTFRAMES 0x204 -#define EMAC_RXMCASTFRAMES 0x208 -#define EMAC_RXPAUSEFRAMES 0x20C -#define EMAC_RXCRCERRORS 0x210 -#define EMAC_RXALIGNCODEERRORS 0x214 -#define EMAC_RXOVERSIZED 0x218 -#define EMAC_RXJABBER 0x21C -#define EMAC_RXUNDERSIZED 0x220 -#define EMAC_RXFRAGMENTS 0x224 -#define EMAC_RXFILTERED 0x228 -#define EMAC_RXQOSFILTERED 0x22C -#define EMAC_RXOCTETS 0x230 -#define EMAC_TXGOODFRAMES 0x234 -#define EMAC_TXBCASTFRAMES 0x238 -#define EMAC_TXMCASTFRAMES 0x23C -#define EMAC_TXPAUSEFRAMES 0x240 -#define EMAC_TXDEFERRED 0x244 -#define EMAC_TXCOLLISION 0x248 -#define EMAC_TXSINGLECOLL 0x24C -#define EMAC_TXMULTICOLL 0x250 -#define EMAC_TXEXCESSIVECOLL 0x254 -#define EMAC_TXLATECOLL 0x258 -#define EMAC_TXUNDERRUN 0x25C -#define EMAC_TXCARRIERSENSE 0x260 -#define EMAC_TXOCTETS 0x264 -#define EMAC_NETOCTETS 0x280 -#define EMAC_RXSOFOVERRUNS 0x284 -#define EMAC_RXMOFOVERRUNS 0x288 -#define EMAC_RXDMAOVERRUNS 0x28C +#define EMAC_RXGOODFRAMES 0x200 +#define EMAC_RXBCASTFRAMES 0x204 +#define EMAC_RXMCASTFRAMES 0x208 +#define EMAC_RXPAUSEFRAMES 0x20C +#define EMAC_RXCRCERRORS 0x210 +#define EMAC_RXALIGNCODEERRORS 0x214 +#define EMAC_RXOVERSIZED 0x218 +#define EMAC_RXJABBER 0x21C +#define EMAC_RXUNDERSIZED 0x220 +#define EMAC_RXFRAGMENTS 0x224 +#define EMAC_RXFILTERED 0x228 +#define EMAC_RXQOSFILTERED 0x22C +#define EMAC_RXOCTETS 0x230 +#define EMAC_TXGOODFRAMES 0x234 +#define EMAC_TXBCASTFRAMES 0x238 +#define EMAC_TXMCASTFRAMES 0x23C +#define EMAC_TXPAUSEFRAMES 0x240 +#define EMAC_TXDEFERRED 0x244 +#define EMAC_TXCOLLISION 0x248 +#define EMAC_TXSINGLECOLL 0x24C +#define EMAC_TXMULTICOLL 0x250 +#define EMAC_TXEXCESSIVECOLL 0x254 +#define EMAC_TXLATECOLL 0x258 +#define EMAC_TXUNDERRUN 0x25C +#define EMAC_TXCARRIERSENSE 0x260 +#define EMAC_TXOCTETS 0x264 +#define EMAC_NETOCTETS 0x280 +#define EMAC_RXSOFOVERRUNS 0x284 +#define EMAC_RXMOFOVERRUNS 0x288 +#define EMAC_RXDMAOVERRUNS 0x28C /* EMAC DM644x control registers */ -#define EMAC_CTRL_EWCTL (0x4) -#define EMAC_CTRL_EWINTTCNT (0x8) +#define EMAC_CTRL_EWCTL (0x4) +#define EMAC_CTRL_EWINTTCNT (0x8) /* EMAC MDIO related */ /* Mask & Control defines */ -#define MDIO_CONTROL_CLKDIV (0xFF) -#define MDIO_CONTROL_ENABLE BIT(30) -#define MDIO_USERACCESS_GO BIT(31) -#define MDIO_USERACCESS_WRITE BIT(30) -#define MDIO_USERACCESS_READ (0) -#define MDIO_USERACCESS_REGADR (0x1F << 21) -#define MDIO_USERACCESS_PHYADR (0x1F << 16) -#define MDIO_USERACCESS_DATA (0xFFFF) -#define MDIO_USERPHYSEL_LINKSEL BIT(7) -#define MDIO_VER_MODID (0xFFFF << 16) -#define MDIO_VER_REVMAJ (0xFF << 8) -#define MDIO_VER_REVMIN (0xFF) +#define MDIO_CONTROL_CLKDIV (0xFF) +#define MDIO_CONTROL_ENABLE BIT(30) +#define MDIO_USERACCESS_GO BIT(31) +#define MDIO_USERACCESS_WRITE BIT(30) +#define MDIO_USERACCESS_READ (0) +#define MDIO_USERACCESS_REGADR (0x1F << 21) +#define MDIO_USERACCESS_PHYADR (0x1F << 16) +#define MDIO_USERACCESS_DATA (0xFFFF) +#define MDIO_USERPHYSEL_LINKSEL BIT(7) +#define MDIO_VER_MODID (0xFFFF << 16) +#define MDIO_VER_REVMAJ (0xFF << 8) +#define MDIO_VER_REVMIN (0xFF) -#define MDIO_USERACCESS(inst) (0x80 + (inst * 8)) -#define MDIO_USERPHYSEL(inst) (0x84 + (inst * 8)) -#define MDIO_CONTROL (0x04) +#define MDIO_USERACCESS(inst) (0x80 + (inst * 8)) +#define MDIO_USERPHYSEL(inst) (0x84 + (inst * 8)) +#define MDIO_CONTROL (0x04) /* EMAC DM646X control module registers */ -#define EMAC_DM646X_CMRXINTEN (0x14) -#define EMAC_DM646X_CMTXINTEN (0x18) +#define EMAC_DM646X_CMRXINTEN (0x14) +#define EMAC_DM646X_CMTXINTEN (0x18) /* EMAC EOI codes for C0 */ -#define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01) -#define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02) +#define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01) +#define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02) /* EMAC Stats Clear Mask */ #define EMAC_STATS_CLR_MASK (0xFFFFFFFF) @@ -283,9 +269,9 @@ enum { * EMAC network buffer data structure */ struct emac_netbufobj { - void *buf_token; - char *data_ptr; - int length; + void *buf_token; + char *data_ptr; + int length; }; /** net_pkt_obj: EMAC network packet data structure @@ -293,10 +279,10 @@ struct emac_netbufobj { * EMAC network packet data structure - supports buffer list (for future) */ struct emac_netpktobj { - void *pkt_token; /* data token may hold tx/rx chan id */ - struct emac_netbufobj *buf_list; /* array of network buffer objects */ - int num_bufs; - int pkt_length; + void *pkt_token; /* data token may hold tx/rx chan id */ + struct emac_netbufobj *buf_list; /* array of network buffer objects */ + int num_bufs; + int pkt_length; }; /** emac_tx_bd: EMAC TX Buffer descriptor data structure @@ -304,12 +290,12 @@ struct emac_netpktobj { * EMAC TX Buffer descriptor data structure */ struct emac_tx_bd { - int h_next; - int buff_ptr; - int off_b_len; - int mode; /* SOP, EOP, ownership, EOQ, teardown,Qstarv, length */ - struct emac_tx_bd __iomem *next; - void *buf_token; + int h_next; + int buff_ptr; + int off_b_len; + int mode; /* SOP, EOP, ownership, EOQ, teardown,Qstarv, length */ + struct emac_tx_bd __iomem *next; + void *buf_token; }; /** emac_txch: EMAC TX Channel data structure @@ -317,29 +303,29 @@ struct emac_tx_bd { * EMAC TX Channel data structure */ struct emac_txch { - /* Config related */ - rt_uint32_t num_bd; - rt_uint32_t service_max; + /* Config related */ + rt_uint32_t num_bd; + rt_uint32_t service_max; - /* CPPI specific */ - rt_uint32_t alloc_size; - void __iomem *bd_mem; - struct emac_tx_bd __iomem *bd_pool_head; - struct emac_tx_bd __iomem *active_queue_head; - struct emac_tx_bd __iomem *active_queue_tail; - struct emac_tx_bd __iomem *last_hw_bdprocessed; - rt_uint32_t queue_active; - rt_uint32_t teardown_pending; - rt_uint32_t *tx_complete; + /* CPPI specific */ + rt_uint32_t alloc_size; + void __iomem *bd_mem; + struct emac_tx_bd __iomem *bd_pool_head; + struct emac_tx_bd __iomem *active_queue_head; + struct emac_tx_bd __iomem *active_queue_tail; + struct emac_tx_bd __iomem *last_hw_bdprocessed; + rt_uint32_t queue_active; + rt_uint32_t teardown_pending; + rt_uint32_t *tx_complete; - /** statistics */ - rt_uint32_t proc_count; /* TX: # of times emac_tx_bdproc is called */ - rt_uint32_t mis_queued_packets; - rt_uint32_t queue_reinit; - rt_uint32_t end_of_queue_add; - rt_uint32_t out_of_tx_bd; - rt_uint32_t no_active_pkts; /* IRQ when there were no packets to process */ - rt_uint32_t active_queue_count; + /** statistics */ + rt_uint32_t proc_count; /* TX: # of times emac_tx_bdproc is called */ + rt_uint32_t mis_queued_packets; + rt_uint32_t queue_reinit; + rt_uint32_t end_of_queue_add; + rt_uint32_t out_of_tx_bd; + rt_uint32_t no_active_pkts; /* IRQ when there were no packets to process */ + rt_uint32_t active_queue_count; }; /** emac_rx_bd: EMAC RX Buffer descriptor data structure @@ -347,13 +333,13 @@ struct emac_txch { * EMAC RX Buffer descriptor data structure */ struct emac_rx_bd { - int h_next; - int buff_ptr; - int off_b_len; - int mode; - struct emac_rx_bd __iomem *next; - void *data_ptr; - void *buf_token; + int h_next; + int buff_ptr; + int off_b_len; + int mode; + struct emac_rx_bd __iomem *next; + void *data_ptr; + void *buf_token; }; /** emac_rxch: EMAC RX Channel data structure @@ -361,68 +347,68 @@ struct emac_rx_bd { * EMAC RX Channel data structure */ struct emac_rxch { - /* configuration info */ - rt_uint32_t num_bd; - rt_uint32_t service_max; - rt_uint32_t buf_size; - char mac_addr[6]; + /* configuration info */ + rt_uint32_t num_bd; + rt_uint32_t service_max; + rt_uint32_t buf_size; + char mac_addr[6]; - /** CPPI specific */ - rt_uint32_t alloc_size; - void __iomem *bd_mem; - struct emac_rx_bd __iomem *bd_pool_head; - struct emac_rx_bd __iomem *active_queue_head; - struct emac_rx_bd __iomem *active_queue_tail; - rt_uint32_t queue_active; - rt_uint32_t teardown_pending; + /** CPPI specific */ + rt_uint32_t alloc_size; + void __iomem *bd_mem; + struct emac_rx_bd __iomem *bd_pool_head; + struct emac_rx_bd __iomem *active_queue_head; + struct emac_rx_bd __iomem *active_queue_tail; + rt_uint32_t queue_active; + rt_uint32_t teardown_pending; - /* packet and buffer objects */ - struct emac_netpktobj pkt_queue; - struct emac_netbufobj buf_queue; + /* packet and buffer objects */ + struct emac_netpktobj pkt_queue; + struct emac_netbufobj buf_queue; - /** statistics */ - rt_uint32_t proc_count; /* number of times emac_rx_bdproc is called */ - rt_uint32_t processed_bd; - rt_uint32_t recycled_bd; - rt_uint32_t out_of_rx_bd; - rt_uint32_t out_of_rx_buffers; - rt_uint32_t queue_reinit; - rt_uint32_t end_of_queue_add; - rt_uint32_t end_of_queue; - rt_uint32_t mis_queued_packets; + /** statistics */ + rt_uint32_t proc_count; /* number of times emac_rx_bdproc is called */ + rt_uint32_t processed_bd; + rt_uint32_t recycled_bd; + rt_uint32_t out_of_rx_bd; + rt_uint32_t out_of_rx_buffers; + rt_uint32_t queue_reinit; + rt_uint32_t end_of_queue_add; + rt_uint32_t end_of_queue; + rt_uint32_t mis_queued_packets; }; struct net_device_stats { - unsigned long rx_packets; /* total packets received */ - unsigned long tx_packets; /* total packets transmitted */ - unsigned long rx_bytes; /* total bytes received */ - unsigned long tx_bytes; /* total bytes transmitted */ - unsigned long rx_errors; /* bad packets received */ - unsigned long tx_errors; /* packet transmit problems */ - unsigned long rx_dropped; /* no space in linux buffers */ - unsigned long tx_dropped; /* no space available in linux */ - unsigned long multicast; /* multicast packets received */ - unsigned long collisions; + unsigned long rx_packets; /* total packets received */ + unsigned long tx_packets; /* total packets transmitted */ + unsigned long rx_bytes; /* total bytes received */ + unsigned long tx_bytes; /* total bytes transmitted */ + unsigned long rx_errors; /* bad packets received */ + unsigned long tx_errors; /* packet transmit problems */ + unsigned long rx_dropped; /* no space in linux buffers */ + unsigned long tx_dropped; /* no space available in linux */ + unsigned long multicast; /* multicast packets received */ + unsigned long collisions; - /* detailed rx_errors: */ - unsigned long rx_length_errors; - unsigned long rx_over_errors; /* receiver ring buff overflow */ - unsigned long rx_crc_errors; /* recved pkt with crc error */ - unsigned long rx_frame_errors; /* recv'd frame alignment error */ - unsigned long rx_fifo_errors; /* recv'r fifo overrun */ - unsigned long rx_missed_errors; /* receiver missed packet */ + /* detailed rx_errors: */ + unsigned long rx_length_errors; + unsigned long rx_over_errors; /* receiver ring buff overflow */ + unsigned long rx_crc_errors; /* recved pkt with crc error */ + unsigned long rx_frame_errors; /* recv'd frame alignment error */ + unsigned long rx_fifo_errors; /* recv'r fifo overrun */ + unsigned long rx_missed_errors; /* receiver missed packet */ - /* detailed tx_errors */ - unsigned long tx_aborted_errors; - unsigned long tx_carrier_errors; - unsigned long tx_fifo_errors; - unsigned long tx_heartbeat_errors; - unsigned long tx_window_errors; - - /* for cslip etc */ - unsigned long rx_compressed; - unsigned long tx_compressed; + /* detailed tx_errors */ + unsigned long tx_aborted_errors; + unsigned long tx_carrier_errors; + unsigned long tx_fifo_errors; + unsigned long tx_heartbeat_errors; + unsigned long tx_window_errors; + + /* for cslip etc */ + unsigned long rx_compressed; + unsigned long tx_compressed; }; @@ -433,44 +419,44 @@ struct net_device_stats #define MAX_ADDR_LEN 6 struct emac_priv { - /* inherit from ethernet device */ - struct eth_device parent; + /* inherit from ethernet device */ + struct eth_device parent; - /* interface address info. */ - rt_uint8_t mac_addr[MAX_ADDR_LEN]; /* hw address */ - unsigned short phy_addr; - - struct rt_semaphore tx_lock; - struct rt_semaphore rx_lock; - void __iomem *remap_addr; - rt_uint32_t emac_base_phys; - void __iomem *emac_base; - void __iomem *ctrl_base; - void __iomem *emac_ctrl_ram; - void __iomem *mdio_base; - rt_uint32_t ctrl_ram_size; - rt_uint32_t hw_ram_addr; - struct emac_txch *txch[EMAC_DEF_MAX_TX_CH]; - struct emac_rxch *rxch[EMAC_DEF_MAX_RX_CH]; - rt_uint32_t link; /* 1=link on, 0=link off */ - rt_uint32_t speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */ - rt_uint32_t duplex; /* Link duplex: 0=Half, 1=Full */ - rt_uint32_t rx_buf_size; - rt_uint32_t isr_count; - rt_uint8_t rmii_en; - rt_uint8_t version; - struct net_device_stats net_dev_stats; - rt_uint32_t mac_hash1; - rt_uint32_t mac_hash2; - rt_uint32_t multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS]; - rt_uint32_t rx_addr_type; - /* periodic timer required for MDIO polling */ - struct rt_timer timer; - rt_uint32_t periodic_ticks; - rt_uint32_t timer_active; - rt_uint32_t phy_mask; - /* mii_bus,phy members */ - struct rt_semaphore lock; + /* interface address info. */ + rt_uint8_t mac_addr[MAX_ADDR_LEN]; /* hw address */ + unsigned short phy_addr; + + struct rt_semaphore tx_lock; + struct rt_semaphore rx_lock; + void __iomem *remap_addr; + rt_uint32_t emac_base_phys; + void __iomem *emac_base; + void __iomem *ctrl_base; + void __iomem *emac_ctrl_ram; + void __iomem *mdio_base; + rt_uint32_t ctrl_ram_size; + rt_uint32_t hw_ram_addr; + struct emac_txch *txch[EMAC_DEF_MAX_TX_CH]; + struct emac_rxch *rxch[EMAC_DEF_MAX_RX_CH]; + rt_uint32_t link; /* 1=link on, 0=link off */ + rt_uint32_t speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */ + rt_uint32_t duplex; /* Link duplex: 0=Half, 1=Full */ + rt_uint32_t rx_buf_size; + rt_uint32_t isr_count; + rt_uint8_t rmii_en; + rt_uint8_t version; + struct net_device_stats net_dev_stats; + rt_uint32_t mac_hash1; + rt_uint32_t mac_hash2; + rt_uint32_t multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS]; + rt_uint32_t rx_addr_type; + /* periodic timer required for MDIO polling */ + struct rt_timer timer; + rt_uint32_t periodic_ticks; + rt_uint32_t timer_active; + rt_uint32_t phy_mask; + /* mii_bus,phy members */ + struct rt_semaphore lock; }; diff --git a/bsp/dm365/drivers/davinci_serial.c b/bsp/dm365/drivers/davinci_serial.c index 0671cb4e49..96118ac347 100644 --- a/bsp/dm365/drivers/davinci_serial.c +++ b/bsp/dm365/drivers/davinci_serial.c @@ -1,25 +1,11 @@ /* - * File : davinci_serial.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ #include @@ -32,35 +18,35 @@ static struct rt_serial_device davinci_serial_dev0; static struct rt_serial_device davinci_serial_dev1; -#define LSR_DR 0x01 /* Data ready */ -#define LSR_THRE 0x20 /* Xmit holding register empty */ -//#define USTAT_TXB_EMPTY 0x02 /* tx buffer empty */ -#define BPS 115200 /* serial baudrate */ +#define LSR_DR 0x01 /* Data ready */ +#define LSR_THRE 0x20 /* Xmit holding register empty */ +//#define USTAT_TXB_EMPTY 0x02 /* tx buffer empty */ +#define BPS 115200 /* serial baudrate */ typedef struct uartport { - volatile rt_uint32_t rbr; - volatile rt_uint32_t ier; - volatile rt_uint32_t fcr; - volatile rt_uint32_t lcr; - volatile rt_uint32_t mcr; - volatile rt_uint32_t lsr; - volatile rt_uint32_t msr; - volatile rt_uint32_t scr; - volatile rt_uint32_t dll; - volatile rt_uint32_t dlh; - - volatile rt_uint32_t res[2]; - volatile rt_uint32_t pwremu_mgmt; - volatile rt_uint32_t mdr; + volatile rt_uint32_t rbr; + volatile rt_uint32_t ier; + volatile rt_uint32_t fcr; + volatile rt_uint32_t lcr; + volatile rt_uint32_t mcr; + volatile rt_uint32_t lsr; + volatile rt_uint32_t msr; + volatile rt_uint32_t scr; + volatile rt_uint32_t dll; + volatile rt_uint32_t dlh; + + volatile rt_uint32_t res[2]; + volatile rt_uint32_t pwremu_mgmt; + volatile rt_uint32_t mdr; }uartport; #define thr rbr #define iir fcr -#define UART0 ((struct uartport *)DAVINCI_UART0_BASE) +#define UART0 ((struct uartport *)DAVINCI_UART0_BASE) -#define UART1 ((struct uartport *)DM365_UART1_BASE) +#define UART1 ((struct uartport *)DM365_UART1_BASE) /** @@ -68,8 +54,8 @@ typedef struct uartport */ void rt_davinci_serial_handler(int vector, void *param) { - struct rt_serial_device *dev = (struct rt_serial_device *)param; - rt_hw_serial_isr(dev, RT_SERIAL_EVENT_RX_IND); + struct rt_serial_device *dev = (struct rt_serial_device *)param; + rt_hw_serial_isr(dev, RT_SERIAL_EVENT_RX_IND); } /** @@ -84,23 +70,23 @@ static rt_err_t davinci_uart_configure(struct rt_serial_device *serial, static rt_err_t davinci_uart_control(struct rt_serial_device *serial, int cmd, void *arg) { - uartport *uart = serial->parent.user_data; + uartport *uart = serial->parent.user_data; switch (cmd) { case RT_DEVICE_CTRL_CLR_INT: /* disable rx irq */ - if (uart == UART0) - rt_hw_interrupt_mask(IRQ_UARTINT0); - else if (uart == UART1) - rt_hw_interrupt_mask(IRQ_UARTINT1); + if (uart == UART0) + rt_hw_interrupt_mask(IRQ_UARTINT0); + else if (uart == UART1) + rt_hw_interrupt_mask(IRQ_UARTINT1); break; case RT_DEVICE_CTRL_SET_INT: /* enable rx irq */ - if (uart == UART0) - rt_hw_interrupt_umask(IRQ_UARTINT0); - else if (uart == UART1) - rt_hw_interrupt_umask(IRQ_UARTINT1); + if (uart == UART0) + rt_hw_interrupt_umask(IRQ_UARTINT0); + else if (uart == UART1) + rt_hw_interrupt_umask(IRQ_UARTINT1); break; } @@ -110,10 +96,10 @@ static rt_err_t davinci_uart_control(struct rt_serial_device *serial, static int davinci_uart_putc(struct rt_serial_device *serial, char c) { rt_uint32_t level; - uartport *uart = serial->parent.user_data; + uartport *uart = serial->parent.user_data; while (!(uart->lsr & LSR_THRE)); - uart->thr = c; + uart->thr = c; return 1; } @@ -121,16 +107,16 @@ static int davinci_uart_putc(struct rt_serial_device *serial, char c) static int davinci_uart_getc(struct rt_serial_device *serial) { int result; - uartport *uart = serial->parent.user_data; + uartport *uart = serial->parent.user_data; if (uart->lsr & LSR_DR) - { - result = uart->rbr & 0xff; - } - else - { - result = -1; - } + { + result = uart->rbr & 0xff; + } + else + { + result = -1; + } return result; } @@ -145,78 +131,78 @@ static const struct rt_uart_ops davinci_uart_ops = void davinci_uart0_init(void) { - rt_uint32_t divisor; + rt_uint32_t divisor; - divisor = (24000000 + (115200 * (16 / 2))) / (16 * 115200); - UART0->ier = 0; - UART0->lcr = 0x83; //8N1 - UART0->dll = 0; - UART0->dlh = 0; - UART0->lcr = 0x03; - UART0->mcr = 0x03; //RTS,CTS - UART0->fcr = 0x07; //FIFO - UART0->lcr = 0x83; - UART0->dll = divisor & 0xff; - UART0->dlh = (divisor >> 8) & 0xff; - UART0->lcr = 0x03; - UART0->mdr = 0; //16x over-sampling - UART0->pwremu_mgmt = 0x6000; - rt_hw_interrupt_install(IRQ_UARTINT0, rt_davinci_serial_handler, - (void *)&davinci_serial_dev0, "UART0"); - rt_hw_interrupt_mask(IRQ_UARTINT0); - UART0->ier = 0x05; + divisor = (24000000 + (115200 * (16 / 2))) / (16 * 115200); + UART0->ier = 0; + UART0->lcr = 0x83; //8N1 + UART0->dll = 0; + UART0->dlh = 0; + UART0->lcr = 0x03; + UART0->mcr = 0x03; //RTS,CTS + UART0->fcr = 0x07; //FIFO + UART0->lcr = 0x83; + UART0->dll = divisor & 0xff; + UART0->dlh = (divisor >> 8) & 0xff; + UART0->lcr = 0x03; + UART0->mdr = 0; //16x over-sampling + UART0->pwremu_mgmt = 0x6000; + rt_hw_interrupt_install(IRQ_UARTINT0, rt_davinci_serial_handler, + (void *)&davinci_serial_dev0, "UART0"); + rt_hw_interrupt_mask(IRQ_UARTINT0); + UART0->ier = 0x05; } void davinci_uart_gpio_init() { - rt_uint32_t val; + rt_uint32_t val; - val = davinci_readl(PINMUX3); - val &= 0xf3ffffff; /* gio23 RS485_CTRL */ - val |= 0x60000000; /*UART1_TXD (gio25)*/ - davinci_writel(val, PINMUX3); - val = davinci_readl(PINMUX4); - val |= 0x0000c000; /* UART1_RXD (gio34) */ - davinci_writel(val, PINMUX4); + val = davinci_readl(PINMUX3); + val &= 0xf3ffffff; /* gio23 RS485_CTRL */ + val |= 0x60000000; /*UART1_TXD (gio25)*/ + davinci_writel(val, PINMUX3); + val = davinci_readl(PINMUX4); + val |= 0x0000c000; /* UART1_RXD (gio34) */ + davinci_writel(val, PINMUX4); - val = davinci_readl(DAVINCI_GPIO_BASE + 0x10); - val &= ~(1 << 23); - davinci_writel(val, DAVINCI_GPIO_BASE + 0x10); - davinci_writel((1<<23), DAVINCI_GPIO_BASE + 0x1C); + val = davinci_readl(DAVINCI_GPIO_BASE + 0x10); + val &= ~(1 << 23); + davinci_writel(val, DAVINCI_GPIO_BASE + 0x10); + davinci_writel((1<<23), DAVINCI_GPIO_BASE + 0x1C); } void davinci_uart1_init(void) { - rt_uint32_t divisor; - rt_uint32_t freq; - rt_uint32_t baudrate; - struct clk *clk; + rt_uint32_t divisor; + rt_uint32_t freq; + rt_uint32_t baudrate; + struct clk *clk; - davinci_uart_gpio_init(); - psc_change_state(DAVINCI_DM365_LPSC_UART1, PSC_ENABLE); - clk = clk_get("UART1"); - freq = clk_get_rate(clk); + davinci_uart_gpio_init(); + psc_change_state(DAVINCI_DM365_LPSC_UART1, PSC_ENABLE); + clk = clk_get("UART1"); + freq = clk_get_rate(clk); - baudrate = 9600; - divisor = (freq + (baudrate * (16 / 2))) / (16 * baudrate); - UART1->ier = 0; - UART1->lcr = 0x87; //8N2, 0x83 8N1 - UART1->dll = 0; - UART1->dlh = 0; - UART1->lcr = 0x07; - UART1->mcr = 0x03; //RTS,CTS - UART1->fcr = 0x07; //FIFO - UART1->lcr = 0x87; - UART1->dll = divisor & 0xff; - UART1->dlh = (divisor >> 8) & 0xff; - UART1->lcr = 0x07; - UART1->mdr = 0; //16x over-sampling - UART1->pwremu_mgmt = 0x6000; - - rt_hw_interrupt_install(IRQ_UARTINT1, rt_davinci_serial_handler, - (void *)&davinci_serial_dev1, "UART1"); - rt_hw_interrupt_mask(IRQ_UARTINT1); - UART1->ier = 0x05; + baudrate = 9600; + divisor = (freq + (baudrate * (16 / 2))) / (16 * baudrate); + UART1->ier = 0; + UART1->lcr = 0x87; //8N2, 0x83 8N1 + UART1->dll = 0; + UART1->dlh = 0; + UART1->lcr = 0x07; + UART1->mcr = 0x03; //RTS,CTS + UART1->fcr = 0x07; //FIFO + UART1->lcr = 0x87; + UART1->dll = divisor & 0xff; + UART1->dlh = (divisor >> 8) & 0xff; + UART1->lcr = 0x07; + UART1->mdr = 0; //16x over-sampling + UART1->pwremu_mgmt = 0x6000; + + rt_hw_interrupt_install(IRQ_UARTINT1, rt_davinci_serial_handler, + (void *)&davinci_serial_dev1, "UART1"); + rt_hw_interrupt_mask(IRQ_UARTINT1); + UART1->ier = 0x05; } @@ -225,39 +211,39 @@ void davinci_uart1_init(void) */ int rt_hw_uart_init(void) { - davinci_serial_dev0.ops = &davinci_uart_ops; + davinci_serial_dev0.ops = &davinci_uart_ops; //davinci_serial_dev0.config = RT_SERIAL_CONFIG_DEFAULT; - davinci_serial_dev0.config.baud_rate = BAUD_RATE_115200; + davinci_serial_dev0.config.baud_rate = BAUD_RATE_115200; davinci_serial_dev0.config.bit_order = BIT_ORDER_LSB; davinci_serial_dev0.config.data_bits = DATA_BITS_8; davinci_serial_dev0.config.parity = PARITY_NONE; davinci_serial_dev0.config.stop_bits = STOP_BITS_1; davinci_serial_dev0.config.invert = NRZ_NORMAL; - davinci_serial_dev0.config.bufsz = RT_SERIAL_RB_BUFSZ; + davinci_serial_dev0.config.bufsz = RT_SERIAL_RB_BUFSZ; /* register vcom device */ rt_hw_serial_register(&davinci_serial_dev0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, UART0); - davinci_uart0_init(); + davinci_uart0_init(); - davinci_serial_dev1.ops = &davinci_uart_ops; + davinci_serial_dev1.ops = &davinci_uart_ops; //davinci_serial_dev1.config = RT_SERIAL_CONFIG_DEFAULT; - davinci_serial_dev1.config.baud_rate = BAUD_RATE_115200; + davinci_serial_dev1.config.baud_rate = BAUD_RATE_115200; davinci_serial_dev1.config.bit_order = BIT_ORDER_LSB; davinci_serial_dev1.config.data_bits = DATA_BITS_8; davinci_serial_dev1.config.parity = PARITY_NONE; davinci_serial_dev1.config.stop_bits = STOP_BITS_1; davinci_serial_dev1.config.invert = NRZ_NORMAL; - davinci_serial_dev1.config.bufsz = RT_SERIAL_RB_BUFSZ; + davinci_serial_dev1.config.bufsz = RT_SERIAL_RB_BUFSZ; /* register vcom device */ rt_hw_serial_register(&davinci_serial_dev1, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, UART1); - davinci_uart1_init(); + davinci_uart1_init(); - return 0; + return 0; } INIT_BOARD_EXPORT(rt_hw_uart_init); diff --git a/bsp/dm365/drivers/gpio.c b/bsp/dm365/drivers/gpio.c index 6c1f6b05e1..b226c736c8 100644 --- a/bsp/dm365/drivers/gpio.c +++ b/bsp/dm365/drivers/gpio.c @@ -1,176 +1,162 @@ /* - * File : gpio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ #include #include "gpio.h" -#define GPIO0_BASE (DAVINCI_GPIO_BASE + 0x10) -#define GPIO1_BASE (DAVINCI_GPIO_BASE + 0x38) -#define GPIO2_BASE (DAVINCI_GPIO_BASE + 0x60) -#define GPIO3_BASE (DAVINCI_GPIO_BASE + 0x88) +#define GPIO0_BASE (DAVINCI_GPIO_BASE + 0x10) +#define GPIO1_BASE (DAVINCI_GPIO_BASE + 0x38) +#define GPIO2_BASE (DAVINCI_GPIO_BASE + 0x60) +#define GPIO3_BASE (DAVINCI_GPIO_BASE + 0x88) static unsigned int dm365_gpio_base = (unsigned int)GPIO0_BASE; -#define GPIO_OE (dm365_gpio_base + 0x00) -#define GPIO_DATAIN (dm365_gpio_base + 0x10) -#define GPIO_DATAOUT (dm365_gpio_base + 0x04) -#define GPIO_CLROUT (dm365_gpio_base + 0x0C) -#define GPIO_SETOUT (dm365_gpio_base + 0x08) +#define GPIO_OE (dm365_gpio_base + 0x00) +#define GPIO_DATAIN (dm365_gpio_base + 0x10) +#define GPIO_DATAOUT (dm365_gpio_base + 0x04) +#define GPIO_CLROUT (dm365_gpio_base + 0x0C) +#define GPIO_SETOUT (dm365_gpio_base + 0x08) -#define gpio_dirin(n) *(volatile unsigned int *)((GPIO_OE)) |= 1<<(n) -#define gpio_dirout(n) *(volatile unsigned int *)((GPIO_OE)) &= ~(1u<<(n)) -#define gpio_set(n) *(volatile unsigned int *)((GPIO_SETOUT)) = 1<<(n) -#define gpio_clr(n) *(volatile unsigned int *)((GPIO_CLROUT)) = 1<<(n) -#define gpio_get(n) ( ( *(volatile unsigned int *)((GPIO_DATAIN)) & (1<<(n)) ) ? 1 : 0 ) +#define gpio_dirin(n) *(volatile unsigned int *)((GPIO_OE)) |= 1<<(n) +#define gpio_dirout(n) *(volatile unsigned int *)((GPIO_OE)) &= ~(1u<<(n)) +#define gpio_set(n) *(volatile unsigned int *)((GPIO_SETOUT)) = 1<<(n) +#define gpio_clr(n) *(volatile unsigned int *)((GPIO_CLROUT)) = 1<<(n) +#define gpio_get(n) ( ( *(volatile unsigned int *)((GPIO_DATAIN)) & (1<<(n)) ) ? 1 : 0 ) #define GPIO_GRP_MASK (5) - + static int gpio_to_base(unsigned int gpio) { - unsigned int grp_idx; - int ret; + unsigned int grp_idx; + int ret; - grp_idx = gpio >> GPIO_GRP_MASK; + grp_idx = gpio >> GPIO_GRP_MASK; - switch (grp_idx) { - case 0: - dm365_gpio_base = (unsigned int)GPIO0_BASE; - ret = 0; - break; - case 1: - dm365_gpio_base = (unsigned int)GPIO1_BASE; - ret = 0; - break; - case 2: - dm365_gpio_base = (unsigned int)GPIO2_BASE; - ret = 0; - break; - case 3: - dm365_gpio_base = (unsigned int)GPIO3_BASE; - ret = 0; - break; - default: - ret =-RT_EIO; - break; - } - return ret; + switch (grp_idx) { + case 0: + dm365_gpio_base = (unsigned int)GPIO0_BASE; + ret = 0; + break; + case 1: + dm365_gpio_base = (unsigned int)GPIO1_BASE; + ret = 0; + break; + case 2: + dm365_gpio_base = (unsigned int)GPIO2_BASE; + ret = 0; + break; + case 3: + dm365_gpio_base = (unsigned int)GPIO3_BASE; + ret = 0; + break; + default: + ret =-RT_EIO; + break; + } + return ret; } int gpio_direction_input(unsigned int gpio) { - unsigned int offset; - int ret=0; + unsigned int offset; + int ret=0; - rt_ubase_t temp = rt_hw_interrupt_disable(); - ret = gpio_to_base(gpio); - if (ret < 0) { - goto gpio_free; - } - offset = gpio & ((1 << GPIO_GRP_MASK) -1); + rt_ubase_t temp = rt_hw_interrupt_disable(); + ret = gpio_to_base(gpio); + if (ret < 0) { + goto gpio_free; + } + offset = gpio & ((1 << GPIO_GRP_MASK) -1); - gpio_dirin(offset); + gpio_dirin(offset); gpio_free: - rt_hw_interrupt_enable(temp); + rt_hw_interrupt_enable(temp); - return ret; + return ret; } int gpio_direction_output(unsigned int gpio, int value) { - unsigned int offset; - int ret=0; + unsigned int offset; + int ret=0; - rt_ubase_t temp = rt_hw_interrupt_disable(); - ret = gpio_to_base(gpio); - if (ret < 0) { - goto gpio_free; - } + rt_ubase_t temp = rt_hw_interrupt_disable(); + ret = gpio_to_base(gpio); + if (ret < 0) { + goto gpio_free; + } - offset = gpio & ((1 << GPIO_GRP_MASK) -1); + offset = gpio & ((1 << GPIO_GRP_MASK) -1); - if (value) { - gpio_set(offset); - } - else { - gpio_clr(offset); - } + if (value) { + gpio_set(offset); + } + else { + gpio_clr(offset); + } - gpio_dirout(offset); + gpio_dirout(offset); gpio_free: - rt_hw_interrupt_enable(temp); + rt_hw_interrupt_enable(temp); - return ret; + return ret; } int gpio_set_value(unsigned int gpio, int value) { - unsigned int offset; - int ret=0; + unsigned int offset; + int ret=0; - rt_ubase_t temp = rt_hw_interrupt_disable(); - ret = gpio_to_base(gpio); - if (ret < 0) { - goto gpio_free; - } + rt_ubase_t temp = rt_hw_interrupt_disable(); + ret = gpio_to_base(gpio); + if (ret < 0) { + goto gpio_free; + } - offset = gpio & ((1 << GPIO_GRP_MASK) -1); + offset = gpio & ((1 << GPIO_GRP_MASK) -1); - if (value) { - gpio_set(offset); - } - else { - gpio_clr(offset); - } + if (value) { + gpio_set(offset); + } + else { + gpio_clr(offset); + } gpio_free: - rt_hw_interrupt_enable(temp); + rt_hw_interrupt_enable(temp); - return ret; + return ret; } int gpio_get_value(unsigned int gpio) { - unsigned int offset; - int ret=0; + unsigned int offset; + int ret=0; - rt_ubase_t temp = rt_hw_interrupt_disable(); - ret = gpio_to_base(gpio); - if (ret < 0) { - goto gpio_free; - } + rt_ubase_t temp = rt_hw_interrupt_disable(); + ret = gpio_to_base(gpio); + if (ret < 0) { + goto gpio_free; + } - offset = gpio & ((1 << GPIO_GRP_MASK) -1); - ret = gpio_get(offset); + offset = gpio & ((1 << GPIO_GRP_MASK) -1); + ret = gpio_get(offset); gpio_free: - rt_hw_interrupt_enable(temp); + rt_hw_interrupt_enable(temp); - return ret; + return ret; } diff --git a/bsp/dm365/drivers/gpio.h b/bsp/dm365/drivers/gpio.h index c40798ed22..a6c8265648 100644 --- a/bsp/dm365/drivers/gpio.h +++ b/bsp/dm365/drivers/gpio.h @@ -1,51 +1,37 @@ /* - * File : gpio.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ -#ifndef __DM365_GPIO_H -#define __DM365_GPIO_H +#ifndef __DM365_GPIO_H +#define __DM365_GPIO_H #include -#define GPIO(X) (X) +#define GPIO(X) (X) -#define get_io(r) *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) -#define set_io(r,v) *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) = (v) -#define and_io(r,v) *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) &= (v) -#define or_io(r,v) *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) |= (v) +#define get_io(r) *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) +#define set_io(r,v) *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) = (v) +#define and_io(r,v) *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) &= (v) +#define or_io(r,v) *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) |= (v) -#define v_get_io(r) *((volatile u_int *)(r)) -#define v_set_io(r,v) *((volatile u_int *)(r)) = (v) -#define v_and_io(r,v) *((volatile u_int *)(r)) &= (v) -#define v_or_io(r,v) *((volatile u_int *)(r)) |= (v) +#define v_get_io(r) *((volatile u_int *)(r)) +#define v_set_io(r,v) *((volatile u_int *)(r)) = (v) +#define v_and_io(r,v) *((volatile u_int *)(r)) &= (v) +#define v_or_io(r,v) *((volatile u_int *)(r)) |= (v) enum gpio_intr_mode { LEVELDETECT_LOW = 0, LEVELDETECT_HIGH, - RISINGDETECT, + RISINGDETECT, FALLINGDETECT, - EDGEDETECT //both rising-edge and falling-edge detect + EDGEDETECT //both rising-edge and falling-edge detect }; enum gpio_intr_req @@ -56,10 +42,10 @@ enum gpio_intr_req enum gpio_intr_num { - GPIOINT0A = 96, - GPIOINT0B, - GPIOINT1A, - GPIOINT1B, + GPIOINT0A = 96, + GPIOINT0B, + GPIOINT1A, + GPIOINT1B, }; enum pin_func_mod @@ -70,4 +56,4 @@ enum pin_func_mod IIC_MOD=0x20 }; -#endif /* __TI814X_GPIO_H */ +#endif /* __TI814X_GPIO_H */ diff --git a/bsp/dm365/drivers/i2c-davinci.c b/bsp/dm365/drivers/i2c-davinci.c index c1d8a07ba4..6da4e72d6c 100644 --- a/bsp/dm365/drivers/i2c-davinci.c +++ b/bsp/dm365/drivers/i2c-davinci.c @@ -1,25 +1,11 @@ /* - * File : i2c-davinci.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ #include @@ -27,61 +13,61 @@ #include /* ----- global defines ----------------------------------------------- */ -#define BIT(nr) (1UL << (nr)) +#define BIT(nr) (1UL << (nr)) -#define DAVINCI_I2C_TIMEOUT (1*RT_TICK_PER_SECOND) -#define DAVINCI_I2C_MAX_TRIES 2 +#define DAVINCI_I2C_TIMEOUT (1*RT_TICK_PER_SECOND) +#define DAVINCI_I2C_MAX_TRIES 2 #define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_AAS | \ - DAVINCI_I2C_IMR_SCD | \ - DAVINCI_I2C_IMR_ARDY | \ - DAVINCI_I2C_IMR_NACK | \ - DAVINCI_I2C_IMR_AL) + DAVINCI_I2C_IMR_SCD | \ + DAVINCI_I2C_IMR_ARDY | \ + DAVINCI_I2C_IMR_NACK | \ + DAVINCI_I2C_IMR_AL) -#define DAVINCI_I2C_OAR_REG 0x00 -#define DAVINCI_I2C_IMR_REG 0x04 -#define DAVINCI_I2C_STR_REG 0x08 -#define DAVINCI_I2C_CLKL_REG 0x0c -#define DAVINCI_I2C_CLKH_REG 0x10 -#define DAVINCI_I2C_CNT_REG 0x14 -#define DAVINCI_I2C_DRR_REG 0x18 -#define DAVINCI_I2C_SAR_REG 0x1c -#define DAVINCI_I2C_DXR_REG 0x20 -#define DAVINCI_I2C_MDR_REG 0x24 -#define DAVINCI_I2C_IVR_REG 0x28 -#define DAVINCI_I2C_EMDR_REG 0x2c -#define DAVINCI_I2C_PSC_REG 0x30 +#define DAVINCI_I2C_OAR_REG 0x00 +#define DAVINCI_I2C_IMR_REG 0x04 +#define DAVINCI_I2C_STR_REG 0x08 +#define DAVINCI_I2C_CLKL_REG 0x0c +#define DAVINCI_I2C_CLKH_REG 0x10 +#define DAVINCI_I2C_CNT_REG 0x14 +#define DAVINCI_I2C_DRR_REG 0x18 +#define DAVINCI_I2C_SAR_REG 0x1c +#define DAVINCI_I2C_DXR_REG 0x20 +#define DAVINCI_I2C_MDR_REG 0x24 +#define DAVINCI_I2C_IVR_REG 0x28 +#define DAVINCI_I2C_EMDR_REG 0x2c +#define DAVINCI_I2C_PSC_REG 0x30 -#define DAVINCI_I2C_IVR_AAS 0x07 -#define DAVINCI_I2C_IVR_SCD 0x06 -#define DAVINCI_I2C_IVR_XRDY 0x05 -#define DAVINCI_I2C_IVR_RDR 0x04 -#define DAVINCI_I2C_IVR_ARDY 0x03 -#define DAVINCI_I2C_IVR_NACK 0x02 -#define DAVINCI_I2C_IVR_AL 0x01 +#define DAVINCI_I2C_IVR_AAS 0x07 +#define DAVINCI_I2C_IVR_SCD 0x06 +#define DAVINCI_I2C_IVR_XRDY 0x05 +#define DAVINCI_I2C_IVR_RDR 0x04 +#define DAVINCI_I2C_IVR_ARDY 0x03 +#define DAVINCI_I2C_IVR_NACK 0x02 +#define DAVINCI_I2C_IVR_AL 0x01 -#define DAVINCI_I2C_STR_BB BIT(12) -#define DAVINCI_I2C_STR_RSFULL BIT(11) -#define DAVINCI_I2C_STR_SCD BIT(5) -#define DAVINCI_I2C_STR_ARDY BIT(2) -#define DAVINCI_I2C_STR_NACK BIT(1) -#define DAVINCI_I2C_STR_AL BIT(0) +#define DAVINCI_I2C_STR_BB BIT(12) +#define DAVINCI_I2C_STR_RSFULL BIT(11) +#define DAVINCI_I2C_STR_SCD BIT(5) +#define DAVINCI_I2C_STR_ARDY BIT(2) +#define DAVINCI_I2C_STR_NACK BIT(1) +#define DAVINCI_I2C_STR_AL BIT(0) -#define DAVINCI_I2C_MDR_NACK BIT(15) -#define DAVINCI_I2C_MDR_STT BIT(13) -#define DAVINCI_I2C_MDR_STP BIT(11) -#define DAVINCI_I2C_MDR_MST BIT(10) -#define DAVINCI_I2C_MDR_TRX BIT(9) -#define DAVINCI_I2C_MDR_XA BIT(8) -#define DAVINCI_I2C_MDR_RM BIT(7) -#define DAVINCI_I2C_MDR_IRS BIT(5) +#define DAVINCI_I2C_MDR_NACK BIT(15) +#define DAVINCI_I2C_MDR_STT BIT(13) +#define DAVINCI_I2C_MDR_STP BIT(11) +#define DAVINCI_I2C_MDR_MST BIT(10) +#define DAVINCI_I2C_MDR_TRX BIT(9) +#define DAVINCI_I2C_MDR_XA BIT(8) +#define DAVINCI_I2C_MDR_RM BIT(7) +#define DAVINCI_I2C_MDR_IRS BIT(5) -#define DAVINCI_I2C_IMR_AAS BIT(6) -#define DAVINCI_I2C_IMR_SCD BIT(5) -#define DAVINCI_I2C_IMR_XRDY BIT(4) -#define DAVINCI_I2C_IMR_RRDY BIT(3) -#define DAVINCI_I2C_IMR_ARDY BIT(2) -#define DAVINCI_I2C_IMR_NACK BIT(1) -#define DAVINCI_I2C_IMR_AL BIT(0) +#define DAVINCI_I2C_IMR_AAS BIT(6) +#define DAVINCI_I2C_IMR_SCD BIT(5) +#define DAVINCI_I2C_IMR_XRDY BIT(4) +#define DAVINCI_I2C_IMR_RRDY BIT(3) +#define DAVINCI_I2C_IMR_ARDY BIT(2) +#define DAVINCI_I2C_IMR_NACK BIT(1) +#define DAVINCI_I2C_IMR_AL BIT(0) #ifdef RT_EDMA_DEBUG #define i2c_dbg(fmt, ...) rt_kprintf(fmt, ##__VA_ARGS__) @@ -91,42 +77,42 @@ struct davinci_i2c_dev { - void *base; - struct rt_semaphore completion; - struct clk *clk; - int cmd_err; - rt_uint8_t *buf; - rt_uint32_t buf_len; - int irq; - int stop; - rt_uint8_t terminate; - rt_uint32_t bus_freq; - rt_uint32_t bus_delay; - struct rt_i2c_bus_device *bus; + void *base; + struct rt_semaphore completion; + struct clk *clk; + int cmd_err; + rt_uint8_t *buf; + rt_uint32_t buf_len; + int irq; + int stop; + rt_uint8_t terminate; + rt_uint32_t bus_freq; + rt_uint32_t bus_delay; + struct rt_i2c_bus_device *bus; }; static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev, - int reg, rt_uint16_t val) + int reg, rt_uint16_t val) { - davinci_writew(val, i2c_dev->base + reg); + davinci_writew(val, i2c_dev->base + reg); } static inline rt_uint16_t davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg) { - return davinci_readw(i2c_dev->base + reg); + return davinci_readw(i2c_dev->base + reg); } static void udelay (rt_uint32_t us) { - rt_int32_t i; - for (; us > 0; us--) - { - i = 50000; - while(i > 0) - { - i--; - } - } + rt_int32_t i; + for (; us > 0; us--) + { + i = 50000; + while(i > 0) + { + i--; + } + } } @@ -134,17 +120,17 @@ static void udelay (rt_uint32_t us) /* Generate a pulse on the i2c clock pin. */ static void generic_i2c_clock_pulse(unsigned int scl_pin) { - rt_uint16_t i; + rt_uint16_t i; - if (scl_pin) { - /* Send high and low on the SCL line */ - for (i = 0; i < 9; i++) { - gpio_set_value(scl_pin, 0); - udelay(20); - gpio_set_value(scl_pin, 1); - udelay(20); - } - } + if (scl_pin) { + /* Send high and low on the SCL line */ + for (i = 0; i < 9; i++) { + gpio_set_value(scl_pin, 0); + udelay(20); + gpio_set_value(scl_pin, 1); + udelay(20); + } + } } #endif @@ -153,78 +139,78 @@ static void generic_i2c_clock_pulse(unsigned int scl_pin) */ static void i2c_recover_bus(struct davinci_i2c_dev *dev) { - rt_uint32_t flag = 0; + rt_uint32_t flag = 0; - i2c_dbg("initiating i2c bus recovery\n"); - /* Send NACK to the slave */ - flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); - flag |= DAVINCI_I2C_MDR_NACK; - /* write the data into mode register */ - davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); + i2c_dbg("initiating i2c bus recovery\n"); + /* Send NACK to the slave */ + flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); + flag |= DAVINCI_I2C_MDR_NACK; + /* write the data into mode register */ + davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); #if 0 - if (pdata) - generic_i2c_clock_pulse(pdata->scl_pin); + if (pdata) + generic_i2c_clock_pulse(pdata->scl_pin); #endif - /* Send STOP */ - flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); - flag |= DAVINCI_I2C_MDR_STP; - davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); + /* Send STOP */ + flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); + flag |= DAVINCI_I2C_MDR_STP; + davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); } static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev, - int val) + int val) { - rt_uint16_t w; + rt_uint16_t w; - w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG); - if (!val) /* put I2C into reset */ - w &= ~DAVINCI_I2C_MDR_IRS; - else /* take I2C out of reset */ - w |= DAVINCI_I2C_MDR_IRS; + w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG); + if (!val) /* put I2C into reset */ + w &= ~DAVINCI_I2C_MDR_IRS; + else /* take I2C out of reset */ + w |= DAVINCI_I2C_MDR_IRS; - davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w); + davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w); } static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev) { - rt_uint16_t psc; - rt_uint32_t clk; - rt_uint32_t d; - rt_uint32_t clkh; - rt_uint32_t clkl; - rt_uint32_t input_clock = clk_get_rate(dev->clk); + rt_uint16_t psc; + rt_uint32_t clk; + rt_uint32_t d; + rt_uint32_t clkh; + rt_uint32_t clkl; + rt_uint32_t input_clock = clk_get_rate(dev->clk); - /* NOTE: I2C Clock divider programming info - * As per I2C specs the following formulas provide prescaler - * and low/high divider values - * input clk --> PSC Div -----------> ICCL/H Div --> output clock - * module clk - * - * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ] - * - * Thus, - * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d; - * - * where if PSC == 0, d = 7, - * if PSC == 1, d = 6 - * if PSC > 1 , d = 5 - */ + /* NOTE: I2C Clock divider programming info + * As per I2C specs the following formulas provide prescaler + * and low/high divider values + * input clk --> PSC Div -----------> ICCL/H Div --> output clock + * module clk + * + * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ] + * + * Thus, + * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d; + * + * where if PSC == 0, d = 7, + * if PSC == 1, d = 6 + * if PSC > 1 , d = 5 + */ - /* get minimum of 7 MHz clock, but max of 12 MHz */ - psc = (input_clock / 7000000) - 1; - if ((input_clock / (psc + 1)) > 12000000) - psc++; /* better to run under spec than over */ - d = (psc >= 2) ? 5 : 7 - psc; + /* get minimum of 7 MHz clock, but max of 12 MHz */ + psc = (input_clock / 7000000) - 1; + if ((input_clock / (psc + 1)) > 12000000) + psc++; /* better to run under spec than over */ + d = (psc >= 2) ? 5 : 7 - psc; - clk = ((input_clock / (psc + 1)) / (dev->bus_freq * 1000)) - (d << 1); - clkh = clk >> 1; - clkl = clk - clkh; + clk = ((input_clock / (psc + 1)) / (dev->bus_freq * 1000)) - (d << 1); + clkh = clk >> 1; + clkl = clk - clkh; - davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc); - davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh); - davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl); + davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc); + davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh); + davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl); - i2c_dbg("input_clock = %d, CLK = %d\n", input_clock, clk); + i2c_dbg("input_clock = %d, CLK = %d\n", input_clock, clk); } /* @@ -234,65 +220,65 @@ static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev) */ static int i2c_davinci_init(struct davinci_i2c_dev *dev) { - /* put I2C into reset */ - davinci_i2c_reset_ctrl(dev, 0); + /* put I2C into reset */ + davinci_i2c_reset_ctrl(dev, 0); - /* compute clock dividers */ - i2c_davinci_calc_clk_dividers(dev); + /* compute clock dividers */ + i2c_davinci_calc_clk_dividers(dev); - /* Respond at reserved "SMBus Host" slave address" (and zero); - * we seem to have no option to not respond... - */ - davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08); + /* Respond at reserved "SMBus Host" slave address" (and zero); + * we seem to have no option to not respond... + */ + davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08); - i2c_dbg("PSC = %d\n", - davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG)); - i2c_dbg("CLKL = %d\n", - davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG)); - i2c_dbg("CLKH = %d\n", - davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG)); - i2c_dbg("bus_freq = %dkHz, bus_delay = %d\n", - dev->bus_freq, dev->bus_delay); + i2c_dbg("PSC = %d\n", + davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG)); + i2c_dbg("CLKL = %d\n", + davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG)); + i2c_dbg("CLKH = %d\n", + davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG)); + i2c_dbg("bus_freq = %dkHz, bus_delay = %d\n", + dev->bus_freq, dev->bus_delay); - /* Take the I2C module out of reset: */ - davinci_i2c_reset_ctrl(dev, 1); + /* Take the I2C module out of reset: */ + davinci_i2c_reset_ctrl(dev, 1); - /* Enable interrupts */ - davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL); + /* Enable interrupts */ + davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL); - return 0; + return 0; } /* * Waiting for bus not busy */ static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev, - char allow_sleep) + char allow_sleep) { - unsigned long timeout; - static rt_uint16_t to_cnt; - RT_ASSERT(dev != RT_NULL); - RT_ASSERT(dev->bus != RT_NULL); + unsigned long timeout; + static rt_uint16_t to_cnt; + RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev->bus != RT_NULL); - timeout = rt_tick_get() + dev->bus->timeout; - while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) - & DAVINCI_I2C_STR_BB) { - if (to_cnt <= DAVINCI_I2C_MAX_TRIES) { - if (rt_tick_get() >= timeout) { - rt_kprintf("timeout waiting for bus ready\n"); - to_cnt++; - return -RT_ETIMEOUT; - } else { - to_cnt = 0; - i2c_recover_bus(dev); - i2c_davinci_init(dev); - } - } - if (allow_sleep) - rt_thread_delay(2); - } + timeout = rt_tick_get() + dev->bus->timeout; + while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) + & DAVINCI_I2C_STR_BB) { + if (to_cnt <= DAVINCI_I2C_MAX_TRIES) { + if (rt_tick_get() >= timeout) { + rt_kprintf("timeout waiting for bus ready\n"); + to_cnt++; + return -RT_ETIMEOUT; + } else { + to_cnt = 0; + i2c_recover_bus(dev); + i2c_davinci_init(dev); + } + } + if (allow_sleep) + rt_thread_delay(2); + } - return 0; + return 0; } /* @@ -302,125 +288,125 @@ static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev, static int i2c_davinci_xfer_msg(struct rt_i2c_bus_device *bus, struct rt_i2c_msg *msg, int stop) { - struct davinci_i2c_dev *dev = bus->priv; - rt_uint32_t flag; - rt_uint16_t w; - int r; + struct davinci_i2c_dev *dev = bus->priv; + rt_uint32_t flag; + rt_uint16_t w; + int r; - /* Introduce a delay, required for some boards (e.g Davinci EVM) */ - if (dev->bus_delay) - udelay(dev->bus_delay); + /* Introduce a delay, required for some boards (e.g Davinci EVM) */ + if (dev->bus_delay) + udelay(dev->bus_delay); - /* set the slave address */ - davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr); + /* set the slave address */ + davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr); - dev->buf = msg->buf; - dev->buf_len = msg->len; - dev->stop = stop; + dev->buf = msg->buf; + dev->buf_len = msg->len; + dev->stop = stop; - davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len); + davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len); - //INIT_COMPLETION(dev->cmd_complete); - dev->cmd_err = 0; + //INIT_COMPLETION(dev->cmd_complete); + dev->cmd_err = 0; - /* Take I2C out of reset and configure it as master */ - flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST; + /* Take I2C out of reset and configure it as master */ + flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST; - /* if the slave address is ten bit address, enable XA bit */ - if (msg->flags & RT_I2C_ADDR_10BIT) - flag |= DAVINCI_I2C_MDR_XA; - if (!(msg->flags & RT_I2C_RD)) - flag |= DAVINCI_I2C_MDR_TRX; - if (msg->len == 0) - flag |= DAVINCI_I2C_MDR_RM; + /* if the slave address is ten bit address, enable XA bit */ + if (msg->flags & RT_I2C_ADDR_10BIT) + flag |= DAVINCI_I2C_MDR_XA; + if (!(msg->flags & RT_I2C_RD)) + flag |= DAVINCI_I2C_MDR_TRX; + if (msg->len == 0) + flag |= DAVINCI_I2C_MDR_RM; - /* Enable receive or transmit interrupts */ - w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG); - if (msg->flags & RT_I2C_RD) - w |= DAVINCI_I2C_IMR_RRDY; - else - w |= DAVINCI_I2C_IMR_XRDY; - davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w); + /* Enable receive or transmit interrupts */ + w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG); + if (msg->flags & RT_I2C_RD) + w |= DAVINCI_I2C_IMR_RRDY; + else + w |= DAVINCI_I2C_IMR_XRDY; + davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w); - dev->terminate = 0; + dev->terminate = 0; - /* - * Write mode register first as needed for correct behaviour - * on OMAP-L138, but don't set STT yet to avoid a race with XRDY - * occurring before we have loaded DXR - */ - davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); + /* + * Write mode register first as needed for correct behaviour + * on OMAP-L138, but don't set STT yet to avoid a race with XRDY + * occurring before we have loaded DXR + */ + davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); - /* - * First byte should be set here, not after interrupt, - * because transmit-data-ready interrupt can come before - * NACK-interrupt during sending of previous message and - * ICDXR may have wrong data - * It also saves us one interrupt, slightly faster - */ - if ((!(msg->flags & RT_I2C_RD)) && dev->buf_len) - { - davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++); - dev->buf_len--; - } + /* + * First byte should be set here, not after interrupt, + * because transmit-data-ready interrupt can come before + * NACK-interrupt during sending of previous message and + * ICDXR may have wrong data + * It also saves us one interrupt, slightly faster + */ + if ((!(msg->flags & RT_I2C_RD)) && dev->buf_len) + { + davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++); + dev->buf_len--; + } - /* Set STT to begin transmit now DXR is loaded */ - flag |= DAVINCI_I2C_MDR_STT; - if (stop && msg->len != 0) - flag |= DAVINCI_I2C_MDR_STP; - davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); + /* Set STT to begin transmit now DXR is loaded */ + flag |= DAVINCI_I2C_MDR_STT; + if (stop && msg->len != 0) + flag |= DAVINCI_I2C_MDR_STP; + davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); - r = rt_sem_take(&dev->completion, dev->bus->timeout); - if (r == -RT_ETIMEOUT) - { - rt_kprintf("controller timed out\n"); - i2c_recover_bus(dev); - i2c_davinci_init(dev); - dev->buf_len = 0; - return -RT_ETIMEOUT; - } - if (dev->buf_len) - { - /* This should be 0 if all bytes were transferred - * or dev->cmd_err denotes an error. - * A signal may have aborted the transfer. - */ - if (r == RT_EOK) - { - rt_kprintf("abnormal termination buf_len=%i\n", - dev->buf_len); - r = -RT_EIO; - } - dev->terminate = 1; - dev->buf_len = 0; - } - if (r < 0) - return r; + r = rt_sem_take(&dev->completion, dev->bus->timeout); + if (r == -RT_ETIMEOUT) + { + rt_kprintf("controller timed out\n"); + i2c_recover_bus(dev); + i2c_davinci_init(dev); + dev->buf_len = 0; + return -RT_ETIMEOUT; + } + if (dev->buf_len) + { + /* This should be 0 if all bytes were transferred + * or dev->cmd_err denotes an error. + * A signal may have aborted the transfer. + */ + if (r == RT_EOK) + { + rt_kprintf("abnormal termination buf_len=%i\n", + dev->buf_len); + r = -RT_EIO; + } + dev->terminate = 1; + dev->buf_len = 0; + } + if (r < 0) + return r; - /* no error */ - if (!dev->cmd_err) - return msg->len; + /* no error */ + if (!dev->cmd_err) + return msg->len; - /* We have an error */ - if (dev->cmd_err & DAVINCI_I2C_STR_AL) - { - i2c_davinci_init(dev); - return -RT_EIO; - } + /* We have an error */ + if (dev->cmd_err & DAVINCI_I2C_STR_AL) + { + i2c_davinci_init(dev); + return -RT_EIO; + } - if (dev->cmd_err & DAVINCI_I2C_STR_NACK) - { - if (msg->flags & RT_I2C_IGNORE_NACK) - return msg->len; - if (stop) - { - w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); - w |= DAVINCI_I2C_MDR_STP; - davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); - } - return -RT_EIO; - } - return -RT_EIO; + if (dev->cmd_err & DAVINCI_I2C_STR_NACK) + { + if (msg->flags & RT_I2C_IGNORE_NACK) + return msg->len; + if (stop) + { + w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); + w |= DAVINCI_I2C_MDR_STP; + davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); + } + return -RT_EIO; + } + return -RT_EIO; } /* @@ -429,52 +415,52 @@ i2c_davinci_xfer_msg(struct rt_i2c_bus_device *bus, struct rt_i2c_msg *msg, int static int i2c_davinci_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], int num) { - struct davinci_i2c_dev *dev = bus->priv; - int i; - int ret; + struct davinci_i2c_dev *dev = bus->priv; + int i; + int ret; - i2c_dbg("%s: msgs: %d\n", __func__, num); + i2c_dbg("%s: msgs: %d\n", __func__, num); - ret = i2c_davinci_wait_bus_not_busy(dev, 1); - if (ret < 0) - { - i2c_dbg("timeout waiting for bus ready\n"); - return ret; - } + ret = i2c_davinci_wait_bus_not_busy(dev, 1); + if (ret < 0) + { + i2c_dbg("timeout waiting for bus ready\n"); + return ret; + } - for (i = 0; i < num; i++) - { - ret = i2c_davinci_xfer_msg(bus, &msgs[i], (i == (num - 1))); - i2c_dbg("%s [%d/%d] ret: %d\n", __func__, i + 1, num, - ret); - if (ret < 0) - return ret; - } + for (i = 0; i < num; i++) + { + ret = i2c_davinci_xfer_msg(bus, &msgs[i], (i == (num - 1))); + i2c_dbg("%s [%d/%d] ret: %d\n", __func__, i + 1, num, + ret); + if (ret < 0) + return ret; + } - return num; + return num; } static void terminate_read(struct davinci_i2c_dev *dev) { - rt_uint16_t w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); - w |= DAVINCI_I2C_MDR_NACK; - davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); + rt_uint16_t w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); + w |= DAVINCI_I2C_MDR_NACK; + davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); - /* Throw away data */ - davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG); - if (!dev->terminate) - rt_kprintf("RDR IRQ while no data requested\n"); + /* Throw away data */ + davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG); + if (!dev->terminate) + rt_kprintf("RDR IRQ while no data requested\n"); } static void terminate_write(struct davinci_i2c_dev *dev) { - rt_uint16_t w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); - w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP; - davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); + rt_uint16_t w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); + w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP; + davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); - if (!dev->terminate) - i2c_dbg("TDR IRQ while no data to send\n"); + if (!dev->terminate) + i2c_dbg("TDR IRQ while no data to send\n"); } /* @@ -483,173 +469,173 @@ static void terminate_write(struct davinci_i2c_dev *dev) */ static void i2c_davinci_isr(int irq, void *param) { - struct davinci_i2c_dev *dev = (struct davinci_i2c_dev *)param; - rt_uint32_t stat; - int count = 0; - rt_uint16_t w; + struct davinci_i2c_dev *dev = (struct davinci_i2c_dev *)param; + rt_uint32_t stat; + int count = 0; + rt_uint16_t w; - while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) { - i2c_dbg("%s: stat=0x%x\n", __func__, stat); - if (count++ == 100) { - rt_kprintf("Too much work in one IRQ\n"); - break; - } + while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) { + i2c_dbg("%s: stat=0x%x\n", __func__, stat); + if (count++ == 100) { + rt_kprintf("Too much work in one IRQ\n"); + break; + } - switch (stat) { - case DAVINCI_I2C_IVR_AL: - /* Arbitration lost, must retry */ - dev->cmd_err |= DAVINCI_I2C_STR_AL; - dev->buf_len = 0; - rt_sem_release(&dev->completion); - break; + switch (stat) { + case DAVINCI_I2C_IVR_AL: + /* Arbitration lost, must retry */ + dev->cmd_err |= DAVINCI_I2C_STR_AL; + dev->buf_len = 0; + rt_sem_release(&dev->completion); + break; - case DAVINCI_I2C_IVR_NACK: - dev->cmd_err |= DAVINCI_I2C_STR_NACK; - dev->buf_len = 0; - rt_sem_release(&dev->completion); - break; + case DAVINCI_I2C_IVR_NACK: + dev->cmd_err |= DAVINCI_I2C_STR_NACK; + dev->buf_len = 0; + rt_sem_release(&dev->completion); + break; - case DAVINCI_I2C_IVR_ARDY: - davinci_i2c_write_reg(dev, - DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY); - if (((dev->buf_len == 0) && (dev->stop != 0)) || - (dev->cmd_err & DAVINCI_I2C_STR_NACK)) { - w = davinci_i2c_read_reg(dev, - DAVINCI_I2C_MDR_REG); - w |= DAVINCI_I2C_MDR_STP; - davinci_i2c_write_reg(dev, - DAVINCI_I2C_MDR_REG, w); - } - rt_sem_release(&dev->completion); - break; + case DAVINCI_I2C_IVR_ARDY: + davinci_i2c_write_reg(dev, + DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY); + if (((dev->buf_len == 0) && (dev->stop != 0)) || + (dev->cmd_err & DAVINCI_I2C_STR_NACK)) { + w = davinci_i2c_read_reg(dev, + DAVINCI_I2C_MDR_REG); + w |= DAVINCI_I2C_MDR_STP; + davinci_i2c_write_reg(dev, + DAVINCI_I2C_MDR_REG, w); + } + rt_sem_release(&dev->completion); + break; - case DAVINCI_I2C_IVR_RDR: - if (dev->buf_len) { - *dev->buf++ = - davinci_i2c_read_reg(dev, - DAVINCI_I2C_DRR_REG); - dev->buf_len--; - if (dev->buf_len) - continue; + case DAVINCI_I2C_IVR_RDR: + if (dev->buf_len) { + *dev->buf++ = + davinci_i2c_read_reg(dev, + DAVINCI_I2C_DRR_REG); + dev->buf_len--; + if (dev->buf_len) + continue; - davinci_i2c_write_reg(dev, - DAVINCI_I2C_STR_REG, - DAVINCI_I2C_IMR_RRDY); - } else { - /* signal can terminate transfer */ - terminate_read(dev); - } - break; + davinci_i2c_write_reg(dev, + DAVINCI_I2C_STR_REG, + DAVINCI_I2C_IMR_RRDY); + } else { + /* signal can terminate transfer */ + terminate_read(dev); + } + break; - case DAVINCI_I2C_IVR_XRDY: - if (dev->buf_len) { - davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, - *dev->buf++); - dev->buf_len--; - if (dev->buf_len) - continue; + case DAVINCI_I2C_IVR_XRDY: + if (dev->buf_len) { + davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, + *dev->buf++); + dev->buf_len--; + if (dev->buf_len) + continue; - w = davinci_i2c_read_reg(dev, - DAVINCI_I2C_IMR_REG); - w &= ~DAVINCI_I2C_IMR_XRDY; - davinci_i2c_write_reg(dev, - DAVINCI_I2C_IMR_REG, - w); - } else { - /* signal can terminate transfer */ - terminate_write(dev); - } - break; + w = davinci_i2c_read_reg(dev, + DAVINCI_I2C_IMR_REG); + w &= ~DAVINCI_I2C_IMR_XRDY; + davinci_i2c_write_reg(dev, + DAVINCI_I2C_IMR_REG, + w); + } else { + /* signal can terminate transfer */ + terminate_write(dev); + } + break; - case DAVINCI_I2C_IVR_SCD: - davinci_i2c_write_reg(dev, - DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD); - rt_sem_release(&dev->completion); - break; + case DAVINCI_I2C_IVR_SCD: + davinci_i2c_write_reg(dev, + DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD); + rt_sem_release(&dev->completion); + break; - case DAVINCI_I2C_IVR_AAS: - i2c_dbg("Address as slave interrupt\n"); - break; + case DAVINCI_I2C_IVR_AAS: + i2c_dbg("Address as slave interrupt\n"); + break; - default: - i2c_dbg("Unrecognized irq stat %d\n", stat); - break; - } - } + default: + i2c_dbg("Unrecognized irq stat %d\n", stat); + break; + } + } } static struct rt_i2c_bus_device_ops bus_ops = { - .master_xfer = i2c_davinci_xfer, + .master_xfer = i2c_davinci_xfer, }; int davinci_i2c_init(char *bus_name) { - struct rt_i2c_bus_device *bus; - struct davinci_i2c_dev *dev; - int r; + struct rt_i2c_bus_device *bus; + struct davinci_i2c_dev *dev; + int r; - bus = rt_malloc(sizeof(struct rt_i2c_bus_device)); - if (bus == RT_NULL) - { - rt_kprintf("rt_malloc failed\n"); - return -RT_ENOMEM; - } - - rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device)); + bus = rt_malloc(sizeof(struct rt_i2c_bus_device)); + if (bus == RT_NULL) + { + rt_kprintf("rt_malloc failed\n"); + return -RT_ENOMEM; + } - bus->ops = &bus_ops; - bus->timeout = DAVINCI_I2C_TIMEOUT; + rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device)); - dev = rt_malloc(sizeof(struct davinci_i2c_dev)); - if (!dev) - { - r = -RT_ENOMEM; - goto err; - } + bus->ops = &bus_ops; + bus->timeout = DAVINCI_I2C_TIMEOUT; - rt_memset((void *)dev, 0, sizeof(struct davinci_i2c_dev)); + dev = rt_malloc(sizeof(struct davinci_i2c_dev)); + if (!dev) + { + r = -RT_ENOMEM; + goto err; + } - rt_sem_init(&dev->completion, "i2c_ack", 0, RT_IPC_FLAG_FIFO); + rt_memset((void *)dev, 0, sizeof(struct davinci_i2c_dev)); - dev->irq = IRQ_I2C; + rt_sem_init(&dev->completion, "i2c_ack", 0, RT_IPC_FLAG_FIFO); - dev->clk = clk_get("I2CCLK"); - if (dev->clk == RT_NULL) { - r = -RT_ERROR; - goto err1; - } + dev->irq = IRQ_I2C; - psc_change_state(DAVINCI_DM365_LPSC_I2C, 3); + dev->clk = clk_get("I2CCLK"); + if (dev->clk == RT_NULL) { + r = -RT_ERROR; + goto err1; + } - dev->base = DAVINCI_I2C_BASE; - dev->bus_freq = 100; - dev->bus_delay = 0; - dev->bus = bus; + psc_change_state(DAVINCI_DM365_LPSC_I2C, 3); - bus->priv = dev; + dev->base = DAVINCI_I2C_BASE; + dev->bus_freq = 100; + dev->bus_delay = 0; + dev->bus = bus; - i2c_davinci_init(dev); + bus->priv = dev; - rt_hw_interrupt_install(dev->irq, i2c_davinci_isr, (void *)dev, "I2C"); - rt_hw_interrupt_umask(dev->irq); + i2c_davinci_init(dev); - return rt_i2c_bus_device_register(bus, bus_name); + rt_hw_interrupt_install(dev->irq, i2c_davinci_isr, (void *)dev, "I2C"); + rt_hw_interrupt_umask(dev->irq); + + return rt_i2c_bus_device_register(bus, bus_name); err1: - rt_free(dev); + rt_free(dev); err: - rt_free(bus); + rt_free(bus); - return r; + return r; } int rt_hw_iic_init(void) { - davinci_i2c_init("I2C1"); + davinci_i2c_init("I2C1"); } INIT_DEVICE_EXPORT(rt_hw_iic_init); diff --git a/bsp/dm365/drivers/mii.h b/bsp/dm365/drivers/mii.h index de799bccce..8b42352bf4 100644 --- a/bsp/dm365/drivers/mii.h +++ b/bsp/dm365/drivers/mii.h @@ -1,25 +1,11 @@ /* - * File : mii.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-03-18 weety first version + * Date Author Notes + * 2011-03-18 weety first version */ @@ -37,7 +23,7 @@ #define MII_EXPANSION 0x06 /* Expansion register */ #define MII_CTRL1000 0x09 /* 1000BASE-T control */ #define MII_STAT1000 0x0a /* 1000BASE-T status */ -#define MII_ESTATUS 0x0f /* Extended Status */ +#define MII_ESTATUS 0x0f /* Extended Status */ #define MII_DCOUNTER 0x12 /* Disconnect counter */ #define MII_FCSCOUNTER 0x13 /* False carrier counter */ #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ @@ -52,7 +38,7 @@ /* Basic mode control register. */ #define BMCR_RESV 0x003f /* Unused... */ -#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ #define BMCR_CTST 0x0080 /* Collision test */ #define BMCR_FULLDPLX 0x0100 /* Full duplex */ #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ @@ -71,7 +57,7 @@ #define BMSR_RFAULT 0x0010 /* Remote fault detected */ #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ #define BMSR_RESV 0x00c0 /* Unused... */ -#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ +#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */ #define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */ #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ @@ -100,7 +86,7 @@ #define ADVERTISE_NPAGE 0x8000 /* Next page bit */ #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ - ADVERTISE_CSMA) + ADVERTISE_CSMA) #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ ADVERTISE_100HALF | ADVERTISE_100FULL) @@ -122,8 +108,8 @@ #define LPA_LPACK 0x4000 /* Link partner acked us */ #define LPA_NPAGE 0x8000 /* Next page bit */ -#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) -#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) +#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) /* Expansion register for auto-negotiation. */ #define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ @@ -133,8 +119,8 @@ #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ #define EXPANSION_RESV 0xffe0 /* Unused... */ -#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ -#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ +#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ +#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ /* N-way test register. */ #define NWAYTEST_RESV1 0x00ff /* Unused... */ @@ -152,8 +138,8 @@ #define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */ /* Flow control flags */ -#define FLOW_CTRL_TX 0x01 -#define FLOW_CTRL_RX 0x02 +#define FLOW_CTRL_TX 0x01 +#define FLOW_CTRL_RX 0x02 /** * mii_nway_result @@ -188,11 +174,11 @@ rt_inline unsigned int mii_nway_result (unsigned int negotiated) } /* The forced speed, 10Mb, 100Mb, gigabit, 2.5Gb, 10GbE. */ -#define SPEED_10 10 -#define SPEED_100 100 -#define SPEED_1000 1000 -#define SPEED_2500 2500 -#define SPEED_10000 10000 +#define SPEED_10 10 +#define SPEED_100 100 +#define SPEED_1000 1000 +#define SPEED_2500 2500 +#define SPEED_10000 10000 #endif /* __MII_H__ */ diff --git a/bsp/dm365/drivers/mmcsd.c b/bsp/dm365/drivers/mmcsd.c index 00a1c045ea..8e12236256 100644 --- a/bsp/dm365/drivers/mmcsd.c +++ b/bsp/dm365/drivers/mmcsd.c @@ -1,25 +1,11 @@ /* - * File : mmcsd.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ #include @@ -32,66 +18,66 @@ #define RT_USING_MMCSD0 -#define MMCSD_DEBUG 0 +#define MMCSD_DEBUG 0 #if MMCSD_DEBUG -#define mmc_dbg(fmt, ...) rt_kprintf(fmt, ##__VA_ARGS__) +#define mmc_dbg(fmt, ...) rt_kprintf(fmt, ##__VA_ARGS__) #else #define mmc_dbg(fmt, ...) #endif -#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<29)) -#define CACHE_LINE_SIZE 32 +#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<29)) +#define CACHE_LINE_SIZE 32 extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size); extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); -#define EVT_QUEUE_NUM 0 /* EDMA3 Event queue number. */ +#define EVT_QUEUE_NUM 0 /* EDMA3 Event queue number. */ static unsigned rw_threshold = 32; static rt_bool_t use_dma = RT_TRUE; enum DATA_DIR_TYPE { - DM365_MMC_DATADIR_NONE = 0, - DM365_MMC_DATADIR_READ, - DM365_MMC_DATADIR_WRITE, + DM365_MMC_DATADIR_NONE = 0, + DM365_MMC_DATADIR_READ, + DM365_MMC_DATADIR_WRITE, }; -struct mmc_dm365_host +struct mmc_dm365_host { - struct rt_mmcsd_host *mmc; - struct rt_mmcsd_req *req; - struct rt_mmcsd_data *data; - struct rt_mmcsd_cmd *cmd; - struct edmacc_param tx_template; - struct edmacc_param rx_template; + struct rt_mmcsd_host *mmc; + struct rt_mmcsd_req *req; + struct rt_mmcsd_data *data; + struct rt_mmcsd_cmd *cmd; + struct edmacc_param tx_template; + struct edmacc_param rx_template; - rt_uint32_t mmc_input_clk; - rt_uint32_t ns_in_one_cycle; /* for ns in one cycle calculation */ + rt_uint32_t mmc_input_clk; + rt_uint32_t ns_in_one_cycle; /* for ns in one cycle calculation */ - mmcsd_regs_t *mmcsd_regs; - rt_uint8_t bus_mode; + mmcsd_regs_t *mmcsd_regs; + rt_uint8_t bus_mode; - enum DATA_DIR_TYPE data_dir; + enum DATA_DIR_TYPE data_dir; - rt_uint32_t rxdma; - rt_uint32_t txdma; - rt_bool_t use_dma; - rt_bool_t do_dma; + rt_uint32_t rxdma; + rt_uint32_t txdma; + rt_bool_t use_dma; + rt_bool_t do_dma; - rt_uint8_t *buffer; - rt_uint32_t buffer_bytes_left; - rt_uint32_t bytes_left; + rt_uint8_t *buffer; + rt_uint32_t buffer_bytes_left; + rt_uint32_t bytes_left; - rt_uint8_t *dma_buffer; - rt_bool_t use_dma_buffer; - rt_bool_t sdio_int; + rt_uint8_t *dma_buffer; + rt_bool_t use_dma_buffer; + rt_bool_t sdio_int; }; void *mmc_priv(struct rt_mmcsd_host *host) { - return (void *)host->private_data; + return (void *)host->private_data; } static void delay_us(rt_uint32_t us) @@ -102,1380 +88,1380 @@ static void delay_us(rt_uint32_t us) } /******************************************************************************************************* -** : calculate_freq_for_card() -** : ˺ڼSDƵķƵ -** -** 䡡: host -> DM365 MMC host -** mmc_req_freq -> MMCƵ +** 函数名称: calculate_freq_for_card() +** 功能描述: 此函数用于计算设置SD卡频率所需的分频数 ** -** 䡡: Ƶֵ -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 MMC host句柄 +** mmc_req_freq -> MMC工作频率 +** +** 输　出: 分频值 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static rt_uint32_t calculate_freq_for_card(struct mmc_dm365_host *host, rt_uint32_t mmc_req_freq) { - rt_uint32_t mmc_freq = 0; - rt_uint32_t mmc_pclk = 0; - rt_uint32_t mmc_push_pull_divisor = 0; + rt_uint32_t mmc_freq = 0; + rt_uint32_t mmc_pclk = 0; + rt_uint32_t mmc_push_pull_divisor = 0; - mmc_pclk = host->mmc_input_clk; - - if (mmc_req_freq && mmc_pclk > (2 * mmc_req_freq)) - mmc_push_pull_divisor = ((rt_uint32_t)mmc_pclk / (2 * mmc_req_freq)) - 1; - else - mmc_push_pull_divisor = 0; + mmc_pclk = host->mmc_input_clk; - mmc_freq = (rt_uint32_t)mmc_pclk / (2 * (mmc_push_pull_divisor + 1)); + if (mmc_req_freq && mmc_pclk > (2 * mmc_req_freq)) + mmc_push_pull_divisor = ((rt_uint32_t)mmc_pclk / (2 * mmc_req_freq)) - 1; + else + mmc_push_pull_divisor = 0; - if (mmc_freq > mmc_req_freq) - mmc_push_pull_divisor = mmc_push_pull_divisor + 1; - - /* Convert ns to clock cycles */ - if (mmc_req_freq <= 400000) - host->ns_in_one_cycle = (1000000)/(((mmc_pclk/(2*(mmc_push_pull_divisor+1)))/1000)); - else - host->ns_in_one_cycle = (1000000)/(((mmc_pclk/(2*(mmc_push_pull_divisor+1)))/1000000)); + mmc_freq = (rt_uint32_t)mmc_pclk / (2 * (mmc_push_pull_divisor + 1)); - return mmc_push_pull_divisor; + if (mmc_freq > mmc_req_freq) + mmc_push_pull_divisor = mmc_push_pull_divisor + 1; + + /* Convert ns to clock cycles */ + if (mmc_req_freq <= 400000) + host->ns_in_one_cycle = (1000000)/(((mmc_pclk/(2*(mmc_push_pull_divisor+1)))/1000)); + else + host->ns_in_one_cycle = (1000000)/(((mmc_pclk/(2*(mmc_push_pull_divisor+1)))/1000000)); + + return mmc_push_pull_divisor; } /******************************************************************************************************* -** : calculate_freq_for_card() -** : ˺ڼMMC clockƵ -** -** 䡡: host -> DM365 MMC host -** ios -> MMC +** 函数名称: calculate_freq_for_card() +** 功能描述: 此函数用于计算MMC clock分频数 ** -** 䡡: ȡPHYĴֵ -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 MMC host句柄 +** ios -> MMC 操作句柄 +** +** 输　出: 读取到的PHY寄存器值 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void calculate_clk_divider(struct rt_mmcsd_host *mmc, struct rt_mmcsd_io_cfg *ios) { - rt_uint32_t temp = 0; - rt_uint32_t mmc_pclk = 0; - rt_uint32_t open_drain_freq = 0; - rt_uint32_t mmc_push_pull_freq = 0; - struct mmc_dm365_host *host = mmc_priv(mmc); + rt_uint32_t temp = 0; + rt_uint32_t mmc_pclk = 0; + rt_uint32_t open_drain_freq = 0; + rt_uint32_t mmc_push_pull_freq = 0; + struct mmc_dm365_host *host = mmc_priv(mmc); - mmc_pclk = host->mmc_input_clk; + mmc_pclk = host->mmc_input_clk; - if (ios->bus_mode == MMCSD_BUSMODE_OPENDRAIN) - { - /* Ignoring the init clock value passed for fixing the inter - * operability with different cards. - */ - open_drain_freq = ((rt_uint32_t)mmc_pclk / (2 * MMCSD_INIT_CLOCK)) - 1; + if (ios->bus_mode == MMCSD_BUSMODE_OPENDRAIN) + { + /* Ignoring the init clock value passed for fixing the inter + * operability with different cards. + */ + open_drain_freq = ((rt_uint32_t)mmc_pclk / (2 * MMCSD_INIT_CLOCK)) - 1; - if (open_drain_freq > 0xFF) - open_drain_freq = 0xFF; + if (open_drain_freq > 0xFF) + open_drain_freq = 0xFF; - temp = host->mmcsd_regs->MMCCLK & ~MMCCLK_CLKRT_MASK; - temp |= open_drain_freq; - host->mmcsd_regs->MMCCLK = temp; + temp = host->mmcsd_regs->MMCCLK & ~MMCCLK_CLKRT_MASK; + temp |= open_drain_freq; + host->mmcsd_regs->MMCCLK = temp; - - /* Convert ns to clock cycles */ - host->ns_in_one_cycle = (1000000) / (MMCSD_INIT_CLOCK / 1000); - } - else - { - mmc_push_pull_freq = calculate_freq_for_card(host, ios->clock); - if (mmc_push_pull_freq > 0xFF) - mmc_push_pull_freq = 0xFF; + /* Convert ns to clock cycles */ + host->ns_in_one_cycle = (1000000) / (MMCSD_INIT_CLOCK / 1000); + } + else + { + mmc_push_pull_freq = calculate_freq_for_card(host, ios->clock); - temp = host->mmcsd_regs->MMCCLK & ~MMCCLK_CLKEN; - host->mmcsd_regs->MMCCLK = temp; - - delay_us(10); + if (mmc_push_pull_freq > 0xFF) + mmc_push_pull_freq = 0xFF; - temp = host->mmcsd_regs->MMCCLK & ~MMCCLK_CLKRT_MASK; - temp |= mmc_push_pull_freq; - host->mmcsd_regs->MMCCLK = temp; - - host->mmcsd_regs->MMCCLK = temp | MMCCLK_CLKEN; + temp = host->mmcsd_regs->MMCCLK & ~MMCCLK_CLKEN; + host->mmcsd_regs->MMCCLK = temp; - delay_us(10); - } + delay_us(10); + + temp = host->mmcsd_regs->MMCCLK & ~MMCCLK_CLKRT_MASK; + temp |= mmc_push_pull_freq; + host->mmcsd_regs->MMCCLK = temp; + + host->mmcsd_regs->MMCCLK = temp | MMCCLK_CLKEN; + + delay_us(10); + } } /******************************************************************************************************* -** : mmc_dm365_set_ios() -** : ˺mmc -** -** 䡡: mmc -> mmc host -** ios -> mmc +** 函数名称: mmc_dm365_set_ios() +** 功能描述: 此函数是mmc设置设置 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: mmc -> mmc host 句柄 +** ios -> mmc 操作句柄 +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void mmc_dm365_set_ios(struct rt_mmcsd_host *mmc, struct rt_mmcsd_io_cfg *ios) { - struct mmc_dm365_host *host = mmc_priv(mmc); + struct mmc_dm365_host *host = mmc_priv(mmc); - mmc_dbg("clock %dHz busmode %d powermode %d Vdd %04x\n", ios->clock, ios->bus_mode, ios->power_mode, ios->vdd); + mmc_dbg("clock %dHz busmode %d powermode %d Vdd %04x\n", ios->clock, ios->bus_mode, ios->power_mode, ios->vdd); - switch (ios->bus_width) + switch (ios->bus_width) { - case MMCSD_BUS_WIDTH_8: + case MMCSD_BUS_WIDTH_8: mmc_dbg("Enabling 8 bit mode\n"); - host->mmcsd_regs->MMCCTL = (host->mmcsd_regs->MMCCTL & ~MMCCTL_WIDTH_4_BIT) | MMCCTL_WIDTH_8_BIT; - break; - case MMCSD_BUS_WIDTH_4: + host->mmcsd_regs->MMCCTL = (host->mmcsd_regs->MMCCTL & ~MMCCTL_WIDTH_4_BIT) | MMCCTL_WIDTH_8_BIT; + break; + case MMCSD_BUS_WIDTH_4: mmc_dbg("Enabling 4 bit mode\n"); - host->mmcsd_regs->MMCCTL = (host->mmcsd_regs->MMCCTL & ~MMCCTL_WIDTH_8_BIT) | MMCCTL_WIDTH_4_BIT; - break; - case MMCSD_BUS_WIDTH_1: + host->mmcsd_regs->MMCCTL = (host->mmcsd_regs->MMCCTL & ~MMCCTL_WIDTH_8_BIT) | MMCCTL_WIDTH_4_BIT; + break; + case MMCSD_BUS_WIDTH_1: mmc_dbg("Enabling 1 bit mode\n"); - host->mmcsd_regs->MMCCTL = host->mmcsd_regs->MMCCTL & ~(MMCCTL_WIDTH_8_BIT | MMCCTL_WIDTH_4_BIT); - break; - } + host->mmcsd_regs->MMCCTL = host->mmcsd_regs->MMCCTL & ~(MMCCTL_WIDTH_8_BIT | MMCCTL_WIDTH_4_BIT); + break; + } - calculate_clk_divider(mmc, ios); + calculate_clk_divider(mmc, ios); - host->bus_mode = ios->bus_mode; - if (ios->power_mode == MMCSD_POWER_UP) + host->bus_mode = ios->bus_mode; + if (ios->power_mode == MMCSD_POWER_UP) { - unsigned long timeout = rt_tick_get() + 500; - rt_bool_t lose = 1; + unsigned long timeout = rt_tick_get() + 500; + rt_bool_t lose = 1; - host->mmcsd_regs->MMCARGHL = 0; - host->mmcsd_regs->MMCCMD = MMCCMD_INITCK; - - while (rt_tick_get() < timeout) - { - rt_uint32_t tmp = host->mmcsd_regs->MMCST0; + host->mmcsd_regs->MMCARGHL = 0; + host->mmcsd_regs->MMCCMD = MMCCMD_INITCK; - if (tmp & MMCST0_RSPDNE) - { - lose = 0; - break; - } - } - if (lose) - mmc_dbg("powerup timeout\n"); - } + while (rt_tick_get() < timeout) + { + rt_uint32_t tmp = host->mmcsd_regs->MMCST0; + + if (tmp & MMCST0_RSPDNE) + { + lose = 0; + break; + } + } + if (lose) + mmc_dbg("powerup timeout\n"); + } } /******************************************************************************************************* -** : dm365_fifo_data_trans() -** : ˺fifoģʽ -** -** 䡡: host -> DM365 mmc host -** n -> ֽ +** 函数名称: dm365_fifo_data_trans() +** 功能描述: 此函数是fifo模式传输 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 mmc host 句柄 +** n -> 传输字节数 +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void dm365_fifo_data_trans(struct mmc_dm365_host *host, rt_uint32_t n) { - rt_uint8_t *p; - rt_uint32_t i; + rt_uint8_t *p; + rt_uint32_t i; - p = host->buffer; + p = host->buffer; - if (host->bytes_left < n) - n = host->bytes_left; - - host->bytes_left -= n; + if (host->bytes_left < n) + n = host->bytes_left; - /* NOTE: we never transfer more than rw_threshold bytes - * to/from the fifo here; there's no I/O overlap. - * This also assumes that access width( i.e. ACCWD) is 4 bytes - */ - if (host->data_dir == DM365_MMC_DATADIR_WRITE) - { - for (i = 0; i < (n >> 2); i++) - { - host->mmcsd_regs->MMCDXR = *((rt_uint32_t *)p); - p = p + 4; - } - if (n & 3) - { - rt_kprintf("to do ... \n"); -// iowrite8_rep(host->base + MMCSD_MMCDXR, p, (n & 3)); - p = p + (n & 3); - } - } - else - { - for (i = 0; i < (n >> 2); i++) - { - *((rt_uint32_t *)p) = host->mmcsd_regs->MMCDRR; - p = p + 4; - } - if (n & 3) - { + host->bytes_left -= n; + + /* NOTE: we never transfer more than rw_threshold bytes + * to/from the fifo here; there's no I/O overlap. + * This also assumes that access width( i.e. ACCWD) is 4 bytes + */ + if (host->data_dir == DM365_MMC_DATADIR_WRITE) + { + for (i = 0; i < (n >> 2); i++) + { + host->mmcsd_regs->MMCDXR = *((rt_uint32_t *)p); + p = p + 4; + } + if (n & 3) + { rt_kprintf("to do ... \n"); -// ioread8_rep(host->base + MMCSD_MMCDRR, p, (n & 3)); - p = p + (n & 3); - } - } - host->buffer = p; +// iowrite8_rep(host->base + MMCSD_MMCDXR, p, (n & 3)); + p = p + (n & 3); + } + } + else + { + for (i = 0; i < (n >> 2); i++) + { + *((rt_uint32_t *)p) = host->mmcsd_regs->MMCDRR; + p = p + 4; + } + if (n & 3) + { + rt_kprintf("to do ... \n"); +// ioread8_rep(host->base + MMCSD_MMCDRR, p, (n & 3)); + p = p + (n & 3); + } + } + host->buffer = p; } /******************************************************************************************************* -** : mmc_dm365_start_command() -** : ˺ǿʼSD -** -** 䡡: host -> DM365 mmc host -** cmd -> SD +** 函数名称: mmc_dm365_start_command() +** 功能描述: 此函数是开始发送SD命令 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 mmc host 句柄 +** cmd -> SD命令句柄 +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void mmc_dm365_start_command(struct mmc_dm365_host *host, struct rt_mmcsd_cmd *cmd) { - rt_uint32_t cmd_reg = 0; - rt_uint32_t im_val; - - host->cmd = cmd; + rt_uint32_t cmd_reg = 0; + rt_uint32_t im_val; - switch (resp_type(cmd)) - { - case RESP_R1B: - /* There's some spec confusion about when R1B is - * allowed, but if the card doesn't issue a BUSY - * then it's harmless for us to allow it. - */ - cmd_reg |= MMCCMD_BSYEXP; - /* FALLTHROUGH */ - case RESP_R1: /* 48 bits, CRC */ + host->cmd = cmd; + + switch (resp_type(cmd)) + { + case RESP_R1B: + /* There's some spec confusion about when R1B is + * allowed, but if the card doesn't issue a BUSY + * then it's harmless for us to allow it. + */ + cmd_reg |= MMCCMD_BSYEXP; + /* FALLTHROUGH */ + case RESP_R1: /* 48 bits, CRC */ case RESP_R4: - case RESP_R5: + case RESP_R5: case RESP_R6: - case RESP_R7: - cmd_reg |= MMCCMD_RSPFMT_R1456; - break; - case RESP_R2: /* 136 bits, CRC */ - cmd_reg |= MMCCMD_RSPFMT_R2; - break; - case RESP_R3: /* 48 bits, no CRC */ - cmd_reg |= MMCCMD_RSPFMT_R3; - break; - default: - cmd_reg |= MMCCMD_RSPFMT_NONE; - mmc_dbg("unknown resp_type %04x\n", resp_type(cmd)); - break; - } + case RESP_R7: + cmd_reg |= MMCCMD_RSPFMT_R1456; + break; + case RESP_R2: /* 136 bits, CRC */ + cmd_reg |= MMCCMD_RSPFMT_R2; + break; + case RESP_R3: /* 48 bits, no CRC */ + cmd_reg |= MMCCMD_RSPFMT_R3; + break; + default: + cmd_reg |= MMCCMD_RSPFMT_NONE; + mmc_dbg("unknown resp_type %04x\n", resp_type(cmd)); + break; + } - /* Set command index */ - cmd_reg |= cmd->cmd_code; + /* Set command index */ + cmd_reg |= cmd->cmd_code; - /* Enable EDMA transfer triggers */ - if (host->do_dma == RT_TRUE) - cmd_reg |= MMCCMD_DMATRIG; + /* Enable EDMA transfer triggers */ + if (host->do_dma == RT_TRUE) + cmd_reg |= MMCCMD_DMATRIG; - if (host->data != RT_NULL && host->data_dir == DM365_MMC_DATADIR_READ) - cmd_reg |= MMCCMD_DMATRIG; + if (host->data != RT_NULL && host->data_dir == DM365_MMC_DATADIR_READ) + cmd_reg |= MMCCMD_DMATRIG; - /* Setting whether command involves data transfer or not */ - if (cmd->data) - cmd_reg |= MMCCMD_WDATX; + /* Setting whether command involves data transfer or not */ + if (cmd->data) + cmd_reg |= MMCCMD_WDATX; - /* Setting whether stream or block transfer */ - if (cmd->flags & MMC_DATA_STREAM) - { - mmc_dbg("to do\n"); - cmd_reg |= MMCCMD_STRMTP; - } + /* Setting whether stream or block transfer */ + if (cmd->flags & MMC_DATA_STREAM) + { + mmc_dbg("to do\n"); + cmd_reg |= MMCCMD_STRMTP; + } - /* Setting whether data read or write */ - if (host->data_dir == DM365_MMC_DATADIR_WRITE) - cmd_reg |= MMCCMD_DTRW; + /* Setting whether data read or write */ + if (host->data_dir == DM365_MMC_DATADIR_WRITE) + cmd_reg |= MMCCMD_DTRW; - if (host->bus_mode == MMCSD_BUSMODE_PUSHPULL) - { - cmd_reg |= MMCCMD_PPLEN; - } - - /* set Command timeout */ - host->mmcsd_regs->MMCTOR = 0x1FFF; - - /* Enable interrupt (calculate here, defer until FIFO is stuffed). */ - im_val = MMCST0_RSPDNE | MMCST0_CRCRS | MMCST0_TOUTRS; - if (host->data_dir == DM365_MMC_DATADIR_WRITE) - { - im_val |= MMCST0_DATDNE | MMCST0_CRCWR; + if (host->bus_mode == MMCSD_BUSMODE_PUSHPULL) + { + cmd_reg |= MMCCMD_PPLEN; + } - if (host->do_dma == RT_FALSE) - im_val |= MMCST0_DXRDY; - } - else if (host->data_dir == DM365_MMC_DATADIR_READ) - { - im_val |= MMCST0_DATDNE | MMCST0_CRCRD | MMCST0_TOUTRD; + /* set Command timeout */ + host->mmcsd_regs->MMCTOR = 0x1FFF; - if (host->do_dma == RT_FALSE) - im_val |= MMCST0_DRRDY; - } + /* Enable interrupt (calculate here, defer until FIFO is stuffed). */ + im_val = MMCST0_RSPDNE | MMCST0_CRCRS | MMCST0_TOUTRS; + if (host->data_dir == DM365_MMC_DATADIR_WRITE) + { + im_val |= MMCST0_DATDNE | MMCST0_CRCWR; - /* - * Before non-DMA WRITE commands the controller needs priming: - * FIFO should be populated with 32 bytes i.e. whatever is the FIFO size - */ - if ((host->do_dma == RT_FALSE) && (host->data_dir == DM365_MMC_DATADIR_WRITE)) - dm365_fifo_data_trans(host, rw_threshold); + if (host->do_dma == RT_FALSE) + im_val |= MMCST0_DXRDY; + } + else if (host->data_dir == DM365_MMC_DATADIR_READ) + { + im_val |= MMCST0_DATDNE | MMCST0_CRCRD | MMCST0_TOUTRD; - host->mmcsd_regs->MMCARGHL = cmd->arg; - host->mmcsd_regs->MMCCMD = cmd_reg; - host->mmcsd_regs->MMCIM = im_val; + if (host->do_dma == RT_FALSE) + im_val |= MMCST0_DRRDY; + } + + /* + * Before non-DMA WRITE commands the controller needs priming: + * FIFO should be populated with 32 bytes i.e. whatever is the FIFO size + */ + if ((host->do_dma == RT_FALSE) && (host->data_dir == DM365_MMC_DATADIR_WRITE)) + dm365_fifo_data_trans(host, rw_threshold); + + host->mmcsd_regs->MMCARGHL = cmd->arg; + host->mmcsd_regs->MMCCMD = cmd_reg; + host->mmcsd_regs->MMCIM = im_val; } /******************************************************************************************************* -** : dm365_abort_dma() -** : ˺ֹDMA -** -** 䡡: host -> DM365 mmc host +** 函数名称: dm365_abort_dma() +** 功能描述: 此函数终止DMA传输 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 mmc host 句柄 +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void dm365_abort_dma(struct mmc_dm365_host *host) { - int sync_dev; + int sync_dev; - if (host->data_dir == DM365_MMC_DATADIR_READ) - sync_dev = host->rxdma; - else - sync_dev = host->txdma; + if (host->data_dir == DM365_MMC_DATADIR_READ) + sync_dev = host->rxdma; + else + sync_dev = host->txdma; - //EDMA3DisableTransfer(EDMA0CC0_REG_BASE, sync_dev, EDMA3_TRIG_MODE_EVENT); - edma_stop(sync_dev); - edma_clean_channel(sync_dev); + //EDMA3DisableTransfer(EDMA0CC0_REG_BASE, sync_dev, EDMA3_TRIG_MODE_EVENT); + edma_stop(sync_dev); + edma_clean_channel(sync_dev); } /******************************************************************************************************* -** : mmc_request_done() -** : ˺ڽһMMC -** -** 䡡: host -> DM365 mmc host -** mrq -> request +** 函数名称: mmc_request_done() +** 功能描述: 此函数用于结束处理一个MMC请求 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 mmc host 句柄 +** mrq -> request 句柄 +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ void mmc_request_done(struct rt_mmcsd_host *host, struct rt_mmcsd_req *mrq) { - struct rt_mmcsd_cmd *cmd = mrq->cmd; - int err = cmd->err; + struct rt_mmcsd_cmd *cmd = mrq->cmd; + int err = cmd->err; - if (err && cmd->retries) - { - mmc_dbg("req failed (CMD%u): %d, retrying...\n", cmd->cmd_code, err); + if (err && cmd->retries) + { + mmc_dbg("req failed (CMD%u): %d, retrying...\n", cmd->cmd_code, err); - cmd->retries--; - cmd->err = 0; - host->ops->request(host, mrq); - } - else - { - mmc_dbg("%s: req done (CMD%u): %d: %08x %08x %08x %08x\n", - "dm365 host", cmd->cmd_code, err, - cmd->resp[0], cmd->resp[1], - cmd->resp[2], cmd->resp[3]); + cmd->retries--; + cmd->err = 0; + host->ops->request(host, mrq); + } + else + { + mmc_dbg("%s: req done (CMD%u): %d: %08x %08x %08x %08x\n", + "dm365 host", cmd->cmd_code, err, + cmd->resp[0], cmd->resp[1], + cmd->resp[2], cmd->resp[3]); - if (mrq->data) - { - mmc_dbg("%s: %d bytes transferred: %d\n", - "dm365 host", - mrq->data->bytes_xfered, mrq->data->err); - } + if (mrq->data) + { + mmc_dbg("%s: %d bytes transferred: %d\n", + "dm365 host", + mrq->data->bytes_xfered, mrq->data->err); + } - if (mrq->stop) - { - mmc_dbg("%s: (CMD%u): %d: %08x %08x %08x %08x\n", - "dm365 host", mrq->stop->cmd_code, - mrq->stop->err, - mrq->stop->resp[0], mrq->stop->resp[1], - mrq->stop->resp[2], mrq->stop->resp[3]); - } + if (mrq->stop) + { + mmc_dbg("%s: (CMD%u): %d: %08x %08x %08x %08x\n", + "dm365 host", mrq->stop->cmd_code, + mrq->stop->err, + mrq->stop->resp[0], mrq->stop->resp[1], + mrq->stop->resp[2], mrq->stop->resp[3]); + } - mmcsd_req_complete(host); - } + mmcsd_req_complete(host); + } } /******************************************************************************************************* -** : mmc_dm365_xfer_done() -** : ݴͽô˺ -** -** 䡡: host -> DM365 mmc host -** data -> data +** 函数名称: mmc_dm365_xfer_done() +** 功能描述: 数据传送结束调用此函数 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 mmc host 句柄 +** data -> data 句柄 +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void mmc_dm365_xfer_done(struct mmc_dm365_host *host, struct rt_mmcsd_data *data) { - host->data = RT_NULL; + host->data = RT_NULL; - if (host->mmc->flags & MMCSD_SUP_SDIO_IRQ) { - /* - * SDIO Interrupt Detection work-around as suggested by - * Davinci Errata (TMS320DM355 Silicon Revision 1.1 Errata - * 2.1.6): Signal SDIO interrupt only if it is enabled by core - */ - if (host->sdio_int && !(host->mmcsd_regs->SDIOST0 & - SDIOST0_DAT1_HI)) { - host->mmcsd_regs->SDIOIST = SDIOIST_IOINT; - sdio_irq_wakeup(host->mmc); - } - } + if (host->mmc->flags & MMCSD_SUP_SDIO_IRQ) { + /* + * SDIO Interrupt Detection work-around as suggested by + * Davinci Errata (TMS320DM355 Silicon Revision 1.1 Errata + * 2.1.6): Signal SDIO interrupt only if it is enabled by core + */ + if (host->sdio_int && !(host->mmcsd_regs->SDIOST0 & + SDIOST0_DAT1_HI)) { + host->mmcsd_regs->SDIOIST = SDIOIST_IOINT; + sdio_irq_wakeup(host->mmc); + } + } - if (host->do_dma == RT_TRUE) - { - dm365_abort_dma(host); + if (host->do_dma == RT_TRUE) + { + dm365_abort_dma(host); - if (data->flags & DATA_DIR_READ) - { - /* read operation */ - if (host->use_dma_buffer == RT_TRUE) - { - /* copy DMA buffer to read buffer */ - memcpy(data->buf, (void*)MMU_NOCACHE_ADDR(host->dma_buffer), data->blks * data->blksize); - } - /*else - { - mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blks * data->blksize); - }*/ - } + if (data->flags & DATA_DIR_READ) + { + /* read operation */ + if (host->use_dma_buffer == RT_TRUE) + { + /* copy DMA buffer to read buffer */ + memcpy(data->buf, (void*)MMU_NOCACHE_ADDR(host->dma_buffer), data->blks * data->blksize); + } + /*else + { + mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blks * data->blksize); + }*/ + } - host->do_dma = RT_FALSE; - } - - host->data_dir = DM365_MMC_DATADIR_NONE; + host->do_dma = RT_FALSE; + } - if (!data->stop || (host->cmd && host->cmd->err)) - { - mmc_request_done(host->mmc, data->mrq); - host->mmcsd_regs->MMCIM = 0; - } - else - mmc_dm365_start_command(host, data->stop); + host->data_dir = DM365_MMC_DATADIR_NONE; + + if (!data->stop || (host->cmd && host->cmd->err)) + { + mmc_request_done(host->mmc, data->mrq); + host->mmcsd_regs->MMCIM = 0; + } + else + mmc_dm365_start_command(host, data->stop); } static void mmc_dm365_dma_cb(unsigned channel, rt_uint16_t ch_status, void *data) { - if (DMA_COMPLETE != ch_status) { - struct mmc_dm365_host *host = data; + if (DMA_COMPLETE != ch_status) { + struct mmc_dm365_host *host = data; - /* Currently means: DMA Event Missed, or "null" transfer - * request was seen. In the future, TC errors (like bad - * addresses) might be presented too. - */ - mmc_dbg("DMA %s error\n", - (host->data->flags & MMC_DATA_WRITE) - ? "write" : "read"); - host->data->err = -RT_EIO; - mmc_dm365_xfer_done(host, host->data); - } + /* Currently means: DMA Event Missed, or "null" transfer + * request was seen. In the future, TC errors (like bad + * addresses) might be presented too. + */ + mmc_dbg("DMA %s error\n", + (host->data->flags & MMC_DATA_WRITE) + ? "write" : "read"); + host->data->err = -RT_EIO; + mmc_dm365_xfer_done(host, host->data); + } } /******************************************************************************************************* -** : mmc_dm365_dma_setup() -** : DMA ú -** -** 䡡: host -> DM365 mmc host -** tx -> жTxRx -** template -> ڱEDMA3CCPaRAMEntry +** 函数名称: mmc_dm365_dma_setup() +** 功能描述: DMA 设置函数 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 mmc host 句柄 +** tx -> 布尔变量，用于判断Tx或者是Rx +** template -> 用于保存EDMA3CCPaRAMEntry机构数据 +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void mmc_dm365_dma_setup(struct mmc_dm365_host *host, rt_bool_t tx, struct edmacc_param *template) { - rt_uint32_t sync_dev; - const rt_uint16_t acnt = 4; - const rt_uint16_t bcnt = rw_threshold >> 2; - const rt_uint16_t ccnt = 0; - rt_uint32_t src_port = 0; - rt_uint32_t dst_port = 0; - rt_int16_t src_bidx, dst_bidx; - rt_int16_t src_cidx, dst_cidx; + rt_uint32_t sync_dev; + const rt_uint16_t acnt = 4; + const rt_uint16_t bcnt = rw_threshold >> 2; + const rt_uint16_t ccnt = 0; + rt_uint32_t src_port = 0; + rt_uint32_t dst_port = 0; + rt_int16_t src_bidx, dst_bidx; + rt_int16_t src_cidx, dst_cidx; //edmacc_param paramSet; - /* - * A-B Sync transfer: each DMA request is for one "frame" of - * rw_threshold bytes, broken into "acnt"-size chunks repeated - * "bcnt" times. Each segment needs "ccnt" such frames; since - * we tell the block layer our mmc->max_seg_size limit, we can - * trust (later) that it's within bounds. - * - * The FIFOs are read/written in 4-byte chunks (acnt == 4) and - * EDMA will optimize memory operations to use larger bursts. - */ - if (tx) - { - sync_dev = host->txdma; + /* + * A-B Sync transfer: each DMA request is for one "frame" of + * rw_threshold bytes, broken into "acnt"-size chunks repeated + * "bcnt" times. Each segment needs "ccnt" such frames; since + * we tell the block layer our mmc->max_seg_size limit, we can + * trust (later) that it's within bounds. + * + * The FIFOs are read/written in 4-byte chunks (acnt == 4) and + * EDMA will optimize memory operations to use larger bursts. + */ + if (tx) + { + sync_dev = host->txdma; - /* src_prt, ccnt, and link to be set up later */ - /*paramSet.srcBIdx = acnt; - paramSet.srcCIdx = acnt * bcnt; + /* src_prt, ccnt, and link to be set up later */ + /*paramSet.srcBIdx = acnt; + paramSet.srcCIdx = acnt * bcnt; - paramSet.destAddr = (rt_uint32_t)&(host->mmcsd_regs->MMCDXR); - paramSet.destBIdx = 0; - paramSet.destCIdx = 0;*/ - /* src_prt, ccnt, and link to be set up later */ - src_bidx = acnt; - src_cidx = acnt * bcnt; + paramSet.destAddr = (rt_uint32_t)&(host->mmcsd_regs->MMCDXR); + paramSet.destBIdx = 0; + paramSet.destCIdx = 0;*/ + /* src_prt, ccnt, and link to be set up later */ + src_bidx = acnt; + src_cidx = acnt * bcnt; - dst_port = (rt_uint32_t)&(host->mmcsd_regs->MMCDXR); - dst_bidx = 0; - dst_cidx = 0; - } - else - { - sync_dev = host->rxdma; + dst_port = (rt_uint32_t)&(host->mmcsd_regs->MMCDXR); + dst_bidx = 0; + dst_cidx = 0; + } + else + { + sync_dev = host->rxdma; - /* dst_prt, ccnt, and link to be set up later */ - /*paramSet.srcAddr = (rt_uint32_t)&(host->mmcsd_regs->MMCDRR); - paramSet.srcBIdx = 0; - paramSet.srcCIdx = 0; + /* dst_prt, ccnt, and link to be set up later */ + /*paramSet.srcAddr = (rt_uint32_t)&(host->mmcsd_regs->MMCDRR); + paramSet.srcBIdx = 0; + paramSet.srcCIdx = 0; - paramSet.destBIdx = acnt; - paramSet.destCIdx = acnt * bcnt;*/ - src_port = (rt_uint32_t)&(host->mmcsd_regs->MMCDRR); - src_bidx = 0; - src_cidx = 0; + paramSet.destBIdx = acnt; + paramSet.destCIdx = acnt * bcnt;*/ + src_port = (rt_uint32_t)&(host->mmcsd_regs->MMCDRR); + src_bidx = 0; + src_cidx = 0; - /* dst_prt, ccnt, and link to be set up later */ - dst_bidx = acnt; - dst_cidx = acnt * bcnt; - } - /* - * We can't use FIFO mode for the FIFOs because MMC FIFO addresses - * are not 256-bit (32-byte) aligned. So we use INCR, and the W8BIT - * parameter is ignored. - */ - edma_set_src(sync_dev, src_port, INCR, W8BIT); - edma_set_dest(sync_dev, dst_port, INCR, W8BIT); + /* dst_prt, ccnt, and link to be set up later */ + dst_bidx = acnt; + dst_cidx = acnt * bcnt; + } + /* + * We can't use FIFO mode for the FIFOs because MMC FIFO addresses + * are not 256-bit (32-byte) aligned. So we use INCR, and the W8BIT + * parameter is ignored. + */ + edma_set_src(sync_dev, src_port, INCR, W8BIT); + edma_set_dest(sync_dev, dst_port, INCR, W8BIT); - edma_set_src_index(sync_dev, src_bidx, src_cidx); - edma_set_dest_index(sync_dev, dst_bidx, dst_cidx); + edma_set_src_index(sync_dev, src_bidx, src_cidx); + edma_set_dest_index(sync_dev, dst_bidx, dst_cidx); - edma_set_transfer_params(sync_dev, acnt, bcnt, ccnt, 8, ABSYNC); + edma_set_transfer_params(sync_dev, acnt, bcnt, ccnt, 8, ABSYNC); - edma_read_slot(sync_dev, template); + edma_read_slot(sync_dev, template); + + /* don't bother with irqs or chaining */ + template->opt |= EDMA_CHAN_SLOT(sync_dev) << 12; - /* don't bother with irqs or chaining */ - template->opt |= EDMA_CHAN_SLOT(sync_dev) << 12; - #if 0 - paramSet.opt = 0u; - /* Src & Dest are in INCR modes */ - paramSet.opt &= 0xFFFFFFFCu; - /* Program the TCC */ - paramSet.opt |= ((sync_dev << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC); - - paramSet.aCnt = acnt; - paramSet.bCnt = bcnt; - - /* AB Sync Transfer Mode */ - paramSet.opt |= (1 << EDMA3CC_OPT_SYNCDIM_SHIFT); - - /* Now, write the PaRAM Set. */ - EDMA3SetPaRAM(EDMA0CC0_REG_BASE, sync_dev, ¶mSet); + paramSet.opt = 0u; + /* Src & Dest are in INCR modes */ + paramSet.opt &= 0xFFFFFFFCu; + /* Program the TCC */ + paramSet.opt |= ((sync_dev << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC); - EDMA3GetPaRAM(EDMA0CC0_REG_BASE, sync_dev, template); + paramSet.aCnt = acnt; + paramSet.bCnt = bcnt; + + /* AB Sync Transfer Mode */ + paramSet.opt |= (1 << EDMA3CC_OPT_SYNCDIM_SHIFT); + + /* Now, write the PaRAM Set. */ + EDMA3SetPaRAM(EDMA0CC0_REG_BASE, sync_dev, ¶mSet); + + EDMA3GetPaRAM(EDMA0CC0_REG_BASE, sync_dev, template); #endif } /******************************************************************************************************* -** : mmc_dm365_send_dma_request() -** : DMA -** -** 䡡: host -> DM365 mmc host -** data -> DMAݽṹ +** 函数名称: mmc_dm365_send_dma_request() +** 功能描述: 发送DMA请求 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 mmc host 句柄 +** data -> DMA传送数据结构句柄 +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void mmc_dm365_send_dma_request(struct mmc_dm365_host *host, struct rt_mmcsd_data *data) { - //struct EDMA3CCPaRAMEntry *template; - struct edmacc_param *template; - rt_uint32_t buf_ptr; - rt_uint32_t channel; - rt_uint32_t bytes_left = host->bytes_left; - rt_uint32_t count = host->bytes_left; - const rt_uint32_t shift = ffs(rw_threshold) - 1; + //struct EDMA3CCPaRAMEntry *template; + struct edmacc_param *template; + rt_uint32_t buf_ptr; + rt_uint32_t channel; + rt_uint32_t bytes_left = host->bytes_left; + rt_uint32_t count = host->bytes_left; + const rt_uint32_t shift = ffs(rw_threshold) - 1; - if (host->use_dma_buffer == RT_TRUE) - buf_ptr = host->dma_buffer;//MMU_NOCACHE_ADDR(host->dma_buffer); - else - buf_ptr = (rt_uint32_t)data->buf; + if (host->use_dma_buffer == RT_TRUE) + buf_ptr = host->dma_buffer;//MMU_NOCACHE_ADDR(host->dma_buffer); + else + buf_ptr = (rt_uint32_t)data->buf; - if (host->data_dir == DM365_MMC_DATADIR_WRITE) - { - template = &host->tx_template; - channel = host->txdma; - } - else - { - template = &host->rx_template; - channel = host->rxdma; - } + if (host->data_dir == DM365_MMC_DATADIR_WRITE) + { + template = &host->tx_template; + channel = host->txdma; + } + else + { + template = &host->rx_template; + channel = host->rxdma; + } - template->link_bcntrld = 0xffff; - //template->bCntReload = 0x0; + template->link_bcntrld = 0xffff; + //template->bCntReload = 0x0; - if (count > bytes_left) - count = bytes_left; - bytes_left -= count; + if (count > bytes_left) + count = bytes_left; + bytes_left -= count; - if (host->data_dir == DM365_MMC_DATADIR_WRITE) - template->src = buf_ptr; - else - template->dst = buf_ptr; - template->ccnt = count >> shift; + if (host->data_dir == DM365_MMC_DATADIR_WRITE) + template->src = buf_ptr; + else + template->dst = buf_ptr; + template->ccnt = count >> shift; - edma_write_slot(channel, template); + edma_write_slot(channel, template); - edma_clear_event(channel); + edma_clear_event(channel); - /*EDMA3SetPaRAM(EDMA0CC0_REG_BASE, channel, template); - EDMA3ClrEvt(EDMA0CC0_REG_BASE, channel); - EDMA3EnableTransfer(EDMA0CC0_REG_BASE, channel, EDMA3_TRIG_MODE_EVENT);*/ - edma_start(channel); + /*EDMA3SetPaRAM(EDMA0CC0_REG_BASE, channel, template); + EDMA3ClrEvt(EDMA0CC0_REG_BASE, channel); + EDMA3EnableTransfer(EDMA0CC0_REG_BASE, channel, EDMA3_TRIG_MODE_EVENT);*/ + edma_start(channel); } /******************************************************************************************************* -** : mmc_dm365_start_dma_transfer() -** : ʼDMA -** -** 䡡: host -> DM365 mmc host -** data -> DMAݽṹ +** 函数名称: mmc_dm365_start_dma_transfer() +** 功能描述: 开始DMA传输 ** -** 䡡: DMAֽ -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 mmc host 句柄 +** data -> DMA传送数据结构句柄 +** +** 输　出: DMA传输字节数 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static int mmc_dm365_start_dma_transfer(struct mmc_dm365_host *host, struct rt_mmcsd_data *data) { - /* set initial value */ - host->use_dma_buffer = RT_FALSE; + /* set initial value */ + host->use_dma_buffer = RT_FALSE; - if (!(data->flags & DATA_DIR_READ)) - { - if ((rt_uint32_t)data->buf & (RT_ALIGN_SIZE - 1)) - { - /* not align to basic size, use DMA buffer */ - host->use_dma_buffer = RT_TRUE; - memcpy((void*)MMU_NOCACHE_ADDR(host->dma_buffer), data->buf, data->blks * data->blksize); - } - else - { - rt_uint32_t addr; - addr = ((rt_uint32_t)data->buf & ~(CACHE_LINE_SIZE - 1)); - /* write data case, always clean DCache */ - mmu_clean_dcache(addr, (data->blks + 1)* data->blksize); - } - } - else - { - /* whether align to cache line in read operation */ - if (((rt_uint32_t)data->buf) & (CACHE_LINE_SIZE - 1)) - host->use_dma_buffer = RT_TRUE; - else - mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blks * data->blksize); - } + if (!(data->flags & DATA_DIR_READ)) + { + if ((rt_uint32_t)data->buf & (RT_ALIGN_SIZE - 1)) + { + /* not align to basic size, use DMA buffer */ + host->use_dma_buffer = RT_TRUE; + memcpy((void*)MMU_NOCACHE_ADDR(host->dma_buffer), data->buf, data->blks * data->blksize); + } + else + { + rt_uint32_t addr; + addr = ((rt_uint32_t)data->buf & ~(CACHE_LINE_SIZE - 1)); + /* write data case, always clean DCache */ + mmu_clean_dcache(addr, (data->blks + 1)* data->blksize); + } + } + else + { + /* whether align to cache line in read operation */ + if (((rt_uint32_t)data->buf) & (CACHE_LINE_SIZE - 1)) + host->use_dma_buffer = RT_TRUE; + else + mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blks * data->blksize); + } - host->do_dma = RT_TRUE; - mmc_dm365_send_dma_request(host, data); + host->do_dma = RT_TRUE; + mmc_dm365_send_dma_request(host, data); - return 0; + return 0; } #if 0 /******************************************************************************************************* -** : acquire_dma_channels() -** : ȡDMA channel -** -** 䡡: host -> DM365 mmc host +** 函数名称: acquire_dma_channels() +** 功能描述: 获取DMA channel ** -** 䡡: DMA ͨ -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 mmc host 句柄 +** +** 输　出: DMA 通道号 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static int acquire_dma_channels(struct mmc_dm365_host *host) { - int r; + int r; - /* Acquire master DMA write channel */ - r = EDMA3RequestChannel(EDMA0CC0_REG_BASE, EDMA3_CHANNEL_TYPE_DMA, host->txdma, host->txdma, EVT_QUEUE_NUM); - if (r < 0) - { - rt_kprintf("alloc %s channel err %d\n", "tx", r); - return r; - } - mmc_dm365_dma_setup(host, RT_TRUE, &host->tx_template); + /* Acquire master DMA write channel */ + r = EDMA3RequestChannel(EDMA0CC0_REG_BASE, EDMA3_CHANNEL_TYPE_DMA, host->txdma, host->txdma, EVT_QUEUE_NUM); + if (r < 0) + { + rt_kprintf("alloc %s channel err %d\n", "tx", r); + return r; + } + mmc_dm365_dma_setup(host, RT_TRUE, &host->tx_template); - /* Acquire master DMA read channel */ - r = EDMA3RequestChannel(EDMA0CC0_REG_BASE, EDMA3_CHANNEL_TYPE_DMA, host->rxdma, host->rxdma, EVT_QUEUE_NUM); - if (r < 0) - { - rt_kprintf("alloc %s channel err %d\n", "rx", r); - goto free_master_write; - } - mmc_dm365_dma_setup(host, RT_FALSE, &host->rx_template); + /* Acquire master DMA read channel */ + r = EDMA3RequestChannel(EDMA0CC0_REG_BASE, EDMA3_CHANNEL_TYPE_DMA, host->rxdma, host->rxdma, EVT_QUEUE_NUM); + if (r < 0) + { + rt_kprintf("alloc %s channel err %d\n", "rx", r); + goto free_master_write; + } + mmc_dm365_dma_setup(host, RT_FALSE, &host->rx_template); - return 0; + return 0; free_master_write: - EDMA3FreeChannel(EDMA0CC0_REG_BASE, EDMA3_CHANNEL_TYPE_DMA, host->txdma, EDMA3_TRIG_MODE_EVENT, host->txdma, EVT_QUEUE_NUM); + EDMA3FreeChannel(EDMA0CC0_REG_BASE, EDMA3_CHANNEL_TYPE_DMA, host->txdma, EDMA3_TRIG_MODE_EVENT, host->txdma, EVT_QUEUE_NUM); - return r; + return r; } #endif static int acquire_dma_channels(struct mmc_dm365_host *host) { - //u32 link_size; - int r, i; + //u32 link_size; + int r, i; - /* Acquire master DMA write channel */ - r = edma_alloc_channel(host->txdma, mmc_dm365_dma_cb, host, - EVENTQ_DEFAULT); - if (r < 0) { - mmc_dbg("alloc %s channel err %d\n", - "tx", r); - return r; - } - mmc_dm365_dma_setup(host, RT_TRUE, &host->tx_template); + /* Acquire master DMA write channel */ + r = edma_alloc_channel(host->txdma, mmc_dm365_dma_cb, host, + EVENTQ_DEFAULT); + if (r < 0) { + mmc_dbg("alloc %s channel err %d\n", + "tx", r); + return r; + } + mmc_dm365_dma_setup(host, RT_TRUE, &host->tx_template); - /* Acquire master DMA read channel */ - r = edma_alloc_channel(host->rxdma, mmc_dm365_dma_cb, host, - EVENTQ_DEFAULT); - if (r < 0) { - mmc_dbg("alloc %s channel err %d\n", - "rx", r); - goto free_master_write; - } - mmc_dm365_dma_setup(host, RT_FALSE, &host->rx_template); + /* Acquire master DMA read channel */ + r = edma_alloc_channel(host->rxdma, mmc_dm365_dma_cb, host, + EVENTQ_DEFAULT); + if (r < 0) { + mmc_dbg("alloc %s channel err %d\n", + "rx", r); + goto free_master_write; + } + mmc_dm365_dma_setup(host, RT_FALSE, &host->rx_template); - /* Allocate parameter RAM slots, which will later be bound to a - * channel as needed to handle a scatterlist. - */ + /* Allocate parameter RAM slots, which will later be bound to a + * channel as needed to handle a scatterlist. + */ #if 0 - link_size = min_t(unsigned, host->nr_sg, ARRAY_SIZE(host->links)); - for (i = 0; i < link_size; i++) { - r = edma_alloc_slot(EDMA_CTLR(host->txdma), EDMA_SLOT_ANY); - if (r < 0) { - mmc_dbg("dma PaRAM alloc --> %d\n", - r); - break; - } - host->links[i] = r; - } - host->n_link = i; + link_size = min_t(unsigned, host->nr_sg, ARRAY_SIZE(host->links)); + for (i = 0; i < link_size; i++) { + r = edma_alloc_slot(EDMA_CTLR(host->txdma), EDMA_SLOT_ANY); + if (r < 0) { + mmc_dbg("dma PaRAM alloc --> %d\n", + r); + break; + } + host->links[i] = r; + } + host->n_link = i; #endif - return 0; + return 0; free_master_write: - edma_free_channel(host->txdma); + edma_free_channel(host->txdma); - return r; + return r; } /******************************************************************************************************* -** : mmc_dm365_prepare_data() -** : ׼ DMA -** -** 䡡: host -> DM365 mmc host -** req -> SD request ṹ +** 函数名称: mmc_dm365_prepare_data() +** 功能描述: 准备 DMA 数据 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 mmc host 句柄 +** req -> SD request 结构句柄 +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void mmc_dm365_prepare_data(struct mmc_dm365_host *host, struct rt_mmcsd_req *req) { - int timeout; - int fifo_lev; - struct rt_mmcsd_data *data = req->data; + int timeout; + int fifo_lev; + struct rt_mmcsd_data *data = req->data; - fifo_lev = (rw_threshold == 64) ? MMCFIFOCTL_FIFOLEV : 0; + fifo_lev = (rw_threshold == 64) ? MMCFIFOCTL_FIFOLEV : 0; - host->data = data; - if (data == RT_NULL) - { - host->data_dir = DM365_MMC_DATADIR_NONE; - host->mmcsd_regs->MMCBLEN = 0; - host->mmcsd_regs->MMCNBLK = 0; - return; - } + host->data = data; + if (data == RT_NULL) + { + host->data_dir = DM365_MMC_DATADIR_NONE; + host->mmcsd_regs->MMCBLEN = 0; + host->mmcsd_regs->MMCNBLK = 0; + return; + } - mmc_dbg("%s %s, %d blocks of %d bytes\n", - (data->flags & DATA_STREAM) ? "stream" : "block", - (data->flags & DATA_DIR_WRITE) ? "write" : "read", - data->blks, data->blksize); - mmc_dbg(" DTO %d cycles + %d ns\n", - data->timeout_clks, data->timeout_ns); - timeout = data->timeout_clks + (data->timeout_ns / host->ns_in_one_cycle); - if (timeout > 0xffff) - timeout = 0xffff; + mmc_dbg("%s %s, %d blocks of %d bytes\n", + (data->flags & DATA_STREAM) ? "stream" : "block", + (data->flags & DATA_DIR_WRITE) ? "write" : "read", + data->blks, data->blksize); + mmc_dbg(" DTO %d cycles + %d ns\n", + data->timeout_clks, data->timeout_ns); + timeout = data->timeout_clks + (data->timeout_ns / host->ns_in_one_cycle); + if (timeout > 0xffff) + timeout = 0xffff; - host->mmcsd_regs->MMCTOD = timeout; - host->mmcsd_regs->MMCNBLK = data->blks; - host->mmcsd_regs->MMCBLEN = data->blksize; - - /* Configure the FIFO */ - switch (data->flags & DATA_DIR_WRITE) - { - case DATA_DIR_WRITE: - host->data_dir = DM365_MMC_DATADIR_WRITE; - host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST; - host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_WR; - break; + host->mmcsd_regs->MMCTOD = timeout; + host->mmcsd_regs->MMCNBLK = data->blks; + host->mmcsd_regs->MMCBLEN = data->blksize; - default: - host->data_dir = DM365_MMC_DATADIR_READ; - host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST; - host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_RD; - break; - } + /* Configure the FIFO */ + switch (data->flags & DATA_DIR_WRITE) + { + case DATA_DIR_WRITE: + host->data_dir = DM365_MMC_DATADIR_WRITE; + host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST; + host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_WR; + break; - host->buffer = RT_NULL; - host->bytes_left = data->blks * data->blksize; + default: + host->data_dir = DM365_MMC_DATADIR_READ; + host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST; + host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_RD; + break; + } - /* For now we try to use DMA whenever we won't need partial FIFO - * reads or writes, either for the whole transfer (as tested here) - * or for any individual scatterlist segment (tested when we call - * start_dma_transfer). - * - * While we *could* change that, unusual block sizes are rarely - * used. The occasional fallback to PIO should't hurt. - */ - if ((host->use_dma == RT_TRUE) && (host->bytes_left & (rw_threshold - 1)) == 0 && - mmc_dm365_start_dma_transfer(host, data) == 0) - { - /* zero this to ensure we take no PIO paths */ - host->bytes_left = 0; - } - else - { - /* Revert to CPU Copy */ - host->buffer = (rt_uint8_t*)req->data->buf; - } + host->buffer = RT_NULL; + host->bytes_left = data->blks * data->blksize; + + /* For now we try to use DMA whenever we won't need partial FIFO + * reads or writes, either for the whole transfer (as tested here) + * or for any individual scatterlist segment (tested when we call + * start_dma_transfer). + * + * While we *could* change that, unusual block sizes are rarely + * used. The occasional fallback to PIO should't hurt. + */ + if ((host->use_dma == RT_TRUE) && (host->bytes_left & (rw_threshold - 1)) == 0 && + mmc_dm365_start_dma_transfer(host, data) == 0) + { + /* zero this to ensure we take no PIO paths */ + host->bytes_left = 0; + } + else + { + /* Revert to CPU Copy */ + host->buffer = (rt_uint8_t*)req->data->buf; + } } /******************************************************************************************************* -** : mmc_dm365_request() -** : ˺ʵSD request -** -** 䡡: host -> DM365 mmc host -** req -> SD request ṹ +** 函数名称: mmc_dm365_request() +** 功能描述: 此函数实现SD request操作 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 mmc host 句柄 +** req -> SD request 结构句柄 +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void mmc_dm365_request(struct rt_mmcsd_host *mmc, struct rt_mmcsd_req *req) { - struct mmc_dm365_host *host = mmc_priv(mmc); - unsigned long timeout = rt_tick_get() + 900; - rt_uint32_t mmcst1 = 0; + struct mmc_dm365_host *host = mmc_priv(mmc); + unsigned long timeout = rt_tick_get() + 900; + rt_uint32_t mmcst1 = 0; - /* Card may still be sending BUSY after a previous operation, - * typically some kind of write. If so, we can't proceed yet. - */ - while (rt_tick_get() < timeout) + /* Card may still be sending BUSY after a previous operation, + * typically some kind of write. If so, we can't proceed yet. + */ + while (rt_tick_get() < timeout) { - mmcst1 = host->mmcsd_regs->MMCST1; - if (!(mmcst1 & MMCST1_BUSY)) - break; - } - if (mmcst1 & MMCST1_BUSY) + mmcst1 = host->mmcsd_regs->MMCST1; + if (!(mmcst1 & MMCST1_BUSY)) + break; + } + if (mmcst1 & MMCST1_BUSY) { - mmc_dbg("still BUSY? bad ... \n"); - req->cmd->err = -RT_ETIMEOUT; - mmc_request_done(mmc, req); - return; - } + mmc_dbg("still BUSY? bad ... \n"); + req->cmd->err = -RT_ETIMEOUT; + mmc_request_done(mmc, req); + return; + } - host->do_dma = RT_FALSE; - mmc_dm365_prepare_data(host, req); - mmc_dm365_start_command(host, req->cmd); + host->do_dma = RT_FALSE; + mmc_dm365_prepare_data(host, req); + mmc_dm365_start_command(host, req->cmd); } static void mmc_dm365_enable_sdio_irq(struct rt_mmcsd_host *mmc, rt_int32_t enable) { - struct mmc_dm365_host *host = mmc_priv(mmc); + struct mmc_dm365_host *host = mmc_priv(mmc); - if (enable) - { - if (!(host->mmcsd_regs->SDIOST0 & SDIOST0_DAT1_HI)) - { - host->mmcsd_regs->SDIOIST = SDIOIST_IOINT; - sdio_irq_wakeup(host->mmc); - } - else - { - host->sdio_int = RT_TRUE; - host->mmcsd_regs->SDIOIEN |= SDIOIEN_IOINTEN; - } - } - else - { - host->sdio_int = RT_FALSE; - host->mmcsd_regs->SDIOIEN &= ~SDIOIEN_IOINTEN; - } + if (enable) + { + if (!(host->mmcsd_regs->SDIOST0 & SDIOST0_DAT1_HI)) + { + host->mmcsd_regs->SDIOIST = SDIOIST_IOINT; + sdio_irq_wakeup(host->mmc); + } + else + { + host->sdio_int = RT_TRUE; + host->mmcsd_regs->SDIOIEN |= SDIOIEN_IOINTEN; + } + } + else + { + host->sdio_int = RT_FALSE; + host->mmcsd_regs->SDIOIEN &= ~SDIOIEN_IOINTEN; + } } -static const struct rt_mmcsd_host_ops mmc_dm365_ops = +static const struct rt_mmcsd_host_ops mmc_dm365_ops = { - mmc_dm365_request, - mmc_dm365_set_ios, + mmc_dm365_request, + mmc_dm365_set_ios, RT_NULL, mmc_dm365_enable_sdio_irq }; /******************************************************************************************************* -** : mmc_dm365_reset_ctrl() -** : ˺reset mmc -** -** 䡡: host -> DM365 mmc host -** val -> жresetenable +** 函数名称: mmc_dm365_reset_ctrl() +** 功能描述: 此函数用于reset mmc控制器 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 mmc host 句柄 +** val -> 判断做reset还是enable +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void mmc_dm365_reset_ctrl(struct mmc_dm365_host *host, int val) { - rt_uint32_t temp; + rt_uint32_t temp; - temp = host->mmcsd_regs->MMCCTL; - - if (val) /* reset */ - temp |= MMCCTL_CMDRST | MMCCTL_DATRST; - else /* enable */ - temp &= ~(MMCCTL_CMDRST | MMCCTL_DATRST); + temp = host->mmcsd_regs->MMCCTL; - host->mmcsd_regs->MMCCTL = temp; + if (val) /* reset */ + temp |= MMCCTL_CMDRST | MMCCTL_DATRST; + else /* enable */ + temp &= ~(MMCCTL_CMDRST | MMCCTL_DATRST); - delay_us(10); + host->mmcsd_regs->MMCCTL = temp; + + delay_us(10); } /******************************************************************************************************* -** : init_mmcsd_host() -** : ˺ڳʼDM365 MMCSD -** -** 䡡: host -> DM365 mmc host +** 函数名称: init_mmcsd_host() +** 功能描述: 此函数用于初始化DM365 MMCSD控制器 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 mmc host 句柄 +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void init_mmcsd_host(struct mmc_dm365_host *host) { - mmc_dm365_reset_ctrl(host, 1); + mmc_dm365_reset_ctrl(host, 1); - host->mmcsd_regs->MMCCLK = 0; - host->mmcsd_regs->MMCCLK = MMCCLK_CLKEN; + host->mmcsd_regs->MMCCLK = 0; + host->mmcsd_regs->MMCCLK = MMCCLK_CLKEN; - host->mmcsd_regs->MMCTOR = 0x1FFF; - host->mmcsd_regs->MMCTOD = 0xFFFF; - - mmc_dm365_reset_ctrl(host, 0); + host->mmcsd_regs->MMCTOR = 0x1FFF; + host->mmcsd_regs->MMCTOD = 0xFFFF; + + mmc_dm365_reset_ctrl(host, 0); } /******************************************************************************************************* -** : mmc_dm365_cmd_done() -** : SD ô˺ -** -** 䡡: host -> DM365 mmc host -** cmd -> SD ṹ +** 函数名称: mmc_dm365_cmd_done() +** 功能描述: 结束SD 命令后调用此函数 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 mmc host 句柄 +** cmd -> SD 命令结构句柄 +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void mmc_dm365_cmd_done(struct mmc_dm365_host *host, struct rt_mmcsd_cmd *cmd) { - host->cmd = RT_NULL; + host->cmd = RT_NULL; - if (resp_type(cmd) != RESP_NONE) - { - if (resp_type(cmd) == RESP_R2) - { - /* response type 2 */ - cmd->resp[3] = host->mmcsd_regs->MMCRSP01; - cmd->resp[2] = host->mmcsd_regs->MMCRSP23; - cmd->resp[1] = host->mmcsd_regs->MMCRSP45; - cmd->resp[0] = host->mmcsd_regs->MMCRSP67; - } - else - { - /* response types 1, 1b, 3, 4, 5, 6 */ - cmd->resp[0] = host->mmcsd_regs->MMCRSP67; - } - } + if (resp_type(cmd) != RESP_NONE) + { + if (resp_type(cmd) == RESP_R2) + { + /* response type 2 */ + cmd->resp[3] = host->mmcsd_regs->MMCRSP01; + cmd->resp[2] = host->mmcsd_regs->MMCRSP23; + cmd->resp[1] = host->mmcsd_regs->MMCRSP45; + cmd->resp[0] = host->mmcsd_regs->MMCRSP67; + } + else + { + /* response types 1, 1b, 3, 4, 5, 6 */ + cmd->resp[0] = host->mmcsd_regs->MMCRSP67; + } + } - if (host->data == RT_NULL || cmd->err) - { - if (cmd->err == -RT_ETIMEOUT) - cmd->mrq->cmd->retries = 0; - mmc_request_done(host->mmc, cmd->mrq); - host->mmcsd_regs->MMCIM = 0; - } + if (host->data == RT_NULL || cmd->err) + { + if (cmd->err == -RT_ETIMEOUT) + cmd->mrq->cmd->retries = 0; + mmc_request_done(host->mmc, cmd->mrq); + host->mmcsd_regs->MMCIM = 0; + } } /******************************************************************************************************* -** : dm365_abort_data() -** : ˺ֹݴ -** -** 䡡: host -> DM365 mmc host -** data -> data ṹ +** 函数名称: dm365_abort_data() +** 功能描述: 此函数用于终止数据传输 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: host -> DM365 mmc host 句柄 +** data -> data 结构句柄 +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void dm365_abort_data(struct mmc_dm365_host *host, struct rt_mmcsd_data *data) { - mmc_dm365_reset_ctrl(host, 1); - mmc_dm365_reset_ctrl(host, 0); + mmc_dm365_reset_ctrl(host, 1); + mmc_dm365_reset_ctrl(host, 0); } static void mmc_dm365_sdio_irq(int irq, void *param) { - struct mmc_dm365_host *host = (struct mmc_dm365_host *)param; - rt_uint32_t status; + struct mmc_dm365_host *host = (struct mmc_dm365_host *)param; + rt_uint32_t status; - status = host->mmcsd_regs->SDIOIST;//readl(host->base + DAVINCI_SDIOIST); - if (status & SDIOIST_IOINT) { - mmc_dbg("SDIO interrupt status %x\n", status); - //writel(status | SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); - host->mmcsd_regs->SDIOIST = status | SDIOIST_IOINT; - sdio_irq_wakeup(host->mmc); - } + status = host->mmcsd_regs->SDIOIST;//readl(host->base + DAVINCI_SDIOIST); + if (status & SDIOIST_IOINT) { + mmc_dbg("SDIO interrupt status %x\n", status); + //writel(status | SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); + host->mmcsd_regs->SDIOIST = status | SDIOIST_IOINT; + sdio_irq_wakeup(host->mmc); + } } /******************************************************************************************************* -** : mmc_dm365_irq() -** : MMCSDжϴ -** -** 䡡: irq ->ж +** 函数名称: mmc_dm365_irq() +** 功能描述: MMCSD的中断处理程序 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: irq ->中断向量号 +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void mmc_dm365_irq(int irq, void *param) { - struct mmc_dm365_host *host = (struct mmc_dm365_host *)param; - rt_uint32_t status, qstatus; - int end_command = 0; - int end_transfer = 0; - struct rt_mmcsd_data *data = host->data; + struct mmc_dm365_host *host = (struct mmc_dm365_host *)param; + rt_uint32_t status, qstatus; + int end_command = 0; + int end_transfer = 0; + struct rt_mmcsd_data *data = host->data; - if (host->cmd == RT_NULL && host->data == RT_NULL) - { - status = host->mmcsd_regs->MMCST0; - mmc_dbg("Spurious interrupt 0x%04x\n", status); - /* Disable the interrupt from mmcsd */ - host->mmcsd_regs->MMCIM = 0; - return; - } + if (host->cmd == RT_NULL && host->data == RT_NULL) + { + status = host->mmcsd_regs->MMCST0; + mmc_dbg("Spurious interrupt 0x%04x\n", status); + /* Disable the interrupt from mmcsd */ + host->mmcsd_regs->MMCIM = 0; + return; + } - status = host->mmcsd_regs->MMCST0; - qstatus = status; - - /* handle FIFO first when using PIO for data. - * bytes_left will decrease to zero as I/O progress and status will - * read zero over iteration because this controller status - * register(MMCST0) reports any status only once and it is cleared - * by read. So, it is not unbouned loop even in the case of - * non-dma. - */ - while (host->bytes_left && (status & (MMCST0_DXRDY | MMCST0_DRRDY))) - { - dm365_fifo_data_trans(host, rw_threshold); - status = host->mmcsd_regs->MMCST0; - if (!status) - break; - qstatus |= status; - } + status = host->mmcsd_regs->MMCST0; + qstatus = status; - if (qstatus & MMCST0_DATDNE) - { - /* All blocks sent/received, and CRC checks passed */ - if (data != RT_NULL) - { - if ((host->do_dma == RT_FALSE) && (host->bytes_left > 0)) - { - /* if datasize < rw_threshold - * no RX ints are generated - */ - rt_kprintf("to do! host->bytes_left=0x%x\n", host->bytes_left); - dm365_fifo_data_trans(host, host->bytes_left); - } - end_transfer = 1; - data->bytes_xfered = data->blks* data->blksize; - } - else - { - mmc_dbg("DATDNE with no host->data\n"); - } - } + /* handle FIFO first when using PIO for data. + * bytes_left will decrease to zero as I/O progress and status will + * read zero over iteration because this controller status + * register(MMCST0) reports any status only once and it is cleared + * by read. So, it is not unbouned loop even in the case of + * non-dma. + */ + while (host->bytes_left && (status & (MMCST0_DXRDY | MMCST0_DRRDY))) + { + dm365_fifo_data_trans(host, rw_threshold); + status = host->mmcsd_regs->MMCST0; + if (!status) + break; + qstatus |= status; + } - if (qstatus & MMCST0_TOUTRD) - { - /* Read data timeout */ - data->err = -RT_ETIMEOUT; - end_transfer = 1; + if (qstatus & MMCST0_DATDNE) + { + /* All blocks sent/received, and CRC checks passed */ + if (data != RT_NULL) + { + if ((host->do_dma == RT_FALSE) && (host->bytes_left > 0)) + { + /* if datasize < rw_threshold + * no RX ints are generated + */ + rt_kprintf("to do! host->bytes_left=0x%x\n", host->bytes_left); + dm365_fifo_data_trans(host, host->bytes_left); + } + end_transfer = 1; + data->bytes_xfered = data->blks* data->blksize; + } + else + { + mmc_dbg("DATDNE with no host->data\n"); + } + } - mmc_dbg("read data timeout, status %x\n", qstatus); - rt_kprintf("read data timeout, status %x\n", qstatus); + if (qstatus & MMCST0_TOUTRD) + { + /* Read data timeout */ + data->err = -RT_ETIMEOUT; + end_transfer = 1; - dm365_abort_data(host, data); - } + mmc_dbg("read data timeout, status %x\n", qstatus); + rt_kprintf("read data timeout, status %x\n", qstatus); - if (qstatus & (MMCST0_CRCWR | MMCST0_CRCRD)) - { - /* Data CRC error */ - data->err = -RT_ERROR; - end_transfer = 1; + dm365_abort_data(host, data); + } - /* NOTE: this controller uses CRCWR to report both CRC - * errors and timeouts (on writes). MMCDRSP values are - * only weakly documented, but 0x9f was clearly a timeout - * case and the two three-bit patterns in various SD specs - * (101, 010) aren't part of it ... - */ - if (qstatus & MMCST0_CRCWR) - { - rt_uint32_t temp = host->mmcsd_regs->MMCDRSP; + if (qstatus & (MMCST0_CRCWR | MMCST0_CRCRD)) + { + /* Data CRC error */ + data->err = -RT_ERROR; + end_transfer = 1; - if (temp == 0x9f) - data->err = -RT_ETIMEOUT; - } - mmc_dbg("data %s %s error\n", (qstatus & MMCST0_CRCWR) ? "write" : "read", (data->err == -110) ? "timeout" : "CRC"); + /* NOTE: this controller uses CRCWR to report both CRC + * errors and timeouts (on writes). MMCDRSP values are + * only weakly documented, but 0x9f was clearly a timeout + * case and the two three-bit patterns in various SD specs + * (101, 010) aren't part of it ... + */ + if (qstatus & MMCST0_CRCWR) + { + rt_uint32_t temp = host->mmcsd_regs->MMCDRSP; - rt_kprintf("data %s %s error\n", (qstatus & MMCST0_CRCWR) ? "write" : "read", (data->err == -110) ? "timeout" : "CRC"); + if (temp == 0x9f) + data->err = -RT_ETIMEOUT; + } + mmc_dbg("data %s %s error\n", (qstatus & MMCST0_CRCWR) ? "write" : "read", (data->err == -110) ? "timeout" : "CRC"); - dm365_abort_data(host, data); - } + rt_kprintf("data %s %s error\n", (qstatus & MMCST0_CRCWR) ? "write" : "read", (data->err == -110) ? "timeout" : "CRC"); - if (qstatus & MMCST0_TOUTRS) - { - /* Command timeout */ - if (host->cmd) - { - mmc_dbg("CMD%d timeout, status %x\n", host->cmd->cmd_code, qstatus); - host->cmd->err = -RT_ETIMEOUT; - if (data) - { - end_transfer = 1; - dm365_abort_data(host, data); - } - else - end_command = 1; - } - } + dm365_abort_data(host, data); + } - if (qstatus & MMCST0_CRCRS) - { - /* Command CRC error */ - mmc_dbg("Command CRC error\n"); - if (host->cmd) - { - host->cmd->err = -RT_ERROR; - end_command = 1; - } - } + if (qstatus & MMCST0_TOUTRS) + { + /* Command timeout */ + if (host->cmd) + { + mmc_dbg("CMD%d timeout, status %x\n", host->cmd->cmd_code, qstatus); + host->cmd->err = -RT_ETIMEOUT; + if (data) + { + end_transfer = 1; + dm365_abort_data(host, data); + } + else + end_command = 1; + } + } - if (qstatus & MMCST0_RSPDNE) - { - /* End of command phase */ - end_command = (int) host->cmd; - } + if (qstatus & MMCST0_CRCRS) + { + /* Command CRC error */ + mmc_dbg("Command CRC error\n"); + if (host->cmd) + { + host->cmd->err = -RT_ERROR; + end_command = 1; + } + } - if (end_command) - mmc_dm365_cmd_done(host, host->cmd); - if (end_transfer) - mmc_dm365_xfer_done(host, data); + if (qstatus & MMCST0_RSPDNE) + { + /* End of command phase */ + end_command = (int) host->cmd; + } - return; + if (end_command) + mmc_dm365_cmd_done(host, host->cmd); + if (end_transfer) + mmc_dm365_xfer_done(host, data); + + return; } #if 0 /******************************************************************************************************* -** : rt_hw_edma_init() -** : ˺ڳʼEDMA3 -** -** 䡡: +** 函数名称: rt_hw_edma_init() +** 功能描述: 此函数用于初始化EDMA3 ** -** 䡡: -** -** ȫֱ: -** ģ: +** 输　入: 无 +** +** 输　出: 无 +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ static void rt_hw_edma_init(void) { - psc_transition(PSC0, DOMAIN0, LPSC_TPCC, PSC_ENABLE); - psc_transition(PSC0, DOMAIN0, LPSC_TPTC0, PSC_ENABLE); + psc_transition(PSC0, DOMAIN0, LPSC_TPCC, PSC_ENABLE); + psc_transition(PSC0, DOMAIN0, LPSC_TPTC0, PSC_ENABLE); - /* Initialization of EDMA3 */ + /* Initialization of EDMA3 */ edma3_init(EDMA0CC0_REG_BASE, EVT_QUEUE_NUM); - + /* Register EDMA3 Interrupts */ -// ConfigureAINTCIntEDMA3(); +// ConfigureAINTCIntEDMA3(); } #endif /******************************************************************************************************* -** : rt_hw_mmcsd_init() -** : ˺ڳʼMMCģ -** -** 䡡: +** 函数名称: rt_hw_mmcsd_init() +** 功能描述: 此函数用于初始化MMC驱动模块 ** -** 䡡: ʼɹ0ʼʧܣ-RT_ENOMEM -** -** ȫֱ: -** ģ: +** 输　入: 无 +** +** 输　出: 如果初始化成功，返回0；如果初始化失败，返回-RT_ENOMEM +** +** 全局变量: +** 调用模块: 无 ** ********************************************************************************************************/ int rt_hw_mmcsd_init(void) { - struct clk *clk; - struct mmc_dm365_host *dm365_host; - struct rt_mmcsd_host *mmc = RT_NULL; + struct clk *clk; + struct mmc_dm365_host *dm365_host; + struct rt_mmcsd_host *mmc = RT_NULL; - mmc = mmcsd_alloc_host(); - if (!mmc) - { - mmc_dbg("alloc mmc failed\n"); - return -RT_ERROR; - } + mmc = mmcsd_alloc_host(); + if (!mmc) + { + mmc_dbg("alloc mmc failed\n"); + return -RT_ERROR; + } - dm365_host = rt_malloc(sizeof(struct mmc_dm365_host)); - if (!dm365_host) - { - mmc_dbg("alloc mci failed\n"); - goto err; - } + dm365_host = rt_malloc(sizeof(struct mmc_dm365_host)); + if (!dm365_host) + { + mmc_dbg("alloc mci failed\n"); + goto err; + } - rt_memset(dm365_host, 0, sizeof(struct mmc_dm365_host)); + rt_memset(dm365_host, 0, sizeof(struct mmc_dm365_host)); #ifdef RT_USING_MMCSD0 - //psc_transition(PSC0, DOMAIN0, LPSC_MMCSD0, PSC_ENABLE); - //pinmux_config(PINMUX_MMCSD0_REG, PINMUX_MMCSD0_MASK, PINMUX_MMCSD0_VAL); - psc_change_state(DAVINCI_DM365_LPSC_MMC_SD0, PSC_ENABLE); - dm365_host->mmcsd_regs = (mmcsd_regs_t *)DM365_MMC_SD0_BASE; + //psc_transition(PSC0, DOMAIN0, LPSC_MMCSD0, PSC_ENABLE); + //pinmux_config(PINMUX_MMCSD0_REG, PINMUX_MMCSD0_MASK, PINMUX_MMCSD0_VAL); + psc_change_state(DAVINCI_DM365_LPSC_MMC_SD0, PSC_ENABLE); + dm365_host->mmcsd_regs = (mmcsd_regs_t *)DM365_MMC_SD0_BASE; #else #ifdef RT_USING_MMCSD1 - psc_transition(PSC1, DOMAIN0, LPSC_MMCSD1, PSC_ENABLE); - pinmux_config(PINMUX_MMCSD1_REG, PINMUX_MMCSD1_MASK, PINMUX_MMCSD1_VAL); - dm365_host->mmcsd_regs = MMCSD1; + psc_transition(PSC1, DOMAIN0, LPSC_MMCSD1, PSC_ENABLE); + pinmux_config(PINMUX_MMCSD1_REG, PINMUX_MMCSD1_MASK, PINMUX_MMCSD1_VAL); + dm365_host->mmcsd_regs = MMCSD1; #endif #endif - //rt_hw_edma_init(); + //rt_hw_edma_init(); - clk = clk_get("MMCSDCLK0"); - dm365_host->mmc_input_clk = clk_get_rate(clk); - dm365_host->rxdma = DM365_DMA_MMC0RXEVT; - dm365_host->txdma = DM365_DMA_MMC0TXEVT; - dm365_host->use_dma = use_dma; - if ((dm365_host->use_dma == RT_TRUE)&& acquire_dma_channels(dm365_host) != 0) - { - dm365_host->use_dma = RT_FALSE; - } - else - { - dm365_host->dma_buffer = (rt_uint8_t*)rt_malloc_align(64*1024, 32); - if (dm365_host->dma_buffer == RT_NULL) - dm365_host->use_dma = RT_FALSE; - } + clk = clk_get("MMCSDCLK0"); + dm365_host->mmc_input_clk = clk_get_rate(clk); + dm365_host->rxdma = DM365_DMA_MMC0RXEVT; + dm365_host->txdma = DM365_DMA_MMC0TXEVT; + dm365_host->use_dma = use_dma; + if ((dm365_host->use_dma == RT_TRUE)&& acquire_dma_channels(dm365_host) != 0) + { + dm365_host->use_dma = RT_FALSE; + } + else + { + dm365_host->dma_buffer = (rt_uint8_t*)rt_malloc_align(64*1024, 32); + if (dm365_host->dma_buffer == RT_NULL) + dm365_host->use_dma = RT_FALSE; + } - mmc->ops = &mmc_dm365_ops; - mmc->freq_min = 312500; - mmc->freq_max = 25000000; - mmc->valid_ocr = VDD_32_33 | VDD_33_34; - mmc->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE; - mmc->flags |= MMCSD_SUP_SDIO_IRQ; + mmc->ops = &mmc_dm365_ops; + mmc->freq_min = 312500; + mmc->freq_max = 25000000; + mmc->valid_ocr = VDD_32_33 | VDD_33_34; + mmc->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE; + mmc->flags |= MMCSD_SUP_SDIO_IRQ; - dm365_host->mmc = mmc; - mmc->private_data = dm365_host; + dm365_host->mmc = mmc; + mmc->private_data = dm365_host; - /* install interrupt */ + /* install interrupt */ #ifdef RT_USING_MMCSD0 - rt_hw_interrupt_install(IRQ_DM3XX_MMCINT0, mmc_dm365_irq, - (void *)dm365_host, "MMC0"); - rt_hw_interrupt_umask(IRQ_DM3XX_MMCINT0); - rt_hw_interrupt_install(IRQ_DM3XX_SDIOINT0, mmc_dm365_sdio_irq, - (void *)dm365_host, "SDIO0"); - rt_hw_interrupt_umask(IRQ_DM3XX_SDIOINT0); + rt_hw_interrupt_install(IRQ_DM3XX_MMCINT0, mmc_dm365_irq, + (void *)dm365_host, "MMC0"); + rt_hw_interrupt_umask(IRQ_DM3XX_MMCINT0); + rt_hw_interrupt_install(IRQ_DM3XX_SDIOINT0, mmc_dm365_sdio_irq, + (void *)dm365_host, "SDIO0"); + rt_hw_interrupt_umask(IRQ_DM3XX_SDIOINT0); #endif #ifdef RT_USING_MMCSD1 - rt_hw_interrupt_install(MMCSD_INT1, mmc_dm365_irq, - (void *)dm365_host, "MMC1"); - rt_hw_interrupt_umask(MMCSD_INT1); + rt_hw_interrupt_install(MMCSD_INT1, mmc_dm365_irq, + (void *)dm365_host, "MMC1"); + rt_hw_interrupt_umask(MMCSD_INT1); #endif - init_mmcsd_host(dm365_host); + init_mmcsd_host(dm365_host); - mmcsd_change(mmc); + mmcsd_change(mmc); - return 0; + return 0; err: - mmcsd_free_host(mmc); + mmcsd_free_host(mmc); - return -RT_ENOMEM; + return -RT_ENOMEM; } INIT_DEVICE_EXPORT(rt_hw_mmcsd_init); diff --git a/bsp/dm365/drivers/mmcsd.h b/bsp/dm365/drivers/mmcsd.h index 71fb93649d..812b44a72e 100644 --- a/bsp/dm365/drivers/mmcsd.h +++ b/bsp/dm365/drivers/mmcsd.h @@ -1,25 +1,11 @@ /* - * File : mmcsd.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ #ifndef __DAVINCI_MMC_H__ @@ -44,18 +30,18 @@ #define MMCCLK_CLKRT_MASK (0xFF << 0) /* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */ -#define MMCST0_DATDNE (1 << 0) /* data done */ -#define MMCST0_BSYDNE (1 << 1) /* busy done */ -#define MMCST0_RSPDNE (1 << 2) /* command done */ -#define MMCST0_TOUTRD (1 << 3) /* data read timeout */ -#define MMCST0_TOUTRS (1 << 4) /* command response timeout */ -#define MMCST0_CRCWR (1 << 5) /* data write CRC error */ -#define MMCST0_CRCRD (1 << 6) /* data read CRC error */ -#define MMCST0_CRCRS (1 << 7) /* command response CRC error */ -#define MMCST0_DXRDY (1 << 9) /* data transmit ready (fifo empty) */ -#define MMCST0_DRRDY (1 << 10) /* data receive ready (data in fifo)*/ -#define MMCST0_DATED (1 << 11) /* DAT3 edge detect */ -#define MMCST0_TRNDNE (1 << 12) /* transfer done */ +#define MMCST0_DATDNE (1 << 0) /* data done */ +#define MMCST0_BSYDNE (1 << 1) /* busy done */ +#define MMCST0_RSPDNE (1 << 2) /* command done */ +#define MMCST0_TOUTRD (1 << 3) /* data read timeout */ +#define MMCST0_TOUTRS (1 << 4) /* command response timeout */ +#define MMCST0_CRCWR (1 << 5) /* data write CRC error */ +#define MMCST0_CRCRD (1 << 6) /* data read CRC error */ +#define MMCST0_CRCRS (1 << 7) /* command response CRC error */ +#define MMCST0_DXRDY (1 << 9) /* data transmit ready (fifo empty) */ +#define MMCST0_DRRDY (1 << 10) /* data receive ready (data in fifo)*/ +#define MMCST0_DATED (1 << 11) /* DAT3 edge detect */ +#define MMCST0_TRNDNE (1 << 12) /* transfer done */ /* DAVINCI_MMCST1 definitions */ #define MMCST1_BUSY (1 << 0) @@ -100,44 +86,44 @@ #define SDIOIST_RWS (1 << 1) /* MMCSD Init clock in Hz in opendrain mode */ -#define MMCSD_INIT_CLOCK 200000 +#define MMCSD_INIT_CLOCK 200000 -#define MAX_CCNT ((1 << 16) - 1) +#define MAX_CCNT ((1 << 16) - 1) -#define MAX_NR_SG 16 +#define MAX_NR_SG 16 -#define MMC_DATA_WRITE (1 << 8) -#define MMC_DATA_READ (1 << 9) -#define MMC_DATA_STREAM (1 << 10) +#define MMC_DATA_WRITE (1 << 8) +#define MMC_DATA_READ (1 << 9) +#define MMC_DATA_STREAM (1 << 10) typedef struct { - volatile rt_uint32_t MMCCTL; - volatile rt_uint32_t MMCCLK; - volatile rt_uint32_t MMCST0; - volatile rt_uint32_t MMCST1; - volatile rt_uint32_t MMCIM; - volatile rt_uint32_t MMCTOR; - volatile rt_uint32_t MMCTOD; - volatile rt_uint32_t MMCBLEN; - volatile rt_uint32_t MMCNBLK; - volatile rt_uint32_t MMCNBLC; - volatile rt_uint32_t MMCDRR; - volatile rt_uint32_t MMCDXR; - volatile rt_uint32_t MMCCMD; - volatile rt_uint32_t MMCARGHL; - volatile rt_uint32_t MMCRSP01; - volatile rt_uint32_t MMCRSP23; - volatile rt_uint32_t MMCRSP45; - volatile rt_uint32_t MMCRSP67; - volatile rt_uint32_t MMCDRSP; - volatile rt_uint32_t reserved0; - volatile rt_uint32_t MMCCIDX; - volatile rt_uint32_t reserved1[4]; - volatile rt_uint32_t SDIOCTL; - volatile rt_uint32_t SDIOST0; - volatile rt_uint32_t SDIOIEN; - volatile rt_uint32_t SDIOIST; - volatile rt_uint32_t MMCFIFOCTL; + volatile rt_uint32_t MMCCTL; + volatile rt_uint32_t MMCCLK; + volatile rt_uint32_t MMCST0; + volatile rt_uint32_t MMCST1; + volatile rt_uint32_t MMCIM; + volatile rt_uint32_t MMCTOR; + volatile rt_uint32_t MMCTOD; + volatile rt_uint32_t MMCBLEN; + volatile rt_uint32_t MMCNBLK; + volatile rt_uint32_t MMCNBLC; + volatile rt_uint32_t MMCDRR; + volatile rt_uint32_t MMCDXR; + volatile rt_uint32_t MMCCMD; + volatile rt_uint32_t MMCARGHL; + volatile rt_uint32_t MMCRSP01; + volatile rt_uint32_t MMCRSP23; + volatile rt_uint32_t MMCRSP45; + volatile rt_uint32_t MMCRSP67; + volatile rt_uint32_t MMCDRSP; + volatile rt_uint32_t reserved0; + volatile rt_uint32_t MMCCIDX; + volatile rt_uint32_t reserved1[4]; + volatile rt_uint32_t SDIOCTL; + volatile rt_uint32_t SDIOST0; + volatile rt_uint32_t SDIOIEN; + volatile rt_uint32_t SDIOIST; + volatile rt_uint32_t MMCFIFOCTL; }mmcsd_regs_t; extern int rt_hw_mmcsd_init(void); diff --git a/bsp/dm365/drivers/spi-davinci.c b/bsp/dm365/drivers/spi-davinci.c index fb5d9729d4..35de558e14 100644 --- a/bsp/dm365/drivers/spi-davinci.c +++ b/bsp/dm365/drivers/spi-davinci.c @@ -1,25 +1,11 @@ /* - * File : spi-davinci.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ #include @@ -34,13 +20,13 @@ #define barrier() __asm__ __volatile__("": : :"memory") #define cpu_relax() barrier() -#define SPI_DEBUG 0 +#define SPI_DEBUG 0 #if SPI_DEBUG #define spi_dbg(dev, fmt, ...) \ - do { \ - rt_kprintf("%s:", dev->parent.name); \ - rt_kprintf(fmt, ##__VA_ARGS__); \ - } while(0) + do { \ + rt_kprintf("%s:", dev->parent.name); \ + rt_kprintf(fmt, ##__VA_ARGS__); \ + } while(0) #else #define spi_dbg(dev, fmt, ...) #endif @@ -48,50 +34,50 @@ #define SZ_64K 0x10000 #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) -#define SPI_NO_RESOURCE ((resource_size_t)-1) +#define SPI_NO_RESOURCE ((resource_size_t)-1) -#define SPI_MAX_CHIPSELECT 2 +#define SPI_MAX_CHIPSELECT 2 -#define CS_DEFAULT 0xFF +#define CS_DEFAULT 0xFF #define __iomem -#define BIT(nr) (1UL << (nr)) +#define BIT(nr) (1UL << (nr)) -#define SPIFMT_PHASE_MASK BIT(16) -#define SPIFMT_POLARITY_MASK BIT(17) -#define SPIFMT_DISTIMER_MASK BIT(18) -#define SPIFMT_SHIFTDIR_MASK BIT(20) -#define SPIFMT_WAITENA_MASK BIT(21) -#define SPIFMT_PARITYENA_MASK BIT(22) -#define SPIFMT_ODD_PARITY_MASK BIT(23) -#define SPIFMT_WDELAY_MASK 0x3f000000u -#define SPIFMT_WDELAY_SHIFT 24 -#define SPIFMT_PRESCALE_SHIFT 8 +#define SPIFMT_PHASE_MASK BIT(16) +#define SPIFMT_POLARITY_MASK BIT(17) +#define SPIFMT_DISTIMER_MASK BIT(18) +#define SPIFMT_SHIFTDIR_MASK BIT(20) +#define SPIFMT_WAITENA_MASK BIT(21) +#define SPIFMT_PARITYENA_MASK BIT(22) +#define SPIFMT_ODD_PARITY_MASK BIT(23) +#define SPIFMT_WDELAY_MASK 0x3f000000u +#define SPIFMT_WDELAY_SHIFT 24 +#define SPIFMT_PRESCALE_SHIFT 8 /* SPIPC0 */ -#define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ -#define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ -#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ -#define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ +#define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ +#define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ +#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ +#define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ -#define SPIINT_MASKALL 0x0101035F -#define SPIINT_MASKINT 0x0000015F -#define SPI_INTLVL_1 0x000001FF -#define SPI_INTLVL_0 0x00000000 +#define SPIINT_MASKALL 0x0101035F +#define SPIINT_MASKINT 0x0000015F +#define SPI_INTLVL_1 0x000001FF +#define SPI_INTLVL_0 0x00000000 /* SPIDAT1 (upper 16 bit defines) */ -#define SPIDAT1_CSHOLD_MASK BIT(12) +#define SPIDAT1_CSHOLD_MASK BIT(12) /* SPIGCR1 */ -#define SPIGCR1_CLKMOD_MASK BIT(1) +#define SPIGCR1_CLKMOD_MASK BIT(1) #define SPIGCR1_MASTER_MASK BIT(0) -#define SPIGCR1_POWERDOWN_MASK BIT(8) -#define SPIGCR1_LOOPBACK_MASK BIT(16) -#define SPIGCR1_SPIENA_MASK BIT(24) +#define SPIGCR1_POWERDOWN_MASK BIT(8) +#define SPIGCR1_LOOPBACK_MASK BIT(16) +#define SPIGCR1_SPIENA_MASK BIT(24) /* SPIBUF */ -#define SPIBUF_TXFULL_MASK BIT(29) -#define SPIBUF_RXEMPTY_MASK BIT(31) +#define SPIBUF_TXFULL_MASK BIT(29) +#define SPIBUF_RXEMPTY_MASK BIT(31) /* SPIDELAY */ #define SPIDELAY_C2TDELAY_SHIFT 24 @@ -104,67 +90,67 @@ #define SPIDELAY_C2EDELAY_MASK 0xFF /* Error Masks */ -#define SPIFLG_DLEN_ERR_MASK BIT(0) -#define SPIFLG_TIMEOUT_MASK BIT(1) -#define SPIFLG_PARERR_MASK BIT(2) -#define SPIFLG_DESYNC_MASK BIT(3) -#define SPIFLG_BITERR_MASK BIT(4) -#define SPIFLG_OVRRUN_MASK BIT(6) -#define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) -#define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ - | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ - | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ - | SPIFLG_OVRRUN_MASK) +#define SPIFLG_DLEN_ERR_MASK BIT(0) +#define SPIFLG_TIMEOUT_MASK BIT(1) +#define SPIFLG_PARERR_MASK BIT(2) +#define SPIFLG_DESYNC_MASK BIT(3) +#define SPIFLG_BITERR_MASK BIT(4) +#define SPIFLG_OVRRUN_MASK BIT(6) +#define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) +#define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ + | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ + | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ + | SPIFLG_OVRRUN_MASK) -#define SPIINT_DMA_REQ_EN BIT(16) +#define SPIINT_DMA_REQ_EN BIT(16) /* SPI Controller registers */ -#define SPIGCR0 0x00 -#define SPIGCR1 0x04 -#define SPIINT 0x08 -#define SPILVL 0x0c -#define SPIFLG 0x10 -#define SPIPC0 0x14 -#define SPIDAT1 0x3c -#define SPIBUF 0x40 -#define SPIDELAY 0x48 -#define SPIDEF 0x4c -#define SPIFMT0 0x50 +#define SPIGCR0 0x00 +#define SPIGCR1 0x04 +#define SPIINT 0x08 +#define SPILVL 0x0c +#define SPIFLG 0x10 +#define SPIPC0 0x14 +#define SPIDAT1 0x3c +#define SPIBUF 0x40 +#define SPIDELAY 0x48 +#define SPIDEF 0x4c +#define SPIFMT0 0x50 /* We have 2 DMA channels per CS, one for RX and one for TX */ struct davinci_spi_dma { - int tx_channel; - int rx_channel; - int dummy_param_slot; - enum dma_event_q eventq; + int tx_channel; + int rx_channel; + int dummy_param_slot; + enum dma_event_q eventq; }; /* SPI Controller driver's private data. */ struct davinci_spi { - struct rt_spi_bus parent; - struct clk *clk; + struct rt_spi_bus parent; + struct clk *clk; - u8 version; - void __iomem *base; - u32 irq; - struct rt_completion done; + u8 version; + void __iomem *base; + u32 irq; + struct rt_completion done; - const void *tx; - void *rx; + const void *tx; + void *rx; #define SMP_CACHE_BYTES 32 -#define SPI_TMP_BUFSZ (SMP_CACHE_BYTES + 1) - u8 rx_tmp_buf[SPI_TMP_BUFSZ]; - int rcount; - int wcount; - struct davinci_spi_dma dma; +#define SPI_TMP_BUFSZ (SMP_CACHE_BYTES + 1) + u8 rx_tmp_buf[SPI_TMP_BUFSZ]; + int rcount; + int wcount; + struct davinci_spi_dma dma; - void (*get_rx)(u32 rx_data, struct davinci_spi *); - u32 (*get_tx)(struct davinci_spi *); + void (*get_rx)(u32 rx_data, struct davinci_spi *); + u32 (*get_tx)(struct davinci_spi *); - u8 bytes_per_word[SPI_MAX_CHIPSELECT]; - u8 chip_sel[SPI_MAX_CHIPSELECT]; - struct davinci_spi_config *controller_data; - int cshold_bug; + u8 bytes_per_word[SPI_MAX_CHIPSELECT]; + u8 chip_sel[SPI_MAX_CHIPSELECT]; + struct davinci_spi_config *controller_data; + int cshold_bug; }; static struct davinci_spi_config davinci_spi_default_cfg; @@ -174,58 +160,58 @@ extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi) { - if (dspi->rx) { - u8 *rx = dspi->rx; - *rx++ = (u8)data; - dspi->rx = rx; - } + if (dspi->rx) { + u8 *rx = dspi->rx; + *rx++ = (u8)data; + dspi->rx = rx; + } } static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi) { - if (dspi->rx) { - u16 *rx = dspi->rx; - *rx++ = (u16)data; - dspi->rx = rx; - } + if (dspi->rx) { + u16 *rx = dspi->rx; + *rx++ = (u16)data; + dspi->rx = rx; + } } static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi) { - u32 data = 0; - if (dspi->tx) { - const u8 *tx = dspi->tx; - data = *tx++; - dspi->tx = tx; - } - return data; + u32 data = 0; + if (dspi->tx) { + const u8 *tx = dspi->tx; + data = *tx++; + dspi->tx = tx; + } + return data; } static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi) { - u32 data = 0; - if (dspi->tx) { - const u16 *tx = dspi->tx; - data = *tx++; - dspi->tx = tx; - } - return data; + u32 data = 0; + if (dspi->tx) { + const u16 *tx = dspi->tx; + data = *tx++; + dspi->tx = tx; + } + return data; } static inline void set_io_bits(void __iomem *addr, u32 bits) { - u32 v = readl(addr); + u32 v = readl(addr); - v |= bits; - writel(v, addr); + v |= bits; + writel(v, addr); } static inline void clear_io_bits(void __iomem *addr, u32 bits) { - u32 v = readl(addr); + u32 v = readl(addr); - v &= ~bits; - writel(v, addr); + v &= ~bits; + writel(v, addr); } /* @@ -233,39 +219,39 @@ static inline void clear_io_bits(void __iomem *addr, u32 bits) */ static void davinci_spi_chipselect(struct rt_spi_device *spi, int value) { - struct davinci_spi *dspi; - u8 chip_sel = (u8)spi->parent.user_data; - u16 spidat1 = CS_DEFAULT; - bool gpio_chipsel = RT_FALSE; + struct davinci_spi *dspi; + u8 chip_sel = (u8)spi->parent.user_data; + u16 spidat1 = CS_DEFAULT; + bool gpio_chipsel = RT_FALSE; - dspi = spi->bus->parent.user_data; + dspi = spi->bus->parent.user_data; - if (chip_sel < SPI_MAX_CHIPSELECT && - dspi->chip_sel[chip_sel] != SPI_INTERN_CS) - gpio_chipsel = RT_TRUE; + if (chip_sel < SPI_MAX_CHIPSELECT && + dspi->chip_sel[chip_sel] != SPI_INTERN_CS) + gpio_chipsel = RT_TRUE; - /* - * Board specific chip select logic decides the polarity and cs - * line for the controller - */ - if (gpio_chipsel) { - if (value == 0) - gpio_set_value(dspi->chip_sel[chip_sel], 0); - else - gpio_set_value(dspi->chip_sel[chip_sel], 1); - } else { - spidat1 = readw(dspi->base + SPIDAT1 + 2); - if (value == 0) { - spidat1 |= SPIDAT1_CSHOLD_MASK; - spidat1 &= ~(0x1 << chip_sel); - } else { - spidat1 &= ~SPIDAT1_CSHOLD_MASK; - spidat1 |= 0x03; - } - rt_kprintf("0x%04x\n", spidat1); + /* + * Board specific chip select logic decides the polarity and cs + * line for the controller + */ + if (gpio_chipsel) { + if (value == 0) + gpio_set_value(dspi->chip_sel[chip_sel], 0); + else + gpio_set_value(dspi->chip_sel[chip_sel], 1); + } else { + spidat1 = readw(dspi->base + SPIDAT1 + 2); + if (value == 0) { + spidat1 |= SPIDAT1_CSHOLD_MASK; + spidat1 &= ~(0x1 << chip_sel); + } else { + spidat1 &= ~SPIDAT1_CSHOLD_MASK; + spidat1 |= 0x03; + } + rt_kprintf("0x%04x\n", spidat1); - writew(spidat1, dspi->base + SPIDAT1 + 2); - } + writew(spidat1, dspi->base + SPIDAT1 + 2); + } } /** @@ -279,25 +265,25 @@ static void davinci_spi_chipselect(struct rt_spi_device *spi, int value) * or negative error number if valid prescalar cannot be updated. */ static inline int davinci_spi_get_prescale(struct davinci_spi *dspi, - u32 max_speed_hz) + u32 max_speed_hz) { - int ret; + int ret; - ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz); + ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz); - if (ret < 3) { - rt_kprintf("spi clock freq too high\n"); - ret = 3; - } - if (ret > 256) { - rt_kprintf("spi clock freq too litter\n"); - ret = 256; - } + if (ret < 3) { + rt_kprintf("spi clock freq too high\n"); + ret = 3; + } + if (ret > 256) { + rt_kprintf("spi clock freq too litter\n"); + ret = 256; + } - /*if (ret < 3 || ret > 256) - return -RT_ERROR;*/ + /*if (ret < 3 || ret > 256) + return -RT_ERROR;*/ - return ret - 1; + return ret - 1; } /** @@ -310,104 +296,104 @@ static inline int davinci_spi_get_prescale(struct davinci_spi *dspi, * SPI slave device freq. */ static int davinci_spi_setup_transfer(struct rt_spi_device *spi, - struct rt_spi_configuration *cfg) + struct rt_spi_configuration *cfg) { - struct davinci_spi *dspi; - struct davinci_spi_config *spicfg; - u8 bits_per_word = 0; - u32 hz = 0, spifmt = 0, prescale = 0; - u8 chip_select = (u8)spi->parent.user_data; + struct davinci_spi *dspi; + struct davinci_spi_config *spicfg; + u8 bits_per_word = 0; + u32 hz = 0, spifmt = 0, prescale = 0; + u8 chip_select = (u8)spi->parent.user_data; - dspi = spi->bus->parent.user_data; - spicfg = (struct davinci_spi_config *)dspi->controller_data; - if (!spicfg) - spicfg = &davinci_spi_default_cfg; + dspi = spi->bus->parent.user_data; + spicfg = (struct davinci_spi_config *)dspi->controller_data; + if (!spicfg) + spicfg = &davinci_spi_default_cfg; - bits_per_word = cfg->data_width; - hz = cfg->max_hz; + bits_per_word = cfg->data_width; + hz = cfg->max_hz; - /* - * Assign function pointer to appropriate transfer method - * 8bit, 16bit or 32bit transfer - */ - if (bits_per_word <= 8 && bits_per_word >= 2) { - dspi->get_rx = davinci_spi_rx_buf_u8; - dspi->get_tx = davinci_spi_tx_buf_u8; - dspi->bytes_per_word[chip_select] = 1; - } else if (bits_per_word <= 16 && bits_per_word >= 2) { - dspi->get_rx = davinci_spi_rx_buf_u16; - dspi->get_tx = davinci_spi_tx_buf_u16; - dspi->bytes_per_word[chip_select] = 2; - } else - return -RT_ERROR; + /* + * Assign function pointer to appropriate transfer method + * 8bit, 16bit or 32bit transfer + */ + if (bits_per_word <= 8 && bits_per_word >= 2) { + dspi->get_rx = davinci_spi_rx_buf_u8; + dspi->get_tx = davinci_spi_tx_buf_u8; + dspi->bytes_per_word[chip_select] = 1; + } else if (bits_per_word <= 16 && bits_per_word >= 2) { + dspi->get_rx = davinci_spi_rx_buf_u16; + dspi->get_tx = davinci_spi_tx_buf_u16; + dspi->bytes_per_word[chip_select] = 2; + } else + return -RT_ERROR; - /* Set up SPIFMTn register, unique to this chipselect. */ + /* Set up SPIFMTn register, unique to this chipselect. */ - prescale = davinci_spi_get_prescale(dspi, hz); - if (prescale < 0) - return prescale; + prescale = davinci_spi_get_prescale(dspi, hz); + if (prescale < 0) + return prescale; - spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f); + spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f); - if (!(cfg->mode & RT_SPI_MSB)) - spifmt |= SPIFMT_SHIFTDIR_MASK; + if (!(cfg->mode & RT_SPI_MSB)) + spifmt |= SPIFMT_SHIFTDIR_MASK; - if (cfg->mode & RT_SPI_CPOL) - spifmt |= SPIFMT_POLARITY_MASK; + if (cfg->mode & RT_SPI_CPOL) + spifmt |= SPIFMT_POLARITY_MASK; - if (!(cfg->mode & RT_SPI_CPHA)) - spifmt |= SPIFMT_PHASE_MASK; + if (!(cfg->mode & RT_SPI_CPHA)) + spifmt |= SPIFMT_PHASE_MASK; - /* - * Version 1 hardware supports two basic SPI modes: - * - Standard SPI mode uses 4 pins, with chipselect - * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) - * (distinct from SPI_3WIRE, with just one data wire; - * or similar variants without MOSI or without MISO) - * - * Version 2 hardware supports an optional handshaking signal, - * so it can support two more modes: - * - 5 pin SPI variant is standard SPI plus SPI_READY - * - 4 pin with enable is (SPI_READY | SPI_NO_CS) - */ + /* + * Version 1 hardware supports two basic SPI modes: + * - Standard SPI mode uses 4 pins, with chipselect + * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) + * (distinct from SPI_3WIRE, with just one data wire; + * or similar variants without MOSI or without MISO) + * + * Version 2 hardware supports an optional handshaking signal, + * so it can support two more modes: + * - 5 pin SPI variant is standard SPI plus SPI_READY + * - 4 pin with enable is (SPI_READY | SPI_NO_CS) + */ - if (dspi->version == SPI_VERSION_2) { + if (dspi->version == SPI_VERSION_2) { - u32 delay = 0; + u32 delay = 0; - spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT) - & SPIFMT_WDELAY_MASK); + spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT) + & SPIFMT_WDELAY_MASK); - if (spicfg->odd_parity) - spifmt |= SPIFMT_ODD_PARITY_MASK; + if (spicfg->odd_parity) + spifmt |= SPIFMT_ODD_PARITY_MASK; - if (spicfg->parity_enable) - spifmt |= SPIFMT_PARITYENA_MASK; + if (spicfg->parity_enable) + spifmt |= SPIFMT_PARITYENA_MASK; - if (spicfg->timer_disable) { - spifmt |= SPIFMT_DISTIMER_MASK; - } else { - delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT) - & SPIDELAY_C2TDELAY_MASK; - delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT) - & SPIDELAY_T2CDELAY_MASK; - } + if (spicfg->timer_disable) { + spifmt |= SPIFMT_DISTIMER_MASK; + } else { + delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT) + & SPIDELAY_C2TDELAY_MASK; + delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT) + & SPIDELAY_T2CDELAY_MASK; + } - if (cfg->mode & RT_SPI_READY) { - spifmt |= SPIFMT_WAITENA_MASK; - delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT) - & SPIDELAY_T2EDELAY_MASK; - delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT) - & SPIDELAY_C2EDELAY_MASK; - } + if (cfg->mode & RT_SPI_READY) { + spifmt |= SPIFMT_WAITENA_MASK; + delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT) + & SPIDELAY_T2EDELAY_MASK; + delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT) + & SPIDELAY_C2EDELAY_MASK; + } - writel(delay, dspi->base + SPIDELAY); - } + writel(delay, dspi->base + SPIDELAY); + } - writel(spifmt, dspi->base + SPIFMT0); + writel(spifmt, dspi->base + SPIFMT0); - return 0; + return 0; } #if 0 @@ -419,73 +405,73 @@ static int davinci_spi_setup_transfer(struct rt_spi_device *spi, */ static int davinci_spi_setup(struct spi_device *spi) { - int retval = 0; - struct davinci_spi *dspi; - struct davinci_spi_platform_data *pdata; + int retval = 0; + struct davinci_spi *dspi; + struct davinci_spi_platform_data *pdata; - dspi = spi_master_get_devdata(spi->master); - pdata = dspi->pdata; + dspi = spi_master_get_devdata(spi->master); + pdata = dspi->pdata; - /* if bits per word length is zero then set it default 8 */ - if (!spi->bits_per_word) - spi->bits_per_word = 8; + /* if bits per word length is zero then set it default 8 */ + if (!spi->bits_per_word) + spi->bits_per_word = 8; - if (!(spi->mode & SPI_NO_CS)) { - if ((pdata->chip_sel == NULL) || - (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS)) - set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select); + if (!(spi->mode & SPI_NO_CS)) { + if ((pdata->chip_sel == NULL) || + (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS)) + set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select); - } + } - if (spi->mode & SPI_READY) - set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK); + if (spi->mode & SPI_READY) + set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK); - if (spi->mode & SPI_LOOP) - set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); - else - clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); + if (spi->mode & SPI_LOOP) + set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); + else + clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK); - return retval; + return retval; } #endif static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status) { - struct rt_device *sdev = &dspi->parent.parent; + struct rt_device *sdev = &dspi->parent.parent; - if (int_status & SPIFLG_TIMEOUT_MASK) { - spi_dbg(sdev, "SPI Time-out Error\n"); - return -RT_ETIMEOUT; - } - if (int_status & SPIFLG_DESYNC_MASK) { - spi_dbg(sdev, "SPI Desynchronization Error\n"); - return -RT_EIO; - } - if (int_status & SPIFLG_BITERR_MASK) { - spi_dbg(sdev, "SPI Bit error\n"); - return -RT_EIO; - } + if (int_status & SPIFLG_TIMEOUT_MASK) { + spi_dbg(sdev, "SPI Time-out Error\n"); + return -RT_ETIMEOUT; + } + if (int_status & SPIFLG_DESYNC_MASK) { + spi_dbg(sdev, "SPI Desynchronization Error\n"); + return -RT_EIO; + } + if (int_status & SPIFLG_BITERR_MASK) { + spi_dbg(sdev, "SPI Bit error\n"); + return -RT_EIO; + } - if (dspi->version == SPI_VERSION_2) { - if (int_status & SPIFLG_DLEN_ERR_MASK) { - spi_dbg(sdev, "SPI Data Length Error\n"); - return -RT_EIO; - } - if (int_status & SPIFLG_PARERR_MASK) { - spi_dbg(sdev, "SPI Parity Error\n"); - return -RT_EIO; - } - if (int_status & SPIFLG_OVRRUN_MASK) { - spi_dbg(sdev, "SPI Data Overrun error\n"); - return -RT_EIO; - } - if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) { - spi_dbg(sdev, "SPI Buffer Init Active\n"); - return -RT_EBUSY; - } - } + if (dspi->version == SPI_VERSION_2) { + if (int_status & SPIFLG_DLEN_ERR_MASK) { + spi_dbg(sdev, "SPI Data Length Error\n"); + return -RT_EIO; + } + if (int_status & SPIFLG_PARERR_MASK) { + spi_dbg(sdev, "SPI Parity Error\n"); + return -RT_EIO; + } + if (int_status & SPIFLG_OVRRUN_MASK) { + spi_dbg(sdev, "SPI Data Overrun error\n"); + return -RT_EIO; + } + if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) { + spi_dbg(sdev, "SPI Buffer Init Active\n"); + return -RT_EBUSY; + } + } - return 0; + return 0; } /** @@ -497,50 +483,50 @@ static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status) */ static int davinci_spi_process_events(struct davinci_spi *dspi) { - u32 buf, status, errors = 0, spidat1; + u32 buf, status, errors = 0, spidat1; - buf = readl(dspi->base + SPIBUF); + buf = readl(dspi->base + SPIBUF); - if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) { - dspi->get_rx(buf & 0xFFFF, dspi); - dspi->rcount--; - } + if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) { + dspi->get_rx(buf & 0xFFFF, dspi); + dspi->rcount--; + } - status = readl(dspi->base + SPIFLG); + status = readl(dspi->base + SPIFLG); - if (unlikely(status & SPIFLG_ERROR_MASK)) { - errors = status & SPIFLG_ERROR_MASK; - goto out; - } + if (unlikely(status & SPIFLG_ERROR_MASK)) { + errors = status & SPIFLG_ERROR_MASK; + goto out; + } - if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) { - spidat1 = readl(dspi->base + SPIDAT1); - dspi->wcount--; - spidat1 &= ~0xFFFF; - spidat1 |= 0xFFFF & dspi->get_tx(dspi); - writel(spidat1, dspi->base + SPIDAT1); - } + if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) { + spidat1 = readl(dspi->base + SPIDAT1); + dspi->wcount--; + spidat1 &= ~0xFFFF; + spidat1 |= 0xFFFF & dspi->get_tx(dspi); + writel(spidat1, dspi->base + SPIDAT1); + } out: - return errors; + return errors; } static void davinci_spi_dma_callback(unsigned lch, u16 status, void *data) { - struct davinci_spi *dspi = data; - struct davinci_spi_dma *dma = &dspi->dma; + struct davinci_spi *dspi = data; + struct davinci_spi_dma *dma = &dspi->dma; - edma_stop(lch); + edma_stop(lch); - if (status == DMA_COMPLETE) { - if (lch == dma->rx_channel) - dspi->rcount = 0; - if (lch == dma->tx_channel) - dspi->wcount = 0; - } + if (status == DMA_COMPLETE) { + if (lch == dma->rx_channel) + dspi->rcount = 0; + if (lch == dma->tx_channel) + dspi->wcount = 0; + } - if ((!dspi->wcount && !dspi->rcount) || (status != DMA_COMPLETE)) - rt_completion_done(&dspi->done); + if ((!dspi->wcount && !dspi->rcount) || (status != DMA_COMPLETE)) + rt_completion_done(&dspi->done); } /** @@ -554,186 +540,186 @@ static void davinci_spi_dma_callback(unsigned lch, u16 status, void *data) */ static int davinci_spi_bufs(struct rt_spi_device *spi, struct rt_spi_message *msg) { - struct davinci_spi *dspi; - int data_type, ret; - u32 tx_data, spidat1; - u32 errors = 0; - struct davinci_spi_config *spicfg; - unsigned rx_buf_count; - struct rt_device *sdev; - u8 chip_select = (u8)spi->parent.user_data; + struct davinci_spi *dspi; + int data_type, ret; + u32 tx_data, spidat1; + u32 errors = 0; + struct davinci_spi_config *spicfg; + unsigned rx_buf_count; + struct rt_device *sdev; + u8 chip_select = (u8)spi->parent.user_data; - dspi = spi->bus->parent.user_data; - spicfg = (struct davinci_spi_config *)dspi->controller_data; - if (!spicfg) - spicfg = &davinci_spi_default_cfg; - sdev = &dspi->parent.parent; + dspi = spi->bus->parent.user_data; + spicfg = (struct davinci_spi_config *)dspi->controller_data; + if (!spicfg) + spicfg = &davinci_spi_default_cfg; + sdev = &dspi->parent.parent; - /* convert len to words based on bits_per_word */ - data_type = dspi->bytes_per_word[chip_select]; + /* convert len to words based on bits_per_word */ + data_type = dspi->bytes_per_word[chip_select]; - dspi->tx = msg->send_buf; - dspi->rx = msg->recv_buf; - dspi->wcount = msg->length / data_type; - dspi->rcount = dspi->wcount; + dspi->tx = msg->send_buf; + dspi->rx = msg->recv_buf; + dspi->wcount = msg->length / data_type; + dspi->rcount = dspi->wcount; - spidat1 = readl(dspi->base + SPIDAT1); + spidat1 = readl(dspi->base + SPIDAT1); - clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); - set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); + clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); + set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); - rt_completion_init(&(dspi->done)); + rt_completion_init(&(dspi->done)); - if (msg->cs_take) - davinci_spi_chipselect(spi, 0); + if (msg->cs_take) + davinci_spi_chipselect(spi, 0); - if (spicfg->io_type == SPI_IO_TYPE_INTR) - set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); + if (spicfg->io_type == SPI_IO_TYPE_INTR) + set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); - if (msg->length > 0) { - if (spicfg->io_type != SPI_IO_TYPE_DMA) { - /* start the transfer */ - dspi->wcount--; - tx_data = dspi->get_tx(dspi); - spidat1 &= 0xFFFF0000; - spidat1 |= tx_data & 0xFFFF; - writel(spidat1, dspi->base + SPIDAT1); - } else { - struct davinci_spi_dma *dma; - unsigned long tx_reg, rx_reg; - struct edmacc_param param; - void *rx_buf; - int b, c; + if (msg->length > 0) { + if (spicfg->io_type != SPI_IO_TYPE_DMA) { + /* start the transfer */ + dspi->wcount--; + tx_data = dspi->get_tx(dspi); + spidat1 &= 0xFFFF0000; + spidat1 |= tx_data & 0xFFFF; + writel(spidat1, dspi->base + SPIDAT1); + } else { + struct davinci_spi_dma *dma; + unsigned long tx_reg, rx_reg; + struct edmacc_param param; + void *rx_buf; + int b, c; - dma = &dspi->dma; + dma = &dspi->dma; - tx_reg = (unsigned long)dspi->base + SPIDAT1; - rx_reg = (unsigned long)dspi->base + SPIBUF; + tx_reg = (unsigned long)dspi->base + SPIDAT1; + rx_reg = (unsigned long)dspi->base + SPIBUF; - /* - * Transmit DMA setup - * - * If there is transmit data, map the transmit buffer, set it - * as the source of data and set the source B index to data - * size. If there is no transmit data, set the transmit register - * as the source of data, and set the source B index to zero. - * - * The destination is always the transmit register itself. And - * the destination never increments. - */ + /* + * Transmit DMA setup + * + * If there is transmit data, map the transmit buffer, set it + * as the source of data and set the source B index to data + * size. If there is no transmit data, set the transmit register + * as the source of data, and set the source B index to zero. + * + * The destination is always the transmit register itself. And + * the destination never increments. + */ - if (msg->send_buf) { - mmu_clean_dcache((rt_uint32_t)msg->send_buf, (rt_uint32_t)msg->length); - } + if (msg->send_buf) { + mmu_clean_dcache((rt_uint32_t)msg->send_buf, (rt_uint32_t)msg->length); + } - /* - * If number of words is greater than 65535, then we need - * to configure a 3 dimension transfer. Use the BCNTRLD - * feature to allow for transfers that aren't even multiples - * of 65535 (or any other possible b size) by first transferring - * the remainder amount then grabbing the next N blocks of - * 65535 words. - */ + /* + * If number of words is greater than 65535, then we need + * to configure a 3 dimension transfer. Use the BCNTRLD + * feature to allow for transfers that aren't even multiples + * of 65535 (or any other possible b size) by first transferring + * the remainder amount then grabbing the next N blocks of + * 65535 words. + */ - c = dspi->wcount / (SZ_64K - 1); /* N 65535 Blocks */ - b = dspi->wcount - c * (SZ_64K - 1); /* Remainder */ - if (b) - c++; - else - b = SZ_64K - 1; + c = dspi->wcount / (SZ_64K - 1); /* N 65535 Blocks */ + b = dspi->wcount - c * (SZ_64K - 1); /* Remainder */ + if (b) + c++; + else + b = SZ_64K - 1; - param.opt = TCINTEN | EDMA_TCC(dma->tx_channel); - param.src = msg->send_buf ? msg->send_buf : tx_reg; - param.a_b_cnt = b << 16 | data_type; - param.dst = tx_reg; - param.src_dst_bidx = msg->send_buf ? data_type : 0; - param.link_bcntrld = 0xffffffff; - param.src_dst_cidx = msg->send_buf ? data_type : 0; - param.ccnt = c; - edma_write_slot(dma->tx_channel, ¶m); - edma_link(dma->tx_channel, dma->dummy_param_slot); + param.opt = TCINTEN | EDMA_TCC(dma->tx_channel); + param.src = msg->send_buf ? msg->send_buf : tx_reg; + param.a_b_cnt = b << 16 | data_type; + param.dst = tx_reg; + param.src_dst_bidx = msg->send_buf ? data_type : 0; + param.link_bcntrld = 0xffffffff; + param.src_dst_cidx = msg->send_buf ? data_type : 0; + param.ccnt = c; + edma_write_slot(dma->tx_channel, ¶m); + edma_link(dma->tx_channel, dma->dummy_param_slot); - /* - * Receive DMA setup - * - * If there is receive buffer, use it to receive data. If there - * is none provided, use a temporary receive buffer. Set the - * destination B index to 0 so effectively only one byte is used - * in the temporary buffer (address does not increment). - * - * The source of receive data is the receive data register. The - * source address never increments. - */ + /* + * Receive DMA setup + * + * If there is receive buffer, use it to receive data. If there + * is none provided, use a temporary receive buffer. Set the + * destination B index to 0 so effectively only one byte is used + * in the temporary buffer (address does not increment). + * + * The source of receive data is the receive data register. The + * source address never increments. + */ - if (msg->recv_buf) { - rx_buf = msg->recv_buf; - rx_buf_count = msg->length; - } else { - rx_buf = dspi->rx_tmp_buf; - rx_buf_count = sizeof(dspi->rx_tmp_buf); - } + if (msg->recv_buf) { + rx_buf = msg->recv_buf; + rx_buf_count = msg->length; + } else { + rx_buf = dspi->rx_tmp_buf; + rx_buf_count = sizeof(dspi->rx_tmp_buf); + } - mmu_invalidate_dcache((rt_uint32_t)rx_buf, (rt_uint32_t)rx_buf_count); + mmu_invalidate_dcache((rt_uint32_t)rx_buf, (rt_uint32_t)rx_buf_count); - param.opt = TCINTEN | EDMA_TCC(dma->rx_channel); - param.src = rx_reg; - param.a_b_cnt = b << 16 | data_type; - param.dst = rx_buf; - param.src_dst_bidx = (msg->recv_buf ? data_type : 0) << 16; - param.link_bcntrld = 0xffffffff; - param.src_dst_cidx = (msg->recv_buf ? data_type : 0) << 16; - param.ccnt = c; - edma_write_slot(dma->rx_channel, ¶m); + param.opt = TCINTEN | EDMA_TCC(dma->rx_channel); + param.src = rx_reg; + param.a_b_cnt = b << 16 | data_type; + param.dst = rx_buf; + param.src_dst_bidx = (msg->recv_buf ? data_type : 0) << 16; + param.link_bcntrld = 0xffffffff; + param.src_dst_cidx = (msg->recv_buf ? data_type : 0) << 16; + param.ccnt = c; + edma_write_slot(dma->rx_channel, ¶m); - if (dspi->cshold_bug) - writew(spidat1 >> 16, dspi->base + SPIDAT1 + 2); + if (dspi->cshold_bug) + writew(spidat1 >> 16, dspi->base + SPIDAT1 + 2); - edma_start(dma->rx_channel); - edma_start(dma->tx_channel); - set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); - } + edma_start(dma->rx_channel); + edma_start(dma->tx_channel); + set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); + } - /* Wait for the transfer to complete */ - if (spicfg->io_type != SPI_IO_TYPE_POLL) { - rt_completion_wait(&(dspi->done), RT_WAITING_FOREVER); - } else { - while (dspi->rcount > 0 || dspi->wcount > 0) { - errors = davinci_spi_process_events(dspi); - if (errors) - break; - cpu_relax(); - } - } - } + /* Wait for the transfer to complete */ + if (spicfg->io_type != SPI_IO_TYPE_POLL) { + rt_completion_wait(&(dspi->done), RT_WAITING_FOREVER); + } else { + while (dspi->rcount > 0 || dspi->wcount > 0) { + errors = davinci_spi_process_events(dspi); + if (errors) + break; + cpu_relax(); + } + } + } - if (msg->cs_release) - davinci_spi_chipselect(spi, 1); + if (msg->cs_release) + davinci_spi_chipselect(spi, 1); - clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL); - if (spicfg->io_type == SPI_IO_TYPE_DMA) { - clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); - } + clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL); + if (spicfg->io_type == SPI_IO_TYPE_DMA) { + clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); + } - clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); - set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); + clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); + set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); - /* - * Check for bit error, desync error,parity error,timeout error and - * receive overflow errors - */ - if (errors) { - ret = davinci_spi_check_error(dspi, errors); - rt_kprintf("%s: error reported but no error found!\n", - spi->bus->parent.parent.name); - return ret; - } + /* + * Check for bit error, desync error,parity error,timeout error and + * receive overflow errors + */ + if (errors) { + ret = davinci_spi_check_error(dspi, errors); + rt_kprintf("%s: error reported but no error found!\n", + spi->bus->parent.parent.name); + return ret; + } - if (dspi->rcount != 0 || dspi->wcount != 0) { - spi_dbg(sdev, "SPI data transfer error\n"); - return -RT_EIO; - } + if (dspi->rcount != 0 || dspi->wcount != 0) { + spi_dbg(sdev, "SPI data transfer error\n"); + return -RT_EIO; + } - return msg->length; + return msg->length; } /** @@ -749,65 +735,65 @@ static int davinci_spi_bufs(struct rt_spi_device *spi, struct rt_spi_message *ms */ static void davinci_spi_irq(int irq, void *data) { - struct davinci_spi *dspi = data; - int status; + struct davinci_spi *dspi = data; + int status; - status = davinci_spi_process_events(dspi); - if (unlikely(status != 0)) - clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); + status = davinci_spi_process_events(dspi); + if (unlikely(status != 0)) + clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); - if ((!dspi->rcount && !dspi->wcount) || status) - rt_completion_done(&dspi->done); + if ((!dspi->rcount && !dspi->wcount) || status) + rt_completion_done(&dspi->done); } static int davinci_spi_request_dma(struct davinci_spi *dspi) { - int r; - struct davinci_spi_dma *dma = &dspi->dma; + int r; + struct davinci_spi_dma *dma = &dspi->dma; - r = edma_alloc_channel(dma->rx_channel, davinci_spi_dma_callback, dspi, - dma->eventq); - if (r < 0) { - rt_kprintf("Unable to request DMA channel for SPI RX\n"); - r = -RT_EFULL; - goto rx_dma_failed; - } + r = edma_alloc_channel(dma->rx_channel, davinci_spi_dma_callback, dspi, + dma->eventq); + if (r < 0) { + rt_kprintf("Unable to request DMA channel for SPI RX\n"); + r = -RT_EFULL; + goto rx_dma_failed; + } - r = edma_alloc_channel(dma->tx_channel, davinci_spi_dma_callback, dspi, - dma->eventq); - if (r < 0) { - rt_kprintf("Unable to request DMA channel for SPI TX\n"); - r = -RT_EFULL; - goto tx_dma_failed; - } + r = edma_alloc_channel(dma->tx_channel, davinci_spi_dma_callback, dspi, + dma->eventq); + if (r < 0) { + rt_kprintf("Unable to request DMA channel for SPI TX\n"); + r = -RT_EFULL; + goto tx_dma_failed; + } - r = edma_alloc_slot(EDMA_CTLR(dma->tx_channel), EDMA_SLOT_ANY); - if (r < 0) { - rt_kprintf("Unable to request SPI TX DMA param slot\n"); - r = -RT_EFULL; - goto param_failed; - } - dma->dummy_param_slot = r; - edma_link(dma->dummy_param_slot, dma->dummy_param_slot); + r = edma_alloc_slot(EDMA_CTLR(dma->tx_channel), EDMA_SLOT_ANY); + if (r < 0) { + rt_kprintf("Unable to request SPI TX DMA param slot\n"); + r = -RT_EFULL; + goto param_failed; + } + dma->dummy_param_slot = r; + edma_link(dma->dummy_param_slot, dma->dummy_param_slot); - return 0; + return 0; param_failed: - edma_free_channel(dma->tx_channel); + edma_free_channel(dma->tx_channel); tx_dma_failed: - edma_free_channel(dma->rx_channel); + edma_free_channel(dma->rx_channel); rx_dma_failed: - return r; + return r; } static rt_err_t configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration) { - return davinci_spi_setup_transfer(device, configuration); + return davinci_spi_setup_transfer(device, configuration); } static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message *message) { - return davinci_spi_bufs(device, message); + return davinci_spi_bufs(device, message); }; @@ -820,29 +806,29 @@ static struct rt_spi_ops davinci_spi_ops = static void udelay (volatile rt_uint32_t us) { - volatile rt_int32_t i; - for (; us > 0; us--) - { - i = 5000; - while(i > 0) - { - i--; - } - } + volatile rt_int32_t i; + for (; us > 0; us--) + { + i = 5000; + while(i > 0) + { + i--; + } + } } void spi_pin_cfg(void) { - rt_uint32_t val; + rt_uint32_t val; - val = davinci_readl(PINMUX3); - val |= 0x80000000; /* SPI1 */ - davinci_writel(val, PINMUX3); + val = davinci_readl(PINMUX3); + val |= 0x80000000; /* SPI1 */ + davinci_writel(val, PINMUX3); - val = davinci_readl(PINMUX4); - val &= 0xffffffc0; /* SPI1 */ - val |= 0x05;//0x00000015; /* SPI1 */ - davinci_writel(val, PINMUX4); + val = davinci_readl(PINMUX4); + val &= 0xffffffc0; /* SPI1 */ + val |= 0x05;//0x00000015; /* SPI1 */ + davinci_writel(val, PINMUX4); } /** @@ -858,87 +844,87 @@ void spi_pin_cfg(void) */ static int davinci_spi_probe(struct davinci_spi *dspi, char *spi_bus_name) { - int i = 0, ret = 0; - u32 spipc0; + int i = 0, ret = 0; + u32 spipc0; - spi_pin_cfg(); - psc_change_state(DAVINCI_DM365_LPSC_SPI1, PSC_ENABLE); + spi_pin_cfg(); + psc_change_state(DAVINCI_DM365_LPSC_SPI1, PSC_ENABLE); - dspi->base = DM3XX_SPI1_BASE;//spi; + dspi->base = DM3XX_SPI1_BASE;//spi; - dspi->irq = IRQ_DM3XX_SPINT1_0; + dspi->irq = IRQ_DM3XX_SPINT1_0; - rt_hw_interrupt_install(dspi->irq, davinci_spi_irq, dspi, spi_bus_name); - rt_hw_interrupt_umask(dspi->irq); + rt_hw_interrupt_install(dspi->irq, davinci_spi_irq, dspi, spi_bus_name); + rt_hw_interrupt_umask(dspi->irq); - dspi->clk = clk_get("SPICLK"); + dspi->clk = clk_get("SPICLK"); - dspi->version = SPI_VERSION_1; - dspi->chip_sel[0] = 29;//SPI_INTERN_CS; - dspi->chip_sel[1] = 0;//GPIO0 + dspi->version = SPI_VERSION_1; + dspi->chip_sel[0] = 29;//SPI_INTERN_CS; + dspi->chip_sel[1] = 0;//GPIO0 - dspi->dma.rx_channel = 15; - dspi->dma.tx_channel = 14; - dspi->dma.eventq = EVENTQ_3; + dspi->dma.rx_channel = 15; + dspi->dma.tx_channel = 14; + dspi->dma.eventq = EVENTQ_3; - ret = davinci_spi_request_dma(dspi); - if (ret) - goto err; + ret = davinci_spi_request_dma(dspi); + if (ret) + goto err; - rt_kprintf("%s: DMA: supported\n", spi_bus_name); - rt_kprintf("%s: DMA: RX channel: %d, TX channel: %d, " - "event queue: %d\n", spi_bus_name, dspi->dma.rx_channel, - dspi->dma.tx_channel, dspi->dma.eventq); + rt_kprintf("%s: DMA: supported\n", spi_bus_name); + rt_kprintf("%s: DMA: RX channel: %d, TX channel: %d, " + "event queue: %d\n", spi_bus_name, dspi->dma.rx_channel, + dspi->dma.tx_channel, dspi->dma.eventq); - dspi->get_rx = davinci_spi_rx_buf_u8; - dspi->get_tx = davinci_spi_tx_buf_u8; + dspi->get_rx = davinci_spi_rx_buf_u8; + dspi->get_tx = davinci_spi_tx_buf_u8; - rt_completion_init(&dspi->done); + rt_completion_init(&dspi->done); - /* Reset In/OUT SPI module */ - writel(0, dspi->base + SPIGCR0); - udelay(100); - writel(1, dspi->base + SPIGCR0); + /* Reset In/OUT SPI module */ + writel(0, dspi->base + SPIGCR0); + udelay(100); + writel(1, dspi->base + SPIGCR0); - /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ - spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; - writel(spipc0, dspi->base + SPIPC0); + /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ + spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; + writel(spipc0, dspi->base + SPIPC0); - /* initialize chip selects */ - for (i = 0; i < SPI_MAX_CHIPSELECT; i++) { - if (dspi->chip_sel[i] != SPI_INTERN_CS) - gpio_direction_output(dspi->chip_sel[i], 1); - } + /* initialize chip selects */ + for (i = 0; i < SPI_MAX_CHIPSELECT; i++) { + if (dspi->chip_sel[i] != SPI_INTERN_CS) + gpio_direction_output(dspi->chip_sel[i], 1); + } - if (0) - writel(SPI_INTLVL_1, dspi->base + SPILVL); - else - writel(SPI_INTLVL_0, dspi->base + SPILVL); + if (0) + writel(SPI_INTLVL_1, dspi->base + SPILVL); + else + writel(SPI_INTLVL_0, dspi->base + SPILVL); - writel(CS_DEFAULT, dspi->base + SPIDEF); + writel(CS_DEFAULT, dspi->base + SPIDEF); - /* master mode default */ - set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); - set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK); - set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); + /* master mode default */ + set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK); + set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK); + set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); - //set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);//LOOP BACK mode + //set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);//LOOP BACK mode - rt_kprintf("%s: Controller at 0x%p\n", spi_bus_name, dspi->base); + rt_kprintf("%s: Controller at 0x%p\n", spi_bus_name, dspi->base); - dspi->parent.parent.user_data = dspi; + dspi->parent.parent.user_data = dspi; - return rt_spi_bus_register(&dspi->parent, spi_bus_name, &davinci_spi_ops); + return rt_spi_bus_register(&dspi->parent, spi_bus_name, &davinci_spi_ops); - return ret; + return ret; free_dma: - edma_free_channel(dspi->dma.tx_channel); - edma_free_channel(dspi->dma.rx_channel); - edma_free_slot(dspi->dma.dummy_param_slot); + edma_free_channel(dspi->dma.tx_channel); + edma_free_channel(dspi->dma.rx_channel); + edma_free_slot(dspi->dma.dummy_param_slot); err: - return ret; + return ret; } @@ -947,15 +933,15 @@ int rt_hw_spi_init(void) /* register spi bus */ { static struct davinci_spi dspi; - rt_memset(&dspi, 0, sizeof(dspi)); - davinci_spi_probe(&dspi, "spi1"); + rt_memset(&dspi, 0, sizeof(dspi)); + davinci_spi_probe(&dspi, "spi1"); } /* attach cs */ { static struct rt_spi_device spi_device; rt_spi_bus_attach_device(&spi_device, "spi10", "spi1", (void *)0); } - { + { static struct rt_spi_device spi_device; rt_spi_bus_attach_device(&spi_device, "spi11", "spi1", (void *)1); } diff --git a/bsp/dm365/drivers/spi-davinci.h b/bsp/dm365/drivers/spi-davinci.h index 07e8bef4df..d1761e03f3 100644 --- a/bsp/dm365/drivers/spi-davinci.h +++ b/bsp/dm365/drivers/spi-davinci.h @@ -1,25 +1,11 @@ /* - * File : spi-davinci.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version + * Date Author Notes + * 2011-01-13 weety first version */ #ifndef __DAVINCI_SPI_H @@ -30,46 +16,46 @@ typedef unsigned short u16; typedef unsigned char u8; typedef unsigned int bool; -#define SPI_INTERN_CS 0xFF +#define SPI_INTERN_CS 0xFF enum { - SPI_VERSION_1, /* For DM355/DM365/DM6467 */ - SPI_VERSION_2, /* For DA8xx */ + SPI_VERSION_1, /* For DM355/DM365/DM6467 */ + SPI_VERSION_2, /* For DA8xx */ }; /** * davinci_spi_config - Per-chip-select configuration for SPI slave devices * - * @wdelay: amount of delay between transmissions. Measured in number of - * SPI module clocks. - * @odd_parity: polarity of parity flag at the end of transmit data stream. - * 0 - odd parity, 1 - even parity. + * @wdelay: amount of delay between transmissions. Measured in number of + * SPI module clocks. + * @odd_parity: polarity of parity flag at the end of transmit data stream. + * 0 - odd parity, 1 - even parity. * @parity_enable: enable transmission of parity at end of each transmit - * data stream. - * @io_type: type of IO transfer. Choose between polled, interrupt and DMA. + * data stream. + * @io_type: type of IO transfer. Choose between polled, interrupt and DMA. * @timer_disable: disable chip-select timers (setup and hold) - * @c2tdelay: chip-select setup time. Measured in number of SPI module clocks. - * @t2cdelay: chip-select hold time. Measured in number of SPI module clocks. - * @t2edelay: transmit data finished to SPI ENAn pin inactive time. Measured - * in number of SPI clocks. - * @c2edelay: chip-select active to SPI ENAn signal active time. Measured in - * number of SPI clocks. + * @c2tdelay: chip-select setup time. Measured in number of SPI module clocks. + * @t2cdelay: chip-select hold time. Measured in number of SPI module clocks. + * @t2edelay: transmit data finished to SPI ENAn pin inactive time. Measured + * in number of SPI clocks. + * @c2edelay: chip-select active to SPI ENAn signal active time. Measured in + * number of SPI clocks. */ struct davinci_spi_config { - u8 wdelay; - u8 odd_parity; - u8 parity_enable; -#define SPI_IO_TYPE_INTR 0 -#define SPI_IO_TYPE_POLL 1 -#define SPI_IO_TYPE_DMA 2 - u8 io_type; - u8 timer_disable; - u8 c2tdelay; - u8 t2cdelay; - u8 t2edelay; - u8 c2edelay; + u8 wdelay; + u8 odd_parity; + u8 parity_enable; +#define SPI_IO_TYPE_INTR 0 +#define SPI_IO_TYPE_POLL 1 +#define SPI_IO_TYPE_DMA 2 + u8 io_type; + u8 timer_disable; + u8 c2tdelay; + u8 t2cdelay; + u8 t2edelay; + u8 c2edelay; }; extern int rt_hw_spi_init(void); -#endif /* __DAVINCI_SPI_H */ +#endif /* __DAVINCI_SPI_H */ diff --git a/bsp/dm365/platform/dm365.c b/bsp/dm365/platform/dm365.c index 010e2a030e..0fe2d0a94a 100644 --- a/bsp/dm365/platform/dm365.c +++ b/bsp/dm365/platform/dm365.c @@ -1,25 +1,11 @@ /* - * File : dm365.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ #include @@ -40,285 +26,285 @@ static rt_uint32_t vpssrate, vencrate_sd, vencrate_hd; /* Four Transfer Controllers on DM365 */ static const rt_int8_t dm365_queue_tc_mapping[][2] = { - /* {event queue no, TC no} */ - {0, 0}, - {1, 1}, - {2, 2}, - {3, 3}, - {-1, -1}, + /* {event queue no, TC no} */ + {0, 0}, + {1, 1}, + {2, 2}, + {3, 3}, + {-1, -1}, }; static const rt_int8_t dm365_queue_priority_mapping[][2] = { - /* {event queue no, Priority} */ - {0, 7}, - {1, 7}, - {2, 7}, - {3, 0}, - {-1, -1}, + /* {event queue no, Priority} */ + {0, 7}, + {1, 7}, + {2, 7}, + {3, 0}, + {-1, -1}, }; static struct edma_soc_info edma_cc0_info = { - .n_channel = 64, - .n_region = 4, - .n_slot = 256, - .n_tc = 4, - .n_cc = 1, - .queue_tc_mapping = dm365_queue_tc_mapping, - .queue_priority_mapping = dm365_queue_priority_mapping, - .default_queue = EVENTQ_3, + .n_channel = 64, + .n_region = 4, + .n_slot = 256, + .n_tc = 4, + .n_cc = 1, + .queue_tc_mapping = dm365_queue_tc_mapping, + .queue_priority_mapping = dm365_queue_priority_mapping, + .default_queue = EVENTQ_3, }; static struct edma_soc_info *dm365_edma_info[EDMA_MAX_CC] = { - &edma_cc0_info, + &edma_cc0_info, }; static rt_list_t clocks; struct clk { - char name[32]; - rt_uint32_t *rate_hz; - struct clk *parent; - rt_list_t node; + char name[32]; + rt_uint32_t *rate_hz; + struct clk *parent; + rt_list_t node; }; static struct clk davinci_dm365_clks[] = { - { - .name = "ARMCLK", - .rate_hz = &armrate, - }, - { - .name = "UART0", - .rate_hz = &fixedrate, - }, - { - .name = "UART1", - .rate_hz = &commonrate, - }, - { - .name = "HPI", - .rate_hz = &commonrate, - }, - { - .name = "EMACCLK", - .rate_hz = &commonrate, - }, - { - .name = "I2CCLK", - .rate_hz = &fixedrate, - }, - { - .name = "McBSPCLK", - .rate_hz = &commonrate, - }, - { - .name = "MMCSDCLK0", - .rate_hz = &mmcsdrate, - }, - { - .name = "MMCSDCLK1", - .rate_hz = &mmcsdrate, - }, - { - .name = "SPICLK", - .rate_hz = &commonrate, - }, - { - .name = "gpio", - .rate_hz = &commonrate, - }, - { - .name = "AEMIFCLK", - .rate_hz = &commonrate, - }, - { - .name = "PWM0_CLK", - .rate_hz = &fixedrate, - }, - { - .name = "PWM1_CLK", - .rate_hz = &fixedrate, - }, - { - .name = "PWM2_CLK", - .rate_hz = &fixedrate, - }, - { - .name = "PWM3_CLK", - .rate_hz = &fixedrate, - }, - { - .name = "USBCLK", - .rate_hz = &fixedrate, - }, - { - .name = "VOICECODEC_CLK", - .rate_hz = &voicerate, - }, - { - .name = "RTC_CLK", - .rate_hz = &fixedrate, - }, - { - .name = "KEYSCAN_CLK", - .rate_hz = &fixedrate, - }, - { - .name = "ADCIF_CLK", - .rate_hz = &fixedrate, - }, + { + .name = "ARMCLK", + .rate_hz = &armrate, + }, + { + .name = "UART0", + .rate_hz = &fixedrate, + }, + { + .name = "UART1", + .rate_hz = &commonrate, + }, + { + .name = "HPI", + .rate_hz = &commonrate, + }, + { + .name = "EMACCLK", + .rate_hz = &commonrate, + }, + { + .name = "I2CCLK", + .rate_hz = &fixedrate, + }, + { + .name = "McBSPCLK", + .rate_hz = &commonrate, + }, + { + .name = "MMCSDCLK0", + .rate_hz = &mmcsdrate, + }, + { + .name = "MMCSDCLK1", + .rate_hz = &mmcsdrate, + }, + { + .name = "SPICLK", + .rate_hz = &commonrate, + }, + { + .name = "gpio", + .rate_hz = &commonrate, + }, + { + .name = "AEMIFCLK", + .rate_hz = &commonrate, + }, + { + .name = "PWM0_CLK", + .rate_hz = &fixedrate, + }, + { + .name = "PWM1_CLK", + .rate_hz = &fixedrate, + }, + { + .name = "PWM2_CLK", + .rate_hz = &fixedrate, + }, + { + .name = "PWM3_CLK", + .rate_hz = &fixedrate, + }, + { + .name = "USBCLK", + .rate_hz = &fixedrate, + }, + { + .name = "VOICECODEC_CLK", + .rate_hz = &voicerate, + }, + { + .name = "RTC_CLK", + .rate_hz = &fixedrate, + }, + { + .name = "KEYSCAN_CLK", + .rate_hz = &fixedrate, + }, + { + .name = "ADCIF_CLK", + .rate_hz = &fixedrate, + }, }; /* clocks cannot be de-registered no refcounting necessary */ struct clk *clk_get(const char *id) { - struct clk *clk; - rt_list_t *list; - - for (list = (&clocks)->next; list != &clocks; list = list->next) - { - clk = (struct clk *)rt_list_entry(list, struct clk, node); - if (rt_strcmp(id, clk->name) == 0) - return clk; - } + struct clk *clk; + rt_list_t *list; - return RT_NULL; + for (list = (&clocks)->next; list != &clocks; list = list->next) + { + clk = (struct clk *)rt_list_entry(list, struct clk, node); + if (rt_strcmp(id, clk->name) == 0) + return clk; + } + + return RT_NULL; } rt_uint32_t clk_get_rate(struct clk *clk) { - rt_uint32_t flags; - rt_uint32_t *rate; + rt_uint32_t flags; + rt_uint32_t *rate; - for (;;) { - rate = clk->rate_hz; - if (rate || !clk->parent) - break; - clk = clk->parent; - } - return *rate; + for (;;) { + rate = clk->rate_hz; + if (rate || !clk->parent) + break; + clk = clk->parent; + } + return *rate; } void clk_register(struct clk *clk) { - rt_list_insert_after(&clocks, &clk->node); + rt_list_insert_after(&clocks, &clk->node); } int davinci_register_clks(struct clk *clk_list, int num_clks) { - struct clk *clkp; - int i; + struct clk *clkp; + int i; - for (i = 0, clkp = clk_list; i < num_clks; i++, clkp++) - { - //rt_kprintf("1:%s\n", clkp->name); - clk_register(clkp); - //rt_kprintf("2:%s\n", clkp->name); - } + for (i = 0, clkp = clk_list; i < num_clks; i++, clkp++) + { + //rt_kprintf("1:%s\n", clkp->name); + clk_register(clkp); + //rt_kprintf("2:%s\n", clkp->name); + } - return 0; + return 0; } /* PLL/Reset register offsets */ -#define PLLM 0x110 -#define PREDIV 0x114 -#define PLLDIV2 0x11C -#define POSTDIV 0x128 -#define PLLDIV4 0x160 -#define PLLDIV5 0x164 -#define PLLDIV6 0x168 -#define PLLDIV7 0x16C -#define PLLDIV8 0x170 +#define PLLM 0x110 +#define PREDIV 0x114 +#define PLLDIV2 0x11C +#define POSTDIV 0x128 +#define PLLDIV4 0x160 +#define PLLDIV5 0x164 +#define PLLDIV6 0x168 +#define PLLDIV7 0x16C +#define PLLDIV8 0x170 int davinci_clk_init(void) { - struct clk *clk_list; - int num_clks; - rt_uint32_t pll0_mult, pll1_mult; + struct clk *clk_list; + int num_clks; + rt_uint32_t pll0_mult, pll1_mult; - unsigned long prediv, postdiv; - unsigned long pll_rate; - unsigned long pll_div2, pll_div4, pll_div5, - pll_div6, pll_div7, pll_div8; + unsigned long prediv, postdiv; + unsigned long pll_rate; + unsigned long pll_div2, pll_div4, pll_div5, + pll_div6, pll_div7, pll_div8; - rt_list_init(&clocks); + rt_list_init(&clocks); - //davinci_psc_register(davinci_psc_base, 1); + //davinci_psc_register(davinci_psc_base, 1); - pll0_mult = davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLM); - pll1_mult = davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLM); + pll0_mult = davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLM); + pll1_mult = davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLM); - commonrate = ((pll0_mult + 1) * 27000000) / 6; - armrate = ((pll0_mult + 1) * 27000000) / 2; + commonrate = ((pll0_mult + 1) * 27000000) / 6; + armrate = ((pll0_mult + 1) * 27000000) / 2; - fixedrate = 24000000; + fixedrate = 24000000; - /* Read PLL0 configuration */ - prediv = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PREDIV) & - 0x1f) + 1; - postdiv = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + POSTDIV) & - 0x1f) + 1; + /* Read PLL0 configuration */ + prediv = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PREDIV) & + 0x1f) + 1; + postdiv = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + POSTDIV) & + 0x1f) + 1; - /* PLL0 dividers */ - pll_div4 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV4) & - 0x1f) + 1; /* EDMA, EMAC, config, common */ - pll_div5 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV5) & - 0x1f) + 1; /* VPSS */ - pll_div6 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV6) & - 0x1f) + 1; /* VENC */ - pll_div7 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV7) & - 0x1f) + 1; /* DDR */ - pll_div8 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV8) & - 0x1f) + 1; /* MMC/SD */ + /* PLL0 dividers */ + pll_div4 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV4) & + 0x1f) + 1; /* EDMA, EMAC, config, common */ + pll_div5 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV5) & + 0x1f) + 1; /* VPSS */ + pll_div6 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV6) & + 0x1f) + 1; /* VENC */ + pll_div7 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV7) & + 0x1f) + 1; /* DDR */ + pll_div8 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV8) & + 0x1f) + 1; /* MMC/SD */ - pll_rate = ((fixedrate / prediv) * (2 * pll0_mult)) / postdiv; + pll_rate = ((fixedrate / prediv) * (2 * pll0_mult)) / postdiv; - commonrate = pll_rate / pll_div4; /* 486/4 = 121.5MHz */ - vpssrate = pll_rate / pll_div5; /* 486/2 = 243MHz */ - vencrate_sd = pll_rate / pll_div6; /* 486/18 = 27MHz */ - ddrrate = pll_rate / pll_div7; /* 486/2 = 243MHz */ - mmcsdrate = pll_rate / pll_div8; /* 486/4 = 121.5MHz */ + commonrate = pll_rate / pll_div4; /* 486/4 = 121.5MHz */ + vpssrate = pll_rate / pll_div5; /* 486/2 = 243MHz */ + vencrate_sd = pll_rate / pll_div6; /* 486/18 = 27MHz */ + ddrrate = pll_rate / pll_div7; /* 486/2 = 243MHz */ + mmcsdrate = pll_rate / pll_div8; /* 486/4 = 121.5MHz */ - rt_kprintf( - "PLL0: fixedrate: %d, commonrate: %d, vpssrate: %d\n", - fixedrate, commonrate, vpssrate); - rt_kprintf( - "PLL0: vencrate_sd: %d, ddrrate: %d mmcsdrate: %d\n", - vencrate_sd, (ddrrate/2), mmcsdrate); + rt_kprintf( + "PLL0: fixedrate: %d, commonrate: %d, vpssrate: %d\n", + fixedrate, commonrate, vpssrate); + rt_kprintf( + "PLL0: vencrate_sd: %d, ddrrate: %d mmcsdrate: %d\n", + vencrate_sd, (ddrrate/2), mmcsdrate); - /* Read PLL1 configuration */ - prediv = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PREDIV) & - 0x1f) + 1; - postdiv = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + POSTDIV) & - 0x1f) + 1; - pll_rate = ((fixedrate / prediv) * (2 * pll1_mult)) / postdiv; + /* Read PLL1 configuration */ + prediv = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PREDIV) & + 0x1f) + 1; + postdiv = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + POSTDIV) & + 0x1f) + 1; + pll_rate = ((fixedrate / prediv) * (2 * pll1_mult)) / postdiv; - /* PLL1 dividers */ - pll_div2 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV2) & - 0x1f) + 1; /* ARM */ - pll_div4 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV4) & - 0x1f) + 1; /* VOICE */ - pll_div5 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV5) & - 0x1f) + 1; /* VENC */ + /* PLL1 dividers */ + pll_div2 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV2) & + 0x1f) + 1; /* ARM */ + pll_div4 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV4) & + 0x1f) + 1; /* VOICE */ + pll_div5 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV5) & + 0x1f) + 1; /* VENC */ - armrate = pll_rate / pll_div2; /* 594/2 = 297MHz */ - voicerate = pll_rate / pll_div4; /* 594/6 = 99MHz */ - vencrate_hd = pll_rate / pll_div5; /* 594/8 = 74.25MHz */ + armrate = pll_rate / pll_div2; /* 594/2 = 297MHz */ + voicerate = pll_rate / pll_div4; /* 594/6 = 99MHz */ + vencrate_hd = pll_rate / pll_div5; /* 594/8 = 74.25MHz */ - rt_kprintf( - "PLL1: armrate: %d, voicerate: %d, vencrate_hd: %d\n", - armrate, voicerate, vencrate_hd); + rt_kprintf( + "PLL1: armrate: %d, voicerate: %d, vencrate_hd: %d\n", + armrate, voicerate, vencrate_hd); - clk_list = davinci_dm365_clks; - num_clks = ARRAY_SIZE(davinci_dm365_clks); + clk_list = davinci_dm365_clks; + num_clks = ARRAY_SIZE(davinci_dm365_clks); - return davinci_register_clks(clk_list, num_clks); + return davinci_register_clks(clk_list, num_clks); } int platform_init(void) { - edma_init(dm365_edma_info); + edma_init(dm365_edma_info); } INIT_BOARD_EXPORT(platform_init); @@ -326,44 +312,44 @@ INIT_BOARD_EXPORT(platform_init); /* Reset board using the watchdog timer */ void reset_system(void) { - rt_uint32_t tgcr, wdtcr; - rt_uint32_t base = DAVINCI_WDOG_BASE; + rt_uint32_t tgcr, wdtcr; + rt_uint32_t base = DAVINCI_WDOG_BASE; - /* Disable, internal clock source */ - davinci_writel(0, base + TCR); + /* Disable, internal clock source */ + davinci_writel(0, base + TCR); - /* Reset timer, set mode to 64-bit watchdog, and unreset */ - davinci_writel(0, base + TGCR); - tgcr = (TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT) | - (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | - (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); - davinci_writel(tgcr, base + TGCR); + /* Reset timer, set mode to 64-bit watchdog, and unreset */ + davinci_writel(0, base + TGCR); + tgcr = (TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT) | + (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) | + (TGCR_UNRESET << TGCR_TIM34RS_SHIFT); + davinci_writel(tgcr, base + TGCR); - /* Clear counter and period regs */ - davinci_writel(0, base + TIM12); - davinci_writel(0, base + TIM34); - davinci_writel(0, base + PRD12); - davinci_writel(0, base + PRD34); + /* Clear counter and period regs */ + davinci_writel(0, base + TIM12); + davinci_writel(0, base + TIM34); + davinci_writel(0, base + PRD12); + davinci_writel(0, base + PRD34); - /* Enable periodic mode */ - davinci_writel(TCR_ENAMODE_PERIODIC << ENAMODE12_SHIFT, base + TCR); + /* Enable periodic mode */ + davinci_writel(TCR_ENAMODE_PERIODIC << ENAMODE12_SHIFT, base + TCR); - /* Put watchdog in pre-active state */ - wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) | - (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); - davinci_writel(wdtcr, base + WDTCR); + /* Put watchdog in pre-active state */ + wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) | + (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); + davinci_writel(wdtcr, base + WDTCR); - /* Put watchdog in active state */ - wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) | - (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); - davinci_writel(wdtcr, base + WDTCR); + /* Put watchdog in active state */ + wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) | + (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT); + davinci_writel(wdtcr, base + WDTCR); - /* - * Write an invalid value to the WDKEY field to trigger - * a watchdog reset. - */ - wdtcr = 0xDEADBEEF; - davinci_writel(wdtcr, base + WDTCR); + /* + * Write an invalid value to the WDKEY field to trigger + * a watchdog reset. + */ + wdtcr = 0xDEADBEEF; + davinci_writel(wdtcr, base + WDTCR); } diff --git a/bsp/dm365/platform/dm365_timer.h b/bsp/dm365/platform/dm365_timer.h index 2dd6114c02..93a0e3ef6b 100644 --- a/bsp/dm365/platform/dm365_timer.h +++ b/bsp/dm365/platform/dm365_timer.h @@ -1,74 +1,60 @@ /* - * File : dm365_timer.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ #ifndef __ASM_ARCH_TIME_H #define __ASM_ARCH_TIME_H /* Timer register offsets */ -#define PID12 0x0 -#define TIM12 0x10 -#define TIM34 0x14 -#define PRD12 0x18 -#define PRD34 0x1c -#define TCR 0x20 -#define TGCR 0x24 -#define WDTCR 0x28 -#define CMP12(n) (0x60 + ((n) << 2)) +#define PID12 0x0 +#define TIM12 0x10 +#define TIM34 0x14 +#define PRD12 0x18 +#define PRD34 0x1c +#define TCR 0x20 +#define TGCR 0x24 +#define WDTCR 0x28 +#define CMP12(n) (0x60 + ((n) << 2)) /* Timer register bitfields */ -#define ENAMODE12_SHIFT 6 -#define ENAMODE34_SHIFT 22 -#define TCR_ENAMODE_DISABLE 0x0 -#define TCR_ENAMODE_ONESHOT 0x1 -#define TCR_ENAMODE_PERIODIC 0x2 -#define TCR_ENAMODE_MASK 0x3 +#define ENAMODE12_SHIFT 6 +#define ENAMODE34_SHIFT 22 +#define TCR_ENAMODE_DISABLE 0x0 +#define TCR_ENAMODE_ONESHOT 0x1 +#define TCR_ENAMODE_PERIODIC 0x2 +#define TCR_ENAMODE_MASK 0x3 -#define TGCR_TIMMODE_SHIFT 2 -#define TGCR_TIMMODE_64BIT_GP 0x0 -#define TGCR_TIMMODE_32BIT_UNCHAINED 0x1 -#define TGCR_TIMMODE_64BIT_WDOG 0x2 -#define TGCR_TIMMODE_32BIT_CHAINED 0x3 +#define TGCR_TIMMODE_SHIFT 2 +#define TGCR_TIMMODE_64BIT_GP 0x0 +#define TGCR_TIMMODE_32BIT_UNCHAINED 0x1 +#define TGCR_TIMMODE_64BIT_WDOG 0x2 +#define TGCR_TIMMODE_32BIT_CHAINED 0x3 -#define TGCR_TIM12RS_SHIFT 0 -#define TGCR_TIM34RS_SHIFT 1 -#define TGCR_RESET 0x0 -#define TGCR_UNRESET 0x1 -#define TGCR_RESET_MASK 0x3 +#define TGCR_TIM12RS_SHIFT 0 +#define TGCR_TIM34RS_SHIFT 1 +#define TGCR_RESET 0x0 +#define TGCR_UNRESET 0x1 +#define TGCR_RESET_MASK 0x3 -#define WDTCR_WDEN_SHIFT 14 -#define WDTCR_WDEN_DISABLE 0x0 -#define WDTCR_WDEN_ENABLE 0x1 -#define WDTCR_WDKEY_SHIFT 16 -#define WDTCR_WDKEY_SEQ0 0xA5C6 -#define WDTCR_WDKEY_SEQ1 0xDA7E +#define WDTCR_WDEN_SHIFT 14 +#define WDTCR_WDEN_DISABLE 0x0 +#define WDTCR_WDEN_ENABLE 0x1 +#define WDTCR_WDKEY_SHIFT 16 +#define WDTCR_WDKEY_SEQ0 0xA5C6 +#define WDTCR_WDKEY_SEQ1 0xDA7E enum { - T0_BOT, - T0_TOP, - T1_BOT, - T1_TOP, - NUM_TIMERS + T0_BOT, + T0_TOP, + T1_BOT, + T1_TOP, + NUM_TIMERS }; #endif /* __ASM_ARCH_TIME_H__ */ diff --git a/bsp/dm365/platform/dm36x.h b/bsp/dm365/platform/dm36x.h index 85be007c24..2aa72a23ce 100644 --- a/bsp/dm365/platform/dm36x.h +++ b/bsp/dm365/platform/dm36x.h @@ -1,25 +1,11 @@ /* - * File : dm36x.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ #ifndef __DM36X_H__ @@ -43,43 +29,43 @@ extern "C" { /* * Base register addresses */ -#define DAVINCI_DMA_3PCC_BASE (0x01C00000) -#define DAVINCI_DMA_3PTC0_BASE (0x01C10000) -#define DAVINCI_DMA_3PTC1_BASE (0x01C10400) -#define DAVINCI_I2C_BASE (0x01C21000) -#define DAVINCI_TIMER0_BASE (0x01C21400) -#define DAVINCI_TIMER1_BASE (0x01C21800) -#define DAVINCI_WDOG_BASE (0x01C21C00) -#define DAVINCI_PWM0_BASE (0x01C22000) -#define DAVINCI_PWM1_BASE (0x01C22400) -#define DAVINCI_PWM2_BASE (0x01C22800) -#define DAVINCI_SYSTEM_MODULE_BASE (0x01C40000) -#define DAVINCI_PLL_CNTRL0_BASE (0x01C40800) -#define DAVINCI_PLL_CNTRL1_BASE (0x01C40C00) -#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01C41000) -#define DAVINCI_SYSTEM_DFT_BASE (0x01C42000) -#define DAVINCI_IEEE1394_BASE (0x01C60000) -#define DAVINCI_USB_OTG_BASE (0x01C64000) -#define DAVINCI_CFC_ATA_BASE (0x01C66000) -#define DAVINCI_SPI_BASE (0x01C66800) -#define DAVINCI_GPIO_BASE (0x01C67000) -#define DAVINCI_UHPI_BASE (0x01C67800) -#define DAVINCI_VPSS_REGS_BASE (0x01C70000) -#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01C80000) -#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01C81000) -#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01C82000) -#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01C84000) -#define DAVINCI_IMCOP_BASE (0x01CC0000) -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01E00000) -#define DAVINCI_VLYNQ_BASE (0x01E01000) -#define DAVINCI_MCBSP_BASE (0x01E02000) -#define DAVINCI_MMC_SD_BASE (0x01E10000) -#define DAVINCI_MS_BASE (0x01E20000) -#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000) -#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000) -#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000) -#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) -#define DAVINCI_VLYNQ_REMOTE_BASE (0x0C000000) +#define DAVINCI_DMA_3PCC_BASE (0x01C00000) +#define DAVINCI_DMA_3PTC0_BASE (0x01C10000) +#define DAVINCI_DMA_3PTC1_BASE (0x01C10400) +#define DAVINCI_I2C_BASE (0x01C21000) +#define DAVINCI_TIMER0_BASE (0x01C21400) +#define DAVINCI_TIMER1_BASE (0x01C21800) +#define DAVINCI_WDOG_BASE (0x01C21C00) +#define DAVINCI_PWM0_BASE (0x01C22000) +#define DAVINCI_PWM1_BASE (0x01C22400) +#define DAVINCI_PWM2_BASE (0x01C22800) +#define DAVINCI_SYSTEM_MODULE_BASE (0x01C40000) +#define DAVINCI_PLL_CNTRL0_BASE (0x01C40800) +#define DAVINCI_PLL_CNTRL1_BASE (0x01C40C00) +#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01C41000) +#define DAVINCI_SYSTEM_DFT_BASE (0x01C42000) +#define DAVINCI_IEEE1394_BASE (0x01C60000) +#define DAVINCI_USB_OTG_BASE (0x01C64000) +#define DAVINCI_CFC_ATA_BASE (0x01C66000) +#define DAVINCI_SPI_BASE (0x01C66800) +#define DAVINCI_GPIO_BASE (0x01C67000) +#define DAVINCI_UHPI_BASE (0x01C67800) +#define DAVINCI_VPSS_REGS_BASE (0x01C70000) +#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01C80000) +#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01C81000) +#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01C82000) +#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01C84000) +#define DAVINCI_IMCOP_BASE (0x01CC0000) +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01E00000) +#define DAVINCI_VLYNQ_BASE (0x01E01000) +#define DAVINCI_MCBSP_BASE (0x01E02000) +#define DAVINCI_MMC_SD_BASE (0x01E10000) +#define DAVINCI_MS_BASE (0x01E20000) +#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000) +#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) +#define DAVINCI_VLYNQ_REMOTE_BASE (0x0C000000) /* @@ -91,14 +77,14 @@ extern "C" { * In case of only one VLYNQ IP, define only the * 'LOW_VLYNQ_CONTROL_BASE'. */ -#define LOW_VLYNQ_CONTROL_BASE DAVINCI_VLYNQ_BASE +#define LOW_VLYNQ_CONTROL_BASE DAVINCI_VLYNQ_BASE -#define DM365_EMAC_BASE (0x01D07000) -#define DM365_EMAC_CNTRL_OFFSET (0x0000) -#define DM365_EMAC_CNTRL_MOD_OFFSET (0x3000) -#define DM365_EMAC_CNTRL_RAM_OFFSET (0x1000) -#define DM365_EMAC_MDIO_OFFSET (0x4000) -#define DM365_EMAC_CNTRL_RAM_SIZE (0x2000) +#define DM365_EMAC_BASE (0x01D07000) +#define DM365_EMAC_CNTRL_OFFSET (0x0000) +#define DM365_EMAC_CNTRL_MOD_OFFSET (0x3000) +#define DM365_EMAC_CNTRL_RAM_OFFSET (0x1000) +#define DM365_EMAC_MDIO_OFFSET (0x4000) +#define DM365_EMAC_CNTRL_RAM_SIZE (0x2000) /* @@ -110,117 +96,117 @@ extern "C" { /* * System module registers */ -#define PINMUX0 (DAVINCI_SYSTEM_MODULE_BASE + 0x00) -#define PINMUX1 (DAVINCI_SYSTEM_MODULE_BASE + 0x04) -#define PINMUX2 (DAVINCI_SYSTEM_MODULE_BASE + 0x08) -#define PINMUX3 (DAVINCI_SYSTEM_MODULE_BASE + 0x0c) -#define PINMUX4 (DAVINCI_SYSTEM_MODULE_BASE + 0x10) +#define PINMUX0 (DAVINCI_SYSTEM_MODULE_BASE + 0x00) +#define PINMUX1 (DAVINCI_SYSTEM_MODULE_BASE + 0x04) +#define PINMUX2 (DAVINCI_SYSTEM_MODULE_BASE + 0x08) +#define PINMUX3 (DAVINCI_SYSTEM_MODULE_BASE + 0x0c) +#define PINMUX4 (DAVINCI_SYSTEM_MODULE_BASE + 0x10) -#define DM365_ARM_INTMUX (DAVINCI_SYSTEM_MODULE_BASE + 0x18) -#define DM365_EDMA_EVTMUX (DAVINCI_SYSTEM_MODULE_BASE + 0x1C) -#define DAVINCI_PUPDCTL1 (DAVINCI_SYSTEM_MODULE_BASE + 0x7C) +#define DM365_ARM_INTMUX (DAVINCI_SYSTEM_MODULE_BASE + 0x18) +#define DM365_EDMA_EVTMUX (DAVINCI_SYSTEM_MODULE_BASE + 0x1C) +#define DAVINCI_PUPDCTL1 (DAVINCI_SYSTEM_MODULE_BASE + 0x7C) -#define ASYNC_EMIF_REVID 0x00 -#define ASYNC_EMIF_AWCCR 0x04 -#define ASYNC_EMIF_A1CR 0x10 -#define ASYNC_EMIF_A2CR 0x14 -#define ASYNC_EMIF_A3CR 0x18 +#define ASYNC_EMIF_REVID 0x00 +#define ASYNC_EMIF_AWCCR 0x04 +#define ASYNC_EMIF_A1CR 0x10 +#define ASYNC_EMIF_A2CR 0x14 +#define ASYNC_EMIF_A3CR 0x18 /* * Base register addresses common across DM355 and DM365 */ -#define DM3XX_TIMER2_BASE (0x01C20800) -#define DM3XX_REALTIME_BASE (0x01C20C00) -#define DM3XX_PWM3_BASE (0x01C22C00) -#define DM3XX_SPI_BASE (0x01C66000) -#define DM3XX_SPI0_BASE DM3XX_SPI_BASE -#define DM3XX_SPI1_BASE (0x01C66800) -#define DM3XX_SPI2_BASE (0x01C67800) +#define DM3XX_TIMER2_BASE (0x01C20800) +#define DM3XX_REALTIME_BASE (0x01C20C00) +#define DM3XX_PWM3_BASE (0x01C22C00) +#define DM3XX_SPI_BASE (0x01C66000) +#define DM3XX_SPI0_BASE DM3XX_SPI_BASE +#define DM3XX_SPI1_BASE (0x01C66800) +#define DM3XX_SPI2_BASE (0x01C67800) /* * DM365 base register address */ -#define DM365_DMA_3PTC2_BASE (0x01C10800) -#define DM365_DMA_3PTC3_BASE (0x01C10C00) -#define DM365_TIMER3_BASE (0x01C23800) -#define DM365_ADCIF_BASE (0x01C23C00) -#define DM365_SPI3_BASE (0x01C68000) -#define DM365_SPI4_BASE (0x01C23000) -#define DM365_RTC_BASE (0x01C69000) -#define DM365_KEYSCAN_BASE (0x01C69400) -#define DM365_UHPI_BASE (0x01C69800) -#define DM365_IMCOP_BASE (0x01CA0000) -#define DM365_MMC_SD1_BASE (0x01D00000) -#define DM365_MCBSP_BASE (0x01D02000) -#define DM365_UART1_BASE (0x01D06000) -#define DM365_EMAC_CNTRL_BASE (0x01D07000) -#define DM365_EMAC_WRAP_RAM_BASE (0x01D08000) -#define DM365_EMAC_WRAP_CNTRL_BASE (0x01D0A000) -#define DM365_EMAC_MDIO_BASE (0x01D0B000) -#define DM365_VOICE_CODEC_BASE (0x01D0C000) -#define DM365_ASYNC_EMIF_CNTRL_BASE (0x01D10000) -#define DM365_MMC_SD0_BASE (0x01D11000) -#define DM365_MS_BASE (0x01D20000) -#define DM365_KALEIDO_BASE (0x01E00000) +#define DM365_DMA_3PTC2_BASE (0x01C10800) +#define DM365_DMA_3PTC3_BASE (0x01C10C00) +#define DM365_TIMER3_BASE (0x01C23800) +#define DM365_ADCIF_BASE (0x01C23C00) +#define DM365_SPI3_BASE (0x01C68000) +#define DM365_SPI4_BASE (0x01C23000) +#define DM365_RTC_BASE (0x01C69000) +#define DM365_KEYSCAN_BASE (0x01C69400) +#define DM365_UHPI_BASE (0x01C69800) +#define DM365_IMCOP_BASE (0x01CA0000) +#define DM365_MMC_SD1_BASE (0x01D00000) +#define DM365_MCBSP_BASE (0x01D02000) +#define DM365_UART1_BASE (0x01D06000) +#define DM365_EMAC_CNTRL_BASE (0x01D07000) +#define DM365_EMAC_WRAP_RAM_BASE (0x01D08000) +#define DM365_EMAC_WRAP_CNTRL_BASE (0x01D0A000) +#define DM365_EMAC_MDIO_BASE (0x01D0B000) +#define DM365_VOICE_CODEC_BASE (0x01D0C000) +#define DM365_ASYNC_EMIF_CNTRL_BASE (0x01D10000) +#define DM365_MMC_SD0_BASE (0x01D11000) +#define DM365_MS_BASE (0x01D20000) +#define DM365_KALEIDO_BASE (0x01E00000) -#define DAVINCI_UART0_BASE (0x01C20000) +#define DAVINCI_UART0_BASE (0x01C20000) -#define PSC_MDCTL_BASE (0x01c41a00) -#define PSC_MDSTAT_BASE (0x01c41800) -#define PSC_PTCMD (0x01c41120) -#define PSC_PTSTAT (0x01c41128) +#define PSC_MDCTL_BASE (0x01c41a00) +#define PSC_MDSTAT_BASE (0x01c41800) +#define PSC_PTCMD (0x01c41120) +#define PSC_PTSTAT (0x01c41128) -#define DM365_EINT_ENABLE0 0x01c48018 -#define DM365_EINT_ENABLE1 0x01c4801c +#define DM365_EINT_ENABLE0 0x01c48018 +#define DM365_EINT_ENABLE1 0x01c4801c -#define davinci_readb(a) (*(volatile unsigned char *)(a)) -#define davinci_readw(a) (*(volatile unsigned short *)(a)) -#define davinci_readl(a) (*(volatile unsigned int *)(a)) +#define davinci_readb(a) (*(volatile unsigned char *)(a)) +#define davinci_readw(a) (*(volatile unsigned short *)(a)) +#define davinci_readl(a) (*(volatile unsigned int *)(a)) -#define davinci_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define davinci_writew(v,a) (*(volatile unsigned short *)(a) = (v)) -#define davinci_writel(v,a) (*(volatile unsigned int *)(a) = (v)) +#define davinci_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define davinci_writew(v,a) (*(volatile unsigned short *)(a) = (v)) +#define davinci_writel(v,a) (*(volatile unsigned int *)(a) = (v)) -#define readb(a) davinci_readb(a) -#define readw(a) davinci_readw(a) -#define readl(a) davinci_readl(a) +#define readb(a) davinci_readb(a) +#define readw(a) davinci_readw(a) +#define readl(a) davinci_readl(a) -#define write(v,a) davinci_writeb(v,a) -#define writew(v,a) davinci_writew(v,a) -#define writel(v,a) davinci_writel(v,a) +#define write(v,a) davinci_writeb(v,a) +#define writew(v,a) davinci_writew(v,a) +#define writel(v,a) davinci_writel(v,a) /* define timer register struct*/ typedef struct timer_regs_s { - rt_uint32_t pid12; /* 0x0 */ - rt_uint32_t emumgt_clksped; /* 0x4 */ - rt_uint32_t gpint_en; /* 0x8 */ - rt_uint32_t gpdir_dat; /* 0xC */ - rt_uint32_t tim12; /* 0x10 */ - rt_uint32_t tim34; /* 0x14 */ - rt_uint32_t prd12; /* 0x18 */ - rt_uint32_t prd34; /* 0x1C */ - rt_uint32_t tcr; /* 0x20 */ - rt_uint32_t tgcr; /* 0x24 */ - rt_uint32_t wdtcr; /* 0x28 */ - rt_uint32_t tlgc; /* 0x2C */ - rt_uint32_t tlmr; /* 0x30 */ + rt_uint32_t pid12; /* 0x0 */ + rt_uint32_t emumgt_clksped; /* 0x4 */ + rt_uint32_t gpint_en; /* 0x8 */ + rt_uint32_t gpdir_dat; /* 0xC */ + rt_uint32_t tim12; /* 0x10 */ + rt_uint32_t tim34; /* 0x14 */ + rt_uint32_t prd12; /* 0x18 */ + rt_uint32_t prd34; /* 0x1C */ + rt_uint32_t tcr; /* 0x20 */ + rt_uint32_t tgcr; /* 0x24 */ + rt_uint32_t wdtcr; /* 0x28 */ + rt_uint32_t tlgc; /* 0x2C */ + rt_uint32_t tlmr; /* 0x30 */ } timer_regs_t; /*****************************/ /* CPU Mode */ /*****************************/ -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define ABORTMODE 0x17 +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 struct rt_hw_register { diff --git a/bsp/dm365/platform/dma.c b/bsp/dm365/platform/dma.c index 2acf572f49..baaedf650a 100644 --- a/bsp/dm365/platform/dma.c +++ b/bsp/dm365/platform/dma.c @@ -1,113 +1,99 @@ /* - * File : dma.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ #include /* Offsets matching "struct edmacc_param" */ -#define PARM_OPT 0x00 -#define PARM_SRC 0x04 -#define PARM_A_B_CNT 0x08 -#define PARM_DST 0x0c -#define PARM_SRC_DST_BIDX 0x10 -#define PARM_LINK_BCNTRLD 0x14 -#define PARM_SRC_DST_CIDX 0x18 -#define PARM_CCNT 0x1c +#define PARM_OPT 0x00 +#define PARM_SRC 0x04 +#define PARM_A_B_CNT 0x08 +#define PARM_DST 0x0c +#define PARM_SRC_DST_BIDX 0x10 +#define PARM_LINK_BCNTRLD 0x14 +#define PARM_SRC_DST_CIDX 0x18 +#define PARM_CCNT 0x1c -#define PARM_SIZE 0x20 +#define PARM_SIZE 0x20 /* Offsets for EDMA CC global channel registers and their shadows */ -#define SH_ER 0x00 /* 64 bits */ -#define SH_ECR 0x08 /* 64 bits */ -#define SH_ESR 0x10 /* 64 bits */ -#define SH_CER 0x18 /* 64 bits */ -#define SH_EER 0x20 /* 64 bits */ -#define SH_EECR 0x28 /* 64 bits */ -#define SH_EESR 0x30 /* 64 bits */ -#define SH_SER 0x38 /* 64 bits */ -#define SH_SECR 0x40 /* 64 bits */ -#define SH_IER 0x50 /* 64 bits */ -#define SH_IECR 0x58 /* 64 bits */ -#define SH_IESR 0x60 /* 64 bits */ -#define SH_IPR 0x68 /* 64 bits */ -#define SH_ICR 0x70 /* 64 bits */ -#define SH_IEVAL 0x78 -#define SH_QER 0x80 -#define SH_QEER 0x84 -#define SH_QEECR 0x88 -#define SH_QEESR 0x8c -#define SH_QSER 0x90 -#define SH_QSECR 0x94 -#define SH_SIZE 0x200 +#define SH_ER 0x00 /* 64 bits */ +#define SH_ECR 0x08 /* 64 bits */ +#define SH_ESR 0x10 /* 64 bits */ +#define SH_CER 0x18 /* 64 bits */ +#define SH_EER 0x20 /* 64 bits */ +#define SH_EECR 0x28 /* 64 bits */ +#define SH_EESR 0x30 /* 64 bits */ +#define SH_SER 0x38 /* 64 bits */ +#define SH_SECR 0x40 /* 64 bits */ +#define SH_IER 0x50 /* 64 bits */ +#define SH_IECR 0x58 /* 64 bits */ +#define SH_IESR 0x60 /* 64 bits */ +#define SH_IPR 0x68 /* 64 bits */ +#define SH_ICR 0x70 /* 64 bits */ +#define SH_IEVAL 0x78 +#define SH_QER 0x80 +#define SH_QEER 0x84 +#define SH_QEECR 0x88 +#define SH_QEESR 0x8c +#define SH_QSER 0x90 +#define SH_QSECR 0x94 +#define SH_SIZE 0x200 /* Offsets for EDMA CC global registers */ -#define EDMA_REV 0x0000 -#define EDMA_CCCFG 0x0004 -#define EDMA_QCHMAP 0x0200 /* 8 registers */ -#define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */ -#define EDMA_QDMAQNUM 0x0260 -#define EDMA_QUETCMAP 0x0280 -#define EDMA_QUEPRI 0x0284 -#define EDMA_EMR 0x0300 /* 64 bits */ -#define EDMA_EMCR 0x0308 /* 64 bits */ -#define EDMA_QEMR 0x0310 -#define EDMA_QEMCR 0x0314 -#define EDMA_CCERR 0x0318 -#define EDMA_CCERRCLR 0x031c -#define EDMA_EEVAL 0x0320 -#define EDMA_DRAE 0x0340 /* 4 x 64 bits*/ -#define EDMA_QRAE 0x0380 /* 4 registers */ -#define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */ -#define EDMA_QSTAT 0x0600 /* 2 registers */ -#define EDMA_QWMTHRA 0x0620 -#define EDMA_QWMTHRB 0x0624 -#define EDMA_CCSTAT 0x0640 +#define EDMA_REV 0x0000 +#define EDMA_CCCFG 0x0004 +#define EDMA_QCHMAP 0x0200 /* 8 registers */ +#define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */ +#define EDMA_QDMAQNUM 0x0260 +#define EDMA_QUETCMAP 0x0280 +#define EDMA_QUEPRI 0x0284 +#define EDMA_EMR 0x0300 /* 64 bits */ +#define EDMA_EMCR 0x0308 /* 64 bits */ +#define EDMA_QEMR 0x0310 +#define EDMA_QEMCR 0x0314 +#define EDMA_CCERR 0x0318 +#define EDMA_CCERRCLR 0x031c +#define EDMA_EEVAL 0x0320 +#define EDMA_DRAE 0x0340 /* 4 x 64 bits*/ +#define EDMA_QRAE 0x0380 /* 4 registers */ +#define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */ +#define EDMA_QSTAT 0x0600 /* 2 registers */ +#define EDMA_QWMTHRA 0x0620 +#define EDMA_QWMTHRB 0x0624 +#define EDMA_CCSTAT 0x0640 -#define EDMA_M 0x1000 /* global channel registers */ -#define EDMA_ECR 0x1008 -#define EDMA_ECRH 0x100C -#define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */ -#define EDMA_PARM 0x4000 /* 128 param entries */ +#define EDMA_M 0x1000 /* global channel registers */ +#define EDMA_ECR 0x1008 +#define EDMA_ECRH 0x100C +#define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */ +#define EDMA_PARM 0x4000 /* 128 param entries */ -#define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5)) +#define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5)) -#define EDMA_DCHMAP 0x0100 /* 64 registers */ -#define CHMAP_EXIST BIT(24) +#define EDMA_DCHMAP 0x0100 /* 64 registers */ +#define CHMAP_EXIST BIT(24) #define EDMA_MAX_DMACH 64 #define EDMA_MAX_PARAMENTRY 512 -#define EDMA_CC0_BASE_REG 0x01c00000 -#define EDMA_TC0_BASE_REG 0x01c10000 -#define EDMA_TC1_BASE_REG 0x01c10400 -#define EDMA_TC2_BASE_REG 0x01c10800 -#define EDMA_TC3_BASE_REG 0x01c10c00 +#define EDMA_CC0_BASE_REG 0x01c00000 +#define EDMA_TC0_BASE_REG 0x01c10000 +#define EDMA_TC1_BASE_REG 0x01c10400 +#define EDMA_TC2_BASE_REG 0x01c10800 +#define EDMA_TC3_BASE_REG 0x01c10c00 -#define min_t(type, x, y) ({ \ - type __min1 = (x); \ - type __min2 = (y); \ - __min1 < __min2 ? __min1: __min2; }) +#define min_t(type, x, y) ({ \ + type __min1 = (x); \ + type __min2 = (y); \ + __min1 < __min2 ? __min1: __min2; }) @@ -117,130 +103,130 @@ static void volatile *edmacc_regs_base[EDMA_MAX_CC]; static inline unsigned int edma_read(unsigned ctlr, int offset) { - return (unsigned int)davinci_readl(edmacc_regs_base[ctlr] + offset); + return (unsigned int)davinci_readl(edmacc_regs_base[ctlr] + offset); } static inline void edma_write(unsigned ctlr, int offset, int val) { - davinci_writel(val, edmacc_regs_base[ctlr] + offset); + davinci_writel(val, edmacc_regs_base[ctlr] + offset); } static inline void edma_modify(unsigned ctlr, int offset, unsigned and, - unsigned or) + unsigned or) { - unsigned val = edma_read(ctlr, offset); - val &= and; - val |= or; - edma_write(ctlr, offset, val); + unsigned val = edma_read(ctlr, offset); + val &= and; + val |= or; + edma_write(ctlr, offset, val); } static inline void edma_and(unsigned ctlr, int offset, unsigned and) { - unsigned val = edma_read(ctlr, offset); - val &= and; - edma_write(ctlr, offset, val); + unsigned val = edma_read(ctlr, offset); + val &= and; + edma_write(ctlr, offset, val); } static inline void edma_or(unsigned ctlr, int offset, unsigned or) { - unsigned val = edma_read(ctlr, offset); - val |= or; - edma_write(ctlr, offset, val); + unsigned val = edma_read(ctlr, offset); + val |= or; + edma_write(ctlr, offset, val); } static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i) { - return edma_read(ctlr, offset + (i << 2)); + return edma_read(ctlr, offset + (i << 2)); } static inline void edma_write_array(unsigned ctlr, int offset, int i, - unsigned val) + unsigned val) { - edma_write(ctlr, offset + (i << 2), val); + edma_write(ctlr, offset + (i << 2), val); } static inline void edma_modify_array(unsigned ctlr, int offset, int i, - unsigned and, unsigned or) + unsigned and, unsigned or) { - edma_modify(ctlr, offset + (i << 2), and, or); + edma_modify(ctlr, offset + (i << 2), and, or); } static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or) { - edma_or(ctlr, offset + (i << 2), or); + edma_or(ctlr, offset + (i << 2), or); } static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j, - unsigned or) + unsigned or) { - edma_or(ctlr, offset + ((i*2 + j) << 2), or); + edma_or(ctlr, offset + ((i*2 + j) << 2), or); } static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j, - unsigned val) + unsigned val) { - edma_write(ctlr, offset + ((i*2 + j) << 2), val); + edma_write(ctlr, offset + ((i*2 + j) << 2), val); } static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset) { - return edma_read(ctlr, EDMA_SHADOW0 + offset); + return edma_read(ctlr, EDMA_SHADOW0 + offset); } static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset, - int i) + int i) { - return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2)); + return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2)); } static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val) { - edma_write(ctlr, EDMA_SHADOW0 + offset, val); + edma_write(ctlr, EDMA_SHADOW0 + offset, val); } static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i, - unsigned val) + unsigned val) { - edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val); + edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val); } static inline unsigned int edma_parm_read(unsigned ctlr, int offset, - int param_no) + int param_no) { - return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5)); + return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5)); } static inline void edma_parm_write(unsigned ctlr, int offset, int param_no, - unsigned val) + unsigned val) { - edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val); + edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val); } static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no, - unsigned and, unsigned or) + unsigned and, unsigned or) { - edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or); + edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or); } static inline void edma_parm_and(unsigned ctlr, int offset, int param_no, - unsigned and) + unsigned and) { - edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and); + edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and); } static inline void edma_parm_or(unsigned ctlr, int offset, int param_no, - unsigned or) + unsigned or) { - edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or); + edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or); } #if 0 static inline void set_bits(int offset, int len, unsigned long *p) { - for (; len > 0; len--) - set_bit(offset + (len - 1), p); + for (; len > 0; len--) + set_bit(offset + (len - 1), p); } static inline void clear_bits(int offset, int len, unsigned long *p) { - for (; len > 0; len--) - clear_bit(offset + (len - 1), p); + for (; len > 0; len--) + clear_bit(offset + (len - 1), p); } #endif /*****************************************************************************/ -#define BIT(nr) (1UL << (nr)) +#define BIT(nr) (1UL << (nr)) #define BITS_PER_LONG 32 -#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) -#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) -#define BITS_PER_BYTE 8 +#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) +#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) +#define BITS_PER_BYTE 8 #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) -#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) +#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) #define DECLARE_BITMAP(name,bits) \ - unsigned long name[BITS_TO_LONGS(bits)] + unsigned long name[BITS_TO_LONGS(bits)] /** * test_bit - Determine whether a bit is set @@ -249,44 +235,44 @@ static inline void clear_bits(int offset, int len, unsigned long *p) */ static inline int test_bit(int nr, const volatile unsigned long *addr) { - return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1))); + return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1))); } static inline void clear_bit(int nr, volatile unsigned long *addr) { - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - rt_base_t level; + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + rt_base_t level; - level = rt_hw_interrupt_disable(); - *p &= ~mask; - rt_hw_interrupt_enable(level); + level = rt_hw_interrupt_disable(); + *p &= ~mask; + rt_hw_interrupt_enable(level); } static inline int test_and_set_bit(int nr, volatile unsigned long *addr) { - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long old; - rt_base_t level; + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old; + rt_base_t level; - level = rt_hw_interrupt_disable(); - old = *p; - *p = old | mask; - rt_hw_interrupt_enable(level); + level = rt_hw_interrupt_disable(); + old = *p; + *p = old | mask; + rt_hw_interrupt_enable(level); - return (old & mask) != 0; + return (old & mask) != 0; } static inline void set_bit(int nr, volatile unsigned long *addr) { - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - rt_base_t level; + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + rt_base_t level; - level = rt_hw_interrupt_disable(); - *p |= mask; - rt_hw_interrupt_enable(level); + level = rt_hw_interrupt_disable(); + *p |= mask; + rt_hw_interrupt_enable(level); } /* @@ -300,45 +286,45 @@ extern int _find_next_bit_le(const unsigned long *p, int size, int offset); /* * These are the little endian, atomic definitions. */ -#define find_first_zero_bit(p,sz) _find_first_zero_bit_le(p,sz) -#define find_next_zero_bit(p,sz,off) _find_next_zero_bit_le(p,sz,off) -#define find_first_bit(p,sz) _find_first_bit_le(p,sz) -#define find_next_bit(p,sz,off) _find_next_bit_le(p,sz,off) +#define find_first_zero_bit(p,sz) _find_first_zero_bit_le(p,sz) +#define find_next_zero_bit(p,sz,off) _find_next_zero_bit_le(p,sz,off) +#define find_first_bit(p,sz) _find_first_bit_le(p,sz) +#define find_next_bit(p,sz,off) _find_next_bit_le(p,sz,off) /* actual number of DMA channels and slots on this silicon */ struct edma { - /* how many dma resources of each type */ - unsigned num_channels; - unsigned num_region; - unsigned num_slots; - unsigned num_tc; - unsigned num_cc; - enum dma_event_q default_queue; + /* how many dma resources of each type */ + unsigned num_channels; + unsigned num_region; + unsigned num_slots; + unsigned num_tc; + unsigned num_cc; + enum dma_event_q default_queue; - /* list of channels with no even trigger; terminated by "-1" */ - const rt_int8_t *noevent; + /* list of channels with no even trigger; terminated by "-1" */ + const rt_int8_t *noevent; - /* The edma_inuse bit for each PaRAM slot is clear unless the - * channel is in use ... by ARM or DSP, for QDMA, or whatever. - */ - DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY); + /* The edma_inuse bit for each PaRAM slot is clear unless the + * channel is in use ... by ARM or DSP, for QDMA, or whatever. + */ + DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY); - /* The edma_unused bit for each channel is clear unless - * it is not being used on this platform. It uses a bit - * of SOC-specific initialization code. - */ - DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH); + /* The edma_unused bit for each channel is clear unless + * it is not being used on this platform. It uses a bit + * of SOC-specific initialization code. + */ + DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH); - unsigned irq_res_start; - unsigned irq_res_end; + unsigned irq_res_start; + unsigned irq_res_end; - struct dma_interrupt_data { - void (*callback)(unsigned channel, unsigned short ch_status, - void *data); - void *data; - } intr_data[EDMA_MAX_DMACH]; + struct dma_interrupt_data { + void (*callback)(unsigned channel, unsigned short ch_status, + void *data); + void *data; + } intr_data[EDMA_MAX_DMACH]; }; static struct edma *edma_cc[EDMA_MAX_CC]; @@ -346,38 +332,38 @@ static int arch_num_cc; /* dummy param set used to (re)initialize parameter RAM slots */ static const struct edmacc_param dummy_paramset = { - .link_bcntrld = 0xffff, - .ccnt = 1, + .link_bcntrld = 0xffff, + .ccnt = 1, }; /*****************************************************************************/ static void map_dmach_queue(unsigned ctlr, unsigned ch_no, - enum dma_event_q queue_no) + enum dma_event_q queue_no) { - int bit = (ch_no & 0x7) * 4; + int bit = (ch_no & 0x7) * 4; - /* default to low priority queue */ - if (queue_no == EVENTQ_DEFAULT) - queue_no = edma_cc[ctlr]->default_queue; + /* default to low priority queue */ + if (queue_no == EVENTQ_DEFAULT) + queue_no = edma_cc[ctlr]->default_queue; - queue_no &= 7; - edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3), - ~(0x7 << bit), queue_no << bit); + queue_no &= 7; + edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3), + ~(0x7 << bit), queue_no << bit); } static void map_queue_tc(unsigned ctlr, int queue_no, int tc_no) { - int bit = queue_no * 4; - edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit)); + int bit = queue_no * 4; + edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit)); } static void assign_priority_to_queue(unsigned ctlr, int queue_no, - int priority) + int priority) { - int bit = queue_no * 4; - edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit), - ((priority & 0x7) << bit)); + int bit = queue_no * 4; + edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit), + ((priority & 0x7) << bit)); } /** @@ -393,45 +379,45 @@ static void assign_priority_to_queue(unsigned ctlr, int queue_no, */ static void map_dmach_param(unsigned ctlr) { - int i; - for (i = 0; i < EDMA_MAX_DMACH; i++) - edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5)); + int i; + for (i = 0; i < EDMA_MAX_DMACH; i++) + edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5)); } static inline void setup_dma_interrupt(unsigned lch, - void (*callback)(unsigned channel, rt_uint16_t ch_status, void *data), - void *data) + void (*callback)(unsigned channel, rt_uint16_t ch_status, void *data), + void *data) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(lch); - lch = EDMA_CHAN_SLOT(lch); + ctlr = EDMA_CTLR(lch); + lch = EDMA_CHAN_SLOT(lch); - if (!callback) - edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5, - BIT(lch & 0x1f)); + if (!callback) + edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5, + BIT(lch & 0x1f)); - edma_cc[ctlr]->intr_data[lch].callback = callback; - edma_cc[ctlr]->intr_data[lch].data = data; + edma_cc[ctlr]->intr_data[lch].callback = callback; + edma_cc[ctlr]->intr_data[lch].data = data; - if (callback) { - edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5, - BIT(lch & 0x1f)); - edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5, - BIT(lch & 0x1f)); - } + if (callback) { + edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5, + BIT(lch & 0x1f)); + edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5, + BIT(lch & 0x1f)); + } } static int irq2ctlr(int irq) { - if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end) - return 0; - else if (irq >= edma_cc[1]->irq_res_start && - irq <= edma_cc[1]->irq_res_end) - return 1; + if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end) + return 0; + else if (irq >= edma_cc[1]->irq_res_start && + irq <= edma_cc[1]->irq_res_end) + return 1; - return -1; + return -1; } /****************************************************************************** @@ -441,53 +427,53 @@ static int irq2ctlr(int irq) *****************************************************************************/ static void dma_irq_handler(int irq, void *data) { - int i; - int ctlr; - unsigned int cnt = 0; + int i; + int ctlr; + unsigned int cnt = 0; - ctlr = irq2ctlr(irq); - if (ctlr < 0) - return ; + ctlr = irq2ctlr(irq); + if (ctlr < 0) + return ; - edma_dbg("dma_irq_handler\n"); + edma_dbg("dma_irq_handler\n"); - if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0) && - (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0)) - return ; + if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0) && + (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0)) + return ; - while (1) { - int j; - if (edma_shadow0_read_array(ctlr, SH_IPR, 0) & - edma_shadow0_read_array(ctlr, SH_IER, 0)) - j = 0; - else if (edma_shadow0_read_array(ctlr, SH_IPR, 1) & - edma_shadow0_read_array(ctlr, SH_IER, 1)) - j = 1; - else - break; - edma_dbg("IPR%d %08x\n", j, - edma_shadow0_read_array(ctlr, SH_IPR, j)); - for (i = 0; i < 32; i++) { - int k = (j << 5) + i; - if ((edma_shadow0_read_array(ctlr, SH_IPR, j) & BIT(i)) - && (edma_shadow0_read_array(ctlr, - SH_IER, j) & BIT(i))) { - /* Clear the corresponding IPR bits */ - edma_shadow0_write_array(ctlr, SH_ICR, j, - BIT(i)); - if (edma_cc[ctlr]->intr_data[k].callback) - edma_cc[ctlr]->intr_data[k].callback( - k, DMA_COMPLETE, - edma_cc[ctlr]->intr_data[k]. - data); - } - } - cnt++; - if (cnt > 10) - break; - } - edma_shadow0_write(ctlr, SH_IEVAL, 1); - return ; + while (1) { + int j; + if (edma_shadow0_read_array(ctlr, SH_IPR, 0) & + edma_shadow0_read_array(ctlr, SH_IER, 0)) + j = 0; + else if (edma_shadow0_read_array(ctlr, SH_IPR, 1) & + edma_shadow0_read_array(ctlr, SH_IER, 1)) + j = 1; + else + break; + edma_dbg("IPR%d %08x\n", j, + edma_shadow0_read_array(ctlr, SH_IPR, j)); + for (i = 0; i < 32; i++) { + int k = (j << 5) + i; + if ((edma_shadow0_read_array(ctlr, SH_IPR, j) & BIT(i)) + && (edma_shadow0_read_array(ctlr, + SH_IER, j) & BIT(i))) { + /* Clear the corresponding IPR bits */ + edma_shadow0_write_array(ctlr, SH_ICR, j, + BIT(i)); + if (edma_cc[ctlr]->intr_data[k].callback) + edma_cc[ctlr]->intr_data[k].callback( + k, DMA_COMPLETE, + edma_cc[ctlr]->intr_data[k]. + data); + } + } + cnt++; + if (cnt > 10) + break; + } + edma_shadow0_write(ctlr, SH_IEVAL, 1); + return ; } /****************************************************************************** @@ -497,90 +483,90 @@ static void dma_irq_handler(int irq, void *data) *****************************************************************************/ static void dma_ccerr_handler(int irq, void *data) { - int i; - int ctlr; - unsigned int cnt = 0; + int i; + int ctlr; + unsigned int cnt = 0; - ctlr = irq2ctlr(irq); - if (ctlr < 0) - return ; + ctlr = irq2ctlr(irq); + if (ctlr < 0) + return ; - edma_dbg("dma_ccerr_handler\n"); + edma_dbg("dma_ccerr_handler\n"); - if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && - (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && - (edma_read(ctlr, EDMA_QEMR) == 0) && - (edma_read(ctlr, EDMA_CCERR) == 0)) - return ; + if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && + (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && + (edma_read(ctlr, EDMA_QEMR) == 0) && + (edma_read(ctlr, EDMA_CCERR) == 0)) + return ; - while (1) { - int j = -1; - if (edma_read_array(ctlr, EDMA_EMR, 0)) - j = 0; - else if (edma_read_array(ctlr, EDMA_EMR, 1)) - j = 1; - if (j >= 0) { - edma_dbg("EMR%d %08x\n", j, - edma_read_array(ctlr, EDMA_EMR, j)); - for (i = 0; i < 32; i++) { - int k = (j << 5) + i; - if (edma_read_array(ctlr, EDMA_EMR, j) & - BIT(i)) { - /* Clear the corresponding EMR bits */ - edma_write_array(ctlr, EDMA_EMCR, j, - BIT(i)); - /* Clear any SER */ - edma_shadow0_write_array(ctlr, SH_SECR, - j, BIT(i)); - if (edma_cc[ctlr]->intr_data[k]. - callback) { - edma_cc[ctlr]->intr_data[k]. - callback(k, - DMA_CC_ERROR, - edma_cc[ctlr]->intr_data - [k].data); - } - } - } - } else if (edma_read(ctlr, EDMA_QEMR)) { - edma_dbg("QEMR %02x\n", - edma_read(ctlr, EDMA_QEMR)); - for (i = 0; i < 8; i++) { - if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) { - /* Clear the corresponding IPR bits */ - edma_write(ctlr, EDMA_QEMCR, BIT(i)); - edma_shadow0_write(ctlr, SH_QSECR, - BIT(i)); + while (1) { + int j = -1; + if (edma_read_array(ctlr, EDMA_EMR, 0)) + j = 0; + else if (edma_read_array(ctlr, EDMA_EMR, 1)) + j = 1; + if (j >= 0) { + edma_dbg("EMR%d %08x\n", j, + edma_read_array(ctlr, EDMA_EMR, j)); + for (i = 0; i < 32; i++) { + int k = (j << 5) + i; + if (edma_read_array(ctlr, EDMA_EMR, j) & + BIT(i)) { + /* Clear the corresponding EMR bits */ + edma_write_array(ctlr, EDMA_EMCR, j, + BIT(i)); + /* Clear any SER */ + edma_shadow0_write_array(ctlr, SH_SECR, + j, BIT(i)); + if (edma_cc[ctlr]->intr_data[k]. + callback) { + edma_cc[ctlr]->intr_data[k]. + callback(k, + DMA_CC_ERROR, + edma_cc[ctlr]->intr_data + [k].data); + } + } + } + } else if (edma_read(ctlr, EDMA_QEMR)) { + edma_dbg("QEMR %02x\n", + edma_read(ctlr, EDMA_QEMR)); + for (i = 0; i < 8; i++) { + if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) { + /* Clear the corresponding IPR bits */ + edma_write(ctlr, EDMA_QEMCR, BIT(i)); + edma_shadow0_write(ctlr, SH_QSECR, + BIT(i)); - /* NOTE: not reported!! */ - } - } - } else if (edma_read(ctlr, EDMA_CCERR)) { - edma_dbg("CCERR %08x\n", - edma_read(ctlr, EDMA_CCERR)); - /* FIXME: CCERR.BIT(16) ignored! much better - * to just write CCERRCLR with CCERR value... - */ - for (i = 0; i < 8; i++) { - if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) { - /* Clear the corresponding IPR bits */ - edma_write(ctlr, EDMA_CCERRCLR, BIT(i)); + /* NOTE: not reported!! */ + } + } + } else if (edma_read(ctlr, EDMA_CCERR)) { + edma_dbg("CCERR %08x\n", + edma_read(ctlr, EDMA_CCERR)); + /* FIXME: CCERR.BIT(16) ignored! much better + * to just write CCERRCLR with CCERR value... + */ + for (i = 0; i < 8; i++) { + if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) { + /* Clear the corresponding IPR bits */ + edma_write(ctlr, EDMA_CCERRCLR, BIT(i)); - /* NOTE: not reported!! */ - } - } - } - if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && - (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && - (edma_read(ctlr, EDMA_QEMR) == 0) && - (edma_read(ctlr, EDMA_CCERR) == 0)) - break; - cnt++; - if (cnt > 10) - break; - } - edma_write(ctlr, EDMA_EEVAL, 1); - return ; + /* NOTE: not reported!! */ + } + } + } + if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && + (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && + (edma_read(ctlr, EDMA_QEMR) == 0) && + (edma_read(ctlr, EDMA_CCERR) == 0)) + break; + cnt++; + if (cnt > 10) + break; + } + edma_write(ctlr, EDMA_EEVAL, 1); + return ; } /****************************************************************************** @@ -589,92 +575,92 @@ static void dma_ccerr_handler(int irq, void *data) * *****************************************************************************/ -#define tc_errs_handled RT_FALSE/* disabled as long as they're NOPs */ +#define tc_errs_handled RT_FALSE/* disabled as long as they're NOPs */ static void dma_tc0err_handler(int irq, void *data) { - edma_dbg("dma_tc0err_handler\n"); - return ; + edma_dbg("dma_tc0err_handler\n"); + return ; } static void dma_tc1err_handler(int irq, void *data) { - edma_dbg("dma_tc1err_handler\n"); - return ; + edma_dbg("dma_tc1err_handler\n"); + return ; } static int reserve_contiguous_slots(int ctlr, unsigned int id, - unsigned int num_slots, - unsigned int start_slot) + unsigned int num_slots, + unsigned int start_slot) { - int i, j; - unsigned int count = num_slots; - int stop_slot = start_slot; - DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY); + int i, j; + unsigned int count = num_slots; + int stop_slot = start_slot; + DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY); - for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) { - j = EDMA_CHAN_SLOT(i); - if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) { - /* Record our current beginning slot */ - if (count == num_slots) - stop_slot = i; + for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) { + j = EDMA_CHAN_SLOT(i); + if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) { + /* Record our current beginning slot */ + if (count == num_slots) + stop_slot = i; - count--; - set_bit(j, tmp_inuse); + count--; + set_bit(j, tmp_inuse); - if (count == 0) - break; - } else { - clear_bit(j, tmp_inuse); + if (count == 0) + break; + } else { + clear_bit(j, tmp_inuse); - if (id == EDMA_CONT_PARAMS_FIXED_EXACT) { - stop_slot = i; - break; - } else { - count = num_slots; - } - } - } + if (id == EDMA_CONT_PARAMS_FIXED_EXACT) { + stop_slot = i; + break; + } else { + count = num_slots; + } + } + } - /* - * We have to clear any bits that we set - * if we run out parameter RAM slots, i.e we do find a set - * of contiguous parameter RAM slots but do not find the exact number - * requested as we may reach the total number of parameter RAM slots - */ - if (i == edma_cc[ctlr]->num_slots) - stop_slot = i; + /* + * We have to clear any bits that we set + * if we run out parameter RAM slots, i.e we do find a set + * of contiguous parameter RAM slots but do not find the exact number + * requested as we may reach the total number of parameter RAM slots + */ + if (i == edma_cc[ctlr]->num_slots) + stop_slot = i; - for (j = start_slot; j < stop_slot; j++) - if (test_bit(j, tmp_inuse)) - clear_bit(j, edma_cc[ctlr]->edma_inuse); + for (j = start_slot; j < stop_slot; j++) + if (test_bit(j, tmp_inuse)) + clear_bit(j, edma_cc[ctlr]->edma_inuse); - if (count) - return -RT_EBUSY; + if (count) + return -RT_EBUSY; - for (j = i - num_slots + 1; j <= i; ++j) - rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(j)), - &dummy_paramset, PARM_SIZE); + for (j = i - num_slots + 1; j <= i; ++j) + rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(j)), + &dummy_paramset, PARM_SIZE); - return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1); + return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1); } #if 0 static int prepare_unused_channel_list(struct device *dev, void *data) { - struct platform_device *pdev = to_platform_device(dev); - int i, ctlr; + struct platform_device *pdev = to_platform_device(dev); + int i, ctlr; - for (i = 0; i < pdev->num_resources; i++) { - if ((pdev->resource[i].flags & IORESOURCE_DMA) && - (int)pdev->resource[i].start >= 0) { - ctlr = EDMA_CTLR(pdev->resource[i].start); - clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start), - edma_cc[ctlr]->edma_unused); - } - } + for (i = 0; i < pdev->num_resources; i++) { + if ((pdev->resource[i].flags & IORESOURCE_DMA) && + (int)pdev->resource[i].start >= 0) { + ctlr = EDMA_CTLR(pdev->resource[i].start); + clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start), + edma_cc[ctlr]->edma_unused); + } + } - return 0; + return 0; } #endif @@ -690,8 +676,8 @@ static rt_bool_t unused_chan_list_done; * @callback: optional; to be issued on DMA completion or errors * @data: passed to callback * @eventq_no: an EVENTQ_* constant, used to choose which Transfer - * Controller (TC) executes requests using this channel. Use - * EVENTQ_DEFAULT unless you really need a high priority queue. + * Controller (TC) executes requests using this channel. Use + * EVENTQ_DEFAULT unless you really need a high priority queue. * * This allocates a DMA channel and its associated parameter RAM slot. * The parameter RAM is initialized to hold a dummy transfer. @@ -715,77 +701,77 @@ static rt_bool_t unused_chan_list_done; * Returns the number of the channel, else negative errno. */ int edma_alloc_channel(int channel, - void (*callback)(unsigned channel, rt_uint16_t ch_status, void *data), - void *data, - enum dma_event_q eventq_no) + void (*callback)(unsigned channel, rt_uint16_t ch_status, void *data), + void *data, + enum dma_event_q eventq_no) { - unsigned i, done = 0, ctlr = 0; - int ret = 0; + unsigned i, done = 0, ctlr = 0; + int ret = 0; #if 0 - if (!unused_chan_list_done) { - /* - * Scan all the platform devices to find out the EDMA channels - * used and clear them in the unused list, making the rest - * available for ARM usage. - */ - ret = bus_for_each_dev(&platform_bus_type, NULL, NULL, - prepare_unused_channel_list); - if (ret < 0) - return ret; + if (!unused_chan_list_done) { + /* + * Scan all the platform devices to find out the EDMA channels + * used and clear them in the unused list, making the rest + * available for ARM usage. + */ + ret = bus_for_each_dev(&platform_bus_type, NULL, NULL, + prepare_unused_channel_list); + if (ret < 0) + return ret; - unused_chan_list_done = true; - } + unused_chan_list_done = true; + } #endif - if (channel >= 0) { - ctlr = EDMA_CTLR(channel); - channel = EDMA_CHAN_SLOT(channel); - clear_bit(channel, edma_cc[ctlr]->edma_unused); - } + if (channel >= 0) { + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); + clear_bit(channel, edma_cc[ctlr]->edma_unused); + } - if (channel < 0) { - for (i = 0; i < arch_num_cc; i++) { - channel = 0; - for (;;) { - channel = find_next_bit(edma_cc[i]->edma_unused, - edma_cc[i]->num_channels, - channel); - if (channel == edma_cc[i]->num_channels) - break; - if (!test_and_set_bit(channel, - edma_cc[i]->edma_inuse)) { - done = 1; - ctlr = i; - break; - } - channel++; - } - if (done) - break; - } - if (!done) - return -RT_ENOMEM; - } else if (channel >= edma_cc[ctlr]->num_channels) { - return -RT_ERROR; - } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) { - return -RT_EBUSY; - } + if (channel < 0) { + for (i = 0; i < arch_num_cc; i++) { + channel = 0; + for (;;) { + channel = find_next_bit(edma_cc[i]->edma_unused, + edma_cc[i]->num_channels, + channel); + if (channel == edma_cc[i]->num_channels) + break; + if (!test_and_set_bit(channel, + edma_cc[i]->edma_inuse)) { + done = 1; + ctlr = i; + break; + } + channel++; + } + if (done) + break; + } + if (!done) + return -RT_ENOMEM; + } else if (channel >= edma_cc[ctlr]->num_channels) { + return -RT_ERROR; + } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) { + return -RT_EBUSY; + } - /* ensure access through shadow region 0 */ - edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f)); + /* ensure access through shadow region 0 */ + edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f)); - /* ensure no events are pending */ - edma_stop(EDMA_CTLR_CHAN(ctlr, channel)); - rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(channel)), - &dummy_paramset, PARM_SIZE); + /* ensure no events are pending */ + edma_stop(EDMA_CTLR_CHAN(ctlr, channel)); + rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(channel)), + &dummy_paramset, PARM_SIZE); - if (callback) - setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel), - callback, data); + if (callback) + setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel), + callback, data); - map_dmach_queue(ctlr, channel, eventq_no); + map_dmach_queue(ctlr, channel, eventq_no); - return EDMA_CTLR_CHAN(ctlr, channel); + return EDMA_CTLR_CHAN(ctlr, channel); } @@ -802,20 +788,20 @@ int edma_alloc_channel(int channel, */ void edma_free_channel(unsigned channel) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(channel); - channel = EDMA_CHAN_SLOT(channel); + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); - if (channel >= edma_cc[ctlr]->num_channels) - return; + if (channel >= edma_cc[ctlr]->num_channels) + return; - setup_dma_interrupt(channel, RT_NULL, RT_NULL); - /* REVISIT should probably take out of shadow region 0 */ + setup_dma_interrupt(channel, RT_NULL, RT_NULL); + /* REVISIT should probably take out of shadow region 0 */ - rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(channel)), - &dummy_paramset, PARM_SIZE); - clear_bit(channel, edma_cc[ctlr]->edma_inuse); + rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(channel)), + &dummy_paramset, PARM_SIZE); + clear_bit(channel, edma_cc[ctlr]->edma_inuse); } @@ -835,30 +821,30 @@ void edma_free_channel(unsigned channel) */ int edma_alloc_slot(unsigned ctlr, int slot) { - if (slot >= 0) - slot = EDMA_CHAN_SLOT(slot); + if (slot >= 0) + slot = EDMA_CHAN_SLOT(slot); - if (slot < 0) { - slot = edma_cc[ctlr]->num_channels; - for (;;) { - slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse, - edma_cc[ctlr]->num_slots, slot); - if (slot == edma_cc[ctlr]->num_slots) - return -RT_ENOMEM; - if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) - break; - } - } else if (slot < edma_cc[ctlr]->num_channels || - slot >= edma_cc[ctlr]->num_slots) { - return -RT_ERROR; - } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) { - return -RT_EBUSY; - } + if (slot < 0) { + slot = edma_cc[ctlr]->num_channels; + for (;;) { + slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse, + edma_cc[ctlr]->num_slots, slot); + if (slot == edma_cc[ctlr]->num_slots) + return -RT_ENOMEM; + if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) + break; + } + } else if (slot < edma_cc[ctlr]->num_channels || + slot >= edma_cc[ctlr]->num_slots) { + return -RT_ERROR; + } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) { + return -RT_EBUSY; + } - rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)), - &dummy_paramset, PARM_SIZE); + rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)), + &dummy_paramset, PARM_SIZE); - return EDMA_CTLR_CHAN(ctlr, slot); + return EDMA_CTLR_CHAN(ctlr, slot); } @@ -872,18 +858,18 @@ int edma_alloc_slot(unsigned ctlr, int slot) */ void edma_free_slot(unsigned slot) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); - if (slot < edma_cc[ctlr]->num_channels || - slot >= edma_cc[ctlr]->num_slots) - return; + if (slot < edma_cc[ctlr]->num_channels || + slot >= edma_cc[ctlr]->num_slots) + return; - rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)), - &dummy_paramset, PARM_SIZE); - clear_bit(slot, edma_cc[ctlr]->edma_inuse); + rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)), + &dummy_paramset, PARM_SIZE); + clear_bit(slot, edma_cc[ctlr]->edma_inuse); } @@ -915,35 +901,35 @@ void edma_free_slot(unsigned slot) */ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count) { - /* - * The start slot requested should be greater than - * the number of channels and lesser than the total number - * of slots - */ - if ((id != EDMA_CONT_PARAMS_ANY) && - (slot < edma_cc[ctlr]->num_channels || - slot >= edma_cc[ctlr]->num_slots)) - return -RT_ERROR; + /* + * The start slot requested should be greater than + * the number of channels and lesser than the total number + * of slots + */ + if ((id != EDMA_CONT_PARAMS_ANY) && + (slot < edma_cc[ctlr]->num_channels || + slot >= edma_cc[ctlr]->num_slots)) + return -RT_ERROR; - /* - * The number of parameter RAM slots requested cannot be less than 1 - * and cannot be more than the number of slots minus the number of - * channels - */ - if (count < 1 || count > - (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels)) - return -RT_ERROR; + /* + * The number of parameter RAM slots requested cannot be less than 1 + * and cannot be more than the number of slots minus the number of + * channels + */ + if (count < 1 || count > + (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels)) + return -RT_ERROR; - switch (id) { - case EDMA_CONT_PARAMS_ANY: - return reserve_contiguous_slots(ctlr, id, count, - edma_cc[ctlr]->num_channels); - case EDMA_CONT_PARAMS_FIXED_EXACT: - case EDMA_CONT_PARAMS_FIXED_NOT_EXACT: - return reserve_contiguous_slots(ctlr, id, count, slot); - default: - return -RT_ERROR; - } + switch (id) { + case EDMA_CONT_PARAMS_ANY: + return reserve_contiguous_slots(ctlr, id, count, + edma_cc[ctlr]->num_channels); + case EDMA_CONT_PARAMS_FIXED_EXACT: + case EDMA_CONT_PARAMS_FIXED_NOT_EXACT: + return reserve_contiguous_slots(ctlr, id, count, slot); + default: + return -RT_ERROR; + } } @@ -963,27 +949,27 @@ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count) */ int edma_free_cont_slots(unsigned slot, int count) { - unsigned ctlr, slot_to_free; - int i; + unsigned ctlr, slot_to_free; + int i; - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); - if (slot < edma_cc[ctlr]->num_channels || - slot >= edma_cc[ctlr]->num_slots || - count < 1) - return -RT_ERROR; + if (slot < edma_cc[ctlr]->num_channels || + slot >= edma_cc[ctlr]->num_slots || + count < 1) + return -RT_ERROR; - for (i = slot; i < slot + count; ++i) { - ctlr = EDMA_CTLR(i); - slot_to_free = EDMA_CHAN_SLOT(i); + for (i = slot; i < slot + count; ++i) { + ctlr = EDMA_CTLR(i); + slot_to_free = EDMA_CHAN_SLOT(i); - rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free)), - &dummy_paramset, PARM_SIZE); - clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse); - } + rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free)), + &dummy_paramset, PARM_SIZE); + clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse); + } - return 0; + return 0; } @@ -997,35 +983,35 @@ int edma_free_cont_slots(unsigned slot, int count) * @src_port: physical address of source (memory, controller FIFO, etc) * @addressMode: INCR, except in very rare cases * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the - * width to use when addressing the fifo (e.g. W8BIT, W32BIT) + * width to use when addressing the fifo (e.g. W8BIT, W32BIT) * * Note that the source address is modified during the DMA transfer * according to edma_set_src_index(). */ void edma_set_src(unsigned slot, rt_uint32_t src_port, - enum address_mode mode, enum fifo_width width) + enum address_mode mode, enum fifo_width width) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); - if (slot < edma_cc[ctlr]->num_slots) { - unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); + if (slot < edma_cc[ctlr]->num_slots) { + unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); - if (mode) { - /* set SAM and program FWID */ - i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8)); - } else { - /* clear SAM */ - i &= ~SAM; - } - edma_parm_write(ctlr, PARM_OPT, slot, i); + if (mode) { + /* set SAM and program FWID */ + i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8)); + } else { + /* clear SAM */ + i &= ~SAM; + } + edma_parm_write(ctlr, PARM_OPT, slot, i); - /* set the source port address - in source register of param structure */ - edma_parm_write(ctlr, PARM_SRC, slot, src_port); - } + /* set the source port address + in source register of param structure */ + edma_parm_write(ctlr, PARM_SRC, slot, src_port); + } } @@ -1035,34 +1021,34 @@ void edma_set_src(unsigned slot, rt_uint32_t src_port, * @dest_port: physical address of destination (memory, controller FIFO, etc) * @addressMode: INCR, except in very rare cases * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the - * width to use when addressing the fifo (e.g. W8BIT, W32BIT) + * width to use when addressing the fifo (e.g. W8BIT, W32BIT) * * Note that the destination address is modified during the DMA transfer * according to edma_set_dest_index(). */ void edma_set_dest(unsigned slot, rt_uint32_t dest_port, - enum address_mode mode, enum fifo_width width) + enum address_mode mode, enum fifo_width width) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); - if (slot < edma_cc[ctlr]->num_slots) { - unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); + if (slot < edma_cc[ctlr]->num_slots) { + unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); - if (mode) { - /* set DAM and program FWID */ - i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8)); - } else { - /* clear DAM */ - i &= ~DAM; - } - edma_parm_write(ctlr, PARM_OPT, slot, i); - /* set the destination port address - in dest register of param structure */ - edma_parm_write(ctlr, PARM_DST, slot, dest_port); - } + if (mode) { + /* set DAM and program FWID */ + i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8)); + } else { + /* clear DAM */ + i &= ~DAM; + } + edma_parm_write(ctlr, PARM_OPT, slot, i); + /* set the destination port address + in dest register of param structure */ + edma_parm_write(ctlr, PARM_DST, slot, dest_port); + } } @@ -1077,17 +1063,17 @@ void edma_set_dest(unsigned slot, rt_uint32_t dest_port, */ void edma_get_position(unsigned slot, rt_uint32_t *src, rt_uint32_t *dst) { - struct edmacc_param temp; - unsigned ctlr; + struct edmacc_param temp; + unsigned ctlr; - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); - edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp); - if (src != RT_NULL) - *src = temp.src; - if (dst != RT_NULL) - *dst = temp.dst; + edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp); + if (src != RT_NULL) + *src = temp.src; + if (dst != RT_NULL) + *dst = temp.dst; } @@ -1103,17 +1089,17 @@ void edma_get_position(unsigned slot, rt_uint32_t *src, rt_uint32_t *dst) */ void edma_set_src_index(unsigned slot, rt_int16_t src_bidx, rt_int16_t src_cidx) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); - if (slot < edma_cc[ctlr]->num_slots) { - edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, - 0xffff0000, src_bidx); - edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, - 0xffff0000, src_cidx); - } + if (slot < edma_cc[ctlr]->num_slots) { + edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, + 0xffff0000, src_bidx); + edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, + 0xffff0000, src_cidx); + } } @@ -1129,17 +1115,17 @@ void edma_set_src_index(unsigned slot, rt_int16_t src_bidx, rt_int16_t src_cidx) */ void edma_set_dest_index(unsigned slot, rt_int16_t dest_bidx, rt_int16_t dest_cidx) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); - if (slot < edma_cc[ctlr]->num_slots) { - edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, - 0x0000ffff, dest_bidx << 16); - edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, - 0x0000ffff, dest_cidx << 16); - } + if (slot < edma_cc[ctlr]->num_slots) { + edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, + 0x0000ffff, dest_bidx << 16); + edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, + 0x0000ffff, dest_cidx << 16); + } } @@ -1150,7 +1136,7 @@ void edma_set_dest_index(unsigned slot, rt_int16_t dest_bidx, rt_int16_t dest_ci * @bcnt: how many arrays per frame (at least one) * @ccnt: how many frames per block (at least one) * @bcnt_rld: used only for A-Synchronized transfers; this specifies - * the value to reload into bcnt when it decrements to zero + * the value to reload into bcnt when it decrements to zero * @sync_mode: ASYNC or ABSYNC * * See the EDMA3 documentation to understand how to configure and link @@ -1173,25 +1159,25 @@ void edma_set_dest_index(unsigned slot, rt_int16_t dest_bidx, rt_int16_t dest_ci * efficient burst modes to access memory. */ void edma_set_transfer_params(unsigned slot, - rt_uint16_t acnt, rt_uint16_t bcnt, rt_uint16_t ccnt, - rt_uint16_t bcnt_rld, enum sync_dimension sync_mode) + rt_uint16_t acnt, rt_uint16_t bcnt, rt_uint16_t ccnt, + rt_uint16_t bcnt_rld, enum sync_dimension sync_mode) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); - if (slot < edma_cc[ctlr]->num_slots) { - edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot, - 0x0000ffff, bcnt_rld << 16); - if (sync_mode == ASYNC) - edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM); - else - edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM); - /* Set the acount, bcount, ccount registers */ - edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt); - edma_parm_write(ctlr, PARM_CCNT, slot, ccnt); - } + if (slot < edma_cc[ctlr]->num_slots) { + edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot, + 0x0000ffff, bcnt_rld << 16); + if (sync_mode == ASYNC) + edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM); + else + edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM); + /* Set the acount, bcount, ccount registers */ + edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt); + edma_parm_write(ctlr, PARM_CCNT, slot, ccnt); + } } @@ -1204,19 +1190,19 @@ void edma_set_transfer_params(unsigned slot, */ void edma_link(unsigned from, unsigned to) { - unsigned ctlr_from, ctlr_to; + unsigned ctlr_from, ctlr_to; - ctlr_from = EDMA_CTLR(from); - from = EDMA_CHAN_SLOT(from); - ctlr_to = EDMA_CTLR(to); - to = EDMA_CHAN_SLOT(to); + ctlr_from = EDMA_CTLR(from); + from = EDMA_CHAN_SLOT(from); + ctlr_to = EDMA_CTLR(to); + to = EDMA_CHAN_SLOT(to); - if (from >= edma_cc[ctlr_from]->num_slots) - return; - if (to >= edma_cc[ctlr_to]->num_slots) - return; - edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000, - PARM_OFFSET(to)); + if (from >= edma_cc[ctlr_from]->num_slots) + return; + if (to >= edma_cc[ctlr_to]->num_slots) + return; + edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000, + PARM_OFFSET(to)); } @@ -1229,14 +1215,14 @@ void edma_link(unsigned from, unsigned to) */ void edma_unlink(unsigned from) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(from); - from = EDMA_CHAN_SLOT(from); + ctlr = EDMA_CTLR(from); + from = EDMA_CHAN_SLOT(from); - if (from >= edma_cc[ctlr]->num_slots) - return; - edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff); + if (from >= edma_cc[ctlr]->num_slots) + return; + edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff); } @@ -1256,15 +1242,15 @@ void edma_unlink(unsigned from) */ void edma_write_slot(unsigned slot, const struct edmacc_param *param) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); - if (slot >= edma_cc[ctlr]->num_slots) - return; - rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)), param, - PARM_SIZE); + if (slot >= edma_cc[ctlr]->num_slots) + return; + rt_memcpy((void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)), param, + PARM_SIZE); } @@ -1278,15 +1264,15 @@ void edma_write_slot(unsigned slot, const struct edmacc_param *param) */ void edma_read_slot(unsigned slot, struct edmacc_param *param) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(slot); - slot = EDMA_CHAN_SLOT(slot); + ctlr = EDMA_CTLR(slot); + slot = EDMA_CHAN_SLOT(slot); - if (slot >= edma_cc[ctlr]->num_slots) - return; - rt_memcpy(param, (void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)), - PARM_SIZE); + if (slot >= edma_cc[ctlr]->num_slots) + return; + rt_memcpy(param, (void *)(edmacc_regs_base[ctlr] + PARM_OFFSET(slot)), + PARM_SIZE); } @@ -1303,16 +1289,16 @@ void edma_read_slot(unsigned slot, struct edmacc_param *param) */ void edma_pause(unsigned channel) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(channel); - channel = EDMA_CHAN_SLOT(channel); + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); - if (channel < edma_cc[ctlr]->num_channels) { - unsigned int mask = BIT(channel & 0x1f); + if (channel < edma_cc[ctlr]->num_channels) { + unsigned int mask = BIT(channel & 0x1f); - edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask); - } + edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask); + } } @@ -1324,16 +1310,16 @@ void edma_pause(unsigned channel) */ void edma_resume(unsigned channel) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(channel); - channel = EDMA_CHAN_SLOT(channel); + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); - if (channel < edma_cc[ctlr]->num_channels) { - unsigned int mask = BIT(channel & 0x1f); + if (channel < edma_cc[ctlr]->num_channels) { + unsigned int mask = BIT(channel & 0x1f); - edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask); - } + edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask); + } } @@ -1350,38 +1336,38 @@ void edma_resume(unsigned channel) */ int edma_start(unsigned channel) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(channel); - channel = EDMA_CHAN_SLOT(channel); + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); - if (channel < edma_cc[ctlr]->num_channels) { - int j = channel >> 5; - unsigned int mask = BIT(channel & 0x1f); + if (channel < edma_cc[ctlr]->num_channels) { + int j = channel >> 5; + unsigned int mask = BIT(channel & 0x1f); - /* EDMA channels without event association */ - if (test_bit(channel, edma_cc[ctlr]->edma_unused)) { - edma_dbg("EDMA: ESR%d %08x\n", j, - edma_shadow0_read_array(ctlr, SH_ESR, j)); - edma_shadow0_write_array(ctlr, SH_ESR, j, mask); - return 0; - } + /* EDMA channels without event association */ + if (test_bit(channel, edma_cc[ctlr]->edma_unused)) { + edma_dbg("EDMA: ESR%d %08x\n", j, + edma_shadow0_read_array(ctlr, SH_ESR, j)); + edma_shadow0_write_array(ctlr, SH_ESR, j, mask); + return 0; + } - /* EDMA channel with event association */ - edma_dbg("EDMA: ER%d %08x\n", j, - edma_shadow0_read_array(ctlr, SH_ER, j)); - /* Clear any pending event or error */ - edma_write_array(ctlr, EDMA_ECR, j, mask); - edma_write_array(ctlr, EDMA_EMCR, j, mask); - /* Clear any SER */ - edma_shadow0_write_array(ctlr, SH_SECR, j, mask); - edma_shadow0_write_array(ctlr, SH_EESR, j, mask); - edma_dbg("EDMA: EER%d %08x\n", j, - edma_shadow0_read_array(ctlr, SH_EER, j)); - return 0; - } + /* EDMA channel with event association */ + edma_dbg("EDMA: ER%d %08x\n", j, + edma_shadow0_read_array(ctlr, SH_ER, j)); + /* Clear any pending event or error */ + edma_write_array(ctlr, EDMA_ECR, j, mask); + edma_write_array(ctlr, EDMA_EMCR, j, mask); + /* Clear any SER */ + edma_shadow0_write_array(ctlr, SH_SECR, j, mask); + edma_shadow0_write_array(ctlr, SH_EESR, j, mask); + edma_dbg("EDMA: EER%d %08x\n", j, + edma_shadow0_read_array(ctlr, SH_EER, j)); + return 0; + } - return -RT_ERROR; + return -RT_ERROR; } @@ -1396,27 +1382,27 @@ int edma_start(unsigned channel) */ void edma_stop(unsigned channel) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(channel); - channel = EDMA_CHAN_SLOT(channel); + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); - if (channel < edma_cc[ctlr]->num_channels) { - int j = channel >> 5; - unsigned int mask = BIT(channel & 0x1f); + if (channel < edma_cc[ctlr]->num_channels) { + int j = channel >> 5; + unsigned int mask = BIT(channel & 0x1f); - edma_shadow0_write_array(ctlr, SH_EECR, j, mask); - edma_shadow0_write_array(ctlr, SH_ECR, j, mask); - edma_shadow0_write_array(ctlr, SH_SECR, j, mask); - edma_write_array(ctlr, EDMA_EMCR, j, mask); + edma_shadow0_write_array(ctlr, SH_EECR, j, mask); + edma_shadow0_write_array(ctlr, SH_ECR, j, mask); + edma_shadow0_write_array(ctlr, SH_SECR, j, mask); + edma_write_array(ctlr, EDMA_EMCR, j, mask); - edma_dbg("EDMA: EER%d %08x\n", j, - edma_shadow0_read_array(ctlr, SH_EER, j)); + edma_dbg("EDMA: EER%d %08x\n", j, + edma_shadow0_read_array(ctlr, SH_EER, j)); - /* REVISIT: consider guarding against inappropriate event - * chaining by overwriting with dummy_paramset. - */ - } + /* REVISIT: consider guarding against inappropriate event + * chaining by overwriting with dummy_paramset. + */ + } } @@ -1435,45 +1421,45 @@ void edma_stop(unsigned channel) void edma_clean_channel(unsigned channel) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(channel); - channel = EDMA_CHAN_SLOT(channel); + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); - if (channel < edma_cc[ctlr]->num_channels) { - int j = (channel >> 5); - unsigned int mask = BIT(channel & 0x1f); + if (channel < edma_cc[ctlr]->num_channels) { + int j = (channel >> 5); + unsigned int mask = BIT(channel & 0x1f); - edma_dbg("EDMA: EMR%d %08x\n", j, - edma_read_array(ctlr, EDMA_EMR, j)); - edma_shadow0_write_array(ctlr, SH_ECR, j, mask); - /* Clear the corresponding EMR bits */ - edma_write_array(ctlr, EDMA_EMCR, j, mask); - /* Clear any SER */ - edma_shadow0_write_array(ctlr, SH_SECR, j, mask); - edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); - } + edma_dbg("EDMA: EMR%d %08x\n", j, + edma_read_array(ctlr, EDMA_EMR, j)); + edma_shadow0_write_array(ctlr, SH_ECR, j, mask); + /* Clear the corresponding EMR bits */ + edma_write_array(ctlr, EDMA_EMCR, j, mask); + /* Clear any SER */ + edma_shadow0_write_array(ctlr, SH_SECR, j, mask); + edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); + } } /* * edma_clear_event - clear an outstanding event on the DMA channel * Arguments: - * channel - channel number + * channel - channel number */ void edma_clear_event(unsigned channel) { - unsigned ctlr; + unsigned ctlr; - ctlr = EDMA_CTLR(channel); - channel = EDMA_CHAN_SLOT(channel); + ctlr = EDMA_CTLR(channel); + channel = EDMA_CHAN_SLOT(channel); - if (channel >= edma_cc[ctlr]->num_channels) - return; - if (channel < 32) - edma_write(ctlr, EDMA_ECR, BIT(channel)); - else - edma_write(ctlr, EDMA_ECRH, BIT(channel - 32)); + if (channel >= edma_cc[ctlr]->num_channels) + return; + if (channel < 32) + edma_write(ctlr, EDMA_ECR, BIT(channel)); + else + edma_write(ctlr, EDMA_ECRH, BIT(channel - 32)); } @@ -1481,112 +1467,112 @@ void edma_clear_event(unsigned channel) int edma_init(struct edma_soc_info **info) { - //struct edma_soc_info **info = pdev->dev.platform_data; - const rt_int8_t (*queue_priority_mapping)[2]; - const rt_int8_t (*queue_tc_mapping)[2]; - int i, j, off, ln, found = 0; - int status = -1; - const rt_int16_t (*rsv_chans)[2]; - const rt_int16_t (*rsv_slots)[2]; - int irq[EDMA_MAX_CC] = {0, 0}; - int err_irq[EDMA_MAX_CC] = {0, 0}; + //struct edma_soc_info **info = pdev->dev.platform_data; + const rt_int8_t (*queue_priority_mapping)[2]; + const rt_int8_t (*queue_tc_mapping)[2]; + int i, j, off, ln, found = 0; + int status = -1; + const rt_int16_t (*rsv_chans)[2]; + const rt_int16_t (*rsv_slots)[2]; + int irq[EDMA_MAX_CC] = {0, 0}; + int err_irq[EDMA_MAX_CC] = {0, 0}; - RT_ASSERT(info != RT_NULL); + RT_ASSERT(info != RT_NULL); - psc_change_state(DAVINCI_DM365_LPSC_TPCC, PSC_ENABLE); - psc_change_state(DAVINCI_DM365_LPSC_TPTC0, PSC_ENABLE); - psc_change_state(DAVINCI_DM365_LPSC_TPTC1, PSC_ENABLE); - psc_change_state(DAVINCI_DM365_LPSC_TPTC2, PSC_ENABLE); - psc_change_state(DAVINCI_DM365_LPSC_TPTC3, PSC_ENABLE); + psc_change_state(DAVINCI_DM365_LPSC_TPCC, PSC_ENABLE); + psc_change_state(DAVINCI_DM365_LPSC_TPTC0, PSC_ENABLE); + psc_change_state(DAVINCI_DM365_LPSC_TPTC1, PSC_ENABLE); + psc_change_state(DAVINCI_DM365_LPSC_TPTC2, PSC_ENABLE); + psc_change_state(DAVINCI_DM365_LPSC_TPTC3, PSC_ENABLE); - edmacc_regs_base[0] = (void *)EDMA_CC0_BASE_REG; + edmacc_regs_base[0] = (void *)EDMA_CC0_BASE_REG; - edma_cc[0] = rt_malloc(sizeof(struct edma)); - if (!edma_cc[0]) { - status = -RT_ENOMEM; - goto fail1; - } - rt_memset(edma_cc[0], 0, sizeof(struct edma)); + edma_cc[0] = rt_malloc(sizeof(struct edma)); + if (!edma_cc[0]) { + status = -RT_ENOMEM; + goto fail1; + } + rt_memset(edma_cc[0], 0, sizeof(struct edma)); - edma_cc[0]->num_channels = min_t(unsigned, info[0]->n_channel, - EDMA_MAX_DMACH); - edma_cc[0]->num_slots = min_t(unsigned, info[0]->n_slot, - EDMA_MAX_PARAMENTRY); - edma_cc[0]->num_cc = min_t(unsigned, info[0]->n_cc, - EDMA_MAX_CC); + edma_cc[0]->num_channels = min_t(unsigned, info[0]->n_channel, + EDMA_MAX_DMACH); + edma_cc[0]->num_slots = min_t(unsigned, info[0]->n_slot, + EDMA_MAX_PARAMENTRY); + edma_cc[0]->num_cc = min_t(unsigned, info[0]->n_cc, + EDMA_MAX_CC); - edma_cc[0]->default_queue = info[0]->default_queue; - if (!edma_cc[0]->default_queue) - edma_cc[0]->default_queue = EVENTQ_1; + edma_cc[0]->default_queue = info[0]->default_queue; + if (!edma_cc[0]->default_queue) + edma_cc[0]->default_queue = EVENTQ_1; - edma_dbg("DMA REG BASE ADDR=%p\n", - edmacc_regs_base[j]); + edma_dbg("DMA REG BASE ADDR=%p\n", + edmacc_regs_base[j]); - for (i = 0; i < edma_cc[0]->num_slots; i++) - rt_memcpy((void *)(edmacc_regs_base[0] + PARM_OFFSET(i)), - &dummy_paramset, PARM_SIZE); + for (i = 0; i < edma_cc[0]->num_slots; i++) + rt_memcpy((void *)(edmacc_regs_base[0] + PARM_OFFSET(i)), + &dummy_paramset, PARM_SIZE); - /* Mark all channels as unused */ - rt_memset(edma_cc[0]->edma_unused, 0xff, - sizeof(edma_cc[0]->edma_unused)); + /* Mark all channels as unused */ + rt_memset(edma_cc[0]->edma_unused, 0xff, + sizeof(edma_cc[0]->edma_unused)); - edma_cc[0]->irq_res_start = IRQ_CCINT0; - rt_hw_interrupt_install(IRQ_CCINT0, dma_irq_handler, RT_NULL, "edma"); - rt_hw_interrupt_umask(IRQ_CCINT0); + edma_cc[0]->irq_res_start = IRQ_CCINT0; + rt_hw_interrupt_install(IRQ_CCINT0, dma_irq_handler, RT_NULL, "edma"); + rt_hw_interrupt_umask(IRQ_CCINT0); - edma_cc[0]->irq_res_end = IRQ_CCERRINT; - rt_hw_interrupt_install(IRQ_CCERRINT, dma_ccerr_handler, RT_NULL, "edma_error"); - rt_hw_interrupt_umask(IRQ_CCERRINT); + edma_cc[0]->irq_res_end = IRQ_CCERRINT; + rt_hw_interrupt_install(IRQ_CCERRINT, dma_ccerr_handler, RT_NULL, "edma_error"); + rt_hw_interrupt_umask(IRQ_CCERRINT); - /* Everything lives on transfer controller 1 until otherwise - * specified. This way, long transfers on the low priority queue - * started by the codec engine will not cause audio defects. - */ - for (i = 0; i < edma_cc[0]->num_channels; i++) - map_dmach_queue(0, i, EVENTQ_1); + /* Everything lives on transfer controller 1 until otherwise + * specified. This way, long transfers on the low priority queue + * started by the codec engine will not cause audio defects. + */ + for (i = 0; i < edma_cc[0]->num_channels; i++) + map_dmach_queue(0, i, EVENTQ_1); - queue_tc_mapping = info[0]->queue_tc_mapping; - queue_priority_mapping = info[0]->queue_priority_mapping; + queue_tc_mapping = info[0]->queue_tc_mapping; + queue_priority_mapping = info[0]->queue_priority_mapping; - /* Event queue to TC mapping */ - for (i = 0; queue_tc_mapping[i][0] != -1; i++) - map_queue_tc(0, queue_tc_mapping[i][0], - queue_tc_mapping[i][1]); + /* Event queue to TC mapping */ + for (i = 0; queue_tc_mapping[i][0] != -1; i++) + map_queue_tc(0, queue_tc_mapping[i][0], + queue_tc_mapping[i][1]); - /* Event queue priority mapping */ - for (i = 0; queue_priority_mapping[i][0] != -1; i++) - assign_priority_to_queue(0, - queue_priority_mapping[i][0], - queue_priority_mapping[i][1]); + /* Event queue priority mapping */ + for (i = 0; queue_priority_mapping[i][0] != -1; i++) + assign_priority_to_queue(0, + queue_priority_mapping[i][0], + queue_priority_mapping[i][1]); - /* Map the channel to param entry if channel mapping logic - * exist - */ - if (edma_read(0, EDMA_CCCFG) & CHMAP_EXIST) - map_dmach_param(0); + /* Map the channel to param entry if channel mapping logic + * exist + */ + if (edma_read(0, EDMA_CCCFG) & CHMAP_EXIST) + map_dmach_param(0); - for (i = 0; i < info[0]->n_region; i++) { - edma_write_array2(0, EDMA_DRAE, i, 0, 0x0); - edma_write_array2(0, EDMA_DRAE, i, 1, 0x0); - edma_write_array(0, EDMA_QRAE, i, 0x0); - } - arch_num_cc++; + for (i = 0; i < info[0]->n_region; i++) { + edma_write_array2(0, EDMA_DRAE, i, 0, 0x0); + edma_write_array2(0, EDMA_DRAE, i, 1, 0x0); + edma_write_array(0, EDMA_QRAE, i, 0x0); + } + arch_num_cc++; - if (tc_errs_handled) { - rt_hw_interrupt_install(IRQ_TCERRINT0, dma_tc0err_handler, "edma_tc0"); - rt_hw_interrupt_umask(IRQ_TCERRINT0); - rt_hw_interrupt_install(IRQ_TCERRINT, dma_tc1err_handler, "edma_tc1"); - rt_hw_interrupt_umask(IRQ_TCERRINT); - } + if (tc_errs_handled) { + rt_hw_interrupt_install(IRQ_TCERRINT0, dma_tc0err_handler, "edma_tc0"); + rt_hw_interrupt_umask(IRQ_TCERRINT0); + rt_hw_interrupt_install(IRQ_TCERRINT, dma_tc1err_handler, "edma_tc1"); + rt_hw_interrupt_umask(IRQ_TCERRINT); + } - return 0; + return 0; fail: fail1: - rt_free(edma_cc[0]); + rt_free(edma_cc[0]); - return status; + return status; } diff --git a/bsp/dm365/platform/edma.h b/bsp/dm365/platform/edma.h index 34d5bb1ef7..57007f5bbb 100644 --- a/bsp/dm365/platform/edma.h +++ b/bsp/dm365/platform/edma.h @@ -1,39 +1,25 @@ /* - * File : edma.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ /* * This EDMA3 programming framework exposes two basic kinds of resource: * - * Channel Triggers transfers, usually from a hardware event but - * also manually or by "chaining" from DMA completions. - * Each channel is coupled to a Parameter RAM (PaRAM) slot. + * Channel Triggers transfers, usually from a hardware event but + * also manually or by "chaining" from DMA completions. + * Each channel is coupled to a Parameter RAM (PaRAM) slot. * - * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM - * "set"), source and destination addresses, a link to a - * next PaRAM slot (if any), options for the transfer, and - * instructions for updating those addresses. There are - * more than twice as many slots as event channels. + * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM + * "set"), source and destination addresses, a link to a + * next PaRAM slot (if any), options for the transfer, and + * instructions for updating those addresses. There are + * more than twice as many slots as event channels. * * Each PaRAM set describes a sequence of transfers, either for one large * buffer or for several discontiguous smaller buffers. An EDMA transfer @@ -66,14 +52,14 @@ /* PaRAM slots are laid out like this */ struct edmacc_param { - unsigned int opt; - unsigned int src; - unsigned int a_b_cnt; - unsigned int dst; - unsigned int src_dst_bidx; - unsigned int link_bcntrld; - unsigned int src_dst_cidx; - unsigned int ccnt; + unsigned int opt; + unsigned int src; + unsigned int a_b_cnt; + unsigned int dst; + unsigned int src_dst_bidx; + unsigned int link_bcntrld; + unsigned int src_dst_cidx; + unsigned int ccnt; }; #define CCINT0_INTERRUPT 16 @@ -82,110 +68,110 @@ struct edmacc_param { #define TCERRINT1_INTERRUPT 19 /* fields in edmacc_param.opt */ -#define SAM BIT(0) -#define DAM BIT(1) -#define SYNCDIM BIT(2) -#define STATIC BIT(3) -#define EDMA_FWID (0x07 << 8) -#define TCCMODE BIT(11) -#define EDMA_TCC(t) ((t) << 12) -#define TCINTEN BIT(20) -#define ITCINTEN BIT(21) -#define TCCHEN BIT(22) -#define ITCCHEN BIT(23) +#define SAM BIT(0) +#define DAM BIT(1) +#define SYNCDIM BIT(2) +#define STATIC BIT(3) +#define EDMA_FWID (0x07 << 8) +#define TCCMODE BIT(11) +#define EDMA_TCC(t) ((t) << 12) +#define TCINTEN BIT(20) +#define ITCINTEN BIT(21) +#define TCCHEN BIT(22) +#define ITCCHEN BIT(23) #define TRWORD (0x7<<2) #define PAENTRY (0x1ff<<5) /* DM365 specific EDMA3 Events Information */ enum dm365_edma_ch { - DM365_DMA_TIMER3_TINT6, - DM365_DMA_TIMER3_TINT7, - DM365_DMA_MCBSP_TX = 2, - DM365_DMA_VCIF_TX = 2, - DM365_DMA_MCBSP_RX = 3, - DM365_DMA_VCIF_RX = 3, - DM365_DMA_VPSS_EVT1, - DM365_DMA_VPSS_EVT2, - DM365_DMA_VPSS_EVT3, - DM365_DMA_VPSS_EVT4, - DM365_DMA_TIMER2_TINT4, - DM365_DMA_TIMER2_TINT5, - DM365_DMA_SPI2XEVT, - DM365_DMA_SPI2REVT, - DM365_DMA_IMCOP_IMX0INT = 12, - DM365_DMA_KALEIDO_ARMINT = 12, - DM365_DMA_IMCOP_SEQINT, - DM365_DMA_SPI1XEVT, - DM365_DMA_SPI1REVT, - DM365_DMA_SPI0XEVT, - DM365_DMA_SPI0REVT, - DM365_DMA_URXEVT0 = 18, - DM365_DMA_SPI3XEVT = 18, - DM365_DMA_UTXEVT0 = 19, - DM365_DMA_SPI3REVT = 19, - DM365_DMA_URXEVT1, - DM365_DMA_UTXEVT1, - DM365_DMA_TIMER4_TINT8, - DM365_DMA_TIMER4_TINT9, - DM365_DMA_RTOINT, - DM365_DMA_GPIONT9, - DM365_DMA_MMC0RXEVT = 26, - DM365_DMA_MEMSTK_MSEVT = 26, - DM365_DMA_MMC0TXEVT, - DM365_DMA_I2C_ICREVT, - DM365_DMA_I2C_ICXEVT, - DM365_DMA_MMC1RXEVT, - DM365_DMA_MMC1TXEVT, - DM365_DMA_GPIOINT0, - DM365_DMA_GPIOINT1, - DM365_DMA_GPIOINT2, - DM365_DMA_GPIOINT3, - DM365_DMA_GPIOINT4, - DM365_DMA_GPIOINT5, - DM365_DMA_GPIOINT6, - DM365_DMA_GPIOINT7, - DM365_DMA_GPIOINT10 = 40, - DM365_DMA_EMAC_RXTHREESH = 40, - DM365_DMA_GPIOINT11 = 41, - DM365_DMA_EMAC_RXPULSE = 41, - DM365_DMA_GPIOINT12 = 42, - DM365_DMA_EMAC_TXPULSE = 42, - DM365_DMA_GPIOINT13 = 43, - DM365_DMA_EMAC_MISCPULSE = 43, - DM365_DMA_GPIOINT14 = 44, - DM365_DMA_SPI4XEVT = 44, - DM365_DMA_GPIOINT15 = 45, - DM365_DMA_SPI4REVT = 45, - DM365_DMA_ADC_ADINT, - DM365_DMA_GPIOINT8, - DM365_DMA_TIMER0_TINT0, - DM365_DMA_TIMER0_TINT1, - DM365_DMA_TIMER1_TINT2, - DM365_DMA_TIMER1_TINT3, - DM365_DMA_PWM0, - DM365_DMA_PWM1 = 53, - DM365_DMA_IMCOP_IMX1INT = 53, - DM365_DMA_PWM2 = 54, - DM365_DMA_IMCOP_NSFINT = 54, - DM365_DMA_PWM3 = 55, - DM365_DMA_KALEIDO6_CP_UNDEF = 55, - DM365_DMA_IMCOP_VLCDINT = 56, - DM365_DMA_KALEIDO5_CP_ECDCMP = 56, - DM365_DMA_IMCOP_BIMINT = 57, - DM365_DMA_KALEIDO8_CP_ME = 57, - DM365_DMA_IMCOP_DCTINT = 58, - DM365_DMA_KALEIDO1_CP_CALC = 58, - DM365_DMA_IMCOP_QIQINT = 59, - DM365_DMA_KALEIDO7_CP_IPE = 59, - DM365_DMA_IMCOP_BPSINT = 60, - DM365_DMA_KALEIDO2_CP_BS = 60, - DM365_DMA_IMCOP_VLCDERRINT = 61, - DM365_DMA_KALEIDO0_CP_LPF = 61, - DM365_DMA_IMCOP_RCNTINT = 62, - DM365_DMA_KALEIDO3_CP_MC = 62, - DM365_DMA_IMCOP_COPCINT = 63, - DM365_DMA_KALEIDO4_CP_ECDEND = 63, + DM365_DMA_TIMER3_TINT6, + DM365_DMA_TIMER3_TINT7, + DM365_DMA_MCBSP_TX = 2, + DM365_DMA_VCIF_TX = 2, + DM365_DMA_MCBSP_RX = 3, + DM365_DMA_VCIF_RX = 3, + DM365_DMA_VPSS_EVT1, + DM365_DMA_VPSS_EVT2, + DM365_DMA_VPSS_EVT3, + DM365_DMA_VPSS_EVT4, + DM365_DMA_TIMER2_TINT4, + DM365_DMA_TIMER2_TINT5, + DM365_DMA_SPI2XEVT, + DM365_DMA_SPI2REVT, + DM365_DMA_IMCOP_IMX0INT = 12, + DM365_DMA_KALEIDO_ARMINT = 12, + DM365_DMA_IMCOP_SEQINT, + DM365_DMA_SPI1XEVT, + DM365_DMA_SPI1REVT, + DM365_DMA_SPI0XEVT, + DM365_DMA_SPI0REVT, + DM365_DMA_URXEVT0 = 18, + DM365_DMA_SPI3XEVT = 18, + DM365_DMA_UTXEVT0 = 19, + DM365_DMA_SPI3REVT = 19, + DM365_DMA_URXEVT1, + DM365_DMA_UTXEVT1, + DM365_DMA_TIMER4_TINT8, + DM365_DMA_TIMER4_TINT9, + DM365_DMA_RTOINT, + DM365_DMA_GPIONT9, + DM365_DMA_MMC0RXEVT = 26, + DM365_DMA_MEMSTK_MSEVT = 26, + DM365_DMA_MMC0TXEVT, + DM365_DMA_I2C_ICREVT, + DM365_DMA_I2C_ICXEVT, + DM365_DMA_MMC1RXEVT, + DM365_DMA_MMC1TXEVT, + DM365_DMA_GPIOINT0, + DM365_DMA_GPIOINT1, + DM365_DMA_GPIOINT2, + DM365_DMA_GPIOINT3, + DM365_DMA_GPIOINT4, + DM365_DMA_GPIOINT5, + DM365_DMA_GPIOINT6, + DM365_DMA_GPIOINT7, + DM365_DMA_GPIOINT10 = 40, + DM365_DMA_EMAC_RXTHREESH = 40, + DM365_DMA_GPIOINT11 = 41, + DM365_DMA_EMAC_RXPULSE = 41, + DM365_DMA_GPIOINT12 = 42, + DM365_DMA_EMAC_TXPULSE = 42, + DM365_DMA_GPIOINT13 = 43, + DM365_DMA_EMAC_MISCPULSE = 43, + DM365_DMA_GPIOINT14 = 44, + DM365_DMA_SPI4XEVT = 44, + DM365_DMA_GPIOINT15 = 45, + DM365_DMA_SPI4REVT = 45, + DM365_DMA_ADC_ADINT, + DM365_DMA_GPIOINT8, + DM365_DMA_TIMER0_TINT0, + DM365_DMA_TIMER0_TINT1, + DM365_DMA_TIMER1_TINT2, + DM365_DMA_TIMER1_TINT3, + DM365_DMA_PWM0, + DM365_DMA_PWM1 = 53, + DM365_DMA_IMCOP_IMX1INT = 53, + DM365_DMA_PWM2 = 54, + DM365_DMA_IMCOP_NSFINT = 54, + DM365_DMA_PWM3 = 55, + DM365_DMA_KALEIDO6_CP_UNDEF = 55, + DM365_DMA_IMCOP_VLCDINT = 56, + DM365_DMA_KALEIDO5_CP_ECDCMP = 56, + DM365_DMA_IMCOP_BIMINT = 57, + DM365_DMA_KALEIDO8_CP_ME = 57, + DM365_DMA_IMCOP_DCTINT = 58, + DM365_DMA_KALEIDO1_CP_CALC = 58, + DM365_DMA_IMCOP_QIQINT = 59, + DM365_DMA_KALEIDO7_CP_IPE = 59, + DM365_DMA_IMCOP_BPSINT = 60, + DM365_DMA_KALEIDO2_CP_BS = 60, + DM365_DMA_IMCOP_VLCDERRINT = 61, + DM365_DMA_KALEIDO0_CP_LPF = 61, + DM365_DMA_IMCOP_RCNTINT = 62, + DM365_DMA_KALEIDO3_CP_MC = 62, + DM365_DMA_IMCOP_COPCINT = 63, + DM365_DMA_KALEIDO4_CP_ECDEND = 63, }; /* end DM365 specific info */ @@ -197,48 +183,48 @@ enum dm365_edma_ch { #define DMA_TC2_ERROR 4 enum address_mode { - INCR = 0, - FIFO = 1 + INCR = 0, + FIFO = 1 }; enum fifo_width { - W8BIT = 0, - W16BIT = 1, - W32BIT = 2, - W64BIT = 3, - W128BIT = 4, - W256BIT = 5 + W8BIT = 0, + W16BIT = 1, + W32BIT = 2, + W64BIT = 3, + W128BIT = 4, + W256BIT = 5 }; enum dma_event_q { - EVENTQ_0 = 0, - EVENTQ_1 = 1, - EVENTQ_2 = 2, - EVENTQ_3 = 3, - EVENTQ_DEFAULT = -1 + EVENTQ_0 = 0, + EVENTQ_1 = 1, + EVENTQ_2 = 2, + EVENTQ_3 = 3, + EVENTQ_DEFAULT = -1 }; enum sync_dimension { - ASYNC = 0, - ABSYNC = 1 + ASYNC = 0, + ABSYNC = 1 }; -#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan)) -#define EDMA_CTLR(i) ((i) >> 16) -#define EDMA_CHAN_SLOT(i) ((i) & 0xffff) +#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan)) +#define EDMA_CTLR(i) ((i) >> 16) +#define EDMA_CHAN_SLOT(i) ((i) & 0xffff) -#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */ -#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */ -#define EDMA_CONT_PARAMS_ANY 1001 -#define EDMA_CONT_PARAMS_FIXED_EXACT 1002 +#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */ +#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */ +#define EDMA_CONT_PARAMS_ANY 1001 +#define EDMA_CONT_PARAMS_FIXED_EXACT 1002 #define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003 #define EDMA_MAX_CC 2 /* alloc/free DMA channels and their dedicated parameter RAM slots */ int edma_alloc_channel(int channel, - void (*callback)(unsigned channel, rt_uint16_t ch_status, void *data), - void *data, enum dma_event_q); + void (*callback)(unsigned channel, rt_uint16_t ch_status, void *data), + void *data, enum dma_event_q); void edma_free_channel(unsigned channel); /* alloc/free parameter RAM slots */ @@ -251,14 +237,14 @@ int edma_free_cont_slots(unsigned slot, int count); /* calls that operate on part of a parameter RAM slot */ void edma_set_src(unsigned slot, rt_uint32_t src_port, - enum address_mode mode, enum fifo_width); + enum address_mode mode, enum fifo_width); void edma_set_dest(unsigned slot, rt_uint32_t dest_port, - enum address_mode mode, enum fifo_width); + enum address_mode mode, enum fifo_width); void edma_get_position(unsigned slot, rt_uint32_t *src, rt_uint32_t *dst); void edma_set_src_index(unsigned slot, rt_int16_t src_bidx, rt_int16_t src_cidx); void edma_set_dest_index(unsigned slot, rt_int16_t dest_bidx, rt_int16_t dest_cidx); void edma_set_transfer_params(unsigned slot, rt_uint16_t acnt, rt_uint16_t bcnt, rt_uint16_t ccnt, - rt_uint16_t bcnt_rld, enum sync_dimension sync_mode); + rt_uint16_t bcnt_rld, enum sync_dimension sync_mode); void edma_link(unsigned from, unsigned to); void edma_unlink(unsigned from); @@ -277,26 +263,26 @@ void edma_resume(unsigned channel); struct edma_rsv_info { - const rt_int16_t (*rsv_chans)[2]; - const rt_int16_t (*rsv_slots)[2]; + const rt_int16_t (*rsv_chans)[2]; + const rt_int16_t (*rsv_slots)[2]; }; /* platform_data for EDMA driver */ struct edma_soc_info { - /* how many dma resources of each type */ - unsigned n_channel; - unsigned n_region; - unsigned n_slot; - unsigned n_tc; - unsigned n_cc; - enum dma_event_q default_queue; + /* how many dma resources of each type */ + unsigned n_channel; + unsigned n_region; + unsigned n_slot; + unsigned n_tc; + unsigned n_cc; + enum dma_event_q default_queue; - /* Resource reservation for other cores */ - struct edma_rsv_info *rsv; + /* Resource reservation for other cores */ + struct edma_rsv_info *rsv; - const rt_int8_t (*queue_tc_mapping)[2]; - const rt_int8_t (*queue_priority_mapping)[2]; + const rt_int8_t (*queue_tc_mapping)[2]; + const rt_int8_t (*queue_priority_mapping)[2]; }; int edma_init(struct edma_soc_info **info); diff --git a/bsp/dm365/platform/findbit.S b/bsp/dm365/platform/findbit.S index 0c18563c96..229d9502cd 100644 --- a/bsp/dm365/platform/findbit.S +++ b/bsp/dm365/platform/findbit.S @@ -1,25 +1,11 @@ /* - * File : findbit.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ //#include //.text @@ -30,20 +16,20 @@ */ .globl _find_first_zero_bit_le _find_first_zero_bit_le: - teq r1, #0 - beq 3f - mov r2, #0 + teq r1, #0 + beq 3f + mov r2, #0 1: - ldrb r3, [r0, r2, lsr #3] - lsr r3, r2, #3 - ldrb r3, [r0, r3] - eors r3, r3, #0xff @ invert bits - bne .L_found @ any now set - found zero bit - add r2, r2, #8 @ next bit pointer -2: cmp r2, r1 @ any more? - blo 1b -3: mov r0, r1 @ no free bits - mov pc, lr + ldrb r3, [r0, r2, lsr #3] + lsr r3, r2, #3 + ldrb r3, [r0, r3] + eors r3, r3, #0xff @ invert bits + bne .L_found @ any now set - found zero bit + add r2, r2, #8 @ next bit pointer +2: cmp r2, r1 @ any more? + blo 1b +3: mov r0, r1 @ no free bits + mov pc, lr //ENDPROC(_find_first_zero_bit_le) /* @@ -52,19 +38,19 @@ _find_first_zero_bit_le: */ .globl _find_next_zero_bit_le _find_next_zero_bit_le: - teq r1, #0 - beq 3b - ands ip, r2, #7 - beq 1b @ If new byte, goto old routine - ldrb r3, [r0, r2, lsr #3] - lsr r3, r2, #3 - ldrb r3, [r0, r3] - eor r3, r3, #0xff @ now looking for a 1 bit - movs r3, r3, lsr ip @ shift off unused bits - bne .L_found - orr r2, r2, #7 @ if zero, then no bits here - add r2, r2, #1 @ align bit pointer - b 2b @ loop for next bit + teq r1, #0 + beq 3b + ands ip, r2, #7 + beq 1b @ If new byte, goto old routine + ldrb r3, [r0, r2, lsr #3] + lsr r3, r2, #3 + ldrb r3, [r0, r3] + eor r3, r3, #0xff @ now looking for a 1 bit + movs r3, r3, lsr ip @ shift off unused bits + bne .L_found + orr r2, r2, #7 @ if zero, then no bits here + add r2, r2, #1 @ align bit pointer + b 2b @ loop for next bit //ENDPROC(_find_next_zero_bit_le) /* @@ -73,20 +59,20 @@ _find_next_zero_bit_le: */ .globl _find_first_bit_le _find_first_bit_le: - teq r1, #0 - beq 3f - mov r2, #0 + teq r1, #0 + beq 3f + mov r2, #0 1: - ldrb r3, [r0, r2, lsr #3] - lsr r3, r2, #3 - ldrb r3, [r0, r3] - movs r3, r3 - bne .L_found @ any now set - found zero bit - add r2, r2, #8 @ next bit pointer -2: cmp r2, r1 @ any more? - blo 1b -3: mov r0, r1 @ no free bits - mov pc, lr + ldrb r3, [r0, r2, lsr #3] + lsr r3, r2, #3 + ldrb r3, [r0, r3] + movs r3, r3 + bne .L_found @ any now set - found zero bit + add r2, r2, #8 @ next bit pointer +2: cmp r2, r1 @ any more? + blo 1b +3: mov r0, r1 @ no free bits + mov pc, lr //ENDPROC(_find_first_bit_le) /* @@ -95,87 +81,87 @@ _find_first_bit_le: */ .globl _find_next_bit_le _find_next_bit_le: - teq r1, #0 - beq 3b - ands ip, r2, #7 - beq 1b @ If new byte, goto old routine - ldrb r3, [r0, r2, lsr #3] - lsr r3, r2, #3 - ldrb r3, [r0, r3] - movs r3, r3, lsr ip @ shift off unused bits - bne .L_found - orr r2, r2, #7 @ if zero, then no bits here - add r2, r2, #1 @ align bit pointer - b 2b @ loop for next bit + teq r1, #0 + beq 3b + ands ip, r2, #7 + beq 1b @ If new byte, goto old routine + ldrb r3, [r0, r2, lsr #3] + lsr r3, r2, #3 + ldrb r3, [r0, r3] + movs r3, r3, lsr ip @ shift off unused bits + bne .L_found + orr r2, r2, #7 @ if zero, then no bits here + add r2, r2, #1 @ align bit pointer + b 2b @ loop for next bit //ENDPROC(_find_next_bit_le) #ifdef __ARMEB__ ENTRY(_find_first_zero_bit_be) - teq r1, #0 - beq 3f - mov r2, #0 -1: eor r3, r2, #0x18 @ big endian byte ordering - ARM( ldrb r3, [r0, r3, lsr #3] ) - THUMB( lsr r3, #3 ) - THUMB( ldrb r3, [r0, r3] ) - eors r3, r3, #0xff @ invert bits - bne .L_found @ any now set - found zero bit - add r2, r2, #8 @ next bit pointer -2: cmp r2, r1 @ any more? - blo 1b -3: mov r0, r1 @ no free bits - mov pc, lr + teq r1, #0 + beq 3f + mov r2, #0 +1: eor r3, r2, #0x18 @ big endian byte ordering + ARM( ldrb r3, [r0, r3, lsr #3] ) + THUMB( lsr r3, #3 ) + THUMB( ldrb r3, [r0, r3] ) + eors r3, r3, #0xff @ invert bits + bne .L_found @ any now set - found zero bit + add r2, r2, #8 @ next bit pointer +2: cmp r2, r1 @ any more? + blo 1b +3: mov r0, r1 @ no free bits + mov pc, lr ENDPROC(_find_first_zero_bit_be) ENTRY(_find_next_zero_bit_be) - teq r1, #0 - beq 3b - ands ip, r2, #7 - beq 1b @ If new byte, goto old routine - eor r3, r2, #0x18 @ big endian byte ordering - ARM( ldrb r3, [r0, r3, lsr #3] ) - THUMB( lsr r3, #3 ) - THUMB( ldrb r3, [r0, r3] ) - eor r3, r3, #0xff @ now looking for a 1 bit - movs r3, r3, lsr ip @ shift off unused bits - bne .L_found - orr r2, r2, #7 @ if zero, then no bits here - add r2, r2, #1 @ align bit pointer - b 2b @ loop for next bit + teq r1, #0 + beq 3b + ands ip, r2, #7 + beq 1b @ If new byte, goto old routine + eor r3, r2, #0x18 @ big endian byte ordering + ARM( ldrb r3, [r0, r3, lsr #3] ) + THUMB( lsr r3, #3 ) + THUMB( ldrb r3, [r0, r3] ) + eor r3, r3, #0xff @ now looking for a 1 bit + movs r3, r3, lsr ip @ shift off unused bits + bne .L_found + orr r2, r2, #7 @ if zero, then no bits here + add r2, r2, #1 @ align bit pointer + b 2b @ loop for next bit ENDPROC(_find_next_zero_bit_be) ENTRY(_find_first_bit_be) - teq r1, #0 - beq 3f - mov r2, #0 -1: eor r3, r2, #0x18 @ big endian byte ordering - ARM( ldrb r3, [r0, r3, lsr #3] ) - THUMB( lsr r3, #3 ) - THUMB( ldrb r3, [r0, r3] ) - movs r3, r3 - bne .L_found @ any now set - found zero bit - add r2, r2, #8 @ next bit pointer -2: cmp r2, r1 @ any more? - blo 1b -3: mov r0, r1 @ no free bits - mov pc, lr + teq r1, #0 + beq 3f + mov r2, #0 +1: eor r3, r2, #0x18 @ big endian byte ordering + ARM( ldrb r3, [r0, r3, lsr #3] ) + THUMB( lsr r3, #3 ) + THUMB( ldrb r3, [r0, r3] ) + movs r3, r3 + bne .L_found @ any now set - found zero bit + add r2, r2, #8 @ next bit pointer +2: cmp r2, r1 @ any more? + blo 1b +3: mov r0, r1 @ no free bits + mov pc, lr ENDPROC(_find_first_bit_be) ENTRY(_find_next_bit_be) - teq r1, #0 - beq 3b - ands ip, r2, #7 - beq 1b @ If new byte, goto old routine - eor r3, r2, #0x18 @ big endian byte ordering - ARM( ldrb r3, [r0, r3, lsr #3] ) - THUMB( lsr r3, #3 ) - THUMB( ldrb r3, [r0, r3] ) - movs r3, r3, lsr ip @ shift off unused bits - bne .L_found - orr r2, r2, #7 @ if zero, then no bits here - add r2, r2, #1 @ align bit pointer - b 2b @ loop for next bit + teq r1, #0 + beq 3b + ands ip, r2, #7 + beq 1b @ If new byte, goto old routine + eor r3, r2, #0x18 @ big endian byte ordering + ARM( ldrb r3, [r0, r3, lsr #3] ) + THUMB( lsr r3, #3 ) + THUMB( ldrb r3, [r0, r3] ) + movs r3, r3, lsr ip @ shift off unused bits + bne .L_found + orr r2, r2, #7 @ if zero, then no bits here + add r2, r2, #1 @ align bit pointer + b 2b @ loop for next bit ENDPROC(_find_next_bit_be) #endif @@ -185,23 +171,23 @@ ENDPROC(_find_next_bit_be) */ .L_found: #if 1 //__LINUX_ARM_ARCH__ >= 5 - rsb r0, r3, #0 - and r3, r3, r0 - clz r3, r3 - rsb r3, r3, #31 - add r0, r2, r3 + rsb r0, r3, #0 + and r3, r3, r0 + clz r3, r3 + rsb r3, r3, #31 + add r0, r2, r3 #else - tst r3, #0x0f - addeq r2, r2, #4 - movne r3, r3, lsl #4 - tst r3, #0x30 - addeq r2, r2, #2 - movne r3, r3, lsl #2 - tst r3, #0x40 - addeq r2, r2, #1 - mov r0, r2 + tst r3, #0x0f + addeq r2, r2, #4 + movne r3, r3, lsl #4 + tst r3, #0x30 + addeq r2, r2, #2 + movne r3, r3, lsl #2 + tst r3, #0x40 + addeq r2, r2, #1 + mov r0, r2 #endif - cmp r1, r0 @ Clamp to maxbit - movlo r0, r1 - mov pc, lr + cmp r1, r0 @ Clamp to maxbit + movlo r0, r1 + mov pc, lr diff --git a/bsp/dm365/platform/interrupt.c b/bsp/dm365/platform/interrupt.c index eee5709da0..6334072bcd 100644 --- a/bsp/dm365/platform/interrupt.c +++ b/bsp/dm365/platform/interrupt.c @@ -1,25 +1,11 @@ /* - * File : interrupt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ @@ -27,7 +13,7 @@ #include #include "dm36x.h" -#define MAX_HANDLERS 64 +#define MAX_HANDLERS 64 extern rt_uint32_t rt_interrupt_nest; @@ -37,95 +23,95 @@ struct rt_irq_desc irq_desc[MAX_HANDLERS]; rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; rt_uint32_t rt_thread_switch_interrupt_flag; -#define IRQ_BIT(irq) ((irq) & 0x1f) +#define IRQ_BIT(irq) ((irq) & 0x1f) -#define FIQ_REG0_OFFSET 0x0000 -#define FIQ_REG1_OFFSET 0x0004 -#define IRQ_REG0_OFFSET 0x0008 -#define IRQ_REG1_OFFSET 0x000C -#define IRQ_ENT_REG0_OFFSET 0x0018 -#define IRQ_ENT_REG1_OFFSET 0x001C -#define IRQ_INCTL_REG_OFFSET 0x0020 -#define IRQ_EABASE_REG_OFFSET 0x0024 -#define IRQ_INTPRI0_REG_OFFSET 0x0030 -#define IRQ_INTPRI7_REG_OFFSET 0x004C +#define FIQ_REG0_OFFSET 0x0000 +#define FIQ_REG1_OFFSET 0x0004 +#define IRQ_REG0_OFFSET 0x0008 +#define IRQ_REG1_OFFSET 0x000C +#define IRQ_ENT_REG0_OFFSET 0x0018 +#define IRQ_ENT_REG1_OFFSET 0x001C +#define IRQ_INCTL_REG_OFFSET 0x0020 +#define IRQ_EABASE_REG_OFFSET 0x0024 +#define IRQ_INTPRI0_REG_OFFSET 0x0030 +#define IRQ_INTPRI7_REG_OFFSET 0x004C /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ static const rt_uint8_t dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = { - [IRQ_DM3XX_VPSSINT0] = 2, - [IRQ_DM3XX_VPSSINT1] = 6, - [IRQ_DM3XX_VPSSINT2] = 6, - [IRQ_DM3XX_VPSSINT3] = 6, - [IRQ_DM3XX_VPSSINT4] = 6, - [IRQ_DM3XX_VPSSINT5] = 6, - [IRQ_DM3XX_VPSSINT6] = 6, - [IRQ_DM3XX_VPSSINT7] = 7, - [IRQ_DM3XX_VPSSINT8] = 6, - [IRQ_ASQINT] = 6, - [IRQ_DM365_IMXINT0] = 6, - [IRQ_DM3XX_IMCOPINT] = 6, - [IRQ_USBINT] = 4, - [IRQ_DM3XX_RTOINT] = 4, - [IRQ_DM3XX_TINT5] = 7, - [IRQ_DM3XX_TINT6] = 7, - [IRQ_CCINT0] = 5, /* dma */ - [IRQ_DM3XX_SPINT1_0] = 5, /* dma */ - [IRQ_DM3XX_SPINT1_1] = 5, /* dma */ - [IRQ_DM3XX_SPINT2_0] = 5, /* dma */ - [IRQ_DM365_PSCINT] = 7, - [IRQ_DM3XX_SPINT2_1] = 7, - [IRQ_DM3XX_TINT7] = 4, - [IRQ_DM3XX_SDIOINT0] = 7, - [IRQ_DM365_MBXINT] = 7, - [IRQ_DM365_MBRINT] = 7, - [IRQ_DM3XX_MMCINT0] = 7, - [IRQ_DM3XX_MMCINT1] = 7, - [IRQ_DM3XX_PWMINT3] = 7, - [IRQ_DM365_DDRINT] = 7, - [IRQ_DM365_AEMIFINT] = 7, - [IRQ_DM3XX_SDIOINT1] = 4, - [IRQ_DM365_TINT0] = 2, /* clockevent */ - [IRQ_DM365_TINT1] = 2, /* clocksource */ - [IRQ_DM365_TINT2] = 7, /* DSP timer */ - [IRQ_DM365_TINT3] = 7, /* system tick */ - [IRQ_PWMINT0] = 7, - [IRQ_PWMINT1] = 7, - [IRQ_DM365_PWMINT2] = 7, - [IRQ_DM365_IICINT] = 3, - [IRQ_UARTINT0] = 3, - [IRQ_UARTINT1] = 3, - [IRQ_DM3XX_SPINT0_0] = 3, - [IRQ_DM3XX_SPINT0_1] = 3, - [IRQ_DM3XX_GPIO0] = 3, - [IRQ_DM3XX_GPIO1] = 7, - [IRQ_DM3XX_GPIO2] = 4, - [IRQ_DM3XX_GPIO3] = 4, - [IRQ_DM3XX_GPIO4] = 7, - [IRQ_DM3XX_GPIO5] = 7, - [IRQ_DM3XX_GPIO6] = 7, - [IRQ_DM3XX_GPIO7] = 7, - [IRQ_DM3XX_GPIO8] = 7, - [IRQ_DM3XX_GPIO9] = 7, - [IRQ_DM365_GPIO10] = 7, - [IRQ_DM365_GPIO11] = 7, - [IRQ_DM365_GPIO12] = 7, - [IRQ_DM365_GPIO13] = 7, - [IRQ_DM365_GPIO14] = 7, - [IRQ_DM365_GPIO15] = 7, - [IRQ_DM365_KEYINT] = 7, - [IRQ_DM365_COMMTX] = 7, - [IRQ_DM365_COMMRX] = 7, - [IRQ_EMUINT] = 7, + [IRQ_DM3XX_VPSSINT0] = 2, + [IRQ_DM3XX_VPSSINT1] = 6, + [IRQ_DM3XX_VPSSINT2] = 6, + [IRQ_DM3XX_VPSSINT3] = 6, + [IRQ_DM3XX_VPSSINT4] = 6, + [IRQ_DM3XX_VPSSINT5] = 6, + [IRQ_DM3XX_VPSSINT6] = 6, + [IRQ_DM3XX_VPSSINT7] = 7, + [IRQ_DM3XX_VPSSINT8] = 6, + [IRQ_ASQINT] = 6, + [IRQ_DM365_IMXINT0] = 6, + [IRQ_DM3XX_IMCOPINT] = 6, + [IRQ_USBINT] = 4, + [IRQ_DM3XX_RTOINT] = 4, + [IRQ_DM3XX_TINT5] = 7, + [IRQ_DM3XX_TINT6] = 7, + [IRQ_CCINT0] = 5, /* dma */ + [IRQ_DM3XX_SPINT1_0] = 5, /* dma */ + [IRQ_DM3XX_SPINT1_1] = 5, /* dma */ + [IRQ_DM3XX_SPINT2_0] = 5, /* dma */ + [IRQ_DM365_PSCINT] = 7, + [IRQ_DM3XX_SPINT2_1] = 7, + [IRQ_DM3XX_TINT7] = 4, + [IRQ_DM3XX_SDIOINT0] = 7, + [IRQ_DM365_MBXINT] = 7, + [IRQ_DM365_MBRINT] = 7, + [IRQ_DM3XX_MMCINT0] = 7, + [IRQ_DM3XX_MMCINT1] = 7, + [IRQ_DM3XX_PWMINT3] = 7, + [IRQ_DM365_DDRINT] = 7, + [IRQ_DM365_AEMIFINT] = 7, + [IRQ_DM3XX_SDIOINT1] = 4, + [IRQ_DM365_TINT0] = 2, /* clockevent */ + [IRQ_DM365_TINT1] = 2, /* clocksource */ + [IRQ_DM365_TINT2] = 7, /* DSP timer */ + [IRQ_DM365_TINT3] = 7, /* system tick */ + [IRQ_PWMINT0] = 7, + [IRQ_PWMINT1] = 7, + [IRQ_DM365_PWMINT2] = 7, + [IRQ_DM365_IICINT] = 3, + [IRQ_UARTINT0] = 3, + [IRQ_UARTINT1] = 3, + [IRQ_DM3XX_SPINT0_0] = 3, + [IRQ_DM3XX_SPINT0_1] = 3, + [IRQ_DM3XX_GPIO0] = 3, + [IRQ_DM3XX_GPIO1] = 7, + [IRQ_DM3XX_GPIO2] = 4, + [IRQ_DM3XX_GPIO3] = 4, + [IRQ_DM3XX_GPIO4] = 7, + [IRQ_DM3XX_GPIO5] = 7, + [IRQ_DM3XX_GPIO6] = 7, + [IRQ_DM3XX_GPIO7] = 7, + [IRQ_DM3XX_GPIO8] = 7, + [IRQ_DM3XX_GPIO9] = 7, + [IRQ_DM365_GPIO10] = 7, + [IRQ_DM365_GPIO11] = 7, + [IRQ_DM365_GPIO12] = 7, + [IRQ_DM365_GPIO13] = 7, + [IRQ_DM365_GPIO14] = 7, + [IRQ_DM365_GPIO15] = 7, + [IRQ_DM365_KEYINT] = 7, + [IRQ_DM365_COMMTX] = 7, + [IRQ_DM365_COMMRX] = 7, + [IRQ_EMUINT] = 7, }; static inline unsigned int davinci_irq_readl(int offset) { - return davinci_readl(DAVINCI_ARM_INTC_BASE + offset); + return davinci_readl(DAVINCI_ARM_INTC_BASE + offset); } static inline void davinci_irq_writel(unsigned long value, int offset) { - davinci_writel(value, DAVINCI_ARM_INTC_BASE + offset); + davinci_writel(value, DAVINCI_ARM_INTC_BASE + offset); } /** @@ -135,8 +121,8 @@ static inline void davinci_irq_writel(unsigned long value, int offset) rt_isr_handler_t rt_hw_interrupt_handle(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); - return RT_NULL; + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + return RT_NULL; } /** @@ -144,59 +130,59 @@ rt_isr_handler_t rt_hw_interrupt_handle(int vector, void *param) */ void rt_hw_interrupt_init(void) { - int i; - register rt_uint32_t idx; - const rt_uint8_t *priority; - priority = dm365_default_priorities; + int i; + register rt_uint32_t idx; + const rt_uint8_t *priority; + priority = dm365_default_priorities; - /* Clear all interrupt requests */ - davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); - davinci_irq_writel(~0x0, FIQ_REG1_OFFSET); - davinci_irq_writel(~0x0, IRQ_REG0_OFFSET); - davinci_irq_writel(~0x0, IRQ_REG1_OFFSET); + /* Clear all interrupt requests */ + davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); + davinci_irq_writel(~0x0, FIQ_REG1_OFFSET); + davinci_irq_writel(~0x0, IRQ_REG0_OFFSET); + davinci_irq_writel(~0x0, IRQ_REG1_OFFSET); - /* Disable all interrupts */ - davinci_irq_writel(0x0, IRQ_ENT_REG0_OFFSET); - davinci_irq_writel(0x0, IRQ_ENT_REG1_OFFSET); + /* Disable all interrupts */ + davinci_irq_writel(0x0, IRQ_ENT_REG0_OFFSET); + davinci_irq_writel(0x0, IRQ_ENT_REG1_OFFSET); - /* Interrupts disabled immediately, IRQ entry reflects all */ - davinci_irq_writel(0x0, IRQ_INCTL_REG_OFFSET); + /* Interrupts disabled immediately, IRQ entry reflects all */ + davinci_irq_writel(0x0, IRQ_INCTL_REG_OFFSET); - /* we don't use the hardware vector table, just its entry addresses */ - davinci_irq_writel(0, IRQ_EABASE_REG_OFFSET); + /* we don't use the hardware vector table, just its entry addresses */ + davinci_irq_writel(0, IRQ_EABASE_REG_OFFSET); - /* Clear all interrupt requests */ - davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); - davinci_irq_writel(~0x0, FIQ_REG1_OFFSET); - davinci_irq_writel(~0x0, IRQ_REG0_OFFSET); - davinci_irq_writel(~0x0, IRQ_REG1_OFFSET); + /* Clear all interrupt requests */ + davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); + davinci_irq_writel(~0x0, FIQ_REG1_OFFSET); + davinci_irq_writel(~0x0, IRQ_REG0_OFFSET); + davinci_irq_writel(~0x0, IRQ_REG1_OFFSET); - for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) { - unsigned j; - rt_uint32_t pri; + for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) { + unsigned j; + rt_uint32_t pri; - for (j = 0, pri = 0; j < 32; j += 4, priority++) - pri |= (*priority & 0x07) << j; - davinci_irq_writel(pri, i); - } + for (j = 0, pri = 0; j < 32; j += 4, priority++) + pri |= (*priority & 0x07) << j; + davinci_irq_writel(pri, i); + } - /* init exceptions table */ - for(idx=0; idx < MAX_HANDLERS; idx++) - { - - irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle; - irq_desc[idx].param = RT_NULL; - #ifdef RT_USING_INTERRUPT_INFO - rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default"); - irq_desc[idx].counter = 0; - #endif - } + /* init exceptions table */ + for(idx=0; idx < MAX_HANDLERS; idx++) + { - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle; + irq_desc[idx].param = RT_NULL; + #ifdef RT_USING_INTERRUPT_INFO + rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default"); + irq_desc[idx].counter = 0; + #endif + } + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } /** @@ -205,20 +191,20 @@ void rt_hw_interrupt_init(void) */ void rt_hw_interrupt_mask(int irq) { - unsigned int mask; - rt_uint32_t l; + unsigned int mask; + rt_uint32_t l; - mask = 1 << IRQ_BIT(irq); + mask = 1 << IRQ_BIT(irq); - if (irq > 31) { - l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET); - l &= ~mask; - davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET); - } else { - l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET); - l &= ~mask; - davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET); - } + if (irq > 31) { + l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET); + l &= ~mask; + davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET); + } else { + l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET); + l &= ~mask; + davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET); + } } /** @@ -227,20 +213,20 @@ void rt_hw_interrupt_mask(int irq) */ void rt_hw_interrupt_umask(int irq) { - unsigned int mask; - rt_uint32_t l; + unsigned int mask; + rt_uint32_t l; - mask = 1 << IRQ_BIT(irq); + mask = 1 << IRQ_BIT(irq); - if (irq > 31) { - l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET); - l |= mask; - davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET); - } else { - l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET); - l |= mask; - davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET); - } + if (irq > 31) { + l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET); + l |= mask; + davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET); + } else { + l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET); + l |= mask; + davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET); + } } /** @@ -253,25 +239,25 @@ void rt_hw_interrupt_umask(int irq) */ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) + void *param, const char *name) { - rt_isr_handler_t old_handler = RT_NULL; + rt_isr_handler_t old_handler = RT_NULL; - if(vector < MAX_HANDLERS) - { - old_handler = irq_desc[vector].handler; - if (handler != RT_NULL) - { - irq_desc[vector].handler = (rt_isr_handler_t)handler; - irq_desc[vector].param = param; - #ifdef RT_USING_INTERRUPT_INFO - rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name); - irq_desc[vector].counter = 0; - #endif - } - } + if(vector < MAX_HANDLERS) + { + old_handler = irq_desc[vector].handler; + if (handler != RT_NULL) + { + irq_desc[vector].handler = (rt_isr_handler_t)handler; + irq_desc[vector].param = param; + #ifdef RT_USING_INTERRUPT_INFO + rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name); + irq_desc[vector].counter = 0; + #endif + } + } - return old_handler; + return old_handler; } @@ -279,16 +265,16 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, #ifdef RT_USING_INTERRUPT_INFO void list_irq(void) { - int irq; - - rt_kprintf("number\tcount\tname\n"); - for (irq = 0; irq < MAX_HANDLERS; irq++) - { - if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default"))) - { - rt_kprintf("%02ld: %10ld %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name); - } - } + int irq; + + rt_kprintf("number\tcount\tname\n"); + for (irq = 0; irq < MAX_HANDLERS; irq++) + { + if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default"))) + { + rt_kprintf("%02ld: %10ld %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name); + } + } } #include diff --git a/bsp/dm365/platform/irqs.h b/bsp/dm365/platform/irqs.h index b0e345f923..b8c4ecc9e4 100644 --- a/bsp/dm365/platform/irqs.h +++ b/bsp/dm365/platform/irqs.h @@ -1,25 +1,11 @@ /* - * File : irqs.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ #ifndef __DM36X_IRQS_H__ @@ -32,7 +18,7 @@ extern "C" { /* Base address */ #define DAVINCI_ARM_INTC_BASE 0x01C48000 -#define DAVINCI_N_AINTC_IRQ 64 +#define DAVINCI_N_AINTC_IRQ 64 /* Interrupt lines */ #define IRQ_VDINT0 0 @@ -102,100 +88,100 @@ extern "C" { /* * Base Interrupts common across DM355 and DM365 */ -#define IRQ_DM3XX_VPSSINT0 0 -#define IRQ_DM3XX_VPSSINT1 1 -#define IRQ_DM3XX_VPSSINT2 2 -#define IRQ_DM3XX_VPSSINT3 3 -#define IRQ_DM3XX_VPSSINT4 4 -#define IRQ_DM3XX_VPSSINT5 5 -#define IRQ_DM3XX_VPSSINT6 6 -#define IRQ_DM3XX_VPSSINT7 7 -#define IRQ_DM3XX_VPSSINT8 8 -#define IRQ_DM3XX_IMCOPINT 11 -#define IRQ_DM3XX_RTOINT 13 -#define IRQ_DM3XX_TINT4 13 -#define IRQ_DM3XX_TINT2_TINT12 13 -#define IRQ_DM3XX_TINT5 14 -#define IRQ_DM3XX_TINT2_TINT34 14 -#define IRQ_DM3XX_TINT6 15 -#define IRQ_DM3XX_TINT3_TINT12 15 -#define IRQ_DM3XX_SPINT1_0 17 -#define IRQ_DM3XX_SPINT1_1 18 -#define IRQ_DM3XX_SPINT2_0 19 -#define IRQ_DM3XX_SPINT2_1 21 -#define IRQ_DM3XX_TINT7 22 -#define IRQ_DM3XX_TINT3_TINT34 22 -#define IRQ_DM3XX_SDIOINT0 23 -#define IRQ_DM3XX_MMCINT0 26 -#define IRQ_DM3XX_MSINT 26 -#define IRQ_DM3XX_MMCINT1 27 -#define IRQ_DM3XX_PWMINT3 28 -#define IRQ_DM3XX_SDIOINT1 31 -#define IRQ_DM3XX_SPINT0_0 42 -#define IRQ_DM3XX_SPINT0_1 43 -#define IRQ_DM3XX_GPIO0 44 -#define IRQ_DM3XX_GPIO1 45 -#define IRQ_DM3XX_GPIO2 46 -#define IRQ_DM3XX_GPIO3 47 -#define IRQ_DM3XX_GPIO4 48 -#define IRQ_DM3XX_GPIO5 49 -#define IRQ_DM3XX_GPIO6 50 -#define IRQ_DM3XX_GPIO7 51 -#define IRQ_DM3XX_GPIO8 52 -#define IRQ_DM3XX_GPIO9 53 +#define IRQ_DM3XX_VPSSINT0 0 +#define IRQ_DM3XX_VPSSINT1 1 +#define IRQ_DM3XX_VPSSINT2 2 +#define IRQ_DM3XX_VPSSINT3 3 +#define IRQ_DM3XX_VPSSINT4 4 +#define IRQ_DM3XX_VPSSINT5 5 +#define IRQ_DM3XX_VPSSINT6 6 +#define IRQ_DM3XX_VPSSINT7 7 +#define IRQ_DM3XX_VPSSINT8 8 +#define IRQ_DM3XX_IMCOPINT 11 +#define IRQ_DM3XX_RTOINT 13 +#define IRQ_DM3XX_TINT4 13 +#define IRQ_DM3XX_TINT2_TINT12 13 +#define IRQ_DM3XX_TINT5 14 +#define IRQ_DM3XX_TINT2_TINT34 14 +#define IRQ_DM3XX_TINT6 15 +#define IRQ_DM3XX_TINT3_TINT12 15 +#define IRQ_DM3XX_SPINT1_0 17 +#define IRQ_DM3XX_SPINT1_1 18 +#define IRQ_DM3XX_SPINT2_0 19 +#define IRQ_DM3XX_SPINT2_1 21 +#define IRQ_DM3XX_TINT7 22 +#define IRQ_DM3XX_TINT3_TINT34 22 +#define IRQ_DM3XX_SDIOINT0 23 +#define IRQ_DM3XX_MMCINT0 26 +#define IRQ_DM3XX_MSINT 26 +#define IRQ_DM3XX_MMCINT1 27 +#define IRQ_DM3XX_PWMINT3 28 +#define IRQ_DM3XX_SDIOINT1 31 +#define IRQ_DM3XX_SPINT0_0 42 +#define IRQ_DM3XX_SPINT0_1 43 +#define IRQ_DM3XX_GPIO0 44 +#define IRQ_DM3XX_GPIO1 45 +#define IRQ_DM3XX_GPIO2 46 +#define IRQ_DM3XX_GPIO3 47 +#define IRQ_DM3XX_GPIO4 48 +#define IRQ_DM3XX_GPIO5 49 +#define IRQ_DM3XX_GPIO6 50 +#define IRQ_DM3XX_GPIO7 51 +#define IRQ_DM3XX_GPIO8 52 +#define IRQ_DM3XX_GPIO9 53 /* DaVinci DM365-specific Interrupts */ -#define IRQ_DM365_INSFINT 7 -#define IRQ_DM365_IMXINT1 8 -#define IRQ_DM365_IMXINT0 10 -#define IRQ_DM365_KLD_ARMINT 10 -#define IRQ_DM365_CCERRINT 17 -#define IRQ_DM365_TCERRINT0 18 -#define IRQ_DM365_SPINT2_0 19 -#define IRQ_DM365_PSCINT 20 -#define IRQ_DM365_TVINT 20 -#define IRQ_DM365_SPINT4_0 21 -#define IRQ_DM365_MBXINT 24 -#define IRQ_DM365_VCINT 24 -#define IRQ_DM365_MBRINT 25 -#define IRQ_DM365_TINT9 28 -#define IRQ_DM365_TINT4_TINT34 28 -#define IRQ_DM365_DDRINT 29 -#define IRQ_DM365_RTCINT 29 -#define IRQ_DM365_AEMIFINT 30 -#define IRQ_DM365_HPIINT 30 -#define IRQ_DM365_TINT0 32 -#define IRQ_DM365_TINT0_TINT12 32 -#define IRQ_DM365_TINT1 33 -#define IRQ_DM365_TINT0_TINT34 33 -#define IRQ_DM365_TINT2 34 -#define IRQ_DM365_TINT1_TINT12 34 -#define IRQ_DM365_TINT3 35 -#define IRQ_DM365_TINT1_TINT34 35 -#define IRQ_DM365_PWMINT2 38 -#define IRQ_DM365_TINT8 38 -#define IRQ_DM365_TINT4_TINT12 38 -#define IRQ_DM365_IICINT 39 -#define IRQ_DM365_SPINT3_0 43 -#define IRQ_DM365_EMAC_RXTHRESH 52 -#define IRQ_DM365_EMAC_RXPULSE 53 -#define IRQ_DM365_GPIO10 54 -#define IRQ_DM365_EMAC_TXPULSE 54 -#define IRQ_DM365_GPIO11 55 +#define IRQ_DM365_INSFINT 7 +#define IRQ_DM365_IMXINT1 8 +#define IRQ_DM365_IMXINT0 10 +#define IRQ_DM365_KLD_ARMINT 10 +#define IRQ_DM365_CCERRINT 17 +#define IRQ_DM365_TCERRINT0 18 +#define IRQ_DM365_SPINT2_0 19 +#define IRQ_DM365_PSCINT 20 +#define IRQ_DM365_TVINT 20 +#define IRQ_DM365_SPINT4_0 21 +#define IRQ_DM365_MBXINT 24 +#define IRQ_DM365_VCINT 24 +#define IRQ_DM365_MBRINT 25 +#define IRQ_DM365_TINT9 28 +#define IRQ_DM365_TINT4_TINT34 28 +#define IRQ_DM365_DDRINT 29 +#define IRQ_DM365_RTCINT 29 +#define IRQ_DM365_AEMIFINT 30 +#define IRQ_DM365_HPIINT 30 +#define IRQ_DM365_TINT0 32 +#define IRQ_DM365_TINT0_TINT12 32 +#define IRQ_DM365_TINT1 33 +#define IRQ_DM365_TINT0_TINT34 33 +#define IRQ_DM365_TINT2 34 +#define IRQ_DM365_TINT1_TINT12 34 +#define IRQ_DM365_TINT3 35 +#define IRQ_DM365_TINT1_TINT34 35 +#define IRQ_DM365_PWMINT2 38 +#define IRQ_DM365_TINT8 38 +#define IRQ_DM365_TINT4_TINT12 38 +#define IRQ_DM365_IICINT 39 +#define IRQ_DM365_SPINT3_0 43 +#define IRQ_DM365_EMAC_RXTHRESH 52 +#define IRQ_DM365_EMAC_RXPULSE 53 +#define IRQ_DM365_GPIO10 54 +#define IRQ_DM365_EMAC_TXPULSE 54 +#define IRQ_DM365_GPIO11 55 #define IRQ_DM365_EMAC_MISCPULSE 55 -#define IRQ_DM365_GPIO12 56 -#define IRQ_DM365_PWRGIO0 56 -#define IRQ_DM365_GPIO13 57 -#define IRQ_DM365_PWRGIO1 57 -#define IRQ_DM365_GPIO14 58 -#define IRQ_DM365_PWRGIO2 58 -#define IRQ_DM365_GPIO15 59 -#define IRQ_DM365_ADCINT 59 -#define IRQ_DM365_KEYINT 60 -#define IRQ_DM365_COMMTX 61 -#define IRQ_DM365_TCERRINT2 61 -#define IRQ_DM365_COMMRX 62 -#define IRQ_DM365_TCERRINT3 62 +#define IRQ_DM365_GPIO12 56 +#define IRQ_DM365_PWRGIO0 56 +#define IRQ_DM365_GPIO13 57 +#define IRQ_DM365_PWRGIO1 57 +#define IRQ_DM365_GPIO14 58 +#define IRQ_DM365_PWRGIO2 58 +#define IRQ_DM365_GPIO15 59 +#define IRQ_DM365_ADCINT 59 +#define IRQ_DM365_KEYINT 60 +#define IRQ_DM365_COMMTX 61 +#define IRQ_DM365_TCERRINT2 61 +#define IRQ_DM365_COMMRX 62 +#define IRQ_DM365_TCERRINT3 62 #ifdef __cplusplus diff --git a/bsp/dm365/platform/psc.c b/bsp/dm365/platform/psc.c index 0fbed347f6..b2e0a90197 100644 --- a/bsp/dm365/platform/psc.c +++ b/bsp/dm365/platform/psc.c @@ -1,25 +1,11 @@ /* - * File : psc.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ #include "dm36x.h" @@ -33,13 +19,13 @@ * ------------------------------------------------------------------------ */ void psc_change_state(int id, int state) { - rt_uint32_t mdstat, mdctl; + rt_uint32_t mdstat, mdctl; - if (id > DAVINCI_DM365_LPSC_KALEIDO) - return; + if (id > DAVINCI_DM365_LPSC_KALEIDO) + return; - mdstat = PSC_MDSTAT_BASE + (id * 4); - mdctl = PSC_MDCTL_BASE + (id * 4); + mdstat = PSC_MDSTAT_BASE + (id * 4); + mdctl = PSC_MDCTL_BASE + (id * 4); /* * Step 0 - Ignore request if the state is already set as is diff --git a/bsp/dm365/platform/psc.h b/bsp/dm365/platform/psc.h index 10068a9553..116b7b2dd7 100644 --- a/bsp/dm365/platform/psc.h +++ b/bsp/dm365/platform/psc.h @@ -1,25 +1,11 @@ /* - * File : psc.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ #ifndef __DM36X_PSC_H @@ -31,69 +17,69 @@ extern "C" { /* PSC register offsets */ -#define EPCPR 0x070 -#define PTCMD 0x120 -#define PTSTAT 0x128 -#define PDSTAT 0x200 -#define PDCTL1 0x304 -#define MDSTAT(n) (0x800 + (n) * 4) -#define MDCTL(n) (0xA00 + (n) * 4) +#define EPCPR 0x070 +#define PTCMD 0x120 +#define PTSTAT 0x128 +#define PDSTAT 0x200 +#define PDCTL1 0x304 +#define MDSTAT(n) (0x800 + (n) * 4) +#define MDCTL(n) (0xA00 + (n) * 4) /* Power and Sleep Controller (PSC) Domains */ -#define DAVINCI_GPSC_ARMDOMAIN 0 -#define DAVINCI_GPSC_DSPDOMAIN 1 +#define DAVINCI_GPSC_ARMDOMAIN 0 +#define DAVINCI_GPSC_DSPDOMAIN 1 -#define DAVINCI_DM365_LPSC_TPCC 0 -#define DAVINCI_DM365_LPSC_TPTC0 1 -#define DAVINCI_DM365_LPSC_TPTC1 2 -#define DAVINCI_DM365_LPSC_TPTC2 3 -#define DAVINCI_DM365_LPSC_TPTC3 4 -#define DAVINCI_DM365_LPSC_TIMER3 5 -#define DAVINCI_DM365_LPSC_SPI1 6 -#define DAVINCI_DM365_LPSC_MMC_SD1 7 -#define DAVINCI_DM365_LPSC_McBSP 8 -#define DAVINCI_DM365_LPSC_USB 9 -#define DAVINCI_DM365_LPSC_PWM3 10 -#define DAVINCI_DM365_LPSC_SPI2 11 -#define DAVINCI_DM365_LPSC_RTO 12 -#define DAVINCI_DM365_LPSC_DDR_EMIF 13 -#define DAVINCI_DM365_LPSC_AEMIF 14 -#define DAVINCI_DM365_LPSC_MMC_SD 15 -#define DAVINCI_DM365_LPSC_MMC_SD0 15 -#define DAVINCI_DM365_LPSC_MEMSTICK 16 -#define DAVINCI_DM365_LPSC_TIMER4 17 -#define DAVINCI_DM365_LPSC_I2C 18 -#define DAVINCI_DM365_LPSC_UART0 19 -#define DAVINCI_DM365_LPSC_UART1 20 -#define DAVINCI_DM365_LPSC_UHPI 21 -#define DAVINCI_DM365_LPSC_SPI0 22 -#define DAVINCI_DM365_LPSC_PWM0 23 -#define DAVINCI_DM365_LPSC_PWM1 24 -#define DAVINCI_DM365_LPSC_PWM2 25 -#define DAVINCI_DM365_LPSC_GPIO 26 -#define DAVINCI_DM365_LPSC_TIMER0 27 -#define DAVINCI_DM365_LPSC_TIMER1 28 -#define DAVINCI_DM365_LPSC_TIMER2 29 +#define DAVINCI_DM365_LPSC_TPCC 0 +#define DAVINCI_DM365_LPSC_TPTC0 1 +#define DAVINCI_DM365_LPSC_TPTC1 2 +#define DAVINCI_DM365_LPSC_TPTC2 3 +#define DAVINCI_DM365_LPSC_TPTC3 4 +#define DAVINCI_DM365_LPSC_TIMER3 5 +#define DAVINCI_DM365_LPSC_SPI1 6 +#define DAVINCI_DM365_LPSC_MMC_SD1 7 +#define DAVINCI_DM365_LPSC_McBSP 8 +#define DAVINCI_DM365_LPSC_USB 9 +#define DAVINCI_DM365_LPSC_PWM3 10 +#define DAVINCI_DM365_LPSC_SPI2 11 +#define DAVINCI_DM365_LPSC_RTO 12 +#define DAVINCI_DM365_LPSC_DDR_EMIF 13 +#define DAVINCI_DM365_LPSC_AEMIF 14 +#define DAVINCI_DM365_LPSC_MMC_SD 15 +#define DAVINCI_DM365_LPSC_MMC_SD0 15 +#define DAVINCI_DM365_LPSC_MEMSTICK 16 +#define DAVINCI_DM365_LPSC_TIMER4 17 +#define DAVINCI_DM365_LPSC_I2C 18 +#define DAVINCI_DM365_LPSC_UART0 19 +#define DAVINCI_DM365_LPSC_UART1 20 +#define DAVINCI_DM365_LPSC_UHPI 21 +#define DAVINCI_DM365_LPSC_SPI0 22 +#define DAVINCI_DM365_LPSC_PWM0 23 +#define DAVINCI_DM365_LPSC_PWM1 24 +#define DAVINCI_DM365_LPSC_PWM2 25 +#define DAVINCI_DM365_LPSC_GPIO 26 +#define DAVINCI_DM365_LPSC_TIMER0 27 +#define DAVINCI_DM365_LPSC_TIMER1 28 +#define DAVINCI_DM365_LPSC_TIMER2 29 #define DAVINCI_DM365_LPSC_SYSTEM_SUBSYS 30 -#define DAVINCI_DM365_LPSC_ARM 31 -#define DAVINCI_DM365_LPSC_SCR0 33 -#define DAVINCI_DM365_LPSC_SCR1 34 -#define DAVINCI_DM365_LPSC_EMU 35 -#define DAVINCI_DM365_LPSC_CHIPDFT 36 -#define DAVINCI_DM365_LPSC_PBIST 37 -#define DAVINCI_DM365_LPSC_SPI3 38 -#define DAVINCI_DM365_LPSC_SPI4 39 -#define DAVINCI_DM365_LPSC_CPGMAC 40 -#define DAVINCI_DM365_LPSC_RTC 41 -#define DAVINCI_DM365_LPSC_KEYSCAN 42 -#define DAVINCI_DM365_LPSC_ADCIF 43 -#define DAVINCI_DM365_LPSC_VOICE_CODEC 44 -#define DAVINCI_DM365_LPSC_DAC_CLKRES 45 -#define DAVINCI_DM365_LPSC_DAC_CLK 46 -#define DAVINCI_DM365_LPSC_VPSSMSTR 47 -#define DAVINCI_DM365_LPSC_IMCOP 50 -#define DAVINCI_DM365_LPSC_KALEIDO 51 +#define DAVINCI_DM365_LPSC_ARM 31 +#define DAVINCI_DM365_LPSC_SCR0 33 +#define DAVINCI_DM365_LPSC_SCR1 34 +#define DAVINCI_DM365_LPSC_EMU 35 +#define DAVINCI_DM365_LPSC_CHIPDFT 36 +#define DAVINCI_DM365_LPSC_PBIST 37 +#define DAVINCI_DM365_LPSC_SPI3 38 +#define DAVINCI_DM365_LPSC_SPI4 39 +#define DAVINCI_DM365_LPSC_CPGMAC 40 +#define DAVINCI_DM365_LPSC_RTC 41 +#define DAVINCI_DM365_LPSC_KEYSCAN 42 +#define DAVINCI_DM365_LPSC_ADCIF 43 +#define DAVINCI_DM365_LPSC_VOICE_CODEC 44 +#define DAVINCI_DM365_LPSC_DAC_CLKRES 45 +#define DAVINCI_DM365_LPSC_DAC_CLK 46 +#define DAVINCI_DM365_LPSC_VPSSMSTR 47 +#define DAVINCI_DM365_LPSC_IMCOP 50 +#define DAVINCI_DM365_LPSC_KALEIDO 51 #define PSC_ENABLE 3 #define PSC_DISABLE 2 diff --git a/bsp/dm365/platform/reset.c b/bsp/dm365/platform/reset.c index 9d7d549dbf..dc80fac76e 100644 --- a/bsp/dm365/platform/reset.c +++ b/bsp/dm365/platform/reset.c @@ -1,25 +1,11 @@ /* - * File : reset.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ @@ -38,7 +24,7 @@ */ void machine_reset() { - reset_system(); + reset_system(); } /** @@ -58,14 +44,14 @@ FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, reset, restart the system); #ifdef FINSH_USING_MSH int cmd_reset(int argc, char** argv) { - rt_hw_cpu_reset(); - return 0; + rt_hw_cpu_reset(); + return 0; } int cmd_shutdown(int argc, char** argv) { - rt_hw_cpu_shutdown(); - return 0; + rt_hw_cpu_shutdown(); + return 0; } FINSH_FUNCTION_EXPORT_ALIAS(cmd_reset, __cmd_reset, restart the system.); diff --git a/bsp/dm365/platform/start_gcc.S b/bsp/dm365/platform/start_gcc.S index ff926e5a0d..836fb4b28f 100644 --- a/bsp/dm365/platform/start_gcc.S +++ b/bsp/dm365/platform/start_gcc.S @@ -1,21 +1,7 @@ /* - * File : start.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -46,21 +32,21 @@ .equ I_BIT, 0x80 @ when I bit is set, IRQ is disabled .equ F_BIT, 0x40 @ when F bit is set, FIQ is disabled -.equ USERMODE, 0x10 -.equ FIQMODE, 0x11 -.equ IRQMODE, 0x12 -.equ SVCMODE, 0x13 -.equ ABORTMODE, 0x17 -.equ UNDEFMODE, 0x1b -.equ MODEMASK, 0x1f -.equ NOINT, 0xc0 +.equ USERMODE, 0x10 +.equ FIQMODE, 0x11 +.equ IRQMODE, 0x12 +.equ SVCMODE, 0x13 +.equ ABORTMODE, 0x17 +.equ UNDEFMODE, 0x1b +.equ MODEMASK, 0x1f +.equ NOINT, 0xc0 -.equ RAM_BASE, 0x00000000 /*Start address of RAM */ -.equ ROM_BASE, 0x80000000 /*Start address of Flash */ +.equ RAM_BASE, 0x00000000 /*Start address of RAM */ +.equ ROM_BASE, 0x80000000 /*Start address of Flash */ -.equ EINT_ENABLE0, 0x01c48018 -.equ EINT_ENABLE1, 0x01c4801c +.equ EINT_ENABLE0, 0x01c48018 +.equ EINT_ENABLE1, 0x01c4801c /* ************************************************************************* @@ -124,7 +110,7 @@ _rtthread_end: * rtthread bss start and end which are defined in linker script */ .globl _bss_start -_bss_start: +_bss_start: .word __bss_start .globl _bss_end @@ -147,7 +133,7 @@ UNDEFINED_STACK_START: .globl ABORT_STACK_START ABORT_STACK_START: .word _abort_stack_start + CONFIG_STACKSIZE - + .globl _STACK_START _STACK_START: .word _svc_stack_start + 1024 @@ -162,16 +148,16 @@ reset: msr cpsr,r0 /* mask all IRQs by clearing all bits in the INTMRs */ - mov r1, $0 - ldr r0, =EINT_ENABLE0 - str r1, [r0] - ldr r0, =EINT_ENABLE1 - str r1, [r0] + mov r1, $0 + ldr r0, =EINT_ENABLE0 + str r1, [r0] + ldr r0, =EINT_ENABLE1 + str r1, [r0] #if 0 /* set interrupt vector */ ldr r0, _TEXT_BASE - mov r1, #0x00 - add r2, r0, #0x40 /* size, 32bytes */ + mov r1, #0x00 + add r2, r0, #0x40 /* size, 32bytes */ copy_loop: ldmia r0!, {r3-r10} /* copy from source address [r0] */ @@ -212,13 +198,13 @@ ctor_end: /* start RT-Thread Kernel */ ldr pc, _rtthread_startup -_rtthread_startup: +_rtthread_startup: .word rtthread_startup #if defined (__FLASH_BUILD__) -_load_address: +_load_address: .word ROM_BASE + _TEXT_BASE #else -_load_address: +_load_address: .word RAM_BASE + _TEXT_BASE #endif diff --git a/bsp/dm365/platform/system_clock.c b/bsp/dm365/platform/system_clock.c index b4e81e98a2..7d4c58874f 100644 --- a/bsp/dm365/platform/system_clock.c +++ b/bsp/dm365/platform/system_clock.c @@ -1,25 +1,11 @@ /* - * File : system_clock.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ @@ -33,6 +19,6 @@ extern int davinci_clk_init(void); */ void rt_hw_clock_init(void) { - davinci_clk_init(); + davinci_clk_init(); } diff --git a/bsp/dm365/platform/trap.c b/bsp/dm365/platform/trap.c index 169e4da40b..5c5f0272b3 100644 --- a/bsp/dm365/platform/trap.c +++ b/bsp/dm365/platform/trap.c @@ -1,25 +1,11 @@ /* - * File : trap.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2010-11-13 weety first version + * Date Author Notes + * 2010-11-13 weety first version */ @@ -46,13 +32,13 @@ extern long list_thread(void); void rt_hw_show_register (struct rt_hw_register *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); } /** @@ -65,15 +51,15 @@ void rt_hw_show_register (struct rt_hw_register *regs) */ void rt_hw_trap_udef(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("undefined instruction\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_kprintf("undefined instruction\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -87,10 +73,10 @@ void rt_hw_trap_udef(struct rt_hw_register *regs) */ void rt_hw_trap_swi(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("software interrupt\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("software interrupt\n"); + rt_hw_cpu_shutdown(); } /** @@ -103,15 +89,15 @@ void rt_hw_trap_swi(struct rt_hw_register *regs) */ void rt_hw_trap_pabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("prefetch abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_kprintf("prefetch abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -124,30 +110,30 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs) */ void rt_hw_trap_dabt(struct rt_hw_register *regs) { - rt_uint32_t fault_addr; - rt_uint32_t fault_status; - asm volatile ("mrc p15, 0, %0, c6, c0, 0" - : - :"r"(fault_addr) - :"cc"); - rt_kprintf("unhandler access to 0x%08x\n", fault_addr); + rt_uint32_t fault_addr; + rt_uint32_t fault_status; + asm volatile ("mrc p15, 0, %0, c6, c0, 0" + : + :"r"(fault_addr) + :"cc"); + rt_kprintf("unhandler access to 0x%08x\n", fault_addr); - /* read DFSR */ - asm volatile ("MRC p15, 0, %0, c5, c0, 0" - : - :"r"(fault_status) - :"cc"); - rt_kprintf("fault status 0x%08x\n", fault_status); + /* read DFSR */ + asm volatile ("MRC p15, 0, %0, c5, c0, 0" + : + :"r"(fault_status) + :"cc"); + rt_kprintf("fault status 0x%08x\n", fault_status); - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("data abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_kprintf("data abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -159,9 +145,9 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs) */ void rt_hw_trap_resv(struct rt_hw_register *regs) { - rt_kprintf("not used\n"); - rt_hw_show_register(regs); - rt_hw_cpu_shutdown(); + rt_kprintf("not used\n"); + rt_hw_show_register(regs); + rt_hw_cpu_shutdown(); } extern struct rt_irq_desc irq_desc[]; @@ -169,32 +155,32 @@ extern struct rt_irq_desc irq_desc[]; void rt_hw_trap_irq() { - rt_isr_handler_t isr_func; - rt_uint32_t val, irq, mask; - void *param; + rt_isr_handler_t isr_func; + rt_uint32_t val, irq, mask; + void *param; - /* get irq number */ - val = readl(DAVINCI_ARM_INTC_BASE+0x14) - readl(DAVINCI_ARM_INTC_BASE+0x24); - irq = (val >> 2) - 1; - /* clear pending register */ - mask = 1 << (irq & 0x1f); - if (irq > 31) - writel(mask, DAVINCI_ARM_INTC_BASE+0x0c); //IRQ1 - else - writel(mask, DAVINCI_ARM_INTC_BASE+0x08); //IRQ0 - - /* get interrupt service routine */ - isr_func = irq_desc[irq].handler; - param = irq_desc[irq].param; + /* get irq number */ + val = readl(DAVINCI_ARM_INTC_BASE+0x14) - readl(DAVINCI_ARM_INTC_BASE+0x24); + irq = (val >> 2) - 1; + /* clear pending register */ + mask = 1 << (irq & 0x1f); + if (irq > 31) + writel(mask, DAVINCI_ARM_INTC_BASE+0x0c); //IRQ1 + else + writel(mask, DAVINCI_ARM_INTC_BASE+0x08); //IRQ0 - /* turn to interrupt service routine */ - isr_func(irq, param); - irq_desc[irq].counter++; + /* get interrupt service routine */ + isr_func = irq_desc[irq].handler; + param = irq_desc[irq].param; + + /* turn to interrupt service routine */ + isr_func(irq, param); + irq_desc[irq].counter++; } void rt_hw_trap_fiq() { - rt_kprintf("fast interrupt request\n"); + rt_kprintf("fast interrupt request\n"); } /*@}*/ diff --git a/bsp/efm32/EFM32GG_DK3750/dvk.h b/bsp/efm32/EFM32GG_DK3750/dvk.h index 41af36b264..870c8b4121 100644 --- a/bsp/efm32/EFM32GG_DK3750/dvk.h +++ b/bsp/efm32/EFM32GG_DK3750/dvk.h @@ -164,7 +164,7 @@ int DVK_BRD3600A_usbVBUSGetOCFlagState(void); /* For "backward compatibility" with DVK */ /** DVK_enablePeripheral() backward compatibility */ -#define DVK_enablePeripheral(X) DVK_peripheralAccess(X, true) +#define DVK_enablePeripheral(X) DVK_peripheralAccess(X, true) /** DVK_disablePeripheral() backward compatibility */ #define DVK_disablePeripheral(X) DVK_peripheralAccess(X, false) @@ -193,7 +193,7 @@ __STATIC_INLINE uint16_t DVK_EBI_readRegister(volatile uint16_t *addr) /**************************************************************************//** * @brief Read data from 16-bit board control register * @param addr Register to read - * @return Value of board controller register + * @return Value of board controller register *****************************************************************************/ __STATIC_INLINE uint16_t DVK_readRegister(volatile uint16_t *addr) { diff --git a/bsp/efm32/EFM32GG_DK3750/trace.c b/bsp/efm32/EFM32GG_DK3750/trace.c index 5450de0270..2d5ffd71a5 100644 --- a/bsp/efm32/EFM32GG_DK3750/trace.c +++ b/bsp/efm32/EFM32GG_DK3750/trace.c @@ -125,7 +125,7 @@ void TRACE_SWOSetup(void) /**************************************************************************//** * @brief Profiler configuration for EFM32GG990F11024/EFM32GG-DK3750 * @return true if energyAware Profiler/SWO is enabled, false if not - * @note If first word of the user page is zero, this will not + * @note If first word of the user page is zero, this will not * enable SWO profiler output *****************************************************************************/ bool TRACE_ProfilerSetup(void) @@ -141,7 +141,7 @@ bool TRACE_ProfilerSetup(void) { TRACE_SWOSetup(); return true; - } + } } /** @} (end group BSP) */ diff --git a/bsp/efm32/EFM32GG_DK3750/trace.h b/bsp/efm32/EFM32GG_DK3750/trace.h index c45e35846c..0a812381ef 100644 --- a/bsp/efm32/EFM32GG_DK3750/trace.h +++ b/bsp/efm32/EFM32GG_DK3750/trace.h @@ -58,7 +58,7 @@ bool TRACE_ProfilerSetup(void); * for TRACE_ProfilerSetup. If TRACE_ProfilerEnable(false) has been run, * no example project will enable SWO trace. * @param[in] enable - * @note Add "em_msc.c" to build to use this function. + * @note Add "em_msc.c" to build to use this function. *****************************************************************************/ __STATIC_INLINE void TRACE_ProfilerEnable(bool enable) { @@ -69,7 +69,7 @@ __STATIC_INLINE void TRACE_ProfilerEnable(bool enable) data = *userpage; if(enable) { - if(data == 0xFFFFFFFF) + if(data == 0xFFFFFFFF) { return; } diff --git a/bsp/efm32/EFM32_Gxxx_DK/dvk.c b/bsp/efm32/EFM32_Gxxx_DK/dvk.c index 38569358e5..b1489c6c79 100644 --- a/bsp/efm32/EFM32_Gxxx_DK/dvk.c +++ b/bsp/efm32/EFM32_Gxxx_DK/dvk.c @@ -52,7 +52,7 @@ bool DVK_init(void) #endif #ifdef DVK_SPI_CONTROL ret = DVK_SPI_init(); -#endif +#endif if ( ret == false ) { /* Board is configured in wrong mode, please restart KIT! */ diff --git a/bsp/efm32/EFM32_Gxxx_DK/dvk_bcregisters.h b/bsp/efm32/EFM32_Gxxx_DK/dvk_bcregisters.h index 813d22e545..70b427d7ff 100644 --- a/bsp/efm32/EFM32_Gxxx_DK/dvk_bcregisters.h +++ b/bsp/efm32/EFM32_Gxxx_DK/dvk_bcregisters.h @@ -73,7 +73,7 @@ #define BC_HW_VERSION ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x14)) /**< HW version */ #define BC_FW_BUILDNO ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x15)) /**< FW build number */ #define BC_FW_VERSION ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x16)) /**< FW version */ -#define BC_SCRATCH_COMMON ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x17)) /**< Scratch common */ +#define BC_SCRATCH_COMMON ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x17)) /**< Scratch common */ #define BC_SCRATCH_EFM0 ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x18)) /**< Scratch EFM0 */ #define BC_SCRATCH_EFM1 ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x19)) /**< Scratch EFM1 */ #define BC_SCRATCH_EFM2 ((volatile uint16_t *)(BC_REGISTER_BASE + sizeof(uint16_t) * 0x1A)) /**< Scratch EFM2 */ diff --git a/bsp/efm32/EFM32_Gxxx_DK/dvk_boardcontrol.c b/bsp/efm32/EFM32_Gxxx_DK/dvk_boardcontrol.c index 72855106fc..a309df8204 100644 --- a/bsp/efm32/EFM32_Gxxx_DK/dvk_boardcontrol.c +++ b/bsp/efm32/EFM32_Gxxx_DK/dvk_boardcontrol.c @@ -155,7 +155,7 @@ uint16_t DVK_getPushButtons(void) /* Check state */ aemState = DVK_readRegister(BC_AEMSTATE); /* Read pushbutton status */ - if ( aemState == BC_AEMSTATE_EFM ) + if ( aemState == BC_AEMSTATE_EFM ) { pb = (~(DVK_readRegister(BC_PUSHBUTTON))) & 0x000f; } @@ -174,7 +174,7 @@ uint16_t DVK_getJoystick(void) /* Check state */ aemState = DVK_readRegister(BC_AEMSTATE); /* Read pushbutton status */ - if ( aemState == BC_AEMSTATE_EFM ) + if ( aemState == BC_AEMSTATE_EFM ) { joyStick = (~(DVK_readRegister(BC_JOYSTICK))) & 0x001f; } diff --git a/bsp/efm32/EFM32_Gxxx_DK/dvk_ebi.c b/bsp/efm32/EFM32_Gxxx_DK/dvk_ebi.c index 02f6c0b303..0fed351767 100644 --- a/bsp/efm32/EFM32_Gxxx_DK/dvk_ebi.c +++ b/bsp/efm32/EFM32_Gxxx_DK/dvk_ebi.c @@ -163,7 +163,7 @@ bool DVK_EBI_init(void) * be configured for EBI access */ ebiMagic = DVK_EBI_readRegister(BC_MAGIC); while ((ebiMagic != BC_MAGIC_VALUE) && retry) - { + { DVK_EBI_disable(); /* Enable SPI interface */ DVK_SPI_init(); @@ -172,13 +172,13 @@ bool DVK_EBI_init(void) DVK_SPI_writeRegister(BC_CFG, BC_CFG_EBI); /* Disable SPI */ DVK_SPI_disable(); - + /* Now setup EBI again */ DVK_EBI_configure(); /* Wait until ready */ ebiMagic = DVK_EBI_readRegister(BC_MAGIC); if (ebiMagic == BC_MAGIC_VALUE) break; - + retry--; } if ( ! retry ) return false; diff --git a/bsp/efm32/EFM32_Gxxx_DK/dvk_spi.c b/bsp/efm32/EFM32_Gxxx_DK/dvk_spi.c index 358b62bc9a..d4c536e21b 100644 --- a/bsp/efm32/EFM32_Gxxx_DK/dvk_spi.c +++ b/bsp/efm32/EFM32_Gxxx_DK/dvk_spi.c @@ -106,7 +106,7 @@ static void spiInit(void) /* Configure SPI bus connect pins, DOUT set to 0, disable EBI */ GPIO_PinModeSet(PORT_SPIBUS_CONNECT, PIN_SPIBUS_CONNECT, gpioModePushPull, 0); GPIO_PinModeSet(PORT_EBIBUS_CONNECT, PIN_EBIBUS_CONNECT, gpioModePushPull, 1); - + /* Configure SPI pins */ GPIO_PinModeSet(PORT_SPI_TX, PIN_SPI_TX, gpioModePushPull, 0); GPIO_PinModeSet(PORT_SPI_RX, PIN_SPI_RX, gpioModePushPull, 0); @@ -164,11 +164,11 @@ static uint16_t spiAccess(uint8_t spiaddr, uint8_t rw, uint16_t spidata) /* Just ignore data read back */ USART_Rx(USART_USED); - /* SPI data LSB */ + /* SPI data LSB */ USART_Tx(USART_USED, spidata & 0xFF); tmp = (uint16_t)USART_Rx(USART_USED); - /* SPI data MSB */ + /* SPI data MSB */ USART_Tx(USART_USED, spidata >> 8); tmp |= (uint16_t)USART_Rx(USART_USED) << 8; @@ -213,7 +213,7 @@ bool DVK_SPI_init(void) if(spiMagic != BC_MAGIC_VALUE) { return false; - } + } else { return true; diff --git a/bsp/efm32/EFM32_Gxxx_DK/trace.c b/bsp/efm32/EFM32_Gxxx_DK/trace.c index 0ef4438a29..ef1617cc1f 100644 --- a/bsp/efm32/EFM32_Gxxx_DK/trace.c +++ b/bsp/efm32/EFM32_Gxxx_DK/trace.c @@ -89,7 +89,7 @@ void TRACE_SWOSetup(void) /**************************************************************************//** * @brief Profiler configuration * @return true if energyAware Profiler/SWO is enabled, false if not - * @note If first word of the user page is zero, this will not + * @note If first word of the user page is zero, this will not * enable SWO profiler output, see trace.h *****************************************************************************/ bool TRACE_ProfilerSetup(void) @@ -105,7 +105,7 @@ bool TRACE_ProfilerSetup(void) { TRACE_SWOSetup(); return true; - } + } } /** @} (end group BSP) */ diff --git a/bsp/efm32/EFM32_Gxxx_DK/trace.h b/bsp/efm32/EFM32_Gxxx_DK/trace.h index 311e7ed357..1abb391a6c 100644 --- a/bsp/efm32/EFM32_Gxxx_DK/trace.h +++ b/bsp/efm32/EFM32_Gxxx_DK/trace.h @@ -58,7 +58,7 @@ bool TRACE_ProfilerSetup(void); * in TRACE_ProfilerSetup. If TRACE_ProfilerEnable(false) has been run, * no example project will enable SWO trace. * @param[in] enable - * @note Add "em_msc.c" to build to use this function. + * @note Add "em_msc.c" to build to use this function. *****************************************************************************/ __STATIC_INLINE void TRACE_ProfilerEnable(bool enable) { @@ -69,7 +69,7 @@ __STATIC_INLINE void TRACE_ProfilerEnable(bool enable) data = *userpage; if(enable) { - if(data == 0xFFFFFFFF) + if(data == 0xFFFFFFFF) { return; } @@ -81,7 +81,7 @@ __STATIC_INLINE void TRACE_ProfilerEnable(bool enable) return; } } - + /* Initialize MSC */ MSC_Init(); diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ARM/arm_cortexM0x_math.uvopt b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ARM/arm_cortexM0x_math.uvopt deleted file mode 100644 index 5514cddd39..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ARM/arm_cortexM0x_math.uvopt +++ /dev/null @@ -1,4197 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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- - arm_fir_init_q31.c - 1 - ..\FilteringFunctions\arm_fir_init_q31.c - - - arm_fir_interpolate_f32.c - 1 - ..\FilteringFunctions\arm_fir_interpolate_f32.c - - - arm_fir_interpolate_init_f32.c - 1 - ..\FilteringFunctions\arm_fir_interpolate_init_f32.c - - - arm_fir_interpolate_init_q15.c - 1 - ..\FilteringFunctions\arm_fir_interpolate_init_q15.c - - - arm_fir_interpolate_init_q31.c - 1 - ..\FilteringFunctions\arm_fir_interpolate_init_q31.c - - - arm_fir_interpolate_q15.c - 1 - ..\FilteringFunctions\arm_fir_interpolate_q15.c - - - arm_fir_interpolate_q31.c - 1 - ..\FilteringFunctions\arm_fir_interpolate_q31.c - - - arm_fir_lattice_f32.c - 1 - ..\FilteringFunctions\arm_fir_lattice_f32.c - - - arm_fir_lattice_init_f32.c - 1 - ..\FilteringFunctions\arm_fir_lattice_init_f32.c - - - arm_fir_lattice_init_q15.c - 1 - ..\FilteringFunctions\arm_fir_lattice_init_q15.c - - - arm_fir_lattice_init_q31.c - 1 - ..\FilteringFunctions\arm_fir_lattice_init_q31.c - - - arm_fir_lattice_q15.c - 1 - ..\FilteringFunctions\arm_fir_lattice_q15.c - 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1 - ..\FilteringFunctions\arm_iir_lattice_init_f32.c - - - arm_iir_lattice_init_q15.c - 1 - ..\FilteringFunctions\arm_iir_lattice_init_q15.c - - - arm_iir_lattice_init_q31.c - 1 - ..\FilteringFunctions\arm_iir_lattice_init_q31.c - - - arm_iir_lattice_q15.c - 1 - ..\FilteringFunctions\arm_iir_lattice_q15.c - - - arm_iir_lattice_q31.c - 1 - ..\FilteringFunctions\arm_iir_lattice_q31.c - - - arm_lms_f32.c - 1 - ..\FilteringFunctions\arm_lms_f32.c - - - arm_lms_init_f32.c - 1 - ..\FilteringFunctions\arm_lms_init_f32.c - - - arm_lms_init_q15.c - 1 - ..\FilteringFunctions\arm_lms_init_q15.c - - - arm_lms_init_q31.c - 1 - ..\FilteringFunctions\arm_lms_init_q31.c - - - arm_lms_norm_f32.c - 1 - ..\FilteringFunctions\arm_lms_norm_f32.c - - - arm_lms_norm_init_f32.c - 1 - ..\FilteringFunctions\arm_lms_norm_init_f32.c - - - arm_lms_norm_init_q15.c - 1 - ..\FilteringFunctions\arm_lms_norm_init_q15.c - - - arm_lms_norm_init_q31.c - 1 - ..\FilteringFunctions\arm_lms_norm_init_q31.c - - - arm_lms_norm_q15.c - 1 - ..\FilteringFunctions\arm_lms_norm_q15.c - - - arm_lms_norm_q31.c - 1 - ..\FilteringFunctions\arm_lms_norm_q31.c - - - arm_lms_q15.c - 1 - ..\FilteringFunctions\arm_lms_q15.c - - - arm_lms_q31.c - 1 - ..\FilteringFunctions\arm_lms_q31.c - - - - - MatrixFunctions - - - arm_mat_add_f32.c - 1 - ..\MatrixFunctions\arm_mat_add_f32.c - - - arm_mat_add_q15.c - 1 - ..\MatrixFunctions\arm_mat_add_q15.c - - - arm_mat_add_q31.c - 1 - ..\MatrixFunctions\arm_mat_add_q31.c - - - arm_mat_init_f32.c - 1 - ..\MatrixFunctions\arm_mat_init_f32.c - - - arm_mat_init_q15.c - 1 - ..\MatrixFunctions\arm_mat_init_q15.c - - - arm_mat_init_q31.c - 1 - ..\MatrixFunctions\arm_mat_init_q31.c - - - arm_mat_inverse_f32.c - 1 - ..\MatrixFunctions\arm_mat_inverse_f32.c - - - arm_mat_mult_f32.c - 1 - ..\MatrixFunctions\arm_mat_mult_f32.c - - - arm_mat_mult_fast_q15.c - 1 - ..\MatrixFunctions\arm_mat_mult_fast_q15.c - - - arm_mat_mult_fast_q31.c - 1 - ..\MatrixFunctions\arm_mat_mult_fast_q31.c - - - arm_mat_mult_q15.c - 1 - ..\MatrixFunctions\arm_mat_mult_q15.c - - - arm_mat_mult_q31.c - 1 - ..\MatrixFunctions\arm_mat_mult_q31.c - - - arm_mat_scale_f32.c - 1 - ..\MatrixFunctions\arm_mat_scale_f32.c - - - arm_mat_scale_q15.c - 1 - ..\MatrixFunctions\arm_mat_scale_q15.c - - - arm_mat_scale_q31.c - 1 - ..\MatrixFunctions\arm_mat_scale_q31.c - - - arm_mat_sub_f32.c - 1 - ..\MatrixFunctions\arm_mat_sub_f32.c - - - arm_mat_sub_q15.c - 1 - ..\MatrixFunctions\arm_mat_sub_q15.c - - - arm_mat_sub_q31.c - 1 - ..\MatrixFunctions\arm_mat_sub_q31.c - - - arm_mat_trans_f32.c - 1 - ..\MatrixFunctions\arm_mat_trans_f32.c - - - arm_mat_trans_q15.c - 1 - ..\MatrixFunctions\arm_mat_trans_q15.c - - - arm_mat_trans_q31.c - 1 - ..\MatrixFunctions\arm_mat_trans_q31.c - - - - - TransformFunctions - - - arm_bitreversal.c - 1 - ..\TransformFunctions\arm_bitreversal.c - - - arm_cfft_radix2_f32.c - 1 - ..\TransformFunctions\arm_cfft_radix2_f32.c - - - arm_cfft_radix2_init_f32.c - 1 - ..\TransformFunctions\arm_cfft_radix2_init_f32.c - - - arm_cfft_radix2_init_q15.c - 1 - ..\TransformFunctions\arm_cfft_radix2_init_q15.c - - - arm_cfft_radix2_init_q31.c - 1 - ..\TransformFunctions\arm_cfft_radix2_init_q31.c - - - arm_cfft_radix2_q15.c - 1 - ..\TransformFunctions\arm_cfft_radix2_q15.c - - - arm_cfft_radix2_q31.c - 1 - ..\TransformFunctions\arm_cfft_radix2_q31.c - - - arm_cfft_radix4_f32.c - 1 - ..\TransformFunctions\arm_cfft_radix4_f32.c - - - arm_cfft_radix4_init_f32.c - 1 - ..\TransformFunctions\arm_cfft_radix4_init_f32.c - - - arm_cfft_radix4_init_q15.c - 1 - ..\TransformFunctions\arm_cfft_radix4_init_q15.c - - - arm_cfft_radix4_init_q31.c - 1 - ..\TransformFunctions\arm_cfft_radix4_init_q31.c - - - arm_cfft_radix4_q15.c - 1 - ..\TransformFunctions\arm_cfft_radix4_q15.c - - - arm_cfft_radix4_q31.c - 1 - ..\TransformFunctions\arm_cfft_radix4_q31.c - - - arm_dct4_f32.c - 1 - ..\TransformFunctions\arm_dct4_f32.c - - - arm_dct4_init_f32.c - 1 - ..\TransformFunctions\arm_dct4_init_f32.c - - - arm_dct4_init_q15.c - 1 - ..\TransformFunctions\arm_dct4_init_q15.c - - - arm_dct4_init_q31.c - 1 - ..\TransformFunctions\arm_dct4_init_q31.c - - - arm_dct4_q15.c - 1 - ..\TransformFunctions\arm_dct4_q15.c - - - arm_dct4_q31.c - 1 - ..\TransformFunctions\arm_dct4_q31.c - - - arm_rfft_f32.c - 1 - ..\TransformFunctions\arm_rfft_f32.c - - - arm_rfft_init_f32.c - 1 - ..\TransformFunctions\arm_rfft_init_f32.c - - - arm_rfft_init_q15.c - 1 - ..\TransformFunctions\arm_rfft_init_q15.c - - - arm_rfft_init_q31.c - 1 - ..\TransformFunctions\arm_rfft_init_q31.c - - - arm_rfft_q15.c - 1 - ..\TransformFunctions\arm_rfft_q15.c - - - arm_rfft_q31.c - 1 - ..\TransformFunctions\arm_rfft_q31.c - - - - - ControllerFunctions - - - arm_pid_init_f32.c - 1 - ..\ControllerFunctions\arm_pid_init_f32.c - - - arm_pid_init_q15.c - 1 - ..\ControllerFunctions\arm_pid_init_q15.c - - - arm_pid_init_q31.c - 1 - ..\ControllerFunctions\arm_pid_init_q31.c - - - arm_pid_reset_f32.c - 1 - ..\ControllerFunctions\arm_pid_reset_f32.c - - - arm_pid_reset_q15.c - 1 - ..\ControllerFunctions\arm_pid_reset_q15.c - - - arm_pid_reset_q31.c - 1 - ..\ControllerFunctions\arm_pid_reset_q31.c - - - arm_sin_cos_f32.c - 1 - ..\ControllerFunctions\arm_sin_cos_f32.c - - - arm_sin_cos_q31.c - 1 - ..\ControllerFunctions\arm_sin_cos_q31.c - - - - - StatisticsFunctions - - - arm_max_f32.c - 1 - ..\StatisticsFunctions\arm_max_f32.c - - - arm_max_q7.c - 1 - ..\StatisticsFunctions\arm_max_q7.c - - - arm_max_q15.c - 1 - ..\StatisticsFunctions\arm_max_q15.c - - - arm_max_q31.c - 1 - ..\StatisticsFunctions\arm_max_q31.c - - - arm_mean_f32.c - 1 - ..\StatisticsFunctions\arm_mean_f32.c - - - arm_mean_q7.c - 1 - ..\StatisticsFunctions\arm_mean_q7.c - - - arm_mean_q15.c - 1 - ..\StatisticsFunctions\arm_mean_q15.c - - - arm_mean_q31.c - 1 - ..\StatisticsFunctions\arm_mean_q31.c - - - arm_min_f32.c - 1 - ..\StatisticsFunctions\arm_min_f32.c - - - arm_min_q7.c - 1 - ..\StatisticsFunctions\arm_min_q7.c - - - arm_min_q15.c - 1 - ..\StatisticsFunctions\arm_min_q15.c - - - arm_min_q31.c - 1 - ..\StatisticsFunctions\arm_min_q31.c - - - arm_power_f32.c - 1 - ..\StatisticsFunctions\arm_power_f32.c - - - arm_power_q7.c - 1 - ..\StatisticsFunctions\arm_power_q7.c - - - arm_power_q15.c - 1 - ..\StatisticsFunctions\arm_power_q15.c - - - arm_power_q31.c - 1 - ..\StatisticsFunctions\arm_power_q31.c - - - arm_rms_f32.c - 1 - ..\StatisticsFunctions\arm_rms_f32.c - - - arm_rms_q15.c - 1 - ..\StatisticsFunctions\arm_rms_q15.c - - - arm_rms_q31.c - 1 - ..\StatisticsFunctions\arm_rms_q31.c - - - arm_std_f32.c - 1 - ..\StatisticsFunctions\arm_std_f32.c - - - arm_std_q15.c - 1 - ..\StatisticsFunctions\arm_std_q15.c - - - arm_std_q31.c - 1 - ..\StatisticsFunctions\arm_std_q31.c - - - arm_var_f32.c - 1 - ..\StatisticsFunctions\arm_var_f32.c - - - arm_var_q15.c - 1 - ..\StatisticsFunctions\arm_var_q15.c - - - arm_var_q31.c - 1 - ..\StatisticsFunctions\arm_var_q31.c - - - - - SupportFunctions - - - arm_copy_f32.c - 1 - ..\SupportFunctions\arm_copy_f32.c - - - arm_copy_q7.c - 1 - ..\SupportFunctions\arm_copy_q7.c - - - arm_copy_q15.c - 1 - ..\SupportFunctions\arm_copy_q15.c - - - arm_copy_q31.c - 1 - ..\SupportFunctions\arm_copy_q31.c - - - arm_fill_f32.c - 1 - ..\SupportFunctions\arm_fill_f32.c - - - arm_fill_q7.c - 1 - ..\SupportFunctions\arm_fill_q7.c - - - arm_fill_q15.c - 1 - ..\SupportFunctions\arm_fill_q15.c - - - arm_fill_q31.c - 1 - ..\SupportFunctions\arm_fill_q31.c - - - arm_float_to_q7.c - 1 - ..\SupportFunctions\arm_float_to_q7.c - - - arm_float_to_q15.c - 1 - ..\SupportFunctions\arm_float_to_q15.c - - - arm_float_to_q31.c - 1 - ..\SupportFunctions\arm_float_to_q31.c - - - arm_q7_to_float.c - 1 - ..\SupportFunctions\arm_q7_to_float.c - - - arm_q7_to_q15.c - 1 - ..\SupportFunctions\arm_q7_to_q15.c - - - arm_q7_to_q31.c - 1 - ..\SupportFunctions\arm_q7_to_q31.c - - - arm_q15_to_float.c - 1 - ..\SupportFunctions\arm_q15_to_float.c - - - arm_q15_to_q7.c - 1 - ..\SupportFunctions\arm_q15_to_q7.c - - - arm_q15_to_q31.c - 1 - ..\SupportFunctions\arm_q15_to_q31.c - - - arm_q31_to_float.c - 1 - ..\SupportFunctions\arm_q31_to_float.c - - - arm_q31_to_q7.c - 1 - ..\SupportFunctions\arm_q31_to_q7.c - - - arm_q31_to_q15.c - 1 - ..\SupportFunctions\arm_q31_to_q15.c - - - - - CommonTables - - - arm_common_tables.c - 1 - ..\CommonTables\arm_common_tables.c - - - - - - - - diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ARM/arm_cortexMx_math_Build.bat b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ARM/arm_cortexMx_math_Build.bat deleted file mode 100644 index 69cf1aa0e8..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ARM/arm_cortexMx_math_Build.bat +++ /dev/null @@ -1,29 +0,0 @@ - -SET TMP=C:\Temp -SET TEMP=C:\Temp - -SET UVEXE=C:\Keil\UV4\UV4.EXE - -@echo Building DSP Library for Cortex-M0 Little Endian -%UVEXE% -rb arm_cortexM0x_math.uvproj -t"DSP_Lib CM0 LE" -o"DSP_Lib CM0 LE.txt" -j0 - -@echo Building DSP Library for Cortex-M0 Big Endian -%UVEXE% -rb arm_cortexM0x_math.uvproj -t"DSP_Lib CM0 BE" -o"DSP_Lib CM0 BE.txt" -j0 - -@echo Building DSP Library for Cortex-M3 Little Endian -%UVEXE% -rb arm_cortexM3x_math.uvproj -t"DSP_Lib CM3 LE" -o"DSP_Lib CM3 LE.txt" -j0 - -@echo Building DSP Library for Cortex-M3 Big Endian -%UVEXE% -rb arm_cortexM3x_math.uvproj -t"DSP_Lib CM3 BE" -o"DSP_Lib CM3 BE.txt" -j0 - -@echo Building DSP Library for Cortex-M4 Little Endian -%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 LE" -o"DSP_Lib CM4 LE.txt" -j0 - -@echo Building DSP Library for Cortex-M4 Big Endian -%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 BE" -o"DSP_Lib CM4 BE.txt" -j0 - -@echo Building DSP Library for Cortex-M4 with FPU Little Endian -%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 LE FPU" -o"DSP_Lib CM4 LE FPU.txt" -j0 - -@echo Building DSP Library for Cortex-M4 with FPU Big Endian -%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 BE FPU" -o"DSP_Lib CM4 BE FPU.txt" -j0 \ No newline at end of file diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_f32.c deleted file mode 100644 index 3c9d360c66..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_f32.c +++ /dev/null @@ -1,159 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_abs_f32.c -* -* Description: Vector absolute value. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* ---------------------------------------------------------------------------- */ - -#include "arm_math.h" -#include - -/** - * @ingroup groupMath - */ - -/** - * @defgroup BasicAbs Vector Absolute Value - * - * Computes the absolute value of a vector on an element-by-element basis. - * - * 
        
- *     pDst[n] = abs(pSrcA[n]),   0 <= n < blockSize.        
- *
- * - * The operation can be done in-place by setting the input and output pointers to the same buffer. - * There are separate functions for floating-point, Q7, Q15, and Q31 data types. - */ - -/** - * @addtogroup BasicAbs - * @{ - */ - -/** - * @brief Floating-point vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - -void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0 - - /* Run the below code for Cortex-M4 and Cortex-M3 */ - float32_t in1, in2, in3, in4; /* temporary variables */ - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = |A| */ - /* Calculate absolute and then store the results in the destination buffer. */ - /* read sample from source */ - in1 = *pSrc; - in2 = *(pSrc + 1); - in3 = *(pSrc + 2); - - /* find absolute value */ - in1 = fabsf(in1); - - /* read sample from source */ - in4 = *(pSrc + 3); - - /* find absolute value */ - in2 = fabsf(in2); - - /* read sample from source */ - *pDst = in1; - - /* find absolute value */ - in3 = fabsf(in3); - - /* find absolute value */ - in4 = fabsf(in4); - - /* store result to destination */ - *(pDst + 1) = in2; - - /* store result to destination */ - *(pDst + 2) = in3; - - /* store result to destination */ - *(pDst + 3) = in4; - - - /* Update source pointer to process next sampels */ - pSrc += 4u; - - /* Update destination pointer to process next sampels */ - pDst += 4u; - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0 */ - - while(blkCnt > 0u) - { - /* C = |A| */ - /* Calculate absolute and then store the results in the destination buffer. */ - *pDst++ = fabsf(*pSrc++); - - /* Decrement the loop counter */ - blkCnt--; - } -} - -/** - * @} end of BasicAbs group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q15.c deleted file mode 100644 index 6b6fdf4ef4..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q15.c +++ /dev/null @@ -1,173 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_abs_q15.c -* -* Description: Q15 vector absolute value. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup BasicAbs - * @{ - */ - -/** - * @brief Q15 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF. - */ - -void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0 - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - - q15_t in1; /* Input value1 */ - q15_t in2; /* Input value2 */ - - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = |A| */ - /* Read two inputs */ - in1 = *pSrc++; - in2 = *pSrc++; - - - /* Store the Absolute result in the destination buffer by packing the two values, in a single cycle */ - -#ifndef ARM_MATH_BIG_ENDIAN - - *__SIMD32(pDst)++ = - __PKHBT(((in1 > 0) ? in1 : __QSUB16(0, in1)), - ((in2 > 0) ? in2 : __QSUB16(0, in2)), 16); - -#else - - - *__SIMD32(pDst)++ = - __PKHBT(((in2 > 0) ? in2 : __QSUB16(0, in2)), - ((in1 > 0) ? in1 : __QSUB16(0, in1)), 16); - -#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ - - in1 = *pSrc++; - in2 = *pSrc++; - - -#ifndef ARM_MATH_BIG_ENDIAN - - *__SIMD32(pDst)++ = - __PKHBT(((in1 > 0) ? in1 : __QSUB16(0, in1)), - ((in2 > 0) ? in2 : __QSUB16(0, in2)), 16); - -#else - - - *__SIMD32(pDst)++ = - __PKHBT(((in2 > 0) ? in2 : __QSUB16(0, in2)), - ((in1 > 0) ? in1 : __QSUB16(0, in1)), 16); - -#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = |A| */ - /* Read the input */ - in1 = *pSrc++; - - /* Calculate absolute value of input and then store the result in the destination buffer. */ - *pDst++ = (in1 > 0) ? in1 : __QSUB16(0, in1); - - /* Decrement the loop counter */ - blkCnt--; - } - -#else - - /* Run the below code for Cortex-M0 */ - - q15_t in; /* Temporary input variable */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = |A| */ - /* Read the input */ - in = *pSrc++; - - /* Calculate absolute value of input and then store the result in the destination buffer. */ - *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in); - - /* Decrement the loop counter */ - blkCnt--; - } - -#endif /* #ifndef ARM_MATH_CM0 */ - -} - -/** - * @} end of BasicAbs group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q31.c deleted file mode 100644 index 5c3d56f749..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q31.c +++ /dev/null @@ -1,125 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_abs_q31.c -* -* Description: Q31 vector absolute value. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup BasicAbs - * @{ - */ - - -/** - * @brief Q31 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF. - */ - -void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - q31_t in; /* Input value */ - -#ifndef ARM_MATH_CM0 - - /* Run the below code for Cortex-M4 and Cortex-M3 */ - q31_t in1, in2, in3, in4; - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = |A| */ - /* Calculate absolute of input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */ - in1 = *pSrc++; - in2 = *pSrc++; - in3 = *pSrc++; - in4 = *pSrc++; - - *pDst++ = (in1 > 0) ? in1 : __QSUB(0, in1); - *pDst++ = (in2 > 0) ? in2 : __QSUB(0, in2); - *pDst++ = (in3 > 0) ? in3 : __QSUB(0, in3); - *pDst++ = (in4 > 0) ? in4 : __QSUB(0, in4); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0 */ - - while(blkCnt > 0u) - { - /* C = |A| */ - /* Calculate absolute value of the input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */ - in = *pSrc++; - *pDst++ = (in > 0) ? in : ((in == 0x80000000) ? 0x7fffffff : -in); - - /* Decrement the loop counter */ - blkCnt--; - } - -} - -/** - * @} end of BasicAbs group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q7.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q7.c deleted file mode 100644 index 0ae0a2f5b3..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q7.c +++ /dev/null @@ -1,152 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_abs_q7.c -* -* Description: Q7 vector absolute value. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup BasicAbs - * @{ - */ - -/** - * @brief Q7 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - * - * \par Conditions for optimum performance - * Input and output buffers should be aligned by 32-bit - * - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F. - */ - -void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - q7_t in; /* Input value1 */ - -#ifndef ARM_MATH_CM0 - - /* Run the below code for Cortex-M4 and Cortex-M3 */ - q31_t in1, in2, in3, in4; /* temporary input variables */ - q31_t out1, out2, out3, out4; /* temporary output variables */ - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = |A| */ - /* Read inputs */ - in1 = (q31_t) * pSrc; - in2 = (q31_t) * (pSrc + 1); - in3 = (q31_t) * (pSrc + 2); - - /* find absolute value */ - out1 = (in1 > 0) ? in1 : __QSUB8(0, in1); - - /* read input */ - in4 = (q31_t) * (pSrc + 3); - - /* find absolute value */ - out2 = (in2 > 0) ? in2 : __QSUB8(0, in2); - - /* store result to destination */ - *pDst = (q7_t) out1; - - /* find absolute value */ - out3 = (in3 > 0) ? in3 : __QSUB8(0, in3); - - /* find absolute value */ - out4 = (in4 > 0) ? in4 : __QSUB8(0, in4); - - /* store result to destination */ - *(pDst + 1) = (q7_t) out2; - - /* store result to destination */ - *(pDst + 2) = (q7_t) out3; - - /* store result to destination */ - *(pDst + 3) = (q7_t) out4; - - /* update pointers to process next samples */ - pSrc += 4u; - pDst += 4u; - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; -#else - - /* Run the below code for Cortex-M0 */ - blkCnt = blockSize; - -#endif // #define ARM_MATH_CM0 - - while(blkCnt > 0u) - { - /* C = |A| */ - /* Read the input */ - in = *pSrc++; - - /* Store the Absolute result in the destination buffer */ - *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? 0x7f : -in); - - /* Decrement the loop counter */ - blkCnt--; - } -} - -/** - * @} end of BasicAbs group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_f32.c deleted file mode 100644 index 29425373f2..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_f32.c +++ /dev/null @@ -1,145 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_add_f32.c -* -* Description: Floating-point vector addition. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* ---------------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @defgroup BasicAdd Vector Addition - * - * Element-by-element addition of two vectors. - * - * 
        
- *     pDst[n] = pSrcA[n] + pSrcB[n],   0 <= n < blockSize.        
- *
- * - * There are separate functions for floating-point, Q7, Q15, and Q31 data types. - */ - -/** - * @addtogroup BasicAdd - * @{ - */ - -/** - * @brief Floating-point vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - -void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0 - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - float32_t inA1, inA2, inA3, inA4; /* temporary input variabels */ - float32_t inB1, inB2, inB3, inB4; /* temporary input variables */ - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A + B */ - /* Add and then store the results in the destination buffer. */ - - /* read four inputs from sourceA and four inputs from sourceB */ - inA1 = *pSrcA; - inB1 = *pSrcB; - inA2 = *(pSrcA + 1); - inB2 = *(pSrcB + 1); - inA3 = *(pSrcA + 2); - inB3 = *(pSrcB + 2); - inA4 = *(pSrcA + 3); - inB4 = *(pSrcB + 3); - - /* C = A + B */ - /* add and store result to destination */ - *pDst = inA1 + inB1; - *(pDst + 1) = inA2 + inB2; - *(pDst + 2) = inA3 + inB3; - *(pDst + 3) = inA4 + inB4; - - /* update pointers to process next samples */ - pSrcA += 4u; - pSrcB += 4u; - pDst += 4u; - - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0 */ - - while(blkCnt > 0u) - { - /* C = A + B */ - /* Add and then store the results in the destination buffer. */ - *pDst++ = (*pSrcA++) + (*pSrcB++); - - /* Decrement the loop counter */ - blkCnt--; - } -} - -/** - * @} end of BasicAdd group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q15.c deleted file mode 100644 index 6de4a03368..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q15.c +++ /dev/null @@ -1,135 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_add_q15.c -* -* Description: Q15 vector addition -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup BasicAdd - * @{ - */ - -/** - * @brief Q15 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. - */ - -void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0 - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q31_t inA1, inA2, inB1, inB2; - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A + B */ - /* Add and then store the results in the destination buffer. */ - inA1 = *__SIMD32(pSrcA)++; - inA2 = *__SIMD32(pSrcA)++; - inB1 = *__SIMD32(pSrcB)++; - inB2 = *__SIMD32(pSrcB)++; - - *__SIMD32(pDst)++ = __QADD16(inA1, inB1); - *__SIMD32(pDst)++ = __QADD16(inA2, inB2); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A + B */ - /* Add and then store the results in the destination buffer. */ - *pDst++ = (q15_t) __QADD16(*pSrcA++, *pSrcB++); - - /* Decrement the loop counter */ - blkCnt--; - } - -#else - - /* Run the below code for Cortex-M0 */ - - - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A + B */ - /* Add and then store the results in the destination buffer. */ - *pDst++ = (q15_t) __SSAT(((q31_t) * pSrcA++ + *pSrcB++), 16); - - /* Decrement the loop counter */ - blkCnt--; - } - -#endif /* #ifndef ARM_MATH_CM0 */ - - -} - -/** - * @} end of BasicAdd group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q31.c deleted file mode 100644 index 576efe6c74..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q31.c +++ /dev/null @@ -1,143 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_add_q31.c -* -* Description: Q31 vector addition. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup BasicAdd - * @{ - */ - - -/** - * @brief Q31 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated. - */ - -void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0 - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q31_t inA1, inA2, inA3, inA4; - q31_t inB1, inB2, inB3, inB4; - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A + B */ - /* Add and then store the results in the destination buffer. */ - inA1 = *pSrcA++; - inA2 = *pSrcA++; - inB1 = *pSrcB++; - inB2 = *pSrcB++; - - inA3 = *pSrcA++; - inA4 = *pSrcA++; - inB3 = *pSrcB++; - inB4 = *pSrcB++; - - *pDst++ = __QADD(inA1, inB1); - *pDst++ = __QADD(inA2, inB2); - *pDst++ = __QADD(inA3, inB3); - *pDst++ = __QADD(inA4, inB4); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A + B */ - /* Add and then store the results in the destination buffer. */ - *pDst++ = __QADD(*pSrcA++, *pSrcB++); - - /* Decrement the loop counter */ - blkCnt--; - } - -#else - - /* Run the below code for Cortex-M0 */ - - - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A + B */ - /* Add and then store the results in the destination buffer. */ - *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrcA++ + *pSrcB++); - - /* Decrement the loop counter */ - blkCnt--; - } - -#endif /* #ifndef ARM_MATH_CM0 */ - -} - -/** - * @} end of BasicAdd group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q7.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q7.c deleted file mode 100644 index 6f75e1d42f..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q7.c +++ /dev/null @@ -1,129 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_add_q7.c -* -* Description: Q7 vector addition. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup BasicAdd - * @{ - */ - -/** - * @brief Q7 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. - */ - -void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0 - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A + B */ - /* Add and then store the results in the destination buffer. */ - *__SIMD32(pDst)++ = __QADD8(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A + B */ - /* Add and then store the results in the destination buffer. */ - *pDst++ = (q7_t) __SSAT(*pSrcA++ + *pSrcB++, 8); - - /* Decrement the loop counter */ - blkCnt--; - } - -#else - - /* Run the below code for Cortex-M0 */ - - - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A + B */ - /* Add and then store the results in the destination buffer. */ - *pDst++ = (q7_t) __SSAT((q15_t) * pSrcA++ + *pSrcB++, 8); - - /* Decrement the loop counter */ - blkCnt--; - } - -#endif /* #ifndef ARM_MATH_CM0 */ - - -} - -/** - * @} end of BasicAdd group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_f32.c deleted file mode 100644 index 933b001703..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_f32.c +++ /dev/null @@ -1,125 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_dot_prod_f32.c -* -* Description: Floating-point dot product. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* ---------------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @defgroup dot_prod Vector Dot Product - * - * Computes the dot product of two vectors. - * The vectors are multiplied element-by-element and then summed. - * There are separate functions for floating-point, Q7, Q15, and Q31 data types. - */ - -/** - * @addtogroup dot_prod - * @{ - */ - -/** - * @brief Dot product of floating-point vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - -void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result) -{ - float32_t sum = 0.0f; /* Temporary result storage */ - uint32_t blkCnt; /* loop counter */ - - -#ifndef ARM_MATH_CM0 - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ - /* Calculate dot product and then store the result in a temporary buffer */ - sum += (*pSrcA++) * (*pSrcB++); - sum += (*pSrcA++) * (*pSrcB++); - sum += (*pSrcA++) * (*pSrcB++); - sum += (*pSrcA++) * (*pSrcB++); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0 */ - - - while(blkCnt > 0u) - { - /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ - /* Calculate dot product and then store the result in a temporary buffer. */ - sum += (*pSrcA++) * (*pSrcB++); - - /* Decrement the loop counter */ - blkCnt--; - } - /* Store the result back in the destination buffer */ - *result = sum; -} - -/** - * @} end of dot_prod group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q15.c deleted file mode 100644 index 865e4c4331..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q15.c +++ /dev/null @@ -1,135 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_dot_prod_q15.c -* -* Description: Q15 dot product. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup dot_prod - * @{ - */ - -/** - * @brief Dot product of Q15 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The intermediate multiplications are in 1.15 x 1.15 = 2.30 format and these - * results are added to a 64-bit accumulator in 34.30 format. - * Nonsaturating additions are used and given that there are 33 guard bits in the accumulator - * there is no risk of overflow. - * The return result is in 34.30 format. - */ - -void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result) -{ - q63_t sum = 0; /* Temporary result storage */ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0 - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ - /* Calculate dot product and then store the result in a temporary buffer. */ - sum = __SMLALD(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++, sum); - sum = __SMLALD(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++, sum); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ - /* Calculate dot product and then store the results in a temporary buffer. */ - sum = __SMLALD(*pSrcA++, *pSrcB++, sum); - - /* Decrement the loop counter */ - blkCnt--; - } - - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ - /* Calculate dot product and then store the results in a temporary buffer. */ - sum += (q63_t) ((q31_t) * pSrcA++ * *pSrcB++); - - /* Decrement the loop counter */ - blkCnt--; - } - -#endif /* #ifndef ARM_MATH_CM0 */ - - /* Store the result in the destination buffer in 34.30 format */ - *result = sum; - -} - -/** - * @} end of dot_prod group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q31.c deleted file mode 100644 index 1f98e41d6c..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q31.c +++ /dev/null @@ -1,138 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_dot_prod_q31.c -* -* Description: Q31 dot product. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup dot_prod - * @{ - */ - -/** - * @brief Dot product of Q31 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The intermediate multiplications are in 1.31 x 1.31 = 2.62 format and these - * are truncated to 2.48 format by discarding the lower 14 bits. - * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format. - * There are 15 guard bits in the accumulator and there is no risk of overflow as long as - * the length of the vectors is less than 2^16 elements. - * The return result is in 16.48 format. - */ - -void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result) -{ - q63_t sum = 0; /* Temporary result storage */ - uint32_t blkCnt; /* loop counter */ - - -#ifndef ARM_MATH_CM0 - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q31_t inA1, inA2, inA3, inA4; - q31_t inB1, inB2, inB3, inB4; - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ - /* Calculate dot product and then store the result in a temporary buffer. */ - inA1 = *pSrcA++; - inA2 = *pSrcA++; - inA3 = *pSrcA++; - inA4 = *pSrcA++; - inB1 = *pSrcB++; - inB2 = *pSrcB++; - inB3 = *pSrcB++; - inB4 = *pSrcB++; - - sum += ((q63_t) inA1 * inB1) >> 14u; - sum += ((q63_t) inA2 * inB2) >> 14u; - sum += ((q63_t) inA3 * inB3) >> 14u; - sum += ((q63_t) inA4 * inB4) >> 14u; - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0 */ - - - while(blkCnt > 0u) - { - /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ - /* Calculate dot product and then store the result in a temporary buffer. */ - sum += ((q63_t) * pSrcA++ * *pSrcB++) >> 14u; - - /* Decrement the loop counter */ - blkCnt--; - } - - /* Store the result in the destination buffer in 16.48 format */ - *result = sum; -} - -/** - * @} end of dot_prod group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q7.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q7.c deleted file mode 100644 index 9cf0bf4034..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q7.c +++ /dev/null @@ -1,154 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_dot_prod_q7.c -* -* Description: Q7 dot product. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup dot_prod - * @{ - */ - -/** - * @brief Dot product of Q7 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The intermediate multiplications are in 1.7 x 1.7 = 2.14 format and these - * results are added to an accumulator in 18.14 format. - * Nonsaturating additions are used and there is no danger of wrap around as long as - * the vectors are less than 2^18 elements long. - * The return result is in 18.14 format. - */ - -void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result) -{ - uint32_t blkCnt; /* loop counter */ - - q31_t sum = 0; /* Temporary variables to store output */ - -#ifndef ARM_MATH_CM0 - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - - q31_t input1, input2; /* Temporary variables to store input */ - q31_t inA1, inA2, inB1, inB2; /* Temporary variables to store input */ - - - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* read 4 samples at a time from sourceA */ - input1 = *__SIMD32(pSrcA)++; - /* read 4 samples at a time from sourceB */ - input2 = *__SIMD32(pSrcB)++; - - /* extract two q7_t samples to q15_t samples */ - inA1 = __SXTB16(__ROR(input1, 8)); - /* extract reminaing two samples */ - inA2 = __SXTB16(input1); - /* extract two q7_t samples to q15_t samples */ - inB1 = __SXTB16(__ROR(input2, 8)); - /* extract reminaing two samples */ - inB2 = __SXTB16(input2); - - /* multiply and accumulate two samples at a time */ - sum = __SMLAD(inA1, inB1, sum); - sum = __SMLAD(inA2, inB2, sum); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ - /* Dot product and then store the results in a temporary buffer. */ - sum = __SMLAD(*pSrcA++, *pSrcB++, sum); - - /* Decrement the loop counter */ - blkCnt--; - } - -#else - - /* Run the below code for Cortex-M0 */ - - - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ - /* Dot product and then store the results in a temporary buffer. */ - sum += (q31_t) ((q15_t) * pSrcA++ * *pSrcB++); - - /* Decrement the loop counter */ - blkCnt--; - } - -#endif /* #ifndef ARM_MATH_CM0 */ - - - /* Store the result in the destination buffer in 18.14 format */ - *result = sum; -} - -/** - * @} end of dot_prod group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_f32.c deleted file mode 100644 index 682931eacd..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_f32.c +++ /dev/null @@ -1,172 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_mult_f32.c -* -* Description: Floating-point vector multiplication. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -* Version 0.0.5 2010/04/26 -* incorporated review comments and updated with latest CMSIS layer -* -* Version 0.0.3 2010/03/10 -* Initial version -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @defgroup BasicMult Vector Multiplication - * - * Element-by-element multiplication of two vectors. - * - * 
        
- *     pDst[n] = pSrcA[n] * pSrcB[n],   0 <= n < blockSize.        
- *
- * - * There are separate functions for floating-point, Q7, Q15, and Q31 data types. - */ - -/** - * @addtogroup BasicMult - * @{ - */ - -/** - * @brief Floating-point vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - -void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counters */ -#ifndef ARM_MATH_CM0 - - /* Run the below code for Cortex-M4 and Cortex-M3 */ - float32_t inA1, inA2, inA3, inA4; /* temporary input variables */ - float32_t inB1, inB2, inB3, inB4; /* temporary input variables */ - float32_t out1, out2, out3, out4; /* temporary output variables */ - - /* loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A * B */ - /* Multiply the inputs and store the results in output buffer */ - /* read sample from sourceA */ - inA1 = *pSrcA; - /* read sample from sourceB */ - inB1 = *pSrcB; - /* read sample from sourceA */ - inA2 = *(pSrcA + 1); - /* read sample from sourceB */ - inB2 = *(pSrcB + 1); - - /* out = sourceA * sourceB */ - out1 = inA1 * inB1; - - /* read sample from sourceA */ - inA3 = *(pSrcA + 2); - /* read sample from sourceB */ - inB3 = *(pSrcB + 2); - - /* out = sourceA * sourceB */ - out2 = inA2 * inB2; - - /* read sample from sourceA */ - inA4 = *(pSrcA + 3); - - /* store result to destination buffer */ - *pDst = out1; - - /* read sample from sourceB */ - inB4 = *(pSrcB + 3); - - /* out = sourceA * sourceB */ - out3 = inA3 * inB3; - - /* store result to destination buffer */ - *(pDst + 1) = out2; - - /* out = sourceA * sourceB */ - out4 = inA4 * inB4; - /* store result to destination buffer */ - *(pDst + 2) = out3; - /* store result to destination buffer */ - *(pDst + 3) = out4; - - - /* update pointers to process next samples */ - pSrcA += 4u; - pSrcB += 4u; - pDst += 4u; - - /* Decrement the blockSize loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0 */ - - while(blkCnt > 0u) - { - /* C = A * B */ - /* Multiply the inputs and store the results in output buffer */ - *pDst++ = (*pSrcA++) * (*pSrcB++); - - /* Decrement the blockSize loop counter */ - blkCnt--; - } -} - -/** - * @} end of BasicMult group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q15.c deleted file mode 100644 index 00a522d97a..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q15.c +++ /dev/null @@ -1,152 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_mult_q15.c -* -* Description: Q15 vector multiplication. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -* Version 0.0.5 2010/04/26 -* incorporated review comments and updated with latest CMSIS layer -* -* Version 0.0.3 2010/03/10 -* Initial version -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup BasicMult - * @{ - */ - - -/** - * @brief Q15 vector multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. - */ - -void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counters */ - -#ifndef ARM_MATH_CM0 - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q31_t inA1, inA2, inB1, inB2; /* temporary input variables */ - q15_t out1, out2, out3, out4; /* temporary output variables */ - q31_t mul1, mul2, mul3, mul4; /* temporary variables */ - - /* loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* read two samples at a time from sourceA */ - inA1 = *__SIMD32(pSrcA)++; - /* read two samples at a time from sourceB */ - inB1 = *__SIMD32(pSrcB)++; - /* read two samples at a time from sourceA */ - inA2 = *__SIMD32(pSrcA)++; - /* read two samples at a time from sourceB */ - inB2 = *__SIMD32(pSrcB)++; - - /* multiply mul = sourceA * sourceB */ - mul1 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16)); - mul2 = (q31_t) ((q15_t) inA1 * (q15_t) inB1); - mul3 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB2 >> 16)); - mul4 = (q31_t) ((q15_t) inA2 * (q15_t) inB2); - - /* saturate result to 16 bit */ - out1 = (q15_t) __SSAT(mul1 >> 15, 16); - out2 = (q15_t) __SSAT(mul2 >> 15, 16); - out3 = (q15_t) __SSAT(mul3 >> 15, 16); - out4 = (q15_t) __SSAT(mul4 >> 15, 16); - - /* store the result */ -#ifndef ARM_MATH_BIG_ENDIAN - - *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16); - *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16); - -#else - - *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16); - *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16); - -#endif // #ifndef ARM_MATH_BIG_ENDIAN - - /* Decrement the blockSize loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0 */ - - - while(blkCnt > 0u) - { - /* C = A * B */ - /* Multiply the inputs and store the result in the destination buffer */ - *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); - - /* Decrement the blockSize loop counter */ - blkCnt--; - } -} - -/** - * @} end of BasicMult group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q31.c deleted file mode 100644 index 4697a80626..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q31.c +++ /dev/null @@ -1,143 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_mult_q31.c -* -* Description: Q31 vector multiplication. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -* Version 0.0.5 2010/04/26 -* incorporated review comments and updated with latest CMSIS layer -* -* Version 0.0.3 2010/03/10 -* Initial version -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup BasicMult - * @{ - */ - -/** - * @brief Q31 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated. - */ - -void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counters */ - -#ifndef ARM_MATH_CM0 - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q31_t inA1, inA2, inA3, inA4; /* temporary input variables */ - q31_t inB1, inB2, inB3, inB4; /* temporary input variables */ - q31_t out1, out2, out3, out4; /* temporary output variables */ - - /* loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A * B */ - /* Multiply the inputs and then store the results in the destination buffer. */ - inA1 = *pSrcA++; - inA2 = *pSrcA++; - inA3 = *pSrcA++; - inA4 = *pSrcA++; - inB1 = *pSrcB++; - inB2 = *pSrcB++; - inB3 = *pSrcB++; - inB4 = *pSrcB++; - - out1 = ((q63_t) inA1 * inB1) >> 32; - out2 = ((q63_t) inA2 * inB2) >> 32; - out3 = ((q63_t) inA3 * inB3) >> 32; - out4 = ((q63_t) inA4 * inB4) >> 32; - - out1 = __SSAT(out1, 31); - out2 = __SSAT(out2, 31); - out3 = __SSAT(out3, 31); - out4 = __SSAT(out4, 31); - - *pDst++ = out1 << 1u; - *pDst++ = out2 << 1u; - *pDst++ = out3 << 1u; - *pDst++ = out4 << 1u; - - /* Decrement the blockSize loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0 */ - - while(blkCnt > 0u) - { - /* C = A * B */ - /* Multiply the inputs and then store the results in the destination buffer. */ - *pDst++ = - (q31_t) clip_q63_to_q31(((q63_t) (*pSrcA++) * (*pSrcB++)) >> 31); - - /* Decrement the blockSize loop counter */ - blkCnt--; - } -} - -/** - * @} end of BasicMult group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q7.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q7.c deleted file mode 100644 index 1e65a77a9c..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q7.c +++ /dev/null @@ -1,128 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_mult_q7.c -* -* Description: Q7 vector multiplication. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* -* Version 0.0.5 2010/04/26 -* incorporated review comments and updated with latest CMSIS layer -* -* Version 0.0.3 2010/03/10 DP -* Initial version -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup BasicMult - * @{ - */ - -/** - * @brief Q7 vector multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. - */ - -void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counters */ - -#ifndef ARM_MATH_CM0 - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q7_t out1, out2, out3, out4; /* Temporary variables to store the product */ - - /* loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A * B */ - /* Multiply the inputs and store the results in temporary variables */ - out1 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); - out2 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); - out3 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); - out4 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); - - /* Store the results of 4 inputs in the destination buffer in single cycle by packing */ - *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4); - - /* Decrement the blockSize loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0 */ - - - while(blkCnt > 0u) - { - /* C = A * B */ - /* Multiply the inputs and store the result in the destination buffer */ - *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8); - - /* Decrement the blockSize loop counter */ - blkCnt--; - } -} - -/** - * @} end of BasicMult group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_f32.c deleted file mode 100644 index b0f82896db..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_f32.c +++ /dev/null @@ -1,137 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_negate_f32.c -* -* Description: Negates floating-point vectors. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* ---------------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @defgroup negate Vector Negate - * - * Negates the elements of a vector. - * - * 
        
- *     pDst[n] = -pSrc[n],   0 <= n < blockSize.        
- *
- */ - -/** - * @addtogroup negate - * @{ - */ - -/** - * @brief Negates the elements of a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - -void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - - -#ifndef ARM_MATH_CM0 - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - float32_t in1, in2, in3, in4; /* temporary variables */ - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* read inputs from source */ - in1 = *pSrc; - in2 = *(pSrc + 1); - in3 = *(pSrc + 2); - in4 = *(pSrc + 3); - - /* negate the input */ - in1 = -in1; - in2 = -in2; - in3 = -in3; - in4 = -in4; - - /* store the result to destination */ - *pDst = in1; - *(pDst + 1) = in2; - *(pDst + 2) = in3; - *(pDst + 3) = in4; - - /* update pointers to process next samples */ - pSrc += 4u; - pDst += 4u; - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0 */ - - while(blkCnt > 0u) - { - /* C = -A */ - /* Negate and then store the results in the destination buffer. */ - *pDst++ = -*pSrc++; - - /* Decrement the loop counter */ - blkCnt--; - } -} - -/** - * @} end of negate group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q15.c deleted file mode 100644 index c47e03eeff..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q15.c +++ /dev/null @@ -1,137 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_negate_q15.c -* -* Description: Negates Q15 vectors. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* -------------------------------------------------------------------- */ -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup negate - * @{ - */ - -/** - * @brief Negates the elements of a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - * - * \par Conditions for optimum performance - * Input and output buffers should be aligned by 32-bit - * - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF. - */ - -void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - q15_t in; - -#ifndef ARM_MATH_CM0 - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - - q31_t in1, in2; /* Temporary variables */ - - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = -A */ - /* Read two inputs at a time */ - in1 = _SIMD32_OFFSET(pSrc); - in2 = _SIMD32_OFFSET(pSrc + 2); - - /* negate two samples at a time */ - in1 = __QSUB16(0, in1); - - /* negate two samples at a time */ - in2 = __QSUB16(0, in2); - - /* store the result to destination 2 samples at a time */ - _SIMD32_OFFSET(pDst) = in1; - /* store the result to destination 2 samples at a time */ - _SIMD32_OFFSET(pDst + 2) = in2; - - - /* update pointers to process next samples */ - pSrc += 4u; - pDst += 4u; - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0 */ - - while(blkCnt > 0u) - { - /* C = -A */ - /* Negate and then store the result in the destination buffer. */ - in = *pSrc++; - *pDst++ = (in == (q15_t) 0x8000) ? 0x7fff : -in; - - /* Decrement the loop counter */ - blkCnt--; - } -} - -/** - * @} end of negate group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q31.c deleted file mode 100644 index 362b54ecbc..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q31.c +++ /dev/null @@ -1,124 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_negate_q31.c -* -* Description: Negates Q31 vectors. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup negate - * @{ - */ - -/** - * @brief Negates the elements of a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF. - */ - -void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize) -{ - q31_t in; /* Temporary variable */ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0 - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q31_t in1, in2, in3, in4; - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = -A */ - /* Negate and then store the results in the destination buffer. */ - in1 = *pSrc++; - in2 = *pSrc++; - in3 = *pSrc++; - in4 = *pSrc++; - - *pDst++ = __QSUB(0, in1); - *pDst++ = __QSUB(0, in2); - *pDst++ = __QSUB(0, in3); - *pDst++ = __QSUB(0, in4); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0 */ - - - while(blkCnt > 0u) - { - /* C = -A */ - /* Negate and then store the result in the destination buffer. */ - in = *pSrc++; - *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in; - - /* Decrement the loop counter */ - blkCnt--; - } -} - -/** - * @} end of negate group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q7.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q7.c deleted file mode 100644 index 64914d291e..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q7.c +++ /dev/null @@ -1,120 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_negate_q7.c -* -* Description: Negates Q7 vectors. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup negate - * @{ - */ - -/** - * @brief Negates the elements of a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F. - */ - -void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - q7_t in; - -#ifndef ARM_MATH_CM0 - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q31_t input; /* Input values1-4 */ - q31_t zero = 0x00000000; - - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = -A */ - /* Read four inputs */ - input = *__SIMD32(pSrc)++; - - /* Store the Negated results in the destination buffer in a single cycle by packing the results */ - *__SIMD32(pDst)++ = __QSUB8(zero, input); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0 */ - - while(blkCnt > 0u) - { - /* C = -A */ - /* Negate and then store the results in the destination buffer. */ \ - in = *pSrc++; - *pDst++ = (in == (q7_t) 0x80) ? 0x7f : -in; - - /* Decrement the loop counter */ - blkCnt--; - } -} - -/** - * @} end of negate group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_f32.c deleted file mode 100644 index d7ca663bbd..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_f32.c +++ /dev/null @@ -1,158 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_offset_f32.c -* -* Description: Floating-point vector offset. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* ---------------------------------------------------------------------------- */ -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @defgroup offset Vector Offset - * - * Adds a constant offset to each element of a vector. - * - * 
        
- *     pDst[n] = pSrc[n] + offset,   0 <= n < blockSize.        
- *
- * - * There are separate functions for floating-point, Q7, Q15, and Q31 data types. - */ - -/** - * @addtogroup offset - * @{ - */ - -/** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - -void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0 - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - float32_t in1, in2, in3, in4; - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A + offset */ - /* Add offset and then store the results in the destination buffer. */ - /* read samples from source */ - in1 = *pSrc; - in2 = *(pSrc + 1); - - /* add offset to input */ - in1 = in1 + offset; - - /* read samples from source */ - in3 = *(pSrc + 2); - - /* add offset to input */ - in2 = in2 + offset; - - /* read samples from source */ - in4 = *(pSrc + 3); - - /* add offset to input */ - in3 = in3 + offset; - - /* store result to destination */ - *pDst = in1; - - /* add offset to input */ - in4 = in4 + offset; - - /* store result to destination */ - *(pDst + 1) = in2; - - /* store result to destination */ - *(pDst + 2) = in3; - - /* store result to destination */ - *(pDst + 3) = in4; - - /* update pointers to process next samples */ - pSrc += 4u; - pDst += 4u; - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0 */ - - while(blkCnt > 0u) - { - /* C = A + offset */ - /* Add offset and then store the result in the destination buffer. */ - *pDst++ = (*pSrc++) + offset; - - /* Decrement the loop counter */ - blkCnt--; - } -} - -/** - * @} end of offset group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q15.c deleted file mode 100644 index 0a06f4c9c1..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q15.c +++ /dev/null @@ -1,131 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_offset_q15.c -* -* Description: Q15 vector offset. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup offset - * @{ - */ - -/** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. - */ - -void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0 - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q31_t offset_packed; /* Offset packed to 32 bit */ - - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* Offset is packed to 32 bit in order to use SIMD32 for addition */ - offset_packed = __PKHBT(offset, offset, 16); - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A + offset */ - /* Add offset and then store the results in the destination buffer, 2 samples at a time. */ - *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed); - *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A + offset */ - /* Add offset and then store the results in the destination buffer. */ - *pDst++ = (q15_t) __QADD16(*pSrc++, offset); - - /* Decrement the loop counter */ - blkCnt--; - } - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A + offset */ - /* Add offset and then store the results in the destination buffer. */ - *pDst++ = (q15_t) __SSAT(((q31_t) * pSrc++ + offset), 16); - - /* Decrement the loop counter */ - blkCnt--; - } - -#endif /* #ifndef ARM_MATH_CM0 */ - -} - -/** - * @} end of offset group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q31.c deleted file mode 100644 index 4c2997ce6d..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q31.c +++ /dev/null @@ -1,135 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_offset_q31.c -* -* Description: Q31 vector offset. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup offset - * @{ - */ - -/** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. - */ - -void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0 - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q31_t in1, in2, in3, in4; - - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A + offset */ - /* Add offset and then store the results in the destination buffer. */ - in1 = *pSrc++; - in2 = *pSrc++; - in3 = *pSrc++; - in4 = *pSrc++; - - *pDst++ = __QADD(in1, offset); - *pDst++ = __QADD(in2, offset); - *pDst++ = __QADD(in3, offset); - *pDst++ = __QADD(in4, offset); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A + offset */ - /* Add offset and then store the result in the destination buffer. */ - *pDst++ = __QADD(*pSrc++, offset); - - /* Decrement the loop counter */ - blkCnt--; - } - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A + offset */ - /* Add offset and then store the result in the destination buffer. */ - *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrc++ + offset); - - /* Decrement the loop counter */ - blkCnt--; - } - -#endif /* #ifndef ARM_MATH_CM0 */ - -} - -/** - * @} end of offset group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q7.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q7.c deleted file mode 100644 index e54dba9dab..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q7.c +++ /dev/null @@ -1,130 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_offset_q7.c -* -* Description: Q7 vector offset. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup offset - * @{ - */ - -/** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * Results outside of the allowable Q7 range [0x80 0x7F] are saturated. - */ - -void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0 - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q31_t offset_packed; /* Offset packed to 32 bit */ - - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* Offset is packed to 32 bit in order to use SIMD32 for addition */ - offset_packed = __PACKq7(offset, offset, offset, offset); - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A + offset */ - /* Add offset and then store the results in the destination bufferfor 4 samples at a time. */ - *__SIMD32(pDst)++ = __QADD8(*__SIMD32(pSrc)++, offset_packed); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A + offset */ - /* Add offset and then store the result in the destination buffer. */ - *pDst++ = (q7_t) __SSAT(*pSrc++ + offset, 8); - - /* Decrement the loop counter */ - blkCnt--; - } - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A + offset */ - /* Add offset and then store the result in the destination buffer. */ - *pDst++ = (q7_t) __SSAT((q15_t) * pSrc++ + offset, 8); - - /* Decrement the loop counter */ - blkCnt--; - } - -#endif /* #ifndef ARM_MATH_CM0 */ - -} - -/** - * @} end of offset group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_f32.c deleted file mode 100644 index 0baf3863fe..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_f32.c +++ /dev/null @@ -1,161 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_scale_f32.c -* -* Description: Multiplies a floating-point vector by a scalar. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* ---------------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @defgroup scale Vector Scale - * - * Multiply a vector by a scalar value. For floating-point data, the algorithm used is: - * - * 
        
- *     pDst[n] = pSrc[n] * scale,   0 <= n < blockSize.        
- *
- * - * In the fixed-point Q7, Q15, and Q31 functions, scale is represented by - * a fractional multiplication scaleFract and an arithmetic shift shift. - * The shift allows the gain of the scaling operation to exceed 1.0. - * The algorithm used with fixed-point data is: - * - * 
        
- *     pDst[n] = (pSrc[n] * scaleFract) << shift,   0 <= n < blockSize.        
- *
- * - * The overall scale factor applied to the fixed-point data is - * 
        
- *     scale = scaleFract * 2^shift.        
- *
- */ - -/** - * @addtogroup scale - * @{ - */ - -/** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - -void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ -#ifndef ARM_MATH_CM0 - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - float32_t in1, in2, in3, in4; /* temporary variabels */ - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A * scale */ - /* Scale the input and then store the results in the destination buffer. */ - /* read input samples from source */ - in1 = *pSrc; - in2 = *(pSrc + 1); - - /* multiply with scaling factor */ - in1 = in1 * scale; - - /* read input sample from source */ - in3 = *(pSrc + 2); - - /* multiply with scaling factor */ - in2 = in2 * scale; - - /* read input sample from source */ - in4 = *(pSrc + 3); - - /* multiply with scaling factor */ - in3 = in3 * scale; - in4 = in4 * scale; - /* store the result to destination */ - *pDst = in1; - *(pDst + 1) = in2; - *(pDst + 2) = in3; - *(pDst + 3) = in4; - - /* update pointers to process next samples */ - pSrc += 4u; - pDst += 4u; - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0 */ - - while(blkCnt > 0u) - { - /* C = A * scale */ - /* Scale the input and then store the result in the destination buffer. */ - *pDst++ = (*pSrc++) * scale; - - /* Decrement the loop counter */ - blkCnt--; - } -} - -/** - * @} end of scale group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q15.c deleted file mode 100644 index 9b35ffec66..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q15.c +++ /dev/null @@ -1,157 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_scale_q15.c -* -* Description: Multiplies a Q15 vector by a scalar. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup scale - * @{ - */ - -/** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The input data *pSrc and scaleFract are in 1.15 format. - * These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format. - */ - - -void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize) -{ - int8_t kShift = 15 - shift; /* shift to apply after scaling */ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0 - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q15_t in1, in2, in3, in4; - q31_t inA1, inA2; /* Temporary variables */ - q31_t out1, out2, out3, out4; - - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* Reading 2 inputs from memory */ - inA1 = *__SIMD32(pSrc)++; - inA2 = *__SIMD32(pSrc)++; - - /* C = A * scale */ - /* Scale the inputs and then store the 2 results in the destination buffer - * in single cycle by packing the outputs */ - out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract); - out2 = (q31_t) ((q15_t) inA1 * scaleFract); - out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract); - out4 = (q31_t) ((q15_t) inA2 * scaleFract); - - /* apply shifting */ - out1 = out1 >> kShift; - out2 = out2 >> kShift; - out3 = out3 >> kShift; - out4 = out4 >> kShift; - - /* saturate the output */ - in1 = (q15_t) (__SSAT(out1, 16)); - in2 = (q15_t) (__SSAT(out2, 16)); - in3 = (q15_t) (__SSAT(out3, 16)); - in4 = (q15_t) (__SSAT(out4, 16)); - - /* store the result to destination */ - *__SIMD32(pDst)++ = __PKHBT(in2, in1, 16); - *__SIMD32(pDst)++ = __PKHBT(in4, in3, 16); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A * scale */ - /* Scale the input and then store the result in the destination buffer. */ - *pDst++ = (q15_t) (__SSAT(((*pSrc++) * scaleFract) >> kShift, 16)); - - /* Decrement the loop counter */ - blkCnt--; - } - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A * scale */ - /* Scale the input and then store the result in the destination buffer. */ - *pDst++ = (q15_t) (__SSAT(((q31_t) * pSrc++ * scaleFract) >> kShift, 16)); - - /* Decrement the loop counter */ - blkCnt--; - } - -#endif /* #ifndef ARM_MATH_CM0 */ - -} - -/** - * @} end of scale group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q31.c deleted file mode 100644 index cef8102450..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q31.c +++ /dev/null @@ -1,221 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_scale_q31.c -* -* Description: Multiplies a Q31 vector by a scalar. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup scale - * @{ - */ - -/** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The input data *pSrc and scaleFract are in 1.31 format. - * These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format. - */ - -void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize) -{ - int8_t kShift = shift + 1; /* Shift to apply after scaling */ - int8_t sign = (kShift & 0x80); - uint32_t blkCnt; /* loop counter */ - q31_t in, out; - -#ifndef ARM_MATH_CM0 - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - - q31_t in1, in2, in3, in4; /* temporary input variables */ - q31_t out1, out2, out3, out4; /* temporary output variabels */ - - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - if(sign == 0u) - { - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* read four inputs from source */ - in1 = *pSrc; - in2 = *(pSrc + 1); - in3 = *(pSrc + 2); - in4 = *(pSrc + 3); - - /* multiply input with scaler value */ - in1 = ((q63_t) in1 * scaleFract) >> 32; - in2 = ((q63_t) in2 * scaleFract) >> 32; - in3 = ((q63_t) in3 * scaleFract) >> 32; - in4 = ((q63_t) in4 * scaleFract) >> 32; - - /* apply shifting */ - out1 = in1 << kShift; - out2 = in2 << kShift; - - /* saturate the results. */ - if(in1 != (out1 >> kShift)) - out1 = 0x7FFFFFFF ^ (in1 >> 31); - - if(in2 != (out2 >> kShift)) - out2 = 0x7FFFFFFF ^ (in2 >> 31); - - out3 = in3 << kShift; - out4 = in4 << kShift; - - *pDst = out1; - *(pDst + 1) = out2; - - if(in3 != (out3 >> kShift)) - out3 = 0x7FFFFFFF ^ (in3 >> 31); - - if(in4 != (out4 >> kShift)) - out4 = 0x7FFFFFFF ^ (in4 >> 31); - - /* Store result destination */ - *(pDst + 2) = out3; - *(pDst + 3) = out4; - - /* Update pointers to process next sampels */ - pSrc += 4u; - pDst += 4u; - - /* Decrement the loop counter */ - blkCnt--; - } - - } - else - { - kShift = -kShift; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* read four inputs from source */ - in1 = *pSrc; - in2 = *(pSrc + 1); - in3 = *(pSrc + 2); - in4 = *(pSrc + 3); - - /* multiply input with scaler value */ - in1 = ((q63_t) in1 * scaleFract) >> 32; - in2 = ((q63_t) in2 * scaleFract) >> 32; - in3 = ((q63_t) in3 * scaleFract) >> 32; - in4 = ((q63_t) in4 * scaleFract) >> 32; - - /* apply shifting */ - out1 = in1 >> kShift; - out2 = in2 >> kShift; - - out3 = in3 >> kShift; - out4 = in4 >> kShift; - - /* Store result destination */ - *pDst = out1; - *(pDst + 1) = out2; - - *(pDst + 2) = out3; - *(pDst + 3) = out4; - - /* Update pointers to process next sampels */ - pSrc += 4u; - pDst += 4u; - - /* Decrement the loop counter */ - blkCnt--; - } - } - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0 */ - - while(blkCnt > 0u) - { - /* C = A * scale */ - /* Scale the input and then store the result in the destination buffer. */ - in = *pSrc++; - in = ((q63_t) in * scaleFract) >> 32; - - if(sign == 0) - { - out = in << kShift; - if(in != (out >> kShift)) - out = 0x7FFFFFFF ^ (in >> 31); - } - else - { - out = in >> kShift; - } - - *pDst++ = out; - - /* Decrement the loop counter */ - blkCnt--; - } -} - -/** - * @} end of scale group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q7.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q7.c deleted file mode 100644 index c899d91044..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q7.c +++ /dev/null @@ -1,144 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_scale_q7.c -* -* Description: Multiplies a Q7 vector by a scalar. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup scale - * @{ - */ - -/** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The input data *pSrc and scaleFract are in 1.7 format. - * These are multiplied to yield a 2.14 intermediate result and this is shifted with saturation to 1.7 format. - */ - -void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize) -{ - int8_t kShift = 7 - shift; /* shift to apply after scaling */ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0 - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q7_t in1, in2, in3, in4, out1, out2, out3, out4; /* Temporary variables to store input & output */ - - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* Reading 4 inputs from memory */ - in1 = *pSrc++; - in2 = *pSrc++; - in3 = *pSrc++; - in4 = *pSrc++; - - /* C = A * scale */ - /* Scale the inputs and then store the results in the temporary variables. */ - out1 = (q7_t) (__SSAT(((in1) * scaleFract) >> kShift, 8)); - out2 = (q7_t) (__SSAT(((in2) * scaleFract) >> kShift, 8)); - out3 = (q7_t) (__SSAT(((in3) * scaleFract) >> kShift, 8)); - out4 = (q7_t) (__SSAT(((in4) * scaleFract) >> kShift, 8)); - - /* Packing the individual outputs into 32bit and storing in - * destination buffer in single write */ - *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A * scale */ - /* Scale the input and then store the result in the destination buffer. */ - *pDst++ = (q7_t) (__SSAT(((*pSrc++) * scaleFract) >> kShift, 8)); - - /* Decrement the loop counter */ - blkCnt--; - } - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A * scale */ - /* Scale the input and then store the result in the destination buffer. */ - *pDst++ = (q7_t) (__SSAT((((q15_t) * pSrc++ * scaleFract) >> kShift), 8)); - - /* Decrement the loop counter */ - blkCnt--; - } - -#endif /* #ifndef ARM_MATH_CM0 */ - -} - -/** - * @} end of scale group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q15.c deleted file mode 100644 index b2ee2a5a41..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q15.c +++ /dev/null @@ -1,243 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_shift_q15.c -* -* Description: Shifts the elements of a Q15 vector by a specified number of bits. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup shift - * @{ - */ - -/** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. - */ - -void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - uint8_t sign; /* Sign of shiftBits */ - -#ifndef ARM_MATH_CM0 - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - - q15_t in1, in2; /* Temporary variables */ - - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* Getting the sign of shiftBits */ - sign = (shiftBits & 0x80); - - /* If the shift value is positive then do right shift else left shift */ - if(sign == 0u) - { - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* Read 2 inputs */ - in1 = *pSrc++; - in2 = *pSrc++; - /* C = A << shiftBits */ - /* Shift the inputs and then store the results in the destination buffer. */ -#ifndef ARM_MATH_BIG_ENDIAN - - *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16), - __SSAT((in2 << shiftBits), 16), 16); - -#else - - *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16), - __SSAT((in1 << shiftBits), 16), 16); - -#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ - - in1 = *pSrc++; - in2 = *pSrc++; - -#ifndef ARM_MATH_BIG_ENDIAN - - *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16), - __SSAT((in2 << shiftBits), 16), 16); - -#else - - *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16), - __SSAT((in1 << shiftBits), 16), 16); - -#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A << shiftBits */ - /* Shift and then store the results in the destination buffer. */ - *pDst++ = __SSAT((*pSrc++ << shiftBits), 16); - - /* Decrement the loop counter */ - blkCnt--; - } - } - else - { - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* Read 2 inputs */ - in1 = *pSrc++; - in2 = *pSrc++; - - /* C = A >> shiftBits */ - /* Shift the inputs and then store the results in the destination buffer. */ -#ifndef ARM_MATH_BIG_ENDIAN - - *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits), - (in2 >> -shiftBits), 16); - -#else - - *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits), - (in1 >> -shiftBits), 16); - -#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ - - in1 = *pSrc++; - in2 = *pSrc++; - -#ifndef ARM_MATH_BIG_ENDIAN - - *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits), - (in2 >> -shiftBits), 16); - -#else - - *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits), - (in1 >> -shiftBits), 16); - -#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A >> shiftBits */ - /* Shift the inputs and then store the results in the destination buffer. */ - *pDst++ = (*pSrc++ >> -shiftBits); - - /* Decrement the loop counter */ - blkCnt--; - } - } - -#else - - /* Run the below code for Cortex-M0 */ - - /* Getting the sign of shiftBits */ - sign = (shiftBits & 0x80); - - /* If the shift value is positive then do right shift else left shift */ - if(sign == 0u) - { - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A << shiftBits */ - /* Shift and then store the results in the destination buffer. */ - *pDst++ = __SSAT(((q31_t) * pSrc++ << shiftBits), 16); - - /* Decrement the loop counter */ - blkCnt--; - } - } - else - { - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A >> shiftBits */ - /* Shift the inputs and then store the results in the destination buffer. */ - *pDst++ = (*pSrc++ >> -shiftBits); - - /* Decrement the loop counter */ - blkCnt--; - } - } - -#endif /* #ifndef ARM_MATH_CM0 */ - -} - -/** - * @} end of shift group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q31.c deleted file mode 100644 index 799035e80c..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q31.c +++ /dev/null @@ -1,195 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_shift_q31.c -* -* Description: Shifts the elements of a Q31 vector by a specified number of bits. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ -/** - * @defgroup shift Vector Shift - * - * Shifts the elements of a fixed-point vector by a specified number of bits. - * There are separate functions for Q7, Q15, and Q31 data types. - * The underlying algorithm used is: - * - * 
        
- *     pDst[n] = pSrc[n] << shift,   0 <= n < blockSize.        
- *
- * - * If shift is positive then the elements of the vector are shifted to the left. - * If shift is negative then the elements of the vector are shifted to the right. - */ - -/** - * @addtogroup shift - * @{ - */ - -/** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - * - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated. - */ - -void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - uint8_t sign = (shiftBits & 0x80); /* Sign of shiftBits */ - -#ifndef ARM_MATH_CM0 - - q31_t in1, in2, in3, in4; /* Temporary input variables */ - q31_t out1, out2, out3, out4; /* Temporary output variables */ - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - - if(sign == 0u) - { - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A << shiftBits */ - /* Shift the input and then store the results in the destination buffer. */ - in1 = *pSrc; - in2 = *(pSrc + 1); - out1 = in1 << shiftBits; - in3 = *(pSrc + 2); - out2 = in2 << shiftBits; - in4 = *(pSrc + 3); - if(in1 != (out1 >> shiftBits)) - out1 = 0x7FFFFFFF ^ (in1 >> 31); - - if(in2 != (out2 >> shiftBits)) - out2 = 0x7FFFFFFF ^ (in2 >> 31); - - *pDst = out1; - out3 = in3 << shiftBits; - *(pDst + 1) = out2; - out4 = in4 << shiftBits; - - if(in3 != (out3 >> shiftBits)) - out3 = 0x7FFFFFFF ^ (in3 >> 31); - - if(in4 != (out4 >> shiftBits)) - out4 = 0x7FFFFFFF ^ (in4 >> 31); - - *(pDst + 2) = out3; - *(pDst + 3) = out4; - - /* Update destination pointer to process next sampels */ - pSrc += 4u; - pDst += 4u; - - /* Decrement the loop counter */ - blkCnt--; - } - } - else - { - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A >> shiftBits */ - /* Shift the input and then store the results in the destination buffer. */ - in1 = *pSrc; - in2 = *(pSrc + 1); - in3 = *(pSrc + 2); - in4 = *(pSrc + 3); - - *pDst = (in1 >> -shiftBits); - *(pDst + 1) = (in2 >> -shiftBits); - *(pDst + 2) = (in3 >> -shiftBits); - *(pDst + 3) = (in4 >> -shiftBits); - - - pSrc += 4u; - pDst += 4u; - - blkCnt--; - } - - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0 */ - - - while(blkCnt > 0u) - { - /* C = A (>> or <<) shiftBits */ - /* Shift the input and then store the result in the destination buffer. */ - *pDst++ = (sign == 0u) ? clip_q63_to_q31((q63_t) * pSrc++ << shiftBits) : - (*pSrc++ >> -shiftBits); - - /* Decrement the loop counter */ - blkCnt--; - } - - -} - -/** - * @} end of shift group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q7.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q7.c deleted file mode 100644 index 687a333234..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q7.c +++ /dev/null @@ -1,215 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_shift_q7.c -* -* Description: Processing function for the Q7 Shifting -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup shift - * @{ - */ - - -/** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - * - * \par Conditions for optimum performance - * Input and output buffers should be aligned by 32-bit - * - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * Results outside of the allowable Q7 range [0x8 0x7F] will be saturated. - */ - -void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - uint8_t sign; /* Sign of shiftBits */ - -#ifndef ARM_MATH_CM0 - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q7_t in1; /* Input value1 */ - q7_t in2; /* Input value2 */ - q7_t in3; /* Input value3 */ - q7_t in4; /* Input value4 */ - - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* Getting the sign of shiftBits */ - sign = (shiftBits & 0x80); - - /* If the shift value is positive then do right shift else left shift */ - if(sign == 0u) - { - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A << shiftBits */ - /* Read 4 inputs */ - in1 = *pSrc; - in2 = *(pSrc + 1); - in3 = *(pSrc + 2); - in4 = *(pSrc + 3); - - /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */ - *__SIMD32(pDst)++ = __PACKq7(__SSAT((in1 << shiftBits), 8), - __SSAT((in2 << shiftBits), 8), - __SSAT((in3 << shiftBits), 8), - __SSAT((in4 << shiftBits), 8)); - /* Update source pointer to process next sampels */ - pSrc += 4u; - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A << shiftBits */ - /* Shift the input and then store the result in the destination buffer. */ - *pDst++ = (q7_t) __SSAT((*pSrc++ << shiftBits), 8); - - /* Decrement the loop counter */ - blkCnt--; - } - } - else - { - shiftBits = -shiftBits; - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A >> shiftBits */ - /* Read 4 inputs */ - in1 = *pSrc; - in2 = *(pSrc + 1); - in3 = *(pSrc + 2); - in4 = *(pSrc + 3); - - /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */ - *__SIMD32(pDst)++ = __PACKq7((in1 >> shiftBits), (in2 >> shiftBits), - (in3 >> shiftBits), (in4 >> shiftBits)); - - - pSrc += 4u; - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A >> shiftBits */ - /* Shift the input and then store the result in the destination buffer. */ - in1 = *pSrc++; - *pDst++ = (in1 >> shiftBits); - - /* Decrement the loop counter */ - blkCnt--; - } - } - -#else - - /* Run the below code for Cortex-M0 */ - - /* Getting the sign of shiftBits */ - sign = (shiftBits & 0x80); - - /* If the shift value is positive then do right shift else left shift */ - if(sign == 0u) - { - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A << shiftBits */ - /* Shift the input and then store the result in the destination buffer. */ - *pDst++ = (q7_t) __SSAT(((q15_t) * pSrc++ << shiftBits), 8); - - /* Decrement the loop counter */ - blkCnt--; - } - } - else - { - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A >> shiftBits */ - /* Shift the input and then store the result in the destination buffer. */ - *pDst++ = (*pSrc++ >> -shiftBits); - - /* Decrement the loop counter */ - blkCnt--; - } - } - -#endif /* #ifndef ARM_MATH_CM0 */ -} - -/** - * @} end of shift group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_f32.c deleted file mode 100644 index 0fcd328693..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_f32.c +++ /dev/null @@ -1,145 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_sub_f32.c -* -* Description: Floating-point vector subtraction. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* ---------------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @defgroup BasicSub Vector Subtraction - * - * Element-by-element subtraction of two vectors. - * - * 
        
- *     pDst[n] = pSrcA[n] - pSrcB[n],   0 <= n < blockSize.        
- *
- * - * There are separate functions for floating-point, Q7, Q15, and Q31 data types. - */ - -/** - * @addtogroup BasicSub - * @{ - */ - - -/** - * @brief Floating-point vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - -void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0 - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - float32_t inA1, inA2, inA3, inA4; /* temporary variables */ - float32_t inB1, inB2, inB3, inB4; /* temporary variables */ - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A - B */ - /* Subtract and then store the results in the destination buffer. */ - /* Read 4 input samples from sourceA and sourceB */ - inA1 = *pSrcA; - inB1 = *pSrcB; - inA2 = *(pSrcA + 1); - inB2 = *(pSrcB + 1); - inA3 = *(pSrcA + 2); - inB3 = *(pSrcB + 2); - inA4 = *(pSrcA + 3); - inB4 = *(pSrcB + 3); - - /* dst = srcA - srcB */ - /* subtract and store the result */ - *pDst = inA1 - inB1; - *(pDst + 1) = inA2 - inB2; - *(pDst + 2) = inA3 - inB3; - *(pDst + 3) = inA4 - inB4; - - - /* Update pointers to process next sampels */ - pSrcA += 4u; - pSrcB += 4u; - pDst += 4u; - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - -#endif /* #ifndef ARM_MATH_CM0 */ - - while(blkCnt > 0u) - { - /* C = A - B */ - /* Subtract and then store the results in the destination buffer. */ - *pDst++ = (*pSrcA++) - (*pSrcB++); - - /* Decrement the loop counter */ - blkCnt--; - } -} - -/** - * @} end of BasicSub group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q15.c deleted file mode 100644 index c372c12357..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q15.c +++ /dev/null @@ -1,135 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_sub_q15.c -* -* Description: Q15 vector subtraction. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup BasicSub - * @{ - */ - -/** - * @brief Q15 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. - */ - -void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - - -#ifndef ARM_MATH_CM0 - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q31_t inA1, inA2; - q31_t inB1, inB2; - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A - B */ - /* Subtract and then store the results in the destination buffer two samples at a time. */ - inA1 = *__SIMD32(pSrcA)++; - inA2 = *__SIMD32(pSrcA)++; - inB1 = *__SIMD32(pSrcB)++; - inB2 = *__SIMD32(pSrcB)++; - - *__SIMD32(pDst)++ = __QSUB16(inA1, inB1); - *__SIMD32(pDst)++ = __QSUB16(inA2, inB2); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A - B */ - /* Subtract and then store the result in the destination buffer. */ - *pDst++ = (q15_t) __QSUB16(*pSrcA++, *pSrcB++); - - /* Decrement the loop counter */ - blkCnt--; - } - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A - B */ - /* Subtract and then store the result in the destination buffer. */ - *pDst++ = (q15_t) __SSAT(((q31_t) * pSrcA++ - *pSrcB++), 16); - - /* Decrement the loop counter */ - blkCnt--; - } - -#endif /* #ifndef ARM_MATH_CM0 */ - - -} - -/** - * @} end of BasicSub group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q31.c deleted file mode 100644 index 829f25db0b..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q31.c +++ /dev/null @@ -1,141 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_sub_q31.c -* -* Description: Q31 vector subtraction. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup BasicSub - * @{ - */ - -/** - * @brief Q31 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated. - */ - -void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - - -#ifndef ARM_MATH_CM0 - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - q31_t inA1, inA2, inA3, inA4; - q31_t inB1, inB2, inB3, inB4; - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A - B */ - /* Subtract and then store the results in the destination buffer. */ - inA1 = *pSrcA++; - inA2 = *pSrcA++; - inB1 = *pSrcB++; - inB2 = *pSrcB++; - - inA3 = *pSrcA++; - inA4 = *pSrcA++; - inB3 = *pSrcB++; - inB4 = *pSrcB++; - - *pDst++ = __QSUB(inA1, inB1); - *pDst++ = __QSUB(inA2, inB2); - *pDst++ = __QSUB(inA3, inB3); - *pDst++ = __QSUB(inA4, inB4); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A - B */ - /* Subtract and then store the result in the destination buffer. */ - *pDst++ = __QSUB(*pSrcA++, *pSrcB++); - - /* Decrement the loop counter */ - blkCnt--; - } - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A - B */ - /* Subtract and then store the result in the destination buffer. */ - *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrcA++ - *pSrcB++); - - /* Decrement the loop counter */ - blkCnt--; - } - -#endif /* #ifndef ARM_MATH_CM0 */ - -} - -/** - * @} end of BasicSub group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q7.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q7.c deleted file mode 100644 index 0bbaf8f055..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q7.c +++ /dev/null @@ -1,126 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_sub_q7.c -* -* Description: Q7 vector subtraction. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -* Version 0.0.7 2010/06/10 -* Misra-C changes done -* -------------------------------------------------------------------- */ - -#include "arm_math.h" - -/** - * @ingroup groupMath - */ - -/** - * @addtogroup BasicSub - * @{ - */ - -/** - * @brief Q7 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function uses saturating arithmetic. - * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. - */ - -void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize) -{ - uint32_t blkCnt; /* loop counter */ - -#ifndef ARM_MATH_CM0 - -/* Run the below code for Cortex-M4 and Cortex-M3 */ - - /*loop Unrolling */ - blkCnt = blockSize >> 2u; - - /* First part of the processing with loop unrolling. Compute 4 outputs at a time. - ** a second loop below computes the remaining 1 to 3 samples. */ - while(blkCnt > 0u) - { - /* C = A - B */ - /* Subtract and then store the results in the destination buffer 4 samples at a time. */ - *__SIMD32(pDst)++ = __QSUB8(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++); - - /* Decrement the loop counter */ - blkCnt--; - } - - /* If the blockSize is not a multiple of 4, compute any remaining output samples here. - ** No loop unrolling is used. */ - blkCnt = blockSize % 0x4u; - - while(blkCnt > 0u) - { - /* C = A - B */ - /* Subtract and then store the result in the destination buffer. */ - *pDst++ = __SSAT(*pSrcA++ - *pSrcB++, 8); - - /* Decrement the loop counter */ - blkCnt--; - } - -#else - - /* Run the below code for Cortex-M0 */ - - /* Initialize blkCnt with number of samples */ - blkCnt = blockSize; - - while(blkCnt > 0u) - { - /* C = A - B */ - /* Subtract and then store the result in the destination buffer. */ - *pDst++ = (q7_t) __SSAT((q15_t) * pSrcA++ - *pSrcB++, 8); - - /* Decrement the loop counter */ - blkCnt--; - } - -#endif /* #ifndef ARM_MATH_CM0 */ - - -} - -/** - * @} end of BasicSub group - */ diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/CommonTables/arm_common_tables.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/CommonTables/arm_common_tables.c deleted file mode 100644 index eeea42387f..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/CommonTables/arm_common_tables.c +++ /dev/null @@ -1,4689 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_common_tables.c -* -* Description: This file has common tables like fft twiddle factors, Bitreverse, reciprocal etc which are used across different functions -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -------------------------------------------------------------------- */ - - -#include "arm_math.h" -#include "arm_common_tables.h" - -/** - * @ingroup groupTransforms - */ - -/** - * @addtogroup CFFT_CIFFT Complex FFT Tables - * @{ - */ - -/** -* \par -* Pseudo code for Generation of Bit reversal Table is -* \par -* 
for(l=1;l <= N/4;l++)    
-* {    
-*   for(i=0;i> 1;    
-*  }
-* \par -* where N = 4096 logN2 = 12 -* \par -* N is the maximum FFT Size supported -*/ - -/* -* @brief Table for bit reversal process -*/ -const uint16_t armBitRevTable[1024] = { - 0x400, 0x200, 0x600, 0x100, 0x500, 0x300, 0x700, - 0x80, 0x480, 0x280, 0x680, 0x180, 0x580, 0x380, - 0x780, 0x40, 0x440, 0x240, 0x640, 0x140, 0x540, - 0x340, 0x740, 0xc0, 0x4c0, 0x2c0, 0x6c0, 0x1c0, - 0x5c0, 0x3c0, 0x7c0, 0x20, 0x420, 0x220, 0x620, - 0x120, 0x520, 0x320, 0x720, 0xa0, 0x4a0, 0x2a0, - 0x6a0, 0x1a0, 0x5a0, 0x3a0, 0x7a0, 0x60, 0x460, - 0x260, 0x660, 0x160, 0x560, 0x360, 0x760, 0xe0, - 0x4e0, 0x2e0, 0x6e0, 0x1e0, 0x5e0, 0x3e0, 0x7e0, - 0x10, 0x410, 0x210, 0x610, 0x110, 0x510, 0x310, - 0x710, 0x90, 0x490, 0x290, 0x690, 0x190, 0x590, - 0x390, 0x790, 0x50, 0x450, 0x250, 0x650, 0x150, - 0x550, 0x350, 0x750, 0xd0, 0x4d0, 0x2d0, 0x6d0, - 0x1d0, 0x5d0, 0x3d0, 0x7d0, 0x30, 0x430, 0x230, - 0x630, 0x130, 0x530, 0x330, 0x730, 0xb0, 0x4b0, - 0x2b0, 0x6b0, 0x1b0, 0x5b0, 0x3b0, 0x7b0, 0x70, - 0x470, 0x270, 0x670, 0x170, 0x570, 0x370, 0x770, - 0xf0, 0x4f0, 0x2f0, 0x6f0, 0x1f0, 0x5f0, 0x3f0, - 0x7f0, 0x8, 0x408, 0x208, 0x608, 0x108, 0x508, - 0x308, 0x708, 0x88, 0x488, 0x288, 0x688, 0x188, - 0x588, 0x388, 0x788, 0x48, 0x448, 0x248, 0x648, - 0x148, 0x548, 0x348, 0x748, 0xc8, 0x4c8, 0x2c8, - 0x6c8, 0x1c8, 0x5c8, 0x3c8, 0x7c8, 0x28, 0x428, - 0x228, 0x628, 0x128, 0x528, 0x328, 0x728, 0xa8, - 0x4a8, 0x2a8, 0x6a8, 0x1a8, 0x5a8, 0x3a8, 0x7a8, - 0x68, 0x468, 0x268, 0x668, 0x168, 0x568, 0x368, - 0x768, 0xe8, 0x4e8, 0x2e8, 0x6e8, 0x1e8, 0x5e8, - 0x3e8, 0x7e8, 0x18, 0x418, 0x218, 0x618, 0x118, - 0x518, 0x318, 0x718, 0x98, 0x498, 0x298, 0x698, - 0x198, 0x598, 0x398, 0x798, 0x58, 0x458, 0x258, - 0x658, 0x158, 0x558, 0x358, 0x758, 0xd8, 0x4d8, - 0x2d8, 0x6d8, 0x1d8, 0x5d8, 0x3d8, 0x7d8, 0x38, - 0x438, 0x238, 0x638, 0x138, 0x538, 0x338, 0x738, - 0xb8, 0x4b8, 0x2b8, 0x6b8, 0x1b8, 0x5b8, 0x3b8, - 0x7b8, 0x78, 0x478, 0x278, 0x678, 0x178, 0x578, - 0x378, 0x778, 0xf8, 0x4f8, 0x2f8, 0x6f8, 0x1f8, - 0x5f8, 0x3f8, 0x7f8, 0x4, 0x404, 0x204, 0x604, - 0x104, 0x504, 0x304, 0x704, 0x84, 0x484, 0x284, - 0x684, 0x184, 0x584, 0x384, 0x784, 0x44, 0x444, - 0x244, 0x644, 0x144, 0x544, 0x344, 0x744, 0xc4, - 0x4c4, 0x2c4, 0x6c4, 0x1c4, 0x5c4, 0x3c4, 0x7c4, - 0x24, 0x424, 0x224, 0x624, 0x124, 0x524, 0x324, - 0x724, 0xa4, 0x4a4, 0x2a4, 0x6a4, 0x1a4, 0x5a4, - 0x3a4, 0x7a4, 0x64, 0x464, 0x264, 0x664, 0x164, - 0x564, 0x364, 0x764, 0xe4, 0x4e4, 0x2e4, 0x6e4, - 0x1e4, 0x5e4, 0x3e4, 0x7e4, 0x14, 0x414, 0x214, - 0x614, 0x114, 0x514, 0x314, 0x714, 0x94, 0x494, - 0x294, 0x694, 0x194, 0x594, 0x394, 0x794, 0x54, - 0x454, 0x254, 0x654, 0x154, 0x554, 0x354, 0x754, - 0xd4, 0x4d4, 0x2d4, 0x6d4, 0x1d4, 0x5d4, 0x3d4, - 0x7d4, 0x34, 0x434, 0x234, 0x634, 0x134, 0x534, - 0x334, 0x734, 0xb4, 0x4b4, 0x2b4, 0x6b4, 0x1b4, - 0x5b4, 0x3b4, 0x7b4, 0x74, 0x474, 0x274, 0x674, - 0x174, 0x574, 0x374, 0x774, 0xf4, 0x4f4, 0x2f4, - 0x6f4, 0x1f4, 0x5f4, 0x3f4, 0x7f4, 0xc, 0x40c, - 0x20c, 0x60c, 0x10c, 0x50c, 0x30c, 0x70c, 0x8c, - 0x48c, 0x28c, 0x68c, 0x18c, 0x58c, 0x38c, 0x78c, - 0x4c, 0x44c, 0x24c, 0x64c, 0x14c, 0x54c, 0x34c, - 0x74c, 0xcc, 0x4cc, 0x2cc, 0x6cc, 0x1cc, 0x5cc, - 0x3cc, 0x7cc, 0x2c, 0x42c, 0x22c, 0x62c, 0x12c, - 0x52c, 0x32c, 0x72c, 0xac, 0x4ac, 0x2ac, 0x6ac, - 0x1ac, 0x5ac, 0x3ac, 0x7ac, 0x6c, 0x46c, 0x26c, - 0x66c, 0x16c, 0x56c, 0x36c, 0x76c, 0xec, 0x4ec, - 0x2ec, 0x6ec, 0x1ec, 0x5ec, 0x3ec, 0x7ec, 0x1c, - 0x41c, 0x21c, 0x61c, 0x11c, 0x51c, 0x31c, 0x71c, - 0x9c, 0x49c, 0x29c, 0x69c, 0x19c, 0x59c, 0x39c, - 0x79c, 0x5c, 0x45c, 0x25c, 0x65c, 0x15c, 0x55c, - 0x35c, 0x75c, 0xdc, 0x4dc, 0x2dc, 0x6dc, 0x1dc, - 0x5dc, 0x3dc, 0x7dc, 0x3c, 0x43c, 0x23c, 0x63c, - 0x13c, 0x53c, 0x33c, 0x73c, 0xbc, 0x4bc, 0x2bc, - 0x6bc, 0x1bc, 0x5bc, 0x3bc, 0x7bc, 0x7c, 0x47c, - 0x27c, 0x67c, 0x17c, 0x57c, 0x37c, 0x77c, 0xfc, - 0x4fc, 0x2fc, 0x6fc, 0x1fc, 0x5fc, 0x3fc, 0x7fc, - 0x2, 0x402, 0x202, 0x602, 0x102, 0x502, 0x302, - 0x702, 0x82, 0x482, 0x282, 0x682, 0x182, 0x582, - 0x382, 0x782, 0x42, 0x442, 0x242, 0x642, 0x142, - 0x542, 0x342, 0x742, 0xc2, 0x4c2, 0x2c2, 0x6c2, - 0x1c2, 0x5c2, 0x3c2, 0x7c2, 0x22, 0x422, 0x222, - 0x622, 0x122, 0x522, 0x322, 0x722, 0xa2, 0x4a2, - 0x2a2, 0x6a2, 0x1a2, 0x5a2, 0x3a2, 0x7a2, 0x62, - 0x462, 0x262, 0x662, 0x162, 0x562, 0x362, 0x762, - 0xe2, 0x4e2, 0x2e2, 0x6e2, 0x1e2, 0x5e2, 0x3e2, - 0x7e2, 0x12, 0x412, 0x212, 0x612, 0x112, 0x512, - 0x312, 0x712, 0x92, 0x492, 0x292, 0x692, 0x192, - 0x592, 0x392, 0x792, 0x52, 0x452, 0x252, 0x652, - 0x152, 0x552, 0x352, 0x752, 0xd2, 0x4d2, 0x2d2, - 0x6d2, 0x1d2, 0x5d2, 0x3d2, 0x7d2, 0x32, 0x432, - 0x232, 0x632, 0x132, 0x532, 0x332, 0x732, 0xb2, - 0x4b2, 0x2b2, 0x6b2, 0x1b2, 0x5b2, 0x3b2, 0x7b2, - 0x72, 0x472, 0x272, 0x672, 0x172, 0x572, 0x372, - 0x772, 0xf2, 0x4f2, 0x2f2, 0x6f2, 0x1f2, 0x5f2, - 0x3f2, 0x7f2, 0xa, 0x40a, 0x20a, 0x60a, 0x10a, - 0x50a, 0x30a, 0x70a, 0x8a, 0x48a, 0x28a, 0x68a, - 0x18a, 0x58a, 0x38a, 0x78a, 0x4a, 0x44a, 0x24a, - 0x64a, 0x14a, 0x54a, 0x34a, 0x74a, 0xca, 0x4ca, - 0x2ca, 0x6ca, 0x1ca, 0x5ca, 0x3ca, 0x7ca, 0x2a, - 0x42a, 0x22a, 0x62a, 0x12a, 0x52a, 0x32a, 0x72a, - 0xaa, 0x4aa, 0x2aa, 0x6aa, 0x1aa, 0x5aa, 0x3aa, - 0x7aa, 0x6a, 0x46a, 0x26a, 0x66a, 0x16a, 0x56a, - 0x36a, 0x76a, 0xea, 0x4ea, 0x2ea, 0x6ea, 0x1ea, - 0x5ea, 0x3ea, 0x7ea, 0x1a, 0x41a, 0x21a, 0x61a, - 0x11a, 0x51a, 0x31a, 0x71a, 0x9a, 0x49a, 0x29a, - 0x69a, 0x19a, 0x59a, 0x39a, 0x79a, 0x5a, 0x45a, - 0x25a, 0x65a, 0x15a, 0x55a, 0x35a, 0x75a, 0xda, - 0x4da, 0x2da, 0x6da, 0x1da, 0x5da, 0x3da, 0x7da, - 0x3a, 0x43a, 0x23a, 0x63a, 0x13a, 0x53a, 0x33a, - 0x73a, 0xba, 0x4ba, 0x2ba, 0x6ba, 0x1ba, 0x5ba, - 0x3ba, 0x7ba, 0x7a, 0x47a, 0x27a, 0x67a, 0x17a, - 0x57a, 0x37a, 0x77a, 0xfa, 0x4fa, 0x2fa, 0x6fa, - 0x1fa, 0x5fa, 0x3fa, 0x7fa, 0x6, 0x406, 0x206, - 0x606, 0x106, 0x506, 0x306, 0x706, 0x86, 0x486, - 0x286, 0x686, 0x186, 0x586, 0x386, 0x786, 0x46, - 0x446, 0x246, 0x646, 0x146, 0x546, 0x346, 0x746, - 0xc6, 0x4c6, 0x2c6, 0x6c6, 0x1c6, 0x5c6, 0x3c6, - 0x7c6, 0x26, 0x426, 0x226, 0x626, 0x126, 0x526, - 0x326, 0x726, 0xa6, 0x4a6, 0x2a6, 0x6a6, 0x1a6, - 0x5a6, 0x3a6, 0x7a6, 0x66, 0x466, 0x266, 0x666, - 0x166, 0x566, 0x366, 0x766, 0xe6, 0x4e6, 0x2e6, - 0x6e6, 0x1e6, 0x5e6, 0x3e6, 0x7e6, 0x16, 0x416, - 0x216, 0x616, 0x116, 0x516, 0x316, 0x716, 0x96, - 0x496, 0x296, 0x696, 0x196, 0x596, 0x396, 0x796, - 0x56, 0x456, 0x256, 0x656, 0x156, 0x556, 0x356, - 0x756, 0xd6, 0x4d6, 0x2d6, 0x6d6, 0x1d6, 0x5d6, - 0x3d6, 0x7d6, 0x36, 0x436, 0x236, 0x636, 0x136, - 0x536, 0x336, 0x736, 0xb6, 0x4b6, 0x2b6, 0x6b6, - 0x1b6, 0x5b6, 0x3b6, 0x7b6, 0x76, 0x476, 0x276, - 0x676, 0x176, 0x576, 0x376, 0x776, 0xf6, 0x4f6, - 0x2f6, 0x6f6, 0x1f6, 0x5f6, 0x3f6, 0x7f6, 0xe, - 0x40e, 0x20e, 0x60e, 0x10e, 0x50e, 0x30e, 0x70e, - 0x8e, 0x48e, 0x28e, 0x68e, 0x18e, 0x58e, 0x38e, - 0x78e, 0x4e, 0x44e, 0x24e, 0x64e, 0x14e, 0x54e, - 0x34e, 0x74e, 0xce, 0x4ce, 0x2ce, 0x6ce, 0x1ce, - 0x5ce, 0x3ce, 0x7ce, 0x2e, 0x42e, 0x22e, 0x62e, - 0x12e, 0x52e, 0x32e, 0x72e, 0xae, 0x4ae, 0x2ae, - 0x6ae, 0x1ae, 0x5ae, 0x3ae, 0x7ae, 0x6e, 0x46e, - 0x26e, 0x66e, 0x16e, 0x56e, 0x36e, 0x76e, 0xee, - 0x4ee, 0x2ee, 0x6ee, 0x1ee, 0x5ee, 0x3ee, 0x7ee, - 0x1e, 0x41e, 0x21e, 0x61e, 0x11e, 0x51e, 0x31e, - 0x71e, 0x9e, 0x49e, 0x29e, 0x69e, 0x19e, 0x59e, - 0x39e, 0x79e, 0x5e, 0x45e, 0x25e, 0x65e, 0x15e, - 0x55e, 0x35e, 0x75e, 0xde, 0x4de, 0x2de, 0x6de, - 0x1de, 0x5de, 0x3de, 0x7de, 0x3e, 0x43e, 0x23e, - 0x63e, 0x13e, 0x53e, 0x33e, 0x73e, 0xbe, 0x4be, - 0x2be, 0x6be, 0x1be, 0x5be, 0x3be, 0x7be, 0x7e, - 0x47e, 0x27e, 0x67e, 0x17e, 0x57e, 0x37e, 0x77e, - 0xfe, 0x4fe, 0x2fe, 0x6fe, 0x1fe, 0x5fe, 0x3fe, - 0x7fe, 0x1 -}; - - -/* -* @brief Floating-point Twiddle factors Table Generation -*/ - - -/** -* \par -* Example code for Floating-point Twiddle factors Generation: -* \par -* 
for(i = 0; i< 3N/4; i++)    
-* {    
-*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);    
-*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);    
-* }
-* \par -* where N = 4096 and PI = 3.14159265358979 -* \par -* Cos and Sin values are in interleaved fashion -* -*/ -const float32_t twiddleCoef[6144] = { - 1.000000000000000000f, 0.000000000000000000f, 0.999998823451701880f, - 0.001533980186284766f, 0.999995293809576190f, 0.003067956762965976f, - 0.999989411081928400f, 0.004601926120448571f, 0.999981175282601110f, - 0.006135884649154475f, 0.999970586430974140f, 0.007669828739531097f, - 0.999957644551963900f, 0.009203754782059819f, 0.999942349676023910f, - 0.010737659167264491f, 0.999924701839144500f, 0.012271538285719925f, - 0.999904701082852900f, 0.013805388528060391f, 0.999882347454212560f, - 0.015339206284988100f, 0.999857641005823860f, 0.016872987947281710f, - 0.999830581795823400f, 0.018406729905804820f, 0.999801169887884260f, - 0.019940428551514441f, 0.999769405351215280f, 0.021474080275469508f, - 0.999735288260561680f, 0.023007681468839369f, 0.999698818696204250f, - 0.024541228522912288f, 0.999659996743959220f, 0.026074717829103901f, - 0.999618822495178640f, 0.027608145778965740f, 0.999575296046749220f, - 0.029141508764193722f, 0.999529417501093140f, 0.030674803176636626f, - 0.999481186966166950f, 0.032208025408304586f, 0.999430604555461730f, - 0.033741171851377580f, 0.999377670388002850f, 0.035274238898213947f, - 0.999322384588349540f, 0.036807222941358832f, 0.999264747286594420f, - 0.038340120373552694f, 0.999204758618363890f, 0.039872927587739811f, - 0.999142418724816910f, 0.041405640977076739f, 0.999077727752645360f, - 0.042938256934940820f, 0.999010685854073380f, 0.044470771854938668f, - 0.998941293186856870f, 0.046003182130914623f, 0.998869549914283560f, - 0.047535484156959303f, 0.998795456205172410f, 0.049067674327418015f, - 0.998719012233872940f, 0.050599749036899282f, 0.998640218180265270f, - 0.052131704680283324f, 0.998559074229759310f, 0.053663537652730520f, - 0.998475580573294770f, 0.055195244349689934f, 0.998389737407340160f, - 0.056726821166907748f, 0.998301544933892890f, 0.058258264500435752f, - 0.998211003360478190f, 0.059789570746639868f, 0.998118112900149180f, - 0.061320736302208578f, 0.998022873771486240f, 0.062851757564161406f, - 0.997925286198596000f, 0.064382630929857465f, 0.997825350411111640f, - 0.065913352797003805f, 0.997723066644191640f, 0.067443919563664051f, - 0.997618435138519550f, 0.068974327628266746f, 0.997511456140303450f, - 0.070504573389613856f, 0.997402129901275300f, 0.072034653246889332f, - 0.997290456678690210f, 0.073564563599667426f, 0.997176436735326190f, - 0.075094300847921305f, 0.997060070339482960f, 0.076623861392031492f, - 0.996941357764982160f, 0.078153241632794232f, 0.996820299291165670f, - 0.079682437971430126f, 0.996696895202896060f, 0.081211446809592441f, - 0.996571145790554840f, 0.082740264549375692f, 0.996443051350042630f, - 0.084268887593324071f, 0.996312612182778000f, 0.085797312344439894f, - 0.996179828595696980f, 0.087325535206192059f, 0.996044700901251970f, - 0.088853552582524600f, 0.995907229417411720f, 0.090381360877864983f, - 0.995767414467659820f, 0.091908956497132724f, 0.995625256380994310f, - 0.093436335845747787f, 0.995480755491926940f, 0.094963495329638992f, - 0.995333912140482280f, 0.096490431355252593f, 0.995184726672196930f, - 0.098017140329560604f, 0.995033199438118630f, 0.099543618660069319f, - 0.994879330794805620f, 0.101069862754827820f, 0.994723121104325700f, - 0.102595869022436280f, 0.994564570734255420f, 0.104121633872054590f, - 0.994403680057679100f, 0.105647153713410620f, 0.994240449453187900f, - 0.107172424956808840f, 0.994074879304879370f, 0.108697444013138720f, - 0.993906970002356060f, 0.110222207293883060f, 0.993736721940724600f, - 0.111746711211126590f, 0.993564135520595300f, 0.113270952177564350f, - 0.993389211148080650f, 0.114794926606510080f, 0.993211949234794500f, - 0.116318630911904750f, 0.993032350197851410f, 0.117842061508324980f, - 0.992850414459865100f, 0.119365214810991350f, 0.992666142448948020f, - 0.120888087235777080f, 0.992479534598709970f, 0.122410675199216200f, - 0.992290591348257370f, 0.123932975118512160f, 0.992099313142191800f, - 0.125454983411546230f, 0.991905700430609330f, 0.126976696496885870f, - 0.991709753669099530f, 0.128498110793793170f, 0.991511473318743900f, - 0.130019222722233350f, 0.991310859846115440f, 0.131540028702883120f, - 0.991107913723276890f, 0.133060525157139060f, 0.990902635427780010f, - 0.134580708507126170f, 0.990695025442664630f, 0.136100575175706200f, - 0.990485084256457090f, 0.137620121586486040f, 0.990272812363169110f, - 0.139139344163826200f, 0.990058210262297120f, 0.140658239332849210f, - 0.989841278458820530f, 0.142176803519448030f, 0.989622017463200890f, - 0.143695033150294470f, 0.989400427791380380f, 0.145212924652847460f, - 0.989176509964781010f, 0.146730474455361750f, 0.988950264510302990f, - 0.148247678986896030f, 0.988721691960323780f, 0.149764534677321510f, - 0.988490792852696590f, 0.151281037957330220f, 0.988257567730749460f, - 0.152797185258443440f, 0.988022017143283530f, 0.154312973013020100f, - 0.987784141644572180f, 0.155828397654265230f, 0.987543941794359230f, - 0.157343455616238250f, 0.987301418157858430f, 0.158858143333861450f, - 0.987056571305750970f, 0.160372457242928280f, 0.986809401814185530f, - 0.161886393780111830f, 0.986559910264775410f, 0.163399949382973230f, - 0.986308097244598670f, 0.164913120489969890f, 0.986053963346195440f, - 0.166425903540464100f, 0.985797509167567480f, 0.167938294974731170f, - 0.985538735312176060f, 0.169450291233967960f, 0.985277642388941220f, - 0.170961888760301220f, 0.985014231012239840f, 0.172473083996795950f, - 0.984748501801904210f, 0.173983873387463820f, 0.984480455383220930f, - 0.175494253377271430f, 0.984210092386929030f, 0.177004220412148750f, - 0.983937413449218920f, 0.178513770938997510f, 0.983662419211730250f, - 0.180022901405699510f, 0.983385110321551180f, 0.181531608261124970f, - 0.983105487431216290f, 0.183039887955140950f, 0.982823551198705240f, - 0.184547736938619620f, 0.982539302287441240f, 0.186055151663446630f, - 0.982252741366289370f, 0.187562128582529600f, 0.981963869109555240f, - 0.189068664149806190f, 0.981672686196983110f, 0.190574754820252740f, - 0.981379193313754560f, 0.192080397049892440f, 0.981083391150486710f, - 0.193585587295803610f, 0.980785280403230430f, 0.195090322016128250f, - 0.980484861773469380f, 0.196594597670080220f, 0.980182135968117430f, - 0.198098410717953560f, 0.979877103699517640f, 0.199601757621130970f, - 0.979569765685440520f, 0.201104634842091900f, 0.979260122649082020f, - 0.202607038844421130f, 0.978948175319062200f, 0.204108966092816870f, - 0.978633924429423210f, 0.205610413053099240f, 0.978317370719627650f, - 0.207111376192218560f, 0.977998514934557140f, 0.208611851978263490f, - 0.977677357824509930f, 0.210111836880469610f, 0.977353900145199960f, - 0.211611327369227550f, 0.977028142657754390f, 0.213110319916091360f, - 0.976700086128711840f, 0.214608810993786760f, 0.976369731330021140f, - 0.216106797076219520f, 0.976037079039039020f, 0.217604274638483640f, - 0.975702130038528570f, 0.219101240156869800f, 0.975364885116656980f, - 0.220597690108873510f, 0.975025345066994120f, 0.222093620973203510f, - 0.974683510688510670f, 0.223589029229789990f, 0.974339382785575860f, - 0.225083911359792830f, 0.973992962167955830f, 0.226578263845610000f, - 0.973644249650811980f, 0.228072083170885730f, 0.973293246054698250f, - 0.229565365820518870f, 0.972939952205560180f, 0.231058108280671110f, - 0.972584368934732210f, 0.232550307038775240f, 0.972226497078936270f, - 0.234041958583543430f, 0.971866337480279400f, 0.235533059404975490f, - 0.971503890986251780f, 0.237023605994367200f, 0.971139158449725090f, - 0.238513594844318420f, 0.970772140728950350f, 0.240003022448741500f, - 0.970402838687555500f, 0.241491885302869330f, 0.970031253194543970f, - 0.242980179903263870f, 0.969657385124292450f, 0.244467902747824150f, - 0.969281235356548530f, 0.245955050335794590f, 0.968902804776428870f, - 0.247441619167773270f, 0.968522094274417380f, 0.248927605745720150f, - 0.968139104746362440f, 0.250413006572965220f, 0.967753837093475510f, - 0.251897818154216970f, 0.967366292222328510f, 0.253382036995570160f, - 0.966976471044852070f, 0.254865659604514570f, 0.966584374478333120f, - 0.256348682489942910f, 0.966190003445412500f, 0.257831102162158990f, - 0.965793358874083680f, 0.259312915132886230f, 0.965394441697689400f, - 0.260794117915275510f, 0.964993252854920320f, 0.262274707023913590f, - 0.964589793289812760f, 0.263754678974831350f, 0.964184063951745830f, - 0.265234030285511790f, 0.963776065795439840f, 0.266712757474898370f, - 0.963365799780954050f, 0.268190857063403180f, 0.962953266873683880f, - 0.269668325572915090f, 0.962538468044359160f, 0.271145159526808010f, - 0.962121404269041580f, 0.272621355449948980f, 0.961702076529122540f, - 0.274096909868706380f, 0.961280485811320640f, 0.275571819310958140f, - 0.960856633107679660f, 0.277046080306099900f, 0.960430519415565790f, - 0.278519689385053060f, 0.960002145737665960f, 0.279992643080273220f, - 0.959571513081984520f, 0.281464937925757940f, 0.959138622461841890f, - 0.282936570457055390f, 0.958703474895871600f, 0.284407537211271880f, - 0.958266071408017670f, 0.285877834727080620f, 0.957826413027532910f, - 0.287347459544729510f, 0.957384500788975860f, 0.288816408206049480f, - 0.956940335732208820f, 0.290284677254462330f, 0.956493918902395100f, - 0.291752263234989260f, 0.956045251349996410f, 0.293219162694258630f, - 0.955594334130771110f, 0.294685372180514330f, 0.955141168305770780f, - 0.296150888243623790f, 0.954685754941338340f, 0.297615707435086200f, - 0.954228095109105670f, 0.299079826308040480f, 0.953768189885990330f, - 0.300543241417273450f, 0.953306040354193860f, 0.302005949319228080f, - 0.952841647601198720f, 0.303467946572011320f, 0.952375012719765880f, - 0.304929229735402370f, 0.951906136807932350f, 0.306389795370860920f, - 0.951435020969008340f, 0.307849640041534870f, 0.950961666311575080f, - 0.309308760312268730f, 0.950486073949481700f, 0.310767152749611470f, - 0.950008245001843000f, 0.312224813921824880f, 0.949528180593036670f, - 0.313681740398891520f, 0.949045881852700560f, 0.315137928752522440f, - 0.948561349915730270f, 0.316593375556165850f, 0.948074585922276230f, - 0.318048077385014950f, 0.947585591017741090f, 0.319502030816015690f, - 0.947094366352777220f, 0.320955232427875210f, 0.946600913083283530f, - 0.322407678801069850f, 0.946105232370403450f, 0.323859366517852850f, - 0.945607325380521280f, 0.325310292162262930f, 0.945107193285260610f, - 0.326760452320131730f, 0.944604837261480260f, 0.328209843579092500f, - 0.944100258491272660f, 0.329658462528587490f, 0.943593458161960390f, - 0.331106305759876430f, 0.943084437466093490f, 0.332553369866044220f, - 0.942573197601446870f, 0.333999651442009380f, 0.942059739771017310f, - 0.335445147084531600f, 0.941544065183020810f, 0.336889853392220050f, - 0.941026175050889260f, 0.338333766965541130f, 0.940506070593268300f, - 0.339776884406826850f, 0.939983753034014050f, 0.341219202320282360f, - 0.939459223602189920f, 0.342660717311994380f, 0.938932483532064600f, - 0.344101425989938810f, 0.938403534063108060f, 0.345541324963989090f, - 0.937872376439989890f, 0.346980410845923680f, 0.937339011912574960f, - 0.348418680249434560f, 0.936803441735921560f, 0.349856129790134920f, - 0.936265667170278260f, 0.351292756085567090f, 0.935725689481080370f, - 0.352728555755210730f, 0.935183509938947610f, 0.354163525420490340f, - 0.934639129819680780f, 0.355597661704783850f, 0.934092550404258980f, - 0.357030961233429980f, 0.933543772978836170f, 0.358463420633736540f, - 0.932992798834738960f, 0.359895036534988110f, 0.932439629268462360f, - 0.361325805568454280f, 0.931884265581668150f, 0.362755724367397230f, - 0.931326709081180430f, 0.364184789567079890f, 0.930766961078983710f, - 0.365612997804773850f, 0.930205022892219070f, 0.367040345719767180f, - 0.929640895843181330f, 0.368466829953372320f, 0.929074581259315860f, - 0.369892447148934100f, 0.928506080473215590f, 0.371317193951837540f, - 0.927935394822617890f, 0.372741067009515760f, 0.927362525650401110f, - 0.374164062971457930f, 0.926787474304581750f, 0.375586178489217220f, - 0.926210242138311380f, 0.377007410216418260f, 0.925630830509872720f, - 0.378427754808765560f, 0.925049240782677580f, 0.379847208924051160f, - 0.924465474325262600f, 0.381265769222162380f, 0.923879532511286740f, - 0.382683432365089780f, 0.923291416719527640f, 0.384100195016935040f, - 0.922701128333878630f, 0.385516053843918850f, 0.922108668743345180f, - 0.386931005514388580f, 0.921514039342042010f, 0.388345046698826250f, - 0.920917241529189520f, 0.389758174069856410f, 0.920318276709110590f, - 0.391170384302253870f, 0.919717146291227360f, 0.392581674072951470f, - 0.919113851690057770f, 0.393992040061048100f, 0.918508394325212250f, - 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-0.997402129901275300f, -0.070504573389614356f, -0.997511456140303450f, - -0.068974327628267079f, -0.997618435138519550f, -0.067443919563664231f, - -0.997723066644191640f, -0.065913352797003832f, -0.997825350411111640f, - -0.064382630929857312f, -0.997925286198596000f, -0.062851757564161989f, - -0.998022873771486130f, -0.061320736302208995f, -0.998118112900149180f, - -0.059789570746640132f, -0.998211003360478190f, -0.058258264500435857f, - -0.998301544933892780f, -0.056726821166907686f, -0.998389737407340160f, - -0.055195244349689712f, -0.998475580573294770f, -0.053663537652731026f, - -0.998559074229759310f, -0.052131704680283657f, -0.998640218180265160f, - -0.050599749036899455f, -0.998719012233872940f, -0.049067674327418029f, - -0.998795456205172410f, -0.047535484156959157f, -0.998869549914283560f, - -0.046003182130915206f, -0.998941293186856870f, -0.044470771854939084f, - -0.999010685854073270f, -0.042938256934941084f, -0.999077727752645360f, - -0.041405640977076837f, -0.999142418724816910f, -0.039872927587739748f, - -0.999204758618363890f, -0.038340120373552472f, -0.999264747286594420f, - -0.036807222941359331f, -0.999322384588349430f, -0.035274238898214294f, - -0.999377670388002850f, -0.033741171851377760f, -0.999430604555461730f, - -0.032208025408304600f, -0.999481186966166950f, -0.030674803176636484f, - -0.999529417501093140f, -0.029141508764194309f, -0.999575296046749220f, - -0.027608145778966163f, -0.999618822495178640f, -0.026074717829104161f, - -0.999659996743959220f, -0.024541228522912389f, -0.999698818696204250f, - -0.023007681468839310f, -0.999735288260561680f, -0.021474080275469286f, - -0.999769405351215280f, -0.019940428551514944f, -0.999801169887884260f, - -0.018406729905805164f, -0.999830581795823400f, -0.016872987947281894f, - -0.999857641005823860f, -0.015339206284988121f, -0.999882347454212560f, - -0.013805388528060250f, -0.999904701082852900f, -0.012271538285720512f, - -0.999924701839144500f, -0.010737659167264916f, -0.999942349676023910f, - -0.009203754782060083f, -0.999957644551963900f, -0.007669828739531199f, - -0.999970586430974140f, -0.006135884649154416f, -0.999981175282601110f, - -0.004601926120448350f, -0.999989411081928400f, -0.003067956762966483f, - -0.999995293809576190f, -0.001533980186285111f, -0.999998823451701880f, -}; - -/* -* @brief Q31 Twiddle factors Table -*/ - -/** -* \par -* Example code for Q31 Twiddle factors Generation:: -* \par -* 
for(i = 0; i< 3N/4; i++)    
-* {    
-*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);    
-*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);    
-* }
-* \par -* where N = 4096 and PI = 3.14159265358979 -* \par -* Cos and Sin values are interleaved fashion -* \par -* Convert Floating point to Q31(Fixed point 1.31): -* round(twiddleCoefQ31(i) * pow(2, 31)) -* -*/ - -const q31_t twiddleCoefQ31[6144] = { - 0x7fffffff, 0x0, 0x7ffff621, 0x3243f5, 0x7fffd886, 0x6487e3, 0x7fffa72c, - 0x96cbc1, - 0x7fff6216, 0xc90f88, 0x7fff0943, 0xfb5330, 0x7ffe9cb2, 0x12d96b1, - 0x7ffe1c65, 0x15fda03, - 0x7ffd885a, 0x1921d20, 0x7ffce093, 0x1c45ffe, 0x7ffc250f, 0x1f6a297, - 0x7ffb55ce, 0x228e4e2, - 0x7ffa72d1, 0x25b26d7, 0x7ff97c18, 0x28d6870, 0x7ff871a2, 0x2bfa9a4, - 0x7ff75370, 0x2f1ea6c, - 0x7ff62182, 0x3242abf, 0x7ff4dbd9, 0x3566a96, 0x7ff38274, 0x388a9ea, - 0x7ff21553, 0x3bae8b2, - 0x7ff09478, 0x3ed26e6, 0x7feeffe1, 0x41f6480, 0x7fed5791, 0x451a177, - 0x7feb9b85, 0x483ddc3, - 0x7fe9cbc0, 0x4b6195d, 0x7fe7e841, 0x4e8543e, 0x7fe5f108, 0x51a8e5c, - 0x7fe3e616, 0x54cc7b1, - 0x7fe1c76b, 0x57f0035, 0x7fdf9508, 0x5b137df, 0x7fdd4eec, 0x5e36ea9, - 0x7fdaf519, 0x615a48b, - 0x7fd8878e, 0x647d97c, 0x7fd6064c, 0x67a0d76, 0x7fd37153, 0x6ac406f, - 0x7fd0c8a3, 0x6de7262, - 0x7fce0c3e, 0x710a345, 0x7fcb3c23, 0x742d311, 0x7fc85854, 0x77501be, - 0x7fc560cf, 0x7a72f45, - 0x7fc25596, 0x7d95b9e, 0x7fbf36aa, 0x80b86c2, 0x7fbc040a, 0x83db0a7, - 0x7fb8bdb8, 0x86fd947, - 0x7fb563b3, 0x8a2009a, 0x7fb1f5fc, 0x8d42699, 0x7fae7495, 0x9064b3a, - 0x7faadf7c, 0x9386e78, - 0x7fa736b4, 0x96a9049, 0x7fa37a3c, 0x99cb0a7, 0x7f9faa15, 0x9cecf89, - 0x7f9bc640, 0xa00ece8, - 0x7f97cebd, 0xa3308bd, 0x7f93c38c, 0xa6522fe, 0x7f8fa4b0, 0xa973ba5, - 0x7f8b7227, 0xac952aa, - 0x7f872bf3, 0xafb6805, 0x7f82d214, 0xb2d7baf, 0x7f7e648c, 0xb5f8d9f, - 0x7f79e35a, 0xb919dcf, - 0x7f754e80, 0xbc3ac35, 0x7f70a5fe, 0xbf5b8cb, 0x7f6be9d4, 0xc27c389, - 0x7f671a05, 0xc59cc68, - 0x7f62368f, 0xc8bd35e, 0x7f5d3f75, 0xcbdd865, 0x7f5834b7, 0xcefdb76, - 0x7f531655, 0xd21dc87, - 0x7f4de451, 0xd53db92, 0x7f489eaa, 0xd85d88f, 0x7f434563, 0xdb7d376, - 0x7f3dd87c, 0xde9cc40, - 0x7f3857f6, 0xe1bc2e4, 0x7f32c3d1, 0xe4db75b, 0x7f2d1c0e, 0xe7fa99e, - 0x7f2760af, 0xeb199a4, - 0x7f2191b4, 0xee38766, 0x7f1baf1e, 0xf1572dc, 0x7f15b8ee, 0xf475bff, - 0x7f0faf25, 0xf7942c7, - 0x7f0991c4, 0xfab272b, 0x7f0360cb, 0xfdd0926, 0x7efd1c3c, 0x100ee8ad, - 0x7ef6c418, 0x1040c5bb, - 0x7ef05860, 0x1072a048, 0x7ee9d914, 0x10a4784b, 0x7ee34636, 0x10d64dbd, - 0x7edc9fc6, 0x11082096, - 0x7ed5e5c6, 0x1139f0cf, 0x7ecf1837, 0x116bbe60, 0x7ec8371a, 0x119d8941, - 0x7ec14270, 0x11cf516a, - 0x7eba3a39, 0x120116d5, 0x7eb31e78, 0x1232d979, 0x7eabef2c, 0x1264994e, - 0x7ea4ac58, 0x1296564d, - 0x7e9d55fc, 0x12c8106f, 0x7e95ec1a, 0x12f9c7aa, 0x7e8e6eb2, 0x132b7bf9, - 0x7e86ddc6, 0x135d2d53, - 0x7e7f3957, 0x138edbb1, 0x7e778166, 0x13c0870a, 0x7e6fb5f4, 0x13f22f58, - 0x7e67d703, 0x1423d492, - 0x7e5fe493, 0x145576b1, 0x7e57dea7, 0x148715ae, 0x7e4fc53e, 0x14b8b17f, - 0x7e47985b, 0x14ea4a1f, - 0x7e3f57ff, 0x151bdf86, 0x7e37042a, 0x154d71aa, 0x7e2e9cdf, 0x157f0086, - 0x7e26221f, 0x15b08c12, - 0x7e1d93ea, 0x15e21445, 0x7e14f242, 0x16139918, 0x7e0c3d29, 0x16451a83, - 0x7e0374a0, 0x1676987f, - 0x7dfa98a8, 0x16a81305, 0x7df1a942, 0x16d98a0c, 0x7de8a670, 0x170afd8d, - 0x7ddf9034, 0x173c6d80, - 0x7dd6668f, 0x176dd9de, 0x7dcd2981, 0x179f429f, 0x7dc3d90d, 0x17d0a7bc, - 0x7dba7534, 0x1802092c, - 0x7db0fdf8, 0x183366e9, 0x7da77359, 0x1864c0ea, 0x7d9dd55a, 0x18961728, - 0x7d9423fc, 0x18c7699b, - 0x7d8a5f40, 0x18f8b83c, 0x7d808728, 0x192a0304, 0x7d769bb5, 0x195b49ea, - 0x7d6c9ce9, 0x198c8ce7, - 0x7d628ac6, 0x19bdcbf3, 0x7d58654d, 0x19ef0707, 0x7d4e2c7f, 0x1a203e1b, - 0x7d43e05e, 0x1a517128, - 0x7d3980ec, 0x1a82a026, 0x7d2f0e2b, 0x1ab3cb0d, 0x7d24881b, 0x1ae4f1d6, - 0x7d19eebf, 0x1b161479, - 0x7d0f4218, 0x1b4732ef, 0x7d048228, 0x1b784d30, 0x7cf9aef0, 0x1ba96335, - 0x7ceec873, 0x1bda74f6, - 0x7ce3ceb2, 0x1c0b826a, 0x7cd8c1ae, 0x1c3c8b8c, 0x7ccda169, 0x1c6d9053, - 0x7cc26de5, 0x1c9e90b8, - 0x7cb72724, 0x1ccf8cb3, 0x7cabcd28, 0x1d00843d, 0x7ca05ff1, 0x1d31774d, - 0x7c94df83, 0x1d6265dd, - 0x7c894bde, 0x1d934fe5, 0x7c7da505, 0x1dc4355e, 0x7c71eaf9, 0x1df5163f, - 0x7c661dbc, 0x1e25f282, - 0x7c5a3d50, 0x1e56ca1e, 0x7c4e49b7, 0x1e879d0d, 0x7c4242f2, 0x1eb86b46, - 0x7c362904, 0x1ee934c3, - 0x7c29fbee, 0x1f19f97b, 0x7c1dbbb3, 0x1f4ab968, 0x7c116853, 0x1f7b7481, - 0x7c0501d2, 0x1fac2abf, - 0x7bf88830, 0x1fdcdc1b, 0x7bebfb70, 0x200d888d, 0x7bdf5b94, 0x203e300d, - 0x7bd2a89e, 0x206ed295, - 0x7bc5e290, 0x209f701c, 0x7bb9096b, 0x20d0089c, 0x7bac1d31, 0x21009c0c, - 0x7b9f1de6, 0x21312a65, - 0x7b920b89, 0x2161b3a0, 0x7b84e61f, 0x219237b5, 0x7b77ada8, 0x21c2b69c, - 0x7b6a6227, 0x21f3304f, - 0x7b5d039e, 0x2223a4c5, 0x7b4f920e, 0x225413f8, 0x7b420d7a, 0x22847de0, - 0x7b3475e5, 0x22b4e274, - 0x7b26cb4f, 0x22e541af, 0x7b190dbc, 0x23159b88, 0x7b0b3d2c, 0x2345eff8, - 0x7afd59a4, 0x23763ef7, - 0x7aef6323, 0x23a6887f, 0x7ae159ae, 0x23d6cc87, 0x7ad33d45, 0x24070b08, - 0x7ac50dec, 0x243743fa, - 0x7ab6cba4, 0x24677758, 0x7aa8766f, 0x2497a517, 0x7a9a0e50, 0x24c7cd33, - 0x7a8b9348, 0x24f7efa2, - 0x7a7d055b, 0x25280c5e, 0x7a6e648a, 0x2558235f, 0x7a5fb0d8, 0x2588349d, - 0x7a50ea47, 0x25b84012, - 0x7a4210d8, 0x25e845b6, 0x7a332490, 0x26184581, 0x7a24256f, 0x26483f6c, - 0x7a151378, 0x26783370, - 0x7a05eead, 0x26a82186, 0x79f6b711, 0x26d809a5, 0x79e76ca7, 0x2707ebc7, - 0x79d80f6f, 0x2737c7e3, - 0x79c89f6e, 0x27679df4, 0x79b91ca4, 0x27976df1, 0x79a98715, 0x27c737d3, - 0x7999dec4, 0x27f6fb92, - 0x798a23b1, 0x2826b928, 0x797a55e0, 0x2856708d, 0x796a7554, 0x288621b9, - 0x795a820e, 0x28b5cca5, - 0x794a7c12, 0x28e5714b, 0x793a6361, 0x29150fa1, 0x792a37fe, 0x2944a7a2, - 0x7919f9ec, 0x29743946, - 0x7909a92d, 0x29a3c485, 0x78f945c3, 0x29d34958, 0x78e8cfb2, 0x2a02c7b8, - 0x78d846fb, 0x2a323f9e, - 0x78c7aba2, 0x2a61b101, 0x78b6fda8, 0x2a911bdc, 0x78a63d11, 0x2ac08026, - 0x789569df, 0x2aefddd8, - 0x78848414, 0x2b1f34eb, 0x78738bb3, 0x2b4e8558, 0x786280bf, 0x2b7dcf17, - 0x7851633b, 0x2bad1221, - 0x78403329, 0x2bdc4e6f, 0x782ef08b, 0x2c0b83fa, 0x781d9b65, 0x2c3ab2b9, - 0x780c33b8, 0x2c69daa6, - 0x77fab989, 0x2c98fbba, 0x77e92cd9, 0x2cc815ee, 0x77d78daa, 0x2cf72939, - 0x77c5dc01, 0x2d263596, - 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0xb397c649, 0x994e783d, - 0xb3c0200c, 0x99307ee0, 0xb3e88592, 0x9912955f, 0xb410f6d3, 0x98f4bbbc, - 0xb43973ca, 0x98d6f1fe, - 0xb461fc70, 0x98b93828, 0xb48a90c0, 0x989b8e40, 0xb4b330b3, 0x987df449, - 0xb4dbdc42, 0x98606a49, - 0xb5049368, 0x9842f043, 0xb52d561e, 0x9825863d, 0xb556245e, 0x98082c3b, - 0xb57efe22, 0x97eae242, - 0xb5a7e362, 0x97cda855, 0xb5d0d41a, 0x97b07e7a, 0xb5f9d043, 0x979364b5, - 0xb622d7d6, 0x97765b0a, - 0xb64beacd, 0x9759617f, 0xb6750921, 0x973c7817, 0xb69e32cd, 0x971f9ed7, - 0xb6c767ca, 0x9702d5c3, - 0xb6f0a812, 0x96e61ce0, 0xb719f39e, 0x96c97432, 0xb7434a67, 0x96acdbbe, - 0xb76cac69, 0x96905388, - 0xb796199b, 0x9673db94, 0xb7bf91f8, 0x965773e7, 0xb7e9157a, 0x963b1c86, - 0xb812a41a, 0x961ed574, - 0xb83c3dd1, 0x96029eb6, 0xb865e299, 0x95e67850, 0xb88f926d, 0x95ca6247, - 0xb8b94d44, 0x95ae5c9f, - 0xb8e31319, 0x9592675c, 0xb90ce3e6, 0x95768283, 0xb936bfa4, 0x955aae17, - 0xb960a64c, 0x953eea1e, - 0xb98a97d8, 0x9523369c, 0xb9b49442, 0x95079394, 0xb9de9b83, 0x94ec010b, - 0xba08ad95, 0x94d07f05, - 0xba32ca71, 0x94b50d87, 0xba5cf210, 0x9499ac95, 0xba87246d, 0x947e5c33, - 0xbab16180, 0x94631c65, - 0xbadba943, 0x9447ed2f, 0xbb05fbb0, 0x942cce96, 0xbb3058c0, 0x9411c09e, - 0xbb5ac06d, 0x93f6c34a, - 0xbb8532b0, 0x93dbd6a0, 0xbbafaf82, 0x93c0faa3, 0xbbda36dd, 0x93a62f57, - 0xbc04c8ba, 0x938b74c1, - 0xbc2f6513, 0x9370cae4, 0xbc5a0be2, 0x935631c5, 0xbc84bd1f, 0x933ba968, - 0xbcaf78c4, 0x932131d1, - 0xbcda3ecb, 0x9306cb04, 0xbd050f2c, 0x92ec7505, 0xbd2fe9e2, 0x92d22fd9, - 0xbd5acee5, 0x92b7fb82, - 0xbd85be30, 0x929dd806, 0xbdb0b7bb, 0x9283c568, 0xbddbbb7f, 0x9269c3ac, - 0xbe06c977, 0x924fd2d7, - 0xbe31e19b, 0x9235f2ec, 0xbe5d03e6, 0x921c23ef, 0xbe88304f, 0x920265e4, - 0xbeb366d1, 0x91e8b8d0, - 0xbedea765, 0x91cf1cb6, 0xbf09f205, 0x91b5919a, 0xbf3546a8, 0x919c1781, - 0xbf60a54a, 0x9182ae6d, - 0xbf8c0de3, 0x91695663, 0xbfb7806c, 0x91500f67, 0xbfe2fcdf, 0x9136d97d, - 0xc00e8336, 0x911db4a9, - 0xc03a1368, 0x9104a0ee, 0xc065ad70, 0x90eb9e50, 0xc0915148, 0x90d2acd4, - 0xc0bcfee7, 0x90b9cc7d, - 0xc0e8b648, 0x90a0fd4e, 0xc1147764, 0x90883f4d, 0xc1404233, 0x906f927c, - 0xc16c16b0, 0x9056f6df, - 0xc197f4d4, 0x903e6c7b, 0xc1c3dc97, 0x9025f352, 0xc1efcdf3, 0x900d8b69, - 0xc21bc8e1, 0x8ff534c4, - 0xc247cd5a, 0x8fdcef66, 0xc273db58, 0x8fc4bb53, 0xc29ff2d4, 0x8fac988f, - 0xc2cc13c7, 0x8f94871d, - 0xc2f83e2a, 0x8f7c8701, 0xc32471f7, 0x8f649840, 0xc350af26, 0x8f4cbadb, - 0xc37cf5b0, 0x8f34eed8, - 0xc3a94590, 0x8f1d343a, 0xc3d59ebe, 0x8f058b04, 0xc4020133, 0x8eedf33b, - 0xc42e6ce8, 0x8ed66ce1, - 0xc45ae1d7, 0x8ebef7fb, 0xc4875ff9, 0x8ea7948c, 0xc4b3e746, 0x8e904298, - 0xc4e077b8, 0x8e790222, - 0xc50d1149, 0x8e61d32e, 0xc539b3f1, 0x8e4ab5bf, 0xc5665fa9, 0x8e33a9da, - 0xc593146a, 0x8e1caf80, - 0xc5bfd22e, 0x8e05c6b7, 0xc5ec98ee, 0x8deeef82, 0xc61968a2, 0x8dd829e4, - 0xc6464144, 0x8dc175e0, - 0xc67322ce, 0x8daad37b, 0xc6a00d37, 0x8d9442b8, 0xc6cd0079, 0x8d7dc399, - 0xc6f9fc8d, 0x8d675623, - 0xc727016d, 0x8d50fa59, 0xc7540f11, 0x8d3ab03f, 0xc7812572, 0x8d2477d8, - 0xc7ae4489, 0x8d0e5127, - 0xc7db6c50, 0x8cf83c30, 0xc8089cbf, 0x8ce238f6, 0xc835d5d0, 0x8ccc477d, - 0xc863177b, 0x8cb667c8, - 0xc89061ba, 0x8ca099da, 0xc8bdb485, 0x8c8addb7, 0xc8eb0fd6, 0x8c753362, - 0xc91873a5, 0x8c5f9ade, - 0xc945dfec, 0x8c4a142f, 0xc97354a4, 0x8c349f58, 0xc9a0d1c5, 0x8c1f3c5d, - 0xc9ce5748, 0x8c09eb40, - 0xc9fbe527, 0x8bf4ac05, 0xca297b5a, 0x8bdf7eb0, 0xca5719db, 0x8bca6343, - 0xca84c0a3, 0x8bb559c1, - 0xcab26fa9, 0x8ba0622f, 0xcae026e8, 0x8b8b7c8f, 0xcb0de658, 0x8b76a8e4, - 0xcb3badf3, 0x8b61e733, - 0xcb697db0, 0x8b4d377c, 0xcb97558a, 0x8b3899c6, 0xcbc53579, 0x8b240e11, - 0xcbf31d75, 0x8b0f9462, - 0xcc210d79, 0x8afb2cbb, 0xcc4f057c, 0x8ae6d720, 0xcc7d0578, 0x8ad29394, - 0xccab0d65, 0x8abe6219, - 0xccd91d3d, 0x8aaa42b4, 0xcd0734f9, 0x8a963567, 0xcd355491, 0x8a823a36, - 0xcd637bfe, 0x8a6e5123, - 0xcd91ab39, 0x8a5a7a31, 0xcdbfe23a, 0x8a46b564, 0xcdee20fc, 0x8a3302be, - 0xce1c6777, 0x8a1f6243, - 0xce4ab5a2, 0x8a0bd3f5, 0xce790b79, 0x89f857d8, 0xcea768f2, 0x89e4edef, - 0xced5ce08, 0x89d1963c, - 0xcf043ab3, 0x89be50c3, 0xcf32aeeb, 0x89ab1d87, 0xcf612aaa, 0x8997fc8a, - 0xcf8fade9, 0x8984edcf, - 0xcfbe389f, 0x8971f15a, 0xcfeccac7, 0x895f072e, 0xd01b6459, 0x894c2f4c, - 0xd04a054e, 0x893969b9, - 0xd078ad9e, 0x8926b677, 0xd0a75d42, 0x89141589, 0xd0d61434, 0x890186f2, - 0xd104d26b, 0x88ef0ab4, - 0xd13397e2, 0x88dca0d3, 0xd1626490, 0x88ca4951, 0xd191386e, 0x88b80432, - 0xd1c01375, 0x88a5d177, - 0xd1eef59e, 0x8893b125, 0xd21ddee2, 0x8881a33d, 0xd24ccf39, 0x886fa7c2, - 0xd27bc69c, 0x885dbeb8, - 0xd2aac504, 0x884be821, 0xd2d9ca6a, 0x883a23ff, 0xd308d6c7, 0x88287256, - 0xd337ea12, 0x8816d327, - 0xd3670446, 0x88054677, 0xd396255a, 0x87f3cc48, 0xd3c54d47, 0x87e2649b, - 0xd3f47c06, 0x87d10f75, - 0xd423b191, 0x87bfccd7, 0xd452eddf, 0x87ae9cc5, 0xd48230e9, 0x879d7f41, - 0xd4b17aa8, 0x878c744d, - 0xd4e0cb15, 0x877b7bec, 0xd5102228, 0x876a9621, 0xd53f7fda, 0x8759c2ef, - 0xd56ee424, 0x87490258, - 0xd59e4eff, 0x8738545e, 0xd5cdc062, 0x8727b905, 0xd5fd3848, 0x8717304e, - 0xd62cb6a8, 0x8706ba3d, - 0xd65c3b7b, 0x86f656d3, 0xd68bc6ba, 0x86e60614, 0xd6bb585e, 0x86d5c802, - 0xd6eaf05f, 0x86c59c9f, - 0xd71a8eb5, 0x86b583ee, 0xd74a335b, 0x86a57df2, 0xd779de47, 0x86958aac, - 0xd7a98f73, 0x8685aa20, - 0xd7d946d8, 0x8675dc4f, 0xd809046e, 0x8666213c, 0xd838c82d, 0x865678eb, - 0xd868920f, 0x8646e35c, - 0xd898620c, 0x86376092, 0xd8c8381d, 0x8627f091, 0xd8f81439, 0x86189359, - 0xd927f65b, 0x860948ef, - 0xd957de7a, 0x85fa1153, 0xd987cc90, 0x85eaec88, 0xd9b7c094, 0x85dbda91, - 0xd9e7ba7f, 0x85ccdb70, - 0xda17ba4a, 0x85bdef28, 0xda47bfee, 0x85af15b9, 0xda77cb63, 0x85a04f28, - 0xdaa7dca1, 0x85919b76, - 0xdad7f3a2, 0x8582faa5, 0xdb08105e, 0x85746cb8, 0xdb3832cd, 0x8565f1b0, - 0xdb685ae9, 0x85578991, - 0xdb9888a8, 0x8549345c, 0xdbc8bc06, 0x853af214, 0xdbf8f4f8, 0x852cc2bb, - 0xdc293379, 0x851ea652, - 0xdc597781, 0x85109cdd, 0xdc89c109, 0x8502a65c, 0xdcba1008, 0x84f4c2d4, - 0xdcea6478, 0x84e6f244, - 0xdd1abe51, 0x84d934b1, 0xdd4b1d8c, 0x84cb8a1b, 0xdd7b8220, 0x84bdf286, - 0xddabec08, 0x84b06df2, - 0xdddc5b3b, 0x84a2fc62, 0xde0ccfb1, 0x84959dd9, 0xde3d4964, 0x84885258, - 0xde6dc84b, 0x847b19e1, - 0xde9e4c60, 0x846df477, 0xdeced59b, 0x8460e21a, 0xdeff63f4, 0x8453e2cf, - 0xdf2ff764, 0x8446f695, - 0xdf608fe4, 0x843a1d70, 0xdf912d6b, 0x842d5762, 0xdfc1cff3, 0x8420a46c, - 0xdff27773, 0x84140490, - 0xe02323e5, 0x840777d0, 0xe053d541, 0x83fafe2e, 0xe0848b7f, 0x83ee97ad, - 0xe0b54698, 0x83e2444d, - 0xe0e60685, 0x83d60412, 0xe116cb3d, 0x83c9d6fc, 0xe14794ba, 0x83bdbd0e, - 0xe17862f3, 0x83b1b649, - 0xe1a935e2, 0x83a5c2b0, 0xe1da0d7e, 0x8399e244, 0xe20ae9c1, 0x838e1507, - 0xe23bcaa2, 0x83825afb, - 0xe26cb01b, 0x8376b422, 0xe29d9a23, 0x836b207d, 0xe2ce88b3, 0x835fa00f, - 0xe2ff7bc3, 0x835432d8, - 0xe330734d, 0x8348d8dc, 0xe3616f48, 0x833d921b, 0xe3926fad, 0x83325e97, - 0xe3c37474, 0x83273e52, - 0xe3f47d96, 0x831c314e, 0xe4258b0a, 0x8311378d, 0xe4569ccb, 0x83065110, - 0xe487b2d0, 0x82fb7dd8, - 0xe4b8cd11, 0x82f0bde8, 0xe4e9eb87, 0x82e61141, 0xe51b0e2a, 0x82db77e5, - 0xe54c34f3, 0x82d0f1d5, - 0xe57d5fda, 0x82c67f14, 0xe5ae8ed8, 0x82bc1fa2, 0xe5dfc1e5, 0x82b1d381, - 0xe610f8f9, 0x82a79ab3, - 0xe642340d, 0x829d753a, 0xe6737319, 0x82936317, 0xe6a4b616, 0x8289644b, - 0xe6d5fcfc, 0x827f78d8, - 0xe70747c4, 0x8275a0c0, 0xe7389665, 0x826bdc04, 0xe769e8d8, 0x82622aa6, - 0xe79b3f16, 0x82588ca7, - 0xe7cc9917, 0x824f0208, 0xe7fdf6d4, 0x82458acc, 0xe82f5844, 0x823c26f3, - 0xe860bd61, 0x8232d67f, - 0xe8922622, 0x82299971, 0xe8c39280, 0x82206fcc, 0xe8f50273, 0x82175990, - 0xe92675f4, 0x820e56be, - 0xe957ecfb, 0x82056758, 0xe9896781, 0x81fc8b60, 0xe9bae57d, 0x81f3c2d7, - 0xe9ec66e8, 0x81eb0dbe, - 0xea1debbb, 0x81e26c16, 0xea4f73ee, 0x81d9dde1, 0xea80ff7a, 0x81d16321, - 0xeab28e56, 0x81c8fbd6, - 0xeae4207a, 0x81c0a801, 0xeb15b5e1, 0x81b867a5, 0xeb474e81, 0x81b03ac2, - 0xeb78ea52, 0x81a82159, - 0xebaa894f, 0x81a01b6d, 0xebdc2b6e, 0x819828fd, 0xec0dd0a8, 0x81904a0c, - 0xec3f78f6, 0x81887e9a, - 0xec71244f, 0x8180c6a9, 0xeca2d2ad, 0x8179223a, 0xecd48407, 0x8171914e, - 0xed063856, 0x816a13e6, - 0xed37ef91, 0x8162aa04, 0xed69a9b3, 0x815b53a8, 0xed9b66b2, 0x815410d4, - 0xedcd2687, 0x814ce188, - 0xedfee92b, 0x8145c5c7, 0xee30ae96, 0x813ebd90, 0xee6276bf, 0x8137c8e6, - 0xee9441a0, 0x8130e7c9, - 0xeec60f31, 0x812a1a3a, 0xeef7df6a, 0x8123603a, 0xef29b243, 0x811cb9ca, - 0xef5b87b5, 0x811626ec, - 0xef8d5fb8, 0x810fa7a0, 0xefbf3a45, 0x81093be8, 0xeff11753, 0x8102e3c4, - 0xf022f6da, 0x80fc9f35, - 0xf054d8d5, 0x80f66e3c, 0xf086bd39, 0x80f050db, 0xf0b8a401, 0x80ea4712, - 0xf0ea8d24, 0x80e450e2, - 0xf11c789a, 0x80de6e4c, 0xf14e665c, 0x80d89f51, 0xf1805662, 0x80d2e3f2, - 0xf1b248a5, 0x80cd3c2f, - 0xf1e43d1c, 0x80c7a80a, 0xf21633c0, 0x80c22784, 0xf2482c8a, 0x80bcba9d, - 0xf27a2771, 0x80b76156, - 0xf2ac246e, 0x80b21baf, 0xf2de2379, 0x80ace9ab, 0xf310248a, 0x80a7cb49, - 0xf342279b, 0x80a2c08b, - 0xf3742ca2, 0x809dc971, 0xf3a63398, 0x8098e5fb, 0xf3d83c77, 0x8094162c, - 0xf40a4735, 0x808f5a02, - 0xf43c53cb, 0x808ab180, 0xf46e6231, 0x80861ca6, 0xf4a07261, 0x80819b74, - 0xf4d28451, 0x807d2dec, - 0xf50497fb, 0x8078d40d, 0xf536ad56, 0x80748dd9, 0xf568c45b, 0x80705b50, - 0xf59add02, 0x806c3c74, - 0xf5ccf743, 0x80683143, 0xf5ff1318, 0x806439c0, 0xf6313077, 0x806055eb, - 0xf6634f59, 0x805c85c4, - 0xf6956fb7, 0x8058c94c, 0xf6c79188, 0x80552084, 0xf6f9b4c6, 0x80518b6b, - 0xf72bd967, 0x804e0a04, - 0xf75dff66, 0x804a9c4d, 0xf79026b9, 0x80474248, 0xf7c24f59, 0x8043fbf6, - 0xf7f4793e, 0x8040c956, - 0xf826a462, 0x803daa6a, 0xf858d0bb, 0x803a9f31, 0xf88afe42, 0x8037a7ac, - 0xf8bd2cef, 0x8034c3dd, - 0xf8ef5cbb, 0x8031f3c2, 0xf9218d9e, 0x802f375d, 0xf953bf91, 0x802c8ead, - 0xf985f28a, 0x8029f9b4, - 0xf9b82684, 0x80277872, 0xf9ea5b75, 0x80250ae7, 0xfa1c9157, 0x8022b114, - 0xfa4ec821, 0x80206af8, - 0xfa80ffcb, 0x801e3895, 0xfab3384f, 0x801c19ea, 0xfae571a4, 0x801a0ef8, - 0xfb17abc2, 0x801817bf, - 0xfb49e6a3, 0x80163440, 0xfb7c223d, 0x8014647b, 0xfbae5e89, 0x8012a86f, - 0xfbe09b80, 0x8011001f, - 0xfc12d91a, 0x800f6b88, 0xfc45174e, 0x800deaad, 0xfc775616, 0x800c7d8c, - 0xfca9956a, 0x800b2427, - 0xfcdbd541, 0x8009de7e, 0xfd0e1594, 0x8008ac90, 0xfd40565c, 0x80078e5e, - 0xfd729790, 0x800683e8, - 0xfda4d929, 0x80058d2f, 0xfdd71b1e, 0x8004aa32, 0xfe095d69, 0x8003daf1, - 0xfe3ba002, 0x80031f6d, - 0xfe6de2e0, 0x800277a6, 0xfea025fd, 0x8001e39b, 0xfed2694f, 0x8001634e, - 0xff04acd0, 0x8000f6bd, - 0xff36f078, 0x80009dea, 0xff69343f, 0x800058d4, 0xff9b781d, 0x8000277a, - 0xffcdbc0b, 0x800009df, - -}; - - -/* -* @brief Q15 Twiddle factors Table -*/ - -/** -* \par -* Example code for Q15 Twiddle factors Generation:: -* \par -* 
for(i = 0; i< 3N/4; i++)    
-* {    
-*	twiddleCoefQ15[2*i]= cos(i * 2*PI/(float)N);    
-*	twiddleCoefQ15[2*i+1]= sin(i * 2*PI/(float)N);    
-* }
-* \par -* where N = 4096 and PI = 3.14159265358979 -* \par -* Cos and Sin values are interleaved fashion -* \par -* Convert Floating point to Q15(Fixed point 1.15): -* round(twiddleCoefQ15(i) * pow(2, 15)) -* -*/ - -const q15_t ALIGN4 twiddleCoefQ15[6144] = { - - 0x7fff, 0x0, 0x7fff, 0x32, 0x7fff, 0x65, 0x7fff, 0x97, - 0x7fff, 0xc9, 0x7fff, 0xfb, 0x7fff, 0x12e, 0x7ffe, 0x160, - 0x7ffe, 0x192, 0x7ffd, 0x1c4, 0x7ffc, 0x1f7, 0x7ffb, 0x229, - 0x7ffa, 0x25b, 0x7ff9, 0x28d, 0x7ff8, 0x2c0, 0x7ff7, 0x2f2, - 0x7ff6, 0x324, 0x7ff5, 0x356, 0x7ff4, 0x389, 0x7ff2, 0x3bb, - 0x7ff1, 0x3ed, 0x7fef, 0x41f, 0x7fed, 0x452, 0x7fec, 0x484, - 0x7fea, 0x4b6, 0x7fe8, 0x4e8, 0x7fe6, 0x51b, 0x7fe4, 0x54d, - 0x7fe2, 0x57f, 0x7fe0, 0x5b1, 0x7fdd, 0x5e3, 0x7fdb, 0x616, - 0x7fd9, 0x648, 0x7fd6, 0x67a, 0x7fd3, 0x6ac, 0x7fd1, 0x6de, - 0x7fce, 0x711, 0x7fcb, 0x743, 0x7fc8, 0x775, 0x7fc5, 0x7a7, - 0x7fc2, 0x7d9, 0x7fbf, 0x80c, 0x7fbc, 0x83e, 0x7fb9, 0x870, - 0x7fb5, 0x8a2, 0x7fb2, 0x8d4, 0x7fae, 0x906, 0x7fab, 0x938, - 0x7fa7, 0x96b, 0x7fa3, 0x99d, 0x7fa0, 0x9cf, 0x7f9c, 0xa01, - 0x7f98, 0xa33, 0x7f94, 0xa65, 0x7f90, 0xa97, 0x7f8b, 0xac9, - 0x7f87, 0xafb, 0x7f83, 0xb2d, 0x7f7e, 0xb60, 0x7f7a, 0xb92, - 0x7f75, 0xbc4, 0x7f71, 0xbf6, 0x7f6c, 0xc28, 0x7f67, 0xc5a, - 0x7f62, 0xc8c, 0x7f5d, 0xcbe, 0x7f58, 0xcf0, 0x7f53, 0xd22, - 0x7f4e, 0xd54, 0x7f49, 0xd86, 0x7f43, 0xdb8, 0x7f3e, 0xdea, - 0x7f38, 0xe1c, 0x7f33, 0xe4e, 0x7f2d, 0xe80, 0x7f27, 0xeb2, - 0x7f22, 0xee4, 0x7f1c, 0xf15, 0x7f16, 0xf47, 0x7f10, 0xf79, - 0x7f0a, 0xfab, 0x7f03, 0xfdd, 0x7efd, 0x100f, 0x7ef7, 0x1041, - 0x7ef0, 0x1073, 0x7eea, 0x10a4, 0x7ee3, 0x10d6, 0x7edd, 0x1108, - 0x7ed6, 0x113a, 0x7ecf, 0x116c, 0x7ec8, 0x119e, 0x7ec1, 0x11cf, - 0x7eba, 0x1201, 0x7eb3, 0x1233, 0x7eac, 0x1265, 0x7ea5, 0x1296, - 0x7e9d, 0x12c8, 0x7e96, 0x12fa, 0x7e8e, 0x132b, 0x7e87, 0x135d, - 0x7e7f, 0x138f, 0x7e78, 0x13c1, 0x7e70, 0x13f2, 0x7e68, 0x1424, - 0x7e60, 0x1455, 0x7e58, 0x1487, 0x7e50, 0x14b9, 0x7e48, 0x14ea, - 0x7e3f, 0x151c, 0x7e37, 0x154d, 0x7e2f, 0x157f, 0x7e26, 0x15b1, - 0x7e1e, 0x15e2, 0x7e15, 0x1614, 0x7e0c, 0x1645, 0x7e03, 0x1677, - 0x7dfb, 0x16a8, 0x7df2, 0x16da, 0x7de9, 0x170b, 0x7de0, 0x173c, - 0x7dd6, 0x176e, 0x7dcd, 0x179f, 0x7dc4, 0x17d1, 0x7dba, 0x1802, - 0x7db1, 0x1833, 0x7da7, 0x1865, 0x7d9e, 0x1896, 0x7d94, 0x18c7, - 0x7d8a, 0x18f9, 0x7d81, 0x192a, 0x7d77, 0x195b, 0x7d6d, 0x198d, - 0x7d63, 0x19be, 0x7d58, 0x19ef, 0x7d4e, 0x1a20, 0x7d44, 0x1a51, - 0x7d3a, 0x1a83, 0x7d2f, 0x1ab4, 0x7d25, 0x1ae5, 0x7d1a, 0x1b16, - 0x7d0f, 0x1b47, 0x7d05, 0x1b78, 0x7cfa, 0x1ba9, 0x7cef, 0x1bda, - 0x7ce4, 0x1c0c, 0x7cd9, 0x1c3d, 0x7cce, 0x1c6e, 0x7cc2, 0x1c9f, - 0x7cb7, 0x1cd0, 0x7cac, 0x1d01, 0x7ca0, 0x1d31, 0x7c95, 0x1d62, - 0x7c89, 0x1d93, 0x7c7e, 0x1dc4, 0x7c72, 0x1df5, 0x7c66, 0x1e26, - 0x7c5a, 0x1e57, 0x7c4e, 0x1e88, 0x7c42, 0x1eb8, 0x7c36, 0x1ee9, - 0x7c2a, 0x1f1a, 0x7c1e, 0x1f4b, 0x7c11, 0x1f7b, 0x7c05, 0x1fac, - 0x7bf9, 0x1fdd, 0x7bec, 0x200e, 0x7bdf, 0x203e, 0x7bd3, 0x206f, - 0x7bc6, 0x209f, 0x7bb9, 0x20d0, 0x7bac, 0x2101, 0x7b9f, 0x2131, - 0x7b92, 0x2162, 0x7b85, 0x2192, 0x7b78, 0x21c3, 0x7b6a, 0x21f3, - 0x7b5d, 0x2224, 0x7b50, 0x2254, 0x7b42, 0x2284, 0x7b34, 0x22b5, - 0x7b27, 0x22e5, 0x7b19, 0x2316, 0x7b0b, 0x2346, 0x7afd, 0x2376, - 0x7aef, 0x23a7, 0x7ae1, 0x23d7, 0x7ad3, 0x2407, 0x7ac5, 0x2437, - 0x7ab7, 0x2467, 0x7aa8, 0x2498, 0x7a9a, 0x24c8, 0x7a8c, 0x24f8, - 0x7a7d, 0x2528, 0x7a6e, 0x2558, 0x7a60, 0x2588, 0x7a51, 0x25b8, - 0x7a42, 0x25e8, 0x7a33, 0x2618, 0x7a24, 0x2648, 0x7a15, 0x2678, - 0x7a06, 0x26a8, 0x79f7, 0x26d8, 0x79e7, 0x2708, 0x79d8, 0x2738, - 0x79c9, 0x2768, 0x79b9, 0x2797, 0x79aa, 0x27c7, 0x799a, 0x27f7, - 0x798a, 0x2827, 0x797a, 0x2856, 0x796a, 0x2886, 0x795b, 0x28b6, - 0x794a, 0x28e5, 0x793a, 0x2915, 0x792a, 0x2945, 0x791a, 0x2974, - 0x790a, 0x29a4, 0x78f9, 0x29d3, 0x78e9, 0x2a03, 0x78d8, 0x2a32, - 0x78c8, 0x2a62, 0x78b7, 0x2a91, 0x78a6, 0x2ac1, 0x7895, 0x2af0, - 0x7885, 0x2b1f, 0x7874, 0x2b4f, 0x7863, 0x2b7e, 0x7851, 0x2bad, - 0x7840, 0x2bdc, 0x782f, 0x2c0c, 0x781e, 0x2c3b, 0x780c, 0x2c6a, - 0x77fb, 0x2c99, 0x77e9, 0x2cc8, 0x77d8, 0x2cf7, 0x77c6, 0x2d26, - 0x77b4, 0x2d55, 0x77a2, 0x2d84, 0x7790, 0x2db3, 0x777e, 0x2de2, - 0x776c, 0x2e11, 0x775a, 0x2e40, 0x7748, 0x2e6f, 0x7736, 0x2e9e, - 0x7723, 0x2ecc, 0x7711, 0x2efb, 0x76fe, 0x2f2a, 0x76ec, 0x2f59, - 0x76d9, 0x2f87, 0x76c7, 0x2fb6, 0x76b4, 0x2fe5, 0x76a1, 0x3013, - 0x768e, 0x3042, 0x767b, 0x3070, 0x7668, 0x309f, 0x7655, 0x30cd, - 0x7642, 0x30fc, 0x762e, 0x312a, 0x761b, 0x3159, 0x7608, 0x3187, - 0x75f4, 0x31b5, 0x75e1, 0x31e4, 0x75cd, 0x3212, 0x75b9, 0x3240, - 0x75a6, 0x326e, 0x7592, 0x329d, 0x757e, 0x32cb, 0x756a, 0x32f9, - 0x7556, 0x3327, 0x7542, 0x3355, 0x752d, 0x3383, 0x7519, 0x33b1, - 0x7505, 0x33df, 0x74f0, 0x340d, 0x74dc, 0x343b, 0x74c7, 0x3469, - 0x74b3, 0x3497, 0x749e, 0x34c4, 0x7489, 0x34f2, 0x7475, 0x3520, - 0x7460, 0x354e, 0x744b, 0x357b, 0x7436, 0x35a9, 0x7421, 0x35d7, - 0x740b, 0x3604, 0x73f6, 0x3632, 0x73e1, 0x365f, 0x73cb, 0x368d, - 0x73b6, 0x36ba, 0x73a0, 0x36e8, 0x738b, 0x3715, 0x7375, 0x3742, - 0x735f, 0x3770, 0x734a, 0x379d, 0x7334, 0x37ca, 0x731e, 0x37f7, - 0x7308, 0x3825, 0x72f2, 0x3852, 0x72dc, 0x387f, 0x72c5, 0x38ac, - 0x72af, 0x38d9, 0x7299, 0x3906, 0x7282, 0x3933, 0x726c, 0x3960, - 0x7255, 0x398d, 0x723f, 0x39ba, 0x7228, 0x39e7, 0x7211, 0x3a13, - 0x71fa, 0x3a40, 0x71e3, 0x3a6d, 0x71cc, 0x3a9a, 0x71b5, 0x3ac6, - 0x719e, 0x3af3, 0x7187, 0x3b20, 0x7170, 0x3b4c, 0x7158, 0x3b79, - 0x7141, 0x3ba5, 0x712a, 0x3bd2, 0x7112, 0x3bfe, 0x70fa, 0x3c2a, - 0x70e3, 0x3c57, 0x70cb, 0x3c83, 0x70b3, 0x3caf, 0x709b, 0x3cdc, - 0x7083, 0x3d08, 0x706b, 0x3d34, 0x7053, 0x3d60, 0x703b, 0x3d8c, - 0x7023, 0x3db8, 0x700b, 0x3de4, 0x6ff2, 0x3e10, 0x6fda, 0x3e3c, - 0x6fc2, 0x3e68, 0x6fa9, 0x3e94, 0x6f90, 0x3ec0, 0x6f78, 0x3eec, - 0x6f5f, 0x3f17, 0x6f46, 0x3f43, 0x6f2d, 0x3f6f, 0x6f14, 0x3f9a, - 0x6efb, 0x3fc6, 0x6ee2, 0x3ff1, 0x6ec9, 0x401d, 0x6eb0, 0x4048, - 0x6e97, 0x4074, 0x6e7d, 0x409f, 0x6e64, 0x40cb, 0x6e4a, 0x40f6, - 0x6e31, 0x4121, 0x6e17, 0x414d, 0x6dfe, 0x4178, 0x6de4, 0x41a3, - 0x6dca, 0x41ce, 0x6db0, 0x41f9, 0x6d96, 0x4224, 0x6d7c, 0x424f, - 0x6d62, 0x427a, 0x6d48, 0x42a5, 0x6d2e, 0x42d0, 0x6d14, 0x42fb, - 0x6cf9, 0x4326, 0x6cdf, 0x4351, 0x6cc4, 0x437b, 0x6caa, 0x43a6, - 0x6c8f, 0x43d1, 0x6c75, 0x43fb, 0x6c5a, 0x4426, 0x6c3f, 0x4450, - 0x6c24, 0x447b, 0x6c09, 0x44a5, 0x6bee, 0x44d0, 0x6bd3, 0x44fa, - 0x6bb8, 0x4524, 0x6b9d, 0x454f, 0x6b82, 0x4579, 0x6b66, 0x45a3, - 0x6b4b, 0x45cd, 0x6b30, 0x45f7, 0x6b14, 0x4621, 0x6af8, 0x464b, - 0x6add, 0x4675, 0x6ac1, 0x469f, 0x6aa5, 0x46c9, 0x6a89, 0x46f3, - 0x6a6e, 0x471d, 0x6a52, 0x4747, 0x6a36, 0x4770, 0x6a1a, 0x479a, - 0x69fd, 0x47c4, 0x69e1, 0x47ed, 0x69c5, 0x4817, 0x69a9, 0x4840, - 0x698c, 0x486a, 0x6970, 0x4893, 0x6953, 0x48bd, 0x6937, 0x48e6, - 0x691a, 0x490f, 0x68fd, 0x4939, 0x68e0, 0x4962, 0x68c4, 0x498b, - 0x68a7, 0x49b4, 0x688a, 0x49dd, 0x686d, 0x4a06, 0x6850, 0x4a2f, - 0x6832, 0x4a58, 0x6815, 0x4a81, 0x67f8, 0x4aaa, 0x67da, 0x4ad3, - 0x67bd, 0x4afb, 0x67a0, 0x4b24, 0x6782, 0x4b4d, 0x6764, 0x4b75, - 0x6747, 0x4b9e, 0x6729, 0x4bc7, 0x670b, 0x4bef, 0x66ed, 0x4c17, - 0x66d0, 0x4c40, 0x66b2, 0x4c68, 0x6693, 0x4c91, 0x6675, 0x4cb9, - 0x6657, 0x4ce1, 0x6639, 0x4d09, 0x661b, 0x4d31, 0x65fc, 0x4d59, - 0x65de, 0x4d81, 0x65c0, 0x4da9, 0x65a1, 0x4dd1, 0x6582, 0x4df9, - 0x6564, 0x4e21, 0x6545, 0x4e49, 0x6526, 0x4e71, 0x6507, 0x4e98, - 0x64e9, 0x4ec0, 0x64ca, 0x4ee8, 0x64ab, 0x4f0f, 0x648b, 0x4f37, - 0x646c, 0x4f5e, 0x644d, 0x4f85, 0x642e, 0x4fad, 0x640f, 0x4fd4, - 0x63ef, 0x4ffb, 0x63d0, 0x5023, 0x63b0, 0x504a, 0x6391, 0x5071, - 0x6371, 0x5098, 0x6351, 0x50bf, 0x6332, 0x50e6, 0x6312, 0x510d, - 0x62f2, 0x5134, 0x62d2, 0x515b, 0x62b2, 0x5181, 0x6292, 0x51a8, - 0x6272, 0x51cf, 0x6252, 0x51f5, 0x6232, 0x521c, 0x6211, 0x5243, - 0x61f1, 0x5269, 0x61d1, 0x5290, 0x61b0, 0x52b6, 0x6190, 0x52dc, - 0x616f, 0x5303, 0x614e, 0x5329, 0x612e, 0x534f, 0x610d, 0x5375, - 0x60ec, 0x539b, 0x60cb, 0x53c1, 0x60aa, 0x53e7, 0x6089, 0x540d, - 0x6068, 0x5433, 0x6047, 0x5459, 0x6026, 0x547f, 0x6005, 0x54a4, - 0x5fe4, 0x54ca, 0x5fc2, 0x54f0, 0x5fa1, 0x5515, 0x5f80, 0x553b, - 0x5f5e, 0x5560, 0x5f3c, 0x5586, 0x5f1b, 0x55ab, 0x5ef9, 0x55d0, - 0x5ed7, 0x55f6, 0x5eb6, 0x561b, 0x5e94, 0x5640, 0x5e72, 0x5665, - 0x5e50, 0x568a, 0x5e2e, 0x56af, 0x5e0c, 0x56d4, 0x5dea, 0x56f9, - 0x5dc8, 0x571e, 0x5da5, 0x5743, 0x5d83, 0x5767, 0x5d61, 0x578c, - 0x5d3e, 0x57b1, 0x5d1c, 0x57d5, 0x5cf9, 0x57fa, 0x5cd7, 0x581e, - 0x5cb4, 0x5843, 0x5c91, 0x5867, 0x5c6f, 0x588c, 0x5c4c, 0x58b0, - 0x5c29, 0x58d4, 0x5c06, 0x58f8, 0x5be3, 0x591c, 0x5bc0, 0x5940, - 0x5b9d, 0x5964, 0x5b7a, 0x5988, 0x5b57, 0x59ac, 0x5b34, 0x59d0, - 0x5b10, 0x59f4, 0x5aed, 0x5a18, 0x5ac9, 0x5a3b, 0x5aa6, 0x5a5f, - 0x5a82, 0x5a82, 0x5a5f, 0x5aa6, 0x5a3b, 0x5ac9, 0x5a18, 0x5aed, - 0x59f4, 0x5b10, 0x59d0, 0x5b34, 0x59ac, 0x5b57, 0x5988, 0x5b7a, - 0x5964, 0x5b9d, 0x5940, 0x5bc0, 0x591c, 0x5be3, 0x58f8, 0x5c06, - 0x58d4, 0x5c29, 0x58b0, 0x5c4c, 0x588c, 0x5c6f, 0x5867, 0x5c91, - 0x5843, 0x5cb4, 0x581e, 0x5cd7, 0x57fa, 0x5cf9, 0x57d5, 0x5d1c, - 0x57b1, 0x5d3e, 0x578c, 0x5d61, 0x5767, 0x5d83, 0x5743, 0x5da5, - 0x571e, 0x5dc8, 0x56f9, 0x5dea, 0x56d4, 0x5e0c, 0x56af, 0x5e2e, - 0x568a, 0x5e50, 0x5665, 0x5e72, 0x5640, 0x5e94, 0x561b, 0x5eb6, - 0x55f6, 0x5ed7, 0x55d0, 0x5ef9, 0x55ab, 0x5f1b, 0x5586, 0x5f3c, - 0x5560, 0x5f5e, 0x553b, 0x5f80, 0x5515, 0x5fa1, 0x54f0, 0x5fc2, - 0x54ca, 0x5fe4, 0x54a4, 0x6005, 0x547f, 0x6026, 0x5459, 0x6047, - 0x5433, 0x6068, 0x540d, 0x6089, 0x53e7, 0x60aa, 0x53c1, 0x60cb, - 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0xd958, 0x85fa, 0xd988, 0x85eb, 0xd9b8, 0x85dc, 0xd9e8, 0x85cd, - 0xda18, 0x85be, 0xda48, 0x85af, 0xda78, 0x85a0, 0xdaa8, 0x8592, - 0xdad8, 0x8583, 0xdb08, 0x8574, 0xdb38, 0x8566, 0xdb68, 0x8558, - 0xdb99, 0x8549, 0xdbc9, 0x853b, 0xdbf9, 0x852d, 0xdc29, 0x851f, - 0xdc59, 0x8511, 0xdc8a, 0x8503, 0xdcba, 0x84f5, 0xdcea, 0x84e7, - 0xdd1b, 0x84d9, 0xdd4b, 0x84cc, 0xdd7c, 0x84be, 0xddac, 0x84b0, - 0xdddc, 0x84a3, 0xde0d, 0x8496, 0xde3d, 0x8488, 0xde6e, 0x847b, - 0xde9e, 0x846e, 0xdecf, 0x8461, 0xdeff, 0x8454, 0xdf30, 0x8447, - 0xdf61, 0x843a, 0xdf91, 0x842d, 0xdfc2, 0x8421, 0xdff2, 0x8414, - 0xe023, 0x8407, 0xe054, 0x83fb, 0xe085, 0x83ef, 0xe0b5, 0x83e2, - 0xe0e6, 0x83d6, 0xe117, 0x83ca, 0xe148, 0x83be, 0xe178, 0x83b2, - 0xe1a9, 0x83a6, 0xe1da, 0x839a, 0xe20b, 0x838e, 0xe23c, 0x8382, - 0xe26d, 0x8377, 0xe29e, 0x836b, 0xe2cf, 0x8360, 0xe2ff, 0x8354, - 0xe330, 0x8349, 0xe361, 0x833e, 0xe392, 0x8332, 0xe3c3, 0x8327, - 0xe3f4, 0x831c, 0xe426, 0x8311, 0xe457, 0x8306, 0xe488, 0x82fb, - 0xe4b9, 0x82f1, 0xe4ea, 0x82e6, 0xe51b, 0x82db, 0xe54c, 0x82d1, - 0xe57d, 0x82c6, 0xe5af, 0x82bc, 0xe5e0, 0x82b2, 0xe611, 0x82a8, - 0xe642, 0x829d, 0xe673, 0x8293, 0xe6a5, 0x8289, 0xe6d6, 0x827f, - 0xe707, 0x8276, 0xe739, 0x826c, 0xe76a, 0x8262, 0xe79b, 0x8259, - 0xe7cd, 0x824f, 0xe7fe, 0x8246, 0xe82f, 0x823c, 0xe861, 0x8233, - 0xe892, 0x822a, 0xe8c4, 0x8220, 0xe8f5, 0x8217, 0xe926, 0x820e, - 0xe958, 0x8205, 0xe989, 0x81fd, 0xe9bb, 0x81f4, 0xe9ec, 0x81eb, - 0xea1e, 0x81e2, 0xea4f, 0x81da, 0xea81, 0x81d1, 0xeab3, 0x81c9, - 0xeae4, 0x81c1, 0xeb16, 0x81b8, 0xeb47, 0x81b0, 0xeb79, 0x81a8, - 0xebab, 0x81a0, 0xebdc, 0x8198, 0xec0e, 0x8190, 0xec3f, 0x8188, - 0xec71, 0x8181, 0xeca3, 0x8179, 0xecd5, 0x8172, 0xed06, 0x816a, - 0xed38, 0x8163, 0xed6a, 0x815b, 0xed9b, 0x8154, 0xedcd, 0x814d, - 0xedff, 0x8146, 0xee31, 0x813f, 0xee62, 0x8138, 0xee94, 0x8131, - 0xeec6, 0x812a, 0xeef8, 0x8123, 0xef2a, 0x811d, 0xef5c, 0x8116, - 0xef8d, 0x8110, 0xefbf, 0x8109, 0xeff1, 0x8103, 0xf023, 0x80fd, - 0xf055, 0x80f6, 0xf087, 0x80f0, 0xf0b9, 0x80ea, 0xf0eb, 0x80e4, - 0xf11c, 0x80de, 0xf14e, 0x80d9, 0xf180, 0x80d3, 0xf1b2, 0x80cd, - 0xf1e4, 0x80c8, 0xf216, 0x80c2, 0xf248, 0x80bd, 0xf27a, 0x80b7, - 0xf2ac, 0x80b2, 0xf2de, 0x80ad, 0xf310, 0x80a8, 0xf342, 0x80a3, - 0xf374, 0x809e, 0xf3a6, 0x8099, 0xf3d8, 0x8094, 0xf40a, 0x808f, - 0xf43c, 0x808b, 0xf46e, 0x8086, 0xf4a0, 0x8082, 0xf4d3, 0x807d, - 0xf505, 0x8079, 0xf537, 0x8075, 0xf569, 0x8070, 0xf59b, 0x806c, - 0xf5cd, 0x8068, 0xf5ff, 0x8064, 0xf631, 0x8060, 0xf663, 0x805d, - 0xf695, 0x8059, 0xf6c8, 0x8055, 0xf6fa, 0x8052, 0xf72c, 0x804e, - 0xf75e, 0x804b, 0xf790, 0x8047, 0xf7c2, 0x8044, 0xf7f4, 0x8041, - 0xf827, 0x803e, 0xf859, 0x803b, 0xf88b, 0x8038, 0xf8bd, 0x8035, - 0xf8ef, 0x8032, 0xf922, 0x802f, 0xf954, 0x802d, 0xf986, 0x802a, - 0xf9b8, 0x8027, 0xf9ea, 0x8025, 0xfa1d, 0x8023, 0xfa4f, 0x8020, - 0xfa81, 0x801e, 0xfab3, 0x801c, 0xfae5, 0x801a, 0xfb18, 0x8018, - 0xfb4a, 0x8016, 0xfb7c, 0x8014, 0xfbae, 0x8013, 0xfbe1, 0x8011, - 0xfc13, 0x800f, 0xfc45, 0x800e, 0xfc77, 0x800c, 0xfcaa, 0x800b, - 0xfcdc, 0x800a, 0xfd0e, 0x8009, 0xfd40, 0x8008, 0xfd73, 0x8007, - 0xfda5, 0x8006, 0xfdd7, 0x8005, 0xfe09, 0x8004, 0xfe3c, 0x8003, - 0xfe6e, 0x8002, 0xfea0, 0x8002, 0xfed2, 0x8001, 0xff05, 0x8001, - 0xff37, 0x8001, 0xff69, 0x8000, 0xff9b, 0x8000, 0xffce, 0x8000, -}; - -/** - * @} end of CFFT_CIFFT group - */ - -/* -* @brief Q15 table for reciprocal -*/ -const q15_t ALIGN4 armRecipTableQ15[64] = { - 0x7F03, 0x7D13, 0x7B31, 0x795E, 0x7798, 0x75E0, - 0x7434, 0x7294, 0x70FF, 0x6F76, 0x6DF6, 0x6C82, - 0x6B16, 0x69B5, 0x685C, 0x670C, 0x65C4, 0x6484, - 0x634C, 0x621C, 0x60F3, 0x5FD0, 0x5EB5, 0x5DA0, - 0x5C91, 0x5B88, 0x5A85, 0x5988, 0x5890, 0x579E, - 0x56B0, 0x55C8, 0x54E4, 0x5405, 0x532B, 0x5255, - 0x5183, 0x50B6, 0x4FEC, 0x4F26, 0x4E64, 0x4DA6, - 0x4CEC, 0x4C34, 0x4B81, 0x4AD0, 0x4A23, 0x4978, - 0x48D1, 0x482D, 0x478C, 0x46ED, 0x4651, 0x45B8, - 0x4521, 0x448D, 0x43FC, 0x436C, 0x42DF, 0x4255, - 0x41CC, 0x4146, 0x40C2, 0x4040 -}; - -/* -* @brief Q31 table for reciprocal -*/ -const q31_t armRecipTableQ31[64] = { - 0x7F03F03F, 0x7D137420, 0x7B31E739, 0x795E9F94, 0x7798FD29, 0x75E06928, - 0x7434554D, 0x72943B4B, 0x70FF9C40, 0x6F760031, 0x6DF6F593, 0x6C8210E3, - 0x6B16EC3A, 0x69B526F6, 0x685C655F, 0x670C505D, 0x65C4952D, 0x6484E519, - 0x634CF53E, 0x621C7E4F, 0x60F33C61, 0x5FD0EEB3, 0x5EB55785, 0x5DA03BEB, - 0x5C9163A1, 0x5B8898E6, 0x5A85A85A, 0x598860DF, 0x58909373, 0x579E1318, - 0x56B0B4B8, 0x55C84F0B, 0x54E4BA80, 0x5405D124, 0x532B6E8F, 0x52556FD0, - 0x5183B35A, 0x50B618F3, 0x4FEC81A2, 0x4F26CFA2, 0x4E64E64E, 0x4DA6AA1D, - 0x4CEC008B, 0x4C34D010, 0x4B810016, 0x4AD078EF, 0x4A2323C4, 0x4978EA96, - 0x48D1B827, 0x482D77FE, 0x478C1657, 0x46ED801D, 0x4651A2E5, 0x45B86CE2, - 0x4521CCE1, 0x448DB244, 0x43FC0CFA, 0x436CCD78, 0x42DFE4B4, 0x42554426, - 0x41CCDDB6, 0x4146A3C6, 0x40C28923, 0x40408102 -}; diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c deleted file mode 100644 index cdaf4c84e1..0000000000 --- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c +++ /dev/null @@ -1,174 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 15. February 2012 -* $Revision: V1.1.0 -* -* Project: CMSIS DSP Library -* Title: arm_cmplx_conj_f32.c -* -* Description: Floating-point complex conjugate. -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Version 1.1.0 2012/02/15 -* Updated with more optimizations, bug fixes and minor API changes. -* -* Version 1.0.10 2011/7/15 -* Big Endian support added and Merged M0 and M3/M4 Source code. -* -* Version 1.0.3 2010/11/29 -* Re-organized the CMSIS folders and updated documentation. -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* ---------------------------------------------------------------------------- */ -#include "arm_math.h" - -/** - * @ingroup groupCmplxMath - */ - -/** - * @defgroup cmplx_conj Complex Conjugate - * - * Conjugates the elements of a complex data vector. - * - * The pSrc points to the source data and - * pDst points to the where the result should be written. - * numSamples specifies the number of complex samples - * and the data in each array is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * Each array has a total of 2*numSamples values. - * The underlying algorithm is used: - * - * 
        
- * for(n=0; n        
- *        
- * There are separate functions for floating-point, Q15, and Q31 data types.        
- */
-
-/**        
- * @addtogroup cmplx_conj        
- * @{        
- */
-
-/**        
- * @brief  Floating-point complex conjugate.        
- * @param  *pSrc points to the input vector        
- * @param  *pDst points to the output vector        
- * @param  numSamples number of complex samples in each vector        
- * @return none.        
- */
-
-void arm_cmplx_conj_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t numSamples)
-{
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  float32_t inR1, inR2, inR3, inR4;
-  float32_t inI1, inI2, inI3, inI4;
-
-  /*loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
-    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
-    /* read real input samples */
-    inR1 = pSrc[0];
-    /* store real samples to destination */
-    pDst[0] = inR1;
-    inR2 = pSrc[2];
-    pDst[2] = inR2;
-    inR3 = pSrc[4];
-    pDst[4] = inR3;
-    inR4 = pSrc[6];
-    pDst[6] = inR4;
-
-    /* read imaginary input samples */
-    inI1 = pSrc[1];
-    inI2 = pSrc[3];
-
-    /* conjugate input */
-    inI1 = -inI1;
-
-    /* read imaginary input samples */
-    inI3 = pSrc[5];
-
-    /* conjugate input */
-    inI2 = -inI2;
-
-    /* read imaginary input samples */
-    inI4 = pSrc[7];
-
-    /* conjugate input */
-    inI3 = -inI3;
-
-    /* store imaginary samples to destination */
-    pDst[1] = inI1;
-    pDst[3] = inI2;
-
-    /* conjugate input */
-    inI4 = -inI4;
-
-    /* store imaginary samples to destination */
-    pDst[5] = inI3;
-
-    /* increment source pointer by 8 to process next sampels */
-    pSrc += 8u;
-
-    /* store imaginary sample to destination */
-    pDst[7] = inI4;
-
-    /* increment destination pointer by 8 to store next samples */
-    pDst += 8u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  blkCnt = numSamples;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* realOut + j (imagOut) = realIn + j (-1) imagIn */
-    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
-    *pDst++ = *pSrc++;
-    *pDst++ = -*pSrc++;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-}
-
-/**        
- * @} end of cmplx_conj group        
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c
deleted file mode 100644
index 92905fdf49..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_cmplx_conj_q15.c    
-*    
-* Description:	Q15 complex conjugate.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupCmplxMath    
- */
-
-/**    
- * @addtogroup cmplx_conj    
- * @{    
- */
-
-/**    
- * @brief  Q15 complex conjugate.    
- * @param  *pSrc points to the input vector    
- * @param  *pDst points to the output vector    
- * @param  numSamples number of complex samples in each vector    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function uses saturating arithmetic.    
- * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF.    
- */
-
-void arm_cmplx_conj_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t numSamples)
-{
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  uint32_t blkCnt;                               /* loop counter */
-  q31_t in1, in2, in3, in4;
-  q31_t zero = 0;
-
-  /*loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
-    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
-    in1 = *__SIMD32(pSrc)++;
-    in2 = *__SIMD32(pSrc)++;
-    in3 = *__SIMD32(pSrc)++;
-    in4 = *__SIMD32(pSrc)++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    in1 = __QASX(zero, in1);
-    in2 = __QASX(zero, in2);
-    in3 = __QASX(zero, in3);
-    in4 = __QASX(zero, in4);
-
-#else
-
-    in1 = __QSAX(zero, in1);
-    in2 = __QSAX(zero, in2);
-    in3 = __QSAX(zero, in3);
-    in4 = __QSAX(zero, in4);
-
-#endif //       #ifndef ARM_MATH_BIG_ENDIAN
-
-    in1 = ((uint32_t) in1 >> 16) | ((uint32_t) in1 << 16);
-    in2 = ((uint32_t) in2 >> 16) | ((uint32_t) in2 << 16);
-    in3 = ((uint32_t) in3 >> 16) | ((uint32_t) in3 << 16);
-    in4 = ((uint32_t) in4 >> 16) | ((uint32_t) in4 << 16);
-
-    *__SIMD32(pDst)++ = in1;
-    *__SIMD32(pDst)++ = in2;
-    *__SIMD32(pDst)++ = in3;
-    *__SIMD32(pDst)++ = in4;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
-    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
-    *pDst++ = *pSrc++;
-    *pDst++ = __SSAT(-*pSrc++, 16);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-#else
-
-  q15_t in;
-
-  /* Run the below code for Cortex-M0 */
-
-  while(numSamples > 0u)
-  {
-    /* realOut + j (imagOut) = realIn+ j (-1) imagIn */
-    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
-    *pDst++ = *pSrc++;
-    in = *pSrc++;
-    *pDst++ = (in == (q15_t) 0x8000) ? 0x7fff : -in;
-
-    /* Decrement the loop counter */
-    numSamples--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
- * @} end of cmplx_conj group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c
deleted file mode 100644
index 5f874aa690..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_cmplx_conj_q31.c    
-*    
-* Description:	Q31 complex conjugate.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-#include "arm_math.h"
-
-/**        
- * @ingroup groupCmplxMath        
- */
-
-/**        
- * @addtogroup cmplx_conj        
- * @{        
- */
-
-/**        
- * @brief  Q31 complex conjugate.        
- * @param  *pSrc points to the input vector        
- * @param  *pDst points to the output vector        
- * @param  numSamples number of complex samples in each vector        
- * @return none.        
- *        
- * Scaling and Overflow Behavior:        
- * \par        
- * The function uses saturating arithmetic.        
- * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF.        
- */
-
-void arm_cmplx_conj_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t numSamples)
-{
-  uint32_t blkCnt;                               /* loop counter */
-  q31_t in;                                      /* Input value */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  q31_t inR1, inR2, inR3, inR4;                  /* Temporary real variables */
-  q31_t inI1, inI2, inI3, inI4;                  /* Temporary imaginary variables */
-
-  /*loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
-    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
-    /* Saturated to 0x7fffffff if the input is -1(0x80000000) */
-    /* read real input sample */
-    inR1 = pSrc[0];
-    /* store real input sample */
-    pDst[0] = inR1;
-
-    /* read imaginary input sample */
-    inI1 = pSrc[1];
-
-    /* read real input sample */
-    inR2 = pSrc[2];
-    /* store real input sample */
-    pDst[2] = inR2;
-
-    /* read imaginary input sample */
-    inI2 = pSrc[3];
-
-    /* negate imaginary input sample */
-    inI1 = __QSUB(0, inI1);
-
-    /* read real input sample */
-    inR3 = pSrc[4];
-    /* store real input sample */
-    pDst[4] = inR3;
-
-    /* read imaginary input sample */
-    inI3 = pSrc[5];
-
-    /* negate imaginary input sample */
-    inI2 = __QSUB(0, inI2);
-
-    /* read real input sample */
-    inR4 = pSrc[6];
-    /* store real input sample */
-    pDst[6] = inR4;
-
-    /* negate imaginary input sample */
-    inI3 = __QSUB(0, inI3);
-
-    /* store imaginary input sample */
-    inI4 = pSrc[7];
-
-    /* store imaginary input samples */
-    pDst[1] = inI1;
-
-    /* negate imaginary input sample */
-    inI4 = __QSUB(0, inI4);
-
-    /* store imaginary input samples */
-    pDst[3] = inI2;
-
-    /* increment source pointer by 8 to proecess next samples */
-    pSrc += 8u;
-
-    /* store imaginary input samples */
-    pDst[5] = inI3;
-    pDst[7] = inI4;
-
-    /* increment destination pointer by 8 to process next samples */
-    pDst += 8u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  blkCnt = numSamples;
-
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
-    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
-    /* Saturated to 0x7fffffff if the input is -1(0x80000000) */
-    *pDst++ = *pSrc++;
-    in = *pSrc++;
-    *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-}
-
-/**        
- * @} end of cmplx_conj group        
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
deleted file mode 100644
index 200b309aae..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_cmplx_dot_prod_f32.c    
-*    
-* Description:	Floating-point complex dot product    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupCmplxMath    
- */
-
-/**    
- * @defgroup cmplx_dot_prod Complex Dot Product    
- *    
- * Computes the dot product of two complex vectors.    
- * The vectors are multiplied element-by-element and then summed.    
- *   
- * The pSrcA points to the first complex input vector and    
- * pSrcB points to the second complex input vector.    
- * numSamples specifies the number of complex samples    
- * and the data in each array is stored in an interleaved fashion    
- * (real, imag, real, imag, ...).    
- * Each array has a total of 2*numSamples values.    
- *    
- * The underlying algorithm is used:    
- * 
    
- * realResult=0;    
- * imagResult=0;    
- * for(n=0; n    
- *    
- * There are separate functions for floating-point, Q15, and Q31 data types.    
- */
-
-/**    
- * @addtogroup cmplx_dot_prod    
- * @{    
- */
-
-/**    
- * @brief  Floating-point complex dot product    
- * @param  *pSrcA points to the first input vector    
- * @param  *pSrcB points to the second input vector    
- * @param  numSamples number of complex samples in each vector    
- * @param  *realResult real part of the result returned here    
- * @param  *imagResult imaginary part of the result returned here    
- * @return none.    
- */
-
-void arm_cmplx_dot_prod_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  uint32_t numSamples,
-  float32_t * realResult,
-  float32_t * imagResult)
-{
-  float32_t real_sum = 0.0f, imag_sum = 0.0f;    /* Temporary result storage */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  uint32_t blkCnt;                               /* loop counter */
-
-  /*loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
-    real_sum += (*pSrcA++) * (*pSrcB++);
-    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
-    imag_sum += (*pSrcA++) * (*pSrcB++);
-
-    real_sum += (*pSrcA++) * (*pSrcB++);
-    imag_sum += (*pSrcA++) * (*pSrcB++);
-
-    real_sum += (*pSrcA++) * (*pSrcB++);
-    imag_sum += (*pSrcA++) * (*pSrcB++);
-
-    real_sum += (*pSrcA++) * (*pSrcB++);
-    imag_sum += (*pSrcA++) * (*pSrcB++);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
-    real_sum += (*pSrcA++) * (*pSrcB++);
-    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
-    imag_sum += (*pSrcA++) * (*pSrcB++);
-
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  while(numSamples > 0u)
-  {
-    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
-    real_sum += (*pSrcA++) * (*pSrcB++);
-    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
-    imag_sum += (*pSrcA++) * (*pSrcB++);
-
-
-    /* Decrement the loop counter */
-    numSamples--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  /* Store the real and imaginary results in the destination buffers */
-  *realResult = real_sum;
-  *imagResult = imag_sum;
-}
-
-/**    
- * @} end of cmplx_dot_prod group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
deleted file mode 100644
index db7fbae527..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_cmplx_dot_prod_q15.c    
-*    
-* Description:	Processing function for the Q15 Complex Dot product    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupCmplxMath    
- */
-
-/**    
- * @addtogroup cmplx_dot_prod    
- * @{    
- */
-
-/**    
- * @brief  Q15 complex dot product    
- * @param  *pSrcA points to the first input vector    
- * @param  *pSrcB points to the second input vector    
- * @param  numSamples number of complex samples in each vector    
- * @param  *realResult real part of the result returned here    
- * @param  *imagResult imaginary part of the result returned here    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using an internal 64-bit accumulator.    
- * The intermediate 1.15 by 1.15 multiplications are performed with full precision and yield a 2.30 result.    
- * These are accumulated in a 64-bit accumulator with 34.30 precision.    
- * As a final step, the accumulators are converted to 8.24 format.    
- * The return results realResult and imagResult are in 8.24 format.    
- */
-
-void arm_cmplx_dot_prod_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  uint32_t numSamples,
-  q31_t * realResult,
-  q31_t * imagResult)
-{
-  q63_t real_sum = 0, imag_sum = 0;              /* Temporary result storage */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  uint32_t blkCnt;                               /* loop counter */
-
-
-  /*loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
-    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
-
-    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
-    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
-
-    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
-    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
-
-    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
-    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
-
-    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
-    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
-    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
-    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
-    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  while(numSamples > 0u)
-  {
-    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
-    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
-    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
-    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
-
-    /* Decrement the loop counter */
-    numSamples--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  /* Store the real and imaginary results in 8.24 format  */
-  /* Convert real data in 34.30 to 8.24 by 6 right shifts */
-  *realResult = (q31_t) (real_sum) >> 6;
-  /* Convert imaginary data in 34.30 to 8.24 by 6 right shifts */
-  *imagResult = (q31_t) (imag_sum) >> 6;
-}
-
-/**    
- * @} end of cmplx_dot_prod group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
deleted file mode 100644
index 1acc49dc2c..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_cmplx_dot_prod_q31.c    
-*    
-* Description:	Q31 complex dot product    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupCmplxMath    
- */
-
-/**    
- * @addtogroup cmplx_dot_prod    
- * @{    
- */
-
-/**    
- * @brief  Q31 complex dot product    
- * @param  *pSrcA points to the first input vector    
- * @param  *pSrcB points to the second input vector    
- * @param  numSamples number of complex samples in each vector    
- * @param  *realResult real part of the result returned here    
- * @param  *imagResult imaginary part of the result returned here    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using an internal 64-bit accumulator.    
- * The intermediate 1.31 by 1.31 multiplications are performed with 64-bit precision and then shifted to 16.48 format.    
- * The internal real and imaginary accumulators are in 16.48 format and provide 15 guard bits.    
- * Additions are nonsaturating and no overflow will occur as long as numSamples is less than 32768.    
- * The return results realResult and imagResult are in 16.48 format.    
- * Input down scaling is not required.    
- */
-
-void arm_cmplx_dot_prod_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  uint32_t numSamples,
-  q63_t * realResult,
-  q63_t * imagResult)
-{
-  q63_t real_sum = 0, imag_sum = 0;              /* Temporary result storage */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  uint32_t blkCnt;                               /* loop counter */
-
-
-  /*loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
-    /* Convert real data in 2.62 to 16.48 by 14 right shifts */
-    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
-    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
-    /* Convert imag data in 2.62 to 16.48 by 14 right shifts */
-    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
-
-    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
-    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
-
-    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
-    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
-
-    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
-    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
-
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the numSamples  is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
-    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
-    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
-    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  while(numSamples > 0u)
-  {
-    /* outReal = realA[0]* realB[0] + realA[2]* realB[2] + realA[4]* realB[4] + .....+ realA[numSamples-2]* realB[numSamples-2] */
-    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
-    /* outImag = imagA[1]* imagB[1] + imagA[3]* imagB[3] + imagA[5]* imagB[5] + .....+ imagA[numSamples-1]* imagB[numSamples-1] */
-    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
-
-    /* Decrement the loop counter */
-    numSamples--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  /* Store the real and imaginary results in 16.48 format  */
-  *realResult = real_sum;
-  *imagResult = imag_sum;
-}
-
-/**    
- * @} end of cmplx_dot_prod group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c
deleted file mode 100644
index 043e002a84..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_cmplx_mag_f32.c    
-*    
-* Description:	Floating-point complex magnitude.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupCmplxMath    
- */
-
-/**    
- * @defgroup cmplx_mag Complex Magnitude    
- *    
- * Computes the magnitude of the elements of a complex data vector.    
- *   
- * The pSrc points to the source data and    
- * pDst points to the where the result should be written.    
- * numSamples specifies the number of complex samples    
- * in the input array and the data is stored in an interleaved fashion    
- * (real, imag, real, imag, ...).    
- * The input array has a total of 2*numSamples values;    
- * the output array has a total of numSamples values.    
- * The underlying algorithm is used:    
- *    
- * 
    
- * for(n=0; n    
- *    
- * There are separate functions for floating-point, Q15, and Q31 data types.    
- */
-
-/**    
- * @addtogroup cmplx_mag    
- * @{    
- */
-/**    
- * @brief Floating-point complex magnitude.    
- * @param[in]       *pSrc points to complex input buffer    
- * @param[out]      *pDst points to real output buffer    
- * @param[in]       numSamples number of complex samples in the input vector    
- * @return none.    
- *    
- */
-
-
-void arm_cmplx_mag_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t numSamples)
-{
-  float32_t realIn, imagIn;                      /* Temporary variables to hold input values */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  uint32_t blkCnt;                               /* loop counter */
-
-  /*loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-
-    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
-    realIn = *pSrc++;
-    imagIn = *pSrc++;
-    /* store the result in the destination buffer. */
-    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
-
-    realIn = *pSrc++;
-    imagIn = *pSrc++;
-    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
-
-    realIn = *pSrc++;
-    imagIn = *pSrc++;
-    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
-
-    realIn = *pSrc++;
-    imagIn = *pSrc++;
-    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
-
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
-    realIn = *pSrc++;
-    imagIn = *pSrc++;
-    /* store the result in the destination buffer. */
-    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  while(numSamples > 0u)
-  {
-    /* out = sqrt((real * real) + (imag * imag)) */
-    realIn = *pSrc++;
-    imagIn = *pSrc++;
-    /* store the result in the destination buffer. */
-    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
-
-    /* Decrement the loop counter */
-    numSamples--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
- * @} end of cmplx_mag group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c
deleted file mode 100644
index 13b862b5a2..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_cmplx_mag_q15.c    
-*    
-* Description:	Q15 complex magnitude.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupCmplxMath    
- */
-
-/**    
- * @addtogroup cmplx_mag    
- * @{    
- */
-
-
-/**    
- * @brief  Q15 complex magnitude    
- * @param  *pSrc points to the complex input vector    
- * @param  *pDst points to the real output vector    
- * @param  numSamples number of complex samples in the input vector    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function implements 1.15 by 1.15 multiplications and finally output is converted into 2.14 format.    
- */
-
-void arm_cmplx_mag_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t numSamples)
-{
-  q31_t acc0, acc1;                              /* Accumulators */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  uint32_t blkCnt;                               /* loop counter */
-  q31_t in1, in2, in3, in4;
-  q31_t acc2, acc3;
-
-
-  /*loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-
-    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
-    in1 = *__SIMD32(pSrc)++;
-    in2 = *__SIMD32(pSrc)++;
-    in3 = *__SIMD32(pSrc)++;
-    in4 = *__SIMD32(pSrc)++;
-
-    acc0 = __SMUAD(in1, in1);
-    acc1 = __SMUAD(in2, in2);
-    acc2 = __SMUAD(in3, in3);
-    acc3 = __SMUAD(in4, in4);
-
-    /* store the result in 2.14 format in the destination buffer. */
-    arm_sqrt_q15((q15_t) ((acc0) >> 17), pDst++);
-    arm_sqrt_q15((q15_t) ((acc1) >> 17), pDst++);
-    arm_sqrt_q15((q15_t) ((acc2) >> 17), pDst++);
-    arm_sqrt_q15((q15_t) ((acc3) >> 17), pDst++);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
-    in1 = *__SIMD32(pSrc)++;
-    acc0 = __SMUAD(in1, in1);
-
-    /* store the result in 2.14 format in the destination buffer. */
-    arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  q15_t real, imag;                              /* Temporary variables to hold input values */
-
-  while(numSamples > 0u)
-  {
-    /* out = sqrt(real * real + imag * imag) */
-    real = *pSrc++;
-    imag = *pSrc++;
-
-    acc0 = (real * real);
-    acc1 = (imag * imag);
-
-    /* store the result in 2.14 format in the destination buffer. */
-    arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
-
-    /* Decrement the loop counter */
-    numSamples--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
- * @} end of cmplx_mag group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c
deleted file mode 100644
index bf1af75e6b..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_cmplx_mag_q31.c    
-*    
-* Description:	Q31 complex magnitude    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**        
- * @ingroup groupCmplxMath        
- */
-
-/**        
- * @addtogroup cmplx_mag        
- * @{        
- */
-
-/**        
- * @brief  Q31 complex magnitude        
- * @param  *pSrc points to the complex input vector        
- * @param  *pDst points to the real output vector        
- * @param  numSamples number of complex samples in the input vector        
- * @return none.        
- *        
- * Scaling and Overflow Behavior:        
- * \par        
- * The function implements 1.31 by 1.31 multiplications and finally output is converted into 2.30 format.        
- * Input down scaling is not required.        
- */
-
-void arm_cmplx_mag_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t numSamples)
-{
-  q31_t real, imag;                              /* Temporary variables to hold input values */
-  q31_t acc0, acc1;                              /* Accumulators */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  q31_t real1, real2, imag1, imag2;              /* Temporary variables to hold input values */
-  q31_t out1, out2, out3, out4;                  /* Accumulators */
-  q63_t mul1, mul2, mul3, mul4;                  /* Temporary variables */
-
-
-  /*loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* read complex input from source buffer */
-    real1 = pSrc[0];
-    imag1 = pSrc[1];
-    real2 = pSrc[2];
-    imag2 = pSrc[3];
-
-    /* calculate power of input values */
-    mul1 = (q63_t) real1 *real1;
-    mul2 = (q63_t) imag1 *imag1;
-    mul3 = (q63_t) real2 *real2;
-    mul4 = (q63_t) imag2 *imag2;
-
-    /* get the result to 3.29 format */
-    out1 = (q31_t) (mul1 >> 33);
-    out2 = (q31_t) (mul2 >> 33);
-    out3 = (q31_t) (mul3 >> 33);
-    out4 = (q31_t) (mul4 >> 33);
-
-    /* add real and imaginary accumulators */
-    out1 = out1 + out2;
-    out3 = out3 + out4;
-
-    /* read complex input from source buffer */
-    real1 = pSrc[4];
-    imag1 = pSrc[5];
-    real2 = pSrc[6];
-    imag2 = pSrc[7];
-
-    /* calculate square root */
-    arm_sqrt_q31(out1, &pDst[0]);
-
-    /* calculate power of input values */
-    mul1 = (q63_t) real1 *real1;
-
-    /* calculate square root */
-    arm_sqrt_q31(out3, &pDst[1]);
-
-    /* calculate power of input values */
-    mul2 = (q63_t) imag1 *imag1;
-    mul3 = (q63_t) real2 *real2;
-    mul4 = (q63_t) imag2 *imag2;
-
-    /* get the result to 3.29 format */
-    out1 = (q31_t) (mul1 >> 33);
-    out2 = (q31_t) (mul2 >> 33);
-    out3 = (q31_t) (mul3 >> 33);
-    out4 = (q31_t) (mul4 >> 33);
-
-    /* add real and imaginary accumulators */
-    out1 = out1 + out2;
-    out3 = out3 + out4;
-
-    /* calculate square root */
-    arm_sqrt_q31(out1, &pDst[2]);
-
-    /* increment destination by 8 to process next samples */
-    pSrc += 8u;
-
-    /* calculate square root */
-    arm_sqrt_q31(out3, &pDst[3]);
-
-    /* increment destination by 4 to process next samples */
-    pDst += 4u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  blkCnt = numSamples;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
-    real = *pSrc++;
-    imag = *pSrc++;
-    acc0 = (q31_t) (((q63_t) real * real) >> 33);
-    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
-    /* store the result in 2.30 format in the destination buffer. */
-    arm_sqrt_q31(acc0 + acc1, pDst++);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-}
-
-/**        
- * @} end of cmplx_mag group        
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
deleted file mode 100644
index c49d006a19..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
+++ /dev/null
@@ -1,207 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_cmplx_mag_squared_f32.c    
-*    
-* Description:	Floating-point complex magnitude squared.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-#include "arm_math.h"
-
-/**        
- * @ingroup groupCmplxMath        
- */
-
-/**        
- * @defgroup cmplx_mag_squared Complex Magnitude Squared        
- *        
- * Computes the magnitude squared of the elements of a complex data vector.        
- *       
- * The pSrc points to the source data and        
- * pDst points to the where the result should be written.        
- * numSamples specifies the number of complex samples        
- * in the input array and the data is stored in an interleaved fashion        
- * (real, imag, real, imag, ...).        
- * The input array has a total of 2*numSamples values;        
- * the output array has a total of numSamples values.        
- *        
- * The underlying algorithm is used:        
- *        
- * 
        
- * for(n=0; n        
- *        
- * There are separate functions for floating-point, Q15, and Q31 data types.        
- */
-
-/**        
- * @addtogroup cmplx_mag_squared        
- * @{        
- */
-
-
-/**        
- * @brief  Floating-point complex magnitude squared        
- * @param[in]  *pSrc points to the complex input vector        
- * @param[out]  *pDst points to the real output vector        
- * @param[in]  numSamples number of complex samples in the input vector        
- * @return none.        
- */
-
-void arm_cmplx_mag_squared_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t numSamples)
-{
-  float32_t real, imag;                          /* Temporary variables to store real and imaginary values */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0
-  float32_t real1, real2, real3, real4;          /* Temporary variables to hold real values */
-  float32_t imag1, imag2, imag3, imag4;          /* Temporary variables to hold imaginary values */
-  float32_t mul1, mul2, mul3, mul4;              /* Temporary variables */
-  float32_t mul5, mul6, mul7, mul8;              /* Temporary variables */
-  float32_t out1, out2, out3, out4;              /* Temporary variables to hold output values */
-
-  /*loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
-    /* read real input sample from source buffer */
-    real1 = pSrc[0];
-    /* read imaginary input sample from source buffer */
-    imag1 = pSrc[1];
-
-    /* calculate power of real value */
-    mul1 = real1 * real1;
-
-    /* read real input sample from source buffer */
-    real2 = pSrc[2];
-
-    /* calculate power of imaginary value */
-    mul2 = imag1 * imag1;
-
-    /* read imaginary input sample from source buffer */
-    imag2 = pSrc[3];
-
-    /* calculate power of real value */
-    mul3 = real2 * real2;
-
-    /* read real input sample from source buffer */
-    real3 = pSrc[4];
-
-    /* calculate power of imaginary value */
-    mul4 = imag2 * imag2;
-
-    /* read imaginary input sample from source buffer */
-    imag3 = pSrc[5];
-
-    /* calculate power of real value */
-    mul5 = real3 * real3;
-    /* calculate power of imaginary value */
-    mul6 = imag3 * imag3;
-
-    /* read real input sample from source buffer */
-    real4 = pSrc[6];
-
-    /* accumulate real and imaginary powers */
-    out1 = mul1 + mul2;
-
-    /* read imaginary input sample from source buffer */
-    imag4 = pSrc[7];
-
-    /* accumulate real and imaginary powers */
-    out2 = mul3 + mul4;
-
-    /* calculate power of real value */
-    mul7 = real4 * real4;
-    /* calculate power of imaginary value */
-    mul8 = imag4 * imag4;
-
-    /* store output to destination */
-    pDst[0] = out1;
-
-    /* accumulate real and imaginary powers */
-    out3 = mul5 + mul6;
-
-    /* store output to destination */
-    pDst[1] = out2;
-
-    /* accumulate real and imaginary powers */
-    out4 = mul7 + mul8;
-
-    /* store output to destination */
-    pDst[2] = out3;
-
-    /* increment destination pointer by 8 to process next samples */
-    pSrc += 8u;
-
-    /* store output to destination */
-    pDst[3] = out4;
-
-    /* increment destination pointer by 4 to process next samples */
-    pDst += 4u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  blkCnt = numSamples;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
-    real = *pSrc++;
-    imag = *pSrc++;
-
-    /* out = (real * real) + (imag * imag) */
-    /* store the result in the destination buffer. */
-    *pDst++ = (real * real) + (imag * imag);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-}
-
-/**        
- * @} end of cmplx_mag_squared group        
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
deleted file mode 100644
index 42694058ae..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_cmplx_mag_squared_q15.c    
-*    
-* Description:	Q15 complex magnitude squared.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupCmplxMath    
- */
-
-/**    
- * @addtogroup cmplx_mag_squared    
- * @{    
- */
-
-/**    
- * @brief  Q15 complex magnitude squared    
- * @param  *pSrc points to the complex input vector    
- * @param  *pDst points to the real output vector    
- * @param  numSamples number of complex samples in the input vector    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format.    
- */
-
-void arm_cmplx_mag_squared_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t numSamples)
-{
-  q31_t acc0, acc1;                              /* Accumulators */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  uint32_t blkCnt;                               /* loop counter */
-  q31_t in1, in2, in3, in4;
-  q31_t acc2, acc3;
-
-  /*loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
-    in1 = *__SIMD32(pSrc)++;
-    in2 = *__SIMD32(pSrc)++;
-    in3 = *__SIMD32(pSrc)++;
-    in4 = *__SIMD32(pSrc)++;
-
-    acc0 = __SMUAD(in1, in1);
-    acc1 = __SMUAD(in2, in2);
-    acc2 = __SMUAD(in3, in3);
-    acc3 = __SMUAD(in4, in4);
-
-    /* store the result in 3.13 format in the destination buffer. */
-    *pDst++ = (q15_t) (acc0 >> 17);
-    *pDst++ = (q15_t) (acc1 >> 17);
-    *pDst++ = (q15_t) (acc2 >> 17);
-    *pDst++ = (q15_t) (acc3 >> 17);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
-    in1 = *__SIMD32(pSrc)++;
-    acc0 = __SMUAD(in1, in1);
-
-    /* store the result in 3.13 format in the destination buffer. */
-    *pDst++ = (q15_t) (acc0 >> 17);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  q15_t real, imag;                              /* Temporary variables to store real and imaginary values */
-
-  while(numSamples > 0u)
-  {
-    /* out = ((real * real) + (imag * imag)) */
-    real = *pSrc++;
-    imag = *pSrc++;
-    acc0 = (real * real);
-    acc1 = (imag * imag);
-    /* store the result in 3.13 format in the destination buffer. */
-    *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
-
-    /* Decrement the loop counter */
-    numSamples--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
- * @} end of cmplx_mag_squared group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
deleted file mode 100644
index 7670c88497..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_cmplx_mag_squared_q31.c    
-*    
-* Description:	Q31 complex magnitude squared.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupCmplxMath    
- */
-
-/**    
- * @addtogroup cmplx_mag_squared    
- * @{    
- */
-
-
-/**    
- * @brief  Q31 complex magnitude squared    
- * @param  *pSrc points to the complex input vector    
- * @param  *pDst points to the real output vector    
- * @param  numSamples number of complex samples in the input vector    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format.    
- * Input down scaling is not required.    
- */
-
-void arm_cmplx_mag_squared_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t numSamples)
-{
-  q31_t real, imag;                              /* Temporary variables to store real and imaginary values */
-  q31_t acc0, acc1;                              /* Accumulators */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  uint32_t blkCnt;                               /* loop counter */
-
-  /* loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
-    real = *pSrc++;
-    imag = *pSrc++;
-    acc0 = (q31_t) (((q63_t) real * real) >> 33);
-    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
-    /* store the result in 3.29 format in the destination buffer. */
-    *pDst++ = acc0 + acc1;
-
-    real = *pSrc++;
-    imag = *pSrc++;
-    acc0 = (q31_t) (((q63_t) real * real) >> 33);
-    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
-    /* store the result in 3.29 format in the destination buffer. */
-    *pDst++ = acc0 + acc1;
-
-    real = *pSrc++;
-    imag = *pSrc++;
-    acc0 = (q31_t) (((q63_t) real * real) >> 33);
-    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
-    /* store the result in 3.29 format in the destination buffer. */
-    *pDst++ = acc0 + acc1;
-
-    real = *pSrc++;
-    imag = *pSrc++;
-    acc0 = (q31_t) (((q63_t) real * real) >> 33);
-    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
-    /* store the result in 3.29 format in the destination buffer. */
-    *pDst++ = acc0 + acc1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
-    real = *pSrc++;
-    imag = *pSrc++;
-    acc0 = (q31_t) (((q63_t) real * real) >> 33);
-    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
-    /* store the result in 3.29 format in the destination buffer. */
-    *pDst++ = acc0 + acc1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  while(numSamples > 0u)
-  {
-    /* out = ((real * real) + (imag * imag)) */
-    real = *pSrc++;
-    imag = *pSrc++;
-    acc0 = (q31_t) (((q63_t) real * real) >> 33);
-    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
-    /* store the result in 3.29 format in the destination buffer. */
-    *pDst++ = acc0 + acc1;
-
-    /* Decrement the loop counter */
-    numSamples--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
- * @} end of cmplx_mag_squared group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
deleted file mode 100644
index 15109f231c..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_cmplx_mult_cmplx_f32.c    
-*    
-* Description:	Floating-point complex-by-complex multiplication    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-#include "arm_math.h"
-
-/**        
- * @ingroup groupCmplxMath        
- */
-
-/**        
- * @defgroup CmplxByCmplxMult Complex-by-Complex Multiplication        
- *        
- * Multiplies a complex vector by another complex vector and generates a complex result.        
- * The data in the complex arrays is stored in an interleaved fashion        
- * (real, imag, real, imag, ...).        
- * The parameter numSamples represents the number of complex        
- * samples processed.  The complex arrays have a total of 2*numSamples        
- * real values.        
- *        
- * The underlying algorithm is used:        
- *        
- * 
        
- * for(n=0; n        
- *        
- * There are separate functions for floating-point, Q15, and Q31 data types.        
- */
-
-/**        
- * @addtogroup CmplxByCmplxMult        
- * @{        
- */
-
-
-/**        
- * @brief  Floating-point complex-by-complex multiplication        
- * @param[in]  *pSrcA points to the first input vector        
- * @param[in]  *pSrcB points to the second input vector        
- * @param[out]  *pDst  points to the output vector        
- * @param[in]  numSamples number of complex samples in each vector        
- * @return none.        
- */
-
-void arm_cmplx_mult_cmplx_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t numSamples)
-{
-  float32_t a1, b1, c1, d1;                      /* Temporary variables to store real and imaginary values */
-  uint32_t blkCnt;                               /* loop counters */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  float32_t a2, b2, c2, d2;                      /* Temporary variables to store real and imaginary values */
-  float32_t acc1, acc2, acc3, acc4;
-
-
-  /* loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
-    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
-    a1 = *pSrcA;                /* A[2 * i] */
-    c1 = *pSrcB;                /* B[2 * i] */
-
-    b1 = *(pSrcA + 1);          /* A[2 * i + 1] */
-    acc1 = a1 * c1;             /* acc1 = A[2 * i] * B[2 * i] */
-
-    a2 = *(pSrcA + 2);          /* A[2 * i + 2] */
-    acc2 = (b1 * c1);           /* acc2 = A[2 * i + 1] * B[2 * i] */
-
-    d1 = *(pSrcB + 1);          /* B[2 * i + 1] */
-    c2 = *(pSrcB + 2);          /* B[2 * i + 2] */
-    acc1 -= b1 * d1;            /* acc1 =      A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1] */
-
-    d2 = *(pSrcB + 3);          /* B[2 * i + 3] */
-    acc3 = a2 * c2;             /* acc3 =       A[2 * i + 2] * B[2 * i + 2] */
-
-    b2 = *(pSrcA + 3);          /* A[2 * i + 3] */
-    acc2 += (a1 * d1);          /* acc2 =      A[2 * i + 1] * B[2 * i] + A[2 * i] * B[2 * i + 1] */
-
-    a1 = *(pSrcA + 4);          /* A[2 * i + 4] */
-    acc4 = (a2 * d2);           /* acc4 =   A[2 * i + 2] * B[2 * i + 3] */
-
-    c1 = *(pSrcB + 4);          /* B[2 * i + 4] */
-    acc3 -= (b2 * d2);          /* acc3 =       A[2 * i + 2] * B[2 * i + 2] - A[2 * i + 3] * B[2 * i + 3] */
-    *pDst = acc1;               /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1] */
-
-    b1 = *(pSrcA + 5);          /* A[2 * i + 5] */
-    acc4 += b2 * c2;            /* acc4 =   A[2 * i + 2] * B[2 * i + 3] + A[2 * i + 3] * B[2 * i + 2] */
-
-    *(pDst + 1) = acc2;         /* C[2 * i + 1] = A[2 * i + 1] * B[2 * i] + A[2 * i] * B[2 * i + 1]  */
-    acc1 = (a1 * c1);
-
-    d1 = *(pSrcB + 5);
-    acc2 = (b1 * c1);
-
-    *(pDst + 2) = acc3;
-    *(pDst + 3) = acc4;
-
-    a2 = *(pSrcA + 6);
-    acc1 -= (b1 * d1);
-
-    c2 = *(pSrcB + 6);
-    acc2 += (a1 * d1);
-
-    b2 = *(pSrcA + 7);
-    acc3 = (a2 * c2);
-
-    d2 = *(pSrcB + 7);
-    acc4 = (b2 * c2);
-
-    *(pDst + 4) = acc1;
-    pSrcA += 8u;
-
-    acc3 -= (b2 * d2);
-    acc4 += (a2 * d2);
-
-    *(pDst + 5) = acc2;
-    pSrcB += 8u;
-
-    *(pDst + 6) = acc3;
-    *(pDst + 7) = acc4;
-
-    pDst += 8u;
-
-    /* Decrement the numSamples loop counter */
-    blkCnt--;
-  }
-
-  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  blkCnt = numSamples;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
-    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
-    a1 = *pSrcA++;
-    b1 = *pSrcA++;
-    c1 = *pSrcB++;
-    d1 = *pSrcB++;
-
-    /* store the result in the destination buffer. */
-    *pDst++ = (a1 * c1) - (b1 * d1);
-    *pDst++ = (a1 * d1) + (b1 * c1);
-
-    /* Decrement the numSamples loop counter */
-    blkCnt--;
-  }
-}
-
-/**        
- * @} end of CmplxByCmplxMult group        
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
deleted file mode 100644
index 89412f5ba1..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
+++ /dev/null
@@ -1,185 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_cmplx_mult_cmplx_q15.c    
-*    
-* Description:	Q15 complex-by-complex multiplication    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupCmplxMath    
- */
-
-/**    
- * @addtogroup CmplxByCmplxMult    
- * @{    
- */
-
-/**    
- * @brief  Q15 complex-by-complex multiplication    
- * @param[in]  *pSrcA points to the first input vector    
- * @param[in]  *pSrcB points to the second input vector    
- * @param[out]  *pDst  points to the output vector    
- * @param[in]  numSamples number of complex samples in each vector    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format.    
- */
-
-void arm_cmplx_mult_cmplx_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t numSamples)
-{
-  q15_t a, b, c, d;                              /* Temporary variables to store real and imaginary values */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  uint32_t blkCnt;                               /* loop counters */
-
-  /* loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
-    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
-    a = *pSrcA++;
-    b = *pSrcA++;
-    c = *pSrcB++;
-    d = *pSrcB++;
-
-    /* store the result in 3.13 format in the destination buffer. */
-    *pDst++ =
-      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
-    /* store the result in 3.13 format in the destination buffer. */
-    *pDst++ =
-      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
-
-    a = *pSrcA++;
-    b = *pSrcA++;
-    c = *pSrcB++;
-    d = *pSrcB++;
-
-    /* store the result in 3.13 format in the destination buffer. */
-    *pDst++ =
-      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
-    /* store the result in 3.13 format in the destination buffer. */
-    *pDst++ =
-      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
-
-    a = *pSrcA++;
-    b = *pSrcA++;
-    c = *pSrcB++;
-    d = *pSrcB++;
-
-    /* store the result in 3.13 format in the destination buffer. */
-    *pDst++ =
-      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
-    /* store the result in 3.13 format in the destination buffer. */
-    *pDst++ =
-      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
-
-    a = *pSrcA++;
-    b = *pSrcA++;
-    c = *pSrcB++;
-    d = *pSrcB++;
-
-    /* store the result in 3.13 format in the destination buffer. */
-    *pDst++ =
-      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
-    /* store the result in 3.13 format in the destination buffer. */
-    *pDst++ =
-      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
-
-    /* Decrement the blockSize loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
-    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
-    a = *pSrcA++;
-    b = *pSrcA++;
-    c = *pSrcB++;
-    d = *pSrcB++;
-
-    /* store the result in 3.13 format in the destination buffer. */
-    *pDst++ =
-      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
-    /* store the result in 3.13 format in the destination buffer. */
-    *pDst++ =
-      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
-
-    /* Decrement the blockSize loop counter */
-    blkCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  while(numSamples > 0u)
-  {
-    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
-    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
-    a = *pSrcA++;
-    b = *pSrcA++;
-    c = *pSrcB++;
-    d = *pSrcB++;
-
-    /* store the result in 3.13 format in the destination buffer. */
-    *pDst++ =
-      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
-    /* store the result in 3.13 format in the destination buffer. */
-    *pDst++ =
-      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
-
-    /* Decrement the blockSize loop counter */
-    numSamples--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
- * @} end of CmplxByCmplxMult group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
deleted file mode 100644
index 668cbfa610..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
+++ /dev/null
@@ -1,318 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_cmplx_mult_cmplx_q31.c    
-*    
-* Description:	Q31 complex-by-complex multiplication    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupCmplxMath    
- */
-
-/**    
- * @addtogroup CmplxByCmplxMult    
- * @{    
- */
-
-
-/**    
- * @brief  Q31 complex-by-complex multiplication    
- * @param[in]  *pSrcA points to the first input vector    
- * @param[in]  *pSrcB points to the second input vector    
- * @param[out]  *pDst  points to the output vector    
- * @param[in]  numSamples number of complex samples in each vector    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format.    
- * Input down scaling is not required.    
- */
-
-void arm_cmplx_mult_cmplx_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t numSamples)
-{
-  q31_t a, b, c, d;                              /* Temporary variables to store real and imaginary values */
-  uint32_t blkCnt;                               /* loop counters */
-  q31_t mul1, mul2, mul3, mul4;
-  q31_t out1, out2;
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /* loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
-    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
-    a = *pSrcA++;
-    b = *pSrcA++;
-    c = *pSrcB++;
-    d = *pSrcB++;
-
-    mul1 = (q31_t) (((q63_t) a * c) >> 32);
-    mul2 = (q31_t) (((q63_t) b * d) >> 32);
-    mul3 = (q31_t) (((q63_t) a * d) >> 32);
-    mul4 = (q31_t) (((q63_t) b * c) >> 32);
-
-    mul1 = (mul1 >> 1);
-    mul2 = (mul2 >> 1);
-    mul3 = (mul3 >> 1);
-    mul4 = (mul4 >> 1);
-
-    out1 = mul1 - mul2;
-    out2 = mul3 + mul4;
-
-    /* store the real result in 3.29 format in the destination buffer. */
-    *pDst++ = out1;
-    /* store the imag result in 3.29 format in the destination buffer. */
-    *pDst++ = out2;
-
-    a = *pSrcA++;
-    b = *pSrcA++;
-    c = *pSrcB++;
-    d = *pSrcB++;
-
-    mul1 = (q31_t) (((q63_t) a * c) >> 32);
-    mul2 = (q31_t) (((q63_t) b * d) >> 32);
-    mul3 = (q31_t) (((q63_t) a * d) >> 32);
-    mul4 = (q31_t) (((q63_t) b * c) >> 32);
-
-    mul1 = (mul1 >> 1);
-    mul2 = (mul2 >> 1);
-    mul3 = (mul3 >> 1);
-    mul4 = (mul4 >> 1);
-
-    out1 = mul1 - mul2;
-    out2 = mul3 + mul4;
-
-    /* store the real result in 3.29 format in the destination buffer. */
-    *pDst++ = out1;
-    /* store the imag result in 3.29 format in the destination buffer. */
-    *pDst++ = out2;
-
-    a = *pSrcA++;
-    b = *pSrcA++;
-    c = *pSrcB++;
-    d = *pSrcB++;
-
-    mul1 = (q31_t) (((q63_t) a * c) >> 32);
-    mul2 = (q31_t) (((q63_t) b * d) >> 32);
-    mul3 = (q31_t) (((q63_t) a * d) >> 32);
-    mul4 = (q31_t) (((q63_t) b * c) >> 32);
-
-    mul1 = (mul1 >> 1);
-    mul2 = (mul2 >> 1);
-    mul3 = (mul3 >> 1);
-    mul4 = (mul4 >> 1);
-
-    out1 = mul1 - mul2;
-    out2 = mul3 + mul4;
-
-    /* store the real result in 3.29 format in the destination buffer. */
-    *pDst++ = out1;
-    /* store the imag result in 3.29 format in the destination buffer. */
-    *pDst++ = out2;
-
-    a = *pSrcA++;
-    b = *pSrcA++;
-    c = *pSrcB++;
-    d = *pSrcB++;
-
-    mul1 = (q31_t) (((q63_t) a * c) >> 32);
-    mul2 = (q31_t) (((q63_t) b * d) >> 32);
-    mul3 = (q31_t) (((q63_t) a * d) >> 32);
-    mul4 = (q31_t) (((q63_t) b * c) >> 32);
-
-    mul1 = (mul1 >> 1);
-    mul2 = (mul2 >> 1);
-    mul3 = (mul3 >> 1);
-    mul4 = (mul4 >> 1);
-
-    out1 = mul1 - mul2;
-    out2 = mul3 + mul4;
-
-    /* store the real result in 3.29 format in the destination buffer. */
-    *pDst++ = out1;
-    /* store the imag result in 3.29 format in the destination buffer. */
-    *pDst++ = out2;
-
-    /* Decrement the blockSize loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
-    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
-    a = *pSrcA++;
-    b = *pSrcA++;
-    c = *pSrcB++;
-    d = *pSrcB++;
-
-    mul1 = (q31_t) (((q63_t) a * c) >> 32);
-    mul2 = (q31_t) (((q63_t) b * d) >> 32);
-    mul3 = (q31_t) (((q63_t) a * d) >> 32);
-    mul4 = (q31_t) (((q63_t) b * c) >> 32);
-
-    mul1 = (mul1 >> 1);
-    mul2 = (mul2 >> 1);
-    mul3 = (mul3 >> 1);
-    mul4 = (mul4 >> 1);
-
-    out1 = mul1 - mul2;
-    out2 = mul3 + mul4;
-
-    /* store the real result in 3.29 format in the destination buffer. */
-    *pDst++ = out1;
-    /* store the imag result in 3.29 format in the destination buffer. */
-    *pDst++ = out2;
-
-    /* Decrement the blockSize loop counter */
-    blkCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* loop Unrolling */
-  blkCnt = numSamples >> 1u;
-
-  /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.     
-   ** a second loop below computes the remaining 1 sample. */
-  while(blkCnt > 0u)
-  {
-    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
-    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
-    a = *pSrcA++;
-    b = *pSrcA++;
-    c = *pSrcB++;
-    d = *pSrcB++;
-
-    mul1 = (q31_t) (((q63_t) a * c) >> 32);
-    mul2 = (q31_t) (((q63_t) b * d) >> 32);
-    mul3 = (q31_t) (((q63_t) a * d) >> 32);
-    mul4 = (q31_t) (((q63_t) b * c) >> 32);
-
-    mul1 = (mul1 >> 1);
-    mul2 = (mul2 >> 1);
-    mul3 = (mul3 >> 1);
-    mul4 = (mul4 >> 1);
-
-    out1 = mul1 - mul2;
-    out2 = mul3 + mul4;
-
-    /* store the real result in 3.29 format in the destination buffer. */
-    *pDst++ = out1;
-    /* store the imag result in 3.29 format in the destination buffer. */
-    *pDst++ = out2;
-
-    a = *pSrcA++;
-    b = *pSrcA++;
-    c = *pSrcB++;
-    d = *pSrcB++;
-
-    mul1 = (q31_t) (((q63_t) a * c) >> 32);
-    mul2 = (q31_t) (((q63_t) b * d) >> 32);
-    mul3 = (q31_t) (((q63_t) a * d) >> 32);
-    mul4 = (q31_t) (((q63_t) b * c) >> 32);
-
-    mul1 = (mul1 >> 1);
-    mul2 = (mul2 >> 1);
-    mul3 = (mul3 >> 1);
-    mul4 = (mul4 >> 1);
-
-    out1 = mul1 - mul2;
-    out2 = mul3 + mul4;
-
-    /* store the real result in 3.29 format in the destination buffer. */
-    *pDst++ = out1;
-    /* store the imag result in 3.29 format in the destination buffer. */
-    *pDst++ = out2;
-
-    /* Decrement the blockSize loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 2, compute any remaining output samples here.     
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x2u;
-
-  while(blkCnt > 0u)
-  {
-    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
-    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
-    a = *pSrcA++;
-    b = *pSrcA++;
-    c = *pSrcB++;
-    d = *pSrcB++;
-
-    mul1 = (q31_t) (((q63_t) a * c) >> 32);
-    mul2 = (q31_t) (((q63_t) b * d) >> 32);
-    mul3 = (q31_t) (((q63_t) a * d) >> 32);
-    mul4 = (q31_t) (((q63_t) b * c) >> 32);
-
-    mul1 = (mul1 >> 1);
-    mul2 = (mul2 >> 1);
-    mul3 = (mul3 >> 1);
-    mul4 = (mul4 >> 1);
-
-    out1 = mul1 - mul2;
-    out2 = mul3 + mul4;
-
-    /* store the real result in 3.29 format in the destination buffer. */
-    *pDst++ = out1;
-    /* store the imag result in 3.29 format in the destination buffer. */
-    *pDst++ = out2;
-
-    /* Decrement the blockSize loop counter */
-    blkCnt--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
- * @} end of CmplxByCmplxMult group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
deleted file mode 100644
index bbd7cf6746..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
+++ /dev/null
@@ -1,217 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_cmplx_mult_real_f32.c    
-*    
-* Description:	Floating-point complex by real multiplication    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**        
- * @ingroup groupCmplxMath        
- */
-
-/**        
- * @defgroup CmplxByRealMult Complex-by-Real Multiplication        
- *        
- * Multiplies a complex vector by a real vector and generates a complex result.        
- * The data in the complex arrays is stored in an interleaved fashion        
- * (real, imag, real, imag, ...).        
- * The parameter numSamples represents the number of complex        
- * samples processed.  The complex arrays have a total of 2*numSamples        
- * real values while the real array has a total of numSamples        
- * real values.        
- *        
- * The underlying algorithm is used:        
- *        
- * 
        
- * for(n=0; n        
- *        
- * There are separate functions for floating-point, Q15, and Q31 data types.        
- */
-
-/**        
- * @addtogroup CmplxByRealMult        
- * @{        
- */
-
-
-/**        
- * @brief  Floating-point complex-by-real multiplication        
- * @param[in]  *pSrcCmplx points to the complex input vector        
- * @param[in]  *pSrcReal points to the real input vector        
- * @param[out]  *pCmplxDst points to the complex output vector        
- * @param[in]  numSamples number of samples in each vector        
- * @return none.        
- */
-
-void arm_cmplx_mult_real_f32(
-  float32_t * pSrcCmplx,
-  float32_t * pSrcReal,
-  float32_t * pCmplxDst,
-  uint32_t numSamples)
-{
-  float32_t in;                                  /* Temporary variable to store input value */
-  uint32_t blkCnt;                               /* loop counters */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  float32_t inA1, inA2, inA3, inA4;              /* Temporary variables to hold input data */
-  float32_t inA5, inA6, inA7, inA8;              /* Temporary variables to hold input data */
-  float32_t inB1, inB2, inB3, inB4;              /* Temporary variables to hold input data */
-  float32_t out1, out2, out3, out4;              /* Temporary variables to hold output data */
-  float32_t out5, out6, out7, out8;              /* Temporary variables to hold output data */
-
-  /* loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C[2 * i] = A[2 * i] * B[i].            */
-    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
-    /* read input from complex input buffer */
-    inA1 = pSrcCmplx[0];
-    inA2 = pSrcCmplx[1];
-    /* read input from real input buffer */
-    inB1 = pSrcReal[0];
-
-    /* read input from complex input buffer */
-    inA3 = pSrcCmplx[2];
-
-    /* multiply complex buffer real input with real buffer input */
-    out1 = inA1 * inB1;
-
-    /* read input from complex input buffer */
-    inA4 = pSrcCmplx[3];
-
-    /* multiply complex buffer imaginary input with real buffer input */
-    out2 = inA2 * inB1;
-
-    /* read input from real input buffer */
-    inB2 = pSrcReal[1];
-    /* read input from complex input buffer */
-    inA5 = pSrcCmplx[4];
-
-    /* multiply complex buffer real input with real buffer input */
-    out3 = inA3 * inB2;
-
-    /* read input from complex input buffer */
-    inA6 = pSrcCmplx[5];
-    /* read input from real input buffer */
-    inB3 = pSrcReal[2];
-
-    /* multiply complex buffer imaginary input with real buffer input */
-    out4 = inA4 * inB2;
-
-    /* read input from complex input buffer */
-    inA7 = pSrcCmplx[6];
-
-    /* multiply complex buffer real input with real buffer input */
-    out5 = inA5 * inB3;
-
-    /* read input from complex input buffer */
-    inA8 = pSrcCmplx[7];
-
-    /* multiply complex buffer imaginary input with real buffer input */
-    out6 = inA6 * inB3;
-
-    /* read input from real input buffer */
-    inB4 = pSrcReal[3];
-
-    /* store result to destination bufer */
-    pCmplxDst[0] = out1;
-
-    /* multiply complex buffer real input with real buffer input */
-    out7 = inA7 * inB4;
-
-    /* store result to destination bufer */
-    pCmplxDst[1] = out2;
-
-    /* multiply complex buffer imaginary input with real buffer input */
-    out8 = inA8 * inB4;
-
-    /* store result to destination bufer */
-    pCmplxDst[2] = out3;
-    pCmplxDst[3] = out4;
-    pCmplxDst[4] = out5;
-
-    /* incremnet complex input buffer by 8 to process next samples */
-    pSrcCmplx += 8u;
-
-    /* store result to destination bufer */
-    pCmplxDst[5] = out6;
-
-    /* increment real input buffer by 4 to process next samples */
-    pSrcReal += 4u;
-
-    /* store result to destination bufer */
-    pCmplxDst[6] = out7;
-    pCmplxDst[7] = out8;
-
-    /* increment destination buffer by 8 to process next sampels */
-    pCmplxDst += 8u;
-
-    /* Decrement the numSamples loop counter */
-    blkCnt--;
-  }
-
-  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  blkCnt = numSamples;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* C[2 * i] = A[2 * i] * B[i].            */
-    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
-    in = *pSrcReal++;
-    /* store the result in the destination buffer. */
-    *pCmplxDst++ = (*pSrcCmplx++) * (in);
-    *pCmplxDst++ = (*pSrcCmplx++) * (in);
-
-    /* Decrement the numSamples loop counter */
-    blkCnt--;
-  }
-}
-
-/**        
- * @} end of CmplxByRealMult group        
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
deleted file mode 100644
index 2e56b0f3f6..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_cmplx_mult_real_q15.c    
-*    
-* Description:	Q15 complex by real multiplication    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupCmplxMath    
- */
-
-/**    
- * @addtogroup CmplxByRealMult    
- * @{    
- */
-
-
-/**    
- * @brief  Q15 complex-by-real multiplication    
- * @param[in]  *pSrcCmplx points to the complex input vector    
- * @param[in]  *pSrcReal points to the real input vector    
- * @param[out]  *pCmplxDst points to the complex output vector    
- * @param[in]  numSamples number of samples in each vector    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function uses saturating arithmetic.    
- * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.    
- */
-
-void arm_cmplx_mult_real_q15(
-  q15_t * pSrcCmplx,
-  q15_t * pSrcReal,
-  q15_t * pCmplxDst,
-  uint32_t numSamples)
-{
-  q15_t in;                                      /* Temporary variable to store input value */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  uint32_t blkCnt;                               /* loop counters */
-  q31_t inA1, inA2;                              /* Temporary variables to hold input data */
-  q31_t inB1;                                    /* Temporary variables to hold input data */
-  q15_t out1, out2, out3, out4;                  /* Temporary variables to hold output data */
-  q31_t mul1, mul2, mul3, mul4;                  /* Temporary variables to hold intermediate data */
-
-  /* loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C[2 * i] = A[2 * i] * B[i].            */
-    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
-    /* read complex number both real and imaginary from complex input buffer */
-    inA1 = *__SIMD32(pSrcCmplx)++;
-    /* read two real values at a time from real input buffer */
-    inB1 = *__SIMD32(pSrcReal)++;
-    /* read complex number both real and imaginary from complex input buffer */
-    inA2 = *__SIMD32(pSrcCmplx)++;
-
-    /* multiply complex number with real numbers */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1));
-    mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1));
-    mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16));
-    mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16));
-
-#else
-
-    mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
-    mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16));
-    mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1);
-    mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1);
-
-#endif //      #ifndef ARM_MATH_BIG_ENDIAN
-
-    /* saturate the result */
-    out1 = (q15_t) __SSAT(mul1 >> 15u, 16);
-    out2 = (q15_t) __SSAT(mul2 >> 15u, 16);
-    out3 = (q15_t) __SSAT(mul3 >> 15u, 16);
-    out4 = (q15_t) __SSAT(mul4 >> 15u, 16);
-
-    /* pack real and imaginary outputs and store them to destination */
-    *__SIMD32(pCmplxDst)++ = __PKHBT(out1, out2, 16);
-    *__SIMD32(pCmplxDst)++ = __PKHBT(out3, out4, 16);
-
-    inA1 = *__SIMD32(pSrcCmplx)++;
-    inB1 = *__SIMD32(pSrcReal)++;
-    inA2 = *__SIMD32(pSrcCmplx)++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1));
-    mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1));
-    mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16));
-    mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16));
-
-#else
-
-    mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
-    mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16));
-    mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1);
-    mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1);
-
-#endif //      #ifndef ARM_MATH_BIG_ENDIAN
-
-    out1 = (q15_t) __SSAT(mul1 >> 15u, 16);
-    out2 = (q15_t) __SSAT(mul2 >> 15u, 16);
-    out3 = (q15_t) __SSAT(mul3 >> 15u, 16);
-    out4 = (q15_t) __SSAT(mul4 >> 15u, 16);
-
-    *__SIMD32(pCmplxDst)++ = __PKHBT(out1, out2, 16);
-    *__SIMD32(pCmplxDst)++ = __PKHBT(out3, out4, 16);
-
-    /* Decrement the numSamples loop counter */
-    blkCnt--;
-  }
-
-  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C[2 * i] = A[2 * i] * B[i].            */
-    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
-    in = *pSrcReal++;
-    /* store the result in the destination buffer. */
-    *pCmplxDst++ =
-      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
-    *pCmplxDst++ =
-      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
-
-    /* Decrement the numSamples loop counter */
-    blkCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  while(numSamples > 0u)
-  {
-    /* realOut = realA * realB.            */
-    /* imagOut = imagA * realB.                */
-    in = *pSrcReal++;
-    /* store the result in the destination buffer. */
-    *pCmplxDst++ =
-      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
-    *pCmplxDst++ =
-      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
-
-    /* Decrement the numSamples loop counter */
-    numSamples--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
- * @} end of CmplxByRealMult group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
deleted file mode 100644
index 94483f62b0..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
+++ /dev/null
@@ -1,215 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_cmplx_mult_real_q31.c    
-*    
-* Description:	Q31 complex by real multiplication    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupCmplxMath    
- */
-
-/**    
- * @addtogroup CmplxByRealMult    
- * @{    
- */
-
-
-/**    
- * @brief  Q31 complex-by-real multiplication    
- * @param[in]  *pSrcCmplx points to the complex input vector    
- * @param[in]  *pSrcReal points to the real input vector    
- * @param[out]  *pCmplxDst points to the complex output vector    
- * @param[in]  numSamples number of samples in each vector    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function uses saturating arithmetic.    
- * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.    
- */
-
-void arm_cmplx_mult_real_q31(
-  q31_t * pSrcCmplx,
-  q31_t * pSrcReal,
-  q31_t * pCmplxDst,
-  uint32_t numSamples)
-{
-  q31_t inA1;                                    /* Temporary variable to store input value */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  uint32_t blkCnt;                               /* loop counters */
-  q31_t inA2, inA3, inA4;                        /* Temporary variables to hold input data */
-  q31_t inB1, inB2;                              /* Temporary variabels to hold input data */
-  q31_t out1, out2, out3, out4;                  /* Temporary variables to hold output data */
-
-  /* loop Unrolling */
-  blkCnt = numSamples >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C[2 * i] = A[2 * i] * B[i].            */
-    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
-    /* read real input from complex input buffer */
-    inA1 = *pSrcCmplx++;
-    inA2 = *pSrcCmplx++;
-    /* read input from real input bufer */
-    inB1 = *pSrcReal++;
-    inB2 = *pSrcReal++;
-    /* read imaginary input from complex input buffer */
-    inA3 = *pSrcCmplx++;
-    inA4 = *pSrcCmplx++;
-
-    /* multiply complex input with real input */
-    out1 = ((q63_t) inA1 * inB1) >> 32;
-    out2 = ((q63_t) inA2 * inB1) >> 32;
-    out3 = ((q63_t) inA3 * inB2) >> 32;
-    out4 = ((q63_t) inA4 * inB2) >> 32;
-
-    /* sature the result */
-    out1 = __SSAT(out1, 31);
-    out2 = __SSAT(out2, 31);
-    out3 = __SSAT(out3, 31);
-    out4 = __SSAT(out4, 31);
-
-    /* get result in 1.31 format */
-    out1 = out1 << 1;
-    out2 = out2 << 1;
-    out3 = out3 << 1;
-    out4 = out4 << 1;
-
-    /* store the result to destination buffer */
-    *pCmplxDst++ = out1;
-    *pCmplxDst++ = out2;
-    *pCmplxDst++ = out3;
-    *pCmplxDst++ = out4;
-
-    /* read real input from complex input buffer */
-    inA1 = *pSrcCmplx++;
-    inA2 = *pSrcCmplx++;
-    /* read input from real input bufer */
-    inB1 = *pSrcReal++;
-    inB2 = *pSrcReal++;
-    /* read imaginary input from complex input buffer */
-    inA3 = *pSrcCmplx++;
-    inA4 = *pSrcCmplx++;
-
-    /* multiply complex input with real input */
-    out1 = ((q63_t) inA1 * inB1) >> 32;
-    out2 = ((q63_t) inA2 * inB1) >> 32;
-    out3 = ((q63_t) inA3 * inB2) >> 32;
-    out4 = ((q63_t) inA4 * inB2) >> 32;
-
-    /* sature the result */
-    out1 = __SSAT(out1, 31);
-    out2 = __SSAT(out2, 31);
-    out3 = __SSAT(out3, 31);
-    out4 = __SSAT(out4, 31);
-
-    /* get result in 1.31 format */
-    out1 = out1 << 1;
-    out2 = out2 << 1;
-    out3 = out3 << 1;
-    out4 = out4 << 1;
-
-    /* store the result to destination buffer */
-    *pCmplxDst++ = out1;
-    *pCmplxDst++ = out2;
-    *pCmplxDst++ = out3;
-    *pCmplxDst++ = out4;
-
-    /* Decrement the numSamples loop counter */
-    blkCnt--;
-  }
-
-  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = numSamples % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C[2 * i] = A[2 * i] * B[i].            */
-    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
-    /* read real input from complex input buffer */
-    inA1 = *pSrcCmplx++;
-    inA2 = *pSrcCmplx++;
-    /* read input from real input bufer */
-    inB1 = *pSrcReal++;
-
-    /* multiply complex input with real input */
-    out1 = ((q63_t) inA1 * inB1) >> 32;
-    out2 = ((q63_t) inA2 * inB1) >> 32;
-
-    /* sature the result */
-    out1 = __SSAT(out1, 31);
-    out2 = __SSAT(out2, 31);
-
-    /* get result in 1.31 format */
-    out1 = out1 << 1;
-    out2 = out2 << 1;
-
-    /* store the result to destination buffer */
-    *pCmplxDst++ = out1;
-    *pCmplxDst++ = out2;
-
-    /* Decrement the numSamples loop counter */
-    blkCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  while(numSamples > 0u)
-  {
-    /* realOut = realA * realB.            */
-    /* imagReal = imagA * realB.               */
-    inA1 = *pSrcReal++;
-    /* store the result in the destination buffer. */
-    *pCmplxDst++ =
-      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * inA1) >> 31);
-    *pCmplxDst++ =
-      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * inA1) >> 31);
-
-    /* Decrement the numSamples loop counter */
-    numSamples--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
- * @} end of CmplxByRealMult group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_f32.c
deleted file mode 100644
index 9ae46d9ae8..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_f32.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_pid_init_f32.c    
-*    
-* Description:	Floating-point PID Control initialization function    
-*				   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
- /**    
- * @addtogroup PID    
- * @{    
- */
-
-/**    
- * @brief  Initialization function for the floating-point PID Control.   
- * @param[in,out] *S points to an instance of the PID structure.   
- * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state & 1 = reset the state.   
- * @return none.   
- * \par Description:   
- * \par    
- * The resetStateFlag specifies whether to set state to zero or not. \n   
- * The function computes the structure fields: A0, A1 A2    
- * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)    
- * also sets the state variables to all zeros.    
- */
-
-void arm_pid_init_f32(
-  arm_pid_instance_f32 * S,
-  int32_t resetStateFlag)
-{
-
-  /* Derived coefficient A0 */
-  S->A0 = S->Kp + S->Ki + S->Kd;
-
-  /* Derived coefficient A1 */
-  S->A1 = (-S->Kp) - ((float32_t) 2.0 * S->Kd);
-
-  /* Derived coefficient A2 */
-  S->A2 = S->Kd;
-
-  /* Check whether state needs reset or not */
-  if(resetStateFlag)
-  {
-    /* Clear the state buffer.  The size will be always 3 samples */
-    memset(S->state, 0, 3u * sizeof(float32_t));
-  }
-
-}
-
-/**    
- * @} end of PID group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q15.c
deleted file mode 100644
index a10b1e1cfe..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q15.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_pid_init_q15.c    
-*    
-* Description:	Q15 PID Control initialization function    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
- /**    
- * @addtogroup PID    
- * @{    
- */
-
-/**    
- * @details    
- * @param[in,out] *S points to an instance of the Q15 PID structure.    
- * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.    
- * @return none.    
- * \par Description:   
- * \par    
- * The resetStateFlag specifies whether to set state to zero or not. \n   
- * The function computes the structure fields: A0, A1 A2    
- * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)    
- * also sets the state variables to all zeros.    
- */
-
-void arm_pid_init_q15(
-  arm_pid_instance_q15 * S,
-  int32_t resetStateFlag)
-{
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /* Derived coefficient A0 */
-  S->A0 = __QADD16(__QADD16(S->Kp, S->Ki), S->Kd);
-
-  /* Derived coefficients and pack into A1 */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-  S->A1 = __PKHBT(-__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), S->Kd, 16);
-
-#else
-
-  S->A1 = __PKHBT(S->Kd, -__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), 16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-  /* Check whether state needs reset or not */
-  if(resetStateFlag)
-  {
-    /* Clear the state buffer.  The size will be always 3 samples */
-    memset(S->state, 0, 3u * sizeof(q15_t));
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q31_t temp;                                    /*to store the sum */
-
-  /* Derived coefficient A0 */
-  temp = S->Kp + S->Ki + S->Kd;
-  S->A0 = (q15_t) __SSAT(temp, 16);
-
-  /* Derived coefficients and pack into A1 */
-  temp = -(S->Kd + S->Kd + S->Kp);
-  S->A1 = (q15_t) __SSAT(temp, 16);
-  S->A2 = S->Kd;
-
-
-
-  /* Check whether state needs reset or not */
-  if(resetStateFlag)
-  {
-    /* Clear the state buffer.  The size will be always 3 samples */
-    memset(S->state, 0, 3u * sizeof(q15_t));
-  }
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
- * @} end of PID group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q31.c
deleted file mode 100644
index 0afd13bb78..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q31.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_pid_init_q31.c    
-*    
-* Description:	Q31 PID Control initialization function     
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
- /**    
- * @addtogroup PID    
- * @{    
- */
-
-/**    
- * @brief  Initialization function for the Q31 PID Control.   
- * @param[in,out] *S points to an instance of the Q31 PID structure.   
- * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.   
- * @return none.    
- * \par Description:   
- * \par    
- * The resetStateFlag specifies whether to set state to zero or not. \n   
- * The function computes the structure fields: A0, A1 A2    
- * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)    
- * also sets the state variables to all zeros.    
- */
-
-void arm_pid_init_q31(
-  arm_pid_instance_q31 * S,
-  int32_t resetStateFlag)
-{
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /* Derived coefficient A0 */
-  S->A0 = __QADD(__QADD(S->Kp, S->Ki), S->Kd);
-
-  /* Derived coefficient A1 */
-  S->A1 = -__QADD(__QADD(S->Kd, S->Kd), S->Kp);
-
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q31_t temp;
-
-  /* Derived coefficient A0 */
-  temp = clip_q63_to_q31((q63_t) S->Kp + S->Ki);
-  S->A0 = clip_q63_to_q31((q63_t) temp + S->Kd);
-
-  /* Derived coefficient A1 */
-  temp = clip_q63_to_q31((q63_t) S->Kd + S->Kd);
-  S->A1 = -clip_q63_to_q31((q63_t) temp + S->Kp);
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  /* Derived coefficient A2 */
-  S->A2 = S->Kd;
-
-  /* Check whether state needs reset or not */
-  if(resetStateFlag)
-  {
-    /* Clear the state buffer.  The size will be always 3 samples */
-    memset(S->state, 0, 3u * sizeof(q31_t));
-  }
-
-}
-
-/**    
- * @} end of PID group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_f32.c
deleted file mode 100644
index 739812e97f..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_f32.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_pid_reset_f32.c    
-*    
-* Description:	Floating-point PID Control reset function   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
- /**    
- * @addtogroup PID    
- * @{    
- */
-
-/**    
-* @brief  Reset function for the floating-point PID Control.   
-* @param[in] *S	Instance pointer of PID control data structure.   
-* @return none.    
-* \par Description:   
-* The function resets the state buffer to zeros.    
-*/
-void arm_pid_reset_f32(
-  arm_pid_instance_f32 * S)
-{
-
-  /* Clear the state buffer.  The size will be always 3 samples */
-  memset(S->state, 0, 3u * sizeof(float32_t));
-}
-
-/**    
- * @} end of PID group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q15.c
deleted file mode 100644
index 588e2b8694..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q15.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_pid_reset_q15.c    
-*    
-* Description:	Q15 PID Control reset function   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
- /**    
- * @addtogroup PID    
- * @{    
- */
-
-/**    
-* @brief  Reset function for the Q15 PID Control.   
-* @param[in] *S		Instance pointer of PID control data structure.   
-* @return none.    
-* \par Description:   
-* The function resets the state buffer to zeros.    
-*/
-void arm_pid_reset_q15(
-  arm_pid_instance_q15 * S)
-{
-  /* Reset state to zero, The size will be always 3 samples */
-  memset(S->state, 0, 3u * sizeof(q15_t));
-}
-
-/**    
- * @} end of PID group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q31.c
deleted file mode 100644
index 4b63f410d0..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q31.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_pid_reset_q31.c    
-*    
-* Description:	Q31 PID Control reset function   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
- /**    
- * @addtogroup PID    
- * @{    
- */
-
-/**    
-* @brief  Reset function for the Q31 PID Control.   
-* @param[in] *S	Instance pointer of PID control data structure.   
-* @return none.    
-* \par Description:   
-* The function resets the state buffer to zeros.    
-*/
-void arm_pid_reset_q31(
-  arm_pid_instance_q31 * S)
-{
-
-  /* Clear the state buffer.  The size will be always 3 samples */
-  memset(S->state, 0, 3u * sizeof(q31_t));
-}
-
-/**    
- * @} end of PID group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_f32.c
deleted file mode 100644
index 8ee5f359dd..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_f32.c
+++ /dev/null
@@ -1,428 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_sin_cos_f32.c    
-*    
-* Description:	Sine and Cosine calculation for floating-point values.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupController    
- */
-
-/**    
- * @defgroup SinCos Sine Cosine   
- *    
- * Computes the trigonometric sine and cosine values using a combination of table lookup   
- * and linear interpolation.     
- * There are separate functions for Q31 and floating-point data types.   
- * The input to the floating-point version is in degrees while the   
- * fixed-point Q31 have a scaled input with the range   
- * [-1 0.9999] mapping to [-180 179] degrees.   
- *   
- * The implementation is based on table lookup using 360 values together with linear interpolation.   
- * The steps used are:   
- *  -# Calculation of the nearest integer table index.   
- *  -# Compute the fractional portion (fract) of the input.   
- *  -# Fetch the value corresponding to \c index from sine table to \c y0 and also value from \c index+1 to \c y1.      
- *  -# Sine value is computed as  *psinVal = y0 + (fract * (y1 - y0)).    
- *  -# Fetch the value corresponding to \c index from cosine table to \c y0 and also value from \c index+1 to \c y1.      
- *  -# Cosine value is computed as  *pcosVal = y0 + (fract * (y1 - y0)).    
- */
-
- /**    
- * @addtogroup SinCos    
- * @{    
- */
-
-
-/**    
-* \par    
-* Cosine Table is generated from following loop    
-* 
for(i = 0; i < 360; i++)    
-* {    
-*    cosTable[i]= cos((i-180) * PI/180.0);    
-* } 
   
-*/
-
-static const float32_t cosTable[360] = {
-  -0.999847695156391270f, -0.999390827019095760f, -0.998629534754573830f,
-  -0.997564050259824200f, -0.996194698091745550f, -0.994521895368273290f,
-  -0.992546151641321980f, -0.990268068741570250f,
-  -0.987688340595137660f, -0.984807753012208020f, -0.981627183447663980f,
-  -0.978147600733805690f, -0.974370064785235250f, -0.970295726275996470f,
-  -0.965925826289068200f, -0.961261695938318670f,
-  -0.956304755963035440f, -0.951056516295153530f, -0.945518575599316740f,
-  -0.939692620785908320f, -0.933580426497201740f, -0.927183854566787310f,
-  -0.920504853452440150f, -0.913545457642600760f,
-  -0.906307787036649940f, -0.898794046299167040f, -0.891006524188367790f,
-  -0.882947592858926770f, -0.874619707139395740f, -0.866025403784438710f,
-  -0.857167300702112220f, -0.848048096156425960f,
-  -0.838670567945424160f, -0.829037572555041620f, -0.819152044288991580f,
-  -0.809016994374947340f, -0.798635510047292940f, -0.788010753606721900f,
-  -0.777145961456970680f, -0.766044443118977900f,
-  -0.754709580222772010f, -0.743144825477394130f, -0.731353701619170460f,
-  -0.719339800338651300f, -0.707106781186547460f, -0.694658370458997030f,
-  -0.681998360062498370f, -0.669130606358858240f,
-  -0.656059028990507500f, -0.642787609686539360f, -0.629320391049837280f,
-  -0.615661475325658290f, -0.601815023152048380f, -0.587785252292473030f,
-  -0.573576436351045830f, -0.559192903470746680f,
-  -0.544639035015027080f, -0.529919264233204790f, -0.515038074910054270f,
-  -0.499999999999999780f, -0.484809620246337000f, -0.469471562785890530f,
-  -0.453990499739546750f, -0.438371146789077510f,
-  -0.422618261740699330f, -0.406736643075800100f, -0.390731128489273600f,
-  -0.374606593415912070f, -0.358367949545300270f, -0.342020143325668710f,
-  -0.325568154457156420f, -0.309016994374947340f,
-  -0.292371704722736660f, -0.275637355816999050f, -0.258819045102520850f,
-  -0.241921895599667790f, -0.224951054343864810f, -0.207911690817759120f,
-  -0.190808995376544800f, -0.173648177666930300f,
-  -0.156434465040231040f, -0.139173100960065350f, -0.121869343405147370f,
-  -0.104528463267653330f, -0.087155742747658235f, -0.069756473744125330f,
-  -0.052335956242943620f, -0.034899496702500733f,
-  -0.017452406437283477f, 0.000000000000000061f, 0.017452406437283376f,
-  0.034899496702501080f, 0.052335956242943966f, 0.069756473744125455f,
-  0.087155742747658138f, 0.104528463267653460f,
-  0.121869343405147490f, 0.139173100960065690f, 0.156434465040230920f,
-  0.173648177666930410f, 0.190808995376544920f, 0.207911690817759450f,
-  0.224951054343864920f, 0.241921895599667900f,
-  0.258819045102520740f, 0.275637355816999160f, 0.292371704722736770f,
-  0.309016994374947450f, 0.325568154457156760f, 0.342020143325668820f,
-  0.358367949545300380f, 0.374606593415911960f,
-  0.390731128489273940f, 0.406736643075800210f, 0.422618261740699440f,
-  0.438371146789077460f, 0.453990499739546860f, 0.469471562785890860f,
-  0.484809620246337110f, 0.500000000000000110f,
-  0.515038074910054380f, 0.529919264233204900f, 0.544639035015027200f,
-  0.559192903470746790f, 0.573576436351046050f, 0.587785252292473140f,
-  0.601815023152048270f, 0.615661475325658290f,
-  0.629320391049837500f, 0.642787609686539360f, 0.656059028990507280f,
-  0.669130606358858240f, 0.681998360062498480f, 0.694658370458997370f,
-  0.707106781186547570f, 0.719339800338651190f,
-  0.731353701619170570f, 0.743144825477394240f, 0.754709580222772010f,
-  0.766044443118978010f, 0.777145961456970900f, 0.788010753606722010f,
-  0.798635510047292830f, 0.809016994374947450f,
-  0.819152044288991800f, 0.829037572555041620f, 0.838670567945424050f,
-  0.848048096156425960f, 0.857167300702112330f, 0.866025403784438710f,
-  0.874619707139395740f, 0.882947592858926990f,
-  0.891006524188367900f, 0.898794046299167040f, 0.906307787036649940f,
-  0.913545457642600870f, 0.920504853452440370f, 0.927183854566787420f,
-  0.933580426497201740f, 0.939692620785908430f,
-  0.945518575599316850f, 0.951056516295153530f, 0.956304755963035440f,
-  0.961261695938318890f, 0.965925826289068310f, 0.970295726275996470f,
-  0.974370064785235250f, 0.978147600733805690f,
-  0.981627183447663980f, 0.984807753012208020f, 0.987688340595137770f,
-  0.990268068741570360f, 0.992546151641321980f, 0.994521895368273290f,
-  0.996194698091745550f, 0.997564050259824200f,
-  0.998629534754573830f, 0.999390827019095760f, 0.999847695156391270f,
-  1.000000000000000000f, 0.999847695156391270f, 0.999390827019095760f,
-  0.998629534754573830f, 0.997564050259824200f,
-  0.996194698091745550f, 0.994521895368273290f, 0.992546151641321980f,
-  0.990268068741570360f, 0.987688340595137770f, 0.984807753012208020f,
-  0.981627183447663980f, 0.978147600733805690f,
-  0.974370064785235250f, 0.970295726275996470f, 0.965925826289068310f,
-  0.961261695938318890f, 0.956304755963035440f, 0.951056516295153530f,
-  0.945518575599316850f, 0.939692620785908430f,
-  0.933580426497201740f, 0.927183854566787420f, 0.920504853452440370f,
-  0.913545457642600870f, 0.906307787036649940f, 0.898794046299167040f,
-  0.891006524188367900f, 0.882947592858926990f,
-  0.874619707139395740f, 0.866025403784438710f, 0.857167300702112330f,
-  0.848048096156425960f, 0.838670567945424050f, 0.829037572555041620f,
-  0.819152044288991800f, 0.809016994374947450f,
-  0.798635510047292830f, 0.788010753606722010f, 0.777145961456970900f,
-  0.766044443118978010f, 0.754709580222772010f, 0.743144825477394240f,
-  0.731353701619170570f, 0.719339800338651190f,
-  0.707106781186547570f, 0.694658370458997370f, 0.681998360062498480f,
-  0.669130606358858240f, 0.656059028990507280f, 0.642787609686539360f,
-  0.629320391049837500f, 0.615661475325658290f,
-  0.601815023152048270f, 0.587785252292473140f, 0.573576436351046050f,
-  0.559192903470746790f, 0.544639035015027200f, 0.529919264233204900f,
-  0.515038074910054380f, 0.500000000000000110f,
-  0.484809620246337110f, 0.469471562785890860f, 0.453990499739546860f,
-  0.438371146789077460f, 0.422618261740699440f, 0.406736643075800210f,
-  0.390731128489273940f, 0.374606593415911960f,
-  0.358367949545300380f, 0.342020143325668820f, 0.325568154457156760f,
-  0.309016994374947450f, 0.292371704722736770f, 0.275637355816999160f,
-  0.258819045102520740f, 0.241921895599667900f,
-  0.224951054343864920f, 0.207911690817759450f, 0.190808995376544920f,
-  0.173648177666930410f, 0.156434465040230920f, 0.139173100960065690f,
-  0.121869343405147490f, 0.104528463267653460f,
-  0.087155742747658138f, 0.069756473744125455f, 0.052335956242943966f,
-  0.034899496702501080f, 0.017452406437283376f, 0.000000000000000061f,
-  -0.017452406437283477f, -0.034899496702500733f,
-  -0.052335956242943620f, -0.069756473744125330f, -0.087155742747658235f,
-  -0.104528463267653330f, -0.121869343405147370f, -0.139173100960065350f,
-  -0.156434465040231040f, -0.173648177666930300f,
-  -0.190808995376544800f, -0.207911690817759120f, -0.224951054343864810f,
-  -0.241921895599667790f, -0.258819045102520850f, -0.275637355816999050f,
-  -0.292371704722736660f, -0.309016994374947340f,
-  -0.325568154457156420f, -0.342020143325668710f, -0.358367949545300270f,
-  -0.374606593415912070f, -0.390731128489273600f, -0.406736643075800100f,
-  -0.422618261740699330f, -0.438371146789077510f,
-  -0.453990499739546750f, -0.469471562785890530f, -0.484809620246337000f,
-  -0.499999999999999780f, -0.515038074910054270f, -0.529919264233204790f,
-  -0.544639035015027080f, -0.559192903470746680f,
-  -0.573576436351045830f, -0.587785252292473030f, -0.601815023152048380f,
-  -0.615661475325658290f, -0.629320391049837280f, -0.642787609686539360f,
-  -0.656059028990507500f, -0.669130606358858240f,
-  -0.681998360062498370f, -0.694658370458997030f, -0.707106781186547460f,
-  -0.719339800338651300f, -0.731353701619170460f, -0.743144825477394130f,
-  -0.754709580222772010f, -0.766044443118977900f,
-  -0.777145961456970680f, -0.788010753606721900f, -0.798635510047292940f,
-  -0.809016994374947340f, -0.819152044288991580f, -0.829037572555041620f,
-  -0.838670567945424160f, -0.848048096156425960f,
-  -0.857167300702112220f, -0.866025403784438710f, -0.874619707139395740f,
-  -0.882947592858926770f, -0.891006524188367790f, -0.898794046299167040f,
-  -0.906307787036649940f, -0.913545457642600760f,
-  -0.920504853452440150f, -0.927183854566787310f, -0.933580426497201740f,
-  -0.939692620785908320f, -0.945518575599316740f, -0.951056516295153530f,
-  -0.956304755963035440f, -0.961261695938318670f,
-  -0.965925826289068200f, -0.970295726275996470f, -0.974370064785235250f,
-  -0.978147600733805690f, -0.981627183447663980f, -0.984807753012208020f,
-  -0.987688340595137660f, -0.990268068741570250f,
-  -0.992546151641321980f, -0.994521895368273290f, -0.996194698091745550f,
-  -0.997564050259824200f, -0.998629534754573830f, -0.999390827019095760f,
-  -0.999847695156391270f, -1.000000000000000000f
-};
-
-/**    
-* \par    
-* Sine Table is generated from following loop    
-* 
for(i = 0; i < 360; i++)    
-* {    
-*    sinTable[i]= sin((i-180) * PI/180.0);    
-* } 
    
-*/
-
-
-static const float32_t sinTable[360] = {
-  -0.017452406437283439f, -0.034899496702500699f, -0.052335956242943807f,
-  -0.069756473744125524f, -0.087155742747658638f, -0.104528463267653730f,
-  -0.121869343405147550f, -0.139173100960065740f,
-  -0.156434465040230980f, -0.173648177666930280f, -0.190808995376544970f,
-  -0.207911690817759310f, -0.224951054343864780f, -0.241921895599667730f,
-  -0.258819045102521020f, -0.275637355816999660f,
-  -0.292371704722737050f, -0.309016994374947510f, -0.325568154457156980f,
-  -0.342020143325668880f, -0.358367949545300210f, -0.374606593415912240f,
-  -0.390731128489274160f, -0.406736643075800430f,
-  -0.422618261740699500f, -0.438371146789077290f, -0.453990499739546860f,
-  -0.469471562785891080f, -0.484809620246337170f, -0.499999999999999940f,
-  -0.515038074910054380f, -0.529919264233204900f,
-  -0.544639035015026860f, -0.559192903470746900f, -0.573576436351046380f,
-  -0.587785252292473250f, -0.601815023152048160f, -0.615661475325658400f,
-  -0.629320391049837720f, -0.642787609686539470f,
-  -0.656059028990507280f, -0.669130606358858350f, -0.681998360062498590f,
-  -0.694658370458997140f, -0.707106781186547570f, -0.719339800338651410f,
-  -0.731353701619170570f, -0.743144825477394240f,
-  -0.754709580222771790f, -0.766044443118978010f, -0.777145961456971010f,
-  -0.788010753606722010f, -0.798635510047292720f, -0.809016994374947450f,
-  -0.819152044288992020f, -0.829037572555041740f,
-  -0.838670567945424050f, -0.848048096156426070f, -0.857167300702112330f,
-  -0.866025403784438710f, -0.874619707139395850f, -0.882947592858927100f,
-  -0.891006524188367900f, -0.898794046299166930f,
-  -0.906307787036650050f, -0.913545457642600980f, -0.920504853452440370f,
-  -0.927183854566787420f, -0.933580426497201740f, -0.939692620785908430f,
-  -0.945518575599316850f, -0.951056516295153640f,
-  -0.956304755963035550f, -0.961261695938318890f, -0.965925826289068310f,
-  -0.970295726275996470f, -0.974370064785235250f, -0.978147600733805690f,
-  -0.981627183447663980f, -0.984807753012208020f,
-  -0.987688340595137660f, -0.990268068741570360f, -0.992546151641322090f,
-  -0.994521895368273400f, -0.996194698091745550f, -0.997564050259824200f,
-  -0.998629534754573830f, -0.999390827019095760f,
-  -0.999847695156391270f, -1.000000000000000000f, -0.999847695156391270f,
-  -0.999390827019095760f, -0.998629534754573830f, -0.997564050259824200f,
-  -0.996194698091745550f, -0.994521895368273290f,
-  -0.992546151641321980f, -0.990268068741570250f, -0.987688340595137770f,
-  -0.984807753012208020f, -0.981627183447663980f, -0.978147600733805580f,
-  -0.974370064785235250f, -0.970295726275996470f,
-  -0.965925826289068310f, -0.961261695938318890f, -0.956304755963035440f,
-  -0.951056516295153530f, -0.945518575599316740f, -0.939692620785908320f,
-  -0.933580426497201740f, -0.927183854566787420f,
-  -0.920504853452440260f, -0.913545457642600870f, -0.906307787036649940f,
-  -0.898794046299167040f, -0.891006524188367790f, -0.882947592858926880f,
-  -0.874619707139395740f, -0.866025403784438600f,
-  -0.857167300702112220f, -0.848048096156426070f, -0.838670567945423940f,
-  -0.829037572555041740f, -0.819152044288991800f, -0.809016994374947450f,
-  -0.798635510047292830f, -0.788010753606722010f,
-  -0.777145961456970790f, -0.766044443118978010f, -0.754709580222772010f,
-  -0.743144825477394240f, -0.731353701619170460f, -0.719339800338651080f,
-  -0.707106781186547460f, -0.694658370458997250f,
-  -0.681998360062498480f, -0.669130606358858240f, -0.656059028990507160f,
-  -0.642787609686539250f, -0.629320391049837390f, -0.615661475325658180f,
-  -0.601815023152048270f, -0.587785252292473140f,
-  -0.573576436351046050f, -0.559192903470746900f, -0.544639035015027080f,
-  -0.529919264233204900f, -0.515038074910054160f, -0.499999999999999940f,
-  -0.484809620246337060f, -0.469471562785890810f,
-  -0.453990499739546750f, -0.438371146789077400f, -0.422618261740699440f,
-  -0.406736643075800150f, -0.390731128489273720f, -0.374606593415912010f,
-  -0.358367949545300270f, -0.342020143325668710f,
-  -0.325568154457156640f, -0.309016994374947400f, -0.292371704722736770f,
-  -0.275637355816999160f, -0.258819045102520740f, -0.241921895599667730f,
-  -0.224951054343865000f, -0.207911690817759310f,
-  -0.190808995376544800f, -0.173648177666930330f, -0.156434465040230870f,
-  -0.139173100960065440f, -0.121869343405147480f, -0.104528463267653460f,
-  -0.087155742747658166f, -0.069756473744125302f,
-  -0.052335956242943828f, -0.034899496702500969f, -0.017452406437283512f,
-  0.000000000000000000f, 0.017452406437283512f, 0.034899496702500969f,
-  0.052335956242943828f, 0.069756473744125302f,
-  0.087155742747658166f, 0.104528463267653460f, 0.121869343405147480f,
-  0.139173100960065440f, 0.156434465040230870f, 0.173648177666930330f,
-  0.190808995376544800f, 0.207911690817759310f,
-  0.224951054343865000f, 0.241921895599667730f, 0.258819045102520740f,
-  0.275637355816999160f, 0.292371704722736770f, 0.309016994374947400f,
-  0.325568154457156640f, 0.342020143325668710f,
-  0.358367949545300270f, 0.374606593415912010f, 0.390731128489273720f,
-  0.406736643075800150f, 0.422618261740699440f, 0.438371146789077400f,
-  0.453990499739546750f, 0.469471562785890810f,
-  0.484809620246337060f, 0.499999999999999940f, 0.515038074910054160f,
-  0.529919264233204900f, 0.544639035015027080f, 0.559192903470746900f,
-  0.573576436351046050f, 0.587785252292473140f,
-  0.601815023152048270f, 0.615661475325658180f, 0.629320391049837390f,
-  0.642787609686539250f, 0.656059028990507160f, 0.669130606358858240f,
-  0.681998360062498480f, 0.694658370458997250f,
-  0.707106781186547460f, 0.719339800338651080f, 0.731353701619170460f,
-  0.743144825477394240f, 0.754709580222772010f, 0.766044443118978010f,
-  0.777145961456970790f, 0.788010753606722010f,
-  0.798635510047292830f, 0.809016994374947450f, 0.819152044288991800f,
-  0.829037572555041740f, 0.838670567945423940f, 0.848048096156426070f,
-  0.857167300702112220f, 0.866025403784438600f,
-  0.874619707139395740f, 0.882947592858926880f, 0.891006524188367790f,
-  0.898794046299167040f, 0.906307787036649940f, 0.913545457642600870f,
-  0.920504853452440260f, 0.927183854566787420f,
-  0.933580426497201740f, 0.939692620785908320f, 0.945518575599316740f,
-  0.951056516295153530f, 0.956304755963035440f, 0.961261695938318890f,
-  0.965925826289068310f, 0.970295726275996470f,
-  0.974370064785235250f, 0.978147600733805580f, 0.981627183447663980f,
-  0.984807753012208020f, 0.987688340595137770f, 0.990268068741570250f,
-  0.992546151641321980f, 0.994521895368273290f,
-  0.996194698091745550f, 0.997564050259824200f, 0.998629534754573830f,
-  0.999390827019095760f, 0.999847695156391270f, 1.000000000000000000f,
-  0.999847695156391270f, 0.999390827019095760f,
-  0.998629534754573830f, 0.997564050259824200f, 0.996194698091745550f,
-  0.994521895368273400f, 0.992546151641322090f, 0.990268068741570360f,
-  0.987688340595137660f, 0.984807753012208020f,
-  0.981627183447663980f, 0.978147600733805690f, 0.974370064785235250f,
-  0.970295726275996470f, 0.965925826289068310f, 0.961261695938318890f,
-  0.956304755963035550f, 0.951056516295153640f,
-  0.945518575599316850f, 0.939692620785908430f, 0.933580426497201740f,
-  0.927183854566787420f, 0.920504853452440370f, 0.913545457642600980f,
-  0.906307787036650050f, 0.898794046299166930f,
-  0.891006524188367900f, 0.882947592858927100f, 0.874619707139395850f,
-  0.866025403784438710f, 0.857167300702112330f, 0.848048096156426070f,
-  0.838670567945424050f, 0.829037572555041740f,
-  0.819152044288992020f, 0.809016994374947450f, 0.798635510047292720f,
-  0.788010753606722010f, 0.777145961456971010f, 0.766044443118978010f,
-  0.754709580222771790f, 0.743144825477394240f,
-  0.731353701619170570f, 0.719339800338651410f, 0.707106781186547570f,
-  0.694658370458997140f, 0.681998360062498590f, 0.669130606358858350f,
-  0.656059028990507280f, 0.642787609686539470f,
-  0.629320391049837720f, 0.615661475325658400f, 0.601815023152048160f,
-  0.587785252292473250f, 0.573576436351046380f, 0.559192903470746900f,
-  0.544639035015026860f, 0.529919264233204900f,
-  0.515038074910054380f, 0.499999999999999940f, 0.484809620246337170f,
-  0.469471562785891080f, 0.453990499739546860f, 0.438371146789077290f,
-  0.422618261740699500f, 0.406736643075800430f,
-  0.390731128489274160f, 0.374606593415912240f, 0.358367949545300210f,
-  0.342020143325668880f, 0.325568154457156980f, 0.309016994374947510f,
-  0.292371704722737050f, 0.275637355816999660f,
-  0.258819045102521020f, 0.241921895599667730f, 0.224951054343864780f,
-  0.207911690817759310f, 0.190808995376544970f, 0.173648177666930280f,
-  0.156434465040230980f, 0.139173100960065740f,
-  0.121869343405147550f, 0.104528463267653730f, 0.087155742747658638f,
-  0.069756473744125524f, 0.052335956242943807f, 0.034899496702500699f,
-  0.017452406437283439f, 0.000000000000000122f
-};
-
-
-/**    
- * @brief  Floating-point sin_cos function.   
- * @param[in]  theta    input value in degrees    
- * @param[out] *pSinVal points to the processed sine output.    
- * @param[out] *pCosVal points to the processed cos output.    
- * @return none.   
- */
-
-
-void arm_sin_cos_f32(
-  float32_t theta,
-  float32_t * pSinVal,
-  float32_t * pCosVal)
-{
-  int32_t i;                                     /* Index for reading nearwst output values */
-  float32_t x1 = -179.0f;                        /* Initial input value */
-  float32_t y0, y1;                              /* nearest output values */
-  float32_t y2, y3;
-  float32_t fract;                               /* fractional part of input */
-
-  /* Calculation of fractional part */
-  if(theta > 0.0f)
-  {
-    fract = theta - (float32_t) ((int32_t) theta);
-  }
-  else
-  {
-    fract = (theta - (float32_t) ((int32_t) theta)) + 1.0f;
-  }
-
-  /* index calculation for reading nearest output values */
-  i = (uint32_t) (theta - x1);
-
-  /* Checking min and max index of table */
-  if(i < 0)
-  {
-    i = 0;
-  }
-  else if(i >= 359)
-  {
-    i = 358;
-  }
-
-  /* reading nearest sine output values */
-  y0 = sinTable[i];
-  y1 = sinTable[i + 1u];
-
-  /* reading nearest cosine output values */
-  y2 = cosTable[i];
-  y3 = cosTable[i + 1u];
-
-  y1 = y1 - y0;
-  y3 = y3 - y2;
-
-  y1 = fract * y1;
-  y3 = fract * y3;
-
-  /* Calculation of sine value */
-  *pSinVal = y0 + y1;
-
-  /* Calculation of cosine value */
-  *pCosVal = y2 + y3;
-
-}
-
-/**    
- * @} end of SinCos group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_q31.c
deleted file mode 100644
index e4c8373672..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_q31.c
+++ /dev/null
@@ -1,324 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_sin_cos_q31.c    
-*    
-* Description:	Cosine & Sine calculation for Q31 values.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupController    
- */
-
- /**    
- * @addtogroup SinCos    
- * @{    
- */
-
-/**    
-* \par    
-* Sine Table is generated from following loop    
-* 
for(i = 0; i < 360; i++)    
-* {    
-*    sinTable[i]= sin((i-180) * PI/180.0);    
-* } 
   
-* Convert above coefficients to fixed point 1.31 format.    
-*/
-
-static const int32_t sinTableQ31[360] = {
-
-  0x0, 0xfdc41e9b, 0xfb8869ce, 0xf94d0e2e, 0xf7123849, 0xf4d814a4, 0xf29ecfb2,
-  0xf06695da,
-  0xee2f9369, 0xebf9f498, 0xe9c5e582, 0xe7939223, 0xe5632654, 0xe334cdc9,
-  0xe108b40d, 0xdedf047d,
-  0xdcb7ea46, 0xda939061, 0xd8722192, 0xd653c860, 0xd438af17, 0xd220ffc0,
-  0xd00ce422, 0xcdfc85bb,
-  0xcbf00dbe, 0xc9e7a512, 0xc7e3744b, 0xc5e3a3a9, 0xc3e85b18, 0xc1f1c224,
-  0xc0000000, 0xbe133b7c,
-  0xbc2b9b05, 0xba4944a2, 0xb86c5df0, 0xb6950c1e, 0xb4c373ee, 0xb2f7b9af,
-  0xb1320139, 0xaf726def,
-  0xadb922b7, 0xac0641fb, 0xaa59eda4, 0xa8b4471a, 0xa7156f3c, 0xa57d8666,
-  0xa3ecac65, 0xa263007d,
-  0xa0e0a15f, 0x9f65ad2d, 0x9df24175, 0x9c867b2c, 0x9b2276b0, 0x99c64fc5,
-  0x98722192, 0x9726069c,
-  0x95e218c9, 0x94a6715d, 0x937328f5, 0x92485786, 0x9126145f, 0x900c7621,
-  0x8efb92c2, 0x8df37f8b,
-  0x8cf45113, 0x8bfe1b3f, 0x8b10f144, 0x8a2ce59f, 0x89520a1a, 0x88806fc4,
-  0x87b826f7, 0x86f93f50,
-  0x8643c7b3, 0x8597ce46, 0x84f56073, 0x845c8ae3, 0x83cd5982, 0x8347d77b,
-  0x82cc0f36, 0x825a0a5b,
-  0x81f1d1ce, 0x81936daf, 0x813ee55b, 0x80f43f69, 0x80b381ac, 0x807cb130,
-  0x804fd23a, 0x802ce84c,
-  0x8013f61d, 0x8004fda0, 0x80000000, 0x8004fda0, 0x8013f61d, 0x802ce84c,
-  0x804fd23a, 0x807cb130,
-  0x80b381ac, 0x80f43f69, 0x813ee55b, 0x81936daf, 0x81f1d1ce, 0x825a0a5b,
-  0x82cc0f36, 0x8347d77b,
-  0x83cd5982, 0x845c8ae3, 0x84f56073, 0x8597ce46, 0x8643c7b3, 0x86f93f50,
-  0x87b826f7, 0x88806fc4,
-  0x89520a1a, 0x8a2ce59f, 0x8b10f144, 0x8bfe1b3f, 0x8cf45113, 0x8df37f8b,
-  0x8efb92c2, 0x900c7621,
-  0x9126145f, 0x92485786, 0x937328f5, 0x94a6715d, 0x95e218c9, 0x9726069c,
-  0x98722192, 0x99c64fc5,
-  0x9b2276b0, 0x9c867b2c, 0x9df24175, 0x9f65ad2d, 0xa0e0a15f, 0xa263007d,
-  0xa3ecac65, 0xa57d8666,
-  0xa7156f3c, 0xa8b4471a, 0xaa59eda4, 0xac0641fb, 0xadb922b7, 0xaf726def,
-  0xb1320139, 0xb2f7b9af,
-  0xb4c373ee, 0xb6950c1e, 0xb86c5df0, 0xba4944a2, 0xbc2b9b05, 0xbe133b7c,
-  0xc0000000, 0xc1f1c224,
-  0xc3e85b18, 0xc5e3a3a9, 0xc7e3744b, 0xc9e7a512, 0xcbf00dbe, 0xcdfc85bb,
-  0xd00ce422, 0xd220ffc0,
-  0xd438af17, 0xd653c860, 0xd8722192, 0xda939061, 0xdcb7ea46, 0xdedf047d,
-  0xe108b40d, 0xe334cdc9,
-  0xe5632654, 0xe7939223, 0xe9c5e582, 0xebf9f498, 0xee2f9369, 0xf06695da,
-  0xf29ecfb2, 0xf4d814a4,
-  0xf7123849, 0xf94d0e2e, 0xfb8869ce, 0xfdc41e9b, 0x0, 0x23be165, 0x4779632,
-  0x6b2f1d2,
-  0x8edc7b7, 0xb27eb5c, 0xd61304e, 0xf996a26, 0x11d06c97, 0x14060b68,
-  0x163a1a7e, 0x186c6ddd,
-  0x1a9cd9ac, 0x1ccb3237, 0x1ef74bf3, 0x2120fb83, 0x234815ba, 0x256c6f9f,
-  0x278dde6e, 0x29ac37a0,
-  0x2bc750e9, 0x2ddf0040, 0x2ff31bde, 0x32037a45, 0x340ff242, 0x36185aee,
-  0x381c8bb5, 0x3a1c5c57,
-  0x3c17a4e8, 0x3e0e3ddc, 0x40000000, 0x41ecc484, 0x43d464fb, 0x45b6bb5e,
-  0x4793a210, 0x496af3e2,
-  0x4b3c8c12, 0x4d084651, 0x4ecdfec7, 0x508d9211, 0x5246dd49, 0x53f9be05,
-  0x55a6125c, 0x574bb8e6,
-  0x58ea90c4, 0x5a82799a, 0x5c13539b, 0x5d9cff83, 0x5f1f5ea1, 0x609a52d3,
-  0x620dbe8b, 0x637984d4,
-  0x64dd8950, 0x6639b03b, 0x678dde6e, 0x68d9f964, 0x6a1de737, 0x6b598ea3,
-  0x6c8cd70b, 0x6db7a87a,
-  0x6ed9eba1, 0x6ff389df, 0x71046d3e, 0x720c8075, 0x730baeed, 0x7401e4c1,
-  0x74ef0ebc, 0x75d31a61,
-  0x76adf5e6, 0x777f903c, 0x7847d909, 0x7906c0b0, 0x79bc384d, 0x7a6831ba,
-  0x7b0a9f8d, 0x7ba3751d,
-  0x7c32a67e, 0x7cb82885, 0x7d33f0ca, 0x7da5f5a5, 0x7e0e2e32, 0x7e6c9251,
-  0x7ec11aa5, 0x7f0bc097,
-  0x7f4c7e54, 0x7f834ed0, 0x7fb02dc6, 0x7fd317b4, 0x7fec09e3, 0x7ffb0260,
-  0x7fffffff, 0x7ffb0260,
-  0x7fec09e3, 0x7fd317b4, 0x7fb02dc6, 0x7f834ed0, 0x7f4c7e54, 0x7f0bc097,
-  0x7ec11aa5, 0x7e6c9251,
-  0x7e0e2e32, 0x7da5f5a5, 0x7d33f0ca, 0x7cb82885, 0x7c32a67e, 0x7ba3751d,
-  0x7b0a9f8d, 0x7a6831ba,
-  0x79bc384d, 0x7906c0b0, 0x7847d909, 0x777f903c, 0x76adf5e6, 0x75d31a61,
-  0x74ef0ebc, 0x7401e4c1,
-  0x730baeed, 0x720c8075, 0x71046d3e, 0x6ff389df, 0x6ed9eba1, 0x6db7a87a,
-  0x6c8cd70b, 0x6b598ea3,
-  0x6a1de737, 0x68d9f964, 0x678dde6e, 0x6639b03b, 0x64dd8950, 0x637984d4,
-  0x620dbe8b, 0x609a52d3,
-  0x5f1f5ea1, 0x5d9cff83, 0x5c13539b, 0x5a82799a, 0x58ea90c4, 0x574bb8e6,
-  0x55a6125c, 0x53f9be05,
-  0x5246dd49, 0x508d9211, 0x4ecdfec7, 0x4d084651, 0x4b3c8c12, 0x496af3e2,
-  0x4793a210, 0x45b6bb5e,
-  0x43d464fb, 0x41ecc484, 0x40000000, 0x3e0e3ddc, 0x3c17a4e8, 0x3a1c5c57,
-  0x381c8bb5, 0x36185aee,
-  0x340ff242, 0x32037a45, 0x2ff31bde, 0x2ddf0040, 0x2bc750e9, 0x29ac37a0,
-  0x278dde6e, 0x256c6f9f,
-  0x234815ba, 0x2120fb83, 0x1ef74bf3, 0x1ccb3237, 0x1a9cd9ac, 0x186c6ddd,
-  0x163a1a7e, 0x14060b68,
-  0x11d06c97, 0xf996a26, 0xd61304e, 0xb27eb5c, 0x8edc7b7, 0x6b2f1d2,
-  0x4779632, 0x23be165,
-
-
-};
-
-/**    
-* \par    
-* Cosine Table is generated from following loop    
-* 
for(i = 0; i < 360; i++)    
-* {    
-*    cosTable[i]= cos((i-180) * PI/180.0);    
-* } 
   
-* \par    
-* Convert above coefficients to fixed point 1.31 format.    
-*/
-static const int32_t cosTableQ31[360] = {
-  0x80000000, 0x8004fda0, 0x8013f61d, 0x802ce84c, 0x804fd23a, 0x807cb130,
-  0x80b381ac, 0x80f43f69,
-  0x813ee55b, 0x81936daf, 0x81f1d1ce, 0x825a0a5b, 0x82cc0f36, 0x8347d77b,
-  0x83cd5982, 0x845c8ae3,
-  0x84f56073, 0x8597ce46, 0x8643c7b3, 0x86f93f50, 0x87b826f7, 0x88806fc4,
-  0x89520a1a, 0x8a2ce59f,
-  0x8b10f144, 0x8bfe1b3f, 0x8cf45113, 0x8df37f8b, 0x8efb92c2, 0x900c7621,
-  0x9126145f, 0x92485786,
-  0x937328f5, 0x94a6715d, 0x95e218c9, 0x9726069c, 0x98722192, 0x99c64fc5,
-  0x9b2276b0, 0x9c867b2c,
-  0x9df24175, 0x9f65ad2d, 0xa0e0a15f, 0xa263007d, 0xa3ecac65, 0xa57d8666,
-  0xa7156f3c, 0xa8b4471a,
-  0xaa59eda4, 0xac0641fb, 0xadb922b7, 0xaf726def, 0xb1320139, 0xb2f7b9af,
-  0xb4c373ee, 0xb6950c1e,
-  0xb86c5df0, 0xba4944a2, 0xbc2b9b05, 0xbe133b7c, 0xc0000000, 0xc1f1c224,
-  0xc3e85b18, 0xc5e3a3a9,
-  0xc7e3744b, 0xc9e7a512, 0xcbf00dbe, 0xcdfc85bb, 0xd00ce422, 0xd220ffc0,
-  0xd438af17, 0xd653c860,
-  0xd8722192, 0xda939061, 0xdcb7ea46, 0xdedf047d, 0xe108b40d, 0xe334cdc9,
-  0xe5632654, 0xe7939223,
-  0xe9c5e582, 0xebf9f498, 0xee2f9369, 0xf06695da, 0xf29ecfb2, 0xf4d814a4,
-  0xf7123849, 0xf94d0e2e,
-  0xfb8869ce, 0xfdc41e9b, 0x0, 0x23be165, 0x4779632, 0x6b2f1d2, 0x8edc7b7,
-  0xb27eb5c,
-  0xd61304e, 0xf996a26, 0x11d06c97, 0x14060b68, 0x163a1a7e, 0x186c6ddd,
-  0x1a9cd9ac, 0x1ccb3237,
-  0x1ef74bf3, 0x2120fb83, 0x234815ba, 0x256c6f9f, 0x278dde6e, 0x29ac37a0,
-  0x2bc750e9, 0x2ddf0040,
-  0x2ff31bde, 0x32037a45, 0x340ff242, 0x36185aee, 0x381c8bb5, 0x3a1c5c57,
-  0x3c17a4e8, 0x3e0e3ddc,
-  0x40000000, 0x41ecc484, 0x43d464fb, 0x45b6bb5e, 0x4793a210, 0x496af3e2,
-  0x4b3c8c12, 0x4d084651,
-  0x4ecdfec7, 0x508d9211, 0x5246dd49, 0x53f9be05, 0x55a6125c, 0x574bb8e6,
-  0x58ea90c4, 0x5a82799a,
-  0x5c13539b, 0x5d9cff83, 0x5f1f5ea1, 0x609a52d3, 0x620dbe8b, 0x637984d4,
-  0x64dd8950, 0x6639b03b,
-  0x678dde6e, 0x68d9f964, 0x6a1de737, 0x6b598ea3, 0x6c8cd70b, 0x6db7a87a,
-  0x6ed9eba1, 0x6ff389df,
-  0x71046d3e, 0x720c8075, 0x730baeed, 0x7401e4c1, 0x74ef0ebc, 0x75d31a61,
-  0x76adf5e6, 0x777f903c,
-  0x7847d909, 0x7906c0b0, 0x79bc384d, 0x7a6831ba, 0x7b0a9f8d, 0x7ba3751d,
-  0x7c32a67e, 0x7cb82885,
-  0x7d33f0ca, 0x7da5f5a5, 0x7e0e2e32, 0x7e6c9251, 0x7ec11aa5, 0x7f0bc097,
-  0x7f4c7e54, 0x7f834ed0,
-  0x7fb02dc6, 0x7fd317b4, 0x7fec09e3, 0x7ffb0260, 0x7fffffff, 0x7ffb0260,
-  0x7fec09e3, 0x7fd317b4,
-  0x7fb02dc6, 0x7f834ed0, 0x7f4c7e54, 0x7f0bc097, 0x7ec11aa5, 0x7e6c9251,
-  0x7e0e2e32, 0x7da5f5a5,
-  0x7d33f0ca, 0x7cb82885, 0x7c32a67e, 0x7ba3751d, 0x7b0a9f8d, 0x7a6831ba,
-  0x79bc384d, 0x7906c0b0,
-  0x7847d909, 0x777f903c, 0x76adf5e6, 0x75d31a61, 0x74ef0ebc, 0x7401e4c1,
-  0x730baeed, 0x720c8075,
-  0x71046d3e, 0x6ff389df, 0x6ed9eba1, 0x6db7a87a, 0x6c8cd70b, 0x6b598ea3,
-  0x6a1de737, 0x68d9f964,
-  0x678dde6e, 0x6639b03b, 0x64dd8950, 0x637984d4, 0x620dbe8b, 0x609a52d3,
-  0x5f1f5ea1, 0x5d9cff83,
-  0x5c13539b, 0x5a82799a, 0x58ea90c4, 0x574bb8e6, 0x55a6125c, 0x53f9be05,
-  0x5246dd49, 0x508d9211,
-  0x4ecdfec7, 0x4d084651, 0x4b3c8c12, 0x496af3e2, 0x4793a210, 0x45b6bb5e,
-  0x43d464fb, 0x41ecc484,
-  0x40000000, 0x3e0e3ddc, 0x3c17a4e8, 0x3a1c5c57, 0x381c8bb5, 0x36185aee,
-  0x340ff242, 0x32037a45,
-  0x2ff31bde, 0x2ddf0040, 0x2bc750e9, 0x29ac37a0, 0x278dde6e, 0x256c6f9f,
-  0x234815ba, 0x2120fb83,
-  0x1ef74bf3, 0x1ccb3237, 0x1a9cd9ac, 0x186c6ddd, 0x163a1a7e, 0x14060b68,
-  0x11d06c97, 0xf996a26,
-  0xd61304e, 0xb27eb5c, 0x8edc7b7, 0x6b2f1d2, 0x4779632, 0x23be165, 0x0,
-  0xfdc41e9b,
-  0xfb8869ce, 0xf94d0e2e, 0xf7123849, 0xf4d814a4, 0xf29ecfb2, 0xf06695da,
-  0xee2f9369, 0xebf9f498,
-  0xe9c5e582, 0xe7939223, 0xe5632654, 0xe334cdc9, 0xe108b40d, 0xdedf047d,
-  0xdcb7ea46, 0xda939061,
-  0xd8722192, 0xd653c860, 0xd438af17, 0xd220ffc0, 0xd00ce422, 0xcdfc85bb,
-  0xcbf00dbe, 0xc9e7a512,
-  0xc7e3744b, 0xc5e3a3a9, 0xc3e85b18, 0xc1f1c224, 0xc0000000, 0xbe133b7c,
-  0xbc2b9b05, 0xba4944a2,
-  0xb86c5df0, 0xb6950c1e, 0xb4c373ee, 0xb2f7b9af, 0xb1320139, 0xaf726def,
-  0xadb922b7, 0xac0641fb,
-  0xaa59eda4, 0xa8b4471a, 0xa7156f3c, 0xa57d8666, 0xa3ecac65, 0xa263007d,
-  0xa0e0a15f, 0x9f65ad2d,
-  0x9df24175, 0x9c867b2c, 0x9b2276b0, 0x99c64fc5, 0x98722192, 0x9726069c,
-  0x95e218c9, 0x94a6715d,
-  0x937328f5, 0x92485786, 0x9126145f, 0x900c7621, 0x8efb92c2, 0x8df37f8b,
-  0x8cf45113, 0x8bfe1b3f,
-  0x8b10f144, 0x8a2ce59f, 0x89520a1a, 0x88806fc4, 0x87b826f7, 0x86f93f50,
-  0x8643c7b3, 0x8597ce46,
-  0x84f56073, 0x845c8ae3, 0x83cd5982, 0x8347d77b, 0x82cc0f36, 0x825a0a5b,
-  0x81f1d1ce, 0x81936daf,
-  0x813ee55b, 0x80f43f69, 0x80b381ac, 0x807cb130, 0x804fd23a, 0x802ce84c,
-  0x8013f61d, 0x8004fda0,
-
-};
-
-
-/**    
- * @brief  Q31 sin_cos function.   
- * @param[in]  theta    scaled input value in degrees    
- * @param[out] *pSinVal points to the processed sine output.    
- * @param[out] *pCosVal points to the processed cosine output.    
- * @return none.   
- *    
- * The Q31 input value is in the range [-1 0.999999] and is mapped to a degree value in the range [-180 179].   
- *    
- */
-
-
-void arm_sin_cos_q31(
-  q31_t theta,
-  q31_t * pSinVal,
-  q31_t * pCosVal)
-{
-  q31_t x0;                                      /* Nearest input value */
-  q31_t y0, y1;                                  /* Nearest output values */
-  q31_t xSpacing = INPUT_SPACING;                /* Spaing between inputs */
-  int32_t i;                                     /* Index */
-  q31_t oneByXSpacing;                           /* 1/ xSpacing value */
-  q31_t out;                                     /* temporary variable */
-  uint32_t sign_bits;                            /* No.of sign bits */
-  uint32_t firstX = 0x80000000;                  /* First X value */
-
-  /* Calculation of index */
-  i = ((uint32_t) theta - firstX) / (uint32_t) xSpacing;
-
-  /* Checking min and max index of table */
-  if(i < 0)
-  {
-    i = 0;
-  }
-  else if(i >= 359)
-  {
-    i = 358;
-  }
-
-  /* Calculation of first nearest input value */
-  x0 = (q31_t) firstX + ((q31_t) i * xSpacing);
-
-  /* Reading nearest sine output values from table */
-  y0 = sinTableQ31[i];
-  y1 = sinTableQ31[i + 1u];
-
-  /* Calculation of 1/(x1-x0) */
-  /* (x1-x0) is xSpacing which is fixed value */
-  sign_bits = 8u;
-  oneByXSpacing = 0x5A000000;
-
-  /* Calculation of (theta - x0)/(x1-x0) */
-  out =
-    (((q31_t) (((q63_t) (theta - x0) * oneByXSpacing) >> 32)) << sign_bits);
-
-  /* Calculation of y0 + (y1 - y0) * ((theta - x0)/(x1-x0)) */
-  *pSinVal = __QADD(y0, ((q31_t) (((q63_t) (y1 - y0) * out) >> 30)));
-
-  /* Reading nearest cosine output values from table */
-  y0 = cosTableQ31[i];
-  y1 = cosTableQ31[i + 1u];
-
-  /* Calculation of y0 + (y1 - y0) * ((theta - x0)/(x1-x0)) */
-  *pCosVal = __QADD(y0, ((q31_t) (((q63_t) (y1 - y0) * out) >> 30)));
-
-}
-
-/**    
- * @} end of SinCos group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_f32.c
deleted file mode 100644
index b04aa02f54..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_f32.c
+++ /dev/null
@@ -1,280 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_cos_f32.c    
-*    
-* Description:	Fast cosine calculation for floating-point values.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-/**    
- * @ingroup groupFastMath    
- */
-
-/**    
- * @defgroup cos Cosine    
- *    
- * Computes the trigonometric cosine function using a combination of table lookup   
- * and cubic interpolation.  There are separate functions for   
- * Q15, Q31, and floating-point data types.   
- * The input to the floating-point version is in radians while the   
- * fixed-point Q15 and Q31 have a scaled input with the range   
- * [0 +0.9999] mapping to [0 2*pi), Where range excludes 2*pi.   
- *   
- * The implementation is based on table lookup using 256 values together with cubic interpolation.   
- * The steps used are:   
- *  -# Calculation of the nearest integer table index   
- *  -# Fetch the four table values a, b, c, and d     
- *  -# Compute the fractional portion (fract) of the table index.   
- *  -# Calculation of wa, wb, wc, wd    
- *  -# The final result equals a*wa + b*wb + c*wc + d*wd   
- *   
- * where   
- * 
    
- *    a=Table[index-1];    
- *    b=Table[index+0];    
- *    c=Table[index+1];    
- *    d=Table[index+2];    
- * 
   
- * and   
- * 
    
- *    wa=-(1/6)*fract.^3 + (1/2)*fract.^2 - (1/3)*fract;    
- *    wb=(1/2)*fract.^3 - fract.^2 - (1/2)*fract + 1;    
- *    wc=-(1/2)*fract.^3+(1/2)*fract.^2+fract;    
- *    wd=(1/6)*fract.^3 - (1/6)*fract;    
- * 
    
- */
-
- /**    
- * @addtogroup cos    
- * @{    
- */
-
-
-/**    
-* \par    
-* Example code for Generation of Cos Table:   
-* tableSize = 256;    
-* 
for(n = -1; n < (tableSize + 2); n++)    
-* {    
-*	cosTable[n+1]= cos(2*pi*n/tableSize);    
-* } 
    
-* where pi value is  3.14159265358979    
-*/
-
-static const float32_t cosTable[260] = {
-  0.999698817729949950f, 1.000000000000000000f, 0.999698817729949950f,
-  0.998795449733734130f, 0.997290432453155520f, 0.995184719562530520f,
-  0.992479562759399410f, 0.989176511764526370f,
-  0.985277652740478520f, 0.980785250663757320f, 0.975702106952667240f,
-  0.970031261444091800f, 0.963776051998138430f, 0.956940352916717530f,
-  0.949528157711029050f, 0.941544055938720700f,
-  0.932992815971374510f, 0.923879504203796390f, 0.914209783077239990f,
-  0.903989315032958980f, 0.893224298954010010f, 0.881921291351318360f,
-  0.870086967945098880f, 0.857728600502014160f,
-  0.844853579998016360f, 0.831469595432281490f, 0.817584812641143800f,
-  0.803207516670227050f, 0.788346409797668460f, 0.773010432720184330f,
-  0.757208824157714840f, 0.740951120853424070f,
-  0.724247097969055180f, 0.707106769084930420f, 0.689540565013885500f,
-  0.671558976173400880f, 0.653172850608825680f, 0.634393274784088130f,
-  0.615231573581695560f, 0.595699310302734380f,
-  0.575808167457580570f, 0.555570244789123540f, 0.534997642040252690f,
-  0.514102756977081300f, 0.492898195981979370f, 0.471396744251251220f,
-  0.449611335992813110f, 0.427555084228515630f,
-  0.405241310596466060f, 0.382683426141738890f, 0.359895050525665280f,
-  0.336889863014221190f, 0.313681751489639280f, 0.290284663438797000f,
-  0.266712754964828490f, 0.242980182170867920f,
-  0.219101235270500180f, 0.195090323686599730f, 0.170961886644363400f,
-  0.146730467677116390f, 0.122410677373409270f, 0.098017141222953796f,
-  0.073564566671848297f, 0.049067676067352295f,
-  0.024541229009628296f, 0.000000000000000061f, -0.024541229009628296f,
-  -0.049067676067352295f, -0.073564566671848297f, -0.098017141222953796f,
-  -0.122410677373409270f, -0.146730467677116390f,
-  -0.170961886644363400f, -0.195090323686599730f, -0.219101235270500180f,
-  -0.242980182170867920f, -0.266712754964828490f, -0.290284663438797000f,
-  -0.313681751489639280f, -0.336889863014221190f,
-  -0.359895050525665280f, -0.382683426141738890f, -0.405241310596466060f,
-  -0.427555084228515630f, -0.449611335992813110f, -0.471396744251251220f,
-  -0.492898195981979370f, -0.514102756977081300f,
-  -0.534997642040252690f, -0.555570244789123540f, -0.575808167457580570f,
-  -0.595699310302734380f, -0.615231573581695560f, -0.634393274784088130f,
-  -0.653172850608825680f, -0.671558976173400880f,
-  -0.689540565013885500f, -0.707106769084930420f, -0.724247097969055180f,
-  -0.740951120853424070f, -0.757208824157714840f, -0.773010432720184330f,
-  -0.788346409797668460f, -0.803207516670227050f,
-  -0.817584812641143800f, -0.831469595432281490f, -0.844853579998016360f,
-  -0.857728600502014160f, -0.870086967945098880f, -0.881921291351318360f,
-  -0.893224298954010010f, -0.903989315032958980f,
-  -0.914209783077239990f, -0.923879504203796390f, -0.932992815971374510f,
-  -0.941544055938720700f, -0.949528157711029050f, -0.956940352916717530f,
-  -0.963776051998138430f, -0.970031261444091800f,
-  -0.975702106952667240f, -0.980785250663757320f, -0.985277652740478520f,
-  -0.989176511764526370f, -0.992479562759399410f, -0.995184719562530520f,
-  -0.997290432453155520f, -0.998795449733734130f,
-  -0.999698817729949950f, -1.000000000000000000f, -0.999698817729949950f,
-  -0.998795449733734130f, -0.997290432453155520f, -0.995184719562530520f,
-  -0.992479562759399410f, -0.989176511764526370f,
-  -0.985277652740478520f, -0.980785250663757320f, -0.975702106952667240f,
-  -0.970031261444091800f, -0.963776051998138430f, -0.956940352916717530f,
-  -0.949528157711029050f, -0.941544055938720700f,
-  -0.932992815971374510f, -0.923879504203796390f, -0.914209783077239990f,
-  -0.903989315032958980f, -0.893224298954010010f, -0.881921291351318360f,
-  -0.870086967945098880f, -0.857728600502014160f,
-  -0.844853579998016360f, -0.831469595432281490f, -0.817584812641143800f,
-  -0.803207516670227050f, -0.788346409797668460f, -0.773010432720184330f,
-  -0.757208824157714840f, -0.740951120853424070f,
-  -0.724247097969055180f, -0.707106769084930420f, -0.689540565013885500f,
-  -0.671558976173400880f, -0.653172850608825680f, -0.634393274784088130f,
-  -0.615231573581695560f, -0.595699310302734380f,
-  -0.575808167457580570f, -0.555570244789123540f, -0.534997642040252690f,
-  -0.514102756977081300f, -0.492898195981979370f, -0.471396744251251220f,
-  -0.449611335992813110f, -0.427555084228515630f,
-  -0.405241310596466060f, -0.382683426141738890f, -0.359895050525665280f,
-  -0.336889863014221190f, -0.313681751489639280f, -0.290284663438797000f,
-  -0.266712754964828490f, -0.242980182170867920f,
-  -0.219101235270500180f, -0.195090323686599730f, -0.170961886644363400f,
-  -0.146730467677116390f, -0.122410677373409270f, -0.098017141222953796f,
-  -0.073564566671848297f, -0.049067676067352295f,
-  -0.024541229009628296f, -0.000000000000000184f, 0.024541229009628296f,
-  0.049067676067352295f, 0.073564566671848297f, 0.098017141222953796f,
-  0.122410677373409270f, 0.146730467677116390f,
-  0.170961886644363400f, 0.195090323686599730f, 0.219101235270500180f,
-  0.242980182170867920f, 0.266712754964828490f, 0.290284663438797000f,
-  0.313681751489639280f, 0.336889863014221190f,
-  0.359895050525665280f, 0.382683426141738890f, 0.405241310596466060f,
-  0.427555084228515630f, 0.449611335992813110f, 0.471396744251251220f,
-  0.492898195981979370f, 0.514102756977081300f,
-  0.534997642040252690f, 0.555570244789123540f, 0.575808167457580570f,
-  0.595699310302734380f, 0.615231573581695560f, 0.634393274784088130f,
-  0.653172850608825680f, 0.671558976173400880f,
-  0.689540565013885500f, 0.707106769084930420f, 0.724247097969055180f,
-  0.740951120853424070f, 0.757208824157714840f, 0.773010432720184330f,
-  0.788346409797668460f, 0.803207516670227050f,
-  0.817584812641143800f, 0.831469595432281490f, 0.844853579998016360f,
-  0.857728600502014160f, 0.870086967945098880f, 0.881921291351318360f,
-  0.893224298954010010f, 0.903989315032958980f,
-  0.914209783077239990f, 0.923879504203796390f, 0.932992815971374510f,
-  0.941544055938720700f, 0.949528157711029050f, 0.956940352916717530f,
-  0.963776051998138430f, 0.970031261444091800f,
-  0.975702106952667240f, 0.980785250663757320f, 0.985277652740478520f,
-  0.989176511764526370f, 0.992479562759399410f, 0.995184719562530520f,
-  0.997290432453155520f, 0.998795449733734130f,
-  0.999698817729949950f, 1.000000000000000000f, 0.999698817729949950f,
-  0.998795449733734130f
-};
-
-/**   
- * @brief  Fast approximation to the trigonometric cosine function for floating-point data.   
- * @param[in] x input value in radians.   
- * @return cos(x).   
- */
-
-
-float32_t arm_cos_f32(
-  float32_t x)
-{
-  float32_t cosVal, fract, in;
-  int32_t index;
-  uint32_t tableSize = (uint32_t) TABLE_SIZE;
-  float32_t wa, wb, wc, wd;
-  float32_t a, b, c, d;
-  float32_t *tablePtr;
-  int32_t n;
-  float32_t fractsq, fractby2, fractby6, fractby3, fractsqby2;
-  float32_t oneminusfractby2;
-  float32_t frby2xfrsq, frby6xfrsq;
-
-  /* input x is in radians */
-  /* Scale the input to [0 1] range from [0 2*PI] , divide input by 2*pi */
-  in = x * 0.159154943092f;
-
-  /* Calculation of floor value of input */
-  n = (int32_t) in;
-
-  /* Make negative values towards -infinity */
-  if(x < 0.0f)
-  {
-    n = n - 1;
-  }
-
-  /* Map input value to [0 1] */
-  in = in - (float32_t) n;
-
-  /* Calculation of index of the table */
-  index = (uint32_t) (tableSize * in);
-
-  /* fractional value calculation */
-  fract = ((float32_t) tableSize * in) - (float32_t) index;
-
-  /* Checking min and max index of table */
-  if(index < 0)
-  {
-    index = 0;
-  }
-  else if(index > 256)
-  {
-    index = 256;
-  }
-
-  /* Initialise table pointer */
-  tablePtr = (float32_t *) & cosTable[index];
-
-  /* Read four nearest values of input value from the cos table */
-  a = tablePtr[0];
-  b = tablePtr[1];
-  c = tablePtr[2];
-  d = tablePtr[3];
-
-  /* Cubic interpolation process */
-  fractsq = fract * fract;
-  fractby2 = fract * 0.5f;
-  fractby6 = fract * 0.166666667f;
-  fractby3 = fract * 0.3333333333333f;
-  fractsqby2 = fractsq * 0.5f;
-  frby2xfrsq = (fractby2) * fractsq;
-  frby6xfrsq = (fractby6) * fractsq;
-  oneminusfractby2 = 1.0f - fractby2;
-  wb = fractsqby2 - fractby3;
-  wc = (fractsqby2 + fract);
-  wa = wb - frby6xfrsq;
-  wb = frby2xfrsq - fractsq;
-  cosVal = wa * a;
-  wc = wc - frby2xfrsq;
-  wd = (frby6xfrsq) - fractby6;
-  wb = wb + oneminusfractby2;
-
-  /* Calculate cos value */
-  cosVal = (cosVal + (b * wb)) + ((c * wc) + (d * wd));
-
-  /* Return the output value */
-  return (cosVal);
-
-}
-
-/**    
- * @} end of cos group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q15.c
deleted file mode 100644
index 12339fd75e..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q15.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_cos_q15.c    
-*    
-* Description:	Fast cosine calculation for Q15 values.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFastMath    
- */
-
- /**    
- * @addtogroup cos    
- * @{    
- */
-
-/**   
-* \par    
-* Table Values are in Q15(1.15 Fixed point format) and generation is done in three steps    
-* \par    
-* First Generate cos values in floating point:    
-* tableSize = 256;     
-* 
for(n = -1; n < (tableSize + 1); n++)    
-* {    
-*	cosTable[n+1]= cos(2*pi*n/tableSize);    
-* }
   
-* where pi value is  3.14159265358979    
-* \par    
-* Secondly Convert Floating point to Q15(Fixed point):    
-*	(cosTable[i] * pow(2, 15))    
-* \par    
-* Finally Rounding to nearest integer is done    
-* 	cosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5);    
-*/
-
-static const q15_t cosTableQ15[259] = {
-  0x7ff6, 0x7fff, 0x7ff6, 0x7fd9, 0x7fa7, 0x7f62, 0x7f0a, 0x7e9d,
-  0x7e1e, 0x7d8a, 0x7ce4, 0x7c2a, 0x7b5d, 0x7a7d, 0x798a, 0x7885,
-  0x776c, 0x7642, 0x7505, 0x73b6, 0x7255, 0x70e3, 0x6f5f, 0x6dca,
-  0x6c24, 0x6a6e, 0x68a7, 0x66d0, 0x64e9, 0x62f2, 0x60ec, 0x5ed7,
-  0x5cb4, 0x5a82, 0x5843, 0x55f6, 0x539b, 0x5134, 0x4ec0, 0x4c40,
-  0x49b4, 0x471d, 0x447b, 0x41ce, 0x3f17, 0x3c57, 0x398d, 0x36ba,
-  0x33df, 0x30fc, 0x2e11, 0x2b1f, 0x2827, 0x2528, 0x2224, 0x1f1a,
-  0x1c0c, 0x18f9, 0x15e2, 0x12c8, 0xfab, 0xc8c, 0x96b, 0x648,
-  0x324, 0x0, 0xfcdc, 0xf9b8, 0xf695, 0xf374, 0xf055, 0xed38,
-  0xea1e, 0xe707, 0xe3f4, 0xe0e6, 0xdddc, 0xdad8, 0xd7d9, 0xd4e1,
-  0xd1ef, 0xcf04, 0xcc21, 0xc946, 0xc673, 0xc3a9, 0xc0e9, 0xbe32,
-  0xbb85, 0xb8e3, 0xb64c, 0xb3c0, 0xb140, 0xaecc, 0xac65, 0xaa0a,
-  0xa7bd, 0xa57e, 0xa34c, 0xa129, 0x9f14, 0x9d0e, 0x9b17, 0x9930,
-  0x9759, 0x9592, 0x93dc, 0x9236, 0x90a1, 0x8f1d, 0x8dab, 0x8c4a,
-  0x8afb, 0x89be, 0x8894, 0x877b, 0x8676, 0x8583, 0x84a3, 0x83d6,
-  0x831c, 0x8276, 0x81e2, 0x8163, 0x80f6, 0x809e, 0x8059, 0x8027,
-  0x800a, 0x8000, 0x800a, 0x8027, 0x8059, 0x809e, 0x80f6, 0x8163,
-  0x81e2, 0x8276, 0x831c, 0x83d6, 0x84a3, 0x8583, 0x8676, 0x877b,
-  0x8894, 0x89be, 0x8afb, 0x8c4a, 0x8dab, 0x8f1d, 0x90a1, 0x9236,
-  0x93dc, 0x9592, 0x9759, 0x9930, 0x9b17, 0x9d0e, 0x9f14, 0xa129,
-  0xa34c, 0xa57e, 0xa7bd, 0xaa0a, 0xac65, 0xaecc, 0xb140, 0xb3c0,
-  0xb64c, 0xb8e3, 0xbb85, 0xbe32, 0xc0e9, 0xc3a9, 0xc673, 0xc946,
-  0xcc21, 0xcf04, 0xd1ef, 0xd4e1, 0xd7d9, 0xdad8, 0xdddc, 0xe0e6,
-  0xe3f4, 0xe707, 0xea1e, 0xed38, 0xf055, 0xf374, 0xf695, 0xf9b8,
-  0xfcdc, 0x0, 0x324, 0x648, 0x96b, 0xc8c, 0xfab, 0x12c8,
-  0x15e2, 0x18f9, 0x1c0c, 0x1f1a, 0x2224, 0x2528, 0x2827, 0x2b1f,
-  0x2e11, 0x30fc, 0x33df, 0x36ba, 0x398d, 0x3c57, 0x3f17, 0x41ce,
-  0x447b, 0x471d, 0x49b4, 0x4c40, 0x4ec0, 0x5134, 0x539b, 0x55f6,
-  0x5843, 0x5a82, 0x5cb4, 0x5ed7, 0x60ec, 0x62f2, 0x64e9, 0x66d0,
-  0x68a7, 0x6a6e, 0x6c24, 0x6dca, 0x6f5f, 0x70e3, 0x7255, 0x73b6,
-  0x7505, 0x7642, 0x776c, 0x7885, 0x798a, 0x7a7d, 0x7b5d, 0x7c2a,
-  0x7ce4, 0x7d8a, 0x7e1e, 0x7e9d, 0x7f0a, 0x7f62, 0x7fa7, 0x7fd9,
-  0x7ff6, 0x7fff, 0x7ff6
-};
-
-
-/**   
- * @brief Fast approximation to the trigonometric cosine function for Q15 data.   
- * @param[in] x Scaled input value in radians.   
- * @return  cos(x).   
- *   
- * The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi), Here range excludes 2*pi.   
- */
-
-q15_t arm_cos_q15(
-  q15_t x)
-{
-  q31_t cosVal;                                  /* Temporary variable for output */
-  q15_t *tablePtr;                               /* Pointer to table */
-  q15_t in, in2;                                 /* Temporary variables for input */
-  q31_t wa, wb, wc, wd;                          /* Cubic interpolation coefficients */
-  q15_t a, b, c, d;                              /* Four nearest output values */
-  q15_t fract, fractCube, fractSquare;           /* Variables for fractional value */
-  q15_t oneBy6 = 0x1555;                         /* Fixed point value of 1/6 */
-  q15_t tableSpacing = TABLE_SPACING_Q15;        /* Table spacing */
-  int32_t index;                                 /* Index variable */
-
-  in = x;
-
-  /* Calculate the nearest index */
-  index = (int32_t) in / tableSpacing;
-
-  /* Calculate the nearest value of input */
-  in2 = (q15_t) index *tableSpacing;
-
-  /* Calculation of fractional value */
-  fract = (in - in2) << 8;
-
-  /* fractSquare = fract * fract */
-  fractSquare = (q15_t) ((fract * fract) >> 15);
-
-  /* fractCube = fract * fract * fract */
-  fractCube = (q15_t) ((fractSquare * fract) >> 15);
-
-  /* Checking min and max index of table */
-  if(index < 0)
-  {
-    index = 0;
-  }
-  else if(index > 256)
-  {
-    index = 256;
-  }
-
-  /* Initialise table pointer */
-  tablePtr = (q15_t *) & cosTableQ15[index];
-
-  /* Cubic interpolation process */
-  /* Calculation of wa */
-  /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAA)*fract; */
-  wa = (q31_t) oneBy6 *fractCube;
-  wa += (q31_t) 0x2AAA *fract;
-  wa = -(wa >> 15);
-  wa += (fractSquare >> 1u);
-
-  /* Read first nearest value of output from the cos table */
-  a = *tablePtr++;
-
-  /* cosVal = a * wa */
-  cosVal = a * wa;
-
-  /* Calculation of wb */
-  wb = (((fractCube >> 1u) - fractSquare) - (fract >> 1u)) + 0x7FFF;
-
-  /* Read second nearest value of output from the cos table */
-  b = *tablePtr++;
-
-  /*      cosVal += b*wb */
-  cosVal += b * wb;
-
-  /* Calculation of wc */
-  wc = -(q31_t) fractCube + fractSquare;
-  wc = (wc >> 1u) + fract;
-
-  /* Read third nearest value of output from the cos table */
-  c = *tablePtr++;
-
-  /* cosVal += c*wc */
-  cosVal += c * wc;
-
-  /* Calculation of wd */
-  /* wd = (oneBy6)*fractCube - (oneBy6)*fract; */
-  fractCube = fractCube - fract;
-  wd = ((q15_t) (((q31_t) oneBy6 * fractCube) >> 15));
-
-  /* Read fourth nearest value of output from the cos table */
-  d = *tablePtr++;
-
-  /* cosVal += d*wd; */
-  cosVal += d * wd;
-
-  /* Convert output value in 1.15(q15) format and saturate */
-  cosVal = __SSAT((cosVal >> 15), 16);
-
-  /* Return the output value in 1.15(q15) format */
-  return ((q15_t) cosVal);
-
-}
-
-/**    
- * @} end of cos group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q31.c
deleted file mode 100644
index 10ecedb41a..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q31.c
+++ /dev/null
@@ -1,239 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_cos_q31.c    
-*    
-* Description:	Fast cosine calculation for Q31 values.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFastMath    
- */
-
- /**    
- * @addtogroup cos    
- * @{    
- */
-
-/**    
- * \par    
- * Table Values are in Q31(1.31 Fixed point format) and generation is done in three steps    
- * First Generate cos values in floating point:    
- * tableSize = 256;      
- * 
for(n = -1; n < (tableSize + 1); n++)    
- * {    
- *	cosTable[n+1]= cos(2*pi*n/tableSize);    
- * } 
     
- * where pi value is  3.14159265358979    
- * \par    
- * Secondly Convert Floating point to Q31(Fixed point):    
- *	(cosTable[i] * pow(2, 31))    
- * \par    
- * Finally Rounding to nearest integer is done    
- * 	cosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5);    
- */
-
-
-static const q31_t cosTableQ31[259] = {
-  0x7ff62182, 0x7fffffff, 0x7ff62182, 0x7fd8878e, 0x7fa736b4, 0x7f62368f,
-  0x7f0991c4, 0x7e9d55fc,
-  0x7e1d93ea, 0x7d8a5f40, 0x7ce3ceb2, 0x7c29fbee, 0x7b5d039e, 0x7a7d055b,
-  0x798a23b1, 0x78848414,
-  0x776c4edb, 0x7641af3d, 0x7504d345, 0x73b5ebd1, 0x72552c85, 0x70e2cbc6,
-  0x6f5f02b2, 0x6dca0d14,
-  0x6c242960, 0x6a6d98a4, 0x68a69e81, 0x66cf8120, 0x64e88926, 0x62f201ac,
-  0x60ec3830, 0x5ed77c8a,
-  0x5cb420e0, 0x5a82799a, 0x5842dd54, 0x55f5a4d2, 0x539b2af0, 0x5133cc94,
-  0x4ebfe8a5, 0x4c3fdff4,
-  0x49b41533, 0x471cece7, 0x447acd50, 0x41ce1e65, 0x3f1749b8, 0x3c56ba70,
-  0x398cdd32, 0x36ba2014,
-  0x33def287, 0x30fbc54d, 0x2e110a62, 0x2b1f34eb, 0x2826b928, 0x25280c5e,
-  0x2223a4c5, 0x1f19f97b,
-  0x1c0b826a, 0x18f8b83c, 0x15e21445, 0x12c8106f, 0xfab272b, 0xc8bd35e,
-  0x96a9049, 0x647d97c,
-  0x3242abf, 0x0, 0xfcdbd541, 0xf9b82684, 0xf6956fb7, 0xf3742ca2, 0xf054d8d5,
-  0xed37ef91,
-  0xea1debbb, 0xe70747c4, 0xe3f47d96, 0xe0e60685, 0xdddc5b3b, 0xdad7f3a2,
-  0xd7d946d8, 0xd4e0cb15,
-  0xd1eef59e, 0xcf043ab3, 0xcc210d79, 0xc945dfec, 0xc67322ce, 0xc3a94590,
-  0xc0e8b648, 0xbe31e19b,
-  0xbb8532b0, 0xb8e31319, 0xb64beacd, 0xb3c0200c, 0xb140175b, 0xaecc336c,
-  0xac64d510, 0xaa0a5b2e,
-  0xa7bd22ac, 0xa57d8666, 0xa34bdf20, 0xa1288376, 0x9f13c7d0, 0x9d0dfe54,
-  0x9b1776da, 0x99307ee0,
-  0x9759617f, 0x9592675c, 0x93dbd6a0, 0x9235f2ec, 0x90a0fd4e, 0x8f1d343a,
-  0x8daad37b, 0x8c4a142f,
-  0x8afb2cbb, 0x89be50c3, 0x8893b125, 0x877b7bec, 0x8675dc4f, 0x8582faa5,
-  0x84a2fc62, 0x83d60412,
-  0x831c314e, 0x8275a0c0, 0x81e26c16, 0x8162aa04, 0x80f66e3c, 0x809dc971,
-  0x8058c94c, 0x80277872,
-  0x8009de7e, 0x80000000, 0x8009de7e, 0x80277872, 0x8058c94c, 0x809dc971,
-  0x80f66e3c, 0x8162aa04,
-  0x81e26c16, 0x8275a0c0, 0x831c314e, 0x83d60412, 0x84a2fc62, 0x8582faa5,
-  0x8675dc4f, 0x877b7bec,
-  0x8893b125, 0x89be50c3, 0x8afb2cbb, 0x8c4a142f, 0x8daad37b, 0x8f1d343a,
-  0x90a0fd4e, 0x9235f2ec,
-  0x93dbd6a0, 0x9592675c, 0x9759617f, 0x99307ee0, 0x9b1776da, 0x9d0dfe54,
-  0x9f13c7d0, 0xa1288376,
-  0xa34bdf20, 0xa57d8666, 0xa7bd22ac, 0xaa0a5b2e, 0xac64d510, 0xaecc336c,
-  0xb140175b, 0xb3c0200c,
-  0xb64beacd, 0xb8e31319, 0xbb8532b0, 0xbe31e19b, 0xc0e8b648, 0xc3a94590,
-  0xc67322ce, 0xc945dfec,
-  0xcc210d79, 0xcf043ab3, 0xd1eef59e, 0xd4e0cb15, 0xd7d946d8, 0xdad7f3a2,
-  0xdddc5b3b, 0xe0e60685,
-  0xe3f47d96, 0xe70747c4, 0xea1debbb, 0xed37ef91, 0xf054d8d5, 0xf3742ca2,
-  0xf6956fb7, 0xf9b82684,
-  0xfcdbd541, 0x0, 0x3242abf, 0x647d97c, 0x96a9049, 0xc8bd35e, 0xfab272b,
-  0x12c8106f,
-  0x15e21445, 0x18f8b83c, 0x1c0b826a, 0x1f19f97b, 0x2223a4c5, 0x25280c5e,
-  0x2826b928, 0x2b1f34eb,
-  0x2e110a62, 0x30fbc54d, 0x33def287, 0x36ba2014, 0x398cdd32, 0x3c56ba70,
-  0x3f1749b8, 0x41ce1e65,
-  0x447acd50, 0x471cece7, 0x49b41533, 0x4c3fdff4, 0x4ebfe8a5, 0x5133cc94,
-  0x539b2af0, 0x55f5a4d2,
-  0x5842dd54, 0x5a82799a, 0x5cb420e0, 0x5ed77c8a, 0x60ec3830, 0x62f201ac,
-  0x64e88926, 0x66cf8120,
-  0x68a69e81, 0x6a6d98a4, 0x6c242960, 0x6dca0d14, 0x6f5f02b2, 0x70e2cbc6,
-  0x72552c85, 0x73b5ebd1,
-  0x7504d345, 0x7641af3d, 0x776c4edb, 0x78848414, 0x798a23b1, 0x7a7d055b,
-  0x7b5d039e, 0x7c29fbee,
-  0x7ce3ceb2, 0x7d8a5f40, 0x7e1d93ea, 0x7e9d55fc, 0x7f0991c4, 0x7f62368f,
-  0x7fa736b4, 0x7fd8878e,
-  0x7ff62182, 0x7fffffff, 0x7ff62182
-};
-
-/**   
- * @brief Fast approximation to the trigonometric cosine function for Q31 data.   
- * @param[in] x Scaled input value in radians.   
- * @return  cos(x).   
- *   
- * The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi), Here range excludes 2*pi.   
- */
-
-q31_t arm_cos_q31(
-  q31_t x)
-{
-  q31_t cosVal, in, in2;                         /* Temporary variables for input, output */
-  q31_t wa, wb, wc, wd;                          /* Cubic interpolation coefficients */
-  q31_t a, b, c, d;                              /* Four nearest output values */
-  q31_t *tablePtr;                               /* Pointer to table */
-  q31_t fract, fractCube, fractSquare;           /* Temporary values for fractional values */
-  q31_t oneBy6 = 0x15555555;                     /* Fixed point value of 1/6 */
-  q31_t tableSpacing = TABLE_SPACING_Q31;        /* Table spacing */
-  q31_t temp;                                    /* Temporary variable for intermediate process */
-  int32_t index;                                 /* Index variable */
-
-  in = x;
-
-  /* Calculate the nearest index */
-  index = in / tableSpacing;
-
-  /* Calculate the nearest value of input */
-  in2 = ((q31_t) index) * tableSpacing;
-
-  /* Calculation of fractional value */
-  fract = (in - in2) << 8;
-
-  /* fractSquare = fract * fract */
-  fractSquare = ((q31_t) (((q63_t) fract * fract) >> 32));
-  fractSquare = fractSquare << 1;
-
-  /* fractCube = fract * fract * fract */
-  fractCube = ((q31_t) (((q63_t) fractSquare * fract) >> 32));
-  fractCube = fractCube << 1;
-
-  /* Checking min and max index of table */
-  if(index < 0)
-  {
-    index = 0;
-  }
-  else if(index > 256)
-  {
-    index = 256;
-  }
-
-  /* Initialise table pointer */
-  tablePtr = (q31_t *) & cosTableQ31[index];
-
-  /* Cubic interpolation process */
-  /* Calculation of wa */
-  /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAAAAAA)*fract; */
-  wa = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));
-  temp = 0x2AAAAAAA;
-  wa = (q31_t) ((((q63_t) wa << 32) + ((q63_t) temp * fract)) >> 32);
-  wa = -(wa << 1u);
-  wa += (fractSquare >> 1u);
-
-  /* Read first nearest value of output from the cos table */
-  a = *tablePtr++;
-
-  /* cosVal = a*wa */
-  cosVal = ((q31_t) (((q63_t) a * wa) >> 32));
-
-  /* q31(1.31) Fixed point value of 1 */
-  temp = 0x7FFFFFFF;
-
-  /* Calculation of wb */
-  wb = ((fractCube >> 1u) - (fractSquare + (fract >> 1u))) + temp;
-  /* Read second nearest value of output from the cos table */
-  b = *tablePtr++;
-
-  /*      cosVal += b*wb */
-  cosVal = (q31_t) ((((q63_t) cosVal << 32) + ((q63_t) b * (wb))) >> 32);
-
-  /* Calculation of wc */
-  wc = -fractCube + fractSquare;
-  wc = (wc >> 1u) + fract;
-  /* Read third nearest values of output value from the cos table */
-  c = *tablePtr++;
-
-  /*      cosVal += c*wc */
-  cosVal = (q31_t) ((((q63_t) cosVal << 32) + ((q63_t) c * (wc))) >> 32);
-
-  /* Calculation of wd */
-  /* wd = (oneBy6)*fractCube - (oneBy6)*fract; */
-  fractCube = fractCube - fract;
-  wd = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));
-  wd = (wd << 1u);
-
-  /* Read fourth nearest value of output from the cos table */
-  d = *tablePtr++;
-
-  /* cosVal += d*wd; */
-  cosVal = (q31_t) ((((q63_t) cosVal << 32) + ((q63_t) d * (wd))) >> 32);
-
-
-  /* convert cosVal in 2.30 format to 1.31 format */
-  return (__QADD(cosVal, cosVal));
-
-}
-
-/**    
- * @} end of cos group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_f32.c
deleted file mode 100644
index bbbdd6c6c9..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_f32.c
+++ /dev/null
@@ -1,281 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_sin_f32.c    
-*    
-* Description:	Fast sine calculation for floating-point values.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFastMath    
- */
-
-/**    
- * @defgroup sin Sine    
- *    
- * Computes the trigonometric sine function using a combination of table lookup   
- * and cubic interpolation.  There are separate functions for   
- * Q15, Q31, and floating-point data types.   
- * The input to the floating-point version is in radians while the   
- * fixed-point Q15 and Q31 have a scaled input with the range   
- * [0 +0.9999] mapping to [0 2*pi), Where range excludes 2*pi.   
- *   
- * The implementation is based on table lookup using 256 values together with cubic interpolation.   
- * The steps used are:   
- *  -# Calculation of the nearest integer table index   
- *  -# Fetch the four table values a, b, c, and d     
- *  -# Compute the fractional portion (fract) of the table index.   
- *  -# Calculation of wa, wb, wc, wd    
- *  -# The final result equals a*wa + b*wb + c*wc + d*wd   
- *   
- * where   
- * 
    
- *    a=Table[index-1];    
- *    b=Table[index+0];    
- *    c=Table[index+1];    
- *    d=Table[index+2];    
- * 
   
- * and   
- * 
    
- *    wa=-(1/6)*fract.^3 + (1/2)*fract.^2 - (1/3)*fract;    
- *    wb=(1/2)*fract.^3 - fract.^2 - (1/2)*fract + 1;    
- *    wc=-(1/2)*fract.^3+(1/2)*fract.^2+fract;    
- *    wd=(1/6)*fract.^3 - (1/6)*fract;    
- * 
    
- */
-
-/**    
- * @addtogroup sin    
- * @{    
- */
-
-
-/**   
- * \par    
- * Example code for Generation of Floating-point Sin Table:   
- * tableSize = 256;    
- * 
for(n = -1; n < (tableSize + 1); n++)    
- * {    
- *	sinTable[n+1]=sin(2*pi*n/tableSize);    
- * }
    
- * \par    
- * where pi value is  3.14159265358979    
- */
-
-static const float32_t sinTable[259] = {
-  -0.024541229009628296f, 0.000000000000000000f, 0.024541229009628296f,
-  0.049067676067352295f, 0.073564566671848297f, 0.098017141222953796f,
-  0.122410677373409270f, 0.146730467677116390f,
-  0.170961886644363400f, 0.195090323686599730f, 0.219101235270500180f,
-  0.242980182170867920f, 0.266712754964828490f, 0.290284663438797000f,
-  0.313681751489639280f, 0.336889863014221190f,
-  0.359895050525665280f, 0.382683426141738890f, 0.405241310596466060f,
-  0.427555084228515630f, 0.449611335992813110f, 0.471396744251251220f,
-  0.492898195981979370f, 0.514102756977081300f,
-  0.534997642040252690f, 0.555570244789123540f, 0.575808167457580570f,
-  0.595699310302734380f, 0.615231573581695560f, 0.634393274784088130f,
-  0.653172850608825680f, 0.671558976173400880f,
-  0.689540565013885500f, 0.707106769084930420f, 0.724247097969055180f,
-  0.740951120853424070f, 0.757208824157714840f, 0.773010432720184330f,
-  0.788346409797668460f, 0.803207516670227050f,
-  0.817584812641143800f, 0.831469595432281490f, 0.844853579998016360f,
-  0.857728600502014160f, 0.870086967945098880f, 0.881921291351318360f,
-  0.893224298954010010f, 0.903989315032958980f,
-  0.914209783077239990f, 0.923879504203796390f, 0.932992815971374510f,
-  0.941544055938720700f, 0.949528157711029050f, 0.956940352916717530f,
-  0.963776051998138430f, 0.970031261444091800f,
-  0.975702106952667240f, 0.980785250663757320f, 0.985277652740478520f,
-  0.989176511764526370f, 0.992479562759399410f, 0.995184719562530520f,
-  0.997290432453155520f, 0.998795449733734130f,
-  0.999698817729949950f, 1.000000000000000000f, 0.999698817729949950f,
-  0.998795449733734130f, 0.997290432453155520f, 0.995184719562530520f,
-  0.992479562759399410f, 0.989176511764526370f,
-  0.985277652740478520f, 0.980785250663757320f, 0.975702106952667240f,
-  0.970031261444091800f, 0.963776051998138430f, 0.956940352916717530f,
-  0.949528157711029050f, 0.941544055938720700f,
-  0.932992815971374510f, 0.923879504203796390f, 0.914209783077239990f,
-  0.903989315032958980f, 0.893224298954010010f, 0.881921291351318360f,
-  0.870086967945098880f, 0.857728600502014160f,
-  0.844853579998016360f, 0.831469595432281490f, 0.817584812641143800f,
-  0.803207516670227050f, 0.788346409797668460f, 0.773010432720184330f,
-  0.757208824157714840f, 0.740951120853424070f,
-  0.724247097969055180f, 0.707106769084930420f, 0.689540565013885500f,
-  0.671558976173400880f, 0.653172850608825680f, 0.634393274784088130f,
-  0.615231573581695560f, 0.595699310302734380f,
-  0.575808167457580570f, 0.555570244789123540f, 0.534997642040252690f,
-  0.514102756977081300f, 0.492898195981979370f, 0.471396744251251220f,
-  0.449611335992813110f, 0.427555084228515630f,
-  0.405241310596466060f, 0.382683426141738890f, 0.359895050525665280f,
-  0.336889863014221190f, 0.313681751489639280f, 0.290284663438797000f,
-  0.266712754964828490f, 0.242980182170867920f,
-  0.219101235270500180f, 0.195090323686599730f, 0.170961886644363400f,
-  0.146730467677116390f, 0.122410677373409270f, 0.098017141222953796f,
-  0.073564566671848297f, 0.049067676067352295f,
-  0.024541229009628296f, 0.000000000000000122f, -0.024541229009628296f,
-  -0.049067676067352295f, -0.073564566671848297f, -0.098017141222953796f,
-  -0.122410677373409270f, -0.146730467677116390f,
-  -0.170961886644363400f, -0.195090323686599730f, -0.219101235270500180f,
-  -0.242980182170867920f, -0.266712754964828490f, -0.290284663438797000f,
-  -0.313681751489639280f, -0.336889863014221190f,
-  -0.359895050525665280f, -0.382683426141738890f, -0.405241310596466060f,
-  -0.427555084228515630f, -0.449611335992813110f, -0.471396744251251220f,
-  -0.492898195981979370f, -0.514102756977081300f,
-  -0.534997642040252690f, -0.555570244789123540f, -0.575808167457580570f,
-  -0.595699310302734380f, -0.615231573581695560f, -0.634393274784088130f,
-  -0.653172850608825680f, -0.671558976173400880f,
-  -0.689540565013885500f, -0.707106769084930420f, -0.724247097969055180f,
-  -0.740951120853424070f, -0.757208824157714840f, -0.773010432720184330f,
-  -0.788346409797668460f, -0.803207516670227050f,
-  -0.817584812641143800f, -0.831469595432281490f, -0.844853579998016360f,
-  -0.857728600502014160f, -0.870086967945098880f, -0.881921291351318360f,
-  -0.893224298954010010f, -0.903989315032958980f,
-  -0.914209783077239990f, -0.923879504203796390f, -0.932992815971374510f,
-  -0.941544055938720700f, -0.949528157711029050f, -0.956940352916717530f,
-  -0.963776051998138430f, -0.970031261444091800f,
-  -0.975702106952667240f, -0.980785250663757320f, -0.985277652740478520f,
-  -0.989176511764526370f, -0.992479562759399410f, -0.995184719562530520f,
-  -0.997290432453155520f, -0.998795449733734130f,
-  -0.999698817729949950f, -1.000000000000000000f, -0.999698817729949950f,
-  -0.998795449733734130f, -0.997290432453155520f, -0.995184719562530520f,
-  -0.992479562759399410f, -0.989176511764526370f,
-  -0.985277652740478520f, -0.980785250663757320f, -0.975702106952667240f,
-  -0.970031261444091800f, -0.963776051998138430f, -0.956940352916717530f,
-  -0.949528157711029050f, -0.941544055938720700f,
-  -0.932992815971374510f, -0.923879504203796390f, -0.914209783077239990f,
-  -0.903989315032958980f, -0.893224298954010010f, -0.881921291351318360f,
-  -0.870086967945098880f, -0.857728600502014160f,
-  -0.844853579998016360f, -0.831469595432281490f, -0.817584812641143800f,
-  -0.803207516670227050f, -0.788346409797668460f, -0.773010432720184330f,
-  -0.757208824157714840f, -0.740951120853424070f,
-  -0.724247097969055180f, -0.707106769084930420f, -0.689540565013885500f,
-  -0.671558976173400880f, -0.653172850608825680f, -0.634393274784088130f,
-  -0.615231573581695560f, -0.595699310302734380f,
-  -0.575808167457580570f, -0.555570244789123540f, -0.534997642040252690f,
-  -0.514102756977081300f, -0.492898195981979370f, -0.471396744251251220f,
-  -0.449611335992813110f, -0.427555084228515630f,
-  -0.405241310596466060f, -0.382683426141738890f, -0.359895050525665280f,
-  -0.336889863014221190f, -0.313681751489639280f, -0.290284663438797000f,
-  -0.266712754964828490f, -0.242980182170867920f,
-  -0.219101235270500180f, -0.195090323686599730f, -0.170961886644363400f,
-  -0.146730467677116390f, -0.122410677373409270f, -0.098017141222953796f,
-  -0.073564566671848297f, -0.049067676067352295f,
-  -0.024541229009628296f, -0.000000000000000245f, 0.024541229009628296f
-};
-
-
-/**   
- * @brief  Fast approximation to the trigonometric sine function for floating-point data.   
- * @param[in] x input value in radians.   
- * @return  sin(x).   
- */
-
-float32_t arm_sin_f32(
-  float32_t x)
-{
-  float32_t sinVal, fract, in;                   /* Temporary variables for input, output */
-  int32_t index;                                 /* Index variable */
-  uint32_t tableSize = (uint32_t) TABLE_SIZE;    /* Initialise tablesize */
-  float32_t wa, wb, wc, wd;                      /* Cubic interpolation coefficients */
-  float32_t a, b, c, d;                          /* Four nearest output values */
-  float32_t *tablePtr;                           /* Pointer to table */
-  int32_t n;
-  float32_t fractsq, fractby2, fractby6, fractby3, fractsqby2;
-  float32_t oneminusfractby2;
-  float32_t frby2xfrsq, frby6xfrsq;
-
-  /* input x is in radians */
-  /* Scale the input to [0 1] range from [0 2*PI] , divide input by 2*pi */
-  in = x * 0.159154943092f;
-
-  /* Calculation of floor value of input */
-  n = (int32_t) in;
-
-  /* Make negative values towards -infinity */
-  if(x < 0.0f)
-  {
-    n = n - 1;
-  }
-
-  /* Map input value to [0 1] */
-  in = in - (float32_t) n;
-
-  /* Calculation of index of the table */
-  index = (uint32_t) (tableSize * in);
-
-  /* fractional value calculation */
-  fract = ((float32_t) tableSize * in) - (float32_t) index;
-
-  /* Checking min and max index of table */
-  if(index < 0)
-  {
-    index = 0;
-  }
-  else if(index > 256)
-  {
-    index = 256;
-  }
-
-  /* Initialise table pointer */
-  tablePtr = (float32_t *) & sinTable[index];
-
-  /* Read four nearest values of input value from the sin table */
-  a = tablePtr[0];
-  b = tablePtr[1];
-  c = tablePtr[2];
-  d = tablePtr[3];
-
-  /* Cubic interpolation process */
-  fractsq = fract * fract;
-  fractby2 = fract * 0.5f;
-  fractby6 = fract * 0.166666667f;
-  fractby3 = fract * 0.3333333333333f;
-  fractsqby2 = fractsq * 0.5f;
-  frby2xfrsq = (fractby2) * fractsq;
-  frby6xfrsq = (fractby6) * fractsq;
-  oneminusfractby2 = 1.0f - fractby2;
-  wb = fractsqby2 - fractby3;
-  wc = (fractsqby2 + fract);
-  wa = wb - frby6xfrsq;
-  wb = frby2xfrsq - fractsq;
-  sinVal = wa * a;
-  wc = wc - frby2xfrsq;
-  wd = (frby6xfrsq) - fractby6;
-  wb = wb + oneminusfractby2;
-
-  /* Calculate sin value */
-  sinVal = (sinVal + (b * wb)) + ((c * wc) + (d * wd));
-
-  /* Return the output value */
-  return (sinVal);
-
-}
-
-/**    
- * @} end of sin group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q15.c
deleted file mode 100644
index 5eb35652ca..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q15.c
+++ /dev/null
@@ -1,208 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_sin_q15.c    
-*    
-* Description:	Fast sine calculation for Q15 values.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFastMath    
- */
-
- /**    
- * @addtogroup sin    
- * @{    
- */
-
-
-/**    
- * \par    
- * Example code for Generation of Q15 Sin Table:   
- * \par    
- * 
tableSize = 256;    
- * for(n = -1; n < (tableSize + 1); n++)    
- * {    
- *	sinTable[n+1]=sin(2*pi*n/tableSize);    
- * } 
    
- * where pi value is  3.14159265358979    
- * \par    
- * Convert Floating point to Q15(Fixed point):    
- *	(sinTable[i] * pow(2, 15))    
- * \par    
- * rounding to nearest integer is done    
- * 	sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5);    
- */
-
-
-static const q15_t sinTableQ15[259] = {
-  0xfcdc, 0x0, 0x324, 0x648, 0x96b, 0xc8c, 0xfab, 0x12c8,
-  0x15e2, 0x18f9, 0x1c0c, 0x1f1a, 0x2224, 0x2528, 0x2827, 0x2b1f,
-  0x2e11, 0x30fc, 0x33df, 0x36ba, 0x398d, 0x3c57, 0x3f17, 0x41ce,
-  0x447b, 0x471d, 0x49b4, 0x4c40, 0x4ec0, 0x5134, 0x539b, 0x55f6,
-  0x5843, 0x5a82, 0x5cb4, 0x5ed7, 0x60ec, 0x62f2, 0x64e9, 0x66d0,
-  0x68a7, 0x6a6e, 0x6c24, 0x6dca, 0x6f5f, 0x70e3, 0x7255, 0x73b6,
-  0x7505, 0x7642, 0x776c, 0x7885, 0x798a, 0x7a7d, 0x7b5d, 0x7c2a,
-  0x7ce4, 0x7d8a, 0x7e1e, 0x7e9d, 0x7f0a, 0x7f62, 0x7fa7, 0x7fd9,
-  0x7ff6, 0x7fff, 0x7ff6, 0x7fd9, 0x7fa7, 0x7f62, 0x7f0a, 0x7e9d,
-  0x7e1e, 0x7d8a, 0x7ce4, 0x7c2a, 0x7b5d, 0x7a7d, 0x798a, 0x7885,
-  0x776c, 0x7642, 0x7505, 0x73b6, 0x7255, 0x70e3, 0x6f5f, 0x6dca,
-  0x6c24, 0x6a6e, 0x68a7, 0x66d0, 0x64e9, 0x62f2, 0x60ec, 0x5ed7,
-  0x5cb4, 0x5a82, 0x5843, 0x55f6, 0x539b, 0x5134, 0x4ec0, 0x4c40,
-  0x49b4, 0x471d, 0x447b, 0x41ce, 0x3f17, 0x3c57, 0x398d, 0x36ba,
-  0x33df, 0x30fc, 0x2e11, 0x2b1f, 0x2827, 0x2528, 0x2224, 0x1f1a,
-  0x1c0c, 0x18f9, 0x15e2, 0x12c8, 0xfab, 0xc8c, 0x96b, 0x648,
-  0x324, 0x0, 0xfcdc, 0xf9b8, 0xf695, 0xf374, 0xf055, 0xed38,
-  0xea1e, 0xe707, 0xe3f4, 0xe0e6, 0xdddc, 0xdad8, 0xd7d9, 0xd4e1,
-  0xd1ef, 0xcf04, 0xcc21, 0xc946, 0xc673, 0xc3a9, 0xc0e9, 0xbe32,
-  0xbb85, 0xb8e3, 0xb64c, 0xb3c0, 0xb140, 0xaecc, 0xac65, 0xaa0a,
-  0xa7bd, 0xa57e, 0xa34c, 0xa129, 0x9f14, 0x9d0e, 0x9b17, 0x9930,
-  0x9759, 0x9592, 0x93dc, 0x9236, 0x90a1, 0x8f1d, 0x8dab, 0x8c4a,
-  0x8afb, 0x89be, 0x8894, 0x877b, 0x8676, 0x8583, 0x84a3, 0x83d6,
-  0x831c, 0x8276, 0x81e2, 0x8163, 0x80f6, 0x809e, 0x8059, 0x8027,
-  0x800a, 0x8000, 0x800a, 0x8027, 0x8059, 0x809e, 0x80f6, 0x8163,
-  0x81e2, 0x8276, 0x831c, 0x83d6, 0x84a3, 0x8583, 0x8676, 0x877b,
-  0x8894, 0x89be, 0x8afb, 0x8c4a, 0x8dab, 0x8f1d, 0x90a1, 0x9236,
-  0x93dc, 0x9592, 0x9759, 0x9930, 0x9b17, 0x9d0e, 0x9f14, 0xa129,
-  0xa34c, 0xa57e, 0xa7bd, 0xaa0a, 0xac65, 0xaecc, 0xb140, 0xb3c0,
-  0xb64c, 0xb8e3, 0xbb85, 0xbe32, 0xc0e9, 0xc3a9, 0xc673, 0xc946,
-  0xcc21, 0xcf04, 0xd1ef, 0xd4e1, 0xd7d9, 0xdad8, 0xdddc, 0xe0e6,
-  0xe3f4, 0xe707, 0xea1e, 0xed38, 0xf055, 0xf374, 0xf695, 0xf9b8,
-  0xfcdc, 0x0, 0x324
-};
-
-
-/**   
- * @brief Fast approximation to the trigonometric sine function for Q15 data.   
- * @param[in] x Scaled input value in radians.   
- * @return  sin(x).   
- *   
- * The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi), Here range excludes 2*pi.   
- */
-
-q15_t arm_sin_q15(
-  q15_t x)
-{
-  q31_t sinVal;                                  /* Temporary variables output */
-  q15_t *tablePtr;                               /* Pointer to table */
-  q15_t fract, in, in2;                          /* Temporary variables for input, output */
-  q31_t wa, wb, wc, wd;                          /* Cubic interpolation coefficients */
-  q15_t a, b, c, d;                              /* Four nearest output values */
-  q15_t fractCube, fractSquare;                  /* Temporary values for fractional value */
-  q15_t oneBy6 = 0x1555;                         /* Fixed point value of 1/6 */
-  q15_t tableSpacing = TABLE_SPACING_Q15;        /* Table spacing */
-  int32_t index;                                 /* Index variable */
-
-  in = x;
-
-  /* Calculate the nearest index */
-  index = (int32_t) in / tableSpacing;
-
-  /* Calculate the nearest value of input */
-  in2 = (q15_t) ((index) * tableSpacing);
-
-  /* Calculation of fractional value */
-  fract = (in - in2) << 8;
-
-  /* fractSquare = fract * fract */
-  fractSquare = (q15_t) ((fract * fract) >> 15);
-
-  /* fractCube = fract * fract * fract */
-  fractCube = (q15_t) ((fractSquare * fract) >> 15);
-
-  /* Checking min and max index of table */
-  if(index < 0)
-  {
-    index = 0;
-  }
-  else if(index > 256)
-  {
-    index = 256;
-  }
-
-  /* Initialise table pointer */
-  tablePtr = (q15_t *) & sinTableQ15[index];
-
-  /* Cubic interpolation process */
-  /* Calculation of wa */
-  /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAA)*fract; */
-  wa = (q31_t) oneBy6 *fractCube;
-  wa += (q31_t) 0x2AAA *fract;
-  wa = -(wa >> 15);
-  wa += ((q31_t) fractSquare >> 1u);
-
-  /* Read first nearest value of output from the sin table */
-  a = *tablePtr++;
-
-  /* sinVal = a * wa */
-  sinVal = a * wa;
-
-  /* Calculation of wb */
-  wb = (((q31_t) fractCube >> 1u) - (q31_t) fractSquare) -
-    (((q31_t) fract >> 1u) - 0x7FFF);
-
-  /* Read second nearest value of output from the sin table */
-  b = *tablePtr++;
-
-  /*      sinVal += b*wb */
-  sinVal += b * wb;
-
-
-  /* Calculation of wc */
-  wc = -(q31_t) fractCube + fractSquare;
-  wc = (wc >> 1u) + fract;
-
-  /* Read third nearest value of output from the sin table */
-  c = *tablePtr++;
-
-  /* sinVal += c*wc */
-  sinVal += c * wc;
-
-  /* Calculation of wd */
-  /* wd = (oneBy6)*fractCube - (oneBy6)*fract; */
-  fractCube = fractCube - fract;
-  wd = ((q15_t) (((q31_t) oneBy6 * fractCube) >> 15));
-
-  /* Read fourth nearest value of output from the sin table */
-  d = *tablePtr++;
-
-  /* sinVal += d*wd; */
-  sinVal += d * wd;
-
-  /* Convert output value in 1.15(q15) format and saturate */
-  sinVal = __SSAT((sinVal >> 15), 16);
-
-  /* Return the output value in 1.15(q15) format */
-  return ((q15_t) sinVal);
-
-}
-
-/**    
- * @} end of sin group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q31.c
deleted file mode 100644
index cf540e24f0..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q31.c
+++ /dev/null
@@ -1,240 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_sin_q31.c    
-*    
-* Description:	Fast sine calculation for Q31 values.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFastMath    
- */
-
- /**    
- * @addtogroup sin    
- * @{    
- */
-
-/**   
- * \par    
- * Tables generated are in Q31(1.31 Fixed point format)    
- * Generation of sin values in floating point:    
- * 
tableSize = 256;      
- * for(n = -1; n < (tableSize + 1); n++)    
- * {    
- *	sinTable[n+1]= sin(2*pi*n/tableSize);    
- * } 
    
- * where pi value is  3.14159265358979    
- * \par    
- * Convert Floating point to Q31(Fixed point):    
- *	(sinTable[i] * pow(2, 31))    
- * \par    
- * rounding to nearest integer is done    
- * 	sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5);    
- */
-
-static const q31_t sinTableQ31[259] = {
-  0xfcdbd541, 0x0, 0x3242abf, 0x647d97c, 0x96a9049, 0xc8bd35e, 0xfab272b,
-  0x12c8106f,
-  0x15e21445, 0x18f8b83c, 0x1c0b826a, 0x1f19f97b, 0x2223a4c5, 0x25280c5e,
-  0x2826b928, 0x2b1f34eb,
-  0x2e110a62, 0x30fbc54d, 0x33def287, 0x36ba2014, 0x398cdd32, 0x3c56ba70,
-  0x3f1749b8, 0x41ce1e65,
-  0x447acd50, 0x471cece7, 0x49b41533, 0x4c3fdff4, 0x4ebfe8a5, 0x5133cc94,
-  0x539b2af0, 0x55f5a4d2,
-  0x5842dd54, 0x5a82799a, 0x5cb420e0, 0x5ed77c8a, 0x60ec3830, 0x62f201ac,
-  0x64e88926, 0x66cf8120,
-  0x68a69e81, 0x6a6d98a4, 0x6c242960, 0x6dca0d14, 0x6f5f02b2, 0x70e2cbc6,
-  0x72552c85, 0x73b5ebd1,
-  0x7504d345, 0x7641af3d, 0x776c4edb, 0x78848414, 0x798a23b1, 0x7a7d055b,
-  0x7b5d039e, 0x7c29fbee,
-  0x7ce3ceb2, 0x7d8a5f40, 0x7e1d93ea, 0x7e9d55fc, 0x7f0991c4, 0x7f62368f,
-  0x7fa736b4, 0x7fd8878e,
-  0x7ff62182, 0x7fffffff, 0x7ff62182, 0x7fd8878e, 0x7fa736b4, 0x7f62368f,
-  0x7f0991c4, 0x7e9d55fc,
-  0x7e1d93ea, 0x7d8a5f40, 0x7ce3ceb2, 0x7c29fbee, 0x7b5d039e, 0x7a7d055b,
-  0x798a23b1, 0x78848414,
-  0x776c4edb, 0x7641af3d, 0x7504d345, 0x73b5ebd1, 0x72552c85, 0x70e2cbc6,
-  0x6f5f02b2, 0x6dca0d14,
-  0x6c242960, 0x6a6d98a4, 0x68a69e81, 0x66cf8120, 0x64e88926, 0x62f201ac,
-  0x60ec3830, 0x5ed77c8a,
-  0x5cb420e0, 0x5a82799a, 0x5842dd54, 0x55f5a4d2, 0x539b2af0, 0x5133cc94,
-  0x4ebfe8a5, 0x4c3fdff4,
-  0x49b41533, 0x471cece7, 0x447acd50, 0x41ce1e65, 0x3f1749b8, 0x3c56ba70,
-  0x398cdd32, 0x36ba2014,
-  0x33def287, 0x30fbc54d, 0x2e110a62, 0x2b1f34eb, 0x2826b928, 0x25280c5e,
-  0x2223a4c5, 0x1f19f97b,
-  0x1c0b826a, 0x18f8b83c, 0x15e21445, 0x12c8106f, 0xfab272b, 0xc8bd35e,
-  0x96a9049, 0x647d97c,
-  0x3242abf, 0x0, 0xfcdbd541, 0xf9b82684, 0xf6956fb7, 0xf3742ca2, 0xf054d8d5,
-  0xed37ef91,
-  0xea1debbb, 0xe70747c4, 0xe3f47d96, 0xe0e60685, 0xdddc5b3b, 0xdad7f3a2,
-  0xd7d946d8, 0xd4e0cb15,
-  0xd1eef59e, 0xcf043ab3, 0xcc210d79, 0xc945dfec, 0xc67322ce, 0xc3a94590,
-  0xc0e8b648, 0xbe31e19b,
-  0xbb8532b0, 0xb8e31319, 0xb64beacd, 0xb3c0200c, 0xb140175b, 0xaecc336c,
-  0xac64d510, 0xaa0a5b2e,
-  0xa7bd22ac, 0xa57d8666, 0xa34bdf20, 0xa1288376, 0x9f13c7d0, 0x9d0dfe54,
-  0x9b1776da, 0x99307ee0,
-  0x9759617f, 0x9592675c, 0x93dbd6a0, 0x9235f2ec, 0x90a0fd4e, 0x8f1d343a,
-  0x8daad37b, 0x8c4a142f,
-  0x8afb2cbb, 0x89be50c3, 0x8893b125, 0x877b7bec, 0x8675dc4f, 0x8582faa5,
-  0x84a2fc62, 0x83d60412,
-  0x831c314e, 0x8275a0c0, 0x81e26c16, 0x8162aa04, 0x80f66e3c, 0x809dc971,
-  0x8058c94c, 0x80277872,
-  0x8009de7e, 0x80000000, 0x8009de7e, 0x80277872, 0x8058c94c, 0x809dc971,
-  0x80f66e3c, 0x8162aa04,
-  0x81e26c16, 0x8275a0c0, 0x831c314e, 0x83d60412, 0x84a2fc62, 0x8582faa5,
-  0x8675dc4f, 0x877b7bec,
-  0x8893b125, 0x89be50c3, 0x8afb2cbb, 0x8c4a142f, 0x8daad37b, 0x8f1d343a,
-  0x90a0fd4e, 0x9235f2ec,
-  0x93dbd6a0, 0x9592675c, 0x9759617f, 0x99307ee0, 0x9b1776da, 0x9d0dfe54,
-  0x9f13c7d0, 0xa1288376,
-  0xa34bdf20, 0xa57d8666, 0xa7bd22ac, 0xaa0a5b2e, 0xac64d510, 0xaecc336c,
-  0xb140175b, 0xb3c0200c,
-  0xb64beacd, 0xb8e31319, 0xbb8532b0, 0xbe31e19b, 0xc0e8b648, 0xc3a94590,
-  0xc67322ce, 0xc945dfec,
-  0xcc210d79, 0xcf043ab3, 0xd1eef59e, 0xd4e0cb15, 0xd7d946d8, 0xdad7f3a2,
-  0xdddc5b3b, 0xe0e60685,
-  0xe3f47d96, 0xe70747c4, 0xea1debbb, 0xed37ef91, 0xf054d8d5, 0xf3742ca2,
-  0xf6956fb7, 0xf9b82684,
-  0xfcdbd541, 0x0, 0x3242abf
-};
-
-
-/**   
- * @brief Fast approximation to the trigonometric sine function for Q31 data.   
- * @param[in] x Scaled input value in radians.   
- * @return  sin(x).   
- *   
- * The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi), Here range excludes 2*pi.   
- */
-
-q31_t arm_sin_q31(
-  q31_t x)
-{
-  q31_t sinVal, in, in2;                         /* Temporary variables for input, output */
-  int32_t index;                                 /* Index variables */
-  q31_t wa, wb, wc, wd;                          /* Cubic interpolation coefficients */
-  q31_t a, b, c, d;                              /* Four nearest output values */
-  q31_t *tablePtr;                               /* Pointer to table */
-  q31_t fract, fractCube, fractSquare;           /* Temporary values for fractional values */
-  q31_t oneBy6 = 0x15555555;                     /* Fixed point value of 1/6 */
-  q31_t tableSpacing = TABLE_SPACING_Q31;        /* Table spacing */
-  q31_t temp;                                    /* Temporary variable for intermediate process */
-
-  in = x;
-
-  /* Calculate the nearest index */
-  index = (uint32_t) in / (uint32_t) tableSpacing;
-
-  /* Calculate the nearest value of input */
-  in2 = (q31_t) index *tableSpacing;
-
-  /* Calculation of fractional value */
-  fract = (in - in2) << 8;
-
-  /* fractSquare = fract * fract */
-  fractSquare = ((q31_t) (((q63_t) fract * fract) >> 32));
-  fractSquare = fractSquare << 1;
-
-  /* fractCube = fract * fract * fract */
-  fractCube = ((q31_t) (((q63_t) fractSquare * fract) >> 32));
-  fractCube = fractCube << 1;
-
-  /* Checking min and max index of table */
-  if(index < 0)
-  {
-    index = 0;
-  }
-  else if(index > 256)
-  {
-    index = 256;
-  }
-
-  /* Initialise table pointer */
-  tablePtr = (q31_t *) & sinTableQ31[index];
-
-  /* Cubic interpolation process */
-  /* Calculation of wa */
-  /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAAAAAA)*fract; */
-  wa = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));
-  temp = 0x2AAAAAAA;
-  wa = (q31_t) ((((q63_t) wa << 32) + ((q63_t) temp * fract)) >> 32);
-  wa = -(wa << 1u);
-  wa += (fractSquare >> 1u);
-
-  /* Read first nearest value of output from the sin table */
-  a = *tablePtr++;
-
-  /* sinVal = a*wa */
-  sinVal = ((q31_t) (((q63_t) a * wa) >> 32));
-
-  /* q31(1.31) Fixed point value of 1 */
-  temp = 0x7FFFFFFF;
-
-  /* Calculation of wb */
-  wb = ((fractCube >> 1u) - (fractSquare + (fract >> 1u))) + temp;
-
-  /* Read second nearest value of output from the sin table */
-  b = *tablePtr++;
-
-  /*  sinVal += b*wb */
-  sinVal = (q31_t) ((((q63_t) sinVal << 32) + (q63_t) b * (wb)) >> 32);
-
-  /* Calculation of wc */
-  wc = -fractCube + fractSquare;
-  wc = (wc >> 1u) + fract;
-
-  /* Read third nearest value of output from the sin table */
-  c = *tablePtr++;
-
-  /*      sinVal += c*wc */
-  sinVal = (q31_t) ((((q63_t) sinVal << 32) + ((q63_t) c * wc)) >> 32);
-
-  /* Calculation of wd */
-  /* wd = (oneBy6) * fractCube - (oneBy6) * fract; */
-  fractCube = fractCube - fract;
-  wd = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));
-  wd = (wd << 1u);
-
-  /* Read fourth nearest value of output from the sin table */
-  d = *tablePtr++;
-
-  /* sinVal += d*wd; */
-  sinVal = (q31_t) ((((q63_t) sinVal << 32) + ((q63_t) d * wd)) >> 32);
-
-  /* convert sinVal in 2.30 format to 1.31 format */
-  return (__QADD(sinVal, sinVal));
-
-}
-
-/**    
- * @} end of sin group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q15.c
deleted file mode 100644
index 32eee32522..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q15.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/* ----------------------------------------------------------------------     
-* Copyright (C) 2011 ARM Limited. All rights reserved.  
-*     
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*     
-* Project:      CMSIS DSP Library  
-* Title:		arm_sqrt_q15.c     
-*     
-* Description:	Q15 square root function.    
-*     
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-* 
-* Version 1.0.0 2011/03/08 
-*     Alpha release. 
-* 
-* Version 1.0.1 2011/09/30 
-*     Beta release.  
-*     
-* -------------------------------------------------------------------- */
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-
-/**     
- * @ingroup groupFastMath     
- */
-
-/**     
- * @addtogroup SQRT     
- * @{     
- */
-
-  /**    
-   * @brief  Q15 square root function.    
-   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.    
-   * @param[out]  *pOut  square root of input value.    
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if    
-   * in is negative value and returns zero output for negative values.    
-   */
-
-arm_status arm_sqrt_q15(
-  q15_t in,
-  q15_t * pOut)
-{
-  q15_t number, temp1, var1, signBits1, half;
-  q31_t bits_val1;
-  float32_t temp_float1;
-
-  number = in;
-
-  /* If the input is a positive number then compute the signBits. */
-  if(number > 0)
-  {
-    signBits1 = __CLZ(number) - 17;
-
-    /* Shift by the number of signBits1 */
-    if((signBits1 % 2) == 0)
-    {
-      number = number << signBits1;
-    }
-    else
-    {
-      number = number << (signBits1 - 1);
-    }
-
-    /* Calculate half value of the number */
-    half = number >> 1;
-    /* Store the number for later use */
-    temp1 = number;
-
-    /*Convert to float */
-    temp_float1 = number * 3.051757812500000e-005f;
-    /*Store as integer */
-    bits_val1 = *(int *) &temp_float1;
-    /* Subtract the shifted value from the magic number to give intial guess */
-    bits_val1 = 0x5f3759df - (bits_val1 >> 1);  // gives initial guess  
-    /* Store as float */
-    temp_float1 = *(float *) &bits_val1;
-    /* Convert to integer format */
-    var1 = (q31_t) (temp_float1 * 16384);
-
-    /* 1st iteration */
-    var1 = ((q15_t) ((q31_t) var1 * (0x3000 -
-                                     ((q15_t)
-                                      ((((q15_t)
-                                         (((q31_t) var1 * var1) >> 15)) *
-                                        (q31_t) half) >> 15))) >> 15)) << 2;
-    /* 2nd iteration */
-    var1 = ((q15_t) ((q31_t) var1 * (0x3000 -
-                                     ((q15_t)
-                                      ((((q15_t)
-                                         (((q31_t) var1 * var1) >> 15)) *
-                                        (q31_t) half) >> 15))) >> 15)) << 2;
-    /* 3rd iteration */
-    var1 = ((q15_t) ((q31_t) var1 * (0x3000 -
-                                     ((q15_t)
-                                      ((((q15_t)
-                                         (((q31_t) var1 * var1) >> 15)) *
-                                        (q31_t) half) >> 15))) >> 15)) << 2;
-
-    /* Multiply the inverse square root with the original value */
-    var1 = ((q15_t) (((q31_t) temp1 * var1) >> 15)) << 1;
-
-    /* Shift the output down accordingly */
-    if((signBits1 % 2) == 0)
-    {
-      var1 = var1 >> (signBits1 / 2);
-    }
-    else
-    {
-      var1 = var1 >> ((signBits1 - 1) / 2);
-    }
-    *pOut = var1;
-
-    return (ARM_MATH_SUCCESS);
-  }
-  /* If the number is a negative number then store zero as its square root value */
-  else
-  {
-    *pOut = 0;
-    return (ARM_MATH_ARGUMENT_ERROR);
-  }
-}
-
-/**     
- * @} end of SQRT group     
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q31.c
deleted file mode 100644
index 65de4b3d16..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q31.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/* ----------------------------------------------------------------------     
-* Copyright (C) 2011 ARM Limited. All rights reserved.  
-*     
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*     
-* Project:      CMSIS DSP Library  
-* Title:		arm_sqrt_q31.c     
-*     
-* Description:	Q31 square root function.    
-*     
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-* 
-* Version 1.0.0 2011/03/08 
-*     Alpha release. 
-* 
-* Version 1.0.1 2011/09/30 
-*     Beta release.  
-*     
-* -------------------------------------------------------------------- */
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**     
- * @ingroup groupFastMath     
- */
-
-/**     
- * @addtogroup SQRT     
- * @{     
- */
-
-/**    
- * @brief Q31 square root function.    
- * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.    
- * @param[out]  *pOut square root of input value.    
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if    
- * in is negative value and returns zero output for negative values.    
- */
-
-arm_status arm_sqrt_q31(
-  q31_t in,
-  q31_t * pOut)
-{
-  q31_t number, temp1, bits_val1, var1, signBits1, half;
-  float32_t temp_float1;
-
-  number = in;
-
-  /* If the input is a positive number then compute the signBits. */
-  if(number > 0)
-  {
-    signBits1 = __CLZ(number) - 1;
-
-    /* Shift by the number of signBits1 */
-    if((signBits1 % 2) == 0)
-    {
-      number = number << signBits1;
-    }
-    else
-    {
-      number = number << (signBits1 - 1);
-    }
-
-    /* Calculate half value of the number */
-    half = number >> 1;
-    /* Store the number for later use */
-    temp1 = number;
-
-    /*Convert to float */
-    temp_float1 = number * 4.6566128731e-010f;
-    /*Store as integer */
-    bits_val1 = *(int *) &temp_float1;
-    /* Subtract the shifted value from the magic number to give intial guess */
-    bits_val1 = 0x5f3759df - (bits_val1 >> 1);  // gives initial guess  
-    /* Store as float */
-    temp_float1 = *(float *) &bits_val1;
-    /* Convert to integer format */
-    var1 = (q31_t) (temp_float1 * 1073741824);
-
-    /* 1st iteration */
-    var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -
-                                     ((q31_t)
-                                      ((((q31_t)
-                                         (((q63_t) var1 * var1) >> 31)) *
-                                        (q63_t) half) >> 31))) >> 31)) << 2;
-    /* 2nd iteration */
-    var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -
-                                     ((q31_t)
-                                      ((((q31_t)
-                                         (((q63_t) var1 * var1) >> 31)) *
-                                        (q63_t) half) >> 31))) >> 31)) << 2;
-    /* 3rd iteration */
-    var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -
-                                     ((q31_t)
-                                      ((((q31_t)
-                                         (((q63_t) var1 * var1) >> 31)) *
-                                        (q63_t) half) >> 31))) >> 31)) << 2;
-
-    /* Multiply the inverse square root with the original value */
-    var1 = ((q31_t) (((q63_t) temp1 * var1) >> 31)) << 1;
-
-    /* Shift the output down accordingly */
-    if((signBits1 % 2) == 0)
-    {
-      var1 = var1 >> (signBits1 / 2);
-    }
-    else
-    {
-      var1 = var1 >> ((signBits1 - 1) / 2);
-    }
-    *pOut = var1;
-
-    return (ARM_MATH_SUCCESS);
-  }
-  /* If the number is a negative number then store zero as its square root value */
-  else
-  {
-    *pOut = 0;
-    return (ARM_MATH_ARGUMENT_ERROR);
-  }
-}
-
-/**     
- * @} end of SQRT group     
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
deleted file mode 100644
index 4ca7111b39..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_biquad_cascade_df1_32x64_init_q31.c    
-*    
-* Description:	High precision Q31 Biquad cascade filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup BiquadCascadeDF1_32x64    
- * @{    
- */
-
-/**    
- * @details    
- *    
- * @param[in,out] *S           	points to an instance of the high precision Q31 Biquad cascade filter structure.    
- * @param[in]     numStages     number of 2nd order stages in the filter.    
- * @param[in]     *pCoeffs      points to the filter coefficients.    
- * @param[in]     *pState       points to the state buffer.    
- * @param[in]     postShift     Shift to be applied after the accumulator.  Varies according to the coefficients format.    
- * @return        none    
- *    
- * Coefficient and State Ordering:    
- *    
- * \par    
- * The coefficients are stored in the array pCoeffs in the following order:    
- * 
    
- *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    
- * 
    
- * where b1x and a1x are the coefficients for the first stage,    
- * b2x and a2x are the coefficients for the second stage,    
- * and so on.  The pCoeffs array contains a total of 5*numStages values.    
- *    
- * \par    
- * The pState points to state variables array and size of each state variable is 1.63 format.    
- * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].    
- * The state variables are arranged in the state array as:    
- * 
    
- *     {x[n-1], x[n-2], y[n-1], y[n-2]}    
- * 
    
- * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    
- * The state array has a total length of 4*numStages values.    
- * The state variables are updated after each block of data is processed; the coefficients are untouched.    
- */
-
-void arm_biquad_cas_df1_32x64_init_q31(
-  arm_biquad_cas_df1_32x64_ins_q31 * S,
-  uint8_t numStages,
-  q31_t * pCoeffs,
-  q63_t * pState,
-  uint8_t postShift)
-{
-  /* Assign filter stages */
-  S->numStages = numStages;
-
-  /* Assign postShift to be applied to the output */
-  S->postShift = postShift;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and size is always 4 * numStages */
-  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q63_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-}
-
-/**    
- * @} end of BiquadCascadeDF1_32x64 group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
deleted file mode 100644
index 607f7f5074..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
+++ /dev/null
@@ -1,553 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_biquad_cascade_df1_32x64_q31.c    
-*    
-* Description:	High precision Q31 Biquad cascade filter processing function    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @defgroup BiquadCascadeDF1_32x64 High Precision Q31 Biquad Cascade Filter    
- *    
- * This function implements a high precision Biquad cascade filter which operates on    
- * Q31 data values.  The filter coefficients are in 1.31 format and the state variables    
- * are in 1.63 format.  The double precision state variables reduce quantization noise    
- * in the filter and provide a cleaner output.    
- * These filters are particularly useful when implementing filters in which the    
- * singularities are close to the unit circle.  This is common for low pass or high    
- * pass filters with very low cutoff frequencies.    
- *    
- * The function operates on blocks of input and output data    
- * and each call to the function processes blockSize samples through    
- * the filter. pSrc and pDst points to input and output arrays    
- * containing blockSize Q31 values.    
- *    
- * \par Algorithm    
- * Each Biquad stage implements a second order filter using the difference equation:    
- * 
    
- *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    
- * 
    
- * A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage.    
- * \image html Biquad.gif "Single Biquad filter stage"    
- * Coefficients b0, b1, and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients.    
- * Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.    
- * Pay careful attention to the sign of the feedback coefficients.    
- * Some design tools use the difference equation    
- * 
    
- *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]    
- * 
    
- * In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.    
- *    
- * \par    
- * Higher order filters are realized as a cascade of second order sections.    
- * numStages refers to the number of second order stages used.    
- * For example, an 8th order filter would be realized with numStages=4 second order stages.    
- * \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages"    
- * A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).    
- *    
- * \par    
- * The pState points to state variables array .    
- * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2] and each state variable in 1.63 format to improve precision.    
- * The state variables are arranged in the array as:    
- * 
    
- *     {x[n-1], x[n-2], y[n-1], y[n-2]}    
- * 
    
- *    
- * \par    
- * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    
- * The state array has a total length of 4*numStages values of data in 1.63 format.    
- * The state variables are updated after each block of data is processed; the coefficients are untouched.    
- *    
- * \par Instance Structure    
- * The coefficients and state variables for a filter are stored together in an instance data structure.    
- * A separate instance structure must be defined for each filter.    
- * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.    
- *    
- * \par Init Function    
- * There is also an associated initialization function which performs the following operations:    
- * - Sets the values of the internal structure fields.    
- * - Zeros out the values in the state buffer.    
- * \par    
- * Use of the initialization function is optional.    
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
- * To place an instance structure into a const data section, the instance structure must be manually initialized.    
- * Set the values in the state buffer to zeros before static initialization.    
- * For example, to statically initialize the filter instance structure use    
- * 
    
- *     arm_biquad_cas_df1_32x64_ins_q31 S1 = {numStages, pState, pCoeffs, postShift};    
- * 
    
- * where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer;    
- * pCoeffs is the address of the coefficient buffer; postShift shift to be applied which is described in detail below.    
- * \par Fixed-Point Behavior    
- * Care must be taken while using Biquad Cascade 32x64 filter function.    
- * Following issues must be considered:    
- * - Scaling of coefficients    
- * - Filter gain    
- * - Overflow and saturation    
- *    
- * \par    
- * Filter coefficients are represented as fractional values and    
- * restricted to lie in the range [-1 +1).    
- * The processing function has an additional scaling parameter postShift    
- * which allows the filter coefficients to exceed the range [+1 -1).    
- * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.    
- * \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator"    
- * This essentially scales the filter coefficients by 2^postShift.    
- * For example, to realize the coefficients    
- * 
    
- *    {1.5, -0.8, 1.2, 1.6, -0.9}    
- * 
    
- * set the Coefficient array to:    
- * 
    
- *    {0.75, -0.4, 0.6, 0.8, -0.45}    
- * 
    
- * and set postShift=1    
- *    
- * \par    
- * The second thing to keep in mind is the gain through the filter.    
- * The frequency response of a Biquad filter is a function of its coefficients.    
- * It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies.    
- * This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter.    
- * To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.    
- *    
- * \par    
- * The third item to consider is the overflow and saturation behavior of the fixed-point Q31 version.    
- * This is described in the function specific documentation below.    
- */
-
-/**    
- * @addtogroup BiquadCascadeDF1_32x64    
- * @{    
- */
-
-/**    
- * @details    
-    
- * @param[in]  *S points to an instance of the high precision Q31 Biquad cascade filter.    
- * @param[in]  *pSrc points to the block of input data.    
- * @param[out] *pDst points to the block of output data.    
- * @param[in]  blockSize number of samples to process.    
- * @return none.    
- *    
- * \par    
- * The function is implemented using an internal 64-bit accumulator.    
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
- * Thus, if the accumulator result overflows it wraps around rather than clip.    
- * In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25).    
- * After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to    
- * 1.31 format by discarding the low 32 bits.    
- *    
- * \par    
- * Two related functions are provided in the CMSIS DSP library.    
- * arm_biquad_cascade_df1_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q63 accumulator.    
- * arm_biquad_cascade_df1_fast_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q31 accumulator.    
- */
-
-void arm_biquad_cas_df1_32x64_q31(
-  const arm_biquad_cas_df1_32x64_ins_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  q31_t *pIn = pSrc;                             /*  input pointer initialization  */
-  q31_t *pOut = pDst;                            /*  output pointer initialization */
-  q63_t *pState = S->pState;                     /*  state pointer initialization  */
-  q31_t *pCoeffs = S->pCoeffs;                   /*  coeff pointer initialization  */
-  q63_t acc;                                     /*  accumulator                   */
-  q31_t Xn1, Xn2;                                /*  Input Filter state variables        */
-  q63_t Yn1, Yn2;                                /*  Output Filter state variables        */
-  q31_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
-  q31_t Xn;                                      /*  temporary input               */
-  int32_t shift = (int32_t) S->postShift + 1;    /*  Shift to be applied to the output */
-  uint32_t sample, stage = S->numStages;         /*  loop counters                     */
-  q31_t acc_l, acc_h;                            /*  temporary output               */
-  uint32_t uShift = ((uint32_t) S->postShift + 1u);
-  uint32_t lShift = 32u - uShift;                /*  Shift to be applied to the output */
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  do
-  {
-    /* Reading the coefficients */
-    b0 = *pCoeffs++;
-    b1 = *pCoeffs++;
-    b2 = *pCoeffs++;
-    a1 = *pCoeffs++;
-    a2 = *pCoeffs++;
-
-    /* Reading the state values */
-    Xn1 = (q31_t) (pState[0]);
-    Xn2 = (q31_t) (pState[1]);
-    Yn1 = pState[2];
-    Yn2 = pState[3];
-
-    /* Apply loop unrolling and compute 4 output values simultaneously. */
-    /* The variable acc hold output value that is being computed and    
-     * stored in the destination buffer    
-     * acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    
-     */
-
-    sample = blockSize >> 2u;
-
-    /* First part of the processing with loop unrolling. Compute 4 outputs at a time.    
-     ** a second loop below computes the remaining 1 to 3 samples. */
-    while(sample > 0u)
-    {
-      /* Read the input */
-      Xn = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-
-      /* acc =  b0 * x[n] */
-      acc = (q63_t) Xn *b0;
-
-      /* acc +=  b1 * x[n-1] */
-      acc += (q63_t) Xn1 *b1;
-
-      /* acc +=  b[2] * x[n-2] */
-      acc += (q63_t) Xn2 *b2;
-
-      /* acc +=  a1 * y[n-1] */
-      acc += mult32x64(Yn1, a1);
-
-      /* acc +=  a2 * y[n-2] */
-      acc += mult32x64(Yn2, a2);
-
-      /* The result is converted to 1.63 , Yn2 variable is reused */
-      Yn2 = acc << shift;
-
-      /* Calc lower part of acc */
-      acc_l = acc & 0xffffffff;
-
-      /* Calc upper part of acc */
-      acc_h = (acc >> 32) & 0xffffffff;
-
-      /* Apply shift for lower part of acc and upper part of acc */
-      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-      /* Store the output in the destination buffer in 1.31 format. */
-      *pOut = acc_h;
-
-      /* Read the second input into Xn2, to reuse the value */
-      Xn2 = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-
-      /* acc +=  b1 * x[n-1] */
-      acc = (q63_t) Xn *b1;
-
-      /* acc =  b0 * x[n] */
-      acc += (q63_t) Xn2 *b0;
-
-      /* acc +=  b[2] * x[n-2] */
-      acc += (q63_t) Xn1 *b2;
-
-      /* acc +=  a1 * y[n-1] */
-      acc += mult32x64(Yn2, a1);
-
-      /* acc +=  a2 * y[n-2] */
-      acc += mult32x64(Yn1, a2);
-
-      /* The result is converted to 1.63, Yn1 variable is reused */
-      Yn1 = acc << shift;
-
-      /* Calc lower part of acc */
-      acc_l = acc & 0xffffffff;
-
-      /* Calc upper part of acc */
-      acc_h = (acc >> 32) & 0xffffffff;
-
-      /* Apply shift for lower part of acc and upper part of acc */
-      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-      /* Read the third input into Xn1, to reuse the value */
-      Xn1 = *pIn++;
-
-      /* The result is converted to 1.31 */
-      /* Store the output in the destination buffer. */
-      *(pOut + 1u) = acc_h;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-
-      /* acc =  b0 * x[n] */
-      acc = (q63_t) Xn1 *b0;
-
-      /* acc +=  b1 * x[n-1] */
-      acc += (q63_t) Xn2 *b1;
-
-      /* acc +=  b[2] * x[n-2] */
-      acc += (q63_t) Xn *b2;
-
-      /* acc +=  a1 * y[n-1] */
-      acc += mult32x64(Yn1, a1);
-
-      /* acc +=  a2 * y[n-2] */
-      acc += mult32x64(Yn2, a2);
-
-      /* The result is converted to 1.63, Yn2 variable is reused  */
-      Yn2 = acc << shift;
-
-      /* Calc lower part of acc */
-      acc_l = acc & 0xffffffff;
-
-      /* Calc upper part of acc */
-      acc_h = (acc >> 32) & 0xffffffff;
-
-      /* Apply shift for lower part of acc and upper part of acc */
-      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-      /* Store the output in the destination buffer in 1.31 format. */
-      *(pOut + 2u) = acc_h;
-
-      /* Read the fourth input into Xn, to reuse the value */
-      Xn = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-      /* acc =  b0 * x[n] */
-      acc = (q63_t) Xn *b0;
-
-      /* acc +=  b1 * x[n-1] */
-      acc += (q63_t) Xn1 *b1;
-
-      /* acc +=  b[2] * x[n-2] */
-      acc += (q63_t) Xn2 *b2;
-
-      /* acc +=  a1 * y[n-1] */
-      acc += mult32x64(Yn2, a1);
-
-      /* acc +=  a2 * y[n-2] */
-      acc += mult32x64(Yn1, a2);
-
-      /* The result is converted to 1.63, Yn1 variable is reused  */
-      Yn1 = acc << shift;
-
-      /* Calc lower part of acc */
-      acc_l = acc & 0xffffffff;
-
-      /* Calc upper part of acc */
-      acc_h = (acc >> 32) & 0xffffffff;
-
-      /* Apply shift for lower part of acc and upper part of acc */
-      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-      /* Store the output in the destination buffer in 1.31 format. */
-      *(pOut + 3u) = acc_h;
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc    */
-      Xn2 = Xn1;
-      Xn1 = Xn;
-
-      /* update output pointer */
-      pOut += 4u;
-
-      /* decrement the loop counter */
-      sample--;
-    }
-
-    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-     ** No loop unrolling is used. */
-    sample = (blockSize & 0x3u);
-
-    while(sample > 0u)
-    {
-      /* Read the input */
-      Xn = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-
-      /* acc =  b0 * x[n] */
-      acc = (q63_t) Xn *b0;
-      /* acc +=  b1 * x[n-1] */
-      acc += (q63_t) Xn1 *b1;
-      /* acc +=  b[2] * x[n-2] */
-      acc += (q63_t) Xn2 *b2;
-      /* acc +=  a1 * y[n-1] */
-      acc += mult32x64(Yn1, a1);
-      /* acc +=  a2 * y[n-2] */
-      acc += mult32x64(Yn2, a2);
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc    */
-      Xn2 = Xn1;
-      Xn1 = Xn;
-      Yn2 = Yn1;
-      /* The result is converted to 1.63, Yn1 variable is reused  */
-      Yn1 = acc << shift;
-
-      /* Calc lower part of acc */
-      acc_l = acc & 0xffffffff;
-
-      /* Calc upper part of acc */
-      acc_h = (acc >> 32) & 0xffffffff;
-
-      /* Apply shift for lower part of acc and upper part of acc */
-      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-      /* Store the output in the destination buffer in 1.31 format. */
-      *pOut++ = acc_h;
-      //Yn1 = acc << shift; 
-
-      /* Store the output in the destination buffer in 1.31 format. */
-//      *pOut++ = (q31_t) (acc >> (32 - shift)); 
-
-      /* decrement the loop counter */
-      sample--;
-    }
-
-    /*  The first stage output is given as input to the second stage. */
-    pIn = pDst;
-
-    /* Reset to destination buffer working pointer */
-    pOut = pDst;
-
-    /*  Store the updated state variables back into the pState array */
-    /*  Store the updated state variables back into the pState array */
-    *pState++ = (q63_t) Xn1;
-    *pState++ = (q63_t) Xn2;
-    *pState++ = Yn1;
-    *pState++ = Yn2;
-
-  } while(--stage);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  do
-  {
-    /* Reading the coefficients */
-    b0 = *pCoeffs++;
-    b1 = *pCoeffs++;
-    b2 = *pCoeffs++;
-    a1 = *pCoeffs++;
-    a2 = *pCoeffs++;
-
-    /* Reading the state values */
-    Xn1 = pState[0];
-    Xn2 = pState[1];
-    Yn1 = pState[2];
-    Yn2 = pState[3];
-
-    /* The variable acc hold output value that is being computed and        
-     * stored in the destination buffer            
-     * acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]            
-     */
-
-    sample = blockSize;
-
-    while(sample > 0u)
-    {
-      /* Read the input */
-      Xn = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-      /* acc =  b0 * x[n] */
-      acc = (q63_t) Xn *b0;
-      /* acc +=  b1 * x[n-1] */
-      acc += (q63_t) Xn1 *b1;
-      /* acc +=  b[2] * x[n-2] */
-      acc += (q63_t) Xn2 *b2;
-      /* acc +=  a1 * y[n-1] */
-      acc += mult32x64(Yn1, a1);
-      /* acc +=  a2 * y[n-2] */
-      acc += mult32x64(Yn2, a2);
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc    */
-      Xn2 = Xn1;
-      Xn1 = Xn;
-      Yn2 = Yn1;
-
-      /* The result is converted to 1.63, Yn1 variable is reused  */
-      Yn1 = acc << shift;
-
-      /* Calc lower part of acc */
-      acc_l = acc & 0xffffffff;
-
-      /* Calc upper part of acc */
-      acc_h = (acc >> 32) & 0xffffffff;
-
-      /* Apply shift for lower part of acc and upper part of acc */
-      acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-      /* Store the output in the destination buffer in 1.31 format. */
-      *pOut++ = acc_h;
-
-      //Yn1 = acc << shift; 
-
-      /* Store the output in the destination buffer in 1.31 format. */
-      //*pOut++ = (q31_t) (acc >> (32 - shift)); 
-
-      /* decrement the loop counter */
-      sample--;
-    }
-
-    /*  The first stage output is given as input to the second stage. */
-    pIn = pDst;
-
-    /* Reset to destination buffer working pointer */
-    pOut = pDst;
-
-    /*  Store the updated state variables back into the pState array */
-    *pState++ = (q63_t) Xn1;
-    *pState++ = (q63_t) Xn2;
-    *pState++ = Yn1;
-    *pState++ = Yn2;
-
-  } while(--stage);
-
-#endif /*    #ifndef ARM_MATH_CM0     */
-}
-
-  /**    
-   * @} end of BiquadCascadeDF1_32x64 group    
-   */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c
deleted file mode 100644
index 4ea80e1615..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c
+++ /dev/null
@@ -1,421 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_biquad_cascade_df1_f32.c    
-*    
-* Description:	Processing function for the    
-*               floating-point Biquad cascade DirectFormI(DF1) filter.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-* 	 incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @defgroup BiquadCascadeDF1 Biquad Cascade IIR Filters Using Direct Form I Structure    
- *    
- * This set of functions implements arbitrary order recursive (IIR) filters.    
- * The filters are implemented as a cascade of second order Biquad sections.    
- * The functions support Q15, Q31 and floating-point data types.  
- * Fast version of Q15 and Q31 also supported on CortexM4 and Cortex-M3.    
- *    
- * The functions operate on blocks of input and output data and each call to the function    
- * processes blockSize samples through the filter.    
- * pSrc points to the array of input data and    
- * pDst points to the array of output data.    
- * Both arrays contain blockSize values.    
- *    
- * \par Algorithm    
- * Each Biquad stage implements a second order filter using the difference equation:    
- * 
    
- *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    
- * 
    
- * A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage.    
- * \image html Biquad.gif "Single Biquad filter stage"    
- * Coefficients b0, b1 and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients.    
- * Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.    
- * Pay careful attention to the sign of the feedback coefficients.    
- * Some design tools use the difference equation    
- * 
    
- *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]    
- * 
    
- * In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.    
- *    
- * \par    
- * Higher order filters are realized as a cascade of second order sections.    
- * numStages refers to the number of second order stages used.    
- * For example, an 8th order filter would be realized with numStages=4 second order stages.    
- * \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages"    
- * A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).    
- *    
- * \par    
- * The pState points to state variables array.    
- * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].    
- * The state variables are arranged in the pState array as:    
- * 
    
- *     {x[n-1], x[n-2], y[n-1], y[n-2]}    
- * 
    
- *    
- * \par    
- * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    
- * The state array has a total length of 4*numStages values.    
- * The state variables are updated after each block of data is processed, the coefficients are untouched.    
- *    
- * \par Instance Structure    
- * The coefficients and state variables for a filter are stored together in an instance data structure.    
- * A separate instance structure must be defined for each filter.    
- * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.    
- * There are separate instance structure declarations for each of the 3 supported data types.    
- *    
- * \par Init Functions    
- * There is also an associated initialization function for each data type.    
- * The initialization function performs following operations:    
- * - Sets the values of the internal structure fields.    
- * - Zeros out the values in the state buffer.    
- *    
- * \par    
- * Use of the initialization function is optional.    
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
- * To place an instance structure into a const data section, the instance structure must be manually initialized.    
- * Set the values in the state buffer to zeros before static initialization.    
- * The code below statically initializes each of the 3 different data type filter instance structures    
- * 
    
- *     arm_biquad_casd_df1_inst_f32 S1 = {numStages, pState, pCoeffs};    
- *     arm_biquad_casd_df1_inst_q15 S2 = {numStages, pState, pCoeffs, postShift};    
- *     arm_biquad_casd_df1_inst_q31 S3 = {numStages, pState, pCoeffs, postShift};    
- * 
    
- * where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer;    
- * pCoeffs is the address of the coefficient buffer; postShift shift to be applied.    
- *    
- * \par Fixed-Point Behavior    
- * Care must be taken when using the Q15 and Q31 versions of the Biquad Cascade filter functions.    
- * Following issues must be considered:    
- * - Scaling of coefficients    
- * - Filter gain    
- * - Overflow and saturation    
- *    
- * \par    
- * Scaling of coefficients:     
- * Filter coefficients are represented as fractional values and    
- * coefficients are restricted to lie in the range [-1 +1).    
- * The fixed-point functions have an additional scaling parameter postShift    
- * which allow the filter coefficients to exceed the range [+1 -1).    
- * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.    
- * \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator"    
- * This essentially scales the filter coefficients by 2^postShift.    
- * For example, to realize the coefficients    
- * 
    
- *    {1.5, -0.8, 1.2, 1.6, -0.9}    
- * 
    
- * set the pCoeffs array to:    
- * 
    
- *    {0.75, -0.4, 0.6, 0.8, -0.45}    
- * 
    
- * and set postShift=1    
- *    
- * \par    
- * Filter gain:     
- * The frequency response of a Biquad filter is a function of its coefficients.    
- * It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies.    
- * This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter.    
- * To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.    
- *    
- * \par    
- * Overflow and saturation:     
- * For Q15 and Q31 versions, it is described separately as part of the function specific documentation below.    
- */
-
-/**    
- * @addtogroup BiquadCascadeDF1    
- * @{    
- */
-
-/**    
- * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.    
- * @param[in]  *pSrc      points to the block of input data.    
- * @param[out] *pDst      points to the block of output data.    
- * @param[in]  blockSize  number of samples to process per call.    
- * @return     none.    
- *    
- */
-
-void arm_biquad_cascade_df1_f32(
-  const arm_biquad_casd_df1_inst_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize)
-{
-  float32_t *pIn = pSrc;                         /*  source pointer            */
-  float32_t *pOut = pDst;                        /*  destination pointer       */
-  float32_t *pState = S->pState;                 /*  pState pointer            */
-  float32_t *pCoeffs = S->pCoeffs;               /*  coefficient pointer       */
-  float32_t acc;                                 /*  Simulates the accumulator */
-  float32_t b0, b1, b2, a1, a2;                  /*  Filter coefficients       */
-  float32_t Xn1, Xn2, Yn1, Yn2;                  /*  Filter pState variables   */
-  float32_t Xn;                                  /*  temporary input           */
-  uint32_t sample, stage = S->numStages;         /*  loop counters             */
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  do
-  {
-    /* Reading the coefficients */
-    b0 = *pCoeffs++;
-    b1 = *pCoeffs++;
-    b2 = *pCoeffs++;
-    a1 = *pCoeffs++;
-    a2 = *pCoeffs++;
-
-    /* Reading the pState values */
-    Xn1 = pState[0];
-    Xn2 = pState[1];
-    Yn1 = pState[2];
-    Yn2 = pState[3];
-
-    /* Apply loop unrolling and compute 4 output values simultaneously. */
-    /*      The variable acc hold output values that are being computed:    
-     *    
-     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]    
-     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]    
-     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]    
-     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]    
-     */
-
-    sample = blockSize >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-     ** a second loop below computes the remaining 1 to 3 samples. */
-    while(sample > 0u)
-    {
-      /* Read the first input */
-      Xn = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-      Yn2 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = Yn2;
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc   */
-
-      /* Read the second input */
-      Xn2 = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-      Yn1 = (b0 * Xn2) + (b1 * Xn) + (b2 * Xn1) + (a1 * Yn2) + (a2 * Yn1);
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = Yn1;
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc   */
-
-      /* Read the third input */
-      Xn1 = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-      Yn2 = (b0 * Xn1) + (b1 * Xn2) + (b2 * Xn) + (a1 * Yn1) + (a2 * Yn2);
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = Yn2;
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as: */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc   */
-
-      /* Read the forth input */
-      Xn = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-      Yn1 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn2) + (a2 * Yn1);
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = Yn1;
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc   */
-      Xn2 = Xn1;
-      Xn1 = Xn;
-
-      /* decrement the loop counter */
-      sample--;
-
-    }
-
-    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-     ** No loop unrolling is used. */
-    sample = blockSize & 0x3u;
-
-    while(sample > 0u)
-    {
-      /* Read the input */
-      Xn = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-      acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = acc;
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:    */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc   */
-      Xn2 = Xn1;
-      Xn1 = Xn;
-      Yn2 = Yn1;
-      Yn1 = acc;
-
-      /* decrement the loop counter */
-      sample--;
-
-    }
-
-    /*  Store the updated state variables back into the pState array */
-    *pState++ = Xn1;
-    *pState++ = Xn2;
-    *pState++ = Yn1;
-    *pState++ = Yn2;
-
-    /*  The first stage goes from the input buffer to the output buffer. */
-    /*  Subsequent numStages  occur in-place in the output buffer */
-    pIn = pDst;
-
-    /* Reset the output pointer */
-    pOut = pDst;
-
-    /* decrement the loop counter */
-    stage--;
-
-  } while(stage > 0u);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  do
-  {
-    /* Reading the coefficients */
-    b0 = *pCoeffs++;
-    b1 = *pCoeffs++;
-    b2 = *pCoeffs++;
-    a1 = *pCoeffs++;
-    a2 = *pCoeffs++;
-
-    /* Reading the pState values */
-    Xn1 = pState[0];
-    Xn2 = pState[1];
-    Yn1 = pState[2];
-    Yn2 = pState[3];
-
-    /*      The variables acc holds the output value that is computed:        
-     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]        
-     */
-
-    sample = blockSize;
-
-    while(sample > 0u)
-    {
-      /* Read the input */
-      Xn = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-      acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = acc;
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:    */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc   */
-      Xn2 = Xn1;
-      Xn1 = Xn;
-      Yn2 = Yn1;
-      Yn1 = acc;
-
-      /* decrement the loop counter */
-      sample--;
-    }
-
-    /*  Store the updated state variables back into the pState array */
-    *pState++ = Xn1;
-    *pState++ = Xn2;
-    *pState++ = Yn1;
-    *pState++ = Yn2;
-
-    /*  The first stage goes from the input buffer to the output buffer. */
-    /*  Subsequent numStages  occur in-place in the output buffer */
-    pIn = pDst;
-
-    /* Reset the output pointer */
-    pOut = pDst;
-
-    /* decrement the loop counter */
-    stage--;
-
-  } while(stage > 0u);
-
-#endif /*   #ifndef ARM_MATH_CM0         */
-
-}
-
-
-  /**    
-   * @} end of BiquadCascadeDF1 group    
-   */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
deleted file mode 100644
index 3d9b5f64aa..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
+++ /dev/null
@@ -1,283 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_biquad_cascade_df1_fast_q15.c    
-*    
-* Description:	Fast processing function for the    
-*				Q15 Biquad cascade filter.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.9  2010/08/16     
-*    Initial version    
-*    
-*    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup BiquadCascadeDF1    
- * @{    
- */
-
-/**    
- * @details    
- * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.    
- * @param[in]  *pSrc points to the block of input data.    
- * @param[out] *pDst points to the block of output data.    
- * @param[in]  blockSize number of samples to process per call.    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * This fast version uses a 32-bit accumulator with 2.30 format.    
- * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
- * Thus, if the accumulator result overflows it wraps around and distorts the result.    
- * In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25).    
- * The 2.30 accumulator is then shifted by postShift bits and the result truncated to 1.15 format by discarding the low 16 bits.    
- *    
- * \par    
- * Refer to the function arm_biquad_cascade_df1_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.  Both the slow and the fast versions use the same instance structure.    
- * Use the function arm_biquad_cascade_df1_init_q15() to initialize the filter structure.    
- *    
- */
-
-void arm_biquad_cascade_df1_fast_q15(
-  const arm_biquad_casd_df1_inst_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pIn = pSrc;                             /*  Source pointer                               */
-  q15_t *pOut = pDst;                            /*  Destination pointer                          */
-  q31_t in;                                      /*  Temporary variable to hold input value       */
-  q31_t out;                                     /*  Temporary variable to hold output value      */
-  q31_t b0;                                      /*  Temporary variable to hold bo value          */
-  q31_t b1, a1;                                  /*  Filter coefficients                          */
-  q31_t state_in, state_out;                     /*  Filter state variables                       */
-  q31_t acc;                                     /*  Accumulator                                  */
-  int32_t shift = (int32_t) (15 - S->postShift); /*  Post shift                                   */
-  q15_t *pState = S->pState;                     /*  State pointer                                */
-  q15_t *pCoeffs = S->pCoeffs;                   /*  Coefficient pointer                          */
-  uint32_t sample, stage = S->numStages;         /*  Stage loop counter                           */
-
-
-
-  do
-  {
-
-    /* Read the b0 and 0 coefficients using SIMD  */
-    b0 = *__SIMD32(pCoeffs)++;
-
-    /* Read the b1 and b2 coefficients using SIMD */
-    b1 = *__SIMD32(pCoeffs)++;
-
-    /* Read the a1 and a2 coefficients using SIMD */
-    a1 = *__SIMD32(pCoeffs)++;
-
-    /* Read the input state values from the state buffer:  x[n-1], x[n-2] */
-    state_in = *__SIMD32(pState)++;
-
-    /* Read the output state values from the state buffer:  y[n-1], y[n-2] */
-    state_out = *__SIMD32(pState)--;
-
-    /* Apply loop unrolling and compute 2 output values simultaneously. */
-    /*      The variable acc hold output values that are being computed:       
-     *    
-     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]       
-     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]       
-     */
-    sample = blockSize >> 1u;
-
-    /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.    
-     ** a second loop below computes the remaining 1 sample. */
-    while(sample > 0u)
-    {
-
-      /* Read the input */
-      in = *__SIMD32(pIn)++;
-
-      /* out =  b0 * x[n] + 0 * 0 */
-      out = __SMUAD(b0, in);
-      /* acc =  b1 * x[n-1] + acc +=  b2 * x[n-2] + out */
-      acc = __SMLAD(b1, state_in, out);
-      /* acc +=  a1 * y[n-1] + acc +=  a2 * y[n-2] */
-      acc = __SMLAD(a1, state_out, acc);
-
-      /* The result is converted from 3.29 to 1.31 and then saturation is applied */
-      out = __SSAT((acc >> shift), 16);
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc   */
-      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
-      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      state_in = __PKHBT(in, state_in, 16);
-      state_out = __PKHBT(out, state_out, 16);
-
-#else
-
-      state_in = __PKHBT(state_in >> 16, (in >> 16), 16);
-      state_out = __PKHBT(state_out >> 16, (out), 16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-      /* out =  b0 * x[n] + 0 * 0 */
-      out = __SMUADX(b0, in);
-      /* acc0 =  b1 * x[n-1] , acc0 +=  b2 * x[n-2] + out */
-      acc = __SMLAD(b1, state_in, out);
-      /* acc +=  a1 * y[n-1] + acc +=  a2 * y[n-2] */
-      acc = __SMLAD(a1, state_out, acc);
-
-      /* The result is converted from 3.29 to 1.31 and then saturation is applied */
-      out = __SSAT((acc >> shift), 16);
-
-
-      /* Store the output in the destination buffer. */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      *__SIMD32(pOut)++ = __PKHBT(state_out, out, 16);
-
-#else
-
-      *__SIMD32(pOut)++ = __PKHBT(out, state_out >> 16, 16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc   */
-      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
-      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      state_in = __PKHBT(in >> 16, state_in, 16);
-      state_out = __PKHBT(out, state_out, 16);
-
-#else
-
-      state_in = __PKHBT(state_in >> 16, in, 16);
-      state_out = __PKHBT(state_out >> 16, out, 16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-
-      /* Decrement the loop counter */
-      sample--;
-
-    }
-
-    /* If the blockSize is not a multiple of 2, compute any remaining output samples here.    
-     ** No loop unrolling is used. */
-
-    if((blockSize & 0x1u) != 0u)
-    {
-      /* Read the input */
-      in = *pIn++;
-
-      /* out =  b0 * x[n] + 0 * 0 */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      out = __SMUAD(b0, in);
-
-#else
-
-      out = __SMUADX(b0, in);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-      /* acc =  b1 * x[n-1], acc +=  b2 * x[n-2] + out */
-      acc = __SMLAD(b1, state_in, out);
-      /* acc +=  a1 * y[n-1] + acc +=  a2 * y[n-2] */
-      acc = __SMLAD(a1, state_out, acc);
-
-      /* The result is converted from 3.29 to 1.31 and then saturation is applied */
-      out = __SSAT((acc >> shift), 16);
-
-      /* Store the output in the destination buffer. */
-      *pOut++ = (q15_t) out;
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc   */
-      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
-      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      state_in = __PKHBT(in, state_in, 16);
-      state_out = __PKHBT(out, state_out, 16);
-
-#else
-
-      state_in = __PKHBT(state_in >> 16, in, 16);
-      state_out = __PKHBT(state_out >> 16, out, 16);
-
-#endif /*   #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-    }
-
-    /*  The first stage goes from the input buffer to the output buffer.  */
-    /*  Subsequent (numStages - 1) occur in-place in the output buffer  */
-    pIn = pDst;
-
-    /* Reset the output pointer */
-    pOut = pDst;
-
-    /*  Store the updated state variables back into the state array */
-    *__SIMD32(pState)++ = state_in;
-    *__SIMD32(pState)++ = state_out;
-
-
-    /* Decrement the loop counter */
-    stage--;
-
-  } while(stage > 0u);
-}
-
-
-/**    
- * @} end of BiquadCascadeDF1 group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
deleted file mode 100644
index 62f02502c1..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
+++ /dev/null
@@ -1,275 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_biquad_cascade_df1_fast_q31.c    
-*    
-* Description:	Processing function for the    
-*				Q31 Fast Biquad cascade DirectFormI(DF1) filter.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.9  2010/08/27     
-*    Initial version    
-*    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup BiquadCascadeDF1    
- * @{    
- */
-
-/**    
- * @details    
- *    
- * @param[in]  *S        points to an instance of the Q31 Biquad cascade structure.    
- * @param[in]  *pSrc     points to the block of input data.    
- * @param[out] *pDst     points to the block of output data.    
- * @param[in]  blockSize number of samples to process per call.    
- * @return 	   none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * This function is optimized for speed at the expense of fixed-point precision and overflow protection.    
- * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.    
- * These intermediate results are added to a 2.30 accumulator.    
- * Finally, the accumulator is saturated and converted to a 1.31 result.    
- * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.    
- * In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). Use the intialization function    
- * arm_biquad_cascade_df1_init_q31() to initialize filter structure.    
- *    
- * \par    
- * Refer to the function arm_biquad_cascade_df1_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.  Both the slow and the fast versions use the same instance structure.    
- * Use the function arm_biquad_cascade_df1_init_q31() to initialize the filter structure.    
- */
-
-void arm_biquad_cascade_df1_fast_q31(
-  const arm_biquad_casd_df1_inst_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  q31_t acc;                                     /*  accumulator                   */
-  q31_t Xn1, Xn2, Yn1, Yn2;                      /*  Filter state variables        */
-  q31_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
-  q31_t *pIn = pSrc;                             /*  input pointer initialization  */
-  q31_t *pOut = pDst;                            /*  output pointer initialization */
-  q31_t *pState = S->pState;                     /*  pState pointer initialization */
-  q31_t *pCoeffs = S->pCoeffs;                   /*  coeff pointer initialization  */
-  q31_t Xn;                                      /*  temporary input               */
-  int32_t shift = (int32_t) S->postShift + 1;    /*  Shift to be applied to the output */
-  uint32_t sample, stage = S->numStages;         /*  loop counters                     */
-
-
-  do
-  {
-    /* Reading the coefficients */
-    b0 = *pCoeffs++;
-    b1 = *pCoeffs++;
-    b2 = *pCoeffs++;
-    a1 = *pCoeffs++;
-    a2 = *pCoeffs++;
-
-    /* Reading the state values */
-    Xn1 = pState[0];
-    Xn2 = pState[1];
-    Yn1 = pState[2];
-    Yn2 = pState[3];
-
-    /* Apply loop unrolling and compute 4 output values simultaneously. */
-    /*      The variables acc ... acc3 hold output values that are being computed:       
-     *       
-     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]       
-     */
-
-    sample = blockSize >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.       
-     ** a second loop below computes the remaining 1 to 3 samples. */
-    while(sample > 0u)
-    {
-      /* Read the input */
-      Xn = *pIn;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-      /* acc =  b0 * x[n] */
-      acc = (q31_t) (((q63_t) b1 * Xn1) >> 32);
-      /* acc +=  b1 * x[n-1] */
-      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b0 * (Xn))) >> 32);
-      /* acc +=  b[2] * x[n-2] */
-      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
-      /* acc +=  a1 * y[n-1] */
-      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
-      /* acc +=  a2 * y[n-2] */
-      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
-
-      /* The result is converted to 1.31 , Yn2 variable is reused */
-      Yn2 = acc << shift;
-
-      /* Read the second input */
-      Xn2 = *(pIn + 1u);
-
-      /* Store the output in the destination buffer. */
-      *pOut = Yn2;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-      /* acc =  b0 * x[n] */
-      acc = (q31_t) (((q63_t) b0 * (Xn2)) >> 32);
-      /* acc +=  b1 * x[n-1] */
-      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn))) >> 32);
-      /* acc +=  b[2] * x[n-2] */
-      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn1))) >> 32);
-      /* acc +=  a1 * y[n-1] */
-      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);
-      /* acc +=  a2 * y[n-2] */
-      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);
-
-      /* The result is converted to 1.31, Yn1 variable is reused  */
-      Yn1 = acc << shift;
-
-      /* Read the third input  */
-      Xn1 = *(pIn + 2u);
-
-      /* Store the output in the destination buffer. */
-      *(pOut + 1u) = Yn1;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-      /* acc =  b0 * x[n] */
-      acc = (q31_t) (((q63_t) b0 * (Xn1)) >> 32);
-      /* acc +=  b1 * x[n-1] */
-      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn2))) >> 32);
-      /* acc +=  b[2] * x[n-2] */
-      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn))) >> 32);
-      /* acc +=  a1 * y[n-1] */
-      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
-      /* acc +=  a2 * y[n-2] */
-      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
-
-      /* The result is converted to 1.31, Yn2 variable is reused  */
-      Yn2 = acc << shift;
-
-      /* Read the forth input */
-      Xn = *(pIn + 3u);
-
-      /* Store the output in the destination buffer. */
-      *(pOut + 2u) = Yn2;
-      pIn += 4u;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-      /* acc =  b0 * x[n] */
-      acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);
-      /* acc +=  b1 * x[n-1] */
-      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);
-      /* acc +=  b[2] * x[n-2] */
-      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
-      /* acc +=  a1 * y[n-1] */
-      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);
-      /* acc +=  a2 * y[n-2] */
-      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      Xn2 = Xn1;
-
-      /* The result is converted to 1.31, Yn1 variable is reused  */
-      Yn1 = acc << shift;
-
-      /* Xn1 = Xn     */
-      Xn1 = Xn;
-
-      /* Store the output in the destination buffer. */
-      *(pOut + 3u) = Yn1;
-      pOut += 4u;
-
-      /* decrement the loop counter */
-      sample--;
-    }
-
-    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.       
-     ** No loop unrolling is used. */
-    sample = (blockSize & 0x3u);
-
-    while(sample > 0u)
-    {
-      /* Read the input */
-      Xn = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-      /* acc =  b0 * x[n] */
-      acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);
-      /* acc +=  b1 * x[n-1] */
-      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);
-      /* acc +=  b[2] * x[n-2] */
-      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
-      /* acc +=  a1 * y[n-1] */
-      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
-      /* acc +=  a2 * y[n-2] */
-      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
-      /* The result is converted to 1.31  */
-      acc = acc << shift;
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc    */
-      Xn2 = Xn1;
-      Xn1 = Xn;
-      Yn2 = Yn1;
-      Yn1 = acc;
-
-      /* Store the output in the destination buffer. */
-      *pOut++ = acc;
-
-      /* decrement the loop counter */
-      sample--;
-    }
-
-    /*  The first stage goes from the input buffer to the output buffer. */
-    /*  Subsequent stages occur in-place in the output buffer */
-    pIn = pDst;
-
-    /* Reset to destination pointer */
-    pOut = pDst;
-
-    /*  Store the updated state variables back into the pState array */
-    *pState++ = Xn1;
-    *pState++ = Xn2;
-    *pState++ = Yn1;
-    *pState++ = Yn2;
-
-  } while(--stage);
-}
-
-/**    
-  * @} end of BiquadCascadeDF1 group    
-  */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
deleted file mode 100644
index b5032a55f1..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_biquad_cascade_df1_init_f32.c    
-*    
-* Description:  floating-point Biquad cascade DirectFormI(DF1) filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-* 	 incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup BiquadCascadeDF1    
- * @{    
- */
-
-/**    
- * @details    
- * @brief  Initialization function for the floating-point Biquad cascade filter.    
- * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.    
- * @param[in]     numStages    number of 2nd order stages in the filter.    
- * @param[in]     *pCoeffs     points to the filter coefficients array.    
- * @param[in]     *pState      points to the state array.    
- * @return        none    
- *    
- *    
- * Coefficient and State Ordering:    
- *    
- * \par    
- * The coefficients are stored in the array pCoeffs in the following order:    
- * 
    
- *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    
- * 
    
- *    
- * \par    
- * where b1x and a1x are the coefficients for the first stage,    
- * b2x and a2x are the coefficients for the second stage,    
- * and so on.  The pCoeffs array contains a total of 5*numStages values.    
- *    
- * \par    
- * The pState is a pointer to state array.    
- * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].    
- * The state variables are arranged in the pState array as:    
- * 
    
- *     {x[n-1], x[n-2], y[n-1], y[n-2]}    
- * 
    
- * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    
- * The state array has a total length of 4*numStages values.    
- * The state variables are updated after each block of data is processed; the coefficients are untouched.    
- *    
- */
-
-void arm_biquad_cascade_df1_init_f32(
-  arm_biquad_casd_df1_inst_f32 * S,
-  uint8_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState)
-{
-  /* Assign filter stages */
-  S->numStages = numStages;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and size is always 4 * numStages */
-  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(float32_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-}
-
-/**    
- * @} end of BiquadCascadeDF1 group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
deleted file mode 100644
index fa102f681b..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_biquad_cascade_df1_init_q15.c    
-*    
-* Description:  Q15 Biquad cascade DirectFormI(DF1) filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-* 	 incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup BiquadCascadeDF1    
- * @{    
- */
-
-/**    
- * @details    
- *    
- * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.    
- * @param[in]     numStages    number of 2nd order stages in the filter.    
- * @param[in]     *pCoeffs     points to the filter coefficients.    
- * @param[in]     *pState      points to the state buffer.    
- * @param[in]     postShift    Shift to be applied to the accumulator result. Varies according to the coefficients format    
- * @return        none    
- *    
- * Coefficient and State Ordering:    
- *    
- * \par    
- * The coefficients are stored in the array pCoeffs in the following order:    
- * 
    
- *     {b10, 0, b11, b12, a11, a12, b20, 0, b21, b22, a21, a22, ...}    
- * 
    
- * where b1x and a1x are the coefficients for the first stage,    
- * b2x and a2x are the coefficients for the second stage,    
- * and so on.  The pCoeffs array contains a total of 6*numStages values.    
- * The zero coefficient between b1 and b2 facilities  use of 16-bit SIMD instructions on the Cortex-M4.    
- *    
- * \par    
- * The state variables are stored in the array pState.    
- * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].    
- * The state variables are arranged in the pState array as:    
- * 
    
- *     {x[n-1], x[n-2], y[n-1], y[n-2]}    
- * 
    
- * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    
- * The state array has a total length of 4*numStages values.    
- * The state variables are updated after each block of data is processed; the coefficients are untouched.    
- */
-
-void arm_biquad_cascade_df1_init_q15(
-  arm_biquad_casd_df1_inst_q15 * S,
-  uint8_t numStages,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  int8_t postShift)
-{
-  /* Assign filter stages */
-  S->numStages = numStages;
-
-  /* Assign postShift to be applied to the output */
-  S->postShift = postShift;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and size is always 4 * numStages */
-  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q15_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-}
-
-/**    
- * @} end of BiquadCascadeDF1 group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
deleted file mode 100644
index 74eea26474..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_biquad_cascade_df1_init_q31.c    
-*    
-* Description:	Q31 Biquad cascade DirectFormI(DF1) filter initialization function.    
-*    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-* 	 incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup BiquadCascadeDF1    
- * @{    
- */
-
-/**    
- * @details    
- *    
- * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.    
- * @param[in]     numStages    number of 2nd order stages in the filter.    
- * @param[in]     *pCoeffs     points to the filter coefficients buffer.    
- * @param[in]     *pState      points to the state buffer.    
- * @param[in]     postShift    Shift to be applied after the accumulator.  Varies according to the coefficients format    
- * @return        none    
- *    
- * Coefficient and State Ordering:    
- *    
- * \par    
- * The coefficients are stored in the array pCoeffs in the following order:    
- * 
    
- *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    
- * 
    
- * where b1x and a1x are the coefficients for the first stage,    
- * b2x and a2x are the coefficients for the second stage,    
- * and so on.  The pCoeffs array contains a total of 5*numStages values.    
- *    
- * \par    
- * The pState points to state variables array.    
- * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].    
- * The state variables are arranged in the pState array as:    
- * 
    
- *     {x[n-1], x[n-2], y[n-1], y[n-2]}    
- * 
    
- * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.    
- * The state array has a total length of 4*numStages values.    
- * The state variables are updated after each block of data is processed; the coefficients are untouched.    
- */
-
-void arm_biquad_cascade_df1_init_q31(
-  arm_biquad_casd_df1_inst_q31 * S,
-  uint8_t numStages,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  int8_t postShift)
-{
-  /* Assign filter stages */
-  S->numStages = numStages;
-
-  /* Assign postShift to be applied to the output */
-  S->postShift = postShift;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and size is always 4 * numStages */
-  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q31_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-}
-
-/**    
- * @} end of BiquadCascadeDF1 group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c
deleted file mode 100644
index 3109c08602..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c
+++ /dev/null
@@ -1,408 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_biquad_cascade_df1_q15.c    
-*    
-* Description:	Processing function for the    
-*				Q15 Biquad cascade DirectFormI(DF1) filter.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-* 	 incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup BiquadCascadeDF1    
- * @{    
- */
-
-/**    
- * @brief Processing function for the Q15 Biquad cascade filter.    
- * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.    
- * @param[in]  *pSrc points to the block of input data.    
- * @param[out] *pDst points to the location where the output result is written.    
- * @param[in]  blockSize number of samples to process per call.    
- * @return none.    
- *    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using a 64-bit internal accumulator.    
- * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.    
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    
- * The accumulator is then shifted by postShift bits to truncate the result to 1.15 format by discarding the low 16 bits.    
- * Finally, the result is saturated to 1.15 format.    
- *    
- * \par    
- * Refer to the function arm_biquad_cascade_df1_fast_q15() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.    
- */
-
-void arm_biquad_cascade_df1_q15(
-  const arm_biquad_casd_df1_inst_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q15_t *pIn = pSrc;                             /*  Source pointer                               */
-  q15_t *pOut = pDst;                            /*  Destination pointer                          */
-  q31_t in;                                      /*  Temporary variable to hold input value       */
-  q31_t out;                                     /*  Temporary variable to hold output value      */
-  q31_t b0;                                      /*  Temporary variable to hold bo value          */
-  q31_t b1, a1;                                  /*  Filter coefficients                          */
-  q31_t state_in, state_out;                     /*  Filter state variables                       */
-  q31_t acc_l, acc_h;
-  q63_t acc;                                     /*  Accumulator                                  */
-  int32_t lShift = (15 - (int32_t) S->postShift);       /*  Post shift                                   */
-  q15_t *pState = S->pState;                     /*  State pointer                                */
-  q15_t *pCoeffs = S->pCoeffs;                   /*  Coefficient pointer                          */
-  uint32_t sample, stage = (uint32_t) S->numStages;     /*  Stage loop counter                           */
-  int32_t uShift = (32 - lShift);
-
-  do
-  {
-    /* Read the b0 and 0 coefficients using SIMD  */
-    b0 = *__SIMD32(pCoeffs)++;
-
-    /* Read the b1 and b2 coefficients using SIMD */
-    b1 = *__SIMD32(pCoeffs)++;
-
-    /* Read the a1 and a2 coefficients using SIMD */
-    a1 = *__SIMD32(pCoeffs)++;
-
-    /* Read the input state values from the state buffer:  x[n-1], x[n-2] */
-    state_in = *__SIMD32(pState)++;
-
-    /* Read the output state values from the state buffer:  y[n-1], y[n-2] */
-    state_out = *__SIMD32(pState)--;
-
-    /* Apply loop unrolling and compute 2 output values simultaneously. */
-    /*      The variable acc hold output values that are being computed:    
-     *    
-     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    
-     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    
-     */
-    sample = blockSize >> 1u;
-
-    /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.    
-     ** a second loop below computes the remaining 1 sample. */
-    while(sample > 0u)
-    {
-
-      /* Read the input */
-      in = *__SIMD32(pIn)++;
-
-      /* out =  b0 * x[n] + 0 * 0 */
-      out = __SMUAD(b0, in);
-
-      /* acc +=  b1 * x[n-1] +  b2 * x[n-2] + out */
-      acc = __SMLALD(b1, state_in, out);
-      /* acc +=  a1 * y[n-1] +  a2 * y[n-2] */
-      acc = __SMLALD(a1, state_out, acc);
-
-      /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
-      /* Calc lower part of acc */
-      acc_l = acc & 0xffffffff;
-
-      /* Calc upper part of acc */
-      acc_h = (acc >> 32) & 0xffffffff;
-
-      /* Apply shift for lower part of acc and upper part of acc */
-      out = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-      out = __SSAT(out, 16);
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc   */
-      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
-      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      state_in = __PKHBT(in, state_in, 16);
-      state_out = __PKHBT(out, state_out, 16);
-
-#else
-
-      state_in = __PKHBT(state_in >> 16, (in >> 16), 16);
-      state_out = __PKHBT(state_out >> 16, (out), 16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-      /* out =  b0 * x[n] + 0 * 0 */
-      out = __SMUADX(b0, in);
-      /* acc +=  b1 * x[n-1] +  b2 * x[n-2] + out */
-      acc = __SMLALD(b1, state_in, out);
-      /* acc +=  a1 * y[n-1] + a2 * y[n-2] */
-      acc = __SMLALD(a1, state_out, acc);
-
-      /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
-      /* Calc lower part of acc */
-      acc_l = acc & 0xffffffff;
-
-      /* Calc upper part of acc */
-      acc_h = (acc >> 32) & 0xffffffff;
-
-      /* Apply shift for lower part of acc and upper part of acc */
-      out = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-      out = __SSAT(out, 16);
-
-      /* Store the output in the destination buffer. */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      *__SIMD32(pOut)++ = __PKHBT(state_out, out, 16);
-
-#else
-
-      *__SIMD32(pOut)++ = __PKHBT(out, state_out >> 16, 16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc   */
-      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
-      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      state_in = __PKHBT(in >> 16, state_in, 16);
-      state_out = __PKHBT(out, state_out, 16);
-
-#else
-
-      state_in = __PKHBT(state_in >> 16, in, 16);
-      state_out = __PKHBT(state_out >> 16, out, 16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-
-      /* Decrement the loop counter */
-      sample--;
-
-    }
-
-    /* If the blockSize is not a multiple of 2, compute any remaining output samples here.    
-     ** No loop unrolling is used. */
-
-    if((blockSize & 0x1u) != 0u)
-    {
-      /* Read the input */
-      in = *pIn++;
-
-      /* out =  b0 * x[n] + 0 * 0 */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      out = __SMUAD(b0, in);
-
-#else
-
-      out = __SMUADX(b0, in);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-      /* acc =  b1 * x[n-1] + b2 * x[n-2] + out */
-      acc = __SMLALD(b1, state_in, out);
-      /* acc +=  a1 * y[n-1] + a2 * y[n-2] */
-      acc = __SMLALD(a1, state_out, acc);
-
-      /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
-      /* Calc lower part of acc */
-      acc_l = acc & 0xffffffff;
-
-      /* Calc upper part of acc */
-      acc_h = (acc >> 32) & 0xffffffff;
-
-      /* Apply shift for lower part of acc and upper part of acc */
-      out = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-      out = __SSAT(out, 16);
-
-      /* Store the output in the destination buffer. */
-      *pOut++ = (q15_t) out;
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc   */
-      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
-      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      state_in = __PKHBT(in, state_in, 16);
-      state_out = __PKHBT(out, state_out, 16);
-
-#else
-
-      state_in = __PKHBT(state_in >> 16, in, 16);
-      state_out = __PKHBT(state_out >> 16, out, 16);
-
-#endif /*   #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-    }
-
-    /*  The first stage goes from the input wire to the output wire.  */
-    /*  Subsequent numStages occur in-place in the output wire  */
-    pIn = pDst;
-
-    /* Reset the output pointer */
-    pOut = pDst;
-
-    /*  Store the updated state variables back into the state array */
-    *__SIMD32(pState)++ = state_in;
-    *__SIMD32(pState)++ = state_out;
-
-
-    /* Decrement the loop counter */
-    stage--;
-
-  } while(stage > 0u);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q15_t *pIn = pSrc;                             /*  Source pointer                               */
-  q15_t *pOut = pDst;                            /*  Destination pointer                          */
-  q15_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
-  q15_t Xn1, Xn2, Yn1, Yn2;                      /*  Filter state variables        */
-  q15_t Xn;                                      /*  temporary input               */
-  q63_t acc;                                     /*  Accumulator                                  */
-  int32_t shift = (15 - (int32_t) S->postShift); /*  Post shift                                   */
-  q15_t *pState = S->pState;                     /*  State pointer                                */
-  q15_t *pCoeffs = S->pCoeffs;                   /*  Coefficient pointer                          */
-  uint32_t sample, stage = (uint32_t) S->numStages;     /*  Stage loop counter                           */
-
-  do
-  {
-    /* Reading the coefficients */
-    b0 = *pCoeffs++;
-    b1 = *pCoeffs++;
-    b2 = *pCoeffs++;
-    a1 = *pCoeffs++;
-    a2 = *pCoeffs++;
-
-    /* Reading the state values */
-    Xn1 = pState[0];
-    Xn2 = pState[1];
-    Yn1 = pState[2];
-    Yn2 = pState[3];
-
-    /*      The variables acc holds the output value that is computed:         
-     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]         
-     */
-
-    sample = blockSize;
-
-    while(sample > 0u)
-    {
-      /* Read the input */
-      Xn = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-      /* acc =  b0 * x[n] */
-      acc = (q31_t) b0 *Xn;
-
-      /* acc +=  b1 * x[n-1] */
-      acc += (q31_t) b1 *Xn1;
-      /* acc +=  b[2] * x[n-2] */
-      acc += (q31_t) b2 *Xn2;
-      /* acc +=  a1 * y[n-1] */
-      acc += (q31_t) a1 *Yn1;
-      /* acc +=  a2 * y[n-2] */
-      acc += (q31_t) a2 *Yn2;
-
-      /* The result is converted to 1.31  */
-      acc = __SSAT((acc >> shift), 16);
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc    */
-      Xn2 = Xn1;
-      Xn1 = Xn;
-      Yn2 = Yn1;
-      Yn1 = (q15_t) acc;
-
-      /* Store the output in the destination buffer. */
-      *pOut++ = (q15_t) acc;
-
-      /* decrement the loop counter */
-      sample--;
-    }
-
-    /*  The first stage goes from the input buffer to the output buffer. */
-    /*  Subsequent stages occur in-place in the output buffer */
-    pIn = pDst;
-
-    /* Reset to destination pointer */
-    pOut = pDst;
-
-    /*  Store the updated state variables back into the pState array */
-    *pState++ = Xn1;
-    *pState++ = Xn2;
-    *pState++ = Yn1;
-    *pState++ = Yn2;
-
-  } while(--stage);
-
-#endif /*     #ifndef ARM_MATH_CM0 */
-
-}
-
-
-/**    
- * @} end of BiquadCascadeDF1 group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c
deleted file mode 100644
index 53a7a1047a..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c
+++ /dev/null
@@ -1,400 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_biquad_cascade_df1_q31.c    
-*    
-* Description:	Processing function for the    
-*				Q31 Biquad cascade filter    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-* 	 incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup BiquadCascadeDF1    
- * @{    
- */
-
-/**    
- * @brief Processing function for the Q31 Biquad cascade filter.    
- * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.    
- * @param[in]  *pSrc      points to the block of input data.    
- * @param[out] *pDst      points to the block of output data.    
- * @param[in]  blockSize  number of samples to process per call.    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using an internal 64-bit accumulator.    
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
- * Thus, if the accumulator result overflows it wraps around rather than clip.    
- * In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25).    
- * After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to    
- * 1.31 format by discarding the low 32 bits.    
- *    
- * \par    
- * Refer to the function arm_biquad_cascade_df1_fast_q31() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.    
- */
-
-void arm_biquad_cascade_df1_q31(
-  const arm_biquad_casd_df1_inst_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  q63_t acc;                                     /*  accumulator                   */
-  uint32_t uShift = ((uint32_t) S->postShift + 1u);
-  uint32_t lShift = 32u - uShift;                /*  Shift to be applied to the output */
-  q31_t *pIn = pSrc;                             /*  input pointer initialization  */
-  q31_t *pOut = pDst;                            /*  output pointer initialization */
-  q31_t *pState = S->pState;                     /*  pState pointer initialization */
-  q31_t *pCoeffs = S->pCoeffs;                   /*  coeff pointer initialization  */
-  q31_t Xn1, Xn2, Yn1, Yn2;                      /*  Filter state variables        */
-  q31_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
-  q31_t Xn;                                      /*  temporary input               */
-  uint32_t sample, stage = S->numStages;         /*  loop counters                     */
-
-
-#ifndef ARM_MATH_CM0
-
-  q31_t acc_l, acc_h;                            /*  temporary output variables    */
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  do
-  {
-    /* Reading the coefficients */
-    b0 = *pCoeffs++;
-    b1 = *pCoeffs++;
-    b2 = *pCoeffs++;
-    a1 = *pCoeffs++;
-    a2 = *pCoeffs++;
-
-    /* Reading the state values */
-    Xn1 = pState[0];
-    Xn2 = pState[1];
-    Yn1 = pState[2];
-    Yn2 = pState[3];
-
-    /* Apply loop unrolling and compute 4 output values simultaneously. */
-    /*      The variable acc hold output values that are being computed:    
-     *    
-     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]    
-     */
-
-    sample = blockSize >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-     ** a second loop below computes the remaining 1 to 3 samples. */
-    while(sample > 0u)
-    {
-      /* Read the input */
-      Xn = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-
-      /* acc =  b0 * x[n] */
-      acc = (q63_t) b0 *Xn;
-      /* acc +=  b1 * x[n-1] */
-      acc += (q63_t) b1 *Xn1;
-      /* acc +=  b[2] * x[n-2] */
-      acc += (q63_t) b2 *Xn2;
-      /* acc +=  a1 * y[n-1] */
-      acc += (q63_t) a1 *Yn1;
-      /* acc +=  a2 * y[n-2] */
-      acc += (q63_t) a2 *Yn2;
-
-      /* The result is converted to 1.31 , Yn2 variable is reused */
-
-      /* Calc lower part of acc */
-      acc_l = acc & 0xffffffff;
-
-      /* Calc upper part of acc */
-      acc_h = (acc >> 32) & 0xffffffff;
-
-      /* Apply shift for lower part of acc and upper part of acc */
-      Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-      /* Store the output in the destination buffer. */
-      *pOut++ = Yn2;
-
-      /* Read the second input */
-      Xn2 = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-
-      /* acc =  b0 * x[n] */
-      acc = (q63_t) b0 *Xn2;
-      /* acc +=  b1 * x[n-1] */
-      acc += (q63_t) b1 *Xn;
-      /* acc +=  b[2] * x[n-2] */
-      acc += (q63_t) b2 *Xn1;
-      /* acc +=  a1 * y[n-1] */
-      acc += (q63_t) a1 *Yn2;
-      /* acc +=  a2 * y[n-2] */
-      acc += (q63_t) a2 *Yn1;
-
-
-      /* The result is converted to 1.31, Yn1 variable is reused  */
-
-      /* Calc lower part of acc */
-      acc_l = acc & 0xffffffff;
-
-      /* Calc upper part of acc */
-      acc_h = (acc >> 32) & 0xffffffff;
-
-
-      /* Apply shift for lower part of acc and upper part of acc */
-      Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-      /* Store the output in the destination buffer. */
-      *pOut++ = Yn1;
-
-      /* Read the third input  */
-      Xn1 = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-
-      /* acc =  b0 * x[n] */
-      acc = (q63_t) b0 *Xn1;
-      /* acc +=  b1 * x[n-1] */
-      acc += (q63_t) b1 *Xn2;
-      /* acc +=  b[2] * x[n-2] */
-      acc += (q63_t) b2 *Xn;
-      /* acc +=  a1 * y[n-1] */
-      acc += (q63_t) a1 *Yn1;
-      /* acc +=  a2 * y[n-2] */
-      acc += (q63_t) a2 *Yn2;
-
-      /* The result is converted to 1.31, Yn2 variable is reused  */
-      /* Calc lower part of acc */
-      acc_l = acc & 0xffffffff;
-
-      /* Calc upper part of acc */
-      acc_h = (acc >> 32) & 0xffffffff;
-
-
-      /* Apply shift for lower part of acc and upper part of acc */
-      Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-      /* Store the output in the destination buffer. */
-      *pOut++ = Yn2;
-
-      /* Read the forth input */
-      Xn = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-
-      /* acc =  b0 * x[n] */
-      acc = (q63_t) b0 *Xn;
-      /* acc +=  b1 * x[n-1] */
-      acc += (q63_t) b1 *Xn1;
-      /* acc +=  b[2] * x[n-2] */
-      acc += (q63_t) b2 *Xn2;
-      /* acc +=  a1 * y[n-1] */
-      acc += (q63_t) a1 *Yn2;
-      /* acc +=  a2 * y[n-2] */
-      acc += (q63_t) a2 *Yn1;
-
-      /* The result is converted to 1.31, Yn1 variable is reused  */
-      /* Calc lower part of acc */
-      acc_l = acc & 0xffffffff;
-
-      /* Calc upper part of acc */
-      acc_h = (acc >> 32) & 0xffffffff;
-
-      /* Apply shift for lower part of acc and upper part of acc */
-      Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc    */
-      Xn2 = Xn1;
-      Xn1 = Xn;
-
-      /* Store the output in the destination buffer. */
-      *pOut++ = Yn1;
-
-      /* decrement the loop counter */
-      sample--;
-    }
-
-    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-     ** No loop unrolling is used. */
-    sample = (blockSize & 0x3u);
-
-    while(sample > 0u)
-    {
-      /* Read the input */
-      Xn = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-
-      /* acc =  b0 * x[n] */
-      acc = (q63_t) b0 *Xn;
-      /* acc +=  b1 * x[n-1] */
-      acc += (q63_t) b1 *Xn1;
-      /* acc +=  b[2] * x[n-2] */
-      acc += (q63_t) b2 *Xn2;
-      /* acc +=  a1 * y[n-1] */
-      acc += (q63_t) a1 *Yn1;
-      /* acc +=  a2 * y[n-2] */
-      acc += (q63_t) a2 *Yn2;
-
-      /* The result is converted to 1.31  */
-      acc = acc >> lShift;
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc    */
-      Xn2 = Xn1;
-      Xn1 = Xn;
-      Yn2 = Yn1;
-      Yn1 = (q31_t) acc;
-
-      /* Store the output in the destination buffer. */
-      *pOut++ = (q31_t) acc;
-
-      /* decrement the loop counter */
-      sample--;
-    }
-
-    /*  The first stage goes from the input buffer to the output buffer. */
-    /*  Subsequent stages occur in-place in the output buffer */
-    pIn = pDst;
-
-    /* Reset to destination pointer */
-    pOut = pDst;
-
-    /*  Store the updated state variables back into the pState array */
-    *pState++ = Xn1;
-    *pState++ = Xn2;
-    *pState++ = Yn1;
-    *pState++ = Yn2;
-
-  } while(--stage);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  do
-  {
-    /* Reading the coefficients */
-    b0 = *pCoeffs++;
-    b1 = *pCoeffs++;
-    b2 = *pCoeffs++;
-    a1 = *pCoeffs++;
-    a2 = *pCoeffs++;
-
-    /* Reading the state values */
-    Xn1 = pState[0];
-    Xn2 = pState[1];
-    Yn1 = pState[2];
-    Yn2 = pState[3];
-
-    /*      The variables acc holds the output value that is computed:         
-     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]         
-     */
-
-    sample = blockSize;
-
-    while(sample > 0u)
-    {
-      /* Read the input */
-      Xn = *pIn++;
-
-      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
-      /* acc =  b0 * x[n] */
-      acc = (q63_t) b0 *Xn;
-
-      /* acc +=  b1 * x[n-1] */
-      acc += (q63_t) b1 *Xn1;
-      /* acc +=  b[2] * x[n-2] */
-      acc += (q63_t) b2 *Xn2;
-      /* acc +=  a1 * y[n-1] */
-      acc += (q63_t) a1 *Yn1;
-      /* acc +=  a2 * y[n-2] */
-      acc += (q63_t) a2 *Yn2;
-
-      /* The result is converted to 1.31  */
-      acc = acc >> lShift;
-
-      /* Every time after the output is computed state should be updated. */
-      /* The states should be updated as:  */
-      /* Xn2 = Xn1    */
-      /* Xn1 = Xn     */
-      /* Yn2 = Yn1    */
-      /* Yn1 = acc    */
-      Xn2 = Xn1;
-      Xn1 = Xn;
-      Yn2 = Yn1;
-      Yn1 = (q31_t) acc;
-
-      /* Store the output in the destination buffer. */
-      *pOut++ = (q31_t) acc;
-
-      /* decrement the loop counter */
-      sample--;
-    }
-
-    /*  The first stage goes from the input buffer to the output buffer. */
-    /*  Subsequent stages occur in-place in the output buffer */
-    pIn = pDst;
-
-    /* Reset to destination pointer */
-    pOut = pDst;
-
-    /*  Store the updated state variables back into the pState array */
-    *pState++ = Xn1;
-    *pState++ = Xn2;
-    *pState++ = Yn1;
-    *pState++ = Yn2;
-
-  } while(--stage);
-
-#endif /*  #ifndef ARM_MATH_CM0 */
-}
-
-/**    
-  * @} end of BiquadCascadeDF1 group    
-  */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c
deleted file mode 100644
index 0b81422fff..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c
+++ /dev/null
@@ -1,377 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_biquad_cascade_df2T_f32.c    
-*    
-* Description:  Processing function for the floating-point transposed    
-*               direct form II Biquad cascade filter.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**       
- * @ingroup groupFilters       
- */
-
-/**       
- * @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure       
- *       
- * This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure.       
- * The filters are implemented as a cascade of second order Biquad sections.       
- * These functions provide a slight memory savings as compared to the direct form I Biquad filter functions.      
- * Only floating-point data is supported.       
- *       
- * This function operate on blocks of input and output data and each call to the function       
- * processes blockSize samples through the filter.       
- * pSrc points to the array of input data and       
- * pDst points to the array of output data.       
- * Both arrays contain blockSize values.       
- *       
- * \par Algorithm       
- * Each Biquad stage implements a second order filter using the difference equation:       
- * 
       
- *    y[n] = b0 * x[n] + d1       
- *    d1 = b1 * x[n] + a1 * y[n] + d2       
- *    d2 = b2 * x[n] + a2 * y[n]       
- * 
       
- * where d1 and d2 represent the two state values.       
- *       
- * \par       
- * A Biquad filter using a transposed Direct Form II structure is shown below.       
- * \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad"       
- * Coefficients b0, b1, and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients.       
- * Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.       
- * Pay careful attention to the sign of the feedback coefficients.       
- * Some design tools flip the sign of the feedback coefficients:       
- * 
       
- *    y[n] = b0 * x[n] + d1;       
- *    d1 = b1 * x[n] - a1 * y[n] + d2;       
- *    d2 = b2 * x[n] - a2 * y[n];       
- * 
       
- * In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.       
- *       
- * \par       
- * Higher order filters are realized as a cascade of second order sections.       
- * numStages refers to the number of second order stages used.       
- * For example, an 8th order filter would be realized with numStages=4 second order stages.       
- * A 9th order filter would be realized with numStages=5 second order stages with the       
- * coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).       
- *       
- * \par       
- * pState points to the state variable array.       
- * Each Biquad stage has 2 state variables d1 and d2.       
- * The state variables are arranged in the pState array as:       
- * 
       
- *     {d11, d12, d21, d22, ...}       
- * 
       
- * where d1x refers to the state variables for the first Biquad and       
- * d2x refers to the state variables for the second Biquad.       
- * The state array has a total length of 2*numStages values.       
- * The state variables are updated after each block of data is processed; the coefficients are untouched.       
- *       
- * \par       
- * The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II.    
- * The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types.    
- * That is why the Direct Form I structure supports Q15 and Q31 data types.    
- * The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables d1 and d2.    
- * Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad.    
- * The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.    
- *       
- * \par Instance Structure       
- * The coefficients and state variables for a filter are stored together in an instance data structure.       
- * A separate instance structure must be defined for each filter.       
- * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.       
- *       
- * \par Init Functions       
- * There is also an associated initialization function.      
- * The initialization function performs following operations:       
- * - Sets the values of the internal structure fields.       
- * - Zeros out the values in the state buffer.       
- *       
- * \par       
- * Use of the initialization function is optional.       
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.       
- * To place an instance structure into a const data section, the instance structure must be manually initialized.       
- * Set the values in the state buffer to zeros before static initialization.       
- * For example, to statically initialize the instance structure use       
- * 
       
- *     arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};       
- * 
       
- * where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer.       
- * pCoeffs is the address of the coefficient buffer;        
- *       
- */
-
-/**       
- * @addtogroup BiquadCascadeDF2T       
- * @{       
- */
-
-/**      
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.      
- * @param[in]  *S        points to an instance of the filter data structure.      
- * @param[in]  *pSrc     points to the block of input data.      
- * @param[out] *pDst     points to the block of output data      
- * @param[in]  blockSize number of samples to process.      
- * @return none.      
- */
-
-void arm_biquad_cascade_df2T_f32(
-  const arm_biquad_cascade_df2T_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize)
-{
-
-  float32_t *pIn = pSrc;                         /*  source pointer            */
-  float32_t *pOut = pDst;                        /*  destination pointer       */
-  float32_t *pState = S->pState;                 /*  State pointer             */
-  float32_t *pCoeffs = S->pCoeffs;               /*  coefficient pointer       */
-  float32_t acc0;                                /*  accumulator               */
-  float32_t b0, b1, b2, a1, a2;                  /*  Filter coefficients       */
-  float32_t Xn;                                  /*  temporary input           */
-  float32_t d1, d2;                              /*  state variables           */
-  uint32_t sample, stage = S->numStages;         /*  loop counters             */
-
-#ifndef ARM_MATH_CM0
-
-  float32_t Xn1, Xn2;                            /*  Input State variables     */
-  float32_t acc1;                                /*  accumulator               */
-
-
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  do
-  {
-    /* Reading the coefficients */
-    b0 = *pCoeffs++;
-    b1 = *pCoeffs++;
-    b2 = *pCoeffs++;
-    a1 = *pCoeffs++;
-    a2 = *pCoeffs++;
-
-    /*Reading the state values */
-    d1 = pState[0];
-    d2 = pState[1];
-
-    /* Apply loop unrolling and compute 4 output values simultaneously. */
-    sample = blockSize >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.       
-     ** a second loop below computes the remaining 1 to 3 samples. */
-    while(sample > 0u)
-    {
-
-      /* y[n] = b0 * x[n] + d1 */
-      /* d1 = b1 * x[n] + a1 * y[n] + d2 */
-      /* d2 = b2 * x[n] + a2 * y[n] */
-
-      /* Read the first input */
-      Xn1 = *pIn++;
-
-      /* y[n] = b0 * x[n] + d1 */
-      acc0 = (b0 * Xn1) + d1;
-
-      /* d1 = b1 * x[n] + d2 */
-      d1 = (b1 * Xn1) + d2;
-
-      /* d2 = b2 * x[n] */
-      d2 = (b2 * Xn1);
-
-      /* Read the second input */
-      Xn2 = *pIn++;
-
-      /* d1 = b1 * x[n] + a1 * y[n] */
-      d1 = (a1 * acc0) + d1;
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = acc0;
-
-      d2 = (a2 * acc0) + d2;
-
-      /* y[n] = b0 * x[n] + d1 */
-      acc1 = (b0 * Xn2) + d1;
-
-      /* Read the third input */
-      Xn1 = *pIn++;
-
-      d1 = (b1 * Xn2) + d2;
-
-      d2 = (b2 * Xn2);
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = acc1;
-
-      d1 = (a1 * acc1) + d1;
-
-      d2 = (a2 * acc1) + d2;
-
-      /* y[n] = b0 * x[n] + d1 */
-      acc0 = (b0 * Xn1) + d1;
-
-      d1 = (b1 * Xn1) + d2;
-
-      d2 = (b2 * Xn1);
-
-      /* Read the fourth input */
-      Xn2 = *pIn++;
-
-      d1 = (a1 * acc0) + d1;
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = acc0;
-
-      d2 = (a2 * acc0) + d2;
-
-      /* y[n] = b0 * x[n] + d1 */
-      acc1 = (b0 * Xn2) + d1;
-
-      d1 = (b1 * Xn2) + d2;
-
-      d2 = (b2 * Xn2);
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = acc1;
-
-      d1 = (a1 * acc1) + d1;
-
-      d2 = (a2 * acc1) + d2;
-
-      /* decrement the loop counter */
-      sample--;
-
-    }
-
-    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.       
-     ** No loop unrolling is used. */
-    sample = blockSize & 0x3u;
-
-    while(sample > 0u)
-    {
-      /* Read the input */
-      Xn = *pIn++;
-
-      /* y[n] = b0 * x[n] + d1 */
-      acc0 = (b0 * Xn) + d1;
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = acc0;
-
-      /* Every time after the output is computed state should be updated. */
-      /* d1 = b1 * x[n] + a1 * y[n] + d2 */
-      d1 = ((b1 * Xn) + (a1 * acc0)) + d2;
-
-      /* d2 = b2 * x[n] + a2 * y[n] */
-      d2 = (b2 * Xn) + (a2 * acc0);
-
-      /* decrement the loop counter */
-      sample--;
-    }
-
-    /* Store the updated state variables back into the state array */
-    *pState++ = d1;
-    *pState++ = d2;
-
-    /* The current stage input is given as the output to the next stage */
-    pIn = pDst;
-
-    /*Reset the output working pointer */
-    pOut = pDst;
-
-    /* decrement the loop counter */
-    stage--;
-
-  } while(stage > 0u);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  do
-  {
-    /* Reading the coefficients */
-    b0 = *pCoeffs++;
-    b1 = *pCoeffs++;
-    b2 = *pCoeffs++;
-    a1 = *pCoeffs++;
-    a2 = *pCoeffs++;
-
-    /*Reading the state values */
-    d1 = pState[0];
-    d2 = pState[1];
-
-
-    sample = blockSize;
-
-    while(sample > 0u)
-    {
-      /* Read the input */
-      Xn = *pIn++;
-
-      /* y[n] = b0 * x[n] + d1 */
-      acc0 = (b0 * Xn) + d1;
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = acc0;
-
-      /* Every time after the output is computed state should be updated. */
-      /* d1 = b1 * x[n] + a1 * y[n] + d2 */
-      d1 = ((b1 * Xn) + (a1 * acc0)) + d2;
-
-      /* d2 = b2 * x[n] + a2 * y[n] */
-      d2 = (b2 * Xn) + (a2 * acc0);
-
-      /* decrement the loop counter */
-      sample--;
-    }
-
-    /* Store the updated state variables back into the state array */
-    *pState++ = d1;
-    *pState++ = d2;
-
-    /* The current stage input is given as the output to the next stage */
-    pIn = pDst;
-
-    /*Reset the output working pointer */
-    pOut = pDst;
-
-    /* decrement the loop counter */
-    stage--;
-
-  } while(stage > 0u);
-
-#endif /*  #ifndef ARM_MATH_CM0         */
-
-}
-
-
-  /**       
-   * @} end of BiquadCascadeDF2T group       
-   */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
deleted file mode 100644
index 3f0afd706b..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_biquad_cascade_df2T_init_f32.c    
-*    
-* Description:  Initialization function for the floating-point transposed   
-*               direct form II Biquad cascade filter.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup BiquadCascadeDF2T    
- * @{    
- */
-
-/**   
- * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.   
- * @param[in,out] *S           points to an instance of the filter data structure.   
- * @param[in]     numStages    number of 2nd order stages in the filter.   
- * @param[in]     *pCoeffs     points to the filter coefficients.   
- * @param[in]     *pState      points to the state buffer.   
- * @return        none   
- *    
- * Coefficient and State Ordering:    
- * \par    
- * The coefficients are stored in the array pCoeffs in the following order:    
- * 
    
- *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}    
- * 
    
- *    
- * \par    
- * where b1x and a1x are the coefficients for the first stage,    
- * b2x and a2x are the coefficients for the second stage,    
- * and so on.  The pCoeffs array contains a total of 5*numStages values.    
- *    
- * \par    
- * The pState is a pointer to state array.    
- * Each Biquad stage has 2 state variables d1, and d2.    
- * The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on.    
- * The state array has a total length of 2*numStages values.    
- * The state variables are updated after each block of data is processed; the coefficients are untouched.    
- */
-
-void arm_biquad_cascade_df2T_init_f32(
-  arm_biquad_cascade_df2T_instance_f32 * S,
-  uint8_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState)
-{
-  /* Assign filter stages */
-  S->numStages = numStages;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and size is always 2 * numStages */
-  memset(pState, 0, (2u * (uint32_t) numStages) * sizeof(float32_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-}
-
-/**    
- * @} end of BiquadCascadeDF2T group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_f32.c
deleted file mode 100644
index 9b036c85c9..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_f32.c
+++ /dev/null
@@ -1,646 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_conv_f32.c    
-*    
-* Description:	Convolution of floating-point sequences.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*  
-* Version 1.0.11 2011/10/18  
-*    Bug Fix in conv, correlation, partial convolution.  
-* 
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-*    
-* -------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @defgroup Conv Convolution    
- *    
- * Convolution is a mathematical operation that operates on two finite length vectors to generate a finite length output vector.    
- * Convolution is similar to correlation and is frequently used in filtering and data analysis.    
- * The CMSIS DSP library contains functions for convolving Q7, Q15, Q31, and floating-point data types.    
- * The library also provides fast versions of the Q15 and Q31 functions on Cortex-M4 and Cortex-M3.    
- *    
- * \par Algorithm    
- * Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively.    
- * Then the convolution    
- *    
- * 
    
- *                   c[n] = a[n] * b[n]    
- * 
    
- *    
- * \par    
- * is defined as    
- * \image html ConvolutionEquation.gif    
- * \par    
- * Note that c[n] is of length srcALen + srcBLen - 1 and is defined over the interval n=0, 1, 2, ..., srcALen + srcBLen - 2.    
- * pSrcA points to the first input vector of length srcALen and    
- * pSrcB points to the second input vector of length srcBLen.    
- * The output result is written to pDst and the calling function must allocate srcALen+srcBLen-1 words for the result.    
- *    
- * \par    
- * Conceptually, when two signals a[n] and b[n] are convolved,    
- * the signal b[n] slides over a[n].    
- * For each offset \c n, the overlapping portions of a[n] and b[n] are multiplied and summed together.    
- *    
- * \par    
- * Note that convolution is a commutative operation:    
- *    
- * 
    
- *                   a[n] * b[n] = b[n] * a[n].    
- * 
    
- *    
- * \par    
- * This means that switching the A and B arguments to the convolution functions has no effect.    
- *    
- * Fixed-Point Behavior    
- *    
- * \par    
- * Convolution requires summing up a large number of intermediate products.    
- * As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation.    
- * Refer to the function specific documentation below for further details of the particular algorithm used.    
- *
- *
- * Fast Versions
- *
- * \par 
- * Fast versions are supported for Q31 and Q15.  Cycles for Fast versions are less compared to Q31 and Q15 of conv and the design requires
- * the input signals should be scaled down to avoid intermediate overflows.   
- *
- *
- * Opt Versions
- *
- * \par 
- * Opt versions are supported for Q15 and Q7.  Design uses internal scratch buffer for getting good optimisation.
- * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions 
- */
-
-/**    
- * @addtogroup Conv    
- * @{    
- */
-
-/**    
- * @brief Convolution of floating-point sequences.    
- * @param[in] *pSrcA points to the first input sequence.    
- * @param[in] srcALen length of the first input sequence.    
- * @param[in] *pSrcB points to the second input sequence.    
- * @param[in] srcBLen length of the second input sequence.    
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.    
- * @return none.    
- */
-
-void arm_conv_f32(
-  float32_t * pSrcA,
-  uint32_t srcALen,
-  float32_t * pSrcB,
-  uint32_t srcBLen,
-  float32_t * pDst)
-{
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  float32_t *pIn1;                               /* inputA pointer */
-  float32_t *pIn2;                               /* inputB pointer */
-  float32_t *pOut = pDst;                        /* output pointer */
-  float32_t *px;                                 /* Intermediate inputA pointer */
-  float32_t *py;                                 /* Intermediate inputB pointer */
-  float32_t *pSrc1, *pSrc2;                      /* Intermediate pointers */
-  float32_t sum, acc0, acc1, acc2, acc3;         /* Accumulator */
-  float32_t x0, x1, x2, x3, c0;                  /* Temporary variables to hold state and coefficient values */
-  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counters */
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcA;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcB;
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcB;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcA;
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-  }
-
-  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
-  /* The function is internally    
-   * divided into three stages according to the number of multiplications that has to be    
-   * taken place between inputA samples and inputB samples. In the first stage of the    
-   * algorithm, the multiplications increase by one for every iteration.    
-   * In the second stage of the algorithm, srcBLen number of multiplications are done.    
-   * In the third stage of the algorithm, the multiplications decrease by one    
-   * for every iteration. */
-
-  /* The algorithm is implemented in three stages.    
-     The loop counters of each stage is initiated here. */
-  blockSize1 = srcBLen - 1u;
-  blockSize2 = srcALen - (srcBLen - 1u);
-  blockSize3 = blockSize1;
-
-  /* --------------------------    
-   * initializations of stage1    
-   * -------------------------*/
-
-  /* sum = x[0] * y[0]    
-   * sum = x[0] * y[1] + x[1] * y[0]    
-   * ....    
-   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]    
-   */
-
-  /* In this stage the MAC operations are increased by 1 for every iteration.    
-     The count variable holds the number of MAC operations performed */
-  count = 1u;
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-
-  /* ------------------------    
-   * Stage1 process    
-   * ----------------------*/
-
-  /* The first stage starts here */
-  while(blockSize1 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0.0f;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* x[0] * y[srcBLen - 1] */
-      sum += *px++ * *py--;
-
-      /* x[1] * y[srcBLen - 2] */
-      sum += *px++ * *py--;
-
-      /* x[2] * y[srcBLen - 3] */
-      sum += *px++ * *py--;
-
-      /* x[3] * y[srcBLen - 4] */
-      sum += *px++ * *py--;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.    
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      sum += *px++ * *py--;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = sum;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pIn2 + count;
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* --------------------------    
-   * Initializations of stage2    
-   * ------------------------*/
-
-  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]    
-   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]    
-   * ....    
-   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]    
-   */
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  pSrc2 = pIn2 + (srcBLen - 1u);
-  py = pSrc2;
-
-  /* count is index by which the pointer pIn1 to be incremented */
-  count = 0u;
-
-  /* -------------------    
-   * Stage2 process    
-   * ------------------*/
-
-  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
-   * So, to loop unroll over blockSize2,    
-   * srcBLen should be greater than or equal to 4 */
-  if(srcBLen >= 4u)
-  {
-    /* Loop unroll over blockSize2, by 4 */
-    blkCnt = blockSize2 >> 2u;
-
-    while(blkCnt > 0u)
-    {
-      /* Set all accumulators to zero */
-      acc0 = 0.0f;
-      acc1 = 0.0f;
-      acc2 = 0.0f;
-      acc3 = 0.0f;
-
-      /* read x[0], x[1], x[2] samples */
-      x0 = *(px++);
-      x1 = *(px++);
-      x2 = *(px++);
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      do
-      {
-        /* Read y[srcBLen - 1] sample */
-        c0 = *(py--);
-
-        /* Read x[3] sample */
-        x3 = *(px);
-
-        /* Perform the multiply-accumulate */
-        /* acc0 +=  x[0] * y[srcBLen - 1] */
-        acc0 += x0 * c0;
-
-        /* acc1 +=  x[1] * y[srcBLen - 1] */
-        acc1 += x1 * c0;
-
-        /* acc2 +=  x[2] * y[srcBLen - 1] */
-        acc2 += x2 * c0;
-
-        /* acc3 +=  x[3] * y[srcBLen - 1] */
-        acc3 += x3 * c0;
-
-        /* Read y[srcBLen - 2] sample */
-        c0 = *(py--);
-
-        /* Read x[4] sample */
-        x0 = *(px + 1u);
-
-        /* Perform the multiply-accumulate */
-        /* acc0 +=  x[1] * y[srcBLen - 2] */
-        acc0 += x1 * c0;
-        /* acc1 +=  x[2] * y[srcBLen - 2] */
-        acc1 += x2 * c0;
-        /* acc2 +=  x[3] * y[srcBLen - 2] */
-        acc2 += x3 * c0;
-        /* acc3 +=  x[4] * y[srcBLen - 2] */
-        acc3 += x0 * c0;
-
-        /* Read y[srcBLen - 3] sample */
-        c0 = *(py--);
-
-        /* Read x[5] sample */
-        x1 = *(px + 2u);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[2] * y[srcBLen - 3] */
-        acc0 += x2 * c0;
-        /* acc1 +=  x[3] * y[srcBLen - 2] */
-        acc1 += x3 * c0;
-        /* acc2 +=  x[4] * y[srcBLen - 2] */
-        acc2 += x0 * c0;
-        /* acc3 +=  x[5] * y[srcBLen - 2] */
-        acc3 += x1 * c0;
-
-        /* Read y[srcBLen - 4] sample */
-        c0 = *(py--);
-
-        /* Read x[6] sample */
-        x2 = *(px + 3u);
-        px += 4u;
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[3] * y[srcBLen - 4] */
-        acc0 += x3 * c0;
-        /* acc1 +=  x[4] * y[srcBLen - 4] */
-        acc1 += x0 * c0;
-        /* acc2 +=  x[5] * y[srcBLen - 4] */
-        acc2 += x1 * c0;
-        /* acc3 +=  x[6] * y[srcBLen - 4] */
-        acc3 += x2 * c0;
-
-
-      } while(--k);
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Read y[srcBLen - 5] sample */
-        c0 = *(py--);
-
-        /* Read x[7] sample */
-        x3 = *(px++);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[4] * y[srcBLen - 5] */
-        acc0 += x0 * c0;
-        /* acc1 +=  x[5] * y[srcBLen - 5] */
-        acc1 += x1 * c0;
-        /* acc2 +=  x[6] * y[srcBLen - 5] */
-        acc2 += x2 * c0;
-        /* acc3 +=  x[7] * y[srcBLen - 5] */
-        acc3 += x3 * c0;
-
-        /* Reuse the present samples for the next MAC */
-        x0 = x1;
-        x1 = x2;
-        x2 = x3;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = acc0;
-      *pOut++ = acc1;
-      *pOut++ = acc2;
-      *pOut++ = acc3;
-
-      /* Increment the pointer pIn1 index, count by 4 */
-      count += 4u;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-
-    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.    
-     ** No loop unrolling is used. */
-    blkCnt = blockSize2 % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0.0f;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += *px++ * *py--;
-        sum += *px++ * *py--;
-        sum += *px++ * *py--;
-        sum += *px++ * *py--;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += *px++ * *py--;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = sum;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-  else
-  {
-    /* If the srcBLen is not a multiple of 4,    
-     * the blockSize2 loop cannot be unrolled by 4 */
-    blkCnt = blockSize2;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0.0f;
-
-      /* srcBLen number of MACS should be performed */
-      k = srcBLen;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += *px++ * *py--;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = sum;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-
-
-  /* --------------------------    
-   * Initializations of stage3    
-   * -------------------------*/
-
-  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]    
-   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]    
-   * ....    
-   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]    
-   * sum +=  x[srcALen-1] * y[srcBLen-1]    
-   */
-
-  /* In this stage the MAC operations are decreased by 1 for every iteration.    
-     The blockSize3 variable holds the number of MAC operations performed */
-
-  /* Working pointer of inputA */
-  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-  px = pSrc1;
-
-  /* Working pointer of inputB */
-  pSrc2 = pIn2 + (srcBLen - 1u);
-  py = pSrc2;
-
-  /* -------------------    
-   * Stage3 process    
-   * ------------------*/
-
-  while(blockSize3 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0.0f;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = blockSize3 >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
-      sum += *px++ * *py--;
-
-      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
-      sum += *px++ * *py--;
-
-      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
-      sum += *px++ * *py--;
-
-      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
-      sum += *px++ * *py--;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.    
-     ** No loop unrolling is used. */
-    k = blockSize3 % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* sum +=  x[srcALen-1] * y[srcBLen-1] */
-      sum += *px++ * *py--;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = sum;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pSrc2;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
-  float32_t *pIn2 = pSrcB;                       /* inputB pointer */
-  float32_t sum;                                 /* Accumulator */
-  uint32_t i, j;                                 /* loop counters */
-
-  /* Loop to calculate convolution for output length number of times */
-  for (i = 0u; i < ((srcALen + srcBLen) - 1u); i++)
-  {
-    /* Initialize sum with zero to carry out MAC operations */
-    sum = 0.0f;
-
-    /* Loop to perform MAC operations according to convolution equation */
-    for (j = 0u; j <= i; j++)
-    {
-      /* Check the array limitations */
-      if((((i - j) < srcBLen) && (j < srcALen)))
-      {
-        /* z[i] += x[i-j] * y[j] */
-        sum += pIn1[j] * pIn2[i - j];
-      }
-    }
-    /* Store the output in the destination buffer */
-    pDst[i] = sum;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0        */
-
-}
-
-/**    
- * @} end of Conv group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_opt_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_opt_q15.c
deleted file mode 100644
index a8097419d3..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_opt_q15.c
+++ /dev/null
@@ -1,538 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_conv_fast_opt_q15.c    
-*    
-* Description:	Fast Q15 Convolution.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*  
-* Version 1.0.11 2011/10/18  
-*    Bug Fix in conv, correlation, partial convolution.  
-* 
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup Conv    
- * @{    
- */
-
-/**    
- * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.    
- * @param[in] *pSrcA points to the first input sequence.    
- * @param[in] srcALen length of the first input sequence.    
- * @param[in] *pSrcB points to the second input sequence.    
- * @param[in] srcBLen length of the second input sequence.    
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.    
- * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
- * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).   
- * @return none.    
- *    
- * \par Restrictions    
- *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
- *	In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit    
- *     
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * This fast version uses a 32-bit accumulator with 2.30 format.    
- * The accumulator maintains full precision of the intermediate multiplication results    
- * but provides only a single guard bit. There is no saturation on intermediate additions.    
- * Thus, if the accumulator overflows it wraps around and distorts the result.    
- * The input signals should be scaled down to avoid intermediate overflows.    
- * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,    
- * as maximum of min(srcALen, srcBLen) number of additions are carried internally.    
- * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.    
- *    
- * \par    
- * See arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.    
- */
-
-void arm_conv_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2)
-{
-  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators */
-  q31_t x1, x2, x3;                              /* Temporary variables to hold state and coefficient values */
-  q31_t y1, y2;                                  /* State variables */
-  q15_t *pOut = pDst;                            /* output pointer */
-  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */
-  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */
-  q15_t *pIn1;                                   /* inputA pointer */
-  q15_t *pIn2;                                   /* inputB pointer */
-  q15_t *px;                                     /* Intermediate inputA pointer  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  uint32_t j, k, blkCnt;                         /* loop counter */
-  uint32_t tapCnt;                               /* loop count */
-#ifdef UNALIGNED_SUPPORT_DISABLE
-
-  q15_t a, b;
-
-#endif	/*	#ifdef UNALIGNED_SUPPORT_DISABLE	*/
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcA;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcB;
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcB;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcA;
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-  }
-
-  /* Pointer to take end of scratch2 buffer */
-  pScr2 = pScratch2 + srcBLen - 1;
-
-  /* points to smaller length sequence */
-  px = pIn2;
-
-  /* Apply loop unrolling and do 4 Copies simultaneously. */
-  k = srcBLen >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-
-  /* Copy smaller length input sequence in reverse order into second scratch buffer */
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    *pScr2-- = *px++;
-    *pScr2-- = *px++;
-    *pScr2-- = *px++;
-    *pScr2-- = *px++;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  k = srcBLen % 0x4u;
-
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    *pScr2-- = *px++;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* Initialze temporary scratch pointer */
-  pScr1 = pScratch1;
-
-  /* Assuming scratch1 buffer is aligned by 32-bit */
-  /* Fill (srcBLen - 1u) zeros in scratch1 buffer */
-  arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-  /* Update temporary scratch pointer */
-  pScr1 += (srcBLen - 1u);
-
-  /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-  /* Copy (srcALen) samples in scratch buffer */
-  arm_copy_q15(pIn1, pScr1, srcALen);
-
-  /* Update pointers */
-  pScr1 += srcALen;
-
-#else
-
-  /* Apply loop unrolling and do 4 Copies simultaneously. */
-  k = srcALen >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    *pScr1++ = *pIn1++;
-    *pScr1++ = *pIn1++;
-    *pScr1++ = *pIn1++;
-    *pScr1++ = *pIn1++;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  k = srcALen % 0x4u;
-
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    *pScr1++ = *pIn1++;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-  /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
-  arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-  /* Update pointer */
-  pScr1 += (srcBLen - 1u);
-
-#else
-
-  /* Apply loop unrolling and do 4 Copies simultaneously. */
-  k = (srcBLen - 1u) >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    *pScr1++ = 0;
-    *pScr1++ = 0;
-    *pScr1++ = 0;
-    *pScr1++ = 0;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  k = (srcBLen - 1u) % 0x4u;
-
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    *pScr1++ = 0;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-  /* Temporary pointer for scratch2 */
-  py = pScratch2;
-
-
-  /* Initialization of pIn2 pointer */
-  pIn2 = py;
-
-  /* First part of the processing with loop unrolling process 4 data points at a time.       
-   ** a second loop below process for the remaining 1 to 3 samples. */
-
-  /* Actual convolution process starts here */
-  blkCnt = (srcALen + srcBLen - 1u) >> 2;
-
-  while(blkCnt > 0)
-  {
-    /* Initialze temporary scratch pointer as scratch1 */
-    pScr1 = pScratch1;
-
-    /* Clear Accumlators */
-    acc0 = 0;
-    acc1 = 0;
-    acc2 = 0;
-    acc3 = 0;
-
-    /* Read two samples from scratch1 buffer */
-    x1 = *__SIMD32(pScr1)++;
-
-    /* Read next two samples from scratch1 buffer */
-    x2 = *__SIMD32(pScr1)++;
-
-    tapCnt = (srcBLen) >> 2u;
-
-    while(tapCnt > 0u)
-    {
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-      /* Read four samples from smaller buffer */
-      y1 = _SIMD32_OFFSET(pIn2);
-      y2 = _SIMD32_OFFSET(pIn2 + 2u);
-
-      /* multiply and accumlate */
-      acc0 = __SMLAD(x1, y1, acc0);
-      acc2 = __SMLAD(x2, y1, acc2);
-
-      /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      /* multiply and accumlate */
-      acc1 = __SMLADX(x3, y1, acc1);
-
-      /* Read next two samples from scratch1 buffer */
-      x1 = _SIMD32_OFFSET(pScr1);
-
-      /* multiply and accumlate */
-      acc0 = __SMLAD(x2, y2, acc0);
-      acc2 = __SMLAD(x1, y2, acc2);
-
-      /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x1, x2, 0);
-#else
-      x3 = __PKHBT(x2, x1, 0);
-#endif
-
-      acc3 = __SMLADX(x3, y1, acc3);
-      acc1 = __SMLADX(x3, y2, acc1);
-
-      x2 = _SIMD32_OFFSET(pScr1 + 2u);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc3 = __SMLADX(x3, y2, acc3);
-
-#else	 
-
-      /* Read four samples from smaller buffer */
-	  a = *pIn2;
-	  b = *(pIn2 + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      y1 = __PKHBT(a, b, 16);
-#else
-      y1 = __PKHBT(b, a, 16);
-#endif
-	  
-	  a = *(pIn2 + 2);
-	  b = *(pIn2 + 3);
-#ifndef ARM_MATH_BIG_ENDIAN
-      y2 = __PKHBT(a, b, 16);
-#else
-      y2 = __PKHBT(b, a, 16);
-#endif				
-
-      acc0 = __SMLAD(x1, y1, acc0);
-
-      acc2 = __SMLAD(x2, y1, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc1 = __SMLADX(x3, y1, acc1);
-
-	  a = *pScr1;
-	  b = *(pScr1 + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x1 = __PKHBT(a, b, 16);
-#else
-      x1 = __PKHBT(b, a, 16);
-#endif
-
-      acc0 = __SMLAD(x2, y2, acc0);
-
-      acc2 = __SMLAD(x1, y2, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x1, x2, 0);
-#else
-      x3 = __PKHBT(x2, x1, 0);
-#endif
-
-      acc3 = __SMLADX(x3, y1, acc3);
-
-      acc1 = __SMLADX(x3, y2, acc1);
-
-	  a = *(pScr1 + 2);
-	  b = *(pScr1 + 3);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x2 = __PKHBT(a, b, 16);
-#else
-      x2 = __PKHBT(b, a, 16);
-#endif
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc3 = __SMLADX(x3, y2, acc3);
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-      /* update scratch pointers */
-      pIn2 += 4u;
-      pScr1 += 4u;
-
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Update scratch pointer for remaining samples of smaller length sequence */
-    pScr1 -= 4u;
-
-    /* apply same above for remaining samples of smaller length sequence */
-    tapCnt = (srcBLen) & 3u;
-
-    while(tapCnt > 0u)
-    {
-
-      /* accumlate the results */
-      acc0 += (*pScr1++ * *pIn2);
-      acc1 += (*pScr1++ * *pIn2);
-      acc2 += (*pScr1++ * *pIn2);
-      acc3 += (*pScr1++ * *pIn2++);
-
-      pScr1 -= 3u;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    blkCnt--;
-
-
-    /* Store the results in the accumulators in the destination buffer. */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    *__SIMD32(pOut)++ =
-      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
-
-    *__SIMD32(pOut)++ =
-      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
-
-
-#else
-
-    *__SIMD32(pOut)++ =
-      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
-
-    *__SIMD32(pOut)++ =
-      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
-
-
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */
-
-    /* Initialization of inputB pointer */
-    pIn2 = py;
-
-    pScratch1 += 4u;
-
-  }
-
-
-  blkCnt = (srcALen + srcBLen - 1u) & 0x3;
-
-  /* Calculate convolution for remaining samples of Bigger length sequence */
-  while(blkCnt > 0)
-  {
-    /* Initialze temporary scratch pointer as scratch1 */
-    pScr1 = pScratch1;
-
-    /* Clear Accumlators */
-    acc0 = 0;
-
-    tapCnt = (srcBLen) >> 1u;
-
-    while(tapCnt > 0u)
-    {
-
-      acc0 += (*pScr1++ * *pIn2++);
-      acc0 += (*pScr1++ * *pIn2++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    tapCnt = (srcBLen) & 1u;
-
-    /* apply same above for remaining samples of smaller length sequence */
-    while(tapCnt > 0u)
-    {
-
-      /* accumlate the results */
-      acc0 += (*pScr1++ * *pIn2++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    blkCnt--;
-
-    /* The result is in 2.30 format.  Convert to 1.15 with saturation.       
-     ** Then store the output in the destination buffer. */
-    *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-
-    /* Initialization of inputB pointer */
-    pIn2 = py;
-
-    pScratch1 += 1u;
-
-  }
-
-}
-
-/**    
- * @} end of Conv group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q15.c
deleted file mode 100644
index 499e6cfb25..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q15.c
+++ /dev/null
@@ -1,1405 +0,0 @@
-/* ----------------------------------------------------------------------   
-* Copyright (C) 2010 ARM Limited. All rights reserved.   
-*   
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*   
-* Project: 	    CMSIS DSP Library   
-* Title:		arm_conv_fast_q15.c   
-*   
-* Description:	Fast Q15 Convolution.   
-*   
-* Target Processor: Cortex-M4/Cortex-M3
-* 
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-* 
-* Version 1.0.11 2011/10/18 
-*    Bug Fix in conv, correlation, partial convolution. 
-*
-* Version 1.0.10 2011/7/15 
-*    Big Endian support added and Merged M0 and M3/M4 Source code.  
-*   
-* Version 1.0.3 2010/11/29  
-*    Re-organized the CMSIS folders and updated documentation.   
-*    
-* Version 1.0.2 2010/11/11   
-*    Documentation updated.    
-*   
-* Version 1.0.1 2010/10/05    
-*    Production release and review comments incorporated.   
-*   
-* Version 1.0.0 2010/09/20    
-*    Production release and review comments incorporated.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**   
- * @ingroup groupFilters   
- */
-
-/**   
- * @addtogroup Conv   
- * @{   
- */
-
-/**   
- * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.   
- * @param[in] *pSrcA points to the first input sequence.   
- * @param[in] srcALen length of the first input sequence.   
- * @param[in] *pSrcB points to the second input sequence.   
- * @param[in] srcBLen length of the second input sequence.   
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   
- * @return none.   
- *   
- * Scaling and Overflow Behavior:   
- *   
- * \par   
- * This fast version uses a 32-bit accumulator with 2.30 format.   
- * The accumulator maintains full precision of the intermediate multiplication results   
- * but provides only a single guard bit. There is no saturation on intermediate additions.   
- * Thus, if the accumulator overflows it wraps around and distorts the result.   
- * The input signals should be scaled down to avoid intermediate overflows.   
- * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,   
- * as maximum of min(srcALen, srcBLen) number of additions are carried internally.   
- * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.   
- *   
- * \par   
- * See arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.   
- */
-
-void arm_conv_fast_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst)
-{
-#ifndef UNALIGNED_SUPPORT_DISABLE
-  q15_t *pIn1;                                   /* inputA pointer */
-  q15_t *pIn2;                                   /* inputB pointer */
-  q15_t *pOut = pDst;                            /* output pointer */
-  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
-  q15_t *px;                                     /* Intermediate inputA pointer  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
-  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
-  uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt;     /* loop counter */
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcA;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcB;
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcB;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcA;
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-  }
-
-  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
-  /* The function is internally   
-   * divided into three stages according to the number of multiplications that has to be   
-   * taken place between inputA samples and inputB samples. In the first stage of the   
-   * algorithm, the multiplications increase by one for every iteration.   
-   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
-   * In the third stage of the algorithm, the multiplications decrease by one   
-   * for every iteration. */
-
-  /* The algorithm is implemented in three stages.   
-     The loop counters of each stage is initiated here. */
-  blockSize1 = srcBLen - 1u;
-  blockSize2 = srcALen - (srcBLen - 1u);
-  blockSize3 = blockSize1;
-
-  /* --------------------------   
-   * Initializations of stage1   
-   * -------------------------*/
-
-  /* sum = x[0] * y[0]   
-   * sum = x[0] * y[1] + x[1] * y[0]   
-   * ....   
-   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
-   */
-
-  /* In this stage the MAC operations are increased by 1 for every iteration.   
-     The count variable holds the number of MAC operations performed */
-  count = 1u;
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-
-  /* ------------------------   
-   * Stage1 process   
-   * ----------------------*/
-
-  /* For loop unrolling by 4, this stage is divided into two. */
-  /* First part of this stage computes the MAC operations less than 4 */
-  /* Second part of this stage computes the MAC operations greater than or equal to 4 */
-
-  /* The first part of the stage starts here */
-  while((count < 4u) && (blockSize1 > 0u))
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Loop over number of MAC operations between   
-     * inputA samples and inputB samples */
-    k = count;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      sum = __SMLAD(*px++, *py--, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q15_t) (sum >> 15);
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pIn2 + count;
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* The second part of the stage starts here */
-  /* The internal loop, over count, is unrolled by 4 */
-  /* To, read the last two inputB samples using SIMD:   
-   * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
-  py = py - 1;
-
-  while(blockSize1 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
-      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-      /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
-      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* For the next MAC operations, the pointer py is used without SIMD   
-     * So, py is incremented by 1 */
-    py = py + 1u;
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      sum = __SMLAD(*px++, *py--, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q15_t) (sum >> 15);
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pIn2 + (count - 1u);
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* --------------------------   
-   * Initializations of stage2   
-   * ------------------------*/
-
-  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
-   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
-   * ....   
-   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
-   */
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  pSrc2 = pIn2 + (srcBLen - 1u);
-  py = pSrc2;
-
-  /* count is the index by which the pointer pIn1 to be incremented */
-  count = 0u;
-
-
-  /* --------------------   
-   * Stage2 process   
-   * -------------------*/
-
-  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
-   * So, to loop unroll over blockSize2,   
-   * srcBLen should be greater than or equal to 4 */
-  if(srcBLen >= 4u)
-  {
-    /* Loop unroll over blockSize2, by 4 */
-    blkCnt = blockSize2 >> 2u;
-
-    while(blkCnt > 0u)
-    {
-      py = py - 1u;
-
-      /* Set all accumulators to zero */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-
-      /* read x[0], x[1] samples */
-      x0 = *__SIMD32(px);
-      /* read x[1], x[2] samples */
-      x1 = _SIMD32_OFFSET(px+1);
-	  px+= 2u;
-
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      do
-      {
-        /* Read the last two inputB samples using SIMD:   
-         * y[srcBLen - 1] and y[srcBLen - 2] */
-        c0 = *__SIMD32(py)--;
-
-        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
-        acc0 = __SMLADX(x0, c0, acc0);
-
-        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
-        acc1 = __SMLADX(x1, c0, acc1);
-
-        /* Read x[2], x[3] */
-        x2 = *__SIMD32(px);
-
-        /* Read x[3], x[4] */
-        x3 = _SIMD32_OFFSET(px+1);
-
-        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
-        acc2 = __SMLADX(x2, c0, acc2);
-
-        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
-        acc3 = __SMLADX(x3, c0, acc3);
-
-        /* Read y[srcBLen - 3] and y[srcBLen - 4] */
-        c0 = *__SIMD32(py)--;
-
-        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
-        acc0 = __SMLADX(x2, c0, acc0);
-
-        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
-        acc1 = __SMLADX(x3, c0, acc1);
-
-        /* Read x[4], x[5] */
-        x0 = _SIMD32_OFFSET(px+2);
-
-        /* Read x[5], x[6] */
-        x1 = _SIMD32_OFFSET(px+3);
-		px += 4u;
-
-        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
-        acc2 = __SMLADX(x0, c0, acc2);
-
-        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
-        acc3 = __SMLADX(x1, c0, acc3);
-
-      } while(--k);
-
-      /* For the next MAC operations, SIMD is not used   
-       * So, the 16 bit pointer if inputB, py is updated */
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      if(k == 1u)
-      {
-        /* Read y[srcBLen - 5] */
-        c0 = *(py+1);
-
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-
-#else
-
-        c0 = c0 & 0x0000FFFF;
-
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-
-        /* Read x[7] */
-        x3 = *__SIMD32(px);
-		px++;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLAD(x0, c0, acc0);
-        acc1 = __SMLAD(x1, c0, acc1);
-        acc2 = __SMLADX(x1, c0, acc2);
-        acc3 = __SMLADX(x3, c0, acc3);
-      }
-
-      if(k == 2u)
-      {
-        /* Read y[srcBLen - 5], y[srcBLen - 6] */
-        c0 = _SIMD32_OFFSET(py);
-
-        /* Read x[7], x[8] */
-        x3 = *__SIMD32(px);
-
-        /* Read x[9] */
-        x2 = _SIMD32_OFFSET(px+1);
-		px += 2u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLADX(x0, c0, acc0);
-        acc1 = __SMLADX(x1, c0, acc1);
-        acc2 = __SMLADX(x3, c0, acc2);
-        acc3 = __SMLADX(x2, c0, acc3);
-      }
-
-      if(k == 3u)
-      {
-        /* Read y[srcBLen - 5], y[srcBLen - 6] */
-        c0 = _SIMD32_OFFSET(py);
-
-        /* Read x[7], x[8] */
-        x3 = *__SIMD32(px);
-
-        /* Read x[9] */
-        x2 = _SIMD32_OFFSET(px+1);
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLADX(x0, c0, acc0);
-        acc1 = __SMLADX(x1, c0, acc1);
-        acc2 = __SMLADX(x3, c0, acc2);
-        acc3 = __SMLADX(x2, c0, acc3);
-
-        /* Read y[srcBLen - 7] */
-		c0 = *(py-1);
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-#else
-
-        c0 = c0 & 0x0000FFFF;
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-
-        /* Read x[10] */
-        x3 =  _SIMD32_OFFSET(px+2);
-		px += 3u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLADX(x1, c0, acc0);
-        acc1 = __SMLAD(x2, c0, acc1);
-        acc2 = __SMLADX(x2, c0, acc2);
-        acc3 = __SMLADX(x3, c0, acc3);
-      }
-
-      /* Store the results in the accumulators in the destination buffer. */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-      *__SIMD32(pOut)++ = __PKHBT((acc0 >> 15), (acc1 >> 15), 16);
-      *__SIMD32(pOut)++ = __PKHBT((acc2 >> 15), (acc3 >> 15), 16);
-
-#else
-
-      *__SIMD32(pOut)++ = __PKHBT((acc1 >> 15), (acc0 >> 15), 16);
-      *__SIMD32(pOut)++ = __PKHBT((acc3 >> 15), (acc2 >> 15), 16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-      /* Increment the pointer pIn1 index, count by 4 */
-      count += 4u;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
-     ** No loop unrolling is used. */
-    blkCnt = blockSize2 % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += ((q31_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (sum >> 15);
-
-      /* Increment the pointer pIn1 index, count by 1 */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-  else
-  {
-    /* If the srcBLen is not a multiple of 4,   
-     * the blockSize2 loop cannot be unrolled by 4 */
-    blkCnt = blockSize2;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* srcBLen number of MACS should be performed */
-      k = srcBLen;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += ((q31_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (sum >> 15);
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-
-
-  /* --------------------------   
-   * Initializations of stage3   
-   * -------------------------*/
-
-  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
-   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
-   * ....   
-   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
-   * sum +=  x[srcALen-1] * y[srcBLen-1]   
-   */
-
-  /* In this stage the MAC operations are decreased by 1 for every iteration.   
-     The blockSize3 variable holds the number of MAC operations performed */
-
-  /* Working pointer of inputA */
-  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-  px = pSrc1;
-
-  /* Working pointer of inputB */
-  pSrc2 = pIn2 + (srcBLen - 1u);
-  pIn2 = pSrc2 - 1u;
-  py = pIn2;
-
-  /* -------------------   
-   * Stage3 process   
-   * ------------------*/
-
-  /* For loop unrolling by 4, this stage is divided into two. */
-  /* First part of this stage computes the MAC operations greater than 4 */
-  /* Second part of this stage computes the MAC operations less than or equal to 4 */
-
-  /* The first part of the stage starts here */
-  j = blockSize3 >> 2u;
-
-  while((j > 0u) && (blockSize3 > 0u))
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = blockSize3 >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   
-       * with y[srcBLen - 1], y[srcBLen - 2] respectively */
-      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-      /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   
-       * with y[srcBLen - 3], y[srcBLen - 4] respectively */
-      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* For the next MAC operations, the pointer py is used without SIMD   
-     * So, py is incremented by 1 */
-    py = py + 1u;
-
-    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = blockSize3 % 0x4u;
-
-    while(k > 0u)
-    {
-      /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
-      sum = __SMLAD(*px++, *py--, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q15_t) (sum >> 15);
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pIn2;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-
-    j--;
-  }
-
-  /* The second part of the stage starts here */
-  /* SIMD is not used for the next MAC operations,   
-   * so pointer py is updated to read only one sample at a time */
-  py = py + 1u;
-
-  while(blockSize3 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = blockSize3;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* sum +=  x[srcALen-1] * y[srcBLen-1] */
-      sum = __SMLAD(*px++, *py--, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q15_t) (sum >> 15);
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pSrc2;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-  }
-
-#else
-  q15_t *pIn1;                                   /* inputA pointer */
-  q15_t *pIn2;                                   /* inputB pointer */
-  q15_t *pOut = pDst;                            /* output pointer */
-  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
-  q15_t *px;                                     /* Intermediate inputA pointer  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
-  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
-  uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt;     /* loop counter */
-  q15_t a, b;
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcA;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcB;
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcB;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcA;
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-  }
-
-  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
-  /* The function is internally   
-   * divided into three stages according to the number of multiplications that has to be   
-   * taken place between inputA samples and inputB samples. In the first stage of the   
-   * algorithm, the multiplications increase by one for every iteration.   
-   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
-   * In the third stage of the algorithm, the multiplications decrease by one   
-   * for every iteration. */
-
-  /* The algorithm is implemented in three stages.   
-     The loop counters of each stage is initiated here. */
-  blockSize1 = srcBLen - 1u;
-  blockSize2 = srcALen - (srcBLen - 1u);
-  blockSize3 = blockSize1;
-
-  /* --------------------------   
-   * Initializations of stage1   
-   * -------------------------*/
-
-  /* sum = x[0] * y[0]   
-   * sum = x[0] * y[1] + x[1] * y[0]   
-   * ....   
-   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
-   */
-
-  /* In this stage the MAC operations are increased by 1 for every iteration.   
-     The count variable holds the number of MAC operations performed */
-  count = 1u;
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-
-  /* ------------------------   
-   * Stage1 process   
-   * ----------------------*/
-
-  /* For loop unrolling by 4, this stage is divided into two. */
-  /* First part of this stage computes the MAC operations less than 4 */
-  /* Second part of this stage computes the MAC operations greater than or equal to 4 */
-
-  /* The first part of the stage starts here */
-  while((count < 4u) && (blockSize1 > 0u))
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Loop over number of MAC operations between   
-     * inputA samples and inputB samples */
-    k = count;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      sum += ((q31_t) * px++ * *py--);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q15_t) (sum >> 15);
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pIn2 + count;
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* The second part of the stage starts here */
-  /* The internal loop, over count, is unrolled by 4 */
-  /* To, read the last two inputB samples using SIMD:   
-   * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
-  py = py - 1;
-
-  while(blockSize1 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-	py++;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      sum += ((q31_t) * px++ * *py--);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q15_t) (sum >> 15);
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pIn2 + (count - 1u);
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* --------------------------   
-   * Initializations of stage2   
-   * ------------------------*/
-
-  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
-   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
-   * ....   
-   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
-   */
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  pSrc2 = pIn2 + (srcBLen - 1u);
-  py = pSrc2;
-
-  /* count is the index by which the pointer pIn1 to be incremented */
-  count = 0u;
-
-
-  /* --------------------   
-   * Stage2 process   
-   * -------------------*/
-
-  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
-   * So, to loop unroll over blockSize2,   
-   * srcBLen should be greater than or equal to 4 */
-  if(srcBLen >= 4u)
-  {
-    /* Loop unroll over blockSize2, by 4 */
-    blkCnt = blockSize2 >> 2u;
-
-    while(blkCnt > 0u)
-    {
-      py = py - 1u;
-
-      /* Set all accumulators to zero */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;	  
-
-      /* read x[0], x[1] samples */
-	  a = *px++;
-	  b = *px++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-	  x0 = __PKHBT(a, b, 16);
-	  a = *px;
-	  x1 = __PKHBT(b, a, 16);
-
-#else
-
-	  x0 = __PKHBT(b, a, 16);
-	  a = *px;
-	  x1 = __PKHBT(a, b, 16);
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      do
-      {
-        /* Read the last two inputB samples using SIMD:   
-         * y[srcBLen - 1] and y[srcBLen - 2] */
-		a = *py;
-		b = *(py+1);
-		py -= 2;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-		c0 = __PKHBT(a, b, 16);
-
-#else
-
- 		c0 = __PKHBT(b, a, 16);;
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
-        acc0 = __SMLADX(x0, c0, acc0);
-
-        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
-        acc1 = __SMLADX(x1, c0, acc1);
-
-	  a = *px;
-	  b = *(px + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-	  x2 = __PKHBT(a, b, 16);
-	  a = *(px + 2);
-	  x3 = __PKHBT(b, a, 16);
-
-#else
-
-	  x2 = __PKHBT(b, a, 16);
-	  a = *(px + 2);
-	  x3 = __PKHBT(a, b, 16);
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
-
-        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
-        acc2 = __SMLADX(x2, c0, acc2);
-
-        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
-        acc3 = __SMLADX(x3, c0, acc3);
-
-        /* Read y[srcBLen - 3] and y[srcBLen - 4] */
-		a = *py;
-		b = *(py+1);
-		py -= 2;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-		c0 = __PKHBT(a, b, 16);
-
-#else
-
- 		c0 = __PKHBT(b, a, 16);;
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
-        acc0 = __SMLADX(x2, c0, acc0);
-
-        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
-        acc1 = __SMLADX(x3, c0, acc1);
-
-        /* Read x[4], x[5], x[6] */
-	  a = *(px + 2);
-	  b = *(px + 3);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-	  x0 = __PKHBT(a, b, 16);
-	  a = *(px + 4);
-	  x1 = __PKHBT(b, a, 16);
-
-#else
-
-	  x0 = __PKHBT(b, a, 16);
-	  a = *(px + 4);
-	  x1 = __PKHBT(a, b, 16);
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
-
-		px += 4u;
-
-        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
-        acc2 = __SMLADX(x0, c0, acc2);
-
-        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
-        acc3 = __SMLADX(x1, c0, acc3);
-
-      } while(--k);
-
-      /* For the next MAC operations, SIMD is not used   
-       * So, the 16 bit pointer if inputB, py is updated */
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      if(k == 1u)
-      {
-        /* Read y[srcBLen - 5] */
-        c0 = *(py+1);
-
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-
-#else
-
-        c0 = c0 & 0x0000FFFF;
-
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-
-        /* Read x[7] */
-		a = *px;
-		b = *(px+1);
-		px++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-		x3 = __PKHBT(a, b, 16);
-
-#else
-
- 		x3 = __PKHBT(b, a, 16);;
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLAD(x0, c0, acc0);
-        acc1 = __SMLAD(x1, c0, acc1);
-        acc2 = __SMLADX(x1, c0, acc2);
-        acc3 = __SMLADX(x3, c0, acc3);
-      }
-
-      if(k == 2u)
-      {
-        /* Read y[srcBLen - 5], y[srcBLen - 6] */
-		a = *py;
-		b = *(py+1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-		c0 = __PKHBT(a, b, 16);
-
-#else
-
- 		c0 = __PKHBT(b, a, 16);;
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-        /* Read x[7], x[8], x[9] */
-	  a = *px;
-	  b = *(px + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-	  x3 = __PKHBT(a, b, 16);
-	  a = *(px + 2);
-	  x2 = __PKHBT(b, a, 16);
-
-#else
-
-	  x3 = __PKHBT(b, a, 16);
-	  a = *(px + 2);
-	  x2 = __PKHBT(a, b, 16);
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
-		px += 2u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLADX(x0, c0, acc0);
-        acc1 = __SMLADX(x1, c0, acc1);
-        acc2 = __SMLADX(x3, c0, acc2);
-        acc3 = __SMLADX(x2, c0, acc3);
-      }
-
-      if(k == 3u)
-      {
-        /* Read y[srcBLen - 5], y[srcBLen - 6] */
-		a = *py;
-		b = *(py+1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-		c0 = __PKHBT(a, b, 16);
-
-#else
-
- 		c0 = __PKHBT(b, a, 16);;
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-        /* Read x[7], x[8], x[9] */
-	  a = *px;
-	  b = *(px + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-	  x3 = __PKHBT(a, b, 16);
-	  a = *(px + 2);
-	  x2 = __PKHBT(b, a, 16);
-
-#else
-
-	  x3 = __PKHBT(b, a, 16);
-	  a = *(px + 2);
-	  x2 = __PKHBT(a, b, 16);
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLADX(x0, c0, acc0);
-        acc1 = __SMLADX(x1, c0, acc1);
-        acc2 = __SMLADX(x3, c0, acc2);
-        acc3 = __SMLADX(x2, c0, acc3);
-
-        /* Read y[srcBLen - 7] */
-		c0 = *(py-1);
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-#else
-
-        c0 = c0 & 0x0000FFFF;
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-
-        /* Read x[10] */
-		a = *(px+2);
-		b = *(px+3);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-		x3 = __PKHBT(a, b, 16);
-
-#else
-
- 		x3 = __PKHBT(b, a, 16);;
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-		px += 3u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLADX(x1, c0, acc0);
-        acc1 = __SMLAD(x2, c0, acc1);
-        acc2 = __SMLADX(x2, c0, acc2);
-        acc3 = __SMLADX(x3, c0, acc3);
-      }
-
-      /* Store the results in the accumulators in the destination buffer. */
-	  *pOut++ = (q15_t)(acc0 >> 15);
-	  *pOut++ = (q15_t)(acc1 >> 15);
-	  *pOut++ = (q15_t)(acc2 >> 15);
-	  *pOut++ = (q15_t)(acc3 >> 15);
-
-      /* Increment the pointer pIn1 index, count by 4 */
-      count += 4u;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
-     ** No loop unrolling is used. */
-    blkCnt = blockSize2 % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += ((q31_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (sum >> 15);
-
-      /* Increment the pointer pIn1 index, count by 1 */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-  else
-  {
-    /* If the srcBLen is not a multiple of 4,   
-     * the blockSize2 loop cannot be unrolled by 4 */
-    blkCnt = blockSize2;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* srcBLen number of MACS should be performed */
-      k = srcBLen;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += ((q31_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (sum >> 15);
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-
-
-  /* --------------------------   
-   * Initializations of stage3   
-   * -------------------------*/
-
-  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
-   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
-   * ....   
-   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
-   * sum +=  x[srcALen-1] * y[srcBLen-1]   
-   */
-
-  /* In this stage the MAC operations are decreased by 1 for every iteration.   
-     The blockSize3 variable holds the number of MAC operations performed */
-
-  /* Working pointer of inputA */
-  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-  px = pSrc1;
-
-  /* Working pointer of inputB */
-  pSrc2 = pIn2 + (srcBLen - 1u);
-  pIn2 = pSrc2 - 1u;
-  py = pIn2;
-
-  /* -------------------   
-   * Stage3 process   
-   * ------------------*/
-
-  /* For loop unrolling by 4, this stage is divided into two. */
-  /* First part of this stage computes the MAC operations greater than 4 */
-  /* Second part of this stage computes the MAC operations less than or equal to 4 */
-
-  /* The first part of the stage starts here */
-  j = blockSize3 >> 2u;
-
-  while((j > 0u) && (blockSize3 > 0u))
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = blockSize3 >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-	py++;
-
-    while(k > 0u)
-    {	
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = blockSize3 % 0x4u;
-
-    while(k > 0u)
-    {
-      /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
-        sum += ((q31_t) * px++ * *py--);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q15_t) (sum >> 15);
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pIn2;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-
-    j--;
-  }
-
-  /* The second part of the stage starts here */
-  /* SIMD is not used for the next MAC operations,   
-   * so pointer py is updated to read only one sample at a time */
-  py = py + 1u;
-
-  while(blockSize3 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = blockSize3;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* sum +=  x[srcALen-1] * y[srcBLen-1] */
-        sum += ((q31_t) * px++ * *py--);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q15_t) (sum >> 15);
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pSrc2;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-  }
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-}
-
-/**   
- * @} end of Conv group   
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q31.c
deleted file mode 100644
index 46c694b707..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q31.c
+++ /dev/null
@@ -1,572 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_conv_fast_q31.c    
-*    
-* Description:	Q31 Convolution (fast version).    
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*  
-* Version 1.0.11 2011/10/18  
-*    Bug Fix in conv, correlation, partial convolution.  
-* 
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup Conv    
- * @{    
- */
-
-/**    
- * @param[in] *pSrcA points to the first input sequence.    
- * @param[in] srcALen length of the first input sequence.    
- * @param[in] *pSrcB points to the second input sequence.    
- * @param[in] srcBLen length of the second input sequence.    
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * This function is optimized for speed at the expense of fixed-point precision and overflow protection.    
- * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.    
- * These intermediate results are accumulated in a 32-bit register in 2.30 format.    
- * Finally, the accumulator is saturated and converted to a 1.31 result.    
- *    
- * \par    
- * The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result.    
- * In order to avoid overflows completely the input signals must be scaled down.    
- * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,    
- * as maximum of min(srcALen, srcBLen) number of additions are carried internally.    
- *    
- * \par    
- * See arm_conv_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.    
- */
-
-void arm_conv_fast_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst)
-{
-  q31_t *pIn1;                                   /* inputA pointer */
-  q31_t *pIn2;                                   /* inputB pointer */
-  q31_t *pOut = pDst;                            /* output pointer */
-  q31_t *px;                                     /* Intermediate inputA pointer  */
-  q31_t *py;                                     /* Intermediate inputB pointer  */
-  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
-  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
-  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
-  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counter */
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcA;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcB;
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcB;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcA;
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-  }
-
-  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
-  /* The function is internally    
-   * divided into three stages according to the number of multiplications that has to be    
-   * taken place between inputA samples and inputB samples. In the first stage of the    
-   * algorithm, the multiplications increase by one for every iteration.    
-   * In the second stage of the algorithm, srcBLen number of multiplications are done.    
-   * In the third stage of the algorithm, the multiplications decrease by one    
-   * for every iteration. */
-
-  /* The algorithm is implemented in three stages.    
-     The loop counters of each stage is initiated here. */
-  blockSize1 = srcBLen - 1u;
-  blockSize2 = srcALen - (srcBLen - 1u);
-  blockSize3 = blockSize1;
-
-  /* --------------------------    
-   * Initializations of stage1    
-   * -------------------------*/
-
-  /* sum = x[0] * y[0]    
-   * sum = x[0] * y[1] + x[1] * y[0]    
-   * ....    
-   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]    
-   */
-
-  /* In this stage the MAC operations are increased by 1 for every iteration.    
-     The count variable holds the number of MAC operations performed */
-  count = 1u;
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-
-  /* ------------------------    
-   * Stage1 process    
-   * ----------------------*/
-
-  /* The first stage starts here */
-  while(blockSize1 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* x[0] * y[srcBLen - 1] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py--))) >> 32);
-
-      /* x[1] * y[srcBLen - 2] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py--))) >> 32);
-
-      /* x[2] * y[srcBLen - 3] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py--))) >> 32);
-
-      /* x[3] * y[srcBLen - 4] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py--))) >> 32);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.    
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py--))) >> 32);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = sum << 1;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pIn2 + count;
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* --------------------------    
-   * Initializations of stage2    
-   * ------------------------*/
-
-  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]    
-   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]    
-   * ....    
-   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]    
-   */
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  pSrc2 = pIn2 + (srcBLen - 1u);
-  py = pSrc2;
-
-  /* count is index by which the pointer pIn1 to be incremented */
-  count = 0u;
-
-  /* -------------------    
-   * Stage2 process    
-   * ------------------*/
-
-  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
-   * So, to loop unroll over blockSize2,    
-   * srcBLen should be greater than or equal to 4 */
-  if(srcBLen >= 4u)
-  {
-    /* Loop unroll over blockSize2, by 4 */
-    blkCnt = blockSize2 >> 2u;
-
-    while(blkCnt > 0u)
-    {
-      /* Set all accumulators to zero */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-      /* read x[0], x[1], x[2] samples */
-      x0 = *(px++);
-      x1 = *(px++);
-      x2 = *(px++);
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      do
-      {
-        /* Read y[srcBLen - 1] sample */
-        c0 = *(py--);
-
-        /* Read x[3] sample */
-        x3 = *(px++);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[0] * y[srcBLen - 1] */
-        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
-
-        /* acc1 +=  x[1] * y[srcBLen - 1] */
-        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
-
-        /* acc2 +=  x[2] * y[srcBLen - 1] */
-        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
-
-        /* acc3 +=  x[3] * y[srcBLen - 1] */
-        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
-
-        /* Read y[srcBLen - 2] sample */
-        c0 = *(py--);
-
-        /* Read x[4] sample */
-        x0 = *(px++);
-
-        /* Perform the multiply-accumulate */
-        /* acc0 +=  x[1] * y[srcBLen - 2] */
-        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
-        /* acc1 +=  x[2] * y[srcBLen - 2] */
-        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
-        /* acc2 +=  x[3] * y[srcBLen - 2] */
-        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
-        /* acc3 +=  x[4] * y[srcBLen - 2] */
-        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
-
-        /* Read y[srcBLen - 3] sample */
-        c0 = *(py--);
-
-        /* Read x[5] sample */
-        x1 = *(px++);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[2] * y[srcBLen - 3] */
-        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
-        /* acc1 +=  x[3] * y[srcBLen - 3] */
-        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
-        /* acc2 +=  x[4] * y[srcBLen - 3] */
-        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
-        /* acc3 +=  x[5] * y[srcBLen - 3] */
-        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
-
-        /* Read y[srcBLen - 4] sample */
-        c0 = *(py--);
-
-        /* Read x[6] sample */
-        x2 = *(px++);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[3] * y[srcBLen - 4] */
-        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
-        /* acc1 +=  x[4] * y[srcBLen - 4] */
-        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
-        /* acc2 +=  x[5] * y[srcBLen - 4] */
-        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
-        /* acc3 +=  x[6] * y[srcBLen - 4] */
-        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
-
-
-      } while(--k);
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Read y[srcBLen - 5] sample */
-        c0 = *(py--);
-
-        /* Read x[7] sample */
-        x3 = *(px++);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[4] * y[srcBLen - 5] */
-        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
-        /* acc1 +=  x[5] * y[srcBLen - 5] */
-        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
-        /* acc2 +=  x[6] * y[srcBLen - 5] */
-        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
-        /* acc3 +=  x[7] * y[srcBLen - 5] */
-        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
-
-        /* Reuse the present samples for the next MAC */
-        x0 = x1;
-        x1 = x2;
-        x2 = x3;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the results in the accumulators in the destination buffer. */
-      *pOut++ = (q31_t) (acc0 << 1);
-      *pOut++ = (q31_t) (acc1 << 1);
-      *pOut++ = (q31_t) (acc2 << 1);
-      *pOut++ = (q31_t) (acc3 << 1);
-
-      /* Increment the pointer pIn1 index, count by 4 */
-      count += 4u;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.    
-     ** No loop unrolling is used. */
-    blkCnt = blockSize2 % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = sum << 1;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-  else
-  {
-    /* If the srcBLen is not a multiple of 4,    
-     * the blockSize2 loop cannot be unrolled by 4 */
-    blkCnt = blockSize2;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* srcBLen number of MACS should be performed */
-      k = srcBLen;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = sum << 1;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-
-
-  /* --------------------------    
-   * Initializations of stage3    
-   * -------------------------*/
-
-  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]    
-   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]    
-   * ....    
-   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]    
-   * sum +=  x[srcALen-1] * y[srcBLen-1]    
-   */
-
-  /* In this stage the MAC operations are decreased by 1 for every iteration.    
-     The blockSize3 variable holds the number of MAC operations performed */
-
-  /* Working pointer of inputA */
-  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-  px = pSrc1;
-
-  /* Working pointer of inputB */
-  pSrc2 = pIn2 + (srcBLen - 1u);
-  py = pSrc2;
-
-  /* -------------------    
-   * Stage3 process    
-   * ------------------*/
-
-  while(blockSize3 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = blockSize3 >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py--))) >> 32);
-
-      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py--))) >> 32);
-
-      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py--))) >> 32);
-
-      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py--))) >> 32);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.    
-     ** No loop unrolling is used. */
-    k = blockSize3 % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py--))) >> 32);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = sum << 1;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pSrc2;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-  }
-
-}
-
-/**    
- * @} end of Conv group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q15.c
deleted file mode 100644
index 2d9ada7be2..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q15.c
+++ /dev/null
@@ -1,544 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_conv_opt_q15.c    
-*    
-* Description:	Convolution of Q15 sequences.      
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.11 2011/10/18  
-*    Bug Fix in conv, correlation, partial convolution.  
-* 
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-*    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup Conv    
- * @{    
- */
-
-/**    
- * @brief Convolution of Q15 sequences.    
- * @param[in] *pSrcA points to the first input sequence.    
- * @param[in] srcALen length of the first input sequence.    
- * @param[in] *pSrcB points to the second input sequence.    
- * @param[in] srcBLen length of the second input sequence.    
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.    
- * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.    
- * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).    
- * @return none.    
- *    
- * \par Restrictions    
- *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
- *	In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit    
- *    
- *       
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The function is implemented using a 64-bit internal accumulator.    
- * Both inputs are in 1.15 format and multiplications yield a 2.30 result.    
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    
- * This approach provides 33 guard bits and there is no risk of overflow.    
- * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.    
- *  
- *   
- * \par    
- * Refer to arm_conv_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.     
- * 
- *  
- */
-
-void arm_conv_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2)
-{
-  q63_t acc0, acc1, acc2, acc3;                  /* Accumulator */
-  q31_t x1, x2, x3;                              /* Temporary variables to hold state and coefficient values */
-  q31_t y1, y2;                                  /* State variables */
-  q15_t *pOut = pDst;                            /* output pointer */
-  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */
-  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */
-  q15_t *pIn1;                                   /* inputA pointer */
-  q15_t *pIn2;                                   /* inputB pointer */
-  q15_t *px;                                     /* Intermediate inputA pointer  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  uint32_t j, k, blkCnt;                         /* loop counter */
-  uint32_t tapCnt;                               /* loop count */
-#ifdef UNALIGNED_SUPPORT_DISABLE
-
-  q15_t a, b;
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcA;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcB;
-
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcB;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcA;
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-  }
-
-  /* pointer to take end of scratch2 buffer */
-  pScr2 = pScratch2 + srcBLen - 1;
-
-  /* points to smaller length sequence */
-  px = pIn2;
-
-  /* Apply loop unrolling and do 4 Copies simultaneously. */
-  k = srcBLen >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-  /* Copy smaller length input sequence in reverse order into second scratch buffer */
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    *pScr2-- = *px++;
-    *pScr2-- = *px++;
-    *pScr2-- = *px++;
-    *pScr2-- = *px++;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  k = srcBLen % 0x4u;
-
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    *pScr2-- = *px++;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* Initialze temporary scratch pointer */
-  pScr1 = pScratch1;
-
-  /* Assuming scratch1 buffer is aligned by 32-bit */
-  /* Fill (srcBLen - 1u) zeros in scratch buffer */
-  arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-  /* Update temporary scratch pointer */
-  pScr1 += (srcBLen - 1u);
-
-  /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-  /* Copy (srcALen) samples in scratch buffer */
-  arm_copy_q15(pIn1, pScr1, srcALen);
-
-  /* Update pointers */
-  pScr1 += srcALen;
-
-#else
-
-  /* Apply loop unrolling and do 4 Copies simultaneously. */
-  k = srcALen >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    *pScr1++ = *pIn1++;
-    *pScr1++ = *pIn1++;
-    *pScr1++ = *pIn1++;
-    *pScr1++ = *pIn1++;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  k = srcALen % 0x4u;
-
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    *pScr1++ = *pIn1++;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-#endif
-
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-  /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
-  arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-  /* Update pointer */
-  pScr1 += (srcBLen - 1u);
-
-#else
-
-  /* Apply loop unrolling and do 4 Copies simultaneously. */
-  k = (srcBLen - 1u) >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    *pScr1++ = 0;
-    *pScr1++ = 0;
-    *pScr1++ = 0;
-    *pScr1++ = 0;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  k = (srcBLen - 1u) % 0x4u;
-
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    *pScr1++ = 0;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-#endif
-
-  /* Temporary pointer for scratch2 */
-  py = pScratch2;
-
-
-  /* Initialization of pIn2 pointer */
-  pIn2 = py;
-
-  /* First part of the processing with loop unrolling process 4 data points at a time.       
-   ** a second loop below process for the remaining 1 to 3 samples. */
-
-  /* Actual convolution process starts here */
-  blkCnt = (srcALen + srcBLen - 1u) >> 2;
-
-  while(blkCnt > 0)
-  {
-    /* Initialze temporary scratch pointer as scratch1 */
-    pScr1 = pScratch1;
-
-    /* Clear Accumlators */
-    acc0 = 0;
-    acc1 = 0;
-    acc2 = 0;
-    acc3 = 0;
-
-    /* Read two samples from scratch1 buffer */
-    x1 = *__SIMD32(pScr1)++;
-
-    /* Read next two samples from scratch1 buffer */
-    x2 = *__SIMD32(pScr1)++;
-
-    tapCnt = (srcBLen) >> 2u;
-
-    while(tapCnt > 0u)
-    {
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-      /* Read four samples from smaller buffer */
-      y1 = _SIMD32_OFFSET(pIn2);
-      y2 = _SIMD32_OFFSET(pIn2 + 2u);
-
-      /* multiply and accumlate */
-      acc0 = __SMLALD(x1, y1, acc0);
-      acc2 = __SMLALD(x2, y1, acc2);
-
-      /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      /* multiply and accumlate */
-      acc1 = __SMLALDX(x3, y1, acc1);
-
-      /* Read next two samples from scratch1 buffer */
-      x1 = _SIMD32_OFFSET(pScr1);
-
-      /* multiply and accumlate */
-      acc0 = __SMLALD(x2, y2, acc0);
-      acc2 = __SMLALD(x1, y2, acc2);
-
-      /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x1, x2, 0);
-#else
-      x3 = __PKHBT(x2, x1, 0);
-#endif
-
-      acc3 = __SMLALDX(x3, y1, acc3);
-      acc1 = __SMLALDX(x3, y2, acc1);
-
-      x2 = _SIMD32_OFFSET(pScr1 + 2u);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc3 = __SMLALDX(x3, y2, acc3);
-
-#else	 
-
-      /* Read four samples from smaller buffer */
-	  a = *pIn2;
-	  b = *(pIn2 + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      y1 = __PKHBT(a, b, 16);
-#else
-      y1 = __PKHBT(b, a, 16);
-#endif
-	  
-	  a = *(pIn2 + 2);
-	  b = *(pIn2 + 3);
-#ifndef ARM_MATH_BIG_ENDIAN
-      y2 = __PKHBT(a, b, 16);
-#else
-      y2 = __PKHBT(b, a, 16);
-#endif				
-
-      acc0 = __SMLALD(x1, y1, acc0);
-
-      acc2 = __SMLALD(x2, y1, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc1 = __SMLALDX(x3, y1, acc1);
-
-	  a = *pScr1;
-	  b = *(pScr1 + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x1 = __PKHBT(a, b, 16);
-#else
-      x1 = __PKHBT(b, a, 16);
-#endif
-
-      acc0 = __SMLALD(x2, y2, acc0);
-
-      acc2 = __SMLALD(x1, y2, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x1, x2, 0);
-#else
-      x3 = __PKHBT(x2, x1, 0);
-#endif
-
-      acc3 = __SMLALDX(x3, y1, acc3);
-
-      acc1 = __SMLALDX(x3, y2, acc1);
-
-	  a = *(pScr1 + 2);
-	  b = *(pScr1 + 3);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x2 = __PKHBT(a, b, 16);
-#else
-      x2 = __PKHBT(b, a, 16);
-#endif
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc3 = __SMLALDX(x3, y2, acc3);
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-      pIn2 += 4u;
-      pScr1 += 4u;
-
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Update scratch pointer for remaining samples of smaller length sequence */
-    pScr1 -= 4u;
-
-    /* apply same above for remaining samples of smaller length sequence */
-    tapCnt = (srcBLen) & 3u;
-
-    while(tapCnt > 0u)
-    {
-
-      /* accumlate the results */
-      acc0 += (*pScr1++ * *pIn2);
-      acc1 += (*pScr1++ * *pIn2);
-      acc2 += (*pScr1++ * *pIn2);
-      acc3 += (*pScr1++ * *pIn2++);
-
-      pScr1 -= 3u;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    blkCnt--;
-
-
-    /* Store the results in the accumulators in the destination buffer. */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    *__SIMD32(pOut)++ =
-      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
-
-    *__SIMD32(pOut)++ =
-      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
-
-#else
-
-    *__SIMD32(pOut)++ =
-      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
-
-    *__SIMD32(pOut)++ =
-      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
-
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */
-
-    /* Initialization of inputB pointer */
-    pIn2 = py;
-
-    pScratch1 += 4u;
-
-  }
-
-
-  blkCnt = (srcALen + srcBLen - 1u) & 0x3;
-
-  /* Calculate convolution for remaining samples of Bigger length sequence */
-  while(blkCnt > 0)
-  {
-    /* Initialze temporary scratch pointer as scratch1 */
-    pScr1 = pScratch1;
-
-    /* Clear Accumlators */
-    acc0 = 0;
-
-    tapCnt = (srcBLen) >> 1u;
-
-    while(tapCnt > 0u)
-    {
-
-      /* Read next two samples from scratch1 buffer */
-      acc0 += (*pScr1++ * *pIn2++);
-      acc0 += (*pScr1++ * *pIn2++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    tapCnt = (srcBLen) & 1u;
-
-    /* apply same above for remaining samples of smaller length sequence */
-    while(tapCnt > 0u)
-    {
-
-      /* accumlate the results */
-      acc0 += (*pScr1++ * *pIn2++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    blkCnt--;
-
-    /* The result is in 2.30 format.  Convert to 1.15 with saturation.       
-     ** Then store the output in the destination buffer. */
-    *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-
-
-    /* Initialization of inputB pointer */
-    pIn2 = py;
-
-    pScratch1 += 1u;
-
-  }
-
-}
-
-
-/**    
- * @} end of Conv group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q7.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q7.c
deleted file mode 100644
index b57e4a24b0..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q7.c
+++ /dev/null
@@ -1,434 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_conv_opt_q7.c    
-*    
-* Description:	Convolution of Q7 sequences.  
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*  
-* Version 1.0.11 2011/10/18  
-*    Bug Fix in conv, correlation, partial convolution.  
-* 
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-*    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup Conv    
- * @{    
- */
-
-/**    
- * @brief Convolution of Q7 sequences.    
- * @param[in] *pSrcA points to the first input sequence.    
- * @param[in] srcALen length of the first input sequence.    
- * @param[in] *pSrcB points to the second input sequence.    
- * @param[in] srcBLen length of the second input sequence.    
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.    
- * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
- * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).   
- * @return none.    
- *    
- * \par Restrictions    
- *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
- *	In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit     
- *       
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The function is implemented using a 32-bit internal accumulator.    
- * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.    
- * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.    
- * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.    
- * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.    
- *
- */
-
-void arm_conv_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2)
-{
-
-  q15_t *pScr2, *pScr1;                          /* Intermediate pointers for scratch pointers */
-  q15_t x4;                                      /* Temporary input variable */
-  q7_t *pIn1, *pIn2;                             /* inputA and inputB pointer */
-  uint32_t j, k, blkCnt, tapCnt;                 /* loop counter */
-  q7_t *px;                                      /* Temporary input1 pointer */
-  q15_t *py;                                     /* Temporary input2 pointer */
-  q31_t acc0, acc1, acc2, acc3;                  /* Accumulator */
-  q31_t x1, x2, x3, y1;                          /* Temporary input variables */
-  q7_t *pOut = pDst;                             /* output pointer */
-  q7_t out0, out1, out2, out3;                   /* temporary variables */
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcA;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcB;
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcB;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcA;
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-  }
-
-  /* pointer to take end of scratch2 buffer */
-  pScr2 = pScratch2;
-
-  /* points to smaller length sequence */
-  px = pIn2 + srcBLen - 1;
-
-  /* Apply loop unrolling and do 4 Copies simultaneously. */
-  k = srcBLen >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    x4 = (q15_t) * px--;
-    *pScr2++ = x4;
-    x4 = (q15_t) * px--;
-    *pScr2++ = x4;
-    x4 = (q15_t) * px--;
-    *pScr2++ = x4;
-    x4 = (q15_t) * px--;
-    *pScr2++ = x4;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  k = srcBLen % 0x4u;
-
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    x4 = (q15_t) * px--;
-    *pScr2++ = x4;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* Initialze temporary scratch pointer */
-  pScr1 = pScratch1;
-
-  /* Fill (srcBLen - 1u) zeros in scratch buffer */
-  arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-  /* Update temporary scratch pointer */
-  pScr1 += (srcBLen - 1u);
-
-  /* Copy (srcALen) samples in scratch buffer */
-  /* Apply loop unrolling and do 4 Copies simultaneously. */
-  k = srcALen >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    x4 = (q15_t) * pIn1++;
-    *pScr1++ = x4;
-    x4 = (q15_t) * pIn1++;
-    *pScr1++ = x4;
-    x4 = (q15_t) * pIn1++;
-    *pScr1++ = x4;
-    x4 = (q15_t) * pIn1++;
-    *pScr1++ = x4;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  k = srcALen % 0x4u;
-
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    x4 = (q15_t) * pIn1++;
-    *pScr1++ = x4;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-  /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
-  arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-  /* Update pointer */
-  pScr1 += (srcBLen - 1u);
-
-#else
-
-  /* Apply loop unrolling and do 4 Copies simultaneously. */
-  k = (srcBLen - 1u) >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    *pScr1++ = 0;
-    *pScr1++ = 0;
-    *pScr1++ = 0;
-    *pScr1++ = 0;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  k = (srcBLen - 1u) % 0x4u;
-
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    *pScr1++ = 0;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-#endif
-
-  /* Temporary pointer for scratch2 */
-  py = pScratch2;
-
-  /* Initialization of pIn2 pointer */
-  pIn2 = (q7_t *) py;
-
-  pScr2 = py;
-
-  /* Actual convolution process starts here */
-  blkCnt = (srcALen + srcBLen - 1u) >> 2;
-
-  while(blkCnt > 0)
-  {
-    /* Initialze temporary scratch pointer as scratch1 */
-    pScr1 = pScratch1;
-
-    /* Clear Accumlators */
-    acc0 = 0;
-    acc1 = 0;
-    acc2 = 0;
-    acc3 = 0;
-
-    /* Read two samples from scratch1 buffer */
-    x1 = *__SIMD32(pScr1)++;
-
-    /* Read next two samples from scratch1 buffer */
-    x2 = *__SIMD32(pScr1)++;
-
-    tapCnt = (srcBLen) >> 2u;
-
-    while(tapCnt > 0u)
-    {
-
-      /* Read four samples from smaller buffer */
-      y1 = _SIMD32_OFFSET(pScr2);
-
-      /* multiply and accumlate */
-      acc0 = __SMLAD(x1, y1, acc0);
-      acc2 = __SMLAD(x2, y1, acc2);
-
-      /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      /* multiply and accumlate */
-      acc1 = __SMLADX(x3, y1, acc1);
-
-      /* Read next two samples from scratch1 buffer */
-      x1 = *__SIMD32(pScr1)++;
-
-      /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x1, x2, 0);
-#else
-      x3 = __PKHBT(x2, x1, 0);
-#endif
-
-      acc3 = __SMLADX(x3, y1, acc3);
-
-      /* Read four samples from smaller buffer */
-      y1 = _SIMD32_OFFSET(pScr2 + 2u);
-
-      acc0 = __SMLAD(x2, y1, acc0);
-
-      acc2 = __SMLAD(x1, y1, acc2);
-
-      acc1 = __SMLADX(x3, y1, acc1);
-
-      x2 = *__SIMD32(pScr1)++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc3 = __SMLADX(x3, y1, acc3);
-
-      pScr2 += 4u;
-
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-
-
-    /* Update scratch pointer for remaining samples of smaller length sequence */
-    pScr1 -= 4u;
-
-
-    /* apply same above for remaining samples of smaller length sequence */
-    tapCnt = (srcBLen) & 3u;
-
-    while(tapCnt > 0u)
-    {
-
-      /* accumlate the results */
-      acc0 += (*pScr1++ * *pScr2);
-      acc1 += (*pScr1++ * *pScr2);
-      acc2 += (*pScr1++ * *pScr2);
-      acc3 += (*pScr1++ * *pScr2++);
-
-      pScr1 -= 3u;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    blkCnt--;
-
-    /* Store the result in the accumulator in the destination buffer. */
-    out0 = (q7_t) (__SSAT(acc0 >> 7u, 8));
-    out1 = (q7_t) (__SSAT(acc1 >> 7u, 8));
-    out2 = (q7_t) (__SSAT(acc2 >> 7u, 8));
-    out3 = (q7_t) (__SSAT(acc3 >> 7u, 8));
-
-    *__SIMD32(pOut)++ = __PACKq7(out0, out1, out2, out3);
-
-    /* Initialization of inputB pointer */
-    pScr2 = py;
-
-    pScratch1 += 4u;
-
-  }
-
-
-  blkCnt = (srcALen + srcBLen - 1u) & 0x3;
-
-  /* Calculate convolution for remaining samples of Bigger length sequence */
-  while(blkCnt > 0)
-  {
-    /* Initialze temporary scratch pointer as scratch1 */
-    pScr1 = pScratch1;
-
-    /* Clear Accumlators */
-    acc0 = 0;
-
-    tapCnt = (srcBLen) >> 1u;
-
-    while(tapCnt > 0u)
-    {
-      acc0 += (*pScr1++ * *pScr2++);
-      acc0 += (*pScr1++ * *pScr2++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    tapCnt = (srcBLen) & 1u;
-
-    /* apply same above for remaining samples of smaller length sequence */
-    while(tapCnt > 0u)
-    {
-
-      /* accumlate the results */
-      acc0 += (*pScr1++ * *pScr2++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    blkCnt--;
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
-
-    /* Initialization of inputB pointer */
-    pScr2 = py;
-
-    pScratch1 += 1u;
-
-  }
-
-}
-
-
-/**    
- * @} end of Conv group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_f32.c
deleted file mode 100644
index b3200f7e8b..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_f32.c
+++ /dev/null
@@ -1,661 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_conv_partial_f32.c    
-*    
-* Description:	Partial convolution of floating-point sequences.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-* 
-* Version 1.0.11 2011/10/18  
-*    Bug Fix in conv, correlation, partial convolution.  
-* 
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-*    
-* -------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @defgroup PartialConv Partial Convolution    
- *    
- * Partial Convolution is equivalent to Convolution except that a subset of the output samples is generated.    
- * Each function has two additional arguments.    
- * firstIndex specifies the starting index of the subset of output samples.    
- * numPoints is the number of output samples to compute.    
- * The function computes the output in the range    
- * [firstIndex, ..., firstIndex+numPoints-1].    
- * The output array pDst contains numPoints values.    
- *    
- * The allowable range of output indices is [0 srcALen+srcBLen-2].    
- * If the requested subset does not fall in this range then the functions return ARM_MATH_ARGUMENT_ERROR.    
- * Otherwise the functions return ARM_MATH_SUCCESS.    
- * \note Refer arm_conv_f32() for details on fixed point behavior.   
- *
- * 
- * Fast Versions
- *
- * \par 
- * Fast versions are supported for Q31 and Q15 of partial convolution.  Cycles for Fast versions are less compared to Q31 and Q15 of partial conv and the design requires
- * the input signals should be scaled down to avoid intermediate overflows.   
- *
- *
- * Opt Versions
- *
- * \par 
- * Opt versions are supported for Q15 and Q7.  Design uses internal scratch buffer for getting good optimisation.
- * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions of partial convolution
- */
-
-/**    
- * @addtogroup PartialConv    
- * @{    
- */
-
-/**    
- * @brief Partial convolution of floating-point sequences.    
- * @param[in]       *pSrcA points to the first input sequence.    
- * @param[in]       srcALen length of the first input sequence.    
- * @param[in]       *pSrcB points to the second input sequence.    
- * @param[in]       srcBLen length of the second input sequence.    
- * @param[out]      *pDst points to the location where the output result is written.    
- * @param[in]       firstIndex is the first output sample to start with.    
- * @param[in]       numPoints is the number of output points to be computed.    
- * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].    
- */
-
-arm_status arm_conv_partial_f32(
-  float32_t * pSrcA,
-  uint32_t srcALen,
-  float32_t * pSrcB,
-  uint32_t srcBLen,
-  float32_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints)
-{
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
-  float32_t *pIn2 = pSrcB;                       /* inputB pointer */
-  float32_t *pOut = pDst;                        /* output pointer */
-  float32_t *px;                                 /* Intermediate inputA pointer */
-  float32_t *py;                                 /* Intermediate inputB pointer */
-  float32_t *pSrc1, *pSrc2;                      /* Intermediate pointers */
-  float32_t sum, acc0, acc1, acc2, acc3;         /* Accumulator */
-  float32_t x0, x1, x2, x3, c0;                  /* Temporary variables to hold state and coefficient values */
-  uint32_t j, k, count = 0u, blkCnt, check;
-  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters */
-  arm_status status;                             /* status of Partial convolution */
-
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_MATH_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-
-    /* The algorithm implementation is based on the lengths of the inputs. */
-    /* srcB is always made to slide across srcA. */
-    /* So srcBLen is always considered as shorter or equal to srcALen */
-    if(srcALen >= srcBLen)
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcA;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcB;
-    }
-    else
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcB;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcA;
-
-      /* srcBLen is always considered as shorter or equal to srcALen */
-      j = srcBLen;
-      srcBLen = srcALen;
-      srcALen = j;
-    }
-
-    /* Conditions to check which loopCounter holds    
-     * the first and last indices of the output samples to be calculated. */
-    check = firstIndex + numPoints;
-    blockSize3 = (int32_t) check - (int32_t) srcALen;
-    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
-    blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex;
-    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
-                                     (int32_t) numPoints) : 0;
-    blockSize2 = ((int32_t) check - blockSize3) -
-      (blockSize1 + (int32_t) firstIndex);
-    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
-
-    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
-    /* The function is internally    
-     * divided into three stages according to the number of multiplications that has to be    
-     * taken place between inputA samples and inputB samples. In the first stage of the    
-     * algorithm, the multiplications increase by one for every iteration.    
-     * In the second stage of the algorithm, srcBLen number of multiplications are done.    
-     * In the third stage of the algorithm, the multiplications decrease by one    
-     * for every iteration. */
-
-    /* Set the output pointer to point to the firstIndex    
-     * of the output sample to be calculated. */
-    pOut = pDst + firstIndex;
-
-    /* --------------------------    
-     * Initializations of stage1    
-     * -------------------------*/
-
-    /* sum = x[0] * y[0]    
-     * sum = x[0] * y[1] + x[1] * y[0]    
-     * ....    
-     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]    
-     */
-
-    /* In this stage the MAC operations are increased by 1 for every iteration.    
-       The count variable holds the number of MAC operations performed.    
-       Since the partial convolution starts from from firstIndex    
-       Number of Macs to be performed is firstIndex + 1 */
-    count = 1u + firstIndex;
-
-    /* Working pointer of inputA */
-    px = pIn1;
-
-    /* Working pointer of inputB */
-    pSrc1 = pIn2 + firstIndex;
-    py = pSrc1;
-
-    /* ------------------------    
-     * Stage1 process    
-     * ----------------------*/
-
-    /* The first stage starts here */
-    while(blockSize1 > 0)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0.0f;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* x[0] * y[srcBLen - 1] */
-        sum += *px++ * *py--;
-
-        /* x[1] * y[srcBLen - 2] */
-        sum += *px++ * *py--;
-
-        /* x[2] * y[srcBLen - 3] */
-        sum += *px++ * *py--;
-
-        /* x[3] * y[srcBLen - 4] */
-        sum += *px++ * *py--;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the count is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = count % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += *px++ * *py--;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = sum;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      py = ++pSrc1;
-      px = pIn1;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Decrement the loop counter */
-      blockSize1--;
-    }
-
-    /* --------------------------    
-     * Initializations of stage2    
-     * ------------------------*/
-
-    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]    
-     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]    
-     * ....    
-     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]    
-     */
-
-    /* Working pointer of inputA */
-    px = pIn1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + (srcBLen - 1u);
-    py = pSrc2;
-
-    /* count is index by which the pointer pIn1 to be incremented */
-    count = 0u;
-
-    /* -------------------    
-     * Stage2 process    
-     * ------------------*/
-
-    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
-     * So, to loop unroll over blockSize2,    
-     * srcBLen should be greater than or equal to 4 */
-    if(srcBLen >= 4u)
-    {
-      /* Loop unroll over blockSize2, by 4 */
-      blkCnt = ((uint32_t) blockSize2 >> 2u);
-
-      while(blkCnt > 0u)
-      {
-        /* Set all accumulators to zero */
-        acc0 = 0.0f;
-        acc1 = 0.0f;
-        acc2 = 0.0f;
-        acc3 = 0.0f;
-
-        /* read x[0], x[1], x[2] samples */
-        x0 = *(px++);
-        x1 = *(px++);
-        x2 = *(px++);
-
-        /* Apply loop unrolling and compute 4 MACs simultaneously. */
-        k = srcBLen >> 2u;
-
-        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-        do
-        {
-          /* Read y[srcBLen - 1] sample */
-          c0 = *(py--);
-
-          /* Read x[3] sample */
-          x3 = *(px++);
-
-          /* Perform the multiply-accumulate */
-          /* acc0 +=  x[0] * y[srcBLen - 1] */
-          acc0 += x0 * c0;
-
-          /* acc1 +=  x[1] * y[srcBLen - 1] */
-          acc1 += x1 * c0;
-
-          /* acc2 +=  x[2] * y[srcBLen - 1] */
-          acc2 += x2 * c0;
-
-          /* acc3 +=  x[3] * y[srcBLen - 1] */
-          acc3 += x3 * c0;
-
-          /* Read y[srcBLen - 2] sample */
-          c0 = *(py--);
-
-          /* Read x[4] sample */
-          x0 = *(px++);
-
-          /* Perform the multiply-accumulate */
-          /* acc0 +=  x[1] * y[srcBLen - 2] */
-          acc0 += x1 * c0;
-          /* acc1 +=  x[2] * y[srcBLen - 2] */
-          acc1 += x2 * c0;
-          /* acc2 +=  x[3] * y[srcBLen - 2] */
-          acc2 += x3 * c0;
-          /* acc3 +=  x[4] * y[srcBLen - 2] */
-          acc3 += x0 * c0;
-
-          /* Read y[srcBLen - 3] sample */
-          c0 = *(py--);
-
-          /* Read x[5] sample */
-          x1 = *(px++);
-
-          /* Perform the multiply-accumulates */
-          /* acc0 +=  x[2] * y[srcBLen - 3] */
-          acc0 += x2 * c0;
-          /* acc1 +=  x[3] * y[srcBLen - 2] */
-          acc1 += x3 * c0;
-          /* acc2 +=  x[4] * y[srcBLen - 2] */
-          acc2 += x0 * c0;
-          /* acc3 +=  x[5] * y[srcBLen - 2] */
-          acc3 += x1 * c0;
-
-          /* Read y[srcBLen - 4] sample */
-          c0 = *(py--);
-
-          /* Read x[6] sample */
-          x2 = *(px++);
-
-          /* Perform the multiply-accumulates */
-          /* acc0 +=  x[3] * y[srcBLen - 4] */
-          acc0 += x3 * c0;
-          /* acc1 +=  x[4] * y[srcBLen - 4] */
-          acc1 += x0 * c0;
-          /* acc2 +=  x[5] * y[srcBLen - 4] */
-          acc2 += x1 * c0;
-          /* acc3 +=  x[6] * y[srcBLen - 4] */
-          acc3 += x2 * c0;
-
-
-        } while(--k);
-
-        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
-         ** No loop unrolling is used. */
-        k = srcBLen % 0x4u;
-
-        while(k > 0u)
-        {
-          /* Read y[srcBLen - 5] sample */
-          c0 = *(py--);
-
-          /* Read x[7] sample */
-          x3 = *(px++);
-
-          /* Perform the multiply-accumulates */
-          /* acc0 +=  x[4] * y[srcBLen - 5] */
-          acc0 += x0 * c0;
-          /* acc1 +=  x[5] * y[srcBLen - 5] */
-          acc1 += x1 * c0;
-          /* acc2 +=  x[6] * y[srcBLen - 5] */
-          acc2 += x2 * c0;
-          /* acc3 +=  x[7] * y[srcBLen - 5] */
-          acc3 += x3 * c0;
-
-          /* Reuse the present samples for the next MAC */
-          x0 = x1;
-          x1 = x2;
-          x2 = x3;
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = acc0;
-        *pOut++ = acc1;
-        *pOut++ = acc2;
-        *pOut++ = acc3;
-
-        /* Increment the pointer pIn1 index, count by 1 */
-        count += 4u;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-
-      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.    
-       ** No loop unrolling is used. */
-      blkCnt = (uint32_t) blockSize2 % 0x4u;
-
-      while(blkCnt > 0u)
-      {
-        /* Accumulator is made zero for every iteration */
-        sum = 0.0f;
-
-        /* Apply loop unrolling and compute 4 MACs simultaneously. */
-        k = srcBLen >> 2u;
-
-        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulates */
-          sum += *px++ * *py--;
-          sum += *px++ * *py--;
-          sum += *px++ * *py--;
-          sum += *px++ * *py--;
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
-         ** No loop unrolling is used. */
-        k = srcBLen % 0x4u;
-
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulate */
-          sum += *px++ * *py--;
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = sum;
-
-        /* Increment the MAC count */
-        count++;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-    }
-    else
-    {
-      /* If the srcBLen is not a multiple of 4,    
-       * the blockSize2 loop cannot be unrolled by 4 */
-      blkCnt = (uint32_t) blockSize2;
-
-      while(blkCnt > 0u)
-      {
-        /* Accumulator is made zero for every iteration */
-        sum = 0.0f;
-
-        /* srcBLen number of MACS should be performed */
-        k = srcBLen;
-
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulate */
-          sum += *px++ * *py--;
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = sum;
-
-        /* Increment the MAC count */
-        count++;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-    }
-
-
-    /* --------------------------    
-     * Initializations of stage3    
-     * -------------------------*/
-
-    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]    
-     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]    
-     * ....    
-     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]    
-     * sum +=  x[srcALen-1] * y[srcBLen-1]    
-     */
-
-    /* In this stage the MAC operations are decreased by 1 for every iteration.    
-       The count variable holds the number of MAC operations performed */
-    count = srcBLen - 1u;
-
-    /* Working pointer of inputA */
-    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-    px = pSrc1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + (srcBLen - 1u);
-    py = pSrc2;
-
-    while(blockSize3 > 0)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0.0f;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
-        sum += *px++ * *py--;
-
-        /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
-        sum += *px++ * *py--;
-
-        /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
-        sum += *px++ * *py--;
-
-        /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
-        sum += *px++ * *py--;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the count is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = count % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
-        sum += *px++ * *py--;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = sum;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = ++pSrc1;
-      py = pSrc2;
-
-      /* Decrement the MAC count */
-      count--;
-
-      /* Decrement the loop counter */
-      blockSize3--;
-
-    }
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
-  float32_t *pIn2 = pSrcB;                       /* inputB pointer */
-  float32_t sum;                                 /* Accumulator */
-  uint32_t i, j;                                 /* loop counters */
-  arm_status status;                             /* status of Partial convolution */
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-    /* Loop to calculate convolution for output length number of values */
-    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
-    {
-      /* Initialize sum with zero to carry on MAC operations */
-      sum = 0.0f;
-
-      /* Loop to perform MAC operations according to convolution equation */
-      for (j = 0u; j <= i; j++)
-      {
-        /* Check the array limitations for inputs */
-        if((((i - j) < srcBLen) && (j < srcALen)))
-        {
-          /* z[i] += x[i-j] * y[j] */
-          sum += pIn1[j] * pIn2[i - j];
-        }
-      }
-      /* Store the output in the destination buffer */
-      pDst[i] = sum;
-    }
-    /* set status as ARM_SUCCESS as there are no argument errors */
-    status = ARM_MATH_SUCCESS;
-  }
-  return (status);
-
-#endif /*   #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
- * @} end of PartialConv group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c
deleted file mode 100644
index 1c04d2217a..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c
+++ /dev/null
@@ -1,763 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_conv_partial_fast_opt_q15.c    
-*    
-* Description:	Fast Q15 Partial convolution.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-* 
-* Version 1.0.11 2011/10/18  
-*    Bug Fix in conv, correlation, partial convolution.  
-* 
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup PartialConv    
- * @{    
- */
-
-/**    
- * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.    
- * @param[in]       *pSrcA points to the first input sequence.    
- * @param[in]       srcALen length of the first input sequence.    
- * @param[in]       *pSrcB points to the second input sequence.    
- * @param[in]       srcBLen length of the second input sequence.    
- * @param[out]      *pDst points to the location where the output result is written.    
- * @param[in]       firstIndex is the first output sample to start with.    
- * @param[in]       numPoints is the number of output points to be computed.    
- * @param[in]       *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
- * @param[in]       *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).   
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].    
- *    
- * See arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.    
- *    
- * \par Restrictions    
- *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
- *	In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit    
- *     
- */
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-arm_status arm_conv_partial_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2)
-{
-
-  q15_t *pOut = pDst;                            /* output pointer */
-  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */
-  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */
-  q31_t acc0, acc1, acc2, acc3;                  /* Accumulator */
-  q31_t x1, x2, x3;                              /* Temporary variables to hold state and coefficient values */
-  q31_t y1, y2;                                  /* State variables */
-  q15_t *pIn1;                                   /* inputA pointer */
-  q15_t *pIn2;                                   /* inputB pointer */
-  q15_t *px;                                     /* Intermediate inputA pointer  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  uint32_t j, k, blkCnt;                         /* loop counter */
-  arm_status status;
-
-  uint32_t tapCnt;                               /* loop count */
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_MATH_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-
-    /* The algorithm implementation is based on the lengths of the inputs. */
-    /* srcB is always made to slide across srcA. */
-    /* So srcBLen is always considered as shorter or equal to srcALen */
-    if(srcALen >= srcBLen)
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcA;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcB;
-    }
-    else
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcB;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcA;
-
-      /* srcBLen is always considered as shorter or equal to srcALen */
-      j = srcBLen;
-      srcBLen = srcALen;
-      srcALen = j;
-    }
-
-    /* Temporary pointer for scratch2 */
-    py = pScratch2;
-
-    /* pointer to take end of scratch2 buffer */
-    pScr2 = pScratch2 + srcBLen - 1;
-
-    /* points to smaller length sequence */
-    px = pIn2;
-
-    /* Apply loop unrolling and do 4 Copies simultaneously. */
-    k = srcBLen >> 2u;
-
-    /* First part of the processing with loop unrolling copies 4 data points at a time.       
-     ** a second loop below copies for the remaining 1 to 3 samples. */
-
-    /* Copy smaller length input sequence in reverse order into second scratch buffer */
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner */
-      *pScr2-- = *px++;
-      *pScr2-- = *px++;
-      *pScr2-- = *px++;
-      *pScr2-- = *px++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, copy remaining samples here.       
-     ** No loop unrolling is used. */
-    k = srcBLen % 0x4u;
-
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner for remaining samples */
-      *pScr2-- = *px++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Initialze temporary scratch pointer */
-    pScr1 = pScratch1;
-
-    /* Assuming scratch1 buffer is aligned by 32-bit */
-    /* Fill (srcBLen - 1u) zeros in scratch buffer */
-    arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-    /* Update temporary scratch pointer */
-    pScr1 += (srcBLen - 1u);
-
-    /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
-
-    /* Copy (srcALen) samples in scratch buffer */
-    arm_copy_q15(pIn1, pScr1, srcALen);
-
-    /* Update pointers */
-    pScr1 += srcALen;
-
-    /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
-    arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-    /* Update pointer */
-    pScr1 += (srcBLen - 1u);
-
-    /* Initialization of pIn2 pointer */
-    pIn2 = py;
-
-    pScratch1 += firstIndex;
-
-    pOut = pDst + firstIndex;
-
-    /* First part of the processing with loop unrolling process 4 data points at a time.       
-     ** a second loop below process for the remaining 1 to 3 samples. */
-
-    /* Actual convolution process starts here */
-    blkCnt = (numPoints) >> 2;
-
-    while(blkCnt > 0)
-    {
-      /* Initialze temporary scratch pointer as scratch1 */
-      pScr1 = pScratch1;
-
-      /* Clear Accumlators */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-      /* Read two samples from scratch1 buffer */
-      x1 = *__SIMD32(pScr1)++;
-
-      /* Read next two samples from scratch1 buffer */
-      x2 = *__SIMD32(pScr1)++;
-
-      tapCnt = (srcBLen) >> 2u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read four samples from smaller buffer */
-        y1 = _SIMD32_OFFSET(pIn2);
-        y2 = _SIMD32_OFFSET(pIn2 + 2u);
-
-        /* multiply and accumlate */
-        acc0 = __SMLAD(x1, y1, acc0);
-        acc2 = __SMLAD(x2, y1, acc2);
-
-        /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
-        x3 = __PKHBT(x2, x1, 0);
-#else
-        x3 = __PKHBT(x1, x2, 0);
-#endif
-
-        /* multiply and accumlate */
-        acc1 = __SMLADX(x3, y1, acc1);
-
-        /* Read next two samples from scratch1 buffer */
-        x1 = _SIMD32_OFFSET(pScr1);
-
-        /* multiply and accumlate */
-        acc0 = __SMLAD(x2, y2, acc0);
-
-        acc2 = __SMLAD(x1, y2, acc2);
-
-        /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
-        x3 = __PKHBT(x1, x2, 0);
-#else
-        x3 = __PKHBT(x2, x1, 0);
-#endif
-
-        acc3 = __SMLADX(x3, y1, acc3);
-        acc1 = __SMLADX(x3, y2, acc1);
-
-        x2 = _SIMD32_OFFSET(pScr1 + 2u);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-        x3 = __PKHBT(x2, x1, 0);
-#else
-        x3 = __PKHBT(x1, x2, 0);
-#endif
-
-        acc3 = __SMLADX(x3, y2, acc3);
-
-        /* update scratch pointers */
-        pIn2 += 4u;
-        pScr1 += 4u;
-
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* Update scratch pointer for remaining samples of smaller length sequence */
-      pScr1 -= 4u;
-
-      /* apply same above for remaining samples of smaller length sequence */
-      tapCnt = (srcBLen) & 3u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* accumlate the results */
-        acc0 += (*pScr1++ * *pIn2);
-        acc1 += (*pScr1++ * *pIn2);
-        acc2 += (*pScr1++ * *pIn2);
-        acc3 += (*pScr1++ * *pIn2++);
-
-        pScr1 -= 3u;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      blkCnt--;
-
-
-      /* Store the results in the accumulators in the destination buffer. */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
-
-#else
-
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-      /* Initialization of inputB pointer */
-      pIn2 = py;
-
-      pScratch1 += 4u;
-
-    }
-
-
-    blkCnt = numPoints & 0x3;
-
-    /* Calculate convolution for remaining samples of Bigger length sequence */
-    while(blkCnt > 0)
-    {
-      /* Initialze temporary scratch pointer as scratch1 */
-      pScr1 = pScratch1;
-
-      /* Clear Accumlators */
-      acc0 = 0;
-
-      tapCnt = (srcBLen) >> 1u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read next two samples from scratch1 buffer */
-        x1 = *__SIMD32(pScr1)++;
-
-        /* Read two samples from smaller buffer */
-        y1 = *__SIMD32(pIn2)++;
-
-        acc0 = __SMLAD(x1, y1, acc0);
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      tapCnt = (srcBLen) & 1u;
-
-      /* apply same above for remaining samples of smaller length sequence */
-      while(tapCnt > 0u)
-      {
-
-        /* accumlate the results */
-        acc0 += (*pScr1++ * *pIn2++);
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      blkCnt--;
-
-      /* The result is in 2.30 format.  Convert to 1.15 with saturation.       
-       ** Then store the output in the destination buffer. */
-      *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-
-      /* Initialization of inputB pointer */
-      pIn2 = py;
-
-      pScratch1 += 1u;
-
-    }
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-  /* Return to application */
-  return (status);
-}
-
-#else
-
-arm_status arm_conv_partial_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2)
-{
-
-  q15_t *pOut = pDst;                            /* output pointer */
-  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */
-  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */
-  q31_t acc0, acc1, acc2, acc3;                  /* Accumulator */
-  q15_t *pIn1;                                   /* inputA pointer */
-  q15_t *pIn2;                                   /* inputB pointer */
-  q15_t *px;                                     /* Intermediate inputA pointer  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  uint32_t j, k, blkCnt;                         /* loop counter */
-  arm_status status;                             /* Status variable */
-  uint32_t tapCnt;                               /* loop count */
-  q15_t x10, x11, x20, x21;                      /* Temporary variables to hold srcA buffer */
-  q15_t y10, y11;                                /* Temporary variables to hold srcB buffer */
-
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_MATH_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-
-    /* The algorithm implementation is based on the lengths of the inputs. */
-    /* srcB is always made to slide across srcA. */
-    /* So srcBLen is always considered as shorter or equal to srcALen */
-    if(srcALen >= srcBLen)
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcA;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcB;
-    }
-    else
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcB;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcA;
-
-      /* srcBLen is always considered as shorter or equal to srcALen */
-      j = srcBLen;
-      srcBLen = srcALen;
-      srcALen = j;
-    }
-
-    /* Temporary pointer for scratch2 */
-    py = pScratch2;
-
-    /* pointer to take end of scratch2 buffer */
-    pScr2 = pScratch2 + srcBLen - 1;
-
-    /* points to smaller length sequence */
-    px = pIn2;
-
-    /* Apply loop unrolling and do 4 Copies simultaneously. */
-    k = srcBLen >> 2u;
-
-    /* First part of the processing with loop unrolling copies 4 data points at a time.       
-     ** a second loop below copies for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner */
-      *pScr2-- = *px++;
-      *pScr2-- = *px++;
-      *pScr2-- = *px++;
-      *pScr2-- = *px++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, copy remaining samples here.       
-     ** No loop unrolling is used. */
-    k = srcBLen % 0x4u;
-
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner for remaining samples */
-      *pScr2-- = *px++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Initialze temporary scratch pointer */
-    pScr1 = pScratch1;
-
-    /* Fill (srcBLen - 1u) zeros in scratch buffer */
-    arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-    /* Update temporary scratch pointer */
-    pScr1 += (srcBLen - 1u);
-
-    /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
-
-
-    /* Apply loop unrolling and do 4 Copies simultaneously. */
-    k = srcALen >> 2u;
-
-    /* First part of the processing with loop unrolling copies 4 data points at a time.       
-     ** a second loop below copies for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner */
-      *pScr1++ = *pIn1++;
-      *pScr1++ = *pIn1++;
-      *pScr1++ = *pIn1++;
-      *pScr1++ = *pIn1++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, copy remaining samples here.       
-     ** No loop unrolling is used. */
-    k = srcALen % 0x4u;
-
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner for remaining samples */
-      *pScr1++ = *pIn1++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-
-    /* Apply loop unrolling and do 4 Copies simultaneously. */
-    k = (srcBLen - 1u) >> 2u;
-
-    /* First part of the processing with loop unrolling copies 4 data points at a time.       
-     ** a second loop below copies for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner */
-      *pScr1++ = 0;
-      *pScr1++ = 0;
-      *pScr1++ = 0;
-      *pScr1++ = 0;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, copy remaining samples here.       
-     ** No loop unrolling is used. */
-    k = (srcBLen - 1u) % 0x4u;
-
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner for remaining samples */
-      *pScr1++ = 0;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-
-    /* Initialization of pIn2 pointer */
-    pIn2 = py;
-
-    pScratch1 += firstIndex;
-
-    pOut = pDst + firstIndex;
-
-    /* Actual convolution process starts here */
-    blkCnt = (numPoints) >> 2;
-
-    while(blkCnt > 0)
-    {
-      /* Initialze temporary scratch pointer as scratch1 */
-      pScr1 = pScratch1;
-
-      /* Clear Accumlators */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-      /* Read two samples from scratch1 buffer */
-      x10 = *pScr1++;
-      x11 = *pScr1++;
-
-      /* Read next two samples from scratch1 buffer */
-      x20 = *pScr1++;
-      x21 = *pScr1++;
-
-      tapCnt = (srcBLen) >> 2u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read two samples from smaller buffer */
-        y10 = *pIn2;
-        y11 = *(pIn2 + 1u);
-
-        /* multiply and accumlate */
-        acc0 += (q31_t) x10 *y10;
-        acc0 += (q31_t) x11 *y11;
-        acc2 += (q31_t) x20 *y10;
-        acc2 += (q31_t) x21 *y11;
-
-        /* multiply and accumlate */
-        acc1 += (q31_t) x11 *y10;
-        acc1 += (q31_t) x20 *y11;
-
-        /* Read next two samples from scratch1 buffer */
-        x10 = *pScr1;
-        x11 = *(pScr1 + 1u);
-
-        /* multiply and accumlate */
-        acc3 += (q31_t) x21 *y10;
-        acc3 += (q31_t) x10 *y11;
-
-        /* Read next two samples from scratch2 buffer */
-        y10 = *(pIn2 + 2u);
-        y11 = *(pIn2 + 3u);
-
-        /* multiply and accumlate */
-        acc0 += (q31_t) x20 *y10;
-        acc0 += (q31_t) x21 *y11;
-        acc2 += (q31_t) x10 *y10;
-        acc2 += (q31_t) x11 *y11;
-        acc1 += (q31_t) x21 *y10;
-        acc1 += (q31_t) x10 *y11;
-
-        /* Read next two samples from scratch1 buffer */
-        x20 = *(pScr1 + 2);
-        x21 = *(pScr1 + 3);
-
-        /* multiply and accumlate */
-        acc3 += (q31_t) x11 *y10;
-        acc3 += (q31_t) x20 *y11;
-
-        /* update scratch pointers */
-        pIn2 += 4u;
-        pScr1 += 4u;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* Update scratch pointer for remaining samples of smaller length sequence */
-      pScr1 -= 4u;
-
-      /* apply same above for remaining samples of smaller length sequence */
-      tapCnt = (srcBLen) & 3u;
-
-      while(tapCnt > 0u)
-      {
-        /* accumlate the results */
-        acc0 += (*pScr1++ * *pIn2);
-        acc1 += (*pScr1++ * *pIn2);
-        acc2 += (*pScr1++ * *pIn2);
-        acc3 += (*pScr1++ * *pIn2++);
-
-        pScr1 -= 3u;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      blkCnt--;
-
-
-      /* Store the results in the accumulators in the destination buffer. */
-      *pOut++ = __SSAT((acc0 >> 15), 16);
-      *pOut++ = __SSAT((acc1 >> 15), 16);
-      *pOut++ = __SSAT((acc2 >> 15), 16);
-      *pOut++ = __SSAT((acc3 >> 15), 16);
-
-      /* Initialization of inputB pointer */
-      pIn2 = py;
-
-      pScratch1 += 4u;
-
-    }
-
-
-    blkCnt = numPoints & 0x3;
-
-    /* Calculate convolution for remaining samples of Bigger length sequence */
-    while(blkCnt > 0)
-    {
-      /* Initialze temporary scratch pointer as scratch1 */
-      pScr1 = pScratch1;
-
-      /* Clear Accumlators */
-      acc0 = 0;
-
-      tapCnt = (srcBLen) >> 1u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read next two samples from scratch1 buffer */
-        x10 = *pScr1++;
-        x11 = *pScr1++;
-
-        /* Read two samples from smaller buffer */
-        y10 = *pIn2++;
-        y11 = *pIn2++;
-
-        /* multiply and accumlate */
-        acc0 += (q31_t) x10 *y10;
-        acc0 += (q31_t) x11 *y11;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      tapCnt = (srcBLen) & 1u;
-
-      /* apply same above for remaining samples of smaller length sequence */
-      while(tapCnt > 0u)
-      {
-
-        /* accumlate the results */
-        acc0 += (*pScr1++ * *pIn2++);
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      blkCnt--;
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-
-      /* Initialization of inputB pointer */
-      pIn2 = py;
-
-      pScratch1 += 1u;
-
-    }
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-/**    
- * @} end of PartialConv group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q15.c
deleted file mode 100644
index 5d6eb6f49f..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q15.c
+++ /dev/null
@@ -1,1473 +0,0 @@
-/* ----------------------------------------------------------------------   
-* Copyright (C) 2010 ARM Limited. All rights reserved.   
-*   
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*   
-* Project: 	    CMSIS DSP Library   
-* Title:		arm_conv_partial_fast_q15.c   
-*   
-* Description:	Fast Q15 Partial convolution.   
-*   
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-* 
-* Version 1.0.11 2011/10/18 
-*    Bug Fix in conv, correlation, partial convolution. 
-*
-* Version 1.0.10 2011/7/15 
-*    Big Endian support added and Merged M0 and M3/M4 Source code.  
-*   
-* Version 1.0.3 2010/11/29  
-*    Re-organized the CMSIS folders and updated documentation.   
-*    
-* Version 1.0.2 2010/11/11   
-*    Documentation updated.    
-*   
-* Version 1.0.1 2010/10/05    
-*    Production release and review comments incorporated.   
-*   
-* Version 1.0.0 2010/09/20    
-*    Production release and review comments incorporated.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**   
- * @ingroup groupFilters   
- */
-
-/**   
- * @addtogroup PartialConv   
- * @{   
- */
-
-/**   
- * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.   
- * @param[in]       *pSrcA points to the first input sequence.   
- * @param[in]       srcALen length of the first input sequence.   
- * @param[in]       *pSrcB points to the second input sequence.   
- * @param[in]       srcBLen length of the second input sequence.   
- * @param[out]      *pDst points to the location where the output result is written.   
- * @param[in]       firstIndex is the first output sample to start with.   
- * @param[in]       numPoints is the number of output points to be computed.   
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
- *   
- * See arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.   
- */
-
-
-arm_status arm_conv_partial_fast_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints)
-{
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-  q15_t *pIn1;                                   /* inputA pointer               */
-  q15_t *pIn2;                                   /* inputB pointer               */
-  q15_t *pOut = pDst;                            /* output pointer               */
-  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator                  */
-  q15_t *px;                                     /* Intermediate inputA pointer  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
-  q31_t x0, x1, x2, x3, c0;
-  uint32_t j, k, count, check, blkCnt;
-  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters                 */
-  arm_status status;                             /* status of Partial convolution */
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_MATH_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-
-    /* The algorithm implementation is based on the lengths of the inputs. */
-    /* srcB is always made to slide across srcA. */
-    /* So srcBLen is always considered as shorter or equal to srcALen */
-    if(srcALen >=srcBLen)
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcA;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcB;
-    }
-    else
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcB;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcA;
-
-      /* srcBLen is always considered as shorter or equal to srcALen */
-      j = srcBLen;
-      srcBLen = srcALen;
-      srcALen = j;
-    }
-
-    /* Conditions to check which loopCounter holds   
-     * the first and last indices of the output samples to be calculated. */
-    check = firstIndex + numPoints;
-    blockSize3 = ((int32_t) check - (int32_t) srcALen);
-    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
-    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
-    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
-                                     (int32_t) numPoints) : 0;
-    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
-                                    (int32_t) firstIndex);
-    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
-
-    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
-    /* The function is internally   
-     * divided into three stages according to the number of multiplications that has to be   
-     * taken place between inputA samples and inputB samples. In the first stage of the   
-     * algorithm, the multiplications increase by one for every iteration.   
-     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
-     * In the third stage of the algorithm, the multiplications decrease by one   
-     * for every iteration. */
-
-    /* Set the output pointer to point to the firstIndex   
-     * of the output sample to be calculated. */
-    pOut = pDst + firstIndex;
-
-    /* --------------------------   
-     * Initializations of stage1   
-     * -------------------------*/
-
-    /* sum = x[0] * y[0]   
-     * sum = x[0] * y[1] + x[1] * y[0]   
-     * ....   
-     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
-     */
-
-    /* In this stage the MAC operations are increased by 1 for every iteration.   
-       The count variable holds the number of MAC operations performed.   
-       Since the partial convolution starts from firstIndex   
-       Number of Macs to be performed is firstIndex + 1 */
-    count = 1u + firstIndex;
-
-    /* Working pointer of inputA */
-    px = pIn1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + firstIndex;
-    py = pSrc2;
-
-    /* ------------------------   
-     * Stage1 process   
-     * ----------------------*/
-
-    /* For loop unrolling by 4, this stage is divided into two. */
-    /* First part of this stage computes the MAC operations less than 4 */
-    /* Second part of this stage computes the MAC operations greater than or equal to 4 */
-
-    /* The first part of the stage starts here */
-    while((count < 4u) && (blockSize1 > 0))
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Loop over number of MAC operations between   
-       * inputA samples and inputB samples */
-      k = count;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum = __SMLAD(*px++, *py--, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (sum >> 15);
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      py = ++pSrc2;
-      px = pIn1;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Decrement the loop counter */
-      blockSize1--;
-    }
-
-    /* The second part of the stage starts here */
-    /* The internal loop, over count, is unrolled by 4 */
-    /* To, read the last two inputB samples using SIMD:   
-     * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
-    py = py - 1;
-
-    while(blockSize1 > 0)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
-        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-        /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
-        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* For the next MAC operations, the pointer py is used without SIMD   
-       * So, py is incremented by 1 */
-      py = py + 1u;
-
-      /* If the count is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = count % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum = __SMLAD(*px++, *py--, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (sum >> 15);
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      py = ++pSrc2 - 1u;
-      px = pIn1;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Decrement the loop counter */
-      blockSize1--;
-    }
-
-    /* --------------------------   
-     * Initializations of stage2   
-     * ------------------------*/
-
-    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
-     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
-     * ....   
-     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
-     */
-
-    /* Working pointer of inputA */
-    px = pIn1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + (srcBLen - 1u);
-    py = pSrc2;
-
-    /* count is the index by which the pointer pIn1 to be incremented */
-    count = 0u;
-
-
-    /* --------------------   
-     * Stage2 process   
-     * -------------------*/
-
-    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
-     * So, to loop unroll over blockSize2,   
-     * srcBLen should be greater than or equal to 4 */
-    if(srcBLen >= 4u)
-    {
-      /* Loop unroll over blockSize2, by 4 */
-      blkCnt = ((uint32_t) blockSize2 >> 2u);
-
-      while(blkCnt > 0u)
-      {
-      py = py - 1u;
-
-        /* Set all accumulators to zero */
-        acc0 = 0;
-        acc1 = 0;
-        acc2 = 0;
-        acc3 = 0;
-
-
-        /* read x[0], x[1] samples */
-      x0 = *__SIMD32(px);
-        /* read x[1], x[2] samples */
-      x1 = _SIMD32_OFFSET(px+1);
-	  px+= 2u;
-
-
-        /* Apply loop unrolling and compute 4 MACs simultaneously. */
-        k = srcBLen >> 2u;
-
-        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-        do
-        {
-          /* Read the last two inputB samples using SIMD:   
-           * y[srcBLen - 1] and y[srcBLen - 2] */
-        c0 = *__SIMD32(py)--;
-
-          /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
-          acc0 = __SMLADX(x0, c0, acc0);
-
-          /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
-          acc1 = __SMLADX(x1, c0, acc1);
-
-          /* Read x[2], x[3] */
-        x2 = *__SIMD32(px);
-
-          /* Read x[3], x[4] */
-        x3 = _SIMD32_OFFSET(px+1);
-
-          /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
-          acc2 = __SMLADX(x2, c0, acc2);
-
-          /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
-          acc3 = __SMLADX(x3, c0, acc3);
-
-          /* Read y[srcBLen - 3] and y[srcBLen - 4] */
-        c0 = *__SIMD32(py)--;
-
-          /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
-          acc0 = __SMLADX(x2, c0, acc0);
-
-          /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
-          acc1 = __SMLADX(x3, c0, acc1);
-
-          /* Read x[4], x[5] */
-        x0 = _SIMD32_OFFSET(px+2);
-
-          /* Read x[5], x[6] */
-        x1 = _SIMD32_OFFSET(px+3);
-		px += 4u;
-
-          /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
-          acc2 = __SMLADX(x0, c0, acc2);
-
-          /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
-          acc3 = __SMLADX(x1, c0, acc3);
-
-        } while(--k);
-
-        /* For the next MAC operations, SIMD is not used   
-         * So, the 16 bit pointer if inputB, py is updated */
-
-        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-         ** No loop unrolling is used. */
-        k = srcBLen % 0x4u;
-
-        if(k == 1u)
-        {
-          /* Read y[srcBLen - 5] */
-        c0 = *(py+1);
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-
-#else
-
-        c0 = c0 & 0x0000FFFF;
-
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-
-          /* Read x[7] */
-        x3 = *__SIMD32(px);
-		px++;
-
-          /* Perform the multiply-accumulates */
-          acc0 = __SMLAD(x0, c0, acc0);
-          acc1 = __SMLAD(x1, c0, acc1);
-          acc2 = __SMLADX(x1, c0, acc2);
-          acc3 = __SMLADX(x3, c0, acc3);
-        }
-
-        if(k == 2u)
-        {
-          /* Read y[srcBLen - 5], y[srcBLen - 6] */
-        c0 = _SIMD32_OFFSET(py);
-
-          /* Read x[7], x[8] */
-        x3 = *__SIMD32(px);
-
-        /* Read x[9] */
-        x2 = _SIMD32_OFFSET(px+1);
-		px += 2u;
-
-          /* Perform the multiply-accumulates */
-          acc0 = __SMLADX(x0, c0, acc0);
-          acc1 = __SMLADX(x1, c0, acc1);
-          acc2 = __SMLADX(x3, c0, acc2);
-          acc3 = __SMLADX(x2, c0, acc3);
-        }
-
-        if(k == 3u)
-        {
-          /* Read y[srcBLen - 5], y[srcBLen - 6] */
-        c0 = _SIMD32_OFFSET(py);
-
-          /* Read x[7], x[8] */
-        x3 = *__SIMD32(px);
-
-          /* Read x[9] */
-        x2 = _SIMD32_OFFSET(px+1);
-
-          /* Perform the multiply-accumulates */
-          acc0 = __SMLADX(x0, c0, acc0);
-          acc1 = __SMLADX(x1, c0, acc1);
-          acc2 = __SMLADX(x3, c0, acc2);
-          acc3 = __SMLADX(x2, c0, acc3);
-
-		c0 = *(py-1);
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-#else
-
-        c0 = c0 & 0x0000FFFF;
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-
-          /* Read x[10] */
-        x3 =  _SIMD32_OFFSET(px+2);
-		px += 3u;
-
-          /* Perform the multiply-accumulates */
-          acc0 = __SMLADX(x1, c0, acc0);
-          acc1 = __SMLAD(x2, c0, acc1);
-          acc2 = __SMLADX(x2, c0, acc2);
-          acc3 = __SMLADX(x3, c0, acc3);
-        }
-
-        /* Store the results in the accumulators in the destination buffer. */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        *__SIMD32(pOut)++ = __PKHBT(acc0 >> 15, acc1 >> 15, 16);
-        *__SIMD32(pOut)++ = __PKHBT(acc2 >> 15, acc3 >> 15, 16);
-
-#else
-
-        *__SIMD32(pOut)++ = __PKHBT(acc1 >> 15, acc0 >> 15, 16);
-        *__SIMD32(pOut)++ = __PKHBT(acc3 >> 15, acc2 >> 15, 16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-        /* Increment the pointer pIn1 index, count by 4 */
-        count += 4u;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-
-      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
-       ** No loop unrolling is used. */
-      blkCnt = (uint32_t) blockSize2 % 0x4u;
-
-      while(blkCnt > 0u)
-      {
-        /* Accumulator is made zero for every iteration */
-        sum = 0;
-
-        /* Apply loop unrolling and compute 4 MACs simultaneously. */
-        k = srcBLen >> 2u;
-
-        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulates */
-          sum += ((q31_t) * px++ * *py--);
-          sum += ((q31_t) * px++ * *py--);
-          sum += ((q31_t) * px++ * *py--);
-          sum += ((q31_t) * px++ * *py--);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-         ** No loop unrolling is used. */
-        k = srcBLen % 0x4u;
-
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulates */
-          sum += ((q31_t) * px++ * *py--);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = (q15_t) (sum >> 15);
-
-        /* Increment the pointer pIn1 index, count by 1 */
-        count++;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-    }
-    else
-    {
-      /* If the srcBLen is not a multiple of 4,   
-       * the blockSize2 loop cannot be unrolled by 4 */
-      blkCnt = (uint32_t) blockSize2;
-
-      while(blkCnt > 0u)
-      {
-        /* Accumulator is made zero for every iteration */
-        sum = 0;
-
-        /* srcBLen number of MACS should be performed */
-        k = srcBLen;
-
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulate */
-          sum += ((q31_t) * px++ * *py--);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = (q15_t) (sum >> 15);
-
-        /* Increment the MAC count */
-        count++;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-    }
-
-
-    /* --------------------------   
-     * Initializations of stage3   
-     * -------------------------*/
-
-    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
-     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
-     * ....   
-     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
-     * sum +=  x[srcALen-1] * y[srcBLen-1]   
-     */
-
-    /* In this stage the MAC operations are decreased by 1 for every iteration.   
-       The count variable holds the number of MAC operations performed */
-    count = srcBLen - 1u;
-
-    /* Working pointer of inputA */
-    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-    px = pSrc1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + (srcBLen - 1u);
-    pIn2 = pSrc2 - 1u;
-    py = pIn2;
-
-    /* -------------------   
-     * Stage3 process   
-     * ------------------*/
-
-    /* For loop unrolling by 4, this stage is divided into two. */
-    /* First part of this stage computes the MAC operations greater than 4 */
-    /* Second part of this stage computes the MAC operations less than or equal to 4 */
-
-    /* The first part of the stage starts here */
-    j = count >> 2u;
-
-    while((j > 0u) && (blockSize3 > 0))
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   
-         * with y[srcBLen - 1], y[srcBLen - 2] respectively */
-        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-        /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   
-         * with y[srcBLen - 3], y[srcBLen - 4] respectively */
-        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* For the next MAC operations, the pointer py is used without SIMD   
-       * So, py is incremented by 1 */
-      py = py + 1u;
-
-      /* If the count is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = count % 0x4u;
-
-      while(k > 0u)
-      {
-        /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
-        sum = __SMLAD(*px++, *py--, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (sum >> 15);
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = ++pSrc1;
-      py = pIn2;
-
-      /* Decrement the MAC count */
-      count--;
-
-      /* Decrement the loop counter */
-      blockSize3--;
-
-      j--;
-    }
-
-    /* The second part of the stage starts here */
-    /* SIMD is not used for the next MAC operations,   
-     * so pointer py is updated to read only one sample at a time */
-    py = py + 1u;
-
-    while(blockSize3 > 0)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
-        sum = __SMLAD(*px++, *py--, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (sum >> 15);
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = ++pSrc1;
-      py = pSrc2;
-
-      /* Decrement the MAC count */
-      count--;
-
-      /* Decrement the loop counter */
-      blockSize3--;
-    }
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-
-#else
-
-  q15_t *pIn1;                                   /* inputA pointer               */
-  q15_t *pIn2;                                   /* inputB pointer               */
-  q15_t *pOut = pDst;                            /* output pointer               */
-  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator                  */
-  q15_t *px;                                     /* Intermediate inputA pointer  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
-  q31_t x0, x1, x2, x3, c0;
-  uint32_t j, k, count, check, blkCnt;
-  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters                 */
-  arm_status status;                             /* status of Partial convolution */
-  q15_t a, b;
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_MATH_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-
-    /* The algorithm implementation is based on the lengths of the inputs. */
-    /* srcB is always made to slide across srcA. */
-    /* So srcBLen is always considered as shorter or equal to srcALen */
-    if(srcALen >=srcBLen)
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcA;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcB;
-    }
-    else
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcB;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcA;
-
-      /* srcBLen is always considered as shorter or equal to srcALen */
-      j = srcBLen;
-      srcBLen = srcALen;
-      srcALen = j;
-    }
-
-    /* Conditions to check which loopCounter holds   
-     * the first and last indices of the output samples to be calculated. */
-    check = firstIndex + numPoints;
-    blockSize3 = ((int32_t) check - (int32_t) srcALen);
-    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
-    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
-    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
-                                     (int32_t) numPoints) : 0;
-    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
-                                    (int32_t) firstIndex);
-    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
-
-    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
-    /* The function is internally   
-     * divided into three stages according to the number of multiplications that has to be   
-     * taken place between inputA samples and inputB samples. In the first stage of the   
-     * algorithm, the multiplications increase by one for every iteration.   
-     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
-     * In the third stage of the algorithm, the multiplications decrease by one   
-     * for every iteration. */
-
-    /* Set the output pointer to point to the firstIndex   
-     * of the output sample to be calculated. */
-    pOut = pDst + firstIndex;
-
-    /* --------------------------   
-     * Initializations of stage1   
-     * -------------------------*/
-
-    /* sum = x[0] * y[0]   
-     * sum = x[0] * y[1] + x[1] * y[0]   
-     * ....   
-     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
-     */
-
-    /* In this stage the MAC operations are increased by 1 for every iteration.   
-       The count variable holds the number of MAC operations performed.   
-       Since the partial convolution starts from firstIndex   
-       Number of Macs to be performed is firstIndex + 1 */
-    count = 1u + firstIndex;
-
-    /* Working pointer of inputA */
-    px = pIn1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + firstIndex;
-    py = pSrc2;
-
-    /* ------------------------   
-     * Stage1 process   
-     * ----------------------*/
-
-    /* For loop unrolling by 4, this stage is divided into two. */
-    /* First part of this stage computes the MAC operations less than 4 */
-    /* Second part of this stage computes the MAC operations greater than or equal to 4 */
-
-    /* The first part of the stage starts here */
-  while((count < 4u) && (blockSize1 > 0u))
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Loop over number of MAC operations between   
-       * inputA samples and inputB samples */
-      k = count;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-      sum += ((q31_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (sum >> 15);
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      py = ++pSrc2;
-      px = pIn1;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Decrement the loop counter */
-      blockSize1--;
-    }
-
-    /* The second part of the stage starts here */
-    /* The internal loop, over count, is unrolled by 4 */
-    /* To, read the last two inputB samples using SIMD:   
-     * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
-    py = py - 1;
-
-  while(blockSize1 > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-	py++;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-      /* If the count is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = count % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-      sum += ((q31_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (sum >> 15);
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      py = ++pSrc2 - 1u;
-      px = pIn1;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Decrement the loop counter */
-      blockSize1--;
-    }
-
-    /* --------------------------   
-     * Initializations of stage2   
-     * ------------------------*/
-
-    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
-     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
-     * ....   
-     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
-     */
-
-    /* Working pointer of inputA */
-    px = pIn1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + (srcBLen - 1u);
-    py = pSrc2;
-
-    /* count is the index by which the pointer pIn1 to be incremented */
-    count = 0u;
-
-
-    /* --------------------   
-     * Stage2 process   
-     * -------------------*/
-
-    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
-     * So, to loop unroll over blockSize2,   
-     * srcBLen should be greater than or equal to 4 */
-    if(srcBLen >= 4u)
-    {
-      /* Loop unroll over blockSize2, by 4 */
-      blkCnt = ((uint32_t) blockSize2 >> 2u);
-
-      while(blkCnt > 0u)
-      {
-      py = py - 1u;
-
-        /* Set all accumulators to zero */
-        acc0 = 0;
-        acc1 = 0;
-        acc2 = 0;
-        acc3 = 0;
-
-      /* read x[0], x[1] samples */
-	  a = *px++;
-	  b = *px++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-	  x0 = __PKHBT(a, b, 16);
-	  a = *px;
-	  x1 = __PKHBT(b, a, 16);
-
-#else
-
-	  x0 = __PKHBT(b, a, 16);
-	  a = *px;
-	  x1 = __PKHBT(a, b, 16);
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      do
-      {
-        /* Read the last two inputB samples using SIMD:   
-         * y[srcBLen - 1] and y[srcBLen - 2] */
-		a = *py;
-		b = *(py+1);
-		py -= 2;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-		c0 = __PKHBT(a, b, 16);
-
-#else
-
- 		c0 = __PKHBT(b, a, 16);;
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
-        acc0 = __SMLADX(x0, c0, acc0);
-
-        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
-        acc1 = __SMLADX(x1, c0, acc1);
-
-	  a = *px;
-	  b = *(px + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-	  x2 = __PKHBT(a, b, 16);
-	  a = *(px + 2);
-	  x3 = __PKHBT(b, a, 16);
-
-#else
-
-	  x2 = __PKHBT(b, a, 16);
-	  a = *(px + 2);
-	  x3 = __PKHBT(a, b, 16);
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
-
-        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
-        acc2 = __SMLADX(x2, c0, acc2);
-
-        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
-        acc3 = __SMLADX(x3, c0, acc3);
-
-        /* Read y[srcBLen - 3] and y[srcBLen - 4] */
-		a = *py;
-		b = *(py+1);
-		py -= 2;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-		c0 = __PKHBT(a, b, 16);
-
-#else
-
- 		c0 = __PKHBT(b, a, 16);;
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
-        acc0 = __SMLADX(x2, c0, acc0);
-
-        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
-        acc1 = __SMLADX(x3, c0, acc1);
-
-        /* Read x[4], x[5], x[6] */
-	  a = *(px + 2);
-	  b = *(px + 3);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-	  x0 = __PKHBT(a, b, 16);
-	  a = *(px + 4);
-	  x1 = __PKHBT(b, a, 16);
-
-#else
-
-	  x0 = __PKHBT(b, a, 16);
-	  a = *(px + 4);
-	  x1 = __PKHBT(a, b, 16);
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
-
-		px += 4u;
-
-        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
-        acc2 = __SMLADX(x0, c0, acc2);
-
-        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
-        acc3 = __SMLADX(x1, c0, acc3);
-
-      } while(--k);
-
-      /* For the next MAC operations, SIMD is not used   
-       * So, the 16 bit pointer if inputB, py is updated */
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      if(k == 1u)
-      {
-        /* Read y[srcBLen - 5] */
-        c0 = *(py+1);
-
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-
-#else
-
-        c0 = c0 & 0x0000FFFF;
-
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-
-        /* Read x[7] */
-		a = *px;
-		b = *(px+1);
-		px++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-		x3 = __PKHBT(a, b, 16);
-
-#else
-
- 		x3 = __PKHBT(b, a, 16);;
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLAD(x0, c0, acc0);
-        acc1 = __SMLAD(x1, c0, acc1);
-        acc2 = __SMLADX(x1, c0, acc2);
-        acc3 = __SMLADX(x3, c0, acc3);
-      }
-
-      if(k == 2u)
-      {
-        /* Read y[srcBLen - 5], y[srcBLen - 6] */
-		a = *py;
-		b = *(py+1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-		c0 = __PKHBT(a, b, 16);
-
-#else
-
- 		c0 = __PKHBT(b, a, 16);;
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-        /* Read x[7], x[8], x[9] */
-	  a = *px;
-	  b = *(px + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-	  x3 = __PKHBT(a, b, 16);
-	  a = *(px + 2);
-	  x2 = __PKHBT(b, a, 16);
-
-#else
-
-	  x3 = __PKHBT(b, a, 16);
-	  a = *(px + 2);
-	  x2 = __PKHBT(a, b, 16);
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
-		px += 2u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLADX(x0, c0, acc0);
-        acc1 = __SMLADX(x1, c0, acc1);
-        acc2 = __SMLADX(x3, c0, acc2);
-        acc3 = __SMLADX(x2, c0, acc3);
-      }
-
-      if(k == 3u)
-      {
-        /* Read y[srcBLen - 5], y[srcBLen - 6] */
-		a = *py;
-		b = *(py+1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-		c0 = __PKHBT(a, b, 16);
-
-#else
-
- 		c0 = __PKHBT(b, a, 16);;
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-        /* Read x[7], x[8], x[9] */
-	  a = *px;
-	  b = *(px + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-	  x3 = __PKHBT(a, b, 16);
-	  a = *(px + 2);
-	  x2 = __PKHBT(b, a, 16);
-
-#else
-
-	  x3 = __PKHBT(b, a, 16);
-	  a = *(px + 2);
-	  x2 = __PKHBT(a, b, 16);
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	   */
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLADX(x0, c0, acc0);
-        acc1 = __SMLADX(x1, c0, acc1);
-        acc2 = __SMLADX(x3, c0, acc2);
-        acc3 = __SMLADX(x2, c0, acc3);
-
-        /* Read y[srcBLen - 7] */
-		c0 = *(py-1);
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-#else
-
-        c0 = c0 & 0x0000FFFF;
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-
-        /* Read x[10] */
-		a = *(px+2);
-		b = *(px+3);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-		x3 = __PKHBT(a, b, 16);
-
-#else
-
- 		x3 = __PKHBT(b, a, 16);;
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-		px += 3u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLADX(x1, c0, acc0);
-        acc1 = __SMLAD(x2, c0, acc1);
-        acc2 = __SMLADX(x2, c0, acc2);
-        acc3 = __SMLADX(x3, c0, acc3);
-      }
-
-      /* Store the results in the accumulators in the destination buffer. */
-	  *pOut++ = (q15_t)(acc0 >> 15);
-	  *pOut++ = (q15_t)(acc1 >> 15);
-	  *pOut++ = (q15_t)(acc2 >> 15);
-	  *pOut++ = (q15_t)(acc3 >> 15);
-
-        /* Increment the pointer pIn1 index, count by 4 */
-        count += 4u;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-
-      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
-       ** No loop unrolling is used. */
-      blkCnt = (uint32_t) blockSize2 % 0x4u;
-
-      while(blkCnt > 0u)
-      {
-        /* Accumulator is made zero for every iteration */
-        sum = 0;
-
-        /* Apply loop unrolling and compute 4 MACs simultaneously. */
-        k = srcBLen >> 2u;
-
-        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulates */
-          sum += ((q31_t) * px++ * *py--);
-          sum += ((q31_t) * px++ * *py--);
-          sum += ((q31_t) * px++ * *py--);
-          sum += ((q31_t) * px++ * *py--);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-         ** No loop unrolling is used. */
-        k = srcBLen % 0x4u;
-
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulates */
-          sum += ((q31_t) * px++ * *py--);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = (q15_t) (sum >> 15);
-
-        /* Increment the pointer pIn1 index, count by 1 */
-        count++;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-    }
-    else
-    {
-      /* If the srcBLen is not a multiple of 4,   
-       * the blockSize2 loop cannot be unrolled by 4 */
-      blkCnt = (uint32_t) blockSize2;
-
-      while(blkCnt > 0u)
-      {
-        /* Accumulator is made zero for every iteration */
-        sum = 0;
-
-        /* srcBLen number of MACS should be performed */
-        k = srcBLen;
-
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulate */
-          sum += ((q31_t) * px++ * *py--);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = (q15_t) (sum >> 15);
-
-        /* Increment the MAC count */
-        count++;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-    }
-
-
-    /* --------------------------   
-     * Initializations of stage3   
-     * -------------------------*/
-
-    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
-     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
-     * ....   
-     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
-     * sum +=  x[srcALen-1] * y[srcBLen-1]   
-     */
-
-    /* In this stage the MAC operations are decreased by 1 for every iteration.   
-       The count variable holds the number of MAC operations performed */
-    count = srcBLen - 1u;
-
-    /* Working pointer of inputA */
-    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-    px = pSrc1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + (srcBLen - 1u);
-    pIn2 = pSrc2 - 1u;
-    py = pIn2;
-
-    /* -------------------   
-     * Stage3 process   
-     * ------------------*/
-
-    /* For loop unrolling by 4, this stage is divided into two. */
-    /* First part of this stage computes the MAC operations greater than 4 */
-    /* Second part of this stage computes the MAC operations less than or equal to 4 */
-
-    /* The first part of the stage starts here */
-    j = count >> 2u;
-
-    while((j > 0u) && (blockSize3 > 0))
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-	py++;
-
-    while(k > 0u)
-    {	
-      /* Perform the multiply-accumulates */
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-        sum += ((q31_t) * px++ * *py--);
-      /* Decrement the loop counter */
-      k--;
-    }
-
-
-      /* If the count is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = count % 0x4u;
-
-      while(k > 0u)
-      {
-      /* Perform the multiply-accumulates */
-        sum += ((q31_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (sum >> 15);
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = ++pSrc1;
-      py = pIn2;
-
-      /* Decrement the MAC count */
-      count--;
-
-      /* Decrement the loop counter */
-      blockSize3--;
-
-      j--;
-    }
-
-    /* The second part of the stage starts here */
-    /* SIMD is not used for the next MAC operations,   
-     * so pointer py is updated to read only one sample at a time */
-    py = py + 1u;
-
-  while(blockSize3 > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
-        sum += ((q31_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (sum >> 15);
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = ++pSrc1;
-      py = pSrc2;
-
-      /* Decrement the MAC count */
-      count--;
-
-      /* Decrement the loop counter */
-      blockSize3--;
-    }
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-
-#endif /*     #ifndef UNALIGNED_SUPPORT_DISABLE      */
-}
-
-/**   
- * @} end of PartialConv group   
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q31.c
deleted file mode 100644
index 0e4795f478..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q31.c
+++ /dev/null
@@ -1,599 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_conv_partial_fast_q31.c    
-*    
-* Description:	Fast Q31 Partial convolution.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.11 2011/10/18  
-*    Bug Fix in conv, correlation, partial convolution.  
-* 
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup PartialConv    
- * @{    
- */
-
-/**    
- * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.    
- * @param[in]       *pSrcA points to the first input sequence.    
- * @param[in]       srcALen length of the first input sequence.    
- * @param[in]       *pSrcB points to the second input sequence.    
- * @param[in]       srcBLen length of the second input sequence.    
- * @param[out]      *pDst points to the location where the output result is written.    
- * @param[in]       firstIndex is the first output sample to start with.    
- * @param[in]       numPoints is the number of output points to be computed.    
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].    
- *    
- * \par    
- * See arm_conv_partial_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.    
- */
-
-arm_status arm_conv_partial_fast_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints)
-{
-  q31_t *pIn1;                                   /* inputA pointer               */
-  q31_t *pIn2;                                   /* inputB pointer               */
-  q31_t *pOut = pDst;                            /* output pointer               */
-  q31_t *px;                                     /* Intermediate inputA pointer  */
-  q31_t *py;                                     /* Intermediate inputB pointer  */
-  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
-  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
-  q31_t x0, x1, x2, x3, c0;
-  uint32_t j, k, count, check, blkCnt;
-  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters                 */
-  arm_status status;                             /* status of Partial convolution */
-
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_MATH_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-
-    /* The algorithm implementation is based on the lengths of the inputs. */
-    /* srcB is always made to slide across srcA. */
-    /* So srcBLen is always considered as shorter or equal to srcALen */
-    if(srcALen >= srcBLen)
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcA;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcB;
-    }
-    else
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcB;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcA;
-
-      /* srcBLen is always considered as shorter or equal to srcALen */
-      j = srcBLen;
-      srcBLen = srcALen;
-      srcALen = j;
-    }
-
-    /* Conditions to check which loopCounter holds    
-     * the first and last indices of the output samples to be calculated. */
-    check = firstIndex + numPoints;
-    blockSize3 = ((int32_t) check - (int32_t) srcALen);
-    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
-    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
-    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
-                                     (int32_t) numPoints) : 0;
-    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
-                                    (int32_t) firstIndex);
-    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
-
-    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
-    /* The function is internally    
-     * divided into three stages according to the number of multiplications that has to be    
-     * taken place between inputA samples and inputB samples. In the first stage of the    
-     * algorithm, the multiplications increase by one for every iteration.    
-     * In the second stage of the algorithm, srcBLen number of multiplications are done.    
-     * In the third stage of the algorithm, the multiplications decrease by one    
-     * for every iteration. */
-
-    /* Set the output pointer to point to the firstIndex    
-     * of the output sample to be calculated. */
-    pOut = pDst + firstIndex;
-
-    /* --------------------------    
-     * Initializations of stage1    
-     * -------------------------*/
-
-    /* sum = x[0] * y[0]    
-     * sum = x[0] * y[1] + x[1] * y[0]    
-     * ....    
-     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]    
-     */
-
-    /* In this stage the MAC operations are increased by 1 for every iteration.    
-       The count variable holds the number of MAC operations performed.    
-       Since the partial convolution starts from firstIndex    
-       Number of Macs to be performed is firstIndex + 1 */
-    count = 1u + firstIndex;
-
-    /* Working pointer of inputA */
-    px = pIn1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + firstIndex;
-    py = pSrc2;
-
-    /* ------------------------    
-     * Stage1 process    
-     * ----------------------*/
-
-    /* The first loop starts here */
-    while(blockSize1 > 0)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* x[0] * y[srcBLen - 1] */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-
-        /* x[1] * y[srcBLen - 2] */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-
-        /* x[2] * y[srcBLen - 3] */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-
-        /* x[3] * y[srcBLen - 4] */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the count is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = count % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = sum << 1;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      py = ++pSrc2;
-      px = pIn1;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Decrement the loop counter */
-      blockSize1--;
-    }
-
-    /* --------------------------    
-     * Initializations of stage2    
-     * ------------------------*/
-
-    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]    
-     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]    
-     * ....    
-     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]    
-     */
-
-    /* Working pointer of inputA */
-    px = pIn1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + (srcBLen - 1u);
-    py = pSrc2;
-
-    /* count is index by which the pointer pIn1 to be incremented */
-    count = 0u;
-
-    /* -------------------    
-     * Stage2 process    
-     * ------------------*/
-
-    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
-     * So, to loop unroll over blockSize2,    
-     * srcBLen should be greater than or equal to 4 */
-    if(srcBLen >= 4u)
-    {
-      /* Loop unroll over blockSize2 */
-      blkCnt = ((uint32_t) blockSize2 >> 2u);
-
-      while(blkCnt > 0u)
-      {
-        /* Set all accumulators to zero */
-        acc0 = 0;
-        acc1 = 0;
-        acc2 = 0;
-        acc3 = 0;
-
-        /* read x[0], x[1], x[2] samples */
-        x0 = *(px++);
-        x1 = *(px++);
-        x2 = *(px++);
-
-        /* Apply loop unrolling and compute 4 MACs simultaneously. */
-        k = srcBLen >> 2u;
-
-        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-        do
-        {
-          /* Read y[srcBLen - 1] sample */
-          c0 = *(py--);
-
-          /* Read x[3] sample */
-          x3 = *(px++);
-
-          /* Perform the multiply-accumulate */
-          /* acc0 +=  x[0] * y[srcBLen - 1] */
-          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
-
-          /* acc1 +=  x[1] * y[srcBLen - 1] */
-          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
-
-          /* acc2 +=  x[2] * y[srcBLen - 1] */
-          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
-
-          /* acc3 +=  x[3] * y[srcBLen - 1] */
-          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
-
-          /* Read y[srcBLen - 2] sample */
-          c0 = *(py--);
-
-          /* Read x[4] sample */
-          x0 = *(px++);
-
-          /* Perform the multiply-accumulate */
-          /* acc0 +=  x[1] * y[srcBLen - 2] */
-          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
-          /* acc1 +=  x[2] * y[srcBLen - 2] */
-          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
-          /* acc2 +=  x[3] * y[srcBLen - 2] */
-          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
-          /* acc3 +=  x[4] * y[srcBLen - 2] */
-          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
-
-          /* Read y[srcBLen - 3] sample */
-          c0 = *(py--);
-
-          /* Read x[5] sample */
-          x1 = *(px++);
-
-          /* Perform the multiply-accumulates */
-          /* acc0 +=  x[2] * y[srcBLen - 3] */
-          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
-          /* acc1 +=  x[3] * y[srcBLen - 2] */
-          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
-          /* acc2 +=  x[4] * y[srcBLen - 2] */
-          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
-          /* acc3 +=  x[5] * y[srcBLen - 2] */
-          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
-
-          /* Read y[srcBLen - 4] sample */
-          c0 = *(py--);
-
-          /* Read x[6] sample */
-          x2 = *(px++);
-
-          /* Perform the multiply-accumulates */
-          /* acc0 +=  x[3] * y[srcBLen - 4] */
-          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
-          /* acc1 +=  x[4] * y[srcBLen - 4] */
-          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
-          /* acc2 +=  x[5] * y[srcBLen - 4] */
-          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
-          /* acc3 +=  x[6] * y[srcBLen - 4] */
-          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
-
-
-        } while(--k);
-
-        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
-         ** No loop unrolling is used. */
-        k = srcBLen % 0x4u;
-
-        while(k > 0u)
-        {
-          /* Read y[srcBLen - 5] sample */
-          c0 = *(py--);
-
-          /* Read x[7] sample */
-          x3 = *(px++);
-
-          /* Perform the multiply-accumulates */
-          /* acc0 +=  x[4] * y[srcBLen - 5] */
-          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
-          /* acc1 +=  x[5] * y[srcBLen - 5] */
-          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
-          /* acc2 +=  x[6] * y[srcBLen - 5] */
-          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
-          /* acc3 +=  x[7] * y[srcBLen - 5] */
-          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
-
-          /* Reuse the present samples for the next MAC */
-          x0 = x1;
-          x1 = x2;
-          x2 = x3;
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = (q31_t) (acc0 << 1);
-        *pOut++ = (q31_t) (acc1 << 1);
-        *pOut++ = (q31_t) (acc2 << 1);
-        *pOut++ = (q31_t) (acc3 << 1);
-
-        /* Increment the pointer pIn1 index, count by 4 */
-        count += 4u;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-
-      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.    
-       ** No loop unrolling is used. */
-      blkCnt = (uint32_t) blockSize2 % 0x4u;
-
-      while(blkCnt > 0u)
-      {
-        /* Accumulator is made zero for every iteration */
-        sum = 0;
-
-        /* Apply loop unrolling and compute 4 MACs simultaneously. */
-        k = srcBLen >> 2u;
-
-        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulates */
-          sum = (q31_t) ((((q63_t) sum << 32) +
-                          ((q63_t) * px++ * (*py--))) >> 32);
-          sum = (q31_t) ((((q63_t) sum << 32) +
-                          ((q63_t) * px++ * (*py--))) >> 32);
-          sum = (q31_t) ((((q63_t) sum << 32) +
-                          ((q63_t) * px++ * (*py--))) >> 32);
-          sum = (q31_t) ((((q63_t) sum << 32) +
-                          ((q63_t) * px++ * (*py--))) >> 32);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
-         ** No loop unrolling is used. */
-        k = srcBLen % 0x4u;
-
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulate */
-          sum = (q31_t) ((((q63_t) sum << 32) +
-                          ((q63_t) * px++ * (*py--))) >> 32);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = sum << 1;
-
-        /* Increment the MAC count */
-        count++;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-    }
-    else
-    {
-      /* If the srcBLen is not a multiple of 4,    
-       * the blockSize2 loop cannot be unrolled by 4 */
-      blkCnt = (uint32_t) blockSize2;
-
-      while(blkCnt > 0u)
-      {
-        /* Accumulator is made zero for every iteration */
-        sum = 0;
-
-        /* srcBLen number of MACS should be performed */
-        k = srcBLen;
-
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulate */
-          sum = (q31_t) ((((q63_t) sum << 32) +
-                          ((q63_t) * px++ * (*py--))) >> 32);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = sum << 1;
-
-        /* Increment the MAC count */
-        count++;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-    }
-
-
-    /* --------------------------    
-     * Initializations of stage3    
-     * -------------------------*/
-
-    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]    
-     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]    
-     * ....    
-     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]    
-     * sum +=  x[srcALen-1] * y[srcBLen-1]    
-     */
-
-    /* In this stage the MAC operations are decreased by 1 for every iteration.    
-       The count variable holds the number of MAC operations performed */
-    count = srcBLen - 1u;
-
-    /* Working pointer of inputA */
-    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-    px = pSrc1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + (srcBLen - 1u);
-    py = pSrc2;
-
-    /* -------------------    
-     * Stage3 process    
-     * ------------------*/
-
-    while(blockSize3 > 0)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-
-        /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-
-        /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-
-        /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the count is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = count % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py--))) >> 32);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = sum << 1;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = ++pSrc1;
-      py = pSrc2;
-
-      /* Decrement the MAC count */
-      count--;
-
-      /* Decrement the loop counter */
-      blockSize3--;
-
-    }
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-
-}
-
-/**    
- * @} end of PartialConv group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q15.c
deleted file mode 100644
index 0dd3347a82..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q15.c
+++ /dev/null
@@ -1,764 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_conv_partial_opt_q15.c    
-*    
-* Description:	Partial convolution of Q15 sequences.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*  
-* Version 1.0.11 2011/10/18  
-*    Bug Fix in conv, correlation, partial convolution.  
-* 
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-*    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup PartialConv    
- * @{    
- */
-
-/**    
- * @brief Partial convolution of Q15 sequences.    
- * @param[in]       *pSrcA points to the first input sequence.    
- * @param[in]       srcALen length of the first input sequence.    
- * @param[in]       *pSrcB points to the second input sequence.    
- * @param[in]       srcBLen length of the second input sequence.    
- * @param[out]      *pDst points to the location where the output result is written.    
- * @param[in]       firstIndex is the first output sample to start with.    
- * @param[in]       numPoints is the number of output points to be computed.    
- * @param[in]       *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
- * @param[in]       *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).   
- * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].    
- *    
- * \par Restrictions    
- *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
- *	In this case input, output, state buffers should be aligned by 32-bit    
- *    
- * Refer to arm_conv_partial_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.   
- *  
- * 
- */
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-arm_status arm_conv_partial_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2)
-{
-
-  q15_t *pOut = pDst;                            /* output pointer */
-  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */
-  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */
-  q63_t acc0, acc1, acc2, acc3;                  /* Accumulator */
-  q31_t x1, x2, x3;                              /* Temporary variables to hold state and coefficient values */
-  q31_t y1, y2;                                  /* State variables */
-  q15_t *pIn1;                                   /* inputA pointer */
-  q15_t *pIn2;                                   /* inputB pointer */
-  q15_t *px;                                     /* Intermediate inputA pointer  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  uint32_t j, k, blkCnt;                         /* loop counter */
-  arm_status status;                             /* Status variable */
-  uint32_t tapCnt;                               /* loop count */
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_MATH_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-
-    /* The algorithm implementation is based on the lengths of the inputs. */
-    /* srcB is always made to slide across srcA. */
-    /* So srcBLen is always considered as shorter or equal to srcALen */
-    if(srcALen >= srcBLen)
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcA;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcB;
-    }
-    else
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcB;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcA;
-
-      /* srcBLen is always considered as shorter or equal to srcALen */
-      j = srcBLen;
-      srcBLen = srcALen;
-      srcALen = j;
-    }
-
-    /* Temporary pointer for scratch2 */
-    py = pScratch2;
-
-    /* pointer to take end of scratch2 buffer */
-    pScr2 = pScratch2 + srcBLen - 1;
-
-    /* points to smaller length sequence */
-    px = pIn2;
-
-    /* Apply loop unrolling and do 4 Copies simultaneously. */
-    k = srcBLen >> 2u;
-
-    /* First part of the processing with loop unrolling copies 4 data points at a time.       
-     ** a second loop below copies for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner */
-      *pScr2-- = *px++;
-      *pScr2-- = *px++;
-      *pScr2-- = *px++;
-      *pScr2-- = *px++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, copy remaining samples here.       
-     ** No loop unrolling is used. */
-    k = srcBLen % 0x4u;
-
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner for remaining samples */
-      *pScr2-- = *px++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Initialze temporary scratch pointer */
-    pScr1 = pScratch1;
-
-    /* Fill (srcBLen - 1u) zeros in scratch buffer */
-    arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-    /* Update temporary scratch pointer */
-    pScr1 += (srcBLen - 1u);
-
-    /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
-
-    /* Copy (srcALen) samples in scratch buffer */
-    arm_copy_q15(pIn1, pScr1, srcALen);
-
-    /* Update pointers */
-    pScr1 += srcALen;
-
-    /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
-    arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-    /* Update pointer */
-    pScr1 += (srcBLen - 1u);
-
-    /* Initialization of pIn2 pointer */
-    pIn2 = py;
-
-    pScratch1 += firstIndex;
-
-    pOut = pDst + firstIndex;
-
-    /* Actual convolution process starts here */
-    blkCnt = (numPoints) >> 2;
-
-    while(blkCnt > 0)
-    {
-      /* Initialze temporary scratch pointer as scratch1 */
-      pScr1 = pScratch1;
-
-      /* Clear Accumlators */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-      /* Read two samples from scratch1 buffer */
-      x1 = *__SIMD32(pScr1)++;
-
-      /* Read next two samples from scratch1 buffer */
-      x2 = *__SIMD32(pScr1)++;
-
-      tapCnt = (srcBLen) >> 2u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read four samples from smaller buffer */
-        y1 = _SIMD32_OFFSET(pIn2);
-        y2 = _SIMD32_OFFSET(pIn2 + 2u);
-
-        /* multiply and accumlate */
-        acc0 = __SMLALD(x1, y1, acc0);
-        acc2 = __SMLALD(x2, y1, acc2);
-
-        /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
-        x3 = __PKHBT(x2, x1, 0);
-#else
-        x3 = __PKHBT(x1, x2, 0);
-#endif
-
-        /* multiply and accumlate */
-        acc1 = __SMLALDX(x3, y1, acc1);
-
-        /* Read next two samples from scratch1 buffer */
-        x1 = _SIMD32_OFFSET(pScr1);
-
-        /* multiply and accumlate */
-        acc0 = __SMLALD(x2, y2, acc0);
-        acc2 = __SMLALD(x1, y2, acc2);
-
-        /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
-        x3 = __PKHBT(x1, x2, 0);
-#else
-        x3 = __PKHBT(x2, x1, 0);
-#endif
-
-        acc3 = __SMLALDX(x3, y1, acc3);
-        acc1 = __SMLALDX(x3, y2, acc1);
-
-        x2 = _SIMD32_OFFSET(pScr1 + 2u);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-        x3 = __PKHBT(x2, x1, 0);
-#else
-        x3 = __PKHBT(x1, x2, 0);
-#endif
-
-        acc3 = __SMLALDX(x3, y2, acc3);
-
-        /* update scratch pointers */
-        pIn2 += 4u;
-        pScr1 += 4u;
-
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* Update scratch pointer for remaining samples of smaller length sequence */
-      pScr1 -= 4u;
-
-      /* apply same above for remaining samples of smaller length sequence */
-      tapCnt = (srcBLen) & 3u;
-
-      while(tapCnt > 0u)
-      {
-        /* accumlate the results */
-        acc0 += (*pScr1++ * *pIn2);
-        acc1 += (*pScr1++ * *pIn2);
-        acc2 += (*pScr1++ * *pIn2);
-        acc3 += (*pScr1++ * *pIn2++);
-
-        pScr1 -= 3u;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      blkCnt--;
-
-
-      /* Store the results in the accumulators in the destination buffer. */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
-
-#else
-
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-      /* Initialization of inputB pointer */
-      pIn2 = py;
-
-      pScratch1 += 4u;
-
-    }
-
-
-    blkCnt = numPoints & 0x3;
-
-    /* Calculate convolution for remaining samples of Bigger length sequence */
-    while(blkCnt > 0)
-    {
-      /* Initialze temporary scratch pointer as scratch1 */
-      pScr1 = pScratch1;
-
-      /* Clear Accumlators */
-      acc0 = 0;
-
-      tapCnt = (srcBLen) >> 1u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read next two samples from scratch1 buffer */
-        x1 = *__SIMD32(pScr1)++;
-
-        /* Read two samples from smaller buffer */
-        y1 = *__SIMD32(pIn2)++;
-
-        acc0 = __SMLALD(x1, y1, acc0);
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      tapCnt = (srcBLen) & 1u;
-
-      /* apply same above for remaining samples of smaller length sequence */
-      while(tapCnt > 0u)
-      {
-
-        /* accumlate the results */
-        acc0 += (*pScr1++ * *pIn2++);
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      blkCnt--;
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-
-      /* Initialization of inputB pointer */
-      pIn2 = py;
-
-      pScratch1 += 1u;
-
-    }
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-#else
-
-arm_status arm_conv_partial_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2)
-{
-
-  q15_t *pOut = pDst;                            /* output pointer */
-  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch1 */
-  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch1 */
-  q63_t acc0, acc1, acc2, acc3;                  /* Accumulator */
-  q15_t *pIn1;                                   /* inputA pointer */
-  q15_t *pIn2;                                   /* inputB pointer */
-  q15_t *px;                                     /* Intermediate inputA pointer  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  uint32_t j, k, blkCnt;                         /* loop counter */
-  arm_status status;                             /* Status variable */
-  uint32_t tapCnt;                               /* loop count */
-  q15_t x10, x11, x20, x21;                      /* Temporary variables to hold srcA buffer */
-  q15_t y10, y11;                                /* Temporary variables to hold srcB buffer */
-
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_MATH_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-
-    /* The algorithm implementation is based on the lengths of the inputs. */
-    /* srcB is always made to slide across srcA. */
-    /* So srcBLen is always considered as shorter or equal to srcALen */
-    if(srcALen >= srcBLen)
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcA;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcB;
-    }
-    else
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcB;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcA;
-
-      /* srcBLen is always considered as shorter or equal to srcALen */
-      j = srcBLen;
-      srcBLen = srcALen;
-      srcALen = j;
-    }
-
-    /* Temporary pointer for scratch2 */
-    py = pScratch2;
-
-    /* pointer to take end of scratch2 buffer */
-    pScr2 = pScratch2 + srcBLen - 1;
-
-    /* points to smaller length sequence */
-    px = pIn2;
-
-    /* Apply loop unrolling and do 4 Copies simultaneously. */
-    k = srcBLen >> 2u;
-
-    /* First part of the processing with loop unrolling copies 4 data points at a time.       
-     ** a second loop below copies for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner */
-      *pScr2-- = *px++;
-      *pScr2-- = *px++;
-      *pScr2-- = *px++;
-      *pScr2-- = *px++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, copy remaining samples here.       
-     ** No loop unrolling is used. */
-    k = srcBLen % 0x4u;
-
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner for remaining samples */
-      *pScr2-- = *px++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Initialze temporary scratch pointer */
-    pScr1 = pScratch1;
-
-    /* Fill (srcBLen - 1u) zeros in scratch buffer */
-    arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-    /* Update temporary scratch pointer */
-    pScr1 += (srcBLen - 1u);
-
-    /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
-
-
-    /* Apply loop unrolling and do 4 Copies simultaneously. */
-    k = srcALen >> 2u;
-
-    /* First part of the processing with loop unrolling copies 4 data points at a time.       
-     ** a second loop below copies for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner */
-      *pScr1++ = *pIn1++;
-      *pScr1++ = *pIn1++;
-      *pScr1++ = *pIn1++;
-      *pScr1++ = *pIn1++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, copy remaining samples here.       
-     ** No loop unrolling is used. */
-    k = srcALen % 0x4u;
-
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner for remaining samples */
-      *pScr1++ = *pIn1++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-
-    /* Apply loop unrolling and do 4 Copies simultaneously. */
-    k = (srcBLen - 1u) >> 2u;
-
-    /* First part of the processing with loop unrolling copies 4 data points at a time.       
-     ** a second loop below copies for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner */
-      *pScr1++ = 0;
-      *pScr1++ = 0;
-      *pScr1++ = 0;
-      *pScr1++ = 0;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, copy remaining samples here.       
-     ** No loop unrolling is used. */
-    k = (srcBLen - 1u) % 0x4u;
-
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner for remaining samples */
-      *pScr1++ = 0;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-
-    /* Initialization of pIn2 pointer */
-    pIn2 = py;
-
-    pScratch1 += firstIndex;
-
-    pOut = pDst + firstIndex;
-
-    /* Actual convolution process starts here */
-    blkCnt = (numPoints) >> 2;
-
-    while(blkCnt > 0)
-    {
-      /* Initialze temporary scratch pointer as scratch1 */
-      pScr1 = pScratch1;
-
-      /* Clear Accumlators */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-      /* Read two samples from scratch1 buffer */
-      x10 = *pScr1++;
-      x11 = *pScr1++;
-
-      /* Read next two samples from scratch1 buffer */
-      x20 = *pScr1++;
-      x21 = *pScr1++;
-
-      tapCnt = (srcBLen) >> 2u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read two samples from smaller buffer */
-        y10 = *pIn2;
-        y11 = *(pIn2 + 1u);
-
-        /* multiply and accumlate */
-        acc0 += (q63_t) x10 *y10;
-        acc0 += (q63_t) x11 *y11;
-        acc2 += (q63_t) x20 *y10;
-        acc2 += (q63_t) x21 *y11;
-
-        /* multiply and accumlate */
-        acc1 += (q63_t) x11 *y10;
-        acc1 += (q63_t) x20 *y11;
-
-        /* Read next two samples from scratch1 buffer */
-        x10 = *pScr1;
-        x11 = *(pScr1 + 1u);
-
-        /* multiply and accumlate */
-        acc3 += (q63_t) x21 *y10;
-        acc3 += (q63_t) x10 *y11;
-
-        /* Read next two samples from scratch2 buffer */
-        y10 = *(pIn2 + 2u);
-        y11 = *(pIn2 + 3u);
-
-        /* multiply and accumlate */
-        acc0 += (q63_t) x20 *y10;
-        acc0 += (q63_t) x21 *y11;
-        acc2 += (q63_t) x10 *y10;
-        acc2 += (q63_t) x11 *y11;
-        acc1 += (q63_t) x21 *y10;
-        acc1 += (q63_t) x10 *y11;
-
-        /* Read next two samples from scratch1 buffer */
-        x20 = *(pScr1 + 2);
-        x21 = *(pScr1 + 3);
-
-        /* multiply and accumlate */
-        acc3 += (q63_t) x11 *y10;
-        acc3 += (q63_t) x20 *y11;
-
-        /* update scratch pointers */
-        pIn2 += 4u;
-        pScr1 += 4u;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* Update scratch pointer for remaining samples of smaller length sequence */
-      pScr1 -= 4u;
-
-      /* apply same above for remaining samples of smaller length sequence */
-      tapCnt = (srcBLen) & 3u;
-
-      while(tapCnt > 0u)
-      {
-        /* accumlate the results */
-        acc0 += (*pScr1++ * *pIn2);
-        acc1 += (*pScr1++ * *pIn2);
-        acc2 += (*pScr1++ * *pIn2);
-        acc3 += (*pScr1++ * *pIn2++);
-
-        pScr1 -= 3u;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      blkCnt--;
-
-
-      /* Store the results in the accumulators in the destination buffer. */
-      *pOut++ = __SSAT((acc0 >> 15), 16);
-      *pOut++ = __SSAT((acc1 >> 15), 16);
-      *pOut++ = __SSAT((acc2 >> 15), 16);
-      *pOut++ = __SSAT((acc3 >> 15), 16);
-
-
-      /* Initialization of inputB pointer */
-      pIn2 = py;
-
-      pScratch1 += 4u;
-
-    }
-
-
-    blkCnt = numPoints & 0x3;
-
-    /* Calculate convolution for remaining samples of Bigger length sequence */
-    while(blkCnt > 0)
-    {
-      /* Initialze temporary scratch pointer as scratch1 */
-      pScr1 = pScratch1;
-
-      /* Clear Accumlators */
-      acc0 = 0;
-
-      tapCnt = (srcBLen) >> 1u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read next two samples from scratch1 buffer */
-        x10 = *pScr1++;
-        x11 = *pScr1++;
-
-        /* Read two samples from smaller buffer */
-        y10 = *pIn2++;
-        y11 = *pIn2++;
-
-        /* multiply and accumlate */
-        acc0 += (q63_t) x10 *y10;
-        acc0 += (q63_t) x11 *y11;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      tapCnt = (srcBLen) & 1u;
-
-      /* apply same above for remaining samples of smaller length sequence */
-      while(tapCnt > 0u)
-      {
-
-        /* accumlate the results */
-        acc0 += (*pScr1++ * *pIn2++);
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      blkCnt--;
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-
-
-      /* Initialization of inputB pointer */
-      pIn2 = py;
-
-      pScratch1 += 1u;
-
-    }
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-
-/**    
- * @} end of PartialConv group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q7.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q7.c
deleted file mode 100644
index 6a82603165..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q7.c
+++ /dev/null
@@ -1,806 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_conv_partial_opt_q7.c    
-*    
-* Description:	Partial convolution of Q7 sequences.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*  
-* Version 1.0.11 2011/10/18  
-*    Bug Fix in conv, correlation, partial convolution.  
-* 
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-*    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup PartialConv    
- * @{    
- */
-
-/**    
- * @brief Partial convolution of Q7 sequences.    
- * @param[in]       *pSrcA points to the first input sequence.    
- * @param[in]       srcALen length of the first input sequence.    
- * @param[in]       *pSrcB points to the second input sequence.    
- * @param[in]       srcBLen length of the second input sequence.    
- * @param[out]      *pDst points to the location where the output result is written.    
- * @param[in]       firstIndex is the first output sample to start with.    
- * @param[in]       numPoints is the number of output points to be computed.    
- * @param[in]      *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.    
- * @param[in]      *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).    
- * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].    
- *    
- * \par Restrictions    
- *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
- *	In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit   
- * 
- *
- * 
- */
-
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-arm_status arm_conv_partial_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2)
-{
-
-  q15_t *pScr2, *pScr1;                          /* Intermediate pointers for scratch pointers */
-  q15_t x4;                                      /* Temporary input variable */
-  q7_t *pIn1, *pIn2;                             /* inputA and inputB pointer */
-  uint32_t j, k, blkCnt, tapCnt;                 /* loop counter */
-  q7_t *px;                                      /* Temporary input1 pointer */
-  q15_t *py;                                     /* Temporary input2 pointer */
-  q31_t acc0, acc1, acc2, acc3;                  /* Accumulator */
-  q31_t x1, x2, x3, y1;                          /* Temporary input variables */
-  arm_status status;
-  q7_t *pOut = pDst;                             /* output pointer */
-  q7_t out0, out1, out2, out3;                   /* temporary variables */
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_MATH_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-
-    /* The algorithm implementation is based on the lengths of the inputs. */
-    /* srcB is always made to slide across srcA. */
-    /* So srcBLen is always considered as shorter or equal to srcALen */
-    if(srcALen >= srcBLen)
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcA;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcB;
-    }
-    else
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcB;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcA;
-
-      /* srcBLen is always considered as shorter or equal to srcALen */
-      j = srcBLen;
-      srcBLen = srcALen;
-      srcALen = j;
-    }
-
-    /* pointer to take end of scratch2 buffer */
-    pScr2 = pScratch2;
-
-    /* points to smaller length sequence */
-    px = pIn2 + srcBLen - 1;
-
-    /* Apply loop unrolling and do 4 Copies simultaneously. */
-    k = srcBLen >> 2u;
-
-    /* First part of the processing with loop unrolling copies 4 data points at a time.       
-     ** a second loop below copies for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner */
-      x4 = (q15_t) * px--;
-      *pScr2++ = x4;
-      x4 = (q15_t) * px--;
-      *pScr2++ = x4;
-      x4 = (q15_t) * px--;
-      *pScr2++ = x4;
-      x4 = (q15_t) * px--;
-      *pScr2++ = x4;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, copy remaining samples here.       
-     ** No loop unrolling is used. */
-    k = srcBLen % 0x4u;
-
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner for remaining samples */
-      x4 = (q15_t) * px--;
-      *pScr2++ = x4;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Initialze temporary scratch pointer */
-    pScr1 = pScratch1;
-
-    /* Fill (srcBLen - 1u) zeros in scratch buffer */
-    arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-    /* Update temporary scratch pointer */
-    pScr1 += (srcBLen - 1u);
-
-    /* Copy (srcALen) samples in scratch buffer */
-    /* Apply loop unrolling and do 4 Copies simultaneously. */
-    k = srcALen >> 2u;
-
-    /* First part of the processing with loop unrolling copies 4 data points at a time.       
-     ** a second loop below copies for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner */
-      x4 = (q15_t) * pIn1++;
-      *pScr1++ = x4;
-      x4 = (q15_t) * pIn1++;
-      *pScr1++ = x4;
-      x4 = (q15_t) * pIn1++;
-      *pScr1++ = x4;
-      x4 = (q15_t) * pIn1++;
-      *pScr1++ = x4;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, copy remaining samples here.       
-     ** No loop unrolling is used. */
-    k = srcALen % 0x4u;
-
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner for remaining samples */
-      x4 = (q15_t) * pIn1++;
-      *pScr1++ = x4;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
-    arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-    /* Update pointer */
-    pScr1 += (srcBLen - 1u);
-
-
-    /* Temporary pointer for scratch2 */
-    py = pScratch2;
-
-    /* Initialization of pIn2 pointer */
-    pIn2 = (q7_t *) py;
-
-    pScr2 = py;
-
-    pOut = pDst + firstIndex;
-
-    pScratch1 += firstIndex;
-
-    /* Actual convolution process starts here */
-    blkCnt = (numPoints) >> 2;
-
-
-    while(blkCnt > 0)
-    {
-      /* Initialze temporary scratch pointer as scratch1 */
-      pScr1 = pScratch1;
-
-      /* Clear Accumlators */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-      /* Read two samples from scratch1 buffer */
-      x1 = *__SIMD32(pScr1)++;
-
-      /* Read next two samples from scratch1 buffer */
-      x2 = *__SIMD32(pScr1)++;
-
-      tapCnt = (srcBLen) >> 2u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read four samples from smaller buffer */
-        y1 = _SIMD32_OFFSET(pScr2);
-
-        /* multiply and accumlate */
-        acc0 = __SMLAD(x1, y1, acc0);
-        acc2 = __SMLAD(x2, y1, acc2);
-
-        /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
-        x3 = __PKHBT(x2, x1, 0);
-#else
-        x3 = __PKHBT(x1, x2, 0);
-#endif
-
-        /* multiply and accumlate */
-        acc1 = __SMLADX(x3, y1, acc1);
-
-        /* Read next two samples from scratch1 buffer */
-        x1 = *__SIMD32(pScr1)++;
-
-        /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
-        x3 = __PKHBT(x1, x2, 0);
-#else
-        x3 = __PKHBT(x2, x1, 0);
-#endif
-
-        acc3 = __SMLADX(x3, y1, acc3);
-
-        /* Read four samples from smaller buffer */
-        y1 = _SIMD32_OFFSET(pScr2 + 2u);
-
-        acc0 = __SMLAD(x2, y1, acc0);
-
-        acc2 = __SMLAD(x1, y1, acc2);
-
-        acc1 = __SMLADX(x3, y1, acc1);
-
-        x2 = *__SIMD32(pScr1)++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-        x3 = __PKHBT(x2, x1, 0);
-#else
-        x3 = __PKHBT(x1, x2, 0);
-#endif
-
-        acc3 = __SMLADX(x3, y1, acc3);
-
-        pScr2 += 4u;
-
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-
-
-      /* Update scratch pointer for remaining samples of smaller length sequence */
-      pScr1 -= 4u;
-
-
-      /* apply same above for remaining samples of smaller length sequence */
-      tapCnt = (srcBLen) & 3u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* accumlate the results */
-        acc0 += (*pScr1++ * *pScr2);
-        acc1 += (*pScr1++ * *pScr2);
-        acc2 += (*pScr1++ * *pScr2);
-        acc3 += (*pScr1++ * *pScr2++);
-
-        pScr1 -= 3u;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      blkCnt--;
-
-      /* Store the result in the accumulator in the destination buffer. */
-      out0 = (q7_t) (__SSAT(acc0 >> 7u, 8));
-      out1 = (q7_t) (__SSAT(acc1 >> 7u, 8));
-      out2 = (q7_t) (__SSAT(acc2 >> 7u, 8));
-      out3 = (q7_t) (__SSAT(acc3 >> 7u, 8));
-
-      *__SIMD32(pOut)++ = __PACKq7(out0, out1, out2, out3);
-
-      /* Initialization of inputB pointer */
-      pScr2 = py;
-
-      pScratch1 += 4u;
-
-    }
-
-    blkCnt = (numPoints) & 0x3;
-
-    /* Calculate convolution for remaining samples of Bigger length sequence */
-    while(blkCnt > 0)
-    {
-      /* Initialze temporary scratch pointer as scratch1 */
-      pScr1 = pScratch1;
-
-      /* Clear Accumlators */
-      acc0 = 0;
-
-      tapCnt = (srcBLen) >> 1u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read next two samples from scratch1 buffer */
-        x1 = *__SIMD32(pScr1)++;
-
-        /* Read two samples from smaller buffer */
-        y1 = *__SIMD32(pScr2)++;
-
-        acc0 = __SMLAD(x1, y1, acc0);
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      tapCnt = (srcBLen) & 1u;
-
-      /* apply same above for remaining samples of smaller length sequence */
-      while(tapCnt > 0u)
-      {
-
-        /* accumlate the results */
-        acc0 += (*pScr1++ * *pScr2++);
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      blkCnt--;
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
-
-      /* Initialization of inputB pointer */
-      pScr2 = py;
-
-      pScratch1 += 1u;
-
-    }
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-
-
-  }
-
-  return (status);
-
-}
-
-#else
-
-arm_status arm_conv_partial_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2)
-{
-
-  q15_t *pScr2, *pScr1;                          /* Intermediate pointers for scratch pointers */
-  q15_t x4;                                      /* Temporary input variable */
-  q7_t *pIn1, *pIn2;                             /* inputA and inputB pointer */
-  uint32_t j, k, blkCnt, tapCnt;                 /* loop counter */
-  q7_t *px;                                      /* Temporary input1 pointer */
-  q15_t *py;                                     /* Temporary input2 pointer */
-  q31_t acc0, acc1, acc2, acc3;                  /* Accumulator */
-  arm_status status;
-  q7_t *pOut = pDst;                             /* output pointer */
-  q15_t x10, x11, x20, x21;                      /* Temporary input variables */
-  q15_t y10, y11;                                /* Temporary input variables */
-  q7_t out0, out1, out2, out3;                   /* temporary variables */
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_MATH_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-
-    /* The algorithm implementation is based on the lengths of the inputs. */
-    /* srcB is always made to slide across srcA. */
-    /* So srcBLen is always considered as shorter or equal to srcALen */
-    if(srcALen >= srcBLen)
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcA;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcB;
-    }
-    else
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcB;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcA;
-
-      /* srcBLen is always considered as shorter or equal to srcALen */
-      j = srcBLen;
-      srcBLen = srcALen;
-      srcALen = j;
-    }
-
-    /* pointer to take end of scratch2 buffer */
-    pScr2 = pScratch2;
-
-    /* points to smaller length sequence */
-    px = pIn2 + srcBLen - 1;
-
-    /* Apply loop unrolling and do 4 Copies simultaneously. */
-    k = srcBLen >> 2u;
-
-    /* First part of the processing with loop unrolling copies 4 data points at a time.       
-     ** a second loop below copies for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner */
-      x4 = (q15_t) * px--;
-      *pScr2++ = x4;
-      x4 = (q15_t) * px--;
-      *pScr2++ = x4;
-      x4 = (q15_t) * px--;
-      *pScr2++ = x4;
-      x4 = (q15_t) * px--;
-      *pScr2++ = x4;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, copy remaining samples here.       
-     ** No loop unrolling is used. */
-    k = srcBLen % 0x4u;
-
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner for remaining samples */
-      x4 = (q15_t) * px--;
-      *pScr2++ = x4;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Initialze temporary scratch pointer */
-    pScr1 = pScratch1;
-
-    /* Fill (srcBLen - 1u) zeros in scratch buffer */
-    arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-    /* Update temporary scratch pointer */
-    pScr1 += (srcBLen - 1u);
-
-    /* Copy (srcALen) samples in scratch buffer */
-    /* Apply loop unrolling and do 4 Copies simultaneously. */
-    k = srcALen >> 2u;
-
-    /* First part of the processing with loop unrolling copies 4 data points at a time.       
-     ** a second loop below copies for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner */
-      x4 = (q15_t) * pIn1++;
-      *pScr1++ = x4;
-      x4 = (q15_t) * pIn1++;
-      *pScr1++ = x4;
-      x4 = (q15_t) * pIn1++;
-      *pScr1++ = x4;
-      x4 = (q15_t) * pIn1++;
-      *pScr1++ = x4;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, copy remaining samples here.       
-     ** No loop unrolling is used. */
-    k = srcALen % 0x4u;
-
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner for remaining samples */
-      x4 = (q15_t) * pIn1++;
-      *pScr1++ = x4;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Apply loop unrolling and do 4 Copies simultaneously. */
-    k = (srcBLen - 1u) >> 2u;
-
-    /* First part of the processing with loop unrolling copies 4 data points at a time.       
-     ** a second loop below copies for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner */
-      *pScr1++ = 0;
-      *pScr1++ = 0;
-      *pScr1++ = 0;
-      *pScr1++ = 0;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, copy remaining samples here.       
-     ** No loop unrolling is used. */
-    k = (srcBLen - 1u) % 0x4u;
-
-    while(k > 0u)
-    {
-      /* copy second buffer in reversal manner for remaining samples */
-      *pScr1++ = 0;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-
-    /* Temporary pointer for scratch2 */
-    py = pScratch2;
-
-    /* Initialization of pIn2 pointer */
-    pIn2 = (q7_t *) py;
-
-    pScr2 = py;
-
-    pOut = pDst + firstIndex;
-
-    pScratch1 += firstIndex;
-
-    /* Actual convolution process starts here */
-    blkCnt = (numPoints) >> 2;
-
-
-    while(blkCnt > 0)
-    {
-      /* Initialze temporary scratch pointer as scratch1 */
-      pScr1 = pScratch1;
-
-      /* Clear Accumlators */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-      /* Read two samples from scratch1 buffer */
-      x10 = *pScr1++;
-      x11 = *pScr1++;
-
-      /* Read next two samples from scratch1 buffer */
-      x20 = *pScr1++;
-      x21 = *pScr1++;
-
-      tapCnt = (srcBLen) >> 2u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read four samples from smaller buffer */
-        y10 = *pScr2;
-        y11 = *(pScr2 + 1u);
-
-        /* multiply and accumlate */
-        acc0 += (q31_t) x10 *y10;
-        acc0 += (q31_t) x11 *y11;
-        acc2 += (q31_t) x20 *y10;
-        acc2 += (q31_t) x21 *y11;
-
-
-        acc1 += (q31_t) x11 *y10;
-        acc1 += (q31_t) x20 *y11;
-
-        /* Read next two samples from scratch1 buffer */
-        x10 = *pScr1;
-        x11 = *(pScr1 + 1u);
-
-        /* multiply and accumlate */
-        acc3 += (q31_t) x21 *y10;
-        acc3 += (q31_t) x10 *y11;
-
-        /* Read next two samples from scratch2 buffer */
-        y10 = *(pScr2 + 2u);
-        y11 = *(pScr2 + 3u);
-
-        /* multiply and accumlate */
-        acc0 += (q31_t) x20 *y10;
-        acc0 += (q31_t) x21 *y11;
-        acc2 += (q31_t) x10 *y10;
-        acc2 += (q31_t) x11 *y11;
-        acc1 += (q31_t) x21 *y10;
-        acc1 += (q31_t) x10 *y11;
-
-        /* Read next two samples from scratch1 buffer */
-        x20 = *(pScr1 + 2);
-        x21 = *(pScr1 + 3);
-
-        /* multiply and accumlate */
-        acc3 += (q31_t) x11 *y10;
-        acc3 += (q31_t) x20 *y11;
-
-        /* update scratch pointers */
-
-        pScr1 += 4u;
-        pScr2 += 4u;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-
-
-      /* Update scratch pointer for remaining samples of smaller length sequence */
-      pScr1 -= 4u;
-
-
-      /* apply same above for remaining samples of smaller length sequence */
-      tapCnt = (srcBLen) & 3u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* accumlate the results */
-        acc0 += (*pScr1++ * *pScr2);
-        acc1 += (*pScr1++ * *pScr2);
-        acc2 += (*pScr1++ * *pScr2);
-        acc3 += (*pScr1++ * *pScr2++);
-
-        pScr1 -= 3u;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      blkCnt--;
-
-      /* Store the result in the accumulator in the destination buffer. */
-      out0 = (q7_t) (__SSAT(acc0 >> 7u, 8));
-      out1 = (q7_t) (__SSAT(acc1 >> 7u, 8));
-      out2 = (q7_t) (__SSAT(acc2 >> 7u, 8));
-      out3 = (q7_t) (__SSAT(acc3 >> 7u, 8));
-
-
-      *__SIMD32(pOut)++ = __PACKq7(out0, out1, out2, out3);
-
-      /* Initialization of inputB pointer */
-      pScr2 = py;
-
-      pScratch1 += 4u;
-
-    }
-
-    blkCnt = (numPoints) & 0x3;
-
-    /* Calculate convolution for remaining samples of Bigger length sequence */
-    while(blkCnt > 0)
-    {
-      /* Initialze temporary scratch pointer as scratch1 */
-      pScr1 = pScratch1;
-
-      /* Clear Accumlators */
-      acc0 = 0;
-
-      tapCnt = (srcBLen) >> 1u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read next two samples from scratch1 buffer */
-        x10 = *pScr1++;
-        x11 = *pScr1++;
-
-        /* Read two samples from smaller buffer */
-        y10 = *pScr2++;
-        y11 = *pScr2++;
-
-        /* multiply and accumlate */
-        acc0 += (q31_t) x10 *y10;
-        acc0 += (q31_t) x11 *y11;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      tapCnt = (srcBLen) & 1u;
-
-      /* apply same above for remaining samples of smaller length sequence */
-      while(tapCnt > 0u)
-      {
-
-        /* accumlate the results */
-        acc0 += (*pScr1++ * *pScr2++);
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      blkCnt--;
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
-
-      /* Initialization of inputB pointer */
-      pScr2 = py;
-
-      pScratch1 += 1u;
-
-    }
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-
-  }
-
-  return (status);
-
-}
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-
-
-/**    
- * @} end of PartialConv group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q15.c
deleted file mode 100644
index 83d7cc6219..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q15.c
+++ /dev/null
@@ -1,778 +0,0 @@
-/* ----------------------------------------------------------------------   
-* Copyright (C) 2010 ARM Limited. All rights reserved.   
-*   
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*   
-* Project: 	    CMSIS DSP Library   
-* Title:		arm_conv_partial_q15.c   
-*   
-* Description:	Partial convolution of Q15 sequences.  
-*   
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-* 
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*  
-* Version 1.0.11 2011/10/18 
-*    Bug Fix in conv, correlation, partial convolution. 
-*
-* Version 1.0.10 2011/7/15 
-*    Big Endian support added and Merged M0 and M3/M4 Source code.  
-*   
-* Version 1.0.3 2010/11/29  
-*    Re-organized the CMSIS folders and updated documentation.   
-*    
-* Version 1.0.2 2010/11/11   
-*    Documentation updated.    
-*   
-* Version 1.0.1 2010/10/05    
-*    Production release and review comments incorporated.   
-*   
-* Version 1.0.0 2010/09/20    
-*    Production release and review comments incorporated   
-*   
-* Version 0.0.7  2010/06/10    
-*    Misra-C changes done   
-*   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**   
- * @ingroup groupFilters   
- */
-
-/**   
- * @addtogroup PartialConv   
- * @{   
- */
-
-/**   
- * @brief Partial convolution of Q15 sequences.   
- * @param[in]       *pSrcA points to the first input sequence.   
- * @param[in]       srcALen length of the first input sequence.   
- * @param[in]       *pSrcB points to the second input sequence.   
- * @param[in]       srcBLen length of the second input sequence.   
- * @param[out]      *pDst points to the location where the output result is written.   
- * @param[in]       firstIndex is the first output sample to start with.   
- * @param[in]       numPoints is the number of output points to be computed.   
- * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
- *   
- * Refer to arm_conv_partial_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.  
- * 
- * \par    
- * Refer the function arm_conv_partial_opt_q15() for a faster implementation of this function using scratch buffers.
- * 
- */
-
-
-arm_status arm_conv_partial_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints)
-{
-
-#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q15_t *pIn1;                                   /* inputA pointer               */
-  q15_t *pIn2;                                   /* inputB pointer               */
-  q15_t *pOut = pDst;                            /* output pointer               */
-  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulator                  */
-  q15_t *px;                                     /* Intermediate inputA pointer  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
-  q31_t x0, x1, x2, x3, c0;                      /* Temporary input variables */
-  uint32_t j, k, count, check, blkCnt;
-  int32_t blockSize1, blockSize2, blockSize3;    /* loop counter                 */
-  arm_status status;                             /* status of Partial convolution */
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_MATH_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-
-    /* The algorithm implementation is based on the lengths of the inputs. */
-    /* srcB is always made to slide across srcA. */
-    /* So srcBLen is always considered as shorter or equal to srcALen */
-    if(srcALen >= srcBLen)
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcA;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcB;
-    }
-    else
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcB;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcA;
-
-      /* srcBLen is always considered as shorter or equal to srcALen */
-      j = srcBLen;
-      srcBLen = srcALen;
-      srcALen = j;
-    }
-
-    /* Conditions to check which loopCounter holds   
-     * the first and last indices of the output samples to be calculated. */
-    check = firstIndex + numPoints;
-    blockSize3 = ((int32_t) check - (int32_t) srcALen);
-    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
-    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
-    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
-                                     (int32_t) numPoints) : 0;
-    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
-                                    (int32_t) firstIndex);
-    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
-
-    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
-    /* The function is internally   
-     * divided into three stages according to the number of multiplications that has to be   
-     * taken place between inputA samples and inputB samples. In the first stage of the   
-     * algorithm, the multiplications increase by one for every iteration.   
-     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
-     * In the third stage of the algorithm, the multiplications decrease by one   
-     * for every iteration. */
-
-    /* Set the output pointer to point to the firstIndex   
-     * of the output sample to be calculated. */
-    pOut = pDst + firstIndex;
-
-    /* --------------------------   
-     * Initializations of stage1   
-     * -------------------------*/
-
-    /* sum = x[0] * y[0]   
-     * sum = x[0] * y[1] + x[1] * y[0]   
-     * ....   
-     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
-     */
-
-    /* In this stage the MAC operations are increased by 1 for every iteration.   
-       The count variable holds the number of MAC operations performed.   
-       Since the partial convolution starts from firstIndex   
-       Number of Macs to be performed is firstIndex + 1 */
-    count = 1u + firstIndex;
-
-    /* Working pointer of inputA */
-    px = pIn1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + firstIndex;
-    py = pSrc2;
-
-    /* ------------------------   
-     * Stage1 process   
-     * ----------------------*/
-
-    /* For loop unrolling by 4, this stage is divided into two. */
-    /* First part of this stage computes the MAC operations less than 4 */
-    /* Second part of this stage computes the MAC operations greater than or equal to 4 */
-
-    /* The first part of the stage starts here */
-    while((count < 4u) && (blockSize1 > 0))
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Loop over number of MAC operations between   
-       * inputA samples and inputB samples */
-      k = count;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum = __SMLALD(*px++, *py--, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      py = ++pSrc2;
-      px = pIn1;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Decrement the loop counter */
-      blockSize1--;
-    }
-
-    /* The second part of the stage starts here */
-    /* The internal loop, over count, is unrolled by 4 */
-    /* To, read the last two inputB samples using SIMD:   
-     * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
-    py = py - 1;
-
-    while(blockSize1 > 0)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
-        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-        /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
-        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* For the next MAC operations, the pointer py is used without SIMD   
-       * So, py is incremented by 1 */
-      py = py + 1u;
-
-      /* If the count is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = count % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum = __SMLALD(*px++, *py--, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      py = ++pSrc2 - 1u;
-      px = pIn1;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Decrement the loop counter */
-      blockSize1--;
-    }
-
-    /* --------------------------   
-     * Initializations of stage2   
-     * ------------------------*/
-
-    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
-     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
-     * ....   
-     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
-     */
-
-    /* Working pointer of inputA */
-    px = pIn1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + (srcBLen - 1u);
-    py = pSrc2;
-
-  /* count is the index by which the pointer pIn1 to be incremented */
-  count = 0u;
-
-
-  /* --------------------   
-   * Stage2 process   
-   * -------------------*/
-
-  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
-   * So, to loop unroll over blockSize2,   
-   * srcBLen should be greater than or equal to 4 */
-  if(srcBLen >= 4u)
-  {
-    /* Loop unroll over blockSize2, by 4 */
-    blkCnt = blockSize2 >> 2u;
-
-    while(blkCnt > 0u)
-    {
-      py = py - 1u;
-
-      /* Set all accumulators to zero */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-
-      /* read x[0], x[1] samples */
-      x0 = *__SIMD32(px);
-      /* read x[1], x[2] samples */
-      x1 = _SIMD32_OFFSET(px+1);
-	  px+= 2u;
-
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      do
-      {
-        /* Read the last two inputB samples using SIMD:   
-         * y[srcBLen - 1] and y[srcBLen - 2] */
-        c0 = *__SIMD32(py)--;
-
-        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
-        acc0 = __SMLALDX(x0, c0, acc0);
-
-        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
-        acc1 = __SMLALDX(x1, c0, acc1);
-
-        /* Read x[2], x[3] */
-        x2 = *__SIMD32(px);
-
-        /* Read x[3], x[4] */
-        x3 = _SIMD32_OFFSET(px+1);
-
-        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
-        acc2 = __SMLALDX(x2, c0, acc2);
-
-        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
-        acc3 = __SMLALDX(x3, c0, acc3);
-
-        /* Read y[srcBLen - 3] and y[srcBLen - 4] */
-        c0 = *__SIMD32(py)--;
-
-        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
-        acc0 = __SMLALDX(x2, c0, acc0);
-
-        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
-        acc1 = __SMLALDX(x3, c0, acc1);
-
-        /* Read x[4], x[5] */
-        x0 = _SIMD32_OFFSET(px+2);
-
-        /* Read x[5], x[6] */
-        x1 = _SIMD32_OFFSET(px+3);
-		px += 4u;
-
-        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
-        acc2 = __SMLALDX(x0, c0, acc2);
-
-        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
-        acc3 = __SMLALDX(x1, c0, acc3);
-
-      } while(--k);
-
-      /* For the next MAC operations, SIMD is not used   
-       * So, the 16 bit pointer if inputB, py is updated */
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      if(k == 1u)
-      {
-        /* Read y[srcBLen - 5] */
-        c0 = *(py+1);
-
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-
-#else
-
-        c0 = c0 & 0x0000FFFF;
-
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-
-        /* Read x[7] */
-        x3 = *__SIMD32(px);
-		px++;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLALD(x0, c0, acc0);
-        acc1 = __SMLALD(x1, c0, acc1);
-        acc2 = __SMLALDX(x1, c0, acc2);
-        acc3 = __SMLALDX(x3, c0, acc3);
-      }
-
-      if(k == 2u)
-      {
-        /* Read y[srcBLen - 5], y[srcBLen - 6] */
-        c0 = _SIMD32_OFFSET(py);
-
-        /* Read x[7], x[8] */
-        x3 = *__SIMD32(px);
-
-        /* Read x[9] */
-        x2 = _SIMD32_OFFSET(px+1);
-		px += 2u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLALDX(x0, c0, acc0);
-        acc1 = __SMLALDX(x1, c0, acc1);
-        acc2 = __SMLALDX(x3, c0, acc2);
-        acc3 = __SMLALDX(x2, c0, acc3);
-      }
-
-      if(k == 3u)
-      {
-        /* Read y[srcBLen - 5], y[srcBLen - 6] */
-        c0 = _SIMD32_OFFSET(py);
-
-        /* Read x[7], x[8] */
-        x3 = *__SIMD32(px);
-
-        /* Read x[9] */
-        x2 = _SIMD32_OFFSET(px+1);
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLALDX(x0, c0, acc0);
-        acc1 = __SMLALDX(x1, c0, acc1);
-        acc2 = __SMLALDX(x3, c0, acc2);
-        acc3 = __SMLALDX(x2, c0, acc3);
-
-		c0 = *(py-1);
-
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-#else
-
-        c0 = c0 & 0x0000FFFF;
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-
-        /* Read x[10] */
-        x3 =  _SIMD32_OFFSET(px+2);
-		px += 3u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLALDX(x1, c0, acc0);
-        acc1 = __SMLALD(x2, c0, acc1);
-        acc2 = __SMLALDX(x2, c0, acc2);
-        acc3 = __SMLALDX(x3, c0, acc3);
-      }
-
-
-      /* Store the results in the accumulators in the destination buffer. */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
-
-#else
-
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-      /* Increment the pointer pIn1 index, count by 4 */
-      count += 4u;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-
-      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
-       ** No loop unrolling is used. */
-      blkCnt = (uint32_t) blockSize2 % 0x4u;
-  	  
-      while(blkCnt > 0u)
-      {
-        /* Accumulator is made zero for every iteration */
-        sum = 0;
-
-        /* Apply loop unrolling and compute 4 MACs simultaneously. */
-        k = srcBLen >> 2u;
-
-        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulates */
-          sum += (q63_t) ((q31_t) * px++ * *py--);
-          sum += (q63_t) ((q31_t) * px++ * *py--);
-          sum += (q63_t) ((q31_t) * px++ * *py--);
-          sum += (q63_t) ((q31_t) * px++ * *py--);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-         ** No loop unrolling is used. */
-        k = srcBLen % 0x4u;
-
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulates */
-          sum += (q63_t) ((q31_t) * px++ * *py--);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
-
-        /* Increment the pointer pIn1 index, count by 1 */
-        count++;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-    }
-    else
-    {
-      /* If the srcBLen is not a multiple of 4,   
-       * the blockSize2 loop cannot be unrolled by 4 */
-      blkCnt = (uint32_t) blockSize2;
-
-      while(blkCnt > 0u)
-      {
-        /* Accumulator is made zero for every iteration */
-        sum = 0;
-
-        /* srcBLen number of MACS should be performed */
-        k = srcBLen;
-
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulate */
-          sum += (q63_t) ((q31_t) * px++ * *py--);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
-
-        /* Increment the MAC count */
-        count++;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-  
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-    }
-
-
-    /* --------------------------   
-     * Initializations of stage3   
-     * -------------------------*/
-
-    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
-     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
-     * ....   
-     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
-     * sum +=  x[srcALen-1] * y[srcBLen-1]   
-     */
-
-    /* In this stage the MAC operations are decreased by 1 for every iteration.   
-       The count variable holds the number of MAC operations performed */
-    count = srcBLen - 1u;
-
-    /* Working pointer of inputA */
-    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-    px = pSrc1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + (srcBLen - 1u);
-    pIn2 = pSrc2 - 1u;
-    py = pIn2;
-
-    /* -------------------   
-     * Stage3 process   
-     * ------------------*/
-
-    /* For loop unrolling by 4, this stage is divided into two. */
-    /* First part of this stage computes the MAC operations greater than 4 */
-    /* Second part of this stage computes the MAC operations less than or equal to 4 */
-
-    /* The first part of the stage starts here */
-    j = count >> 2u;
-
-    while((j > 0u) && (blockSize3 > 0))
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   
-         * with y[srcBLen - 1], y[srcBLen - 2] respectively */
-        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-        /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   
-         * with y[srcBLen - 3], y[srcBLen - 4] respectively */
-        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* For the next MAC operations, the pointer py is used without SIMD   
-       * So, py is incremented by 1 */
-      py = py + 1u;
-
-      /* If the count is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = count % 0x4u;
-
-      while(k > 0u)
-      {
-        /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
-        sum = __SMLALD(*px++, *py--, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = ++pSrc1;
-      py = pIn2;
-
-      /* Decrement the MAC count */
-      count--;
-
-      /* Decrement the loop counter */
-      blockSize3--;
-
-      j--;
-    }
-
-    /* The second part of the stage starts here */
-    /* SIMD is not used for the next MAC operations,   
-     * so pointer py is updated to read only one sample at a time */
-    py = py + 1u;
-
-    while(blockSize3 > 0)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
-        sum = __SMLALD(*px++, *py--, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = ++pSrc1;
-      py = pSrc2;
-
-      /* Decrement the MAC count */
-      count--;
-
-      /* Decrement the loop counter */
-      blockSize3--;
-    }
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q15_t *pIn1 = pSrcA;                           /* inputA pointer */
-  q15_t *pIn2 = pSrcB;                           /* inputB pointer */
-  q63_t sum;                                     /* Accumulator */
-  uint32_t i, j;                                 /* loop counters */
-  arm_status status;                             /* status of Partial convolution */
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-    /* Loop to calculate convolution for output length number of values */
-    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
-    {
-      /* Initialize sum with zero to carry on MAC operations */
-      sum = 0;
-
-      /* Loop to perform MAC operations according to convolution equation */
-      for (j = 0; j <= i; j++)
-      {
-        /* Check the array limitations */
-        if(((i - j) < srcBLen) && (j < srcALen))
-        {
-          /* z[i] += x[i-j] * y[j] */
-          sum += ((q31_t) pIn1[j] * (pIn2[i - j]));
-        }
-      }
-
-      /* Store the output in the destination buffer */
-      pDst[i] = (q15_t) __SSAT((sum >> 15u), 16u);
-    }
-    /* set status as ARM_SUCCESS as there are no argument errors */
-    status = ARM_MATH_SUCCESS;
-  }
-  return (status);
-
-#endif /* #if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)  */
-
-}
-
-/**   
- * @} end of PartialConv group   
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q31.c
deleted file mode 100644
index 89c98be966..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q31.c
+++ /dev/null
@@ -1,599 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_conv_partial_q31.c    
-*    
-* Description:	Partial convolution of Q31 sequences.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*  
-* Version 1.0.11 2011/10/18  
-*    Bug Fix in conv, correlation, partial convolution.  
-* 
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-*    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup PartialConv    
- * @{    
- */
-
-/**    
- * @brief Partial convolution of Q31 sequences.    
- * @param[in]       *pSrcA points to the first input sequence.    
- * @param[in]       srcALen length of the first input sequence.    
- * @param[in]       *pSrcB points to the second input sequence.    
- * @param[in]       srcBLen length of the second input sequence.    
- * @param[out]      *pDst points to the location where the output result is written.    
- * @param[in]       firstIndex is the first output sample to start with.    
- * @param[in]       numPoints is the number of output points to be computed.    
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].    
- *    
- * See arm_conv_partial_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.    
- */
-
-arm_status arm_conv_partial_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints)
-{
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t *pIn1;                                   /* inputA pointer               */
-  q31_t *pIn2;                                   /* inputB pointer               */
-  q31_t *pOut = pDst;                            /* output pointer               */
-  q31_t *px;                                     /* Intermediate inputA pointer  */
-  q31_t *py;                                     /* Intermediate inputB pointer  */
-  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
-  q63_t sum, acc0, acc1, acc2;                   /* Accumulator                  */
-  q31_t x0, x1, x2, c0;
-  uint32_t j, k, count, check, blkCnt;
-  int32_t blockSize1, blockSize2, blockSize3;    /* loop counter                 */
-  arm_status status;                             /* status of Partial convolution */
-
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_MATH_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-
-    /* The algorithm implementation is based on the lengths of the inputs. */
-    /* srcB is always made to slide across srcA. */
-    /* So srcBLen is always considered as shorter or equal to srcALen */
-    if(srcALen >= srcBLen)
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcA;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcB;
-    }
-    else
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcB;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcA;
-
-      /* srcBLen is always considered as shorter or equal to srcALen */
-      j = srcBLen;
-      srcBLen = srcALen;
-      srcALen = j;
-    }
-
-    /* Conditions to check which loopCounter holds    
-     * the first and last indices of the output samples to be calculated. */
-    check = firstIndex + numPoints;
-    blockSize3 = ((int32_t) check - (int32_t) srcALen);
-    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
-    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
-    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
-                                     (int32_t) numPoints) : 0;
-    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
-                                    (int32_t) firstIndex);
-    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
-
-    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
-    /* The function is internally    
-     * divided into three stages according to the number of multiplications that has to be    
-     * taken place between inputA samples and inputB samples. In the first stage of the    
-     * algorithm, the multiplications increase by one for every iteration.    
-     * In the second stage of the algorithm, srcBLen number of multiplications are done.    
-     * In the third stage of the algorithm, the multiplications decrease by one    
-     * for every iteration. */
-
-    /* Set the output pointer to point to the firstIndex    
-     * of the output sample to be calculated. */
-    pOut = pDst + firstIndex;
-
-    /* --------------------------    
-     * Initializations of stage1    
-     * -------------------------*/
-
-    /* sum = x[0] * y[0]    
-     * sum = x[0] * y[1] + x[1] * y[0]    
-     * ....    
-     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]    
-     */
-
-    /* In this stage the MAC operations are increased by 1 for every iteration.    
-       The count variable holds the number of MAC operations performed.    
-       Since the partial convolution starts from firstIndex    
-       Number of Macs to be performed is firstIndex + 1 */
-    count = 1u + firstIndex;
-
-    /* Working pointer of inputA */
-    px = pIn1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + firstIndex;
-    py = pSrc2;
-
-    /* ------------------------    
-     * Stage1 process    
-     * ----------------------*/
-
-    /* The first loop starts here */
-    while(blockSize1 > 0)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* x[0] * y[srcBLen - 1] */
-        sum += (q63_t) * px++ * (*py--);
-        /* x[1] * y[srcBLen - 2] */
-        sum += (q63_t) * px++ * (*py--);
-        /* x[2] * y[srcBLen - 3] */
-        sum += (q63_t) * px++ * (*py--);
-        /* x[3] * y[srcBLen - 4] */
-        sum += (q63_t) * px++ * (*py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the count is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = count % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += (q63_t) * px++ * (*py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q31_t) (sum >> 31);
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      py = ++pSrc2;
-      px = pIn1;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Decrement the loop counter */
-      blockSize1--;
-    }
-
-    /* --------------------------    
-     * Initializations of stage2    
-     * ------------------------*/
-
-    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]    
-     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]    
-     * ....    
-     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]    
-     */
-
-    /* Working pointer of inputA */
-    px = pIn1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + (srcBLen - 1u);
-    py = pSrc2;
-
-    /* count is index by which the pointer pIn1 to be incremented */
-    count = 0u;
-
-    /* -------------------    
-     * Stage2 process    
-     * ------------------*/
-
-    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
-     * So, to loop unroll over blockSize2,    
-     * srcBLen should be greater than or equal to 4 */
-    if(srcBLen >= 4u)
-    {
-      /* Loop unroll over blkCnt */
-
-      blkCnt = blockSize2 / 3;
-      while(blkCnt > 0u)
-      {
-        /* Set all accumulators to zero */
-        acc0 = 0;
-        acc1 = 0;
-        acc2 = 0;
-
-        /* read x[0], x[1] samples */
-        x0 = *(px++);
-        x1 = *(px++);
-
-        /* Apply loop unrolling and compute 3 MACs simultaneously. */
-        k = srcBLen / 3;
-
-        /* First part of the processing with loop unrolling.  Compute 3 MACs at a time.        
-         ** a second loop below computes MACs for the remaining 1 to 2 samples. */
-        do
-        {
-          /* Read y[srcBLen - 1] sample */
-          c0 = *(py);
-
-          /* Read x[2] sample */
-          x2 = *(px);
-
-          /* Perform the multiply-accumulates */
-          /* acc0 +=  x[0] * y[srcBLen - 1] */
-          acc0 += (q63_t) x0 *c0;
-          /* acc1 +=  x[1] * y[srcBLen - 1] */
-          acc1 += (q63_t) x1 *c0;
-          /* acc2 +=  x[2] * y[srcBLen - 1] */
-          acc2 += (q63_t) x2 *c0;
-
-          /* Read y[srcBLen - 2] sample */
-          c0 = *(py - 1u);
-
-          /* Read x[3] sample */
-          x0 = *(px + 1u);
-
-          /* Perform the multiply-accumulate */
-          /* acc0 +=  x[1] * y[srcBLen - 2] */
-          acc0 += (q63_t) x1 *c0;
-          /* acc1 +=  x[2] * y[srcBLen - 2] */
-          acc1 += (q63_t) x2 *c0;
-          /* acc2 +=  x[3] * y[srcBLen - 2] */
-          acc2 += (q63_t) x0 *c0;
-
-          /* Read y[srcBLen - 3] sample */
-          c0 = *(py - 2u);
-
-          /* Read x[4] sample */
-          x1 = *(px + 2u);
-
-          /* Perform the multiply-accumulates */
-          /* acc0 +=  x[2] * y[srcBLen - 3] */
-          acc0 += (q63_t) x2 *c0;
-          /* acc1 +=  x[3] * y[srcBLen - 2] */
-          acc1 += (q63_t) x0 *c0;
-          /* acc2 +=  x[4] * y[srcBLen - 2] */
-          acc2 += (q63_t) x1 *c0;
-
-
-          px += 3u;
-
-          py -= 3u;
-
-        } while(--k);
-
-        /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.        
-         ** No loop unrolling is used. */
-        k = srcBLen - (3 * (srcBLen / 3));
-
-        while(k > 0u)
-        {
-          /* Read y[srcBLen - 5] sample */
-          c0 = *(py--);
-
-          /* Read x[7] sample */
-          x2 = *(px++);
-
-          /* Perform the multiply-accumulates */
-          /* acc0 +=  x[4] * y[srcBLen - 5] */
-          acc0 += (q63_t) x0 *c0;
-          /* acc1 +=  x[5] * y[srcBLen - 5] */
-          acc1 += (q63_t) x1 *c0;
-          /* acc2 +=  x[6] * y[srcBLen - 5] */
-          acc2 += (q63_t) x2 *c0;
-
-          /* Reuse the present samples for the next MAC */
-          x0 = x1;
-          x1 = x2;
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = (q31_t) (acc0 >> 31);
-        *pOut++ = (q31_t) (acc1 >> 31);
-        *pOut++ = (q31_t) (acc2 >> 31);
-
-        /* Increment the pointer pIn1 index, count by 3 */
-        count += 3u;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-
-      /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.        
-       ** No loop unrolling is used. */
-      blkCnt = blockSize2 - 3 * (blockSize2 / 3);
-
-      while(blkCnt > 0u)
-      {
-        /* Accumulator is made zero for every iteration */
-        sum = 0;
-
-        /* Apply loop unrolling and compute 4 MACs simultaneously. */
-        k = srcBLen >> 2u;
-
-        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulates */
-          sum += (q63_t) * px++ * (*py--);
-          sum += (q63_t) * px++ * (*py--);
-          sum += (q63_t) * px++ * (*py--);
-          sum += (q63_t) * px++ * (*py--);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
-         ** No loop unrolling is used. */
-        k = srcBLen % 0x4u;
-
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulate */
-          sum += (q63_t) * px++ * (*py--);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = (q31_t) (sum >> 31);
-
-        /* Increment the MAC count */
-        count++;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-    }
-    else
-    {
-      /* If the srcBLen is not a multiple of 4,    
-       * the blockSize2 loop cannot be unrolled by 4 */
-      blkCnt = (uint32_t) blockSize2;
-
-      while(blkCnt > 0u)
-      {
-        /* Accumulator is made zero for every iteration */
-        sum = 0;
-
-        /* srcBLen number of MACS should be performed */
-        k = srcBLen;
-
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulate */
-          sum += (q63_t) * px++ * (*py--);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = (q31_t) (sum >> 31);
-
-        /* Increment the MAC count */
-        count++;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-    }
-
-
-    /* --------------------------    
-     * Initializations of stage3    
-     * -------------------------*/
-
-    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]    
-     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]    
-     * ....    
-     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]    
-     * sum +=  x[srcALen-1] * y[srcBLen-1]    
-     */
-
-    /* In this stage the MAC operations are decreased by 1 for every iteration.    
-       The blockSize3 variable holds the number of MAC operations performed */
-    count = srcBLen - 1u;
-
-    /* Working pointer of inputA */
-    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-    px = pSrc1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + (srcBLen - 1u);
-    py = pSrc2;
-
-    /* -------------------    
-     * Stage3 process    
-     * ------------------*/
-
-    while(blockSize3 > 0)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        sum += (q63_t) * px++ * (*py--);
-        sum += (q63_t) * px++ * (*py--);
-        sum += (q63_t) * px++ * (*py--);
-        sum += (q63_t) * px++ * (*py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = count % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += (q63_t) * px++ * (*py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q31_t) (sum >> 31);
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = ++pSrc1;
-      py = pSrc2;
-
-      /* Decrement the MAC count */
-      count--;
-
-      /* Decrement the loop counter */
-      blockSize3--;
-
-    }
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q31_t *pIn1 = pSrcA;                           /* inputA pointer */
-  q31_t *pIn2 = pSrcB;                           /* inputB pointer */
-  q63_t sum;                                     /* Accumulator */
-  uint32_t i, j;                                 /* loop counters */
-  arm_status status;                             /* status of Partial convolution */
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-    /* Loop to calculate convolution for output length number of values */
-    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
-    {
-      /* Initialize sum with zero to carry on MAC operations */
-      sum = 0;
-
-      /* Loop to perform MAC operations according to convolution equation */
-      for (j = 0; j <= i; j++)
-      {
-        /* Check the array limitations */
-        if(((i - j) < srcBLen) && (j < srcALen))
-        {
-          /* z[i] += x[i-j] * y[j] */
-          sum += ((q63_t) pIn1[j] * (pIn2[i - j]));
-        }
-      }
-
-      /* Store the output in the destination buffer */
-      pDst[i] = (q31_t) (sum >> 31u);
-    }
-    /* set status as ARM_SUCCESS as there are no argument errors */
-    status = ARM_MATH_SUCCESS;
-  }
-  return (status);
-
-#endif /*    #ifndef ARM_MATH_CM0      */
-
-}
-
-/**    
- * @} end of PartialConv group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q7.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q7.c
deleted file mode 100644
index b532669947..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q7.c
+++ /dev/null
@@ -1,733 +0,0 @@
-/* ----------------------------------------------------------------------   
-* Copyright (C) 2010 ARM Limited. All rights reserved.   
-*   
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*   
-* Project: 	    CMSIS DSP Library   
-* Title:		arm_conv_partial_q7.c   
-*   
-* Description:	Partial convolution of Q7 sequences.   
-*   
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*  
-* Version 1.0.11 2011/10/18 
-*    Bug Fix in conv, correlation, partial convolution. 
-*
-* Version 1.0.10 2011/7/15 
-*    Big Endian support added and Merged M0 and M3/M4 Source code.  
-*   
-* Version 1.0.3 2010/11/29  
-*    Re-organized the CMSIS folders and updated documentation.   
-*    
-* Version 1.0.2 2010/11/11   
-*    Documentation updated.    
-*   
-* Version 1.0.1 2010/10/05    
-*    Production release and review comments incorporated.   
-*   
-* Version 1.0.0 2010/09/20    
-*    Production release and review comments incorporated   
-*   
-* Version 0.0.7  2010/06/10    
-*    Misra-C changes done   
-*   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**   
- * @ingroup groupFilters   
- */
-
-/**   
- * @addtogroup PartialConv   
- * @{   
- */
-
-/**   
- * @brief Partial convolution of Q7 sequences.   
- * @param[in]       *pSrcA points to the first input sequence.   
- * @param[in]       srcALen length of the first input sequence.   
- * @param[in]       *pSrcB points to the second input sequence.   
- * @param[in]       srcBLen length of the second input sequence.   
- * @param[out]      *pDst points to the location where the output result is written.   
- * @param[in]       firstIndex is the first output sample to start with.   
- * @param[in]       numPoints is the number of output points to be computed.   
- * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
- *  
- * \par    
- * Refer the function arm_conv_partial_opt_q7() for a faster implementation of this function.
- *  
- */
-
-arm_status arm_conv_partial_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints)
-{
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q7_t *pIn1;                                    /* inputA pointer */
-  q7_t *pIn2;                                    /* inputB pointer */
-  q7_t *pOut = pDst;                             /* output pointer */
-  q7_t *px;                                      /* Intermediate inputA pointer */
-  q7_t *py;                                      /* Intermediate inputB pointer */
-  q7_t *pSrc1, *pSrc2;                           /* Intermediate pointers */
-  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
-  q31_t input1, input2;
-  q15_t in1, in2;
-  q7_t x0, x1, x2, x3, c0, c1;
-  uint32_t j, k, count, check, blkCnt;
-  int32_t blockSize1, blockSize2, blockSize3;    /* loop counter */
-  arm_status status;
-
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_MATH_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-
-    /* The algorithm implementation is based on the lengths of the inputs. */
-    /* srcB is always made to slide across srcA. */
-    /* So srcBLen is always considered as shorter or equal to srcALen */
-    if(srcALen >= srcBLen)
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcA;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcB;
-    }
-    else
-    {
-      /* Initialization of inputA pointer */
-      pIn1 = pSrcB;
-
-      /* Initialization of inputB pointer */
-      pIn2 = pSrcA;
-
-      /* srcBLen is always considered as shorter or equal to srcALen */
-      j = srcBLen;
-      srcBLen = srcALen;
-      srcALen = j;
-    }
-
-    /* Conditions to check which loopCounter holds   
-     * the first and last indices of the output samples to be calculated. */
-    check = firstIndex + numPoints;
-    blockSize3 = ((int32_t) check - (int32_t) srcALen);
-    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
-    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
-    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
-                                     (int32_t) numPoints) : 0;
-    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
-                                    (int32_t) firstIndex);
-    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
-
-    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
-    /* The function is internally   
-     * divided into three stages according to the number of multiplications that has to be   
-     * taken place between inputA samples and inputB samples. In the first stage of the   
-     * algorithm, the multiplications increase by one for every iteration.   
-     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
-     * In the third stage of the algorithm, the multiplications decrease by one   
-     * for every iteration. */
-
-    /* Set the output pointer to point to the firstIndex   
-     * of the output sample to be calculated. */
-    pOut = pDst + firstIndex;
-
-    /* --------------------------   
-     * Initializations of stage1   
-     * -------------------------*/
-
-    /* sum = x[0] * y[0]   
-     * sum = x[0] * y[1] + x[1] * y[0]   
-     * ....   
-     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
-     */
-
-    /* In this stage the MAC operations are increased by 1 for every iteration.   
-       The count variable holds the number of MAC operations performed.   
-       Since the partial convolution starts from from firstIndex   
-       Number of Macs to be performed is firstIndex + 1 */
-    count = 1u + firstIndex;
-
-    /* Working pointer of inputA */
-    px = pIn1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + firstIndex;
-    py = pSrc2;
-
-    /* ------------------------   
-     * Stage1 process   
-     * ----------------------*/
-
-    /* The first stage starts here */
-    while(blockSize1 > 0)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* x[0] , x[1] */
-        in1 = (q15_t) * px++;
-        in2 = (q15_t) * px++;
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* y[srcBLen - 1] , y[srcBLen - 2] */
-        in1 = (q15_t) * py--;
-        in2 = (q15_t) * py--;
-        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* x[0] * y[srcBLen - 1] */
-        /* x[1] * y[srcBLen - 2] */
-        sum = __SMLAD(input1, input2, sum);
-
-        /* x[2] , x[3] */
-        in1 = (q15_t) * px++;
-        in2 = (q15_t) * px++;
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* y[srcBLen - 3] , y[srcBLen - 4] */
-        in1 = (q15_t) * py--;
-        in2 = (q15_t) * py--;
-        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* x[2] * y[srcBLen - 3] */
-        /* x[3] * y[srcBLen - 4] */
-        sum = __SMLAD(input1, input2, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the count is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = count % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += ((q31_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      py = ++pSrc2;
-      px = pIn1;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Decrement the loop counter */
-      blockSize1--;
-    }
-
-    /* --------------------------   
-     * Initializations of stage2   
-     * ------------------------*/
-
-    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
-     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
-     * ....   
-     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
-     */
-
-    /* Working pointer of inputA */
-    px = pIn1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + (srcBLen - 1u);
-    py = pSrc2;
-
-    /* count is index by which the pointer pIn1 to be incremented */
-    count = 0u;
-
-    /* -------------------   
-     * Stage2 process   
-     * ------------------*/
-
-    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
-     * So, to loop unroll over blockSize2,   
-     * srcBLen should be greater than or equal to 4 */
-    if(srcBLen >= 4u)
-    {
-      /* Loop unroll over blockSize2, by 4 */
-      blkCnt = ((uint32_t) blockSize2 >> 2u);
-
-      while(blkCnt > 0u)
-      {
-        /* Set all accumulators to zero */
-        acc0 = 0;
-        acc1 = 0;
-        acc2 = 0;
-        acc3 = 0;
-
-        /* read x[0], x[1], x[2] samples */
-        x0 = *(px++);
-        x1 = *(px++);
-        x2 = *(px++);
-
-        /* Apply loop unrolling and compute 4 MACs simultaneously. */
-        k = srcBLen >> 2u;
-
-        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-        do
-        {
-          /* Read y[srcBLen - 1] sample */
-          c0 = *(py--);
-          /* Read y[srcBLen - 2] sample */
-          c1 = *(py--);
-
-          /* Read x[3] sample */
-          x3 = *(px++);
-
-          /* x[0] and x[1] are packed */
-          in1 = (q15_t) x0;
-          in2 = (q15_t) x1;
-
-          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-          /* y[srcBLen - 1]   and y[srcBLen - 2] are packed */
-          in1 = (q15_t) c0;
-          in2 = (q15_t) c1;
-
-          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-          /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2]  */
-          acc0 = __SMLAD(input1, input2, acc0);
-
-          /* x[1] and x[2] are packed */
-          in1 = (q15_t) x1;
-          in2 = (q15_t) x2;
-
-          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-          /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2]  */
-          acc1 = __SMLAD(input1, input2, acc1);
-
-          /* x[2] and x[3] are packed */
-          in1 = (q15_t) x2;
-          in2 = (q15_t) x3;
-
-          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-          /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2]  */
-          acc2 = __SMLAD(input1, input2, acc2);
-
-          /* Read x[4] sample */
-          x0 = *(px++);
-
-          /* x[3] and x[4] are packed */
-          in1 = (q15_t) x3;
-          in2 = (q15_t) x0;
-
-          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-          /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2]  */
-          acc3 = __SMLAD(input1, input2, acc3);
-
-          /* Read y[srcBLen - 3] sample */
-          c0 = *(py--);
-          /* Read y[srcBLen - 4] sample */
-          c1 = *(py--);
-
-          /* Read x[5] sample */
-          x1 = *(px++);
-
-          /* x[2] and x[3] are packed */
-          in1 = (q15_t) x2;
-          in2 = (q15_t) x3;
-
-          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-          /* y[srcBLen - 3] and y[srcBLen - 4] are packed */
-          in1 = (q15_t) c0;
-          in2 = (q15_t) c1;
-
-          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-          /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4]  */
-          acc0 = __SMLAD(input1, input2, acc0);
-
-          /* x[3] and x[4] are packed */
-          in1 = (q15_t) x3;
-          in2 = (q15_t) x0;
-
-          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-          /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4]  */
-          acc1 = __SMLAD(input1, input2, acc1);
-
-          /* x[4] and x[5] are packed */
-          in1 = (q15_t) x0;
-          in2 = (q15_t) x1;
-
-          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-          /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4]  */
-          acc2 = __SMLAD(input1, input2, acc2);
-
-          /* Read x[6] sample */
-          x2 = *(px++);
-
-          /* x[5] and x[6] are packed */
-          in1 = (q15_t) x1;
-          in2 = (q15_t) x2;
-
-          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-          /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4]  */
-          acc3 = __SMLAD(input1, input2, acc3);
-
-        } while(--k);
-
-        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-         ** No loop unrolling is used. */
-        k = srcBLen % 0x4u;
-
-        while(k > 0u)
-        {
-          /* Read y[srcBLen - 5] sample */
-          c0 = *(py--);
-
-          /* Read x[7] sample */
-          x3 = *(px++);
-
-          /* Perform the multiply-accumulates */
-          /* acc0 +=  x[4] * y[srcBLen - 5] */
-          acc0 += ((q31_t) x0 * c0);
-          /* acc1 +=  x[5] * y[srcBLen - 5] */
-          acc1 += ((q31_t) x1 * c0);
-          /* acc2 +=  x[6] * y[srcBLen - 5] */
-          acc2 += ((q31_t) x2 * c0);
-          /* acc3 +=  x[7] * y[srcBLen - 5] */
-          acc3 += ((q31_t) x3 * c0);
-
-          /* Reuse the present samples for the next MAC */
-          x0 = x1;
-          x1 = x2;
-          x2 = x3;
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = (q7_t) (__SSAT(acc0 >> 7, 8));
-        *pOut++ = (q7_t) (__SSAT(acc1 >> 7, 8));
-        *pOut++ = (q7_t) (__SSAT(acc2 >> 7, 8));
-        *pOut++ = (q7_t) (__SSAT(acc3 >> 7, 8));
-
-        /* Increment the pointer pIn1 index, count by 4 */
-        count += 4u;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-
-      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
-       ** No loop unrolling is used. */
-      blkCnt = (uint32_t) blockSize2 % 0x4u;
-
-      while(blkCnt > 0u)
-      {
-        /* Accumulator is made zero for every iteration */
-        sum = 0;
-
-        /* Apply loop unrolling and compute 4 MACs simultaneously. */
-        k = srcBLen >> 2u;
-
-        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-        while(k > 0u)
-        {
-
-          /* Reading two inputs of SrcA buffer and packing */
-          in1 = (q15_t) * px++;
-          in2 = (q15_t) * px++;
-          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-          /* Reading two inputs of SrcB buffer and packing */
-          in1 = (q15_t) * py--;
-          in2 = (q15_t) * py--;
-          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-          /* Perform the multiply-accumulates */
-          sum = __SMLAD(input1, input2, sum);
-
-          /* Reading two inputs of SrcA buffer and packing */
-          in1 = (q15_t) * px++;
-          in2 = (q15_t) * px++;
-          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-          /* Reading two inputs of SrcB buffer and packing */
-          in1 = (q15_t) * py--;
-          in2 = (q15_t) * py--;
-          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-          /* Perform the multiply-accumulates */
-          sum = __SMLAD(input1, input2, sum);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-         ** No loop unrolling is used. */
-        k = srcBLen % 0x4u;
-
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulates */
-          sum += ((q31_t) * px++ * *py--);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
-
-        /* Increment the pointer pIn1 index, count by 1 */
- 	    count++;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-      	px = pIn1 + count;
-        py = pSrc2;	
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-    }
-    else
-    {
-      /* If the srcBLen is not a multiple of 4,   
-       * the blockSize2 loop cannot be unrolled by 4 */
-      blkCnt = (uint32_t) blockSize2;
-
-      while(blkCnt > 0u)
-      {
-        /* Accumulator is made zero for every iteration */
-        sum = 0;
-
-        /* srcBLen number of MACS should be performed */
-        k = srcBLen;
-
-        while(k > 0u)
-        {
-          /* Perform the multiply-accumulate */
-          sum += ((q31_t) * px++ * *py--);
-
-          /* Decrement the loop counter */
-          k--;
-        }
-
-        /* Store the result in the accumulator in the destination buffer. */
-        *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
-
-        /* Increment the MAC count */
-        count++;
-
-        /* Update the inputA and inputB pointers for next MAC calculation */
-        px = pIn1 + count;
-        py = pSrc2;
-
-        /* Decrement the loop counter */
-        blkCnt--;
-      }
-    }
-
-
-    /* --------------------------   
-     * Initializations of stage3   
-     * -------------------------*/
-
-    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
-     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
-     * ....   
-     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
-     * sum +=  x[srcALen-1] * y[srcBLen-1]   
-     */
-
-    /* In this stage the MAC operations are decreased by 1 for every iteration.   
-       The count variable holds the number of MAC operations performed */
-    count = srcBLen - 1u;
-
-    /* Working pointer of inputA */
-    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-    px = pSrc1;
-
-    /* Working pointer of inputB */
-    pSrc2 = pIn2 + (srcBLen - 1u);
-    py = pSrc2;
-
-    /* -------------------   
-     * Stage3 process   
-     * ------------------*/
-
-    while(blockSize3 > 0)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = count >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */
-        in1 = (q15_t) * px++;
-        in2 = (q15_t) * px++;
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */
-        in1 = (q15_t) * py--;
-        in2 = (q15_t) * py--;
-        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
-        /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
-        sum = __SMLAD(input1, input2, sum);
-
-        /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */
-        in1 = (q15_t) * px++;
-        in2 = (q15_t) * px++;
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */
-        in1 = (q15_t) * py--;
-        in2 = (q15_t) * py--;
-        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
-        /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
-        sum = __SMLAD(input1, input2, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the count is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = count % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
-        sum += ((q31_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = ++pSrc1;
-      py = pSrc2;
-
-      /* Decrement the MAC count */
-      count--;
-
-      /* Decrement the loop counter */
-      blockSize3--;
-
-    }
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q7_t *pIn1 = pSrcA;                            /* inputA pointer */
-  q7_t *pIn2 = pSrcB;                            /* inputB pointer */
-  q31_t sum;                                     /* Accumulator */
-  uint32_t i, j;                                 /* loop counters */
-  arm_status status;                             /* status of Partial convolution */
-
-  /* Check for range of output samples to be calculated */
-  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
-  {
-    /* Set status as ARM_ARGUMENT_ERROR */
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-    /* Loop to calculate convolution for output length number of values */
-    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
-    {
-      /* Initialize sum with zero to carry on MAC operations */
-      sum = 0;
-
-      /* Loop to perform MAC operations according to convolution equation */
-      for (j = 0; j <= i; j++)
-      {
-        /* Check the array limitations */
-        if(((i - j) < srcBLen) && (j < srcALen))
-        {
-          /* z[i] += x[i-j] * y[j] */
-          sum += ((q15_t) pIn1[j] * (pIn2[i - j]));
-        }
-      }
-
-      /* Store the output in the destination buffer */
-      pDst[i] = (q7_t) __SSAT((sum >> 7u), 8u);
-    }
-    /* set status as ARM_SUCCESS as there are no argument errors */
-    status = ARM_MATH_SUCCESS;
-  }
-  return (status);
-
-#endif /*  #ifndef ARM_MATH_CM0 */
-
-}
-
-/**   
- * @} end of PartialConv group   
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q15.c
deleted file mode 100644
index ac6425dfe1..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q15.c
+++ /dev/null
@@ -1,733 +0,0 @@
-/* ----------------------------------------------------------------------   
-* Copyright (C) 2010 ARM Limited. All rights reserved.   
-*   
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*   
-* Project: 	    CMSIS DSP Library   
-* Title:		arm_conv_q15.c   
-*   
-* Description:	Convolution of Q15 sequences.     
-*   
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.11 2011/10/18 
-*    Bug Fix in conv, correlation, partial convolution. 
-*
-* Version 1.0.10 2011/7/15 
-*    Big Endian support added and Merged M0 and M3/M4 Source code.  
-*   
-* Version 1.0.3 2010/11/29  
-*    Re-organized the CMSIS folders and updated documentation.   
-*    
-* Version 1.0.2 2010/11/11   
-*    Documentation updated.    
-*   
-* Version 1.0.1 2010/10/05    
-*    Production release and review comments incorporated.   
-*   
-* Version 1.0.0 2010/09/20    
-*    Production release and review comments incorporated   
-*   
-* Version 0.0.7  2010/06/10    
-*    Misra-C changes done   
-*   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**   
- * @ingroup groupFilters   
- */
-
-/**   
- * @addtogroup Conv   
- * @{   
- */
-
-/**   
- * @brief Convolution of Q15 sequences.   
- * @param[in] *pSrcA points to the first input sequence.   
- * @param[in] srcALen length of the first input sequence.   
- * @param[in] *pSrcB points to the second input sequence.   
- * @param[in] srcBLen length of the second input sequence.   
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   
- * @return none.   
- *   
- * @details   
- * Scaling and Overflow Behavior:   
- *   
- * \par   
- * The function is implemented using a 64-bit internal accumulator.   
- * Both inputs are in 1.15 format and multiplications yield a 2.30 result.   
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
- * This approach provides 33 guard bits and there is no risk of overflow.   
- * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.   
- *   
- * \par   
- * Refer to arm_conv_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4. 
- *
- * \par    
- * Refer the function arm_conv_opt_q15() for a faster implementation of this function using scratch buffers.
- *  
- */
-
-void arm_conv_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst)
-{
-
-#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q15_t *pIn1;                                   /* inputA pointer */
-  q15_t *pIn2;                                   /* inputB pointer */
-  q15_t *pOut = pDst;                            /* output pointer */
-  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
-  q15_t *px;                                     /* Intermediate inputA pointer  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
-  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
-  uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt;     /* loop counter */
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcA;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcB;
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcB;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcA;
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-  }
-
-  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
-  /* The function is internally   
-   * divided into three stages according to the number of multiplications that has to be   
-   * taken place between inputA samples and inputB samples. In the first stage of the   
-   * algorithm, the multiplications increase by one for every iteration.   
-   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
-   * In the third stage of the algorithm, the multiplications decrease by one   
-   * for every iteration. */
-
-  /* The algorithm is implemented in three stages.   
-     The loop counters of each stage is initiated here. */
-  blockSize1 = srcBLen - 1u;
-  blockSize2 = srcALen - (srcBLen - 1u);
-
-  /* --------------------------   
-   * Initializations of stage1   
-   * -------------------------*/
-
-  /* sum = x[0] * y[0]   
-   * sum = x[0] * y[1] + x[1] * y[0]   
-   * ....   
-   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
-   */
-
-  /* In this stage the MAC operations are increased by 1 for every iteration.   
-     The count variable holds the number of MAC operations performed */
-  count = 1u;
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-
-  /* ------------------------   
-   * Stage1 process   
-   * ----------------------*/
-
-  /* For loop unrolling by 4, this stage is divided into two. */
-  /* First part of this stage computes the MAC operations less than 4 */
-  /* Second part of this stage computes the MAC operations greater than or equal to 4 */
-
-  /* The first part of the stage starts here */
-  while((count < 4u) && (blockSize1 > 0u))
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Loop over number of MAC operations between   
-     * inputA samples and inputB samples */
-    k = count;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      sum = __SMLALD(*px++, *py--, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pIn2 + count;
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* The second part of the stage starts here */
-  /* The internal loop, over count, is unrolled by 4 */
-  /* To, read the last two inputB samples using SIMD:   
-   * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
-  py = py - 1;
-
-  while(blockSize1 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
-      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-      /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
-      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* For the next MAC operations, the pointer py is used without SIMD   
-     * So, py is incremented by 1 */
-    py = py + 1u;
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      sum = __SMLALD(*px++, *py--, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pIn2 + (count - 1u);
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* --------------------------   
-   * Initializations of stage2   
-   * ------------------------*/
-
-  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
-   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
-   * ....   
-   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
-   */
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  pSrc2 = pIn2 + (srcBLen - 1u);
-  py = pSrc2;
-
-  /* count is the index by which the pointer pIn1 to be incremented */
-  count = 0u;
-
-
-  /* --------------------   
-   * Stage2 process   
-   * -------------------*/
-
-  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
-   * So, to loop unroll over blockSize2,   
-   * srcBLen should be greater than or equal to 4 */
-  if(srcBLen >= 4u)
-  {
-    /* Loop unroll over blockSize2, by 4 */
-    blkCnt = blockSize2 >> 2u;
-
-    while(blkCnt > 0u)
-    {
-      py = py - 1u;
-
-      /* Set all accumulators to zero */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-
-      /* read x[0], x[1] samples */
-      x0 = *__SIMD32(px);
-      /* read x[1], x[2] samples */
-      x1 = _SIMD32_OFFSET(px+1);
-	  px+= 2u;
-
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      do
-      {
-        /* Read the last two inputB samples using SIMD:   
-         * y[srcBLen - 1] and y[srcBLen - 2] */
-        c0 = *__SIMD32(py)--;
-
-        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
-        acc0 = __SMLALDX(x0, c0, acc0);
-
-        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
-        acc1 = __SMLALDX(x1, c0, acc1);
-
-        /* Read x[2], x[3] */
-        x2 = *__SIMD32(px);
-
-        /* Read x[3], x[4] */
-        x3 = _SIMD32_OFFSET(px+1);
-
-        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
-        acc2 = __SMLALDX(x2, c0, acc2);
-
-        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
-        acc3 = __SMLALDX(x3, c0, acc3);
-
-        /* Read y[srcBLen - 3] and y[srcBLen - 4] */
-        c0 = *__SIMD32(py)--;
-
-        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
-        acc0 = __SMLALDX(x2, c0, acc0);
-
-        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
-        acc1 = __SMLALDX(x3, c0, acc1);
-
-        /* Read x[4], x[5] */
-        x0 = _SIMD32_OFFSET(px+2);
-
-        /* Read x[5], x[6] */
-        x1 = _SIMD32_OFFSET(px+3);
-		px += 4u;
-
-        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
-        acc2 = __SMLALDX(x0, c0, acc2);
-
-        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
-        acc3 = __SMLALDX(x1, c0, acc3);
-
-      } while(--k);
-
-      /* For the next MAC operations, SIMD is not used   
-       * So, the 16 bit pointer if inputB, py is updated */
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      if(k == 1u)
-      {
-        /* Read y[srcBLen - 5] */
-        c0 = *(py+1);
-
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-
-#else
-
-        c0 = c0 & 0x0000FFFF;
-
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-        /* Read x[7] */
-        x3 = *__SIMD32(px);
-		px++;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLALD(x0, c0, acc0);
-        acc1 = __SMLALD(x1, c0, acc1);
-        acc2 = __SMLALDX(x1, c0, acc2);
-        acc3 = __SMLALDX(x3, c0, acc3);
-      }
-
-      if(k == 2u)
-      {
-        /* Read y[srcBLen - 5], y[srcBLen - 6] */
-        c0 = _SIMD32_OFFSET(py);
-
-        /* Read x[7], x[8] */
-        x3 = *__SIMD32(px);
-
-        /* Read x[9] */
-        x2 = _SIMD32_OFFSET(px+1);
-		px += 2u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLALDX(x0, c0, acc0);
-        acc1 = __SMLALDX(x1, c0, acc1);
-        acc2 = __SMLALDX(x3, c0, acc2);
-        acc3 = __SMLALDX(x2, c0, acc3);
-      }
-
-      if(k == 3u)
-      {
-        /* Read y[srcBLen - 5], y[srcBLen - 6] */
-        c0 = _SIMD32_OFFSET(py);
-
-        /* Read x[7], x[8] */
-        x3 = *__SIMD32(px);
-
-        /* Read x[9] */
-        x2 = _SIMD32_OFFSET(px+1);
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLALDX(x0, c0, acc0);
-        acc1 = __SMLALDX(x1, c0, acc1);
-        acc2 = __SMLALDX(x3, c0, acc2);
-        acc3 = __SMLALDX(x2, c0, acc3);
-
-		c0 = *(py-1);
-
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-#else
-
-        c0 = c0 & 0x0000FFFF;
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-        /* Read x[10] */
-        x3 =  _SIMD32_OFFSET(px+2);
-		px += 3u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLALDX(x1, c0, acc0);
-        acc1 = __SMLALD(x2, c0, acc1);
-        acc2 = __SMLALDX(x2, c0, acc2);
-        acc3 = __SMLALDX(x3, c0, acc3);
-      }
-
-
-      /* Store the results in the accumulators in the destination buffer. */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
-
-#else
-
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
-      *__SIMD32(pOut)++ =
-        __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-      /* Increment the pointer pIn1 index, count by 4 */
-      count += 4u;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-       /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
-     ** No loop unrolling is used. */
-    blkCnt = blockSize2 % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += (q63_t) ((q31_t) * px++ * *py--);
-        sum += (q63_t) ((q31_t) * px++ * *py--);
-        sum += (q63_t) ((q31_t) * px++ * *py--);
-        sum += (q63_t) ((q31_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += (q63_t) ((q31_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
-
-      /* Increment the pointer pIn1 index, count by 1 */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-  else
-  {
-    /* If the srcBLen is not a multiple of 4,   
-     * the blockSize2 loop cannot be unrolled by 4 */
-    blkCnt = blockSize2;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* srcBLen number of MACS should be performed */
-      k = srcBLen;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += (q63_t) ((q31_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-
-
-  /* --------------------------   
-   * Initializations of stage3   
-   * -------------------------*/
-
-  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
-   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
-   * ....   
-   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
-   * sum +=  x[srcALen-1] * y[srcBLen-1]   
-   */
-
-  /* In this stage the MAC operations are decreased by 1 for every iteration.   
-     The blockSize3 variable holds the number of MAC operations performed */
-
-  blockSize3 = srcBLen - 1u;
-
-  /* Working pointer of inputA */
-  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-  px = pSrc1;
-
-  /* Working pointer of inputB */
-  pSrc2 = pIn2 + (srcBLen - 1u);
-  pIn2 = pSrc2 - 1u;
-  py = pIn2;
-
-  /* -------------------   
-   * Stage3 process   
-   * ------------------*/
-
-  /* For loop unrolling by 4, this stage is divided into two. */
-  /* First part of this stage computes the MAC operations greater than 4 */
-  /* Second part of this stage computes the MAC operations less than or equal to 4 */
-
-  /* The first part of the stage starts here */
-  j = blockSize3 >> 2u;
-
-  while((j > 0u) && (blockSize3 > 0u))
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = blockSize3 >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   
-       * with y[srcBLen - 1], y[srcBLen - 2] respectively */
-      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-      /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   
-       * with y[srcBLen - 3], y[srcBLen - 4] respectively */
-      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* For the next MAC operations, the pointer py is used without SIMD   
-     * So, py is incremented by 1 */
-    py = py + 1u;
-
-    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = blockSize3 % 0x4u;
-
-    while(k > 0u)
-    {
-      /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
-      sum = __SMLALD(*px++, *py--, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pIn2;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-
-    j--;
-  }
-
-  /* The second part of the stage starts here */
-  /* SIMD is not used for the next MAC operations,   
-   * so pointer py is updated to read only one sample at a time */
-  py = py + 1u;
-
-  while(blockSize3 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = blockSize3;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* sum +=  x[srcALen-1] * y[srcBLen-1] */
-      sum = __SMLALD(*px++, *py--, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pSrc2;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-  }
-
-#else
-
-/* Run the below code for Cortex-M0 */
-
-  q15_t *pIn1 = pSrcA;                           /* input pointer */
-  q15_t *pIn2 = pSrcB;                           /* coefficient pointer */
-  q63_t sum;                                     /* Accumulator */
-  uint32_t i, j;                                 /* loop counter */
-
-  /* Loop to calculate output of convolution for output length number of times */
-  for (i = 0; i < (srcALen + srcBLen - 1); i++)
-  {
-    /* Initialize sum with zero to carry on MAC operations */
-    sum = 0;
-
-    /* Loop to perform MAC operations according to convolution equation */
-    for (j = 0; j <= i; j++)
-    {
-      /* Check the array limitations */
-      if(((i - j) < srcBLen) && (j < srcALen))
-      {
-        /* z[i] += x[i-j] * y[j] */
-        sum += (q31_t) pIn1[j] * (pIn2[i - j]);
-      }
-    }
-
-    /* Store the output in the destination buffer */
-    pDst[i] = (q15_t) __SSAT((sum >> 15u), 16u);
-  }
-
-#endif /*  #if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)*/
-
-}
-
-/**   
- * @} end of Conv group   
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q31.c
deleted file mode 100644
index 713ea1bd47..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q31.c
+++ /dev/null
@@ -1,564 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_conv_q31.c    
-*    
-* Description:	Convolution of Q31 sequences.  
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-* 
-* Version 1.0.11 2011/10/18  
-*    Bug Fix in conv, correlation, partial convolution.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-*    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup Conv    
- * @{    
- */
-
-/**    
- * @brief Convolution of Q31 sequences.    
- * @param[in] *pSrcA points to the first input sequence.    
- * @param[in] srcALen length of the first input sequence.    
- * @param[in] *pSrcB points to the second input sequence.    
- * @param[in] srcBLen length of the second input sequence.    
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The function is implemented using an internal 64-bit accumulator.    
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
- * There is no saturation on intermediate additions.    
- * Thus, if the accumulator overflows it wraps around and distorts the result.    
- * The input signals should be scaled down to avoid intermediate overflows.    
- * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,    
- * as maximum of min(srcALen, srcBLen) number of additions are carried internally.    
- * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.    
- *    
- * \par    
- * See arm_conv_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.    
- */
-
-void arm_conv_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst)
-{
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t *pIn1;                                   /* inputA pointer */
-  q31_t *pIn2;                                   /* inputB pointer */
-  q31_t *pOut = pDst;                            /* output pointer */
-  q31_t *px;                                     /* Intermediate inputA pointer  */
-  q31_t *py;                                     /* Intermediate inputB pointer  */
-  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
-  q63_t sum;                                     /* Accumulator */
-  q63_t acc0, acc1, acc2;                        /* Accumulator */
-  q31_t x0, x1, x2, c0;                          /* Temporary variables to hold state and coefficient values */
-  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counter */
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcA;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcB;
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (q31_t *) pSrcB;
-
-    /* Initialization of inputB pointer */
-    pIn2 = (q31_t *) pSrcA;
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-  }
-
-  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
-  /* The function is internally    
-   * divided into three stages according to the number of multiplications that has to be    
-   * taken place between inputA samples and inputB samples. In the first stage of the    
-   * algorithm, the multiplications increase by one for every iteration.    
-   * In the second stage of the algorithm, srcBLen number of multiplications are done.    
-   * In the third stage of the algorithm, the multiplications decrease by one    
-   * for every iteration. */
-
-  /* The algorithm is implemented in three stages.    
-     The loop counters of each stage is initiated here. */
-  blockSize1 = srcBLen - 1u;
-  blockSize2 = srcALen - (srcBLen - 1u);
-  blockSize3 = blockSize1;
-
-  /* --------------------------    
-   * Initializations of stage1    
-   * -------------------------*/
-
-  /* sum = x[0] * y[0]    
-   * sum = x[0] * y[1] + x[1] * y[0]    
-   * ....    
-   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]    
-   */
-
-  /* In this stage the MAC operations are increased by 1 for every iteration.    
-     The count variable holds the number of MAC operations performed */
-  count = 1u;
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-
-  /* ------------------------    
-   * Stage1 process    
-   * ----------------------*/
-
-  /* The first stage starts here */
-  while(blockSize1 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* x[0] * y[srcBLen - 1] */
-      sum += (q63_t) * px++ * (*py--);
-      /* x[1] * y[srcBLen - 2] */
-      sum += (q63_t) * px++ * (*py--);
-      /* x[2] * y[srcBLen - 3] */
-      sum += (q63_t) * px++ * (*py--);
-      /* x[3] * y[srcBLen - 4] */
-      sum += (q63_t) * px++ * (*py--);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.    
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      sum += (q63_t) * px++ * (*py--);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q31_t) (sum >> 31);
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pIn2 + count;
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* --------------------------    
-   * Initializations of stage2    
-   * ------------------------*/
-
-  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]    
-   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]    
-   * ....    
-   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]    
-   */
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  pSrc2 = pIn2 + (srcBLen - 1u);
-  py = pSrc2;
-
-  /* count is index by which the pointer pIn1 to be incremented */
-  count = 0u;
-
-  /* -------------------    
-   * Stage2 process    
-   * ------------------*/
-
-  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
-   * So, to loop unroll over blockSize2,    
-   * srcBLen should be greater than or equal to 4 */
-  if(srcBLen >= 4u)
-  {
-    /* Loop unroll by 3 */
-    blkCnt = blockSize2 / 3;
-
-    while(blkCnt > 0u)
-    {
-      /* Set all accumulators to zero */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-
-      /* read x[0], x[1], x[2] samples */
-      x0 = *(px++);
-      x1 = *(px++);
-
-      /* Apply loop unrolling and compute 3 MACs simultaneously. */
-      k = srcBLen / 3;
-
-      /* First part of the processing with loop unrolling.  Compute 3 MACs at a time.        
-       ** a second loop below computes MACs for the remaining 1 to 2 samples. */
-      do
-      {
-        /* Read y[srcBLen - 1] sample */
-        c0 = *(py);
-
-        /* Read x[3] sample */
-        x2 = *(px);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[0] * y[srcBLen - 1] */
-        acc0 += ((q63_t) x0 * c0);
-        /* acc1 +=  x[1] * y[srcBLen - 1] */
-        acc1 += ((q63_t) x1 * c0);
-        /* acc2 +=  x[2] * y[srcBLen - 1] */
-        acc2 += ((q63_t) x2 * c0);
-
-        /* Read y[srcBLen - 2] sample */
-        c0 = *(py - 1u);
-
-        /* Read x[4] sample */
-        x0 = *(px + 1u);
-
-        /* Perform the multiply-accumulate */
-        /* acc0 +=  x[1] * y[srcBLen - 2] */
-        acc0 += ((q63_t) x1 * c0);
-        /* acc1 +=  x[2] * y[srcBLen - 2] */
-        acc1 += ((q63_t) x2 * c0);
-        /* acc2 +=  x[3] * y[srcBLen - 2] */
-        acc2 += ((q63_t) x0 * c0);
-
-        /* Read y[srcBLen - 3] sample */
-        c0 = *(py - 2u);
-
-        /* Read x[5] sample */
-        x1 = *(px + 2u);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[2] * y[srcBLen - 3] */
-        acc0 += ((q63_t) x2 * c0);
-        /* acc1 +=  x[3] * y[srcBLen - 2] */
-        acc1 += ((q63_t) x0 * c0);
-        /* acc2 +=  x[4] * y[srcBLen - 2] */
-        acc2 += ((q63_t) x1 * c0);
-
-        /* update scratch pointers */
-        px += 3u;
-        py -= 3u;
-
-      } while(--k);
-
-      /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.        
-       ** No loop unrolling is used. */
-      k = srcBLen - (3 * (srcBLen / 3));
-
-      while(k > 0u)
-      {
-        /* Read y[srcBLen - 5] sample */
-        c0 = *(py--);
-
-        /* Read x[7] sample */
-        x2 = *(px++);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[4] * y[srcBLen - 5] */
-        acc0 += ((q63_t) x0 * c0);
-        /* acc1 +=  x[5] * y[srcBLen - 5] */
-        acc1 += ((q63_t) x1 * c0);
-        /* acc2 +=  x[6] * y[srcBLen - 5] */
-        acc2 += ((q63_t) x2 * c0);
-
-        /* Reuse the present samples for the next MAC */
-        x0 = x1;
-        x1 = x2;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the results in the accumulators in the destination buffer. */
-      *pOut++ = (q31_t) (acc0 >> 31);
-      *pOut++ = (q31_t) (acc1 >> 31);
-      *pOut++ = (q31_t) (acc2 >> 31);
-
-      /* Increment the pointer pIn1 index, count by 3 */
-      count += 3u;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.        
-     ** No loop unrolling is used. */
-    blkCnt = blockSize2 - 3 * (blockSize2 / 3);
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += (q63_t) * px++ * (*py--);
-        sum += (q63_t) * px++ * (*py--);
-        sum += (q63_t) * px++ * (*py--);
-        sum += (q63_t) * px++ * (*py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += (q63_t) * px++ * (*py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q31_t) (sum >> 31);
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-  else
-  {
-    /* If the srcBLen is not a multiple of 4,    
-     * the blockSize2 loop cannot be unrolled by 4 */
-    blkCnt = blockSize2;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* srcBLen number of MACS should be performed */
-      k = srcBLen;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += (q63_t) * px++ * (*py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q31_t) (sum >> 31);
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-
-
-  /* --------------------------    
-   * Initializations of stage3    
-   * -------------------------*/
-
-  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]    
-   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]    
-   * ....    
-   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]    
-   * sum +=  x[srcALen-1] * y[srcBLen-1]    
-   */
-
-  /* In this stage the MAC operations are decreased by 1 for every iteration.    
-     The blockSize3 variable holds the number of MAC operations performed */
-
-  /* Working pointer of inputA */
-  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-  px = pSrc1;
-
-  /* Working pointer of inputB */
-  pSrc2 = pIn2 + (srcBLen - 1u);
-  py = pSrc2;
-
-  /* -------------------    
-   * Stage3 process    
-   * ------------------*/
-
-  while(blockSize3 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = blockSize3 >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
-      sum += (q63_t) * px++ * (*py--);
-      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
-      sum += (q63_t) * px++ * (*py--);
-      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
-      sum += (q63_t) * px++ * (*py--);
-      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
-      sum += (q63_t) * px++ * (*py--);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.    
-     ** No loop unrolling is used. */
-    k = blockSize3 % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      sum += (q63_t) * px++ * (*py--);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q31_t) (sum >> 31);
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pSrc2;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q31_t *pIn1 = pSrcA;                           /* input pointer */
-  q31_t *pIn2 = pSrcB;                           /* coefficient pointer */
-  q63_t sum;                                     /* Accumulator */
-  uint32_t i, j;                                 /* loop counter */
-
-  /* Loop to calculate output of convolution for output length number of times */
-  for (i = 0; i < (srcALen + srcBLen - 1); i++)
-  {
-    /* Initialize sum with zero to carry on MAC operations */
-    sum = 0;
-
-    /* Loop to perform MAC operations according to convolution equation */
-    for (j = 0; j <= i; j++)
-    {
-      /* Check the array limitations */
-      if(((i - j) < srcBLen) && (j < srcALen))
-      {
-        /* z[i] += x[i-j] * y[j] */
-        sum += ((q63_t) pIn1[j] * (pIn2[i - j]));
-      }
-    }
-
-    /* Store the output in the destination buffer */
-    pDst[i] = (q31_t) (sum >> 31u);
-  }
-
-#endif /*     #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
- * @} end of Conv group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q7.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q7.c
deleted file mode 100644
index 9fc7e4044f..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q7.c
+++ /dev/null
@@ -1,689 +0,0 @@
-/* ----------------------------------------------------------------------   
-* Copyright (C) 2010 ARM Limited. All rights reserved.   
-*   
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*   
-* Project: 	    CMSIS DSP Library   
-* Title:		arm_conv_q7.c   
-*   
-* Description:	Convolution of Q7 sequences. 
-*   
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*  
-* Version 1.0.11 2011/10/18 
-*    Bug Fix in conv, correlation, partial convolution. 
-*
-* Version 1.0.10 2011/7/15 
-*    Big Endian support added and Merged M0 and M3/M4 Source code.  
-*   
-* Version 1.0.3 2010/11/29  
-*    Re-organized the CMSIS folders and updated documentation.   
-*    
-* Version 1.0.2 2010/11/11   
-*    Documentation updated.    
-*   
-* Version 1.0.1 2010/10/05    
-*    Production release and review comments incorporated.   
-*   
-* Version 1.0.0 2010/09/20    
-*    Production release and review comments incorporated   
-*   
-* Version 0.0.7  2010/06/10    
-*    Misra-C changes done   
-*   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**   
- * @ingroup groupFilters   
- */
-
-/**   
- * @addtogroup Conv   
- * @{   
- */
-
-/**   
- * @brief Convolution of Q7 sequences.   
- * @param[in] *pSrcA points to the first input sequence.   
- * @param[in] srcALen length of the first input sequence.   
- * @param[in] *pSrcB points to the second input sequence.   
- * @param[in] srcBLen length of the second input sequence.   
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   
- * @return none.   
- *   
- * @details   
- * Scaling and Overflow Behavior:   
- *   
- * \par   
- * The function is implemented using a 32-bit internal accumulator.   
- * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.   
- * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.   
- * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.   
- * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.   
- *
- * \par    
- * Refer the function arm_conv_opt_q7() for a faster implementation of this function.
- * 
- */
-
-void arm_conv_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst)
-{
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q7_t *pIn1;                                    /* inputA pointer */
-  q7_t *pIn2;                                    /* inputB pointer */
-  q7_t *pOut = pDst;                             /* output pointer */
-  q7_t *px;                                      /* Intermediate inputA pointer */
-  q7_t *py;                                      /* Intermediate inputB pointer */
-  q7_t *pSrc1, *pSrc2;                           /* Intermediate pointers */
-  q7_t x0, x1, x2, x3, c0, c1;                   /* Temporary variables to hold state and coefficient values */
-  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
-  q31_t input1, input2;                          /* Temporary input variables */
-  q15_t in1, in2;                                /* Temporary input variables */
-  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counter */
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcA;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcB;
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcB;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcA;
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-  }
-
-  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
-  /* The function is internally   
-   * divided into three stages according to the number of multiplications that has to be   
-   * taken place between inputA samples and inputB samples. In the first stage of the   
-   * algorithm, the multiplications increase by one for every iteration.   
-   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
-   * In the third stage of the algorithm, the multiplications decrease by one   
-   * for every iteration. */
-
-  /* The algorithm is implemented in three stages.   
-     The loop counters of each stage is initiated here. */
-  blockSize1 = srcBLen - 1u;
-  blockSize2 = (srcALen - srcBLen) + 1u;
-  blockSize3 = blockSize1;
-
-  /* --------------------------   
-   * Initializations of stage1   
-   * -------------------------*/
-
-  /* sum = x[0] * y[0]   
-   * sum = x[0] * y[1] + x[1] * y[0]   
-   * ....   
-   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
-   */
-
-  /* In this stage the MAC operations are increased by 1 for every iteration.   
-     The count variable holds the number of MAC operations performed */
-  count = 1u;
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-
-  /* ------------------------   
-   * Stage1 process   
-   * ----------------------*/
-
-  /* The first stage starts here */
-  while(blockSize1 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* x[0] , x[1] */
-      in1 = (q15_t) * px++;
-      in2 = (q15_t) * px++;
-      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-      /* y[srcBLen - 1] , y[srcBLen - 2] */
-      in1 = (q15_t) * py--;
-      in2 = (q15_t) * py--;
-      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-      /* x[0] * y[srcBLen - 1] */
-      /* x[1] * y[srcBLen - 2] */
-      sum = __SMLAD(input1, input2, sum);
-
-      /* x[2] , x[3] */
-      in1 = (q15_t) * px++;
-      in2 = (q15_t) * px++;
-      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-      /* y[srcBLen - 3] , y[srcBLen - 4] */
-      in1 = (q15_t) * py--;
-      in2 = (q15_t) * py--;
-      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-      /* x[2] * y[srcBLen - 3] */
-      /* x[3] * y[srcBLen - 4] */
-      sum = __SMLAD(input1, input2, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      sum += ((q15_t) * px++ * *py--);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pIn2 + count;
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* --------------------------   
-   * Initializations of stage2   
-   * ------------------------*/
-
-  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
-   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
-   * ....   
-   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
-   */
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  pSrc2 = pIn2 + (srcBLen - 1u);
-  py = pSrc2;
-
-  /* count is index by which the pointer pIn1 to be incremented */
-  count = 0u;
-
-  /* -------------------   
-   * Stage2 process   
-   * ------------------*/
-
-  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
-   * So, to loop unroll over blockSize2,   
-   * srcBLen should be greater than or equal to 4 */
-  if(srcBLen >= 4u)
-  {
-    /* Loop unroll over blockSize2, by 4 */
-    blkCnt = blockSize2 >> 2u;
-
-    while(blkCnt > 0u)
-    {
-      /* Set all accumulators to zero */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-      /* read x[0], x[1], x[2] samples */
-      x0 = *(px++);
-      x1 = *(px++);
-      x2 = *(px++);
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      do
-      {
-        /* Read y[srcBLen - 1] sample */
-        c0 = *(py--);
-        /* Read y[srcBLen - 2] sample */
-        c1 = *(py--);
-
-        /* Read x[3] sample */
-        x3 = *(px++);
-
-        /* x[0] and x[1] are packed */
-        in1 = (q15_t) x0;
-        in2 = (q15_t) x1;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-        /* y[srcBLen - 1]   and y[srcBLen - 2] are packed */
-        in1 = (q15_t) c0;
-        in2 = (q15_t) c1;
-
-        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-        /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2]  */
-        acc0 = __SMLAD(input1, input2, acc0);
-
-        /* x[1] and x[2] are packed */
-        in1 = (q15_t) x1;
-        in2 = (q15_t) x2;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-        /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2]  */
-        acc1 = __SMLAD(input1, input2, acc1);
-
-        /* x[2] and x[3] are packed */
-        in1 = (q15_t) x2;
-        in2 = (q15_t) x3;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-        /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2]  */
-        acc2 = __SMLAD(input1, input2, acc2);
-
-        /* Read x[4] sample */
-        x0 = *(px++);
-
-        /* x[3] and x[4] are packed */
-        in1 = (q15_t) x3;
-        in2 = (q15_t) x0;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-        /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2]  */
-        acc3 = __SMLAD(input1, input2, acc3);
-
-        /* Read y[srcBLen - 3] sample */
-        c0 = *(py--);
-        /* Read y[srcBLen - 4] sample */
-        c1 = *(py--);
-
-        /* Read x[5] sample */
-        x1 = *(px++);
-
-        /* x[2] and x[3] are packed */
-        in1 = (q15_t) x2;
-        in2 = (q15_t) x3;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-        /* y[srcBLen - 3] and y[srcBLen - 4] are packed */
-        in1 = (q15_t) c0;
-        in2 = (q15_t) c1;
-
-        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-        /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4]  */
-        acc0 = __SMLAD(input1, input2, acc0);
-
-        /* x[3] and x[4] are packed */
-        in1 = (q15_t) x3;
-        in2 = (q15_t) x0;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-        /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4]  */
-        acc1 = __SMLAD(input1, input2, acc1);
-
-        /* x[4] and x[5] are packed */
-        in1 = (q15_t) x0;
-        in2 = (q15_t) x1;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-        /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4]  */
-        acc2 = __SMLAD(input1, input2, acc2);
-
-        /* Read x[6] sample */
-        x2 = *(px++);
-
-        /* x[5] and x[6] are packed */
-        in1 = (q15_t) x1;
-        in2 = (q15_t) x2;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-        /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4]  */
-        acc3 = __SMLAD(input1, input2, acc3);
-
-      } while(--k);
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Read y[srcBLen - 5] sample */
-        c0 = *(py--);
-
-        /* Read x[7] sample */
-        x3 = *(px++);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[4] * y[srcBLen - 5] */
-        acc0 += ((q15_t) x0 * c0);
-        /* acc1 +=  x[5] * y[srcBLen - 5] */
-        acc1 += ((q15_t) x1 * c0);
-        /* acc2 +=  x[6] * y[srcBLen - 5] */
-        acc2 += ((q15_t) x2 * c0);
-        /* acc3 +=  x[7] * y[srcBLen - 5] */
-        acc3 += ((q15_t) x3 * c0);
-
-        /* Reuse the present samples for the next MAC */
-        x0 = x1;
-        x1 = x2;
-        x2 = x3;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
-      *pOut++ = (q7_t) (__SSAT(acc1 >> 7u, 8));
-      *pOut++ = (q7_t) (__SSAT(acc2 >> 7u, 8));
-      *pOut++ = (q7_t) (__SSAT(acc3 >> 7u, 8));
-
-      /* Increment the pointer pIn1 index, count by 4 */
-      count += 4u;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
-     ** No loop unrolling is used. */
-    blkCnt = blockSize2 % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-
-        /* Reading two inputs of SrcA buffer and packing */
-        in1 = (q15_t) * px++;
-        in2 = (q15_t) * px++;
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-        /* Reading two inputs of SrcB buffer and packing */
-        in1 = (q15_t) * py--;
-        in2 = (q15_t) * py--;
-        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-        /* Perform the multiply-accumulates */
-        sum = __SMLAD(input1, input2, sum);
-
-        /* Reading two inputs of SrcA buffer and packing */
-        in1 = (q15_t) * px++;
-        in2 = (q15_t) * px++;
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-        /* Reading two inputs of SrcB buffer and packing */
-        in1 = (q15_t) * py--;
-        in2 = (q15_t) * py--;
-        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-        /* Perform the multiply-accumulates */
-        sum = __SMLAD(input1, input2, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += ((q15_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
-
-      /* Increment the pointer pIn1 index, count by 1 */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-  else
-  {
-    /* If the srcBLen is not a multiple of 4,   
-     * the blockSize2 loop cannot be unrolled by 4 */
-    blkCnt = blockSize2;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* srcBLen number of MACS should be performed */
-      k = srcBLen;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += ((q15_t) * px++ * *py--);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pSrc2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-
-
-  /* --------------------------   
-   * Initializations of stage3   
-   * -------------------------*/
-
-  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
-   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
-   * ....   
-   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
-   * sum +=  x[srcALen-1] * y[srcBLen-1]   
-   */
-
-  /* In this stage the MAC operations are decreased by 1 for every iteration.   
-     The blockSize3 variable holds the number of MAC operations performed */
-
-  /* Working pointer of inputA */
-  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
-  px = pSrc1;
-
-  /* Working pointer of inputB */
-  pSrc2 = pIn2 + (srcBLen - 1u);
-  py = pSrc2;
-
-  /* -------------------   
-   * Stage3 process   
-   * ------------------*/
-
-  while(blockSize3 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = blockSize3 >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */
-      in1 = (q15_t) * px++;
-      in2 = (q15_t) * px++;
-      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-      /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */
-      in1 = (q15_t) * py--;
-      in2 = (q15_t) * py--;
-      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
-      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
-      sum = __SMLAD(input1, input2, sum);
-
-      /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */
-      in1 = (q15_t) * px++;
-      in2 = (q15_t) * px++;
-      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-      /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */
-      in1 = (q15_t) * py--;
-      in2 = (q15_t) * py--;
-      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
-
-      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
-      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
-      sum = __SMLAD(input1, input2, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = blockSize3 % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      sum += ((q15_t) * px++ * *py--);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pSrc2;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q7_t *pIn1 = pSrcA;                            /* input pointer */
-  q7_t *pIn2 = pSrcB;                            /* coefficient pointer */
-  q31_t sum;                                     /* Accumulator */
-  uint32_t i, j;                                 /* loop counter */
-
-  /* Loop to calculate output of convolution for output length number of times */
-  for (i = 0; i < (srcALen + srcBLen - 1); i++)
-  {
-    /* Initialize sum with zero to carry on MAC operations */
-    sum = 0;
-
-    /* Loop to perform MAC operations according to convolution equation */
-    for (j = 0; j <= i; j++)
-    {
-      /* Check the array limitations */
-      if(((i - j) < srcBLen) && (j < srcALen))
-      {
-        /* z[i] += x[i-j] * y[j] */
-        sum += (q15_t) pIn1[j] * (pIn2[i - j]);
-      }
-    }
-
-    /* Store the output in the destination buffer */
-    pDst[i] = (q7_t) __SSAT((sum >> 7u), 8u);
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0        */
-
-}
-
-/**   
- * @} end of Conv group   
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_f32.c
deleted file mode 100644
index 317950ec49..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_f32.c
+++ /dev/null
@@ -1,738 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_correlate_f32.c    
-*    
-* Description:	 Correlation of floating-point sequences.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-* 
-* Version 1.0.11 2011/10/18  
-*    Bug Fix in conv, correlation, partial convolution.  
-* 
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-*    
-* -------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @defgroup Corr Correlation    
- *    
- * Correlation is a mathematical operation that is similar to convolution.    
- * As with convolution, correlation uses two signals to produce a third signal.    
- * The underlying algorithms in correlation and convolution are identical except that one of the inputs is flipped in convolution.    
- * Correlation is commonly used to measure the similarity between two signals.    
- * It has applications in pattern recognition, cryptanalysis, and searching.    
- * The CMSIS library provides correlation functions for Q7, Q15, Q31 and floating-point data types.    
- * Fast versions of the Q15 and Q31 functions are also provided.    
- *    
- * \par Algorithm    
- * Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively.    
- * The convolution of the two signals is denoted by    
- * 
    
- *                   c[n] = a[n] * b[n]    
- * 
    
- * In correlation, one of the signals is flipped in time    
- * 
    
- *                   c[n] = a[n] * b[-n]    
- * 
    
- *    
- * \par    
- * and this is mathematically defined as    
- * \image html CorrelateEquation.gif    
- * \par    
- * The pSrcA points to the first input vector of length srcALen and pSrcB points to the second input vector of length srcBLen.    
- * The result c[n] is of length 2 * max(srcALen, srcBLen) - 1 and is defined over the interval n=0, 1, 2, ..., (2 * max(srcALen, srcBLen) - 2).    
- * The output result is written to pDst and the calling function must allocate 2 * max(srcALen, srcBLen) - 1 words for the result.    
- *    
- * Note   
- * \par  
- * The pDst should be initialized to all zeros before being used.  
- *  
- * Fixed-Point Behavior    
- * \par    
- * Correlation requires summing up a large number of intermediate products.    
- * As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation.    
- * Refer to the function specific documentation below for further details of the particular algorithm used.    
- *
- *
- * Fast Versions
- *
- * \par 
- * Fast versions are supported for Q31 and Q15.  Cycles for Fast versions are less compared to Q31 and Q15 of correlate and the design requires
- * the input signals should be scaled down to avoid intermediate overflows.   
- *
- *
- * Opt Versions
- *
- * \par 
- * Opt versions are supported for Q15 and Q7.  Design uses internal scratch buffer for getting good optimisation.
- * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions of correlate 
- */
-
-/**    
- * @addtogroup Corr    
- * @{    
- */
-/**    
- * @brief Correlation of floating-point sequences.    
- * @param[in]  *pSrcA points to the first input sequence.    
- * @param[in]  srcALen length of the first input sequence.    
- * @param[in]  *pSrcB points to the second input sequence.    
- * @param[in]  srcBLen length of the second input sequence.    
- * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.    
- * @return none.    
- */
-
-void arm_correlate_f32(
-  float32_t * pSrcA,
-  uint32_t srcALen,
-  float32_t * pSrcB,
-  uint32_t srcBLen,
-  float32_t * pDst)
-{
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  float32_t *pIn1;                               /* inputA pointer */
-  float32_t *pIn2;                               /* inputB pointer */
-  float32_t *pOut = pDst;                        /* output pointer */
-  float32_t *px;                                 /* Intermediate inputA pointer */
-  float32_t *py;                                 /* Intermediate inputB pointer */
-  float32_t *pSrc1;                              /* Intermediate pointers */
-  float32_t sum, acc0, acc1, acc2, acc3;         /* Accumulators */
-  float32_t x0, x1, x2, x3, c0;                  /* temporary variables for holding input and coefficient values */
-  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counters */
-  int32_t inc = 1;                               /* Destination address modifier */
-
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  /* But CORR(x, y) is reverse of CORR(y, x) */
-  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
-  /* and the destination pointer modifier, inc is set to -1 */
-  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
-  /* But to improve the performance,    
-   * we include zeroes in the output instead of zero padding either of the the inputs*/
-  /* If srcALen > srcBLen,    
-   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
-  /* If srcALen < srcBLen,    
-   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcA;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcB;
-
-    /* Number of output samples is calculated */
-    outBlockSize = (2u * srcALen) - 1u;
-
-    /* When srcALen > srcBLen, zero padding has to be done to srcB    
-     * to make their lengths equal.    
-     * Instead, (outBlockSize - (srcALen + srcBLen - 1))    
-     * number of output samples are made zero */
-    j = outBlockSize - (srcALen + (srcBLen - 1u));
-
-    /* Updating the pointer position to non zero value */
-    pOut += j;
-
-    //while(j > 0u)   
-    //{   
-    //  /* Zero is stored in the destination buffer */   
-    //  *pOut++ = 0.0f;   
-
-    //  /* Decrement the loop counter */   
-    //  j--;   
-    //}   
-
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = pSrcB;
-
-    /* Initialization of inputB pointer */
-    pIn2 = pSrcA;
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-
-    /* CORR(x, y) = Reverse order(CORR(y, x)) */
-    /* Hence set the destination pointer to point to the last output sample */
-    pOut = pDst + ((srcALen + srcBLen) - 2u);
-
-    /* Destination address modifier is set to -1 */
-    inc = -1;
-
-  }
-
-  /* The function is internally    
-   * divided into three parts according to the number of multiplications that has to be    
-   * taken place between inputA samples and inputB samples. In the first part of the    
-   * algorithm, the multiplications increase by one for every iteration.    
-   * In the second part of the algorithm, srcBLen number of multiplications are done.    
-   * In the third part of the algorithm, the multiplications decrease by one    
-   * for every iteration.*/
-  /* The algorithm is implemented in three stages.    
-   * The loop counters of each stage is initiated here. */
-  blockSize1 = srcBLen - 1u;
-  blockSize2 = srcALen - (srcBLen - 1u);
-  blockSize3 = blockSize1;
-
-  /* --------------------------    
-   * Initializations of stage1    
-   * -------------------------*/
-
-  /* sum = x[0] * y[srcBlen - 1]    
-   * sum = x[0] * y[srcBlen-2] + x[1] * y[srcBlen - 1]    
-   * ....    
-   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]    
-   */
-
-  /* In this stage the MAC operations are increased by 1 for every iteration.    
-     The count variable holds the number of MAC operations performed */
-  count = 1u;
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  pSrc1 = pIn2 + (srcBLen - 1u);
-  py = pSrc1;
-
-  /* ------------------------    
-   * Stage1 process    
-   * ----------------------*/
-
-  /* The first stage starts here */
-  while(blockSize1 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0.0f;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* x[0] * y[srcBLen - 4] */
-      sum += *px++ * *py++;
-      /* x[1] * y[srcBLen - 3] */
-      sum += *px++ * *py++;
-      /* x[2] * y[srcBLen - 2] */
-      sum += *px++ * *py++;
-      /* x[3] * y[srcBLen - 1] */
-      sum += *px++ * *py++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.    
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      /* x[0] * y[srcBLen - 1] */
-      sum += *px++ * *py++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = sum;
-    /* Destination pointer is updated according to the address modifier, inc */
-    pOut += inc;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pSrc1 - count;
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* --------------------------    
-   * Initializations of stage2    
-   * ------------------------*/
-
-  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]    
-   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]    
-   * ....    
-   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
-   */
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-  /* count is index by which the pointer pIn1 to be incremented */
-  count = 0u;
-
-  /* -------------------    
-   * Stage2 process    
-   * ------------------*/
-
-  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
-   * So, to loop unroll over blockSize2,    
-   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
-  if(srcBLen >= 4u)
-  {
-    /* Loop unroll over blockSize2, by 4 */
-    blkCnt = blockSize2 >> 2u;
-
-    while(blkCnt > 0u)
-    {
-      /* Set all accumulators to zero */
-      acc0 = 0.0f;
-      acc1 = 0.0f;
-      acc2 = 0.0f;
-      acc3 = 0.0f;
-
-      /* read x[0], x[1], x[2] samples */
-      x0 = *(px++);
-      x1 = *(px++);
-      x2 = *(px++);
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      do
-      {
-        /* Read y[0] sample */
-        c0 = *(py++);
-
-        /* Read x[3] sample */
-        x3 = *(px++);
-
-        /* Perform the multiply-accumulate */
-        /* acc0 +=  x[0] * y[0] */
-        acc0 += x0 * c0;
-        /* acc1 +=  x[1] * y[0] */
-        acc1 += x1 * c0;
-        /* acc2 +=  x[2] * y[0] */
-        acc2 += x2 * c0;
-        /* acc3 +=  x[3] * y[0] */
-        acc3 += x3 * c0;
-
-        /* Read y[1] sample */
-        c0 = *(py++);
-
-        /* Read x[4] sample */
-        x0 = *(px++);
-
-        /* Perform the multiply-accumulate */
-        /* acc0 +=  x[1] * y[1] */
-        acc0 += x1 * c0;
-        /* acc1 +=  x[2] * y[1] */
-        acc1 += x2 * c0;
-        /* acc2 +=  x[3] * y[1] */
-        acc2 += x3 * c0;
-        /* acc3 +=  x[4] * y[1] */
-        acc3 += x0 * c0;
-
-        /* Read y[2] sample */
-        c0 = *(py++);
-
-        /* Read x[5] sample */
-        x1 = *(px++);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[2] * y[2] */
-        acc0 += x2 * c0;
-        /* acc1 +=  x[3] * y[2] */
-        acc1 += x3 * c0;
-        /* acc2 +=  x[4] * y[2] */
-        acc2 += x0 * c0;
-        /* acc3 +=  x[5] * y[2] */
-        acc3 += x1 * c0;
-
-        /* Read y[3] sample */
-        c0 = *(py++);
-
-        /* Read x[6] sample */
-        x2 = *(px++);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[3] * y[3] */
-        acc0 += x3 * c0;
-        /* acc1 +=  x[4] * y[3] */
-        acc1 += x0 * c0;
-        /* acc2 +=  x[5] * y[3] */
-        acc2 += x1 * c0;
-        /* acc3 +=  x[6] * y[3] */
-        acc3 += x2 * c0;
-
-
-      } while(--k);
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Read y[4] sample */
-        c0 = *(py++);
-
-        /* Read x[7] sample */
-        x3 = *(px++);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[4] * y[4] */
-        acc0 += x0 * c0;
-        /* acc1 +=  x[5] * y[4] */
-        acc1 += x1 * c0;
-        /* acc2 +=  x[6] * y[4] */
-        acc2 += x2 * c0;
-        /* acc3 +=  x[7] * y[4] */
-        acc3 += x3 * c0;
-
-        /* Reuse the present samples for the next MAC */
-        x0 = x1;
-        x1 = x2;
-        x2 = x3;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = acc0;
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      *pOut = acc1;
-      pOut += inc;
-
-      *pOut = acc2;
-      pOut += inc;
-
-      *pOut = acc3;
-      pOut += inc;
-
-      /* Increment the pointer pIn1 index, count by 4 */
-      count += 4u;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.    
-     ** No loop unrolling is used. */
-    blkCnt = blockSize2 % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0.0f;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += *px++ * *py++;
-        sum += *px++ * *py++;
-        sum += *px++ * *py++;
-        sum += *px++ * *py++;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += *px++ * *py++;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = sum;
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      /* Increment the pointer pIn1 index, count by 1 */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-  else
-  {
-    /* If the srcBLen is not a multiple of 4,    
-     * the blockSize2 loop cannot be unrolled by 4 */
-    blkCnt = blockSize2;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0.0f;
-
-      /* Loop over srcBLen */
-      k = srcBLen;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += *px++ * *py++;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = sum;
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      /* Increment the pointer pIn1 index, count by 1 */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-
-  /* --------------------------    
-   * Initializations of stage3    
-   * -------------------------*/
-
-  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
-   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
-   * ....    
-   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]    
-   * sum +=  x[srcALen-1] * y[0]    
-   */
-
-  /* In this stage the MAC operations are decreased by 1 for every iteration.    
-     The count variable holds the number of MAC operations performed */
-  count = srcBLen - 1u;
-
-  /* Working pointer of inputA */
-  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
-  px = pSrc1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-  /* -------------------    
-   * Stage3 process    
-   * ------------------*/
-
-  while(blockSize3 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0.0f;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* sum += x[srcALen - srcBLen + 4] * y[3] */
-      sum += *px++ * *py++;
-      /* sum += x[srcALen - srcBLen + 3] * y[2] */
-      sum += *px++ * *py++;
-      /* sum += x[srcALen - srcBLen + 2] * y[1] */
-      sum += *px++ * *py++;
-      /* sum += x[srcALen - srcBLen + 1] * y[0] */
-      sum += *px++ * *py++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.    
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      sum += *px++ * *py++;
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = sum;
-    /* Destination pointer is updated according to the address modifier, inc */
-    pOut += inc;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pIn2;
-
-    /* Decrement the MAC count */
-    count--;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
-  float32_t *pIn2 = pSrcB + (srcBLen - 1u);      /* inputB pointer */
-  float32_t sum;                                 /* Accumulator */
-  uint32_t i = 0u, j;                            /* loop counters */
-  uint32_t inv = 0u;                             /* Reverse order flag */
-  uint32_t tot = 0u;                             /* Length */
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  /* But CORR(x, y) is reverse of CORR(y, x) */
-  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
-  /* and a varaible, inv is set to 1 */
-  /* If lengths are not equal then zero pad has to be done to  make the two    
-   * inputs of same length. But to improve the performance, we include zeroes    
-   * in the output instead of zero padding either of the the inputs*/
-  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the    
-   * starting of the output buffer */
-  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the   
-   * ending of the output buffer */
-  /* Once the zero padding is done the remaining of the output is calcualted   
-   * using convolution but with the shorter signal time shifted. */
-
-  /* Calculate the length of the remaining sequence */
-  tot = ((srcALen + srcBLen) - 2u);
-
-  if(srcALen > srcBLen)
-  {
-    /* Calculating the number of zeros to be padded to the output */
-    j = srcALen - srcBLen;
-
-    /* Initialise the pointer after zero padding */
-    pDst += j;
-  }
-
-  else if(srcALen < srcBLen)
-  {
-    /* Initialization to inputB pointer */
-    pIn1 = pSrcB;
-
-    /* Initialization to the end of inputA pointer */
-    pIn2 = pSrcA + (srcALen - 1u);
-
-    /* Initialisation of the pointer after zero padding */
-    pDst = pDst + tot;
-
-    /* Swapping the lengths */
-    j = srcALen;
-    srcALen = srcBLen;
-    srcBLen = j;
-
-    /* Setting the reverse flag */
-    inv = 1;
-
-  }
-
-  /* Loop to calculate convolution for output length number of times */
-  for (i = 0u; i <= tot; i++)
-  {
-    /* Initialize sum with zero to carry on MAC operations */
-    sum = 0.0f;
-
-    /* Loop to perform MAC operations according to convolution equation */
-    for (j = 0u; j <= i; j++)
-    {
-      /* Check the array limitations */
-      if((((i - j) < srcBLen) && (j < srcALen)))
-      {
-        /* z[i] += x[i-j] * y[j] */
-        sum += pIn1[j] * pIn2[-((int32_t) i - j)];
-      }
-    }
-    /* Store the output in the destination buffer */
-    if(inv == 1)
-      *pDst-- = sum;
-    else
-      *pDst++ = sum;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
- * @} end of Corr group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c
deleted file mode 100644
index 59970e11d4..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c
+++ /dev/null
@@ -1,507 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_correlate_fast_opt_q15.c    
-*    
-* Description:	Fast Q15 Correlation.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-* 
-* Version 1.0.11 2011/10/18  
-*    Bug Fix in conv, correlation, partial convolution.  
-* 
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup Corr    
- * @{    
- */
-
-/**    
- * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.    
- * @param[in] *pSrcA points to the first input sequence.    
- * @param[in] srcALen length of the first input sequence.    
- * @param[in] *pSrcB points to the second input sequence.    
- * @param[in] srcBLen length of the second input sequence.    
- * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.    
- * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
- * @return none.    
- *    
- *    
- * \par Restrictions    
- *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
- *	In this case input, output, scratch buffers should be aligned by 32-bit    
- *    
- *     
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * This fast version uses a 32-bit accumulator with 2.30 format.    
- * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
- * There is no saturation on intermediate additions.    
- * Thus, if the accumulator overflows it wraps around and distorts the result.    
- * The input signals should be scaled down to avoid intermediate overflows.    
- * Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a    
- * maximum of min(srcALen, srcBLen) number of additions is carried internally.    
- * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.    
- *    
- * \par    
- * See arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.    
- */
-
-void arm_correlate_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch)
-{
-  q15_t *pIn1;                                   /* inputA pointer               */
-  q15_t *pIn2;                                   /* inputB pointer               */
-  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators                  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  q31_t x1, x2, x3;                              /* temporary variables for holding input and coefficient values */
-  uint32_t j, blkCnt, outBlockSize;              /* loop counter                 */
-  int32_t inc = 1;                               /* Destination address modifier */
-  uint32_t tapCnt;
-  q31_t y1, y2;
-  q15_t *pScr;                                   /* Intermediate pointers        */
-  q15_t *pOut = pDst;                            /* output pointer               */
-#ifdef UNALIGNED_SUPPORT_DISABLE
-
-  q15_t a, b;
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  /* But CORR(x, y) is reverse of CORR(y, x) */
-  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
-  /* and the destination pointer modifier, inc is set to -1 */
-  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
-  /* But to improve the performance,        
-   * we include zeroes in the output instead of zero padding either of the the inputs*/
-  /* If srcALen > srcBLen,        
-   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
-  /* If srcALen < srcBLen,        
-   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcA);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcB);
-
-    /* Number of output samples is calculated */
-    outBlockSize = (2u * srcALen) - 1u;
-
-    /* When srcALen > srcBLen, zero padding is done to srcB        
-     * to make their lengths equal.        
-     * Instead, (outBlockSize - (srcALen + srcBLen - 1))        
-     * number of output samples are made zero */
-    j = outBlockSize - (srcALen + (srcBLen - 1u));
-
-    /* Updating the pointer position to non zero value */
-    pOut += j;
-
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcB);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcA);
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-
-    /* CORR(x, y) = Reverse order(CORR(y, x)) */
-    /* Hence set the destination pointer to point to the last output sample */
-    pOut = pDst + ((srcALen + srcBLen) - 2u);
-
-    /* Destination address modifier is set to -1 */
-    inc = -1;
-
-  }
-
-  pScr = pScratch;
-
-  /* Fill (srcBLen - 1u) zeros in scratch buffer */
-  arm_fill_q15(0, pScr, (srcBLen - 1u));
-
-  /* Update temporary scratch pointer */
-  pScr += (srcBLen - 1u);
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-  /* Copy (srcALen) samples in scratch buffer */
-  arm_copy_q15(pIn1, pScr, srcALen);
-
-  /* Update pointers */
-  pScr += srcALen;
-
-#else
-
-  /* Apply loop unrolling and do 4 Copies simultaneously. */
-  j = srcALen >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-  while(j > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    *pScr++ = *pIn1++;
-    *pScr++ = *pIn1++;
-    *pScr++ = *pIn1++;
-    *pScr++ = *pIn1++;
-
-    /* Decrement the loop counter */
-    j--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  j = srcALen % 0x4u;
-
-  while(j > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    *pScr++ = *pIn1++;
-
-    /* Decrement the loop counter */
-    j--;
-  }
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-  /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
-  arm_fill_q15(0, pScr, (srcBLen - 1u));
-
-  /* Update pointer */
-  pScr += (srcBLen - 1u);
-
-#else
-
-/* Apply loop unrolling and do 4 Copies simultaneously. */
-  j = (srcBLen - 1u) >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-  while(j > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    *pScr++ = 0;
-    *pScr++ = 0;
-    *pScr++ = 0;
-    *pScr++ = 0;
-
-    /* Decrement the loop counter */
-    j--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  j = (srcBLen - 1u) % 0x4u;
-
-  while(j > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    *pScr++ = 0;
-
-    /* Decrement the loop counter */
-    j--;
-  }
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-  /* Temporary pointer for scratch2 */
-  py = pIn2;
-
-
-  /* Actual correlation process starts here */
-  blkCnt = (srcALen + srcBLen - 1u) >> 2;
-
-  while(blkCnt > 0)
-  {
-    /* Initialze temporary scratch pointer as scratch1 */
-    pScr = pScratch;
-
-    /* Clear Accumlators */
-    acc0 = 0;
-    acc1 = 0;
-    acc2 = 0;
-    acc3 = 0;
-
-    /* Read four samples from scratch1 buffer */
-    x1 = *__SIMD32(pScr)++;
-
-    /* Read next four samples from scratch1 buffer */
-    x2 = *__SIMD32(pScr)++;
-
-    tapCnt = (srcBLen) >> 2u;
-
-    while(tapCnt > 0u)
-    {
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-      /* Read four samples from smaller buffer */
-      y1 = _SIMD32_OFFSET(pIn2);
-      y2 = _SIMD32_OFFSET(pIn2 + 2u);
-
-      acc0 = __SMLAD(x1, y1, acc0);
-
-      acc2 = __SMLAD(x2, y1, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc1 = __SMLADX(x3, y1, acc1);
-
-      x1 = _SIMD32_OFFSET(pScr);
-
-      acc0 = __SMLAD(x2, y2, acc0);
-
-      acc2 = __SMLAD(x1, y2, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x1, x2, 0);
-#else
-      x3 = __PKHBT(x2, x1, 0);
-#endif
-
-      acc3 = __SMLADX(x3, y1, acc3);
-
-      acc1 = __SMLADX(x3, y2, acc1);
-
-      x2 = _SIMD32_OFFSET(pScr + 2u);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc3 = __SMLADX(x3, y2, acc3);
-#else	 
-
-      /* Read four samples from smaller buffer */
-	  a = *pIn2;
-	  b = *(pIn2 + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      y1 = __PKHBT(a, b, 16);
-#else
-      y1 = __PKHBT(b, a, 16);
-#endif
-	  
-	  a = *(pIn2 + 2);
-	  b = *(pIn2 + 3);
-#ifndef ARM_MATH_BIG_ENDIAN
-      y2 = __PKHBT(a, b, 16);
-#else
-      y2 = __PKHBT(b, a, 16);
-#endif				
-
-      acc0 = __SMLAD(x1, y1, acc0);
-
-      acc2 = __SMLAD(x2, y1, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc1 = __SMLADX(x3, y1, acc1);
-
-	  a = *pScr;
-	  b = *(pScr + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x1 = __PKHBT(a, b, 16);
-#else
-      x1 = __PKHBT(b, a, 16);
-#endif
-
-      acc0 = __SMLAD(x2, y2, acc0);
-
-      acc2 = __SMLAD(x1, y2, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x1, x2, 0);
-#else
-      x3 = __PKHBT(x2, x1, 0);
-#endif
-
-      acc3 = __SMLADX(x3, y1, acc3);
-
-      acc1 = __SMLADX(x3, y2, acc1);
-
-	  a = *(pScr + 2);
-	  b = *(pScr + 3);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x2 = __PKHBT(a, b, 16);
-#else
-      x2 = __PKHBT(b, a, 16);
-#endif
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc3 = __SMLADX(x3, y2, acc3);
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-      pIn2 += 4u;
-
-      pScr += 4u;
-
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-
-
-    /* Update scratch pointer for remaining samples of smaller length sequence */
-    pScr -= 4u;
-
-
-    /* apply same above for remaining samples of smaller length sequence */
-    tapCnt = (srcBLen) & 3u;
-
-    while(tapCnt > 0u)
-    {
-
-      /* accumlate the results */
-      acc0 += (*pScr++ * *pIn2);
-      acc1 += (*pScr++ * *pIn2);
-      acc2 += (*pScr++ * *pIn2);
-      acc3 += (*pScr++ * *pIn2++);
-
-      pScr -= 3u;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    blkCnt--;
-
-
-    /* Store the results in the accumulators in the destination buffer. */
-    *pOut = (__SSAT(acc0 >> 15u, 16));
-    pOut += inc;
-    *pOut = (__SSAT(acc1 >> 15u, 16));
-    pOut += inc;
-    *pOut = (__SSAT(acc2 >> 15u, 16));
-    pOut += inc;
-    *pOut = (__SSAT(acc3 >> 15u, 16));
-    pOut += inc;
-
-
-    /* Initialization of inputB pointer */
-    pIn2 = py;
-
-    pScratch += 4u;
-
-  }
-
-
-  blkCnt = (srcALen + srcBLen - 1u) & 0x3;
-
-  /* Calculate correlation for remaining samples of Bigger length sequence */
-  while(blkCnt > 0)
-  {
-    /* Initialze temporary scratch pointer as scratch1 */
-    pScr = pScratch;
-
-    /* Clear Accumlators */
-    acc0 = 0;
-
-    tapCnt = (srcBLen) >> 1u;
-
-    while(tapCnt > 0u)
-    {
-
-      acc0 += (*pScr++ * *pIn2++);
-      acc0 += (*pScr++ * *pIn2++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    tapCnt = (srcBLen) & 1u;
-
-    /* apply same above for remaining samples of smaller length sequence */
-    while(tapCnt > 0u)
-    {
-
-      /* accumlate the results */
-      acc0 += (*pScr++ * *pIn2++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    blkCnt--;
-
-    /* Store the result in the accumulator in the destination buffer. */
-
-    *pOut = (q15_t) (__SSAT((acc0 >> 15), 16));
-
-    pOut += inc;
-
-    /* Initialization of inputB pointer */
-    pIn2 = py;
-
-    pScratch += 1u;
-
-  }
-}
-
-/**    
- * @} end of Corr group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q15.c
deleted file mode 100644
index ca7fe1f2ab..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q15.c
+++ /dev/null
@@ -1,1314 +0,0 @@
-/* ----------------------------------------------------------------------   
-* Copyright (C) 2010 ARM Limited. All rights reserved.   
-*   
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*   
-* Project: 	    CMSIS DSP Library   
-* Title:		arm_correlate_fast_q15.c   
-*   
-* Description:	Fast Q15 Correlation.   
-*   
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-* 
-* Version 1.0.11 2011/10/18 
-*    Bug Fix in conv, correlation, partial convolution. 
-*
-* Version 1.0.10 2011/7/15 
-*    Big Endian support added and Merged M0 and M3/M4 Source code.  
-*   
-* Version 1.0.3 2010/11/29  
-*    Re-organized the CMSIS folders and updated documentation.   
-*    
-* Version 1.0.2 2010/11/11   
-*    Documentation updated.    
-*   
-* Version 1.0.1 2010/10/05    
-*    Production release and review comments incorporated.   
-*   
-* Version 1.0.0 2010/09/20    
-*    Production release and review comments incorporated.   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**   
- * @ingroup groupFilters   
- */
-
-/**   
- * @addtogroup Corr   
- * @{   
- */
-
-/**   
- * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.   
- * @param[in] *pSrcA points to the first input sequence.   
- * @param[in] srcALen length of the first input sequence.   
- * @param[in] *pSrcB points to the second input sequence.   
- * @param[in] srcBLen length of the second input sequence.   
- * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   
- * @return none.   
- *   
- * Scaling and Overflow Behavior:   
- *   
- * \par   
- * This fast version uses a 32-bit accumulator with 2.30 format.   
- * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
- * There is no saturation on intermediate additions.   
- * Thus, if the accumulator overflows it wraps around and distorts the result.   
- * The input signals should be scaled down to avoid intermediate overflows.   
- * Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a   
- * maximum of min(srcALen, srcBLen) number of additions is carried internally.   
- * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.   
- *   
- * \par   
- * See arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.   
- */
-
-void arm_correlate_fast_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst)
-{
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-  q15_t *pIn1;                                   /* inputA pointer               */
-  q15_t *pIn2;                                   /* inputB pointer               */
-  q15_t *pOut = pDst;                            /* output pointer               */
-  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
-  q15_t *px;                                     /* Intermediate inputA pointer  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  q15_t *pSrc1;                                  /* Intermediate pointers        */
-  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
-  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
-  int32_t inc = 1;                               /* Destination address modifier */
-
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  /* But CORR(x, y) is reverse of CORR(y, x) */
-  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
-  /* and the destination pointer modifier, inc is set to -1 */
-  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
-  /* But to improve the performance,   
-   * we include zeroes in the output instead of zero padding either of the the inputs*/
-  /* If srcALen > srcBLen,   
-   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
-  /* If srcALen < srcBLen,   
-   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcA);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcB);
-
-    /* Number of output samples is calculated */
-    outBlockSize = (2u * srcALen) - 1u;
-
-    /* When srcALen > srcBLen, zero padding is done to srcB   
-     * to make their lengths equal.   
-     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
-     * number of output samples are made zero */
-    j = outBlockSize - (srcALen + (srcBLen - 1u));
-
-    /* Updating the pointer position to non zero value */
-    pOut += j;
-
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcB);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcA);
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-
-    /* CORR(x, y) = Reverse order(CORR(y, x)) */
-    /* Hence set the destination pointer to point to the last output sample */
-    pOut = pDst + ((srcALen + srcBLen) - 2u);
-
-    /* Destination address modifier is set to -1 */
-    inc = -1;
-
-  }
-
-  /* The function is internally   
-   * divided into three parts according to the number of multiplications that has to be   
-   * taken place between inputA samples and inputB samples. In the first part of the   
-   * algorithm, the multiplications increase by one for every iteration.   
-   * In the second part of the algorithm, srcBLen number of multiplications are done.   
-   * In the third part of the algorithm, the multiplications decrease by one   
-   * for every iteration.*/
-  /* The algorithm is implemented in three stages.   
-   * The loop counters of each stage is initiated here. */
-  blockSize1 = srcBLen - 1u;
-  blockSize2 = srcALen - (srcBLen - 1u);
-  blockSize3 = blockSize1;
-
-  /* --------------------------   
-   * Initializations of stage1   
-   * -------------------------*/
-
-  /* sum = x[0] * y[srcBlen - 1]   
-   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   
-   * ....   
-   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
-   */
-
-  /* In this stage the MAC operations are increased by 1 for every iteration.   
-     The count variable holds the number of MAC operations performed */
-  count = 1u;
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  pSrc1 = pIn2 + (srcBLen - 1u);
-  py = pSrc1;
-
-  /* ------------------------   
-   * Stage1 process   
-   * ----------------------*/
-
-  /* The first loop starts here */
-  while(blockSize1 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
-      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
-      /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */
-      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* x[0] * y[srcBLen - 1] */
-      sum = __SMLAD(*px++, *py++, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = (q15_t) (sum >> 15);
-    /* Destination pointer is updated according to the address modifier, inc */
-    pOut += inc;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pSrc1 - count;
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* --------------------------   
-   * Initializations of stage2   
-   * ------------------------*/
-
-  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
-   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
-   * ....   
-   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
-   */
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-  /* count is index by which the pointer pIn1 to be incremented */
-  count = 0u;
-
-  /* -------------------   
-   * Stage2 process   
-   * ------------------*/
-
-  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
-   * So, to loop unroll over blockSize2,   
-   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
-  if(srcBLen >= 4u)
-  {
-    /* Loop unroll over blockSize2, by 4 */
-    blkCnt = blockSize2 >> 2u;
-
-    while(blkCnt > 0u)
-    {
-      /* Set all accumulators to zero */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-      /* read x[0], x[1] samples */
-      x0 = *__SIMD32(px);
-      /* read x[1], x[2] samples */
-      x1 = _SIMD32_OFFSET(px + 1);
-	  px += 2u;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      do
-      {
-        /* Read the first two inputB samples using SIMD:   
-         * y[0] and y[1] */
-        c0 = *__SIMD32(py)++;
-
-        /* acc0 +=  x[0] * y[0] + x[1] * y[1] */
-        acc0 = __SMLAD(x0, c0, acc0);
-
-        /* acc1 +=  x[1] * y[0] + x[2] * y[1] */
-        acc1 = __SMLAD(x1, c0, acc1);
-
-        /* Read x[2], x[3] */
-        x2 = *__SIMD32(px);
-
-        /* Read x[3], x[4] */
-        x3 = _SIMD32_OFFSET(px + 1);
-
-        /* acc2 +=  x[2] * y[0] + x[3] * y[1] */
-        acc2 = __SMLAD(x2, c0, acc2);
-
-        /* acc3 +=  x[3] * y[0] + x[4] * y[1] */
-        acc3 = __SMLAD(x3, c0, acc3);
-
-        /* Read y[2] and y[3] */
-        c0 = *__SIMD32(py)++;
-
-        /* acc0 +=  x[2] * y[2] + x[3] * y[3] */
-        acc0 = __SMLAD(x2, c0, acc0);
-
-        /* acc1 +=  x[3] * y[2] + x[4] * y[3] */
-        acc1 = __SMLAD(x3, c0, acc1);
-
-        /* Read x[4], x[5] */
-        x0 = _SIMD32_OFFSET(px + 2);
-
-        /* Read x[5], x[6] */
-        x1 = _SIMD32_OFFSET(px + 3);
-		px += 4u;
-
-        /* acc2 +=  x[4] * y[2] + x[5] * y[3] */
-        acc2 = __SMLAD(x0, c0, acc2);
-
-        /* acc3 +=  x[5] * y[2] + x[6] * y[3] */
-        acc3 = __SMLAD(x1, c0, acc3);
-
-      } while(--k);
-
-      /* For the next MAC operations, SIMD is not used   
-       * So, the 16 bit pointer if inputB, py is updated */
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      if(k == 1u)
-      {
-        /* Read y[4] */
-        c0 = *py;
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-
-#else
-
-        c0 = c0 & 0x0000FFFF;
-
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-
-        /* Read x[7] */
-        x3 = *__SIMD32(px);
-		px++;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLAD(x0, c0, acc0);
-        acc1 = __SMLAD(x1, c0, acc1);
-        acc2 = __SMLADX(x1, c0, acc2);
-        acc3 = __SMLADX(x3, c0, acc3);
-      }
-
-      if(k == 2u)
-      {
-        /* Read y[4], y[5] */
-        c0 = *__SIMD32(py);
-
-        /* Read x[7], x[8] */
-        x3 = *__SIMD32(px);
-
-        /* Read x[9] */
-        x2 = _SIMD32_OFFSET(px + 1);
-		px += 2u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLAD(x0, c0, acc0);
-        acc1 = __SMLAD(x1, c0, acc1);
-        acc2 = __SMLAD(x3, c0, acc2);
-        acc3 = __SMLAD(x2, c0, acc3);
-      }
-
-      if(k == 3u)
-      {
-        /* Read y[4], y[5] */
-        c0 = *__SIMD32(py)++;
-
-        /* Read x[7], x[8] */
-        x3 = *__SIMD32(px);
-
-        /* Read x[9] */
-        x2 = _SIMD32_OFFSET(px + 1);
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLAD(x0, c0, acc0);
-        acc1 = __SMLAD(x1, c0, acc1);
-        acc2 = __SMLAD(x3, c0, acc2);
-        acc3 = __SMLAD(x2, c0, acc3);
-
-        c0 = (*py);
-        /* Read y[6] */
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-#else
-
-        c0 = c0 & 0x0000FFFF;
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-
-        /* Read x[10] */
-        x3 = _SIMD32_OFFSET(px + 2);
-		px += 3u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLADX(x1, c0, acc0);
-        acc1 = __SMLAD(x2, c0, acc1);
-        acc2 = __SMLADX(x2, c0, acc2);
-        acc3 = __SMLADX(x3, c0, acc3);
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q15_t) (acc0 >> 15);
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      *pOut = (q15_t) (acc1 >> 15);
-      pOut += inc;
-
-      *pOut = (q15_t) (acc2 >> 15);
-      pOut += inc;
-
-      *pOut = (q15_t) (acc3 >> 15);
-      pOut += inc;
-
-      /* Increment the pointer pIn1 index, count by 1 */
-      count += 4u;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
-     ** No loop unrolling is used. */
-    blkCnt = blockSize2 % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += ((q31_t) * px++ * *py++);
-        sum += ((q31_t) * px++ * *py++);
-        sum += ((q31_t) * px++ * *py++);
-        sum += ((q31_t) * px++ * *py++);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += ((q31_t) * px++ * *py++);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q15_t) (sum >> 15);
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      /* Increment the pointer pIn1 index, count by 1 */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-  else
-  {
-    /* If the srcBLen is not a multiple of 4,   
-     * the blockSize2 loop cannot be unrolled by 4 */
-    blkCnt = blockSize2;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Loop over srcBLen */
-      k = srcBLen;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += ((q31_t) * px++ * *py++);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q15_t) (sum >> 15);
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-
-  /* --------------------------   
-   * Initializations of stage3   
-   * -------------------------*/
-
-  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
-   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
-   * ....   
-   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
-   * sum +=  x[srcALen-1] * y[0]   
-   */
-
-  /* In this stage the MAC operations are decreased by 1 for every iteration.   
-     The count variable holds the number of MAC operations performed */
-  count = srcBLen - 1u;
-
-  /* Working pointer of inputA */
-  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-  px = pSrc1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-  /* -------------------   
-   * Stage3 process   
-   * ------------------*/
-
-  while(blockSize3 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */
-      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
-      /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */
-      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      sum = __SMLAD(*px++, *py++, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = (q15_t) (sum >> 15);
-    /* Destination pointer is updated according to the address modifier, inc */
-    pOut += inc;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pIn2;
-
-    /* Decrement the MAC count */
-    count--;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-  }
-
-#else
-
-  q15_t *pIn1;                                   /* inputA pointer               */
-  q15_t *pIn2;                                   /* inputB pointer               */
-  q15_t *pOut = pDst;                            /* output pointer               */
-  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
-  q15_t *px;                                     /* Intermediate inputA pointer  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  q15_t *pSrc1;                                  /* Intermediate pointers        */
-  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
-  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
-  int32_t inc = 1;                               /* Destination address modifier */
-  q15_t a, b;
-
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  /* But CORR(x, y) is reverse of CORR(y, x) */
-  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
-  /* and the destination pointer modifier, inc is set to -1 */
-  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
-  /* But to improve the performance,   
-   * we include zeroes in the output instead of zero padding either of the the inputs*/
-  /* If srcALen > srcBLen,   
-   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
-  /* If srcALen < srcBLen,   
-   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcA);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcB);
-
-    /* Number of output samples is calculated */
-    outBlockSize = (2u * srcALen) - 1u;
-
-    /* When srcALen > srcBLen, zero padding is done to srcB   
-     * to make their lengths equal.   
-     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
-     * number of output samples are made zero */
-    j = outBlockSize - (srcALen + (srcBLen - 1u));
-
-    /* Updating the pointer position to non zero value */
-    pOut += j;
-
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcB);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcA);
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-
-    /* CORR(x, y) = Reverse order(CORR(y, x)) */
-    /* Hence set the destination pointer to point to the last output sample */
-    pOut = pDst + ((srcALen + srcBLen) - 2u);
-
-    /* Destination address modifier is set to -1 */
-    inc = -1;
-
-  }
-
-  /* The function is internally   
-   * divided into three parts according to the number of multiplications that has to be   
-   * taken place between inputA samples and inputB samples. In the first part of the   
-   * algorithm, the multiplications increase by one for every iteration.   
-   * In the second part of the algorithm, srcBLen number of multiplications are done.   
-   * In the third part of the algorithm, the multiplications decrease by one   
-   * for every iteration.*/
-  /* The algorithm is implemented in three stages.   
-   * The loop counters of each stage is initiated here. */
-  blockSize1 = srcBLen - 1u;
-  blockSize2 = srcALen - (srcBLen - 1u);
-  blockSize3 = blockSize1;
-
-  /* --------------------------   
-   * Initializations of stage1   
-   * -------------------------*/
-
-  /* sum = x[0] * y[srcBlen - 1]   
-   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   
-   * ....   
-   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
-   */
-
-  /* In this stage the MAC operations are increased by 1 for every iteration.   
-     The count variable holds the number of MAC operations performed */
-  count = 1u;
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  pSrc1 = pIn2 + (srcBLen - 1u);
-  py = pSrc1;
-
-  /* ------------------------   
-   * Stage1 process   
-   * ----------------------*/
-
-  /* The first loop starts here */
-  while(blockSize1 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
-        sum += ((q31_t) * px++ * *py++);
-        sum += ((q31_t) * px++ * *py++);
-        sum += ((q31_t) * px++ * *py++);
-        sum += ((q31_t) * px++ * *py++);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* x[0] * y[srcBLen - 1] */
-        sum += ((q31_t) * px++ * *py++);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = (q15_t) (sum >> 15);
-    /* Destination pointer is updated according to the address modifier, inc */
-    pOut += inc;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pSrc1 - count;
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* --------------------------   
-   * Initializations of stage2   
-   * ------------------------*/
-
-  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
-   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
-   * ....   
-   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
-   */
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-  /* count is index by which the pointer pIn1 to be incremented */
-  count = 0u;
-
-  /* -------------------   
-   * Stage2 process   
-   * ------------------*/
-
-  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
-   * So, to loop unroll over blockSize2,   
-   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
-  if(srcBLen >= 4u)
-  {
-    /* Loop unroll over blockSize2, by 4 */
-    blkCnt = blockSize2 >> 2u;
-
-    while(blkCnt > 0u)
-    {
-      /* Set all accumulators to zero */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-      /* read x[0], x[1], x[2] samples */
-	  a = *px;
-	  b = *(px + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-	  x0 = __PKHBT(a, b, 16);
-	  a = *(px + 2);
-	  x1 = __PKHBT(b, a, 16);
-
-#else
-
-	  x0 = __PKHBT(b, a, 16);
-	  a = *(px + 2);
-	  x1 = __PKHBT(a, b, 16);
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-	  px += 2u;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      do
-      {
-        /* Read the first two inputB samples using SIMD:   
-         * y[0] and y[1] */
-		  a = *py;
-		  b = *(py + 1);
-	
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-		  c0 = __PKHBT(a, b, 16);
-	
-#else
-	
-		  c0 = __PKHBT(b, a, 16);
-	
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-        /* acc0 +=  x[0] * y[0] + x[1] * y[1] */
-        acc0 = __SMLAD(x0, c0, acc0);
-
-        /* acc1 +=  x[1] * y[0] + x[2] * y[1] */
-        acc1 = __SMLAD(x1, c0, acc1);
-
-        /* Read x[2], x[3], x[4] */
-	  	a = *px;
-	  	b = *(px + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-	  	x2 = __PKHBT(a, b, 16);
-	  	a = *(px + 2);
-	  	x3 = __PKHBT(b, a, 16);
-
-#else
-
-	  	x2 = __PKHBT(b, a, 16);
-	  	a = *(px + 2);
-	  	x3 = __PKHBT(a, b, 16);
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-        /* acc2 +=  x[2] * y[0] + x[3] * y[1] */
-        acc2 = __SMLAD(x2, c0, acc2);
-
-        /* acc3 +=  x[3] * y[0] + x[4] * y[1] */
-        acc3 = __SMLAD(x3, c0, acc3);
-
-        /* Read y[2] and y[3] */
-		  a = *(py + 2);
-		  b = *(py + 3);
-
-		  py += 4u;
-	
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-		  c0 = __PKHBT(a, b, 16);
-	
-#else
-	
-		  c0 = __PKHBT(b, a, 16);
-	
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-        /* acc0 +=  x[2] * y[2] + x[3] * y[3] */
-        acc0 = __SMLAD(x2, c0, acc0);
-
-        /* acc1 +=  x[3] * y[2] + x[4] * y[3] */
-        acc1 = __SMLAD(x3, c0, acc1);
-
-        /* Read x[4], x[5], x[6] */
-	  	a = *(px + 2);
-	  	b = *(px + 3);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-	  	x0 = __PKHBT(a, b, 16);
-	  	a = *(px + 4);
-	  	x1 = __PKHBT(b, a, 16);
-
-#else
-
-	  	x0 = __PKHBT(b, a, 16);
-	  	a = *(px + 4);
-	  	x1 = __PKHBT(a, b, 16);
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-		px += 4u;
-
-        /* acc2 +=  x[4] * y[2] + x[5] * y[3] */
-        acc2 = __SMLAD(x0, c0, acc2);
-
-        /* acc3 +=  x[5] * y[2] + x[6] * y[3] */
-        acc3 = __SMLAD(x1, c0, acc3);
-
-      } while(--k);
-
-      /* For the next MAC operations, SIMD is not used   
-       * So, the 16 bit pointer if inputB, py is updated */
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      if(k == 1u)
-      {
-        /* Read y[4] */
-        c0 = *py;
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-
-#else
-
-        c0 = c0 & 0x0000FFFF;
-
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-
-        /* Read x[7] */
-		a = *px;
-		b = *(px + 1);
-
-		px++;;
-	
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-		x3 = __PKHBT(a, b, 16);
-	
-#else
-	
-		x3 = __PKHBT(b, a, 16);
-	
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-		px++;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLAD(x0, c0, acc0);
-        acc1 = __SMLAD(x1, c0, acc1);
-        acc2 = __SMLADX(x1, c0, acc2);
-        acc3 = __SMLADX(x3, c0, acc3);
-      }
-
-      if(k == 2u)
-      {
-        /* Read y[4], y[5] */
-		  a = *py;
-		  b = *(py + 1);
-	
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-		  c0 = __PKHBT(a, b, 16);
-	
-#else
-	
-		  c0 = __PKHBT(b, a, 16);
-	
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-        /* Read x[7], x[8], x[9] */
-	  	a = *px;
-	  	b = *(px + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-	  	x3 = __PKHBT(a, b, 16);
-	  	a = *(px + 2);
-	  	x2 = __PKHBT(b, a, 16);
-
-#else
-
-	  	x3 = __PKHBT(b, a, 16);
-	  	a = *(px + 2);
-	  	x2 = __PKHBT(a, b, 16);
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-		px += 2u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLAD(x0, c0, acc0);
-        acc1 = __SMLAD(x1, c0, acc1);
-        acc2 = __SMLAD(x3, c0, acc2);
-        acc3 = __SMLAD(x2, c0, acc3);
-      }
-
-      if(k == 3u)
-      {
-        /* Read y[4], y[5] */
-		  a = *py;
-		  b = *(py + 1);
-	
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-		  c0 = __PKHBT(a, b, 16);
-	
-#else
-	
-		  c0 = __PKHBT(b, a, 16);
-	
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-		py += 2u;
-
-        /* Read x[7], x[8], x[9] */
-	  	a = *px;
-	  	b = *(px + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-	  	x3 = __PKHBT(a, b, 16);
-	  	a = *(px + 2);
-	  	x2 = __PKHBT(b, a, 16);
-
-#else
-
-	  	x3 = __PKHBT(b, a, 16);
-	  	a = *(px + 2);
-	  	x2 = __PKHBT(a, b, 16);
-
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLAD(x0, c0, acc0);
-        acc1 = __SMLAD(x1, c0, acc1);
-        acc2 = __SMLAD(x3, c0, acc2);
-        acc3 = __SMLAD(x2, c0, acc3);
-
-        c0 = (*py);
-        /* Read y[6] */
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-#else
-
-        c0 = c0 & 0x0000FFFF;
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-
-        /* Read x[10] */
-		b = *(px + 3);
-	
-#ifndef ARM_MATH_BIG_ENDIAN
-	
-		x3 = __PKHBT(a, b, 16);
-	
-#else
-	
-		x3 = __PKHBT(b, a, 16);
-	
-#endif	/*	#ifndef ARM_MATH_BIG_ENDIAN	*/
-
-		px += 3u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLADX(x1, c0, acc0);
-        acc1 = __SMLAD(x2, c0, acc1);
-        acc2 = __SMLADX(x2, c0, acc2);
-        acc3 = __SMLADX(x3, c0, acc3);
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q15_t) (acc0 >> 15);
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      *pOut = (q15_t) (acc1 >> 15);
-      pOut += inc;
-
-      *pOut = (q15_t) (acc2 >> 15);
-      pOut += inc;
-
-      *pOut = (q15_t) (acc3 >> 15);
-      pOut += inc;
-
-      /* Increment the pointer pIn1 index, count by 1 */
-      count += 4u;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
-     ** No loop unrolling is used. */
-    blkCnt = blockSize2 % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += ((q31_t) * px++ * *py++);
-        sum += ((q31_t) * px++ * *py++);
-        sum += ((q31_t) * px++ * *py++);
-        sum += ((q31_t) * px++ * *py++);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += ((q31_t) * px++ * *py++);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q15_t) (sum >> 15);
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      /* Increment the pointer pIn1 index, count by 1 */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-  else
-  {
-    /* If the srcBLen is not a multiple of 4,   
-     * the blockSize2 loop cannot be unrolled by 4 */
-    blkCnt = blockSize2;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Loop over srcBLen */
-      k = srcBLen;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += ((q31_t) * px++ * *py++);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q15_t) (sum >> 15);
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-
-  /* --------------------------   
-   * Initializations of stage3   
-   * -------------------------*/
-
-  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
-   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
-   * ....   
-   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
-   * sum +=  x[srcALen-1] * y[0]   
-   */
-
-  /* In this stage the MAC operations are decreased by 1 for every iteration.   
-     The count variable holds the number of MAC operations performed */
-  count = srcBLen - 1u;
-
-  /* Working pointer of inputA */
-  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-  px = pSrc1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-  /* -------------------   
-   * Stage3 process   
-   * ------------------*/
-
-  while(blockSize3 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-        sum += ((q31_t) * px++ * *py++);
-        sum += ((q31_t) * px++ * *py++);
-        sum += ((q31_t) * px++ * *py++);
-        sum += ((q31_t) * px++ * *py++);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-        sum += ((q31_t) * px++ * *py++);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = (q15_t) (sum >> 15);
-    /* Destination pointer is updated according to the address modifier, inc */
-    pOut += inc;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pIn2;
-
-    /* Decrement the MAC count */
-    count--;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-  }
-
-#endif /*   #ifndef UNALIGNED_SUPPORT_DISABLE */
-
-}
-
-/**   
- * @} end of Corr group   
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q31.c
deleted file mode 100644
index 5b337ca544..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q31.c
+++ /dev/null
@@ -1,607 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_correlate_fast_q31.c    
-*    
-* Description:	Fast Q31 Correlation.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-* 
-* Version 1.0.11 2011/10/18  
-*    Bug Fix in conv, correlation, partial convolution.  
-* 
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup Corr    
- * @{    
- */
-
-/**    
- * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.    
- * @param[in] *pSrcA points to the first input sequence.    
- * @param[in] srcALen length of the first input sequence.    
- * @param[in] *pSrcB points to the second input sequence.    
- * @param[in] srcBLen length of the second input sequence.    
- * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * This function is optimized for speed at the expense of fixed-point precision and overflow protection.    
- * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.    
- * These intermediate results are accumulated in a 32-bit register in 2.30 format.    
- * Finally, the accumulator is saturated and converted to a 1.31 result.    
- *    
- * \par    
- * The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result.    
- * In order to avoid overflows completely the input signals must be scaled down.    
- * The input signals should be scaled down to avoid intermediate overflows.    
- * Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a    
- * maximum of min(srcALen, srcBLen) number of additions is carried internally.    
- *    
- * \par    
- * See arm_correlate_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.    
- */
-
-void arm_correlate_fast_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst)
-{
-  q31_t *pIn1;                                   /* inputA pointer               */
-  q31_t *pIn2;                                   /* inputB pointer               */
-  q31_t *pOut = pDst;                            /* output pointer               */
-  q31_t *px;                                     /* Intermediate inputA pointer  */
-  q31_t *py;                                     /* Intermediate inputB pointer  */
-  q31_t *pSrc1;                                  /* Intermediate pointers        */
-  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
-  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
-  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
-  int32_t inc = 1;                               /* Destination address modifier */
-
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcA);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcB);
-
-    /* Number of output samples is calculated */
-    outBlockSize = (2u * srcALen) - 1u;
-
-    /* When srcALen > srcBLen, zero padding is done to srcB    
-     * to make their lengths equal.    
-     * Instead, (outBlockSize - (srcALen + srcBLen - 1))    
-     * number of output samples are made zero */
-    j = outBlockSize - (srcALen + (srcBLen - 1u));
-
-    /* Updating the pointer position to non zero value */
-    pOut += j;
-
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcB);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcA);
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-
-    /* CORR(x, y) = Reverse order(CORR(y, x)) */
-    /* Hence set the destination pointer to point to the last output sample */
-    pOut = pDst + ((srcALen + srcBLen) - 2u);
-
-    /* Destination address modifier is set to -1 */
-    inc = -1;
-
-  }
-
-  /* The function is internally    
-   * divided into three parts according to the number of multiplications that has to be    
-   * taken place between inputA samples and inputB samples. In the first part of the    
-   * algorithm, the multiplications increase by one for every iteration.    
-   * In the second part of the algorithm, srcBLen number of multiplications are done.    
-   * In the third part of the algorithm, the multiplications decrease by one    
-   * for every iteration.*/
-  /* The algorithm is implemented in three stages.    
-   * The loop counters of each stage is initiated here. */
-  blockSize1 = srcBLen - 1u;
-  blockSize2 = srcALen - (srcBLen - 1u);
-  blockSize3 = blockSize1;
-
-  /* --------------------------    
-   * Initializations of stage1    
-   * -------------------------*/
-
-  /* sum = x[0] * y[srcBlen - 1]    
-   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]    
-   * ....    
-   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]    
-   */
-
-  /* In this stage the MAC operations are increased by 1 for every iteration.    
-     The count variable holds the number of MAC operations performed */
-  count = 1u;
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  pSrc1 = pIn2 + (srcBLen - 1u);
-  py = pSrc1;
-
-  /* ------------------------    
-   * Stage1 process    
-   * ----------------------*/
-
-  /* The first stage starts here */
-  while(blockSize1 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* x[0] * y[srcBLen - 4] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py++))) >> 32);
-      /* x[1] * y[srcBLen - 3] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py++))) >> 32);
-      /* x[2] * y[srcBLen - 2] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py++))) >> 32);
-      /* x[3] * y[srcBLen - 1] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py++))) >> 32);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.    
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* x[0] * y[srcBLen - 1] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py++))) >> 32);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = sum << 1;
-    /* Destination pointer is updated according to the address modifier, inc */
-    pOut += inc;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pSrc1 - count;
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* --------------------------    
-   * Initializations of stage2    
-   * ------------------------*/
-
-  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]    
-   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]    
-   * ....    
-   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
-   */
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-  /* count is index by which the pointer pIn1 to be incremented */
-  count = 0u;
-
-  /* -------------------    
-   * Stage2 process    
-   * ------------------*/
-
-  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
-   * So, to loop unroll over blockSize2,    
-   * srcBLen should be greater than or equal to 4 */
-  if(srcBLen >= 4u)
-  {
-    /* Loop unroll over blockSize2, by 4 */
-    blkCnt = blockSize2 >> 2u;
-
-    while(blkCnt > 0u)
-    {
-      /* Set all accumulators to zero */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-      /* read x[0], x[1], x[2] samples */
-      x0 = *(px++);
-      x1 = *(px++);
-      x2 = *(px++);
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      do
-      {
-        /* Read y[0] sample */
-        c0 = *(py++);
-
-        /* Read x[3] sample */
-        x3 = *(px++);
-
-        /* Perform the multiply-accumulate */
-        /* acc0 +=  x[0] * y[0] */
-        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
-        /* acc1 +=  x[1] * y[0] */
-        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
-        /* acc2 +=  x[2] * y[0] */
-        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
-        /* acc3 +=  x[3] * y[0] */
-        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
-
-        /* Read y[1] sample */
-        c0 = *(py++);
-
-        /* Read x[4] sample */
-        x0 = *(px++);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[1] * y[1] */
-        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
-        /* acc1 +=  x[2] * y[1] */
-        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
-        /* acc2 +=  x[3] * y[1] */
-        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
-        /* acc3 +=  x[4] * y[1] */
-        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
-
-        /* Read y[2] sample */
-        c0 = *(py++);
-
-        /* Read x[5] sample */
-        x1 = *(px++);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[2] * y[2] */
-        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
-        /* acc1 +=  x[3] * y[2] */
-        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
-        /* acc2 +=  x[4] * y[2] */
-        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
-        /* acc3 +=  x[5] * y[2] */
-        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
-
-        /* Read y[3] sample */
-        c0 = *(py++);
-
-        /* Read x[6] sample */
-        x2 = *(px++);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[3] * y[3] */
-        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
-        /* acc1 +=  x[4] * y[3] */
-        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
-        /* acc2 +=  x[5] * y[3] */
-        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
-        /* acc3 +=  x[6] * y[3] */
-        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
-
-
-      } while(--k);
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Read y[4] sample */
-        c0 = *(py++);
-
-        /* Read x[7] sample */
-        x3 = *(px++);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[4] * y[4] */
-        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
-        /* acc1 +=  x[5] * y[4] */
-        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
-        /* acc2 +=  x[6] * y[4] */
-        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
-        /* acc3 +=  x[7] * y[4] */
-        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
-
-        /* Reuse the present samples for the next MAC */
-        x0 = x1;
-        x1 = x2;
-        x2 = x3;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q31_t) (acc0 << 1);
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      *pOut = (q31_t) (acc1 << 1);
-      pOut += inc;
-
-      *pOut = (q31_t) (acc2 << 1);
-      pOut += inc;
-
-      *pOut = (q31_t) (acc3 << 1);
-      pOut += inc;
-
-      /* Increment the pointer pIn1 index, count by 4 */
-      count += 4u;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.    
-     ** No loop unrolling is used. */
-    blkCnt = blockSize2 % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py++))) >> 32);
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py++))) >> 32);
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py++))) >> 32);
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py++))) >> 32);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py++))) >> 32);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = sum << 1;
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-  else
-  {
-    /* If the srcBLen is not a multiple of 4,    
-     * the blockSize2 loop cannot be unrolled by 4 */
-    blkCnt = blockSize2;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Loop over srcBLen */
-      k = srcBLen;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum = (q31_t) ((((q63_t) sum << 32) +
-                        ((q63_t) * px++ * (*py++))) >> 32);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = sum << 1;
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-
-  /* --------------------------    
-   * Initializations of stage3    
-   * -------------------------*/
-
-  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
-   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
-   * ....    
-   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]    
-   * sum +=  x[srcALen-1] * y[0]    
-   */
-
-  /* In this stage the MAC operations are decreased by 1 for every iteration.    
-     The count variable holds the number of MAC operations performed */
-  count = srcBLen - 1u;
-
-  /* Working pointer of inputA */
-  pSrc1 = ((pIn1 + srcALen) - srcBLen) + 1u;
-  px = pSrc1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-  /* -------------------    
-   * Stage3 process    
-   * ------------------*/
-
-  while(blockSize3 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* sum += x[srcALen - srcBLen + 4] * y[3] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py++))) >> 32);
-      /* sum += x[srcALen - srcBLen + 3] * y[2] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py++))) >> 32);
-      /* sum += x[srcALen - srcBLen + 2] * y[1] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py++))) >> 32);
-      /* sum += x[srcALen - srcBLen + 1] * y[0] */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py++))) >> 32);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.    
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      sum = (q31_t) ((((q63_t) sum << 32) +
-                      ((q63_t) * px++ * (*py++))) >> 32);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = sum << 1;
-    /* Destination pointer is updated according to the address modifier, inc */
-    pOut += inc;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pIn2;
-
-    /* Decrement the MAC count */
-    count--;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-  }
-
-}
-
-/**    
- * @} end of Corr group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q15.c
deleted file mode 100644
index 3a1c8cd4a6..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q15.c
+++ /dev/null
@@ -1,512 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_correlate_opt_q15.c    
-*    
-* Description:	Correlation of Q15 sequences.  
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-* 
-* Version 1.0.11 2011/10/18  
-*    Bug Fix in conv, correlation, partial convolution.  
-* 
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-*    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup Corr    
- * @{    
- */
-
-/**    
- * @brief Correlation of Q15 sequences.  
- * @param[in] *pSrcA points to the first input sequence.    
- * @param[in] srcALen length of the first input sequence.    
- * @param[in] *pSrcB points to the second input sequence.    
- * @param[in] srcBLen length of the second input sequence.    
- * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.    
- * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.    
- * @return none.    
- *    
- * \par Restrictions    
- *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
- *	In this case input, output, scratch buffers should be aligned by 32-bit    
- *     
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The function is implemented using a 64-bit internal accumulator.    
- * Both inputs are in 1.15 format and multiplications yield a 2.30 result.    
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    
- * This approach provides 33 guard bits and there is no risk of overflow.    
- * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.    
- *    
- * \par    
- * Refer to arm_correlate_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.   
- *  
- * 
- */
-
-
-void arm_correlate_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch)
-{
-  q15_t *pIn1;                                   /* inputA pointer               */
-  q15_t *pIn2;                                   /* inputB pointer               */
-  q63_t acc0, acc1, acc2, acc3;                  /* Accumulators                  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  q31_t x1, x2, x3;                              /* temporary variables for holding input1 and input2 values */
-  uint32_t j, blkCnt, outBlockSize;              /* loop counter                 */
-  int32_t inc = 1;                               /* output pointer increment     */
-  uint32_t tapCnt;
-  q31_t y1, y2;
-  q15_t *pScr;                                   /* Intermediate pointers        */
-  q15_t *pOut = pDst;                            /* output pointer               */
-#ifdef UNALIGNED_SUPPORT_DISABLE
-
-  q15_t a, b;
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  /* But CORR(x, y) is reverse of CORR(y, x) */
-  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
-  /* and the destination pointer modifier, inc is set to -1 */
-  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
-  /* But to improve the performance,        
-   * we include zeroes in the output instead of zero padding either of the the inputs*/
-  /* If srcALen > srcBLen,        
-   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
-  /* If srcALen < srcBLen,        
-   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcA);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcB);
-
-    /* Number of output samples is calculated */
-    outBlockSize = (2u * srcALen) - 1u;
-
-    /* When srcALen > srcBLen, zero padding is done to srcB        
-     * to make their lengths equal.        
-     * Instead, (outBlockSize - (srcALen + srcBLen - 1))        
-     * number of output samples are made zero */
-    j = outBlockSize - (srcALen + (srcBLen - 1u));
-
-    /* Updating the pointer position to non zero value */
-    pOut += j;
-
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcB);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcA);
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-
-    /* CORR(x, y) = Reverse order(CORR(y, x)) */
-    /* Hence set the destination pointer to point to the last output sample */
-    pOut = pDst + ((srcALen + srcBLen) - 2u);
-
-    /* Destination address modifier is set to -1 */
-    inc = -1;
-
-  }
-
-  pScr = pScratch;
-
-  /* Fill (srcBLen - 1u) zeros in scratch buffer */
-  arm_fill_q15(0, pScr, (srcBLen - 1u));
-
-  /* Update temporary scratch pointer */
-  pScr += (srcBLen - 1u);
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-  /* Copy (srcALen) samples in scratch buffer */
-  arm_copy_q15(pIn1, pScr, srcALen);
-
-  /* Update pointers */
-  //pIn1 += srcALen;    
-  pScr += srcALen;
-
-#else
-
-  /* Apply loop unrolling and do 4 Copies simultaneously. */
-  j = srcALen >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-  while(j > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    *pScr++ = *pIn1++;
-    *pScr++ = *pIn1++;
-    *pScr++ = *pIn1++;
-    *pScr++ = *pIn1++;
-
-    /* Decrement the loop counter */
-    j--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  j = srcALen % 0x4u;
-
-  while(j > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    *pScr++ = *pIn1++;
-
-    /* Decrement the loop counter */
-    j--;
-  }
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-  /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
-  arm_fill_q15(0, pScr, (srcBLen - 1u));
-
-  /* Update pointer */
-  pScr += (srcBLen - 1u);
-
-#else
-
-/* Apply loop unrolling and do 4 Copies simultaneously. */
-  j = (srcBLen - 1u) >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-  while(j > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    *pScr++ = 0;
-    *pScr++ = 0;
-    *pScr++ = 0;
-    *pScr++ = 0;
-
-    /* Decrement the loop counter */
-    j--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  j = (srcBLen - 1u) % 0x4u;
-
-  while(j > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    *pScr++ = 0;
-
-    /* Decrement the loop counter */
-    j--;
-  }
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-  /* Temporary pointer for scratch2 */
-  py = pIn2;
-
-
-  /* Actual correlation process starts here */
-  blkCnt = (srcALen + srcBLen - 1u) >> 2;
-
-  while(blkCnt > 0)
-  {
-    /* Initialze temporary scratch pointer as scratch1 */
-    pScr = pScratch;
-
-    /* Clear Accumlators */
-    acc0 = 0;
-    acc1 = 0;
-    acc2 = 0;
-    acc3 = 0;
-
-    /* Read four samples from scratch1 buffer */
-    x1 = *__SIMD32(pScr)++;
-
-    /* Read next four samples from scratch1 buffer */
-    x2 = *__SIMD32(pScr)++;
-
-    tapCnt = (srcBLen) >> 2u;
-
-    while(tapCnt > 0u)
-    {
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-      /* Read four samples from smaller buffer */
-      y1 = _SIMD32_OFFSET(pIn2);
-      y2 = _SIMD32_OFFSET(pIn2 + 2u);
-
-      acc0 = __SMLALD(x1, y1, acc0);
-
-      acc2 = __SMLALD(x2, y1, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc1 = __SMLALDX(x3, y1, acc1);
-
-      x1 = _SIMD32_OFFSET(pScr);
-
-      acc0 = __SMLALD(x2, y2, acc0);
-
-      acc2 = __SMLALD(x1, y2, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x1, x2, 0);
-#else
-      x3 = __PKHBT(x2, x1, 0);
-#endif
-
-      acc3 = __SMLALDX(x3, y1, acc3);
-
-      acc1 = __SMLALDX(x3, y2, acc1);
-
-      x2 = _SIMD32_OFFSET(pScr + 2u);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc3 = __SMLALDX(x3, y2, acc3);
-
-#else	 
-
-      /* Read four samples from smaller buffer */
-	  a = *pIn2;
-	  b = *(pIn2 + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      y1 = __PKHBT(a, b, 16);
-#else
-      y1 = __PKHBT(b, a, 16);
-#endif
-	  
-	  a = *(pIn2 + 2);
-	  b = *(pIn2 + 3);
-#ifndef ARM_MATH_BIG_ENDIAN
-      y2 = __PKHBT(a, b, 16);
-#else
-      y2 = __PKHBT(b, a, 16);
-#endif				
-
-      acc0 = __SMLALD(x1, y1, acc0);
-
-      acc2 = __SMLALD(x2, y1, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc1 = __SMLALDX(x3, y1, acc1);
-
-	  a = *pScr;
-	  b = *(pScr + 1);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x1 = __PKHBT(a, b, 16);
-#else
-      x1 = __PKHBT(b, a, 16);
-#endif
-
-      acc0 = __SMLALD(x2, y2, acc0);
-
-      acc2 = __SMLALD(x1, y2, acc2);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x1, x2, 0);
-#else
-      x3 = __PKHBT(x2, x1, 0);
-#endif
-
-      acc3 = __SMLALDX(x3, y1, acc3);
-
-      acc1 = __SMLALDX(x3, y2, acc1);
-
-	  a = *(pScr + 2);
-	  b = *(pScr + 3);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x2 = __PKHBT(a, b, 16);
-#else
-      x2 = __PKHBT(b, a, 16);
-#endif
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc3 = __SMLALDX(x3, y2, acc3);
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-      pIn2 += 4u;
-
-      pScr += 4u;
-
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-
-
-    /* Update scratch pointer for remaining samples of smaller length sequence */
-    pScr -= 4u;
-
-
-    /* apply same above for remaining samples of smaller length sequence */
-    tapCnt = (srcBLen) & 3u;
-
-    while(tapCnt > 0u)
-    {
-
-      /* accumlate the results */
-      acc0 += (*pScr++ * *pIn2);
-      acc1 += (*pScr++ * *pIn2);
-      acc2 += (*pScr++ * *pIn2);
-      acc3 += (*pScr++ * *pIn2++);
-
-      pScr -= 3u;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    blkCnt--;
-
-
-    /* Store the results in the accumulators in the destination buffer. */
-    *pOut = (__SSAT(acc0 >> 15u, 16));
-    pOut += inc;
-    *pOut = (__SSAT(acc1 >> 15u, 16));
-    pOut += inc;
-    *pOut = (__SSAT(acc2 >> 15u, 16));
-    pOut += inc;
-    *pOut = (__SSAT(acc3 >> 15u, 16));
-    pOut += inc;
-
-    /* Initialization of inputB pointer */
-    pIn2 = py;
-
-    pScratch += 4u;
-
-  }
-
-
-  blkCnt = (srcALen + srcBLen - 1u) & 0x3;
-
-  /* Calculate correlation for remaining samples of Bigger length sequence */
-  while(blkCnt > 0)
-  {
-    /* Initialze temporary scratch pointer as scratch1 */
-    pScr = pScratch;
-
-    /* Clear Accumlators */
-    acc0 = 0;
-
-    tapCnt = (srcBLen) >> 1u;
-
-    while(tapCnt > 0u)
-    {
-
-      acc0 += (*pScr++ * *pIn2++);
-      acc0 += (*pScr++ * *pIn2++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    tapCnt = (srcBLen) & 1u;
-
-    /* apply same above for remaining samples of smaller length sequence */
-    while(tapCnt > 0u)
-    {
-
-      /* accumlate the results */
-      acc0 += (*pScr++ * *pIn2++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    blkCnt--;
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = (q15_t) (__SSAT((acc0 >> 15), 16));
-
-    pOut += inc;
-
-    /* Initialization of inputB pointer */
-    pIn2 = py;
-
-    pScratch += 1u;
-
-  }
-
-
-}
-
-/**    
- * @} end of Corr group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q7.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q7.c
deleted file mode 100644
index 48a6d091c3..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q7.c
+++ /dev/null
@@ -1,463 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_correlate_opt_q7.c    
-*    
-* Description:	Correlation of Q7 sequences.  
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-* 
-* Version 1.0.11 2011/10/18  
-*    Bug Fix in conv, correlation, partial convolution.  
-* 
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-*    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup Corr    
- * @{    
- */
-
-/**    
- * @brief Correlation of Q7 sequences.    
- * @param[in] *pSrcA points to the first input sequence.    
- * @param[in] srcALen length of the first input sequence.    
- * @param[in] *pSrcB points to the second input sequence.    
- * @param[in] srcBLen length of the second input sequence.    
- * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.    
- * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.    
- * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).    
- * @return none.    
- *    
- *    
- * \par Restrictions    
- *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE    
- *	In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit     
- *        
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The function is implemented using a 32-bit internal accumulator.    
- * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.    
- * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.    
- * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.    
- * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format.  
- *  
- * 
- */
-
-
-
-void arm_correlate_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2)
-{
-  q7_t *pOut = pDst;                             /* output pointer                */
-  q15_t *pScr1 = pScratch1;                      /* Temporary pointer for scratch */
-  q15_t *pScr2 = pScratch2;                      /* Temporary pointer for scratch */
-  q7_t *pIn1;                                    /* inputA pointer                */
-  q7_t *pIn2;                                    /* inputB pointer                */
-  q15_t *py;                                     /* Intermediate inputB pointer   */
-  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators                  */
-  uint32_t j, k = 0u, blkCnt;                    /* loop counter                  */
-  int32_t inc = 1;                               /* output pointer increment          */
-  uint32_t outBlockSize;                         /* loop counter                  */
-  q15_t x4;                                      /* Temporary input variable      */
-  uint32_t tapCnt;                               /* loop counter                  */
-  q31_t x1, x2, x3, y1;                          /* Temporary input variables     */
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  /* But CORR(x, y) is reverse of CORR(y, x) */
-  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
-  /* and the destination pointer modifier, inc is set to -1 */
-  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
-  /* But to improve the performance,        
-   * we include zeroes in the output instead of zero padding either of the the inputs*/
-  /* If srcALen > srcBLen,        
-   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
-  /* If srcALen < srcBLen,        
-   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcA);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcB);
-
-    /* Number of output samples is calculated */
-    outBlockSize = (2u * srcALen) - 1u;
-
-    /* When srcALen > srcBLen, zero padding is done to srcB        
-     * to make their lengths equal.        
-     * Instead, (outBlockSize - (srcALen + srcBLen - 1))        
-     * number of output samples are made zero */
-    j = outBlockSize - (srcALen + (srcBLen - 1u));
-
-    /* Updating the pointer position to non zero value */
-    pOut += j;
-
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcB);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcA);
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-
-    /* CORR(x, y) = Reverse order(CORR(y, x)) */
-    /* Hence set the destination pointer to point to the last output sample */
-    pOut = pDst + ((srcALen + srcBLen) - 2u);
-
-    /* Destination address modifier is set to -1 */
-    inc = -1;
-
-  }
-
-
-  /* Copy (srcBLen) samples in scratch buffer */
-  k = srcBLen >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    x4 = (q15_t) * pIn2++;
-    *pScr2++ = x4;
-    x4 = (q15_t) * pIn2++;
-    *pScr2++ = x4;
-    x4 = (q15_t) * pIn2++;
-    *pScr2++ = x4;
-    x4 = (q15_t) * pIn2++;
-    *pScr2++ = x4;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  k = srcBLen % 0x4u;
-
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    x4 = (q15_t) * pIn2++;
-    *pScr2++ = x4;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* Fill (srcBLen - 1u) zeros in scratch buffer */
-  arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-  /* Update temporary scratch pointer */
-  pScr1 += (srcBLen - 1u);
-
-  /* Copy (srcALen) samples in scratch buffer */
-  k = srcALen >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    x4 = (q15_t) * pIn1++;
-    *pScr1++ = x4;
-    x4 = (q15_t) * pIn1++;
-    *pScr1++ = x4;
-    x4 = (q15_t) * pIn1++;
-    *pScr1++ = x4;
-    x4 = (q15_t) * pIn1++;
-    *pScr1++ = x4;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  k = srcALen % 0x4u;
-
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    x4 = (q15_t) * pIn1++;
-    *pScr1++ = x4;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-  /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
-  arm_fill_q15(0, pScr1, (srcBLen - 1u));
-
-  /* Update pointer */
-  pScr1 += (srcBLen - 1u);
-
-#else
-
-/* Apply loop unrolling and do 4 Copies simultaneously. */
-  k = (srcBLen - 1u) >> 2u;
-
-  /* First part of the processing with loop unrolling copies 4 data points at a time.       
-   ** a second loop below copies for the remaining 1 to 3 samples. */
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner */
-    *pScr1++ = 0;
-    *pScr1++ = 0;
-    *pScr1++ = 0;
-    *pScr1++ = 0;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-  /* If the count is not a multiple of 4, copy remaining samples here.       
-   ** No loop unrolling is used. */
-  k = (srcBLen - 1u) % 0x4u;
-
-  while(k > 0u)
-  {
-    /* copy second buffer in reversal manner for remaining samples */
-    *pScr1++ = 0;
-
-    /* Decrement the loop counter */
-    k--;
-  }
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-  /* Temporary pointer for second sequence */
-  py = pScratch2;
-
-  /* Initialization of pScr2 pointer */
-  pScr2 = pScratch2;
-
-  /* Actual correlation process starts here */
-  blkCnt = (srcALen + srcBLen - 1u) >> 2;
-
-  while(blkCnt > 0)
-  {
-    /* Initialze temporary scratch pointer as scratch1 */
-    pScr1 = pScratch1;
-
-    /* Clear Accumlators */
-    acc0 = 0;
-    acc1 = 0;
-    acc2 = 0;
-    acc3 = 0;
-
-    /* Read two samples from scratch1 buffer */
-    x1 = *__SIMD32(pScr1)++;
-
-    /* Read next two samples from scratch1 buffer */
-    x2 = *__SIMD32(pScr1)++;
-
-    tapCnt = (srcBLen) >> 2u;
-
-    while(tapCnt > 0u)
-    {
-
-      /* Read four samples from smaller buffer */
-      y1 = _SIMD32_OFFSET(pScr2);
-
-      /* multiply and accumlate */
-      acc0 = __SMLAD(x1, y1, acc0);
-      acc2 = __SMLAD(x2, y1, acc2);
-
-      /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      /* multiply and accumlate */
-      acc1 = __SMLADX(x3, y1, acc1);
-
-      /* Read next two samples from scratch1 buffer */
-      x1 = *__SIMD32(pScr1)++;
-
-      /* pack input data */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x1, x2, 0);
-#else
-      x3 = __PKHBT(x2, x1, 0);
-#endif
-
-      acc3 = __SMLADX(x3, y1, acc3);
-
-      /* Read four samples from smaller buffer */
-      y1 = _SIMD32_OFFSET(pScr2 + 2u);
-
-      acc0 = __SMLAD(x2, y1, acc0);
-
-      acc2 = __SMLAD(x1, y1, acc2);
-
-      acc1 = __SMLADX(x3, y1, acc1);
-
-      x2 = *__SIMD32(pScr1)++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-      x3 = __PKHBT(x2, x1, 0);
-#else
-      x3 = __PKHBT(x1, x2, 0);
-#endif
-
-      acc3 = __SMLADX(x3, y1, acc3);
-
-      pScr2 += 4u;
-
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-
-
-    /* Update scratch pointer for remaining samples of smaller length sequence */
-    pScr1 -= 4u;
-
-
-    /* apply same above for remaining samples of smaller length sequence */
-    tapCnt = (srcBLen) & 3u;
-
-    while(tapCnt > 0u)
-    {
-
-      /* accumlate the results */
-      acc0 += (*pScr1++ * *pScr2);
-      acc1 += (*pScr1++ * *pScr2);
-      acc2 += (*pScr1++ * *pScr2);
-      acc3 += (*pScr1++ * *pScr2++);
-
-      pScr1 -= 3u;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    blkCnt--;
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = (q7_t) (__SSAT(acc0 >> 7u, 8));
-    pOut += inc;
-    *pOut = (q7_t) (__SSAT(acc1 >> 7u, 8));
-    pOut += inc;
-    *pOut = (q7_t) (__SSAT(acc2 >> 7u, 8));
-    pOut += inc;
-    *pOut = (q7_t) (__SSAT(acc3 >> 7u, 8));
-    pOut += inc;
-
-    /* Initialization of inputB pointer */
-    pScr2 = py;
-
-    pScratch1 += 4u;
-
-  }
-
-
-  blkCnt = (srcALen + srcBLen - 1u) & 0x3;
-
-  /* Calculate correlation for remaining samples of Bigger length sequence */
-  while(blkCnt > 0)
-  {
-    /* Initialze temporary scratch pointer as scratch1 */
-    pScr1 = pScratch1;
-
-    /* Clear Accumlators */
-    acc0 = 0;
-
-    tapCnt = (srcBLen) >> 1u;
-
-    while(tapCnt > 0u)
-    {
-      acc0 += (*pScr1++ * *pScr2++);
-      acc0 += (*pScr1++ * *pScr2++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    tapCnt = (srcBLen) & 1u;
-
-    /* apply same above for remaining samples of smaller length sequence */
-    while(tapCnt > 0u)
-    {
-
-      /* accumlate the results */
-      acc0 += (*pScr1++ * *pScr2++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    blkCnt--;
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = (q7_t) (__SSAT(acc0 >> 7u, 8));
-
-    pOut += inc;
-
-    /* Initialization of inputB pointer */
-    pScr2 = py;
-
-    pScratch1 += 1u;
-
-  }
-
-}
-
-/**    
- * @} end of Corr group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q15.c
deleted file mode 100644
index 1832424890..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q15.c
+++ /dev/null
@@ -1,718 +0,0 @@
-/* ----------------------------------------------------------------------   
-* Copyright (C) 2010 ARM Limited. All rights reserved.   
-*   
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*   
-* Project: 	    CMSIS DSP Library   
-* Title:		arm_correlate_q15.c   
-*   
-* Description:	Correlation of Q15 sequences. 
-*   
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*
-* Version 1.0.11 2011/10/18 
-*    Bug Fix in conv, correlation, partial convolution. 
-*
-* Version 1.0.10 2011/7/15 
-*    Big Endian support added and Merged M0 and M3/M4 Source code.  
-*   
-* Version 1.0.3 2010/11/29  
-*    Re-organized the CMSIS folders and updated documentation.   
-*    
-* Version 1.0.2 2010/11/11   
-*    Documentation updated.    
-*   
-* Version 1.0.1 2010/10/05    
-*    Production release and review comments incorporated.   
-*   
-* Version 1.0.0 2010/09/20    
-*    Production release and review comments incorporated   
-*   
-* Version 0.0.7  2010/06/10    
-*    Misra-C changes done   
-*   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**   
- * @ingroup groupFilters   
- */
-
-/**   
- * @addtogroup Corr   
- * @{   
- */
-
-/**   
- * @brief Correlation of Q15 sequences. 
- * @param[in] *pSrcA points to the first input sequence.   
- * @param[in] srcALen length of the first input sequence.   
- * @param[in] *pSrcB points to the second input sequence.   
- * @param[in] srcBLen length of the second input sequence.   
- * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   
- * @return none.   
- *   
- * @details   
- * Scaling and Overflow Behavior:   
- *   
- * \par   
- * The function is implemented using a 64-bit internal accumulator.   
- * Both inputs are in 1.15 format and multiplications yield a 2.30 result.   
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
- * This approach provides 33 guard bits and there is no risk of overflow.   
- * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.   
- *   
- * \par   
- * Refer to arm_correlate_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4. 
- *
- * \par    
- * Refer the function arm_correlate_opt_q15() for a faster implementation of this function using scratch buffers.
- * 
- */
-
-void arm_correlate_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst)
-{
-
-#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q15_t *pIn1;                                   /* inputA pointer               */
-  q15_t *pIn2;                                   /* inputB pointer               */
-  q15_t *pOut = pDst;                            /* output pointer               */
-  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
-  q15_t *px;                                     /* Intermediate inputA pointer  */
-  q15_t *py;                                     /* Intermediate inputB pointer  */
-  q15_t *pSrc1;                                  /* Intermediate pointers        */
-  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
-  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
-  int32_t inc = 1;                               /* Destination address modifier */
-
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  /* But CORR(x, y) is reverse of CORR(y, x) */
-  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
-  /* and the destination pointer modifier, inc is set to -1 */
-  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
-  /* But to improve the performance,   
-   * we include zeroes in the output instead of zero padding either of the the inputs*/
-  /* If srcALen > srcBLen,   
-   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
-  /* If srcALen < srcBLen,   
-   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcA);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcB);
-
-    /* Number of output samples is calculated */
-    outBlockSize = (2u * srcALen) - 1u;
-
-    /* When srcALen > srcBLen, zero padding is done to srcB   
-     * to make their lengths equal.   
-     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
-     * number of output samples are made zero */
-    j = outBlockSize - (srcALen + (srcBLen - 1u));
-
-    /* Updating the pointer position to non zero value */
-    pOut += j;
-
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcB);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcA);
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-
-    /* CORR(x, y) = Reverse order(CORR(y, x)) */
-    /* Hence set the destination pointer to point to the last output sample */
-    pOut = pDst + ((srcALen + srcBLen) - 2u);
-
-    /* Destination address modifier is set to -1 */
-    inc = -1;
-
-  }
-
-  /* The function is internally   
-   * divided into three parts according to the number of multiplications that has to be   
-   * taken place between inputA samples and inputB samples. In the first part of the   
-   * algorithm, the multiplications increase by one for every iteration.   
-   * In the second part of the algorithm, srcBLen number of multiplications are done.   
-   * In the third part of the algorithm, the multiplications decrease by one   
-   * for every iteration.*/
-  /* The algorithm is implemented in three stages.   
-   * The loop counters of each stage is initiated here. */
-  blockSize1 = srcBLen - 1u;
-  blockSize2 = srcALen - (srcBLen - 1u);
-  blockSize3 = blockSize1;
-
-  /* --------------------------   
-   * Initializations of stage1   
-   * -------------------------*/
-
-  /* sum = x[0] * y[srcBlen - 1]   
-   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   
-   * ....   
-   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
-   */
-
-  /* In this stage the MAC operations are increased by 1 for every iteration.   
-     The count variable holds the number of MAC operations performed */
-  count = 1u;
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  pSrc1 = pIn2 + (srcBLen - 1u);
-  py = pSrc1;
-
-  /* ------------------------   
-   * Stage1 process   
-   * ----------------------*/
-
-  /* The first loop starts here */
-  while(blockSize1 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
-      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
-      /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */
-      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* x[0] * y[srcBLen - 1] */
-      sum = __SMLALD(*px++, *py++, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = (q15_t) (__SSAT((sum >> 15), 16));
-    /* Destination pointer is updated according to the address modifier, inc */
-    pOut += inc;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pSrc1 - count;
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* --------------------------   
-   * Initializations of stage2   
-   * ------------------------*/
-
-  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
-   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
-   * ....   
-   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
-   */
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-  /* count is index by which the pointer pIn1 to be incremented */
-  count = 0u;
-
-  /* -------------------   
-   * Stage2 process   
-   * ------------------*/
-
-  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
-   * So, to loop unroll over blockSize2,   
-   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
-  if(srcBLen >= 4u)
-  {
-    /* Loop unroll over blockSize2, by 4 */
-    blkCnt = blockSize2 >> 2u;
-
-    while(blkCnt > 0u)
-    {
-      /* Set all accumulators to zero */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-      /* read x[0], x[1] samples */
-      x0 = *__SIMD32(px);
-      /* read x[1], x[2] samples */
-      x1 = _SIMD32_OFFSET(px + 1);
-	  px += 2u;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      do
-      {
-        /* Read the first two inputB samples using SIMD:   
-         * y[0] and y[1] */
-        c0 = *__SIMD32(py)++;
-
-        /* acc0 +=  x[0] * y[0] + x[1] * y[1] */
-        acc0 = __SMLALD(x0, c0, acc0);
-
-        /* acc1 +=  x[1] * y[0] + x[2] * y[1] */
-        acc1 = __SMLALD(x1, c0, acc1);
-
-        /* Read x[2], x[3] */
-        x2 = *__SIMD32(px);
-
-        /* Read x[3], x[4] */
-        x3 = _SIMD32_OFFSET(px + 1);
-
-        /* acc2 +=  x[2] * y[0] + x[3] * y[1] */
-        acc2 = __SMLALD(x2, c0, acc2);
-
-        /* acc3 +=  x[3] * y[0] + x[4] * y[1] */
-        acc3 = __SMLALD(x3, c0, acc3);
-
-        /* Read y[2] and y[3] */
-        c0 = *__SIMD32(py)++;
-
-        /* acc0 +=  x[2] * y[2] + x[3] * y[3] */
-        acc0 = __SMLALD(x2, c0, acc0);
-
-        /* acc1 +=  x[3] * y[2] + x[4] * y[3] */
-        acc1 = __SMLALD(x3, c0, acc1);
-
-        /* Read x[4], x[5] */
-        x0 = _SIMD32_OFFSET(px + 2);
-
-        /* Read x[5], x[6] */
-        x1 = _SIMD32_OFFSET(px + 3);
-
-		px += 4u;
-
-        /* acc2 +=  x[4] * y[2] + x[5] * y[3] */
-        acc2 = __SMLALD(x0, c0, acc2);
-
-        /* acc3 +=  x[5] * y[2] + x[6] * y[3] */
-        acc3 = __SMLALD(x1, c0, acc3);
-
-      } while(--k);
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      if(k == 1u)
-      {
-        /* Read y[4] */
-        c0 = *py;
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-
-#else
-
-        c0 = c0 & 0x0000FFFF;
-
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-        /* Read x[7] */
-        x3 = *__SIMD32(px);
-		px++;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLALD(x0, c0, acc0);
-        acc1 = __SMLALD(x1, c0, acc1);
-        acc2 = __SMLALDX(x1, c0, acc2);
-        acc3 = __SMLALDX(x3, c0, acc3);
-      }
-
-      if(k == 2u)
-      {
-        /* Read y[4], y[5] */
-        c0 = *__SIMD32(py);
-
-        /* Read x[7], x[8] */
-        x3 = *__SIMD32(px);
-
-        /* Read x[9] */
-        x2 = _SIMD32_OFFSET(px + 1);
-		px += 2u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLALD(x0, c0, acc0);
-        acc1 = __SMLALD(x1, c0, acc1);
-        acc2 = __SMLALD(x3, c0, acc2);
-        acc3 = __SMLALD(x2, c0, acc3);
-      }
-
-      if(k == 3u)
-      {
-        /* Read y[4], y[5] */
-        c0 = *__SIMD32(py)++;
-
-        /* Read x[7], x[8] */
-        x3 = *__SIMD32(px);
-
-        /* Read x[9] */
-        x2 = _SIMD32_OFFSET(px + 1);
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLALD(x0, c0, acc0);
-        acc1 = __SMLALD(x1, c0, acc1);
-        acc2 = __SMLALD(x3, c0, acc2);
-        acc3 = __SMLALD(x2, c0, acc3);
-
-        c0 = (*py);
-
-        /* Read y[6] */
-#ifdef  ARM_MATH_BIG_ENDIAN
-
-        c0 = c0 << 16u;
-#else
-
-        c0 = c0 & 0x0000FFFF;
-#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
-        /* Read x[10] */
-        x3 = _SIMD32_OFFSET(px + 2);
-		px += 3u;
-
-        /* Perform the multiply-accumulates */
-        acc0 = __SMLALDX(x1, c0, acc0);
-        acc1 = __SMLALD(x2, c0, acc1);
-        acc2 = __SMLALDX(x2, c0, acc2);
-        acc3 = __SMLALDX(x3, c0, acc3);
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q15_t) (__SSAT(acc0 >> 15, 16));
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      *pOut = (q15_t) (__SSAT(acc1 >> 15, 16));
-      pOut += inc;
-
-      *pOut = (q15_t) (__SSAT(acc2 >> 15, 16));
-      pOut += inc;
-
-      *pOut = (q15_t) (__SSAT(acc3 >> 15, 16));
-      pOut += inc;
-
-      /* Increment the count by 4 as 4 output values are computed */
-      count += 4u;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
-     ** No loop unrolling is used. */
-    blkCnt = blockSize2 % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += ((q63_t) * px++ * *py++);
-        sum += ((q63_t) * px++ * *py++);
-        sum += ((q63_t) * px++ * *py++);
-        sum += ((q63_t) * px++ * *py++);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += ((q63_t) * px++ * *py++);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q15_t) (__SSAT(sum >> 15, 16));
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      /* Increment count by 1, as one output value is computed */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-  else
-  {
-    /* If the srcBLen is not a multiple of 4,   
-     * the blockSize2 loop cannot be unrolled by 4 */
-    blkCnt = blockSize2;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Loop over srcBLen */
-      k = srcBLen;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += ((q63_t) * px++ * *py++);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q15_t) (__SSAT(sum >> 15, 16));
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-
-  /* --------------------------   
-   * Initializations of stage3   
-   * -------------------------*/
-
-  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
-   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
-   * ....   
-   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
-   * sum +=  x[srcALen-1] * y[0]   
-   */
-
-  /* In this stage the MAC operations are decreased by 1 for every iteration.   
-     The count variable holds the number of MAC operations performed */
-  count = srcBLen - 1u;
-
-  /* Working pointer of inputA */
-  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
-  px = pSrc1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-  /* -------------------   
-   * Stage3 process   
-   * ------------------*/
-
-  while(blockSize3 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */
-      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
-      /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */
-      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      sum = __SMLALD(*px++, *py++, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = (q15_t) (__SSAT((sum >> 15), 16));
-    /* Destination pointer is updated according to the address modifier, inc */
-    pOut += inc;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pIn2;
-
-    /* Decrement the MAC count */
-    count--;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-  }
-
-#else
-
-/* Run the below code for Cortex-M0 */
-
-  q15_t *pIn1 = pSrcA;                           /* inputA pointer               */
-  q15_t *pIn2 = pSrcB + (srcBLen - 1u);          /* inputB pointer               */
-  q63_t sum;                                     /* Accumulators                  */
-  uint32_t i = 0u, j;                            /* loop counters */
-  uint32_t inv = 0u;                             /* Reverse order flag */
-  uint32_t tot = 0u;                             /* Length */
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  /* But CORR(x, y) is reverse of CORR(y, x) */
-  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
-  /* and a varaible, inv is set to 1 */
-  /* If lengths are not equal then zero pad has to be done to  make the two   
-   * inputs of same length. But to improve the performance, we include zeroes   
-   * in the output instead of zero padding either of the the inputs*/
-  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the   
-   * starting of the output buffer */
-  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the  
-   * ending of the output buffer */
-  /* Once the zero padding is done the remaining of the output is calcualted  
-   * using convolution but with the shorter signal time shifted. */
-
-  /* Calculate the length of the remaining sequence */
-  tot = ((srcALen + srcBLen) - 2u);
-
-  if(srcALen > srcBLen)
-  {
-    /* Calculating the number of zeros to be padded to the output */
-    j = srcALen - srcBLen;
-
-    /* Initialise the pointer after zero padding */
-    pDst += j;
-  }
-
-  else if(srcALen < srcBLen)
-  {
-    /* Initialization to inputB pointer */
-    pIn1 = pSrcB;
-
-    /* Initialization to the end of inputA pointer */
-    pIn2 = pSrcA + (srcALen - 1u);
-
-    /* Initialisation of the pointer after zero padding */
-    pDst = pDst + tot;
-
-    /* Swapping the lengths */
-    j = srcALen;
-    srcALen = srcBLen;
-    srcBLen = j;
-
-    /* Setting the reverse flag */
-    inv = 1;
-
-  }
-
-  /* Loop to calculate convolution for output length number of times */
-  for (i = 0u; i <= tot; i++)
-  {
-    /* Initialize sum with zero to carry on MAC operations */
-    sum = 0;
-
-    /* Loop to perform MAC operations according to convolution equation */
-    for (j = 0u; j <= i; j++)
-    {
-      /* Check the array limitations */
-      if((((i - j) < srcBLen) && (j < srcALen)))
-      {
-        /* z[i] += x[i-j] * y[j] */
-        sum += ((q31_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
-      }
-    }
-    /* Store the output in the destination buffer */
-    if(inv == 1)
-      *pDst-- = (q15_t) __SSAT((sum >> 15u), 16u);
-    else
-      *pDst++ = (q15_t) __SSAT((sum >> 15u), 16u);
-  }
-
-#endif /*#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE) */
-
-}
-
-/**   
- * @} end of Corr group   
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q31.c
deleted file mode 100644
index 8d0a0c3b12..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q31.c
+++ /dev/null
@@ -1,664 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_correlate_q31.c    
-*    
-* Description:	Correlation of Q31 sequences.  
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.11 2011/10/18  
-*    Bug Fix in conv, correlation, partial convolution.  
-* 
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-*    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup Corr    
- * @{    
- */
-
-/**    
- * @brief Correlation of Q31 sequences.    
- * @param[in] *pSrcA points to the first input sequence.    
- * @param[in] srcALen length of the first input sequence.    
- * @param[in] *pSrcB points to the second input sequence.    
- * @param[in] srcBLen length of the second input sequence.    
- * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The function is implemented using an internal 64-bit accumulator.    
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
- * There is no saturation on intermediate additions.    
- * Thus, if the accumulator overflows it wraps around and distorts the result.    
- * The input signals should be scaled down to avoid intermediate overflows.    
- * Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a    
- * maximum of min(srcALen, srcBLen) number of additions is carried internally.    
- * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.    
- *    
- * \par    
- * See arm_correlate_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.    
- */
-
-void arm_correlate_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst)
-{
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t *pIn1;                                   /* inputA pointer               */
-  q31_t *pIn2;                                   /* inputB pointer               */
-  q31_t *pOut = pDst;                            /* output pointer               */
-  q31_t *px;                                     /* Intermediate inputA pointer  */
-  q31_t *py;                                     /* Intermediate inputB pointer  */
-  q31_t *pSrc1;                                  /* Intermediate pointers        */
-  q63_t sum, acc0, acc1, acc2;                   /* Accumulators                  */
-  q31_t x0, x1, x2, c0;                          /* temporary variables for holding input and coefficient values */
-  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
-  int32_t inc = 1;                               /* Destination address modifier */
-
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  /* But CORR(x, y) is reverse of CORR(y, x) */
-  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
-  /* and the destination pointer modifier, inc is set to -1 */
-  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
-  /* But to improve the performance,    
-   * we include zeroes in the output instead of zero padding either of the the inputs*/
-  /* If srcALen > srcBLen,    
-   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
-  /* If srcALen < srcBLen,    
-   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcA);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcB);
-
-    /* Number of output samples is calculated */
-    outBlockSize = (2u * srcALen) - 1u;
-
-    /* When srcALen > srcBLen, zero padding is done to srcB    
-     * to make their lengths equal.    
-     * Instead, (outBlockSize - (srcALen + srcBLen - 1))    
-     * number of output samples are made zero */
-    j = outBlockSize - (srcALen + (srcBLen - 1u));
-
-    /* Updating the pointer position to non zero value */
-    pOut += j;
-
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcB);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcA);
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-
-    /* CORR(x, y) = Reverse order(CORR(y, x)) */
-    /* Hence set the destination pointer to point to the last output sample */
-    pOut = pDst + ((srcALen + srcBLen) - 2u);
-
-    /* Destination address modifier is set to -1 */
-    inc = -1;
-
-  }
-
-  /* The function is internally    
-   * divided into three parts according to the number of multiplications that has to be    
-   * taken place between inputA samples and inputB samples. In the first part of the    
-   * algorithm, the multiplications increase by one for every iteration.    
-   * In the second part of the algorithm, srcBLen number of multiplications are done.    
-   * In the third part of the algorithm, the multiplications decrease by one    
-   * for every iteration.*/
-  /* The algorithm is implemented in three stages.    
-   * The loop counters of each stage is initiated here. */
-  blockSize1 = srcBLen - 1u;
-  blockSize2 = srcALen - (srcBLen - 1u);
-  blockSize3 = blockSize1;
-
-  /* --------------------------    
-   * Initializations of stage1    
-   * -------------------------*/
-
-  /* sum = x[0] * y[srcBlen - 1]    
-   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]    
-   * ....    
-   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]    
-   */
-
-  /* In this stage the MAC operations are increased by 1 for every iteration.    
-     The count variable holds the number of MAC operations performed */
-  count = 1u;
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  pSrc1 = pIn2 + (srcBLen - 1u);
-  py = pSrc1;
-
-  /* ------------------------    
-   * Stage1 process    
-   * ----------------------*/
-
-  /* The first stage starts here */
-  while(blockSize1 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* x[0] * y[srcBLen - 4] */
-      sum += (q63_t) * px++ * (*py++);
-      /* x[1] * y[srcBLen - 3] */
-      sum += (q63_t) * px++ * (*py++);
-      /* x[2] * y[srcBLen - 2] */
-      sum += (q63_t) * px++ * (*py++);
-      /* x[3] * y[srcBLen - 1] */
-      sum += (q63_t) * px++ * (*py++);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.    
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* x[0] * y[srcBLen - 1] */
-      sum += (q63_t) * px++ * (*py++);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = (q31_t) (sum >> 31);
-    /* Destination pointer is updated according to the address modifier, inc */
-    pOut += inc;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pSrc1 - count;
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* --------------------------    
-   * Initializations of stage2    
-   * ------------------------*/
-
-  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]    
-   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]    
-   * ....    
-   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
-   */
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-  /* count is index by which the pointer pIn1 to be incremented */
-  count = 0u;
-
-  /* -------------------    
-   * Stage2 process    
-   * ------------------*/
-
-  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.    
-   * So, to loop unroll over blockSize2,    
-   * srcBLen should be greater than or equal to 4 */
-  if(srcBLen >= 4u)
-  {
-    /* Loop unroll by 3 */
-    blkCnt = blockSize2 / 3;
-
-    while(blkCnt > 0u)
-    {
-      /* Set all accumulators to zero */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-
-      /* read x[0], x[1] samples */
-      x0 = *(px++);
-      x1 = *(px++);
-
-      /* Apply loop unrolling and compute 3 MACs simultaneously. */
-      k = srcBLen / 3;
-
-      /* First part of the processing with loop unrolling.  Compute 3 MACs at a time.        
-       ** a second loop below computes MACs for the remaining 1 to 2 samples. */
-      do
-      {
-        /* Read y[0] sample */
-        c0 = *(py);
-
-        /* Read x[2] sample */
-        x2 = *(px);
-
-        /* Perform the multiply-accumulate */
-        /* acc0 +=  x[0] * y[0] */
-        acc0 += ((q63_t) x0 * c0);
-        /* acc1 +=  x[1] * y[0] */
-        acc1 += ((q63_t) x1 * c0);
-        /* acc2 +=  x[2] * y[0] */
-        acc2 += ((q63_t) x2 * c0);
-
-        /* Read y[1] sample */
-        c0 = *(py + 1u);
-
-        /* Read x[3] sample */
-        x0 = *(px + 1u);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[1] * y[1] */
-        acc0 += ((q63_t) x1 * c0);
-        /* acc1 +=  x[2] * y[1] */
-        acc1 += ((q63_t) x2 * c0);
-        /* acc2 +=  x[3] * y[1] */
-        acc2 += ((q63_t) x0 * c0);
-
-        /* Read y[2] sample */
-        c0 = *(py + 2u);
-
-        /* Read x[4] sample */
-        x1 = *(px + 2u);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[2] * y[2] */
-        acc0 += ((q63_t) x2 * c0);
-        /* acc1 +=  x[3] * y[2] */
-        acc1 += ((q63_t) x0 * c0);
-        /* acc2 +=  x[4] * y[2] */
-        acc2 += ((q63_t) x1 * c0);
-
-        /* update scratch pointers */
-        px += 3u;
-        py += 3u;
-
-      } while(--k);
-
-      /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.        
-       ** No loop unrolling is used. */
-      k = srcBLen - (3 * (srcBLen / 3));
-
-      while(k > 0u)
-      {
-        /* Read y[4] sample */
-        c0 = *(py++);
-
-        /* Read x[7] sample */
-        x2 = *(px++);
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[4] * y[4] */
-        acc0 += ((q63_t) x0 * c0);
-        /* acc1 +=  x[5] * y[4] */
-        acc1 += ((q63_t) x1 * c0);
-        /* acc2 +=  x[6] * y[4] */
-        acc2 += ((q63_t) x2 * c0);
-
-        /* Reuse the present samples for the next MAC */
-        x0 = x1;
-        x1 = x2;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q31_t) (acc0 >> 31);
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      *pOut = (q31_t) (acc1 >> 31);
-      pOut += inc;
-
-      *pOut = (q31_t) (acc2 >> 31);
-      pOut += inc;
-
-      /* Increment the pointer pIn1 index, count by 3 */
-      count += 3u;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.        
-     ** No loop unrolling is used. */
-    blkCnt = blockSize2 - 3 * (blockSize2 / 3);
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += (q63_t) * px++ * (*py++);
-        sum += (q63_t) * px++ * (*py++);
-        sum += (q63_t) * px++ * (*py++);
-        sum += (q63_t) * px++ * (*py++);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.    
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += (q63_t) * px++ * (*py++);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q31_t) (sum >> 31);
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-  else
-  {
-    /* If the srcBLen is not a multiple of 4,    
-     * the blockSize2 loop cannot be unrolled by 4 */
-    blkCnt = blockSize2;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Loop over srcBLen */
-      k = srcBLen;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += (q63_t) * px++ * (*py++);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q31_t) (sum >> 31);
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-
-  /* --------------------------    
-   * Initializations of stage3    
-   * -------------------------*/
-
-  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
-   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]    
-   * ....    
-   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]    
-   * sum +=  x[srcALen-1] * y[0]    
-   */
-
-  /* In this stage the MAC operations are decreased by 1 for every iteration.    
-     The count variable holds the number of MAC operations performed */
-  count = srcBLen - 1u;
-
-  /* Working pointer of inputA */
-  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
-  px = pSrc1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-  /* -------------------    
-   * Stage3 process    
-   * ------------------*/
-
-  while(blockSize3 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.    
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* sum += x[srcALen - srcBLen + 4] * y[3] */
-      sum += (q63_t) * px++ * (*py++);
-      /* sum += x[srcALen - srcBLen + 3] * y[2] */
-      sum += (q63_t) * px++ * (*py++);
-      /* sum += x[srcALen - srcBLen + 2] * y[1] */
-      sum += (q63_t) * px++ * (*py++);
-      /* sum += x[srcALen - srcBLen + 1] * y[0] */
-      sum += (q63_t) * px++ * (*py++);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.    
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      sum += (q63_t) * px++ * (*py++);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = (q31_t) (sum >> 31);
-    /* Destination pointer is updated according to the address modifier, inc */
-    pOut += inc;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pIn2;
-
-    /* Decrement the MAC count */
-    count--;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q31_t *pIn1 = pSrcA;                           /* inputA pointer               */
-  q31_t *pIn2 = pSrcB + (srcBLen - 1u);          /* inputB pointer               */
-  q63_t sum;                                     /* Accumulators                  */
-  uint32_t i = 0u, j;                            /* loop counters */
-  uint32_t inv = 0u;                             /* Reverse order flag */
-  uint32_t tot = 0u;                             /* Length */
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  /* But CORR(x, y) is reverse of CORR(y, x) */
-  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
-  /* and a varaible, inv is set to 1 */
-  /* If lengths are not equal then zero pad has to be done to  make the two    
-   * inputs of same length. But to improve the performance, we include zeroes    
-   * in the output instead of zero padding either of the the inputs*/
-  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the    
-   * starting of the output buffer */
-  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the   
-   * ending of the output buffer */
-  /* Once the zero padding is done the remaining of the output is calcualted   
-   * using correlation but with the shorter signal time shifted. */
-
-  /* Calculate the length of the remaining sequence */
-  tot = ((srcALen + srcBLen) - 2u);
-
-  if(srcALen > srcBLen)
-  {
-    /* Calculating the number of zeros to be padded to the output */
-    j = srcALen - srcBLen;
-
-    /* Initialise the pointer after zero padding */
-    pDst += j;
-  }
-
-  else if(srcALen < srcBLen)
-  {
-    /* Initialization to inputB pointer */
-    pIn1 = pSrcB;
-
-    /* Initialization to the end of inputA pointer */
-    pIn2 = pSrcA + (srcALen - 1u);
-
-    /* Initialisation of the pointer after zero padding */
-    pDst = pDst + tot;
-
-    /* Swapping the lengths */
-    j = srcALen;
-    srcALen = srcBLen;
-    srcBLen = j;
-
-    /* Setting the reverse flag */
-    inv = 1;
-
-  }
-
-  /* Loop to calculate correlation for output length number of times */
-  for (i = 0u; i <= tot; i++)
-  {
-    /* Initialize sum with zero to carry on MAC operations */
-    sum = 0;
-
-    /* Loop to perform MAC operations according to correlation equation */
-    for (j = 0u; j <= i; j++)
-    {
-      /* Check the array limitations */
-      if((((i - j) < srcBLen) && (j < srcALen)))
-      {
-        /* z[i] += x[i-j] * y[j] */
-        sum += ((q63_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
-      }
-    }
-    /* Store the output in the destination buffer */
-    if(inv == 1)
-      *pDst-- = (q31_t) (sum >> 31u);
-    else
-      *pDst++ = (q31_t) (sum >> 31u);
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
- * @} end of Corr group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q7.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q7.c
deleted file mode 100644
index eb2ddff999..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q7.c
+++ /dev/null
@@ -1,789 +0,0 @@
-/* ----------------------------------------------------------------------   
-* Copyright (C) 2010 ARM Limited. All rights reserved.   
-*   
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*   
-* Project: 	    CMSIS DSP Library   
-* Title:		arm_correlate_q7.c   
-*   
-* Description:	Correlation of Q7 sequences. 
-*   
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*
-* Version 1.0.11 2011/10/18 
-*    Bug Fix in conv, correlation, partial convolution. 
-*
-* Version 1.0.10 2011/7/15 
-*    Big Endian support added and Merged M0 and M3/M4 Source code.  
-*   
-* Version 1.0.3 2010/11/29  
-*    Re-organized the CMSIS folders and updated documentation.   
-*    
-* Version 1.0.2 2010/11/11   
-*    Documentation updated.    
-*   
-* Version 1.0.1 2010/10/05    
-*    Production release and review comments incorporated.   
-*   
-* Version 1.0.0 2010/09/20    
-*    Production release and review comments incorporated   
-*   
-* Version 0.0.7  2010/06/10    
-*    Misra-C changes done   
-*   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**   
- * @ingroup groupFilters   
- */
-
-/**   
- * @addtogroup Corr   
- * @{   
- */
-
-/**   
- * @brief Correlation of Q7 sequences.   
- * @param[in] *pSrcA points to the first input sequence.   
- * @param[in] srcALen length of the first input sequence.   
- * @param[in] *pSrcB points to the second input sequence.   
- * @param[in] srcBLen length of the second input sequence.   
- * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   
- * @return none.   
- *   
- * @details   
- * Scaling and Overflow Behavior:   
- *   
- * \par   
- * The function is implemented using a 32-bit internal accumulator.   
- * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.   
- * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.   
- * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.   
- * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format.   
- *
- * \par    
- * Refer the function arm_correlate_opt_q7() for a faster implementation of this function.
- * 
- */
-
-void arm_correlate_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst)
-{
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q7_t *pIn1;                                    /* inputA pointer               */
-  q7_t *pIn2;                                    /* inputB pointer               */
-  q7_t *pOut = pDst;                             /* output pointer               */
-  q7_t *px;                                      /* Intermediate inputA pointer  */
-  q7_t *py;                                      /* Intermediate inputB pointer  */
-  q7_t *pSrc1;                                   /* Intermediate pointers        */
-  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
-  q31_t input1, input2;                          /* temporary variables */
-  q15_t in1, in2;                                /* temporary variables */
-  q7_t x0, x1, x2, x3, c0, c1;                   /* temporary variables for holding input and coefficient values */
-  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
-  int32_t inc = 1;
-
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  /* But CORR(x, y) is reverse of CORR(y, x) */
-  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
-  /* and the destination pointer modifier, inc is set to -1 */
-  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
-  /* But to improve the performance,   
-   * we include zeroes in the output instead of zero padding either of the the inputs*/
-  /* If srcALen > srcBLen,   
-   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
-  /* If srcALen < srcBLen,   
-   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
-  if(srcALen >= srcBLen)
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcA);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcB);
-
-    /* Number of output samples is calculated */
-    outBlockSize = (2u * srcALen) - 1u;
-
-    /* When srcALen > srcBLen, zero padding is done to srcB   
-     * to make their lengths equal.   
-     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
-     * number of output samples are made zero */
-    j = outBlockSize - (srcALen + (srcBLen - 1u));
-
-    /* Updating the pointer position to non zero value */
-    pOut += j;
-
-  }
-  else
-  {
-    /* Initialization of inputA pointer */
-    pIn1 = (pSrcB);
-
-    /* Initialization of inputB pointer */
-    pIn2 = (pSrcA);
-
-    /* srcBLen is always considered as shorter or equal to srcALen */
-    j = srcBLen;
-    srcBLen = srcALen;
-    srcALen = j;
-
-    /* CORR(x, y) = Reverse order(CORR(y, x)) */
-    /* Hence set the destination pointer to point to the last output sample */
-    pOut = pDst + ((srcALen + srcBLen) - 2u);
-
-    /* Destination address modifier is set to -1 */
-    inc = -1;
-
-  }
-
-  /* The function is internally   
-   * divided into three parts according to the number of multiplications that has to be   
-   * taken place between inputA samples and inputB samples. In the first part of the   
-   * algorithm, the multiplications increase by one for every iteration.   
-   * In the second part of the algorithm, srcBLen number of multiplications are done.   
-   * In the third part of the algorithm, the multiplications decrease by one   
-   * for every iteration.*/
-  /* The algorithm is implemented in three stages.   
-   * The loop counters of each stage is initiated here. */
-  blockSize1 = srcBLen - 1u;
-  blockSize2 = srcALen - (srcBLen - 1u);
-  blockSize3 = blockSize1;
-
-  /* --------------------------   
-   * Initializations of stage1   
-   * -------------------------*/
-
-  /* sum = x[0] * y[srcBlen - 1]   
-   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   
-   * ....   
-   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
-   */
-
-  /* In this stage the MAC operations are increased by 1 for every iteration.   
-     The count variable holds the number of MAC operations performed */
-  count = 1u;
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  pSrc1 = pIn2 + (srcBLen - 1u);
-  py = pSrc1;
-
-  /* ------------------------   
-   * Stage1 process   
-   * ----------------------*/
-
-  /* The first stage starts here */
-  while(blockSize1 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* x[0] , x[1] */
-      in1 = (q15_t) * px++;
-      in2 = (q15_t) * px++;
-      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-      /* y[srcBLen - 4] , y[srcBLen - 3] */
-      in1 = (q15_t) * py++;
-      in2 = (q15_t) * py++;
-      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-      /* x[0] * y[srcBLen - 4] */
-      /* x[1] * y[srcBLen - 3] */
-      sum = __SMLAD(input1, input2, sum);
-
-      /* x[2] , x[3] */
-      in1 = (q15_t) * px++;
-      in2 = (q15_t) * px++;
-      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-      /* y[srcBLen - 2] , y[srcBLen - 1] */
-      in1 = (q15_t) * py++;
-      in2 = (q15_t) * py++;
-      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-      /* x[2] * y[srcBLen - 2] */
-      /* x[3] * y[srcBLen - 1] */
-      sum = __SMLAD(input1, input2, sum);
-
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      /* x[0] * y[srcBLen - 1] */
-      sum += (q31_t) ((q15_t) * px++ * *py++);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = (q7_t) (__SSAT(sum >> 7, 8));
-    /* Destination pointer is updated according to the address modifier, inc */
-    pOut += inc;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    py = pSrc1 - count;
-    px = pIn1;
-
-    /* Increment the MAC count */
-    count++;
-
-    /* Decrement the loop counter */
-    blockSize1--;
-  }
-
-  /* --------------------------   
-   * Initializations of stage2   
-   * ------------------------*/
-
-  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
-   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
-   * ....   
-   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
-   */
-
-  /* Working pointer of inputA */
-  px = pIn1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-  /* count is index by which the pointer pIn1 to be incremented */
-  count = 0u;
-
-  /* -------------------   
-   * Stage2 process   
-   * ------------------*/
-
-  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
-   * So, to loop unroll over blockSize2,   
-   * srcBLen should be greater than or equal to 4 */
-  if(srcBLen >= 4u)
-  {
-    /* Loop unroll over blockSize2, by 4 */
-    blkCnt = blockSize2 >> 2u;
-
-    while(blkCnt > 0u)
-    {
-      /* Set all accumulators to zero */
-      acc0 = 0;
-      acc1 = 0;
-      acc2 = 0;
-      acc3 = 0;
-
-      /* read x[0], x[1], x[2] samples */
-      x0 = *px++;
-      x1 = *px++;
-      x2 = *px++;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      do
-      {
-        /* Read y[0] sample */
-        c0 = *py++;
-        /* Read y[1] sample */
-        c1 = *py++;
-
-        /* Read x[3] sample */
-        x3 = *px++;
-
-        /* x[0] and x[1] are packed */
-        in1 = (q15_t) x0;
-        in2 = (q15_t) x1;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* y[0] and y[1] are packed */
-        in1 = (q15_t) c0;
-        in2 = (q15_t) c1;
-
-        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* acc0 += x[0] * y[0] + x[1] * y[1]  */
-        acc0 = __SMLAD(input1, input2, acc0);
-
-        /* x[1] and x[2] are packed */
-        in1 = (q15_t) x1;
-        in2 = (q15_t) x2;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* acc1 += x[1] * y[0] + x[2] * y[1] */
-        acc1 = __SMLAD(input1, input2, acc1);
-
-        /* x[2] and x[3] are packed */
-        in1 = (q15_t) x2;
-        in2 = (q15_t) x3;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* acc2 += x[2] * y[0] + x[3] * y[1]  */
-        acc2 = __SMLAD(input1, input2, acc2);
-
-        /* Read x[4] sample */
-        x0 = *(px++);
-
-        /* x[3] and x[4] are packed */
-        in1 = (q15_t) x3;
-        in2 = (q15_t) x0;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* acc3 += x[3] * y[0] + x[4] * y[1]  */
-        acc3 = __SMLAD(input1, input2, acc3);
-
-        /* Read y[2] sample */
-        c0 = *py++;
-        /* Read y[3] sample */
-        c1 = *py++;
-
-        /* Read x[5] sample */
-        x1 = *px++;
-
-        /* x[2] and x[3] are packed */
-        in1 = (q15_t) x2;
-        in2 = (q15_t) x3;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* y[2] and y[3] are packed */
-        in1 = (q15_t) c0;
-        in2 = (q15_t) c1;
-
-        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* acc0 += x[2] * y[2] + x[3] * y[3]  */
-        acc0 = __SMLAD(input1, input2, acc0);
-
-        /* x[3] and x[4] are packed */
-        in1 = (q15_t) x3;
-        in2 = (q15_t) x0;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* acc1 += x[3] * y[2] + x[4] * y[3]  */
-        acc1 = __SMLAD(input1, input2, acc1);
-
-        /* x[4] and x[5] are packed */
-        in1 = (q15_t) x0;
-        in2 = (q15_t) x1;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* acc2 += x[4] * y[2] + x[5] * y[3]  */
-        acc2 = __SMLAD(input1, input2, acc2);
-
-        /* Read x[6] sample */
-        x2 = *px++;
-
-        /* x[5] and x[6] are packed */
-        in1 = (q15_t) x1;
-        in2 = (q15_t) x2;
-
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* acc3 += x[5] * y[2] + x[6] * y[3]  */
-        acc3 = __SMLAD(input1, input2, acc3);
-
-      } while(--k);
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Read y[4] sample */
-        c0 = *py++;
-
-        /* Read x[7] sample */
-        x3 = *px++;
-
-        /* Perform the multiply-accumulates */
-        /* acc0 +=  x[4] * y[4] */
-        acc0 += ((q15_t) x0 * c0);
-        /* acc1 +=  x[5] * y[4] */
-        acc1 += ((q15_t) x1 * c0);
-        /* acc2 +=  x[6] * y[4] */
-        acc2 += ((q15_t) x2 * c0);
-        /* acc3 +=  x[7] * y[4] */
-        acc3 += ((q15_t) x3 * c0);
-
-        /* Reuse the present samples for the next MAC */
-        x0 = x1;
-        x1 = x2;
-        x2 = x3;
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q7_t) (__SSAT(acc0 >> 7, 8));
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      *pOut = (q7_t) (__SSAT(acc1 >> 7, 8));
-      pOut += inc;
-
-      *pOut = (q7_t) (__SSAT(acc2 >> 7, 8));
-      pOut += inc;
-
-      *pOut = (q7_t) (__SSAT(acc3 >> 7, 8));
-      pOut += inc;
-
-	  count += 4u;
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
-     ** No loop unrolling is used. */
-    blkCnt = blockSize2 % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Apply loop unrolling and compute 4 MACs simultaneously. */
-      k = srcBLen >> 2u;
-
-      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-      while(k > 0u)
-      {
-        /* Reading two inputs of SrcA buffer and packing */
-        in1 = (q15_t) * px++;
-        in2 = (q15_t) * px++;
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* Reading two inputs of SrcB buffer and packing */
-        in1 = (q15_t) * py++;
-        in2 = (q15_t) * py++;
-        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* Perform the multiply-accumulates */
-        sum = __SMLAD(input1, input2, sum);
-
-        /* Reading two inputs of SrcA buffer and packing */
-        in1 = (q15_t) * px++;
-        in2 = (q15_t) * px++;
-        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* Reading two inputs of SrcB buffer and packing */
-        in1 = (q15_t) * py++;
-        in2 = (q15_t) * py++;
-        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-        /* Perform the multiply-accumulates */
-        sum = __SMLAD(input1, input2, sum);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
-       ** No loop unrolling is used. */
-      k = srcBLen % 0x4u;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulates */
-        sum += ((q15_t) * px++ * *py++);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q7_t) (__SSAT(sum >> 7, 8));
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      /* Increment the pointer pIn1 index, count by 1 */
-	  count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-  else
-  {
-    /* If the srcBLen is not a multiple of 4,   
-     * the blockSize2 loop cannot be unrolled by 4 */
-    blkCnt = blockSize2;
-
-    while(blkCnt > 0u)
-    {
-      /* Accumulator is made zero for every iteration */
-      sum = 0;
-
-      /* Loop over srcBLen */
-      k = srcBLen;
-
-      while(k > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += ((q15_t) * px++ * *py++);
-
-        /* Decrement the loop counter */
-        k--;
-      }
-
-      /* Store the result in the accumulator in the destination buffer. */
-      *pOut = (q7_t) (__SSAT(sum >> 7, 8));
-      /* Destination pointer is updated according to the address modifier, inc */
-      pOut += inc;
-
-      /* Increment the MAC count */
-      count++;
-
-      /* Update the inputA and inputB pointers for next MAC calculation */
-      px = pIn1 + count;
-      py = pIn2;
-
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-  }
-
-  /* --------------------------   
-   * Initializations of stage3   
-   * -------------------------*/
-
-  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
-   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
-   * ....   
-   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
-   * sum +=  x[srcALen-1] * y[0]   
-   */
-
-  /* In this stage the MAC operations are decreased by 1 for every iteration.   
-     The count variable holds the number of MAC operations performed */
-  count = srcBLen - 1u;
-
-  /* Working pointer of inputA */
-  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
-  px = pSrc1;
-
-  /* Working pointer of inputB */
-  py = pIn2;
-
-  /* -------------------   
-   * Stage3 process   
-   * ------------------*/
-
-  while(blockSize3 > 0u)
-  {
-    /* Accumulator is made zero for every iteration */
-    sum = 0;
-
-    /* Apply loop unrolling and compute 4 MACs simultaneously. */
-    k = count >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
-     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
-    while(k > 0u)
-    {
-      /* x[srcALen - srcBLen + 1] , x[srcALen - srcBLen + 2]  */
-      in1 = (q15_t) * px++;
-      in2 = (q15_t) * px++;
-      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-      /* y[0] , y[1] */
-      in1 = (q15_t) * py++;
-      in2 = (q15_t) * py++;
-      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-      /* sum += x[srcALen - srcBLen + 1] * y[0] */
-      /* sum += x[srcALen - srcBLen + 2] * y[1] */
-      sum = __SMLAD(input1, input2, sum);
-
-      /* x[srcALen - srcBLen + 3] , x[srcALen - srcBLen + 4] */
-      in1 = (q15_t) * px++;
-      in2 = (q15_t) * px++;
-      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-      /* y[2] , y[3] */
-      in1 = (q15_t) * py++;
-      in2 = (q15_t) * py++;
-      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
-
-      /* sum += x[srcALen - srcBLen + 3] * y[2] */
-      /* sum += x[srcALen - srcBLen + 4] * y[3] */
-      sum = __SMLAD(input1, input2, sum);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* If the count is not a multiple of 4, compute any remaining MACs here.   
-     ** No loop unrolling is used. */
-    k = count % 0x4u;
-
-    while(k > 0u)
-    {
-      /* Perform the multiply-accumulates */
-      sum += ((q15_t) * px++ * *py++);
-
-      /* Decrement the loop counter */
-      k--;
-    }
-
-    /* Store the result in the accumulator in the destination buffer. */
-    *pOut = (q7_t) (__SSAT(sum >> 7, 8));
-    /* Destination pointer is updated according to the address modifier, inc */
-    pOut += inc;
-
-    /* Update the inputA and inputB pointers for next MAC calculation */
-    px = ++pSrc1;
-    py = pIn2;
-
-    /* Decrement the MAC count */
-    count--;
-
-    /* Decrement the loop counter */
-    blockSize3--;
-  }
-
-#else
-
-/* Run the below code for Cortex-M0 */
-
-  q7_t *pIn1 = pSrcA;                            /* inputA pointer */
-  q7_t *pIn2 = pSrcB + (srcBLen - 1u);           /* inputB pointer */
-  q31_t sum;                                     /* Accumulator */
-  uint32_t i = 0u, j;                            /* loop counters */
-  uint32_t inv = 0u;                             /* Reverse order flag */
-  uint32_t tot = 0u;                             /* Length */
-
-  /* The algorithm implementation is based on the lengths of the inputs. */
-  /* srcB is always made to slide across srcA. */
-  /* So srcBLen is always considered as shorter or equal to srcALen */
-  /* But CORR(x, y) is reverse of CORR(y, x) */
-  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
-  /* and a varaible, inv is set to 1 */
-  /* If lengths are not equal then zero pad has to be done to  make the two   
-   * inputs of same length. But to improve the performance, we include zeroes   
-   * in the output instead of zero padding either of the the inputs*/
-  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the   
-   * starting of the output buffer */
-  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the  
-   * ending of the output buffer */
-  /* Once the zero padding is done the remaining of the output is calcualted  
-   * using convolution but with the shorter signal time shifted. */
-
-  /* Calculate the length of the remaining sequence */
-  tot = ((srcALen + srcBLen) - 2u);
-
-  if(srcALen > srcBLen)
-  {
-    /* Calculating the number of zeros to be padded to the output */
-    j = srcALen - srcBLen;
-
-    /* Initialise the pointer after zero padding */
-    pDst += j;
-  }
-
-  else if(srcALen < srcBLen)
-  {
-    /* Initialization to inputB pointer */
-    pIn1 = pSrcB;
-
-    /* Initialization to the end of inputA pointer */
-    pIn2 = pSrcA + (srcALen - 1u);
-
-    /* Initialisation of the pointer after zero padding */
-    pDst = pDst + tot;
-
-    /* Swapping the lengths */
-    j = srcALen;
-    srcALen = srcBLen;
-    srcBLen = j;
-
-    /* Setting the reverse flag */
-    inv = 1;
-
-  }
-
-  /* Loop to calculate convolution for output length number of times */
-  for (i = 0u; i <= tot; i++)
-  {
-    /* Initialize sum with zero to carry on MAC operations */
-    sum = 0;
-
-    /* Loop to perform MAC operations according to convolution equation */
-    for (j = 0u; j <= i; j++)
-    {
-      /* Check the array limitations */
-      if((((i - j) < srcBLen) && (j < srcALen)))
-      {
-        /* z[i] += x[i-j] * y[j] */
-        sum += ((q15_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
-      }
-    }
-    /* Store the output in the destination buffer */
-    if(inv == 1)
-      *pDst-- = (q7_t) __SSAT((sum >> 7u), 8u);
-    else
-      *pDst++ = (q7_t) __SSAT((sum >> 7u), 8u);
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0 */
-
-}
-
-/**   
- * @} end of Corr group   
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_f32.c
deleted file mode 100644
index 60cd2ad3b3..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_f32.c
+++ /dev/null
@@ -1,518 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_decimate_f32.c    
-*    
-* Description:	FIR decimation for floating-point sequences.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-*    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @defgroup FIR_decimate Finite Impulse Response (FIR) Decimator    
- *    
- * These functions combine an FIR filter together with a decimator.    
- * They are used in multirate systems for reducing the sample rate of a signal without introducing aliasing distortion.    
- * Conceptually, the functions are equivalent to the block diagram below:    
- * \image html FIRDecimator.gif "Components included in the FIR Decimator functions"    
- * When decimating by a factor of M, the signal should be prefiltered by a lowpass filter with a normalized    
- * cutoff frequency of 1/M in order to prevent aliasing distortion.    
- * The user of the function is responsible for providing the filter coefficients.    
- *    
- * The FIR decimator functions provided in the CMSIS DSP Library combine the FIR filter and the decimator in an efficient manner.    
- * Instead of calculating all of the FIR filter outputs and discarding M-1 out of every M, only the    
- * samples output by the decimator are computed.    
- * The functions operate on blocks of input and output data.    
- * pSrc points to an array of blockSize input values and    
- * pDst points to an array of blockSize/M output values.    
- * In order to have an integer number of output samples blockSize    
- * must always be a multiple of the decimation factor M.    
- *    
- * The library provides separate functions for Q15, Q31 and floating-point data types.    
- *    
- * \par Algorithm:    
- * The FIR portion of the algorithm uses the standard form filter:    
- * 
    
- *    y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]    
- * 
    
- * where, b[n] are the filter coefficients.    
- * \par   
- * The pCoeffs points to a coefficient array of size numTaps.    
- * Coefficients are stored in time reversed order.    
- * \par    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * \par    
- * pState points to a state array of size numTaps + blockSize - 1.    
- * Samples in the state buffer are stored in the order:    
- * \par    
- * 
    
- *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}    
- * 
    
- * The state variables are updated after each block of data is processed, the coefficients are untouched.    
- *    
- * \par Instance Structure    
- * The coefficients and state variables for a filter are stored together in an instance data structure.    
- * A separate instance structure must be defined for each filter.    
- * Coefficient arrays may be shared among several instances while state variable array should be allocated separately.    
- * There are separate instance structure declarations for each of the 3 supported data types.    
- *    
- * \par Initialization Functions    
- * There is also an associated initialization function for each data type.    
- * The initialization function performs the following operations:    
- * - Sets the values of the internal structure fields.    
- * - Zeros out the values in the state buffer.    
- * - Checks to make sure that the size of the input is a multiple of the decimation factor.    
- *    
- * \par    
- * Use of the initialization function is optional.    
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
- * To place an instance structure into a const data section, the instance structure must be manually initialized.    
- * The code below statically initializes each of the 3 different data type filter instance structures    
- * 
    
- *arm_fir_decimate_instance_f32 S = {M, numTaps, pCoeffs, pState};    
- *arm_fir_decimate_instance_q31 S = {M, numTaps, pCoeffs, pState};    
- *arm_fir_decimate_instance_q15 S = {M, numTaps, pCoeffs, pState};    
- * 
    
- * where M is the decimation factor; numTaps is the number of filter coefficients in the filter;    
- * pCoeffs is the address of the coefficient buffer;    
- * pState is the address of the state buffer.    
- * Be sure to set the values in the state buffer to zeros when doing static initialization.    
- *    
- * \par Fixed-Point Behavior    
- * Care must be taken when using the fixed-point versions of the FIR decimate filter functions.    
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.    
- * Refer to the function specific documentation below for usage guidelines.    
- */
-
-/**    
- * @addtogroup FIR_decimate    
- * @{    
- */
-
-  /**    
-   * @brief Processing function for the floating-point FIR decimator.    
-   * @param[in] *S        points to an instance of the floating-point FIR decimator structure.    
-   * @param[in] *pSrc     points to the block of input data.    
-   * @param[out] *pDst    points to the block of output data.    
-   * @param[in] blockSize number of input samples to process per call.    
-   * @return none.    
-   */
-
-void arm_fir_decimate_f32(
-  const arm_fir_decimate_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize)
-{
-  float32_t *pState = S->pState;                 /* State pointer */
-  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
-  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
-  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
-  float32_t sum0;                                /* Accumulator */
-  float32_t x0, c0;                              /* Temporary variables to hold state and coefficient values */
-  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
-  uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
-
-#ifndef ARM_MATH_CM0
-
-  uint32_t blkCntN4;
-  float32_t *px0, *px1, *px2, *px3;
-  float32_t acc0, acc1, acc2, acc3;
-  float32_t x1, x2, x3;
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /* S->pState buffer contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + (numTaps - 1u);
-
-  /* Total number of output samples to be computed */
-  blkCnt = outBlockSize / 4;
-  blkCntN4 = outBlockSize - (4 * blkCnt);
-
-  while(blkCnt > 0u)
-  {
-    /* Copy 4 * decimation factor number of new input samples into the state buffer */
-    i = 4 * S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /* Set accumulators to zero */
-    acc0 = 0.0f;
-    acc1 = 0.0f;
-    acc2 = 0.0f;
-    acc3 = 0.0f;
-
-    /* Initialize state pointer for all the samples */
-    px0 = pState;
-    px1 = pState + S->M;
-    px2 = pState + 2 * S->M;
-    px3 = pState + 3 * S->M;
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.       
-     ** Repeat until we've computed numTaps-4 coefficients. */
-
-    while(tapCnt > 0u)
-    {
-      /* Read the b[numTaps-1] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-1] sample for acc0 */
-      x0 = *(px0++);
-      /* Read x[n-numTaps-1] sample for acc1 */
-      x1 = *(px1++);
-      /* Read x[n-numTaps-1] sample for acc2 */
-      x2 = *(px2++);
-      /* Read x[n-numTaps-1] sample for acc3 */
-      x3 = *(px3++);
-
-      /* Perform the multiply-accumulate */
-      acc0 += x0 * c0;
-      acc1 += x1 * c0;
-      acc2 += x2 * c0;
-      acc3 += x3 * c0;
-
-      /* Read the b[numTaps-2] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-2] sample for acc0, acc1, acc2, acc3 */
-      x0 = *(px0++);
-      x1 = *(px1++);
-      x2 = *(px2++);
-      x3 = *(px3++);
-
-      /* Perform the multiply-accumulate */
-      acc0 += x0 * c0;
-      acc1 += x1 * c0;
-      acc2 += x2 * c0;
-      acc3 += x3 * c0;
-
-      /* Read the b[numTaps-3] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-3] sample acc0, acc1, acc2, acc3 */
-      x0 = *(px0++);
-      x1 = *(px1++);
-      x2 = *(px2++);
-      x3 = *(px3++);
-
-      /* Perform the multiply-accumulate */
-      acc0 += x0 * c0;
-      acc1 += x1 * c0;
-      acc2 += x2 * c0;
-      acc3 += x3 * c0;
-
-      /* Read the b[numTaps-4] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-4] sample acc0, acc1, acc2, acc3 */
-      x0 = *(px0++);
-      x1 = *(px1++);
-      x2 = *(px2++);
-      x3 = *(px3++);
-
-      /* Perform the multiply-accumulate */
-      acc0 += x0 * c0;
-      acc1 += x1 * c0;
-      acc2 += x2 * c0;
-      acc3 += x3 * c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *(pb++);
-
-      /* Fetch  state variables for acc0, acc1, acc2, acc3 */
-      x0 = *(px0++);
-      x1 = *(px1++);
-      x2 = *(px2++);
-      x3 = *(px3++);
-
-      /* Perform the multiply-accumulate */
-      acc0 += x0 * c0;
-      acc1 += x1 * c0;
-      acc2 += x2 * c0;
-      acc3 += x3 * c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor       
-     * to process the next group of decimation factor number samples */
-    pState = pState + 4 * S->M;
-
-    /* The result is in the accumulator, store in the destination buffer. */
-    *pDst++ = acc0;
-    *pDst++ = acc1;
-    *pDst++ = acc2;
-    *pDst++ = acc3;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  while(blkCntN4 > 0u)
-  {
-    /* Copy decimation factor number of new input samples into the state buffer */
-    i = S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /* Set accumulator to zero */
-    sum0 = 0.0f;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.       
-     ** Repeat until we've computed numTaps-4 coefficients. */
-    while(tapCnt > 0u)
-    {
-      /* Read the b[numTaps-1] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-1] sample */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Read the b[numTaps-2] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-2] sample */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Read the b[numTaps-3] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-3] sample */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Read the b[numTaps-4] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-4] sample */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *(pb++);
-
-      /* Fetch 1 state variable */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor       
-     * to process the next group of decimation factor number samples */
-    pState = pState + S->M;
-
-    /* The result is in the accumulator, store in the destination buffer. */
-    *pDst++ = sum0;
-
-    /* Decrement the loop counter */
-    blkCntN4--;
-  }
-
-  /* Processing is complete.    
-   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.    
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  i = (numTaps - 1u) >> 2;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-  i = (numTaps - 1u) % 0x04u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-#else
-
-/* Run the below code for Cortex-M0 */
-
-  /* S->pState buffer contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + (numTaps - 1u);
-
-  /* Total number of output samples to be computed */
-  blkCnt = outBlockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* Copy decimation factor number of new input samples into the state buffer */
-    i = S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /* Set accumulator to zero */
-    sum0 = 0.0f;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    tapCnt = numTaps;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *pb++;
-
-      /* Fetch 1 state variable */
-      x0 = *px++;
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor           
-     * to process the next group of decimation factor number samples */
-    pState = pState + S->M;
-
-    /* The result is in the accumulator, store in the destination buffer. */
-    *pDst++ = sum0;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.         
-   ** Now copy the last numTaps - 1 samples to the start of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  /* Copy numTaps number of values */
-  i = (numTaps - 1u);
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0        */
-
-}
-
-/**    
- * @} end of FIR_decimate group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c
deleted file mode 100644
index b3d55464b7..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c
+++ /dev/null
@@ -1,590 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_decimate_fast_q15.c    
-*    
-* Description:	Fast Q15 FIR Decimator.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_decimate    
- * @{    
- */
-
-/**    
- * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.    
- * @param[in] *S points to an instance of the Q15 FIR decimator structure.    
- * @param[in] *pSrc points to the block of input data.    
- * @param[out] *pDst points to the block of output data    
- * @param[in] blockSize number of input samples to process per call.    
- * @return none    
- *    
- * \par Restrictions   
- *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE   
- *	In this case input, output, state buffers should be aligned by 32-bit   
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * This fast version uses a 32-bit accumulator with 2.30 format.    
- * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
- * Thus, if the accumulator result overflows it wraps around and distorts the result.    
- * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (log2 is read as log to the base 2).    
- * The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.    
- *    
- * \par    
- * Refer to the function arm_fir_decimate_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.    
- * Both the slow and the fast versions use the same instance structure.    
- * Use the function arm_fir_decimate_init_q15() to initialize the filter structure.    
- */
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-void arm_fir_decimate_fast_q15(
-  const arm_fir_decimate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pState = S->pState;                     /* State pointer */
-  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q15_t *px;                                     /* Temporary pointer for state buffer */
-  q15_t *pb;                                     /* Temporary pointer coefficient buffer */
-  q31_t x0, x1, c0, c1;                          /* Temporary variables to hold state and coefficient values */
-  q31_t sum0;                                    /* Accumulators */
-  q31_t acc0, acc1;
-  q15_t *px0, *px1;
-  uint32_t blkCntN3;
-  uint32_t numTaps = S->numTaps;                 /* Number of taps */
-  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
-
-
-  /* S->pState buffer contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + (numTaps - 1u);
-
-
-  /* Total number of output samples to be computed */
-  blkCnt = outBlockSize / 2;
-  blkCntN3 = outBlockSize - (2 * blkCnt);
-
-
-  while(blkCnt > 0u)
-  {
-    /* Copy decimation factor number of new input samples into the state buffer */
-    i = 2 * S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /* Set accumulator to zero */
-    acc0 = 0;
-    acc1 = 0;
-
-    /* Initialize state pointer */
-    px0 = pState;
-
-    px1 = pState + S->M;
-
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.       
-     ** Repeat until we've computed numTaps-4 coefficients. */
-    while(tapCnt > 0u)
-    {
-      /* Read the Read b[numTaps-1] and b[numTaps-2]  coefficients */
-      c0 = *__SIMD32(pb)++;
-
-      /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
-      x0 = *__SIMD32(px0)++;
-
-      x1 = *__SIMD32(px1)++;
-
-      /* Perform the multiply-accumulate */
-      acc0 = __SMLAD(x0, c0, acc0);
-
-      acc1 = __SMLAD(x1, c0, acc1);
-
-      /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
-      c0 = *__SIMD32(pb)++;
-
-      /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
-      x0 = *__SIMD32(px0)++;
-
-      x1 = *__SIMD32(px1)++;
-
-      /* Perform the multiply-accumulate */
-      acc0 = __SMLAD(x0, c0, acc0);
-
-      acc1 = __SMLAD(x1, c0, acc1);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *pb++;
-
-      /* Fetch 1 state variable */
-      x0 = *px0++;
-
-      x1 = *px1++;
-
-      /* Perform the multiply-accumulate */
-      acc0 = __SMLAD(x0, c0, acc0);
-      acc1 = __SMLAD(x1, c0, acc1);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor       
-     * to process the next group of decimation factor number samples */
-    pState = pState + S->M * 2;
-
-    /* Store filter output, smlad returns the values in 2.14 format */
-    /* so downsacle by 15 to get output in 1.15 */
-    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-    *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-
-
-  while(blkCntN3 > 0u)
-  {
-    /* Copy decimation factor number of new input samples into the state buffer */
-    i = S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /*Set sum to zero */
-    sum0 = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.       
-     ** Repeat until we've computed numTaps-4 coefficients. */
-    while(tapCnt > 0u)
-    {
-      /* Read the Read b[numTaps-1] and b[numTaps-2]  coefficients */
-      c0 = *__SIMD32(pb)++;
-
-      /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
-      x0 = *__SIMD32(px)++;
-
-      /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
-      c1 = *__SIMD32(pb)++;
-
-      /* Perform the multiply-accumulate */
-      sum0 = __SMLAD(x0, c0, sum0);
-
-      /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
-      x0 = *__SIMD32(px)++;
-
-      /* Perform the multiply-accumulate */
-      sum0 = __SMLAD(x0, c1, sum0);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *pb++;
-
-      /* Fetch 1 state variable */
-      x0 = *px++;
-
-      /* Perform the multiply-accumulate */
-      sum0 = __SMLAD(x0, c0, sum0);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor       
-     * to process the next group of decimation factor number samples */
-    pState = pState + S->M;
-
-    /* Store filter output, smlad returns the values in 2.14 format */
-    /* so downsacle by 15 to get output in 1.15 */
-    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
-
-    /* Decrement the loop counter */
-    blkCntN3--;
-  }
-
-  /* Processing is complete.       
-   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  i = (numTaps - 1u) >> 2u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-  i = (numTaps - 1u) % 0x04u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-}
-
-#else
-
-
-void arm_fir_decimate_fast_q15(
-  const arm_fir_decimate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pState = S->pState;                     /* State pointer */
-  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q15_t *px;                                     /* Temporary pointer for state buffer */
-  q15_t *pb;                                     /* Temporary pointer coefficient buffer */
-  q15_t x0, x1, c0;                              /* Temporary variables to hold state and coefficient values */
-  q31_t sum0;                                    /* Accumulators */
-  q31_t acc0, acc1;
-  q15_t *px0, *px1;
-  uint32_t blkCntN3;
-  uint32_t numTaps = S->numTaps;                 /* Number of taps */
-  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
-
-
-  /* S->pState buffer contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + (numTaps - 1u);
-
-
-  /* Total number of output samples to be computed */
-  blkCnt = outBlockSize / 2;
-  blkCntN3 = outBlockSize - (2 * blkCnt);
-
-  while(blkCnt > 0u)
-  {
-    /* Copy decimation factor number of new input samples into the state buffer */
-    i = 2 * S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /* Set accumulator to zero */
-    acc0 = 0;
-    acc1 = 0;
-
-    /* Initialize state pointer */
-    px0 = pState;
-
-    px1 = pState + S->M;
-
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.       
-     ** Repeat until we've computed numTaps-4 coefficients. */
-    while(tapCnt > 0u)
-    {
-      /* Read the Read b[numTaps-1] coefficients */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-1] for sample 0 and for sample 1 */
-      x0 = *px0++;
-      x1 = *px1++;
-
-      /* Perform the multiply-accumulate */
-      acc0 += x0 * c0;
-      acc1 += x1 * c0;
-
-      /* Read the b[numTaps-2] coefficient */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-2] for sample 0 and sample 1 */
-      x0 = *px0++;
-      x1 = *px1++;
-
-      /* Perform the multiply-accumulate */
-      acc0 += x0 * c0;
-      acc1 += x1 * c0;
-
-      /* Read the b[numTaps-3]  coefficients */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-3] for sample 0 and sample 1 */
-      x0 = *px0++;
-      x1 = *px1++;
-
-      /* Perform the multiply-accumulate */
-      acc0 += x0 * c0;
-      acc1 += x1 * c0;
-
-      /* Read the b[numTaps-4] coefficient */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-4] for sample 0 and sample 1 */
-      x0 = *px0++;
-      x1 = *px1++;
-
-      /* Perform the multiply-accumulate */
-      acc0 += x0 * c0;
-      acc1 += x1 * c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *pb++;
-
-      /* Fetch 1 state variable */
-      x0 = *px0++;
-      x1 = *px1++;
-
-      /* Perform the multiply-accumulate */
-      acc0 += x0 * c0;
-      acc1 += x1 * c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor       
-     * to process the next group of decimation factor number samples */
-    pState = pState + S->M * 2;
-
-    /* Store filter output, smlad returns the values in 2.14 format */
-    /* so downsacle by 15 to get output in 1.15 */
-
-    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-    *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
-
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  while(blkCntN3 > 0u)
-  {
-    /* Copy decimation factor number of new input samples into the state buffer */
-    i = S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /*Set sum to zero */
-    sum0 = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.       
-     ** Repeat until we've computed numTaps-4 coefficients. */
-    while(tapCnt > 0u)
-    {
-      /* Read the Read b[numTaps-1] coefficients */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-1] and sample */
-      x0 = *px++;
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Read the b[numTaps-2] coefficient */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-2] and  sample */
-      x0 = *px++;
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Read the b[numTaps-3]  coefficients */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-3] sample */
-      x0 = *px++;
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Read the b[numTaps-4] coefficient */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-4] sample */
-      x0 = *px++;
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *pb++;
-
-      /* Fetch 1 state variable */
-      x0 = *px++;
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor       
-     * to process the next group of decimation factor number samples */
-    pState = pState + S->M;
-
-    /* Store filter output, smlad returns the values in 2.14 format */
-    /* so downsacle by 15 to get output in 1.15 */
-    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
-
-    /* Decrement the loop counter */
-    blkCntN3--;
-  }
-
-  /* Processing is complete.       
-   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  i = (numTaps - 1u) >> 2u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-  i = (numTaps - 1u) % 0x04u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-}
-
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-/**    
- * @} end of FIR_decimate group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c
deleted file mode 100644
index d2f0e5fd07..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c
+++ /dev/null
@@ -1,343 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_decimate_fast_q31.c    
-*    
-* Description:	Fast Q31 FIR Decimator.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_decimate    
- * @{    
- */
-
-/**    
- * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.    
- * @param[in] *S points to an instance of the Q31 FIR decimator structure.    
- * @param[in] *pSrc points to the block of input data.    
- * @param[out] *pDst points to the block of output data    
- * @param[in] blockSize number of input samples to process per call.    
- * @return none    
- *    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * This function is optimized for speed at the expense of fixed-point precision and overflow protection.    
- * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.    
- * These intermediate results are added to a 2.30 accumulator.    
- * Finally, the accumulator is saturated and converted to a 1.31 result.    
- * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.    
- * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).    
- *    
- * \par    
- * Refer to the function arm_fir_decimate_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.    
- * Both the slow and the fast versions use the same instance structure.    
- * Use the function arm_fir_decimate_init_q31() to initialize the filter structure.    
- */
-
-void arm_fir_decimate_fast_q31(
-  arm_fir_decimate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  q31_t *pState = S->pState;                     /* State pointer */
-  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
-  q31_t *px;                                     /* Temporary pointers for state buffer */
-  q31_t *pb;                                     /* Temporary pointers for coefficient buffer */
-  q31_t sum0;                                    /* Accumulator */
-  uint32_t numTaps = S->numTaps;                 /* Number of taps */
-  uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
-  uint32_t blkCntN2;
-  q31_t x1;
-  q31_t acc0, acc1;
-  q31_t *px0, *px1;
-
-  /* S->pState buffer contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + (numTaps - 1u);
-
-  /* Total number of output samples to be computed */
-
-  blkCnt = outBlockSize / 2;
-  blkCntN2 = outBlockSize - (2 * blkCnt);
-
-  while(blkCnt > 0u)
-  {
-    /* Copy decimation factor number of new input samples into the state buffer */
-    i = 2 * S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /* Set accumulator to zero */
-    acc0 = 0;
-    acc1 = 0;
-
-    /* Initialize state pointer */
-    px0 = pState;
-    px1 = pState + S->M;
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.       
-     ** Repeat until we've computed numTaps-4 coefficients. */
-    while(tapCnt > 0u)
-    {
-      /* Read the b[numTaps-1] coefficient */
-      c0 = *(pb);
-
-      /* Read x[n-numTaps-1] for sample 0 sample 1 */
-      x0 = *(px0);
-      x1 = *(px1);
-
-      /* Perform the multiply-accumulate */
-      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
-      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
-
-      /* Read the b[numTaps-2] coefficient */
-      c0 = *(pb + 1u);
-
-      /* Read x[n-numTaps-2]  for sample 0 sample 1  */
-      x0 = *(px0 + 1u);
-      x1 = *(px1 + 1u);
-
-      /* Perform the multiply-accumulate */
-      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
-      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
-
-      /* Read the b[numTaps-3] coefficient */
-      c0 = *(pb + 2u);
-
-      /* Read x[n-numTaps-3]  for sample 0 sample 1 */
-      x0 = *(px0 + 2u);
-      x1 = *(px1 + 2u);
-      pb += 4u;
-
-      /* Perform the multiply-accumulate */
-      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
-      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
-
-      /* Read the b[numTaps-4] coefficient */
-      c0 = *(pb - 1u);
-
-      /* Read x[n-numTaps-4] for sample 0 sample 1 */
-      x0 = *(px0 + 3u);
-      x1 = *(px1 + 3u);
-
-
-      /* Perform the multiply-accumulate */
-      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
-      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
-
-      /* update state pointers */
-      px0 += 4u;
-      px1 += 4u;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *(pb++);
-
-      /* Fetch 1 state variable */
-      x0 = *(px0++);
-      x1 = *(px1++);
-
-      /* Perform the multiply-accumulate */
-      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
-      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor       
-     * to process the next group of decimation factor number samples */
-    pState = pState + S->M * 2;
-
-    /* The result is in the accumulator, store in the destination buffer. */
-    *pDst++ = (q31_t) (acc0 << 1);
-    *pDst++ = (q31_t) (acc1 << 1);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  while(blkCntN2 > 0u)
-  {
-    /* Copy decimation factor number of new input samples into the state buffer */
-    i = S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /* Set accumulator to zero */
-    sum0 = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.       
-     ** Repeat until we've computed numTaps-4 coefficients. */
-    while(tapCnt > 0u)
-    {
-      /* Read the b[numTaps-1] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-1] sample */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulate */
-      sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
-
-      /* Read the b[numTaps-2] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-2] sample */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulate */
-      sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
-
-      /* Read the b[numTaps-3] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-3] sample */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulate */
-      sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
-
-      /* Read the b[numTaps-4] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-4] sample */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulate */
-      sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *(pb++);
-
-      /* Fetch 1 state variable */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulate */
-      sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor       
-     * to process the next group of decimation factor number samples */
-    pState = pState + S->M;
-
-    /* The result is in the accumulator, store in the destination buffer. */
-    *pDst++ = (q31_t) (sum0 << 1);
-
-    /* Decrement the loop counter */
-    blkCntN2--;
-  }
-
-  /* Processing is complete.       
-   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  i = (numTaps - 1u) >> 2u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-  i = (numTaps - 1u) % 0x04u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-}
-
-/**    
- * @} end of FIR_decimate group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_f32.c
deleted file mode 100644
index 55c1e991a8..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_f32.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_decimate_init_f32.c    
-*    
-* Description:  Floating-point FIR Decimator initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_decimate    
- * @{    
- */
-
-/**    
- * @brief  Initialization function for the floating-point FIR decimator.    
- * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.    
- * @param[in] numTaps  number of coefficients in the filter.    
- * @param[in] M  decimation factor.    
- * @param[in] *pCoeffs points to the filter coefficients.    
- * @param[in] *pState points to the state buffer.    
- * @param[in] blockSize number of input samples to process per call.    
- * @return    The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if    
- * blockSize is not a multiple of M.    
- *    
- * Description:    
- * \par    
- * pCoeffs points to the array of filter coefficients stored in time reversed order:    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * \par    
- * pState points to the array of state variables.    
- * pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_f32().    
- * M is the decimation factor.    
- */
-
-arm_status arm_fir_decimate_init_f32(
-  arm_fir_decimate_instance_f32 * S,
-  uint16_t numTaps,
-  uint8_t M,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  uint32_t blockSize)
-{
-  arm_status status;
-
-  /* The size of the input block must be a multiple of the decimation factor */
-  if((blockSize % M) != 0u)
-  {
-    /* Set status as ARM_MATH_LENGTH_ERROR */
-    status = ARM_MATH_LENGTH_ERROR;
-  }
-  else
-  {
-    /* Assign filter taps */
-    S->numTaps = numTaps;
-
-    /* Assign coefficient pointer */
-    S->pCoeffs = pCoeffs;
-
-    /* Clear state buffer and size is always (blockSize + numTaps - 1) */
-    memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
-
-    /* Assign state pointer */
-    S->pState = pState;
-
-    /* Assign Decimation Factor */
-    S->M = M;
-
-    status = ARM_MATH_SUCCESS;
-  }
-
-  return (status);
-
-}
-
-/**    
- * @} end of FIR_decimate group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q15.c
deleted file mode 100644
index a6ccab926d..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q15.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_decimate_init_q15.c    
-*    
-* Description:  Initialization function for the Q15 FIR Decimator.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_decimate    
- * @{    
- */
-
-/**    
- * @brief  Initialization function for the Q15 FIR decimator.    
- * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.    
- * @param[in] numTaps  number of coefficients in the filter.    
- * @param[in] M  decimation factor.    
- * @param[in] *pCoeffs points to the filter coefficients.    
- * @param[in] *pState points to the state buffer.    
- * @param[in] blockSize number of input samples to process per call.    
- * @return    The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if    
- * blockSize is not a multiple of M.    
- *    
- * Description:    
- * \par    
- * pCoeffs points to the array of filter coefficients stored in time reversed order:    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * \par    
- * pState points to the array of state variables.    
- * pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples    
- * to the call arm_fir_decimate_q15().    
- * M is the decimation factor.    
- */
-
-arm_status arm_fir_decimate_init_q15(
-  arm_fir_decimate_instance_q15 * S,
-  uint16_t numTaps,
-  uint8_t M,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  uint32_t blockSize)
-{
-
-  arm_status status;
-
-  /* The size of the input block must be a multiple of the decimation factor */
-  if((blockSize % M) != 0u)
-  {
-    /* Set status as ARM_MATH_LENGTH_ERROR */
-    status = ARM_MATH_LENGTH_ERROR;
-  }
-  else
-  {
-    /* Assign filter taps */
-    S->numTaps = numTaps;
-
-    /* Assign coefficient pointer */
-    S->pCoeffs = pCoeffs;
-
-    /* Clear the state buffer.  The size of buffer is always (blockSize + numTaps - 1) */
-    memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
-
-    /* Assign state pointer */
-    S->pState = pState;
-
-    /* Assign Decimation factor */
-    S->M = M;
-
-    status = ARM_MATH_SUCCESS;
-  }
-
-  return (status);
-
-}
-
-/**    
- * @} end of FIR_decimate group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q31.c
deleted file mode 100644
index 046ac1aa31..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q31.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_decimate_init_q31.c    
-*    
-* Description:  Initialization function for Q31 FIR Decimation filter.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_decimate    
- * @{    
- */
-
-/**    
- * @brief  Initialization function for the Q31 FIR decimator.    
- * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.    
- * @param[in] numTaps  number of coefficients in the filter.    
- * @param[in] M  decimation factor.    
- * @param[in] *pCoeffs points to the filter coefficients.    
- * @param[in] *pState points to the state buffer.    
- * @param[in] blockSize number of input samples to process per call.    
- * @return    The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if    
- * blockSize is not a multiple of M.    
- *    
- * Description:    
- * \par    
- * pCoeffs points to the array of filter coefficients stored in time reversed order:    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * \par    
- * pState points to the array of state variables.    
- * pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_q31().    
- * M is the decimation factor.    
- */
-
-arm_status arm_fir_decimate_init_q31(
-  arm_fir_decimate_instance_q31 * S,
-  uint16_t numTaps,
-  uint8_t M,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  uint32_t blockSize)
-{
-  arm_status status;
-
-  /* The size of the input block must be a multiple of the decimation factor */
-  if((blockSize % M) != 0u)
-  {
-    /* Set status as ARM_MATH_LENGTH_ERROR */
-    status = ARM_MATH_LENGTH_ERROR;
-  }
-  else
-  {
-    /* Assign filter taps */
-    S->numTaps = numTaps;
-
-    /* Assign coefficient pointer */
-    S->pCoeffs = pCoeffs;
-
-    /* Clear the state buffer.  The size is always (blockSize + numTaps - 1) */
-    memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(q31_t));
-
-    /* Assign state pointer */
-    S->pState = pState;
-
-    /* Assign Decimation factor */
-    S->M = M;
-
-    status = ARM_MATH_SUCCESS;
-  }
-
-  return (status);
-
-}
-
-/**    
- * @} end of FIR_decimate group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q15.c
deleted file mode 100644
index 3fead69284..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q15.c
+++ /dev/null
@@ -1,691 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_decimate_q15.c    
-*    
-* Description:	Q15 FIR Decimator.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_decimate    
- * @{    
- */
-
-/**    
- * @brief Processing function for the Q15 FIR decimator.    
- * @param[in] *S points to an instance of the Q15 FIR decimator structure.    
- * @param[in] *pSrc points to the block of input data.    
- * @param[out] *pDst points to the location where the output result is written.    
- * @param[in] blockSize number of input samples to process per call.    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using a 64-bit internal accumulator.    
- * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.    
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    
- * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.    
- * Lastly, the accumulator is saturated to yield a result in 1.15 format.    
- *    
- * \par    
- * Refer to the function arm_fir_decimate_fast_q15() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.    
- */
-
-#ifndef ARM_MATH_CM0
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-void arm_fir_decimate_q15(
-  const arm_fir_decimate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pState = S->pState;                     /* State pointer */
-  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q15_t *px;                                     /* Temporary pointer for state buffer */
-  q15_t *pb;                                     /* Temporary pointer coefficient buffer */
-  q31_t x0, x1, c0, c1;                          /* Temporary variables to hold state and coefficient values */
-  q63_t sum0;                                    /* Accumulators */
-  q63_t acc0, acc1;
-  q15_t *px0, *px1;
-  uint32_t blkCntN3;
-  uint32_t numTaps = S->numTaps;                 /* Number of taps */
-  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
-
-
-  /* S->pState buffer contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + (numTaps - 1u);
-
-
-  /* Total number of output samples to be computed */
-  blkCnt = outBlockSize / 2;
-  blkCntN3 = outBlockSize - (2 * blkCnt);
-
-
-  while(blkCnt > 0u)
-  {
-    /* Copy decimation factor number of new input samples into the state buffer */
-    i = 2 * S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /* Set accumulator to zero */
-    acc0 = 0;
-    acc1 = 0;
-
-    /* Initialize state pointer */
-    px0 = pState;
-
-    px1 = pState + S->M;
-
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.       
-     ** Repeat until we've computed numTaps-4 coefficients. */
-    while(tapCnt > 0u)
-    {
-      /* Read the Read b[numTaps-1] and b[numTaps-2]  coefficients */
-      c0 = *__SIMD32(pb)++;
-
-      /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
-      x0 = *__SIMD32(px0)++;
-
-      x1 = *__SIMD32(px1)++;
-
-      /* Perform the multiply-accumulate */
-      acc0 = __SMLALD(x0, c0, acc0);
-
-      acc1 = __SMLALD(x1, c0, acc1);
-
-      /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
-      c0 = *__SIMD32(pb)++;
-
-      /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
-      x0 = *__SIMD32(px0)++;
-
-      x1 = *__SIMD32(px1)++;
-
-      /* Perform the multiply-accumulate */
-      acc0 = __SMLALD(x0, c0, acc0);
-
-      acc1 = __SMLALD(x1, c0, acc1);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *pb++;
-
-      /* Fetch 1 state variable */
-      x0 = *px0++;
-
-      x1 = *px1++;
-
-      /* Perform the multiply-accumulate */
-      acc0 = __SMLALD(x0, c0, acc0);
-      acc1 = __SMLALD(x1, c0, acc1);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor       
-     * to process the next group of decimation factor number samples */
-    pState = pState + S->M * 2;
-
-    /* Store filter output, smlad returns the values in 2.14 format */
-    /* so downsacle by 15 to get output in 1.15 */
-    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-    *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-
-
-  while(blkCntN3 > 0u)
-  {
-    /* Copy decimation factor number of new input samples into the state buffer */
-    i = S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /*Set sum to zero */
-    sum0 = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.       
-     ** Repeat until we've computed numTaps-4 coefficients. */
-    while(tapCnt > 0u)
-    {
-      /* Read the Read b[numTaps-1] and b[numTaps-2]  coefficients */
-      c0 = *__SIMD32(pb)++;
-
-      /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
-      x0 = *__SIMD32(px)++;
-
-      /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
-      c1 = *__SIMD32(pb)++;
-
-      /* Perform the multiply-accumulate */
-      sum0 = __SMLALD(x0, c0, sum0);
-
-      /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
-      x0 = *__SIMD32(px)++;
-
-      /* Perform the multiply-accumulate */
-      sum0 = __SMLALD(x0, c1, sum0);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *pb++;
-
-      /* Fetch 1 state variable */
-      x0 = *px++;
-
-      /* Perform the multiply-accumulate */
-      sum0 = __SMLALD(x0, c0, sum0);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor       
-     * to process the next group of decimation factor number samples */
-    pState = pState + S->M;
-
-    /* Store filter output, smlad returns the values in 2.14 format */
-    /* so downsacle by 15 to get output in 1.15 */
-    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
-
-    /* Decrement the loop counter */
-    blkCntN3--;
-  }
-
-  /* Processing is complete.       
-   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  i = (numTaps - 1u) >> 2u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-  i = (numTaps - 1u) % 0x04u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-}
-
-#else
-
-
-void arm_fir_decimate_q15(
-  const arm_fir_decimate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pState = S->pState;                     /* State pointer */
-  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q15_t *px;                                     /* Temporary pointer for state buffer */
-  q15_t *pb;                                     /* Temporary pointer coefficient buffer */
-  q15_t x0, x1, c0;                              /* Temporary variables to hold state and coefficient values */
-  q63_t sum0;                                    /* Accumulators */
-  q63_t acc0, acc1;
-  q15_t *px0, *px1;
-  uint32_t blkCntN3;
-  uint32_t numTaps = S->numTaps;                 /* Number of taps */
-  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
-
-
-  /* S->pState buffer contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + (numTaps - 1u);
-
-
-  /* Total number of output samples to be computed */
-  blkCnt = outBlockSize / 2;
-  blkCntN3 = outBlockSize - (2 * blkCnt);
-
-  while(blkCnt > 0u)
-  {
-    /* Copy decimation factor number of new input samples into the state buffer */
-    i = 2 * S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /* Set accumulator to zero */
-    acc0 = 0;
-    acc1 = 0;
-
-    /* Initialize state pointer */
-    px0 = pState;
-
-    px1 = pState + S->M;
-
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.       
-     ** Repeat until we've computed numTaps-4 coefficients. */
-    while(tapCnt > 0u)
-    {
-      /* Read the Read b[numTaps-1] coefficients */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-1] for sample 0 and for sample 1 */
-      x0 = *px0++;
-      x1 = *px1++;
-
-      /* Perform the multiply-accumulate */
-      acc0 += x0 * c0;
-      acc1 += x1 * c0;
-
-      /* Read the b[numTaps-2] coefficient */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-2] for sample 0 and sample 1 */
-      x0 = *px0++;
-      x1 = *px1++;
-
-      /* Perform the multiply-accumulate */
-      acc0 += x0 * c0;
-      acc1 += x1 * c0;
-
-      /* Read the b[numTaps-3] coefficients */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-3] for sample 0 and sample 1 */
-      x0 = *px0++;
-      x1 = *px1++;
-
-      /* Perform the multiply-accumulate */
-      acc0 += x0 * c0;
-      acc1 += x1 * c0;
-
-      /* Read the b[numTaps-4] coefficient */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-4] for sample 0 and sample 1 */
-      x0 = *px0++;
-      x1 = *px1++;
-
-      /* Perform the multiply-accumulate */
-      acc0 += x0 * c0;
-      acc1 += x1 * c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *pb++;
-
-      /* Fetch 1 state variable */
-      x0 = *px0++;
-      x1 = *px1++;
-
-      /* Perform the multiply-accumulate */
-      acc0 += x0 * c0;
-      acc1 += x1 * c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor       
-     * to process the next group of decimation factor number samples */
-    pState = pState + S->M * 2;
-
-    /* Store filter output, smlad returns the values in 2.14 format */
-    /* so downsacle by 15 to get output in 1.15 */
-
-    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-    *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  while(blkCntN3 > 0u)
-  {
-    /* Copy decimation factor number of new input samples into the state buffer */
-    i = S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /*Set sum to zero */
-    sum0 = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.       
-     ** Repeat until we've computed numTaps-4 coefficients. */
-    while(tapCnt > 0u)
-    {
-      /* Read the Read b[numTaps-1] coefficients */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-1] and sample */
-      x0 = *px++;
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Read the b[numTaps-2] coefficient */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-2] and  sample */
-      x0 = *px++;
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Read the b[numTaps-3]  coefficients */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-3] sample */
-      x0 = *px++;
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Read the b[numTaps-4] coefficient */
-      c0 = *pb++;
-
-      /* Read x[n-numTaps-4] sample */
-      x0 = *px++;
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *pb++;
-
-      /* Fetch 1 state variable */
-      x0 = *px++;
-
-      /* Perform the multiply-accumulate */
-      sum0 += x0 * c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor       
-     * to process the next group of decimation factor number samples */
-    pState = pState + S->M;
-
-    /* Store filter output, smlad returns the values in 2.14 format */
-    /* so downsacle by 15 to get output in 1.15 */
-    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
-
-    /* Decrement the loop counter */
-    blkCntN3--;
-  }
-
-  /* Processing is complete.       
-   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  i = (numTaps - 1u) >> 2u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-  i = (numTaps - 1u) % 0x04u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-}
-
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-#else
-
-
-void arm_fir_decimate_q15(
-  const arm_fir_decimate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pState = S->pState;                     /* State pointer */
-  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q15_t *px;                                     /* Temporary pointer for state buffer */
-  q15_t *pb;                                     /* Temporary pointer coefficient buffer */
-  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
-  q63_t sum0;                                    /* Accumulators */
-  uint32_t numTaps = S->numTaps;                 /* Number of taps */
-  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
-
-
-
-/* Run the below code for Cortex-M0 */
-
-  /* S->pState buffer contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + (numTaps - 1u);
-
-  /* Total number of output samples to be computed */
-  blkCnt = outBlockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* Copy decimation factor number of new input samples into the state buffer */
-    i = S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /*Set sum to zero */
-    sum0 = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    tapCnt = numTaps;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *pb++;
-
-      /* Fetch 1 state variable */
-      x0 = *px++;
-
-      /* Perform the multiply-accumulate */
-      sum0 += (q31_t) x0 *c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor           
-     * to process the next group of decimation factor number samples */
-    pState = pState + S->M;
-
-    /*Store filter output , smlad will return the values in 2.14 format */
-    /* so downsacle by 15 to get output in 1.15 */
-    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.         
-   ** Now copy the last numTaps - 1 samples to the start of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  i = numTaps - 1u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-
-}
-#endif /*   #ifndef ARM_MATH_CM0 */
-
-
-/**    
- * @} end of FIR_decimate group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q31.c
deleted file mode 100644
index 72bf76c3a2..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q31.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_decimate_q31.c    
-*    
-* Description:	Q31 FIR Decimator.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_decimate    
- * @{    
- */
-
-/**    
- * @brief Processing function for the Q31 FIR decimator.    
- * @param[in] *S points to an instance of the Q31 FIR decimator structure.    
- * @param[in] *pSrc points to the block of input data.    
- * @param[out] *pDst points to the block of output data    
- * @param[in] blockSize number of input samples to process per call.    
- * @return none    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using an internal 64-bit accumulator.    
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
- * Thus, if the accumulator result overflows it wraps around rather than clip.    
- * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).    
- * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.    
- *    
- * \par    
- * Refer to the function arm_fir_decimate_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.    
- */
-
-void arm_fir_decimate_q31(
-  const arm_fir_decimate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  q31_t *pState = S->pState;                     /* State pointer */
-  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
-  q31_t *px;                                     /* Temporary pointers for state buffer */
-  q31_t *pb;                                     /* Temporary pointers for coefficient buffer */
-  q63_t sum0;                                    /* Accumulator */
-  uint32_t numTaps = S->numTaps;                 /* Number of taps */
-  uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /* S->pState buffer contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + (numTaps - 1u);
-
-  /* Total number of output samples to be computed */
-  blkCnt = outBlockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* Copy decimation factor number of new input samples into the state buffer */
-    i = S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /* Set accumulator to zero */
-    sum0 = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.    
-     ** Repeat until we've computed numTaps-4 coefficients. */
-    while(tapCnt > 0u)
-    {
-      /* Read the b[numTaps-1] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-1] sample */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulate */
-      sum0 += (q63_t) x0 *c0;
-
-      /* Read the b[numTaps-2] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-2] sample */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulate */
-      sum0 += (q63_t) x0 *c0;
-
-      /* Read the b[numTaps-3] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-3] sample */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulate */
-      sum0 += (q63_t) x0 *c0;
-
-      /* Read the b[numTaps-4] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-4] sample */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulate */
-      sum0 += (q63_t) x0 *c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *(pb++);
-
-      /* Fetch 1 state variable */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulate */
-      sum0 += (q63_t) x0 *c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor    
-     * to process the next group of decimation factor number samples */
-    pState = pState + S->M;
-
-    /* The result is in the accumulator, store in the destination buffer. */
-    *pDst++ = (q31_t) (sum0 >> 31);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.    
-   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.    
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  i = (numTaps - 1u) >> 2u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-  i = (numTaps - 1u) % 0x04u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-#else
-
-/* Run the below code for Cortex-M0 */
-
-  /* S->pState buffer contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + (numTaps - 1u);
-
-  /* Total number of output samples to be computed */
-  blkCnt = outBlockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* Copy decimation factor number of new input samples into the state buffer */
-    i = S->M;
-
-    do
-    {
-      *pStateCurnt++ = *pSrc++;
-
-    } while(--i);
-
-    /* Set accumulator to zero */
-    sum0 = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = pCoeffs;
-
-    tapCnt = numTaps;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *pb++;
-
-      /* Fetch 1 state variable */
-      x0 = *px++;
-
-      /* Perform the multiply-accumulate */
-      sum0 += (q63_t) x0 *c0;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by the decimation factor           
-     * to process the next group of decimation factor number samples */
-    pState = pState + S->M;
-
-    /* The result is in the accumulator, store in the destination buffer. */
-    *pDst++ = (q31_t) (sum0 >> 31);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.         
-   ** Now copy the last numTaps - 1 samples to the start of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  i = numTaps - 1u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
- * @} end of FIR_decimate group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_f32.c
deleted file mode 100644
index a407131e8a..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_f32.c
+++ /dev/null
@@ -1,554 +0,0 @@
-/* ----------------------------------------------------------------------  
-* Copyright (C) 2010 ARM Limited. All rights reserved.  
-*  
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*  
-* Project: 	    CMSIS DSP Library  
-* Title:	    arm_fir_f32.c  
-*  
-* Description:	Floating-point FIR filter processing function.  
-*  
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.2 2010/11/11  
-*    Documentation updated.   
-*  
-* Version 1.0.1 2010/10/05   
-*    Production release and review comments incorporated.  
-*  
-* Version 1.0.0 2010/09/20   
-*    Production release and review comments incorporated.  
-*  
-* Version 0.0.5  2010/04/26   
-* 	 incorporated review comments and updated with latest CMSIS layer  
-*  
-* Version 0.0.3  2010/03/10   
-*    Initial version  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**  
- * @ingroup groupFilters  
- */
-
-/**  
- * @defgroup FIR Finite Impulse Response (FIR) Filters  
- *  
- * This set of functions implements Finite Impulse Response (FIR) filters  
- * for Q7, Q15, Q31, and floating-point data types.  Fast versions of Q15 and Q31 are also provided.  
- * The functions operate on blocks of input and output data and each call to the function processes  
- * blockSize samples through the filter.  pSrc and  
- * pDst points to input and output arrays containing blockSize values.  
- *  
- * \par Algorithm:  
- * The FIR filter algorithm is based upon a sequence of multiply-accumulate (MAC) operations.  
- * Each filter coefficient b[n] is multiplied by a state variable which equals a previous input sample x[n].  
- * 
  
- *    y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]  
- * 
  
- * \par  
- * \image html FIR.gif "Finite Impulse Response filter"  
- * \par  
- * pCoeffs points to a coefficient array of size numTaps.  
- * Coefficients are stored in time reversed order.  
- * \par  
- * 
  
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}  
- * 
  
- * \par  
- * pState points to a state array of size numTaps + blockSize - 1.  
- * Samples in the state buffer are stored in the following order.  
- * \par  
- * 
  
- *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}  
- * 
  
- * \par  
- * Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1.  
- * The increased state buffer length allows circular addressing, which is traditionally used in the FIR filters,  
- * to be avoided and yields a significant speed improvement.  
- * The state variables are updated after each block of data is processed; the coefficients are untouched.  
- * \par Instance Structure  
- * The coefficients and state variables for a filter are stored together in an instance data structure.  
- * A separate instance structure must be defined for each filter.  
- * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.  
- * There are separate instance structure declarations for each of the 4 supported data types.  
- *  
- * \par Initialization Functions  
- * There is also an associated initialization function for each data type.  
- * The initialization function performs the following operations:  
- * - Sets the values of the internal structure fields.  
- * - Zeros out the values in the state buffer.  
- *  
- * \par  
- * Use of the initialization function is optional.  
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.  
- * To place an instance structure into a const data section, the instance structure must be manually initialized.  
- * Set the values in the state buffer to zeros before static initialization.  
- * The code below statically initializes each of the 4 different data type filter instance structures  
- * 
  
- *arm_fir_instance_f32 S = {numTaps, pState, pCoeffs};  
- *arm_fir_instance_q31 S = {numTaps, pState, pCoeffs};  
- *arm_fir_instance_q15 S = {numTaps, pState, pCoeffs};  
- *arm_fir_instance_q7 S =  {numTaps, pState, pCoeffs};  
- * 
  
- *  
- * where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer;  
- * pCoeffs is the address of the coefficient buffer.  
- *  
- * \par Fixed-Point Behavior  
- * Care must be taken when using the fixed-point versions of the FIR filter functions.  
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.  
- * Refer to the function specific documentation below for usage guidelines.  
- */
-
-/**  
- * @addtogroup FIR  
- * @{  
- */
-
-/**  
- *  
- * @param[in]  *S points to an instance of the floating-point FIR filter structure.  
- * @param[in]  *pSrc points to the block of input data.  
- * @param[out] *pDst points to the block of output data.  
- * @param[in]  blockSize number of samples to process per call.  
- * @return     none.  
- *  
- */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-void arm_fir_f32(
-  const arm_fir_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize)
-{
-  float32_t *pState = S->pState;                 /* State pointer */
-  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
-  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
-  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
-  float32_t acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7;     /* Accumulators */
-  float32_t x0, x1, x2, x3, x4, x5, x6, x7, c0;  /* Temporary variables to hold state and coefficient values */
-  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
-  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
-
-  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  /* Apply loop unrolling and compute 4 output values simultaneously.  
-   * The variables acc0 ... acc3 hold output values that are being computed:  
-   *  
-   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]  
-   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]  
-   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]  
-   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]  
-   */
-  blkCnt = blockSize >> 3;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.  
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* Copy four new input samples into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-
-    /* Set all accumulators to zero */
-    acc0 = 0.0f;
-    acc1 = 0.0f;
-    acc2 = 0.0f;
-    acc3 = 0.0f;
-    acc4 = 0.0f;
-    acc5 = 0.0f;
-    acc6 = 0.0f;
-    acc7 = 0.0f;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = (pCoeffs);
-
-    /* Read the first three samples from the state buffer:  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
-    x0 = *px++;
-    x1 = *px++;
-    x2 = *px++;
-    x3 = *px++;
-    x4 = *px++;
-    x5 = *px++;
-    x6 = *px++;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 3u;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.  
-     ** Repeat until we've computed numTaps-4 coefficients. */
-    while(tapCnt > 0u)
-    {
-      /* Read the b[numTaps-1] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-3] sample */
-      x7 = *(px++);
-
-      /* acc0 +=  b[numTaps-1] * x[n-numTaps] */
-      acc0 += x0 * c0;
-
-      /* acc1 +=  b[numTaps-1] * x[n-numTaps-1] */
-      acc1 += x1 * c0;
-
-      /* acc2 +=  b[numTaps-1] * x[n-numTaps-2] */
-      acc2 += x2 * c0;
-
-      /* acc3 +=  b[numTaps-1] * x[n-numTaps-3] */
-      acc3 += x3 * c0;
-
-      /* acc4 +=  b[numTaps-1] * x[n-numTaps-4] */
-      acc4 += x4 * c0;
-
-      /* acc1 +=  b[numTaps-1] * x[n-numTaps-5] */
-      acc5 += x5 * c0;
-
-      /* acc2 +=  b[numTaps-1] * x[n-numTaps-6] */
-      acc6 += x6 * c0;
-
-      /* acc3 +=  b[numTaps-1] * x[n-numTaps-7] */
-      acc7 += x7 * c0;
-
-      /* Read the b[numTaps-2] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-4] sample */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulate */
-      acc0 += x1 * c0;
-      acc1 += x2 * c0;
-      acc2 += x3 * c0;
-      acc3 += x4 * c0;
-      acc4 += x5 * c0;
-      acc5 += x6 * c0;
-      acc6 += x7 * c0;
-      acc7 += x0 * c0;
-
-      /* Read the b[numTaps-3] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-5] sample */
-      x1 = *(px++);
-
-      /* Perform the multiply-accumulates */
-      acc0 += x2 * c0;
-      acc1 += x3 * c0;
-      acc2 += x4 * c0;
-      acc3 += x5 * c0;
-      acc4 += x6 * c0;
-      acc5 += x7 * c0;
-      acc6 += x0 * c0;
-      acc7 += x1 * c0;
-
-      /* Read the b[numTaps-4] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-6] sample */
-      x2 = *(px++);
-
-      /* Perform the multiply-accumulates */
-      acc0 += x3 * c0;
-      acc1 += x4 * c0;
-      acc2 += x5 * c0;
-      acc3 += x6 * c0;
-      acc4 += x7 * c0;
-      acc5 += x0 * c0;
-      acc6 += x1 * c0;
-      acc7 += x2 * c0;
-
-      /* Read the b[numTaps-4] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-6] sample */
-      x3 = *(px++);
-
-      /* Perform the multiply-accumulates */
-      acc0 += x4 * c0;
-      acc1 += x5 * c0;
-      acc2 += x6 * c0;
-      acc3 += x7 * c0;
-      acc4 += x0 * c0;
-      acc5 += x1 * c0;
-      acc6 += x2 * c0;
-      acc7 += x3 * c0;
-
-      /* Read the b[numTaps-4] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-6] sample */
-      x4 = *(px++);
-
-      /* Perform the multiply-accumulates */
-      acc0 += x5 * c0;
-      acc1 += x6 * c0;
-      acc2 += x7 * c0;
-      acc3 += x0 * c0;
-      acc4 += x1 * c0;
-      acc5 += x2 * c0;
-      acc6 += x3 * c0;
-      acc7 += x4 * c0;
-
-      /* Read the b[numTaps-4] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-6] sample */
-      x5 = *(px++);
-
-      /* Perform the multiply-accumulates */
-      acc0 += x6 * c0;
-      acc1 += x7 * c0;
-      acc2 += x0 * c0;
-      acc3 += x1 * c0;
-      acc4 += x2 * c0;
-      acc5 += x3 * c0;
-      acc6 += x4 * c0;
-      acc7 += x5 * c0;
-
-      /* Read the b[numTaps-4] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-6] sample */
-      x6 = *(px++);
-
-      /* Perform the multiply-accumulates */
-      acc0 += x7 * c0;
-      acc1 += x0 * c0;
-      acc2 += x1 * c0;
-      acc3 += x2 * c0;
-      acc4 += x3 * c0;
-      acc5 += x4 * c0;
-      acc6 += x5 * c0;
-      acc7 += x6 * c0;
-
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x8u;
-
-    while(tapCnt > 0u)
-    {
-      /* Read coefficients */
-      c0 = *(pb++);
-
-      /* Fetch 1 state variable */
-      x7 = *(px++);
-
-      /* Perform the multiply-accumulates */
-      acc0 += x0 * c0;
-      acc1 += x1 * c0;
-      acc2 += x2 * c0;
-      acc3 += x3 * c0;
-      acc4 += x4 * c0;
-      acc5 += x5 * c0;
-      acc6 += x6 * c0;
-      acc7 += x7 * c0;
-
-      /* Reuse the present sample states for next sample */
-      x0 = x1;
-      x1 = x2;
-      x2 = x3;
-      x3 = x4;
-      x4 = x5;
-      x5 = x6;
-      x6 = x7;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance the state pointer by 4 to process the next group of 4 samples */
-    pState = pState + 8;
-
-    /* The results in the 4 accumulators, store in the destination buffer. */
-    *pDst++ = acc0;
-    *pDst++ = acc1;
-    *pDst++ = acc2;
-    *pDst++ = acc3;
-    *pDst++ = acc4;
-    *pDst++ = acc5;
-    *pDst++ = acc6;
-    *pDst++ = acc7;
-
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.  
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x8u;
-
-  while(blkCnt > 0u)
-  {
-    /* Copy one sample at a time into state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Set the accumulator to zero */
-    acc0 = 0.0f;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize Coefficient pointer */
-    pb = (pCoeffs);
-
-    i = numTaps;
-
-    /* Perform the multiply-accumulates */
-    do
-    {
-      acc0 += *px++ * *pb++;
-      i--;
-
-    } while(i > 0u);
-
-    /* The result is store in the destination buffer. */
-    *pDst++ = acc0;
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1;
-
-    blkCnt--;
-  }
-
-  /* Processing is complete.  
-   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.  
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  tapCnt = (numTaps - 1u) >> 2u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-  /* Calculate remaining number of copies */
-  tapCnt = (numTaps - 1u) % 0x4u;
-
-  /* Copy the remaining q31_t data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-}
-
-#else
-
-void arm_fir_f32(
-  const arm_fir_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize)
-{
-  float32_t *pState = S->pState;                 /* State pointer */
-  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
-  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
-  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
-  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
-  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
-
-  /* Run the below code for Cortex-M0 */
-
-  float32_t acc;
-
-  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  /* Initialize blkCnt with blockSize */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* Copy one sample at a time into state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Set the accumulator to zero */
-    acc = 0.0f;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize Coefficient pointer */
-    pb = pCoeffs;
-
-    i = numTaps;
-
-    /* Perform the multiply-accumulates */
-    do
-    {
-      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
-      acc += *px++ * *pb++;
-      i--;
-
-    } while(i > 0u);
-
-    /* The result is store in the destination buffer. */
-    *pDst++ = acc;
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1;
-
-    blkCnt--;
-  }
-
-  /* Processing is complete.         
-   ** Now copy the last numTaps - 1 samples to the starting of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  /* Copy numTaps number of values */
-  tapCnt = numTaps - 1u;
-
-  /* Copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-}
-
-#endif /*   #ifndef ARM_MATH_CM0 */
-
-/**  
- * @} end of FIR group  
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q15.c
deleted file mode 100644
index 02634327bc..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q15.c
+++ /dev/null
@@ -1,341 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_fast_q15.c    
-*    
-* Description:  Q15 Fast FIR filter processing function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.9  2010/08/16     
-*    Initial version    
-*    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR    
- * @{    
- */
-
-/**    
- * @param[in] *S points to an instance of the Q15 FIR filter structure.    
- * @param[in] *pSrc points to the block of input data.    
- * @param[out] *pDst points to the block of output data.    
- * @param[in] blockSize number of samples to process per call.    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * This fast version uses a 32-bit accumulator with 2.30 format.    
- * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
- * Thus, if the accumulator result overflows it wraps around and distorts the result.    
- * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.    
- * The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.    
- *    
- * \par    
- * Refer to the function arm_fir_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.  Both the slow and the fast versions use the same instance structure.    
- * Use the function arm_fir_init_q15() to initialize the filter structure.    
- */
-
-void arm_fir_fast_q15(
-  const arm_fir_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pState = S->pState;                     /* State pointer */
-  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators */
-  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */
-  q15_t *px;                                     /* Temporary q31 pointer for SIMD state buffer accesses */
-  q31_t x0, x1, x2, c0;                          /* Temporary variables to hold SIMD state and coefficient values */
-  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */
-  uint32_t tapCnt, blkCnt;                       /* Loop counters */
-
-
-  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  /* Apply loop unrolling and compute 4 output values simultaneously.      
-   * The variables acc0 ... acc3 hold output values that are being computed:      
-   *      
-   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]      
-   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]      
-   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]      
-   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]      
-   */
-
-  blkCnt = blockSize >> 2;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.      
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* Copy four new input samples into the state buffer.      
-     ** Use 32-bit SIMD to move the 16-bit data.  Only requires two copies. */
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-
-
-    /* Set all accumulators to zero */
-    acc0 = 0;
-    acc1 = 0;
-    acc2 = 0;
-    acc3 = 0;
-
-    /* Typecast q15_t pointer to q31_t pointer for state reading in q31_t */
-    px = pState;
-
-    /* Typecast q15_t pointer to q31_t pointer for coefficient reading in q31_t */
-    pb = pCoeffs;
-
-    /* Read the first two samples from the state buffer:  x[n-N], x[n-N-1] */
-    x0 = *__SIMD32(px)++;
-
-    /* Read the third and forth samples from the state buffer: x[n-N-2], x[n-N-3] */
-    x2 = *__SIMD32(px)++;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.      
-     ** Repeat until we've computed numTaps-(numTaps%4) coefficients. */
-    tapCnt = numTaps >> 2;
-
-    while(tapCnt > 0)
-    {
-      /* Read the first two coefficients using SIMD:  b[N] and b[N-1] coefficients */
-      c0 = *__SIMD32(pb)++;
-
-      /* acc0 +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */
-      acc0 = __SMLAD(x0, c0, acc0);
-
-      /* acc2 +=  b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
-      acc2 = __SMLAD(x2, c0, acc2);
-
-      /* pack  x[n-N-1] and x[n-N-2] */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x1 = __PKHBT(x2, x0, 0);
-#else
-      x1 = __PKHBT(x0, x2, 0);
-#endif
-
-      /* Read state x[n-N-4], x[n-N-5] */
-      x0 = _SIMD32_OFFSET(px);
-
-      /* acc1 +=  b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
-      acc1 = __SMLADX(x1, c0, acc1);
-
-      /* pack  x[n-N-3] and x[n-N-4] */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x1 = __PKHBT(x0, x2, 0);
-#else
-      x1 = __PKHBT(x2, x0, 0);
-#endif
-
-      /* acc3 +=  b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
-      acc3 = __SMLADX(x1, c0, acc3);
-
-      /* Read coefficients b[N-2], b[N-3] */
-      c0 = *__SIMD32(pb)++;
-
-      /* acc0 +=  b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
-      acc0 = __SMLAD(x2, c0, acc0);
-
-      /* Read state x[n-N-6], x[n-N-7] with offset */
-      x2 = _SIMD32_OFFSET(px + 2u);
-
-      /* acc2 +=  b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
-      acc2 = __SMLAD(x0, c0, acc2);
-
-      /* acc1 +=  b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
-      acc1 = __SMLADX(x1, c0, acc1);
-
-      /* pack  x[n-N-5] and x[n-N-6] */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x1 = __PKHBT(x2, x0, 0);
-#else
-      x1 = __PKHBT(x0, x2, 0);
-#endif
-
-      /* acc3 +=  b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
-      acc3 = __SMLADX(x1, c0, acc3);
-
-      /* Update state pointer for next state reading */
-      px += 4u;
-
-      /* Decrement tap count */
-      tapCnt--;
-
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps.       
-     ** This is always be 2 taps since the filter length is even. */
-    if((numTaps & 0x3u) != 0u)
-    {
-
-      /* Read last two coefficients */
-      c0 = *__SIMD32(pb)++;
-
-      /* Perform the multiply-accumulates */
-      acc0 = __SMLAD(x0, c0, acc0);
-      acc2 = __SMLAD(x2, c0, acc2);
-
-      /* pack state variables */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x1 = __PKHBT(x2, x0, 0);
-#else
-      x1 = __PKHBT(x0, x2, 0);
-#endif
-
-      /* Read last state variables */
-      x0 = *__SIMD32(px);
-
-      /* Perform the multiply-accumulates */
-      acc1 = __SMLADX(x1, c0, acc1);
-
-      /* pack state variables */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x1 = __PKHBT(x0, x2, 0);
-#else
-      x1 = __PKHBT(x2, x0, 0);
-#endif
-
-      /* Perform the multiply-accumulates */
-      acc3 = __SMLADX(x1, c0, acc3);
-    }
-
-    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.15 with saturation.       
-     ** Then store the 4 outputs in the destination buffer. */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    *__SIMD32(pDst)++ =
-      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
-
-    *__SIMD32(pDst)++ =
-      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
-
-#else
-
-    *__SIMD32(pDst)++ =
-      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
-
-    *__SIMD32(pDst)++ =
-      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
-
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */
-
-    /* Advance the state pointer by 4 to process the next group of 4 samples */
-    pState = pState + 4u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.      
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-  while(blkCnt > 0u)
-  {
-    /* Copy two samples into state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Set the accumulator to zero */
-    acc0 = 0;
-
-    /* Use SIMD to hold states and coefficients */
-    px = pState;
-    pb = pCoeffs;
-
-    tapCnt = numTaps >> 1u;
-
-    do
-    {
-
-      acc0 += (q31_t) * px++ * *pb++;
-	  acc0 += (q31_t) * px++ * *pb++;
-
-      tapCnt--;
-    }
-    while(tapCnt > 0u);
-
-    /* The result is in 2.30 format.  Convert to 1.15 with saturation.      
-     ** Then store the output in the destination buffer. */
-    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.      
-   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.      
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  /* Calculation of count for copying integer writes */
-  tapCnt = (numTaps - 1u) >> 2;
-
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    tapCnt--;
-
-  }
-
-  /* Calculation of count for remaining q15_t data */
-  tapCnt = (numTaps - 1u) % 0x4u;
-
-  /* copy remaining data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-}
-
-/**    
- * @} end of FIR group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q31.c
deleted file mode 100644
index eeccb6c8a0..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q31.c
+++ /dev/null
@@ -1,309 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_fast_q31.c    
-*    
-* Description:	Processing function for the Q31 Fast FIR filter.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.9  2010/08/27     
-*    Initial version    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR    
- * @{    
- */
-
-/**    
- * @param[in] *S points to an instance of the Q31 structure.    
- * @param[in] *pSrc points to the block of input data.    
- * @param[out] *pDst points to the block output data.    
- * @param[in] blockSize number of samples to process per call.    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * This function is optimized for speed at the expense of fixed-point precision and overflow protection.    
- * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.    
- * These intermediate results are added to a 2.30 accumulator.    
- * Finally, the accumulator is saturated and converted to a 1.31 result.    
- * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.    
- * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.    
- *    
- * \par    
- * Refer to the function arm_fir_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.  Both the slow and the fast versions use the same instance structure.    
- * Use the function arm_fir_init_q31() to initialize the filter structure.    
- */
-
-void arm_fir_fast_q31(
-  const arm_fir_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  q31_t *pState = S->pState;                     /* State pointer */
-  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q31_t x0, x1, x2, x3;                          /* Temporary variables to hold state */
-  q31_t c0;                                      /* Temporary variable to hold coefficient value */
-  q31_t *px;                                     /* Temporary pointer for state */
-  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
-  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators */
-  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
-  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
-
-  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  /* Apply loop unrolling and compute 4 output values simultaneously.    
-   * The variables acc0 ... acc3 hold output values that are being computed:    
-   *    
-   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]    
-   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]    
-   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]    
-   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]    
-   */
-  blkCnt = blockSize >> 2;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* Copy four new input samples into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-
-    /* Set all accumulators to zero */
-    acc0 = 0;
-    acc1 = 0;
-    acc2 = 0;
-    acc3 = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize coefficient pointer */
-    pb = pCoeffs;
-
-    /* Read the first three samples from the state buffer:    
-     *  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
-    x0 = *(px++);
-    x1 = *(px++);
-    x2 = *(px++);
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-    i = tapCnt;
-
-    while(i > 0u)
-    {
-      /* Read the b[numTaps] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-3] sample */
-      x3 = *(px++);
-
-      /* acc0 +=  b[numTaps] * x[n-numTaps] */
-      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
-
-      /* acc1 +=  b[numTaps] * x[n-numTaps-1] */
-      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
-
-      /* acc2 +=  b[numTaps] * x[n-numTaps-2] */
-      acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
-
-      /* acc3 +=  b[numTaps] * x[n-numTaps-3] */
-      acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
-
-      /* Read the b[numTaps-1] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-4] sample */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulates */
-      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
-      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
-      acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
-      acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
-
-      /* Read the b[numTaps-2] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-5] sample */
-      x1 = *(px++);
-
-      /* Perform the multiply-accumulates */
-      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
-      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
-      acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
-      acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
-
-      /* Read the b[numTaps-3] coefficients */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-6] sample */
-      x2 = *(px++);
-
-      /* Perform the multiply-accumulates */
-      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
-      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
-      acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
-      acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
-      i--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-
-    i = numTaps - (tapCnt * 4u);
-    while(i > 0u)
-    {
-      /* Read coefficients */
-      c0 = *(pb++);
-
-      /* Fetch 1 state variable */
-      x3 = *(px++);
-
-      /* Perform the multiply-accumulates */
-      acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
-      acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
-      acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
-      acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
-
-      /* Reuse the present sample states for next sample */
-      x0 = x1;
-      x1 = x2;
-      x2 = x3;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Advance the state pointer by 4 to process the next group of 4 samples */
-    pState = pState + 4;
-
-    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.31    
-     ** Then store the 4 outputs in the destination buffer. */
-    *pDst++ = (q31_t) (acc0 << 1);
-    *pDst++ = (q31_t) (acc1 << 1);
-    *pDst++ = (q31_t) (acc2 << 1);
-    *pDst++ = (q31_t) (acc3 << 1);
-
-    /* Decrement the samples loop counter */
-    blkCnt--;
-  }
-
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 4u;
-
-  while(blkCnt > 0u)
-  {
-    /* Copy one sample at a time into state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Set the accumulator to zero */
-    acc0 = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize Coefficient pointer */
-    pb = (pCoeffs);
-
-    i = numTaps;
-
-    /* Perform the multiply-accumulates */
-    do
-    {
-      acc0 =
-        (q31_t) ((((q63_t) acc0 << 32) +
-                  ((q63_t) (*px++) * (*(pb++)))) >> 32);
-      i--;
-    } while(i > 0u);
-
-    /* The result is in 2.30 format.  Convert to 1.31    
-     ** Then store the output in the destination buffer. */
-    *pDst++ = (q31_t) (acc0 << 1);
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1;
-
-    /* Decrement the samples loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.    
-   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.    
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  tapCnt = (numTaps - 1u) >> 2u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-  /* Calculate remaining number of copies */
-  tapCnt = (numTaps - 1u) % 0x4u;
-
-  /* Copy the remaining q31_t data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-
-}
-
-/**    
- * @} end of FIR group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_f32.c
deleted file mode 100644
index 4665ad135d..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_f32.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_init_f32.c    
-*    
-* Description:  Floating-point FIR filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-* 	 incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR    
- * @{    
- */
-
-/**    
- * @details    
- *    
- * @param[in,out] *S points to an instance of the floating-point FIR filter structure.    
- * @param[in] 	  numTaps  Number of filter coefficients in the filter.    
- * @param[in]     *pCoeffs points to the filter coefficients buffer.    
- * @param[in]     *pState points to the state buffer.    
- * @param[in] 	  blockSize number of samples that are processed per call.    
- * @return 		  none.    
- *    
- * Description:    
- * \par    
- * pCoeffs points to the array of filter coefficients stored in time reversed order:    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * \par    
- * pState points to the array of state variables.    
- * pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_f32().    
- */
-
-void arm_fir_init_f32(
-  arm_fir_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  uint32_t blockSize)
-{
-  /* Assign filter taps */
-  S->numTaps = numTaps;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and the size of state buffer is (blockSize + numTaps - 1) */
-  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-}
-
-/**    
- * @} end of FIR group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q15.c
deleted file mode 100644
index cb113916ff..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q15.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_init_q15.c    
-*    
-* Description:  Q15 FIR filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-* 	 incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* ------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR    
- * @{    
- */
-
-/**    
- * @param[in,out]  *S points to an instance of the Q15 FIR filter structure.    
- * @param[in] 	   numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.    
- * @param[in]      *pCoeffs points to the filter coefficients buffer.    
- * @param[in]      *pState points to the state buffer.    
- * @param[in]      blockSize is number of samples processed per call.    
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if    
- * numTaps is not greater than or equal to 4 and even.    
- *    
- * Description:    
- * \par    
- * pCoeffs points to the array of filter coefficients stored in time reversed order:    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * Note that numTaps must be even and greater than or equal to 4.    
- * To implement an odd length filter simply increase numTaps by 1 and set the last coefficient to zero.    
- * For example, to implement a filter with numTaps=3 and coefficients    
- * 
    
- *     {0.3, -0.8, 0.3}    
- * 
    
- * set numTaps=4 and use the coefficients:    
- * 
    
- *     {0.3, -0.8, 0.3, 0}.    
- * 
    
- * Similarly, to implement a two point filter    
- * 
    
- *     {0.3, -0.3}    
- * 
    
- * set numTaps=4 and use the coefficients:    
- * 
    
- *     {0.3, -0.3, 0, 0}.    
- * 
    
- * \par    
- * pState points to the array of state variables.    
- * pState is of length numTaps+blockSize, when running on Cortex-M4 and Cortex-M3  and is of length numTaps+blockSize-1, when running on Cortex-M0 where blockSize is the number of input samples processed by each call to arm_fir_q15().    
- */
-
-arm_status arm_fir_init_q15(
-  arm_fir_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  uint32_t blockSize)
-{
-  arm_status status;
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /* The Number of filter coefficients in the filter must be even and at least 4 */
-  if(numTaps & 0x1u)
-  {
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-  else
-  {
-    /* Assign filter taps */
-    S->numTaps = numTaps;
-
-    /* Assign coefficient pointer */
-    S->pCoeffs = pCoeffs;
-
-    /* Clear the state buffer.  The size is always (blockSize + numTaps ) */
-    memset(pState, 0, (numTaps + (blockSize)) * sizeof(q15_t));
-
-    /* Assign state pointer */
-    S->pState = pState;
-
-    status = ARM_MATH_SUCCESS;
-  }
-
-  return (status);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Assign filter taps */
-  S->numTaps = numTaps;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear the state buffer.  The size is always (blockSize + numTaps - 1) */
-  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-  status = ARM_MATH_SUCCESS;
-
-  return (status);
-
-#endif /*  #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
- * @} end of FIR group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q31.c
deleted file mode 100644
index 121db2a886..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q31.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_init_q31.c    
-*    
-* Description:	Q31 FIR filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-* 	 incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR    
- * @{    
- */
-
-/**    
- * @details    
- *    
- * @param[in,out] *S points to an instance of the Q31 FIR filter structure.    
- * @param[in] 	  numTaps  Number of filter coefficients in the filter.    
- * @param[in] 	  *pCoeffs points to the filter coefficients buffer.    
- * @param[in] 	  *pState points to the state buffer.    
- * @param[in] 	  blockSize number of samples that are processed per call.    
- * @return        none.    
- *    
- * Description:    
- * \par    
- * pCoeffs points to the array of filter coefficients stored in time reversed order:    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * \par    
- * pState points to the array of state variables.    
- * pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q31().    
- */
-
-void arm_fir_init_q31(
-  arm_fir_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  uint32_t blockSize)
-{
-  /* Assign filter taps */
-  S->numTaps = numTaps;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and state array size is (blockSize + numTaps - 1) */
-  memset(pState, 0, (blockSize + ((uint32_t) numTaps - 1u)) * sizeof(q31_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-}
-
-/**    
- * @} end of FIR group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q7.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q7.c
deleted file mode 100644
index 1ea905cb6a..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q7.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_init_q7.c    
-*    
-* Description:  Q7 FIR filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-* 	 incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* ------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR    
- * @{    
- */
-/**    
- * @param[in,out] *S points to an instance of the Q7 FIR filter structure.    
- * @param[in] 	  numTaps  Number of filter coefficients in the filter.    
- * @param[in] 	  *pCoeffs points to the filter coefficients buffer.    
- * @param[in]     *pState points to the state buffer.    
- * @param[in]     blockSize number of samples that are processed per call.    
- * @return     	  none    
- *    
- * Description:    
- * \par    
- * pCoeffs points to the array of filter coefficients stored in time reversed order:    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * \par    
- * pState points to the array of state variables.    
- * pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q7().    
- */
-
-void arm_fir_init_q7(
-  arm_fir_instance_q7 * S,
-  uint16_t numTaps,
-  q7_t * pCoeffs,
-  q7_t * pState,
-  uint32_t blockSize)
-{
-
-  /* Assign filter taps */
-  S->numTaps = numTaps;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear the state buffer.  The size is always (blockSize + numTaps - 1) */
-  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q7_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-}
-
-/**    
- * @} end of FIR group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_f32.c
deleted file mode 100644
index 24e072cdec..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_f32.c
+++ /dev/null
@@ -1,574 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_interpolate_f32.c    
-*    
-* Description:	FIR interpolation for floating-point sequences.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @defgroup FIR_Interpolate Finite Impulse Response (FIR) Interpolator    
- *    
- * These functions combine an upsampler (zero stuffer) and an FIR filter.    
- * They are used in multirate systems for increasing the sample rate of a signal without introducing high frequency images.    
- * Conceptually, the functions are equivalent to the block diagram below:    
- * \image html FIRInterpolator.gif "Components included in the FIR Interpolator functions"    
- * After upsampling by a factor of L, the signal should be filtered by a lowpass filter with a normalized    
- * cutoff frequency of 1/L in order to eliminate high frequency copies of the spectrum.    
- * The user of the function is responsible for providing the filter coefficients.    
- *    
- * The FIR interpolator functions provided in the CMSIS DSP Library combine the upsampler and FIR filter in an efficient manner.    
- * The upsampler inserts L-1 zeros between each sample.    
- * Instead of multiplying by these zero values, the FIR filter is designed to skip them.    
- * This leads to an efficient implementation without any wasted effort.    
- * The functions operate on blocks of input and output data.    
- * pSrc points to an array of blockSize input values and    
- * pDst points to an array of blockSize*L output values.    
- *    
- * The library provides separate functions for Q15, Q31, and floating-point data types.    
- *    
- * \par Algorithm:    
- * The functions use a polyphase filter structure:    
- * 
    
- *    y[n] = b[0] * x[n] + b[L]   * x[n-1] + ... + b[L*(phaseLength-1)] * x[n-phaseLength+1]    
- *    y[n+1] = b[1] * x[n] + b[L+1] * x[n-1] + ... + b[L*(phaseLength-1)+1] * x[n-phaseLength+1]    
- *    ...    
- *    y[n+(L-1)] = b[L-1] * x[n] + b[2*L-1] * x[n-1] + ....+ b[L*(phaseLength-1)+(L-1)] * x[n-phaseLength+1]    
- * 
    
- * This approach is more efficient than straightforward upsample-then-filter algorithms.    
- * With this method the computation is reduced by a factor of 1/L when compared to using a standard FIR filter.    
- * \par    
- * pCoeffs points to a coefficient array of size numTaps.    
- * numTaps must be a multiple of the interpolation factor L and this is checked by the    
- * initialization functions.    
- * Internally, the function divides the FIR filter's impulse response into shorter filters of length    
- * phaseLength=numTaps/L.    
- * Coefficients are stored in time reversed order.    
- * \par    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * \par    
- * pState points to a state array of size blockSize + phaseLength - 1.    
- * Samples in the state buffer are stored in the order:    
- * \par    
- * 
    
- *    {x[n-phaseLength+1], x[n-phaseLength], x[n-phaseLength-1], x[n-phaseLength-2]....x[0], x[1], ..., x[blockSize-1]}    
- * 
    
- * The state variables are updated after each block of data is processed, the coefficients are untouched.    
- *    
- * \par Instance Structure    
- * The coefficients and state variables for a filter are stored together in an instance data structure.    
- * A separate instance structure must be defined for each filter.    
- * Coefficient arrays may be shared among several instances while state variable array should be allocated separately.    
- * There are separate instance structure declarations for each of the 3 supported data types.    
- *    
- * \par Initialization Functions    
- * There is also an associated initialization function for each data type.    
- * The initialization function performs the following operations:    
- * - Sets the values of the internal structure fields.    
- * - Zeros out the values in the state buffer.    
- * - Checks to make sure that the length of the filter is a multiple of the interpolation factor.    
- *    
- * \par    
- * Use of the initialization function is optional.    
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
- * To place an instance structure into a const data section, the instance structure must be manually initialized.    
- * The code below statically initializes each of the 3 different data type filter instance structures    
- * 
    
- * arm_fir_interpolate_instance_f32 S = {L, phaseLength, pCoeffs, pState};    
- * arm_fir_interpolate_instance_q31 S = {L, phaseLength, pCoeffs, pState};    
- * arm_fir_interpolate_instance_q15 S = {L, phaseLength, pCoeffs, pState};    
- * 
    
- * where L is the interpolation factor; phaseLength=numTaps/L is the    
- * length of each of the shorter FIR filters used internally,    
- * pCoeffs is the address of the coefficient buffer;    
- * pState is the address of the state buffer.    
- * Be sure to set the values in the state buffer to zeros when doing static initialization.    
- *    
- * \par Fixed-Point Behavior    
- * Care must be taken when using the fixed-point versions of the FIR interpolate filter functions.    
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.    
- * Refer to the function specific documentation below for usage guidelines.    
- */
-
-/**    
- * @addtogroup FIR_Interpolate    
- * @{    
- */
-
-/**    
- * @brief Processing function for the floating-point FIR interpolator.    
- * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.    
- * @param[in] *pSrc     points to the block of input data.    
- * @param[out] *pDst    points to the block of output data.    
- * @param[in] blockSize number of input samples to process per call.    
- * @return none.    
- */
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-void arm_fir_interpolate_f32(
-  const arm_fir_interpolate_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize)
-{
-  float32_t *pState = S->pState;                 /* State pointer */
-  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
-  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
-  float32_t *ptr1, *ptr2;                        /* Temporary pointers for state and coefficient buffers */
-  float32_t sum0;                                /* Accumulators */
-  float32_t x0, c0;                              /* Temporary variables to hold state and coefficient values */
-  uint32_t i, blkCnt, j;                         /* Loop counters */
-  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
-  float32_t acc0, acc1, acc2, acc3;
-  float32_t x1, x2, x3;
-  uint32_t blkCntN4;
-  float32_t c1, c2, c3;
-
-  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + (phaseLen - 1u);
-
-  /* Initialise  blkCnt */
-  blkCnt = blockSize / 4;
-  blkCntN4 = blockSize - (4 * blkCnt);
-
-  /* Samples loop unrolled by 4 */
-  while(blkCnt > 0u)
-  {
-    /* Copy new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-
-    /* Address modifier index of coefficient buffer */
-    j = 1u;
-
-    /* Loop over the Interpolation factor. */
-    i = (S->L);
-
-    while(i > 0u)
-    {
-      /* Set accumulator to zero */
-      acc0 = 0.0f;
-      acc1 = 0.0f;
-      acc2 = 0.0f;
-      acc3 = 0.0f;
-
-      /* Initialize state pointer */
-      ptr1 = pState;
-
-      /* Initialize coefficient pointer */
-      ptr2 = pCoeffs + (S->L - j);
-
-      /* Loop over the polyPhase length. Unroll by a factor of 4.        
-       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
-      tapCnt = phaseLen >> 2u;
-
-      x0 = *(ptr1++);
-      x1 = *(ptr1++);
-      x2 = *(ptr1++);
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read the input sample */
-        x3 = *(ptr1++);
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Perform the multiply-accumulate */
-        acc0 += x0 * c0;
-        acc1 += x1 * c0;
-        acc2 += x2 * c0;
-        acc3 += x3 * c0;
-
-        /* Read the coefficient */
-        c1 = *(ptr2 + S->L);
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        acc0 += x1 * c1;
-        acc1 += x2 * c1;
-        acc2 += x3 * c1;
-        acc3 += x0 * c1;
-
-        /* Read the coefficient */
-        c2 = *(ptr2 + S->L * 2);
-
-        /* Read the input sample */
-        x1 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        acc0 += x2 * c2;
-        acc1 += x3 * c2;
-        acc2 += x0 * c2;
-        acc3 += x1 * c2;
-
-        /* Read the coefficient */
-        c3 = *(ptr2 + S->L * 3);
-
-        /* Read the input sample */
-        x2 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        acc0 += x3 * c3;
-        acc1 += x0 * c3;
-        acc2 += x1 * c3;
-        acc3 += x2 * c3;
-
-
-        /* Upsampling is done by stuffing L-1 zeros between each sample.        
-         * So instead of multiplying zeros with coefficients,        
-         * Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += 4 * S->L;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
-      tapCnt = phaseLen % 0x4u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read the input sample */
-        x3 = *(ptr1++);
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Perform the multiply-accumulate */
-        acc0 += x0 * c0;
-        acc1 += x1 * c0;
-        acc2 += x2 * c0;
-        acc3 += x3 * c0;
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* update states for next sample processing */
-        x0 = x1;
-        x1 = x2;
-        x2 = x3;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* The result is in the accumulator, store in the destination buffer. */
-      *pDst = acc0;
-      *(pDst + S->L) = acc1;
-      *(pDst + 2 * S->L) = acc2;
-      *(pDst + 3 * S->L) = acc3;
-
-      pDst++;
-
-      /* Increment the address modifier index of coefficient buffer */
-      j++;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Advance the state pointer by 1        
-     * to process the next group of interpolation factor number samples */
-    pState = pState + 4;
-
-    pDst += S->L * 3;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.        
-   ** No loop unrolling is used. */
-
-  while(blkCntN4 > 0u)
-  {
-    /* Copy new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Address modifier index of coefficient buffer */
-    j = 1u;
-
-    /* Loop over the Interpolation factor. */
-    i = S->L;
-    while(i > 0u)
-    {
-      /* Set accumulator to zero */
-      sum0 = 0.0f;
-
-      /* Initialize state pointer */
-      ptr1 = pState;
-
-      /* Initialize coefficient pointer */
-      ptr2 = pCoeffs + (S->L - j);
-
-      /* Loop over the polyPhase length. Unroll by a factor of 4.        
-       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
-      tapCnt = phaseLen >> 2u;
-      while(tapCnt > 0u)
-      {
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Upsampling is done by stuffing L-1 zeros between each sample.        
-         * So instead of multiplying zeros with coefficients,        
-         * Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        sum0 += x0 * c0;
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        sum0 += x0 * c0;
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        sum0 += x0 * c0;
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        sum0 += x0 * c0;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
-      tapCnt = phaseLen % 0x4u;
-
-      while(tapCnt > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum0 += *(ptr1++) * (*ptr2);
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* The result is in the accumulator, store in the destination buffer. */
-      *pDst++ = sum0;
-
-      /* Increment the address modifier index of coefficient buffer */
-      j++;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Advance the state pointer by 1        
-     * to process the next group of interpolation factor number samples */
-    pState = pState + 1;
-
-    /* Decrement the loop counter */
-    blkCntN4--;
-  }
-
-  /* Processing is complete.        
-   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.        
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  tapCnt = (phaseLen - 1u) >> 2u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-  tapCnt = (phaseLen - 1u) % 0x04u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-}
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-void arm_fir_interpolate_f32(
-  const arm_fir_interpolate_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize)
-{
-  float32_t *pState = S->pState;                 /* State pointer */
-  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
-  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
-  float32_t *ptr1, *ptr2;                        /* Temporary pointers for state and coefficient buffers */
-
-
-  float32_t sum;                                 /* Accumulator */
-  uint32_t i, blkCnt;                            /* Loop counters */
-  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
-
-
-  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + (phaseLen - 1u);
-
-  /* Total number of intput samples */
-  blkCnt = blockSize;
-
-  /* Loop over the blockSize. */
-  while(blkCnt > 0u)
-  {
-    /* Copy new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Loop over the Interpolation factor. */
-    i = S->L;
-
-    while(i > 0u)
-    {
-      /* Set accumulator to zero */
-      sum = 0.0f;
-
-      /* Initialize state pointer */
-      ptr1 = pState;
-
-      /* Initialize coefficient pointer */
-      ptr2 = pCoeffs + (i - 1u);
-
-      /* Loop over the polyPhase length */
-      tapCnt = phaseLen;
-
-      while(tapCnt > 0u)
-      {
-        /* Perform the multiply-accumulate */
-        sum += *ptr1++ * *ptr2;
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* The result is in the accumulator, store in the destination buffer. */
-      *pDst++ = sum;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Advance the state pointer by 1           
-     * to process the next group of interpolation factor number samples */
-    pState = pState + 1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.         
-   ** Now copy the last phaseLen - 1 samples to the start of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  tapCnt = phaseLen - 1u;
-
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-}
-
-#endif /*   #ifndef ARM_MATH_CM0 */
-
-
-
- /**    
-  * @} end of FIR_Interpolate group    
-  */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c
deleted file mode 100644
index 097c883b6c..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_interpolate_init_f32.c    
-*    
-* Description:  Floating-point FIR interpolator initialization function    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_Interpolate    
- * @{    
- */
-
-/**    
- * @brief  Initialization function for the floating-point FIR interpolator.    
- * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.    
- * @param[in]     L         upsample factor.    
- * @param[in]     numTaps   number of filter coefficients in the filter.    
- * @param[in]     *pCoeffs  points to the filter coefficient buffer.    
- * @param[in]     *pState   points to the state buffer.    
- * @param[in]     blockSize number of input samples to process per call.    
- * @return        The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if    
- * the filter length numTaps is not a multiple of the interpolation factor L.    
- *    
- * Description:    
- * \par    
- * pCoeffs points to the array of filter coefficients stored in time reversed order:    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}    
- * 
    
- * The length of the filter numTaps must be a multiple of the interpolation factor L.    
- * \par    
- * pState points to the array of state variables.    
- * pState is of length (numTaps/L)+blockSize-1 words    
- * where blockSize is the number of input samples processed by each call to arm_fir_interpolate_f32().    
- */
-
-arm_status arm_fir_interpolate_init_f32(
-  arm_fir_interpolate_instance_f32 * S,
-  uint8_t L,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  uint32_t blockSize)
-{
-  arm_status status;
-
-  /* The filter length must be a multiple of the interpolation factor */
-  if((numTaps % L) != 0u)
-  {
-    /* Set status as ARM_MATH_LENGTH_ERROR */
-    status = ARM_MATH_LENGTH_ERROR;
-  }
-  else
-  {
-
-    /* Assign coefficient pointer */
-    S->pCoeffs = pCoeffs;
-
-    /* Assign Interpolation factor */
-    S->L = L;
-
-    /* Assign polyPhaseLength */
-    S->phaseLength = numTaps / L;
-
-    /* Clear state buffer and size of state array is always phaseLength + blockSize - 1 */
-    memset(pState, 0,
-           (blockSize +
-            ((uint32_t) S->phaseLength - 1u)) * sizeof(float32_t));
-
-    /* Assign state pointer */
-    S->pState = pState;
-
-    status = ARM_MATH_SUCCESS;
-  }
-
-  return (status);
-
-}
-
- /**    
-  * @} end of FIR_Interpolate group    
-  */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c
deleted file mode 100644
index d147d10b3a..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_interpolate_init_q15.c    
-*    
-* Description:  Q15 FIR interpolator initialization function    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_Interpolate    
- * @{    
- */
-
-/**    
- * @brief  Initialization function for the Q15 FIR interpolator.    
- * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.    
- * @param[in]     L         upsample factor.    
- * @param[in]     numTaps   number of filter coefficients in the filter.    
- * @param[in]     *pCoeffs  points to the filter coefficient buffer.    
- * @param[in]     *pState   points to the state buffer.    
- * @param[in]     blockSize number of input samples to process per call.    
- * @return        The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if    
- * the filter length numTaps is not a multiple of the interpolation factor L.    
- *    
- * Description:    
- * \par    
- * pCoeffs points to the array of filter coefficients stored in time reversed order:    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}    
- * 
    
- * The length of the filter numTaps must be a multiple of the interpolation factor L.    
- * \par    
- * pState points to the array of state variables.    
- * pState is of length (numTaps/L)+blockSize-1 words    
- * where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q15().    
- */
-
-arm_status arm_fir_interpolate_init_q15(
-  arm_fir_interpolate_instance_q15 * S,
-  uint8_t L,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  uint32_t blockSize)
-{
-  arm_status status;
-
-  /* The filter length must be a multiple of the interpolation factor */
-  if((numTaps % L) != 0u)
-  {
-    /* Set status as ARM_MATH_LENGTH_ERROR */
-    status = ARM_MATH_LENGTH_ERROR;
-  }
-  else
-  {
-
-    /* Assign coefficient pointer */
-    S->pCoeffs = pCoeffs;
-
-    /* Assign Interpolation factor */
-    S->L = L;
-
-    /* Assign polyPhaseLength */
-    S->phaseLength = numTaps / L;
-
-    /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */
-    memset(pState, 0,
-           (blockSize + ((uint32_t) S->phaseLength - 1u)) * sizeof(q15_t));
-
-    /* Assign state pointer */
-    S->pState = pState;
-
-    status = ARM_MATH_SUCCESS;
-  }
-
-  return (status);
-
-}
-
- /**    
-  * @} end of FIR_Interpolate group    
-  */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c
deleted file mode 100644
index 21e25dd542..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_interpolate_init_q31.c    
-*    
-* Description:  Q31 FIR interpolator initialization function    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_Interpolate    
- * @{    
- */
-
-
-/**    
- * @brief  Initialization function for the Q31 FIR interpolator.    
- * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.    
- * @param[in]     L         upsample factor.    
- * @param[in]     numTaps   number of filter coefficients in the filter.    
- * @param[in]     *pCoeffs  points to the filter coefficient buffer.    
- * @param[in]     *pState   points to the state buffer.    
- * @param[in]     blockSize number of input samples to process per call.    
- * @return        The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if    
- * the filter length numTaps is not a multiple of the interpolation factor L.    
- *    
- * Description:    
- * \par    
- * pCoeffs points to the array of filter coefficients stored in time reversed order:    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}    
- * 
    
- * The length of the filter numTaps must be a multiple of the interpolation factor L.    
- * \par    
- * pState points to the array of state variables.    
- * pState is of length (numTaps/L)+blockSize-1 words    
- * where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q31().    
- */
-
-arm_status arm_fir_interpolate_init_q31(
-  arm_fir_interpolate_instance_q31 * S,
-  uint8_t L,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  uint32_t blockSize)
-{
-  arm_status status;
-
-  /* The filter length must be a multiple of the interpolation factor */
-  if((numTaps % L) != 0u)
-  {
-    /* Set status as ARM_MATH_LENGTH_ERROR */
-    status = ARM_MATH_LENGTH_ERROR;
-  }
-  else
-  {
-
-    /* Assign coefficient pointer */
-    S->pCoeffs = pCoeffs;
-
-    /* Assign Interpolation factor */
-    S->L = L;
-
-    /* Assign polyPhaseLength */
-    S->phaseLength = numTaps / L;
-
-    /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */
-    memset(pState, 0,
-           (blockSize + ((uint32_t) S->phaseLength - 1u)) * sizeof(q31_t));
-
-    /* Assign state pointer */
-    S->pState = pState;
-
-    status = ARM_MATH_SUCCESS;
-  }
-
-  return (status);
-
-}
-
- /**    
-  * @} end of FIR_Interpolate group    
-  */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q15.c
deleted file mode 100644
index 3f11c47ae4..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q15.c
+++ /dev/null
@@ -1,503 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_fir_interpolate_q15.c    
-*    
-* Description:	Q15 FIR interpolation.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_Interpolate    
- * @{    
- */
-
-/**    
- * @brief Processing function for the Q15 FIR interpolator.    
- * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.    
- * @param[in] *pSrc     points to the block of input data.    
- * @param[out] *pDst    points to the block of output data.    
- * @param[in] blockSize number of input samples to process per call.    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using a 64-bit internal accumulator.    
- * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.    
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    
- * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.    
- * Lastly, the accumulator is saturated to yield a result in 1.15 format.    
- */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-void arm_fir_interpolate_q15(
-  const arm_fir_interpolate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pState = S->pState;                     /* State pointer                                            */
-  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer                                      */
-  q15_t *pStateCurnt;                            /* Points to the current sample of the state                */
-  q15_t *ptr1, *ptr2;                            /* Temporary pointers for state and coefficient buffers     */
-  q63_t sum0;                                    /* Accumulators                                             */
-  q15_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
-  uint32_t i, blkCnt, j, tapCnt;                 /* Loop counters                                            */
-  uint16_t phaseLen = S->phaseLength;            /* Length of each polyphase filter component */
-  uint32_t blkCntN2;
-  q63_t acc0, acc1;
-  q15_t x1;
-
-  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
-
-  /* Initialise  blkCnt */
-  blkCnt = blockSize / 2;
-  blkCntN2 = blockSize - (2 * blkCnt);
-
-  /* Samples loop unrolled by 2 */
-  while(blkCnt > 0u)
-  {
-    /* Copy new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-
-    /* Address modifier index of coefficient buffer */
-    j = 1u;
-
-    /* Loop over the Interpolation factor. */
-    i = (S->L);
-
-    while(i > 0u)
-    {
-      /* Set accumulator to zero */
-      acc0 = 0;
-      acc1 = 0;
-
-      /* Initialize state pointer */
-      ptr1 = pState;
-
-      /* Initialize coefficient pointer */
-      ptr2 = pCoeffs + (S->L - j);
-
-      /* Loop over the polyPhase length. Unroll by a factor of 4.        
-       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
-      tapCnt = phaseLen >> 2u;
-
-      x0 = *(ptr1++);
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read the input sample */
-        x1 = *(ptr1++);
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Perform the multiply-accumulate */
-        acc0 += (q63_t) x0 *c0;
-        acc1 += (q63_t) x1 *c0;
-
-
-        /* Read the coefficient */
-        c0 = *(ptr2 + S->L);
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        acc0 += (q63_t) x1 *c0;
-        acc1 += (q63_t) x0 *c0;
-
-
-        /* Read the coefficient */
-        c0 = *(ptr2 + S->L * 2);
-
-        /* Read the input sample */
-        x1 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        acc0 += (q63_t) x0 *c0;
-        acc1 += (q63_t) x1 *c0;
-
-        /* Read the coefficient */
-        c0 = *(ptr2 + S->L * 3);
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        acc0 += (q63_t) x1 *c0;
-        acc1 += (q63_t) x0 *c0;
-
-
-        /* Upsampling is done by stuffing L-1 zeros between each sample.        
-         * So instead of multiplying zeros with coefficients,        
-         * Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += 4 * S->L;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
-      tapCnt = phaseLen % 0x4u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read the input sample */
-        x1 = *(ptr1++);
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Perform the multiply-accumulate */
-        acc0 += (q63_t) x0 *c0;
-        acc1 += (q63_t) x1 *c0;
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* update states for next sample processing */
-        x0 = x1;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* The result is in the accumulator, store in the destination buffer. */
-      *pDst = (q15_t) (__SSAT((acc0 >> 15), 16));
-      *(pDst + S->L) = (q15_t) (__SSAT((acc1 >> 15), 16));
-
-      pDst++;
-
-      /* Increment the address modifier index of coefficient buffer */
-      j++;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Advance the state pointer by 1        
-     * to process the next group of interpolation factor number samples */
-    pState = pState + 2;
-
-    pDst += S->L;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 2, compute any remaining output samples here.        
-   ** No loop unrolling is used. */
-  blkCnt = blkCntN2;
-
-  /* Loop over the blockSize. */
-  while(blkCnt > 0u)
-  {
-    /* Copy new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Address modifier index of coefficient buffer */
-    j = 1u;
-
-    /* Loop over the Interpolation factor. */
-    i = S->L;
-    while(i > 0u)
-    {
-      /* Set accumulator to zero */
-      sum0 = 0;
-
-      /* Initialize state pointer */
-      ptr1 = pState;
-
-      /* Initialize coefficient pointer */
-      ptr2 = pCoeffs + (S->L - j);
-
-      /* Loop over the polyPhase length. Unroll by a factor of 4.        
-       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
-      tapCnt = phaseLen >> 2;
-      while(tapCnt > 0u)
-      {
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Upsampling is done by stuffing L-1 zeros between each sample.        
-         * So instead of multiplying zeros with coefficients,        
-         * Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        sum0 += (q63_t) x0 *c0;
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        sum0 += (q63_t) x0 *c0;
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        sum0 += (q63_t) x0 *c0;
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        sum0 += (q63_t) x0 *c0;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
-      tapCnt = phaseLen & 0x3u;
-
-      while(tapCnt > 0u)
-      {
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        sum0 += (q63_t) x0 *c0;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* The result is in the accumulator, store in the destination buffer. */
-      *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
-
-      j++;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Advance the state pointer by 1        
-     * to process the next group of interpolation factor number samples */
-    pState = pState + 1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-
-  /* Processing is complete.    
-   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.    
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  i = ((uint32_t) phaseLen - 1u) >> 2u;
-
-  /* copy data */
-  while(i > 0u)
-  {
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-
-#else
-
-    *pStateCurnt++ = *pState++;
-	*pStateCurnt++ = *pState++;
-	*pStateCurnt++ = *pState++;
-	*pStateCurnt++ = *pState++;
-	
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-	
-	/* Decrement the loop counter */
-    i--;
-  }
-
-  i = ((uint32_t) phaseLen - 1u) % 0x04u;
-
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-}
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-void arm_fir_interpolate_q15(
-  const arm_fir_interpolate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pState = S->pState;                     /* State pointer                                            */
-  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer                                      */
-  q15_t *pStateCurnt;                            /* Points to the current sample of the state                */
-  q15_t *ptr1, *ptr2;                            /* Temporary pointers for state and coefficient buffers     */
-  q63_t sum;                                     /* Accumulator */
-  q15_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
-  uint32_t i, blkCnt, tapCnt;                    /* Loop counters                                            */
-  uint16_t phaseLen = S->phaseLength;            /* Length of each polyphase filter component */
-
-
-  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + (phaseLen - 1u);
-
-  /* Total number of intput samples */
-  blkCnt = blockSize;
-
-  /* Loop over the blockSize. */
-  while(blkCnt > 0u)
-  {
-    /* Copy new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Loop over the Interpolation factor. */
-    i = S->L;
-
-    while(i > 0u)
-    {
-      /* Set accumulator to zero */
-      sum = 0;
-
-      /* Initialize state pointer */
-      ptr1 = pState;
-
-      /* Initialize coefficient pointer */
-      ptr2 = pCoeffs + (i - 1u);
-
-      /* Loop over the polyPhase length */
-      tapCnt = (uint32_t) phaseLen;
-
-      while(tapCnt > 0u)
-      {
-        /* Read the coefficient */
-        c0 = *ptr2;
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *ptr1++;
-
-        /* Perform the multiply-accumulate */
-        sum += ((q31_t) x0 * c0);
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* Store the result after converting to 1.15 format in the destination buffer */
-      *pDst++ = (q15_t) (__SSAT((sum >> 15), 16));
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Advance the state pointer by 1           
-     * to process the next group of interpolation factor number samples */
-    pState = pState + 1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.         
-   ** Now copy the last phaseLen - 1 samples to the start of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  i = (uint32_t) phaseLen - 1u;
-
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-}
-
-#endif /*   #ifndef ARM_MATH_CM0 */
-
-
- /**    
-  * @} end of FIR_Interpolate group    
-  */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q31.c
deleted file mode 100644
index 05e64e1465..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q31.c
+++ /dev/null
@@ -1,499 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_fir_interpolate_q31.c    
-*    
-* Description:	Q31 FIR interpolation.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_Interpolate    
- * @{    
- */
-
-/**    
- * @brief Processing function for the Q31 FIR interpolator.    
- * @param[in] *S        points to an instance of the Q31 FIR interpolator structure.    
- * @param[in] *pSrc     points to the block of input data.    
- * @param[out] *pDst    points to the block of output data.    
- * @param[in] blockSize number of input samples to process per call.    
- * @return none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using an internal 64-bit accumulator.    
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
- * Thus, if the accumulator result overflows it wraps around rather than clip.    
- * In order to avoid overflows completely the input signal must be scaled down by 1/(numTaps/L).    
- * since numTaps/L additions occur per output sample.    
- * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.    
- */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-void arm_fir_interpolate_q31(
-  const arm_fir_interpolate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  q31_t *pState = S->pState;                     /* State pointer */
-  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q31_t *ptr1, *ptr2;                            /* Temporary pointers for state and coefficient buffers */
-  q63_t sum0;                                    /* Accumulators */
-  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
-  uint32_t i, blkCnt, j;                         /* Loop counters */
-  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
-
-  uint32_t blkCntN2;
-  q63_t acc0, acc1;
-  q31_t x1;
-
-  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
-
-  /* Initialise  blkCnt */
-  blkCnt = blockSize / 2;
-  blkCntN2 = blockSize - (2 * blkCnt);
-
-  /* Samples loop unrolled by 2 */
-  while(blkCnt > 0u)
-  {
-    /* Copy new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-
-    /* Address modifier index of coefficient buffer */
-    j = 1u;
-
-    /* Loop over the Interpolation factor. */
-    i = (S->L);
-
-    while(i > 0u)
-    {
-      /* Set accumulator to zero */
-      acc0 = 0;
-      acc1 = 0;
-
-      /* Initialize state pointer */
-      ptr1 = pState;
-
-      /* Initialize coefficient pointer */
-      ptr2 = pCoeffs + (S->L - j);
-
-      /* Loop over the polyPhase length. Unroll by a factor of 4.        
-       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
-      tapCnt = phaseLen >> 2u;
-
-      x0 = *(ptr1++);
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read the input sample */
-        x1 = *(ptr1++);
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Perform the multiply-accumulate */
-        acc0 += (q63_t) x0 *c0;
-        acc1 += (q63_t) x1 *c0;
-
-
-        /* Read the coefficient */
-        c0 = *(ptr2 + S->L);
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        acc0 += (q63_t) x1 *c0;
-        acc1 += (q63_t) x0 *c0;
-
-
-        /* Read the coefficient */
-        c0 = *(ptr2 + S->L * 2);
-
-        /* Read the input sample */
-        x1 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        acc0 += (q63_t) x0 *c0;
-        acc1 += (q63_t) x1 *c0;
-
-        /* Read the coefficient */
-        c0 = *(ptr2 + S->L * 3);
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        acc0 += (q63_t) x1 *c0;
-        acc1 += (q63_t) x0 *c0;
-
-
-        /* Upsampling is done by stuffing L-1 zeros between each sample.        
-         * So instead of multiplying zeros with coefficients,        
-         * Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += 4 * S->L;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
-      tapCnt = phaseLen % 0x4u;
-
-      while(tapCnt > 0u)
-      {
-
-        /* Read the input sample */
-        x1 = *(ptr1++);
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Perform the multiply-accumulate */
-        acc0 += (q63_t) x0 *c0;
-        acc1 += (q63_t) x1 *c0;
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* update states for next sample processing */
-        x0 = x1;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* The result is in the accumulator, store in the destination buffer. */
-      *pDst = (q31_t) (acc0 >> 31);
-      *(pDst + S->L) = (q31_t) (acc1 >> 31);
-
-
-      pDst++;
-
-      /* Increment the address modifier index of coefficient buffer */
-      j++;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Advance the state pointer by 1        
-     * to process the next group of interpolation factor number samples */
-    pState = pState + 2;
-
-    pDst += S->L;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 2, compute any remaining output samples here.        
-   ** No loop unrolling is used. */
-  blkCnt = blkCntN2;
-
-  /* Loop over the blockSize. */
-  while(blkCnt > 0u)
-  {
-    /* Copy new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Address modifier index of coefficient buffer */
-    j = 1u;
-
-    /* Loop over the Interpolation factor. */
-    i = S->L;
-    while(i > 0u)
-    {
-      /* Set accumulator to zero */
-      sum0 = 0;
-
-      /* Initialize state pointer */
-      ptr1 = pState;
-
-      /* Initialize coefficient pointer */
-      ptr2 = pCoeffs + (S->L - j);
-
-      /* Loop over the polyPhase length. Unroll by a factor of 4.        
-       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
-      tapCnt = phaseLen >> 2;
-      while(tapCnt > 0u)
-      {
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Upsampling is done by stuffing L-1 zeros between each sample.        
-         * So instead of multiplying zeros with coefficients,        
-         * Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        sum0 += (q63_t) x0 *c0;
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        sum0 += (q63_t) x0 *c0;
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        sum0 += (q63_t) x0 *c0;
-
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        sum0 += (q63_t) x0 *c0;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
-      tapCnt = phaseLen & 0x3u;
-
-      while(tapCnt > 0u)
-      {
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *(ptr1++);
-
-        /* Perform the multiply-accumulate */
-        sum0 += (q63_t) x0 *c0;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* The result is in the accumulator, store in the destination buffer. */
-      *pDst++ = (q31_t) (sum0 >> 31);
-
-      /* Increment the address modifier index of coefficient buffer */
-      j++;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Advance the state pointer by 1        
-     * to process the next group of interpolation factor number samples */
-    pState = pState + 1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.        
-   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.        
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  tapCnt = (phaseLen - 1u) >> 2u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-  tapCnt = (phaseLen - 1u) % 0x04u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-}
-
-
-#else
-
-void arm_fir_interpolate_q31(
-  const arm_fir_interpolate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  q31_t *pState = S->pState;                     /* State pointer */
-  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q31_t *ptr1, *ptr2;                            /* Temporary pointers for state and coefficient buffers */
-
-  /* Run the below code for Cortex-M0 */
-
-  q63_t sum;                                     /* Accumulator */
-  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
-  uint32_t i, blkCnt;                            /* Loop counters */
-  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
-
-
-  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
-
-  /* Total number of intput samples */
-  blkCnt = blockSize;
-
-  /* Loop over the blockSize. */
-  while(blkCnt > 0u)
-  {
-    /* Copy new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Loop over the Interpolation factor. */
-    i = S->L;
-
-    while(i > 0u)
-    {
-      /* Set accumulator to zero */
-      sum = 0;
-
-      /* Initialize state pointer */
-      ptr1 = pState;
-
-      /* Initialize coefficient pointer */
-      ptr2 = pCoeffs + (i - 1u);
-
-      tapCnt = phaseLen;
-
-      while(tapCnt > 0u)
-      {
-        /* Read the coefficient */
-        c0 = *(ptr2);
-
-        /* Increment the coefficient pointer by interpolation factor times. */
-        ptr2 += S->L;
-
-        /* Read the input sample */
-        x0 = *ptr1++;
-
-        /* Perform the multiply-accumulate */
-        sum += (q63_t) x0 *c0;
-
-        /* Decrement the loop counter */
-        tapCnt--;
-      }
-
-      /* The result is in the accumulator, store in the destination buffer. */
-      *pDst++ = (q31_t) (sum >> 31);
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Advance the state pointer by 1           
-     * to process the next group of interpolation factor number samples */
-    pState = pState + 1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.         
-   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  tapCnt = phaseLen - 1u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-}
-
-#endif /*   #ifndef ARM_MATH_CM0 */
-
- /**    
-  * @} end of FIR_Interpolate group    
-  */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_f32.c
deleted file mode 100644
index 3b5fc9408f..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_f32.c
+++ /dev/null
@@ -1,499 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_lattice_f32.c    
-*    
-* Description:	Processing function for the floating-point FIR Lattice filter.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @defgroup FIR_Lattice Finite Impulse Response (FIR) Lattice Filters    
- *    
- * This set of functions implements Finite Impulse Response (FIR) lattice filters    
- * for Q15, Q31 and floating-point data types.  Lattice filters are used in a     
- * variety of adaptive filter applications.  The filter structure is feedforward and    
- * the net impulse response is finite length.    
- * The functions operate on blocks    
- * of input and output data and each call to the function processes    
- * blockSize samples through the filter.  pSrc and    
- * pDst point to input and output arrays containing blockSize values.    
- *    
- * \par Algorithm:    
- * \image html FIRLattice.gif "Finite Impulse Response Lattice filter"    
- * The following difference equation is implemented:    
- * 
    
- *    f0[n] = g0[n] = x[n]    
- *    fm[n] = fm-1[n] + km * gm-1[n-1] for m = 1, 2, ...M    
- *    gm[n] = km * fm-1[n] + gm-1[n-1] for m = 1, 2, ...M    
- *    y[n] = fM[n]    
- * 
    
- * \par    
- * pCoeffs points to tha array of reflection coefficients of size numStages.    
- * Reflection Coefficients are stored in the following order.    
- * \par    
- * 
    
- *    {k1, k2, ..., kM}    
- * 
    
- * where M is number of stages    
- * \par    
- * pState points to a state array of size numStages.    
- * The state variables (g values) hold previous inputs and are stored in the following order.    
- * 
    
- *    {g0[n], g1[n], g2[n] ...gM-1[n]}    
- * 
    
- * The state variables are updated after each block of data is processed; the coefficients are untouched.    
- * \par Instance Structure    
- * The coefficients and state variables for a filter are stored together in an instance data structure.    
- * A separate instance structure must be defined for each filter.    
- * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.    
- * There are separate instance structure declarations for each of the 3 supported data types.    
- *    
- * \par Initialization Functions    
- * There is also an associated initialization function for each data type.    
- * The initialization function performs the following operations:    
- * - Sets the values of the internal structure fields.    
- * - Zeros out the values in the state buffer.    
- *    
- * \par    
- * Use of the initialization function is optional.    
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
- * To place an instance structure into a const data section, the instance structure must be manually initialized.    
- * Set the values in the state buffer to zeros and then manually initialize the instance structure as follows:    
- * 
    
- *arm_fir_lattice_instance_f32 S = {numStages, pState, pCoeffs};    
- *arm_fir_lattice_instance_q31 S = {numStages, pState, pCoeffs};    
- *arm_fir_lattice_instance_q15 S = {numStages, pState, pCoeffs};    
- * 
    
- * \par    
- * where numStages is the number of stages in the filter; pState is the address of the state buffer;    
- * pCoeffs is the address of the coefficient buffer.    
- * \par Fixed-Point Behavior    
- * Care must be taken when using the fixed-point versions of the FIR Lattice filter functions.    
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.    
- * Refer to the function specific documentation below for usage guidelines.    
- */
-
-/**    
- * @addtogroup FIR_Lattice    
- * @{    
- */
-
-
-  /**    
-   * @brief Processing function for the floating-point FIR lattice filter.    
-   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.    
-   * @param[in]  *pSrc     points to the block of input data.    
-   * @param[out] *pDst     points to the block of output data    
-   * @param[in]  blockSize number of samples to process.    
-   * @return none.    
-   */
-
-void arm_fir_lattice_f32(
-  const arm_fir_lattice_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize)
-{
-  float32_t *pState;                             /* State pointer */
-  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
-  float32_t *px;                                 /* temporary state pointer */
-  float32_t *pk;                                 /* temporary coefficient pointer */
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  float32_t fcurr1, fnext1, gcurr1, gnext1;      /* temporary variables for first sample in loop unrolling */
-  float32_t fcurr2, fnext2, gnext2;              /* temporary variables for second sample in loop unrolling */
-  float32_t fcurr3, fnext3, gnext3;              /* temporary variables for third sample in loop unrolling */
-  float32_t fcurr4, fnext4, gnext4;              /* temporary variables for fourth sample in loop unrolling */
-  uint32_t numStages = S->numStages;             /* Number of stages in the filter */
-  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
-
-  gcurr1 = 0.0f;
-  pState = &S->pState[0];
-
-  blkCnt = blockSize >> 2;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-     a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-
-    /* Read two samples from input buffer */
-    /* f0(n) = x(n) */
-    fcurr1 = *pSrc++;
-    fcurr2 = *pSrc++;
-
-    /* Initialize coeff pointer */
-    pk = (pCoeffs);
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Read g0(n-1) from state */
-    gcurr1 = *px;
-
-    /* Process first sample for first tap */
-    /* f1(n) = f0(n) +  K1 * g0(n-1) */
-    fnext1 = fcurr1 + ((*pk) * gcurr1);
-    /* g1(n) = f0(n) * K1  +  g0(n-1) */
-    gnext1 = (fcurr1 * (*pk)) + gcurr1;
-
-    /* Process second sample for first tap */
-    /* for sample 2 processing */
-    fnext2 = fcurr2 + ((*pk) * fcurr1);
-    gnext2 = (fcurr2 * (*pk)) + fcurr1;
-
-    /* Read next two samples from input buffer */
-    /* f0(n+2) = x(n+2) */
-    fcurr3 = *pSrc++;
-    fcurr4 = *pSrc++;
-
-    /* Copy only last input samples into the state buffer    
-       which will be used for next four samples processing */
-    *px++ = fcurr4;
-
-    /* Process third sample for first tap */
-    fnext3 = fcurr3 + ((*pk) * fcurr2);
-    gnext3 = (fcurr3 * (*pk)) + fcurr2;
-
-    /* Process fourth sample for first tap */
-    fnext4 = fcurr4 + ((*pk) * fcurr3);
-    gnext4 = (fcurr4 * (*pk++)) + fcurr3;
-
-    /* Update of f values for next coefficient set processing */
-    fcurr1 = fnext1;
-    fcurr2 = fnext2;
-    fcurr3 = fnext3;
-    fcurr4 = fnext4;
-
-    /* Loop unrolling.  Process 4 taps at a time . */
-    stageCnt = (numStages - 1u) >> 2u;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.    
-     ** Repeat until we've computed numStages-3 coefficients. */
-
-    /* Process 2nd, 3rd, 4th and 5th taps ... here */
-    while(stageCnt > 0u)
-    {
-      /* Read g1(n-1), g3(n-1) .... from state */
-      gcurr1 = *px;
-
-      /* save g1(n) in state buffer */
-      *px++ = gnext4;
-
-      /* Process first sample for 2nd, 6th .. tap */
-      /* Sample processing for K2, K6.... */
-      /* f2(n) = f1(n) +  K2 * g1(n-1) */
-      fnext1 = fcurr1 + ((*pk) * gcurr1);
-      /* Process second sample for 2nd, 6th .. tap */
-      /* for sample 2 processing */
-      fnext2 = fcurr2 + ((*pk) * gnext1);
-      /* Process third sample for 2nd, 6th .. tap */
-      fnext3 = fcurr3 + ((*pk) * gnext2);
-      /* Process fourth sample for 2nd, 6th .. tap */
-      fnext4 = fcurr4 + ((*pk) * gnext3);
-
-      /* g2(n) = f1(n) * K2  +  g1(n-1) */
-      /* Calculation of state values for next stage */
-      gnext4 = (fcurr4 * (*pk)) + gnext3;
-      gnext3 = (fcurr3 * (*pk)) + gnext2;
-      gnext2 = (fcurr2 * (*pk)) + gnext1;
-      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
-
-
-      /* Read g2(n-1), g4(n-1) .... from state */
-      gcurr1 = *px;
-
-      /* save g2(n) in state buffer */
-      *px++ = gnext4;
-
-      /* Sample processing for K3, K7.... */
-      /* Process first sample for 3rd, 7th .. tap */
-      /* f3(n) = f2(n) +  K3 * g2(n-1) */
-      fcurr1 = fnext1 + ((*pk) * gcurr1);
-      /* Process second sample for 3rd, 7th .. tap */
-      fcurr2 = fnext2 + ((*pk) * gnext1);
-      /* Process third sample for 3rd, 7th .. tap */
-      fcurr3 = fnext3 + ((*pk) * gnext2);
-      /* Process fourth sample for 3rd, 7th .. tap */
-      fcurr4 = fnext4 + ((*pk) * gnext3);
-
-      /* Calculation of state values for next stage */
-      /* g3(n) = f2(n) * K3  +  g2(n-1) */
-      gnext4 = (fnext4 * (*pk)) + gnext3;
-      gnext3 = (fnext3 * (*pk)) + gnext2;
-      gnext2 = (fnext2 * (*pk)) + gnext1;
-      gnext1 = (fnext1 * (*pk++)) + gcurr1;
-
-
-      /* Read g1(n-1), g3(n-1) .... from state */
-      gcurr1 = *px;
-
-      /* save g3(n) in state buffer */
-      *px++ = gnext4;
-
-      /* Sample processing for K4, K8.... */
-      /* Process first sample for 4th, 8th .. tap */
-      /* f4(n) = f3(n) +  K4 * g3(n-1) */
-      fnext1 = fcurr1 + ((*pk) * gcurr1);
-      /* Process second sample for 4th, 8th .. tap */
-      /* for sample 2 processing */
-      fnext2 = fcurr2 + ((*pk) * gnext1);
-      /* Process third sample for 4th, 8th .. tap */
-      fnext3 = fcurr3 + ((*pk) * gnext2);
-      /* Process fourth sample for 4th, 8th .. tap */
-      fnext4 = fcurr4 + ((*pk) * gnext3);
-
-      /* g4(n) = f3(n) * K4  +  g3(n-1) */
-      /* Calculation of state values for next stage */
-      gnext4 = (fcurr4 * (*pk)) + gnext3;
-      gnext3 = (fcurr3 * (*pk)) + gnext2;
-      gnext2 = (fcurr2 * (*pk)) + gnext1;
-      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
-
-      /* Read g2(n-1), g4(n-1) .... from state */
-      gcurr1 = *px;
-
-      /* save g4(n) in state buffer */
-      *px++ = gnext4;
-
-      /* Sample processing for K5, K9.... */
-      /* Process first sample for 5th, 9th .. tap */
-      /* f5(n) = f4(n) +  K5 * g4(n-1) */
-      fcurr1 = fnext1 + ((*pk) * gcurr1);
-      /* Process second sample for 5th, 9th .. tap */
-      fcurr2 = fnext2 + ((*pk) * gnext1);
-      /* Process third sample for 5th, 9th .. tap */
-      fcurr3 = fnext3 + ((*pk) * gnext2);
-      /* Process fourth sample for 5th, 9th .. tap */
-      fcurr4 = fnext4 + ((*pk) * gnext3);
-
-      /* Calculation of state values for next stage */
-      /* g5(n) = f4(n) * K5  +  g4(n-1) */
-      gnext4 = (fnext4 * (*pk)) + gnext3;
-      gnext3 = (fnext3 * (*pk)) + gnext2;
-      gnext2 = (fnext2 * (*pk)) + gnext1;
-      gnext1 = (fnext1 * (*pk++)) + gcurr1;
-
-      stageCnt--;
-    }
-
-    /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */
-    stageCnt = (numStages - 1u) % 0x4u;
-
-    while(stageCnt > 0u)
-    {
-      gcurr1 = *px;
-
-      /* save g value in state buffer */
-      *px++ = gnext4;
-
-      /* Process four samples for last three taps here */
-      fnext1 = fcurr1 + ((*pk) * gcurr1);
-      fnext2 = fcurr2 + ((*pk) * gnext1);
-      fnext3 = fcurr3 + ((*pk) * gnext2);
-      fnext4 = fcurr4 + ((*pk) * gnext3);
-
-      /* g1(n) = f0(n) * K1  +  g0(n-1) */
-      gnext4 = (fcurr4 * (*pk)) + gnext3;
-      gnext3 = (fcurr3 * (*pk)) + gnext2;
-      gnext2 = (fcurr2 * (*pk)) + gnext1;
-      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
-
-      /* Update of f values for next coefficient set processing */
-      fcurr1 = fnext1;
-      fcurr2 = fnext2;
-      fcurr3 = fnext3;
-      fcurr4 = fnext4;
-
-      stageCnt--;
-
-    }
-
-    /* The results in the 4 accumulators, store in the destination buffer. */
-    /* y(n) = fN(n) */
-    *pDst++ = fcurr1;
-    *pDst++ = fcurr2;
-    *pDst++ = fcurr3;
-    *pDst++ = fcurr4;
-
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* f0(n) = x(n) */
-    fcurr1 = *pSrc++;
-
-    /* Initialize coeff pointer */
-    pk = (pCoeffs);
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* read g2(n) from state buffer */
-    gcurr1 = *px;
-
-    /* for sample 1 processing */
-    /* f1(n) = f0(n) +  K1 * g0(n-1) */
-    fnext1 = fcurr1 + ((*pk) * gcurr1);
-    /* g1(n) = f0(n) * K1  +  g0(n-1) */
-    gnext1 = (fcurr1 * (*pk++)) + gcurr1;
-
-    /* save g1(n) in state buffer */
-    *px++ = fcurr1;
-
-    /* f1(n) is saved in fcurr1    
-       for next stage processing */
-    fcurr1 = fnext1;
-
-    stageCnt = (numStages - 1u);
-
-    /* stage loop */
-    while(stageCnt > 0u)
-    {
-      /* read g2(n) from state buffer */
-      gcurr1 = *px;
-
-      /* save g1(n) in state buffer */
-      *px++ = gnext1;
-
-      /* Sample processing for K2, K3.... */
-      /* f2(n) = f1(n) +  K2 * g1(n-1) */
-      fnext1 = fcurr1 + ((*pk) * gcurr1);
-      /* g2(n) = f1(n) * K2  +  g1(n-1) */
-      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
-
-      /* f1(n) is saved in fcurr1    
-         for next stage processing */
-      fcurr1 = fnext1;
-
-      stageCnt--;
-
-    }
-
-    /* y(n) = fN(n) */
-    *pDst++ = fcurr1;
-
-    blkCnt--;
-
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  float32_t fcurr, fnext, gcurr, gnext;          /* temporary variables */
-  uint32_t numStages = S->numStages;             /* Length of the filter */
-  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
-
-  pState = &S->pState[0];
-
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* f0(n) = x(n) */
-    fcurr = *pSrc++;
-
-    /* Initialize coeff pointer */
-    pk = pCoeffs;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* read g0(n-1) from state buffer */
-    gcurr = *px;
-
-    /* for sample 1 processing */
-    /* f1(n) = f0(n) +  K1 * g0(n-1) */
-    fnext = fcurr + ((*pk) * gcurr);
-    /* g1(n) = f0(n) * K1  +  g0(n-1) */
-    gnext = (fcurr * (*pk++)) + gcurr;
-
-    /* save f0(n) in state buffer */
-    *px++ = fcurr;
-
-    /* f1(n) is saved in fcurr            
-       for next stage processing */
-    fcurr = fnext;
-
-    stageCnt = (numStages - 1u);
-
-    /* stage loop */
-    while(stageCnt > 0u)
-    {
-      /* read g2(n) from state buffer */
-      gcurr = *px;
-
-      /* save g1(n) in state buffer */
-      *px++ = gnext;
-
-      /* Sample processing for K2, K3.... */
-      /* f2(n) = f1(n) +  K2 * g1(n-1) */
-      fnext = fcurr + ((*pk) * gcurr);
-      /* g2(n) = f1(n) * K2  +  g1(n-1) */
-      gnext = (fcurr * (*pk++)) + gcurr;
-
-      /* f1(n) is saved in fcurr1            
-         for next stage processing */
-      fcurr = fnext;
-
-      stageCnt--;
-
-    }
-
-    /* y(n) = fN(n) */
-    *pDst++ = fcurr;
-
-    blkCnt--;
-
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
- * @} end of FIR_Lattice group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_f32.c
deleted file mode 100644
index 13f3bab16b..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_f32.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_lattice_init_f32.c    
-*    
-* Description:  Floating-point FIR Lattice filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_Lattice    
- * @{    
- */
-
-/**    
- * @brief Initialization function for the floating-point FIR lattice filter.    
- * @param[in] *S points to an instance of the floating-point FIR lattice structure.    
- * @param[in] numStages  number of filter stages.    
- * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.    
- * @param[in] *pState points to the state buffer.  The array is of length numStages.    
- * @return none.    
- */
-
-void arm_fir_lattice_init_f32(
-  arm_fir_lattice_instance_f32 * S,
-  uint16_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState)
-{
-  /* Assign filter taps */
-  S->numStages = numStages;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and size is always numStages */
-  memset(pState, 0, (numStages) * sizeof(float32_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-}
-
-/**    
- * @} end of FIR_Lattice group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q15.c
deleted file mode 100644
index 8bdc71a7c8..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q15.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_lattice_init_q15.c    
-*    
-* Description:  Q15 FIR Lattice filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_Lattice    
- * @{    
- */
-
-  /**    
-   * @brief Initialization function for the Q15 FIR lattice filter.    
-   * @param[in] *S points to an instance of the Q15 FIR lattice structure.    
-   * @param[in] numStages  number of filter stages.    
-   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.     
-   * @param[in] *pState points to the state buffer.  The array is of length numStages.     
-   * @return none.    
-   */
-
-void arm_fir_lattice_init_q15(
-  arm_fir_lattice_instance_q15 * S,
-  uint16_t numStages,
-  q15_t * pCoeffs,
-  q15_t * pState)
-{
-  /* Assign filter taps */
-  S->numStages = numStages;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and size is always numStages */
-  memset(pState, 0, (numStages) * sizeof(q15_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-}
-
-/**    
- * @} end of FIR_Lattice group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q31.c
deleted file mode 100644
index b79d3844f2..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q31.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_lattice_init_q31.c    
-*    
-* Description:  Q31 FIR lattice filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_Lattice    
- * @{    
- */
-
-  /**    
-   * @brief Initialization function for the Q31 FIR lattice filter.    
-   * @param[in] *S points to an instance of the Q31 FIR lattice structure.    
-   * @param[in] numStages  number of filter stages.    
-   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.    
-   * @param[in] *pState points to the state buffer.   The array is of length numStages.    
-   * @return none.    
-   */
-
-void arm_fir_lattice_init_q31(
-  arm_fir_lattice_instance_q31 * S,
-  uint16_t numStages,
-  q31_t * pCoeffs,
-  q31_t * pState)
-{
-  /* Assign filter taps */
-  S->numStages = numStages;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and size is always numStages */
-  memset(pState, 0, (numStages) * sizeof(q31_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-}
-
-/**    
- * @} end of FIR_Lattice group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q15.c
deleted file mode 100644
index 655b9b5fb8..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q15.c
+++ /dev/null
@@ -1,531 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_lattice_q15.c    
-*    
-* Description:	Q15 FIR lattice filter processing function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_Lattice    
- * @{    
- */
-
-
-/**    
- * @brief Processing function for the Q15 FIR lattice filter.    
- * @param[in]  *S        points to an instance of the Q15 FIR lattice structure.    
- * @param[in]  *pSrc     points to the block of input data.    
- * @param[out] *pDst     points to the block of output data    
- * @param[in]  blockSize number of samples to process.    
- * @return none.    
- */
-
-void arm_fir_lattice_q15(
-  const arm_fir_lattice_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pState;                                 /* State pointer */
-  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q15_t *px;                                     /* temporary state pointer */
-  q15_t *pk;                                     /* temporary coefficient pointer */
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t fcurnt1, fnext1, gcurnt1 = 0, gnext1;    /* temporary variables for first sample in loop unrolling */
-  q31_t fcurnt2, fnext2, gnext2;                 /* temporary variables for second sample in loop unrolling */
-  q31_t fcurnt3, fnext3, gnext3;                 /* temporary variables for third sample in loop unrolling */
-  q31_t fcurnt4, fnext4, gnext4;                 /* temporary variables for fourth sample in loop unrolling */
-  uint32_t numStages = S->numStages;             /* Number of stages in the filter */
-  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
-
-  pState = &S->pState[0];
-
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-
-    /* Read two samples from input buffer */
-    /* f0(n) = x(n) */
-    fcurnt1 = *pSrc++;
-    fcurnt2 = *pSrc++;
-
-    /* Initialize coeff pointer */
-    pk = (pCoeffs);
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Read g0(n-1) from state */
-    gcurnt1 = *px;
-
-    /* Process first sample for first tap */
-    /* f1(n) = f0(n) +  K1 * g0(n-1) */
-    fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
-    fnext1 = __SSAT(fnext1, 16);
-
-    /* g1(n) = f0(n) * K1  +  g0(n-1) */
-    gnext1 = (q31_t) ((fcurnt1 * (*pk)) >> 15u) + gcurnt1;
-    gnext1 = __SSAT(gnext1, 16);
-
-    /* Process second sample for first tap */
-    /* for sample 2 processing */
-    fnext2 = (q31_t) ((fcurnt1 * (*pk)) >> 15u) + fcurnt2;
-    fnext2 = __SSAT(fnext2, 16);
-
-    gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + fcurnt1;
-    gnext2 = __SSAT(gnext2, 16);
-
-
-    /* Read next two samples from input buffer */
-    /* f0(n+2) = x(n+2) */
-    fcurnt3 = *pSrc++;
-    fcurnt4 = *pSrc++;
-
-    /* Copy only last input samples into the state buffer    
-       which is used for next four samples processing */
-    *px++ = (q15_t) fcurnt4;
-
-    /* Process third sample for first tap */
-    fnext3 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + fcurnt3;
-    fnext3 = __SSAT(fnext3, 16);
-    gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + fcurnt2;
-    gnext3 = __SSAT(gnext3, 16);
-
-    /* Process fourth sample for first tap */
-    fnext4 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + fcurnt4;
-    fnext4 = __SSAT(fnext4, 16);
-    gnext4 = (q31_t) ((fcurnt4 * (*pk++)) >> 15u) + fcurnt3;
-    gnext4 = __SSAT(gnext4, 16);
-
-    /* Update of f values for next coefficient set processing */
-    fcurnt1 = fnext1;
-    fcurnt2 = fnext2;
-    fcurnt3 = fnext3;
-    fcurnt4 = fnext4;
-
-
-    /* Loop unrolling.  Process 4 taps at a time . */
-    stageCnt = (numStages - 1u) >> 2;
-
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.    
-     ** Repeat until we've computed numStages-3 coefficients. */
-
-    /* Process 2nd, 3rd, 4th and 5th taps ... here */
-    while(stageCnt > 0u)
-    {
-      /* Read g1(n-1), g3(n-1) .... from state */
-      gcurnt1 = *px;
-
-      /* save g1(n) in state buffer */
-      *px++ = (q15_t) gnext4;
-
-      /* Process first sample for 2nd, 6th .. tap */
-      /* Sample processing for K2, K6.... */
-      /* f1(n) = f0(n) +  K1 * g0(n-1) */
-      fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
-      fnext1 = __SSAT(fnext1, 16);
-
-
-      /* Process second sample for 2nd, 6th .. tap */
-      /* for sample 2 processing */
-      fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
-      fnext2 = __SSAT(fnext2, 16);
-      /* Process third sample for 2nd, 6th .. tap */
-      fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
-      fnext3 = __SSAT(fnext3, 16);
-      /* Process fourth sample for 2nd, 6th .. tap */
-      /* fnext4 = fcurnt4 + (*pk) * gnext3; */
-      fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
-      fnext4 = __SSAT(fnext4, 16);
-
-      /* g1(n) = f0(n) * K1  +  g0(n-1) */
-      /* Calculation of state values for next stage */
-      gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
-      gnext4 = __SSAT(gnext4, 16);
-      gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
-      gnext3 = __SSAT(gnext3, 16);
-
-      gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
-      gnext2 = __SSAT(gnext2, 16);
-
-      gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
-      gnext1 = __SSAT(gnext1, 16);
-
-
-      /* Read g2(n-1), g4(n-1) .... from state */
-      gcurnt1 = *px;
-
-      /* save g1(n) in state buffer */
-      *px++ = (q15_t) gnext4;
-
-      /* Sample processing for K3, K7.... */
-      /* Process first sample for 3rd, 7th .. tap */
-      /* f3(n) = f2(n) +  K3 * g2(n-1) */
-      fcurnt1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fnext1;
-      fcurnt1 = __SSAT(fcurnt1, 16);
-
-      /* Process second sample for 3rd, 7th .. tap */
-      fcurnt2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fnext2;
-      fcurnt2 = __SSAT(fcurnt2, 16);
-
-      /* Process third sample for 3rd, 7th .. tap */
-      fcurnt3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fnext3;
-      fcurnt3 = __SSAT(fcurnt3, 16);
-
-      /* Process fourth sample for 3rd, 7th .. tap */
-      fcurnt4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fnext4;
-      fcurnt4 = __SSAT(fcurnt4, 16);
-
-      /* Calculation of state values for next stage */
-      /* g3(n) = f2(n) * K3  +  g2(n-1) */
-      gnext4 = (q31_t) ((fnext4 * (*pk)) >> 15u) + gnext3;
-      gnext4 = __SSAT(gnext4, 16);
-
-      gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15u) + gnext2;
-      gnext3 = __SSAT(gnext3, 16);
-
-      gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15u) + gnext1;
-      gnext2 = __SSAT(gnext2, 16);
-
-      gnext1 = (q31_t) ((fnext1 * (*pk++)) >> 15u) + gcurnt1;
-      gnext1 = __SSAT(gnext1, 16);
-
-      /* Read g1(n-1), g3(n-1) .... from state */
-      gcurnt1 = *px;
-
-      /* save g1(n) in state buffer */
-      *px++ = (q15_t) gnext4;
-
-      /* Sample processing for K4, K8.... */
-      /* Process first sample for 4th, 8th .. tap */
-      /* f4(n) = f3(n) +  K4 * g3(n-1) */
-      fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
-      fnext1 = __SSAT(fnext1, 16);
-
-      /* Process second sample for 4th, 8th .. tap */
-      /* for sample 2 processing */
-      fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
-      fnext2 = __SSAT(fnext2, 16);
-
-      /* Process third sample for 4th, 8th .. tap */
-      fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
-      fnext3 = __SSAT(fnext3, 16);
-
-      /* Process fourth sample for 4th, 8th .. tap */
-      fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
-      fnext4 = __SSAT(fnext4, 16);
-
-      /* g4(n) = f3(n) * K4  +  g3(n-1) */
-      /* Calculation of state values for next stage */
-      gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
-      gnext4 = __SSAT(gnext4, 16);
-
-      gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
-      gnext3 = __SSAT(gnext3, 16);
-
-      gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
-      gnext2 = __SSAT(gnext2, 16);
-      gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
-      gnext1 = __SSAT(gnext1, 16);
-
-
-      /* Read g2(n-1), g4(n-1) .... from state */
-      gcurnt1 = *px;
-
-      /* save g4(n) in state buffer */
-      *px++ = (q15_t) gnext4;
-
-      /* Sample processing for K5, K9.... */
-      /* Process first sample for 5th, 9th .. tap */
-      /* f5(n) = f4(n) +  K5 * g4(n-1) */
-      fcurnt1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fnext1;
-      fcurnt1 = __SSAT(fcurnt1, 16);
-
-      /* Process second sample for 5th, 9th .. tap */
-      fcurnt2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fnext2;
-      fcurnt2 = __SSAT(fcurnt2, 16);
-
-      /* Process third sample for 5th, 9th .. tap */
-      fcurnt3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fnext3;
-      fcurnt3 = __SSAT(fcurnt3, 16);
-
-      /* Process fourth sample for 5th, 9th .. tap */
-      fcurnt4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fnext4;
-      fcurnt4 = __SSAT(fcurnt4, 16);
-
-      /* Calculation of state values for next stage */
-      /* g5(n) = f4(n) * K5  +  g4(n-1) */
-      gnext4 = (q31_t) ((fnext4 * (*pk)) >> 15u) + gnext3;
-      gnext4 = __SSAT(gnext4, 16);
-      gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15u) + gnext2;
-      gnext3 = __SSAT(gnext3, 16);
-      gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15u) + gnext1;
-      gnext2 = __SSAT(gnext2, 16);
-      gnext1 = (q31_t) ((fnext1 * (*pk++)) >> 15u) + gcurnt1;
-      gnext1 = __SSAT(gnext1, 16);
-
-      stageCnt--;
-    }
-
-    /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */
-    stageCnt = (numStages - 1u) % 0x4u;
-
-    while(stageCnt > 0u)
-    {
-      gcurnt1 = *px;
-
-      /* save g value in state buffer */
-      *px++ = (q15_t) gnext4;
-
-      /* Process four samples for last three taps here */
-      fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
-      fnext1 = __SSAT(fnext1, 16);
-      fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
-      fnext2 = __SSAT(fnext2, 16);
-
-      fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
-      fnext3 = __SSAT(fnext3, 16);
-
-      fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
-      fnext4 = __SSAT(fnext4, 16);
-
-      /* g1(n) = f0(n) * K1  +  g0(n-1) */
-      gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
-      gnext4 = __SSAT(gnext4, 16);
-      gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
-      gnext3 = __SSAT(gnext3, 16);
-      gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
-      gnext2 = __SSAT(gnext2, 16);
-      gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
-      gnext1 = __SSAT(gnext1, 16);
-
-      /* Update of f values for next coefficient set processing */
-      fcurnt1 = fnext1;
-      fcurnt2 = fnext2;
-      fcurnt3 = fnext3;
-      fcurnt4 = fnext4;
-
-      stageCnt--;
-
-    }
-
-    /* The results in the 4 accumulators, store in the destination buffer. */
-    /* y(n) = fN(n) */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-    *__SIMD32(pDst)++ = __PKHBT(fcurnt1, fcurnt2, 16);
-    *__SIMD32(pDst)++ = __PKHBT(fcurnt3, fcurnt4, 16);
-
-#else
-
-    *__SIMD32(pDst)++ = __PKHBT(fcurnt2, fcurnt1, 16);
-    *__SIMD32(pDst)++ = __PKHBT(fcurnt4, fcurnt3, 16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* f0(n) = x(n) */
-    fcurnt1 = *pSrc++;
-
-    /* Initialize coeff pointer */
-    pk = (pCoeffs);
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* read g2(n) from state buffer */
-    gcurnt1 = *px;
-
-    /* for sample 1 processing */
-    /* f1(n) = f0(n) +  K1 * g0(n-1) */
-    fnext1 = (((q31_t) gcurnt1 * (*pk)) >> 15u) + fcurnt1;
-    fnext1 = __SSAT(fnext1, 16);
-
-
-    /* g1(n) = f0(n) * K1  +  g0(n-1) */
-    gnext1 = (((q31_t) fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
-    gnext1 = __SSAT(gnext1, 16);
-
-    /* save g1(n) in state buffer */
-    *px++ = (q15_t) fcurnt1;
-
-    /* f1(n) is saved in fcurnt1    
-       for next stage processing */
-    fcurnt1 = fnext1;
-
-    stageCnt = (numStages - 1u);
-
-    /* stage loop */
-    while(stageCnt > 0u)
-    {
-      /* read g2(n) from state buffer */
-      gcurnt1 = *px;
-
-      /* save g1(n) in state buffer */
-      *px++ = (q15_t) gnext1;
-
-      /* Sample processing for K2, K3.... */
-      /* f2(n) = f1(n) +  K2 * g1(n-1) */
-      fnext1 = (((q31_t) gcurnt1 * (*pk)) >> 15u) + fcurnt1;
-      fnext1 = __SSAT(fnext1, 16);
-
-      /* g2(n) = f1(n) * K2  +  g1(n-1) */
-      gnext1 = (((q31_t) fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
-      gnext1 = __SSAT(gnext1, 16);
-
-
-      /* f1(n) is saved in fcurnt1    
-         for next stage processing */
-      fcurnt1 = fnext1;
-
-      stageCnt--;
-
-    }
-
-    /* y(n) = fN(n) */
-    *pDst++ = __SSAT(fcurnt1, 16);
-
-
-    blkCnt--;
-
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q31_t fcurnt, fnext, gcurnt, gnext;            /* temporary variables */
-  uint32_t numStages = S->numStages;             /* Length of the filter */
-  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
-
-  pState = &S->pState[0];
-
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* f0(n) = x(n) */
-    fcurnt = *pSrc++;
-
-    /* Initialize coeff pointer */
-    pk = (pCoeffs);
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* read g0(n-1) from state buffer */
-    gcurnt = *px;
-
-    /* for sample 1 processing */
-    /* f1(n) = f0(n) +  K1 * g0(n-1) */
-    fnext = ((gcurnt * (*pk)) >> 15u) + fcurnt;
-    fnext = __SSAT(fnext, 16);
-
-
-    /* g1(n) = f0(n) * K1  +  g0(n-1) */
-    gnext = ((fcurnt * (*pk++)) >> 15u) + gcurnt;
-    gnext = __SSAT(gnext, 16);
-
-    /* save f0(n) in state buffer */
-    *px++ = (q15_t) fcurnt;
-
-    /* f1(n) is saved in fcurnt            
-       for next stage processing */
-    fcurnt = fnext;
-
-    stageCnt = (numStages - 1u);
-
-    /* stage loop */
-    while(stageCnt > 0u)
-    {
-      /* read g1(n-1) from state buffer */
-      gcurnt = *px;
-
-      /* save g0(n-1) in state buffer */
-      *px++ = (q15_t) gnext;
-
-      /* Sample processing for K2, K3.... */
-      /* f2(n) = f1(n) +  K2 * g1(n-1) */
-      fnext = ((gcurnt * (*pk)) >> 15u) + fcurnt;
-      fnext = __SSAT(fnext, 16);
-
-      /* g2(n) = f1(n) * K2  +  g1(n-1) */
-      gnext = ((fcurnt * (*pk++)) >> 15u) + gcurnt;
-      gnext = __SSAT(gnext, 16);
-
-
-      /* f1(n) is saved in fcurnt            
-         for next stage processing */
-      fcurnt = fnext;
-
-      stageCnt--;
-
-    }
-
-    /* y(n) = fN(n) */
-    *pDst++ = __SSAT(fcurnt, 16);
-
-
-    blkCnt--;
-
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
- * @} end of FIR_Lattice group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q31.c
deleted file mode 100644
index c923721333..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q31.c
+++ /dev/null
@@ -1,348 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_lattice_q31.c    
-*    
-* Description:	Q31 FIR lattice filter processing function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_Lattice    
- * @{    
- */
-
-
-/**    
- * @brief Processing function for the Q31 FIR lattice filter.    
- * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.    
- * @param[in]  *pSrc     points to the block of input data.    
- * @param[out] *pDst     points to the block of output data    
- * @param[in]  blockSize number of samples to process.    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- * In order to avoid overflows the input signal must be scaled down by 2*log2(numStages) bits.    
- */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-void arm_fir_lattice_q31(
-  const arm_fir_lattice_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  q31_t *pState;                                 /* State pointer */
-  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q31_t *px;                                     /* temporary state pointer */
-  q31_t *pk;                                     /* temporary coefficient pointer */
-  q31_t fcurr1, fnext1, gcurr1 = 0, gnext1;      /* temporary variables for first sample in loop unrolling */
-  q31_t fcurr2, fnext2, gnext2;                  /* temporary variables for second sample in loop unrolling */
-  uint32_t numStages = S->numStages;             /* Length of the filter */
-  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
-  q31_t k;
-
-  pState = &S->pState[0];
-
-  blkCnt = blockSize >> 1u;
-
-  /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.        
-     a second loop below computes the remaining 1 sample. */
-  while(blkCnt > 0u)
-  {
-    /* f0(n) = x(n) */
-    fcurr1 = *pSrc++;
-
-    /* f0(n) = x(n) */
-    fcurr2 = *pSrc++;
-
-    /* Initialize coeff pointer */
-    pk = (pCoeffs);
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* read g0(n - 1) from state buffer */
-    gcurr1 = *px;
-
-    /* Read the reflection coefficient */
-    k = *pk++;
-
-    /* for sample 1 processing */
-    /* f1(n) = f0(n) +  K1 * g0(n-1) */
-    fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
-
-    /* g1(n) = f0(n) * K1  +  g0(n-1) */
-    gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
-    fnext1 = fcurr1 + (fnext1 << 1u);
-    gnext1 = gcurr1 + (gnext1 << 1u);
-
-    /* for sample 1 processing */
-    /* f1(n) = f0(n) +  K1 * g0(n-1) */
-    fnext2 = (q31_t) (((q63_t) fcurr1 * k) >> 32);
-
-    /* g1(n) = f0(n) * K1  +  g0(n-1) */
-    gnext2 = (q31_t) (((q63_t) fcurr2 * (k)) >> 32);
-    fnext2 = fcurr2 + (fnext2 << 1u);
-    gnext2 = fcurr1 + (gnext2 << 1u);
-
-    /* save g1(n) in state buffer */
-    *px++ = fcurr2;
-
-    /* f1(n) is saved in fcurr1        
-       for next stage processing */
-    fcurr1 = fnext1;
-    fcurr2 = fnext2;
-
-    stageCnt = (numStages - 1u);
-
-    /* stage loop */
-    while(stageCnt > 0u)
-    {
-
-      /* Read the reflection coefficient */
-      k = *pk++;
-
-      /* read g2(n) from state buffer */
-      gcurr1 = *px;
-
-      /* save g1(n) in state buffer */
-      *px++ = gnext2;
-
-      /* Sample processing for K2, K3.... */
-      /* f2(n) = f1(n) +  K2 * g1(n-1) */
-      fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
-      fnext2 = (q31_t) (((q63_t) gnext1 * k) >> 32);
-
-      fnext1 = fcurr1 + (fnext1 << 1u);
-      fnext2 = fcurr2 + (fnext2 << 1u);
-
-      /* g2(n) = f1(n) * K2  +  g1(n-1) */
-      gnext2 = (q31_t) (((q63_t) fcurr2 * (k)) >> 32);
-      gnext2 = gnext1 + (gnext2 << 1u);
-
-      /* g2(n) = f1(n) * K2  +  g1(n-1) */
-      gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
-      gnext1 = gcurr1 + (gnext1 << 1u);
-
-      /* f1(n) is saved in fcurr1        
-         for next stage processing */
-      fcurr1 = fnext1;
-      fcurr2 = fnext2;
-
-      stageCnt--;
-
-    }
-
-    /* y(n) = fN(n) */
-    *pDst++ = fcurr1;
-    *pDst++ = fcurr2;
-
-    blkCnt--;
-
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.        
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x2u;
-
-  while(blkCnt > 0u)
-  {
-    /* f0(n) = x(n) */
-    fcurr1 = *pSrc++;
-
-    /* Initialize coeff pointer */
-    pk = (pCoeffs);
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* read g0(n - 1) from state buffer */
-    gcurr1 = *px;
-
-    /* Read the reflection coefficient */
-    k = *pk++;
-
-    /* for sample 1 processing */
-    /* f1(n) = f0(n) +  K1 * g0(n-1) */
-    fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
-    fnext1 = fcurr1 + (fnext1 << 1u);
-
-    /* g1(n) = f0(n) * K1  +  g0(n-1) */
-    gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
-    gnext1 = gcurr1 + (gnext1 << 1u);
-
-    /* save g1(n) in state buffer */
-    *px++ = fcurr1;
-
-    /* f1(n) is saved in fcurr1        
-       for next stage processing */
-    fcurr1 = fnext1;
-
-    stageCnt = (numStages - 1u);
-
-    /* stage loop */
-    while(stageCnt > 0u)
-    {
-      /* Read the reflection coefficient */
-      k = *pk++;
-
-      /* read g2(n) from state buffer */
-      gcurr1 = *px;
-
-      /* save g1(n) in state buffer */
-      *px++ = gnext1;
-
-      /* Sample processing for K2, K3.... */
-      /* f2(n) = f1(n) +  K2 * g1(n-1) */
-      fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
-      fnext1 = fcurr1 + (fnext1 << 1u);
-
-      /* g2(n) = f1(n) * K2  +  g1(n-1) */
-      gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
-      gnext1 = gcurr1 + (gnext1 << 1u);
-
-      /* f1(n) is saved in fcurr1        
-         for next stage processing */
-      fcurr1 = fnext1;
-
-      stageCnt--;
-
-    }
-
-
-    /* y(n) = fN(n) */
-    *pDst++ = fcurr1;
-
-    blkCnt--;
-
-  }
-
-
-}
-
-
-#else
-
-/* Run the below code for Cortex-M0 */
-
-void arm_fir_lattice_q31(
-  const arm_fir_lattice_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  q31_t *pState;                                 /* State pointer */
-  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q31_t *px;                                     /* temporary state pointer */
-  q31_t *pk;                                     /* temporary coefficient pointer */
-  q31_t fcurr, fnext, gcurr, gnext;              /* temporary variables */
-  uint32_t numStages = S->numStages;             /* Length of the filter */
-  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
-
-  pState = &S->pState[0];
-
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* f0(n) = x(n) */
-    fcurr = *pSrc++;
-
-    /* Initialize coeff pointer */
-    pk = (pCoeffs);
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* read g0(n-1) from state buffer */
-    gcurr = *px;
-
-    /* for sample 1 processing */
-    /* f1(n) = f0(n) +  K1 * g0(n-1) */
-    fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr;
-    /* g1(n) = f0(n) * K1  +  g0(n-1) */
-    gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr;
-    /* save g1(n) in state buffer */
-    *px++ = fcurr;
-
-    /* f1(n) is saved in fcurr1            
-       for next stage processing */
-    fcurr = fnext;
-
-    stageCnt = (numStages - 1u);
-
-    /* stage loop */
-    while(stageCnt > 0u)
-    {
-      /* read g2(n) from state buffer */
-      gcurr = *px;
-
-      /* save g1(n) in state buffer */
-      *px++ = gnext;
-
-      /* Sample processing for K2, K3.... */
-      /* f2(n) = f1(n) +  K2 * g1(n-1) */
-      fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr;
-      /* g2(n) = f1(n) * K2  +  g1(n-1) */
-      gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr;
-
-      /* f1(n) is saved in fcurr1            
-         for next stage processing */
-      fcurr = fnext;
-
-      stageCnt--;
-
-    }
-
-    /* y(n) = fN(n) */
-    *pDst++ = fcurr;
-
-    blkCnt--;
-
-  }
-
-}
-
-#endif /*   #ifndef ARM_MATH_CM0 */
-
-
-/**    
- * @} end of FIR_Lattice group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q15.c
deleted file mode 100644
index ac3e2210c3..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q15.c
+++ /dev/null
@@ -1,689 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_q15.c    
-*    
-* Description:  Q15 FIR filter processing function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-* 	 incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**       
- * @ingroup groupFilters       
- */
-
-/**       
- * @addtogroup FIR       
- * @{       
- */
-
-/**       
- * @brief Processing function for the Q15 FIR filter.       
- * @param[in] *S points to an instance of the Q15 FIR structure.       
- * @param[in] *pSrc points to the block of input data.       
- * @param[out] *pDst points to the block of output data.       
- * @param[in]  blockSize number of samples to process per call.       
- * @return none.       
- *   
- *   
- * \par Restrictions   
- *  If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE   
- *	In this case input, output, state buffers should be aligned by 32-bit   
- *   
- * Scaling and Overflow Behavior:       
- * \par       
- * The function is implemented using a 64-bit internal accumulator.       
- * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.       
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.       
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.       
- * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.       
- * Lastly, the accumulator is saturated to yield a result in 1.15 format.       
- *       
- * \par       
- * Refer to the function arm_fir_fast_q15() for a faster but less precise implementation of this function.       
- */
-
-#ifndef ARM_MATH_CM0
-
-/* Run the below code for Cortex-M4 and Cortex-M3 */
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-
-void arm_fir_q15(
-  const arm_fir_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pState = S->pState;                     /* State pointer */
-  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q15_t *px1;                                    /* Temporary q15 pointer for state buffer */
-  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */
-  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold SIMD state and coefficient values */
-  q63_t acc0, acc1, acc2, acc3;                  /* Accumulators */
-  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */
-  uint32_t tapCnt, blkCnt;                       /* Loop counters */
-
-
-  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  /* Apply loop unrolling and compute 4 output values simultaneously.       
-   * The variables acc0 ... acc3 hold output values that are being computed:       
-   *       
-   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]       
-   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]       
-   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]       
-   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]       
-   */
-
-  blkCnt = blockSize >> 2;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.       
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* Copy four new input samples into the state buffer.       
-     ** Use 32-bit SIMD to move the 16-bit data.  Only requires two copies. */
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;
-
-    /* Set all accumulators to zero */
-    acc0 = 0;
-    acc1 = 0;
-    acc2 = 0;
-    acc3 = 0;
-
-    /* Initialize state pointer of type q15 */
-    px1 = pState;
-
-    /* Initialize coeff pointer of type q31 */
-    pb = pCoeffs;
-
-    /* Read the first two samples from the state buffer:  x[n-N], x[n-N-1] */
-    x0 = _SIMD32_OFFSET(px1);
-
-    /* Read the third and forth samples from the state buffer: x[n-N-1], x[n-N-2] */
-    x1 = _SIMD32_OFFSET(px1 + 1u);
-
-    px1 += 2u;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.       
-     ** Repeat until we've computed numTaps-4 coefficients. */
-    tapCnt = numTaps >> 2;
-
-    while(tapCnt > 0u)
-    {
-      /* Read the first two coefficients using SIMD:  b[N] and b[N-1] coefficients */
-      c0 = *__SIMD32(pb)++;
-
-      /* acc0 +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */
-      acc0 = __SMLALD(x0, c0, acc0);
-
-      /* acc1 +=  b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
-      acc1 = __SMLALD(x1, c0, acc1);
-
-      /* Read state x[n-N-2], x[n-N-3] */
-      x2 = _SIMD32_OFFSET(px1);
-
-      /* Read state x[n-N-3], x[n-N-4] */
-      x3 = _SIMD32_OFFSET(px1 + 1u);
-
-      /* acc2 +=  b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
-      acc2 = __SMLALD(x2, c0, acc2);
-
-      /* acc3 +=  b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
-      acc3 = __SMLALD(x3, c0, acc3);
-
-      /* Read coefficients b[N-2], b[N-3] */
-      c0 = *__SIMD32(pb)++;
-
-      /* acc0 +=  b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
-      acc0 = __SMLALD(x2, c0, acc0);
-
-      /* acc1 +=  b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
-      acc1 = __SMLALD(x3, c0, acc1);
-
-      /* Read state x[n-N-4], x[n-N-5] */
-      x0 = _SIMD32_OFFSET(px1 + 2u);
-
-      /* Read state x[n-N-5], x[n-N-6] */
-      x1 = _SIMD32_OFFSET(px1 + 3u);
-
-      /* acc2 +=  b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
-      acc2 = __SMLALD(x0, c0, acc2);
-
-      /* acc3 +=  b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
-      acc3 = __SMLALD(x1, c0, acc3);
-
-      px1 += 4u;
-
-      tapCnt--;
-
-    }
-
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps.       
-     ** This is always be 2 taps since the filter length is even. */
-    if((numTaps & 0x3u) != 0u)
-    {
-      /* Read 2 coefficients */
-      c0 = *__SIMD32(pb)++;
-
-      /* Fetch 4 state variables */
-      x2 = _SIMD32_OFFSET(px1);
-
-      x3 = _SIMD32_OFFSET(px1 + 1u);
-
-      /* Perform the multiply-accumulates */
-      acc0 = __SMLALD(x0, c0, acc0);
-
-      px1 += 2u;
-
-      acc1 = __SMLALD(x1, c0, acc1);
-      acc2 = __SMLALD(x2, c0, acc2);
-      acc3 = __SMLALD(x3, c0, acc3);
-    }
-
-    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.15 with saturation.       
-     ** Then store the 4 outputs in the destination buffer. */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    *__SIMD32(pDst)++ =
-      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
-    *__SIMD32(pDst)++ =
-      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
-
-#else
-
-    *__SIMD32(pDst)++ =
-      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
-    *__SIMD32(pDst)++ =
-      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */
-
-
-
-    /* Advance the state pointer by 4 to process the next group of 4 samples */
-    pState = pState + 4;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.       
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-  while(blkCnt > 0u)
-  {
-    /* Copy two samples into state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Set the accumulator to zero */
-    acc0 = 0;
-
-    /* Initialize state pointer of type q15 */
-    px1 = pState;
-
-    /* Initialize coeff pointer of type q31 */
-    pb = pCoeffs;
-
-    tapCnt = numTaps >> 1;
-
-    do
-    {
-
-      c0 = *__SIMD32(pb)++;
-      x0 = *__SIMD32(px1)++;
-
-      acc0 = __SMLALD(x0, c0, acc0);
-      tapCnt--;
-    }
-    while(tapCnt > 0u);
-
-    /* The result is in 2.30 format.  Convert to 1.15 with saturation.       
-     ** Then store the output in the destination buffer. */
-    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.       
-   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  /* Calculation of count for copying integer writes */
-  tapCnt = (numTaps - 1u) >> 2;
-
-  while(tapCnt > 0u)
-  {
-
-    /* Copy state values to start of state buffer */
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-
-    tapCnt--;
-
-  }
-
-  /* Calculation of count for remaining q15_t data */
-  tapCnt = (numTaps - 1u) % 0x4u;
-
-  /* copy remaining data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-}
-
-#else /* UNALIGNED_SUPPORT_DISABLE */
-
-void arm_fir_q15(
-  const arm_fir_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pState = S->pState;                     /* State pointer */
-  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q63_t acc0, acc1, acc2, acc3;                  /* Accumulators */
-  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */
-  q15_t *px;                                     /* Temporary q31 pointer for SIMD state buffer accesses */
-  q31_t x0, x1, x2, c0;                          /* Temporary variables to hold SIMD state and coefficient values */
-  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */
-  uint32_t tapCnt, blkCnt;                       /* Loop counters */
-
-
-  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  /* Apply loop unrolling and compute 4 output values simultaneously.      
-   * The variables acc0 ... acc3 hold output values that are being computed:      
-   *      
-   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]      
-   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]      
-   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]      
-   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]      
-   */
-
-  blkCnt = blockSize >> 2;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.      
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* Copy four new input samples into the state buffer.      
-     ** Use 32-bit SIMD to move the 16-bit data.  Only requires two copies. */
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-
-
-    /* Set all accumulators to zero */
-    acc0 = 0;
-    acc1 = 0;
-    acc2 = 0;
-    acc3 = 0;
-
-    /* Typecast q15_t pointer to q31_t pointer for state reading in q31_t */
-    px = pState;
-
-    /* Typecast q15_t pointer to q31_t pointer for coefficient reading in q31_t */
-    pb = pCoeffs;
-
-    /* Read the first two samples from the state buffer:  x[n-N], x[n-N-1] */
-    x0 = *__SIMD32(px)++;
-
-    /* Read the third and forth samples from the state buffer: x[n-N-2], x[n-N-3] */
-    x2 = *__SIMD32(px)++;
-
-    /* Loop over the number of taps.  Unroll by a factor of 4.      
-     ** Repeat until we've computed numTaps-(numTaps%4) coefficients. */
-    tapCnt = numTaps >> 2;
-
-    while(tapCnt > 0)
-    {
-      /* Read the first two coefficients using SIMD:  b[N] and b[N-1] coefficients */
-      c0 = *__SIMD32(pb)++;
-
-      /* acc0 +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */
-      acc0 = __SMLALD(x0, c0, acc0);
-
-      /* acc2 +=  b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
-      acc2 = __SMLALD(x2, c0, acc2);
-
-      /* pack  x[n-N-1] and x[n-N-2] */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x1 = __PKHBT(x2, x0, 0);
-#else
-      x1 = __PKHBT(x0, x2, 0);
-#endif
-
-      /* Read state x[n-N-4], x[n-N-5] */
-      x0 = _SIMD32_OFFSET(px);
-
-      /* acc1 +=  b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
-      acc1 = __SMLALDX(x1, c0, acc1);
-
-      /* pack  x[n-N-3] and x[n-N-4] */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x1 = __PKHBT(x0, x2, 0);
-#else
-      x1 = __PKHBT(x2, x0, 0);
-#endif
-
-      /* acc3 +=  b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
-      acc3 = __SMLALDX(x1, c0, acc3);
-
-      /* Read coefficients b[N-2], b[N-3] */
-      c0 = *__SIMD32(pb)++;
-
-      /* acc0 +=  b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
-      acc0 = __SMLALD(x2, c0, acc0);
-
-      /* Read state x[n-N-6], x[n-N-7] with offset */
-      x2 = _SIMD32_OFFSET(px + 2u);
-
-      /* acc2 +=  b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
-      acc2 = __SMLALD(x0, c0, acc2);
-
-      /* acc1 +=  b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
-      acc1 = __SMLALDX(x1, c0, acc1);
-
-      /* pack  x[n-N-5] and x[n-N-6] */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x1 = __PKHBT(x2, x0, 0);
-#else
-      x1 = __PKHBT(x0, x2, 0);
-#endif
-
-      /* acc3 +=  b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
-      acc3 = __SMLALDX(x1, c0, acc3);
-
-      /* Update state pointer for next state reading */
-      px += 4u;
-
-      /* Decrement tap count */
-      tapCnt--;
-
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps.       
-     ** This is always be 2 taps since the filter length is even. */
-    if((numTaps & 0x3u) != 0u)
-    {
-
-      /* Read last two coefficients */
-      c0 = *__SIMD32(pb)++;
-
-      /* Perform the multiply-accumulates */
-      acc0 = __SMLALD(x0, c0, acc0);
-      acc2 = __SMLALD(x2, c0, acc2);
-
-      /* pack state variables */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x1 = __PKHBT(x2, x0, 0);
-#else
-      x1 = __PKHBT(x0, x2, 0);
-#endif
-
-      /* Read last state variables */
-      x0 = *__SIMD32(px);
-
-      /* Perform the multiply-accumulates */
-      acc1 = __SMLALDX(x1, c0, acc1);
-
-      /* pack state variables */
-#ifndef ARM_MATH_BIG_ENDIAN
-      x1 = __PKHBT(x0, x2, 0);
-#else
-      x1 = __PKHBT(x2, x0, 0);
-#endif
-
-      /* Perform the multiply-accumulates */
-      acc3 = __SMLALDX(x1, c0, acc3);
-    }
-
-    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.15 with saturation.       
-     ** Then store the 4 outputs in the destination buffer. */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    *__SIMD32(pDst)++ =
-      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
-
-    *__SIMD32(pDst)++ =
-      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
-
-#else
-
-    *__SIMD32(pDst)++ =
-      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
-
-    *__SIMD32(pDst)++ =
-      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */
-
-    /* Advance the state pointer by 4 to process the next group of 4 samples */
-    pState = pState + 4;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.      
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-  while(blkCnt > 0u)
-  {
-    /* Copy two samples into state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Set the accumulator to zero */
-    acc0 = 0;
-
-    /* Use SIMD to hold states and coefficients */
-    px = pState;
-    pb = pCoeffs;
-
-    tapCnt = numTaps >> 1u;
-
-    do
-    {
-      acc0 += (q31_t) * px++ * *pb++;
-	  acc0 += (q31_t) * px++ * *pb++;
-      tapCnt--;
-    }
-    while(tapCnt > 0u);
-
-    /* The result is in 2.30 format.  Convert to 1.15 with saturation.      
-     ** Then store the output in the destination buffer. */
-    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.      
-   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.      
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  /* Calculation of count for copying integer writes */
-  tapCnt = (numTaps - 1u) >> 2;
-
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    tapCnt--;
-
-  }
-
-  /* Calculation of count for remaining q15_t data */
-  tapCnt = (numTaps - 1u) % 0x4u;
-
-  /* copy remaining data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-}
-
-
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
-#else /* ARM_MATH_CM0 */
-
-
-/* Run the below code for Cortex-M0 */
-
-void arm_fir_q15(
-  const arm_fir_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pState = S->pState;                     /* State pointer */
-  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
-
-
-
-  q15_t *px;                                     /* Temporary pointer for state buffer */
-  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */
-  q63_t acc;                                     /* Accumulator */
-  uint32_t numTaps = S->numTaps;                 /* Number of nTaps in the filter */
-  uint32_t tapCnt, blkCnt;                       /* Loop counters */
-
-  /* S->pState buffer contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  /* Initialize blkCnt with blockSize */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* Copy one sample at a time into state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Set the accumulator to zero */
-    acc = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize Coefficient pointer */
-    pb = pCoeffs;
-
-    tapCnt = numTaps;
-
-    /* Perform the multiply-accumulates */
-    do
-    {
-      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
-      acc += (q31_t) * px++ * *pb++;
-      tapCnt--;
-    } while(tapCnt > 0u);
-
-    /* The result is in 2.30 format.  Convert to 1.15         
-     ** Then store the output in the destination buffer. */
-    *pDst++ = (q15_t) __SSAT((acc >> 15u), 16);
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1;
-
-    /* Decrement the samples loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.         
-   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  /* Copy numTaps number of values */
-  tapCnt = (numTaps - 1u);
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-}
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-
-
-
-/**       
- * @} end of FIR group       
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q31.c
deleted file mode 100644
index 8113d7e274..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q31.c
+++ /dev/null
@@ -1,363 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_q31.c    
-*    
-* Description:	Q31 FIR filter processing function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-* 	 incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR    
- * @{    
- */
-
-/**    
- * @param[in] *S points to an instance of the Q31 FIR filter structure.    
- * @param[in] *pSrc points to the block of input data.    
- * @param[out] *pDst points to the block of output data.    
- * @param[in] blockSize number of samples to process per call.    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using an internal 64-bit accumulator.    
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
- * Thus, if the accumulator result overflows it wraps around rather than clip.    
- * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.    
- * After all multiply-accumulates are performed, the 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.  
- *    
- * \par    
- * Refer to the function arm_fir_fast_q31() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.    
- */
-
-void arm_fir_q31(
-  const arm_fir_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  q31_t *pState = S->pState;                     /* State pointer */
-  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t x0, x1, x2;                              /* Temporary variables to hold state */
-  q31_t c0;                                      /* Temporary variable to hold coefficient value */
-  q31_t *px;                                     /* Temporary pointer for state */
-  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
-  q63_t acc0, acc1, acc2;                        /* Accumulators */
-  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
-  uint32_t i, tapCnt, blkCnt, tapCntN3;          /* Loop counters */
-
-  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  /* Apply loop unrolling and compute 4 output values simultaneously.    
-   * The variables acc0 ... acc3 hold output values that are being computed:    
-   *    
-   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]    
-   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]    
-   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]    
-   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]    
-   */
-  blkCnt = blockSize / 3;
-  blockSize = blockSize - (3 * blkCnt);
-
-  tapCnt = numTaps / 3;
-  tapCntN3 = numTaps - (3 * tapCnt);
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* Copy three new input samples into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-
-    /* Set all accumulators to zero */
-    acc0 = 0;
-    acc1 = 0;
-    acc2 = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize coefficient pointer */
-    pb = pCoeffs;
-
-    /* Read the first two samples from the state buffer:    
-     *  x[n-numTaps], x[n-numTaps-1] */
-    x0 = *(px++);
-    x1 = *(px++);
-
-    /* Loop unrolling.  Process 3 taps at a time. */
-    i = tapCnt;
-
-    while(i > 0u)
-    {
-      /* Read the b[numTaps] coefficient */
-      c0 = *pb;
-
-      /* Read x[n-numTaps-2] sample */
-      x2 = *(px++);
-
-      /* Perform the multiply-accumulates */
-      acc0 += ((q63_t) x0 * c0);
-      acc1 += ((q63_t) x1 * c0);
-      acc2 += ((q63_t) x2 * c0);
-
-      /* Read the coefficient and state */
-      c0 = *(pb + 1u);
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulates */
-      acc0 += ((q63_t) x1 * c0);
-      acc1 += ((q63_t) x2 * c0);
-      acc2 += ((q63_t) x0 * c0);
-
-      /* Read the coefficient and state */
-      c0 = *(pb + 2u);
-      x1 = *(px++);
-
-      /* update coefficient pointer */
-      pb += 3u;
-
-      /* Perform the multiply-accumulates */
-      acc0 += ((q63_t) x2 * c0);
-      acc1 += ((q63_t) x0 * c0);
-      acc2 += ((q63_t) x1 * c0);
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* If the filter length is not a multiple of 3, compute the remaining filter taps */
-
-    i = tapCntN3;
-
-    while(i > 0u)
-    {
-      /* Read coefficients */
-      c0 = *(pb++);
-
-      /* Fetch 1 state variable */
-      x2 = *(px++);
-
-      /* Perform the multiply-accumulates */
-      acc0 += ((q63_t) x0 * c0);
-      acc1 += ((q63_t) x1 * c0);
-      acc2 += ((q63_t) x2 * c0);
-
-      /* Reuse the present sample states for next sample */
-      x0 = x1;
-      x1 = x2;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Advance the state pointer by 3 to process the next group of 3 samples */
-    pState = pState + 3;
-
-    /* The results in the 3 accumulators are in 2.30 format.  Convert to 1.31    
-     ** Then store the 3 outputs in the destination buffer. */
-    *pDst++ = (q31_t) (acc0 >> 31u);
-    *pDst++ = (q31_t) (acc1 >> 31u);
-    *pDst++ = (q31_t) (acc2 >> 31u);
-
-    /* Decrement the samples loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 3, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-
-  while(blockSize > 0u)
-  {
-    /* Copy one sample at a time into state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Set the accumulator to zero */
-    acc0 = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize Coefficient pointer */
-    pb = (pCoeffs);
-
-    i = numTaps;
-
-    /* Perform the multiply-accumulates */
-    do
-    {
-      acc0 += (q63_t) * (px++) * (*(pb++));
-      i--;
-    } while(i > 0u);
-
-    /* The result is in 2.62 format.  Convert to 1.31    
-     ** Then store the output in the destination buffer. */
-    *pDst++ = (q31_t) (acc0 >> 31u);
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1;
-
-    /* Decrement the samples loop counter */
-    blockSize--;
-  }
-
-  /* Processing is complete.    
-   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.    
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  tapCnt = (numTaps - 1u) >> 2u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-  /* Calculate remaining number of copies */
-  tapCnt = (numTaps - 1u) % 0x4u;
-
-  /* Copy the remaining q31_t data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-#else
-
-/* Run the below code for Cortex-M0 */
-
-  q31_t *px;                                     /* Temporary pointer for state */
-  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
-  q63_t acc;                                     /* Accumulator */
-  uint32_t numTaps = S->numTaps;                 /* Length of the filter */
-  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
-
-  /* S->pState buffer contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  /* Initialize blkCnt with blockSize */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* Copy one sample at a time into state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Set the accumulator to zero */
-    acc = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize Coefficient pointer */
-    pb = pCoeffs;
-
-    i = numTaps;
-
-    /* Perform the multiply-accumulates */
-    do
-    {
-      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
-      acc += (q63_t) * px++ * *pb++;
-      i--;
-    } while(i > 0u);
-
-    /* The result is in 2.62 format.  Convert to 1.31         
-     ** Then store the output in the destination buffer. */
-    *pDst++ = (q31_t) (acc >> 31u);
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1;
-
-    /* Decrement the samples loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.         
-   ** Now copy the last numTaps - 1 samples to the starting of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  /* Copy numTaps number of values */
-  tapCnt = numTaps - 1u;
-
-  /* Copy the data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-
-#endif /*  #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
- * @} end of FIR group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q7.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q7.c
deleted file mode 100644
index 97974992a0..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q7.c
+++ /dev/null
@@ -1,388 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_q7.c    
-*    
-* Description:  Q7 FIR filter processing function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-* 	 incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR    
- * @{    
- */
-
-/**    
- * @param[in]   *S points to an instance of the Q7 FIR filter structure.    
- * @param[in]   *pSrc points to the block of input data.    
- * @param[out]  *pDst points to the block of output data.    
- * @param[in]   blockSize number of samples to process per call.    
- * @return 	none.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using a 32-bit internal accumulator.    
- * Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result.    
- * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.    
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    
- * The accumulator is converted to 18.7 format by discarding the low 7 bits.    
- * Finally, the result is truncated to 1.7 format.    
- */
-
-void arm_fir_q7(
-  const arm_fir_instance_q7 * S,
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize)
-{
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q7_t *pState = S->pState;                      /* State pointer */
-  q7_t *pCoeffs = S->pCoeffs;                    /* Coefficient pointer */
-  q7_t *pStateCurnt;                             /* Points to the current sample of the state */
-  q7_t x0, x1, x2, x3;                           /* Temporary variables to hold state */
-  q7_t c0;                                       /* Temporary variable to hold coefficient value */
-  q7_t *px;                                      /* Temporary pointer for state */
-  q7_t *pb;                                      /* Temporary pointer for coefficient buffer */
-  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators */
-  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
-  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
-
-  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  /* Apply loop unrolling and compute 4 output values simultaneously.    
-   * The variables acc0 ... acc3 hold output values that are being computed:    
-   *    
-   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]    
-   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]    
-   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]    
-   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]    
-   */
-  blkCnt = blockSize >> 2;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* Copy four new input samples into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-    *pStateCurnt++ = *pSrc++;
-
-    /* Set all accumulators to zero */
-    acc0 = 0;
-    acc1 = 0;
-    acc2 = 0;
-    acc3 = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize coefficient pointer */
-    pb = pCoeffs;
-
-    /* Read the first three samples from the state buffer:    
-     *  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
-    x0 = *(px++);
-    x1 = *(px++);
-    x2 = *(px++);
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-    i = tapCnt;
-
-    while(i > 0u)
-    {
-      /* Read the b[numTaps] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-3] sample */
-      x3 = *(px++);
-
-      /* acc0 +=  b[numTaps] * x[n-numTaps] */
-      acc0 += ((q15_t) x0 * c0);
-
-      /* acc1 +=  b[numTaps] * x[n-numTaps-1] */
-      acc1 += ((q15_t) x1 * c0);
-
-      /* acc2 +=  b[numTaps] * x[n-numTaps-2] */
-      acc2 += ((q15_t) x2 * c0);
-
-      /* acc3 +=  b[numTaps] * x[n-numTaps-3] */
-      acc3 += ((q15_t) x3 * c0);
-
-      /* Read the b[numTaps-1] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-4] sample */
-      x0 = *(px++);
-
-      /* Perform the multiply-accumulates */
-      acc0 += ((q15_t) x1 * c0);
-      acc1 += ((q15_t) x2 * c0);
-      acc2 += ((q15_t) x3 * c0);
-      acc3 += ((q15_t) x0 * c0);
-
-      /* Read the b[numTaps-2] coefficient */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-5] sample */
-      x1 = *(px++);
-
-      /* Perform the multiply-accumulates */
-      acc0 += ((q15_t) x2 * c0);
-      acc1 += ((q15_t) x3 * c0);
-      acc2 += ((q15_t) x0 * c0);
-      acc3 += ((q15_t) x1 * c0);
-      /* Read the b[numTaps-3] coefficients */
-      c0 = *(pb++);
-
-      /* Read x[n-numTaps-6] sample */
-      x2 = *(px++);
-
-      /* Perform the multiply-accumulates */
-      acc0 += ((q15_t) x3 * c0);
-      acc1 += ((q15_t) x0 * c0);
-      acc2 += ((q15_t) x1 * c0);
-      acc3 += ((q15_t) x2 * c0);
-      i--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-
-    i = numTaps - (tapCnt * 4u);
-    while(i > 0u)
-    {
-      /* Read coefficients */
-      c0 = *(pb++);
-
-      /* Fetch 1 state variable */
-      x3 = *(px++);
-
-      /* Perform the multiply-accumulates */
-      acc0 += ((q15_t) x0 * c0);
-      acc1 += ((q15_t) x1 * c0);
-      acc2 += ((q15_t) x2 * c0);
-      acc3 += ((q15_t) x3 * c0);
-
-      /* Reuse the present sample states for next sample */
-      x0 = x1;
-      x1 = x2;
-      x2 = x3;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Advance the state pointer by 4 to process the next group of 4 samples */
-    pState = pState + 4;
-
-    /* The results in the 4 accumulators are in 2.62 format.  Convert to 1.31    
-     ** Then store the 4 outputs in the destination buffer. */
-    acc0 = __SSAT((acc0 >> 7u), 8);
-    *pDst++ = acc0;
-    acc1 = __SSAT((acc1 >> 7u), 8);
-    *pDst++ = acc1;
-    acc2 = __SSAT((acc2 >> 7u), 8);
-    *pDst++ = acc2;
-    acc3 = __SSAT((acc3 >> 7u), 8);
-    *pDst++ = acc3;
-
-    /* Decrement the samples loop counter */
-    blkCnt--;
-  }
-
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 4u;
-
-  while(blkCnt > 0u)
-  {
-    /* Copy one sample at a time into state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Set the accumulator to zero */
-    acc0 = 0;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize Coefficient pointer */
-    pb = (pCoeffs);
-
-    i = numTaps;
-
-    /* Perform the multiply-accumulates */
-    do
-    {
-      acc0 += (q15_t) * (px++) * (*(pb++));
-      i--;
-    } while(i > 0u);
-
-    /* The result is in 2.14 format.  Convert to 1.7    
-     ** Then store the output in the destination buffer. */
-    *pDst++ = __SSAT((acc0 >> 7u), 8);
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1;
-
-    /* Decrement the samples loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.    
-   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.    
-   ** This prepares the state buffer for the next function call. */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-  tapCnt = (numTaps - 1u) >> 2u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-  /* Calculate remaining number of copies */
-  tapCnt = (numTaps - 1u) % 0x4u;
-
-  /* Copy the remaining q31_t data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-#else
-
-/* Run the below code for Cortex-M0 */
-
-  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */
-  uint32_t i, blkCnt;                            /* Loop counters */
-  q7_t *pState = S->pState;                      /* State pointer */
-  q7_t *pCoeffs = S->pCoeffs;                    /* Coefficient pointer */
-  q7_t *px, *pb;                                 /* Temporary pointers to state and coeff */
-  q31_t acc = 0;                                 /* Accumlator */
-  q7_t *pStateCurnt;                             /* Points to the current sample of the state */
-
-
-  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = S->pState + (numTaps - 1u);
-
-  /* Initialize blkCnt with blockSize */
-  blkCnt = blockSize;
-
-  /* Perform filtering upto BlockSize - BlockSize%4  */
-  while(blkCnt > 0u)
-  {
-    /* Copy one sample at a time into state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Set accumulator to zero */
-    acc = 0;
-
-    /* Initialize state pointer of type q7 */
-    px = pState;
-
-    /* Initialize coeff pointer of type q7 */
-    pb = pCoeffs;
-
-
-    i = numTaps;
-
-    while(i > 0u)
-    {
-      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
-      acc += (q15_t) * px++ * *pb++;
-      i--;
-    }
-
-    /* Store the 1.7 format filter output in destination buffer */
-    *pDst++ = (q7_t) __SSAT((acc >> 7), 8);
-
-    /* Advance the state pointer by 1 to process the next sample */
-    pState = pState + 1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete.         
-   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.       
-   ** This prepares the state buffer for the next function call. */
-
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = S->pState;
-
-
-  /* Copy numTaps number of values */
-  i = (numTaps - 1u);
-
-  /* Copy q7_t data */
-  while(i > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    i--;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
- * @} end of FIR group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_f32.c
deleted file mode 100644
index 3b2dff4531..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_f32.c
+++ /dev/null
@@ -1,365 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_sparse_f32.c    
-*    
-* Description:	Floating-point sparse FIR filter processing function.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ------------------------------------------------------------------- */
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @defgroup FIR_Sparse Finite Impulse Response (FIR) Sparse Filters    
- *    
- * This group of functions implements sparse FIR filters.     
- * Sparse FIR filters are equivalent to standard FIR filters except that most of the coefficients are equal to zero.   
- * Sparse filters are used for simulating reflections in communications and audio applications.   
- *   
- * There are separate functions for Q7, Q15, Q31, and floating-point data types.    
- * The functions operate on blocks  of input and output data and each call to the function processes    
- * blockSize samples through the filter.  pSrc and    
- * pDst points to input and output arrays respectively containing blockSize values.    
- *    
- * \par Algorithm:    
- * The sparse filter instant structure contains an array of tap indices pTapDelay which specifies the locations of the non-zero coefficients.   
- * This is in addition to the coefficient array b.   
- * The implementation essentially skips the multiplications by zero and leads to an efficient realization.   
- * 
   
- *     y[n] = b[0] * x[n-pTapDelay[0]] + b[1] * x[n-pTapDelay[1]] + b[2] * x[n-pTapDelay[2]] + ...+ b[numTaps-1] * x[n-pTapDelay[numTaps-1]]    
- * 
    
- * \par    
- * \image html FIRSparse.gif "Sparse FIR filter.  b[n] represents the filter coefficients"   
- * \par    
- * pCoeffs points to a coefficient array of size numTaps;    
- * pTapDelay points to an array of nonzero indices and is also of size numTaps;   
- * pState points to a state array of size maxDelay + blockSize, where   
- * maxDelay is the largest offset value that is ever used in the pTapDelay array.   
- * Some of the processing functions also require temporary working buffers.   
- *   
- * \par Instance Structure    
- * The coefficients and state variables for a filter are stored together in an instance data structure.    
- * A separate instance structure must be defined for each filter.    
- * Coefficient and offset arrays may be shared among several instances while state variable arrays cannot be shared.    
- * There are separate instance structure declarations for each of the 4 supported data types.    
- *    
- * \par Initialization Functions    
- * There is also an associated initialization function for each data type.    
- * The initialization function performs the following operations:    
- * - Sets the values of the internal structure fields.    
- * - Zeros out the values in the state buffer.    
- *    
- * \par    
- * Use of the initialization function is optional.    
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
- * To place an instance structure into a const data section, the instance structure must be manually initialized.    
- * Set the values in the state buffer to zeros before static initialization.    
- * The code below statically initializes each of the 4 different data type filter instance structures    
- * 
    
- *arm_fir_sparse_instance_f32 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};    
- *arm_fir_sparse_instance_q31 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};    
- *arm_fir_sparse_instance_q15 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};    
- *arm_fir_sparse_instance_q7 S =  {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};    
- * 
    
- * \par    
- *    
- * \par Fixed-Point Behavior    
- * Care must be taken when using the fixed-point versions of the sparse FIR filter functions.    
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.    
- * Refer to the function specific documentation below for usage guidelines.    
- */
-
-/**    
- * @addtogroup FIR_Sparse    
- * @{    
- */
-
-/**   
- * @brief Processing function for the floating-point sparse FIR filter.   
- * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.   
- * @param[in]  *pSrc       points to the block of input data.   
- * @param[out] *pDst       points to the block of output data   
- * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.   
- * @param[in]  blockSize   number of input samples to process per call.   
- * @return none.   
- */
-
-void arm_fir_sparse_f32(
-  arm_fir_sparse_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  float32_t * pScratchIn,
-  uint32_t blockSize)
-{
-
-  float32_t *pState = S->pState;                 /* State pointer */
-  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
-  float32_t *px;                                 /* Scratch buffer pointer */
-  float32_t *py = pState;                        /* Temporary pointers for state buffer */
-  float32_t *pb = pScratchIn;                    /* Temporary pointers for scratch buffer */
-  float32_t *pOut;                               /* Destination pointer */
-  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
-  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
-  uint16_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter  */
-  int32_t readIndex;                             /* Read index of the state buffer */
-  uint32_t tapCnt, blkCnt;                       /* loop counters */
-  float32_t coeff = *pCoeffs++;                  /* Read the first coefficient value */
-
-
-
-  /* BlockSize of Input samples are copied into the state buffer */
-  /* StateIndex points to the starting position to write in the state buffer */
-  arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1,
-                        (int32_t *) pSrc, 1, blockSize);
-
-
-  /* Read Index, from where the state buffer should be read, is calculated. */
-  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
-
-  /* Wraparound of readIndex */
-  if(readIndex < 0)
-  {
-    readIndex += (int32_t) delaySize;
-  }
-
-  /* Working pointer for state buffer is updated */
-  py = pState;
-
-  /* blockSize samples are read from the state buffer */
-  arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
-                       (int32_t *) pb, (int32_t *) pb, blockSize, 1,
-                       blockSize);
-
-  /* Working pointer for the scratch buffer */
-  px = pb;
-
-  /* Working pointer for destination buffer */
-  pOut = pDst;
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /* Loop over the blockSize. Unroll by a factor of 4.    
-   * Compute 4 Multiplications at a time. */
-  blkCnt = blockSize >> 2u;
-
-  while(blkCnt > 0u)
-  {
-    /* Perform Multiplications and store in destination buffer */
-    *pOut++ = *px++ * coeff;
-    *pOut++ = *px++ * coeff;
-    *pOut++ = *px++ * coeff;
-    *pOut++ = *px++ * coeff;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4,    
-   * compute the remaining samples */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* Perform Multiplications and store in destination buffer */
-    *pOut++ = *px++ * coeff;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Load the coefficient value and    
-   * increment the coefficient buffer for the next set of state values */
-  coeff = *pCoeffs++;
-
-  /* Read Index, from where the state buffer should be read, is calculated. */
-  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
-
-  /* Wraparound of readIndex */
-  if(readIndex < 0)
-  {
-    readIndex += (int32_t) delaySize;
-  }
-
-  /* Loop over the number of taps. */
-  tapCnt = (uint32_t) numTaps - 1u;
-
-  while(tapCnt > 0u)
-  {
-
-    /* Working pointer for state buffer is updated */
-    py = pState;
-
-    /* blockSize samples are read from the state buffer */
-    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
-                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
-                         blockSize);
-
-    /* Working pointer for the scratch buffer */
-    px = pb;
-
-    /* Working pointer for destination buffer */
-    pOut = pDst;
-
-    /* Loop over the blockSize. Unroll by a factor of 4.    
-     * Compute 4 MACS at a time. */
-    blkCnt = blockSize >> 2u;
-
-    while(blkCnt > 0u)
-    {
-      /* Perform Multiply-Accumulate */
-      *pOut++ += *px++ * coeff;
-      *pOut++ += *px++ * coeff;
-      *pOut++ += *px++ * coeff;
-      *pOut++ += *px++ * coeff;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize is not a multiple of 4,    
-     * compute the remaining samples */
-    blkCnt = blockSize % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Perform Multiply-Accumulate */
-      *pOut++ += *px++ * coeff;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* Load the coefficient value and    
-     * increment the coefficient buffer for the next set of state values */
-    coeff = *pCoeffs++;
-
-    /* Read Index, from where the state buffer should be read, is calculated. */
-    readIndex = ((int32_t) S->stateIndex -
-                 (int32_t) blockSize) - *pTapDelay++;
-
-    /* Wraparound of readIndex */
-    if(readIndex < 0)
-    {
-      readIndex += (int32_t) delaySize;
-    }
-
-    /* Decrement the tap loop counter */
-    tapCnt--;
-  }
-
-#else
-
-/* Run the below code for Cortex-M0 */
-
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* Perform Multiplications and store in destination buffer */
-    *pOut++ = *px++ * coeff;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Load the coefficient value and           
-   * increment the coefficient buffer for the next set of state values */
-  coeff = *pCoeffs++;
-
-  /* Read Index, from where the state buffer should be read, is calculated. */
-  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
-
-  /* Wraparound of readIndex */
-  if(readIndex < 0)
-  {
-    readIndex += (int32_t) delaySize;
-  }
-
-  /* Loop over the number of taps. */
-  tapCnt = (uint32_t) numTaps - 1u;
-
-  while(tapCnt > 0u)
-  {
-
-    /* Working pointer for state buffer is updated */
-    py = pState;
-
-    /* blockSize samples are read from the state buffer */
-    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
-                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
-                         blockSize);
-
-    /* Working pointer for the scratch buffer */
-    px = pb;
-
-    /* Working pointer for destination buffer */
-    pOut = pDst;
-
-    blkCnt = blockSize;
-
-    while(blkCnt > 0u)
-    {
-      /* Perform Multiply-Accumulate */
-      *pOut++ += *px++ * coeff;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* Load the coefficient value and           
-     * increment the coefficient buffer for the next set of state values */
-    coeff = *pCoeffs++;
-
-    /* Read Index, from where the state buffer should be read, is calculated. */
-    readIndex =
-      ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
-
-    /* Wraparound of readIndex */
-    if(readIndex < 0)
-    {
-      readIndex += (int32_t) delaySize;
-    }
-
-    /* Decrement the tap loop counter */
-    tapCnt--;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0        */
-
-}
-
-/**    
- * @} end of FIR_Sparse group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_f32.c
deleted file mode 100644
index cc9cb53f76..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_f32.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_sparse_init_f32.c    
-*    
-* Description:	Floating-point sparse FIR filter initialization function.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_Sparse    
- * @{    
- */
-
-/**   
- * @brief  Initialization function for the floating-point sparse FIR filter.   
- * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.   
- * @param[in]     numTaps    number of nonzero coefficients in the filter.   
- * @param[in]     *pCoeffs   points to the array of filter coefficients.   
- * @param[in]     *pState    points to the state buffer.   
- * @param[in]     *pTapDelay points to the array of offset times.   
- * @param[in]     maxDelay   maximum offset time supported.   
- * @param[in]     blockSize  number of samples that will be processed per block.   
- * @return none   
- *    
- * Description:    
- * \par    
- * pCoeffs holds the filter coefficients and has length numTaps.    
- * pState holds the filter's state variables and must be of length    
- * maxDelay + blockSize, where maxDelay    
- * is the maximum number of delay line values.    
- * blockSize is the    
- * number of samples processed by the arm_fir_sparse_f32() function.    
- */
-
-void arm_fir_sparse_init_f32(
-  arm_fir_sparse_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize)
-{
-  /* Assign filter taps */
-  S->numTaps = numTaps;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Assign TapDelay pointer */
-  S->pTapDelay = pTapDelay;
-
-  /* Assign MaxDelay */
-  S->maxDelay = maxDelay;
-
-  /* reset the stateIndex to 0 */
-  S->stateIndex = 0u;
-
-  /* Clear state buffer and size is always maxDelay + blockSize */
-  memset(pState, 0, (maxDelay + blockSize) * sizeof(float32_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-}
-
-/**    
- * @} end of FIR_Sparse group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q15.c
deleted file mode 100644
index ef25875281..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q15.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_sparse_init_q15.c    
-*    
-* Description:	Q15 sparse FIR filter initialization function.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_Sparse    
- * @{    
- */
-
-/**   
- * @brief  Initialization function for the Q15 sparse FIR filter.   
- * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.   
- * @param[in]     numTaps    number of nonzero coefficients in the filter.   
- * @param[in]     *pCoeffs   points to the array of filter coefficients.   
- * @param[in]     *pState    points to the state buffer.   
- * @param[in]     *pTapDelay points to the array of offset times.   
- * @param[in]     maxDelay   maximum offset time supported.   
- * @param[in]     blockSize  number of samples that will be processed per block.   
- * @return none   
- *    
- * Description:    
- * \par    
- * pCoeffs holds the filter coefficients and has length numTaps.    
- * pState holds the filter's state variables and must be of length    
- * maxDelay + blockSize, where maxDelay    
- * is the maximum number of delay line values.    
- * blockSize is the    
- * number of words processed by arm_fir_sparse_q15() function.    
- */
-
-void arm_fir_sparse_init_q15(
-  arm_fir_sparse_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize)
-{
-  /* Assign filter taps */
-  S->numTaps = numTaps;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Assign TapDelay pointer */
-  S->pTapDelay = pTapDelay;
-
-  /* Assign MaxDelay */
-  S->maxDelay = maxDelay;
-
-  /* reset the stateIndex to 0 */
-  S->stateIndex = 0u;
-
-  /* Clear state buffer and size is always maxDelay + blockSize */
-  memset(pState, 0, (maxDelay + blockSize) * sizeof(q15_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-}
-
-/**    
- * @} end of FIR_Sparse group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q31.c
deleted file mode 100644
index abad5b85d5..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q31.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_sparse_init_q31.c    
-*    
-* Description:	Q31 sparse FIR filter initialization function.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_Sparse    
- * @{    
- */
-
-/**   
- * @brief  Initialization function for the Q31 sparse FIR filter.   
- * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.   
- * @param[in]     numTaps    number of nonzero coefficients in the filter.   
- * @param[in]     *pCoeffs   points to the array of filter coefficients.   
- * @param[in]     *pState    points to the state buffer.   
- * @param[in]     *pTapDelay points to the array of offset times.   
- * @param[in]     maxDelay   maximum offset time supported.   
- * @param[in]     blockSize  number of samples that will be processed per block.   
- * @return none   
- *    
- * Description:    
- * \par    
- * pCoeffs holds the filter coefficients and has length numTaps.    
- * pState holds the filter's state variables and must be of length    
- * maxDelay + blockSize, where maxDelay    
- * is the maximum number of delay line values.    
- * blockSize is the number of words processed by arm_fir_sparse_q31() function.    
- */
-
-void arm_fir_sparse_init_q31(
-  arm_fir_sparse_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize)
-{
-  /* Assign filter taps */
-  S->numTaps = numTaps;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Assign TapDelay pointer */
-  S->pTapDelay = pTapDelay;
-
-  /* Assign MaxDelay */
-  S->maxDelay = maxDelay;
-
-  /* reset the stateIndex to 0 */
-  S->stateIndex = 0u;
-
-  /* Clear state buffer and size is always maxDelay + blockSize */
-  memset(pState, 0, (maxDelay + blockSize) * sizeof(q31_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-}
-
-/**    
- * @} end of FIR_Sparse group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q7.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q7.c
deleted file mode 100644
index 9fb5c564d5..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q7.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_fir_sparse_init_q7.c    
-*    
-* Description:	Q7 sparse FIR filter initialization function.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_Sparse    
- * @{    
- */
-
-/**   
- * @brief  Initialization function for the Q7 sparse FIR filter.   
- * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.   
- * @param[in]     numTaps    number of nonzero coefficients in the filter.   
- * @param[in]     *pCoeffs   points to the array of filter coefficients.   
- * @param[in]     *pState    points to the state buffer.   
- * @param[in]     *pTapDelay points to the array of offset times.   
- * @param[in]     maxDelay   maximum offset time supported.   
- * @param[in]     blockSize  number of samples that will be processed per block.   
- * @return none   
- *    
- * Description:    
- * \par    
- * pCoeffs holds the filter coefficients and has length numTaps.    
- * pState holds the filter's state variables and must be of length    
- * maxDelay + blockSize, where maxDelay    
- * is the maximum number of delay line values.    
- * blockSize is the    
- * number of samples processed by the arm_fir_sparse_q7() function.    
- */
-
-void arm_fir_sparse_init_q7(
-  arm_fir_sparse_instance_q7 * S,
-  uint16_t numTaps,
-  q7_t * pCoeffs,
-  q7_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize)
-{
-  /* Assign filter taps */
-  S->numTaps = numTaps;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Assign TapDelay pointer */
-  S->pTapDelay = pTapDelay;
-
-  /* Assign MaxDelay */
-  S->maxDelay = maxDelay;
-
-  /* reset the stateIndex to 0 */
-  S->stateIndex = 0u;
-
-  /* Clear state buffer and size is always maxDelay + blockSize */
-  memset(pState, 0, (maxDelay + blockSize) * sizeof(q7_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-}
-
-/**    
- * @} end of FIR_Sparse group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q15.c
deleted file mode 100644
index 62e7afecbb..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q15.c
+++ /dev/null
@@ -1,406 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_sparse_q15.c    
-*    
-* Description:	Q15 sparse FIR filter processing function.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ------------------------------------------------------------------- */
-#include "arm_math.h"
-
-/**    
- * @addtogroup FIR_Sparse    
- * @{    
- */
-
-/**   
- * @brief Processing function for the Q15 sparse FIR filter.   
- * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.   
- * @param[in]  *pSrc        points to the block of input data.   
- * @param[out] *pDst        points to the block of output data   
- * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.   
- * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.   
- * @param[in]  blockSize    number of input samples to process per call.   
- * @return none.   
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using an internal 32-bit accumulator.   
- * The 1.15 x 1.15 multiplications yield a 2.30 result and these are added to a 2.30 accumulator.   
- * Thus the full precision of the multiplications is maintained but there is only a single guard bit in the accumulator.   
- * If the accumulator result overflows it will wrap around rather than saturate.   
- * After all multiply-accumulates are performed, the 2.30 accumulator is truncated to 2.15 format and then saturated to 1.15 format.    
- * In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits.   
- */
-
-
-void arm_fir_sparse_q15(
-  arm_fir_sparse_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  q15_t * pScratchIn,
-  q31_t * pScratchOut,
-  uint32_t blockSize)
-{
-
-  q15_t *pState = S->pState;                     /* State pointer */
-  q15_t *pIn = pSrc;                             /* Working pointer for input */
-  q15_t *pOut = pDst;                            /* Working pointer for output */
-  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q15_t *px;                                     /* Temporary pointers for scratch buffer */
-  q15_t *pb = pScratchIn;                        /* Temporary pointers for scratch buffer */
-  q15_t *py = pState;                            /* Temporary pointers for state buffer */
-  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
-  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
-  uint16_t numTaps = S->numTaps;                 /* Filter order */
-  int32_t readIndex;                             /* Read index of the state buffer */
-  uint32_t tapCnt, blkCnt;                       /* loop counters */
-  q15_t coeff = *pCoeffs++;                      /* Read the first coefficient value */
-  q31_t *pScr2 = pScratchOut;                    /* Working pointer for pScratchOut */
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t in1, in2;                                /* Temporary variables */
-
-
-  /* BlockSize of Input samples are copied into the state buffer */
-  /* StateIndex points to the starting position to write in the state buffer */
-  arm_circularWrite_q15(py, delaySize, &S->stateIndex, 1, pIn, 1, blockSize);
-
-  /* Loop over the number of taps. */
-  tapCnt = numTaps;
-
-  /* Read Index, from where the state buffer should be read, is calculated. */
-  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
-
-  /* Wraparound of readIndex */
-  if(readIndex < 0)
-  {
-    readIndex += (int32_t) delaySize;
-  }
-
-  /* Working pointer for state buffer is updated */
-  py = pState;
-
-  /* blockSize samples are read from the state buffer */
-  arm_circularRead_q15(py, delaySize, &readIndex, 1,
-                       pb, pb, blockSize, 1, blockSize);
-
-  /* Working pointer for the scratch buffer of state values */
-  px = pb;
-
-  /* Working pointer for scratch buffer of output values */
-  pScratchOut = pScr2;
-
-  /* Loop over the blockSize. Unroll by a factor of 4.    
-   * Compute 4 multiplications at a time. */
-  blkCnt = blockSize >> 2;
-
-  while(blkCnt > 0u)
-  {
-    /* Perform multiplication and store in the scratch buffer */
-    *pScratchOut++ = ((q31_t) * px++ * coeff);
-    *pScratchOut++ = ((q31_t) * px++ * coeff);
-    *pScratchOut++ = ((q31_t) * px++ * coeff);
-    *pScratchOut++ = ((q31_t) * px++ * coeff);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4,    
-   * compute the remaining samples */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* Perform multiplication and store in the scratch buffer */
-    *pScratchOut++ = ((q31_t) * px++ * coeff);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Load the coefficient value and    
-   * increment the coefficient buffer for the next set of state values */
-  coeff = *pCoeffs++;
-
-  /* Read Index, from where the state buffer should be read, is calculated. */
-  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
-
-  /* Wraparound of readIndex */
-  if(readIndex < 0)
-  {
-    readIndex += (int32_t) delaySize;
-  }
-
-  /* Loop over the number of taps. */
-  tapCnt = (uint32_t) numTaps - 1u;
-
-  while(tapCnt > 0u)
-  {
-    /* Working pointer for state buffer is updated */
-    py = pState;
-
-    /* blockSize samples are read from the state buffer */
-    arm_circularRead_q15(py, delaySize, &readIndex, 1,
-                         pb, pb, blockSize, 1, blockSize);
-
-    /* Working pointer for the scratch buffer of state values */
-    px = pb;
-
-    /* Working pointer for scratch buffer of output values */
-    pScratchOut = pScr2;
-
-    /* Loop over the blockSize. Unroll by a factor of 4.    
-     * Compute 4 MACS at a time. */
-    blkCnt = blockSize >> 2;
-
-    while(blkCnt > 0u)
-    {
-      /* Perform Multiply-Accumulate */
-      *pScratchOut++ += (q31_t) * px++ * coeff;
-      *pScratchOut++ += (q31_t) * px++ * coeff;
-      *pScratchOut++ += (q31_t) * px++ * coeff;
-      *pScratchOut++ += (q31_t) * px++ * coeff;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize is not a multiple of 4,    
-     * compute the remaining samples */
-    blkCnt = blockSize % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Perform Multiply-Accumulate */
-      *pScratchOut++ += (q31_t) * px++ * coeff;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* Load the coefficient value and    
-     * increment the coefficient buffer for the next set of state values */
-    coeff = *pCoeffs++;
-
-    /* Read Index, from where the state buffer should be read, is calculated. */
-    readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
-
-    /* Wraparound of readIndex */
-    if(readIndex < 0)
-    {
-      readIndex += (int32_t) delaySize;
-    }
-
-    /* Decrement the tap loop counter */
-    tapCnt--;
-  }
-
-  /* All the output values are in pScratchOut buffer.    
-     Convert them into 1.15 format, saturate and store in the destination buffer. */
-  /* Loop over the blockSize. */
-  blkCnt = blockSize >> 2;
-
-  while(blkCnt > 0u)
-  {
-    in1 = *pScr2++;
-    in2 = *pScr2++;
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-    *__SIMD32(pOut)++ =
-      __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16),
-              16);
-
-#else
-    *__SIMD32(pOut)++ =
-      __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16),
-              16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-    in1 = *pScr2++;
-
-    in2 = *pScr2++;
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-    *__SIMD32(pOut)++ =
-      __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16),
-              16);
-
-#else
-
-    *__SIMD32(pOut)++ =
-      __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16),
-              16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-
-    blkCnt--;
-
-  }
-
-  /* If the blockSize is not a multiple of 4,    
-     remaining samples are processed in the below loop */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16);
-    blkCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* BlockSize of Input samples are copied into the state buffer */
-  /* StateIndex points to the starting position to write in the state buffer */
-  arm_circularWrite_q15(py, delaySize, &S->stateIndex, 1, pIn, 1, blockSize);
-
-  /* Loop over the number of taps. */
-  tapCnt = numTaps;
-
-  /* Read Index, from where the state buffer should be read, is calculated. */
-  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
-
-  /* Wraparound of readIndex */
-  if(readIndex < 0)
-  {
-    readIndex += (int32_t) delaySize;
-  }
-
-  /* Working pointer for state buffer is updated */
-  py = pState;
-
-  /* blockSize samples are read from the state buffer */
-  arm_circularRead_q15(py, delaySize, &readIndex, 1,
-                       pb, pb, blockSize, 1, blockSize);
-
-  /* Working pointer for the scratch buffer of state values */
-  px = pb;
-
-  /* Working pointer for scratch buffer of output values */
-  pScratchOut = pScr2;
-
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* Perform multiplication and store in the scratch buffer */
-    *pScratchOut++ = ((q31_t) * px++ * coeff);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Load the coefficient value and           
-   * increment the coefficient buffer for the next set of state values */
-  coeff = *pCoeffs++;
-
-  /* Read Index, from where the state buffer should be read, is calculated. */
-  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
-
-  /* Wraparound of readIndex */
-  if(readIndex < 0)
-  {
-    readIndex += (int32_t) delaySize;
-  }
-
-  /* Loop over the number of taps. */
-  tapCnt = (uint32_t) numTaps - 1u;
-
-  while(tapCnt > 0u)
-  {
-    /* Working pointer for state buffer is updated */
-    py = pState;
-
-    /* blockSize samples are read from the state buffer */
-    arm_circularRead_q15(py, delaySize, &readIndex, 1,
-                         pb, pb, blockSize, 1, blockSize);
-
-    /* Working pointer for the scratch buffer of state values */
-    px = pb;
-
-    /* Working pointer for scratch buffer of output values */
-    pScratchOut = pScr2;
-
-    blkCnt = blockSize;
-
-    while(blkCnt > 0u)
-    {
-      /* Perform Multiply-Accumulate */
-      *pScratchOut++ += (q31_t) * px++ * coeff;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* Load the coefficient value and           
-     * increment the coefficient buffer for the next set of state values */
-    coeff = *pCoeffs++;
-
-    /* Read Index, from where the state buffer should be read, is calculated. */
-    readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
-
-    /* Wraparound of readIndex */
-    if(readIndex < 0)
-    {
-      readIndex += (int32_t) delaySize;
-    }
-
-    /* Decrement the tap loop counter */
-    tapCnt--;
-  }
-
-  /* All the output values are in pScratchOut buffer.       
-     Convert them into 1.15 format, saturate and store in the destination buffer. */
-  /* Loop over the blockSize. */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16);
-    blkCnt--;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
- * @} end of FIR_Sparse group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q31.c
deleted file mode 100644
index 9f02312501..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q31.c
+++ /dev/null
@@ -1,370 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_sparse_q31.c    
-*    
-* Description:	Q31 sparse FIR filter processing function.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ------------------------------------------------------------------- */
-#include "arm_math.h"
-
-
-/**    
- * @addtogroup FIR_Sparse    
- * @{    
- */
-
-/**   
- * @brief Processing function for the Q31 sparse FIR filter.   
- * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.   
- * @param[in]  *pSrc       points to the block of input data.   
- * @param[out] *pDst       points to the block of output data   
- * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.   
- * @param[in]  blockSize   number of input samples to process per call.   
- * @return none.   
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using an internal 32-bit accumulator.   
- * The 1.31 x 1.31 multiplications are truncated to 2.30 format.   
- * This leads to loss of precision on the intermediate multiplications and provides only a single guard bit.    
- * If the accumulator result overflows, it wraps around rather than saturate.   
- * In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits.   
- */
-
-void arm_fir_sparse_q31(
-  arm_fir_sparse_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  q31_t * pScratchIn,
-  uint32_t blockSize)
-{
-
-  q31_t *pState = S->pState;                     /* State pointer */
-  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q31_t *px;                                     /* Scratch buffer pointer */
-  q31_t *py = pState;                            /* Temporary pointers for state buffer */
-  q31_t *pb = pScratchIn;                        /* Temporary pointers for scratch buffer */
-  q31_t *pOut;                                   /* Destination pointer */
-  q63_t out;                                     /* Temporary output variable */
-  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
-  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
-  uint16_t numTaps = S->numTaps;                 /* Filter order */
-  int32_t readIndex;                             /* Read index of the state buffer */
-  uint32_t tapCnt, blkCnt;                       /* loop counters */
-  q31_t coeff = *pCoeffs++;                      /* Read the first coefficient value */
-  q31_t in;
-
-
-  /* BlockSize of Input samples are copied into the state buffer */
-  /* StateIndex points to the starting position to write in the state buffer */
-  arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1,
-                        (int32_t *) pSrc, 1, blockSize);
-
-  /* Read Index, from where the state buffer should be read, is calculated. */
-  readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
-
-  /* Wraparound of readIndex */
-  if(readIndex < 0)
-  {
-    readIndex += (int32_t) delaySize;
-  }
-
-  /* Working pointer for state buffer is updated */
-  py = pState;
-
-  /* blockSize samples are read from the state buffer */
-  arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
-                       (int32_t *) pb, (int32_t *) pb, blockSize, 1,
-                       blockSize);
-
-  /* Working pointer for the scratch buffer of state values */
-  px = pb;
-
-  /* Working pointer for scratch buffer of output values */
-  pOut = pDst;
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /* Loop over the blockSize. Unroll by a factor of 4.    
-   * Compute 4 Multiplications at a time. */
-  blkCnt = blockSize >> 2;
-
-  while(blkCnt > 0u)
-  {
-    /* Perform Multiplications and store in the destination buffer */
-    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
-    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
-    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
-    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4,    
-   * compute the remaining samples */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* Perform Multiplications and store in the destination buffer */
-    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Load the coefficient value and    
-   * increment the coefficient buffer for the next set of state values */
-  coeff = *pCoeffs++;
-
-  /* Read Index, from where the state buffer should be read, is calculated. */
-  readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
-
-  /* Wraparound of readIndex */
-  if(readIndex < 0)
-  {
-    readIndex += (int32_t) delaySize;
-  }
-
-  /* Loop over the number of taps. */
-  tapCnt = (uint32_t) numTaps - 1u;
-
-  while(tapCnt > 0u)
-  {
-    /* Working pointer for state buffer is updated */
-    py = pState;
-
-    /* blockSize samples are read from the state buffer */
-    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
-                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
-                         blockSize);
-
-    /* Working pointer for the scratch buffer of state values */
-    px = pb;
-
-    /* Working pointer for scratch buffer of output values */
-    pOut = pDst;
-
-    /* Loop over the blockSize. Unroll by a factor of 4.    
-     * Compute 4 MACS at a time. */
-    blkCnt = blockSize >> 2;
-
-    while(blkCnt > 0u)
-    {
-      out = *pOut;
-      out += ((q63_t) * px++ * coeff) >> 32;
-      *pOut++ = (q31_t) (out);
-
-      out = *pOut;
-      out += ((q63_t) * px++ * coeff) >> 32;
-      *pOut++ = (q31_t) (out);
-
-      out = *pOut;
-      out += ((q63_t) * px++ * coeff) >> 32;
-      *pOut++ = (q31_t) (out);
-
-      out = *pOut;
-      out += ((q63_t) * px++ * coeff) >> 32;
-      *pOut++ = (q31_t) (out);
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize is not a multiple of 4,    
-     * compute the remaining samples */
-    blkCnt = blockSize % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Perform Multiply-Accumulate */
-      out = *pOut;
-      out += ((q63_t) * px++ * coeff) >> 32;
-      *pOut++ = (q31_t) (out);
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* Load the coefficient value and    
-     * increment the coefficient buffer for the next set of state values */
-    coeff = *pCoeffs++;
-
-    /* Read Index, from where the state buffer should be read, is calculated. */
-    readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
-
-    /* Wraparound of readIndex */
-    if(readIndex < 0)
-    {
-      readIndex += (int32_t) delaySize;
-    }
-
-    /* Decrement the tap loop counter */
-    tapCnt--;
-  }
-
-  /* Working output pointer is updated */
-  pOut = pDst;
-
-  /* Output is converted into 1.31 format. */
-  /* Loop over the blockSize. Unroll by a factor of 4.    
-   * process 4 output samples at a time. */
-  blkCnt = blockSize >> 2;
-
-  while(blkCnt > 0u)
-  {
-    in = *pOut << 1;
-    *pOut++ = in;
-    in = *pOut << 1;
-    *pOut++ = in;
-    in = *pOut << 1;
-    *pOut++ = in;
-    in = *pOut << 1;
-    *pOut++ = in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4,    
-   * process the remaining output samples */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    in = *pOut << 1;
-    *pOut++ = in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* Perform Multiplications and store in the destination buffer */
-    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Load the coefficient value and           
-   * increment the coefficient buffer for the next set of state values */
-  coeff = *pCoeffs++;
-
-  /* Read Index, from where the state buffer should be read, is calculated. */
-  readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
-
-  /* Wraparound of readIndex */
-  if(readIndex < 0)
-  {
-    readIndex += (int32_t) delaySize;
-  }
-
-  /* Loop over the number of taps. */
-  tapCnt = (uint32_t) numTaps - 1u;
-
-  while(tapCnt > 0u)
-  {
-    /* Working pointer for state buffer is updated */
-    py = pState;
-
-    /* blockSize samples are read from the state buffer */
-    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
-                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
-                         blockSize);
-
-    /* Working pointer for the scratch buffer of state values */
-    px = pb;
-
-    /* Working pointer for scratch buffer of output values */
-    pOut = pDst;
-
-    blkCnt = blockSize;
-
-    while(blkCnt > 0u)
-    {
-      /* Perform Multiply-Accumulate */
-      out = *pOut;
-      out += ((q63_t) * px++ * coeff) >> 32;
-      *pOut++ = (q31_t) (out);
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* Load the coefficient value and           
-     * increment the coefficient buffer for the next set of state values */
-    coeff = *pCoeffs++;
-
-    /* Read Index, from where the state buffer should be read, is calculated. */
-    readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
-
-    /* Wraparound of readIndex */
-    if(readIndex < 0)
-    {
-      readIndex += (int32_t) delaySize;
-    }
-
-    /* Decrement the tap loop counter */
-    tapCnt--;
-  }
-
-  /* Working output pointer is updated */
-  pOut = pDst;
-
-  /* Output is converted into 1.31 format. */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    in = *pOut << 1;
-    *pOut++ = in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
- * @} end of FIR_Sparse group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q7.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q7.c
deleted file mode 100644
index e67339250f..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q7.c
+++ /dev/null
@@ -1,398 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_fir_sparse_q7.c    
-*    
-* Description:	Q7 sparse FIR filter processing function.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ------------------------------------------------------------------- */
-#include "arm_math.h"
-
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup FIR_Sparse    
- * @{    
- */
-
-
-/**   
- * @brief Processing function for the Q7 sparse FIR filter.   
- * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.   
- * @param[in]  *pSrc        points to the block of input data.   
- * @param[out] *pDst        points to the block of output data   
- * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.   
- * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.   
- * @param[in]  blockSize    number of input samples to process per call.   
- * @return none.   
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using a 32-bit internal accumulator.    
- * Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result.    
- * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.    
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    
- * The accumulator is then converted to 18.7 format by discarding the low 7 bits.   
- * Finally, the result is truncated to 1.7 format.   
- */
-
-void arm_fir_sparse_q7(
-  arm_fir_sparse_instance_q7 * S,
-  q7_t * pSrc,
-  q7_t * pDst,
-  q7_t * pScratchIn,
-  q31_t * pScratchOut,
-  uint32_t blockSize)
-{
-
-  q7_t *pState = S->pState;                      /* State pointer */
-  q7_t *pCoeffs = S->pCoeffs;                    /* Coefficient pointer */
-  q7_t *px;                                      /* Scratch buffer pointer */
-  q7_t *py = pState;                             /* Temporary pointers for state buffer */
-  q7_t *pb = pScratchIn;                         /* Temporary pointers for scratch buffer */
-  q7_t *pOut = pDst;                             /* Destination pointer */
-  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
-  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
-  uint16_t numTaps = S->numTaps;                 /* Filter order */
-  int32_t readIndex;                             /* Read index of the state buffer */
-  uint32_t tapCnt, blkCnt;                       /* loop counters */
-  q7_t coeff = *pCoeffs++;                       /* Read the coefficient value */
-  q31_t *pScr2 = pScratchOut;                    /* Working pointer for scratch buffer of output values */
-  q31_t in;
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q7_t in1, in2, in3, in4;
-
-  /* BlockSize of Input samples are copied into the state buffer */
-  /* StateIndex points to the starting position to write in the state buffer */
-  arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1,
-                       blockSize);
-
-  /* Loop over the number of taps. */
-  tapCnt = numTaps;
-
-  /* Read Index, from where the state buffer should be read, is calculated. */
-  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
-
-  /* Wraparound of readIndex */
-  if(readIndex < 0)
-  {
-    readIndex += (int32_t) delaySize;
-  }
-
-  /* Working pointer for state buffer is updated */
-  py = pState;
-
-  /* blockSize samples are read from the state buffer */
-  arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
-                      (int32_t) blockSize, 1, blockSize);
-
-  /* Working pointer for the scratch buffer of state values */
-  px = pb;
-
-  /* Working pointer for scratch buffer of output values */
-  pScratchOut = pScr2;
-
-  /* Loop over the blockSize. Unroll by a factor of 4.    
-   * Compute 4 multiplications at a time. */
-  blkCnt = blockSize >> 2;
-
-  while(blkCnt > 0u)
-  {
-    /* Perform multiplication and store in the scratch buffer */
-    *pScratchOut++ = ((q31_t) * px++ * coeff);
-    *pScratchOut++ = ((q31_t) * px++ * coeff);
-    *pScratchOut++ = ((q31_t) * px++ * coeff);
-    *pScratchOut++ = ((q31_t) * px++ * coeff);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4,    
-   * compute the remaining samples */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* Perform multiplication and store in the scratch buffer */
-    *pScratchOut++ = ((q31_t) * px++ * coeff);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Load the coefficient value and    
-   * increment the coefficient buffer for the next set of state values */
-  coeff = *pCoeffs++;
-
-  /* Read Index, from where the state buffer should be read, is calculated. */
-  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
-
-  /* Wraparound of readIndex */
-  if(readIndex < 0)
-  {
-    readIndex += (int32_t) delaySize;
-  }
-
-  /* Loop over the number of taps. */
-  tapCnt = (uint32_t) numTaps - 1u;
-
-  while(tapCnt > 0u)
-  {
-    /* Working pointer for state buffer is updated */
-    py = pState;
-
-    /* blockSize samples are read from the state buffer */
-    arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
-                        (int32_t) blockSize, 1, blockSize);
-
-    /* Working pointer for the scratch buffer of state values */
-    px = pb;
-
-    /* Working pointer for scratch buffer of output values */
-    pScratchOut = pScr2;
-
-    /* Loop over the blockSize. Unroll by a factor of 4.    
-     * Compute 4 MACS at a time. */
-    blkCnt = blockSize >> 2;
-
-    while(blkCnt > 0u)
-    {
-      /* Perform Multiply-Accumulate */
-      in = *pScratchOut + ((q31_t) * px++ * coeff);
-      *pScratchOut++ = in;
-      in = *pScratchOut + ((q31_t) * px++ * coeff);
-      *pScratchOut++ = in;
-      in = *pScratchOut + ((q31_t) * px++ * coeff);
-      *pScratchOut++ = in;
-      in = *pScratchOut + ((q31_t) * px++ * coeff);
-      *pScratchOut++ = in;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize is not a multiple of 4,    
-     * compute the remaining samples */
-    blkCnt = blockSize % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* Perform Multiply-Accumulate */
-      in = *pScratchOut + ((q31_t) * px++ * coeff);
-      *pScratchOut++ = in;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* Load the coefficient value and    
-     * increment the coefficient buffer for the next set of state values */
-    coeff = *pCoeffs++;
-
-    /* Read Index, from where the state buffer should be read, is calculated. */
-    readIndex = ((int32_t) S->stateIndex -
-                 (int32_t) blockSize) - *pTapDelay++;
-
-    /* Wraparound of readIndex */
-    if(readIndex < 0)
-    {
-      readIndex += (int32_t) delaySize;
-    }
-
-    /* Decrement the tap loop counter */
-    tapCnt--;
-  }
-
-  /* All the output values are in pScratchOut buffer.    
-     Convert them into 1.15 format, saturate and store in the destination buffer. */
-  /* Loop over the blockSize. */
-  blkCnt = blockSize >> 2;
-
-  while(blkCnt > 0u)
-  {
-    in1 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
-    in2 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
-    in3 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
-    in4 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
-
-    *__SIMD32(pOut)++ = __PACKq7(in1, in2, in3, in4);
-
-    /* Decrement the blockSize loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4,    
-     remaining samples are processed in the below loop */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8);
-
-    /* Decrement the blockSize loop counter */
-    blkCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* BlockSize of Input samples are copied into the state buffer */
-  /* StateIndex points to the starting position to write in the state buffer */
-  arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1,
-                       blockSize);
-
-  /* Loop over the number of taps. */
-  tapCnt = numTaps;
-
-  /* Read Index, from where the state buffer should be read, is calculated. */
-  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
-
-  /* Wraparound of readIndex */
-  if(readIndex < 0)
-  {
-    readIndex += (int32_t) delaySize;
-  }
-
-  /* Working pointer for state buffer is updated */
-  py = pState;
-
-  /* blockSize samples are read from the state buffer */
-  arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
-                      (int32_t) blockSize, 1, blockSize);
-
-  /* Working pointer for the scratch buffer of state values */
-  px = pb;
-
-  /* Working pointer for scratch buffer of output values */
-  pScratchOut = pScr2;
-
-  /* Loop over the blockSize */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* Perform multiplication and store in the scratch buffer */
-    *pScratchOut++ = ((q31_t) * px++ * coeff);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Load the coefficient value and           
-   * increment the coefficient buffer for the next set of state values */
-  coeff = *pCoeffs++;
-
-  /* Read Index, from where the state buffer should be read, is calculated. */
-  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
-
-  /* Wraparound of readIndex */
-  if(readIndex < 0)
-  {
-    readIndex += (int32_t) delaySize;
-  }
-
-  /* Loop over the number of taps. */
-  tapCnt = (uint32_t) numTaps - 1u;
-
-  while(tapCnt > 0u)
-  {
-    /* Working pointer for state buffer is updated */
-    py = pState;
-
-    /* blockSize samples are read from the state buffer */
-    arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
-                        (int32_t) blockSize, 1, blockSize);
-
-    /* Working pointer for the scratch buffer of state values */
-    px = pb;
-
-    /* Working pointer for scratch buffer of output values */
-    pScratchOut = pScr2;
-
-    /* Loop over the blockSize */
-    blkCnt = blockSize;
-
-    while(blkCnt > 0u)
-    {
-      /* Perform Multiply-Accumulate */
-      in = *pScratchOut + ((q31_t) * px++ * coeff);
-      *pScratchOut++ = in;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* Load the coefficient value and           
-     * increment the coefficient buffer for the next set of state values */
-    coeff = *pCoeffs++;
-
-    /* Read Index, from where the state buffer should be read, is calculated. */
-    readIndex =
-      ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
-
-    /* Wraparound of readIndex */
-    if(readIndex < 0)
-    {
-      readIndex += (int32_t) delaySize;
-    }
-
-    /* Decrement the tap loop counter */
-    tapCnt--;
-  }
-
-  /* All the output values are in pScratchOut buffer.       
-     Convert them into 1.15 format, saturate and store in the destination buffer. */
-  /* Loop over the blockSize. */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8);
-
-    /* Decrement the blockSize loop counter */
-    blkCnt--;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
- * @} end of FIR_Sparse group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_f32.c
deleted file mode 100644
index 264e15ed9e..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_f32.c
+++ /dev/null
@@ -1,440 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_iir_lattice_f32.c    
-*    
-* Description:	Floating-point IIR Lattice filter processing function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @defgroup IIR_Lattice Infinite Impulse Response (IIR) Lattice Filters    
- *    
- * This set of functions implements lattice filters    
- * for Q15, Q31 and floating-point data types.  Lattice filters are used in a     
- * variety of adaptive filter applications.  The filter structure has feedforward and    
- * feedback components and the net impulse response is infinite length.    
- * The functions operate on blocks    
- * of input and output data and each call to the function processes    
- * blockSize samples through the filter.  pSrc and    
- * pDst point to input and output arrays containing blockSize values.    
-    
- * \par Algorithm:    
- * \image html IIRLattice.gif "Infinite Impulse Response Lattice filter"    
- * 
    
- *    fN(n)   =  x(n)    
- *    fm-1(n) = fm(n) - km * gm-1(n-1)   for m = N, N-1, ...1    
- *    gm(n)   = km * fm-1(n) + gm-1(n-1) for m = N, N-1, ...1    
- *    y(n)    = vN * gN(n) + vN-1 * gN-1(n) + ...+ v0 * g0(n)    
- * 
    
- * \par    
- * pkCoeffs points to array of reflection coefficients of size numStages.     
- * Reflection coefficients are stored in time-reversed order.    
- * \par    
- * 
    
- *    {kN, kN-1, ....k1}    
- * 
    
- * pvCoeffs points to the array of ladder coefficients of size (numStages+1).     
- * Ladder coefficients are stored in time-reversed order.    
- * \par    
- * 
    
- *    {vN, vN-1, ...v0}    
- * 
    
- * pState points to a state array of size numStages + blockSize.    
- * The state variables shown in the figure above (the g values) are stored in the pState array.    
- * The state variables are updated after each block of data is processed; the coefficients are untouched.    
- * \par Instance Structure    
- * The coefficients and state variables for a filter are stored together in an instance data structure.    
- * A separate instance structure must be defined for each filter.    
- * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.    
- * There are separate instance structure declarations for each of the 3 supported data types.    
-  *    
- * \par Initialization Functions    
- * There is also an associated initialization function for each data type.    
- * The initialization function performs the following operations:    
- * - Sets the values of the internal structure fields.    
- * - Zeros out the values in the state buffer.    
- *    
- * \par    
- * Use of the initialization function is optional.    
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
- * To place an instance structure into a const data section, the instance structure must be manually initialized.    
- * Set the values in the state buffer to zeros and then manually initialize the instance structure as follows:    
- * 
    
- *arm_iir_lattice_instance_f32 S = {numStages, pState, pkCoeffs, pvCoeffs};    
- *arm_iir_lattice_instance_q31 S = {numStages, pState, pkCoeffs, pvCoeffs};    
- *arm_iir_lattice_instance_q15 S = {numStages, pState, pkCoeffs, pvCoeffs};    
- * 
    
- * \par    
- * where numStages is the number of stages in the filter; pState points to the state buffer array;    
- * pkCoeffs points to array of the reflection coefficients; pvCoeffs points to the array of ladder coefficients.    
- * \par Fixed-Point Behavior    
- * Care must be taken when using the fixed-point versions of the IIR lattice filter functions.    
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.    
- * Refer to the function specific documentation below for usage guidelines.    
- */
-
-/**    
- * @addtogroup IIR_Lattice    
- * @{    
- */
-
-/**    
- * @brief Processing function for the floating-point IIR lattice filter.    
- * @param[in] *S points to an instance of the floating-point IIR lattice structure.    
- * @param[in] *pSrc points to the block of input data.    
- * @param[out] *pDst points to the block of output data.    
- * @param[in] blockSize number of samples to process.    
- * @return none.    
- */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-void arm_iir_lattice_f32(
-  const arm_iir_lattice_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize)
-{
-  float32_t fnext1, gcurr1, gnext;               /* Temporary variables for lattice stages */
-  float32_t acc;                                 /* Accumlator */
-  uint32_t blkCnt, tapCnt;                       /* temporary variables for counts */
-  float32_t *px1, *px2, *pk, *pv;                /* temporary pointers for state and coef */
-  uint32_t numStages = S->numStages;             /* number of stages */
-  float32_t *pState;                             /* State pointer */
-  float32_t *pStateCurnt;                        /* State current pointer */
-  float32_t k1, k2;
-  float32_t v1, v2, v3, v4;
-  float32_t gcurr2;
-  float32_t fnext2;
-
-  /* initialise loop count */
-  blkCnt = blockSize;
-
-  /* initialise state pointer */
-  pState = &S->pState[0];
-
-  /* Sample processing */
-  while(blkCnt > 0u)
-  {
-    /* Read Sample from input buffer */
-    /* fN(n) = x(n) */
-    fnext2 = *pSrc++;
-
-    /* Initialize Ladder coeff pointer */
-    pv = &S->pvCoeffs[0];
-    /* Initialize Reflection coeff pointer */
-    pk = &S->pkCoeffs[0];
-
-    /* Initialize state read pointer */
-    px1 = pState;
-    /* Initialize state write pointer */
-    px2 = pState;
-
-    /* Set accumulator to zero */
-    acc = 0.0;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = (numStages) >> 2;
-
-    while(tapCnt > 0u)
-    {
-      /* Read gN-1(n-1) from state buffer */
-      gcurr1 = *px1;
-
-      /* read reflection coefficient kN */
-      k1 = *pk;
-
-      /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
-      fnext1 = fnext2 - (k1 * gcurr1);
-
-      /* read ladder coefficient vN */
-      v1 = *pv;
-
-      /* read next reflection coefficient kN-1 */
-      k2 = *(pk + 1u);
-
-      /* Read gN-2(n-1) from state buffer */
-      gcurr2 = *(px1 + 1u);
-
-      /* read next ladder coefficient vN-1 */
-      v2 = *(pv + 1u);
-
-      /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
-      fnext2 = fnext1 - (k2 * gcurr2);
-
-      /* gN(n)   = kN * fN-1(n) + gN-1(n-1) */
-      gnext = gcurr1 + (k1 * fnext1);
-
-      /* read reflection coefficient kN-2 */
-      k1 = *(pk + 2u);
-
-      /* write gN(n) into state for next sample processing */
-      *px2++ = gnext;
-
-      /* Read gN-3(n-1) from state buffer */
-      gcurr1 = *(px1 + 2u);
-
-      /* y(n) += gN(n) * vN  */
-      acc += (gnext * v1);
-
-      /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
-      fnext1 = fnext2 - (k1 * gcurr1);
-
-      /* gN-1(n)   = kN-1 * fN-2(n) + gN-2(n-1) */
-      gnext = gcurr2 + (k2 * fnext2);
-
-      /* Read gN-4(n-1) from state buffer */
-      gcurr2 = *(px1 + 3u);
-
-      /* y(n) += gN-1(n) * vN-1  */
-      acc += (gnext * v2);
-
-      /* read reflection coefficient kN-3 */
-      k2 = *(pk + 3u);
-
-      /* write gN-1(n) into state for next sample processing */
-      *px2++ = gnext;
-
-      /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
-      fnext2 = fnext1 - (k2 * gcurr2);
-
-      /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
-      gnext = gcurr1 + (k1 * fnext1);
-
-      /* read ladder coefficient vN-2 */
-      v3 = *(pv + 2u);
-
-      /* y(n) += gN-2(n) * vN-2  */
-      acc += (gnext * v3);
-
-      /* write gN-2(n) into state for next sample processing */
-      *px2++ = gnext;
-
-      /* update pointer */
-      pk += 4u;
-
-      /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */
-      gnext = (fnext2 * k2) + gcurr2;
-
-      /* read next ladder coefficient vN-3 */
-      v4 = *(pv + 3u);
-
-      /* y(n) += gN-4(n) * vN-4  */
-      acc += (gnext * v4);
-
-      /* write gN-3(n) into state for next sample processing */
-      *px2++ = gnext;
-
-      /* update pointers */
-      px1 += 4u;
-      pv += 4u;
-
-      tapCnt--;
-
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = (numStages) % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      gcurr1 = *px1++;
-      /* Process sample for last taps */
-      fnext1 = fnext2 - ((*pk) * gcurr1);
-      gnext = (fnext1 * (*pk++)) + gcurr1;
-      /* Output samples for last taps */
-      acc += (gnext * (*pv++));
-      *px2++ = gnext;
-      fnext2 = fnext1;
-
-      tapCnt--;
-
-    }
-
-    /* y(n) += g0(n) * v0 */
-    acc += (fnext2 * (*pv));
-
-    *px2++ = fnext2;
-
-    /* write out into pDst */
-    *pDst++ = acc;
-
-    /* Advance the state pointer by 4 to process the next group of 4 samples */
-    pState = pState + 1u;
-
-    blkCnt--;
-
-  }
-
-  /* Processing is complete. Now copy last S->numStages samples to start of the buffer        
-     for the preperation of next frame process */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = &S->pState[0];
-  pState = &S->pState[blockSize];
-
-  tapCnt = numStages >> 2u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-
-  }
-
-  /* Calculate remaining number of copies */
-  tapCnt = (numStages) % 0x4u;
-
-  /* Copy the remaining q31_t data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-}
-
-#else
-
-void arm_iir_lattice_f32(
-  const arm_iir_lattice_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize)
-{
-  float32_t fcurr, fnext = 0, gcurr, gnext;      /* Temporary variables for lattice stages */
-  float32_t acc;                                 /* Accumlator */
-  uint32_t blkCnt, tapCnt;                       /* temporary variables for counts */
-  float32_t *px1, *px2, *pk, *pv;                /* temporary pointers for state and coef */
-  uint32_t numStages = S->numStages;             /* number of stages */
-  float32_t *pState;                             /* State pointer */
-  float32_t *pStateCurnt;                        /* State current pointer */
-
-
-  /* Run the below code for Cortex-M0 */
-
-  blkCnt = blockSize;
-
-  pState = &S->pState[0];
-
-  /* Sample processing */
-  while(blkCnt > 0u)
-  {
-    /* Read Sample from input buffer */
-    /* fN(n) = x(n) */
-    fcurr = *pSrc++;
-
-    /* Initialize state read pointer */
-    px1 = pState;
-    /* Initialize state write pointer */
-    px2 = pState;
-    /* Set accumulator to zero */
-    acc = 0.0f;
-    /* Initialize Ladder coeff pointer */
-    pv = &S->pvCoeffs[0];
-    /* Initialize Reflection coeff pointer */
-    pk = &S->pkCoeffs[0];
-
-
-    /* Process sample for numStages */
-    tapCnt = numStages;
-
-    while(tapCnt > 0u)
-    {
-      gcurr = *px1++;
-      /* Process sample for last taps */
-      fnext = fcurr - ((*pk) * gcurr);
-      gnext = (fnext * (*pk++)) + gcurr;
-
-      /* Output samples for last taps */
-      acc += (gnext * (*pv++));
-      *px2++ = gnext;
-      fcurr = fnext;
-
-      /* Decrementing loop counter */
-      tapCnt--;
-
-    }
-
-    /* y(n) += g0(n) * v0 */
-    acc += (fnext * (*pv));
-
-    *px2++ = fnext;
-
-    /* write out into pDst */
-    *pDst++ = acc;
-
-    /* Advance the state pointer by 1 to process the next group of samples */
-    pState = pState + 1u;
-    blkCnt--;
-
-  }
-
-  /* Processing is complete. Now copy last S->numStages samples to start of the buffer           
-     for the preperation of next frame process */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = &S->pState[0];
-  pState = &S->pState[blockSize];
-
-  tapCnt = numStages;
-
-  /* Copy the data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-}
-
-#endif /*   #ifndef ARM_MATH_CM0 */
-
-
-/**    
- * @} end of IIR_Lattice group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_f32.c
deleted file mode 100644
index e2227e3e5b..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_f32.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_iir_lattice_init_f32.c    
-*    
-* Description:  Floating-point IIR lattice filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup IIR_Lattice    
- * @{    
- */
-
-/**    
- * @brief Initialization function for the floating-point IIR lattice filter.    
- * @param[in] *S points to an instance of the floating-point IIR lattice structure.    
- * @param[in] numStages number of stages in the filter.    
- * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.    
- * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.    
- * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.    
- * @param[in] blockSize number of samples to process.    
- * @return none.    
- */
-
-void arm_iir_lattice_init_f32(
-  arm_iir_lattice_instance_f32 * S,
-  uint16_t numStages,
-  float32_t * pkCoeffs,
-  float32_t * pvCoeffs,
-  float32_t * pState,
-  uint32_t blockSize)
-{
-  /* Assign filter taps */
-  S->numStages = numStages;
-
-  /* Assign reflection coefficient pointer */
-  S->pkCoeffs = pkCoeffs;
-
-  /* Assign ladder coefficient pointer */
-  S->pvCoeffs = pvCoeffs;
-
-  /* Clear state buffer and size is always blockSize + numStages */
-  memset(pState, 0, (numStages + blockSize) * sizeof(float32_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-
-}
-
-  /**    
-   * @} end of IIR_Lattice group    
-   */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q15.c
deleted file mode 100644
index 618505c2cb..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q15.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_iir_lattice_init_q15.c    
-*    
-* Description:  Q15 IIR lattice filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup IIR_Lattice    
- * @{    
- */
-
-  /**    
-   * @brief Initialization function for the Q15 IIR lattice filter.    
-   * @param[in] *S points to an instance of the Q15 IIR lattice structure.    
-   * @param[in] numStages  number of stages in the filter.    
-   * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.    
-   * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.    
-   * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.    
-   * @param[in] blockSize number of samples to process per call.    
-   * @return none.    
-   */
-
-void arm_iir_lattice_init_q15(
-  arm_iir_lattice_instance_q15 * S,
-  uint16_t numStages,
-  q15_t * pkCoeffs,
-  q15_t * pvCoeffs,
-  q15_t * pState,
-  uint32_t blockSize)
-{
-  /* Assign filter taps */
-  S->numStages = numStages;
-
-  /* Assign reflection coefficient pointer */
-  S->pkCoeffs = pkCoeffs;
-
-  /* Assign ladder coefficient pointer */
-  S->pvCoeffs = pvCoeffs;
-
-  /* Clear state buffer and size is always blockSize + numStages */
-  memset(pState, 0, (numStages + blockSize) * sizeof(q15_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-
-}
-
-/**    
- * @} end of IIR_Lattice group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q31.c
deleted file mode 100644
index 85d18e6697..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q31.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_iir_lattice_init_q31.c    
-*    
-* Description:  Initialization function for the Q31 IIR lattice filter.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup IIR_Lattice    
- * @{    
- */
-
-  /**    
-   * @brief Initialization function for the Q31 IIR lattice filter.    
-   * @param[in] *S points to an instance of the Q31 IIR lattice structure.    
-   * @param[in] numStages number of stages in the filter.    
-   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.    
-   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.    
-   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.    
-   * @param[in] blockSize number of samples to process.    
-   * @return none.    
-   */
-
-void arm_iir_lattice_init_q31(
-  arm_iir_lattice_instance_q31 * S,
-  uint16_t numStages,
-  q31_t * pkCoeffs,
-  q31_t * pvCoeffs,
-  q31_t * pState,
-  uint32_t blockSize)
-{
-  /* Assign filter taps */
-  S->numStages = numStages;
-
-  /* Assign reflection coefficient pointer */
-  S->pkCoeffs = pkCoeffs;
-
-  /* Assign ladder coefficient pointer */
-  S->pvCoeffs = pvCoeffs;
-
-  /* Clear state buffer and size is always blockSize + numStages */
-  memset(pState, 0, (numStages + blockSize) * sizeof(q31_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-
-}
-
-/**    
- * @} end of IIR_Lattice group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q15.c
deleted file mode 100644
index a706ae1331..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q15.c
+++ /dev/null
@@ -1,457 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_iir_lattice_q15.c    
-*    
-* Description:	Q15 IIR lattice filter processing function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup IIR_Lattice    
- * @{    
- */
-
-/**    
- * @brief Processing function for the Q15 IIR lattice filter.    
- * @param[in] *S points to an instance of the Q15 IIR lattice structure.    
- * @param[in] *pSrc points to the block of input data.    
- * @param[out] *pDst points to the block of output data.    
- * @param[in] blockSize number of samples to process.    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using a 64-bit internal accumulator.    
- * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.    
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    
- * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.    
- * Lastly, the accumulator is saturated to yield a result in 1.15 format.    
- */
-
-void arm_iir_lattice_q15(
-  const arm_iir_lattice_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t fcurr, fnext, gcurr = 0, gnext;          /* Temporary variables for lattice stages */
-  q15_t gnext1, gnext2;                          /* Temporary variables for lattice stages */
-  uint32_t stgCnt;                               /* Temporary variables for counts */
-  q63_t acc;                                     /* Accumlator */
-  uint32_t blkCnt, tapCnt;                       /* Temporary variables for counts */
-  q15_t *px1, *px2, *pk, *pv;                    /* temporary pointers for state and coef */
-  uint32_t numStages = S->numStages;             /* number of stages */
-  q15_t *pState;                                 /* State pointer */
-  q15_t *pStateCurnt;                            /* State current pointer */
-  q15_t out;                                     /* Temporary variable for output */
-  q15_t v1, v2;
-  q31_t v;                                       /* Temporary variable for ladder coefficient */
-
-
-  blkCnt = blockSize;
-
-  pState = &S->pState[0];
-
-  /* Sample processing */
-  while(blkCnt > 0u)
-  {
-    /* Read Sample from input buffer */
-    /* fN(n) = x(n) */
-    fcurr = *pSrc++;
-
-    /* Initialize state read pointer */
-    px1 = pState;
-    /* Initialize state write pointer */
-    px2 = pState;
-    /* Set accumulator to zero */
-    acc = 0;
-    /* Initialize Ladder coeff pointer */
-    pv = &S->pvCoeffs[0];
-    /* Initialize Reflection coeff pointer */
-    pk = &S->pkCoeffs[0];
-
-
-    /* Process sample for first tap */
-    gcurr = *px1++;
-    /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
-    fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
-    fnext = __SSAT(fnext, 16);
-    /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
-    gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
-    gnext = __SSAT(gnext, 16);
-    /* write gN(n) into state for next sample processing */
-    *px2++ = (q15_t) gnext;
-    /* y(n) += gN(n) * vN  */
-    acc += (q31_t) ((gnext * (*pv++)));
-
-
-    /* Update f values for next coefficient processing */
-    fcurr = fnext;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = (numStages - 1u) >> 2;
-
-    while(tapCnt > 0u)
-    {
-
-      /* Process sample for 2nd, 6th ...taps */
-      /* Read gN-2(n-1) from state buffer */
-      gcurr = *px1++;
-      /* Process sample for 2nd, 6th .. taps */
-      /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
-      fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
-      fnext = __SSAT(fnext, 16);
-      /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
-      gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
-      gnext1 = (q15_t) __SSAT(gnext, 16);
-      /* write gN-1(n) into state */
-      *px2++ = (q15_t) gnext1;
-
-
-      /* Process sample for 3nd, 7th ...taps */
-      /* Read gN-3(n-1) from state */
-      gcurr = *px1++;
-      /* Process sample for 3rd, 7th .. taps */
-      /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
-      fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15);
-      fcurr = __SSAT(fcurr, 16);
-      /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
-      gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr;
-      gnext2 = (q15_t) __SSAT(gnext, 16);
-      /* write gN-2(n) into state */
-      *px2++ = (q15_t) gnext2;
-
-      /* Read vN-1 and vN-2 at a time */
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-      v = *__SIMD32(pv)++;
-
-#else
-
-	  v1 = *pv++;
-	  v2 = *pv++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-	  v = __PKHBT(v1, v2, 16);
-
-#else
-
-	  v = __PKHBT(v2, v1, 16);
-
-#endif	/* 	#ifndef ARM_MATH_BIG_ENDIAN		*/
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE */
-
-
-      /* Pack gN-1(n) and gN-2(n) */
-
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      gnext = __PKHBT(gnext1, gnext2, 16);
-
-#else
-
-      gnext = __PKHBT(gnext2, gnext1, 16);
-
-#endif /*   #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-      /* y(n) += gN-1(n) * vN-1  */
-      /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */
-      /* y(n) += gN-2(n) * vN-2  */
-      /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */
-      acc = __SMLALD(gnext, v, acc);
-
-
-      /* Process sample for 4th, 8th ...taps */
-      /* Read gN-4(n-1) from state */
-      gcurr = *px1++;
-      /* Process sample for 4th, 8th .. taps */
-      /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
-      fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
-      fnext = __SSAT(fnext, 16);
-      /* gN-3(n) = kN-3 * fN-1(n) + gN-1(n-1) */
-      gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
-      gnext1 = (q15_t) __SSAT(gnext, 16);
-      /* write  gN-3(n) for the next sample process */
-      *px2++ = (q15_t) gnext1;
-
-
-      /* Process sample for 5th, 9th ...taps */
-      /* Read gN-5(n-1) from state */
-      gcurr = *px1++;
-      /* Process sample for 5th, 9th .. taps */
-      /* fN-5(n) = fN-4(n) - kN-4 * gN-5(n-1) */
-      fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15);
-      fcurr = __SSAT(fcurr, 16);
-      /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */
-      gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr;
-      gnext2 = (q15_t) __SSAT(gnext, 16);
-      /* write      gN-4(n) for the next sample process */
-      *px2++ = (q15_t) gnext2;
-
-      /* Read vN-3 and vN-4 at a time */
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-      v = *__SIMD32(pv)++;
-
-#else
-
-	  v1 = *pv++;
-	  v2 = *pv++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-	  v = __PKHBT(v1, v2, 16);
-
-#else
-
-	  v = __PKHBT(v2, v1, 16);
-
-#endif	/* #ifndef ARM_MATH_BIG_ENDIAN	 */
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE */
-
-
-      /* Pack gN-3(n) and gN-4(n) */
-#ifndef  ARM_MATH_BIG_ENDIAN
-
-      gnext = __PKHBT(gnext1, gnext2, 16);
-
-#else
-
-      gnext = __PKHBT(gnext2, gnext1, 16);
-
-#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
-
-      /* y(n) += gN-4(n) * vN-4  */
-      /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */
-      /* y(n) += gN-3(n) * vN-3  */
-      /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */
-      acc = __SMLALD(gnext, v, acc);
-
-      tapCnt--;
-
-    }
-
-    fnext = fcurr;
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = (numStages - 1u) % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      gcurr = *px1++;
-      /* Process sample for last taps */
-      fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
-      fnext = __SSAT(fnext, 16);
-      gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
-      gnext = __SSAT(gnext, 16);
-      /* Output samples for last taps */
-      acc += (q31_t) (((q31_t) gnext * (*pv++)));
-      *px2++ = (q15_t) gnext;
-      fcurr = fnext;
-
-      tapCnt--;
-    }
-
-    /* y(n) += g0(n) * v0 */
-    acc += (q31_t) (((q31_t) fnext * (*pv++)));
-
-    out = (q15_t) __SSAT(acc >> 15, 16);
-    *px2++ = (q15_t) fnext;
-
-    /* write out into pDst */
-    *pDst++ = out;
-
-    /* Advance the state pointer by 4 to process the next group of 4 samples */
-    pState = pState + 1u;
-    blkCnt--;
-
-  }
-
-  /* Processing is complete. Now copy last S->numStages samples to start of the buffer    
-     for the preperation of next frame process */
-  /* Points to the start of the state buffer */
-  pStateCurnt = &S->pState[0];
-  pState = &S->pState[blockSize];
-
-  stgCnt = (numStages >> 2u);
-
-  /* copy data */
-  while(stgCnt > 0u)
-  {
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-
-#else
-
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-#endif /*	#ifndef UNALIGNED_SUPPORT_DISABLE */
-
-    /* Decrement the loop counter */
-    stgCnt--;
-
-  }
-
-  /* Calculation of count for remaining q15_t data */
-  stgCnt = (numStages) % 0x4u;
-
-  /* copy data */
-  while(stgCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    stgCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q31_t fcurr, fnext = 0, gcurr = 0, gnext;      /* Temporary variables for lattice stages */
-  uint32_t stgCnt;                               /* Temporary variables for counts */
-  q63_t acc;                                     /* Accumlator */
-  uint32_t blkCnt, tapCnt;                       /* Temporary variables for counts */
-  q15_t *px1, *px2, *pk, *pv;                    /* temporary pointers for state and coef */
-  uint32_t numStages = S->numStages;             /* number of stages */
-  q15_t *pState;                                 /* State pointer */
-  q15_t *pStateCurnt;                            /* State current pointer */
-  q15_t out;                                     /* Temporary variable for output */
-
-
-  blkCnt = blockSize;
-
-  pState = &S->pState[0];
-
-  /* Sample processing */
-  while(blkCnt > 0u)
-  {
-    /* Read Sample from input buffer */
-    /* fN(n) = x(n) */
-    fcurr = *pSrc++;
-
-    /* Initialize state read pointer */
-    px1 = pState;
-    /* Initialize state write pointer */
-    px2 = pState;
-    /* Set accumulator to zero */
-    acc = 0;
-    /* Initialize Ladder coeff pointer */
-    pv = &S->pvCoeffs[0];
-    /* Initialize Reflection coeff pointer */
-    pk = &S->pkCoeffs[0];
-
-    tapCnt = numStages;
-
-    while(tapCnt > 0u)
-    {
-      gcurr = *px1++;
-      /* Process sample */
-      /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
-      fnext = fcurr - ((gcurr * (*pk)) >> 15);
-      fnext = __SSAT(fnext, 16);
-      /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
-      gnext = ((fnext * (*pk++)) >> 15) + gcurr;
-      gnext = __SSAT(gnext, 16);
-      /* Output samples */
-      /* y(n) += gN(n) * vN */
-      acc += (q31_t) ((gnext * (*pv++)));
-      /* write gN(n) into state for next sample processing */
-      *px2++ = (q15_t) gnext;
-      /* Update f values for next coefficient processing */
-      fcurr = fnext;
-
-      tapCnt--;
-    }
-
-    /* y(n) += g0(n) * v0 */
-    acc += (q31_t) ((fnext * (*pv++)));
-
-    out = (q15_t) __SSAT(acc >> 15, 16);
-    *px2++ = (q15_t) fnext;
-
-    /* write out into pDst */
-    *pDst++ = out;
-
-    /* Advance the state pointer by 1 to process the next group of samples */
-    pState = pState + 1u;
-    blkCnt--;
-
-  }
-
-  /* Processing is complete. Now copy last S->numStages samples to start of the buffer           
-     for the preperation of next frame process */
-  /* Points to the start of the state buffer */
-  pStateCurnt = &S->pState[0];
-  pState = &S->pState[blockSize];
-
-  stgCnt = numStages;
-
-  /* copy data */
-  while(stgCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    stgCnt--;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0 */
-
-}
-
-
-
-
-/**    
- * @} end of IIR_Lattice group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q31.c
deleted file mode 100644
index cff10f872e..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q31.c
+++ /dev/null
@@ -1,345 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_iir_lattice_q31.c    
-*    
-* Description:	Q31 IIR lattice filter processing function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup IIR_Lattice    
- * @{    
- */
-
-/**    
- * @brief Processing function for the Q31 IIR lattice filter.    
- * @param[in] *S points to an instance of the Q31 IIR lattice structure.    
- * @param[in] *pSrc points to the block of input data.    
- * @param[out] *pDst points to the block of output data.    
- * @param[in] blockSize number of samples to process.    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using an internal 64-bit accumulator.    
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.    
- * Thus, if the accumulator result overflows it wraps around rather than clip.    
- * In order to avoid overflows completely the input signal must be scaled down by 2*log2(numStages) bits.    
- * After all multiply-accumulates are performed, the 2.62 accumulator is saturated to 1.32 format and then truncated to 1.31 format.    
- */
-
-void arm_iir_lattice_q31(
-  const arm_iir_lattice_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  q31_t fcurr, fnext = 0, gcurr = 0, gnext;      /* Temporary variables for lattice stages */
-  q63_t acc;                                     /* Accumlator */
-  uint32_t blkCnt, tapCnt;                       /* Temporary variables for counts */
-  q31_t *px1, *px2, *pk, *pv;                    /* Temporary pointers for state and coef */
-  uint32_t numStages = S->numStages;             /* number of stages */
-  q31_t *pState;                                 /* State pointer */
-  q31_t *pStateCurnt;                            /* State current pointer */
-
-  blkCnt = blockSize;
-
-  pState = &S->pState[0];
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /* Sample processing */
-  while(blkCnt > 0u)
-  {
-    /* Read Sample from input buffer */
-    /* fN(n) = x(n) */
-    fcurr = *pSrc++;
-
-    /* Initialize state read pointer */
-    px1 = pState;
-    /* Initialize state write pointer */
-    px2 = pState;
-    /* Set accumulator to zero */
-    acc = 0;
-    /* Initialize Ladder coeff pointer */
-    pv = &S->pvCoeffs[0];
-    /* Initialize Reflection coeff pointer */
-    pk = &S->pkCoeffs[0];
-
-
-    /* Process sample for first tap */
-    gcurr = *px1++;
-    /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
-    fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
-    /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
-    gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
-    /* write gN-1(n-1) into state for next sample processing */
-    *px2++ = gnext;
-    /* y(n) += gN(n) * vN  */
-    acc += ((q63_t) gnext * *pv++);
-
-    /* Update f values for next coefficient processing */
-    fcurr = fnext;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = (numStages - 1u) >> 2;
-
-    while(tapCnt > 0u)
-    {
-
-      /* Process sample for 2nd, 6th .. taps */
-      /* Read gN-2(n-1) from state buffer */
-      gcurr = *px1++;
-      /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
-      fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
-      /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
-      gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
-      /* y(n) += gN-1(n) * vN-1  */
-      /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */
-      acc += ((q63_t) gnext * *pv++);
-      /* write gN-1(n) into state for next sample processing */
-      *px2++ = gnext;
-
-      /* Process sample for 3nd, 7th ...taps */
-      /* Read gN-3(n-1) from state buffer */
-      gcurr = *px1++;
-      /* Process sample for 3rd, 7th .. taps */
-      /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
-      fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
-      /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
-      gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31));
-      /* y(n) += gN-2(n) * vN-2  */
-      /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */
-      acc += ((q63_t) gnext * *pv++);
-      /* write gN-2(n) into state for next sample processing */
-      *px2++ = gnext;
-
-
-      /* Process sample for 4th, 8th ...taps */
-      /* Read gN-4(n-1) from state buffer */
-      gcurr = *px1++;
-      /* Process sample for 4th, 8th .. taps */
-      /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
-      fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
-      /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */
-      gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
-      /* y(n) += gN-3(n) * vN-3  */
-      /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */
-      acc += ((q63_t) gnext * *pv++);
-      /* write gN-3(n) into state for next sample processing */
-      *px2++ = gnext;
-
-
-      /* Process sample for 5th, 9th ...taps */
-      /* Read gN-5(n-1) from state buffer */
-      gcurr = *px1++;
-      /* Process sample for 5th, 9th .. taps */
-      /* fN-5(n) = fN-4(n) - kN-4 * gN-1(n-1) */
-      fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
-      /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */
-      gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31));
-      /* y(n) += gN-4(n) * vN-4  */
-      /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */
-      acc += ((q63_t) gnext * *pv++);
-      /* write gN-4(n) into state for next sample processing */
-      *px2++ = gnext;
-
-      tapCnt--;
-
-    }
-
-    fnext = fcurr;
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = (numStages - 1u) % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      gcurr = *px1++;
-      /* Process sample for last taps */
-      fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
-      gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
-      /* Output samples for last taps */
-      acc += ((q63_t) gnext * *pv++);
-      *px2++ = gnext;
-      fcurr = fnext;
-
-      tapCnt--;
-
-    }
-
-    /* y(n) += g0(n) * v0 */
-    acc += (q63_t) fnext *(
-  *pv++);
-
-    *px2++ = fnext;
-
-    /* write out into pDst */
-    *pDst++ = (q31_t) (acc >> 31u);
-
-    /* Advance the state pointer by 4 to process the next group of 4 samples */
-    pState = pState + 1u;
-    blkCnt--;
-
-  }
-
-  /* Processing is complete. Now copy last S->numStages samples to start of the buffer    
-     for the preperation of next frame process */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = &S->pState[0];
-  pState = &S->pState[blockSize];
-
-  tapCnt = numStages >> 2u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-
-  }
-
-  /* Calculate remaining number of copies */
-  tapCnt = (numStages) % 0x4u;
-
-  /* Copy the remaining q31_t data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  };
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  /* Sample processing */
-  while(blkCnt > 0u)
-  {
-    /* Read Sample from input buffer */
-    /* fN(n) = x(n) */
-    fcurr = *pSrc++;
-
-    /* Initialize state read pointer */
-    px1 = pState;
-    /* Initialize state write pointer */
-    px2 = pState;
-    /* Set accumulator to zero */
-    acc = 0;
-    /* Initialize Ladder coeff pointer */
-    pv = &S->pvCoeffs[0];
-    /* Initialize Reflection coeff pointer */
-    pk = &S->pkCoeffs[0];
-
-    tapCnt = numStages;
-
-    while(tapCnt > 0u)
-    {
-      gcurr = *px1++;
-      /* Process sample */
-      /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
-      fnext =
-        clip_q63_to_q31(((q63_t) fcurr -
-                         ((q31_t) (((q63_t) gcurr * (*pk)) >> 31))));
-      /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
-      gnext =
-        clip_q63_to_q31(((q63_t) gcurr +
-                         ((q31_t) (((q63_t) fnext * (*pk++)) >> 31))));
-      /* Output samples */
-      /* y(n) += gN(n) * vN  */
-      acc += ((q63_t) gnext * *pv++);
-      /* write gN-1(n-1) into state for next sample processing */
-      *px2++ = gnext;
-      /* Update f values for next coefficient processing */
-      fcurr = fnext;
-
-      tapCnt--;
-    }
-
-    /* y(n) += g0(n) * v0 */
-    acc += (q63_t) fnext *(
-  *pv++);
-
-    *px2++ = fnext;
-
-    /* write out into pDst */
-    *pDst++ = (q31_t) (acc >> 31u);
-
-    /* Advance the state pointer by 1 to process the next group of samples */
-    pState = pState + 1u;
-    blkCnt--;
-
-  }
-
-  /* Processing is complete. Now copy last S->numStages samples to start of the buffer           
-     for the preperation of next frame process */
-
-  /* Points to the start of the state buffer */
-  pStateCurnt = &S->pState[0];
-  pState = &S->pState[blockSize];
-
-  tapCnt = numStages;
-
-  /* Copy the remaining q31_t data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0 */
-
-}
-
-
-
-
-/**    
- * @} end of IIR_Lattice group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_f32.c
deleted file mode 100644
index ca804ed101..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_f32.c
+++ /dev/null
@@ -1,434 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_lms_f32.c    
-*    
-* Description:	Processing function for the floating-point LMS filter.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @defgroup LMS Least Mean Square (LMS) Filters    
- *    
- * LMS filters are a class of adaptive filters that are able to "learn" an unknown transfer functions.    
- * LMS filters use a gradient descent method in which the filter coefficients are updated based on the instantaneous error signal.    
- * Adaptive filters are often used in communication systems, equalizers, and noise removal.    
- * The CMSIS DSP Library contains LMS filter functions that operate on Q15, Q31, and floating-point data types.    
- * The library also contains normalized LMS filters in which the filter coefficient adaptation is indepedent of the level of the input signal.    
- *    
- * An LMS filter consists of two components as shown below.    
- * The first component is a standard transversal or FIR filter.    
- * The second component is a coefficient update mechanism.    
- * The LMS filter has two input signals.    
- * The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter.    
- * That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input.    
- * The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input.    
- * This "error signal" tends towards zero as the filter adapts.    
- * The LMS processing functions accept the input and reference input signals and generate the filter output and error signal.    
- * \image html LMS.gif "Internal structure of the Least Mean Square filter"    
- *    
- * The functions operate on blocks of data and each call to the function processes    
- * blockSize samples through the filter.    
- * pSrc points to input signal, pRef points to reference signal,    
- * pOut points to output signal and pErr points to error signal.    
- * All arrays contain blockSize values.    
- *    
- * The functions operate on a block-by-block basis.    
- * Internally, the filter coefficients b[n] are updated on a sample-by-sample basis.    
- * The convergence of the LMS filter is slower compared to the normalized LMS algorithm.    
- *    
- * \par Algorithm:    
- * The output signal y[n] is computed by a standard FIR filter:    
- * 
    
- *     y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]    
- * 
    
- *    
- * \par    
- * The error signal equals the difference between the reference signal d[n] and the filter output:    
- * 
    
- *     e[n] = d[n] - y[n].    
- * 
    
- *    
- * \par    
- * After each sample of the error signal is computed, the filter coefficients b[k] are updated on a sample-by-sample basis:    
- * 
    
- *     b[k] = b[k] + e[n] * mu * x[n-k],  for k=0, 1, ..., numTaps-1    
- * 
    
- * where mu is the step size and controls the rate of coefficient convergence.    
- *\par    
- * In the APIs, pCoeffs points to a coefficient array of size numTaps.    
- * Coefficients are stored in time reversed order.    
- * \par    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * \par    
- * pState points to a state array of size numTaps + blockSize - 1.    
- * Samples in the state buffer are stored in the order:    
- * \par    
- * 
    
- *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}    
- * 
    
- * \par    
- * Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples.    
- * The increased state buffer length allows circular addressing, which is traditionally used in FIR filters,    
- * to be avoided and yields a significant speed improvement.    
- * The state variables are updated after each block of data is processed.    
- * \par Instance Structure    
- * The coefficients and state variables for a filter are stored together in an instance data structure.    
- * A separate instance structure must be defined for each filter and    
- * coefficient and state arrays cannot be shared among instances.    
- * There are separate instance structure declarations for each of the 3 supported data types.    
- *    
- * \par Initialization Functions    
- * There is also an associated initialization function for each data type.    
- * The initialization function performs the following operations:    
- * - Sets the values of the internal structure fields.    
- * - Zeros out the values in the state buffer.    
- * \par    
- * Use of the initialization function is optional.    
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
- * To place an instance structure into a const data section, the instance structure must be manually initialized.    
- * Set the values in the state buffer to zeros before static initialization.    
- * The code below statically initializes each of the 3 different data type filter instance structures    
- * 
    
- *    arm_lms_instance_f32 S = {numTaps, pState, pCoeffs, mu};    
- *    arm_lms_instance_q31 S = {numTaps, pState, pCoeffs, mu, postShift};    
- *    arm_lms_instance_q15 S = {numTaps, pState, pCoeffs, mu, postShift};    
- * 
    
- * where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer;    
- * pCoeffs is the address of the coefficient buffer; mu is the step size parameter; and postShift is the shift applied to coefficients.    
- *    
- * \par Fixed-Point Behavior:    
- * Care must be taken when using the Q15 and Q31 versions of the LMS filter.    
- * The following issues must be considered:    
- * - Scaling of coefficients    
- * - Overflow and saturation    
- *    
- * \par Scaling of Coefficients:    
- * Filter coefficients are represented as fractional values and    
- * coefficients are restricted to lie in the range [-1 +1).    
- * The fixed-point functions have an additional scaling parameter postShift.    
- * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.    
- * This essentially scales the filter coefficients by 2^postShift and    
- * allows the filter coefficients to exceed the range [+1 -1).    
- * The value of postShift is set by the user based on the expected gain through the system being modeled.    
- *    
- * \par Overflow and Saturation:    
- * Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are    
- * described separately as part of the function specific documentation below.    
- */
-
-/**    
- * @addtogroup LMS    
- * @{    
- */
-
-/**           
- * @details           
- * This function operates on floating-point data types.       
- *    
- * @brief Processing function for floating-point LMS filter.    
- * @param[in]  *S points to an instance of the floating-point LMS filter structure.    
- * @param[in]  *pSrc points to the block of input data.    
- * @param[in]  *pRef points to the block of reference data.    
- * @param[out] *pOut points to the block of output data.    
- * @param[out] *pErr points to the block of error data.    
- * @param[in]  blockSize number of samples to process.    
- * @return     none.    
- */
-
-void arm_lms_f32(
-  const arm_lms_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pRef,
-  float32_t * pOut,
-  float32_t * pErr,
-  uint32_t blockSize)
-{
-  float32_t *pState = S->pState;                 /* State pointer */
-  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
-  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
-  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
-  float32_t mu = S->mu;                          /* Adaptive factor */
-  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
-  uint32_t tapCnt, blkCnt;                       /* Loop counters */
-  float32_t sum, e, d;                           /* accumulator, error, reference data sample */
-  float32_t w = 0.0f;                            /* weight factor */
-
-  e = 0.0f;
-  d = 0.0f;
-
-  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  blkCnt = blockSize;
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  while(blkCnt > 0u)
-  {
-    /* Copy the new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = (pCoeffs);
-
-    /* Set the accumulator to zero */
-    sum = 0.0f;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      sum += (*px++) * (*pb++);
-      sum += (*px++) * (*pb++);
-      sum += (*px++) * (*pb++);
-      sum += (*px++) * (*pb++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      sum += (*px++) * (*pb++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* The result in the accumulator, store in the destination buffer. */
-    *pOut++ = sum;
-
-    /* Compute and store error */
-    d = (float32_t) (*pRef++);
-    e = d - sum;
-    *pErr++ = e;
-
-    /* Calculation of Weighting factor for the updating filter coefficients */
-    w = e * mu;
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = (pCoeffs);
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Update filter coefficients */
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      *pb = *pb + (w * (*px++));
-      pb++;
-
-      *pb = *pb + (w * (*px++));
-      pb++;
-
-      *pb = *pb + (w * (*px++));
-      pb++;
-
-      *pb = *pb + (w * (*px++));
-      pb++;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      *pb = *pb + (w * (*px++));
-      pb++;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-
-  /* Processing is complete. Now copy the last numTaps - 1 samples to the    
-     satrt of the state buffer. This prepares the state buffer for the    
-     next function call. */
-
-  /* Points to the start of the pState buffer */
-  pStateCurnt = S->pState;
-
-  /* Loop unrolling for (numTaps - 1u) samples copy */
-  tapCnt = (numTaps - 1u) >> 2u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-  /* Calculate remaining number of copies */
-  tapCnt = (numTaps - 1u) % 0x4u;
-
-  /* Copy the remaining q31_t data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  while(blkCnt > 0u)
-  {
-    /* Copy the new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize pCoeffs pointer */
-    pb = pCoeffs;
-
-    /* Set the accumulator to zero */
-    sum = 0.0f;
-
-    /* Loop over numTaps number of values */
-    tapCnt = numTaps;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      sum += (*px++) * (*pb++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* The result is stored in the destination buffer. */
-    *pOut++ = sum;
-
-    /* Compute and store error */
-    d = (float32_t) (*pRef++);
-    e = d - sum;
-    *pErr++ = e;
-
-    /* Weighting factor for the LMS version */
-    w = e * mu;
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize pCoeffs pointer */
-    pb = pCoeffs;
-
-    /* Loop over numTaps number of values */
-    tapCnt = numTaps;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      *pb = *pb + (w * (*px++));
-      pb++;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-
-  /* Processing is complete. Now copy the last numTaps - 1 samples to the        
-   * start of the state buffer. This prepares the state buffer for the        
-   * next function call. */
-
-  /* Points to the start of the pState buffer */
-  pStateCurnt = S->pState;
-
-  /*  Copy (numTaps - 1u) samples  */
-  tapCnt = (numTaps - 1u);
-
-  /* Copy the data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
-   * @} end of LMS group    
-   */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_f32.c
deleted file mode 100644
index 8030ba334b..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_f32.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_lms_init_f32.c    
-*    
-* Description:  Floating-point LMS filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @addtogroup LMS    
- * @{    
- */
-
-  /**    
-   * @brief Initialization function for floating-point LMS filter.    
-   * @param[in] *S points to an instance of the floating-point LMS filter structure.    
-   * @param[in] numTaps  number of filter coefficients.    
-   * @param[in] *pCoeffs points to the coefficient buffer.    
-   * @param[in] *pState points to state buffer.    
-   * @param[in] mu step size that controls filter coefficient updates.    
-   * @param[in] blockSize number of samples to process.    
-   * @return none.    
-   */
-
-/**    
- * \par Description:    
- * pCoeffs points to the array of filter coefficients stored in time reversed order:    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * The initial filter coefficients serve as a starting point for the adaptive filter.    
- * pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_f32().    
- */
-
-void arm_lms_init_f32(
-  arm_lms_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  float32_t mu,
-  uint32_t blockSize)
-{
-  /* Assign filter taps */
-  S->numTaps = numTaps;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and size is always blockSize + numTaps */
-  memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(float32_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-  /* Assign Step size value */
-  S->mu = mu;
-}
-
-/**    
- * @} end of LMS group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q15.c
deleted file mode 100644
index e6dbf3467b..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q15.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_lms_init_q15.c    
-*    
-* Description:  Q15 LMS filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup LMS    
- * @{    
- */
-
-/**    
-* @brief Initialization function for the Q15 LMS filter.    
-* @param[in] *S points to an instance of the Q15 LMS filter structure.    
-* @param[in] numTaps  number of filter coefficients.    
-* @param[in] *pCoeffs points to the coefficient buffer.    
-* @param[in] *pState points to the state buffer.    
-* @param[in] mu step size that controls filter coefficient updates.    
-* @param[in] blockSize number of samples to process.    
-* @param[in] postShift bit shift applied to coefficients.    
-* @return    none.    
-*    
-* \par Description:    
-* pCoeffs points to the array of filter coefficients stored in time reversed order:    
-* 
    
-*    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
-* 
    
-* The initial filter coefficients serve as a starting point for the adaptive filter.    
-* pState points to the array of state variables and size of array is    
-* numTaps+blockSize-1 samples, where blockSize is the number of    
-* input samples processed by each call to arm_lms_q15().    
-*/
-
-void arm_lms_init_q15(
-  arm_lms_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  q15_t mu,
-  uint32_t blockSize,
-  uint32_t postShift)
-{
-  /* Assign filter taps */
-  S->numTaps = numTaps;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and size is always blockSize + numTaps - 1 */
-  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-  /* Assign Step size value */
-  S->mu = mu;
-
-  /* Assign postShift value to be applied */
-  S->postShift = postShift;
-
-}
-
-/**    
- * @} end of LMS group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q31.c
deleted file mode 100644
index bb3dfcb2a8..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q31.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_lms_init_q31.c    
-*    
-* Description:  Q31 LMS filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup LMS    
- * @{    
- */
-
-  /**    
-   * @brief Initialization function for Q31 LMS filter.    
-   * @param[in] *S points to an instance of the Q31 LMS filter structure.    
-   * @param[in] numTaps  number of filter coefficients.    
-   * @param[in] *pCoeffs points to coefficient buffer.    
-   * @param[in] *pState points to state buffer.    
-   * @param[in] mu step size that controls filter coefficient updates.    
-   * @param[in] blockSize number of samples to process.    
-   * @param[in] postShift bit shift applied to coefficients.    
-   * @return none.    
- *    
- * \par Description:    
- * pCoeffs points to the array of filter coefficients stored in time reversed order:    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * The initial filter coefficients serve as a starting point for the adaptive filter.    
- * pState points to an array of length numTaps+blockSize-1 samples,    
- * where blockSize is the number of input samples processed by each call to    
- * arm_lms_q31().    
- */
-
-void arm_lms_init_q31(
-  arm_lms_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  q31_t mu,
-  uint32_t blockSize,
-  uint32_t postShift)
-{
-  /* Assign filter taps */
-  S->numTaps = numTaps;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and size is always blockSize + numTaps - 1 */
-  memset(pState, 0, ((uint32_t) numTaps + (blockSize - 1u)) * sizeof(q31_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-  /* Assign Step size value */
-  S->mu = mu;
-
-  /* Assign postShift value to be applied */
-  S->postShift = postShift;
-
-}
-
-/**    
- * @} end of LMS group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_f32.c
deleted file mode 100644
index 3237f0f1b6..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_f32.c
+++ /dev/null
@@ -1,456 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_lms_norm_f32.c    
-*    
-* Description:	Processing function for the floating-point Normalised LMS.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @defgroup LMS_NORM Normalized LMS Filters    
- *    
- * This set of functions implements a commonly used adaptive filter.    
- * It is related to the Least Mean Square (LMS) adaptive filter and includes an additional normalization    
- * factor which increases the adaptation rate of the filter.    
- * The CMSIS DSP Library contains normalized LMS filter functions that operate on Q15, Q31, and floating-point data types.    
- *    
- * A normalized least mean square (NLMS) filter consists of two components as shown below.    
- * The first component is a standard transversal or FIR filter.    
- * The second component is a coefficient update mechanism.    
- * The NLMS filter has two input signals.    
- * The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter.    
- * That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input.    
- * The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input.    
- * This "error signal" tends towards zero as the filter adapts.    
- * The NLMS processing functions accept the input and reference input signals and generate the filter output and error signal.    
- * \image html LMS.gif "Internal structure of the NLMS adaptive filter"    
- *    
- * The functions operate on blocks of data and each call to the function processes    
- * blockSize samples through the filter.    
- * pSrc points to input signal, pRef points to reference signal,    
- * pOut points to output signal and pErr points to error signal.    
- * All arrays contain blockSize values.    
- *    
- * The functions operate on a block-by-block basis.    
- * Internally, the filter coefficients b[n] are updated on a sample-by-sample basis.    
- * The convergence of the LMS filter is slower compared to the normalized LMS algorithm.    
- *    
- * \par Algorithm:    
- * The output signal y[n] is computed by a standard FIR filter:    
- * 
    
- *     y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]    
- * 
    
- *    
- * \par    
- * The error signal equals the difference between the reference signal d[n] and the filter output:    
- * 
    
- *     e[n] = d[n] - y[n].    
- * 
    
- *    
- * \par    
- * After each sample of the error signal is computed the instanteous energy of the filter state variables is calculated:    
- * 
    
- *    E = x[n]^2 + x[n-1]^2 + ... + x[n-numTaps+1]^2.    
- * 
    
- * The filter coefficients b[k] are then updated on a sample-by-sample basis:    
- * 
    
- *     b[k] = b[k] + e[n] * (mu/E) * x[n-k],  for k=0, 1, ..., numTaps-1    
- * 
    
- * where mu is the step size and controls the rate of coefficient convergence.    
- *\par    
- * In the APIs, pCoeffs points to a coefficient array of size numTaps.    
- * Coefficients are stored in time reversed order.    
- * \par    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * \par    
- * pState points to a state array of size numTaps + blockSize - 1.    
- * Samples in the state buffer are stored in the order:    
- * \par    
- * 
    
- *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}    
- * 
    
- * \par    
- * Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples.    
- * The increased state buffer length allows circular addressing, which is traditionally used in FIR filters,    
- * to be avoided and yields a significant speed improvement.    
- * The state variables are updated after each block of data is processed.    
- * \par Instance Structure    
- * The coefficients and state variables for a filter are stored together in an instance data structure.    
- * A separate instance structure must be defined for each filter and    
- * coefficient and state arrays cannot be shared among instances.    
- * There are separate instance structure declarations for each of the 3 supported data types.    
- *    
- * \par Initialization Functions    
- * There is also an associated initialization function for each data type.    
- * The initialization function performs the following operations:    
- * - Sets the values of the internal structure fields.    
- * - Zeros out the values in the state buffer.    
- * \par    
- * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.    
- * \par Fixed-Point Behavior:    
- * Care must be taken when using the Q15 and Q31 versions of the normalised LMS filter.    
- * The following issues must be considered:    
- * - Scaling of coefficients    
- * - Overflow and saturation    
- *    
- * \par Scaling of Coefficients:    
- * Filter coefficients are represented as fractional values and    
- * coefficients are restricted to lie in the range [-1 +1).    
- * The fixed-point functions have an additional scaling parameter postShift.    
- * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.    
- * This essentially scales the filter coefficients by 2^postShift and    
- * allows the filter coefficients to exceed the range [+1 -1).    
- * The value of postShift is set by the user based on the expected gain through the system being modeled.    
- *    
- * \par Overflow and Saturation:    
- * Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are    
- * described separately as part of the function specific documentation below.    
- */
-
-
-/**    
- * @addtogroup LMS_NORM    
- * @{    
- */
-
-
-  /**    
-   * @brief Processing function for floating-point normalized LMS filter.    
-   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.    
-   * @param[in] *pSrc points to the block of input data.    
-   * @param[in] *pRef points to the block of reference data.    
-   * @param[out] *pOut points to the block of output data.    
-   * @param[out] *pErr points to the block of error data.    
-   * @param[in] blockSize number of samples to process.    
-   * @return none.    
-   */
-
-void arm_lms_norm_f32(
-  arm_lms_norm_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pRef,
-  float32_t * pOut,
-  float32_t * pErr,
-  uint32_t blockSize)
-{
-  float32_t *pState = S->pState;                 /* State pointer */
-  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
-  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
-  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
-  float32_t mu = S->mu;                          /* Adaptive factor */
-  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
-  uint32_t tapCnt, blkCnt;                       /* Loop counters */
-  float32_t energy;                              /* Energy of the input */
-  float32_t sum, e, d;                           /* accumulator, error, reference data sample */
-  float32_t w, x0, in;                           /* weight factor, temporary variable to hold input sample and state */
-
-  /* Initializations of error,  difference, Coefficient update */
-  e = 0.0f;
-  d = 0.0f;
-  w = 0.0f;
-
-  energy = S->energy;
-  x0 = S->x0;
-
-  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  while(blkCnt > 0u)
-  {
-    /* Copy the new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc;
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = (pCoeffs);
-
-    /* Read the sample from input buffer */
-    in = *pSrc++;
-
-    /* Update the energy calculation */
-    energy -= x0 * x0;
-    energy += in * in;
-
-    /* Set the accumulator to zero */
-    sum = 0.0f;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      sum += (*px++) * (*pb++);
-      sum += (*px++) * (*pb++);
-      sum += (*px++) * (*pb++);
-      sum += (*px++) * (*pb++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      sum += (*px++) * (*pb++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* The result in the accumulator, store in the destination buffer. */
-    *pOut++ = sum;
-
-    /* Compute and store error */
-    d = (float32_t) (*pRef++);
-    e = d - sum;
-    *pErr++ = e;
-
-    /* Calculation of Weighting factor for updating filter coefficients */
-    /* epsilon value 0.000000119209289f */
-    w = (e * mu) / (energy + 0.000000119209289f);
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = (pCoeffs);
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Update filter coefficients */
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      *pb += w * (*px++);
-      pb++;
-
-      *pb += w * (*px++);
-      pb++;
-
-      *pb += w * (*px++);
-      pb++;
-
-      *pb += w * (*px++);
-      pb++;
-
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      *pb += w * (*px++);
-      pb++;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    x0 = *pState;
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  S->energy = energy;
-  S->x0 = x0;
-
-  /* Processing is complete. Now copy the last numTaps - 1 samples to the    
-     satrt of the state buffer. This prepares the state buffer for the    
-     next function call. */
-
-  /* Points to the start of the pState buffer */
-  pStateCurnt = S->pState;
-
-  /* Loop unrolling for (numTaps - 1u)/4 samples copy */
-  tapCnt = (numTaps - 1u) >> 2u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-  /* Calculate remaining number of copies */
-  tapCnt = (numTaps - 1u) % 0x4u;
-
-  /* Copy the remaining q31_t data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  while(blkCnt > 0u)
-  {
-    /* Copy the new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc;
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize pCoeffs pointer */
-    pb = pCoeffs;
-
-    /* Read the sample from input buffer */
-    in = *pSrc++;
-
-    /* Update the energy calculation */
-    energy -= x0 * x0;
-    energy += in * in;
-
-    /* Set the accumulator to zero */
-    sum = 0.0f;
-
-    /* Loop over numTaps number of values */
-    tapCnt = numTaps;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      sum += (*px++) * (*pb++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* The result in the accumulator is stored in the destination buffer. */
-    *pOut++ = sum;
-
-    /* Compute and store error */
-    d = (float32_t) (*pRef++);
-    e = d - sum;
-    *pErr++ = e;
-
-    /* Calculation of Weighting factor for updating filter coefficients */
-    /* epsilon value 0.000000119209289f */
-    w = (e * mu) / (energy + 0.000000119209289f);
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize pCcoeffs pointer */
-    pb = pCoeffs;
-
-    /* Loop over numTaps number of values */
-    tapCnt = numTaps;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      *pb += w * (*px++);
-      pb++;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    x0 = *pState;
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  S->energy = energy;
-  S->x0 = x0;
-
-  /* Processing is complete. Now copy the last numTaps - 1 samples to the        
-     satrt of the state buffer. This prepares the state buffer for the        
-     next function call. */
-
-  /* Points to the start of the pState buffer */
-  pStateCurnt = S->pState;
-
-  /* Copy (numTaps - 1u) samples  */
-  tapCnt = (numTaps - 1u);
-
-  /* Copy the remaining q31_t data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
-   * @} end of LMS_NORM group    
-   */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_f32.c
deleted file mode 100644
index 6b7b6289e7..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_f32.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_lms_norm_init_f32.c    
-*    
-* Description:  Floating-point NLMS filter initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup LMS_NORM    
- * @{    
- */
-
-  /**    
-   * @brief Initialization function for floating-point normalized LMS filter.    
-   * @param[in] *S points to an instance of the floating-point LMS filter structure.    
-   * @param[in] numTaps  number of filter coefficients.    
-   * @param[in] *pCoeffs points to coefficient buffer.    
-   * @param[in] *pState points to state buffer.    
-   * @param[in] mu step size that controls filter coefficient updates.    
-   * @param[in] blockSize number of samples to process.    
-   * @return none.    
-   *    
- * \par Description:    
- * pCoeffs points to the array of filter coefficients stored in time reversed order:    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * The initial filter coefficients serve as a starting point for the adaptive filter.    
- * pState points to an array of length numTaps+blockSize-1 samples,    
- * where blockSize is the number of input samples processed by each call to arm_lms_norm_f32().    
- */
-
-void arm_lms_norm_init_f32(
-  arm_lms_norm_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  float32_t mu,
-  uint32_t blockSize)
-{
-  /* Assign filter taps */
-  S->numTaps = numTaps;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and size is always blockSize + numTaps - 1 */
-  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-  /* Assign Step size value */
-  S->mu = mu;
-
-  /* Initialise Energy to zero */
-  S->energy = 0.0f;
-
-  /* Initialise x0 to zero */
-  S->x0 = 0.0f;
-
-}
-
-/**    
- * @} end of LMS_NORM group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q15.c
deleted file mode 100644
index a70e97bffa..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q15.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_lms_norm_init_q15.c    
-*    
-* Description:  Q15 NLMS initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**    
- * @addtogroup LMS_NORM    
- * @{    
- */
-
-  /**    
-   * @brief Initialization function for Q15 normalized LMS filter.    
-   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.    
-   * @param[in] numTaps  number of filter coefficients.    
-   * @param[in] *pCoeffs points to coefficient buffer.    
-   * @param[in] *pState points to state buffer.    
-   * @param[in] mu step size that controls filter coefficient updates.    
-   * @param[in] blockSize number of samples to process.    
-   * @param[in] postShift bit shift applied to coefficients.    
-   * @return none.    
- *    
- * Description:    
- * \par    
- * pCoeffs points to the array of filter coefficients stored in time reversed order:    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * The initial filter coefficients serve as a starting point for the adaptive filter.    
- * pState points to the array of state variables and size of array is    
- * numTaps+blockSize-1 samples, where blockSize is the number of input samples processed    
- * by each call to arm_lms_norm_q15().    
- */
-
-void arm_lms_norm_init_q15(
-  arm_lms_norm_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  q15_t mu,
-  uint32_t blockSize,
-  uint8_t postShift)
-{
-  /* Assign filter taps */
-  S->numTaps = numTaps;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and size is always blockSize + numTaps - 1 */
-  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
-
-  /* Assign post Shift value applied to coefficients */
-  S->postShift = postShift;
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-  /* Assign Step size value */
-  S->mu = mu;
-
-  /* Initialize reciprocal pointer table */
-  S->recipTable = (q15_t *) armRecipTableQ15;
-
-  /* Initialise Energy to zero */
-  S->energy = 0;
-
-  /* Initialise x0 to zero */
-  S->x0 = 0;
-
-}
-
-/**    
- * @} end of LMS_NORM group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q31.c
deleted file mode 100644
index b539ecf92c..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q31.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/*-----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_lms_norm_init_q31.c    
-*    
-* Description:  Q31 NLMS initialization function.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ---------------------------------------------------------------------------*/
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**    
- * @addtogroup LMS_NORM    
- * @{    
- */
-
-  /**    
-   * @brief Initialization function for Q31 normalized LMS filter.    
-   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.    
-   * @param[in] numTaps  number of filter coefficients.    
-   * @param[in] *pCoeffs points to coefficient buffer.    
-   * @param[in] *pState points to state buffer.    
-   * @param[in] mu step size that controls filter coefficient updates.    
-   * @param[in] blockSize number of samples to process.    
-   * @param[in] postShift bit shift applied to coefficients.    
-   * @return none.    
- *    
- * Description:    
- * \par    
- * pCoeffs points to the array of filter coefficients stored in time reversed order:    
- * 
    
- *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}    
- * 
    
- * The initial filter coefficients serve as a starting point for the adaptive filter.    
- * pState points to an array of length numTaps+blockSize-1 samples,    
- * where blockSize is the number of input samples processed by each call to arm_lms_norm_q31().    
- */
-
-void arm_lms_norm_init_q31(
-  arm_lms_norm_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  q31_t mu,
-  uint32_t blockSize,
-  uint8_t postShift)
-{
-  /* Assign filter taps */
-  S->numTaps = numTaps;
-
-  /* Assign coefficient pointer */
-  S->pCoeffs = pCoeffs;
-
-  /* Clear state buffer and size is always blockSize + numTaps - 1  */
-  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q31_t));
-
-  /* Assign post Shift value applied to coefficients */
-  S->postShift = postShift;
-
-  /* Assign state pointer */
-  S->pState = pState;
-
-  /* Assign Step size value */
-  S->mu = mu;
-
-  /* Initialize reciprocal pointer table */
-  S->recipTable = (q31_t *) armRecipTableQ31;
-
-  /* Initialise Energy to zero */
-  S->energy = 0;
-
-  /* Initialise x0 to zero */
-  S->x0 = 0;
-
-}
-
-/**    
- * @} end of LMS_NORM group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q15.c
deleted file mode 100644
index 13f36a066c..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q15.c
+++ /dev/null
@@ -1,435 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_lms_norm_q15.c    
-*    
-* Description:	Q15 NLMS filter.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup LMS_NORM    
- * @{    
- */
-
-/**    
-* @brief Processing function for Q15 normalized LMS filter.    
-* @param[in] *S points to an instance of the Q15 normalized LMS filter structure.    
-* @param[in] *pSrc points to the block of input data.    
-* @param[in] *pRef points to the block of reference data.    
-* @param[out] *pOut points to the block of output data.    
-* @param[out] *pErr points to the block of error data.    
-* @param[in] blockSize number of samples to process.    
-* @return none.    
-*    
-* Scaling and Overflow Behavior:     
-* \par     
-* The function is implemented using a 64-bit internal accumulator.     
-* Both coefficients and state variables are represented in 1.15 format and    
-* multiplications yield a 2.30 result. The 2.30 intermediate results are    
-* accumulated in a 64-bit accumulator in 34.30 format.     
-* There is no risk of internal overflow with this approach and the full    
-* precision of intermediate multiplications is preserved. After all additions    
-* have been performed, the accumulator is truncated to 34.15 format by    
-* discarding low 15 bits. Lastly, the accumulator is saturated to yield a    
-* result in 1.15 format.    
-*    
-* \par   
-* 	In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.    
-*    
- */
-
-void arm_lms_norm_q15(
-  arm_lms_norm_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pRef,
-  q15_t * pOut,
-  q15_t * pErr,
-  uint32_t blockSize)
-{
-  q15_t *pState = S->pState;                     /* State pointer */
-  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q15_t *px, *pb;                                /* Temporary pointers for state and coefficient buffers */
-  q15_t mu = S->mu;                              /* Adaptive factor */
-  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
-  uint32_t tapCnt, blkCnt;                       /* Loop counters */
-  q31_t energy;                                  /* Energy of the input */
-  q63_t acc;                                     /* Accumulator */
-  q15_t e = 0, d = 0;                            /* error, reference data sample */
-  q15_t w = 0, in;                               /* weight factor and state */
-  q15_t x0;                                      /* temporary variable to hold input sample */
-  //uint32_t shift = (uint32_t) S->postShift + 1u; /* Shift to be applied to the output */ 
-  q15_t errorXmu, oneByEnergy;                   /* Temporary variables to store error and mu product and reciprocal of energy */
-  q15_t postShift;                               /* Post shift to be applied to weight after reciprocal calculation */
-  q31_t coef;                                    /* Teporary variable for coefficient */
-  q31_t acc_l, acc_h;
-  int32_t lShift = (15 - (int32_t) S->postShift);       /*  Post shift  */
-  int32_t uShift = (32 - lShift);
-
-  energy = S->energy;
-  x0 = S->x0;
-
-  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  while(blkCnt > 0u)
-  {
-    /* Copy the new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc;
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = (pCoeffs);
-
-    /* Read the sample from input buffer */
-    in = *pSrc++;
-
-    /* Update the energy calculation */
-    energy -= (((q31_t) x0 * (x0)) >> 15);
-    energy += (((q31_t) in * (in)) >> 15);
-
-    /* Set the accumulator to zero */
-    acc = 0;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    while(tapCnt > 0u)
-    {
-
-      /* Perform the multiply-accumulate */
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
-      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
-
-#else
-
-      acc += (((q31_t) * px++ * (*pb++)));
-      acc += (((q31_t) * px++ * (*pb++)));
-      acc += (((q31_t) * px++ * (*pb++)));
-      acc += (((q31_t) * px++ * (*pb++)));
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      acc += (((q31_t) * px++ * (*pb++)));
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Calc lower part of acc */
-    acc_l = acc & 0xffffffff;
-
-    /* Calc upper part of acc */
-    acc_h = (acc >> 32) & 0xffffffff;
-
-    /* Apply shift for lower part of acc and upper part of acc */
-    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-    /* Converting the result to 1.15 format and saturate the output */
-    acc = __SSAT(acc, 16u);
-
-    /* Store the result from accumulator into the destination buffer. */
-    *pOut++ = (q15_t) acc;
-
-    /* Compute and store error */
-    d = *pRef++;
-    e = d - (q15_t) acc;
-    *pErr++ = e;
-
-    /* Calculation of 1/energy */
-    postShift = arm_recip_q15((q15_t) energy + DELTA_Q15,
-                              &oneByEnergy, S->recipTable);
-
-    /* Calculation of e * mu value */
-    errorXmu = (q15_t) (((q31_t) e * mu) >> 15);
-
-    /* Calculation of (e * mu) * (1/energy) value */
-    acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift));
-
-    /* Weighting factor for the normalized version */
-    w = (q15_t) __SSAT((q31_t) acc, 16);
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = (pCoeffs);
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Update filter coefficients */
-    while(tapCnt > 0u)
-    {
-      coef = *pb + (((q31_t) w * (*px++)) >> 15);
-      *pb++ = (q15_t) __SSAT((coef), 16);
-      coef = *pb + (((q31_t) w * (*px++)) >> 15);
-      *pb++ = (q15_t) __SSAT((coef), 16);
-      coef = *pb + (((q31_t) w * (*px++)) >> 15);
-      *pb++ = (q15_t) __SSAT((coef), 16);
-      coef = *pb + (((q31_t) w * (*px++)) >> 15);
-      *pb++ = (q15_t) __SSAT((coef), 16);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      coef = *pb + (((q31_t) w * (*px++)) >> 15);
-      *pb++ = (q15_t) __SSAT((coef), 16);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Read the sample from state buffer */
-    x0 = *pState;
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Save energy and x0 values for the next frame */
-  S->energy = (q15_t) energy;
-  S->x0 = x0;
-
-  /* Processing is complete. Now copy the last numTaps - 1 samples to the    
-     satrt of the state buffer. This prepares the state buffer for the    
-     next function call. */
-
-  /* Points to the start of the pState buffer */
-  pStateCurnt = S->pState;
-
-  /* Calculation of count for copying integer writes */
-  tapCnt = (numTaps - 1u) >> 2;
-
-  while(tapCnt > 0u)
-  {
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-
-#else
-
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-#endif
-
-    tapCnt--;
-
-  }
-
-  /* Calculation of count for remaining q15_t data */
-  tapCnt = (numTaps - 1u) % 0x4u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  while(blkCnt > 0u)
-  {
-    /* Copy the new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc;
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize pCoeffs pointer */
-    pb = pCoeffs;
-
-    /* Read the sample from input buffer */
-    in = *pSrc++;
-
-    /* Update the energy calculation */
-    energy -= (((q31_t) x0 * (x0)) >> 15);
-    energy += (((q31_t) in * (in)) >> 15);
-
-    /* Set the accumulator to zero */
-    acc = 0;
-
-    /* Loop over numTaps number of values */
-    tapCnt = numTaps;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      acc += (((q31_t) * px++ * (*pb++)));
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Calc lower part of acc */
-    acc_l = acc & 0xffffffff;
-
-    /* Calc upper part of acc */
-    acc_h = (acc >> 32) & 0xffffffff;
-
-    /* Apply shift for lower part of acc and upper part of acc */
-    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-    /* Converting the result to 1.15 format and saturate the output */
-    acc = __SSAT(acc, 16u);
-
-    /* Converting the result to 1.15 format */
-    //acc = __SSAT((acc >> (16u - shift)), 16u); 
-
-    /* Store the result from accumulator into the destination buffer. */
-    *pOut++ = (q15_t) acc;
-
-    /* Compute and store error */
-    d = *pRef++;
-    e = d - (q15_t) acc;
-    *pErr++ = e;
-
-    /* Calculation of 1/energy */
-    postShift = arm_recip_q15((q15_t) energy + DELTA_Q15,
-                              &oneByEnergy, S->recipTable);
-
-    /* Calculation of e * mu value */
-    errorXmu = (q15_t) (((q31_t) e * mu) >> 15);
-
-    /* Calculation of (e * mu) * (1/energy) value */
-    acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift));
-
-    /* Weighting factor for the normalized version */
-    w = (q15_t) __SSAT((q31_t) acc, 16);
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = (pCoeffs);
-
-    /* Loop over numTaps number of values */
-    tapCnt = numTaps;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      coef = *pb + (((q31_t) w * (*px++)) >> 15);
-      *pb++ = (q15_t) __SSAT((coef), 16);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Read the sample from state buffer */
-    x0 = *pState;
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Save energy and x0 values for the next frame */
-  S->energy = (q15_t) energy;
-  S->x0 = x0;
-
-  /* Processing is complete. Now copy the last numTaps - 1 samples to the        
-     satrt of the state buffer. This prepares the state buffer for the        
-     next function call. */
-
-  /* Points to the start of the pState buffer */
-  pStateCurnt = S->pState;
-
-  /* copy (numTaps - 1u) data */
-  tapCnt = (numTaps - 1u);
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0 */
-
-}
-
-
-/**    
-   * @} end of LMS_NORM group    
-   */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q31.c
deleted file mode 100644
index fee7015b0b..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q31.c
+++ /dev/null
@@ -1,426 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_lms_norm_q31.c    
-*    
-* Description:	Processing function for the Q31 NLMS filter.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup LMS_NORM    
- * @{    
- */
-
-/**    
-* @brief Processing function for Q31 normalized LMS filter.    
-* @param[in] *S points to an instance of the Q31 normalized LMS filter structure.    
-* @param[in] *pSrc points to the block of input data.    
-* @param[in] *pRef points to the block of reference data.    
-* @param[out] *pOut points to the block of output data.    
-* @param[out] *pErr points to the block of error data.    
-* @param[in] blockSize number of samples to process.    
-* @return none.    
-*    
-* Scaling and Overflow Behavior:     
-* \par     
-* The function is implemented using an internal 64-bit accumulator.     
-* The accumulator has a 2.62 format and maintains full precision of the intermediate   
-* multiplication results but provides only a single guard bit.     
-* Thus, if the accumulator result overflows it wraps around rather than clip.     
-* In order to avoid overflows completely the input signal must be scaled down by    
-* log2(numTaps) bits. The reference signal should not be scaled down.     
-* After all multiply-accumulates are performed, the 2.62 accumulator is shifted    
-* and saturated to 1.31 format to yield the final result.     
-* The output signal and error signal are in 1.31 format.     
-*    
-* \par    
-* 	In this filter, filter coefficients are updated for each sample and the    
-* updation of filter cofficients are saturted.    
-*     
-*/
-
-void arm_lms_norm_q31(
-  arm_lms_norm_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pRef,
-  q31_t * pOut,
-  q31_t * pErr,
-  uint32_t blockSize)
-{
-  q31_t *pState = S->pState;                     /* State pointer */
-  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q31_t *px, *pb;                                /* Temporary pointers for state and coefficient buffers */
-  q31_t mu = S->mu;                              /* Adaptive factor */
-  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
-  uint32_t tapCnt, blkCnt;                       /* Loop counters */
-  q63_t energy;                                  /* Energy of the input */
-  q63_t acc;                                     /* Accumulator */
-  q31_t e = 0, d = 0;                            /* error, reference data sample */
-  q31_t w = 0, in;                               /* weight factor and state */
-  q31_t x0;                                      /* temporary variable to hold input sample */
-//  uint32_t shift = 32u - ((uint32_t) S->postShift + 1u);        /* Shift to be applied to the output */      
-  q31_t errorXmu, oneByEnergy;                   /* Temporary variables to store error and mu product and reciprocal of energy */
-  q31_t postShift;                               /* Post shift to be applied to weight after reciprocal calculation */
-  q31_t coef;                                    /* Temporary variable for coef */
-  q31_t acc_l, acc_h;                            /*  temporary input */
-  uint32_t uShift = ((uint32_t) S->postShift + 1u);
-  uint32_t lShift = 32u - uShift;                /*  Shift to be applied to the output */
-
-  energy = S->energy;
-  x0 = S->x0;
-
-  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  while(blkCnt > 0u)
-  {
-
-    /* Copy the new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc;
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = (pCoeffs);
-
-    /* Read the sample from input buffer */
-    in = *pSrc++;
-
-    /* Update the energy calculation */
-    energy = (q31_t) ((((q63_t) energy << 32) -
-                       (((q63_t) x0 * x0) << 1)) >> 32);
-    energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32);
-
-    /* Set the accumulator to zero */
-    acc = 0;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      acc += ((q63_t) (*px++)) * (*pb++);
-      acc += ((q63_t) (*px++)) * (*pb++);
-      acc += ((q63_t) (*px++)) * (*pb++);
-      acc += ((q63_t) (*px++)) * (*pb++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      acc += ((q63_t) (*px++)) * (*pb++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Converting the result to 1.31 format */
-    /* Calc lower part of acc */
-    acc_l = acc & 0xffffffff;
-
-    /* Calc upper part of acc */
-    acc_h = (acc >> 32) & 0xffffffff;
-
-    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-    /* Store the result from accumulator into the destination buffer. */
-    *pOut++ = (q31_t) acc;
-
-    /* Compute and store error */
-    d = *pRef++;
-    e = d - (q31_t) acc;
-    *pErr++ = e;
-
-    /* Calculates the reciprocal of energy */
-    postShift = arm_recip_q31(energy + DELTA_Q31,
-                              &oneByEnergy, &S->recipTable[0]);
-
-    /* Calculation of product of (e * mu) */
-    errorXmu = (q31_t) (((q63_t) e * mu) >> 31);
-
-    /* Weighting factor for the normalized version */
-    w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift));
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = (pCoeffs);
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Update filter coefficients */
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-
-      /* coef is in 2.30 format */
-      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
-      /* get coef in 1.31 format by left shifting */
-      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
-      /* update coefficient buffer to next coefficient */
-      pb++;
-
-      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
-      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
-      pb++;
-
-      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
-      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
-      pb++;
-
-      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
-      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
-      pb++;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
-      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
-      pb++;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Read the sample from state buffer */
-    x0 = *pState;
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Save energy and x0 values for the next frame */
-  S->energy = (q31_t) energy;
-  S->x0 = x0;
-
-  /* Processing is complete. Now copy the last numTaps - 1 samples to the    
-     satrt of the state buffer. This prepares the state buffer for the    
-     next function call. */
-
-  /* Points to the start of the pState buffer */
-  pStateCurnt = S->pState;
-
-  /* Loop unrolling for (numTaps - 1u) samples copy */
-  tapCnt = (numTaps - 1u) >> 2u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-  /* Calculate remaining number of copies */
-  tapCnt = (numTaps - 1u) % 0x4u;
-
-  /* Copy the remaining q31_t data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  while(blkCnt > 0u)
-  {
-
-    /* Copy the new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc;
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize pCoeffs pointer */
-    pb = pCoeffs;
-
-    /* Read the sample from input buffer */
-    in = *pSrc++;
-
-    /* Update the energy calculation */
-    energy =
-      (q31_t) ((((q63_t) energy << 32) - (((q63_t) x0 * x0) << 1)) >> 32);
-    energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32);
-
-    /* Set the accumulator to zero */
-    acc = 0;
-
-    /* Loop over numTaps number of values */
-    tapCnt = numTaps;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      acc += ((q63_t) (*px++)) * (*pb++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Converting the result to 1.31 format */
-    /* Converting the result to 1.31 format */
-    /* Calc lower part of acc */
-    acc_l = acc & 0xffffffff;
-
-    /* Calc upper part of acc */
-    acc_h = (acc >> 32) & 0xffffffff;
-
-    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-
-    //acc = (q31_t) (acc >> shift); 
-
-    /* Store the result from accumulator into the destination buffer. */
-    *pOut++ = (q31_t) acc;
-
-    /* Compute and store error */
-    d = *pRef++;
-    e = d - (q31_t) acc;
-    *pErr++ = e;
-
-    /* Calculates the reciprocal of energy */
-    postShift =
-      arm_recip_q31(energy + DELTA_Q31, &oneByEnergy, &S->recipTable[0]);
-
-    /* Calculation of product of (e * mu) */
-    errorXmu = (q31_t) (((q63_t) e * mu) >> 31);
-
-    /* Weighting factor for the normalized version */
-    w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift));
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize coeff pointer */
-    pb = (pCoeffs);
-
-    /* Loop over numTaps number of values */
-    tapCnt = numTaps;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      /* coef is in 2.30 format */
-      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
-      /* get coef in 1.31 format by left shifting */
-      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
-      /* update coefficient buffer to next coefficient */
-      pb++;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Read the sample from state buffer */
-    x0 = *pState;
-
-    /* Advance state pointer by 1 for the next sample */
-    pState = pState + 1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Save energy and x0 values for the next frame */
-  S->energy = (q31_t) energy;
-  S->x0 = x0;
-
-  /* Processing is complete. Now copy the last numTaps - 1 samples to the     
-     start of the state buffer. This prepares the state buffer for the        
-     next function call. */
-
-  /* Points to the start of the pState buffer */
-  pStateCurnt = S->pState;
-
-  /* Loop for (numTaps - 1u) samples copy */
-  tapCnt = (numTaps - 1u);
-
-  /* Copy the remaining q31_t data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
- * @} end of LMS_NORM group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q15.c
deleted file mode 100644
index bb225d3c2e..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q15.c
+++ /dev/null
@@ -1,374 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_lms_q15.c    
-*    
-* Description:	Processing function for the Q15 LMS filter.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup LMS    
- * @{    
- */
-
- /**    
- * @brief Processing function for Q15 LMS filter.    
- * @param[in] *S points to an instance of the Q15 LMS filter structure.    
- * @param[in] *pSrc points to the block of input data.    
- * @param[in] *pRef points to the block of reference data.    
- * @param[out] *pOut points to the block of output data.    
- * @param[out] *pErr points to the block of error data.    
- * @param[in] blockSize number of samples to process.    
- * @return none.    
- *    
- * \par Scaling and Overflow Behavior:    
- * The function is implemented using a 64-bit internal accumulator.    
- * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.    
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.    
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.    
- * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.    
- * Lastly, the accumulator is saturated to yield a result in 1.15 format.    
- *   
- * \par   
- * 	In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.   
- *    
- */
-
-void arm_lms_q15(
-  const arm_lms_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pRef,
-  q15_t * pOut,
-  q15_t * pErr,
-  uint32_t blockSize)
-{
-  q15_t *pState = S->pState;                     /* State pointer */
-  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
-  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q15_t mu = S->mu;                              /* Adaptive factor */
-  q15_t *px;                                     /* Temporary pointer for state */
-  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */
-  uint32_t tapCnt, blkCnt;                       /* Loop counters */
-  q63_t acc;                                     /* Accumulator */
-  q15_t e = 0;                                   /* error of data sample */
-  q15_t alpha;                                   /* Intermediate constant for taps update */
-  q31_t acc_l, acc_h;
-  int32_t lShift = (15 - (int32_t) S->postShift);       /*  Post shift  */
-  int32_t uShift = (32 - lShift);
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t coef;                                    /* Teporary variable for coefficient */
-
-  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  /* Initializing blkCnt with blockSize */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* Copy the new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize coefficient pointer */
-    pb = pCoeffs;
-
-    /* Set the accumulator to zero */
-    acc = 0;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2u;
-
-    while(tapCnt > 0u)
-    {
-      /* acc +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */
-      /* Perform the multiply-accumulate */
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
-      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
-
-#else
-
-      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
-      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
-      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
-      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
-
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Calc lower part of acc */
-    acc_l = acc & 0xffffffff;
-
-    /* Calc upper part of acc */
-    acc_h = (acc >> 32) & 0xffffffff;
-
-    /* Apply shift for lower part of acc and upper part of acc */
-    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-    /* Converting the result to 1.15 format and saturate the output */
-    acc = __SSAT(acc, 16);
-
-    /* Store the result from accumulator into the destination buffer. */
-    *pOut++ = (q15_t) acc;
-
-    /* Compute and store error */
-    e = *pRef++ - (q15_t) acc;
-
-    *pErr++ = (q15_t) e;
-
-    /* Compute alpha i.e. intermediate constant for taps update */
-    alpha = (q15_t) (((q31_t) e * (mu)) >> 15);
-
-    /* Initialize state pointer */
-    /* Advance state pointer by 1 for the next sample */
-    px = pState++;
-
-    /* Initialize coefficient pointer */
-    pb = pCoeffs;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2u;
-
-    /* Update filter coefficients */
-    while(tapCnt > 0u)
-    {
-      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
-      *pb++ = (q15_t) __SSAT((coef), 16);
-      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
-      *pb++ = (q15_t) __SSAT((coef), 16);
-      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
-      *pb++ = (q15_t) __SSAT((coef), 16);
-      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
-      *pb++ = (q15_t) __SSAT((coef), 16);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
-      *pb++ = (q15_t) __SSAT((coef), 16);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Decrement the loop counter */
-    blkCnt--;
-
-  }
-
-  /* Processing is complete. Now copy the last numTaps - 1 samples to the    
-     satrt of the state buffer. This prepares the state buffer for the    
-     next function call. */
-
-  /* Points to the start of the pState buffer */
-  pStateCurnt = S->pState;
-
-  /* Calculation of count for copying integer writes */
-  tapCnt = (numTaps - 1u) >> 2;
-
-  while(tapCnt > 0u)
-  {
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
-#else
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-#endif
-
-    tapCnt--;
-
-  }
-
-  /* Calculation of count for remaining q15_t data */
-  tapCnt = (numTaps - 1u) % 0x4u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* Copy the new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize pCoeffs pointer */
-    pb = pCoeffs;
-
-    /* Set the accumulator to zero */
-    acc = 0;
-
-    /* Loop over numTaps number of values */
-    tapCnt = numTaps;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      acc += (q63_t) ((q31_t) (*px++) * (*pb++));
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Calc lower part of acc */
-    acc_l = acc & 0xffffffff;
-
-    /* Calc upper part of acc */
-    acc_h = (acc >> 32) & 0xffffffff;
-
-    /* Apply shift for lower part of acc and upper part of acc */
-    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-    /* Converting the result to 1.15 format and saturate the output */
-    acc = __SSAT(acc, 16);
-
-    /* Store the result from accumulator into the destination buffer. */
-    *pOut++ = (q15_t) acc;
-
-    /* Compute and store error */
-    e = *pRef++ - (q15_t) acc;
-
-    *pErr++ = (q15_t) e;
-
-    /* Compute alpha i.e. intermediate constant for taps update */
-    alpha = (q15_t) (((q31_t) e * (mu)) >> 15);
-
-    /* Initialize pState pointer */
-    /* Advance state pointer by 1 for the next sample */
-    px = pState++;
-
-    /* Initialize pCoeffs pointer */
-    pb = pCoeffs;
-
-    /* Loop over numTaps number of values */
-    tapCnt = numTaps;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      *pb++ += (q15_t) (((q31_t) alpha * (*px++)) >> 15);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Decrement the loop counter */
-    blkCnt--;
-
-  }
-
-  /* Processing is complete. Now copy the last numTaps - 1 samples to the        
-     start of the state buffer. This prepares the state buffer for the   
-     next function call. */
-
-  /* Points to the start of the pState buffer */
-  pStateCurnt = S->pState;
-
-  /*  Copy (numTaps - 1u) samples  */
-  tapCnt = (numTaps - 1u);
-
-  /* Copy the data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
-   * @} end of LMS group    
-   */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q31.c
deleted file mode 100644
index 96ae9ecf65..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q31.c
+++ /dev/null
@@ -1,364 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_lms_q31.c    
-*    
-* Description:	Processing function for the Q31 LMS filter.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-/**    
- * @ingroup groupFilters    
- */
-
-/**    
- * @addtogroup LMS    
- * @{    
- */
-
- /**    
- * @brief Processing function for Q31 LMS filter.    
- * @param[in]  *S points to an instance of the Q15 LMS filter structure.    
- * @param[in]  *pSrc points to the block of input data.    
- * @param[in]  *pRef points to the block of reference data.    
- * @param[out] *pOut points to the block of output data.    
- * @param[out] *pErr points to the block of error data.    
- * @param[in]  blockSize number of samples to process.    
- * @return     none.    
- *    
- * \par Scaling and Overflow Behavior:     
- * The function is implemented using an internal 64-bit accumulator.     
- * The accumulator has a 2.62 format and maintains full precision of the intermediate    
- * multiplication results but provides only a single guard bit.     
- * Thus, if the accumulator result overflows it wraps around rather than clips.     
- * In order to avoid overflows completely the input signal must be scaled down by    
- * log2(numTaps) bits.     
- * The reference signal should not be scaled down.     
- * After all multiply-accumulates are performed, the 2.62 accumulator is shifted    
- * and saturated to 1.31 format to yield the final result.     
- * The output signal and error signal are in 1.31 format.     
- *    
- * \par    
- * 	In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.    
- */
-
-void arm_lms_q31(
-  const arm_lms_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pRef,
-  q31_t * pOut,
-  q31_t * pErr,
-  uint32_t blockSize)
-{
-  q31_t *pState = S->pState;                     /* State pointer */
-  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
-  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
-  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
-  q31_t mu = S->mu;                              /* Adaptive factor */
-  q31_t *px;                                     /* Temporary pointer for state */
-  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
-  uint32_t tapCnt, blkCnt;                       /* Loop counters */
-  q63_t acc;                                     /* Accumulator */
-  q31_t e = 0;                                   /* error of data sample */
-  q31_t alpha;                                   /* Intermediate constant for taps update */
-  q31_t coef;                                    /* Temporary variable for coef */
-  q31_t acc_l, acc_h;                            /*  temporary input */
-  uint32_t uShift = ((uint32_t) S->postShift + 1u);
-  uint32_t lShift = 32u - uShift;                /*  Shift to be applied to the output */
-
-  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
-  /* pStateCurnt points to the location where the new input data should be written */
-  pStateCurnt = &(S->pState[(numTaps - 1u)]);
-
-  /* Initializing blkCnt with blockSize */
-  blkCnt = blockSize;
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  while(blkCnt > 0u)
-  {
-    /* Copy the new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Initialize state pointer */
-    px = pState;
-
-    /* Initialize coefficient pointer */
-    pb = pCoeffs;
-
-    /* Set the accumulator to zero */
-    acc = 0;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      /* acc +=  b[N] * x[n-N] */
-      acc += ((q63_t) (*px++)) * (*pb++);
-
-      /* acc +=  b[N-1] * x[n-N-1] */
-      acc += ((q63_t) (*px++)) * (*pb++);
-
-      /* acc +=  b[N-2] * x[n-N-2] */
-      acc += ((q63_t) (*px++)) * (*pb++);
-
-      /* acc +=  b[N-3] * x[n-N-3] */
-      acc += ((q63_t) (*px++)) * (*pb++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      acc += ((q63_t) (*px++)) * (*pb++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Converting the result to 1.31 format */
-    /* Calc lower part of acc */
-    acc_l = acc & 0xffffffff;
-
-    /* Calc upper part of acc */
-    acc_h = (acc >> 32) & 0xffffffff;
-
-    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-    /* Store the result from accumulator into the destination buffer. */
-    *pOut++ = (q31_t) acc;
-
-    /* Compute and store error */
-    e = *pRef++ - (q31_t) acc;
-
-    *pErr++ = (q31_t) e;
-
-    /* Compute alpha i.e. intermediate constant for taps update */
-    alpha = (q31_t) (((q63_t) e * mu) >> 31);
-
-    /* Initialize state pointer */
-    /* Advance state pointer by 1 for the next sample */
-    px = pState++;
-
-    /* Initialize coefficient pointer */
-    pb = pCoeffs;
-
-    /* Loop unrolling.  Process 4 taps at a time. */
-    tapCnt = numTaps >> 2;
-
-    /* Update filter coefficients */
-    while(tapCnt > 0u)
-    {
-      /* coef is in 2.30 format */
-      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
-      /* get coef in 1.31 format by left shifting */
-      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
-      /* update coefficient buffer to next coefficient */
-      pb++;
-
-      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
-      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
-      pb++;
-
-      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
-      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
-      pb++;
-
-      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
-      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
-      pb++;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
-    tapCnt = numTaps % 0x4u;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
-      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
-      pb++;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete. Now copy the last numTaps - 1 samples to the    
-     satrt of the state buffer. This prepares the state buffer for the    
-     next function call. */
-
-  /* Points to the start of the pState buffer */
-  pStateCurnt = S->pState;
-
-  /* Loop unrolling for (numTaps - 1u) samples copy */
-  tapCnt = (numTaps - 1u) >> 2u;
-
-  /* copy data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
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-  }
-
-  /* Calculate remaining number of copies */
-  tapCnt = (numTaps - 1u) % 0x4u;
-
-  /* Copy the remaining q31_t data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  while(blkCnt > 0u)
-  {
-    /* Copy the new input sample into the state buffer */
-    *pStateCurnt++ = *pSrc++;
-
-    /* Initialize pState pointer */
-    px = pState;
-
-    /* Initialize pCoeffs pointer */
-    pb = pCoeffs;
-
-    /* Set the accumulator to zero */
-    acc = 0;
-
-    /* Loop over numTaps number of values */
-    tapCnt = numTaps;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      acc += ((q63_t) (*px++)) * (*pb++);
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Converting the result to 1.31 format */
-    /* Store the result from accumulator into the destination buffer. */
-    /* Calc lower part of acc */
-    acc_l = acc & 0xffffffff;
-
-    /* Calc upper part of acc */
-    acc_h = (acc >> 32) & 0xffffffff;
-
-    acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
-
-    *pOut++ = (q31_t) acc;
-
-    /* Compute and store error */
-    e = *pRef++ - (q31_t) acc;
-
-    *pErr++ = (q31_t) e;
-
-    /* Weighting factor for the LMS version */
-    alpha = (q31_t) (((q63_t) e * mu) >> 31);
-
-    /* Initialize pState pointer */
-    /* Advance state pointer by 1 for the next sample */
-    px = pState++;
-
-    /* Initialize pCoeffs pointer */
-    pb = pCoeffs;
-
-    /* Loop over numTaps number of values */
-    tapCnt = numTaps;
-
-    while(tapCnt > 0u)
-    {
-      /* Perform the multiply-accumulate */
-      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
-      *pb += (coef << 1u);
-      pb++;
-
-      /* Decrement the loop counter */
-      tapCnt--;
-    }
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Processing is complete. Now copy the last numTaps - 1 samples to the     
-     start of the state buffer. This prepares the state buffer for the   
-     next function call. */
-
-  /* Points to the start of the pState buffer */
-  pStateCurnt = S->pState;
-
-  /*  Copy (numTaps - 1u) samples  */
-  tapCnt = (numTaps - 1u);
-
-  /* Copy the data */
-  while(tapCnt > 0u)
-  {
-    *pStateCurnt++ = *pState++;
-
-    /* Decrement the loop counter */
-    tapCnt--;
-  }
-
-#endif /*   #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
-   * @} end of LMS group    
-   */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/G++/arm_cortexM0x_math.uvopt b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/G++/arm_cortexM0x_math.uvopt
deleted file mode 100644
index 0740c1eb79..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/G++/arm_cortexM0x_math.uvopt
+++ /dev/null
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diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/G++/arm_cortexM0x_math.uvproj b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/G++/arm_cortexM0x_math.uvproj
deleted file mode 100644
index 6c370a47d6..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/G++/arm_cortexM0x_math.uvproj
+++ /dev/null
@@ -1,3253 +0,0 @@
-
-
-
-  1.1
-
-  
### uVision Project, (C) Keil Software

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-              1
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-        
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-              1
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-            
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-              1
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-              1
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-              1
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-        
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-              1
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-        
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-              1
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diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/G++/arm_cortexM3x_math.uvopt b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/G++/arm_cortexM3x_math.uvopt
deleted file mode 100644
index b56521505e..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/G++/arm_cortexM3x_math.uvopt
+++ /dev/null
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diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/G++/arm_cortexM3x_math.uvproj b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/G++/arm_cortexM3x_math.uvproj
deleted file mode 100644
index 6ace95fc32..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/G++/arm_cortexM3x_math.uvproj
+++ /dev/null
@@ -1,3253 +0,0 @@
-
-
-
-  1.1
-
-  
### uVision Project, (C) Keil Software

-
-  
-    
-      DSP_Lib CM3 LE
-      0x3
-      ARM-GNU
-      
-        
-          Cortex-M3
-          ARM
-          CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE
-          
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-          
-          4349
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diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/G++/arm_cortexM4x_math.uvopt b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/G++/arm_cortexM4x_math.uvopt
deleted file mode 100644
index 84e27482e5..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/G++/arm_cortexM4x_math.uvopt
+++ /dev/null
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diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/G++/arm_cortexM4x_math.uvproj b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/G++/arm_cortexM4x_math.uvproj
deleted file mode 100644
index 3c2a5e6adb..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/G++/arm_cortexM4x_math.uvproj
+++ /dev/null
@@ -1,6495 +0,0 @@
-
-
-
-  1.1
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-  
### uVision Project, (C) Keil Software

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-            
-            
-              arm_mat_mult_q31.c
-              1
-              ../MatrixFunctions/arm_mat_mult_q31.c
-            
-            
-              arm_mat_scale_f32.c
-              1
-              ../MatrixFunctions/arm_mat_scale_f32.c
-            
-            
-              arm_mat_scale_q15.c
-              1
-              ../MatrixFunctions/arm_mat_scale_q15.c
-            
-            
-              arm_mat_scale_q31.c
-              1
-              ../MatrixFunctions/arm_mat_scale_q31.c
-            
-            
-              arm_mat_sub_f32.c
-              1
-              ../MatrixFunctions/arm_mat_sub_f32.c
-            
-            
-              arm_mat_sub_q15.c
-              1
-              ../MatrixFunctions/arm_mat_sub_q15.c
-            
-            
-              arm_mat_sub_q31.c
-              1
-              ../MatrixFunctions/arm_mat_sub_q31.c
-            
-            
-              arm_mat_trans_f32.c
-              1
-              ../MatrixFunctions/arm_mat_trans_f32.c
-            
-            
-              arm_mat_trans_q15.c
-              1
-              ../MatrixFunctions/arm_mat_trans_q15.c
-            
-            
-              arm_mat_trans_q31.c
-              1
-              ../MatrixFunctions/arm_mat_trans_q31.c
-            
-          
-        
-        
-          TransformFunctions
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-            
-              arm_bitreversal.c
-              1
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-            
-              arm_cfft_radix2_f32.c
-              1
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-            
-              arm_cfft_radix2_init_f32.c
-              1
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-            
-              arm_cfft_radix2_init_q15.c
-              1
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-            
-              arm_cfft_radix2_init_q31.c
-              1
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-            
-              arm_cfft_radix2_q15.c
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-            
-              arm_cfft_radix2_q31.c
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-            
-            
-              arm_cfft_radix4_f32.c
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-            
-              arm_cfft_radix4_init_f32.c
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-            
-              arm_cfft_radix4_init_q15.c
-              1
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-            
-              arm_cfft_radix4_init_q31.c
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-            
-              arm_cfft_radix4_q15.c
-              1
-              ../TransformFunctions/arm_cfft_radix4_q15.c
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-            
-              arm_cfft_radix4_q31.c
-              1
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-            
-            
-              arm_dct4_f32.c
-              1
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-            
-            
-              arm_dct4_init_f32.c
-              1
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-            
-              arm_dct4_init_q15.c
-              1
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-            
-            
-              arm_dct4_init_q31.c
-              1
-              ../TransformFunctions/arm_dct4_init_q31.c
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-            
-              arm_dct4_q15.c
-              1
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-            
-              arm_dct4_q31.c
-              1
-              ../TransformFunctions/arm_dct4_q31.c
-            
-            
-              arm_rfft_f32.c
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-            
-              arm_rfft_init_f32.c
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-            
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-            
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-            
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-            
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-              arm_common_tables.c
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diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/G++/arm_cortexMx_math_Build.bat b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/G++/arm_cortexMx_math_Build.bat
deleted file mode 100644
index 007812c2d0..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/G++/arm_cortexMx_math_Build.bat
+++ /dev/null
@@ -1,17 +0,0 @@
-
-SET TMP=C:\Temp
-SET TEMP=C:\Temp
-
-SET UVEXE=C:\Keil\UV4\UV4.EXE
-
-@echo   Building DSP Library for Cortex-M0 Little Endian
-%UVEXE% -rb arm_cortexM0x_math.uvproj -t"DSP_Lib CM0 LE" -o"DSP_Lib CM0 LE.txt" -j0
-
-@echo   Building DSP Library for Cortex-M3 Little Endian
-%UVEXE% -rb arm_cortexM3x_math.uvproj -t"DSP_Lib CM3 LE" -o"DSP_Lib CM3 LE.txt" -j0
-
-@echo   Building DSP Library for Cortex-M4 Little Endian
-%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 LE" -o"DSP_Lib CM4 LE.txt" -j0
-
-@echo   Building DSP Library for Cortex-M4 with FPU Little Endian
-%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 LE FPU" -o"DSP_Lib CM4 LE FPU.txt" -j0
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/GCC/arm_cortexM0x_math.uvopt b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/GCC/arm_cortexM0x_math.uvopt
deleted file mode 100644
index 6ecf373652..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/GCC/arm_cortexM0x_math.uvopt
+++ /dev/null
@@ -1,3937 +0,0 @@
-
-
-
-  1.0
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### uVision Project, (C) Keil Software

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diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/GCC/arm_cortexM0x_math.uvproj b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/GCC/arm_cortexM0x_math.uvproj
deleted file mode 100644
index dfdbbd51b6..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/GCC/arm_cortexM0x_math.uvproj
+++ /dev/null
@@ -1,3253 +0,0 @@
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-          TransformFunctions
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diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/GCC/arm_cortexM3x_math.uvopt b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/GCC/arm_cortexM3x_math.uvopt
deleted file mode 100644
index 8e5a82fd8e..0000000000
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+++ /dev/null
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diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/GCC/arm_cortexM3x_math.uvproj b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/GCC/arm_cortexM3x_math.uvproj
deleted file mode 100644
index a32c386769..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/GCC/arm_cortexM3x_math.uvproj
+++ /dev/null
@@ -1,3253 +0,0 @@
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-              arm_lms_norm_f32.c
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-          
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-          MatrixFunctions
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-              1
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-              arm_mat_scale_f32.c
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-              1
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-              arm_rfft_init_q15.c
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-          
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-          
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-              arm_pid_init_f32.c
-              1
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-              arm_pid_init_q15.c
-              1
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-              arm_pid_init_q31.c
-              1
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-              arm_pid_reset_f32.c
-              1
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-              arm_pid_reset_q15.c
-              1
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-              1
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-              arm_sin_cos_f32.c
-              1
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-              1
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-          
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-        
-          StatisticsFunctions
-          
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-              1
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-              arm_max_q7.c
-              1
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-              arm_max_q15.c
-              1
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-              arm_max_q31.c
-              1
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-              arm_mean_f32.c
-              1
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-              arm_mean_q7.c
-              1
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-              arm_mean_q15.c
-              1
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-              arm_mean_q31.c
-              1
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-              arm_min_f32.c
-              1
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-              arm_min_q7.c
-              1
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-              arm_min_q15.c
-              1
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-              arm_min_q31.c
-              1
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-              arm_power_f32.c
-              1
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-              arm_power_q7.c
-              1
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-              arm_power_q15.c
-              1
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-              arm_power_q31.c
-              1
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-              arm_rms_f32.c
-              1
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-              arm_rms_q15.c
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-              arm_std_f32.c
-              1
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-              arm_std_q15.c
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-              arm_var_q15.c
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-              arm_var_q31.c
-              1
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-        
-        
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-          
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-              arm_copy_f32.c
-              1
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-              arm_copy_q7.c
-              1
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-              arm_copy_q15.c
-              1
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-              arm_copy_q31.c
-              1
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-              arm_fill_f32.c
-              1
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-              arm_fill_q7.c
-              1
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-              arm_fill_q15.c
-              1
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-              arm_fill_q31.c
-              1
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-              arm_float_to_q7.c
-              1
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-              arm_float_to_q15.c
-              1
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-              arm_float_to_q31.c
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-              arm_q7_to_float.c
-              1
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-              arm_q7_to_q15.c
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-              arm_q7_to_q31.c
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-              arm_q15_to_float.c
-              1
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-              arm_q15_to_q7.c
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-              arm_q15_to_q31.c
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-              arm_q31_to_float.c
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-              arm_q31_to_q7.c
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-              arm_q31_to_q15.c
-              1
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-          CommonTables
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-              arm_common_tables.c
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diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/GCC/arm_cortexM4x_math.uvopt b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/GCC/arm_cortexM4x_math.uvopt
deleted file mode 100644
index 9201baab89..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/GCC/arm_cortexM4x_math.uvopt
+++ /dev/null
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diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/GCC/arm_cortexM4x_math.uvproj b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/GCC/arm_cortexM4x_math.uvproj
deleted file mode 100644
index ad55fd5688..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/GCC/arm_cortexM4x_math.uvproj
+++ /dev/null
@@ -1,6495 +0,0 @@
-
-
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-  1.1
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-  
### uVision Project, (C) Keil Software

-
-  
-    
-      DSP_Lib CM4 LE
-      0x3
-      ARM-GNU
-      
-        
-          Cortex-M4
-          ARM
-          CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE
-          
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-          
-          5125
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-            
-            
-            0
-            0
-          
-          
-            1
-            0
-            cmd.exe /C copy ".\intermediateFiles\lib@L.a" "..\..\..\Lib\GCC\"
-            
-            0
-            0
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-          0
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-        
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-          0
-          0
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-          0
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-          1
-          0
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-          0
-          0
-          3
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-          
-        
-        
-          SARMCM3.DLL
-          
-          DCM.DLL
-          -pCM4
-          SARMCM3.DLL
-          
-          TCM.DLL
-          -pCM4
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-          
-            1
-            0
-            0
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-            16
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-            1
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-              
-                0
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-                0
-                0x0
-                0x0
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-                0
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-                0
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-            
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-            0
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-            5
-            2
-            1
-            
-              -mcpu=cortex-m4 -fno-strict-aliasing -ffunction-sections
-              ARM_MATH_CM4, ARM_MATH_MATRIX_CHECK, ARM_MATH_ROUNDING, UNALIGNED_SUPPORT_DISABLE
-              
-              ..\..\..\Include
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-            
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-            
-            -mcpu=cortex-m4 -Wl,--gc-sections
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-            
-              arm_shift_q31.c
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-            
-              arm_sqrt_q31.c
-              1
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-        
-          ComplexMathFunctions
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-              arm_cmplx_conj_f32.c
-              1
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-          TransformFunctions
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-            
-            
-              arm_fir_f32.c
-              1
-              ../FilteringFunctions/arm_fir_f32.c
-            
-            
-              arm_fir_fast_q15.c
-              1
-              ../FilteringFunctions/arm_fir_fast_q15.c
-            
-            
-              arm_fir_fast_q31.c
-              1
-              ../FilteringFunctions/arm_fir_fast_q31.c
-            
-            
-              arm_fir_init_f32.c
-              1
-              ../FilteringFunctions/arm_fir_init_f32.c
-            
-            
-              arm_fir_init_q7.c
-              1
-              ../FilteringFunctions/arm_fir_init_q7.c
-            
-            
-              arm_fir_init_q15.c
-              1
-              ../FilteringFunctions/arm_fir_init_q15.c
-            
-            
-              arm_fir_init_q31.c
-              1
-              ../FilteringFunctions/arm_fir_init_q31.c
-            
-            
-              arm_fir_interpolate_f32.c
-              1
-              ../FilteringFunctions/arm_fir_interpolate_f32.c
-            
-            
-              arm_fir_interpolate_init_f32.c
-              1
-              ../FilteringFunctions/arm_fir_interpolate_init_f32.c
-            
-            
-              arm_fir_interpolate_init_q15.c
-              1
-              ../FilteringFunctions/arm_fir_interpolate_init_q15.c
-            
-            
-              arm_fir_interpolate_init_q31.c
-              1
-              ../FilteringFunctions/arm_fir_interpolate_init_q31.c
-            
-            
-              arm_fir_interpolate_q15.c
-              1
-              ../FilteringFunctions/arm_fir_interpolate_q15.c
-            
-            
-              arm_fir_interpolate_q31.c
-              1
-              ../FilteringFunctions/arm_fir_interpolate_q31.c
-            
-            
-              arm_fir_lattice_f32.c
-              1
-              ../FilteringFunctions/arm_fir_lattice_f32.c
-            
-            
-              arm_fir_lattice_init_f32.c
-              1
-              ../FilteringFunctions/arm_fir_lattice_init_f32.c
-            
-            
-              arm_fir_lattice_init_q15.c
-              1
-              ../FilteringFunctions/arm_fir_lattice_init_q15.c
-            
-            
-              arm_fir_lattice_init_q31.c
-              1
-              ../FilteringFunctions/arm_fir_lattice_init_q31.c
-            
-            
-              arm_fir_lattice_q15.c
-              1
-              ../FilteringFunctions/arm_fir_lattice_q15.c
-            
-            
-              arm_fir_lattice_q31.c
-              1
-              ../FilteringFunctions/arm_fir_lattice_q31.c
-            
-            
-              arm_fir_q7.c
-              1
-              ../FilteringFunctions/arm_fir_q7.c
-            
-            
-              arm_fir_q15.c
-              1
-              ../FilteringFunctions/arm_fir_q15.c
-            
-            
-              arm_fir_q31.c
-              1
-              ../FilteringFunctions/arm_fir_q31.c
-            
-            
-              arm_fir_sparse_f32.c
-              1
-              ../FilteringFunctions/arm_fir_sparse_f32.c
-            
-            
-              arm_fir_sparse_init_f32.c
-              1
-              ../FilteringFunctions/arm_fir_sparse_init_f32.c
-            
-            
-              arm_fir_sparse_init_q7.c
-              1
-              ../FilteringFunctions/arm_fir_sparse_init_q7.c
-            
-            
-              arm_fir_sparse_init_q15.c
-              1
-              ../FilteringFunctions/arm_fir_sparse_init_q15.c
-            
-            
-              arm_fir_sparse_init_q31.c
-              1
-              ../FilteringFunctions/arm_fir_sparse_init_q31.c
-            
-            
-              arm_fir_sparse_q7.c
-              1
-              ../FilteringFunctions/arm_fir_sparse_q7.c
-            
-            
-              arm_fir_sparse_q15.c
-              1
-              ../FilteringFunctions/arm_fir_sparse_q15.c
-            
-            
-              arm_fir_sparse_q31.c
-              1
-              ../FilteringFunctions/arm_fir_sparse_q31.c
-            
-            
-              arm_iir_lattice_f32.c
-              1
-              ../FilteringFunctions/arm_iir_lattice_f32.c
-            
-            
-              arm_iir_lattice_init_f32.c
-              1
-              ../FilteringFunctions/arm_iir_lattice_init_f32.c
-            
-            
-              arm_iir_lattice_init_q15.c
-              1
-              ../FilteringFunctions/arm_iir_lattice_init_q15.c
-            
-            
-              arm_iir_lattice_init_q31.c
-              1
-              ../FilteringFunctions/arm_iir_lattice_init_q31.c
-            
-            
-              arm_iir_lattice_q15.c
-              1
-              ../FilteringFunctions/arm_iir_lattice_q15.c
-            
-            
-              arm_iir_lattice_q31.c
-              1
-              ../FilteringFunctions/arm_iir_lattice_q31.c
-            
-            
-              arm_lms_f32.c
-              1
-              ../FilteringFunctions/arm_lms_f32.c
-            
-            
-              arm_lms_init_f32.c
-              1
-              ../FilteringFunctions/arm_lms_init_f32.c
-            
-            
-              arm_lms_init_q15.c
-              1
-              ../FilteringFunctions/arm_lms_init_q15.c
-            
-            
-              arm_lms_init_q31.c
-              1
-              ../FilteringFunctions/arm_lms_init_q31.c
-            
-            
-              arm_lms_norm_f32.c
-              1
-              ../FilteringFunctions/arm_lms_norm_f32.c
-            
-            
-              arm_lms_norm_init_f32.c
-              1
-              ../FilteringFunctions/arm_lms_norm_init_f32.c
-            
-            
-              arm_lms_norm_init_q15.c
-              1
-              ../FilteringFunctions/arm_lms_norm_init_q15.c
-            
-            
-              arm_lms_norm_init_q31.c
-              1
-              ../FilteringFunctions/arm_lms_norm_init_q31.c
-            
-            
-              arm_lms_norm_q15.c
-              1
-              ../FilteringFunctions/arm_lms_norm_q15.c
-            
-            
-              arm_lms_norm_q31.c
-              1
-              ../FilteringFunctions/arm_lms_norm_q31.c
-            
-            
-              arm_lms_q15.c
-              1
-              ../FilteringFunctions/arm_lms_q15.c
-            
-            
-              arm_lms_q31.c
-              1
-              ../FilteringFunctions/arm_lms_q31.c
-            
-          
-        
-        
-          MatrixFunctions
-          
-            
-              arm_mat_add_f32.c
-              1
-              ../MatrixFunctions/arm_mat_add_f32.c
-            
-            
-              arm_mat_add_q15.c
-              1
-              ../MatrixFunctions/arm_mat_add_q15.c
-            
-            
-              arm_mat_add_q31.c
-              1
-              ../MatrixFunctions/arm_mat_add_q31.c
-            
-            
-              arm_mat_init_f32.c
-              1
-              ../MatrixFunctions/arm_mat_init_f32.c
-            
-            
-              arm_mat_init_q15.c
-              1
-              ../MatrixFunctions/arm_mat_init_q15.c
-            
-            
-              arm_mat_init_q31.c
-              1
-              ../MatrixFunctions/arm_mat_init_q31.c
-            
-            
-              arm_mat_inverse_f32.c
-              1
-              ../MatrixFunctions/arm_mat_inverse_f32.c
-            
-            
-              arm_mat_mult_f32.c
-              1
-              ../MatrixFunctions/arm_mat_mult_f32.c
-            
-            
-              arm_mat_mult_fast_q15.c
-              1
-              ../MatrixFunctions/arm_mat_mult_fast_q15.c
-            
-            
-              arm_mat_mult_fast_q31.c
-              1
-              ../MatrixFunctions/arm_mat_mult_fast_q31.c
-            
-            
-              arm_mat_mult_q15.c
-              1
-              ../MatrixFunctions/arm_mat_mult_q15.c
-            
-            
-              arm_mat_mult_q31.c
-              1
-              ../MatrixFunctions/arm_mat_mult_q31.c
-            
-            
-              arm_mat_scale_f32.c
-              1
-              ../MatrixFunctions/arm_mat_scale_f32.c
-            
-            
-              arm_mat_scale_q15.c
-              1
-              ../MatrixFunctions/arm_mat_scale_q15.c
-            
-            
-              arm_mat_scale_q31.c
-              1
-              ../MatrixFunctions/arm_mat_scale_q31.c
-            
-            
-              arm_mat_sub_f32.c
-              1
-              ../MatrixFunctions/arm_mat_sub_f32.c
-            
-            
-              arm_mat_sub_q15.c
-              1
-              ../MatrixFunctions/arm_mat_sub_q15.c
-            
-            
-              arm_mat_sub_q31.c
-              1
-              ../MatrixFunctions/arm_mat_sub_q31.c
-            
-            
-              arm_mat_trans_f32.c
-              1
-              ../MatrixFunctions/arm_mat_trans_f32.c
-            
-            
-              arm_mat_trans_q15.c
-              1
-              ../MatrixFunctions/arm_mat_trans_q15.c
-            
-            
-              arm_mat_trans_q31.c
-              1
-              ../MatrixFunctions/arm_mat_trans_q31.c
-            
-          
-        
-        
-          TransformFunctions
-          
-            
-              arm_bitreversal.c
-              1
-              ../TransformFunctions/arm_bitreversal.c
-            
-            
-              arm_cfft_radix2_f32.c
-              1
-              ../TransformFunctions/arm_cfft_radix2_f32.c
-            
-            
-              arm_cfft_radix2_init_f32.c
-              1
-              ../TransformFunctions/arm_cfft_radix2_init_f32.c
-            
-            
-              arm_cfft_radix2_init_q15.c
-              1
-              ../TransformFunctions/arm_cfft_radix2_init_q15.c
-            
-            
-              arm_cfft_radix2_init_q31.c
-              1
-              ../TransformFunctions/arm_cfft_radix2_init_q31.c
-            
-            
-              arm_cfft_radix2_q15.c
-              1
-              ../TransformFunctions/arm_cfft_radix2_q15.c
-            
-            
-              arm_cfft_radix2_q31.c
-              1
-              ../TransformFunctions/arm_cfft_radix2_q31.c
-            
-            
-              arm_cfft_radix4_f32.c
-              1
-              ../TransformFunctions/arm_cfft_radix4_f32.c
-            
-            
-              arm_cfft_radix4_init_f32.c
-              1
-              ../TransformFunctions/arm_cfft_radix4_init_f32.c
-            
-            
-              arm_cfft_radix4_init_q15.c
-              1
-              ../TransformFunctions/arm_cfft_radix4_init_q15.c
-            
-            
-              arm_cfft_radix4_init_q31.c
-              1
-              ../TransformFunctions/arm_cfft_radix4_init_q31.c
-            
-            
-              arm_cfft_radix4_q15.c
-              1
-              ../TransformFunctions/arm_cfft_radix4_q15.c
-            
-            
-              arm_cfft_radix4_q31.c
-              1
-              ../TransformFunctions/arm_cfft_radix4_q31.c
-            
-            
-              arm_dct4_f32.c
-              1
-              ../TransformFunctions/arm_dct4_f32.c
-            
-            
-              arm_dct4_init_f32.c
-              1
-              ../TransformFunctions/arm_dct4_init_f32.c
-            
-            
-              arm_dct4_init_q15.c
-              1
-              ../TransformFunctions/arm_dct4_init_q15.c
-            
-            
-              arm_dct4_init_q31.c
-              1
-              ../TransformFunctions/arm_dct4_init_q31.c
-            
-            
-              arm_dct4_q15.c
-              1
-              ../TransformFunctions/arm_dct4_q15.c
-            
-            
-              arm_dct4_q31.c
-              1
-              ../TransformFunctions/arm_dct4_q31.c
-            
-            
-              arm_rfft_f32.c
-              1
-              ../TransformFunctions/arm_rfft_f32.c
-            
-            
-              arm_rfft_init_f32.c
-              1
-              ../TransformFunctions/arm_rfft_init_f32.c
-            
-            
-              arm_rfft_init_q15.c
-              1
-              ../TransformFunctions/arm_rfft_init_q15.c
-            
-            
-              arm_rfft_init_q31.c
-              1
-              ../TransformFunctions/arm_rfft_init_q31.c
-            
-            
-              arm_rfft_q15.c
-              1
-              ../TransformFunctions/arm_rfft_q15.c
-            
-            
-              arm_rfft_q31.c
-              1
-              ../TransformFunctions/arm_rfft_q31.c
-            
-          
-        
-        
-          ControllerFunctions
-          
-            
-              arm_pid_init_f32.c
-              1
-              ../ControllerFunctions/arm_pid_init_f32.c
-            
-            
-              arm_pid_init_q15.c
-              1
-              ../ControllerFunctions/arm_pid_init_q15.c
-            
-            
-              arm_pid_init_q31.c
-              1
-              ../ControllerFunctions/arm_pid_init_q31.c
-            
-            
-              arm_pid_reset_f32.c
-              1
-              ../ControllerFunctions/arm_pid_reset_f32.c
-            
-            
-              arm_pid_reset_q15.c
-              1
-              ../ControllerFunctions/arm_pid_reset_q15.c
-            
-            
-              arm_pid_reset_q31.c
-              1
-              ../ControllerFunctions/arm_pid_reset_q31.c
-            
-            
-              arm_sin_cos_f32.c
-              1
-              ../ControllerFunctions/arm_sin_cos_f32.c
-            
-            
-              arm_sin_cos_q31.c
-              1
-              ../ControllerFunctions/arm_sin_cos_q31.c
-            
-          
-        
-        
-          StatisticsFunctions
-          
-            
-              arm_max_f32.c
-              1
-              ../StatisticsFunctions/arm_max_f32.c
-            
-            
-              arm_max_q7.c
-              1
-              ../StatisticsFunctions/arm_max_q7.c
-            
-            
-              arm_max_q15.c
-              1
-              ../StatisticsFunctions/arm_max_q15.c
-            
-            
-              arm_max_q31.c
-              1
-              ../StatisticsFunctions/arm_max_q31.c
-            
-            
-              arm_mean_f32.c
-              1
-              ../StatisticsFunctions/arm_mean_f32.c
-            
-            
-              arm_mean_q7.c
-              1
-              ../StatisticsFunctions/arm_mean_q7.c
-            
-            
-              arm_mean_q15.c
-              1
-              ../StatisticsFunctions/arm_mean_q15.c
-            
-            
-              arm_mean_q31.c
-              1
-              ../StatisticsFunctions/arm_mean_q31.c
-            
-            
-              arm_min_f32.c
-              1
-              ../StatisticsFunctions/arm_min_f32.c
-            
-            
-              arm_min_q7.c
-              1
-              ../StatisticsFunctions/arm_min_q7.c
-            
-            
-              arm_min_q15.c
-              1
-              ../StatisticsFunctions/arm_min_q15.c
-            
-            
-              arm_min_q31.c
-              1
-              ../StatisticsFunctions/arm_min_q31.c
-            
-            
-              arm_power_f32.c
-              1
-              ../StatisticsFunctions/arm_power_f32.c
-            
-            
-              arm_power_q7.c
-              1
-              ../StatisticsFunctions/arm_power_q7.c
-            
-            
-              arm_power_q15.c
-              1
-              ../StatisticsFunctions/arm_power_q15.c
-            
-            
-              arm_power_q31.c
-              1
-              ../StatisticsFunctions/arm_power_q31.c
-            
-            
-              arm_rms_f32.c
-              1
-              ../StatisticsFunctions/arm_rms_f32.c
-            
-            
-              arm_rms_q15.c
-              1
-              ../StatisticsFunctions/arm_rms_q15.c
-            
-            
-              arm_rms_q31.c
-              1
-              ../StatisticsFunctions/arm_rms_q31.c
-            
-            
-              arm_std_f32.c
-              1
-              ../StatisticsFunctions/arm_std_f32.c
-            
-            
-              arm_std_q15.c
-              1
-              ../StatisticsFunctions/arm_std_q15.c
-            
-            
-              arm_std_q31.c
-              1
-              ../StatisticsFunctions/arm_std_q31.c
-            
-            
-              arm_var_f32.c
-              1
-              ../StatisticsFunctions/arm_var_f32.c
-            
-            
-              arm_var_q15.c
-              1
-              ../StatisticsFunctions/arm_var_q15.c
-            
-            
-              arm_var_q31.c
-              1
-              ../StatisticsFunctions/arm_var_q31.c
-            
-          
-        
-        
-          SupportFunctions
-          
-            
-              arm_copy_f32.c
-              1
-              ../SupportFunctions/arm_copy_f32.c
-            
-            
-              arm_copy_q7.c
-              1
-              ../SupportFunctions/arm_copy_q7.c
-            
-            
-              arm_copy_q15.c
-              1
-              ../SupportFunctions/arm_copy_q15.c
-            
-            
-              arm_copy_q31.c
-              1
-              ../SupportFunctions/arm_copy_q31.c
-            
-            
-              arm_fill_f32.c
-              1
-              ../SupportFunctions/arm_fill_f32.c
-            
-            
-              arm_fill_q7.c
-              1
-              ../SupportFunctions/arm_fill_q7.c
-            
-            
-              arm_fill_q15.c
-              1
-              ../SupportFunctions/arm_fill_q15.c
-            
-            
-              arm_fill_q31.c
-              1
-              ../SupportFunctions/arm_fill_q31.c
-            
-            
-              arm_float_to_q7.c
-              1
-              ../SupportFunctions/arm_float_to_q7.c
-            
-            
-              arm_float_to_q15.c
-              1
-              ../SupportFunctions/arm_float_to_q15.c
-            
-            
-              arm_float_to_q31.c
-              1
-              ../SupportFunctions/arm_float_to_q31.c
-            
-            
-              arm_q7_to_float.c
-              1
-              ../SupportFunctions/arm_q7_to_float.c
-            
-            
-              arm_q7_to_q15.c
-              1
-              ../SupportFunctions/arm_q7_to_q15.c
-            
-            
-              arm_q7_to_q31.c
-              1
-              ../SupportFunctions/arm_q7_to_q31.c
-            
-            
-              arm_q15_to_float.c
-              1
-              ../SupportFunctions/arm_q15_to_float.c
-            
-            
-              arm_q15_to_q7.c
-              1
-              ../SupportFunctions/arm_q15_to_q7.c
-            
-            
-              arm_q15_to_q31.c
-              1
-              ../SupportFunctions/arm_q15_to_q31.c
-            
-            
-              arm_q31_to_float.c
-              1
-              ../SupportFunctions/arm_q31_to_float.c
-            
-            
-              arm_q31_to_q7.c
-              1
-              ../SupportFunctions/arm_q31_to_q7.c
-            
-            
-              arm_q31_to_q15.c
-              1
-              ../SupportFunctions/arm_q31_to_q15.c
-            
-          
-        
-        
-          CommonTables
-          
-            
-              arm_common_tables.c
-              1
-              ../CommonTables/arm_common_tables.c
-            
-          
-        
-      
-    
-  
-
-
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/GCC/arm_cortexMx_math_Build.bat b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/GCC/arm_cortexMx_math_Build.bat
deleted file mode 100644
index 007812c2d0..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/GCC/arm_cortexMx_math_Build.bat
+++ /dev/null
@@ -1,17 +0,0 @@
-
-SET TMP=C:\Temp
-SET TEMP=C:\Temp
-
-SET UVEXE=C:\Keil\UV4\UV4.EXE
-
-@echo   Building DSP Library for Cortex-M0 Little Endian
-%UVEXE% -rb arm_cortexM0x_math.uvproj -t"DSP_Lib CM0 LE" -o"DSP_Lib CM0 LE.txt" -j0
-
-@echo   Building DSP Library for Cortex-M3 Little Endian
-%UVEXE% -rb arm_cortexM3x_math.uvproj -t"DSP_Lib CM3 LE" -o"DSP_Lib CM3 LE.txt" -j0
-
-@echo   Building DSP Library for Cortex-M4 Little Endian
-%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 LE" -o"DSP_Lib CM4 LE.txt" -j0
-
-@echo   Building DSP Library for Cortex-M4 with FPU Little Endian
-%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 LE FPU" -o"DSP_Lib CM4 LE FPU.txt" -j0
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_f32.c
deleted file mode 100644
index 9ebd9e21c7..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_f32.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_mat_add_f32.c    
-*    
-* Description:	Floating-point matrix addition    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-*    incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**        
- * @ingroup groupMatrix        
- */
-
-/**        
- * @defgroup MatrixAdd Matrix Addition        
- *        
- * Adds two matrices.        
- * \image html MatrixAddition.gif "Addition of two 3 x 3 matrices"        
- *        
- * The functions check to make sure that        
- * pSrcA, pSrcB, and pDst have the same        
- * number of rows and columns.        
- */
-
-/**        
- * @addtogroup MatrixAdd        
- * @{        
- */
-
-
-/**        
- * @brief Floating-point matrix addition.        
- * @param[in]       *pSrcA points to the first input matrix structure        
- * @param[in]       *pSrcB points to the second input matrix structure        
- * @param[out]      *pDst points to output matrix structure        
- * @return     		The function returns either        
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.        
- */
-
-arm_status arm_mat_add_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst)
-{
-  float32_t *pIn1 = pSrcA->pData;                /* input data matrix pointer A  */
-  float32_t *pIn2 = pSrcB->pData;                /* input data matrix pointer B  */
-  float32_t *pOut = pDst->pData;                 /* output data matrix pointer   */
-
-#ifndef ARM_MATH_CM0
-
-  float32_t inA1, inA2, inB1, inB2, out1, out2;  /* temporary variables */
-
-#endif //      #ifndef ARM_MATH_CM0
-
-  uint32_t numSamples;                           /* total number of elements in the matrix  */
-  uint32_t blkCnt;                               /* loop counters */
-  arm_status status;                             /* status of matrix addition */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-  /* Check for matrix mismatch condition */
-  if((pSrcA->numRows != pSrcB->numRows) ||
-     (pSrcA->numCols != pSrcB->numCols) ||
-     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif
-  {
-
-    /* Total number of samples in the input matrix */
-    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
-
-#ifndef ARM_MATH_CM0
-
-    /* Loop unrolling */
-    blkCnt = numSamples >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-     ** a second loop below computes the remaining 1 to 3 samples. */
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) + B(m,n) */
-      /* Add and then store the results in the destination buffer. */
-      /* Read values from source A */
-      inA1 = pIn1[0];
-
-      /* Read values from source B */
-      inB1 = pIn2[0];
-
-      /* Read values from source A */
-      inA2 = pIn1[1];
-
-      /* out = sourceA + sourceB */
-      out1 = inA1 + inB1;
-
-      /* Read values from source B */
-      inB2 = pIn2[1];
-
-      /* Read values from source A */
-      inA1 = pIn1[2];
-
-      /* out = sourceA + sourceB */
-      out2 = inA2 + inB2;
-
-      /* Read values from source B */
-      inB1 = pIn2[2];
-
-      /* Store result in destination */
-      pOut[0] = out1;
-      pOut[1] = out2;
-
-      /* Read values from source A */
-      inA2 = pIn1[3];
-
-      /* Read values from source B */
-      inB2 = pIn2[3];
-
-      /* out = sourceA + sourceB */
-      out1 = inA1 + inB1;
-
-      /* out = sourceA + sourceB */
-      out2 = inA2 + inB2;
-
-      /* Store result in destination */
-      pOut[2] = out1;
-
-      /* Store result in destination */
-      pOut[3] = out2;
-
-
-      /* update pointers to process next sampels */
-      pIn1 += 4u;
-      pIn2 += 4u;
-      pOut += 4u;
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
-     ** No loop unrolling is used. */
-    blkCnt = numSamples % 0x4u;
-
-#else
-
-    /* Run the below code for Cortex-M0 */
-
-    /* Initialize blkCnt with number of samples */
-    blkCnt = numSamples;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) + B(m,n) */
-      /* Add and then store the results in the destination buffer. */
-      *pOut++ = (*pIn1++) + (*pIn2++);
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-/**        
- * @} end of MatrixAdd group        
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q15.c
deleted file mode 100644
index 9c86301310..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q15.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_add_q15.c    
-*    
-* Description:	Q15 matrix addition    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-*    incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupMatrix    
- */
-
-/**    
- * @addtogroup MatrixAdd    
- * @{    
- */
-
-/**    
- * @brief Q15 matrix addition.    
- * @param[in]       *pSrcA points to the first input matrix structure    
- * @param[in]       *pSrcB points to the second input matrix structure    
- * @param[out]      *pDst points to output matrix structure    
- * @return     		The function returns either    
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function uses saturating arithmetic.    
- * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.    
- */
-
-arm_status arm_mat_add_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst)
-{
-  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A  */
-  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B */
-  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
-  uint16_t numSamples;                           /* total number of elements in the matrix  */
-  uint32_t blkCnt;                               /* loop counters  */
-  arm_status status;                             /* status of matrix addition  */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
-  /* Check for matrix mismatch condition */
-  if((pSrcA->numRows != pSrcB->numRows) ||
-     (pSrcA->numCols != pSrcB->numCols) ||
-     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-    /* Total number of samples in the input matrix */
-    numSamples = (uint16_t) (pSrcA->numRows * pSrcA->numCols);
-
-#ifndef ARM_MATH_CM0
-
-    /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-    /* Loop unrolling */
-    blkCnt = (uint32_t) numSamples >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-     ** a second loop below computes the remaining 1 to 3 samples. */
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) + B(m,n) */
-      /* Add, Saturate and then store the results in the destination buffer. */
-      *__SIMD32(pOut)++ = __QADD16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
-      *__SIMD32(pOut)++ = __QADD16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-     ** No loop unrolling is used. */
-    blkCnt = (uint32_t) numSamples % 0x4u;
-
-    /* q15 pointers of input and output are initialized */
-
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) + B(m,n) */
-      /* Add, Saturate and then store the results in the destination buffer. */
-      *pOut++ = (q15_t) __QADD16(*pInA++, *pInB++);
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-#else
-
-    /* Run the below code for Cortex-M0 */
-
-    /* Initialize blkCnt with number of samples */
-    blkCnt = (uint32_t) numSamples;
-
-
-    /* q15 pointers of input and output are initialized */
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) + B(m,n) */
-      /* Add, Saturate and then store the results in the destination buffer. */
-      *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ + *pInB++), 16);
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-/**    
- * @} end of MatrixAdd group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q31.c
deleted file mode 100644
index ee1207e570..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q31.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_add_q31.c    
-*    
-* Description:	Q31 matrix addition    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-*    incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**      
- * @ingroup groupMatrix      
- */
-
-/**      
- * @addtogroup MatrixAdd      
- * @{      
- */
-
-/**      
- * @brief Q31 matrix addition.      
- * @param[in]       *pSrcA points to the first input matrix structure      
- * @param[in]       *pSrcB points to the second input matrix structure      
- * @param[out]      *pDst points to output matrix structure      
- * @return     		The function returns either      
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.      
- *      
- * Scaling and Overflow Behavior:      
- * \par      
- * The function uses saturating arithmetic.      
- * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.      
- */
-
-arm_status arm_mat_add_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst)
-{
-  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
-  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
-  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
-  q31_t inA1, inB1;                              /* temporary variables */
-
-#ifndef ARM_MATH_CM0
-
-  q31_t inA2, inB2;                              /* temporary variables */
-  q31_t out1, out2;                              /* temporary variables */
-
-#endif //      #ifndef ARM_MATH_CM0
-
-  uint32_t numSamples;                           /* total number of elements in the matrix  */
-  uint32_t blkCnt;                               /* loop counters */
-  arm_status status;                             /* status of matrix addition */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-  /* Check for matrix mismatch condition */
-  if((pSrcA->numRows != pSrcB->numRows) ||
-     (pSrcA->numCols != pSrcB->numCols) ||
-     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif
-  {
-    /* Total number of samples in the input matrix */
-    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
-
-#ifndef ARM_MATH_CM0
-
-    /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-    /* Loop Unrolling */
-    blkCnt = numSamples >> 2u;
-
-
-    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-     ** a second loop below computes the remaining 1 to 3 samples. */
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) + B(m,n) */
-      /* Add, saturate and then store the results in the destination buffer. */
-      /* Read values from source A */
-      inA1 = pIn1[0];
-
-      /* Read values from source B */
-      inB1 = pIn2[0];
-
-      /* Read values from source A */
-      inA2 = pIn1[1];
-
-      /* Add and saturate */
-      out1 = __QADD(inA1, inB1);
-
-      /* Read values from source B */
-      inB2 = pIn2[1];
-
-      /* Read values from source A */
-      inA1 = pIn1[2];
-
-      /* Add and saturate */
-      out2 = __QADD(inA2, inB2);
-
-      /* Read values from source B */
-      inB1 = pIn2[2];
-
-      /* Store result in destination */
-      pOut[0] = out1;
-      pOut[1] = out2;
-
-      /* Read values from source A */
-      inA2 = pIn1[3];
-
-      /* Read values from source B */
-      inB2 = pIn2[3];
-
-      /* Add and saturate */
-      out1 = __QADD(inA1, inB1);
-      out2 = __QADD(inA2, inB2);
-
-      /* Store result in destination */
-      pOut[2] = out1;
-      pOut[3] = out2;
-
-      /* update pointers to process next sampels */
-      pIn1 += 4u;
-      pIn2 += 4u;
-      pOut += 4u;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.      
-     ** No loop unrolling is used. */
-    blkCnt = numSamples % 0x4u;
-
-#else
-
-    /* Run the below code for Cortex-M0 */
-
-    /* Initialize blkCnt with number of samples */
-    blkCnt = numSamples;
-
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) + B(m,n) */
-      /* Add, saturate and then store the results in the destination buffer. */
-      inA1 = *pIn1++;
-      inB1 = *pIn2++;
-
-      inA1 = __QADD(inA1, inB1);
-
-      /* Decrement the loop counter */
-      blkCnt--;
-
-      *pOut++ = inA1;
-
-    }
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-/**      
- * @} end of MatrixAdd group      
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_f32.c
deleted file mode 100644
index 8d2cea559b..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_f32.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_mat_init_f32.c    
-*    
-* Description:	Floating-point matrix initialization.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-*    incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupMatrix    
- */
-
-/**    
- * @defgroup MatrixInit Matrix Initialization    
- *    
- * Initializes the underlying matrix data structure.    
- * The functions set the numRows,    
- * numCols, and pData fields    
- * of the matrix data structure.    
- */
-
-/**    
- * @addtogroup MatrixInit    
- * @{    
- */
-
-/**    
-   * @brief  Floating-point matrix initialization.    
-   * @param[in,out] *S             points to an instance of the floating-point matrix structure.    
-   * @param[in]     nRows          number of rows in the matrix.    
-   * @param[in]     nColumns       number of columns in the matrix.    
-   * @param[in]     *pData	   points to the matrix data array.    
-   * @return        none    
-   */
-
-void arm_mat_init_f32(
-  arm_matrix_instance_f32 * S,
-  uint16_t nRows,
-  uint16_t nColumns,
-  float32_t * pData)
-{
-  /* Assign Number of Rows */
-  S->numRows = nRows;
-
-  /* Assign Number of Columns */
-  S->numCols = nColumns;
-
-  /* Assign Data pointer */
-  S->pData = pData;
-}
-
-/**    
- * @} end of MatrixInit group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q15.c
deleted file mode 100644
index 7255627c2e..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q15.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_mat_init_q15.c    
-*    
-* Description:	Q15 matrix initialization.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-*    incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------------- */
-
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupMatrix    
- */
-
-/**    
- * @addtogroup MatrixInit    
- * @{    
- */
-
-  /**    
-   * @brief  Q15 matrix initialization.    
-   * @param[in,out] *S             points to an instance of the floating-point matrix structure.    
-   * @param[in]     nRows          number of rows in the matrix.    
-   * @param[in]     nColumns       number of columns in the matrix.    
-   * @param[in]     *pData	   points to the matrix data array.    
-   * @return        none    
-   */
-
-void arm_mat_init_q15(
-  arm_matrix_instance_q15 * S,
-  uint16_t nRows,
-  uint16_t nColumns,
-  q15_t * pData)
-{
-  /* Assign Number of Rows */
-  S->numRows = nRows;
-
-  /* Assign Number of Columns */
-  S->numCols = nColumns;
-
-  /* Assign Data pointer */
-  S->pData = pData;
-}
-
-/**    
- * @} end of MatrixInit group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q31.c
deleted file mode 100644
index 86ad404da6..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q31.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_mat_init_q31.c    
-*    
-* Description:	Q31 matrix initialization.    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-*    incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------------- */
-
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupMatrix    
- */
-
-/**    
- * @defgroup MatrixInit Matrix Initialization    
- *    
- */
-
-/**    
- * @addtogroup MatrixInit    
- * @{    
- */
-
-  /**    
-   * @brief  Q31 matrix initialization.    
-   * @param[in,out] *S             points to an instance of the floating-point matrix structure.    
-   * @param[in]     nRows          number of rows in the matrix.    
-   * @param[in]     nColumns       number of columns in the matrix.    
-   * @param[in]     *pData	   points to the matrix data array.    
-   * @return        none    
-   */
-
-void arm_mat_init_q31(
-  arm_matrix_instance_q31 * S,
-  uint16_t nRows,
-  uint16_t nColumns,
-  q31_t * pData)
-{
-  /* Assign Number of Rows */
-  S->numRows = nRows;
-
-  /* Assign Number of Columns */
-  S->numCols = nColumns;
-
-  /* Assign Data pointer */
-  S->pData = pData;
-}
-
-/**    
- * @} end of MatrixInit group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f32.c
deleted file mode 100644
index e8c6daebb2..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f32.c
+++ /dev/null
@@ -1,668 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_inverse_f32.c    
-*    
-* Description:	Floating-point matrix inverse.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupMatrix    
- */
-
-/**    
- * @defgroup MatrixInv Matrix Inverse    
- *    
- * Computes the inverse of a matrix.    
- *    
- * The inverse is defined only if the input matrix is square and non-singular (the determinant    
- * is non-zero). The function checks that the input and output matrices are square and of the    
- * same size.    
- *    
- * Matrix inversion is numerically sensitive and the CMSIS DSP library only supports matrix    
- * inversion of floating-point matrices.    
- *    
- * \par Algorithm    
- * The Gauss-Jordan method is used to find the inverse.    
- * The algorithm performs a sequence of elementary row-operations till it    
- * reduces the input matrix to an identity matrix. Applying the same sequence    
- * of elementary row-operations to an identity matrix yields the inverse matrix.    
- * If the input matrix is singular, then the algorithm terminates and returns error status    
- * ARM_MATH_SINGULAR.    
- * \image html MatrixInverse.gif "Matrix Inverse of a 3 x 3 matrix using Gauss-Jordan Method"    
- */
-
-/**    
- * @addtogroup MatrixInv    
- * @{    
- */
-
-/**    
- * @brief Floating-point matrix inverse.    
- * @param[in]       *pSrc points to input matrix structure    
- * @param[out]      *pDst points to output matrix structure    
- * @return     		The function returns    
- * ARM_MATH_SIZE_MISMATCH if the input matrix is not square or if the size    
- * of the output matrix does not match the size of the input matrix.    
- * If the input matrix is found to be singular (non-invertible), then the function returns    
- * ARM_MATH_SINGULAR.  Otherwise, the function returns ARM_MATH_SUCCESS.    
- */
-
-arm_status arm_mat_inverse_f32(
-  const arm_matrix_instance_f32 * pSrc,
-  arm_matrix_instance_f32 * pDst)
-{
-  float32_t *pIn = pSrc->pData;                  /* input data matrix pointer */
-  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
-  float32_t *pInT1, *pInT2;                      /* Temporary input data matrix pointer */
-  float32_t *pInT3, *pInT4;                      /* Temporary output data matrix pointer */
-  float32_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst;  /* Temporary input and output data matrix pointer */
-  uint32_t numRows = pSrc->numRows;              /* Number of rows in the matrix  */
-  uint32_t numCols = pSrc->numCols;              /* Number of Cols in the matrix  */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  float32_t Xchg, in = 0.0f, in1;                /* Temporary input values  */
-  uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l;      /* loop counters */
-  arm_status status;                             /* status of matrix inverse */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
-  /* Check for matrix mismatch condition */
-  if((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
-     || (pSrc->numRows != pDst->numRows))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-
-    /*--------------------------------------------------------------------------------------------------------------    
-	 * Matrix Inverse can be solved using elementary row operations.    
-	 *    
-	 *	Gauss-Jordan Method:    
-	 *    
-	 *	   1. First combine the identity matrix and the input matrix separated by a bar to form an    
-	 *        augmented matrix as follows:    
-	 *				        _ 	      	       _         _	       _    
-	 *					   |  a11  a12 | 1   0  |       |  X11 X12  |    
-	 *					   |           |        |   =   |           |    
-	 *					   |_ a21  a22 | 0   1 _|       |_ X21 X21 _|    
-	 *    
-	 *		2. In our implementation, pDst Matrix is used as identity matrix.    
-	 *    
-	 *		3. Begin with the first row. Let i = 1.    
-	 *    
-	 *	    4. Check to see if the pivot for row i is zero.    
-	 *		   The pivot is the element of the main diagonal that is on the current row.    
-	 *		   For instance, if working with row i, then the pivot element is aii.    
-	 *		   If the pivot is zero, exchange that row with a row below it that does not    
-	 *		   contain a zero in column i. If this is not possible, then an inverse    
-	 *		   to that matrix does not exist.    
-	 *    
-	 *	    5. Divide every element of row i by the pivot.    
-	 *    
-	 *	    6. For every row below and  row i, replace that row with the sum of that row and    
-	 *		   a multiple of row i so that each new element in column i below row i is zero.    
-	 *    
-	 *	    7. Move to the next row and column and repeat steps 2 through 5 until you have zeros    
-	 *		   for every element below and above the main diagonal.    
-	 *    
-	 *		8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc).    
-	 *		   Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst).    
-	 *----------------------------------------------------------------------------------------------------------------*/
-
-    /* Working pointer for destination matrix */
-    pInT2 = pOut;
-
-    /* Loop over the number of rows */
-    rowCnt = numRows;
-
-    /* Making the destination matrix as identity matrix */
-    while(rowCnt > 0u)
-    {
-      /* Writing all zeroes in lower triangle of the destination matrix */
-      j = numRows - rowCnt;
-      while(j > 0u)
-      {
-        *pInT2++ = 0.0f;
-        j--;
-      }
-
-      /* Writing all ones in the diagonal of the destination matrix */
-      *pInT2++ = 1.0f;
-
-      /* Writing all zeroes in upper triangle of the destination matrix */
-      j = rowCnt - 1u;
-      while(j > 0u)
-      {
-        *pInT2++ = 0.0f;
-        j--;
-      }
-
-      /* Decrement the loop counter */
-      rowCnt--;
-    }
-
-    /* Loop over the number of columns of the input matrix.    
-       All the elements in each column are processed by the row operations */
-    loopCnt = numCols;
-
-    /* Index modifier to navigate through the columns */
-    l = 0u;
-
-    while(loopCnt > 0u)
-    {
-      /* Check if the pivot element is zero..    
-       * If it is zero then interchange the row with non zero row below.    
-       * If there is no non zero element to replace in the rows below,    
-       * then the matrix is Singular. */
-
-      /* Working pointer for the input matrix that points    
-       * to the pivot element of the particular row  */
-      pInT1 = pIn + (l * numCols);
-
-      /* Working pointer for the destination matrix that points    
-       * to the pivot element of the particular row  */
-      pInT3 = pOut + (l * numCols);
-
-      /* Temporary variable to hold the pivot value */
-      in = *pInT1;
-
-      /* Destination pointer modifier */
-      k = 1u;
-
-      /* Check if the pivot element is zero */
-      if(*pInT1 == 0.0f)
-      {
-        /* Loop over the number rows present below */
-        i = numRows - (l + 1u);
-
-        while(i > 0u)
-        {
-          /* Update the input and destination pointers */
-          pInT2 = pInT1 + (numCols * l);
-          pInT4 = pInT3 + (numCols * k);
-
-          /* Check if there is a non zero pivot element to    
-           * replace in the rows below */
-          if(*pInT2 != 0.0f)
-          {
-            /* Loop over number of columns    
-             * to the right of the pilot element */
-            j = numCols - l;
-
-            while(j > 0u)
-            {
-              /* Exchange the row elements of the input matrix */
-              Xchg = *pInT2;
-              *pInT2++ = *pInT1;
-              *pInT1++ = Xchg;
-
-              /* Decrement the loop counter */
-              j--;
-            }
-
-            /* Loop over number of columns of the destination matrix */
-            j = numCols;
-
-            while(j > 0u)
-            {
-              /* Exchange the row elements of the destination matrix */
-              Xchg = *pInT4;
-              *pInT4++ = *pInT3;
-              *pInT3++ = Xchg;
-
-              /* Decrement the loop counter */
-              j--;
-            }
-
-            /* Flag to indicate whether exchange is done or not */
-            flag = 1u;
-
-            /* Break after exchange is done */
-            break;
-          }
-
-          /* Update the destination pointer modifier */
-          k++;
-
-          /* Decrement the loop counter */
-          i--;
-        }
-      }
-
-      /* Update the status if the matrix is singular */
-      if((flag != 1u) && (in == 0.0f))
-      {
-        status = ARM_MATH_SINGULAR;
-
-        break;
-      }
-
-      /* Points to the pivot row of input and destination matrices */
-      pPivotRowIn = pIn + (l * numCols);
-      pPivotRowDst = pOut + (l * numCols);
-
-      /* Temporary pointers to the pivot row pointers */
-      pInT1 = pPivotRowIn;
-      pInT2 = pPivotRowDst;
-
-      /* Pivot element of the row */
-      in = *(pIn + (l * numCols));
-
-      /* Loop over number of columns    
-       * to the right of the pilot element */
-      j = (numCols - l);
-
-      while(j > 0u)
-      {
-        /* Divide each element of the row of the input matrix    
-         * by the pivot element */
-        in1 = *pInT1;
-        *pInT1++ = in1 / in;
-
-        /* Decrement the loop counter */
-        j--;
-      }
-
-      /* Loop over number of columns of the destination matrix */
-      j = numCols;
-
-      while(j > 0u)
-      {
-        /* Divide each element of the row of the destination matrix    
-         * by the pivot element */
-        in1 = *pInT2;
-        *pInT2++ = in1 / in;
-
-        /* Decrement the loop counter */
-        j--;
-      }
-
-      /* Replace the rows with the sum of that row and a multiple of row i    
-       * so that each new element in column i above row i is zero.*/
-
-      /* Temporary pointers for input and destination matrices */
-      pInT1 = pIn;
-      pInT2 = pOut;
-
-      /* index used to check for pivot element */
-      i = 0u;
-
-      /* Loop over number of rows */
-      /*  to be replaced by the sum of that row and a multiple of row i */
-      k = numRows;
-
-      while(k > 0u)
-      {
-        /* Check for the pivot element */
-        if(i == l)
-        {
-          /* If the processing element is the pivot element,    
-             only the columns to the right are to be processed */
-          pInT1 += numCols - l;
-
-          pInT2 += numCols;
-        }
-        else
-        {
-          /* Element of the reference row */
-          in = *pInT1;
-
-          /* Working pointers for input and destination pivot rows */
-          pPRT_in = pPivotRowIn;
-          pPRT_pDst = pPivotRowDst;
-
-          /* Loop over the number of columns to the right of the pivot element,    
-             to replace the elements in the input matrix */
-          j = (numCols - l);
-
-          while(j > 0u)
-          {
-            /* Replace the element by the sum of that row    
-               and a multiple of the reference row  */
-            in1 = *pInT1;
-            *pInT1++ = in1 - (in * *pPRT_in++);
-
-            /* Decrement the loop counter */
-            j--;
-          }
-
-          /* Loop over the number of columns to    
-             replace the elements in the destination matrix */
-          j = numCols;
-
-          while(j > 0u)
-          {
-            /* Replace the element by the sum of that row    
-               and a multiple of the reference row  */
-            in1 = *pInT2;
-            *pInT2++ = in1 - (in * *pPRT_pDst++);
-
-            /* Decrement the loop counter */
-            j--;
-          }
-
-        }
-
-        /* Increment the temporary input pointer */
-        pInT1 = pInT1 + l;
-
-        /* Decrement the loop counter */
-        k--;
-
-        /* Increment the pivot index */
-        i++;
-      }
-
-      /* Increment the input pointer */
-      pIn++;
-
-      /* Decrement the loop counter */
-      loopCnt--;
-
-      /* Increment the index modifier */
-      l++;
-    }
-
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  float32_t Xchg, in = 0.0f;                     /* Temporary input values  */
-  uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l;      /* loop counters */
-  arm_status status;                             /* status of matrix inverse */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-  /* Check for matrix mismatch condition */
-  if((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
-     || (pSrc->numRows != pDst->numRows))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
-  {
-
-    /*--------------------------------------------------------------------------------------------------------------       
-	 * Matrix Inverse can be solved using elementary row operations.        
-	 *        
-	 *	Gauss-Jordan Method:       
-	 *	 	       
-	 *	   1. First combine the identity matrix and the input matrix separated by a bar to form an        
-	 *        augmented matrix as follows:        
-	 *				        _  _	      _	    _	   _   _         _	       _       
-	 *					   |  |  a11  a12  | | | 1   0  |   |       |  X11 X12  |         
-	 *					   |  |            | | |        |   |   =   |           |        
-	 *					   |_ |_ a21  a22 _| | |_0   1 _|  _|       |_ X21 X21 _|       
-	 *					          
-	 *		2. In our implementation, pDst Matrix is used as identity matrix.    
-	 *       
-	 *		3. Begin with the first row. Let i = 1.       
-	 *       
-	 *	    4. Check to see if the pivot for row i is zero.       
-	 *		   The pivot is the element of the main diagonal that is on the current row.       
-	 *		   For instance, if working with row i, then the pivot element is aii.       
-	 *		   If the pivot is zero, exchange that row with a row below it that does not        
-	 *		   contain a zero in column i. If this is not possible, then an inverse        
-	 *		   to that matrix does not exist.       
-	 *	       
-	 *	    5. Divide every element of row i by the pivot.       
-	 *	       
-	 *	    6. For every row below and  row i, replace that row with the sum of that row and        
-	 *		   a multiple of row i so that each new element in column i below row i is zero.       
-	 *	       
-	 *	    7. Move to the next row and column and repeat steps 2 through 5 until you have zeros       
-	 *		   for every element below and above the main diagonal.        
-	 *		   		          
-	 *		8. Now an identical matrix is formed to the left of the bar(input matrix, src).       
-	 *		   Therefore, the matrix to the right of the bar is our solution(dst matrix, dst).         
-	 *----------------------------------------------------------------------------------------------------------------*/
-
-    /* Working pointer for destination matrix */
-    pInT2 = pOut;
-
-    /* Loop over the number of rows */
-    rowCnt = numRows;
-
-    /* Making the destination matrix as identity matrix */
-    while(rowCnt > 0u)
-    {
-      /* Writing all zeroes in lower triangle of the destination matrix */
-      j = numRows - rowCnt;
-      while(j > 0u)
-      {
-        *pInT2++ = 0.0f;
-        j--;
-      }
-
-      /* Writing all ones in the diagonal of the destination matrix */
-      *pInT2++ = 1.0f;
-
-      /* Writing all zeroes in upper triangle of the destination matrix */
-      j = rowCnt - 1u;
-      while(j > 0u)
-      {
-        *pInT2++ = 0.0f;
-        j--;
-      }
-
-      /* Decrement the loop counter */
-      rowCnt--;
-    }
-
-    /* Loop over the number of columns of the input matrix.     
-       All the elements in each column are processed by the row operations */
-    loopCnt = numCols;
-
-    /* Index modifier to navigate through the columns */
-    l = 0u;
-    //for(loopCnt = 0u; loopCnt < numCols; loopCnt++)   
-    while(loopCnt > 0u)
-    {
-      /* Check if the pivot element is zero..    
-       * If it is zero then interchange the row with non zero row below.   
-       * If there is no non zero element to replace in the rows below,   
-       * then the matrix is Singular. */
-
-      /* Working pointer for the input matrix that points     
-       * to the pivot element of the particular row  */
-      pInT1 = pIn + (l * numCols);
-
-      /* Working pointer for the destination matrix that points     
-       * to the pivot element of the particular row  */
-      pInT3 = pOut + (l * numCols);
-
-      /* Temporary variable to hold the pivot value */
-      in = *pInT1;
-
-      /* Destination pointer modifier */
-      k = 1u;
-
-      /* Check if the pivot element is zero */
-      if(*pInT1 == 0.0f)
-      {
-        /* Loop over the number rows present below */
-        for (i = (l + 1u); i < numRows; i++)
-        {
-          /* Update the input and destination pointers */
-          pInT2 = pInT1 + (numCols * l);
-          pInT4 = pInT3 + (numCols * k);
-
-          /* Check if there is a non zero pivot element to     
-           * replace in the rows below */
-          if(*pInT2 != 0.0f)
-          {
-            /* Loop over number of columns     
-             * to the right of the pilot element */
-            for (j = 0u; j < (numCols - l); j++)
-            {
-              /* Exchange the row elements of the input matrix */
-              Xchg = *pInT2;
-              *pInT2++ = *pInT1;
-              *pInT1++ = Xchg;
-            }
-
-            for (j = 0u; j < numCols; j++)
-            {
-              Xchg = *pInT4;
-              *pInT4++ = *pInT3;
-              *pInT3++ = Xchg;
-            }
-
-            /* Flag to indicate whether exchange is done or not */
-            flag = 1u;
-
-            /* Break after exchange is done */
-            break;
-          }
-
-          /* Update the destination pointer modifier */
-          k++;
-        }
-      }
-
-      /* Update the status if the matrix is singular */
-      if((flag != 1u) && (in == 0.0f))
-      {
-        status = ARM_MATH_SINGULAR;
-
-        break;
-      }
-
-      /* Points to the pivot row of input and destination matrices */
-      pPivotRowIn = pIn + (l * numCols);
-      pPivotRowDst = pOut + (l * numCols);
-
-      /* Temporary pointers to the pivot row pointers */
-      pInT1 = pPivotRowIn;
-      pInT2 = pPivotRowDst;
-
-      /* Pivot element of the row */
-      in = *(pIn + (l * numCols));
-
-      /* Loop over number of columns     
-       * to the right of the pilot element */
-      for (j = 0u; j < (numCols - l); j++)
-      {
-        /* Divide each element of the row of the input matrix     
-         * by the pivot element */
-        *pInT1++ = *pInT1 / in;
-      }
-      for (j = 0u; j < numCols; j++)
-      {
-        /* Divide each element of the row of the destination matrix     
-         * by the pivot element */
-        *pInT2++ = *pInT2 / in;
-      }
-
-      /* Replace the rows with the sum of that row and a multiple of row i     
-       * so that each new element in column i above row i is zero.*/
-
-      /* Temporary pointers for input and destination matrices */
-      pInT1 = pIn;
-      pInT2 = pOut;
-
-      for (i = 0u; i < numRows; i++)
-      {
-        /* Check for the pivot element */
-        if(i == l)
-        {
-          /* If the processing element is the pivot element,     
-             only the columns to the right are to be processed */
-          pInT1 += numCols - l;
-          pInT2 += numCols;
-        }
-        else
-        {
-          /* Element of the reference row */
-          in = *pInT1;
-
-          /* Working pointers for input and destination pivot rows */
-          pPRT_in = pPivotRowIn;
-          pPRT_pDst = pPivotRowDst;
-
-          /* Loop over the number of columns to the right of the pivot element,     
-             to replace the elements in the input matrix */
-          for (j = 0u; j < (numCols - l); j++)
-          {
-            /* Replace the element by the sum of that row     
-               and a multiple of the reference row  */
-            *pInT1++ = *pInT1 - (in * *pPRT_in++);
-          }
-          /* Loop over the number of columns to     
-             replace the elements in the destination matrix */
-          for (j = 0u; j < numCols; j++)
-          {
-            /* Replace the element by the sum of that row     
-               and a multiple of the reference row  */
-            *pInT2++ = *pInT2 - (in * *pPRT_pDst++);
-          }
-
-        }
-        /* Increment the temporary input pointer */
-        pInT1 = pInT1 + l;
-      }
-      /* Increment the input pointer */
-      pIn++;
-
-      /* Decrement the loop counter */
-      loopCnt--;
-      /* Increment the index modifier */
-      l++;
-    }
-
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-    /* Set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-
-    if((flag != 1u) && (in == 0.0f))
-    {
-      status = ARM_MATH_SINGULAR;
-    }
-  }
-  /* Return to application */
-  return (status);
-}
-
-/**    
- * @} end of MatrixInv group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_f32.c
deleted file mode 100644
index a04f12600a..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_f32.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_mult_f32.c    
-*    
-* Description:  Floating-point matrix multiplication.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-*    incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupMatrix    
- */
-
-/**    
- * @defgroup MatrixMult Matrix Multiplication    
- *    
- * Multiplies two matrices.    
- *    
- * \image html MatrixMultiplication.gif "Multiplication of two 3 x 3 matrices"    
-    
- * Matrix multiplication is only defined if the number of columns of the    
- * first matrix equals the number of rows of the second matrix.    
- * Multiplying an M x N matrix with an N x P matrix results    
- * in an M x P matrix.    
- * When matrix size checking is enabled, the functions check: (1) that the inner dimensions of    
- * pSrcA and pSrcB are equal; and (2) that the size of the output    
- * matrix equals the outer dimensions of pSrcA and pSrcB.    
- */
-
-
-/**    
- * @addtogroup MatrixMult    
- * @{    
- */
-
-/**    
- * @brief Floating-point matrix multiplication.    
- * @param[in]       *pSrcA points to the first input matrix structure    
- * @param[in]       *pSrcB points to the second input matrix structure    
- * @param[out]      *pDst points to output matrix structure    
- * @return     		The function returns either    
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    
- */
-
-arm_status arm_mat_mult_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst)
-{
-  float32_t *pIn1 = pSrcA->pData;                /* input data matrix pointer A */
-  float32_t *pIn2 = pSrcB->pData;                /* input data matrix pointer B */
-  float32_t *pInA = pSrcA->pData;                /* input data matrix pointer A  */
-  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
-  float32_t *px;                                 /* Temporary output data matrix pointer */
-  float32_t sum;                                 /* Accumulator */
-  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A */
-  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
-  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  float32_t in1, in2, in3, in4;
-  uint16_t col, i = 0u, j, row = numRowsA, colCnt;      /* loop counters */
-  arm_status status;                             /* status of matrix multiplication */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
-  /* Check for matrix mismatch condition */
-  if((pSrcA->numCols != pSrcB->numRows) ||
-     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
-  {
-
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
-    /* row loop */
-    do
-    {
-      /* Output pointer is set to starting address of the row being processed */
-      px = pOut + i;
-
-      /* For every row wise process, the column loop counter is to be initiated */
-      col = numColsB;
-
-      /* For every row wise process, the pIn2 pointer is set    
-       ** to the starting address of the pSrcB data */
-      pIn2 = pSrcB->pData;
-
-      j = 0u;
-
-      /* column loop */
-      do
-      {
-        /* Set the variable sum, that acts as accumulator, to zero */
-        sum = 0.0f;
-
-        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
-        pIn1 = pInA;
-
-        /* Apply loop unrolling and compute 4 MACs simultaneously. */
-        colCnt = numColsA >> 2u;
-
-        /* matrix multiplication        */
-        while(colCnt > 0u)
-        {
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-          in3 = *pIn2;
-          pIn2 += numColsB;
-          in1 = pIn1[0];
-          in2 = pIn1[1];
-          sum += in1 * in3;
-          in4 = *pIn2;
-          pIn2 += numColsB;
-          sum += in2 * in4;
-
-          in3 = *pIn2;
-          pIn2 += numColsB;
-          in1 = pIn1[2];
-          in2 = pIn1[3];
-          sum += in1 * in3;
-          in4 = *pIn2;
-          pIn2 += numColsB;
-          sum += in2 * in4;
-          pIn1 += 4u;
-
-          /* Decrement the loop count */
-          colCnt--;
-        }
-
-        /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here.    
-         ** No loop unrolling is used. */
-        colCnt = numColsA % 0x4u;
-
-        while(colCnt > 0u)
-        {
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-          sum += *pIn1++ * (*pIn2);
-          pIn2 += numColsB;
-
-          /* Decrement the loop counter */
-          colCnt--;
-        }
-
-        /* Store the result in the destination buffer */
-        *px++ = sum;
-
-        /* Update the pointer pIn2 to point to the  starting address of the next column */
-        j++;
-        pIn2 = pSrcB->pData + j;
-
-        /* Decrement the column loop counter */
-        col--;
-
-      } while(col > 0u);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  float32_t *pInB = pSrcB->pData;                /* input data matrix pointer B */
-  uint16_t col, i = 0u, row = numRowsA, colCnt;  /* loop counters */
-  arm_status status;                             /* status of matrix multiplication */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-  /* Check for matrix mismatch condition */
-  if((pSrcA->numCols != pSrcB->numRows) ||
-     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
-  {
-
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-    /* The following loop performs the dot-product of each row in pInA with each column in pInB */
-    /* row loop */
-    do
-    {
-      /* Output pointer is set to starting address of the row being processed */
-      px = pOut + i;
-
-      /* For every row wise process, the column loop counter is to be initiated */
-      col = numColsB;
-
-      /* For every row wise process, the pIn2 pointer is set     
-       ** to the starting address of the pSrcB data */
-      pIn2 = pSrcB->pData;
-
-      /* column loop */
-      do
-      {
-        /* Set the variable sum, that acts as accumulator, to zero */
-        sum = 0.0f;
-
-        /* Initialize the pointer pIn1 to point to the starting address of the row being processed */
-        pIn1 = pInA;
-
-        /* Matrix A columns number of MAC operations are to be performed */
-        colCnt = numColsA;
-
-        while(colCnt > 0u)
-        {
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-          sum += *pIn1++ * (*pIn2);
-          pIn2 += numColsB;
-
-          /* Decrement the loop counter */
-          colCnt--;
-        }
-
-        /* Store the result in the destination buffer */
-        *px++ = sum;
-
-        /* Decrement the column loop counter */
-        col--;
-
-        /* Update the pointer pIn2 to point to the  starting address of the next column */
-        pIn2 = pInB + (numColsB - col);
-
-      } while(col > 0u);
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-      /* Update the pointer pInA to point to the  starting address of the next row */
-      i = i + numColsB;
-      pInA = pInA + numColsA;
-
-      /* Decrement the row loop counter */
-      row--;
-
-    } while(row > 0u);
-    /* Set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-/**    
- * @} end of MatrixMult group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q15.c
deleted file mode 100644
index 5699511cf8..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q15.c
+++ /dev/null
@@ -1,361 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_mult_fast_q15.c    
-*    
-* Description:	 Q15 matrix multiplication (fast variant)    
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupMatrix    
- */
-
-/**    
- * @addtogroup MatrixMult    
- * @{    
- */
-
-
-/**    
- * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4    
- * @param[in]       *pSrcA points to the first input matrix structure    
- * @param[in]       *pSrcB points to the second input matrix structure    
- * @param[out]      *pDst points to output matrix structure    
- * @param[in]		*pState points to the array for storing intermediate results    
- * @return     		The function returns either    
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The difference between the function arm_mat_mult_q15() and this fast variant is that    
- * the fast variant use a 32-bit rather than a 64-bit accumulator.    
- * The result of each 1.15 x 1.15 multiplication is truncated to        
- * 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30        
- * format. Finally, the accumulator is saturated and converted to a 1.15 result.        
- *        
- * \par        
- * The fast version has the same overflow behavior as the standard version but provides        
- * less precision since it discards the low 16 bits of each multiplication result.        
- * In order to avoid overflows completely the input signals must be scaled down.        
- * Scale down one of the input matrices by log2(numColsA) bits to        
- * avoid overflows, as a total of numColsA additions are computed internally for each        
- * output element.        
- *        
- * \par    
- * See arm_mat_mult_q15() for a slower implementation of this function    
- * which uses 64-bit accumulation to provide higher precision.    
- */
-
-arm_status arm_mat_mult_fast_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst,
-  q15_t * pState)
-{
-  q31_t sum;                                     /* accumulator */
-  q15_t *pSrcBT = pState;                        /* input data matrix pointer for transpose */
-  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A of Q15 type */
-  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B of Q15 type */
-  q15_t *px;                                     /* Temporary output data matrix pointer */
-  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
-  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
-  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
-  uint16_t numRowsB = pSrcB->numRows;            /* number of rows of input matrix A    */
-  uint16_t col, i = 0u, row = numRowsB, colCnt;  /* loop counters */
-  arm_status status;                             /* status of matrix multiplication */
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-  q31_t in;                                      /* Temporary variable to hold the input value */
-  q31_t inA1, inA2, inB1, inB2;
-
-#else
-
-  q15_t in;                                      /* Temporary variable to hold the input value */
-  q15_t inA1, inA2, inB1, inB2;
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-#ifdef ARM_MATH_MATRIX_CHECK
-  /* Check for matrix mismatch condition */
-  if((pSrcA->numCols != pSrcB->numRows) ||
-     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif
-  {
-    /* Matrix transpose */
-    do
-    {
-      /* Apply loop unrolling and exchange the columns with row elements */
-      col = numColsB >> 2;
-
-      /* The pointer px is set to starting address of the column being processed */
-      px = pSrcBT + i;
-
-      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
-       ** a second loop below computes the remaining 1 to 3 samples. */
-      while(col > 0u)
-      {
-#ifndef UNALIGNED_SUPPORT_DISABLE
-        /* Read two elements from the row */
-        in = *__SIMD32(pInB)++;
-
-        /* Unpack and store one element in the destination */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        *px = (q15_t) in;
-
-#else
-
-        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-        /* Unpack and store the second element in the destination */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#else
-
-        *px = (q15_t) in;
-
-#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-        /* Read two elements from the row */
-        in = *__SIMD32(pInB)++;
-
-        /* Unpack and store one element in the destination */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        *px = (q15_t) in;
-
-#else
-
-        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-        /* Unpack and store the second element in the destination */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#else
-
-        *px = (q15_t) in;
-
-#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
-
-#else
-
-        /* Read one element from the row */
-        in = *pInB++;
-
-        /* Store one element in the destination */
-        *px = in;
- 
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-        /* Read one element from the row */
-        in = *pInB++;
-
-        /* Store one element in the destination */
-        *px = in;
- 
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-        /* Read one element from the row */
-        in = *pInB++;
-
-        /* Store one element in the destination */
-        *px = in;
- 
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-        /* Read one element from the row */
-        in = *pInB++;
-
-        /* Store one element in the destination */
-        *px = in;
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-        
-		/* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-        /* Decrement the column loop counter */
-        col--;
-      }
-
-      /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.        
-       ** No loop unrolling is used. */
-      col = numColsB % 0x4u;
-
-      while(col > 0u)
-      {
-        /* Read and store the input element in the destination */
-        *px = *pInB++;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-        /* Decrement the column loop counter */
-        col--;
-      }
-
-      i++;
-
-      /* Decrement the row loop counter */
-      row--;
-
-    } while(row > 0u);
-
-    /* Reset the variables for the usage in the following multiplication process */
-    row = numRowsA;
-    i = 0u;
-    px = pDst->pData;
-
-    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
-    /* row loop */
-    do
-    {
-      /* For every row wise process, the column loop counter is to be initiated */
-      col = numColsB;
-
-      /* For every row wise process, the pIn2 pointer is set        
-       ** to the starting address of the transposed pSrcB data */
-      pInB = pSrcBT;
-
-      /* column loop */
-      do
-      {
-        /* Set the variable sum, that acts as accumulator, to zero */
-        sum = 0;
-
-        /* Apply loop unrolling and compute 2 MACs simultaneously. */
-        colCnt = numColsA >> 2;
-
-        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
-        pInA = pSrcA->pData + i;
-
-        /* matrix multiplication */
-        while(colCnt > 0u)
-        {
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-          inA1 = *__SIMD32(pInA)++;
-          inB1 = *__SIMD32(pInB)++;
-          inA2 = *__SIMD32(pInA)++;
-          inB2 = *__SIMD32(pInB)++;
-
-          sum = __SMLAD(inA1, inB1, sum);
-          sum = __SMLAD(inA2, inB2, sum);
-
-#else
-
-          inA1 = *pInA++;
-          inB1 = *pInB++;
-          inA2 = *pInA++;
-          sum += inA1 * inB1;
-          inB2 = *pInB++;
-
-          inA1 = *pInA++;
-          inB1 = *pInB++;
-          sum += inA2 * inB2;
-          inA2 = *pInA++;
-          inB2 = *pInB++;
-
-          sum += inA1 * inB1;
-          sum += inA2 * inB2;
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-          /* Decrement the loop counter */
-          colCnt--;
-        }
-
-        /* process odd column samples */
-        colCnt = numColsA % 0x4u;
-
-        while(colCnt > 0u)
-        {
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-          sum += (q31_t) (*pInA++) * (*pInB++);
-
-          colCnt--;
-        }
-
-        /* Saturate and store the result in the destination buffer */
-        *px = (q15_t) (sum >> 15);
-        px++;
-
-        /* Decrement the column loop counter */
-        col--;
-
-      } while(col > 0u);
-
-      i = i + numColsA;
-
-      /* Decrement the row loop counter */
-      row--;
-
-    } while(row > 0u);
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-/**        
- * @} end of MatrixMult group        
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q31.c
deleted file mode 100644
index a7b08fbabf..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q31.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_mult_fast_q31.c    
-*    
-* Description:	 Q31 matrix multiplication (fast variant).    
-*    
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupMatrix    
- */
-
-/**    
- * @addtogroup MatrixMult    
- * @{    
- */
-
-/**    
- * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4    
- * @param[in]       *pSrcA points to the first input matrix structure    
- * @param[in]       *pSrcB points to the second input matrix structure    
- * @param[out]      *pDst points to output matrix structure    
- * @return     		The function returns either    
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The difference between the function arm_mat_mult_q31() and this fast variant is that    
- * the fast variant use a 32-bit rather than a 64-bit accumulator.    
- * The result of each 1.31 x 1.31 multiplication is truncated to    
- * 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30    
- * format. Finally, the accumulator is saturated and converted to a 1.31 result.    
- *    
- * \par    
- * The fast version has the same overflow behavior as the standard version but provides    
- * less precision since it discards the low 32 bits of each multiplication result.    
- * In order to avoid overflows completely the input signals must be scaled down.    
- * Scale down one of the input matrices by log2(numColsA) bits to    
- * avoid overflows, as a total of numColsA additions are computed internally for each    
- * output element.    
- *    
- * \par    
- * See arm_mat_mult_q31() for a slower implementation of this function    
- * which uses 64-bit accumulation to provide higher precision.    
- */
-
-arm_status arm_mat_mult_fast_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst)
-{
-  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
-  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
-  q31_t *pInA = pSrcA->pData;                    /* input data matrix pointer A */
-//  q31_t *pSrcB = pSrcB->pData;                    /* input data matrix pointer B */    
-  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
-  q31_t *px;                                     /* Temporary output data matrix pointer */
-  q31_t sum;                                     /* Accumulator */
-  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
-  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
-  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
-  uint16_t col, i = 0u, j, row = numRowsA, colCnt;      /* loop counters */
-  arm_status status;                             /* status of matrix multiplication */
-  q31_t inA1, inA2, inA3, inA4, inB1, inB2, inB3, inB4;
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
-  /* Check for matrix mismatch condition */
-  if((pSrcA->numCols != pSrcB->numRows) ||
-     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
-    /* row loop */
-    do
-    {
-      /* Output pointer is set to starting address of the row being processed */
-      px = pOut + i;
-
-      /* For every row wise process, the column loop counter is to be initiated */
-      col = numColsB;
-
-      /* For every row wise process, the pIn2 pointer is set    
-       ** to the starting address of the pSrcB data */
-      pIn2 = pSrcB->pData;
-
-      j = 0u;
-
-      /* column loop */
-      do
-      {
-        /* Set the variable sum, that acts as accumulator, to zero */
-        sum = 0;
-
-        /* Initiate the pointer pIn1 to point to the starting address of pInA */
-        pIn1 = pInA;
-
-        /* Apply loop unrolling and compute 4 MACs simultaneously. */
-        colCnt = numColsA >> 2;
-
-
-        /* matrix multiplication */
-        while(colCnt > 0u)
-        {
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-          /* Perform the multiply-accumulates */
-          inB1 = *pIn2;
-          pIn2 += numColsB;
-
-          inA1 = pIn1[0];
-          inA2 = pIn1[1];
-
-          inB2 = *pIn2;
-          pIn2 += numColsB;
-
-          inB3 = *pIn2;
-          pIn2 += numColsB;
-
-          sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA1 * inB1)) >> 32);
-          sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA2 * inB2)) >> 32);
-
-          inA3 = pIn1[2];
-          inA4 = pIn1[3];
-
-          inB4 = *pIn2;
-          pIn2 += numColsB;
-
-          sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA3 * inB3)) >> 32);
-          sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA4 * inB4)) >> 32);
-
-          pIn1 += 4u;
-
-          /* Decrement the loop counter */
-          colCnt--;
-        }
-
-        /* If the columns of pSrcA is not a multiple of 4, compute any remaining output samples here.    
-         ** No loop unrolling is used. */
-        colCnt = numColsA % 0x4u;
-
-        while(colCnt > 0u)
-        {
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-          /* Perform the multiply-accumulates */
-          sum = (q31_t) ((((q63_t) sum << 32) +
-                          ((q63_t) * pIn1++ * (*pIn2))) >> 32);
-          pIn2 += numColsB;
-
-          /* Decrement the loop counter */
-          colCnt--;
-        }
-
-        /* Convert the result from 2.30 to 1.31 format and store in destination buffer */
-        *px++ = sum << 1;
-
-        /* Update the pointer pIn2 to point to the  starting address of the next column */
-        j++;
-        pIn2 = pSrcB->pData + j;
-
-        /* Decrement the column loop counter */
-        col--;
-
-      } while(col > 0u);
-
-      /* Update the pointer pInA to point to the  starting address of the next row */
-      i = i + numColsB;
-      pInA = pInA + numColsA;
-
-      /* Decrement the row loop counter */
-      row--;
-
-    } while(row > 0u);
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-  /* Return to application */
-  return (status);
-}
-
-/**    
- * @} end of MatrixMult group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q15.c
deleted file mode 100644
index 46ceca1f26..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q15.c
+++ /dev/null
@@ -1,467 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_mult_q15.c    
-*    
-* Description:	 Q15 matrix multiplication.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-*    incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupMatrix    
- */
-
-/**    
- * @addtogroup MatrixMult    
- * @{    
- */
-
-
-/**    
- * @brief Q15 matrix multiplication    
- * @param[in]       *pSrcA points to the first input matrix structure    
- * @param[in]       *pSrcB points to the second input matrix structure    
- * @param[out]      *pDst points to output matrix structure    
- * @param[in]		*pState points to the array for storing intermediate results   
- * @return     		The function returns either    
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The function is implemented using a 64-bit internal accumulator. The inputs to the    
- * multiplications are in 1.15 format and multiplications yield a 2.30 result.    
- * The 2.30 intermediate    
- * results are accumulated in a 64-bit accumulator in 34.30 format. This approach    
- * provides 33 guard bits and there is no risk of overflow. The 34.30 result is then    
- * truncated to 34.15 format by discarding the low 15 bits and then saturated to    
- * 1.15 format.    
- *    
- * \par    
- * Refer to arm_mat_mult_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.    
- *    
- */
-
-arm_status arm_mat_mult_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst,
-  q15_t * pState)
-{
-  q63_t sum;                                     /* accumulator */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q15_t *pSrcBT = pState;                        /* input data matrix pointer for transpose */
-  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A of Q15 type */
-  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B of Q15 type */
-  q15_t *px;                                     /* Temporary output data matrix pointer */
-  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
-  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
-  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
-  uint16_t numRowsB = pSrcB->numRows;            /* number of rows of input matrix A    */
-  uint16_t col, i = 0u, row = numRowsB, colCnt;  /* loop counters */
-  arm_status status;                             /* status of matrix multiplication */
-
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-  q31_t in;                                      /* Temporary variable to hold the input value */
-  q31_t pSourceA1, pSourceB1, pSourceA2, pSourceB2;
-
-#else
-
-  q15_t in;                                      /* Temporary variable to hold the input value */
-  q15_t inA1, inB1, inA2, inB2;
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-#ifdef ARM_MATH_MATRIX_CHECK
-  /* Check for matrix mismatch condition */
-  if((pSrcA->numCols != pSrcB->numRows) ||
-     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
-  {
-    /* Matrix transpose */
-    do
-    {
-      /* Apply loop unrolling and exchange the columns with row elements */
-      col = numColsB >> 2;
-
-      /* The pointer px is set to starting address of the column being processed */
-      px = pSrcBT + i;
-
-      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.        
-       ** a second loop below computes the remaining 1 to 3 samples. */
-      while(col > 0u)
-      {
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-        /* Read two elements from the row */
-        in = *__SIMD32(pInB)++;
-
-        /* Unpack and store one element in the destination */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        *px = (q15_t) in;
-
-#else
-
-        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-        /* Unpack and store the second element in the destination */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#else
-
-        *px = (q15_t) in;
-
-#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-        /* Read two elements from the row */
-        in = *__SIMD32(pInB)++;
-
-        /* Unpack and store one element in the destination */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        *px = (q15_t) in;
-
-#else
-
-        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-        /* Unpack and store the second element in the destination */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#else
-
-        *px = (q15_t) in;
-
-#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-#else
-
-        /* Read one element from the row */
-        in = *pInB++;
-
-        /* Store one element in the destination */
-        *px = in;
- 
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-        /* Read one element from the row */
-        in = *pInB++;
-
-        /* Store one element in the destination */
-        *px = in;
- 
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-        /* Read one element from the row */
-        in = *pInB++;
-
-        /* Store one element in the destination */
-        *px = in;
- 
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-        /* Read one element from the row */
-        in = *pInB++;
-
-        /* Store one element in the destination */
-        *px = in;
- 
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-       /* Decrement the column loop counter */
-        col--;
-      }
-
-      /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.        
-       ** No loop unrolling is used. */
-      col = numColsB % 0x4u;
-
-      while(col > 0u)
-      {
-        /* Read and store the input element in the destination */
-        *px = *pInB++;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += numRowsB;
-
-        /* Decrement the column loop counter */
-        col--;
-      }
-
-      i++;
-
-      /* Decrement the row loop counter */
-      row--;
-
-    } while(row > 0u);
-
-    /* Reset the variables for the usage in the following multiplication process */
-    row = numRowsA;
-    i = 0u;
-    px = pDst->pData;
-
-    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
-    /* row loop */
-    do
-    {
-      /* For every row wise process, the column loop counter is to be initiated */
-      col = numColsB;
-
-      /* For every row wise process, the pIn2 pointer is set        
-       ** to the starting address of the transposed pSrcB data */
-      pInB = pSrcBT;
-
-      /* column loop */
-      do
-      {
-        /* Set the variable sum, that acts as accumulator, to zero */
-        sum = 0;
-
-        /* Apply loop unrolling and compute 2 MACs simultaneously. */
-        colCnt = numColsA >> 2;
-
-        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
-        pInA = pSrcA->pData + i;
-
-
-        /* matrix multiplication */
-        while(colCnt > 0u)
-        {
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-          /* read real and imag values from pSrcA and pSrcB buffer */
-          pSourceA1 = *__SIMD32(pInA)++;
-          pSourceB1 = *__SIMD32(pInB)++;
-
-          pSourceA2 = *__SIMD32(pInA)++;
-          pSourceB2 = *__SIMD32(pInB)++;
-
-          /* Multiply and Accumlates */
-          sum = __SMLALD(pSourceA1, pSourceB1, sum);
-          sum = __SMLALD(pSourceA2, pSourceB2, sum);
-
-#else
-          /* read real and imag values from pSrcA and pSrcB buffer */
-          inA1 = *pInA++;
-          inB1 = *pInB++;
-          inA2 = *pInA++;
-          /* Multiply and Accumlates */
-          sum += inA1 * inB1;
-          inB2 = *pInB++;
-
-          inA1 = *pInA++;
-          inB1 = *pInB++;
-          /* Multiply and Accumlates */
-          sum += inA2 * inB2;
-          inA2 = *pInA++;
-          inB2 = *pInB++;
-
-          /* Multiply and Accumlates */
-          sum += inA1 * inB1;
-          sum += inA2 * inB2;
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-          /* Decrement the loop counter */
-          colCnt--;
-        }
-
-        /* process remaining column samples */
-        colCnt = numColsA & 3u;
-
-        while(colCnt > 0u)
-        {
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-          sum += *pInA++ * *pInB++;
-
-          /* Decrement the loop counter */
-          colCnt--;
-        }
-
-        /* Saturate and store the result in the destination buffer */
-        *px = (q15_t) (__SSAT((sum >> 15), 16));
-        px++;
-
-        /* Decrement the column loop counter */
-        col--;
-
-      } while(col > 0u);
-
-      i = i + numColsA;
-
-      /* Decrement the row loop counter */
-      row--;
-
-    } while(row > 0u);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q15_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
-  q15_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
-  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A of Q15 type */
-  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B of Q15 type */
-  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
-  q15_t *px;                                     /* Temporary output data matrix pointer */
-  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
-  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
-  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
-  uint16_t col, i = 0u, row = numRowsA, colCnt;  /* loop counters */
-  arm_status status;                             /* status of matrix multiplication */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-  /* Check for matrix mismatch condition */
-  if((pSrcA->numCols != pSrcB->numRows) ||
-     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
-    /* row loop */
-    do
-    {
-      /* Output pointer is set to starting address of the row being processed */
-      px = pOut + i;
-
-      /* For every row wise process, the column loop counter is to be initiated */
-      col = numColsB;
-
-      /* For every row wise process, the pIn2 pointer is set          
-       ** to the starting address of the pSrcB data */
-      pIn2 = pSrcB->pData;
-
-      /* column loop */
-      do
-      {
-        /* Set the variable sum, that acts as accumulator, to zero */
-        sum = 0;
-
-        /* Initiate the pointer pIn1 to point to the starting address of pSrcA */
-        pIn1 = pInA;
-
-        /* Matrix A columns number of MAC operations are to be performed */
-        colCnt = numColsA;
-
-        /* matrix multiplication */
-        while(colCnt > 0u)
-        {
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-          /* Perform the multiply-accumulates */
-          sum += (q31_t) * pIn1++ * *pIn2;
-          pIn2 += numColsB;
-
-          /* Decrement the loop counter */
-          colCnt--;
-        }
-
-        /* Convert the result from 34.30 to 1.15 format and store the saturated value in destination buffer */
-        /* Saturate and store the result in the destination buffer */
-        *px++ = (q15_t) __SSAT((sum >> 15), 16);
-
-        /* Decrement the column loop counter */
-        col--;
-
-        /* Update the pointer pIn2 to point to the  starting address of the next column */
-        pIn2 = pInB + (numColsB - col);
-
-      } while(col > 0u);
-
-      /* Update the pointer pSrcA to point to the  starting address of the next row */
-      i = i + numColsB;
-      pInA = pInA + numColsA;
-
-      /* Decrement the row loop counter */
-      row--;
-
-    } while(row > 0u);
-
-#endif /* #ifndef ARM_MATH_CM0 */
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-/**        
- * @} end of MatrixMult group        
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q31.c
deleted file mode 100644
index 54026e3db4..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q31.c
+++ /dev/null
@@ -1,292 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_mult_q31.c    
-*    
-* Description:	 Q31 matrix multiplication.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-*    incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupMatrix    
- */
-
-/**    
- * @addtogroup MatrixMult    
- * @{    
- */
-
-/**    
- * @brief Q31 matrix multiplication    
- * @param[in]       *pSrcA points to the first input matrix structure    
- * @param[in]       *pSrcB points to the second input matrix structure    
- * @param[out]      *pDst points to output matrix structure    
- * @return     		The function returns either    
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The function is implemented using an internal 64-bit accumulator.    
- * The accumulator has a 2.62 format and maintains full precision of the intermediate    
- * multiplication results but provides only a single guard bit. There is no saturation    
- * on intermediate additions. Thus, if the accumulator overflows it wraps around and    
- * distorts the result. The input signals should be scaled down to avoid intermediate    
- * overflows. The input is thus scaled down by log2(numColsA) bits    
- * to avoid overflows, as a total of numColsA additions are performed internally.    
- * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.    
- *    
- * \par    
- * See arm_mat_mult_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.    
- *    
- */
-
-arm_status arm_mat_mult_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst)
-{
-  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
-  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
-  q31_t *pInA = pSrcA->pData;                    /* input data matrix pointer A */
-  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
-  q31_t *px;                                     /* Temporary output data matrix pointer */
-  q63_t sum;                                     /* Accumulator */
-  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
-  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
-  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  uint16_t col, i = 0u, j, row = numRowsA, colCnt;      /* loop counters */
-  arm_status status;                             /* status of matrix multiplication */
-  q31_t a0, a1, a2, a3, b0, b1, b2, b3;
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
-  /* Check for matrix mismatch condition */
-  if((pSrcA->numCols != pSrcB->numRows) ||
-     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
-    /* row loop */
-    do
-    {
-      /* Output pointer is set to starting address of the row being processed */
-      px = pOut + i;
-
-      /* For every row wise process, the column loop counter is to be initiated */
-      col = numColsB;
-
-      /* For every row wise process, the pIn2 pointer is set    
-       ** to the starting address of the pSrcB data */
-      pIn2 = pSrcB->pData;
-
-      j = 0u;
-
-      /* column loop */
-      do
-      {
-        /* Set the variable sum, that acts as accumulator, to zero */
-        sum = 0;
-
-        /* Initiate the pointer pIn1 to point to the starting address of pInA */
-        pIn1 = pInA;
-
-        /* Apply loop unrolling and compute 4 MACs simultaneously. */
-        colCnt = numColsA >> 2;
-
-
-        /* matrix multiplication */
-        while(colCnt > 0u)
-        {
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-          /* Perform the multiply-accumulates */
-          b0 = *pIn2;
-          pIn2 += numColsB;
-
-          a0 = *pIn1++;
-          a1 = *pIn1++;
-
-          b1 = *pIn2;
-          pIn2 += numColsB;
-          b2 = *pIn2;
-          pIn2 += numColsB;
-
-          sum += (q63_t) a0 *b0;
-          sum += (q63_t) a1 *b1;
-
-          a2 = *pIn1++;
-          a3 = *pIn1++;
-
-          b3 = *pIn2;
-          pIn2 += numColsB;
-
-          sum += (q63_t) a2 *b2;
-          sum += (q63_t) a3 *b3;
-
-          /* Decrement the loop counter */
-          colCnt--;
-        }
-
-        /* If the columns of pSrcA is not a multiple of 4, compute any remaining output samples here.    
-         ** No loop unrolling is used. */
-        colCnt = numColsA % 0x4u;
-
-        while(colCnt > 0u)
-        {
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-          /* Perform the multiply-accumulates */
-          sum += (q63_t) * pIn1++ * *pIn2;
-          pIn2 += numColsB;
-
-          /* Decrement the loop counter */
-          colCnt--;
-        }
-
-        /* Convert the result from 2.62 to 1.31 format and store in destination buffer */
-        *px++ = (q31_t) (sum >> 31);
-
-        /* Update the pointer pIn2 to point to the  starting address of the next column */
-        j++;
-        pIn2 = (pSrcB->pData) + j;
-
-        /* Decrement the column loop counter */
-        col--;
-
-      } while(col > 0u);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q31_t *pInB = pSrcB->pData;                    /* input data matrix pointer B */
-  uint16_t col, i = 0u, row = numRowsA, colCnt;  /* loop counters */
-  arm_status status;                             /* status of matrix multiplication */
-
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-  /* Check for matrix mismatch condition */
-  if((pSrcA->numCols != pSrcB->numRows) ||
-     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
-    /* row loop */
-    do
-    {
-      /* Output pointer is set to starting address of the row being processed */
-      px = pOut + i;
-
-      /* For every row wise process, the column loop counter is to be initiated */
-      col = numColsB;
-
-      /* For every row wise process, the pIn2 pointer is set          
-       ** to the starting address of the pSrcB data */
-      pIn2 = pSrcB->pData;
-
-      /* column loop */
-      do
-      {
-        /* Set the variable sum, that acts as accumulator, to zero */
-        sum = 0;
-
-        /* Initiate the pointer pIn1 to point to the starting address of pInA */
-        pIn1 = pInA;
-
-        /* Matrix A columns number of MAC operations are to be performed */
-        colCnt = numColsA;
-
-        /* matrix multiplication */
-        while(colCnt > 0u)
-        {
-          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
-          /* Perform the multiply-accumulates */
-          sum += (q63_t) * pIn1++ * *pIn2;
-          pIn2 += numColsB;
-
-          /* Decrement the loop counter */
-          colCnt--;
-        }
-
-        /* Convert the result from 2.62 to 1.31 format and store in destination buffer */
-        *px++ = (q31_t) (sum >> 31);
-
-        /* Decrement the column loop counter */
-        col--;
-
-        /* Update the pointer pIn2 to point to the  starting address of the next column */
-        pIn2 = pInB + (numColsB - col);
-
-      } while(col > 0u);
-
-#endif
-
-      /* Update the pointer pInA to point to the  starting address of the next row */
-      i = i + numColsB;
-      pInA = pInA + numColsA;
-
-      /* Decrement the row loop counter */
-      row--;
-
-    } while(row > 0u);
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-  /* Return to application */
-  return (status);
-}
-
-/**    
- * @} end of MatrixMult group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_f32.c
deleted file mode 100644
index 833c282a7c..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_f32.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:        arm_mat_scale_f32.c    
-*    
-* Description:	Multiplies a floating-point matrix by a scalar.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-*    incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**        
- * @ingroup groupMatrix        
- */
-
-/**        
- * @defgroup MatrixScale Matrix Scale        
- *        
- * Multiplies a matrix by a scalar.  This is accomplished by multiplying each element in the        
- * matrix by the scalar.  For example:        
- * \image html MatrixScale.gif "Matrix Scaling of a 3 x 3 matrix"        
- *        
- * The function checks to make sure that the input and output matrices are of the same size.        
- *        
- * In the fixed-point Q15 and Q31 functions, scale is represented by        
- * a fractional multiplication scaleFract and an arithmetic shift shift.        
- * The shift allows the gain of the scaling operation to exceed 1.0.        
- * The overall scale factor applied to the fixed-point data is        
- * 
        
- *     scale = scaleFract * 2^shift.        
- * 
        
- */
-
-/**        
- * @addtogroup MatrixScale        
- * @{        
- */
-
-/**        
- * @brief Floating-point matrix scaling.        
- * @param[in]       *pSrc points to input matrix structure        
- * @param[in]       scale scale factor to be applied         
- * @param[out]      *pDst points to output matrix structure        
- * @return     		The function returns either ARM_MATH_SIZE_MISMATCH         
- * or ARM_MATH_SUCCESS based on the outcome of size checking.        
- *        
- */
-
-arm_status arm_mat_scale_f32(
-  const arm_matrix_instance_f32 * pSrc,
-  float32_t scale,
-  arm_matrix_instance_f32 * pDst)
-{
-  float32_t *pIn = pSrc->pData;                  /* input data matrix pointer */
-  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
-  uint32_t numSamples;                           /* total number of elements in the matrix */
-  uint32_t blkCnt;                               /* loop counters */
-  arm_status status;                             /* status of matrix scaling     */
-
-#ifndef ARM_MATH_CM0
-
-  float32_t in1, in2, in3, in4;                  /* temporary variables */
-  float32_t out1, out2, out3, out4;              /* temporary variables */
-
-#endif //      #ifndef ARM_MATH_CM0
-
-#ifdef ARM_MATH_MATRIX_CHECK
-  /* Check for matrix mismatch condition */
-  if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
-  {
-    /* Total number of samples in the input matrix */
-    numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
-
-#ifndef ARM_MATH_CM0
-
-    /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-    /* Loop Unrolling */
-    blkCnt = numSamples >> 2;
-
-    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-     ** a second loop below computes the remaining 1 to 3 samples. */
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) * scale */
-      /* Scaling and results are stored in the destination buffer. */
-      in1 = pIn[0];
-      in2 = pIn[1];
-      in3 = pIn[2];
-      in4 = pIn[3];
-
-      out1 = in1 * scale;
-      out2 = in2 * scale;
-      out3 = in3 * scale;
-      out4 = in4 * scale;
-
-
-      pOut[0] = out1;
-      pOut[1] = out2;
-      pOut[2] = out3;
-      pOut[3] = out4;
-
-      /* update pointers to process next sampels */
-      pIn += 4u;
-      pOut += 4u;
-
-      /* Decrement the numSamples loop counter */
-      blkCnt--;
-    }
-
-    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
-     ** No loop unrolling is used. */
-    blkCnt = numSamples % 0x4u;
-
-#else
-
-    /* Run the below code for Cortex-M0 */
-
-    /* Initialize blkCnt with number of samples */
-    blkCnt = numSamples;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) * scale */
-      /* The results are stored in the destination buffer. */
-      *pOut++ = (*pIn++) * scale;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* Set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-/**        
- * @} end of MatrixScale group        
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q15.c
deleted file mode 100644
index 684fbcc50c..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q15.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_scale_q15.c    
-*    
-* Description:	Multiplies a Q15 matrix by a scalar.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-*    incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupMatrix    
- */
-
-/**    
- * @addtogroup MatrixScale    
- * @{    
- */
-
-/**    
- * @brief Q15 matrix scaling.    
- * @param[in]       *pSrc points to input matrix    
- * @param[in]       scaleFract fractional portion of the scale factor    
- * @param[in]       shift number of bits to shift the result by    
- * @param[out]      *pDst points to output matrix structure    
- * @return     		The function returns either    
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- * \par    
- * The input data *pSrc and scaleFract are in 1.15 format.    
- * These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format.    
- */
-
-arm_status arm_mat_scale_q15(
-  const arm_matrix_instance_q15 * pSrc,
-  q15_t scaleFract,
-  int32_t shift,
-  arm_matrix_instance_q15 * pDst)
-{
-  q15_t *pIn = pSrc->pData;                      /* input data matrix pointer */
-  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
-  uint32_t numSamples;                           /* total number of elements in the matrix */
-  int32_t totShift = 15 - shift;                 /* total shift to apply after scaling */
-  uint32_t blkCnt;                               /* loop counters */
-  arm_status status;                             /* status of matrix scaling     */
-
-#ifndef ARM_MATH_CM0
-
-  q15_t in1, in2, in3, in4;
-  q31_t out1, out2, out3, out4;
-  q31_t inA1, inA2;
-
-#endif //     #ifndef ARM_MATH_CM0
-
-#ifdef ARM_MATH_MATRIX_CHECK
-  /* Check for matrix mismatch */
-  if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif //    #ifdef ARM_MATH_MATRIX_CHECK
-  {
-    /* Total number of samples in the input matrix */
-    numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
-
-#ifndef ARM_MATH_CM0
-
-    /* Run the below code for Cortex-M4 and Cortex-M3 */
-    /* Loop Unrolling */
-    blkCnt = numSamples >> 2;
-
-    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-     ** a second loop below computes the remaining 1 to 3 samples. */
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) * k */
-      /* Scale, saturate and then store the results in the destination buffer. */
-      /* Reading 2 inputs from memory */
-      inA1 = _SIMD32_OFFSET(pIn);
-      inA2 = _SIMD32_OFFSET(pIn + 2);
-
-      /* C = A * scale */
-      /* Scale the inputs and then store the 2 results in the destination buffer        
-       * in single cycle by packing the outputs */
-      out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract);
-      out2 = (q31_t) ((q15_t) inA1 * scaleFract);
-      out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract);
-      out4 = (q31_t) ((q15_t) inA2 * scaleFract);
-
-      out1 = out1 >> totShift;
-      inA1 = _SIMD32_OFFSET(pIn + 4);
-      out2 = out2 >> totShift;
-      inA2 = _SIMD32_OFFSET(pIn + 6);
-      out3 = out3 >> totShift;
-      out4 = out4 >> totShift;
-
-      in1 = (q15_t) (__SSAT(out1, 16));
-      in2 = (q15_t) (__SSAT(out2, 16));
-      in3 = (q15_t) (__SSAT(out3, 16));
-      in4 = (q15_t) (__SSAT(out4, 16));
-
-      _SIMD32_OFFSET(pOut) = __PKHBT(in2, in1, 16);
-      _SIMD32_OFFSET(pOut + 2) = __PKHBT(in4, in3, 16);
-
-      /* update pointers to process next sampels */
-      pIn += 4u;
-      pOut += 4u;
-
-
-      /* Decrement the numSamples loop counter */
-      blkCnt--;
-    }
-
-    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
-     ** No loop unrolling is used. */
-    blkCnt = numSamples % 0x4u;
-
-#else
-
-    /* Run the below code for Cortex-M0 */
-
-    /* Initialize blkCnt with number of samples */
-    blkCnt = numSamples;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) * k */
-      /* Scale, saturate and then store the results in the destination buffer. */
-      *pOut++ =
-        (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> totShift, 16));
-
-      /* Decrement the numSamples loop counter */
-      blkCnt--;
-    }
-    /* Set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-/**        
- * @} end of MatrixScale group        
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q31.c
deleted file mode 100644
index 7227ad38ae..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q31.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_scale_q31.c    
-*    
-* Description:	Multiplies a Q31 matrix by a scalar.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-*    incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**        
- * @ingroup groupMatrix        
- */
-
-/**        
- * @addtogroup MatrixScale        
- * @{        
- */
-
-/**        
- * @brief Q31 matrix scaling.        
- * @param[in]       *pSrc points to input matrix        
- * @param[in]       scaleFract fractional portion of the scale factor        
- * @param[in]       shift number of bits to shift the result by        
- * @param[out]      *pDst points to output matrix structure        
- * @return     		The function returns either        
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.        
- *        
- * @details        
- * Scaling and Overflow Behavior:        
- * \par        
- * The input data *pSrc and scaleFract are in 1.31 format.        
- * These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format.        
- */
-
-arm_status arm_mat_scale_q31(
-  const arm_matrix_instance_q31 * pSrc,
-  q31_t scaleFract,
-  int32_t shift,
-  arm_matrix_instance_q31 * pDst)
-{
-  q31_t *pIn = pSrc->pData;                      /* input data matrix pointer */
-  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
-  uint32_t numSamples;                           /* total number of elements in the matrix */
-  int32_t totShift = shift + 1;                  /* shift to apply after scaling */
-  uint32_t blkCnt;                               /* loop counters  */
-  arm_status status;                             /* status of matrix scaling      */
-  q31_t in1, in2, out1;                          /* temporary variabels */
-
-#ifndef ARM_MATH_CM0
-
-  q31_t in3, in4, out2, out3, out4;              /* temporary variables */
-
-#endif //      #ifndef ARM_MAT_CM0
-
-#ifdef ARM_MATH_MATRIX_CHECK
-  /* Check for matrix mismatch  */
-  if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif //    #ifdef ARM_MATH_MATRIX_CHECK
-  {
-    /* Total number of samples in the input matrix */
-    numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
-
-#ifndef ARM_MATH_CM0
-
-    /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-    /* Loop Unrolling */
-    blkCnt = numSamples >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-     ** a second loop below computes the remaining 1 to 3 samples. */
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) * k */
-      /* Read values from input */
-      in1 = *pIn;
-      in2 = *(pIn + 1);
-      in3 = *(pIn + 2);
-      in4 = *(pIn + 3);
-
-      /* multiply input with scaler value */
-      in1 = ((q63_t) in1 * scaleFract) >> 32;
-      in2 = ((q63_t) in2 * scaleFract) >> 32;
-      in3 = ((q63_t) in3 * scaleFract) >> 32;
-      in4 = ((q63_t) in4 * scaleFract) >> 32;
-
-      /* apply shifting */
-      out1 = in1 << totShift;
-      out2 = in2 << totShift;
-
-      /* saturate the results. */
-      if(in1 != (out1 >> totShift))
-        out1 = 0x7FFFFFFF ^ (in1 >> 31);
-
-      if(in2 != (out2 >> totShift))
-        out2 = 0x7FFFFFFF ^ (in2 >> 31);
-
-      out3 = in3 << totShift;
-      out4 = in4 << totShift;
-
-      *pOut = out1;
-      *(pOut + 1) = out2;
-
-      if(in3 != (out3 >> totShift))
-        out3 = 0x7FFFFFFF ^ (in3 >> 31);
-
-      if(in4 != (out4 >> totShift))
-        out4 = 0x7FFFFFFF ^ (in4 >> 31);
-
-
-      *(pOut + 2) = out3;
-      *(pOut + 3) = out4;
-
-      /* update pointers to process next sampels */
-      pIn += 4u;
-      pOut += 4u;
-
-
-      /* Decrement the numSamples loop counter */
-      blkCnt--;
-    }
-
-    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
-     ** No loop unrolling is used. */
-    blkCnt = numSamples % 0x4u;
-
-#else
-
-    /* Run the below code for Cortex-M0 */
-
-    /* Initialize blkCnt with number of samples */
-    blkCnt = numSamples;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) * k */
-      /* Scale, saturate and then store the results in the destination buffer. */
-      in1 = *pIn++;
-
-      in2 = ((q63_t) in1 * scaleFract) >> 32;
-
-      out1 = in2 << totShift;
-
-      if(in2 != (out1 >> totShift))
-        out1 = 0x7FFFFFFF ^ (in2 >> 31);
-
-      *pOut++ = out1;
-
-      /* Decrement the numSamples loop counter */
-      blkCnt--;
-    }
-
-    /* Set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-/**        
- * @} end of MatrixScale group        
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_f32.c
deleted file mode 100644
index 6ee7a46c8f..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_f32.c
+++ /dev/null
@@ -1,207 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_sub_f32.c    
-*    
-* Description:	Floating-point matrix subtraction.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-*    incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**        
- * @ingroup groupMatrix        
- */
-
-/**        
- * @defgroup MatrixSub Matrix Subtraction        
- *        
- * Subtract two matrices.        
- * \image html MatrixSubtraction.gif "Subraction of two 3 x 3 matrices"        
- *        
- * The functions check to make sure that        
- * pSrcA, pSrcB, and pDst have the same        
- * number of rows and columns.        
- */
-
-/**        
- * @addtogroup MatrixSub        
- * @{        
- */
-
-/**        
- * @brief Floating-point matrix subtraction        
- * @param[in]       *pSrcA points to the first input matrix structure        
- * @param[in]       *pSrcB points to the second input matrix structure        
- * @param[out]      *pDst points to output matrix structure        
- * @return     		The function returns either        
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.        
- */
-
-arm_status arm_mat_sub_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst)
-{
-  float32_t *pIn1 = pSrcA->pData;                /* input data matrix pointer A */
-  float32_t *pIn2 = pSrcB->pData;                /* input data matrix pointer B */
-  float32_t *pOut = pDst->pData;                 /* output data matrix pointer  */
-
-#ifndef ARM_MATH_CM0
-
-  float32_t inA1, inA2, inB1, inB2, out1, out2;  /* temporary variables */
-
-#endif //      #ifndef ARM_MATH_CM0
-
-  uint32_t numSamples;                           /* total number of elements in the matrix  */
-  uint32_t blkCnt;                               /* loop counters */
-  arm_status status;                             /* status of matrix subtraction */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-  /* Check for matrix mismatch condition */
-  if((pSrcA->numRows != pSrcB->numRows) ||
-     (pSrcA->numCols != pSrcB->numCols) ||
-     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
-  {
-    /* Total number of samples in the input matrix */
-    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
-
-#ifndef ARM_MATH_CM0
-
-    /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-    /* Loop Unrolling */
-    blkCnt = numSamples >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-     ** a second loop below computes the remaining 1 to 3 samples. */
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) - B(m,n) */
-      /* Subtract and then store the results in the destination buffer. */
-      /* Read values from source A */
-      inA1 = pIn1[0];
-
-      /* Read values from source B */
-      inB1 = pIn2[0];
-
-      /* Read values from source A */
-      inA2 = pIn1[1];
-
-      /* out = sourceA - sourceB */
-      out1 = inA1 - inB1;
-
-      /* Read values from source B */
-      inB2 = pIn2[1];
-
-      /* Read values from source A */
-      inA1 = pIn1[2];
-
-      /* out = sourceA - sourceB */
-      out2 = inA2 - inB2;
-
-      /* Read values from source B */
-      inB1 = pIn2[2];
-
-      /* Store result in destination */
-      pOut[0] = out1;
-      pOut[1] = out2;
-
-      /* Read values from source A */
-      inA2 = pIn1[3];
-
-      /* Read values from source B */
-      inB2 = pIn2[3];
-
-      /* out = sourceA - sourceB */
-      out1 = inA1 - inB1;
-
-
-      /* out = sourceA - sourceB */
-      out2 = inA2 - inB2;
-
-      /* Store result in destination */
-      pOut[2] = out1;
-
-      /* Store result in destination */
-      pOut[3] = out2;
-
-
-      /* update pointers to process next sampels */
-      pIn1 += 4u;
-      pIn2 += 4u;
-      pOut += 4u;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.    
-     ** No loop unrolling is used. */
-    blkCnt = numSamples % 0x4u;
-
-#else
-
-    /* Run the below code for Cortex-M0 */
-
-    /* Initialize blkCnt with number of samples */
-    blkCnt = numSamples;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) - B(m,n) */
-      /* Subtract and then store the results in the destination buffer. */
-      *pOut++ = (*pIn1++) - (*pIn2++);
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* Set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-/**        
- * @} end of MatrixSub group        
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q15.c
deleted file mode 100644
index ea32f04bd1..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q15.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_sub_q15.c    
-*    
-* Description:	Q15 Matrix subtraction    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-*    incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupMatrix    
- */
-
-/**    
- * @addtogroup MatrixSub    
- * @{    
- */
-
-/**    
- * @brief Q15 matrix subtraction.    
- * @param[in]       *pSrcA points to the first input matrix structure    
- * @param[in]       *pSrcB points to the second input matrix structure    
- * @param[out]      *pDst points to output matrix structure    
- * @return     		The function returns either    
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.    
- *    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function uses saturating arithmetic.    
- * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.    
- */
-
-arm_status arm_mat_sub_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst)
-{
-  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A */
-  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B */
-  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
-  uint32_t numSamples;                           /* total number of elements in the matrix */
-  uint32_t blkCnt;                               /* loop counters  */
-  arm_status status;                             /* status of matrix subtraction  */
-
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
-  /* Check for matrix mismatch condition */
-  if((pSrcA->numRows != pSrcB->numRows) ||
-     (pSrcA->numCols != pSrcB->numCols) ||
-     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-    /* Total number of samples in the input matrix */
-    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
-
-#ifndef ARM_MATH_CM0
-
-    /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-    /* Apply loop unrolling */
-    blkCnt = numSamples >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-     ** a second loop below computes the remaining 1 to 3 samples. */
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) - B(m,n) */
-      /* Subtract, Saturate and then store the results in the destination buffer. */
-      *__SIMD32(pOut)++ = __QSUB16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
-      *__SIMD32(pOut)++ = __QSUB16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-     ** No loop unrolling is used. */
-    blkCnt = numSamples % 0x4u;
-
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) - B(m,n) */
-      /* Subtract and then store the results in the destination buffer. */
-      *pOut++ = (q15_t) __QSUB16(*pInA++, *pInB++);
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-#else
-
-    /* Run the below code for Cortex-M0 */
-
-    /* Initialize blkCnt with number of samples */
-    blkCnt = numSamples;
-
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) - B(m,n) */
-      /* Subtract and then store the results in the destination buffer. */
-      *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16);
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-    /* Set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-/**    
- * @} end of MatrixSub group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q31.c
deleted file mode 100644
index 157d59b725..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q31.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_sub_q31.c    
-*    
-* Description:	Q31 matrix subtraction    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-*    incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**        
- * @ingroup groupMatrix        
- */
-
-/**        
- * @addtogroup MatrixSub        
- * @{        
- */
-
-/**        
- * @brief Q31 matrix subtraction.        
- * @param[in]       *pSrcA points to the first input matrix structure        
- * @param[in]       *pSrcB points to the second input matrix structure        
- * @param[out]      *pDst points to output matrix structure        
- * @return     		The function returns either        
- * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.        
- *        
- * Scaling and Overflow Behavior:        
- * \par        
- * The function uses saturating arithmetic.        
- * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.        
- */
-
-
-arm_status arm_mat_sub_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst)
-{
-  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
-  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
-  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
-  q31_t inA1, inB1;                              /* temporary variables */
-
-#ifndef ARM_MATH_CM0
-
-  q31_t inA2, inB2;                              /* temporary variables */
-  q31_t out1, out2;                              /* temporary variables */
-
-#endif //      #ifndef ARM_MATH_CM0
-
-  uint32_t numSamples;                           /* total number of elements in the matrix  */
-  uint32_t blkCnt;                               /* loop counters */
-  arm_status status;                             /* status of matrix subtraction */
-
-
-#ifdef ARM_MATH_MATRIX_CHECK
-  /* Check for matrix mismatch condition  */
-  if((pSrcA->numRows != pSrcB->numRows) ||
-     (pSrcA->numCols != pSrcB->numCols) ||
-     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif
-  {
-    /* Total number of samples in the input matrix */
-    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
-
-#ifndef ARM_MATH_CM0
-
-    /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-    /* Loop Unrolling */
-    blkCnt = numSamples >> 2u;
-
-    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-     ** a second loop below computes the remaining 1 to 3 samples. */
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) - B(m,n) */
-      /* Subtract, saturate and then store the results in the destination buffer. */
-      /* Read values from source A */
-      inA1 = pIn1[0];
-
-      /* Read values from source B */
-      inB1 = pIn2[0];
-
-      /* Read values from source A */
-      inA2 = pIn1[1];
-
-      /* Subtract and saturate */
-      out1 = __QSUB(inA1, inB1);
-
-      /* Read values from source B */
-      inB2 = pIn2[1];
-
-      /* Read values from source A */
-      inA1 = pIn1[2];
-
-      /* Subtract and saturate */
-      out2 = __QSUB(inA2, inB2);
-
-      /* Read values from source B */
-      inB1 = pIn2[2];
-
-      /* Store result in destination */
-      pOut[0] = out1;
-      pOut[1] = out2;
-
-      /* Read values from source A */
-      inA2 = pIn1[3];
-
-      /* Read values from source B */
-      inB2 = pIn2[3];
-
-      /* Subtract and saturate */
-      out1 = __QSUB(inA1, inB1);
-
-      /* Subtract and saturate */
-      out2 = __QSUB(inA2, inB2);
-
-      /* Store result in destination */
-      pOut[2] = out1;
-      pOut[3] = out2;
-
-      /* update pointers to process next samples */
-      pIn1 += 4u;
-      pIn2 += 4u;
-      pOut += 4u;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.        
-     ** No loop unrolling is used. */
-    blkCnt = numSamples % 0x4u;
-
-#else
-
-    /* Run the below code for Cortex-M0 */
-
-    /* Initialize blkCnt with number of samples */
-    blkCnt = numSamples;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-    while(blkCnt > 0u)
-    {
-      /* C(m,n) = A(m,n) - B(m,n) */
-      /* Subtract, saturate and then store the results in the destination buffer. */
-      inA1 = *pIn1++;
-      inB1 = *pIn2++;
-
-      inA1 = __QSUB(inA1, inB1);
-
-      *pOut++ = inA1;
-
-      /* Decrement the loop counter */
-      blkCnt--;
-    }
-
-    /* Set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-/**        
- * @} end of MatrixSub group        
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_f32.c
deleted file mode 100644
index 721b512b79..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_f32.c
+++ /dev/null
@@ -1,216 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_trans_f32.c    
-*    
-* Description:	Floating-point matrix transpose.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-*    incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------- */
-
-/**    
- * @defgroup MatrixTrans Matrix Transpose    
- *    
- * Tranposes a matrix.    
- * Transposing an M x N matrix flips it around the center diagonal and results in an N x M matrix.    
- * \image html MatrixTranspose.gif "Transpose of a 3 x 3 matrix"    
- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupMatrix    
- */
-
-/**    
- * @addtogroup MatrixTrans    
- * @{    
- */
-
-/**    
-  * @brief Floating-point matrix transpose.    
-  * @param[in]  *pSrc points to the input matrix    
-  * @param[out] *pDst points to the output matrix    
-  * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH    
-  * or ARM_MATH_SUCCESS based on the outcome of size checking.    
-  */
-
-
-arm_status arm_mat_trans_f32(
-  const arm_matrix_instance_f32 * pSrc,
-  arm_matrix_instance_f32 * pDst)
-{
-  float32_t *pIn = pSrc->pData;                  /* input data matrix pointer */
-  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
-  float32_t *px;                                 /* Temporary output data matrix pointer */
-  uint16_t nRows = pSrc->numRows;                /* number of rows */
-  uint16_t nColumns = pSrc->numCols;             /* number of columns */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  uint16_t blkCnt, i = 0u, row = nRows;          /* loop counters */
-  arm_status status;                             /* status of matrix transpose  */
-
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
-  /* Check for matrix mismatch condition */
-  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-    /* Matrix transpose by exchanging the rows with columns */
-    /* row loop     */
-    do
-    {
-      /* Loop Unrolling */
-      blkCnt = nColumns >> 2;
-
-      /* The pointer px is set to starting address of the column being processed */
-      px = pOut + i;
-
-      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-       ** a second loop below computes the remaining 1 to 3 samples. */
-      while(blkCnt > 0u)        /* column loop */
-      {
-        /* Read and store the input element in the destination */
-        *px = *pIn++;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += nRows;
-
-        /* Read and store the input element in the destination */
-        *px = *pIn++;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += nRows;
-
-        /* Read and store the input element in the destination */
-        *px = *pIn++;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += nRows;
-
-        /* Read and store the input element in the destination */
-        *px = *pIn++;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += nRows;
-
-        /* Decrement the column loop counter */
-        blkCnt--;
-      }
-
-      /* Perform matrix transpose for last 3 samples here. */
-      blkCnt = nColumns % 0x4u;
-
-      while(blkCnt > 0u)
-      {
-        /* Read and store the input element in the destination */
-        *px = *pIn++;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += nRows;
-
-        /* Decrement the column loop counter */
-        blkCnt--;
-      }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  uint16_t col, i = 0u, row = nRows;             /* loop counters */
-  arm_status status;                             /* status of matrix transpose  */
-
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-  /* Check for matrix mismatch condition */
-  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-    /* Matrix transpose by exchanging the rows with columns */
-    /* row loop     */
-    do
-    {
-      /* The pointer px is set to starting address of the column being processed */
-      px = pOut + i;
-
-      /* Initialize column loop counter */
-      col = nColumns;
-
-      while(col > 0u)
-      {
-        /* Read and store the input element in the destination */
-        *px = *pIn++;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += nRows;
-
-        /* Decrement the column loop counter */
-        col--;
-      }
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-      i++;
-
-      /* Decrement the row loop counter */
-      row--;
-
-    } while(row > 0u);          /* row loop end  */
-
-    /* Set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-/**    
- * @} end of MatrixTrans group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q15.c
deleted file mode 100644
index bb03e72de0..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q15.c
+++ /dev/null
@@ -1,282 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_trans_q15.c    
-*    
-* Description:	Q15 matrix transpose.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-*    incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupMatrix    
- */
-
-/**    
- * @addtogroup MatrixTrans    
- * @{    
- */
-
-/*    
- * @brief Q15 matrix transpose.    
- * @param[in]  *pSrc points to the input matrix    
- * @param[out] *pDst points to the output matrix    
- * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH    
- * or ARM_MATH_SUCCESS based on the outcome of size checking.    
- */
-
-arm_status arm_mat_trans_q15(
-  const arm_matrix_instance_q15 * pSrc,
-  arm_matrix_instance_q15 * pDst)
-{
-  q15_t *pSrcA = pSrc->pData;                    /* input data matrix pointer */
-  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
-  uint16_t nRows = pSrc->numRows;                /* number of nRows */
-  uint16_t nColumns = pSrc->numCols;             /* number of nColumns */
-  uint16_t col, row = nRows, i = 0u;             /* row and column loop counters */
-  arm_status status;                             /* status of matrix transpose */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-  q31_t in;                                      /* variable to hold temporary output  */
-
-#else
-
-  q15_t in;
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
-  /* Check for matrix mismatch condition */
-  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-    /* Matrix transpose by exchanging the rows with columns */
-    /* row loop     */
-    do
-    {
-
-      /* Apply loop unrolling and exchange the columns with row elements */
-      col = nColumns >> 2u;
-
-      /* The pointer pOut is set to starting address of the column being processed */
-      pOut = pDst->pData + i;
-
-      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-       ** a second loop below computes the remaining 1 to 3 samples. */
-      while(col > 0u)
-      {
-#ifndef UNALIGNED_SUPPORT_DISABLE
-
-        /* Read two elements from the row */
-        in = *__SIMD32(pSrcA)++;
-
-        /* Unpack and store one element in the destination */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        *pOut = (q15_t) in;
-
-#else
-
-        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
-
-        /* Update the pointer pOut to point to the next row of the transposed matrix */
-        pOut += nRows;
-
-        /* Unpack and store the second element in the destination */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#else
-
-        *pOut = (q15_t) in;
-
-#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
-
-        /* Update the pointer pOut to point to the next row of the transposed matrix */
-        pOut += nRows;
-
-        /* Read two elements from the row */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        in = *__SIMD32(pSrcA)++;
-
-#else
-
-        in = *__SIMD32(pSrcA)++;
-
-#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
-
-        /* Unpack and store one element in the destination */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        *pOut = (q15_t) in;
-
-#else
-
-        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
-
-        /* Update the pointer pOut to point to the next row of the transposed matrix */
-        pOut += nRows;
-
-        /* Unpack and store the second element in the destination */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
-
-#else
-
-        *pOut = (q15_t) in;
-
-#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
-
-#else	 
-        /* Read one element from the row */
-        in = *pSrcA++;
-
-        /* Store one element in the destination */
-        *pOut = in;
- 
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        pOut += nRows;
-
-        /* Read one element from the row */
-        in = *pSrcA++;
-
-        /* Store one element in the destination */
-        *pOut = in;
- 
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        pOut += nRows;
-
-        /* Read one element from the row */
-        in = *pSrcA++;
-
-        /* Store one element in the destination */
-        *pOut = in;
- 
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        pOut += nRows;
-
-        /* Read one element from the row */
-        in = *pSrcA++;
-
-        /* Store one element in the destination */
-        *pOut = in;
-
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-        /* Update the pointer pOut to point to the next row of the transposed matrix */
-        pOut += nRows;
-
-        /* Decrement the column loop counter */
-        col--;
-      }
-
-      /* Perform matrix transpose for last 3 samples here. */
-      col = nColumns % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-  /* Check for matrix mismatch condition */
-  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-    /* Matrix transpose by exchanging the rows with columns */
-    /* row loop     */
-    do
-    {
-      /* The pointer pOut is set to starting address of the column being processed */
-      pOut = pDst->pData + i;
-
-      /* Initialize column loop counter */
-      col = nColumns;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-      while(col > 0u)
-      {
-        /* Read and store the input element in the destination */
-        *pOut = *pSrcA++;
-
-        /* Update the pointer pOut to point to the next row of the transposed matrix */
-        pOut += nRows;
-
-        /* Decrement the column loop counter */
-        col--;
-      }
-
-      i++;
-
-      /* Decrement the row loop counter */
-      row--;
-
-    } while(row > 0u);
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-  /* Return to application */
-  return (status);
-}
-
-/**    
- * @} end of MatrixTrans group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q31.c
deleted file mode 100644
index 70cb018605..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q31.c
+++ /dev/null
@@ -1,208 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_mat_trans_q31.c    
-*    
-* Description:	Q31 matrix transpose.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-*    incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupMatrix    
- */
-
-/**    
- * @addtogroup MatrixTrans    
- * @{    
- */
-
-/*    
-  * @brief Q31 matrix transpose.    
-  * @param[in]  *pSrc points to the input matrix    
-  * @param[out] *pDst points to the output matrix    
-  * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH    
-  * or ARM_MATH_SUCCESS based on the outcome of size checking.    
- */
-
-arm_status arm_mat_trans_q31(
-  const arm_matrix_instance_q31 * pSrc,
-  arm_matrix_instance_q31 * pDst)
-{
-  q31_t *pIn = pSrc->pData;                      /* input data matrix pointer  */
-  q31_t *pOut = pDst->pData;                     /* output data matrix pointer  */
-  q31_t *px;                                     /* Temporary output data matrix pointer */
-  uint16_t nRows = pSrc->numRows;                /* number of nRows */
-  uint16_t nColumns = pSrc->numCols;             /* number of nColumns  */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  uint16_t blkCnt, i = 0u, row = nRows;          /* loop counters */
-  arm_status status;                             /* status of matrix transpose */
-
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-
-  /* Check for matrix mismatch condition */
-  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-    /* Matrix transpose by exchanging the rows with columns */
-    /* row loop     */
-    do
-    {
-      /* Apply loop unrolling and exchange the columns with row elements */
-      blkCnt = nColumns >> 2u;
-
-      /* The pointer px is set to starting address of the column being processed */
-      px = pOut + i;
-
-      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-       ** a second loop below computes the remaining 1 to 3 samples. */
-      while(blkCnt > 0u)
-      {
-        /* Read and store the input element in the destination */
-        *px = *pIn++;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += nRows;
-
-        /* Read and store the input element in the destination */
-        *px = *pIn++;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += nRows;
-
-        /* Read and store the input element in the destination */
-        *px = *pIn++;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += nRows;
-
-        /* Read and store the input element in the destination */
-        *px = *pIn++;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += nRows;
-
-        /* Decrement the column loop counter */
-        blkCnt--;
-      }
-
-      /* Perform matrix transpose for last 3 samples here. */
-      blkCnt = nColumns % 0x4u;
-
-      while(blkCnt > 0u)
-      {
-        /* Read and store the input element in the destination */
-        *px = *pIn++;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += nRows;
-
-        /* Decrement the column loop counter */
-        blkCnt--;
-      }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  uint16_t col, i = 0u, row = nRows;             /* loop counters */
-  arm_status status;                             /* status of matrix transpose */
-
-
-#ifdef ARM_MATH_MATRIX_CHECK
-
-  /* Check for matrix mismatch condition */
-  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
-  {
-    /* Set status as ARM_MATH_SIZE_MISMATCH */
-    status = ARM_MATH_SIZE_MISMATCH;
-  }
-  else
-#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
-
-  {
-    /* Matrix transpose by exchanging the rows with columns */
-    /* row loop     */
-    do
-    {
-      /* The pointer px is set to starting address of the column being processed */
-      px = pOut + i;
-
-      /* Initialize column loop counter */
-      col = nColumns;
-
-      while(col > 0u)
-      {
-        /* Read and store the input element in the destination */
-        *px = *pIn++;
-
-        /* Update the pointer px to point to the next row of the transposed matrix */
-        px += nRows;
-
-        /* Decrement the column loop counter */
-        col--;
-      }
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-      i++;
-
-      /* Decrement the row loop counter */
-      row--;
-
-    }
-    while(row > 0u);            /* row loop end */
-
-    /* set status as ARM_MATH_SUCCESS */
-    status = ARM_MATH_SUCCESS;
-  }
-
-  /* Return to application */
-  return (status);
-}
-
-/**    
- * @} end of MatrixTrans group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_f32.c
deleted file mode 100644
index 06a348cd42..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_f32.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_max_f32.c    
-*    
-* Description:	Maximum value of a floating-point vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @defgroup Max Maximum    
- *    
- * Computes the maximum value of an array of data.     
- * The function returns both the maximum value and its position within the array.     
- * There are separate functions for floating-point, Q31, Q15, and Q7 data types.    
- */
-
-/**    
- * @addtogroup Max    
- * @{    
- */
-
-
-/**    
- * @brief Maximum value of a floating-point vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult maximum value returned here    
- * @param[out]      *pIndex index of maximum value returned here    
- * @return none.    
- */
-
-void arm_max_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult,
-  uint32_t * pIndex)
-{
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  float32_t maxVal1, maxVal2, out;               /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex, count;              /* loop counter */
-
-  /* Initialise the count value. */
-  count = 0u;
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-  /* Loop unrolling */
-  blkCnt = (blockSize - 1u) >> 2u;
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  while(blkCnt > 0u)
-  {
-    /* Initialize maxVal to the next consecutive values one by one */
-    maxVal1 = *pSrc++;
-
-    maxVal2 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal1)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal1;
-      outIndex = count + 1u;
-    }
-
-    maxVal1 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal2)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal2;
-      outIndex = count + 2u;
-    }
-
-    maxVal2 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal1)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal1;
-      outIndex = count + 3u;
-    }
-
-    /* compare for the maximum value */
-    if(out < maxVal2)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal2;
-      outIndex = count + 4u;
-    }
-
-    count += 4u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* if (blockSize - 1u) is not multiple of 4 */
-  blkCnt = (blockSize - 1u) % 4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  float32_t maxVal1, out;                        /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex;                     /* loop counter */
-
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-  blkCnt = (blockSize - 1u);
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* Initialize maxVal to the next consecutive values one by one */
-    maxVal1 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal1)
-    {
-      /* Update the maximum value and it's index */
-      out = maxVal1;
-      outIndex = blockSize - blkCnt;
-    }
-
-
-    /* Decrement the loop counter */
-    blkCnt--;
-
-  }
-
-  /* Store the maximum value and it's index into destination pointers */
-  *pResult = out;
-  *pIndex = outIndex;
-}
-
-/**    
- * @} end of Max group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q15.c
deleted file mode 100644
index 5544cde57e..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q15.c
+++ /dev/null
@@ -1,168 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_max_q15.c    
-*    
-* Description:	Maximum value of a Q15 vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @addtogroup Max    
- * @{    
- */
-
-
-/**    
- * @brief Maximum value of a Q15 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult maximum value returned here    
- * @param[out]      *pIndex index of maximum value returned here    
- * @return none.    
- */
-
-void arm_max_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult,
-  uint32_t * pIndex)
-{
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  q15_t maxVal1, maxVal2, out;                   /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex, count;              /* loop counter */
-
-  /* Initialise the count value. */
-  count = 0u;
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-  /* Loop unrolling */
-  blkCnt = (blockSize - 1u) >> 2u;
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  while(blkCnt > 0u)
-  {
-    /* Initialize maxVal to the next consecutive values one by one */
-    maxVal1 = *pSrc++;
-
-    maxVal2 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal1)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal1;
-      outIndex = count + 1u;
-    }
-
-    maxVal1 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal2)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal2;
-      outIndex = count + 2u;
-    }
-
-    maxVal2 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal1)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal1;
-      outIndex = count + 3u;
-    }
-
-    /* compare for the maximum value */
-    if(out < maxVal2)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal2;
-      outIndex = count + 4u;
-    }
-
-    count += 4u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* if (blockSize - 1u) is not multiple of 4 */
-  blkCnt = (blockSize - 1u) % 4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  q15_t maxVal1, out;                            /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex;                     /* loop counter */
-
-  blkCnt = (blockSize - 1u);
-
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* Initialize maxVal to the next consecutive values one by one */
-    maxVal1 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal1)
-    {
-      /* Update the maximum value and it's index */
-      out = maxVal1;
-      outIndex = blockSize - blkCnt;
-    }
-    /* Decrement the loop counter */
-    blkCnt--;
-
-  }
-
-  /* Store the maximum value and its index into destination pointers */
-  *pResult = out;
-  *pIndex = outIndex;
-}
-
-/**    
- * @} end of Max group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q31.c
deleted file mode 100644
index 208f2b67b9..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q31.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_max_q31.c    
-*    
-* Description:	Maximum value of a Q31 vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @addtogroup Max    
- * @{    
- */
-
-
-/**    
- * @brief Maximum value of a Q31 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult maximum value returned here    
- * @param[out]      *pIndex index of maximum value returned here    
- * @return none.    
- */
-
-void arm_max_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult,
-  uint32_t * pIndex)
-{
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  q31_t maxVal1, maxVal2, out;                   /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex, count;              /* loop counter */
-
-  /* Initialise the count value. */
-  count = 0u;
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-  /* Loop unrolling */
-  blkCnt = (blockSize - 1u) >> 2u;
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  while(blkCnt > 0u)
-  {
-    /* Initialize maxVal to the next consecutive values one by one */
-    maxVal1 = *pSrc++;
-
-    maxVal2 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal1)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal1;
-      outIndex = count + 1u;
-    }
-
-    maxVal1 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal2)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal2;
-      outIndex = count + 2u;
-    }
-
-    maxVal2 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal1)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal1;
-      outIndex = count + 3u;
-    }
-
-    /* compare for the maximum value */
-    if(out < maxVal2)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal2;
-      outIndex = count + 4u;
-    }
-
-    count += 4u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* if (blockSize - 1u) is not multiple of 4 */
-  blkCnt = (blockSize - 1u) % 4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  q31_t maxVal1, out;                            /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex;                     /* loop counter */
-
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-  blkCnt = (blockSize - 1u);
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* Initialize maxVal to the next consecutive values one by one */
-    maxVal1 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal1)
-    {
-      /* Update the maximum value and it's index */
-      out = maxVal1;
-      outIndex = blockSize - blkCnt;
-    }
-
-    /* Decrement the loop counter */
-    blkCnt--;
-
-  }
-
-  /* Store the maximum value and its index into destination pointers */
-  *pResult = out;
-  *pIndex = outIndex;
-}
-
-/**    
- * @} end of Max group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q7.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q7.c
deleted file mode 100644
index 22ee440443..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q7.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_max_q7.c    
-*    
-* Description:	Maximum value of a Q7 vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @addtogroup Max    
- * @{    
- */
-
-
-/**    
- * @brief Maximum value of a Q7 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult maximum value returned here    
- * @param[out]      *pIndex index of maximum value returned here    
-  * @return none.    
- */
-
-void arm_max_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q7_t * pResult,
-  uint32_t * pIndex)
-{
-#ifndef ARM_MATH_CM0
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q7_t maxVal1, maxVal2, out;                    /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex, count;              /* loop counter */
-
-  /* Initialise the count value. */
-  count = 0u;
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-  /* Loop unrolling */
-  blkCnt = (blockSize - 1u) >> 2u;
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  while(blkCnt > 0u)
-  {
-    /* Initialize maxVal to the next consecutive values one by one */
-    maxVal1 = *pSrc++;
-
-    maxVal2 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal1)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal1;
-      outIndex = count + 1u;
-    }
-
-    maxVal1 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal2)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal2;
-      outIndex = count + 2u;
-    }
-
-    maxVal2 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal1)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal1;
-      outIndex = count + 3u;
-    }
-
-    /* compare for the maximum value */
-    if(out < maxVal2)
-    {
-      /* Update the maximum value and its index */
-      out = maxVal2;
-      outIndex = count + 4u;
-    }
-
-    count += 4u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* if (blockSize - 1u) is not multiple of 4 */
-  blkCnt = (blockSize - 1u) % 4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  q7_t maxVal1, out;                             /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex;                     /* loop counter */
-
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-  blkCnt = (blockSize - 1u);
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* Initialize maxVal to the next consecutive values one by one */
-    maxVal1 = *pSrc++;
-
-    /* compare for the maximum value */
-    if(out < maxVal1)
-    {
-      /* Update the maximum value and it's index */
-      out = maxVal1;
-      outIndex = blockSize - blkCnt;
-    }
-    /* Decrement the loop counter */
-    blkCnt--;
-
-  }
-
-  /* Store the maximum value and its index into destination pointers */
-  *pResult = out;
-  *pIndex = outIndex;
-
-}
-
-/**    
- * @} end of Max group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_f32.c
deleted file mode 100644
index ea4ffb0cc5..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_f32.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_mean_f32.c    
-*    
-* Description:	Mean value of a floating-point vector.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @defgroup mean Mean    
- *    
- * Calculates the mean of the input vector. Mean is defined as the average of the elements in the vector.    
- * The underlying algorithm is used:    
- *    
- * 
    
- * 	Result = (pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]) / blockSize;    
- * 
    
- *    
- * There are separate functions for floating-point, Q31, Q15, and Q7 data types.    
- */
-
-/**    
- * @addtogroup mean    
- * @{    
- */
-
-
-/**    
- * @brief Mean value of a floating-point vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult mean value returned here    
- * @return none.    
- */
-
-
-void arm_mean_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult)
-{
-  float32_t sum = 0.0f;                          /* Temporary result storage */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  float32_t in1, in2, in3, in4;
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
-    in1 = *pSrc++;
-    in2 = *pSrc++;
-    in3 = *pSrc++;
-    in4 = *pSrc++;
-
-    sum += in1;
-    sum += in2;
-    sum += in3;
-    sum += in4;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
-    sum += *pSrc++;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
-  /* Store the result to the destination */
-  *pResult = sum / (float32_t) blockSize;
-}
-
-/**    
- * @} end of mean group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q15.c
deleted file mode 100644
index 2e8fdfa091..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q15.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_mean_q15.c    
-*    
-* Description:	Mean value of a Q15 vector.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @addtogroup mean    
- * @{    
- */
-
-/**    
- * @brief Mean value of a Q15 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult mean value returned here    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using a 32-bit internal accumulator.    
- * The input is represented in 1.15 format and is accumulated in a 32-bit     
- * accumulator in 17.15 format.     
- * There is no risk of internal overflow with this approach, and the     
- * full precision of intermediate result is preserved.     
- * Finally, the accumulator is saturated and truncated to yield a result of 1.15 format.    
- *    
- */
-
-
-void arm_mean_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult)
-{
-  q31_t sum = 0;                                 /* Temporary result storage */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  q31_t in;
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
-    in = *__SIMD32(pSrc)++;
-    sum += ((in << 16) >> 16);
-    sum += (in >> 16);
-    in = *__SIMD32(pSrc)++;
-    sum += ((in << 16) >> 16);
-    sum += (in >> 16);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
-    sum += *pSrc++;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
-  /* Store the result to the destination */
-  *pResult = (q15_t) (sum / blockSize);
-}
-
-/**    
- * @} end of mean group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q31.c
deleted file mode 100644
index 4dd3ce6b36..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q31.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_mean_q31.c    
-*    
-* Description:	Mean value of a Q31 vector.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @addtogroup mean    
- * @{    
- */
-
-/**    
- * @brief Mean value of a Q31 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult mean value returned here    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- *\par    
- * The function is implemented using a 64-bit internal accumulator.    
- * The input is represented in 1.31 format and is accumulated in a 64-bit    
- * accumulator in 33.31 format.    
- * There is no risk of internal overflow with this approach, and the     
- * full precision of intermediate result is preserved.     
- * Finally, the accumulator is truncated to yield a result of 1.31 format.    
- *    
- */
-
-
-void arm_mean_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult)
-{
-  q63_t sum = 0;                                 /* Temporary result storage */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  q31_t in1, in2, in3, in4;
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
-    in1 = *pSrc++;
-    in2 = *pSrc++;
-    in3 = *pSrc++;
-    in4 = *pSrc++;
-
-    sum += in1;
-    sum += in2;
-    sum += in3;
-    sum += in4;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
-    sum += *pSrc++;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
-  /* Store the result to the destination */
-  *pResult = (q31_t) (sum / (int32_t) blockSize);
-}
-
-/**    
- * @} end of mean group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q7.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q7.c
deleted file mode 100644
index 22c60ccdd9..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q7.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_mean_q7.c    
-*    
-* Description:	Mean value of a Q7 vector.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @addtogroup mean    
- * @{    
- */
-
-/**    
- * @brief Mean value of a Q7 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult mean value returned here    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function is implemented using a 32-bit internal accumulator.     
- * The input is represented in 1.7 format and is accumulated in a 32-bit    
- * accumulator in 25.7 format.    
- * There is no risk of internal overflow with this approach, and the     
- * full precision of intermediate result is preserved.     
- * Finally, the accumulator is truncated to yield a result of 1.7 format.    
- *    
- */
-
-
-void arm_mean_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q7_t * pResult)
-{
-  q31_t sum = 0;                                 /* Temporary result storage */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  q31_t in;
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
-    in = *__SIMD32(pSrc)++;
-
-    sum += ((in << 24) >> 24);
-    sum += ((in << 16) >> 24);
-    sum += ((in << 8) >> 24);
-    sum += (in >> 24);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
-    sum += *pSrc++;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
-  /* Store the result to the destination */
-  *pResult = (q7_t) (sum / (int32_t) blockSize);
-}
-
-/**    
- * @} end of mean group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_f32.c
deleted file mode 100644
index 723b693ca6..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_f32.c
+++ /dev/null
@@ -1,175 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_min_f32.c    
-*    
-* Description:	Minimum value of a floating-point vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @defgroup Min Minimum    
- *    
- * Computes the minimum value of an array of data.     
- * The function returns both the minimum value and its position within the array.     
- * There are separate functions for floating-point, Q31, Q15, and Q7 data types.    
- */
-
-/**    
- * @addtogroup Min    
- * @{    
- */
-
-
-/**    
- * @brief Minimum value of a floating-point vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult minimum value returned here    
- * @param[out]      *pIndex index of minimum value returned here    
-  * @return none.    
- *    
- */
-
-void arm_min_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult,
-  uint32_t * pIndex)
-{
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  float32_t minVal1, minVal2, out;               /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex, count;              /* loop counter */
-
-  /* Initialise the count value. */
-  count = 0u;
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-  /* Loop unrolling */
-  blkCnt = (blockSize - 1u) >> 2u;
-
-  while(blkCnt > 0)
-  {
-    /* Initialize minVal to the next consecutive values one by one */
-    minVal1 = *pSrc++;
-    minVal2 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal1)
-    {
-      /* Update the minimum value and its index */
-      out = minVal1;
-      outIndex = count + 1u;
-    }
-
-    minVal1 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal2)
-    {
-      /* Update the minimum value and its index */
-      out = minVal2;
-      outIndex = count + 2u;
-    }
-
-    minVal2 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal1)
-    {
-      /* Update the minimum value and its index */
-      out = minVal1;
-      outIndex = count + 3u;
-    }
-
-    /* compare for the minimum value */
-    if(out > minVal2)
-    {
-      /* Update the minimum value and its index */
-      out = minVal2;
-      outIndex = count + 4u;
-    }
-
-    count += 4u;
-
-    blkCnt--;
-  }
-
-  /* if (blockSize - 1u ) is not multiple of 4 */
-  blkCnt = (blockSize - 1u) % 4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  float32_t minVal1, out;                        /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex;                     /* loop counter */
-
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-  blkCnt = (blockSize - 1u);
-
-#endif //      #ifndef ARM_MATH_CM0
-
-  while(blkCnt > 0)
-  {
-    /* Initialize minVal to the next consecutive values one by one */
-    minVal1 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal1)
-    {
-      /* Update the minimum value and it's index */
-      out = minVal1;
-      outIndex = blockSize - blkCnt;
-    }
-
-    blkCnt--;
-
-  }
-
-  /* Store the minimum value and it's index into destination pointers */
-  *pResult = out;
-  *pIndex = outIndex;
-}
-
-/**    
- * @} end of Min group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q15.c
deleted file mode 100644
index 831505bb24..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q15.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_min_q15.c    
-*    
-* Description:	Minimum value of a Q15 vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-
-/**    
- * @addtogroup Min    
- * @{    
- */
-
-
-/**    
- * @brief Minimum value of a Q15 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult minimum value returned here    
- * @param[out]      *pIndex index of minimum value returned here    
- * @return none.    
- *    
- */
-
-void arm_min_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult,
-  uint32_t * pIndex)
-{
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  q15_t minVal1, minVal2, out;                   /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex, count;              /* loop counter */
-
-  /* Initialise the count value. */
-  count = 0u;
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-  /* Loop unrolling */
-  blkCnt = (blockSize - 1u) >> 2u;
-
-  while(blkCnt > 0)
-  {
-    /* Initialize minVal to the next consecutive values one by one */
-    minVal1 = *pSrc++;
-    minVal2 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal1)
-    {
-      /* Update the minimum value and its index */
-      out = minVal1;
-      outIndex = count + 1u;
-    }
-
-    minVal1 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal2)
-    {
-      /* Update the minimum value and its index */
-      out = minVal2;
-      outIndex = count + 2u;
-    }
-
-    minVal2 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal1)
-    {
-      /* Update the minimum value and its index */
-      out = minVal1;
-      outIndex = count + 3u;
-    }
-
-    /* compare for the minimum value */
-    if(out > minVal2)
-    {
-      /* Update the minimum value and its index */
-      out = minVal2;
-      outIndex = count + 4u;
-    }
-
-    count += 4u;
-
-    blkCnt--;
-  }
-
-  /* if (blockSize - 1u ) is not multiple of 4 */
-  blkCnt = (blockSize - 1u) % 4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  q15_t minVal1, out;                            /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex;                     /* loop counter */
-
-  blkCnt = (blockSize - 1u);
-
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-#endif //      #ifndef ARM_MATH_CM0
-
-  while(blkCnt > 0)
-  {
-    /* Initialize minVal to the next consecutive values one by one */
-    minVal1 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal1)
-    {
-      /* Update the minimum value and it's index */
-      out = minVal1;
-      outIndex = blockSize - blkCnt;
-    }
-
-    blkCnt--;
-
-  }
-
-
-
-  /* Store the minimum value and its index into destination pointers */
-  *pResult = out;
-  *pIndex = outIndex;
-}
-
-/**    
- * @} end of Min group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q31.c
deleted file mode 100644
index 76896902ee..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q31.c
+++ /dev/null
@@ -1,168 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_min_q31.c    
-*    
-* Description:	Minimum value of a Q31 vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-
-/**    
- * @addtogroup Min    
- * @{    
- */
-
-
-/**    
- * @brief Minimum value of a Q31 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult minimum value returned here    
- * @param[out]      *pIndex index of minimum value returned here    
- * @return none.    
- *    
- */
-
-void arm_min_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult,
-  uint32_t * pIndex)
-{
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  q31_t minVal1, minVal2, out;                   /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex, count;              /* loop counter */
-
-  /* Initialise the count value. */
-  count = 0u;
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-
-  /* Loop unrolling */
-  blkCnt = (blockSize - 1u) >> 2u;
-
-  while(blkCnt > 0)
-  {
-    /* Initialize minVal to the next consecutive values one by one */
-    minVal1 = *pSrc++;
-    minVal2 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal1)
-    {
-      /* Update the minimum value and its index */
-      out = minVal1;
-      outIndex = count + 1u;
-    }
-
-    minVal1 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal2)
-    {
-      /* Update the minimum value and its index */
-      out = minVal2;
-      outIndex = count + 2u;
-    }
-
-    minVal2 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal1)
-    {
-      /* Update the minimum value and its index */
-      out = minVal1;
-      outIndex = count + 3u;
-    }
-
-    /* compare for the minimum value */
-    if(out > minVal2)
-    {
-      /* Update the minimum value and its index */
-      out = minVal2;
-      outIndex = count + 4u;
-    }
-
-    count += 4u;
-
-    blkCnt--;
-  }
-
-  /* if (blockSize - 1u ) is not multiple of 4 */
-  blkCnt = (blockSize - 1u) % 4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  q31_t minVal1, out;                            /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex;                     /* loop counter */
-
-  blkCnt = (blockSize - 1u);
-
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-#endif //      #ifndef ARM_MATH_CM0
-
-  while(blkCnt > 0)
-  {
-    /* Initialize minVal to the next consecutive values one by one */
-    minVal1 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal1)
-    {
-      /* Update the minimum value and it's index */
-      out = minVal1;
-      outIndex = blockSize - blkCnt;
-    }
-
-    blkCnt--;
-
-  }
-
-  /* Store the minimum value and its index into destination pointers */
-  *pResult = out;
-  *pIndex = outIndex;
-}
-
-/**    
- * @} end of Min group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q7.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q7.c
deleted file mode 100644
index 88e4dcef5e..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q7.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_min_q7.c    
-*    
-* Description:	Minimum value of a Q7 vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @addtogroup Min    
- * @{    
- */
-
-
-/**    
- * @brief Minimum value of a Q7 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult minimum value returned here    
- * @param[out]      *pIndex index of minimum value returned here    
- * @return none.    
- *    
- */
-
-void arm_min_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q7_t * pResult,
-  uint32_t * pIndex)
-{
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q7_t minVal1, minVal2, out;                    /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex, count;              /* loop counter */
-
-  /* Initialise the count value. */
-  count = 0u;
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-  /* Loop unrolling */
-  blkCnt = (blockSize - 1u) >> 2u;
-
-  while(blkCnt > 0)
-  {
-    /* Initialize minVal to the next consecutive values one by one */
-    minVal1 = *pSrc++;
-    minVal2 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal1)
-    {
-      /* Update the minimum value and its index */
-      out = minVal1;
-      outIndex = count + 1u;
-    }
-
-    minVal1 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal2)
-    {
-      /* Update the minimum value and its index */
-      out = minVal2;
-      outIndex = count + 2u;
-    }
-
-    minVal2 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal1)
-    {
-      /* Update the minimum value and its index */
-      out = minVal1;
-      outIndex = count + 3u;
-    }
-
-    /* compare for the minimum value */
-    if(out > minVal2)
-    {
-      /* Update the minimum value and its index */
-      out = minVal2;
-      outIndex = count + 4u;
-    }
-
-    count += 4u;
-
-    blkCnt--;
-  }
-
-  /* if (blockSize - 1u ) is not multiple of 4 */
-  blkCnt = (blockSize - 1u) % 4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q7_t minVal1, out;                             /* Temporary variables to store the output value. */
-  uint32_t blkCnt, outIndex;                     /* loop counter */
-
-  /* Initialise the index value to zero. */
-  outIndex = 0u;
-  /* Load first input value that act as reference value for comparision */
-  out = *pSrc++;
-
-  blkCnt = (blockSize - 1u);
-
-#endif //      #ifndef ARM_MATH_CM0
-
-  while(blkCnt > 0)
-  {
-    /* Initialize minVal to the next consecutive values one by one */
-    minVal1 = *pSrc++;
-
-    /* compare for the minimum value */
-    if(out > minVal1)
-    {
-      /* Update the minimum value and it's index */
-      out = minVal1;
-      outIndex = blockSize - blkCnt;
-    }
-
-    blkCnt--;
-
-  }
-
-  /* Store the minimum value and its index into destination pointers */
-  *pResult = out;
-  *pIndex = outIndex;
-
-
-}
-
-/**    
- * @} end of Min group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_f32.c
deleted file mode 100644
index 4e3505b997..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_f32.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_power_f32.c    
-*    
-* Description:	Sum of the squares of the elements of a floating-point vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @defgroup power Power    
- *    
- * Calculates the sum of the squares of the elements in the input vector.    
- * The underlying algorithm is used:    
- *    
- * 
    
- * 	Result = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + pSrc[2] * pSrc[2] + ... + pSrc[blockSize-1] * pSrc[blockSize-1];    
- * 
    
- *   
- * There are separate functions for floating point, Q31, Q15, and Q7 data types.     
- */
-
-/**    
- * @addtogroup power    
- * @{    
- */
-
-
-/**    
- * @brief Sum of the squares of the elements of a floating-point vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult sum of the squares value returned here    
- * @return none.    
- *    
- */
-
-
-void arm_power_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult)
-{
-  float32_t sum = 0.0f;                          /* accumulator */
-  float32_t in;                                  /* Temporary variable to store input value */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
-    /* Compute Power and then store the result in a temporary variable, sum. */
-    in = *pSrc++;
-    sum += in * in;
-    in = *pSrc++;
-    sum += in * in;
-    in = *pSrc++;
-    sum += in * in;
-    in = *pSrc++;
-    sum += in * in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-
-  while(blkCnt > 0u)
-  {
-    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
-    /* compute power and then store the result in a temporary variable, sum. */
-    in = *pSrc++;
-    sum += in * in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Store the result to the destination */
-  *pResult = sum;
-}
-
-/**    
- * @} end of power group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q15.c
deleted file mode 100644
index a8d0db898d..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q15.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_power_q15.c    
-*    
-* Description:	Sum of the squares of the elements of a Q15 vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @addtogroup power    
- * @{    
- */
-
-/**    
- * @brief Sum of the squares of the elements of a Q15 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult sum of the squares value returned here    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The function is implemented using a 64-bit internal accumulator.     
- * The input is represented in 1.15 format.   
- * Intermediate multiplication yields a 2.30 format, and this    
- * result is added without saturation to a 64-bit accumulator in 34.30 format.    
- * With 33 guard bits in the accumulator, there is no risk of overflow, and the    
- * full precision of the intermediate multiplication is preserved.    
- * Finally, the return result is in 34.30 format.     
- *    
- */
-
-void arm_power_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q63_t * pResult)
-{
-  q63_t sum = 0;                                 /* Temporary result storage */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t in32;                                    /* Temporary variable to store input value */
-  q15_t in16;                                    /* Temporary variable to store input value */
-  uint32_t blkCnt;                               /* loop counter */
-
-
-  /* loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
-    /* Compute Power and then store the result in a temporary variable, sum. */
-    in32 = *__SIMD32(pSrc)++;
-    sum = __SMLALD(in32, in32, sum);
-    in32 = *__SIMD32(pSrc)++;
-    sum = __SMLALD(in32, in32, sum);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
-    /* Compute Power and then store the result in a temporary variable, sum. */
-    in16 = *pSrc++;
-    sum = __SMLALD(in16, in16, sum);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q15_t in;                                      /* Temporary variable to store input value */
-  uint32_t blkCnt;                               /* loop counter */
-
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
-    /* Compute Power and then store the result in a temporary variable, sum. */
-    in = *pSrc++;
-    sum += ((q31_t) in * in);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  /* Store the results in 34.30 format  */
-  *pResult = sum;
-}
-
-/**    
- * @} end of power group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q31.c
deleted file mode 100644
index 49cdb67fa3..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q31.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_power_q31.c    
-*    
-* Description:	Sum of the squares of the elements of a Q31 vector.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @addtogroup power    
- * @{    
- */
-
-/**    
- * @brief Sum of the squares of the elements of a Q31 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult sum of the squares value returned here    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The function is implemented using a 64-bit internal accumulator.    
- * The input is represented in 1.31 format.    
- * Intermediate multiplication yields a 2.62 format, and this    
- * result is truncated to 2.48 format by discarding the lower 14 bits.    
- * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format.    
- * With 15 guard bits in the accumulator, there is no risk of overflow, and the    
- * full precision of the intermediate multiplication is preserved.    
- * Finally, the return result is in 16.48 format.     
- *    
- */
-
-void arm_power_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q63_t * pResult)
-{
-  q63_t sum = 0;                                 /* Temporary result storage */
-  q31_t in;
-  uint32_t blkCnt;                               /* loop counter */
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
-    /* Compute Power then shift intermediate results by 14 bits to maintain 16.48 format and then store the result in a temporary variable sum, providing 15 guard bits. */
-    in = *pSrc++;
-    sum += ((q63_t) in * in) >> 14u;
-
-    in = *pSrc++;
-    sum += ((q63_t) in * in) >> 14u;
-
-    in = *pSrc++;
-    sum += ((q63_t) in * in) >> 14u;
-
-    in = *pSrc++;
-    sum += ((q63_t) in * in) >> 14u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
-    /* Compute Power and then store the result in a temporary variable, sum. */
-    in = *pSrc++;
-    sum += ((q63_t) in * in) >> 14u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Store the results in 16.48 format  */
-  *pResult = sum;
-}
-
-/**    
- * @} end of power group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q7.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q7.c
deleted file mode 100644
index 39fd2e98d0..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q7.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_power_q7.c    
-*    
-* Description:	Sum of the squares of the elements of a Q7 vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @addtogroup power    
- * @{    
- */
-
-/**    
- * @brief Sum of the squares of the elements of a Q7 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult sum of the squares value returned here    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The function is implemented using a 32-bit internal accumulator.     
- * The input is represented in 1.7 format.   
- * Intermediate multiplication yields a 2.14 format, and this    
- * result is added without saturation to an accumulator in 18.14 format.    
- * With 17 guard bits in the accumulator, there is no risk of overflow, and the    
- * full precision of the intermediate multiplication is preserved.    
- * Finally, the return result is in 18.14 format.     
- *    
- */
-
-void arm_power_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult)
-{
-  q31_t sum = 0;                                 /* Temporary result storage */
-  q7_t in;                                       /* Temporary variable to store input */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t input1;                                  /* Temporary variable to store packed input */
-  q31_t in1, in2;                                /* Temporary variables to store input */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* Reading two inputs of pSrc vector and packing */
-    input1 = *__SIMD32(pSrc)++;
-
-    in1 = __SXTB16(__ROR(input1, 8));
-    in2 = __SXTB16(input1);
-
-    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
-    /* calculate power and accumulate to accumulator */
-    sum = __SMLAD(in1, in1, sum);
-    sum = __SMLAD(in2, in2, sum);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
-    /* Compute Power and then store the result in a temporary variable, sum. */
-    in = *pSrc++;
-    sum += ((q15_t) in * in);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Store the result in 18.14 format  */
-  *pResult = sum;
-}
-
-/**    
- * @} end of power group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_f32.c
deleted file mode 100644
index eacc166ffb..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_f32.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_rms_f32.c    
-*    
-* Description:	Root mean square value of an array of F32 type    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @defgroup RMS Root mean square (RMS)    
- *    
- *     
- * Calculates the Root Mean Sqaure of the elements in the input vector.    
- * The underlying algorithm is used:    
- *    
- * 
    
- * 	Result = sqrt(((pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]) / blockSize));    
- * 
    
- *   
- * There are separate functions for floating point, Q31, and Q15 data types.     
- */
-
-/**    
- * @addtogroup RMS    
- * @{    
- */
-
-
-/**    
- * @brief Root Mean Square of the elements of a floating-point vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult rms value returned here    
- * @return none.    
- *    
- */
-
-void arm_rms_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult)
-{
-  float32_t sum = 0.0f;                          /* Accumulator */
-  float32_t in;                                  /* Tempoprary variable to store input value */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /* loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
-    /* Compute sum of the squares and then store the result in a temporary variable, sum  */
-    in = *pSrc++;
-    sum += in * in;
-    in = *pSrc++;
-    sum += in * in;
-    in = *pSrc++;
-    sum += in * in;
-    in = *pSrc++;
-    sum += in * in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
-    /* Compute sum of the squares and then store the results in a temporary variable, sum  */
-    in = *pSrc++;
-    sum += in * in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Compute Rms and store the result in the destination */
-  arm_sqrt_f32(sum / (float32_t) blockSize, pResult);
-}
-
-/**    
- * @} end of RMS group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q15.c
deleted file mode 100644
index 4621a2c21a..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q15.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_rms_q15.c    
-*    
-* Description:	Root Mean Square of the elements of a Q15 vector.  
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @addtogroup RMS    
- * @{    
- */
-
-/**    
- * @brief Root Mean Square of the elements of a Q15 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult rms value returned here    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The function is implemented using a 64-bit internal accumulator.    
- * The input is represented in 1.15 format.    
- * Intermediate multiplication yields a 2.30 format, and this    
- * result is added without saturation to a 64-bit accumulator in 34.30 format.    
- * With 33 guard bits in the accumulator, there is no risk of overflow, and the    
- * full precision of the intermediate multiplication is preserved.    
- * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower     
- * 15 bits, and then saturated to yield a result in 1.15 format.    
- *    
- */
-
-void arm_rms_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult)
-{
-  q63_t sum = 0;                                 /* accumulator */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t in;                                      /* temporary variable to store the input value */
-  q15_t in1;                                     /* temporary variable to store the input value */
-  uint32_t blkCnt;                               /* loop counter */
-
-  /* loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
-    /* Compute sum of the squares and then store the results in a temporary variable, sum */
-    in = *__SIMD32(pSrc)++;
-    sum = __SMLALD(in, in, sum);
-    in = *__SIMD32(pSrc)++;
-    sum = __SMLALD(in, in, sum);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
-    /* Compute sum of the squares and then store the results in a temporary variable, sum */
-    in1 = *pSrc++;
-    sum = __SMLALD(in1, in1, sum);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Truncating and saturating the accumulator to 1.15 format */
-  sum = __SSAT((q31_t) (sum >> 15), 16);
-
-  in1 = (q15_t) (sum / blockSize);
-
-  /* Store the result in the destination */
-  arm_sqrt_q15(in1, pResult);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q15_t in;                                      /* temporary variable to store the input value */
-  uint32_t blkCnt;                               /* loop counter */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
-    /* Compute sum of the squares and then store the results in a temporary variable, sum */
-    in = *pSrc++;
-    sum += ((q31_t) in * in);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Truncating and saturating the accumulator to 1.15 format */
-  sum = __SSAT((q31_t) (sum >> 15), 16);
-
-  in = (q15_t) (sum / blockSize);
-
-  /* Store the result in the destination */
-  arm_sqrt_q15(in, pResult);
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
- * @} end of RMS group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q31.c
deleted file mode 100644
index 56eff443ad..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q31.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_rms_q31.c    
-*    
-* Description:	Root Mean Square of the elements of a Q31 vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**        
- * @addtogroup RMS        
- * @{        
- */
-
-
-/**        
- * @brief Root Mean Square of the elements of a Q31 vector.        
- * @param[in]       *pSrc points to the input vector        
- * @param[in]       blockSize length of the input vector        
- * @param[out]      *pResult rms value returned here        
- * @return none.        
- *        
- * @details        
- * Scaling and Overflow Behavior:        
- *        
- *\par        
- * The function is implemented using an internal 64-bit accumulator.        
- * The input is represented in 1.31 format, and intermediate multiplication        
- * yields a 2.62 format.        
- * The accumulator maintains full precision of the intermediate multiplication results,         
- * but provides only a single guard bit.        
- * There is no saturation on intermediate additions.        
- * If the accumulator overflows, it wraps around and distorts the result.         
- * In order to avoid overflows completely, the input signal must be scaled down by         
- * log2(blockSize) bits, as a total of blockSize additions are performed internally.         
- * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.        
- *        
- */
-
-void arm_rms_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult)
-{
-  q63_t sum = 0;                                 /* accumulator */
-  q31_t in;                                      /* Temporary variable to store the input */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t in1, in2, in3, in4;                      /* Temporary input variables */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 8 outputs at a time.        
-   ** a second loop below computes the remaining 1 to 7 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
-    /* Compute sum of the squares and then store the result in a temporary variable, sum */
-    /* read two samples from source buffer */
-    in1 = pSrc[0];
-    in2 = pSrc[1];
-
-    /* calculate power and accumulate to accumulator */
-    sum += (q63_t) in1 *in1;
-    sum += (q63_t) in2 *in2;
-
-    /* read two samples from source buffer */
-    in3 = pSrc[2];
-    in4 = pSrc[3];
-
-    /* calculate power and accumulate to accumulator */
-    sum += (q63_t) in3 *in3;
-    sum += (q63_t) in4 *in4;
-
-
-    /* update source buffer to process next samples */
-    pSrc += 4u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 8, compute any remaining output samples here.        
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
-    /* Compute sum of the squares and then store the results in a temporary variable, sum */
-    in = *pSrc++;
-    sum += (q63_t) in *in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Convert data in 2.62 to 1.31 by 31 right shifts and saturate */
-
-  sum = __SSAT(sum >> 31, 31);
-
-
-  /* Compute Rms and store the result in the destination vector */
-  arm_sqrt_q31((q31_t) ((q31_t) sum / (int32_t) blockSize), pResult);
-}
-
-/**        
- * @} end of RMS group        
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_f32.c
deleted file mode 100644
index 2fcc4e5a73..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_f32.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_std_f32.c    
-*    
-* Description:	Standard deviation of the elements of a floating-point vector.  
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @defgroup STD Standard deviation    
- *    
- * Calculates the standard deviation of the elements in the input vector.     
- * The underlying algorithm is used:    
- *   
- * 
    
- * 	Result = sqrt((sumOfSquares - sum2 / blockSize) / (blockSize - 1))   
- *   
- *	   where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]   
- *   
- *	                   sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]   
- * 
   
- *    
- * There are separate functions for floating point, Q31, and Q15 data types.    
- */
-
-/**    
- * @addtogroup STD    
- * @{    
- */
-
-
-/**    
- * @brief Standard deviation of the elements of a floating-point vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult standard deviation value returned here    
- * @return none.    
- *    
- */
-
-
-void arm_std_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult)
-{
-  float32_t sum = 0.0f;                          /* Temporary result storage */
-  float32_t sumOfSquares = 0.0f;                 /* Sum of squares */
-  float32_t in;                                  /* input value */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  float32_t meanOfSquares, mean, squareOfMean;
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
-    /* Compute Sum of squares of the input samples    
-     * and then store the result in a temporary variable, sum. */
-    in = *pSrc++;
-    sum += in;
-    sumOfSquares += in * in;
-    in = *pSrc++;
-    sum += in;
-    sumOfSquares += in * in;
-    in = *pSrc++;
-    sum += in;
-    sumOfSquares += in * in;
-    in = *pSrc++;
-    sum += in;
-    sumOfSquares += in * in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
-    /* Compute Sum of squares of the input samples    
-     * and then store the result in a temporary variable, sum. */
-    in = *pSrc++;
-    sum += in;
-    sumOfSquares += in * in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Compute Mean of squares of the input samples    
-   * and then store the result in a temporary variable, meanOfSquares. */
-  meanOfSquares = sumOfSquares / ((float32_t) blockSize - 1.0f);
-
-  /* Compute mean of all input values */
-  mean = sum / (float32_t) blockSize;
-
-  /* Compute square of mean */
-  squareOfMean = (mean * mean) * (((float32_t) blockSize) /
-                                  ((float32_t) blockSize - 1.0f));
-
-  /* Compute standard deviation and then store the result to the destination */
-  arm_sqrt_f32((meanOfSquares - squareOfMean), pResult);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  float32_t squareOfSum;                         /* Square of Sum */
-  float32_t var;                                 /* Temporary varaince storage */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
-    /* Compute Sum of squares of the input samples     
-     * and then store the result in a temporary variable, sumOfSquares. */
-    in = *pSrc++;
-    sumOfSquares += in * in;
-
-    /* C = (A[0] + A[1] + ... + A[blockSize-1]) */
-    /* Compute Sum of the input samples     
-     * and then store the result in a temporary variable, sum. */
-    sum += in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Compute the square of sum */
-  squareOfSum = ((sum * sum) / (float32_t) blockSize);
-
-  /* Compute the variance */
-  var = ((sumOfSquares - squareOfSum) / (float32_t) (blockSize - 1.0f));
-
-  /* Compute standard deviation and then store the result to the destination */
-  arm_sqrt_f32(var, pResult);
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
- * @} end of STD group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q15.c
deleted file mode 100644
index ac51167a12..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q15.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_std_q15.c    
-*    
-* Description:	Standard deviation of an array of Q15 type.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @addtogroup STD    
- * @{    
- */
-
-/**    
- * @brief Standard deviation of the elements of a Q15 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult standard deviation value returned here    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The function is implemented using a 64-bit internal accumulator.    
- * The input is represented in 1.15 format.   
- * Intermediate multiplication yields a 2.30 format, and this    
- * result is added without saturation to a 64-bit accumulator in 34.30 format.    
- * With 33 guard bits in the accumulator, there is no risk of overflow, and the    
- * full precision of the intermediate multiplication is preserved.    
- * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower     
- * 15 bits, and then saturated to yield a result in 1.15 format.    
- */
-
-void arm_std_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult)
-{
-  q31_t sum = 0;                                 /* Accumulator */
-  q31_t meanOfSquares, squareOfMean;             /* square of mean and mean of square */
-  q15_t mean;                                    /* mean */
-  uint32_t blkCnt;                               /* loop counter */
-  q15_t t;                                       /* Temporary variable */
-  q63_t sumOfSquares = 0;                        /* Accumulator */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t in;                                      /* input value */
-  q15_t in1;                                     /* input value */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
-    /* Compute Sum of squares of the input samples    
-     * and then store the result in a temporary variable, sum. */
-    in = *__SIMD32(pSrc)++;
-    sum += ((in << 16) >> 16);
-    sum += (in >> 16);
-    sumOfSquares = __SMLALD(in, in, sumOfSquares);
-    in = *__SIMD32(pSrc)++;
-    sum += ((in << 16) >> 16);
-    sum += (in >> 16);
-    sumOfSquares = __SMLALD(in, in, sumOfSquares);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
-    /* Compute Sum of squares of the input samples    
-     * and then store the result in a temporary variable, sum. */
-    in1 = *pSrc++;
-    sumOfSquares = __SMLALD(in1, in1, sumOfSquares);
-    sum += in1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Compute Mean of squares of the input samples    
-   * and then store the result in a temporary variable, meanOfSquares. */
-  t = (q15_t) ((1.0 / (blockSize - 1)) * 16384LL);
-  sumOfSquares = __SSAT((sumOfSquares >> 15u), 16u);
-
-  meanOfSquares = (q31_t) ((sumOfSquares * t) >> 14u);
-
-  /* Compute mean of all input values */
-  t = (q15_t) ((1.0 / (blockSize * (blockSize - 1))) * 32768LL);
-  mean = (q15_t) __SSAT(sum, 16u);
-
-  /* Compute square of mean */
-  squareOfMean = ((q31_t) mean * mean) >> 15;
-  squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 15);
-
-  /* mean of the squares minus the square of the mean. */
-  in1 = (q15_t) (meanOfSquares - squareOfMean);
-
-  /* Compute standard deviation and store the result to the destination */
-  arm_sqrt_q15(in1, pResult);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  q15_t in;                                      /* input value */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
-    /* Compute Sum of squares of the input samples     
-     * and then store the result in a temporary variable, sumOfSquares. */
-    in = *pSrc++;
-    sumOfSquares += (in * in);
-
-    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
-    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
-    sum += in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Compute Mean of squares of the input samples     
-   * and then store the result in a temporary variable, meanOfSquares. */
-  t = (q15_t) ((1.0 / (blockSize - 1)) * 16384LL);
-  sumOfSquares = __SSAT((sumOfSquares >> 15u), 16u);
-  meanOfSquares = (q31_t) ((sumOfSquares * t) >> 14u);
-
-  /* Compute mean of all input values */
-  mean = (q15_t) __SSAT(sum, 16u);
-
-  /* Compute square of mean of the input samples   
-   * and then store the result in a temporary variable, squareOfMean.*/
-  t = (q15_t) ((1.0 / (blockSize * (blockSize - 1))) * 32768LL);
-  squareOfMean = ((q31_t) mean * mean) >> 15;
-  squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 15);
-
-  /* mean of the squares minus the square of the mean. */
-  in = (q15_t) (meanOfSquares - squareOfMean);
-
-  /* Compute standard deviation and store the result to the destination */
-  arm_sqrt_q15(in, pResult);
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-
-}
-
-/**    
- * @} end of STD group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q31.c
deleted file mode 100644
index de60bc06ea..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q31.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_std_q31.c    
-*    
-* Description:	Standard deviation of an array of Q31 type.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @addtogroup STD    
- * @{    
- */
-
-
-/**    
- * @brief Standard deviation of the elements of a Q31 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult standard deviation value returned here    
- * @return none.    
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- *\par    
- * The function is implemented using an internal 64-bit accumulator.    
- * The input is represented in 1.31 format, and intermediate multiplication    
- * yields a 2.62 format.    
- * The accumulator maintains full precision of the intermediate multiplication results,     
- * but provides only a single guard bit.    
- * There is no saturation on intermediate additions.    
- * If the accumulator overflows it wraps around and distorts the result.    
- * In order to avoid overflows completely the input signal must be scaled down by     
- * log2(blockSize) bits, as a total of blockSize additions are performed internally.     
- * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.    
- *    
- */
-
-
-void arm_std_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult)
-{
-  q63_t sum = 0;                                 /* Accumulator */
-  q31_t meanOfSquares, squareOfMean;             /* square of mean and mean of square */
-  q31_t mean;                                    /* mean */
-  q31_t in;                                      /* input value */
-  q31_t t;                                       /* Temporary variable */
-  uint32_t blkCnt;                               /* loop counter */
-  q63_t sumOfSquares = 0;                        /* Accumulator */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
-    /* Compute Sum of squares of the input samples    
-     * and then store the result in a temporary variable, sum. */
-    in = *pSrc++;
-    sum += in;
-    sumOfSquares += ((q63_t) (in) * (in));
-    in = *pSrc++;
-    sum += in;
-    sumOfSquares += ((q63_t) (in) * (in));
-    in = *pSrc++;
-    sum += in;
-    sumOfSquares += ((q63_t) (in) * (in));
-    in = *pSrc++;
-    sum += in;
-    sumOfSquares += ((q63_t) (in) * (in));
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
-    /* Compute Sum of squares of the input samples    
-     * and then store the result in a temporary variable, sum. */
-    in = *pSrc++;
-    sum += in;
-    sumOfSquares += ((q63_t) (in) * (in));
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  t = (q31_t) ((1.0f / (float32_t) (blockSize - 1u)) * 1073741824.0f);
-
-  /* Compute Mean of squares of the input samples    
-   * and then store the result in a temporary variable, meanOfSquares. */
-  sumOfSquares = (sumOfSquares >> 31);
-  meanOfSquares = (q31_t) ((sumOfSquares * t) >> 30);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
-    /* Compute Sum of squares of the input samples     
-     * and then store the result in a temporary variable, sumOfSquares. */
-    in = *pSrc++;
-    sumOfSquares += ((q63_t) (in) * (in));
-
-    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
-    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
-    sum += in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Compute Mean of squares of the input samples     
-   * and then store the result in a temporary variable, meanOfSquares. */
-  t = (q31_t) ((1.0f / (float32_t) (blockSize - 1u)) * 1073741824.0f);
-  sumOfSquares = (sumOfSquares >> 31);
-  meanOfSquares = (q31_t) ((sumOfSquares * t) >> 30);
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  /* Compute mean of all input values */
-  t = (q31_t) ((1.0f / (blockSize * (blockSize - 1u))) * 2147483648.0f);
-  mean = (q31_t) (sum);
-
-  /* Compute square of mean */
-  squareOfMean = (q31_t) (((q63_t) mean * mean) >> 31);
-  squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 31);
-
-
-  /* Compute standard deviation and then store the result to the destination */
-  arm_sqrt_q31(meanOfSquares - squareOfMean, pResult);
-
-}
-
-/**    
- * @} end of STD group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_f32.c
deleted file mode 100644
index 4dfd846c2b..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_f32.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_var_f32.c    
-*    
-* Description:	Variance of the elements of a floating-point vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @defgroup variance  Variance    
- *    
- * Calculates the variance of the elements in the input vector.    
- * The underlying algorithm is used:    
- *    
- * 
    
- * 	Result = (sumOfSquares - sum2 / blockSize) / (blockSize - 1)   
- *   
- *	   where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]   
- *   
- *	                   sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]   
- * 
   
- *    
- * There are separate functions for floating point, Q31, and Q15 data types.    
- */
-
-/**    
- * @addtogroup variance    
- * @{    
- */
-
-
-/**    
- * @brief Variance of the elements of a floating-point vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult variance value returned here    
- * @return none.    
- *    
- */
-
-
-void arm_var_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult)
-{
-
-  float32_t sum = 0.0f;                          /* Temporary result storage */
-  float32_t sumOfSquares = 0.0f;                 /* Sum of squares */
-  float32_t in;                                  /* input value */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  float32_t meanOfSquares, mean, squareOfMean;   /* Temporary variables */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
-    /* Compute Sum of squares of the input samples    
-     * and then store the result in a temporary variable, sum. */
-    in = *pSrc++;
-    sum += in;
-    sumOfSquares += in * in;
-    in = *pSrc++;
-    sum += in;
-    sumOfSquares += in * in;
-    in = *pSrc++;
-    sum += in;
-    sumOfSquares += in * in;
-    in = *pSrc++;
-    sum += in;
-    sumOfSquares += in * in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
-    /* Compute Sum of squares of the input samples    
-     * and then store the result in a temporary variable, sum. */
-    in = *pSrc++;
-    sum += in;
-    sumOfSquares += in * in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Compute Mean of squares of the input samples    
-   * and then store the result in a temporary variable, meanOfSquares. */
-  meanOfSquares = sumOfSquares / ((float32_t) blockSize - 1.0f);
-
-  /* Compute mean of all input values */
-  mean = sum / (float32_t) blockSize;
-
-  /* Compute square of mean */
-  squareOfMean = (mean * mean) * (((float32_t) blockSize) /
-                                  ((float32_t) blockSize - 1.0f));
-
-  /* Compute variance and then store the result to the destination */
-  *pResult = meanOfSquares - squareOfMean;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  float32_t squareOfSum;                         /* Square of Sum */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
-    /* Compute Sum of squares of the input samples     
-     * and then store the result in a temporary variable, sumOfSquares. */
-    in = *pSrc++;
-    sumOfSquares += in * in;
-
-    /* C = (A[0] + A[1] + ... + A[blockSize-1]) */
-    /* Compute Sum of the input samples     
-     * and then store the result in a temporary variable, sum. */
-    sum += in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Compute the square of sum */
-  squareOfSum = ((sum * sum) / (float32_t) blockSize);
-
-  /* Compute the variance */
-  *pResult = ((sumOfSquares - squareOfSum) / (float32_t) (blockSize - 1.0f));
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
- * @} end of variance group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q15.c
deleted file mode 100644
index d37e66a57c..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q15.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_var_q15.c    
-*    
-* Description:	Variance of an array of Q15 type.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupStats    
- */
-
-/**    
- * @addtogroup variance    
- * @{    
- */
-
-/**    
- * @brief Variance of the elements of a Q15 vector.    
- * @param[in]       *pSrc points to the input vector    
- * @param[in]       blockSize length of the input vector    
- * @param[out]      *pResult variance value returned here    
- * @return none.    
- *    
- * @details    
- * Scaling and Overflow Behavior:    
- *    
- * \par    
- * The function is implemented using a 64-bit internal accumulator.    
- * The input is represented in 1.15 format.   
- * Intermediate multiplication yields a 2.30 format, and this    
- * result is added without saturation to a 64-bit accumulator in 34.30 format.    
- * With 33 guard bits in the accumulator, there is no risk of overflow, and the    
- * full precision of the intermediate multiplication is preserved.    
- * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower     
- * 15 bits, and then saturated to yield a result in 1.15 format.    
- *    
- */
-
-
-void arm_var_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult)
-{
-  q31_t sum = 0;                                 /* Accumulator */
-  q31_t meanOfSquares, squareOfMean;             /* Mean of square and square of mean */
-  q15_t mean;                                    /* mean */
-  uint32_t blkCnt;                               /* loop counter */
-  q15_t t;                                       /* Temporary variable */
-  q63_t sumOfSquares = 0;                        /* Accumulator */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t in;                                      /* Input variable */
-  q15_t in1;                                     /* Temporary variable */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
-    /* Compute Sum of squares of the input samples    
-     * and then store the result in a temporary variable, sum. */
-    in = *__SIMD32(pSrc)++;
-    sum += ((in << 16) >> 16);
-    sum += (in >> 16);
-    sumOfSquares = __SMLALD(in, in, sumOfSquares);
-    in = *__SIMD32(pSrc)++;
-    sum += ((in << 16) >> 16);
-    sum += (in >> 16);
-    sumOfSquares = __SMLALD(in, in, sumOfSquares);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
-    /* Compute Sum of squares of the input samples    
-     * and then store the result in a temporary variable, sum. */
-    in1 = *pSrc++;
-    sum += in1;
-    sumOfSquares = __SMLALD(in1, in1, sumOfSquares);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Compute Mean of squares of the input samples    
-   * and then store the result in a temporary variable, meanOfSquares. */
-  t = (q15_t) ((1.0f / (float32_t) (blockSize - 1u)) * 16384);
-  sumOfSquares = __SSAT((sumOfSquares >> 15u), 16u);
-
-  meanOfSquares = (q31_t) ((sumOfSquares * t) >> 14u);
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q15_t in;                                      /* Temporary variable */
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
-    /* Compute Sum of squares of the input samples     
-     * and then store the result in a temporary variable, sumOfSquares. */
-    in = *pSrc++;
-    sumOfSquares += (in * in);
-
-    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
-    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
-    sum += in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* Compute Mean of squares of the input samples     
-   * and then store the result in a temporary variable, meanOfSquares. */
-  t = (q15_t) ((1.0f / (float32_t) (blockSize - 1u)) * 16384);
-  sumOfSquares = __SSAT((sumOfSquares >> 15u), 16u);
-  meanOfSquares = (q31_t) ((sumOfSquares * t) >> 14u);
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  /* Compute mean of all input values */
-  t = (q15_t) ((1.0f / (float32_t) (blockSize * (blockSize - 1u))) * 32768);
-  mean = __SSAT(sum, 16u);
-
-  /* Compute square of mean */
-  squareOfMean = ((q31_t) mean * mean) >> 15;
-  squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 15);
-
-  /* Compute variance and then store the result to the destination */
-  *pResult = (meanOfSquares - squareOfMean);
-
-}
-
-/**    
- * @} end of variance group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q31.c
deleted file mode 100644
index 7acef7ef12..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q31.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_var_q31.c    
-*    
-* Description:	Variance of an array of Q31 type.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**        
- * @ingroup groupStats        
- */
-
-/**        
- * @addtogroup variance        
- * @{        
- */
-
-/**        
- * @brief Variance of the elements of a Q31 vector.        
- * @param[in]       *pSrc points to the input vector        
- * @param[in]       blockSize length of the input vector        
- * @param[out]      *pResult variance value returned here        
- * @return none.        
- *        
- * @details        
- * Scaling and Overflow Behavior:        
- *        
- *\par        
- * The function is implemented using an internal 64-bit accumulator.        
- * The input is represented in 1.31 format, and intermediate multiplication        
- * yields a 2.62 format.        
- * The accumulator maintains full precision of the intermediate multiplication results,         
- * but provides only a single guard bit.        
- * There is no saturation on intermediate additions.        
- * If the accumulator overflows it wraps around and distorts the result.        
- * In order to avoid overflows completely the input signal must be scaled down by         
- * log2(blockSize) bits, as a total of blockSize additions are performed internally.         
- * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.        
- *        
- */
-
-
-void arm_var_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q63_t * pResult)
-{
-  q63_t sum = 0, sumSquare = 0;                  /* Accumulator */
-  q31_t meanOfSquares, squareOfMean;             /* square of mean and mean of square */
-  q31_t mean;                                    /* mean */
-  q31_t in;                                      /* input value */
-  q31_t t;                                       /* Temporary variable */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  q63_t sumSquare1 = 0;                          /* Accumulator */
-  q31_t in1, in2, in3, in4;                      /* Temporary input variables */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
-    /* Compute Sum of squares of the input samples        
-     * and then store the result in a temporary variable, sum. */
-    /* read input samples from source buffer */
-    in1 = pSrc[0];
-    in2 = pSrc[1];
-
-    /* calculate sum of inputs */
-    sum += in1;
-    /* calculate sum of squares */
-    sumSquare += ((q63_t) (in1) * (in1));
-    in3 = pSrc[2];
-    sum += in2;
-    sumSquare1 += ((q63_t) (in2) * (in2));
-    in4 = pSrc[3];
-    sum += in3;
-    sumSquare += ((q63_t) (in3) * (in3));
-    sum += in4;
-    sumSquare1 += ((q63_t) (in4) * (in4));
-
-    /* update input pointer to process next samples */
-    pSrc += 4u;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* add two accumulators */
-  sumSquare = sumSquare + sumSquare1;
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
-    /* Compute Sum of squares of the input samples        
-     * and then store the result in a temporary variable, sum. */
-    in = *pSrc++;
-    sumSquare += ((q63_t) (in) * (in));
-    sum += in;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  t = (q31_t) ((1.0f / (float32_t) (blockSize - 1u)) * 1073741824.0f);
-
-  /* Compute Mean of squares of the input samples        
-   * and then store the result in a temporary variable, meanOfSquares. */
-  sumSquare = (sumSquare >> 31);
-  meanOfSquares = (q31_t) ((sumSquare * t) >> 30);
-
-  /* Compute mean of all input values */
-  t = (q31_t) ((1.0f / (blockSize * (blockSize - 1u))) * 2147483648.0f);
-  mean = (q31_t) (sum);
-
-  /* Compute square of mean */
-  squareOfMean = (q31_t) (((q63_t) mean * mean) >> 31);
-  squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 31);
-
-  /* Compute variance and then store the result to the destination */
-  *pResult = (q63_t) meanOfSquares - squareOfMean;
-
-}
-
-/**        
- * @} end of variance group        
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_f32.c
deleted file mode 100644
index 5621b87520..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_f32.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_copy_f32.c    
-*    
-* Description:	Copies the elements of a floating-point vector.  
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @defgroup copy Vector Copy    
- *    
- * Copies sample by sample from source vector to destination vector.    
- *    
- * 
    
- * 	pDst[n] = pSrc[n];   0 <= n < blockSize.    
- * 
    
- *   
- * There are separate functions for floating point, Q31, Q15, and Q7 data types.     
- */
-
-/**    
- * @addtogroup copy    
- * @{    
- */
-
-/**    
- * @brief Copies the elements of a floating-point vector.     
- * @param[in]       *pSrc points to input vector    
- * @param[out]      *pDst points to output vector    
- * @param[in]       blockSize length of the input vector   
- * @return none.    
- *    
- */
-
-
-void arm_copy_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize)
-{
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  float32_t in1, in2, in3, in4;
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = A */
-    /* Copy and then store the results in the destination buffer */
-    in1 = *pSrc++;
-    in2 = *pSrc++;
-    in3 = *pSrc++;
-    in4 = *pSrc++;
-
-    *pDst++ = in1;
-    *pDst++ = in2;
-    *pDst++ = in3;
-    *pDst++ = in4;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* C = A */
-    /* Copy and then store the results in the destination buffer */
-    *pDst++ = *pSrc++;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-}
-
-/**    
- * @} end of BasicCopy group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q15.c
deleted file mode 100644
index e605a72698..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q15.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_copy_q15.c    
-*    
-* Description:	Copies the elements of a Q15 vector.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @addtogroup copy    
- * @{    
- */
-/**    
- * @brief Copies the elements of a Q15 vector.     
- * @param[in]       *pSrc points to input vector    
- * @param[out]      *pDst points to output vector    
- * @param[in]       blockSize length of the input vector   
- * @return none.    
- *    
- */
-
-void arm_copy_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = A */
-    /* Read two inputs */
-    *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;
-    *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* C = A */
-    /* Copy and then store the value in the destination buffer */
-    *pDst++ = *pSrc++;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-}
-
-/**    
- * @} end of BasicCopy group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q31.c
deleted file mode 100644
index 843083db22..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q31.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_copy_q31.c    
-*    
-* Description:	Copies the elements of a Q31 vector.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @addtogroup copy    
- * @{    
- */
-
-/**    
- * @brief Copies the elements of a Q31 vector.     
- * @param[in]       *pSrc points to input vector    
- * @param[out]      *pDst points to output vector    
- * @param[in]       blockSize length of the input vector   
- * @return none.    
- *    
- */
-
-void arm_copy_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  uint32_t blkCnt;                               /* loop counter */
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  q31_t in1, in2, in3, in4;
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = A */
-    /* Copy and then store the values in the destination buffer */
-    in1 = *pSrc++;
-    in2 = *pSrc++;
-    in3 = *pSrc++;
-    in4 = *pSrc++;
-
-    *pDst++ = in1;
-    *pDst++ = in2;
-    *pDst++ = in3;
-    *pDst++ = in4;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* C = A */
-    /* Copy and then store the value in the destination buffer */
-    *pDst++ = *pSrc++;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-}
-
-/**    
- * @} end of BasicCopy group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q7.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q7.c
deleted file mode 100644
index 06288fc0b0..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q7.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_copy_q7.c    
-*    
-* Description:	Copies the elements of a Q7 vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @addtogroup copy    
- * @{    
- */
-
-/**    
- * @brief Copies the elements of a Q7 vector.    
- * @param[in]       *pSrc points to input vector    
- * @param[out]      *pDst points to output vector    
- * @param[in]       blockSize length of the input vector   
- * @return none.    
- *    
- */
-
-void arm_copy_q7(
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize)
-{
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = A */
-    /* Copy and then store the results in the destination buffer */
-    /* 4 samples are copied and stored at a time using SIMD */
-    *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-
-  while(blkCnt > 0u)
-  {
-    /* C = A */
-    /* Copy and then store the results in the destination buffer */
-    *pDst++ = *pSrc++;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-}
-
-/**    
- * @} end of BasicCopy group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_f32.c
deleted file mode 100644
index 98d6635f58..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_f32.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_fill_f32.c    
-*    
-* Description:	Fills a constant value into a floating-point vector.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @defgroup Fill Vector Fill    
- *    
- * Fills the destination vector with a constant value.    
- *    
- * 
    
- * 	pDst[n] = value;   0 <= n < blockSize.    
- * 
    
- *   
- * There are separate functions for floating point, Q31, Q15, and Q7 data types.     
- */
-
-/**    
- * @addtogroup Fill    
- * @{    
- */
-
-/**    
- * @brief Fills a constant value into a floating-point vector.     
- * @param[in]       value input value to be filled   
- * @param[out]      *pDst points to output vector    
- * @param[in]       blockSize length of the output vector   
- * @return none.    
- *    
- */
-
-
-void arm_fill_f32(
-  float32_t value,
-  float32_t * pDst,
-  uint32_t blockSize)
-{
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  float32_t in1 = value;
-  float32_t in2 = value;
-  float32_t in3 = value;
-  float32_t in4 = value;
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = value */
-    /* Fill the value in the destination buffer */
-    *pDst++ = in1;
-    *pDst++ = in2;
-    *pDst++ = in3;
-    *pDst++ = in4;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-
-  while(blkCnt > 0u)
-  {
-    /* C = value */
-    /* Fill the value in the destination buffer */
-    *pDst++ = value;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-}
-
-/**    
- * @} end of Fill group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q15.c
deleted file mode 100644
index 9de552934a..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q15.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_fill_q15.c    
-*    
-* Description:	Fills a constant value into a Q15 vector.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @addtogroup Fill    
- * @{    
- */
-
-/**    
- * @brief Fills a constant value into a Q15 vector.    
- * @param[in]       value input value to be filled   
- * @param[out]      *pDst points to output vector    
- * @param[in]       blockSize length of the output vector   
- * @return none.    
- *    
- */
-
-void arm_fill_q15(
-  q15_t value,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t packedValue;                             /* value packed to 32 bits */
-
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* Packing two 16 bit values to 32 bit value in order to use SIMD */
-  packedValue = __PKHBT(value, value, 16u);
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = value */
-    /* Fill the value in the destination buffer */
-    *__SIMD32(pDst)++ = packedValue;
-    *__SIMD32(pDst)++ = packedValue;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* C = value */
-    /* Fill the value in the destination buffer */
-    *pDst++ = value;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-}
-
-/**    
- * @} end of Fill group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q31.c
deleted file mode 100644
index 2d4f22e1e7..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q31.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_fill_q31.c    
-*    
-* Description:	Fills a constant value into a Q31 vector.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @addtogroup Fill    
- * @{    
- */
-
-/**    
- * @brief Fills a constant value into a Q31 vector.    
- * @param[in]       value input value to be filled   
- * @param[out]      *pDst points to output vector    
- * @param[in]       blockSize length of the output vector   
- * @return none.    
- *    
- */
-
-void arm_fill_q31(
-  q31_t value,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  uint32_t blkCnt;                               /* loop counter */
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  q31_t in1 = value;
-  q31_t in2 = value;
-  q31_t in3 = value;
-  q31_t in4 = value;
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = value */
-    /* Fill the value in the destination buffer */
-    *pDst++ = in1;
-    *pDst++ = in2;
-    *pDst++ = in3;
-    *pDst++ = in4;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* C = value */
-    /* Fill the value in the destination buffer */
-    *pDst++ = value;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-}
-
-/**    
- * @} end of Fill group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q7.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q7.c
deleted file mode 100644
index 2a26be451b..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q7.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_fill_q7.c    
-*    
-* Description:	Fills a constant value into a Q7 vector.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @addtogroup Fill    
- * @{    
- */
-
-/**    
- * @brief Fills a constant value into a Q7 vector.    
- * @param[in]       value input value to be filled   
- * @param[out]      *pDst points to output vector    
- * @param[in]       blockSize length of the output vector   
- * @return none.    
- *    
- */
-
-void arm_fill_q7(
-  q7_t value,
-  q7_t * pDst,
-  uint32_t blockSize)
-{
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t packedValue;                             /* value packed to 32 bits */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* Packing four 8 bit values to 32 bit value in order to use SIMD */
-  packedValue = __PACKq7(value, value, value, value);
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = value */
-    /* Fill the value in the destination buffer */
-    *__SIMD32(pDst)++ = packedValue;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* C = value */
-    /* Fill the value in the destination buffer */
-    *pDst++ = value;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-}
-
-/**    
- * @} end of Fill group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q15.c
deleted file mode 100644
index 8ff2efd197..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q15.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_float_to_q15.c    
-*    
-* Description:	Converts the elements of the floating-point vector to Q15 vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @addtogroup float_to_x    
- * @{    
- */
-
-/**    
- * @brief Converts the elements of the floating-point vector to Q15 vector.    
- * @param[in]       *pSrc points to the floating-point input vector    
- * @param[out]      *pDst points to the Q15 output vector   
- * @param[in]       blockSize length of the input vector    
- * @return none.    
- *    
- * \par Description:    
- * \par   
- * The equation used for the conversion process is:    
- * 
    
- * 	pDst[n] = (q15_t)(pSrc[n] * 32768);   0 <= n < blockSize.    
- * 
    
- * \par Scaling and Overflow Behavior:    
- * \par    
- * The function uses saturating arithmetic.    
- * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.    
- * \note   
- * In order to apply rounding, the library should be rebuilt with the ROUNDING macro     
- * defined in the preprocessor section of project options.     
- *    
- */
-
-
-void arm_float_to_q15(
-  float32_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  float32_t *pIn = pSrc;                         /* Src pointer */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifdef ARM_MATH_ROUNDING
-
-  float32_t in;
-
-#endif /*      #ifdef ARM_MATH_ROUNDING        */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-
-#ifdef ARM_MATH_ROUNDING
-    /* C = A * 32768 */
-    /* convert from float to q15 and then store the results in the destination buffer */
-    in = *pIn++;
-    in = (in * 32768.0f);
-    in += in > 0 ? 0.5 : -0.5;
-    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
-
-    in = *pIn++;
-    in = (in * 32768.0f);
-    in += in > 0 ? 0.5 : -0.5;
-    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
-
-    in = *pIn++;
-    in = (in * 32768.0f);
-    in += in > 0 ? 0.5 : -0.5;
-    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
-
-    in = *pIn++;
-    in = (in * 32768.0f);
-    in += in > 0 ? 0.5 : -0.5;
-    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
-
-#else
-
-    /* C = A * 32768 */
-    /* convert from float to q15 and then store the results in the destination buffer */
-    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
-    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
-    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
-    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
-
-#endif /*      #ifdef ARM_MATH_ROUNDING        */
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-
-#ifdef ARM_MATH_ROUNDING
-    /* C = A * 32768 */
-    /* convert from float to q15 and then store the results in the destination buffer */
-    in = *pIn++;
-    in = (in * 32768.0f);
-    in += in > 0 ? 0.5 : -0.5;
-    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
-
-#else
-
-    /* C = A * 32768 */
-    /* convert from float to q15 and then store the results in the destination buffer */
-    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
-
-#endif /*      #ifdef ARM_MATH_ROUNDING        */
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-
-#ifdef ARM_MATH_ROUNDING
-    /* C = A * 32768 */
-    /* convert from float to q15 and then store the results in the destination buffer */
-    in = *pIn++;
-    in = (in * 32768.0f);
-    in += in > 0 ? 0.5f : -0.5f;
-    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
-
-#else
-
-    /* C = A * 32768 */
-    /* convert from float to q15 and then store the results in the destination buffer */
-    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
-
-#endif /*      #ifdef ARM_MATH_ROUNDING        */
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
- * @} end of float_to_x group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q31.c
deleted file mode 100644
index 1244c8b753..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q31.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_float_to_q31.c    
-*    
-* Description:	Converts the elements of the floating-point vector to Q31 vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @defgroup float_to_x  Convert 32-bit floating point value    
- */
-
-/**    
- * @addtogroup float_to_x    
- * @{    
- */
-
-/**    
- * @brief Converts the elements of the floating-point vector to Q31 vector.    
- * @param[in]       *pSrc points to the floating-point input vector    
- * @param[out]      *pDst points to the Q31 output vector   
- * @param[in]       blockSize length of the input vector    
- * @return none.    
- *    
- *\par Description:    
- * \par   
- * The equation used for the conversion process is:    
- *   
- * 
    
- * 	pDst[n] = (q31_t)(pSrc[n] * 2147483648);   0 <= n < blockSize.    
- * 
    
- * Scaling and Overflow Behavior:    
- * \par    
- * The function uses saturating arithmetic.    
- * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.    
- *   
- * \note In order to apply rounding, the library should be rebuilt with the ROUNDING macro     
- * defined in the preprocessor section of project options.     
- */
-
-
-void arm_float_to_q31(
-  float32_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  float32_t *pIn = pSrc;                         /* Src pointer */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifdef ARM_MATH_ROUNDING
-
-  float32_t in;
-
-#endif /*      #ifdef ARM_MATH_ROUNDING        */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-
-#ifdef ARM_MATH_ROUNDING
-
-    /* C = A * 32768 */
-    /* convert from float to Q31 and then store the results in the destination buffer */
-    in = *pIn++;
-    in = (in * 2147483648.0f);
-    in += in > 0 ? 0.5 : -0.5;
-    *pDst++ = clip_q63_to_q31((q63_t) (in));
-
-    in = *pIn++;
-    in = (in * 2147483648.0f);
-    in += in > 0 ? 0.5 : -0.5;
-    *pDst++ = clip_q63_to_q31((q63_t) (in));
-
-    in = *pIn++;
-    in = (in * 2147483648.0f);
-    in += in > 0 ? 0.5 : -0.5;
-    *pDst++ = clip_q63_to_q31((q63_t) (in));
-
-    in = *pIn++;
-    in = (in * 2147483648.0f);
-    in += in > 0 ? 0.5 : -0.5;
-    *pDst++ = clip_q63_to_q31((q63_t) (in));
-
-#else
-
-    /* C = A * 2147483648 */
-    /* convert from float to Q31 and then store the results in the destination buffer */
-    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
-    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
-    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
-    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
-
-#endif /*      #ifdef ARM_MATH_ROUNDING        */
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-
-#ifdef ARM_MATH_ROUNDING
-
-    /* C = A * 2147483648 */
-    /* convert from float to Q31 and then store the results in the destination buffer */
-    in = *pIn++;
-    in = (in * 2147483648.0f);
-    in += in > 0 ? 0.5 : -0.5;
-    *pDst++ = clip_q63_to_q31((q63_t) (in));
-
-#else
-
-    /* C = A * 2147483648 */
-    /* convert from float to Q31 and then store the results in the destination buffer */
-    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
-
-#endif /*      #ifdef ARM_MATH_ROUNDING        */
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-
-#ifdef ARM_MATH_ROUNDING
-
-    /* C = A * 2147483648 */
-    /* convert from float to Q31 and then store the results in the destination buffer */
-    in = *pIn++;
-    in = (in * 2147483648.0f);
-    in += in > 0 ? 0.5f : -0.5f;
-    *pDst++ = clip_q63_to_q31((q63_t) (in));
-
-#else
-
-    /* C = A * 2147483648 */
-    /* convert from float to Q31 and then store the results in the destination buffer */
-    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
-
-#endif /*      #ifdef ARM_MATH_ROUNDING        */
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
- * @} end of float_to_x group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q7.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q7.c
deleted file mode 100644
index e43f0531ee..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q7.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_float_to_q7.c    
-*    
-* Description:	Converts the elements of the floating-point vector to Q7 vector.   
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @addtogroup float_to_x    
- * @{    
- */
-
-/**    
- * @brief Converts the elements of the floating-point vector to Q7 vector.    
- * @param[in]       *pSrc points to the floating-point input vector    
- * @param[out]      *pDst points to the Q7 output vector   
- * @param[in]       blockSize length of the input vector    
- * @return none.    
- *    
- *\par Description:    
- * \par   
- * The equation used for the conversion process is:    
- * 
    
- * 	pDst[n] = (q7_t)(pSrc[n] * 128);   0 <= n < blockSize.    
- * 
    
- * \par Scaling and Overflow Behavior:    
- * \par    
- * The function uses saturating arithmetic.    
- * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.    
- * \note   
- * In order to apply rounding, the library should be rebuilt with the ROUNDING macro     
- * defined in the preprocessor section of project options.     
- */
-
-
-void arm_float_to_q7(
-  float32_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize)
-{
-  float32_t *pIn = pSrc;                         /* Src pointer */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifdef ARM_MATH_ROUNDING
-
-  float32_t in;
-
-#endif /*      #ifdef ARM_MATH_ROUNDING        */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-
-#ifdef ARM_MATH_ROUNDING
-    /* C = A * 128 */
-    /* convert from float to q7 and then store the results in the destination buffer */
-    in = *pIn++;
-    in = (in * 128);
-    in += in > 0 ? 0.5 : -0.5;
-    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
-
-    in = *pIn++;
-    in = (in * 128);
-    in += in > 0 ? 0.5 : -0.5;
-    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
-
-    in = *pIn++;
-    in = (in * 128);
-    in += in > 0 ? 0.5 : -0.5;
-    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
-
-    in = *pIn++;
-    in = (in * 128);
-    in += in > 0 ? 0.5 : -0.5;
-    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
-
-#else
-
-    /* C = A * 128 */
-    /* convert from float to q7 and then store the results in the destination buffer */
-    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
-    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
-    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
-    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
-
-#endif /*      #ifdef ARM_MATH_ROUNDING        */
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-  while(blkCnt > 0u)
-  {
-
-#ifdef ARM_MATH_ROUNDING
-    /* C = A * 128 */
-    /* convert from float to q7 and then store the results in the destination buffer */
-    in = *pIn++;
-    in = (in * 128);
-    in += in > 0 ? 0.5 : -0.5;
-    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
-
-#else
-
-    /* C = A * 128 */
-    /* convert from float to q7 and then store the results in the destination buffer */
-    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
-
-#endif /*      #ifdef ARM_MATH_ROUNDING        */
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-  while(blkCnt > 0u)
-  {
-#ifdef ARM_MATH_ROUNDING
-    /* C = A * 128 */
-    /* convert from float to q7 and then store the results in the destination buffer */
-    in = *pIn++;
-    in = (in * 128.0f);
-    in += in > 0 ? 0.5f : -0.5f;
-    *pDst++ = (q7_t) (__SSAT((q31_t) (in), 8));
-
-#else
-
-    /* C = A * 128 */
-    /* convert from float to q7 and then store the results in the destination buffer */
-    *pDst++ = (q7_t) __SSAT((q31_t) (*pIn++ * 128.0f), 8);
-
-#endif /*      #ifdef ARM_MATH_ROUNDING        */
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
- * @} end of float_to_x group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_float.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_float.c
deleted file mode 100644
index c927358515..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_float.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_q15_to_float.c    
-*    
-* Description:	Converts the elements of the Q15 vector to floating-point vector.     
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @defgroup q15_to_x  Convert 16-bit Integer value    
- */
-
-/**    
- * @addtogroup q15_to_x    
- * @{    
- */
-
-
-
-
-/**    
- * @brief  Converts the elements of the Q15 vector to floating-point vector.     
- * @param[in]       *pSrc points to the Q15 input vector    
- * @param[out]      *pDst points to the floating-point output vector   
- * @param[in]       blockSize length of the input vector    
- * @return none.    
- *    
- * \par Description:    
- *    
- * The equation used for the conversion process is:    
- *   
- * 
    
- * 	pDst[n] = (float32_t) pSrc[n] / 32768;   0 <= n < blockSize.    
- * 
    
- *   
- */
-
-
-void arm_q15_to_float(
-  q15_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pIn = pSrc;                             /* Src pointer */
-  uint32_t blkCnt;                               /* loop counter */
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (float32_t) A / 32768 */
-    /* convert from q15 to float and then store the results in the destination buffer */
-    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
-    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
-    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
-    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* C = (float32_t) A / 32768 */
-    /* convert from q15 to float and then store the results in the destination buffer */
-    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-}
-
-/**    
- * @} end of q15_to_x group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q31.c
deleted file mode 100644
index d785e93018..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q31.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_q15_to_q31.c    
-*    
-* Description:	Converts the elements of the Q15 vector to Q31 vector.  
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @addtogroup q15_to_x    
- * @{    
- */
-
-/**    
- * @brief Converts the elements of the Q15 vector to Q31 vector.     
- * @param[in]       *pSrc points to the Q15 input vector    
- * @param[out]      *pDst points to the Q31 output vector   
- * @param[in]       blockSize length of the input vector    
- * @return none.    
- *    
- * \par Description:    
- *    
- * The equation used for the conversion process is:   
- *   
- * 
    
- * 	pDst[n] = (q31_t) pSrc[n] << 16;   0 <= n < blockSize.    
- * 
    
- *   
- */
-
-
-void arm_q15_to_q31(
-  q15_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pIn = pSrc;                             /* Src pointer */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  q31_t in1, in2;
-  q31_t out1, out2, out3, out4;
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (q31_t)A << 16 */
-    /* convert from q15 to q31 and then store the results in the destination buffer */
-    in1 = *__SIMD32(pIn)++;
-    in2 = *__SIMD32(pIn)++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    /* extract lower 16 bits to 32 bit result */
-    out1 = in1 << 16u;
-    /* extract upper 16 bits to 32 bit result */
-    out2 = in1 & 0xFFFF0000;
-    /* extract lower 16 bits to 32 bit result */
-    out3 = in2 << 16u;
-    /* extract upper 16 bits to 32 bit result */
-    out4 = in2 & 0xFFFF0000;
-
-#else
-
-    /* extract upper 16 bits to 32 bit result */
-    out1 = in1 & 0xFFFF0000;
-    /* extract lower 16 bits to 32 bit result */
-    out2 = in1 << 16u;
-    /* extract upper 16 bits to 32 bit result */
-    out3 = in2 & 0xFFFF0000;
-    /* extract lower 16 bits to 32 bit result */
-    out4 = in2 << 16u;
-
-#endif //      #ifndef ARM_MATH_BIG_ENDIAN
-
-    *pDst++ = out1;
-    *pDst++ = out2;
-    *pDst++ = out3;
-    *pDst++ = out4;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* C = (q31_t)A << 16 */
-    /* convert from q15 to q31 and then store the results in the destination buffer */
-    *pDst++ = (q31_t) * pIn++ << 16;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-}
-
-/**    
- * @} end of q15_to_x group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q7.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q7.c
deleted file mode 100644
index 8d9a9be044..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q7.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_q15_to_q7.c    
-*    
-* Description:	Converts the elements of the Q15 vector to Q7 vector.  
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @addtogroup q15_to_x    
- * @{    
- */
-
-
-/**    
- * @brief Converts the elements of the Q15 vector to Q7 vector.     
- * @param[in]       *pSrc points to the Q15 input vector    
- * @param[out]      *pDst points to the Q7 output vector   
- * @param[in]       blockSize length of the input vector    
- * @return none.    
- *    
- * \par Description:    
- *    
- * The equation used for the conversion process is:    
- *   
- * 
    
- * 	pDst[n] = (q7_t) pSrc[n] >> 8;   0 <= n < blockSize.    
- * 
   
- *   
- */
-
-
-void arm_q15_to_q7(
-  q15_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize)
-{
-  q15_t *pIn = pSrc;                             /* Src pointer */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  q31_t in1, in2;
-  q31_t out1, out2;
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (q7_t) A >> 8 */
-    /* convert from q15 to q7 and then store the results in the destination buffer */
-    in1 = *__SIMD32(pIn)++;
-    in2 = *__SIMD32(pIn)++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    out1 = __PKHTB(in2, in1, 16);
-    out2 = __PKHBT(in2, in1, 16);
-
-#else
-
-    out1 = __PKHTB(in1, in2, 16);
-    out2 = __PKHBT(in1, in2, 16);
-
-#endif //      #ifndef ARM_MATH_BIG_ENDIAN
-
-    /* rotate packed value by 24 */
-    out2 = ((uint32_t) out2 << 8) | ((uint32_t) out2 >> 24);
-
-    /* anding with 0xff00ff00 to get two 8 bit values */
-    out1 = out1 & 0xFF00FF00;
-    /* anding with 0x00ff00ff to get two 8 bit values */
-    out2 = out2 & 0x00FF00FF;
-
-    /* oring two values(contains two 8 bit values) to get four packed 8 bit values */
-    out1 = out1 | out2;
-
-    /* store 4 samples at a time to destiantion buffer */
-    *__SIMD32(pDst)++ = out1;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* C = (q7_t) A >> 8 */
-    /* convert from q15 to q7 and then store the results in the destination buffer */
-    *pDst++ = (q7_t) (*pIn++ >> 8);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-}
-
-/**    
- * @} end of q15_to_x group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_float.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_float.c
deleted file mode 100644
index b2f6de9b26..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_float.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_q31_to_float.c    
-*    
-* Description:	Converts the elements of the Q31 vector to floating-point vector.      
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @defgroup q31_to_x  Convert 32-bit Integer value    
- */
-
-/**    
- * @addtogroup q31_to_x    
- * @{    
- */
-
-/**    
- * @brief Converts the elements of the Q31 vector to floating-point vector.    
- * @param[in]       *pSrc points to the Q31 input vector    
- * @param[out]      *pDst points to the floating-point output vector   
- * @param[in]       blockSize length of the input vector    
- * @return none.    
- *    
- * \par Description:    
- *    
- * The equation used for the conversion process is:    
- *   
- * 
    
- * 	pDst[n] = (float32_t) pSrc[n] / 2147483648;   0 <= n < blockSize.    
- * 
    
- *   
- */
-
-
-void arm_q31_to_float(
-  q31_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize)
-{
-  q31_t *pIn = pSrc;                             /* Src pointer */
-  uint32_t blkCnt;                               /* loop counter */
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (float32_t) A / 2147483648 */
-    /* convert from q31 to float and then store the results in the destination buffer */
-    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
-    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
-    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
-    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* C = (float32_t) A / 2147483648 */
-    /* convert from q31 to float and then store the results in the destination buffer */
-    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-}
-
-/**    
- * @} end of q31_to_x group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q15.c
deleted file mode 100644
index 1c99dbb473..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q15.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_q31_to_q15.c    
-*    
-* Description:	Converts the elements of the Q31 vector to Q15 vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @addtogroup q31_to_x    
- * @{    
- */
-
-/**    
- * @brief Converts the elements of the Q31 vector to Q15 vector.    
- * @param[in]       *pSrc points to the Q31 input vector    
- * @param[out]      *pDst points to the Q15 output vector   
- * @param[in]       blockSize length of the input vector    
- * @return none.    
- *     
- * \par Description:    
- *    
- * The equation used for the conversion process is:    
- *   
- * 
    
- * 	pDst[n] = (q15_t) pSrc[n] >> 16;   0 <= n < blockSize.    
- * 
    
- *   
- */
-
-
-void arm_q31_to_q15(
-  q31_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  q31_t *pIn = pSrc;                             /* Src pointer */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  q31_t in1, in2, in3, in4;
-  q31_t out1, out2;
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (q15_t) A >> 16 */
-    /* convert from q31 to q15 and then store the results in the destination buffer */
-    in1 = *pIn++;
-    in2 = *pIn++;
-    in3 = *pIn++;
-    in4 = *pIn++;
-
-    /* pack two higher 16-bit values from two 32-bit values */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    out1 = __PKHTB(in2, in1, 16);
-    out2 = __PKHTB(in4, in3, 16);
-
-#else
-
-    out1 = __PKHTB(in1, in2, 16);
-    out2 = __PKHTB(in3, in4, 16);
-
-#endif //      #ifdef ARM_MATH_BIG_ENDIAN
-
-    *__SIMD32(pDst)++ = out1;
-    *__SIMD32(pDst)++ = out2;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* C = (q15_t) A >> 16 */
-    /* convert from q31 to q15 and then store the results in the destination buffer */
-    *pDst++ = (q15_t) (*pIn++ >> 16);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-}
-
-/**    
- * @} end of q31_to_x group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q7.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q7.c
deleted file mode 100644
index 2531c11e81..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q7.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_q31_to_q7.c    
-*    
-* Description:	Converts the elements of the Q31 vector to Q7 vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @addtogroup q31_to_x    
- * @{    
- */
-
-/**    
- * @brief Converts the elements of the Q31 vector to Q7 vector.    
- * @param[in]       *pSrc points to the Q31 input vector    
- * @param[out]      *pDst points to the Q7 output vector   
- * @param[in]       blockSize length of the input vector    
- * @return none.    
- *    
- * \par Description:    
- *    
- * The equation used for the conversion process is:    
- *   
- * 
    
- * 	pDst[n] = (q7_t) pSrc[n] >> 24;   0 <= n < blockSize.     
- * 
    
- *   
- */
-
-
-void arm_q31_to_q7(
-  q31_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize)
-{
-  q31_t *pIn = pSrc;                             /* Src pointer */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-  q31_t in1, in2, in3, in4;
-  q7_t out1, out2, out3, out4;
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (q7_t) A >> 24 */
-    /* convert from q31 to q7 and then store the results in the destination buffer */
-    in1 = *pIn++;
-    in2 = *pIn++;
-    in3 = *pIn++;
-    in4 = *pIn++;
-
-    out1 = (q7_t) (in1 >> 24);
-    out2 = (q7_t) (in2 >> 24);
-    out3 = (q7_t) (in3 >> 24);
-    out4 = (q7_t) (in4 >> 24);
-
-    *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* C = (q7_t) A >> 24 */
-    /* convert from q31 to q7 and then store the results in the destination buffer */
-    *pDst++ = (q7_t) (*pIn++ >> 24);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-}
-
-/**    
- * @} end of q31_to_x group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_float.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_float.c
deleted file mode 100644
index 8e3f6f1b7d..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_float.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_q7_to_float.c    
-*    
-* Description:	Converts the elements of the Q7 vector to floating-point vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @defgroup q7_to_x  Convert 8-bit Integer value    
- */
-
-/**    
- * @addtogroup q7_to_x    
- * @{    
- */
-
-/**    
- * @brief Converts the elements of the Q7 vector to floating-point vector.    
- * @param[in]       *pSrc points to the Q7 input vector    
- * @param[out]      *pDst points to the floating-point output vector   
- * @param[in]       blockSize length of the input vector    
- * @return none.    
- *		     
- * \par Description:    
- *    
- * The equation used for the conversion process is:    
- *   
- * 
    
- * 	pDst[n] = (float32_t) pSrc[n] / 128;   0 <= n < blockSize.    
- * 
    
- *   
- */
-
-
-void arm_q7_to_float(
-  q7_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize)
-{
-  q7_t *pIn = pSrc;                              /* Src pointer */
-  uint32_t blkCnt;                               /* loop counter */
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (float32_t) A / 128 */
-    /* convert from q7 to float and then store the results in the destination buffer */
-    *pDst++ = ((float32_t) * pIn++ / 128.0f);
-    *pDst++ = ((float32_t) * pIn++ / 128.0f);
-    *pDst++ = ((float32_t) * pIn++ / 128.0f);
-    *pDst++ = ((float32_t) * pIn++ / 128.0f);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* C = (float32_t) A / 128 */
-    /* convert from q7 to float and then store the results in the destination buffer */
-    *pDst++ = ((float32_t) * pIn++ / 128.0f);
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-}
-
-/**    
- * @} end of q7_to_x group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q15.c
deleted file mode 100644
index a48ec29b82..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q15.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_q7_to_q15.c    
-*    
-* Description:	Converts the elements of the Q7 vector to Q15 vector.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @addtogroup q7_to_x    
- * @{    
- */
-
-
-
-
-/**    
- * @brief Converts the elements of the Q7 vector to Q15 vector.    
- * @param[in]       *pSrc points to the Q7 input vector    
- * @param[out]      *pDst points to the Q15 output vector   
- * @param[in]       blockSize length of the input vector    
- * @return none.    
- *    
- * \par Description:    
- *    
- * The equation used for the conversion process is:    
- *   
- * 
    
- * 	pDst[n] = (q15_t) pSrc[n] << 8;   0 <= n < blockSize.    
- * 
    
- *   
- */
-
-
-void arm_q7_to_q15(
-  q7_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize)
-{
-  q7_t *pIn = pSrc;                              /* Src pointer */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0
-  q31_t in;
-  q31_t in1, in2;
-  q31_t out1, out2;
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (q15_t) A << 8 */
-    /* convert from q7 to q15 and then store the results in the destination buffer */
-    in = *__SIMD32(pIn)++;
-
-    /* rotatate in by 8 and extend two q7_t values to q15_t values */
-    in1 = __SXTB16(__ROR(in, 8));
-
-    /* extend remainig two q7_t values to q15_t values */
-    in2 = __SXTB16(in);
-
-    in1 = in1 << 8u;
-    in2 = in2 << 8u;
-
-    in1 = in1 & 0xFF00FF00;
-    in2 = in2 & 0xFF00FF00;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    out2 = __PKHTB(in1, in2, 16);
-    out1 = __PKHBT(in2, in1, 16);
-
-#else
-
-    out1 = __PKHTB(in1, in2, 16);
-    out2 = __PKHBT(in2, in1, 16);
-
-#endif
-
-    *__SIMD32(pDst)++ = out1;
-    *__SIMD32(pDst)++ = out2;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* C = (q15_t) A << 8 */
-    /* convert from q7 to q15 and then store the results in the destination buffer */
-    *pDst++ = (q15_t) * pIn++ << 8;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-}
-
-/**    
- * @} end of q7_to_x group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q31.c
deleted file mode 100644
index 0607a9a4c8..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q31.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/* ----------------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:		arm_q7_to_q31.c    
-*    
-* Description:	Converts the elements of the Q7 vector to Q31 vector.  
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* ---------------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupSupport    
- */
-
-/**    
- * @addtogroup q7_to_x    
- * @{    
- */
-
-/**    
- * @brief Converts the elements of the Q7 vector to Q31 vector.    
- * @param[in]       *pSrc points to the Q7 input vector    
- * @param[out]      *pDst points to the Q31 output vector   
- * @param[in]       blockSize length of the input vector    
- * @return none.    
- *    
- * \par Description:    
- *    
- * The equation used for the conversion process is:    
- *   
- * 
    
- * 	pDst[n] = (q31_t) pSrc[n] << 24;   0 <= n < blockSize.   
- * 
     
- *   
- */
-
-
-void arm_q7_to_q31(
-  q7_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize)
-{
-  q7_t *pIn = pSrc;                              /* Src pointer */
-  uint32_t blkCnt;                               /* loop counter */
-
-#ifndef ARM_MATH_CM0
-
-  q31_t in;
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /*loop Unrolling */
-  blkCnt = blockSize >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  while(blkCnt > 0u)
-  {
-    /* C = (q31_t) A << 24 */
-    /* convert from q7 to q31 and then store the results in the destination buffer */
-    in = *__SIMD32(pIn)++;
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    *pDst++ = (__ROR(in, 8)) & 0xFF000000;
-    *pDst++ = (__ROR(in, 16)) & 0xFF000000;
-    *pDst++ = (__ROR(in, 24)) & 0xFF000000;
-    *pDst++ = (in & 0xFF000000);
-
-#else
-
-    *pDst++ = (in & 0xFF000000);
-    *pDst++ = (__ROR(in, 24)) & 0xFF000000;
-    *pDst++ = (__ROR(in, 16)) & 0xFF000000;
-    *pDst++ = (__ROR(in, 8)) & 0xFF000000;
-
-#endif //              #ifndef ARM_MATH_BIG_ENDIAN
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  blkCnt = blockSize % 0x4u;
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Loop over blockSize number of values */
-  blkCnt = blockSize;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-  while(blkCnt > 0u)
-  {
-    /* C = (q31_t) A << 24 */
-    /* convert from q7 to q31 and then store the results in the destination buffer */
-    *pDst++ = (q31_t) * pIn++ << 24;
-
-    /* Decrement the loop counter */
-    blkCnt--;
-  }
-
-}
-
-/**    
- * @} end of q7_to_x group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_bitreversal.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_bitreversal.c
deleted file mode 100644
index 5529914755..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_bitreversal.c
+++ /dev/null
@@ -1,222 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_bitreversal.c    
-*    
-* Description:	This file has common tables like Bitreverse, reciprocal etc which are used across different functions    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Initial Version  
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/*    
- * @brief  In-place bit reversal function.   
- * @param[in, out] *pSrc        points to the in-place buffer of floating-point data type.   
- * @param[in]      fftSize      length of the FFT.   
- * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table.   
- * @param[in]      *pBitRevTab  points to the bit reversal table.   
- * @return none.   
- */
-
-void arm_bitreversal_f32(
-  float32_t * pSrc,
-  uint16_t fftSize,
-  uint16_t bitRevFactor,
-  uint16_t * pBitRevTab)
-{
-  uint16_t fftLenBy2, fftLenBy2p1;
-  uint16_t i, j;
-  float32_t in;
-
-  /*  Initializations */
-  j = 0u;
-  fftLenBy2 = fftSize >> 1u;
-  fftLenBy2p1 = (fftSize >> 1u) + 1u;
-
-  /* Bit Reversal Implementation */
-  for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
-  {
-    if(i < j)
-    {
-      /*  pSrc[i] <-> pSrc[j]; */
-      in = pSrc[2u * i];
-      pSrc[2u * i] = pSrc[2u * j];
-      pSrc[2u * j] = in;
-
-      /*  pSrc[i+1u] <-> pSrc[j+1u] */
-      in = pSrc[(2u * i) + 1u];
-      pSrc[(2u * i) + 1u] = pSrc[(2u * j) + 1u];
-      pSrc[(2u * j) + 1u] = in;
-
-      /*  pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */
-      in = pSrc[2u * (i + fftLenBy2p1)];
-      pSrc[2u * (i + fftLenBy2p1)] = pSrc[2u * (j + fftLenBy2p1)];
-      pSrc[2u * (j + fftLenBy2p1)] = in;
-
-      /*  pSrc[i+fftLenBy2p1+1u] <-> pSrc[j+fftLenBy2p1+1u] */
-      in = pSrc[(2u * (i + fftLenBy2p1)) + 1u];
-      pSrc[(2u * (i + fftLenBy2p1)) + 1u] =
-        pSrc[(2u * (j + fftLenBy2p1)) + 1u];
-      pSrc[(2u * (j + fftLenBy2p1)) + 1u] = in;
-
-    }
-
-    /*  pSrc[i+1u] <-> pSrc[j+1u] */
-    in = pSrc[2u * (i + 1u)];
-    pSrc[2u * (i + 1u)] = pSrc[2u * (j + fftLenBy2)];
-    pSrc[2u * (j + fftLenBy2)] = in;
-
-    /*  pSrc[i+2u] <-> pSrc[j+2u] */
-    in = pSrc[(2u * (i + 1u)) + 1u];
-    pSrc[(2u * (i + 1u)) + 1u] = pSrc[(2u * (j + fftLenBy2)) + 1u];
-    pSrc[(2u * (j + fftLenBy2)) + 1u] = in;
-
-    /*  Reading the index for the bit reversal */
-    j = *pBitRevTab;
-
-    /*  Updating the bit reversal index depending on the fft length  */
-    pBitRevTab += bitRevFactor;
-  }
-}
-
-
-
-/*    
- * @brief  In-place bit reversal function.   
- * @param[in, out] *pSrc        points to the in-place buffer of Q31 data type.   
- * @param[in]      fftLen       length of the FFT.   
- * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table   
- * @param[in]      *pBitRevTab  points to bit reversal table.   
- * @return none.   
- */
-
-void arm_bitreversal_q31(
-  q31_t * pSrc,
-  uint32_t fftLen,
-  uint16_t bitRevFactor,
-  uint16_t * pBitRevTable)
-{
-  uint32_t fftLenBy2, fftLenBy2p1, i, j;
-  q31_t in;
-
-  /*  Initializations      */
-  j = 0u;
-  fftLenBy2 = fftLen / 2u;
-  fftLenBy2p1 = (fftLen / 2u) + 1u;
-
-  /* Bit Reversal Implementation */
-  for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
-  {
-    if(i < j)
-    {
-      /*  pSrc[i] <-> pSrc[j]; */
-      in = pSrc[2u * i];
-      pSrc[2u * i] = pSrc[2u * j];
-      pSrc[2u * j] = in;
-
-      /*  pSrc[i+1u] <-> pSrc[j+1u] */
-      in = pSrc[(2u * i) + 1u];
-      pSrc[(2u * i) + 1u] = pSrc[(2u * j) + 1u];
-      pSrc[(2u * j) + 1u] = in;
-
-      /*  pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */
-      in = pSrc[2u * (i + fftLenBy2p1)];
-      pSrc[2u * (i + fftLenBy2p1)] = pSrc[2u * (j + fftLenBy2p1)];
-      pSrc[2u * (j + fftLenBy2p1)] = in;
-
-      /*  pSrc[i+fftLenBy2p1+1u] <-> pSrc[j+fftLenBy2p1+1u] */
-      in = pSrc[(2u * (i + fftLenBy2p1)) + 1u];
-      pSrc[(2u * (i + fftLenBy2p1)) + 1u] =
-        pSrc[(2u * (j + fftLenBy2p1)) + 1u];
-      pSrc[(2u * (j + fftLenBy2p1)) + 1u] = in;
-
-    }
-
-    /*  pSrc[i+1u] <-> pSrc[j+1u] */
-    in = pSrc[2u * (i + 1u)];
-    pSrc[2u * (i + 1u)] = pSrc[2u * (j + fftLenBy2)];
-    pSrc[2u * (j + fftLenBy2)] = in;
-
-    /*  pSrc[i+2u] <-> pSrc[j+2u] */
-    in = pSrc[(2u * (i + 1u)) + 1u];
-    pSrc[(2u * (i + 1u)) + 1u] = pSrc[(2u * (j + fftLenBy2)) + 1u];
-    pSrc[(2u * (j + fftLenBy2)) + 1u] = in;
-
-    /*  Reading the index for the bit reversal */
-    j = *pBitRevTable;
-
-    /*  Updating the bit reversal index depending on the fft length */
-    pBitRevTable += bitRevFactor;
-  }
-}
-
-
-
-/*    
-   * @brief  In-place bit reversal function.   
-   * @param[in, out] *pSrc        points to the in-place buffer of Q15 data type.   
-   * @param[in]      fftLen       length of the FFT.   
-   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table   
-   * @param[in]      *pBitRevTab  points to bit reversal table.   
-   * @return none.   
- */
-
-void arm_bitreversal_q15(
-  q15_t * pSrc16,
-  uint32_t fftLen,
-  uint16_t bitRevFactor,
-  uint16_t * pBitRevTab)
-{
-  q31_t *pSrc = (q31_t *) pSrc16;
-  q31_t in;
-  uint32_t fftLenBy2, fftLenBy2p1;
-  uint32_t i, j;
-
-  /*  Initializations */
-  j = 0u;
-  fftLenBy2 = fftLen / 2u;
-  fftLenBy2p1 = (fftLen / 2u) + 1u;
-
-  /* Bit Reversal Implementation */
-  for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
-  {
-    if(i < j)
-    {
-      /*  pSrc[i] <-> pSrc[j]; */
-      /*  pSrc[i+1u] <-> pSrc[j+1u] */
-      in = pSrc[i];
-      pSrc[i] = pSrc[j];
-      pSrc[j] = in;
-
-      /*  pSrc[i + fftLenBy2p1] <-> pSrc[j + fftLenBy2p1];  */
-      /*  pSrc[i + fftLenBy2p1+1u] <-> pSrc[j + fftLenBy2p1+1u] */
-      in = pSrc[i + fftLenBy2p1];
-      pSrc[i + fftLenBy2p1] = pSrc[j + fftLenBy2p1];
-      pSrc[j + fftLenBy2p1] = in;
-    }
-
-    /*  pSrc[i+1u] <-> pSrc[j+fftLenBy2];         */
-    /*  pSrc[i+2] <-> pSrc[j+fftLenBy2+1u]  */
-    in = pSrc[i + 1u];
-    pSrc[i + 1u] = pSrc[j + fftLenBy2];
-    pSrc[j + fftLenBy2] = in;
-
-    /*  Reading the index for the bit reversal */
-    j = *pBitRevTab;
-
-    /*  Updating the bit reversal index depending on the fft length  */
-    pBitRevTab += bitRevFactor;
-  }
-}
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_f32.c
deleted file mode 100644
index 3cfc45fd9a..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_f32.c
+++ /dev/null
@@ -1,511 +0,0 @@
-/* ----------------------------------------------------------------------   
-* Copyright (C) 2010 ARM Limited. All rights reserved.   
-*   
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*   
-* Project: 	    CMSIS DSP Library   
-* Title:	    arm_cfft_radix2_f32.c   
-*   
-* Description:	Radix-2 Decimation in Frequency CFFT & CIFFT Floating point processing function   
-*   
-*   
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.3 2010/11/29  
-*    Initial version   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**   
- * @ingroup groupTransforms   
- */
-
-/**   
- * @defgroup Radix2_CFFT_CIFFT Radix-2 Complex FFT Functions   
- *   
- * \par   
- * Complex Fast Fourier Transform(CFFT) and Complex Inverse Fast Fourier Transform(CIFFT) is an efficient algorithm to compute Discrete Fourier Transform(DFT) and Inverse Discrete Fourier Transform(IDFT).   
- * Computational complexity of CFFT reduces drastically when compared to DFT.   
- * \par   
- * This set of functions implements CFFT/CIFFT   
- * for Q15, Q31, and floating-point data types.  The functions operates on in-place buffer which uses same buffer for input and output.   
- * Complex input is stored in input buffer in an interleaved fashion.   
- *   
- * \par   
- * The functions operate on blocks of input and output data and each call to the function processes   
- * 2*fftLen samples through the transform.  pSrc  points to In-place arrays containing 2*fftLen values.   
- * \par  
- * The pSrc points to the array of in-place buffer of size 2*fftLen and inputs and outputs are stored in an interleaved fashion as shown below.   
- * 
 {real[0], imag[0], real[1], imag[1],..} 
   
- *   
- * \par Lengths supported by the transform:  
- * \par   
- * Internally, the function utilize a radix-2 decimation in frequency(DIF) algorithm   
- * and the size of the FFT supported are of the lengths [16, 32, 64, 128, 256, 512, 1024, 2048, 4096].  
- *    
- *   
- * \par Algorithm:   
- *   
- * Complex Fast Fourier Transform:   
- * \par    
- * Input real and imaginary data:   
- * 
   
- * x(n) = xa + j * ya   
- * x(n+N/2 ) = xb + j * yb   
- * 
   
- * where N is length of FFT   
- * \par   
- * Output real and imaginary data:   
- * 
   
- * X(2r) = xa'+ j * ya'   
- * X(2r+1) = xb'+ j * yb'   
- * 
   
- * \par   
- * Twiddle factors for radix-2 FFT:   
- * 
   
- * Wn = cosVal + j * (- sinVal)   
- * 
   
- *   
- * \par   
- * \image html CFFT_Radix2.gif "Radix-2 Decimation-in Frequency Complex Fast Fourier Transform"   
- *   
- * \par   
- * Output from Radix-2 CFFT Results in Digit reversal order. Interchange middle two branches of every butterfly results in Bit reversed output.   
- * \par   
- *  Butterfly CFFT equations:   
- * 
   
- * xa' = xa + xb  
- * ya' = ya + yb  
- * xb' = (xa-xb)* cosVal + (ya-yb) * sinVal   
- * yb' = (ya-yb)* cosVal - (xa-xb) * sinVal   
- * 
   
- *   
- *   
- * Complex Inverse Fast Fourier Transform:   
- * \par   
- * CIFFT uses same twiddle factor table as CFFT with modifications in the design equation as shown below.   
- *   
- * \par   
- *  Modified Butterfly CIFFT equations:   
- * 
   
- * xa' = xa + xb  
- * ya' = ya + yb  
- * xb' = (xa-xb)* cosVal - (ya-yb) * sinVal   
- * yb' = (ya-yb)* cosVal + (xa-xb) * sinVal   
- * 
   
- *   
- * \par Instance Structure   
- * A separate instance structure must be defined for each Instance but the twiddle factors and bit reversal tables can be reused.   
- * There are separate instance structure declarations for each of the 3 supported data types.   
- *   
- * \par Initialization Functions   
- * There is also an associated initialization function for each data type.   
- * The initialization function performs the following operations:   
- * - Sets the values of the internal structure fields.   
- * - Initializes twiddle factor table and bit reversal table pointers   
- * \par   
- * Use of the initialization function is optional.   
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
- * To place an instance structure into a const data section, the instance structure must be manually initialized.   
- * Manually initialize the instance structure as follows:   
- * 
   
- *arm_cfft_radix2_instance_f32 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor, onebyfftLen};   
- *arm_cfft_radix2_instance_q31 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};   
- *arm_cfft_radix2_instance_q15 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};   
- * 
   
- * \par   
- * where fftLen length of CFFT/CIFFT; ifftFlag Flag for selection of CFFT or CIFFT(Set ifftFlag to calculate CIFFT otherwise calculates CFFT);   
- * bitReverseFlag Flag for selection of output order(Set bitReverseFlag to output in normal order otherwise output in bit reversed order);    
- * pTwiddlepoints to array of twiddle coefficients; pBitRevTable points to the array of bit reversal table.   
- * twidCoefModifier modifier for twiddle factor table which supports all FFT lengths with same table;    
- * pBitRevTable modifier for bit reversal table which supports all FFT lengths with same table.   
- * onebyfftLen value of 1/fftLen to calculate CIFFT;   
- *  
- * \par Fixed-Point Behavior   
- * Care must be taken when using the fixed-point versions of the CFFT/CIFFT function.   
- * Refer to the function specific documentation below for usage guidelines.   
- */
-
-
-/**   
- * @addtogroup Radix2_CFFT_CIFFT   
- * @{   
- */
-
-/**   
- * @details   
- * @brief Processing function for the floating-point Radix-2 CFFT/CIFFT.  
- * @param[in]      *S    points to an instance of the floating-point Radix-2 CFFT/CIFFT structure.  
- * @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.  
- * @return none.  
- */
-
-void arm_cfft_radix2_f32(
-  const arm_cfft_radix2_instance_f32 * S,
-  float32_t * pSrc)
-{
-
-  if(S->ifftFlag == 1u)
-  {
-    /*  Complex IFFT radix-2  */
-    arm_radix2_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle,
-                                     S->twidCoefModifier, S->onebyfftLen);
-  }
-  else
-  {
-    /*  Complex FFT radix-2  */
-    arm_radix2_butterfly_f32(pSrc, S->fftLen, S->pTwiddle,
-                             S->twidCoefModifier);
-  }
-
-  if(S->bitReverseFlag == 1u)
-  {
-    /*  Bit Reversal */
-    arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
-  }
-
-}
-
-
-/**    
- * @} end of Radix2_CFFT_CIFFT group    
- */
-
-
-
-/* ----------------------------------------------------------------------    
-** Internal helper function used by the FFTs    
-** ------------------------------------------------------------------- */
-
-/*    
- * @brief  Core function for the floating-point CFFT butterfly process.   
- * @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.   
- * @param[in]      fftLen           length of the FFT.   
- * @param[in]      *pCoef           points to the twiddle coefficient buffer.   
- * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
- * @return none.   
- */
-
-void arm_radix2_butterfly_f32(
-  float32_t * pSrc,
-  uint32_t fftLen,
-  float32_t * pCoef,
-  uint16_t twidCoefModifier)
-{
-
-  int i, j, k, l;
-  int n1, n2, ia;
-  float32_t xt, yt, cosVal, sinVal;
-
-#ifndef ARM_MATH_CM0
-
-  /*  Initializations for the first stage */
-  n2 = fftLen;
-
-  n1 = n2;
-  n2 = n2 >> 1;
-  ia = 0;
-
-  // loop for groups 
-  for (i = 0; i < n2; i++)
-  {
-    cosVal = pCoef[ia * 2];
-    sinVal = pCoef[(ia * 2) + 1];
-
-    /*  Twiddle coefficients index modifier */
-    ia = ia + twidCoefModifier;
-
-    /*  index calculation for the input as, */
-    /*  pSrc[i + 0], pSrc[i + fftLen/1] */
-    l = i + n2;
-
-    /*  Butterfly implementation */
-    xt = pSrc[2 * i] - pSrc[2 * l];
-    pSrc[2 * i] = pSrc[2 * i] + pSrc[2 * l];
-
-    yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-    pSrc[2 * i + 1] = pSrc[2 * l + 1] + pSrc[2 * i + 1];
-
-    pSrc[2u * l] = xt * cosVal + yt * sinVal;
-
-    pSrc[2u * l + 1u] = yt * cosVal - xt * sinVal;
-
-  }                             // groups loop end 
-
-  twidCoefModifier = twidCoefModifier << 1u;
-
-  // loop for stage 
-  for (k = fftLen / 2; k > 2; k = k >> 1)
-  {
-    n1 = n2;
-    n2 = n2 >> 1;
-    ia = 0;
-
-    // loop for groups 
-    for (j = 0; j < n2; j++)
-    {
-      cosVal = pCoef[ia * 2];
-      sinVal = pCoef[(ia * 2) + 1];
-      ia = ia + twidCoefModifier;
-
-      // loop for butterfly 
-      for (i = j; i < fftLen; i += n1)
-      {
-        l = i + n2;
-        xt = pSrc[2 * i] - pSrc[2 * l];
-        pSrc[2 * i] = pSrc[2 * i] + pSrc[2 * l];
-
-        yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-        pSrc[2 * i + 1] = pSrc[2 * l + 1] + pSrc[2 * i + 1];
-
-        pSrc[2u * l] = xt * cosVal + yt * sinVal;
-
-        pSrc[2u * l + 1u] = yt * cosVal - xt * sinVal;
-
-      }                         // butterfly loop end 
-
-    }                           // groups loop end 
-
-    twidCoefModifier = twidCoefModifier << 1u;
-  }                             // stages loop end 
-
-  n1 = n2;
-  n2 = n2 >> 1;
-  ia = 0;
-
-  cosVal = pCoef[ia * 2];
-  sinVal = pCoef[(ia * 2) + 1];
-  ia = ia + twidCoefModifier;
-
-  // loop for butterfly 
-  for (i = 0; i < fftLen; i += n1)
-  {
-    l = i + n2;
-    xt = pSrc[2 * i] - pSrc[2 * l];
-    pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
-
-    yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-    pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
-
-    pSrc[2u * l] = xt;
-
-    pSrc[2u * l + 1u] = yt;
-
-  }                             // groups loop end 
-
-#else
-
-  //N = fftLen; 
-  n2 = fftLen;
-
-  // loop for stage 
-  for (k = fftLen; k > 1; k = k >> 1)
-  {
-    n1 = n2;
-    n2 = n2 >> 1;
-    ia = 0;
-
-    // loop for groups 
-    for (j = 0; j < n2; j++)
-    {
-      cosVal = pCoef[ia * 2];
-      sinVal = pCoef[(ia * 2) + 1];
-      ia = ia + twidCoefModifier;
-
-      // loop for butterfly 
-      for (i = j; i < fftLen; i += n1)
-      {
-        l = i + n2;
-        xt = pSrc[2 * i] - pSrc[2 * l];
-        pSrc[2 * i] = pSrc[2 * i] + pSrc[2 * l];
-
-        yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-        pSrc[2 * i + 1] = pSrc[2 * l + 1] + pSrc[2 * i + 1];
-
-        pSrc[2 * l] = (cosVal * xt + sinVal * yt);      // >> 15; 
-        pSrc[2 * l + 1] = (cosVal * yt - sinVal * xt);  // >> 15; 
-
-      }
-    }
-    twidCoefModifier = twidCoefModifier << 1u;
-  }
-
-#endif //    #ifndef ARM_MATH_CM0
-
-}
-
-
-void arm_radix2_butterfly_inverse_f32(
-  float32_t * pSrc,
-  uint32_t fftLen,
-  float32_t * pCoef,
-  uint16_t twidCoefModifier,
-  float32_t onebyfftLen)
-{
-
-  int i, j, k, l;
-  int n1, n2, ia;
-  float32_t xt, yt, cosVal, sinVal;
-
-#ifndef ARM_MATH_CM0
-
-  //N = fftLen; 
-  n2 = fftLen;
-
-  n1 = n2;
-  n2 = n2 >> 1;
-  ia = 0;
-
-  // loop for groups 
-  for (i = 0; i < n2; i++)
-  {
-    cosVal = pCoef[ia * 2];
-    sinVal = pCoef[(ia * 2) + 1];
-    ia = ia + twidCoefModifier;
-
-    l = i + n2;
-    xt = pSrc[2 * i] - pSrc[2 * l];
-    pSrc[2 * i] = pSrc[2 * i] + pSrc[2 * l];
-
-    yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-    pSrc[2 * i + 1] = pSrc[2 * l + 1] + pSrc[2 * i + 1];
-
-    pSrc[2u * l] = xt * cosVal - yt * sinVal;
-
-    pSrc[2u * l + 1u] = yt * cosVal + xt * sinVal;
-
-  }                             // groups loop end 
-
-  twidCoefModifier = twidCoefModifier << 1u;
-
-  // loop for stage 
-  for (k = fftLen / 2; k > 2; k = k >> 1)
-  {
-    n1 = n2;
-    n2 = n2 >> 1;
-    ia = 0;
-
-    // loop for groups 
-    for (j = 0; j < n2; j++)
-    {
-      cosVal = pCoef[ia * 2];
-      sinVal = pCoef[(ia * 2) + 1];
-      ia = ia + twidCoefModifier;
-
-      // loop for butterfly 
-      for (i = j; i < fftLen; i += n1)
-      {
-        l = i + n2;
-        xt = pSrc[2 * i] - pSrc[2 * l];
-        pSrc[2 * i] = pSrc[2 * i] + pSrc[2 * l];
-
-        yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-        pSrc[2 * i + 1] = pSrc[2 * l + 1] + pSrc[2 * i + 1];
-
-        pSrc[2u * l] = xt * cosVal - yt * sinVal;
-
-        pSrc[2u * l + 1u] = yt * cosVal + xt * sinVal;
-
-      }                         // butterfly loop end 
-
-    }                           // groups loop end 
-
-    twidCoefModifier = twidCoefModifier << 1u;
-  }                             // stages loop end 
-
-  n1 = n2;
-  n2 = n2 >> 1;
-  ia = 0;
-
-  cosVal = pCoef[ia * 2];
-  sinVal = pCoef[(ia * 2) + 1];
-  ia = ia + twidCoefModifier;
-
-  // loop for butterfly 
-  for (i = 0; i < fftLen; i += n1)
-  {
-    l = i + n2;
-    xt = pSrc[2 * i] - pSrc[2 * l];
-    pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) * onebyfftLen;
-
-    yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-    pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) * onebyfftLen;
-
-    pSrc[2u * l] = xt * onebyfftLen;
-
-    pSrc[2u * l + 1u] = yt * onebyfftLen;
-
-  }                             // butterfly loop end 
-
-#else
-
-  //N = fftLen; 
-  n2 = fftLen;
-
-  // loop for stage 
-  for (k = fftLen; k > 2; k = k >> 1)
-  {
-    n1 = n2;
-    n2 = n2 >> 1;
-    ia = 0;
-
-    // loop for groups 
-    for (j = 0; j < n2; j++)
-    {
-      cosVal = pCoef[ia * 2];
-      sinVal = pCoef[(ia * 2) + 1];
-      ia = ia + twidCoefModifier;
-
-      // loop for butterfly 
-      for (i = j; i < fftLen; i += n1)
-      {
-        l = i + n2;
-        xt = pSrc[2 * i] - pSrc[2 * l];
-        pSrc[2 * i] = pSrc[2 * i] + pSrc[2 * l];
-
-        yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-        pSrc[2 * i + 1] = pSrc[2 * l + 1] + pSrc[2 * i + 1];
-
-        pSrc[2u * l] = xt * cosVal - yt * sinVal;
-
-        pSrc[2u * l + 1u] = yt * cosVal + xt * sinVal;
-
-      }                         // butterfly loop end 
-
-    }                           // groups loop end 
-
-    twidCoefModifier = twidCoefModifier << 1u;
-  }                             // stages loop end 
-
-  n1 = n2;
-  n2 = n2 >> 1;
-  ia = 0;
-
-  cosVal = pCoef[ia * 2];
-  sinVal = pCoef[(ia * 2) + 1];
-  ia = ia + twidCoefModifier;
-
-  // loop for butterfly 
-  for (i = 0; i < fftLen; i += n1)
-  {
-    l = i + n2;
-    xt = pSrc[2 * i] - pSrc[2 * l];
-    pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) * onebyfftLen;
-
-    yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-    pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) * onebyfftLen;
-
-    pSrc[2u * l] = xt * onebyfftLen;
-
-    pSrc[2u * l + 1u] = yt * onebyfftLen;
-
-  }                             // butterfly loop end 
-
-#endif //      #ifndef ARM_MATH_CM0
-
-}
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_f32.c
deleted file mode 100644
index 76c781fc32..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_f32.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/* ----------------------------------------------------------------------   
-* Copyright (C) 2010 ARM Limited. All rights reserved.   
-*   
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*   
-* Project: 	    CMSIS DSP Library   
-* Title:	    arm_cfft_radix4_init_f32.c   
-*   
-* Description:	Radix-4 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function   
-*   
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.3 2010/11/29  
-*    Re-organized the CMSIS folders and updated documentation.   
-*    
-* Version 1.0.2 2010/11/11   
-*    Documentation updated.    
-*   
-* Version 1.0.1 2010/10/05    
-*    Production release and review comments incorporated.   
-*   
-* Version 1.0.0 2010/09/20    
-*    Production release and review comments incorporated.   
-*   
-* Version 0.0.5  2010/04/26    
-* 	 incorporated review comments and updated with latest CMSIS layer   
-*   
-* Version 0.0.3  2010/03/10    
-*    Initial version   
-* -------------------------------------------------------------------- */
-
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**   
- * @ingroup groupTransforms   
- */
-
-/**   
- * @addtogroup Radix2_CFFT_CIFFT   
- * @{   
- */
-
-/**   
-* @brief  Initialization function for the floating-point CFFT/CIFFT.  
-* @param[in,out] *S             points to an instance of the floating-point CFFT/CIFFT structure.  
-* @param[in]     fftLen         length of the FFT.  
-* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.  
-* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
-* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.  
-*   
-* \par Description:  
-* \par   
-* The parameter ifftFlag controls whether a forward or inverse transform is computed.   
-* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated  
-* \par   
-* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.   
-* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
-* \par   
-* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.   
-* \par   
-* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.   
-*/
-arm_status arm_cfft_radix2_init_f32(
-  arm_cfft_radix2_instance_f32 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag)
-{
-  /*  Initialise the default arm status */
-  arm_status status = ARM_MATH_SUCCESS;
-
-  /*  Initialise the FFT length */
-  S->fftLen = fftLen;
-
-  /*  Initialise the Twiddle coefficient pointer */
-  S->pTwiddle = (float32_t *) twiddleCoef;
-
-  /*  Initialise the Flag for selection of CFFT or CIFFT */
-  S->ifftFlag = ifftFlag;
-
-  /*  Initialise the Flag for calculation Bit reversal or not */
-  S->bitReverseFlag = bitReverseFlag;
-
-  /*  Initializations of structure parameters depending on the FFT length */
-  switch (S->fftLen)
-  {
-
-  case 4096u:
-    /*  Initializations of structure parameters for 4096 point FFT */
-
-    /*  Initialise the twiddle coef modifier value */
-    S->twidCoefModifier = 1u;
-    /*  Initialise the bit reversal table modifier */
-    S->bitRevFactor = 1u;
-    /*  Initialise the bit reversal table pointer */
-    S->pBitRevTable = (uint16_t *) armBitRevTable;
-    /*  Initialise the 1/fftLen Value */
-    S->onebyfftLen = 0.000244140625;
-    break;
-
-  case 2048u:
-    /*  Initializations of structure parameters for 2048 point FFT */
-
-    /*  Initialise the twiddle coef modifier value */
-    S->twidCoefModifier = 2u;
-    /*  Initialise the bit reversal table modifier */
-    S->bitRevFactor = 2u;
-    /*  Initialise the bit reversal table pointer */
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[1];
-    /*  Initialise the 1/fftLen Value */
-    S->onebyfftLen = 0.00048828125;
-    break;
-
-  case 1024u:
-    /*  Initializations of structure parameters for 1024 point FFT */
-
-    /*  Initialise the twiddle coef modifier value */
-    S->twidCoefModifier = 4u;
-    /*  Initialise the bit reversal table modifier */
-    S->bitRevFactor = 4u;
-    /*  Initialise the bit reversal table pointer */
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
-    /*  Initialise the 1/fftLen Value */
-    S->onebyfftLen = 0.0009765625f;
-    break;
-
-  case 512u:
-    /*  Initializations of structure parameters for 512 point FFT */
-
-    /*  Initialise the twiddle coef modifier value */
-    S->twidCoefModifier = 8u;
-    /*  Initialise the bit reversal table modifier */
-    S->bitRevFactor = 8u;
-    /*  Initialise the bit reversal table pointer */
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[7];
-    /*  Initialise the 1/fftLen Value */
-    S->onebyfftLen = 0.001953125;
-    break;
-
-  case 256u:
-    /*  Initializations of structure parameters for 256 point FFT */
-    S->twidCoefModifier = 16u;
-    S->bitRevFactor = 16u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
-    S->onebyfftLen = 0.00390625f;
-    break;
-
-  case 128u:
-    /*  Initializations of structure parameters for 128 point FFT */
-    S->twidCoefModifier = 32u;
-    S->bitRevFactor = 32u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[31];
-    S->onebyfftLen = 0.0078125;
-    break;
-
-  case 64u:
-    /*  Initializations of structure parameters for 64 point FFT */
-    S->twidCoefModifier = 64u;
-    S->bitRevFactor = 64u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
-    S->onebyfftLen = 0.015625f;
-    break;
-
-  case 32u:
-    /*  Initializations of structure parameters for 64 point FFT */
-    S->twidCoefModifier = 128u;
-    S->bitRevFactor = 128u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[127];
-    S->onebyfftLen = 0.03125;
-    break;
-
-  case 16u:
-    /*  Initializations of structure parameters for 16 point FFT */
-    S->twidCoefModifier = 256u;
-    S->bitRevFactor = 256u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
-    S->onebyfftLen = 0.0625f;
-    break;
-
-
-  default:
-    /*  Reporting argument error if fftSize is not valid value */
-    status = ARM_MATH_ARGUMENT_ERROR;
-    break;
-  }
-
-  return (status);
-}
-
-/**   
- * @} end of Radix2_CFFT_CIFFT group   
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q15.c
deleted file mode 100644
index b6ba22c186..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q15.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_cfft_radix2_init_q15.c    
-*    
-* Description:	Radix-2 Decimation in Frequency Q15 FFT & IFFT initialization function    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-* 	 incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**    
- * @ingroup groupTransforms    
- */
-
-
-/**    
- * @addtogroup Radix2_CFFT_CIFFT    
- * @{    
- */
-
-/**   
-* @brief Initialization function for the Q15 CFFT/CIFFT.   
-* @param[in,out] *S             points to an instance of the Q15 CFFT/CIFFT structure.   
-* @param[in]     fftLen         length of the FFT.   
-* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.  
-* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
-* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.  
-*   
-* \par Description:  
-* \par   
-* The parameter ifftFlag controls whether a forward or inverse transform is computed.   
-* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated  
-* \par   
-* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.   
-* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
-* \par   
-* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.   
-* \par   
-* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.   
-*/
-
-arm_status arm_cfft_radix2_init_q15(
-  arm_cfft_radix2_instance_q15 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag)
-{
-  /*  Initialise the default arm status */
-  arm_status status = ARM_MATH_SUCCESS;
-
-  /*  Initialise the FFT length */
-  S->fftLen = fftLen;
-
-  /*  Initialise the Twiddle coefficient pointer */
-  S->pTwiddle = (q15_t *) twiddleCoefQ15;
-  /*  Initialise the Flag for selection of CFFT or CIFFT */
-  S->ifftFlag = ifftFlag;
-  /*  Initialise the Flag for calculation Bit reversal or not */
-  S->bitReverseFlag = bitReverseFlag;
-
-  /*  Initializations of structure parameters depending on the FFT length */
-  switch (S->fftLen)
-  {
-  case 4096u:
-    /*  Initializations of structure parameters for 4096 point FFT */
-
-    /*  Initialise the twiddle coef modifier value */
-    S->twidCoefModifier = 1u;
-    /*  Initialise the bit reversal table modifier */
-    S->bitRevFactor = 1u;
-    /*  Initialise the bit reversal table pointer */
-    S->pBitRevTable = (uint16_t *) armBitRevTable;
-
-    break;
-
-  case 2048u:
-    /*  Initializations of structure parameters for 2048 point FFT */
-
-    /*  Initialise the twiddle coef modifier value */
-    S->twidCoefModifier = 2u;
-    /*  Initialise the bit reversal table modifier */
-    S->bitRevFactor = 2u;
-    /*  Initialise the bit reversal table pointer */
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[1];
-
-    break;
-
-  case 1024u:
-    /*  Initializations of structure parameters for 1024 point FFT */
-    S->twidCoefModifier = 4u;
-    S->bitRevFactor = 4u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
-
-    break;
-
-  case 512u:
-    /*  Initializations of structure parameters for 512 point FFT */
-    S->twidCoefModifier = 8u;
-    S->bitRevFactor = 8u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[7];
-
-    break;
-
-  case 256u:
-    /*  Initializations of structure parameters for 256 point FFT */
-    S->twidCoefModifier = 16u;
-    S->bitRevFactor = 16u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
-
-    break;
-
-  case 128u:
-    /*  Initializations of structure parameters for 128 point FFT */
-    S->twidCoefModifier = 32u;
-    S->bitRevFactor = 32u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[31];
-
-    break;
-
-  case 64u:
-    /*  Initializations of structure parameters for 64 point FFT */
-    S->twidCoefModifier = 64u;
-    S->bitRevFactor = 64u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
-
-    break;
-
-  case 32u:
-    /*  Initializations of structure parameters for 32 point FFT */
-    S->twidCoefModifier = 128u;
-    S->bitRevFactor = 128u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[127];
-
-    break;
-
-  case 16u:
-    /*  Initializations of structure parameters for 16 point FFT */
-    S->twidCoefModifier = 256u;
-    S->bitRevFactor = 256u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
-
-    break;
-
-  default:
-    /*  Reporting argument error if fftSize is not valid value */
-    status = ARM_MATH_ARGUMENT_ERROR;
-    break;
-  }
-
-  return (status);
-}
-
-/**    
- * @} end of Radix2_CFFT_CIFFT group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q31.c
deleted file mode 100644
index 94eeeb00ae..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q31.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/* ----------------------------------------------------------------------   
-* Copyright (C) 2010 ARM Limited. All rights reserved.   
-*   
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*   
-* Project: 	    CMSIS DSP Library   
-* Title:	    arm_cfft_radix2_init_q31.c   
-*   
-* Description:	Radix-2 Decimation in Frequency Fixed-point CFFT & CIFFT Initialization function   
-*   
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* -------------------------------------------------------------------- */
-
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**   
- * @ingroup groupTransforms   
- */
-
-/**   
- * @addtogroup Radix2_CFFT_CIFFT   
- * @{   
- */
-
-
-/**    
-*    
-* @brief  Initialization function for the Q31 CFFT/CIFFT.   
-* @param[in,out] *S             points to an instance of the Q31 CFFT/CIFFT structure.   
-* @param[in]     fftLen         length of the FFT.  
-* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.  
-* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
-* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.  
-*   
-* \par Description:  
-* \par   
-* The parameter ifftFlag controls whether a forward or inverse transform is computed.   
-* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated  
-* \par   
-* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.   
-* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
-* \par   
-* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.   
-* \par   
-* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.   
-*/
-
-arm_status arm_cfft_radix2_init_q31(
-  arm_cfft_radix2_instance_q31 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag)
-{
-  /*  Initialise the default arm status */
-  arm_status status = ARM_MATH_SUCCESS;
-
-  /*  Initialise the FFT length */
-  S->fftLen = fftLen;
-
-  /*  Initialise the Twiddle coefficient pointer */
-  S->pTwiddle = (q31_t *) twiddleCoefQ31;
-  /*  Initialise the Flag for selection of CFFT or CIFFT */
-  S->ifftFlag = ifftFlag;
-  /*  Initialise the Flag for calculation Bit reversal or not */
-  S->bitReverseFlag = bitReverseFlag;
-
-  /*  Initializations of Instance structure depending on the FFT length */
-  switch (S->fftLen)
-  {
-    /*  Initializations of structure parameters for 4096 point FFT */
-  case 4096u:
-    /*  Initialise the twiddle coef modifier value */
-    S->twidCoefModifier = 1u;
-    /*  Initialise the bit reversal table modifier */
-    S->bitRevFactor = 1u;
-    /*  Initialise the bit reversal table pointer */
-    S->pBitRevTable = (uint16_t *) armBitRevTable;
-    break;
-
-    /*  Initializations of structure parameters for 2048 point FFT */
-  case 2048u:
-    /*  Initialise the twiddle coef modifier value */
-    S->twidCoefModifier = 2u;
-    /*  Initialise the bit reversal table modifier */
-    S->bitRevFactor = 2u;
-    /*  Initialise the bit reversal table pointer */
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[1];
-    break;
-
-    /*  Initializations of structure parameters for 1024 point FFT */
-  case 1024u:
-    /*  Initialise the twiddle coef modifier value */
-    S->twidCoefModifier = 4u;
-    /*  Initialise the bit reversal table modifier */
-    S->bitRevFactor = 4u;
-    /*  Initialise the bit reversal table pointer */
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
-    break;
-
-    /*  Initializations of structure parameters for 512 point FFT */
-  case 512u:
-    /*  Initialise the twiddle coef modifier value */
-    S->twidCoefModifier = 8u;
-    /*  Initialise the bit reversal table modifier */
-    S->bitRevFactor = 8u;
-    /*  Initialise the bit reversal table pointer */
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[7];
-    break;
-
-  case 256u:
-    /*  Initializations of structure parameters for 256 point FFT */
-    S->twidCoefModifier = 16u;
-    S->bitRevFactor = 16u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
-    break;
-
-  case 128u:
-    /*  Initializations of structure parameters for 128 point FFT */
-    S->twidCoefModifier = 32u;
-    S->bitRevFactor = 32u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[31];
-    break;
-
-  case 64u:
-    /*  Initializations of structure parameters for 64 point FFT */
-    S->twidCoefModifier = 64u;
-    S->bitRevFactor = 64u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
-    break;
-
-  case 32u:
-    /*  Initializations of structure parameters for 32 point FFT */
-    S->twidCoefModifier = 128u;
-    S->bitRevFactor = 128u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[127];
-    break;
-
-  case 16u:
-    /*  Initializations of structure parameters for 16 point FFT */
-    S->twidCoefModifier = 256u;
-    S->bitRevFactor = 256u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
-    break;
-
-
-  default:
-    /*  Reporting argument error if fftSize is not valid value */
-    status = ARM_MATH_ARGUMENT_ERROR;
-    break;
-  }
-
-  return (status);
-}
-
-/**   
- * @} end of Radix2_CFFT_CIFFT group   
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q15.c
deleted file mode 100644
index c385091c7a..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q15.c
+++ /dev/null
@@ -1,712 +0,0 @@
-/* ----------------------------------------------------------------------   
-* Copyright (C) 2010 ARM Limited. All rights reserved.   
-*   
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*   
-* Project: 	    CMSIS DSP Library   
-* Title:	    arm_cfft_radix2_q15.c   
-*   
-* Description:	Radix-2 Decimation in Frequency CFFT & CIFFT Fixed point processing function   
-*   
-*   
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 0.0.3  2010/03/10    
-*    Initial version   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**   
- * @ingroup groupTransforms   
- */
-
-/**   
- * @defgroup Radix2_CFFT_CIFFT Radix-2 Complex FFT Functions   
- *   
- * \par   
- * Complex Fast Fourier Transform(CFFT) and Complex Inverse Fast Fourier Transform(CIFFT) is an efficient algorithm to compute Discrete Fourier Transform(DFT) and Inverse Discrete Fourier Transform(IDFT).   
- * Computational complexity of CFFT reduces drastically when compared to DFT.    
- */
-
-
-/**   
- * @addtogroup Radix2_CFFT_CIFFT   
- * @{   
- */
-
-/**   
- * @details   
- * @brief Processing function for the fixed-point CFFT/CIFFT.  
- * @param[in]      *S    points to an instance of the fixed-point CFFT/CIFFT structure.  
- * @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.  
- * @return none.  
- */
-
-void arm_cfft_radix2_q15(
-  const arm_cfft_radix2_instance_q15 * S,
-  q15_t * pSrc)
-{
-
-  if(S->ifftFlag == 1u)
-  {
-    arm_radix2_butterfly_inverse_q15(pSrc, S->fftLen,
-                                     S->pTwiddle, S->twidCoefModifier);
-  }
-  else
-  {
-    arm_radix2_butterfly_q15(pSrc, S->fftLen,
-                             S->pTwiddle, S->twidCoefModifier);
-  }
-
-  arm_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
-}
-
-/**   
- * @} end of Radix2_CFFT_CIFFT group   
- */
-
-void arm_radix2_butterfly_q15(
-  q15_t * pSrc,
-  uint32_t fftLen,
-  q15_t * pCoef,
-  uint16_t twidCoefModifier)
-{
-#ifndef ARM_MATH_CM0
-
-  int i, j, k, l;
-  int n1, n2, ia;
-  q15_t in;
-  q31_t T, S, R;
-  q31_t coeff, out1, out2;
-
-  //N = fftLen; 
-  n2 = fftLen;
-
-  n1 = n2;
-  n2 = n2 >> 1;
-  ia = 0;
-
-  // loop for groups 
-  for (i = 0; i < n2; i++)
-  {
-    coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
-
-    ia = ia + twidCoefModifier;
-
-    l = i + n2;
-
-    T = _SIMD32_OFFSET(pSrc + (2 * i));
-    in = ((int16_t) (T & 0xFFFF)) >> 2;
-    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
-
-    S = _SIMD32_OFFSET(pSrc + (2 * l));
-    in = ((int16_t) (S & 0xFFFF)) >> 2;
-    S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);
-
-    R = __QSUB16(T, S);
-
-    _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    out1 = __SMUAD(coeff, R) >> 16;
-    out2 = __SMUSDX(coeff, R);
-
-#else
-
-    out1 = __SMUSDX(R, coeff) >> 16u;
-    out2 = __SMUAD(coeff, R);
-
-#endif //     #ifndef ARM_MATH_BIG_ENDIAN
-
-    _SIMD32_OFFSET(pSrc + (2u * l)) =
-      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
-    coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
-
-    ia = ia + twidCoefModifier;
-
-    // loop for butterfly 
-    i++;
-    l++;
-
-    T = _SIMD32_OFFSET(pSrc + (2 * i));
-    in = ((int16_t) (T & 0xFFFF)) >> 2;
-    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
-
-    S = _SIMD32_OFFSET(pSrc + (2 * l));
-    in = ((int16_t) (S & 0xFFFF)) >> 2;
-    S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);
-
-    R = __QSUB16(T, S);
-
-    _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    out1 = __SMUAD(coeff, R) >> 16;
-    out2 = __SMUSDX(coeff, R);
-
-#else
-
-    out1 = __SMUSDX(R, coeff) >> 16u;
-    out2 = __SMUAD(coeff, R);
-
-#endif //     #ifndef ARM_MATH_BIG_ENDIAN
-
-    _SIMD32_OFFSET(pSrc + (2u * l)) =
-      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
-  }                             // groups loop end 
-
-  twidCoefModifier = twidCoefModifier << 1u;
-
-  // loop for stage 
-  for (k = fftLen / 2; k > 2; k = k >> 1)
-  {
-    n1 = n2;
-    n2 = n2 >> 1;
-    ia = 0;
-
-    // loop for groups 
-    for (j = 0; j < n2; j++)
-    {
-      coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
-
-      ia = ia + twidCoefModifier;
-
-      // loop for butterfly 
-      for (i = j; i < fftLen; i += n1)
-      {
-        l = i + n2;
-
-        T = _SIMD32_OFFSET(pSrc + (2 * i));
-
-        S = _SIMD32_OFFSET(pSrc + (2 * l));
-
-        R = __QSUB16(T, S);
-
-        _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        out1 = __SMUAD(coeff, R) >> 16;
-        out2 = __SMUSDX(coeff, R);
-
-#else
-
-        out1 = __SMUSDX(R, coeff) >> 16u;
-        out2 = __SMUAD(coeff, R);
-
-#endif //     #ifndef ARM_MATH_BIG_ENDIAN
-
-        _SIMD32_OFFSET(pSrc + (2u * l)) =
-          (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
-        i += n1;
-
-        l = i + n2;
-
-        T = _SIMD32_OFFSET(pSrc + (2 * i));
-
-        S = _SIMD32_OFFSET(pSrc + (2 * l));
-
-        R = __QSUB16(T, S);
-
-        _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        out1 = __SMUAD(coeff, R) >> 16;
-        out2 = __SMUSDX(coeff, R);
-
-#else
-
-        out1 = __SMUSDX(R, coeff) >> 16u;
-        out2 = __SMUAD(coeff, R);
-
-#endif //     #ifndef ARM_MATH_BIG_ENDIAN
-
-        _SIMD32_OFFSET(pSrc + (2u * l)) =
-          (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
-      }                         // butterfly loop end 
-
-    }                           // groups loop end 
-
-    twidCoefModifier = twidCoefModifier << 1u;
-  }                             // stages loop end 
-
-  n1 = n2;
-  n2 = n2 >> 1;
-  ia = 0;
-
-  coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
-
-  ia = ia + twidCoefModifier;
-
-  // loop for butterfly 
-  for (i = 0; i < fftLen; i += n1)
-  {
-    l = i + n2;
-
-    T = _SIMD32_OFFSET(pSrc + (2 * i));
-
-    S = _SIMD32_OFFSET(pSrc + (2 * l));
-
-    R = __QSUB16(T, S);
-
-    _SIMD32_OFFSET(pSrc + (2 * i)) = __QADD16(T, S);
-
-    _SIMD32_OFFSET(pSrc + (2u * l)) = R;
-
-    i += n1;
-    l = i + n2;
-
-    T = _SIMD32_OFFSET(pSrc + (2 * i));
-
-    S = _SIMD32_OFFSET(pSrc + (2 * l));
-
-    R = __QSUB16(T, S);
-
-    _SIMD32_OFFSET(pSrc + (2 * i)) = __QADD16(T, S);
-
-    _SIMD32_OFFSET(pSrc + (2u * l)) = R;
-
-  }                             // groups loop end 
-
-
-#else
-
-  int i, j, k, l;
-  int n1, n2, ia;
-  q15_t xt, yt, cosVal, sinVal;
-
-
-  //N = fftLen; 
-  n2 = fftLen;
-
-  n1 = n2;
-  n2 = n2 >> 1;
-  ia = 0;
-
-  // loop for groups 
-  for (j = 0; j < n2; j++)
-  {
-    cosVal = pCoef[ia * 2];
-    sinVal = pCoef[(ia * 2) + 1];
-    ia = ia + twidCoefModifier;
-
-    // loop for butterfly 
-    for (i = j; i < fftLen; i += n1)
-    {
-      l = i + n2;
-      xt = (pSrc[2 * i] >> 2u) - (pSrc[2 * l] >> 2u);
-      pSrc[2 * i] = ((pSrc[2 * i] >> 2u) + (pSrc[2 * l] >> 2u)) >> 1u;
-
-      yt = (pSrc[2 * i + 1] >> 2u) - (pSrc[2 * l + 1] >> 2u);
-      pSrc[2 * i + 1] =
-        ((pSrc[2 * l + 1] >> 2u) + (pSrc[2 * i + 1] >> 2u)) >> 1u;
-
-      pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) +
-                      ((int16_t) (((q31_t) yt * sinVal) >> 16)));
-
-      pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) -
-                           ((int16_t) (((q31_t) xt * sinVal) >> 16)));
-
-    }                           // butterfly loop end 
-
-  }                             // groups loop end 
-
-  twidCoefModifier = twidCoefModifier << 1u;
-
-  // loop for stage 
-  for (k = fftLen / 2; k > 2; k = k >> 1)
-  {
-    n1 = n2;
-    n2 = n2 >> 1;
-    ia = 0;
-
-    // loop for groups 
-    for (j = 0; j < n2; j++)
-    {
-      cosVal = pCoef[ia * 2];
-      sinVal = pCoef[(ia * 2) + 1];
-      ia = ia + twidCoefModifier;
-
-      // loop for butterfly 
-      for (i = j; i < fftLen; i += n1)
-      {
-        l = i + n2;
-        xt = pSrc[2 * i] - pSrc[2 * l];
-        pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
-
-        yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-        pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
-
-        pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) +
-                        ((int16_t) (((q31_t) yt * sinVal) >> 16)));
-
-        pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) -
-                             ((int16_t) (((q31_t) xt * sinVal) >> 16)));
-
-      }                         // butterfly loop end 
-
-    }                           // groups loop end 
-
-    twidCoefModifier = twidCoefModifier << 1u;
-  }                             // stages loop end 
-
-  n1 = n2;
-  n2 = n2 >> 1;
-  ia = 0;
-
-  // loop for groups 
-  for (j = 0; j < n2; j++)
-  {
-    cosVal = pCoef[ia * 2];
-    sinVal = pCoef[(ia * 2) + 1];
-
-    ia = ia + twidCoefModifier;
-
-    // loop for butterfly 
-    for (i = j; i < fftLen; i += n1)
-    {
-      l = i + n2;
-      xt = pSrc[2 * i] - pSrc[2 * l];
-      pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
-
-      yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-      pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
-
-      pSrc[2u * l] = xt;
-
-      pSrc[2u * l + 1u] = yt;
-
-    }                           // butterfly loop end 
-
-  }                             // groups loop end 
-
-  twidCoefModifier = twidCoefModifier << 1u;
-
-#endif //             #ifndef ARM_MATH_CM0
-
-}
-
-
-void arm_radix2_butterfly_inverse_q15(
-  q15_t * pSrc,
-  uint32_t fftLen,
-  q15_t * pCoef,
-  uint16_t twidCoefModifier)
-{
-#ifndef ARM_MATH_CM0
-
-  int i, j, k, l;
-  int n1, n2, ia;
-  q15_t in;
-  q31_t T, S, R;
-  q31_t coeff, out1, out2;
-
-  //N = fftLen; 
-  n2 = fftLen;
-
-  n1 = n2;
-  n2 = n2 >> 1;
-  ia = 0;
-
-  // loop for groups 
-  for (i = 0; i < n2; i++)
-  {
-    coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
-
-    ia = ia + twidCoefModifier;
-
-    l = i + n2;
-
-    T = _SIMD32_OFFSET(pSrc + (2 * i));
-    in = ((int16_t) (T & 0xFFFF)) >> 2;
-    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
-
-    S = _SIMD32_OFFSET(pSrc + (2 * l));
-    in = ((int16_t) (S & 0xFFFF)) >> 2;
-    S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);
-
-    R = __QSUB16(T, S);
-
-    _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    out1 = __SMUSD(coeff, R) >> 16;
-    out2 = __SMUADX(coeff, R);
-#else
-
-    out1 = __SMUADX(R, coeff) >> 16u;
-    out2 = __SMUSD(__QSUB(0, coeff), R);
-
-#endif //     #ifndef ARM_MATH_BIG_ENDIAN
-
-    _SIMD32_OFFSET(pSrc + (2u * l)) =
-      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
-    coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
-
-    ia = ia + twidCoefModifier;
-
-    // loop for butterfly 
-    i++;
-    l++;
-
-    T = _SIMD32_OFFSET(pSrc + (2 * i));
-    in = ((int16_t) (T & 0xFFFF)) >> 2;
-    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
-
-    S = _SIMD32_OFFSET(pSrc + (2 * l));
-    in = ((int16_t) (S & 0xFFFF)) >> 2;
-    S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);
-
-    R = __QSUB16(T, S);
-
-    _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    out1 = __SMUSD(coeff, R) >> 16;
-    out2 = __SMUADX(coeff, R);
-#else
-
-    out1 = __SMUADX(R, coeff) >> 16u;
-    out2 = __SMUSD(__QSUB(0, coeff), R);
-
-#endif //     #ifndef ARM_MATH_BIG_ENDIAN
-
-    _SIMD32_OFFSET(pSrc + (2u * l)) =
-      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
-  }                             // groups loop end 
-
-  twidCoefModifier = twidCoefModifier << 1u;
-
-  // loop for stage 
-  for (k = fftLen / 2; k > 2; k = k >> 1)
-  {
-    n1 = n2;
-    n2 = n2 >> 1;
-    ia = 0;
-
-    // loop for groups 
-    for (j = 0; j < n2; j++)
-    {
-      coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
-
-      ia = ia + twidCoefModifier;
-
-      // loop for butterfly 
-      for (i = j; i < fftLen; i += n1)
-      {
-        l = i + n2;
-
-        T = _SIMD32_OFFSET(pSrc + (2 * i));
-
-        S = _SIMD32_OFFSET(pSrc + (2 * l));
-
-        R = __QSUB16(T, S);
-
-        _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        out1 = __SMUSD(coeff, R) >> 16;
-        out2 = __SMUADX(coeff, R);
-
-#else
-
-        out1 = __SMUADX(R, coeff) >> 16u;
-        out2 = __SMUSD(__QSUB(0, coeff), R);
-
-#endif //     #ifndef ARM_MATH_BIG_ENDIAN
-
-        _SIMD32_OFFSET(pSrc + (2u * l)) =
-          (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
-        i += n1;
-
-        l = i + n2;
-
-        T = _SIMD32_OFFSET(pSrc + (2 * i));
-
-        S = _SIMD32_OFFSET(pSrc + (2 * l));
-
-        R = __QSUB16(T, S);
-
-        _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        out1 = __SMUSD(coeff, R) >> 16;
-        out2 = __SMUADX(coeff, R);
-#else
-
-        out1 = __SMUADX(R, coeff) >> 16u;
-        out2 = __SMUSD(__QSUB(0, coeff), R);
-
-#endif //     #ifndef ARM_MATH_BIG_ENDIAN
-
-        _SIMD32_OFFSET(pSrc + (2u * l)) =
-          (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
-      }                         // butterfly loop end 
-
-    }                           // groups loop end 
-
-    twidCoefModifier = twidCoefModifier << 1u;
-  }                             // stages loop end 
-
-  n1 = n2;
-  n2 = n2 >> 1;
-  ia = 0;
-
-  // loop for groups 
-  for (j = 0; j < n2; j++)
-  {
-    coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
-
-    ia = ia + twidCoefModifier;
-
-    // loop for butterfly 
-    for (i = j; i < fftLen; i += n1)
-    {
-      l = i + n2;
-
-      T = _SIMD32_OFFSET(pSrc + (2 * i));
-
-      S = _SIMD32_OFFSET(pSrc + (2 * l));
-
-      R = __QSUB16(T, S);
-
-      _SIMD32_OFFSET(pSrc + (2 * i)) = __QADD16(T, S);
-
-      _SIMD32_OFFSET(pSrc + (2u * l)) = R;
-
-    }                           // butterfly loop end 
-
-  }                             // groups loop end 
-
-  twidCoefModifier = twidCoefModifier << 1u;
-
-#else
-
-
-  int i, j, k, l;
-  int n1, n2, ia;
-  q15_t xt, yt, cosVal, sinVal;
-
-  //N = fftLen; 
-  n2 = fftLen;
-
-  n1 = n2;
-  n2 = n2 >> 1;
-  ia = 0;
-
-  // loop for groups 
-  for (j = 0; j < n2; j++)
-  {
-    cosVal = pCoef[ia * 2];
-    sinVal = pCoef[(ia * 2) + 1];
-    ia = ia + twidCoefModifier;
-
-    // loop for butterfly 
-    for (i = j; i < fftLen; i += n1)
-    {
-      l = i + n2;
-      xt = (pSrc[2 * i] >> 2u) - (pSrc[2 * l] >> 2u);
-      pSrc[2 * i] = ((pSrc[2 * i] >> 2u) + (pSrc[2 * l] >> 2u)) >> 1u;
-
-      yt = (pSrc[2 * i + 1] >> 2u) - (pSrc[2 * l + 1] >> 2u);
-      pSrc[2 * i + 1] =
-        ((pSrc[2 * l + 1] >> 2u) + (pSrc[2 * i + 1] >> 2u)) >> 1u;
-
-      pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) -
-                      ((int16_t) (((q31_t) yt * sinVal) >> 16)));
-
-      pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) +
-                           ((int16_t) (((q31_t) xt * sinVal) >> 16)));
-
-    }                           // butterfly loop end 
-
-  }                             // groups loop end 
-
-  twidCoefModifier = twidCoefModifier << 1u;
-
-  // loop for stage 
-  for (k = fftLen / 2; k > 2; k = k >> 1)
-  {
-    n1 = n2;
-    n2 = n2 >> 1;
-    ia = 0;
-
-    // loop for groups 
-    for (j = 0; j < n2; j++)
-    {
-      cosVal = pCoef[ia * 2];
-      sinVal = pCoef[(ia * 2) + 1];
-      ia = ia + twidCoefModifier;
-
-      // loop for butterfly 
-      for (i = j; i < fftLen; i += n1)
-      {
-        l = i + n2;
-        xt = pSrc[2 * i] - pSrc[2 * l];
-        pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
-
-        yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-        pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
-
-        pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) -
-                        ((int16_t) (((q31_t) yt * sinVal) >> 16)));
-
-        pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) +
-                             ((int16_t) (((q31_t) xt * sinVal) >> 16)));
-
-      }                         // butterfly loop end 
-
-    }                           // groups loop end 
-
-    twidCoefModifier = twidCoefModifier << 1u;
-  }                             // stages loop end 
-
-  n1 = n2;
-  n2 = n2 >> 1;
-  ia = 0;
-
-  cosVal = pCoef[ia * 2];
-  sinVal = pCoef[(ia * 2) + 1];
-
-  ia = ia + twidCoefModifier;
-
-  // loop for butterfly 
-  for (i = 0; i < fftLen; i += n1)
-  {
-    l = i + n2;
-    xt = pSrc[2 * i] - pSrc[2 * l];
-    pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
-
-    yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-    pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
-
-    pSrc[2u * l] = xt;
-
-    pSrc[2u * l + 1u] = yt;
-
-  }                             // groups loop end 
-
-
-#endif //             #ifndef ARM_MATH_CM0
-
-}
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q31.c
deleted file mode 100644
index 5b950c39c6..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q31.c
+++ /dev/null
@@ -1,310 +0,0 @@
-/* ----------------------------------------------------------------------   
-* Copyright (C) 2010 ARM Limited. All rights reserved.   
-*   
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*   
-* Project: 	    CMSIS DSP Library   
-* Title:	    arm_cfft_radix2_q31.c   
-*   
-* Description:	Radix-2 Decimation in Frequency CFFT & CIFFT Fixed point processing function   
-*   
-*   
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 0.0.3  2010/03/10    
-*    Initial version   
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**   
- * @ingroup groupTransforms   
- */
-
-/**   
- * @defgroup Radix2_CFFT_CIFFT Radix-2 Complex FFT Functions   
- *   
- * \par   
- * Complex Fast Fourier Transform(CFFT) and Complex Inverse Fast Fourier Transform(CIFFT) is an efficient algorithm to compute Discrete Fourier Transform(DFT) and Inverse Discrete Fourier Transform(IDFT).   
- * Computational complexity of CFFT reduces drastically when compared to DFT.    
- */
-
-
-/**   
- * @addtogroup Radix2_CFFT_CIFFT   
- * @{   
- */
-
-/**   
- * @details   
- * @brief Processing function for the fixed-point CFFT/CIFFT.  
- * @param[in]      *S    points to an instance of the fixed-point CFFT/CIFFT structure.  
- * @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.  
- * @return none.  
- */
-
-void arm_cfft_radix2_q31(
-  const arm_cfft_radix2_instance_q31 * S,
-  q31_t * pSrc)
-{
-
-  if(S->ifftFlag == 1u)
-  {
-    arm_radix2_butterfly_inverse_q31(pSrc, S->fftLen,
-                                     S->pTwiddle, S->twidCoefModifier);
-  }
-  else
-  {
-    arm_radix2_butterfly_q31(pSrc, S->fftLen,
-                             S->pTwiddle, S->twidCoefModifier);
-  }
-
-  arm_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
-}
-
-/**   
- * @} end of Radix2_CFFT_CIFFT group   
- */
-
-void arm_radix2_butterfly_q31(
-  q31_t * pSrc,
-  uint32_t fftLen,
-  q31_t * pCoef,
-  uint16_t twidCoefModifier)
-{
-
-  int i, j, k, l;
-  int n1, n2, ia;
-  q31_t xt, yt, cosVal, sinVal;
-
-  //N = fftLen; 
-  n2 = fftLen;
-
-  n1 = n2;
-  n2 = n2 >> 1;
-  ia = 0;
-
-  // loop for groups 
-  for (i = 0; i < n2; i++)
-  {
-    cosVal = pCoef[ia * 2];
-    sinVal = pCoef[(ia * 2) + 1];
-    ia = ia + twidCoefModifier;
-
-    l = i + n2;
-    xt = (pSrc[2 * i] >> 2u) - (pSrc[2 * l] >> 2u);
-    pSrc[2 * i] = ((pSrc[2 * i] >> 2u) + (pSrc[2 * l] >> 2u)) >> 1u;
-
-    yt = (pSrc[2 * i + 1] >> 2u) - (pSrc[2 * l + 1] >> 2u);
-    pSrc[2 * i + 1] =
-      ((pSrc[2 * l + 1] >> 2u) + (pSrc[2 * i + 1] >> 2u)) >> 1u;
-
-    pSrc[2u * l] = (((int32_t) (((q63_t) xt * cosVal) >> 32)) +
-                    ((int32_t) (((q63_t) yt * sinVal) >> 32)));
-
-    pSrc[2u * l + 1u] = (((int32_t) (((q63_t) yt * cosVal) >> 32)) -
-                         ((int32_t) (((q63_t) xt * sinVal) >> 32)));
-
-  }                             // groups loop end 
-
-  twidCoefModifier = twidCoefModifier << 1u;
-
-  // loop for stage 
-  for (k = fftLen / 2; k > 2; k = k >> 1)
-  {
-    n1 = n2;
-    n2 = n2 >> 1;
-    ia = 0;
-
-    // loop for groups 
-    for (j = 0; j < n2; j++)
-    {
-      cosVal = pCoef[ia * 2];
-      sinVal = pCoef[(ia * 2) + 1];
-      ia = ia + twidCoefModifier;
-
-      // loop for butterfly 
-      for (i = j; i < fftLen; i += n1)
-      {
-        l = i + n2;
-        xt = pSrc[2 * i] - pSrc[2 * l];
-        pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
-
-        yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-        pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
-
-        pSrc[2u * l] = (((int32_t) (((q63_t) xt * cosVal) >> 32)) +
-                        ((int32_t) (((q63_t) yt * sinVal) >> 32)));
-
-        pSrc[2u * l + 1u] = (((int32_t) (((q63_t) yt * cosVal) >> 32)) -
-                             ((int32_t) (((q63_t) xt * sinVal) >> 32)));
-
-      }                         // butterfly loop end 
-
-    }                           // groups loop end 
-
-    twidCoefModifier = twidCoefModifier << 1u;
-  }                             // stages loop end 
-
-  n1 = n2;
-  n2 = n2 >> 1;
-  ia = 0;
-
-  cosVal = pCoef[ia * 2];
-  sinVal = pCoef[(ia * 2) + 1];
-  ia = ia + twidCoefModifier;
-
-  // loop for butterfly 
-  for (i = 0; i < fftLen; i += n1)
-  {
-    l = i + n2;
-    xt = pSrc[2 * i] - pSrc[2 * l];
-    pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
-
-    yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-    pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
-
-    pSrc[2u * l] = xt;
-
-    pSrc[2u * l + 1u] = yt;
-
-    i += n1;
-    l = i + n2;
-
-    xt = pSrc[2 * i] - pSrc[2 * l];
-    pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
-
-    yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-    pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
-
-    pSrc[2u * l] = xt;
-
-    pSrc[2u * l + 1u] = yt;
-
-  }                             // butterfly loop end 
-
-}
-
-
-void arm_radix2_butterfly_inverse_q31(
-  q31_t * pSrc,
-  uint32_t fftLen,
-  q31_t * pCoef,
-  uint16_t twidCoefModifier)
-{
-
-  int i, j, k, l;
-  int n1, n2, ia;
-  q31_t xt, yt, cosVal, sinVal;
-
-  //N = fftLen; 
-  n2 = fftLen;
-
-  n1 = n2;
-  n2 = n2 >> 1;
-  ia = 0;
-
-  // loop for groups 
-  for (i = 0; i < n2; i++)
-  {
-    cosVal = pCoef[ia * 2];
-    sinVal = pCoef[(ia * 2) + 1];
-    ia = ia + twidCoefModifier;
-
-    l = i + n2;
-    xt = (pSrc[2 * i] >> 2u) - (pSrc[2 * l] >> 2u);
-    pSrc[2 * i] = ((pSrc[2 * i] >> 2u) + (pSrc[2 * l] >> 2u)) >> 1u;
-
-    yt = (pSrc[2 * i + 1] >> 2u) - (pSrc[2 * l + 1] >> 2u);
-    pSrc[2 * i + 1] =
-      ((pSrc[2 * l + 1] >> 2u) + (pSrc[2 * i + 1] >> 2u)) >> 1u;
-
-    pSrc[2u * l] = (((int32_t) (((q63_t) xt * cosVal) >> 32)) -
-                    ((int32_t) (((q63_t) yt * sinVal) >> 32)));
-
-    pSrc[2u * l + 1u] = (((int32_t) (((q63_t) yt * cosVal) >> 32)) +
-                         ((int32_t) (((q63_t) xt * sinVal) >> 32)));
-
-  }                             // groups loop end 
-
-  twidCoefModifier = twidCoefModifier << 1u;
-
-  // loop for stage 
-  for (k = fftLen / 2; k > 2; k = k >> 1)
-  {
-    n1 = n2;
-    n2 = n2 >> 1;
-    ia = 0;
-
-    // loop for groups 
-    for (j = 0; j < n2; j++)
-    {
-      cosVal = pCoef[ia * 2];
-      sinVal = pCoef[(ia * 2) + 1];
-      ia = ia + twidCoefModifier;
-
-      // loop for butterfly 
-      for (i = j; i < fftLen; i += n1)
-      {
-        l = i + n2;
-        xt = pSrc[2 * i] - pSrc[2 * l];
-        pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
-
-        yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-        pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
-
-        pSrc[2u * l] = (((int32_t) (((q63_t) xt * cosVal) >> 32)) -
-                        ((int32_t) (((q63_t) yt * sinVal) >> 32)));
-
-        pSrc[2u * l + 1u] = (((int32_t) (((q63_t) yt * cosVal) >> 32)) +
-                             ((int32_t) (((q63_t) xt * sinVal) >> 32)));
-
-      }                         // butterfly loop end 
-
-    }                           // groups loop end 
-
-    twidCoefModifier = twidCoefModifier << 1u;
-  }                             // stages loop end 
-
-  n1 = n2;
-  n2 = n2 >> 1;
-  ia = 0;
-
-  cosVal = pCoef[ia * 2];
-  sinVal = pCoef[(ia * 2) + 1];
-  ia = ia + twidCoefModifier;
-
-  // loop for butterfly 
-  for (i = 0; i < fftLen; i += n1)
-  {
-    l = i + n2;
-    xt = pSrc[2 * i] - pSrc[2 * l];
-    pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
-
-    yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-    pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
-
-    pSrc[2u * l] = xt;
-
-    pSrc[2u * l + 1u] = yt;
-
-    i += n1;
-    l = i + n2;
-
-    xt = pSrc[2 * i] - pSrc[2 * l];
-    pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
-
-    yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
-    pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
-
-    pSrc[2u * l] = xt;
-
-    pSrc[2u * l + 1u] = yt;
-
-  }                             // butterfly loop end 
-
-}
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_f32.c
deleted file mode 100644
index d1fb3196e3..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_f32.c
+++ /dev/null
@@ -1,1236 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_cfft_radix4_f32.c    
-*    
-* Description:	Radix-4 Decimation in Frequency CFFT & CIFFT Floating point processing function    
-*    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-* 	 incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupTransforms    
- */
-
-/**    
- * @defgroup Radix4_CFFT_CIFFT Radix-4 Complex FFT Functions    
- *    
- * \par    
- * Complex Fast Fourier Transform(CFFT) and Complex Inverse Fast Fourier Transform(CIFFT) is an efficient algorithm to compute Discrete Fourier Transform(DFT) and Inverse Discrete Fourier Transform(IDFT).    
- * Computational complexity of CFFT reduces drastically when compared to DFT.    
- * \par    
- * This set of functions implements CFFT/CIFFT    
- * for Q15, Q31, and floating-point data types.  The functions operates on in-place buffer which uses same buffer for input and output.    
- * Complex input is stored in input buffer in an interleaved fashion.    
- *    
- * \par    
- * The functions operate on blocks of input and output data and each call to the function processes    
- * 2*fftLen samples through the transform.  pSrc  points to In-place arrays containing 2*fftLen values.    
- * \par   
- * The pSrc points to the array of in-place buffer of size 2*fftLen and inputs and outputs are stored in an interleaved fashion as shown below.    
- * 
 {real[0], imag[0], real[1], imag[1],..} 
    
- *    
- * \par Lengths supported by the transform:   
- * \par    
- * Internally, the function utilize a radix-4 decimation in frequency(DIF) algorithm    
- * and the size of the FFT supported are of the lengths [16, 64, 256, 1024].   
- *     
- *    
- * \par Algorithm:    
- *    
- * Complex Fast Fourier Transform:    
- * \par     
- * Input real and imaginary data:    
- * 
    
- * x(n) = xa + j * ya    
- * x(n+N/4 ) = xb + j * yb    
- * x(n+N/2 ) = xc + j * yc    
- * x(n+3N 4) = xd + j * yd    
- * 
    
- * where N is length of FFT    
- * \par    
- * Output real and imaginary data:    
- * 
    
- * X(4r) = xa'+ j * ya'    
- * X(4r+1) = xb'+ j * yb'    
- * X(4r+2) = xc'+ j * yc'    
- * X(4r+3) = xd'+ j * yd'    
- * 
    
- * \par    
- * Twiddle factors for radix-4 FFT:    
- * 
    
- * Wn = co1 + j * (- si1)    
- * W2n = co2 + j * (- si2)    
- * W3n = co3 + j * (- si3)    
- * 
    
- *    
- * \par    
- * \image html CFFT.gif "Radix-4 Decimation-in Frequency Complex Fast Fourier Transform"    
- *    
- * \par    
- * Output from Radix-4 CFFT Results in Digit reversal order. Interchange middle two branches of every butterfly results in Bit reversed output.    
- * \par    
- *  Butterfly CFFT equations:    
- * 
    
- * xa' = xa + xb + xc + xd    
- * ya' = ya + yb + yc + yd    
- * xc' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)    
- * yc' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)    
- * xb' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)    
- * yb' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)    
- * xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)    
- * yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)    
- * 
    
- *    
- *    
- * Complex Inverse Fast Fourier Transform:    
- * \par    
- * CIFFT uses same twiddle factor table as CFFT with modifications in the design equation as shown below.    
- *    
- * \par    
- *  Modified Butterfly CIFFT equations:    
- * 
    
- * xa' = xa + xb + xc + xd    
- * ya' = ya + yb + yc + yd    
- * xc' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)    
- * yc' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)    
- * xb' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)    
- * yb' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)    
- * xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)    
- * yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)    
- * 
    
- *    
- * \par Instance Structure    
- * A separate instance structure must be defined for each Instance but the twiddle factors and bit reversal tables can be reused.    
- * There are separate instance structure declarations for each of the 3 supported data types.    
- *    
- * \par Initialization Functions    
- * There is also an associated initialization function for each data type.    
- * The initialization function performs the following operations:    
- * - Sets the values of the internal structure fields.    
- * - Initializes twiddle factor table and bit reversal table pointers    
- * \par    
- * Use of the initialization function is optional.    
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
- * To place an instance structure into a const data section, the instance structure must be manually initialized.    
- * Manually initialize the instance structure as follows:    
- * 
    
- *arm_cfft_radix4_instance_f32 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor, onebyfftLen};    
- *arm_cfft_radix4_instance_q31 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};    
- *arm_cfft_radix4_instance_q15 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};    
- * 
    
- * \par    
- * where fftLen length of CFFT/CIFFT; ifftFlag Flag for selection of CFFT or CIFFT(Set ifftFlag to calculate CIFFT otherwise calculates CFFT);    
- * bitReverseFlag Flag for selection of output order(Set bitReverseFlag to output in normal order otherwise output in bit reversed order);     
- * pTwiddlepoints to array of twiddle coefficients; pBitRevTable points to the array of bit reversal table.    
- * twidCoefModifier modifier for twiddle factor table which supports all FFT lengths with same table;     
- * pBitRevTable modifier for bit reversal table which supports all FFT lengths with same table.    
- * onebyfftLen value of 1/fftLen to calculate CIFFT;    
- *   
- * \par Fixed-Point Behavior    
- * Care must be taken when using the fixed-point versions of the CFFT/CIFFT function.    
- * Refer to the function specific documentation below for usage guidelines.    
- */
-
-
-/**    
- * @addtogroup Radix4_CFFT_CIFFT    
- * @{    
- */
-
-/**    
- * @details    
- * @brief Processing function for the floating-point Radix-4 CFFT/CIFFT.   
- * @param[in]      *S    points to an instance of the floating-point Radix-4 CFFT/CIFFT structure.   
- * @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.   
- * @return none.   
- */
-
-void arm_cfft_radix4_f32(
-  const arm_cfft_radix4_instance_f32 * S,
-  float32_t * pSrc)
-{
-
-  if(S->ifftFlag == 1u)
-  {
-    /*  Complex IFFT radix-4  */
-    arm_radix4_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle,
-                                     S->twidCoefModifier, S->onebyfftLen);
-  }
-  else
-  {
-    /*  Complex FFT radix-4  */
-    arm_radix4_butterfly_f32(pSrc, S->fftLen, S->pTwiddle,
-                             S->twidCoefModifier);
-  }
-
-  if(S->bitReverseFlag == 1u)
-  {
-    /*  Bit Reversal */
-    arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
-  }
-
-}
-
-
-/**    
- * @} end of Radix4_CFFT_CIFFT group    
- */
-
-
-/* ----------------------------------------------------------------------    
-** Internal helper function used by the FFTs    
-** ------------------------------------------------------------------- */
-
-/*    
- * @brief  Core function for the floating-point CFFT butterfly process.   
- * @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.   
- * @param[in]      fftLen           length of the FFT.   
- * @param[in]      *pCoef           points to the twiddle coefficient buffer.   
- * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
- * @return none.   
- */
-
-void arm_radix4_butterfly_f32(
-  float32_t * pSrc,
-  uint16_t fftLen,
-  float32_t * pCoef,
-  uint16_t twidCoefModifier)
-{
-
-  float32_t co1, co2, co3, si1, si2, si3;
-  uint32_t ia1, ia2, ia3;
-  uint32_t i0, i1, i2, i3;
-  uint32_t n1, n2, j, k;
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn;
-  float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc,
-    Ybminusd;
-  float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out;
-  float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out;
-  float32_t *ptr1;
-
-  /*  Initializations for the first stage */
-  n2 = fftLen;
-  n1 = n2;
-
-  /* n2 = fftLen/4 */
-  n2 >>= 2u;
-  i0 = 0u;
-  ia1 = 0u;
-
-  j = n2;
-
-  /*  Calculation of first stage */
-  do
-  {
-    /*  index calculation for the input as, */
-    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
-    i1 = i0 + n2;
-    i2 = i1 + n2;
-    i3 = i2 + n2;
-
-    xaIn = pSrc[(2u * i0)];
-    yaIn = pSrc[(2u * i0) + 1u];
-
-    xcIn = pSrc[(2u * i2)];
-    ycIn = pSrc[(2u * i2) + 1u];
-
-    xbIn = pSrc[(2u * i1)];
-    ybIn = pSrc[(2u * i1) + 1u];
-
-    xdIn = pSrc[(2u * i3)];
-    ydIn = pSrc[(2u * i3) + 1u];
-
-    /* xa + xc */
-    Xaplusc = xaIn + xcIn;
-    /* xb + xd */
-    Xbplusd = xbIn + xdIn;
-    /* ya + yc */
-    Yaplusc = yaIn + ycIn;
-    /* yb + yd */
-    Ybplusd = ybIn + ydIn;
-
-    /*  index calculation for the coefficients */
-    ia2 = ia1 + ia1;
-    co2 = pCoef[ia2 * 2u];
-    si2 = pCoef[(ia2 * 2u) + 1u];
-
-    /* xa - xc */
-    Xaminusc = xaIn - xcIn;
-    /* xb - xd */
-    Xbminusd = xbIn - xdIn;
-    /* ya - yc */
-    Yaminusc = yaIn - ycIn;
-    /* yb + yd */
-    Ybminusd = ybIn - ydIn;
-
-    /* xa' = xa + xb + xc + xd */
-    pSrc[(2u * i0)] = Xaplusc + Xbplusd;
-    /* ya' = ya + yb + yc + yd */
-    pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
-
-    /* (xa - xc) + (yb - yd) */
-    Xb12C_out = (Xaminusc + Ybminusd);
-    /* (ya - yc) + (xb - xd) */
-    Yb12C_out = (Yaminusc - Xbminusd);
-    /* (xa + xc) - (xb + xd) */
-    Xc12C_out = (Xaplusc - Xbplusd);
-    /* (ya + yc) - (yb + yd) */
-    Yc12C_out = (Yaplusc - Ybplusd);
-    /* (xa - xc) - (yb - yd) */
-    Xd12C_out = (Xaminusc - Ybminusd);
-    /* (ya - yc) + (xb - xd) */
-    Yd12C_out = (Xbminusd + Yaminusc);
-
-    co1 = pCoef[ia1 * 2u];
-    si1 = pCoef[(ia1 * 2u) + 1u];
-
-    /*  index calculation for the coefficients */
-    ia3 = ia2 + ia1;
-    co3 = pCoef[ia3 * 2u];
-    si3 = pCoef[(ia3 * 2u) + 1u];
-
-    Xb12_out = Xb12C_out * co1;
-    Yb12_out = Yb12C_out * co1;
-    Xc12_out = Xc12C_out * co2;
-    Yc12_out = Yc12C_out * co2;
-    Xd12_out = Xd12C_out * co3;
-    Yd12_out = Yd12C_out * co3;
-
-    /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
-    Xb12_out += Yb12C_out * si1;
-    /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
-    Yb12_out -= Xb12C_out * si1;
-    /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
-    Xc12_out += Yc12C_out * si2;
-    /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
-    Yc12_out -= Xc12C_out * si2;
-    /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
-    Xd12_out += Yd12C_out * si3;
-    /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
-    Yd12_out -= Xd12C_out * si3;
-
-
-    /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
-    pSrc[2u * i1] = Xc12_out;
-
-    /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
-    pSrc[(2u * i1) + 1u] = Yc12_out;
-
-    /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
-    pSrc[2u * i2] = Xb12_out;
-
-    /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
-    pSrc[(2u * i2) + 1u] = Yb12_out;
-
-    /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
-    pSrc[2u * i3] = Xd12_out;
-
-    /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
-    pSrc[(2u * i3) + 1u] = Yd12_out;
-
-    /*  Twiddle coefficients index modifier */
-    ia1 = ia1 + twidCoefModifier;
-
-    /*  Updating input index */
-    i0 = i0 + 1u;
-
-  }
-  while(--j);
-
-  twidCoefModifier <<= 2u;
-
-  /*  Calculation of second stage to excluding last stage */
-  for (k = fftLen / 4; k > 4u; k >>= 2u)
-  {
-    /*  Initializations for the first stage */
-    n1 = n2;
-    n2 >>= 2u;
-    ia1 = 0u;
-
-    /*  Calculation of first stage */
-    for (j = 0u; j <= (n2 - 1u); j++)
-    {
-      /*  index calculation for the coefficients */
-      ia2 = ia1 + ia1;
-      ia3 = ia2 + ia1;
-      co1 = pCoef[ia1 * 2u];
-      si1 = pCoef[(ia1 * 2u) + 1u];
-      co2 = pCoef[ia2 * 2u];
-      si2 = pCoef[(ia2 * 2u) + 1u];
-      co3 = pCoef[ia3 * 2u];
-      si3 = pCoef[(ia3 * 2u) + 1u];
-
-      /*  Twiddle coefficients index modifier */
-      ia1 = ia1 + twidCoefModifier;
-
-      for (i0 = j; i0 < fftLen; i0 += n1)
-      {
-        /*  index calculation for the input as, */
-        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
-        i1 = i0 + n2;
-        i2 = i1 + n2;
-        i3 = i2 + n2;
-
-        xaIn = pSrc[(2u * i0)];
-        yaIn = pSrc[(2u * i0) + 1u];
-
-        xbIn = pSrc[(2u * i1)];
-        ybIn = pSrc[(2u * i1) + 1u];
-
-        xcIn = pSrc[(2u * i2)];
-        ycIn = pSrc[(2u * i2) + 1u];
-
-        xdIn = pSrc[(2u * i3)];
-        ydIn = pSrc[(2u * i3) + 1u];
-
-        /* xa - xc */
-        Xaminusc = xaIn - xcIn;
-        /* (xb - xd) */
-        Xbminusd = xbIn - xdIn;
-        /* ya - yc */
-        Yaminusc = yaIn - ycIn;
-        /* (yb - yd) */
-        Ybminusd = ybIn - ydIn;
-
-        /* xa + xc */
-        Xaplusc = xaIn + xcIn;
-        /* xb + xd */
-        Xbplusd = xbIn + xdIn;
-        /* ya + yc */
-        Yaplusc = yaIn + ycIn;
-        /* yb + yd */
-        Ybplusd = ybIn + ydIn;
-
-        /* (xa - xc) + (yb - yd) */
-        Xb12C_out = (Xaminusc + Ybminusd);
-        /* (ya - yc) -  (xb - xd) */
-        Yb12C_out = (Yaminusc - Xbminusd);
-        /* xa + xc -(xb + xd) */
-        Xc12C_out = (Xaplusc - Xbplusd);
-        /* (ya + yc) - (yb + yd) */
-        Yc12C_out = (Yaplusc - Ybplusd);
-        /* (xa - xc) - (yb - yd) */
-        Xd12C_out = (Xaminusc - Ybminusd);
-        /* (ya - yc) +  (xb - xd) */
-        Yd12C_out = (Xbminusd + Yaminusc);
-
-        pSrc[(2u * i0)] = Xaplusc + Xbplusd;
-        pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
-
-        Xb12_out = Xb12C_out * co1;
-        Yb12_out = Yb12C_out * co1;
-        Xc12_out = Xc12C_out * co2;
-        Yc12_out = Yc12C_out * co2;
-        Xd12_out = Xd12C_out * co3;
-        Yd12_out = Yd12C_out * co3;
-
-        /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
-        Xb12_out += Yb12C_out * si1;
-        /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
-        Yb12_out -= Xb12C_out * si1;
-        /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
-        Xc12_out += Yc12C_out * si2;
-        /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
-        Yc12_out -= Xc12C_out * si2;
-        /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
-        Xd12_out += Yd12C_out * si3;
-        /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
-        Yd12_out -= Xd12C_out * si3;
-
-        /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
-        pSrc[2u * i1] = Xc12_out;
-
-        /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
-        pSrc[(2u * i1) + 1u] = Yc12_out;
-
-        /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
-        pSrc[2u * i2] = Xb12_out;
-
-        /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
-        pSrc[(2u * i2) + 1u] = Yb12_out;
-
-        /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
-        pSrc[2u * i3] = Xd12_out;
-
-        /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
-        pSrc[(2u * i3) + 1u] = Yd12_out;
-
-      }
-    }
-    twidCoefModifier <<= 2u;
-  }
-
-  j = fftLen >> 2;
-  ptr1 = &pSrc[0];
-
-  /*  Calculations of last stage */
-  do
-  {
-
-    xaIn = ptr1[0];
-    xcIn = ptr1[4];
-    yaIn = ptr1[1];
-    ycIn = ptr1[5];
-
-    /* xa + xc */
-    Xaplusc = xaIn + xcIn;
-
-    xbIn = ptr1[2];
-
-    /* xa - xc */
-    Xaminusc = xaIn - xcIn;
-
-    xdIn = ptr1[6];
-
-    /* ya + yc */
-    Yaplusc = yaIn + ycIn;
-
-    ybIn = ptr1[3];
-
-    /* ya - yc */
-    Yaminusc = yaIn - ycIn;
-
-    ydIn = ptr1[7];
-
-    /* xb + xd */
-    Xbplusd = xbIn + xdIn;
-
-    /* yb + yd */
-    Ybplusd = ybIn + ydIn;
-
-    /* xa' = xa + xb + xc + xd */
-    ptr1[0] = (Xaplusc + Xbplusd);
-
-    /* (xb-xd) */
-    Xbminusd = xbIn - xdIn;
-
-    /* ya' = ya + yb + yc + yd */
-    ptr1[1] = (Yaplusc + Ybplusd);
-
-    /* (yb-yd) */
-    Ybminusd = ybIn - ydIn;
-
-    /* xc' = (xa-xb+xc-xd) */
-    ptr1[2] = (Xaplusc - Xbplusd);
-    /* yc' = (ya-yb+yc-yd) */
-    ptr1[3] = (Yaplusc - Ybplusd);
-    /* xb' = (xa+yb-xc-yd) */
-    ptr1[4] = (Xaminusc + Ybminusd);
-    /* yb' = (ya-xb-yc+xd) */
-    ptr1[5] = (Yaminusc - Xbminusd);
-    /* xd' = (xa-yb-xc+yd)) */
-    ptr1[6] = (Xaminusc - Ybminusd);
-    /* yd' = (ya+xb-yc-xd) */
-    ptr1[7] = (Xbminusd + Yaminusc);
-
-    /* increment pointer by 8 */
-    ptr1 = ptr1 + 8u;
-
-  } while(--j);
-
-#else
-
-  float32_t t1, t2, r1, r2, s1, s2;
-
-  /* Run the below code for Cortex-M0 */
-
-  /*  Initializations for the fft calculation */
-  n2 = fftLen;
-  n1 = n2;
-  for (k = fftLen; k > 1u; k >>= 2u)
-  {
-    /*  Initializations for the fft calculation */
-    n1 = n2;
-    n2 >>= 2u;
-    ia1 = 0u;
-
-    /*  FFT Calculation */
-    for (j = 0u; j <= (n2 - 1u); j++)
-    {
-      /*  index calculation for the coefficients */
-      ia2 = ia1 + ia1;
-      ia3 = ia2 + ia1;
-      co1 = pCoef[ia1 * 2u];
-      si1 = pCoef[(ia1 * 2u) + 1u];
-      co2 = pCoef[ia2 * 2u];
-      si2 = pCoef[(ia2 * 2u) + 1u];
-      co3 = pCoef[ia3 * 2u];
-      si3 = pCoef[(ia3 * 2u) + 1u];
-
-      /*  Twiddle coefficients index modifier */
-      ia1 = ia1 + twidCoefModifier;
-
-      for (i0 = j; i0 < fftLen; i0 += n1)
-      {
-        /*  index calculation for the input as, */
-        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
-        i1 = i0 + n2;
-        i2 = i1 + n2;
-        i3 = i2 + n2;
-
-        /* xa + xc */
-        r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
-
-        /* xa - xc */
-        r2 = pSrc[(2u * i0)] - pSrc[(2u * i2)];
-
-        /* ya + yc */
-        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
-
-        /* ya - yc */
-        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
-
-        /* xb + xd */
-        t1 = pSrc[2u * i1] + pSrc[2u * i3];
-
-        /* xa' = xa + xb + xc + xd */
-        pSrc[2u * i0] = r1 + t1;
-
-        /* xa + xc -(xb + xd) */
-        r1 = r1 - t1;
-
-        /* yb + yd */
-        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
-
-        /* ya' = ya + yb + yc + yd */
-        pSrc[(2u * i0) + 1u] = s1 + t2;
-
-        /* (ya + yc) - (yb + yd) */
-        s1 = s1 - t2;
-
-        /* (yb - yd) */
-        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
-
-        /* (xb - xd) */
-        t2 = pSrc[2u * i1] - pSrc[2u * i3];
-
-        /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
-        pSrc[2u * i1] = (r1 * co2) + (s1 * si2);
-
-        /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
-        pSrc[(2u * i1) + 1u] = (s1 * co2) - (r1 * si2);
-
-        /* (xa - xc) + (yb - yd) */
-        r1 = r2 + t1;
-
-        /* (xa - xc) - (yb - yd) */
-        r2 = r2 - t1;
-
-        /* (ya - yc) -  (xb - xd) */
-        s1 = s2 - t2;
-
-        /* (ya - yc) +  (xb - xd) */
-        s2 = s2 + t2;
-
-        /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
-        pSrc[2u * i2] = (r1 * co1) + (s1 * si1);
-
-        /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
-        pSrc[(2u * i2) + 1u] = (s1 * co1) - (r1 * si1);
-
-        /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
-        pSrc[2u * i3] = (r2 * co3) + (s2 * si3);
-
-        /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
-        pSrc[(2u * i3) + 1u] = (s2 * co3) - (r2 * si3);
-      }
-    }
-    twidCoefModifier <<= 2u;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-}
-
-/*    
- * @brief  Core function for the floating-point CIFFT butterfly process.   
- * @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.   
- * @param[in]      fftLen           length of the FFT.   
- * @param[in]      *pCoef           points to twiddle coefficient buffer.   
- * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
- * @param[in]      onebyfftLen      value of 1/fftLen.   
- * @return none.   
- */
-
-void arm_radix4_butterfly_inverse_f32(
-  float32_t * pSrc,
-  uint16_t fftLen,
-  float32_t * pCoef,
-  uint16_t twidCoefModifier,
-  float32_t onebyfftLen)
-{
-  float32_t co1, co2, co3, si1, si2, si3;
-  uint32_t ia1, ia2, ia3;
-  uint32_t i0, i1, i2, i3;
-  uint32_t n1, n2, j, k;
-
-#ifndef ARM_MATH_CM0
-
-  float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn;
-  float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc,
-    Ybminusd;
-  float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out;
-  float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out;
-  float32_t *ptr1;
-
-
-  /*  Initializations for the first stage */
-  n2 = fftLen;
-  n1 = n2;
-
-  /* n2 = fftLen/4 */
-  n2 >>= 2u;
-  i0 = 0u;
-  ia1 = 0u;
-
-  j = n2;
-
-  /*  Calculation of first stage */
-  do
-  {
-    /*  index calculation for the input as, */
-    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
-    i1 = i0 + n2;
-    i2 = i1 + n2;
-    i3 = i2 + n2;
-
-    /*  Butterfly implementation */
-    xaIn = pSrc[(2u * i0)];
-    yaIn = pSrc[(2u * i0) + 1u];
-
-    xcIn = pSrc[(2u * i2)];
-    ycIn = pSrc[(2u * i2) + 1u];
-
-    xbIn = pSrc[(2u * i1)];
-    ybIn = pSrc[(2u * i1) + 1u];
-
-    xdIn = pSrc[(2u * i3)];
-    ydIn = pSrc[(2u * i3) + 1u];
-
-    /* xa + xc */
-    Xaplusc = xaIn + xcIn;
-    /* xb + xd */
-    Xbplusd = xbIn + xdIn;
-    /* ya + yc */
-    Yaplusc = yaIn + ycIn;
-    /* yb + yd */
-    Ybplusd = ybIn + ydIn;
-
-    /*  index calculation for the coefficients */
-    ia2 = ia1 + ia1;
-    co2 = pCoef[ia2 * 2u];
-    si2 = pCoef[(ia2 * 2u) + 1u];
-
-    /* xa - xc */
-    Xaminusc = xaIn - xcIn;
-    /* xb - xd */
-    Xbminusd = xbIn - xdIn;
-    /* ya - yc */
-    Yaminusc = yaIn - ycIn;
-    /* yb - yd */
-    Ybminusd = ybIn - ydIn;
-
-    /* xa' = xa + xb + xc + xd */
-    pSrc[(2u * i0)] = Xaplusc + Xbplusd;
-
-    /* ya' = ya + yb + yc + yd */
-    pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
-
-    /* (xa - xc) - (yb - yd) */
-    Xb12C_out = (Xaminusc - Ybminusd);
-    /* (ya - yc) + (xb - xd) */
-    Yb12C_out = (Yaminusc + Xbminusd);
-    /* (xa + xc) - (xb + xd) */
-    Xc12C_out = (Xaplusc - Xbplusd);
-    /* (ya + yc) - (yb + yd) */
-    Yc12C_out = (Yaplusc - Ybplusd);
-    /* (xa - xc) + (yb - yd) */
-    Xd12C_out = (Xaminusc + Ybminusd);
-    /* (ya - yc) - (xb - xd) */
-    Yd12C_out = (Yaminusc - Xbminusd);
-
-    co1 = pCoef[ia1 * 2u];
-    si1 = pCoef[(ia1 * 2u) + 1u];
-
-    /*  index calculation for the coefficients */
-    ia3 = ia2 + ia1;
-    co3 = pCoef[ia3 * 2u];
-    si3 = pCoef[(ia3 * 2u) + 1u];
-
-    Xb12_out = Xb12C_out * co1;
-    Yb12_out = Yb12C_out * co1;
-    Xc12_out = Xc12C_out * co2;
-    Yc12_out = Yc12C_out * co2;
-    Xd12_out = Xd12C_out * co3;
-    Yd12_out = Yd12C_out * co3;
-
-    /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
-    Xb12_out -= Yb12C_out * si1;
-    /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
-    Yb12_out += Xb12C_out * si1;
-    /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
-    Xc12_out -= Yc12C_out * si2;
-    /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
-    Yc12_out += Xc12C_out * si2;
-    /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
-    Xd12_out -= Yd12C_out * si3;
-    /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
-    Yd12_out += Xd12C_out * si3;
-
-    /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
-    pSrc[2u * i1] = Xc12_out;
-
-    /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
-    pSrc[(2u * i1) + 1u] = Yc12_out;
-
-    /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
-    pSrc[2u * i2] = Xb12_out;
-
-    /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
-    pSrc[(2u * i2) + 1u] = Yb12_out;
-
-    /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
-    pSrc[2u * i3] = Xd12_out;
-
-    /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
-    pSrc[(2u * i3) + 1u] = Yd12_out;
-
-    /*  Twiddle coefficients index modifier */
-    ia1 = ia1 + twidCoefModifier;
-
-    /*  Updating input index */
-    i0 = i0 + 1u;
-
-  } while(--j);
-
-  twidCoefModifier <<= 2u;
-
-  /*  Calculation of second stage to excluding last stage */
-  for (k = fftLen / 4; k > 4u; k >>= 2u)
-  {
-    /*  Initializations for the first stage */
-    n1 = n2;
-    n2 >>= 2u;
-    ia1 = 0u;
-
-    /*  Calculation of first stage */
-    for (j = 0u; j <= (n2 - 1u); j++)
-    {
-      /*  index calculation for the coefficients */
-      ia2 = ia1 + ia1;
-      ia3 = ia2 + ia1;
-      co1 = pCoef[ia1 * 2u];
-      si1 = pCoef[(ia1 * 2u) + 1u];
-      co2 = pCoef[ia2 * 2u];
-      si2 = pCoef[(ia2 * 2u) + 1u];
-      co3 = pCoef[ia3 * 2u];
-      si3 = pCoef[(ia3 * 2u) + 1u];
-
-      /*  Twiddle coefficients index modifier */
-      ia1 = ia1 + twidCoefModifier;
-
-      for (i0 = j; i0 < fftLen; i0 += n1)
-      {
-        /*  index calculation for the input as, */
-        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
-        i1 = i0 + n2;
-        i2 = i1 + n2;
-        i3 = i2 + n2;
-
-        xaIn = pSrc[(2u * i0)];
-        yaIn = pSrc[(2u * i0) + 1u];
-
-        xbIn = pSrc[(2u * i1)];
-        ybIn = pSrc[(2u * i1) + 1u];
-
-        xcIn = pSrc[(2u * i2)];
-        ycIn = pSrc[(2u * i2) + 1u];
-
-        xdIn = pSrc[(2u * i3)];
-        ydIn = pSrc[(2u * i3) + 1u];
-
-        /* xa - xc */
-        Xaminusc = xaIn - xcIn;
-        /* (xb - xd) */
-        Xbminusd = xbIn - xdIn;
-        /* ya - yc */
-        Yaminusc = yaIn - ycIn;
-        /* (yb - yd) */
-        Ybminusd = ybIn - ydIn;
-
-        /* xa + xc */
-        Xaplusc = xaIn + xcIn;
-        /* xb + xd */
-        Xbplusd = xbIn + xdIn;
-        /* ya + yc */
-        Yaplusc = yaIn + ycIn;
-        /* yb + yd */
-        Ybplusd = ybIn + ydIn;
-
-        /* (xa - xc) - (yb - yd) */
-        Xb12C_out = (Xaminusc - Ybminusd);
-        /* (ya - yc) +  (xb - xd) */
-        Yb12C_out = (Yaminusc + Xbminusd);
-        /* xa + xc -(xb + xd) */
-        Xc12C_out = (Xaplusc - Xbplusd);
-        /* (ya + yc) - (yb + yd) */
-        Yc12C_out = (Yaplusc - Ybplusd);
-        /* (xa - xc) + (yb - yd) */
-        Xd12C_out = (Xaminusc + Ybminusd);
-        /* (ya - yc) -  (xb - xd) */
-        Yd12C_out = (Yaminusc - Xbminusd);
-
-        pSrc[(2u * i0)] = Xaplusc + Xbplusd;
-        pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
-
-        Xb12_out = Xb12C_out * co1;
-        Yb12_out = Yb12C_out * co1;
-        Xc12_out = Xc12C_out * co2;
-        Yc12_out = Yc12C_out * co2;
-        Xd12_out = Xd12C_out * co3;
-        Yd12_out = Yd12C_out * co3;
-
-        /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
-        Xb12_out -= Yb12C_out * si1;
-        /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
-        Yb12_out += Xb12C_out * si1;
-        /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
-        Xc12_out -= Yc12C_out * si2;
-        /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
-        Yc12_out += Xc12C_out * si2;
-        /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
-        Xd12_out -= Yd12C_out * si3;
-        /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
-        Yd12_out += Xd12C_out * si3;
-
-        /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
-        pSrc[2u * i1] = Xc12_out;
-
-        /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
-        pSrc[(2u * i1) + 1u] = Yc12_out;
-
-        /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
-        pSrc[2u * i2] = Xb12_out;
-
-        /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
-        pSrc[(2u * i2) + 1u] = Yb12_out;
-
-        /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
-        pSrc[2u * i3] = Xd12_out;
-
-        /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
-        pSrc[(2u * i3) + 1u] = Yd12_out;
-
-      }
-    }
-    twidCoefModifier <<= 2u;
-  }
-  /*  Initializations of last stage */
-
-  j = fftLen >> 2;
-  ptr1 = &pSrc[0];
-
-  /*  Calculations of last stage */
-  do
-  {
-
-    xaIn = ptr1[0];
-    xcIn = ptr1[4];
-    yaIn = ptr1[1];
-    ycIn = ptr1[5];
-
-    /*  Butterfly implementation */
-    /* xa + xc */
-    Xaplusc = xaIn + xcIn;
-
-    xbIn = ptr1[2];
-
-    /* xa - xc */
-    Xaminusc = xaIn - xcIn;
-
-    xdIn = ptr1[6];
-
-    /* ya + yc */
-    Yaplusc = yaIn + ycIn;
-
-    ybIn = ptr1[3];
-
-    /* ya - yc */
-    Yaminusc = yaIn - ycIn;
-
-    ydIn = ptr1[7];
-
-    /* xc + xd */
-    Xbplusd = xbIn + xdIn;
-
-    /* yb + yd */
-    Ybplusd = ybIn + ydIn;
-
-    /* xa' = xa + xb + xc + xd */
-    ptr1[0] = (Xaplusc + Xbplusd) * onebyfftLen;
-
-    /* (xb-xd) */
-    Xbminusd = xbIn - xdIn;
-
-    /* ya' = ya + yb + yc + yd */
-    ptr1[1] = (Yaplusc + Ybplusd) * onebyfftLen;
-
-    /* (yb-yd) */
-    Ybminusd = ybIn - ydIn;
-
-    /* xc' = (xa-xb+xc-xd) * onebyfftLen */
-    ptr1[2] = (Xaplusc - Xbplusd) * onebyfftLen;
-
-    /* yc' = (ya-yb+yc-yd) * onebyfftLen  */
-    ptr1[3] = (Yaplusc - Ybplusd) * onebyfftLen;
-
-    /* xb' = (xa-yb-xc+yd) * onebyfftLen */
-    ptr1[4] = (Xaminusc - Ybminusd) * onebyfftLen;
-
-    /* yb' = (ya+xb-yc-xd) * onebyfftLen */
-    ptr1[5] = (Yaminusc + Xbminusd) * onebyfftLen;
-
-    /* xd' = (xa-yb-xc+yd) * onebyfftLen */
-    ptr1[6] = (Xaminusc + Ybminusd) * onebyfftLen;
-
-    /* yd' = (ya-xb-yc+xd) * onebyfftLen */
-    ptr1[7] = (Yaminusc - Xbminusd) * onebyfftLen;
-
-    /* increment source pointer by 8 for next calculations */
-    ptr1 = ptr1 + 8u;
-
-  } while(--j);
-
-#else
-
-  float32_t t1, t2, r1, r2, s1, s2;
-
-  /* Run the below code for Cortex-M0 */
-
-  /*  Initializations for the first stage */
-  n2 = fftLen;
-  n1 = n2;
-
-  /*  Calculation of first stage */
-  for (k = fftLen; k > 4u; k >>= 2u)
-  {
-    /*  Initializations for the first stage */
-    n1 = n2;
-    n2 >>= 2u;
-    ia1 = 0u;
-
-    /*  Calculation of first stage */
-    for (j = 0u; j <= (n2 - 1u); j++)
-    {
-      /*  index calculation for the coefficients */
-      ia2 = ia1 + ia1;
-      ia3 = ia2 + ia1;
-      co1 = pCoef[ia1 * 2u];
-      si1 = pCoef[(ia1 * 2u) + 1u];
-      co2 = pCoef[ia2 * 2u];
-      si2 = pCoef[(ia2 * 2u) + 1u];
-      co3 = pCoef[ia3 * 2u];
-      si3 = pCoef[(ia3 * 2u) + 1u];
-
-      /*  Twiddle coefficients index modifier */
-      ia1 = ia1 + twidCoefModifier;
-
-      for (i0 = j; i0 < fftLen; i0 += n1)
-      {
-        /*  index calculation for the input as, */
-        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
-        i1 = i0 + n2;
-        i2 = i1 + n2;
-        i3 = i2 + n2;
-
-        /* xa + xc */
-        r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
-
-        /* xa - xc */
-        r2 = pSrc[(2u * i0)] - pSrc[(2u * i2)];
-
-        /* ya + yc */
-        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
-
-        /* ya - yc */
-        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
-
-        /* xb + xd */
-        t1 = pSrc[2u * i1] + pSrc[2u * i3];
-
-        /* xa' = xa + xb + xc + xd */
-        pSrc[2u * i0] = r1 + t1;
-
-        /* xa + xc -(xb + xd) */
-        r1 = r1 - t1;
-
-        /* yb + yd */
-        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
-
-        /* ya' = ya + yb + yc + yd */
-        pSrc[(2u * i0) + 1u] = s1 + t2;
-
-        /* (ya + yc) - (yb + yd) */
-        s1 = s1 - t2;
-
-        /* (yb - yd) */
-        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
-
-        /* (xb - xd) */
-        t2 = pSrc[2u * i1] - pSrc[2u * i3];
-
-        /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
-        pSrc[2u * i1] = (r1 * co2) - (s1 * si2);
-
-        /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
-        pSrc[(2u * i1) + 1u] = (s1 * co2) + (r1 * si2);
-
-        /* (xa - xc) - (yb - yd) */
-        r1 = r2 - t1;
-
-        /* (xa - xc) + (yb - yd) */
-        r2 = r2 + t1;
-
-        /* (ya - yc) +  (xb - xd) */
-        s1 = s2 + t2;
-
-        /* (ya - yc) -  (xb - xd) */
-        s2 = s2 - t2;
-
-        /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
-        pSrc[2u * i2] = (r1 * co1) - (s1 * si1);
-
-        /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
-        pSrc[(2u * i2) + 1u] = (s1 * co1) + (r1 * si1);
-
-        /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
-        pSrc[2u * i3] = (r2 * co3) - (s2 * si3);
-
-        /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
-        pSrc[(2u * i3) + 1u] = (s2 * co3) + (r2 * si3);
-      }
-    }
-    twidCoefModifier <<= 2u;
-  }
-  /*  Initializations of last stage */
-  n1 = n2;
-  n2 >>= 2u;
-
-  /*  Calculations of last stage */
-  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
-  {
-    /*  index calculation for the input as, */
-    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
-    i1 = i0 + n2;
-    i2 = i1 + n2;
-    i3 = i2 + n2;
-
-    /*  Butterfly implementation */
-    /* xa + xc */
-    r1 = pSrc[2u * i0] + pSrc[2u * i2];
-
-    /* xa - xc */
-    r2 = pSrc[2u * i0] - pSrc[2u * i2];
-
-    /* ya + yc */
-    s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
-
-    /* ya - yc */
-    s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
-
-    /* xc + xd */
-    t1 = pSrc[2u * i1] + pSrc[2u * i3];
-
-    /* xa' = xa + xb + xc + xd */
-    pSrc[2u * i0] = (r1 + t1) * onebyfftLen;
-
-    /* (xa + xb) - (xc + xd) */
-    r1 = r1 - t1;
-
-    /* yb + yd */
-    t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
-
-    /* ya' = ya + yb + yc + yd */
-    pSrc[(2u * i0) + 1u] = (s1 + t2) * onebyfftLen;
-
-    /* (ya + yc) - (yb + yd) */
-    s1 = s1 - t2;
-
-    /* (yb-yd) */
-    t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
-
-    /* (xb-xd) */
-    t2 = pSrc[2u * i1] - pSrc[2u * i3];
-
-    /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
-    pSrc[2u * i1] = r1 * onebyfftLen;
-
-    /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
-    pSrc[(2u * i1) + 1u] = s1 * onebyfftLen;
-
-
-    /* (xa - xc) - (yb-yd) */
-    r1 = r2 - t1;
-
-    /* (xa - xc) + (yb-yd) */
-    r2 = r2 + t1;
-
-    /* (ya - yc) + (xb-xd) */
-    s1 = s2 + t2;
-
-    /* (ya - yc) - (xb-xd) */
-    s2 = s2 - t2;
-
-    /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
-    pSrc[2u * i2] = r1 * onebyfftLen;
-
-    /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
-    pSrc[(2u * i2) + 1u] = s1 * onebyfftLen;
-
-    /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
-    pSrc[2u * i3] = r2 * onebyfftLen;
-
-    /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
-    pSrc[(2u * i3) + 1u] = s2 * onebyfftLen;
-  }
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-}
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_f32.c
deleted file mode 100644
index 11cf66ff8b..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_f32.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_cfft_radix4_init_f32.c    
-*    
-* Description:	Radix-4 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-* 	 incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------- */
-
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**    
- * @ingroup groupTransforms    
- */
-
-/**    
- * @addtogroup Radix4_CFFT_CIFFT    
- * @{    
- */
-
-/**    
-* @brief  Initialization function for the floating-point CFFT/CIFFT.   
-* @param[in,out] *S             points to an instance of the floating-point CFFT/CIFFT structure.   
-* @param[in]     fftLen         length of the FFT.   
-* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.   
-* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.   
-* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.   
-*    
-* \par Description:   
-* \par    
-* The parameter ifftFlag controls whether a forward or inverse transform is computed.    
-* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated   
-* \par    
-* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.    
-* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.    
-* \par    
-* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.    
-* \par    
-* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.    
-*/
-
-arm_status arm_cfft_radix4_init_f32(
-  arm_cfft_radix4_instance_f32 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag)
-{
-  /*  Initialise the default arm status */
-  arm_status status = ARM_MATH_SUCCESS;
-
-  /*  Initialise the FFT length */
-  S->fftLen = fftLen;
-
-  /*  Initialise the Twiddle coefficient pointer */
-  S->pTwiddle = (float32_t *) twiddleCoef;
-
-  /*  Initialise the Flag for selection of CFFT or CIFFT */
-  S->ifftFlag = ifftFlag;
-
-  /*  Initialise the Flag for calculation Bit reversal or not */
-  S->bitReverseFlag = bitReverseFlag;
-
-  /*  Initializations of structure parameters depending on the FFT length */
-  switch (S->fftLen)
-  {
-
-  case 4096u:
-    /*  Initializations of structure parameters for 4096 point FFT */
-
-    /*  Initialise the twiddle coef modifier value */
-    S->twidCoefModifier = 1u;
-    /*  Initialise the bit reversal table modifier */
-    S->bitRevFactor = 1u;
-    /*  Initialise the bit reversal table pointer */
-    S->pBitRevTable = (uint16_t *) armBitRevTable;
-    /*  Initialise the 1/fftLen Value */
-    S->onebyfftLen = 0.000244140625;
-    break;
-
-  case 1024u:
-    /*  Initializations of structure parameters for 1024 point FFT */
-
-    /*  Initialise the twiddle coef modifier value */
-    S->twidCoefModifier = 4u;
-    /*  Initialise the bit reversal table modifier */
-    S->bitRevFactor = 4u;
-    /*  Initialise the bit reversal table pointer */
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
-    /*  Initialise the 1/fftLen Value */
-    S->onebyfftLen = 0.0009765625f;
-    break;
-
-
-  case 256u:
-    /*  Initializations of structure parameters for 256 point FFT */
-    S->twidCoefModifier = 16u;
-    S->bitRevFactor = 16u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
-    S->onebyfftLen = 0.00390625f;
-    break;
-
-  case 64u:
-    /*  Initializations of structure parameters for 64 point FFT */
-    S->twidCoefModifier = 64u;
-    S->bitRevFactor = 64u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
-    S->onebyfftLen = 0.015625f;
-    break;
-
-  case 16u:
-    /*  Initializations of structure parameters for 16 point FFT */
-    S->twidCoefModifier = 256u;
-    S->bitRevFactor = 256u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
-    S->onebyfftLen = 0.0625f;
-    break;
-
-
-  default:
-    /*  Reporting argument error if fftSize is not valid value */
-    status = ARM_MATH_ARGUMENT_ERROR;
-    break;
-  }
-
-  return (status);
-}
-
-/**    
- * @} end of Radix4_CFFT_CIFFT group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q15.c
deleted file mode 100644
index dd637a3612..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q15.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_cfft_radix4_init_q15.c    
-*    
-* Description:	Radix-4 Decimation in Frequency Q15 FFT & IFFT initialization function    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-* 	 incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**    
- * @ingroup groupTransforms    
- */
-
-
-/**    
- * @addtogroup Radix4_CFFT_CIFFT    
- * @{    
- */
-
-
-/**    
-* @brief Initialization function for the Q15 CFFT/CIFFT.   
-* @param[in,out] *S             points to an instance of the Q15 CFFT/CIFFT structure.   
-* @param[in]     fftLen         length of the FFT.   
-* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.   
-* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.   
-* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.   
-*    
-* \par Description:   
-* \par    
-* The parameter ifftFlag controls whether a forward or inverse transform is computed.    
-* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated   
-* \par    
-* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.    
-* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.    
-* \par    
-* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.    
-* \par    
-* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.    
-*/
-
-arm_status arm_cfft_radix4_init_q15(
-  arm_cfft_radix4_instance_q15 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag)
-{
-  /*  Initialise the default arm status */
-  arm_status status = ARM_MATH_SUCCESS;
-  /*  Initialise the FFT length */
-  S->fftLen = fftLen;
-  /*  Initialise the Twiddle coefficient pointer */
-  S->pTwiddle = (q15_t *) twiddleCoefQ15;
-  /*  Initialise the Flag for selection of CFFT or CIFFT */
-  S->ifftFlag = ifftFlag;
-  /*  Initialise the Flag for calculation Bit reversal or not */
-  S->bitReverseFlag = bitReverseFlag;
-
-  /*  Initializations of structure parameters depending on the FFT length */
-  switch (S->fftLen)
-  {
-  case 4096u:
-    /*  Initializations of structure parameters for 4096 point FFT */
-
-    /*  Initialise the twiddle coef modifier value */
-    S->twidCoefModifier = 1u;
-    /*  Initialise the bit reversal table modifier */
-    S->bitRevFactor = 1u;
-    /*  Initialise the bit reversal table pointer */
-    S->pBitRevTable = (uint16_t *) armBitRevTable;
-
-    break;
-
-  case 1024u:
-    /*  Initializations of structure parameters for 1024 point FFT */
-    S->twidCoefModifier = 4u;
-    S->bitRevFactor = 4u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
-
-    break;
-
-  case 256u:
-    /*  Initializations of structure parameters for 256 point FFT */
-    S->twidCoefModifier = 16u;
-    S->bitRevFactor = 16u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
-
-    break;
-
-  case 64u:
-    /*  Initializations of structure parameters for 64 point FFT */
-    S->twidCoefModifier = 64u;
-    S->bitRevFactor = 64u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
-
-    break;
-
-  case 16u:
-    /*  Initializations of structure parameters for 16 point FFT */
-    S->twidCoefModifier = 256u;
-    S->bitRevFactor = 256u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
-
-    break;
-
-  default:
-    /*  Reporting argument error if fftSize is not valid value */
-    status = ARM_MATH_ARGUMENT_ERROR;
-    break;
-  }
-
-  return (status);
-}
-
-/**    
- * @} end of Radix4_CFFT_CIFFT group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q31.c
deleted file mode 100644
index 66f06e6342..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q31.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_cfft_radix4_init_q31.c    
-*    
-* Description:	Radix-4 Decimation in Frequency Q31 FFT & IFFT initialization function    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-* 	 incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-/**    
- * @ingroup groupTransforms    
- */
-
-/**    
- * @addtogroup Radix4_CFFT_CIFFT    
- * @{    
- */
-
-/**    
-*    
-* @brief  Initialization function for the Q31 CFFT/CIFFT.   
-* @param[in,out] *S             points to an instance of the Q31 CFFT/CIFFT structure.   
-* @param[in]     fftLen         length of the FFT.   
-* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.   
-* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.   
-* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.   
-*    
-* \par Description:   
-* \par    
-* The parameter ifftFlag controls whether a forward or inverse transform is computed.    
-* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated   
-* \par    
-* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.    
-* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.    
-* \par    
-* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.    
-* \par    
-* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.    
-*/
-
-arm_status arm_cfft_radix4_init_q31(
-  arm_cfft_radix4_instance_q31 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag)
-{
-  /*  Initialise the default arm status */
-  arm_status status = ARM_MATH_SUCCESS;
-  /*  Initialise the FFT length */
-  S->fftLen = fftLen;
-  /*  Initialise the Twiddle coefficient pointer */
-  S->pTwiddle = (q31_t *) twiddleCoefQ31;
-  /*  Initialise the Flag for selection of CFFT or CIFFT */
-  S->ifftFlag = ifftFlag;
-  /*  Initialise the Flag for calculation Bit reversal or not */
-  S->bitReverseFlag = bitReverseFlag;
-
-  /*  Initializations of Instance structure depending on the FFT length */
-  switch (S->fftLen)
-  {
-    /*  Initializations of structure parameters for 4096 point FFT */
-  case 4096u:
-    /*  Initialise the twiddle coef modifier value */
-    S->twidCoefModifier = 1u;
-    /*  Initialise the bit reversal table modifier */
-    S->bitRevFactor = 1u;
-    /*  Initialise the bit reversal table pointer */
-    S->pBitRevTable = (uint16_t *) armBitRevTable;
-    break;
-
-    /*  Initializations of structure parameters for 1024 point FFT */
-  case 1024u:
-    /*  Initialise the twiddle coef modifier value */
-    S->twidCoefModifier = 4u;
-    /*  Initialise the bit reversal table modifier */
-    S->bitRevFactor = 4u;
-    /*  Initialise the bit reversal table pointer */
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
-    break;
-
-  case 256u:
-    /*  Initializations of structure parameters for 256 point FFT */
-    S->twidCoefModifier = 16u;
-    S->bitRevFactor = 16u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
-    break;
-
-  case 64u:
-    /*  Initializations of structure parameters for 64 point FFT */
-    S->twidCoefModifier = 64u;
-    S->bitRevFactor = 64u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
-    break;
-
-  case 16u:
-    /*  Initializations of structure parameters for 16 point FFT */
-    S->twidCoefModifier = 256u;
-    S->bitRevFactor = 256u;
-    S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
-    break;
-
-  default:
-    /*  Reporting argument error if fftSize is not valid value */
-    status = ARM_MATH_ARGUMENT_ERROR;
-    break;
-  }
-
-  return (status);
-}
-
-/**    
- * @} end of Radix4_CFFT_CIFFT group    
- */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q15.c
deleted file mode 100644
index 023e2f7abc..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q15.c
+++ /dev/null
@@ -1,1896 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_cfft_radix4_q15.c    
-*    
-* Description:	This file has function definition of Radix-4 FFT & IFFT function and    
-*				In-place bit reversal using bit reversal table    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-* 	 incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupTransforms    
- */
-
-/**    
- * @addtogroup Radix4_CFFT_CIFFT    
- * @{    
- */
-
-
-/**    
- * @details    
- * @brief Processing function for the Q15 CFFT/CIFFT.   
- * @param[in]      *S    points to an instance of the Q15 CFFT/CIFFT structure.   
- * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.   
- * @return none.   
- *     
- * \par Input and output formats:    
- * \par    
- * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.   
- * Hence the output format is different for different FFT sizes.    
- * The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT:   
- * \par   
- * \image html CFFTQ15.gif "Input and Output Formats for Q15 CFFT"    
- * \image html CIFFTQ15.gif "Input and Output Formats for Q15 CIFFT"    
- */
-
-void arm_cfft_radix4_q15(
-  const arm_cfft_radix4_instance_q15 * S,
-  q15_t * pSrc)
-{
-  if(S->ifftFlag == 1u)
-  {
-    /*  Complex IFFT radix-4  */
-    arm_radix4_butterfly_inverse_q15(pSrc, S->fftLen, S->pTwiddle,
-                                     S->twidCoefModifier);
-  }
-  else
-  {
-    /*  Complex FFT radix-4  */
-    arm_radix4_butterfly_q15(pSrc, S->fftLen, S->pTwiddle,
-                             S->twidCoefModifier);
-  }
-
-  if(S->bitReverseFlag == 1u)
-  {
-    /*  Bit Reversal */
-    arm_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
-  }
-
-}
-
-/**    
- * @} end of Radix4_CFFT_CIFFT group    
- */
-
-/*    
-* Radix-4 FFT algorithm used is :    
-*    
-* Input real and imaginary data:    
-* x(n) = xa + j * ya    
-* x(n+N/4 ) = xb + j * yb    
-* x(n+N/2 ) = xc + j * yc    
-* x(n+3N 4) = xd + j * yd    
-*    
-*    
-* Output real and imaginary data:    
-* x(4r) = xa'+ j * ya'    
-* x(4r+1) = xb'+ j * yb'    
-* x(4r+2) = xc'+ j * yc'    
-* x(4r+3) = xd'+ j * yd'    
-*    
-*    
-* Twiddle factors for radix-4 FFT:    
-* Wn = co1 + j * (- si1)    
-* W2n = co2 + j * (- si2)    
-* W3n = co3 + j * (- si3)    
-    
-* The real and imaginary output values for the radix-4 butterfly are    
-* xa' = xa + xb + xc + xd    
-* ya' = ya + yb + yc + yd    
-* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)    
-* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)    
-* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)    
-* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)    
-* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)    
-* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)    
-*    
-*/
-
-/**    
- * @brief  Core function for the Q15 CFFT butterfly process.   
- * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.   
- * @param[in]      fftLen           length of the FFT.   
- * @param[in]      *pCoef16         points to twiddle coefficient buffer.   
- * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
- * @return none.   
- */
-
-void arm_radix4_butterfly_q15(
-  q15_t * pSrc16,
-  uint32_t fftLen,
-  q15_t * pCoef16,
-  uint32_t twidCoefModifier)
-{
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t R, S, T, U;
-  q31_t C1, C2, C3, out1, out2;
-  uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
-  q15_t in;
-
-  q15_t *ptr1;
-
-
-
-  q31_t xaya, xbyb, xcyc, xdyd;
-
-  /* Total process is divided into three stages */
-
-  /* process first stage, middle stages, & last stage */
-
-  /*  Initializations for the first stage */
-  n2 = fftLen;
-  n1 = n2;
-
-  /* n2 = fftLen/4 */
-  n2 >>= 2u;
-
-  /* Index for twiddle coefficient */
-  ic = 0u;
-
-  /* Index for input read and output write */
-  i0 = 0u;
-  j = n2;
-
-  /* Input is in 1.15(q15) format */
-
-  /*  start of first stage process */
-  do
-  {
-    /*  Butterfly implementation */
-
-    /*  index calculation for the input as, */
-    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
-    i1 = i0 + n2;
-    i2 = i1 + n2;
-    i3 = i2 + n2;
-
-    /*  Reading i0, i0+fftLen/2 inputs */
-    /* Read ya (real), xa(imag) input */
-    T = _SIMD32_OFFSET(pSrc16 + (2u * i0));
-    in = ((int16_t) (T & 0xFFFF)) >> 2;
-    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
-
-    /* Read yc (real), xc(imag) input */
-    S = _SIMD32_OFFSET(pSrc16 + (2u * i2));
-    in = ((int16_t) (S & 0xFFFF)) >> 2;
-    S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);
-
-    /* R = packed((ya + yc), (xa + xc) ) */
-    R = __QADD16(T, S);
-
-    /* S = packed((ya - yc), (xa - xc) ) */
-    S = __QSUB16(T, S);
-
-    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
-    /* Read yb (real), xb(imag) input */
-    T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
-    in = ((int16_t) (T & 0xFFFF)) >> 2;
-    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
-
-    /* Read yd (real), xd(imag) input */
-    U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
-    in = ((int16_t) (U & 0xFFFF)) >> 2;
-    U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);
-
-    /* T = packed((yb + yd), (xb + xd) ) */
-    T = __QADD16(T, U);
-
-    /*  writing the butterfly processed i0 sample */
-    /* xa' = xa + xb + xc + xd */
-    /* ya' = ya + yb + yc + yd */
-    _SIMD32_OFFSET(pSrc16 + (2u * i0)) = __SHADD16(R, T);
-
-    /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */
-    R = __QSUB16(R, T);
-
-    /* co2 & si2 are read from SIMD Coefficient pointer */
-    C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
-    out1 = __SMUAD(C2, R) >> 16u;
-    /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
-    out2 = __SMUSDX(C2, R);
-
-#else
-
-    /* xc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
-    out1 = __SMUSDX(R, C2) >> 16u;
-    /* yc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
-    out2 = __SMUAD(C2, R);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-    /*  Reading i0+fftLen/4 */
-    /* T = packed(yb, xb) */
-    T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
-    in = ((int16_t) (T & 0xFFFF)) >> 2;
-    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
-
-    /* writing the butterfly processed i0 + fftLen/4 sample */
-    /* writing output(xc', yc') in little endian format */
-    _SIMD32_OFFSET(pSrc16 + (2u * i1)) =
-      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
-    /*  Butterfly calculations */
-    /* U = packed(yd, xd) */
-    U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
-    in = ((int16_t) (U & 0xFFFF)) >> 2;
-    U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);
-
-    /* T = packed(yb-yd, xb-xd) */
-    T = __QSUB16(T, U);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
-    R = __QASX(S, T);
-    /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
-    S = __QSAX(S, T);
-
-#else
-
-    /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
-    R = __QSAX(S, T);
-    /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
-    S = __QASX(S, T);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-    /* co1 & si1 are read from SIMD Coefficient pointer */
-    C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
-    /*  Butterfly process for the i0+fftLen/2 sample */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
-    out1 = __SMUAD(C1, S) >> 16u;
-    /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
-    out2 = __SMUSDX(C1, S);
-
-#else
-
-    /* xb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
-    out1 = __SMUSDX(S, C1) >> 16u;
-    /* yb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
-    out2 = __SMUAD(C1, S);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-    /* writing output(xb', yb') in little endian format */
-    _SIMD32_OFFSET(pSrc16 + (2u * i2)) =
-      ((out2) & 0xFFFF0000) | ((out1) & 0x0000FFFF);
-
-
-    /* co3 & si3 are read from SIMD Coefficient pointer */
-    C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
-    /*  Butterfly process for the i0+3fftLen/4 sample */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
-    out1 = __SMUAD(C3, R) >> 16u;
-    /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
-    out2 = __SMUSDX(C3, R);
-
-#else
-
-    /* xd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
-    out1 = __SMUSDX(R, C3) >> 16u;
-    /* yd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
-    out2 = __SMUAD(C3, R);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-    /* writing output(xd', yd') in little endian format */
-    _SIMD32_OFFSET(pSrc16 + (2u * i3)) =
-      ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
-    /*  Twiddle coefficients index modifier */
-    ic = ic + twidCoefModifier;
-
-    /*  Updating input index */
-    i0 = i0 + 1u;
-
-  } while(--j);
-  /* data is in 4.11(q11) format */
-
-  /* end of first stage process */
-
-
-  /* start of middle stage process */
-
-  /*  Twiddle coefficients index modifier */
-  twidCoefModifier <<= 2u;
-
-  /*  Calculation of Middle stage */
-  for (k = fftLen / 4u; k > 4u; k >>= 2u)
-  {
-    /*  Initializations for the middle stage */
-    n1 = n2;
-    n2 >>= 2u;
-    ic = 0u;
-
-    for (j = 0u; j <= (n2 - 1u); j++)
-    {
-      /*  index calculation for the coefficients */
-      C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
-      C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
-      C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
-
-      /*  Twiddle coefficients index modifier */
-      ic = ic + twidCoefModifier;
-
-      /*  Butterfly implementation */
-      for (i0 = j; i0 < fftLen; i0 += n1)
-      {
-        /*  index calculation for the input as, */
-        /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
-        i1 = i0 + n2;
-        i2 = i1 + n2;
-        i3 = i2 + n2;
-
-        /*  Reading i0, i0+fftLen/2 inputs */
-        /* Read ya (real), xa(imag) input */
-        T = _SIMD32_OFFSET(pSrc16 + (2u * i0));
-
-        /* Read yc (real), xc(imag) input */
-        S = _SIMD32_OFFSET(pSrc16 + (2u * i2));
-
-        /* R = packed( (ya + yc), (xa + xc)) */
-        R = __QADD16(T, S);
-
-        /* S = packed((ya - yc), (xa - xc)) */
-        S = __QSUB16(T, S);
-
-        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
-        /* Read yb (real), xb(imag) input */
-        T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
-
-        /* Read yd (real), xd(imag) input */
-        U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
-
-        /* T = packed( (yb + yd), (xb + xd)) */
-        T = __QADD16(T, U);
-
-        /*  writing the butterfly processed i0 sample */
-
-        /* xa' = xa + xb + xc + xd */
-        /* ya' = ya + yb + yc + yd */
-        out1 = __SHADD16(R, T);
-        in = ((int16_t) (out1 & 0xFFFF)) >> 1;
-        out1 = ((out1 >> 1) & 0xFFFF0000) | (in & 0xFFFF);
-        _SIMD32_OFFSET(pSrc16 + (2u * i0)) = out1;
-
-        /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */
-        R = __SHSUB16(R, T);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
-        out1 = __SMUAD(C2, R) >> 16u;
-
-        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
-        out2 = __SMUSDX(C2, R);
-
-#else
-
-        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
-        out1 = __SMUSDX(R, C2) >> 16u;
-
-        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
-        out2 = __SMUAD(C2, R);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-        /*  Reading i0+3fftLen/4 */
-        /* Read yb (real), xb(imag) input */
-        T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
-
-        /*  writing the butterfly processed i0 + fftLen/4 sample */
-        /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
-        /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
-        _SIMD32_OFFSET(pSrc16 + (2u * i1)) =
-          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
-        /*  Butterfly calculations */
-
-        /* Read yd (real), xd(imag) input */
-        U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
-
-        /* T = packed(yb-yd, xb-xd) */
-        T = __QSUB16(T, U);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
-        R = __SHASX(S, T);
-
-        /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
-        S = __SHSAX(S, T);
-
-
-        /*  Butterfly process for the i0+fftLen/2 sample */
-        out1 = __SMUAD(C1, S) >> 16u;
-        out2 = __SMUSDX(C1, S);
-
-#else
-
-        /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
-        R = __SHSAX(S, T);
-
-        /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
-        S = __SHASX(S, T);
-
-
-        /*  Butterfly process for the i0+fftLen/2 sample */
-        out1 = __SMUSDX(S, C1) >> 16u;
-        out2 = __SMUAD(C1, S);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-        /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
-        /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
-        _SIMD32_OFFSET(pSrc16 + (2u * i2)) =
-          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
-        /*  Butterfly process for the i0+3fftLen/4 sample */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        out1 = __SMUAD(C3, R) >> 16u;
-        out2 = __SMUSDX(C3, R);
-
-#else
-
-        out1 = __SMUSDX(R, C3) >> 16u;
-        out2 = __SMUAD(C3, R);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-        /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
-        /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
-        _SIMD32_OFFSET(pSrc16 + (2u * i3)) =
-          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-      }
-    }
-    /*  Twiddle coefficients index modifier */
-    twidCoefModifier <<= 2u;
-  }
-  /* end of middle stage process */
-
-
-  /* data is in 10.6(q6) format for the 1024 point */
-  /* data is in 8.8(q8) format for the 256 point */
-  /* data is in 6.10(q10) format for the 64 point */
-  /* data is in 4.12(q12) format for the 16 point */
-
-  /*  Initializations for the last stage */
-  j = fftLen >> 2;
-
-  ptr1 = &pSrc16[0];
-
-  /* start of last stage process */
-
-  /*  Butterfly implementation */
-  do
-  {
-    /* Read xa (real), ya(imag) input */
-    xaya = *__SIMD32(ptr1)++;
-
-    /* Read xb (real), yb(imag) input */
-    xbyb = *__SIMD32(ptr1)++;
-
-    /* Read xc (real), yc(imag) input */
-    xcyc = *__SIMD32(ptr1)++;
-
-    /* Read xd (real), yd(imag) input */
-    xdyd = *__SIMD32(ptr1)++;
-
-    /* R = packed((ya + yc), (xa + xc)) */
-    R = __QADD16(xaya, xcyc);
-
-    /* T = packed((yb + yd), (xb + xd)) */
-    T = __QADD16(xbyb, xdyd);
-
-    /* pointer updation for writing */
-    ptr1 = ptr1 - 8u;
-
-
-    /* xa' = xa + xb + xc + xd */
-    /* ya' = ya + yb + yc + yd */
-    *__SIMD32(ptr1)++ = __SHADD16(R, T);
-
-    /* T = packed((yb + yd), (xb + xd)) */
-    T = __QADD16(xbyb, xdyd);
-
-    /* xc' = (xa-xb+xc-xd) */
-    /* yc' = (ya-yb+yc-yd) */
-    *__SIMD32(ptr1)++ = __SHSUB16(R, T);
-
-    /* S = packed((ya - yc), (xa - xc)) */
-    S = __QSUB16(xaya, xcyc);
-
-    /* Read yd (real), xd(imag) input */
-    /* T = packed( (yb - yd), (xb - xd))  */
-    U = __QSUB16(xbyb, xdyd);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    /* xb' = (xa+yb-xc-yd) */
-    /* yb' = (ya-xb-yc+xd) */
-    *__SIMD32(ptr1)++ = __SHSAX(S, U);
-
-
-    /* xd' = (xa-yb-xc+yd) */
-    /* yd' = (ya+xb-yc-xd) */
-    *__SIMD32(ptr1)++ = __SHASX(S, U);
-
-#else
-
-    /* xb' = (xa+yb-xc-yd) */
-    /* yb' = (ya-xb-yc+xd) */
-    *__SIMD32(ptr1)++ = __SHASX(S, U);
-
-
-    /* xd' = (xa-yb-xc+yd) */
-    /* yd' = (ya+xb-yc-xd) */
-    *__SIMD32(ptr1)++ = __SHSAX(S, U);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-  } while(--j);
-
-  /* end of last stage process */
-
-  /* output is in 11.5(q5) format for the 1024 point */
-  /* output is in 9.7(q7) format for the 256 point   */
-  /* output is in 7.9(q9) format for the 64 point  */
-  /* output is in 5.11(q11) format for the 16 point  */
-
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q15_t R0, R1, S0, S1, T0, T1, U0, U1;
-  q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2;
-  uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
-
-  /* Total process is divided into three stages */
-
-  /* process first stage, middle stages, & last stage */
-
-  /*  Initializations for the first stage */
-  n2 = fftLen;
-  n1 = n2;
-
-  /* n2 = fftLen/4 */
-  n2 >>= 2u;
-
-  /* Index for twiddle coefficient */
-  ic = 0u;
-
-  /* Index for input read and output write */
-  i0 = 0u;
-  j = n2;
-
-  /* Input is in 1.15(q15) format */
-
-  /*  start of first stage process */
-  do
-  {
-    /*  Butterfly implementation */
-
-    /*  index calculation for the input as, */
-    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
-    i1 = i0 + n2;
-    i2 = i1 + n2;
-    i3 = i2 + n2;
-
-    /*  Reading i0, i0+fftLen/2 inputs */
-
-    /* input is down scale by 4 to avoid overflow */
-    /* Read ya (real), xa(imag) input */
-    T0 = pSrc16[i0 * 2u] >> 2u;
-    T1 = pSrc16[(i0 * 2u) + 1u] >> 2u;
-
-    /* input is down scale by 4 to avoid overflow */
-    /* Read yc (real), xc(imag) input */
-    S0 = pSrc16[i2 * 2u] >> 2u;
-    S1 = pSrc16[(i2 * 2u) + 1u] >> 2u;
-
-    /* R0 = (ya + yc) */
-    R0 = __SSAT(T0 + S0, 16u);
-    /* R1 = (xa + xc) */
-    R1 = __SSAT(T1 + S1, 16u);
-
-    /* S0 = (ya - yc) */
-    S0 = __SSAT(T0 - S0, 16);
-    /* S1 = (xa - xc) */
-    S1 = __SSAT(T1 - S1, 16);
-
-    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
-    /* input is down scale by 4 to avoid overflow */
-    /* Read yb (real), xb(imag) input */
-    T0 = pSrc16[i1 * 2u] >> 2u;
-    T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
-
-    /* input is down scale by 4 to avoid overflow */
-    /* Read yd (real), xd(imag) input */
-    U0 = pSrc16[i3 * 2u] >> 2u;
-    U1 = pSrc16[(i3 * 2u) + 1] >> 2u;
-
-    /* T0 = (yb + yd) */
-    T0 = __SSAT(T0 + U0, 16u);
-    /* T1 = (xb + xd) */
-    T1 = __SSAT(T1 + U1, 16u);
-
-    /*  writing the butterfly processed i0 sample */
-    /* ya' = ya + yb + yc + yd */
-    /* xa' = xa + xb + xc + xd */
-    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
-    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
-
-    /* R0 = (ya + yc) - (yb + yd) */
-    /* R1 = (xa + xc) - (xb + xd) */
-    R0 = __SSAT(R0 - T0, 16u);
-    R1 = __SSAT(R1 - T1, 16u);
-
-    /* co2 & si2 are read from Coefficient pointer */
-    Co2 = pCoef16[2u * ic * 2u];
-    Si2 = pCoef16[(2u * ic * 2u) + 1];
-
-    /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
-    out1 = (short) ((Co2 * R0 + Si2 * R1) >> 16u);
-    /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
-    out2 = (short) ((-Si2 * R0 + Co2 * R1) >> 16u);
-
-    /*  Reading i0+fftLen/4 */
-    /* input is down scale by 4 to avoid overflow */
-    /* T0 = yb, T1 =  xb */
-    T0 = pSrc16[i1 * 2u] >> 2;
-    T1 = pSrc16[(i1 * 2u) + 1] >> 2;
-
-    /* writing the butterfly processed i0 + fftLen/4 sample */
-    /* writing output(xc', yc') in little endian format */
-    pSrc16[i1 * 2u] = out1;
-    pSrc16[(i1 * 2u) + 1] = out2;
-
-    /*  Butterfly calculations */
-    /* input is down scale by 4 to avoid overflow */
-    /* U0 = yd, U1 = xd */
-    U0 = pSrc16[i3 * 2u] >> 2;
-    U1 = pSrc16[(i3 * 2u) + 1] >> 2;
-    /* T0 = yb-yd */
-    T0 = __SSAT(T0 - U0, 16);
-    /* T1 = xb-xd */
-    T1 = __SSAT(T1 - U1, 16);
-
-    /* R1 = (ya-yc) + (xb- xd),  R0 = (xa-xc) - (yb-yd)) */
-    R0 = (short) __SSAT((q31_t) (S0 - T1), 16);
-    R1 = (short) __SSAT((q31_t) (S1 + T0), 16);
-
-    /* S1 = (ya-yc) - (xb- xd), S0 = (xa-xc) + (yb-yd)) */
-    S0 = (short) __SSAT(((q31_t) S0 + T1), 16u);
-    S1 = (short) __SSAT(((q31_t) S1 - T0), 16u);
-
-    /* co1 & si1 are read from Coefficient pointer */
-    Co1 = pCoef16[ic * 2u];
-    Si1 = pCoef16[(ic * 2u) + 1];
-    /*  Butterfly process for the i0+fftLen/2 sample */
-    /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
-    out1 = (short) ((Si1 * S1 + Co1 * S0) >> 16);
-    /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
-    out2 = (short) ((-Si1 * S0 + Co1 * S1) >> 16);
-
-    /* writing output(xb', yb') in little endian format */
-    pSrc16[i2 * 2u] = out1;
-    pSrc16[(i2 * 2u) + 1] = out2;
-
-    /* Co3 & si3 are read from Coefficient pointer */
-    Co3 = pCoef16[3u * (ic * 2u)];
-    Si3 = pCoef16[(3u * (ic * 2u)) + 1];
-    /*  Butterfly process for the i0+3fftLen/4 sample */
-    /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */
-    out1 = (short) ((Si3 * R1 + Co3 * R0) >> 16u);
-    /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */
-    out2 = (short) ((-Si3 * R0 + Co3 * R1) >> 16u);
-    /* writing output(xd', yd') in little endian format */
-    pSrc16[i3 * 2u] = out1;
-    pSrc16[(i3 * 2u) + 1] = out2;
-
-    /*  Twiddle coefficients index modifier */
-    ic = ic + twidCoefModifier;
-
-    /*  Updating input index */
-    i0 = i0 + 1u;
-
-  } while(--j);
-  /* data is in 4.11(q11) format */
-
-  /* end of first stage process */
-
-
-  /* start of middle stage process */
-
-  /*  Twiddle coefficients index modifier */
-  twidCoefModifier <<= 2u;
-
-  /*  Calculation of Middle stage */
-  for (k = fftLen / 4u; k > 4u; k >>= 2u)
-  {
-    /*  Initializations for the middle stage */
-    n1 = n2;
-    n2 >>= 2u;
-    ic = 0u;
-
-    for (j = 0u; j <= (n2 - 1u); j++)
-    {
-      /*  index calculation for the coefficients */
-      Co1 = pCoef16[ic * 2u];
-      Si1 = pCoef16[(ic * 2u) + 1u];
-      Co2 = pCoef16[2u * (ic * 2u)];
-      Si2 = pCoef16[(2u * (ic * 2u)) + 1u];
-      Co3 = pCoef16[3u * (ic * 2u)];
-      Si3 = pCoef16[(3u * (ic * 2u)) + 1u];
-
-      /*  Twiddle coefficients index modifier */
-      ic = ic + twidCoefModifier;
-
-      /*  Butterfly implementation */
-      for (i0 = j; i0 < fftLen; i0 += n1)
-      {
-        /*  index calculation for the input as, */
-        /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
-        i1 = i0 + n2;
-        i2 = i1 + n2;
-        i3 = i2 + n2;
-
-        /*  Reading i0, i0+fftLen/2 inputs */
-        /* Read ya (real), xa(imag) input */
-        T0 = pSrc16[i0 * 2u];
-        T1 = pSrc16[(i0 * 2u) + 1u];
-
-        /* Read yc (real), xc(imag) input */
-        S0 = pSrc16[i2 * 2u];
-        S1 = pSrc16[(i2 * 2u) + 1u];
-
-        /* R0 = (ya + yc), R1 = (xa + xc) */
-        R0 = __SSAT(T0 + S0, 16);
-        R1 = __SSAT(T1 + S1, 16);
-
-        /* S0 = (ya - yc), S1 =(xa - xc) */
-        S0 = __SSAT(T0 - S0, 16);
-        S1 = __SSAT(T1 - S1, 16);
-
-        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
-        /* Read yb (real), xb(imag) input */
-        T0 = pSrc16[i1 * 2u];
-        T1 = pSrc16[(i1 * 2u) + 1u];
-
-        /* Read yd (real), xd(imag) input */
-        U0 = pSrc16[i3 * 2u];
-        U1 = pSrc16[(i3 * 2u) + 1u];
-
-
-        /* T0 = (yb + yd), T1 = (xb + xd) */
-        T0 = __SSAT(T0 + U0, 16);
-        T1 = __SSAT(T1 + U1, 16);
-
-        /*  writing the butterfly processed i0 sample */
-
-        /* xa' = xa + xb + xc + xd */
-        /* ya' = ya + yb + yc + yd */
-        out1 = ((R0 >> 1u) + (T0 >> 1u)) >> 1u;
-        out2 = ((R1 >> 1u) + (T1 >> 1u)) >> 1u;
-
-        pSrc16[i0 * 2u] = out1;
-        pSrc16[(2u * i0) + 1u] = out2;
-
-        /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
-        R0 = (R0 >> 1u) - (T0 >> 1u);
-        R1 = (R1 >> 1u) - (T1 >> 1u);
-
-        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
-        out1 = (short) ((Co2 * R0 + Si2 * R1) >> 16u);
-
-        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
-        out2 = (short) ((-Si2 * R0 + Co2 * R1) >> 16u);
-
-        /*  Reading i0+3fftLen/4 */
-        /* Read yb (real), xb(imag) input */
-        T0 = pSrc16[i1 * 2u];
-        T1 = pSrc16[(i1 * 2u) + 1u];
-
-        /*  writing the butterfly processed i0 + fftLen/4 sample */
-        /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
-        /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
-        pSrc16[i1 * 2u] = out1;
-        pSrc16[(i1 * 2u) + 1u] = out2;
-
-        /*  Butterfly calculations */
-
-        /* Read yd (real), xd(imag) input */
-        U0 = pSrc16[i3 * 2u];
-        U1 = pSrc16[(i3 * 2u) + 1u];
-
-        /* T0 = yb-yd, T1 = xb-xd */
-        T0 = __SSAT(T0 - U0, 16);
-        T1 = __SSAT(T1 - U1, 16);
-
-        /* R0 = (ya-yc) + (xb- xd), R1 = (xa-xc) - (yb-yd)) */
-        R0 = (S0 >> 1u) - (T1 >> 1u);
-        R1 = (S1 >> 1u) + (T0 >> 1u);
-
-        /* S0 = (ya-yc) - (xb- xd), S1 = (xa-xc) + (yb-yd)) */
-        S0 = (S0 >> 1u) + (T1 >> 1u);
-        S1 = (S1 >> 1u) - (T0 >> 1u);
-
-        /*  Butterfly process for the i0+fftLen/2 sample */
-        out1 = (short) ((Co1 * S0 + Si1 * S1) >> 16u);
-
-        out2 = (short) ((-Si1 * S0 + Co1 * S1) >> 16u);
-
-        /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
-        /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
-        pSrc16[i2 * 2u] = out1;
-        pSrc16[(i2 * 2u) + 1u] = out2;
-
-        /*  Butterfly process for the i0+3fftLen/4 sample */
-        out1 = (short) ((Si3 * R1 + Co3 * R0) >> 16u);
-
-        out2 = (short) ((-Si3 * R0 + Co3 * R1) >> 16u);
-        /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */
-        /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */
-        pSrc16[i3 * 2u] = out1;
-        pSrc16[(i3 * 2u) + 1u] = out2;
-      }
-    }
-    /*  Twiddle coefficients index modifier */
-    twidCoefModifier <<= 2u;
-  }
-  /* end of middle stage process */
-
-
-  /* data is in 10.6(q6) format for the 1024 point */
-  /* data is in 8.8(q8) format for the 256 point */
-  /* data is in 6.10(q10) format for the 64 point */
-  /* data is in 4.12(q12) format for the 16 point */
-
-  /*  Initializations for the last stage */
-  n1 = n2;
-  n2 >>= 2u;
-
-  /* start of last stage process */
-
-  /*  Butterfly implementation */
-  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
-  {
-    /*  index calculation for the input as, */
-    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
-    i1 = i0 + n2;
-    i2 = i1 + n2;
-    i3 = i2 + n2;
-
-    /*  Reading i0, i0+fftLen/2 inputs */
-    /* Read ya (real), xa(imag) input */
-    T0 = pSrc16[i0 * 2u];
-    T1 = pSrc16[(i0 * 2u) + 1u];
-
-    /* Read yc (real), xc(imag) input */
-    S0 = pSrc16[i2 * 2u];
-    S1 = pSrc16[(i2 * 2u) + 1u];
-
-    /* R0 = (ya + yc), R1 = (xa + xc) */
-    R0 = __SSAT(T0 + S0, 16u);
-    R1 = __SSAT(T1 + S1, 16u);
-
-    /* S0 = (ya - yc), S1 = (xa - xc) */
-    S0 = __SSAT(T0 - S0, 16u);
-    S1 = __SSAT(T1 - S1, 16u);
-
-    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
-    /* Read yb (real), xb(imag) input */
-    T0 = pSrc16[i1 * 2u];
-    T1 = pSrc16[(i1 * 2u) + 1u];
-    /* Read yd (real), xd(imag) input */
-    U0 = pSrc16[i3 * 2u];
-    U1 = pSrc16[(i3 * 2u) + 1u];
-
-    /* T0 = (yb + yd), T1 = (xb + xd)) */
-    T0 = __SSAT(T0 + U0, 16u);
-    T1 = __SSAT(T1 + U1, 16u);
-
-    /*  writing the butterfly processed i0 sample */
-    /* xa' = xa + xb + xc + xd */
-    /* ya' = ya + yb + yc + yd */
-    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
-    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
-
-    /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
-    R0 = (R0 >> 1u) - (T0 >> 1u);
-    R1 = (R1 >> 1u) - (T1 >> 1u);
-    /* Read yb (real), xb(imag) input */
-    T0 = pSrc16[i1 * 2u];
-    T1 = pSrc16[(i1 * 2u) + 1u];
-
-    /*  writing the butterfly processed i0 + fftLen/4 sample */
-    /* xc' = (xa-xb+xc-xd) */
-    /* yc' = (ya-yb+yc-yd) */
-    pSrc16[i1 * 2u] = R0;
-    pSrc16[(i1 * 2u) + 1u] = R1;
-
-    /* Read yd (real), xd(imag) input */
-    U0 = pSrc16[i3 * 2u];
-    U1 = pSrc16[(i3 * 2u) + 1u];
-    /* T0 = (yb - yd), T1 = (xb - xd)  */
-    T0 = __SSAT(T0 - U0, 16u);
-    T1 = __SSAT(T1 - U1, 16u);
-
-    /*  writing the butterfly processed i0 + fftLen/2 sample */
-    /* xb' = (xa+yb-xc-yd) */
-    /* yb' = (ya-xb-yc+xd) */
-    pSrc16[i2 * 2u] = (S0 >> 1u) + (T1 >> 1u);
-    pSrc16[(i2 * 2u) + 1u] = (S1 >> 1u) - (T0 >> 1u);
-
-    /*  writing the butterfly processed i0 + 3fftLen/4 sample */
-    /* xd' = (xa-yb-xc+yd) */
-    /* yd' = (ya+xb-yc-xd) */
-    pSrc16[i3 * 2u] = (S0 >> 1u) - (T1 >> 1u);
-    pSrc16[(i3 * 2u) + 1u] = (S1 >> 1u) + (T0 >> 1u);
-
-  }
-
-  /* end of last stage process */
-
-  /* output is in 11.5(q5) format for the 1024 point */
-  /* output is in 9.7(q7) format for the 256 point   */
-  /* output is in 7.9(q9) format for the 64 point  */
-  /* output is in 5.11(q11) format for the 16 point  */
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-}
-
-
-/**    
- * @brief  Core function for the Q15 CIFFT butterfly process.   
- * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.   
- * @param[in]      fftLen           length of the FFT.   
- * @param[in]      *pCoef16         points to twiddle coefficient buffer.   
- * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
- * @return none.   
- */
-
-/*    
-* Radix-4 IFFT algorithm used is :    
-*    
-* CIFFT uses same twiddle coefficients as CFFT function    
-*  x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4]    
-*    
-*    
-* IFFT is implemented with following changes in equations from FFT    
-*    
-* Input real and imaginary data:    
-* x(n) = xa + j * ya    
-* x(n+N/4 ) = xb + j * yb    
-* x(n+N/2 ) = xc + j * yc    
-* x(n+3N 4) = xd + j * yd    
-*    
-*    
-* Output real and imaginary data:    
-* x(4r) = xa'+ j * ya'    
-* x(4r+1) = xb'+ j * yb'    
-* x(4r+2) = xc'+ j * yc'    
-* x(4r+3) = xd'+ j * yd'    
-*    
-*    
-* Twiddle factors for radix-4 IFFT:    
-* Wn = co1 + j * (si1)    
-* W2n = co2 + j * (si2)    
-* W3n = co3 + j * (si3)    
-    
-* The real and imaginary output values for the radix-4 butterfly are    
-* xa' = xa + xb + xc + xd    
-* ya' = ya + yb + yc + yd    
-* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)    
-* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)    
-* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)    
-* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)    
-* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)    
-* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)    
-*    
-*/
-
-void arm_radix4_butterfly_inverse_q15(
-  q15_t * pSrc16,
-  uint32_t fftLen,
-  q15_t * pCoef16,
-  uint32_t twidCoefModifier)
-{
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  q31_t R, S, T, U;
-  q31_t C1, C2, C3, out1, out2;
-  uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
-  q15_t in;
-
-  q15_t *ptr1;
-
-
-
-  q31_t xaya, xbyb, xcyc, xdyd;
-
-  /* Total process is divided into three stages */
-
-  /* process first stage, middle stages, & last stage */
-
-  /*  Initializations for the first stage */
-  n2 = fftLen;
-  n1 = n2;
-
-  /* n2 = fftLen/4 */
-  n2 >>= 2u;
-
-  /* Index for twiddle coefficient */
-  ic = 0u;
-
-  /* Index for input read and output write */
-  i0 = 0u;
-  j = n2;
-
-  /* Input is in 1.15(q15) format */
-
-  /*  start of first stage process */
-  do
-  {
-    /*  Butterfly implementation */
-
-    /*  index calculation for the input as, */
-    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
-    i1 = i0 + n2;
-    i2 = i1 + n2;
-    i3 = i2 + n2;
-
-    /*  Reading i0, i0+fftLen/2 inputs */
-    /* Read ya (real), xa(imag) input */
-    T = _SIMD32_OFFSET(pSrc16 + (2u * i0));
-    in = ((int16_t) (T & 0xFFFF)) >> 2;
-    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
-
-    /* Read yc (real), xc(imag) input */
-    S = _SIMD32_OFFSET(pSrc16 + (2u * i2));
-    in = ((int16_t) (S & 0xFFFF)) >> 2;
-    S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);
-
-    /* R = packed((ya + yc), (xa + xc) ) */
-    R = __QADD16(T, S);
-
-    /* S = packed((ya - yc), (xa - xc) ) */
-    S = __QSUB16(T, S);
-
-    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
-    /* Read yb (real), xb(imag) input */
-    T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
-    in = ((int16_t) (T & 0xFFFF)) >> 2;
-    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
-
-    /* Read yd (real), xd(imag) input */
-    U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
-    in = ((int16_t) (U & 0xFFFF)) >> 2;
-    U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);
-
-    /* T = packed((yb + yd), (xb + xd) ) */
-    T = __QADD16(T, U);
-
-    /*  writing the butterfly processed i0 sample */
-    /* xa' = xa + xb + xc + xd */
-    /* ya' = ya + yb + yc + yd */
-    _SIMD32_OFFSET(pSrc16 + (2u * i0)) = __SHADD16(R, T);
-
-    /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */
-    R = __QSUB16(R, T);
-
-    /* co2 & si2 are read from SIMD Coefficient pointer */
-    C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
-    out1 = __SMUSD(C2, R) >> 16u;
-    /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
-    out2 = __SMUADX(C2, R);
-
-#else
-
-    /* xc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
-    out1 = __SMUADX(C2, R) >> 16u;
-    /* yc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
-    out2 = __SMUSD(__QSUB16(0, C2), R);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-    /*  Reading i0+fftLen/4 */
-    /* T = packed(yb, xb) */
-    T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
-    in = ((int16_t) (T & 0xFFFF)) >> 2;
-    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
-
-    /* writing the butterfly processed i0 + fftLen/4 sample */
-    /* writing output(xc', yc') in little endian format */
-    _SIMD32_OFFSET(pSrc16 + (2u * i1)) =
-      (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
-    /*  Butterfly calculations */
-    /* U = packed(yd, xd) */
-    U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
-    in = ((int16_t) (U & 0xFFFF)) >> 2;
-    U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);
-
-    /* T = packed(yb-yd, xb-xd) */
-    T = __QSUB16(T, U);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
-    R = __QSAX(S, T);
-    /* S = packed((ya-yc) + (xb- xd),  (xa-xc) - (yb-yd)) */
-    S = __QASX(S, T);
-
-#else
-
-    /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
-    R = __QASX(S, T);
-    /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
-    S = __QSAX(S, T);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-    /* co1 & si1 are read from SIMD Coefficient pointer */
-    C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
-    /*  Butterfly process for the i0+fftLen/2 sample */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
-    out1 = __SMUSD(C1, S) >> 16u;
-    /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
-    out2 = __SMUADX(C1, S);
-
-#else
-
-    /* xb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
-    out1 = __SMUADX(C1, S) >> 16u;
-    /* yb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
-    out2 = __SMUSD(__QSUB16(0, C1), S);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-    /* writing output(xb', yb') in little endian format */
-    _SIMD32_OFFSET(pSrc16 + (2u * i2)) =
-      ((out2) & 0xFFFF0000) | ((out1) & 0x0000FFFF);
-
-
-    /* co3 & si3 are read from SIMD Coefficient pointer */
-    C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
-    /*  Butterfly process for the i0+3fftLen/4 sample */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
-    out1 = __SMUSD(C3, R) >> 16u;
-    /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
-    out2 = __SMUADX(C3, R);
-
-#else
-
-    /* xd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
-    out1 = __SMUADX(C3, R) >> 16u;
-    /* yd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
-    out2 = __SMUSD(__QSUB16(0, C3), R);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-    /* writing output(xd', yd') in little endian format */
-    _SIMD32_OFFSET(pSrc16 + (2u * i3)) =
-      ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
-    /*  Twiddle coefficients index modifier */
-    ic = ic + twidCoefModifier;
-
-    /*  Updating input index */
-    i0 = i0 + 1u;
-
-  } while(--j);
-  /* data is in 4.11(q11) format */
-
-  /* end of first stage process */
-
-
-  /* start of middle stage process */
-
-  /*  Twiddle coefficients index modifier */
-  twidCoefModifier <<= 2u;
-
-  /*  Calculation of Middle stage */
-  for (k = fftLen / 4u; k > 4u; k >>= 2u)
-  {
-    /*  Initializations for the middle stage */
-    n1 = n2;
-    n2 >>= 2u;
-    ic = 0u;
-
-    for (j = 0u; j <= (n2 - 1u); j++)
-    {
-      /*  index calculation for the coefficients */
-      C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
-      C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
-      C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
-
-      /*  Twiddle coefficients index modifier */
-      ic = ic + twidCoefModifier;
-
-      /*  Butterfly implementation */
-      for (i0 = j; i0 < fftLen; i0 += n1)
-      {
-        /*  index calculation for the input as, */
-        /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
-        i1 = i0 + n2;
-        i2 = i1 + n2;
-        i3 = i2 + n2;
-
-        /*  Reading i0, i0+fftLen/2 inputs */
-        /* Read ya (real), xa(imag) input */
-        T = _SIMD32_OFFSET(pSrc16 + (2u * i0));
-
-        /* Read yc (real), xc(imag) input */
-        S = _SIMD32_OFFSET(pSrc16 + (2u * i2));
-
-        /* R = packed( (ya + yc), (xa + xc)) */
-        R = __QADD16(T, S);
-
-        /* S = packed((ya - yc), (xa - xc)) */
-        S = __QSUB16(T, S);
-
-        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
-        /* Read yb (real), xb(imag) input */
-        T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
-
-        /* Read yd (real), xd(imag) input */
-        U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
-
-        /* T = packed( (yb + yd), (xb + xd)) */
-        T = __QADD16(T, U);
-
-        /*  writing the butterfly processed i0 sample */
-
-        /* xa' = xa + xb + xc + xd */
-        /* ya' = ya + yb + yc + yd */
-        out1 = __SHADD16(R, T);
-        in = ((int16_t) (out1 & 0xFFFF)) >> 1;
-        out1 = ((out1 >> 1) & 0xFFFF0000) | (in & 0xFFFF);
-        _SIMD32_OFFSET(pSrc16 + (2u * i0)) = out1;
-
-        /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */
-        R = __SHSUB16(R, T);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
-        out1 = __SMUSD(C2, R) >> 16u;
-
-        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
-        out2 = __SMUADX(C2, R);
-
-#else
-
-        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
-        out1 = __SMUADX(R, C2) >> 16u;
-
-        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
-        out2 = __SMUSD(__QSUB16(0, C2), R);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-        /*  Reading i0+3fftLen/4 */
-        /* Read yb (real), xb(imag) input */
-        T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
-
-        /*  writing the butterfly processed i0 + fftLen/4 sample */
-        /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
-        /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
-        _SIMD32_OFFSET(pSrc16 + (2u * i1)) =
-          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
-        /*  Butterfly calculations */
-
-        /* Read yd (real), xd(imag) input */
-        U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
-
-        /* T = packed(yb-yd, xb-xd) */
-        T = __QSUB16(T, U);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
-        R = __SHSAX(S, T);
-
-        /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
-        S = __SHASX(S, T);
-
-
-        /*  Butterfly process for the i0+fftLen/2 sample */
-        out1 = __SMUSD(C1, S) >> 16u;
-        out2 = __SMUADX(C1, S);
-
-#else
-
-        /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
-        R = __SHASX(S, T);
-
-        /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
-        S = __SHSAX(S, T);
-
-
-        /*  Butterfly process for the i0+fftLen/2 sample */
-        out1 = __SMUADX(S, C1) >> 16u;
-        out2 = __SMUSD(__QSUB16(0, C1), S);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-        /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
-        /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
-        _SIMD32_OFFSET(pSrc16 + (2u * i2)) =
-          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-
-        /*  Butterfly process for the i0+3fftLen/4 sample */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-        out1 = __SMUSD(C3, R) >> 16u;
-        out2 = __SMUADX(C3, R);
-
-#else
-
-        out1 = __SMUADX(C3, R) >> 16u;
-        out2 = __SMUSD(__QSUB16(0, C3), R);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-        /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
-        /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
-        _SIMD32_OFFSET(pSrc16 + (2u * i3)) =
-          ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
-      }
-    }
-    /*  Twiddle coefficients index modifier */
-    twidCoefModifier <<= 2u;
-  }
-  /* end of middle stage process */
-
-  /* data is in 10.6(q6) format for the 1024 point */
-  /* data is in 8.8(q8) format for the 256 point */
-  /* data is in 6.10(q10) format for the 64 point */
-  /* data is in 4.12(q12) format for the 16 point */
-
-  /*  Initializations for the last stage */
-  j = fftLen >> 2;
-
-  ptr1 = &pSrc16[0];
-
-  /* start of last stage process */
-
-  /*  Butterfly implementation */
-  do
-  {
-    /* Read xa (real), ya(imag) input */
-    xaya = *__SIMD32(ptr1)++;
-
-    /* Read xb (real), yb(imag) input */
-    xbyb = *__SIMD32(ptr1)++;
-
-    /* Read xc (real), yc(imag) input */
-    xcyc = *__SIMD32(ptr1)++;
-
-    /* Read xd (real), yd(imag) input */
-    xdyd = *__SIMD32(ptr1)++;
-
-    /* R = packed((ya + yc), (xa + xc)) */
-    R = __QADD16(xaya, xcyc);
-
-    /* T = packed((yb + yd), (xb + xd)) */
-    T = __QADD16(xbyb, xdyd);
-
-    /* pointer updation for writing */
-    ptr1 = ptr1 - 8u;
-
-
-    /* xa' = xa + xb + xc + xd */
-    /* ya' = ya + yb + yc + yd */
-    *__SIMD32(ptr1)++ = __SHADD16(R, T);
-
-    /* T = packed((yb + yd), (xb + xd)) */
-    T = __QADD16(xbyb, xdyd);
-
-    /* xc' = (xa-xb+xc-xd) */
-    /* yc' = (ya-yb+yc-yd) */
-    *__SIMD32(ptr1)++ = __SHSUB16(R, T);
-
-    /* S = packed((ya - yc), (xa - xc)) */
-    S = __QSUB16(xaya, xcyc);
-
-    /* Read yd (real), xd(imag) input */
-    /* T = packed( (yb - yd), (xb - xd))  */
-    U = __QSUB16(xbyb, xdyd);
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    /* xb' = (xa+yb-xc-yd) */
-    /* yb' = (ya-xb-yc+xd) */
-    *__SIMD32(ptr1)++ = __SHASX(S, U);
-
-
-    /* xd' = (xa-yb-xc+yd) */
-    /* yd' = (ya+xb-yc-xd) */
-    *__SIMD32(ptr1)++ = __SHSAX(S, U);
-
-#else
-
-    /* xb' = (xa+yb-xc-yd) */
-    /* yb' = (ya-xb-yc+xd) */
-    *__SIMD32(ptr1)++ = __SHSAX(S, U);
-
-
-    /* xd' = (xa-yb-xc+yd) */
-    /* yd' = (ya+xb-yc-xd) */
-    *__SIMD32(ptr1)++ = __SHASX(S, U);
-
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-  } while(--j);
-
-  /* end of last stage  process */
-
-  /* output is in 11.5(q5) format for the 1024 point */
-  /* output is in 9.7(q7) format for the 256 point   */
-  /* output is in 7.9(q9) format for the 64 point  */
-  /* output is in 5.11(q11) format for the 16 point  */
-
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  q15_t R0, R1, S0, S1, T0, T1, U0, U1;
-  q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2;
-  uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
-
-  /* Total process is divided into three stages */
-
-  /* process first stage, middle stages, & last stage */
-
-  /*  Initializations for the first stage */
-  n2 = fftLen;
-  n1 = n2;
-
-  /* n2 = fftLen/4 */
-  n2 >>= 2u;
-
-  /* Index for twiddle coefficient */
-  ic = 0u;
-
-  /* Index for input read and output write */
-  i0 = 0u;
-
-  j = n2;
-
-  /* Input is in 1.15(q15) format */
-
-  /*  Start of first stage process */
-  do
-  {
-    /*  Butterfly implementation */
-
-    /*  index calculation for the input as, */
-    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
-    i1 = i0 + n2;
-    i2 = i1 + n2;
-    i3 = i2 + n2;
-
-    /*  Reading i0, i0+fftLen/2 inputs */
-    /* input is down scale by 4 to avoid overflow */
-    /* Read ya (real), xa(imag) input */
-    T0 = pSrc16[i0 * 2u] >> 2u;
-    T1 = pSrc16[(i0 * 2u) + 1u] >> 2u;
-    /* input is down scale by 4 to avoid overflow */
-    /* Read yc (real), xc(imag) input */
-    S0 = pSrc16[i2 * 2u] >> 2u;
-    S1 = pSrc16[(i2 * 2u) + 1u] >> 2u;
-
-    /* R0 = (ya + yc), R1 = (xa + xc) */
-    R0 = __SSAT(T0 + S0, 16u);
-    R1 = __SSAT(T1 + S1, 16u);
-    /* S0 = (ya - yc), S1 = (xa - xc) */
-    S0 = __SSAT(T0 - S0, 16u);
-    S1 = __SSAT(T1 - S1, 16u);
-
-    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
-    /* input is down scale by 4 to avoid overflow */
-    /* Read yb (real), xb(imag) input */
-    T0 = pSrc16[i1 * 2u] >> 2u;
-    T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
-    /* Read yd (real), xd(imag) input */
-    /* input is down scale by 4 to avoid overflow */
-    U0 = pSrc16[i3 * 2u] >> 2u;
-    U1 = pSrc16[(i3 * 2u) + 1u] >> 2u;
-
-    /* T0 = (yb + yd), T1 = (xb + xd) */
-    T0 = __SSAT(T0 + U0, 16u);
-    T1 = __SSAT(T1 + U1, 16u);
-
-    /*  writing the butterfly processed i0 sample */
-    /* xa' = xa + xb + xc + xd */
-    /* ya' = ya + yb + yc + yd */
-    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
-    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
-
-    /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc)- (xb + xd) */
-    R0 = __SSAT(R0 - T0, 16u);
-    R1 = __SSAT(R1 - T1, 16u);
-    /* co2 & si2 are read from Coefficient pointer */
-    Co2 = pCoef16[2u * ic * 2u];
-    Si2 = pCoef16[(2u * ic * 2u) + 1u];
-    /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
-    out1 = (short) ((Co2 * R0 - Si2 * R1) >> 16u);
-    /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
-    out2 = (short) ((Si2 * R0 + Co2 * R1) >> 16u);
-
-    /*  Reading i0+fftLen/4 */
-    /* input is down scale by 4 to avoid overflow */
-    /* T0 = yb, T1 = xb */
-    T0 = pSrc16[i1 * 2u] >> 2u;
-    T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
-
-    /* writing the butterfly processed i0 + fftLen/4 sample */
-    /* writing output(xc', yc') in little endian format */
-    pSrc16[i1 * 2u] = out1;
-    pSrc16[(i1 * 2u) + 1u] = out2;
-
-    /*  Butterfly calculations */
-    /* input is down scale by 4 to avoid overflow */
-    /* U0 = yd, U1 = xd) */
-    U0 = pSrc16[i3 * 2u] >> 2u;
-    U1 = pSrc16[(i3 * 2u) + 1u] >> 2u;
-
-    /* T0 = yb-yd, T1 = xb-xd) */
-    T0 = __SSAT(T0 - U0, 16u);
-    T1 = __SSAT(T1 - U1, 16u);
-    /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */
-    R0 = (short) __SSAT((q31_t) (S0 + T1), 16);
-    R1 = (short) __SSAT((q31_t) (S1 - T0), 16);
-    /* S = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */
-    S0 = (short) __SSAT((q31_t) (S0 - T1), 16);
-    S1 = (short) __SSAT((q31_t) (S1 + T0), 16);
-
-    /* co1 & si1 are read from Coefficient pointer */
-    Co1 = pCoef16[ic * 2u];
-    Si1 = pCoef16[(ic * 2u) + 1u];
-    /*  Butterfly process for the i0+fftLen/2 sample */
-    /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
-    out1 = (short) ((Co1 * S0 - Si1 * S1) >> 16u);
-    /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
-    out2 = (short) ((Si1 * S0 + Co1 * S1) >> 16u);
-    /* writing output(xb', yb') in little endian format */
-    pSrc16[i2 * 2u] = out1;
-    pSrc16[(i2 * 2u) + 1u] = out2;
-
-    /* Co3 & si3 are read from Coefficient pointer */
-    Co3 = pCoef16[3u * ic * 2u];
-    Si3 = pCoef16[(3u * ic * 2u) + 1u];
-    /*  Butterfly process for the i0+3fftLen/4 sample */
-    /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */
-    out1 = (short) ((Co3 * R0 - Si3 * R1) >> 16u);
-    /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */
-    out2 = (short) ((Si3 * R0 + Co3 * R1) >> 16u);
-    /* writing output(xd', yd') in little endian format */
-    pSrc16[i3 * 2u] = out1;
-    pSrc16[(i3 * 2u) + 1u] = out2;
-
-    /*  Twiddle coefficients index modifier */
-    ic = ic + twidCoefModifier;
-
-    /*  Updating input index */
-    i0 = i0 + 1u;
-
-  } while(--j);
-
-  /*  End of first stage process */
-
-  /* data is in 4.11(q11) format */
-
-
-  /*  Start of Middle stage process */
-
-  /*  Twiddle coefficients index modifier */
-  twidCoefModifier <<= 2u;
-
-  /*  Calculation of Middle stage */
-  for (k = fftLen / 4u; k > 4u; k >>= 2u)
-  {
-    /*  Initializations for the middle stage */
-    n1 = n2;
-    n2 >>= 2u;
-    ic = 0u;
-
-    for (j = 0u; j <= (n2 - 1u); j++)
-    {
-      /*  index calculation for the coefficients */
-      Co1 = pCoef16[ic * 2u];
-      Si1 = pCoef16[(ic * 2u) + 1u];
-      Co2 = pCoef16[2u * ic * 2u];
-      Si2 = pCoef16[2u * ic * 2u + 1u];
-      Co3 = pCoef16[3u * ic * 2u];
-      Si3 = pCoef16[(3u * ic * 2u) + 1u];
-
-      /*  Twiddle coefficients index modifier */
-      ic = ic + twidCoefModifier;
-
-      /*  Butterfly implementation */
-      for (i0 = j; i0 < fftLen; i0 += n1)
-      {
-        /*  index calculation for the input as, */
-        /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
-        i1 = i0 + n2;
-        i2 = i1 + n2;
-        i3 = i2 + n2;
-
-        /*  Reading i0, i0+fftLen/2 inputs */
-        /* Read ya (real), xa(imag) input */
-        T0 = pSrc16[i0 * 2u];
-        T1 = pSrc16[(i0 * 2u) + 1u];
-
-        /* Read yc (real), xc(imag) input */
-        S0 = pSrc16[i2 * 2u];
-        S1 = pSrc16[(i2 * 2u) + 1u];
-
-
-        /* R0 = (ya + yc), R1 = (xa + xc) */
-        R0 = __SSAT(T0 + S0, 16u);
-        R1 = __SSAT(T1 + S1, 16u);
-        /* S0 = (ya - yc), S1 = (xa - xc) */
-        S0 = __SSAT(T0 - S0, 16u);
-        S1 = __SSAT(T1 - S1, 16u);
-
-        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
-        /* Read yb (real), xb(imag) input */
-        T0 = pSrc16[i1 * 2u];
-        T1 = pSrc16[(i1 * 2u) + 1u];
-
-        /* Read yd (real), xd(imag) input */
-        U0 = pSrc16[i3 * 2u];
-        U1 = pSrc16[(i3 * 2u) + 1u];
-
-        /* T0 = (yb + yd), T1 = (xb + xd) */
-        T0 = __SSAT(T0 + U0, 16u);
-        T1 = __SSAT(T1 + U1, 16u);
-
-        /*  writing the butterfly processed i0 sample */
-        /* xa' = xa + xb + xc + xd */
-        /* ya' = ya + yb + yc + yd */
-        pSrc16[i0 * 2u] = ((R0 >> 1u) + (T0 >> 1u)) >> 1u;
-        pSrc16[(i0 * 2u) + 1u] = ((R1 >> 1u) + (T1 >> 1u)) >> 1u;
-
-        /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
-        R0 = (R0 >> 1u) - (T0 >> 1u);
-        R1 = (R1 >> 1u) - (T1 >> 1u);
-
-        /* (ya-yb+yc-yd)* (si2) - (xa-xb+xc-xd)* co2 */
-        out1 = (short) ((Co2 * R0 - Si2 * R1) >> 16);
-        /* (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
-        out2 = (short) ((Si2 * R0 + Co2 * R1) >> 16);
-
-        /*  Reading i0+3fftLen/4 */
-        /* Read yb (real), xb(imag) input */
-        T0 = pSrc16[i1 * 2u];
-        T1 = pSrc16[(i1 * 2u) + 1u];
-
-        /*  writing the butterfly processed i0 + fftLen/4 sample */
-        /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
-        /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
-        pSrc16[i1 * 2u] = out1;
-        pSrc16[(i1 * 2u) + 1u] = out2;
-
-        /*  Butterfly calculations */
-        /* Read yd (real), xd(imag) input */
-        U0 = pSrc16[i3 * 2u];
-        U1 = pSrc16[(i3 * 2u) + 1u];
-
-        /* T0 = yb-yd, T1 = xb-xd) */
-        T0 = __SSAT(T0 - U0, 16u);
-        T1 = __SSAT(T1 - U1, 16u);
-
-        /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */
-        R0 = (S0 >> 1u) + (T1 >> 1u);
-        R1 = (S1 >> 1u) - (T0 >> 1u);
-
-        /* S1 = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */
-        S0 = (S0 >> 1u) - (T1 >> 1u);
-        S1 = (S1 >> 1u) + (T0 >> 1u);
-
-        /*  Butterfly process for the i0+fftLen/2 sample */
-        out1 = (short) ((Co1 * S0 - Si1 * S1) >> 16u);
-        out2 = (short) ((Si1 * S0 + Co1 * S1) >> 16u);
-        /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
-        /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
-        pSrc16[i2 * 2u] = out1;
-        pSrc16[(i2 * 2u) + 1u] = out2;
-
-        /*  Butterfly process for the i0+3fftLen/4 sample */
-        out1 = (short) ((Co3 * R0 - Si3 * R1) >> 16u);
-
-        out2 = (short) ((Si3 * R0 + Co3 * R1) >> 16u);
-        /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */
-        /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */
-        pSrc16[i3 * 2u] = out1;
-        pSrc16[(i3 * 2u) + 1u] = out2;
-
-
-      }
-    }
-    /*  Twiddle coefficients index modifier */
-    twidCoefModifier <<= 2u;
-  }
-  /*  End of Middle stages process */
-
-
-  /* data is in 10.6(q6) format for the 1024 point */
-  /* data is in 8.8(q8) format for the 256 point   */
-  /* data is in 6.10(q10) format for the 64 point  */
-  /* data is in 4.12(q12) format for the 16 point  */
-
-  /* start of last stage process */
-
-
-  /*  Initializations for the last stage */
-  n1 = n2;
-  n2 >>= 2u;
-
-  /*  Butterfly implementation */
-  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
-  {
-    /*  index calculation for the input as, */
-    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
-    i1 = i0 + n2;
-    i2 = i1 + n2;
-    i3 = i2 + n2;
-
-    /*  Reading i0, i0+fftLen/2 inputs */
-    /* Read ya (real), xa(imag) input */
-    T0 = pSrc16[i0 * 2u];
-    T1 = pSrc16[(i0 * 2u) + 1u];
-    /* Read yc (real), xc(imag) input */
-    S0 = pSrc16[i2 * 2u];
-    S1 = pSrc16[(i2 * 2u) + 1u];
-
-    /* R0 = (ya + yc), R1 = (xa + xc) */
-    R0 = __SSAT(T0 + S0, 16u);
-    R1 = __SSAT(T1 + S1, 16u);
-    /* S0 = (ya - yc), S1 = (xa - xc) */
-    S0 = __SSAT(T0 - S0, 16u);
-    S1 = __SSAT(T1 - S1, 16u);
-
-    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
-    /* Read yb (real), xb(imag) input */
-    T0 = pSrc16[i1 * 2u];
-    T1 = pSrc16[(i1 * 2u) + 1u];
-    /* Read yd (real), xd(imag) input */
-    U0 = pSrc16[i3 * 2u];
-    U1 = pSrc16[(i3 * 2u) + 1u];
-
-    /* T0 = (yb + yd), T1 = (xb + xd) */
-    T0 = __SSAT(T0 + U0, 16u);
-    T1 = __SSAT(T1 + U1, 16u);
-
-    /*  writing the butterfly processed i0 sample */
-    /* xa' = xa + xb + xc + xd */
-    /* ya' = ya + yb + yc + yd */
-    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
-    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
-
-    /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
-    R0 = (R0 >> 1u) - (T0 >> 1u);
-    R1 = (R1 >> 1u) - (T1 >> 1u);
-
-    /* Read yb (real), xb(imag) input */
-    T0 = pSrc16[i1 * 2u];
-    T1 = pSrc16[(i1 * 2u) + 1u];
-
-    /*  writing the butterfly processed i0 + fftLen/4 sample */
-    /* xc' = (xa-xb+xc-xd) */
-    /* yc' = (ya-yb+yc-yd) */
-    pSrc16[i1 * 2u] = R0;
-    pSrc16[(i1 * 2u) + 1u] = R1;
-
-    /* Read yd (real), xd(imag) input */
-    U0 = pSrc16[i3 * 2u];
-    U1 = pSrc16[(i3 * 2u) + 1u];
-    /* T0 = (yb - yd), T1 = (xb - xd) */
-    T0 = __SSAT(T0 - U0, 16u);
-    T1 = __SSAT(T1 - U1, 16u);
-
-    /*  writing the butterfly processed i0 + fftLen/2 sample */
-    /* xb' = (xa-yb-xc+yd) */
-    /* yb' = (ya+xb-yc-xd) */
-    pSrc16[i2 * 2u] = (S0 >> 1u) - (T1 >> 1u);
-    pSrc16[(i2 * 2u) + 1u] = (S1 >> 1u) + (T0 >> 1u);
-
-
-    /*  writing the butterfly processed i0 + 3fftLen/4 sample */
-    /* xd' = (xa+yb-xc-yd) */
-    /* yd' = (ya-xb-yc+xd) */
-    pSrc16[i3 * 2u] = (S0 >> 1u) + (T1 >> 1u);
-    pSrc16[(i3 * 2u) + 1u] = (S1 >> 1u) - (T0 >> 1u);
-  }
-  /* end of last stage  process */
-
-  /* output is in 11.5(q5) format for the 1024 point */
-  /* output is in 9.7(q7) format for the 256 point   */
-  /* output is in 7.9(q9) format for the 64 point  */
-  /* output is in 5.11(q11) format for the 16 point  */
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-}
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q31.c
deleted file mode 100644
index cfa5d8df0e..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q31.c
+++ /dev/null
@@ -1,891 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_cfft_radix4_q31.c    
-*    
-* Description:	This file has function definition of Radix-4 FFT & IFFT function and    
-*				In-place bit reversal using bit reversal table    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.5  2010/04/26     
-* 	 incorporated review comments and updated with latest CMSIS layer    
-*    
-* Version 0.0.3  2010/03/10     
-*    Initial version    
-* -------------------------------------------------------------------- */
-#include "arm_math.h"
-
-
-/**    
- * @ingroup groupTransforms    
- */
-
-/**    
- * @addtogroup Radix4_CFFT_CIFFT    
- * @{    
- */
-
-/**    
- * @details    
- * @brief Processing function for the Q31 CFFT/CIFFT.    
- * @param[in]      *S    points to an instance of the Q31 CFFT/CIFFT structure.   
- * @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.   
- * @return none.    
- *     
- * \par Input and output formats:    
- * \par    
- * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.   
- * Hence the output format is different for different FFT sizes.    
- * The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT:   
- * \par   
- * \image html CFFTQ31.gif "Input and Output Formats for Q31 CFFT"    
- * \image html CIFFTQ31.gif "Input and Output Formats for Q31 CIFFT"    
- *    
- */
-
-void arm_cfft_radix4_q31(
-  const arm_cfft_radix4_instance_q31 * S,
-  q31_t * pSrc)
-{
-  if(S->ifftFlag == 1u)
-  {
-    /* Complex IFFT radix-4 */
-    arm_radix4_butterfly_inverse_q31(pSrc, S->fftLen, S->pTwiddle,
-                                     S->twidCoefModifier);
-  }
-  else
-  {
-    /* Complex FFT radix-4 */
-    arm_radix4_butterfly_q31(pSrc, S->fftLen, S->pTwiddle,
-                             S->twidCoefModifier);
-  }
-
-
-  if(S->bitReverseFlag == 1u)
-  {
-    /*  Bit Reversal */
-    arm_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
-  }
-
-}
-
-/**    
- * @} end of Radix4_CFFT_CIFFT group    
- */
-
-/*    
-* Radix-4 FFT algorithm used is :    
-*    
-* Input real and imaginary data:    
-* x(n) = xa + j * ya    
-* x(n+N/4 ) = xb + j * yb    
-* x(n+N/2 ) = xc + j * yc    
-* x(n+3N 4) = xd + j * yd    
-*    
-*    
-* Output real and imaginary data:    
-* x(4r) = xa'+ j * ya'    
-* x(4r+1) = xb'+ j * yb'    
-* x(4r+2) = xc'+ j * yc'    
-* x(4r+3) = xd'+ j * yd'    
-*    
-*    
-* Twiddle factors for radix-4 FFT:    
-* Wn = co1 + j * (- si1)    
-* W2n = co2 + j * (- si2)    
-* W3n = co3 + j * (- si3)    
-*    
-*  Butterfly implementation:    
-* xa' = xa + xb + xc + xd    
-* ya' = ya + yb + yc + yd    
-* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)    
-* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)    
-* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)    
-* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)    
-* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)    
-* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)    
-*    
-*/
-
-/**    
- * @brief  Core function for the Q31 CFFT butterfly process.   
- * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.   
- * @param[in]      fftLen           length of the FFT.   
- * @param[in]      *pCoef           points to twiddle coefficient buffer.   
- * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
- * @return none.   
- */
-
-void arm_radix4_butterfly_q31(
-  q31_t * pSrc,
-  uint32_t fftLen,
-  q31_t * pCoef,
-  uint32_t twidCoefModifier)
-{
-  uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k;
-  q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
-
-  q31_t xa, xb, xc, xd;
-  q31_t ya, yb, yc, yd;
-  q31_t xa_out, xb_out, xc_out, xd_out;
-  q31_t ya_out, yb_out, yc_out, yd_out;
-
-  q31_t *ptr1;
-  q63_t xaya, xbyb, xcyc, xdyd;
-  /* Total process is divided into three stages */
-
-  /* process first stage, middle stages, & last stage */
-
-
-  /* start of first stage process */
-
-  /*  Initializations for the first stage */
-  n2 = fftLen;
-  n1 = n2;
-  /* n2 = fftLen/4 */
-  n2 >>= 2u;
-  i0 = 0u;
-  ia1 = 0u;
-
-  j = n2;
-
-  /*  Calculation of first stage */
-  do
-  {
-    /*  index calculation for the input as, */
-    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
-    i1 = i0 + n2;
-    i2 = i1 + n2;
-    i3 = i2 + n2;
-
-    /* input is in 1.31(q31) format and provide 4 guard bits for the input */
-
-    /*  Butterfly implementation */
-    /* xa + xc */
-    r1 = (pSrc[(2u * i0)] >> 4u) + (pSrc[(2u * i2)] >> 4u);
-    /* xa - xc */
-    r2 = (pSrc[2u * i0] >> 4u) - (pSrc[2u * i2] >> 4u);
-
-    /* xb + xd */
-    t1 = (pSrc[2u * i1] >> 4u) + (pSrc[2u * i3] >> 4u);
-
-    /* ya + yc */
-    s1 = (pSrc[(2u * i0) + 1u] >> 4u) + (pSrc[(2u * i2) + 1u] >> 4u);
-    /* ya - yc */
-    s2 = (pSrc[(2u * i0) + 1u] >> 4u) - (pSrc[(2u * i2) + 1u] >> 4u);
-
-    /* xa' = xa + xb + xc + xd */
-    pSrc[2u * i0] = (r1 + t1);
-    /* (xa + xc) - (xb + xd) */
-    r1 = r1 - t1;
-    /* yb + yd */
-    t2 = (pSrc[(2u * i1) + 1u] >> 4u) + (pSrc[(2u * i3) + 1u] >> 4u);
-
-    /* ya' = ya + yb + yc + yd */
-    pSrc[(2u * i0) + 1u] = (s1 + t2);
-
-    /* (ya + yc) - (yb + yd) */
-    s1 = s1 - t2;
-
-    /* yb - yd */
-    t1 = (pSrc[(2u * i1) + 1u] >> 4u) - (pSrc[(2u * i3) + 1u] >> 4u);
-    /* xb - xd */
-    t2 = (pSrc[2u * i1] >> 4u) - (pSrc[2u * i3] >> 4u);
-
-    /*  index calculation for the coefficients */
-    ia2 = 2u * ia1;
-    co2 = pCoef[ia2 * 2u];
-    si2 = pCoef[(ia2 * 2u) + 1u];
-
-    /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
-    pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
-                     ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;
-
-    /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
-    pSrc[(2u * i1) + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
-                            ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;
-
-    /* (xa - xc) + (yb - yd) */
-    r1 = r2 + t1;
-    /* (xa - xc) - (yb - yd) */
-    r2 = r2 - t1;
-
-    /* (ya - yc) - (xb - xd) */
-    s1 = s2 - t2;
-    /* (ya - yc) + (xb - xd) */
-    s2 = s2 + t2;
-
-    co1 = pCoef[ia1 * 2u];
-    si1 = pCoef[(ia1 * 2u) + 1u];
-
-    /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
-    pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
-                     ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;
-
-    /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
-    pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
-                            ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;
-
-    /*  index calculation for the coefficients */
-    ia3 = 3u * ia1;
-    co3 = pCoef[ia3 * 2u];
-    si3 = pCoef[(ia3 * 2u) + 1u];
-
-    /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
-    pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
-                     ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;
-
-    /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
-    pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
-                            ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;
-
-    /*  Twiddle coefficients index modifier */
-    ia1 = ia1 + twidCoefModifier;
-
-    /*  Updating input index */
-    i0 = i0 + 1u;
-
-  } while(--j);
-
-  /* end of first stage process */
-
-  /* data is in 5.27(q27) format */
-
-
-  /* start of Middle stages process */
-
-
-  /* each stage in middle stages provides two down scaling of the input */
-
-  twidCoefModifier <<= 2u;
-
-
-  for (k = fftLen / 4u; k > 4u; k >>= 2u)
-  {
-    /*  Initializations for the first stage */
-    n1 = n2;
-    n2 >>= 2u;
-    ia1 = 0u;
-
-    /*  Calculation of first stage */
-    for (j = 0u; j <= (n2 - 1u); j++)
-    {
-      /*  index calculation for the coefficients */
-      ia2 = ia1 + ia1;
-      ia3 = ia2 + ia1;
-      co1 = pCoef[ia1 * 2u];
-      si1 = pCoef[(ia1 * 2u) + 1u];
-      co2 = pCoef[ia2 * 2u];
-      si2 = pCoef[(ia2 * 2u) + 1u];
-      co3 = pCoef[ia3 * 2u];
-      si3 = pCoef[(ia3 * 2u) + 1u];
-      /*  Twiddle coefficients index modifier */
-      ia1 = ia1 + twidCoefModifier;
-
-      for (i0 = j; i0 < fftLen; i0 += n1)
-      {
-        /*  index calculation for the input as, */
-        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
-        i1 = i0 + n2;
-        i2 = i1 + n2;
-        i3 = i2 + n2;
-
-        /*  Butterfly implementation */
-        /* xa + xc */
-        r1 = pSrc[2u * i0] + pSrc[2u * i2];
-        /* xa - xc */
-        r2 = pSrc[2u * i0] - pSrc[2u * i2];
-
-        /* ya + yc */
-        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
-        /* ya - yc */
-        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
-
-        /* xb + xd */
-        t1 = pSrc[2u * i1] + pSrc[2u * i3];
-
-        /* xa' = xa + xb + xc + xd */
-        pSrc[2u * i0] = (r1 + t1) >> 2u;
-        /* xa + xc -(xb + xd) */
-        r1 = r1 - t1;
-
-        /* yb + yd */
-        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
-        /* ya' = ya + yb + yc + yd */
-        pSrc[(2u * i0) + 1u] = (s1 + t2) >> 2u;
-
-        /* (ya + yc) - (yb + yd) */
-        s1 = s1 - t2;
-
-        /* (yb - yd) */
-        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
-        /* (xb - xd) */
-        t2 = pSrc[2u * i1] - pSrc[2u * i3];
-
-        /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
-        pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
-                         ((int32_t) (((q63_t) s1 * si2) >> 32))) >> 1u;
-
-        /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
-        pSrc[(2u * i1) + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
-                                ((int32_t) (((q63_t) r1 * si2) >> 32))) >> 1u;
-
-        /* (xa - xc) + (yb - yd) */
-        r1 = r2 + t1;
-        /* (xa - xc) - (yb - yd) */
-        r2 = r2 - t1;
-
-        /* (ya - yc) -  (xb - xd) */
-        s1 = s2 - t2;
-        /* (ya - yc) +  (xb - xd) */
-        s2 = s2 + t2;
-
-        /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
-        pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
-                         ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;
-
-        /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
-        pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
-                                ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;
-
-        /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
-        pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
-                         ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;
-
-        /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
-        pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
-                                ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;
-      }
-    }
-    twidCoefModifier <<= 2u;
-  }
-
-  /* End of Middle stages process */
-
-  /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */
-  /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */
-  /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */
-  /* data is in 5.27(q27) format for the 16 point as there are no middle stages */
-
-
-  /* start of Last stage process */
-  /*  Initializations for the last stage */
-  j = fftLen >> 2;
-  ptr1 = &pSrc[0];
-
-  /*  Calculations of last stage */
-  do
-  {
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    /* Read xa (real), ya(imag) input */
-    xaya = *__SIMD64(ptr1)++;
-    xa = (q31_t) xaya;
-    ya = (q31_t) (xaya >> 32);
-
-    /* Read xb (real), yb(imag) input */
-    xbyb = *__SIMD64(ptr1)++;
-    xb = (q31_t) xbyb;
-    yb = (q31_t) (xbyb >> 32);
-
-    /* Read xc (real), yc(imag) input */
-    xcyc = *__SIMD64(ptr1)++;
-    xc = (q31_t) xcyc;
-    yc = (q31_t) (xcyc >> 32);
-
-    /* Read xc (real), yc(imag) input */
-    xdyd = *__SIMD64(ptr1)++;
-    xd = (q31_t) xdyd;
-    yd = (q31_t) (xdyd >> 32);
-
-#else
-
-    /* Read xa (real), ya(imag) input */
-    xaya = *__SIMD64(ptr1)++;
-    ya = (q31_t) xaya;
-    xa = (q31_t) (xaya >> 32);
-
-    /* Read xb (real), yb(imag) input */
-    xbyb = *__SIMD64(ptr1)++;
-    yb = (q31_t) xbyb;
-    xb = (q31_t) (xbyb >> 32);
-
-    /* Read xc (real), yc(imag) input */
-    xcyc = *__SIMD64(ptr1)++;
-    yc = (q31_t) xcyc;
-    xc = (q31_t) (xcyc >> 32);
-
-    /* Read xc (real), yc(imag) input */
-    xdyd = *__SIMD64(ptr1)++;
-    yd = (q31_t) xdyd;
-    xd = (q31_t) (xdyd >> 32);
-
-
-#endif
-
-    /* xa' = xa + xb + xc + xd */
-    xa_out = xa + xb + xc + xd;
-
-    /* ya' = ya + yb + yc + yd */
-    ya_out = ya + yb + yc + yd;
-
-    /* pointer updation for writing */
-    ptr1 = ptr1 - 8u;
-
-    /* writing xa' and ya' */
-    *ptr1++ = xa_out;
-    *ptr1++ = ya_out;
-
-    xc_out = (xa - xb + xc - xd);
-    yc_out = (ya - yb + yc - yd);
-
-    /* writing xc' and yc' */
-    *ptr1++ = xc_out;
-    *ptr1++ = yc_out;
-
-    xb_out = (xa + yb - xc - yd);
-    yb_out = (ya - xb - yc + xd);
-
-    /* writing xb' and yb' */
-    *ptr1++ = xb_out;
-    *ptr1++ = yb_out;
-
-    xd_out = (xa - yb - xc + yd);
-    yd_out = (ya + xb - yc - xd);
-
-    /* writing xd' and yd' */
-    *ptr1++ = xd_out;
-    *ptr1++ = yd_out;
-
-
-  } while(--j);
-
-  /* output is in 11.21(q21) format for the 1024 point */
-  /* output is in 9.23(q23) format for the 256 point */
-  /* output is in 7.25(q25) format for the 64 point */
-  /* output is in 5.27(q27) format for the 16 point */
-
-  /* End of last stage process */
-
-}
-
-
-/**    
- * @brief  Core function for the Q31 CIFFT butterfly process.   
- * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.   
- * @param[in]      fftLen           length of the FFT.   
- * @param[in]      *pCoef           points to twiddle coefficient buffer.   
- * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
- * @return none.   
- */
-
-
-/*    
-* Radix-4 IFFT algorithm used is :    
-*    
-* CIFFT uses same twiddle coefficients as CFFT Function    
-*  x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4]    
-*    
-*    
-* IFFT is implemented with following changes in equations from FFT    
-*    
-* Input real and imaginary data:    
-* x(n) = xa + j * ya    
-* x(n+N/4 ) = xb + j * yb    
-* x(n+N/2 ) = xc + j * yc    
-* x(n+3N 4) = xd + j * yd    
-*    
-*    
-* Output real and imaginary data:    
-* x(4r) = xa'+ j * ya'    
-* x(4r+1) = xb'+ j * yb'    
-* x(4r+2) = xc'+ j * yc'    
-* x(4r+3) = xd'+ j * yd'    
-*    
-*    
-* Twiddle factors for radix-4 IFFT:    
-* Wn = co1 + j * (si1)    
-* W2n = co2 + j * (si2)    
-* W3n = co3 + j * (si3)    
-    
-* The real and imaginary output values for the radix-4 butterfly are    
-* xa' = xa + xb + xc + xd    
-* ya' = ya + yb + yc + yd    
-* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)    
-* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)    
-* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)    
-* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)    
-* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)    
-* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)    
-*    
-*/
-
-void arm_radix4_butterfly_inverse_q31(
-  q31_t * pSrc,
-  uint32_t fftLen,
-  q31_t * pCoef,
-  uint32_t twidCoefModifier)
-{
-  uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k;
-  q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
-  q31_t xa, xb, xc, xd;
-  q31_t ya, yb, yc, yd;
-  q31_t xa_out, xb_out, xc_out, xd_out;
-  q31_t ya_out, yb_out, yc_out, yd_out;
-
-  q31_t *ptr1;
-  q63_t xaya, xbyb, xcyc, xdyd;
-
-  /* input is be 1.31(q31) format for all FFT sizes */
-  /* Total process is divided into three stages */
-  /* process first stage, middle stages, & last stage */
-
-  /* Start of first stage process */
-
-  /* Initializations for the first stage */
-  n2 = fftLen;
-  n1 = n2;
-  /* n2 = fftLen/4 */
-  n2 >>= 2u;
-  i0 = 0u;
-  ia1 = 0u;
-
-  j = n2;
-
-  do
-  {
-
-    /* input is in 1.31(q31) format and provide 4 guard bits for the input */
-
-    /*  index calculation for the input as, */
-    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
-    i1 = i0 + n2;
-    i2 = i1 + n2;
-    i3 = i2 + n2;
-
-    /*  Butterfly implementation */
-    /* xa + xc */
-    r1 = (pSrc[2u * i0] >> 4u) + (pSrc[2u * i2] >> 4u);
-    /* xa - xc */
-    r2 = (pSrc[2u * i0] >> 4u) - (pSrc[2u * i2] >> 4u);
-
-    /* xb + xd */
-    t1 = (pSrc[2u * i1] >> 4u) + (pSrc[2u * i3] >> 4u);
-
-    /* ya + yc */
-    s1 = (pSrc[(2u * i0) + 1u] >> 4u) + (pSrc[(2u * i2) + 1u] >> 4u);
-    /* ya - yc */
-    s2 = (pSrc[(2u * i0) + 1u] >> 4u) - (pSrc[(2u * i2) + 1u] >> 4u);
-
-    /* xa' = xa + xb + xc + xd */
-    pSrc[2u * i0] = (r1 + t1);
-    /* (xa + xc) - (xb + xd) */
-    r1 = r1 - t1;
-    /* yb + yd */
-    t2 = (pSrc[(2u * i1) + 1u] >> 4u) + (pSrc[(2u * i3) + 1u] >> 4u);
-    /* ya' = ya + yb + yc + yd */
-    pSrc[(2u * i0) + 1u] = (s1 + t2);
-
-    /* (ya + yc) - (yb + yd) */
-    s1 = s1 - t2;
-
-    /* yb - yd */
-    t1 = (pSrc[(2u * i1) + 1u] >> 4u) - (pSrc[(2u * i3) + 1u] >> 4u);
-    /* xb - xd */
-    t2 = (pSrc[2u * i1] >> 4u) - (pSrc[2u * i3] >> 4u);
-
-    /*  index calculation for the coefficients */
-    ia2 = 2u * ia1;
-    co2 = pCoef[ia2 * 2u];
-    si2 = pCoef[(ia2 * 2u) + 1u];
-
-    /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
-    pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) -
-                     ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;
-
-    /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
-    pSrc[2u * i1 + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) +
-                          ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;
-
-    /* (xa - xc) - (yb - yd) */
-    r1 = r2 - t1;
-    /* (xa - xc) + (yb - yd) */
-    r2 = r2 + t1;
-
-    /* (ya - yc) + (xb - xd) */
-    s1 = s2 + t2;
-    /* (ya - yc) - (xb - xd) */
-    s2 = s2 - t2;
-
-    co1 = pCoef[ia1 * 2u];
-    si1 = pCoef[(ia1 * 2u) + 1u];
-
-    /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
-    pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
-                     ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;
-
-    /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
-    pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
-                            ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;
-
-    /*  index calculation for the coefficients */
-    ia3 = 3u * ia1;
-    co3 = pCoef[ia3 * 2u];
-    si3 = pCoef[(ia3 * 2u) + 1u];
-
-    /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
-    pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
-                     ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;
-
-    /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
-    pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
-                            ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;
-
-    /*  Twiddle coefficients index modifier */
-    ia1 = ia1 + twidCoefModifier;
-
-    /*  Updating input index */
-    i0 = i0 + 1u;
-
-  } while(--j);
-
-  /* data is in 5.27(q27) format */
-  /* each stage provides two down scaling of the input */
-
-
-  /* Start of Middle stages process */
-
-  twidCoefModifier <<= 2u;
-
-  /*  Calculation of second stage to excluding last stage */
-  for (k = fftLen / 4u; k > 4u; k >>= 2u)
-  {
-    /*  Initializations for the first stage */
-    n1 = n2;
-    n2 >>= 2u;
-    ia1 = 0u;
-
-    for (j = 0; j <= (n2 - 1u); j++)
-    {
-      /*  index calculation for the coefficients */
-      ia2 = ia1 + ia1;
-      ia3 = ia2 + ia1;
-      co1 = pCoef[ia1 * 2u];
-      si1 = pCoef[(ia1 * 2u) + 1u];
-      co2 = pCoef[ia2 * 2u];
-      si2 = pCoef[(ia2 * 2u) + 1u];
-      co3 = pCoef[ia3 * 2u];
-      si3 = pCoef[(ia3 * 2u) + 1u];
-      /*  Twiddle coefficients index modifier */
-      ia1 = ia1 + twidCoefModifier;
-
-      for (i0 = j; i0 < fftLen; i0 += n1)
-      {
-        /*  index calculation for the input as, */
-        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
-        i1 = i0 + n2;
-        i2 = i1 + n2;
-        i3 = i2 + n2;
-
-        /*  Butterfly implementation */
-        /* xa + xc */
-        r1 = pSrc[2u * i0] + pSrc[2u * i2];
-        /* xa - xc */
-        r2 = pSrc[2u * i0] - pSrc[2u * i2];
-
-        /* ya + yc */
-        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
-        /* ya - yc */
-        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
-
-        /* xb + xd */
-        t1 = pSrc[2u * i1] + pSrc[2u * i3];
-
-        /* xa' = xa + xb + xc + xd */
-        pSrc[2u * i0] = (r1 + t1) >> 2u;
-        /* xa + xc -(xb + xd) */
-        r1 = r1 - t1;
-        /* yb + yd */
-        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
-        /* ya' = ya + yb + yc + yd */
-        pSrc[(2u * i0) + 1u] = (s1 + t2) >> 2u;
-
-        /* (ya + yc) - (yb + yd) */
-        s1 = s1 - t2;
-
-        /* (yb - yd) */
-        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
-        /* (xb - xd) */
-        t2 = pSrc[2u * i1] - pSrc[2u * i3];
-
-        /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
-        pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32u)) -
-                         ((int32_t) (((q63_t) s1 * si2) >> 32u))) >> 1u;
-
-        /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
-        pSrc[(2u * i1) + 1u] =
-          (((int32_t) (((q63_t) s1 * co2) >> 32u)) +
-           ((int32_t) (((q63_t) r1 * si2) >> 32u))) >> 1u;
-
-        /* (xa - xc) - (yb - yd) */
-        r1 = r2 - t1;
-        /* (xa - xc) + (yb - yd) */
-        r2 = r2 + t1;
-
-        /* (ya - yc) +  (xb - xd) */
-        s1 = s2 + t2;
-        /* (ya - yc) -  (xb - xd) */
-        s2 = s2 - t2;
-
-        /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
-        pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
-                         ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;
-
-        /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
-        pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
-                                ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;
-
-        /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
-        pSrc[(2u * i3)] = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
-                           ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;
-
-        /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
-        pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
-                                ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;
-      }
-    }
-    twidCoefModifier <<= 2u;
-  }
-
-  /* End of Middle stages process */
-
-  /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */
-  /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */
-  /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */
-  /* data is in 5.27(q27) format for the 16 point as there are no middle stages */
-
-
-  /* Start of last stage process */
-
-
-  /*  Initializations for the last stage */
-  j = fftLen >> 2;
-  ptr1 = &pSrc[0];
-
-  /*  Calculations of last stage */
-  do
-  {
-#ifndef ARM_MATH_BIG_ENDIAN
-    /* Read xa (real), ya(imag) input */
-    xaya = *__SIMD64(ptr1)++;
-    xa = (q31_t) xaya;
-    ya = (q31_t) (xaya >> 32);
-
-    /* Read xb (real), yb(imag) input */
-    xbyb = *__SIMD64(ptr1)++;
-    xb = (q31_t) xbyb;
-    yb = (q31_t) (xbyb >> 32);
-
-    /* Read xc (real), yc(imag) input */
-    xcyc = *__SIMD64(ptr1)++;
-    xc = (q31_t) xcyc;
-    yc = (q31_t) (xcyc >> 32);
-
-    /* Read xc (real), yc(imag) input */
-    xdyd = *__SIMD64(ptr1)++;
-    xd = (q31_t) xdyd;
-    yd = (q31_t) (xdyd >> 32);
-
-#else
-
-    /* Read xa (real), ya(imag) input */
-    xaya = *__SIMD64(ptr1)++;
-    ya = (q31_t) xaya;
-    xa = (q31_t) (xaya >> 32);
-
-    /* Read xb (real), yb(imag) input */
-    xbyb = *__SIMD64(ptr1)++;
-    yb = (q31_t) xbyb;
-    xb = (q31_t) (xbyb >> 32);
-
-    /* Read xc (real), yc(imag) input */
-    xcyc = *__SIMD64(ptr1)++;
-    yc = (q31_t) xcyc;
-    xc = (q31_t) (xcyc >> 32);
-
-    /* Read xc (real), yc(imag) input */
-    xdyd = *__SIMD64(ptr1)++;
-    yd = (q31_t) xdyd;
-    xd = (q31_t) (xdyd >> 32);
-
-
-#endif
-
-    /* xa' = xa + xb + xc + xd */
-    xa_out = xa + xb + xc + xd;
-
-    /* ya' = ya + yb + yc + yd */
-    ya_out = ya + yb + yc + yd;
-
-    /* pointer updation for writing */
-    ptr1 = ptr1 - 8u;
-
-    /* writing xa' and ya' */
-    *ptr1++ = xa_out;
-    *ptr1++ = ya_out;
-
-    xc_out = (xa - xb + xc - xd);
-    yc_out = (ya - yb + yc - yd);
-
-    /* writing xc' and yc' */
-    *ptr1++ = xc_out;
-    *ptr1++ = yc_out;
-
-    xb_out = (xa - yb - xc + yd);
-    yb_out = (ya + xb - yc - xd);
-
-    /* writing xb' and yb' */
-    *ptr1++ = xb_out;
-    *ptr1++ = yb_out;
-
-    xd_out = (xa + yb - xc - yd);
-    yd_out = (ya - xb - yc + xd);
-
-    /* writing xd' and yd' */
-    *ptr1++ = xd_out;
-    *ptr1++ = yd_out;
-
-
-  } while(--j);
-
-  /* output is in 11.21(q21) format for the 1024 point */
-  /* output is in 9.23(q23) format for the 256 point */
-  /* output is in 7.25(q25) format for the 64 point */
-  /* output is in 5.27(q27) format for the 16 point */
-
-  /* End of last stage process */
-}
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_f32.c
deleted file mode 100644
index 75cc3ef689..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_f32.c
+++ /dev/null
@@ -1,453 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_dct4_f32.c    
-*    
-* Description:	Processing function of DCT4 & IDCT4 F32.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupTransforms    
- */
-
-/**    
- * @defgroup DCT4_IDCT4 DCT Type IV Functions    
- * Representation of signals by minimum number of values is important for storage and transmission.    
- * The possibility of large discontinuity between the beginning and end of a period of a signal    
- * in DFT can be avoided by extending the signal so that it is even-symmetric.    
- * Discrete Cosine Transform (DCT) is constructed such that its energy is heavily concentrated in the lower part of the    
- * spectrum and is very widely used in signal and image coding applications.    
- * The family of DCTs (DCT type- 1,2,3,4) is the outcome of different combinations of homogeneous boundary conditions.    
- * DCT has an excellent energy-packing capability, hence has many applications and in data compression in particular.    
- *    
- * DCT is essentially the Discrete Fourier Transform(DFT) of an even-extended real signal.    
- * Reordering of the input data makes the computation of DCT just a problem of    
- * computing the DFT of a real signal with a few additional operations.    
- * This approach provides regular, simple, and very efficient DCT algorithms for practical hardware and software implementations.    
- *     
- * DCT type-II can be implemented using Fast fourier transform (FFT) internally, as the transform is applied on real values, Real FFT can be used.    
- * DCT4 is implemented using DCT2 as their implementations are similar except with some added pre-processing and post-processing.    
- * DCT2 implementation can be described in the following steps:    
- * - Re-ordering input    
- * - Calculating Real FFT    
- * - Multiplication of weights and Real FFT output and getting real part from the product.    
- *    
- * This process is explained by the block diagram below:    
- * \image html DCT4.gif "Discrete Cosine Transform - type-IV"    
- *    
- * \par Algorithm:    
- * The N-point type-IV DCT is defined as a real, linear transformation by the formula:    
- * \image html DCT4Equation.gif    
- * where k = 0,1,2,.....N-1    
- *\par    
- * Its inverse is defined as follows:    
- * \image html IDCT4Equation.gif    
- * where n = 0,1,2,.....N-1    
- *\par    
- * The DCT4 matrices become involutory (i.e. they are self-inverse) by multiplying with an overall scale factor of sqrt(2/N).    
- * The symmetry of the transform matrix indicates that the fast algorithms for the forward    
- * and inverse transform computation are identical.    
- * Note that the implementation of Inverse DCT4 and DCT4 is same, hence same process function can be used for both.    
- *    
- * \par Lengths supported by the transform:    
- *  As DCT4 internally uses Real FFT, it supports all the lengths supported by arm_rfft_f32().    
- * The library provides separate functions for Q15, Q31, and floating-point data types.    
- * \par Instance Structure    
- * The instances for Real FFT and FFT, cosine values table and twiddle factor table are stored in an instance data structure.    
- * A separate instance structure must be defined for each transform.    
- * There are separate instance structure declarations for each of the 3 supported data types.    
- *    
- * \par Initialization Functions    
- * There is also an associated initialization function for each data type.    
- * The initialization function performs the following operations:    
- * - Sets the values of the internal structure fields.    
- * - Initializes Real FFT as its process function is used internally in DCT4, by calling arm_rfft_init_f32().    
- * \par    
- * Use of the initialization function is optional.    
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
- * To place an instance structure into a const data section, the instance structure must be manually initialized.    
- * Manually initialize the instance structure as follows:    
- * 
    
- *arm_dct4_instance_f32 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};    
- *arm_dct4_instance_q31 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};   
- *arm_dct4_instance_q15 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};   
- * 
   
- * where \c N is the length of the DCT4; \c Nby2 is half of the length of the DCT4;   
- * \c normalize is normalizing factor used and is equal to sqrt(2/N);    
- * \c pTwiddle points to the twiddle factor table;   
- * \c pCosFactor points to the cosFactor table;   
- * \c pRfft points to the real FFT instance;   
- * \c pCfft points to the complex FFT instance;   
- * The CFFT and RFFT structures also needs to be initialized, refer to arm_cfft_radix4_f32()   
- * and arm_rfft_f32() respectively for details regarding static initialization.   
- *   
- * \par Fixed-Point Behavior    
- * Care must be taken when using the fixed-point versions of the DCT4 transform functions.    
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.    
- * Refer to the function specific documentation below for usage guidelines.    
- */
-
- /**    
- * @addtogroup DCT4_IDCT4    
- * @{    
- */
-
-/**    
- * @brief Processing function for the floating-point DCT4/IDCT4.   
- * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.   
- * @param[in]       *pState        points to state buffer.   
- * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.   
- * @return none.   
- */
-
-void arm_dct4_f32(
-  const arm_dct4_instance_f32 * S,
-  float32_t * pState,
-  float32_t * pInlineBuffer)
-{
-  uint32_t i;                                    /* Loop counter */
-  float32_t *weights = S->pTwiddle;              /* Pointer to the Weights table */
-  float32_t *cosFact = S->pCosFactor;            /* Pointer to the cos factors table */
-  float32_t *pS1, *pS2, *pbuff;                  /* Temporary pointers for input buffer and pState buffer */
-  float32_t in;                                  /* Temporary variable */
-
-
-  /* DCT4 computation involves DCT2 (which is calculated using RFFT)    
-   * along with some pre-processing and post-processing.    
-   * Computational procedure is explained as follows:    
-   * (a) Pre-processing involves multiplying input with cos factor,    
-   *     r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))    
-   *              where,    
-   *                 r(n) -- output of preprocessing    
-   *                 u(n) -- input to preprocessing(actual Source buffer)    
-   * (b) Calculation of DCT2 using FFT is divided into three steps:    
-   *                  Step1: Re-ordering of even and odd elements of input.    
-   *                  Step2: Calculating FFT of the re-ordered input.    
-   *                  Step3: Taking the real part of the product of FFT output and weights.    
-   * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:    
-   *                   Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
-   *                        where,    
-   *                           Y4 -- DCT4 output,   Y2 -- DCT2 output    
-   * (d) Multiplying the output with the normalizing factor sqrt(2/N).    
-   */
-
-        /*-------- Pre-processing ------------*/
-  /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
-  arm_scale_f32(pInlineBuffer, 2.0f, pInlineBuffer, S->N);
-  arm_mult_f32(pInlineBuffer, cosFact, pInlineBuffer, S->N);
-
-  /* ----------------------------------------------------------------    
-   * Step1: Re-ordering of even and odd elements as,    
-   *             pState[i] =  pInlineBuffer[2*i] and    
-   *             pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2    
-   ---------------------------------------------------------------------*/
-
-  /* pS1 initialized to pState */
-  pS1 = pState;
-
-  /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
-  pS2 = pState + (S->N - 1u);
-
-  /* pbuff initialized to input buffer */
-  pbuff = pInlineBuffer;
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
-  i = (uint32_t) S->Nby2 >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  do
-  {
-    /* Re-ordering of even and odd elements */
-    /* pState[i] =  pInlineBuffer[2*i] */
-    *pS1++ = *pbuff++;
-    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
-    *pS2-- = *pbuff++;
-
-    *pS1++ = *pbuff++;
-    *pS2-- = *pbuff++;
-
-    *pS1++ = *pbuff++;
-    *pS2-- = *pbuff++;
-
-    *pS1++ = *pbuff++;
-    *pS2-- = *pbuff++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-  /* pbuff initialized to input buffer */
-  pbuff = pInlineBuffer;
-
-  /* pS1 initialized to pState */
-  pS1 = pState;
-
-  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
-  i = (uint32_t) S->N >> 2u;
-
-  /* Processing with loop unrolling 4 times as N is always multiple of 4.    
-   * Compute 4 outputs at a time */
-  do
-  {
-    /* Writing the re-ordered output back to inplace input buffer */
-    *pbuff++ = *pS1++;
-    *pbuff++ = *pS1++;
-    *pbuff++ = *pS1++;
-    *pbuff++ = *pS1++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-
-  /* ---------------------------------------------------------    
-   *     Step2: Calculate RFFT for N-point input    
-   * ---------------------------------------------------------- */
-  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
-  arm_rfft_f32(S->pRfft, pInlineBuffer, pState);
-
-        /*----------------------------------------------------------------------    
-	 *  Step3: Multiply the FFT output with the weights.    
-	 *----------------------------------------------------------------------*/
-  arm_cmplx_mult_cmplx_f32(pState, weights, pState, S->N);
-
-  /* ----------- Post-processing ---------- */
-  /* DCT-IV can be obtained from DCT-II by the equation,    
-   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
-   *       Hence, Y4(0) = Y2(0)/2  */
-  /* Getting only real part from the output and Converting to DCT-IV */
-
-  /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
-  i = ((uint32_t) S->N - 1u) >> 2u;
-
-  /* pbuff initialized to input buffer. */
-  pbuff = pInlineBuffer;
-
-  /* pS1 initialized to pState */
-  pS1 = pState;
-
-  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
-  in = *pS1++ * (float32_t) 0.5;
-  /* input buffer acts as inplace, so output values are stored in the input itself. */
-  *pbuff++ = in;
-
-  /* pState pointer is incremented twice as the real values are located alternatively in the array */
-  pS1++;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  do
-  {
-    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
-    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    /* points to the next real value */
-    pS1++;
-
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    pS1++;
-
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    pS1++;
-
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    pS1++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  i = ((uint32_t) S->N - 1u) % 0x4u;
-
-  while(i > 0u)
-  {
-    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
-    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    /* points to the next real value */
-    pS1++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-
-        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
-
-  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
-  i = (uint32_t) S->N >> 2u;
-
-  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
-  pbuff = pInlineBuffer;
-
-  /* Processing with loop unrolling 4 times as N is always multiple of 4.  Compute 4 outputs at a time */
-  do
-  {
-    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
-    in = *pbuff;
-    *pbuff++ = in * S->normalize;
-
-    in = *pbuff;
-    *pbuff++ = in * S->normalize;
-
-    in = *pbuff;
-    *pbuff++ = in * S->normalize;
-
-    in = *pbuff;
-    *pbuff++ = in * S->normalize;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Initializing the loop counter to N/2 */
-  i = (uint32_t) S->Nby2;
-
-  do
-  {
-    /* Re-ordering of even and odd elements */
-    /* pState[i] =  pInlineBuffer[2*i] */
-    *pS1++ = *pbuff++;
-    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
-    *pS2-- = *pbuff++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-  /* pbuff initialized to input buffer */
-  pbuff = pInlineBuffer;
-
-  /* pS1 initialized to pState */
-  pS1 = pState;
-
-  /* Initializing the loop counter */
-  i = (uint32_t) S->N;
-
-  do
-  {
-    /* Writing the re-ordered output back to inplace input buffer */
-    *pbuff++ = *pS1++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-
-  /* ---------------------------------------------------------    
-   *     Step2: Calculate RFFT for N-point input    
-   * ---------------------------------------------------------- */
-  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
-  arm_rfft_f32(S->pRfft, pInlineBuffer, pState);
-
-        /*----------------------------------------------------------------------    
-	 *  Step3: Multiply the FFT output with the weights.    
-	 *----------------------------------------------------------------------*/
-  arm_cmplx_mult_cmplx_f32(pState, weights, pState, S->N);
-
-  /* ----------- Post-processing ---------- */
-  /* DCT-IV can be obtained from DCT-II by the equation,    
-   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
-   *       Hence, Y4(0) = Y2(0)/2  */
-  /* Getting only real part from the output and Converting to DCT-IV */
-
-  /* pbuff initialized to input buffer. */
-  pbuff = pInlineBuffer;
-
-  /* pS1 initialized to pState */
-  pS1 = pState;
-
-  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
-  in = *pS1++ * (float32_t) 0.5;
-  /* input buffer acts as inplace, so output values are stored in the input itself. */
-  *pbuff++ = in;
-
-  /* pState pointer is incremented twice as the real values are located alternatively in the array */
-  pS1++;
-
-  /* Initializing the loop counter */
-  i = ((uint32_t) S->N - 1u);
-
-  do
-  {
-    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
-    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    /* points to the next real value */
-    pS1++;
-
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-
-        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
-
-  /* Initializing the loop counter */
-  i = (uint32_t) S->N;
-
-  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
-  pbuff = pInlineBuffer;
-
-  do
-  {
-    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
-    in = *pbuff;
-    *pbuff++ = in * S->normalize;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
-   * @} end of DCT4_IDCT4 group    
-   */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_f32.c
deleted file mode 100644
index f6848f61fc..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_f32.c
+++ /dev/null
@@ -1,16511 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_dct4_init_f32.c    
-*    
-* Description:	Initialization function of DCT-4 & IDCT4 F32    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupTransforms    
- */
-
-/**    
- * @addtogroup DCT4_IDCT4    
- * @{    
- */
-
-/*    
-* @brief  Weights Table    
-*/
-
-/**    
-* \par    
-* Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
    
-* \par    
-* C command to generate the table    
-* 
    
-* for(i = 0; i< N; i++)    
-* {    
-*    weights[2*i]= cos(i*c);    
-*    weights[(2*i)+1]= -sin(i * c);    
-* } 
    
-* \par    
-* Where N is the Number of weights to be calculated and c is pi/(2*N)    
-* \par    
-* In the tables below the real and imaginary values are placed alternatively, hence the    
-* array length is 2*N.    
-*/
-
-static const float32_t Weights_128[256] = {
-  1.000000000000000000f, 0.000000000000000000f, 0.999924701839144500f,
-  -0.012271538285719925f,
-  0.999698818696204250f, -0.024541228522912288f, 0.999322384588349540f,
-  -0.036807222941358832f,
-  0.998795456205172410f, -0.049067674327418015f, 0.998118112900149180f,
-  -0.061320736302208578f,
-  0.997290456678690210f, -0.073564563599667426f, 0.996312612182778000f,
-  -0.085797312344439894f,
-  0.995184726672196930f, -0.098017140329560604f, 0.993906970002356060f,
-  -0.110222207293883060f,
-  0.992479534598709970f, -0.122410675199216200f, 0.990902635427780010f,
-  -0.134580708507126170f,
-  0.989176509964781010f, -0.146730474455361750f, 0.987301418157858430f,
-  -0.158858143333861450f,
-  0.985277642388941220f, -0.170961888760301220f, 0.983105487431216290f,
-  -0.183039887955140950f,
-  0.980785280403230430f, -0.195090322016128250f, 0.978317370719627650f,
-  -0.207111376192218560f,
-  0.975702130038528570f, -0.219101240156869800f, 0.972939952205560180f,
-  -0.231058108280671110f,
-  0.970031253194543970f, -0.242980179903263870f, 0.966976471044852070f,
-  -0.254865659604514570f,
-  0.963776065795439840f, -0.266712757474898370f, 0.960430519415565790f,
-  -0.278519689385053060f,
-  0.956940335732208820f, -0.290284677254462330f, 0.953306040354193860f,
-  -0.302005949319228080f,
-  0.949528180593036670f, -0.313681740398891520f, 0.945607325380521280f,
-  -0.325310292162262930f,
-  0.941544065183020810f, -0.336889853392220050f, 0.937339011912574960f,
-  -0.348418680249434560f,
-  0.932992798834738960f, -0.359895036534988110f, 0.928506080473215590f,
-  -0.371317193951837540f,
-  0.923879532511286740f, -0.382683432365089780f, 0.919113851690057770f,
-  -0.393992040061048100f,
-  0.914209755703530690f, -0.405241314004989860f, 0.909167983090522380f,
-  -0.416429560097637150f,
-  0.903989293123443340f, -0.427555093430282080f, 0.898674465693953820f,
-  -0.438616238538527660f,
-  0.893224301195515320f, -0.449611329654606540f, 0.887639620402853930f,
-  -0.460538710958240010f,
-  0.881921264348355050f, -0.471396736825997640f, 0.876070094195406600f,
-  -0.482183772079122720f,
-  0.870086991108711460f, -0.492898192229784040f, 0.863972856121586810f,
-  -0.503538383725717580f,
-  0.857728610000272120f, -0.514102744193221660f, 0.851355193105265200f,
-  -0.524589682678468950f,
-  0.844853565249707120f, -0.534997619887097150f, 0.838224705554838080f,
-  -0.545324988422046460f,
-  0.831469612302545240f, -0.555570233019602180f, 0.824589302785025290f,
-  -0.565731810783613120f,
-  0.817584813151583710f, -0.575808191417845340f, 0.810457198252594770f,
-  -0.585797857456438860f,
-  0.803207531480644940f, -0.595699304492433360f, 0.795836904608883570f,
-  -0.605511041404325550f,
-  0.788346427626606340f, -0.615231590580626820f, 0.780737228572094490f,
-  -0.624859488142386340f,
-  0.773010453362736990f, -0.634393284163645490f, 0.765167265622458960f,
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-
-static const float32_t Weights_2048[4096] = {
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-  0.002300969151425887, -0.999997352766978210, 0.002109222019415816,
-    -0.999997775588762350,
-  0.001917474809855460, -0.999998161643486980, 0.001725727529795258,
-    -0.999998510931137790,
-  0.001533980186284766, -0.999998823451701880, 0.001342232786374430,
-    -0.999999099205167830,
-  0.001150485337113809, -0.999999338191525530, 0.000958737845553352,
-    -0.999999540410766110,
-  0.000766990318742846, -0.999999705862882230, 0.000575242763732077,
-    -0.999999834547867670,
-  0.000383495187571497, -0.999999926465717890, 0.000191747597310674,
-    -0.999999981616429330,
-
-};
-
-/**    
-* \par    
-* cosFactor tables are generated using the formula : 
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
    
-* \par    
-* C command to generate the table    
-* \par    
-* 
 for(i = 0; i< N; i++)    
-* {    
-*    cos_factors[i]= 2 * cos((2*i+1)*c/2);    
-* } 
    
-* \par    
-* where N is the number of factors to generate and c is pi/(2*N)    
-*/
-static const float32_t cos_factors_128[128] = {
-  0.999981175282601110f, 0.999830581795823400f, 0.999529417501093140f,
-  0.999077727752645360f,
-  0.998475580573294770f, 0.997723066644191640f, 0.996820299291165670f,
-  0.995767414467659820f,
-  0.994564570734255420f, 0.993211949234794500f, 0.991709753669099530f,
-  0.990058210262297120f,
-  0.988257567730749460f, 0.986308097244598670f, 0.984210092386929030f,
-  0.981963869109555240f,
-  0.979569765685440520f, 0.977028142657754390f, 0.974339382785575860f,
-  0.971503890986251780f,
-  0.968522094274417380f, 0.965394441697689400f, 0.962121404269041580f,
-  0.958703474895871600f,
-  0.955141168305770780f, 0.951435020969008340f, 0.947585591017741090f,
-  0.943593458161960390f,
-  0.939459223602189920f, 0.935183509938947610f, 0.930766961078983710f,
-  0.926210242138311380f,
-  0.921514039342042010f, 0.916679059921042700f, 0.911706032005429880f,
-  0.906595704514915330f,
-  0.901348847046022030f, 0.895966249756185220f, 0.890448723244757880f,
-  0.884797098430937790f,
-  0.879012226428633530f, 0.873094978418290090f, 0.867046245515692650f,
-  0.860866938637767310f,
-  0.854557988365400530f, 0.848120344803297230f, 0.841554977436898440f,
-  0.834862874986380010f,
-  0.828045045257755800f, 0.821102514991104650f, 0.814036329705948410f,
-  0.806847553543799330f,
-  0.799537269107905010f, 0.792106577300212390f, 0.784556597155575240f,
-  0.776888465673232440f,
-  0.769103337645579700f, 0.761202385484261780f, 0.753186799043612520f,
-  0.745057785441466060f,
-  0.736816568877369900f, 0.728464390448225200f, 0.720002507961381650f,
-  0.711432195745216430f,
-  0.702754744457225300f, 0.693971460889654000f, 0.685083667772700360f,
-  0.676092703575316030f,
-  0.666999922303637470f, 0.657806693297078640f, 0.648514401022112550f,
-  0.639124444863775730f,
-  0.629638238914927100f, 0.620057211763289210f, 0.610382806276309480f,
-  0.600616479383868970f,
-  0.590759701858874280f, 0.580813958095764530f, 0.570780745886967370f,
-  0.560661576197336030f,
-  0.550457972936604810f, 0.540171472729892970f, 0.529803624686294830f,
-  0.519355990165589530f,
-  0.508830142543106990f, 0.498227666972781870f, 0.487550160148436050f,
-  0.476799230063322250f,
-  0.465976495767966130f, 0.455083587126343840f, 0.444122144570429260f,
-  0.433093818853152010f,
-  0.422000270799799790f, 0.410843171057903910f, 0.399624199845646790f,
-  0.388345046698826300f,
-  0.377007410216418310f, 0.365612997804773960f, 0.354163525420490510f,
-  0.342660717311994380f,
-  0.331106305759876430f, 0.319502030816015750f, 0.307849640041534980f,
-  0.296150888243623960f,
-  0.284407537211271820f, 0.272621355449948980f, 0.260794117915275570f,
-  0.248927605745720260f,
-  0.237023605994367340f, 0.225083911359792780f, 0.213110319916091360f,
-  0.201104634842091960f,
-  0.189068664149806280f, 0.177004220412148860f, 0.164913120489970090f,
-  0.152797185258443410f,
-  0.140658239332849240f, 0.128498110793793220f, 0.116318630911904880f,
-  0.104121633872054730f,
-  0.091908956497132696f, 0.079682437971430126f, 0.067443919563664106f,
-  0.055195244349690031f,
-  0.042938256934940959f, 0.030674803176636581f, 0.018406729905804820f,
-  0.006135884649154515f
-};
-
-static const float32_t cos_factors_512[512] = {
-  0.999998823451701880f, 0.999989411081928400f, 0.999970586430974140f,
-  0.999942349676023910f,
-  0.999904701082852900f, 0.999857641005823860f, 0.999801169887884260f,
-  0.999735288260561680f,
-  0.999659996743959220f, 0.999575296046749220f, 0.999481186966166950f,
-  0.999377670388002850f,
-  0.999264747286594420f, 0.999142418724816910f, 0.999010685854073380f,
-  0.998869549914283560f,
-  0.998719012233872940f, 0.998559074229759310f, 0.998389737407340160f,
-  0.998211003360478190f,
-  0.998022873771486240f, 0.997825350411111640f, 0.997618435138519550f,
-  0.997402129901275300f,
-  0.997176436735326190f, 0.996941357764982160f, 0.996696895202896060f,
-  0.996443051350042630f,
-  0.996179828595696980f, 0.995907229417411720f, 0.995625256380994310f,
-  0.995333912140482280f,
-  0.995033199438118630f, 0.994723121104325700f, 0.994403680057679100f,
-  0.994074879304879370f,
-  0.993736721940724600f, 0.993389211148080650f, 0.993032350197851410f,
-  0.992666142448948020f,
-  0.992290591348257370f, 0.991905700430609330f, 0.991511473318743900f,
-  0.991107913723276890f,
-  0.990695025442664630f, 0.990272812363169110f, 0.989841278458820530f,
-  0.989400427791380380f,
-  0.988950264510302990f, 0.988490792852696590f, 0.988022017143283530f,
-  0.987543941794359230f,
-  0.987056571305750970f, 0.986559910264775410f, 0.986053963346195440f,
-  0.985538735312176060f,
-  0.985014231012239840f, 0.984480455383220930f, 0.983937413449218920f,
-  0.983385110321551180f,
-  0.982823551198705240f, 0.982252741366289370f, 0.981672686196983110f,
-  0.981083391150486710f,
-  0.980484861773469380f, 0.979877103699517640f, 0.979260122649082020f,
-  0.978633924429423210f,
-  0.977998514934557140f, 0.977353900145199960f, 0.976700086128711840f,
-  0.976037079039039020f,
-  0.975364885116656980f, 0.974683510688510670f, 0.973992962167955830f,
-  0.973293246054698250f,
-  0.972584368934732210f, 0.971866337480279400f, 0.971139158449725090f,
-  0.970402838687555500f,
-  0.969657385124292450f, 0.968902804776428870f, 0.968139104746362440f,
-  0.967366292222328510f,
-  0.966584374478333120f, 0.965793358874083680f, 0.964993252854920320f,
-  0.964184063951745830f,
-  0.963365799780954050f, 0.962538468044359160f, 0.961702076529122540f,
-  0.960856633107679660f,
-  0.960002145737665960f, 0.959138622461841890f, 0.958266071408017670f,
-  0.957384500788975860f,
-  0.956493918902395100f, 0.955594334130771110f, 0.954685754941338340f,
-  0.953768189885990330f,
-  0.952841647601198720f, 0.951906136807932350f, 0.950961666311575080f,
-  0.950008245001843000f,
-  0.949045881852700560f, 0.948074585922276230f, 0.947094366352777220f,
-  0.946105232370403450f,
-  0.945107193285260610f, 0.944100258491272660f, 0.943084437466093490f,
-  0.942059739771017310f,
-  0.941026175050889260f, 0.939983753034014050f, 0.938932483532064600f,
-  0.937872376439989890f,
-  0.936803441735921560f, 0.935725689481080370f, 0.934639129819680780f,
-  0.933543772978836170f,
-  0.932439629268462360f, 0.931326709081180430f, 0.930205022892219070f,
-  0.929074581259315860f,
-  0.927935394822617890f, 0.926787474304581750f, 0.925630830509872720f,
-  0.924465474325262600f,
-  0.923291416719527640f, 0.922108668743345180f, 0.920917241529189520f,
-  0.919717146291227360f,
-  0.918508394325212250f, 0.917290997008377910f, 0.916064965799331720f,
-  0.914830312237946200f,
-  0.913587047945250810f, 0.912335184623322750f, 0.911074734055176360f,
-  0.909805708104652220f,
-  0.908528118716306120f, 0.907241977915295820f, 0.905947297807268460f,
-  0.904644090578246240f,
-  0.903332368494511820f, 0.902012143902493180f, 0.900683429228646970f,
-  0.899346236979341570f,
-  0.898000579740739880f, 0.896646470178680150f, 0.895283921038557580f,
-  0.893912945145203250f,
-  0.892533555402764580f, 0.891145764794583180f, 0.889749586383072780f,
-  0.888345033309596350f,
-  0.886932118794342190f, 0.885510856136199950f, 0.884081258712634990f,
-  0.882643339979562790f,
-  0.881197113471222090f, 0.879742592800047410f, 0.878279791656541580f,
-  0.876808723809145650f,
-  0.875329403104110890f, 0.873841843465366860f, 0.872346058894391540f,
-  0.870842063470078980f,
-  0.869329871348606840f, 0.867809496763303320f, 0.866280954024512990f,
-  0.864744257519462380f,
-  0.863199421712124160f, 0.861646461143081300f, 0.860085390429390140f,
-  0.858516224264442740f,
-  0.856938977417828760f, 0.855353664735196030f, 0.853760301138111410f,
-  0.852158901623919830f,
-  0.850549481265603480f, 0.848932055211639610f, 0.847306638685858320f,
-  0.845673246987299070f,
-  0.844031895490066410f, 0.842382599643185850f, 0.840725374970458070f,
-  0.839060237070312740f,
-  0.837387201615661940f, 0.835706284353752600f, 0.834017501106018130f,
-  0.832320867767929680f,
-  0.830616400308846310f, 0.828904114771864870f, 0.827184027273669130f,
-  0.825456154004377550f,
-  0.823720511227391430f, 0.821977115279241550f, 0.820225982569434690f,
-  0.818467129580298660f,
-  0.816700572866827850f, 0.814926329056526620f, 0.813144414849253590f,
-  0.811354847017063730f,
-  0.809557642404051260f, 0.807752817926190360f, 0.805940390571176280f,
-  0.804120377398265810f,
-  0.802292795538115720f, 0.800457662192622820f, 0.798614994634760820f,
-  0.796764810208418830f,
-  0.794907126328237010f, 0.793041960479443640f, 0.791169330217690200f,
-  0.789289253168885650f,
-  0.787401747029031430f, 0.785506829564053930f, 0.783604518609638200f,
-  0.781694832071059390f,
-  0.779777787923014550f, 0.777853404209453150f, 0.775921699043407690f,
-  0.773982690606822900f,
-  0.772036397150384520f, 0.770082836993347900f, 0.768122028523365420f,
-  0.766153990196312920f,
-  0.764178740536116670f, 0.762196298134578900f, 0.760206681651202420f,
-  0.758209909813015280f,
-  0.756206001414394540f, 0.754194975316889170f, 0.752176850449042810f,
-  0.750151645806215070f,
-  0.748119380450403600f, 0.746080073510063780f, 0.744033744179929290f,
-  0.741980411720831070f,
-  0.739920095459516200f, 0.737852814788465980f, 0.735778589165713590f,
-  0.733697438114660370f,
-  0.731609381223892630f, 0.729514438146997010f, 0.727412628602375770f,
-  0.725303972373060770f,
-  0.723188489306527460f, 0.721066199314508110f, 0.718937122372804490f,
-  0.716801278521099540f,
-  0.714658687862769090f, 0.712509370564692320f, 0.710353346857062420f,
-  0.708190637033195400f,
-  0.706021261449339740f, 0.703845240524484940f, 0.701662594740168570f,
-  0.699473344640283770f,
-  0.697277510830886630f, 0.695075113980000880f, 0.692866174817424740f,
-  0.690650714134534720f,
-  0.688428752784090550f, 0.686200311680038700f, 0.683965411797315510f,
-  0.681724074171649820f,
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-  0.672694769070772970f,
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-  0.663564158612039880f,
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-  0.654333617831800550f,
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-  0.645004536815544040f,
-  0.642657033966226860f, 0.640303482184151670f, 0.637943903621844170f,
-  0.635578320488556230f,
-  0.633206755050057190f, 0.630829229628424470f, 0.628445766601832710f,
-  0.626056388404343520f,
-  0.623661117525694640f, 0.621259976511087660f, 0.618852987960976320f,
-  0.616440174530853650f,
-  0.614021558931038490f, 0.611597163926462020f, 0.609167012336453210f,
-  0.606731127034524480f,
-  0.604289530948156070f, 0.601842247058580030f, 0.599389298400564540f,
-  0.596930708062196500f,
-  0.594466499184664540f, 0.591996694962040990f, 0.589521318641063940f,
-  0.587040393520918080f,
-  0.584553942953015330f, 0.582061990340775550f, 0.579564559139405740f,
-  0.577061672855679550f,
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-  0.566996048825108680f,
-  0.564466241520519500f, 0.561931121244689470f, 0.559390711859136140f,
-  0.556845037275160100f,
-  0.554294121453620110f, 0.551737988404707450f, 0.549176662187719770f,
-  0.546610166910834860f,
-  0.544038526730883930f, 0.541461765853123560f, 0.538879908531008420f,
-  0.536292979065963180f,
-  0.533701001807152960f, 0.531104001151255000f, 0.528502001542228480f,
-  0.525895027471084740f,
-  0.523283103475656430f, 0.520666254140367270f, 0.518044504095999340f,
-  0.515417878019463150f,
-  0.512786400633563070f, 0.510150096706766700f, 0.507508991052970870f,
-  0.504863108531267480f,
-  0.502212474045710900f, 0.499557112545081890f, 0.496897049022654640f,
-  0.494232308515959730f,
-  0.491562916106550060f, 0.488888896919763230f, 0.486210276124486530f,
-  0.483527078932918740f,
-  0.480839330600333900f, 0.478147056424843120f, 0.475450281747155870f,
-  0.472749031950342900f,
-  0.470043332459595620f, 0.467333208741988530f, 0.464618686306237820f,
-  0.461899790702462840f,
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-  0.450980989045103810f,
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-  0.439994271309633260f,
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-  0.428941292055329550f,
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-  0.417823715820212380f,
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-  0.406643216870369140f,
-  0.403838457567654130f, 0.401029897183575790f, 0.398217562153373620f,
-  0.395401478947816300f,
-  0.392581674072951530f, 0.389758174069856410f, 0.386931005514388690f,
-  0.384100195016935040f,
-  0.381265769222162490f, 0.378427754808765620f, 0.375586178489217330f,
-  0.372741067009515810f,
-  0.369892447148934270f, 0.367040345719767240f, 0.364184789567079840f,
-  0.361325805568454340f,
-  0.358463420633736540f, 0.355597661704783960f, 0.352728555755210730f,
-  0.349856129790135030f,
-  0.346980410845923680f, 0.344101425989938980f, 0.341219202320282410f,
-  0.338333766965541290f,
-  0.335445147084531660f, 0.332553369866044220f, 0.329658462528587550f,
-  0.326760452320131790f,
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-  0.315137928752522440f,
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-  0.303467946572011370f,
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-  0.291752263234989370f,
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-  0.279992643080273380f,
-  0.277046080306099950f, 0.274096909868706330f, 0.271145159526808070f,
-  0.268190857063403180f,
-  0.265234030285511900f, 0.262274707023913590f, 0.259312915132886350f,
-  0.256348682489942910f,
-  0.253382036995570270f, 0.250413006572965280f, 0.247441619167773440f,
-  0.244467902747824210f,
-  0.241491885302869300f, 0.238513594844318500f, 0.235533059404975460f,
-  0.232550307038775330f,
-  0.229565365820518870f, 0.226578263845610110f, 0.223589029229790020f,
-  0.220597690108873650f,
-  0.217604274638483670f, 0.214608810993786920f, 0.211611327369227610f,
-  0.208611851978263460f,
-  0.205610413053099320f, 0.202607038844421110f, 0.199601757621131050f,
-  0.196594597670080220f,
-  0.193585587295803750f, 0.190574754820252800f, 0.187562128582529740f,
-  0.184547736938619640f,
-  0.181531608261125130f, 0.178513770938997590f, 0.175494253377271400f,
-  0.172473083996796030f,
-  0.169450291233967930f, 0.166425903540464220f, 0.163399949382973230f,
-  0.160372457242928400f,
-  0.157343455616238280f, 0.154312973013020240f, 0.151281037957330250f,
-  0.148247678986896200f,
-  0.145212924652847520f, 0.142176803519448000f, 0.139139344163826280f,
-  0.136100575175706200f,
-  0.133060525157139180f, 0.130019222722233350f, 0.126976696496885980f,
-  0.123932975118512200f,
-  0.120888087235777220f, 0.117842061508325020f, 0.114794926606510250f,
-  0.111746711211126660f,
-  0.108697444013138670f, 0.105647153713410700f, 0.102595869022436280f,
-  0.099543618660069444f,
-  0.096490431355252607f, 0.093436335845747912f, 0.090381360877865011f,
-  0.087325535206192226f,
-  0.084268887593324127f, 0.081211446809592386f, 0.078153241632794315f,
-  0.075094300847921291f,
-  0.072034653246889416f, 0.068974327628266732f, 0.065913352797003930f,
-  0.062851757564161420f,
-  0.059789570746640007f, 0.056726821166907783f, 0.053663537652730679f,
-  0.050599749036899337f,
-  0.047535484156959261f, 0.044470771854938744f, 0.041405640977076712f,
-  0.038340120373552791f,
-  0.035274238898213947f, 0.032208025408304704f, 0.029141508764193740f,
-  0.026074717829104040f,
-  0.023007681468839410f, 0.019940428551514598f, 0.016872987947281773f,
-  0.013805388528060349f,
-  0.010737659167264572f, 0.007669828739531077f, 0.004601926120448672f,
-  0.001533980186284766f
-};
-
-static const float32_t cos_factors_2048[2048] = {
-  0.999999926465717890f, 0.999999338191525530f, 0.999998161643486980f,
-  0.999996396822294350f,
-  0.999994043728985820f, 0.999991102364945590f, 0.999987572731904080f,
-  0.999983454831937730f,
-  0.999978748667468830f, 0.999973454241265940f, 0.999967571556443780f,
-  0.999961100616462820f,
-  0.999954041425129780f, 0.999946393986597460f, 0.999938158305364590f,
-  0.999929334386276070f,
-  0.999919922234522750f, 0.999909921855641540f, 0.999899333255515390f,
-  0.999888156440373320f,
-  0.999876391416790410f, 0.999864038191687680f, 0.999851096772332190f,
-  0.999837567166337090f,
-  0.999823449381661570f, 0.999808743426610520f, 0.999793449309835270f,
-  0.999777567040332940f,
-  0.999761096627446610f, 0.999744038080865430f, 0.999726391410624470f,
-  0.999708156627104880f,
-  0.999689333741033640f, 0.999669922763483760f, 0.999649923705874240f,
-  0.999629336579970110f,
-  0.999608161397882110f, 0.999586398172067070f, 0.999564046915327740f,
-  0.999541107640812940f,
-  0.999517580362016990f, 0.999493465092780590f, 0.999468761847290050f,
-  0.999443470640077770f,
-  0.999417591486021720f, 0.999391124400346050f, 0.999364069398620550f,
-  0.999336426496761240f,
-  0.999308195711029470f, 0.999279377058032710f, 0.999249970554724420f,
-  0.999219976218403530f,
-  0.999189394066714920f, 0.999158224117649430f, 0.999126466389543390f,
-  0.999094120901079070f,
-  0.999061187671284600f, 0.999027666719533690f, 0.998993558065545680f,
-  0.998958861729386080f,
-  0.998923577731465780f, 0.998887706092541290f, 0.998851246833715180f,
-  0.998814199976435390f,
-  0.998776565542495610f, 0.998738343554035230f, 0.998699534033539280f,
-  0.998660137003838490f,
-  0.998620152488108870f, 0.998579580509872500f, 0.998538421092996730f,
-  0.998496674261694640f,
-  0.998454340040524800f, 0.998411418454391300f, 0.998367909528543820f,
-  0.998323813288577560f,
-  0.998279129760433200f, 0.998233858970396850f, 0.998188000945100300f,
-  0.998141555711520520f,
-  0.998094523296980010f, 0.998046903729146840f, 0.997998697036034390f,
-  0.997949903246001190f,
-  0.997900522387751620f, 0.997850554490335110f, 0.997799999583146470f,
-  0.997748857695925690f,
-  0.997697128858758500f, 0.997644813102075420f, 0.997591910456652630f,
-  0.997538420953611340f,
-  0.997484344624417930f, 0.997429681500884180f, 0.997374431615167150f,
-  0.997318594999768600f,
-  0.997262171687536170f, 0.997205161711661850f, 0.997147565105683480f,
-  0.997089381903483400f,
-  0.997030612139289450f, 0.996971255847674320f, 0.996911313063555740f,
-  0.996850783822196610f,
-  0.996789668159204560f, 0.996727966110532490f, 0.996665677712478160f,
-  0.996602803001684130f,
-  0.996539342015137940f, 0.996475294790172160f, 0.996410661364464100f,
-  0.996345441776035900f,
-  0.996279636063254650f, 0.996213244264832040f, 0.996146266419824620f,
-  0.996078702567633980f,
-  0.996010552748005870f, 0.995941817001031350f, 0.995872495367145730f,
-  0.995802587887129160f,
-  0.995732094602106430f, 0.995661015553546910f, 0.995589350783264600f,
-  0.995517100333418110f,
-  0.995444264246510340f, 0.995370842565388990f, 0.995296835333246090f,
-  0.995222242593618360f,
-  0.995147064390386470f, 0.995071300767776170f, 0.994994951770357020f,
-  0.994918017443043200f,
-  0.994840497831093180f, 0.994762392980109930f, 0.994683702936040250f,
-  0.994604427745175660f,
-  0.994524567454151740f, 0.994444122109948040f, 0.994363091759888570f,
-  0.994281476451641550f,
-  0.994199276233218910f, 0.994116491152977070f, 0.994033121259616400f,
-  0.993949166602181130f,
-  0.993864627230059750f, 0.993779503192984580f, 0.993693794541031790f,
-  0.993607501324621610f,
-  0.993520623594518090f, 0.993433161401829360f, 0.993345114798006910f,
-  0.993256483834846440f,
-  0.993167268564487230f, 0.993077469039412300f, 0.992987085312448390f,
-  0.992896117436765980f,
-  0.992804565465879140f, 0.992712429453645460f, 0.992619709454266140f,
-  0.992526405522286100f,
-  0.992432517712593660f, 0.992338046080420420f, 0.992242990681341700f,
-  0.992147351571276090f,
-  0.992051128806485720f, 0.991954322443575950f, 0.991856932539495470f,
-  0.991758959151536110f,
-  0.991660402337333210f, 0.991561262154865290f, 0.991461538662453790f,
-  0.991361231918763460f,
-  0.991260341982802440f, 0.991158868913921350f, 0.991056812771814340f,
-  0.990954173616518500f,
-  0.990850951508413620f, 0.990747146508222710f, 0.990642758677011570f,
-  0.990537788076188750f,
-  0.990432234767505970f, 0.990326098813057330f, 0.990219380275280000f,
-  0.990112079216953770f,
-  0.990004195701200910f, 0.989895729791486660f, 0.989786681551618640f,
-  0.989677051045747210f,
-  0.989566838338365120f, 0.989456043494307710f, 0.989344666578752640f,
-  0.989232707657220050f,
-  0.989120166795572690f, 0.989007044060015270f, 0.988893339517095130f,
-  0.988779053233701520f,
-  0.988664185277066230f, 0.988548735714763200f, 0.988432704614708340f,
-  0.988316092045159690f,
-  0.988198898074717610f, 0.988081122772324070f, 0.987962766207263420f,
-  0.987843828449161740f,
-  0.987724309567986960f, 0.987604209634049160f, 0.987483528717999710f,
-  0.987362266890832400f,
-  0.987240424223882250f, 0.987118000788826280f, 0.986994996657682980f,
-  0.986871411902812470f,
-  0.986747246596916590f, 0.986622500813038480f, 0.986497174624562880f,
-  0.986371268105216030f,
-  0.986244781329065460f, 0.986117714370520090f, 0.985990067304330140f,
-  0.985861840205586980f,
-  0.985733033149723490f, 0.985603646212513400f, 0.985473679470071810f,
-  0.985343132998854790f,
-  0.985212006875659350f, 0.985080301177623800f, 0.984948015982227030f,
-  0.984815151367289140f,
-  0.984681707410970940f, 0.984547684191773960f, 0.984413081788540700f,
-  0.984277900280454370f,
-  0.984142139747038570f, 0.984005800268157870f, 0.983868881924017220f,
-  0.983731384795162090f,
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-  0.983175610055424420f,
-  0.983035220223095640f, 0.982894252096474070f, 0.982752705758487830f,
-  0.982610581292404750f,
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-  0.982036303824369020f,
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-  0.981452783056635520f,
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-  0.980860024481523870f,
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-  0.980258033678303550f,
-  0.980106094103951770f, 0.979953577958436740f, 0.979800485331479790f,
-  0.979646816313141210f,
-  0.979492570993820810f, 0.979337749464256780f, 0.979182351815526930f,
-  0.979026378139047580f,
-  0.978869828526574120f, 0.978712703070200420f, 0.978555001862359550f,
-  0.978396724995823090f,
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-  0.977757862810002760f,
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-  0.977109797594800880f,
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-  0.976452535450054060f,
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-  0.975786082562163930f,
-  0.975618034019781750f, 0.975449411546446380f, 0.975280215241354220f,
-  0.975110445204038890f,
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-  0.974425629735034990f,
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-  0.973731642600896400f,
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-  0.973028490333694210f,
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-  0.972316179551765300f,
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-  0.971594716959650160f,
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-  0.970864109348029470f,
-  0.970680029339806130f, 0.970495378305530560f, 0.970310156353828110f,
-  0.970124363593660280f,
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-  0.969375486659311280f,
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-  0.966288809384209690f,
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-  0.965494383997269500f,
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-  0.963878277983814200f,
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-  0.958812473320129310f,
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-  0.957936538962351420f,
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-  0.945732010777477150f,
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-  0.052514674564603257f,
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-  0.046386267926707213f,
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-  0.037190455560088091f,
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-  0.034124446197403423f,
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-  0.031058115642434700f,
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-  0.024924606404281485f,
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-  0.021857485452021874f,
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-  0.018790158768784596f,
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-  0.015722655225417017f,
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-  0.012655003694430301f,
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-  0.009587233049729183f,
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-  0.003451449920135975f,
-  0.002684463154596083f, 0.001917474809855460f, 0.001150485337113809f,
-  0.000383495187571497f
-};
-
-static const float32_t cos_factors_8192[8192] = {
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-  1.999999255465430200, 1.999998887794072000, 1.999998446588471700,
-    1.999997931848645600,
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-    1.999995137547503600,
-  1.999994255136887000, 1.999993299192198700, 1.999992269713474200,
-    1.999991166700750800,
-  1.999989990154069600, 1.999988740073473500, 1.999987416459008600,
-    1.999986019310723500,
-  1.999984548628669600, 1.999983004412901000, 1.999981386663474400,
-    1.999979695380449400,
-  1.999977930563888100, 1.999976092213855400, 1.999974180330418700,
-    1.999972194913648900,
-  1.999970135963618400, 1.999968003480403000, 1.999965797464081200,
-    1.999963517914734100,
-  1.999961164832445800, 1.999958738217302300, 1.999956238069392900,
-    1.999953664388809800,
-  1.999951017175647600, 1.999948296430003500, 1.999945502151977600,
-    1.999942634341672600,
-  1.999939692999193900, 1.999936678124649700, 1.999933589718150700,
-    1.999930427779810900,
-  1.999927192309745900, 1.999923883308075200, 1.999920500774920300,
-    1.999917044710405500,
-  1.999913515114657900, 1.999909911987807200, 1.999906235329986100,
-    1.999902485141329400,
-  1.999898661421975400, 1.999894764172064600, 1.999890793391740000,
-    1.999886749081147800,
-  1.999882631240436700, 1.999878439869758200, 1.999874174969266300,
-    1.999869836539117700,
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-    1.999851747525188200,
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-    1.999832482050000900,
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-    1.999812040124888700,
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-    1.999790421761877400,
-  1.999784833354177900, 1.999779171420106700, 1.999773435959872000,
-    1.999767626973684400,
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-    1.999743655773719400,
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-    1.999718508176084000,
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-    1.999692184195571900,
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-    1.999664683847668800,
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-    1.999636007148552400,
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-    1.999606154115092500,
-  1.999598507056529000, 1.999590786478444600, 1.999582992381123000,
-    1.999575124764850800,
-  1.999567183629917100, 1.999559168976613900, 1.999551080805236100,
-    1.999542919116081000,
-  1.999534683909448600, 1.999526375185641800, 1.999517992944965800,
-    1.999509537187729200,
-  1.999501007914242600, 1.999492405124819700, 1.999483728819776900,
-    1.999474978999432800,
-  1.999466155664109600, 1.999457258814131500, 1.999448288449825500,
-    1.999439244571521700,
-  1.999430127179552500, 1.999420936274252800, 1.999411671855960900,
-    1.999402333925017300,
-  1.999392922481765500, 1.999383437526551300, 1.999373879059723500,
-    1.999364247081633500,
-  1.999354541592635500, 1.999344762593086500, 1.999334910083345700,
-    1.999324984063775700,
-  1.999314984534741100, 1.999304911496609700, 1.999294764949752100,
-    1.999284544894541100,
-  1.999274251331352400, 1.999263884260564600, 1.999253443682558900,
-    1.999242929597719200,
-  1.999232342006432000, 1.999221680909086400, 1.999210946306074500,
-    1.999200138197791100,
-  1.999189256584633600, 1.999178301467001900, 1.999167272845298900,
-    1.999156170719930100,
-  1.999144995091303600, 1.999133745959830600, 1.999122423325924200,
-    1.999111027190001000,
-  1.999099557552479900, 1.999088014413782800, 1.999076397774334000,
-    1.999064707634560700,
-  1.999052943994892300, 1.999041106855761900, 1.999029196217604100,
-    1.999017212080857400,
-  1.999005154445962200, 1.998993023313361700, 1.998980818683502100,
-    1.998968540556831800,
-  1.998956188933802800, 1.998943763814868800, 1.998931265200486900,
-    1.998918693091116200,
-  1.998906047487219600, 1.998893328389261400, 1.998880535797709700,
-    1.998867669713034500,
-  1.998854730135709400, 1.998841717066209400, 1.998828630505013400,
-    1.998815470452602400,
-  1.998802236909460500, 1.998788929876074100, 1.998775549352932400,
-    1.998762095340527400,
-  1.998748567839354000, 1.998734966849909000, 1.998721292372693100,
-    1.998707544408208700,
-  1.998693722956961500, 1.998679828019459300, 1.998665859596213500,
-    1.998651817687737300,
-  1.998637702294547000, 1.998623513417161700, 1.998609251056103100,
-    1.998594915211895600,
-  1.998580505885066100, 1.998566023076144600, 1.998551466785663400,
-    1.998536837014157900,
-  1.998522133762165900, 1.998507357030227900, 1.998492506818887200,
-    1.998477583128690100,
-  1.998462585960185000, 1.998447515313923400, 1.998432371190459500,
-    1.998417153590349900,
-  1.998401862514154200, 1.998386497962434800, 1.998371059935756300,
-    1.998355548434686400,
-  1.998339963459795400, 1.998324305011656600, 1.998308573090845200,
-    1.998292767697940100,
-  1.998276888833522300, 1.998260936498175400, 1.998244910692486000,
-    1.998228811417043700,
-  1.998212638672439900, 1.998196392459269400, 1.998180072778129600,
-    1.998163679629620500,
-  1.998147213014344900, 1.998130672932908000, 1.998114059385918400,
-    1.998097372373986300,
-  1.998080611897725700, 1.998063777957752600, 1.998046870554686100,
-    1.998029889689147700,
-  1.998012835361761900, 1.997995707573155600, 1.997978506323958600,
-    1.997961231614803200,
-  1.997943883446324800, 1.997926461819161000, 1.997908966733952500,
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-  0.110199032897608850, 0.109816118257049110, 0.109433199578864170,
-    0.109050276877133770,
-  0.108667350165936400, 0.108284419459350770, 0.107901484771457020,
-    0.107518546116333660,
-  0.107135603508061170, 0.106752656960718350, 0.106369706488385940,
-    0.105986752105143480,
-  0.105603793825070680, 0.105220831662248700, 0.104837865630757090,
-    0.104454895744677270,
-  0.104071922018089540, 0.103688944465074300, 0.103305963099713400,
-    0.102922977936087120,
-  0.102539988988277600, 0.102156996270365800, 0.101773999796432830,
-    0.101390999580561250,
-  0.101007995636832020, 0.100624987979327970, 0.100241976622130760,
-    0.099858961579322170,
-  0.099475942864985456, 0.099092920493202258, 0.098709894478056073,
-    0.098326864833628791,
-  0.097943831574004214, 0.097560794713264939, 0.097177754265493674,
-    0.096794710244774623,
-  0.096411662665190329, 0.096028611540825232, 0.095645556885762609,
-    0.095262498714085819,
-  0.094879437039879722, 0.094496371877227495, 0.094113303240214247,
-    0.093730231142923864,
-  0.093347155599440373, 0.092964076623849271, 0.092580994230234359,
-    0.092197908432681386,
-  0.091814819245274432, 0.091431726682099479, 0.091048630757241303,
-    0.090665531484784803,
-  0.090282428878816323, 0.089899322953420582, 0.089516213722684160,
-    0.089133101200692441,
-  0.088749985401530951, 0.088366866339286629, 0.087983744028044805,
-    0.087600618481892656,
-  0.087217489714916191, 0.086834357741201490, 0.086451222574836131,
-    0.086068084229906014,
-  0.085684942720498897, 0.085301798060701386, 0.084918650264600160,
-    0.084535499346283349,
-  0.084152345319837438, 0.083769188199350780, 0.083386027998910095,
-    0.083002864732603973,
-  0.082619698414519799, 0.082236529058745025, 0.081853356679368619,
-    0.081470181290477811,
-  0.081087002906161790, 0.080703821540508452, 0.080320637207605849,
-    0.079937449921543474,
-  0.079554259696409127, 0.079171066546292510, 0.078787870485282088,
-    0.078404671527466441,
-  0.078021469686935602, 0.077638264977777913, 0.077255057414083589,
-    0.076871847009941652,
-  0.076488633779441206, 0.076105417736672773, 0.075722198895725248,
-    0.075338977270689375,
-  0.074955752875654230, 0.074572525724710764, 0.074189295831948693,
-    0.073806063211457842,
-  0.073422827877329483, 0.073039589843653177, 0.072656349124520389,
-    0.072273105734021334,
-  0.071889859686246352, 0.071506610995287156, 0.071123359675233852,
-    0.070740105740178361,
-  0.070356849204211397, 0.069973590081423773, 0.069590328385907715,
-    0.069207064131753759,
-  0.068823797333054326, 0.068440528003900616, 0.068057256158383886,
-    0.067673981810596848,
-  0.067290704974630494, 0.066907425664577733, 0.066524143894529736,
-    0.066140859678579578,
-  0.065757573030819083, 0.065374283965340146, 0.064990992496236119,
-    0.064607698637598646,
-  0.064224402403521202, 0.063841103808096086, 0.063457802865415636,
-    0.063074499589573618,
-  0.062691193994662109, 0.062307886094775049, 0.061924575904005130,
-    0.061541263436445129,
-  0.061157948706189229, 0.060774631727329942, 0.060391312513961619,
-    0.060007991080177375,
-  0.059624667440070382, 0.059241341607735261, 0.058858013597264912,
-    0.058474683422754095,
-  0.058091351098295878, 0.057708016637985186, 0.057324680055915692,
-    0.056941341366181127,
-  0.056558000582876661, 0.056174657720095743, 0.055791312791933681,
-    0.055407965812484541,
-  0.055024616795842439, 0.054641265756102911, 0.054257912707359794,
-    0.053874557663708772,
-  0.053491200639244271, 0.053107841648060788, 0.052724480704254229,
-    0.052341117821918783,
-  0.051957753015150501, 0.051574386298044173, 0.051191017684694640,
-    0.050807647189198162,
-  0.050424274825649297, 0.050040900608144430, 0.049657524550778251,
-    0.049274146667647289,
-  0.048890766972846805, 0.048507385480472134, 0.048124002204620014,
-    0.047740617159385448,
-  0.047357230358865306, 0.046973841817155179, 0.046590451548350717,
-    0.046207059566548990,
-  0.045823665885845313, 0.045440270520336883, 0.045056873484119603,
-    0.044673474791289434,
-  0.044290074455943754, 0.043906672492178188, 0.043523268914090238,
-    0.043139863735776100,
-  0.042756456971332048, 0.042373048634855741, 0.041989638740443119,
-    0.041606227302191955,
-  0.041222814334198304, 0.040839399850560058, 0.040455983865373815,
-    0.040072566392736257,
-  0.039689147446745419, 0.039305727041497644, 0.038922305191091085,
-    0.038538881909622631,
-  0.038155457211189216, 0.037772031109889144, 0.037388603619819022,
-    0.037005174755077273,
-  0.036621744529761024, 0.036238312957967478, 0.035854880053795196,
-    0.035471445831341021,
-  0.035088010304703626, 0.034704573487980395, 0.034321135395268765,
-    0.033937696040667535,
-  0.033554255438273790, 0.033170813602186440, 0.032787370546502645,
-    0.032403926285321405,
-  0.032020480832740429, 0.031637034202857461, 0.031253586409771626,
-    0.030870137467580314,
-  0.030486687390382738, 0.030103236192276818, 0.029719783887360508,
-    0.029336330489733147,
-  0.028952876013492331, 0.028569420472737472, 0.028185963881566689,
-    0.027802506254078142,
-  0.027419047604371360, 0.027035587946544135, 0.026652127294696067,
-    0.026268665662925468,
-  0.025885203065330677, 0.025501739516011413, 0.025118275029065638,
-    0.024734809618593138,
-  0.024351343298691951, 0.023967876083461924, 0.023584407987001611,
-    0.023200939023409587,
-  0.022817469206785804, 0.022433998551228459, 0.022050527070837558,
-    0.021667054779711814,
-  0.021283581691949955, 0.020900107821652084, 0.020516633182916549,
-    0.020133157789843505,
-  0.019749681656531803, 0.019366204797080316, 0.018982727225589285,
-    0.018599248956157190,
-  0.018215770002884327, 0.017832290379869671, 0.017448810101212228,
-    0.017065329181012358,
-  0.016681847633368677, 0.016298365472381587, 0.015914882712149747,
-    0.015531399366773606,
-  0.015147915450352307, 0.014764430976985016, 0.014380945960772247,
-    0.013997460415812761,
-  0.013613974356207112, 0.013230487796054543, 0.012847000749454314,
-    0.012463513230507034,
-  0.012080025253311559, 0.011696536831968529, 0.011313047980577277,
-    0.010929558713237145,
-  0.010546069044048827, 0.010162578987111254, 0.009779088556525145,
-    0.009395597766389905,
-  0.009012106630804949, 0.008628615163871038, 0.008245123379687167,
-    0.007861631292354124,
-  0.007478138915970929, 0.007094646264638386, 0.006711153352455981,
-    0.006327660193523208,
-  0.005944166801940901, 0.005560673191808128, 0.005177179377225743,
-    0.004793685372293270,
-  0.004410191191110246, 0.004026696847777542, 0.003643202356394263,
-    0.003259707731061291,
-  0.002876212985878184, 0.002492718134944503, 0.002109223192361147,
-    0.001725728172227238,
-  0.001342233088643682, 0.000958737955710053, 0.000575242787525925,
-    0.000191747598192208,
-
-};
-
-/**    
- * @brief  Initialization function for the floating-point DCT4/IDCT4.   
- * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.   
- * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.   
- * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.   
- * @param[in]     N			 length of the DCT4.   
- * @param[in]     Nby2       half of the length of the DCT4.   
- * @param[in]     normalize  normalizing factor.   
- * @return        arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.   
- * \par Normalizing factor:    
- * The normalizing factor is sqrt(2/N), which depends on the size of transform N.    
- * Floating-point normalizing factors are mentioned in the table below for different DCT sizes:    
- * \image html dct4NormalizingF32Table.gif    
- */
-
-arm_status arm_dct4_init_f32(
-  arm_dct4_instance_f32 * S,
-  arm_rfft_instance_f32 * S_RFFT,
-  arm_cfft_radix4_instance_f32 * S_CFFT,
-  uint16_t N,
-  uint16_t Nby2,
-  float32_t normalize)
-{
-  /*  Initialize the default arm status */
-  arm_status status = ARM_MATH_SUCCESS;
-
-  /* Initializing the pointer array with the weight table base addresses of different lengths */
-  float32_t *twiddlePtr[4] =
-    { (float32_t *) Weights_128, (float32_t *) Weights_512,
-    (float32_t *) Weights_2048, (float32_t *) Weights_8192
-  };
-
-  /* Initializing the pointer array with the cos factor table base addresses of different lengths */
-  float32_t *pCosFactor[4] =
-    { (float32_t *) cos_factors_128, (float32_t *) cos_factors_512,
-    (float32_t *) cos_factors_2048, (float32_t *) cos_factors_8192
-  };
-
-  /* Initialize the DCT4 length */
-  S->N = N;
-
-  /* Initialize the half of DCT4 length */
-  S->Nby2 = Nby2;
-
-  /* Initialize the DCT4 Normalizing factor */
-  S->normalize = normalize;
-
-  /* Initialize Real FFT Instance */
-  S->pRfft = S_RFFT;
-
-  /* Initialize Complex FFT Instance */
-  S->pCfft = S_CFFT;
-
-  switch (N)
-  {
-    /* Initialize the table modifier values */
-  case 8192u:
-    S->pTwiddle = twiddlePtr[3];
-    S->pCosFactor = pCosFactor[3];
-    break;
-  case 2048u:
-    S->pTwiddle = twiddlePtr[2];
-    S->pCosFactor = pCosFactor[2];
-    break;
-  case 512u:
-    S->pTwiddle = twiddlePtr[1];
-    S->pCosFactor = pCosFactor[1];
-    break;
-  case 128u:
-    S->pTwiddle = twiddlePtr[0];
-    S->pCosFactor = pCosFactor[0];
-    break;
-  default:
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-
-  /* Initialize the RFFT/RIFFT */
-  arm_rfft_init_f32(S->pRfft, S->pCfft, S->N, 0u, 1u);
-
-  /* return the status of DCT4 Init function */
-  return (status);
-}
-
-/**    
-   * @} end of DCT4_IDCT4 group    
-   */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q15.c
deleted file mode 100644
index 8038716bd7..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q15.c
+++ /dev/null
@@ -1,4276 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_dct4_init_q15.c    
-*    
-* Description:	Initialization function of DCT-4 & IDCT4 Q15    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupTransforms    
- */
-
-/**    
- * @addtogroup DCT4_IDCT4    
- * @{    
- */
-
-/*    
-* @brief  Weights Table    
-*/
-
-/**    
-* \par    
-* Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
    
-* \par    
-* C command to generate the table    
-* 
    
-* for(i = 0; i< N; i++)    
-* {    
-*   weights[2*i]= cos(i*c);    
-*   weights[(2*i)+1]= -sin(i * c);    
-* } 
    
-* \par    
-* where N is the Number of weights to be calculated and c is pi/(2*N)    
-* \par    
-* Converted the output to q15 format by multiplying with 2^31 and saturated if required.    
-* \par    
-* In the tables below the real and imaginary values are placed alternatively, hence the    
-* array length is 2*N.    
-*/
-
-static const q15_t ALIGN4 WeightsQ15_128[256] = {
-  0x7fff, 0x0, 0x7ffd, 0xfe6e, 0x7ff6, 0xfcdc, 0x7fe9, 0xfb4a,
-  0x7fd8, 0xf9b9, 0x7fc2, 0xf827, 0x7fa7, 0xf696, 0x7f87, 0xf505,
-  0x7f62, 0xf375, 0x7f38, 0xf1e5, 0x7f09, 0xf055, 0x7ed5, 0xeec7,
-  0x7e9d, 0xed38, 0x7e5f, 0xebab, 0x7e1d, 0xea1e, 0x7dd6, 0xe893,
-  0x7d8a, 0xe708, 0x7d39, 0xe57e, 0x7ce3, 0xe3f5, 0x7c89, 0xe26d,
-  0x7c29, 0xe0e7, 0x7bc5, 0xdf61, 0x7b5d, 0xdddd, 0x7aef, 0xdc5a,
-  0x7a7d, 0xdad8, 0x7a05, 0xd958, 0x798a, 0xd7da, 0x7909, 0xd65d,
-  0x7884, 0xd4e1, 0x77fa, 0xd368, 0x776c, 0xd1ef, 0x76d9, 0xd079,
-  0x7641, 0xcf05, 0x75a5, 0xcd92, 0x7504, 0xcc22, 0x745f, 0xcab3,
-  0x73b5, 0xc946, 0x7307, 0xc7dc, 0x7255, 0xc674, 0x719e, 0xc50e,
-  0x70e2, 0xc3aa, 0x7023, 0xc248, 0x6f5f, 0xc0e9, 0x6e96, 0xbf8d,
-  0x6dca, 0xbe32, 0x6cf9, 0xbcdb, 0x6c24, 0xbb86, 0x6b4a, 0xba33,
-  0x6a6d, 0xb8e4, 0x698c, 0xb797, 0x68a6, 0xb64c, 0x67bd, 0xb505,
-  0x66cf, 0xb3c1, 0x65dd, 0xb27f, 0x64e8, 0xb141, 0x63ef, 0xb005,
-  0x62f2, 0xaecd, 0x61f1, 0xad97, 0x60ec, 0xac65, 0x5fe3, 0xab36,
-  0x5ed7, 0xaa0b, 0x5dc7, 0xa8e3, 0x5cb4, 0xa7be, 0x5b9d, 0xa69c,
-  0x5a82, 0xa57e, 0x5964, 0xa463, 0x5842, 0xa34c, 0x571d, 0xa239,
-  0x55f5, 0xa129, 0x54ca, 0xa01d, 0x539b, 0x9f14, 0x5269, 0x9e0f,
-  0x5133, 0x9d0e, 0x4ffb, 0x9c11, 0x4ebf, 0x9b18, 0x4d81, 0x9a23,
-  0x4c3f, 0x9931, 0x4afb, 0x9843, 0x49b4, 0x975a, 0x4869, 0x9674,
-  0x471c, 0x9593, 0x45cd, 0x94b6, 0x447a, 0x93dc, 0x4325, 0x9307,
-  0x41ce, 0x9236, 0x4073, 0x916a, 0x3f17, 0x90a1, 0x3db8, 0x8fdd,
-  0x3c56, 0x8f1e, 0x3af2, 0x8e62, 0x398c, 0x8dab, 0x3824, 0x8cf9,
-  0x36ba, 0x8c4b, 0x354d, 0x8ba1, 0x33de, 0x8afc, 0x326e, 0x8a5b,
-  0x30fb, 0x89bf, 0x2f87, 0x8927, 0x2e11, 0x8894, 0x2c98, 0x8806,
-  0x2b1f, 0x877c, 0x29a3, 0x86f7, 0x2826, 0x8676, 0x26a8, 0x85fb,
-  0x2528, 0x8583, 0x23a6, 0x8511, 0x2223, 0x84a3, 0x209f, 0x843b,
-  0x1f19, 0x83d7, 0x1d93, 0x8377, 0x1c0b, 0x831d, 0x1a82, 0x82c7,
-  0x18f8, 0x8276, 0x176d, 0x822a, 0x15e2, 0x81e3, 0x1455, 0x81a1,
-  0x12c8, 0x8163, 0x1139, 0x812b, 0xfab, 0x80f7, 0xe1b, 0x80c8,
-  0xc8b, 0x809e, 0xafb, 0x8079, 0x96a, 0x8059, 0x7d9, 0x803e,
-  0x647, 0x8028, 0x4b6, 0x8017, 0x324, 0x800a, 0x192, 0x8003,
-};
-
-static const q15_t ALIGN4 WeightsQ15_512[1024] = {
-  0x7fff, 0x0, 0x7fff, 0xff9c, 0x7fff, 0xff37, 0x7ffe, 0xfed3,
-  0x7ffd, 0xfe6e, 0x7ffc, 0xfe0a, 0x7ffa, 0xfda5, 0x7ff8, 0xfd41,
-  0x7ff6, 0xfcdc, 0x7ff3, 0xfc78, 0x7ff0, 0xfc13, 0x7fed, 0xfbaf,
-  0x7fe9, 0xfb4a, 0x7fe5, 0xfae6, 0x7fe1, 0xfa81, 0x7fdd, 0xfa1d,
-  0x7fd8, 0xf9b9, 0x7fd3, 0xf954, 0x7fce, 0xf8f0, 0x7fc8, 0xf88b,
-  0x7fc2, 0xf827, 0x7fbc, 0xf7c3, 0x7fb5, 0xf75e, 0x7fae, 0xf6fa,
-  0x7fa7, 0xf696, 0x7f9f, 0xf632, 0x7f97, 0xf5cd, 0x7f8f, 0xf569,
-  0x7f87, 0xf505, 0x7f7e, 0xf4a1, 0x7f75, 0xf43d, 0x7f6b, 0xf3d9,
-  0x7f62, 0xf375, 0x7f58, 0xf311, 0x7f4d, 0xf2ad, 0x7f43, 0xf249,
-  0x7f38, 0xf1e5, 0x7f2d, 0xf181, 0x7f21, 0xf11d, 0x7f15, 0xf0b9,
-  0x7f09, 0xf055, 0x7efd, 0xeff2, 0x7ef0, 0xef8e, 0x7ee3, 0xef2a,
-  0x7ed5, 0xeec7, 0x7ec8, 0xee63, 0x7eba, 0xedff, 0x7eab, 0xed9c,
-  0x7e9d, 0xed38, 0x7e8e, 0xecd5, 0x7e7f, 0xec72, 0x7e6f, 0xec0e,
-  0x7e5f, 0xebab, 0x7e4f, 0xeb48, 0x7e3f, 0xeae5, 0x7e2e, 0xea81,
-  0x7e1d, 0xea1e, 0x7e0c, 0xe9bb, 0x7dfa, 0xe958, 0x7de8, 0xe8f6,
-  0x7dd6, 0xe893, 0x7dc3, 0xe830, 0x7db0, 0xe7cd, 0x7d9d, 0xe76a,
-  0x7d8a, 0xe708, 0x7d76, 0xe6a5, 0x7d62, 0xe643, 0x7d4e, 0xe5e0,
-  0x7d39, 0xe57e, 0x7d24, 0xe51c, 0x7d0f, 0xe4b9, 0x7cf9, 0xe457,
-  0x7ce3, 0xe3f5, 0x7ccd, 0xe393, 0x7cb7, 0xe331, 0x7ca0, 0xe2cf,
-  0x7c89, 0xe26d, 0x7c71, 0xe20b, 0x7c5a, 0xe1aa, 0x7c42, 0xe148,
-  0x7c29, 0xe0e7, 0x7c11, 0xe085, 0x7bf8, 0xe024, 0x7bdf, 0xdfc2,
-  0x7bc5, 0xdf61, 0x7bac, 0xdf00, 0x7b92, 0xde9f, 0x7b77, 0xde3e,
-  0x7b5d, 0xdddd, 0x7b42, 0xdd7c, 0x7b26, 0xdd1b, 0x7b0b, 0xdcbb,
-  0x7aef, 0xdc5a, 0x7ad3, 0xdbf9, 0x7ab6, 0xdb99, 0x7a9a, 0xdb39,
-  0x7a7d, 0xdad8, 0x7a5f, 0xda78, 0x7a42, 0xda18, 0x7a24, 0xd9b8,
-  0x7a05, 0xd958, 0x79e7, 0xd8f9, 0x79c8, 0xd899, 0x79a9, 0xd839,
-  0x798a, 0xd7da, 0x796a, 0xd77a, 0x794a, 0xd71b, 0x792a, 0xd6bc,
-  0x7909, 0xd65d, 0x78e8, 0xd5fe, 0x78c7, 0xd59f, 0x78a6, 0xd540,
-  0x7884, 0xd4e1, 0x7862, 0xd483, 0x7840, 0xd424, 0x781d, 0xd3c6,
-  0x77fa, 0xd368, 0x77d7, 0xd309, 0x77b4, 0xd2ab, 0x7790, 0xd24d,
-  0x776c, 0xd1ef, 0x7747, 0xd192, 0x7723, 0xd134, 0x76fe, 0xd0d7,
-  0x76d9, 0xd079, 0x76b3, 0xd01c, 0x768e, 0xcfbf, 0x7668, 0xcf62,
-  0x7641, 0xcf05, 0x761b, 0xcea8, 0x75f4, 0xce4b, 0x75cc, 0xcdef,
-  0x75a5, 0xcd92, 0x757d, 0xcd36, 0x7555, 0xccda, 0x752d, 0xcc7e,
-  0x7504, 0xcc22, 0x74db, 0xcbc6, 0x74b2, 0xcb6a, 0x7489, 0xcb0e,
-  0x745f, 0xcab3, 0x7435, 0xca58, 0x740b, 0xc9fc, 0x73e0, 0xc9a1,
-  0x73b5, 0xc946, 0x738a, 0xc8ec, 0x735f, 0xc891, 0x7333, 0xc836,
-  0x7307, 0xc7dc, 0x72db, 0xc782, 0x72af, 0xc728, 0x7282, 0xc6ce,
-  0x7255, 0xc674, 0x7227, 0xc61a, 0x71fa, 0xc5c0, 0x71cc, 0xc567,
-  0x719e, 0xc50e, 0x716f, 0xc4b4, 0x7141, 0xc45b, 0x7112, 0xc403,
-  0x70e2, 0xc3aa, 0x70b3, 0xc351, 0x7083, 0xc2f9, 0x7053, 0xc2a0,
-  0x7023, 0xc248, 0x6ff2, 0xc1f0, 0x6fc1, 0xc198, 0x6f90, 0xc141,
-  0x6f5f, 0xc0e9, 0x6f2d, 0xc092, 0x6efb, 0xc03b, 0x6ec9, 0xbfe3,
-  0x6e96, 0xbf8d, 0x6e63, 0xbf36, 0x6e30, 0xbedf, 0x6dfd, 0xbe89,
-  0x6dca, 0xbe32, 0x6d96, 0xbddc, 0x6d62, 0xbd86, 0x6d2d, 0xbd30,
-  0x6cf9, 0xbcdb, 0x6cc4, 0xbc85, 0x6c8f, 0xbc30, 0x6c59, 0xbbdb,
-  0x6c24, 0xbb86, 0x6bee, 0xbb31, 0x6bb8, 0xbadc, 0x6b81, 0xba88,
-  0x6b4a, 0xba33, 0x6b13, 0xb9df, 0x6adc, 0xb98b, 0x6aa5, 0xb937,
-  0x6a6d, 0xb8e4, 0x6a35, 0xb890, 0x69fd, 0xb83d, 0x69c4, 0xb7ea,
-  0x698c, 0xb797, 0x6953, 0xb744, 0x6919, 0xb6f1, 0x68e0, 0xb69f,
-  0x68a6, 0xb64c, 0x686c, 0xb5fa, 0x6832, 0xb5a8, 0x67f7, 0xb557,
-  0x67bd, 0xb505, 0x6782, 0xb4b4, 0x6746, 0xb462, 0x670b, 0xb411,
-  0x66cf, 0xb3c1, 0x6693, 0xb370, 0x6657, 0xb31f, 0x661a, 0xb2cf,
-  0x65dd, 0xb27f, 0x65a0, 0xb22f, 0x6563, 0xb1df, 0x6526, 0xb190,
-  0x64e8, 0xb141, 0x64aa, 0xb0f1, 0x646c, 0xb0a2, 0x642d, 0xb054,
-  0x63ef, 0xb005, 0x63b0, 0xafb7, 0x6371, 0xaf69, 0x6331, 0xaf1b,
-  0x62f2, 0xaecd, 0x62b2, 0xae7f, 0x6271, 0xae32, 0x6231, 0xade4,
-  0x61f1, 0xad97, 0x61b0, 0xad4b, 0x616f, 0xacfe, 0x612d, 0xacb2,
-  0x60ec, 0xac65, 0x60aa, 0xac19, 0x6068, 0xabcd, 0x6026, 0xab82,
-  0x5fe3, 0xab36, 0x5fa0, 0xaaeb, 0x5f5e, 0xaaa0, 0x5f1a, 0xaa55,
-  0x5ed7, 0xaa0b, 0x5e93, 0xa9c0, 0x5e50, 0xa976, 0x5e0b, 0xa92c,
-  0x5dc7, 0xa8e3, 0x5d83, 0xa899, 0x5d3e, 0xa850, 0x5cf9, 0xa807,
-  0x5cb4, 0xa7be, 0x5c6e, 0xa775, 0x5c29, 0xa72c, 0x5be3, 0xa6e4,
-  0x5b9d, 0xa69c, 0x5b56, 0xa654, 0x5b10, 0xa60d, 0x5ac9, 0xa5c5,
-  0x5a82, 0xa57e, 0x5a3b, 0xa537, 0x59f3, 0xa4f0, 0x59ac, 0xa4aa,
-  0x5964, 0xa463, 0x591c, 0xa41d, 0x58d4, 0xa3d7, 0x588b, 0xa392,
-  0x5842, 0xa34c, 0x57f9, 0xa307, 0x57b0, 0xa2c2, 0x5767, 0xa27d,
-  0x571d, 0xa239, 0x56d4, 0xa1f5, 0x568a, 0xa1b0, 0x5640, 0xa16d,
-  0x55f5, 0xa129, 0x55ab, 0xa0e6, 0x5560, 0xa0a2, 0x5515, 0xa060,
-  0x54ca, 0xa01d, 0x547e, 0x9fda, 0x5433, 0x9f98, 0x53e7, 0x9f56,
-  0x539b, 0x9f14, 0x534e, 0x9ed3, 0x5302, 0x9e91, 0x52b5, 0x9e50,
-  0x5269, 0x9e0f, 0x521c, 0x9dcf, 0x51ce, 0x9d8f, 0x5181, 0x9d4e,
-  0x5133, 0x9d0e, 0x50e5, 0x9ccf, 0x5097, 0x9c8f, 0x5049, 0x9c50,
-  0x4ffb, 0x9c11, 0x4fac, 0x9bd3, 0x4f5e, 0x9b94, 0x4f0f, 0x9b56,
-  0x4ebf, 0x9b18, 0x4e70, 0x9ada, 0x4e21, 0x9a9d, 0x4dd1, 0x9a60,
-  0x4d81, 0x9a23, 0x4d31, 0x99e6, 0x4ce1, 0x99a9, 0x4c90, 0x996d,
-  0x4c3f, 0x9931, 0x4bef, 0x98f5, 0x4b9e, 0x98ba, 0x4b4c, 0x987e,
-  0x4afb, 0x9843, 0x4aa9, 0x9809, 0x4a58, 0x97ce, 0x4a06, 0x9794,
-  0x49b4, 0x975a, 0x4961, 0x9720, 0x490f, 0x96e7, 0x48bc, 0x96ad,
-  0x4869, 0x9674, 0x4816, 0x963c, 0x47c3, 0x9603, 0x4770, 0x95cb,
-  0x471c, 0x9593, 0x46c9, 0x955b, 0x4675, 0x9524, 0x4621, 0x94ed,
-  0x45cd, 0x94b6, 0x4578, 0x947f, 0x4524, 0x9448, 0x44cf, 0x9412,
-  0x447a, 0x93dc, 0x4425, 0x93a7, 0x43d0, 0x9371, 0x437b, 0x933c,
-  0x4325, 0x9307, 0x42d0, 0x92d3, 0x427a, 0x929e, 0x4224, 0x926a,
-  0x41ce, 0x9236, 0x4177, 0x9203, 0x4121, 0x91d0, 0x40ca, 0x919d,
-  0x4073, 0x916a, 0x401d, 0x9137, 0x3fc5, 0x9105, 0x3f6e, 0x90d3,
-  0x3f17, 0x90a1, 0x3ebf, 0x9070, 0x3e68, 0x903f, 0x3e10, 0x900e,
-  0x3db8, 0x8fdd, 0x3d60, 0x8fad, 0x3d07, 0x8f7d, 0x3caf, 0x8f4d,
-  0x3c56, 0x8f1e, 0x3bfd, 0x8eee, 0x3ba5, 0x8ebf, 0x3b4c, 0x8e91,
-  0x3af2, 0x8e62, 0x3a99, 0x8e34, 0x3a40, 0x8e06, 0x39e6, 0x8dd9,
-  0x398c, 0x8dab, 0x3932, 0x8d7e, 0x38d8, 0x8d51, 0x387e, 0x8d25,
-  0x3824, 0x8cf9, 0x37ca, 0x8ccd, 0x376f, 0x8ca1, 0x3714, 0x8c76,
-  0x36ba, 0x8c4b, 0x365f, 0x8c20, 0x3604, 0x8bf5, 0x35a8, 0x8bcb,
-  0x354d, 0x8ba1, 0x34f2, 0x8b77, 0x3496, 0x8b4e, 0x343a, 0x8b25,
-  0x33de, 0x8afc, 0x3382, 0x8ad3, 0x3326, 0x8aab, 0x32ca, 0x8a83,
-  0x326e, 0x8a5b, 0x3211, 0x8a34, 0x31b5, 0x8a0c, 0x3158, 0x89e5,
-  0x30fb, 0x89bf, 0x309e, 0x8998, 0x3041, 0x8972, 0x2fe4, 0x894d,
-  0x2f87, 0x8927, 0x2f29, 0x8902, 0x2ecc, 0x88dd, 0x2e6e, 0x88b9,
-  0x2e11, 0x8894, 0x2db3, 0x8870, 0x2d55, 0x884c, 0x2cf7, 0x8829,
-  0x2c98, 0x8806, 0x2c3a, 0x87e3, 0x2bdc, 0x87c0, 0x2b7d, 0x879e,
-  0x2b1f, 0x877c, 0x2ac0, 0x875a, 0x2a61, 0x8739, 0x2a02, 0x8718,
-  0x29a3, 0x86f7, 0x2944, 0x86d6, 0x28e5, 0x86b6, 0x2886, 0x8696,
-  0x2826, 0x8676, 0x27c7, 0x8657, 0x2767, 0x8638, 0x2707, 0x8619,
-  0x26a8, 0x85fb, 0x2648, 0x85dc, 0x25e8, 0x85be, 0x2588, 0x85a1,
-  0x2528, 0x8583, 0x24c7, 0x8566, 0x2467, 0x854a, 0x2407, 0x852d,
-  0x23a6, 0x8511, 0x2345, 0x84f5, 0x22e5, 0x84da, 0x2284, 0x84be,
-  0x2223, 0x84a3, 0x21c2, 0x8489, 0x2161, 0x846e, 0x2100, 0x8454,
-  0x209f, 0x843b, 0x203e, 0x8421, 0x1fdc, 0x8408, 0x1f7b, 0x83ef,
-  0x1f19, 0x83d7, 0x1eb8, 0x83be, 0x1e56, 0x83a6, 0x1df5, 0x838f,
-  0x1d93, 0x8377, 0x1d31, 0x8360, 0x1ccf, 0x8349, 0x1c6d, 0x8333,
-  0x1c0b, 0x831d, 0x1ba9, 0x8307, 0x1b47, 0x82f1, 0x1ae4, 0x82dc,
-  0x1a82, 0x82c7, 0x1a20, 0x82b2, 0x19bd, 0x829e, 0x195b, 0x828a,
-  0x18f8, 0x8276, 0x1896, 0x8263, 0x1833, 0x8250, 0x17d0, 0x823d,
-  0x176d, 0x822a, 0x170a, 0x8218, 0x16a8, 0x8206, 0x1645, 0x81f4,
-  0x15e2, 0x81e3, 0x157f, 0x81d2, 0x151b, 0x81c1, 0x14b8, 0x81b1,
-  0x1455, 0x81a1, 0x13f2, 0x8191, 0x138e, 0x8181, 0x132b, 0x8172,
-  0x12c8, 0x8163, 0x1264, 0x8155, 0x1201, 0x8146, 0x119d, 0x8138,
-  0x1139, 0x812b, 0x10d6, 0x811d, 0x1072, 0x8110, 0x100e, 0x8103,
-  0xfab, 0x80f7, 0xf47, 0x80eb, 0xee3, 0x80df, 0xe7f, 0x80d3,
-  0xe1b, 0x80c8, 0xdb7, 0x80bd, 0xd53, 0x80b3, 0xcef, 0x80a8,
-  0xc8b, 0x809e, 0xc27, 0x8095, 0xbc3, 0x808b, 0xb5f, 0x8082,
-  0xafb, 0x8079, 0xa97, 0x8071, 0xa33, 0x8069, 0x9ce, 0x8061,
-  0x96a, 0x8059, 0x906, 0x8052, 0x8a2, 0x804b, 0x83d, 0x8044,
-  0x7d9, 0x803e, 0x775, 0x8038, 0x710, 0x8032, 0x6ac, 0x802d,
-  0x647, 0x8028, 0x5e3, 0x8023, 0x57f, 0x801f, 0x51a, 0x801b,
-  0x4b6, 0x8017, 0x451, 0x8013, 0x3ed, 0x8010, 0x388, 0x800d,
-  0x324, 0x800a, 0x2bf, 0x8008, 0x25b, 0x8006, 0x1f6, 0x8004,
-  0x192, 0x8003, 0x12d, 0x8002, 0xc9, 0x8001, 0x64, 0x8001,
-};
-
-static const q15_t ALIGN4 WeightsQ15_2048[4096] = {
-  0x7fff, 0x0, 0x7fff, 0xffe7, 0x7fff, 0xffce, 0x7fff, 0xffb5,
-  0x7fff, 0xff9c, 0x7fff, 0xff83, 0x7fff, 0xff6a, 0x7fff, 0xff51,
-  0x7fff, 0xff37, 0x7fff, 0xff1e, 0x7fff, 0xff05, 0x7ffe, 0xfeec,
-  0x7ffe, 0xfed3, 0x7ffe, 0xfeba, 0x7ffe, 0xfea1, 0x7ffd, 0xfe88,
-  0x7ffd, 0xfe6e, 0x7ffd, 0xfe55, 0x7ffc, 0xfe3c, 0x7ffc, 0xfe23,
-  0x7ffc, 0xfe0a, 0x7ffb, 0xfdf1, 0x7ffb, 0xfdd8, 0x7ffa, 0xfdbe,
-  0x7ffa, 0xfda5, 0x7ff9, 0xfd8c, 0x7ff9, 0xfd73, 0x7ff8, 0xfd5a,
-  0x7ff8, 0xfd41, 0x7ff7, 0xfd28, 0x7ff7, 0xfd0f, 0x7ff6, 0xfcf5,
-  0x7ff6, 0xfcdc, 0x7ff5, 0xfcc3, 0x7ff4, 0xfcaa, 0x7ff4, 0xfc91,
-  0x7ff3, 0xfc78, 0x7ff2, 0xfc5f, 0x7ff2, 0xfc46, 0x7ff1, 0xfc2c,
-  0x7ff0, 0xfc13, 0x7fef, 0xfbfa, 0x7fee, 0xfbe1, 0x7fee, 0xfbc8,
-  0x7fed, 0xfbaf, 0x7fec, 0xfb96, 0x7feb, 0xfb7d, 0x7fea, 0xfb64,
-  0x7fe9, 0xfb4a, 0x7fe8, 0xfb31, 0x7fe7, 0xfb18, 0x7fe6, 0xfaff,
-  0x7fe5, 0xfae6, 0x7fe4, 0xfacd, 0x7fe3, 0xfab4, 0x7fe2, 0xfa9b,
-  0x7fe1, 0xfa81, 0x7fe0, 0xfa68, 0x7fdf, 0xfa4f, 0x7fde, 0xfa36,
-  0x7fdd, 0xfa1d, 0x7fdc, 0xfa04, 0x7fda, 0xf9eb, 0x7fd9, 0xf9d2,
-  0x7fd8, 0xf9b9, 0x7fd7, 0xf9a0, 0x7fd6, 0xf986, 0x7fd4, 0xf96d,
-  0x7fd3, 0xf954, 0x7fd2, 0xf93b, 0x7fd0, 0xf922, 0x7fcf, 0xf909,
-  0x7fce, 0xf8f0, 0x7fcc, 0xf8d7, 0x7fcb, 0xf8be, 0x7fc9, 0xf8a5,
-  0x7fc8, 0xf88b, 0x7fc6, 0xf872, 0x7fc5, 0xf859, 0x7fc3, 0xf840,
-  0x7fc2, 0xf827, 0x7fc0, 0xf80e, 0x7fbf, 0xf7f5, 0x7fbd, 0xf7dc,
-  0x7fbc, 0xf7c3, 0x7fba, 0xf7aa, 0x7fb8, 0xf791, 0x7fb7, 0xf778,
-  0x7fb5, 0xf75e, 0x7fb3, 0xf745, 0x7fb1, 0xf72c, 0x7fb0, 0xf713,
-  0x7fae, 0xf6fa, 0x7fac, 0xf6e1, 0x7faa, 0xf6c8, 0x7fa9, 0xf6af,
-  0x7fa7, 0xf696, 0x7fa5, 0xf67d, 0x7fa3, 0xf664, 0x7fa1, 0xf64b,
-  0x7f9f, 0xf632, 0x7f9d, 0xf619, 0x7f9b, 0xf600, 0x7f99, 0xf5e7,
-  0x7f97, 0xf5cd, 0x7f95, 0xf5b4, 0x7f93, 0xf59b, 0x7f91, 0xf582,
-  0x7f8f, 0xf569, 0x7f8d, 0xf550, 0x7f8b, 0xf537, 0x7f89, 0xf51e,
-  0x7f87, 0xf505, 0x7f85, 0xf4ec, 0x7f82, 0xf4d3, 0x7f80, 0xf4ba,
-  0x7f7e, 0xf4a1, 0x7f7c, 0xf488, 0x7f79, 0xf46f, 0x7f77, 0xf456,
-  0x7f75, 0xf43d, 0x7f72, 0xf424, 0x7f70, 0xf40b, 0x7f6e, 0xf3f2,
-  0x7f6b, 0xf3d9, 0x7f69, 0xf3c0, 0x7f67, 0xf3a7, 0x7f64, 0xf38e,
-  0x7f62, 0xf375, 0x7f5f, 0xf35c, 0x7f5d, 0xf343, 0x7f5a, 0xf32a,
-  0x7f58, 0xf311, 0x7f55, 0xf2f8, 0x7f53, 0xf2df, 0x7f50, 0xf2c6,
-  0x7f4d, 0xf2ad, 0x7f4b, 0xf294, 0x7f48, 0xf27b, 0x7f45, 0xf262,
-  0x7f43, 0xf249, 0x7f40, 0xf230, 0x7f3d, 0xf217, 0x7f3b, 0xf1fe,
-  0x7f38, 0xf1e5, 0x7f35, 0xf1cc, 0x7f32, 0xf1b3, 0x7f2f, 0xf19a,
-  0x7f2d, 0xf181, 0x7f2a, 0xf168, 0x7f27, 0xf14f, 0x7f24, 0xf136,
-  0x7f21, 0xf11d, 0x7f1e, 0xf104, 0x7f1b, 0xf0eb, 0x7f18, 0xf0d2,
-  0x7f15, 0xf0b9, 0x7f12, 0xf0a0, 0x7f0f, 0xf087, 0x7f0c, 0xf06e,
-  0x7f09, 0xf055, 0x7f06, 0xf03c, 0x7f03, 0xf023, 0x7f00, 0xf00b,
-  0x7efd, 0xeff2, 0x7ef9, 0xefd9, 0x7ef6, 0xefc0, 0x7ef3, 0xefa7,
-  0x7ef0, 0xef8e, 0x7eed, 0xef75, 0x7ee9, 0xef5c, 0x7ee6, 0xef43,
-  0x7ee3, 0xef2a, 0x7edf, 0xef11, 0x7edc, 0xeef8, 0x7ed9, 0xeedf,
-  0x7ed5, 0xeec7, 0x7ed2, 0xeeae, 0x7ecf, 0xee95, 0x7ecb, 0xee7c,
-  0x7ec8, 0xee63, 0x7ec4, 0xee4a, 0x7ec1, 0xee31, 0x7ebd, 0xee18,
-  0x7eba, 0xedff, 0x7eb6, 0xede7, 0x7eb3, 0xedce, 0x7eaf, 0xedb5,
-  0x7eab, 0xed9c, 0x7ea8, 0xed83, 0x7ea4, 0xed6a, 0x7ea1, 0xed51,
-  0x7e9d, 0xed38, 0x7e99, 0xed20, 0x7e95, 0xed07, 0x7e92, 0xecee,
-  0x7e8e, 0xecd5, 0x7e8a, 0xecbc, 0x7e86, 0xeca3, 0x7e83, 0xec8a,
-  0x7e7f, 0xec72, 0x7e7b, 0xec59, 0x7e77, 0xec40, 0x7e73, 0xec27,
-  0x7e6f, 0xec0e, 0x7e6b, 0xebf5, 0x7e67, 0xebdd, 0x7e63, 0xebc4,
-  0x7e5f, 0xebab, 0x7e5b, 0xeb92, 0x7e57, 0xeb79, 0x7e53, 0xeb61,
-  0x7e4f, 0xeb48, 0x7e4b, 0xeb2f, 0x7e47, 0xeb16, 0x7e43, 0xeafd,
-  0x7e3f, 0xeae5, 0x7e3b, 0xeacc, 0x7e37, 0xeab3, 0x7e32, 0xea9a,
-  0x7e2e, 0xea81, 0x7e2a, 0xea69, 0x7e26, 0xea50, 0x7e21, 0xea37,
-  0x7e1d, 0xea1e, 0x7e19, 0xea06, 0x7e14, 0xe9ed, 0x7e10, 0xe9d4,
-  0x7e0c, 0xe9bb, 0x7e07, 0xe9a3, 0x7e03, 0xe98a, 0x7dff, 0xe971,
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-  0x2d55, 0x884c, 0x2d3d, 0x8844, 0x2d26, 0x883b, 0x2d0e, 0x8832,
-  0x2cf7, 0x8829, 0x2cdf, 0x8820, 0x2cc8, 0x8817, 0x2cb0, 0x880f,
-  0x2c98, 0x8806, 0x2c81, 0x87fd, 0x2c69, 0x87f4, 0x2c52, 0x87ec,
-  0x2c3a, 0x87e3, 0x2c23, 0x87da, 0x2c0b, 0x87d2, 0x2bf3, 0x87c9,
-  0x2bdc, 0x87c0, 0x2bc4, 0x87b8, 0x2bad, 0x87af, 0x2b95, 0x87a7,
-  0x2b7d, 0x879e, 0x2b66, 0x8795, 0x2b4e, 0x878d, 0x2b36, 0x8784,
-  0x2b1f, 0x877c, 0x2b07, 0x8774, 0x2aef, 0x876b, 0x2ad8, 0x8763,
-  0x2ac0, 0x875a, 0x2aa8, 0x8752, 0x2a91, 0x874a, 0x2a79, 0x8741,
-  0x2a61, 0x8739, 0x2a49, 0x8731, 0x2a32, 0x8728, 0x2a1a, 0x8720,
-  0x2a02, 0x8718, 0x29eb, 0x870f, 0x29d3, 0x8707, 0x29bb, 0x86ff,
-  0x29a3, 0x86f7, 0x298b, 0x86ef, 0x2974, 0x86e7, 0x295c, 0x86de,
-  0x2944, 0x86d6, 0x292c, 0x86ce, 0x2915, 0x86c6, 0x28fd, 0x86be,
-  0x28e5, 0x86b6, 0x28cd, 0x86ae, 0x28b5, 0x86a6, 0x289d, 0x869e,
-  0x2886, 0x8696, 0x286e, 0x868e, 0x2856, 0x8686, 0x283e, 0x867e,
-  0x2826, 0x8676, 0x280e, 0x866e, 0x27f6, 0x8667, 0x27df, 0x865f,
-  0x27c7, 0x8657, 0x27af, 0x864f, 0x2797, 0x8647, 0x277f, 0x8640,
-  0x2767, 0x8638, 0x274f, 0x8630, 0x2737, 0x8628, 0x271f, 0x8621,
-  0x2707, 0x8619, 0x26ef, 0x8611, 0x26d8, 0x860a, 0x26c0, 0x8602,
-  0x26a8, 0x85fb, 0x2690, 0x85f3, 0x2678, 0x85eb, 0x2660, 0x85e4,
-  0x2648, 0x85dc, 0x2630, 0x85d5, 0x2618, 0x85cd, 0x2600, 0x85c6,
-  0x25e8, 0x85be, 0x25d0, 0x85b7, 0x25b8, 0x85b0, 0x25a0, 0x85a8,
-  0x2588, 0x85a1, 0x2570, 0x8599, 0x2558, 0x8592, 0x2540, 0x858b,
-  0x2528, 0x8583, 0x250f, 0x857c, 0x24f7, 0x8575, 0x24df, 0x856e,
-  0x24c7, 0x8566, 0x24af, 0x855f, 0x2497, 0x8558, 0x247f, 0x8551,
-  0x2467, 0x854a, 0x244f, 0x8543, 0x2437, 0x853b, 0x241f, 0x8534,
-  0x2407, 0x852d, 0x23ee, 0x8526, 0x23d6, 0x851f, 0x23be, 0x8518,
-  0x23a6, 0x8511, 0x238e, 0x850a, 0x2376, 0x8503, 0x235e, 0x84fc,
-  0x2345, 0x84f5, 0x232d, 0x84ee, 0x2315, 0x84e7, 0x22fd, 0x84e1,
-  0x22e5, 0x84da, 0x22cd, 0x84d3, 0x22b4, 0x84cc, 0x229c, 0x84c5,
-  0x2284, 0x84be, 0x226c, 0x84b8, 0x2254, 0x84b1, 0x223b, 0x84aa,
-  0x2223, 0x84a3, 0x220b, 0x849d, 0x21f3, 0x8496, 0x21da, 0x848f,
-  0x21c2, 0x8489, 0x21aa, 0x8482, 0x2192, 0x847c, 0x2179, 0x8475,
-  0x2161, 0x846e, 0x2149, 0x8468, 0x2131, 0x8461, 0x2118, 0x845b,
-  0x2100, 0x8454, 0x20e8, 0x844e, 0x20d0, 0x8447, 0x20b7, 0x8441,
-  0x209f, 0x843b, 0x2087, 0x8434, 0x206e, 0x842e, 0x2056, 0x8427,
-  0x203e, 0x8421, 0x2025, 0x841b, 0x200d, 0x8415, 0x1ff5, 0x840e,
-  0x1fdc, 0x8408, 0x1fc4, 0x8402, 0x1fac, 0x83fb, 0x1f93, 0x83f5,
-  0x1f7b, 0x83ef, 0x1f63, 0x83e9, 0x1f4a, 0x83e3, 0x1f32, 0x83dd,
-  0x1f19, 0x83d7, 0x1f01, 0x83d0, 0x1ee9, 0x83ca, 0x1ed0, 0x83c4,
-  0x1eb8, 0x83be, 0x1ea0, 0x83b8, 0x1e87, 0x83b2, 0x1e6f, 0x83ac,
-  0x1e56, 0x83a6, 0x1e3e, 0x83a0, 0x1e25, 0x839a, 0x1e0d, 0x8394,
-  0x1df5, 0x838f, 0x1ddc, 0x8389, 0x1dc4, 0x8383, 0x1dab, 0x837d,
-  0x1d93, 0x8377, 0x1d7a, 0x8371, 0x1d62, 0x836c, 0x1d49, 0x8366,
-  0x1d31, 0x8360, 0x1d18, 0x835a, 0x1d00, 0x8355, 0x1ce8, 0x834f,
-  0x1ccf, 0x8349, 0x1cb7, 0x8344, 0x1c9e, 0x833e, 0x1c86, 0x8338,
-  0x1c6d, 0x8333, 0x1c55, 0x832d, 0x1c3c, 0x8328, 0x1c24, 0x8322,
-  0x1c0b, 0x831d, 0x1bf2, 0x8317, 0x1bda, 0x8312, 0x1bc1, 0x830c,
-  0x1ba9, 0x8307, 0x1b90, 0x8301, 0x1b78, 0x82fc, 0x1b5f, 0x82f7,
-  0x1b47, 0x82f1, 0x1b2e, 0x82ec, 0x1b16, 0x82e7, 0x1afd, 0x82e1,
-  0x1ae4, 0x82dc, 0x1acc, 0x82d7, 0x1ab3, 0x82d1, 0x1a9b, 0x82cc,
-  0x1a82, 0x82c7, 0x1a6a, 0x82c2, 0x1a51, 0x82bd, 0x1a38, 0x82b7,
-  0x1a20, 0x82b2, 0x1a07, 0x82ad, 0x19ef, 0x82a8, 0x19d6, 0x82a3,
-  0x19bd, 0x829e, 0x19a5, 0x8299, 0x198c, 0x8294, 0x1973, 0x828f,
-  0x195b, 0x828a, 0x1942, 0x8285, 0x192a, 0x8280, 0x1911, 0x827b,
-  0x18f8, 0x8276, 0x18e0, 0x8271, 0x18c7, 0x826c, 0x18ae, 0x8268,
-  0x1896, 0x8263, 0x187d, 0x825e, 0x1864, 0x8259, 0x184c, 0x8254,
-  0x1833, 0x8250, 0x181a, 0x824b, 0x1802, 0x8246, 0x17e9, 0x8241,
-  0x17d0, 0x823d, 0x17b7, 0x8238, 0x179f, 0x8233, 0x1786, 0x822f,
-  0x176d, 0x822a, 0x1755, 0x8226, 0x173c, 0x8221, 0x1723, 0x821c,
-  0x170a, 0x8218, 0x16f2, 0x8213, 0x16d9, 0x820f, 0x16c0, 0x820a,
-  0x16a8, 0x8206, 0x168f, 0x8201, 0x1676, 0x81fd, 0x165d, 0x81f9,
-  0x1645, 0x81f4, 0x162c, 0x81f0, 0x1613, 0x81ec, 0x15fa, 0x81e7,
-  0x15e2, 0x81e3, 0x15c9, 0x81df, 0x15b0, 0x81da, 0x1597, 0x81d6,
-  0x157f, 0x81d2, 0x1566, 0x81ce, 0x154d, 0x81c9, 0x1534, 0x81c5,
-  0x151b, 0x81c1, 0x1503, 0x81bd, 0x14ea, 0x81b9, 0x14d1, 0x81b5,
-  0x14b8, 0x81b1, 0x149f, 0x81ad, 0x1487, 0x81a9, 0x146e, 0x81a5,
-  0x1455, 0x81a1, 0x143c, 0x819d, 0x1423, 0x8199, 0x140b, 0x8195,
-  0x13f2, 0x8191, 0x13d9, 0x818d, 0x13c0, 0x8189, 0x13a7, 0x8185,
-  0x138e, 0x8181, 0x1376, 0x817d, 0x135d, 0x817a, 0x1344, 0x8176,
-  0x132b, 0x8172, 0x1312, 0x816e, 0x12f9, 0x816b, 0x12e0, 0x8167,
-  0x12c8, 0x8163, 0x12af, 0x815f, 0x1296, 0x815c, 0x127d, 0x8158,
-  0x1264, 0x8155, 0x124b, 0x8151, 0x1232, 0x814d, 0x1219, 0x814a,
-  0x1201, 0x8146, 0x11e8, 0x8143, 0x11cf, 0x813f, 0x11b6, 0x813c,
-  0x119d, 0x8138, 0x1184, 0x8135, 0x116b, 0x8131, 0x1152, 0x812e,
-  0x1139, 0x812b, 0x1121, 0x8127, 0x1108, 0x8124, 0x10ef, 0x8121,
-  0x10d6, 0x811d, 0x10bd, 0x811a, 0x10a4, 0x8117, 0x108b, 0x8113,
-  0x1072, 0x8110, 0x1059, 0x810d, 0x1040, 0x810a, 0x1027, 0x8107,
-  0x100e, 0x8103, 0xff5, 0x8100, 0xfdd, 0x80fd, 0xfc4, 0x80fa,
-  0xfab, 0x80f7, 0xf92, 0x80f4, 0xf79, 0x80f1, 0xf60, 0x80ee,
-  0xf47, 0x80eb, 0xf2e, 0x80e8, 0xf15, 0x80e5, 0xefc, 0x80e2,
-  0xee3, 0x80df, 0xeca, 0x80dc, 0xeb1, 0x80d9, 0xe98, 0x80d6,
-  0xe7f, 0x80d3, 0xe66, 0x80d1, 0xe4d, 0x80ce, 0xe34, 0x80cb,
-  0xe1b, 0x80c8, 0xe02, 0x80c5, 0xde9, 0x80c3, 0xdd0, 0x80c0,
-  0xdb7, 0x80bd, 0xd9e, 0x80bb, 0xd85, 0x80b8, 0xd6c, 0x80b5,
-  0xd53, 0x80b3, 0xd3a, 0x80b0, 0xd21, 0x80ad, 0xd08, 0x80ab,
-  0xcef, 0x80a8, 0xcd6, 0x80a6, 0xcbd, 0x80a3, 0xca4, 0x80a1,
-  0xc8b, 0x809e, 0xc72, 0x809c, 0xc59, 0x8099, 0xc40, 0x8097,
-  0xc27, 0x8095, 0xc0e, 0x8092, 0xbf5, 0x8090, 0xbdc, 0x808e,
-  0xbc3, 0x808b, 0xbaa, 0x8089, 0xb91, 0x8087, 0xb78, 0x8084,
-  0xb5f, 0x8082, 0xb46, 0x8080, 0xb2d, 0x807e, 0xb14, 0x807b,
-  0xafb, 0x8079, 0xae2, 0x8077, 0xac9, 0x8075, 0xab0, 0x8073,
-  0xa97, 0x8071, 0xa7e, 0x806f, 0xa65, 0x806d, 0xa4c, 0x806b,
-  0xa33, 0x8069, 0xa19, 0x8067, 0xa00, 0x8065, 0x9e7, 0x8063,
-  0x9ce, 0x8061, 0x9b5, 0x805f, 0x99c, 0x805d, 0x983, 0x805b,
-  0x96a, 0x8059, 0x951, 0x8057, 0x938, 0x8056, 0x91f, 0x8054,
-  0x906, 0x8052, 0x8ed, 0x8050, 0x8d4, 0x804f, 0x8bb, 0x804d,
-  0x8a2, 0x804b, 0x888, 0x8049, 0x86f, 0x8048, 0x856, 0x8046,
-  0x83d, 0x8044, 0x824, 0x8043, 0x80b, 0x8041, 0x7f2, 0x8040,
-  0x7d9, 0x803e, 0x7c0, 0x803d, 0x7a7, 0x803b, 0x78e, 0x803a,
-  0x775, 0x8038, 0x75b, 0x8037, 0x742, 0x8035, 0x729, 0x8034,
-  0x710, 0x8032, 0x6f7, 0x8031, 0x6de, 0x8030, 0x6c5, 0x802e,
-  0x6ac, 0x802d, 0x693, 0x802c, 0x67a, 0x802a, 0x660, 0x8029,
-  0x647, 0x8028, 0x62e, 0x8027, 0x615, 0x8026, 0x5fc, 0x8024,
-  0x5e3, 0x8023, 0x5ca, 0x8022, 0x5b1, 0x8021, 0x598, 0x8020,
-  0x57f, 0x801f, 0x565, 0x801e, 0x54c, 0x801d, 0x533, 0x801c,
-  0x51a, 0x801b, 0x501, 0x801a, 0x4e8, 0x8019, 0x4cf, 0x8018,
-  0x4b6, 0x8017, 0x49c, 0x8016, 0x483, 0x8015, 0x46a, 0x8014,
-  0x451, 0x8013, 0x438, 0x8012, 0x41f, 0x8012, 0x406, 0x8011,
-  0x3ed, 0x8010, 0x3d4, 0x800f, 0x3ba, 0x800e, 0x3a1, 0x800e,
-  0x388, 0x800d, 0x36f, 0x800c, 0x356, 0x800c, 0x33d, 0x800b,
-  0x324, 0x800a, 0x30b, 0x800a, 0x2f1, 0x8009, 0x2d8, 0x8009,
-  0x2bf, 0x8008, 0x2a6, 0x8008, 0x28d, 0x8007, 0x274, 0x8007,
-  0x25b, 0x8006, 0x242, 0x8006, 0x228, 0x8005, 0x20f, 0x8005,
-  0x1f6, 0x8004, 0x1dd, 0x8004, 0x1c4, 0x8004, 0x1ab, 0x8003,
-  0x192, 0x8003, 0x178, 0x8003, 0x15f, 0x8002, 0x146, 0x8002,
-  0x12d, 0x8002, 0x114, 0x8002, 0xfb, 0x8001, 0xe2, 0x8001,
-  0xc9, 0x8001, 0xaf, 0x8001, 0x96, 0x8001, 0x7d, 0x8001,
-  0x64, 0x8001, 0x4b, 0x8001, 0x32, 0x8001, 0x19, 0x8001,
-};
-
-static const q15_t ALIGN4 WeightsQ15_8192[16384] = {
-  0x7fff, 0x0, 0x7fff, 0xfffa, 0x7fff, 0xfff4, 0x7fff, 0xffee,
-  0x7fff, 0xffe7, 0x7fff, 0xffe1, 0x7fff, 0xffdb, 0x7fff, 0xffd5,
-  0x7fff, 0xffce, 0x7fff, 0xffc8, 0x7fff, 0xffc2, 0x7fff, 0xffbb,
-  0x7fff, 0xffb5, 0x7fff, 0xffaf, 0x7fff, 0xffa9, 0x7fff, 0xffa2,
-  0x7fff, 0xff9c, 0x7fff, 0xff96, 0x7fff, 0xff8f, 0x7fff, 0xff89,
-  0x7fff, 0xff83, 0x7fff, 0xff7d, 0x7fff, 0xff76, 0x7fff, 0xff70,
-  0x7fff, 0xff6a, 0x7fff, 0xff63, 0x7fff, 0xff5d, 0x7fff, 0xff57,
-  0x7fff, 0xff51, 0x7fff, 0xff4a, 0x7fff, 0xff44, 0x7fff, 0xff3e,
-  0x7fff, 0xff37, 0x7fff, 0xff31, 0x7fff, 0xff2b, 0x7fff, 0xff25,
-  0x7fff, 0xff1e, 0x7fff, 0xff18, 0x7fff, 0xff12, 0x7fff, 0xff0b,
-  0x7fff, 0xff05, 0x7ffe, 0xfeff, 0x7ffe, 0xfef9, 0x7ffe, 0xfef2,
-  0x7ffe, 0xfeec, 0x7ffe, 0xfee6, 0x7ffe, 0xfedf, 0x7ffe, 0xfed9,
-  0x7ffe, 0xfed3, 0x7ffe, 0xfecd, 0x7ffe, 0xfec6, 0x7ffe, 0xfec0,
-  0x7ffe, 0xfeba, 0x7ffe, 0xfeb3, 0x7ffe, 0xfead, 0x7ffe, 0xfea7,
-  0x7ffe, 0xfea1, 0x7ffe, 0xfe9a, 0x7ffd, 0xfe94, 0x7ffd, 0xfe8e,
-  0x7ffd, 0xfe88, 0x7ffd, 0xfe81, 0x7ffd, 0xfe7b, 0x7ffd, 0xfe75,
-  0x7ffd, 0xfe6e, 0x7ffd, 0xfe68, 0x7ffd, 0xfe62, 0x7ffd, 0xfe5c,
-  0x7ffd, 0xfe55, 0x7ffd, 0xfe4f, 0x7ffd, 0xfe49, 0x7ffc, 0xfe42,
-  0x7ffc, 0xfe3c, 0x7ffc, 0xfe36, 0x7ffc, 0xfe30, 0x7ffc, 0xfe29,
-  0x7ffc, 0xfe23, 0x7ffc, 0xfe1d, 0x7ffc, 0xfe16, 0x7ffc, 0xfe10,
-  0x7ffc, 0xfe0a, 0x7ffc, 0xfe04, 0x7ffb, 0xfdfd, 0x7ffb, 0xfdf7,
-  0x7ffb, 0xfdf1, 0x7ffb, 0xfdea, 0x7ffb, 0xfde4, 0x7ffb, 0xfdde,
-  0x7ffb, 0xfdd8, 0x7ffb, 0xfdd1, 0x7ffb, 0xfdcb, 0x7ffb, 0xfdc5,
-  0x7ffa, 0xfdbe, 0x7ffa, 0xfdb8, 0x7ffa, 0xfdb2, 0x7ffa, 0xfdac,
-  0x7ffa, 0xfda5, 0x7ffa, 0xfd9f, 0x7ffa, 0xfd99, 0x7ffa, 0xfd93,
-  0x7ff9, 0xfd8c, 0x7ff9, 0xfd86, 0x7ff9, 0xfd80, 0x7ff9, 0xfd79,
-  0x7ff9, 0xfd73, 0x7ff9, 0xfd6d, 0x7ff9, 0xfd67, 0x7ff9, 0xfd60,
-  0x7ff8, 0xfd5a, 0x7ff8, 0xfd54, 0x7ff8, 0xfd4d, 0x7ff8, 0xfd47,
-  0x7ff8, 0xfd41, 0x7ff8, 0xfd3b, 0x7ff8, 0xfd34, 0x7ff8, 0xfd2e,
-  0x7ff7, 0xfd28, 0x7ff7, 0xfd21, 0x7ff7, 0xfd1b, 0x7ff7, 0xfd15,
-  0x7ff7, 0xfd0f, 0x7ff7, 0xfd08, 0x7ff7, 0xfd02, 0x7ff6, 0xfcfc,
-  0x7ff6, 0xfcf5, 0x7ff6, 0xfcef, 0x7ff6, 0xfce9, 0x7ff6, 0xfce3,
-  0x7ff6, 0xfcdc, 0x7ff5, 0xfcd6, 0x7ff5, 0xfcd0, 0x7ff5, 0xfcc9,
-  0x7ff5, 0xfcc3, 0x7ff5, 0xfcbd, 0x7ff5, 0xfcb7, 0x7ff5, 0xfcb0,
-  0x7ff4, 0xfcaa, 0x7ff4, 0xfca4, 0x7ff4, 0xfc9e, 0x7ff4, 0xfc97,
-  0x7ff4, 0xfc91, 0x7ff4, 0xfc8b, 0x7ff3, 0xfc84, 0x7ff3, 0xfc7e,
-  0x7ff3, 0xfc78, 0x7ff3, 0xfc72, 0x7ff3, 0xfc6b, 0x7ff2, 0xfc65,
-  0x7ff2, 0xfc5f, 0x7ff2, 0xfc58, 0x7ff2, 0xfc52, 0x7ff2, 0xfc4c,
-  0x7ff2, 0xfc46, 0x7ff1, 0xfc3f, 0x7ff1, 0xfc39, 0x7ff1, 0xfc33,
-  0x7ff1, 0xfc2c, 0x7ff1, 0xfc26, 0x7ff0, 0xfc20, 0x7ff0, 0xfc1a,
-  0x7ff0, 0xfc13, 0x7ff0, 0xfc0d, 0x7ff0, 0xfc07, 0x7fef, 0xfc01,
-  0x7fef, 0xfbfa, 0x7fef, 0xfbf4, 0x7fef, 0xfbee, 0x7fef, 0xfbe7,
-  0x7fee, 0xfbe1, 0x7fee, 0xfbdb, 0x7fee, 0xfbd5, 0x7fee, 0xfbce,
-  0x7fee, 0xfbc8, 0x7fed, 0xfbc2, 0x7fed, 0xfbbb, 0x7fed, 0xfbb5,
-  0x7fed, 0xfbaf, 0x7fed, 0xfba9, 0x7fec, 0xfba2, 0x7fec, 0xfb9c,
-  0x7fec, 0xfb96, 0x7fec, 0xfb8f, 0x7fec, 0xfb89, 0x7feb, 0xfb83,
-  0x7feb, 0xfb7d, 0x7feb, 0xfb76, 0x7feb, 0xfb70, 0x7fea, 0xfb6a,
-  0x7fea, 0xfb64, 0x7fea, 0xfb5d, 0x7fea, 0xfb57, 0x7fea, 0xfb51,
-  0x7fe9, 0xfb4a, 0x7fe9, 0xfb44, 0x7fe9, 0xfb3e, 0x7fe9, 0xfb38,
-  0x7fe8, 0xfb31, 0x7fe8, 0xfb2b, 0x7fe8, 0xfb25, 0x7fe8, 0xfb1e,
-  0x7fe7, 0xfb18, 0x7fe7, 0xfb12, 0x7fe7, 0xfb0c, 0x7fe7, 0xfb05,
-  0x7fe6, 0xfaff, 0x7fe6, 0xfaf9, 0x7fe6, 0xfaf3, 0x7fe6, 0xfaec,
-  0x7fe5, 0xfae6, 0x7fe5, 0xfae0, 0x7fe5, 0xfad9, 0x7fe5, 0xfad3,
-  0x7fe4, 0xfacd, 0x7fe4, 0xfac7, 0x7fe4, 0xfac0, 0x7fe4, 0xfaba,
-  0x7fe3, 0xfab4, 0x7fe3, 0xfaad, 0x7fe3, 0xfaa7, 0x7fe3, 0xfaa1,
-  0x7fe2, 0xfa9b, 0x7fe2, 0xfa94, 0x7fe2, 0xfa8e, 0x7fe2, 0xfa88,
-  0x7fe1, 0xfa81, 0x7fe1, 0xfa7b, 0x7fe1, 0xfa75, 0x7fe0, 0xfa6f,
-  0x7fe0, 0xfa68, 0x7fe0, 0xfa62, 0x7fe0, 0xfa5c, 0x7fdf, 0xfa56,
-  0x7fdf, 0xfa4f, 0x7fdf, 0xfa49, 0x7fdf, 0xfa43, 0x7fde, 0xfa3c,
-  0x7fde, 0xfa36, 0x7fde, 0xfa30, 0x7fdd, 0xfa2a, 0x7fdd, 0xfa23,
-  0x7fdd, 0xfa1d, 0x7fdd, 0xfa17, 0x7fdc, 0xfa11, 0x7fdc, 0xfa0a,
-  0x7fdc, 0xfa04, 0x7fdb, 0xf9fe, 0x7fdb, 0xf9f7, 0x7fdb, 0xf9f1,
-  0x7fda, 0xf9eb, 0x7fda, 0xf9e5, 0x7fda, 0xf9de, 0x7fda, 0xf9d8,
-  0x7fd9, 0xf9d2, 0x7fd9, 0xf9cb, 0x7fd9, 0xf9c5, 0x7fd8, 0xf9bf,
-  0x7fd8, 0xf9b9, 0x7fd8, 0xf9b2, 0x7fd7, 0xf9ac, 0x7fd7, 0xf9a6,
-  0x7fd7, 0xf9a0, 0x7fd6, 0xf999, 0x7fd6, 0xf993, 0x7fd6, 0xf98d,
-  0x7fd6, 0xf986, 0x7fd5, 0xf980, 0x7fd5, 0xf97a, 0x7fd5, 0xf974,
-  0x7fd4, 0xf96d, 0x7fd4, 0xf967, 0x7fd4, 0xf961, 0x7fd3, 0xf95b,
-  0x7fd3, 0xf954, 0x7fd3, 0xf94e, 0x7fd2, 0xf948, 0x7fd2, 0xf941,
-  0x7fd2, 0xf93b, 0x7fd1, 0xf935, 0x7fd1, 0xf92f, 0x7fd1, 0xf928,
-  0x7fd0, 0xf922, 0x7fd0, 0xf91c, 0x7fd0, 0xf916, 0x7fcf, 0xf90f,
-  0x7fcf, 0xf909, 0x7fcf, 0xf903, 0x7fce, 0xf8fc, 0x7fce, 0xf8f6,
-  0x7fce, 0xf8f0, 0x7fcd, 0xf8ea, 0x7fcd, 0xf8e3, 0x7fcd, 0xf8dd,
-  0x7fcc, 0xf8d7, 0x7fcc, 0xf8d0, 0x7fcb, 0xf8ca, 0x7fcb, 0xf8c4,
-  0x7fcb, 0xf8be, 0x7fca, 0xf8b7, 0x7fca, 0xf8b1, 0x7fca, 0xf8ab,
-  0x7fc9, 0xf8a5, 0x7fc9, 0xf89e, 0x7fc9, 0xf898, 0x7fc8, 0xf892,
-  0x7fc8, 0xf88b, 0x7fc7, 0xf885, 0x7fc7, 0xf87f, 0x7fc7, 0xf879,
-  0x7fc6, 0xf872, 0x7fc6, 0xf86c, 0x7fc6, 0xf866, 0x7fc5, 0xf860,
-  0x7fc5, 0xf859, 0x7fc5, 0xf853, 0x7fc4, 0xf84d, 0x7fc4, 0xf846,
-  0x7fc3, 0xf840, 0x7fc3, 0xf83a, 0x7fc3, 0xf834, 0x7fc2, 0xf82d,
-  0x7fc2, 0xf827, 0x7fc1, 0xf821, 0x7fc1, 0xf81b, 0x7fc1, 0xf814,
-  0x7fc0, 0xf80e, 0x7fc0, 0xf808, 0x7fc0, 0xf802, 0x7fbf, 0xf7fb,
-  0x7fbf, 0xf7f5, 0x7fbe, 0xf7ef, 0x7fbe, 0xf7e8, 0x7fbe, 0xf7e2,
-  0x7fbd, 0xf7dc, 0x7fbd, 0xf7d6, 0x7fbc, 0xf7cf, 0x7fbc, 0xf7c9,
-  0x7fbc, 0xf7c3, 0x7fbb, 0xf7bd, 0x7fbb, 0xf7b6, 0x7fba, 0xf7b0,
-  0x7fba, 0xf7aa, 0x7fb9, 0xf7a3, 0x7fb9, 0xf79d, 0x7fb9, 0xf797,
-  0x7fb8, 0xf791, 0x7fb8, 0xf78a, 0x7fb7, 0xf784, 0x7fb7, 0xf77e,
-  0x7fb7, 0xf778, 0x7fb6, 0xf771, 0x7fb6, 0xf76b, 0x7fb5, 0xf765,
-  0x7fb5, 0xf75e, 0x7fb4, 0xf758, 0x7fb4, 0xf752, 0x7fb4, 0xf74c,
-  0x7fb3, 0xf745, 0x7fb3, 0xf73f, 0x7fb2, 0xf739, 0x7fb2, 0xf733,
-  0x7fb1, 0xf72c, 0x7fb1, 0xf726, 0x7fb1, 0xf720, 0x7fb0, 0xf71a,
-  0x7fb0, 0xf713, 0x7faf, 0xf70d, 0x7faf, 0xf707, 0x7fae, 0xf700,
-  0x7fae, 0xf6fa, 0x7fae, 0xf6f4, 0x7fad, 0xf6ee, 0x7fad, 0xf6e7,
-  0x7fac, 0xf6e1, 0x7fac, 0xf6db, 0x7fab, 0xf6d5, 0x7fab, 0xf6ce,
-  0x7faa, 0xf6c8, 0x7faa, 0xf6c2, 0x7fa9, 0xf6bc, 0x7fa9, 0xf6b5,
-  0x7fa9, 0xf6af, 0x7fa8, 0xf6a9, 0x7fa8, 0xf6a2, 0x7fa7, 0xf69c,
-  0x7fa7, 0xf696, 0x7fa6, 0xf690, 0x7fa6, 0xf689, 0x7fa5, 0xf683,
-  0x7fa5, 0xf67d, 0x7fa4, 0xf677, 0x7fa4, 0xf670, 0x7fa3, 0xf66a,
-  0x7fa3, 0xf664, 0x7fa3, 0xf65e, 0x7fa2, 0xf657, 0x7fa2, 0xf651,
-  0x7fa1, 0xf64b, 0x7fa1, 0xf644, 0x7fa0, 0xf63e, 0x7fa0, 0xf638,
-  0x7f9f, 0xf632, 0x7f9f, 0xf62b, 0x7f9e, 0xf625, 0x7f9e, 0xf61f,
-  0x7f9d, 0xf619, 0x7f9d, 0xf612, 0x7f9c, 0xf60c, 0x7f9c, 0xf606,
-  0x7f9b, 0xf600, 0x7f9b, 0xf5f9, 0x7f9a, 0xf5f3, 0x7f9a, 0xf5ed,
-  0x7f99, 0xf5e7, 0x7f99, 0xf5e0, 0x7f98, 0xf5da, 0x7f98, 0xf5d4,
-  0x7f97, 0xf5cd, 0x7f97, 0xf5c7, 0x7f96, 0xf5c1, 0x7f96, 0xf5bb,
-  0x7f95, 0xf5b4, 0x7f95, 0xf5ae, 0x7f94, 0xf5a8, 0x7f94, 0xf5a2,
-  0x7f93, 0xf59b, 0x7f93, 0xf595, 0x7f92, 0xf58f, 0x7f92, 0xf589,
-  0x7f91, 0xf582, 0x7f91, 0xf57c, 0x7f90, 0xf576, 0x7f90, 0xf570,
-  0x7f8f, 0xf569, 0x7f8f, 0xf563, 0x7f8e, 0xf55d, 0x7f8e, 0xf556,
-  0x7f8d, 0xf550, 0x7f8d, 0xf54a, 0x7f8c, 0xf544, 0x7f8b, 0xf53d,
-  0x7f8b, 0xf537, 0x7f8a, 0xf531, 0x7f8a, 0xf52b, 0x7f89, 0xf524,
-  0x7f89, 0xf51e, 0x7f88, 0xf518, 0x7f88, 0xf512, 0x7f87, 0xf50b,
-  0x7f87, 0xf505, 0x7f86, 0xf4ff, 0x7f86, 0xf4f9, 0x7f85, 0xf4f2,
-  0x7f85, 0xf4ec, 0x7f84, 0xf4e6, 0x7f83, 0xf4e0, 0x7f83, 0xf4d9,
-  0x7f82, 0xf4d3, 0x7f82, 0xf4cd, 0x7f81, 0xf4c6, 0x7f81, 0xf4c0,
-  0x7f80, 0xf4ba, 0x7f80, 0xf4b4, 0x7f7f, 0xf4ad, 0x7f7e, 0xf4a7,
-  0x7f7e, 0xf4a1, 0x7f7d, 0xf49b, 0x7f7d, 0xf494, 0x7f7c, 0xf48e,
-  0x7f7c, 0xf488, 0x7f7b, 0xf482, 0x7f7b, 0xf47b, 0x7f7a, 0xf475,
-  0x7f79, 0xf46f, 0x7f79, 0xf469, 0x7f78, 0xf462, 0x7f78, 0xf45c,
-  0x7f77, 0xf456, 0x7f77, 0xf450, 0x7f76, 0xf449, 0x7f75, 0xf443,
-  0x7f75, 0xf43d, 0x7f74, 0xf437, 0x7f74, 0xf430, 0x7f73, 0xf42a,
-  0x7f72, 0xf424, 0x7f72, 0xf41e, 0x7f71, 0xf417, 0x7f71, 0xf411,
-  0x7f70, 0xf40b, 0x7f70, 0xf405, 0x7f6f, 0xf3fe, 0x7f6e, 0xf3f8,
-  0x7f6e, 0xf3f2, 0x7f6d, 0xf3ec, 0x7f6d, 0xf3e5, 0x7f6c, 0xf3df,
-  0x7f6b, 0xf3d9, 0x7f6b, 0xf3d2, 0x7f6a, 0xf3cc, 0x7f6a, 0xf3c6,
-  0x7f69, 0xf3c0, 0x7f68, 0xf3b9, 0x7f68, 0xf3b3, 0x7f67, 0xf3ad,
-  0x7f67, 0xf3a7, 0x7f66, 0xf3a0, 0x7f65, 0xf39a, 0x7f65, 0xf394,
-  0x7f64, 0xf38e, 0x7f64, 0xf387, 0x7f63, 0xf381, 0x7f62, 0xf37b,
-  0x7f62, 0xf375, 0x7f61, 0xf36e, 0x7f60, 0xf368, 0x7f60, 0xf362,
-  0x7f5f, 0xf35c, 0x7f5f, 0xf355, 0x7f5e, 0xf34f, 0x7f5d, 0xf349,
-  0x7f5d, 0xf343, 0x7f5c, 0xf33c, 0x7f5b, 0xf336, 0x7f5b, 0xf330,
-  0x7f5a, 0xf32a, 0x7f5a, 0xf323, 0x7f59, 0xf31d, 0x7f58, 0xf317,
-  0x7f58, 0xf311, 0x7f57, 0xf30a, 0x7f56, 0xf304, 0x7f56, 0xf2fe,
-  0x7f55, 0xf2f8, 0x7f55, 0xf2f1, 0x7f54, 0xf2eb, 0x7f53, 0xf2e5,
-  0x7f53, 0xf2df, 0x7f52, 0xf2d8, 0x7f51, 0xf2d2, 0x7f51, 0xf2cc,
-  0x7f50, 0xf2c6, 0x7f4f, 0xf2bf, 0x7f4f, 0xf2b9, 0x7f4e, 0xf2b3,
-  0x7f4d, 0xf2ad, 0x7f4d, 0xf2a6, 0x7f4c, 0xf2a0, 0x7f4b, 0xf29a,
-  0x7f4b, 0xf294, 0x7f4a, 0xf28d, 0x7f49, 0xf287, 0x7f49, 0xf281,
-  0x7f48, 0xf27b, 0x7f47, 0xf274, 0x7f47, 0xf26e, 0x7f46, 0xf268,
-  0x7f45, 0xf262, 0x7f45, 0xf25b, 0x7f44, 0xf255, 0x7f43, 0xf24f,
-  0x7f43, 0xf249, 0x7f42, 0xf242, 0x7f41, 0xf23c, 0x7f41, 0xf236,
-  0x7f40, 0xf230, 0x7f3f, 0xf229, 0x7f3f, 0xf223, 0x7f3e, 0xf21d,
-  0x7f3d, 0xf217, 0x7f3d, 0xf210, 0x7f3c, 0xf20a, 0x7f3b, 0xf204,
-  0x7f3b, 0xf1fe, 0x7f3a, 0xf1f7, 0x7f39, 0xf1f1, 0x7f39, 0xf1eb,
-  0x7f38, 0xf1e5, 0x7f37, 0xf1de, 0x7f36, 0xf1d8, 0x7f36, 0xf1d2,
-  0x7f35, 0xf1cc, 0x7f34, 0xf1c6, 0x7f34, 0xf1bf, 0x7f33, 0xf1b9,
-  0x7f32, 0xf1b3, 0x7f32, 0xf1ad, 0x7f31, 0xf1a6, 0x7f30, 0xf1a0,
-  0x7f2f, 0xf19a, 0x7f2f, 0xf194, 0x7f2e, 0xf18d, 0x7f2d, 0xf187,
-  0x7f2d, 0xf181, 0x7f2c, 0xf17b, 0x7f2b, 0xf174, 0x7f2a, 0xf16e,
-  0x7f2a, 0xf168, 0x7f29, 0xf162, 0x7f28, 0xf15b, 0x7f28, 0xf155,
-  0x7f27, 0xf14f, 0x7f26, 0xf149, 0x7f25, 0xf142, 0x7f25, 0xf13c,
-  0x7f24, 0xf136, 0x7f23, 0xf130, 0x7f23, 0xf129, 0x7f22, 0xf123,
-  0x7f21, 0xf11d, 0x7f20, 0xf117, 0x7f20, 0xf110, 0x7f1f, 0xf10a,
-  0x7f1e, 0xf104, 0x7f1d, 0xf0fe, 0x7f1d, 0xf0f8, 0x7f1c, 0xf0f1,
-  0x7f1b, 0xf0eb, 0x7f1a, 0xf0e5, 0x7f1a, 0xf0df, 0x7f19, 0xf0d8,
-  0x7f18, 0xf0d2, 0x7f17, 0xf0cc, 0x7f17, 0xf0c6, 0x7f16, 0xf0bf,
-  0x7f15, 0xf0b9, 0x7f14, 0xf0b3, 0x7f14, 0xf0ad, 0x7f13, 0xf0a6,
-  0x7f12, 0xf0a0, 0x7f11, 0xf09a, 0x7f11, 0xf094, 0x7f10, 0xf08d,
-  0x7f0f, 0xf087, 0x7f0e, 0xf081, 0x7f0e, 0xf07b, 0x7f0d, 0xf075,
-  0x7f0c, 0xf06e, 0x7f0b, 0xf068, 0x7f0b, 0xf062, 0x7f0a, 0xf05c,
-  0x7f09, 0xf055, 0x7f08, 0xf04f, 0x7f08, 0xf049, 0x7f07, 0xf043,
-  0x7f06, 0xf03c, 0x7f05, 0xf036, 0x7f04, 0xf030, 0x7f04, 0xf02a,
-  0x7f03, 0xf023, 0x7f02, 0xf01d, 0x7f01, 0xf017, 0x7f01, 0xf011,
-  0x7f00, 0xf00b, 0x7eff, 0xf004, 0x7efe, 0xeffe, 0x7efd, 0xeff8,
-  0x7efd, 0xeff2, 0x7efc, 0xefeb, 0x7efb, 0xefe5, 0x7efa, 0xefdf,
-  0x7ef9, 0xefd9, 0x7ef9, 0xefd2, 0x7ef8, 0xefcc, 0x7ef7, 0xefc6,
-  0x7ef6, 0xefc0, 0x7ef5, 0xefb9, 0x7ef5, 0xefb3, 0x7ef4, 0xefad,
-  0x7ef3, 0xefa7, 0x7ef2, 0xefa1, 0x7ef1, 0xef9a, 0x7ef1, 0xef94,
-  0x7ef0, 0xef8e, 0x7eef, 0xef88, 0x7eee, 0xef81, 0x7eed, 0xef7b,
-  0x7eed, 0xef75, 0x7eec, 0xef6f, 0x7eeb, 0xef68, 0x7eea, 0xef62,
-  0x7ee9, 0xef5c, 0x7ee9, 0xef56, 0x7ee8, 0xef50, 0x7ee7, 0xef49,
-  0x7ee6, 0xef43, 0x7ee5, 0xef3d, 0x7ee4, 0xef37, 0x7ee4, 0xef30,
-  0x7ee3, 0xef2a, 0x7ee2, 0xef24, 0x7ee1, 0xef1e, 0x7ee0, 0xef18,
-  0x7edf, 0xef11, 0x7edf, 0xef0b, 0x7ede, 0xef05, 0x7edd, 0xeeff,
-  0x7edc, 0xeef8, 0x7edb, 0xeef2, 0x7eda, 0xeeec, 0x7eda, 0xeee6,
-  0x7ed9, 0xeedf, 0x7ed8, 0xeed9, 0x7ed7, 0xeed3, 0x7ed6, 0xeecd,
-  0x7ed5, 0xeec7, 0x7ed5, 0xeec0, 0x7ed4, 0xeeba, 0x7ed3, 0xeeb4,
-  0x7ed2, 0xeeae, 0x7ed1, 0xeea7, 0x7ed0, 0xeea1, 0x7ecf, 0xee9b,
-  0x7ecf, 0xee95, 0x7ece, 0xee8f, 0x7ecd, 0xee88, 0x7ecc, 0xee82,
-  0x7ecb, 0xee7c, 0x7eca, 0xee76, 0x7ec9, 0xee6f, 0x7ec9, 0xee69,
-  0x7ec8, 0xee63, 0x7ec7, 0xee5d, 0x7ec6, 0xee57, 0x7ec5, 0xee50,
-  0x7ec4, 0xee4a, 0x7ec3, 0xee44, 0x7ec3, 0xee3e, 0x7ec2, 0xee37,
-  0x7ec1, 0xee31, 0x7ec0, 0xee2b, 0x7ebf, 0xee25, 0x7ebe, 0xee1f,
-  0x7ebd, 0xee18, 0x7ebc, 0xee12, 0x7ebb, 0xee0c, 0x7ebb, 0xee06,
-  0x7eba, 0xedff, 0x7eb9, 0xedf9, 0x7eb8, 0xedf3, 0x7eb7, 0xeded,
-  0x7eb6, 0xede7, 0x7eb5, 0xede0, 0x7eb4, 0xedda, 0x7eb4, 0xedd4,
-  0x7eb3, 0xedce, 0x7eb2, 0xedc7, 0x7eb1, 0xedc1, 0x7eb0, 0xedbb,
-  0x7eaf, 0xedb5, 0x7eae, 0xedaf, 0x7ead, 0xeda8, 0x7eac, 0xeda2,
-  0x7eab, 0xed9c, 0x7eab, 0xed96, 0x7eaa, 0xed8f, 0x7ea9, 0xed89,
-  0x7ea8, 0xed83, 0x7ea7, 0xed7d, 0x7ea6, 0xed77, 0x7ea5, 0xed70,
-  0x7ea4, 0xed6a, 0x7ea3, 0xed64, 0x7ea2, 0xed5e, 0x7ea1, 0xed58,
-  0x7ea1, 0xed51, 0x7ea0, 0xed4b, 0x7e9f, 0xed45, 0x7e9e, 0xed3f,
-  0x7e9d, 0xed38, 0x7e9c, 0xed32, 0x7e9b, 0xed2c, 0x7e9a, 0xed26,
-  0x7e99, 0xed20, 0x7e98, 0xed19, 0x7e97, 0xed13, 0x7e96, 0xed0d,
-  0x7e95, 0xed07, 0x7e94, 0xed01, 0x7e94, 0xecfa, 0x7e93, 0xecf4,
-  0x7e92, 0xecee, 0x7e91, 0xece8, 0x7e90, 0xece1, 0x7e8f, 0xecdb,
-  0x7e8e, 0xecd5, 0x7e8d, 0xeccf, 0x7e8c, 0xecc9, 0x7e8b, 0xecc2,
-  0x7e8a, 0xecbc, 0x7e89, 0xecb6, 0x7e88, 0xecb0, 0x7e87, 0xecaa,
-  0x7e86, 0xeca3, 0x7e85, 0xec9d, 0x7e84, 0xec97, 0x7e84, 0xec91,
-  0x7e83, 0xec8a, 0x7e82, 0xec84, 0x7e81, 0xec7e, 0x7e80, 0xec78,
-  0x7e7f, 0xec72, 0x7e7e, 0xec6b, 0x7e7d, 0xec65, 0x7e7c, 0xec5f,
-  0x7e7b, 0xec59, 0x7e7a, 0xec53, 0x7e79, 0xec4c, 0x7e78, 0xec46,
-  0x7e77, 0xec40, 0x7e76, 0xec3a, 0x7e75, 0xec34, 0x7e74, 0xec2d,
-  0x7e73, 0xec27, 0x7e72, 0xec21, 0x7e71, 0xec1b, 0x7e70, 0xec15,
-  0x7e6f, 0xec0e, 0x7e6e, 0xec08, 0x7e6d, 0xec02, 0x7e6c, 0xebfc,
-  0x7e6b, 0xebf5, 0x7e6a, 0xebef, 0x7e69, 0xebe9, 0x7e68, 0xebe3,
-  0x7e67, 0xebdd, 0x7e66, 0xebd6, 0x7e65, 0xebd0, 0x7e64, 0xebca,
-  0x7e63, 0xebc4, 0x7e62, 0xebbe, 0x7e61, 0xebb7, 0x7e60, 0xebb1,
-  0x7e5f, 0xebab, 0x7e5e, 0xeba5, 0x7e5d, 0xeb9f, 0x7e5c, 0xeb98,
-  0x7e5b, 0xeb92, 0x7e5a, 0xeb8c, 0x7e59, 0xeb86, 0x7e58, 0xeb80,
-  0x7e57, 0xeb79, 0x7e56, 0xeb73, 0x7e55, 0xeb6d, 0x7e54, 0xeb67,
-  0x7e53, 0xeb61, 0x7e52, 0xeb5a, 0x7e51, 0xeb54, 0x7e50, 0xeb4e,
-  0x7e4f, 0xeb48, 0x7e4e, 0xeb42, 0x7e4d, 0xeb3b, 0x7e4c, 0xeb35,
-  0x7e4b, 0xeb2f, 0x7e4a, 0xeb29, 0x7e49, 0xeb23, 0x7e48, 0xeb1c,
-  0x7e47, 0xeb16, 0x7e46, 0xeb10, 0x7e45, 0xeb0a, 0x7e44, 0xeb04,
-  0x7e43, 0xeafd, 0x7e42, 0xeaf7, 0x7e41, 0xeaf1, 0x7e40, 0xeaeb,
-  0x7e3f, 0xeae5, 0x7e3e, 0xeade, 0x7e3d, 0xead8, 0x7e3c, 0xead2,
-  0x7e3b, 0xeacc, 0x7e3a, 0xeac6, 0x7e39, 0xeabf, 0x7e38, 0xeab9,
-  0x7e37, 0xeab3, 0x7e35, 0xeaad, 0x7e34, 0xeaa7, 0x7e33, 0xeaa0,
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-  0x7e2e, 0xea81, 0x7e2d, 0xea7b, 0x7e2c, 0xea75, 0x7e2b, 0xea6f,
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-  0x7db0, 0xe7cd, 0x7daf, 0xe7c7, 0x7dae, 0xe7c1, 0x7dad, 0xe7bb,
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-  0x7d94, 0xe739, 0x7d92, 0xe733, 0x7d91, 0xe72d, 0x7d90, 0xe727,
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-  0x7d8a, 0xe708, 0x7d89, 0xe702, 0x7d87, 0xe6fb, 0x7d86, 0xe6f5,
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-  0x7af6, 0xdc72, 0x7af4, 0xdc6c, 0x7af2, 0xdc66, 0x7af1, 0xdc60,
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-  0x7ac5, 0xdbc9, 0x7ac3, 0xdbc3, 0x7ac1, 0xdbbd, 0x7abf, 0xdbb7,
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-  0x7ab6, 0xdb99, 0x7ab5, 0xdb93, 0x7ab3, 0xdb8d, 0x7ab1, 0xdb87,
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-  0x58af, 0xa3b5, 0x58ab, 0xa3b0, 0x58a6, 0xa3ac, 0x58a2, 0xa3a8,
-  0x589d, 0xa3a3, 0x5899, 0xa39f, 0x5894, 0xa39a, 0x5890, 0xa396,
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-  0x580c, 0xa318, 0x5807, 0xa314, 0x5803, 0xa310, 0x57fe, 0xa30b,
-  0x57f9, 0xa307, 0x57f5, 0xa303, 0x57f0, 0xa2ff, 0x57ec, 0xa2fa,
-  0x57e7, 0xa2f6, 0x57e3, 0xa2f2, 0x57de, 0xa2ed, 0x57d9, 0xa2e9,
-  0x57d5, 0xa2e5, 0x57d0, 0xa2e0, 0x57cc, 0xa2dc, 0x57c7, 0xa2d8,
-  0x57c3, 0xa2d3, 0x57be, 0xa2cf, 0x57b9, 0xa2cb, 0x57b5, 0xa2c6,
-  0x57b0, 0xa2c2, 0x57ac, 0xa2be, 0x57a7, 0xa2ba, 0x57a3, 0xa2b5,
-  0x579e, 0xa2b1, 0x5799, 0xa2ad, 0x5795, 0xa2a8, 0x5790, 0xa2a4,
-  0x578c, 0xa2a0, 0x5787, 0xa29b, 0x5783, 0xa297, 0x577e, 0xa293,
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-  0x5767, 0xa27d, 0x5762, 0xa279, 0x575e, 0xa275, 0x5759, 0xa271,
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-  0x5742, 0xa25b, 0x573e, 0xa257, 0x5739, 0xa253, 0x5734, 0xa24e,
-  0x5730, 0xa24a, 0x572b, 0xa246, 0x5727, 0xa241, 0x5722, 0xa23d,
-  0x571d, 0xa239, 0x5719, 0xa235, 0x5714, 0xa230, 0x5710, 0xa22c,
-  0x570b, 0xa228, 0x5706, 0xa224, 0x5702, 0xa21f, 0x56fd, 0xa21b,
-  0x56f9, 0xa217, 0x56f4, 0xa212, 0x56ef, 0xa20e, 0x56eb, 0xa20a,
-  0x56e6, 0xa206, 0x56e2, 0xa201, 0x56dd, 0xa1fd, 0x56d8, 0xa1f9,
-  0x56d4, 0xa1f5, 0x56cf, 0xa1f0, 0x56ca, 0xa1ec, 0x56c6, 0xa1e8,
-  0x56c1, 0xa1e4, 0x56bd, 0xa1df, 0x56b8, 0xa1db, 0x56b3, 0xa1d7,
-  0x56af, 0xa1d3, 0x56aa, 0xa1ce, 0x56a5, 0xa1ca, 0x56a1, 0xa1c6,
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-  0xd3a, 0x80b0, 0xd34, 0x80af, 0xd2e, 0x80af, 0xd28, 0x80ae,
-  0xd21, 0x80ad, 0xd1b, 0x80ad, 0xd15, 0x80ac, 0xd0f, 0x80ab,
-  0xd08, 0x80ab, 0xd02, 0x80aa, 0xcfc, 0x80aa, 0xcf6, 0x80a9,
-  0xcef, 0x80a8, 0xce9, 0x80a8, 0xce3, 0x80a7, 0xcdd, 0x80a6,
-  0xcd6, 0x80a6, 0xcd0, 0x80a5, 0xcca, 0x80a5, 0xcc4, 0x80a4,
-  0xcbd, 0x80a3, 0xcb7, 0x80a3, 0xcb1, 0x80a2, 0xcab, 0x80a1,
-  0xca4, 0x80a1, 0xc9e, 0x80a0, 0xc98, 0x80a0, 0xc92, 0x809f,
-  0xc8b, 0x809e, 0xc85, 0x809e, 0xc7f, 0x809d, 0xc79, 0x809c,
-  0xc72, 0x809c, 0xc6c, 0x809b, 0xc66, 0x809b, 0xc60, 0x809a,
-  0xc59, 0x8099, 0xc53, 0x8099, 0xc4d, 0x8098, 0xc47, 0x8098,
-  0xc40, 0x8097, 0xc3a, 0x8096, 0xc34, 0x8096, 0xc2e, 0x8095,
-  0xc27, 0x8095, 0xc21, 0x8094, 0xc1b, 0x8093, 0xc14, 0x8093,
-  0xc0e, 0x8092, 0xc08, 0x8092, 0xc02, 0x8091, 0xbfb, 0x8090,
-  0xbf5, 0x8090, 0xbef, 0x808f, 0xbe9, 0x808f, 0xbe2, 0x808e,
-  0xbdc, 0x808e, 0xbd6, 0x808d, 0xbd0, 0x808c, 0xbc9, 0x808c,
-  0xbc3, 0x808b, 0xbbd, 0x808b, 0xbb7, 0x808a, 0xbb0, 0x8089,
-  0xbaa, 0x8089, 0xba4, 0x8088, 0xb9e, 0x8088, 0xb97, 0x8087,
-  0xb91, 0x8087, 0xb8b, 0x8086, 0xb85, 0x8085, 0xb7e, 0x8085,
-  0xb78, 0x8084, 0xb72, 0x8084, 0xb6c, 0x8083, 0xb65, 0x8083,
-  0xb5f, 0x8082, 0xb59, 0x8082, 0xb53, 0x8081, 0xb4c, 0x8080,
-  0xb46, 0x8080, 0xb40, 0x807f, 0xb3a, 0x807f, 0xb33, 0x807e,
-  0xb2d, 0x807e, 0xb27, 0x807d, 0xb20, 0x807d, 0xb1a, 0x807c,
-  0xb14, 0x807b, 0xb0e, 0x807b, 0xb07, 0x807a, 0xb01, 0x807a,
-  0xafb, 0x8079, 0xaf5, 0x8079, 0xaee, 0x8078, 0xae8, 0x8078,
-  0xae2, 0x8077, 0xadc, 0x8077, 0xad5, 0x8076, 0xacf, 0x8076,
-  0xac9, 0x8075, 0xac3, 0x8075, 0xabc, 0x8074, 0xab6, 0x8073,
-  0xab0, 0x8073, 0xaaa, 0x8072, 0xaa3, 0x8072, 0xa9d, 0x8071,
-  0xa97, 0x8071, 0xa90, 0x8070, 0xa8a, 0x8070, 0xa84, 0x806f,
-  0xa7e, 0x806f, 0xa77, 0x806e, 0xa71, 0x806e, 0xa6b, 0x806d,
-  0xa65, 0x806d, 0xa5e, 0x806c, 0xa58, 0x806c, 0xa52, 0x806b,
-  0xa4c, 0x806b, 0xa45, 0x806a, 0xa3f, 0x806a, 0xa39, 0x8069,
-  0xa33, 0x8069, 0xa2c, 0x8068, 0xa26, 0x8068, 0xa20, 0x8067,
-  0xa19, 0x8067, 0xa13, 0x8066, 0xa0d, 0x8066, 0xa07, 0x8065,
-  0xa00, 0x8065, 0x9fa, 0x8064, 0x9f4, 0x8064, 0x9ee, 0x8063,
-  0x9e7, 0x8063, 0x9e1, 0x8062, 0x9db, 0x8062, 0x9d5, 0x8061,
-  0x9ce, 0x8061, 0x9c8, 0x8060, 0x9c2, 0x8060, 0x9bc, 0x805f,
-  0x9b5, 0x805f, 0x9af, 0x805e, 0x9a9, 0x805e, 0x9a2, 0x805d,
-  0x99c, 0x805d, 0x996, 0x805d, 0x990, 0x805c, 0x989, 0x805c,
-  0x983, 0x805b, 0x97d, 0x805b, 0x977, 0x805a, 0x970, 0x805a,
-  0x96a, 0x8059, 0x964, 0x8059, 0x95e, 0x8058, 0x957, 0x8058,
-  0x951, 0x8057, 0x94b, 0x8057, 0x944, 0x8057, 0x93e, 0x8056,
-  0x938, 0x8056, 0x932, 0x8055, 0x92b, 0x8055, 0x925, 0x8054,
-  0x91f, 0x8054, 0x919, 0x8053, 0x912, 0x8053, 0x90c, 0x8052,
-  0x906, 0x8052, 0x900, 0x8052, 0x8f9, 0x8051, 0x8f3, 0x8051,
-  0x8ed, 0x8050, 0x8e6, 0x8050, 0x8e0, 0x804f, 0x8da, 0x804f,
-  0x8d4, 0x804f, 0x8cd, 0x804e, 0x8c7, 0x804e, 0x8c1, 0x804d,
-  0x8bb, 0x804d, 0x8b4, 0x804c, 0x8ae, 0x804c, 0x8a8, 0x804c,
-  0x8a2, 0x804b, 0x89b, 0x804b, 0x895, 0x804a, 0x88f, 0x804a,
-  0x888, 0x8049, 0x882, 0x8049, 0x87c, 0x8049, 0x876, 0x8048,
-  0x86f, 0x8048, 0x869, 0x8047, 0x863, 0x8047, 0x85d, 0x8047,
-  0x856, 0x8046, 0x850, 0x8046, 0x84a, 0x8045, 0x843, 0x8045,
-  0x83d, 0x8044, 0x837, 0x8044, 0x831, 0x8044, 0x82a, 0x8043,
-  0x824, 0x8043, 0x81e, 0x8042, 0x818, 0x8042, 0x811, 0x8042,
-  0x80b, 0x8041, 0x805, 0x8041, 0x7fe, 0x8040, 0x7f8, 0x8040,
-  0x7f2, 0x8040, 0x7ec, 0x803f, 0x7e5, 0x803f, 0x7df, 0x803f,
-  0x7d9, 0x803e, 0x7d3, 0x803e, 0x7cc, 0x803d, 0x7c6, 0x803d,
-  0x7c0, 0x803d, 0x7ba, 0x803c, 0x7b3, 0x803c, 0x7ad, 0x803b,
-  0x7a7, 0x803b, 0x7a0, 0x803b, 0x79a, 0x803a, 0x794, 0x803a,
-  0x78e, 0x803a, 0x787, 0x8039, 0x781, 0x8039, 0x77b, 0x8039,
-  0x775, 0x8038, 0x76e, 0x8038, 0x768, 0x8037, 0x762, 0x8037,
-  0x75b, 0x8037, 0x755, 0x8036, 0x74f, 0x8036, 0x749, 0x8036,
-  0x742, 0x8035, 0x73c, 0x8035, 0x736, 0x8035, 0x730, 0x8034,
-  0x729, 0x8034, 0x723, 0x8033, 0x71d, 0x8033, 0x716, 0x8033,
-  0x710, 0x8032, 0x70a, 0x8032, 0x704, 0x8032, 0x6fd, 0x8031,
-  0x6f7, 0x8031, 0x6f1, 0x8031, 0x6ea, 0x8030, 0x6e4, 0x8030,
-  0x6de, 0x8030, 0x6d8, 0x802f, 0x6d1, 0x802f, 0x6cb, 0x802f,
-  0x6c5, 0x802e, 0x6bf, 0x802e, 0x6b8, 0x802e, 0x6b2, 0x802d,
-  0x6ac, 0x802d, 0x6a5, 0x802d, 0x69f, 0x802c, 0x699, 0x802c,
-  0x693, 0x802c, 0x68c, 0x802b, 0x686, 0x802b, 0x680, 0x802b,
-  0x67a, 0x802a, 0x673, 0x802a, 0x66d, 0x802a, 0x667, 0x802a,
-  0x660, 0x8029, 0x65a, 0x8029, 0x654, 0x8029, 0x64e, 0x8028,
-  0x647, 0x8028, 0x641, 0x8028, 0x63b, 0x8027, 0x635, 0x8027,
-  0x62e, 0x8027, 0x628, 0x8026, 0x622, 0x8026, 0x61b, 0x8026,
-  0x615, 0x8026, 0x60f, 0x8025, 0x609, 0x8025, 0x602, 0x8025,
-  0x5fc, 0x8024, 0x5f6, 0x8024, 0x5ef, 0x8024, 0x5e9, 0x8023,
-  0x5e3, 0x8023, 0x5dd, 0x8023, 0x5d6, 0x8023, 0x5d0, 0x8022,
-  0x5ca, 0x8022, 0x5c4, 0x8022, 0x5bd, 0x8021, 0x5b7, 0x8021,
-  0x5b1, 0x8021, 0x5aa, 0x8021, 0x5a4, 0x8020, 0x59e, 0x8020,
-  0x598, 0x8020, 0x591, 0x8020, 0x58b, 0x801f, 0x585, 0x801f,
-  0x57f, 0x801f, 0x578, 0x801e, 0x572, 0x801e, 0x56c, 0x801e,
-  0x565, 0x801e, 0x55f, 0x801d, 0x559, 0x801d, 0x553, 0x801d,
-  0x54c, 0x801d, 0x546, 0x801c, 0x540, 0x801c, 0x539, 0x801c,
-  0x533, 0x801c, 0x52d, 0x801b, 0x527, 0x801b, 0x520, 0x801b,
-  0x51a, 0x801b, 0x514, 0x801a, 0x50d, 0x801a, 0x507, 0x801a,
-  0x501, 0x801a, 0x4fb, 0x8019, 0x4f4, 0x8019, 0x4ee, 0x8019,
-  0x4e8, 0x8019, 0x4e2, 0x8018, 0x4db, 0x8018, 0x4d5, 0x8018,
-  0x4cf, 0x8018, 0x4c8, 0x8017, 0x4c2, 0x8017, 0x4bc, 0x8017,
-  0x4b6, 0x8017, 0x4af, 0x8016, 0x4a9, 0x8016, 0x4a3, 0x8016,
-  0x49c, 0x8016, 0x496, 0x8016, 0x490, 0x8015, 0x48a, 0x8015,
-  0x483, 0x8015, 0x47d, 0x8015, 0x477, 0x8014, 0x471, 0x8014,
-  0x46a, 0x8014, 0x464, 0x8014, 0x45e, 0x8014, 0x457, 0x8013,
-  0x451, 0x8013, 0x44b, 0x8013, 0x445, 0x8013, 0x43e, 0x8013,
-  0x438, 0x8012, 0x432, 0x8012, 0x42b, 0x8012, 0x425, 0x8012,
-  0x41f, 0x8012, 0x419, 0x8011, 0x412, 0x8011, 0x40c, 0x8011,
-  0x406, 0x8011, 0x3ff, 0x8011, 0x3f9, 0x8010, 0x3f3, 0x8010,
-  0x3ed, 0x8010, 0x3e6, 0x8010, 0x3e0, 0x8010, 0x3da, 0x800f,
-  0x3d4, 0x800f, 0x3cd, 0x800f, 0x3c7, 0x800f, 0x3c1, 0x800f,
-  0x3ba, 0x800e, 0x3b4, 0x800e, 0x3ae, 0x800e, 0x3a8, 0x800e,
-  0x3a1, 0x800e, 0x39b, 0x800e, 0x395, 0x800d, 0x38e, 0x800d,
-  0x388, 0x800d, 0x382, 0x800d, 0x37c, 0x800d, 0x375, 0x800c,
-  0x36f, 0x800c, 0x369, 0x800c, 0x362, 0x800c, 0x35c, 0x800c,
-  0x356, 0x800c, 0x350, 0x800b, 0x349, 0x800b, 0x343, 0x800b,
-  0x33d, 0x800b, 0x337, 0x800b, 0x330, 0x800b, 0x32a, 0x800b,
-  0x324, 0x800a, 0x31d, 0x800a, 0x317, 0x800a, 0x311, 0x800a,
-  0x30b, 0x800a, 0x304, 0x800a, 0x2fe, 0x8009, 0x2f8, 0x8009,
-  0x2f1, 0x8009, 0x2eb, 0x8009, 0x2e5, 0x8009, 0x2df, 0x8009,
-  0x2d8, 0x8009, 0x2d2, 0x8008, 0x2cc, 0x8008, 0x2c5, 0x8008,
-  0x2bf, 0x8008, 0x2b9, 0x8008, 0x2b3, 0x8008, 0x2ac, 0x8008,
-  0x2a6, 0x8008, 0x2a0, 0x8007, 0x299, 0x8007, 0x293, 0x8007,
-  0x28d, 0x8007, 0x287, 0x8007, 0x280, 0x8007, 0x27a, 0x8007,
-  0x274, 0x8007, 0x26d, 0x8006, 0x267, 0x8006, 0x261, 0x8006,
-  0x25b, 0x8006, 0x254, 0x8006, 0x24e, 0x8006, 0x248, 0x8006,
-  0x242, 0x8006, 0x23b, 0x8005, 0x235, 0x8005, 0x22f, 0x8005,
-  0x228, 0x8005, 0x222, 0x8005, 0x21c, 0x8005, 0x216, 0x8005,
-  0x20f, 0x8005, 0x209, 0x8005, 0x203, 0x8005, 0x1fc, 0x8004,
-  0x1f6, 0x8004, 0x1f0, 0x8004, 0x1ea, 0x8004, 0x1e3, 0x8004,
-  0x1dd, 0x8004, 0x1d7, 0x8004, 0x1d0, 0x8004, 0x1ca, 0x8004,
-  0x1c4, 0x8004, 0x1be, 0x8004, 0x1b7, 0x8003, 0x1b1, 0x8003,
-  0x1ab, 0x8003, 0x1a4, 0x8003, 0x19e, 0x8003, 0x198, 0x8003,
-  0x192, 0x8003, 0x18b, 0x8003, 0x185, 0x8003, 0x17f, 0x8003,
-  0x178, 0x8003, 0x172, 0x8003, 0x16c, 0x8003, 0x166, 0x8002,
-  0x15f, 0x8002, 0x159, 0x8002, 0x153, 0x8002, 0x14d, 0x8002,
-  0x146, 0x8002, 0x140, 0x8002, 0x13a, 0x8002, 0x133, 0x8002,
-  0x12d, 0x8002, 0x127, 0x8002, 0x121, 0x8002, 0x11a, 0x8002,
-  0x114, 0x8002, 0x10e, 0x8002, 0x107, 0x8002, 0x101, 0x8002,
-  0xfb, 0x8001, 0xf5, 0x8001, 0xee, 0x8001, 0xe8, 0x8001,
-  0xe2, 0x8001, 0xdb, 0x8001, 0xd5, 0x8001, 0xcf, 0x8001,
-  0xc9, 0x8001, 0xc2, 0x8001, 0xbc, 0x8001, 0xb6, 0x8001,
-  0xaf, 0x8001, 0xa9, 0x8001, 0xa3, 0x8001, 0x9d, 0x8001,
-  0x96, 0x8001, 0x90, 0x8001, 0x8a, 0x8001, 0x83, 0x8001,
-  0x7d, 0x8001, 0x77, 0x8001, 0x71, 0x8001, 0x6a, 0x8001,
-  0x64, 0x8001, 0x5e, 0x8001, 0x57, 0x8001, 0x51, 0x8001,
-  0x4b, 0x8001, 0x45, 0x8001, 0x3e, 0x8001, 0x38, 0x8001,
-  0x32, 0x8001, 0x2b, 0x8001, 0x25, 0x8001, 0x1f, 0x8001,
-  0x19, 0x8001, 0x12, 0x8001, 0xc, 0x8001, 0x6, 0x8001,
-};
-
-
-/**    
-* \par    
-* cosFactor tables are generated using the formula : 
 cos_factors[n] = 2 * cos((2n+1)*pi/(4*N)) 
    
-* \par    
-* C command to generate the table    
-* 
    
-* for(i = 0; i< N; i++)    
-* {    
-*   cos_factors[i]= 2 * cos((2*i+1)*c/2);    
-* } 
    
-* \par    
-* where N is the number of factors to generate and c is pi/(2*N)    
-* \par    
-* Then converted to q15 format by multiplying with 2^31 and saturated if required.    
-    
-*/
-
-static const q15_t ALIGN4 cos_factorsQ15_128[128] = {
-  0x7fff, 0x7ffa, 0x7ff0, 0x7fe1, 0x7fce, 0x7fb5, 0x7f97, 0x7f75,
-  0x7f4d, 0x7f21, 0x7ef0, 0x7eba, 0x7e7f, 0x7e3f, 0x7dfa, 0x7db0,
-  0x7d62, 0x7d0f, 0x7cb7, 0x7c5a, 0x7bf8, 0x7b92, 0x7b26, 0x7ab6,
-  0x7a42, 0x79c8, 0x794a, 0x78c7, 0x7840, 0x77b4, 0x7723, 0x768e,
-  0x75f4, 0x7555, 0x74b2, 0x740b, 0x735f, 0x72af, 0x71fa, 0x7141,
-  0x7083, 0x6fc1, 0x6efb, 0x6e30, 0x6d62, 0x6c8f, 0x6bb8, 0x6adc,
-  0x69fd, 0x6919, 0x6832, 0x6746, 0x6657, 0x6563, 0x646c, 0x6371,
-  0x6271, 0x616f, 0x6068, 0x5f5e, 0x5e50, 0x5d3e, 0x5c29, 0x5b10,
-  0x59f3, 0x58d4, 0x57b0, 0x568a, 0x5560, 0x5433, 0x5302, 0x51ce,
-  0x5097, 0x4f5e, 0x4e21, 0x4ce1, 0x4b9e, 0x4a58, 0x490f, 0x47c3,
-  0x4675, 0x4524, 0x43d0, 0x427a, 0x4121, 0x3fc5, 0x3e68, 0x3d07,
-  0x3ba5, 0x3a40, 0x38d8, 0x376f, 0x3604, 0x3496, 0x3326, 0x31b5,
-  0x3041, 0x2ecc, 0x2d55, 0x2bdc, 0x2a61, 0x28e5, 0x2767, 0x25e8,
-  0x2467, 0x22e5, 0x2161, 0x1fdc, 0x1e56, 0x1ccf, 0x1b47, 0x19bd,
-  0x1833, 0x16a8, 0x151b, 0x138e, 0x1201, 0x1072, 0xee3, 0xd53,
-  0xbc3, 0xa33, 0x8a2, 0x710, 0x57f, 0x3ed, 0x25b, 0xc9
-};
-
-static const q15_t ALIGN4 cos_factorsQ15_512[512] = {
-  0x7fff, 0x7fff, 0x7fff, 0x7ffe, 0x7ffc, 0x7ffb, 0x7ff9, 0x7ff7,
-  0x7ff4, 0x7ff2, 0x7fee, 0x7feb, 0x7fe7, 0x7fe3, 0x7fdf, 0x7fda,
-  0x7fd6, 0x7fd0, 0x7fcb, 0x7fc5, 0x7fbf, 0x7fb8, 0x7fb1, 0x7faa,
-  0x7fa3, 0x7f9b, 0x7f93, 0x7f8b, 0x7f82, 0x7f79, 0x7f70, 0x7f67,
-  0x7f5d, 0x7f53, 0x7f48, 0x7f3d, 0x7f32, 0x7f27, 0x7f1b, 0x7f0f,
-  0x7f03, 0x7ef6, 0x7ee9, 0x7edc, 0x7ecf, 0x7ec1, 0x7eb3, 0x7ea4,
-  0x7e95, 0x7e86, 0x7e77, 0x7e67, 0x7e57, 0x7e47, 0x7e37, 0x7e26,
-  0x7e14, 0x7e03, 0x7df1, 0x7ddf, 0x7dcd, 0x7dba, 0x7da7, 0x7d94,
-  0x7d80, 0x7d6c, 0x7d58, 0x7d43, 0x7d2f, 0x7d19, 0x7d04, 0x7cee,
-  0x7cd8, 0x7cc2, 0x7cab, 0x7c94, 0x7c7d, 0x7c66, 0x7c4e, 0x7c36,
-  0x7c1d, 0x7c05, 0x7beb, 0x7bd2, 0x7bb9, 0x7b9f, 0x7b84, 0x7b6a,
-  0x7b4f, 0x7b34, 0x7b19, 0x7afd, 0x7ae1, 0x7ac5, 0x7aa8, 0x7a8b,
-  0x7a6e, 0x7a50, 0x7a33, 0x7a15, 0x79f6, 0x79d8, 0x79b9, 0x7999,
-  0x797a, 0x795a, 0x793a, 0x7919, 0x78f9, 0x78d8, 0x78b6, 0x7895,
-  0x7873, 0x7851, 0x782e, 0x780c, 0x77e9, 0x77c5, 0x77a2, 0x777e,
-  0x775a, 0x7735, 0x7710, 0x76eb, 0x76c6, 0x76a0, 0x767b, 0x7654,
-  0x762e, 0x7607, 0x75e0, 0x75b9, 0x7591, 0x7569, 0x7541, 0x7519,
-  0x74f0, 0x74c7, 0x749e, 0x7474, 0x744a, 0x7420, 0x73f6, 0x73cb,
-  0x73a0, 0x7375, 0x7349, 0x731d, 0x72f1, 0x72c5, 0x7298, 0x726b,
-  0x723e, 0x7211, 0x71e3, 0x71b5, 0x7186, 0x7158, 0x7129, 0x70fa,
-  0x70cb, 0x709b, 0x706b, 0x703b, 0x700a, 0x6fda, 0x6fa9, 0x6f77,
-  0x6f46, 0x6f14, 0x6ee2, 0x6eaf, 0x6e7d, 0x6e4a, 0x6e17, 0x6de3,
-  0x6db0, 0x6d7c, 0x6d48, 0x6d13, 0x6cde, 0x6ca9, 0x6c74, 0x6c3f,
-  0x6c09, 0x6bd3, 0x6b9c, 0x6b66, 0x6b2f, 0x6af8, 0x6ac1, 0x6a89,
-  0x6a51, 0x6a19, 0x69e1, 0x69a8, 0x696f, 0x6936, 0x68fd, 0x68c3,
-  0x6889, 0x684f, 0x6815, 0x67da, 0x679f, 0x6764, 0x6729, 0x66ed,
-  0x66b1, 0x6675, 0x6639, 0x65fc, 0x65bf, 0x6582, 0x6545, 0x6507,
-  0x64c9, 0x648b, 0x644d, 0x640e, 0x63cf, 0x6390, 0x6351, 0x6311,
-  0x62d2, 0x6292, 0x6251, 0x6211, 0x61d0, 0x618f, 0x614e, 0x610d,
-  0x60cb, 0x6089, 0x6047, 0x6004, 0x5fc2, 0x5f7f, 0x5f3c, 0x5ef9,
-  0x5eb5, 0x5e71, 0x5e2d, 0x5de9, 0x5da5, 0x5d60, 0x5d1b, 0x5cd6,
-  0x5c91, 0x5c4b, 0x5c06, 0x5bc0, 0x5b79, 0x5b33, 0x5aec, 0x5aa5,
-  0x5a5e, 0x5a17, 0x59d0, 0x5988, 0x5940, 0x58f8, 0x58af, 0x5867,
-  0x581e, 0x57d5, 0x578c, 0x5742, 0x56f9, 0x56af, 0x5665, 0x561a,
-  0x55d0, 0x5585, 0x553a, 0x54ef, 0x54a4, 0x5458, 0x540d, 0x53c1,
-  0x5375, 0x5328, 0x52dc, 0x528f, 0x5242, 0x51f5, 0x51a8, 0x515a,
-  0x510c, 0x50bf, 0x5070, 0x5022, 0x4fd4, 0x4f85, 0x4f36, 0x4ee7,
-  0x4e98, 0x4e48, 0x4df9, 0x4da9, 0x4d59, 0x4d09, 0x4cb8, 0x4c68,
-  0x4c17, 0x4bc6, 0x4b75, 0x4b24, 0x4ad2, 0x4a81, 0x4a2f, 0x49dd,
-  0x498a, 0x4938, 0x48e6, 0x4893, 0x4840, 0x47ed, 0x479a, 0x4746,
-  0x46f3, 0x469f, 0x464b, 0x45f7, 0x45a3, 0x454e, 0x44fa, 0x44a5,
-  0x4450, 0x43fb, 0x43a5, 0x4350, 0x42fa, 0x42a5, 0x424f, 0x41f9,
-  0x41a2, 0x414c, 0x40f6, 0x409f, 0x4048, 0x3ff1, 0x3f9a, 0x3f43,
-  0x3eeb, 0x3e93, 0x3e3c, 0x3de4, 0x3d8c, 0x3d33, 0x3cdb, 0x3c83,
-  0x3c2a, 0x3bd1, 0x3b78, 0x3b1f, 0x3ac6, 0x3a6c, 0x3a13, 0x39b9,
-  0x395f, 0x3906, 0x38ab, 0x3851, 0x37f7, 0x379c, 0x3742, 0x36e7,
-  0x368c, 0x3631, 0x35d6, 0x357b, 0x351f, 0x34c4, 0x3468, 0x340c,
-  0x33b0, 0x3354, 0x32f8, 0x329c, 0x3240, 0x31e3, 0x3186, 0x312a,
-  0x30cd, 0x3070, 0x3013, 0x2fb5, 0x2f58, 0x2efb, 0x2e9d, 0x2e3f,
-  0x2de2, 0x2d84, 0x2d26, 0x2cc8, 0x2c69, 0x2c0b, 0x2bad, 0x2b4e,
-  0x2aef, 0x2a91, 0x2a32, 0x29d3, 0x2974, 0x2915, 0x28b5, 0x2856,
-  0x27f6, 0x2797, 0x2737, 0x26d8, 0x2678, 0x2618, 0x25b8, 0x2558,
-  0x24f7, 0x2497, 0x2437, 0x23d6, 0x2376, 0x2315, 0x22b4, 0x2254,
-  0x21f3, 0x2192, 0x2131, 0x20d0, 0x206e, 0x200d, 0x1fac, 0x1f4a,
-  0x1ee9, 0x1e87, 0x1e25, 0x1dc4, 0x1d62, 0x1d00, 0x1c9e, 0x1c3c,
-  0x1bda, 0x1b78, 0x1b16, 0x1ab3, 0x1a51, 0x19ef, 0x198c, 0x192a,
-  0x18c7, 0x1864, 0x1802, 0x179f, 0x173c, 0x16d9, 0x1676, 0x1613,
-  0x15b0, 0x154d, 0x14ea, 0x1487, 0x1423, 0x13c0, 0x135d, 0x12f9,
-  0x1296, 0x1232, 0x11cf, 0x116b, 0x1108, 0x10a4, 0x1040, 0xfdd,
-  0xf79, 0xf15, 0xeb1, 0xe4d, 0xde9, 0xd85, 0xd21, 0xcbd,
-  0xc59, 0xbf5, 0xb91, 0xb2d, 0xac9, 0xa65, 0xa00, 0x99c,
-  0x938, 0x8d4, 0x86f, 0x80b, 0x7a7, 0x742, 0x6de, 0x67a,
-  0x615, 0x5b1, 0x54c, 0x4e8, 0x483, 0x41f, 0x3ba, 0x356,
-  0x2f1, 0x28d, 0x228, 0x1c4, 0x15f, 0xfb, 0x96, 0x32,
-};
-
-static const q15_t ALIGN4 cos_factorsQ15_2048[2048] = {
-  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
-  0x7fff, 0x7fff, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffd, 0x7ffd,
-  0x7ffd, 0x7ffd, 0x7ffc, 0x7ffc, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffa,
-  0x7ffa, 0x7ff9, 0x7ff9, 0x7ff8, 0x7ff8, 0x7ff7, 0x7ff7, 0x7ff6,
-  0x7ff5, 0x7ff5, 0x7ff4, 0x7ff3, 0x7ff3, 0x7ff2, 0x7ff1, 0x7ff0,
-  0x7ff0, 0x7fef, 0x7fee, 0x7fed, 0x7fec, 0x7fec, 0x7feb, 0x7fea,
-  0x7fe9, 0x7fe8, 0x7fe7, 0x7fe6, 0x7fe5, 0x7fe4, 0x7fe3, 0x7fe2,
-  0x7fe1, 0x7fe0, 0x7fdf, 0x7fdd, 0x7fdc, 0x7fdb, 0x7fda, 0x7fd9,
-  0x7fd7, 0x7fd6, 0x7fd5, 0x7fd4, 0x7fd2, 0x7fd1, 0x7fd0, 0x7fce,
-  0x7fcd, 0x7fcb, 0x7fca, 0x7fc9, 0x7fc7, 0x7fc6, 0x7fc4, 0x7fc3,
-  0x7fc1, 0x7fc0, 0x7fbe, 0x7fbc, 0x7fbb, 0x7fb9, 0x7fb7, 0x7fb6,
-  0x7fb4, 0x7fb2, 0x7fb1, 0x7faf, 0x7fad, 0x7fab, 0x7fa9, 0x7fa8,
-  0x7fa6, 0x7fa4, 0x7fa2, 0x7fa0, 0x7f9e, 0x7f9c, 0x7f9a, 0x7f98,
-  0x7f96, 0x7f94, 0x7f92, 0x7f90, 0x7f8e, 0x7f8c, 0x7f8a, 0x7f88,
-  0x7f86, 0x7f83, 0x7f81, 0x7f7f, 0x7f7d, 0x7f7b, 0x7f78, 0x7f76,
-  0x7f74, 0x7f71, 0x7f6f, 0x7f6d, 0x7f6a, 0x7f68, 0x7f65, 0x7f63,
-  0x7f60, 0x7f5e, 0x7f5b, 0x7f59, 0x7f56, 0x7f54, 0x7f51, 0x7f4f,
-  0x7f4c, 0x7f49, 0x7f47, 0x7f44, 0x7f41, 0x7f3f, 0x7f3c, 0x7f39,
-  0x7f36, 0x7f34, 0x7f31, 0x7f2e, 0x7f2b, 0x7f28, 0x7f25, 0x7f23,
-  0x7f20, 0x7f1d, 0x7f1a, 0x7f17, 0x7f14, 0x7f11, 0x7f0e, 0x7f0b,
-  0x7f08, 0x7f04, 0x7f01, 0x7efe, 0x7efb, 0x7ef8, 0x7ef5, 0x7ef1,
-  0x7eee, 0x7eeb, 0x7ee8, 0x7ee4, 0x7ee1, 0x7ede, 0x7eda, 0x7ed7,
-  0x7ed4, 0x7ed0, 0x7ecd, 0x7ec9, 0x7ec6, 0x7ec3, 0x7ebf, 0x7ebb,
-  0x7eb8, 0x7eb4, 0x7eb1, 0x7ead, 0x7eaa, 0x7ea6, 0x7ea2, 0x7e9f,
-  0x7e9b, 0x7e97, 0x7e94, 0x7e90, 0x7e8c, 0x7e88, 0x7e84, 0x7e81,
-  0x7e7d, 0x7e79, 0x7e75, 0x7e71, 0x7e6d, 0x7e69, 0x7e65, 0x7e61,
-  0x7e5d, 0x7e59, 0x7e55, 0x7e51, 0x7e4d, 0x7e49, 0x7e45, 0x7e41,
-  0x7e3d, 0x7e39, 0x7e34, 0x7e30, 0x7e2c, 0x7e28, 0x7e24, 0x7e1f,
-  0x7e1b, 0x7e17, 0x7e12, 0x7e0e, 0x7e0a, 0x7e05, 0x7e01, 0x7dfc,
-  0x7df8, 0x7df3, 0x7def, 0x7dea, 0x7de6, 0x7de1, 0x7ddd, 0x7dd8,
-  0x7dd4, 0x7dcf, 0x7dca, 0x7dc6, 0x7dc1, 0x7dbc, 0x7db8, 0x7db3,
-  0x7dae, 0x7da9, 0x7da5, 0x7da0, 0x7d9b, 0x7d96, 0x7d91, 0x7d8c,
-  0x7d87, 0x7d82, 0x7d7e, 0x7d79, 0x7d74, 0x7d6f, 0x7d6a, 0x7d65,
-  0x7d60, 0x7d5a, 0x7d55, 0x7d50, 0x7d4b, 0x7d46, 0x7d41, 0x7d3c,
-  0x7d36, 0x7d31, 0x7d2c, 0x7d27, 0x7d21, 0x7d1c, 0x7d17, 0x7d11,
-  0x7d0c, 0x7d07, 0x7d01, 0x7cfc, 0x7cf6, 0x7cf1, 0x7cec, 0x7ce6,
-  0x7ce1, 0x7cdb, 0x7cd5, 0x7cd0, 0x7cca, 0x7cc5, 0x7cbf, 0x7cb9,
-  0x7cb4, 0x7cae, 0x7ca8, 0x7ca3, 0x7c9d, 0x7c97, 0x7c91, 0x7c8c,
-  0x7c86, 0x7c80, 0x7c7a, 0x7c74, 0x7c6e, 0x7c69, 0x7c63, 0x7c5d,
-  0x7c57, 0x7c51, 0x7c4b, 0x7c45, 0x7c3f, 0x7c39, 0x7c33, 0x7c2d,
-  0x7c26, 0x7c20, 0x7c1a, 0x7c14, 0x7c0e, 0x7c08, 0x7c01, 0x7bfb,
-  0x7bf5, 0x7bef, 0x7be8, 0x7be2, 0x7bdc, 0x7bd5, 0x7bcf, 0x7bc9,
-  0x7bc2, 0x7bbc, 0x7bb5, 0x7baf, 0x7ba8, 0x7ba2, 0x7b9b, 0x7b95,
-  0x7b8e, 0x7b88, 0x7b81, 0x7b7a, 0x7b74, 0x7b6d, 0x7b67, 0x7b60,
-  0x7b59, 0x7b52, 0x7b4c, 0x7b45, 0x7b3e, 0x7b37, 0x7b31, 0x7b2a,
-  0x7b23, 0x7b1c, 0x7b15, 0x7b0e, 0x7b07, 0x7b00, 0x7af9, 0x7af2,
-  0x7aeb, 0x7ae4, 0x7add, 0x7ad6, 0x7acf, 0x7ac8, 0x7ac1, 0x7aba,
-  0x7ab3, 0x7aac, 0x7aa4, 0x7a9d, 0x7a96, 0x7a8f, 0x7a87, 0x7a80,
-  0x7a79, 0x7a72, 0x7a6a, 0x7a63, 0x7a5c, 0x7a54, 0x7a4d, 0x7a45,
-  0x7a3e, 0x7a36, 0x7a2f, 0x7a27, 0x7a20, 0x7a18, 0x7a11, 0x7a09,
-  0x7a02, 0x79fa, 0x79f2, 0x79eb, 0x79e3, 0x79db, 0x79d4, 0x79cc,
-  0x79c4, 0x79bc, 0x79b5, 0x79ad, 0x79a5, 0x799d, 0x7995, 0x798e,
-  0x7986, 0x797e, 0x7976, 0x796e, 0x7966, 0x795e, 0x7956, 0x794e,
-  0x7946, 0x793e, 0x7936, 0x792e, 0x7926, 0x791e, 0x7915, 0x790d,
-  0x7905, 0x78fd, 0x78f5, 0x78ec, 0x78e4, 0x78dc, 0x78d4, 0x78cb,
-  0x78c3, 0x78bb, 0x78b2, 0x78aa, 0x78a2, 0x7899, 0x7891, 0x7888,
-  0x7880, 0x7877, 0x786f, 0x7866, 0x785e, 0x7855, 0x784d, 0x7844,
-  0x783b, 0x7833, 0x782a, 0x7821, 0x7819, 0x7810, 0x7807, 0x77ff,
-  0x77f6, 0x77ed, 0x77e4, 0x77db, 0x77d3, 0x77ca, 0x77c1, 0x77b8,
-  0x77af, 0x77a6, 0x779d, 0x7794, 0x778b, 0x7782, 0x7779, 0x7770,
-  0x7767, 0x775e, 0x7755, 0x774c, 0x7743, 0x773a, 0x7731, 0x7727,
-  0x771e, 0x7715, 0x770c, 0x7703, 0x76f9, 0x76f0, 0x76e7, 0x76dd,
-  0x76d4, 0x76cb, 0x76c1, 0x76b8, 0x76af, 0x76a5, 0x769c, 0x7692,
-  0x7689, 0x767f, 0x7676, 0x766c, 0x7663, 0x7659, 0x7650, 0x7646,
-  0x763c, 0x7633, 0x7629, 0x761f, 0x7616, 0x760c, 0x7602, 0x75f9,
-  0x75ef, 0x75e5, 0x75db, 0x75d1, 0x75c8, 0x75be, 0x75b4, 0x75aa,
-  0x75a0, 0x7596, 0x758c, 0x7582, 0x7578, 0x756e, 0x7564, 0x755a,
-  0x7550, 0x7546, 0x753c, 0x7532, 0x7528, 0x751e, 0x7514, 0x7509,
-  0x74ff, 0x74f5, 0x74eb, 0x74e1, 0x74d6, 0x74cc, 0x74c2, 0x74b7,
-  0x74ad, 0x74a3, 0x7498, 0x748e, 0x7484, 0x7479, 0x746f, 0x7464,
-  0x745a, 0x744f, 0x7445, 0x743a, 0x7430, 0x7425, 0x741b, 0x7410,
-  0x7406, 0x73fb, 0x73f0, 0x73e6, 0x73db, 0x73d0, 0x73c6, 0x73bb,
-  0x73b0, 0x73a5, 0x739b, 0x7390, 0x7385, 0x737a, 0x736f, 0x7364,
-  0x7359, 0x734f, 0x7344, 0x7339, 0x732e, 0x7323, 0x7318, 0x730d,
-  0x7302, 0x72f7, 0x72ec, 0x72e1, 0x72d5, 0x72ca, 0x72bf, 0x72b4,
-  0x72a9, 0x729e, 0x7293, 0x7287, 0x727c, 0x7271, 0x7266, 0x725a,
-  0x724f, 0x7244, 0x7238, 0x722d, 0x7222, 0x7216, 0x720b, 0x71ff,
-  0x71f4, 0x71e9, 0x71dd, 0x71d2, 0x71c6, 0x71bb, 0x71af, 0x71a3,
-  0x7198, 0x718c, 0x7181, 0x7175, 0x7169, 0x715e, 0x7152, 0x7146,
-  0x713b, 0x712f, 0x7123, 0x7117, 0x710c, 0x7100, 0x70f4, 0x70e8,
-  0x70dc, 0x70d1, 0x70c5, 0x70b9, 0x70ad, 0x70a1, 0x7095, 0x7089,
-  0x707d, 0x7071, 0x7065, 0x7059, 0x704d, 0x7041, 0x7035, 0x7029,
-  0x701d, 0x7010, 0x7004, 0x6ff8, 0x6fec, 0x6fe0, 0x6fd3, 0x6fc7,
-  0x6fbb, 0x6faf, 0x6fa2, 0x6f96, 0x6f8a, 0x6f7d, 0x6f71, 0x6f65,
-  0x6f58, 0x6f4c, 0x6f3f, 0x6f33, 0x6f27, 0x6f1a, 0x6f0e, 0x6f01,
-  0x6ef5, 0x6ee8, 0x6edc, 0x6ecf, 0x6ec2, 0x6eb6, 0x6ea9, 0x6e9c,
-  0x6e90, 0x6e83, 0x6e76, 0x6e6a, 0x6e5d, 0x6e50, 0x6e44, 0x6e37,
-  0x6e2a, 0x6e1d, 0x6e10, 0x6e04, 0x6df7, 0x6dea, 0x6ddd, 0x6dd0,
-  0x6dc3, 0x6db6, 0x6da9, 0x6d9c, 0x6d8f, 0x6d82, 0x6d75, 0x6d68,
-  0x6d5b, 0x6d4e, 0x6d41, 0x6d34, 0x6d27, 0x6d1a, 0x6d0c, 0x6cff,
-  0x6cf2, 0x6ce5, 0x6cd8, 0x6cca, 0x6cbd, 0x6cb0, 0x6ca3, 0x6c95,
-  0x6c88, 0x6c7b, 0x6c6d, 0x6c60, 0x6c53, 0x6c45, 0x6c38, 0x6c2a,
-  0x6c1d, 0x6c0f, 0x6c02, 0x6bf5, 0x6be7, 0x6bd9, 0x6bcc, 0x6bbe,
-  0x6bb1, 0x6ba3, 0x6b96, 0x6b88, 0x6b7a, 0x6b6d, 0x6b5f, 0x6b51,
-  0x6b44, 0x6b36, 0x6b28, 0x6b1a, 0x6b0d, 0x6aff, 0x6af1, 0x6ae3,
-  0x6ad5, 0x6ac8, 0x6aba, 0x6aac, 0x6a9e, 0x6a90, 0x6a82, 0x6a74,
-  0x6a66, 0x6a58, 0x6a4a, 0x6a3c, 0x6a2e, 0x6a20, 0x6a12, 0x6a04,
-  0x69f6, 0x69e8, 0x69da, 0x69cb, 0x69bd, 0x69af, 0x69a1, 0x6993,
-  0x6985, 0x6976, 0x6968, 0x695a, 0x694b, 0x693d, 0x692f, 0x6921,
-  0x6912, 0x6904, 0x68f5, 0x68e7, 0x68d9, 0x68ca, 0x68bc, 0x68ad,
-  0x689f, 0x6890, 0x6882, 0x6873, 0x6865, 0x6856, 0x6848, 0x6839,
-  0x682b, 0x681c, 0x680d, 0x67ff, 0x67f0, 0x67e1, 0x67d3, 0x67c4,
-  0x67b5, 0x67a6, 0x6798, 0x6789, 0x677a, 0x676b, 0x675d, 0x674e,
-  0x673f, 0x6730, 0x6721, 0x6712, 0x6703, 0x66f4, 0x66e5, 0x66d6,
-  0x66c8, 0x66b9, 0x66aa, 0x669b, 0x668b, 0x667c, 0x666d, 0x665e,
-  0x664f, 0x6640, 0x6631, 0x6622, 0x6613, 0x6603, 0x65f4, 0x65e5,
-  0x65d6, 0x65c7, 0x65b7, 0x65a8, 0x6599, 0x658a, 0x657a, 0x656b,
-  0x655c, 0x654c, 0x653d, 0x652d, 0x651e, 0x650f, 0x64ff, 0x64f0,
-  0x64e0, 0x64d1, 0x64c1, 0x64b2, 0x64a2, 0x6493, 0x6483, 0x6474,
-  0x6464, 0x6454, 0x6445, 0x6435, 0x6426, 0x6416, 0x6406, 0x63f7,
-  0x63e7, 0x63d7, 0x63c7, 0x63b8, 0x63a8, 0x6398, 0x6388, 0x6378,
-  0x6369, 0x6359, 0x6349, 0x6339, 0x6329, 0x6319, 0x6309, 0x62f9,
-  0x62ea, 0x62da, 0x62ca, 0x62ba, 0x62aa, 0x629a, 0x628a, 0x627a,
-  0x6269, 0x6259, 0x6249, 0x6239, 0x6229, 0x6219, 0x6209, 0x61f9,
-  0x61e8, 0x61d8, 0x61c8, 0x61b8, 0x61a8, 0x6197, 0x6187, 0x6177,
-  0x6166, 0x6156, 0x6146, 0x6135, 0x6125, 0x6115, 0x6104, 0x60f4,
-  0x60e4, 0x60d3, 0x60c3, 0x60b2, 0x60a2, 0x6091, 0x6081, 0x6070,
-  0x6060, 0x604f, 0x603f, 0x602e, 0x601d, 0x600d, 0x5ffc, 0x5fec,
-  0x5fdb, 0x5fca, 0x5fba, 0x5fa9, 0x5f98, 0x5f87, 0x5f77, 0x5f66,
-  0x5f55, 0x5f44, 0x5f34, 0x5f23, 0x5f12, 0x5f01, 0x5ef0, 0x5edf,
-  0x5ecf, 0x5ebe, 0x5ead, 0x5e9c, 0x5e8b, 0x5e7a, 0x5e69, 0x5e58,
-  0x5e47, 0x5e36, 0x5e25, 0x5e14, 0x5e03, 0x5df2, 0x5de1, 0x5dd0,
-  0x5dbf, 0x5dad, 0x5d9c, 0x5d8b, 0x5d7a, 0x5d69, 0x5d58, 0x5d46,
-  0x5d35, 0x5d24, 0x5d13, 0x5d01, 0x5cf0, 0x5cdf, 0x5cce, 0x5cbc,
-  0x5cab, 0x5c9a, 0x5c88, 0x5c77, 0x5c66, 0x5c54, 0x5c43, 0x5c31,
-  0x5c20, 0x5c0e, 0x5bfd, 0x5beb, 0x5bda, 0x5bc8, 0x5bb7, 0x5ba5,
-  0x5b94, 0x5b82, 0x5b71, 0x5b5f, 0x5b4d, 0x5b3c, 0x5b2a, 0x5b19,
-  0x5b07, 0x5af5, 0x5ae4, 0x5ad2, 0x5ac0, 0x5aae, 0x5a9d, 0x5a8b,
-  0x5a79, 0x5a67, 0x5a56, 0x5a44, 0x5a32, 0x5a20, 0x5a0e, 0x59fc,
-  0x59ea, 0x59d9, 0x59c7, 0x59b5, 0x59a3, 0x5991, 0x597f, 0x596d,
-  0x595b, 0x5949, 0x5937, 0x5925, 0x5913, 0x5901, 0x58ef, 0x58dd,
-  0x58cb, 0x58b8, 0x58a6, 0x5894, 0x5882, 0x5870, 0x585e, 0x584b,
-  0x5839, 0x5827, 0x5815, 0x5803, 0x57f0, 0x57de, 0x57cc, 0x57b9,
-  0x57a7, 0x5795, 0x5783, 0x5770, 0x575e, 0x574b, 0x5739, 0x5727,
-  0x5714, 0x5702, 0x56ef, 0x56dd, 0x56ca, 0x56b8, 0x56a5, 0x5693,
-  0x5680, 0x566e, 0x565b, 0x5649, 0x5636, 0x5624, 0x5611, 0x55fe,
-  0x55ec, 0x55d9, 0x55c7, 0x55b4, 0x55a1, 0x558f, 0x557c, 0x5569,
-  0x5556, 0x5544, 0x5531, 0x551e, 0x550b, 0x54f9, 0x54e6, 0x54d3,
-  0x54c0, 0x54ad, 0x549a, 0x5488, 0x5475, 0x5462, 0x544f, 0x543c,
-  0x5429, 0x5416, 0x5403, 0x53f0, 0x53dd, 0x53ca, 0x53b7, 0x53a4,
-  0x5391, 0x537e, 0x536b, 0x5358, 0x5345, 0x5332, 0x531f, 0x530c,
-  0x52f8, 0x52e5, 0x52d2, 0x52bf, 0x52ac, 0x5299, 0x5285, 0x5272,
-  0x525f, 0x524c, 0x5238, 0x5225, 0x5212, 0x51ff, 0x51eb, 0x51d8,
-  0x51c5, 0x51b1, 0x519e, 0x518b, 0x5177, 0x5164, 0x5150, 0x513d,
-  0x512a, 0x5116, 0x5103, 0x50ef, 0x50dc, 0x50c8, 0x50b5, 0x50a1,
-  0x508e, 0x507a, 0x5067, 0x5053, 0x503f, 0x502c, 0x5018, 0x5005,
-  0x4ff1, 0x4fdd, 0x4fca, 0x4fb6, 0x4fa2, 0x4f8f, 0x4f7b, 0x4f67,
-  0x4f54, 0x4f40, 0x4f2c, 0x4f18, 0x4f05, 0x4ef1, 0x4edd, 0x4ec9,
-  0x4eb6, 0x4ea2, 0x4e8e, 0x4e7a, 0x4e66, 0x4e52, 0x4e3e, 0x4e2a,
-  0x4e17, 0x4e03, 0x4def, 0x4ddb, 0x4dc7, 0x4db3, 0x4d9f, 0x4d8b,
-  0x4d77, 0x4d63, 0x4d4f, 0x4d3b, 0x4d27, 0x4d13, 0x4cff, 0x4ceb,
-  0x4cd6, 0x4cc2, 0x4cae, 0x4c9a, 0x4c86, 0x4c72, 0x4c5e, 0x4c49,
-  0x4c35, 0x4c21, 0x4c0d, 0x4bf9, 0x4be4, 0x4bd0, 0x4bbc, 0x4ba8,
-  0x4b93, 0x4b7f, 0x4b6b, 0x4b56, 0x4b42, 0x4b2e, 0x4b19, 0x4b05,
-  0x4af1, 0x4adc, 0x4ac8, 0x4ab4, 0x4a9f, 0x4a8b, 0x4a76, 0x4a62,
-  0x4a4d, 0x4a39, 0x4a24, 0x4a10, 0x49fb, 0x49e7, 0x49d2, 0x49be,
-  0x49a9, 0x4995, 0x4980, 0x496c, 0x4957, 0x4942, 0x492e, 0x4919,
-  0x4905, 0x48f0, 0x48db, 0x48c7, 0x48b2, 0x489d, 0x4888, 0x4874,
-  0x485f, 0x484a, 0x4836, 0x4821, 0x480c, 0x47f7, 0x47e2, 0x47ce,
-  0x47b9, 0x47a4, 0x478f, 0x477a, 0x4765, 0x4751, 0x473c, 0x4727,
-  0x4712, 0x46fd, 0x46e8, 0x46d3, 0x46be, 0x46a9, 0x4694, 0x467f,
-  0x466a, 0x4655, 0x4640, 0x462b, 0x4616, 0x4601, 0x45ec, 0x45d7,
-  0x45c2, 0x45ad, 0x4598, 0x4583, 0x456e, 0x4559, 0x4544, 0x452e,
-  0x4519, 0x4504, 0x44ef, 0x44da, 0x44c5, 0x44af, 0x449a, 0x4485,
-  0x4470, 0x445a, 0x4445, 0x4430, 0x441b, 0x4405, 0x43f0, 0x43db,
-  0x43c5, 0x43b0, 0x439b, 0x4385, 0x4370, 0x435b, 0x4345, 0x4330,
-  0x431b, 0x4305, 0x42f0, 0x42da, 0x42c5, 0x42af, 0x429a, 0x4284,
-  0x426f, 0x425a, 0x4244, 0x422f, 0x4219, 0x4203, 0x41ee, 0x41d8,
-  0x41c3, 0x41ad, 0x4198, 0x4182, 0x416d, 0x4157, 0x4141, 0x412c,
-  0x4116, 0x4100, 0x40eb, 0x40d5, 0x40bf, 0x40aa, 0x4094, 0x407e,
-  0x4069, 0x4053, 0x403d, 0x4027, 0x4012, 0x3ffc, 0x3fe6, 0x3fd0,
-  0x3fbb, 0x3fa5, 0x3f8f, 0x3f79, 0x3f63, 0x3f4d, 0x3f38, 0x3f22,
-  0x3f0c, 0x3ef6, 0x3ee0, 0x3eca, 0x3eb4, 0x3e9e, 0x3e88, 0x3e73,
-  0x3e5d, 0x3e47, 0x3e31, 0x3e1b, 0x3e05, 0x3def, 0x3dd9, 0x3dc3,
-  0x3dad, 0x3d97, 0x3d81, 0x3d6b, 0x3d55, 0x3d3e, 0x3d28, 0x3d12,
-  0x3cfc, 0x3ce6, 0x3cd0, 0x3cba, 0x3ca4, 0x3c8e, 0x3c77, 0x3c61,
-  0x3c4b, 0x3c35, 0x3c1f, 0x3c09, 0x3bf2, 0x3bdc, 0x3bc6, 0x3bb0,
-  0x3b99, 0x3b83, 0x3b6d, 0x3b57, 0x3b40, 0x3b2a, 0x3b14, 0x3afe,
-  0x3ae7, 0x3ad1, 0x3abb, 0x3aa4, 0x3a8e, 0x3a78, 0x3a61, 0x3a4b,
-  0x3a34, 0x3a1e, 0x3a08, 0x39f1, 0x39db, 0x39c4, 0x39ae, 0x3998,
-  0x3981, 0x396b, 0x3954, 0x393e, 0x3927, 0x3911, 0x38fa, 0x38e4,
-  0x38cd, 0x38b7, 0x38a0, 0x388a, 0x3873, 0x385d, 0x3846, 0x382f,
-  0x3819, 0x3802, 0x37ec, 0x37d5, 0x37be, 0x37a8, 0x3791, 0x377a,
-  0x3764, 0x374d, 0x3736, 0x3720, 0x3709, 0x36f2, 0x36dc, 0x36c5,
-  0x36ae, 0x3698, 0x3681, 0x366a, 0x3653, 0x363d, 0x3626, 0x360f,
-  0x35f8, 0x35e1, 0x35cb, 0x35b4, 0x359d, 0x3586, 0x356f, 0x3558,
-  0x3542, 0x352b, 0x3514, 0x34fd, 0x34e6, 0x34cf, 0x34b8, 0x34a1,
-  0x348b, 0x3474, 0x345d, 0x3446, 0x342f, 0x3418, 0x3401, 0x33ea,
-  0x33d3, 0x33bc, 0x33a5, 0x338e, 0x3377, 0x3360, 0x3349, 0x3332,
-  0x331b, 0x3304, 0x32ed, 0x32d6, 0x32bf, 0x32a8, 0x3290, 0x3279,
-  0x3262, 0x324b, 0x3234, 0x321d, 0x3206, 0x31ef, 0x31d8, 0x31c0,
-  0x31a9, 0x3192, 0x317b, 0x3164, 0x314c, 0x3135, 0x311e, 0x3107,
-  0x30f0, 0x30d8, 0x30c1, 0x30aa, 0x3093, 0x307b, 0x3064, 0x304d,
-  0x3036, 0x301e, 0x3007, 0x2ff0, 0x2fd8, 0x2fc1, 0x2faa, 0x2f92,
-  0x2f7b, 0x2f64, 0x2f4c, 0x2f35, 0x2f1e, 0x2f06, 0x2eef, 0x2ed8,
-  0x2ec0, 0x2ea9, 0x2e91, 0x2e7a, 0x2e63, 0x2e4b, 0x2e34, 0x2e1c,
-  0x2e05, 0x2ded, 0x2dd6, 0x2dbe, 0x2da7, 0x2d8f, 0x2d78, 0x2d60,
-  0x2d49, 0x2d31, 0x2d1a, 0x2d02, 0x2ceb, 0x2cd3, 0x2cbc, 0x2ca4,
-  0x2c8d, 0x2c75, 0x2c5e, 0x2c46, 0x2c2e, 0x2c17, 0x2bff, 0x2be8,
-  0x2bd0, 0x2bb8, 0x2ba1, 0x2b89, 0x2b71, 0x2b5a, 0x2b42, 0x2b2b,
-  0x2b13, 0x2afb, 0x2ae4, 0x2acc, 0x2ab4, 0x2a9c, 0x2a85, 0x2a6d,
-  0x2a55, 0x2a3e, 0x2a26, 0x2a0e, 0x29f6, 0x29df, 0x29c7, 0x29af,
-  0x2997, 0x2980, 0x2968, 0x2950, 0x2938, 0x2920, 0x2909, 0x28f1,
-  0x28d9, 0x28c1, 0x28a9, 0x2892, 0x287a, 0x2862, 0x284a, 0x2832,
-  0x281a, 0x2802, 0x27eb, 0x27d3, 0x27bb, 0x27a3, 0x278b, 0x2773,
-  0x275b, 0x2743, 0x272b, 0x2713, 0x26fb, 0x26e4, 0x26cc, 0x26b4,
-  0x269c, 0x2684, 0x266c, 0x2654, 0x263c, 0x2624, 0x260c, 0x25f4,
-  0x25dc, 0x25c4, 0x25ac, 0x2594, 0x257c, 0x2564, 0x254c, 0x2534,
-  0x251c, 0x2503, 0x24eb, 0x24d3, 0x24bb, 0x24a3, 0x248b, 0x2473,
-  0x245b, 0x2443, 0x242b, 0x2413, 0x23fa, 0x23e2, 0x23ca, 0x23b2,
-  0x239a, 0x2382, 0x236a, 0x2352, 0x2339, 0x2321, 0x2309, 0x22f1,
-  0x22d9, 0x22c0, 0x22a8, 0x2290, 0x2278, 0x2260, 0x2247, 0x222f,
-  0x2217, 0x21ff, 0x21e7, 0x21ce, 0x21b6, 0x219e, 0x2186, 0x216d,
-  0x2155, 0x213d, 0x2125, 0x210c, 0x20f4, 0x20dc, 0x20c3, 0x20ab,
-  0x2093, 0x207a, 0x2062, 0x204a, 0x2032, 0x2019, 0x2001, 0x1fe9,
-  0x1fd0, 0x1fb8, 0x1f9f, 0x1f87, 0x1f6f, 0x1f56, 0x1f3e, 0x1f26,
-  0x1f0d, 0x1ef5, 0x1edd, 0x1ec4, 0x1eac, 0x1e93, 0x1e7b, 0x1e62,
-  0x1e4a, 0x1e32, 0x1e19, 0x1e01, 0x1de8, 0x1dd0, 0x1db7, 0x1d9f,
-  0x1d87, 0x1d6e, 0x1d56, 0x1d3d, 0x1d25, 0x1d0c, 0x1cf4, 0x1cdb,
-  0x1cc3, 0x1caa, 0x1c92, 0x1c79, 0x1c61, 0x1c48, 0x1c30, 0x1c17,
-  0x1bff, 0x1be6, 0x1bce, 0x1bb5, 0x1b9d, 0x1b84, 0x1b6c, 0x1b53,
-  0x1b3a, 0x1b22, 0x1b09, 0x1af1, 0x1ad8, 0x1ac0, 0x1aa7, 0x1a8e,
-  0x1a76, 0x1a5d, 0x1a45, 0x1a2c, 0x1a13, 0x19fb, 0x19e2, 0x19ca,
-  0x19b1, 0x1998, 0x1980, 0x1967, 0x194e, 0x1936, 0x191d, 0x1905,
-  0x18ec, 0x18d3, 0x18bb, 0x18a2, 0x1889, 0x1871, 0x1858, 0x183f,
-  0x1827, 0x180e, 0x17f5, 0x17dd, 0x17c4, 0x17ab, 0x1792, 0x177a,
-  0x1761, 0x1748, 0x1730, 0x1717, 0x16fe, 0x16e5, 0x16cd, 0x16b4,
-  0x169b, 0x1682, 0x166a, 0x1651, 0x1638, 0x161f, 0x1607, 0x15ee,
-  0x15d5, 0x15bc, 0x15a4, 0x158b, 0x1572, 0x1559, 0x1541, 0x1528,
-  0x150f, 0x14f6, 0x14dd, 0x14c5, 0x14ac, 0x1493, 0x147a, 0x1461,
-  0x1449, 0x1430, 0x1417, 0x13fe, 0x13e5, 0x13cc, 0x13b4, 0x139b,
-  0x1382, 0x1369, 0x1350, 0x1337, 0x131f, 0x1306, 0x12ed, 0x12d4,
-  0x12bb, 0x12a2, 0x1289, 0x1271, 0x1258, 0x123f, 0x1226, 0x120d,
-  0x11f4, 0x11db, 0x11c2, 0x11a9, 0x1191, 0x1178, 0x115f, 0x1146,
-  0x112d, 0x1114, 0x10fb, 0x10e2, 0x10c9, 0x10b0, 0x1098, 0x107f,
-  0x1066, 0x104d, 0x1034, 0x101b, 0x1002, 0xfe9, 0xfd0, 0xfb7,
-  0xf9e, 0xf85, 0xf6c, 0xf53, 0xf3a, 0xf21, 0xf08, 0xef0,
-  0xed7, 0xebe, 0xea5, 0xe8c, 0xe73, 0xe5a, 0xe41, 0xe28,
-  0xe0f, 0xdf6, 0xddd, 0xdc4, 0xdab, 0xd92, 0xd79, 0xd60,
-  0xd47, 0xd2e, 0xd15, 0xcfc, 0xce3, 0xcca, 0xcb1, 0xc98,
-  0xc7f, 0xc66, 0xc4d, 0xc34, 0xc1b, 0xc02, 0xbe9, 0xbd0,
-  0xbb7, 0xb9e, 0xb85, 0xb6c, 0xb53, 0xb3a, 0xb20, 0xb07,
-  0xaee, 0xad5, 0xabc, 0xaa3, 0xa8a, 0xa71, 0xa58, 0xa3f,
-  0xa26, 0xa0d, 0x9f4, 0x9db, 0x9c2, 0x9a9, 0x990, 0x977,
-  0x95e, 0x944, 0x92b, 0x912, 0x8f9, 0x8e0, 0x8c7, 0x8ae,
-  0x895, 0x87c, 0x863, 0x84a, 0x831, 0x818, 0x7fe, 0x7e5,
-  0x7cc, 0x7b3, 0x79a, 0x781, 0x768, 0x74f, 0x736, 0x71d,
-  0x704, 0x6ea, 0x6d1, 0x6b8, 0x69f, 0x686, 0x66d, 0x654,
-  0x63b, 0x622, 0x609, 0x5ef, 0x5d6, 0x5bd, 0x5a4, 0x58b,
-  0x572, 0x559, 0x540, 0x527, 0x50d, 0x4f4, 0x4db, 0x4c2,
-  0x4a9, 0x490, 0x477, 0x45e, 0x445, 0x42b, 0x412, 0x3f9,
-  0x3e0, 0x3c7, 0x3ae, 0x395, 0x37c, 0x362, 0x349, 0x330,
-  0x317, 0x2fe, 0x2e5, 0x2cc, 0x2b3, 0x299, 0x280, 0x267,
-  0x24e, 0x235, 0x21c, 0x203, 0x1ea, 0x1d0, 0x1b7, 0x19e,
-  0x185, 0x16c, 0x153, 0x13a, 0x121, 0x107, 0xee, 0xd5,
-  0xbc, 0xa3, 0x8a, 0x71, 0x57, 0x3e, 0x25, 0xc,
-
-};
-
-static const q15_t ALIGN4 cos_factorsQ15_8192[8192] = {
-  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
-  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
-  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
-  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
-  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
-  0x7fff, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe,
-  0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe,
-  0x7ffe, 0x7ffe, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd,
-  0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffc,
-  0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc,
-  0x7ffc, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb,
-  0x7ffb, 0x7ffb, 0x7ffb, 0x7ffa, 0x7ffa, 0x7ffa, 0x7ffa, 0x7ffa,
-  0x7ffa, 0x7ffa, 0x7ffa, 0x7ffa, 0x7ff9, 0x7ff9, 0x7ff9, 0x7ff9,
-  0x7ff9, 0x7ff9, 0x7ff9, 0x7ff9, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
-  0x7ff8, 0x7ff8, 0x7ff8, 0x7ff7, 0x7ff7, 0x7ff7, 0x7ff7, 0x7ff7,
-  0x7ff7, 0x7ff7, 0x7ff6, 0x7ff6, 0x7ff6, 0x7ff6, 0x7ff6, 0x7ff6,
-  0x7ff6, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff4,
-  0x7ff4, 0x7ff4, 0x7ff4, 0x7ff4, 0x7ff4, 0x7ff3, 0x7ff3, 0x7ff3,
-  0x7ff3, 0x7ff3, 0x7ff3, 0x7ff2, 0x7ff2, 0x7ff2, 0x7ff2, 0x7ff2,
-  0x7ff1, 0x7ff1, 0x7ff1, 0x7ff1, 0x7ff1, 0x7ff1, 0x7ff0, 0x7ff0,
-  0x7ff0, 0x7ff0, 0x7ff0, 0x7fef, 0x7fef, 0x7fef, 0x7fef, 0x7fef,
-  0x7fee, 0x7fee, 0x7fee, 0x7fee, 0x7fee, 0x7fed, 0x7fed, 0x7fed,
-  0x7fed, 0x7fed, 0x7fec, 0x7fec, 0x7fec, 0x7fec, 0x7feb, 0x7feb,
-  0x7feb, 0x7feb, 0x7feb, 0x7fea, 0x7fea, 0x7fea, 0x7fea, 0x7fe9,
-  0x7fe9, 0x7fe9, 0x7fe9, 0x7fe8, 0x7fe8, 0x7fe8, 0x7fe8, 0x7fe8,
-  0x7fe7, 0x7fe7, 0x7fe7, 0x7fe7, 0x7fe6, 0x7fe6, 0x7fe6, 0x7fe6,
-  0x7fe5, 0x7fe5, 0x7fe5, 0x7fe5, 0x7fe4, 0x7fe4, 0x7fe4, 0x7fe4,
-  0x7fe3, 0x7fe3, 0x7fe3, 0x7fe2, 0x7fe2, 0x7fe2, 0x7fe2, 0x7fe1,
-  0x7fe1, 0x7fe1, 0x7fe1, 0x7fe0, 0x7fe0, 0x7fe0, 0x7fdf, 0x7fdf,
-  0x7fdf, 0x7fdf, 0x7fde, 0x7fde, 0x7fde, 0x7fde, 0x7fdd, 0x7fdd,
-  0x7fdd, 0x7fdc, 0x7fdc, 0x7fdc, 0x7fdb, 0x7fdb, 0x7fdb, 0x7fdb,
-  0x7fda, 0x7fda, 0x7fda, 0x7fd9, 0x7fd9, 0x7fd9, 0x7fd8, 0x7fd8,
-  0x7fd8, 0x7fd8, 0x7fd7, 0x7fd7, 0x7fd7, 0x7fd6, 0x7fd6, 0x7fd6,
-  0x7fd5, 0x7fd5, 0x7fd5, 0x7fd4, 0x7fd4, 0x7fd4, 0x7fd3, 0x7fd3,
-  0x7fd3, 0x7fd2, 0x7fd2, 0x7fd2, 0x7fd1, 0x7fd1, 0x7fd1, 0x7fd0,
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-  0x2251, 0x224a, 0x2244, 0x223e, 0x2238, 0x2232, 0x222c, 0x2226,
-  0x2220, 0x221a, 0x2214, 0x220e, 0x2208, 0x2202, 0x21fc, 0x21f6,
-  0x21f0, 0x21ea, 0x21e4, 0x21dd, 0x21d7, 0x21d1, 0x21cb, 0x21c5,
-  0x21bf, 0x21b9, 0x21b3, 0x21ad, 0x21a7, 0x21a1, 0x219b, 0x2195,
-  0x218f, 0x2189, 0x2183, 0x217c, 0x2176, 0x2170, 0x216a, 0x2164,
-  0x215e, 0x2158, 0x2152, 0x214c, 0x2146, 0x2140, 0x213a, 0x2134,
-  0x212e, 0x2128, 0x2121, 0x211b, 0x2115, 0x210f, 0x2109, 0x2103,
-  0x20fd, 0x20f7, 0x20f1, 0x20eb, 0x20e5, 0x20df, 0x20d9, 0x20d3,
-  0x20cc, 0x20c6, 0x20c0, 0x20ba, 0x20b4, 0x20ae, 0x20a8, 0x20a2,
-  0x209c, 0x2096, 0x2090, 0x208a, 0x2084, 0x207e, 0x2077, 0x2071,
-  0x206b, 0x2065, 0x205f, 0x2059, 0x2053, 0x204d, 0x2047, 0x2041,
-  0x203b, 0x2035, 0x202e, 0x2028, 0x2022, 0x201c, 0x2016, 0x2010,
-  0x200a, 0x2004, 0x1ffe, 0x1ff8, 0x1ff2, 0x1fec, 0x1fe5, 0x1fdf,
-  0x1fd9, 0x1fd3, 0x1fcd, 0x1fc7, 0x1fc1, 0x1fbb, 0x1fb5, 0x1faf,
-  0x1fa9, 0x1fa3, 0x1f9c, 0x1f96, 0x1f90, 0x1f8a, 0x1f84, 0x1f7e,
-  0x1f78, 0x1f72, 0x1f6c, 0x1f66, 0x1f60, 0x1f59, 0x1f53, 0x1f4d,
-  0x1f47, 0x1f41, 0x1f3b, 0x1f35, 0x1f2f, 0x1f29, 0x1f23, 0x1f1d,
-  0x1f16, 0x1f10, 0x1f0a, 0x1f04, 0x1efe, 0x1ef8, 0x1ef2, 0x1eec,
-  0x1ee6, 0x1ee0, 0x1ed9, 0x1ed3, 0x1ecd, 0x1ec7, 0x1ec1, 0x1ebb,
-  0x1eb5, 0x1eaf, 0x1ea9, 0x1ea3, 0x1e9c, 0x1e96, 0x1e90, 0x1e8a,
-  0x1e84, 0x1e7e, 0x1e78, 0x1e72, 0x1e6c, 0x1e66, 0x1e5f, 0x1e59,
-  0x1e53, 0x1e4d, 0x1e47, 0x1e41, 0x1e3b, 0x1e35, 0x1e2f, 0x1e29,
-  0x1e22, 0x1e1c, 0x1e16, 0x1e10, 0x1e0a, 0x1e04, 0x1dfe, 0x1df8,
-  0x1df2, 0x1deb, 0x1de5, 0x1ddf, 0x1dd9, 0x1dd3, 0x1dcd, 0x1dc7,
-  0x1dc1, 0x1dbb, 0x1db4, 0x1dae, 0x1da8, 0x1da2, 0x1d9c, 0x1d96,
-  0x1d90, 0x1d8a, 0x1d84, 0x1d7d, 0x1d77, 0x1d71, 0x1d6b, 0x1d65,
-  0x1d5f, 0x1d59, 0x1d53, 0x1d4c, 0x1d46, 0x1d40, 0x1d3a, 0x1d34,
-  0x1d2e, 0x1d28, 0x1d22, 0x1d1c, 0x1d15, 0x1d0f, 0x1d09, 0x1d03,
-  0x1cfd, 0x1cf7, 0x1cf1, 0x1ceb, 0x1ce4, 0x1cde, 0x1cd8, 0x1cd2,
-  0x1ccc, 0x1cc6, 0x1cc0, 0x1cba, 0x1cb3, 0x1cad, 0x1ca7, 0x1ca1,
-  0x1c9b, 0x1c95, 0x1c8f, 0x1c89, 0x1c83, 0x1c7c, 0x1c76, 0x1c70,
-  0x1c6a, 0x1c64, 0x1c5e, 0x1c58, 0x1c51, 0x1c4b, 0x1c45, 0x1c3f,
-  0x1c39, 0x1c33, 0x1c2d, 0x1c27, 0x1c20, 0x1c1a, 0x1c14, 0x1c0e,
-  0x1c08, 0x1c02, 0x1bfc, 0x1bf6, 0x1bef, 0x1be9, 0x1be3, 0x1bdd,
-  0x1bd7, 0x1bd1, 0x1bcb, 0x1bc4, 0x1bbe, 0x1bb8, 0x1bb2, 0x1bac,
-  0x1ba6, 0x1ba0, 0x1b9a, 0x1b93, 0x1b8d, 0x1b87, 0x1b81, 0x1b7b,
-  0x1b75, 0x1b6f, 0x1b68, 0x1b62, 0x1b5c, 0x1b56, 0x1b50, 0x1b4a,
-  0x1b44, 0x1b3d, 0x1b37, 0x1b31, 0x1b2b, 0x1b25, 0x1b1f, 0x1b19,
-  0x1b13, 0x1b0c, 0x1b06, 0x1b00, 0x1afa, 0x1af4, 0x1aee, 0x1ae8,
-  0x1ae1, 0x1adb, 0x1ad5, 0x1acf, 0x1ac9, 0x1ac3, 0x1abd, 0x1ab6,
-  0x1ab0, 0x1aaa, 0x1aa4, 0x1a9e, 0x1a98, 0x1a91, 0x1a8b, 0x1a85,
-  0x1a7f, 0x1a79, 0x1a73, 0x1a6d, 0x1a66, 0x1a60, 0x1a5a, 0x1a54,
-  0x1a4e, 0x1a48, 0x1a42, 0x1a3b, 0x1a35, 0x1a2f, 0x1a29, 0x1a23,
-  0x1a1d, 0x1a17, 0x1a10, 0x1a0a, 0x1a04, 0x19fe, 0x19f8, 0x19f2,
-  0x19eb, 0x19e5, 0x19df, 0x19d9, 0x19d3, 0x19cd, 0x19c7, 0x19c0,
-  0x19ba, 0x19b4, 0x19ae, 0x19a8, 0x19a2, 0x199b, 0x1995, 0x198f,
-  0x1989, 0x1983, 0x197d, 0x1977, 0x1970, 0x196a, 0x1964, 0x195e,
-  0x1958, 0x1952, 0x194b, 0x1945, 0x193f, 0x1939, 0x1933, 0x192d,
-  0x1926, 0x1920, 0x191a, 0x1914, 0x190e, 0x1908, 0x1901, 0x18fb,
-  0x18f5, 0x18ef, 0x18e9, 0x18e3, 0x18dc, 0x18d6, 0x18d0, 0x18ca,
-  0x18c4, 0x18be, 0x18b8, 0x18b1, 0x18ab, 0x18a5, 0x189f, 0x1899,
-  0x1893, 0x188c, 0x1886, 0x1880, 0x187a, 0x1874, 0x186e, 0x1867,
-  0x1861, 0x185b, 0x1855, 0x184f, 0x1848, 0x1842, 0x183c, 0x1836,
-  0x1830, 0x182a, 0x1823, 0x181d, 0x1817, 0x1811, 0x180b, 0x1805,
-  0x17fe, 0x17f8, 0x17f2, 0x17ec, 0x17e6, 0x17e0, 0x17d9, 0x17d3,
-  0x17cd, 0x17c7, 0x17c1, 0x17bb, 0x17b4, 0x17ae, 0x17a8, 0x17a2,
-  0x179c, 0x1795, 0x178f, 0x1789, 0x1783, 0x177d, 0x1777, 0x1770,
-  0x176a, 0x1764, 0x175e, 0x1758, 0x1752, 0x174b, 0x1745, 0x173f,
-  0x1739, 0x1733, 0x172c, 0x1726, 0x1720, 0x171a, 0x1714, 0x170e,
-  0x1707, 0x1701, 0x16fb, 0x16f5, 0x16ef, 0x16e8, 0x16e2, 0x16dc,
-  0x16d6, 0x16d0, 0x16ca, 0x16c3, 0x16bd, 0x16b7, 0x16b1, 0x16ab,
-  0x16a4, 0x169e, 0x1698, 0x1692, 0x168c, 0x1686, 0x167f, 0x1679,
-  0x1673, 0x166d, 0x1667, 0x1660, 0x165a, 0x1654, 0x164e, 0x1648,
-  0x1642, 0x163b, 0x1635, 0x162f, 0x1629, 0x1623, 0x161c, 0x1616,
-  0x1610, 0x160a, 0x1604, 0x15fd, 0x15f7, 0x15f1, 0x15eb, 0x15e5,
-  0x15de, 0x15d8, 0x15d2, 0x15cc, 0x15c6, 0x15c0, 0x15b9, 0x15b3,
-  0x15ad, 0x15a7, 0x15a1, 0x159a, 0x1594, 0x158e, 0x1588, 0x1582,
-  0x157b, 0x1575, 0x156f, 0x1569, 0x1563, 0x155c, 0x1556, 0x1550,
-  0x154a, 0x1544, 0x153d, 0x1537, 0x1531, 0x152b, 0x1525, 0x151e,
-  0x1518, 0x1512, 0x150c, 0x1506, 0x14ff, 0x14f9, 0x14f3, 0x14ed,
-  0x14e7, 0x14e0, 0x14da, 0x14d4, 0x14ce, 0x14c8, 0x14c1, 0x14bb,
-  0x14b5, 0x14af, 0x14a9, 0x14a2, 0x149c, 0x1496, 0x1490, 0x148a,
-  0x1483, 0x147d, 0x1477, 0x1471, 0x146b, 0x1464, 0x145e, 0x1458,
-  0x1452, 0x144c, 0x1445, 0x143f, 0x1439, 0x1433, 0x142d, 0x1426,
-  0x1420, 0x141a, 0x1414, 0x140e, 0x1407, 0x1401, 0x13fb, 0x13f5,
-  0x13ef, 0x13e8, 0x13e2, 0x13dc, 0x13d6, 0x13d0, 0x13c9, 0x13c3,
-  0x13bd, 0x13b7, 0x13b1, 0x13aa, 0x13a4, 0x139e, 0x1398, 0x1391,
-  0x138b, 0x1385, 0x137f, 0x1379, 0x1372, 0x136c, 0x1366, 0x1360,
-  0x135a, 0x1353, 0x134d, 0x1347, 0x1341, 0x133b, 0x1334, 0x132e,
-  0x1328, 0x1322, 0x131b, 0x1315, 0x130f, 0x1309, 0x1303, 0x12fc,
-  0x12f6, 0x12f0, 0x12ea, 0x12e4, 0x12dd, 0x12d7, 0x12d1, 0x12cb,
-  0x12c4, 0x12be, 0x12b8, 0x12b2, 0x12ac, 0x12a5, 0x129f, 0x1299,
-  0x1293, 0x128d, 0x1286, 0x1280, 0x127a, 0x1274, 0x126d, 0x1267,
-  0x1261, 0x125b, 0x1255, 0x124e, 0x1248, 0x1242, 0x123c, 0x1235,
-  0x122f, 0x1229, 0x1223, 0x121d, 0x1216, 0x1210, 0x120a, 0x1204,
-  0x11fd, 0x11f7, 0x11f1, 0x11eb, 0x11e5, 0x11de, 0x11d8, 0x11d2,
-  0x11cc, 0x11c5, 0x11bf, 0x11b9, 0x11b3, 0x11ad, 0x11a6, 0x11a0,
-  0x119a, 0x1194, 0x118d, 0x1187, 0x1181, 0x117b, 0x1175, 0x116e,
-  0x1168, 0x1162, 0x115c, 0x1155, 0x114f, 0x1149, 0x1143, 0x113d,
-  0x1136, 0x1130, 0x112a, 0x1124, 0x111d, 0x1117, 0x1111, 0x110b,
-  0x1105, 0x10fe, 0x10f8, 0x10f2, 0x10ec, 0x10e5, 0x10df, 0x10d9,
-  0x10d3, 0x10cc, 0x10c6, 0x10c0, 0x10ba, 0x10b4, 0x10ad, 0x10a7,
-  0x10a1, 0x109b, 0x1094, 0x108e, 0x1088, 0x1082, 0x107b, 0x1075,
-  0x106f, 0x1069, 0x1063, 0x105c, 0x1056, 0x1050, 0x104a, 0x1043,
-  0x103d, 0x1037, 0x1031, 0x102a, 0x1024, 0x101e, 0x1018, 0x1012,
-  0x100b, 0x1005, 0xfff, 0xff9, 0xff2, 0xfec, 0xfe6, 0xfe0,
-  0xfd9, 0xfd3, 0xfcd, 0xfc7, 0xfc0, 0xfba, 0xfb4, 0xfae,
-  0xfa8, 0xfa1, 0xf9b, 0xf95, 0xf8f, 0xf88, 0xf82, 0xf7c,
-  0xf76, 0xf6f, 0xf69, 0xf63, 0xf5d, 0xf56, 0xf50, 0xf4a,
-  0xf44, 0xf3e, 0xf37, 0xf31, 0xf2b, 0xf25, 0xf1e, 0xf18,
-  0xf12, 0xf0c, 0xf05, 0xeff, 0xef9, 0xef3, 0xeec, 0xee6,
-  0xee0, 0xeda, 0xed3, 0xecd, 0xec7, 0xec1, 0xeba, 0xeb4,
-  0xeae, 0xea8, 0xea1, 0xe9b, 0xe95, 0xe8f, 0xe89, 0xe82,
-  0xe7c, 0xe76, 0xe70, 0xe69, 0xe63, 0xe5d, 0xe57, 0xe50,
-  0xe4a, 0xe44, 0xe3e, 0xe37, 0xe31, 0xe2b, 0xe25, 0xe1e,
-  0xe18, 0xe12, 0xe0c, 0xe05, 0xdff, 0xdf9, 0xdf3, 0xdec,
-  0xde6, 0xde0, 0xdda, 0xdd3, 0xdcd, 0xdc7, 0xdc1, 0xdba,
-  0xdb4, 0xdae, 0xda8, 0xda1, 0xd9b, 0xd95, 0xd8f, 0xd88,
-  0xd82, 0xd7c, 0xd76, 0xd6f, 0xd69, 0xd63, 0xd5d, 0xd56,
-  0xd50, 0xd4a, 0xd44, 0xd3d, 0xd37, 0xd31, 0xd2b, 0xd24,
-  0xd1e, 0xd18, 0xd12, 0xd0b, 0xd05, 0xcff, 0xcf9, 0xcf2,
-  0xcec, 0xce6, 0xce0, 0xcd9, 0xcd3, 0xccd, 0xcc7, 0xcc0,
-  0xcba, 0xcb4, 0xcae, 0xca7, 0xca1, 0xc9b, 0xc95, 0xc8e,
-  0xc88, 0xc82, 0xc7c, 0xc75, 0xc6f, 0xc69, 0xc63, 0xc5c,
-  0xc56, 0xc50, 0xc4a, 0xc43, 0xc3d, 0xc37, 0xc31, 0xc2a,
-  0xc24, 0xc1e, 0xc18, 0xc11, 0xc0b, 0xc05, 0xbff, 0xbf8,
-  0xbf2, 0xbec, 0xbe6, 0xbdf, 0xbd9, 0xbd3, 0xbcd, 0xbc6,
-  0xbc0, 0xbba, 0xbb4, 0xbad, 0xba7, 0xba1, 0xb9b, 0xb94,
-  0xb8e, 0xb88, 0xb81, 0xb7b, 0xb75, 0xb6f, 0xb68, 0xb62,
-  0xb5c, 0xb56, 0xb4f, 0xb49, 0xb43, 0xb3d, 0xb36, 0xb30,
-  0xb2a, 0xb24, 0xb1d, 0xb17, 0xb11, 0xb0b, 0xb04, 0xafe,
-  0xaf8, 0xaf2, 0xaeb, 0xae5, 0xadf, 0xad8, 0xad2, 0xacc,
-  0xac6, 0xabf, 0xab9, 0xab3, 0xaad, 0xaa6, 0xaa0, 0xa9a,
-  0xa94, 0xa8d, 0xa87, 0xa81, 0xa7b, 0xa74, 0xa6e, 0xa68,
-  0xa62, 0xa5b, 0xa55, 0xa4f, 0xa48, 0xa42, 0xa3c, 0xa36,
-  0xa2f, 0xa29, 0xa23, 0xa1d, 0xa16, 0xa10, 0xa0a, 0xa04,
-  0x9fd, 0x9f7, 0x9f1, 0x9eb, 0x9e4, 0x9de, 0x9d8, 0x9d1,
-  0x9cb, 0x9c5, 0x9bf, 0x9b8, 0x9b2, 0x9ac, 0x9a6, 0x99f,
-  0x999, 0x993, 0x98d, 0x986, 0x980, 0x97a, 0x973, 0x96d,
-  0x967, 0x961, 0x95a, 0x954, 0x94e, 0x948, 0x941, 0x93b,
-  0x935, 0x92f, 0x928, 0x922, 0x91c, 0x915, 0x90f, 0x909,
-  0x903, 0x8fc, 0x8f6, 0x8f0, 0x8ea, 0x8e3, 0x8dd, 0x8d7,
-  0x8d1, 0x8ca, 0x8c4, 0x8be, 0x8b7, 0x8b1, 0x8ab, 0x8a5,
-  0x89e, 0x898, 0x892, 0x88c, 0x885, 0x87f, 0x879, 0x872,
-  0x86c, 0x866, 0x860, 0x859, 0x853, 0x84d, 0x847, 0x840,
-  0x83a, 0x834, 0x82e, 0x827, 0x821, 0x81b, 0x814, 0x80e,
-  0x808, 0x802, 0x7fb, 0x7f5, 0x7ef, 0x7e9, 0x7e2, 0x7dc,
-  0x7d6, 0x7cf, 0x7c9, 0x7c3, 0x7bd, 0x7b6, 0x7b0, 0x7aa,
-  0x7a4, 0x79d, 0x797, 0x791, 0x78a, 0x784, 0x77e, 0x778,
-  0x771, 0x76b, 0x765, 0x75f, 0x758, 0x752, 0x74c, 0x745,
-  0x73f, 0x739, 0x733, 0x72c, 0x726, 0x720, 0x71a, 0x713,
-  0x70d, 0x707, 0x700, 0x6fa, 0x6f4, 0x6ee, 0x6e7, 0x6e1,
-  0x6db, 0x6d5, 0x6ce, 0x6c8, 0x6c2, 0x6bb, 0x6b5, 0x6af,
-  0x6a9, 0x6a2, 0x69c, 0x696, 0x690, 0x689, 0x683, 0x67d,
-  0x676, 0x670, 0x66a, 0x664, 0x65d, 0x657, 0x651, 0x64a,
-  0x644, 0x63e, 0x638, 0x631, 0x62b, 0x625, 0x61f, 0x618,
-  0x612, 0x60c, 0x605, 0x5ff, 0x5f9, 0x5f3, 0x5ec, 0x5e6,
-  0x5e0, 0x5da, 0x5d3, 0x5cd, 0x5c7, 0x5c0, 0x5ba, 0x5b4,
-  0x5ae, 0x5a7, 0x5a1, 0x59b, 0x594, 0x58e, 0x588, 0x582,
-  0x57b, 0x575, 0x56f, 0x569, 0x562, 0x55c, 0x556, 0x54f,
-  0x549, 0x543, 0x53d, 0x536, 0x530, 0x52a, 0x523, 0x51d,
-  0x517, 0x511, 0x50a, 0x504, 0x4fe, 0x4f8, 0x4f1, 0x4eb,
-  0x4e5, 0x4de, 0x4d8, 0x4d2, 0x4cc, 0x4c5, 0x4bf, 0x4b9,
-  0x4b2, 0x4ac, 0x4a6, 0x4a0, 0x499, 0x493, 0x48d, 0x487,
-  0x480, 0x47a, 0x474, 0x46d, 0x467, 0x461, 0x45b, 0x454,
-  0x44e, 0x448, 0x441, 0x43b, 0x435, 0x42f, 0x428, 0x422,
-  0x41c, 0x415, 0x40f, 0x409, 0x403, 0x3fc, 0x3f6, 0x3f0,
-  0x3ea, 0x3e3, 0x3dd, 0x3d7, 0x3d0, 0x3ca, 0x3c4, 0x3be,
-  0x3b7, 0x3b1, 0x3ab, 0x3a4, 0x39e, 0x398, 0x392, 0x38b,
-  0x385, 0x37f, 0x378, 0x372, 0x36c, 0x366, 0x35f, 0x359,
-  0x353, 0x34c, 0x346, 0x340, 0x33a, 0x333, 0x32d, 0x327,
-  0x321, 0x31a, 0x314, 0x30e, 0x307, 0x301, 0x2fb, 0x2f5,
-  0x2ee, 0x2e8, 0x2e2, 0x2db, 0x2d5, 0x2cf, 0x2c9, 0x2c2,
-  0x2bc, 0x2b6, 0x2af, 0x2a9, 0x2a3, 0x29d, 0x296, 0x290,
-  0x28a, 0x283, 0x27d, 0x277, 0x271, 0x26a, 0x264, 0x25e,
-  0x258, 0x251, 0x24b, 0x245, 0x23e, 0x238, 0x232, 0x22c,
-  0x225, 0x21f, 0x219, 0x212, 0x20c, 0x206, 0x200, 0x1f9,
-  0x1f3, 0x1ed, 0x1e6, 0x1e0, 0x1da, 0x1d4, 0x1cd, 0x1c7,
-  0x1c1, 0x1ba, 0x1b4, 0x1ae, 0x1a8, 0x1a1, 0x19b, 0x195,
-  0x18e, 0x188, 0x182, 0x17c, 0x175, 0x16f, 0x169, 0x162,
-  0x15c, 0x156, 0x150, 0x149, 0x143, 0x13d, 0x137, 0x130,
-  0x12a, 0x124, 0x11d, 0x117, 0x111, 0x10b, 0x104, 0xfe,
-  0xf8, 0xf1, 0xeb, 0xe5, 0xdf, 0xd8, 0xd2, 0xcc,
-  0xc5, 0xbf, 0xb9, 0xb3, 0xac, 0xa6, 0xa0, 0x99,
-  0x93, 0x8d, 0x87, 0x80, 0x7a, 0x74, 0x6d, 0x67,
-  0x61, 0x5b, 0x54, 0x4e, 0x48, 0x41, 0x3b, 0x35,
-  0x2f, 0x28, 0x22, 0x1c, 0x15, 0xf, 0x9, 0x3,
-};
-
-/**    
- * @brief  Initialization function for the Q15 DCT4/IDCT4.   
- * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.   
- * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.   
- * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.   
- * @param[in]     N          length of the DCT4.   
- * @param[in]     Nby2       half of the length of the DCT4.   
- * @param[in]     normalize  normalizing factor.   
- * @return  	  arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.   
- * \par Normalizing factor:    
- * The normalizing factor is sqrt(2/N), which depends on the size of transform N.    
- * Normalizing factors in 1.15 format are mentioned in the table below for different DCT sizes:    
- * \image html dct4NormalizingQ15Table.gif    
- */
-
-arm_status arm_dct4_init_q15(
-  arm_dct4_instance_q15 * S,
-  arm_rfft_instance_q15 * S_RFFT,
-  arm_cfft_radix4_instance_q15 * S_CFFT,
-  uint16_t N,
-  uint16_t Nby2,
-  q15_t normalize)
-{
-  /*  Initialise the default arm status */
-  arm_status status = ARM_MATH_SUCCESS;
-
-  /* Initializing the pointer array with the weight table base addresses of different lengths */
-  q15_t *twiddlePtr[4] = { (q15_t *) WeightsQ15_128, (q15_t *) WeightsQ15_512,
-    (q15_t *) WeightsQ15_2048, (q15_t *) WeightsQ15_8192
-  };
-
-  /* Initializing the pointer array with the cos factor table base addresses of different lengths */
-  q15_t *pCosFactor[4] =
-    { (q15_t *) cos_factorsQ15_128, (q15_t *) cos_factorsQ15_512,
-    (q15_t *) cos_factorsQ15_2048, (q15_t *) cos_factorsQ15_8192
-  };
-
-  /* Initialize the DCT4 length */
-  S->N = N;
-
-  /* Initialize the half of DCT4 length */
-  S->Nby2 = Nby2;
-
-  /* Initialize the DCT4 Normalizing factor */
-  S->normalize = normalize;
-
-  /* Initialize Real FFT Instance */
-  S->pRfft = S_RFFT;
-
-  /* Initialize Complex FFT Instance */
-  S->pCfft = S_CFFT;
-
-  switch (N)
-  {
-    /* Initialize the table modifier values */
-  case 8192u:
-    S->pTwiddle = twiddlePtr[3];
-    S->pCosFactor = pCosFactor[3];
-    break;
-  case 2048u:
-    S->pTwiddle = twiddlePtr[2];
-    S->pCosFactor = pCosFactor[2];
-    break;
-  case 512u:
-    S->pTwiddle = twiddlePtr[1];
-    S->pCosFactor = pCosFactor[1];
-    break;
-  case 128u:
-    S->pTwiddle = twiddlePtr[0];
-    S->pCosFactor = pCosFactor[0];
-    break;
-  default:
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-
-  /* Initialize the RFFT/RIFFT */
-  arm_rfft_init_q15(S->pRfft, S->pCfft, S->N, 0u, 1u);
-
-  /* return the status of DCT4 Init function */
-  return (status);
-}
-
-/**    
-   * @} end of DCT4_IDCT4 group    
-   */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q31.c
deleted file mode 100644
index 9294ae062c..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q31.c
+++ /dev/null
@@ -1,8356 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_dct4_init_q31.c    
-*    
-* Description:	Initialization function of DCT-4 & IDCT4 Q31    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupTransforms    
- */
-
-/**    
- * @addtogroup DCT4_IDCT4    
- * @{    
- */
-
-/*    
-* @brief  Weights Table    
-*/
-
-/**    
-* \par    
-* Weights tables are generated using the formula : 
weights[n] = e^(-j*n*pi/(2*N))
    
-* \par    
-* C command to generate the table    
-* 
    
-* for(i = 0; i< N; i++)    
-* {    
-*   weights[2*i]= cos(i*c);    
-*   weights[(2*i)+1]= -sin(i * c);    
-* } 
    
-* \par    
-* where N is the Number of weights to be calculated and c is pi/(2*N)    
-* \par    
-* Convert the output to q31 format by multiplying with 2^31 and saturated if required.    
-* \par    
-* In the tables below the real and imaginary values are placed alternatively, hence the    
-* array length is 2*N.    
-*/
-
-static const q31_t WeightsQ31_128[256] = {
-  0x7fffffff, 0x0, 0x7ffd885a, 0xfe6de2e0, 0x7ff62182, 0xfcdbd541, 0x7fe9cbc0,
-  0xfb49e6a3,
-  0x7fd8878e, 0xf9b82684, 0x7fc25596, 0xf826a462, 0x7fa736b4, 0xf6956fb7,
-  0x7f872bf3, 0xf50497fb,
-  0x7f62368f, 0xf3742ca2, 0x7f3857f6, 0xf1e43d1c, 0x7f0991c4, 0xf054d8d5,
-  0x7ed5e5c6, 0xeec60f31,
-  0x7e9d55fc, 0xed37ef91, 0x7e5fe493, 0xebaa894f, 0x7e1d93ea, 0xea1debbb,
-  0x7dd6668f, 0xe8922622,
-  0x7d8a5f40, 0xe70747c4, 0x7d3980ec, 0xe57d5fda, 0x7ce3ceb2, 0xe3f47d96,
-  0x7c894bde, 0xe26cb01b,
-  0x7c29fbee, 0xe0e60685, 0x7bc5e290, 0xdf608fe4, 0x7b5d039e, 0xdddc5b3b,
-  0x7aef6323, 0xdc597781,
-  0x7a7d055b, 0xdad7f3a2, 0x7a05eead, 0xd957de7a, 0x798a23b1, 0xd7d946d8,
-  0x7909a92d, 0xd65c3b7b,
-  0x78848414, 0xd4e0cb15, 0x77fab989, 0xd3670446, 0x776c4edb, 0xd1eef59e,
-  0x76d94989, 0xd078ad9e,
-  0x7641af3d, 0xcf043ab3, 0x75a585cf, 0xcd91ab39, 0x7504d345, 0xcc210d79,
-  0x745f9dd1, 0xcab26fa9,
-  0x73b5ebd1, 0xc945dfec, 0x7307c3d0, 0xc7db6c50, 0x72552c85, 0xc67322ce,
-  0x719e2cd2, 0xc50d1149,
-  0x70e2cbc6, 0xc3a94590, 0x7023109a, 0xc247cd5a, 0x6f5f02b2, 0xc0e8b648,
-  0x6e96a99d, 0xbf8c0de3,
-  0x6dca0d14, 0xbe31e19b, 0x6cf934fc, 0xbcda3ecb, 0x6c242960, 0xbb8532b0,
-  0x6b4af279, 0xba32ca71,
-  0x6a6d98a4, 0xb8e31319, 0x698c246c, 0xb796199b, 0x68a69e81, 0xb64beacd,
-  0x67bd0fbd, 0xb5049368,
-  0x66cf8120, 0xb3c0200c, 0x65ddfbd3, 0xb27e9d3c, 0x64e88926, 0xb140175b,
-  0x63ef3290, 0xb0049ab3,
-  0x62f201ac, 0xaecc336c, 0x61f1003f, 0xad96ed92, 0x60ec3830, 0xac64d510,
-  0x5fe3b38d, 0xab35f5b5,
-  0x5ed77c8a, 0xaa0a5b2e, 0x5dc79d7c, 0xa8e21106, 0x5cb420e0, 0xa7bd22ac,
-  0x5b9d1154, 0xa69b9b68,
-  0x5a82799a, 0xa57d8666, 0x59646498, 0xa462eeac, 0x5842dd54, 0xa34bdf20,
-  0x571deefa, 0xa2386284,
-  0x55f5a4d2, 0xa1288376, 0x54ca0a4b, 0xa01c4c73, 0x539b2af0, 0x9f13c7d0,
-  0x5269126e, 0x9e0effc1,
-  0x5133cc94, 0x9d0dfe54, 0x4ffb654d, 0x9c10cd70, 0x4ebfe8a5, 0x9b1776da,
-  0x4d8162c4, 0x9a22042d,
-  0x4c3fdff4, 0x99307ee0, 0x4afb6c98, 0x9842f043, 0x49b41533, 0x9759617f,
-  0x4869e665, 0x9673db94,
-  0x471cece7, 0x9592675c, 0x45cd358f, 0x94b50d87, 0x447acd50, 0x93dbd6a0,
-  0x4325c135, 0x9306cb04,
-  0x41ce1e65, 0x9235f2ec, 0x4073f21d, 0x91695663, 0x3f1749b8, 0x90a0fd4e,
-  0x3db832a6, 0x8fdcef66,
-  0x3c56ba70, 0x8f1d343a, 0x3af2eeb7, 0x8e61d32e, 0x398cdd32, 0x8daad37b,
-  0x382493b0, 0x8cf83c30,
-  0x36ba2014, 0x8c4a142f, 0x354d9057, 0x8ba0622f, 0x33def287, 0x8afb2cbb,
-  0x326e54c7, 0x8a5a7a31,
-  0x30fbc54d, 0x89be50c3, 0x2f875262, 0x8926b677, 0x2e110a62, 0x8893b125,
-  0x2c98fbba, 0x88054677,
-  0x2b1f34eb, 0x877b7bec, 0x29a3c485, 0x86f656d3, 0x2826b928, 0x8675dc4f,
-  0x26a82186, 0x85fa1153,
-  0x25280c5e, 0x8582faa5, 0x23a6887f, 0x85109cdd, 0x2223a4c5, 0x84a2fc62,
-  0x209f701c, 0x843a1d70,
-  0x1f19f97b, 0x83d60412, 0x1d934fe5, 0x8376b422, 0x1c0b826a, 0x831c314e,
-  0x1a82a026, 0x82c67f14,
-  0x18f8b83c, 0x8275a0c0, 0x176dd9de, 0x82299971, 0x15e21445, 0x81e26c16,
-  0x145576b1, 0x81a01b6d,
-  0x12c8106f, 0x8162aa04, 0x1139f0cf, 0x812a1a3a, 0xfab272b, 0x80f66e3c,
-  0xe1bc2e4, 0x80c7a80a,
-  0xc8bd35e, 0x809dc971, 0xafb6805, 0x8078d40d, 0x96a9049, 0x8058c94c,
-  0x7d95b9e, 0x803daa6a,
-  0x647d97c, 0x80277872, 0x4b6195d, 0x80163440, 0x3242abf, 0x8009de7e,
-  0x1921d20, 0x800277a6,
-};
-
-static const q31_t WeightsQ31_512[1024] = {
-  0x7fffffff, 0x0, 0x7fffd886, 0xff9b781d, 0x7fff6216, 0xff36f078, 0x7ffe9cb2,
-  0xfed2694f,
-  0x7ffd885a, 0xfe6de2e0, 0x7ffc250f, 0xfe095d69, 0x7ffa72d1, 0xfda4d929,
-  0x7ff871a2, 0xfd40565c,
-  0x7ff62182, 0xfcdbd541, 0x7ff38274, 0xfc775616, 0x7ff09478, 0xfc12d91a,
-  0x7fed5791, 0xfbae5e89,
-  0x7fe9cbc0, 0xfb49e6a3, 0x7fe5f108, 0xfae571a4, 0x7fe1c76b, 0xfa80ffcb,
-  0x7fdd4eec, 0xfa1c9157,
-  0x7fd8878e, 0xf9b82684, 0x7fd37153, 0xf953bf91, 0x7fce0c3e, 0xf8ef5cbb,
-  0x7fc85854, 0xf88afe42,
-  0x7fc25596, 0xf826a462, 0x7fbc040a, 0xf7c24f59, 0x7fb563b3, 0xf75dff66,
-  0x7fae7495, 0xf6f9b4c6,
-  0x7fa736b4, 0xf6956fb7, 0x7f9faa15, 0xf6313077, 0x7f97cebd, 0xf5ccf743,
-  0x7f8fa4b0, 0xf568c45b,
-  0x7f872bf3, 0xf50497fb, 0x7f7e648c, 0xf4a07261, 0x7f754e80, 0xf43c53cb,
-  0x7f6be9d4, 0xf3d83c77,
-  0x7f62368f, 0xf3742ca2, 0x7f5834b7, 0xf310248a, 0x7f4de451, 0xf2ac246e,
-  0x7f434563, 0xf2482c8a,
-  0x7f3857f6, 0xf1e43d1c, 0x7f2d1c0e, 0xf1805662, 0x7f2191b4, 0xf11c789a,
-  0x7f15b8ee, 0xf0b8a401,
-  0x7f0991c4, 0xf054d8d5, 0x7efd1c3c, 0xeff11753, 0x7ef05860, 0xef8d5fb8,
-  0x7ee34636, 0xef29b243,
-  0x7ed5e5c6, 0xeec60f31, 0x7ec8371a, 0xee6276bf, 0x7eba3a39, 0xedfee92b,
-  0x7eabef2c, 0xed9b66b2,
-  0x7e9d55fc, 0xed37ef91, 0x7e8e6eb2, 0xecd48407, 0x7e7f3957, 0xec71244f,
-  0x7e6fb5f4, 0xec0dd0a8,
-  0x7e5fe493, 0xebaa894f, 0x7e4fc53e, 0xeb474e81, 0x7e3f57ff, 0xeae4207a,
-  0x7e2e9cdf, 0xea80ff7a,
-  0x7e1d93ea, 0xea1debbb, 0x7e0c3d29, 0xe9bae57d, 0x7dfa98a8, 0xe957ecfb,
-  0x7de8a670, 0xe8f50273,
-  0x7dd6668f, 0xe8922622, 0x7dc3d90d, 0xe82f5844, 0x7db0fdf8, 0xe7cc9917,
-  0x7d9dd55a, 0xe769e8d8,
-  0x7d8a5f40, 0xe70747c4, 0x7d769bb5, 0xe6a4b616, 0x7d628ac6, 0xe642340d,
-  0x7d4e2c7f, 0xe5dfc1e5,
-  0x7d3980ec, 0xe57d5fda, 0x7d24881b, 0xe51b0e2a, 0x7d0f4218, 0xe4b8cd11,
-  0x7cf9aef0, 0xe4569ccb,
-  0x7ce3ceb2, 0xe3f47d96, 0x7ccda169, 0xe3926fad, 0x7cb72724, 0xe330734d,
-  0x7ca05ff1, 0xe2ce88b3,
-  0x7c894bde, 0xe26cb01b, 0x7c71eaf9, 0xe20ae9c1, 0x7c5a3d50, 0xe1a935e2,
-  0x7c4242f2, 0xe14794ba,
-  0x7c29fbee, 0xe0e60685, 0x7c116853, 0xe0848b7f, 0x7bf88830, 0xe02323e5,
-  0x7bdf5b94, 0xdfc1cff3,
-  0x7bc5e290, 0xdf608fe4, 0x7bac1d31, 0xdeff63f4, 0x7b920b89, 0xde9e4c60,
-  0x7b77ada8, 0xde3d4964,
-  0x7b5d039e, 0xdddc5b3b, 0x7b420d7a, 0xdd7b8220, 0x7b26cb4f, 0xdd1abe51,
-  0x7b0b3d2c, 0xdcba1008,
-  0x7aef6323, 0xdc597781, 0x7ad33d45, 0xdbf8f4f8, 0x7ab6cba4, 0xdb9888a8,
-  0x7a9a0e50, 0xdb3832cd,
-  0x7a7d055b, 0xdad7f3a2, 0x7a5fb0d8, 0xda77cb63, 0x7a4210d8, 0xda17ba4a,
-  0x7a24256f, 0xd9b7c094,
-  0x7a05eead, 0xd957de7a, 0x79e76ca7, 0xd8f81439, 0x79c89f6e, 0xd898620c,
-  0x79a98715, 0xd838c82d,
-  0x798a23b1, 0xd7d946d8, 0x796a7554, 0xd779de47, 0x794a7c12, 0xd71a8eb5,
-  0x792a37fe, 0xd6bb585e,
-  0x7909a92d, 0xd65c3b7b, 0x78e8cfb2, 0xd5fd3848, 0x78c7aba2, 0xd59e4eff,
-  0x78a63d11, 0xd53f7fda,
-  0x78848414, 0xd4e0cb15, 0x786280bf, 0xd48230e9, 0x78403329, 0xd423b191,
-  0x781d9b65, 0xd3c54d47,
-  0x77fab989, 0xd3670446, 0x77d78daa, 0xd308d6c7, 0x77b417df, 0xd2aac504,
-  0x7790583e, 0xd24ccf39,
-  0x776c4edb, 0xd1eef59e, 0x7747fbce, 0xd191386e, 0x77235f2d, 0xd13397e2,
-  0x76fe790e, 0xd0d61434,
-  0x76d94989, 0xd078ad9e, 0x76b3d0b4, 0xd01b6459, 0x768e0ea6, 0xcfbe389f,
-  0x76680376, 0xcf612aaa,
-  0x7641af3d, 0xcf043ab3, 0x761b1211, 0xcea768f2, 0x75f42c0b, 0xce4ab5a2,
-  0x75ccfd42, 0xcdee20fc,
-  0x75a585cf, 0xcd91ab39, 0x757dc5ca, 0xcd355491, 0x7555bd4c, 0xccd91d3d,
-  0x752d6c6c, 0xcc7d0578,
-  0x7504d345, 0xcc210d79, 0x74dbf1ef, 0xcbc53579, 0x74b2c884, 0xcb697db0,
-  0x7489571c, 0xcb0de658,
-  0x745f9dd1, 0xcab26fa9, 0x74359cbd, 0xca5719db, 0x740b53fb, 0xc9fbe527,
-  0x73e0c3a3, 0xc9a0d1c5,
-  0x73b5ebd1, 0xc945dfec, 0x738acc9e, 0xc8eb0fd6, 0x735f6626, 0xc89061ba,
-  0x7333b883, 0xc835d5d0,
-  0x7307c3d0, 0xc7db6c50, 0x72db8828, 0xc7812572, 0x72af05a7, 0xc727016d,
-  0x72823c67, 0xc6cd0079,
-  0x72552c85, 0xc67322ce, 0x7227d61c, 0xc61968a2, 0x71fa3949, 0xc5bfd22e,
-  0x71cc5626, 0xc5665fa9,
-  0x719e2cd2, 0xc50d1149, 0x716fbd68, 0xc4b3e746, 0x71410805, 0xc45ae1d7,
-  0x71120cc5, 0xc4020133,
-  0x70e2cbc6, 0xc3a94590, 0x70b34525, 0xc350af26, 0x708378ff, 0xc2f83e2a,
-  0x70536771, 0xc29ff2d4,
-  0x7023109a, 0xc247cd5a, 0x6ff27497, 0xc1efcdf3, 0x6fc19385, 0xc197f4d4,
-  0x6f906d84, 0xc1404233,
-  0x6f5f02b2, 0xc0e8b648, 0x6f2d532c, 0xc0915148, 0x6efb5f12, 0xc03a1368,
-  0x6ec92683, 0xbfe2fcdf,
-  0x6e96a99d, 0xbf8c0de3, 0x6e63e87f, 0xbf3546a8, 0x6e30e34a, 0xbedea765,
-  0x6dfd9a1c, 0xbe88304f,
-  0x6dca0d14, 0xbe31e19b, 0x6d963c54, 0xbddbbb7f, 0x6d6227fa, 0xbd85be30,
-  0x6d2dd027, 0xbd2fe9e2,
-  0x6cf934fc, 0xbcda3ecb, 0x6cc45698, 0xbc84bd1f, 0x6c8f351c, 0xbc2f6513,
-  0x6c59d0a9, 0xbbda36dd,
-  0x6c242960, 0xbb8532b0, 0x6bee3f62, 0xbb3058c0, 0x6bb812d1, 0xbadba943,
-  0x6b81a3cd, 0xba87246d,
-  0x6b4af279, 0xba32ca71, 0x6b13fef5, 0xb9de9b83, 0x6adcc964, 0xb98a97d8,
-  0x6aa551e9, 0xb936bfa4,
-  0x6a6d98a4, 0xb8e31319, 0x6a359db9, 0xb88f926d, 0x69fd614a, 0xb83c3dd1,
-  0x69c4e37a, 0xb7e9157a,
-  0x698c246c, 0xb796199b, 0x69532442, 0xb7434a67, 0x6919e320, 0xb6f0a812,
-  0x68e06129, 0xb69e32cd,
-  0x68a69e81, 0xb64beacd, 0x686c9b4b, 0xb5f9d043, 0x683257ab, 0xb5a7e362,
-  0x67f7d3c5, 0xb556245e,
-  0x67bd0fbd, 0xb5049368, 0x67820bb7, 0xb4b330b3, 0x6746c7d8, 0xb461fc70,
-  0x670b4444, 0xb410f6d3,
-  0x66cf8120, 0xb3c0200c, 0x66937e91, 0xb36f784f, 0x66573cbb, 0xb31effcc,
-  0x661abbc5, 0xb2ceb6b5,
-  0x65ddfbd3, 0xb27e9d3c, 0x65a0fd0b, 0xb22eb392, 0x6563bf92, 0xb1def9e9,
-  0x6526438f, 0xb18f7071,
-  0x64e88926, 0xb140175b, 0x64aa907f, 0xb0f0eeda, 0x646c59bf, 0xb0a1f71d,
-  0x642de50d, 0xb0533055,
-  0x63ef3290, 0xb0049ab3, 0x63b0426d, 0xafb63667, 0x637114cc, 0xaf6803a2,
-  0x6331a9d4, 0xaf1a0293,
-  0x62f201ac, 0xaecc336c, 0x62b21c7b, 0xae7e965b, 0x6271fa69, 0xae312b92,
-  0x62319b9d, 0xade3f33e,
-  0x61f1003f, 0xad96ed92, 0x61b02876, 0xad4a1aba, 0x616f146c, 0xacfd7ae8,
-  0x612dc447, 0xacb10e4b,
-  0x60ec3830, 0xac64d510, 0x60aa7050, 0xac18cf69, 0x60686ccf, 0xabccfd83,
-  0x60262dd6, 0xab815f8d,
-  0x5fe3b38d, 0xab35f5b5, 0x5fa0fe1f, 0xaaeac02c, 0x5f5e0db3, 0xaa9fbf1e,
-  0x5f1ae274, 0xaa54f2ba,
-  0x5ed77c8a, 0xaa0a5b2e, 0x5e93dc1f, 0xa9bff8a8, 0x5e50015d, 0xa975cb57,
-  0x5e0bec6e, 0xa92bd367,
-  0x5dc79d7c, 0xa8e21106, 0x5d8314b1, 0xa8988463, 0x5d3e5237, 0xa84f2daa,
-  0x5cf95638, 0xa8060d08,
-  0x5cb420e0, 0xa7bd22ac, 0x5c6eb258, 0xa7746ec0, 0x5c290acc, 0xa72bf174,
-  0x5be32a67, 0xa6e3aaf2,
-  0x5b9d1154, 0xa69b9b68, 0x5b56bfbd, 0xa653c303, 0x5b1035cf, 0xa60c21ee,
-  0x5ac973b5, 0xa5c4b855,
-  0x5a82799a, 0xa57d8666, 0x5a3b47ab, 0xa5368c4b, 0x59f3de12, 0xa4efca31,
-  0x59ac3cfd, 0xa4a94043,
-  0x59646498, 0xa462eeac, 0x591c550e, 0xa41cd599, 0x58d40e8c, 0xa3d6f534,
-  0x588b9140, 0xa3914da8,
-  0x5842dd54, 0xa34bdf20, 0x57f9f2f8, 0xa306a9c8, 0x57b0d256, 0xa2c1adc9,
-  0x57677b9d, 0xa27ceb4f,
-  0x571deefa, 0xa2386284, 0x56d42c99, 0xa1f41392, 0x568a34a9, 0xa1affea3,
-  0x56400758, 0xa16c23e1,
-  0x55f5a4d2, 0xa1288376, 0x55ab0d46, 0xa0e51d8c, 0x556040e2, 0xa0a1f24d,
-  0x55153fd4, 0xa05f01e1,
-  0x54ca0a4b, 0xa01c4c73, 0x547ea073, 0x9fd9d22a, 0x5433027d, 0x9f979331,
-  0x53e73097, 0x9f558fb0,
-  0x539b2af0, 0x9f13c7d0, 0x534ef1b5, 0x9ed23bb9, 0x53028518, 0x9e90eb94,
-  0x52b5e546, 0x9e4fd78a,
-  0x5269126e, 0x9e0effc1, 0x521c0cc2, 0x9dce6463, 0x51ced46e, 0x9d8e0597,
-  0x518169a5, 0x9d4de385,
-  0x5133cc94, 0x9d0dfe54, 0x50e5fd6d, 0x9cce562c, 0x5097fc5e, 0x9c8eeb34,
-  0x5049c999, 0x9c4fbd93,
-  0x4ffb654d, 0x9c10cd70, 0x4faccfab, 0x9bd21af3, 0x4f5e08e3, 0x9b93a641,
-  0x4f0f1126, 0x9b556f81,
-  0x4ebfe8a5, 0x9b1776da, 0x4e708f8f, 0x9ad9bc71, 0x4e210617, 0x9a9c406e,
-  0x4dd14c6e, 0x9a5f02f5,
-  0x4d8162c4, 0x9a22042d, 0x4d31494b, 0x99e5443b, 0x4ce10034, 0x99a8c345,
-  0x4c9087b1, 0x996c816f,
-  0x4c3fdff4, 0x99307ee0, 0x4bef092d, 0x98f4bbbc, 0x4b9e0390, 0x98b93828,
-  0x4b4ccf4d, 0x987df449,
-  0x4afb6c98, 0x9842f043, 0x4aa9dba2, 0x98082c3b, 0x4a581c9e, 0x97cda855,
-  0x4a062fbd, 0x979364b5,
-  0x49b41533, 0x9759617f, 0x4961cd33, 0x971f9ed7, 0x490f57ee, 0x96e61ce0,
-  0x48bcb599, 0x96acdbbe,
-  0x4869e665, 0x9673db94, 0x4816ea86, 0x963b1c86, 0x47c3c22f, 0x96029eb6,
-  0x47706d93, 0x95ca6247,
-  0x471cece7, 0x9592675c, 0x46c9405c, 0x955aae17, 0x46756828, 0x9523369c,
-  0x4621647d, 0x94ec010b,
-  0x45cd358f, 0x94b50d87, 0x4578db93, 0x947e5c33, 0x452456bd, 0x9447ed2f,
-  0x44cfa740, 0x9411c09e,
-  0x447acd50, 0x93dbd6a0, 0x4425c923, 0x93a62f57, 0x43d09aed, 0x9370cae4,
-  0x437b42e1, 0x933ba968,
-  0x4325c135, 0x9306cb04, 0x42d0161e, 0x92d22fd9, 0x427a41d0, 0x929dd806,
-  0x42244481, 0x9269c3ac,
-  0x41ce1e65, 0x9235f2ec, 0x4177cfb1, 0x920265e4, 0x4121589b, 0x91cf1cb6,
-  0x40cab958, 0x919c1781,
-  0x4073f21d, 0x91695663, 0x401d0321, 0x9136d97d, 0x3fc5ec98, 0x9104a0ee,
-  0x3f6eaeb8, 0x90d2acd4,
-  0x3f1749b8, 0x90a0fd4e, 0x3ebfbdcd, 0x906f927c, 0x3e680b2c, 0x903e6c7b,
-  0x3e10320d, 0x900d8b69,
-  0x3db832a6, 0x8fdcef66, 0x3d600d2c, 0x8fac988f, 0x3d07c1d6, 0x8f7c8701,
-  0x3caf50da, 0x8f4cbadb,
-  0x3c56ba70, 0x8f1d343a, 0x3bfdfecd, 0x8eedf33b, 0x3ba51e29, 0x8ebef7fb,
-  0x3b4c18ba, 0x8e904298,
-  0x3af2eeb7, 0x8e61d32e, 0x3a99a057, 0x8e33a9da, 0x3a402dd2, 0x8e05c6b7,
-  0x39e6975e, 0x8dd829e4,
-  0x398cdd32, 0x8daad37b, 0x3932ff87, 0x8d7dc399, 0x38d8fe93, 0x8d50fa59,
-  0x387eda8e, 0x8d2477d8,
-  0x382493b0, 0x8cf83c30, 0x37ca2a30, 0x8ccc477d, 0x376f9e46, 0x8ca099da,
-  0x3714f02a, 0x8c753362,
-  0x36ba2014, 0x8c4a142f, 0x365f2e3b, 0x8c1f3c5d, 0x36041ad9, 0x8bf4ac05,
-  0x35a8e625, 0x8bca6343,
-  0x354d9057, 0x8ba0622f, 0x34f219a8, 0x8b76a8e4, 0x34968250, 0x8b4d377c,
-  0x343aca87, 0x8b240e11,
-  0x33def287, 0x8afb2cbb, 0x3382fa88, 0x8ad29394, 0x3326e2c3, 0x8aaa42b4,
-  0x32caab6f, 0x8a823a36,
-  0x326e54c7, 0x8a5a7a31, 0x3211df04, 0x8a3302be, 0x31b54a5e, 0x8a0bd3f5,
-  0x3158970e, 0x89e4edef,
-  0x30fbc54d, 0x89be50c3, 0x309ed556, 0x8997fc8a, 0x3041c761, 0x8971f15a,
-  0x2fe49ba7, 0x894c2f4c,
-  0x2f875262, 0x8926b677, 0x2f29ebcc, 0x890186f2, 0x2ecc681e, 0x88dca0d3,
-  0x2e6ec792, 0x88b80432,
-  0x2e110a62, 0x8893b125, 0x2db330c7, 0x886fa7c2, 0x2d553afc, 0x884be821,
-  0x2cf72939, 0x88287256,
-  0x2c98fbba, 0x88054677, 0x2c3ab2b9, 0x87e2649b, 0x2bdc4e6f, 0x87bfccd7,
-  0x2b7dcf17, 0x879d7f41,
-  0x2b1f34eb, 0x877b7bec, 0x2ac08026, 0x8759c2ef, 0x2a61b101, 0x8738545e,
-  0x2a02c7b8, 0x8717304e,
-  0x29a3c485, 0x86f656d3, 0x2944a7a2, 0x86d5c802, 0x28e5714b, 0x86b583ee,
-  0x288621b9, 0x86958aac,
-  0x2826b928, 0x8675dc4f, 0x27c737d3, 0x865678eb, 0x27679df4, 0x86376092,
-  0x2707ebc7, 0x86189359,
-  0x26a82186, 0x85fa1153, 0x26483f6c, 0x85dbda91, 0x25e845b6, 0x85bdef28,
-  0x2588349d, 0x85a04f28,
-  0x25280c5e, 0x8582faa5, 0x24c7cd33, 0x8565f1b0, 0x24677758, 0x8549345c,
-  0x24070b08, 0x852cc2bb,
-  0x23a6887f, 0x85109cdd, 0x2345eff8, 0x84f4c2d4, 0x22e541af, 0x84d934b1,
-  0x22847de0, 0x84bdf286,
-  0x2223a4c5, 0x84a2fc62, 0x21c2b69c, 0x84885258, 0x2161b3a0, 0x846df477,
-  0x21009c0c, 0x8453e2cf,
-  0x209f701c, 0x843a1d70, 0x203e300d, 0x8420a46c, 0x1fdcdc1b, 0x840777d0,
-  0x1f7b7481, 0x83ee97ad,
-  0x1f19f97b, 0x83d60412, 0x1eb86b46, 0x83bdbd0e, 0x1e56ca1e, 0x83a5c2b0,
-  0x1df5163f, 0x838e1507,
-  0x1d934fe5, 0x8376b422, 0x1d31774d, 0x835fa00f, 0x1ccf8cb3, 0x8348d8dc,
-  0x1c6d9053, 0x83325e97,
-  0x1c0b826a, 0x831c314e, 0x1ba96335, 0x83065110, 0x1b4732ef, 0x82f0bde8,
-  0x1ae4f1d6, 0x82db77e5,
-  0x1a82a026, 0x82c67f14, 0x1a203e1b, 0x82b1d381, 0x19bdcbf3, 0x829d753a,
-  0x195b49ea, 0x8289644b,
-  0x18f8b83c, 0x8275a0c0, 0x18961728, 0x82622aa6, 0x183366e9, 0x824f0208,
-  0x17d0a7bc, 0x823c26f3,
-  0x176dd9de, 0x82299971, 0x170afd8d, 0x82175990, 0x16a81305, 0x82056758,
-  0x16451a83, 0x81f3c2d7,
-  0x15e21445, 0x81e26c16, 0x157f0086, 0x81d16321, 0x151bdf86, 0x81c0a801,
-  0x14b8b17f, 0x81b03ac2,
-  0x145576b1, 0x81a01b6d, 0x13f22f58, 0x81904a0c, 0x138edbb1, 0x8180c6a9,
-  0x132b7bf9, 0x8171914e,
-  0x12c8106f, 0x8162aa04, 0x1264994e, 0x815410d4, 0x120116d5, 0x8145c5c7,
-  0x119d8941, 0x8137c8e6,
-  0x1139f0cf, 0x812a1a3a, 0x10d64dbd, 0x811cb9ca, 0x1072a048, 0x810fa7a0,
-  0x100ee8ad, 0x8102e3c4,
-  0xfab272b, 0x80f66e3c, 0xf475bff, 0x80ea4712, 0xee38766, 0x80de6e4c,
-  0xe7fa99e, 0x80d2e3f2,
-  0xe1bc2e4, 0x80c7a80a, 0xdb7d376, 0x80bcba9d, 0xd53db92, 0x80b21baf,
-  0xcefdb76, 0x80a7cb49,
-  0xc8bd35e, 0x809dc971, 0xc27c389, 0x8094162c, 0xbc3ac35, 0x808ab180,
-  0xb5f8d9f, 0x80819b74,
-  0xafb6805, 0x8078d40d, 0xa973ba5, 0x80705b50, 0xa3308bd, 0x80683143,
-  0x9cecf89, 0x806055eb,
-  0x96a9049, 0x8058c94c, 0x9064b3a, 0x80518b6b, 0x8a2009a, 0x804a9c4d,
-  0x83db0a7, 0x8043fbf6,
-  0x7d95b9e, 0x803daa6a, 0x77501be, 0x8037a7ac, 0x710a345, 0x8031f3c2,
-  0x6ac406f, 0x802c8ead,
-  0x647d97c, 0x80277872, 0x5e36ea9, 0x8022b114, 0x57f0035, 0x801e3895,
-  0x51a8e5c, 0x801a0ef8,
-  0x4b6195d, 0x80163440, 0x451a177, 0x8012a86f, 0x3ed26e6, 0x800f6b88,
-  0x388a9ea, 0x800c7d8c,
-  0x3242abf, 0x8009de7e, 0x2bfa9a4, 0x80078e5e, 0x25b26d7, 0x80058d2f,
-  0x1f6a297, 0x8003daf1,
-  0x1921d20, 0x800277a6, 0x12d96b1, 0x8001634e, 0xc90f88, 0x80009dea,
-  0x6487e3, 0x8000277a,
-};
-
-static const q31_t WeightsQ31_2048[4096] = {
-  0x7fffffff, 0x0, 0x7ffffd88, 0xffe6de05, 0x7ffff621, 0xffcdbc0b, 0x7fffe9cb,
-  0xffb49a12,
-  0x7fffd886, 0xff9b781d, 0x7fffc251, 0xff82562c, 0x7fffa72c, 0xff69343f,
-  0x7fff8719, 0xff501258,
-  0x7fff6216, 0xff36f078, 0x7fff3824, 0xff1dcea0, 0x7fff0943, 0xff04acd0,
-  0x7ffed572, 0xfeeb8b0a,
-  0x7ffe9cb2, 0xfed2694f, 0x7ffe5f03, 0xfeb947a0, 0x7ffe1c65, 0xfea025fd,
-  0x7ffdd4d7, 0xfe870467,
-  0x7ffd885a, 0xfe6de2e0, 0x7ffd36ee, 0xfe54c169, 0x7ffce093, 0xfe3ba002,
-  0x7ffc8549, 0xfe227eac,
-  0x7ffc250f, 0xfe095d69, 0x7ffbbfe6, 0xfdf03c3a, 0x7ffb55ce, 0xfdd71b1e,
-  0x7ffae6c7, 0xfdbdfa18,
-  0x7ffa72d1, 0xfda4d929, 0x7ff9f9ec, 0xfd8bb850, 0x7ff97c18, 0xfd729790,
-  0x7ff8f954, 0xfd5976e9,
-  0x7ff871a2, 0xfd40565c, 0x7ff7e500, 0xfd2735ea, 0x7ff75370, 0xfd0e1594,
-  0x7ff6bcf0, 0xfcf4f55c,
-  0x7ff62182, 0xfcdbd541, 0x7ff58125, 0xfcc2b545, 0x7ff4dbd9, 0xfca9956a,
-  0x7ff4319d, 0xfc9075af,
-  0x7ff38274, 0xfc775616, 0x7ff2ce5b, 0xfc5e36a0, 0x7ff21553, 0xfc45174e,
-  0x7ff1575d, 0xfc2bf821,
-  0x7ff09478, 0xfc12d91a, 0x7fefcca4, 0xfbf9ba39, 0x7feeffe1, 0xfbe09b80,
-  0x7fee2e30, 0xfbc77cf0,
-  0x7fed5791, 0xfbae5e89, 0x7fec7c02, 0xfb95404d, 0x7feb9b85, 0xfb7c223d,
-  0x7feab61a, 0xfb630459,
-  0x7fe9cbc0, 0xfb49e6a3, 0x7fe8dc78, 0xfb30c91b, 0x7fe7e841, 0xfb17abc2,
-  0x7fe6ef1c, 0xfafe8e9b,
-  0x7fe5f108, 0xfae571a4, 0x7fe4ee06, 0xfacc54e0, 0x7fe3e616, 0xfab3384f,
-  0x7fe2d938, 0xfa9a1bf3,
-  0x7fe1c76b, 0xfa80ffcb, 0x7fe0b0b1, 0xfa67e3da, 0x7fdf9508, 0xfa4ec821,
-  0x7fde7471, 0xfa35ac9f,
-  0x7fdd4eec, 0xfa1c9157, 0x7fdc247a, 0xfa037648, 0x7fdaf519, 0xf9ea5b75,
-  0x7fd9c0ca, 0xf9d140de,
-  0x7fd8878e, 0xf9b82684, 0x7fd74964, 0xf99f0c68, 0x7fd6064c, 0xf985f28a,
-  0x7fd4be46, 0xf96cd8ed,
-  0x7fd37153, 0xf953bf91, 0x7fd21f72, 0xf93aa676, 0x7fd0c8a3, 0xf9218d9e,
-  0x7fcf6ce8, 0xf908750a,
-  0x7fce0c3e, 0xf8ef5cbb, 0x7fcca6a7, 0xf8d644b2, 0x7fcb3c23, 0xf8bd2cef,
-  0x7fc9ccb2, 0xf8a41574,
-  0x7fc85854, 0xf88afe42, 0x7fc6df08, 0xf871e759, 0x7fc560cf, 0xf858d0bb,
-  0x7fc3dda9, 0xf83fba68,
-  0x7fc25596, 0xf826a462, 0x7fc0c896, 0xf80d8ea9, 0x7fbf36aa, 0xf7f4793e,
-  0x7fbd9fd0, 0xf7db6423,
-  0x7fbc040a, 0xf7c24f59, 0x7fba6357, 0xf7a93ae0, 0x7fb8bdb8, 0xf79026b9,
-  0x7fb7132b, 0xf77712e5,
-  0x7fb563b3, 0xf75dff66, 0x7fb3af4e, 0xf744ec3b, 0x7fb1f5fc, 0xf72bd967,
-  0x7fb037bf, 0xf712c6ea,
-  0x7fae7495, 0xf6f9b4c6, 0x7facac7f, 0xf6e0a2fa, 0x7faadf7c, 0xf6c79188,
-  0x7fa90d8e, 0xf6ae8071,
-  0x7fa736b4, 0xf6956fb7, 0x7fa55aee, 0xf67c5f59, 0x7fa37a3c, 0xf6634f59,
-  0x7fa1949e, 0xf64a3fb8,
-  0x7f9faa15, 0xf6313077, 0x7f9dbaa0, 0xf6182196, 0x7f9bc640, 0xf5ff1318,
-  0x7f99ccf4, 0xf5e604fc,
-  0x7f97cebd, 0xf5ccf743, 0x7f95cb9a, 0xf5b3e9f0, 0x7f93c38c, 0xf59add02,
-  0x7f91b694, 0xf581d07b,
-  0x7f8fa4b0, 0xf568c45b, 0x7f8d8de1, 0xf54fb8a4, 0x7f8b7227, 0xf536ad56,
-  0x7f895182, 0xf51da273,
-  0x7f872bf3, 0xf50497fb, 0x7f850179, 0xf4eb8def, 0x7f82d214, 0xf4d28451,
-  0x7f809dc5, 0xf4b97b21,
-  0x7f7e648c, 0xf4a07261, 0x7f7c2668, 0xf4876a10, 0x7f79e35a, 0xf46e6231,
-  0x7f779b62, 0xf4555ac5,
-  0x7f754e80, 0xf43c53cb, 0x7f72fcb4, 0xf4234d45, 0x7f70a5fe, 0xf40a4735,
-  0x7f6e4a5e, 0xf3f1419a,
-  0x7f6be9d4, 0xf3d83c77, 0x7f698461, 0xf3bf37cb, 0x7f671a05, 0xf3a63398,
-  0x7f64aabf, 0xf38d2fe0,
-  0x7f62368f, 0xf3742ca2, 0x7f5fbd77, 0xf35b29e0, 0x7f5d3f75, 0xf342279b,
-  0x7f5abc8a, 0xf32925d3,
-  0x7f5834b7, 0xf310248a, 0x7f55a7fa, 0xf2f723c1, 0x7f531655, 0xf2de2379,
-  0x7f507fc7, 0xf2c523b2,
-  0x7f4de451, 0xf2ac246e, 0x7f4b43f2, 0xf29325ad, 0x7f489eaa, 0xf27a2771,
-  0x7f45f47b, 0xf26129ba,
-  0x7f434563, 0xf2482c8a, 0x7f409164, 0xf22f2fe1, 0x7f3dd87c, 0xf21633c0,
-  0x7f3b1aad, 0xf1fd3829,
-  0x7f3857f6, 0xf1e43d1c, 0x7f359057, 0xf1cb429a, 0x7f32c3d1, 0xf1b248a5,
-  0x7f2ff263, 0xf1994f3d,
-  0x7f2d1c0e, 0xf1805662, 0x7f2a40d2, 0xf1675e17, 0x7f2760af, 0xf14e665c,
-  0x7f247ba5, 0xf1356f32,
-  0x7f2191b4, 0xf11c789a, 0x7f1ea2dc, 0xf1038295, 0x7f1baf1e, 0xf0ea8d24,
-  0x7f18b679, 0xf0d19848,
-  0x7f15b8ee, 0xf0b8a401, 0x7f12b67c, 0xf09fb051, 0x7f0faf25, 0xf086bd39,
-  0x7f0ca2e7, 0xf06dcaba,
-  0x7f0991c4, 0xf054d8d5, 0x7f067bba, 0xf03be78a, 0x7f0360cb, 0xf022f6da,
-  0x7f0040f6, 0xf00a06c8,
-  0x7efd1c3c, 0xeff11753, 0x7ef9f29d, 0xefd8287c, 0x7ef6c418, 0xefbf3a45,
-  0x7ef390ae, 0xefa64cae,
-  0x7ef05860, 0xef8d5fb8, 0x7eed1b2c, 0xef747365, 0x7ee9d914, 0xef5b87b5,
-  0x7ee69217, 0xef429caa,
-  0x7ee34636, 0xef29b243, 0x7edff570, 0xef10c883, 0x7edc9fc6, 0xeef7df6a,
-  0x7ed94538, 0xeedef6f9,
-  0x7ed5e5c6, 0xeec60f31, 0x7ed28171, 0xeead2813, 0x7ecf1837, 0xee9441a0,
-  0x7ecbaa1a, 0xee7b5bd9,
-  0x7ec8371a, 0xee6276bf, 0x7ec4bf36, 0xee499253, 0x7ec14270, 0xee30ae96,
-  0x7ebdc0c6, 0xee17cb88,
-  0x7eba3a39, 0xedfee92b, 0x7eb6aeca, 0xede60780, 0x7eb31e78, 0xedcd2687,
-  0x7eaf8943, 0xedb44642,
-  0x7eabef2c, 0xed9b66b2, 0x7ea85033, 0xed8287d7, 0x7ea4ac58, 0xed69a9b3,
-  0x7ea1039b, 0xed50cc46,
-  0x7e9d55fc, 0xed37ef91, 0x7e99a37c, 0xed1f1396, 0x7e95ec1a, 0xed063856,
-  0x7e922fd6, 0xeced5dd0,
-  0x7e8e6eb2, 0xecd48407, 0x7e8aa8ac, 0xecbbaafb, 0x7e86ddc6, 0xeca2d2ad,
-  0x7e830dff, 0xec89fb1e,
-  0x7e7f3957, 0xec71244f, 0x7e7b5fce, 0xec584e41, 0x7e778166, 0xec3f78f6,
-  0x7e739e1d, 0xec26a46d,
-  0x7e6fb5f4, 0xec0dd0a8, 0x7e6bc8eb, 0xebf4fda8, 0x7e67d703, 0xebdc2b6e,
-  0x7e63e03b, 0xebc359fb,
-  0x7e5fe493, 0xebaa894f, 0x7e5be40c, 0xeb91b96c, 0x7e57dea7, 0xeb78ea52,
-  0x7e53d462, 0xeb601c04,
-  0x7e4fc53e, 0xeb474e81, 0x7e4bb13c, 0xeb2e81ca, 0x7e47985b, 0xeb15b5e1,
-  0x7e437a9c, 0xeafceac6,
-  0x7e3f57ff, 0xeae4207a, 0x7e3b3083, 0xeacb56ff, 0x7e37042a, 0xeab28e56,
-  0x7e32d2f4, 0xea99c67e,
-  0x7e2e9cdf, 0xea80ff7a, 0x7e2a61ed, 0xea683949, 0x7e26221f, 0xea4f73ee,
-  0x7e21dd73, 0xea36af69,
-  0x7e1d93ea, 0xea1debbb, 0x7e194584, 0xea0528e5, 0x7e14f242, 0xe9ec66e8,
-  0x7e109a24, 0xe9d3a5c5,
-  0x7e0c3d29, 0xe9bae57d, 0x7e07db52, 0xe9a22610, 0x7e0374a0, 0xe9896781,
-  0x7dff0911, 0xe970a9ce,
-  0x7dfa98a8, 0xe957ecfb, 0x7df62362, 0xe93f3107, 0x7df1a942, 0xe92675f4,
-  0x7ded2a47, 0xe90dbbc2,
-  0x7de8a670, 0xe8f50273, 0x7de41dc0, 0xe8dc4a07, 0x7ddf9034, 0xe8c39280,
-  0x7ddafdce, 0xe8aadbde,
-  0x7dd6668f, 0xe8922622, 0x7dd1ca75, 0xe879714d, 0x7dcd2981, 0xe860bd61,
-  0x7dc883b4, 0xe8480a5d,
-  0x7dc3d90d, 0xe82f5844, 0x7dbf298d, 0xe816a716, 0x7dba7534, 0xe7fdf6d4,
-  0x7db5bc02, 0xe7e5477f,
-  0x7db0fdf8, 0xe7cc9917, 0x7dac3b15, 0xe7b3eb9f, 0x7da77359, 0xe79b3f16,
-  0x7da2a6c6, 0xe782937e,
-  0x7d9dd55a, 0xe769e8d8, 0x7d98ff17, 0xe7513f25, 0x7d9423fc, 0xe7389665,
-  0x7d8f4409, 0xe71fee99,
-  0x7d8a5f40, 0xe70747c4, 0x7d85759f, 0xe6eea1e4, 0x7d808728, 0xe6d5fcfc,
-  0x7d7b93da, 0xe6bd590d,
-  0x7d769bb5, 0xe6a4b616, 0x7d719eba, 0xe68c141a, 0x7d6c9ce9, 0xe6737319,
-  0x7d679642, 0xe65ad315,
-  0x7d628ac6, 0xe642340d, 0x7d5d7a74, 0xe6299604, 0x7d58654d, 0xe610f8f9,
-  0x7d534b50, 0xe5f85cef,
-  0x7d4e2c7f, 0xe5dfc1e5, 0x7d4908d9, 0xe5c727dd, 0x7d43e05e, 0xe5ae8ed8,
-  0x7d3eb30f, 0xe595f6d7,
-  0x7d3980ec, 0xe57d5fda, 0x7d3449f5, 0xe564c9e3, 0x7d2f0e2b, 0xe54c34f3,
-  0x7d29cd8c, 0xe533a10a,
-  0x7d24881b, 0xe51b0e2a, 0x7d1f3dd6, 0xe5027c53, 0x7d19eebf, 0xe4e9eb87,
-  0x7d149ad5, 0xe4d15bc6,
-  0x7d0f4218, 0xe4b8cd11, 0x7d09e489, 0xe4a03f69, 0x7d048228, 0xe487b2d0,
-  0x7cff1af5, 0xe46f2745,
-  0x7cf9aef0, 0xe4569ccb, 0x7cf43e1a, 0xe43e1362, 0x7ceec873, 0xe4258b0a,
-  0x7ce94dfb, 0xe40d03c6,
-  0x7ce3ceb2, 0xe3f47d96, 0x7cde4a98, 0xe3dbf87a, 0x7cd8c1ae, 0xe3c37474,
-  0x7cd333f3, 0xe3aaf184,
-  0x7ccda169, 0xe3926fad, 0x7cc80a0f, 0xe379eeed, 0x7cc26de5, 0xe3616f48,
-  0x7cbcccec, 0xe348f0bd,
-  0x7cb72724, 0xe330734d, 0x7cb17c8d, 0xe317f6fa, 0x7cabcd28, 0xe2ff7bc3,
-  0x7ca618f3, 0xe2e701ac,
-  0x7ca05ff1, 0xe2ce88b3, 0x7c9aa221, 0xe2b610da, 0x7c94df83, 0xe29d9a23,
-  0x7c8f1817, 0xe285248d,
-  0x7c894bde, 0xe26cb01b, 0x7c837ad8, 0xe2543ccc, 0x7c7da505, 0xe23bcaa2,
-  0x7c77ca65, 0xe223599e,
-  0x7c71eaf9, 0xe20ae9c1, 0x7c6c06c0, 0xe1f27b0b, 0x7c661dbc, 0xe1da0d7e,
-  0x7c602fec, 0xe1c1a11b,
-  0x7c5a3d50, 0xe1a935e2, 0x7c5445e9, 0xe190cbd4, 0x7c4e49b7, 0xe17862f3,
-  0x7c4848ba, 0xe15ffb3f,
-  0x7c4242f2, 0xe14794ba, 0x7c3c3860, 0xe12f2f63, 0x7c362904, 0xe116cb3d,
-  0x7c3014de, 0xe0fe6848,
-  0x7c29fbee, 0xe0e60685, 0x7c23de35, 0xe0cda5f5, 0x7c1dbbb3, 0xe0b54698,
-  0x7c179467, 0xe09ce871,
-  0x7c116853, 0xe0848b7f, 0x7c0b3777, 0xe06c2fc4, 0x7c0501d2, 0xe053d541,
-  0x7bfec765, 0xe03b7bf6,
-  0x7bf88830, 0xe02323e5, 0x7bf24434, 0xe00acd0e, 0x7bebfb70, 0xdff27773,
-  0x7be5ade6, 0xdfda2314,
-  0x7bdf5b94, 0xdfc1cff3, 0x7bd9047c, 0xdfa97e0f, 0x7bd2a89e, 0xdf912d6b,
-  0x7bcc47fa, 0xdf78de07,
-  0x7bc5e290, 0xdf608fe4, 0x7bbf7860, 0xdf484302, 0x7bb9096b, 0xdf2ff764,
-  0x7bb295b0, 0xdf17ad0a,
-  0x7bac1d31, 0xdeff63f4, 0x7ba59fee, 0xdee71c24, 0x7b9f1de6, 0xdeced59b,
-  0x7b989719, 0xdeb69059,
-  0x7b920b89, 0xde9e4c60, 0x7b8b7b36, 0xde8609b1, 0x7b84e61f, 0xde6dc84b,
-  0x7b7e4c45, 0xde558831,
-  0x7b77ada8, 0xde3d4964, 0x7b710a49, 0xde250be3, 0x7b6a6227, 0xde0ccfb1,
-  0x7b63b543, 0xddf494ce,
-  0x7b5d039e, 0xdddc5b3b, 0x7b564d36, 0xddc422f8, 0x7b4f920e, 0xddabec08,
-  0x7b48d225, 0xdd93b66a,
-  0x7b420d7a, 0xdd7b8220, 0x7b3b4410, 0xdd634f2b, 0x7b3475e5, 0xdd4b1d8c,
-  0x7b2da2fa, 0xdd32ed43,
-  0x7b26cb4f, 0xdd1abe51, 0x7b1feee5, 0xdd0290b8, 0x7b190dbc, 0xdcea6478,
-  0x7b1227d3, 0xdcd23993,
-  0x7b0b3d2c, 0xdcba1008, 0x7b044dc7, 0xdca1e7da, 0x7afd59a4, 0xdc89c109,
-  0x7af660c2, 0xdc719b96,
-  0x7aef6323, 0xdc597781, 0x7ae860c7, 0xdc4154cd, 0x7ae159ae, 0xdc293379,
-  0x7ada4dd8, 0xdc111388,
-  0x7ad33d45, 0xdbf8f4f8, 0x7acc27f7, 0xdbe0d7cd, 0x7ac50dec, 0xdbc8bc06,
-  0x7abdef25, 0xdbb0a1a4,
-  0x7ab6cba4, 0xdb9888a8, 0x7aafa367, 0xdb807114, 0x7aa8766f, 0xdb685ae9,
-  0x7aa144bc, 0xdb504626,
-  0x7a9a0e50, 0xdb3832cd, 0x7a92d329, 0xdb2020e0, 0x7a8b9348, 0xdb08105e,
-  0x7a844eae, 0xdaf00149,
-  0x7a7d055b, 0xdad7f3a2, 0x7a75b74f, 0xdabfe76a, 0x7a6e648a, 0xdaa7dca1,
-  0x7a670d0d, 0xda8fd349,
-  0x7a5fb0d8, 0xda77cb63, 0x7a584feb, 0xda5fc4ef, 0x7a50ea47, 0xda47bfee,
-  0x7a497feb, 0xda2fbc61,
-  0x7a4210d8, 0xda17ba4a, 0x7a3a9d0f, 0xd9ffb9a9, 0x7a332490, 0xd9e7ba7f,
-  0x7a2ba75a, 0xd9cfbccd,
-  0x7a24256f, 0xd9b7c094, 0x7a1c9ece, 0xd99fc5d4, 0x7a151378, 0xd987cc90,
-  0x7a0d836d, 0xd96fd4c7,
-  0x7a05eead, 0xd957de7a, 0x79fe5539, 0xd93fe9ab, 0x79f6b711, 0xd927f65b,
-  0x79ef1436, 0xd910048a,
-  0x79e76ca7, 0xd8f81439, 0x79dfc064, 0xd8e0256a, 0x79d80f6f, 0xd8c8381d,
-  0x79d059c8, 0xd8b04c52,
-  0x79c89f6e, 0xd898620c, 0x79c0e062, 0xd880794b, 0x79b91ca4, 0xd868920f,
-  0x79b15435, 0xd850ac5a,
-  0x79a98715, 0xd838c82d, 0x79a1b545, 0xd820e589, 0x7999dec4, 0xd809046e,
-  0x79920392, 0xd7f124dd,
-  0x798a23b1, 0xd7d946d8, 0x79823f20, 0xd7c16a5f, 0x797a55e0, 0xd7a98f73,
-  0x797267f2, 0xd791b616,
-  0x796a7554, 0xd779de47, 0x79627e08, 0xd7620808, 0x795a820e, 0xd74a335b,
-  0x79528167, 0xd732603f,
-  0x794a7c12, 0xd71a8eb5, 0x79427210, 0xd702bec0, 0x793a6361, 0xd6eaf05f,
-  0x79325006, 0xd6d32393,
-  0x792a37fe, 0xd6bb585e, 0x79221b4b, 0xd6a38ec0, 0x7919f9ec, 0xd68bc6ba,
-  0x7911d3e2, 0xd674004e,
-  0x7909a92d, 0xd65c3b7b, 0x790179cd, 0xd6447844, 0x78f945c3, 0xd62cb6a8,
-  0x78f10d0f, 0xd614f6a9,
-  0x78e8cfb2, 0xd5fd3848, 0x78e08dab, 0xd5e57b85, 0x78d846fb, 0xd5cdc062,
-  0x78cffba3, 0xd5b606e0,
-  0x78c7aba2, 0xd59e4eff, 0x78bf56f9, 0xd58698c0, 0x78b6fda8, 0xd56ee424,
-  0x78ae9fb0, 0xd557312d,
-  0x78a63d11, 0xd53f7fda, 0x789dd5cb, 0xd527d02e, 0x789569df, 0xd5102228,
-  0x788cf94c, 0xd4f875ca,
-  0x78848414, 0xd4e0cb15, 0x787c0a36, 0xd4c92209, 0x78738bb3, 0xd4b17aa8,
-  0x786b088c, 0xd499d4f2,
-  0x786280bf, 0xd48230e9, 0x7859f44f, 0xd46a8e8d, 0x7851633b, 0xd452eddf,
-  0x7848cd83, 0xd43b4ee0,
-  0x78403329, 0xd423b191, 0x7837942b, 0xd40c15f3, 0x782ef08b, 0xd3f47c06,
-  0x78264849, 0xd3dce3cd,
-  0x781d9b65, 0xd3c54d47, 0x7814e9df, 0xd3adb876, 0x780c33b8, 0xd396255a,
-  0x780378f1, 0xd37e93f4,
-  0x77fab989, 0xd3670446, 0x77f1f581, 0xd34f764f, 0x77e92cd9, 0xd337ea12,
-  0x77e05f91, 0xd3205f8f,
-  0x77d78daa, 0xd308d6c7, 0x77ceb725, 0xd2f14fba, 0x77c5dc01, 0xd2d9ca6a,
-  0x77bcfc3f, 0xd2c246d8,
-  0x77b417df, 0xd2aac504, 0x77ab2ee2, 0xd29344f0, 0x77a24148, 0xd27bc69c,
-  0x77994f11, 0xd2644a0a,
-  0x7790583e, 0xd24ccf39, 0x77875cce, 0xd235562b, 0x777e5cc3, 0xd21ddee2,
-  0x7775581d, 0xd206695d,
-  0x776c4edb, 0xd1eef59e, 0x776340ff, 0xd1d783a6, 0x775a2e89, 0xd1c01375,
-  0x77511778, 0xd1a8a50d,
-  0x7747fbce, 0xd191386e, 0x773edb8b, 0xd179cd99, 0x7735b6af, 0xd1626490,
-  0x772c8d3a, 0xd14afd52,
-  0x77235f2d, 0xd13397e2, 0x771a2c88, 0xd11c343f, 0x7710f54c, 0xd104d26b,
-  0x7707b979, 0xd0ed7267,
-  0x76fe790e, 0xd0d61434, 0x76f5340e, 0xd0beb7d2, 0x76ebea77, 0xd0a75d42,
-  0x76e29c4b, 0xd0900486,
-  0x76d94989, 0xd078ad9e, 0x76cff232, 0xd061588b, 0x76c69647, 0xd04a054e,
-  0x76bd35c7, 0xd032b3e7,
-  0x76b3d0b4, 0xd01b6459, 0x76aa670d, 0xd00416a3, 0x76a0f8d2, 0xcfeccac7,
-  0x76978605, 0xcfd580c6,
-  0x768e0ea6, 0xcfbe389f, 0x768492b4, 0xcfa6f255, 0x767b1231, 0xcf8fade9,
-  0x76718d1c, 0xcf786b5a,
-  0x76680376, 0xcf612aaa, 0x765e7540, 0xcf49ebda, 0x7654e279, 0xcf32aeeb,
-  0x764b4b23, 0xcf1b73de,
-  0x7641af3d, 0xcf043ab3, 0x76380ec8, 0xceed036b, 0x762e69c4, 0xced5ce08,
-  0x7624c031, 0xcebe9a8a,
-  0x761b1211, 0xcea768f2, 0x76115f63, 0xce903942, 0x7607a828, 0xce790b79,
-  0x75fdec60, 0xce61df99,
-  0x75f42c0b, 0xce4ab5a2, 0x75ea672a, 0xce338d97, 0x75e09dbd, 0xce1c6777,
-  0x75d6cfc5, 0xce054343,
-  0x75ccfd42, 0xcdee20fc, 0x75c32634, 0xcdd700a4, 0x75b94a9c, 0xcdbfe23a,
-  0x75af6a7b, 0xcda8c5c1,
-  0x75a585cf, 0xcd91ab39, 0x759b9c9b, 0xcd7a92a2, 0x7591aedd, 0xcd637bfe,
-  0x7587bc98, 0xcd4c674d,
-  0x757dc5ca, 0xcd355491, 0x7573ca75, 0xcd1e43ca, 0x7569ca99, 0xcd0734f9,
-  0x755fc635, 0xccf0281f,
-  0x7555bd4c, 0xccd91d3d, 0x754bafdc, 0xccc21455, 0x75419de7, 0xccab0d65,
-  0x7537876c, 0xcc940871,
-  0x752d6c6c, 0xcc7d0578, 0x75234ce8, 0xcc66047b, 0x751928e0, 0xcc4f057c,
-  0x750f0054, 0xcc38087b,
-  0x7504d345, 0xcc210d79, 0x74faa1b3, 0xcc0a1477, 0x74f06b9e, 0xcbf31d75,
-  0x74e63108, 0xcbdc2876,
-  0x74dbf1ef, 0xcbc53579, 0x74d1ae55, 0xcbae447f, 0x74c7663a, 0xcb97558a,
-  0x74bd199f, 0xcb80689a,
-  0x74b2c884, 0xcb697db0, 0x74a872e8, 0xcb5294ce, 0x749e18cd, 0xcb3badf3,
-  0x7493ba34, 0xcb24c921,
-  0x7489571c, 0xcb0de658, 0x747eef85, 0xcaf7059a, 0x74748371, 0xcae026e8,
-  0x746a12df, 0xcac94a42,
-  0x745f9dd1, 0xcab26fa9, 0x74552446, 0xca9b971e, 0x744aa63f, 0xca84c0a3,
-  0x744023bc, 0xca6dec37,
-  0x74359cbd, 0xca5719db, 0x742b1144, 0xca404992, 0x74208150, 0xca297b5a,
-  0x7415ece2, 0xca12af37,
-  0x740b53fb, 0xc9fbe527, 0x7400b69a, 0xc9e51d2d, 0x73f614c0, 0xc9ce5748,
-  0x73eb6e6e, 0xc9b7937a,
-  0x73e0c3a3, 0xc9a0d1c5, 0x73d61461, 0xc98a1227, 0x73cb60a8, 0xc97354a4,
-  0x73c0a878, 0xc95c993a,
-  0x73b5ebd1, 0xc945dfec, 0x73ab2ab4, 0xc92f28ba, 0x73a06522, 0xc91873a5,
-  0x73959b1b, 0xc901c0ae,
-  0x738acc9e, 0xc8eb0fd6, 0x737ff9ae, 0xc8d4611d, 0x73752249, 0xc8bdb485,
-  0x736a4671, 0xc8a70a0e,
-  0x735f6626, 0xc89061ba, 0x73548168, 0xc879bb89, 0x73499838, 0xc863177b,
-  0x733eaa96, 0xc84c7593,
-  0x7333b883, 0xc835d5d0, 0x7328c1ff, 0xc81f3834, 0x731dc70a, 0xc8089cbf,
-  0x7312c7a5, 0xc7f20373,
-  0x7307c3d0, 0xc7db6c50, 0x72fcbb8c, 0xc7c4d757, 0x72f1aed9, 0xc7ae4489,
-  0x72e69db7, 0xc797b3e7,
-  0x72db8828, 0xc7812572, 0x72d06e2b, 0xc76a992a, 0x72c54fc1, 0xc7540f11,
-  0x72ba2cea, 0xc73d8727,
-  0x72af05a7, 0xc727016d, 0x72a3d9f7, 0xc7107de4, 0x7298a9dd, 0xc6f9fc8d,
-  0x728d7557, 0xc6e37d69,
-  0x72823c67, 0xc6cd0079, 0x7276ff0d, 0xc6b685bd, 0x726bbd48, 0xc6a00d37,
-  0x7260771b, 0xc68996e7,
-  0x72552c85, 0xc67322ce, 0x7249dd86, 0xc65cb0ed, 0x723e8a20, 0xc6464144,
-  0x72333251, 0xc62fd3d6,
-  0x7227d61c, 0xc61968a2, 0x721c7580, 0xc602ffaa, 0x7211107e, 0xc5ec98ee,
-  0x7205a716, 0xc5d6346f,
-  0x71fa3949, 0xc5bfd22e, 0x71eec716, 0xc5a9722c, 0x71e35080, 0xc593146a,
-  0x71d7d585, 0xc57cb8e9,
-  0x71cc5626, 0xc5665fa9, 0x71c0d265, 0xc55008ab, 0x71b54a41, 0xc539b3f1,
-  0x71a9bdba, 0xc523617a,
-  0x719e2cd2, 0xc50d1149, 0x71929789, 0xc4f6c35d, 0x7186fdde, 0xc4e077b8,
-  0x717b5fd3, 0xc4ca2e5b,
-  0x716fbd68, 0xc4b3e746, 0x7164169d, 0xc49da27a, 0x71586b74, 0xc4875ff9,
-  0x714cbbeb, 0xc4711fc2,
-  0x71410805, 0xc45ae1d7, 0x71354fc0, 0xc444a639, 0x7129931f, 0xc42e6ce8,
-  0x711dd220, 0xc41835e6,
-  0x71120cc5, 0xc4020133, 0x7106430e, 0xc3ebced0, 0x70fa74fc, 0xc3d59ebe,
-  0x70eea28e, 0xc3bf70fd,
-  0x70e2cbc6, 0xc3a94590, 0x70d6f0a4, 0xc3931c76, 0x70cb1128, 0xc37cf5b0,
-  0x70bf2d53, 0xc366d140,
-  0x70b34525, 0xc350af26, 0x70a7589f, 0xc33a8f62, 0x709b67c0, 0xc32471f7,
-  0x708f728b, 0xc30e56e4,
-  0x708378ff, 0xc2f83e2a, 0x70777b1c, 0xc2e227cb, 0x706b78e3, 0xc2cc13c7,
-  0x705f7255, 0xc2b6021f,
-  0x70536771, 0xc29ff2d4, 0x70475839, 0xc289e5e7, 0x703b44ad, 0xc273db58,
-  0x702f2ccd, 0xc25dd329,
-  0x7023109a, 0xc247cd5a, 0x7016f014, 0xc231c9ec, 0x700acb3c, 0xc21bc8e1,
-  0x6ffea212, 0xc205ca38,
-  0x6ff27497, 0xc1efcdf3, 0x6fe642ca, 0xc1d9d412, 0x6fda0cae, 0xc1c3dc97,
-  0x6fcdd241, 0xc1ade781,
-  0x6fc19385, 0xc197f4d4, 0x6fb5507a, 0xc182048d, 0x6fa90921, 0xc16c16b0,
-  0x6f9cbd79, 0xc1562b3d,
-  0x6f906d84, 0xc1404233, 0x6f841942, 0xc12a5b95, 0x6f77c0b3, 0xc1147764,
-  0x6f6b63d8, 0xc0fe959f,
-  0x6f5f02b2, 0xc0e8b648, 0x6f529d40, 0xc0d2d960, 0x6f463383, 0xc0bcfee7,
-  0x6f39c57d, 0xc0a726df,
-  0x6f2d532c, 0xc0915148, 0x6f20dc92, 0xc07b7e23, 0x6f1461b0, 0xc065ad70,
-  0x6f07e285, 0xc04fdf32,
-  0x6efb5f12, 0xc03a1368, 0x6eeed758, 0xc0244a14, 0x6ee24b57, 0xc00e8336,
-  0x6ed5bb10, 0xbff8bece,
-  0x6ec92683, 0xbfe2fcdf, 0x6ebc8db0, 0xbfcd3d69, 0x6eaff099, 0xbfb7806c,
-  0x6ea34f3d, 0xbfa1c5ea,
-  0x6e96a99d, 0xbf8c0de3, 0x6e89ffb9, 0xbf765858, 0x6e7d5193, 0xbf60a54a,
-  0x6e709f2a, 0xbf4af4ba,
-  0x6e63e87f, 0xbf3546a8, 0x6e572d93, 0xbf1f9b16, 0x6e4a6e66, 0xbf09f205,
-  0x6e3daaf8, 0xbef44b74,
-  0x6e30e34a, 0xbedea765, 0x6e24175c, 0xbec905d9, 0x6e174730, 0xbeb366d1,
-  0x6e0a72c5, 0xbe9dca4e,
-  0x6dfd9a1c, 0xbe88304f, 0x6df0bd35, 0xbe7298d7, 0x6de3dc11, 0xbe5d03e6,
-  0x6dd6f6b1, 0xbe47717c,
-  0x6dca0d14, 0xbe31e19b, 0x6dbd1f3c, 0xbe1c5444, 0x6db02d29, 0xbe06c977,
-  0x6da336dc, 0xbdf14135,
-  0x6d963c54, 0xbddbbb7f, 0x6d893d93, 0xbdc63856, 0x6d7c3a98, 0xbdb0b7bb,
-  0x6d6f3365, 0xbd9b39ad,
-  0x6d6227fa, 0xbd85be30, 0x6d551858, 0xbd704542, 0x6d48047e, 0xbd5acee5,
-  0x6d3aec6e, 0xbd455b1a,
-  0x6d2dd027, 0xbd2fe9e2, 0x6d20afac, 0xbd1a7b3d, 0x6d138afb, 0xbd050f2c,
-  0x6d066215, 0xbcefa5b0,
-  0x6cf934fc, 0xbcda3ecb, 0x6cec03af, 0xbcc4da7b, 0x6cdece2f, 0xbcaf78c4,
-  0x6cd1947c, 0xbc9a19a5,
-  0x6cc45698, 0xbc84bd1f, 0x6cb71482, 0xbc6f6333, 0x6ca9ce3b, 0xbc5a0be2,
-  0x6c9c83c3, 0xbc44b72c,
-  0x6c8f351c, 0xbc2f6513, 0x6c81e245, 0xbc1a1598, 0x6c748b3f, 0xbc04c8ba,
-  0x6c67300b, 0xbbef7e7c,
-  0x6c59d0a9, 0xbbda36dd, 0x6c4c6d1a, 0xbbc4f1df, 0x6c3f055d, 0xbbafaf82,
-  0x6c319975, 0xbb9a6fc7,
-  0x6c242960, 0xbb8532b0, 0x6c16b521, 0xbb6ff83c, 0x6c093cb6, 0xbb5ac06d,
-  0x6bfbc021, 0xbb458b43,
-  0x6bee3f62, 0xbb3058c0, 0x6be0ba7b, 0xbb1b28e4, 0x6bd3316a, 0xbb05fbb0,
-  0x6bc5a431, 0xbaf0d125,
-  0x6bb812d1, 0xbadba943, 0x6baa7d49, 0xbac6840c, 0x6b9ce39b, 0xbab16180,
-  0x6b8f45c7, 0xba9c41a0,
-  0x6b81a3cd, 0xba87246d, 0x6b73fdae, 0xba7209e7, 0x6b66536b, 0xba5cf210,
-  0x6b58a503, 0xba47dce8,
-  0x6b4af279, 0xba32ca71, 0x6b3d3bcb, 0xba1dbaaa, 0x6b2f80fb, 0xba08ad95,
-  0x6b21c208, 0xb9f3a332,
-  0x6b13fef5, 0xb9de9b83, 0x6b0637c1, 0xb9c99688, 0x6af86c6c, 0xb9b49442,
-  0x6aea9cf8, 0xb99f94b2,
-  0x6adcc964, 0xb98a97d8, 0x6acef1b2, 0xb9759db6, 0x6ac115e2, 0xb960a64c,
-  0x6ab335f4, 0xb94bb19b,
-  0x6aa551e9, 0xb936bfa4, 0x6a9769c1, 0xb921d067, 0x6a897d7d, 0xb90ce3e6,
-  0x6a7b8d1e, 0xb8f7fa21,
-  0x6a6d98a4, 0xb8e31319, 0x6a5fa010, 0xb8ce2ecf, 0x6a51a361, 0xb8b94d44,
-  0x6a43a29a, 0xb8a46e78,
-  0x6a359db9, 0xb88f926d, 0x6a2794c1, 0xb87ab922, 0x6a1987b0, 0xb865e299,
-  0x6a0b7689, 0xb8510ed4,
-  0x69fd614a, 0xb83c3dd1, 0x69ef47f6, 0xb8276f93, 0x69e12a8c, 0xb812a41a,
-  0x69d3090e, 0xb7fddb67,
-  0x69c4e37a, 0xb7e9157a, 0x69b6b9d3, 0xb7d45255, 0x69a88c19, 0xb7bf91f8,
-  0x699a5a4c, 0xb7aad465,
-  0x698c246c, 0xb796199b, 0x697dea7b, 0xb781619c, 0x696fac78, 0xb76cac69,
-  0x69616a65, 0xb757fa01,
-  0x69532442, 0xb7434a67, 0x6944da10, 0xb72e9d9b, 0x69368bce, 0xb719f39e,
-  0x6928397e, 0xb7054c6f,
-  0x6919e320, 0xb6f0a812, 0x690b88b5, 0xb6dc0685, 0x68fd2a3d, 0xb6c767ca,
-  0x68eec7b9, 0xb6b2cbe2,
-  0x68e06129, 0xb69e32cd, 0x68d1f68f, 0xb6899c8d, 0x68c387e9, 0xb6750921,
-  0x68b5153a, 0xb660788c,
-  0x68a69e81, 0xb64beacd, 0x689823bf, 0xb6375fe5, 0x6889a4f6, 0xb622d7d6,
-  0x687b2224, 0xb60e529f,
-  0x686c9b4b, 0xb5f9d043, 0x685e106c, 0xb5e550c1, 0x684f8186, 0xb5d0d41a,
-  0x6840ee9b, 0xb5bc5a50,
-  0x683257ab, 0xb5a7e362, 0x6823bcb7, 0xb5936f53, 0x68151dbe, 0xb57efe22,
-  0x68067ac3, 0xb56a8fd0,
-  0x67f7d3c5, 0xb556245e, 0x67e928c5, 0xb541bbcd, 0x67da79c3, 0xb52d561e,
-  0x67cbc6c0, 0xb518f351,
-  0x67bd0fbd, 0xb5049368, 0x67ae54ba, 0xb4f03663, 0x679f95b7, 0xb4dbdc42,
-  0x6790d2b6, 0xb4c78507,
-  0x67820bb7, 0xb4b330b3, 0x677340ba, 0xb49edf45, 0x676471c0, 0xb48a90c0,
-  0x67559eca, 0xb4764523,
-  0x6746c7d8, 0xb461fc70, 0x6737ecea, 0xb44db6a8, 0x67290e02, 0xb43973ca,
-  0x671a2b20, 0xb42533d8,
-  0x670b4444, 0xb410f6d3, 0x66fc596f, 0xb3fcbcbb, 0x66ed6aa1, 0xb3e88592,
-  0x66de77dc, 0xb3d45157,
-  0x66cf8120, 0xb3c0200c, 0x66c0866d, 0xb3abf1b2, 0x66b187c3, 0xb397c649,
-  0x66a28524, 0xb3839dd3,
-  0x66937e91, 0xb36f784f, 0x66847408, 0xb35b55bf, 0x6675658c, 0xb3473623,
-  0x6666531d, 0xb333197c,
-  0x66573cbb, 0xb31effcc, 0x66482267, 0xb30ae912, 0x66390422, 0xb2f6d550,
-  0x6629e1ec, 0xb2e2c486,
-  0x661abbc5, 0xb2ceb6b5, 0x660b91af, 0xb2baabde, 0x65fc63a9, 0xb2a6a402,
-  0x65ed31b5, 0xb2929f21,
-  0x65ddfbd3, 0xb27e9d3c, 0x65cec204, 0xb26a9e54, 0x65bf8447, 0xb256a26a,
-  0x65b0429f, 0xb242a97e,
-  0x65a0fd0b, 0xb22eb392, 0x6591b38c, 0xb21ac0a6, 0x65826622, 0xb206d0ba,
-  0x657314cf, 0xb1f2e3d0,
-  0x6563bf92, 0xb1def9e9, 0x6554666d, 0xb1cb1304, 0x6545095f, 0xb1b72f23,
-  0x6535a86b, 0xb1a34e47,
-  0x6526438f, 0xb18f7071, 0x6516dacd, 0xb17b95a0, 0x65076e25, 0xb167bdd7,
-  0x64f7fd98, 0xb153e915,
-  0x64e88926, 0xb140175b, 0x64d910d1, 0xb12c48ab, 0x64c99498, 0xb1187d05,
-  0x64ba147d, 0xb104b46a,
-  0x64aa907f, 0xb0f0eeda, 0x649b08a0, 0xb0dd2c56, 0x648b7ce0, 0xb0c96ce0,
-  0x647bed3f, 0xb0b5b077,
-  0x646c59bf, 0xb0a1f71d, 0x645cc260, 0xb08e40d2, 0x644d2722, 0xb07a8d97,
-  0x643d8806, 0xb066dd6d,
-  0x642de50d, 0xb0533055, 0x641e3e38, 0xb03f864f, 0x640e9386, 0xb02bdf5c,
-  0x63fee4f8, 0xb0183b7d,
-  0x63ef3290, 0xb0049ab3, 0x63df7c4d, 0xaff0fcfe, 0x63cfc231, 0xafdd625f,
-  0x63c0043b, 0xafc9cad7,
-  0x63b0426d, 0xafb63667, 0x63a07cc7, 0xafa2a50f, 0x6390b34a, 0xaf8f16d1,
-  0x6380e5f6, 0xaf7b8bac,
-  0x637114cc, 0xaf6803a2, 0x63613fcd, 0xaf547eb3, 0x635166f9, 0xaf40fce1,
-  0x63418a50, 0xaf2d7e2b,
-  0x6331a9d4, 0xaf1a0293, 0x6321c585, 0xaf068a1a, 0x6311dd64, 0xaef314c0,
-  0x6301f171, 0xaedfa285,
-  0x62f201ac, 0xaecc336c, 0x62e20e17, 0xaeb8c774, 0x62d216b3, 0xaea55e9e,
-  0x62c21b7e, 0xae91f8eb,
-  0x62b21c7b, 0xae7e965b, 0x62a219aa, 0xae6b36f0, 0x6292130c, 0xae57daab,
-  0x628208a1, 0xae44818b,
-  0x6271fa69, 0xae312b92, 0x6261e866, 0xae1dd8c0, 0x6251d298, 0xae0a8916,
-  0x6241b8ff, 0xadf73c96,
-  0x62319b9d, 0xade3f33e, 0x62217a72, 0xadd0ad12, 0x6211557e, 0xadbd6a10,
-  0x62012cc2, 0xadaa2a3b,
-  0x61f1003f, 0xad96ed92, 0x61e0cff5, 0xad83b416, 0x61d09be5, 0xad707dc8,
-  0x61c06410, 0xad5d4aaa,
-  0x61b02876, 0xad4a1aba, 0x619fe918, 0xad36edfc, 0x618fa5f7, 0xad23c46e,
-  0x617f5f12, 0xad109e12,
-  0x616f146c, 0xacfd7ae8, 0x615ec603, 0xacea5af2, 0x614e73da, 0xacd73e30,
-  0x613e1df0, 0xacc424a3,
-  0x612dc447, 0xacb10e4b, 0x611d66de, 0xac9dfb29, 0x610d05b7, 0xac8aeb3e,
-  0x60fca0d2, 0xac77de8b,
-  0x60ec3830, 0xac64d510, 0x60dbcbd1, 0xac51cecf, 0x60cb5bb7, 0xac3ecbc7,
-  0x60bae7e1, 0xac2bcbfa,
-  0x60aa7050, 0xac18cf69, 0x6099f505, 0xac05d613, 0x60897601, 0xabf2dffb,
-  0x6078f344, 0xabdfed1f,
-  0x60686ccf, 0xabccfd83, 0x6057e2a2, 0xabba1125, 0x604754bf, 0xaba72807,
-  0x6036c325, 0xab944229,
-  0x60262dd6, 0xab815f8d, 0x601594d1, 0xab6e8032, 0x6004f819, 0xab5ba41a,
-  0x5ff457ad, 0xab48cb46,
-  0x5fe3b38d, 0xab35f5b5, 0x5fd30bbc, 0xab23236a, 0x5fc26038, 0xab105464,
-  0x5fb1b104, 0xaafd88a4,
-  0x5fa0fe1f, 0xaaeac02c, 0x5f90478a, 0xaad7fafb, 0x5f7f8d46, 0xaac53912,
-  0x5f6ecf53, 0xaab27a73,
-  0x5f5e0db3, 0xaa9fbf1e, 0x5f4d4865, 0xaa8d0713, 0x5f3c7f6b, 0xaa7a5253,
-  0x5f2bb2c5, 0xaa67a0e0,
-  0x5f1ae274, 0xaa54f2ba, 0x5f0a0e77, 0xaa4247e1, 0x5ef936d1, 0xaa2fa056,
-  0x5ee85b82, 0xaa1cfc1a,
-  0x5ed77c8a, 0xaa0a5b2e, 0x5ec699e9, 0xa9f7bd92, 0x5eb5b3a2, 0xa9e52347,
-  0x5ea4c9b3, 0xa9d28c4e,
-  0x5e93dc1f, 0xa9bff8a8, 0x5e82eae5, 0xa9ad6855, 0x5e71f606, 0xa99adb56,
-  0x5e60fd84, 0xa98851ac,
-  0x5e50015d, 0xa975cb57, 0x5e3f0194, 0xa9634858, 0x5e2dfe29, 0xa950c8b0,
-  0x5e1cf71c, 0xa93e4c5f,
-  0x5e0bec6e, 0xa92bd367, 0x5dfade20, 0xa9195dc7, 0x5de9cc33, 0xa906eb82,
-  0x5dd8b6a7, 0xa8f47c97,
-  0x5dc79d7c, 0xa8e21106, 0x5db680b4, 0xa8cfa8d2, 0x5da5604f, 0xa8bd43fa,
-  0x5d943c4e, 0xa8aae280,
-  0x5d8314b1, 0xa8988463, 0x5d71e979, 0xa88629a5, 0x5d60baa7, 0xa873d246,
-  0x5d4f883b, 0xa8617e48,
-  0x5d3e5237, 0xa84f2daa, 0x5d2d189a, 0xa83ce06e, 0x5d1bdb65, 0xa82a9693,
-  0x5d0a9a9a, 0xa818501c,
-  0x5cf95638, 0xa8060d08, 0x5ce80e41, 0xa7f3cd59, 0x5cd6c2b5, 0xa7e1910f,
-  0x5cc57394, 0xa7cf582a,
-  0x5cb420e0, 0xa7bd22ac, 0x5ca2ca99, 0xa7aaf094, 0x5c9170bf, 0xa798c1e5,
-  0x5c801354, 0xa786969e,
-  0x5c6eb258, 0xa7746ec0, 0x5c5d4dcc, 0xa7624a4d, 0x5c4be5b0, 0xa7502943,
-  0x5c3a7a05, 0xa73e0ba5,
-  0x5c290acc, 0xa72bf174, 0x5c179806, 0xa719daae, 0x5c0621b2, 0xa707c757,
-  0x5bf4a7d2, 0xa6f5b76d,
-  0x5be32a67, 0xa6e3aaf2, 0x5bd1a971, 0xa6d1a1e7, 0x5bc024f0, 0xa6bf9c4b,
-  0x5bae9ce7, 0xa6ad9a21,
-  0x5b9d1154, 0xa69b9b68, 0x5b8b8239, 0xa689a022, 0x5b79ef96, 0xa677a84e,
-  0x5b68596d, 0xa665b3ee,
-  0x5b56bfbd, 0xa653c303, 0x5b452288, 0xa641d58c, 0x5b3381ce, 0xa62feb8b,
-  0x5b21dd90, 0xa61e0501,
-  0x5b1035cf, 0xa60c21ee, 0x5afe8a8b, 0xa5fa4252, 0x5aecdbc5, 0xa5e8662f,
-  0x5adb297d, 0xa5d68d85,
-  0x5ac973b5, 0xa5c4b855, 0x5ab7ba6c, 0xa5b2e6a0, 0x5aa5fda5, 0xa5a11866,
-  0x5a943d5e, 0xa58f4da8,
-  0x5a82799a, 0xa57d8666, 0x5a70b258, 0xa56bc2a2, 0x5a5ee79a, 0xa55a025b,
-  0x5a4d1960, 0xa5484594,
-  0x5a3b47ab, 0xa5368c4b, 0x5a29727b, 0xa524d683, 0x5a1799d1, 0xa513243b,
-  0x5a05bdae, 0xa5017575,
-  0x59f3de12, 0xa4efca31, 0x59e1faff, 0xa4de2270, 0x59d01475, 0xa4cc7e32,
-  0x59be2a74, 0xa4badd78,
-  0x59ac3cfd, 0xa4a94043, 0x599a4c12, 0xa497a693, 0x598857b2, 0xa486106a,
-  0x59765fde, 0xa4747dc7,
-  0x59646498, 0xa462eeac, 0x595265df, 0xa4516319, 0x594063b5, 0xa43fdb10,
-  0x592e5e19, 0xa42e568f,
-  0x591c550e, 0xa41cd599, 0x590a4893, 0xa40b582e, 0x58f838a9, 0xa3f9de4e,
-  0x58e62552, 0xa3e867fa,
-  0x58d40e8c, 0xa3d6f534, 0x58c1f45b, 0xa3c585fb, 0x58afd6bd, 0xa3b41a50,
-  0x589db5b3, 0xa3a2b234,
-  0x588b9140, 0xa3914da8, 0x58796962, 0xa37fecac, 0x58673e1b, 0xa36e8f41,
-  0x58550f6c, 0xa35d3567,
-  0x5842dd54, 0xa34bdf20, 0x5830a7d6, 0xa33a8c6c, 0x581e6ef1, 0xa3293d4b,
-  0x580c32a7, 0xa317f1bf,
-  0x57f9f2f8, 0xa306a9c8, 0x57e7afe4, 0xa2f56566, 0x57d5696d, 0xa2e4249b,
-  0x57c31f92, 0xa2d2e766,
-  0x57b0d256, 0xa2c1adc9, 0x579e81b8, 0xa2b077c5, 0x578c2dba, 0xa29f4559,
-  0x5779d65b, 0xa28e1687,
-  0x57677b9d, 0xa27ceb4f, 0x57551d80, 0xa26bc3b2, 0x5742bc06, 0xa25a9fb1,
-  0x5730572e, 0xa2497f4c,
-  0x571deefa, 0xa2386284, 0x570b8369, 0xa2274959, 0x56f9147e, 0xa21633cd,
-  0x56e6a239, 0xa20521e0,
-  0x56d42c99, 0xa1f41392, 0x56c1b3a1, 0xa1e308e4, 0x56af3750, 0xa1d201d7,
-  0x569cb7a8, 0xa1c0fe6c,
-  0x568a34a9, 0xa1affea3, 0x5677ae54, 0xa19f027c, 0x566524aa, 0xa18e09fa,
-  0x565297ab, 0xa17d151b,
-  0x56400758, 0xa16c23e1, 0x562d73b2, 0xa15b364d, 0x561adcb9, 0xa14a4c5e,
-  0x5608426e, 0xa1396617,
-  0x55f5a4d2, 0xa1288376, 0x55e303e6, 0xa117a47e, 0x55d05faa, 0xa106c92f,
-  0x55bdb81f, 0xa0f5f189,
-  0x55ab0d46, 0xa0e51d8c, 0x55985f20, 0xa0d44d3b, 0x5585adad, 0xa0c38095,
-  0x5572f8ed, 0xa0b2b79b,
-  0x556040e2, 0xa0a1f24d, 0x554d858d, 0xa09130ad, 0x553ac6ee, 0xa08072ba,
-  0x55280505, 0xa06fb876,
-  0x55153fd4, 0xa05f01e1, 0x5502775c, 0xa04e4efc, 0x54efab9c, 0xa03d9fc8,
-  0x54dcdc96, 0xa02cf444,
-  0x54ca0a4b, 0xa01c4c73, 0x54b734ba, 0xa00ba853, 0x54a45be6, 0x9ffb07e7,
-  0x54917fce, 0x9fea6b2f,
-  0x547ea073, 0x9fd9d22a, 0x546bbdd7, 0x9fc93cdb, 0x5458d7f9, 0x9fb8ab41,
-  0x5445eedb, 0x9fa81d5e,
-  0x5433027d, 0x9f979331, 0x542012e1, 0x9f870cbc, 0x540d2005, 0x9f7689ff,
-  0x53fa29ed, 0x9f660afb,
-  0x53e73097, 0x9f558fb0, 0x53d43406, 0x9f45181f, 0x53c13439, 0x9f34a449,
-  0x53ae3131, 0x9f24342f,
-  0x539b2af0, 0x9f13c7d0, 0x53882175, 0x9f035f2e, 0x537514c2, 0x9ef2fa49,
-  0x536204d7, 0x9ee29922,
-  0x534ef1b5, 0x9ed23bb9, 0x533bdb5d, 0x9ec1e210, 0x5328c1d0, 0x9eb18c26,
-  0x5315a50e, 0x9ea139fd,
-  0x53028518, 0x9e90eb94, 0x52ef61ee, 0x9e80a0ee, 0x52dc3b92, 0x9e705a09,
-  0x52c91204, 0x9e6016e8,
-  0x52b5e546, 0x9e4fd78a, 0x52a2b556, 0x9e3f9bf0, 0x528f8238, 0x9e2f641b,
-  0x527c4bea, 0x9e1f300b,
-  0x5269126e, 0x9e0effc1, 0x5255d5c5, 0x9dfed33e, 0x524295f0, 0x9deeaa82,
-  0x522f52ee, 0x9dde858e,
-  0x521c0cc2, 0x9dce6463, 0x5208c36a, 0x9dbe4701, 0x51f576ea, 0x9dae2d68,
-  0x51e22740, 0x9d9e179a,
-  0x51ced46e, 0x9d8e0597, 0x51bb7e75, 0x9d7df75f, 0x51a82555, 0x9d6decf4,
-  0x5194c910, 0x9d5de656,
-  0x518169a5, 0x9d4de385, 0x516e0715, 0x9d3de482, 0x515aa162, 0x9d2de94d,
-  0x5147388c, 0x9d1df1e9,
-  0x5133cc94, 0x9d0dfe54, 0x51205d7b, 0x9cfe0e8f, 0x510ceb40, 0x9cee229c,
-  0x50f975e6, 0x9cde3a7b,
-  0x50e5fd6d, 0x9cce562c, 0x50d281d5, 0x9cbe75b0, 0x50bf031f, 0x9cae9907,
-  0x50ab814d, 0x9c9ec033,
-  0x5097fc5e, 0x9c8eeb34, 0x50847454, 0x9c7f1a0a, 0x5070e92f, 0x9c6f4cb6,
-  0x505d5af1, 0x9c5f8339,
-  0x5049c999, 0x9c4fbd93, 0x50363529, 0x9c3ffbc5, 0x50229da1, 0x9c303dcf,
-  0x500f0302, 0x9c2083b3,
-  0x4ffb654d, 0x9c10cd70, 0x4fe7c483, 0x9c011b08, 0x4fd420a4, 0x9bf16c7a,
-  0x4fc079b1, 0x9be1c1c8,
-  0x4faccfab, 0x9bd21af3, 0x4f992293, 0x9bc277fa, 0x4f857269, 0x9bb2d8de,
-  0x4f71bf2e, 0x9ba33da0,
-  0x4f5e08e3, 0x9b93a641, 0x4f4a4f89, 0x9b8412c1, 0x4f369320, 0x9b748320,
-  0x4f22d3aa, 0x9b64f760,
-  0x4f0f1126, 0x9b556f81, 0x4efb4b96, 0x9b45eb83, 0x4ee782fb, 0x9b366b68,
-  0x4ed3b755, 0x9b26ef2f,
-  0x4ebfe8a5, 0x9b1776da, 0x4eac16eb, 0x9b080268, 0x4e984229, 0x9af891db,
-  0x4e846a60, 0x9ae92533,
-  0x4e708f8f, 0x9ad9bc71, 0x4e5cb1b9, 0x9aca5795, 0x4e48d0dd, 0x9abaf6a1,
-  0x4e34ecfc, 0x9aab9993,
-  0x4e210617, 0x9a9c406e, 0x4e0d1c30, 0x9a8ceb31, 0x4df92f46, 0x9a7d99de,
-  0x4de53f5a, 0x9a6e4c74,
-  0x4dd14c6e, 0x9a5f02f5, 0x4dbd5682, 0x9a4fbd61, 0x4da95d96, 0x9a407bb9,
-  0x4d9561ac, 0x9a313dfc,
-  0x4d8162c4, 0x9a22042d, 0x4d6d60df, 0x9a12ce4b, 0x4d595bfe, 0x9a039c57,
-  0x4d455422, 0x99f46e51,
-  0x4d31494b, 0x99e5443b, 0x4d1d3b7a, 0x99d61e14, 0x4d092ab0, 0x99c6fbde,
-  0x4cf516ee, 0x99b7dd99,
-  0x4ce10034, 0x99a8c345, 0x4ccce684, 0x9999ace3, 0x4cb8c9dd, 0x998a9a74,
-  0x4ca4aa41, 0x997b8bf8,
-  0x4c9087b1, 0x996c816f, 0x4c7c622d, 0x995d7adc, 0x4c6839b7, 0x994e783d,
-  0x4c540e4e, 0x993f7993,
-  0x4c3fdff4, 0x99307ee0, 0x4c2baea9, 0x99218824, 0x4c177a6e, 0x9912955f,
-  0x4c034345, 0x9903a691,
-  0x4bef092d, 0x98f4bbbc, 0x4bdacc28, 0x98e5d4e0, 0x4bc68c36, 0x98d6f1fe,
-  0x4bb24958, 0x98c81316,
-  0x4b9e0390, 0x98b93828, 0x4b89badd, 0x98aa6136, 0x4b756f40, 0x989b8e40,
-  0x4b6120bb, 0x988cbf46,
-  0x4b4ccf4d, 0x987df449, 0x4b387af9, 0x986f2d4a, 0x4b2423be, 0x98606a49,
-  0x4b0fc99d, 0x9851ab46,
-  0x4afb6c98, 0x9842f043, 0x4ae70caf, 0x98343940, 0x4ad2a9e2, 0x9825863d,
-  0x4abe4433, 0x9816d73b,
-  0x4aa9dba2, 0x98082c3b, 0x4a957030, 0x97f9853d, 0x4a8101de, 0x97eae242,
-  0x4a6c90ad, 0x97dc4349,
-  0x4a581c9e, 0x97cda855, 0x4a43a5b0, 0x97bf1165, 0x4a2f2be6, 0x97b07e7a,
-  0x4a1aaf3f, 0x97a1ef94,
-  0x4a062fbd, 0x979364b5, 0x49f1ad61, 0x9784dddc, 0x49dd282a, 0x97765b0a,
-  0x49c8a01b, 0x9767dc41,
-  0x49b41533, 0x9759617f, 0x499f8774, 0x974aeac6, 0x498af6df, 0x973c7817,
-  0x49766373, 0x972e0971,
-  0x4961cd33, 0x971f9ed7, 0x494d341e, 0x97113847, 0x49389836, 0x9702d5c3,
-  0x4923f97b, 0x96f4774b,
-  0x490f57ee, 0x96e61ce0, 0x48fab391, 0x96d7c682, 0x48e60c62, 0x96c97432,
-  0x48d16265, 0x96bb25f0,
-  0x48bcb599, 0x96acdbbe, 0x48a805ff, 0x969e959b, 0x48935397, 0x96905388,
-  0x487e9e64, 0x96821585,
-  0x4869e665, 0x9673db94, 0x48552b9b, 0x9665a5b4, 0x48406e08, 0x965773e7,
-  0x482badab, 0x9649462d,
-  0x4816ea86, 0x963b1c86, 0x48022499, 0x962cf6f2, 0x47ed5be6, 0x961ed574,
-  0x47d8906d, 0x9610b80a,
-  0x47c3c22f, 0x96029eb6, 0x47aef12c, 0x95f48977, 0x479a1d67, 0x95e67850,
-  0x478546de, 0x95d86b3f,
-  0x47706d93, 0x95ca6247, 0x475b9188, 0x95bc5d66, 0x4746b2bc, 0x95ae5c9f,
-  0x4731d131, 0x95a05ff0,
-  0x471cece7, 0x9592675c, 0x470805df, 0x958472e2, 0x46f31c1a, 0x95768283,
-  0x46de2f99, 0x9568963f,
-  0x46c9405c, 0x955aae17, 0x46b44e65, 0x954cca0c, 0x469f59b4, 0x953eea1e,
-  0x468a624a, 0x95310e4e,
-  0x46756828, 0x9523369c, 0x46606b4e, 0x95156308, 0x464b6bbe, 0x95079394,
-  0x46366978, 0x94f9c83f,
-  0x4621647d, 0x94ec010b, 0x460c5cce, 0x94de3df8, 0x45f7526b, 0x94d07f05,
-  0x45e24556, 0x94c2c435,
-  0x45cd358f, 0x94b50d87, 0x45b82318, 0x94a75afd, 0x45a30df0, 0x9499ac95,
-  0x458df619, 0x948c0252,
-  0x4578db93, 0x947e5c33, 0x4563be60, 0x9470ba39, 0x454e9e80, 0x94631c65,
-  0x45397bf4, 0x945582b7,
-  0x452456bd, 0x9447ed2f, 0x450f2edb, 0x943a5bcf, 0x44fa0450, 0x942cce96,
-  0x44e4d71c, 0x941f4585,
-  0x44cfa740, 0x9411c09e, 0x44ba74bd, 0x94043fdf, 0x44a53f93, 0x93f6c34a,
-  0x449007c4, 0x93e94adf,
-  0x447acd50, 0x93dbd6a0, 0x44659039, 0x93ce668b, 0x4450507e, 0x93c0faa3,
-  0x443b0e21, 0x93b392e6,
-  0x4425c923, 0x93a62f57, 0x44108184, 0x9398cff5, 0x43fb3746, 0x938b74c1,
-  0x43e5ea68, 0x937e1dbb,
-  0x43d09aed, 0x9370cae4, 0x43bb48d4, 0x93637c3d, 0x43a5f41e, 0x935631c5,
-  0x43909ccd, 0x9348eb7e,
-  0x437b42e1, 0x933ba968, 0x4365e65b, 0x932e6b84, 0x4350873c, 0x932131d1,
-  0x433b2585, 0x9313fc51,
-  0x4325c135, 0x9306cb04, 0x43105a50, 0x92f99deb, 0x42faf0d4, 0x92ec7505,
-  0x42e584c3, 0x92df5054,
-  0x42d0161e, 0x92d22fd9, 0x42baa4e6, 0x92c51392, 0x42a5311b, 0x92b7fb82,
-  0x428fbabe, 0x92aae7a8,
-  0x427a41d0, 0x929dd806, 0x4264c653, 0x9290cc9b, 0x424f4845, 0x9283c568,
-  0x4239c7aa, 0x9276c26d,
-  0x42244481, 0x9269c3ac, 0x420ebecb, 0x925cc924, 0x41f93689, 0x924fd2d7,
-  0x41e3abbc, 0x9242e0c4,
-  0x41ce1e65, 0x9235f2ec, 0x41b88e84, 0x9229094f, 0x41a2fc1a, 0x921c23ef,
-  0x418d6729, 0x920f42cb,
-  0x4177cfb1, 0x920265e4, 0x416235b2, 0x91f58d3b, 0x414c992f, 0x91e8b8d0,
-  0x4136fa27, 0x91dbe8a4,
-  0x4121589b, 0x91cf1cb6, 0x410bb48c, 0x91c25508, 0x40f60dfb, 0x91b5919a,
-  0x40e064ea, 0x91a8d26d,
-  0x40cab958, 0x919c1781, 0x40b50b46, 0x918f60d6, 0x409f5ab6, 0x9182ae6d,
-  0x4089a7a8, 0x91760047,
-  0x4073f21d, 0x91695663, 0x405e3a16, 0x915cb0c3, 0x40487f94, 0x91500f67,
-  0x4032c297, 0x91437250,
-  0x401d0321, 0x9136d97d, 0x40074132, 0x912a44f0, 0x3ff17cca, 0x911db4a9,
-  0x3fdbb5ec, 0x911128a8,
-  0x3fc5ec98, 0x9104a0ee, 0x3fb020ce, 0x90f81d7b, 0x3f9a5290, 0x90eb9e50,
-  0x3f8481dd, 0x90df236e,
-  0x3f6eaeb8, 0x90d2acd4, 0x3f58d921, 0x90c63a83, 0x3f430119, 0x90b9cc7d,
-  0x3f2d26a0, 0x90ad62c0,
-  0x3f1749b8, 0x90a0fd4e, 0x3f016a61, 0x90949c28, 0x3eeb889c, 0x90883f4d,
-  0x3ed5a46b, 0x907be6be,
-  0x3ebfbdcd, 0x906f927c, 0x3ea9d4c3, 0x90634287, 0x3e93e950, 0x9056f6df,
-  0x3e7dfb73, 0x904aaf86,
-  0x3e680b2c, 0x903e6c7b, 0x3e52187f, 0x90322dbf, 0x3e3c2369, 0x9025f352,
-  0x3e262bee, 0x9019bd36,
-  0x3e10320d, 0x900d8b69, 0x3dfa35c8, 0x90015dee, 0x3de4371f, 0x8ff534c4,
-  0x3dce3614, 0x8fe90fec,
-  0x3db832a6, 0x8fdcef66, 0x3da22cd7, 0x8fd0d333, 0x3d8c24a8, 0x8fc4bb53,
-  0x3d761a19, 0x8fb8a7c7,
-  0x3d600d2c, 0x8fac988f, 0x3d49fde1, 0x8fa08dab, 0x3d33ec39, 0x8f94871d,
-  0x3d1dd835, 0x8f8884e4,
-  0x3d07c1d6, 0x8f7c8701, 0x3cf1a91c, 0x8f708d75, 0x3cdb8e09, 0x8f649840,
-  0x3cc5709e, 0x8f58a761,
-  0x3caf50da, 0x8f4cbadb, 0x3c992ec0, 0x8f40d2ad, 0x3c830a50, 0x8f34eed8,
-  0x3c6ce38a, 0x8f290f5c,
-  0x3c56ba70, 0x8f1d343a, 0x3c408f03, 0x8f115d72, 0x3c2a6142, 0x8f058b04,
-  0x3c143130, 0x8ef9bcf2,
-  0x3bfdfecd, 0x8eedf33b, 0x3be7ca1a, 0x8ee22de0, 0x3bd19318, 0x8ed66ce1,
-  0x3bbb59c7, 0x8ecab040,
-  0x3ba51e29, 0x8ebef7fb, 0x3b8ee03e, 0x8eb34415, 0x3b78a007, 0x8ea7948c,
-  0x3b625d86, 0x8e9be963,
-  0x3b4c18ba, 0x8e904298, 0x3b35d1a5, 0x8e84a02d, 0x3b1f8848, 0x8e790222,
-  0x3b093ca3, 0x8e6d6877,
-  0x3af2eeb7, 0x8e61d32e, 0x3adc9e86, 0x8e564246, 0x3ac64c0f, 0x8e4ab5bf,
-  0x3aaff755, 0x8e3f2d9b,
-  0x3a99a057, 0x8e33a9da, 0x3a834717, 0x8e282a7b, 0x3a6ceb96, 0x8e1caf80,
-  0x3a568dd4, 0x8e1138ea,
-  0x3a402dd2, 0x8e05c6b7, 0x3a29cb91, 0x8dfa58ea, 0x3a136712, 0x8deeef82,
-  0x39fd0056, 0x8de38a80,
-  0x39e6975e, 0x8dd829e4, 0x39d02c2a, 0x8dcccdaf, 0x39b9bebc, 0x8dc175e0,
-  0x39a34f13, 0x8db6227a,
-  0x398cdd32, 0x8daad37b, 0x39766919, 0x8d9f88e5, 0x395ff2c9, 0x8d9442b8,
-  0x39497a43, 0x8d8900f3,
-  0x3932ff87, 0x8d7dc399, 0x391c8297, 0x8d728aa9, 0x39060373, 0x8d675623,
-  0x38ef821c, 0x8d5c2609,
-  0x38d8fe93, 0x8d50fa59, 0x38c278d9, 0x8d45d316, 0x38abf0ef, 0x8d3ab03f,
-  0x389566d6, 0x8d2f91d5,
-  0x387eda8e, 0x8d2477d8, 0x38684c19, 0x8d196249, 0x3851bb77, 0x8d0e5127,
-  0x383b28a9, 0x8d034474,
-  0x382493b0, 0x8cf83c30, 0x380dfc8d, 0x8ced385b, 0x37f76341, 0x8ce238f6,
-  0x37e0c7cc, 0x8cd73e01,
-  0x37ca2a30, 0x8ccc477d, 0x37b38a6d, 0x8cc1556a, 0x379ce885, 0x8cb667c8,
-  0x37864477, 0x8cab7e98,
-  0x376f9e46, 0x8ca099da, 0x3758f5f2, 0x8c95b98f, 0x37424b7b, 0x8c8addb7,
-  0x372b9ee3, 0x8c800652,
-  0x3714f02a, 0x8c753362, 0x36fe3f52, 0x8c6a64e5, 0x36e78c5b, 0x8c5f9ade,
-  0x36d0d746, 0x8c54d54c,
-  0x36ba2014, 0x8c4a142f, 0x36a366c6, 0x8c3f5788, 0x368cab5c, 0x8c349f58,
-  0x3675edd9, 0x8c29eb9f,
-  0x365f2e3b, 0x8c1f3c5d, 0x36486c86, 0x8c149192, 0x3631a8b8, 0x8c09eb40,
-  0x361ae2d3, 0x8bff4966,
-  0x36041ad9, 0x8bf4ac05, 0x35ed50c9, 0x8bea131e, 0x35d684a6, 0x8bdf7eb0,
-  0x35bfb66e, 0x8bd4eebc,
-  0x35a8e625, 0x8bca6343, 0x359213c9, 0x8bbfdc44, 0x357b3f5d, 0x8bb559c1,
-  0x356468e2, 0x8baadbba,
-  0x354d9057, 0x8ba0622f, 0x3536b5be, 0x8b95ed21, 0x351fd918, 0x8b8b7c8f,
-  0x3508fa66, 0x8b81107b,
-  0x34f219a8, 0x8b76a8e4, 0x34db36df, 0x8b6c45cc, 0x34c4520d, 0x8b61e733,
-  0x34ad6b32, 0x8b578d18,
-  0x34968250, 0x8b4d377c, 0x347f9766, 0x8b42e661, 0x3468aa76, 0x8b3899c6,
-  0x3451bb81, 0x8b2e51ab,
-  0x343aca87, 0x8b240e11, 0x3423d78a, 0x8b19cef8, 0x340ce28b, 0x8b0f9462,
-  0x33f5eb89, 0x8b055e4d,
-  0x33def287, 0x8afb2cbb, 0x33c7f785, 0x8af0ffac, 0x33b0fa84, 0x8ae6d720,
-  0x3399fb85, 0x8adcb318,
-  0x3382fa88, 0x8ad29394, 0x336bf78f, 0x8ac87894, 0x3354f29b, 0x8abe6219,
-  0x333debab, 0x8ab45024,
-  0x3326e2c3, 0x8aaa42b4, 0x330fd7e1, 0x8aa039cb, 0x32f8cb07, 0x8a963567,
-  0x32e1bc36, 0x8a8c358b,
-  0x32caab6f, 0x8a823a36, 0x32b398b3, 0x8a784368, 0x329c8402, 0x8a6e5123,
-  0x32856d5e, 0x8a646365,
-  0x326e54c7, 0x8a5a7a31, 0x32573a3f, 0x8a509585, 0x32401dc6, 0x8a46b564,
-  0x3228ff5c, 0x8a3cd9cc,
-  0x3211df04, 0x8a3302be, 0x31fabcbd, 0x8a29303b, 0x31e39889, 0x8a1f6243,
-  0x31cc7269, 0x8a1598d6,
-  0x31b54a5e, 0x8a0bd3f5, 0x319e2067, 0x8a0213a0, 0x3186f487, 0x89f857d8,
-  0x316fc6be, 0x89eea09d,
-  0x3158970e, 0x89e4edef, 0x31416576, 0x89db3fcf, 0x312a31f8, 0x89d1963c,
-  0x3112fc95, 0x89c7f138,
-  0x30fbc54d, 0x89be50c3, 0x30e48c22, 0x89b4b4dd, 0x30cd5115, 0x89ab1d87,
-  0x30b61426, 0x89a18ac0,
-  0x309ed556, 0x8997fc8a, 0x308794a6, 0x898e72e4, 0x30705217, 0x8984edcf,
-  0x30590dab, 0x897b6d4c,
-  0x3041c761, 0x8971f15a, 0x302a7f3a, 0x896879fb, 0x30133539, 0x895f072e,
-  0x2ffbe95d, 0x895598f3,
-  0x2fe49ba7, 0x894c2f4c, 0x2fcd4c19, 0x8942ca39, 0x2fb5fab2, 0x893969b9,
-  0x2f9ea775, 0x89300dce,
-  0x2f875262, 0x8926b677, 0x2f6ffb7a, 0x891d63b5, 0x2f58a2be, 0x89141589,
-  0x2f41482e, 0x890acbf2,
-  0x2f29ebcc, 0x890186f2, 0x2f128d99, 0x88f84687, 0x2efb2d95, 0x88ef0ab4,
-  0x2ee3cbc1, 0x88e5d378,
-  0x2ecc681e, 0x88dca0d3, 0x2eb502ae, 0x88d372c6, 0x2e9d9b70, 0x88ca4951,
-  0x2e863267, 0x88c12475,
-  0x2e6ec792, 0x88b80432, 0x2e575af3, 0x88aee888, 0x2e3fec8b, 0x88a5d177,
-  0x2e287c5a, 0x889cbf01,
-  0x2e110a62, 0x8893b125, 0x2df996a3, 0x888aa7e3, 0x2de2211e, 0x8881a33d,
-  0x2dcaa9d5, 0x8878a332,
-  0x2db330c7, 0x886fa7c2, 0x2d9bb5f6, 0x8866b0ef, 0x2d843964, 0x885dbeb8,
-  0x2d6cbb10, 0x8854d11e,
-  0x2d553afc, 0x884be821, 0x2d3db928, 0x884303c1, 0x2d263596, 0x883a23ff,
-  0x2d0eb046, 0x883148db,
-  0x2cf72939, 0x88287256, 0x2cdfa071, 0x881fa06f, 0x2cc815ee, 0x8816d327,
-  0x2cb089b1, 0x880e0a7f,
-  0x2c98fbba, 0x88054677, 0x2c816c0c, 0x87fc870f, 0x2c69daa6, 0x87f3cc48,
-  0x2c52478a, 0x87eb1621,
-  0x2c3ab2b9, 0x87e2649b, 0x2c231c33, 0x87d9b7b7, 0x2c0b83fa, 0x87d10f75,
-  0x2bf3ea0d, 0x87c86bd5,
-  0x2bdc4e6f, 0x87bfccd7, 0x2bc4b120, 0x87b7327d, 0x2bad1221, 0x87ae9cc5,
-  0x2b957173, 0x87a60bb1,
-  0x2b7dcf17, 0x879d7f41, 0x2b662b0e, 0x8794f774, 0x2b4e8558, 0x878c744d,
-  0x2b36ddf7, 0x8783f5ca,
-  0x2b1f34eb, 0x877b7bec, 0x2b078a36, 0x877306b4, 0x2aefddd8, 0x876a9621,
-  0x2ad82fd2, 0x87622a35,
-  0x2ac08026, 0x8759c2ef, 0x2aa8ced3, 0x87516050, 0x2a911bdc, 0x87490258,
-  0x2a796740, 0x8740a907,
-  0x2a61b101, 0x8738545e, 0x2a49f920, 0x8730045d, 0x2a323f9e, 0x8727b905,
-  0x2a1a847b, 0x871f7255,
-  0x2a02c7b8, 0x8717304e, 0x29eb0957, 0x870ef2f1, 0x29d34958, 0x8706ba3d,
-  0x29bb87bc, 0x86fe8633,
-  0x29a3c485, 0x86f656d3, 0x298bffb2, 0x86ee2c1e, 0x29743946, 0x86e60614,
-  0x295c7140, 0x86dde4b5,
-  0x2944a7a2, 0x86d5c802, 0x292cdc6d, 0x86cdaffa, 0x29150fa1, 0x86c59c9f,
-  0x28fd4140, 0x86bd8df0,
-  0x28e5714b, 0x86b583ee, 0x28cd9fc1, 0x86ad7e99, 0x28b5cca5, 0x86a57df2,
-  0x289df7f8, 0x869d81f8,
-  0x288621b9, 0x86958aac, 0x286e49ea, 0x868d980e, 0x2856708d, 0x8685aa20,
-  0x283e95a1, 0x867dc0e0,
-  0x2826b928, 0x8675dc4f, 0x280edb23, 0x866dfc6e, 0x27f6fb92, 0x8666213c,
-  0x27df1a77, 0x865e4abb,
-  0x27c737d3, 0x865678eb, 0x27af53a6, 0x864eabcb, 0x27976df1, 0x8646e35c,
-  0x277f86b5, 0x863f1f9e,
-  0x27679df4, 0x86376092, 0x274fb3ae, 0x862fa638, 0x2737c7e3, 0x8627f091,
-  0x271fda96, 0x86203f9c,
-  0x2707ebc7, 0x86189359, 0x26effb76, 0x8610ebca, 0x26d809a5, 0x860948ef,
-  0x26c01655, 0x8601aac7,
-  0x26a82186, 0x85fa1153, 0x26902b39, 0x85f27c93, 0x26783370, 0x85eaec88,
-  0x26603a2c, 0x85e36132,
-  0x26483f6c, 0x85dbda91, 0x26304333, 0x85d458a6, 0x26184581, 0x85ccdb70,
-  0x26004657, 0x85c562f1,
-  0x25e845b6, 0x85bdef28, 0x25d0439f, 0x85b68015, 0x25b84012, 0x85af15b9,
-  0x25a03b11, 0x85a7b015,
-  0x2588349d, 0x85a04f28, 0x25702cb7, 0x8598f2f3, 0x2558235f, 0x85919b76,
-  0x25401896, 0x858a48b1,
-  0x25280c5e, 0x8582faa5, 0x250ffeb7, 0x857bb152, 0x24f7efa2, 0x85746cb8,
-  0x24dfdf20, 0x856d2cd7,
-  0x24c7cd33, 0x8565f1b0, 0x24afb9da, 0x855ebb44, 0x2497a517, 0x85578991,
-  0x247f8eec, 0x85505c99,
-  0x24677758, 0x8549345c, 0x244f5e5c, 0x854210db, 0x243743fa, 0x853af214,
-  0x241f2833, 0x8533d809,
-  0x24070b08, 0x852cc2bb, 0x23eeec78, 0x8525b228, 0x23d6cc87, 0x851ea652,
-  0x23beab33, 0x85179f39,
-  0x23a6887f, 0x85109cdd, 0x238e646a, 0x85099f3e, 0x23763ef7, 0x8502a65c,
-  0x235e1826, 0x84fbb239,
-  0x2345eff8, 0x84f4c2d4, 0x232dc66d, 0x84edd82d, 0x23159b88, 0x84e6f244,
-  0x22fd6f48, 0x84e0111b,
-  0x22e541af, 0x84d934b1, 0x22cd12bd, 0x84d25d06, 0x22b4e274, 0x84cb8a1b,
-  0x229cb0d5, 0x84c4bbf0,
-  0x22847de0, 0x84bdf286, 0x226c4996, 0x84b72ddb, 0x225413f8, 0x84b06df2,
-  0x223bdd08, 0x84a9b2ca,
-  0x2223a4c5, 0x84a2fc62, 0x220b6b32, 0x849c4abd, 0x21f3304f, 0x84959dd9,
-  0x21daf41d, 0x848ef5b7,
-  0x21c2b69c, 0x84885258, 0x21aa77cf, 0x8481b3bb, 0x219237b5, 0x847b19e1,
-  0x2179f64f, 0x847484ca,
-  0x2161b3a0, 0x846df477, 0x21496fa7, 0x846768e7, 0x21312a65, 0x8460e21a,
-  0x2118e3dc, 0x845a6012,
-  0x21009c0c, 0x8453e2cf, 0x20e852f6, 0x844d6a50, 0x20d0089c, 0x8446f695,
-  0x20b7bcfe, 0x844087a0,
-  0x209f701c, 0x843a1d70, 0x208721f9, 0x8433b806, 0x206ed295, 0x842d5762,
-  0x205681f1, 0x8426fb84,
-  0x203e300d, 0x8420a46c, 0x2025dcec, 0x841a521a, 0x200d888d, 0x84140490,
-  0x1ff532f2, 0x840dbbcc,
-  0x1fdcdc1b, 0x840777d0, 0x1fc4840a, 0x8401389b, 0x1fac2abf, 0x83fafe2e,
-  0x1f93d03c, 0x83f4c889,
-  0x1f7b7481, 0x83ee97ad, 0x1f63178f, 0x83e86b99, 0x1f4ab968, 0x83e2444d,
-  0x1f325a0b, 0x83dc21cb,
-  0x1f19f97b, 0x83d60412, 0x1f0197b8, 0x83cfeb22, 0x1ee934c3, 0x83c9d6fc,
-  0x1ed0d09d, 0x83c3c7a0,
-  0x1eb86b46, 0x83bdbd0e, 0x1ea004c1, 0x83b7b746, 0x1e879d0d, 0x83b1b649,
-  0x1e6f342c, 0x83abba17,
-  0x1e56ca1e, 0x83a5c2b0, 0x1e3e5ee5, 0x839fd014, 0x1e25f282, 0x8399e244,
-  0x1e0d84f5, 0x8393f940,
-  0x1df5163f, 0x838e1507, 0x1ddca662, 0x8388359b, 0x1dc4355e, 0x83825afb,
-  0x1dabc334, 0x837c8528,
-  0x1d934fe5, 0x8376b422, 0x1d7adb73, 0x8370e7e9, 0x1d6265dd, 0x836b207d,
-  0x1d49ef26, 0x83655ddf,
-  0x1d31774d, 0x835fa00f, 0x1d18fe54, 0x8359e70d, 0x1d00843d, 0x835432d8,
-  0x1ce80906, 0x834e8373,
-  0x1ccf8cb3, 0x8348d8dc, 0x1cb70f43, 0x83433314, 0x1c9e90b8, 0x833d921b,
-  0x1c861113, 0x8337f5f1,
-  0x1c6d9053, 0x83325e97, 0x1c550e7c, 0x832ccc0d, 0x1c3c8b8c, 0x83273e52,
-  0x1c240786, 0x8321b568,
-  0x1c0b826a, 0x831c314e, 0x1bf2fc3a, 0x8316b205, 0x1bda74f6, 0x8311378d,
-  0x1bc1ec9e, 0x830bc1e6,
-  0x1ba96335, 0x83065110, 0x1b90d8bb, 0x8300e50b, 0x1b784d30, 0x82fb7dd8,
-  0x1b5fc097, 0x82f61b77,
-  0x1b4732ef, 0x82f0bde8, 0x1b2ea43a, 0x82eb652b, 0x1b161479, 0x82e61141,
-  0x1afd83ad, 0x82e0c22a,
-  0x1ae4f1d6, 0x82db77e5, 0x1acc5ef6, 0x82d63274, 0x1ab3cb0d, 0x82d0f1d5,
-  0x1a9b361d, 0x82cbb60b,
-  0x1a82a026, 0x82c67f14, 0x1a6a0929, 0x82c14cf1, 0x1a517128, 0x82bc1fa2,
-  0x1a38d823, 0x82b6f727,
-  0x1a203e1b, 0x82b1d381, 0x1a07a311, 0x82acb4b0, 0x19ef0707, 0x82a79ab3,
-  0x19d669fc, 0x82a2858c,
-  0x19bdcbf3, 0x829d753a, 0x19a52ceb, 0x829869be, 0x198c8ce7, 0x82936317,
-  0x1973ebe6, 0x828e6146,
-  0x195b49ea, 0x8289644b, 0x1942a6f3, 0x82846c26, 0x192a0304, 0x827f78d8,
-  0x19115e1c, 0x827a8a61,
-  0x18f8b83c, 0x8275a0c0, 0x18e01167, 0x8270bbf7, 0x18c7699b, 0x826bdc04,
-  0x18aec0db, 0x826700e9,
-  0x18961728, 0x82622aa6, 0x187d6c82, 0x825d593a, 0x1864c0ea, 0x82588ca7,
-  0x184c1461, 0x8253c4eb,
-  0x183366e9, 0x824f0208, 0x181ab881, 0x824a43fe, 0x1802092c, 0x82458acc,
-  0x17e958ea, 0x8240d673,
-  0x17d0a7bc, 0x823c26f3, 0x17b7f5a3, 0x82377c4c, 0x179f429f, 0x8232d67f,
-  0x17868eb3, 0x822e358b,
-  0x176dd9de, 0x82299971, 0x17552422, 0x82250232, 0x173c6d80, 0x82206fcc,
-  0x1723b5f9, 0x821be240,
-  0x170afd8d, 0x82175990, 0x16f2443e, 0x8212d5b9, 0x16d98a0c, 0x820e56be,
-  0x16c0cef9, 0x8209dc9e,
-  0x16a81305, 0x82056758, 0x168f5632, 0x8200f6ef, 0x1676987f, 0x81fc8b60,
-  0x165dd9f0, 0x81f824ae,
-  0x16451a83, 0x81f3c2d7, 0x162c5a3b, 0x81ef65dc, 0x16139918, 0x81eb0dbe,
-  0x15fad71b, 0x81e6ba7c,
-  0x15e21445, 0x81e26c16, 0x15c95097, 0x81de228d, 0x15b08c12, 0x81d9dde1,
-  0x1597c6b7, 0x81d59e13,
-  0x157f0086, 0x81d16321, 0x15663982, 0x81cd2d0c, 0x154d71aa, 0x81c8fbd6,
-  0x1534a901, 0x81c4cf7d,
-  0x151bdf86, 0x81c0a801, 0x1503153a, 0x81bc8564, 0x14ea4a1f, 0x81b867a5,
-  0x14d17e36, 0x81b44ec4,
-  0x14b8b17f, 0x81b03ac2, 0x149fe3fc, 0x81ac2b9e, 0x148715ae, 0x81a82159,
-  0x146e4694, 0x81a41bf4,
-  0x145576b1, 0x81a01b6d, 0x143ca605, 0x819c1fc5, 0x1423d492, 0x819828fd,
-  0x140b0258, 0x81943715,
-  0x13f22f58, 0x81904a0c, 0x13d95b93, 0x818c61e3, 0x13c0870a, 0x81887e9a,
-  0x13a7b1bf, 0x8184a032,
-  0x138edbb1, 0x8180c6a9, 0x137604e2, 0x817cf201, 0x135d2d53, 0x8179223a,
-  0x13445505, 0x81755754,
-  0x132b7bf9, 0x8171914e, 0x1312a230, 0x816dd02a, 0x12f9c7aa, 0x816a13e6,
-  0x12e0ec6a, 0x81665c84,
-  0x12c8106f, 0x8162aa04, 0x12af33ba, 0x815efc65, 0x1296564d, 0x815b53a8,
-  0x127d7829, 0x8157afcd,
-  0x1264994e, 0x815410d4, 0x124bb9be, 0x815076bd, 0x1232d979, 0x814ce188,
-  0x1219f880, 0x81495136,
-  0x120116d5, 0x8145c5c7, 0x11e83478, 0x81423f3a, 0x11cf516a, 0x813ebd90,
-  0x11b66dad, 0x813b40ca,
-  0x119d8941, 0x8137c8e6, 0x1184a427, 0x813455e6, 0x116bbe60, 0x8130e7c9,
-  0x1152d7ed, 0x812d7e8f,
-  0x1139f0cf, 0x812a1a3a, 0x11210907, 0x8126bac8, 0x11082096, 0x8123603a,
-  0x10ef377d, 0x81200a90,
-  0x10d64dbd, 0x811cb9ca, 0x10bd6356, 0x81196de9, 0x10a4784b, 0x811626ec,
-  0x108b8c9b, 0x8112e4d4,
-  0x1072a048, 0x810fa7a0, 0x1059b352, 0x810c6f52, 0x1040c5bb, 0x81093be8,
-  0x1027d784, 0x81060d63,
-  0x100ee8ad, 0x8102e3c4, 0xff5f938, 0x80ffbf0a, 0xfdd0926, 0x80fc9f35,
-  0xfc41876, 0x80f98446,
-  0xfab272b, 0x80f66e3c, 0xf923546, 0x80f35d19, 0xf7942c7, 0x80f050db,
-  0xf604faf, 0x80ed4984,
-  0xf475bff, 0x80ea4712, 0xf2e67b8, 0x80e74987, 0xf1572dc, 0x80e450e2,
-  0xefc7d6b, 0x80e15d24,
-  0xee38766, 0x80de6e4c, 0xeca90ce, 0x80db845b, 0xeb199a4, 0x80d89f51,
-  0xe98a1e9, 0x80d5bf2e,
-  0xe7fa99e, 0x80d2e3f2, 0xe66b0c3, 0x80d00d9d, 0xe4db75b, 0x80cd3c2f,
-  0xe34bd66, 0x80ca6fa9,
-  0xe1bc2e4, 0x80c7a80a, 0xe02c7d7, 0x80c4e553, 0xde9cc40, 0x80c22784,
-  0xdd0d01f, 0x80bf6e9c,
-  0xdb7d376, 0x80bcba9d, 0xd9ed646, 0x80ba0b85, 0xd85d88f, 0x80b76156,
-  0xd6cda53, 0x80b4bc0e,
-  0xd53db92, 0x80b21baf, 0xd3adc4e, 0x80af8039, 0xd21dc87, 0x80ace9ab,
-  0xd08dc3f, 0x80aa5806,
-  0xcefdb76, 0x80a7cb49, 0xcd6da2d, 0x80a54376, 0xcbdd865, 0x80a2c08b,
-  0xca4d620, 0x80a04289,
-  0xc8bd35e, 0x809dc971, 0xc72d020, 0x809b5541, 0xc59cc68, 0x8098e5fb,
-  0xc40c835, 0x80967b9f,
-  0xc27c389, 0x8094162c, 0xc0ebe66, 0x8091b5a2, 0xbf5b8cb, 0x808f5a02,
-  0xbdcb2bb, 0x808d034c,
-  0xbc3ac35, 0x808ab180, 0xbaaa53b, 0x8088649e, 0xb919dcf, 0x80861ca6,
-  0xb7895f0, 0x8083d998,
-  0xb5f8d9f, 0x80819b74, 0xb4684df, 0x807f623b, 0xb2d7baf, 0x807d2dec,
-  0xb147211, 0x807afe87,
-  0xafb6805, 0x8078d40d, 0xae25d8d, 0x8076ae7e, 0xac952aa, 0x80748dd9,
-  0xab0475c, 0x8072721f,
-  0xa973ba5, 0x80705b50, 0xa7e2f85, 0x806e496c, 0xa6522fe, 0x806c3c74,
-  0xa4c1610, 0x806a3466,
-  0xa3308bd, 0x80683143, 0xa19fb04, 0x8066330c, 0xa00ece8, 0x806439c0,
-  0x9e7de6a, 0x80624560,
-  0x9cecf89, 0x806055eb, 0x9b5c048, 0x805e6b62, 0x99cb0a7, 0x805c85c4,
-  0x983a0a7, 0x805aa512,
-  0x96a9049, 0x8058c94c, 0x9517f8f, 0x8056f272, 0x9386e78, 0x80552084,
-  0x91f5d06, 0x80535381,
-  0x9064b3a, 0x80518b6b, 0x8ed3916, 0x804fc841, 0x8d42699, 0x804e0a04,
-  0x8bb13c5, 0x804c50b2,
-  0x8a2009a, 0x804a9c4d, 0x888ed1b, 0x8048ecd5, 0x86fd947, 0x80474248,
-  0x856c520, 0x80459ca9,
-  0x83db0a7, 0x8043fbf6, 0x8249bdd, 0x80426030, 0x80b86c2, 0x8040c956,
-  0x7f27157, 0x803f376a,
-  0x7d95b9e, 0x803daa6a, 0x7c04598, 0x803c2257, 0x7a72f45, 0x803a9f31,
-  0x78e18a7, 0x803920f8,
-  0x77501be, 0x8037a7ac, 0x75bea8c, 0x8036334e, 0x742d311, 0x8034c3dd,
-  0x729bb4e, 0x80335959,
-  0x710a345, 0x8031f3c2, 0x6f78af6, 0x80309318, 0x6de7262, 0x802f375d,
-  0x6c5598a, 0x802de08e,
-  0x6ac406f, 0x802c8ead, 0x6932713, 0x802b41ba, 0x67a0d76, 0x8029f9b4,
-  0x660f398, 0x8028b69c,
-  0x647d97c, 0x80277872, 0x62ebf22, 0x80263f36, 0x615a48b, 0x80250ae7,
-  0x5fc89b8, 0x8023db86,
-  0x5e36ea9, 0x8022b114, 0x5ca5361, 0x80218b8f, 0x5b137df, 0x80206af8,
-  0x5981c26, 0x801f4f4f,
-  0x57f0035, 0x801e3895, 0x565e40d, 0x801d26c8, 0x54cc7b1, 0x801c19ea,
-  0x533ab20, 0x801b11fa,
-  0x51a8e5c, 0x801a0ef8, 0x5017165, 0x801910e4, 0x4e8543e, 0x801817bf,
-  0x4cf36e5, 0x80172388,
-  0x4b6195d, 0x80163440, 0x49cfba7, 0x801549e6, 0x483ddc3, 0x8014647b,
-  0x46abfb3, 0x801383fe,
-  0x451a177, 0x8012a86f, 0x4388310, 0x8011d1d0, 0x41f6480, 0x8011001f,
-  0x40645c7, 0x8010335c,
-  0x3ed26e6, 0x800f6b88, 0x3d407df, 0x800ea8a3, 0x3bae8b2, 0x800deaad,
-  0x3a1c960, 0x800d31a5,
-  0x388a9ea, 0x800c7d8c, 0x36f8a51, 0x800bce63, 0x3566a96, 0x800b2427,
-  0x33d4abb, 0x800a7edb,
-  0x3242abf, 0x8009de7e, 0x30b0aa4, 0x80094310, 0x2f1ea6c, 0x8008ac90,
-  0x2d8ca16, 0x80081b00,
-  0x2bfa9a4, 0x80078e5e, 0x2a68917, 0x800706ac, 0x28d6870, 0x800683e8,
-  0x27447b0, 0x80060614,
-  0x25b26d7, 0x80058d2f, 0x24205e8, 0x80051939, 0x228e4e2, 0x8004aa32,
-  0x20fc3c6, 0x8004401a,
-  0x1f6a297, 0x8003daf1, 0x1dd8154, 0x80037ab7, 0x1c45ffe, 0x80031f6d,
-  0x1ab3e97, 0x8002c912,
-  0x1921d20, 0x800277a6, 0x178fb99, 0x80022b29, 0x15fda03, 0x8001e39b,
-  0x146b860, 0x8001a0fd,
-  0x12d96b1, 0x8001634e, 0x11474f6, 0x80012a8e, 0xfb5330, 0x8000f6bd,
-  0xe23160, 0x8000c7dc,
-  0xc90f88, 0x80009dea, 0xafeda8, 0x800078e7, 0x96cbc1, 0x800058d4, 0x7da9d4,
-  0x80003daf,
-  0x6487e3, 0x8000277a, 0x4b65ee, 0x80001635, 0x3243f5, 0x800009df, 0x1921fb,
-  0x80000278,
-};
-
-static const q31_t WeightsQ31_8192[16384] = {
-  0x7fffffff, 0x0, 0x7fffffd9, 0xfff9b781, 0x7fffff62, 0xfff36f02, 0x7ffffe9d,
-    0xffed2684,
-  0x7ffffd88, 0xffe6de05, 0x7ffffc25, 0xffe09586, 0x7ffffa73, 0xffda4d08,
-    0x7ffff872, 0xffd40489,
-  0x7ffff621, 0xffcdbc0b, 0x7ffff382, 0xffc7738c, 0x7ffff094, 0xffc12b0e,
-    0x7fffed57, 0xffbae290,
-  0x7fffe9cb, 0xffb49a12, 0x7fffe5f0, 0xffae5195, 0x7fffe1c6, 0xffa80917,
-    0x7fffdd4d, 0xffa1c09a,
-  0x7fffd886, 0xff9b781d, 0x7fffd36f, 0xff952fa0, 0x7fffce09, 0xff8ee724,
-    0x7fffc854, 0xff889ea7,
-  0x7fffc251, 0xff82562c, 0x7fffbbfe, 0xff7c0db0, 0x7fffb55c, 0xff75c535,
-    0x7fffae6c, 0xff6f7cba,
-  0x7fffa72c, 0xff69343f, 0x7fff9f9e, 0xff62ebc5, 0x7fff97c1, 0xff5ca34b,
-    0x7fff8f94, 0xff565ad1,
-  0x7fff8719, 0xff501258, 0x7fff7e4f, 0xff49c9df, 0x7fff7536, 0xff438167,
-    0x7fff6bcd, 0xff3d38ef,
-  0x7fff6216, 0xff36f078, 0x7fff5810, 0xff30a801, 0x7fff4dbb, 0xff2a5f8b,
-    0x7fff4317, 0xff241715,
-  0x7fff3824, 0xff1dcea0, 0x7fff2ce2, 0xff17862b, 0x7fff2151, 0xff113db7,
-    0x7fff1572, 0xff0af543,
-  0x7fff0943, 0xff04acd0, 0x7ffefcc5, 0xfefe645e, 0x7ffeeff8, 0xfef81bec,
-    0x7ffee2dd, 0xfef1d37b,
-  0x7ffed572, 0xfeeb8b0a, 0x7ffec7b9, 0xfee5429a, 0x7ffeb9b0, 0xfedefa2b,
-    0x7ffeab59, 0xfed8b1bd,
-  0x7ffe9cb2, 0xfed2694f, 0x7ffe8dbd, 0xfecc20e2, 0x7ffe7e79, 0xfec5d876,
-    0x7ffe6ee5, 0xfebf900a,
-  0x7ffe5f03, 0xfeb947a0, 0x7ffe4ed2, 0xfeb2ff36, 0x7ffe3e52, 0xfeacb6cc,
-    0x7ffe2d83, 0xfea66e64,
-  0x7ffe1c65, 0xfea025fd, 0x7ffe0af8, 0xfe99dd96, 0x7ffdf93c, 0xfe939530,
-    0x7ffde731, 0xfe8d4ccb,
-  0x7ffdd4d7, 0xfe870467, 0x7ffdc22e, 0xfe80bc04, 0x7ffdaf37, 0xfe7a73a2,
-    0x7ffd9bf0, 0xfe742b41,
-  0x7ffd885a, 0xfe6de2e0, 0x7ffd7476, 0xfe679a81, 0x7ffd6042, 0xfe615223,
-    0x7ffd4bc0, 0xfe5b09c5,
-  0x7ffd36ee, 0xfe54c169, 0x7ffd21ce, 0xfe4e790d, 0x7ffd0c5f, 0xfe4830b3,
-    0x7ffcf6a0, 0xfe41e85a,
-  0x7ffce093, 0xfe3ba002, 0x7ffcca37, 0xfe3557ab, 0x7ffcb38c, 0xfe2f0f55,
-    0x7ffc9c92, 0xfe28c700,
-  0x7ffc8549, 0xfe227eac, 0x7ffc6db1, 0xfe1c365a, 0x7ffc55ca, 0xfe15ee09,
-    0x7ffc3d94, 0xfe0fa5b8,
-  0x7ffc250f, 0xfe095d69, 0x7ffc0c3b, 0xfe03151c, 0x7ffbf319, 0xfdfccccf,
-    0x7ffbd9a7, 0xfdf68484,
-  0x7ffbbfe6, 0xfdf03c3a, 0x7ffba5d7, 0xfde9f3f1, 0x7ffb8b78, 0xfde3aba9,
-    0x7ffb70cb, 0xfddd6363,
-  0x7ffb55ce, 0xfdd71b1e, 0x7ffb3a83, 0xfdd0d2db, 0x7ffb1ee9, 0xfdca8a99,
-    0x7ffb0300, 0xfdc44258,
-  0x7ffae6c7, 0xfdbdfa18, 0x7ffaca40, 0xfdb7b1da, 0x7ffaad6a, 0xfdb1699e,
-    0x7ffa9045, 0xfdab2162,
-  0x7ffa72d1, 0xfda4d929, 0x7ffa550e, 0xfd9e90f0, 0x7ffa36fc, 0xfd9848b9,
-    0x7ffa189c, 0xfd920084,
-  0x7ff9f9ec, 0xfd8bb850, 0x7ff9daed, 0xfd85701e, 0x7ff9bba0, 0xfd7f27ed,
-    0x7ff99c03, 0xfd78dfbd,
-  0x7ff97c18, 0xfd729790, 0x7ff95bdd, 0xfd6c4f64, 0x7ff93b54, 0xfd660739,
-    0x7ff91a7b, 0xfd5fbf10,
-  0x7ff8f954, 0xfd5976e9, 0x7ff8d7de, 0xfd532ec3, 0x7ff8b619, 0xfd4ce69f,
-    0x7ff89405, 0xfd469e7c,
-  0x7ff871a2, 0xfd40565c, 0x7ff84ef0, 0xfd3a0e3d, 0x7ff82bef, 0xfd33c61f,
-    0x7ff8089f, 0xfd2d7e04,
-  0x7ff7e500, 0xfd2735ea, 0x7ff7c113, 0xfd20edd2, 0x7ff79cd6, 0xfd1aa5bc,
-    0x7ff7784a, 0xfd145da7,
-  0x7ff75370, 0xfd0e1594, 0x7ff72e46, 0xfd07cd83, 0x7ff708ce, 0xfd018574,
-    0x7ff6e307, 0xfcfb3d67,
-  0x7ff6bcf0, 0xfcf4f55c, 0x7ff6968b, 0xfceead52, 0x7ff66fd7, 0xfce8654b,
-    0x7ff648d4, 0xfce21d45,
-  0x7ff62182, 0xfcdbd541, 0x7ff5f9e1, 0xfcd58d3f, 0x7ff5d1f1, 0xfccf453f,
-    0x7ff5a9b2, 0xfcc8fd41,
-  0x7ff58125, 0xfcc2b545, 0x7ff55848, 0xfcbc6d4c, 0x7ff52f1d, 0xfcb62554,
-    0x7ff505a2, 0xfcafdd5e,
-  0x7ff4dbd9, 0xfca9956a, 0x7ff4b1c0, 0xfca34d78, 0x7ff48759, 0xfc9d0588,
-    0x7ff45ca3, 0xfc96bd9b,
-  0x7ff4319d, 0xfc9075af, 0x7ff40649, 0xfc8a2dc6, 0x7ff3daa6, 0xfc83e5de,
-    0x7ff3aeb4, 0xfc7d9df9,
-  0x7ff38274, 0xfc775616, 0x7ff355e4, 0xfc710e36, 0x7ff32905, 0xfc6ac657,
-    0x7ff2fbd7, 0xfc647e7b,
-  0x7ff2ce5b, 0xfc5e36a0, 0x7ff2a08f, 0xfc57eec9, 0x7ff27275, 0xfc51a6f3,
-    0x7ff2440b, 0xfc4b5f20,
-  0x7ff21553, 0xfc45174e, 0x7ff1e64c, 0xfc3ecf80, 0x7ff1b6f6, 0xfc3887b3,
-    0x7ff18751, 0xfc323fe9,
-  0x7ff1575d, 0xfc2bf821, 0x7ff1271a, 0xfc25b05c, 0x7ff0f688, 0xfc1f6899,
-    0x7ff0c5a7, 0xfc1920d8,
-  0x7ff09478, 0xfc12d91a, 0x7ff062f9, 0xfc0c915e, 0x7ff0312c, 0xfc0649a5,
-    0x7fefff0f, 0xfc0001ee,
-  0x7fefcca4, 0xfbf9ba39, 0x7fef99ea, 0xfbf37287, 0x7fef66e1, 0xfbed2ad8,
-    0x7fef3388, 0xfbe6e32b,
-  0x7feeffe1, 0xfbe09b80, 0x7feecbec, 0xfbda53d8, 0x7fee97a7, 0xfbd40c33,
-    0x7fee6313, 0xfbcdc490,
-  0x7fee2e30, 0xfbc77cf0, 0x7fedf8ff, 0xfbc13552, 0x7fedc37e, 0xfbbaedb7,
-    0x7fed8daf, 0xfbb4a61f,
-  0x7fed5791, 0xfbae5e89, 0x7fed2123, 0xfba816f6, 0x7fecea67, 0xfba1cf66,
-    0x7fecb35c, 0xfb9b87d8,
-  0x7fec7c02, 0xfb95404d, 0x7fec4459, 0xfb8ef8c5, 0x7fec0c62, 0xfb88b13f,
-    0x7febd41b, 0xfb8269bd,
-  0x7feb9b85, 0xfb7c223d, 0x7feb62a1, 0xfb75dac0, 0x7feb296d, 0xfb6f9345,
-    0x7feaefeb, 0xfb694bce,
-  0x7feab61a, 0xfb630459, 0x7fea7bfa, 0xfb5cbce7, 0x7fea418b, 0xfb567578,
-    0x7fea06cd, 0xfb502e0c,
-  0x7fe9cbc0, 0xfb49e6a3, 0x7fe99064, 0xfb439f3c, 0x7fe954ba, 0xfb3d57d9,
-    0x7fe918c0, 0xfb371078,
-  0x7fe8dc78, 0xfb30c91b, 0x7fe89fe0, 0xfb2a81c0, 0x7fe862fa, 0xfb243a69,
-    0x7fe825c5, 0xfb1df314,
-  0x7fe7e841, 0xfb17abc2, 0x7fe7aa6e, 0xfb116474, 0x7fe76c4c, 0xfb0b1d28,
-    0x7fe72ddb, 0xfb04d5e0,
-  0x7fe6ef1c, 0xfafe8e9b, 0x7fe6b00d, 0xfaf84758, 0x7fe670b0, 0xfaf20019,
-    0x7fe63103, 0xfaebb8dd,
-  0x7fe5f108, 0xfae571a4, 0x7fe5b0be, 0xfadf2a6e, 0x7fe57025, 0xfad8e33c,
-    0x7fe52f3d, 0xfad29c0c,
-  0x7fe4ee06, 0xfacc54e0, 0x7fe4ac81, 0xfac60db7, 0x7fe46aac, 0xfabfc691,
-    0x7fe42889, 0xfab97f6e,
-  0x7fe3e616, 0xfab3384f, 0x7fe3a355, 0xfaacf133, 0x7fe36045, 0xfaa6aa1a,
-    0x7fe31ce6, 0xfaa06305,
-  0x7fe2d938, 0xfa9a1bf3, 0x7fe2953b, 0xfa93d4e4, 0x7fe250ef, 0xfa8d8dd8,
-    0x7fe20c55, 0xfa8746d0,
-  0x7fe1c76b, 0xfa80ffcb, 0x7fe18233, 0xfa7ab8ca, 0x7fe13cac, 0xfa7471cc,
-    0x7fe0f6d6, 0xfa6e2ad1,
-  0x7fe0b0b1, 0xfa67e3da, 0x7fe06a3d, 0xfa619ce7, 0x7fe0237a, 0xfa5b55f7,
-    0x7fdfdc69, 0xfa550f0a,
-  0x7fdf9508, 0xfa4ec821, 0x7fdf4d59, 0xfa48813b, 0x7fdf055a, 0xfa423a59,
-    0x7fdebd0d, 0xfa3bf37a,
-  0x7fde7471, 0xfa35ac9f, 0x7fde2b86, 0xfa2f65c8, 0x7fdde24d, 0xfa291ef4,
-    0x7fdd98c4, 0xfa22d823,
-  0x7fdd4eec, 0xfa1c9157, 0x7fdd04c6, 0xfa164a8e, 0x7fdcba51, 0xfa1003c8,
-    0x7fdc6f8d, 0xfa09bd06,
-  0x7fdc247a, 0xfa037648, 0x7fdbd918, 0xf9fd2f8e, 0x7fdb8d67, 0xf9f6e8d7,
-    0x7fdb4167, 0xf9f0a224,
-  0x7fdaf519, 0xf9ea5b75, 0x7fdaa87c, 0xf9e414ca, 0x7fda5b8f, 0xf9ddce22,
-    0x7fda0e54, 0xf9d7877e,
-  0x7fd9c0ca, 0xf9d140de, 0x7fd972f2, 0xf9cafa42, 0x7fd924ca, 0xf9c4b3a9,
-    0x7fd8d653, 0xf9be6d15,
-  0x7fd8878e, 0xf9b82684, 0x7fd8387a, 0xf9b1dff7, 0x7fd7e917, 0xf9ab996e,
-    0x7fd79965, 0xf9a552e9,
-  0x7fd74964, 0xf99f0c68, 0x7fd6f914, 0xf998c5ea, 0x7fd6a875, 0xf9927f71,
-    0x7fd65788, 0xf98c38fc,
-  0x7fd6064c, 0xf985f28a, 0x7fd5b4c1, 0xf97fac1d, 0x7fd562e7, 0xf97965b4,
-    0x7fd510be, 0xf9731f4e,
-  0x7fd4be46, 0xf96cd8ed, 0x7fd46b80, 0xf9669290, 0x7fd4186a, 0xf9604c37,
-    0x7fd3c506, 0xf95a05e2,
-  0x7fd37153, 0xf953bf91, 0x7fd31d51, 0xf94d7944, 0x7fd2c900, 0xf94732fb,
-    0x7fd27460, 0xf940ecb7,
-  0x7fd21f72, 0xf93aa676, 0x7fd1ca35, 0xf934603a, 0x7fd174a8, 0xf92e1a02,
-    0x7fd11ecd, 0xf927d3ce,
-  0x7fd0c8a3, 0xf9218d9e, 0x7fd0722b, 0xf91b4773, 0x7fd01b63, 0xf915014c,
-    0x7fcfc44d, 0xf90ebb29,
-  0x7fcf6ce8, 0xf908750a, 0x7fcf1533, 0xf9022ef0, 0x7fcebd31, 0xf8fbe8da,
-    0x7fce64df, 0xf8f5a2c9,
-  0x7fce0c3e, 0xf8ef5cbb, 0x7fcdb34f, 0xf8e916b2, 0x7fcd5a11, 0xf8e2d0ae,
-    0x7fcd0083, 0xf8dc8aae,
-  0x7fcca6a7, 0xf8d644b2, 0x7fcc4c7d, 0xf8cffebb, 0x7fcbf203, 0xf8c9b8c8,
-    0x7fcb973b, 0xf8c372d9,
-  0x7fcb3c23, 0xf8bd2cef, 0x7fcae0bd, 0xf8b6e70a, 0x7fca8508, 0xf8b0a129,
-    0x7fca2905, 0xf8aa5b4c,
-  0x7fc9ccb2, 0xf8a41574, 0x7fc97011, 0xf89dcfa1, 0x7fc91320, 0xf89789d2,
-    0x7fc8b5e1, 0xf8914407,
-  0x7fc85854, 0xf88afe42, 0x7fc7fa77, 0xf884b880, 0x7fc79c4b, 0xf87e72c4,
-    0x7fc73dd1, 0xf8782d0c,
-  0x7fc6df08, 0xf871e759, 0x7fc67ff0, 0xf86ba1aa, 0x7fc62089, 0xf8655c00,
-    0x7fc5c0d3, 0xf85f165b,
-  0x7fc560cf, 0xf858d0bb, 0x7fc5007c, 0xf8528b1f, 0x7fc49fda, 0xf84c4588,
-    0x7fc43ee9, 0xf845fff5,
-  0x7fc3dda9, 0xf83fba68, 0x7fc37c1b, 0xf83974df, 0x7fc31a3d, 0xf8332f5b,
-    0x7fc2b811, 0xf82ce9dc,
-  0x7fc25596, 0xf826a462, 0x7fc1f2cc, 0xf8205eec, 0x7fc18fb4, 0xf81a197b,
-    0x7fc12c4d, 0xf813d410,
-  0x7fc0c896, 0xf80d8ea9, 0x7fc06491, 0xf8074947, 0x7fc0003e, 0xf80103ea,
-    0x7fbf9b9b, 0xf7fabe92,
-  0x7fbf36aa, 0xf7f4793e, 0x7fbed16a, 0xf7ee33f0, 0x7fbe6bdb, 0xf7e7eea7,
-    0x7fbe05fd, 0xf7e1a963,
-  0x7fbd9fd0, 0xf7db6423, 0x7fbd3955, 0xf7d51ee9, 0x7fbcd28b, 0xf7ced9b4,
-    0x7fbc6b72, 0xf7c89484,
-  0x7fbc040a, 0xf7c24f59, 0x7fbb9c53, 0xf7bc0a33, 0x7fbb344e, 0xf7b5c512,
-    0x7fbacbfa, 0xf7af7ff6,
-  0x7fba6357, 0xf7a93ae0, 0x7fb9fa65, 0xf7a2f5ce, 0x7fb99125, 0xf79cb0c2,
-    0x7fb92796, 0xf7966bbb,
-  0x7fb8bdb8, 0xf79026b9, 0x7fb8538b, 0xf789e1bc, 0x7fb7e90f, 0xf7839cc4,
-    0x7fb77e45, 0xf77d57d2,
-  0x7fb7132b, 0xf77712e5, 0x7fb6a7c3, 0xf770cdfd, 0x7fb63c0d, 0xf76a891b,
-    0x7fb5d007, 0xf764443d,
-  0x7fb563b3, 0xf75dff66, 0x7fb4f710, 0xf757ba93, 0x7fb48a1e, 0xf75175c6,
-    0x7fb41cdd, 0xf74b30fe,
-  0x7fb3af4e, 0xf744ec3b, 0x7fb34170, 0xf73ea77e, 0x7fb2d343, 0xf73862c6,
-    0x7fb264c7, 0xf7321e14,
-  0x7fb1f5fc, 0xf72bd967, 0x7fb186e3, 0xf72594c0, 0x7fb1177b, 0xf71f501e,
-    0x7fb0a7c4, 0xf7190b81,
-  0x7fb037bf, 0xf712c6ea, 0x7fafc76a, 0xf70c8259, 0x7faf56c7, 0xf7063dcd,
-    0x7faee5d5, 0xf6fff946,
-  0x7fae7495, 0xf6f9b4c6, 0x7fae0305, 0xf6f3704a, 0x7fad9127, 0xf6ed2bd4,
-    0x7fad1efa, 0xf6e6e764,
-  0x7facac7f, 0xf6e0a2fa, 0x7fac39b4, 0xf6da5e95, 0x7fabc69b, 0xf6d41a36,
-    0x7fab5333, 0xf6cdd5dc,
-  0x7faadf7c, 0xf6c79188, 0x7faa6b77, 0xf6c14d3a, 0x7fa9f723, 0xf6bb08f1,
-    0x7fa98280, 0xf6b4c4ae,
-  0x7fa90d8e, 0xf6ae8071, 0x7fa8984e, 0xf6a83c3a, 0x7fa822bf, 0xf6a1f808,
-    0x7fa7ace1, 0xf69bb3dd,
-  0x7fa736b4, 0xf6956fb7, 0x7fa6c039, 0xf68f2b96, 0x7fa6496e, 0xf688e77c,
-    0x7fa5d256, 0xf682a367,
-  0x7fa55aee, 0xf67c5f59, 0x7fa4e338, 0xf6761b50, 0x7fa46b32, 0xf66fd74d,
-    0x7fa3f2df, 0xf6699350,
-  0x7fa37a3c, 0xf6634f59, 0x7fa3014b, 0xf65d0b68, 0x7fa2880b, 0xf656c77c,
-    0x7fa20e7c, 0xf6508397,
-  0x7fa1949e, 0xf64a3fb8, 0x7fa11a72, 0xf643fbdf, 0x7fa09ff7, 0xf63db80b,
-    0x7fa0252e, 0xf637743e,
-  0x7f9faa15, 0xf6313077, 0x7f9f2eae, 0xf62aecb5, 0x7f9eb2f8, 0xf624a8fa,
-    0x7f9e36f4, 0xf61e6545,
-  0x7f9dbaa0, 0xf6182196, 0x7f9d3dfe, 0xf611dded, 0x7f9cc10d, 0xf60b9a4b,
-    0x7f9c43ce, 0xf60556ae,
-  0x7f9bc640, 0xf5ff1318, 0x7f9b4863, 0xf5f8cf87, 0x7f9aca37, 0xf5f28bfd,
-    0x7f9a4bbd, 0xf5ec4879,
-  0x7f99ccf4, 0xf5e604fc, 0x7f994ddc, 0xf5dfc184, 0x7f98ce76, 0xf5d97e13,
-    0x7f984ec1, 0xf5d33aa8,
-  0x7f97cebd, 0xf5ccf743, 0x7f974e6a, 0xf5c6b3e5, 0x7f96cdc9, 0xf5c0708d,
-    0x7f964cd9, 0xf5ba2d3b,
-  0x7f95cb9a, 0xf5b3e9f0, 0x7f954a0d, 0xf5ada6ab, 0x7f94c831, 0xf5a7636c,
-    0x7f944606, 0xf5a12034,
-  0x7f93c38c, 0xf59add02, 0x7f9340c4, 0xf59499d6, 0x7f92bdad, 0xf58e56b1,
-    0x7f923a48, 0xf5881393,
-  0x7f91b694, 0xf581d07b, 0x7f913291, 0xf57b8d69, 0x7f90ae3f, 0xf5754a5e,
-    0x7f90299f, 0xf56f0759,
-  0x7f8fa4b0, 0xf568c45b, 0x7f8f1f72, 0xf5628163, 0x7f8e99e6, 0xf55c3e72,
-    0x7f8e140a, 0xf555fb88,
-  0x7f8d8de1, 0xf54fb8a4, 0x7f8d0768, 0xf54975c6, 0x7f8c80a1, 0xf54332ef,
-    0x7f8bf98b, 0xf53cf01f,
-  0x7f8b7227, 0xf536ad56, 0x7f8aea74, 0xf5306a93, 0x7f8a6272, 0xf52a27d7,
-    0x7f89da21, 0xf523e521,
-  0x7f895182, 0xf51da273, 0x7f88c894, 0xf5175fca, 0x7f883f58, 0xf5111d29,
-    0x7f87b5cd, 0xf50ada8f,
-  0x7f872bf3, 0xf50497fb, 0x7f86a1ca, 0xf4fe556e, 0x7f861753, 0xf4f812e7,
-    0x7f858c8d, 0xf4f1d068,
-  0x7f850179, 0xf4eb8def, 0x7f847616, 0xf4e54b7d, 0x7f83ea64, 0xf4df0912,
-    0x7f835e64, 0xf4d8c6ae,
-  0x7f82d214, 0xf4d28451, 0x7f824577, 0xf4cc41fb, 0x7f81b88a, 0xf4c5ffab,
-    0x7f812b4f, 0xf4bfbd63,
-  0x7f809dc5, 0xf4b97b21, 0x7f800fed, 0xf4b338e7, 0x7f7f81c6, 0xf4acf6b3,
-    0x7f7ef350, 0xf4a6b486,
-  0x7f7e648c, 0xf4a07261, 0x7f7dd579, 0xf49a3042, 0x7f7d4617, 0xf493ee2b,
-    0x7f7cb667, 0xf48dac1a,
-  0x7f7c2668, 0xf4876a10, 0x7f7b961b, 0xf481280e, 0x7f7b057e, 0xf47ae613,
-    0x7f7a7494, 0xf474a41f,
-  0x7f79e35a, 0xf46e6231, 0x7f7951d2, 0xf468204b, 0x7f78bffb, 0xf461de6d,
-    0x7f782dd6, 0xf45b9c95,
-  0x7f779b62, 0xf4555ac5, 0x7f77089f, 0xf44f18fb, 0x7f76758e, 0xf448d739,
-    0x7f75e22e, 0xf442957e,
-  0x7f754e80, 0xf43c53cb, 0x7f74ba83, 0xf436121e, 0x7f742637, 0xf42fd079,
-    0x7f73919d, 0xf4298edc,
-  0x7f72fcb4, 0xf4234d45, 0x7f72677c, 0xf41d0bb6, 0x7f71d1f6, 0xf416ca2e,
-    0x7f713c21, 0xf41088ae,
-  0x7f70a5fe, 0xf40a4735, 0x7f700f8c, 0xf40405c3, 0x7f6f78cb, 0xf3fdc459,
-    0x7f6ee1bc, 0xf3f782f6,
-  0x7f6e4a5e, 0xf3f1419a, 0x7f6db2b1, 0xf3eb0046, 0x7f6d1ab6, 0xf3e4bef9,
-    0x7f6c826d, 0xf3de7db4,
-  0x7f6be9d4, 0xf3d83c77, 0x7f6b50ed, 0xf3d1fb40, 0x7f6ab7b8, 0xf3cbba12,
-    0x7f6a1e34, 0xf3c578eb,
-  0x7f698461, 0xf3bf37cb, 0x7f68ea40, 0xf3b8f6b3, 0x7f684fd0, 0xf3b2b5a3,
-    0x7f67b512, 0xf3ac749a,
-  0x7f671a05, 0xf3a63398, 0x7f667ea9, 0xf39ff29f, 0x7f65e2ff, 0xf399b1ad,
-    0x7f654706, 0xf39370c2,
-  0x7f64aabf, 0xf38d2fe0, 0x7f640e29, 0xf386ef05, 0x7f637144, 0xf380ae31,
-    0x7f62d411, 0xf37a6d66,
-  0x7f62368f, 0xf3742ca2, 0x7f6198bf, 0xf36debe6, 0x7f60faa0, 0xf367ab31,
-    0x7f605c33, 0xf3616a85,
-  0x7f5fbd77, 0xf35b29e0, 0x7f5f1e6c, 0xf354e943, 0x7f5e7f13, 0xf34ea8ae,
-    0x7f5ddf6b, 0xf3486820,
-  0x7f5d3f75, 0xf342279b, 0x7f5c9f30, 0xf33be71d, 0x7f5bfe9d, 0xf335a6a7,
-    0x7f5b5dbb, 0xf32f6639,
-  0x7f5abc8a, 0xf32925d3, 0x7f5a1b0b, 0xf322e575, 0x7f59793e, 0xf31ca51f,
-    0x7f58d721, 0xf31664d1,
-  0x7f5834b7, 0xf310248a, 0x7f5791fd, 0xf309e44c, 0x7f56eef5, 0xf303a416,
-    0x7f564b9f, 0xf2fd63e8,
-  0x7f55a7fa, 0xf2f723c1, 0x7f550407, 0xf2f0e3a3, 0x7f545fc5, 0xf2eaa38d,
-    0x7f53bb34, 0xf2e4637f,
-  0x7f531655, 0xf2de2379, 0x7f527127, 0xf2d7e37b, 0x7f51cbab, 0xf2d1a385,
-    0x7f5125e0, 0xf2cb6398,
-  0x7f507fc7, 0xf2c523b2, 0x7f4fd95f, 0xf2bee3d5, 0x7f4f32a9, 0xf2b8a400,
-    0x7f4e8ba4, 0xf2b26433,
-  0x7f4de451, 0xf2ac246e, 0x7f4d3caf, 0xf2a5e4b1, 0x7f4c94be, 0xf29fa4fd,
-    0x7f4bec7f, 0xf2996551,
-  0x7f4b43f2, 0xf29325ad, 0x7f4a9b16, 0xf28ce612, 0x7f49f1eb, 0xf286a67e,
-    0x7f494872, 0xf28066f4,
-  0x7f489eaa, 0xf27a2771, 0x7f47f494, 0xf273e7f7, 0x7f474a30, 0xf26da885,
-    0x7f469f7d, 0xf267691b,
-  0x7f45f47b, 0xf26129ba, 0x7f45492b, 0xf25aea61, 0x7f449d8c, 0xf254ab11,
-    0x7f43f19f, 0xf24e6bc9,
-  0x7f434563, 0xf2482c8a, 0x7f4298d9, 0xf241ed53, 0x7f41ec01, 0xf23bae24,
-    0x7f413ed9, 0xf2356efe,
-  0x7f409164, 0xf22f2fe1, 0x7f3fe3a0, 0xf228f0cc, 0x7f3f358d, 0xf222b1c0,
-    0x7f3e872c, 0xf21c72bc,
-  0x7f3dd87c, 0xf21633c0, 0x7f3d297e, 0xf20ff4ce, 0x7f3c7a31, 0xf209b5e4,
-    0x7f3bca96, 0xf2037702,
-  0x7f3b1aad, 0xf1fd3829, 0x7f3a6a75, 0xf1f6f959, 0x7f39b9ee, 0xf1f0ba91,
-    0x7f390919, 0xf1ea7bd2,
-  0x7f3857f6, 0xf1e43d1c, 0x7f37a684, 0xf1ddfe6f, 0x7f36f4c3, 0xf1d7bfca,
-    0x7f3642b4, 0xf1d1812e,
-  0x7f359057, 0xf1cb429a, 0x7f34ddab, 0xf1c50410, 0x7f342ab1, 0xf1bec58e,
-    0x7f337768, 0xf1b88715,
-  0x7f32c3d1, 0xf1b248a5, 0x7f320feb, 0xf1ac0a3e, 0x7f315bb7, 0xf1a5cbdf,
-    0x7f30a734, 0xf19f8d89,
-  0x7f2ff263, 0xf1994f3d, 0x7f2f3d44, 0xf19310f9, 0x7f2e87d6, 0xf18cd2be,
-    0x7f2dd219, 0xf186948c,
-  0x7f2d1c0e, 0xf1805662, 0x7f2c65b5, 0xf17a1842, 0x7f2baf0d, 0xf173da2b,
-    0x7f2af817, 0xf16d9c1d,
-  0x7f2a40d2, 0xf1675e17, 0x7f29893f, 0xf161201b, 0x7f28d15d, 0xf15ae228,
-    0x7f28192d, 0xf154a43d,
-  0x7f2760af, 0xf14e665c, 0x7f26a7e2, 0xf1482884, 0x7f25eec7, 0xf141eab5,
-    0x7f25355d, 0xf13bacef,
-  0x7f247ba5, 0xf1356f32, 0x7f23c19e, 0xf12f317e, 0x7f230749, 0xf128f3d4,
-    0x7f224ca6, 0xf122b632,
-  0x7f2191b4, 0xf11c789a, 0x7f20d674, 0xf1163b0b, 0x7f201ae5, 0xf10ffd85,
-    0x7f1f5f08, 0xf109c009,
-  0x7f1ea2dc, 0xf1038295, 0x7f1de662, 0xf0fd452b, 0x7f1d299a, 0xf0f707ca,
-    0x7f1c6c83, 0xf0f0ca72,
-  0x7f1baf1e, 0xf0ea8d24, 0x7f1af16a, 0xf0e44fdf, 0x7f1a3368, 0xf0de12a3,
-    0x7f197518, 0xf0d7d571,
-  0x7f18b679, 0xf0d19848, 0x7f17f78c, 0xf0cb5b28, 0x7f173850, 0xf0c51e12,
-    0x7f1678c6, 0xf0bee105,
-  0x7f15b8ee, 0xf0b8a401, 0x7f14f8c7, 0xf0b26707, 0x7f143852, 0xf0ac2a16,
-    0x7f13778e, 0xf0a5ed2f,
-  0x7f12b67c, 0xf09fb051, 0x7f11f51c, 0xf099737d, 0x7f11336d, 0xf09336b2,
-    0x7f107170, 0xf08cf9f1,
-  0x7f0faf25, 0xf086bd39, 0x7f0eec8b, 0xf080808b, 0x7f0e29a3, 0xf07a43e7,
-    0x7f0d666c, 0xf074074c,
-  0x7f0ca2e7, 0xf06dcaba, 0x7f0bdf14, 0xf0678e32, 0x7f0b1af2, 0xf06151b4,
-    0x7f0a5682, 0xf05b1540,
-  0x7f0991c4, 0xf054d8d5, 0x7f08ccb7, 0xf04e9c73, 0x7f08075c, 0xf048601c,
-    0x7f0741b2, 0xf04223ce,
-  0x7f067bba, 0xf03be78a, 0x7f05b574, 0xf035ab4f, 0x7f04eedf, 0xf02f6f1f,
-    0x7f0427fc, 0xf02932f8,
-  0x7f0360cb, 0xf022f6da, 0x7f02994b, 0xf01cbac7, 0x7f01d17d, 0xf0167ebd,
-    0x7f010961, 0xf01042be,
-  0x7f0040f6, 0xf00a06c8, 0x7eff783d, 0xf003cadc, 0x7efeaf36, 0xeffd8ef9,
-    0x7efde5e0, 0xeff75321,
-  0x7efd1c3c, 0xeff11753, 0x7efc524a, 0xefeadb8e, 0x7efb8809, 0xefe49fd3,
-    0x7efabd7a, 0xefde6423,
-  0x7ef9f29d, 0xefd8287c, 0x7ef92771, 0xefd1ecdf, 0x7ef85bf7, 0xefcbb14c,
-    0x7ef7902f, 0xefc575c3,
-  0x7ef6c418, 0xefbf3a45, 0x7ef5f7b3, 0xefb8fed0, 0x7ef52b00, 0xefb2c365,
-    0x7ef45dfe, 0xefac8804,
-  0x7ef390ae, 0xefa64cae, 0x7ef2c310, 0xefa01161, 0x7ef1f524, 0xef99d61f,
-    0x7ef126e9, 0xef939ae6,
-  0x7ef05860, 0xef8d5fb8, 0x7eef8988, 0xef872494, 0x7eeeba62, 0xef80e97a,
-    0x7eedeaee, 0xef7aae6b,
-  0x7eed1b2c, 0xef747365, 0x7eec4b1b, 0xef6e386a, 0x7eeb7abc, 0xef67fd79,
-    0x7eeaaa0f, 0xef61c292,
-  0x7ee9d914, 0xef5b87b5, 0x7ee907ca, 0xef554ce3, 0x7ee83632, 0xef4f121b,
-    0x7ee7644c, 0xef48d75d,
-  0x7ee69217, 0xef429caa, 0x7ee5bf94, 0xef3c6201, 0x7ee4ecc3, 0xef362762,
-    0x7ee419a3, 0xef2feccd,
-  0x7ee34636, 0xef29b243, 0x7ee2727a, 0xef2377c4, 0x7ee19e6f, 0xef1d3d4e,
-    0x7ee0ca17, 0xef1702e4,
-  0x7edff570, 0xef10c883, 0x7edf207b, 0xef0a8e2d, 0x7ede4b38, 0xef0453e2,
-    0x7edd75a6, 0xeefe19a1,
-  0x7edc9fc6, 0xeef7df6a, 0x7edbc998, 0xeef1a53e, 0x7edaf31c, 0xeeeb6b1c,
-    0x7eda1c51, 0xeee53105,
-  0x7ed94538, 0xeedef6f9, 0x7ed86dd1, 0xeed8bcf7, 0x7ed7961c, 0xeed28300,
-    0x7ed6be18, 0xeecc4913,
-  0x7ed5e5c6, 0xeec60f31, 0x7ed50d26, 0xeebfd55a, 0x7ed43438, 0xeeb99b8d,
-    0x7ed35afb, 0xeeb361cb,
-  0x7ed28171, 0xeead2813, 0x7ed1a798, 0xeea6ee66, 0x7ed0cd70, 0xeea0b4c4,
-    0x7ecff2fb, 0xee9a7b2d,
-  0x7ecf1837, 0xee9441a0, 0x7ece3d25, 0xee8e081e, 0x7ecd61c5, 0xee87cea7,
-    0x7ecc8617, 0xee81953b,
-  0x7ecbaa1a, 0xee7b5bd9, 0x7ecacdd0, 0xee752283, 0x7ec9f137, 0xee6ee937,
-    0x7ec9144f, 0xee68aff6,
-  0x7ec8371a, 0xee6276bf, 0x7ec75996, 0xee5c3d94, 0x7ec67bc5, 0xee560473,
-    0x7ec59da5, 0xee4fcb5e,
-  0x7ec4bf36, 0xee499253, 0x7ec3e07a, 0xee435953, 0x7ec3016f, 0xee3d205e,
-    0x7ec22217, 0xee36e775,
-  0x7ec14270, 0xee30ae96, 0x7ec0627a, 0xee2a75c2, 0x7ebf8237, 0xee243cf9,
-    0x7ebea1a6, 0xee1e043b,
-  0x7ebdc0c6, 0xee17cb88, 0x7ebcdf98, 0xee1192e0, 0x7ebbfe1c, 0xee0b5a43,
-    0x7ebb1c52, 0xee0521b2,
-  0x7eba3a39, 0xedfee92b, 0x7eb957d2, 0xedf8b0b0, 0x7eb8751e, 0xedf2783f,
-    0x7eb7921b, 0xedec3fda,
-  0x7eb6aeca, 0xede60780, 0x7eb5cb2a, 0xeddfcf31, 0x7eb4e73d, 0xedd996ed,
-    0x7eb40301, 0xedd35eb5,
-  0x7eb31e78, 0xedcd2687, 0x7eb239a0, 0xedc6ee65, 0x7eb1547a, 0xedc0b64e,
-    0x7eb06f05, 0xedba7e43,
-  0x7eaf8943, 0xedb44642, 0x7eaea333, 0xedae0e4d, 0x7eadbcd4, 0xeda7d664,
-    0x7eacd627, 0xeda19e85,
-  0x7eabef2c, 0xed9b66b2, 0x7eab07e3, 0xed952eea, 0x7eaa204c, 0xed8ef72e,
-    0x7ea93867, 0xed88bf7d,
-  0x7ea85033, 0xed8287d7, 0x7ea767b2, 0xed7c503d, 0x7ea67ee2, 0xed7618ae,
-    0x7ea595c4, 0xed6fe12b,
-  0x7ea4ac58, 0xed69a9b3, 0x7ea3c29e, 0xed637246, 0x7ea2d896, 0xed5d3ae5,
-    0x7ea1ee3f, 0xed570390,
-  0x7ea1039b, 0xed50cc46, 0x7ea018a8, 0xed4a9507, 0x7e9f2d68, 0xed445dd5,
-    0x7e9e41d9, 0xed3e26ad,
-  0x7e9d55fc, 0xed37ef91, 0x7e9c69d1, 0xed31b881, 0x7e9b7d58, 0xed2b817d,
-    0x7e9a9091, 0xed254a84,
-  0x7e99a37c, 0xed1f1396, 0x7e98b618, 0xed18dcb5, 0x7e97c867, 0xed12a5df,
-    0x7e96da67, 0xed0c6f14,
-  0x7e95ec1a, 0xed063856, 0x7e94fd7e, 0xed0001a3, 0x7e940e94, 0xecf9cafb,
-    0x7e931f5c, 0xecf39460,
-  0x7e922fd6, 0xeced5dd0, 0x7e914002, 0xece7274c, 0x7e904fe0, 0xece0f0d4,
-    0x7e8f5f70, 0xecdaba67,
-  0x7e8e6eb2, 0xecd48407, 0x7e8d7da6, 0xecce4db2, 0x7e8c8c4b, 0xecc81769,
-    0x7e8b9aa3, 0xecc1e12c,
-  0x7e8aa8ac, 0xecbbaafb, 0x7e89b668, 0xecb574d5, 0x7e88c3d5, 0xecaf3ebc,
-    0x7e87d0f5, 0xeca908ae,
-  0x7e86ddc6, 0xeca2d2ad, 0x7e85ea49, 0xec9c9cb7, 0x7e84f67e, 0xec9666cd,
-    0x7e840265, 0xec9030f0,
-  0x7e830dff, 0xec89fb1e, 0x7e82194a, 0xec83c558, 0x7e812447, 0xec7d8f9e,
-    0x7e802ef6, 0xec7759f1,
-  0x7e7f3957, 0xec71244f, 0x7e7e436a, 0xec6aeeba, 0x7e7d4d2f, 0xec64b930,
-    0x7e7c56a5, 0xec5e83b3,
-  0x7e7b5fce, 0xec584e41, 0x7e7a68a9, 0xec5218dc, 0x7e797136, 0xec4be383,
-    0x7e787975, 0xec45ae36,
-  0x7e778166, 0xec3f78f6, 0x7e768908, 0xec3943c1, 0x7e75905d, 0xec330e99,
-    0x7e749764, 0xec2cd97d,
-  0x7e739e1d, 0xec26a46d, 0x7e72a488, 0xec206f69, 0x7e71aaa4, 0xec1a3a72,
-    0x7e70b073, 0xec140587,
-  0x7e6fb5f4, 0xec0dd0a8, 0x7e6ebb27, 0xec079bd6, 0x7e6dc00c, 0xec01670f,
-    0x7e6cc4a2, 0xebfb3256,
-  0x7e6bc8eb, 0xebf4fda8, 0x7e6acce6, 0xebeec907, 0x7e69d093, 0xebe89472,
-    0x7e68d3f2, 0xebe25fea,
-  0x7e67d703, 0xebdc2b6e, 0x7e66d9c6, 0xebd5f6fe, 0x7e65dc3b, 0xebcfc29b,
-    0x7e64de62, 0xebc98e45,
-  0x7e63e03b, 0xebc359fb, 0x7e62e1c6, 0xebbd25bd, 0x7e61e303, 0xebb6f18c,
-    0x7e60e3f2, 0xebb0bd67,
-  0x7e5fe493, 0xebaa894f, 0x7e5ee4e6, 0xeba45543, 0x7e5de4ec, 0xeb9e2144,
-    0x7e5ce4a3, 0xeb97ed52,
-  0x7e5be40c, 0xeb91b96c, 0x7e5ae328, 0xeb8b8593, 0x7e59e1f5, 0xeb8551c6,
-    0x7e58e075, 0xeb7f1e06,
-  0x7e57dea7, 0xeb78ea52, 0x7e56dc8a, 0xeb72b6ac, 0x7e55da20, 0xeb6c8312,
-    0x7e54d768, 0xeb664f84,
-  0x7e53d462, 0xeb601c04, 0x7e52d10e, 0xeb59e890, 0x7e51cd6c, 0xeb53b529,
-    0x7e50c97c, 0xeb4d81ce,
-  0x7e4fc53e, 0xeb474e81, 0x7e4ec0b2, 0xeb411b40, 0x7e4dbbd9, 0xeb3ae80c,
-    0x7e4cb6b1, 0xeb34b4e4,
-  0x7e4bb13c, 0xeb2e81ca, 0x7e4aab78, 0xeb284ebc, 0x7e49a567, 0xeb221bbb,
-    0x7e489f08, 0xeb1be8c8,
-  0x7e47985b, 0xeb15b5e1, 0x7e469160, 0xeb0f8307, 0x7e458a17, 0xeb095039,
-    0x7e448281, 0xeb031d79,
-  0x7e437a9c, 0xeafceac6, 0x7e427269, 0xeaf6b81f, 0x7e4169e9, 0xeaf08586,
-    0x7e40611b, 0xeaea52fa,
-  0x7e3f57ff, 0xeae4207a, 0x7e3e4e95, 0xeaddee08, 0x7e3d44dd, 0xead7bba3,
-    0x7e3c3ad7, 0xead1894b,
-  0x7e3b3083, 0xeacb56ff, 0x7e3a25e2, 0xeac524c1, 0x7e391af3, 0xeabef290,
-    0x7e380fb5, 0xeab8c06c,
-  0x7e37042a, 0xeab28e56, 0x7e35f851, 0xeaac5c4c, 0x7e34ec2b, 0xeaa62a4f,
-    0x7e33dfb6, 0xea9ff860,
-  0x7e32d2f4, 0xea99c67e, 0x7e31c5e3, 0xea9394a9, 0x7e30b885, 0xea8d62e1,
-    0x7e2faad9, 0xea873127,
-  0x7e2e9cdf, 0xea80ff7a, 0x7e2d8e97, 0xea7acdda, 0x7e2c8002, 0xea749c47,
-    0x7e2b711f, 0xea6e6ac2,
-  0x7e2a61ed, 0xea683949, 0x7e29526e, 0xea6207df, 0x7e2842a2, 0xea5bd681,
-    0x7e273287, 0xea55a531,
-  0x7e26221f, 0xea4f73ee, 0x7e251168, 0xea4942b9, 0x7e240064, 0xea431191,
-    0x7e22ef12, 0xea3ce077,
-  0x7e21dd73, 0xea36af69, 0x7e20cb85, 0xea307e6a, 0x7e1fb94a, 0xea2a4d78,
-    0x7e1ea6c1, 0xea241c93,
-  0x7e1d93ea, 0xea1debbb, 0x7e1c80c5, 0xea17baf2, 0x7e1b6d53, 0xea118a35,
-    0x7e1a5992, 0xea0b5987,
-  0x7e194584, 0xea0528e5, 0x7e183128, 0xe9fef852, 0x7e171c7f, 0xe9f8c7cc,
-    0x7e160787, 0xe9f29753,
-  0x7e14f242, 0xe9ec66e8, 0x7e13dcaf, 0xe9e6368b, 0x7e12c6ce, 0xe9e0063c,
-    0x7e11b0a0, 0xe9d9d5fa,
-  0x7e109a24, 0xe9d3a5c5, 0x7e0f835a, 0xe9cd759f, 0x7e0e6c42, 0xe9c74586,
-    0x7e0d54dc, 0xe9c1157a,
-  0x7e0c3d29, 0xe9bae57d, 0x7e0b2528, 0xe9b4b58d, 0x7e0a0cd9, 0xe9ae85ab,
-    0x7e08f43d, 0xe9a855d7,
-  0x7e07db52, 0xe9a22610, 0x7e06c21a, 0xe99bf658, 0x7e05a894, 0xe995c6ad,
-    0x7e048ec1, 0xe98f9710,
-  0x7e0374a0, 0xe9896781, 0x7e025a31, 0xe98337ff, 0x7e013f74, 0xe97d088c,
-    0x7e00246a, 0xe976d926,
-  0x7dff0911, 0xe970a9ce, 0x7dfded6c, 0xe96a7a85, 0x7dfcd178, 0xe9644b49,
-    0x7dfbb537, 0xe95e1c1b,
-  0x7dfa98a8, 0xe957ecfb, 0x7df97bcb, 0xe951bde9, 0x7df85ea0, 0xe94b8ee5,
-    0x7df74128, 0xe9455fef,
-  0x7df62362, 0xe93f3107, 0x7df5054f, 0xe939022d, 0x7df3e6ee, 0xe932d361,
-    0x7df2c83f, 0xe92ca4a4,
-  0x7df1a942, 0xe92675f4, 0x7df089f8, 0xe9204752, 0x7def6a60, 0xe91a18bf,
-    0x7dee4a7a, 0xe913ea39,
-  0x7ded2a47, 0xe90dbbc2, 0x7dec09c6, 0xe9078d59, 0x7deae8f7, 0xe9015efe,
-    0x7de9c7da, 0xe8fb30b1,
-  0x7de8a670, 0xe8f50273, 0x7de784b9, 0xe8eed443, 0x7de662b3, 0xe8e8a621,
-    0x7de54060, 0xe8e2780d,
-  0x7de41dc0, 0xe8dc4a07, 0x7de2fad1, 0xe8d61c10, 0x7de1d795, 0xe8cfee27,
-    0x7de0b40b, 0xe8c9c04c,
-  0x7ddf9034, 0xe8c39280, 0x7dde6c0f, 0xe8bd64c2, 0x7ddd479d, 0xe8b73712,
-    0x7ddc22dc, 0xe8b10971,
-  0x7ddafdce, 0xe8aadbde, 0x7dd9d873, 0xe8a4ae59, 0x7dd8b2ca, 0xe89e80e3,
-    0x7dd78cd3, 0xe898537b,
-  0x7dd6668f, 0xe8922622, 0x7dd53ffc, 0xe88bf8d7, 0x7dd4191d, 0xe885cb9a,
-    0x7dd2f1f0, 0xe87f9e6c,
-  0x7dd1ca75, 0xe879714d, 0x7dd0a2ac, 0xe873443c, 0x7dcf7a96, 0xe86d173a,
-    0x7dce5232, 0xe866ea46,
-  0x7dcd2981, 0xe860bd61, 0x7dcc0082, 0xe85a908a, 0x7dcad736, 0xe85463c2,
-    0x7dc9ad9c, 0xe84e3708,
-  0x7dc883b4, 0xe8480a5d, 0x7dc7597f, 0xe841ddc1, 0x7dc62efc, 0xe83bb133,
-    0x7dc5042b, 0xe83584b4,
-  0x7dc3d90d, 0xe82f5844, 0x7dc2ada2, 0xe8292be3, 0x7dc181e8, 0xe822ff90,
-    0x7dc055e2, 0xe81cd34b,
-  0x7dbf298d, 0xe816a716, 0x7dbdfceb, 0xe8107aef, 0x7dbccffc, 0xe80a4ed7,
-    0x7dbba2bf, 0xe80422ce,
-  0x7dba7534, 0xe7fdf6d4, 0x7db9475c, 0xe7f7cae8, 0x7db81936, 0xe7f19f0c,
-    0x7db6eac3, 0xe7eb733e,
-  0x7db5bc02, 0xe7e5477f, 0x7db48cf4, 0xe7df1bcf, 0x7db35d98, 0xe7d8f02d,
-    0x7db22def, 0xe7d2c49b,
-  0x7db0fdf8, 0xe7cc9917, 0x7dafcdb3, 0xe7c66da3, 0x7dae9d21, 0xe7c0423d,
-    0x7dad6c42, 0xe7ba16e7,
-  0x7dac3b15, 0xe7b3eb9f, 0x7dab099a, 0xe7adc066, 0x7da9d7d2, 0xe7a7953d,
-    0x7da8a5bc, 0xe7a16a22,
-  0x7da77359, 0xe79b3f16, 0x7da640a9, 0xe795141a, 0x7da50dab, 0xe78ee92c,
-    0x7da3da5f, 0xe788be4e,
-  0x7da2a6c6, 0xe782937e, 0x7da172df, 0xe77c68be, 0x7da03eab, 0xe7763e0d,
-    0x7d9f0a29, 0xe770136b,
-  0x7d9dd55a, 0xe769e8d8, 0x7d9ca03e, 0xe763be55, 0x7d9b6ad3, 0xe75d93e0,
-    0x7d9a351c, 0xe757697b,
-  0x7d98ff17, 0xe7513f25, 0x7d97c8c4, 0xe74b14de, 0x7d969224, 0xe744eaa6,
-    0x7d955b37, 0xe73ec07e,
-  0x7d9423fc, 0xe7389665, 0x7d92ec73, 0xe7326c5b, 0x7d91b49e, 0xe72c4260,
-    0x7d907c7a, 0xe7261875,
-  0x7d8f4409, 0xe71fee99, 0x7d8e0b4b, 0xe719c4cd, 0x7d8cd240, 0xe7139b10,
-    0x7d8b98e6, 0xe70d7162,
-  0x7d8a5f40, 0xe70747c4, 0x7d89254c, 0xe7011e35, 0x7d87eb0a, 0xe6faf4b5,
-    0x7d86b07c, 0xe6f4cb45,
-  0x7d85759f, 0xe6eea1e4, 0x7d843a76, 0xe6e87893, 0x7d82fefe, 0xe6e24f51,
-    0x7d81c33a, 0xe6dc261f,
-  0x7d808728, 0xe6d5fcfc, 0x7d7f4ac8, 0xe6cfd3e9, 0x7d7e0e1c, 0xe6c9aae5,
-    0x7d7cd121, 0xe6c381f1,
-  0x7d7b93da, 0xe6bd590d, 0x7d7a5645, 0xe6b73038, 0x7d791862, 0xe6b10772,
-    0x7d77da32, 0xe6aadebc,
-  0x7d769bb5, 0xe6a4b616, 0x7d755cea, 0xe69e8d80, 0x7d741dd2, 0xe69864f9,
-    0x7d72de6d, 0xe6923c82,
-  0x7d719eba, 0xe68c141a, 0x7d705eba, 0xe685ebc2, 0x7d6f1e6c, 0xe67fc37a,
-    0x7d6dddd2, 0xe6799b42,
-  0x7d6c9ce9, 0xe6737319, 0x7d6b5bb4, 0xe66d4b01, 0x7d6a1a31, 0xe66722f7,
-    0x7d68d860, 0xe660fafe,
-  0x7d679642, 0xe65ad315, 0x7d6653d7, 0xe654ab3b, 0x7d65111f, 0xe64e8371,
-    0x7d63ce19, 0xe6485bb7,
-  0x7d628ac6, 0xe642340d, 0x7d614725, 0xe63c0c73, 0x7d600338, 0xe635e4e9,
-    0x7d5ebefc, 0xe62fbd6e,
-  0x7d5d7a74, 0xe6299604, 0x7d5c359e, 0xe6236ea9, 0x7d5af07b, 0xe61d475e,
-    0x7d59ab0a, 0xe6172024,
-  0x7d58654d, 0xe610f8f9, 0x7d571f41, 0xe60ad1de, 0x7d55d8e9, 0xe604aad4,
-    0x7d549243, 0xe5fe83d9,
-  0x7d534b50, 0xe5f85cef, 0x7d520410, 0xe5f23614, 0x7d50bc82, 0xe5ec0f4a,
-    0x7d4f74a7, 0xe5e5e88f,
-  0x7d4e2c7f, 0xe5dfc1e5, 0x7d4ce409, 0xe5d99b4b, 0x7d4b9b46, 0xe5d374c1,
-    0x7d4a5236, 0xe5cd4e47,
-  0x7d4908d9, 0xe5c727dd, 0x7d47bf2e, 0xe5c10184, 0x7d467536, 0xe5badb3a,
-    0x7d452af1, 0xe5b4b501,
-  0x7d43e05e, 0xe5ae8ed8, 0x7d42957e, 0xe5a868bf, 0x7d414a51, 0xe5a242b7,
-    0x7d3ffed7, 0xe59c1cbf,
-  0x7d3eb30f, 0xe595f6d7, 0x7d3d66fa, 0xe58fd0ff, 0x7d3c1a98, 0xe589ab38,
-    0x7d3acde9, 0xe5838581,
-  0x7d3980ec, 0xe57d5fda, 0x7d3833a2, 0xe5773a44, 0x7d36e60b, 0xe57114be,
-    0x7d359827, 0xe56aef49,
-  0x7d3449f5, 0xe564c9e3, 0x7d32fb76, 0xe55ea48f, 0x7d31acaa, 0xe5587f4a,
-    0x7d305d91, 0xe5525a17,
-  0x7d2f0e2b, 0xe54c34f3, 0x7d2dbe77, 0xe5460fe0, 0x7d2c6e76, 0xe53feade,
-    0x7d2b1e28, 0xe539c5ec,
-  0x7d29cd8c, 0xe533a10a, 0x7d287ca4, 0xe52d7c39, 0x7d272b6e, 0xe5275779,
-    0x7d25d9eb, 0xe52132c9,
-  0x7d24881b, 0xe51b0e2a, 0x7d2335fe, 0xe514e99b, 0x7d21e393, 0xe50ec51d,
-    0x7d2090db, 0xe508a0b0,
-  0x7d1f3dd6, 0xe5027c53, 0x7d1dea84, 0xe4fc5807, 0x7d1c96e5, 0xe4f633cc,
-    0x7d1b42f9, 0xe4f00fa1,
-  0x7d19eebf, 0xe4e9eb87, 0x7d189a38, 0xe4e3c77d, 0x7d174564, 0xe4dda385,
-    0x7d15f043, 0xe4d77f9d,
-  0x7d149ad5, 0xe4d15bc6, 0x7d134519, 0xe4cb37ff, 0x7d11ef11, 0xe4c5144a,
-    0x7d1098bb, 0xe4bef0a5,
-  0x7d0f4218, 0xe4b8cd11, 0x7d0deb28, 0xe4b2a98e, 0x7d0c93eb, 0xe4ac861b,
-    0x7d0b3c60, 0xe4a662ba,
-  0x7d09e489, 0xe4a03f69, 0x7d088c64, 0xe49a1c29, 0x7d0733f3, 0xe493f8fb,
-    0x7d05db34, 0xe48dd5dd,
-  0x7d048228, 0xe487b2d0, 0x7d0328cf, 0xe4818fd4, 0x7d01cf29, 0xe47b6ce9,
-    0x7d007535, 0xe4754a0e,
-  0x7cff1af5, 0xe46f2745, 0x7cfdc068, 0xe469048d, 0x7cfc658d, 0xe462e1e6,
-    0x7cfb0a65, 0xe45cbf50,
-  0x7cf9aef0, 0xe4569ccb, 0x7cf8532f, 0xe4507a57, 0x7cf6f720, 0xe44a57f4,
-    0x7cf59ac4, 0xe44435a2,
-  0x7cf43e1a, 0xe43e1362, 0x7cf2e124, 0xe437f132, 0x7cf183e1, 0xe431cf14,
-    0x7cf02651, 0xe42bad07,
-  0x7ceec873, 0xe4258b0a, 0x7ced6a49, 0xe41f6920, 0x7cec0bd1, 0xe4194746,
-    0x7ceaad0c, 0xe413257d,
-  0x7ce94dfb, 0xe40d03c6, 0x7ce7ee9c, 0xe406e220, 0x7ce68ef0, 0xe400c08b,
-    0x7ce52ef7, 0xe3fa9f08,
-  0x7ce3ceb2, 0xe3f47d96, 0x7ce26e1f, 0xe3ee5c35, 0x7ce10d3f, 0xe3e83ae5,
-    0x7cdfac12, 0xe3e219a7,
-  0x7cde4a98, 0xe3dbf87a, 0x7cdce8d1, 0xe3d5d75e, 0x7cdb86bd, 0xe3cfb654,
-    0x7cda245c, 0xe3c9955b,
-  0x7cd8c1ae, 0xe3c37474, 0x7cd75eb3, 0xe3bd539e, 0x7cd5fb6a, 0xe3b732d9,
-    0x7cd497d5, 0xe3b11226,
-  0x7cd333f3, 0xe3aaf184, 0x7cd1cfc4, 0xe3a4d0f4, 0x7cd06b48, 0xe39eb075,
-    0x7ccf067f, 0xe3989008,
-  0x7ccda169, 0xe3926fad, 0x7ccc3c06, 0xe38c4f63, 0x7ccad656, 0xe3862f2a,
-    0x7cc97059, 0xe3800f03,
-  0x7cc80a0f, 0xe379eeed, 0x7cc6a378, 0xe373ceea, 0x7cc53c94, 0xe36daef7,
-    0x7cc3d563, 0xe3678f17,
-  0x7cc26de5, 0xe3616f48, 0x7cc1061a, 0xe35b4f8b, 0x7cbf9e03, 0xe3552fdf,
-    0x7cbe359e, 0xe34f1045,
-  0x7cbcccec, 0xe348f0bd, 0x7cbb63ee, 0xe342d146, 0x7cb9faa2, 0xe33cb1e1,
-    0x7cb8910a, 0xe336928e,
-  0x7cb72724, 0xe330734d, 0x7cb5bcf2, 0xe32a541d, 0x7cb45272, 0xe3243500,
-    0x7cb2e7a6, 0xe31e15f4,
-  0x7cb17c8d, 0xe317f6fa, 0x7cb01127, 0xe311d811, 0x7caea574, 0xe30bb93b,
-    0x7cad3974, 0xe3059a76,
-  0x7cabcd28, 0xe2ff7bc3, 0x7caa608e, 0xe2f95d23, 0x7ca8f3a7, 0xe2f33e94,
-    0x7ca78674, 0xe2ed2017,
-  0x7ca618f3, 0xe2e701ac, 0x7ca4ab26, 0xe2e0e352, 0x7ca33d0c, 0xe2dac50b,
-    0x7ca1cea5, 0xe2d4a6d6,
-  0x7ca05ff1, 0xe2ce88b3, 0x7c9ef0f0, 0xe2c86aa2, 0x7c9d81a3, 0xe2c24ca2,
-    0x7c9c1208, 0xe2bc2eb5,
-  0x7c9aa221, 0xe2b610da, 0x7c9931ec, 0xe2aff311, 0x7c97c16b, 0xe2a9d55a,
-    0x7c96509d, 0xe2a3b7b5,
-  0x7c94df83, 0xe29d9a23, 0x7c936e1b, 0xe2977ca2, 0x7c91fc66, 0xe2915f34,
-    0x7c908a65, 0xe28b41d7,
-  0x7c8f1817, 0xe285248d, 0x7c8da57c, 0xe27f0755, 0x7c8c3294, 0xe278ea30,
-    0x7c8abf5f, 0xe272cd1c,
-  0x7c894bde, 0xe26cb01b, 0x7c87d810, 0xe266932c, 0x7c8663f4, 0xe260764f,
-    0x7c84ef8c, 0xe25a5984,
-  0x7c837ad8, 0xe2543ccc, 0x7c8205d6, 0xe24e2026, 0x7c809088, 0xe2480393,
-    0x7c7f1aed, 0xe241e711,
-  0x7c7da505, 0xe23bcaa2, 0x7c7c2ed0, 0xe235ae46, 0x7c7ab84e, 0xe22f91fc,
-    0x7c794180, 0xe22975c4,
-  0x7c77ca65, 0xe223599e, 0x7c7652fd, 0xe21d3d8b, 0x7c74db48, 0xe217218b,
-    0x7c736347, 0xe211059d,
-  0x7c71eaf9, 0xe20ae9c1, 0x7c70725e, 0xe204cdf8, 0x7c6ef976, 0xe1feb241,
-    0x7c6d8041, 0xe1f8969d,
-  0x7c6c06c0, 0xe1f27b0b, 0x7c6a8cf2, 0xe1ec5f8c, 0x7c6912d7, 0xe1e64420,
-    0x7c679870, 0xe1e028c6,
-  0x7c661dbc, 0xe1da0d7e, 0x7c64a2bb, 0xe1d3f24a, 0x7c63276d, 0xe1cdd727,
-    0x7c61abd3, 0xe1c7bc18,
-  0x7c602fec, 0xe1c1a11b, 0x7c5eb3b8, 0xe1bb8631, 0x7c5d3737, 0xe1b56b59,
-    0x7c5bba6a, 0xe1af5094,
-  0x7c5a3d50, 0xe1a935e2, 0x7c58bfe9, 0xe1a31b42, 0x7c574236, 0xe19d00b6,
-    0x7c55c436, 0xe196e63c,
-  0x7c5445e9, 0xe190cbd4, 0x7c52c74f, 0xe18ab180, 0x7c514869, 0xe184973e,
-    0x7c4fc936, 0xe17e7d0f,
-  0x7c4e49b7, 0xe17862f3, 0x7c4cc9ea, 0xe17248ea, 0x7c4b49d2, 0xe16c2ef4,
-    0x7c49c96c, 0xe1661510,
-  0x7c4848ba, 0xe15ffb3f, 0x7c46c7bb, 0xe159e182, 0x7c45466f, 0xe153c7d7,
-    0x7c43c4d7, 0xe14dae3f,
-  0x7c4242f2, 0xe14794ba, 0x7c40c0c1, 0xe1417b48, 0x7c3f3e42, 0xe13b61e9,
-    0x7c3dbb78, 0xe135489d,
-  0x7c3c3860, 0xe12f2f63, 0x7c3ab4fc, 0xe129163d, 0x7c39314b, 0xe122fd2a,
-    0x7c37ad4e, 0xe11ce42a,
-  0x7c362904, 0xe116cb3d, 0x7c34a46d, 0xe110b263, 0x7c331f8a, 0xe10a999c,
-    0x7c319a5a, 0xe10480e9,
-  0x7c3014de, 0xe0fe6848, 0x7c2e8f15, 0xe0f84fbb, 0x7c2d08ff, 0xe0f23740,
-    0x7c2b829d, 0xe0ec1ed9,
-  0x7c29fbee, 0xe0e60685, 0x7c2874f3, 0xe0dfee44, 0x7c26edab, 0xe0d9d616,
-    0x7c256616, 0xe0d3bdfc,
-  0x7c23de35, 0xe0cda5f5, 0x7c225607, 0xe0c78e01, 0x7c20cd8d, 0xe0c17620,
-    0x7c1f44c6, 0xe0bb5e53,
-  0x7c1dbbb3, 0xe0b54698, 0x7c1c3253, 0xe0af2ef2, 0x7c1aa8a6, 0xe0a9175e,
-    0x7c191ead, 0xe0a2ffde,
-  0x7c179467, 0xe09ce871, 0x7c1609d5, 0xe096d117, 0x7c147ef6, 0xe090b9d1,
-    0x7c12f3cb, 0xe08aa29f,
-  0x7c116853, 0xe0848b7f, 0x7c0fdc8f, 0xe07e7473, 0x7c0e507e, 0xe0785d7b,
-    0x7c0cc421, 0xe0724696,
-  0x7c0b3777, 0xe06c2fc4, 0x7c09aa80, 0xe0661906, 0x7c081d3d, 0xe060025c,
-    0x7c068fae, 0xe059ebc5,
-  0x7c0501d2, 0xe053d541, 0x7c0373a9, 0xe04dbed1, 0x7c01e534, 0xe047a875,
-    0x7c005673, 0xe041922c,
-  0x7bfec765, 0xe03b7bf6, 0x7bfd380a, 0xe03565d5, 0x7bfba863, 0xe02f4fc6,
-    0x7bfa1870, 0xe02939cc,
-  0x7bf88830, 0xe02323e5, 0x7bf6f7a4, 0xe01d0e12, 0x7bf566cb, 0xe016f852,
-    0x7bf3d5a6, 0xe010e2a7,
-  0x7bf24434, 0xe00acd0e, 0x7bf0b276, 0xe004b78a, 0x7bef206b, 0xdffea219,
-    0x7bed8e14, 0xdff88cbc,
-  0x7bebfb70, 0xdff27773, 0x7bea6880, 0xdfec623e, 0x7be8d544, 0xdfe64d1c,
-    0x7be741bb, 0xdfe0380e,
-  0x7be5ade6, 0xdfda2314, 0x7be419c4, 0xdfd40e2e, 0x7be28556, 0xdfcdf95c,
-    0x7be0f09b, 0xdfc7e49d,
-  0x7bdf5b94, 0xdfc1cff3, 0x7bddc641, 0xdfbbbb5c, 0x7bdc30a1, 0xdfb5a6d9,
-    0x7bda9ab5, 0xdfaf926a,
-  0x7bd9047c, 0xdfa97e0f, 0x7bd76df7, 0xdfa369c8, 0x7bd5d726, 0xdf9d5595,
-    0x7bd44008, 0xdf974176,
-  0x7bd2a89e, 0xdf912d6b, 0x7bd110e8, 0xdf8b1974, 0x7bcf78e5, 0xdf850591,
-    0x7bcde095, 0xdf7ef1c2,
-  0x7bcc47fa, 0xdf78de07, 0x7bcaaf12, 0xdf72ca60, 0x7bc915dd, 0xdf6cb6cd,
-    0x7bc77c5d, 0xdf66a34e,
-  0x7bc5e290, 0xdf608fe4, 0x7bc44876, 0xdf5a7c8d, 0x7bc2ae10, 0xdf54694b,
-    0x7bc1135e, 0xdf4e561c,
-  0x7bbf7860, 0xdf484302, 0x7bbddd15, 0xdf422ffd, 0x7bbc417e, 0xdf3c1d0b,
-    0x7bbaa59a, 0xdf360a2d,
-  0x7bb9096b, 0xdf2ff764, 0x7bb76cef, 0xdf29e4af, 0x7bb5d026, 0xdf23d20e,
-    0x7bb43311, 0xdf1dbf82,
-  0x7bb295b0, 0xdf17ad0a, 0x7bb0f803, 0xdf119aa6, 0x7baf5a09, 0xdf0b8856,
-    0x7badbbc3, 0xdf05761b,
-  0x7bac1d31, 0xdeff63f4, 0x7baa7e53, 0xdef951e2, 0x7ba8df28, 0xdef33fe3,
-    0x7ba73fb1, 0xdeed2dfa,
-  0x7ba59fee, 0xdee71c24, 0x7ba3ffde, 0xdee10a63, 0x7ba25f82, 0xdedaf8b7,
-    0x7ba0beda, 0xded4e71f,
-  0x7b9f1de6, 0xdeced59b, 0x7b9d7ca5, 0xdec8c42c, 0x7b9bdb18, 0xdec2b2d1,
-    0x7b9a393f, 0xdebca18b,
-  0x7b989719, 0xdeb69059, 0x7b96f4a8, 0xdeb07f3c, 0x7b9551ea, 0xdeaa6e34,
-    0x7b93aee0, 0xdea45d40,
-  0x7b920b89, 0xde9e4c60, 0x7b9067e7, 0xde983b95, 0x7b8ec3f8, 0xde922adf,
-    0x7b8d1fbd, 0xde8c1a3e,
-  0x7b8b7b36, 0xde8609b1, 0x7b89d662, 0xde7ff938, 0x7b883143, 0xde79e8d5,
-    0x7b868bd7, 0xde73d886,
-  0x7b84e61f, 0xde6dc84b, 0x7b83401b, 0xde67b826, 0x7b8199ca, 0xde61a815,
-    0x7b7ff32e, 0xde5b9819,
-  0x7b7e4c45, 0xde558831, 0x7b7ca510, 0xde4f785f, 0x7b7afd8f, 0xde4968a1,
-    0x7b7955c2, 0xde4358f8,
-  0x7b77ada8, 0xde3d4964, 0x7b760542, 0xde3739e4, 0x7b745c91, 0xde312a7a,
-    0x7b72b393, 0xde2b1b24,
-  0x7b710a49, 0xde250be3, 0x7b6f60b2, 0xde1efcb7, 0x7b6db6d0, 0xde18eda0,
-    0x7b6c0ca2, 0xde12de9e,
-  0x7b6a6227, 0xde0ccfb1, 0x7b68b760, 0xde06c0d9, 0x7b670c4d, 0xde00b216,
-    0x7b6560ee, 0xddfaa367,
-  0x7b63b543, 0xddf494ce, 0x7b62094c, 0xddee8649, 0x7b605d09, 0xdde877da,
-    0x7b5eb079, 0xdde26980,
-  0x7b5d039e, 0xdddc5b3b, 0x7b5b5676, 0xddd64d0a, 0x7b59a902, 0xddd03eef,
-    0x7b57fb42, 0xddca30e9,
-  0x7b564d36, 0xddc422f8, 0x7b549ede, 0xddbe151d, 0x7b52f03a, 0xddb80756,
-    0x7b51414a, 0xddb1f9a4,
-  0x7b4f920e, 0xddabec08, 0x7b4de286, 0xdda5de81, 0x7b4c32b1, 0xdd9fd10f,
-    0x7b4a8291, 0xdd99c3b2,
-  0x7b48d225, 0xdd93b66a, 0x7b47216c, 0xdd8da938, 0x7b457068, 0xdd879c1b,
-    0x7b43bf17, 0xdd818f13,
-  0x7b420d7a, 0xdd7b8220, 0x7b405b92, 0xdd757543, 0x7b3ea95d, 0xdd6f687b,
-    0x7b3cf6dc, 0xdd695bc9,
-  0x7b3b4410, 0xdd634f2b, 0x7b3990f7, 0xdd5d42a3, 0x7b37dd92, 0xdd573631,
-    0x7b3629e1, 0xdd5129d4,
-  0x7b3475e5, 0xdd4b1d8c, 0x7b32c19c, 0xdd451159, 0x7b310d07, 0xdd3f053c,
-    0x7b2f5826, 0xdd38f935,
-  0x7b2da2fa, 0xdd32ed43, 0x7b2bed81, 0xdd2ce166, 0x7b2a37bc, 0xdd26d59f,
-    0x7b2881ac, 0xdd20c9ed,
-  0x7b26cb4f, 0xdd1abe51, 0x7b2514a6, 0xdd14b2ca, 0x7b235db2, 0xdd0ea759,
-    0x7b21a671, 0xdd089bfe,
-  0x7b1feee5, 0xdd0290b8, 0x7b1e370d, 0xdcfc8588, 0x7b1c7ee8, 0xdcf67a6d,
-    0x7b1ac678, 0xdcf06f68,
-  0x7b190dbc, 0xdcea6478, 0x7b1754b3, 0xdce4599e, 0x7b159b5f, 0xdcde4eda,
-    0x7b13e1bf, 0xdcd8442b,
-  0x7b1227d3, 0xdcd23993, 0x7b106d9b, 0xdccc2f0f, 0x7b0eb318, 0xdcc624a2,
-    0x7b0cf848, 0xdcc01a4a,
-  0x7b0b3d2c, 0xdcba1008, 0x7b0981c5, 0xdcb405dc, 0x7b07c612, 0xdcadfbc5,
-    0x7b060a12, 0xdca7f1c5,
-  0x7b044dc7, 0xdca1e7da, 0x7b029130, 0xdc9bde05, 0x7b00d44d, 0xdc95d446,
-    0x7aff171e, 0xdc8fca9c,
-  0x7afd59a4, 0xdc89c109, 0x7afb9bdd, 0xdc83b78b, 0x7af9ddcb, 0xdc7dae23,
-    0x7af81f6c, 0xdc77a4d2,
-  0x7af660c2, 0xdc719b96, 0x7af4a1cc, 0xdc6b9270, 0x7af2e28b, 0xdc658960,
-    0x7af122fd, 0xdc5f8066,
-  0x7aef6323, 0xdc597781, 0x7aeda2fe, 0xdc536eb3, 0x7aebe28d, 0xdc4d65fb,
-    0x7aea21d0, 0xdc475d59,
-  0x7ae860c7, 0xdc4154cd, 0x7ae69f73, 0xdc3b4c57, 0x7ae4ddd2, 0xdc3543f7,
-    0x7ae31be6, 0xdc2f3bad,
-  0x7ae159ae, 0xdc293379, 0x7adf972a, 0xdc232b5c, 0x7addd45b, 0xdc1d2354,
-    0x7adc113f, 0xdc171b63,
-  0x7ada4dd8, 0xdc111388, 0x7ad88a25, 0xdc0b0bc2, 0x7ad6c626, 0xdc050414,
-    0x7ad501dc, 0xdbfefc7b,
-  0x7ad33d45, 0xdbf8f4f8, 0x7ad17863, 0xdbf2ed8c, 0x7acfb336, 0xdbece636,
-    0x7acdedbc, 0xdbe6def6,
-  0x7acc27f7, 0xdbe0d7cd, 0x7aca61e6, 0xdbdad0b9, 0x7ac89b89, 0xdbd4c9bc,
-    0x7ac6d4e0, 0xdbcec2d6,
-  0x7ac50dec, 0xdbc8bc06, 0x7ac346ac, 0xdbc2b54c, 0x7ac17f20, 0xdbbcaea8,
-    0x7abfb749, 0xdbb6a81b,
-  0x7abdef25, 0xdbb0a1a4, 0x7abc26b7, 0xdbaa9b43, 0x7aba5dfc, 0xdba494f9,
-    0x7ab894f6, 0xdb9e8ec6,
-  0x7ab6cba4, 0xdb9888a8, 0x7ab50206, 0xdb9282a2, 0x7ab3381d, 0xdb8c7cb1,
-    0x7ab16de7, 0xdb8676d8,
-  0x7aafa367, 0xdb807114, 0x7aadd89a, 0xdb7a6b68, 0x7aac0d82, 0xdb7465d1,
-    0x7aaa421e, 0xdb6e6052,
-  0x7aa8766f, 0xdb685ae9, 0x7aa6aa74, 0xdb625596, 0x7aa4de2d, 0xdb5c505a,
-    0x7aa3119a, 0xdb564b35,
-  0x7aa144bc, 0xdb504626, 0x7a9f7793, 0xdb4a412e, 0x7a9daa1d, 0xdb443c4c,
-    0x7a9bdc5c, 0xdb3e3781,
-  0x7a9a0e50, 0xdb3832cd, 0x7a983ff7, 0xdb322e30, 0x7a967153, 0xdb2c29a9,
-    0x7a94a264, 0xdb262539,
-  0x7a92d329, 0xdb2020e0, 0x7a9103a2, 0xdb1a1c9d, 0x7a8f33d0, 0xdb141871,
-    0x7a8d63b2, 0xdb0e145c,
-  0x7a8b9348, 0xdb08105e, 0x7a89c293, 0xdb020c77, 0x7a87f192, 0xdafc08a6,
-    0x7a862046, 0xdaf604ec,
-  0x7a844eae, 0xdaf00149, 0x7a827ccb, 0xdae9fdbd, 0x7a80aa9c, 0xdae3fa48,
-    0x7a7ed821, 0xdaddf6ea,
-  0x7a7d055b, 0xdad7f3a2, 0x7a7b3249, 0xdad1f072, 0x7a795eec, 0xdacbed58,
-    0x7a778b43, 0xdac5ea56,
-  0x7a75b74f, 0xdabfe76a, 0x7a73e30f, 0xdab9e495, 0x7a720e84, 0xdab3e1d8,
-    0x7a7039ad, 0xdaaddf31,
-  0x7a6e648a, 0xdaa7dca1, 0x7a6c8f1c, 0xdaa1da29, 0x7a6ab963, 0xda9bd7c7,
-    0x7a68e35e, 0xda95d57d,
-  0x7a670d0d, 0xda8fd349, 0x7a653671, 0xda89d12d, 0x7a635f8a, 0xda83cf28,
-    0x7a618857, 0xda7dcd3a,
-  0x7a5fb0d8, 0xda77cb63, 0x7a5dd90e, 0xda71c9a3, 0x7a5c00f9, 0xda6bc7fa,
-    0x7a5a2898, 0xda65c669,
-  0x7a584feb, 0xda5fc4ef, 0x7a5676f3, 0xda59c38c, 0x7a549db0, 0xda53c240,
-    0x7a52c421, 0xda4dc10b,
-  0x7a50ea47, 0xda47bfee, 0x7a4f1021, 0xda41bee8, 0x7a4d35b0, 0xda3bbdf9,
-    0x7a4b5af3, 0xda35bd22,
-  0x7a497feb, 0xda2fbc61, 0x7a47a498, 0xda29bbb9, 0x7a45c8f9, 0xda23bb27,
-    0x7a43ed0e, 0xda1dbaad,
-  0x7a4210d8, 0xda17ba4a, 0x7a403457, 0xda11b9ff, 0x7a3e578b, 0xda0bb9cb,
-    0x7a3c7a73, 0xda05b9ae,
-  0x7a3a9d0f, 0xd9ffb9a9, 0x7a38bf60, 0xd9f9b9bb, 0x7a36e166, 0xd9f3b9e5,
-    0x7a350321, 0xd9edba26,
-  0x7a332490, 0xd9e7ba7f, 0x7a3145b3, 0xd9e1baef, 0x7a2f668c, 0xd9dbbb77,
-    0x7a2d8719, 0xd9d5bc16,
-  0x7a2ba75a, 0xd9cfbccd, 0x7a29c750, 0xd9c9bd9b, 0x7a27e6fb, 0xd9c3be81,
-    0x7a26065b, 0xd9bdbf7e,
-  0x7a24256f, 0xd9b7c094, 0x7a224437, 0xd9b1c1c0, 0x7a2062b5, 0xd9abc305,
-    0x7a1e80e7, 0xd9a5c461,
-  0x7a1c9ece, 0xd99fc5d4, 0x7a1abc69, 0xd999c75f, 0x7a18d9b9, 0xd993c902,
-    0x7a16f6be, 0xd98dcabd,
-  0x7a151378, 0xd987cc90, 0x7a132fe6, 0xd981ce7a, 0x7a114c09, 0xd97bd07c,
-    0x7a0f67e0, 0xd975d295,
-  0x7a0d836d, 0xd96fd4c7, 0x7a0b9eae, 0xd969d710, 0x7a09b9a4, 0xd963d971,
-    0x7a07d44e, 0xd95ddbea,
-  0x7a05eead, 0xd957de7a, 0x7a0408c1, 0xd951e123, 0x7a02228a, 0xd94be3e3,
-    0x7a003c07, 0xd945e6bb,
-  0x79fe5539, 0xd93fe9ab, 0x79fc6e20, 0xd939ecb3, 0x79fa86bc, 0xd933efd3,
-    0x79f89f0c, 0xd92df30b,
-  0x79f6b711, 0xd927f65b, 0x79f4cecb, 0xd921f9c3, 0x79f2e63a, 0xd91bfd43,
-    0x79f0fd5d, 0xd91600da,
-  0x79ef1436, 0xd910048a, 0x79ed2ac3, 0xd90a0852, 0x79eb4105, 0xd9040c32,
-    0x79e956fb, 0xd8fe1029,
-  0x79e76ca7, 0xd8f81439, 0x79e58207, 0xd8f21861, 0x79e3971c, 0xd8ec1ca1,
-    0x79e1abe6, 0xd8e620fa,
-  0x79dfc064, 0xd8e0256a, 0x79ddd498, 0xd8da29f2, 0x79dbe880, 0xd8d42e93,
-    0x79d9fc1d, 0xd8ce334c,
-  0x79d80f6f, 0xd8c8381d, 0x79d62276, 0xd8c23d06, 0x79d43532, 0xd8bc4207,
-    0x79d247a2, 0xd8b64720,
-  0x79d059c8, 0xd8b04c52, 0x79ce6ba2, 0xd8aa519c, 0x79cc7d31, 0xd8a456ff,
-    0x79ca8e75, 0xd89e5c79,
-  0x79c89f6e, 0xd898620c, 0x79c6b01b, 0xd89267b7, 0x79c4c07e, 0xd88c6d7b,
-    0x79c2d095, 0xd8867356,
-  0x79c0e062, 0xd880794b, 0x79beefe3, 0xd87a7f57, 0x79bcff19, 0xd874857c,
-    0x79bb0e04, 0xd86e8bb9,
-  0x79b91ca4, 0xd868920f, 0x79b72af9, 0xd862987d, 0x79b53903, 0xd85c9f04,
-    0x79b346c2, 0xd856a5a3,
-  0x79b15435, 0xd850ac5a, 0x79af615e, 0xd84ab32a, 0x79ad6e3c, 0xd844ba13,
-    0x79ab7ace, 0xd83ec114,
-  0x79a98715, 0xd838c82d, 0x79a79312, 0xd832cf5f, 0x79a59ec3, 0xd82cd6aa,
-    0x79a3aa29, 0xd826de0d,
-  0x79a1b545, 0xd820e589, 0x799fc015, 0xd81aed1d, 0x799dca9a, 0xd814f4ca,
-    0x799bd4d4, 0xd80efc8f,
-  0x7999dec4, 0xd809046e, 0x7997e868, 0xd8030c64, 0x7995f1c1, 0xd7fd1474,
-    0x7993facf, 0xd7f71c9c,
-  0x79920392, 0xd7f124dd, 0x79900c0a, 0xd7eb2d37, 0x798e1438, 0xd7e535a9,
-    0x798c1c1a, 0xd7df3e34,
-  0x798a23b1, 0xd7d946d8, 0x79882afd, 0xd7d34f94, 0x798631ff, 0xd7cd586a,
-    0x798438b5, 0xd7c76158,
-  0x79823f20, 0xd7c16a5f, 0x79804541, 0xd7bb737f, 0x797e4b16, 0xd7b57cb7,
-    0x797c50a1, 0xd7af8609,
-  0x797a55e0, 0xd7a98f73, 0x79785ad5, 0xd7a398f6, 0x79765f7f, 0xd79da293,
-    0x797463de, 0xd797ac48,
-  0x797267f2, 0xd791b616, 0x79706bbb, 0xd78bbffc, 0x796e6f39, 0xd785c9fc,
-    0x796c726c, 0xd77fd415,
-  0x796a7554, 0xd779de47, 0x796877f1, 0xd773e892, 0x79667a44, 0xd76df2f6,
-    0x79647c4c, 0xd767fd72,
-  0x79627e08, 0xd7620808, 0x79607f7a, 0xd75c12b7, 0x795e80a1, 0xd7561d7f,
-    0x795c817d, 0xd7502860,
-  0x795a820e, 0xd74a335b, 0x79588255, 0xd7443e6e, 0x79568250, 0xd73e499a,
-    0x79548201, 0xd73854e0,
-  0x79528167, 0xd732603f, 0x79508082, 0xd72c6bb6, 0x794e7f52, 0xd7267748,
-    0x794c7dd7, 0xd72082f2,
-  0x794a7c12, 0xd71a8eb5, 0x79487a01, 0xd7149a92, 0x794677a6, 0xd70ea688,
-    0x79447500, 0xd708b297,
-  0x79427210, 0xd702bec0, 0x79406ed4, 0xd6fccb01, 0x793e6b4e, 0xd6f6d75d,
-    0x793c677d, 0xd6f0e3d1,
-  0x793a6361, 0xd6eaf05f, 0x79385efa, 0xd6e4fd06, 0x79365a49, 0xd6df09c6,
-    0x7934554d, 0xd6d916a0,
-  0x79325006, 0xd6d32393, 0x79304a74, 0xd6cd30a0, 0x792e4497, 0xd6c73dc6,
-    0x792c3e70, 0xd6c14b05,
-  0x792a37fe, 0xd6bb585e, 0x79283141, 0xd6b565d0, 0x79262a3a, 0xd6af735c,
-    0x792422e8, 0xd6a98101,
-  0x79221b4b, 0xd6a38ec0, 0x79201363, 0xd69d9c98, 0x791e0b31, 0xd697aa8a,
-    0x791c02b4, 0xd691b895,
-  0x7919f9ec, 0xd68bc6ba, 0x7917f0d9, 0xd685d4f9, 0x7915e77c, 0xd67fe351,
-    0x7913ddd4, 0xd679f1c2,
-  0x7911d3e2, 0xd674004e, 0x790fc9a4, 0xd66e0ef2, 0x790dbf1d, 0xd6681db1,
-    0x790bb44a, 0xd6622c89,
-  0x7909a92d, 0xd65c3b7b, 0x79079dc5, 0xd6564a87, 0x79059212, 0xd65059ac,
-    0x79038615, 0xd64a68eb,
-  0x790179cd, 0xd6447844, 0x78ff6d3b, 0xd63e87b6, 0x78fd605d, 0xd6389742,
-    0x78fb5336, 0xd632a6e8,
-  0x78f945c3, 0xd62cb6a8, 0x78f73806, 0xd626c681, 0x78f529fe, 0xd620d675,
-    0x78f31bac, 0xd61ae682,
-  0x78f10d0f, 0xd614f6a9, 0x78eefe28, 0xd60f06ea, 0x78eceef6, 0xd6091745,
-    0x78eadf79, 0xd60327b9,
-  0x78e8cfb2, 0xd5fd3848, 0x78e6bfa0, 0xd5f748f0, 0x78e4af44, 0xd5f159b3,
-    0x78e29e9d, 0xd5eb6a8f,
-  0x78e08dab, 0xd5e57b85, 0x78de7c6f, 0xd5df8c96, 0x78dc6ae8, 0xd5d99dc0,
-    0x78da5917, 0xd5d3af04,
-  0x78d846fb, 0xd5cdc062, 0x78d63495, 0xd5c7d1db, 0x78d421e4, 0xd5c1e36d,
-    0x78d20ee9, 0xd5bbf519,
-  0x78cffba3, 0xd5b606e0, 0x78cde812, 0xd5b018c0, 0x78cbd437, 0xd5aa2abb,
-    0x78c9c012, 0xd5a43cd0,
-  0x78c7aba2, 0xd59e4eff, 0x78c596e7, 0xd5986148, 0x78c381e2, 0xd59273ab,
-    0x78c16c93, 0xd58c8628,
-  0x78bf56f9, 0xd58698c0, 0x78bd4114, 0xd580ab72, 0x78bb2ae5, 0xd57abe3d,
-    0x78b9146c, 0xd574d124,
-  0x78b6fda8, 0xd56ee424, 0x78b4e69a, 0xd568f73f, 0x78b2cf41, 0xd5630a74,
-    0x78b0b79e, 0xd55d1dc3,
-  0x78ae9fb0, 0xd557312d, 0x78ac8778, 0xd55144b0, 0x78aa6ef5, 0xd54b584f,
-    0x78a85628, 0xd5456c07,
-  0x78a63d11, 0xd53f7fda, 0x78a423af, 0xd53993c7, 0x78a20a03, 0xd533a7cf,
-    0x789ff00c, 0xd52dbbf1,
-  0x789dd5cb, 0xd527d02e, 0x789bbb3f, 0xd521e484, 0x7899a06a, 0xd51bf8f6,
-    0x78978549, 0xd5160d82,
-  0x789569df, 0xd5102228, 0x78934e2a, 0xd50a36e9, 0x7891322a, 0xd5044bc4,
-    0x788f15e0, 0xd4fe60ba,
-  0x788cf94c, 0xd4f875ca, 0x788adc6e, 0xd4f28af5, 0x7888bf45, 0xd4eca03a,
-    0x7886a1d1, 0xd4e6b59a,
-  0x78848414, 0xd4e0cb15, 0x7882660c, 0xd4dae0aa, 0x788047ba, 0xd4d4f65a,
-    0x787e291d, 0xd4cf0c24,
-  0x787c0a36, 0xd4c92209, 0x7879eb05, 0xd4c33809, 0x7877cb89, 0xd4bd4e23,
-    0x7875abc3, 0xd4b76458,
-  0x78738bb3, 0xd4b17aa8, 0x78716b59, 0xd4ab9112, 0x786f4ab4, 0xd4a5a798,
-    0x786d29c5, 0xd49fbe37,
-  0x786b088c, 0xd499d4f2, 0x7868e708, 0xd493ebc8, 0x7866c53a, 0xd48e02b8,
-    0x7864a322, 0xd48819c3,
-  0x786280bf, 0xd48230e9, 0x78605e13, 0xd47c4829, 0x785e3b1c, 0xd4765f85,
-    0x785c17db, 0xd47076fb,
-  0x7859f44f, 0xd46a8e8d, 0x7857d079, 0xd464a639, 0x7855ac5a, 0xd45ebe00,
-    0x785387ef, 0xd458d5e2,
-  0x7851633b, 0xd452eddf, 0x784f3e3c, 0xd44d05f6, 0x784d18f4, 0xd4471e29,
-    0x784af361, 0xd4413677,
-  0x7848cd83, 0xd43b4ee0, 0x7846a75c, 0xd4356763, 0x784480ea, 0xd42f8002,
-    0x78425a2f, 0xd42998bc,
-  0x78403329, 0xd423b191, 0x783e0bd9, 0xd41dca81, 0x783be43e, 0xd417e38c,
-    0x7839bc5a, 0xd411fcb2,
-  0x7837942b, 0xd40c15f3, 0x78356bb2, 0xd4062f4f, 0x783342ef, 0xd40048c6,
-    0x783119e2, 0xd3fa6259,
-  0x782ef08b, 0xd3f47c06, 0x782cc6ea, 0xd3ee95cf, 0x782a9cfe, 0xd3e8afb3,
-    0x782872c8, 0xd3e2c9b2,
-  0x78264849, 0xd3dce3cd, 0x78241d7f, 0xd3d6fe03, 0x7821f26b, 0xd3d11853,
-    0x781fc70d, 0xd3cb32c0,
-  0x781d9b65, 0xd3c54d47, 0x781b6f72, 0xd3bf67ea, 0x78194336, 0xd3b982a8,
-    0x781716b0, 0xd3b39d81,
-  0x7814e9df, 0xd3adb876, 0x7812bcc4, 0xd3a7d385, 0x78108f60, 0xd3a1eeb1,
-    0x780e61b1, 0xd39c09f7,
-  0x780c33b8, 0xd396255a, 0x780a0575, 0xd39040d7, 0x7807d6e9, 0xd38a5c70,
-    0x7805a812, 0xd3847824,
-  0x780378f1, 0xd37e93f4, 0x78014986, 0xd378afdf, 0x77ff19d1, 0xd372cbe6,
-    0x77fce9d2, 0xd36ce808,
-  0x77fab989, 0xd3670446, 0x77f888f6, 0xd361209f, 0x77f65819, 0xd35b3d13,
-    0x77f426f2, 0xd35559a4,
-  0x77f1f581, 0xd34f764f, 0x77efc3c5, 0xd3499317, 0x77ed91c0, 0xd343affa,
-    0x77eb5f71, 0xd33dccf8,
-  0x77e92cd9, 0xd337ea12, 0x77e6f9f6, 0xd3320748, 0x77e4c6c9, 0xd32c2499,
-    0x77e29352, 0xd3264206,
-  0x77e05f91, 0xd3205f8f, 0x77de2b86, 0xd31a7d33, 0x77dbf732, 0xd3149af3,
-    0x77d9c293, 0xd30eb8cf,
-  0x77d78daa, 0xd308d6c7, 0x77d55878, 0xd302f4da, 0x77d322fc, 0xd2fd1309,
-    0x77d0ed35, 0xd2f73154,
-  0x77ceb725, 0xd2f14fba, 0x77cc80cb, 0xd2eb6e3c, 0x77ca4a27, 0xd2e58cdb,
-    0x77c81339, 0xd2dfab95,
-  0x77c5dc01, 0xd2d9ca6a, 0x77c3a47f, 0xd2d3e95c, 0x77c16cb4, 0xd2ce0869,
-    0x77bf349f, 0xd2c82793,
-  0x77bcfc3f, 0xd2c246d8, 0x77bac396, 0xd2bc6639, 0x77b88aa3, 0xd2b685b6,
-    0x77b65166, 0xd2b0a54f,
-  0x77b417df, 0xd2aac504, 0x77b1de0f, 0xd2a4e4d5, 0x77afa3f5, 0xd29f04c2,
-    0x77ad6990, 0xd29924cb,
-  0x77ab2ee2, 0xd29344f0, 0x77a8f3ea, 0xd28d6531, 0x77a6b8a9, 0xd287858e,
-    0x77a47d1d, 0xd281a607,
-  0x77a24148, 0xd27bc69c, 0x77a00529, 0xd275e74d, 0x779dc8c0, 0xd270081b,
-    0x779b8c0e, 0xd26a2904,
-  0x77994f11, 0xd2644a0a, 0x779711cb, 0xd25e6b2b, 0x7794d43b, 0xd2588c69,
-    0x77929661, 0xd252adc3,
-  0x7790583e, 0xd24ccf39, 0x778e19d0, 0xd246f0cb, 0x778bdb19, 0xd241127a,
-    0x77899c19, 0xd23b3444,
-  0x77875cce, 0xd235562b, 0x77851d3a, 0xd22f782f, 0x7782dd5c, 0xd2299a4e,
-    0x77809d35, 0xd223bc8a,
-  0x777e5cc3, 0xd21ddee2, 0x777c1c08, 0xd2180156, 0x7779db03, 0xd21223e7,
-    0x777799b5, 0xd20c4694,
-  0x7775581d, 0xd206695d, 0x7773163b, 0xd2008c43, 0x7770d40f, 0xd1faaf45,
-    0x776e919a, 0xd1f4d263,
-  0x776c4edb, 0xd1eef59e, 0x776a0bd3, 0xd1e918f5, 0x7767c880, 0xd1e33c69,
-    0x776584e5, 0xd1dd5ff9,
-  0x776340ff, 0xd1d783a6, 0x7760fcd0, 0xd1d1a76f, 0x775eb857, 0xd1cbcb54,
-    0x775c7395, 0xd1c5ef56,
-  0x775a2e89, 0xd1c01375, 0x7757e933, 0xd1ba37b0, 0x7755a394, 0xd1b45c08,
-    0x77535dab, 0xd1ae807c,
-  0x77511778, 0xd1a8a50d, 0x774ed0fc, 0xd1a2c9ba, 0x774c8a36, 0xd19cee84,
-    0x774a4327, 0xd197136b,
-  0x7747fbce, 0xd191386e, 0x7745b42c, 0xd18b5d8e, 0x77436c40, 0xd18582ca,
-    0x7741240a, 0xd17fa823,
-  0x773edb8b, 0xd179cd99, 0x773c92c2, 0xd173f32c, 0x773a49b0, 0xd16e18db,
-    0x77380054, 0xd1683ea7,
-  0x7735b6af, 0xd1626490, 0x77336cc0, 0xd15c8a95, 0x77312287, 0xd156b0b7,
-    0x772ed805, 0xd150d6f6,
-  0x772c8d3a, 0xd14afd52, 0x772a4225, 0xd14523cb, 0x7727f6c6, 0xd13f4a60,
-    0x7725ab1f, 0xd1397113,
-  0x77235f2d, 0xd13397e2, 0x772112f2, 0xd12dbece, 0x771ec66e, 0xd127e5d7,
-    0x771c79a0, 0xd1220cfc,
-  0x771a2c88, 0xd11c343f, 0x7717df27, 0xd1165b9f, 0x7715917d, 0xd110831b,
-    0x77134389, 0xd10aaab5,
-  0x7710f54c, 0xd104d26b, 0x770ea6c5, 0xd0fefa3f, 0x770c57f5, 0xd0f9222f,
-    0x770a08dc, 0xd0f34a3d,
-  0x7707b979, 0xd0ed7267, 0x770569cc, 0xd0e79aaf, 0x770319d6, 0xd0e1c313,
-    0x7700c997, 0xd0dbeb95,
-  0x76fe790e, 0xd0d61434, 0x76fc283c, 0xd0d03cf0, 0x76f9d721, 0xd0ca65c9,
-    0x76f785bc, 0xd0c48ebf,
-  0x76f5340e, 0xd0beb7d2, 0x76f2e216, 0xd0b8e102, 0x76f08fd5, 0xd0b30a50,
-    0x76ee3d4b, 0xd0ad33ba,
-  0x76ebea77, 0xd0a75d42, 0x76e9975a, 0xd0a186e7, 0x76e743f4, 0xd09bb0aa,
-    0x76e4f044, 0xd095da89,
-  0x76e29c4b, 0xd0900486, 0x76e04808, 0xd08a2ea0, 0x76ddf37c, 0xd08458d7,
-    0x76db9ea7, 0xd07e832c,
-  0x76d94989, 0xd078ad9e, 0x76d6f421, 0xd072d82d, 0x76d49e70, 0xd06d02da,
-    0x76d24876, 0xd0672da3,
-  0x76cff232, 0xd061588b, 0x76cd9ba5, 0xd05b838f, 0x76cb44cf, 0xd055aeb1,
-    0x76c8edb0, 0xd04fd9f1,
-  0x76c69647, 0xd04a054e, 0x76c43e95, 0xd04430c8, 0x76c1e699, 0xd03e5c60,
-    0x76bf8e55, 0xd0388815,
-  0x76bd35c7, 0xd032b3e7, 0x76badcf0, 0xd02cdfd8, 0x76b883d0, 0xd0270be5,
-    0x76b62a66, 0xd0213810,
-  0x76b3d0b4, 0xd01b6459, 0x76b176b8, 0xd01590bf, 0x76af1c72, 0xd00fbd43,
-    0x76acc1e4, 0xd009e9e4,
-  0x76aa670d, 0xd00416a3, 0x76a80bec, 0xcffe4380, 0x76a5b082, 0xcff8707a,
-    0x76a354cf, 0xcff29d92,
-  0x76a0f8d2, 0xcfeccac7, 0x769e9c8d, 0xcfe6f81a, 0x769c3ffe, 0xcfe1258b,
-    0x7699e326, 0xcfdb531a,
-  0x76978605, 0xcfd580c6, 0x7695289b, 0xcfcfae8f, 0x7692cae8, 0xcfc9dc77,
-    0x76906ceb, 0xcfc40a7c,
-  0x768e0ea6, 0xcfbe389f, 0x768bb017, 0xcfb866e0, 0x7689513f, 0xcfb2953f,
-    0x7686f21e, 0xcfacc3bb,
-  0x768492b4, 0xcfa6f255, 0x76823301, 0xcfa1210d, 0x767fd304, 0xcf9b4fe3,
-    0x767d72bf, 0xcf957ed7,
-  0x767b1231, 0xcf8fade9, 0x7678b159, 0xcf89dd18, 0x76765038, 0xcf840c65,
-    0x7673eecf, 0xcf7e3bd1,
-  0x76718d1c, 0xcf786b5a, 0x766f2b20, 0xcf729b01, 0x766cc8db, 0xcf6ccac6,
-    0x766a664d, 0xcf66faa9,
-  0x76680376, 0xcf612aaa, 0x7665a056, 0xcf5b5ac9, 0x76633ced, 0xcf558b06,
-    0x7660d93b, 0xcf4fbb61,
-  0x765e7540, 0xcf49ebda, 0x765c10fc, 0xcf441c71, 0x7659ac6f, 0xcf3e4d26,
-    0x76574798, 0xcf387dfa,
-  0x7654e279, 0xcf32aeeb, 0x76527d11, 0xcf2cdffa, 0x76501760, 0xcf271128,
-    0x764db166, 0xcf214274,
-  0x764b4b23, 0xcf1b73de, 0x7648e497, 0xcf15a566, 0x76467dc2, 0xcf0fd70c,
-    0x764416a4, 0xcf0a08d0,
-  0x7641af3d, 0xcf043ab3, 0x763f478d, 0xcefe6cb3, 0x763cdf94, 0xcef89ed2,
-    0x763a7752, 0xcef2d110,
-  0x76380ec8, 0xceed036b, 0x7635a5f4, 0xcee735e5, 0x76333cd8, 0xcee1687d,
-    0x7630d372, 0xcedb9b33,
-  0x762e69c4, 0xced5ce08, 0x762bffcd, 0xced000fb, 0x7629958c, 0xceca340c,
-    0x76272b03, 0xcec4673c,
-  0x7624c031, 0xcebe9a8a, 0x76225517, 0xceb8cdf7, 0x761fe9b3, 0xceb30181,
-    0x761d7e06, 0xcead352b,
-  0x761b1211, 0xcea768f2, 0x7618a5d3, 0xcea19cd8, 0x7616394c, 0xce9bd0dd,
-    0x7613cc7c, 0xce960500,
-  0x76115f63, 0xce903942, 0x760ef201, 0xce8a6da2, 0x760c8457, 0xce84a220,
-    0x760a1664, 0xce7ed6bd,
-  0x7607a828, 0xce790b79, 0x760539a3, 0xce734053, 0x7602cad5, 0xce6d754c,
-    0x76005bbf, 0xce67aa63,
-  0x75fdec60, 0xce61df99, 0x75fb7cb8, 0xce5c14ed, 0x75f90cc7, 0xce564a60,
-    0x75f69c8d, 0xce507ff2,
-  0x75f42c0b, 0xce4ab5a2, 0x75f1bb40, 0xce44eb71, 0x75ef4a2c, 0xce3f215f,
-    0x75ecd8cf, 0xce39576c,
-  0x75ea672a, 0xce338d97, 0x75e7f53c, 0xce2dc3e1, 0x75e58305, 0xce27fa49,
-    0x75e31086, 0xce2230d0,
-  0x75e09dbd, 0xce1c6777, 0x75de2aac, 0xce169e3b, 0x75dbb753, 0xce10d51f,
-    0x75d943b0, 0xce0b0c21,
-  0x75d6cfc5, 0xce054343, 0x75d45b92, 0xcdff7a83, 0x75d1e715, 0xcdf9b1e2,
-    0x75cf7250, 0xcdf3e95f,
-  0x75ccfd42, 0xcdee20fc, 0x75ca87ec, 0xcde858b8, 0x75c8124d, 0xcde29092,
-    0x75c59c65, 0xcddcc88b,
-  0x75c32634, 0xcdd700a4, 0x75c0afbb, 0xcdd138db, 0x75be38fa, 0xcdcb7131,
-    0x75bbc1ef, 0xcdc5a9a6,
-  0x75b94a9c, 0xcdbfe23a, 0x75b6d301, 0xcdba1aee, 0x75b45b1d, 0xcdb453c0,
-    0x75b1e2f0, 0xcdae8cb1,
-  0x75af6a7b, 0xcda8c5c1, 0x75acf1bd, 0xcda2fef0, 0x75aa78b6, 0xcd9d383f,
-    0x75a7ff67, 0xcd9771ac,
-  0x75a585cf, 0xcd91ab39, 0x75a30bef, 0xcd8be4e4, 0x75a091c6, 0xcd861eaf,
-    0x759e1755, 0xcd805899,
-  0x759b9c9b, 0xcd7a92a2, 0x75992198, 0xcd74ccca, 0x7596a64d, 0xcd6f0711,
-    0x75942ab9, 0xcd694178,
-  0x7591aedd, 0xcd637bfe, 0x758f32b9, 0xcd5db6a3, 0x758cb64c, 0xcd57f167,
-    0x758a3996, 0xcd522c4a,
-  0x7587bc98, 0xcd4c674d, 0x75853f51, 0xcd46a26f, 0x7582c1c2, 0xcd40ddb0,
-    0x758043ea, 0xcd3b1911,
-  0x757dc5ca, 0xcd355491, 0x757b4762, 0xcd2f9030, 0x7578c8b0, 0xcd29cbee,
-    0x757649b7, 0xcd2407cc,
-  0x7573ca75, 0xcd1e43ca, 0x75714aea, 0xcd187fe6, 0x756ecb18, 0xcd12bc22,
-    0x756c4afc, 0xcd0cf87e,
-  0x7569ca99, 0xcd0734f9, 0x756749ec, 0xcd017193, 0x7564c8f8, 0xccfbae4d,
-    0x756247bb, 0xccf5eb26,
-  0x755fc635, 0xccf0281f, 0x755d4467, 0xccea6538, 0x755ac251, 0xcce4a26f,
-    0x75583ff3, 0xccdedfc7,
-  0x7555bd4c, 0xccd91d3d, 0x75533a5c, 0xccd35ad4, 0x7550b725, 0xcccd988a,
-    0x754e33a4, 0xccc7d65f,
-  0x754bafdc, 0xccc21455, 0x75492bcb, 0xccbc5269, 0x7546a772, 0xccb6909e,
-    0x754422d0, 0xccb0cef2,
-  0x75419de7, 0xccab0d65, 0x753f18b4, 0xcca54bf9, 0x753c933a, 0xcc9f8aac,
-    0x753a0d77, 0xcc99c97e,
-  0x7537876c, 0xcc940871, 0x75350118, 0xcc8e4783, 0x75327a7d, 0xcc8886b5,
-    0x752ff399, 0xcc82c607,
-  0x752d6c6c, 0xcc7d0578, 0x752ae4f8, 0xcc774509, 0x75285d3b, 0xcc7184ba,
-    0x7525d536, 0xcc6bc48b,
-  0x75234ce8, 0xcc66047b, 0x7520c453, 0xcc60448c, 0x751e3b75, 0xcc5a84bc,
-    0x751bb24f, 0xcc54c50c,
-  0x751928e0, 0xcc4f057c, 0x75169f2a, 0xcc49460c, 0x7514152b, 0xcc4386bc,
-    0x75118ae4, 0xcc3dc78b,
-  0x750f0054, 0xcc38087b, 0x750c757d, 0xcc32498a, 0x7509ea5d, 0xcc2c8aba,
-    0x75075ef5, 0xcc26cc09,
-  0x7504d345, 0xcc210d79, 0x7502474d, 0xcc1b4f08, 0x74ffbb0d, 0xcc1590b8,
-    0x74fd2e84, 0xcc0fd287,
-  0x74faa1b3, 0xcc0a1477, 0x74f8149a, 0xcc045686, 0x74f58739, 0xcbfe98b6,
-    0x74f2f990, 0xcbf8db05,
-  0x74f06b9e, 0xcbf31d75, 0x74eddd65, 0xcbed6005, 0x74eb4ee3, 0xcbe7a2b5,
-    0x74e8c01a, 0xcbe1e585,
-  0x74e63108, 0xcbdc2876, 0x74e3a1ae, 0xcbd66b86, 0x74e1120c, 0xcbd0aeb7,
-    0x74de8221, 0xcbcaf208,
-  0x74dbf1ef, 0xcbc53579, 0x74d96175, 0xcbbf790a, 0x74d6d0b2, 0xcbb9bcbb,
-    0x74d43fa8, 0xcbb4008d,
-  0x74d1ae55, 0xcbae447f, 0x74cf1cbb, 0xcba88891, 0x74cc8ad8, 0xcba2ccc4,
-    0x74c9f8ad, 0xcb9d1117,
-  0x74c7663a, 0xcb97558a, 0x74c4d380, 0xcb919a1d, 0x74c2407d, 0xcb8bded1,
-    0x74bfad32, 0xcb8623a5,
-  0x74bd199f, 0xcb80689a, 0x74ba85c4, 0xcb7aadaf, 0x74b7f1a1, 0xcb74f2e4,
-    0x74b55d36, 0xcb6f383a,
-  0x74b2c884, 0xcb697db0, 0x74b03389, 0xcb63c347, 0x74ad9e46, 0xcb5e08fe,
-    0x74ab08bb, 0xcb584ed6,
-  0x74a872e8, 0xcb5294ce, 0x74a5dccd, 0xcb4cdae6, 0x74a3466b, 0xcb47211f,
-    0x74a0afc0, 0xcb416779,
-  0x749e18cd, 0xcb3badf3, 0x749b8193, 0xcb35f48d, 0x7498ea11, 0xcb303b49,
-    0x74965246, 0xcb2a8224,
-  0x7493ba34, 0xcb24c921, 0x749121da, 0xcb1f103e, 0x748e8938, 0xcb19577b,
-    0x748bf04d, 0xcb139ed9,
-  0x7489571c, 0xcb0de658, 0x7486bda2, 0xcb082df8, 0x748423e0, 0xcb0275b8,
-    0x748189d7, 0xcafcbd99,
-  0x747eef85, 0xcaf7059a, 0x747c54ec, 0xcaf14dbd, 0x7479ba0b, 0xcaeb9600,
-    0x74771ee2, 0xcae5de64,
-  0x74748371, 0xcae026e8, 0x7471e7b8, 0xcada6f8d, 0x746f4bb8, 0xcad4b853,
-    0x746caf70, 0xcacf013a,
-  0x746a12df, 0xcac94a42, 0x74677608, 0xcac3936b, 0x7464d8e8, 0xcabddcb4,
-    0x74623b80, 0xcab8261e,
-  0x745f9dd1, 0xcab26fa9, 0x745cffda, 0xcaacb955, 0x745a619b, 0xcaa70322,
-    0x7457c314, 0xcaa14d10,
-  0x74552446, 0xca9b971e, 0x74528530, 0xca95e14e, 0x744fe5d2, 0xca902b9f,
-    0x744d462c, 0xca8a7610,
-  0x744aa63f, 0xca84c0a3, 0x7448060a, 0xca7f0b56, 0x7445658d, 0xca79562b,
-    0x7442c4c8, 0xca73a120,
-  0x744023bc, 0xca6dec37, 0x743d8268, 0xca68376e, 0x743ae0cc, 0xca6282c7,
-    0x74383ee9, 0xca5cce40,
-  0x74359cbd, 0xca5719db, 0x7432fa4b, 0xca516597, 0x74305790, 0xca4bb174,
-    0x742db48e, 0xca45fd72,
-  0x742b1144, 0xca404992, 0x74286db3, 0xca3a95d2, 0x7425c9da, 0xca34e234,
-    0x742325b9, 0xca2f2eb6,
-  0x74208150, 0xca297b5a, 0x741ddca0, 0xca23c820, 0x741b37a9, 0xca1e1506,
-    0x74189269, 0xca18620e,
-  0x7415ece2, 0xca12af37, 0x74134714, 0xca0cfc81, 0x7410a0fe, 0xca0749ec,
-    0x740dfaa0, 0xca019779,
-  0x740b53fb, 0xc9fbe527, 0x7408ad0e, 0xc9f632f6, 0x740605d9, 0xc9f080e7,
-    0x74035e5d, 0xc9eacef9,
-  0x7400b69a, 0xc9e51d2d, 0x73fe0e8f, 0xc9df6b81, 0x73fb663c, 0xc9d9b9f7,
-    0x73f8bda2, 0xc9d4088f,
-  0x73f614c0, 0xc9ce5748, 0x73f36b97, 0xc9c8a622, 0x73f0c226, 0xc9c2f51e,
-    0x73ee186e, 0xc9bd443c,
-  0x73eb6e6e, 0xc9b7937a, 0x73e8c426, 0xc9b1e2db, 0x73e61997, 0xc9ac325d,
-    0x73e36ec1, 0xc9a68200,
-  0x73e0c3a3, 0xc9a0d1c5, 0x73de183e, 0xc99b21ab, 0x73db6c91, 0xc99571b3,
-    0x73d8c09d, 0xc98fc1dc,
-  0x73d61461, 0xc98a1227, 0x73d367de, 0xc9846294, 0x73d0bb13, 0xc97eb322,
-    0x73ce0e01, 0xc97903d2,
-  0x73cb60a8, 0xc97354a4, 0x73c8b307, 0xc96da597, 0x73c6051f, 0xc967f6ac,
-    0x73c356ef, 0xc96247e2,
-  0x73c0a878, 0xc95c993a, 0x73bdf9b9, 0xc956eab4, 0x73bb4ab3, 0xc9513c50,
-    0x73b89b66, 0xc94b8e0d,
-  0x73b5ebd1, 0xc945dfec, 0x73b33bf5, 0xc94031ed, 0x73b08bd1, 0xc93a8410,
-    0x73addb67, 0xc934d654,
-  0x73ab2ab4, 0xc92f28ba, 0x73a879bb, 0xc9297b42, 0x73a5c87a, 0xc923cdec,
-    0x73a316f2, 0xc91e20b8,
-  0x73a06522, 0xc91873a5, 0x739db30b, 0xc912c6b5, 0x739b00ad, 0xc90d19e6,
-    0x73984e07, 0xc9076d39,
-  0x73959b1b, 0xc901c0ae, 0x7392e7e6, 0xc8fc1445, 0x7390346b, 0xc8f667fe,
-    0x738d80a8, 0xc8f0bbd9,
-  0x738acc9e, 0xc8eb0fd6, 0x7388184d, 0xc8e563f5, 0x738563b5, 0xc8dfb836,
-    0x7382aed5, 0xc8da0c99,
-  0x737ff9ae, 0xc8d4611d, 0x737d4440, 0xc8ceb5c4, 0x737a8e8a, 0xc8c90a8d,
-    0x7377d88d, 0xc8c35f78,
-  0x73752249, 0xc8bdb485, 0x73726bbe, 0xc8b809b4, 0x736fb4ec, 0xc8b25f06,
-    0x736cfdd2, 0xc8acb479,
-  0x736a4671, 0xc8a70a0e, 0x73678ec9, 0xc8a15fc6, 0x7364d6da, 0xc89bb5a0,
-    0x73621ea4, 0xc8960b9c,
-  0x735f6626, 0xc89061ba, 0x735cad61, 0xc88ab7fa, 0x7359f456, 0xc8850e5d,
-    0x73573b03, 0xc87f64e2,
-  0x73548168, 0xc879bb89, 0x7351c787, 0xc8741252, 0x734f0d5f, 0xc86e693d,
-    0x734c52ef, 0xc868c04b,
-  0x73499838, 0xc863177b, 0x7346dd3a, 0xc85d6ece, 0x734421f6, 0xc857c642,
-    0x7341666a, 0xc8521dd9,
-  0x733eaa96, 0xc84c7593, 0x733bee7c, 0xc846cd6e, 0x7339321b, 0xc841256d,
-    0x73367572, 0xc83b7d8d,
-  0x7333b883, 0xc835d5d0, 0x7330fb4d, 0xc8302e35, 0x732e3dcf, 0xc82a86bd,
-    0x732b800a, 0xc824df67,
-  0x7328c1ff, 0xc81f3834, 0x732603ac, 0xc8199123, 0x73234512, 0xc813ea35,
-    0x73208632, 0xc80e4369,
-  0x731dc70a, 0xc8089cbf, 0x731b079b, 0xc802f638, 0x731847e5, 0xc7fd4fd4,
-    0x731587e8, 0xc7f7a992,
-  0x7312c7a5, 0xc7f20373, 0x7310071a, 0xc7ec5d76, 0x730d4648, 0xc7e6b79c,
-    0x730a8530, 0xc7e111e5,
-  0x7307c3d0, 0xc7db6c50, 0x73050229, 0xc7d5c6de, 0x7302403c, 0xc7d0218e,
-    0x72ff7e07, 0xc7ca7c61,
-  0x72fcbb8c, 0xc7c4d757, 0x72f9f8c9, 0xc7bf3270, 0x72f735c0, 0xc7b98dab,
-    0x72f47270, 0xc7b3e909,
-  0x72f1aed9, 0xc7ae4489, 0x72eeeafb, 0xc7a8a02c, 0x72ec26d6, 0xc7a2fbf3,
-    0x72e9626a, 0xc79d57db,
-  0x72e69db7, 0xc797b3e7, 0x72e3d8be, 0xc7921015, 0x72e1137d, 0xc78c6c67,
-    0x72de4df6, 0xc786c8db,
-  0x72db8828, 0xc7812572, 0x72d8c213, 0xc77b822b, 0x72d5fbb7, 0xc775df08,
-    0x72d33514, 0xc7703c08,
-  0x72d06e2b, 0xc76a992a, 0x72cda6fb, 0xc764f66f, 0x72cadf83, 0xc75f53d7,
-    0x72c817c6, 0xc759b163,
-  0x72c54fc1, 0xc7540f11, 0x72c28775, 0xc74e6ce2, 0x72bfbee3, 0xc748cad6,
-    0x72bcf60a, 0xc74328ed,
-  0x72ba2cea, 0xc73d8727, 0x72b76383, 0xc737e584, 0x72b499d6, 0xc7324404,
-    0x72b1cfe1, 0xc72ca2a7,
-  0x72af05a7, 0xc727016d, 0x72ac3b25, 0xc7216056, 0x72a9705c, 0xc71bbf62,
-    0x72a6a54d, 0xc7161e92,
-  0x72a3d9f7, 0xc7107de4, 0x72a10e5b, 0xc70add5a, 0x729e4277, 0xc7053cf2,
-    0x729b764d, 0xc6ff9cae,
-  0x7298a9dd, 0xc6f9fc8d, 0x7295dd25, 0xc6f45c8f, 0x72931027, 0xc6eebcb5,
-    0x729042e3, 0xc6e91cfd,
-  0x728d7557, 0xc6e37d69, 0x728aa785, 0xc6ddddf8, 0x7287d96c, 0xc6d83eab,
-    0x72850b0d, 0xc6d29f80,
-  0x72823c67, 0xc6cd0079, 0x727f6d7a, 0xc6c76195, 0x727c9e47, 0xc6c1c2d4,
-    0x7279cecd, 0xc6bc2437,
-  0x7276ff0d, 0xc6b685bd, 0x72742f05, 0xc6b0e767, 0x72715eb8, 0xc6ab4933,
-    0x726e8e23, 0xc6a5ab23,
-  0x726bbd48, 0xc6a00d37, 0x7268ec27, 0xc69a6f6e, 0x72661abf, 0xc694d1c8,
-    0x72634910, 0xc68f3446,
-  0x7260771b, 0xc68996e7, 0x725da4df, 0xc683f9ab, 0x725ad25d, 0xc67e5c93,
-    0x7257ff94, 0xc678bf9f,
-  0x72552c85, 0xc67322ce, 0x7252592f, 0xc66d8620, 0x724f8593, 0xc667e996,
-    0x724cb1b0, 0xc6624d30,
-  0x7249dd86, 0xc65cb0ed, 0x72470916, 0xc65714cd, 0x72443460, 0xc65178d1,
-    0x72415f63, 0xc64bdcf9,
-  0x723e8a20, 0xc6464144, 0x723bb496, 0xc640a5b3, 0x7238dec5, 0xc63b0a46,
-    0x723608af, 0xc6356efc,
-  0x72333251, 0xc62fd3d6, 0x72305bae, 0xc62a38d4, 0x722d84c4, 0xc6249df5,
-    0x722aad93, 0xc61f033a,
-  0x7227d61c, 0xc61968a2, 0x7224fe5f, 0xc613ce2f, 0x7222265b, 0xc60e33df,
-    0x721f4e11, 0xc60899b2,
-  0x721c7580, 0xc602ffaa, 0x72199ca9, 0xc5fd65c5, 0x7216c38c, 0xc5f7cc04,
-    0x7213ea28, 0xc5f23267,
-  0x7211107e, 0xc5ec98ee, 0x720e368d, 0xc5e6ff98, 0x720b5c57, 0xc5e16667,
-    0x720881d9, 0xc5dbcd59,
-  0x7205a716, 0xc5d6346f, 0x7202cc0c, 0xc5d09ba9, 0x71fff0bc, 0xc5cb0307,
-    0x71fd1525, 0xc5c56a89,
-  0x71fa3949, 0xc5bfd22e, 0x71f75d25, 0xc5ba39f8, 0x71f480bc, 0xc5b4a1e5,
-    0x71f1a40c, 0xc5af09f7,
-  0x71eec716, 0xc5a9722c, 0x71ebe9da, 0xc5a3da86, 0x71e90c57, 0xc59e4303,
-    0x71e62e8f, 0xc598aba5,
-  0x71e35080, 0xc593146a, 0x71e0722a, 0xc58d7d54, 0x71dd938f, 0xc587e661,
-    0x71dab4ad, 0xc5824f93,
-  0x71d7d585, 0xc57cb8e9, 0x71d4f617, 0xc5772263, 0x71d21662, 0xc5718c00,
-    0x71cf3667, 0xc56bf5c2,
-  0x71cc5626, 0xc5665fa9, 0x71c9759f, 0xc560c9b3, 0x71c694d2, 0xc55b33e2,
-    0x71c3b3bf, 0xc5559e34,
-  0x71c0d265, 0xc55008ab, 0x71bdf0c5, 0xc54a7346, 0x71bb0edf, 0xc544de05,
-    0x71b82cb3, 0xc53f48e9,
-  0x71b54a41, 0xc539b3f1, 0x71b26788, 0xc5341f1d, 0x71af848a, 0xc52e8a6d,
-    0x71aca145, 0xc528f5e1,
-  0x71a9bdba, 0xc523617a, 0x71a6d9e9, 0xc51dcd37, 0x71a3f5d2, 0xc5183919,
-    0x71a11175, 0xc512a51f,
-  0x719e2cd2, 0xc50d1149, 0x719b47e9, 0xc5077d97, 0x719862b9, 0xc501ea0a,
-    0x71957d44, 0xc4fc56a2,
-  0x71929789, 0xc4f6c35d, 0x718fb187, 0xc4f1303d, 0x718ccb3f, 0xc4eb9d42,
-    0x7189e4b2, 0xc4e60a6b,
-  0x7186fdde, 0xc4e077b8, 0x718416c4, 0xc4dae52a, 0x71812f65, 0xc4d552c1,
-    0x717e47bf, 0xc4cfc07c,
-  0x717b5fd3, 0xc4ca2e5b, 0x717877a1, 0xc4c49c5f, 0x71758f29, 0xc4bf0a87,
-    0x7172a66c, 0xc4b978d4,
-  0x716fbd68, 0xc4b3e746, 0x716cd41e, 0xc4ae55dc, 0x7169ea8f, 0xc4a8c497,
-    0x716700b9, 0xc4a33376,
-  0x7164169d, 0xc49da27a, 0x71612c3c, 0xc49811a3, 0x715e4194, 0xc49280f0,
-    0x715b56a7, 0xc48cf062,
-  0x71586b74, 0xc4875ff9, 0x71557ffa, 0xc481cfb4, 0x7152943b, 0xc47c3f94,
-    0x714fa836, 0xc476af98,
-  0x714cbbeb, 0xc4711fc2, 0x7149cf5a, 0xc46b9010, 0x7146e284, 0xc4660083,
-    0x7143f567, 0xc460711b,
-  0x71410805, 0xc45ae1d7, 0x713e1a5c, 0xc45552b8, 0x713b2c6e, 0xc44fc3be,
-    0x71383e3a, 0xc44a34e9,
-  0x71354fc0, 0xc444a639, 0x71326101, 0xc43f17ad, 0x712f71fb, 0xc4398947,
-    0x712c82b0, 0xc433fb05,
-  0x7129931f, 0xc42e6ce8, 0x7126a348, 0xc428def0, 0x7123b32b, 0xc423511d,
-    0x7120c2c8, 0xc41dc36f,
-  0x711dd220, 0xc41835e6, 0x711ae132, 0xc412a882, 0x7117effe, 0xc40d1b42,
-    0x7114fe84, 0xc4078e28,
-  0x71120cc5, 0xc4020133, 0x710f1ac0, 0xc3fc7462, 0x710c2875, 0xc3f6e7b7,
-    0x710935e4, 0xc3f15b31,
-  0x7106430e, 0xc3ebced0, 0x71034ff2, 0xc3e64294, 0x71005c90, 0xc3e0b67d,
-    0x70fd68e9, 0xc3db2a8b,
-  0x70fa74fc, 0xc3d59ebe, 0x70f780c9, 0xc3d01316, 0x70f48c50, 0xc3ca8793,
-    0x70f19792, 0xc3c4fc36,
-  0x70eea28e, 0xc3bf70fd, 0x70ebad45, 0xc3b9e5ea, 0x70e8b7b5, 0xc3b45afc,
-    0x70e5c1e1, 0xc3aed034,
-  0x70e2cbc6, 0xc3a94590, 0x70dfd566, 0xc3a3bb12, 0x70dcdec0, 0xc39e30b8,
-    0x70d9e7d5, 0xc398a685,
-  0x70d6f0a4, 0xc3931c76, 0x70d3f92d, 0xc38d928d, 0x70d10171, 0xc38808c9,
-    0x70ce096f, 0xc3827f2a,
-  0x70cb1128, 0xc37cf5b0, 0x70c8189b, 0xc3776c5c, 0x70c51fc8, 0xc371e32d,
-    0x70c226b0, 0xc36c5a24,
-  0x70bf2d53, 0xc366d140, 0x70bc33b0, 0xc3614881, 0x70b939c7, 0xc35bbfe8,
-    0x70b63f99, 0xc3563774,
-  0x70b34525, 0xc350af26, 0x70b04a6b, 0xc34b26fc, 0x70ad4f6d, 0xc3459ef9,
-    0x70aa5428, 0xc340171b,
-  0x70a7589f, 0xc33a8f62, 0x70a45ccf, 0xc33507cf, 0x70a160ba, 0xc32f8061,
-    0x709e6460, 0xc329f919,
-  0x709b67c0, 0xc32471f7, 0x70986adb, 0xc31eeaf9, 0x70956db1, 0xc3196422,
-    0x70927041, 0xc313dd70,
-  0x708f728b, 0xc30e56e4, 0x708c7490, 0xc308d07d, 0x70897650, 0xc3034a3c,
-    0x708677ca, 0xc2fdc420,
-  0x708378ff, 0xc2f83e2a, 0x708079ee, 0xc2f2b85a, 0x707d7a98, 0xc2ed32af,
-    0x707a7afd, 0xc2e7ad2a,
-  0x70777b1c, 0xc2e227cb, 0x70747af6, 0xc2dca291, 0x70717a8a, 0xc2d71d7e,
-    0x706e79d9, 0xc2d1988f,
-  0x706b78e3, 0xc2cc13c7, 0x706877a7, 0xc2c68f24, 0x70657626, 0xc2c10aa7,
-    0x70627460, 0xc2bb8650,
-  0x705f7255, 0xc2b6021f, 0x705c7004, 0xc2b07e14, 0x70596d6d, 0xc2aafa2e,
-    0x70566a92, 0xc2a5766e,
-  0x70536771, 0xc29ff2d4, 0x7050640b, 0xc29a6f60, 0x704d6060, 0xc294ec12,
-    0x704a5c6f, 0xc28f68e9,
-  0x70475839, 0xc289e5e7, 0x704453be, 0xc284630a, 0x70414efd, 0xc27ee054,
-    0x703e49f8, 0xc2795dc3,
-  0x703b44ad, 0xc273db58, 0x70383f1d, 0xc26e5913, 0x70353947, 0xc268d6f5,
-    0x7032332d, 0xc26354fc,
-  0x702f2ccd, 0xc25dd329, 0x702c2628, 0xc258517c, 0x70291f3e, 0xc252cff5,
-    0x7026180e, 0xc24d4e95,
-  0x7023109a, 0xc247cd5a, 0x702008e0, 0xc2424c46, 0x701d00e1, 0xc23ccb57,
-    0x7019f89d, 0xc2374a8f,
-  0x7016f014, 0xc231c9ec, 0x7013e746, 0xc22c4970, 0x7010de32, 0xc226c91a,
-    0x700dd4da, 0xc22148ea,
-  0x700acb3c, 0xc21bc8e1, 0x7007c159, 0xc21648fd, 0x7004b731, 0xc210c940,
-    0x7001acc4, 0xc20b49a9,
-  0x6ffea212, 0xc205ca38, 0x6ffb971b, 0xc2004aed, 0x6ff88bde, 0xc1facbc9,
-    0x6ff5805d, 0xc1f54cca,
-  0x6ff27497, 0xc1efcdf3, 0x6fef688b, 0xc1ea4f41, 0x6fec5c3b, 0xc1e4d0b6,
-    0x6fe94fa5, 0xc1df5251,
-  0x6fe642ca, 0xc1d9d412, 0x6fe335ab, 0xc1d455f9, 0x6fe02846, 0xc1ced807,
-    0x6fdd1a9c, 0xc1c95a3c,
-  0x6fda0cae, 0xc1c3dc97, 0x6fd6fe7a, 0xc1be5f18, 0x6fd3f001, 0xc1b8e1bf,
-    0x6fd0e144, 0xc1b3648d,
-  0x6fcdd241, 0xc1ade781, 0x6fcac2fa, 0xc1a86a9c, 0x6fc7b36d, 0xc1a2edde,
-    0x6fc4a39c, 0xc19d7145,
-  0x6fc19385, 0xc197f4d4, 0x6fbe832a, 0xc1927888, 0x6fbb728a, 0xc18cfc63,
-    0x6fb861a4, 0xc1878065,
-  0x6fb5507a, 0xc182048d, 0x6fb23f0b, 0xc17c88dc, 0x6faf2d57, 0xc1770d52,
-    0x6fac1b5f, 0xc17191ee,
-  0x6fa90921, 0xc16c16b0, 0x6fa5f69e, 0xc1669b99, 0x6fa2e3d7, 0xc16120a9,
-    0x6f9fd0cb, 0xc15ba5df,
-  0x6f9cbd79, 0xc1562b3d, 0x6f99a9e3, 0xc150b0c0, 0x6f969608, 0xc14b366b,
-    0x6f9381e9, 0xc145bc3c,
-  0x6f906d84, 0xc1404233, 0x6f8d58db, 0xc13ac852, 0x6f8a43ed, 0xc1354e97,
-    0x6f872eba, 0xc12fd503,
-  0x6f841942, 0xc12a5b95, 0x6f810386, 0xc124e24f, 0x6f7ded84, 0xc11f692f,
-    0x6f7ad73e, 0xc119f036,
-  0x6f77c0b3, 0xc1147764, 0x6f74a9e4, 0xc10efeb8, 0x6f7192cf, 0xc1098634,
-    0x6f6e7b76, 0xc1040dd6,
-  0x6f6b63d8, 0xc0fe959f, 0x6f684bf6, 0xc0f91d8f, 0x6f6533ce, 0xc0f3a5a6,
-    0x6f621b62, 0xc0ee2de3,
-  0x6f5f02b2, 0xc0e8b648, 0x6f5be9bc, 0xc0e33ed4, 0x6f58d082, 0xc0ddc786,
-    0x6f55b703, 0xc0d8505f,
-  0x6f529d40, 0xc0d2d960, 0x6f4f8338, 0xc0cd6287, 0x6f4c68eb, 0xc0c7ebd6,
-    0x6f494e5a, 0xc0c2754b,
-  0x6f463383, 0xc0bcfee7, 0x6f431869, 0xc0b788ab, 0x6f3ffd09, 0xc0b21295,
-    0x6f3ce165, 0xc0ac9ca6,
-  0x6f39c57d, 0xc0a726df, 0x6f36a94f, 0xc0a1b13e, 0x6f338cde, 0xc09c3bc5,
-    0x6f307027, 0xc096c673,
-  0x6f2d532c, 0xc0915148, 0x6f2a35ed, 0xc08bdc44, 0x6f271868, 0xc0866767,
-    0x6f23faa0, 0xc080f2b1,
-  0x6f20dc92, 0xc07b7e23, 0x6f1dbe41, 0xc07609bb, 0x6f1a9faa, 0xc070957b,
-    0x6f1780cf, 0xc06b2162,
-  0x6f1461b0, 0xc065ad70, 0x6f11424c, 0xc06039a6, 0x6f0e22a3, 0xc05ac603,
-    0x6f0b02b6, 0xc0555287,
-  0x6f07e285, 0xc04fdf32, 0x6f04c20f, 0xc04a6c05, 0x6f01a155, 0xc044f8fe,
-    0x6efe8056, 0xc03f8620,
-  0x6efb5f12, 0xc03a1368, 0x6ef83d8a, 0xc034a0d8, 0x6ef51bbe, 0xc02f2e6f,
-    0x6ef1f9ad, 0xc029bc2e,
-  0x6eeed758, 0xc0244a14, 0x6eebb4bf, 0xc01ed821, 0x6ee891e1, 0xc0196656,
-    0x6ee56ebe, 0xc013f4b2,
-  0x6ee24b57, 0xc00e8336, 0x6edf27ac, 0xc00911e1, 0x6edc03bc, 0xc003a0b3,
-    0x6ed8df88, 0xbffe2fad,
-  0x6ed5bb10, 0xbff8bece, 0x6ed29653, 0xbff34e17, 0x6ecf7152, 0xbfeddd88,
-    0x6ecc4c0d, 0xbfe86d20,
-  0x6ec92683, 0xbfe2fcdf, 0x6ec600b5, 0xbfdd8cc6, 0x6ec2daa2, 0xbfd81cd5,
-    0x6ebfb44b, 0xbfd2ad0b,
-  0x6ebc8db0, 0xbfcd3d69, 0x6eb966d1, 0xbfc7cdee, 0x6eb63fad, 0xbfc25e9b,
-    0x6eb31845, 0xbfbcef70,
-  0x6eaff099, 0xbfb7806c, 0x6eacc8a8, 0xbfb21190, 0x6ea9a073, 0xbfaca2dc,
-    0x6ea677fa, 0xbfa7344f,
-  0x6ea34f3d, 0xbfa1c5ea, 0x6ea0263b, 0xbf9c57ac, 0x6e9cfcf5, 0xbf96e997,
-    0x6e99d36b, 0xbf917ba9,
-  0x6e96a99d, 0xbf8c0de3, 0x6e937f8a, 0xbf86a044, 0x6e905534, 0xbf8132ce,
-    0x6e8d2a99, 0xbf7bc57f,
-  0x6e89ffb9, 0xbf765858, 0x6e86d496, 0xbf70eb59, 0x6e83a92f, 0xbf6b7e81,
-    0x6e807d83, 0xbf6611d2,
-  0x6e7d5193, 0xbf60a54a, 0x6e7a255f, 0xbf5b38ea, 0x6e76f8e7, 0xbf55ccb2,
-    0x6e73cc2b, 0xbf5060a2,
-  0x6e709f2a, 0xbf4af4ba, 0x6e6d71e6, 0xbf4588fa, 0x6e6a445d, 0xbf401d61,
-    0x6e671690, 0xbf3ab1f1,
-  0x6e63e87f, 0xbf3546a8, 0x6e60ba2a, 0xbf2fdb88, 0x6e5d8b91, 0xbf2a708f,
-    0x6e5a5cb4, 0xbf2505bf,
-  0x6e572d93, 0xbf1f9b16, 0x6e53fe2e, 0xbf1a3096, 0x6e50ce84, 0xbf14c63d,
-    0x6e4d9e97, 0xbf0f5c0d,
-  0x6e4a6e66, 0xbf09f205, 0x6e473df0, 0xbf048824, 0x6e440d37, 0xbeff1e6c,
-    0x6e40dc39, 0xbef9b4dc,
-  0x6e3daaf8, 0xbef44b74, 0x6e3a7972, 0xbeeee234, 0x6e3747a9, 0xbee9791c,
-    0x6e34159b, 0xbee4102d,
-  0x6e30e34a, 0xbedea765, 0x6e2db0b4, 0xbed93ec6, 0x6e2a7ddb, 0xbed3d64f,
-    0x6e274abe, 0xbece6e00,
-  0x6e24175c, 0xbec905d9, 0x6e20e3b7, 0xbec39ddb, 0x6e1dafce, 0xbebe3605,
-    0x6e1a7ba1, 0xbeb8ce57,
-  0x6e174730, 0xbeb366d1, 0x6e14127b, 0xbeadff74, 0x6e10dd82, 0xbea8983f,
-    0x6e0da845, 0xbea33132,
-  0x6e0a72c5, 0xbe9dca4e, 0x6e073d00, 0xbe986391, 0x6e0406f8, 0xbe92fcfe,
-    0x6e00d0ac, 0xbe8d9692,
-  0x6dfd9a1c, 0xbe88304f, 0x6dfa6348, 0xbe82ca35, 0x6df72c30, 0xbe7d6442,
-    0x6df3f4d4, 0xbe77fe78,
-  0x6df0bd35, 0xbe7298d7, 0x6ded8552, 0xbe6d335e, 0x6dea4d2b, 0xbe67ce0d,
-    0x6de714c0, 0xbe6268e5,
-  0x6de3dc11, 0xbe5d03e6, 0x6de0a31f, 0xbe579f0f, 0x6ddd69e9, 0xbe523a60,
-    0x6dda306f, 0xbe4cd5da,
-  0x6dd6f6b1, 0xbe47717c, 0x6dd3bcaf, 0xbe420d47, 0x6dd0826a, 0xbe3ca93b,
-    0x6dcd47e1, 0xbe374557,
-  0x6dca0d14, 0xbe31e19b, 0x6dc6d204, 0xbe2c7e09, 0x6dc396b0, 0xbe271a9f,
-    0x6dc05b18, 0xbe21b75d,
-  0x6dbd1f3c, 0xbe1c5444, 0x6db9e31d, 0xbe16f154, 0x6db6a6ba, 0xbe118e8c,
-    0x6db36a14, 0xbe0c2bed,
-  0x6db02d29, 0xbe06c977, 0x6daceffb, 0xbe01672a, 0x6da9b28a, 0xbdfc0505,
-    0x6da674d5, 0xbdf6a309,
-  0x6da336dc, 0xbdf14135, 0x6d9ff89f, 0xbdebdf8b, 0x6d9cba1f, 0xbde67e09,
-    0x6d997b5b, 0xbde11cb0,
-  0x6d963c54, 0xbddbbb7f, 0x6d92fd09, 0xbdd65a78, 0x6d8fbd7a, 0xbdd0f999,
-    0x6d8c7da8, 0xbdcb98e3,
-  0x6d893d93, 0xbdc63856, 0x6d85fd39, 0xbdc0d7f2, 0x6d82bc9d, 0xbdbb77b7,
-    0x6d7f7bbc, 0xbdb617a4,
-  0x6d7c3a98, 0xbdb0b7bb, 0x6d78f931, 0xbdab57fa, 0x6d75b786, 0xbda5f862,
-    0x6d727597, 0xbda098f3,
-  0x6d6f3365, 0xbd9b39ad, 0x6d6bf0f0, 0xbd95da91, 0x6d68ae37, 0xbd907b9d,
-    0x6d656b3a, 0xbd8b1cd2,
-  0x6d6227fa, 0xbd85be30, 0x6d5ee477, 0xbd805fb7, 0x6d5ba0b0, 0xbd7b0167,
-    0x6d585ca6, 0xbd75a340,
-  0x6d551858, 0xbd704542, 0x6d51d3c6, 0xbd6ae76d, 0x6d4e8ef2, 0xbd6589c1,
-    0x6d4b49da, 0xbd602c3f,
-  0x6d48047e, 0xbd5acee5, 0x6d44bedf, 0xbd5571b5, 0x6d4178fd, 0xbd5014ad,
-    0x6d3e32d7, 0xbd4ab7cf,
-  0x6d3aec6e, 0xbd455b1a, 0x6d37a5c1, 0xbd3ffe8e, 0x6d345ed1, 0xbd3aa22c,
-    0x6d31179e, 0xbd3545f2,
-  0x6d2dd027, 0xbd2fe9e2, 0x6d2a886e, 0xbd2a8dfb, 0x6d274070, 0xbd25323d,
-    0x6d23f830, 0xbd1fd6a8,
-  0x6d20afac, 0xbd1a7b3d, 0x6d1d66e4, 0xbd151ffb, 0x6d1a1dda, 0xbd0fc4e2,
-    0x6d16d48c, 0xbd0a69f2,
-  0x6d138afb, 0xbd050f2c, 0x6d104126, 0xbcffb48f, 0x6d0cf70f, 0xbcfa5a1b,
-    0x6d09acb4, 0xbcf4ffd1,
-  0x6d066215, 0xbcefa5b0, 0x6d031734, 0xbcea4bb9, 0x6cffcc0f, 0xbce4f1eb,
-    0x6cfc80a7, 0xbcdf9846,
-  0x6cf934fc, 0xbcda3ecb, 0x6cf5e90d, 0xbcd4e579, 0x6cf29cdc, 0xbccf8c50,
-    0x6cef5067, 0xbcca3351,
-  0x6cec03af, 0xbcc4da7b, 0x6ce8b6b4, 0xbcbf81cf, 0x6ce56975, 0xbcba294d,
-    0x6ce21bf4, 0xbcb4d0f4,
-  0x6cdece2f, 0xbcaf78c4, 0x6cdb8027, 0xbcaa20be, 0x6cd831dc, 0xbca4c8e1,
-    0x6cd4e34e, 0xbc9f712e,
-  0x6cd1947c, 0xbc9a19a5, 0x6cce4568, 0xbc94c245, 0x6ccaf610, 0xbc8f6b0f,
-    0x6cc7a676, 0xbc8a1402,
-  0x6cc45698, 0xbc84bd1f, 0x6cc10677, 0xbc7f6665, 0x6cbdb613, 0xbc7a0fd6,
-    0x6cba656c, 0xbc74b96f,
-  0x6cb71482, 0xbc6f6333, 0x6cb3c355, 0xbc6a0d20, 0x6cb071e4, 0xbc64b737,
-    0x6cad2031, 0xbc5f6177,
-  0x6ca9ce3b, 0xbc5a0be2, 0x6ca67c01, 0xbc54b676, 0x6ca32985, 0xbc4f6134,
-    0x6c9fd6c6, 0xbc4a0c1b,
-  0x6c9c83c3, 0xbc44b72c, 0x6c99307e, 0xbc3f6267, 0x6c95dcf6, 0xbc3a0dcc,
-    0x6c92892a, 0xbc34b95b,
-  0x6c8f351c, 0xbc2f6513, 0x6c8be0cb, 0xbc2a10f6, 0x6c888c36, 0xbc24bd02,
-    0x6c85375f, 0xbc1f6938,
-  0x6c81e245, 0xbc1a1598, 0x6c7e8ce8, 0xbc14c221, 0x6c7b3748, 0xbc0f6ed5,
-    0x6c77e165, 0xbc0a1bb3,
-  0x6c748b3f, 0xbc04c8ba, 0x6c7134d7, 0xbbff75ec, 0x6c6dde2b, 0xbbfa2347,
-    0x6c6a873d, 0xbbf4d0cc,
-  0x6c67300b, 0xbbef7e7c, 0x6c63d897, 0xbbea2c55, 0x6c6080e0, 0xbbe4da58,
-    0x6c5d28e6, 0xbbdf8885,
-  0x6c59d0a9, 0xbbda36dd, 0x6c56782a, 0xbbd4e55e, 0x6c531f67, 0xbbcf940a,
-    0x6c4fc662, 0xbbca42df,
-  0x6c4c6d1a, 0xbbc4f1df, 0x6c49138f, 0xbbbfa108, 0x6c45b9c1, 0xbbba505c,
-    0x6c425fb1, 0xbbb4ffda,
-  0x6c3f055d, 0xbbafaf82, 0x6c3baac7, 0xbbaa5f54, 0x6c384fef, 0xbba50f50,
-    0x6c34f4d3, 0xbb9fbf77,
-  0x6c319975, 0xbb9a6fc7, 0x6c2e3dd4, 0xbb952042, 0x6c2ae1f0, 0xbb8fd0e7,
-    0x6c2785ca, 0xbb8a81b6,
-  0x6c242960, 0xbb8532b0, 0x6c20ccb4, 0xbb7fe3d3, 0x6c1d6fc6, 0xbb7a9521,
-    0x6c1a1295, 0xbb754699,
-  0x6c16b521, 0xbb6ff83c, 0x6c13576a, 0xbb6aaa09, 0x6c0ff971, 0xbb655c00,
-    0x6c0c9b35, 0xbb600e21,
-  0x6c093cb6, 0xbb5ac06d, 0x6c05ddf5, 0xbb5572e3, 0x6c027ef1, 0xbb502583,
-    0x6bff1faa, 0xbb4ad84e,
-  0x6bfbc021, 0xbb458b43, 0x6bf86055, 0xbb403e63, 0x6bf50047, 0xbb3af1ad,
-    0x6bf19ff6, 0xbb35a521,
-  0x6bee3f62, 0xbb3058c0, 0x6beade8c, 0xbb2b0c8a, 0x6be77d74, 0xbb25c07d,
-    0x6be41c18, 0xbb20749c,
-  0x6be0ba7b, 0xbb1b28e4, 0x6bdd589a, 0xbb15dd57, 0x6bd9f677, 0xbb1091f5,
-    0x6bd69412, 0xbb0b46bd,
-  0x6bd3316a, 0xbb05fbb0, 0x6bcfce80, 0xbb00b0ce, 0x6bcc6b53, 0xbafb6615,
-    0x6bc907e3, 0xbaf61b88,
-  0x6bc5a431, 0xbaf0d125, 0x6bc2403d, 0xbaeb86ed, 0x6bbedc06, 0xbae63cdf,
-    0x6bbb778d, 0xbae0f2fc,
-  0x6bb812d1, 0xbadba943, 0x6bb4add3, 0xbad65fb5, 0x6bb14892, 0xbad11652,
-    0x6bade30f, 0xbacbcd1a,
-  0x6baa7d49, 0xbac6840c, 0x6ba71741, 0xbac13b29, 0x6ba3b0f7, 0xbabbf270,
-    0x6ba04a6a, 0xbab6a9e3,
-  0x6b9ce39b, 0xbab16180, 0x6b997c8a, 0xbaac1948, 0x6b961536, 0xbaa6d13a,
-    0x6b92ada0, 0xbaa18958,
-  0x6b8f45c7, 0xba9c41a0, 0x6b8bddac, 0xba96fa13, 0x6b88754f, 0xba91b2b1,
-    0x6b850caf, 0xba8c6b79,
-  0x6b81a3cd, 0xba87246d, 0x6b7e3aa9, 0xba81dd8b, 0x6b7ad142, 0xba7c96d4,
-    0x6b776799, 0xba775048,
-  0x6b73fdae, 0xba7209e7, 0x6b709381, 0xba6cc3b1, 0x6b6d2911, 0xba677da6,
-    0x6b69be5f, 0xba6237c5,
-  0x6b66536b, 0xba5cf210, 0x6b62e834, 0xba57ac86, 0x6b5f7cbc, 0xba526726,
-    0x6b5c1101, 0xba4d21f2,
-  0x6b58a503, 0xba47dce8, 0x6b5538c4, 0xba42980a, 0x6b51cc42, 0xba3d5356,
-    0x6b4e5f7f, 0xba380ece,
-  0x6b4af279, 0xba32ca71, 0x6b478530, 0xba2d863e, 0x6b4417a6, 0xba284237,
-    0x6b40a9d9, 0xba22fe5b,
-  0x6b3d3bcb, 0xba1dbaaa, 0x6b39cd7a, 0xba187724, 0x6b365ee7, 0xba1333c9,
-    0x6b32f012, 0xba0df099,
-  0x6b2f80fb, 0xba08ad95, 0x6b2c11a1, 0xba036abb, 0x6b28a206, 0xb9fe280d,
-    0x6b253228, 0xb9f8e58a,
-  0x6b21c208, 0xb9f3a332, 0x6b1e51a7, 0xb9ee6106, 0x6b1ae103, 0xb9e91f04,
-    0x6b17701d, 0xb9e3dd2e,
-  0x6b13fef5, 0xb9de9b83, 0x6b108d8b, 0xb9d95a03, 0x6b0d1bdf, 0xb9d418af,
-    0x6b09a9f1, 0xb9ced786,
-  0x6b0637c1, 0xb9c99688, 0x6b02c54f, 0xb9c455b6, 0x6aff529a, 0xb9bf150e,
-    0x6afbdfa4, 0xb9b9d493,
-  0x6af86c6c, 0xb9b49442, 0x6af4f8f2, 0xb9af541d, 0x6af18536, 0xb9aa1423,
-    0x6aee1138, 0xb9a4d455,
-  0x6aea9cf8, 0xb99f94b2, 0x6ae72876, 0xb99a553a, 0x6ae3b3b2, 0xb99515ee,
-    0x6ae03eac, 0xb98fd6cd,
-  0x6adcc964, 0xb98a97d8, 0x6ad953db, 0xb985590e, 0x6ad5de0f, 0xb9801a70,
-    0x6ad26802, 0xb97adbfd,
-  0x6acef1b2, 0xb9759db6, 0x6acb7b21, 0xb9705f9a, 0x6ac8044e, 0xb96b21aa,
-    0x6ac48d39, 0xb965e3e5,
-  0x6ac115e2, 0xb960a64c, 0x6abd9e49, 0xb95b68de, 0x6aba266e, 0xb9562b9c,
-    0x6ab6ae52, 0xb950ee86,
-  0x6ab335f4, 0xb94bb19b, 0x6aafbd54, 0xb94674dc, 0x6aac4472, 0xb9413848,
-    0x6aa8cb4e, 0xb93bfbe0,
-  0x6aa551e9, 0xb936bfa4, 0x6aa1d841, 0xb9318393, 0x6a9e5e58, 0xb92c47ae,
-    0x6a9ae42e, 0xb9270bf5,
-  0x6a9769c1, 0xb921d067, 0x6a93ef13, 0xb91c9505, 0x6a907423, 0xb91759cf,
-    0x6a8cf8f1, 0xb9121ec5,
-  0x6a897d7d, 0xb90ce3e6, 0x6a8601c8, 0xb907a933, 0x6a8285d1, 0xb9026eac,
-    0x6a7f0999, 0xb8fd3451,
-  0x6a7b8d1e, 0xb8f7fa21, 0x6a781062, 0xb8f2c01d, 0x6a749365, 0xb8ed8646,
-    0x6a711625, 0xb8e84c99,
-  0x6a6d98a4, 0xb8e31319, 0x6a6a1ae2, 0xb8ddd9c5, 0x6a669cdd, 0xb8d8a09d,
-    0x6a631e97, 0xb8d367a0,
-  0x6a5fa010, 0xb8ce2ecf, 0x6a5c2147, 0xb8c8f62b, 0x6a58a23c, 0xb8c3bdb2,
-    0x6a5522ef, 0xb8be8565,
-  0x6a51a361, 0xb8b94d44, 0x6a4e2392, 0xb8b4154f, 0x6a4aa381, 0xb8aedd86,
-    0x6a47232e, 0xb8a9a5e9,
-  0x6a43a29a, 0xb8a46e78, 0x6a4021c4, 0xb89f3733, 0x6a3ca0ad, 0xb89a001a,
-    0x6a391f54, 0xb894c92d,
-  0x6a359db9, 0xb88f926d, 0x6a321bdd, 0xb88a5bd8, 0x6a2e99c0, 0xb885256f,
-    0x6a2b1761, 0xb87fef33,
-  0x6a2794c1, 0xb87ab922, 0x6a2411df, 0xb875833e, 0x6a208ebb, 0xb8704d85,
-    0x6a1d0b57, 0xb86b17f9,
-  0x6a1987b0, 0xb865e299, 0x6a1603c8, 0xb860ad66, 0x6a127f9f, 0xb85b785e,
-    0x6a0efb35, 0xb8564383,
-  0x6a0b7689, 0xb8510ed4, 0x6a07f19b, 0xb84bda51, 0x6a046c6c, 0xb846a5fa,
-    0x6a00e6fc, 0xb84171cf,
-  0x69fd614a, 0xb83c3dd1, 0x69f9db57, 0xb83709ff, 0x69f65523, 0xb831d659,
-    0x69f2cead, 0xb82ca2e0,
-  0x69ef47f6, 0xb8276f93, 0x69ebc0fe, 0xb8223c72, 0x69e839c4, 0xb81d097e,
-    0x69e4b249, 0xb817d6b6,
-  0x69e12a8c, 0xb812a41a, 0x69dda28f, 0xb80d71aa, 0x69da1a50, 0xb8083f67,
-    0x69d691cf, 0xb8030d51,
-  0x69d3090e, 0xb7fddb67, 0x69cf800b, 0xb7f8a9a9, 0x69cbf6c7, 0xb7f37818,
-    0x69c86d41, 0xb7ee46b3,
-  0x69c4e37a, 0xb7e9157a, 0x69c15973, 0xb7e3e46e, 0x69bdcf29, 0xb7deb38f,
-    0x69ba449f, 0xb7d982dc,
-  0x69b6b9d3, 0xb7d45255, 0x69b32ec7, 0xb7cf21fb, 0x69afa378, 0xb7c9f1ce,
-    0x69ac17e9, 0xb7c4c1cd,
-  0x69a88c19, 0xb7bf91f8, 0x69a50007, 0xb7ba6251, 0x69a173b5, 0xb7b532d6,
-    0x699de721, 0xb7b00387,
-  0x699a5a4c, 0xb7aad465, 0x6996cd35, 0xb7a5a570, 0x69933fde, 0xb7a076a7,
-    0x698fb246, 0xb79b480b,
-  0x698c246c, 0xb796199b, 0x69889651, 0xb790eb58, 0x698507f6, 0xb78bbd42,
-    0x69817959, 0xb7868f59,
-  0x697dea7b, 0xb781619c, 0x697a5b5c, 0xb77c340c, 0x6976cbfc, 0xb77706a9,
-    0x69733c5b, 0xb771d972,
-  0x696fac78, 0xb76cac69, 0x696c1c55, 0xb7677f8c, 0x69688bf1, 0xb76252db,
-    0x6964fb4c, 0xb75d2658,
-  0x69616a65, 0xb757fa01, 0x695dd93e, 0xb752cdd8, 0x695a47d6, 0xb74da1db,
-    0x6956b62d, 0xb748760b,
-  0x69532442, 0xb7434a67, 0x694f9217, 0xb73e1ef1, 0x694bffab, 0xb738f3a7,
-    0x69486cfe, 0xb733c88b,
-  0x6944da10, 0xb72e9d9b, 0x694146e1, 0xb72972d8, 0x693db371, 0xb7244842,
-    0x693a1fc0, 0xb71f1dd9,
-  0x69368bce, 0xb719f39e, 0x6932f79b, 0xb714c98e, 0x692f6328, 0xb70f9fac,
-    0x692bce73, 0xb70a75f7,
-  0x6928397e, 0xb7054c6f, 0x6924a448, 0xb7002314, 0x69210ed1, 0xb6faf9e6,
-    0x691d7919, 0xb6f5d0e5,
-  0x6919e320, 0xb6f0a812, 0x69164ce7, 0xb6eb7f6b, 0x6912b66c, 0xb6e656f1,
-    0x690f1fb1, 0xb6e12ea4,
-  0x690b88b5, 0xb6dc0685, 0x6907f178, 0xb6d6de92, 0x690459fb, 0xb6d1b6cd,
-    0x6900c23c, 0xb6cc8f35,
-  0x68fd2a3d, 0xb6c767ca, 0x68f991fd, 0xb6c2408c, 0x68f5f97d, 0xb6bd197c,
-    0x68f260bb, 0xb6b7f298,
-  0x68eec7b9, 0xb6b2cbe2, 0x68eb2e76, 0xb6ada559, 0x68e794f3, 0xb6a87efd,
-    0x68e3fb2e, 0xb6a358ce,
-  0x68e06129, 0xb69e32cd, 0x68dcc6e4, 0xb6990cf9, 0x68d92c5d, 0xb693e752,
-    0x68d59196, 0xb68ec1d9,
-  0x68d1f68f, 0xb6899c8d, 0x68ce5b46, 0xb684776e, 0x68cabfbd, 0xb67f527c,
-    0x68c723f3, 0xb67a2db8,
-  0x68c387e9, 0xb6750921, 0x68bfeb9e, 0xb66fe4b8, 0x68bc4f13, 0xb66ac07c,
-    0x68b8b247, 0xb6659c6d,
-  0x68b5153a, 0xb660788c, 0x68b177ed, 0xb65b54d8, 0x68adda5f, 0xb6563151,
-    0x68aa3c90, 0xb6510df8,
-  0x68a69e81, 0xb64beacd, 0x68a30031, 0xb646c7ce, 0x689f61a1, 0xb641a4fe,
-    0x689bc2d1, 0xb63c825b,
-  0x689823bf, 0xb6375fe5, 0x6894846e, 0xb6323d9d, 0x6890e4dc, 0xb62d1b82,
-    0x688d4509, 0xb627f995,
-  0x6889a4f6, 0xb622d7d6, 0x688604a2, 0xb61db644, 0x6882640e, 0xb61894df,
-    0x687ec339, 0xb61373a9,
-  0x687b2224, 0xb60e529f, 0x687780ce, 0xb60931c4, 0x6873df38, 0xb6041116,
-    0x68703d62, 0xb5fef095,
-  0x686c9b4b, 0xb5f9d043, 0x6868f8f4, 0xb5f4b01e, 0x6865565c, 0xb5ef9026,
-    0x6861b384, 0xb5ea705d,
-  0x685e106c, 0xb5e550c1, 0x685a6d13, 0xb5e03153, 0x6856c979, 0xb5db1212,
-    0x685325a0, 0xb5d5f2ff,
-  0x684f8186, 0xb5d0d41a, 0x684bdd2c, 0xb5cbb563, 0x68483891, 0xb5c696da,
-    0x684493b6, 0xb5c1787e,
-  0x6840ee9b, 0xb5bc5a50, 0x683d493f, 0xb5b73c50, 0x6839a3a4, 0xb5b21e7e,
-    0x6835fdc7, 0xb5ad00d9,
-  0x683257ab, 0xb5a7e362, 0x682eb14e, 0xb5a2c61a, 0x682b0ab1, 0xb59da8ff,
-    0x682763d4, 0xb5988c12,
-  0x6823bcb7, 0xb5936f53, 0x68201559, 0xb58e52c2, 0x681c6dbb, 0xb589365e,
-    0x6818c5dd, 0xb5841a29,
-  0x68151dbe, 0xb57efe22, 0x68117560, 0xb579e248, 0x680dccc1, 0xb574c69d,
-    0x680a23e2, 0xb56fab1f,
-  0x68067ac3, 0xb56a8fd0, 0x6802d164, 0xb56574ae, 0x67ff27c4, 0xb56059bb,
-    0x67fb7de5, 0xb55b3ef5,
-  0x67f7d3c5, 0xb556245e, 0x67f42965, 0xb55109f5, 0x67f07ec5, 0xb54befba,
-    0x67ecd3e5, 0xb546d5ac,
-  0x67e928c5, 0xb541bbcd, 0x67e57d64, 0xb53ca21c, 0x67e1d1c4, 0xb5378899,
-    0x67de25e3, 0xb5326f45,
-  0x67da79c3, 0xb52d561e, 0x67d6cd62, 0xb5283d26, 0x67d320c1, 0xb523245b,
-    0x67cf73e1, 0xb51e0bbf,
-  0x67cbc6c0, 0xb518f351, 0x67c8195f, 0xb513db12, 0x67c46bbe, 0xb50ec300,
-    0x67c0bddd, 0xb509ab1d,
-  0x67bd0fbd, 0xb5049368, 0x67b9615c, 0xb4ff7be1, 0x67b5b2bb, 0xb4fa6489,
-    0x67b203da, 0xb4f54d5f,
-  0x67ae54ba, 0xb4f03663, 0x67aaa559, 0xb4eb1f95, 0x67a6f5b8, 0xb4e608f6,
-    0x67a345d8, 0xb4e0f285,
-  0x679f95b7, 0xb4dbdc42, 0x679be557, 0xb4d6c62e, 0x679834b6, 0xb4d1b048,
-    0x679483d6, 0xb4cc9a90,
-  0x6790d2b6, 0xb4c78507, 0x678d2156, 0xb4c26fad, 0x67896fb6, 0xb4bd5a80,
-    0x6785bdd6, 0xb4b84582,
-  0x67820bb7, 0xb4b330b3, 0x677e5957, 0xb4ae1c12, 0x677aa6b8, 0xb4a9079f,
-    0x6776f3d9, 0xb4a3f35b,
-  0x677340ba, 0xb49edf45, 0x676f8d5b, 0xb499cb5e, 0x676bd9bd, 0xb494b7a6,
-    0x676825de, 0xb48fa41c,
-  0x676471c0, 0xb48a90c0, 0x6760bd62, 0xb4857d93, 0x675d08c4, 0xb4806a95,
-    0x675953e7, 0xb47b57c5,
-  0x67559eca, 0xb4764523, 0x6751e96d, 0xb47132b1, 0x674e33d0, 0xb46c206d,
-    0x674a7df4, 0xb4670e57,
-  0x6746c7d8, 0xb461fc70, 0x6743117c, 0xb45ceab8, 0x673f5ae0, 0xb457d92f,
-    0x673ba405, 0xb452c7d4,
-  0x6737ecea, 0xb44db6a8, 0x67343590, 0xb448a5aa, 0x67307df5, 0xb44394db,
-    0x672cc61c, 0xb43e843b,
-  0x67290e02, 0xb43973ca, 0x672555a9, 0xb4346387, 0x67219d10, 0xb42f5373,
-    0x671de438, 0xb42a438e,
-  0x671a2b20, 0xb42533d8, 0x671671c8, 0xb4202451, 0x6712b831, 0xb41b14f8,
-    0x670efe5a, 0xb41605ce,
-  0x670b4444, 0xb410f6d3, 0x670789ee, 0xb40be807, 0x6703cf58, 0xb406d969,
-    0x67001483, 0xb401cafb,
-  0x66fc596f, 0xb3fcbcbb, 0x66f89e1b, 0xb3f7aeaa, 0x66f4e287, 0xb3f2a0c9,
-    0x66f126b4, 0xb3ed9316,
-  0x66ed6aa1, 0xb3e88592, 0x66e9ae4f, 0xb3e3783d, 0x66e5f1be, 0xb3de6b17,
-    0x66e234ed, 0xb3d95e1f,
-  0x66de77dc, 0xb3d45157, 0x66daba8c, 0xb3cf44be, 0x66d6fcfd, 0xb3ca3854,
-    0x66d33f2e, 0xb3c52c19,
-  0x66cf8120, 0xb3c0200c, 0x66cbc2d2, 0xb3bb142f, 0x66c80445, 0xb3b60881,
-    0x66c44579, 0xb3b0fd02,
-  0x66c0866d, 0xb3abf1b2, 0x66bcc721, 0xb3a6e691, 0x66b90797, 0xb3a1dba0,
-    0x66b547cd, 0xb39cd0dd,
-  0x66b187c3, 0xb397c649, 0x66adc77b, 0xb392bbe5, 0x66aa06f3, 0xb38db1b0,
-    0x66a6462b, 0xb388a7aa,
-  0x66a28524, 0xb3839dd3, 0x669ec3de, 0xb37e942b, 0x669b0259, 0xb3798ab2,
-    0x66974095, 0xb3748169,
-  0x66937e91, 0xb36f784f, 0x668fbc4e, 0xb36a6f64, 0x668bf9cb, 0xb36566a8,
-    0x66883709, 0xb3605e1c,
-  0x66847408, 0xb35b55bf, 0x6680b0c8, 0xb3564d91, 0x667ced49, 0xb3514592,
-    0x6679298a, 0xb34c3dc3,
-  0x6675658c, 0xb3473623, 0x6671a14f, 0xb3422eb2, 0x666ddcd3, 0xb33d2771,
-    0x666a1818, 0xb338205f,
-  0x6666531d, 0xb333197c, 0x66628de4, 0xb32e12c9, 0x665ec86b, 0xb3290c45,
-    0x665b02b3, 0xb32405f1,
-  0x66573cbb, 0xb31effcc, 0x66537685, 0xb319f9d6, 0x664fb010, 0xb314f410,
-    0x664be95b, 0xb30fee79,
-  0x66482267, 0xb30ae912, 0x66445b35, 0xb305e3da, 0x664093c3, 0xb300ded2,
-    0x663ccc12, 0xb2fbd9f9,
-  0x66390422, 0xb2f6d550, 0x66353bf3, 0xb2f1d0d6, 0x66317385, 0xb2eccc8c,
-    0x662daad8, 0xb2e7c871,
-  0x6629e1ec, 0xb2e2c486, 0x662618c1, 0xb2ddc0ca, 0x66224f56, 0xb2d8bd3e,
-    0x661e85ad, 0xb2d3b9e2,
-  0x661abbc5, 0xb2ceb6b5, 0x6616f19e, 0xb2c9b3b8, 0x66132738, 0xb2c4b0ea,
-    0x660f5c93, 0xb2bfae4c,
-  0x660b91af, 0xb2baabde, 0x6607c68c, 0xb2b5a99f, 0x6603fb2a, 0xb2b0a790,
-    0x66002f89, 0xb2aba5b1,
-  0x65fc63a9, 0xb2a6a402, 0x65f8978b, 0xb2a1a282, 0x65f4cb2d, 0xb29ca132,
-    0x65f0fe91, 0xb297a011,
-  0x65ed31b5, 0xb2929f21, 0x65e9649b, 0xb28d9e60, 0x65e59742, 0xb2889dcf,
-    0x65e1c9aa, 0xb2839d6d,
-  0x65ddfbd3, 0xb27e9d3c, 0x65da2dbd, 0xb2799d3a, 0x65d65f69, 0xb2749d68,
-    0x65d290d6, 0xb26f9dc6,
-  0x65cec204, 0xb26a9e54, 0x65caf2f3, 0xb2659f12, 0x65c723a3, 0xb2609fff,
-    0x65c35415, 0xb25ba11d,
-  0x65bf8447, 0xb256a26a, 0x65bbb43b, 0xb251a3e7, 0x65b7e3f1, 0xb24ca594,
-    0x65b41367, 0xb247a771,
-  0x65b0429f, 0xb242a97e, 0x65ac7198, 0xb23dabbb, 0x65a8a052, 0xb238ae28,
-    0x65a4cece, 0xb233b0c5,
-  0x65a0fd0b, 0xb22eb392, 0x659d2b09, 0xb229b68f, 0x659958c9, 0xb224b9bc,
-    0x6595864a, 0xb21fbd19,
-  0x6591b38c, 0xb21ac0a6, 0x658de08f, 0xb215c463, 0x658a0d54, 0xb210c850,
-    0x658639db, 0xb20bcc6d,
-  0x65826622, 0xb206d0ba, 0x657e922b, 0xb201d537, 0x657abdf6, 0xb1fcd9e5,
-    0x6576e982, 0xb1f7dec2,
-  0x657314cf, 0xb1f2e3d0, 0x656f3fde, 0xb1ede90e, 0x656b6aae, 0xb1e8ee7c,
-    0x6567953f, 0xb1e3f41a,
-  0x6563bf92, 0xb1def9e9, 0x655fe9a7, 0xb1d9ffe7, 0x655c137d, 0xb1d50616,
-    0x65583d14, 0xb1d00c75,
-  0x6554666d, 0xb1cb1304, 0x65508f87, 0xb1c619c3, 0x654cb863, 0xb1c120b3,
-    0x6548e101, 0xb1bc27d3,
-  0x6545095f, 0xb1b72f23, 0x65413180, 0xb1b236a4, 0x653d5962, 0xb1ad3e55,
-    0x65398105, 0xb1a84636,
-  0x6535a86b, 0xb1a34e47, 0x6531cf91, 0xb19e5689, 0x652df679, 0xb1995efb,
-    0x652a1d23, 0xb194679e,
-  0x6526438f, 0xb18f7071, 0x652269bc, 0xb18a7974, 0x651e8faa, 0xb18582a8,
-    0x651ab55b, 0xb1808c0c,
-  0x6516dacd, 0xb17b95a0, 0x65130000, 0xb1769f65, 0x650f24f5, 0xb171a95b,
-    0x650b49ac, 0xb16cb380,
-  0x65076e25, 0xb167bdd7, 0x6503925f, 0xb162c85d, 0x64ffb65b, 0xb15dd315,
-    0x64fbda18, 0xb158ddfd,
-  0x64f7fd98, 0xb153e915, 0x64f420d9, 0xb14ef45e, 0x64f043dc, 0xb149ffd7,
-    0x64ec66a0, 0xb1450b81,
-  0x64e88926, 0xb140175b, 0x64e4ab6e, 0xb13b2367, 0x64e0cd78, 0xb1362fa2,
-    0x64dcef44, 0xb1313c0e,
-  0x64d910d1, 0xb12c48ab, 0x64d53220, 0xb1275579, 0x64d15331, 0xb1226277,
-    0x64cd7404, 0xb11d6fa6,
-  0x64c99498, 0xb1187d05, 0x64c5b4ef, 0xb1138a95, 0x64c1d507, 0xb10e9856,
-    0x64bdf4e1, 0xb109a648,
-  0x64ba147d, 0xb104b46a, 0x64b633da, 0xb0ffc2bd, 0x64b252fa, 0xb0fad140,
-    0x64ae71dc, 0xb0f5dff5,
-  0x64aa907f, 0xb0f0eeda, 0x64a6aee4, 0xb0ebfdf0, 0x64a2cd0c, 0xb0e70d37,
-    0x649eeaf5, 0xb0e21cae,
-  0x649b08a0, 0xb0dd2c56, 0x6497260d, 0xb0d83c2f, 0x6493433c, 0xb0d34c39,
-    0x648f602d, 0xb0ce5c74,
-  0x648b7ce0, 0xb0c96ce0, 0x64879955, 0xb0c47d7c, 0x6483b58c, 0xb0bf8e4a,
-    0x647fd185, 0xb0ba9f48,
-  0x647bed3f, 0xb0b5b077, 0x647808bc, 0xb0b0c1d7, 0x647423fb, 0xb0abd368,
-    0x64703efc, 0xb0a6e52a,
-  0x646c59bf, 0xb0a1f71d, 0x64687444, 0xb09d0941, 0x64648e8c, 0xb0981b96,
-    0x6460a895, 0xb0932e1b,
-  0x645cc260, 0xb08e40d2, 0x6458dbed, 0xb08953ba, 0x6454f53d, 0xb08466d3,
-    0x64510e4e, 0xb07f7a1c,
-  0x644d2722, 0xb07a8d97, 0x64493fb8, 0xb075a143, 0x64455810, 0xb070b520,
-    0x6441702a, 0xb06bc92e,
-  0x643d8806, 0xb066dd6d, 0x64399fa5, 0xb061f1de, 0x6435b706, 0xb05d067f,
-    0x6431ce28, 0xb0581b51,
-  0x642de50d, 0xb0533055, 0x6429fbb5, 0xb04e458a, 0x6426121e, 0xb0495af0,
-    0x6422284a, 0xb0447087,
-  0x641e3e38, 0xb03f864f, 0x641a53e8, 0xb03a9c49, 0x6416695a, 0xb035b273,
-    0x64127e8f, 0xb030c8cf,
-  0x640e9386, 0xb02bdf5c, 0x640aa83f, 0xb026f61b, 0x6406bcba, 0xb0220d0a,
-    0x6402d0f8, 0xb01d242b,
-  0x63fee4f8, 0xb0183b7d, 0x63faf8bb, 0xb0135301, 0x63f70c3f, 0xb00e6ab5,
-    0x63f31f86, 0xb009829c,
-  0x63ef3290, 0xb0049ab3, 0x63eb455c, 0xafffb2fc, 0x63e757ea, 0xaffacb76,
-    0x63e36a3a, 0xaff5e421,
-  0x63df7c4d, 0xaff0fcfe, 0x63db8e22, 0xafec160c, 0x63d79fba, 0xafe72f4c,
-    0x63d3b114, 0xafe248bd,
-  0x63cfc231, 0xafdd625f, 0x63cbd310, 0xafd87c33, 0x63c7e3b1, 0xafd39638,
-    0x63c3f415, 0xafceb06f,
-  0x63c0043b, 0xafc9cad7, 0x63bc1424, 0xafc4e571, 0x63b823cf, 0xafc0003c,
-    0x63b4333d, 0xafbb1b39,
-  0x63b0426d, 0xafb63667, 0x63ac5160, 0xafb151c7, 0x63a86015, 0xafac6d58,
-    0x63a46e8d, 0xafa7891b,
-  0x63a07cc7, 0xafa2a50f, 0x639c8ac4, 0xaf9dc135, 0x63989884, 0xaf98dd8d,
-    0x6394a606, 0xaf93fa16,
-  0x6390b34a, 0xaf8f16d1, 0x638cc051, 0xaf8a33bd, 0x6388cd1b, 0xaf8550db,
-    0x6384d9a7, 0xaf806e2b,
-  0x6380e5f6, 0xaf7b8bac, 0x637cf208, 0xaf76a95f, 0x6378fddc, 0xaf71c743,
-    0x63750973, 0xaf6ce55a,
-  0x637114cc, 0xaf6803a2, 0x636d1fe9, 0xaf63221c, 0x63692ac7, 0xaf5e40c7,
-    0x63653569, 0xaf595fa4,
-  0x63613fcd, 0xaf547eb3, 0x635d49f4, 0xaf4f9df4, 0x635953dd, 0xaf4abd66,
-    0x63555d8a, 0xaf45dd0b,
-  0x635166f9, 0xaf40fce1, 0x634d702b, 0xaf3c1ce9, 0x6349791f, 0xaf373d22,
-    0x634581d6, 0xaf325d8e,
-  0x63418a50, 0xaf2d7e2b, 0x633d928d, 0xaf289efa, 0x63399a8d, 0xaf23bffb,
-    0x6335a24f, 0xaf1ee12e,
-  0x6331a9d4, 0xaf1a0293, 0x632db11c, 0xaf15242a, 0x6329b827, 0xaf1045f3,
-    0x6325bef5, 0xaf0b67ed,
-  0x6321c585, 0xaf068a1a, 0x631dcbd9, 0xaf01ac78, 0x6319d1ef, 0xaefccf09,
-    0x6315d7c8, 0xaef7f1cb,
-  0x6311dd64, 0xaef314c0, 0x630de2c3, 0xaeee37e6, 0x6309e7e4, 0xaee95b3f,
-    0x6305ecc9, 0xaee47ec9,
-  0x6301f171, 0xaedfa285, 0x62fdf5db, 0xaedac674, 0x62f9fa09, 0xaed5ea95,
-    0x62f5fdf9, 0xaed10ee7,
-  0x62f201ac, 0xaecc336c, 0x62ee0523, 0xaec75823, 0x62ea085c, 0xaec27d0c,
-    0x62e60b58, 0xaebda227,
-  0x62e20e17, 0xaeb8c774, 0x62de109a, 0xaeb3ecf3, 0x62da12df, 0xaeaf12a4,
-    0x62d614e7, 0xaeaa3888,
-  0x62d216b3, 0xaea55e9e, 0x62ce1841, 0xaea084e6, 0x62ca1992, 0xae9bab60,
-    0x62c61aa7, 0xae96d20c,
-  0x62c21b7e, 0xae91f8eb, 0x62be1c19, 0xae8d1ffb, 0x62ba1c77, 0xae88473e,
-    0x62b61c98, 0xae836eb4,
-  0x62b21c7b, 0xae7e965b, 0x62ae1c23, 0xae79be35, 0x62aa1b8d, 0xae74e641,
-    0x62a61aba, 0xae700e80,
-  0x62a219aa, 0xae6b36f0, 0x629e185e, 0xae665f93, 0x629a16d5, 0xae618869,
-    0x6296150f, 0xae5cb171,
-  0x6292130c, 0xae57daab, 0x628e10cc, 0xae530417, 0x628a0e50, 0xae4e2db6,
-    0x62860b97, 0xae495787,
-  0x628208a1, 0xae44818b, 0x627e056e, 0xae3fabc1, 0x627a01fe, 0xae3ad629,
-    0x6275fe52, 0xae3600c4,
-  0x6271fa69, 0xae312b92, 0x626df643, 0xae2c5691, 0x6269f1e1, 0xae2781c4,
-    0x6265ed42, 0xae22ad29,
-  0x6261e866, 0xae1dd8c0, 0x625de34e, 0xae19048a, 0x6259ddf8, 0xae143086,
-    0x6255d866, 0xae0f5cb5,
-  0x6251d298, 0xae0a8916, 0x624dcc8d, 0xae05b5aa, 0x6249c645, 0xae00e271,
-    0x6245bfc0, 0xadfc0f6a,
-  0x6241b8ff, 0xadf73c96, 0x623db202, 0xadf269f4, 0x6239aac7, 0xaded9785,
-    0x6235a351, 0xade8c548,
-  0x62319b9d, 0xade3f33e, 0x622d93ad, 0xaddf2167, 0x62298b81, 0xadda4fc3,
-    0x62258317, 0xadd57e51,
-  0x62217a72, 0xadd0ad12, 0x621d7190, 0xadcbdc05, 0x62196871, 0xadc70b2c,
-    0x62155f16, 0xadc23a85,
-  0x6211557e, 0xadbd6a10, 0x620d4baa, 0xadb899cf, 0x62094199, 0xadb3c9c0,
-    0x6205374c, 0xadaef9e4,
-  0x62012cc2, 0xadaa2a3b, 0x61fd21fc, 0xada55ac4, 0x61f916f9, 0xada08b80,
-    0x61f50bba, 0xad9bbc70,
-  0x61f1003f, 0xad96ed92, 0x61ecf487, 0xad921ee6, 0x61e8e893, 0xad8d506e,
-    0x61e4dc62, 0xad888229,
-  0x61e0cff5, 0xad83b416, 0x61dcc34c, 0xad7ee636, 0x61d8b666, 0xad7a1889,
-    0x61d4a944, 0xad754b0f,
-  0x61d09be5, 0xad707dc8, 0x61cc8e4b, 0xad6bb0b4, 0x61c88074, 0xad66e3d3,
-    0x61c47260, 0xad621725,
-  0x61c06410, 0xad5d4aaa, 0x61bc5584, 0xad587e61, 0x61b846bc, 0xad53b24c,
-    0x61b437b7, 0xad4ee66a,
-  0x61b02876, 0xad4a1aba, 0x61ac18f9, 0xad454f3e, 0x61a80940, 0xad4083f5,
-    0x61a3f94a, 0xad3bb8df,
-  0x619fe918, 0xad36edfc, 0x619bd8aa, 0xad32234b, 0x6197c800, 0xad2d58ce,
-    0x6193b719, 0xad288e85,
-  0x618fa5f7, 0xad23c46e, 0x618b9498, 0xad1efa8a, 0x618782fd, 0xad1a30d9,
-    0x61837126, 0xad15675c,
-  0x617f5f12, 0xad109e12, 0x617b4cc3, 0xad0bd4fb, 0x61773a37, 0xad070c17,
-    0x61732770, 0xad024366,
-  0x616f146c, 0xacfd7ae8, 0x616b012c, 0xacf8b29e, 0x6166edb0, 0xacf3ea87,
-    0x6162d9f8, 0xacef22a3,
-  0x615ec603, 0xacea5af2, 0x615ab1d3, 0xace59375, 0x61569d67, 0xace0cc2b,
-    0x615288be, 0xacdc0514,
-  0x614e73da, 0xacd73e30, 0x614a5eba, 0xacd27780, 0x6146495d, 0xaccdb103,
-    0x614233c5, 0xacc8eab9,
-  0x613e1df0, 0xacc424a3, 0x613a07e0, 0xacbf5ec0, 0x6135f193, 0xacba9910,
-    0x6131db0b, 0xacb5d394,
-  0x612dc447, 0xacb10e4b, 0x6129ad46, 0xacac4935, 0x6125960a, 0xaca78453,
-    0x61217e92, 0xaca2bfa4,
-  0x611d66de, 0xac9dfb29, 0x61194eee, 0xac9936e1, 0x611536c2, 0xac9472cd,
-    0x61111e5b, 0xac8faeec,
-  0x610d05b7, 0xac8aeb3e, 0x6108ecd8, 0xac8627c4, 0x6104d3bc, 0xac81647e,
-    0x6100ba65, 0xac7ca16b,
-  0x60fca0d2, 0xac77de8b, 0x60f88703, 0xac731bdf, 0x60f46cf9, 0xac6e5967,
-    0x60f052b2, 0xac699722,
-  0x60ec3830, 0xac64d510, 0x60e81d72, 0xac601333, 0x60e40278, 0xac5b5189,
-    0x60dfe743, 0xac569012,
-  0x60dbcbd1, 0xac51cecf, 0x60d7b024, 0xac4d0dc0, 0x60d3943b, 0xac484ce4,
-    0x60cf7817, 0xac438c3c,
-  0x60cb5bb7, 0xac3ecbc7, 0x60c73f1b, 0xac3a0b87, 0x60c32243, 0xac354b7a,
-    0x60bf0530, 0xac308ba0,
-  0x60bae7e1, 0xac2bcbfa, 0x60b6ca56, 0xac270c88, 0x60b2ac8f, 0xac224d4a,
-    0x60ae8e8d, 0xac1d8e40,
-  0x60aa7050, 0xac18cf69, 0x60a651d7, 0xac1410c6, 0x60a23322, 0xac0f5256,
-    0x609e1431, 0xac0a941b,
-  0x6099f505, 0xac05d613, 0x6095d59d, 0xac01183f, 0x6091b5fa, 0xabfc5a9f,
-    0x608d961b, 0xabf79d33,
-  0x60897601, 0xabf2dffb, 0x608555ab, 0xabee22f6, 0x60813519, 0xabe96625,
-    0x607d144c, 0xabe4a988,
-  0x6078f344, 0xabdfed1f, 0x6074d200, 0xabdb30ea, 0x6070b080, 0xabd674e9,
-    0x606c8ec5, 0xabd1b91c,
-  0x60686ccf, 0xabccfd83, 0x60644a9d, 0xabc8421d, 0x6060282f, 0xabc386ec,
-    0x605c0587, 0xabbecbee,
-  0x6057e2a2, 0xabba1125, 0x6053bf82, 0xabb5568f, 0x604f9c27, 0xabb09c2e,
-    0x604b7891, 0xababe200,
-  0x604754bf, 0xaba72807, 0x604330b1, 0xaba26e41, 0x603f0c69, 0xab9db4b0,
-    0x603ae7e5, 0xab98fb52,
-  0x6036c325, 0xab944229, 0x60329e2a, 0xab8f8934, 0x602e78f4, 0xab8ad073,
-    0x602a5383, 0xab8617e6,
-  0x60262dd6, 0xab815f8d, 0x602207ee, 0xab7ca768, 0x601de1ca, 0xab77ef77,
-    0x6019bb6b, 0xab7337bb,
-  0x601594d1, 0xab6e8032, 0x60116dfc, 0xab69c8de, 0x600d46ec, 0xab6511be,
-    0x60091fa0, 0xab605ad2,
-  0x6004f819, 0xab5ba41a, 0x6000d057, 0xab56ed97, 0x5ffca859, 0xab523748,
-    0x5ff88021, 0xab4d812d,
-  0x5ff457ad, 0xab48cb46, 0x5ff02efe, 0xab441593, 0x5fec0613, 0xab3f6015,
-    0x5fe7dcee, 0xab3aaacb,
-  0x5fe3b38d, 0xab35f5b5, 0x5fdf89f2, 0xab3140d4, 0x5fdb601b, 0xab2c8c27,
-    0x5fd73609, 0xab27d7ae,
-  0x5fd30bbc, 0xab23236a, 0x5fcee133, 0xab1e6f5a, 0x5fcab670, 0xab19bb7e,
-    0x5fc68b72, 0xab1507d7,
-  0x5fc26038, 0xab105464, 0x5fbe34c4, 0xab0ba125, 0x5fba0914, 0xab06ee1b,
-    0x5fb5dd29, 0xab023b46,
-  0x5fb1b104, 0xaafd88a4, 0x5fad84a3, 0xaaf8d637, 0x5fa95807, 0xaaf423ff,
-    0x5fa52b31, 0xaaef71fb,
-  0x5fa0fe1f, 0xaaeac02c, 0x5f9cd0d2, 0xaae60e91, 0x5f98a34a, 0xaae15d2a,
-    0x5f947588, 0xaadcabf8,
-  0x5f90478a, 0xaad7fafb, 0x5f8c1951, 0xaad34a32, 0x5f87eade, 0xaace999d,
-    0x5f83bc2f, 0xaac9e93e,
-  0x5f7f8d46, 0xaac53912, 0x5f7b5e22, 0xaac0891c, 0x5f772ec2, 0xaabbd959,
-    0x5f72ff28, 0xaab729cc,
-  0x5f6ecf53, 0xaab27a73, 0x5f6a9f44, 0xaaadcb4f, 0x5f666ef9, 0xaaa91c5f,
-    0x5f623e73, 0xaaa46da4,
-  0x5f5e0db3, 0xaa9fbf1e, 0x5f59dcb8, 0xaa9b10cc, 0x5f55ab82, 0xaa9662af,
-    0x5f517a11, 0xaa91b4c7,
-  0x5f4d4865, 0xaa8d0713, 0x5f49167f, 0xaa885994, 0x5f44e45e, 0xaa83ac4a,
-    0x5f40b202, 0xaa7eff34,
-  0x5f3c7f6b, 0xaa7a5253, 0x5f384c9a, 0xaa75a5a8, 0x5f34198e, 0xaa70f930,
-    0x5f2fe647, 0xaa6c4cee,
-  0x5f2bb2c5, 0xaa67a0e0, 0x5f277f09, 0xaa62f507, 0x5f234b12, 0xaa5e4963,
-    0x5f1f16e0, 0xaa599df4,
-  0x5f1ae274, 0xaa54f2ba, 0x5f16adcc, 0xaa5047b4, 0x5f1278eb, 0xaa4b9ce3,
-    0x5f0e43ce, 0xaa46f248,
-  0x5f0a0e77, 0xaa4247e1, 0x5f05d8e6, 0xaa3d9daf, 0x5f01a31a, 0xaa38f3b1,
-    0x5efd6d13, 0xaa3449e9,
-  0x5ef936d1, 0xaa2fa056, 0x5ef50055, 0xaa2af6f7, 0x5ef0c99f, 0xaa264dce,
-    0x5eec92ae, 0xaa21a4d9,
-  0x5ee85b82, 0xaa1cfc1a, 0x5ee4241c, 0xaa18538f, 0x5edfec7b, 0xaa13ab3a,
-    0x5edbb49f, 0xaa0f0319,
-  0x5ed77c8a, 0xaa0a5b2e, 0x5ed34439, 0xaa05b377, 0x5ecf0baf, 0xaa010bf6,
-    0x5ecad2e9, 0xa9fc64a9,
-  0x5ec699e9, 0xa9f7bd92, 0x5ec260af, 0xa9f316b0, 0x5ebe273b, 0xa9ee7002,
-    0x5eb9ed8b, 0xa9e9c98a,
-  0x5eb5b3a2, 0xa9e52347, 0x5eb1797e, 0xa9e07d39, 0x5ead3f1f, 0xa9dbd761,
-    0x5ea90487, 0xa9d731bd,
-  0x5ea4c9b3, 0xa9d28c4e, 0x5ea08ea6, 0xa9cde715, 0x5e9c535e, 0xa9c94211,
-    0x5e9817dc, 0xa9c49d42,
-  0x5e93dc1f, 0xa9bff8a8, 0x5e8fa028, 0xa9bb5444, 0x5e8b63f7, 0xa9b6b014,
-    0x5e87278b, 0xa9b20c1a,
-  0x5e82eae5, 0xa9ad6855, 0x5e7eae05, 0xa9a8c4c5, 0x5e7a70ea, 0xa9a4216b,
-    0x5e763395, 0xa99f7e46,
-  0x5e71f606, 0xa99adb56, 0x5e6db83d, 0xa996389b, 0x5e697a39, 0xa9919616,
-    0x5e653bfc, 0xa98cf3c6,
-  0x5e60fd84, 0xa98851ac, 0x5e5cbed1, 0xa983afc6, 0x5e587fe5, 0xa97f0e16,
-    0x5e5440be, 0xa97a6c9c,
-  0x5e50015d, 0xa975cb57, 0x5e4bc1c2, 0xa9712a47, 0x5e4781ed, 0xa96c896c,
-    0x5e4341de, 0xa967e8c7,
-  0x5e3f0194, 0xa9634858, 0x5e3ac110, 0xa95ea81d, 0x5e368053, 0xa95a0819,
-    0x5e323f5b, 0xa9556849,
-  0x5e2dfe29, 0xa950c8b0, 0x5e29bcbd, 0xa94c294b, 0x5e257b17, 0xa9478a1c,
-    0x5e213936, 0xa942eb23,
-  0x5e1cf71c, 0xa93e4c5f, 0x5e18b4c8, 0xa939add1, 0x5e147239, 0xa9350f78,
-    0x5e102f71, 0xa9307155,
-  0x5e0bec6e, 0xa92bd367, 0x5e07a932, 0xa92735af, 0x5e0365bb, 0xa922982c,
-    0x5dff220b, 0xa91dfadf,
-  0x5dfade20, 0xa9195dc7, 0x5df699fc, 0xa914c0e6, 0x5df2559e, 0xa9102439,
-    0x5dee1105, 0xa90b87c3,
-  0x5de9cc33, 0xa906eb82, 0x5de58727, 0xa9024f76, 0x5de141e1, 0xa8fdb3a1,
-    0x5ddcfc61, 0xa8f91801,
-  0x5dd8b6a7, 0xa8f47c97, 0x5dd470b3, 0xa8efe162, 0x5dd02a85, 0xa8eb4663,
-    0x5dcbe41d, 0xa8e6ab9a,
-  0x5dc79d7c, 0xa8e21106, 0x5dc356a1, 0xa8dd76a9, 0x5dbf0f8c, 0xa8d8dc81,
-    0x5dbac83d, 0xa8d4428f,
-  0x5db680b4, 0xa8cfa8d2, 0x5db238f1, 0xa8cb0f4b, 0x5dadf0f5, 0xa8c675fb,
-    0x5da9a8bf, 0xa8c1dce0,
-  0x5da5604f, 0xa8bd43fa, 0x5da117a5, 0xa8b8ab4b, 0x5d9ccec2, 0xa8b412d1,
-    0x5d9885a5, 0xa8af7a8e,
-  0x5d943c4e, 0xa8aae280, 0x5d8ff2bd, 0xa8a64aa8, 0x5d8ba8f3, 0xa8a1b306,
-    0x5d875eef, 0xa89d1b99,
-  0x5d8314b1, 0xa8988463, 0x5d7eca39, 0xa893ed63, 0x5d7a7f88, 0xa88f5698,
-    0x5d76349d, 0xa88ac004,
-  0x5d71e979, 0xa88629a5, 0x5d6d9e1b, 0xa881937c, 0x5d695283, 0xa87cfd8a,
-    0x5d6506b2, 0xa87867cd,
-  0x5d60baa7, 0xa873d246, 0x5d5c6e62, 0xa86f3cf6, 0x5d5821e4, 0xa86aa7db,
-    0x5d53d52d, 0xa86612f6,
-  0x5d4f883b, 0xa8617e48, 0x5d4b3b10, 0xa85ce9cf, 0x5d46edac, 0xa858558d,
-    0x5d42a00e, 0xa853c180,
-  0x5d3e5237, 0xa84f2daa, 0x5d3a0426, 0xa84a9a0a, 0x5d35b5db, 0xa84606a0,
-    0x5d316757, 0xa841736c,
-  0x5d2d189a, 0xa83ce06e, 0x5d28c9a3, 0xa8384da6, 0x5d247a72, 0xa833bb14,
-    0x5d202b09, 0xa82f28b9,
-  0x5d1bdb65, 0xa82a9693, 0x5d178b89, 0xa82604a4, 0x5d133b72, 0xa82172eb,
-    0x5d0eeb23, 0xa81ce169,
-  0x5d0a9a9a, 0xa818501c, 0x5d0649d7, 0xa813bf06, 0x5d01f8dc, 0xa80f2e26,
-    0x5cfda7a7, 0xa80a9d7c,
-  0x5cf95638, 0xa8060d08, 0x5cf50490, 0xa8017ccb, 0x5cf0b2af, 0xa7fcecc4,
-    0x5cec6095, 0xa7f85cf3,
-  0x5ce80e41, 0xa7f3cd59, 0x5ce3bbb4, 0xa7ef3df5, 0x5cdf68ed, 0xa7eaaec7,
-    0x5cdb15ed, 0xa7e61fd0,
-  0x5cd6c2b5, 0xa7e1910f, 0x5cd26f42, 0xa7dd0284, 0x5cce1b97, 0xa7d8742f,
-    0x5cc9c7b2, 0xa7d3e611,
-  0x5cc57394, 0xa7cf582a, 0x5cc11f3d, 0xa7caca79, 0x5cbccaac, 0xa7c63cfe,
-    0x5cb875e3, 0xa7c1afb9,
-  0x5cb420e0, 0xa7bd22ac, 0x5cafcba4, 0xa7b895d4, 0x5cab762f, 0xa7b40933,
-    0x5ca72080, 0xa7af7cc8,
-  0x5ca2ca99, 0xa7aaf094, 0x5c9e7478, 0xa7a66497, 0x5c9a1e1e, 0xa7a1d8d0,
-    0x5c95c78b, 0xa79d4d3f,
-  0x5c9170bf, 0xa798c1e5, 0x5c8d19ba, 0xa79436c1, 0x5c88c27c, 0xa78fabd4,
-    0x5c846b05, 0xa78b211e,
-  0x5c801354, 0xa786969e, 0x5c7bbb6b, 0xa7820c55, 0x5c776348, 0xa77d8242,
-    0x5c730aed, 0xa778f866,
-  0x5c6eb258, 0xa7746ec0, 0x5c6a598b, 0xa76fe551, 0x5c660084, 0xa76b5c19,
-    0x5c61a745, 0xa766d317,
-  0x5c5d4dcc, 0xa7624a4d, 0x5c58f41a, 0xa75dc1b8, 0x5c549a30, 0xa759395b,
-    0x5c50400d, 0xa754b134,
-  0x5c4be5b0, 0xa7502943, 0x5c478b1b, 0xa74ba18a, 0x5c43304d, 0xa7471a07,
-    0x5c3ed545, 0xa74292bb,
-  0x5c3a7a05, 0xa73e0ba5, 0x5c361e8c, 0xa73984c7, 0x5c31c2db, 0xa734fe1f,
-    0x5c2d66f0, 0xa73077ae,
-  0x5c290acc, 0xa72bf174, 0x5c24ae70, 0xa7276b70, 0x5c2051db, 0xa722e5a3,
-    0x5c1bf50d, 0xa71e600d,
-  0x5c179806, 0xa719daae, 0x5c133ac6, 0xa7155586, 0x5c0edd4e, 0xa710d095,
-    0x5c0a7f9c, 0xa70c4bda,
-  0x5c0621b2, 0xa707c757, 0x5c01c38f, 0xa703430a, 0x5bfd6534, 0xa6febef4,
-    0x5bf906a0, 0xa6fa3b15,
-  0x5bf4a7d2, 0xa6f5b76d, 0x5bf048cd, 0xa6f133fc, 0x5bebe98e, 0xa6ecb0c2,
-    0x5be78a17, 0xa6e82dbe,
-  0x5be32a67, 0xa6e3aaf2, 0x5bdeca7f, 0xa6df285d, 0x5bda6a5d, 0xa6daa5fe,
-    0x5bd60a03, 0xa6d623d7,
-  0x5bd1a971, 0xa6d1a1e7, 0x5bcd48a6, 0xa6cd202d, 0x5bc8e7a2, 0xa6c89eab,
-    0x5bc48666, 0xa6c41d60,
-  0x5bc024f0, 0xa6bf9c4b, 0x5bbbc343, 0xa6bb1b6e, 0x5bb7615d, 0xa6b69ac8,
-    0x5bb2ff3e, 0xa6b21a59,
-  0x5bae9ce7, 0xa6ad9a21, 0x5baa3a57, 0xa6a91a20, 0x5ba5d78e, 0xa6a49a56,
-    0x5ba1748d, 0xa6a01ac4,
-  0x5b9d1154, 0xa69b9b68, 0x5b98ade2, 0xa6971c44, 0x5b944a37, 0xa6929d57,
-    0x5b8fe654, 0xa68e1ea1,
-  0x5b8b8239, 0xa689a022, 0x5b871de5, 0xa68521da, 0x5b82b958, 0xa680a3ca,
-    0x5b7e5493, 0xa67c25f0,
-  0x5b79ef96, 0xa677a84e, 0x5b758a60, 0xa6732ae3, 0x5b7124f2, 0xa66eadb0,
-    0x5b6cbf4c, 0xa66a30b3,
-  0x5b68596d, 0xa665b3ee, 0x5b63f355, 0xa6613760, 0x5b5f8d06, 0xa65cbb0a,
-    0x5b5b267e, 0xa6583eeb,
-  0x5b56bfbd, 0xa653c303, 0x5b5258c4, 0xa64f4752, 0x5b4df193, 0xa64acbd9,
-    0x5b498a2a, 0xa6465097,
-  0x5b452288, 0xa641d58c, 0x5b40baae, 0xa63d5ab9, 0x5b3c529c, 0xa638e01d,
-    0x5b37ea51, 0xa63465b9,
-  0x5b3381ce, 0xa62feb8b, 0x5b2f1913, 0xa62b7196, 0x5b2ab020, 0xa626f7d7,
-    0x5b2646f4, 0xa6227e50,
-  0x5b21dd90, 0xa61e0501, 0x5b1d73f4, 0xa6198be9, 0x5b190a20, 0xa6151308,
-    0x5b14a014, 0xa6109a5f,
-  0x5b1035cf, 0xa60c21ee, 0x5b0bcb52, 0xa607a9b4, 0x5b07609d, 0xa60331b1,
-    0x5b02f5b0, 0xa5feb9e6,
-  0x5afe8a8b, 0xa5fa4252, 0x5afa1f2e, 0xa5f5caf6, 0x5af5b398, 0xa5f153d2,
-    0x5af147ca, 0xa5ecdce5,
-  0x5aecdbc5, 0xa5e8662f, 0x5ae86f87, 0xa5e3efb1, 0x5ae40311, 0xa5df796b,
-    0x5adf9663, 0xa5db035c,
-  0x5adb297d, 0xa5d68d85, 0x5ad6bc5f, 0xa5d217e6, 0x5ad24f09, 0xa5cda27e,
-    0x5acde17b, 0xa5c92d4e,
-  0x5ac973b5, 0xa5c4b855, 0x5ac505b7, 0xa5c04395, 0x5ac09781, 0xa5bbcf0b,
-    0x5abc2912, 0xa5b75aba,
-  0x5ab7ba6c, 0xa5b2e6a0, 0x5ab34b8e, 0xa5ae72be, 0x5aaedc78, 0xa5a9ff14,
-    0x5aaa6d2b, 0xa5a58ba1,
-  0x5aa5fda5, 0xa5a11866, 0x5aa18de7, 0xa59ca563, 0x5a9d1df1, 0xa5983297,
-    0x5a98adc4, 0xa593c004,
-  0x5a943d5e, 0xa58f4da8, 0x5a8fccc1, 0xa58adb84, 0x5a8b5bec, 0xa5866997,
-    0x5a86eadf, 0xa581f7e3,
-  0x5a82799a, 0xa57d8666, 0x5a7e081d, 0xa5791521, 0x5a799669, 0xa574a414,
-    0x5a75247c, 0xa570333f,
-  0x5a70b258, 0xa56bc2a2, 0x5a6c3ffc, 0xa567523c, 0x5a67cd69, 0xa562e20f,
-    0x5a635a9d, 0xa55e7219,
-  0x5a5ee79a, 0xa55a025b, 0x5a5a745f, 0xa55592d5, 0x5a5600ec, 0xa5512388,
-    0x5a518d42, 0xa54cb472,
-  0x5a4d1960, 0xa5484594, 0x5a48a546, 0xa543d6ee, 0x5a4430f5, 0xa53f687f,
-    0x5a3fbc6b, 0xa53afa49,
-  0x5a3b47ab, 0xa5368c4b, 0x5a36d2b2, 0xa5321e85, 0x5a325d82, 0xa52db0f7,
-    0x5a2de81a, 0xa52943a1,
-  0x5a29727b, 0xa524d683, 0x5a24fca4, 0xa520699d, 0x5a208695, 0xa51bfcef,
-    0x5a1c104f, 0xa5179079,
-  0x5a1799d1, 0xa513243b, 0x5a13231b, 0xa50eb836, 0x5a0eac2e, 0xa50a4c68,
-    0x5a0a350a, 0xa505e0d2,
-  0x5a05bdae, 0xa5017575, 0x5a01461a, 0xa4fd0a50, 0x59fcce4f, 0xa4f89f63,
-    0x59f8564c, 0xa4f434ae,
-  0x59f3de12, 0xa4efca31, 0x59ef65a1, 0xa4eb5fec, 0x59eaecf8, 0xa4e6f5e0,
-    0x59e67417, 0xa4e28c0c,
-  0x59e1faff, 0xa4de2270, 0x59dd81b0, 0xa4d9b90c, 0x59d90829, 0xa4d54fe0,
-    0x59d48e6a, 0xa4d0e6ed,
-  0x59d01475, 0xa4cc7e32, 0x59cb9a47, 0xa4c815af, 0x59c71fe3, 0xa4c3ad64,
-    0x59c2a547, 0xa4bf4552,
-  0x59be2a74, 0xa4badd78, 0x59b9af69, 0xa4b675d6, 0x59b53427, 0xa4b20e6d,
-    0x59b0b8ae, 0xa4ada73c,
-  0x59ac3cfd, 0xa4a94043, 0x59a7c115, 0xa4a4d982, 0x59a344f6, 0xa4a072fa,
-    0x599ec8a0, 0xa49c0cab,
-  0x599a4c12, 0xa497a693, 0x5995cf4d, 0xa49340b4, 0x59915250, 0xa48edb0e,
-    0x598cd51d, 0xa48a75a0,
-  0x598857b2, 0xa486106a, 0x5983da10, 0xa481ab6d, 0x597f5c36, 0xa47d46a8,
-    0x597ade26, 0xa478e21b,
-  0x59765fde, 0xa4747dc7, 0x5971e15f, 0xa47019ac, 0x596d62a9, 0xa46bb5c9,
-    0x5968e3bc, 0xa467521e,
-  0x59646498, 0xa462eeac, 0x595fe53c, 0xa45e8b73, 0x595b65aa, 0xa45a2872,
-    0x5956e5e0, 0xa455c5a9,
-  0x595265df, 0xa4516319, 0x594de5a7, 0xa44d00c2, 0x59496538, 0xa4489ea3,
-    0x5944e492, 0xa4443cbd,
-  0x594063b5, 0xa43fdb10, 0x593be2a0, 0xa43b799a, 0x59376155, 0xa437185e,
-    0x5932dfd3, 0xa432b75a,
-  0x592e5e19, 0xa42e568f, 0x5929dc29, 0xa429f5fd, 0x59255a02, 0xa42595a3,
-    0x5920d7a3, 0xa4213581,
-  0x591c550e, 0xa41cd599, 0x5917d242, 0xa41875e9, 0x59134f3e, 0xa4141672,
-    0x590ecc04, 0xa40fb733,
-  0x590a4893, 0xa40b582e, 0x5905c4eb, 0xa406f960, 0x5901410c, 0xa4029acc,
-    0x58fcbcf6, 0xa3fe3c71,
-  0x58f838a9, 0xa3f9de4e, 0x58f3b426, 0xa3f58064, 0x58ef2f6b, 0xa3f122b2,
-    0x58eaaa7a, 0xa3ecc53a,
-  0x58e62552, 0xa3e867fa, 0x58e19ff3, 0xa3e40af3, 0x58dd1a5d, 0xa3dfae25,
-    0x58d89490, 0xa3db5190,
-  0x58d40e8c, 0xa3d6f534, 0x58cf8852, 0xa3d29910, 0x58cb01e1, 0xa3ce3d25,
-    0x58c67b39, 0xa3c9e174,
-  0x58c1f45b, 0xa3c585fb, 0x58bd6d45, 0xa3c12abb, 0x58b8e5f9, 0xa3bccfb3,
-    0x58b45e76, 0xa3b874e5,
-  0x58afd6bd, 0xa3b41a50, 0x58ab4ecc, 0xa3afbff3, 0x58a6c6a5, 0xa3ab65d0,
-    0x58a23e48, 0xa3a70be6,
-  0x589db5b3, 0xa3a2b234, 0x58992ce9, 0xa39e58bb, 0x5894a3e7, 0xa399ff7c,
-    0x58901aaf, 0xa395a675,
-  0x588b9140, 0xa3914da8, 0x5887079a, 0xa38cf513, 0x58827dbe, 0xa3889cb8,
-    0x587df3ab, 0xa3844495,
-  0x58796962, 0xa37fecac, 0x5874dee2, 0xa37b94fb, 0x5870542c, 0xa3773d84,
-    0x586bc93f, 0xa372e646,
-  0x58673e1b, 0xa36e8f41, 0x5862b2c1, 0xa36a3875, 0x585e2730, 0xa365e1e2,
-    0x58599b69, 0xa3618b88,
-  0x58550f6c, 0xa35d3567, 0x58508338, 0xa358df80, 0x584bf6cd, 0xa35489d1,
-    0x58476a2c, 0xa350345c,
-  0x5842dd54, 0xa34bdf20, 0x583e5047, 0xa3478a1d, 0x5839c302, 0xa3433554,
-    0x58353587, 0xa33ee0c3,
-  0x5830a7d6, 0xa33a8c6c, 0x582c19ef, 0xa336384e, 0x58278bd1, 0xa331e469,
-    0x5822fd7c, 0xa32d90be,
-  0x581e6ef1, 0xa3293d4b, 0x5819e030, 0xa324ea13, 0x58155139, 0xa3209713,
-    0x5810c20b, 0xa31c444c,
-  0x580c32a7, 0xa317f1bf, 0x5807a30d, 0xa3139f6b, 0x5803133c, 0xa30f4d51,
-    0x57fe8335, 0xa30afb70,
-  0x57f9f2f8, 0xa306a9c8, 0x57f56284, 0xa3025859, 0x57f0d1da, 0xa2fe0724,
-    0x57ec40fa, 0xa2f9b629,
-  0x57e7afe4, 0xa2f56566, 0x57e31e97, 0xa2f114dd, 0x57de8d15, 0xa2ecc48e,
-    0x57d9fb5c, 0xa2e87477,
-  0x57d5696d, 0xa2e4249b, 0x57d0d747, 0xa2dfd4f7, 0x57cc44ec, 0xa2db858e,
-    0x57c7b25a, 0xa2d7365d,
-  0x57c31f92, 0xa2d2e766, 0x57be8c94, 0xa2ce98a9, 0x57b9f960, 0xa2ca4a25,
-    0x57b565f6, 0xa2c5fbda,
-  0x57b0d256, 0xa2c1adc9, 0x57ac3e80, 0xa2bd5ff2, 0x57a7aa73, 0xa2b91254,
-    0x57a31631, 0xa2b4c4f0,
-  0x579e81b8, 0xa2b077c5, 0x5799ed0a, 0xa2ac2ad3, 0x57955825, 0xa2a7de1c,
-    0x5790c30a, 0xa2a3919e,
-  0x578c2dba, 0xa29f4559, 0x57879833, 0xa29af94e, 0x57830276, 0xa296ad7d,
-    0x577e6c84, 0xa29261e5,
-  0x5779d65b, 0xa28e1687, 0x57753ffc, 0xa289cb63, 0x5770a968, 0xa2858078,
-    0x576c129d, 0xa28135c7,
-  0x57677b9d, 0xa27ceb4f, 0x5762e467, 0xa278a111, 0x575e4cfa, 0xa274570d,
-    0x5759b558, 0xa2700d43,
-  0x57551d80, 0xa26bc3b2, 0x57508572, 0xa2677a5b, 0x574bed2f, 0xa263313e,
-    0x574754b5, 0xa25ee85b,
-  0x5742bc06, 0xa25a9fb1, 0x573e2320, 0xa2565741, 0x57398a05, 0xa2520f0b,
-    0x5734f0b5, 0xa24dc70f,
-  0x5730572e, 0xa2497f4c, 0x572bbd71, 0xa24537c3, 0x5727237f, 0xa240f074,
-    0x57228957, 0xa23ca95f,
-  0x571deefa, 0xa2386284, 0x57195466, 0xa2341be3, 0x5714b99d, 0xa22fd57b,
-    0x57101e9e, 0xa22b8f4d,
-  0x570b8369, 0xa2274959, 0x5706e7ff, 0xa223039f, 0x57024c5f, 0xa21ebe1f,
-    0x56fdb08a, 0xa21a78d9,
-  0x56f9147e, 0xa21633cd, 0x56f4783d, 0xa211eefb, 0x56efdbc7, 0xa20daa62,
-    0x56eb3f1a, 0xa2096604,
-  0x56e6a239, 0xa20521e0, 0x56e20521, 0xa200ddf5, 0x56dd67d4, 0xa1fc9a45,
-    0x56d8ca51, 0xa1f856ce,
-  0x56d42c99, 0xa1f41392, 0x56cf8eab, 0xa1efd08f, 0x56caf088, 0xa1eb8dc7,
-    0x56c6522f, 0xa1e74b38,
-  0x56c1b3a1, 0xa1e308e4, 0x56bd14dd, 0xa1dec6ca, 0x56b875e4, 0xa1da84e9,
-    0x56b3d6b5, 0xa1d64343,
-  0x56af3750, 0xa1d201d7, 0x56aa97b7, 0xa1cdc0a5, 0x56a5f7e7, 0xa1c97fad,
-    0x56a157e3, 0xa1c53ef0,
-  0x569cb7a8, 0xa1c0fe6c, 0x56981739, 0xa1bcbe22, 0x56937694, 0xa1b87e13,
-    0x568ed5b9, 0xa1b43e3e,
-  0x568a34a9, 0xa1affea3, 0x56859364, 0xa1abbf42, 0x5680f1ea, 0xa1a7801b,
-    0x567c503a, 0xa1a3412f,
-  0x5677ae54, 0xa19f027c, 0x56730c3a, 0xa19ac404, 0x566e69ea, 0xa19685c7,
-    0x5669c765, 0xa19247c3,
-  0x566524aa, 0xa18e09fa, 0x566081ba, 0xa189cc6b, 0x565bde95, 0xa1858f16,
-    0x56573b3b, 0xa18151fb,
-  0x565297ab, 0xa17d151b, 0x564df3e6, 0xa178d875, 0x56494fec, 0xa1749c09,
-    0x5644abbc, 0xa1705fd8,
-  0x56400758, 0xa16c23e1, 0x563b62be, 0xa167e824, 0x5636bdef, 0xa163aca2,
-    0x563218eb, 0xa15f715a,
-  0x562d73b2, 0xa15b364d, 0x5628ce43, 0xa156fb79, 0x5624289f, 0xa152c0e1,
-    0x561f82c7, 0xa14e8682,
-  0x561adcb9, 0xa14a4c5e, 0x56163676, 0xa1461275, 0x56118ffe, 0xa141d8c5,
-    0x560ce950, 0xa13d9f51,
-  0x5608426e, 0xa1396617, 0x56039b57, 0xa1352d17, 0x55fef40a, 0xa130f451,
-    0x55fa4c89, 0xa12cbbc7,
-  0x55f5a4d2, 0xa1288376, 0x55f0fce7, 0xa1244b61, 0x55ec54c6, 0xa1201385,
-    0x55e7ac71, 0xa11bdbe4,
-  0x55e303e6, 0xa117a47e, 0x55de5b27, 0xa1136d52, 0x55d9b232, 0xa10f3661,
-    0x55d50909, 0xa10affab,
-  0x55d05faa, 0xa106c92f, 0x55cbb617, 0xa10292ed, 0x55c70c4f, 0xa0fe5ce6,
-    0x55c26251, 0xa0fa271a,
-  0x55bdb81f, 0xa0f5f189, 0x55b90db8, 0xa0f1bc32, 0x55b4631d, 0xa0ed8715,
-    0x55afb84c, 0xa0e95234,
-  0x55ab0d46, 0xa0e51d8c, 0x55a6620c, 0xa0e0e920, 0x55a1b69d, 0xa0dcb4ee,
-    0x559d0af9, 0xa0d880f7,
-  0x55985f20, 0xa0d44d3b, 0x5593b312, 0xa0d019b9, 0x558f06d0, 0xa0cbe672,
-    0x558a5a58, 0xa0c7b366,
-  0x5585adad, 0xa0c38095, 0x558100cc, 0xa0bf4dfe, 0x557c53b6, 0xa0bb1ba2,
-    0x5577a66c, 0xa0b6e981,
-  0x5572f8ed, 0xa0b2b79b, 0x556e4b39, 0xa0ae85ef, 0x55699d51, 0xa0aa547e,
-    0x5564ef34, 0xa0a62348,
-  0x556040e2, 0xa0a1f24d, 0x555b925c, 0xa09dc18d, 0x5556e3a1, 0xa0999107,
-    0x555234b1, 0xa09560bc,
-  0x554d858d, 0xa09130ad, 0x5548d634, 0xa08d00d8, 0x554426a7, 0xa088d13e,
-    0x553f76e4, 0xa084a1de,
-  0x553ac6ee, 0xa08072ba, 0x553616c2, 0xa07c43d1, 0x55316663, 0xa0781522,
-    0x552cb5ce, 0xa073e6af,
-  0x55280505, 0xa06fb876, 0x55235408, 0xa06b8a78, 0x551ea2d6, 0xa0675cb6,
-    0x5519f16f, 0xa0632f2e,
-  0x55153fd4, 0xa05f01e1, 0x55108e05, 0xa05ad4cf, 0x550bdc01, 0xa056a7f9,
-    0x550729c9, 0xa0527b5d,
-  0x5502775c, 0xa04e4efc, 0x54fdc4ba, 0xa04a22d7, 0x54f911e5, 0xa045f6ec,
-    0x54f45edb, 0xa041cb3c,
-  0x54efab9c, 0xa03d9fc8, 0x54eaf829, 0xa039748e, 0x54e64482, 0xa0354990,
-    0x54e190a6, 0xa0311ecd,
-  0x54dcdc96, 0xa02cf444, 0x54d82852, 0xa028c9f7, 0x54d373d9, 0xa0249fe5,
-    0x54cebf2c, 0xa020760e,
-  0x54ca0a4b, 0xa01c4c73, 0x54c55535, 0xa0182312, 0x54c09feb, 0xa013f9ed,
-    0x54bbea6d, 0xa00fd102,
-  0x54b734ba, 0xa00ba853, 0x54b27ed3, 0xa0077fdf, 0x54adc8b8, 0xa00357a7,
-    0x54a91269, 0x9fff2fa9,
-  0x54a45be6, 0x9ffb07e7, 0x549fa52e, 0x9ff6e060, 0x549aee42, 0x9ff2b914,
-    0x54963722, 0x9fee9204,
-  0x54917fce, 0x9fea6b2f, 0x548cc845, 0x9fe64495, 0x54881089, 0x9fe21e36,
-    0x54835898, 0x9fddf812,
-  0x547ea073, 0x9fd9d22a, 0x5479e81a, 0x9fd5ac7d, 0x54752f8d, 0x9fd1870c,
-    0x547076cc, 0x9fcd61d6,
-  0x546bbdd7, 0x9fc93cdb, 0x546704ae, 0x9fc5181b, 0x54624b50, 0x9fc0f397,
-    0x545d91bf, 0x9fbccf4f,
-  0x5458d7f9, 0x9fb8ab41, 0x54541e00, 0x9fb4876f, 0x544f63d2, 0x9fb063d9,
-    0x544aa971, 0x9fac407e,
-  0x5445eedb, 0x9fa81d5e, 0x54413412, 0x9fa3fa79, 0x543c7914, 0x9f9fd7d1,
-    0x5437bde3, 0x9f9bb563,
-  0x5433027d, 0x9f979331, 0x542e46e4, 0x9f93713b, 0x54298b17, 0x9f8f4f80,
-    0x5424cf16, 0x9f8b2e00,
-  0x542012e1, 0x9f870cbc, 0x541b5678, 0x9f82ebb4, 0x541699db, 0x9f7ecae7,
-    0x5411dd0a, 0x9f7aaa55,
-  0x540d2005, 0x9f7689ff, 0x540862cd, 0x9f7269e5, 0x5403a561, 0x9f6e4a06,
-    0x53fee7c1, 0x9f6a2a63,
-  0x53fa29ed, 0x9f660afb, 0x53f56be5, 0x9f61ebcf, 0x53f0adaa, 0x9f5dccde,
-    0x53ebef3a, 0x9f59ae29,
-  0x53e73097, 0x9f558fb0, 0x53e271c0, 0x9f517173, 0x53ddb2b6, 0x9f4d5371,
-    0x53d8f378, 0x9f4935aa,
-  0x53d43406, 0x9f45181f, 0x53cf7460, 0x9f40fad0, 0x53cab486, 0x9f3cddbd,
-    0x53c5f479, 0x9f38c0e5,
-  0x53c13439, 0x9f34a449, 0x53bc73c4, 0x9f3087e9, 0x53b7b31c, 0x9f2c6bc5,
-    0x53b2f240, 0x9f284fdc,
-  0x53ae3131, 0x9f24342f, 0x53a96fee, 0x9f2018bd, 0x53a4ae77, 0x9f1bfd88,
-    0x539feccd, 0x9f17e28e,
-  0x539b2af0, 0x9f13c7d0, 0x539668de, 0x9f0fad4e, 0x5391a699, 0x9f0b9307,
-    0x538ce421, 0x9f0778fd,
-  0x53882175, 0x9f035f2e, 0x53835e95, 0x9eff459b, 0x537e9b82, 0x9efb2c44,
-    0x5379d83c, 0x9ef71328,
-  0x537514c2, 0x9ef2fa49, 0x53705114, 0x9eeee1a5, 0x536b8d33, 0x9eeac93e,
-    0x5366c91f, 0x9ee6b112,
-  0x536204d7, 0x9ee29922, 0x535d405c, 0x9ede816e, 0x53587bad, 0x9eda69f6,
-    0x5353b6cb, 0x9ed652ba,
-  0x534ef1b5, 0x9ed23bb9, 0x534a2c6c, 0x9ece24f5, 0x534566f0, 0x9eca0e6d,
-    0x5340a140, 0x9ec5f820,
-  0x533bdb5d, 0x9ec1e210, 0x53371547, 0x9ebdcc3b, 0x53324efd, 0x9eb9b6a3,
-    0x532d8880, 0x9eb5a146,
-  0x5328c1d0, 0x9eb18c26, 0x5323faec, 0x9ead7742, 0x531f33d5, 0x9ea96299,
-    0x531a6c8b, 0x9ea54e2d,
-  0x5315a50e, 0x9ea139fd, 0x5310dd5d, 0x9e9d2608, 0x530c1579, 0x9e991250,
-    0x53074d62, 0x9e94fed4,
-  0x53028518, 0x9e90eb94, 0x52fdbc9a, 0x9e8cd890, 0x52f8f3e9, 0x9e88c5c9,
-    0x52f42b05, 0x9e84b33d,
-  0x52ef61ee, 0x9e80a0ee, 0x52ea98a4, 0x9e7c8eda, 0x52e5cf27, 0x9e787d03,
-    0x52e10576, 0x9e746b68,
-  0x52dc3b92, 0x9e705a09, 0x52d7717b, 0x9e6c48e7, 0x52d2a732, 0x9e683800,
-    0x52cddcb5, 0x9e642756,
-  0x52c91204, 0x9e6016e8, 0x52c44721, 0x9e5c06b6, 0x52bf7c0b, 0x9e57f6c0,
-    0x52bab0c2, 0x9e53e707,
-  0x52b5e546, 0x9e4fd78a, 0x52b11996, 0x9e4bc849, 0x52ac4db4, 0x9e47b944,
-    0x52a7819f, 0x9e43aa7c,
-  0x52a2b556, 0x9e3f9bf0, 0x529de8db, 0x9e3b8da0, 0x52991c2d, 0x9e377f8c,
-    0x52944f4c, 0x9e3371b5,
-  0x528f8238, 0x9e2f641b, 0x528ab4f1, 0x9e2b56bc, 0x5285e777, 0x9e27499a,
-    0x528119ca, 0x9e233cb4,
-  0x527c4bea, 0x9e1f300b, 0x52777dd7, 0x9e1b239e, 0x5272af92, 0x9e17176d,
-    0x526de11a, 0x9e130b79,
-  0x5269126e, 0x9e0effc1, 0x52644390, 0x9e0af446, 0x525f7480, 0x9e06e907,
-    0x525aa53c, 0x9e02de04,
-  0x5255d5c5, 0x9dfed33e, 0x5251061c, 0x9dfac8b4, 0x524c3640, 0x9df6be67,
-    0x52476631, 0x9df2b456,
-  0x524295f0, 0x9deeaa82, 0x523dc57b, 0x9deaa0ea, 0x5238f4d4, 0x9de6978f,
-    0x523423fb, 0x9de28e70,
-  0x522f52ee, 0x9dde858e, 0x522a81af, 0x9dda7ce9, 0x5225b03d, 0x9dd6747f,
-    0x5220de99, 0x9dd26c53,
-  0x521c0cc2, 0x9dce6463, 0x52173ab8, 0x9dca5caf, 0x5212687b, 0x9dc65539,
-    0x520d960c, 0x9dc24dfe,
-  0x5208c36a, 0x9dbe4701, 0x5203f096, 0x9dba4040, 0x51ff1d8f, 0x9db639bb,
-    0x51fa4a56, 0x9db23373,
-  0x51f576ea, 0x9dae2d68, 0x51f0a34b, 0x9daa279a, 0x51ebcf7a, 0x9da62208,
-    0x51e6fb76, 0x9da21cb2,
-  0x51e22740, 0x9d9e179a, 0x51dd52d7, 0x9d9a12be, 0x51d87e3c, 0x9d960e1f,
-    0x51d3a96f, 0x9d9209bd,
-  0x51ced46e, 0x9d8e0597, 0x51c9ff3c, 0x9d8a01ae, 0x51c529d7, 0x9d85fe02,
-    0x51c0543f, 0x9d81fa92,
-  0x51bb7e75, 0x9d7df75f, 0x51b6a879, 0x9d79f469, 0x51b1d24a, 0x9d75f1b0,
-    0x51acfbe9, 0x9d71ef34,
-  0x51a82555, 0x9d6decf4, 0x51a34e8f, 0x9d69eaf1, 0x519e7797, 0x9d65e92b,
-    0x5199a06d, 0x9d61e7a2,
-  0x5194c910, 0x9d5de656, 0x518ff180, 0x9d59e546, 0x518b19bf, 0x9d55e473,
-    0x518641cb, 0x9d51e3dd,
-  0x518169a5, 0x9d4de385, 0x517c914c, 0x9d49e368, 0x5177b8c2, 0x9d45e389,
-    0x5172e005, 0x9d41e3e7,
-  0x516e0715, 0x9d3de482, 0x51692df4, 0x9d39e559, 0x516454a0, 0x9d35e66e,
-    0x515f7b1a, 0x9d31e7bf,
-  0x515aa162, 0x9d2de94d, 0x5155c778, 0x9d29eb19, 0x5150ed5c, 0x9d25ed21,
-    0x514c130d, 0x9d21ef66,
-  0x5147388c, 0x9d1df1e9, 0x51425dd9, 0x9d19f4a8, 0x513d82f4, 0x9d15f7a4,
-    0x5138a7dd, 0x9d11fadd,
-  0x5133cc94, 0x9d0dfe54, 0x512ef119, 0x9d0a0207, 0x512a156b, 0x9d0605f7,
-    0x5125398c, 0x9d020a25,
-  0x51205d7b, 0x9cfe0e8f, 0x511b8137, 0x9cfa1337, 0x5116a4c1, 0x9cf6181c,
-    0x5111c81a, 0x9cf21d3d,
-  0x510ceb40, 0x9cee229c, 0x51080e35, 0x9cea2838, 0x510330f7, 0x9ce62e11,
-    0x50fe5388, 0x9ce23427,
-  0x50f975e6, 0x9cde3a7b, 0x50f49813, 0x9cda410b, 0x50efba0d, 0x9cd647d9,
-    0x50eadbd6, 0x9cd24ee4,
-  0x50e5fd6d, 0x9cce562c, 0x50e11ed2, 0x9cca5db1, 0x50dc4005, 0x9cc66573,
-    0x50d76106, 0x9cc26d73,
-  0x50d281d5, 0x9cbe75b0, 0x50cda272, 0x9cba7e2a, 0x50c8c2de, 0x9cb686e1,
-    0x50c3e317, 0x9cb28fd5,
-  0x50bf031f, 0x9cae9907, 0x50ba22f5, 0x9caaa276, 0x50b5429a, 0x9ca6ac23,
-    0x50b0620c, 0x9ca2b60c,
-  0x50ab814d, 0x9c9ec033, 0x50a6a05c, 0x9c9aca97, 0x50a1bf39, 0x9c96d539,
-    0x509cdde4, 0x9c92e017,
-  0x5097fc5e, 0x9c8eeb34, 0x50931aa6, 0x9c8af68d, 0x508e38bd, 0x9c870224,
-    0x508956a1, 0x9c830df8,
-  0x50847454, 0x9c7f1a0a, 0x507f91d5, 0x9c7b2659, 0x507aaf25, 0x9c7732e5,
-    0x5075cc43, 0x9c733faf,
-  0x5070e92f, 0x9c6f4cb6, 0x506c05ea, 0x9c6b59fa, 0x50672273, 0x9c67677c,
-    0x50623ecb, 0x9c63753c,
-  0x505d5af1, 0x9c5f8339, 0x505876e5, 0x9c5b9173, 0x505392a8, 0x9c579feb,
-    0x504eae39, 0x9c53aea0,
-  0x5049c999, 0x9c4fbd93, 0x5044e4c7, 0x9c4bccc3, 0x503fffc4, 0x9c47dc31,
-    0x503b1a8f, 0x9c43ebdc,
-  0x50363529, 0x9c3ffbc5, 0x50314f91, 0x9c3c0beb, 0x502c69c8, 0x9c381c4f,
-    0x502783cd, 0x9c342cf0,
-  0x50229da1, 0x9c303dcf, 0x501db743, 0x9c2c4eec, 0x5018d0b4, 0x9c286046,
-    0x5013e9f4, 0x9c2471de,
-  0x500f0302, 0x9c2083b3, 0x500a1bdf, 0x9c1c95c6, 0x5005348a, 0x9c18a816,
-    0x50004d04, 0x9c14baa4,
-  0x4ffb654d, 0x9c10cd70, 0x4ff67d64, 0x9c0ce07a, 0x4ff1954b, 0x9c08f3c1,
-    0x4fecacff, 0x9c050745,
-  0x4fe7c483, 0x9c011b08, 0x4fe2dbd5, 0x9bfd2f08, 0x4fddf2f6, 0x9bf94346,
-    0x4fd909e5, 0x9bf557c1,
-  0x4fd420a4, 0x9bf16c7a, 0x4fcf3731, 0x9bed8171, 0x4fca4d8d, 0x9be996a6,
-    0x4fc563b7, 0x9be5ac18,
-  0x4fc079b1, 0x9be1c1c8, 0x4fbb8f79, 0x9bddd7b6, 0x4fb6a510, 0x9bd9ede2,
-    0x4fb1ba76, 0x9bd6044b,
-  0x4faccfab, 0x9bd21af3, 0x4fa7e4af, 0x9bce31d8, 0x4fa2f981, 0x9bca48fa,
-    0x4f9e0e22, 0x9bc6605b,
-  0x4f992293, 0x9bc277fa, 0x4f9436d2, 0x9bbe8fd6, 0x4f8f4ae0, 0x9bbaa7f0,
-    0x4f8a5ebd, 0x9bb6c048,
-  0x4f857269, 0x9bb2d8de, 0x4f8085e4, 0x9baef1b2, 0x4f7b992d, 0x9bab0ac3,
-    0x4f76ac46, 0x9ba72413,
-  0x4f71bf2e, 0x9ba33da0, 0x4f6cd1e5, 0x9b9f576b, 0x4f67e46a, 0x9b9b7174,
-    0x4f62f6bf, 0x9b978bbc,
-  0x4f5e08e3, 0x9b93a641, 0x4f591ad6, 0x9b8fc104, 0x4f542c98, 0x9b8bdc05,
-    0x4f4f3e29, 0x9b87f744,
-  0x4f4a4f89, 0x9b8412c1, 0x4f4560b8, 0x9b802e7b, 0x4f4071b6, 0x9b7c4a74,
-    0x4f3b8284, 0x9b7866ab,
-  0x4f369320, 0x9b748320, 0x4f31a38c, 0x9b709fd3, 0x4f2cb3c7, 0x9b6cbcc4,
-    0x4f27c3d1, 0x9b68d9f3,
-  0x4f22d3aa, 0x9b64f760, 0x4f1de352, 0x9b61150b, 0x4f18f2c9, 0x9b5d32f4,
-    0x4f140210, 0x9b59511c,
-  0x4f0f1126, 0x9b556f81, 0x4f0a200b, 0x9b518e24, 0x4f052ec0, 0x9b4dad06,
-    0x4f003d43, 0x9b49cc26,
-  0x4efb4b96, 0x9b45eb83, 0x4ef659b8, 0x9b420b1f, 0x4ef167aa, 0x9b3e2af9,
-    0x4eec756b, 0x9b3a4b11,
-  0x4ee782fb, 0x9b366b68, 0x4ee2905a, 0x9b328bfc, 0x4edd9d89, 0x9b2eaccf,
-    0x4ed8aa87, 0x9b2acde0,
-  0x4ed3b755, 0x9b26ef2f, 0x4ecec3f2, 0x9b2310bc, 0x4ec9d05e, 0x9b1f3288,
-    0x4ec4dc99, 0x9b1b5492,
-  0x4ebfe8a5, 0x9b1776da, 0x4ebaf47f, 0x9b139960, 0x4eb60029, 0x9b0fbc24,
-    0x4eb10ba2, 0x9b0bdf27,
-  0x4eac16eb, 0x9b080268, 0x4ea72203, 0x9b0425e8, 0x4ea22ceb, 0x9b0049a5,
-    0x4e9d37a3, 0x9afc6da1,
-  0x4e984229, 0x9af891db, 0x4e934c80, 0x9af4b654, 0x4e8e56a5, 0x9af0db0b,
-    0x4e89609b, 0x9aed0000,
-  0x4e846a60, 0x9ae92533, 0x4e7f73f4, 0x9ae54aa5, 0x4e7a7d58, 0x9ae17056,
-    0x4e75868c, 0x9add9644,
-  0x4e708f8f, 0x9ad9bc71, 0x4e6b9862, 0x9ad5e2dd, 0x4e66a105, 0x9ad20987,
-    0x4e61a977, 0x9ace306f,
-  0x4e5cb1b9, 0x9aca5795, 0x4e57b9ca, 0x9ac67efb, 0x4e52c1ab, 0x9ac2a69e,
-    0x4e4dc95c, 0x9abece80,
-  0x4e48d0dd, 0x9abaf6a1, 0x4e43d82d, 0x9ab71eff, 0x4e3edf4d, 0x9ab3479d,
-    0x4e39e63d, 0x9aaf7079,
-  0x4e34ecfc, 0x9aab9993, 0x4e2ff38b, 0x9aa7c2ec, 0x4e2af9ea, 0x9aa3ec83,
-    0x4e260019, 0x9aa01659,
-  0x4e210617, 0x9a9c406e, 0x4e1c0be6, 0x9a986ac1, 0x4e171184, 0x9a949552,
-    0x4e1216f2, 0x9a90c022,
-  0x4e0d1c30, 0x9a8ceb31, 0x4e08213e, 0x9a89167e, 0x4e03261b, 0x9a85420a,
-    0x4dfe2ac9, 0x9a816dd5,
-  0x4df92f46, 0x9a7d99de, 0x4df43393, 0x9a79c625, 0x4def37b0, 0x9a75f2ac,
-    0x4dea3b9d, 0x9a721f71,
-  0x4de53f5a, 0x9a6e4c74, 0x4de042e7, 0x9a6a79b6, 0x4ddb4644, 0x9a66a737,
-    0x4dd64971, 0x9a62d4f7,
-  0x4dd14c6e, 0x9a5f02f5, 0x4dcc4f3b, 0x9a5b3132, 0x4dc751d8, 0x9a575fae,
-    0x4dc25445, 0x9a538e68,
-  0x4dbd5682, 0x9a4fbd61, 0x4db8588f, 0x9a4bec99, 0x4db35a6c, 0x9a481c0f,
-    0x4dae5c19, 0x9a444bc5,
-  0x4da95d96, 0x9a407bb9, 0x4da45ee3, 0x9a3cabeb, 0x4d9f6001, 0x9a38dc5d,
-    0x4d9a60ee, 0x9a350d0d,
-  0x4d9561ac, 0x9a313dfc, 0x4d90623a, 0x9a2d6f2a, 0x4d8b6298, 0x9a29a097,
-    0x4d8662c6, 0x9a25d243,
-  0x4d8162c4, 0x9a22042d, 0x4d7c6293, 0x9a1e3656, 0x4d776231, 0x9a1a68be,
-    0x4d7261a0, 0x9a169b65,
-  0x4d6d60df, 0x9a12ce4b, 0x4d685fef, 0x9a0f016f, 0x4d635ece, 0x9a0b34d3,
-    0x4d5e5d7e, 0x9a076875,
-  0x4d595bfe, 0x9a039c57, 0x4d545a4f, 0x99ffd077, 0x4d4f5870, 0x99fc04d6,
-    0x4d4a5661, 0x99f83974,
-  0x4d455422, 0x99f46e51, 0x4d4051b4, 0x99f0a36d, 0x4d3b4f16, 0x99ecd8c8,
-    0x4d364c48, 0x99e90e62,
-  0x4d31494b, 0x99e5443b, 0x4d2c461e, 0x99e17a53, 0x4d2742c2, 0x99ddb0aa,
-    0x4d223f36, 0x99d9e73f,
-  0x4d1d3b7a, 0x99d61e14, 0x4d18378f, 0x99d25528, 0x4d133374, 0x99ce8c7b,
-    0x4d0e2f2a, 0x99cac40d,
-  0x4d092ab0, 0x99c6fbde, 0x4d042607, 0x99c333ee, 0x4cff212e, 0x99bf6c3d,
-    0x4cfa1c26, 0x99bba4cb,
-  0x4cf516ee, 0x99b7dd99, 0x4cf01187, 0x99b416a5, 0x4ceb0bf0, 0x99b04ff0,
-    0x4ce6062a, 0x99ac897b,
-  0x4ce10034, 0x99a8c345, 0x4cdbfa0f, 0x99a4fd4d, 0x4cd6f3bb, 0x99a13795,
-    0x4cd1ed37, 0x999d721c,
-  0x4ccce684, 0x9999ace3, 0x4cc7dfa1, 0x9995e7e8, 0x4cc2d88f, 0x9992232d,
-    0x4cbdd14e, 0x998e5eb1,
-  0x4cb8c9dd, 0x998a9a74, 0x4cb3c23d, 0x9986d676, 0x4caeba6e, 0x998312b7,
-    0x4ca9b26f, 0x997f4f38,
-  0x4ca4aa41, 0x997b8bf8, 0x4c9fa1e4, 0x9977c8f7, 0x4c9a9958, 0x99740635,
-    0x4c95909c, 0x997043b2,
-  0x4c9087b1, 0x996c816f, 0x4c8b7e97, 0x9968bf6b, 0x4c86754e, 0x9964fda7,
-    0x4c816bd5, 0x99613c22,
-  0x4c7c622d, 0x995d7adc, 0x4c775856, 0x9959b9d5, 0x4c724e50, 0x9955f90d,
-    0x4c6d441b, 0x99523885,
-  0x4c6839b7, 0x994e783d, 0x4c632f23, 0x994ab833, 0x4c5e2460, 0x9946f869,
-    0x4c59196f, 0x994338df,
-  0x4c540e4e, 0x993f7993, 0x4c4f02fe, 0x993bba87, 0x4c49f77f, 0x9937fbbb,
-    0x4c44ebd1, 0x99343d2e,
-  0x4c3fdff4, 0x99307ee0, 0x4c3ad3e7, 0x992cc0d2, 0x4c35c7ac, 0x99290303,
-    0x4c30bb42, 0x99254574,
-  0x4c2baea9, 0x99218824, 0x4c26a1e1, 0x991dcb13, 0x4c2194e9, 0x991a0e42,
-    0x4c1c87c3, 0x991651b1,
-  0x4c177a6e, 0x9912955f, 0x4c126cea, 0x990ed94c, 0x4c0d5f37, 0x990b1d79,
-    0x4c085156, 0x990761e5,
-  0x4c034345, 0x9903a691, 0x4bfe3505, 0x98ffeb7d, 0x4bf92697, 0x98fc30a8,
-    0x4bf417f9, 0x98f87612,
-  0x4bef092d, 0x98f4bbbc, 0x4be9fa32, 0x98f101a6, 0x4be4eb08, 0x98ed47cf,
-    0x4bdfdbaf, 0x98e98e38,
-  0x4bdacc28, 0x98e5d4e0, 0x4bd5bc72, 0x98e21bc8, 0x4bd0ac8d, 0x98de62f0,
-    0x4bcb9c79, 0x98daaa57,
-  0x4bc68c36, 0x98d6f1fe, 0x4bc17bc5, 0x98d339e4, 0x4bbc6b25, 0x98cf820b,
-    0x4bb75a56, 0x98cbca70,
-  0x4bb24958, 0x98c81316, 0x4bad382c, 0x98c45bfb, 0x4ba826d1, 0x98c0a520,
-    0x4ba31548, 0x98bcee84,
-  0x4b9e0390, 0x98b93828, 0x4b98f1a9, 0x98b5820c, 0x4b93df93, 0x98b1cc30,
-    0x4b8ecd4f, 0x98ae1693,
-  0x4b89badd, 0x98aa6136, 0x4b84a83b, 0x98a6ac19, 0x4b7f956b, 0x98a2f73c,
-    0x4b7a826d, 0x989f429e,
-  0x4b756f40, 0x989b8e40, 0x4b705be4, 0x9897da22, 0x4b6b485a, 0x98942643,
-    0x4b6634a2, 0x989072a5,
-  0x4b6120bb, 0x988cbf46, 0x4b5c0ca5, 0x98890c27, 0x4b56f861, 0x98855948,
-    0x4b51e3ee, 0x9881a6a9,
-  0x4b4ccf4d, 0x987df449, 0x4b47ba7e, 0x987a422a, 0x4b42a580, 0x9876904a,
-    0x4b3d9053, 0x9872deaa,
-  0x4b387af9, 0x986f2d4a, 0x4b336570, 0x986b7c2a, 0x4b2e4fb8, 0x9867cb4a,
-    0x4b2939d2, 0x98641aa9,
-  0x4b2423be, 0x98606a49, 0x4b1f0d7b, 0x985cba28, 0x4b19f70a, 0x98590a48,
-    0x4b14e06b, 0x98555aa7,
-  0x4b0fc99d, 0x9851ab46, 0x4b0ab2a1, 0x984dfc26, 0x4b059b77, 0x984a4d45,
-    0x4b00841f, 0x98469ea4,
-  0x4afb6c98, 0x9842f043, 0x4af654e3, 0x983f4223, 0x4af13d00, 0x983b9442,
-    0x4aec24ee, 0x9837e6a1,
-  0x4ae70caf, 0x98343940, 0x4ae1f441, 0x98308c1f, 0x4adcdba5, 0x982cdf3f,
-    0x4ad7c2da, 0x9829329e,
-  0x4ad2a9e2, 0x9825863d, 0x4acd90bb, 0x9821da1d, 0x4ac87767, 0x981e2e3c,
-    0x4ac35de4, 0x981a829c,
-  0x4abe4433, 0x9816d73b, 0x4ab92a54, 0x98132c1b, 0x4ab41046, 0x980f813b,
-    0x4aaef60b, 0x980bd69b,
-  0x4aa9dba2, 0x98082c3b, 0x4aa4c10b, 0x9804821b, 0x4a9fa645, 0x9800d83c,
-    0x4a9a8b52, 0x97fd2e9c,
-  0x4a957030, 0x97f9853d, 0x4a9054e1, 0x97f5dc1e, 0x4a8b3963, 0x97f2333f,
-    0x4a861db8, 0x97ee8aa0,
-  0x4a8101de, 0x97eae242, 0x4a7be5d7, 0x97e73a23, 0x4a76c9a2, 0x97e39245,
-    0x4a71ad3e, 0x97dfeaa7,
-  0x4a6c90ad, 0x97dc4349, 0x4a6773ee, 0x97d89c2c, 0x4a625701, 0x97d4f54f,
-    0x4a5d39e6, 0x97d14eb2,
-  0x4a581c9e, 0x97cda855, 0x4a52ff27, 0x97ca0239, 0x4a4de182, 0x97c65c5c,
-    0x4a48c3b0, 0x97c2b6c1,
-  0x4a43a5b0, 0x97bf1165, 0x4a3e8782, 0x97bb6c4a, 0x4a396926, 0x97b7c76f,
-    0x4a344a9d, 0x97b422d4,
-  0x4a2f2be6, 0x97b07e7a, 0x4a2a0d01, 0x97acda60, 0x4a24edee, 0x97a93687,
-    0x4a1fcead, 0x97a592ed,
-  0x4a1aaf3f, 0x97a1ef94, 0x4a158fa3, 0x979e4c7c, 0x4a106fda, 0x979aa9a4,
-    0x4a0b4fe2, 0x9797070c,
-  0x4a062fbd, 0x979364b5, 0x4a010f6b, 0x978fc29e, 0x49fbeeea, 0x978c20c8,
-    0x49f6ce3c, 0x97887f32,
-  0x49f1ad61, 0x9784dddc, 0x49ec8c57, 0x97813cc7, 0x49e76b21, 0x977d9bf2,
-    0x49e249bc, 0x9779fb5e,
-  0x49dd282a, 0x97765b0a, 0x49d8066b, 0x9772baf7, 0x49d2e47e, 0x976f1b24,
-    0x49cdc263, 0x976b7b92,
-  0x49c8a01b, 0x9767dc41, 0x49c37da5, 0x97643d2f, 0x49be5b02, 0x97609e5f,
-    0x49b93832, 0x975cffcf,
-  0x49b41533, 0x9759617f, 0x49aef208, 0x9755c370, 0x49a9ceaf, 0x975225a1,
-    0x49a4ab28, 0x974e8813,
-  0x499f8774, 0x974aeac6, 0x499a6393, 0x97474db9, 0x49953f84, 0x9743b0ed,
-    0x49901b48, 0x97401462,
-  0x498af6df, 0x973c7817, 0x4985d248, 0x9738dc0d, 0x4980ad84, 0x97354043,
-    0x497b8892, 0x9731a4ba,
-  0x49766373, 0x972e0971, 0x49713e27, 0x972a6e6a, 0x496c18ae, 0x9726d3a3,
-    0x4966f307, 0x9723391c,
-  0x4961cd33, 0x971f9ed7, 0x495ca732, 0x971c04d2, 0x49578103, 0x97186b0d,
-    0x49525aa7, 0x9714d18a,
-  0x494d341e, 0x97113847, 0x49480d68, 0x970d9f45, 0x4942e684, 0x970a0683,
-    0x493dbf74, 0x97066e03,
-  0x49389836, 0x9702d5c3, 0x493370cb, 0x96ff3dc4, 0x492e4933, 0x96fba605,
-    0x4929216e, 0x96f80e88,
-  0x4923f97b, 0x96f4774b, 0x491ed15c, 0x96f0e04f, 0x4919a90f, 0x96ed4994,
-    0x49148095, 0x96e9b319,
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-    0x48ffdcec, 0x96db5bb8,
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-    0x48eb3672, 0x96cd0865,
-  0x48e60c62, 0x96c97432, 0x48e0e227, 0x96c5e040, 0x48dbb7be, 0x96c24c8f,
-    0x48d68d28, 0x96beb91f,
-  0x48d16265, 0x96bb25f0, 0x48cc3775, 0x96b79302, 0x48c70c59, 0x96b40055,
-    0x48c1e10f, 0x96b06de9,
-  0x48bcb599, 0x96acdbbe, 0x48b789f5, 0x96a949d3, 0x48b25e25, 0x96a5b82a,
-    0x48ad3228, 0x96a226c2,
-  0x48a805ff, 0x969e959b, 0x48a2d9a8, 0x969b04b4, 0x489dad25, 0x9697740f,
-    0x48988074, 0x9693e3ab,
-  0x48935397, 0x96905388, 0x488e268e, 0x968cc3a5, 0x4888f957, 0x96893404,
-    0x4883cbf4, 0x9685a4a4,
-  0x487e9e64, 0x96821585, 0x487970a7, 0x967e86a7, 0x487442be, 0x967af80a,
-    0x486f14a8, 0x967769af,
-  0x4869e665, 0x9673db94, 0x4864b7f5, 0x96704dba, 0x485f8959, 0x966cc022,
-    0x485a5a90, 0x966932cb,
-  0x48552b9b, 0x9665a5b4, 0x484ffc79, 0x966218df, 0x484acd2a, 0x965e8c4b,
-    0x48459daf, 0x965afff9,
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-    0x4830de05, 0x964cd139,
-  0x482badab, 0x9649462d, 0x48267d24, 0x9645bb61, 0x48214c71, 0x964230d7,
-    0x481c1b92, 0x963ea68d,
-  0x4816ea86, 0x963b1c86, 0x4811b94d, 0x963792bf, 0x480c87e8, 0x96340939,
-    0x48075657, 0x96307ff5,
-  0x48022499, 0x962cf6f2, 0x47fcf2af, 0x96296e31, 0x47f7c099, 0x9625e5b0,
-    0x47f28e56, 0x96225d71,
-  0x47ed5be6, 0x961ed574, 0x47e8294a, 0x961b4db7, 0x47e2f682, 0x9617c63c,
-    0x47ddc38e, 0x96143f02,
-  0x47d8906d, 0x9610b80a, 0x47d35d20, 0x960d3153, 0x47ce29a7, 0x9609aadd,
-    0x47c8f601, 0x960624a9,
-  0x47c3c22f, 0x96029eb6, 0x47be8e31, 0x95ff1904, 0x47b95a06, 0x95fb9394,
-    0x47b425af, 0x95f80e65,
-  0x47aef12c, 0x95f48977, 0x47a9bc7d, 0x95f104cb, 0x47a487a2, 0x95ed8061,
-    0x479f529a, 0x95e9fc38,
-  0x479a1d67, 0x95e67850, 0x4794e807, 0x95e2f4a9, 0x478fb27b, 0x95df7145,
-    0x478a7cc2, 0x95dbee21,
-  0x478546de, 0x95d86b3f, 0x478010cd, 0x95d4e89f, 0x477ada91, 0x95d16640,
-    0x4775a428, 0x95cde423,
-  0x47706d93, 0x95ca6247, 0x476b36d3, 0x95c6e0ac, 0x4765ffe6, 0x95c35f53,
-    0x4760c8cd, 0x95bfde3c,
-  0x475b9188, 0x95bc5d66, 0x47565a17, 0x95b8dcd2, 0x4751227a, 0x95b55c7f,
-    0x474beab1, 0x95b1dc6e,
-  0x4746b2bc, 0x95ae5c9f, 0x47417a9b, 0x95aadd11, 0x473c424e, 0x95a75dc4,
-    0x473709d5, 0x95a3deb9,
-  0x4731d131, 0x95a05ff0, 0x472c9860, 0x959ce169, 0x47275f63, 0x95996323,
-    0x4722263b, 0x9595e51e,
-  0x471cece7, 0x9592675c, 0x4717b367, 0x958ee9db, 0x471279ba, 0x958b6c9b,
-    0x470d3fe3, 0x9587ef9e,
-  0x470805df, 0x958472e2, 0x4702cbaf, 0x9580f667, 0x46fd9154, 0x957d7a2f,
-    0x46f856cd, 0x9579fe38,
-  0x46f31c1a, 0x95768283, 0x46ede13b, 0x9573070f, 0x46e8a631, 0x956f8bdd,
-    0x46e36afb, 0x956c10ed,
-  0x46de2f99, 0x9568963f, 0x46d8f40b, 0x95651bd2, 0x46d3b852, 0x9561a1a8,
-    0x46ce7c6d, 0x955e27bf,
-  0x46c9405c, 0x955aae17, 0x46c40420, 0x955734b2, 0x46bec7b8, 0x9553bb8e,
-    0x46b98b24, 0x955042ac,
-  0x46b44e65, 0x954cca0c, 0x46af117a, 0x954951ae, 0x46a9d464, 0x9545d992,
-    0x46a49722, 0x954261b7,
-  0x469f59b4, 0x953eea1e, 0x469a1c1b, 0x953b72c7, 0x4694de56, 0x9537fbb2,
-    0x468fa066, 0x953484df,
-  0x468a624a, 0x95310e4e, 0x46852403, 0x952d97fe, 0x467fe590, 0x952a21f1,
-    0x467aa6f2, 0x9526ac25,
-  0x46756828, 0x9523369c, 0x46702933, 0x951fc154, 0x466aea12, 0x951c4c4e,
-    0x4665aac6, 0x9518d78a,
-  0x46606b4e, 0x95156308, 0x465b2bab, 0x9511eec8, 0x4655ebdd, 0x950e7aca,
-    0x4650abe3, 0x950b070e,
-  0x464b6bbe, 0x95079394, 0x46462b6d, 0x9504205c, 0x4640eaf2, 0x9500ad66,
-    0x463baa4a, 0x94fd3ab1,
-  0x46366978, 0x94f9c83f, 0x4631287a, 0x94f6560f, 0x462be751, 0x94f2e421,
-    0x4626a5fd, 0x94ef7275,
-  0x4621647d, 0x94ec010b, 0x461c22d2, 0x94e88fe3, 0x4616e0fc, 0x94e51efd,
-    0x46119efa, 0x94e1ae59,
-  0x460c5cce, 0x94de3df8, 0x46071a76, 0x94dacdd8, 0x4601d7f3, 0x94d75dfa,
-    0x45fc9545, 0x94d3ee5f,
-  0x45f7526b, 0x94d07f05, 0x45f20f67, 0x94cd0fee, 0x45eccc37, 0x94c9a119,
-    0x45e788dc, 0x94c63286,
-  0x45e24556, 0x94c2c435, 0x45dd01a5, 0x94bf5627, 0x45d7bdc9, 0x94bbe85a,
-    0x45d279c2, 0x94b87ad0,
-  0x45cd358f, 0x94b50d87, 0x45c7f132, 0x94b1a081, 0x45c2acaa, 0x94ae33be,
-    0x45bd67f6, 0x94aac73c,
-  0x45b82318, 0x94a75afd, 0x45b2de0e, 0x94a3eeff, 0x45ad98da, 0x94a08344,
-    0x45a8537a, 0x949d17cc,
-  0x45a30df0, 0x9499ac95, 0x459dc83b, 0x949641a1, 0x4598825a, 0x9492d6ef,
-    0x45933c4f, 0x948f6c7f,
-  0x458df619, 0x948c0252, 0x4588afb8, 0x94889867, 0x4583692c, 0x94852ebe,
-    0x457e2275, 0x9481c557,
-  0x4578db93, 0x947e5c33, 0x45739487, 0x947af351, 0x456e4d4f, 0x94778ab1,
-    0x456905ed, 0x94742254,
-  0x4563be60, 0x9470ba39, 0x455e76a8, 0x946d5260, 0x45592ec6, 0x9469eaca,
-    0x4553e6b8, 0x94668376,
-  0x454e9e80, 0x94631c65, 0x4549561d, 0x945fb596, 0x45440d90, 0x945c4f09,
-    0x453ec4d7, 0x9458e8bf,
-  0x45397bf4, 0x945582b7, 0x453432e6, 0x94521cf1, 0x452ee9ae, 0x944eb76e,
-    0x4529a04b, 0x944b522d,
-  0x452456bd, 0x9447ed2f, 0x451f0d04, 0x94448873, 0x4519c321, 0x944123fa,
-    0x45147913, 0x943dbfc3,
-  0x450f2edb, 0x943a5bcf, 0x4509e478, 0x9436f81d, 0x450499eb, 0x943394ad,
-    0x44ff4f32, 0x94303180,
-  0x44fa0450, 0x942cce96, 0x44f4b943, 0x94296bee, 0x44ef6e0b, 0x94260989,
-    0x44ea22a9, 0x9422a766,
-  0x44e4d71c, 0x941f4585, 0x44df8b64, 0x941be3e8, 0x44da3f83, 0x9418828c,
-    0x44d4f376, 0x94152174,
-  0x44cfa740, 0x9411c09e, 0x44ca5adf, 0x940e600a, 0x44c50e53, 0x940affb9,
-    0x44bfc19d, 0x94079fab,
-  0x44ba74bd, 0x94043fdf, 0x44b527b2, 0x9400e056, 0x44afda7d, 0x93fd810f,
-    0x44aa8d1d, 0x93fa220b,
-  0x44a53f93, 0x93f6c34a, 0x449ff1df, 0x93f364cb, 0x449aa400, 0x93f0068f,
-    0x449555f7, 0x93eca896,
-  0x449007c4, 0x93e94adf, 0x448ab967, 0x93e5ed6b, 0x44856adf, 0x93e2903a,
-    0x44801c2d, 0x93df334c,
-  0x447acd50, 0x93dbd6a0, 0x44757e4a, 0x93d87a36, 0x44702f19, 0x93d51e10,
-    0x446adfbe, 0x93d1c22c,
-  0x44659039, 0x93ce668b, 0x44604089, 0x93cb0b2d, 0x445af0b0, 0x93c7b011,
-    0x4455a0ac, 0x93c45539,
-  0x4450507e, 0x93c0faa3, 0x444b0026, 0x93bda04f, 0x4445afa4, 0x93ba463f,
-    0x44405ef8, 0x93b6ec71,
-  0x443b0e21, 0x93b392e6, 0x4435bd21, 0x93b0399e, 0x44306bf6, 0x93ace099,
-    0x442b1aa2, 0x93a987d6,
-  0x4425c923, 0x93a62f57, 0x4420777b, 0x93a2d71a, 0x441b25a8, 0x939f7f20,
-    0x4415d3ab, 0x939c2769,
-  0x44108184, 0x9398cff5, 0x440b2f34, 0x939578c3, 0x4405dcb9, 0x939221d5,
-    0x44008a14, 0x938ecb29,
-  0x43fb3746, 0x938b74c1, 0x43f5e44d, 0x93881e9b, 0x43f0912b, 0x9384c8b8,
-    0x43eb3ddf, 0x93817318,
-  0x43e5ea68, 0x937e1dbb, 0x43e096c8, 0x937ac8a1, 0x43db42fe, 0x937773ca,
-    0x43d5ef0a, 0x93741f35,
-  0x43d09aed, 0x9370cae4, 0x43cb46a5, 0x936d76d6, 0x43c5f234, 0x936a230a,
-    0x43c09d99, 0x9366cf82,
-  0x43bb48d4, 0x93637c3d, 0x43b5f3e5, 0x9360293a, 0x43b09ecc, 0x935cd67b,
-    0x43ab498a, 0x935983ff,
-  0x43a5f41e, 0x935631c5, 0x43a09e89, 0x9352dfcf, 0x439b48c9, 0x934f8e1c,
-    0x4395f2e0, 0x934c3cab,
-  0x43909ccd, 0x9348eb7e, 0x438b4691, 0x93459a94, 0x4385f02a, 0x934249ed,
-    0x4380999b, 0x933ef989,
-  0x437b42e1, 0x933ba968, 0x4375ebfe, 0x9338598a, 0x437094f1, 0x933509f0,
-    0x436b3dbb, 0x9331ba98,
-  0x4365e65b, 0x932e6b84, 0x43608ed2, 0x932b1cb2, 0x435b371f, 0x9327ce24,
-    0x4355df42, 0x93247fd9,
-  0x4350873c, 0x932131d1, 0x434b2f0c, 0x931de40c, 0x4345d6b3, 0x931a968b,
-    0x43407e31, 0x9317494c,
-  0x433b2585, 0x9313fc51, 0x4335ccaf, 0x9310af99, 0x433073b0, 0x930d6324,
-    0x432b1a87, 0x930a16f3,
-  0x4325c135, 0x9306cb04, 0x432067ba, 0x93037f59, 0x431b0e15, 0x930033f1,
-    0x4315b447, 0x92fce8cc,
-  0x43105a50, 0x92f99deb, 0x430b002f, 0x92f6534c, 0x4305a5e5, 0x92f308f1,
-    0x43004b71, 0x92efbeda,
-  0x42faf0d4, 0x92ec7505, 0x42f5960e, 0x92e92b74, 0x42f03b1e, 0x92e5e226,
-    0x42eae005, 0x92e2991c,
-  0x42e584c3, 0x92df5054, 0x42e02958, 0x92dc07d0, 0x42dacdc3, 0x92d8bf90,
-    0x42d57205, 0x92d57792,
-  0x42d0161e, 0x92d22fd9, 0x42caba0e, 0x92cee862, 0x42c55dd4, 0x92cba12f,
-    0x42c00172, 0x92c85a3f,
-  0x42baa4e6, 0x92c51392, 0x42b54831, 0x92c1cd29, 0x42afeb53, 0x92be8703,
-    0x42aa8e4b, 0x92bb4121,
-  0x42a5311b, 0x92b7fb82, 0x429fd3c1, 0x92b4b626, 0x429a763f, 0x92b1710e,
-    0x42951893, 0x92ae2c3a,
-  0x428fbabe, 0x92aae7a8, 0x428a5cc0, 0x92a7a35a, 0x4284fe99, 0x92a45f50,
-    0x427fa049, 0x92a11b89,
-  0x427a41d0, 0x929dd806, 0x4274e32e, 0x929a94c6, 0x426f8463, 0x929751c9,
-    0x426a256f, 0x92940f10,
-  0x4264c653, 0x9290cc9b, 0x425f670d, 0x928d8a69, 0x425a079e, 0x928a487a,
-    0x4254a806, 0x928706cf,
-  0x424f4845, 0x9283c568, 0x4249e85c, 0x92808444, 0x42448849, 0x927d4363,
-    0x423f280e, 0x927a02c7,
-  0x4239c7aa, 0x9276c26d, 0x4234671d, 0x92738258, 0x422f0667, 0x92704286,
-    0x4229a588, 0x926d02f7,
-  0x42244481, 0x9269c3ac, 0x421ee350, 0x926684a5, 0x421981f7, 0x926345e1,
-    0x42142075, 0x92600761,
-  0x420ebecb, 0x925cc924, 0x42095cf7, 0x92598b2b, 0x4203fafb, 0x92564d76,
-    0x41fe98d6, 0x92531005,
-  0x41f93689, 0x924fd2d7, 0x41f3d413, 0x924c95ec, 0x41ee7174, 0x92495946,
-    0x41e90eac, 0x92461ce3,
-  0x41e3abbc, 0x9242e0c4, 0x41de48a3, 0x923fa4e8, 0x41d8e561, 0x923c6950,
-    0x41d381f7, 0x92392dfc,
-  0x41ce1e65, 0x9235f2ec, 0x41c8baa9, 0x9232b81f, 0x41c356c5, 0x922f7d96,
-    0x41bdf2b9, 0x922c4351,
-  0x41b88e84, 0x9229094f, 0x41b32a26, 0x9225cf91, 0x41adc5a0, 0x92229617,
-    0x41a860f1, 0x921f5ce1,
-  0x41a2fc1a, 0x921c23ef, 0x419d971b, 0x9218eb40, 0x419831f3, 0x9215b2d5,
-    0x4192cca2, 0x92127aae,
-  0x418d6729, 0x920f42cb, 0x41880188, 0x920c0b2c, 0x41829bbe, 0x9208d3d0,
-    0x417d35cb, 0x92059cb8,
-  0x4177cfb1, 0x920265e4, 0x4172696e, 0x91ff2f54, 0x416d0302, 0x91fbf908,
-    0x41679c6f, 0x91f8c300,
-  0x416235b2, 0x91f58d3b, 0x415ccece, 0x91f257bb, 0x415767c1, 0x91ef227e,
-    0x4152008c, 0x91ebed85,
-  0x414c992f, 0x91e8b8d0, 0x414731a9, 0x91e5845f, 0x4141c9fb, 0x91e25032,
-    0x413c6225, 0x91df1c49,
-  0x4136fa27, 0x91dbe8a4, 0x41319200, 0x91d8b542, 0x412c29b1, 0x91d58225,
-    0x4126c13a, 0x91d24f4c,
-  0x4121589b, 0x91cf1cb6, 0x411befd3, 0x91cbea65, 0x411686e4, 0x91c8b857,
-    0x41111dcc, 0x91c5868e,
-  0x410bb48c, 0x91c25508, 0x41064b24, 0x91bf23c7, 0x4100e194, 0x91bbf2c9,
-    0x40fb77dc, 0x91b8c210,
-  0x40f60dfb, 0x91b5919a, 0x40f0a3f3, 0x91b26169, 0x40eb39c3, 0x91af317c,
-    0x40e5cf6a, 0x91ac01d2,
-  0x40e064ea, 0x91a8d26d, 0x40dafa41, 0x91a5a34c, 0x40d58f71, 0x91a2746f,
-    0x40d02478, 0x919f45d6,
-  0x40cab958, 0x919c1781, 0x40c54e0f, 0x9198e970, 0x40bfe29f, 0x9195bba3,
-    0x40ba7706, 0x91928e1a,
-  0x40b50b46, 0x918f60d6, 0x40af9f5e, 0x918c33d5, 0x40aa334e, 0x91890719,
-    0x40a4c716, 0x9185daa1,
-  0x409f5ab6, 0x9182ae6d, 0x4099ee2e, 0x917f827d, 0x4094817f, 0x917c56d1,
-    0x408f14a7, 0x91792b6a,
-  0x4089a7a8, 0x91760047, 0x40843a81, 0x9172d567, 0x407ecd32, 0x916faacc,
-    0x40795fbc, 0x916c8076,
-  0x4073f21d, 0x91695663, 0x406e8457, 0x91662c95, 0x40691669, 0x9163030b,
-    0x4063a854, 0x915fd9c5,
-  0x405e3a16, 0x915cb0c3, 0x4058cbb1, 0x91598806, 0x40535d24, 0x91565f8d,
-    0x404dee70, 0x91533758,
-  0x40487f94, 0x91500f67, 0x40431090, 0x914ce7bb, 0x403da165, 0x9149c053,
-    0x40383212, 0x9146992f,
-  0x4032c297, 0x91437250, 0x402d52f5, 0x91404bb5, 0x4027e32b, 0x913d255e,
-    0x4022733a, 0x9139ff4b,
-  0x401d0321, 0x9136d97d, 0x401792e0, 0x9133b3f3, 0x40122278, 0x91308eae,
-    0x400cb1e9, 0x912d69ad,
-  0x40074132, 0x912a44f0, 0x4001d053, 0x91272078, 0x3ffc5f4d, 0x9123fc44,
-    0x3ff6ee1f, 0x9120d854,
-  0x3ff17cca, 0x911db4a9, 0x3fec0b4e, 0x911a9142, 0x3fe699aa, 0x91176e1f,
-    0x3fe127df, 0x91144b41,
-  0x3fdbb5ec, 0x911128a8, 0x3fd643d2, 0x910e0653, 0x3fd0d191, 0x910ae442,
-    0x3fcb5f28, 0x9107c276,
-  0x3fc5ec98, 0x9104a0ee, 0x3fc079e0, 0x91017faa, 0x3fbb0702, 0x90fe5eab,
-    0x3fb593fb, 0x90fb3df1,
-  0x3fb020ce, 0x90f81d7b, 0x3faaad79, 0x90f4fd4a, 0x3fa539fd, 0x90f1dd5d,
-    0x3f9fc65a, 0x90eebdb4,
-  0x3f9a5290, 0x90eb9e50, 0x3f94de9e, 0x90e87f31, 0x3f8f6a85, 0x90e56056,
-    0x3f89f645, 0x90e241bf,
-  0x3f8481dd, 0x90df236e, 0x3f7f0d4f, 0x90dc0560, 0x3f799899, 0x90d8e798,
-    0x3f7423bc, 0x90d5ca13,
-  0x3f6eaeb8, 0x90d2acd4, 0x3f69398d, 0x90cf8fd9, 0x3f63c43b, 0x90cc7322,
-    0x3f5e4ec2, 0x90c956b1,
-  0x3f58d921, 0x90c63a83, 0x3f53635a, 0x90c31e9b, 0x3f4ded6b, 0x90c002f7,
-    0x3f487755, 0x90bce797,
-  0x3f430119, 0x90b9cc7d, 0x3f3d8ab5, 0x90b6b1a6, 0x3f38142a, 0x90b39715,
-    0x3f329d79, 0x90b07cc8,
-  0x3f2d26a0, 0x90ad62c0, 0x3f27afa1, 0x90aa48fd, 0x3f22387a, 0x90a72f7e,
-    0x3f1cc12c, 0x90a41644,
-  0x3f1749b8, 0x90a0fd4e, 0x3f11d21d, 0x909de49e, 0x3f0c5a5a, 0x909acc32,
-    0x3f06e271, 0x9097b40a,
-  0x3f016a61, 0x90949c28, 0x3efbf22a, 0x9091848a, 0x3ef679cc, 0x908e6d31,
-    0x3ef10148, 0x908b561c,
-  0x3eeb889c, 0x90883f4d, 0x3ee60fca, 0x908528c2, 0x3ee096d1, 0x9082127c,
-    0x3edb1db1, 0x907efc7a,
-  0x3ed5a46b, 0x907be6be, 0x3ed02afd, 0x9078d146, 0x3ecab169, 0x9075bc13,
-    0x3ec537ae, 0x9072a725,
-  0x3ebfbdcd, 0x906f927c, 0x3eba43c4, 0x906c7e17, 0x3eb4c995, 0x906969f8,
-    0x3eaf4f40, 0x9066561d,
-  0x3ea9d4c3, 0x90634287, 0x3ea45a21, 0x90602f35, 0x3e9edf57, 0x905d1c29,
-    0x3e996467, 0x905a0962,
-  0x3e93e950, 0x9056f6df, 0x3e8e6e12, 0x9053e4a1, 0x3e88f2ae, 0x9050d2a9,
-    0x3e837724, 0x904dc0f5,
-  0x3e7dfb73, 0x904aaf86, 0x3e787f9b, 0x90479e5c, 0x3e73039d, 0x90448d76,
-    0x3e6d8778, 0x90417cd6,
-  0x3e680b2c, 0x903e6c7b, 0x3e628ebb, 0x903b5c64, 0x3e5d1222, 0x90384c93,
-    0x3e579564, 0x90353d06,
-  0x3e52187f, 0x90322dbf, 0x3e4c9b73, 0x902f1ebc, 0x3e471e41, 0x902c0fff,
-    0x3e41a0e8, 0x90290186,
-  0x3e3c2369, 0x9025f352, 0x3e36a5c4, 0x9022e564, 0x3e3127f9, 0x901fd7ba,
-    0x3e2baa07, 0x901cca55,
-  0x3e262bee, 0x9019bd36, 0x3e20adaf, 0x9016b05b, 0x3e1b2f4a, 0x9013a3c5,
-    0x3e15b0bf, 0x90109775,
-  0x3e10320d, 0x900d8b69, 0x3e0ab336, 0x900a7fa3, 0x3e053437, 0x90077422,
-    0x3dffb513, 0x900468e5,
-  0x3dfa35c8, 0x90015dee, 0x3df4b657, 0x8ffe533c, 0x3def36c0, 0x8ffb48cf,
-    0x3de9b703, 0x8ff83ea7,
-  0x3de4371f, 0x8ff534c4, 0x3ddeb716, 0x8ff22b26, 0x3dd936e6, 0x8fef21ce,
-    0x3dd3b690, 0x8fec18ba,
-  0x3dce3614, 0x8fe90fec, 0x3dc8b571, 0x8fe60763, 0x3dc334a9, 0x8fe2ff1f,
-    0x3dbdb3ba, 0x8fdff720,
-  0x3db832a6, 0x8fdcef66, 0x3db2b16b, 0x8fd9e7f2, 0x3dad300b, 0x8fd6e0c2,
-    0x3da7ae84, 0x8fd3d9d8,
-  0x3da22cd7, 0x8fd0d333, 0x3d9cab04, 0x8fcdccd3, 0x3d97290b, 0x8fcac6b9,
-    0x3d91a6ed, 0x8fc7c0e3,
-  0x3d8c24a8, 0x8fc4bb53, 0x3d86a23d, 0x8fc1b608, 0x3d811fac, 0x8fbeb103,
-    0x3d7b9cf6, 0x8fbbac42,
-  0x3d761a19, 0x8fb8a7c7, 0x3d709717, 0x8fb5a391, 0x3d6b13ee, 0x8fb29fa0,
-    0x3d6590a0, 0x8faf9bf5,
-  0x3d600d2c, 0x8fac988f, 0x3d5a8992, 0x8fa9956e, 0x3d5505d2, 0x8fa69293,
-    0x3d4f81ec, 0x8fa38ffc,
-  0x3d49fde1, 0x8fa08dab, 0x3d4479b0, 0x8f9d8ba0, 0x3d3ef559, 0x8f9a89da,
-    0x3d3970dc, 0x8f978859,
-  0x3d33ec39, 0x8f94871d, 0x3d2e6771, 0x8f918627, 0x3d28e282, 0x8f8e8576,
-    0x3d235d6f, 0x8f8b850a,
-  0x3d1dd835, 0x8f8884e4, 0x3d1852d6, 0x8f858503, 0x3d12cd51, 0x8f828568,
-    0x3d0d47a6, 0x8f7f8612,
-  0x3d07c1d6, 0x8f7c8701, 0x3d023be0, 0x8f798836, 0x3cfcb5c4, 0x8f7689b0,
-    0x3cf72f83, 0x8f738b70,
-  0x3cf1a91c, 0x8f708d75, 0x3cec2290, 0x8f6d8fbf, 0x3ce69bde, 0x8f6a924f,
-    0x3ce11507, 0x8f679525,
-  0x3cdb8e09, 0x8f649840, 0x3cd606e7, 0x8f619ba0, 0x3cd07f9f, 0x8f5e9f46,
-    0x3ccaf831, 0x8f5ba331,
-  0x3cc5709e, 0x8f58a761, 0x3cbfe8e5, 0x8f55abd8, 0x3cba6107, 0x8f52b093,
-    0x3cb4d904, 0x8f4fb595,
-  0x3caf50da, 0x8f4cbadb, 0x3ca9c88c, 0x8f49c067, 0x3ca44018, 0x8f46c639,
-    0x3c9eb77f, 0x8f43cc50,
-  0x3c992ec0, 0x8f40d2ad, 0x3c93a5dc, 0x8f3dd950, 0x3c8e1cd3, 0x8f3ae038,
-    0x3c8893a4, 0x8f37e765,
-  0x3c830a50, 0x8f34eed8, 0x3c7d80d6, 0x8f31f691, 0x3c77f737, 0x8f2efe8f,
-    0x3c726d73, 0x8f2c06d3,
-  0x3c6ce38a, 0x8f290f5c, 0x3c67597b, 0x8f26182b, 0x3c61cf48, 0x8f232140,
-    0x3c5c44ee, 0x8f202a9a,
-  0x3c56ba70, 0x8f1d343a, 0x3c512fcc, 0x8f1a3e1f, 0x3c4ba504, 0x8f17484b,
-    0x3c461a16, 0x8f1452bb,
-  0x3c408f03, 0x8f115d72, 0x3c3b03ca, 0x8f0e686e, 0x3c35786d, 0x8f0b73b0,
-    0x3c2fecea, 0x8f087f37,
-  0x3c2a6142, 0x8f058b04, 0x3c24d575, 0x8f029717, 0x3c1f4983, 0x8effa370,
-    0x3c19bd6c, 0x8efcb00e,
-  0x3c143130, 0x8ef9bcf2, 0x3c0ea4cf, 0x8ef6ca1c, 0x3c091849, 0x8ef3d78b,
-    0x3c038b9e, 0x8ef0e540,
-  0x3bfdfecd, 0x8eedf33b, 0x3bf871d8, 0x8eeb017c, 0x3bf2e4be, 0x8ee81002,
-    0x3bed577e, 0x8ee51ece,
-  0x3be7ca1a, 0x8ee22de0, 0x3be23c91, 0x8edf3d38, 0x3bdcaee3, 0x8edc4cd5,
-    0x3bd72110, 0x8ed95cb8,
-  0x3bd19318, 0x8ed66ce1, 0x3bcc04fb, 0x8ed37d50, 0x3bc676b9, 0x8ed08e05,
-    0x3bc0e853, 0x8ecd9eff,
-  0x3bbb59c7, 0x8ecab040, 0x3bb5cb17, 0x8ec7c1c6, 0x3bb03c42, 0x8ec4d392,
-    0x3baaad48, 0x8ec1e5a4,
-  0x3ba51e29, 0x8ebef7fb, 0x3b9f8ee5, 0x8ebc0a99, 0x3b99ff7d, 0x8eb91d7c,
-    0x3b946ff0, 0x8eb630a6,
-  0x3b8ee03e, 0x8eb34415, 0x3b895068, 0x8eb057ca, 0x3b83c06c, 0x8ead6bc5,
-    0x3b7e304c, 0x8eaa8006,
-  0x3b78a007, 0x8ea7948c, 0x3b730f9e, 0x8ea4a959, 0x3b6d7f10, 0x8ea1be6c,
-    0x3b67ee5d, 0x8e9ed3c4,
-  0x3b625d86, 0x8e9be963, 0x3b5ccc8a, 0x8e98ff47, 0x3b573b69, 0x8e961571,
-    0x3b51aa24, 0x8e932be2,
-  0x3b4c18ba, 0x8e904298, 0x3b46872c, 0x8e8d5994, 0x3b40f579, 0x8e8a70d7,
-    0x3b3b63a1, 0x8e87885f,
-  0x3b35d1a5, 0x8e84a02d, 0x3b303f84, 0x8e81b841, 0x3b2aad3f, 0x8e7ed09b,
-    0x3b251ad6, 0x8e7be93c,
-  0x3b1f8848, 0x8e790222, 0x3b19f595, 0x8e761b4e, 0x3b1462be, 0x8e7334c1,
-    0x3b0ecfc3, 0x8e704e79,
-  0x3b093ca3, 0x8e6d6877, 0x3b03a95e, 0x8e6a82bc, 0x3afe15f6, 0x8e679d47,
-    0x3af88269, 0x8e64b817,
-  0x3af2eeb7, 0x8e61d32e, 0x3aed5ae1, 0x8e5eee8b, 0x3ae7c6e7, 0x8e5c0a2e,
-    0x3ae232c9, 0x8e592617,
-  0x3adc9e86, 0x8e564246, 0x3ad70a1f, 0x8e535ebb, 0x3ad17593, 0x8e507b76,
-    0x3acbe0e3, 0x8e4d9878,
-  0x3ac64c0f, 0x8e4ab5bf, 0x3ac0b717, 0x8e47d34d, 0x3abb21fb, 0x8e44f121,
-    0x3ab58cba, 0x8e420f3b,
-  0x3aaff755, 0x8e3f2d9b, 0x3aaa61cc, 0x8e3c4c41, 0x3aa4cc1e, 0x8e396b2e,
-    0x3a9f364d, 0x8e368a61,
-  0x3a99a057, 0x8e33a9da, 0x3a940a3e, 0x8e30c999, 0x3a8e7400, 0x8e2de99e,
-    0x3a88dd9d, 0x8e2b09e9,
-  0x3a834717, 0x8e282a7b, 0x3a7db06d, 0x8e254b53, 0x3a78199f, 0x8e226c71,
-    0x3a7282ac, 0x8e1f8dd6,
-  0x3a6ceb96, 0x8e1caf80, 0x3a67545b, 0x8e19d171, 0x3a61bcfd, 0x8e16f3a9,
-    0x3a5c257a, 0x8e141626,
-  0x3a568dd4, 0x8e1138ea, 0x3a50f609, 0x8e0e5bf4, 0x3a4b5e1b, 0x8e0b7f44,
-    0x3a45c608, 0x8e08a2db,
-  0x3a402dd2, 0x8e05c6b7, 0x3a3a9577, 0x8e02eadb, 0x3a34fcf9, 0x8e000f44,
-    0x3a2f6457, 0x8dfd33f4,
-  0x3a29cb91, 0x8dfa58ea, 0x3a2432a7, 0x8df77e27, 0x3a1e9999, 0x8df4a3a9,
-    0x3a190068, 0x8df1c973,
-  0x3a136712, 0x8deeef82, 0x3a0dcd99, 0x8dec15d8, 0x3a0833fc, 0x8de93c74,
-    0x3a029a3b, 0x8de66357,
-  0x39fd0056, 0x8de38a80, 0x39f7664e, 0x8de0b1ef, 0x39f1cc21, 0x8dddd9a5,
-    0x39ec31d1, 0x8ddb01a1,
-  0x39e6975e, 0x8dd829e4, 0x39e0fcc6, 0x8dd5526d, 0x39db620b, 0x8dd27b3c,
-    0x39d5c72c, 0x8dcfa452,
-  0x39d02c2a, 0x8dcccdaf, 0x39ca9104, 0x8dc9f751, 0x39c4f5ba, 0x8dc7213b,
-    0x39bf5a4d, 0x8dc44b6a,
-  0x39b9bebc, 0x8dc175e0, 0x39b42307, 0x8dbea09d, 0x39ae872f, 0x8dbbcba0,
-    0x39a8eb33, 0x8db8f6ea,
-  0x39a34f13, 0x8db6227a, 0x399db2d0, 0x8db34e50, 0x3998166a, 0x8db07a6d,
-    0x399279e0, 0x8dada6d1,
-  0x398cdd32, 0x8daad37b, 0x39874061, 0x8da8006c, 0x3981a36d, 0x8da52da3,
-    0x397c0655, 0x8da25b21,
-  0x39766919, 0x8d9f88e5, 0x3970cbba, 0x8d9cb6f0, 0x396b2e38, 0x8d99e541,
-    0x39659092, 0x8d9713d9,
-  0x395ff2c9, 0x8d9442b8, 0x395a54dd, 0x8d9171dd, 0x3954b6cd, 0x8d8ea148,
-    0x394f1899, 0x8d8bd0fb,
-  0x39497a43, 0x8d8900f3, 0x3943dbc9, 0x8d863133, 0x393e3d2c, 0x8d8361b9,
-    0x39389e6b, 0x8d809286,
-  0x3932ff87, 0x8d7dc399, 0x392d6080, 0x8d7af4f3, 0x3927c155, 0x8d782694,
-    0x39222208, 0x8d75587b,
-  0x391c8297, 0x8d728aa9, 0x3916e303, 0x8d6fbd1d, 0x3911434b, 0x8d6cefd9,
-    0x390ba371, 0x8d6a22db,
-  0x39060373, 0x8d675623, 0x39006352, 0x8d6489b3, 0x38fac30e, 0x8d61bd89,
-    0x38f522a6, 0x8d5ef1a5,
-  0x38ef821c, 0x8d5c2609, 0x38e9e16e, 0x8d595ab3, 0x38e4409e, 0x8d568fa4,
-    0x38de9faa, 0x8d53c4db,
-  0x38d8fe93, 0x8d50fa59, 0x38d35d59, 0x8d4e301f, 0x38cdbbfc, 0x8d4b662a,
-    0x38c81a7c, 0x8d489c7d,
-  0x38c278d9, 0x8d45d316, 0x38bcd713, 0x8d4309f6, 0x38b7352a, 0x8d40411d,
-    0x38b1931e, 0x8d3d788b,
-  0x38abf0ef, 0x8d3ab03f, 0x38a64e9d, 0x8d37e83a, 0x38a0ac29, 0x8d35207d,
-    0x389b0991, 0x8d325905,
-  0x389566d6, 0x8d2f91d5, 0x388fc3f8, 0x8d2ccaec, 0x388a20f8, 0x8d2a0449,
-    0x38847dd5, 0x8d273ded,
-  0x387eda8e, 0x8d2477d8, 0x38793725, 0x8d21b20a, 0x38739399, 0x8d1eec83,
-    0x386defeb, 0x8d1c2742,
-  0x38684c19, 0x8d196249, 0x3862a825, 0x8d169d96, 0x385d040d, 0x8d13d92a,
-    0x38575fd4, 0x8d111505,
-  0x3851bb77, 0x8d0e5127, 0x384c16f7, 0x8d0b8d90, 0x38467255, 0x8d08ca40,
-    0x3840cd90, 0x8d060737,
-  0x383b28a9, 0x8d034474, 0x3835839f, 0x8d0081f9, 0x382fde72, 0x8cfdbfc4,
-    0x382a3922, 0x8cfafdd7,
-  0x382493b0, 0x8cf83c30, 0x381eee1b, 0x8cf57ad0, 0x38194864, 0x8cf2b9b8,
-    0x3813a28a, 0x8ceff8e6,
-  0x380dfc8d, 0x8ced385b, 0x3808566e, 0x8cea7818, 0x3802b02c, 0x8ce7b81b,
-    0x37fd09c8, 0x8ce4f865,
-  0x37f76341, 0x8ce238f6, 0x37f1bc97, 0x8cdf79ce, 0x37ec15cb, 0x8cdcbaee,
-    0x37e66edd, 0x8cd9fc54,
-  0x37e0c7cc, 0x8cd73e01, 0x37db2099, 0x8cd47ff6, 0x37d57943, 0x8cd1c231,
-    0x37cfd1cb, 0x8ccf04b3,
-  0x37ca2a30, 0x8ccc477d, 0x37c48273, 0x8cc98a8e, 0x37beda93, 0x8cc6cde5,
-    0x37b93292, 0x8cc41184,
-  0x37b38a6d, 0x8cc1556a, 0x37ade227, 0x8cbe9996, 0x37a839be, 0x8cbbde0a,
-    0x37a29132, 0x8cb922c6,
-  0x379ce885, 0x8cb667c8, 0x37973fb5, 0x8cb3ad11, 0x379196c3, 0x8cb0f2a1,
-    0x378bedae, 0x8cae3879,
-  0x37864477, 0x8cab7e98, 0x37809b1e, 0x8ca8c4fd, 0x377af1a3, 0x8ca60baa,
-    0x37754806, 0x8ca3529f,
-  0x376f9e46, 0x8ca099da, 0x3769f464, 0x8c9de15c, 0x37644a60, 0x8c9b2926,
-    0x375ea03a, 0x8c987137,
-  0x3758f5f2, 0x8c95b98f, 0x37534b87, 0x8c93022e, 0x374da0fa, 0x8c904b14,
-    0x3747f64c, 0x8c8d9442,
-  0x37424b7b, 0x8c8addb7, 0x373ca088, 0x8c882773, 0x3736f573, 0x8c857176,
-    0x37314a3c, 0x8c82bbc0,
-  0x372b9ee3, 0x8c800652, 0x3725f367, 0x8c7d512b, 0x372047ca, 0x8c7a9c4b,
-    0x371a9c0b, 0x8c77e7b3,
-  0x3714f02a, 0x8c753362, 0x370f4427, 0x8c727f58, 0x37099802, 0x8c6fcb95,
-    0x3703ebbb, 0x8c6d181a,
-  0x36fe3f52, 0x8c6a64e5, 0x36f892c7, 0x8c67b1f9, 0x36f2e61a, 0x8c64ff53,
-    0x36ed394b, 0x8c624cf5,
-  0x36e78c5b, 0x8c5f9ade, 0x36e1df48, 0x8c5ce90e, 0x36dc3214, 0x8c5a3786,
-    0x36d684be, 0x8c578645,
-  0x36d0d746, 0x8c54d54c, 0x36cb29ac, 0x8c522499, 0x36c57bf0, 0x8c4f742f,
-    0x36bfce13, 0x8c4cc40b,
-  0x36ba2014, 0x8c4a142f, 0x36b471f3, 0x8c47649a, 0x36aec3b0, 0x8c44b54d,
-    0x36a9154c, 0x8c420647,
-  0x36a366c6, 0x8c3f5788, 0x369db81e, 0x8c3ca911, 0x36980954, 0x8c39fae1,
-    0x36925a69, 0x8c374cf9,
-  0x368cab5c, 0x8c349f58, 0x3686fc2e, 0x8c31f1ff, 0x36814cde, 0x8c2f44ed,
-    0x367b9d6c, 0x8c2c9822,
-  0x3675edd9, 0x8c29eb9f, 0x36703e24, 0x8c273f63, 0x366a8e4d, 0x8c24936f,
-    0x3664de55, 0x8c21e7c2,
-  0x365f2e3b, 0x8c1f3c5d, 0x36597e00, 0x8c1c913f, 0x3653cda3, 0x8c19e669,
-    0x364e1d25, 0x8c173bda,
-  0x36486c86, 0x8c149192, 0x3642bbc4, 0x8c11e792, 0x363d0ae2, 0x8c0f3dda,
-    0x363759de, 0x8c0c9469,
-  0x3631a8b8, 0x8c09eb40, 0x362bf771, 0x8c07425e, 0x36264609, 0x8c0499c4,
-    0x3620947f, 0x8c01f171,
-  0x361ae2d3, 0x8bff4966, 0x36153107, 0x8bfca1a3, 0x360f7f19, 0x8bf9fa27,
-    0x3609cd0a, 0x8bf752f2,
-  0x36041ad9, 0x8bf4ac05, 0x35fe6887, 0x8bf20560, 0x35f8b614, 0x8bef5f02,
-    0x35f3037f, 0x8becb8ec,
-  0x35ed50c9, 0x8bea131e, 0x35e79df2, 0x8be76d97, 0x35e1eafa, 0x8be4c857,
-    0x35dc37e0, 0x8be22360,
-  0x35d684a6, 0x8bdf7eb0, 0x35d0d14a, 0x8bdcda47, 0x35cb1dcc, 0x8bda3626,
-    0x35c56a2e, 0x8bd7924d,
-  0x35bfb66e, 0x8bd4eebc, 0x35ba028e, 0x8bd24b72, 0x35b44e8c, 0x8bcfa870,
-    0x35ae9a69, 0x8bcd05b5,
-  0x35a8e625, 0x8bca6343, 0x35a331c0, 0x8bc7c117, 0x359d7d39, 0x8bc51f34,
-    0x3597c892, 0x8bc27d98,
-  0x359213c9, 0x8bbfdc44, 0x358c5ee0, 0x8bbd3b38, 0x3586a9d5, 0x8bba9a73,
-    0x3580f4aa, 0x8bb7f9f6,
-  0x357b3f5d, 0x8bb559c1, 0x357589f0, 0x8bb2b9d4, 0x356fd461, 0x8bb01a2e,
-    0x356a1eb2, 0x8bad7ad0,
-  0x356468e2, 0x8baadbba, 0x355eb2f0, 0x8ba83cec, 0x3558fcde, 0x8ba59e65,
-    0x355346ab, 0x8ba30026,
-  0x354d9057, 0x8ba0622f, 0x3547d9e2, 0x8b9dc480, 0x3542234c, 0x8b9b2718,
-    0x353c6c95, 0x8b9889f8,
-  0x3536b5be, 0x8b95ed21, 0x3530fec6, 0x8b935090, 0x352b47ad, 0x8b90b448,
-    0x35259073, 0x8b8e1848,
-  0x351fd918, 0x8b8b7c8f, 0x351a219c, 0x8b88e11e, 0x35146a00, 0x8b8645f5,
-    0x350eb243, 0x8b83ab14,
-  0x3508fa66, 0x8b81107b, 0x35034267, 0x8b7e7629, 0x34fd8a48, 0x8b7bdc20,
-    0x34f7d208, 0x8b79425e,
-  0x34f219a8, 0x8b76a8e4, 0x34ec6127, 0x8b740fb3, 0x34e6a885, 0x8b7176c8,
-    0x34e0efc2, 0x8b6ede26,
-  0x34db36df, 0x8b6c45cc, 0x34d57ddc, 0x8b69adba, 0x34cfc4b7, 0x8b6715ef,
-    0x34ca0b73, 0x8b647e6d,
-  0x34c4520d, 0x8b61e733, 0x34be9887, 0x8b5f5040, 0x34b8dee1, 0x8b5cb995,
-    0x34b3251a, 0x8b5a2333,
-  0x34ad6b32, 0x8b578d18, 0x34a7b12a, 0x8b54f745, 0x34a1f702, 0x8b5261ba,
-    0x349c3cb9, 0x8b4fcc77,
-  0x34968250, 0x8b4d377c, 0x3490c7c6, 0x8b4aa2ca, 0x348b0d1c, 0x8b480e5f,
-    0x34855251, 0x8b457a3c,
-  0x347f9766, 0x8b42e661, 0x3479dc5b, 0x8b4052ce, 0x3474212f, 0x8b3dbf83,
-    0x346e65e3, 0x8b3b2c80,
-  0x3468aa76, 0x8b3899c6, 0x3462eee9, 0x8b360753, 0x345d333c, 0x8b337528,
-    0x3457776f, 0x8b30e345,
-  0x3451bb81, 0x8b2e51ab, 0x344bff73, 0x8b2bc058, 0x34464345, 0x8b292f4e,
-    0x344086f6, 0x8b269e8b,
-  0x343aca87, 0x8b240e11, 0x34350df8, 0x8b217ddf, 0x342f5149, 0x8b1eedf4,
-    0x3429947a, 0x8b1c5e52,
-  0x3423d78a, 0x8b19cef8, 0x341e1a7b, 0x8b173fe6, 0x34185d4b, 0x8b14b11d,
-    0x34129ffb, 0x8b12229b,
-  0x340ce28b, 0x8b0f9462, 0x340724fb, 0x8b0d0670, 0x3401674a, 0x8b0a78c7,
-    0x33fba97a, 0x8b07eb66,
-  0x33f5eb89, 0x8b055e4d, 0x33f02d79, 0x8b02d17c, 0x33ea6f48, 0x8b0044f3,
-    0x33e4b0f8, 0x8afdb8b3,
-  0x33def287, 0x8afb2cbb, 0x33d933f7, 0x8af8a10b, 0x33d37546, 0x8af615a3,
-    0x33cdb676, 0x8af38a83,
-  0x33c7f785, 0x8af0ffac, 0x33c23875, 0x8aee751c, 0x33bc7944, 0x8aebead5,
-    0x33b6b9f4, 0x8ae960d6,
-  0x33b0fa84, 0x8ae6d720, 0x33ab3af4, 0x8ae44db1, 0x33a57b44, 0x8ae1c48b,
-    0x339fbb74, 0x8adf3bad,
-  0x3399fb85, 0x8adcb318, 0x33943b75, 0x8ada2aca, 0x338e7b46, 0x8ad7a2c5,
-    0x3388baf7, 0x8ad51b08,
-  0x3382fa88, 0x8ad29394, 0x337d39f9, 0x8ad00c67, 0x3377794b, 0x8acd8583,
-    0x3371b87d, 0x8acafee8,
-  0x336bf78f, 0x8ac87894, 0x33663682, 0x8ac5f289, 0x33607554, 0x8ac36cc6,
-    0x335ab407, 0x8ac0e74c,
-  0x3354f29b, 0x8abe6219, 0x334f310e, 0x8abbdd30, 0x33496f62, 0x8ab9588e,
-    0x3343ad97, 0x8ab6d435,
-  0x333debab, 0x8ab45024, 0x333829a1, 0x8ab1cc5c, 0x33326776, 0x8aaf48db,
-    0x332ca52c, 0x8aacc5a4,
-  0x3326e2c3, 0x8aaa42b4, 0x33212039, 0x8aa7c00d, 0x331b5d91, 0x8aa53daf,
-    0x33159ac8, 0x8aa2bb99,
-  0x330fd7e1, 0x8aa039cb, 0x330a14da, 0x8a9db845, 0x330451b3, 0x8a9b3708,
-    0x32fe8e6d, 0x8a98b614,
-  0x32f8cb07, 0x8a963567, 0x32f30782, 0x8a93b504, 0x32ed43de, 0x8a9134e8,
-    0x32e7801a, 0x8a8eb516,
-  0x32e1bc36, 0x8a8c358b, 0x32dbf834, 0x8a89b649, 0x32d63412, 0x8a873750,
-    0x32d06fd0, 0x8a84b89e,
-  0x32caab6f, 0x8a823a36, 0x32c4e6ef, 0x8a7fbc16, 0x32bf2250, 0x8a7d3e3e,
-    0x32b95d91, 0x8a7ac0af,
-  0x32b398b3, 0x8a784368, 0x32add3b6, 0x8a75c66a, 0x32a80e99, 0x8a7349b4,
-    0x32a2495d, 0x8a70cd47,
-  0x329c8402, 0x8a6e5123, 0x3296be88, 0x8a6bd547, 0x3290f8ef, 0x8a6959b3,
-    0x328b3336, 0x8a66de68,
-  0x32856d5e, 0x8a646365, 0x327fa767, 0x8a61e8ab, 0x3279e151, 0x8a5f6e3a,
-    0x32741b1c, 0x8a5cf411,
-  0x326e54c7, 0x8a5a7a31, 0x32688e54, 0x8a580099, 0x3262c7c1, 0x8a55874a,
-    0x325d0110, 0x8a530e43,
-  0x32573a3f, 0x8a509585, 0x3251734f, 0x8a4e1d10, 0x324bac40, 0x8a4ba4e3,
-    0x3245e512, 0x8a492cff,
-  0x32401dc6, 0x8a46b564, 0x323a565a, 0x8a443e11, 0x32348ecf, 0x8a41c706,
-    0x322ec725, 0x8a3f5045,
-  0x3228ff5c, 0x8a3cd9cc, 0x32233775, 0x8a3a639b, 0x321d6f6e, 0x8a37edb3,
-    0x3217a748, 0x8a357814,
-  0x3211df04, 0x8a3302be, 0x320c16a1, 0x8a308db0, 0x32064e1e, 0x8a2e18eb,
-    0x3200857d, 0x8a2ba46e,
-  0x31fabcbd, 0x8a29303b, 0x31f4f3df, 0x8a26bc50, 0x31ef2ae1, 0x8a2448ad,
-    0x31e961c5, 0x8a21d554,
-  0x31e39889, 0x8a1f6243, 0x31ddcf30, 0x8a1cef7a, 0x31d805b7, 0x8a1a7cfb,
-    0x31d23c1f, 0x8a180ac4,
-  0x31cc7269, 0x8a1598d6, 0x31c6a894, 0x8a132731, 0x31c0dea1, 0x8a10b5d4,
-    0x31bb148f, 0x8a0e44c0,
-  0x31b54a5e, 0x8a0bd3f5, 0x31af800e, 0x8a096373, 0x31a9b5a0, 0x8a06f339,
-    0x31a3eb13, 0x8a048348,
-  0x319e2067, 0x8a0213a0, 0x3198559d, 0x89ffa441, 0x31928ab4, 0x89fd352b,
-    0x318cbfad, 0x89fac65d,
-  0x3186f487, 0x89f857d8, 0x31812943, 0x89f5e99c, 0x317b5de0, 0x89f37ba9,
-    0x3175925e, 0x89f10dff,
-  0x316fc6be, 0x89eea09d, 0x3169fb00, 0x89ec3384, 0x31642f23, 0x89e9c6b4,
-    0x315e6328, 0x89e75a2d,
-  0x3158970e, 0x89e4edef, 0x3152cad5, 0x89e281fa, 0x314cfe7f, 0x89e0164d,
-    0x31473209, 0x89ddaae9,
-  0x31416576, 0x89db3fcf, 0x313b98c4, 0x89d8d4fd, 0x3135cbf4, 0x89d66a74,
-    0x312fff05, 0x89d40033,
-  0x312a31f8, 0x89d1963c, 0x312464cd, 0x89cf2c8e, 0x311e9783, 0x89ccc328,
-    0x3118ca1b, 0x89ca5a0c,
-  0x3112fc95, 0x89c7f138, 0x310d2ef0, 0x89c588ae, 0x3107612e, 0x89c3206c,
-    0x3101934d, 0x89c0b873,
-  0x30fbc54d, 0x89be50c3, 0x30f5f730, 0x89bbe95c, 0x30f028f4, 0x89b9823e,
-    0x30ea5a9a, 0x89b71b69,
-  0x30e48c22, 0x89b4b4dd, 0x30debd8c, 0x89b24e9a, 0x30d8eed8, 0x89afe8a0,
-    0x30d32006, 0x89ad82ef,
-  0x30cd5115, 0x89ab1d87, 0x30c78206, 0x89a8b868, 0x30c1b2da, 0x89a65391,
-    0x30bbe38f, 0x89a3ef04,
-  0x30b61426, 0x89a18ac0, 0x30b0449f, 0x899f26c5, 0x30aa74fa, 0x899cc313,
-    0x30a4a537, 0x899a5faa,
-  0x309ed556, 0x8997fc8a, 0x30990557, 0x899599b3, 0x3093353a, 0x89933725,
-    0x308d64ff, 0x8990d4e0,
-  0x308794a6, 0x898e72e4, 0x3081c42f, 0x898c1131, 0x307bf39b, 0x8989afc8,
-    0x307622e8, 0x89874ea7,
-  0x30705217, 0x8984edcf, 0x306a8129, 0x89828d41, 0x3064b01d, 0x89802cfc,
-    0x305edef3, 0x897dccff,
-  0x30590dab, 0x897b6d4c, 0x30533c45, 0x89790de2, 0x304d6ac1, 0x8976aec1,
-    0x30479920, 0x89744fe9,
-  0x3041c761, 0x8971f15a, 0x303bf584, 0x896f9315, 0x30362389, 0x896d3518,
-    0x30305171, 0x896ad765,
-  0x302a7f3a, 0x896879fb, 0x3024ace6, 0x89661cda, 0x301eda75, 0x8963c002,
-    0x301907e6, 0x89616373,
-  0x30133539, 0x895f072e, 0x300d626e, 0x895cab31, 0x30078f86, 0x895a4f7e,
-    0x3001bc80, 0x8957f414,
-  0x2ffbe95d, 0x895598f3, 0x2ff6161c, 0x89533e1c, 0x2ff042bd, 0x8950e38e,
-    0x2fea6f41, 0x894e8948,
-  0x2fe49ba7, 0x894c2f4c, 0x2fdec7f0, 0x8949d59a, 0x2fd8f41b, 0x89477c30,
-    0x2fd32028, 0x89452310,
-  0x2fcd4c19, 0x8942ca39, 0x2fc777eb, 0x894071ab, 0x2fc1a3a0, 0x893e1967,
-    0x2fbbcf38, 0x893bc16b,
-  0x2fb5fab2, 0x893969b9, 0x2fb0260f, 0x89371250, 0x2faa514f, 0x8934bb31,
-    0x2fa47c71, 0x8932645b,
-  0x2f9ea775, 0x89300dce, 0x2f98d25d, 0x892db78a, 0x2f92fd26, 0x892b6190,
-    0x2f8d27d3, 0x89290bdf,
-  0x2f875262, 0x8926b677, 0x2f817cd4, 0x89246159, 0x2f7ba729, 0x89220c84,
-    0x2f75d160, 0x891fb7f8,
-  0x2f6ffb7a, 0x891d63b5, 0x2f6a2577, 0x891b0fbc, 0x2f644f56, 0x8918bc0c,
-    0x2f5e7919, 0x891668a6,
-  0x2f58a2be, 0x89141589, 0x2f52cc46, 0x8911c2b5, 0x2f4cf5b0, 0x890f702b,
-    0x2f471efe, 0x890d1dea,
-  0x2f41482e, 0x890acbf2, 0x2f3b7141, 0x89087a44, 0x2f359a37, 0x890628df,
-    0x2f2fc310, 0x8903d7c4,
-  0x2f29ebcc, 0x890186f2, 0x2f24146b, 0x88ff3669, 0x2f1e3ced, 0x88fce62a,
-    0x2f186551, 0x88fa9634,
-  0x2f128d99, 0x88f84687, 0x2f0cb5c3, 0x88f5f724, 0x2f06ddd1, 0x88f3a80b,
-    0x2f0105c1, 0x88f1593b,
-  0x2efb2d95, 0x88ef0ab4, 0x2ef5554b, 0x88ecbc77, 0x2eef7ce5, 0x88ea6e83,
-    0x2ee9a461, 0x88e820d9,
-  0x2ee3cbc1, 0x88e5d378, 0x2eddf304, 0x88e38660, 0x2ed81a29, 0x88e13992,
-    0x2ed24132, 0x88deed0e,
-  0x2ecc681e, 0x88dca0d3, 0x2ec68eed, 0x88da54e1, 0x2ec0b5a0, 0x88d8093a,
-    0x2ebadc35, 0x88d5bddb,
-  0x2eb502ae, 0x88d372c6, 0x2eaf290a, 0x88d127fb, 0x2ea94f49, 0x88cedd79,
-    0x2ea3756b, 0x88cc9340,
-  0x2e9d9b70, 0x88ca4951, 0x2e97c159, 0x88c7ffac, 0x2e91e725, 0x88c5b650,
-    0x2e8c0cd4, 0x88c36d3e,
-  0x2e863267, 0x88c12475, 0x2e8057dd, 0x88bedbf6, 0x2e7a7d36, 0x88bc93c0,
-    0x2e74a272, 0x88ba4bd4,
-  0x2e6ec792, 0x88b80432, 0x2e68ec95, 0x88b5bcd9, 0x2e63117c, 0x88b375ca,
-    0x2e5d3646, 0x88b12f04,
-  0x2e575af3, 0x88aee888, 0x2e517f84, 0x88aca255, 0x2e4ba3f8, 0x88aa5c6c,
-    0x2e45c850, 0x88a816cd,
-  0x2e3fec8b, 0x88a5d177, 0x2e3a10aa, 0x88a38c6b, 0x2e3434ac, 0x88a147a9,
-    0x2e2e5891, 0x889f0330,
-  0x2e287c5a, 0x889cbf01, 0x2e22a007, 0x889a7b1b, 0x2e1cc397, 0x88983780,
-    0x2e16e70b, 0x8895f42d,
-  0x2e110a62, 0x8893b125, 0x2e0b2d9d, 0x88916e66, 0x2e0550bb, 0x888f2bf1,
-    0x2dff73bd, 0x888ce9c5,
-  0x2df996a3, 0x888aa7e3, 0x2df3b96c, 0x8888664b, 0x2deddc19, 0x888624fd,
-    0x2de7feaa, 0x8883e3f8,
-  0x2de2211e, 0x8881a33d, 0x2ddc4376, 0x887f62cb, 0x2dd665b2, 0x887d22a4,
-    0x2dd087d1, 0x887ae2c6,
-  0x2dcaa9d5, 0x8878a332, 0x2dc4cbbc, 0x887663e7, 0x2dbeed86, 0x887424e7,
-    0x2db90f35, 0x8871e630,
-  0x2db330c7, 0x886fa7c2, 0x2dad523d, 0x886d699f, 0x2da77397, 0x886b2bc5,
-    0x2da194d5, 0x8868ee35,
-  0x2d9bb5f6, 0x8866b0ef, 0x2d95d6fc, 0x886473f2, 0x2d8ff7e5, 0x88623740,
-    0x2d8a18b3, 0x885ffad7,
-  0x2d843964, 0x885dbeb8, 0x2d7e59f9, 0x885b82e3, 0x2d787a72, 0x88594757,
-    0x2d729acf, 0x88570c16,
-  0x2d6cbb10, 0x8854d11e, 0x2d66db35, 0x88529670, 0x2d60fb3e, 0x88505c0b,
-    0x2d5b1b2b, 0x884e21f1,
-  0x2d553afc, 0x884be821, 0x2d4f5ab1, 0x8849ae9a, 0x2d497a4a, 0x8847755d,
-    0x2d4399c7, 0x88453c6a,
-  0x2d3db928, 0x884303c1, 0x2d37d86d, 0x8840cb61, 0x2d31f797, 0x883e934c,
-    0x2d2c16a4, 0x883c5b81,
-  0x2d263596, 0x883a23ff, 0x2d20546b, 0x8837ecc7, 0x2d1a7325, 0x8835b5d9,
-    0x2d1491c4, 0x88337f35,
-  0x2d0eb046, 0x883148db, 0x2d08ceac, 0x882f12cb, 0x2d02ecf7, 0x882cdd04,
-    0x2cfd0b26, 0x882aa788,
-  0x2cf72939, 0x88287256, 0x2cf14731, 0x88263d6d, 0x2ceb650d, 0x882408ce,
-    0x2ce582cd, 0x8821d47a,
-  0x2cdfa071, 0x881fa06f, 0x2cd9bdfa, 0x881d6cae, 0x2cd3db67, 0x881b3937,
-    0x2ccdf8b8, 0x8819060a,
-  0x2cc815ee, 0x8816d327, 0x2cc23308, 0x8814a08f, 0x2cbc5006, 0x88126e40,
-    0x2cb66ce9, 0x88103c3b,
-  0x2cb089b1, 0x880e0a7f, 0x2caaa65c, 0x880bd90e, 0x2ca4c2ed, 0x8809a7e7,
-    0x2c9edf61, 0x8807770a,
-  0x2c98fbba, 0x88054677, 0x2c9317f8, 0x8803162e, 0x2c8d341a, 0x8800e62f,
-    0x2c875021, 0x87feb67a,
-  0x2c816c0c, 0x87fc870f, 0x2c7b87dc, 0x87fa57ee, 0x2c75a390, 0x87f82917,
-    0x2c6fbf29, 0x87f5fa8b,
-  0x2c69daa6, 0x87f3cc48, 0x2c63f609, 0x87f19e4f, 0x2c5e114f, 0x87ef70a0,
-    0x2c582c7b, 0x87ed433c,
-  0x2c52478a, 0x87eb1621, 0x2c4c627f, 0x87e8e950, 0x2c467d58, 0x87e6bcca,
-    0x2c409816, 0x87e4908e,
-  0x2c3ab2b9, 0x87e2649b, 0x2c34cd40, 0x87e038f3, 0x2c2ee7ad, 0x87de0d95,
-    0x2c2901fd, 0x87dbe281,
-  0x2c231c33, 0x87d9b7b7, 0x2c1d364e, 0x87d78d38, 0x2c17504d, 0x87d56302,
-    0x2c116a31, 0x87d33916,
-  0x2c0b83fa, 0x87d10f75, 0x2c059da7, 0x87cee61e, 0x2bffb73a, 0x87ccbd11,
-    0x2bf9d0b1, 0x87ca944e,
-  0x2bf3ea0d, 0x87c86bd5, 0x2bee034e, 0x87c643a6, 0x2be81c74, 0x87c41bc2,
-    0x2be2357f, 0x87c1f427,
-  0x2bdc4e6f, 0x87bfccd7, 0x2bd66744, 0x87bda5d1, 0x2bd07ffe, 0x87bb7f16,
-    0x2bca989d, 0x87b958a4,
-  0x2bc4b120, 0x87b7327d, 0x2bbec989, 0x87b50c9f, 0x2bb8e1d7, 0x87b2e70c,
-    0x2bb2fa0a, 0x87b0c1c4,
-  0x2bad1221, 0x87ae9cc5, 0x2ba72a1e, 0x87ac7811, 0x2ba14200, 0x87aa53a6,
-    0x2b9b59c7, 0x87a82f87,
-  0x2b957173, 0x87a60bb1, 0x2b8f8905, 0x87a3e825, 0x2b89a07b, 0x87a1c4e4,
-    0x2b83b7d7, 0x879fa1ed,
-  0x2b7dcf17, 0x879d7f41, 0x2b77e63d, 0x879b5cde, 0x2b71fd48, 0x87993ac6,
-    0x2b6c1438, 0x879718f8,
-  0x2b662b0e, 0x8794f774, 0x2b6041c9, 0x8792d63b, 0x2b5a5868, 0x8790b54c,
-    0x2b546eee, 0x878e94a7,
-  0x2b4e8558, 0x878c744d, 0x2b489ba8, 0x878a543d, 0x2b42b1dd, 0x87883477,
-    0x2b3cc7f7, 0x878614fb,
-  0x2b36ddf7, 0x8783f5ca, 0x2b30f3dc, 0x8781d6e3, 0x2b2b09a6, 0x877fb846,
-    0x2b251f56, 0x877d99f4,
-  0x2b1f34eb, 0x877b7bec, 0x2b194a66, 0x87795e2f, 0x2b135fc6, 0x877740bb,
-    0x2b0d750b, 0x87752392,
-  0x2b078a36, 0x877306b4, 0x2b019f46, 0x8770ea20, 0x2afbb43c, 0x876ecdd6,
-    0x2af5c917, 0x876cb1d6,
-  0x2aefddd8, 0x876a9621, 0x2ae9f27e, 0x87687ab7, 0x2ae4070a, 0x87665f96,
-    0x2ade1b7c, 0x876444c1,
-  0x2ad82fd2, 0x87622a35, 0x2ad2440f, 0x87600ff4, 0x2acc5831, 0x875df5fd,
-    0x2ac66c39, 0x875bdc51,
-  0x2ac08026, 0x8759c2ef, 0x2aba93f9, 0x8757a9d8, 0x2ab4a7b1, 0x8755910b,
-    0x2aaebb50, 0x87537888,
-  0x2aa8ced3, 0x87516050, 0x2aa2e23d, 0x874f4862, 0x2a9cf58c, 0x874d30bf,
-    0x2a9708c1, 0x874b1966,
-  0x2a911bdc, 0x87490258, 0x2a8b2edc, 0x8746eb94, 0x2a8541c3, 0x8744d51b,
-    0x2a7f548e, 0x8742beec,
-  0x2a796740, 0x8740a907, 0x2a7379d8, 0x873e936d, 0x2a6d8c55, 0x873c7e1e,
-    0x2a679eb8, 0x873a6919,
-  0x2a61b101, 0x8738545e, 0x2a5bc330, 0x87363fee, 0x2a55d545, 0x87342bc9,
-    0x2a4fe740, 0x873217ee,
-  0x2a49f920, 0x8730045d, 0x2a440ae7, 0x872df117, 0x2a3e1c93, 0x872bde1c,
-    0x2a382e25, 0x8729cb6b,
-  0x2a323f9e, 0x8727b905, 0x2a2c50fc, 0x8725a6e9, 0x2a266240, 0x87239518,
-    0x2a20736a, 0x87218391,
-  0x2a1a847b, 0x871f7255, 0x2a149571, 0x871d6163, 0x2a0ea64d, 0x871b50bc,
-    0x2a08b710, 0x87194060,
-  0x2a02c7b8, 0x8717304e, 0x29fcd847, 0x87152087, 0x29f6e8bb, 0x8713110a,
-    0x29f0f916, 0x871101d8,
-  0x29eb0957, 0x870ef2f1, 0x29e5197e, 0x870ce454, 0x29df298b, 0x870ad602,
-    0x29d9397f, 0x8708c7fa,
-  0x29d34958, 0x8706ba3d, 0x29cd5918, 0x8704acca, 0x29c768be, 0x87029fa3,
-    0x29c1784a, 0x870092c5,
-  0x29bb87bc, 0x86fe8633, 0x29b59715, 0x86fc79eb, 0x29afa654, 0x86fa6dee,
-    0x29a9b579, 0x86f8623b,
-  0x29a3c485, 0x86f656d3, 0x299dd377, 0x86f44bb6, 0x2997e24f, 0x86f240e3,
-    0x2991f10e, 0x86f0365c,
-  0x298bffb2, 0x86ee2c1e, 0x29860e3e, 0x86ec222c, 0x29801caf, 0x86ea1884,
-    0x297a2b07, 0x86e80f27,
-  0x29743946, 0x86e60614, 0x296e476b, 0x86e3fd4c, 0x29685576, 0x86e1f4cf,
-    0x29626368, 0x86dfec9d,
-  0x295c7140, 0x86dde4b5, 0x29567eff, 0x86dbdd18, 0x29508ca4, 0x86d9d5c6,
-    0x294a9a30, 0x86d7cebf,
-  0x2944a7a2, 0x86d5c802, 0x293eb4fb, 0x86d3c190, 0x2938c23a, 0x86d1bb69,
-    0x2932cf60, 0x86cfb58c,
-  0x292cdc6d, 0x86cdaffa, 0x2926e960, 0x86cbaab3, 0x2920f63a, 0x86c9a5b7,
-    0x291b02fa, 0x86c7a106,
-  0x29150fa1, 0x86c59c9f, 0x290f1c2f, 0x86c39883, 0x290928a3, 0x86c194b2,
-    0x290334ff, 0x86bf912c,
-  0x28fd4140, 0x86bd8df0, 0x28f74d69, 0x86bb8b00, 0x28f15978, 0x86b9885a,
-    0x28eb656e, 0x86b785ff,
-  0x28e5714b, 0x86b583ee, 0x28df7d0e, 0x86b38229, 0x28d988b8, 0x86b180ae,
-    0x28d3944a, 0x86af7f7e,
-  0x28cd9fc1, 0x86ad7e99, 0x28c7ab20, 0x86ab7dff, 0x28c1b666, 0x86a97db0,
-    0x28bbc192, 0x86a77dab,
-  0x28b5cca5, 0x86a57df2, 0x28afd7a0, 0x86a37e83, 0x28a9e281, 0x86a17f5f,
-    0x28a3ed49, 0x869f8086,
-  0x289df7f8, 0x869d81f8, 0x2898028e, 0x869b83b4, 0x28920d0a, 0x869985bc,
-    0x288c176e, 0x8697880f,
-  0x288621b9, 0x86958aac, 0x28802beb, 0x86938d94, 0x287a3604, 0x869190c7,
-    0x28744004, 0x868f9445,
-  0x286e49ea, 0x868d980e, 0x286853b8, 0x868b9c22, 0x28625d6d, 0x8689a081,
-    0x285c670a, 0x8687a52b,
-  0x2856708d, 0x8685aa20, 0x285079f7, 0x8683af5f, 0x284a8349, 0x8681b4ea,
-    0x28448c81, 0x867fbabf,
-  0x283e95a1, 0x867dc0e0, 0x28389ea8, 0x867bc74b, 0x2832a796, 0x8679ce01,
-    0x282cb06c, 0x8677d503,
-  0x2826b928, 0x8675dc4f, 0x2820c1cc, 0x8673e3e6, 0x281aca57, 0x8671ebc8,
-    0x2814d2c9, 0x866ff3f6,
-  0x280edb23, 0x866dfc6e, 0x2808e364, 0x866c0531, 0x2802eb8c, 0x866a0e3f,
-    0x27fcf39c, 0x86681798,
-  0x27f6fb92, 0x8666213c, 0x27f10371, 0x86642b2c, 0x27eb0b36, 0x86623566,
-    0x27e512e3, 0x86603feb,
-  0x27df1a77, 0x865e4abb, 0x27d921f3, 0x865c55d7, 0x27d32956, 0x865a613d,
-    0x27cd30a1, 0x86586cee,
-  0x27c737d3, 0x865678eb, 0x27c13eec, 0x86548532, 0x27bb45ed, 0x865291c4,
-    0x27b54cd6, 0x86509ea2,
-  0x27af53a6, 0x864eabcb, 0x27a95a5d, 0x864cb93e, 0x27a360fc, 0x864ac6fd,
-    0x279d6783, 0x8648d507,
-  0x27976df1, 0x8646e35c, 0x27917447, 0x8644f1fc, 0x278b7a84, 0x864300e7,
-    0x278580a9, 0x8641101d,
-  0x277f86b5, 0x863f1f9e, 0x27798caa, 0x863d2f6b, 0x27739285, 0x863b3f82,
-    0x276d9849, 0x86394fe5,
-  0x27679df4, 0x86376092, 0x2761a387, 0x8635718b, 0x275ba901, 0x863382cf,
-    0x2755ae64, 0x8631945e,
-  0x274fb3ae, 0x862fa638, 0x2749b8e0, 0x862db85e, 0x2743bdf9, 0x862bcace,
-    0x273dc2fa, 0x8629dd8a,
-  0x2737c7e3, 0x8627f091, 0x2731ccb4, 0x862603e3, 0x272bd16d, 0x86241780,
-    0x2725d60e, 0x86222b68,
-  0x271fda96, 0x86203f9c, 0x2719df06, 0x861e541a, 0x2713e35f, 0x861c68e4,
-    0x270de79f, 0x861a7df9,
-  0x2707ebc7, 0x86189359, 0x2701efd7, 0x8616a905, 0x26fbf3ce, 0x8614befb,
-    0x26f5f7ae, 0x8612d53d,
-  0x26effb76, 0x8610ebca, 0x26e9ff26, 0x860f02a3, 0x26e402bd, 0x860d19c6,
-    0x26de063d, 0x860b3135,
-  0x26d809a5, 0x860948ef, 0x26d20cf5, 0x860760f4, 0x26cc102d, 0x86057944,
-    0x26c6134d, 0x860391e0,
-  0x26c01655, 0x8601aac7, 0x26ba1945, 0x85ffc3f9, 0x26b41c1d, 0x85fddd76,
-    0x26ae1edd, 0x85fbf73f,
-  0x26a82186, 0x85fa1153, 0x26a22416, 0x85f82bb2, 0x269c268f, 0x85f6465c,
-    0x269628f0, 0x85f46152,
-  0x26902b39, 0x85f27c93, 0x268a2d6b, 0x85f09820, 0x26842f84, 0x85eeb3f7,
-    0x267e3186, 0x85ecd01a,
-  0x26783370, 0x85eaec88, 0x26723543, 0x85e90942, 0x266c36fe, 0x85e72647,
-    0x266638a1, 0x85e54397,
-  0x26603a2c, 0x85e36132, 0x265a3b9f, 0x85e17f19, 0x26543cfb, 0x85df9d4b,
-    0x264e3e40, 0x85ddbbc9,
-  0x26483f6c, 0x85dbda91, 0x26424082, 0x85d9f9a5, 0x263c417f, 0x85d81905,
-    0x26364265, 0x85d638b0,
-  0x26304333, 0x85d458a6, 0x262a43ea, 0x85d278e7, 0x26244489, 0x85d09974,
-    0x261e4511, 0x85ceba4d,
-  0x26184581, 0x85ccdb70, 0x261245da, 0x85cafcdf, 0x260c461b, 0x85c91e9a,
-    0x26064645, 0x85c740a0,
-  0x26004657, 0x85c562f1, 0x25fa4652, 0x85c3858d, 0x25f44635, 0x85c1a875,
-    0x25ee4601, 0x85bfcba9,
-  0x25e845b6, 0x85bdef28, 0x25e24553, 0x85bc12f2, 0x25dc44d9, 0x85ba3707,
-    0x25d64447, 0x85b85b68,
-  0x25d0439f, 0x85b68015, 0x25ca42de, 0x85b4a50d, 0x25c44207, 0x85b2ca50,
-    0x25be4118, 0x85b0efdf,
-  0x25b84012, 0x85af15b9, 0x25b23ef5, 0x85ad3bdf, 0x25ac3dc0, 0x85ab6250,
-    0x25a63c74, 0x85a9890d,
-  0x25a03b11, 0x85a7b015, 0x259a3997, 0x85a5d768, 0x25943806, 0x85a3ff07,
-    0x258e365d, 0x85a226f2,
-  0x2588349d, 0x85a04f28, 0x258232c6, 0x859e77a9, 0x257c30d8, 0x859ca076,
-    0x25762ed3, 0x859ac98f,
-  0x25702cb7, 0x8598f2f3, 0x256a2a83, 0x85971ca2, 0x25642839, 0x8595469d,
-    0x255e25d7, 0x859370e4,
-  0x2558235f, 0x85919b76, 0x255220cf, 0x858fc653, 0x254c1e28, 0x858df17c,
-    0x25461b6b, 0x858c1cf1,
-  0x25401896, 0x858a48b1, 0x253a15aa, 0x858874bd, 0x253412a8, 0x8586a114,
-    0x252e0f8e, 0x8584cdb7,
-  0x25280c5e, 0x8582faa5, 0x25220916, 0x858127df, 0x251c05b8, 0x857f5564,
-    0x25160243, 0x857d8335,
-  0x250ffeb7, 0x857bb152, 0x2509fb14, 0x8579dfba, 0x2503f75a, 0x85780e6e,
-    0x24fdf389, 0x85763d6d,
-  0x24f7efa2, 0x85746cb8, 0x24f1eba4, 0x85729c4e, 0x24ebe78f, 0x8570cc30,
-    0x24e5e363, 0x856efc5e,
-  0x24dfdf20, 0x856d2cd7, 0x24d9dac7, 0x856b5d9c, 0x24d3d657, 0x85698ead,
-    0x24cdd1d0, 0x8567c009,
-  0x24c7cd33, 0x8565f1b0, 0x24c1c87f, 0x856423a4, 0x24bbc3b4, 0x856255e3,
-    0x24b5bed2, 0x8560886d,
-  0x24afb9da, 0x855ebb44, 0x24a9b4cb, 0x855cee66, 0x24a3afa6, 0x855b21d3,
-    0x249daa6a, 0x8559558c,
-  0x2497a517, 0x85578991, 0x24919fae, 0x8555bde2, 0x248b9a2f, 0x8553f27e,
-    0x24859498, 0x85522766,
-  0x247f8eec, 0x85505c99, 0x24798928, 0x854e9219, 0x2473834f, 0x854cc7e3,
-    0x246d7d5e, 0x854afdfa,
-  0x24677758, 0x8549345c, 0x2461713a, 0x85476b0a, 0x245b6b07, 0x8545a204,
-    0x245564bd, 0x8543d949,
-  0x244f5e5c, 0x854210db, 0x244957e5, 0x854048b7, 0x24435158, 0x853e80e0,
-    0x243d4ab4, 0x853cb954,
-  0x243743fa, 0x853af214, 0x24313d2a, 0x85392b20, 0x242b3644, 0x85376477,
-    0x24252f47, 0x85359e1a,
-  0x241f2833, 0x8533d809, 0x2419210a, 0x85321244, 0x241319ca, 0x85304cca,
-    0x240d1274, 0x852e879d,
-  0x24070b08, 0x852cc2bb, 0x24010385, 0x852afe24, 0x23fafbec, 0x852939da,
-    0x23f4f43e, 0x852775db,
-  0x23eeec78, 0x8525b228, 0x23e8e49d, 0x8523eec1, 0x23e2dcac, 0x85222ba5,
-    0x23dcd4a4, 0x852068d6,
-  0x23d6cc87, 0x851ea652, 0x23d0c453, 0x851ce41a, 0x23cabc09, 0x851b222e,
-    0x23c4b3a9, 0x8519608d,
-  0x23beab33, 0x85179f39, 0x23b8a2a7, 0x8515de30, 0x23b29a05, 0x85141d73,
-    0x23ac914d, 0x85125d02,
-  0x23a6887f, 0x85109cdd, 0x23a07f9a, 0x850edd03, 0x239a76a0, 0x850d1d75,
-    0x23946d90, 0x850b5e34,
-  0x238e646a, 0x85099f3e, 0x23885b2e, 0x8507e094, 0x238251dd, 0x85062235,
-    0x237c4875, 0x85046423,
-  0x23763ef7, 0x8502a65c, 0x23703564, 0x8500e8e2, 0x236a2bba, 0x84ff2bb3,
-    0x236421fb, 0x84fd6ed0,
-  0x235e1826, 0x84fbb239, 0x23580e3b, 0x84f9f5ee, 0x2352043b, 0x84f839ee,
-    0x234bfa24, 0x84f67e3b,
-  0x2345eff8, 0x84f4c2d4, 0x233fe5b6, 0x84f307b8, 0x2339db5e, 0x84f14ce8,
-    0x2333d0f1, 0x84ef9265,
-  0x232dc66d, 0x84edd82d, 0x2327bbd5, 0x84ec1e41, 0x2321b126, 0x84ea64a1,
-    0x231ba662, 0x84e8ab4d,
-  0x23159b88, 0x84e6f244, 0x230f9098, 0x84e53988, 0x23098593, 0x84e38118,
-    0x23037a78, 0x84e1c8f3,
-  0x22fd6f48, 0x84e0111b, 0x22f76402, 0x84de598f, 0x22f158a7, 0x84dca24e,
-    0x22eb4d36, 0x84daeb5a,
-  0x22e541af, 0x84d934b1, 0x22df3613, 0x84d77e54, 0x22d92a61, 0x84d5c844,
-    0x22d31e9a, 0x84d4127f,
-  0x22cd12bd, 0x84d25d06, 0x22c706cb, 0x84d0a7da, 0x22c0fac4, 0x84cef2f9,
-    0x22baeea7, 0x84cd3e64,
-  0x22b4e274, 0x84cb8a1b, 0x22aed62c, 0x84c9d61f, 0x22a8c9cf, 0x84c8226e,
-    0x22a2bd5d, 0x84c66f09,
-  0x229cb0d5, 0x84c4bbf0, 0x2296a437, 0x84c30924, 0x22909785, 0x84c156a3,
-    0x228a8abd, 0x84bfa46e,
-  0x22847de0, 0x84bdf286, 0x227e70ed, 0x84bc40e9, 0x227863e5, 0x84ba8f98,
-    0x227256c8, 0x84b8de94,
-  0x226c4996, 0x84b72ddb, 0x22663c4e, 0x84b57d6f, 0x22602ef1, 0x84b3cd4f,
-    0x225a217f, 0x84b21d7a,
-  0x225413f8, 0x84b06df2, 0x224e065c, 0x84aebeb6, 0x2247f8aa, 0x84ad0fc6,
-    0x2241eae3, 0x84ab6122,
-  0x223bdd08, 0x84a9b2ca, 0x2235cf17, 0x84a804be, 0x222fc111, 0x84a656fe,
-    0x2229b2f6, 0x84a4a98a,
-  0x2223a4c5, 0x84a2fc62, 0x221d9680, 0x84a14f87, 0x22178826, 0x849fa2f7,
-    0x221179b7, 0x849df6b4,
-  0x220b6b32, 0x849c4abd, 0x22055c99, 0x849a9f12, 0x21ff4dea, 0x8498f3b3,
-    0x21f93f27, 0x849748a0,
-  0x21f3304f, 0x84959dd9, 0x21ed2162, 0x8493f35e, 0x21e71260, 0x84924930,
-    0x21e10349, 0x84909f4e,
-  0x21daf41d, 0x848ef5b7, 0x21d4e4dc, 0x848d4c6d, 0x21ced586, 0x848ba36f,
-    0x21c8c61c, 0x8489fabe,
-  0x21c2b69c, 0x84885258, 0x21bca708, 0x8486aa3e, 0x21b6975f, 0x84850271,
-    0x21b087a1, 0x84835af0,
-  0x21aa77cf, 0x8481b3bb, 0x21a467e7, 0x84800cd2, 0x219e57eb, 0x847e6636,
-    0x219847da, 0x847cbfe5,
-  0x219237b5, 0x847b19e1, 0x218c277a, 0x84797429, 0x2186172b, 0x8477cebd,
-    0x218006c8, 0x8476299e,
-  0x2179f64f, 0x847484ca, 0x2173e5c2, 0x8472e043, 0x216dd521, 0x84713c08,
-    0x2167c46b, 0x846f9819,
-  0x2161b3a0, 0x846df477, 0x215ba2c0, 0x846c5120, 0x215591cc, 0x846aae16,
-    0x214f80c4, 0x84690b58,
-  0x21496fa7, 0x846768e7, 0x21435e75, 0x8465c6c1, 0x213d4d2f, 0x846424e8,
-    0x21373bd4, 0x8462835b,
-  0x21312a65, 0x8460e21a, 0x212b18e1, 0x845f4126, 0x21250749, 0x845da07e,
-    0x211ef59d, 0x845c0022,
-  0x2118e3dc, 0x845a6012, 0x2112d206, 0x8458c04f, 0x210cc01d, 0x845720d8,
-    0x2106ae1e, 0x845581ad,
-  0x21009c0c, 0x8453e2cf, 0x20fa89e5, 0x8452443d, 0x20f477aa, 0x8450a5f7,
-    0x20ee655a, 0x844f07fd,
-  0x20e852f6, 0x844d6a50, 0x20e2407e, 0x844bccef, 0x20dc2df2, 0x844a2fda,
-    0x20d61b51, 0x84489311,
-  0x20d0089c, 0x8446f695, 0x20c9f5d3, 0x84455a66, 0x20c3e2f5, 0x8443be82,
-    0x20bdd003, 0x844222eb,
-  0x20b7bcfe, 0x844087a0, 0x20b1a9e4, 0x843eeca2, 0x20ab96b5, 0x843d51f0,
-    0x20a58373, 0x843bb78a,
-  0x209f701c, 0x843a1d70, 0x20995cb2, 0x843883a3, 0x20934933, 0x8436ea23,
-    0x208d35a0, 0x843550ee,
-  0x208721f9, 0x8433b806, 0x20810e3e, 0x84321f6b, 0x207afa6f, 0x8430871b,
-    0x2074e68c, 0x842eef18,
-  0x206ed295, 0x842d5762, 0x2068be8a, 0x842bbff8, 0x2062aa6b, 0x842a28da,
-    0x205c9638, 0x84289209,
-  0x205681f1, 0x8426fb84, 0x20506d96, 0x8425654b, 0x204a5927, 0x8423cf5f,
-    0x204444a4, 0x842239bf,
-  0x203e300d, 0x8420a46c, 0x20381b63, 0x841f0f65, 0x203206a4, 0x841d7aaa,
-    0x202bf1d2, 0x841be63c,
-  0x2025dcec, 0x841a521a, 0x201fc7f2, 0x8418be45, 0x2019b2e4, 0x84172abc,
-    0x20139dc2, 0x84159780,
-  0x200d888d, 0x84140490, 0x20077344, 0x841271ec, 0x20015de7, 0x8410df95,
-    0x1ffb4876, 0x840f4d8a,
-  0x1ff532f2, 0x840dbbcc, 0x1fef1d59, 0x840c2a5a, 0x1fe907ae, 0x840a9935,
-    0x1fe2f1ee, 0x8409085c,
-  0x1fdcdc1b, 0x840777d0, 0x1fd6c634, 0x8405e790, 0x1fd0b03a, 0x8404579d,
-    0x1fca9a2b, 0x8402c7f6,
-  0x1fc4840a, 0x8401389b, 0x1fbe6dd4, 0x83ffa98d, 0x1fb8578b, 0x83fe1acc,
-    0x1fb2412f, 0x83fc8c57,
-  0x1fac2abf, 0x83fafe2e, 0x1fa6143b, 0x83f97052, 0x1f9ffda4, 0x83f7e2c3,
-    0x1f99e6fa, 0x83f65580,
-  0x1f93d03c, 0x83f4c889, 0x1f8db96a, 0x83f33bdf, 0x1f87a285, 0x83f1af82,
-    0x1f818b8d, 0x83f02371,
-  0x1f7b7481, 0x83ee97ad, 0x1f755d61, 0x83ed0c35, 0x1f6f462f, 0x83eb810a,
-    0x1f692ee9, 0x83e9f62b,
-  0x1f63178f, 0x83e86b99, 0x1f5d0022, 0x83e6e153, 0x1f56e8a2, 0x83e5575a,
-    0x1f50d10e, 0x83e3cdad,
-  0x1f4ab968, 0x83e2444d, 0x1f44a1ad, 0x83e0bb3a, 0x1f3e89e0, 0x83df3273,
-    0x1f3871ff, 0x83dda9f9,
-  0x1f325a0b, 0x83dc21cb, 0x1f2c4204, 0x83da99ea, 0x1f2629ea, 0x83d91255,
-    0x1f2011bc, 0x83d78b0d,
-  0x1f19f97b, 0x83d60412, 0x1f13e127, 0x83d47d63, 0x1f0dc8c0, 0x83d2f701,
-    0x1f07b045, 0x83d170eb,
-  0x1f0197b8, 0x83cfeb22, 0x1efb7f17, 0x83ce65a6, 0x1ef56664, 0x83cce076,
-    0x1eef4d9d, 0x83cb5b93,
-  0x1ee934c3, 0x83c9d6fc, 0x1ee31bd6, 0x83c852b2, 0x1edd02d6, 0x83c6ceb5,
-    0x1ed6e9c3, 0x83c54b04,
-  0x1ed0d09d, 0x83c3c7a0, 0x1ecab763, 0x83c24488, 0x1ec49e17, 0x83c0c1be,
-    0x1ebe84b8, 0x83bf3f3f,
-  0x1eb86b46, 0x83bdbd0e, 0x1eb251c1, 0x83bc3b29, 0x1eac3829, 0x83bab991,
-    0x1ea61e7e, 0x83b93845,
-  0x1ea004c1, 0x83b7b746, 0x1e99eaf0, 0x83b63694, 0x1e93d10c, 0x83b4b62e,
-    0x1e8db716, 0x83b33616,
-  0x1e879d0d, 0x83b1b649, 0x1e8182f1, 0x83b036ca, 0x1e7b68c2, 0x83aeb797,
-    0x1e754e80, 0x83ad38b1,
-  0x1e6f342c, 0x83abba17, 0x1e6919c4, 0x83aa3bca, 0x1e62ff4a, 0x83a8bdca,
-    0x1e5ce4be, 0x83a74017,
-  0x1e56ca1e, 0x83a5c2b0, 0x1e50af6c, 0x83a44596, 0x1e4a94a7, 0x83a2c8c9,
-    0x1e4479cf, 0x83a14c48,
-  0x1e3e5ee5, 0x839fd014, 0x1e3843e8, 0x839e542d, 0x1e3228d9, 0x839cd893,
-    0x1e2c0db6, 0x839b5d45,
-  0x1e25f282, 0x8399e244, 0x1e1fd73a, 0x83986790, 0x1e19bbe0, 0x8396ed29,
-    0x1e13a074, 0x8395730e,
-  0x1e0d84f5, 0x8393f940, 0x1e076963, 0x83927fbf, 0x1e014dbf, 0x8391068a,
-    0x1dfb3208, 0x838f8da2,
-  0x1df5163f, 0x838e1507, 0x1deefa63, 0x838c9cb9, 0x1de8de75, 0x838b24b8,
-    0x1de2c275, 0x8389ad03,
-  0x1ddca662, 0x8388359b, 0x1dd68a3c, 0x8386be80, 0x1dd06e04, 0x838547b2,
-    0x1dca51ba, 0x8383d130,
-  0x1dc4355e, 0x83825afb, 0x1dbe18ef, 0x8380e513, 0x1db7fc6d, 0x837f6f78,
-    0x1db1dfda, 0x837dfa2a,
-  0x1dabc334, 0x837c8528, 0x1da5a67c, 0x837b1074, 0x1d9f89b1, 0x83799c0c,
-    0x1d996cd4, 0x837827f0,
-  0x1d934fe5, 0x8376b422, 0x1d8d32e4, 0x837540a1, 0x1d8715d0, 0x8373cd6c,
-    0x1d80f8ab, 0x83725a84,
-  0x1d7adb73, 0x8370e7e9, 0x1d74be29, 0x836f759b, 0x1d6ea0cc, 0x836e039a,
-    0x1d68835e, 0x836c91e5,
-  0x1d6265dd, 0x836b207d, 0x1d5c484b, 0x8369af63, 0x1d562aa6, 0x83683e95,
-    0x1d500cef, 0x8366ce14,
-  0x1d49ef26, 0x83655ddf, 0x1d43d14b, 0x8363edf8, 0x1d3db35e, 0x83627e5d,
-    0x1d37955e, 0x83610f10,
-  0x1d31774d, 0x835fa00f, 0x1d2b592a, 0x835e315b, 0x1d253af5, 0x835cc2f4,
-    0x1d1f1cae, 0x835b54da,
-  0x1d18fe54, 0x8359e70d, 0x1d12dfe9, 0x8358798c, 0x1d0cc16c, 0x83570c59,
-    0x1d06a2dd, 0x83559f72,
-  0x1d00843d, 0x835432d8, 0x1cfa658a, 0x8352c68c, 0x1cf446c5, 0x83515a8c,
-    0x1cee27ef, 0x834feed9,
-  0x1ce80906, 0x834e8373, 0x1ce1ea0c, 0x834d185a, 0x1cdbcb00, 0x834bad8e,
-    0x1cd5abe3, 0x834a430e,
-  0x1ccf8cb3, 0x8348d8dc, 0x1cc96d72, 0x83476ef6, 0x1cc34e1f, 0x8346055e,
-    0x1cbd2eba, 0x83449c12,
-  0x1cb70f43, 0x83433314, 0x1cb0efbb, 0x8341ca62, 0x1caad021, 0x834061fd,
-    0x1ca4b075, 0x833ef9e6,
-  0x1c9e90b8, 0x833d921b, 0x1c9870e9, 0x833c2a9d, 0x1c925109, 0x833ac36c,
-    0x1c8c3116, 0x83395c88,
-  0x1c861113, 0x8337f5f1, 0x1c7ff0fd, 0x83368fa7, 0x1c79d0d6, 0x833529aa,
-    0x1c73b09d, 0x8333c3fa,
-  0x1c6d9053, 0x83325e97, 0x1c676ff8, 0x8330f981, 0x1c614f8b, 0x832f94b8,
-    0x1c5b2f0c, 0x832e303c,
-  0x1c550e7c, 0x832ccc0d, 0x1c4eedda, 0x832b682b, 0x1c48cd27, 0x832a0496,
-    0x1c42ac62, 0x8328a14d,
-  0x1c3c8b8c, 0x83273e52, 0x1c366aa5, 0x8325dba4, 0x1c3049ac, 0x83247943,
-    0x1c2a28a2, 0x8323172f,
-  0x1c240786, 0x8321b568, 0x1c1de659, 0x832053ee, 0x1c17c51b, 0x831ef2c1,
-    0x1c11a3cb, 0x831d91e1,
-  0x1c0b826a, 0x831c314e, 0x1c0560f8, 0x831ad109, 0x1bff3f75, 0x83197110,
-    0x1bf91de0, 0x83181164,
-  0x1bf2fc3a, 0x8316b205, 0x1becda83, 0x831552f4, 0x1be6b8ba, 0x8313f42f,
-    0x1be096e0, 0x831295b7,
-  0x1bda74f6, 0x8311378d, 0x1bd452f9, 0x830fd9af, 0x1bce30ec, 0x830e7c1f,
-    0x1bc80ece, 0x830d1edc,
-  0x1bc1ec9e, 0x830bc1e6, 0x1bbbca5e, 0x830a653c, 0x1bb5a80c, 0x830908e0,
-    0x1baf85a9, 0x8307acd1,
-  0x1ba96335, 0x83065110, 0x1ba340b0, 0x8304f59b, 0x1b9d1e1a, 0x83039a73,
-    0x1b96fb73, 0x83023f98,
-  0x1b90d8bb, 0x8300e50b, 0x1b8ab5f2, 0x82ff8acb, 0x1b849317, 0x82fe30d7,
-    0x1b7e702c, 0x82fcd731,
-  0x1b784d30, 0x82fb7dd8, 0x1b722a23, 0x82fa24cc, 0x1b6c0705, 0x82f8cc0d,
-    0x1b65e3d7, 0x82f7739c,
-  0x1b5fc097, 0x82f61b77, 0x1b599d46, 0x82f4c3a0, 0x1b5379e5, 0x82f36c15,
-    0x1b4d5672, 0x82f214d8,
-  0x1b4732ef, 0x82f0bde8, 0x1b410f5b, 0x82ef6745, 0x1b3aebb6, 0x82ee10ef,
-    0x1b34c801, 0x82ecbae7,
-  0x1b2ea43a, 0x82eb652b, 0x1b288063, 0x82ea0fbd, 0x1b225c7b, 0x82e8ba9c,
-    0x1b1c3883, 0x82e765c8,
-  0x1b161479, 0x82e61141, 0x1b0ff05f, 0x82e4bd07, 0x1b09cc34, 0x82e3691b,
-    0x1b03a7f9, 0x82e2157c,
-  0x1afd83ad, 0x82e0c22a, 0x1af75f50, 0x82df6f25, 0x1af13ae3, 0x82de1c6d,
-    0x1aeb1665, 0x82dcca02,
-  0x1ae4f1d6, 0x82db77e5, 0x1adecd37, 0x82da2615, 0x1ad8a887, 0x82d8d492,
-    0x1ad283c7, 0x82d7835c,
-  0x1acc5ef6, 0x82d63274, 0x1ac63a14, 0x82d4e1d8, 0x1ac01522, 0x82d3918a,
-    0x1ab9f020, 0x82d24189,
-  0x1ab3cb0d, 0x82d0f1d5, 0x1aada5e9, 0x82cfa26f, 0x1aa780b6, 0x82ce5356,
-    0x1aa15b71, 0x82cd048a,
-  0x1a9b361d, 0x82cbb60b, 0x1a9510b7, 0x82ca67d9, 0x1a8eeb42, 0x82c919f5,
-    0x1a88c5bc, 0x82c7cc5e,
-  0x1a82a026, 0x82c67f14, 0x1a7c7a7f, 0x82c53217, 0x1a7654c8, 0x82c3e568,
-    0x1a702f01, 0x82c29906,
-  0x1a6a0929, 0x82c14cf1, 0x1a63e341, 0x82c00129, 0x1a5dbd49, 0x82beb5af,
-    0x1a579741, 0x82bd6a82,
-  0x1a517128, 0x82bc1fa2, 0x1a4b4aff, 0x82bad50f, 0x1a4524c6, 0x82b98aca,
-    0x1a3efe7c, 0x82b840d2,
-  0x1a38d823, 0x82b6f727, 0x1a32b1b9, 0x82b5adca, 0x1a2c8b3f, 0x82b464ba,
-    0x1a2664b5, 0x82b31bf7,
-  0x1a203e1b, 0x82b1d381, 0x1a1a1771, 0x82b08b59, 0x1a13f0b6, 0x82af437e,
-    0x1a0dc9ec, 0x82adfbf0,
-  0x1a07a311, 0x82acb4b0, 0x1a017c27, 0x82ab6dbd, 0x19fb552c, 0x82aa2717,
-    0x19f52e22, 0x82a8e0bf,
-  0x19ef0707, 0x82a79ab3, 0x19e8dfdc, 0x82a654f6, 0x19e2b8a2, 0x82a50f85,
-    0x19dc9157, 0x82a3ca62,
-  0x19d669fc, 0x82a2858c, 0x19d04292, 0x82a14104, 0x19ca1b17, 0x829ffcc8,
-    0x19c3f38d, 0x829eb8db,
-  0x19bdcbf3, 0x829d753a, 0x19b7a449, 0x829c31e7, 0x19b17c8f, 0x829aeee1,
-    0x19ab54c5, 0x8299ac29,
-  0x19a52ceb, 0x829869be, 0x199f0502, 0x829727a0, 0x1998dd09, 0x8295e5cf,
-    0x1992b4ff, 0x8294a44c,
-  0x198c8ce7, 0x82936317, 0x198664be, 0x8292222e, 0x19803c86, 0x8290e194,
-    0x197a143e, 0x828fa146,
-  0x1973ebe6, 0x828e6146, 0x196dc37e, 0x828d2193, 0x19679b07, 0x828be22e,
-    0x19617280, 0x828aa316,
-  0x195b49ea, 0x8289644b, 0x19552144, 0x828825ce, 0x194ef88e, 0x8286e79e,
-    0x1948cfc8, 0x8285a9bb,
-  0x1942a6f3, 0x82846c26, 0x193c7e0f, 0x82832edf, 0x1936551b, 0x8281f1e4,
-    0x19302c17, 0x8280b538,
-  0x192a0304, 0x827f78d8, 0x1923d9e1, 0x827e3cc6, 0x191db0af, 0x827d0102,
-    0x1917876d, 0x827bc58a,
-  0x19115e1c, 0x827a8a61, 0x190b34bb, 0x82794f84, 0x19050b4b, 0x827814f6,
-    0x18fee1cb, 0x8276dab4,
-  0x18f8b83c, 0x8275a0c0, 0x18f28e9e, 0x8274671a, 0x18ec64f0, 0x82732dc0,
-    0x18e63b33, 0x8271f4b5,
-  0x18e01167, 0x8270bbf7, 0x18d9e78b, 0x826f8386, 0x18d3bda0, 0x826e4b62,
-    0x18cd93a5, 0x826d138d,
-  0x18c7699b, 0x826bdc04, 0x18c13f82, 0x826aa4c9, 0x18bb155a, 0x82696ddc,
-    0x18b4eb22, 0x8268373c,
-  0x18aec0db, 0x826700e9, 0x18a89685, 0x8265cae4, 0x18a26c20, 0x8264952d,
-    0x189c41ab, 0x82635fc2,
-  0x18961728, 0x82622aa6, 0x188fec95, 0x8260f5d7, 0x1889c1f3, 0x825fc155,
-    0x18839742, 0x825e8d21,
-  0x187d6c82, 0x825d593a, 0x187741b2, 0x825c25a1, 0x187116d4, 0x825af255,
-    0x186aebe6, 0x8259bf57,
-  0x1864c0ea, 0x82588ca7, 0x185e95de, 0x82575a44, 0x18586ac3, 0x8256282e,
-    0x18523f9a, 0x8254f666,
-  0x184c1461, 0x8253c4eb, 0x1845e919, 0x825293be, 0x183fbdc3, 0x825162df,
-    0x1839925d, 0x8250324d,
-  0x183366e9, 0x824f0208, 0x182d3b65, 0x824dd211, 0x18270fd3, 0x824ca268,
-    0x1820e431, 0x824b730c,
-  0x181ab881, 0x824a43fe, 0x18148cc2, 0x8249153d, 0x180e60f4, 0x8247e6ca,
-    0x18083518, 0x8246b8a4,
-  0x1802092c, 0x82458acc, 0x17fbdd32, 0x82445d41, 0x17f5b129, 0x82433004,
-    0x17ef8511, 0x82420315,
-  0x17e958ea, 0x8240d673, 0x17e32cb5, 0x823faa1e, 0x17dd0070, 0x823e7e18,
-    0x17d6d41d, 0x823d525e,
-  0x17d0a7bc, 0x823c26f3, 0x17ca7b4c, 0x823afbd5, 0x17c44ecd, 0x8239d104,
-    0x17be223f, 0x8238a681,
-  0x17b7f5a3, 0x82377c4c, 0x17b1c8f8, 0x82365264, 0x17ab9c3e, 0x823528ca,
-    0x17a56f76, 0x8233ff7e,
-  0x179f429f, 0x8232d67f, 0x179915ba, 0x8231adce, 0x1792e8c6, 0x8230856a,
-    0x178cbbc4, 0x822f5d54,
-  0x17868eb3, 0x822e358b, 0x17806194, 0x822d0e10, 0x177a3466, 0x822be6e3,
-    0x17740729, 0x822ac004,
-  0x176dd9de, 0x82299971, 0x1767ac85, 0x8228732d, 0x17617f1d, 0x82274d36,
-    0x175b51a7, 0x8226278d,
-  0x17552422, 0x82250232, 0x174ef68f, 0x8223dd24, 0x1748c8ee, 0x8222b863,
-    0x17429b3e, 0x822193f1,
-  0x173c6d80, 0x82206fcc, 0x17363fb4, 0x821f4bf5, 0x173011d9, 0x821e286b,
-    0x1729e3f0, 0x821d052f,
-  0x1723b5f9, 0x821be240, 0x171d87f3, 0x821abfa0, 0x171759df, 0x82199d4d,
-    0x17112bbd, 0x82187b47,
-  0x170afd8d, 0x82175990, 0x1704cf4f, 0x82163826, 0x16fea102, 0x82151709,
-    0x16f872a7, 0x8213f63a,
-  0x16f2443e, 0x8212d5b9, 0x16ec15c7, 0x8211b586, 0x16e5e741, 0x821095a0,
-    0x16dfb8ae, 0x820f7608,
-  0x16d98a0c, 0x820e56be, 0x16d35b5c, 0x820d37c1, 0x16cd2c9f, 0x820c1912,
-    0x16c6fdd3, 0x820afab1,
-  0x16c0cef9, 0x8209dc9e, 0x16baa011, 0x8208bed8, 0x16b4711b, 0x8207a160,
-    0x16ae4217, 0x82068435,
-  0x16a81305, 0x82056758, 0x16a1e3e5, 0x82044ac9, 0x169bb4b7, 0x82032e88,
-    0x1695857b, 0x82021294,
-  0x168f5632, 0x8200f6ef, 0x168926da, 0x81ffdb96, 0x1682f774, 0x81fec08c,
-    0x167cc801, 0x81fda5cf,
-  0x1676987f, 0x81fc8b60, 0x167068f0, 0x81fb713f, 0x166a3953, 0x81fa576c,
-    0x166409a8, 0x81f93de6,
-  0x165dd9f0, 0x81f824ae, 0x1657aa29, 0x81f70bc3, 0x16517a55, 0x81f5f327,
-    0x164b4a73, 0x81f4dad8,
-  0x16451a83, 0x81f3c2d7, 0x163eea86, 0x81f2ab24, 0x1638ba7a, 0x81f193be,
-    0x16328a61, 0x81f07ca6,
-  0x162c5a3b, 0x81ef65dc, 0x16262a06, 0x81ee4f60, 0x161ff9c4, 0x81ed3932,
-    0x1619c975, 0x81ec2351,
-  0x16139918, 0x81eb0dbe, 0x160d68ad, 0x81e9f879, 0x16073834, 0x81e8e381,
-    0x160107ae, 0x81e7ced8,
-  0x15fad71b, 0x81e6ba7c, 0x15f4a679, 0x81e5a66e, 0x15ee75cb, 0x81e492ad,
-    0x15e8450e, 0x81e37f3b,
-  0x15e21445, 0x81e26c16, 0x15dbe36d, 0x81e1593f, 0x15d5b288, 0x81e046b6,
-    0x15cf8196, 0x81df347b,
-  0x15c95097, 0x81de228d, 0x15c31f89, 0x81dd10ee, 0x15bcee6f, 0x81dbff9c,
-    0x15b6bd47, 0x81daee98,
-  0x15b08c12, 0x81d9dde1, 0x15aa5acf, 0x81d8cd79, 0x15a4297f, 0x81d7bd5e,
-    0x159df821, 0x81d6ad92,
-  0x1597c6b7, 0x81d59e13, 0x1591953e, 0x81d48ee1, 0x158b63b9, 0x81d37ffe,
-    0x15853226, 0x81d27169,
-  0x157f0086, 0x81d16321, 0x1578ced9, 0x81d05527, 0x15729d1f, 0x81cf477b,
-    0x156c6b57, 0x81ce3a1d,
-  0x15663982, 0x81cd2d0c, 0x156007a0, 0x81cc204a, 0x1559d5b1, 0x81cb13d5,
-    0x1553a3b4, 0x81ca07af,
-  0x154d71aa, 0x81c8fbd6, 0x15473f94, 0x81c7f04b, 0x15410d70, 0x81c6e50d,
-    0x153adb3f, 0x81c5da1e,
-  0x1534a901, 0x81c4cf7d, 0x152e76b5, 0x81c3c529, 0x1528445d, 0x81c2bb23,
-    0x152211f8, 0x81c1b16b,
-  0x151bdf86, 0x81c0a801, 0x1515ad06, 0x81bf9ee5, 0x150f7a7a, 0x81be9617,
-    0x150947e1, 0x81bd8d97,
-  0x1503153a, 0x81bc8564, 0x14fce287, 0x81bb7d7f, 0x14f6afc7, 0x81ba75e9,
-    0x14f07cf9, 0x81b96ea0,
-  0x14ea4a1f, 0x81b867a5, 0x14e41738, 0x81b760f8, 0x14dde445, 0x81b65a99,
-    0x14d7b144, 0x81b55488,
-  0x14d17e36, 0x81b44ec4, 0x14cb4b1c, 0x81b3494f, 0x14c517f4, 0x81b24427,
-    0x14bee4c0, 0x81b13f4e,
-  0x14b8b17f, 0x81b03ac2, 0x14b27e32, 0x81af3684, 0x14ac4ad7, 0x81ae3294,
-    0x14a61770, 0x81ad2ef2,
-  0x149fe3fc, 0x81ac2b9e, 0x1499b07c, 0x81ab2898, 0x14937cee, 0x81aa25e0,
-    0x148d4954, 0x81a92376,
-  0x148715ae, 0x81a82159, 0x1480e1fa, 0x81a71f8b, 0x147aae3a, 0x81a61e0b,
-    0x14747a6d, 0x81a51cd8,
-  0x146e4694, 0x81a41bf4, 0x146812ae, 0x81a31b5d, 0x1461debc, 0x81a21b14,
-    0x145baabd, 0x81a11b1a,
-  0x145576b1, 0x81a01b6d, 0x144f4299, 0x819f1c0e, 0x14490e74, 0x819e1cfd,
-    0x1442da43, 0x819d1e3a,
-  0x143ca605, 0x819c1fc5, 0x143671bb, 0x819b219e, 0x14303d65, 0x819a23c5,
-    0x142a0902, 0x8199263a,
-  0x1423d492, 0x819828fd, 0x141da016, 0x81972c0e, 0x14176b8e, 0x81962f6d,
-    0x141136f9, 0x8195331a,
-  0x140b0258, 0x81943715, 0x1404cdaa, 0x81933b5e, 0x13fe98f1, 0x81923ff4,
-    0x13f8642a, 0x819144d9,
-  0x13f22f58, 0x81904a0c, 0x13ebfa79, 0x818f4f8d, 0x13e5c58e, 0x818e555c,
-    0x13df9097, 0x818d5b78,
-  0x13d95b93, 0x818c61e3, 0x13d32683, 0x818b689c, 0x13ccf167, 0x818a6fa3,
-    0x13c6bc3f, 0x818976f8,
-  0x13c0870a, 0x81887e9a, 0x13ba51ca, 0x8187868b, 0x13b41c7d, 0x81868eca,
-    0x13ade724, 0x81859757,
-  0x13a7b1bf, 0x8184a032, 0x13a17c4d, 0x8183a95b, 0x139b46d0, 0x8182b2d1,
-    0x13951146, 0x8181bc96,
-  0x138edbb1, 0x8180c6a9, 0x1388a60f, 0x817fd10a, 0x13827062, 0x817edbb9,
-    0x137c3aa8, 0x817de6b6,
-  0x137604e2, 0x817cf201, 0x136fcf10, 0x817bfd9b, 0x13699933, 0x817b0982,
-    0x13636349, 0x817a15b7,
-  0x135d2d53, 0x8179223a, 0x1356f752, 0x81782f0b, 0x1350c144, 0x81773c2b,
-    0x134a8b2b, 0x81764998,
-  0x13445505, 0x81755754, 0x133e1ed4, 0x8174655d, 0x1337e897, 0x817373b5,
-    0x1331b24e, 0x8172825a,
-  0x132b7bf9, 0x8171914e, 0x13254599, 0x8170a090, 0x131f0f2c, 0x816fb020,
-    0x1318d8b4, 0x816ebffe,
-  0x1312a230, 0x816dd02a, 0x130c6ba0, 0x816ce0a4, 0x13063505, 0x816bf16c,
-    0x12fffe5d, 0x816b0282,
-  0x12f9c7aa, 0x816a13e6, 0x12f390ec, 0x81692599, 0x12ed5a21, 0x81683799,
-    0x12e7234b, 0x816749e8,
-  0x12e0ec6a, 0x81665c84, 0x12dab57c, 0x81656f6f, 0x12d47e83, 0x816482a8,
-    0x12ce477f, 0x8163962f,
-  0x12c8106f, 0x8162aa04, 0x12c1d953, 0x8161be27, 0x12bba22b, 0x8160d298,
-    0x12b56af9, 0x815fe758,
-  0x12af33ba, 0x815efc65, 0x12a8fc70, 0x815e11c1, 0x12a2c51b, 0x815d276a,
-    0x129c8dba, 0x815c3d62,
-  0x1296564d, 0x815b53a8, 0x12901ed5, 0x815a6a3c, 0x1289e752, 0x8159811e,
-    0x1283afc3, 0x8158984e,
-  0x127d7829, 0x8157afcd, 0x12774083, 0x8156c799, 0x127108d2, 0x8155dfb4,
-    0x126ad116, 0x8154f81d,
-  0x1264994e, 0x815410d4, 0x125e617b, 0x815329d9, 0x1258299c, 0x8152432c,
-    0x1251f1b3, 0x81515ccd,
-  0x124bb9be, 0x815076bd, 0x124581bd, 0x814f90fb, 0x123f49b2, 0x814eab86,
-    0x1239119b, 0x814dc660,
-  0x1232d979, 0x814ce188, 0x122ca14b, 0x814bfcff, 0x12266913, 0x814b18c3,
-    0x122030cf, 0x814a34d6,
-  0x1219f880, 0x81495136, 0x1213c026, 0x81486de5, 0x120d87c1, 0x81478ae2,
-    0x12074f50, 0x8146a82e,
-  0x120116d5, 0x8145c5c7, 0x11fade4e, 0x8144e3ae, 0x11f4a5bd, 0x814401e4,
-    0x11ee6d20, 0x81432068,
-  0x11e83478, 0x81423f3a, 0x11e1fbc5, 0x81415e5a, 0x11dbc307, 0x81407dc9,
-    0x11d58a3e, 0x813f9d86,
-  0x11cf516a, 0x813ebd90, 0x11c9188b, 0x813ddde9, 0x11c2dfa2, 0x813cfe91,
-    0x11bca6ad, 0x813c1f86,
-  0x11b66dad, 0x813b40ca, 0x11b034a2, 0x813a625b, 0x11a9fb8d, 0x8139843b,
-    0x11a3c26c, 0x8138a66a,
-  0x119d8941, 0x8137c8e6, 0x1197500a, 0x8136ebb1, 0x119116c9, 0x81360ec9,
-    0x118add7d, 0x81353230,
-  0x1184a427, 0x813455e6, 0x117e6ac5, 0x813379e9, 0x11783159, 0x81329e3b,
-    0x1171f7e2, 0x8131c2db,
-  0x116bbe60, 0x8130e7c9, 0x116584d3, 0x81300d05, 0x115f4b3c, 0x812f3290,
-    0x1159119a, 0x812e5868,
-  0x1152d7ed, 0x812d7e8f, 0x114c9e35, 0x812ca505, 0x11466473, 0x812bcbc8,
-    0x11402aa6, 0x812af2da,
-  0x1139f0cf, 0x812a1a3a, 0x1133b6ed, 0x812941e8, 0x112d7d00, 0x812869e4,
-    0x11274309, 0x8127922f,
-  0x11210907, 0x8126bac8, 0x111acefb, 0x8125e3af, 0x111494e4, 0x81250ce4,
-    0x110e5ac2, 0x81243668,
-  0x11082096, 0x8123603a, 0x1101e65f, 0x81228a5a, 0x10fbac1e, 0x8121b4c8,
-    0x10f571d3, 0x8120df85,
-  0x10ef377d, 0x81200a90, 0x10e8fd1c, 0x811f35e9, 0x10e2c2b2, 0x811e6191,
-    0x10dc883c, 0x811d8d86,
-  0x10d64dbd, 0x811cb9ca, 0x10d01333, 0x811be65d, 0x10c9d89e, 0x811b133d,
-    0x10c39dff, 0x811a406c,
-  0x10bd6356, 0x81196de9, 0x10b728a3, 0x81189bb4, 0x10b0ede5, 0x8117c9ce,
-    0x10aab31d, 0x8116f836,
-  0x10a4784b, 0x811626ec, 0x109e3d6e, 0x811555f1, 0x10980287, 0x81148544,
-    0x1091c796, 0x8113b4e5,
-  0x108b8c9b, 0x8112e4d4, 0x10855195, 0x81121512, 0x107f1686, 0x8111459e,
-    0x1078db6c, 0x81107678,
-  0x1072a048, 0x810fa7a0, 0x106c651a, 0x810ed917, 0x106629e1, 0x810e0adc,
-    0x105fee9f, 0x810d3cf0,
-  0x1059b352, 0x810c6f52, 0x105377fc, 0x810ba202, 0x104d3c9b, 0x810ad500,
-    0x10470130, 0x810a084d,
-  0x1040c5bb, 0x81093be8, 0x103a8a3d, 0x81086fd1, 0x10344eb4, 0x8107a409,
-    0x102e1321, 0x8106d88f,
-  0x1027d784, 0x81060d63, 0x10219bdd, 0x81054286, 0x101b602d, 0x810477f7,
-    0x10152472, 0x8103adb6,
-  0x100ee8ad, 0x8102e3c4, 0x1008acdf, 0x81021a20, 0x10027107, 0x810150ca,
-    0xffc3524, 0x810087c3,
-  0xff5f938, 0x80ffbf0a, 0xfefbd42, 0x80fef69f, 0xfe98143, 0x80fe2e83,
-    0xfe34539, 0x80fd66b5,
-  0xfdd0926, 0x80fc9f35, 0xfd6cd08, 0x80fbd804, 0xfd090e1, 0x80fb1121,
-    0xfca54b1, 0x80fa4a8c,
-  0xfc41876, 0x80f98446, 0xfbddc32, 0x80f8be4e, 0xfb79fe4, 0x80f7f8a4,
-    0xfb1638d, 0x80f73349,
-  0xfab272b, 0x80f66e3c, 0xfa4eac0, 0x80f5a97e, 0xf9eae4c, 0x80f4e50e,
-    0xf9871ce, 0x80f420ec,
-  0xf923546, 0x80f35d19, 0xf8bf8b4, 0x80f29994, 0xf85bc19, 0x80f1d65d,
-    0xf7f7f75, 0x80f11375,
-  0xf7942c7, 0x80f050db, 0xf73060f, 0x80ef8e90, 0xf6cc94e, 0x80eecc93,
-    0xf668c83, 0x80ee0ae4,
-  0xf604faf, 0x80ed4984, 0xf5a12d1, 0x80ec8872, 0xf53d5ea, 0x80ebc7ae,
-    0xf4d98f9, 0x80eb0739,
-  0xf475bff, 0x80ea4712, 0xf411efb, 0x80e9873a, 0xf3ae1ee, 0x80e8c7b0,
-    0xf34a4d8, 0x80e80874,
-  0xf2e67b8, 0x80e74987, 0xf282a8f, 0x80e68ae8, 0xf21ed5d, 0x80e5cc98,
-    0xf1bb021, 0x80e50e96,
-  0xf1572dc, 0x80e450e2, 0xf0f358e, 0x80e3937d, 0xf08f836, 0x80e2d666,
-    0xf02bad5, 0x80e2199e,
-  0xefc7d6b, 0x80e15d24, 0xef63ff7, 0x80e0a0f8, 0xef0027b, 0x80dfe51b,
-    0xee9c4f5, 0x80df298c,
-  0xee38766, 0x80de6e4c, 0xedd49ce, 0x80ddb35a, 0xed70c2c, 0x80dcf8b7,
-    0xed0ce82, 0x80dc3e62,
-  0xeca90ce, 0x80db845b, 0xec45311, 0x80dacaa3, 0xebe154b, 0x80da1139,
-    0xeb7d77c, 0x80d9581e,
-  0xeb199a4, 0x80d89f51, 0xeab5bc3, 0x80d7e6d3, 0xea51dd8, 0x80d72ea3,
-    0xe9edfe5, 0x80d676c1,
-  0xe98a1e9, 0x80d5bf2e, 0xe9263e3, 0x80d507e9, 0xe8c25d5, 0x80d450f3,
-    0xe85e7be, 0x80d39a4b,
-  0xe7fa99e, 0x80d2e3f2, 0xe796b74, 0x80d22de7, 0xe732d42, 0x80d1782a,
-    0xe6cef07, 0x80d0c2bc,
-  0xe66b0c3, 0x80d00d9d, 0xe607277, 0x80cf58cc, 0xe5a3421, 0x80cea449,
-    0xe53f5c2, 0x80cdf015,
-  0xe4db75b, 0x80cd3c2f, 0xe4778eb, 0x80cc8898, 0xe413a72, 0x80cbd54f,
-    0xe3afbf0, 0x80cb2255,
-  0xe34bd66, 0x80ca6fa9, 0xe2e7ed2, 0x80c9bd4c, 0xe284036, 0x80c90b3d,
-    0xe220191, 0x80c8597c,
-  0xe1bc2e4, 0x80c7a80a, 0xe15842e, 0x80c6f6e7, 0xe0f456f, 0x80c64612,
-    0xe0906a7, 0x80c5958b,
-  0xe02c7d7, 0x80c4e553, 0xdfc88fe, 0x80c4356a, 0xdf64a1c, 0x80c385cf,
-    0xdf00b32, 0x80c2d682,
-  0xde9cc40, 0x80c22784, 0xde38d44, 0x80c178d4, 0xddd4e40, 0x80c0ca73,
-    0xdd70f34, 0x80c01c60,
-  0xdd0d01f, 0x80bf6e9c, 0xdca9102, 0x80bec127, 0xdc451dc, 0x80be13ff,
-    0xdbe12ad, 0x80bd6727,
-  0xdb7d376, 0x80bcba9d, 0xdb19437, 0x80bc0e61, 0xdab54ef, 0x80bb6274,
-    0xda5159f, 0x80bab6d5,
-  0xd9ed646, 0x80ba0b85, 0xd9896e5, 0x80b96083, 0xd92577b, 0x80b8b5d0,
-    0xd8c1809, 0x80b80b6c,
-  0xd85d88f, 0x80b76156, 0xd7f990c, 0x80b6b78e, 0xd795982, 0x80b60e15,
-    0xd7319ee, 0x80b564ea,
-  0xd6cda53, 0x80b4bc0e, 0xd669aaf, 0x80b41381, 0xd605b03, 0x80b36b42,
-    0xd5a1b4f, 0x80b2c351,
-  0xd53db92, 0x80b21baf, 0xd4d9bcd, 0x80b1745c, 0xd475c00, 0x80b0cd57,
-    0xd411c2b, 0x80b026a1,
-  0xd3adc4e, 0x80af8039, 0xd349c68, 0x80aeda20, 0xd2e5c7b, 0x80ae3455,
-    0xd281c85, 0x80ad8ed9,
-  0xd21dc87, 0x80ace9ab, 0xd1b9c81, 0x80ac44cc, 0xd155c73, 0x80aba03b,
-    0xd0f1c5d, 0x80aafbf9,
-  0xd08dc3f, 0x80aa5806, 0xd029c18, 0x80a9b461, 0xcfc5bea, 0x80a9110b,
-    0xcf61bb4, 0x80a86e03,
-  0xcefdb76, 0x80a7cb49, 0xce99b2f, 0x80a728df, 0xce35ae1, 0x80a686c2,
-    0xcdd1a8b, 0x80a5e4f5,
-  0xcd6da2d, 0x80a54376, 0xcd099c7, 0x80a4a245, 0xcca5959, 0x80a40163,
-    0xcc418e3, 0x80a360d0,
-  0xcbdd865, 0x80a2c08b, 0xcb797e0, 0x80a22095, 0xcb15752, 0x80a180ed,
-    0xcab16bd, 0x80a0e194,
-  0xca4d620, 0x80a04289, 0xc9e957b, 0x809fa3cd, 0xc9854cf, 0x809f0560,
-    0xc92141a, 0x809e6741,
-  0xc8bd35e, 0x809dc971, 0xc85929a, 0x809d2bef, 0xc7f51cf, 0x809c8ebc,
-    0xc7910fb, 0x809bf1d7,
-  0xc72d020, 0x809b5541, 0xc6c8f3e, 0x809ab8fa, 0xc664e53, 0x809a1d01,
-    0xc600d61, 0x80998157,
-  0xc59cc68, 0x8098e5fb, 0xc538b66, 0x80984aee, 0xc4d4a5d, 0x8097b030,
-    0xc47094d, 0x809715c0,
-  0xc40c835, 0x80967b9f, 0xc3a8715, 0x8095e1cc, 0xc3445ee, 0x80954848,
-    0xc2e04c0, 0x8094af13,
-  0xc27c389, 0x8094162c, 0xc21824c, 0x80937d93, 0xc1b4107, 0x8092e54a,
-    0xc14ffba, 0x80924d4f,
-  0xc0ebe66, 0x8091b5a2, 0xc087d0a, 0x80911e44, 0xc023ba7, 0x80908735,
-    0xbfbfa3d, 0x808ff074,
-  0xbf5b8cb, 0x808f5a02, 0xbef7752, 0x808ec3df, 0xbe935d2, 0x808e2e0a,
-    0xbe2f44a, 0x808d9884,
-  0xbdcb2bb, 0x808d034c, 0xbd67124, 0x808c6e63, 0xbd02f87, 0x808bd9c9,
-    0xbc9ede2, 0x808b457d,
-  0xbc3ac35, 0x808ab180, 0xbbd6a82, 0x808a1dd2, 0xbb728c7, 0x80898a72,
-    0xbb0e705, 0x8088f761,
-  0xbaaa53b, 0x8088649e, 0xba4636b, 0x8087d22a, 0xb9e2193, 0x80874005,
-    0xb97dfb5, 0x8086ae2e,
-  0xb919dcf, 0x80861ca6, 0xb8b5be1, 0x80858b6c, 0xb8519ed, 0x8084fa82,
-    0xb7ed7f2, 0x808469e5,
-  0xb7895f0, 0x8083d998, 0xb7253e6, 0x80834999, 0xb6c11d5, 0x8082b9e9,
-    0xb65cfbe, 0x80822a87,
-  0xb5f8d9f, 0x80819b74, 0xb594b7a, 0x80810cb0, 0xb53094d, 0x80807e3a,
-    0xb4cc719, 0x807ff013,
-  0xb4684df, 0x807f623b, 0xb40429d, 0x807ed4b1, 0xb3a0055, 0x807e4776,
-    0xb33be05, 0x807dba89,
-  0xb2d7baf, 0x807d2dec, 0xb273952, 0x807ca19c, 0xb20f6ee, 0x807c159c,
-    0xb1ab483, 0x807b89ea,
-  0xb147211, 0x807afe87, 0xb0e2f98, 0x807a7373, 0xb07ed19, 0x8079e8ad,
-    0xb01aa92, 0x80795e36,
-  0xafb6805, 0x8078d40d, 0xaf52571, 0x80784a33, 0xaeee2d7, 0x8077c0a8,
-    0xae8a036, 0x8077376c,
-  0xae25d8d, 0x8076ae7e, 0xadc1adf, 0x807625df, 0xad5d829, 0x80759d8e,
-    0xacf956d, 0x8075158c,
-  0xac952aa, 0x80748dd9, 0xac30fe1, 0x80740675, 0xabccd11, 0x80737f5f,
-    0xab68a3a, 0x8072f898,
-  0xab0475c, 0x8072721f, 0xaaa0478, 0x8071ebf6, 0xaa3c18e, 0x8071661a,
-    0xa9d7e9d, 0x8070e08e,
-  0xa973ba5, 0x80705b50, 0xa90f8a7, 0x806fd661, 0xa8ab5a2, 0x806f51c1,
-    0xa847297, 0x806ecd6f,
-  0xa7e2f85, 0x806e496c, 0xa77ec6d, 0x806dc5b8, 0xa71a94f, 0x806d4253,
-    0xa6b662a, 0x806cbf3c,
-  0xa6522fe, 0x806c3c74, 0xa5edfcc, 0x806bb9fa, 0xa589c94, 0x806b37cf,
-    0xa525955, 0x806ab5f3,
-  0xa4c1610, 0x806a3466, 0xa45d2c5, 0x8069b327, 0xa3f8f73, 0x80693237,
-    0xa394c1b, 0x8068b196,
-  0xa3308bd, 0x80683143, 0xa2cc558, 0x8067b13f, 0xa2681ed, 0x8067318a,
-    0xa203e7c, 0x8066b224,
-  0xa19fb04, 0x8066330c, 0xa13b787, 0x8065b443, 0xa0d7403, 0x806535c9,
-    0xa073079, 0x8064b79d,
-  0xa00ece8, 0x806439c0, 0x9faa952, 0x8063bc32, 0x9f465b5, 0x80633ef3,
-    0x9ee2213, 0x8062c202,
-  0x9e7de6a, 0x80624560, 0x9e19abb, 0x8061c90c, 0x9db5706, 0x80614d08,
-    0x9d5134b, 0x8060d152,
-  0x9cecf89, 0x806055eb, 0x9c88bc2, 0x805fdad2, 0x9c247f5, 0x805f6009,
-    0x9bc0421, 0x805ee58e,
-  0x9b5c048, 0x805e6b62, 0x9af7c69, 0x805df184, 0x9a93884, 0x805d77f5,
-    0x9a2f498, 0x805cfeb5,
-  0x99cb0a7, 0x805c85c4, 0x9966cb0, 0x805c0d21, 0x99028b3, 0x805b94ce,
-    0x989e4b0, 0x805b1cc8,
-  0x983a0a7, 0x805aa512, 0x97d5c99, 0x805a2daa, 0x9771884, 0x8059b692,
-    0x970d46a, 0x80593fc7,
-  0x96a9049, 0x8058c94c, 0x9644c23, 0x8058531f, 0x95e07f8, 0x8057dd41,
-    0x957c3c6, 0x805767b2,
-  0x9517f8f, 0x8056f272, 0x94b3b52, 0x80567d80, 0x944f70f, 0x805608dd,
-    0x93eb2c6, 0x80559489,
-  0x9386e78, 0x80552084, 0x9322a24, 0x8054accd, 0x92be5ca, 0x80543965,
-    0x925a16b, 0x8053c64c,
-  0x91f5d06, 0x80535381, 0x919189c, 0x8052e106, 0x912d42c, 0x80526ed9,
-    0x90c8fb6, 0x8051fcfb,
-  0x9064b3a, 0x80518b6b, 0x90006ba, 0x80511a2b, 0x8f9c233, 0x8050a939,
-    0x8f37da7, 0x80503896,
-  0x8ed3916, 0x804fc841, 0x8e6f47f, 0x804f583c, 0x8e0afe2, 0x804ee885,
-    0x8da6b40, 0x804e791d,
-  0x8d42699, 0x804e0a04, 0x8cde1ec, 0x804d9b39, 0x8c79d3a, 0x804d2cbd,
-    0x8c15882, 0x804cbe90,
-  0x8bb13c5, 0x804c50b2, 0x8b4cf02, 0x804be323, 0x8ae8a3a, 0x804b75e2,
-    0x8a8456d, 0x804b08f0,
-  0x8a2009a, 0x804a9c4d, 0x89bbbc3, 0x804a2ff9, 0x89576e5, 0x8049c3f3,
-    0x88f3203, 0x8049583d,
-  0x888ed1b, 0x8048ecd5, 0x882a82e, 0x804881bb, 0x87c633c, 0x804816f1,
-    0x8761e44, 0x8047ac75,
-  0x86fd947, 0x80474248, 0x8699445, 0x8046d86a, 0x8634f3e, 0x80466edb,
-    0x85d0a32, 0x8046059b,
-  0x856c520, 0x80459ca9, 0x850800a, 0x80453406, 0x84a3aee, 0x8044cbb2,
-    0x843f5cd, 0x804463ad,
-  0x83db0a7, 0x8043fbf6, 0x8376b7c, 0x8043948e, 0x831264c, 0x80432d75,
-    0x82ae117, 0x8042c6ab,
-  0x8249bdd, 0x80426030, 0x81e569d, 0x8041fa03, 0x8181159, 0x80419425,
-    0x811cc10, 0x80412e96,
-  0x80b86c2, 0x8040c956, 0x805416e, 0x80406465, 0x7fefc16, 0x803fffc2,
-    0x7f8b6b9, 0x803f9b6f,
-  0x7f27157, 0x803f376a, 0x7ec2bf0, 0x803ed3b3, 0x7e5e685, 0x803e704c,
-    0x7dfa114, 0x803e0d34,
-  0x7d95b9e, 0x803daa6a, 0x7d31624, 0x803d47ef, 0x7ccd0a5, 0x803ce5c3,
-    0x7c68b21, 0x803c83e5,
-  0x7c04598, 0x803c2257, 0x7ba000b, 0x803bc117, 0x7b3ba78, 0x803b6026,
-    0x7ad74e1, 0x803aff84,
-  0x7a72f45, 0x803a9f31, 0x7a0e9a5, 0x803a3f2d, 0x79aa400, 0x8039df77,
-    0x7945e56, 0x80398010,
-  0x78e18a7, 0x803920f8, 0x787d2f4, 0x8038c22f, 0x7818d3c, 0x803863b5,
-    0x77b4780, 0x80380589,
-  0x77501be, 0x8037a7ac, 0x76ebbf9, 0x80374a1f, 0x768762e, 0x8036ece0,
-    0x762305f, 0x80368fef,
-  0x75bea8c, 0x8036334e, 0x755a4b4, 0x8035d6fb, 0x74f5ed7, 0x80357af8,
-    0x74918f6, 0x80351f43,
-  0x742d311, 0x8034c3dd, 0x73c8d27, 0x803468c5, 0x7364738, 0x80340dfd,
-    0x7300145, 0x8033b383,
-  0x729bb4e, 0x80335959, 0x7237552, 0x8032ff7d, 0x71d2f52, 0x8032a5ef,
-    0x716e94e, 0x80324cb1,
-  0x710a345, 0x8031f3c2, 0x70a5d37, 0x80319b21, 0x7041726, 0x803142cf,
-    0x6fdd110, 0x8030eacd,
-  0x6f78af6, 0x80309318, 0x6f144d7, 0x80303bb3, 0x6eafeb4, 0x802fe49d,
-    0x6e4b88d, 0x802f8dd5,
-  0x6de7262, 0x802f375d, 0x6d82c32, 0x802ee133, 0x6d1e5fe, 0x802e8b58,
-    0x6cb9fc6, 0x802e35cb,
-  0x6c5598a, 0x802de08e, 0x6bf1349, 0x802d8ba0, 0x6b8cd05, 0x802d3700,
-    0x6b286bc, 0x802ce2af,
-  0x6ac406f, 0x802c8ead, 0x6a5fa1e, 0x802c3afa, 0x69fb3c9, 0x802be796,
-    0x6996d70, 0x802b9480,
-  0x6932713, 0x802b41ba, 0x68ce0b2, 0x802aef42, 0x6869a4c, 0x802a9d19,
-    0x68053e3, 0x802a4b3f,
-  0x67a0d76, 0x8029f9b4, 0x673c704, 0x8029a878, 0x66d808f, 0x8029578b,
-    0x6673a16, 0x802906ec,
-  0x660f398, 0x8028b69c, 0x65aad17, 0x8028669b, 0x6546692, 0x802816e9,
-    0x64e2009, 0x8027c786,
-  0x647d97c, 0x80277872, 0x64192eb, 0x802729ad, 0x63b4c57, 0x8026db36,
-    0x63505be, 0x80268d0e,
-  0x62ebf22, 0x80263f36, 0x6287882, 0x8025f1ac, 0x62231de, 0x8025a471,
-    0x61beb36, 0x80255784,
-  0x615a48b, 0x80250ae7, 0x60f5ddc, 0x8024be99, 0x6091729, 0x80247299,
-    0x602d072, 0x802426e8,
-  0x5fc89b8, 0x8023db86, 0x5f642fa, 0x80239073, 0x5effc38, 0x802345af,
-    0x5e9b572, 0x8022fb3a,
-  0x5e36ea9, 0x8022b114, 0x5dd27dd, 0x8022673c, 0x5d6e10c, 0x80221db3,
-    0x5d09a38, 0x8021d47a,
-  0x5ca5361, 0x80218b8f, 0x5c40c86, 0x802142f3, 0x5bdc5a7, 0x8020faa6,
-    0x5b77ec5, 0x8020b2a7,
-  0x5b137df, 0x80206af8, 0x5aaf0f6, 0x80202397, 0x5a4aa09, 0x801fdc86,
-    0x59e6319, 0x801f95c3,
-  0x5981c26, 0x801f4f4f, 0x591d52f, 0x801f092a, 0x58b8e34, 0x801ec354,
-    0x5854736, 0x801e7dcd,
-  0x57f0035, 0x801e3895, 0x578b930, 0x801df3ab, 0x5727228, 0x801daf11,
-    0x56c2b1c, 0x801d6ac5,
-  0x565e40d, 0x801d26c8, 0x55f9cfb, 0x801ce31a, 0x55955e6, 0x801c9fbb,
-    0x5530ecd, 0x801c5cab,
-  0x54cc7b1, 0x801c19ea, 0x5468092, 0x801bd777, 0x540396f, 0x801b9554,
-    0x539f249, 0x801b537f,
-  0x533ab20, 0x801b11fa, 0x52d63f4, 0x801ad0c3, 0x5271cc4, 0x801a8fdb,
-    0x520d592, 0x801a4f42,
-  0x51a8e5c, 0x801a0ef8, 0x5144723, 0x8019cefd, 0x50dffe7, 0x80198f50,
-    0x507b8a8, 0x80194ff3,
-  0x5017165, 0x801910e4, 0x4fb2a20, 0x8018d225, 0x4f4e2d8, 0x801893b4,
-    0x4ee9b8c, 0x80185592,
-  0x4e8543e, 0x801817bf, 0x4e20cec, 0x8017da3b, 0x4dbc597, 0x80179d06,
-    0x4d57e40, 0x80176020,
-  0x4cf36e5, 0x80172388, 0x4c8ef88, 0x8016e740, 0x4c2a827, 0x8016ab46,
-    0x4bc60c4, 0x80166f9c,
-  0x4b6195d, 0x80163440, 0x4afd1f4, 0x8015f933, 0x4a98a88, 0x8015be75,
-    0x4a34319, 0x80158406,
-  0x49cfba7, 0x801549e6, 0x496b432, 0x80151015, 0x4906cbb, 0x8014d693,
-    0x48a2540, 0x80149d5f,
-  0x483ddc3, 0x8014647b, 0x47d9643, 0x80142be5, 0x4774ec1, 0x8013f39e,
-    0x471073b, 0x8013bba7,
-  0x46abfb3, 0x801383fe, 0x4647828, 0x80134ca4, 0x45e309a, 0x80131599,
-    0x457e90a, 0x8012dedd,
-  0x451a177, 0x8012a86f, 0x44b59e1, 0x80127251, 0x4451249, 0x80123c82,
-    0x43ecaae, 0x80120701,
-  0x4388310, 0x8011d1d0, 0x4323b70, 0x80119ced, 0x42bf3cd, 0x80116859,
-    0x425ac28, 0x80113414,
-  0x41f6480, 0x8011001f, 0x4191cd5, 0x8010cc78, 0x412d528, 0x8010991f,
-    0x40c8d79, 0x80106616,
-  0x40645c7, 0x8010335c, 0x3fffe12, 0x801000f1, 0x3f9b65b, 0x800fced4,
-    0x3f36ea2, 0x800f9d07,
-  0x3ed26e6, 0x800f6b88, 0x3e6df28, 0x800f3a59, 0x3e09767, 0x800f0978,
-    0x3da4fa4, 0x800ed8e6,
-  0x3d407df, 0x800ea8a3, 0x3cdc017, 0x800e78af, 0x3c7784d, 0x800e490a,
-    0x3c13080, 0x800e19b4,
-  0x3bae8b2, 0x800deaad, 0x3b4a0e0, 0x800dbbf5, 0x3ae590d, 0x800d8d8b,
-    0x3a81137, 0x800d5f71,
-  0x3a1c960, 0x800d31a5, 0x39b8185, 0x800d0429, 0x39539a9, 0x800cd6fb,
-    0x38ef1ca, 0x800caa1c,
-  0x388a9ea, 0x800c7d8c, 0x3826207, 0x800c514c, 0x37c1a22, 0x800c255a,
-    0x375d23a, 0x800bf9b7,
-  0x36f8a51, 0x800bce63, 0x3694265, 0x800ba35d, 0x362fa78, 0x800b78a7,
-    0x35cb288, 0x800b4e40,
-  0x3566a96, 0x800b2427, 0x35022a2, 0x800afa5e, 0x349daac, 0x800ad0e3,
-    0x34392b4, 0x800aa7b8,
-  0x33d4abb, 0x800a7edb, 0x33702bf, 0x800a564e, 0x330bac1, 0x800a2e0f,
-    0x32a72c1, 0x800a061f,
-  0x3242abf, 0x8009de7e, 0x31de2bb, 0x8009b72c, 0x3179ab5, 0x80099029,
-    0x31152ae, 0x80096975,
-  0x30b0aa4, 0x80094310, 0x304c299, 0x80091cf9, 0x2fe7a8c, 0x8008f732,
-    0x2f8327d, 0x8008d1ba,
-  0x2f1ea6c, 0x8008ac90, 0x2eba259, 0x800887b6, 0x2e55a44, 0x8008632a,
-    0x2df122e, 0x80083eed,
-  0x2d8ca16, 0x80081b00, 0x2d281fc, 0x8007f761, 0x2cc39e1, 0x8007d411,
-    0x2c5f1c3, 0x8007b110,
-  0x2bfa9a4, 0x80078e5e, 0x2b96184, 0x80076bfb, 0x2b31961, 0x800749e7,
-    0x2acd13d, 0x80072822,
-  0x2a68917, 0x800706ac, 0x2a040f0, 0x8006e585, 0x299f8c7, 0x8006c4ac,
-    0x293b09c, 0x8006a423,
-  0x28d6870, 0x800683e8, 0x2872043, 0x800663fd, 0x280d813, 0x80064460,
-    0x27a8fe2, 0x80062513,
-  0x27447b0, 0x80060614, 0x26dff7c, 0x8005e764, 0x267b747, 0x8005c904,
-    0x2616f10, 0x8005aaf2,
-  0x25b26d7, 0x80058d2f, 0x254de9e, 0x80056fbb, 0x24e9662, 0x80055296,
-    0x2484e26, 0x800535c0,
-  0x24205e8, 0x80051939, 0x23bbda8, 0x8004fd00, 0x2357567, 0x8004e117,
-    0x22f2d25, 0x8004c57d,
-  0x228e4e2, 0x8004aa32, 0x2229c9d, 0x80048f35, 0x21c5457, 0x80047488,
-    0x2160c0f, 0x80045a29,
-  0x20fc3c6, 0x8004401a, 0x2097b7c, 0x80042659, 0x2033331, 0x80040ce7,
-    0x1fceae4, 0x8003f3c5,
-  0x1f6a297, 0x8003daf1, 0x1f05a48, 0x8003c26c, 0x1ea11f7, 0x8003aa36,
-    0x1e3c9a6, 0x8003924f,
-  0x1dd8154, 0x80037ab7, 0x1d73900, 0x8003636e, 0x1d0f0ab, 0x80034c74,
-    0x1caa855, 0x800335c9,
-  0x1c45ffe, 0x80031f6d, 0x1be17a6, 0x80030960, 0x1b7cf4d, 0x8002f3a1,
-    0x1b186f3, 0x8002de32,
-  0x1ab3e97, 0x8002c912, 0x1a4f63b, 0x8002b440, 0x19eaddd, 0x80029fbe,
-    0x198657f, 0x80028b8a,
-  0x1921d20, 0x800277a6, 0x18bd4bf, 0x80026410, 0x1858c5e, 0x800250c9,
-    0x17f43fc, 0x80023dd2,
-  0x178fb99, 0x80022b29, 0x172b335, 0x800218cf, 0x16c6ad0, 0x800206c4,
-    0x166226a, 0x8001f508,
-  0x15fda03, 0x8001e39b, 0x159919c, 0x8001d27d, 0x1534934, 0x8001c1ae,
-    0x14d00ca, 0x8001b12e,
-  0x146b860, 0x8001a0fd, 0x1406ff6, 0x8001911b, 0x13a278a, 0x80018187,
-    0x133df1e, 0x80017243,
-  0x12d96b1, 0x8001634e, 0x1274e43, 0x800154a7, 0x12105d5, 0x80014650,
-    0x11abd66, 0x80013847,
-  0x11474f6, 0x80012a8e, 0x10e2c85, 0x80011d23, 0x107e414, 0x80011008,
-    0x1019ba2, 0x8001033b,
-  0xfb5330, 0x8000f6bd, 0xf50abd, 0x8000ea8e, 0xeec249, 0x8000deaf, 0xe879d5,
-    0x8000d31e,
-  0xe23160, 0x8000c7dc, 0xdbe8eb, 0x8000bce9, 0xd5a075, 0x8000b245, 0xcf57ff,
-    0x8000a7f0,
-  0xc90f88, 0x80009dea, 0xc2c711, 0x80009433, 0xbc7e99, 0x80008aca, 0xb63621,
-    0x800081b1,
-  0xafeda8, 0x800078e7, 0xa9a52f, 0x8000706c, 0xa35cb5, 0x8000683f, 0x9d143b,
-    0x80006062,
-  0x96cbc1, 0x800058d4, 0x908346, 0x80005194, 0x8a3acb, 0x80004aa4, 0x83f250,
-    0x80004402,
-  0x7da9d4, 0x80003daf, 0x776159, 0x800037ac, 0x7118dc, 0x800031f7, 0x6ad060,
-    0x80002c91,
-  0x6487e3, 0x8000277a, 0x5e3f66, 0x800022b3, 0x57f6e9, 0x80001e3a, 0x51ae6b,
-    0x80001a10,
-  0x4b65ee, 0x80001635, 0x451d70, 0x800012a9, 0x3ed4f2, 0x80000f6c, 0x388c74,
-    0x80000c7e,
-  0x3243f5, 0x800009df, 0x2bfb77, 0x8000078e, 0x25b2f8, 0x8000058d, 0x1f6a7a,
-    0x800003db,
-  0x1921fb, 0x80000278, 0x12d97c, 0x80000163, 0xc90fe, 0x8000009e, 0x6487f,
-    0x80000027,
-
-};
-
-/**    
-* \par    
-* cosFactor tables are generated using the formula : 
cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
    
-* \par    
-* C command to generate the table    
-* 
    
-* for(i = 0; i< N; i++)    
-* {    
-*   cos_factors[i]= 2 * cos((2*i+1)*c/2);    
-* } 
    
-* \par    
-* where N is the number of factors to generate and c is pi/(2*N)    
-* \par    
-* Then converted to q31 format by multiplying with 2^31 and saturated if required.    
-*/
-
-
-static const q31_t cos_factorsQ31_128[128] = {
-  0x7fff6216, 0x7ffa72d1, 0x7ff09478, 0x7fe1c76b, 0x7fce0c3e, 0x7fb563b3,
-  0x7f97cebd, 0x7f754e80,
-  0x7f4de451, 0x7f2191b4, 0x7ef05860, 0x7eba3a39, 0x7e7f3957, 0x7e3f57ff,
-  0x7dfa98a8, 0x7db0fdf8,
-  0x7d628ac6, 0x7d0f4218, 0x7cb72724, 0x7c5a3d50, 0x7bf88830, 0x7b920b89,
-  0x7b26cb4f, 0x7ab6cba4,
-  0x7a4210d8, 0x79c89f6e, 0x794a7c12, 0x78c7aba2, 0x78403329, 0x77b417df,
-  0x77235f2d, 0x768e0ea6,
-  0x75f42c0b, 0x7555bd4c, 0x74b2c884, 0x740b53fb, 0x735f6626, 0x72af05a7,
-  0x71fa3949, 0x71410805,
-  0x708378ff, 0x6fc19385, 0x6efb5f12, 0x6e30e34a, 0x6d6227fa, 0x6c8f351c,
-  0x6bb812d1, 0x6adcc964,
-  0x69fd614a, 0x6919e320, 0x683257ab, 0x6746c7d8, 0x66573cbb, 0x6563bf92,
-  0x646c59bf, 0x637114cc,
-  0x6271fa69, 0x616f146c, 0x60686ccf, 0x5f5e0db3, 0x5e50015d, 0x5d3e5237,
-  0x5c290acc, 0x5b1035cf,
-  0x59f3de12, 0x58d40e8c, 0x57b0d256, 0x568a34a9, 0x556040e2, 0x5433027d,
-  0x53028518, 0x51ced46e,
-  0x5097fc5e, 0x4f5e08e3, 0x4e210617, 0x4ce10034, 0x4b9e0390, 0x4a581c9e,
-  0x490f57ee, 0x47c3c22f,
-  0x46756828, 0x452456bd, 0x43d09aed, 0x427a41d0, 0x4121589b, 0x3fc5ec98,
-  0x3e680b2c, 0x3d07c1d6,
-  0x3ba51e29, 0x3a402dd2, 0x38d8fe93, 0x376f9e46, 0x36041ad9, 0x34968250,
-  0x3326e2c3, 0x31b54a5e,
-  0x3041c761, 0x2ecc681e, 0x2d553afc, 0x2bdc4e6f, 0x2a61b101, 0x28e5714b,
-  0x27679df4, 0x25e845b6,
-  0x24677758, 0x22e541af, 0x2161b3a0, 0x1fdcdc1b, 0x1e56ca1e, 0x1ccf8cb3,
-  0x1b4732ef, 0x19bdcbf3,
-  0x183366e9, 0x16a81305, 0x151bdf86, 0x138edbb1, 0x120116d5, 0x1072a048,
-  0xee38766, 0xd53db92,
-  0xbc3ac35, 0xa3308bd, 0x8a2009a, 0x710a345, 0x57f0035, 0x3ed26e6, 0x25b26d7,
-  0xc90f88,
-};
-
-static const q31_t cos_factorsQ31_512[512] = {
-  0x7ffff621, 0x7fffa72c, 0x7fff0943, 0x7ffe1c65, 0x7ffce093, 0x7ffb55ce,
-  0x7ff97c18, 0x7ff75370,
-  0x7ff4dbd9, 0x7ff21553, 0x7feeffe1, 0x7feb9b85, 0x7fe7e841, 0x7fe3e616,
-  0x7fdf9508, 0x7fdaf519,
-  0x7fd6064c, 0x7fd0c8a3, 0x7fcb3c23, 0x7fc560cf, 0x7fbf36aa, 0x7fb8bdb8,
-  0x7fb1f5fc, 0x7faadf7c,
-  0x7fa37a3c, 0x7f9bc640, 0x7f93c38c, 0x7f8b7227, 0x7f82d214, 0x7f79e35a,
-  0x7f70a5fe, 0x7f671a05,
-  0x7f5d3f75, 0x7f531655, 0x7f489eaa, 0x7f3dd87c, 0x7f32c3d1, 0x7f2760af,
-  0x7f1baf1e, 0x7f0faf25,
-  0x7f0360cb, 0x7ef6c418, 0x7ee9d914, 0x7edc9fc6, 0x7ecf1837, 0x7ec14270,
-  0x7eb31e78, 0x7ea4ac58,
-  0x7e95ec1a, 0x7e86ddc6, 0x7e778166, 0x7e67d703, 0x7e57dea7, 0x7e47985b,
-  0x7e37042a, 0x7e26221f,
-  0x7e14f242, 0x7e0374a0, 0x7df1a942, 0x7ddf9034, 0x7dcd2981, 0x7dba7534,
-  0x7da77359, 0x7d9423fc,
-  0x7d808728, 0x7d6c9ce9, 0x7d58654d, 0x7d43e05e, 0x7d2f0e2b, 0x7d19eebf,
-  0x7d048228, 0x7ceec873,
-  0x7cd8c1ae, 0x7cc26de5, 0x7cabcd28, 0x7c94df83, 0x7c7da505, 0x7c661dbc,
-  0x7c4e49b7, 0x7c362904,
-  0x7c1dbbb3, 0x7c0501d2, 0x7bebfb70, 0x7bd2a89e, 0x7bb9096b, 0x7b9f1de6,
-  0x7b84e61f, 0x7b6a6227,
-  0x7b4f920e, 0x7b3475e5, 0x7b190dbc, 0x7afd59a4, 0x7ae159ae, 0x7ac50dec,
-  0x7aa8766f, 0x7a8b9348,
-  0x7a6e648a, 0x7a50ea47, 0x7a332490, 0x7a151378, 0x79f6b711, 0x79d80f6f,
-  0x79b91ca4, 0x7999dec4,
-  0x797a55e0, 0x795a820e, 0x793a6361, 0x7919f9ec, 0x78f945c3, 0x78d846fb,
-  0x78b6fda8, 0x789569df,
-  0x78738bb3, 0x7851633b, 0x782ef08b, 0x780c33b8, 0x77e92cd9, 0x77c5dc01,
-  0x77a24148, 0x777e5cc3,
-  0x775a2e89, 0x7735b6af, 0x7710f54c, 0x76ebea77, 0x76c69647, 0x76a0f8d2,
-  0x767b1231, 0x7654e279,
-  0x762e69c4, 0x7607a828, 0x75e09dbd, 0x75b94a9c, 0x7591aedd, 0x7569ca99,
-  0x75419de7, 0x751928e0,
-  0x74f06b9e, 0x74c7663a, 0x749e18cd, 0x74748371, 0x744aa63f, 0x74208150,
-  0x73f614c0, 0x73cb60a8,
-  0x73a06522, 0x73752249, 0x73499838, 0x731dc70a, 0x72f1aed9, 0x72c54fc1,
-  0x7298a9dd, 0x726bbd48,
-  0x723e8a20, 0x7211107e, 0x71e35080, 0x71b54a41, 0x7186fdde, 0x71586b74,
-  0x7129931f, 0x70fa74fc,
-  0x70cb1128, 0x709b67c0, 0x706b78e3, 0x703b44ad, 0x700acb3c, 0x6fda0cae,
-  0x6fa90921, 0x6f77c0b3,
-  0x6f463383, 0x6f1461b0, 0x6ee24b57, 0x6eaff099, 0x6e7d5193, 0x6e4a6e66,
-  0x6e174730, 0x6de3dc11,
-  0x6db02d29, 0x6d7c3a98, 0x6d48047e, 0x6d138afb, 0x6cdece2f, 0x6ca9ce3b,
-  0x6c748b3f, 0x6c3f055d,
-  0x6c093cb6, 0x6bd3316a, 0x6b9ce39b, 0x6b66536b, 0x6b2f80fb, 0x6af86c6c,
-  0x6ac115e2, 0x6a897d7d,
-  0x6a51a361, 0x6a1987b0, 0x69e12a8c, 0x69a88c19, 0x696fac78, 0x69368bce,
-  0x68fd2a3d, 0x68c387e9,
-  0x6889a4f6, 0x684f8186, 0x68151dbe, 0x67da79c3, 0x679f95b7, 0x676471c0,
-  0x67290e02, 0x66ed6aa1,
-  0x66b187c3, 0x6675658c, 0x66390422, 0x65fc63a9, 0x65bf8447, 0x65826622,
-  0x6545095f, 0x65076e25,
-  0x64c99498, 0x648b7ce0, 0x644d2722, 0x640e9386, 0x63cfc231, 0x6390b34a,
-  0x635166f9, 0x6311dd64,
-  0x62d216b3, 0x6292130c, 0x6251d298, 0x6211557e, 0x61d09be5, 0x618fa5f7,
-  0x614e73da, 0x610d05b7,
-  0x60cb5bb7, 0x60897601, 0x604754bf, 0x6004f819, 0x5fc26038, 0x5f7f8d46,
-  0x5f3c7f6b, 0x5ef936d1,
-  0x5eb5b3a2, 0x5e71f606, 0x5e2dfe29, 0x5de9cc33, 0x5da5604f, 0x5d60baa7,
-  0x5d1bdb65, 0x5cd6c2b5,
-  0x5c9170bf, 0x5c4be5b0, 0x5c0621b2, 0x5bc024f0, 0x5b79ef96, 0x5b3381ce,
-  0x5aecdbc5, 0x5aa5fda5,
-  0x5a5ee79a, 0x5a1799d1, 0x59d01475, 0x598857b2, 0x594063b5, 0x58f838a9,
-  0x58afd6bd, 0x58673e1b,
-  0x581e6ef1, 0x57d5696d, 0x578c2dba, 0x5742bc06, 0x56f9147e, 0x56af3750,
-  0x566524aa, 0x561adcb9,
-  0x55d05faa, 0x5585adad, 0x553ac6ee, 0x54efab9c, 0x54a45be6, 0x5458d7f9,
-  0x540d2005, 0x53c13439,
-  0x537514c2, 0x5328c1d0, 0x52dc3b92, 0x528f8238, 0x524295f0, 0x51f576ea,
-  0x51a82555, 0x515aa162,
-  0x510ceb40, 0x50bf031f, 0x5070e92f, 0x50229da1, 0x4fd420a4, 0x4f857269,
-  0x4f369320, 0x4ee782fb,
-  0x4e984229, 0x4e48d0dd, 0x4df92f46, 0x4da95d96, 0x4d595bfe, 0x4d092ab0,
-  0x4cb8c9dd, 0x4c6839b7,
-  0x4c177a6e, 0x4bc68c36, 0x4b756f40, 0x4b2423be, 0x4ad2a9e2, 0x4a8101de,
-  0x4a2f2be6, 0x49dd282a,
-  0x498af6df, 0x49389836, 0x48e60c62, 0x48935397, 0x48406e08, 0x47ed5be6,
-  0x479a1d67, 0x4746b2bc,
-  0x46f31c1a, 0x469f59b4, 0x464b6bbe, 0x45f7526b, 0x45a30df0, 0x454e9e80,
-  0x44fa0450, 0x44a53f93,
-  0x4450507e, 0x43fb3746, 0x43a5f41e, 0x4350873c, 0x42faf0d4, 0x42a5311b,
-  0x424f4845, 0x41f93689,
-  0x41a2fc1a, 0x414c992f, 0x40f60dfb, 0x409f5ab6, 0x40487f94, 0x3ff17cca,
-  0x3f9a5290, 0x3f430119,
-  0x3eeb889c, 0x3e93e950, 0x3e3c2369, 0x3de4371f, 0x3d8c24a8, 0x3d33ec39,
-  0x3cdb8e09, 0x3c830a50,
-  0x3c2a6142, 0x3bd19318, 0x3b78a007, 0x3b1f8848, 0x3ac64c0f, 0x3a6ceb96,
-  0x3a136712, 0x39b9bebc,
-  0x395ff2c9, 0x39060373, 0x38abf0ef, 0x3851bb77, 0x37f76341, 0x379ce885,
-  0x37424b7b, 0x36e78c5b,
-  0x368cab5c, 0x3631a8b8, 0x35d684a6, 0x357b3f5d, 0x351fd918, 0x34c4520d,
-  0x3468aa76, 0x340ce28b,
-  0x33b0fa84, 0x3354f29b, 0x32f8cb07, 0x329c8402, 0x32401dc6, 0x31e39889,
-  0x3186f487, 0x312a31f8,
-  0x30cd5115, 0x30705217, 0x30133539, 0x2fb5fab2, 0x2f58a2be, 0x2efb2d95,
-  0x2e9d9b70, 0x2e3fec8b,
-  0x2de2211e, 0x2d843964, 0x2d263596, 0x2cc815ee, 0x2c69daa6, 0x2c0b83fa,
-  0x2bad1221, 0x2b4e8558,
-  0x2aefddd8, 0x2a911bdc, 0x2a323f9e, 0x29d34958, 0x29743946, 0x29150fa1,
-  0x28b5cca5, 0x2856708d,
-  0x27f6fb92, 0x27976df1, 0x2737c7e3, 0x26d809a5, 0x26783370, 0x26184581,
-  0x25b84012, 0x2558235f,
-  0x24f7efa2, 0x2497a517, 0x243743fa, 0x23d6cc87, 0x23763ef7, 0x23159b88,
-  0x22b4e274, 0x225413f8,
-  0x21f3304f, 0x219237b5, 0x21312a65, 0x20d0089c, 0x206ed295, 0x200d888d,
-  0x1fac2abf, 0x1f4ab968,
-  0x1ee934c3, 0x1e879d0d, 0x1e25f282, 0x1dc4355e, 0x1d6265dd, 0x1d00843d,
-  0x1c9e90b8, 0x1c3c8b8c,
-  0x1bda74f6, 0x1b784d30, 0x1b161479, 0x1ab3cb0d, 0x1a517128, 0x19ef0707,
-  0x198c8ce7, 0x192a0304,
-  0x18c7699b, 0x1864c0ea, 0x1802092c, 0x179f429f, 0x173c6d80, 0x16d98a0c,
-  0x1676987f, 0x16139918,
-  0x15b08c12, 0x154d71aa, 0x14ea4a1f, 0x148715ae, 0x1423d492, 0x13c0870a,
-  0x135d2d53, 0x12f9c7aa,
-  0x1296564d, 0x1232d979, 0x11cf516a, 0x116bbe60, 0x11082096, 0x10a4784b,
-  0x1040c5bb, 0xfdd0926,
-  0xf7942c7, 0xf1572dc, 0xeb199a4, 0xe4db75b, 0xde9cc40, 0xd85d88f, 0xd21dc87,
-  0xcbdd865,
-  0xc59cc68, 0xbf5b8cb, 0xb919dcf, 0xb2d7baf, 0xac952aa, 0xa6522fe, 0xa00ece8,
-  0x99cb0a7,
-  0x9386e78, 0x8d42699, 0x86fd947, 0x80b86c2, 0x7a72f45, 0x742d311, 0x6de7262,
-  0x67a0d76,
-  0x615a48b, 0x5b137df, 0x54cc7b1, 0x4e8543e, 0x483ddc3, 0x41f6480, 0x3bae8b2,
-  0x3566a96,
-  0x2f1ea6c, 0x28d6870, 0x228e4e2, 0x1c45ffe, 0x15fda03, 0xfb5330, 0x96cbc1,
-  0x3243f5,
-};
-
-static const q31_t cos_factorsQ31_2048[2048] = {
-  0x7fffff62, 0x7ffffa73, 0x7ffff094, 0x7fffe1c6, 0x7fffce09, 0x7fffb55c,
-  0x7fff97c1, 0x7fff7536,
-  0x7fff4dbb, 0x7fff2151, 0x7ffeeff8, 0x7ffeb9b0, 0x7ffe7e79, 0x7ffe3e52,
-  0x7ffdf93c, 0x7ffdaf37,
-  0x7ffd6042, 0x7ffd0c5f, 0x7ffcb38c, 0x7ffc55ca, 0x7ffbf319, 0x7ffb8b78,
-  0x7ffb1ee9, 0x7ffaad6a,
-  0x7ffa36fc, 0x7ff9bba0, 0x7ff93b54, 0x7ff8b619, 0x7ff82bef, 0x7ff79cd6,
-  0x7ff708ce, 0x7ff66fd7,
-  0x7ff5d1f1, 0x7ff52f1d, 0x7ff48759, 0x7ff3daa6, 0x7ff32905, 0x7ff27275,
-  0x7ff1b6f6, 0x7ff0f688,
-  0x7ff0312c, 0x7fef66e1, 0x7fee97a7, 0x7fedc37e, 0x7fecea67, 0x7fec0c62,
-  0x7feb296d, 0x7fea418b,
-  0x7fe954ba, 0x7fe862fa, 0x7fe76c4c, 0x7fe670b0, 0x7fe57025, 0x7fe46aac,
-  0x7fe36045, 0x7fe250ef,
-  0x7fe13cac, 0x7fe0237a, 0x7fdf055a, 0x7fdde24d, 0x7fdcba51, 0x7fdb8d67,
-  0x7fda5b8f, 0x7fd924ca,
-  0x7fd7e917, 0x7fd6a875, 0x7fd562e7, 0x7fd4186a, 0x7fd2c900, 0x7fd174a8,
-  0x7fd01b63, 0x7fcebd31,
-  0x7fcd5a11, 0x7fcbf203, 0x7fca8508, 0x7fc91320, 0x7fc79c4b, 0x7fc62089,
-  0x7fc49fda, 0x7fc31a3d,
-  0x7fc18fb4, 0x7fc0003e, 0x7fbe6bdb, 0x7fbcd28b, 0x7fbb344e, 0x7fb99125,
-  0x7fb7e90f, 0x7fb63c0d,
-  0x7fb48a1e, 0x7fb2d343, 0x7fb1177b, 0x7faf56c7, 0x7fad9127, 0x7fabc69b,
-  0x7fa9f723, 0x7fa822bf,
-  0x7fa6496e, 0x7fa46b32, 0x7fa2880b, 0x7fa09ff7, 0x7f9eb2f8, 0x7f9cc10d,
-  0x7f9aca37, 0x7f98ce76,
-  0x7f96cdc9, 0x7f94c831, 0x7f92bdad, 0x7f90ae3f, 0x7f8e99e6, 0x7f8c80a1,
-  0x7f8a6272, 0x7f883f58,
-  0x7f861753, 0x7f83ea64, 0x7f81b88a, 0x7f7f81c6, 0x7f7d4617, 0x7f7b057e,
-  0x7f78bffb, 0x7f76758e,
-  0x7f742637, 0x7f71d1f6, 0x7f6f78cb, 0x7f6d1ab6, 0x7f6ab7b8, 0x7f684fd0,
-  0x7f65e2ff, 0x7f637144,
-  0x7f60faa0, 0x7f5e7f13, 0x7f5bfe9d, 0x7f59793e, 0x7f56eef5, 0x7f545fc5,
-  0x7f51cbab, 0x7f4f32a9,
-  0x7f4c94be, 0x7f49f1eb, 0x7f474a30, 0x7f449d8c, 0x7f41ec01, 0x7f3f358d,
-  0x7f3c7a31, 0x7f39b9ee,
-  0x7f36f4c3, 0x7f342ab1, 0x7f315bb7, 0x7f2e87d6, 0x7f2baf0d, 0x7f28d15d,
-  0x7f25eec7, 0x7f230749,
-  0x7f201ae5, 0x7f1d299a, 0x7f1a3368, 0x7f173850, 0x7f143852, 0x7f11336d,
-  0x7f0e29a3, 0x7f0b1af2,
-  0x7f08075c, 0x7f04eedf, 0x7f01d17d, 0x7efeaf36, 0x7efb8809, 0x7ef85bf7,
-  0x7ef52b00, 0x7ef1f524,
-  0x7eeeba62, 0x7eeb7abc, 0x7ee83632, 0x7ee4ecc3, 0x7ee19e6f, 0x7ede4b38,
-  0x7edaf31c, 0x7ed7961c,
-  0x7ed43438, 0x7ed0cd70, 0x7ecd61c5, 0x7ec9f137, 0x7ec67bc5, 0x7ec3016f,
-  0x7ebf8237, 0x7ebbfe1c,
-  0x7eb8751e, 0x7eb4e73d, 0x7eb1547a, 0x7eadbcd4, 0x7eaa204c, 0x7ea67ee2,
-  0x7ea2d896, 0x7e9f2d68,
-  0x7e9b7d58, 0x7e97c867, 0x7e940e94, 0x7e904fe0, 0x7e8c8c4b, 0x7e88c3d5,
-  0x7e84f67e, 0x7e812447,
-  0x7e7d4d2f, 0x7e797136, 0x7e75905d, 0x7e71aaa4, 0x7e6dc00c, 0x7e69d093,
-  0x7e65dc3b, 0x7e61e303,
-  0x7e5de4ec, 0x7e59e1f5, 0x7e55da20, 0x7e51cd6c, 0x7e4dbbd9, 0x7e49a567,
-  0x7e458a17, 0x7e4169e9,
-  0x7e3d44dd, 0x7e391af3, 0x7e34ec2b, 0x7e30b885, 0x7e2c8002, 0x7e2842a2,
-  0x7e240064, 0x7e1fb94a,
-  0x7e1b6d53, 0x7e171c7f, 0x7e12c6ce, 0x7e0e6c42, 0x7e0a0cd9, 0x7e05a894,
-  0x7e013f74, 0x7dfcd178,
-  0x7df85ea0, 0x7df3e6ee, 0x7def6a60, 0x7deae8f7, 0x7de662b3, 0x7de1d795,
-  0x7ddd479d, 0x7dd8b2ca,
-  0x7dd4191d, 0x7dcf7a96, 0x7dcad736, 0x7dc62efc, 0x7dc181e8, 0x7dbccffc,
-  0x7db81936, 0x7db35d98,
-  0x7dae9d21, 0x7da9d7d2, 0x7da50dab, 0x7da03eab, 0x7d9b6ad3, 0x7d969224,
-  0x7d91b49e, 0x7d8cd240,
-  0x7d87eb0a, 0x7d82fefe, 0x7d7e0e1c, 0x7d791862, 0x7d741dd2, 0x7d6f1e6c,
-  0x7d6a1a31, 0x7d65111f,
-  0x7d600338, 0x7d5af07b, 0x7d55d8e9, 0x7d50bc82, 0x7d4b9b46, 0x7d467536,
-  0x7d414a51, 0x7d3c1a98,
-  0x7d36e60b, 0x7d31acaa, 0x7d2c6e76, 0x7d272b6e, 0x7d21e393, 0x7d1c96e5,
-  0x7d174564, 0x7d11ef11,
-  0x7d0c93eb, 0x7d0733f3, 0x7d01cf29, 0x7cfc658d, 0x7cf6f720, 0x7cf183e1,
-  0x7cec0bd1, 0x7ce68ef0,
-  0x7ce10d3f, 0x7cdb86bd, 0x7cd5fb6a, 0x7cd06b48, 0x7ccad656, 0x7cc53c94,
-  0x7cbf9e03, 0x7cb9faa2,
-  0x7cb45272, 0x7caea574, 0x7ca8f3a7, 0x7ca33d0c, 0x7c9d81a3, 0x7c97c16b,
-  0x7c91fc66, 0x7c8c3294,
-  0x7c8663f4, 0x7c809088, 0x7c7ab84e, 0x7c74db48, 0x7c6ef976, 0x7c6912d7,
-  0x7c63276d, 0x7c5d3737,
-  0x7c574236, 0x7c514869, 0x7c4b49d2, 0x7c45466f, 0x7c3f3e42, 0x7c39314b,
-  0x7c331f8a, 0x7c2d08ff,
-  0x7c26edab, 0x7c20cd8d, 0x7c1aa8a6, 0x7c147ef6, 0x7c0e507e, 0x7c081d3d,
-  0x7c01e534, 0x7bfba863,
-  0x7bf566cb, 0x7bef206b, 0x7be8d544, 0x7be28556, 0x7bdc30a1, 0x7bd5d726,
-  0x7bcf78e5, 0x7bc915dd,
-  0x7bc2ae10, 0x7bbc417e, 0x7bb5d026, 0x7baf5a09, 0x7ba8df28, 0x7ba25f82,
-  0x7b9bdb18, 0x7b9551ea,
-  0x7b8ec3f8, 0x7b883143, 0x7b8199ca, 0x7b7afd8f, 0x7b745c91, 0x7b6db6d0,
-  0x7b670c4d, 0x7b605d09,
-  0x7b59a902, 0x7b52f03a, 0x7b4c32b1, 0x7b457068, 0x7b3ea95d, 0x7b37dd92,
-  0x7b310d07, 0x7b2a37bc,
-  0x7b235db2, 0x7b1c7ee8, 0x7b159b5f, 0x7b0eb318, 0x7b07c612, 0x7b00d44d,
-  0x7af9ddcb, 0x7af2e28b,
-  0x7aebe28d, 0x7ae4ddd2, 0x7addd45b, 0x7ad6c626, 0x7acfb336, 0x7ac89b89,
-  0x7ac17f20, 0x7aba5dfc,
-  0x7ab3381d, 0x7aac0d82, 0x7aa4de2d, 0x7a9daa1d, 0x7a967153, 0x7a8f33d0,
-  0x7a87f192, 0x7a80aa9c,
-  0x7a795eec, 0x7a720e84, 0x7a6ab963, 0x7a635f8a, 0x7a5c00f9, 0x7a549db0,
-  0x7a4d35b0, 0x7a45c8f9,
-  0x7a3e578b, 0x7a36e166, 0x7a2f668c, 0x7a27e6fb, 0x7a2062b5, 0x7a18d9b9,
-  0x7a114c09, 0x7a09b9a4,
-  0x7a02228a, 0x79fa86bc, 0x79f2e63a, 0x79eb4105, 0x79e3971c, 0x79dbe880,
-  0x79d43532, 0x79cc7d31,
-  0x79c4c07e, 0x79bcff19, 0x79b53903, 0x79ad6e3c, 0x79a59ec3, 0x799dca9a,
-  0x7995f1c1, 0x798e1438,
-  0x798631ff, 0x797e4b16, 0x79765f7f, 0x796e6f39, 0x79667a44, 0x795e80a1,
-  0x79568250, 0x794e7f52,
-  0x794677a6, 0x793e6b4e, 0x79365a49, 0x792e4497, 0x79262a3a, 0x791e0b31,
-  0x7915e77c, 0x790dbf1d,
-  0x79059212, 0x78fd605d, 0x78f529fe, 0x78eceef6, 0x78e4af44, 0x78dc6ae8,
-  0x78d421e4, 0x78cbd437,
-  0x78c381e2, 0x78bb2ae5, 0x78b2cf41, 0x78aa6ef5, 0x78a20a03, 0x7899a06a,
-  0x7891322a, 0x7888bf45,
-  0x788047ba, 0x7877cb89, 0x786f4ab4, 0x7866c53a, 0x785e3b1c, 0x7855ac5a,
-  0x784d18f4, 0x784480ea,
-  0x783be43e, 0x783342ef, 0x782a9cfe, 0x7821f26b, 0x78194336, 0x78108f60,
-  0x7807d6e9, 0x77ff19d1,
-  0x77f65819, 0x77ed91c0, 0x77e4c6c9, 0x77dbf732, 0x77d322fc, 0x77ca4a27,
-  0x77c16cb4, 0x77b88aa3,
-  0x77afa3f5, 0x77a6b8a9, 0x779dc8c0, 0x7794d43b, 0x778bdb19, 0x7782dd5c,
-  0x7779db03, 0x7770d40f,
-  0x7767c880, 0x775eb857, 0x7755a394, 0x774c8a36, 0x77436c40, 0x773a49b0,
-  0x77312287, 0x7727f6c6,
-  0x771ec66e, 0x7715917d, 0x770c57f5, 0x770319d6, 0x76f9d721, 0x76f08fd5,
-  0x76e743f4, 0x76ddf37c,
-  0x76d49e70, 0x76cb44cf, 0x76c1e699, 0x76b883d0, 0x76af1c72, 0x76a5b082,
-  0x769c3ffe, 0x7692cae8,
-  0x7689513f, 0x767fd304, 0x76765038, 0x766cc8db, 0x76633ced, 0x7659ac6f,
-  0x76501760, 0x76467dc2,
-  0x763cdf94, 0x76333cd8, 0x7629958c, 0x761fe9b3, 0x7616394c, 0x760c8457,
-  0x7602cad5, 0x75f90cc7,
-  0x75ef4a2c, 0x75e58305, 0x75dbb753, 0x75d1e715, 0x75c8124d, 0x75be38fa,
-  0x75b45b1d, 0x75aa78b6,
-  0x75a091c6, 0x7596a64d, 0x758cb64c, 0x7582c1c2, 0x7578c8b0, 0x756ecb18,
-  0x7564c8f8, 0x755ac251,
-  0x7550b725, 0x7546a772, 0x753c933a, 0x75327a7d, 0x75285d3b, 0x751e3b75,
-  0x7514152b, 0x7509ea5d,
-  0x74ffbb0d, 0x74f58739, 0x74eb4ee3, 0x74e1120c, 0x74d6d0b2, 0x74cc8ad8,
-  0x74c2407d, 0x74b7f1a1,
-  0x74ad9e46, 0x74a3466b, 0x7498ea11, 0x748e8938, 0x748423e0, 0x7479ba0b,
-  0x746f4bb8, 0x7464d8e8,
-  0x745a619b, 0x744fe5d2, 0x7445658d, 0x743ae0cc, 0x74305790, 0x7425c9da,
-  0x741b37a9, 0x7410a0fe,
-  0x740605d9, 0x73fb663c, 0x73f0c226, 0x73e61997, 0x73db6c91, 0x73d0bb13,
-  0x73c6051f, 0x73bb4ab3,
-  0x73b08bd1, 0x73a5c87a, 0x739b00ad, 0x7390346b, 0x738563b5, 0x737a8e8a,
-  0x736fb4ec, 0x7364d6da,
-  0x7359f456, 0x734f0d5f, 0x734421f6, 0x7339321b, 0x732e3dcf, 0x73234512,
-  0x731847e5, 0x730d4648,
-  0x7302403c, 0x72f735c0, 0x72ec26d6, 0x72e1137d, 0x72d5fbb7, 0x72cadf83,
-  0x72bfbee3, 0x72b499d6,
-  0x72a9705c, 0x729e4277, 0x72931027, 0x7287d96c, 0x727c9e47, 0x72715eb8,
-  0x72661abf, 0x725ad25d,
-  0x724f8593, 0x72443460, 0x7238dec5, 0x722d84c4, 0x7222265b, 0x7216c38c,
-  0x720b5c57, 0x71fff0bc,
-  0x71f480bc, 0x71e90c57, 0x71dd938f, 0x71d21662, 0x71c694d2, 0x71bb0edf,
-  0x71af848a, 0x71a3f5d2,
-  0x719862b9, 0x718ccb3f, 0x71812f65, 0x71758f29, 0x7169ea8f, 0x715e4194,
-  0x7152943b, 0x7146e284,
-  0x713b2c6e, 0x712f71fb, 0x7123b32b, 0x7117effe, 0x710c2875, 0x71005c90,
-  0x70f48c50, 0x70e8b7b5,
-  0x70dcdec0, 0x70d10171, 0x70c51fc8, 0x70b939c7, 0x70ad4f6d, 0x70a160ba,
-  0x70956db1, 0x70897650,
-  0x707d7a98, 0x70717a8a, 0x70657626, 0x70596d6d, 0x704d6060, 0x70414efd,
-  0x70353947, 0x70291f3e,
-  0x701d00e1, 0x7010de32, 0x7004b731, 0x6ff88bde, 0x6fec5c3b, 0x6fe02846,
-  0x6fd3f001, 0x6fc7b36d,
-  0x6fbb728a, 0x6faf2d57, 0x6fa2e3d7, 0x6f969608, 0x6f8a43ed, 0x6f7ded84,
-  0x6f7192cf, 0x6f6533ce,
-  0x6f58d082, 0x6f4c68eb, 0x6f3ffd09, 0x6f338cde, 0x6f271868, 0x6f1a9faa,
-  0x6f0e22a3, 0x6f01a155,
-  0x6ef51bbe, 0x6ee891e1, 0x6edc03bc, 0x6ecf7152, 0x6ec2daa2, 0x6eb63fad,
-  0x6ea9a073, 0x6e9cfcf5,
-  0x6e905534, 0x6e83a92f, 0x6e76f8e7, 0x6e6a445d, 0x6e5d8b91, 0x6e50ce84,
-  0x6e440d37, 0x6e3747a9,
-  0x6e2a7ddb, 0x6e1dafce, 0x6e10dd82, 0x6e0406f8, 0x6df72c30, 0x6dea4d2b,
-  0x6ddd69e9, 0x6dd0826a,
-  0x6dc396b0, 0x6db6a6ba, 0x6da9b28a, 0x6d9cba1f, 0x6d8fbd7a, 0x6d82bc9d,
-  0x6d75b786, 0x6d68ae37,
-  0x6d5ba0b0, 0x6d4e8ef2, 0x6d4178fd, 0x6d345ed1, 0x6d274070, 0x6d1a1dda,
-  0x6d0cf70f, 0x6cffcc0f,
-  0x6cf29cdc, 0x6ce56975, 0x6cd831dc, 0x6ccaf610, 0x6cbdb613, 0x6cb071e4,
-  0x6ca32985, 0x6c95dcf6,
-  0x6c888c36, 0x6c7b3748, 0x6c6dde2b, 0x6c6080e0, 0x6c531f67, 0x6c45b9c1,
-  0x6c384fef, 0x6c2ae1f0,
-  0x6c1d6fc6, 0x6c0ff971, 0x6c027ef1, 0x6bf50047, 0x6be77d74, 0x6bd9f677,
-  0x6bcc6b53, 0x6bbedc06,
-  0x6bb14892, 0x6ba3b0f7, 0x6b961536, 0x6b88754f, 0x6b7ad142, 0x6b6d2911,
-  0x6b5f7cbc, 0x6b51cc42,
-  0x6b4417a6, 0x6b365ee7, 0x6b28a206, 0x6b1ae103, 0x6b0d1bdf, 0x6aff529a,
-  0x6af18536, 0x6ae3b3b2,
-  0x6ad5de0f, 0x6ac8044e, 0x6aba266e, 0x6aac4472, 0x6a9e5e58, 0x6a907423,
-  0x6a8285d1, 0x6a749365,
-  0x6a669cdd, 0x6a58a23c, 0x6a4aa381, 0x6a3ca0ad, 0x6a2e99c0, 0x6a208ebb,
-  0x6a127f9f, 0x6a046c6c,
-  0x69f65523, 0x69e839c4, 0x69da1a50, 0x69cbf6c7, 0x69bdcf29, 0x69afa378,
-  0x69a173b5, 0x69933fde,
-  0x698507f6, 0x6976cbfc, 0x69688bf1, 0x695a47d6, 0x694bffab, 0x693db371,
-  0x692f6328, 0x69210ed1,
-  0x6912b66c, 0x690459fb, 0x68f5f97d, 0x68e794f3, 0x68d92c5d, 0x68cabfbd,
-  0x68bc4f13, 0x68adda5f,
-  0x689f61a1, 0x6890e4dc, 0x6882640e, 0x6873df38, 0x6865565c, 0x6856c979,
-  0x68483891, 0x6839a3a4,
-  0x682b0ab1, 0x681c6dbb, 0x680dccc1, 0x67ff27c4, 0x67f07ec5, 0x67e1d1c4,
-  0x67d320c1, 0x67c46bbe,
-  0x67b5b2bb, 0x67a6f5b8, 0x679834b6, 0x67896fb6, 0x677aa6b8, 0x676bd9bd,
-  0x675d08c4, 0x674e33d0,
-  0x673f5ae0, 0x67307df5, 0x67219d10, 0x6712b831, 0x6703cf58, 0x66f4e287,
-  0x66e5f1be, 0x66d6fcfd,
-  0x66c80445, 0x66b90797, 0x66aa06f3, 0x669b0259, 0x668bf9cb, 0x667ced49,
-  0x666ddcd3, 0x665ec86b,
-  0x664fb010, 0x664093c3, 0x66317385, 0x66224f56, 0x66132738, 0x6603fb2a,
-  0x65f4cb2d, 0x65e59742,
-  0x65d65f69, 0x65c723a3, 0x65b7e3f1, 0x65a8a052, 0x659958c9, 0x658a0d54,
-  0x657abdf6, 0x656b6aae,
-  0x655c137d, 0x654cb863, 0x653d5962, 0x652df679, 0x651e8faa, 0x650f24f5,
-  0x64ffb65b, 0x64f043dc,
-  0x64e0cd78, 0x64d15331, 0x64c1d507, 0x64b252fa, 0x64a2cd0c, 0x6493433c,
-  0x6483b58c, 0x647423fb,
-  0x64648e8c, 0x6454f53d, 0x64455810, 0x6435b706, 0x6426121e, 0x6416695a,
-  0x6406bcba, 0x63f70c3f,
-  0x63e757ea, 0x63d79fba, 0x63c7e3b1, 0x63b823cf, 0x63a86015, 0x63989884,
-  0x6388cd1b, 0x6378fddc,
-  0x63692ac7, 0x635953dd, 0x6349791f, 0x63399a8d, 0x6329b827, 0x6319d1ef,
-  0x6309e7e4, 0x62f9fa09,
-  0x62ea085c, 0x62da12df, 0x62ca1992, 0x62ba1c77, 0x62aa1b8d, 0x629a16d5,
-  0x628a0e50, 0x627a01fe,
-  0x6269f1e1, 0x6259ddf8, 0x6249c645, 0x6239aac7, 0x62298b81, 0x62196871,
-  0x62094199, 0x61f916f9,
-  0x61e8e893, 0x61d8b666, 0x61c88074, 0x61b846bc, 0x61a80940, 0x6197c800,
-  0x618782fd, 0x61773a37,
-  0x6166edb0, 0x61569d67, 0x6146495d, 0x6135f193, 0x6125960a, 0x611536c2,
-  0x6104d3bc, 0x60f46cf9,
-  0x60e40278, 0x60d3943b, 0x60c32243, 0x60b2ac8f, 0x60a23322, 0x6091b5fa,
-  0x60813519, 0x6070b080,
-  0x6060282f, 0x604f9c27, 0x603f0c69, 0x602e78f4, 0x601de1ca, 0x600d46ec,
-  0x5ffca859, 0x5fec0613,
-  0x5fdb601b, 0x5fcab670, 0x5fba0914, 0x5fa95807, 0x5f98a34a, 0x5f87eade,
-  0x5f772ec2, 0x5f666ef9,
-  0x5f55ab82, 0x5f44e45e, 0x5f34198e, 0x5f234b12, 0x5f1278eb, 0x5f01a31a,
-  0x5ef0c99f, 0x5edfec7b,
-  0x5ecf0baf, 0x5ebe273b, 0x5ead3f1f, 0x5e9c535e, 0x5e8b63f7, 0x5e7a70ea,
-  0x5e697a39, 0x5e587fe5,
-  0x5e4781ed, 0x5e368053, 0x5e257b17, 0x5e147239, 0x5e0365bb, 0x5df2559e,
-  0x5de141e1, 0x5dd02a85,
-  0x5dbf0f8c, 0x5dadf0f5, 0x5d9ccec2, 0x5d8ba8f3, 0x5d7a7f88, 0x5d695283,
-  0x5d5821e4, 0x5d46edac,
-  0x5d35b5db, 0x5d247a72, 0x5d133b72, 0x5d01f8dc, 0x5cf0b2af, 0x5cdf68ed,
-  0x5cce1b97, 0x5cbccaac,
-  0x5cab762f, 0x5c9a1e1e, 0x5c88c27c, 0x5c776348, 0x5c660084, 0x5c549a30,
-  0x5c43304d, 0x5c31c2db,
-  0x5c2051db, 0x5c0edd4e, 0x5bfd6534, 0x5bebe98e, 0x5bda6a5d, 0x5bc8e7a2,
-  0x5bb7615d, 0x5ba5d78e,
-  0x5b944a37, 0x5b82b958, 0x5b7124f2, 0x5b5f8d06, 0x5b4df193, 0x5b3c529c,
-  0x5b2ab020, 0x5b190a20,
-  0x5b07609d, 0x5af5b398, 0x5ae40311, 0x5ad24f09, 0x5ac09781, 0x5aaedc78,
-  0x5a9d1df1, 0x5a8b5bec,
-  0x5a799669, 0x5a67cd69, 0x5a5600ec, 0x5a4430f5, 0x5a325d82, 0x5a208695,
-  0x5a0eac2e, 0x59fcce4f,
-  0x59eaecf8, 0x59d90829, 0x59c71fe3, 0x59b53427, 0x59a344f6, 0x59915250,
-  0x597f5c36, 0x596d62a9,
-  0x595b65aa, 0x59496538, 0x59376155, 0x59255a02, 0x59134f3e, 0x5901410c,
-  0x58ef2f6b, 0x58dd1a5d,
-  0x58cb01e1, 0x58b8e5f9, 0x58a6c6a5, 0x5894a3e7, 0x58827dbe, 0x5870542c,
-  0x585e2730, 0x584bf6cd,
-  0x5839c302, 0x58278bd1, 0x58155139, 0x5803133c, 0x57f0d1da, 0x57de8d15,
-  0x57cc44ec, 0x57b9f960,
-  0x57a7aa73, 0x57955825, 0x57830276, 0x5770a968, 0x575e4cfa, 0x574bed2f,
-  0x57398a05, 0x5727237f,
-  0x5714b99d, 0x57024c5f, 0x56efdbc7, 0x56dd67d4, 0x56caf088, 0x56b875e4,
-  0x56a5f7e7, 0x56937694,
-  0x5680f1ea, 0x566e69ea, 0x565bde95, 0x56494fec, 0x5636bdef, 0x5624289f,
-  0x56118ffe, 0x55fef40a,
-  0x55ec54c6, 0x55d9b232, 0x55c70c4f, 0x55b4631d, 0x55a1b69d, 0x558f06d0,
-  0x557c53b6, 0x55699d51,
-  0x5556e3a1, 0x554426a7, 0x55316663, 0x551ea2d6, 0x550bdc01, 0x54f911e5,
-  0x54e64482, 0x54d373d9,
-  0x54c09feb, 0x54adc8b8, 0x549aee42, 0x54881089, 0x54752f8d, 0x54624b50,
-  0x544f63d2, 0x543c7914,
-  0x54298b17, 0x541699db, 0x5403a561, 0x53f0adaa, 0x53ddb2b6, 0x53cab486,
-  0x53b7b31c, 0x53a4ae77,
-  0x5391a699, 0x537e9b82, 0x536b8d33, 0x53587bad, 0x534566f0, 0x53324efd,
-  0x531f33d5, 0x530c1579,
-  0x52f8f3e9, 0x52e5cf27, 0x52d2a732, 0x52bf7c0b, 0x52ac4db4, 0x52991c2d,
-  0x5285e777, 0x5272af92,
-  0x525f7480, 0x524c3640, 0x5238f4d4, 0x5225b03d, 0x5212687b, 0x51ff1d8f,
-  0x51ebcf7a, 0x51d87e3c,
-  0x51c529d7, 0x51b1d24a, 0x519e7797, 0x518b19bf, 0x5177b8c2, 0x516454a0,
-  0x5150ed5c, 0x513d82f4,
-  0x512a156b, 0x5116a4c1, 0x510330f7, 0x50efba0d, 0x50dc4005, 0x50c8c2de,
-  0x50b5429a, 0x50a1bf39,
-  0x508e38bd, 0x507aaf25, 0x50672273, 0x505392a8, 0x503fffc4, 0x502c69c8,
-  0x5018d0b4, 0x5005348a,
-  0x4ff1954b, 0x4fddf2f6, 0x4fca4d8d, 0x4fb6a510, 0x4fa2f981, 0x4f8f4ae0,
-  0x4f7b992d, 0x4f67e46a,
-  0x4f542c98, 0x4f4071b6, 0x4f2cb3c7, 0x4f18f2c9, 0x4f052ec0, 0x4ef167aa,
-  0x4edd9d89, 0x4ec9d05e,
-  0x4eb60029, 0x4ea22ceb, 0x4e8e56a5, 0x4e7a7d58, 0x4e66a105, 0x4e52c1ab,
-  0x4e3edf4d, 0x4e2af9ea,
-  0x4e171184, 0x4e03261b, 0x4def37b0, 0x4ddb4644, 0x4dc751d8, 0x4db35a6c,
-  0x4d9f6001, 0x4d8b6298,
-  0x4d776231, 0x4d635ece, 0x4d4f5870, 0x4d3b4f16, 0x4d2742c2, 0x4d133374,
-  0x4cff212e, 0x4ceb0bf0,
-  0x4cd6f3bb, 0x4cc2d88f, 0x4caeba6e, 0x4c9a9958, 0x4c86754e, 0x4c724e50,
-  0x4c5e2460, 0x4c49f77f,
-  0x4c35c7ac, 0x4c2194e9, 0x4c0d5f37, 0x4bf92697, 0x4be4eb08, 0x4bd0ac8d,
-  0x4bbc6b25, 0x4ba826d1,
-  0x4b93df93, 0x4b7f956b, 0x4b6b485a, 0x4b56f861, 0x4b42a580, 0x4b2e4fb8,
-  0x4b19f70a, 0x4b059b77,
-  0x4af13d00, 0x4adcdba5, 0x4ac87767, 0x4ab41046, 0x4a9fa645, 0x4a8b3963,
-  0x4a76c9a2, 0x4a625701,
-  0x4a4de182, 0x4a396926, 0x4a24edee, 0x4a106fda, 0x49fbeeea, 0x49e76b21,
-  0x49d2e47e, 0x49be5b02,
-  0x49a9ceaf, 0x49953f84, 0x4980ad84, 0x496c18ae, 0x49578103, 0x4942e684,
-  0x492e4933, 0x4919a90f,
-  0x4905061a, 0x48f06054, 0x48dbb7be, 0x48c70c59, 0x48b25e25, 0x489dad25,
-  0x4888f957, 0x487442be,
-  0x485f8959, 0x484acd2a, 0x48360e32, 0x48214c71, 0x480c87e8, 0x47f7c099,
-  0x47e2f682, 0x47ce29a7,
-  0x47b95a06, 0x47a487a2, 0x478fb27b, 0x477ada91, 0x4765ffe6, 0x4751227a,
-  0x473c424e, 0x47275f63,
-  0x471279ba, 0x46fd9154, 0x46e8a631, 0x46d3b852, 0x46bec7b8, 0x46a9d464,
-  0x4694de56, 0x467fe590,
-  0x466aea12, 0x4655ebdd, 0x4640eaf2, 0x462be751, 0x4616e0fc, 0x4601d7f3,
-  0x45eccc37, 0x45d7bdc9,
-  0x45c2acaa, 0x45ad98da, 0x4598825a, 0x4583692c, 0x456e4d4f, 0x45592ec6,
-  0x45440d90, 0x452ee9ae,
-  0x4519c321, 0x450499eb, 0x44ef6e0b, 0x44da3f83, 0x44c50e53, 0x44afda7d,
-  0x449aa400, 0x44856adf,
-  0x44702f19, 0x445af0b0, 0x4445afa4, 0x44306bf6, 0x441b25a8, 0x4405dcb9,
-  0x43f0912b, 0x43db42fe,
-  0x43c5f234, 0x43b09ecc, 0x439b48c9, 0x4385f02a, 0x437094f1, 0x435b371f,
-  0x4345d6b3, 0x433073b0,
-  0x431b0e15, 0x4305a5e5, 0x42f03b1e, 0x42dacdc3, 0x42c55dd4, 0x42afeb53,
-  0x429a763f, 0x4284fe99,
-  0x426f8463, 0x425a079e, 0x42448849, 0x422f0667, 0x421981f7, 0x4203fafb,
-  0x41ee7174, 0x41d8e561,
-  0x41c356c5, 0x41adc5a0, 0x419831f3, 0x41829bbe, 0x416d0302, 0x415767c1,
-  0x4141c9fb, 0x412c29b1,
-  0x411686e4, 0x4100e194, 0x40eb39c3, 0x40d58f71, 0x40bfe29f, 0x40aa334e,
-  0x4094817f, 0x407ecd32,
-  0x40691669, 0x40535d24, 0x403da165, 0x4027e32b, 0x40122278, 0x3ffc5f4d,
-  0x3fe699aa, 0x3fd0d191,
-  0x3fbb0702, 0x3fa539fd, 0x3f8f6a85, 0x3f799899, 0x3f63c43b, 0x3f4ded6b,
-  0x3f38142a, 0x3f22387a,
-  0x3f0c5a5a, 0x3ef679cc, 0x3ee096d1, 0x3ecab169, 0x3eb4c995, 0x3e9edf57,
-  0x3e88f2ae, 0x3e73039d,
-  0x3e5d1222, 0x3e471e41, 0x3e3127f9, 0x3e1b2f4a, 0x3e053437, 0x3def36c0,
-  0x3dd936e6, 0x3dc334a9,
-  0x3dad300b, 0x3d97290b, 0x3d811fac, 0x3d6b13ee, 0x3d5505d2, 0x3d3ef559,
-  0x3d28e282, 0x3d12cd51,
-  0x3cfcb5c4, 0x3ce69bde, 0x3cd07f9f, 0x3cba6107, 0x3ca44018, 0x3c8e1cd3,
-  0x3c77f737, 0x3c61cf48,
-  0x3c4ba504, 0x3c35786d, 0x3c1f4983, 0x3c091849, 0x3bf2e4be, 0x3bdcaee3,
-  0x3bc676b9, 0x3bb03c42,
-  0x3b99ff7d, 0x3b83c06c, 0x3b6d7f10, 0x3b573b69, 0x3b40f579, 0x3b2aad3f,
-  0x3b1462be, 0x3afe15f6,
-  0x3ae7c6e7, 0x3ad17593, 0x3abb21fb, 0x3aa4cc1e, 0x3a8e7400, 0x3a78199f,
-  0x3a61bcfd, 0x3a4b5e1b,
-  0x3a34fcf9, 0x3a1e9999, 0x3a0833fc, 0x39f1cc21, 0x39db620b, 0x39c4f5ba,
-  0x39ae872f, 0x3998166a,
-  0x3981a36d, 0x396b2e38, 0x3954b6cd, 0x393e3d2c, 0x3927c155, 0x3911434b,
-  0x38fac30e, 0x38e4409e,
-  0x38cdbbfc, 0x38b7352a, 0x38a0ac29, 0x388a20f8, 0x38739399, 0x385d040d,
-  0x38467255, 0x382fde72,
-  0x38194864, 0x3802b02c, 0x37ec15cb, 0x37d57943, 0x37beda93, 0x37a839be,
-  0x379196c3, 0x377af1a3,
-  0x37644a60, 0x374da0fa, 0x3736f573, 0x372047ca, 0x37099802, 0x36f2e61a,
-  0x36dc3214, 0x36c57bf0,
-  0x36aec3b0, 0x36980954, 0x36814cde, 0x366a8e4d, 0x3653cda3, 0x363d0ae2,
-  0x36264609, 0x360f7f19,
-  0x35f8b614, 0x35e1eafa, 0x35cb1dcc, 0x35b44e8c, 0x359d7d39, 0x3586a9d5,
-  0x356fd461, 0x3558fcde,
-  0x3542234c, 0x352b47ad, 0x35146a00, 0x34fd8a48, 0x34e6a885, 0x34cfc4b7,
-  0x34b8dee1, 0x34a1f702,
-  0x348b0d1c, 0x3474212f, 0x345d333c, 0x34464345, 0x342f5149, 0x34185d4b,
-  0x3401674a, 0x33ea6f48,
-  0x33d37546, 0x33bc7944, 0x33a57b44, 0x338e7b46, 0x3377794b, 0x33607554,
-  0x33496f62, 0x33326776,
-  0x331b5d91, 0x330451b3, 0x32ed43de, 0x32d63412, 0x32bf2250, 0x32a80e99,
-  0x3290f8ef, 0x3279e151,
-  0x3262c7c1, 0x324bac40, 0x32348ecf, 0x321d6f6e, 0x32064e1e, 0x31ef2ae1,
-  0x31d805b7, 0x31c0dea1,
-  0x31a9b5a0, 0x31928ab4, 0x317b5de0, 0x31642f23, 0x314cfe7f, 0x3135cbf4,
-  0x311e9783, 0x3107612e,
-  0x30f028f4, 0x30d8eed8, 0x30c1b2da, 0x30aa74fa, 0x3093353a, 0x307bf39b,
-  0x3064b01d, 0x304d6ac1,
-  0x30362389, 0x301eda75, 0x30078f86, 0x2ff042bd, 0x2fd8f41b, 0x2fc1a3a0,
-  0x2faa514f, 0x2f92fd26,
-  0x2f7ba729, 0x2f644f56, 0x2f4cf5b0, 0x2f359a37, 0x2f1e3ced, 0x2f06ddd1,
-  0x2eef7ce5, 0x2ed81a29,
-  0x2ec0b5a0, 0x2ea94f49, 0x2e91e725, 0x2e7a7d36, 0x2e63117c, 0x2e4ba3f8,
-  0x2e3434ac, 0x2e1cc397,
-  0x2e0550bb, 0x2deddc19, 0x2dd665b2, 0x2dbeed86, 0x2da77397, 0x2d8ff7e5,
-  0x2d787a72, 0x2d60fb3e,
-  0x2d497a4a, 0x2d31f797, 0x2d1a7325, 0x2d02ecf7, 0x2ceb650d, 0x2cd3db67,
-  0x2cbc5006, 0x2ca4c2ed,
-  0x2c8d341a, 0x2c75a390, 0x2c5e114f, 0x2c467d58, 0x2c2ee7ad, 0x2c17504d,
-  0x2bffb73a, 0x2be81c74,
-  0x2bd07ffe, 0x2bb8e1d7, 0x2ba14200, 0x2b89a07b, 0x2b71fd48, 0x2b5a5868,
-  0x2b42b1dd, 0x2b2b09a6,
-  0x2b135fc6, 0x2afbb43c, 0x2ae4070a, 0x2acc5831, 0x2ab4a7b1, 0x2a9cf58c,
-  0x2a8541c3, 0x2a6d8c55,
-  0x2a55d545, 0x2a3e1c93, 0x2a266240, 0x2a0ea64d, 0x29f6e8bb, 0x29df298b,
-  0x29c768be, 0x29afa654,
-  0x2997e24f, 0x29801caf, 0x29685576, 0x29508ca4, 0x2938c23a, 0x2920f63a,
-  0x290928a3, 0x28f15978,
-  0x28d988b8, 0x28c1b666, 0x28a9e281, 0x28920d0a, 0x287a3604, 0x28625d6d,
-  0x284a8349, 0x2832a796,
-  0x281aca57, 0x2802eb8c, 0x27eb0b36, 0x27d32956, 0x27bb45ed, 0x27a360fc,
-  0x278b7a84, 0x27739285,
-  0x275ba901, 0x2743bdf9, 0x272bd16d, 0x2713e35f, 0x26fbf3ce, 0x26e402bd,
-  0x26cc102d, 0x26b41c1d,
-  0x269c268f, 0x26842f84, 0x266c36fe, 0x26543cfb, 0x263c417f, 0x26244489,
-  0x260c461b, 0x25f44635,
-  0x25dc44d9, 0x25c44207, 0x25ac3dc0, 0x25943806, 0x257c30d8, 0x25642839,
-  0x254c1e28, 0x253412a8,
-  0x251c05b8, 0x2503f75a, 0x24ebe78f, 0x24d3d657, 0x24bbc3b4, 0x24a3afa6,
-  0x248b9a2f, 0x2473834f,
-  0x245b6b07, 0x24435158, 0x242b3644, 0x241319ca, 0x23fafbec, 0x23e2dcac,
-  0x23cabc09, 0x23b29a05,
-  0x239a76a0, 0x238251dd, 0x236a2bba, 0x2352043b, 0x2339db5e, 0x2321b126,
-  0x23098593, 0x22f158a7,
-  0x22d92a61, 0x22c0fac4, 0x22a8c9cf, 0x22909785, 0x227863e5, 0x22602ef1,
-  0x2247f8aa, 0x222fc111,
-  0x22178826, 0x21ff4dea, 0x21e71260, 0x21ced586, 0x21b6975f, 0x219e57eb,
-  0x2186172b, 0x216dd521,
-  0x215591cc, 0x213d4d2f, 0x21250749, 0x210cc01d, 0x20f477aa, 0x20dc2df2,
-  0x20c3e2f5, 0x20ab96b5,
-  0x20934933, 0x207afa6f, 0x2062aa6b, 0x204a5927, 0x203206a4, 0x2019b2e4,
-  0x20015de7, 0x1fe907ae,
-  0x1fd0b03a, 0x1fb8578b, 0x1f9ffda4, 0x1f87a285, 0x1f6f462f, 0x1f56e8a2,
-  0x1f3e89e0, 0x1f2629ea,
-  0x1f0dc8c0, 0x1ef56664, 0x1edd02d6, 0x1ec49e17, 0x1eac3829, 0x1e93d10c,
-  0x1e7b68c2, 0x1e62ff4a,
-  0x1e4a94a7, 0x1e3228d9, 0x1e19bbe0, 0x1e014dbf, 0x1de8de75, 0x1dd06e04,
-  0x1db7fc6d, 0x1d9f89b1,
-  0x1d8715d0, 0x1d6ea0cc, 0x1d562aa6, 0x1d3db35e, 0x1d253af5, 0x1d0cc16c,
-  0x1cf446c5, 0x1cdbcb00,
-  0x1cc34e1f, 0x1caad021, 0x1c925109, 0x1c79d0d6, 0x1c614f8b, 0x1c48cd27,
-  0x1c3049ac, 0x1c17c51b,
-  0x1bff3f75, 0x1be6b8ba, 0x1bce30ec, 0x1bb5a80c, 0x1b9d1e1a, 0x1b849317,
-  0x1b6c0705, 0x1b5379e5,
-  0x1b3aebb6, 0x1b225c7b, 0x1b09cc34, 0x1af13ae3, 0x1ad8a887, 0x1ac01522,
-  0x1aa780b6, 0x1a8eeb42,
-  0x1a7654c8, 0x1a5dbd49, 0x1a4524c6, 0x1a2c8b3f, 0x1a13f0b6, 0x19fb552c,
-  0x19e2b8a2, 0x19ca1b17,
-  0x19b17c8f, 0x1998dd09, 0x19803c86, 0x19679b07, 0x194ef88e, 0x1936551b,
-  0x191db0af, 0x19050b4b,
-  0x18ec64f0, 0x18d3bda0, 0x18bb155a, 0x18a26c20, 0x1889c1f3, 0x187116d4,
-  0x18586ac3, 0x183fbdc3,
-  0x18270fd3, 0x180e60f4, 0x17f5b129, 0x17dd0070, 0x17c44ecd, 0x17ab9c3e,
-  0x1792e8c6, 0x177a3466,
-  0x17617f1d, 0x1748c8ee, 0x173011d9, 0x171759df, 0x16fea102, 0x16e5e741,
-  0x16cd2c9f, 0x16b4711b,
-  0x169bb4b7, 0x1682f774, 0x166a3953, 0x16517a55, 0x1638ba7a, 0x161ff9c4,
-  0x16073834, 0x15ee75cb,
-  0x15d5b288, 0x15bcee6f, 0x15a4297f, 0x158b63b9, 0x15729d1f, 0x1559d5b1,
-  0x15410d70, 0x1528445d,
-  0x150f7a7a, 0x14f6afc7, 0x14dde445, 0x14c517f4, 0x14ac4ad7, 0x14937cee,
-  0x147aae3a, 0x1461debc,
-  0x14490e74, 0x14303d65, 0x14176b8e, 0x13fe98f1, 0x13e5c58e, 0x13ccf167,
-  0x13b41c7d, 0x139b46d0,
-  0x13827062, 0x13699933, 0x1350c144, 0x1337e897, 0x131f0f2c, 0x13063505,
-  0x12ed5a21, 0x12d47e83,
-  0x12bba22b, 0x12a2c51b, 0x1289e752, 0x127108d2, 0x1258299c, 0x123f49b2,
-  0x12266913, 0x120d87c1,
-  0x11f4a5bd, 0x11dbc307, 0x11c2dfa2, 0x11a9fb8d, 0x119116c9, 0x11783159,
-  0x115f4b3c, 0x11466473,
-  0x112d7d00, 0x111494e4, 0x10fbac1e, 0x10e2c2b2, 0x10c9d89e, 0x10b0ede5,
-  0x10980287, 0x107f1686,
-  0x106629e1, 0x104d3c9b, 0x10344eb4, 0x101b602d, 0x10027107, 0xfe98143,
-  0xfd090e1, 0xfb79fe4,
-  0xf9eae4c, 0xf85bc19, 0xf6cc94e, 0xf53d5ea, 0xf3ae1ee, 0xf21ed5d, 0xf08f836,
-  0xef0027b,
-  0xed70c2c, 0xebe154b, 0xea51dd8, 0xe8c25d5, 0xe732d42, 0xe5a3421, 0xe413a72,
-  0xe284036,
-  0xe0f456f, 0xdf64a1c, 0xddd4e40, 0xdc451dc, 0xdab54ef, 0xd92577b, 0xd795982,
-  0xd605b03,
-  0xd475c00, 0xd2e5c7b, 0xd155c73, 0xcfc5bea, 0xce35ae1, 0xcca5959, 0xcb15752,
-  0xc9854cf,
-  0xc7f51cf, 0xc664e53, 0xc4d4a5d, 0xc3445ee, 0xc1b4107, 0xc023ba7, 0xbe935d2,
-  0xbd02f87,
-  0xbb728c7, 0xb9e2193, 0xb8519ed, 0xb6c11d5, 0xb53094d, 0xb3a0055, 0xb20f6ee,
-  0xb07ed19,
-  0xaeee2d7, 0xad5d829, 0xabccd11, 0xaa3c18e, 0xa8ab5a2, 0xa71a94f, 0xa589c94,
-  0xa3f8f73,
-  0xa2681ed, 0xa0d7403, 0x9f465b5, 0x9db5706, 0x9c247f5, 0x9a93884, 0x99028b3,
-  0x9771884,
-  0x95e07f8, 0x944f70f, 0x92be5ca, 0x912d42c, 0x8f9c233, 0x8e0afe2, 0x8c79d3a,
-  0x8ae8a3a,
-  0x89576e5, 0x87c633c, 0x8634f3e, 0x84a3aee, 0x831264c, 0x8181159, 0x7fefc16,
-  0x7e5e685,
-  0x7ccd0a5, 0x7b3ba78, 0x79aa400, 0x7818d3c, 0x768762e, 0x74f5ed7, 0x7364738,
-  0x71d2f52,
-  0x7041726, 0x6eafeb4, 0x6d1e5fe, 0x6b8cd05, 0x69fb3c9, 0x6869a4c, 0x66d808f,
-  0x6546692,
-  0x63b4c57, 0x62231de, 0x6091729, 0x5effc38, 0x5d6e10c, 0x5bdc5a7, 0x5a4aa09,
-  0x58b8e34,
-  0x5727228, 0x55955e6, 0x540396f, 0x5271cc4, 0x50dffe7, 0x4f4e2d8, 0x4dbc597,
-  0x4c2a827,
-  0x4a98a88, 0x4906cbb, 0x4774ec1, 0x45e309a, 0x4451249, 0x42bf3cd, 0x412d528,
-  0x3f9b65b,
-  0x3e09767, 0x3c7784d, 0x3ae590d, 0x39539a9, 0x37c1a22, 0x362fa78, 0x349daac,
-  0x330bac1,
-  0x3179ab5, 0x2fe7a8c, 0x2e55a44, 0x2cc39e1, 0x2b31961, 0x299f8c7, 0x280d813,
-  0x267b747,
-  0x24e9662, 0x2357567, 0x21c5457, 0x2033331, 0x1ea11f7, 0x1d0f0ab, 0x1b7cf4d,
-  0x19eaddd,
-  0x1858c5e, 0x16c6ad0, 0x1534934, 0x13a278a, 0x12105d5, 0x107e414, 0xeec249,
-  0xd5a075,
-  0xbc7e99, 0xa35cb5, 0x8a3acb, 0x7118dc, 0x57f6e9, 0x3ed4f2, 0x25b2f8,
-  0xc90fe,
-
-};
-
-static const q31_t cos_factorsQ31_8192[8192] = {
-  0x7ffffff6, 0x7fffffa7, 0x7fffff09, 0x7ffffe1c, 0x7ffffce1, 0x7ffffb56,
-    0x7ffff97c, 0x7ffff753,
-  0x7ffff4dc, 0x7ffff215, 0x7fffef00, 0x7fffeb9b, 0x7fffe7e8, 0x7fffe3e5,
-    0x7fffdf94, 0x7fffdaf3,
-  0x7fffd604, 0x7fffd0c6, 0x7fffcb39, 0x7fffc55c, 0x7fffbf31, 0x7fffb8b7,
-    0x7fffb1ee, 0x7fffaad6,
-  0x7fffa36f, 0x7fff9bb9, 0x7fff93b4, 0x7fff8b61, 0x7fff82be, 0x7fff79cc,
-    0x7fff708b, 0x7fff66fc,
-  0x7fff5d1d, 0x7fff52ef, 0x7fff4873, 0x7fff3da8, 0x7fff328d, 0x7fff2724,
-    0x7fff1b6b, 0x7fff0f64,
-  0x7fff030e, 0x7ffef669, 0x7ffee975, 0x7ffedc31, 0x7ffece9f, 0x7ffec0be,
-    0x7ffeb28e, 0x7ffea40f,
-  0x7ffe9542, 0x7ffe8625, 0x7ffe76b9, 0x7ffe66fe, 0x7ffe56f5, 0x7ffe469c,
-    0x7ffe35f4, 0x7ffe24fe,
-  0x7ffe13b8, 0x7ffe0224, 0x7ffdf040, 0x7ffdde0e, 0x7ffdcb8d, 0x7ffdb8bc,
-    0x7ffda59d, 0x7ffd922f,
-  0x7ffd7e72, 0x7ffd6a66, 0x7ffd560b, 0x7ffd4161, 0x7ffd2c68, 0x7ffd1720,
-    0x7ffd0189, 0x7ffceba4,
-  0x7ffcd56f, 0x7ffcbeeb, 0x7ffca819, 0x7ffc90f7, 0x7ffc7987, 0x7ffc61c7,
-    0x7ffc49b9, 0x7ffc315b,
-  0x7ffc18af, 0x7ffbffb4, 0x7ffbe66a, 0x7ffbccd0, 0x7ffbb2e8, 0x7ffb98b1,
-    0x7ffb7e2b, 0x7ffb6356,
-  0x7ffb4833, 0x7ffb2cc0, 0x7ffb10fe, 0x7ffaf4ed, 0x7ffad88e, 0x7ffabbdf,
-    0x7ffa9ee2, 0x7ffa8195,
-  0x7ffa63fa, 0x7ffa460f, 0x7ffa27d6, 0x7ffa094e, 0x7ff9ea76, 0x7ff9cb50,
-    0x7ff9abdb, 0x7ff98c17,
-  0x7ff96c04, 0x7ff94ba2, 0x7ff92af1, 0x7ff909f2, 0x7ff8e8a3, 0x7ff8c705,
-    0x7ff8a519, 0x7ff882dd,
-  0x7ff86053, 0x7ff83d79, 0x7ff81a51, 0x7ff7f6da, 0x7ff7d313, 0x7ff7aefe,
-    0x7ff78a9a, 0x7ff765e7,
-  0x7ff740e5, 0x7ff71b94, 0x7ff6f5f4, 0x7ff6d005, 0x7ff6a9c8, 0x7ff6833b,
-    0x7ff65c5f, 0x7ff63535,
-  0x7ff60dbb, 0x7ff5e5f3, 0x7ff5bddc, 0x7ff59576, 0x7ff56cc0, 0x7ff543bc,
-    0x7ff51a69, 0x7ff4f0c7,
-  0x7ff4c6d6, 0x7ff49c96, 0x7ff47208, 0x7ff4472a, 0x7ff41bfd, 0x7ff3f082,
-    0x7ff3c4b7, 0x7ff3989e,
-  0x7ff36c36, 0x7ff33f7e, 0x7ff31278, 0x7ff2e523, 0x7ff2b77f, 0x7ff2898c,
-    0x7ff25b4a, 0x7ff22cb9,
-  0x7ff1fdd9, 0x7ff1ceab, 0x7ff19f2d, 0x7ff16f61, 0x7ff13f45, 0x7ff10edb,
-    0x7ff0de22, 0x7ff0ad19,
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-    0x7fef4d3e, 0x7fef19bf,
-  0x7feee5f0, 0x7feeb1d3, 0x7fee7d67, 0x7fee48ac, 0x7fee13a1, 0x7fedde48,
-    0x7feda8a0, 0x7fed72aa,
-  0x7fed3c64, 0x7fed05cf, 0x7fecceec, 0x7fec97b9, 0x7fec6038, 0x7fec2867,
-    0x7febf048, 0x7febb7da,
-  0x7feb7f1d, 0x7feb4611, 0x7feb0cb6, 0x7fead30c, 0x7fea9914, 0x7fea5ecc,
-    0x7fea2436, 0x7fe9e950,
-  0x7fe9ae1c, 0x7fe97299, 0x7fe936c7, 0x7fe8faa6, 0x7fe8be36, 0x7fe88177,
-    0x7fe84469, 0x7fe8070d,
-  0x7fe7c961, 0x7fe78b67, 0x7fe74d1e, 0x7fe70e85, 0x7fe6cf9e, 0x7fe69068,
-    0x7fe650e3, 0x7fe61110,
-  0x7fe5d0ed, 0x7fe5907b, 0x7fe54fbb, 0x7fe50eac, 0x7fe4cd4d, 0x7fe48ba0,
-    0x7fe449a4, 0x7fe40759,
-  0x7fe3c4bf, 0x7fe381d7, 0x7fe33e9f, 0x7fe2fb19, 0x7fe2b743, 0x7fe2731f,
-    0x7fe22eac, 0x7fe1e9ea,
-  0x7fe1a4d9, 0x7fe15f79, 0x7fe119cb, 0x7fe0d3cd, 0x7fe08d81, 0x7fe046e5,
-    0x7fdffffb, 0x7fdfb8c2,
-  0x7fdf713a, 0x7fdf2963, 0x7fdee13e, 0x7fde98c9, 0x7fde5006, 0x7fde06f3,
-    0x7fddbd92, 0x7fdd73e2,
-  0x7fdd29e3, 0x7fdcdf95, 0x7fdc94f9, 0x7fdc4a0d, 0x7fdbfed3, 0x7fdbb349,
-    0x7fdb6771, 0x7fdb1b4a,
-  0x7fdaced4, 0x7fda820f, 0x7fda34fc, 0x7fd9e799, 0x7fd999e8, 0x7fd94be8,
-    0x7fd8fd98, 0x7fd8aefa,
-  0x7fd8600e, 0x7fd810d2, 0x7fd7c147, 0x7fd7716e, 0x7fd72146, 0x7fd6d0cf,
-    0x7fd68009, 0x7fd62ef4,
-  0x7fd5dd90, 0x7fd58bdd, 0x7fd539dc, 0x7fd4e78c, 0x7fd494ed, 0x7fd441ff,
-    0x7fd3eec2, 0x7fd39b36,
-  0x7fd3475c, 0x7fd2f332, 0x7fd29eba, 0x7fd249f3, 0x7fd1f4dd, 0x7fd19f78,
-    0x7fd149c5, 0x7fd0f3c2,
-  0x7fd09d71, 0x7fd046d1, 0x7fcfefe2, 0x7fcf98a4, 0x7fcf4117, 0x7fcee93c,
-    0x7fce9112, 0x7fce3898,
-  0x7fcddfd0, 0x7fcd86b9, 0x7fcd2d54, 0x7fccd39f, 0x7fcc799c, 0x7fcc1f4a,
-    0x7fcbc4a9, 0x7fcb69b9,
-  0x7fcb0e7a, 0x7fcab2ed, 0x7fca5710, 0x7fc9fae5, 0x7fc99e6b, 0x7fc941a2,
-    0x7fc8e48b, 0x7fc88724,
-  0x7fc8296f, 0x7fc7cb6b, 0x7fc76d18, 0x7fc70e76, 0x7fc6af86, 0x7fc65046,
-    0x7fc5f0b8, 0x7fc590db,
-  0x7fc530af, 0x7fc4d035, 0x7fc46f6b, 0x7fc40e53, 0x7fc3acec, 0x7fc34b36,
-    0x7fc2e931, 0x7fc286de,
-  0x7fc2243b, 0x7fc1c14a, 0x7fc15e0a, 0x7fc0fa7b, 0x7fc0969e, 0x7fc03271,
-    0x7fbfcdf6, 0x7fbf692c,
-  0x7fbf0414, 0x7fbe9eac, 0x7fbe38f6, 0x7fbdd2f0, 0x7fbd6c9c, 0x7fbd05fa,
-    0x7fbc9f08, 0x7fbc37c8,
-  0x7fbbd039, 0x7fbb685b, 0x7fbb002e, 0x7fba97b2, 0x7fba2ee8, 0x7fb9c5cf,
-    0x7fb95c67, 0x7fb8f2b0,
-  0x7fb888ab, 0x7fb81e57, 0x7fb7b3b4, 0x7fb748c2, 0x7fb6dd81, 0x7fb671f2,
-    0x7fb60614, 0x7fb599e7,
-  0x7fb52d6b, 0x7fb4c0a1, 0x7fb45387, 0x7fb3e61f, 0x7fb37869, 0x7fb30a63,
-    0x7fb29c0f, 0x7fb22d6c,
-  0x7fb1be7a, 0x7fb14f39, 0x7fb0dfaa, 0x7fb06fcb, 0x7fafff9e, 0x7faf8f23,
-    0x7faf1e58, 0x7faead3f,
-  0x7fae3bd7, 0x7fadca20, 0x7fad581b, 0x7face5c6, 0x7fac7323, 0x7fac0031,
-    0x7fab8cf1, 0x7fab1962,
-  0x7faaa584, 0x7faa3157, 0x7fa9bcdb, 0x7fa94811, 0x7fa8d2f8, 0x7fa85d90,
-    0x7fa7e7d9, 0x7fa771d4,
-  0x7fa6fb80, 0x7fa684dd, 0x7fa60dec, 0x7fa596ac, 0x7fa51f1d, 0x7fa4a73f,
-    0x7fa42f12, 0x7fa3b697,
-  0x7fa33dcd, 0x7fa2c4b5, 0x7fa24b4d, 0x7fa1d197, 0x7fa15792, 0x7fa0dd3f,
-    0x7fa0629c, 0x7f9fe7ab,
-  0x7f9f6c6b, 0x7f9ef0dd, 0x7f9e7500, 0x7f9df8d4, 0x7f9d7c59, 0x7f9cff90,
-    0x7f9c8278, 0x7f9c0511,
-  0x7f9b875b, 0x7f9b0957, 0x7f9a8b04, 0x7f9a0c62, 0x7f998d72, 0x7f990e33,
-    0x7f988ea5, 0x7f980ec8,
-  0x7f978e9d, 0x7f970e23, 0x7f968d5b, 0x7f960c43, 0x7f958add, 0x7f950929,
-    0x7f948725, 0x7f9404d3,
-  0x7f938232, 0x7f92ff43, 0x7f927c04, 0x7f91f878, 0x7f91749c, 0x7f90f072,
-    0x7f906bf9, 0x7f8fe731,
-  0x7f8f621b, 0x7f8edcb6, 0x7f8e5702, 0x7f8dd0ff, 0x7f8d4aae, 0x7f8cc40f,
-    0x7f8c3d20, 0x7f8bb5e3,
-  0x7f8b2e57, 0x7f8aa67d, 0x7f8a1e54, 0x7f8995dc, 0x7f890d15, 0x7f888400,
-    0x7f87fa9c, 0x7f8770ea,
-  0x7f86e6e9, 0x7f865c99, 0x7f85d1fa, 0x7f85470d, 0x7f84bbd1, 0x7f843047,
-    0x7f83a46e, 0x7f831846,
-  0x7f828bcf, 0x7f81ff0a, 0x7f8171f6, 0x7f80e494, 0x7f8056e3, 0x7f7fc8e3,
-    0x7f7f3a95, 0x7f7eabf8,
-  0x7f7e1d0c, 0x7f7d8dd2, 0x7f7cfe49, 0x7f7c6e71, 0x7f7bde4b, 0x7f7b4dd6,
-    0x7f7abd13, 0x7f7a2c01,
-  0x7f799aa0, 0x7f7908f0, 0x7f7876f2, 0x7f77e4a6, 0x7f77520a, 0x7f76bf21,
-    0x7f762be8, 0x7f759861,
-  0x7f75048b, 0x7f747067, 0x7f73dbf4, 0x7f734732, 0x7f72b222, 0x7f721cc3,
-    0x7f718715, 0x7f70f119,
-  0x7f705ace, 0x7f6fc435, 0x7f6f2d4d, 0x7f6e9617, 0x7f6dfe91, 0x7f6d66be,
-    0x7f6cce9b, 0x7f6c362a,
-  0x7f6b9d6b, 0x7f6b045d, 0x7f6a6b00, 0x7f69d154, 0x7f69375a, 0x7f689d12,
-    0x7f68027b, 0x7f676795,
-  0x7f66cc61, 0x7f6630de, 0x7f65950c, 0x7f64f8ec, 0x7f645c7d, 0x7f63bfc0,
-    0x7f6322b4, 0x7f62855a,
-  0x7f61e7b1, 0x7f6149b9, 0x7f60ab73, 0x7f600cdf, 0x7f5f6dfb, 0x7f5ecec9,
-    0x7f5e2f49, 0x7f5d8f7a,
-  0x7f5cef5c, 0x7f5c4ef0, 0x7f5bae36, 0x7f5b0d2c, 0x7f5a6bd5, 0x7f59ca2e,
-    0x7f592839, 0x7f5885f6,
-  0x7f57e364, 0x7f574083, 0x7f569d54, 0x7f55f9d6, 0x7f55560a, 0x7f54b1ef,
-    0x7f540d86, 0x7f5368ce,
-  0x7f52c3c8, 0x7f521e73, 0x7f5178cf, 0x7f50d2dd, 0x7f502c9d, 0x7f4f860e,
-    0x7f4edf30, 0x7f4e3804,
-  0x7f4d9089, 0x7f4ce8c0, 0x7f4c40a8, 0x7f4b9842, 0x7f4aef8d, 0x7f4a468a,
-    0x7f499d38, 0x7f48f398,
-  0x7f4849a9, 0x7f479f6c, 0x7f46f4e0, 0x7f464a06, 0x7f459edd, 0x7f44f365,
-    0x7f44479f, 0x7f439b8b,
-  0x7f42ef28, 0x7f424277, 0x7f419577, 0x7f40e828, 0x7f403a8b, 0x7f3f8ca0,
-    0x7f3ede66, 0x7f3e2fde,
-  0x7f3d8107, 0x7f3cd1e2, 0x7f3c226e, 0x7f3b72ab, 0x7f3ac29b, 0x7f3a123b,
-    0x7f39618e, 0x7f38b091,
-  0x7f37ff47, 0x7f374dad, 0x7f369bc6, 0x7f35e990, 0x7f35370b, 0x7f348438,
-    0x7f33d116, 0x7f331da6,
-  0x7f3269e8, 0x7f31b5db, 0x7f31017f, 0x7f304cd6, 0x7f2f97dd, 0x7f2ee296,
-    0x7f2e2d01, 0x7f2d771e,
-  0x7f2cc0eb, 0x7f2c0a6b, 0x7f2b539c, 0x7f2a9c7e, 0x7f29e512, 0x7f292d58,
-    0x7f28754f, 0x7f27bcf8,
-  0x7f270452, 0x7f264b5e, 0x7f25921c, 0x7f24d88b, 0x7f241eab, 0x7f23647e,
-    0x7f22aa01, 0x7f21ef37,
-  0x7f21341e, 0x7f2078b6, 0x7f1fbd00, 0x7f1f00fc, 0x7f1e44a9, 0x7f1d8808,
-    0x7f1ccb18, 0x7f1c0dda,
-  0x7f1b504e, 0x7f1a9273, 0x7f19d44a, 0x7f1915d2, 0x7f18570c, 0x7f1797f8,
-    0x7f16d895, 0x7f1618e4,
-  0x7f1558e4, 0x7f149896, 0x7f13d7fa, 0x7f13170f, 0x7f1255d6, 0x7f11944f,
-    0x7f10d279, 0x7f101054,
-  0x7f0f4de2, 0x7f0e8b21, 0x7f0dc811, 0x7f0d04b3, 0x7f0c4107, 0x7f0b7d0d,
-    0x7f0ab8c4, 0x7f09f42d,
-  0x7f092f47, 0x7f086a13, 0x7f07a491, 0x7f06dec0, 0x7f0618a1, 0x7f055233,
-    0x7f048b78, 0x7f03c46d,
-  0x7f02fd15, 0x7f02356e, 0x7f016d79, 0x7f00a535, 0x7effdca4, 0x7eff13c3,
-    0x7efe4a95, 0x7efd8118,
-  0x7efcb74d, 0x7efbed33, 0x7efb22cb, 0x7efa5815, 0x7ef98d11, 0x7ef8c1be,
-    0x7ef7f61d, 0x7ef72a2d,
-  0x7ef65def, 0x7ef59163, 0x7ef4c489, 0x7ef3f760, 0x7ef329e9, 0x7ef25c24,
-    0x7ef18e10, 0x7ef0bfae,
-  0x7eeff0fe, 0x7eef21ff, 0x7eee52b2, 0x7eed8317, 0x7eecb32d, 0x7eebe2f6,
-    0x7eeb1270, 0x7eea419b,
-  0x7ee97079, 0x7ee89f08, 0x7ee7cd49, 0x7ee6fb3b, 0x7ee628df, 0x7ee55635,
-    0x7ee4833d, 0x7ee3aff6,
-  0x7ee2dc61, 0x7ee2087e, 0x7ee1344d, 0x7ee05fcd, 0x7edf8aff, 0x7edeb5e3,
-    0x7edde079, 0x7edd0ac0,
-  0x7edc34b9, 0x7edb5e64, 0x7eda87c0, 0x7ed9b0ce, 0x7ed8d98e, 0x7ed80200,
-    0x7ed72a24, 0x7ed651f9,
-  0x7ed57980, 0x7ed4a0b9, 0x7ed3c7a3, 0x7ed2ee40, 0x7ed2148e, 0x7ed13a8e,
-    0x7ed0603f, 0x7ecf85a3,
-  0x7eceaab8, 0x7ecdcf7f, 0x7eccf3f8, 0x7ecc1822, 0x7ecb3bff, 0x7eca5f8d,
-    0x7ec982cd, 0x7ec8a5bf,
-  0x7ec7c862, 0x7ec6eab7, 0x7ec60cbe, 0x7ec52e77, 0x7ec44fe2, 0x7ec370fe,
-    0x7ec291cd, 0x7ec1b24d,
-  0x7ec0d27f, 0x7ebff263, 0x7ebf11f8, 0x7ebe313f, 0x7ebd5039, 0x7ebc6ee4,
-    0x7ebb8d40, 0x7ebaab4f,
-  0x7eb9c910, 0x7eb8e682, 0x7eb803a6, 0x7eb7207c, 0x7eb63d04, 0x7eb5593d,
-    0x7eb47529, 0x7eb390c6,
-  0x7eb2ac15, 0x7eb1c716, 0x7eb0e1c9, 0x7eaffc2e, 0x7eaf1645, 0x7eae300d,
-    0x7ead4987, 0x7eac62b3,
-  0x7eab7b91, 0x7eaa9421, 0x7ea9ac63, 0x7ea8c457, 0x7ea7dbfc, 0x7ea6f353,
-    0x7ea60a5d, 0x7ea52118,
-  0x7ea43785, 0x7ea34da4, 0x7ea26374, 0x7ea178f7, 0x7ea08e2b, 0x7e9fa312,
-    0x7e9eb7aa, 0x7e9dcbf4,
-  0x7e9cdff0, 0x7e9bf39e, 0x7e9b06fe, 0x7e9a1a10, 0x7e992cd4, 0x7e983f49,
-    0x7e975171, 0x7e96634a,
-  0x7e9574d6, 0x7e948613, 0x7e939702, 0x7e92a7a3, 0x7e91b7f6, 0x7e90c7fb,
-    0x7e8fd7b2, 0x7e8ee71b,
-  0x7e8df636, 0x7e8d0502, 0x7e8c1381, 0x7e8b21b1, 0x7e8a2f94, 0x7e893d28,
-    0x7e884a6f, 0x7e875767,
-  0x7e866411, 0x7e85706d, 0x7e847c7c, 0x7e83883c, 0x7e8293ae, 0x7e819ed2,
-    0x7e80a9a8, 0x7e7fb430,
-  0x7e7ebe6a, 0x7e7dc856, 0x7e7cd1f4, 0x7e7bdb44, 0x7e7ae446, 0x7e79ecf9,
-    0x7e78f55f, 0x7e77fd77,
-  0x7e770541, 0x7e760cbd, 0x7e7513ea, 0x7e741aca, 0x7e73215c, 0x7e7227a0,
-    0x7e712d96, 0x7e70333d,
-  0x7e6f3897, 0x7e6e3da3, 0x7e6d4261, 0x7e6c46d1, 0x7e6b4af2, 0x7e6a4ec6,
-    0x7e69524c, 0x7e685584,
-  0x7e67586e, 0x7e665b0a, 0x7e655d58, 0x7e645f58, 0x7e63610a, 0x7e62626e,
-    0x7e616384, 0x7e60644c,
-  0x7e5f64c7, 0x7e5e64f3, 0x7e5d64d1, 0x7e5c6461, 0x7e5b63a4, 0x7e5a6298,
-    0x7e59613f, 0x7e585f97,
-  0x7e575da2, 0x7e565b5f, 0x7e5558ce, 0x7e5455ef, 0x7e5352c1, 0x7e524f46,
-    0x7e514b7e, 0x7e504767,
-  0x7e4f4302, 0x7e4e3e4f, 0x7e4d394f, 0x7e4c3400, 0x7e4b2e64, 0x7e4a287a,
-    0x7e492241, 0x7e481bbb,
-  0x7e4714e7, 0x7e460dc5, 0x7e450656, 0x7e43fe98, 0x7e42f68c, 0x7e41ee33,
-    0x7e40e58c, 0x7e3fdc97,
-  0x7e3ed353, 0x7e3dc9c3, 0x7e3cbfe4, 0x7e3bb5b7, 0x7e3aab3c, 0x7e39a074,
-    0x7e38955e, 0x7e3789fa,
-  0x7e367e48, 0x7e357248, 0x7e3465fa, 0x7e33595e, 0x7e324c75, 0x7e313f3e,
-    0x7e3031b9, 0x7e2f23e6,
-  0x7e2e15c5, 0x7e2d0756, 0x7e2bf89a, 0x7e2ae990, 0x7e29da38, 0x7e28ca92,
-    0x7e27ba9e, 0x7e26aa5d,
-  0x7e2599cd, 0x7e2488f0, 0x7e2377c5, 0x7e22664c, 0x7e215486, 0x7e204271,
-    0x7e1f300f, 0x7e1e1d5f,
-  0x7e1d0a61, 0x7e1bf716, 0x7e1ae37c, 0x7e19cf95, 0x7e18bb60, 0x7e17a6dd,
-    0x7e16920d, 0x7e157cee,
-  0x7e146782, 0x7e1351c9, 0x7e123bc1, 0x7e11256c, 0x7e100ec8, 0x7e0ef7d7,
-    0x7e0de099, 0x7e0cc90c,
-  0x7e0bb132, 0x7e0a990a, 0x7e098095, 0x7e0867d1, 0x7e074ec0, 0x7e063561,
-    0x7e051bb4, 0x7e0401ba,
-  0x7e02e772, 0x7e01ccdc, 0x7e00b1f9, 0x7dff96c7, 0x7dfe7b48, 0x7dfd5f7b,
-    0x7dfc4361, 0x7dfb26f9,
-  0x7dfa0a43, 0x7df8ed3f, 0x7df7cfee, 0x7df6b24f, 0x7df59462, 0x7df47628,
-    0x7df357a0, 0x7df238ca,
-  0x7df119a7, 0x7deffa35, 0x7deeda77, 0x7dedba6a, 0x7dec9a10, 0x7deb7968,
-    0x7dea5872, 0x7de9372f,
-  0x7de8159e, 0x7de6f3c0, 0x7de5d193, 0x7de4af1a, 0x7de38c52, 0x7de2693d,
-    0x7de145da, 0x7de02229,
-  0x7ddefe2b, 0x7dddd9e0, 0x7ddcb546, 0x7ddb905f, 0x7dda6b2a, 0x7dd945a8,
-    0x7dd81fd8, 0x7dd6f9ba,
-  0x7dd5d34f, 0x7dd4ac96, 0x7dd38590, 0x7dd25e3c, 0x7dd1369a, 0x7dd00eab,
-    0x7dcee66e, 0x7dcdbde3,
-  0x7dcc950b, 0x7dcb6be6, 0x7dca4272, 0x7dc918b1, 0x7dc7eea3, 0x7dc6c447,
-    0x7dc5999d, 0x7dc46ea6,
-  0x7dc34361, 0x7dc217cf, 0x7dc0ebef, 0x7dbfbfc1, 0x7dbe9346, 0x7dbd667d,
-    0x7dbc3967, 0x7dbb0c03,
-  0x7db9de52, 0x7db8b053, 0x7db78207, 0x7db6536d, 0x7db52485, 0x7db3f550,
-    0x7db2c5cd, 0x7db195fd,
-  0x7db065df, 0x7daf3574, 0x7dae04bb, 0x7dacd3b5, 0x7daba261, 0x7daa70c0,
-    0x7da93ed1, 0x7da80c95,
-  0x7da6da0b, 0x7da5a733, 0x7da4740e, 0x7da3409c, 0x7da20cdc, 0x7da0d8cf,
-    0x7d9fa474, 0x7d9e6fcb,
-  0x7d9d3ad6, 0x7d9c0592, 0x7d9ad001, 0x7d999a23, 0x7d9863f7, 0x7d972d7e,
-    0x7d95f6b7, 0x7d94bfa3,
-  0x7d938841, 0x7d925092, 0x7d911896, 0x7d8fe04c, 0x7d8ea7b4, 0x7d8d6ecf,
-    0x7d8c359d, 0x7d8afc1d,
-  0x7d89c250, 0x7d888835, 0x7d874dcd, 0x7d861317, 0x7d84d814, 0x7d839cc4,
-    0x7d826126, 0x7d81253a,
-  0x7d7fe902, 0x7d7eac7c, 0x7d7d6fa8, 0x7d7c3287, 0x7d7af519, 0x7d79b75d,
-    0x7d787954, 0x7d773afd,
-  0x7d75fc59, 0x7d74bd68, 0x7d737e29, 0x7d723e9d, 0x7d70fec4, 0x7d6fbe9d,
-    0x7d6e7e29, 0x7d6d3d67,
-  0x7d6bfc58, 0x7d6abafc, 0x7d697952, 0x7d68375b, 0x7d66f517, 0x7d65b285,
-    0x7d646fa6, 0x7d632c79,
-  0x7d61e8ff, 0x7d60a538, 0x7d5f6124, 0x7d5e1cc2, 0x7d5cd813, 0x7d5b9316,
-    0x7d5a4dcc, 0x7d590835,
-  0x7d57c251, 0x7d567c1f, 0x7d5535a0, 0x7d53eed3, 0x7d52a7ba, 0x7d516053,
-    0x7d50189e, 0x7d4ed09d,
-  0x7d4d884e, 0x7d4c3fb1, 0x7d4af6c8, 0x7d49ad91, 0x7d48640d, 0x7d471a3c,
-    0x7d45d01d, 0x7d4485b1,
-  0x7d433af8, 0x7d41eff1, 0x7d40a49e, 0x7d3f58fd, 0x7d3e0d0e, 0x7d3cc0d3,
-    0x7d3b744a, 0x7d3a2774,
-  0x7d38da51, 0x7d378ce0, 0x7d363f23, 0x7d34f118, 0x7d33a2bf, 0x7d32541a,
-    0x7d310527, 0x7d2fb5e7,
-  0x7d2e665a, 0x7d2d1680, 0x7d2bc659, 0x7d2a75e4, 0x7d292522, 0x7d27d413,
-    0x7d2682b6, 0x7d25310d,
-  0x7d23df16, 0x7d228cd2, 0x7d213a41, 0x7d1fe762, 0x7d1e9437, 0x7d1d40be,
-    0x7d1becf8, 0x7d1a98e5,
-  0x7d194485, 0x7d17efd8, 0x7d169add, 0x7d154595, 0x7d13f001, 0x7d129a1f,
-    0x7d1143ef, 0x7d0fed73,
-  0x7d0e96aa, 0x7d0d3f93, 0x7d0be82f, 0x7d0a907e, 0x7d093880, 0x7d07e035,
-    0x7d06879d, 0x7d052eb8,
-  0x7d03d585, 0x7d027c05, 0x7d012239, 0x7cffc81f, 0x7cfe6db8, 0x7cfd1304,
-    0x7cfbb803, 0x7cfa5cb4,
-  0x7cf90119, 0x7cf7a531, 0x7cf648fb, 0x7cf4ec79, 0x7cf38fa9, 0x7cf2328c,
-    0x7cf0d522, 0x7cef776b,
-  0x7cee1967, 0x7cecbb16, 0x7ceb5c78, 0x7ce9fd8d, 0x7ce89e55, 0x7ce73ed0,
-    0x7ce5defd, 0x7ce47ede,
-  0x7ce31e72, 0x7ce1bdb8, 0x7ce05cb2, 0x7cdefb5e, 0x7cdd99be, 0x7cdc37d0,
-    0x7cdad596, 0x7cd9730e,
-  0x7cd8103a, 0x7cd6ad18, 0x7cd549aa, 0x7cd3e5ee, 0x7cd281e5, 0x7cd11d90,
-    0x7ccfb8ed, 0x7cce53fe,
-  0x7ccceec1, 0x7ccb8937, 0x7cca2361, 0x7cc8bd3d, 0x7cc756cd, 0x7cc5f010,
-    0x7cc48905, 0x7cc321ae,
-  0x7cc1ba09, 0x7cc05218, 0x7cbee9da, 0x7cbd814f, 0x7cbc1877, 0x7cbaaf51,
-    0x7cb945df, 0x7cb7dc20,
-  0x7cb67215, 0x7cb507bc, 0x7cb39d16, 0x7cb23223, 0x7cb0c6e4, 0x7caf5b57,
-    0x7cadef7e, 0x7cac8358,
-  0x7cab16e4, 0x7ca9aa24, 0x7ca83d17, 0x7ca6cfbd, 0x7ca56216, 0x7ca3f423,
-    0x7ca285e2, 0x7ca11755,
-  0x7c9fa87a, 0x7c9e3953, 0x7c9cc9df, 0x7c9b5a1e, 0x7c99ea10, 0x7c9879b6,
-    0x7c97090e, 0x7c95981a,
-  0x7c9426d8, 0x7c92b54a, 0x7c91436f, 0x7c8fd148, 0x7c8e5ed3, 0x7c8cec12,
-    0x7c8b7903, 0x7c8a05a8,
-  0x7c889200, 0x7c871e0c, 0x7c85a9ca, 0x7c84353c, 0x7c82c060, 0x7c814b39,
-    0x7c7fd5c4, 0x7c7e6002,
-  0x7c7ce9f4, 0x7c7b7399, 0x7c79fcf1, 0x7c7885fc, 0x7c770eba, 0x7c75972c,
-    0x7c741f51, 0x7c72a729,
-  0x7c712eb5, 0x7c6fb5f3, 0x7c6e3ce5, 0x7c6cc38a, 0x7c6b49e3, 0x7c69cfee,
-    0x7c6855ad, 0x7c66db1f,
-  0x7c656045, 0x7c63e51e, 0x7c6269aa, 0x7c60ede9, 0x7c5f71db, 0x7c5df581,
-    0x7c5c78da, 0x7c5afbe6,
-  0x7c597ea6, 0x7c580119, 0x7c56833f, 0x7c550519, 0x7c5386a6, 0x7c5207e6,
-    0x7c5088d9, 0x7c4f0980,
-  0x7c4d89da, 0x7c4c09e8, 0x7c4a89a8, 0x7c49091c, 0x7c478844, 0x7c46071f,
-    0x7c4485ad, 0x7c4303ee,
-  0x7c4181e3, 0x7c3fff8b, 0x7c3e7ce7, 0x7c3cf9f5, 0x7c3b76b8, 0x7c39f32d,
-    0x7c386f56, 0x7c36eb33,
-  0x7c3566c2, 0x7c33e205, 0x7c325cfc, 0x7c30d7a6, 0x7c2f5203, 0x7c2dcc14,
-    0x7c2c45d8, 0x7c2abf4f,
-  0x7c29387a, 0x7c27b158, 0x7c2629ea, 0x7c24a22f, 0x7c231a28, 0x7c2191d4,
-    0x7c200933, 0x7c1e8046,
-  0x7c1cf70c, 0x7c1b6d86, 0x7c19e3b3, 0x7c185994, 0x7c16cf28, 0x7c15446f,
-    0x7c13b96a, 0x7c122e19,
-  0x7c10a27b, 0x7c0f1690, 0x7c0d8a59, 0x7c0bfdd5, 0x7c0a7105, 0x7c08e3e8,
-    0x7c07567f, 0x7c05c8c9,
-  0x7c043ac7, 0x7c02ac78, 0x7c011ddd, 0x7bff8ef5, 0x7bfdffc1, 0x7bfc7041,
-    0x7bfae073, 0x7bf9505a,
-  0x7bf7bff4, 0x7bf62f41, 0x7bf49e42, 0x7bf30cf6, 0x7bf17b5e, 0x7befe97a,
-    0x7bee5749, 0x7becc4cc,
-  0x7beb3202, 0x7be99eec, 0x7be80b89, 0x7be677da, 0x7be4e3df, 0x7be34f97,
-    0x7be1bb02, 0x7be02621,
-  0x7bde90f4, 0x7bdcfb7b, 0x7bdb65b5, 0x7bd9cfa2, 0x7bd83944, 0x7bd6a298,
-    0x7bd50ba1, 0x7bd3745d,
-  0x7bd1dccc, 0x7bd044f0, 0x7bceacc7, 0x7bcd1451, 0x7bcb7b8f, 0x7bc9e281,
-    0x7bc84927, 0x7bc6af80,
-  0x7bc5158c, 0x7bc37b4d, 0x7bc1e0c1, 0x7bc045e9, 0x7bbeaac4, 0x7bbd0f53,
-    0x7bbb7396, 0x7bb9d78c,
-  0x7bb83b36, 0x7bb69e94, 0x7bb501a5, 0x7bb3646a, 0x7bb1c6e3, 0x7bb02910,
-    0x7bae8af0, 0x7bacec84,
-  0x7bab4dcc, 0x7ba9aec7, 0x7ba80f76, 0x7ba66fd9, 0x7ba4cfef, 0x7ba32fba,
-    0x7ba18f38, 0x7b9fee69,
-  0x7b9e4d4f, 0x7b9cabe8, 0x7b9b0a35, 0x7b996836, 0x7b97c5ea, 0x7b962352,
-    0x7b94806e, 0x7b92dd3e,
-  0x7b9139c2, 0x7b8f95f9, 0x7b8df1e4, 0x7b8c4d83, 0x7b8aa8d6, 0x7b8903dc,
-    0x7b875e96, 0x7b85b904,
-  0x7b841326, 0x7b826cfc, 0x7b80c686, 0x7b7f1fc3, 0x7b7d78b4, 0x7b7bd159,
-    0x7b7a29b2, 0x7b7881be,
-  0x7b76d97f, 0x7b7530f3, 0x7b73881b, 0x7b71def7, 0x7b703587, 0x7b6e8bcb,
-    0x7b6ce1c2, 0x7b6b376e,
-  0x7b698ccd, 0x7b67e1e0, 0x7b6636a7, 0x7b648b22, 0x7b62df51, 0x7b613334,
-    0x7b5f86ca, 0x7b5dda15,
-  0x7b5c2d13, 0x7b5a7fc6, 0x7b58d22c, 0x7b572446, 0x7b557614, 0x7b53c796,
-    0x7b5218cc, 0x7b5069b6,
-  0x7b4eba53, 0x7b4d0aa5, 0x7b4b5aab, 0x7b49aa64, 0x7b47f9d2, 0x7b4648f3,
-    0x7b4497c9, 0x7b42e652,
-  0x7b413490, 0x7b3f8281, 0x7b3dd026, 0x7b3c1d80, 0x7b3a6a8d, 0x7b38b74e,
-    0x7b3703c3, 0x7b354fed,
-  0x7b339bca, 0x7b31e75b, 0x7b3032a0, 0x7b2e7d9a, 0x7b2cc847, 0x7b2b12a8,
-    0x7b295cbe, 0x7b27a687,
-  0x7b25f004, 0x7b243936, 0x7b22821b, 0x7b20cab5, 0x7b1f1302, 0x7b1d5b04,
-    0x7b1ba2b9, 0x7b19ea23,
-  0x7b183141, 0x7b167813, 0x7b14be99, 0x7b1304d3, 0x7b114ac1, 0x7b0f9063,
-    0x7b0dd5b9, 0x7b0c1ac4,
-  0x7b0a5f82, 0x7b08a3f5, 0x7b06e81b, 0x7b052bf6, 0x7b036f85, 0x7b01b2c8,
-    0x7afff5bf, 0x7afe386a,
-  0x7afc7aca, 0x7afabcdd, 0x7af8fea5, 0x7af74021, 0x7af58151, 0x7af3c235,
-    0x7af202cd, 0x7af0431a,
-  0x7aee831a, 0x7aecc2cf, 0x7aeb0238, 0x7ae94155, 0x7ae78026, 0x7ae5beac,
-    0x7ae3fce6, 0x7ae23ad4,
-  0x7ae07876, 0x7adeb5cc, 0x7adcf2d6, 0x7adb2f95, 0x7ad96c08, 0x7ad7a82f,
-    0x7ad5e40a, 0x7ad41f9a,
-  0x7ad25ade, 0x7ad095d6, 0x7aced082, 0x7acd0ae3, 0x7acb44f8, 0x7ac97ec1,
-    0x7ac7b83e, 0x7ac5f170,
-  0x7ac42a55, 0x7ac262ef, 0x7ac09b3e, 0x7abed341, 0x7abd0af7, 0x7abb4263,
-    0x7ab97982, 0x7ab7b056,
-  0x7ab5e6de, 0x7ab41d1b, 0x7ab2530b, 0x7ab088b0, 0x7aaebe0a, 0x7aacf318,
-    0x7aab27da, 0x7aa95c50,
-  0x7aa7907b, 0x7aa5c45a, 0x7aa3f7ed, 0x7aa22b35, 0x7aa05e31, 0x7a9e90e1,
-    0x7a9cc346, 0x7a9af55f,
-  0x7a99272d, 0x7a9758af, 0x7a9589e5, 0x7a93bad0, 0x7a91eb6f, 0x7a901bc2,
-    0x7a8e4bca, 0x7a8c7b87,
-  0x7a8aaaf7, 0x7a88da1c, 0x7a8708f6, 0x7a853784, 0x7a8365c6, 0x7a8193bd,
-    0x7a7fc168, 0x7a7deec8,
-  0x7a7c1bdc, 0x7a7a48a4, 0x7a787521, 0x7a76a153, 0x7a74cd38, 0x7a72f8d3,
-    0x7a712422, 0x7a6f4f25,
-  0x7a6d79dd, 0x7a6ba449, 0x7a69ce6a, 0x7a67f83f, 0x7a6621c9, 0x7a644b07,
-    0x7a6273fa, 0x7a609ca1,
-  0x7a5ec4fc, 0x7a5ced0d, 0x7a5b14d1, 0x7a593c4b, 0x7a576379, 0x7a558a5b,
-    0x7a53b0f2, 0x7a51d73d,
-  0x7a4ffd3d, 0x7a4e22f2, 0x7a4c485b, 0x7a4a6d78, 0x7a48924b, 0x7a46b6d1,
-    0x7a44db0d, 0x7a42fefd,
-  0x7a4122a1, 0x7a3f45fa, 0x7a3d6908, 0x7a3b8bca, 0x7a39ae41, 0x7a37d06d,
-    0x7a35f24d, 0x7a3413e2,
-  0x7a32352b, 0x7a305629, 0x7a2e76dc, 0x7a2c9743, 0x7a2ab75f, 0x7a28d72f,
-    0x7a26f6b4, 0x7a2515ee,
-  0x7a2334dd, 0x7a215380, 0x7a1f71d7, 0x7a1d8fe4, 0x7a1bada5, 0x7a19cb1b,
-    0x7a17e845, 0x7a160524,
-  0x7a1421b8, 0x7a123e01, 0x7a1059fe, 0x7a0e75b0, 0x7a0c9117, 0x7a0aac32,
-    0x7a08c702, 0x7a06e187,
-  0x7a04fbc1, 0x7a0315af, 0x7a012f52, 0x79ff48aa, 0x79fd61b6, 0x79fb7a77,
-    0x79f992ed, 0x79f7ab18,
-  0x79f5c2f8, 0x79f3da8c, 0x79f1f1d5, 0x79f008d3, 0x79ee1f86, 0x79ec35ed,
-    0x79ea4c09, 0x79e861da,
-  0x79e67760, 0x79e48c9b, 0x79e2a18a, 0x79e0b62e, 0x79deca87, 0x79dcde95,
-    0x79daf258, 0x79d905d0,
-  0x79d718fc, 0x79d52bdd, 0x79d33e73, 0x79d150be, 0x79cf62be, 0x79cd7473,
-    0x79cb85dc, 0x79c996fb,
-  0x79c7a7ce, 0x79c5b856, 0x79c3c893, 0x79c1d885, 0x79bfe82c, 0x79bdf788,
-    0x79bc0698, 0x79ba155e,
-  0x79b823d8, 0x79b63207, 0x79b43fec, 0x79b24d85, 0x79b05ad3, 0x79ae67d6,
-    0x79ac748e, 0x79aa80fb,
-  0x79a88d1d, 0x79a698f4, 0x79a4a480, 0x79a2afc1, 0x79a0bab6, 0x799ec561,
-    0x799ccfc1, 0x799ad9d5,
-  0x7998e39f, 0x7996ed1e, 0x7994f651, 0x7992ff3a, 0x799107d8, 0x798f102a,
-    0x798d1832, 0x798b1fef,
-  0x79892761, 0x79872e87, 0x79853563, 0x79833bf4, 0x7981423a, 0x797f4835,
-    0x797d4de5, 0x797b534a,
-  0x79795864, 0x79775d33, 0x797561b8, 0x797365f1, 0x797169df, 0x796f6d83,
-    0x796d70dc, 0x796b73e9,
-  0x796976ac, 0x79677924, 0x79657b51, 0x79637d33, 0x79617eca, 0x795f8017,
-    0x795d8118, 0x795b81cf,
-  0x7959823b, 0x7957825c, 0x79558232, 0x795381bd, 0x795180fe, 0x794f7ff3,
-    0x794d7e9e, 0x794b7cfe,
-  0x79497b13, 0x794778dd, 0x7945765d, 0x79437391, 0x7941707b, 0x793f6d1a,
-    0x793d696f, 0x793b6578,
-  0x79396137, 0x79375cab, 0x793557d4, 0x793352b2, 0x79314d46, 0x792f478f,
-    0x792d418d, 0x792b3b40,
-  0x792934a9, 0x79272dc7, 0x7925269a, 0x79231f22, 0x79211760, 0x791f0f53,
-    0x791d06fb, 0x791afe59,
-  0x7918f56c, 0x7916ec34, 0x7914e2b2, 0x7912d8e4, 0x7910cecc, 0x790ec46a,
-    0x790cb9bd, 0x790aaec5,
-  0x7908a382, 0x790697f5, 0x79048c1d, 0x79027ffa, 0x7900738d, 0x78fe66d5,
-    0x78fc59d3, 0x78fa4c86,
-  0x78f83eee, 0x78f6310c, 0x78f422df, 0x78f21467, 0x78f005a5, 0x78edf698,
-    0x78ebe741, 0x78e9d79f,
-  0x78e7c7b2, 0x78e5b77b, 0x78e3a6f9, 0x78e1962d, 0x78df8516, 0x78dd73b5,
-    0x78db6209, 0x78d95012,
-  0x78d73dd1, 0x78d52b46, 0x78d31870, 0x78d1054f, 0x78cef1e4, 0x78ccde2e,
-    0x78caca2e, 0x78c8b5e3,
-  0x78c6a14e, 0x78c48c6e, 0x78c27744, 0x78c061cf, 0x78be4c10, 0x78bc3606,
-    0x78ba1fb2, 0x78b80913,
-  0x78b5f22a, 0x78b3daf7, 0x78b1c379, 0x78afabb0, 0x78ad939d, 0x78ab7b40,
-    0x78a96298, 0x78a749a6,
-  0x78a53069, 0x78a316e2, 0x78a0fd11, 0x789ee2f5, 0x789cc88f, 0x789aadde,
-    0x789892e3, 0x7896779d,
-  0x78945c0d, 0x78924033, 0x7890240e, 0x788e07a0, 0x788beae6, 0x7889cde2,
-    0x7887b094, 0x788592fc,
-  0x78837519, 0x788156ec, 0x787f3875, 0x787d19b3, 0x787afaa7, 0x7878db50,
-    0x7876bbb0, 0x78749bc5,
-  0x78727b8f, 0x78705b10, 0x786e3a46, 0x786c1932, 0x7869f7d3, 0x7867d62a,
-    0x7865b437, 0x786391fa,
-  0x78616f72, 0x785f4ca1, 0x785d2984, 0x785b061e, 0x7858e26e, 0x7856be73,
-    0x78549a2e, 0x7852759e,
-  0x785050c5, 0x784e2ba1, 0x784c0633, 0x7849e07b, 0x7847ba79, 0x7845942c,
-    0x78436d96, 0x784146b5,
-  0x783f1f8a, 0x783cf815, 0x783ad055, 0x7838a84c, 0x78367ff8, 0x7834575a,
-    0x78322e72, 0x78300540,
-  0x782ddbc4, 0x782bb1fd, 0x782987ed, 0x78275d92, 0x782532ed, 0x782307fe,
-    0x7820dcc5, 0x781eb142,
-  0x781c8575, 0x781a595d, 0x78182cfc, 0x78160051, 0x7813d35b, 0x7811a61b,
-    0x780f7892, 0x780d4abe,
-  0x780b1ca0, 0x7808ee38, 0x7806bf86, 0x7804908a, 0x78026145, 0x780031b5,
-    0x77fe01db, 0x77fbd1b6,
-  0x77f9a148, 0x77f77090, 0x77f53f8e, 0x77f30e42, 0x77f0dcac, 0x77eeaacc,
-    0x77ec78a2, 0x77ea462e,
-  0x77e81370, 0x77e5e068, 0x77e3ad17, 0x77e1797b, 0x77df4595, 0x77dd1165,
-    0x77dadcec, 0x77d8a828,
-  0x77d6731a, 0x77d43dc3, 0x77d20822, 0x77cfd236, 0x77cd9c01, 0x77cb6582,
-    0x77c92eb9, 0x77c6f7a6,
-  0x77c4c04a, 0x77c288a3, 0x77c050b2, 0x77be1878, 0x77bbdff4, 0x77b9a726,
-    0x77b76e0e, 0x77b534ac,
-  0x77b2fb00, 0x77b0c10b, 0x77ae86cc, 0x77ac4c43, 0x77aa1170, 0x77a7d653,
-    0x77a59aec, 0x77a35f3c,
-  0x77a12342, 0x779ee6fe, 0x779caa70, 0x779a6d99, 0x77983077, 0x7795f30c,
-    0x7793b557, 0x77917759,
-  0x778f3910, 0x778cfa7e, 0x778abba2, 0x77887c7d, 0x77863d0d, 0x7783fd54,
-    0x7781bd52, 0x777f7d05,
-  0x777d3c6f, 0x777afb8f, 0x7778ba65, 0x777678f2, 0x77743735, 0x7771f52e,
-    0x776fb2de, 0x776d7044,
-  0x776b2d60, 0x7768ea33, 0x7766a6bc, 0x776462fb, 0x77621ef1, 0x775fda9d,
-    0x775d95ff, 0x775b5118,
-  0x77590be7, 0x7756c66c, 0x775480a8, 0x77523a9b, 0x774ff443, 0x774dada2,
-    0x774b66b8, 0x77491f84,
-  0x7746d806, 0x7744903f, 0x7742482e, 0x773fffd4, 0x773db730, 0x773b6e42,
-    0x7739250b, 0x7736db8b,
-  0x773491c0, 0x773247ad, 0x772ffd50, 0x772db2a9, 0x772b67b9, 0x77291c7f,
-    0x7726d0fc, 0x7724852f,
-  0x77223919, 0x771fecb9, 0x771da010, 0x771b531d, 0x771905e1, 0x7716b85b,
-    0x77146a8c, 0x77121c74,
-  0x770fce12, 0x770d7f66, 0x770b3072, 0x7708e133, 0x770691ab, 0x770441da,
-    0x7701f1c0, 0x76ffa15c,
-  0x76fd50ae, 0x76faffb8, 0x76f8ae78, 0x76f65cee, 0x76f40b1b, 0x76f1b8ff,
-    0x76ef6699, 0x76ed13ea,
-  0x76eac0f2, 0x76e86db0, 0x76e61a25, 0x76e3c650, 0x76e17233, 0x76df1dcb,
-    0x76dcc91b, 0x76da7421,
-  0x76d81ede, 0x76d5c952, 0x76d3737c, 0x76d11d5d, 0x76cec6f5, 0x76cc7043,
-    0x76ca1948, 0x76c7c204,
-  0x76c56a77, 0x76c312a0, 0x76c0ba80, 0x76be6217, 0x76bc0965, 0x76b9b069,
-    0x76b75724, 0x76b4fd96,
-  0x76b2a3bf, 0x76b0499e, 0x76adef34, 0x76ab9481, 0x76a93985, 0x76a6de40,
-    0x76a482b1, 0x76a226da,
-  0x769fcab9, 0x769d6e4f, 0x769b119b, 0x7698b49f, 0x76965759, 0x7693f9ca,
-    0x76919bf3, 0x768f3dd2,
-  0x768cdf67, 0x768a80b4, 0x768821b8, 0x7685c272, 0x768362e4, 0x7681030c,
-    0x767ea2eb, 0x767c4281,
-  0x7679e1ce, 0x767780d2, 0x76751f8d, 0x7672bdfe, 0x76705c27, 0x766dfa07,
-    0x766b979d, 0x766934eb,
-  0x7666d1ef, 0x76646eab, 0x76620b1d, 0x765fa747, 0x765d4327, 0x765adebe,
-    0x76587a0d, 0x76561512,
-  0x7653afce, 0x76514a42, 0x764ee46c, 0x764c7e4d, 0x764a17e6, 0x7647b135,
-    0x76454a3c, 0x7642e2f9,
-  0x76407b6e, 0x763e139a, 0x763bab7c, 0x76394316, 0x7636da67, 0x7634716f,
-    0x7632082e, 0x762f9ea4,
-  0x762d34d1, 0x762acab6, 0x76286051, 0x7625f5a3, 0x76238aad, 0x76211f6e,
-    0x761eb3e6, 0x761c4815,
-  0x7619dbfb, 0x76176f98, 0x761502ed, 0x761295f9, 0x761028bb, 0x760dbb35,
-    0x760b4d67, 0x7608df4f,
-  0x760670ee, 0x76040245, 0x76019353, 0x75ff2418, 0x75fcb495, 0x75fa44c8,
-    0x75f7d4b3, 0x75f56455,
-  0x75f2f3ae, 0x75f082bf, 0x75ee1187, 0x75eba006, 0x75e92e3c, 0x75e6bc2a,
-    0x75e449ce, 0x75e1d72b,
-  0x75df643e, 0x75dcf109, 0x75da7d8b, 0x75d809c4, 0x75d595b4, 0x75d3215c,
-    0x75d0acbc, 0x75ce37d2,
-  0x75cbc2a0, 0x75c94d25, 0x75c6d762, 0x75c46156, 0x75c1eb01, 0x75bf7464,
-    0x75bcfd7e, 0x75ba864f,
-  0x75b80ed8, 0x75b59718, 0x75b31f0f, 0x75b0a6be, 0x75ae2e25, 0x75abb542,
-    0x75a93c18, 0x75a6c2a4,
-  0x75a448e8, 0x75a1cee4, 0x759f5496, 0x759cda01, 0x759a5f22, 0x7597e3fc,
-    0x7595688c, 0x7592ecd4,
-  0x759070d4, 0x758df48b, 0x758b77fa, 0x7588fb20, 0x75867dfd, 0x75840093,
-    0x758182df, 0x757f04e3,
-  0x757c869f, 0x757a0812, 0x7577893d, 0x75750a1f, 0x75728ab9, 0x75700b0a,
-    0x756d8b13, 0x756b0ad3,
-  0x75688a4b, 0x7566097b, 0x75638862, 0x75610701, 0x755e8557, 0x755c0365,
-    0x7559812b, 0x7556fea8,
-  0x75547bdd, 0x7551f8c9, 0x754f756e, 0x754cf1c9, 0x754a6ddd, 0x7547e9a8,
-    0x7545652a, 0x7542e065,
-  0x75405b57, 0x753dd600, 0x753b5061, 0x7538ca7b, 0x7536444b, 0x7533bdd4,
-    0x75313714, 0x752eb00c,
-  0x752c28bb, 0x7529a122, 0x75271941, 0x75249118, 0x752208a7, 0x751f7fed,
-    0x751cf6eb, 0x751a6da0,
-  0x7517e40e, 0x75155a33, 0x7512d010, 0x751045a5, 0x750dbaf2, 0x750b2ff6,
-    0x7508a4b2, 0x75061926,
-  0x75038d52, 0x75010136, 0x74fe74d1, 0x74fbe825, 0x74f95b30, 0x74f6cdf3,
-    0x74f4406d, 0x74f1b2a0,
-  0x74ef248b, 0x74ec962d, 0x74ea0787, 0x74e7789a, 0x74e4e964, 0x74e259e6,
-    0x74dfca20, 0x74dd3a11,
-  0x74daa9bb, 0x74d8191d, 0x74d58836, 0x74d2f708, 0x74d06591, 0x74cdd3d2,
-    0x74cb41cc, 0x74c8af7d,
-  0x74c61ce6, 0x74c38a07, 0x74c0f6e0, 0x74be6372, 0x74bbcfbb, 0x74b93bbc,
-    0x74b6a775, 0x74b412e6,
-  0x74b17e0f, 0x74aee8f0, 0x74ac5389, 0x74a9bddb, 0x74a727e4, 0x74a491a5,
-    0x74a1fb1e, 0x749f6450,
-  0x749ccd39, 0x749a35db, 0x74979e34, 0x74950646, 0x74926e10, 0x748fd592,
-    0x748d3ccb, 0x748aa3be,
-  0x74880a68, 0x748570ca, 0x7482d6e4, 0x74803cb7, 0x747da242, 0x747b0784,
-    0x74786c7f, 0x7475d132,
-  0x7473359e, 0x747099c1, 0x746dfd9d, 0x746b6131, 0x7468c47c, 0x74662781,
-    0x74638a3d, 0x7460ecb2,
-  0x745e4ede, 0x745bb0c3, 0x74591261, 0x745673b6, 0x7453d4c4, 0x7451358a,
-    0x744e9608, 0x744bf63e,
-  0x7449562d, 0x7446b5d4, 0x74441533, 0x7441744b, 0x743ed31b, 0x743c31a3,
-    0x74398fe3, 0x7436eddc,
-  0x74344b8d, 0x7431a8f6, 0x742f0618, 0x742c62f2, 0x7429bf84, 0x74271bcf,
-    0x742477d2, 0x7421d38e,
-  0x741f2f01, 0x741c8a2d, 0x7419e512, 0x74173faf, 0x74149a04, 0x7411f412,
-    0x740f4dd8, 0x740ca756,
-  0x740a008d, 0x7407597d, 0x7404b224, 0x74020a85, 0x73ff629d, 0x73fcba6e,
-    0x73fa11f8, 0x73f7693a,
-  0x73f4c034, 0x73f216e7, 0x73ef6d53, 0x73ecc377, 0x73ea1953, 0x73e76ee8,
-    0x73e4c435, 0x73e2193b,
-  0x73df6df9, 0x73dcc270, 0x73da16a0, 0x73d76a88, 0x73d4be28, 0x73d21182,
-    0x73cf6493, 0x73ccb75d,
-  0x73ca09e0, 0x73c75c1c, 0x73c4ae10, 0x73c1ffbc, 0x73bf5121, 0x73bca23f,
-    0x73b9f315, 0x73b743a4,
-  0x73b493ec, 0x73b1e3ec, 0x73af33a5, 0x73ac8316, 0x73a9d240, 0x73a72123,
-    0x73a46fbf, 0x73a1be13,
-  0x739f0c20, 0x739c59e5, 0x7399a763, 0x7396f49a, 0x73944189, 0x73918e32,
-    0x738eda93, 0x738c26ac,
-  0x7389727f, 0x7386be0a, 0x7384094e, 0x7381544a, 0x737e9f00, 0x737be96e,
-    0x73793395, 0x73767d74,
-  0x7373c70d, 0x7371105e, 0x736e5968, 0x736ba22b, 0x7368eaa6, 0x736632db,
-    0x73637ac8, 0x7360c26e,
-  0x735e09cd, 0x735b50e4, 0x735897b5, 0x7355de3e, 0x73532481, 0x73506a7c,
-    0x734db030, 0x734af59d,
-  0x73483ac2, 0x73457fa1, 0x7342c438, 0x73400889, 0x733d4c92, 0x733a9054,
-    0x7337d3d0, 0x73351704,
-  0x733259f1, 0x732f9c97, 0x732cdef6, 0x732a210d, 0x732762de, 0x7324a468,
-    0x7321e5ab, 0x731f26a7,
-  0x731c675b, 0x7319a7c9, 0x7316e7f0, 0x731427cf, 0x73116768, 0x730ea6ba,
-    0x730be5c5, 0x73092489,
-  0x73066306, 0x7303a13b, 0x7300df2a, 0x72fe1cd2, 0x72fb5a34, 0x72f8974e,
-    0x72f5d421, 0x72f310ad,
-  0x72f04cf3, 0x72ed88f1, 0x72eac4a9, 0x72e8001a, 0x72e53b44, 0x72e27627,
-    0x72dfb0c3, 0x72dceb18,
-  0x72da2526, 0x72d75eee, 0x72d4986f, 0x72d1d1a9, 0x72cf0a9c, 0x72cc4348,
-    0x72c97bad, 0x72c6b3cc,
-  0x72c3eba4, 0x72c12335, 0x72be5a7f, 0x72bb9183, 0x72b8c83f, 0x72b5feb5,
-    0x72b334e4, 0x72b06acd,
-  0x72ada06f, 0x72aad5c9, 0x72a80ade, 0x72a53fab, 0x72a27432, 0x729fa872,
-    0x729cdc6b, 0x729a101e,
-  0x7297438a, 0x729476af, 0x7291a98e, 0x728edc26, 0x728c0e77, 0x72894082,
-    0x72867245, 0x7283a3c3,
-  0x7280d4f9, 0x727e05e9, 0x727b3693, 0x727866f6, 0x72759712, 0x7272c6e7,
-    0x726ff676, 0x726d25bf,
-  0x726a54c1, 0x7267837c, 0x7264b1f0, 0x7261e01e, 0x725f0e06, 0x725c3ba7,
-    0x72596901, 0x72569615,
-  0x7253c2e3, 0x7250ef6a, 0x724e1baa, 0x724b47a4, 0x72487357, 0x72459ec4,
-    0x7242c9ea, 0x723ff4ca,
-  0x723d1f63, 0x723a49b6, 0x723773c3, 0x72349d89, 0x7231c708, 0x722ef041,
-    0x722c1934, 0x722941e0,
-  0x72266a46, 0x72239266, 0x7220ba3f, 0x721de1d1, 0x721b091d, 0x72183023,
-    0x721556e3, 0x72127d5c,
-  0x720fa38e, 0x720cc97b, 0x7209ef21, 0x72071480, 0x7204399a, 0x72015e6d,
-    0x71fe82f9, 0x71fba740,
-  0x71f8cb40, 0x71f5eefa, 0x71f3126d, 0x71f0359a, 0x71ed5881, 0x71ea7b22,
-    0x71e79d7c, 0x71e4bf90,
-  0x71e1e15e, 0x71df02e5, 0x71dc2427, 0x71d94522, 0x71d665d6, 0x71d38645,
-    0x71d0a66d, 0x71cdc650,
-  0x71cae5ec, 0x71c80542, 0x71c52451, 0x71c2431b, 0x71bf619e, 0x71bc7fdb,
-    0x71b99dd2, 0x71b6bb83,
-  0x71b3d8ed, 0x71b0f612, 0x71ae12f0, 0x71ab2f89, 0x71a84bdb, 0x71a567e7,
-    0x71a283ad, 0x719f9f2c,
-  0x719cba66, 0x7199d55a, 0x7196f008, 0x71940a6f, 0x71912490, 0x718e3e6c,
-    0x718b5801, 0x71887151,
-  0x71858a5a, 0x7182a31d, 0x717fbb9a, 0x717cd3d2, 0x7179ebc3, 0x7177036e,
-    0x71741ad3, 0x717131f3,
-  0x716e48cc, 0x716b5f5f, 0x716875ad, 0x71658bb4, 0x7162a175, 0x715fb6f1,
-    0x715ccc26, 0x7159e116,
-  0x7156f5c0, 0x71540a24, 0x71511e42, 0x714e321a, 0x714b45ac, 0x714858f8,
-    0x71456bfe, 0x71427ebf,
-  0x713f9139, 0x713ca36e, 0x7139b55d, 0x7136c706, 0x7133d869, 0x7130e987,
-    0x712dfa5e, 0x712b0af0,
-  0x71281b3c, 0x71252b42, 0x71223b02, 0x711f4a7d, 0x711c59b2, 0x711968a1,
-    0x7116774a, 0x711385ad,
-  0x711093cb, 0x710da1a3, 0x710aaf35, 0x7107bc82, 0x7104c989, 0x7101d64a,
-    0x70fee2c5, 0x70fbeefb,
-  0x70f8faeb, 0x70f60695, 0x70f311fa, 0x70f01d19, 0x70ed27f2, 0x70ea3286,
-    0x70e73cd4, 0x70e446dc,
-  0x70e1509f, 0x70de5a1c, 0x70db6353, 0x70d86c45, 0x70d574f1, 0x70d27d58,
-    0x70cf8579, 0x70cc8d54,
-  0x70c994ea, 0x70c69c3a, 0x70c3a345, 0x70c0aa0a, 0x70bdb08a, 0x70bab6c4,
-    0x70b7bcb8, 0x70b4c267,
-  0x70b1c7d1, 0x70aeccf5, 0x70abd1d3, 0x70a8d66c, 0x70a5dac0, 0x70a2dece,
-    0x709fe296, 0x709ce619,
-  0x7099e957, 0x7096ec4f, 0x7093ef01, 0x7090f16e, 0x708df396, 0x708af579,
-    0x7087f715, 0x7084f86d,
-  0x7081f97f, 0x707efa4c, 0x707bfad3, 0x7078fb15, 0x7075fb11, 0x7072fac9,
-    0x706ffa3a, 0x706cf967,
-  0x7069f84e, 0x7066f6f0, 0x7063f54c, 0x7060f363, 0x705df135, 0x705aeec1,
-    0x7057ec08, 0x7054e90a,
-  0x7051e5c7, 0x704ee23e, 0x704bde70, 0x7048da5d, 0x7045d604, 0x7042d166,
-    0x703fcc83, 0x703cc75b,
-  0x7039c1ed, 0x7036bc3b, 0x7033b643, 0x7030b005, 0x702da983, 0x702aa2bb,
-    0x70279baf, 0x7024945d,
-  0x70218cc6, 0x701e84e9, 0x701b7cc8, 0x70187461, 0x70156bb5, 0x701262c4,
-    0x700f598e, 0x700c5013,
-  0x70094653, 0x70063c4e, 0x70033203, 0x70002774, 0x6ffd1c9f, 0x6ffa1185,
-    0x6ff70626, 0x6ff3fa82,
-  0x6ff0ee99, 0x6fede26b, 0x6fead5f8, 0x6fe7c940, 0x6fe4bc43, 0x6fe1af01,
-    0x6fdea17a, 0x6fdb93ae,
-  0x6fd8859d, 0x6fd57746, 0x6fd268ab, 0x6fcf59cb, 0x6fcc4aa6, 0x6fc93b3c,
-    0x6fc62b8d, 0x6fc31b99,
-  0x6fc00b60, 0x6fbcfae2, 0x6fb9ea20, 0x6fb6d918, 0x6fb3c7cb, 0x6fb0b63a,
-    0x6fada464, 0x6faa9248,
-  0x6fa77fe8, 0x6fa46d43, 0x6fa15a59, 0x6f9e472b, 0x6f9b33b7, 0x6f981fff,
-    0x6f950c01, 0x6f91f7bf,
-  0x6f8ee338, 0x6f8bce6c, 0x6f88b95c, 0x6f85a407, 0x6f828e6c, 0x6f7f788d,
-    0x6f7c626a, 0x6f794c01,
-  0x6f763554, 0x6f731e62, 0x6f70072b, 0x6f6cefb0, 0x6f69d7f0, 0x6f66bfeb,
-    0x6f63a7a1, 0x6f608f13,
-  0x6f5d7640, 0x6f5a5d28, 0x6f5743cb, 0x6f542a2a, 0x6f511044, 0x6f4df61a,
-    0x6f4adbab, 0x6f47c0f7,
-  0x6f44a5ff, 0x6f418ac2, 0x6f3e6f40, 0x6f3b537a, 0x6f38376f, 0x6f351b1f,
-    0x6f31fe8b, 0x6f2ee1b2,
-  0x6f2bc495, 0x6f28a733, 0x6f25898d, 0x6f226ba2, 0x6f1f4d72, 0x6f1c2efe,
-    0x6f191045, 0x6f15f148,
-  0x6f12d206, 0x6f0fb280, 0x6f0c92b6, 0x6f0972a6, 0x6f065253, 0x6f0331ba,
-    0x6f0010de, 0x6efcefbd,
-  0x6ef9ce57, 0x6ef6acad, 0x6ef38abe, 0x6ef0688b, 0x6eed4614, 0x6eea2358,
-    0x6ee70058, 0x6ee3dd13,
-  0x6ee0b98a, 0x6edd95bd, 0x6eda71ab, 0x6ed74d55, 0x6ed428ba, 0x6ed103db,
-    0x6ecddeb8, 0x6ecab950,
-  0x6ec793a4, 0x6ec46db4, 0x6ec1477f, 0x6ebe2106, 0x6ebafa49, 0x6eb7d347,
-    0x6eb4ac02, 0x6eb18477,
-  0x6eae5ca9, 0x6eab3496, 0x6ea80c3f, 0x6ea4e3a4, 0x6ea1bac4, 0x6e9e91a1,
-    0x6e9b6839, 0x6e983e8d,
-  0x6e95149c, 0x6e91ea67, 0x6e8ebfef, 0x6e8b9532, 0x6e886a30, 0x6e853eeb,
-    0x6e821361, 0x6e7ee794,
-  0x6e7bbb82, 0x6e788f2c, 0x6e756291, 0x6e7235b3, 0x6e6f0890, 0x6e6bdb2a,
-    0x6e68ad7f, 0x6e657f90,
-  0x6e62515d, 0x6e5f22e6, 0x6e5bf42b, 0x6e58c52c, 0x6e5595e9, 0x6e526662,
-    0x6e4f3696, 0x6e4c0687,
-  0x6e48d633, 0x6e45a59c, 0x6e4274c1, 0x6e3f43a1, 0x6e3c123e, 0x6e38e096,
-    0x6e35aeab, 0x6e327c7b,
-  0x6e2f4a08, 0x6e2c1750, 0x6e28e455, 0x6e25b115, 0x6e227d92, 0x6e1f49cb,
-    0x6e1c15c0, 0x6e18e171,
-  0x6e15acde, 0x6e127807, 0x6e0f42ec, 0x6e0c0d8e, 0x6e08d7eb, 0x6e05a205,
-    0x6e026bda, 0x6dff356c,
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-    0x6cc94e4b, 0x6cc5fe8f,
-  0x6cc2ae90, 0x6cbf5e4d, 0x6cbc0dc8, 0x6cb8bcff, 0x6cb56bf4, 0x6cb21aa5,
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-  0x6bb6605a, 0x6bb2fb3b, 0x6baf95d9, 0x6bac3034, 0x6ba8ca4e, 0x6ba56425,
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-  0x6b9b301b, 0x6b97c8e8, 0x6b946173, 0x6b90f9bc, 0x6b8d91c2, 0x6b8a2986,
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-  0x6b7fef43, 0x6b7c85fe, 0x6b791c76, 0x6b75b2ac, 0x6b7248a0, 0x6b6ede51,
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-  0x6b649dd8, 0x6b613280, 0x6b5dc6e6, 0x6b5a5b0a, 0x6b56eeec, 0x6b53828b,
-    0x6b5015e9, 0x6b4ca904,
-  0x6b493bdd, 0x6b45ce73, 0x6b4260c8, 0x6b3ef2da, 0x6b3b84ab, 0x6b381639,
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-  0x6b2dc956, 0x6b2a59dc, 0x6b26ea1f, 0x6b237a21, 0x6b2009e0, 0x6b1c995d,
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-  0x6b124648, 0x6b0ed4bd, 0x6b0b62f0, 0x6b07f0e1, 0x6b047e90, 0x6b010bfd,
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-  0x6af6b2b7, 0x6af33f1c, 0x6aefcb3f, 0x6aec5720, 0x6ae8e2bf, 0x6ae56e1c,
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-    0x6ac648cb, 0x6ac2d195,
-  0x6abf5a1e, 0x6abbe264, 0x6ab86a68, 0x6ab4f22b, 0x6ab179ac, 0x6aae00eb,
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-  0x6aa3951d, 0x6aa01b55, 0x6a9ca14b, 0x6a992700, 0x6a95ac72, 0x6a9231a3,
-    0x6a8eb692, 0x6a8b3b3f,
-  0x6a87bfab, 0x6a8443d5, 0x6a80c7bd, 0x6a7d4b64, 0x6a79cec8, 0x6a7651ec,
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-  0x6a6bd9cb, 0x6a685be8, 0x6a64ddc2, 0x6a615f5c, 0x6a5de0b3, 0x6a5a61c9,
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-  0x6a4fe382, 0x6a4c6391, 0x6a48e360, 0x6a4562ec, 0x6a41e237, 0x6a3e6140,
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-  0x6a33dcd4, 0x6a305ad7, 0x6a2cd899, 0x6a295619, 0x6a25d358, 0x6a225055,
-    0x6a1ecd11, 0x6a1b498c,
-  0x6a17c5c5, 0x6a1441bc, 0x6a10bd72, 0x6a0d38e7, 0x6a09b41a, 0x6a062f0c,
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-    0x69750433, 0x69717472,
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-  0x6918180c, 0x691481b2, 0x6910eb17, 0x690d543b, 0x6909bd1f, 0x690625c2,
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-  0x68de940f, 0x68daf9a9, 0x68d75f02, 0x68d3c41b, 0x68d028f2, 0x68cc8d8a,
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-  0x68c1b9cc, 0x68be1d61, 0x68ba80b5, 0x68b6e3c8, 0x68b3469b, 0x68afa92e,
-    0x68ac0b7f, 0x68a86d91,
-  0x68a4cf61, 0x68a130f1, 0x689d9241, 0x6899f350, 0x6896541f, 0x6892b4ad,
-    0x688f14fa, 0x688b7507,
-  0x6887d4d4, 0x68843460, 0x688093ab, 0x687cf2b6, 0x68795181, 0x6875b00b,
-    0x68720e55, 0x686e6c5e,
-  0x686aca27, 0x686727b0, 0x686384f8, 0x685fe200, 0x685c3ec7, 0x68589b4e,
-    0x6854f795, 0x6851539b,
-  0x684daf61, 0x684a0ae6, 0x6846662c, 0x6842c131, 0x683f1bf5, 0x683b7679,
-    0x6837d0bd, 0x68342ac1,
-  0x68308485, 0x682cde08, 0x6829374b, 0x6825904d, 0x6821e910, 0x681e4192,
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-  0x68134997, 0x680fa118, 0x680bf85a, 0x68084f5a, 0x6804a61b, 0x6800fc9c,
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-  0x67f5fe9d, 0x67f2541d, 0x67eea95d, 0x67eafe5d, 0x67e7531c, 0x67e3a79c,
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-  0x6744ecb2, 0x67413636, 0x673d7f7b, 0x6739c880, 0x67361145, 0x673259ca,
-    0x672ea210, 0x672aea17,
-  0x672731dd, 0x67237964, 0x671fc0ac, 0x671c07b4, 0x67184e7c, 0x67149504,
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-  0x66eb8c80, 0x66e7d00f, 0x66e4135d, 0x66e0566c, 0x66dc993c, 0x66d8dbcd,
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-  0x6618d6b9, 0x66150c73, 0x661141ed, 0x660d7729, 0x6609ac25, 0x6605e0e3,
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-  0x6561d4a4, 0x655dfe99, 0x655a2850, 0x655651c8, 0x65527b02, 0x654ea3fd,
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-  0x652456ad, 0x65207cbb, 0x651ca28a, 0x6518c81b, 0x6514ed6e, 0x65111283,
-    0x650d3759, 0x65095bf0,
-  0x6505804a, 0x6501a465, 0x64fdc841, 0x64f9ebe0, 0x64f60f40, 0x64f23262,
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-  0x64c7a4cb, 0x64c3c502, 0x64bfe4fc, 0x64bc04b6, 0x64b82433, 0x64b44372,
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-    0x649151bc, 0x648d6e8e,
-  0x64898b22, 0x6485a778, 0x6481c390, 0x647ddf6a, 0x6479fb06, 0x64761664,
-    0x64723184, 0x646e4c66,
-  0x646a670a, 0x64668170, 0x64629b98, 0x645eb582, 0x645acf2e, 0x6456e89d,
-    0x645301cd, 0x644f1ac0,
-  0x644b3375, 0x64474bec, 0x64436425, 0x643f7c20, 0x643b93dd, 0x6437ab5d,
-    0x6433c29f, 0x642fd9a3,
-  0x642bf069, 0x642806f1, 0x64241d3c, 0x64203348, 0x641c4917, 0x64185ea9,
-    0x641473fc, 0x64108912,
-  0x640c9dea, 0x6408b284, 0x6404c6e1, 0x6400db00, 0x63fceee1, 0x63f90285,
-    0x63f515eb, 0x63f12913,
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-    0x63d5a86f, 0x63d1b9aa,
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-    0x63b62b8e, 0x63b23add,
-  0x63ae49ee, 0x63aa58c2, 0x63a66759, 0x63a275b2, 0x639e83cd, 0x639a91ac,
-    0x63969f4c, 0x6392acaf,
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-    0x637703af, 0x63730f27,
-  0x636f1a62, 0x636b2560, 0x63673020, 0x63633aa3, 0x635f44e8, 0x635b4ef0,
-    0x635758bb, 0x63536249,
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-    0x63379e76, 0x6333a619,
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-    0x6317d4e3, 0x6313da9e,
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-    0x62f7fc08, 0x62f3ffda,
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-    0x62d813eb, 0x62d415d4,
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-    0x62b81c8f, 0x62b41c91,
-  0x62b01c57, 0x62ac1bdf, 0x62a81b2b, 0x62a41a3a, 0x62a0190c, 0x629c17a1,
-    0x629815fa, 0x62941415,
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-    0x62780030, 0x6273fc65,
-  0x626ff85e, 0x626bf41a, 0x6267ef99, 0x6263eadc, 0x625fe5e1, 0x625be0ab,
-    0x6257db37, 0x6253d587,
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-    0x6237a714, 0x62339f7e,
-  0x622f97ad, 0x622b8f9e, 0x62278754, 0x62237ecc, 0x621f7608, 0x621b6d08,
-    0x621763cb, 0x62135a51,
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-    0x61d6afdd, 0x61d2a29c,
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-    0x61b63f41, 0x61b2301e,
-  0x61ae20bf, 0x61aa1124, 0x61a6014d, 0x61a1f139, 0x619de0e9, 0x6199d05d,
-    0x6195bf94, 0x6191ae90,
-  0x618d9d4f, 0x61898bd2, 0x61857a19, 0x61816824, 0x617d55f2, 0x61794385,
-    0x617530db, 0x61711df5,
-  0x616d0ad3, 0x6168f775, 0x6164e3db, 0x6160d005, 0x615cbbf3, 0x6158a7a4,
-    0x6154931a, 0x61507e54,
-  0x614c6951, 0x61485413, 0x61443e98, 0x614028e2, 0x613c12f0, 0x6137fcc1,
-    0x6133e657, 0x612fcfb0,
-  0x612bb8ce, 0x6127a1b0, 0x61238a56, 0x611f72c0, 0x611b5aee, 0x611742e0,
-    0x61132a96, 0x610f1210,
-  0x610af94f, 0x6106e051, 0x6102c718, 0x60feada3, 0x60fa93f2, 0x60f67a05,
-    0x60f25fdd, 0x60ee4579,
-  0x60ea2ad8, 0x60e60ffd, 0x60e1f4e5, 0x60ddd991, 0x60d9be02, 0x60d5a237,
-    0x60d18631, 0x60cd69ee,
-  0x60c94d70, 0x60c530b6, 0x60c113c1, 0x60bcf690, 0x60b8d923, 0x60b4bb7a,
-    0x60b09d96, 0x60ac7f76,
-  0x60a8611b, 0x60a44284, 0x60a023b1, 0x609c04a3, 0x6097e559, 0x6093c5d3,
-    0x608fa612, 0x608b8616,
-  0x608765dd, 0x6083456a, 0x607f24ba, 0x607b03d0, 0x6076e2a9, 0x6072c148,
-    0x606e9faa, 0x606a7dd2,
-  0x60665bbd, 0x6062396e, 0x605e16e2, 0x6059f41c, 0x6055d11a, 0x6051addc,
-    0x604d8a63, 0x604966af,
-  0x604542bf, 0x60411e94, 0x603cfa2e, 0x6038d58c, 0x6034b0af, 0x60308b97,
-    0x602c6643, 0x602840b4,
-  0x60241ae9, 0x601ff4e3, 0x601bcea2, 0x6017a826, 0x6013816e, 0x600f5a7b,
-    0x600b334d, 0x60070be4,
-  0x6002e43f, 0x5ffebc5f, 0x5ffa9444, 0x5ff66bee, 0x5ff2435d, 0x5fee1a90,
-    0x5fe9f188, 0x5fe5c845,
-  0x5fe19ec7, 0x5fdd750e, 0x5fd94b19, 0x5fd520ea, 0x5fd0f67f, 0x5fcccbd9,
-    0x5fc8a0f8, 0x5fc475dc,
-  0x5fc04a85, 0x5fbc1ef3, 0x5fb7f326, 0x5fb3c71e, 0x5faf9adb, 0x5fab6e5d,
-    0x5fa741a3, 0x5fa314af,
-  0x5f9ee780, 0x5f9aba16, 0x5f968c70, 0x5f925e90, 0x5f8e3075, 0x5f8a021f,
-    0x5f85d38e, 0x5f81a4c2,
-  0x5f7d75bb, 0x5f794679, 0x5f7516fd, 0x5f70e745, 0x5f6cb753, 0x5f688726,
-    0x5f6456be, 0x5f60261b,
-  0x5f5bf53d, 0x5f57c424, 0x5f5392d1, 0x5f4f6143, 0x5f4b2f7a, 0x5f46fd76,
-    0x5f42cb37, 0x5f3e98be,
-  0x5f3a660a, 0x5f36331b, 0x5f31fff1, 0x5f2dcc8d, 0x5f2998ee, 0x5f256515,
-    0x5f213100, 0x5f1cfcb1,
-  0x5f18c827, 0x5f149363, 0x5f105e64, 0x5f0c292a, 0x5f07f3b6, 0x5f03be07,
-    0x5eff881d, 0x5efb51f9,
-  0x5ef71b9b, 0x5ef2e501, 0x5eeeae2d, 0x5eea771f, 0x5ee63fd6, 0x5ee20853,
-    0x5eddd094, 0x5ed9989c,
-  0x5ed56069, 0x5ed127fb, 0x5eccef53, 0x5ec8b671, 0x5ec47d54, 0x5ec043fc,
-    0x5ebc0a6a, 0x5eb7d09e,
-  0x5eb39697, 0x5eaf5c56, 0x5eab21da, 0x5ea6e724, 0x5ea2ac34, 0x5e9e7109,
-    0x5e9a35a4, 0x5e95fa05,
-  0x5e91be2b, 0x5e8d8217, 0x5e8945c8, 0x5e85093f, 0x5e80cc7c, 0x5e7c8f7f,
-    0x5e785247, 0x5e7414d5,
-  0x5e6fd729, 0x5e6b9943, 0x5e675b22, 0x5e631cc7, 0x5e5ede32, 0x5e5a9f62,
-    0x5e566059, 0x5e522115,
-  0x5e4de197, 0x5e49a1df, 0x5e4561ed, 0x5e4121c0, 0x5e3ce15a, 0x5e38a0b9,
-    0x5e345fde, 0x5e301ec9,
-  0x5e2bdd7a, 0x5e279bf1, 0x5e235a2e, 0x5e1f1830, 0x5e1ad5f9, 0x5e169388,
-    0x5e1250dc, 0x5e0e0df7,
-  0x5e09cad7, 0x5e05877e, 0x5e0143ea, 0x5dfd001d, 0x5df8bc15, 0x5df477d4,
-    0x5df03359, 0x5debeea3,
-  0x5de7a9b4, 0x5de3648b, 0x5ddf1f28, 0x5ddad98b, 0x5dd693b4, 0x5dd24da3,
-    0x5dce0759, 0x5dc9c0d4,
-  0x5dc57a16, 0x5dc1331d, 0x5dbcebeb, 0x5db8a480, 0x5db45cda, 0x5db014fa,
-    0x5dabcce1, 0x5da7848e,
-  0x5da33c01, 0x5d9ef33b, 0x5d9aaa3a, 0x5d966100, 0x5d92178d, 0x5d8dcddf,
-    0x5d8983f8, 0x5d8539d7,
-  0x5d80ef7c, 0x5d7ca4e8, 0x5d785a1a, 0x5d740f12, 0x5d6fc3d1, 0x5d6b7856,
-    0x5d672ca2, 0x5d62e0b4,
-  0x5d5e948c, 0x5d5a482a, 0x5d55fb90, 0x5d51aebb, 0x5d4d61ad, 0x5d491465,
-    0x5d44c6e4, 0x5d40792a,
-  0x5d3c2b35, 0x5d37dd08, 0x5d338ea0, 0x5d2f4000, 0x5d2af125, 0x5d26a212,
-    0x5d2252c5, 0x5d1e033e,
-  0x5d19b37e, 0x5d156385, 0x5d111352, 0x5d0cc2e5, 0x5d087240, 0x5d042161,
-    0x5cffd048, 0x5cfb7ef7,
-  0x5cf72d6b, 0x5cf2dba7, 0x5cee89a9, 0x5cea3772, 0x5ce5e501, 0x5ce19258,
-    0x5cdd3f75, 0x5cd8ec58,
-  0x5cd49903, 0x5cd04574, 0x5ccbf1ab, 0x5cc79daa, 0x5cc3496f, 0x5cbef4fc,
-    0x5cbaa04f, 0x5cb64b68,
-  0x5cb1f649, 0x5cada0f0, 0x5ca94b5e, 0x5ca4f594, 0x5ca09f8f, 0x5c9c4952,
-    0x5c97f2dc, 0x5c939c2c,
-  0x5c8f4544, 0x5c8aee22, 0x5c8696c7, 0x5c823f34, 0x5c7de767, 0x5c798f61,
-    0x5c753722, 0x5c70deaa,
-  0x5c6c85f9, 0x5c682d0f, 0x5c63d3eb, 0x5c5f7a8f, 0x5c5b20fa, 0x5c56c72c,
-    0x5c526d25, 0x5c4e12e5,
-  0x5c49b86d, 0x5c455dbb, 0x5c4102d0, 0x5c3ca7ad, 0x5c384c50, 0x5c33f0bb,
-    0x5c2f94ec, 0x5c2b38e5,
-  0x5c26dca5, 0x5c22802c, 0x5c1e237b, 0x5c19c690, 0x5c15696d, 0x5c110c11,
-    0x5c0cae7c, 0x5c0850ae,
-  0x5c03f2a8, 0x5bff9469, 0x5bfb35f1, 0x5bf6d740, 0x5bf27857, 0x5bee1935,
-    0x5be9b9da, 0x5be55a46,
-  0x5be0fa7a, 0x5bdc9a75, 0x5bd83a37, 0x5bd3d9c1, 0x5bcf7912, 0x5bcb182b,
-    0x5bc6b70b, 0x5bc255b2,
-  0x5bbdf421, 0x5bb99257, 0x5bb53054, 0x5bb0ce19, 0x5bac6ba6, 0x5ba808f9,
-    0x5ba3a615, 0x5b9f42f7,
-  0x5b9adfa2, 0x5b967c13, 0x5b92184d, 0x5b8db44d, 0x5b895016, 0x5b84eba6,
-    0x5b8086fd, 0x5b7c221c,
-  0x5b77bd02, 0x5b7357b0, 0x5b6ef226, 0x5b6a8c63, 0x5b662668, 0x5b61c035,
-    0x5b5d59c9, 0x5b58f324,
-  0x5b548c48, 0x5b502533, 0x5b4bbde6, 0x5b475660, 0x5b42eea2, 0x5b3e86ac,
-    0x5b3a1e7e, 0x5b35b617,
-  0x5b314d78, 0x5b2ce4a1, 0x5b287b91, 0x5b241249, 0x5b1fa8c9, 0x5b1b3f11,
-    0x5b16d521, 0x5b126af8,
-  0x5b0e0098, 0x5b0995ff, 0x5b052b2e, 0x5b00c025, 0x5afc54e3, 0x5af7e96a,
-    0x5af37db8, 0x5aef11cf,
-  0x5aeaa5ad, 0x5ae63953, 0x5ae1ccc1, 0x5add5ff7, 0x5ad8f2f5, 0x5ad485bb,
-    0x5ad01849, 0x5acbaa9f,
-  0x5ac73cbd, 0x5ac2cea3, 0x5abe6050, 0x5ab9f1c6, 0x5ab58304, 0x5ab1140a,
-    0x5aaca4d8, 0x5aa8356f,
-  0x5aa3c5cd, 0x5a9f55f3, 0x5a9ae5e2, 0x5a967598, 0x5a920517, 0x5a8d945d,
-    0x5a89236c, 0x5a84b243,
-  0x5a8040e3, 0x5a7bcf4a, 0x5a775d7a, 0x5a72eb71, 0x5a6e7931, 0x5a6a06ba,
-    0x5a65940a, 0x5a612123,
-  0x5a5cae04, 0x5a583aad, 0x5a53c71e, 0x5a4f5358, 0x5a4adf5a, 0x5a466b24,
-    0x5a41f6b7, 0x5a3d8212,
-  0x5a390d35, 0x5a349821, 0x5a3022d5, 0x5a2bad51, 0x5a273796, 0x5a22c1a3,
-    0x5a1e4b79, 0x5a19d517,
-  0x5a155e7d, 0x5a10e7ac, 0x5a0c70a3, 0x5a07f963, 0x5a0381eb, 0x59ff0a3c,
-    0x59fa9255, 0x59f61a36,
-  0x59f1a1e0, 0x59ed2953, 0x59e8b08e, 0x59e43792, 0x59dfbe5e, 0x59db44f3,
-    0x59d6cb50, 0x59d25176,
-  0x59cdd765, 0x59c95d1c, 0x59c4e29c, 0x59c067e4, 0x59bbecf5, 0x59b771cf,
-    0x59b2f671, 0x59ae7add,
-  0x59a9ff10, 0x59a5830d, 0x59a106d2, 0x599c8a60, 0x59980db6, 0x599390d5,
-    0x598f13bd, 0x598a966e,
-  0x598618e8, 0x59819b2a, 0x597d1d35, 0x59789f09, 0x597420a6, 0x596fa20b,
-    0x596b233a, 0x5966a431,
-  0x596224f1, 0x595da57a, 0x595925cc, 0x5954a5e6, 0x595025ca, 0x594ba576,
-    0x594724ec, 0x5942a42a,
-  0x593e2331, 0x5939a202, 0x5935209b, 0x59309efd, 0x592c1d28, 0x59279b1c,
-    0x592318d9, 0x591e9660,
-  0x591a13af, 0x591590c7, 0x59110da8, 0x590c8a53, 0x590806c6, 0x59038302,
-    0x58feff08, 0x58fa7ad7,
-  0x58f5f66e, 0x58f171cf, 0x58ececf9, 0x58e867ed, 0x58e3e2a9, 0x58df5d2e,
-    0x58dad77d, 0x58d65195,
-  0x58d1cb76, 0x58cd4520, 0x58c8be94, 0x58c437d1, 0x58bfb0d7, 0x58bb29a6,
-    0x58b6a23e, 0x58b21aa0,
-  0x58ad92cb, 0x58a90ac0, 0x58a4827d, 0x589ffa04, 0x589b7155, 0x5896e86f,
-    0x58925f52, 0x588dd5fe,
-  0x58894c74, 0x5884c2b3, 0x588038bb, 0x587bae8d, 0x58772429, 0x5872998e,
-    0x586e0ebc, 0x586983b4,
-  0x5864f875, 0x58606d00, 0x585be154, 0x58575571, 0x5852c958, 0x584e3d09,
-    0x5849b083, 0x584523c7,
-  0x584096d4, 0x583c09ab, 0x58377c4c, 0x5832eeb6, 0x582e60e9, 0x5829d2e6,
-    0x582544ad, 0x5820b63e,
-  0x581c2798, 0x581798bb, 0x581309a9, 0x580e7a60, 0x5809eae1, 0x58055b2b,
-    0x5800cb3f, 0x57fc3b1d,
-  0x57f7aac5, 0x57f31a36, 0x57ee8971, 0x57e9f876, 0x57e56744, 0x57e0d5dd,
-    0x57dc443f, 0x57d7b26b,
-  0x57d32061, 0x57ce8e20, 0x57c9fbaa, 0x57c568fd, 0x57c0d61a, 0x57bc4301,
-    0x57b7afb2, 0x57b31c2d,
-  0x57ae8872, 0x57a9f480, 0x57a56059, 0x57a0cbfb, 0x579c3768, 0x5797a29e,
-    0x57930d9e, 0x578e7869,
-  0x5789e2fd, 0x57854d5b, 0x5780b784, 0x577c2176, 0x57778b32, 0x5772f4b9,
-    0x576e5e09, 0x5769c724,
-  0x57653009, 0x576098b7, 0x575c0130, 0x57576973, 0x5752d180, 0x574e3957,
-    0x5749a0f9, 0x57450864,
-  0x57406f9a, 0x573bd69a, 0x57373d64, 0x5732a3f8, 0x572e0a56, 0x5729707f,
-    0x5724d672, 0x57203c2f,
-  0x571ba1b7, 0x57170708, 0x57126c24, 0x570dd10a, 0x570935bb, 0x57049a36,
-    0x56fffe7b, 0x56fb628b,
-  0x56f6c664, 0x56f22a09, 0x56ed8d77, 0x56e8f0b0, 0x56e453b4, 0x56dfb681,
-    0x56db1919, 0x56d67b7c,
-  0x56d1dda9, 0x56cd3fa1, 0x56c8a162, 0x56c402ef, 0x56bf6446, 0x56bac567,
-    0x56b62653, 0x56b18709,
-  0x56ace78a, 0x56a847d6, 0x56a3a7ec, 0x569f07cc, 0x569a6777, 0x5695c6ed,
-    0x5691262d, 0x568c8538,
-  0x5687e40e, 0x568342ae, 0x567ea118, 0x5679ff4e, 0x56755d4e, 0x5670bb19,
-    0x566c18ae, 0x5667760e,
-  0x5662d339, 0x565e302e, 0x56598cee, 0x5654e979, 0x565045cf, 0x564ba1f0,
-    0x5646fddb, 0x56425991,
-  0x563db512, 0x5639105d, 0x56346b74, 0x562fc655, 0x562b2101, 0x56267b78,
-    0x5621d5ba, 0x561d2fc6,
-  0x5618899e, 0x5613e340, 0x560f3cae, 0x560a95e6, 0x5605eee9, 0x560147b7,
-    0x55fca050, 0x55f7f8b4,
-  0x55f350e3, 0x55eea8dd, 0x55ea00a2, 0x55e55832, 0x55e0af8d, 0x55dc06b3,
-    0x55d75da4, 0x55d2b460,
-  0x55ce0ae7, 0x55c96139, 0x55c4b757, 0x55c00d3f, 0x55bb62f3, 0x55b6b871,
-    0x55b20dbb, 0x55ad62d0,
-  0x55a8b7b0, 0x55a40c5b, 0x559f60d1, 0x559ab513, 0x55960920, 0x55915cf8,
-    0x558cb09b, 0x55880409,
-  0x55835743, 0x557eaa48, 0x5579fd18, 0x55754fb3, 0x5570a21a, 0x556bf44c,
-    0x55674649, 0x55629812,
-  0x555de9a6, 0x55593b05, 0x55548c30, 0x554fdd26, 0x554b2de7, 0x55467e74,
-    0x5541cecc, 0x553d1ef0,
-  0x55386edf, 0x5533be99, 0x552f0e1f, 0x552a5d70, 0x5525ac8d, 0x5520fb75,
-    0x551c4a29, 0x551798a8,
-  0x5512e6f3, 0x550e3509, 0x550982eb, 0x5504d099, 0x55001e12, 0x54fb6b56,
-    0x54f6b866, 0x54f20542,
-  0x54ed51e9, 0x54e89e5c, 0x54e3ea9a, 0x54df36a5, 0x54da827a, 0x54d5ce1c,
-    0x54d11989, 0x54cc64c2,
-  0x54c7afc6, 0x54c2fa96, 0x54be4532, 0x54b98f9a, 0x54b4d9cd, 0x54b023cc,
-    0x54ab6d97, 0x54a6b72e,
-  0x54a20090, 0x549d49bf, 0x549892b9, 0x5493db7f, 0x548f2410, 0x548a6c6e,
-    0x5485b497, 0x5480fc8c,
-  0x547c444d, 0x54778bda, 0x5472d333, 0x546e1a58, 0x54696149, 0x5464a805,
-    0x545fee8e, 0x545b34e3,
-  0x54567b03, 0x5451c0f0, 0x544d06a8, 0x54484c2d, 0x5443917d, 0x543ed699,
-    0x543a1b82, 0x54356037,
-  0x5430a4b7, 0x542be904, 0x54272d1d, 0x54227102, 0x541db4b3, 0x5418f830,
-    0x54143b79, 0x540f7e8e,
-  0x540ac170, 0x5406041d, 0x54014697, 0x53fc88dd, 0x53f7caef, 0x53f30cce,
-    0x53ee4e78, 0x53e98fef,
-  0x53e4d132, 0x53e01242, 0x53db531d, 0x53d693c5, 0x53d1d439, 0x53cd147a,
-    0x53c85486, 0x53c3945f,
-  0x53bed405, 0x53ba1377, 0x53b552b5, 0x53b091bf, 0x53abd096, 0x53a70f39,
-    0x53a24da9, 0x539d8be5,
-  0x5398c9ed, 0x539407c2, 0x538f4564, 0x538a82d1, 0x5385c00c, 0x5380fd12,
-    0x537c39e6, 0x53777685,
-  0x5372b2f2, 0x536def2a, 0x53692b30, 0x53646701, 0x535fa2a0, 0x535ade0b,
-    0x53561942, 0x53515447,
-  0x534c8f17, 0x5347c9b5, 0x5343041f, 0x533e3e55, 0x53397859, 0x5334b229,
-    0x532febc5, 0x532b252f,
-  0x53265e65, 0x53219767, 0x531cd037, 0x531808d3, 0x5313413c, 0x530e7972,
-    0x5309b174, 0x5304e943,
-  0x530020df, 0x52fb5848, 0x52f68f7e, 0x52f1c680, 0x52ecfd4f, 0x52e833ec,
-    0x52e36a55, 0x52dea08a,
-  0x52d9d68d, 0x52d50c5d, 0x52d041f9, 0x52cb7763, 0x52c6ac99, 0x52c1e19d,
-    0x52bd166d, 0x52b84b0a,
-  0x52b37f74, 0x52aeb3ac, 0x52a9e7b0, 0x52a51b81, 0x52a04f1f, 0x529b828a,
-    0x5296b5c3, 0x5291e8c8,
-  0x528d1b9b, 0x52884e3a, 0x528380a7, 0x527eb2e0, 0x5279e4e7, 0x527516bb,
-    0x5270485c, 0x526b79ca,
-  0x5266ab06, 0x5261dc0e, 0x525d0ce4, 0x52583d87, 0x52536df7, 0x524e9e34,
-    0x5249ce3f, 0x5244fe17,
-  0x52402dbc, 0x523b5d2e, 0x52368c6e, 0x5231bb7b, 0x522cea55, 0x522818fc,
-    0x52234771, 0x521e75b3,
-  0x5219a3c3, 0x5214d1a0, 0x520fff4a, 0x520b2cc2, 0x52065a07, 0x52018719,
-    0x51fcb3f9, 0x51f7e0a6,
-  0x51f30d21, 0x51ee3969, 0x51e9657e, 0x51e49162, 0x51dfbd12, 0x51dae890,
-    0x51d613dc, 0x51d13ef5,
-  0x51cc69db, 0x51c79490, 0x51c2bf11, 0x51bde960, 0x51b9137d, 0x51b43d68,
-    0x51af6720, 0x51aa90a5,
-  0x51a5b9f9, 0x51a0e31a, 0x519c0c08, 0x519734c4, 0x51925d4e, 0x518d85a6,
-    0x5188adcb, 0x5183d5be,
-  0x517efd7f, 0x517a250d, 0x51754c69, 0x51707393, 0x516b9a8b, 0x5166c150,
-    0x5161e7e4, 0x515d0e45,
-  0x51583473, 0x51535a70, 0x514e803b, 0x5149a5d3, 0x5144cb39, 0x513ff06d,
-    0x513b156f, 0x51363a3f,
-  0x51315edd, 0x512c8348, 0x5127a782, 0x5122cb8a, 0x511def5f, 0x51191302,
-    0x51143674, 0x510f59b3,
-  0x510a7cc1, 0x51059f9c, 0x5100c246, 0x50fbe4bd, 0x50f70703, 0x50f22916,
-    0x50ed4af8, 0x50e86ca8,
-  0x50e38e25, 0x50deaf71, 0x50d9d08b, 0x50d4f173, 0x50d0122a, 0x50cb32ae,
-    0x50c65301, 0x50c17322,
-  0x50bc9311, 0x50b7b2ce, 0x50b2d259, 0x50adf1b3, 0x50a910db, 0x50a42fd1,
-    0x509f4e95, 0x509a6d28,
-  0x50958b88, 0x5090a9b8, 0x508bc7b5, 0x5086e581, 0x5082031b, 0x507d2083,
-    0x50783dba, 0x50735abf,
-  0x506e7793, 0x50699435, 0x5064b0a5, 0x505fcce4, 0x505ae8f1, 0x505604cd,
-    0x50512077, 0x504c3bef,
-  0x50475736, 0x5042724c, 0x503d8d30, 0x5038a7e2, 0x5033c263, 0x502edcb2,
-    0x5029f6d1, 0x502510bd,
-  0x50202a78, 0x501b4402, 0x50165d5a, 0x50117681, 0x500c8f77, 0x5007a83b,
-    0x5002c0cd, 0x4ffdd92f,
-  0x4ff8f15f, 0x4ff4095e, 0x4fef212b, 0x4fea38c7, 0x4fe55032, 0x4fe0676c,
-    0x4fdb7e74, 0x4fd6954b,
-  0x4fd1abf0, 0x4fccc265, 0x4fc7d8a8, 0x4fc2eeba, 0x4fbe049b, 0x4fb91a4b,
-    0x4fb42fc9, 0x4faf4517,
-  0x4faa5a33, 0x4fa56f1e, 0x4fa083d8, 0x4f9b9861, 0x4f96acb8, 0x4f91c0df,
-    0x4f8cd4d4, 0x4f87e899,
-  0x4f82fc2c, 0x4f7e0f8f, 0x4f7922c0, 0x4f7435c0, 0x4f6f488f, 0x4f6a5b2e,
-    0x4f656d9b, 0x4f607fd7,
-  0x4f5b91e3, 0x4f56a3bd, 0x4f51b566, 0x4f4cc6df, 0x4f47d827, 0x4f42e93d,
-    0x4f3dfa23, 0x4f390ad8,
-  0x4f341b5c, 0x4f2f2baf, 0x4f2a3bd2, 0x4f254bc3, 0x4f205b84, 0x4f1b6b14,
-    0x4f167a73, 0x4f1189a1,
-  0x4f0c989f, 0x4f07a76b, 0x4f02b608, 0x4efdc473, 0x4ef8d2ad, 0x4ef3e0b7,
-    0x4eeeee90, 0x4ee9fc39,
-  0x4ee509b1, 0x4ee016f8, 0x4edb240e, 0x4ed630f4, 0x4ed13da9, 0x4ecc4a2e,
-    0x4ec75682, 0x4ec262a5,
-  0x4ebd6e98, 0x4eb87a5a, 0x4eb385ec, 0x4eae914d, 0x4ea99c7d, 0x4ea4a77d,
-    0x4e9fb24d, 0x4e9abcec,
-  0x4e95c75b, 0x4e90d199, 0x4e8bdba6, 0x4e86e583, 0x4e81ef30, 0x4e7cf8ac,
-    0x4e7801f8, 0x4e730b14,
-  0x4e6e13ff, 0x4e691cba, 0x4e642544, 0x4e5f2d9e, 0x4e5a35c7, 0x4e553dc1,
-    0x4e50458a, 0x4e4b4d22,
-  0x4e46548b, 0x4e415bc3, 0x4e3c62cb, 0x4e3769a2, 0x4e32704a, 0x4e2d76c1,
-    0x4e287d08, 0x4e23831e,
-  0x4e1e8905, 0x4e198ebb, 0x4e149441, 0x4e0f9997, 0x4e0a9ebd, 0x4e05a3b2,
-    0x4e00a878, 0x4dfbad0d,
-  0x4df6b173, 0x4df1b5a8, 0x4decb9ad, 0x4de7bd82, 0x4de2c127, 0x4dddc49c,
-    0x4dd8c7e1, 0x4dd3caf6,
-  0x4dcecdda, 0x4dc9d08f, 0x4dc4d314, 0x4dbfd569, 0x4dbad78e, 0x4db5d983,
-    0x4db0db48, 0x4dabdcdd,
-  0x4da6de43, 0x4da1df78, 0x4d9ce07d, 0x4d97e153, 0x4d92e1f9, 0x4d8de26f,
-    0x4d88e2b5, 0x4d83e2cb,
-  0x4d7ee2b1, 0x4d79e268, 0x4d74e1ef, 0x4d6fe146, 0x4d6ae06d, 0x4d65df64,
-    0x4d60de2c, 0x4d5bdcc4,
-  0x4d56db2d, 0x4d51d965, 0x4d4cd76e, 0x4d47d547, 0x4d42d2f1, 0x4d3dd06b,
-    0x4d38cdb5, 0x4d33cad0,
-  0x4d2ec7bb, 0x4d29c476, 0x4d24c102, 0x4d1fbd5e, 0x4d1ab98b, 0x4d15b588,
-    0x4d10b155, 0x4d0bacf3,
-  0x4d06a862, 0x4d01a3a0, 0x4cfc9eb0, 0x4cf79990, 0x4cf29440, 0x4ced8ec1,
-    0x4ce88913, 0x4ce38335,
-  0x4cde7d28, 0x4cd976eb, 0x4cd4707f, 0x4ccf69e3, 0x4cca6318, 0x4cc55c1e,
-    0x4cc054f4, 0x4cbb4d9b,
-  0x4cb64613, 0x4cb13e5b, 0x4cac3674, 0x4ca72e5e, 0x4ca22619, 0x4c9d1da4,
-    0x4c981500, 0x4c930c2d,
-  0x4c8e032a, 0x4c88f9f8, 0x4c83f097, 0x4c7ee707, 0x4c79dd48, 0x4c74d359,
-    0x4c6fc93b, 0x4c6abeef,
-  0x4c65b473, 0x4c60a9c8, 0x4c5b9eed, 0x4c5693e4, 0x4c5188ac, 0x4c4c7d44,
-    0x4c4771ae, 0x4c4265e8,
-  0x4c3d59f3, 0x4c384dd0, 0x4c33417d, 0x4c2e34fb, 0x4c29284b, 0x4c241b6b,
-    0x4c1f0e5c, 0x4c1a011f,
-  0x4c14f3b2, 0x4c0fe617, 0x4c0ad84c, 0x4c05ca53, 0x4c00bc2b, 0x4bfbadd4,
-    0x4bf69f4e, 0x4bf19099,
-  0x4bec81b5, 0x4be772a3, 0x4be26362, 0x4bdd53f2, 0x4bd84453, 0x4bd33485,
-    0x4bce2488, 0x4bc9145d,
-  0x4bc40403, 0x4bbef37b, 0x4bb9e2c3, 0x4bb4d1dd, 0x4bafc0c8, 0x4baaaf85,
-    0x4ba59e12, 0x4ba08c72,
-  0x4b9b7aa2, 0x4b9668a4, 0x4b915677, 0x4b8c441c, 0x4b873192, 0x4b821ed9,
-    0x4b7d0bf2, 0x4b77f8dc,
-  0x4b72e598, 0x4b6dd225, 0x4b68be84, 0x4b63aab4, 0x4b5e96b6, 0x4b598289,
-    0x4b546e2d, 0x4b4f59a4,
-  0x4b4a44eb, 0x4b453005, 0x4b401aef, 0x4b3b05ac, 0x4b35f03a, 0x4b30da9a,
-    0x4b2bc4cb, 0x4b26aece,
-  0x4b2198a2, 0x4b1c8248, 0x4b176bc0, 0x4b12550a, 0x4b0d3e25, 0x4b082712,
-    0x4b030fd1, 0x4afdf861,
-  0x4af8e0c3, 0x4af3c8f7, 0x4aeeb0fd, 0x4ae998d4, 0x4ae4807d, 0x4adf67f8,
-    0x4ada4f45, 0x4ad53664,
-  0x4ad01d54, 0x4acb0417, 0x4ac5eaab, 0x4ac0d111, 0x4abbb749, 0x4ab69d53,
-    0x4ab1832f, 0x4aac68dc,
-  0x4aa74e5c, 0x4aa233ae, 0x4a9d18d1, 0x4a97fdc7, 0x4a92e28e, 0x4a8dc728,
-    0x4a88ab93, 0x4a838fd1,
-  0x4a7e73e0, 0x4a7957c2, 0x4a743b76, 0x4a6f1efc, 0x4a6a0253, 0x4a64e57d,
-    0x4a5fc879, 0x4a5aab48,
-  0x4a558de8, 0x4a50705a, 0x4a4b529f, 0x4a4634b6, 0x4a41169f, 0x4a3bf85a,
-    0x4a36d9e7, 0x4a31bb47,
-  0x4a2c9c79, 0x4a277d7d, 0x4a225e53, 0x4a1d3efc, 0x4a181f77, 0x4a12ffc4,
-    0x4a0ddfe4, 0x4a08bfd5,
-  0x4a039f9a, 0x49fe7f30, 0x49f95e99, 0x49f43dd4, 0x49ef1ce2, 0x49e9fbc2,
-    0x49e4da74, 0x49dfb8f9,
-  0x49da9750, 0x49d5757a, 0x49d05376, 0x49cb3145, 0x49c60ee6, 0x49c0ec59,
-    0x49bbc9a0, 0x49b6a6b8,
-  0x49b183a3, 0x49ac6061, 0x49a73cf1, 0x49a21954, 0x499cf589, 0x4997d191,
-    0x4992ad6c, 0x498d8919,
-  0x49886499, 0x49833fec, 0x497e1b11, 0x4978f609, 0x4973d0d3, 0x496eab70,
-    0x496985e0, 0x49646023,
-  0x495f3a38, 0x495a1420, 0x4954eddb, 0x494fc768, 0x494aa0c9, 0x494579fc,
-    0x49405302, 0x493b2bdb,
-  0x49360486, 0x4930dd05, 0x492bb556, 0x49268d7a, 0x49216571, 0x491c3d3b,
-    0x491714d8, 0x4911ec47,
-  0x490cc38a, 0x49079aa0, 0x49027188, 0x48fd4844, 0x48f81ed2, 0x48f2f534,
-    0x48edcb68, 0x48e8a170,
-  0x48e3774a, 0x48de4cf8, 0x48d92278, 0x48d3f7cc, 0x48ceccf3, 0x48c9a1ed,
-    0x48c476b9, 0x48bf4b59,
-  0x48ba1fcd, 0x48b4f413, 0x48afc82c, 0x48aa9c19, 0x48a56fd9, 0x48a0436c,
-    0x489b16d2, 0x4895ea0b,
-  0x4890bd18, 0x488b8ff8, 0x488662ab, 0x48813531, 0x487c078b, 0x4876d9b8,
-    0x4871abb8, 0x486c7d8c,
-  0x48674f33, 0x486220ad, 0x485cf1fa, 0x4857c31b, 0x48529410, 0x484d64d7,
-    0x48483572, 0x484305e1,
-  0x483dd623, 0x4838a638, 0x48337621, 0x482e45dd, 0x4829156d, 0x4823e4d0,
-    0x481eb407, 0x48198311,
-  0x481451ef, 0x480f20a0, 0x4809ef25, 0x4804bd7e, 0x47ff8baa, 0x47fa59a9,
-    0x47f5277d, 0x47eff523,
-  0x47eac29e, 0x47e58fec, 0x47e05d0e, 0x47db2a03, 0x47d5f6cc, 0x47d0c369,
-    0x47cb8fd9, 0x47c65c1d,
-  0x47c12835, 0x47bbf421, 0x47b6bfe0, 0x47b18b74, 0x47ac56da, 0x47a72215,
-    0x47a1ed24, 0x479cb806,
-  0x479782bc, 0x47924d46, 0x478d17a4, 0x4787e1d6, 0x4782abdb, 0x477d75b5,
-    0x47783f62, 0x477308e3,
-  0x476dd239, 0x47689b62, 0x4763645f, 0x475e2d30, 0x4758f5d5, 0x4753be4e,
-    0x474e869b, 0x47494ebc,
-  0x474416b1, 0x473ede7a, 0x4739a617, 0x47346d89, 0x472f34ce, 0x4729fbe7,
-    0x4724c2d5, 0x471f8996,
-  0x471a502c, 0x47151696, 0x470fdcd4, 0x470aa2e6, 0x470568cd, 0x47002e87,
-    0x46faf416, 0x46f5b979,
-  0x46f07eb0, 0x46eb43bc, 0x46e6089b, 0x46e0cd4f, 0x46db91d8, 0x46d65634,
-    0x46d11a65, 0x46cbde6a,
-  0x46c6a244, 0x46c165f1, 0x46bc2974, 0x46b6ecca, 0x46b1aff5, 0x46ac72f4,
-    0x46a735c8, 0x46a1f870,
-  0x469cbaed, 0x46977d3e, 0x46923f63, 0x468d015d, 0x4687c32c, 0x468284cf,
-    0x467d4646, 0x46780792,
-  0x4672c8b3, 0x466d89a8, 0x46684a71, 0x46630b0f, 0x465dcb82, 0x46588bc9,
-    0x46534be5, 0x464e0bd6,
-  0x4648cb9b, 0x46438b35, 0x463e4aa3, 0x463909e7, 0x4633c8fe, 0x462e87eb,
-    0x462946ac, 0x46240542,
-  0x461ec3ad, 0x461981ec, 0x46144001, 0x460efde9, 0x4609bba7, 0x4604793a,
-    0x45ff36a1, 0x45f9f3dd,
-  0x45f4b0ee, 0x45ef6dd4, 0x45ea2a8f, 0x45e4e71f, 0x45dfa383, 0x45da5fbc,
-    0x45d51bcb, 0x45cfd7ae,
-  0x45ca9366, 0x45c54ef3, 0x45c00a55, 0x45bac58c, 0x45b58098, 0x45b03b79,
-    0x45aaf630, 0x45a5b0bb,
-  0x45a06b1b, 0x459b2550, 0x4595df5a, 0x45909939, 0x458b52ee, 0x45860c77,
-    0x4580c5d6, 0x457b7f0a,
-  0x45763813, 0x4570f0f1, 0x456ba9a4, 0x4566622c, 0x45611a8a, 0x455bd2bc,
-    0x45568ac4, 0x455142a2,
-  0x454bfa54, 0x4546b1dc, 0x45416939, 0x453c206b, 0x4536d773, 0x45318e4f,
-    0x452c4502, 0x4526fb89,
-  0x4521b1e6, 0x451c6818, 0x45171e20, 0x4511d3fd, 0x450c89af, 0x45073f37,
-    0x4501f494, 0x44fca9c6,
-  0x44f75ecf, 0x44f213ac, 0x44ecc85f, 0x44e77ce7, 0x44e23145, 0x44dce579,
-    0x44d79982, 0x44d24d60,
-  0x44cd0114, 0x44c7b49e, 0x44c267fd, 0x44bd1b32, 0x44b7ce3c, 0x44b2811c,
-    0x44ad33d2, 0x44a7e65d,
-  0x44a298be, 0x449d4af5, 0x4497fd01, 0x4492aee3, 0x448d609b, 0x44881228,
-    0x4482c38b, 0x447d74c4,
-  0x447825d2, 0x4472d6b7, 0x446d8771, 0x44683801, 0x4462e866, 0x445d98a2,
-    0x445848b3, 0x4452f89b,
-  0x444da858, 0x444857ea, 0x44430753, 0x443db692, 0x443865a7, 0x44331491,
-    0x442dc351, 0x442871e8,
-  0x44232054, 0x441dce96, 0x44187caf, 0x44132a9d, 0x440dd861, 0x440885fc,
-    0x4403336c, 0x43fde0b2,
-  0x43f88dcf, 0x43f33ac1, 0x43ede78a, 0x43e89429, 0x43e3409d, 0x43ddece8,
-    0x43d8990a, 0x43d34501,
-  0x43cdf0ce, 0x43c89c72, 0x43c347eb, 0x43bdf33b, 0x43b89e62, 0x43b3495e,
-    0x43adf431, 0x43a89ed9,
-  0x43a34959, 0x439df3ae, 0x43989dda, 0x439347dc, 0x438df1b4, 0x43889b63,
-    0x438344e8, 0x437dee43,
-  0x43789775, 0x4373407d, 0x436de95b, 0x43689210, 0x43633a9c, 0x435de2fd,
-    0x43588b36, 0x43533344,
-  0x434ddb29, 0x434882e5, 0x43432a77, 0x433dd1e0, 0x4338791f, 0x43332035,
-    0x432dc721, 0x43286de4,
-  0x4323147d, 0x431dbaed, 0x43186133, 0x43130751, 0x430dad44, 0x4308530f,
-    0x4302f8b0, 0x42fd9e28,
-  0x42f84376, 0x42f2e89b, 0x42ed8d97, 0x42e83269, 0x42e2d713, 0x42dd7b93,
-    0x42d81fe9, 0x42d2c417,
-  0x42cd681b, 0x42c80bf6, 0x42c2afa8, 0x42bd5331, 0x42b7f690, 0x42b299c7,
-    0x42ad3cd4, 0x42a7dfb8,
-  0x42a28273, 0x429d2505, 0x4297c76e, 0x429269ae, 0x428d0bc4, 0x4287adb2,
-    0x42824f76, 0x427cf112,
-  0x42779285, 0x427233ce, 0x426cd4ef, 0x426775e6, 0x426216b5, 0x425cb75a,
-    0x425757d7, 0x4251f82b,
-  0x424c9856, 0x42473858, 0x4241d831, 0x423c77e1, 0x42371769, 0x4231b6c7,
-    0x422c55fd, 0x4226f50a,
-  0x422193ee, 0x421c32a9, 0x4216d13c, 0x42116fa5, 0x420c0de6, 0x4206abfe,
-    0x420149ee, 0x41fbe7b5,
-  0x41f68553, 0x41f122c8, 0x41ebc015, 0x41e65d39, 0x41e0fa35, 0x41db9707,
-    0x41d633b1, 0x41d0d033,
-  0x41cb6c8c, 0x41c608bc, 0x41c0a4c4, 0x41bb40a3, 0x41b5dc5a, 0x41b077e8,
-    0x41ab134e, 0x41a5ae8b,
-  0x41a049a0, 0x419ae48c, 0x41957f4f, 0x419019eb, 0x418ab45d, 0x41854ea8,
-    0x417fe8ca, 0x417a82c3,
-  0x41751c94, 0x416fb63d, 0x416a4fbd, 0x4164e916, 0x415f8245, 0x415a1b4d,
-    0x4154b42c, 0x414f4ce2,
-  0x4149e571, 0x41447dd7, 0x413f1615, 0x4139ae2b, 0x41344618, 0x412edddd,
-    0x4129757b, 0x41240cef,
-  0x411ea43c, 0x41193b61, 0x4113d25d, 0x410e6931, 0x4108ffdd, 0x41039661,
-    0x40fe2cbd, 0x40f8c2f1,
-  0x40f358fc, 0x40edeee0, 0x40e8849b, 0x40e31a2f, 0x40ddaf9b, 0x40d844de,
-    0x40d2d9f9, 0x40cd6eed,
-  0x40c803b8, 0x40c2985c, 0x40bd2cd8, 0x40b7c12b, 0x40b25557, 0x40ace95b,
-    0x40a77d37, 0x40a210eb,
-  0x409ca477, 0x409737dc, 0x4091cb18, 0x408c5e2d, 0x4086f11a, 0x408183df,
-    0x407c167c, 0x4076a8f1,
-  0x40713b3f, 0x406bcd65, 0x40665f63, 0x4060f13a, 0x405b82e9, 0x40561470,
-    0x4050a5cf, 0x404b3707,
-  0x4045c817, 0x404058ff, 0x403ae9c0, 0x40357a59, 0x40300acb, 0x402a9b15,
-    0x40252b37, 0x401fbb32,
-  0x401a4b05, 0x4014dab1, 0x400f6a35, 0x4009f992, 0x400488c7, 0x3fff17d5,
-    0x3ff9a6bb, 0x3ff4357a,
-  0x3feec411, 0x3fe95281, 0x3fe3e0c9, 0x3fde6eeb, 0x3fd8fce4, 0x3fd38ab6,
-    0x3fce1861, 0x3fc8a5e5,
-  0x3fc33341, 0x3fbdc076, 0x3fb84d83, 0x3fb2da6a, 0x3fad6729, 0x3fa7f3c0,
-    0x3fa28031, 0x3f9d0c7a,
-  0x3f97989c, 0x3f922496, 0x3f8cb06a, 0x3f873c16, 0x3f81c79b, 0x3f7c52f9,
-    0x3f76de30, 0x3f71693f,
-  0x3f6bf428, 0x3f667ee9, 0x3f610983, 0x3f5b93f6, 0x3f561e42, 0x3f50a867,
-    0x3f4b3265, 0x3f45bc3c,
-  0x3f4045ec, 0x3f3acf75, 0x3f3558d7, 0x3f2fe211, 0x3f2a6b25, 0x3f24f412,
-    0x3f1f7cd8, 0x3f1a0577,
-  0x3f148def, 0x3f0f1640, 0x3f099e6b, 0x3f04266e, 0x3efeae4a, 0x3ef93600,
-    0x3ef3bd8f, 0x3eee44f7,
-  0x3ee8cc38, 0x3ee35352, 0x3eddda46, 0x3ed86113, 0x3ed2e7b9, 0x3ecd6e38,
-    0x3ec7f491, 0x3ec27ac2,
-  0x3ebd00cd, 0x3eb786b2, 0x3eb20c6f, 0x3eac9206, 0x3ea71777, 0x3ea19cc1,
-    0x3e9c21e4, 0x3e96a6e0,
-  0x3e912bb6, 0x3e8bb065, 0x3e8634ee, 0x3e80b950, 0x3e7b3d8c, 0x3e75c1a1,
-    0x3e70458f, 0x3e6ac957,
-  0x3e654cf8, 0x3e5fd073, 0x3e5a53c8, 0x3e54d6f6, 0x3e4f59fe, 0x3e49dcdf,
-    0x3e445f99, 0x3e3ee22e,
-  0x3e39649c, 0x3e33e6e3, 0x3e2e6904, 0x3e28eaff, 0x3e236cd4, 0x3e1dee82,
-    0x3e18700a, 0x3e12f16b,
-  0x3e0d72a6, 0x3e07f3bb, 0x3e0274aa, 0x3dfcf572, 0x3df77615, 0x3df1f691,
-    0x3dec76e6, 0x3de6f716,
-  0x3de1771f, 0x3ddbf703, 0x3dd676c0, 0x3dd0f656, 0x3dcb75c7, 0x3dc5f512,
-    0x3dc07436, 0x3dbaf335,
-  0x3db5720d, 0x3daff0c0, 0x3daa6f4c, 0x3da4edb2, 0x3d9f6bf2, 0x3d99ea0d,
-    0x3d946801, 0x3d8ee5cf,
-  0x3d896377, 0x3d83e0f9, 0x3d7e5e56, 0x3d78db8c, 0x3d73589d, 0x3d6dd587,
-    0x3d68524c, 0x3d62ceeb,
-  0x3d5d4b64, 0x3d57c7b7, 0x3d5243e4, 0x3d4cbfeb, 0x3d473bcd, 0x3d41b789,
-    0x3d3c331f, 0x3d36ae8f,
-  0x3d3129da, 0x3d2ba4fe, 0x3d261ffd, 0x3d209ad7, 0x3d1b158a, 0x3d159018,
-    0x3d100a80, 0x3d0a84c3,
-  0x3d04fee0, 0x3cff78d7, 0x3cf9f2a9, 0x3cf46c55, 0x3ceee5db, 0x3ce95f3c,
-    0x3ce3d877, 0x3cde518d,
-  0x3cd8ca7d, 0x3cd34347, 0x3ccdbbed, 0x3cc8346c, 0x3cc2acc6, 0x3cbd24fb,
-    0x3cb79d0a, 0x3cb214f4,
-  0x3cac8cb8, 0x3ca70457, 0x3ca17bd0, 0x3c9bf324, 0x3c966a53, 0x3c90e15c,
-    0x3c8b5840, 0x3c85cefe,
-  0x3c804598, 0x3c7abc0c, 0x3c75325a, 0x3c6fa883, 0x3c6a1e87, 0x3c649466,
-    0x3c5f0a20, 0x3c597fb4,
-  0x3c53f523, 0x3c4e6a6d, 0x3c48df91, 0x3c435491, 0x3c3dc96b, 0x3c383e20,
-    0x3c32b2b0, 0x3c2d271b,
-  0x3c279b61, 0x3c220f81, 0x3c1c837d, 0x3c16f753, 0x3c116b04, 0x3c0bde91,
-    0x3c0651f8, 0x3c00c53a,
-  0x3bfb3857, 0x3bf5ab50, 0x3bf01e23, 0x3bea90d1, 0x3be5035a, 0x3bdf75bf,
-    0x3bd9e7fe, 0x3bd45a19,
-  0x3bcecc0e, 0x3bc93ddf, 0x3bc3af8b, 0x3bbe2112, 0x3bb89274, 0x3bb303b1,
-    0x3bad74c9, 0x3ba7e5bd,
-  0x3ba2568c, 0x3b9cc736, 0x3b9737bb, 0x3b91a81c, 0x3b8c1857, 0x3b86886e,
-    0x3b80f861, 0x3b7b682e,
-  0x3b75d7d7, 0x3b70475c, 0x3b6ab6bb, 0x3b6525f6, 0x3b5f950c, 0x3b5a03fe,
-    0x3b5472cb, 0x3b4ee173,
-  0x3b494ff7, 0x3b43be57, 0x3b3e2c91, 0x3b389aa8, 0x3b330899, 0x3b2d7666,
-    0x3b27e40f, 0x3b225193,
-  0x3b1cbef3, 0x3b172c2e, 0x3b119945, 0x3b0c0637, 0x3b067305, 0x3b00dfaf,
-    0x3afb4c34, 0x3af5b894,
-  0x3af024d1, 0x3aea90e9, 0x3ae4fcdc, 0x3adf68ac, 0x3ad9d457, 0x3ad43fdd,
-    0x3aceab40, 0x3ac9167e,
-  0x3ac38198, 0x3abdec8d, 0x3ab8575f, 0x3ab2c20c, 0x3aad2c95, 0x3aa796fa,
-    0x3aa2013a, 0x3a9c6b57,
-  0x3a96d54f, 0x3a913f23, 0x3a8ba8d3, 0x3a86125f, 0x3a807bc7, 0x3a7ae50a,
-    0x3a754e2a, 0x3a6fb726,
-  0x3a6a1ffd, 0x3a6488b1, 0x3a5ef140, 0x3a5959ab, 0x3a53c1f3, 0x3a4e2a16,
-    0x3a489216, 0x3a42f9f2,
-  0x3a3d61a9, 0x3a37c93d, 0x3a3230ad, 0x3a2c97f9, 0x3a26ff21, 0x3a216625,
-    0x3a1bcd05, 0x3a1633c1,
-  0x3a109a5a, 0x3a0b00cf, 0x3a056720, 0x39ffcd4d, 0x39fa3356, 0x39f4993c,
-    0x39eefefe, 0x39e9649c,
-  0x39e3ca17, 0x39de2f6d, 0x39d894a0, 0x39d2f9b0, 0x39cd5e9b, 0x39c7c363,
-    0x39c22808, 0x39bc8c89,
-  0x39b6f0e6, 0x39b1551f, 0x39abb935, 0x39a61d28, 0x39a080f6, 0x399ae4a2,
-    0x39954829, 0x398fab8e,
-  0x398a0ece, 0x398471ec, 0x397ed4e5, 0x397937bc, 0x39739a6e, 0x396dfcfe,
-    0x39685f6a, 0x3962c1b2,
-  0x395d23d7, 0x395785d9, 0x3951e7b8, 0x394c4973, 0x3946ab0a, 0x39410c7f,
-    0x393b6dd0, 0x3935cefd,
-  0x39303008, 0x392a90ef, 0x3924f1b3, 0x391f5254, 0x3919b2d1, 0x3914132b,
-    0x390e7362, 0x3908d376,
-  0x39033367, 0x38fd9334, 0x38f7f2de, 0x38f25266, 0x38ecb1ca, 0x38e7110a,
-    0x38e17028, 0x38dbcf23,
-  0x38d62dfb, 0x38d08caf, 0x38caeb41, 0x38c549af, 0x38bfa7fb, 0x38ba0623,
-    0x38b46429, 0x38aec20b,
-  0x38a91fcb, 0x38a37d67, 0x389ddae1, 0x38983838, 0x3892956c, 0x388cf27d,
-    0x38874f6b, 0x3881ac36,
-  0x387c08de, 0x38766564, 0x3870c1c6, 0x386b1e06, 0x38657a23, 0x385fd61d,
-    0x385a31f5, 0x38548daa,
-  0x384ee93b, 0x384944ab, 0x38439ff7, 0x383dfb21, 0x38385628, 0x3832b10d,
-    0x382d0bce, 0x3827666d,
-  0x3821c0ea, 0x381c1b44, 0x3816757b, 0x3810cf90, 0x380b2982, 0x38058351,
-    0x37ffdcfe, 0x37fa3688,
-  0x37f48ff0, 0x37eee936, 0x37e94259, 0x37e39b59, 0x37ddf437, 0x37d84cf2,
-    0x37d2a58b, 0x37ccfe02,
-  0x37c75656, 0x37c1ae87, 0x37bc0697, 0x37b65e84, 0x37b0b64e, 0x37ab0df6,
-    0x37a5657c, 0x379fbce0,
-  0x379a1421, 0x37946b40, 0x378ec23d, 0x37891917, 0x37836fcf, 0x377dc665,
-    0x37781cd9, 0x3772732a,
-  0x376cc959, 0x37671f66, 0x37617551, 0x375bcb1a, 0x375620c1, 0x37507645,
-    0x374acba7, 0x374520e7,
-  0x373f7606, 0x3739cb02, 0x37341fdc, 0x372e7493, 0x3728c929, 0x37231d9d,
-    0x371d71ef, 0x3717c61f,
-  0x37121a2d, 0x370c6e19, 0x3706c1e2, 0x3701158a, 0x36fb6910, 0x36f5bc75,
-    0x36f00fb7, 0x36ea62d7,
-  0x36e4b5d6, 0x36df08b2, 0x36d95b6d, 0x36d3ae06, 0x36ce007d, 0x36c852d2,
-    0x36c2a506, 0x36bcf718,
-  0x36b74908, 0x36b19ad6, 0x36abec82, 0x36a63e0d, 0x36a08f76, 0x369ae0bd,
-    0x369531e3, 0x368f82e7,
-  0x3689d3c9, 0x3684248a, 0x367e7529, 0x3678c5a7, 0x36731602, 0x366d663d,
-    0x3667b655, 0x3662064c,
-  0x365c5622, 0x3656a5d6, 0x3650f569, 0x364b44da, 0x36459429, 0x363fe357,
-    0x363a3264, 0x3634814f,
-  0x362ed019, 0x36291ec1, 0x36236d48, 0x361dbbad, 0x361809f1, 0x36125814,
-    0x360ca615, 0x3606f3f5,
-  0x360141b4, 0x35fb8f52, 0x35f5dcce, 0x35f02a28, 0x35ea7762, 0x35e4c47a,
-    0x35df1171, 0x35d95e47,
-  0x35d3aafc, 0x35cdf78f, 0x35c84401, 0x35c29052, 0x35bcdc82, 0x35b72891,
-    0x35b1747e, 0x35abc04b,
-  0x35a60bf6, 0x35a05781, 0x359aa2ea, 0x3594ee32, 0x358f3959, 0x3589845f,
-    0x3583cf44, 0x357e1a08,
-  0x357864ab, 0x3572af2d, 0x356cf98e, 0x356743ce, 0x35618ded, 0x355bd7eb,
-    0x355621c9, 0x35506b85,
-  0x354ab520, 0x3544fe9b, 0x353f47f5, 0x3539912e, 0x3533da46, 0x352e233d,
-    0x35286c14, 0x3522b4c9,
-  0x351cfd5e, 0x351745d2, 0x35118e26, 0x350bd658, 0x35061e6a, 0x3500665c,
-    0x34faae2c, 0x34f4f5dc,
-  0x34ef3d6b, 0x34e984da, 0x34e3cc28, 0x34de1355, 0x34d85a62, 0x34d2a14e,
-    0x34cce819, 0x34c72ec4,
-  0x34c1754e, 0x34bbbbb8, 0x34b60202, 0x34b0482a, 0x34aa8e33, 0x34a4d41a,
-    0x349f19e2, 0x34995f88,
-  0x3493a50f, 0x348dea75, 0x34882fba, 0x348274e0, 0x347cb9e4, 0x3476fec9,
-    0x3471438d, 0x346b8830,
-  0x3465ccb4, 0x34601117, 0x345a5559, 0x3454997c, 0x344edd7e, 0x34492160,
-    0x34436521, 0x343da8c3,
-  0x3437ec44, 0x34322fa5, 0x342c72e6, 0x3426b606, 0x3420f907, 0x341b3be7,
-    0x34157ea7, 0x340fc147,
-  0x340a03c7, 0x34044626, 0x33fe8866, 0x33f8ca86, 0x33f30c85, 0x33ed4e65,
-    0x33e79024, 0x33e1d1c4,
-  0x33dc1343, 0x33d654a2, 0x33d095e2, 0x33cad701, 0x33c51801, 0x33bf58e1,
-    0x33b999a0, 0x33b3da40,
-  0x33ae1ac0, 0x33a85b20, 0x33a29b60, 0x339cdb81, 0x33971b81, 0x33915b62,
-    0x338b9b22, 0x3385dac4,
-  0x33801a45, 0x337a59a6, 0x337498e8, 0x336ed80a, 0x3369170c, 0x336355ef,
-    0x335d94b2, 0x3357d355,
-  0x335211d8, 0x334c503c, 0x33468e80, 0x3340cca5, 0x333b0aaa, 0x3335488f,
-    0x332f8655, 0x3329c3fb,
-  0x33240182, 0x331e3ee9, 0x33187c31, 0x3312b959, 0x330cf661, 0x3307334a,
-    0x33017014, 0x32fbacbe,
-  0x32f5e948, 0x32f025b4, 0x32ea61ff, 0x32e49e2c, 0x32deda39, 0x32d91626,
-    0x32d351f5, 0x32cd8da4,
-  0x32c7c933, 0x32c204a3, 0x32bc3ff4, 0x32b67b26, 0x32b0b638, 0x32aaf12b,
-    0x32a52bff, 0x329f66b4,
-  0x3299a149, 0x3293dbbf, 0x328e1616, 0x3288504e, 0x32828a67, 0x327cc460,
-    0x3276fe3a, 0x327137f6,
-  0x326b7192, 0x3265ab0f, 0x325fe46c, 0x325a1dab, 0x325456cb, 0x324e8fcc,
-    0x3248c8ad, 0x32430170,
-  0x323d3a14, 0x32377298, 0x3231aafe, 0x322be345, 0x32261b6c, 0x32205375,
-    0x321a8b5f, 0x3214c32a,
-  0x320efad6, 0x32093263, 0x320369d2, 0x31fda121, 0x31f7d852, 0x31f20f64,
-    0x31ec4657, 0x31e67d2b,
-  0x31e0b3e0, 0x31daea77, 0x31d520ef, 0x31cf5748, 0x31c98d83, 0x31c3c39e,
-    0x31bdf99b, 0x31b82f7a,
-  0x31b2653a, 0x31ac9adb, 0x31a6d05d, 0x31a105c1, 0x319b3b06, 0x3195702d,
-    0x318fa535, 0x3189da1e,
-  0x31840ee9, 0x317e4395, 0x31787823, 0x3172ac92, 0x316ce0e3, 0x31671515,
-    0x31614929, 0x315b7d1e,
-  0x3155b0f5, 0x314fe4ae, 0x314a1848, 0x31444bc3, 0x313e7f21, 0x3138b260,
-    0x3132e580, 0x312d1882,
-  0x31274b66, 0x31217e2c, 0x311bb0d3, 0x3115e35c, 0x311015c6, 0x310a4813,
-    0x31047a41, 0x30feac51,
-  0x30f8de42, 0x30f31016, 0x30ed41cb, 0x30e77362, 0x30e1a4db, 0x30dbd636,
-    0x30d60772, 0x30d03891,
-  0x30ca6991, 0x30c49a74, 0x30becb38, 0x30b8fbde, 0x30b32c66, 0x30ad5cd0,
-    0x30a78d1c, 0x30a1bd4a,
-  0x309bed5a, 0x30961d4c, 0x30904d20, 0x308a7cd6, 0x3084ac6e, 0x307edbe9,
-    0x30790b45, 0x30733a83,
-  0x306d69a4, 0x306798a7, 0x3061c78b, 0x305bf652, 0x305624fb, 0x30505387,
-    0x304a81f4, 0x3044b044,
-  0x303ede76, 0x30390c8a, 0x30333a80, 0x302d6859, 0x30279614, 0x3021c3b1,
-    0x301bf131, 0x30161e93,
-  0x30104bd7, 0x300a78fe, 0x3004a607, 0x2ffed2f2, 0x2ff8ffc0, 0x2ff32c70,
-    0x2fed5902, 0x2fe78577,
-  0x2fe1b1cf, 0x2fdbde09, 0x2fd60a25, 0x2fd03624, 0x2fca6206, 0x2fc48dc9,
-    0x2fbeb970, 0x2fb8e4f9,
-  0x2fb31064, 0x2fad3bb3, 0x2fa766e3, 0x2fa191f7, 0x2f9bbced, 0x2f95e7c5,
-    0x2f901280, 0x2f8a3d1e,
-  0x2f84679f, 0x2f7e9202, 0x2f78bc48, 0x2f72e671, 0x2f6d107c, 0x2f673a6a,
-    0x2f61643b, 0x2f5b8def,
-  0x2f55b785, 0x2f4fe0ff, 0x2f4a0a5b, 0x2f44339a, 0x2f3e5cbb, 0x2f3885c0,
-    0x2f32aea8, 0x2f2cd772,
-  0x2f27001f, 0x2f2128af, 0x2f1b5122, 0x2f157979, 0x2f0fa1b2, 0x2f09c9ce,
-    0x2f03f1cd, 0x2efe19ae,
-  0x2ef84173, 0x2ef2691b, 0x2eec90a7, 0x2ee6b815, 0x2ee0df66, 0x2edb069a,
-    0x2ed52db1, 0x2ecf54ac,
-  0x2ec97b89, 0x2ec3a24a, 0x2ebdc8ee, 0x2eb7ef75, 0x2eb215df, 0x2eac3c2d,
-    0x2ea6625d, 0x2ea08871,
-  0x2e9aae68, 0x2e94d443, 0x2e8efa00, 0x2e891fa1, 0x2e834525, 0x2e7d6a8d,
-    0x2e778fd8, 0x2e71b506,
-  0x2e6bda17, 0x2e65ff0c, 0x2e6023e5, 0x2e5a48a0, 0x2e546d3f, 0x2e4e91c2,
-    0x2e48b628, 0x2e42da71,
-  0x2e3cfe9e, 0x2e3722ae, 0x2e3146a2, 0x2e2b6a79, 0x2e258e34, 0x2e1fb1d3,
-    0x2e19d554, 0x2e13f8ba,
-  0x2e0e1c03, 0x2e083f30, 0x2e026240, 0x2dfc8534, 0x2df6a80b, 0x2df0cac6,
-    0x2deaed65, 0x2de50fe8,
-  0x2ddf324e, 0x2dd95498, 0x2dd376c5, 0x2dcd98d7, 0x2dc7bacc, 0x2dc1dca4,
-    0x2dbbfe61, 0x2db62001,
-  0x2db04186, 0x2daa62ee, 0x2da4843a, 0x2d9ea569, 0x2d98c67d, 0x2d92e774,
-    0x2d8d084f, 0x2d87290f,
-  0x2d8149b2, 0x2d7b6a39, 0x2d758aa4, 0x2d6faaf3, 0x2d69cb26, 0x2d63eb3d,
-    0x2d5e0b38, 0x2d582b17,
-  0x2d524ada, 0x2d4c6a81, 0x2d468a0c, 0x2d40a97b, 0x2d3ac8ce, 0x2d34e805,
-    0x2d2f0721, 0x2d292620,
-  0x2d234504, 0x2d1d63cc, 0x2d178278, 0x2d11a108, 0x2d0bbf7d, 0x2d05ddd5,
-    0x2cfffc12, 0x2cfa1a33,
-  0x2cf43839, 0x2cee5622, 0x2ce873f0, 0x2ce291a2, 0x2cdcaf39, 0x2cd6ccb4,
-    0x2cd0ea13, 0x2ccb0756,
-  0x2cc5247e, 0x2cbf418b, 0x2cb95e7b, 0x2cb37b51, 0x2cad980a, 0x2ca7b4a8,
-    0x2ca1d12a, 0x2c9bed91,
-  0x2c9609dd, 0x2c90260d, 0x2c8a4221, 0x2c845e1a, 0x2c7e79f7, 0x2c7895b9,
-    0x2c72b160, 0x2c6ccceb,
-  0x2c66e85b, 0x2c6103af, 0x2c5b1ee8, 0x2c553a06, 0x2c4f5508, 0x2c496fef,
-    0x2c438abb, 0x2c3da56b,
-  0x2c37c000, 0x2c31da7a, 0x2c2bf4d8, 0x2c260f1c, 0x2c202944, 0x2c1a4351,
-    0x2c145d42, 0x2c0e7719,
-  0x2c0890d4, 0x2c02aa74, 0x2bfcc3f9, 0x2bf6dd63, 0x2bf0f6b1, 0x2beb0fe5,
-    0x2be528fd, 0x2bdf41fb,
-  0x2bd95add, 0x2bd373a4, 0x2bcd8c51, 0x2bc7a4e2, 0x2bc1bd58, 0x2bbbd5b3,
-    0x2bb5edf4, 0x2bb00619,
-  0x2baa1e23, 0x2ba43613, 0x2b9e4de7, 0x2b9865a1, 0x2b927d3f, 0x2b8c94c3,
-    0x2b86ac2c, 0x2b80c37a,
-  0x2b7adaae, 0x2b74f1c6, 0x2b6f08c4, 0x2b691fa6, 0x2b63366f, 0x2b5d4d1c,
-    0x2b5763ae, 0x2b517a26,
-  0x2b4b9083, 0x2b45a6c6, 0x2b3fbced, 0x2b39d2fa, 0x2b33e8ed, 0x2b2dfec5,
-    0x2b281482, 0x2b222a24,
-  0x2b1c3fac, 0x2b165519, 0x2b106a6c, 0x2b0a7fa4, 0x2b0494c2, 0x2afea9c5,
-    0x2af8bead, 0x2af2d37b,
-  0x2aece82f, 0x2ae6fcc8, 0x2ae11146, 0x2adb25aa, 0x2ad539f4, 0x2acf4e23,
-    0x2ac96238, 0x2ac37633,
-  0x2abd8a13, 0x2ab79dd8, 0x2ab1b184, 0x2aabc515, 0x2aa5d88b, 0x2a9febe8,
-    0x2a99ff2a, 0x2a941252,
-  0x2a8e255f, 0x2a883853, 0x2a824b2c, 0x2a7c5deb, 0x2a76708f, 0x2a70831a,
-    0x2a6a958a, 0x2a64a7e0,
-  0x2a5eba1c, 0x2a58cc3e, 0x2a52de46, 0x2a4cf033, 0x2a470207, 0x2a4113c0,
-    0x2a3b2560, 0x2a3536e5,
-  0x2a2f4850, 0x2a2959a1, 0x2a236ad9, 0x2a1d7bf6, 0x2a178cf9, 0x2a119de2,
-    0x2a0baeb2, 0x2a05bf67,
-  0x29ffd003, 0x29f9e084, 0x29f3f0ec, 0x29ee013a, 0x29e8116e, 0x29e22188,
-    0x29dc3188, 0x29d6416f,
-  0x29d0513b, 0x29ca60ee, 0x29c47087, 0x29be8007, 0x29b88f6c, 0x29b29eb8,
-    0x29acadea, 0x29a6bd02,
-  0x29a0cc01, 0x299adae6, 0x2994e9b1, 0x298ef863, 0x298906fb, 0x2983157a,
-    0x297d23df, 0x2977322a,
-  0x2971405b, 0x296b4e74, 0x29655c72, 0x295f6a57, 0x29597823, 0x295385d5,
-    0x294d936d, 0x2947a0ec,
-  0x2941ae52, 0x293bbb9e, 0x2935c8d1, 0x292fd5ea, 0x2929e2ea, 0x2923efd0,
-    0x291dfc9d, 0x29180951,
-  0x291215eb, 0x290c226c, 0x29062ed4, 0x29003b23, 0x28fa4758, 0x28f45374,
-    0x28ee5f76, 0x28e86b5f,
-  0x28e27730, 0x28dc82e6, 0x28d68e84, 0x28d09a09, 0x28caa574, 0x28c4b0c6,
-    0x28bebbff, 0x28b8c71f,
-  0x28b2d226, 0x28acdd13, 0x28a6e7e8, 0x28a0f2a3, 0x289afd46, 0x289507cf,
-    0x288f123f, 0x28891c97,
-  0x288326d5, 0x287d30fa, 0x28773b07, 0x287144fa, 0x286b4ed5, 0x28655896,
-    0x285f623f, 0x28596bce,
-  0x28537545, 0x284d7ea3, 0x284787e8, 0x28419114, 0x283b9a28, 0x2835a322,
-    0x282fac04, 0x2829b4cd,
-  0x2823bd7d, 0x281dc615, 0x2817ce93, 0x2811d6f9, 0x280bdf46, 0x2805e77b,
-    0x27ffef97, 0x27f9f79a,
-  0x27f3ff85, 0x27ee0756, 0x27e80f10, 0x27e216b0, 0x27dc1e38, 0x27d625a8,
-    0x27d02cff, 0x27ca343d,
-  0x27c43b63, 0x27be4270, 0x27b84965, 0x27b25041, 0x27ac5705, 0x27a65db0,
-    0x27a06443, 0x279a6abd,
-  0x2794711f, 0x278e7768, 0x27887d99, 0x278283b2, 0x277c89b3, 0x27768f9b,
-    0x2770956a, 0x276a9b21,
-  0x2764a0c0, 0x275ea647, 0x2758abb6, 0x2752b10c, 0x274cb64a, 0x2746bb6f,
-    0x2740c07d, 0x273ac572,
-  0x2734ca4f, 0x272ecf14, 0x2728d3c0, 0x2722d855, 0x271cdcd1, 0x2716e136,
-    0x2710e582, 0x270ae9b6,
-  0x2704edd2, 0x26fef1d5, 0x26f8f5c1, 0x26f2f995, 0x26ecfd51, 0x26e700f5,
-    0x26e10480, 0x26db07f4,
-  0x26d50b50, 0x26cf0e94, 0x26c911c0, 0x26c314d4, 0x26bd17d0, 0x26b71ab4,
-    0x26b11d80, 0x26ab2034,
-  0x26a522d1, 0x269f2556, 0x269927c3, 0x26932a18, 0x268d2c55, 0x26872e7b,
-    0x26813088, 0x267b327e,
-  0x2675345d, 0x266f3623, 0x266937d2, 0x26633969, 0x265d3ae9, 0x26573c50,
-    0x26513da1, 0x264b3ed9,
-  0x26453ffa, 0x263f4103, 0x263941f5, 0x263342cf, 0x262d4392, 0x2627443d,
-    0x262144d0, 0x261b454c,
-  0x261545b0, 0x260f45fd, 0x26094633, 0x26034651, 0x25fd4657, 0x25f74646,
-    0x25f1461e, 0x25eb45de,
-  0x25e54587, 0x25df4519, 0x25d94493, 0x25d343f6, 0x25cd4341, 0x25c74276,
-    0x25c14192, 0x25bb4098,
-  0x25b53f86, 0x25af3e5d, 0x25a93d1d, 0x25a33bc6, 0x259d3a57, 0x259738d1,
-    0x25913734, 0x258b3580,
-  0x258533b5, 0x257f31d2, 0x25792fd8, 0x25732dc8, 0x256d2ba0, 0x25672961,
-    0x2561270b, 0x255b249e,
-  0x2555221a, 0x254f1f7e, 0x25491ccc, 0x25431a03, 0x253d1723, 0x2537142c,
-    0x2531111e, 0x252b0df9,
-  0x25250abd, 0x251f076a, 0x25190400, 0x25130080, 0x250cfce8, 0x2506f93a,
-    0x2500f574, 0x24faf198,
-  0x24f4eda6, 0x24eee99c, 0x24e8e57c, 0x24e2e144, 0x24dcdcf6, 0x24d6d892,
-    0x24d0d416, 0x24cacf84,
-  0x24c4cadb, 0x24bec61c, 0x24b8c146, 0x24b2bc59, 0x24acb756, 0x24a6b23b,
-    0x24a0ad0b, 0x249aa7c4,
-  0x2494a266, 0x248e9cf1, 0x24889766, 0x248291c5, 0x247c8c0d, 0x2476863e,
-    0x24708059, 0x246a7a5e,
-  0x2464744c, 0x245e6e23, 0x245867e4, 0x2452618f, 0x244c5b24, 0x244654a1,
-    0x24404e09, 0x243a475a,
-  0x24344095, 0x242e39ba, 0x242832c8, 0x24222bc0, 0x241c24a1, 0x24161d6d,
-    0x24101622, 0x240a0ec1,
-  0x24040749, 0x23fdffbc, 0x23f7f818, 0x23f1f05e, 0x23ebe88e, 0x23e5e0a7,
-    0x23dfd8ab, 0x23d9d098,
-  0x23d3c86f, 0x23cdc031, 0x23c7b7dc, 0x23c1af71, 0x23bba6f0, 0x23b59e59,
-    0x23af95ac, 0x23a98ce8,
-  0x23a3840f, 0x239d7b20, 0x2397721b, 0x23916900, 0x238b5fcf, 0x23855688,
-    0x237f4d2b, 0x237943b9,
-  0x23733a30, 0x236d3092, 0x236726dd, 0x23611d13, 0x235b1333, 0x2355093e,
-    0x234eff32, 0x2348f511,
-  0x2342eada, 0x233ce08d, 0x2336d62a, 0x2330cbb2, 0x232ac124, 0x2324b680,
-    0x231eabc7, 0x2318a0f8,
-  0x23129613, 0x230c8b19, 0x23068009, 0x230074e3, 0x22fa69a8, 0x22f45e57,
-    0x22ee52f1, 0x22e84775,
-  0x22e23be4, 0x22dc303d, 0x22d62480, 0x22d018ae, 0x22ca0cc7, 0x22c400ca,
-    0x22bdf4b8, 0x22b7e890,
-  0x22b1dc53, 0x22abd001, 0x22a5c399, 0x229fb71b, 0x2299aa89, 0x22939de1,
-    0x228d9123, 0x22878451,
-  0x22817769, 0x227b6a6c, 0x22755d59, 0x226f5032, 0x226942f5, 0x226335a2,
-    0x225d283b, 0x22571abe,
-  0x22510d2d, 0x224aff86, 0x2244f1c9, 0x223ee3f8, 0x2238d612, 0x2232c816,
-    0x222cba06, 0x2226abe0,
-  0x22209da5, 0x221a8f56, 0x221480f1, 0x220e7277, 0x220863e8, 0x22025544,
-    0x21fc468b, 0x21f637be,
-  0x21f028db, 0x21ea19e3, 0x21e40ad7, 0x21ddfbb5, 0x21d7ec7f, 0x21d1dd34,
-    0x21cbcdd3, 0x21c5be5e,
-  0x21bfaed5, 0x21b99f36, 0x21b38f83, 0x21ad7fba, 0x21a76fdd, 0x21a15fec,
-    0x219b4fe5, 0x21953fca,
-  0x218f2f9a, 0x21891f55, 0x21830efc, 0x217cfe8e, 0x2176ee0b, 0x2170dd74,
-    0x216accc8, 0x2164bc08,
-  0x215eab33, 0x21589a49, 0x2152894b, 0x214c7838, 0x21466710, 0x214055d4,
-    0x213a4484, 0x2134331f,
-  0x212e21a6, 0x21281018, 0x2121fe76, 0x211becbf, 0x2115daf4, 0x210fc914,
-    0x2109b720, 0x2103a518,
-  0x20fd92fb, 0x20f780ca, 0x20f16e84, 0x20eb5c2b, 0x20e549bd, 0x20df373a,
-    0x20d924a4, 0x20d311f9,
-  0x20ccff3a, 0x20c6ec66, 0x20c0d97f, 0x20bac683, 0x20b4b373, 0x20aea04f,
-    0x20a88d17, 0x20a279ca,
-  0x209c666a, 0x209652f5, 0x20903f6c, 0x208a2bcf, 0x2084181e, 0x207e0459,
-    0x2077f080, 0x2071dc93,
-  0x206bc892, 0x2065b47d, 0x205fa054, 0x20598c17, 0x205377c6, 0x204d6361,
-    0x20474ee8, 0x20413a5b,
-  0x203b25bb, 0x20351106, 0x202efc3e, 0x2028e761, 0x2022d271, 0x201cbd6d,
-    0x2016a856, 0x2010932a,
-  0x200a7deb, 0x20046898, 0x1ffe5331, 0x1ff83db6, 0x1ff22828, 0x1fec1286,
-    0x1fe5fcd0, 0x1fdfe707,
-  0x1fd9d12a, 0x1fd3bb39, 0x1fcda535, 0x1fc78f1d, 0x1fc178f1, 0x1fbb62b2,
-    0x1fb54c60, 0x1faf35f9,
-  0x1fa91f80, 0x1fa308f2, 0x1f9cf252, 0x1f96db9d, 0x1f90c4d5, 0x1f8aadfa,
-    0x1f84970b, 0x1f7e8009,
-  0x1f7868f4, 0x1f7251ca, 0x1f6c3a8e, 0x1f66233e, 0x1f600bdb, 0x1f59f465,
-    0x1f53dcdb, 0x1f4dc53d,
-  0x1f47ad8d, 0x1f4195c9, 0x1f3b7df2, 0x1f356608, 0x1f2f4e0a, 0x1f2935f9,
-    0x1f231dd5, 0x1f1d059e,
-  0x1f16ed54, 0x1f10d4f6, 0x1f0abc85, 0x1f04a401, 0x1efe8b6a, 0x1ef872c0,
-    0x1ef25a03, 0x1eec4132,
-  0x1ee6284f, 0x1ee00f58, 0x1ed9f64f, 0x1ed3dd32, 0x1ecdc402, 0x1ec7aac0,
-    0x1ec1916a, 0x1ebb7802,
-  0x1eb55e86, 0x1eaf44f8, 0x1ea92b56, 0x1ea311a2, 0x1e9cf7db, 0x1e96de01,
-    0x1e90c414, 0x1e8aaa14,
-  0x1e849001, 0x1e7e75dc, 0x1e785ba3, 0x1e724158, 0x1e6c26fa, 0x1e660c8a,
-    0x1e5ff206, 0x1e59d770,
-  0x1e53bcc7, 0x1e4da20c, 0x1e47873d, 0x1e416c5d, 0x1e3b5169, 0x1e353663,
-    0x1e2f1b4a, 0x1e29001e,
-  0x1e22e4e0, 0x1e1cc990, 0x1e16ae2c, 0x1e1092b6, 0x1e0a772e, 0x1e045b93,
-    0x1dfe3fe6, 0x1df82426,
-  0x1df20853, 0x1debec6f, 0x1de5d077, 0x1ddfb46e, 0x1dd99851, 0x1dd37c23,
-    0x1dcd5fe2, 0x1dc7438e,
-  0x1dc12729, 0x1dbb0ab0, 0x1db4ee26, 0x1daed189, 0x1da8b4da, 0x1da29819,
-    0x1d9c7b45, 0x1d965e5f,
-  0x1d904167, 0x1d8a245c, 0x1d840740, 0x1d7dea11, 0x1d77ccd0, 0x1d71af7d,
-    0x1d6b9217, 0x1d6574a0,
-  0x1d5f5716, 0x1d59397a, 0x1d531bcc, 0x1d4cfe0d, 0x1d46e03a, 0x1d40c256,
-    0x1d3aa460, 0x1d348658,
-  0x1d2e683e, 0x1d284a12, 0x1d222bd3, 0x1d1c0d83, 0x1d15ef21, 0x1d0fd0ad,
-    0x1d09b227, 0x1d03938f,
-  0x1cfd74e5, 0x1cf7562a, 0x1cf1375c, 0x1ceb187d, 0x1ce4f98c, 0x1cdeda89,
-    0x1cd8bb74, 0x1cd29c4d,
-  0x1ccc7d15, 0x1cc65dca, 0x1cc03e6e, 0x1cba1f01, 0x1cb3ff81, 0x1caddff0,
-    0x1ca7c04d, 0x1ca1a099,
-  0x1c9b80d3, 0x1c9560fb, 0x1c8f4112, 0x1c892117, 0x1c83010a, 0x1c7ce0ec,
-    0x1c76c0bc, 0x1c70a07b,
-  0x1c6a8028, 0x1c645fc3, 0x1c5e3f4d, 0x1c581ec6, 0x1c51fe2d, 0x1c4bdd83,
-    0x1c45bcc7, 0x1c3f9bf9,
-  0x1c397b1b, 0x1c335a2b, 0x1c2d3929, 0x1c271816, 0x1c20f6f2, 0x1c1ad5bc,
-    0x1c14b475, 0x1c0e931d,
-  0x1c0871b4, 0x1c025039, 0x1bfc2ead, 0x1bf60d0f, 0x1befeb60, 0x1be9c9a1,
-    0x1be3a7cf, 0x1bdd85ed,
-  0x1bd763fa, 0x1bd141f5, 0x1bcb1fdf, 0x1bc4fdb8, 0x1bbedb80, 0x1bb8b937,
-    0x1bb296dc, 0x1bac7471,
-  0x1ba651f5, 0x1ba02f67, 0x1b9a0cc8, 0x1b93ea19, 0x1b8dc758, 0x1b87a487,
-    0x1b8181a4, 0x1b7b5eb0,
-  0x1b753bac, 0x1b6f1897, 0x1b68f570, 0x1b62d239, 0x1b5caef1, 0x1b568b98,
-    0x1b50682e, 0x1b4a44b3,
-  0x1b442127, 0x1b3dfd8b, 0x1b37d9de, 0x1b31b620, 0x1b2b9251, 0x1b256e71,
-    0x1b1f4a81, 0x1b192680,
-  0x1b13026e, 0x1b0cde4c, 0x1b06ba19, 0x1b0095d5, 0x1afa7180, 0x1af44d1b,
-    0x1aee28a6, 0x1ae8041f,
-  0x1ae1df88, 0x1adbbae1, 0x1ad59629, 0x1acf7160, 0x1ac94c87, 0x1ac3279d,
-    0x1abd02a3, 0x1ab6dd98,
-  0x1ab0b87d, 0x1aaa9352, 0x1aa46e16, 0x1a9e48c9, 0x1a98236c, 0x1a91fdff,
-    0x1a8bd881, 0x1a85b2f3,
-  0x1a7f8d54, 0x1a7967a6, 0x1a7341e6, 0x1a6d1c17, 0x1a66f637, 0x1a60d047,
-    0x1a5aaa47, 0x1a548436,
-  0x1a4e5e15, 0x1a4837e4, 0x1a4211a3, 0x1a3beb52, 0x1a35c4f0, 0x1a2f9e7e,
-    0x1a2977fc, 0x1a23516a,
-  0x1a1d2ac8, 0x1a170416, 0x1a10dd53, 0x1a0ab681, 0x1a048f9e, 0x19fe68ac,
-    0x19f841a9, 0x19f21a96,
-  0x19ebf374, 0x19e5cc41, 0x19dfa4fe, 0x19d97dac, 0x19d35649, 0x19cd2ed7,
-    0x19c70754, 0x19c0dfc2,
-  0x19bab820, 0x19b4906e, 0x19ae68ac, 0x19a840da, 0x19a218f9, 0x199bf107,
-    0x1995c906, 0x198fa0f5,
-  0x198978d4, 0x198350a4, 0x197d2864, 0x19770014, 0x1970d7b4, 0x196aaf45,
-    0x196486c6, 0x195e5e37,
-  0x19583599, 0x19520ceb, 0x194be42d, 0x1945bb60, 0x193f9283, 0x19396997,
-    0x1933409b, 0x192d178f,
-  0x1926ee74, 0x1920c54a, 0x191a9c10, 0x191472c6, 0x190e496d, 0x19082005,
-    0x1901f68d, 0x18fbcd06,
-  0x18f5a36f, 0x18ef79c9, 0x18e95014, 0x18e3264f, 0x18dcfc7b, 0x18d6d297,
-    0x18d0a8a4, 0x18ca7ea2,
-  0x18c45491, 0x18be2a70, 0x18b80040, 0x18b1d601, 0x18ababb2, 0x18a58154,
-    0x189f56e8, 0x18992c6b,
-  0x189301e0, 0x188cd746, 0x1886ac9c, 0x188081e4, 0x187a571c, 0x18742c45,
-    0x186e015f, 0x1867d66a,
-  0x1861ab66, 0x185b8053, 0x18555530, 0x184f29ff, 0x1848febf, 0x1842d370,
-    0x183ca812, 0x18367ca5,
-  0x18305129, 0x182a259e, 0x1823fa04, 0x181dce5b, 0x1817a2a4, 0x181176dd,
-    0x180b4b08, 0x18051f24,
-  0x17fef331, 0x17f8c72f, 0x17f29b1e, 0x17ec6eff, 0x17e642d1, 0x17e01694,
-    0x17d9ea49, 0x17d3bdee,
-  0x17cd9186, 0x17c7650e, 0x17c13888, 0x17bb0bf3, 0x17b4df4f, 0x17aeb29d,
-    0x17a885dc, 0x17a2590d,
-  0x179c2c2f, 0x1795ff42, 0x178fd247, 0x1789a53d, 0x17837825, 0x177d4afe,
-    0x17771dc9, 0x1770f086,
-  0x176ac333, 0x176495d3, 0x175e6864, 0x17583ae7, 0x17520d5b, 0x174bdfc1,
-    0x1745b218, 0x173f8461,
-  0x1739569c, 0x173328c8, 0x172cfae6, 0x1726ccf6, 0x17209ef8, 0x171a70eb,
-    0x171442d0, 0x170e14a7,
-  0x1707e670, 0x1701b82a, 0x16fb89d6, 0x16f55b74, 0x16ef2d04, 0x16e8fe86,
-    0x16e2cff9, 0x16dca15f,
-  0x16d672b6, 0x16d043ff, 0x16ca153a, 0x16c3e667, 0x16bdb787, 0x16b78898,
-    0x16b1599b, 0x16ab2a90,
-  0x16a4fb77, 0x169ecc50, 0x16989d1b, 0x16926dd8, 0x168c3e87, 0x16860f29,
-    0x167fdfbc, 0x1679b042,
-  0x167380ba, 0x166d5123, 0x1667217f, 0x1660f1ce, 0x165ac20e, 0x16549241,
-    0x164e6266, 0x1648327d,
-  0x16420286, 0x163bd282, 0x1635a270, 0x162f7250, 0x16294222, 0x162311e7,
-    0x161ce19e, 0x1616b148,
-  0x161080e4, 0x160a5072, 0x16041ff3, 0x15fdef66, 0x15f7becc, 0x15f18e24,
-    0x15eb5d6e, 0x15e52cab,
-  0x15defbdb, 0x15d8cafd, 0x15d29a11, 0x15cc6918, 0x15c63812, 0x15c006fe,
-    0x15b9d5dd, 0x15b3a4ae,
-  0x15ad7372, 0x15a74228, 0x15a110d2, 0x159adf6e, 0x1594adfc, 0x158e7c7d,
-    0x15884af1, 0x15821958,
-  0x157be7b1, 0x1575b5fe, 0x156f843c, 0x1569526e, 0x15632093, 0x155ceeaa,
-    0x1556bcb4, 0x15508ab1,
-  0x154a58a1, 0x15442683, 0x153df459, 0x1537c221, 0x15318fdd, 0x152b5d8b,
-    0x15252b2c, 0x151ef8c0,
-  0x1518c648, 0x151293c2, 0x150c612f, 0x15062e8f, 0x14fffbe2, 0x14f9c928,
-    0x14f39662, 0x14ed638e,
-  0x14e730ae, 0x14e0fdc0, 0x14dacac6, 0x14d497bf, 0x14ce64ab, 0x14c8318a,
-    0x14c1fe5c, 0x14bbcb22,
-  0x14b597da, 0x14af6486, 0x14a93125, 0x14a2fdb8, 0x149cca3e, 0x149696b7,
-    0x14906323, 0x148a2f82,
-  0x1483fbd5, 0x147dc81c, 0x14779455, 0x14716082, 0x146b2ca3, 0x1464f8b7,
-    0x145ec4be, 0x145890b9,
-  0x14525ca7, 0x144c2888, 0x1445f45d, 0x143fc026, 0x14398be2, 0x14335792,
-    0x142d2335, 0x1426eecb,
-  0x1420ba56, 0x141a85d3, 0x14145145, 0x140e1caa, 0x1407e803, 0x1401b34f,
-    0x13fb7e8f, 0x13f549c3,
-  0x13ef14ea, 0x13e8e005, 0x13e2ab14, 0x13dc7616, 0x13d6410d, 0x13d00bf7,
-    0x13c9d6d4, 0x13c3a1a6,
-  0x13bd6c6b, 0x13b73725, 0x13b101d2, 0x13aacc73, 0x13a49707, 0x139e6190,
-    0x13982c0d, 0x1391f67d,
-  0x138bc0e1, 0x13858b3a, 0x137f5586, 0x13791fc6, 0x1372e9fb, 0x136cb423,
-    0x13667e3f, 0x13604850,
-  0x135a1254, 0x1353dc4c, 0x134da639, 0x1347701a, 0x134139ee, 0x133b03b7,
-    0x1334cd74, 0x132e9725,
-  0x132860ca, 0x13222a64, 0x131bf3f2, 0x1315bd73, 0x130f86ea, 0x13095054,
-    0x130319b3, 0x12fce305,
-  0x12f6ac4d, 0x12f07588, 0x12ea3eb8, 0x12e407dc, 0x12ddd0f4, 0x12d79a01,
-    0x12d16303, 0x12cb2bf8,
-  0x12c4f4e2, 0x12bebdc1, 0x12b88693, 0x12b24f5b, 0x12ac1817, 0x12a5e0c7,
-    0x129fa96c, 0x12997205,
-  0x12933a93, 0x128d0315, 0x1286cb8c, 0x128093f7, 0x127a5c57, 0x127424ac,
-    0x126decf5, 0x1267b533,
-  0x12617d66, 0x125b458d, 0x12550da9, 0x124ed5ba, 0x12489dbf, 0x124265b9,
-    0x123c2da8, 0x1235f58b,
-  0x122fbd63, 0x12298530, 0x12234cf2, 0x121d14a9, 0x1216dc54, 0x1210a3f5,
-    0x120a6b8a, 0x12043314,
-  0x11fdfa93, 0x11f7c207, 0x11f18970, 0x11eb50cd, 0x11e51820, 0x11dedf68,
-    0x11d8a6a4, 0x11d26dd6,
-  0x11cc34fc, 0x11c5fc18, 0x11bfc329, 0x11b98a2e, 0x11b35129, 0x11ad1819,
-    0x11a6defe, 0x11a0a5d8,
-  0x119a6ca7, 0x1194336b, 0x118dfa25, 0x1187c0d3, 0x11818777, 0x117b4e10,
-    0x1175149e, 0x116edb22,
-  0x1168a19b, 0x11626809, 0x115c2e6c, 0x1155f4c4, 0x114fbb12, 0x11498156,
-    0x1143478e, 0x113d0dbc,
-  0x1136d3df, 0x113099f8, 0x112a6006, 0x11242609, 0x111dec02, 0x1117b1f0,
-    0x111177d4, 0x110b3dad,
-  0x1105037c, 0x10fec940, 0x10f88efa, 0x10f254a9, 0x10ec1a4e, 0x10e5dfe8,
-    0x10dfa578, 0x10d96afe,
-  0x10d33079, 0x10ccf5ea, 0x10c6bb50, 0x10c080ac, 0x10ba45fe, 0x10b40b45,
-    0x10add082, 0x10a795b5,
-  0x10a15ade, 0x109b1ffc, 0x1094e510, 0x108eaa1a, 0x10886f19, 0x1082340f,
-    0x107bf8fa, 0x1075bddb,
-  0x106f82b2, 0x1069477f, 0x10630c41, 0x105cd0fa, 0x105695a8, 0x10505a4d,
-    0x104a1ee7, 0x1043e377,
-  0x103da7fd, 0x10376c79, 0x103130ec, 0x102af554, 0x1024b9b2, 0x101e7e06,
-    0x10184251, 0x10120691,
-  0x100bcac7, 0x10058ef4, 0xfff5317, 0xff91730, 0xff2db3e, 0xfec9f44,
-    0xfe6633f, 0xfe02730,
-  0xfd9eb18, 0xfd3aef6, 0xfcd72ca, 0xfc73695, 0xfc0fa55, 0xfbabe0c, 0xfb481ba,
-    0xfae455d,
-  0xfa808f7, 0xfa1cc87, 0xf9b900e, 0xf95538b, 0xf8f16fe, 0xf88da68, 0xf829dc8,
-    0xf7c611f,
-  0xf76246c, 0xf6fe7af, 0xf69aae9, 0xf636e1a, 0xf5d3141, 0xf56f45e, 0xf50b773,
-    0xf4a7a7d,
-  0xf443d7e, 0xf3e0076, 0xf37c365, 0xf318649, 0xf2b4925, 0xf250bf7, 0xf1ecec0,
-    0xf189180,
-  0xf125436, 0xf0c16e3, 0xf05d987, 0xeff9c21, 0xef95eb2, 0xef3213a, 0xeece3b9,
-    0xee6a62f,
-  0xee0689b, 0xeda2afe, 0xed3ed58, 0xecdafa9, 0xec771f1, 0xec1342f, 0xebaf665,
-    0xeb4b891,
-  0xeae7ab4, 0xea83ccf, 0xea1fee0, 0xe9bc0e8, 0xe9582e7, 0xe8f44dd, 0xe8906cb,
-    0xe82c8af,
-  0xe7c8a8a, 0xe764c5c, 0xe700e26, 0xe69cfe6, 0xe63919e, 0xe5d534d, 0xe5714f3,
-    0xe50d690,
-  0xe4a9824, 0xe4459af, 0xe3e1b32, 0xe37dcac, 0xe319e1d, 0xe2b5f85, 0xe2520e5,
-    0xe1ee23c,
-  0xe18a38a, 0xe1264cf, 0xe0c260c, 0xe05e740, 0xdffa86b, 0xdf9698e, 0xdf32aa8,
-    0xdecebba,
-  0xde6acc3, 0xde06dc3, 0xdda2ebb, 0xdd3efab, 0xdcdb091, 0xdc77170, 0xdc13245,
-    0xdbaf313,
-  0xdb4b3d7, 0xdae7494, 0xda83548, 0xda1f5f3, 0xd9bb696, 0xd957731, 0xd8f37c3,
-    0xd88f84d,
-  0xd82b8cf, 0xd7c7948, 0xd7639b9, 0xd6ffa22, 0xd69ba82, 0xd637ada, 0xd5d3b2a,
-    0xd56fb71,
-  0xd50bbb1, 0xd4a7be8, 0xd443c17, 0xd3dfc3e, 0xd37bc5c, 0xd317c73, 0xd2b3c81,
-    0xd24fc87,
-  0xd1ebc85, 0xd187c7b, 0xd123c69, 0xd0bfc4f, 0xd05bc2d, 0xcff7c02, 0xcf93bd0,
-    0xcf2fb96,
-  0xcecbb53, 0xce67b09, 0xce03ab7, 0xcd9fa5d, 0xcd3b9fb, 0xccd7991, 0xcc7391f,
-    0xcc0f8a5,
-  0xcbab824, 0xcb4779a, 0xcae3709, 0xca7f670, 0xca1b5cf, 0xc9b7526, 0xc953475,
-    0xc8ef3bd,
-  0xc88b2fd, 0xc827235, 0xc7c3166, 0xc75f08f, 0xc6fafb0, 0xc696ec9, 0xc632ddb,
-    0xc5cece5,
-  0xc56abe8, 0xc506ae3, 0xc4a29d6, 0xc43e8c2, 0xc3da7a6, 0xc376683, 0xc312558,
-    0xc2ae425,
-  0xc24a2eb, 0xc1e61aa, 0xc182061, 0xc11df11, 0xc0b9db9, 0xc055c5a, 0xbff1af3,
-    0xbf8d985,
-  0xbf29810, 0xbec5693, 0xbe6150f, 0xbdfd383, 0xbd991f0, 0xbd35056, 0xbcd0eb5,
-    0xbc6cd0c,
-  0xbc08b5c, 0xbba49a5, 0xbb407e7, 0xbadc621, 0xba78454, 0xba14280, 0xb9b00a5,
-    0xb94bec2,
-  0xb8e7cd9, 0xb883ae8, 0xb81f8f0, 0xb7bb6f2, 0xb7574ec, 0xb6f32df, 0xb68f0cb,
-    0xb62aeaf,
-  0xb5c6c8d, 0xb562a64, 0xb4fe834, 0xb49a5fd, 0xb4363bf, 0xb3d217a, 0xb36df2e,
-    0xb309cdb,
-  0xb2a5a81, 0xb241820, 0xb1dd5b9, 0xb17934b, 0xb1150d5, 0xb0b0e59, 0xb04cbd6,
-    0xafe894d,
-  0xaf846bc, 0xaf20425, 0xaebc187, 0xae57ee2, 0xadf3c37, 0xad8f985, 0xad2b6cc,
-    0xacc740c,
-  0xac63146, 0xabfee79, 0xab9aba6, 0xab368cc, 0xaad25eb, 0xaa6e304, 0xaa0a016,
-    0xa9a5d22,
-  0xa941a27, 0xa8dd725, 0xa87941d, 0xa81510f, 0xa7b0dfa, 0xa74cadf, 0xa6e87bd,
-    0xa684495,
-  0xa620166, 0xa5bbe31, 0xa557af5, 0xa4f37b3, 0xa48f46b, 0xa42b11d, 0xa3c6dc8,
-    0xa362a6d,
-  0xa2fe70b, 0xa29a3a3, 0xa236035, 0xa1d1cc1, 0xa16d946, 0xa1095c6, 0xa0a523f,
-    0xa040eb1,
-  0x9fdcb1e, 0x9f78784, 0x9f143e5, 0x9eb003f, 0x9e4bc93, 0x9de78e1, 0x9d83529,
-    0x9d1f16b,
-  0x9cbada7, 0x9c569dc, 0x9bf260c, 0x9b8e236, 0x9b29e59, 0x9ac5a77, 0x9a6168f,
-    0x99fd2a0,
-  0x9998eac, 0x9934ab2, 0x98d06b2, 0x986c2ac, 0x9807ea1, 0x97a3a8f, 0x973f678,
-    0x96db25a,
-  0x9676e37, 0x9612a0e, 0x95ae5e0, 0x954a1ab, 0x94e5d71, 0x9481931, 0x941d4eb,
-    0x93b90a0,
-  0x9354c4f, 0x92f07f8, 0x928c39b, 0x9227f39, 0x91c3ad2, 0x915f664, 0x90fb1f1,
-    0x9096d79,
-  0x90328fb, 0x8fce477, 0x8f69fee, 0x8f05b5f, 0x8ea16cb, 0x8e3d231, 0x8dd8d92,
-    0x8d748ed,
-  0x8d10443, 0x8cabf93, 0x8c47ade, 0x8be3624, 0x8b7f164, 0x8b1ac9f, 0x8ab67d4,
-    0x8a52304,
-  0x89ede2f, 0x8989955, 0x8925475, 0x88c0f90, 0x885caa5, 0x87f85b5, 0x87940c1,
-    0x872fbc6,
-  0x86cb6c7, 0x86671c2, 0x8602cb9, 0x859e7aa, 0x853a296, 0x84d5d7d, 0x847185e,
-    0x840d33b,
-  0x83a8e12, 0x83448e5, 0x82e03b2, 0x827be7a, 0x821793e, 0x81b33fc, 0x814eeb5,
-    0x80ea969,
-  0x8086419, 0x8021ec3, 0x7fbd968, 0x7f59409, 0x7ef4ea4, 0x7e9093b, 0x7e2c3cd,
-    0x7dc7e5a,
-  0x7d638e2, 0x7cff365, 0x7c9ade4, 0x7c3685d, 0x7bd22d2, 0x7b6dd42, 0x7b097ad,
-    0x7aa5214,
-  0x7a40c76, 0x79dc6d3, 0x797812b, 0x7913b7f, 0x78af5ce, 0x784b019, 0x77e6a5e,
-    0x77824a0,
-  0x771dedc, 0x76b9914, 0x7655347, 0x75f0d76, 0x758c7a1, 0x75281c6, 0x74c3be7,
-    0x745f604,
-  0x73fb01c, 0x7396a30, 0x733243f, 0x72cde4a, 0x7269851, 0x7205253, 0x71a0c50,
-    0x713c64a,
-  0x70d803f, 0x7073a2f, 0x700f41b, 0x6faae03, 0x6f467e7, 0x6ee21c6, 0x6e7dba1,
-    0x6e19578,
-  0x6db4f4a, 0x6d50919, 0x6cec2e3, 0x6c87ca9, 0x6c2366a, 0x6bbf028, 0x6b5a9e1,
-    0x6af6396,
-  0x6a91d47, 0x6a2d6f4, 0x69c909d, 0x6964a42, 0x69003e3, 0x689bd80, 0x6837718,
-    0x67d30ad,
-  0x676ea3d, 0x670a3ca, 0x66a5d53, 0x66416d8, 0x65dd058, 0x65789d5, 0x651434e,
-    0x64afcc3,
-  0x644b634, 0x63e6fa2, 0x638290b, 0x631e271, 0x62b9bd3, 0x6255531, 0x61f0e8b,
-    0x618c7e1,
-  0x6128134, 0x60c3a83, 0x605f3ce, 0x5ffad15, 0x5f96659, 0x5f31f99, 0x5ecd8d6,
-    0x5e6920e,
-  0x5e04b43, 0x5da0475, 0x5d3bda3, 0x5cd76cd, 0x5c72ff4, 0x5c0e917, 0x5baa237,
-    0x5b45b53,
-  0x5ae146b, 0x5a7cd80, 0x5a18692, 0x59b3fa0, 0x594f8aa, 0x58eb1b2, 0x5886ab5,
-    0x58223b6,
-  0x57bdcb3, 0x57595ac, 0x56f4ea2, 0x5690795, 0x562c085, 0x55c7971, 0x556325a,
-    0x54feb3f,
-  0x549a422, 0x5435d01, 0x53d15dd, 0x536ceb5, 0x530878a, 0x52a405d, 0x523f92c,
-    0x51db1f7,
-  0x5176ac0, 0x5112385, 0x50adc48, 0x5049507, 0x4fe4dc3, 0x4f8067c, 0x4f1bf32,
-    0x4eb77e5,
-  0x4e53095, 0x4dee942, 0x4d8a1ec, 0x4d25a93, 0x4cc1337, 0x4c5cbd8, 0x4bf8476,
-    0x4b93d11,
-  0x4b2f5a9, 0x4acae3e, 0x4a666d1, 0x4a01f60, 0x499d7ed, 0x4939077, 0x48d48fe,
-    0x4870182,
-  0x480ba04, 0x47a7282, 0x4742afe, 0x46de377, 0x4679bee, 0x4615461, 0x45b0cd2,
-    0x454c541,
-  0x44e7dac, 0x4483615, 0x441ee7c, 0x43ba6df, 0x4355f40, 0x42f179f, 0x428cffb,
-    0x4228854,
-  0x41c40ab, 0x415f8ff, 0x40fb151, 0x40969a0, 0x40321ed, 0x3fcda37, 0x3f6927f,
-    0x3f04ac4,
-  0x3ea0307, 0x3e3bb48, 0x3dd7386, 0x3d72bc2, 0x3d0e3fb, 0x3ca9c32, 0x3c45467,
-    0x3be0c99,
-  0x3b7c4c9, 0x3b17cf7, 0x3ab3523, 0x3a4ed4c, 0x39ea573, 0x3985d97, 0x39215ba,
-    0x38bcdda,
-  0x38585f8, 0x37f3e14, 0x378f62e, 0x372ae46, 0x36c665b, 0x3661e6f, 0x35fd680,
-    0x3598e8f,
-  0x353469c, 0x34cfea8, 0x346b6b1, 0x3406eb8, 0x33a26bd, 0x333dec0, 0x32d96c1,
-    0x3274ec0,
-  0x32106bd, 0x31abeb9, 0x31476b2, 0x30e2ea9, 0x307e69f, 0x3019e93, 0x2fb5684,
-    0x2f50e74,
-  0x2eec663, 0x2e87e4f, 0x2e2363a, 0x2dbee22, 0x2d5a609, 0x2cf5def, 0x2c915d2,
-    0x2c2cdb4,
-  0x2bc8594, 0x2b63d73, 0x2aff54f, 0x2a9ad2a, 0x2a36504, 0x29d1cdc, 0x296d4b2,
-    0x2908c87,
-  0x28a445a, 0x283fc2b, 0x27db3fb, 0x2776bc9, 0x2712396, 0x26adb62, 0x264932b,
-    0x25e4af4,
-  0x25802bb, 0x251ba80, 0x24b7244, 0x2452a07, 0x23ee1c8, 0x2389988, 0x2325147,
-    0x22c0904,
-  0x225c0bf, 0x21f787a, 0x2193033, 0x212e7eb, 0x20c9fa1, 0x2065757, 0x2000f0b,
-    0x1f9c6be,
-  0x1f37e6f, 0x1ed3620, 0x1e6edcf, 0x1e0a57d, 0x1da5d2a, 0x1d414d6, 0x1cdcc80,
-    0x1c7842a,
-  0x1c13bd2, 0x1baf37a, 0x1b4ab20, 0x1ae62c5, 0x1a81a69, 0x1a1d20c, 0x19b89ae,
-    0x1954150,
-  0x18ef8f0, 0x188b08f, 0x182682d, 0x17c1fcb, 0x175d767, 0x16f8f03, 0x169469d,
-    0x162fe37,
-  0x15cb5d0, 0x1566d68, 0x15024ff, 0x149dc96, 0x143942b, 0x13d4bc0, 0x1370354,
-    0x130bae7,
-  0x12a727a, 0x1242a0c, 0x11de19d, 0x117992e, 0x11150be, 0x10b084d, 0x104bfdb,
-    0xfe7769,
-  0xf82ef6, 0xf1e683, 0xeb9e0f, 0xe5559b, 0xdf0d26, 0xd8c4b0, 0xd27c3a,
-    0xcc33c3,
-  0xc5eb4c, 0xbfa2d5, 0xb95a5d, 0xb311e4, 0xacc96b, 0xa680f2, 0xa03878,
-    0x99effe,
-  0x93a784, 0x8d5f09, 0x87168e, 0x80ce12, 0x7a8597, 0x743d1a, 0x6df49e,
-    0x67ac21,
-  0x6163a5, 0x5b1b27, 0x54d2aa, 0x4e8a2c, 0x4841af, 0x41f931, 0x3bb0b3,
-    0x356835,
-  0x2f1fb6, 0x28d738, 0x228eb9, 0x1c463b, 0x15fdbc, 0xfb53d, 0x96cbe, 0x3243f,
-
-};
-
-/**    
- * @brief  Initialization function for the Q31 DCT4/IDCT4.   
- * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.   
- * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure   
- * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure   
- * @param[in]     N          length of the DCT4.   
- * @param[in]     Nby2       half of the length of the DCT4.   
- * @param[in]     normalize  normalizing factor.   
- * @return		  arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.   
- * \par Normalizing factor:    
- * The normalizing factor is sqrt(2/N), which depends on the size of transform N.    
- * Normalizing factors in 1.31 format are mentioned in the table below for different DCT sizes:    
- * \image html dct4NormalizingQ31Table.gif    
- */
-
-arm_status arm_dct4_init_q31(
-  arm_dct4_instance_q31 * S,
-  arm_rfft_instance_q31 * S_RFFT,
-  arm_cfft_radix4_instance_q31 * S_CFFT,
-  uint16_t N,
-  uint16_t Nby2,
-  q31_t normalize)
-{
-  /*  Initialise the default arm status */
-  arm_status status = ARM_MATH_SUCCESS;
-
-  /* Initializing the pointer array with the weight table base addresses of different lengths */
-  q31_t *twiddlePtr[4] = { (q31_t *) WeightsQ31_128, (q31_t *) WeightsQ31_512,
-    (q31_t *) WeightsQ31_2048, (q31_t *) WeightsQ31_8192
-  };
-
-  /* Initializing the pointer array with the cos factor table base addresses of different lengths */
-  q31_t *pCosFactor[4] =
-    { (q31_t *) cos_factorsQ31_128, (q31_t *) cos_factorsQ31_512,
-    (q31_t *) cos_factorsQ31_2048, (q31_t *) cos_factorsQ31_8192
-  };
-
-  /* Initialize the DCT4 length */
-  S->N = N;
-
-  /* Initialize the half of DCT4 length */
-  S->Nby2 = Nby2;
-
-  /* Initialize the DCT4 Normalizing factor */
-  S->normalize = normalize;
-
-  /* Initialize Real FFT Instance */
-  S->pRfft = S_RFFT;
-
-  /* Initialize Complex FFT Instance */
-  S->pCfft = S_CFFT;
-
-  switch (N)
-  {
-    /* Initialize the table modifier values */
-  case 8192u:
-    S->pTwiddle = twiddlePtr[3];
-    S->pCosFactor = pCosFactor[3];
-    break;
-  case 2048u:
-    S->pTwiddle = twiddlePtr[2];
-    S->pCosFactor = pCosFactor[2];
-    break;
-  case 512u:
-    S->pTwiddle = twiddlePtr[1];
-    S->pCosFactor = pCosFactor[1];
-    break;
-  case 128u:
-    S->pTwiddle = twiddlePtr[0];
-    S->pCosFactor = pCosFactor[0];
-    break;
-  default:
-    status = ARM_MATH_ARGUMENT_ERROR;
-  }
-
-  /* Initialize the RFFT/RIFFT Function */
-  arm_rfft_init_q31(S->pRfft, S->pCfft, S->N, 0, 1);
-
-  /* return the status of DCT4 Init function */
-  return (status);
-}
-
-/**    
-   * @} end of DCT4_IDCT4 group    
-   */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q15.c
deleted file mode 100644
index ac3f691ecd..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q15.c
+++ /dev/null
@@ -1,386 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_dct4_q15.c    
-*    
-* Description:	Processing function of DCT4 & IDCT4 Q15.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @addtogroup DCT4_IDCT4    
- * @{    
- */
-
-/**    
- * @brief Processing function for the Q15 DCT4/IDCT4.   
- * @param[in]       *S             points to an instance of the Q15 DCT4 structure.   
- * @param[in]       *pState        points to state buffer.   
- * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.   
- * @return none.   
- *     
- * \par Input an output formats:    
- * Internally inputs are downscaled in the RFFT process function to avoid overflows.    
- * Number of bits downscaled, depends on the size of the transform.    
- * The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:     
- *    
- * \image html dct4FormatsQ15Table.gif    
- */
-
-void arm_dct4_q15(
-  const arm_dct4_instance_q15 * S,
-  q15_t * pState,
-  q15_t * pInlineBuffer)
-{
-  uint32_t i;                                    /* Loop counter */
-  q15_t *weights = S->pTwiddle;                  /* Pointer to the Weights table */
-  q15_t *cosFact = S->pCosFactor;                /* Pointer to the cos factors table */
-  q15_t *pS1, *pS2, *pbuff;                      /* Temporary pointers for input buffer and pState buffer */
-  q15_t in;                                      /* Temporary variable */
-
-
-  /* DCT4 computation involves DCT2 (which is calculated using RFFT)    
-   * along with some pre-processing and post-processing.    
-   * Computational procedure is explained as follows:    
-   * (a) Pre-processing involves multiplying input with cos factor,    
-   *     r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))    
-   *              where,    
-   *                 r(n) -- output of preprocessing    
-   *                 u(n) -- input to preprocessing(actual Source buffer)    
-   * (b) Calculation of DCT2 using FFT is divided into three steps:    
-   *                  Step1: Re-ordering of even and odd elements of input.    
-   *                  Step2: Calculating FFT of the re-ordered input.    
-   *                  Step3: Taking the real part of the product of FFT output and weights.    
-   * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:    
-   *                   Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
-   *                        where,    
-   *                           Y4 -- DCT4 output,   Y2 -- DCT2 output    
-   * (d) Multiplying the output with the normalizing factor sqrt(2/N).    
-   */
-
-        /*-------- Pre-processing ------------*/
-  /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
-  arm_mult_q15(pInlineBuffer, cosFact, pInlineBuffer, S->N);
-  arm_shift_q15(pInlineBuffer, 1, pInlineBuffer, S->N);
-
-  /* ----------------------------------------------------------------    
-   * Step1: Re-ordering of even and odd elements as    
-   *             pState[i] =  pInlineBuffer[2*i] and    
-   *             pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2    
-   ---------------------------------------------------------------------*/
-
-  /* pS1 initialized to pState */
-  pS1 = pState;
-
-  /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
-  pS2 = pState + (S->N - 1u);
-
-  /* pbuff initialized to input buffer */
-  pbuff = pInlineBuffer;
-
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
-  i = (uint32_t) S->Nby2 >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  do
-  {
-    /* Re-ordering of even and odd elements */
-    /* pState[i] =  pInlineBuffer[2*i] */
-    *pS1++ = *pbuff++;
-    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
-    *pS2-- = *pbuff++;
-
-    *pS1++ = *pbuff++;
-    *pS2-- = *pbuff++;
-
-    *pS1++ = *pbuff++;
-    *pS2-- = *pbuff++;
-
-    *pS1++ = *pbuff++;
-    *pS2-- = *pbuff++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-  /* pbuff initialized to input buffer */
-  pbuff = pInlineBuffer;
-
-  /* pS1 initialized to pState */
-  pS1 = pState;
-
-  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
-  i = (uint32_t) S->N >> 2u;
-
-  /* Processing with loop unrolling 4 times as N is always multiple of 4.    
-   * Compute 4 outputs at a time */
-  do
-  {
-    /* Writing the re-ordered output back to inplace input buffer */
-    *pbuff++ = *pS1++;
-    *pbuff++ = *pS1++;
-    *pbuff++ = *pS1++;
-    *pbuff++ = *pS1++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-
-  /* ---------------------------------------------------------    
-   *     Step2: Calculate RFFT for N-point input    
-   * ---------------------------------------------------------- */
-  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
-  arm_rfft_q15(S->pRfft, pInlineBuffer, pState);
-
- /*----------------------------------------------------------------------    
-  *  Step3: Multiply the FFT output with the weights.    
-  *----------------------------------------------------------------------*/
-  arm_cmplx_mult_cmplx_q15(pState, weights, pState, S->N);
-
-  /* The output of complex multiplication is in 3.13 format.    
-   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */
-  arm_shift_q15(pState, 2, pState, S->N * 2);
-
-  /* ----------- Post-processing ---------- */
-  /* DCT-IV can be obtained from DCT-II by the equation,    
-   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
-   *       Hence, Y4(0) = Y2(0)/2  */
-  /* Getting only real part from the output and Converting to DCT-IV */
-
-  /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
-  i = ((uint32_t) S->N - 1u) >> 2u;
-
-  /* pbuff initialized to input buffer. */
-  pbuff = pInlineBuffer;
-
-  /* pS1 initialized to pState */
-  pS1 = pState;
-
-  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
-  in = *pS1++ >> 1u;
-  /* input buffer acts as inplace, so output values are stored in the input itself. */
-  *pbuff++ = in;
-
-  /* pState pointer is incremented twice as the real values are located alternatively in the array */
-  pS1++;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  do
-  {
-    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
-    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    /* points to the next real value */
-    pS1++;
-
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    pS1++;
-
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    pS1++;
-
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    pS1++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  i = ((uint32_t) S->N - 1u) % 0x4u;
-
-  while(i > 0u)
-  {
-    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
-    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    /* points to the next real value */
-    pS1++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-
-   /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
-
-  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
-  i = (uint32_t) S->N >> 2u;
-
-  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
-  pbuff = pInlineBuffer;
-
-  /* Processing with loop unrolling 4 times as N is always multiple of 4.  Compute 4 outputs at a time */
-  do
-  {
-    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
-    in = *pbuff;
-    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
-
-    in = *pbuff;
-    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
-
-    in = *pbuff;
-    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
-
-    in = *pbuff;
-    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Initializing the loop counter to N/2 */
-  i = (uint32_t) S->Nby2;
-
-  do
-  {
-    /* Re-ordering of even and odd elements */
-    /* pState[i] =  pInlineBuffer[2*i] */
-    *pS1++ = *pbuff++;
-    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
-    *pS2-- = *pbuff++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-  /* pbuff initialized to input buffer */
-  pbuff = pInlineBuffer;
-
-  /* pS1 initialized to pState */
-  pS1 = pState;
-
-  /* Initializing the loop counter */
-  i = (uint32_t) S->N;
-
-  do
-  {
-    /* Writing the re-ordered output back to inplace input buffer */
-    *pbuff++ = *pS1++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-
-  /* ---------------------------------------------------------    
-   *     Step2: Calculate RFFT for N-point input    
-   * ---------------------------------------------------------- */
-  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
-  arm_rfft_q15(S->pRfft, pInlineBuffer, pState);
-
- /*----------------------------------------------------------------------    
-  *  Step3: Multiply the FFT output with the weights.    
-  *----------------------------------------------------------------------*/
-  arm_cmplx_mult_cmplx_q15(pState, weights, pState, S->N);
-
-  /* The output of complex multiplication is in 3.13 format.    
-   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */
-  arm_shift_q15(pState, 2, pState, S->N * 2);
-
-  /* ----------- Post-processing ---------- */
-  /* DCT-IV can be obtained from DCT-II by the equation,    
-   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
-   *       Hence, Y4(0) = Y2(0)/2  */
-  /* Getting only real part from the output and Converting to DCT-IV */
-
-  /* Initializing the loop counter */
-  i = ((uint32_t) S->N - 1u);
-
-  /* pbuff initialized to input buffer. */
-  pbuff = pInlineBuffer;
-
-  /* pS1 initialized to pState */
-  pS1 = pState;
-
-  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
-  in = *pS1++ >> 1u;
-  /* input buffer acts as inplace, so output values are stored in the input itself. */
-  *pbuff++ = in;
-
-  /* pState pointer is incremented twice as the real values are located alternatively in the array */
-  pS1++;
-
-  do
-  {
-    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
-    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    /* points to the next real value */
-    pS1++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-   /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
-
-  /* Initializing the loop counter */
-  i = (uint32_t) S->N;
-
-  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
-  pbuff = pInlineBuffer;
-
-  do
-  {
-    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
-    in = *pbuff;
-    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
-   * @} end of DCT4_IDCT4 group    
-   */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q31.c
deleted file mode 100644
index a8c3678779..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q31.c
+++ /dev/null
@@ -1,387 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_dct4_q31.c    
-*    
-* Description:	Processing function of DCT4 & IDCT4 Q31.    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @addtogroup DCT4_IDCT4    
- * @{    
- */
-
-/**    
- * @brief Processing function for the Q31 DCT4/IDCT4.   
- * @param[in]       *S             points to an instance of the Q31 DCT4 structure.   
- * @param[in]       *pState        points to state buffer.   
- * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.   
- * @return none.   
- * \par Input an output formats:    
- * Input samples need to be downscaled by 1 bit to avoid saturations in the Q31 DCT process,    
- * as the conversion from DCT2 to DCT4 involves one subtraction.    
- * Internally inputs are downscaled in the RFFT process function to avoid overflows.    
- * Number of bits downscaled, depends on the size of the transform.    
- * The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:     
- *    
- * \image html dct4FormatsQ31Table.gif    
- */
-
-void arm_dct4_q31(
-  const arm_dct4_instance_q31 * S,
-  q31_t * pState,
-  q31_t * pInlineBuffer)
-{
-  uint16_t i;                                    /* Loop counter */
-  q31_t *weights = S->pTwiddle;                  /* Pointer to the Weights table */
-  q31_t *cosFact = S->pCosFactor;                /* Pointer to the cos factors table */
-  q31_t *pS1, *pS2, *pbuff;                      /* Temporary pointers for input buffer and pState buffer */
-  q31_t in;                                      /* Temporary variable */
-
-
-  /* DCT4 computation involves DCT2 (which is calculated using RFFT)    
-   * along with some pre-processing and post-processing.    
-   * Computational procedure is explained as follows:    
-   * (a) Pre-processing involves multiplying input with cos factor,    
-   *     r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))    
-   *              where,    
-   *                 r(n) -- output of preprocessing    
-   *                 u(n) -- input to preprocessing(actual Source buffer)    
-   * (b) Calculation of DCT2 using FFT is divided into three steps:    
-   *                  Step1: Re-ordering of even and odd elements of input.    
-   *                  Step2: Calculating FFT of the re-ordered input.    
-   *                  Step3: Taking the real part of the product of FFT output and weights.    
-   * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:    
-   *                   Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
-   *                        where,    
-   *                           Y4 -- DCT4 output,   Y2 -- DCT2 output    
-   * (d) Multiplying the output with the normalizing factor sqrt(2/N).    
-   */
-
-        /*-------- Pre-processing ------------*/
-  /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
-  arm_mult_q31(pInlineBuffer, cosFact, pInlineBuffer, S->N);
-  arm_shift_q31(pInlineBuffer, 1, pInlineBuffer, S->N);
-
-  /* ----------------------------------------------------------------    
-   * Step1: Re-ordering of even and odd elements as    
-   *             pState[i] =  pInlineBuffer[2*i] and    
-   *             pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2    
-   ---------------------------------------------------------------------*/
-
-  /* pS1 initialized to pState */
-  pS1 = pState;
-
-  /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
-  pS2 = pState + (S->N - 1u);
-
-  /* pbuff initialized to input buffer */
-  pbuff = pInlineBuffer;
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
-  i = S->Nby2 >> 2u;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  do
-  {
-    /* Re-ordering of even and odd elements */
-    /* pState[i] =  pInlineBuffer[2*i] */
-    *pS1++ = *pbuff++;
-    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
-    *pS2-- = *pbuff++;
-
-    *pS1++ = *pbuff++;
-    *pS2-- = *pbuff++;
-
-    *pS1++ = *pbuff++;
-    *pS2-- = *pbuff++;
-
-    *pS1++ = *pbuff++;
-    *pS2-- = *pbuff++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-  /* pbuff initialized to input buffer */
-  pbuff = pInlineBuffer;
-
-  /* pS1 initialized to pState */
-  pS1 = pState;
-
-  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
-  i = S->N >> 2u;
-
-  /* Processing with loop unrolling 4 times as N is always multiple of 4.    
-   * Compute 4 outputs at a time */
-  do
-  {
-    /* Writing the re-ordered output back to inplace input buffer */
-    *pbuff++ = *pS1++;
-    *pbuff++ = *pS1++;
-    *pbuff++ = *pS1++;
-    *pbuff++ = *pS1++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-
-  /* ---------------------------------------------------------    
-   *     Step2: Calculate RFFT for N-point input    
-   * ---------------------------------------------------------- */
-  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
-  arm_rfft_q31(S->pRfft, pInlineBuffer, pState);
-
-  /*----------------------------------------------------------------------    
-   *  Step3: Multiply the FFT output with the weights.    
-   *----------------------------------------------------------------------*/
-  arm_cmplx_mult_cmplx_q31(pState, weights, pState, S->N);
-
-  /* The output of complex multiplication is in 3.29 format.    
-   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */
-  arm_shift_q31(pState, 2, pState, S->N * 2);
-
-  /* ----------- Post-processing ---------- */
-  /* DCT-IV can be obtained from DCT-II by the equation,    
-   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
-   *       Hence, Y4(0) = Y2(0)/2  */
-  /* Getting only real part from the output and Converting to DCT-IV */
-
-  /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
-  i = (S->N - 1u) >> 2u;
-
-  /* pbuff initialized to input buffer. */
-  pbuff = pInlineBuffer;
-
-  /* pS1 initialized to pState */
-  pS1 = pState;
-
-  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
-  in = *pS1++ >> 1u;
-  /* input buffer acts as inplace, so output values are stored in the input itself. */
-  *pbuff++ = in;
-
-  /* pState pointer is incremented twice as the real values are located alternatively in the array */
-  pS1++;
-
-  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.    
-   ** a second loop below computes the remaining 1 to 3 samples. */
-  do
-  {
-    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
-    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    /* points to the next real value */
-    pS1++;
-
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    pS1++;
-
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    pS1++;
-
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    pS1++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.    
-   ** No loop unrolling is used. */
-  i = (S->N - 1u) % 0x4u;
-
-  while(i > 0u)
-  {
-    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
-    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    /* points to the next real value */
-    pS1++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-
-        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
-
-  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
-  i = S->N >> 2u;
-
-  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
-  pbuff = pInlineBuffer;
-
-  /* Processing with loop unrolling 4 times as N is always multiple of 4.  Compute 4 outputs at a time */
-  do
-  {
-    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
-    in = *pbuff;
-    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
-
-    in = *pbuff;
-    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
-
-    in = *pbuff;
-    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
-
-    in = *pbuff;
-    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  /* Initializing the loop counter to N/2 */
-  i = S->Nby2;
-
-  do
-  {
-    /* Re-ordering of even and odd elements */
-    /* pState[i] =  pInlineBuffer[2*i] */
-    *pS1++ = *pbuff++;
-    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
-    *pS2-- = *pbuff++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-  /* pbuff initialized to input buffer */
-  pbuff = pInlineBuffer;
-
-  /* pS1 initialized to pState */
-  pS1 = pState;
-
-  /* Initializing the loop counter */
-  i = S->N;
-
-  do
-  {
-    /* Writing the re-ordered output back to inplace input buffer */
-    *pbuff++ = *pS1++;
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-
-  /* ---------------------------------------------------------    
-   *     Step2: Calculate RFFT for N-point input    
-   * ---------------------------------------------------------- */
-  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
-  arm_rfft_q31(S->pRfft, pInlineBuffer, pState);
-
-  /*----------------------------------------------------------------------    
-   *  Step3: Multiply the FFT output with the weights.    
-   *----------------------------------------------------------------------*/
-  arm_cmplx_mult_cmplx_q31(pState, weights, pState, S->N);
-
-  /* The output of complex multiplication is in 3.29 format.    
-   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */
-  arm_shift_q31(pState, 2, pState, S->N * 2);
-
-  /* ----------- Post-processing ---------- */
-  /* DCT-IV can be obtained from DCT-II by the equation,    
-   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)    
-   *       Hence, Y4(0) = Y2(0)/2  */
-  /* Getting only real part from the output and Converting to DCT-IV */
-
-  /* pbuff initialized to input buffer. */
-  pbuff = pInlineBuffer;
-
-  /* pS1 initialized to pState */
-  pS1 = pState;
-
-  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
-  in = *pS1++ >> 1u;
-  /* input buffer acts as inplace, so output values are stored in the input itself. */
-  *pbuff++ = in;
-
-  /* pState pointer is incremented twice as the real values are located alternatively in the array */
-  pS1++;
-
-  /* Initializing the loop counter */
-  i = (S->N - 1u);
-
-  while(i > 0u)
-  {
-    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
-    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
-    in = *pS1++ - in;
-    *pbuff++ = in;
-    /* points to the next real value */
-    pS1++;
-
-    /* Decrement the loop counter */
-    i--;
-  }
-
-
-        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
-
-  /* Initializing the loop counter */
-  i = S->N;
-
-  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
-  pbuff = pInlineBuffer;
-
-  do
-  {
-    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
-    in = *pbuff;
-    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
-
-    /* Decrement the loop counter */
-    i--;
-  } while(i > 0u);
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-}
-
-/**    
-   * @} end of DCT4_IDCT4 group    
-   */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_f32.c
deleted file mode 100644
index a3a2d23aa5..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_f32.c
+++ /dev/null
@@ -1,382 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_rfft_f32.c    
-*    
-* Description:	RFFT & RIFFT Floating point process function    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupTransforms    
- */
-
-/**    
- * @defgroup RFFT_RIFFT Real FFT Functions    
- *    
- * \par    
- * Complex FFT/IFFT typically assumes complex input and output. However many applications use real valued data in time domain.     
- * Real FFT/IFFT efficiently process real valued sequences with the advantage of requirement of low memory and with less complexity.    
- *    
- * \par    
- * This set of functions implements Real Fast Fourier Transforms(RFFT) and Real Inverse Fast Fourier Transform(RIFFT)    
- * for Q15, Q31, and floating-point data types.      
- *    
- *    
- * \par Algorithm:    
- *    
- * Real Fast Fourier Transform:    
- * \par    
- * Real FFT of N-point is calculated using CFFT of N/2-point and Split RFFT process as shown below figure.    
- * \par    
- * \image html RFFT.gif "Real Fast Fourier Transform"    
- * \par    
- * The RFFT functions operate on blocks of input and output data and each call to the function processes    
- * fftLenR samples through the transform.  pSrc  points to input array containing fftLenR values.    
- * pDst  points to output array containing 2*fftLenR values. \n   
- * Input for real FFT is in the order of     
- * 
{real[0], real[1], real[2], real[3], ..}
    
- * Output for real FFT is complex and are in the order of    
- * 
{real(0), imag(0), real(1), imag(1), ...}
     
- *    
- * Real Inverse Fast Fourier Transform:    
- * \par    
- * Real IFFT of N-point is calculated using Split RIFFT process and CFFT of N/2-point as shown below figure.    
- * \par    
- * \image html RIFFT.gif "Real Inverse Fast Fourier Transform"    
- * \par    
- * The RIFFT functions operate on blocks of input and output data and each call to the function processes    
- * 2*fftLenR samples through the transform.  pSrc  points to input array containing 2*fftLenR values.    
- * pDst  points to output array containing fftLenR values. \n    
- * Input for real IFFT is complex and are in the order of   
- * 
{real(0), imag(0), real(1), imag(1), ...}
   
- *  Output for real IFFT is real and in the order of     
- * 
{real[0], real[1], real[2], real[3], ..}
   
- *    
- * \par Lengths supported by the transform:   
- * \par    
- * Real FFT/IFFT supports the lengths [128, 512, 2048], as it internally uses CFFT/CIFFT.    
- *    
- * \par Instance Structure    
- * A separate instance structure must be defined for each Instance but the twiddle factors can be reused.    
- * There are separate instance structure declarations for each of the 3 supported data types.    
- *    
- * \par Initialization Functions    
- * There is also an associated initialization function for each data type.    
- * The initialization function performs the following operations:    
- * - Sets the values of the internal structure fields.    
- * - Initializes twiddle factor tables.   
- * - Initializes CFFT data structure fields.     
- * \par    
- * Use of the initialization function is optional.    
- * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.    
- * To place an instance structure into a const data section, the instance structure must be manually initialized.    
- * Manually initialize the instance structure as follows:    
- * 
    
- *arm_rfft_instance_f32 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};    
- *arm_rfft_instance_q31 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};    
- *arm_rfft_instance_q15 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};    
- * 
    
- * where fftLenReal length of RFFT/RIFFT; fftLenBy2 length of CFFT/CIFFT.     
- * ifftFlagR Flag for selection of RFFT or RIFFT(Set ifftFlagR to calculate RIFFT otherwise calculates RFFT);    
- * bitReverseFlagR Flag for selection of output order(Set bitReverseFlagR to output in normal order otherwise output in bit reversed order);     
- * twidCoefRModifier modifier for twiddle factor table which supports 128, 512, 2048 RFFT lengths with same table;    
- * pTwiddleARealpoints to A array of twiddle coefficients; pTwiddleBRealpoints to B array of twiddle coefficients;    
- * pCfft points to the CFFT Instance structure. The CFFT structure also needs to be initialized, refer to arm_cfft_radix4_f32() for details regarding    
- * static initialization of cfft structure.    
- *    
- * \par Fixed-Point Behavior    
- * Care must be taken when using the fixed-point versions of the RFFT/RIFFT function.    
- * Refer to the function specific documentation below for usage guidelines.    
- */
-
-/*--------------------------------------------------------------------    
- *		Internal functions prototypes    
- *--------------------------------------------------------------------*/
-
-void arm_split_rfft_f32(
-  float32_t * pSrc,
-  uint32_t fftLen,
-  float32_t * pATable,
-  float32_t * pBTable,
-  float32_t * pDst,
-  uint32_t modifier);
-void arm_split_rifft_f32(
-  float32_t * pSrc,
-  uint32_t fftLen,
-  float32_t * pATable,
-  float32_t * pBTable,
-  float32_t * pDst,
-  uint32_t modifier);
-
-/**    
- * @addtogroup RFFT_RIFFT    
- * @{    
- */
-
-/**    
- * @brief Processing function for the floating-point RFFT/RIFFT.   
- * @param[in]  *S    points to an instance of the floating-point RFFT/RIFFT structure.   
- * @param[in]  *pSrc points to the input buffer.   
- * @param[out] *pDst points to the output buffer.   
- * @return none.   
- */
-
-void arm_rfft_f32(
-  const arm_rfft_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst)
-{
-  const arm_cfft_radix4_instance_f32 *S_CFFT = S->pCfft;
-
-
-  /* Calculation of Real IFFT of input */
-  if(S->ifftFlagR == 1u)
-  {
-    /*  Real IFFT core process */
-    arm_split_rifft_f32(pSrc, S->fftLenBy2, S->pTwiddleAReal,
-                        S->pTwiddleBReal, pDst, S->twidCoefRModifier);
-
-
-    /* Complex radix-4 IFFT process */
-    arm_radix4_butterfly_inverse_f32(pDst, S_CFFT->fftLen,
-                                     S_CFFT->pTwiddle,
-                                     S_CFFT->twidCoefModifier,
-                                     S_CFFT->onebyfftLen);
-
-    /* Bit reversal process */
-    if(S->bitReverseFlagR == 1u)
-    {
-      arm_bitreversal_f32(pDst, S_CFFT->fftLen,
-                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
-    }
-  }
-  else
-  {
-
-    /* Calculation of RFFT of input */
-
-    /* Complex radix-4 FFT process */
-    arm_radix4_butterfly_f32(pSrc, S_CFFT->fftLen,
-                             S_CFFT->pTwiddle, S_CFFT->twidCoefModifier);
-
-    /* Bit reversal process */
-    if(S->bitReverseFlagR == 1u)
-    {
-      arm_bitreversal_f32(pSrc, S_CFFT->fftLen,
-                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
-    }
-
-
-    /*  Real FFT core process */
-    arm_split_rfft_f32(pSrc, S->fftLenBy2, S->pTwiddleAReal,
-                       S->pTwiddleBReal, pDst, S->twidCoefRModifier);
-  }
-
-}
-
-/**    
-   * @} end of RFFT_RIFFT group    
-   */
-
-/**    
- * @brief  Core Real FFT process    
- * @param[in]   *pSrc 				points to the input buffer.    
- * @param[in]   fftLen  			length of FFT.    
- * @param[in]   *pATable 			points to the twiddle Coef A buffer.    
- * @param[in]   *pBTable 			points to the twiddle Coef B buffer.    
- * @param[out]  *pDst 				points to the output buffer.    
- * @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
- * @return none.    
- */
-
-void arm_split_rfft_f32(
-  float32_t * pSrc,
-  uint32_t fftLen,
-  float32_t * pATable,
-  float32_t * pBTable,
-  float32_t * pDst,
-  uint32_t modifier)
-{
-  uint32_t i;                                    /* Loop Counter */
-  float32_t outR, outI;                          /* Temporary variables for output */
-  float32_t *pCoefA, *pCoefB;                    /* Temporary pointers for twiddle factors */
-  float32_t CoefA1, CoefA2, CoefB1;              /* Temporary variables for twiddle coefficients */
-  float32_t *pDst1 = &pDst[2], *pDst2 = &pDst[(4u * fftLen) - 1u];      /* temp pointers for output buffer */
-  float32_t *pSrc1 = &pSrc[2], *pSrc2 = &pSrc[(2u * fftLen) - 1u];      /* temp pointers for input buffer */
-
-  /* Init coefficient pointers */
-  pCoefA = &pATable[modifier * 2u];
-  pCoefB = &pBTable[modifier * 2u];
-
-  i = fftLen - 1u;
-
-  while(i > 0u)
-  {
-    /*    
-       outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]    
-       + pSrc[2 * n - 2 * i] * pBTable[2 * i] +    
-       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
-     */
-
-    /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +    
-       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
-       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
-
-    /* read pATable[2 * i] */
-    CoefA1 = *pCoefA++;
-    /* pATable[2 * i + 1] */
-    CoefA2 = *pCoefA;
-
-    /* pSrc[2 * i] * pATable[2 * i] */
-    outR = *pSrc1 * CoefA1;
-    /* pSrc[2 * i] * CoefA2 */
-    outI = *pSrc1++ * CoefA2;
-
-    /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */
-    outR -= (*pSrc1 + *pSrc2) * CoefA2;
-    /* pSrc[2 * i + 1] * CoefA1 */
-    outI += *pSrc1++ * CoefA1;
-
-    CoefB1 = *pCoefB;
-
-    /* pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */
-    outI -= *pSrc2-- * CoefB1;
-    /* pSrc[2 * fftLen - 2 * i] * CoefA2 */
-    outI -= *pSrc2 * CoefA2;
-
-    /* pSrc[2 * fftLen - 2 * i] * CoefB1 */
-    outR += *pSrc2-- * CoefB1;
-
-    /* write output */
-    *pDst1++ = outR;
-    *pDst1++ = outI;
-
-    /* write complex conjugate output */
-    *pDst2-- = -outI;
-    *pDst2-- = outR;
-
-    /* update coefficient pointer */
-    pCoefB = pCoefB + (modifier * 2u);
-    pCoefA = pCoefA + ((modifier * 2u) - 1u);
-
-    i--;
-
-  }
-
-  pDst[2u * fftLen] = pSrc[0] - pSrc[1];
-  pDst[(2u * fftLen) + 1u] = 0.0f;
-
-  pDst[0] = pSrc[0] + pSrc[1];
-  pDst[1] = 0.0f;
-
-}
-
-
-/**    
- * @brief  Core Real IFFT process    
- * @param[in]   *pSrc 				points to the input buffer.    
- * @param[in]   fftLen  			length of FFT.   
- * @param[in]   *pATable 			points to the twiddle Coef A buffer.   
- * @param[in]   *pBTable 			points to the twiddle Coef B buffer.   
- * @param[out]  *pDst 				points to the output buffer.   
- * @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.    
- * @return none.    
- */
-
-void arm_split_rifft_f32(
-  float32_t * pSrc,
-  uint32_t fftLen,
-  float32_t * pATable,
-  float32_t * pBTable,
-  float32_t * pDst,
-  uint32_t modifier)
-{
-  float32_t outR, outI;                          /* Temporary variables for output */
-  float32_t *pCoefA, *pCoefB;                    /* Temporary pointers for twiddle factors */
-  float32_t CoefA1, CoefA2, CoefB1;              /* Temporary variables for twiddle coefficients */
-  float32_t *pSrc1 = &pSrc[0], *pSrc2 = &pSrc[(2u * fftLen) + 1u];
-
-  pCoefA = &pATable[0];
-  pCoefB = &pBTable[0];
-
-  while(fftLen > 0u)
-  {
-    /*    
-       outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +    
-       pIn[2 * n - 2 * i] * pBTable[2 * i] -    
-       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
-
-       outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -    
-       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
-       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);    
-
-     */
-
-    CoefA1 = *pCoefA++;
-    CoefA2 = *pCoefA;
-
-    /* outR = (pSrc[2 * i] * CoefA1 */
-    outR = *pSrc1 * CoefA1;
-
-    /* - pSrc[2 * i] * CoefA2 */
-    outI = -(*pSrc1++) * CoefA2;
-
-    /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */
-    outR += (*pSrc1 + *pSrc2) * CoefA2;
-
-    /* pSrc[2 * i + 1] * CoefA1 */
-    outI += (*pSrc1++) * CoefA1;
-
-    CoefB1 = *pCoefB;
-
-    /* - pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */
-    outI -= *pSrc2-- * CoefB1;
-
-    /* pSrc[2 * fftLen - 2 * i] * CoefB1 */
-    outR += *pSrc2 * CoefB1;
-
-    /* pSrc[2 * fftLen - 2 * i] * CoefA2 */
-    outI += *pSrc2-- * CoefA2;
-
-    /* write output */
-    *pDst++ = outR;
-    *pDst++ = outI;
-
-    /* update coefficient pointer */
-    pCoefB = pCoefB + (modifier * 2u);
-    pCoefA = pCoefA + ((modifier * 2u) - 1u);
-
-    /* Decrement loop count */
-    fftLen--;
-  }
-
-}
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_f32.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_f32.c
deleted file mode 100644
index 0133ae511c..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_f32.c
+++ /dev/null
@@ -1,8369 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_rfft_init_f32.c    
-*    
-* Description:	RFFT & RIFFT Floating point initialisation function    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* -------------------------------------------------------------------- */
-
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupTransforms    
- */
-
-/**    
- * @addtogroup RFFT_RIFFT    
- * @{    
- */
-
-/**    
-* \par    
-* Generation of realCoefA array:    
-* \par    
-* 	n = 4096    
-* 
for (i = 0; i < n; i++)    
-*  {    
-*    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));    
-*    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    
-*  } 
    
-*/
-
-
-
-static const float32_t realCoefA[8192] = {
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-    -0.499999850988388f,
-  0.499233007431030f, -0.499999403953552f, 0.498849511146545f,
-    -0.499998688697815f,
-  0.498466014862061f, -0.499997645616531f, 0.498082518577576f,
-    -0.499996334314346f,
-  0.497699022293091f, -0.499994695186615f, 0.497315555810928f,
-    -0.499992787837982f,
-  0.496932059526443f, -0.499990582466125f, 0.496548563241959f,
-    -0.499988079071045f,
-  0.496165096759796f, -0.499985307455063f, 0.495781600475311f,
-    -0.499982208013535f,
-  0.495398133993149f, -0.499978810548782f, 0.495014637708664f,
-    -0.499975144863129f,
-  0.494631171226501f, -0.499971181154251f, 0.494247704744339f,
-    -0.499966919422150f,
-  0.493864238262177f, -0.499962359666824f, 0.493480771780014f,
-    -0.499957501888275f,
-  0.493097305297852f, -0.499952346086502f, 0.492713838815689f,
-    -0.499946922063828f,
-  0.492330402135849f, -0.499941170215607f, 0.491946935653687f,
-    -0.499935150146484f,
-  0.491563498973846f, -0.499928832054138f, 0.491180062294006f,
-    -0.499922215938568f,
-  0.490796625614166f, -0.499915301799774f, 0.490413218736649f,
-    -0.499908089637756f,
-  0.490029782056808f, -0.499900579452515f, 0.489646375179291f,
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-    -0.499819844961166f,
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-    -0.499798685312271f,
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-    -0.499776333570480f,
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-    -0.499752789735794f,
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-    -0.499702215194702f,
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-    -0.499675154685974f,
-  0.481596380472183f, -0.499661177396774f, 0.481213152408600f,
-    -0.499646931886673f,
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-    -0.499617516994476f,
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-    -0.499586939811707f,
-  0.479297190904617f, -0.499571204185486f, 0.478914022445679f,
-    -0.499555170536041f,
-  0.478530883789063f, -0.499538868665695f, 0.478147745132446f,
-    -0.499522238969803f,
-  0.477764606475830f, -0.499505341053009f, 0.477381497621536f,
-    -0.499488145112991f,
-  0.476998418569565f, -0.499470651149750f, 0.476615339517593f,
-    -0.499452859163284f,
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-    -0.499416410923004f,
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-    -0.499378770589828f,
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-    -0.499339967966080f,
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-    -0.499299973249435f,
-  0.473168224096298f, -0.499279528856277f, 0.472785294055939f,
-    -0.499258816242218f,
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-    -0.499216467142105f,
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-    -0.499172955751419f,
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-    -0.499128282070160f,
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-    -0.499082416296005f,
-  0.469339638948441f, -0.499059051275253f, 0.468956857919693f,
-    -0.499035388231277f,
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-    -0.498937815427780f,
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-    -0.498616874217987f,
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-    -0.498559266328812f,
-  0.461688071489334f, -0.498530030250549f, 0.461305707693100f,
-    -0.498500496149063f,
-  0.460923373699188f, -0.498470664024353f, 0.460541069507599f,
-    -0.498440563678741f,
-  0.460158795118332f, -0.498410135507584f, 0.459776520729065f,
-    -0.498379439115524f,
-  0.459394276142120f, -0.498348444700241f, 0.459012061357498f,
-    -0.498317152261734f,
-  0.458629876375198f, -0.498285561800003f, 0.458247691392899f,
-    -0.498253703117371f,
-  0.457865566015244f, -0.498221516609192f, 0.457483440637589f,
-    -0.498189061880112f,
-  0.457101345062256f, -0.498156309127808f, 0.456719279289246f,
-    -0.498123258352280f,
-  0.456337243318558f, -0.498089909553528f, 0.455955207347870f,
-    -0.498056292533875f,
-  0.455573230981827f, -0.498022347688675f, 0.455191254615784f,
-    -0.497988134622574f,
-  0.454809308052063f, -0.497953623533249f, 0.454427421092987f,
-    -0.497918814420700f,
-  0.454045534133911f, -0.497883707284927f, 0.453663676977158f,
-    -0.497848302125931f,
-  0.453281819820404f, -0.497812628746033f, 0.452900022268295f,
-    -0.497776657342911f,
-  0.452518254518509f, -0.497740387916565f, 0.452136516571045f,
-    -0.497703820466995f,
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-    -0.497629791498184f,
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-    -0.497554630041122f,
-  0.450228184461594f, -0.497516602277756f, 0.449846625328064f,
-    -0.497478276491165f,
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-    -0.497161179780960f,
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-    -0.497078984975815f,
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-    -0.496561229228973f,
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-    -0.496286571025848f,
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-    -0.496192663908005f,
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-    -0.496097624301910f,
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-    -0.496001392602921f,
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-    -0.495903998613358f,
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-    -0.495805442333221f,
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-    -0.495705723762512f,
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-    -0.495604842901230f,
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-    -0.495502769947052f,
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-    -0.495399564504623f,
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-    -0.495295166969299f,
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-    -0.495189607143402f,
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-    -0.495082914829254f,
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-  0.403959810733795f, 0.490689605474472f, 0.404336184263229f,
-    0.490763127803802f,
-  0.404712617397308f, 0.490836352109909f, 0.405089110136032f,
-    0.490909278392792f,
-  0.405465662479401f, 0.490981936454773f, 0.405842274427414f,
-    0.491054296493530f,
-  0.406218945980072f, 0.491126358509064f, 0.406595647335052f,
-    0.491198152303696f,
-  0.406972438097000f, 0.491269648075104f, 0.407349258661270f,
-    0.491340845823288f,
-  0.407726138830185f, 0.491411775350571f, 0.408103078603745f,
-    0.491482406854630f,
-  0.408480048179626f, 0.491552740335464f, 0.408857107162476f,
-    0.491622805595398f,
-  0.409234195947647f, 0.491692543029785f, 0.409611344337463f,
-    0.491762012243271f,
-  0.409988552331924f, 0.491831213235855f, 0.410365819931030f,
-    0.491900116205215f,
-  0.410743117332459f, 0.491968721151352f, 0.411120474338531f,
-    0.492037028074265f,
-  0.411497890949249f, 0.492105036973953f, 0.411875367164612f,
-    0.492172777652740f,
-  0.412252873182297f, 0.492240220308304f, 0.412630438804626f,
-    0.492307394742966f,
-  0.413008064031601f, 0.492374241352081f, 0.413385748863220f,
-    0.492440819740295f,
-  0.413763463497162f, 0.492507129907608f, 0.414141237735748f,
-    0.492573112249374f,
-  0.414519041776657f, 0.492638826370239f, 0.414896935224533f,
-    0.492704242467880f,
-  0.415274858474731f, 0.492769360542297f, 0.415652841329575f,
-    0.492834210395813f,
-  0.416030853986740f, 0.492898762226105f, 0.416408926248550f,
-    0.492963016033173f,
-  0.416787058115005f, 0.493026971817017f, 0.417165219783783f,
-    0.493090659379959f,
-  0.417543441057205f, 0.493154048919678f, 0.417921721935272f,
-    0.493217140436172f,
-  0.418300032615662f, 0.493279963731766f, 0.418678402900696f,
-    0.493342459201813f,
-  0.419056802988052f, 0.493404686450958f, 0.419435262680054f,
-    0.493466645479202f,
-  0.419813781976700f, 0.493528276681900f, 0.420192331075668f,
-    0.493589639663696f,
-  0.420570939779282f, 0.493650704622269f, 0.420949578285217f,
-    0.493711471557617f,
-  0.421328276395798f, 0.493771970272064f, 0.421707004308701f,
-    0.493832170963287f,
-  0.422085791826248f, 0.493892073631287f, 0.422464638948441f,
-    0.493951678276062f,
-  0.422843515872955f, 0.494011014699936f, 0.423222452402115f,
-    0.494070053100586f,
-  0.423601418733597f, 0.494128793478012f, 0.423980414867401f,
-    0.494187235832214f,
-  0.424359470605850f, 0.494245409965515f, 0.424738585948944f,
-    0.494303256273270f,
-  0.425117731094360f, 0.494360834360123f, 0.425496935844421f,
-    0.494418144226074f,
-  0.425876170396805f, 0.494475126266479f, 0.426255434751511f,
-    0.494531840085983f,
-  0.426634758710861f, 0.494588255882263f, 0.427014142274857f,
-    0.494644373655319f,
-  0.427393525838852f, 0.494700223207474f, 0.427772998809814f,
-    0.494755744934082f,
-  0.428152471780777f, 0.494810998439789f, 0.428532034158707f,
-    0.494865983724594f,
-  0.428911596536636f, 0.494920641183853f, 0.429291218519211f,
-    0.494975030422211f,
-  0.429670870304108f, 0.495029091835022f, 0.430050581693649f,
-    0.495082914829254f,
-  0.430430322885513f, 0.495136409997940f, 0.430810123682022f,
-    0.495189607143402f,
-  0.431189924478531f, 0.495242536067963f, 0.431569814682007f,
-    0.495295166969299f,
-  0.431949704885483f, 0.495347499847412f, 0.432329654693604f,
-    0.495399564504623f,
-  0.432709634304047f, 0.495451331138611f, 0.433089673519135f,
-    0.495502769947052f,
-  0.433469742536545f, 0.495553970336914f, 0.433849841356277f,
-    0.495604842901230f,
-  0.434229999780655f, 0.495655417442322f, 0.434610158205032f,
-    0.495705723762512f,
-  0.434990376234055f, 0.495755732059479f, 0.435370653867722f,
-    0.495805442333221f,
-  0.435750931501389f, 0.495854884386063f, 0.436131268739700f,
-    0.495903998613358f,
-  0.436511665582657f, 0.495952844619751f, 0.436892062425613f,
-    0.496001392602921f,
-  0.437272518873215f, 0.496049642562866f, 0.437653005123138f,
-    0.496097624301910f,
-  0.438033521175385f, 0.496145308017731f, 0.438414067029953f,
-    0.496192663908005f,
-  0.438794672489166f, 0.496239781379700f, 0.439175277948380f,
-    0.496286571025848f,
-  0.439555943012238f, 0.496333062648773f, 0.439936667680740f,
-    0.496379286050797f,
-  0.440317392349243f, 0.496425211429596f, 0.440698176622391f,
-    0.496470838785172f,
-  0.441078960895538f, 0.496516168117523f, 0.441459804773331f,
-    0.496561229228973f,
-  0.441840678453445f, 0.496605962514877f, 0.442221581935883f,
-    0.496650427579880f,
-  0.442602545022964f, 0.496694594621658f, 0.442983508110046f,
-    0.496738493442535f,
-  0.443364530801773f, 0.496782064437866f, 0.443745553493500f,
-    0.496825367212296f,
-  0.444126635789871f, 0.496868371963501f, 0.444507747888565f,
-    0.496911078691483f,
-  0.444888889789581f, 0.496953487396240f, 0.445270061492920f,
-    0.496995598077774f,
-  0.445651292800903f, 0.497037440538406f, 0.446032524108887f,
-    0.497078984975815f,
-  0.446413785219193f, 0.497120231389999f, 0.446795076131821f,
-    0.497161179780960f,
-  0.447176426649094f, 0.497201830148697f, 0.447557777166367f,
-    0.497242212295532f,
-  0.447939187288284f, 0.497282296419144f, 0.448320597410202f,
-    0.497322082519531f,
-  0.448702067136765f, 0.497361570596695f, 0.449083566665649f,
-    0.497400760650635f,
-  0.449465066194534f, 0.497439652681351f, 0.449846625328064f,
-    0.497478276491165f,
-  0.450228184461594f, 0.497516602277756f, 0.450609803199768f,
-    0.497554630041122f,
-  0.450991421937943f, 0.497592359781265f, 0.451373100280762f,
-    0.497629791498184f,
-  0.451754778623581f, 0.497666954994202f, 0.452136516571045f,
-    0.497703820466995f,
-  0.452518254518509f, 0.497740387916565f, 0.452900022268295f,
-    0.497776657342911f,
-  0.453281819820404f, 0.497812628746033f, 0.453663676977158f,
-    0.497848302125931f,
-  0.454045534133911f, 0.497883707284927f, 0.454427421092987f,
-    0.497918814420700f,
-  0.454809308052063f, 0.497953623533249f, 0.455191254615784f,
-    0.497988134622574f,
-  0.455573230981827f, 0.498022347688675f, 0.455955207347870f,
-    0.498056292533875f,
-  0.456337243318558f, 0.498089909553528f, 0.456719279289246f,
-    0.498123258352280f,
-  0.457101345062256f, 0.498156309127808f, 0.457483440637589f,
-    0.498189061880112f,
-  0.457865566015244f, 0.498221516609192f, 0.458247691392899f,
-    0.498253703117371f,
-  0.458629876375198f, 0.498285561800003f, 0.459012061357498f,
-    0.498317152261734f,
-  0.459394276142120f, 0.498348444700241f, 0.459776520729065f,
-    0.498379439115524f,
-  0.460158795118332f, 0.498410135507584f, 0.460541069507599f,
-    0.498440563678741f,
-  0.460923373699188f, 0.498470664024353f, 0.461305707693100f,
-    0.498500496149063f,
-  0.461688071489334f, 0.498530030250549f, 0.462070435285568f,
-    0.498559266328812f,
-  0.462452858686447f, 0.498588204383850f, 0.462835282087326f,
-    0.498616874217987f,
-  0.463217705488205f, 0.498645216226578f, 0.463600188493729f,
-    0.498673290014267f,
-  0.463982671499252f, 0.498701065778732f, 0.464365184307098f,
-    0.498728543519974f,
-  0.464747726917267f, 0.498755723237991f, 0.465130269527435f,
-    0.498782604932785f,
-  0.465512841939926f, 0.498809218406677f, 0.465895414352417f,
-    0.498835533857346f,
-  0.466278046369553f, 0.498861521482468f, 0.466660678386688f,
-    0.498887240886688f,
-  0.467043310403824f, 0.498912662267685f, 0.467426002025604f,
-    0.498937815427780f,
-  0.467808693647385f, 0.498962640762329f, 0.468191385269165f,
-    0.498987197875977f,
-  0.468574106693268f, 0.499011427164078f, 0.468956857919693f,
-    0.499035388231277f,
-  0.469339638948441f, 0.499059051275253f, 0.469722419977188f,
-    0.499082416296005f,
-  0.470105201005936f, 0.499105513095856f, 0.470488041639328f,
-    0.499128282070160f,
-  0.470870882272720f, 0.499150782823563f, 0.471253722906113f,
-    0.499172955751419f,
-  0.471636593341827f, 0.499194860458374f, 0.472019463777542f,
-    0.499216467142105f,
-  0.472402364015579f, 0.499237775802612f, 0.472785294055939f,
-    0.499258816242218f,
-  0.473168224096298f, 0.499279528856277f, 0.473551183938980f,
-    0.499299973249435f,
-  0.473934143781662f, 0.499320119619370f, 0.474317133426666f,
-    0.499339967966080f,
-  0.474700123071671f, 0.499359518289566f, 0.475083142518997f,
-    0.499378770589828f,
-  0.475466161966324f, 0.499397724866867f, 0.475849211215973f,
-    0.499416410923004f,
-  0.476232260465622f, 0.499434769153595f, 0.476615339517593f,
-    0.499452859163284f,
-  0.476998418569565f, 0.499470651149750f, 0.477381497621536f,
-    0.499488145112991f,
-  0.477764606475830f, 0.499505341053009f, 0.478147745132446f,
-    0.499522238969803f,
-  0.478530883789063f, 0.499538868665695f, 0.478914022445679f,
-    0.499555170536041f,
-  0.479297190904617f, 0.499571204185486f, 0.479680359363556f,
-    0.499586939811707f,
-  0.480063527822495f, 0.499602377414703f, 0.480446726083755f,
-    0.499617516994476f,
-  0.480829954147339f, 0.499632388353348f, 0.481213152408600f,
-    0.499646931886673f,
-  0.481596380472183f, 0.499661177396774f, 0.481979638338089f,
-    0.499675154685974f,
-  0.482362866401672f, 0.499688833951950f, 0.482746154069901f,
-    0.499702215194702f,
-  0.483129411935806f, 0.499715298414230f, 0.483512699604034f,
-    0.499728083610535f,
-  0.483895987272263f, 0.499740600585938f, 0.484279274940491f,
-    0.499752789735794f,
-  0.484662592411041f, 0.499764710664749f, 0.485045909881592f,
-    0.499776333570480f,
-  0.485429257154465f, 0.499787658452988f, 0.485812574625015f,
-    0.499798685312271f,
-  0.486195921897888f, 0.499809414148331f, 0.486579269170761f,
-    0.499819844961166f,
-  0.486962646245956f, 0.499830007553101f, 0.487346023321152f,
-    0.499839842319489f,
-  0.487729400396347f, 0.499849408864975f, 0.488112777471542f,
-    0.499858677387238f,
-  0.488496154546738f, 0.499867647886276f, 0.488879561424255f,
-    0.499876320362091f,
-  0.489262968301773f, 0.499884694814682f, 0.489646375179291f,
-    0.499892801046371f,
-  0.490029782056808f, 0.499900579452515f, 0.490413218736649f,
-    0.499908089637756f,
-  0.490796625614166f, 0.499915301799774f, 0.491180062294006f,
-    0.499922215938568f,
-  0.491563498973846f, 0.499928832054138f, 0.491946935653687f,
-    0.499935150146484f,
-  0.492330402135849f, 0.499941170215607f, 0.492713838815689f,
-    0.499946922063828f,
-  0.493097305297852f, 0.499952346086502f, 0.493480771780014f,
-    0.499957501888275f,
-  0.493864238262177f, 0.499962359666824f, 0.494247704744339f,
-    0.499966919422150f,
-  0.494631171226501f, 0.499971181154251f, 0.495014637708664f,
-    0.499975144863129f,
-  0.495398133993149f, 0.499978810548782f, 0.495781600475311f,
-    0.499982208013535f,
-  0.496165096759796f, 0.499985307455063f, 0.496548563241959f,
-    0.499988079071045f,
-  0.496932059526443f, 0.499990582466125f, 0.497315555810928f,
-    0.499992787837982f,
-  0.497699022293091f, 0.499994695186615f, 0.498082518577576f,
-    0.499996334314346f,
-  0.498466014862061f, 0.499997645616531f, 0.498849511146545f,
-    0.499998688697815f,
-  0.499233007431030f, 0.499999403953552f, 0.499616503715515f,
-    0.499999850988388f,
-};
-
-
-/**    
-* \par   
-* Generation of realCoefB array:    
-* \par   
-* n = 4096    
-* 
for (i = 0; i < n; i++)    
-* {    
-*    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));    
-*    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    
-*  } 
    
-*    
-*/
-static const float32_t realCoefB[8192] = {
-  0.500000000000000f, 0.500000000000000f, 0.500383496284485f,
-    0.499999850988388f,
-  0.500766992568970f, 0.499999403953552f, 0.501150488853455f,
-    0.499998688697815f,
-  0.501533985137939f, 0.499997645616531f, 0.501917481422424f,
-    0.499996334314346f,
-  0.502300977706909f, 0.499994695186615f, 0.502684473991394f,
-    0.499992787837982f,
-  0.503067970275879f, 0.499990582466125f, 0.503451406955719f,
-    0.499988079071045f,
-  0.503834903240204f, 0.499985307455063f, 0.504218399524689f,
-    0.499982208013535f,
-  0.504601895809174f, 0.499978810548782f, 0.504985332489014f,
-    0.499975144863129f,
-  0.505368828773499f, 0.499971181154251f, 0.505752325057983f,
-    0.499966919422150f,
-  0.506135761737823f, 0.499962359666824f, 0.506519258022308f,
-    0.499957501888275f,
-  0.506902694702148f, 0.499952346086502f, 0.507286131381989f,
-    0.499946922063828f,
-  0.507669627666473f, 0.499941170215607f, 0.508053064346313f,
-    0.499935150146484f,
-  0.508436501026154f, 0.499928832054138f, 0.508819937705994f,
-    0.499922215938568f,
-  0.509203374385834f, 0.499915301799774f, 0.509586811065674f,
-    0.499908089637756f,
-  0.509970188140869f, 0.499900579452515f, 0.510353624820709f,
-    0.499892801046371f,
-  0.510737061500549f, 0.499884694814682f, 0.511120438575745f,
-    0.499876320362091f,
-  0.511503815650940f, 0.499867647886276f, 0.511887252330780f,
-    0.499858677387238f,
-  0.512270629405975f, 0.499849408864975f, 0.512654006481171f,
-    0.499839842319489f,
-  0.513037383556366f, 0.499830007553101f, 0.513420701026917f,
-    0.499819844961166f,
-  0.513804078102112f, 0.499809414148331f, 0.514187395572662f,
-    0.499798685312271f,
-  0.514570772647858f, 0.499787658452988f, 0.514954090118408f,
-    0.499776333570480f,
-  0.515337407588959f, 0.499764710664749f, 0.515720725059509f,
-    0.499752789735794f,
-  0.516103982925415f, 0.499740600585938f, 0.516487300395966f,
-    0.499728083610535f,
-  0.516870558261871f, 0.499715298414230f, 0.517253875732422f,
-    0.499702215194702f,
-  0.517637133598328f, 0.499688833951950f, 0.518020391464233f,
-    0.499675154685974f,
-  0.518403589725494f, 0.499661177396774f, 0.518786847591400f,
-    0.499646931886673f,
-  0.519170045852661f, 0.499632388353348f, 0.519553244113922f,
-    0.499617516994476f,
-  0.519936442375183f, 0.499602377414703f, 0.520319640636444f,
-    0.499586939811707f,
-  0.520702838897705f, 0.499571204185486f, 0.521085977554321f,
-    0.499555170536041f,
-  0.521469116210938f, 0.499538868665695f, 0.521852254867554f,
-    0.499522238969803f,
-  0.522235393524170f, 0.499505341053009f, 0.522618472576141f,
-    0.499488145112991f,
-  0.523001611232758f, 0.499470651149750f, 0.523384690284729f,
-    0.499452859163284f,
-  0.523767769336700f, 0.499434769153595f, 0.524150788784027f,
-    0.499416410923004f,
-  0.524533808231354f, 0.499397724866867f, 0.524916887283325f,
-    0.499378770589828f,
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-  0.570329129695892f, -0.495029091835022f, 0.569949388504028f,
-    -0.495082914829254f,
-  0.569569647312164f, -0.495136409997940f, 0.569189906120300f,
-    -0.495189607143402f,
-  0.568810045719147f, -0.495242536067963f, 0.568430185317993f,
-    -0.495295166969299f,
-  0.568050265312195f, -0.495347499847412f, 0.567670345306396f,
-    -0.495399564504623f,
-  0.567290365695953f, -0.495451331138611f, 0.566910326480865f,
-    -0.495502769947052f,
-  0.566530287265778f, -0.495553970336914f, 0.566150128841400f,
-    -0.495604842901230f,
-  0.565770030021667f, -0.495655417442322f, 0.565389811992645f,
-    -0.495705723762512f,
-  0.565009593963623f, -0.495755732059479f, 0.564629375934601f,
-    -0.495805442333221f,
-  0.564249038696289f, -0.495854884386063f, 0.563868701457977f,
-    -0.495903998613358f,
-  0.563488364219666f, -0.495952844619751f, 0.563107967376709f,
-    -0.496001392602921f,
-  0.562727510929108f, -0.496049642562866f, 0.562346994876862f,
-    -0.496097624301910f,
-  0.561966478824615f, -0.496145308017731f, 0.561585903167725f,
-    -0.496192663908005f,
-  0.561205327510834f, -0.496239781379700f, 0.560824692249298f,
-    -0.496286571025848f,
-  0.560444056987762f, -0.496333062648773f, 0.560063362121582f,
-    -0.496379286050797f,
-  0.559682607650757f, -0.496425211429596f, 0.559301853179932f,
-    -0.496470838785172f,
-  0.558921039104462f, -0.496516168117523f, 0.558540165424347f,
-    -0.496561229228973f,
-  0.558159291744232f, -0.496605962514877f, 0.557778418064117f,
-    -0.496650427579880f,
-  0.557397484779358f, -0.496694594621658f, 0.557016491889954f,
-    -0.496738493442535f,
-  0.556635499000549f, -0.496782064437866f, 0.556254446506500f,
-    -0.496825367212296f,
-  0.555873334407806f, -0.496868371963501f, 0.555492222309113f,
-    -0.496911078691483f,
-  0.555111110210419f, -0.496953487396240f, 0.554729938507080f,
-    -0.496995598077774f,
-  0.554348707199097f, -0.497037440538406f, 0.553967475891113f,
-    -0.497078984975815f,
-  0.553586184978485f, -0.497120231389999f, 0.553204894065857f,
-    -0.497161179780960f,
-  0.552823603153229f, -0.497201830148697f, 0.552442193031311f,
-    -0.497242212295532f,
-  0.552060842514038f, -0.497282296419144f, 0.551679372787476f,
-    -0.497322082519531f,
-  0.551297962665558f, -0.497361570596695f, 0.550916433334351f,
-    -0.497400760650635f,
-  0.550534904003143f, -0.497439652681351f, 0.550153374671936f,
-    -0.497478276491165f,
-  0.549771785736084f, -0.497516602277756f, 0.549390196800232f,
-    -0.497554630041122f,
-  0.549008548259735f, -0.497592359781265f, 0.548626899719238f,
-    -0.497629791498184f,
-  0.548245191574097f, -0.497666954994202f, 0.547863483428955f,
-    -0.497703820466995f,
-  0.547481775283813f, -0.497740387916565f, 0.547099947929382f,
-    -0.497776657342911f,
-  0.546718180179596f, -0.497812628746033f, 0.546336352825165f,
-    -0.497848302125931f,
-  0.545954465866089f, -0.497883707284927f, 0.545572578907013f,
-    -0.497918814420700f,
-  0.545190691947937f, -0.497953623533249f, 0.544808745384216f,
-    -0.497988134622574f,
-  0.544426798820496f, -0.498022347688675f, 0.544044792652130f,
-    -0.498056292533875f,
-  0.543662786483765f, -0.498089909553528f, 0.543280720710754f,
-    -0.498123258352280f,
-  0.542898654937744f, -0.498156309127808f, 0.542516589164734f,
-    -0.498189061880112f,
-  0.542134463787079f, -0.498221516609192f, 0.541752278804779f,
-    -0.498253703117371f,
-  0.541370153427124f, -0.498285561800003f, 0.540987968444824f,
-    -0.498317152261734f,
-  0.540605723857880f, -0.498348444700241f, 0.540223479270935f,
-    -0.498379439115524f,
-  0.539841234683990f, -0.498410135507584f, 0.539458930492401f,
-    -0.498440563678741f,
-  0.539076626300812f, -0.498470664024353f, 0.538694262504578f,
-    -0.498500496149063f,
-  0.538311958312988f, -0.498530030250549f, 0.537929534912109f,
-    -0.498559266328812f,
-  0.537547171115875f, -0.498588204383850f, 0.537164747714996f,
-    -0.498616874217987f,
-  0.536782264709473f, -0.498645216226578f, 0.536399841308594f,
-    -0.498673290014267f,
-  0.536017298698425f, -0.498701065778732f, 0.535634815692902f,
-    -0.498728543519974f,
-  0.535252273082733f, -0.498755723237991f, 0.534869730472565f,
-    -0.498782604932785f,
-  0.534487187862396f, -0.498809218406677f, 0.534104585647583f,
-    -0.498835533857346f,
-  0.533721983432770f, -0.498861521482468f, 0.533339321613312f,
-    -0.498887240886688f,
-  0.532956659793854f, -0.498912662267685f, 0.532573997974396f,
-    -0.498937815427780f,
-  0.532191336154938f, -0.498962640762329f, 0.531808614730835f,
-    -0.498987197875977f,
-  0.531425893306732f, -0.499011427164078f, 0.531043112277985f,
-    -0.499035388231277f,
-  0.530660390853882f, -0.499059051275253f, 0.530277609825134f,
-    -0.499082416296005f,
-  0.529894769191742f, -0.499105513095856f, 0.529511988162994f,
-    -0.499128282070160f,
-  0.529129147529602f, -0.499150782823563f, 0.528746306896210f,
-    -0.499172955751419f,
-  0.528363406658173f, -0.499194860458374f, 0.527980506420136f,
-    -0.499216467142105f,
-  0.527597606182098f, -0.499237775802612f, 0.527214705944061f,
-    -0.499258816242218f,
-  0.526831746101379f, -0.499279528856277f, 0.526448845863342f,
-    -0.499299973249435f,
-  0.526065826416016f, -0.499320119619370f, 0.525682866573334f,
-    -0.499339967966080f,
-  0.525299847126007f, -0.499359518289566f, 0.524916887283325f,
-    -0.499378770589828f,
-  0.524533808231354f, -0.499397724866867f, 0.524150788784027f,
-    -0.499416410923004f,
-  0.523767769336700f, -0.499434769153595f, 0.523384690284729f,
-    -0.499452859163284f,
-  0.523001611232758f, -0.499470651149750f, 0.522618472576141f,
-    -0.499488145112991f,
-  0.522235393524170f, -0.499505341053009f, 0.521852254867554f,
-    -0.499522238969803f,
-  0.521469116210938f, -0.499538868665695f, 0.521085977554321f,
-    -0.499555170536041f,
-  0.520702838897705f, -0.499571204185486f, 0.520319640636444f,
-    -0.499586939811707f,
-  0.519936442375183f, -0.499602377414703f, 0.519553244113922f,
-    -0.499617516994476f,
-  0.519170045852661f, -0.499632388353348f, 0.518786847591400f,
-    -0.499646931886673f,
-  0.518403589725494f, -0.499661177396774f, 0.518020391464233f,
-    -0.499675154685974f,
-  0.517637133598328f, -0.499688833951950f, 0.517253875732422f,
-    -0.499702215194702f,
-  0.516870558261871f, -0.499715298414230f, 0.516487300395966f,
-    -0.499728083610535f,
-  0.516103982925415f, -0.499740600585938f, 0.515720725059509f,
-    -0.499752789735794f,
-  0.515337407588959f, -0.499764710664749f, 0.514954090118408f,
-    -0.499776333570480f,
-  0.514570772647858f, -0.499787658452988f, 0.514187395572662f,
-    -0.499798685312271f,
-  0.513804078102112f, -0.499809414148331f, 0.513420701026917f,
-    -0.499819844961166f,
-  0.513037383556366f, -0.499830007553101f, 0.512654006481171f,
-    -0.499839842319489f,
-  0.512270629405975f, -0.499849408864975f, 0.511887252330780f,
-    -0.499858677387238f,
-  0.511503815650940f, -0.499867647886276f, 0.511120438575745f,
-    -0.499876320362091f,
-  0.510737061500549f, -0.499884694814682f, 0.510353624820709f,
-    -0.499892801046371f,
-  0.509970188140869f, -0.499900579452515f, 0.509586811065674f,
-    -0.499908089637756f,
-  0.509203374385834f, -0.499915301799774f, 0.508819937705994f,
-    -0.499922215938568f,
-  0.508436501026154f, -0.499928832054138f, 0.508053064346313f,
-    -0.499935150146484f,
-  0.507669627666473f, -0.499941170215607f, 0.507286131381989f,
-    -0.499946922063828f,
-  0.506902694702148f, -0.499952346086502f, 0.506519258022308f,
-    -0.499957501888275f,
-  0.506135761737823f, -0.499962359666824f, 0.505752325057983f,
-    -0.499966919422150f,
-  0.505368828773499f, -0.499971181154251f, 0.504985332489014f,
-    -0.499975144863129f,
-  0.504601895809174f, -0.499978810548782f, 0.504218399524689f,
-    -0.499982208013535f,
-  0.503834903240204f, -0.499985307455063f, 0.503451406955719f,
-    -0.499988079071045f,
-  0.503067970275879f, -0.499990582466125f, 0.502684473991394f,
-    -0.499992787837982f,
-  0.502300977706909f, -0.499994695186615f, 0.501917481422424f,
-    -0.499996334314346f,
-  0.501533985137939f, -0.499997645616531f, 0.501150488853455f,
-    -0.499998688697815f,
-  0.500766992568970f, -0.499999403953552f, 0.500383496284485f,
-    -0.499999850988388f,
-};
-
-
-
-/**    
-* @brief  Initialization function for the floating-point RFFT/RIFFT.   
-* @param[in,out] *S             points to an instance of the floating-point RFFT/RIFFT structure.   
-* @param[in,out] *S_CFFT        points to an instance of the floating-point CFFT/CIFFT structure.   
-* @param[in]     fftLenReal     length of the FFT.   
-* @param[in]     ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.   
-* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.   
-* @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.   
-*    
-* \par Description:   
-* \par   
-* The parameter fftLenReal	Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048.    
-* \par    
-* The parameter ifftFlagR controls whether a forward or inverse transform is computed.    
-* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.    
-* \par    
-* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.    
-* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
-* \par    
-* This function also initializes Twiddle factor table.     
-*/
-
-arm_status arm_rfft_init_f32(
-  arm_rfft_instance_f32 * S,
-  arm_cfft_radix4_instance_f32 * S_CFFT,
-  uint32_t fftLenReal,
-  uint32_t ifftFlagR,
-  uint32_t bitReverseFlag)
-{
-
-  /*  Initialise the default arm status */
-  arm_status status = ARM_MATH_SUCCESS;
-
-  /*  Initialize the Real FFT length */
-  S->fftLenReal = (uint16_t) fftLenReal;
-
-  /*  Initialize the Complex FFT length */
-  S->fftLenBy2 = (uint16_t) fftLenReal / 2u;
-
-  /*  Initialize the Twiddle coefficientA pointer */
-  S->pTwiddleAReal = (float32_t *) realCoefA;
-
-  /*  Initialize the Twiddle coefficientB pointer */
-  S->pTwiddleBReal = (float32_t *) realCoefB;
-
-  /*  Initialize the Flag for selection of RFFT or RIFFT */
-  S->ifftFlagR = (uint8_t) ifftFlagR;
-
-  /*  Initialize the Flag for calculation Bit reversal or not */
-  S->bitReverseFlagR = (uint8_t) bitReverseFlag;
-
-  /*  Initializations of structure parameters depending on the FFT length */
-  switch (S->fftLenReal)
-  {
-    /* Init table modifier value */
-  case 8192u:
-    S->twidCoefRModifier = 1u;
-    break;
-  case 2048u:
-    S->twidCoefRModifier = 4u;
-    break;
-  case 512u:
-    S->twidCoefRModifier = 16u;
-    break;
-  case 128u:
-    S->twidCoefRModifier = 64u;
-    break;
-  default:
-    /*  Reporting argument error if rfftSize is not valid value */
-    status = ARM_MATH_ARGUMENT_ERROR;
-    break;
-  }
-
-  /* Init Complex FFT Instance */
-  S->pCfft = S_CFFT;
-
-  if(S->ifftFlagR)
-  {
-    /* Initializes the CIFFT Module for fftLenreal/2 length */
-    arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 1u, 0u);
-  }
-  else
-  {
-    /* Initializes the CFFT Module for fftLenreal/2 length */
-    arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 0u, 0u);
-  }
-
-  /* return the status of RFFT Init function */
-  return (status);
-
-}
-
-  /**    
-   * @} end of RFFT_RIFFT group    
-   */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q15.c
deleted file mode 100644
index 144b2d0c61..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q15.c
+++ /dev/null
@@ -1,2229 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_rfft_init_q15.c    
-*    
-* Description:	RFFT & RIFFT Q15 initialisation function    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* -------------------------------------------------------------------- */
-
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupTransforms    
- */
-
-/**    
- * @addtogroup RFFT_RIFFT    
- * @{    
- */
-
-
-
-/**    
-* \par    
-* Generation floating point real_CoefA array:    
-* \par    
-* n = 4096    
-* 
for (i = 0; i < n; i++)    
-*  {    
-*    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));    
-*    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    
-*  } 
    
-* \par    
-* Convert to fixed point Q15 format    
-*       round(pATable[i] * pow(2, 15))    
-*/
-
-
-static const q15_t ALIGN4 realCoefAQ15[8192] = {
-  0x4000, 0xc000, 0x3ff3, 0xc000, 0x3fe7, 0xc000, 0x3fda, 0xc000,
-  0x3fce, 0xc000, 0x3fc1, 0xc000, 0x3fb5, 0xc000, 0x3fa8, 0xc000,
-  0x3f9b, 0xc000, 0x3f8f, 0xc000, 0x3f82, 0xc000, 0x3f76, 0xc001,
-  0x3f69, 0xc001, 0x3f5d, 0xc001, 0x3f50, 0xc001, 0x3f44, 0xc001,
-  0x3f37, 0xc001, 0x3f2a, 0xc001, 0x3f1e, 0xc002, 0x3f11, 0xc002,
-  0x3f05, 0xc002, 0x3ef8, 0xc002, 0x3eec, 0xc002, 0x3edf, 0xc003,
-  0x3ed2, 0xc003, 0x3ec6, 0xc003, 0x3eb9, 0xc003, 0x3ead, 0xc004,
-  0x3ea0, 0xc004, 0x3e94, 0xc004, 0x3e87, 0xc004, 0x3e7a, 0xc005,
-  0x3e6e, 0xc005, 0x3e61, 0xc005, 0x3e55, 0xc006, 0x3e48, 0xc006,
-  0x3e3c, 0xc006, 0x3e2f, 0xc007, 0x3e23, 0xc007, 0x3e16, 0xc007,
-  0x3e09, 0xc008, 0x3dfd, 0xc008, 0x3df0, 0xc009, 0x3de4, 0xc009,
-  0x3dd7, 0xc009, 0x3dcb, 0xc00a, 0x3dbe, 0xc00a, 0x3db2, 0xc00b,
-  0x3da5, 0xc00b, 0x3d98, 0xc00c, 0x3d8c, 0xc00c, 0x3d7f, 0xc00d,
-  0x3d73, 0xc00d, 0x3d66, 0xc00e, 0x3d5a, 0xc00e, 0x3d4d, 0xc00f,
-  0x3d40, 0xc00f, 0x3d34, 0xc010, 0x3d27, 0xc010, 0x3d1b, 0xc011,
-  0x3d0e, 0xc011, 0x3d02, 0xc012, 0x3cf5, 0xc013, 0x3ce9, 0xc013,
-  0x3cdc, 0xc014, 0x3cd0, 0xc014, 0x3cc3, 0xc015, 0x3cb6, 0xc016,
-  0x3caa, 0xc016, 0x3c9d, 0xc017, 0x3c91, 0xc018, 0x3c84, 0xc018,
-  0x3c78, 0xc019, 0x3c6b, 0xc01a, 0x3c5f, 0xc01a, 0x3c52, 0xc01b,
-  0x3c45, 0xc01c, 0x3c39, 0xc01d, 0x3c2c, 0xc01d, 0x3c20, 0xc01e,
-  0x3c13, 0xc01f, 0x3c07, 0xc020, 0x3bfa, 0xc020, 0x3bee, 0xc021,
-  0x3be1, 0xc022, 0x3bd5, 0xc023, 0x3bc8, 0xc024, 0x3bbc, 0xc024,
-  0x3baf, 0xc025, 0x3ba2, 0xc026, 0x3b96, 0xc027, 0x3b89, 0xc028,
-  0x3b7d, 0xc029, 0x3b70, 0xc02a, 0x3b64, 0xc02b, 0x3b57, 0xc02b,
-  0x3b4b, 0xc02c, 0x3b3e, 0xc02d, 0x3b32, 0xc02e, 0x3b25, 0xc02f,
-  0x3b19, 0xc030, 0x3b0c, 0xc031, 0x3b00, 0xc032, 0x3af3, 0xc033,
-  0x3ae6, 0xc034, 0x3ada, 0xc035, 0x3acd, 0xc036, 0x3ac1, 0xc037,
-  0x3ab4, 0xc038, 0x3aa8, 0xc039, 0x3a9b, 0xc03a, 0x3a8f, 0xc03b,
-  0x3a82, 0xc03c, 0x3a76, 0xc03d, 0x3a69, 0xc03f, 0x3a5d, 0xc040,
-  0x3a50, 0xc041, 0x3a44, 0xc042, 0x3a37, 0xc043, 0x3a2b, 0xc044,
-  0x3a1e, 0xc045, 0x3a12, 0xc047, 0x3a05, 0xc048, 0x39f9, 0xc049,
-  0x39ec, 0xc04a, 0x39e0, 0xc04b, 0x39d3, 0xc04c, 0x39c7, 0xc04e,
-  0x39ba, 0xc04f, 0x39ae, 0xc050, 0x39a1, 0xc051, 0x3995, 0xc053,
-  0x3988, 0xc054, 0x397c, 0xc055, 0x396f, 0xc056, 0x3963, 0xc058,
-  0x3956, 0xc059, 0x394a, 0xc05a, 0x393d, 0xc05c, 0x3931, 0xc05d,
-  0x3924, 0xc05e, 0x3918, 0xc060, 0x390b, 0xc061, 0x38ff, 0xc062,
-  0x38f2, 0xc064, 0x38e6, 0xc065, 0x38d9, 0xc067, 0x38cd, 0xc068,
-  0x38c0, 0xc069, 0x38b4, 0xc06b, 0x38a7, 0xc06c, 0x389b, 0xc06e,
-  0x388e, 0xc06f, 0x3882, 0xc071, 0x3875, 0xc072, 0x3869, 0xc074,
-  0x385c, 0xc075, 0x3850, 0xc077, 0x3843, 0xc078, 0x3837, 0xc07a,
-  0x382a, 0xc07b, 0x381e, 0xc07d, 0x3811, 0xc07e, 0x3805, 0xc080,
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-  0x3795, 0xc08e, 0x3788, 0xc090, 0x377c, 0xc092, 0x376f, 0xc093,
-  0x3763, 0xc095, 0x3757, 0xc097, 0x374a, 0xc098, 0x373e, 0xc09a,
-  0x3731, 0xc09c, 0x3725, 0xc09e, 0x3718, 0xc09f, 0x370c, 0xc0a1,
-  0x36ff, 0xc0a3, 0x36f3, 0xc0a5, 0x36e7, 0xc0a6, 0x36da, 0xc0a8,
-  0x36ce, 0xc0aa, 0x36c1, 0xc0ac, 0x36b5, 0xc0ae, 0x36a8, 0xc0af,
-  0x369c, 0xc0b1, 0x3690, 0xc0b3, 0x3683, 0xc0b5, 0x3677, 0xc0b7,
-  0x366a, 0xc0b9, 0x365e, 0xc0bb, 0x3651, 0xc0bd, 0x3645, 0xc0be,
-  0x3639, 0xc0c0, 0x362c, 0xc0c2, 0x3620, 0xc0c4, 0x3613, 0xc0c6,
-  0x3607, 0xc0c8, 0x35fa, 0xc0ca, 0x35ee, 0xc0cc, 0x35e2, 0xc0ce,
-  0x35d5, 0xc0d0, 0x35c9, 0xc0d2, 0x35bc, 0xc0d4, 0x35b0, 0xc0d6,
-  0x35a4, 0xc0d8, 0x3597, 0xc0da, 0x358b, 0xc0dc, 0x357e, 0xc0de,
-  0x3572, 0xc0e0, 0x3566, 0xc0e2, 0x3559, 0xc0e4, 0x354d, 0xc0e7,
-  0x3540, 0xc0e9, 0x3534, 0xc0eb, 0x3528, 0xc0ed, 0x351b, 0xc0ef,
-  0x350f, 0xc0f1, 0x3503, 0xc0f3, 0x34f6, 0xc0f6, 0x34ea, 0xc0f8,
-  0x34dd, 0xc0fa, 0x34d1, 0xc0fc, 0x34c5, 0xc0fe, 0x34b8, 0xc100,
-  0x34ac, 0xc103, 0x34a0, 0xc105, 0x3493, 0xc107, 0x3487, 0xc109,
-  0x347b, 0xc10c, 0x346e, 0xc10e, 0x3462, 0xc110, 0x3455, 0xc113,
-  0x3449, 0xc115, 0x343d, 0xc117, 0x3430, 0xc119, 0x3424, 0xc11c,
-  0x3418, 0xc11e, 0x340b, 0xc120, 0x33ff, 0xc123, 0x33f3, 0xc125,
-  0x33e6, 0xc128, 0x33da, 0xc12a, 0x33ce, 0xc12c, 0x33c1, 0xc12f,
-  0x33b5, 0xc131, 0x33a9, 0xc134, 0x339c, 0xc136, 0x3390, 0xc138,
-  0x3384, 0xc13b, 0x3377, 0xc13d, 0x336b, 0xc140, 0x335f, 0xc142,
-  0x3352, 0xc145, 0x3346, 0xc147, 0x333a, 0xc14a, 0x332d, 0xc14c,
-  0x3321, 0xc14f, 0x3315, 0xc151, 0x3308, 0xc154, 0x32fc, 0xc156,
-  0x32f0, 0xc159, 0x32e4, 0xc15b, 0x32d7, 0xc15e, 0x32cb, 0xc161,
-  0x32bf, 0xc163, 0x32b2, 0xc166, 0x32a6, 0xc168, 0x329a, 0xc16b,
-  0x328e, 0xc16e, 0x3281, 0xc170, 0x3275, 0xc173, 0x3269, 0xc176,
-  0x325c, 0xc178, 0x3250, 0xc17b, 0x3244, 0xc17e, 0x3238, 0xc180,
-  0x322b, 0xc183, 0x321f, 0xc186, 0x3213, 0xc189, 0x3207, 0xc18b,
-  0x31fa, 0xc18e, 0x31ee, 0xc191, 0x31e2, 0xc194, 0x31d5, 0xc196,
-  0x31c9, 0xc199, 0x31bd, 0xc19c, 0x31b1, 0xc19f, 0x31a4, 0xc1a2,
-  0x3198, 0xc1a4, 0x318c, 0xc1a7, 0x3180, 0xc1aa, 0x3174, 0xc1ad,
-  0x3167, 0xc1b0, 0x315b, 0xc1b3, 0x314f, 0xc1b6, 0x3143, 0xc1b8,
-  0x3136, 0xc1bb, 0x312a, 0xc1be, 0x311e, 0xc1c1, 0x3112, 0xc1c4,
-  0x3105, 0xc1c7, 0x30f9, 0xc1ca, 0x30ed, 0xc1cd, 0x30e1, 0xc1d0,
-  0x30d5, 0xc1d3, 0x30c8, 0xc1d6, 0x30bc, 0xc1d9, 0x30b0, 0xc1dc,
-  0x30a4, 0xc1df, 0x3098, 0xc1e2, 0x308b, 0xc1e5, 0x307f, 0xc1e8,
-  0x3073, 0xc1eb, 0x3067, 0xc1ee, 0x305b, 0xc1f1, 0x304e, 0xc1f4,
-  0x3042, 0xc1f7, 0x3036, 0xc1fa, 0x302a, 0xc1fd, 0x301e, 0xc201,
-  0x3012, 0xc204, 0x3005, 0xc207, 0x2ff9, 0xc20a, 0x2fed, 0xc20d,
-  0x2fe1, 0xc210, 0x2fd5, 0xc213, 0x2fc9, 0xc217, 0x2fbc, 0xc21a,
-  0x2fb0, 0xc21d, 0x2fa4, 0xc220, 0x2f98, 0xc223, 0x2f8c, 0xc227,
-  0x2f80, 0xc22a, 0x2f74, 0xc22d, 0x2f67, 0xc230, 0x2f5b, 0xc234,
-  0x2f4f, 0xc237, 0x2f43, 0xc23a, 0x2f37, 0xc23e, 0x2f2b, 0xc241,
-  0x2f1f, 0xc244, 0x2f13, 0xc247, 0x2f06, 0xc24b, 0x2efa, 0xc24e,
-  0x2eee, 0xc251, 0x2ee2, 0xc255, 0x2ed6, 0xc258, 0x2eca, 0xc25c,
-  0x2ebe, 0xc25f, 0x2eb2, 0xc262, 0x2ea6, 0xc266, 0x2e99, 0xc269,
-  0x2e8d, 0xc26d, 0x2e81, 0xc270, 0x2e75, 0xc273, 0x2e69, 0xc277,
-  0x2e5d, 0xc27a, 0x2e51, 0xc27e, 0x2e45, 0xc281, 0x2e39, 0xc285,
-  0x2e2d, 0xc288, 0x2e21, 0xc28c, 0x2e15, 0xc28f, 0x2e09, 0xc293,
-  0x2dfc, 0xc296, 0x2df0, 0xc29a, 0x2de4, 0xc29d, 0x2dd8, 0xc2a1,
-  0x2dcc, 0xc2a5, 0x2dc0, 0xc2a8, 0x2db4, 0xc2ac, 0x2da8, 0xc2af,
-  0x2d9c, 0xc2b3, 0x2d90, 0xc2b7, 0x2d84, 0xc2ba, 0x2d78, 0xc2be,
-  0x2d6c, 0xc2c1, 0x2d60, 0xc2c5, 0x2d54, 0xc2c9, 0x2d48, 0xc2cc,
-  0x2d3c, 0xc2d0, 0x2d30, 0xc2d4, 0x2d24, 0xc2d8, 0x2d18, 0xc2db,
-  0x2d0c, 0xc2df, 0x2d00, 0xc2e3, 0x2cf4, 0xc2e6, 0x2ce8, 0xc2ea,
-  0x2cdc, 0xc2ee, 0x2cd0, 0xc2f2, 0x2cc4, 0xc2f5, 0x2cb8, 0xc2f9,
-  0x2cac, 0xc2fd, 0x2ca0, 0xc301, 0x2c94, 0xc305, 0x2c88, 0xc308,
-  0x2c7c, 0xc30c, 0x2c70, 0xc310, 0x2c64, 0xc314, 0x2c58, 0xc318,
-  0x2c4c, 0xc31c, 0x2c40, 0xc320, 0x2c34, 0xc323, 0x2c28, 0xc327,
-  0x2c1c, 0xc32b, 0x2c10, 0xc32f, 0x2c05, 0xc333, 0x2bf9, 0xc337,
-  0x2bed, 0xc33b, 0x2be1, 0xc33f, 0x2bd5, 0xc343, 0x2bc9, 0xc347,
-  0x2bbd, 0xc34b, 0x2bb1, 0xc34f, 0x2ba5, 0xc353, 0x2b99, 0xc357,
-  0x2b8d, 0xc35b, 0x2b81, 0xc35f, 0x2b75, 0xc363, 0x2b6a, 0xc367,
-  0x2b5e, 0xc36b, 0x2b52, 0xc36f, 0x2b46, 0xc373, 0x2b3a, 0xc377,
-  0x2b2e, 0xc37b, 0x2b22, 0xc37f, 0x2b16, 0xc383, 0x2b0a, 0xc387,
-  0x2aff, 0xc38c, 0x2af3, 0xc390, 0x2ae7, 0xc394, 0x2adb, 0xc398,
-  0x2acf, 0xc39c, 0x2ac3, 0xc3a0, 0x2ab7, 0xc3a5, 0x2aac, 0xc3a9,
-  0x2aa0, 0xc3ad, 0x2a94, 0xc3b1, 0x2a88, 0xc3b5, 0x2a7c, 0xc3ba,
-  0x2a70, 0xc3be, 0x2a65, 0xc3c2, 0x2a59, 0xc3c6, 0x2a4d, 0xc3ca,
-  0x2a41, 0xc3cf, 0x2a35, 0xc3d3, 0x2a29, 0xc3d7, 0x2a1e, 0xc3dc,
-  0x2a12, 0xc3e0, 0x2a06, 0xc3e4, 0x29fa, 0xc3e9, 0x29ee, 0xc3ed,
-  0x29e3, 0xc3f1, 0x29d7, 0xc3f6, 0x29cb, 0xc3fa, 0x29bf, 0xc3fe,
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-  0x289a, 0xc46e, 0x288e, 0xc473, 0x2882, 0xc478, 0x2877, 0xc47c,
-  0x286b, 0xc481, 0x285f, 0xc485, 0x2854, 0xc48a, 0x2848, 0xc48f,
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-  0x27b1, 0xc4cc, 0x27a5, 0xc4d1, 0x2799, 0xc4d6, 0x278e, 0xc4da,
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-  0x222d, 0xc75f, 0x2222, 0xc765, 0x2217, 0xc76b, 0x220c, 0xc771,
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-  0x21a8, 0xc7a6, 0x219d, 0xc7ac, 0x2192, 0xc7b2, 0x2187, 0xc7b8,
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-  0x2150, 0xc7d6, 0x2145, 0xc7dc, 0x213a, 0xc7e2, 0x212f, 0xc7e8,
-  0x2124, 0xc7ee, 0x2119, 0xc7f5, 0x210e, 0xc7fb, 0x2103, 0xc801,
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-  0x20cc, 0xc81f, 0x20c1, 0xc825, 0x20b6, 0xc82b, 0x20ab, 0xc832,
-  0x20a0, 0xc838, 0x2095, 0xc83e, 0x208a, 0xc844, 0x207f, 0xc84a,
-  0x2074, 0xc850, 0x2069, 0xc857, 0x205e, 0xc85d, 0x2054, 0xc863,
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-  0x1fc6, 0xc8b5, 0x1fbb, 0xc8bb, 0x1fb0, 0xc8c1, 0x1fa5, 0xc8c8,
-  0x1f9b, 0xc8ce, 0x1f90, 0xc8d4, 0x1f85, 0xc8db, 0x1f7a, 0xc8e1,
-  0x1f6f, 0xc8e8, 0x1f65, 0xc8ee, 0x1f5a, 0xc8f4, 0x1f4f, 0xc8fb,
-  0x1f44, 0xc901, 0x1f39, 0xc908, 0x1f2f, 0xc90e, 0x1f24, 0xc915,
-  0x1f19, 0xc91b, 0x1f0e, 0xc921, 0x1f03, 0xc928, 0x1ef9, 0xc92e,
-  0x1eee, 0xc935, 0x1ee3, 0xc93b, 0x1ed8, 0xc942, 0x1ece, 0xc948,
-  0x1ec3, 0xc94f, 0x1eb8, 0xc955, 0x1ead, 0xc95c, 0x1ea3, 0xc963,
-  0x1e98, 0xc969, 0x1e8d, 0xc970, 0x1e83, 0xc976, 0x1e78, 0xc97d,
-  0x1e6d, 0xc983, 0x1e62, 0xc98a, 0x1e58, 0xc991, 0x1e4d, 0xc997,
-  0x1e42, 0xc99e, 0x1e38, 0xc9a4, 0x1e2d, 0xc9ab, 0x1e22, 0xc9b2,
-  0x1e18, 0xc9b8, 0x1e0d, 0xc9bf, 0x1e02, 0xc9c6, 0x1df8, 0xc9cc,
-  0x1ded, 0xc9d3, 0x1de2, 0xc9da, 0x1dd8, 0xc9e0, 0x1dcd, 0xc9e7,
-  0x1dc3, 0xc9ee, 0x1db8, 0xc9f5, 0x1dad, 0xc9fb, 0x1da3, 0xca02,
-  0x1d98, 0xca09, 0x1d8e, 0xca10, 0x1d83, 0xca16, 0x1d78, 0xca1d,
-  0x1d6e, 0xca24, 0x1d63, 0xca2b, 0x1d59, 0xca32, 0x1d4e, 0xca38,
-  0x1d44, 0xca3f, 0x1d39, 0xca46, 0x1d2e, 0xca4d, 0x1d24, 0xca54,
-  0x1d19, 0xca5b, 0x1d0f, 0xca61, 0x1d04, 0xca68, 0x1cfa, 0xca6f,
-  0x1cef, 0xca76, 0x1ce5, 0xca7d, 0x1cda, 0xca84, 0x1cd0, 0xca8b,
-  0x1cc5, 0xca92, 0x1cbb, 0xca99, 0x1cb0, 0xca9f, 0x1ca6, 0xcaa6,
-  0x1c9b, 0xcaad, 0x1c91, 0xcab4, 0x1c86, 0xcabb, 0x1c7c, 0xcac2,
-  0x1c72, 0xcac9, 0x1c67, 0xcad0, 0x1c5d, 0xcad7, 0x1c52, 0xcade,
-  0x1c48, 0xcae5, 0x1c3d, 0xcaec, 0x1c33, 0xcaf3, 0x1c29, 0xcafa,
-  0x1c1e, 0xcb01, 0x1c14, 0xcb08, 0x1c09, 0xcb0f, 0x1bff, 0xcb16,
-  0x1bf5, 0xcb1e, 0x1bea, 0xcb25, 0x1be0, 0xcb2c, 0x1bd5, 0xcb33,
-  0x1bcb, 0xcb3a, 0x1bc1, 0xcb41, 0x1bb6, 0xcb48, 0x1bac, 0xcb4f,
-  0x1ba2, 0xcb56, 0x1b97, 0xcb5e, 0x1b8d, 0xcb65, 0x1b83, 0xcb6c,
-  0x1b78, 0xcb73, 0x1b6e, 0xcb7a, 0x1b64, 0xcb81, 0x1b59, 0xcb89,
-  0x1b4f, 0xcb90, 0x1b45, 0xcb97, 0x1b3b, 0xcb9e, 0x1b30, 0xcba5,
-  0x1b26, 0xcbad, 0x1b1c, 0xcbb4, 0x1b11, 0xcbbb, 0x1b07, 0xcbc2,
-  0x1afd, 0xcbca, 0x1af3, 0xcbd1, 0x1ae8, 0xcbd8, 0x1ade, 0xcbe0,
-  0x1ad4, 0xcbe7, 0x1aca, 0xcbee, 0x1abf, 0xcbf5, 0x1ab5, 0xcbfd,
-  0x1aab, 0xcc04, 0x1aa1, 0xcc0b, 0x1a97, 0xcc13, 0x1a8c, 0xcc1a,
-  0x1a82, 0xcc21, 0x1a78, 0xcc29, 0x1a6e, 0xcc30, 0x1a64, 0xcc38,
-  0x1a5a, 0xcc3f, 0x1a4f, 0xcc46, 0x1a45, 0xcc4e, 0x1a3b, 0xcc55,
-  0x1a31, 0xcc5d, 0x1a27, 0xcc64, 0x1a1d, 0xcc6b, 0x1a13, 0xcc73,
-  0x1a08, 0xcc7a, 0x19fe, 0xcc82, 0x19f4, 0xcc89, 0x19ea, 0xcc91,
-  0x19e0, 0xcc98, 0x19d6, 0xcca0, 0x19cc, 0xcca7, 0x19c2, 0xccaf,
-  0x19b8, 0xccb6, 0x19ae, 0xccbe, 0x19a4, 0xccc5, 0x199a, 0xcccd,
-  0x198f, 0xccd4, 0x1985, 0xccdc, 0x197b, 0xcce3, 0x1971, 0xcceb,
-  0x1967, 0xccf3, 0x195d, 0xccfa, 0x1953, 0xcd02, 0x1949, 0xcd09,
-  0x193f, 0xcd11, 0x1935, 0xcd19, 0x192b, 0xcd20, 0x1921, 0xcd28,
-  0x1917, 0xcd30, 0x190d, 0xcd37, 0x1903, 0xcd3f, 0x18f9, 0xcd46,
-  0x18ef, 0xcd4e, 0x18e6, 0xcd56, 0x18dc, 0xcd5d, 0x18d2, 0xcd65,
-  0x18c8, 0xcd6d, 0x18be, 0xcd75, 0x18b4, 0xcd7c, 0x18aa, 0xcd84,
-  0x18a0, 0xcd8c, 0x1896, 0xcd93, 0x188c, 0xcd9b, 0x1882, 0xcda3,
-  0x1878, 0xcdab, 0x186f, 0xcdb2, 0x1865, 0xcdba, 0x185b, 0xcdc2,
-  0x1851, 0xcdca, 0x1847, 0xcdd2, 0x183d, 0xcdd9, 0x1833, 0xcde1,
-  0x182a, 0xcde9, 0x1820, 0xcdf1, 0x1816, 0xcdf9, 0x180c, 0xce01,
-  0x1802, 0xce08, 0x17f8, 0xce10, 0x17ef, 0xce18, 0x17e5, 0xce20,
-  0x17db, 0xce28, 0x17d1, 0xce30, 0x17c8, 0xce38, 0x17be, 0xce40,
-  0x17b4, 0xce47, 0x17aa, 0xce4f, 0x17a0, 0xce57, 0x1797, 0xce5f,
-  0x178d, 0xce67, 0x1783, 0xce6f, 0x177a, 0xce77, 0x1770, 0xce7f,
-  0x1766, 0xce87, 0x175c, 0xce8f, 0x1753, 0xce97, 0x1749, 0xce9f,
-  0x173f, 0xcea7, 0x1736, 0xceaf, 0x172c, 0xceb7, 0x1722, 0xcebf,
-  0x1719, 0xcec7, 0x170f, 0xcecf, 0x1705, 0xced7, 0x16fc, 0xcedf,
-  0x16f2, 0xcee7, 0x16e8, 0xceef, 0x16df, 0xcef7, 0x16d5, 0xceff,
-  0x16cb, 0xcf07, 0x16c2, 0xcf10, 0x16b8, 0xcf18, 0x16af, 0xcf20,
-  0x16a5, 0xcf28, 0x169b, 0xcf30, 0x1692, 0xcf38, 0x1688, 0xcf40,
-  0x167f, 0xcf48, 0x1675, 0xcf51, 0x166c, 0xcf59, 0x1662, 0xcf61,
-  0x1659, 0xcf69, 0x164f, 0xcf71, 0x1645, 0xcf79, 0x163c, 0xcf82,
-  0x1632, 0xcf8a, 0x1629, 0xcf92, 0x161f, 0xcf9a, 0x1616, 0xcfa3,
-  0x160c, 0xcfab, 0x1603, 0xcfb3, 0x15f9, 0xcfbb, 0x15f0, 0xcfc4,
-  0x15e6, 0xcfcc, 0x15dd, 0xcfd4, 0x15d4, 0xcfdc, 0x15ca, 0xcfe5,
-  0x15c1, 0xcfed, 0x15b7, 0xcff5, 0x15ae, 0xcffe, 0x15a4, 0xd006,
-  0x159b, 0xd00e, 0x1592, 0xd016, 0x1588, 0xd01f, 0x157f, 0xd027,
-  0x1575, 0xd030, 0x156c, 0xd038, 0x1563, 0xd040, 0x1559, 0xd049,
-  0x1550, 0xd051, 0x1547, 0xd059, 0x153d, 0xd062, 0x1534, 0xd06a,
-  0x152a, 0xd073, 0x1521, 0xd07b, 0x1518, 0xd083, 0x150e, 0xd08c,
-  0x1505, 0xd094, 0x14fc, 0xd09d, 0x14f3, 0xd0a5, 0x14e9, 0xd0ae,
-  0x14e0, 0xd0b6, 0x14d7, 0xd0bf, 0x14cd, 0xd0c7, 0x14c4, 0xd0d0,
-  0x14bb, 0xd0d8, 0x14b2, 0xd0e0, 0x14a8, 0xd0e9, 0x149f, 0xd0f2,
-  0x1496, 0xd0fa, 0x148d, 0xd103, 0x1483, 0xd10b, 0x147a, 0xd114,
-  0x1471, 0xd11c, 0x1468, 0xd125, 0x145f, 0xd12d, 0x1455, 0xd136,
-  0x144c, 0xd13e, 0x1443, 0xd147, 0x143a, 0xd150, 0x1431, 0xd158,
-  0x1428, 0xd161, 0x141e, 0xd169, 0x1415, 0xd172, 0x140c, 0xd17b,
-  0x1403, 0xd183, 0x13fa, 0xd18c, 0x13f1, 0xd195, 0x13e8, 0xd19d,
-  0x13df, 0xd1a6, 0x13d5, 0xd1af, 0x13cc, 0xd1b7, 0x13c3, 0xd1c0,
-  0x13ba, 0xd1c9, 0x13b1, 0xd1d1, 0x13a8, 0xd1da, 0x139f, 0xd1e3,
-  0x1396, 0xd1eb, 0x138d, 0xd1f4, 0x1384, 0xd1fd, 0x137b, 0xd206,
-  0x1372, 0xd20e, 0x1369, 0xd217, 0x1360, 0xd220, 0x1357, 0xd229,
-  0x134e, 0xd231, 0x1345, 0xd23a, 0x133c, 0xd243, 0x1333, 0xd24c,
-  0x132a, 0xd255, 0x1321, 0xd25d, 0x1318, 0xd266, 0x130f, 0xd26f,
-  0x1306, 0xd278, 0x12fd, 0xd281, 0x12f4, 0xd28a, 0x12eb, 0xd292,
-  0x12e2, 0xd29b, 0x12d9, 0xd2a4, 0x12d1, 0xd2ad, 0x12c8, 0xd2b6,
-  0x12bf, 0xd2bf, 0x12b6, 0xd2c8, 0x12ad, 0xd2d1, 0x12a4, 0xd2d9,
-  0x129b, 0xd2e2, 0x1292, 0xd2eb, 0x128a, 0xd2f4, 0x1281, 0xd2fd,
-  0x1278, 0xd306, 0x126f, 0xd30f, 0x1266, 0xd318, 0x125d, 0xd321,
-  0x1255, 0xd32a, 0x124c, 0xd333, 0x1243, 0xd33c, 0x123a, 0xd345,
-  0x1231, 0xd34e, 0x1229, 0xd357, 0x1220, 0xd360, 0x1217, 0xd369,
-  0x120e, 0xd372, 0x1206, 0xd37b, 0x11fd, 0xd384, 0x11f4, 0xd38d,
-  0x11eb, 0xd396, 0x11e3, 0xd39f, 0x11da, 0xd3a8, 0x11d1, 0xd3b1,
-  0x11c9, 0xd3ba, 0x11c0, 0xd3c3, 0x11b7, 0xd3cc, 0x11af, 0xd3d5,
-  0x11a6, 0xd3df, 0x119d, 0xd3e8, 0x1195, 0xd3f1, 0x118c, 0xd3fa,
-  0x1183, 0xd403, 0x117b, 0xd40c, 0x1172, 0xd415, 0x1169, 0xd41e,
-  0x1161, 0xd428, 0x1158, 0xd431, 0x1150, 0xd43a, 0x1147, 0xd443,
-  0x113e, 0xd44c, 0x1136, 0xd455, 0x112d, 0xd45f, 0x1125, 0xd468,
-  0x111c, 0xd471, 0x1114, 0xd47a, 0x110b, 0xd483, 0x1103, 0xd48d,
-  0x10fa, 0xd496, 0x10f2, 0xd49f, 0x10e9, 0xd4a8, 0x10e0, 0xd4b2,
-  0x10d8, 0xd4bb, 0x10d0, 0xd4c4, 0x10c7, 0xd4cd, 0x10bf, 0xd4d7,
-  0x10b6, 0xd4e0, 0x10ae, 0xd4e9, 0x10a5, 0xd4f3, 0x109d, 0xd4fc,
-  0x1094, 0xd505, 0x108c, 0xd50e, 0x1083, 0xd518, 0x107b, 0xd521,
-  0x1073, 0xd52a, 0x106a, 0xd534, 0x1062, 0xd53d, 0x1059, 0xd547,
-  0x1051, 0xd550, 0x1049, 0xd559, 0x1040, 0xd563, 0x1038, 0xd56c,
-  0x1030, 0xd575, 0x1027, 0xd57f, 0x101f, 0xd588, 0x1016, 0xd592,
-  0x100e, 0xd59b, 0x1006, 0xd5a4, 0xffe, 0xd5ae, 0xff5, 0xd5b7,
-  0xfed, 0xd5c1, 0xfe5, 0xd5ca, 0xfdc, 0xd5d4, 0xfd4, 0xd5dd,
-  0xfcc, 0xd5e6, 0xfc4, 0xd5f0, 0xfbb, 0xd5f9, 0xfb3, 0xd603,
-  0xfab, 0xd60c, 0xfa3, 0xd616, 0xf9a, 0xd61f, 0xf92, 0xd629,
-  0xf8a, 0xd632, 0xf82, 0xd63c, 0xf79, 0xd645, 0xf71, 0xd64f,
-  0xf69, 0xd659, 0xf61, 0xd662, 0xf59, 0xd66c, 0xf51, 0xd675,
-  0xf48, 0xd67f, 0xf40, 0xd688, 0xf38, 0xd692, 0xf30, 0xd69b,
-  0xf28, 0xd6a5, 0xf20, 0xd6af, 0xf18, 0xd6b8, 0xf10, 0xd6c2,
-  0xf07, 0xd6cb, 0xeff, 0xd6d5, 0xef7, 0xd6df, 0xeef, 0xd6e8,
-  0xee7, 0xd6f2, 0xedf, 0xd6fc, 0xed7, 0xd705, 0xecf, 0xd70f,
-  0xec7, 0xd719, 0xebf, 0xd722, 0xeb7, 0xd72c, 0xeaf, 0xd736,
-  0xea7, 0xd73f, 0xe9f, 0xd749, 0xe97, 0xd753, 0xe8f, 0xd75c,
-  0xe87, 0xd766, 0xe7f, 0xd770, 0xe77, 0xd77a, 0xe6f, 0xd783,
-  0xe67, 0xd78d, 0xe5f, 0xd797, 0xe57, 0xd7a0, 0xe4f, 0xd7aa,
-  0xe47, 0xd7b4, 0xe40, 0xd7be, 0xe38, 0xd7c8, 0xe30, 0xd7d1,
-  0xe28, 0xd7db, 0xe20, 0xd7e5, 0xe18, 0xd7ef, 0xe10, 0xd7f8,
-  0xe08, 0xd802, 0xe01, 0xd80c, 0xdf9, 0xd816, 0xdf1, 0xd820,
-  0xde9, 0xd82a, 0xde1, 0xd833, 0xdd9, 0xd83d, 0xdd2, 0xd847,
-  0xdca, 0xd851, 0xdc2, 0xd85b, 0xdba, 0xd865, 0xdb2, 0xd86f,
-  0xdab, 0xd878, 0xda3, 0xd882, 0xd9b, 0xd88c, 0xd93, 0xd896,
-  0xd8c, 0xd8a0, 0xd84, 0xd8aa, 0xd7c, 0xd8b4, 0xd75, 0xd8be,
-  0xd6d, 0xd8c8, 0xd65, 0xd8d2, 0xd5d, 0xd8dc, 0xd56, 0xd8e6,
-  0xd4e, 0xd8ef, 0xd46, 0xd8f9, 0xd3f, 0xd903, 0xd37, 0xd90d,
-  0xd30, 0xd917, 0xd28, 0xd921, 0xd20, 0xd92b, 0xd19, 0xd935,
-  0xd11, 0xd93f, 0xd09, 0xd949, 0xd02, 0xd953, 0xcfa, 0xd95d,
-  0xcf3, 0xd967, 0xceb, 0xd971, 0xce3, 0xd97b, 0xcdc, 0xd985,
-  0xcd4, 0xd98f, 0xccd, 0xd99a, 0xcc5, 0xd9a4, 0xcbe, 0xd9ae,
-  0xcb6, 0xd9b8, 0xcaf, 0xd9c2, 0xca7, 0xd9cc, 0xca0, 0xd9d6,
-  0xc98, 0xd9e0, 0xc91, 0xd9ea, 0xc89, 0xd9f4, 0xc82, 0xd9fe,
-  0xc7a, 0xda08, 0xc73, 0xda13, 0xc6b, 0xda1d, 0xc64, 0xda27,
-  0xc5d, 0xda31, 0xc55, 0xda3b, 0xc4e, 0xda45, 0xc46, 0xda4f,
-  0xc3f, 0xda5a, 0xc38, 0xda64, 0xc30, 0xda6e, 0xc29, 0xda78,
-  0xc21, 0xda82, 0xc1a, 0xda8c, 0xc13, 0xda97, 0xc0b, 0xdaa1,
-  0xc04, 0xdaab, 0xbfd, 0xdab5, 0xbf5, 0xdabf, 0xbee, 0xdaca,
-  0xbe7, 0xdad4, 0xbe0, 0xdade, 0xbd8, 0xdae8, 0xbd1, 0xdaf3,
-  0xbca, 0xdafd, 0xbc2, 0xdb07, 0xbbb, 0xdb11, 0xbb4, 0xdb1c,
-  0xbad, 0xdb26, 0xba5, 0xdb30, 0xb9e, 0xdb3b, 0xb97, 0xdb45,
-  0xb90, 0xdb4f, 0xb89, 0xdb59, 0xb81, 0xdb64, 0xb7a, 0xdb6e,
-  0xb73, 0xdb78, 0xb6c, 0xdb83, 0xb65, 0xdb8d, 0xb5e, 0xdb97,
-  0xb56, 0xdba2, 0xb4f, 0xdbac, 0xb48, 0xdbb6, 0xb41, 0xdbc1,
-  0xb3a, 0xdbcb, 0xb33, 0xdbd5, 0xb2c, 0xdbe0, 0xb25, 0xdbea,
-  0xb1e, 0xdbf5, 0xb16, 0xdbff, 0xb0f, 0xdc09, 0xb08, 0xdc14,
-  0xb01, 0xdc1e, 0xafa, 0xdc29, 0xaf3, 0xdc33, 0xaec, 0xdc3d,
-  0xae5, 0xdc48, 0xade, 0xdc52, 0xad7, 0xdc5d, 0xad0, 0xdc67,
-  0xac9, 0xdc72, 0xac2, 0xdc7c, 0xabb, 0xdc86, 0xab4, 0xdc91,
-  0xaad, 0xdc9b, 0xaa6, 0xdca6, 0xa9f, 0xdcb0, 0xa99, 0xdcbb,
-  0xa92, 0xdcc5, 0xa8b, 0xdcd0, 0xa84, 0xdcda, 0xa7d, 0xdce5,
-  0xa76, 0xdcef, 0xa6f, 0xdcfa, 0xa68, 0xdd04, 0xa61, 0xdd0f,
-  0xa5b, 0xdd19, 0xa54, 0xdd24, 0xa4d, 0xdd2e, 0xa46, 0xdd39,
-  0xa3f, 0xdd44, 0xa38, 0xdd4e, 0xa32, 0xdd59, 0xa2b, 0xdd63,
-  0xa24, 0xdd6e, 0xa1d, 0xdd78, 0xa16, 0xdd83, 0xa10, 0xdd8e,
-  0xa09, 0xdd98, 0xa02, 0xdda3, 0x9fb, 0xddad, 0x9f5, 0xddb8,
-  0x9ee, 0xddc3, 0x9e7, 0xddcd, 0x9e0, 0xddd8, 0x9da, 0xdde2,
-  0x9d3, 0xdded, 0x9cc, 0xddf8, 0x9c6, 0xde02, 0x9bf, 0xde0d,
-  0x9b8, 0xde18, 0x9b2, 0xde22, 0x9ab, 0xde2d, 0x9a4, 0xde38,
-  0x99e, 0xde42, 0x997, 0xde4d, 0x991, 0xde58, 0x98a, 0xde62,
-  0x983, 0xde6d, 0x97d, 0xde78, 0x976, 0xde83, 0x970, 0xde8d,
-  0x969, 0xde98, 0x963, 0xdea3, 0x95c, 0xdead, 0x955, 0xdeb8,
-  0x94f, 0xdec3, 0x948, 0xdece, 0x942, 0xded8, 0x93b, 0xdee3,
-  0x935, 0xdeee, 0x92e, 0xdef9, 0x928, 0xdf03, 0x921, 0xdf0e,
-  0x91b, 0xdf19, 0x915, 0xdf24, 0x90e, 0xdf2f, 0x908, 0xdf39,
-  0x901, 0xdf44, 0x8fb, 0xdf4f, 0x8f4, 0xdf5a, 0x8ee, 0xdf65,
-  0x8e8, 0xdf6f, 0x8e1, 0xdf7a, 0x8db, 0xdf85, 0x8d4, 0xdf90,
-  0x8ce, 0xdf9b, 0x8c8, 0xdfa5, 0x8c1, 0xdfb0, 0x8bb, 0xdfbb,
-  0x8b5, 0xdfc6, 0x8ae, 0xdfd1, 0x8a8, 0xdfdc, 0x8a2, 0xdfe7,
-  0x89b, 0xdff1, 0x895, 0xdffc, 0x88f, 0xe007, 0x889, 0xe012,
-  0x882, 0xe01d, 0x87c, 0xe028, 0x876, 0xe033, 0x870, 0xe03e,
-  0x869, 0xe049, 0x863, 0xe054, 0x85d, 0xe05e, 0x857, 0xe069,
-  0x850, 0xe074, 0x84a, 0xe07f, 0x844, 0xe08a, 0x83e, 0xe095,
-  0x838, 0xe0a0, 0x832, 0xe0ab, 0x82b, 0xe0b6, 0x825, 0xe0c1,
-  0x81f, 0xe0cc, 0x819, 0xe0d7, 0x813, 0xe0e2, 0x80d, 0xe0ed,
-  0x807, 0xe0f8, 0x801, 0xe103, 0x7fb, 0xe10e, 0x7f5, 0xe119,
-  0x7ee, 0xe124, 0x7e8, 0xe12f, 0x7e2, 0xe13a, 0x7dc, 0xe145,
-  0x7d6, 0xe150, 0x7d0, 0xe15b, 0x7ca, 0xe166, 0x7c4, 0xe171,
-  0x7be, 0xe17c, 0x7b8, 0xe187, 0x7b2, 0xe192, 0x7ac, 0xe19d,
-  0x7a6, 0xe1a8, 0x7a0, 0xe1b3, 0x79a, 0xe1be, 0x795, 0xe1ca,
-  0x78f, 0xe1d5, 0x789, 0xe1e0, 0x783, 0xe1eb, 0x77d, 0xe1f6,
-  0x777, 0xe201, 0x771, 0xe20c, 0x76b, 0xe217, 0x765, 0xe222,
-  0x75f, 0xe22d, 0x75a, 0xe239, 0x754, 0xe244, 0x74e, 0xe24f,
-  0x748, 0xe25a, 0x742, 0xe265, 0x73d, 0xe270, 0x737, 0xe27b,
-  0x731, 0xe287, 0x72b, 0xe292, 0x725, 0xe29d, 0x720, 0xe2a8,
-  0x71a, 0xe2b3, 0x714, 0xe2be, 0x70e, 0xe2ca, 0x709, 0xe2d5,
-  0x703, 0xe2e0, 0x6fd, 0xe2eb, 0x6f7, 0xe2f6, 0x6f2, 0xe301,
-  0x6ec, 0xe30d, 0x6e6, 0xe318, 0x6e1, 0xe323, 0x6db, 0xe32e,
-  0x6d5, 0xe33a, 0x6d0, 0xe345, 0x6ca, 0xe350, 0x6c5, 0xe35b,
-  0x6bf, 0xe367, 0x6b9, 0xe372, 0x6b4, 0xe37d, 0x6ae, 0xe388,
-  0x6a8, 0xe394, 0x6a3, 0xe39f, 0x69d, 0xe3aa, 0x698, 0xe3b5,
-  0x692, 0xe3c1, 0x68d, 0xe3cc, 0x687, 0xe3d7, 0x682, 0xe3e2,
-  0x67c, 0xe3ee, 0x677, 0xe3f9, 0x671, 0xe404, 0x66c, 0xe410,
-  0x666, 0xe41b, 0x661, 0xe426, 0x65b, 0xe432, 0x656, 0xe43d,
-  0x650, 0xe448, 0x64b, 0xe454, 0x645, 0xe45f, 0x640, 0xe46a,
-  0x63b, 0xe476, 0x635, 0xe481, 0x630, 0xe48c, 0x62a, 0xe498,
-  0x625, 0xe4a3, 0x620, 0xe4ae, 0x61a, 0xe4ba, 0x615, 0xe4c5,
-  0x610, 0xe4d0, 0x60a, 0xe4dc, 0x605, 0xe4e7, 0x600, 0xe4f3,
-  0x5fa, 0xe4fe, 0x5f5, 0xe509, 0x5f0, 0xe515, 0x5ea, 0xe520,
-  0x5e5, 0xe52c, 0x5e0, 0xe537, 0x5db, 0xe542, 0x5d5, 0xe54e,
-  0x5d0, 0xe559, 0x5cb, 0xe565, 0x5c6, 0xe570, 0x5c1, 0xe57c,
-  0x5bb, 0xe587, 0x5b6, 0xe592, 0x5b1, 0xe59e, 0x5ac, 0xe5a9,
-  0x5a7, 0xe5b5, 0x5a1, 0xe5c0, 0x59c, 0xe5cc, 0x597, 0xe5d7,
-  0x592, 0xe5e3, 0x58d, 0xe5ee, 0x588, 0xe5fa, 0x583, 0xe605,
-  0x57e, 0xe611, 0x578, 0xe61c, 0x573, 0xe628, 0x56e, 0xe633,
-  0x569, 0xe63f, 0x564, 0xe64a, 0x55f, 0xe656, 0x55a, 0xe661,
-  0x555, 0xe66d, 0x550, 0xe678, 0x54b, 0xe684, 0x546, 0xe68f,
-  0x541, 0xe69b, 0x53c, 0xe6a6, 0x537, 0xe6b2, 0x532, 0xe6bd,
-  0x52d, 0xe6c9, 0x528, 0xe6d4, 0x523, 0xe6e0, 0x51e, 0xe6ec,
-  0x51a, 0xe6f7, 0x515, 0xe703, 0x510, 0xe70e, 0x50b, 0xe71a,
-  0x506, 0xe725, 0x501, 0xe731, 0x4fc, 0xe73d, 0x4f7, 0xe748,
-  0x4f2, 0xe754, 0x4ee, 0xe75f, 0x4e9, 0xe76b, 0x4e4, 0xe777,
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-  0x2cdc, 0x3d12, 0x2ce8, 0x3d16, 0x2cf4, 0x3d1a, 0x2d00, 0x3d1d,
-  0x2d0c, 0x3d21, 0x2d18, 0x3d25, 0x2d24, 0x3d28, 0x2d30, 0x3d2c,
-  0x2d3c, 0x3d30, 0x2d48, 0x3d34, 0x2d54, 0x3d37, 0x2d60, 0x3d3b,
-  0x2d6c, 0x3d3f, 0x2d78, 0x3d42, 0x2d84, 0x3d46, 0x2d90, 0x3d49,
-  0x2d9c, 0x3d4d, 0x2da8, 0x3d51, 0x2db4, 0x3d54, 0x2dc0, 0x3d58,
-  0x2dcc, 0x3d5b, 0x2dd8, 0x3d5f, 0x2de4, 0x3d63, 0x2df0, 0x3d66,
-  0x2dfc, 0x3d6a, 0x2e09, 0x3d6d, 0x2e15, 0x3d71, 0x2e21, 0x3d74,
-  0x2e2d, 0x3d78, 0x2e39, 0x3d7b, 0x2e45, 0x3d7f, 0x2e51, 0x3d82,
-  0x2e5d, 0x3d86, 0x2e69, 0x3d89, 0x2e75, 0x3d8d, 0x2e81, 0x3d90,
-  0x2e8d, 0x3d93, 0x2e99, 0x3d97, 0x2ea6, 0x3d9a, 0x2eb2, 0x3d9e,
-  0x2ebe, 0x3da1, 0x2eca, 0x3da4, 0x2ed6, 0x3da8, 0x2ee2, 0x3dab,
-  0x2eee, 0x3daf, 0x2efa, 0x3db2, 0x2f06, 0x3db5, 0x2f13, 0x3db9,
-  0x2f1f, 0x3dbc, 0x2f2b, 0x3dbf, 0x2f37, 0x3dc2, 0x2f43, 0x3dc6,
-  0x2f4f, 0x3dc9, 0x2f5b, 0x3dcc, 0x2f67, 0x3dd0, 0x2f74, 0x3dd3,
-  0x2f80, 0x3dd6, 0x2f8c, 0x3dd9, 0x2f98, 0x3ddd, 0x2fa4, 0x3de0,
-  0x2fb0, 0x3de3, 0x2fbc, 0x3de6, 0x2fc9, 0x3de9, 0x2fd5, 0x3ded,
-  0x2fe1, 0x3df0, 0x2fed, 0x3df3, 0x2ff9, 0x3df6, 0x3005, 0x3df9,
-  0x3012, 0x3dfc, 0x301e, 0x3dff, 0x302a, 0x3e03, 0x3036, 0x3e06,
-  0x3042, 0x3e09, 0x304e, 0x3e0c, 0x305b, 0x3e0f, 0x3067, 0x3e12,
-  0x3073, 0x3e15, 0x307f, 0x3e18, 0x308b, 0x3e1b, 0x3098, 0x3e1e,
-  0x30a4, 0x3e21, 0x30b0, 0x3e24, 0x30bc, 0x3e27, 0x30c8, 0x3e2a,
-  0x30d5, 0x3e2d, 0x30e1, 0x3e30, 0x30ed, 0x3e33, 0x30f9, 0x3e36,
-  0x3105, 0x3e39, 0x3112, 0x3e3c, 0x311e, 0x3e3f, 0x312a, 0x3e42,
-  0x3136, 0x3e45, 0x3143, 0x3e48, 0x314f, 0x3e4a, 0x315b, 0x3e4d,
-  0x3167, 0x3e50, 0x3174, 0x3e53, 0x3180, 0x3e56, 0x318c, 0x3e59,
-  0x3198, 0x3e5c, 0x31a4, 0x3e5e, 0x31b1, 0x3e61, 0x31bd, 0x3e64,
-  0x31c9, 0x3e67, 0x31d5, 0x3e6a, 0x31e2, 0x3e6c, 0x31ee, 0x3e6f,
-  0x31fa, 0x3e72, 0x3207, 0x3e75, 0x3213, 0x3e77, 0x321f, 0x3e7a,
-  0x322b, 0x3e7d, 0x3238, 0x3e80, 0x3244, 0x3e82, 0x3250, 0x3e85,
-  0x325c, 0x3e88, 0x3269, 0x3e8a, 0x3275, 0x3e8d, 0x3281, 0x3e90,
-  0x328e, 0x3e92, 0x329a, 0x3e95, 0x32a6, 0x3e98, 0x32b2, 0x3e9a,
-  0x32bf, 0x3e9d, 0x32cb, 0x3e9f, 0x32d7, 0x3ea2, 0x32e4, 0x3ea5,
-  0x32f0, 0x3ea7, 0x32fc, 0x3eaa, 0x3308, 0x3eac, 0x3315, 0x3eaf,
-  0x3321, 0x3eb1, 0x332d, 0x3eb4, 0x333a, 0x3eb6, 0x3346, 0x3eb9,
-  0x3352, 0x3ebb, 0x335f, 0x3ebe, 0x336b, 0x3ec0, 0x3377, 0x3ec3,
-  0x3384, 0x3ec5, 0x3390, 0x3ec8, 0x339c, 0x3eca, 0x33a9, 0x3ecc,
-  0x33b5, 0x3ecf, 0x33c1, 0x3ed1, 0x33ce, 0x3ed4, 0x33da, 0x3ed6,
-  0x33e6, 0x3ed8, 0x33f3, 0x3edb, 0x33ff, 0x3edd, 0x340b, 0x3ee0,
-  0x3418, 0x3ee2, 0x3424, 0x3ee4, 0x3430, 0x3ee7, 0x343d, 0x3ee9,
-  0x3449, 0x3eeb, 0x3455, 0x3eed, 0x3462, 0x3ef0, 0x346e, 0x3ef2,
-  0x347b, 0x3ef4, 0x3487, 0x3ef7, 0x3493, 0x3ef9, 0x34a0, 0x3efb,
-  0x34ac, 0x3efd, 0x34b8, 0x3f00, 0x34c5, 0x3f02, 0x34d1, 0x3f04,
-  0x34dd, 0x3f06, 0x34ea, 0x3f08, 0x34f6, 0x3f0a, 0x3503, 0x3f0d,
-  0x350f, 0x3f0f, 0x351b, 0x3f11, 0x3528, 0x3f13, 0x3534, 0x3f15,
-  0x3540, 0x3f17, 0x354d, 0x3f19, 0x3559, 0x3f1c, 0x3566, 0x3f1e,
-  0x3572, 0x3f20, 0x357e, 0x3f22, 0x358b, 0x3f24, 0x3597, 0x3f26,
-  0x35a4, 0x3f28, 0x35b0, 0x3f2a, 0x35bc, 0x3f2c, 0x35c9, 0x3f2e,
-  0x35d5, 0x3f30, 0x35e2, 0x3f32, 0x35ee, 0x3f34, 0x35fa, 0x3f36,
-  0x3607, 0x3f38, 0x3613, 0x3f3a, 0x3620, 0x3f3c, 0x362c, 0x3f3e,
-  0x3639, 0x3f40, 0x3645, 0x3f42, 0x3651, 0x3f43, 0x365e, 0x3f45,
-  0x366a, 0x3f47, 0x3677, 0x3f49, 0x3683, 0x3f4b, 0x3690, 0x3f4d,
-  0x369c, 0x3f4f, 0x36a8, 0x3f51, 0x36b5, 0x3f52, 0x36c1, 0x3f54,
-  0x36ce, 0x3f56, 0x36da, 0x3f58, 0x36e7, 0x3f5a, 0x36f3, 0x3f5b,
-  0x36ff, 0x3f5d, 0x370c, 0x3f5f, 0x3718, 0x3f61, 0x3725, 0x3f62,
-  0x3731, 0x3f64, 0x373e, 0x3f66, 0x374a, 0x3f68, 0x3757, 0x3f69,
-  0x3763, 0x3f6b, 0x376f, 0x3f6d, 0x377c, 0x3f6e, 0x3788, 0x3f70,
-  0x3795, 0x3f72, 0x37a1, 0x3f73, 0x37ae, 0x3f75, 0x37ba, 0x3f77,
-  0x37c7, 0x3f78, 0x37d3, 0x3f7a, 0x37e0, 0x3f7b, 0x37ec, 0x3f7d,
-  0x37f9, 0x3f7f, 0x3805, 0x3f80, 0x3811, 0x3f82, 0x381e, 0x3f83,
-  0x382a, 0x3f85, 0x3837, 0x3f86, 0x3843, 0x3f88, 0x3850, 0x3f89,
-  0x385c, 0x3f8b, 0x3869, 0x3f8c, 0x3875, 0x3f8e, 0x3882, 0x3f8f,
-  0x388e, 0x3f91, 0x389b, 0x3f92, 0x38a7, 0x3f94, 0x38b4, 0x3f95,
-  0x38c0, 0x3f97, 0x38cd, 0x3f98, 0x38d9, 0x3f99, 0x38e6, 0x3f9b,
-  0x38f2, 0x3f9c, 0x38ff, 0x3f9e, 0x390b, 0x3f9f, 0x3918, 0x3fa0,
-  0x3924, 0x3fa2, 0x3931, 0x3fa3, 0x393d, 0x3fa4, 0x394a, 0x3fa6,
-  0x3956, 0x3fa7, 0x3963, 0x3fa8, 0x396f, 0x3faa, 0x397c, 0x3fab,
-  0x3988, 0x3fac, 0x3995, 0x3fad, 0x39a1, 0x3faf, 0x39ae, 0x3fb0,
-  0x39ba, 0x3fb1, 0x39c7, 0x3fb2, 0x39d3, 0x3fb4, 0x39e0, 0x3fb5,
-  0x39ec, 0x3fb6, 0x39f9, 0x3fb7, 0x3a05, 0x3fb8, 0x3a12, 0x3fb9,
-  0x3a1e, 0x3fbb, 0x3a2b, 0x3fbc, 0x3a37, 0x3fbd, 0x3a44, 0x3fbe,
-  0x3a50, 0x3fbf, 0x3a5d, 0x3fc0, 0x3a69, 0x3fc1, 0x3a76, 0x3fc3,
-  0x3a82, 0x3fc4, 0x3a8f, 0x3fc5, 0x3a9b, 0x3fc6, 0x3aa8, 0x3fc7,
-  0x3ab4, 0x3fc8, 0x3ac1, 0x3fc9, 0x3acd, 0x3fca, 0x3ada, 0x3fcb,
-  0x3ae6, 0x3fcc, 0x3af3, 0x3fcd, 0x3b00, 0x3fce, 0x3b0c, 0x3fcf,
-  0x3b19, 0x3fd0, 0x3b25, 0x3fd1, 0x3b32, 0x3fd2, 0x3b3e, 0x3fd3,
-  0x3b4b, 0x3fd4, 0x3b57, 0x3fd5, 0x3b64, 0x3fd5, 0x3b70, 0x3fd6,
-  0x3b7d, 0x3fd7, 0x3b89, 0x3fd8, 0x3b96, 0x3fd9, 0x3ba2, 0x3fda,
-  0x3baf, 0x3fdb, 0x3bbc, 0x3fdc, 0x3bc8, 0x3fdc, 0x3bd5, 0x3fdd,
-  0x3be1, 0x3fde, 0x3bee, 0x3fdf, 0x3bfa, 0x3fe0, 0x3c07, 0x3fe0,
-  0x3c13, 0x3fe1, 0x3c20, 0x3fe2, 0x3c2c, 0x3fe3, 0x3c39, 0x3fe3,
-  0x3c45, 0x3fe4, 0x3c52, 0x3fe5, 0x3c5f, 0x3fe6, 0x3c6b, 0x3fe6,
-  0x3c78, 0x3fe7, 0x3c84, 0x3fe8, 0x3c91, 0x3fe8, 0x3c9d, 0x3fe9,
-  0x3caa, 0x3fea, 0x3cb6, 0x3fea, 0x3cc3, 0x3feb, 0x3cd0, 0x3fec,
-  0x3cdc, 0x3fec, 0x3ce9, 0x3fed, 0x3cf5, 0x3fed, 0x3d02, 0x3fee,
-  0x3d0e, 0x3fef, 0x3d1b, 0x3fef, 0x3d27, 0x3ff0, 0x3d34, 0x3ff0,
-  0x3d40, 0x3ff1, 0x3d4d, 0x3ff1, 0x3d5a, 0x3ff2, 0x3d66, 0x3ff2,
-  0x3d73, 0x3ff3, 0x3d7f, 0x3ff3, 0x3d8c, 0x3ff4, 0x3d98, 0x3ff4,
-  0x3da5, 0x3ff5, 0x3db2, 0x3ff5, 0x3dbe, 0x3ff6, 0x3dcb, 0x3ff6,
-  0x3dd7, 0x3ff7, 0x3de4, 0x3ff7, 0x3df0, 0x3ff7, 0x3dfd, 0x3ff8,
-  0x3e09, 0x3ff8, 0x3e16, 0x3ff9, 0x3e23, 0x3ff9, 0x3e2f, 0x3ff9,
-  0x3e3c, 0x3ffa, 0x3e48, 0x3ffa, 0x3e55, 0x3ffa, 0x3e61, 0x3ffb,
-  0x3e6e, 0x3ffb, 0x3e7a, 0x3ffb, 0x3e87, 0x3ffc, 0x3e94, 0x3ffc,
-  0x3ea0, 0x3ffc, 0x3ead, 0x3ffc, 0x3eb9, 0x3ffd, 0x3ec6, 0x3ffd,
-  0x3ed2, 0x3ffd, 0x3edf, 0x3ffd, 0x3eec, 0x3ffe, 0x3ef8, 0x3ffe,
-  0x3f05, 0x3ffe, 0x3f11, 0x3ffe, 0x3f1e, 0x3ffe, 0x3f2a, 0x3fff,
-  0x3f37, 0x3fff, 0x3f44, 0x3fff, 0x3f50, 0x3fff, 0x3f5d, 0x3fff,
-  0x3f69, 0x3fff, 0x3f76, 0x3fff, 0x3f82, 0x4000, 0x3f8f, 0x4000,
-  0x3f9b, 0x4000, 0x3fa8, 0x4000, 0x3fb5, 0x4000, 0x3fc1, 0x4000,
-  0x3fce, 0x4000, 0x3fda, 0x4000, 0x3fe7, 0x4000, 0x3ff3, 0x4000,
-};
-
-/**    
-* \par   
-* Generation of real_CoefB array:    
-* \par    
-* n = 4096    
-* 
for (i = 0; i < n; i++)    
-*  {    
-*    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));    
-*    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    
-*  } 
   
-* \par    
-* Convert to fixed point Q15 format    
-*       round(pBTable[i] * pow(2, 15))    
-*    
-*/
-
-static const q15_t ALIGN4 realCoefBQ15[8192] = {
-  0x4000, 0x4000, 0x400d, 0x4000, 0x4019, 0x4000, 0x4026, 0x4000,
-  0x4032, 0x4000, 0x403f, 0x4000, 0x404b, 0x4000, 0x4058, 0x4000,
-  0x4065, 0x4000, 0x4071, 0x4000, 0x407e, 0x4000, 0x408a, 0x3fff,
-  0x4097, 0x3fff, 0x40a3, 0x3fff, 0x40b0, 0x3fff, 0x40bc, 0x3fff,
-  0x40c9, 0x3fff, 0x40d6, 0x3fff, 0x40e2, 0x3ffe, 0x40ef, 0x3ffe,
-  0x40fb, 0x3ffe, 0x4108, 0x3ffe, 0x4114, 0x3ffe, 0x4121, 0x3ffd,
-  0x412e, 0x3ffd, 0x413a, 0x3ffd, 0x4147, 0x3ffd, 0x4153, 0x3ffc,
-  0x4160, 0x3ffc, 0x416c, 0x3ffc, 0x4179, 0x3ffc, 0x4186, 0x3ffb,
-  0x4192, 0x3ffb, 0x419f, 0x3ffb, 0x41ab, 0x3ffa, 0x41b8, 0x3ffa,
-  0x41c4, 0x3ffa, 0x41d1, 0x3ff9, 0x41dd, 0x3ff9, 0x41ea, 0x3ff9,
-  0x41f7, 0x3ff8, 0x4203, 0x3ff8, 0x4210, 0x3ff7, 0x421c, 0x3ff7,
-  0x4229, 0x3ff7, 0x4235, 0x3ff6, 0x4242, 0x3ff6, 0x424e, 0x3ff5,
-  0x425b, 0x3ff5, 0x4268, 0x3ff4, 0x4274, 0x3ff4, 0x4281, 0x3ff3,
-  0x428d, 0x3ff3, 0x429a, 0x3ff2, 0x42a6, 0x3ff2, 0x42b3, 0x3ff1,
-  0x42c0, 0x3ff1, 0x42cc, 0x3ff0, 0x42d9, 0x3ff0, 0x42e5, 0x3fef,
-  0x42f2, 0x3fef, 0x42fe, 0x3fee, 0x430b, 0x3fed, 0x4317, 0x3fed,
-  0x4324, 0x3fec, 0x4330, 0x3fec, 0x433d, 0x3feb, 0x434a, 0x3fea,
-  0x4356, 0x3fea, 0x4363, 0x3fe9, 0x436f, 0x3fe8, 0x437c, 0x3fe8,
-  0x4388, 0x3fe7, 0x4395, 0x3fe6, 0x43a1, 0x3fe6, 0x43ae, 0x3fe5,
-  0x43bb, 0x3fe4, 0x43c7, 0x3fe3, 0x43d4, 0x3fe3, 0x43e0, 0x3fe2,
-  0x43ed, 0x3fe1, 0x43f9, 0x3fe0, 0x4406, 0x3fe0, 0x4412, 0x3fdf,
-  0x441f, 0x3fde, 0x442b, 0x3fdd, 0x4438, 0x3fdc, 0x4444, 0x3fdc,
-  0x4451, 0x3fdb, 0x445e, 0x3fda, 0x446a, 0x3fd9, 0x4477, 0x3fd8,
-  0x4483, 0x3fd7, 0x4490, 0x3fd6, 0x449c, 0x3fd5, 0x44a9, 0x3fd5,
-  0x44b5, 0x3fd4, 0x44c2, 0x3fd3, 0x44ce, 0x3fd2, 0x44db, 0x3fd1,
-  0x44e7, 0x3fd0, 0x44f4, 0x3fcf, 0x4500, 0x3fce, 0x450d, 0x3fcd,
-  0x451a, 0x3fcc, 0x4526, 0x3fcb, 0x4533, 0x3fca, 0x453f, 0x3fc9,
-  0x454c, 0x3fc8, 0x4558, 0x3fc7, 0x4565, 0x3fc6, 0x4571, 0x3fc5,
-  0x457e, 0x3fc4, 0x458a, 0x3fc3, 0x4597, 0x3fc1, 0x45a3, 0x3fc0,
-  0x45b0, 0x3fbf, 0x45bc, 0x3fbe, 0x45c9, 0x3fbd, 0x45d5, 0x3fbc,
-  0x45e2, 0x3fbb, 0x45ee, 0x3fb9, 0x45fb, 0x3fb8, 0x4607, 0x3fb7,
-  0x4614, 0x3fb6, 0x4620, 0x3fb5, 0x462d, 0x3fb4, 0x4639, 0x3fb2,
-  0x4646, 0x3fb1, 0x4652, 0x3fb0, 0x465f, 0x3faf, 0x466b, 0x3fad,
-  0x4678, 0x3fac, 0x4684, 0x3fab, 0x4691, 0x3faa, 0x469d, 0x3fa8,
-  0x46aa, 0x3fa7, 0x46b6, 0x3fa6, 0x46c3, 0x3fa4, 0x46cf, 0x3fa3,
-  0x46dc, 0x3fa2, 0x46e8, 0x3fa0, 0x46f5, 0x3f9f, 0x4701, 0x3f9e,
-  0x470e, 0x3f9c, 0x471a, 0x3f9b, 0x4727, 0x3f99, 0x4733, 0x3f98,
-  0x4740, 0x3f97, 0x474c, 0x3f95, 0x4759, 0x3f94, 0x4765, 0x3f92,
-  0x4772, 0x3f91, 0x477e, 0x3f8f, 0x478b, 0x3f8e, 0x4797, 0x3f8c,
-  0x47a4, 0x3f8b, 0x47b0, 0x3f89, 0x47bd, 0x3f88, 0x47c9, 0x3f86,
-  0x47d6, 0x3f85, 0x47e2, 0x3f83, 0x47ef, 0x3f82, 0x47fb, 0x3f80,
-  0x4807, 0x3f7f, 0x4814, 0x3f7d, 0x4820, 0x3f7b, 0x482d, 0x3f7a,
-  0x4839, 0x3f78, 0x4846, 0x3f77, 0x4852, 0x3f75, 0x485f, 0x3f73,
-  0x486b, 0x3f72, 0x4878, 0x3f70, 0x4884, 0x3f6e, 0x4891, 0x3f6d,
-  0x489d, 0x3f6b, 0x48a9, 0x3f69, 0x48b6, 0x3f68, 0x48c2, 0x3f66,
-  0x48cf, 0x3f64, 0x48db, 0x3f62, 0x48e8, 0x3f61, 0x48f4, 0x3f5f,
-  0x4901, 0x3f5d, 0x490d, 0x3f5b, 0x4919, 0x3f5a, 0x4926, 0x3f58,
-  0x4932, 0x3f56, 0x493f, 0x3f54, 0x494b, 0x3f52, 0x4958, 0x3f51,
-  0x4964, 0x3f4f, 0x4970, 0x3f4d, 0x497d, 0x3f4b, 0x4989, 0x3f49,
-  0x4996, 0x3f47, 0x49a2, 0x3f45, 0x49af, 0x3f43, 0x49bb, 0x3f42,
-  0x49c7, 0x3f40, 0x49d4, 0x3f3e, 0x49e0, 0x3f3c, 0x49ed, 0x3f3a,
-  0x49f9, 0x3f38, 0x4a06, 0x3f36, 0x4a12, 0x3f34, 0x4a1e, 0x3f32,
-  0x4a2b, 0x3f30, 0x4a37, 0x3f2e, 0x4a44, 0x3f2c, 0x4a50, 0x3f2a,
-  0x4a5c, 0x3f28, 0x4a69, 0x3f26, 0x4a75, 0x3f24, 0x4a82, 0x3f22,
-  0x4a8e, 0x3f20, 0x4a9a, 0x3f1e, 0x4aa7, 0x3f1c, 0x4ab3, 0x3f19,
-  0x4ac0, 0x3f17, 0x4acc, 0x3f15, 0x4ad8, 0x3f13, 0x4ae5, 0x3f11,
-  0x4af1, 0x3f0f, 0x4afd, 0x3f0d, 0x4b0a, 0x3f0a, 0x4b16, 0x3f08,
-  0x4b23, 0x3f06, 0x4b2f, 0x3f04, 0x4b3b, 0x3f02, 0x4b48, 0x3f00,
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-  0x72d0, 0xd917, 0x72c9, 0xd90d, 0x72c1, 0xd903, 0x72ba, 0xd8f9,
-  0x72b2, 0xd8ef, 0x72aa, 0xd8e6, 0x72a3, 0xd8dc, 0x729b, 0xd8d2,
-  0x7293, 0xd8c8, 0x728b, 0xd8be, 0x7284, 0xd8b4, 0x727c, 0xd8aa,
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-  0x7236, 0xd851, 0x722e, 0xd847, 0x7227, 0xd83d, 0x721f, 0xd833,
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-  0x71f8, 0xd802, 0x71f0, 0xd7f8, 0x71e8, 0xd7ef, 0x71e0, 0xd7e5,
-  0x71d8, 0xd7db, 0x71d0, 0xd7d1, 0x71c8, 0xd7c8, 0x71c0, 0xd7be,
-  0x71b9, 0xd7b4, 0x71b1, 0xd7aa, 0x71a9, 0xd7a0, 0x71a1, 0xd797,
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-  0x7159, 0xd73f, 0x7151, 0xd736, 0x7149, 0xd72c, 0x7141, 0xd722,
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-  0x7119, 0xd6f2, 0x7111, 0xd6e8, 0x7109, 0xd6df, 0x7101, 0xd6d5,
-  0x70f9, 0xd6cb, 0x70f0, 0xd6c2, 0x70e8, 0xd6b8, 0x70e0, 0xd6af,
-  0x70d8, 0xd6a5, 0x70d0, 0xd69b, 0x70c8, 0xd692, 0x70c0, 0xd688,
-  0x70b8, 0xd67f, 0x70af, 0xd675, 0x70a7, 0xd66c, 0x709f, 0xd662,
-  0x7097, 0xd659, 0x708f, 0xd64f, 0x7087, 0xd645, 0x707e, 0xd63c,
-  0x7076, 0xd632, 0x706e, 0xd629, 0x7066, 0xd61f, 0x705d, 0xd616,
-  0x7055, 0xd60c, 0x704d, 0xd603, 0x7045, 0xd5f9, 0x703c, 0xd5f0,
-  0x7034, 0xd5e6, 0x702c, 0xd5dd, 0x7024, 0xd5d4, 0x701b, 0xd5ca,
-  0x7013, 0xd5c1, 0x700b, 0xd5b7, 0x7002, 0xd5ae, 0x6ffa, 0xd5a4,
-  0x6ff2, 0xd59b, 0x6fea, 0xd592, 0x6fe1, 0xd588, 0x6fd9, 0xd57f,
-  0x6fd0, 0xd575, 0x6fc8, 0xd56c, 0x6fc0, 0xd563, 0x6fb7, 0xd559,
-  0x6faf, 0xd550, 0x6fa7, 0xd547, 0x6f9e, 0xd53d, 0x6f96, 0xd534,
-  0x6f8d, 0xd52a, 0x6f85, 0xd521, 0x6f7d, 0xd518, 0x6f74, 0xd50e,
-  0x6f6c, 0xd505, 0x6f63, 0xd4fc, 0x6f5b, 0xd4f3, 0x6f52, 0xd4e9,
-  0x6f4a, 0xd4e0, 0x6f41, 0xd4d7, 0x6f39, 0xd4cd, 0x6f30, 0xd4c4,
-  0x6f28, 0xd4bb, 0x6f20, 0xd4b2, 0x6f17, 0xd4a8, 0x6f0e, 0xd49f,
-  0x6f06, 0xd496, 0x6efd, 0xd48d, 0x6ef5, 0xd483, 0x6eec, 0xd47a,
-  0x6ee4, 0xd471, 0x6edb, 0xd468, 0x6ed3, 0xd45f, 0x6eca, 0xd455,
-  0x6ec2, 0xd44c, 0x6eb9, 0xd443, 0x6eb0, 0xd43a, 0x6ea8, 0xd431,
-  0x6e9f, 0xd428, 0x6e97, 0xd41e, 0x6e8e, 0xd415, 0x6e85, 0xd40c,
-  0x6e7d, 0xd403, 0x6e74, 0xd3fa, 0x6e6b, 0xd3f1, 0x6e63, 0xd3e8,
-  0x6e5a, 0xd3df, 0x6e51, 0xd3d5, 0x6e49, 0xd3cc, 0x6e40, 0xd3c3,
-  0x6e37, 0xd3ba, 0x6e2f, 0xd3b1, 0x6e26, 0xd3a8, 0x6e1d, 0xd39f,
-  0x6e15, 0xd396, 0x6e0c, 0xd38d, 0x6e03, 0xd384, 0x6dfa, 0xd37b,
-  0x6df2, 0xd372, 0x6de9, 0xd369, 0x6de0, 0xd360, 0x6dd7, 0xd357,
-  0x6dcf, 0xd34e, 0x6dc6, 0xd345, 0x6dbd, 0xd33c, 0x6db4, 0xd333,
-  0x6dab, 0xd32a, 0x6da3, 0xd321, 0x6d9a, 0xd318, 0x6d91, 0xd30f,
-  0x6d88, 0xd306, 0x6d7f, 0xd2fd, 0x6d76, 0xd2f4, 0x6d6e, 0xd2eb,
-  0x6d65, 0xd2e2, 0x6d5c, 0xd2d9, 0x6d53, 0xd2d1, 0x6d4a, 0xd2c8,
-  0x6d41, 0xd2bf, 0x6d38, 0xd2b6, 0x6d2f, 0xd2ad, 0x6d27, 0xd2a4,
-  0x6d1e, 0xd29b, 0x6d15, 0xd292, 0x6d0c, 0xd28a, 0x6d03, 0xd281,
-  0x6cfa, 0xd278, 0x6cf1, 0xd26f, 0x6ce8, 0xd266, 0x6cdf, 0xd25d,
-  0x6cd6, 0xd255, 0x6ccd, 0xd24c, 0x6cc4, 0xd243, 0x6cbb, 0xd23a,
-  0x6cb2, 0xd231, 0x6ca9, 0xd229, 0x6ca0, 0xd220, 0x6c97, 0xd217,
-  0x6c8e, 0xd20e, 0x6c85, 0xd206, 0x6c7c, 0xd1fd, 0x6c73, 0xd1f4,
-  0x6c6a, 0xd1eb, 0x6c61, 0xd1e3, 0x6c58, 0xd1da, 0x6c4f, 0xd1d1,
-  0x6c46, 0xd1c9, 0x6c3d, 0xd1c0, 0x6c34, 0xd1b7, 0x6c2b, 0xd1af,
-  0x6c21, 0xd1a6, 0x6c18, 0xd19d, 0x6c0f, 0xd195, 0x6c06, 0xd18c,
-  0x6bfd, 0xd183, 0x6bf4, 0xd17b, 0x6beb, 0xd172, 0x6be2, 0xd169,
-  0x6bd8, 0xd161, 0x6bcf, 0xd158, 0x6bc6, 0xd150, 0x6bbd, 0xd147,
-  0x6bb4, 0xd13e, 0x6bab, 0xd136, 0x6ba1, 0xd12d, 0x6b98, 0xd125,
-  0x6b8f, 0xd11c, 0x6b86, 0xd114, 0x6b7d, 0xd10b, 0x6b73, 0xd103,
-  0x6b6a, 0xd0fa, 0x6b61, 0xd0f2, 0x6b58, 0xd0e9, 0x6b4e, 0xd0e0,
-  0x6b45, 0xd0d8, 0x6b3c, 0xd0d0, 0x6b33, 0xd0c7, 0x6b29, 0xd0bf,
-  0x6b20, 0xd0b6, 0x6b17, 0xd0ae, 0x6b0d, 0xd0a5, 0x6b04, 0xd09d,
-  0x6afb, 0xd094, 0x6af2, 0xd08c, 0x6ae8, 0xd083, 0x6adf, 0xd07b,
-  0x6ad6, 0xd073, 0x6acc, 0xd06a, 0x6ac3, 0xd062, 0x6ab9, 0xd059,
-  0x6ab0, 0xd051, 0x6aa7, 0xd049, 0x6a9d, 0xd040, 0x6a94, 0xd038,
-  0x6a8b, 0xd030, 0x6a81, 0xd027, 0x6a78, 0xd01f, 0x6a6e, 0xd016,
-  0x6a65, 0xd00e, 0x6a5c, 0xd006, 0x6a52, 0xcffe, 0x6a49, 0xcff5,
-  0x6a3f, 0xcfed, 0x6a36, 0xcfe5, 0x6a2c, 0xcfdc, 0x6a23, 0xcfd4,
-  0x6a1a, 0xcfcc, 0x6a10, 0xcfc4, 0x6a07, 0xcfbb, 0x69fd, 0xcfb3,
-  0x69f4, 0xcfab, 0x69ea, 0xcfa3, 0x69e1, 0xcf9a, 0x69d7, 0xcf92,
-  0x69ce, 0xcf8a, 0x69c4, 0xcf82, 0x69bb, 0xcf79, 0x69b1, 0xcf71,
-  0x69a7, 0xcf69, 0x699e, 0xcf61, 0x6994, 0xcf59, 0x698b, 0xcf51,
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-  0x6935, 0xcf07, 0x692b, 0xceff, 0x6921, 0xcef7, 0x6918, 0xceef,
-  0x690e, 0xcee7, 0x6904, 0xcedf, 0x68fb, 0xced7, 0x68f1, 0xcecf,
-  0x68e7, 0xcec7, 0x68de, 0xcebf, 0x68d4, 0xceb7, 0x68ca, 0xceaf,
-  0x68c1, 0xcea7, 0x68b7, 0xce9f, 0x68ad, 0xce97, 0x68a4, 0xce8f,
-  0x689a, 0xce87, 0x6890, 0xce7f, 0x6886, 0xce77, 0x687d, 0xce6f,
-  0x6873, 0xce67, 0x6869, 0xce5f, 0x6860, 0xce57, 0x6856, 0xce4f,
-  0x684c, 0xce47, 0x6842, 0xce40, 0x6838, 0xce38, 0x682f, 0xce30,
-  0x6825, 0xce28, 0x681b, 0xce20, 0x6811, 0xce18, 0x6808, 0xce10,
-  0x67fe, 0xce08, 0x67f4, 0xce01, 0x67ea, 0xcdf9, 0x67e0, 0xcdf1,
-  0x67d6, 0xcde9, 0x67cd, 0xcde1, 0x67c3, 0xcdd9, 0x67b9, 0xcdd2,
-  0x67af, 0xcdca, 0x67a5, 0xcdc2, 0x679b, 0xcdba, 0x6791, 0xcdb2,
-  0x6788, 0xcdab, 0x677e, 0xcda3, 0x6774, 0xcd9b, 0x676a, 0xcd93,
-  0x6760, 0xcd8c, 0x6756, 0xcd84, 0x674c, 0xcd7c, 0x6742, 0xcd75,
-  0x6738, 0xcd6d, 0x672e, 0xcd65, 0x6724, 0xcd5d, 0x671a, 0xcd56,
-  0x6711, 0xcd4e, 0x6707, 0xcd46, 0x66fd, 0xcd3f, 0x66f3, 0xcd37,
-  0x66e9, 0xcd30, 0x66df, 0xcd28, 0x66d5, 0xcd20, 0x66cb, 0xcd19,
-  0x66c1, 0xcd11, 0x66b7, 0xcd09, 0x66ad, 0xcd02, 0x66a3, 0xccfa,
-  0x6699, 0xccf3, 0x668f, 0xcceb, 0x6685, 0xcce3, 0x667b, 0xccdc,
-  0x6671, 0xccd4, 0x6666, 0xcccd, 0x665c, 0xccc5, 0x6652, 0xccbe,
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-  0x6620, 0xcc98, 0x6616, 0xcc91, 0x660c, 0xcc89, 0x6602, 0xcc82,
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-  0x65cf, 0xcc5d, 0x65c5, 0xcc55, 0x65bb, 0xcc4e, 0x65b1, 0xcc46,
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-  0x6555, 0xcc04, 0x654b, 0xcbfd, 0x6541, 0xcbf5, 0x6536, 0xcbee,
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-  0x638e, 0xcac9, 0x6384, 0xcac2, 0x637a, 0xcabb, 0x636f, 0xcab4,
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-  0x6311, 0xca76, 0x6306, 0xca6f, 0x62fc, 0xca68, 0x62f1, 0xca61,
-  0x62e7, 0xca5b, 0x62dc, 0xca54, 0x62d2, 0xca4d, 0x62c7, 0xca46,
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-  0x623d, 0xc9ee, 0x6233, 0xc9e7, 0x6228, 0xc9e0, 0x621e, 0xc9da,
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-  0x61e8, 0xc9b8, 0x61de, 0xc9b2, 0x61d3, 0xc9ab, 0x61c8, 0xc9a4,
-  0x61be, 0xc99e, 0x61b3, 0xc997, 0x61a8, 0xc991, 0x619e, 0xc98a,
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-  0x60e7, 0xc91b, 0x60dc, 0xc915, 0x60d1, 0xc90e, 0x60c7, 0xc908,
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-  0x6091, 0xc8e8, 0x6086, 0xc8e1, 0x607b, 0xc8db, 0x6070, 0xc8d4,
-  0x6065, 0xc8ce, 0x605b, 0xc8c8, 0x6050, 0xc8c1, 0x6045, 0xc8bb,
-  0x603a, 0xc8b5, 0x602f, 0xc8ae, 0x6024, 0xc8a8, 0x6019, 0xc8a2,
-  0x600f, 0xc89b, 0x6004, 0xc895, 0x5ff9, 0xc88f, 0x5fee, 0xc889,
-  0x5fe3, 0xc882, 0x5fd8, 0xc87c, 0x5fcd, 0xc876, 0x5fc2, 0xc870,
-  0x5fb7, 0xc869, 0x5fac, 0xc863, 0x5fa2, 0xc85d, 0x5f97, 0xc857,
-  0x5f8c, 0xc850, 0x5f81, 0xc84a, 0x5f76, 0xc844, 0x5f6b, 0xc83e,
-  0x5f60, 0xc838, 0x5f55, 0xc832, 0x5f4a, 0xc82b, 0x5f3f, 0xc825,
-  0x5f34, 0xc81f, 0x5f29, 0xc819, 0x5f1e, 0xc813, 0x5f13, 0xc80d,
-  0x5f08, 0xc807, 0x5efd, 0xc801, 0x5ef2, 0xc7fb, 0x5ee7, 0xc7f5,
-  0x5edc, 0xc7ee, 0x5ed1, 0xc7e8, 0x5ec6, 0xc7e2, 0x5ebb, 0xc7dc,
-  0x5eb0, 0xc7d6, 0x5ea5, 0xc7d0, 0x5e9a, 0xc7ca, 0x5e8f, 0xc7c4,
-  0x5e84, 0xc7be, 0x5e79, 0xc7b8, 0x5e6e, 0xc7b2, 0x5e63, 0xc7ac,
-  0x5e58, 0xc7a6, 0x5e4d, 0xc7a0, 0x5e42, 0xc79a, 0x5e36, 0xc795,
-  0x5e2b, 0xc78f, 0x5e20, 0xc789, 0x5e15, 0xc783, 0x5e0a, 0xc77d,
-  0x5dff, 0xc777, 0x5df4, 0xc771, 0x5de9, 0xc76b, 0x5dde, 0xc765,
-  0x5dd3, 0xc75f, 0x5dc7, 0xc75a, 0x5dbc, 0xc754, 0x5db1, 0xc74e,
-  0x5da6, 0xc748, 0x5d9b, 0xc742, 0x5d90, 0xc73d, 0x5d85, 0xc737,
-  0x5d79, 0xc731, 0x5d6e, 0xc72b, 0x5d63, 0xc725, 0x5d58, 0xc720,
-  0x5d4d, 0xc71a, 0x5d42, 0xc714, 0x5d36, 0xc70e, 0x5d2b, 0xc709,
-  0x5d20, 0xc703, 0x5d15, 0xc6fd, 0x5d0a, 0xc6f7, 0x5cff, 0xc6f2,
-  0x5cf3, 0xc6ec, 0x5ce8, 0xc6e6, 0x5cdd, 0xc6e1, 0x5cd2, 0xc6db,
-  0x5cc6, 0xc6d5, 0x5cbb, 0xc6d0, 0x5cb0, 0xc6ca, 0x5ca5, 0xc6c5,
-  0x5c99, 0xc6bf, 0x5c8e, 0xc6b9, 0x5c83, 0xc6b4, 0x5c78, 0xc6ae,
-  0x5c6c, 0xc6a8, 0x5c61, 0xc6a3, 0x5c56, 0xc69d, 0x5c4b, 0xc698,
-  0x5c3f, 0xc692, 0x5c34, 0xc68d, 0x5c29, 0xc687, 0x5c1e, 0xc682,
-  0x5c12, 0xc67c, 0x5c07, 0xc677, 0x5bfc, 0xc671, 0x5bf0, 0xc66c,
-  0x5be5, 0xc666, 0x5bda, 0xc661, 0x5bce, 0xc65b, 0x5bc3, 0xc656,
-  0x5bb8, 0xc650, 0x5bac, 0xc64b, 0x5ba1, 0xc645, 0x5b96, 0xc640,
-  0x5b8a, 0xc63b, 0x5b7f, 0xc635, 0x5b74, 0xc630, 0x5b68, 0xc62a,
-  0x5b5d, 0xc625, 0x5b52, 0xc620, 0x5b46, 0xc61a, 0x5b3b, 0xc615,
-  0x5b30, 0xc610, 0x5b24, 0xc60a, 0x5b19, 0xc605, 0x5b0d, 0xc600,
-  0x5b02, 0xc5fa, 0x5af7, 0xc5f5, 0x5aeb, 0xc5f0, 0x5ae0, 0xc5ea,
-  0x5ad4, 0xc5e5, 0x5ac9, 0xc5e0, 0x5abe, 0xc5db, 0x5ab2, 0xc5d5,
-  0x5aa7, 0xc5d0, 0x5a9b, 0xc5cb, 0x5a90, 0xc5c6, 0x5a84, 0xc5c1,
-  0x5a79, 0xc5bb, 0x5a6e, 0xc5b6, 0x5a62, 0xc5b1, 0x5a57, 0xc5ac,
-  0x5a4b, 0xc5a7, 0x5a40, 0xc5a1, 0x5a34, 0xc59c, 0x5a29, 0xc597,
-  0x5a1d, 0xc592, 0x5a12, 0xc58d, 0x5a06, 0xc588, 0x59fb, 0xc583,
-  0x59ef, 0xc57e, 0x59e4, 0xc578, 0x59d8, 0xc573, 0x59cd, 0xc56e,
-  0x59c1, 0xc569, 0x59b6, 0xc564, 0x59aa, 0xc55f, 0x599f, 0xc55a,
-  0x5993, 0xc555, 0x5988, 0xc550, 0x597c, 0xc54b, 0x5971, 0xc546,
-  0x5965, 0xc541, 0x595a, 0xc53c, 0x594e, 0xc537, 0x5943, 0xc532,
-  0x5937, 0xc52d, 0x592c, 0xc528, 0x5920, 0xc523, 0x5914, 0xc51e,
-  0x5909, 0xc51a, 0x58fd, 0xc515, 0x58f2, 0xc510, 0x58e6, 0xc50b,
-  0x58db, 0xc506, 0x58cf, 0xc501, 0x58c3, 0xc4fc, 0x58b8, 0xc4f7,
-  0x58ac, 0xc4f2, 0x58a1, 0xc4ee, 0x5895, 0xc4e9, 0x5889, 0xc4e4,
-  0x587e, 0xc4df, 0x5872, 0xc4da, 0x5867, 0xc4d6, 0x585b, 0xc4d1,
-  0x584f, 0xc4cc, 0x5844, 0xc4c7, 0x5838, 0xc4c2, 0x582d, 0xc4be,
-  0x5821, 0xc4b9, 0x5815, 0xc4b4, 0x580a, 0xc4b0, 0x57fe, 0xc4ab,
-  0x57f2, 0xc4a6, 0x57e7, 0xc4a1, 0x57db, 0xc49d, 0x57cf, 0xc498,
-  0x57c4, 0xc493, 0x57b8, 0xc48f, 0x57ac, 0xc48a, 0x57a1, 0xc485,
-  0x5795, 0xc481, 0x5789, 0xc47c, 0x577e, 0xc478, 0x5772, 0xc473,
-  0x5766, 0xc46e, 0x575b, 0xc46a, 0x574f, 0xc465, 0x5743, 0xc461,
-  0x5737, 0xc45c, 0x572c, 0xc457, 0x5720, 0xc453, 0x5714, 0xc44e,
-  0x5709, 0xc44a, 0x56fd, 0xc445, 0x56f1, 0xc441, 0x56e5, 0xc43c,
-  0x56da, 0xc438, 0x56ce, 0xc433, 0x56c2, 0xc42f, 0x56b6, 0xc42a,
-  0x56ab, 0xc426, 0x569f, 0xc422, 0x5693, 0xc41d, 0x5687, 0xc419,
-  0x567c, 0xc414, 0x5670, 0xc410, 0x5664, 0xc40b, 0x5658, 0xc407,
-  0x564c, 0xc403, 0x5641, 0xc3fe, 0x5635, 0xc3fa, 0x5629, 0xc3f6,
-  0x561d, 0xc3f1, 0x5612, 0xc3ed, 0x5606, 0xc3e9, 0x55fa, 0xc3e4,
-  0x55ee, 0xc3e0, 0x55e2, 0xc3dc, 0x55d7, 0xc3d7, 0x55cb, 0xc3d3,
-  0x55bf, 0xc3cf, 0x55b3, 0xc3ca, 0x55a7, 0xc3c6, 0x559b, 0xc3c2,
-  0x5590, 0xc3be, 0x5584, 0xc3ba, 0x5578, 0xc3b5, 0x556c, 0xc3b1,
-  0x5560, 0xc3ad, 0x5554, 0xc3a9, 0x5549, 0xc3a5, 0x553d, 0xc3a0,
-  0x5531, 0xc39c, 0x5525, 0xc398, 0x5519, 0xc394, 0x550d, 0xc390,
-  0x5501, 0xc38c, 0x54f6, 0xc387, 0x54ea, 0xc383, 0x54de, 0xc37f,
-  0x54d2, 0xc37b, 0x54c6, 0xc377, 0x54ba, 0xc373, 0x54ae, 0xc36f,
-  0x54a2, 0xc36b, 0x5496, 0xc367, 0x548b, 0xc363, 0x547f, 0xc35f,
-  0x5473, 0xc35b, 0x5467, 0xc357, 0x545b, 0xc353, 0x544f, 0xc34f,
-  0x5443, 0xc34b, 0x5437, 0xc347, 0x542b, 0xc343, 0x541f, 0xc33f,
-  0x5413, 0xc33b, 0x5407, 0xc337, 0x53fb, 0xc333, 0x53f0, 0xc32f,
-  0x53e4, 0xc32b, 0x53d8, 0xc327, 0x53cc, 0xc323, 0x53c0, 0xc320,
-  0x53b4, 0xc31c, 0x53a8, 0xc318, 0x539c, 0xc314, 0x5390, 0xc310,
-  0x5384, 0xc30c, 0x5378, 0xc308, 0x536c, 0xc305, 0x5360, 0xc301,
-  0x5354, 0xc2fd, 0x5348, 0xc2f9, 0x533c, 0xc2f5, 0x5330, 0xc2f2,
-  0x5324, 0xc2ee, 0x5318, 0xc2ea, 0x530c, 0xc2e6, 0x5300, 0xc2e3,
-  0x52f4, 0xc2df, 0x52e8, 0xc2db, 0x52dc, 0xc2d8, 0x52d0, 0xc2d4,
-  0x52c4, 0xc2d0, 0x52b8, 0xc2cc, 0x52ac, 0xc2c9, 0x52a0, 0xc2c5,
-  0x5294, 0xc2c1, 0x5288, 0xc2be, 0x527c, 0xc2ba, 0x5270, 0xc2b7,
-  0x5264, 0xc2b3, 0x5258, 0xc2af, 0x524c, 0xc2ac, 0x5240, 0xc2a8,
-  0x5234, 0xc2a5, 0x5228, 0xc2a1, 0x521c, 0xc29d, 0x5210, 0xc29a,
-  0x5204, 0xc296, 0x51f7, 0xc293, 0x51eb, 0xc28f, 0x51df, 0xc28c,
-  0x51d3, 0xc288, 0x51c7, 0xc285, 0x51bb, 0xc281, 0x51af, 0xc27e,
-  0x51a3, 0xc27a, 0x5197, 0xc277, 0x518b, 0xc273, 0x517f, 0xc270,
-  0x5173, 0xc26d, 0x5167, 0xc269, 0x515a, 0xc266, 0x514e, 0xc262,
-  0x5142, 0xc25f, 0x5136, 0xc25c, 0x512a, 0xc258, 0x511e, 0xc255,
-  0x5112, 0xc251, 0x5106, 0xc24e, 0x50fa, 0xc24b, 0x50ed, 0xc247,
-  0x50e1, 0xc244, 0x50d5, 0xc241, 0x50c9, 0xc23e, 0x50bd, 0xc23a,
-  0x50b1, 0xc237, 0x50a5, 0xc234, 0x5099, 0xc230, 0x508c, 0xc22d,
-  0x5080, 0xc22a, 0x5074, 0xc227, 0x5068, 0xc223, 0x505c, 0xc220,
-  0x5050, 0xc21d, 0x5044, 0xc21a, 0x5037, 0xc217, 0x502b, 0xc213,
-  0x501f, 0xc210, 0x5013, 0xc20d, 0x5007, 0xc20a, 0x4ffb, 0xc207,
-  0x4fee, 0xc204, 0x4fe2, 0xc201, 0x4fd6, 0xc1fd, 0x4fca, 0xc1fa,
-  0x4fbe, 0xc1f7, 0x4fb2, 0xc1f4, 0x4fa5, 0xc1f1, 0x4f99, 0xc1ee,
-  0x4f8d, 0xc1eb, 0x4f81, 0xc1e8, 0x4f75, 0xc1e5, 0x4f68, 0xc1e2,
-  0x4f5c, 0xc1df, 0x4f50, 0xc1dc, 0x4f44, 0xc1d9, 0x4f38, 0xc1d6,
-  0x4f2b, 0xc1d3, 0x4f1f, 0xc1d0, 0x4f13, 0xc1cd, 0x4f07, 0xc1ca,
-  0x4efb, 0xc1c7, 0x4eee, 0xc1c4, 0x4ee2, 0xc1c1, 0x4ed6, 0xc1be,
-  0x4eca, 0xc1bb, 0x4ebd, 0xc1b8, 0x4eb1, 0xc1b6, 0x4ea5, 0xc1b3,
-  0x4e99, 0xc1b0, 0x4e8c, 0xc1ad, 0x4e80, 0xc1aa, 0x4e74, 0xc1a7,
-  0x4e68, 0xc1a4, 0x4e5c, 0xc1a2, 0x4e4f, 0xc19f, 0x4e43, 0xc19c,
-  0x4e37, 0xc199, 0x4e2b, 0xc196, 0x4e1e, 0xc194, 0x4e12, 0xc191,
-  0x4e06, 0xc18e, 0x4df9, 0xc18b, 0x4ded, 0xc189, 0x4de1, 0xc186,
-  0x4dd5, 0xc183, 0x4dc8, 0xc180, 0x4dbc, 0xc17e, 0x4db0, 0xc17b,
-  0x4da4, 0xc178, 0x4d97, 0xc176, 0x4d8b, 0xc173, 0x4d7f, 0xc170,
-  0x4d72, 0xc16e, 0x4d66, 0xc16b, 0x4d5a, 0xc168, 0x4d4e, 0xc166,
-  0x4d41, 0xc163, 0x4d35, 0xc161, 0x4d29, 0xc15e, 0x4d1c, 0xc15b,
-  0x4d10, 0xc159, 0x4d04, 0xc156, 0x4cf8, 0xc154, 0x4ceb, 0xc151,
-  0x4cdf, 0xc14f, 0x4cd3, 0xc14c, 0x4cc6, 0xc14a, 0x4cba, 0xc147,
-  0x4cae, 0xc145, 0x4ca1, 0xc142, 0x4c95, 0xc140, 0x4c89, 0xc13d,
-  0x4c7c, 0xc13b, 0x4c70, 0xc138, 0x4c64, 0xc136, 0x4c57, 0xc134,
-  0x4c4b, 0xc131, 0x4c3f, 0xc12f, 0x4c32, 0xc12c, 0x4c26, 0xc12a,
-  0x4c1a, 0xc128, 0x4c0d, 0xc125, 0x4c01, 0xc123, 0x4bf5, 0xc120,
-  0x4be8, 0xc11e, 0x4bdc, 0xc11c, 0x4bd0, 0xc119, 0x4bc3, 0xc117,
-  0x4bb7, 0xc115, 0x4bab, 0xc113, 0x4b9e, 0xc110, 0x4b92, 0xc10e,
-  0x4b85, 0xc10c, 0x4b79, 0xc109, 0x4b6d, 0xc107, 0x4b60, 0xc105,
-  0x4b54, 0xc103, 0x4b48, 0xc100, 0x4b3b, 0xc0fe, 0x4b2f, 0xc0fc,
-  0x4b23, 0xc0fa, 0x4b16, 0xc0f8, 0x4b0a, 0xc0f6, 0x4afd, 0xc0f3,
-  0x4af1, 0xc0f1, 0x4ae5, 0xc0ef, 0x4ad8, 0xc0ed, 0x4acc, 0xc0eb,
-  0x4ac0, 0xc0e9, 0x4ab3, 0xc0e7, 0x4aa7, 0xc0e4, 0x4a9a, 0xc0e2,
-  0x4a8e, 0xc0e0, 0x4a82, 0xc0de, 0x4a75, 0xc0dc, 0x4a69, 0xc0da,
-  0x4a5c, 0xc0d8, 0x4a50, 0xc0d6, 0x4a44, 0xc0d4, 0x4a37, 0xc0d2,
-  0x4a2b, 0xc0d0, 0x4a1e, 0xc0ce, 0x4a12, 0xc0cc, 0x4a06, 0xc0ca,
-  0x49f9, 0xc0c8, 0x49ed, 0xc0c6, 0x49e0, 0xc0c4, 0x49d4, 0xc0c2,
-  0x49c7, 0xc0c0, 0x49bb, 0xc0be, 0x49af, 0xc0bd, 0x49a2, 0xc0bb,
-  0x4996, 0xc0b9, 0x4989, 0xc0b7, 0x497d, 0xc0b5, 0x4970, 0xc0b3,
-  0x4964, 0xc0b1, 0x4958, 0xc0af, 0x494b, 0xc0ae, 0x493f, 0xc0ac,
-  0x4932, 0xc0aa, 0x4926, 0xc0a8, 0x4919, 0xc0a6, 0x490d, 0xc0a5,
-  0x4901, 0xc0a3, 0x48f4, 0xc0a1, 0x48e8, 0xc09f, 0x48db, 0xc09e,
-  0x48cf, 0xc09c, 0x48c2, 0xc09a, 0x48b6, 0xc098, 0x48a9, 0xc097,
-  0x489d, 0xc095, 0x4891, 0xc093, 0x4884, 0xc092, 0x4878, 0xc090,
-  0x486b, 0xc08e, 0x485f, 0xc08d, 0x4852, 0xc08b, 0x4846, 0xc089,
-  0x4839, 0xc088, 0x482d, 0xc086, 0x4820, 0xc085, 0x4814, 0xc083,
-  0x4807, 0xc081, 0x47fb, 0xc080, 0x47ef, 0xc07e, 0x47e2, 0xc07d,
-  0x47d6, 0xc07b, 0x47c9, 0xc07a, 0x47bd, 0xc078, 0x47b0, 0xc077,
-  0x47a4, 0xc075, 0x4797, 0xc074, 0x478b, 0xc072, 0x477e, 0xc071,
-  0x4772, 0xc06f, 0x4765, 0xc06e, 0x4759, 0xc06c, 0x474c, 0xc06b,
-  0x4740, 0xc069, 0x4733, 0xc068, 0x4727, 0xc067, 0x471a, 0xc065,
-  0x470e, 0xc064, 0x4701, 0xc062, 0x46f5, 0xc061, 0x46e8, 0xc060,
-  0x46dc, 0xc05e, 0x46cf, 0xc05d, 0x46c3, 0xc05c, 0x46b6, 0xc05a,
-  0x46aa, 0xc059, 0x469d, 0xc058, 0x4691, 0xc056, 0x4684, 0xc055,
-  0x4678, 0xc054, 0x466b, 0xc053, 0x465f, 0xc051, 0x4652, 0xc050,
-  0x4646, 0xc04f, 0x4639, 0xc04e, 0x462d, 0xc04c, 0x4620, 0xc04b,
-  0x4614, 0xc04a, 0x4607, 0xc049, 0x45fb, 0xc048, 0x45ee, 0xc047,
-  0x45e2, 0xc045, 0x45d5, 0xc044, 0x45c9, 0xc043, 0x45bc, 0xc042,
-  0x45b0, 0xc041, 0x45a3, 0xc040, 0x4597, 0xc03f, 0x458a, 0xc03d,
-  0x457e, 0xc03c, 0x4571, 0xc03b, 0x4565, 0xc03a, 0x4558, 0xc039,
-  0x454c, 0xc038, 0x453f, 0xc037, 0x4533, 0xc036, 0x4526, 0xc035,
-  0x451a, 0xc034, 0x450d, 0xc033, 0x4500, 0xc032, 0x44f4, 0xc031,
-  0x44e7, 0xc030, 0x44db, 0xc02f, 0x44ce, 0xc02e, 0x44c2, 0xc02d,
-  0x44b5, 0xc02c, 0x44a9, 0xc02b, 0x449c, 0xc02b, 0x4490, 0xc02a,
-  0x4483, 0xc029, 0x4477, 0xc028, 0x446a, 0xc027, 0x445e, 0xc026,
-  0x4451, 0xc025, 0x4444, 0xc024, 0x4438, 0xc024, 0x442b, 0xc023,
-  0x441f, 0xc022, 0x4412, 0xc021, 0x4406, 0xc020, 0x43f9, 0xc020,
-  0x43ed, 0xc01f, 0x43e0, 0xc01e, 0x43d4, 0xc01d, 0x43c7, 0xc01d,
-  0x43bb, 0xc01c, 0x43ae, 0xc01b, 0x43a1, 0xc01a, 0x4395, 0xc01a,
-  0x4388, 0xc019, 0x437c, 0xc018, 0x436f, 0xc018, 0x4363, 0xc017,
-  0x4356, 0xc016, 0x434a, 0xc016, 0x433d, 0xc015, 0x4330, 0xc014,
-  0x4324, 0xc014, 0x4317, 0xc013, 0x430b, 0xc013, 0x42fe, 0xc012,
-  0x42f2, 0xc011, 0x42e5, 0xc011, 0x42d9, 0xc010, 0x42cc, 0xc010,
-  0x42c0, 0xc00f, 0x42b3, 0xc00f, 0x42a6, 0xc00e, 0x429a, 0xc00e,
-  0x428d, 0xc00d, 0x4281, 0xc00d, 0x4274, 0xc00c, 0x4268, 0xc00c,
-  0x425b, 0xc00b, 0x424e, 0xc00b, 0x4242, 0xc00a, 0x4235, 0xc00a,
-  0x4229, 0xc009, 0x421c, 0xc009, 0x4210, 0xc009, 0x4203, 0xc008,
-  0x41f7, 0xc008, 0x41ea, 0xc007, 0x41dd, 0xc007, 0x41d1, 0xc007,
-  0x41c4, 0xc006, 0x41b8, 0xc006, 0x41ab, 0xc006, 0x419f, 0xc005,
-  0x4192, 0xc005, 0x4186, 0xc005, 0x4179, 0xc004, 0x416c, 0xc004,
-  0x4160, 0xc004, 0x4153, 0xc004, 0x4147, 0xc003, 0x413a, 0xc003,
-  0x412e, 0xc003, 0x4121, 0xc003, 0x4114, 0xc002, 0x4108, 0xc002,
-  0x40fb, 0xc002, 0x40ef, 0xc002, 0x40e2, 0xc002, 0x40d6, 0xc001,
-  0x40c9, 0xc001, 0x40bc, 0xc001, 0x40b0, 0xc001, 0x40a3, 0xc001,
-  0x4097, 0xc001, 0x408a, 0xc001, 0x407e, 0xc000, 0x4071, 0xc000,
-  0x4065, 0xc000, 0x4058, 0xc000, 0x404b, 0xc000, 0x403f, 0xc000,
-  0x4032, 0xc000, 0x4026, 0xc000, 0x4019, 0xc000, 0x400d, 0xc000,
-};
-
-/**    
-* @brief  Initialization function for the Q15 RFFT/RIFFT.   
-* @param[in, out] *S             points to an instance of the Q15 RFFT/RIFFT structure.   
-* @param[in]      *S_CFFT        points to an instance of the Q15 CFFT/CIFFT structure.   
-* @param[in]      fftLenReal     length of the FFT.   
-* @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.   
-* @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.   
-* @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.   
-*    
-* \par Description:   
-* \par   
-* The parameter fftLenReal	Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048.    
-* \par    
-* The parameter ifftFlagR controls whether a forward or inverse transform is computed.    
-* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.    
-* \par    
-* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.    
-* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
-* \par    
-* This function also initializes Twiddle factor table.     
-*/
-
-arm_status arm_rfft_init_q15(
-  arm_rfft_instance_q15 * S,
-  arm_cfft_radix4_instance_q15 * S_CFFT,
-  uint32_t fftLenReal,
-  uint32_t ifftFlagR,
-  uint32_t bitReverseFlag)
-{
-
-  /*  Initialise the default arm status */
-  arm_status status = ARM_MATH_SUCCESS;
-
-  /*  Initialize the Real FFT length */
-  S->fftLenReal = (uint16_t) fftLenReal;
-
-  /*  Initialize the Complex FFT length */
-  S->fftLenBy2 = (uint16_t) fftLenReal / 2u;
-
-  /*  Initialize the Twiddle coefficientA pointer */
-  S->pTwiddleAReal = (q15_t *) realCoefAQ15;
-
-  /*  Initialize the Twiddle coefficientB pointer */
-  S->pTwiddleBReal = (q15_t *) realCoefBQ15;
-
-  /*  Initialize the Flag for selection of RFFT or RIFFT */
-  S->ifftFlagR = (uint8_t) ifftFlagR;
-
-  /*  Initialize the Flag for calculation Bit reversal or not */
-  S->bitReverseFlagR = (uint8_t) bitReverseFlag;
-
-  /*  Initialization of coef modifier depending on the FFT length */
-  switch (S->fftLenReal)
-  {
-  case 8192:
-    S->twidCoefRModifier = 1u;
-    break;
-  case 2048u:
-    S->twidCoefRModifier = 4u;
-    break;
-  case 512u:
-    S->twidCoefRModifier = 16u;
-    break;
-  case 128u:
-    S->twidCoefRModifier = 64u;
-    break;
-  default:
-    /*  Reporting argument error if rfftSize is not valid value */
-    status = ARM_MATH_ARGUMENT_ERROR;
-    break;
-  }
-
-  /* Init Complex FFT Instance */
-  S->pCfft = S_CFFT;
-
-  if(S->ifftFlagR)
-  {
-    /* Initializes the CIFFT Module for fftLenreal/2 length */
-    arm_cfft_radix4_init_q15(S->pCfft, S->fftLenBy2, 1u, 1u);
-  }
-  else
-  {
-    /* Initializes the CFFT Module for fftLenreal/2 length */
-    arm_cfft_radix4_init_q15(S->pCfft, S->fftLenBy2, 0u, 1u);
-  }
-
-  /* return the status of RFFT Init function */
-  return (status);
-
-}
-
-  /**    
-   * @} end of RFFT_RIFFT group    
-   */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q31.c
deleted file mode 100644
index f2f82f73b4..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q31.c
+++ /dev/null
@@ -1,4274 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_rfft_init_q31.c    
-*    
-* Description:	RFFT & RIFFT Q31 initialisation function    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/**    
- * @ingroup groupTransforms    
- */
-
-/**    
- * @addtogroup RFFT_RIFFT    
- * @{    
- */
-
-/**    
-* \par    
-* Generation floating point realCoefAQ31 array:    
-* \par    
-* n = 4096    
-* 
for (i = 0; i < n; i++)    
-* {    
-*    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));    
-*    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    
-* }
    
-* \par    
-* Convert to fixed point Q31 format    
-*     round(pATable[i] * pow(2, 31))    
-*/
-
-
-static const q31_t realCoefAQ31[8192] = {
-  0x40000000, 0xc0000000, 0x3ff36f02, 0xc000013c,
-  0x3fe6de05, 0xc00004ef, 0x3fda4d09, 0xc0000b1a,
-  0x3fcdbc0f, 0xc00013bd, 0x3fc12b16, 0xc0001ed8,
-  0x3fb49a1f, 0xc0002c6a, 0x3fa8092c, 0xc0003c74,
-  0x3f9b783c, 0xc0004ef5, 0x3f8ee750, 0xc00063ee,
-  0x3f825668, 0xc0007b5f, 0x3f75c585, 0xc0009547,
-  0x3f6934a8, 0xc000b1a7, 0x3f5ca3d0, 0xc000d07e,
-  0x3f5012fe, 0xc000f1ce, 0x3f438234, 0xc0011594,
-  0x3f36f170, 0xc0013bd3, 0x3f2a60b4, 0xc0016489,
-  0x3f1dd001, 0xc0018fb6, 0x3f113f56, 0xc001bd5c,
-  0x3f04aeb5, 0xc001ed78, 0x3ef81e1d, 0xc002200d,
-  0x3eeb8d8f, 0xc0025519, 0x3edefd0c, 0xc0028c9c,
-  0x3ed26c94, 0xc002c697, 0x3ec5dc28, 0xc003030a,
-  0x3eb94bc8, 0xc00341f4, 0x3eacbb74, 0xc0038356,
-  0x3ea02b2e, 0xc003c72f, 0x3e939af5, 0xc0040d80,
-  0x3e870aca, 0xc0045648, 0x3e7a7aae, 0xc004a188,
-  0x3e6deaa1, 0xc004ef3f, 0x3e615aa3, 0xc0053f6e,
-  0x3e54cab5, 0xc0059214, 0x3e483ad8, 0xc005e731,
-  0x3e3bab0b, 0xc0063ec6, 0x3e2f1b50, 0xc00698d3,
-  0x3e228ba7, 0xc006f556, 0x3e15fc11, 0xc0075452,
-  0x3e096c8d, 0xc007b5c4, 0x3dfcdd1d, 0xc00819ae,
-  0x3df04dc0, 0xc008800f, 0x3de3be78, 0xc008e8e8,
-  0x3dd72f45, 0xc0095438, 0x3dcaa027, 0xc009c1ff,
-  0x3dbe111e, 0xc00a323d, 0x3db1822c, 0xc00aa4f3,
-  0x3da4f351, 0xc00b1a20, 0x3d98648d, 0xc00b91c4,
-  0x3d8bd5e1, 0xc00c0be0, 0x3d7f474d, 0xc00c8872,
-  0x3d72b8d2, 0xc00d077c, 0x3d662a70, 0xc00d88fd,
-  0x3d599c28, 0xc00e0cf5, 0x3d4d0df9, 0xc00e9364,
-  0x3d407fe6, 0xc00f1c4a, 0x3d33f1ed, 0xc00fa7a8,
-  0x3d276410, 0xc010357c, 0x3d1ad650, 0xc010c5c7,
-  0x3d0e48ab, 0xc011588a, 0x3d01bb24, 0xc011edc3,
-  0x3cf52dbb, 0xc0128574, 0x3ce8a06f, 0xc0131f9b,
-  0x3cdc1342, 0xc013bc39, 0x3ccf8634, 0xc0145b4e,
-  0x3cc2f945, 0xc014fcda, 0x3cb66c77, 0xc015a0dd,
-  0x3ca9dfc8, 0xc0164757, 0x3c9d533b, 0xc016f047,
-  0x3c90c6cf, 0xc0179bae, 0x3c843a85, 0xc018498c,
-  0x3c77ae5e, 0xc018f9e1, 0x3c6b2259, 0xc019acac,
-  0x3c5e9678, 0xc01a61ee, 0x3c520aba, 0xc01b19a7,
-  0x3c457f21, 0xc01bd3d6, 0x3c38f3ac, 0xc01c907c,
-  0x3c2c685d, 0xc01d4f99, 0x3c1fdd34, 0xc01e112b,
-  0x3c135231, 0xc01ed535, 0x3c06c754, 0xc01f9bb5,
-  0x3bfa3c9f, 0xc02064ab, 0x3bedb212, 0xc0213018,
-  0x3be127ac, 0xc021fdfb, 0x3bd49d70, 0xc022ce54,
-  0x3bc8135c, 0xc023a124, 0x3bbb8973, 0xc024766a,
-  0x3baeffb3, 0xc0254e27, 0x3ba2761e, 0xc0262859,
-  0x3b95ecb4, 0xc0270502, 0x3b896375, 0xc027e421,
-  0x3b7cda63, 0xc028c5b6, 0x3b70517d, 0xc029a9c1,
-  0x3b63c8c4, 0xc02a9042, 0x3b574039, 0xc02b7939,
-  0x3b4ab7db, 0xc02c64a6, 0x3b3e2fac, 0xc02d5289,
-  0x3b31a7ac, 0xc02e42e2, 0x3b251fdc, 0xc02f35b1,
-  0x3b18983b, 0xc0302af5, 0x3b0c10cb, 0xc03122b0,
-  0x3aff898c, 0xc0321ce0, 0x3af3027e, 0xc0331986,
-  0x3ae67ba2, 0xc03418a2, 0x3ad9f4f8, 0xc0351a33,
-  0x3acd6e81, 0xc0361e3a, 0x3ac0e83d, 0xc03724b6,
-  0x3ab4622d, 0xc0382da8, 0x3aa7dc52, 0xc0393910,
-  0x3a9b56ab, 0xc03a46ed, 0x3a8ed139, 0xc03b573f,
-  0x3a824bfd, 0xc03c6a07, 0x3a75c6f8, 0xc03d7f44,
-  0x3a694229, 0xc03e96f6, 0x3a5cbd91, 0xc03fb11d,
-  0x3a503930, 0xc040cdba, 0x3a43b508, 0xc041eccc,
-  0x3a373119, 0xc0430e53, 0x3a2aad62, 0xc044324f,
-  0x3a1e29e5, 0xc04558c0, 0x3a11a6a3, 0xc04681a6,
-  0x3a05239a, 0xc047ad01, 0x39f8a0cd, 0xc048dad1,
-  0x39ec1e3b, 0xc04a0b16, 0x39df9be6, 0xc04b3dcf,
-  0x39d319cc, 0xc04c72fe, 0x39c697f0, 0xc04daaa1,
-  0x39ba1651, 0xc04ee4b8, 0x39ad94f0, 0xc0502145,
-  0x39a113cd, 0xc0516045, 0x399492ea, 0xc052a1bb,
-  0x39881245, 0xc053e5a5, 0x397b91e1, 0xc0552c03,
-  0x396f11bc, 0xc05674d6, 0x396291d9, 0xc057c01d,
-  0x39561237, 0xc0590dd8, 0x394992d7, 0xc05a5e07,
-  0x393d13b8, 0xc05bb0ab, 0x393094dd, 0xc05d05c3,
-  0x39241645, 0xc05e5d4e, 0x391797f0, 0xc05fb74e,
-  0x390b19e0, 0xc06113c2, 0x38fe9c15, 0xc06272aa,
-  0x38f21e8e, 0xc063d405, 0x38e5a14d, 0xc06537d4,
-  0x38d92452, 0xc0669e18, 0x38cca79e, 0xc06806ce,
-  0x38c02b31, 0xc06971f9, 0x38b3af0c, 0xc06adf97,
-  0x38a7332e, 0xc06c4fa8, 0x389ab799, 0xc06dc22e,
-  0x388e3c4d, 0xc06f3726, 0x3881c14b, 0xc070ae92,
-  0x38754692, 0xc0722871, 0x3868cc24, 0xc073a4c3,
-  0x385c5201, 0xc0752389, 0x384fd829, 0xc076a4c2,
-  0x38435e9d, 0xc078286e, 0x3836e55d, 0xc079ae8c,
-  0x382a6c6a, 0xc07b371e, 0x381df3c5, 0xc07cc223,
-  0x38117b6d, 0xc07e4f9b, 0x38050364, 0xc07fdf85,
-  0x37f88ba9, 0xc08171e2, 0x37ec143e, 0xc08306b2,
-  0x37df9d22, 0xc0849df4, 0x37d32657, 0xc08637a9,
-  0x37c6afdc, 0xc087d3d0, 0x37ba39b3, 0xc089726a,
-  0x37adc3db, 0xc08b1376, 0x37a14e55, 0xc08cb6f5,
-  0x3794d922, 0xc08e5ce5, 0x37886442, 0xc0900548,
-  0x377befb5, 0xc091b01d, 0x376f7b7d, 0xc0935d64,
-  0x37630799, 0xc0950d1d, 0x3756940a, 0xc096bf48,
-  0x374a20d0, 0xc09873e4, 0x373daded, 0xc09a2af3,
-  0x37313b60, 0xc09be473, 0x3724c92a, 0xc09da065,
-  0x3718574b, 0xc09f5ec8, 0x370be5c4, 0xc0a11f9d,
-  0x36ff7496, 0xc0a2e2e3, 0x36f303c0, 0xc0a4a89b,
-  0x36e69344, 0xc0a670c4, 0x36da2321, 0xc0a83b5e,
-  0x36cdb359, 0xc0aa086a, 0x36c143ec, 0xc0abd7e6,
-  0x36b4d4d9, 0xc0ada9d4, 0x36a86623, 0xc0af7e33,
-  0x369bf7c9, 0xc0b15502, 0x368f89cb, 0xc0b32e42,
-  0x36831c2b, 0xc0b509f3, 0x3676aee8, 0xc0b6e815,
-  0x366a4203, 0xc0b8c8a7, 0x365dd57d, 0xc0baabaa,
-  0x36516956, 0xc0bc911d, 0x3644fd8f, 0xc0be7901,
-  0x36389228, 0xc0c06355, 0x362c2721, 0xc0c25019,
-  0x361fbc7b, 0xc0c43f4d, 0x36135237, 0xc0c630f2,
-  0x3606e854, 0xc0c82506, 0x35fa7ed4, 0xc0ca1b8a,
-  0x35ee15b7, 0xc0cc147f, 0x35e1acfd, 0xc0ce0fe3,
-  0x35d544a7, 0xc0d00db6, 0x35c8dcb6, 0xc0d20dfa,
-  0x35bc7529, 0xc0d410ad, 0x35b00e02, 0xc0d615cf,
-  0x35a3a740, 0xc0d81d61, 0x359740e5, 0xc0da2762,
-  0x358adaf0, 0xc0dc33d2, 0x357e7563, 0xc0de42b2,
-  0x3572103d, 0xc0e05401, 0x3565ab80, 0xc0e267be,
-  0x3559472b, 0xc0e47deb, 0x354ce33f, 0xc0e69686,
-  0x35407fbd, 0xc0e8b190, 0x35341ca5, 0xc0eacf09,
-  0x3527b9f7, 0xc0eceef1, 0x351b57b5, 0xc0ef1147,
-  0x350ef5de, 0xc0f1360b, 0x35029473, 0xc0f35d3e,
-  0x34f63374, 0xc0f586df, 0x34e9d2e3, 0xc0f7b2ee,
-  0x34dd72be, 0xc0f9e16b, 0x34d11308, 0xc0fc1257,
-  0x34c4b3c0, 0xc0fe45b0, 0x34b854e7, 0xc1007b77,
-  0x34abf67e, 0xc102b3ac, 0x349f9884, 0xc104ee4f,
-  0x34933afa, 0xc1072b5f, 0x3486dde1, 0xc1096add,
-  0x347a8139, 0xc10bacc8, 0x346e2504, 0xc10df120,
-  0x3461c940, 0xc11037e6, 0x34556def, 0xc1128119,
-  0x34491311, 0xc114ccb9, 0x343cb8a7, 0xc1171ac6,
-  0x34305eb0, 0xc1196b3f, 0x3424052f, 0xc11bbe26,
-  0x3417ac22, 0xc11e1379, 0x340b538b, 0xc1206b39,
-  0x33fefb6a, 0xc122c566, 0x33f2a3bf, 0xc12521ff,
-  0x33e64c8c, 0xc1278104, 0x33d9f5cf, 0xc129e276,
-  0x33cd9f8b, 0xc12c4653, 0x33c149bf, 0xc12eac9d,
-  0x33b4f46c, 0xc1311553, 0x33a89f92, 0xc1338075,
-  0x339c4b32, 0xc135ee02, 0x338ff74d, 0xc1385dfb,
-  0x3383a3e2, 0xc13ad060, 0x337750f2, 0xc13d4530,
-  0x336afe7e, 0xc13fbc6c, 0x335eac86, 0xc1423613,
-  0x33525b0b, 0xc144b225, 0x33460a0d, 0xc14730a3,
-  0x3339b98d, 0xc149b18b, 0x332d698a, 0xc14c34df,
-  0x33211a07, 0xc14eba9d, 0x3314cb02, 0xc15142c6,
-  0x33087c7d, 0xc153cd5a, 0x32fc2e77, 0xc1565a58,
-  0x32efe0f2, 0xc158e9c1, 0x32e393ef, 0xc15b7b94,
-  0x32d7476c, 0xc15e0fd1, 0x32cafb6b, 0xc160a678,
-  0x32beafed, 0xc1633f8a, 0x32b264f2, 0xc165db05,
-  0x32a61a7a, 0xc16878eb, 0x3299d085, 0xc16b193a,
-  0x328d8715, 0xc16dbbf3, 0x32813e2a, 0xc1706115,
-  0x3274f5c3, 0xc17308a1, 0x3268ade3, 0xc175b296,
-  0x325c6688, 0xc1785ef4, 0x32501fb5, 0xc17b0dbb,
-  0x3243d968, 0xc17dbeec, 0x323793a3, 0xc1807285,
-  0x322b4e66, 0xc1832888, 0x321f09b1, 0xc185e0f3,
-  0x3212c585, 0xc1889bc6, 0x320681e3, 0xc18b5903,
-  0x31fa3ecb, 0xc18e18a7, 0x31edfc3d, 0xc190dab4,
-  0x31e1ba3a, 0xc1939f29, 0x31d578c2, 0xc1966606,
-  0x31c937d6, 0xc1992f4c, 0x31bcf777, 0xc19bfaf9,
-  0x31b0b7a4, 0xc19ec90d, 0x31a4785e, 0xc1a1998a,
-  0x319839a6, 0xc1a46c6e, 0x318bfb7d, 0xc1a741b9,
-  0x317fbde2, 0xc1aa196c, 0x317380d6, 0xc1acf386,
-  0x31674459, 0xc1afd007, 0x315b086d, 0xc1b2aef0,
-  0x314ecd11, 0xc1b5903f, 0x31429247, 0xc1b873f5,
-  0x3136580d, 0xc1bb5a11, 0x312a1e66, 0xc1be4294,
-  0x311de551, 0xc1c12d7e, 0x3111accf, 0xc1c41ace,
-  0x310574e0, 0xc1c70a84, 0x30f93d86, 0xc1c9fca0,
-  0x30ed06bf, 0xc1ccf122, 0x30e0d08d, 0xc1cfe80a,
-  0x30d49af1, 0xc1d2e158, 0x30c865ea, 0xc1d5dd0c,
-  0x30bc317a, 0xc1d8db25, 0x30affda0, 0xc1dbdba3,
-  0x30a3ca5d, 0xc1dede87, 0x309797b2, 0xc1e1e3d0,
-  0x308b659f, 0xc1e4eb7e, 0x307f3424, 0xc1e7f591,
-  0x30730342, 0xc1eb0209, 0x3066d2fa, 0xc1ee10e5,
-  0x305aa34c, 0xc1f12227, 0x304e7438, 0xc1f435cc,
-  0x304245c0, 0xc1f74bd6, 0x303617e2, 0xc1fa6445,
-  0x3029eaa1, 0xc1fd7f17, 0x301dbdfb, 0xc2009c4e,
-  0x301191f3, 0xc203bbe8, 0x30056687, 0xc206dde6,
-  0x2ff93bba, 0xc20a0248, 0x2fed118a, 0xc20d290d,
-  0x2fe0e7f9, 0xc2105236, 0x2fd4bf08, 0xc2137dc2,
-  0x2fc896b5, 0xc216abb1, 0x2fbc6f03, 0xc219dc03,
-  0x2fb047f2, 0xc21d0eb8, 0x2fa42181, 0xc22043d0,
-  0x2f97fbb2, 0xc2237b4b, 0x2f8bd685, 0xc226b528,
-  0x2f7fb1fa, 0xc229f167, 0x2f738e12, 0xc22d3009,
-  0x2f676ace, 0xc230710d, 0x2f5b482d, 0xc233b473,
-  0x2f4f2630, 0xc236fa3b, 0x2f4304d8, 0xc23a4265,
-  0x2f36e426, 0xc23d8cf1, 0x2f2ac419, 0xc240d9de,
-  0x2f1ea4b2, 0xc244292c, 0x2f1285f2, 0xc2477adc,
-  0x2f0667d9, 0xc24aceed, 0x2efa4a67, 0xc24e255e,
-  0x2eee2d9d, 0xc2517e31, 0x2ee2117c, 0xc254d965,
-  0x2ed5f604, 0xc25836f9, 0x2ec9db35, 0xc25b96ee,
-  0x2ebdc110, 0xc25ef943, 0x2eb1a796, 0xc2625df8,
-  0x2ea58ec6, 0xc265c50e, 0x2e9976a1, 0xc2692e83,
-  0x2e8d5f29, 0xc26c9a58, 0x2e81485c, 0xc270088e,
-  0x2e75323c, 0xc2737922, 0x2e691cc9, 0xc276ec16,
-  0x2e5d0804, 0xc27a616a, 0x2e50f3ed, 0xc27dd91c,
-  0x2e44e084, 0xc281532e, 0x2e38cdcb, 0xc284cf9f,
-  0x2e2cbbc1, 0xc2884e6e, 0x2e20aa67, 0xc28bcf9c,
-  0x2e1499bd, 0xc28f5329, 0x2e0889c4, 0xc292d914,
-  0x2dfc7a7c, 0xc296615d, 0x2df06be6, 0xc299ec05,
-  0x2de45e03, 0xc29d790a, 0x2dd850d2, 0xc2a1086d,
-  0x2dcc4454, 0xc2a49a2e, 0x2dc0388a, 0xc2a82e4d,
-  0x2db42d74, 0xc2abc4c9, 0x2da82313, 0xc2af5da2,
-  0x2d9c1967, 0xc2b2f8d8, 0x2d901070, 0xc2b6966c,
-  0x2d84082f, 0xc2ba365c, 0x2d7800a5, 0xc2bdd8a9,
-  0x2d6bf9d1, 0xc2c17d52, 0x2d5ff3b5, 0xc2c52459,
-  0x2d53ee51, 0xc2c8cdbb, 0x2d47e9a5, 0xc2cc7979,
-  0x2d3be5b1, 0xc2d02794, 0x2d2fe277, 0xc2d3d80a,
-  0x2d23dff7, 0xc2d78add, 0x2d17de31, 0xc2db400a,
-  0x2d0bdd25, 0xc2def794, 0x2cffdcd4, 0xc2e2b178,
-  0x2cf3dd3f, 0xc2e66db8, 0x2ce7de66, 0xc2ea2c53,
-  0x2cdbe04a, 0xc2eded49, 0x2ccfe2ea, 0xc2f1b099,
-  0x2cc3e648, 0xc2f57644, 0x2cb7ea63, 0xc2f93e4a,
-  0x2cabef3d, 0xc2fd08a9, 0x2c9ff4d6, 0xc300d563,
-  0x2c93fb2e, 0xc304a477, 0x2c880245, 0xc30875e5,
-  0x2c7c0a1d, 0xc30c49ad, 0x2c7012b5, 0xc3101fce,
-  0x2c641c0e, 0xc313f848, 0x2c582629, 0xc317d31c,
-  0x2c4c3106, 0xc31bb049, 0x2c403ca5, 0xc31f8fcf,
-  0x2c344908, 0xc32371ae, 0x2c28562d, 0xc32755e5,
-  0x2c1c6417, 0xc32b3c75, 0x2c1072c4, 0xc32f255e,
-  0x2c048237, 0xc333109e, 0x2bf8926f, 0xc336fe37,
-  0x2beca36c, 0xc33aee27, 0x2be0b52f, 0xc33ee070,
-  0x2bd4c7ba, 0xc342d510, 0x2bc8db0b, 0xc346cc07,
-  0x2bbcef23, 0xc34ac556, 0x2bb10404, 0xc34ec0fc,
-  0x2ba519ad, 0xc352bef9, 0x2b99301f, 0xc356bf4d,
-  0x2b8d475b, 0xc35ac1f7, 0x2b815f60, 0xc35ec6f8,
-  0x2b75782f, 0xc362ce50, 0x2b6991ca, 0xc366d7fd,
-  0x2b5dac2f, 0xc36ae401, 0x2b51c760, 0xc36ef25b,
-  0x2b45e35d, 0xc373030a, 0x2b3a0027, 0xc377160f,
-  0x2b2e1dbe, 0xc37b2b6a, 0x2b223c22, 0xc37f4319,
-  0x2b165b54, 0xc3835d1e, 0x2b0a7b54, 0xc3877978,
-  0x2afe9c24, 0xc38b9827, 0x2af2bdc3, 0xc38fb92a,
-  0x2ae6e031, 0xc393dc82, 0x2adb0370, 0xc398022f,
-  0x2acf277f, 0xc39c2a2f, 0x2ac34c60, 0xc3a05484,
-  0x2ab77212, 0xc3a4812c, 0x2aab9896, 0xc3a8b028,
-  0x2a9fbfed, 0xc3ace178, 0x2a93e817, 0xc3b1151b,
-  0x2a881114, 0xc3b54b11, 0x2a7c3ae5, 0xc3b9835a,
-  0x2a70658a, 0xc3bdbdf6, 0x2a649105, 0xc3c1fae5,
-  0x2a58bd54, 0xc3c63a26, 0x2a4cea79, 0xc3ca7bba,
-  0x2a411874, 0xc3cebfa0, 0x2a354746, 0xc3d305d8,
-  0x2a2976ef, 0xc3d74e62, 0x2a1da770, 0xc3db993e,
-  0x2a11d8c8, 0xc3dfe66c, 0x2a060af9, 0xc3e435ea,
-  0x29fa3e03, 0xc3e887bb, 0x29ee71e6, 0xc3ecdbdc,
-  0x29e2a6a3, 0xc3f1324e, 0x29d6dc3b, 0xc3f58b10,
-  0x29cb12ad, 0xc3f9e624, 0x29bf49fa, 0xc3fe4388,
-  0x29b38223, 0xc402a33c, 0x29a7bb28, 0xc4070540,
-  0x299bf509, 0xc40b6994, 0x29902fc7, 0xc40fd037,
-  0x29846b63, 0xc414392b, 0x2978a7dd, 0xc418a46d,
-  0x296ce535, 0xc41d11ff, 0x2961236c, 0xc42181e0,
-  0x29556282, 0xc425f410, 0x2949a278, 0xc42a688f,
-  0x293de34e, 0xc42edf5c, 0x29322505, 0xc4335877,
-  0x2926679c, 0xc437d3e1, 0x291aab16, 0xc43c5199,
-  0x290eef71, 0xc440d19e, 0x290334af, 0xc44553f2,
-  0x28f77acf, 0xc449d892, 0x28ebc1d3, 0xc44e5f80,
-  0x28e009ba, 0xc452e8bc, 0x28d45286, 0xc4577444,
-  0x28c89c37, 0xc45c0219, 0x28bce6cd, 0xc460923b,
-  0x28b13248, 0xc46524a9, 0x28a57ea9, 0xc469b963,
-  0x2899cbf1, 0xc46e5069, 0x288e1a20, 0xc472e9bc,
-  0x28826936, 0xc477855a, 0x2876b934, 0xc47c2344,
-  0x286b0a1a, 0xc480c379, 0x285f5be9, 0xc48565f9,
-  0x2853aea1, 0xc48a0ac4, 0x28480243, 0xc48eb1db,
-  0x283c56cf, 0xc4935b3c, 0x2830ac45, 0xc49806e7,
-  0x282502a7, 0xc49cb4dd, 0x281959f4, 0xc4a1651c,
-  0x280db22d, 0xc4a617a6, 0x28020b52, 0xc4aacc7a,
-  0x27f66564, 0xc4af8397, 0x27eac063, 0xc4b43cfd,
-  0x27df1c50, 0xc4b8f8ad, 0x27d3792b, 0xc4bdb6a6,
-  0x27c7d6f4, 0xc4c276e8, 0x27bc35ad, 0xc4c73972,
-  0x27b09555, 0xc4cbfe45, 0x27a4f5ed, 0xc4d0c560,
-  0x27995776, 0xc4d58ec3, 0x278db9ef, 0xc4da5a6f,
-  0x27821d59, 0xc4df2862, 0x277681b6, 0xc4e3f89c,
-  0x276ae704, 0xc4e8cb1e, 0x275f4d45, 0xc4ed9fe7,
-  0x2753b479, 0xc4f276f7, 0x27481ca1, 0xc4f7504e,
-  0x273c85bc, 0xc4fc2bec, 0x2730efcc, 0xc50109d0,
-  0x27255ad1, 0xc505e9fb, 0x2719c6cb, 0xc50acc6b,
-  0x270e33bb, 0xc50fb121, 0x2702a1a1, 0xc514981d,
-  0x26f7107e, 0xc519815f, 0x26eb8052, 0xc51e6ce6,
-  0x26dff11d, 0xc5235ab2, 0x26d462e1, 0xc5284ac3,
-  0x26c8d59c, 0xc52d3d18, 0x26bd4951, 0xc53231b3,
-  0x26b1bdff, 0xc5372891, 0x26a633a6, 0xc53c21b4,
-  0x269aaa48, 0xc5411d1b, 0x268f21e5, 0xc5461ac6,
-  0x26839a7c, 0xc54b1ab4, 0x26781410, 0xc5501ce5,
-  0x266c8e9f, 0xc555215a, 0x26610a2a, 0xc55a2812,
-  0x265586b3, 0xc55f310d, 0x264a0438, 0xc5643c4a,
-  0x263e82bc, 0xc56949ca, 0x2633023e, 0xc56e598c,
-  0x262782be, 0xc5736b90, 0x261c043d, 0xc5787fd6,
-  0x261086bc, 0xc57d965d, 0x26050a3b, 0xc582af26,
-  0x25f98ebb, 0xc587ca31, 0x25ee143b, 0xc58ce77c,
-  0x25e29abc, 0xc5920708, 0x25d72240, 0xc59728d5,
-  0x25cbaac5, 0xc59c4ce3, 0x25c0344d, 0xc5a17330,
-  0x25b4bed8, 0xc5a69bbe, 0x25a94a67, 0xc5abc68c,
-  0x259dd6f9, 0xc5b0f399, 0x25926490, 0xc5b622e6,
-  0x2586f32c, 0xc5bb5472, 0x257b82cd, 0xc5c0883d,
-  0x25701374, 0xc5c5be47, 0x2564a521, 0xc5caf690,
-  0x255937d5, 0xc5d03118, 0x254dcb8f, 0xc5d56ddd,
-  0x25426051, 0xc5daace1, 0x2536f61b, 0xc5dfee22,
-  0x252b8cee, 0xc5e531a1, 0x252024c9, 0xc5ea775e,
-  0x2514bdad, 0xc5efbf58, 0x2509579b, 0xc5f5098f,
-  0x24fdf294, 0xc5fa5603, 0x24f28e96, 0xc5ffa4b3,
-  0x24e72ba4, 0xc604f5a0, 0x24dbc9bd, 0xc60a48c9,
-  0x24d068e2, 0xc60f9e2e, 0x24c50914, 0xc614f5cf,
-  0x24b9aa52, 0xc61a4fac, 0x24ae4c9d, 0xc61fabc4,
-  0x24a2eff6, 0xc6250a18, 0x2497945d, 0xc62a6aa6,
-  0x248c39d3, 0xc62fcd6f, 0x2480e057, 0xc6353273,
-  0x247587eb, 0xc63a99b1, 0x246a308f, 0xc6400329,
-  0x245eda43, 0xc6456edb, 0x24538507, 0xc64adcc7,
-  0x244830dd, 0xc6504ced, 0x243cddc4, 0xc655bf4c,
-  0x24318bbe, 0xc65b33e4, 0x24263ac9, 0xc660aab5,
-  0x241aeae8, 0xc66623be, 0x240f9c1a, 0xc66b9f01,
-  0x24044e60, 0xc6711c7b, 0x23f901ba, 0xc6769c2e,
-  0x23edb628, 0xc67c1e18, 0x23e26bac, 0xc681a23a,
-  0x23d72245, 0xc6872894, 0x23cbd9f4, 0xc68cb124,
-  0x23c092b9, 0xc6923bec, 0x23b54c95, 0xc697c8eb,
-  0x23aa0788, 0xc69d5820, 0x239ec393, 0xc6a2e98b,
-  0x239380b6, 0xc6a87d2d, 0x23883ef2, 0xc6ae1304,
-  0x237cfe47, 0xc6b3ab12, 0x2371beb5, 0xc6b94554,
-  0x2366803c, 0xc6bee1cd, 0x235b42df, 0xc6c4807a,
-  0x2350069b, 0xc6ca215c, 0x2344cb73, 0xc6cfc472,
-  0x23399167, 0xc6d569be, 0x232e5876, 0xc6db113d,
-  0x232320a2, 0xc6e0baf0, 0x2317e9eb, 0xc6e666d7,
-  0x230cb451, 0xc6ec14f2, 0x23017fd5, 0xc6f1c540,
-  0x22f64c77, 0xc6f777c1, 0x22eb1a37, 0xc6fd2c75,
-  0x22dfe917, 0xc702e35c, 0x22d4b916, 0xc7089c75,
-  0x22c98a35, 0xc70e57c0, 0x22be5c74, 0xc714153e,
-  0x22b32fd4, 0xc719d4ed, 0x22a80456, 0xc71f96ce,
-  0x229cd9f8, 0xc7255ae0, 0x2291b0bd, 0xc72b2123,
-  0x228688a4, 0xc730e997, 0x227b61af, 0xc736b43c,
-  0x22703bdc, 0xc73c8111, 0x2265172e, 0xc7425016,
-  0x2259f3a3, 0xc748214c, 0x224ed13d, 0xc74df4b1,
-  0x2243affc, 0xc753ca46, 0x22388fe1, 0xc759a20a,
-  0x222d70eb, 0xc75f7bfe, 0x2222531c, 0xc7655820,
-  0x22173674, 0xc76b3671, 0x220c1af3, 0xc77116f0,
-  0x22010099, 0xc776f99d, 0x21f5e768, 0xc77cde79,
-  0x21eacf5f, 0xc782c582, 0x21dfb87f, 0xc788aeb9,
-  0x21d4a2c8, 0xc78e9a1d, 0x21c98e3b, 0xc79487ae,
-  0x21be7ad8, 0xc79a776c, 0x21b368a0, 0xc7a06957,
-  0x21a85793, 0xc7a65d6e, 0x219d47b1, 0xc7ac53b1,
-  0x219238fb, 0xc7b24c20, 0x21872b72, 0xc7b846ba,
-  0x217c1f15, 0xc7be4381, 0x217113e5, 0xc7c44272,
-  0x216609e3, 0xc7ca438f, 0x215b0110, 0xc7d046d6,
-  0x214ff96a, 0xc7d64c47, 0x2144f2f3, 0xc7dc53e3,
-  0x2139edac, 0xc7e25daa, 0x212ee995, 0xc7e8699a,
-  0x2123e6ad, 0xc7ee77b3, 0x2118e4f6, 0xc7f487f6,
-  0x210de470, 0xc7fa9a62, 0x2102e51c, 0xc800aef7,
-  0x20f7e6f9, 0xc806c5b5, 0x20ecea09, 0xc80cde9b,
-  0x20e1ee4b, 0xc812f9a9, 0x20d6f3c1, 0xc81916df,
-  0x20cbfa6a, 0xc81f363d, 0x20c10247, 0xc82557c3,
-  0x20b60b58, 0xc82b7b70, 0x20ab159e, 0xc831a143,
-  0x20a0211a, 0xc837c93e, 0x20952dcb, 0xc83df35f,
-  0x208a3bb2, 0xc8441fa6, 0x207f4acf, 0xc84a4e14,
-  0x20745b24, 0xc8507ea7, 0x20696cb0, 0xc856b160,
-  0x205e7f74, 0xc85ce63e, 0x2053936f, 0xc8631d42,
-  0x2048a8a4, 0xc869566a, 0x203dbf11, 0xc86f91b7,
-  0x2032d6b8, 0xc875cf28, 0x2027ef99, 0xc87c0ebd,
-  0x201d09b4, 0xc8825077, 0x2012250a, 0xc8889454,
-  0x2007419b, 0xc88eda54, 0x1ffc5f67, 0xc8952278,
-  0x1ff17e70, 0xc89b6cbf, 0x1fe69eb4, 0xc8a1b928,
-  0x1fdbc036, 0xc8a807b4, 0x1fd0e2f5, 0xc8ae5862,
-  0x1fc606f1, 0xc8b4ab32, 0x1fbb2c2c, 0xc8bb0023,
-  0x1fb052a5, 0xc8c15736, 0x1fa57a5d, 0xc8c7b06b,
-  0x1f9aa354, 0xc8ce0bc0, 0x1f8fcd8b, 0xc8d46936,
-  0x1f84f902, 0xc8dac8cd, 0x1f7a25ba, 0xc8e12a84,
-  0x1f6f53b3, 0xc8e78e5b, 0x1f6482ed, 0xc8edf452,
-  0x1f59b369, 0xc8f45c68, 0x1f4ee527, 0xc8fac69e,
-  0x1f441828, 0xc90132f2, 0x1f394c6b, 0xc907a166,
-  0x1f2e81f3, 0xc90e11f7, 0x1f23b8be, 0xc91484a8,
-  0x1f18f0ce, 0xc91af976, 0x1f0e2a22, 0xc9217062,
-  0x1f0364bc, 0xc927e96b, 0x1ef8a09b, 0xc92e6492,
-  0x1eedddc0, 0xc934e1d6, 0x1ee31c2b, 0xc93b6137,
-  0x1ed85bdd, 0xc941e2b4, 0x1ecd9cd7, 0xc948664d,
-  0x1ec2df18, 0xc94eec03, 0x1eb822a1, 0xc95573d4,
-  0x1ead6773, 0xc95bfdc1, 0x1ea2ad8d, 0xc96289c9,
-  0x1e97f4f1, 0xc96917ec, 0x1e8d3d9e, 0xc96fa82a,
-  0x1e828796, 0xc9763a83, 0x1e77d2d8, 0xc97ccef5,
-  0x1e6d1f65, 0xc9836582, 0x1e626d3e, 0xc989fe29,
-  0x1e57bc62, 0xc99098e9, 0x1e4d0cd2, 0xc99735c2,
-  0x1e425e8f, 0xc99dd4b4, 0x1e37b199, 0xc9a475bf,
-  0x1e2d05f1, 0xc9ab18e3, 0x1e225b96, 0xc9b1be1e,
-  0x1e17b28a, 0xc9b86572, 0x1e0d0acc, 0xc9bf0edd,
-  0x1e02645d, 0xc9c5ba60, 0x1df7bf3e, 0xc9cc67fa,
-  0x1ded1b6e, 0xc9d317ab, 0x1de278ef, 0xc9d9c973,
-  0x1dd7d7c1, 0xc9e07d51, 0x1dcd37e4, 0xc9e73346,
-  0x1dc29958, 0xc9edeb50, 0x1db7fc1e, 0xc9f4a570,
-  0x1dad6036, 0xc9fb61a5, 0x1da2c5a2, 0xca021fef,
-  0x1d982c60, 0xca08e04f, 0x1d8d9472, 0xca0fa2c3,
-  0x1d82fdd8, 0xca16674b, 0x1d786892, 0xca1d2de7,
-  0x1d6dd4a2, 0xca23f698, 0x1d634206, 0xca2ac15b,
-  0x1d58b0c0, 0xca318e32, 0x1d4e20d0, 0xca385d1d,
-  0x1d439236, 0xca3f2e19, 0x1d3904f4, 0xca460129,
-  0x1d2e7908, 0xca4cd64b, 0x1d23ee74, 0xca53ad7e,
-  0x1d196538, 0xca5a86c4, 0x1d0edd55, 0xca61621b,
-  0x1d0456ca, 0xca683f83, 0x1cf9d199, 0xca6f1efc,
-  0x1cef4dc2, 0xca760086, 0x1ce4cb44, 0xca7ce420,
-  0x1cda4a21, 0xca83c9ca, 0x1ccfca59, 0xca8ab184,
-  0x1cc54bec, 0xca919b4e, 0x1cbacedb, 0xca988727,
-  0x1cb05326, 0xca9f750f, 0x1ca5d8cd, 0xcaa66506,
-  0x1c9b5fd2, 0xcaad570c, 0x1c90e834, 0xcab44b1f,
-  0x1c8671f3, 0xcabb4141, 0x1c7bfd11, 0xcac23971,
-  0x1c71898d, 0xcac933ae, 0x1c671768, 0xcad02ff8,
-  0x1c5ca6a2, 0xcad72e4f, 0x1c52373c, 0xcade2eb3,
-  0x1c47c936, 0xcae53123, 0x1c3d5c91, 0xcaec35a0,
-  0x1c32f14d, 0xcaf33c28, 0x1c28876a, 0xcafa44bc,
-  0x1c1e1ee9, 0xcb014f5b, 0x1c13b7c9, 0xcb085c05,
-  0x1c09520d, 0xcb0f6aba, 0x1bfeedb3, 0xcb167b79,
-  0x1bf48abd, 0xcb1d8e43, 0x1bea292b, 0xcb24a316,
-  0x1bdfc8fc, 0xcb2bb9f4, 0x1bd56a32, 0xcb32d2da,
-  0x1bcb0cce, 0xcb39edca, 0x1bc0b0ce, 0xcb410ac3,
-  0x1bb65634, 0xcb4829c4, 0x1babfd01, 0xcb4f4acd,
-  0x1ba1a534, 0xcb566ddf, 0x1b974ece, 0xcb5d92f8,
-  0x1b8cf9cf, 0xcb64ba19, 0x1b82a638, 0xcb6be341,
-  0x1b785409, 0xcb730e70, 0x1b6e0342, 0xcb7a3ba5,
-  0x1b63b3e5, 0xcb816ae1, 0x1b5965f1, 0xcb889c23,
-  0x1b4f1967, 0xcb8fcf6b, 0x1b44ce46, 0xcb9704b9,
-  0x1b3a8491, 0xcb9e3c0b, 0x1b303c46, 0xcba57563,
-  0x1b25f566, 0xcbacb0bf, 0x1b1baff2, 0xcbb3ee20,
-  0x1b116beb, 0xcbbb2d85, 0x1b072950, 0xcbc26eee,
-  0x1afce821, 0xcbc9b25a, 0x1af2a860, 0xcbd0f7ca,
-  0x1ae86a0d, 0xcbd83f3d, 0x1ade2d28, 0xcbdf88b3,
-  0x1ad3f1b1, 0xcbe6d42b, 0x1ac9b7a9, 0xcbee21a5,
-  0x1abf7f11, 0xcbf57121, 0x1ab547e8, 0xcbfcc29f,
-  0x1aab122f, 0xcc04161e, 0x1aa0dde7, 0xcc0b6b9e,
-  0x1a96ab0f, 0xcc12c31f, 0x1a8c79a9, 0xcc1a1ca0,
-  0x1a8249b4, 0xcc217822, 0x1a781b31, 0xcc28d5a3,
-  0x1a6dee21, 0xcc303524, 0x1a63c284, 0xcc3796a5,
-  0x1a599859, 0xcc3efa25, 0x1a4f6fa3, 0xcc465fa3,
-  0x1a454860, 0xcc4dc720, 0x1a3b2292, 0xcc55309b,
-  0x1a30fe38, 0xcc5c9c14, 0x1a26db54, 0xcc64098b,
-  0x1a1cb9e5, 0xcc6b78ff, 0x1a1299ec, 0xcc72ea70,
-  0x1a087b69, 0xcc7a5dde, 0x19fe5e5e, 0xcc81d349,
-  0x19f442c9, 0xcc894aaf, 0x19ea28ac, 0xcc90c412,
-  0x19e01006, 0xcc983f70, 0x19d5f8d9, 0xcc9fbcca,
-  0x19cbe325, 0xcca73c1e, 0x19c1cee9, 0xccaebd6e,
-  0x19b7bc27, 0xccb640b8, 0x19adaadf, 0xccbdc5fc,
-  0x19a39b11, 0xccc54d3a, 0x19998cbe, 0xccccd671,
-  0x198f7fe6, 0xccd461a2, 0x19857489, 0xccdbeecc,
-  0x197b6aa8, 0xcce37def, 0x19716243, 0xcceb0f0a,
-  0x19675b5a, 0xccf2a21d, 0x195d55ef, 0xccfa3729,
-  0x19535201, 0xcd01ce2b, 0x19494f90, 0xcd096725,
-  0x193f4e9e, 0xcd110216, 0x19354f2a, 0xcd189efe,
-  0x192b5135, 0xcd203ddc, 0x192154bf, 0xcd27deb0,
-  0x191759c9, 0xcd2f817b, 0x190d6053, 0xcd37263a,
-  0x1903685d, 0xcd3eccef, 0x18f971e8, 0xcd467599,
-  0x18ef7cf4, 0xcd4e2037, 0x18e58982, 0xcd55ccca,
-  0x18db9792, 0xcd5d7b50, 0x18d1a724, 0xcd652bcb,
-  0x18c7b838, 0xcd6cde39, 0x18bdcad0, 0xcd74929a,
-  0x18b3deeb, 0xcd7c48ee, 0x18a9f48a, 0xcd840134,
-  0x18a00bae, 0xcd8bbb6d, 0x18962456, 0xcd937798,
-  0x188c3e83, 0xcd9b35b4, 0x18825a35, 0xcda2f5c2,
-  0x1878776d, 0xcdaab7c0, 0x186e962b, 0xcdb27bb0,
-  0x1864b670, 0xcdba4190, 0x185ad83c, 0xcdc20960,
-  0x1850fb8e, 0xcdc9d320, 0x18472069, 0xcdd19ed0,
-  0x183d46cc, 0xcdd96c6f, 0x18336eb7, 0xcde13bfd,
-  0x1829982b, 0xcde90d79, 0x181fc328, 0xcdf0e0e4,
-  0x1815efae, 0xcdf8b63d, 0x180c1dbf, 0xce008d84,
-  0x18024d59, 0xce0866b8, 0x17f87e7f, 0xce1041d9,
-  0x17eeb130, 0xce181ee8, 0x17e4e56c, 0xce1ffde2,
-  0x17db1b34, 0xce27dec9, 0x17d15288, 0xce2fc19c,
-  0x17c78b68, 0xce37a65b, 0x17bdc5d6, 0xce3f8d05,
-  0x17b401d1, 0xce47759a, 0x17aa3f5a, 0xce4f6019,
-  0x17a07e70, 0xce574c84, 0x1796bf16, 0xce5f3ad8,
-  0x178d014a, 0xce672b16, 0x1783450d, 0xce6f1d3d,
-  0x17798a60, 0xce77114e, 0x176fd143, 0xce7f0748,
-  0x176619b6, 0xce86ff2a, 0x175c63ba, 0xce8ef8f4,
-  0x1752af4f, 0xce96f4a7, 0x1748fc75, 0xce9ef241,
-  0x173f4b2e, 0xcea6f1c2, 0x17359b78, 0xceaef32b,
-  0x172bed55, 0xceb6f67a, 0x172240c5, 0xcebefbb0,
-  0x171895c9, 0xcec702cb, 0x170eec60, 0xcecf0bcd,
-  0x1705448b, 0xced716b4, 0x16fb9e4b, 0xcedf2380,
-  0x16f1f99f, 0xcee73231, 0x16e85689, 0xceef42c7,
-  0x16deb508, 0xcef75541, 0x16d5151d, 0xceff699f,
-  0x16cb76c9, 0xcf077fe1, 0x16c1da0b, 0xcf0f9805,
-  0x16b83ee4, 0xcf17b20d, 0x16aea555, 0xcf1fcdf8,
-  0x16a50d5d, 0xcf27ebc5, 0x169b76fe, 0xcf300b74,
-  0x1691e237, 0xcf382d05, 0x16884f09, 0xcf405077,
-  0x167ebd74, 0xcf4875ca, 0x16752d79, 0xcf509cfe,
-  0x166b9f18, 0xcf58c613, 0x16621251, 0xcf60f108,
-  0x16588725, 0xcf691ddd, 0x164efd94, 0xcf714c91,
-  0x1645759f, 0xcf797d24, 0x163bef46, 0xcf81af97,
-  0x16326a88, 0xcf89e3e8, 0x1628e767, 0xcf921a17,
-  0x161f65e4, 0xcf9a5225, 0x1615e5fd, 0xcfa28c10,
-  0x160c67b4, 0xcfaac7d8, 0x1602eb0a, 0xcfb3057d,
-  0x15f96ffd, 0xcfbb4500, 0x15eff690, 0xcfc3865e,
-  0x15e67ec1, 0xcfcbc999, 0x15dd0892, 0xcfd40eaf,
-  0x15d39403, 0xcfdc55a1, 0x15ca2115, 0xcfe49e6d,
-  0x15c0afc6, 0xcfece915, 0x15b74019, 0xcff53597,
-  0x15add20d, 0xcffd83f4, 0x15a465a3, 0xd005d42a,
-  0x159afadb, 0xd00e2639, 0x159191b5, 0xd0167a22,
-  0x15882a32, 0xd01ecfe4, 0x157ec452, 0xd027277e,
-  0x15756016, 0xd02f80f1, 0x156bfd7d, 0xd037dc3b,
-  0x15629c89, 0xd040395d, 0x15593d3a, 0xd0489856,
-  0x154fdf8f, 0xd050f926, 0x15468389, 0xd0595bcd,
-  0x153d292a, 0xd061c04a, 0x1533d070, 0xd06a269d,
-  0x152a795d, 0xd0728ec6, 0x152123f0, 0xd07af8c4,
-  0x1517d02b, 0xd0836497, 0x150e7e0d, 0xd08bd23f,
-  0x15052d97, 0xd09441bb, 0x14fbdec9, 0xd09cb30b,
-  0x14f291a4, 0xd0a5262f, 0x14e94627, 0xd0ad9b26,
-  0x14dffc54, 0xd0b611f1, 0x14d6b42b, 0xd0be8a8d,
-  0x14cd6dab, 0xd0c704fd, 0x14c428d6, 0xd0cf813e,
-  0x14bae5ab, 0xd0d7ff51, 0x14b1a42c, 0xd0e07f36,
-  0x14a86458, 0xd0e900ec, 0x149f2630, 0xd0f18472,
-  0x1495e9b3, 0xd0fa09c9, 0x148caee4, 0xd10290f0,
-  0x148375c1, 0xd10b19e7, 0x147a3e4b, 0xd113a4ad,
-  0x14710883, 0xd11c3142, 0x1467d469, 0xd124bfa6,
-  0x145ea1fd, 0xd12d4fd9, 0x14557140, 0xd135e1d9,
-  0x144c4232, 0xd13e75a8, 0x144314d3, 0xd1470b44,
-  0x1439e923, 0xd14fa2ad, 0x1430bf24, 0xd1583be2,
-  0x142796d5, 0xd160d6e5, 0x141e7037, 0xd16973b3,
-  0x14154b4a, 0xd172124d, 0x140c280e, 0xd17ab2b3,
-  0x14030684, 0xd18354e4, 0x13f9e6ad, 0xd18bf8e0,
-  0x13f0c887, 0xd1949ea6, 0x13e7ac15, 0xd19d4636,
-  0x13de9156, 0xd1a5ef90, 0x13d5784a, 0xd1ae9ab4,
-  0x13cc60f2, 0xd1b747a0, 0x13c34b4f, 0xd1bff656,
-  0x13ba3760, 0xd1c8a6d4, 0x13b12526, 0xd1d1591a,
-  0x13a814a2, 0xd1da0d28, 0x139f05d3, 0xd1e2c2fd,
-  0x1395f8ba, 0xd1eb7a9a, 0x138ced57, 0xd1f433fd,
-  0x1383e3ab, 0xd1fcef27, 0x137adbb6, 0xd205ac17,
-  0x1371d579, 0xd20e6acc, 0x1368d0f3, 0xd2172b48,
-  0x135fce26, 0xd21fed88, 0x1356cd11, 0xd228b18d,
-  0x134dcdb4, 0xd2317756, 0x1344d011, 0xd23a3ee4,
-  0x133bd427, 0xd2430835, 0x1332d9f7, 0xd24bd34a,
-  0x1329e181, 0xd254a021, 0x1320eac6, 0xd25d6ebc,
-  0x1317f5c6, 0xd2663f19, 0x130f0280, 0xd26f1138,
-  0x130610f7, 0xd277e518, 0x12fd2129, 0xd280babb,
-  0x12f43318, 0xd289921e, 0x12eb46c3, 0xd2926b41,
-  0x12e25c2b, 0xd29b4626, 0x12d97350, 0xd2a422ca,
-  0x12d08c33, 0xd2ad012e, 0x12c7a6d4, 0xd2b5e151,
-  0x12bec333, 0xd2bec333, 0x12b5e151, 0xd2c7a6d4,
-  0x12ad012e, 0xd2d08c33, 0x12a422ca, 0xd2d97350,
-  0x129b4626, 0xd2e25c2b, 0x12926b41, 0xd2eb46c3,
-  0x1289921e, 0xd2f43318, 0x1280babb, 0xd2fd2129,
-  0x1277e518, 0xd30610f7, 0x126f1138, 0xd30f0280,
-  0x12663f19, 0xd317f5c6, 0x125d6ebc, 0xd320eac6,
-  0x1254a021, 0xd329e181, 0x124bd34a, 0xd332d9f7,
-  0x12430835, 0xd33bd427, 0x123a3ee4, 0xd344d011,
-  0x12317756, 0xd34dcdb4, 0x1228b18d, 0xd356cd11,
-  0x121fed88, 0xd35fce26, 0x12172b48, 0xd368d0f3,
-  0x120e6acc, 0xd371d579, 0x1205ac17, 0xd37adbb6,
-  0x11fcef27, 0xd383e3ab, 0x11f433fd, 0xd38ced57,
-  0x11eb7a9a, 0xd395f8ba, 0x11e2c2fd, 0xd39f05d3,
-  0x11da0d28, 0xd3a814a2, 0x11d1591a, 0xd3b12526,
-  0x11c8a6d4, 0xd3ba3760, 0x11bff656, 0xd3c34b4f,
-  0x11b747a0, 0xd3cc60f2, 0x11ae9ab4, 0xd3d5784a,
-  0x11a5ef90, 0xd3de9156, 0x119d4636, 0xd3e7ac15,
-  0x11949ea6, 0xd3f0c887, 0x118bf8e0, 0xd3f9e6ad,
-  0x118354e4, 0xd4030684, 0x117ab2b3, 0xd40c280e,
-  0x1172124d, 0xd4154b4a, 0x116973b3, 0xd41e7037,
-  0x1160d6e5, 0xd42796d5, 0x11583be2, 0xd430bf24,
-  0x114fa2ad, 0xd439e923, 0x11470b44, 0xd44314d3,
-  0x113e75a8, 0xd44c4232, 0x1135e1d9, 0xd4557140,
-  0x112d4fd9, 0xd45ea1fd, 0x1124bfa6, 0xd467d469,
-  0x111c3142, 0xd4710883, 0x1113a4ad, 0xd47a3e4b,
-  0x110b19e7, 0xd48375c1, 0x110290f0, 0xd48caee4,
-  0x10fa09c9, 0xd495e9b3, 0x10f18472, 0xd49f2630,
-  0x10e900ec, 0xd4a86458, 0x10e07f36, 0xd4b1a42c,
-  0x10d7ff51, 0xd4bae5ab, 0x10cf813e, 0xd4c428d6,
-  0x10c704fd, 0xd4cd6dab, 0x10be8a8d, 0xd4d6b42b,
-  0x10b611f1, 0xd4dffc54, 0x10ad9b26, 0xd4e94627,
-  0x10a5262f, 0xd4f291a4, 0x109cb30b, 0xd4fbdec9,
-  0x109441bb, 0xd5052d97, 0x108bd23f, 0xd50e7e0d,
-  0x10836497, 0xd517d02b, 0x107af8c4, 0xd52123f0,
-  0x10728ec6, 0xd52a795d, 0x106a269d, 0xd533d070,
-  0x1061c04a, 0xd53d292a, 0x10595bcd, 0xd5468389,
-  0x1050f926, 0xd54fdf8f, 0x10489856, 0xd5593d3a,
-  0x1040395d, 0xd5629c89, 0x1037dc3b, 0xd56bfd7d,
-  0x102f80f1, 0xd5756016, 0x1027277e, 0xd57ec452,
-  0x101ecfe4, 0xd5882a32, 0x10167a22, 0xd59191b5,
-  0x100e2639, 0xd59afadb, 0x1005d42a, 0xd5a465a3,
-  0xffd83f4, 0xd5add20d, 0xff53597, 0xd5b74019,
-  0xfece915, 0xd5c0afc6, 0xfe49e6d, 0xd5ca2115,
-  0xfdc55a1, 0xd5d39403, 0xfd40eaf, 0xd5dd0892,
-  0xfcbc999, 0xd5e67ec1, 0xfc3865e, 0xd5eff690,
-  0xfbb4500, 0xd5f96ffd, 0xfb3057d, 0xd602eb0a,
-  0xfaac7d8, 0xd60c67b4, 0xfa28c10, 0xd615e5fd,
-  0xf9a5225, 0xd61f65e4, 0xf921a17, 0xd628e767,
-  0xf89e3e8, 0xd6326a88, 0xf81af97, 0xd63bef46,
-  0xf797d24, 0xd645759f, 0xf714c91, 0xd64efd94,
-  0xf691ddd, 0xd6588725, 0xf60f108, 0xd6621251,
-  0xf58c613, 0xd66b9f18, 0xf509cfe, 0xd6752d79,
-  0xf4875ca, 0xd67ebd74, 0xf405077, 0xd6884f09,
-  0xf382d05, 0xd691e237, 0xf300b74, 0xd69b76fe,
-  0xf27ebc5, 0xd6a50d5d, 0xf1fcdf8, 0xd6aea555,
-  0xf17b20d, 0xd6b83ee4, 0xf0f9805, 0xd6c1da0b,
-  0xf077fe1, 0xd6cb76c9, 0xeff699f, 0xd6d5151d,
-  0xef75541, 0xd6deb508, 0xeef42c7, 0xd6e85689,
-  0xee73231, 0xd6f1f99f, 0xedf2380, 0xd6fb9e4b,
-  0xed716b4, 0xd705448b, 0xecf0bcd, 0xd70eec60,
-  0xec702cb, 0xd71895c9, 0xebefbb0, 0xd72240c5,
-  0xeb6f67a, 0xd72bed55, 0xeaef32b, 0xd7359b78,
-  0xea6f1c2, 0xd73f4b2e, 0xe9ef241, 0xd748fc75,
-  0xe96f4a7, 0xd752af4f, 0xe8ef8f4, 0xd75c63ba,
-  0xe86ff2a, 0xd76619b6, 0xe7f0748, 0xd76fd143,
-  0xe77114e, 0xd7798a60, 0xe6f1d3d, 0xd783450d,
-  0xe672b16, 0xd78d014a, 0xe5f3ad8, 0xd796bf16,
-  0xe574c84, 0xd7a07e70, 0xe4f6019, 0xd7aa3f5a,
-  0xe47759a, 0xd7b401d1, 0xe3f8d05, 0xd7bdc5d6,
-  0xe37a65b, 0xd7c78b68, 0xe2fc19c, 0xd7d15288,
-  0xe27dec9, 0xd7db1b34, 0xe1ffde2, 0xd7e4e56c,
-  0xe181ee8, 0xd7eeb130, 0xe1041d9, 0xd7f87e7f,
-  0xe0866b8, 0xd8024d59, 0xe008d84, 0xd80c1dbf,
-  0xdf8b63d, 0xd815efae, 0xdf0e0e4, 0xd81fc328,
-  0xde90d79, 0xd829982b, 0xde13bfd, 0xd8336eb7,
-  0xdd96c6f, 0xd83d46cc, 0xdd19ed0, 0xd8472069,
-  0xdc9d320, 0xd850fb8e, 0xdc20960, 0xd85ad83c,
-  0xdba4190, 0xd864b670, 0xdb27bb0, 0xd86e962b,
-  0xdaab7c0, 0xd878776d, 0xda2f5c2, 0xd8825a35,
-  0xd9b35b4, 0xd88c3e83, 0xd937798, 0xd8962456,
-  0xd8bbb6d, 0xd8a00bae, 0xd840134, 0xd8a9f48a,
-  0xd7c48ee, 0xd8b3deeb, 0xd74929a, 0xd8bdcad0,
-  0xd6cde39, 0xd8c7b838, 0xd652bcb, 0xd8d1a724,
-  0xd5d7b50, 0xd8db9792, 0xd55ccca, 0xd8e58982,
-  0xd4e2037, 0xd8ef7cf4, 0xd467599, 0xd8f971e8,
-  0xd3eccef, 0xd903685d, 0xd37263a, 0xd90d6053,
-  0xd2f817b, 0xd91759c9, 0xd27deb0, 0xd92154bf,
-  0xd203ddc, 0xd92b5135, 0xd189efe, 0xd9354f2a,
-  0xd110216, 0xd93f4e9e, 0xd096725, 0xd9494f90,
-  0xd01ce2b, 0xd9535201, 0xcfa3729, 0xd95d55ef,
-  0xcf2a21d, 0xd9675b5a, 0xceb0f0a, 0xd9716243,
-  0xce37def, 0xd97b6aa8, 0xcdbeecc, 0xd9857489,
-  0xcd461a2, 0xd98f7fe6, 0xcccd671, 0xd9998cbe,
-  0xcc54d3a, 0xd9a39b11, 0xcbdc5fc, 0xd9adaadf,
-  0xcb640b8, 0xd9b7bc27, 0xcaebd6e, 0xd9c1cee9,
-  0xca73c1e, 0xd9cbe325, 0xc9fbcca, 0xd9d5f8d9,
-  0xc983f70, 0xd9e01006, 0xc90c412, 0xd9ea28ac,
-  0xc894aaf, 0xd9f442c9, 0xc81d349, 0xd9fe5e5e,
-  0xc7a5dde, 0xda087b69, 0xc72ea70, 0xda1299ec,
-  0xc6b78ff, 0xda1cb9e5, 0xc64098b, 0xda26db54,
-  0xc5c9c14, 0xda30fe38, 0xc55309b, 0xda3b2292,
-  0xc4dc720, 0xda454860, 0xc465fa3, 0xda4f6fa3,
-  0xc3efa25, 0xda599859, 0xc3796a5, 0xda63c284,
-  0xc303524, 0xda6dee21, 0xc28d5a3, 0xda781b31,
-  0xc217822, 0xda8249b4, 0xc1a1ca0, 0xda8c79a9,
-  0xc12c31f, 0xda96ab0f, 0xc0b6b9e, 0xdaa0dde7,
-  0xc04161e, 0xdaab122f, 0xbfcc29f, 0xdab547e8,
-  0xbf57121, 0xdabf7f11, 0xbee21a5, 0xdac9b7a9,
-  0xbe6d42b, 0xdad3f1b1, 0xbdf88b3, 0xdade2d28,
-  0xbd83f3d, 0xdae86a0d, 0xbd0f7ca, 0xdaf2a860,
-  0xbc9b25a, 0xdafce821, 0xbc26eee, 0xdb072950,
-  0xbbb2d85, 0xdb116beb, 0xbb3ee20, 0xdb1baff2,
-  0xbacb0bf, 0xdb25f566, 0xba57563, 0xdb303c46,
-  0xb9e3c0b, 0xdb3a8491, 0xb9704b9, 0xdb44ce46,
-  0xb8fcf6b, 0xdb4f1967, 0xb889c23, 0xdb5965f1,
-  0xb816ae1, 0xdb63b3e5, 0xb7a3ba5, 0xdb6e0342,
-  0xb730e70, 0xdb785409, 0xb6be341, 0xdb82a638,
-  0xb64ba19, 0xdb8cf9cf, 0xb5d92f8, 0xdb974ece,
-  0xb566ddf, 0xdba1a534, 0xb4f4acd, 0xdbabfd01,
-  0xb4829c4, 0xdbb65634, 0xb410ac3, 0xdbc0b0ce,
-  0xb39edca, 0xdbcb0cce, 0xb32d2da, 0xdbd56a32,
-  0xb2bb9f4, 0xdbdfc8fc, 0xb24a316, 0xdbea292b,
-  0xb1d8e43, 0xdbf48abd, 0xb167b79, 0xdbfeedb3,
-  0xb0f6aba, 0xdc09520d, 0xb085c05, 0xdc13b7c9,
-  0xb014f5b, 0xdc1e1ee9, 0xafa44bc, 0xdc28876a,
-  0xaf33c28, 0xdc32f14d, 0xaec35a0, 0xdc3d5c91,
-  0xae53123, 0xdc47c936, 0xade2eb3, 0xdc52373c,
-  0xad72e4f, 0xdc5ca6a2, 0xad02ff8, 0xdc671768,
-  0xac933ae, 0xdc71898d, 0xac23971, 0xdc7bfd11,
-  0xabb4141, 0xdc8671f3, 0xab44b1f, 0xdc90e834,
-  0xaad570c, 0xdc9b5fd2, 0xaa66506, 0xdca5d8cd,
-  0xa9f750f, 0xdcb05326, 0xa988727, 0xdcbacedb,
-  0xa919b4e, 0xdcc54bec, 0xa8ab184, 0xdccfca59,
-  0xa83c9ca, 0xdcda4a21, 0xa7ce420, 0xdce4cb44,
-  0xa760086, 0xdcef4dc2, 0xa6f1efc, 0xdcf9d199,
-  0xa683f83, 0xdd0456ca, 0xa61621b, 0xdd0edd55,
-  0xa5a86c4, 0xdd196538, 0xa53ad7e, 0xdd23ee74,
-  0xa4cd64b, 0xdd2e7908, 0xa460129, 0xdd3904f4,
-  0xa3f2e19, 0xdd439236, 0xa385d1d, 0xdd4e20d0,
-  0xa318e32, 0xdd58b0c0, 0xa2ac15b, 0xdd634206,
-  0xa23f698, 0xdd6dd4a2, 0xa1d2de7, 0xdd786892,
-  0xa16674b, 0xdd82fdd8, 0xa0fa2c3, 0xdd8d9472,
-  0xa08e04f, 0xdd982c60, 0xa021fef, 0xdda2c5a2,
-  0x9fb61a5, 0xddad6036, 0x9f4a570, 0xddb7fc1e,
-  0x9edeb50, 0xddc29958, 0x9e73346, 0xddcd37e4,
-  0x9e07d51, 0xddd7d7c1, 0x9d9c973, 0xdde278ef,
-  0x9d317ab, 0xdded1b6e, 0x9cc67fa, 0xddf7bf3e,
-  0x9c5ba60, 0xde02645d, 0x9bf0edd, 0xde0d0acc,
-  0x9b86572, 0xde17b28a, 0x9b1be1e, 0xde225b96,
-  0x9ab18e3, 0xde2d05f1, 0x9a475bf, 0xde37b199,
-  0x99dd4b4, 0xde425e8f, 0x99735c2, 0xde4d0cd2,
-  0x99098e9, 0xde57bc62, 0x989fe29, 0xde626d3e,
-  0x9836582, 0xde6d1f65, 0x97ccef5, 0xde77d2d8,
-  0x9763a83, 0xde828796, 0x96fa82a, 0xde8d3d9e,
-  0x96917ec, 0xde97f4f1, 0x96289c9, 0xdea2ad8d,
-  0x95bfdc1, 0xdead6773, 0x95573d4, 0xdeb822a1,
-  0x94eec03, 0xdec2df18, 0x948664d, 0xdecd9cd7,
-  0x941e2b4, 0xded85bdd, 0x93b6137, 0xdee31c2b,
-  0x934e1d6, 0xdeedddc0, 0x92e6492, 0xdef8a09b,
-  0x927e96b, 0xdf0364bc, 0x9217062, 0xdf0e2a22,
-  0x91af976, 0xdf18f0ce, 0x91484a8, 0xdf23b8be,
-  0x90e11f7, 0xdf2e81f3, 0x907a166, 0xdf394c6b,
-  0x90132f2, 0xdf441828, 0x8fac69e, 0xdf4ee527,
-  0x8f45c68, 0xdf59b369, 0x8edf452, 0xdf6482ed,
-  0x8e78e5b, 0xdf6f53b3, 0x8e12a84, 0xdf7a25ba,
-  0x8dac8cd, 0xdf84f902, 0x8d46936, 0xdf8fcd8b,
-  0x8ce0bc0, 0xdf9aa354, 0x8c7b06b, 0xdfa57a5d,
-  0x8c15736, 0xdfb052a5, 0x8bb0023, 0xdfbb2c2c,
-  0x8b4ab32, 0xdfc606f1, 0x8ae5862, 0xdfd0e2f5,
-  0x8a807b4, 0xdfdbc036, 0x8a1b928, 0xdfe69eb4,
-  0x89b6cbf, 0xdff17e70, 0x8952278, 0xdffc5f67,
-  0x88eda54, 0xe007419b, 0x8889454, 0xe012250a,
-  0x8825077, 0xe01d09b4, 0x87c0ebd, 0xe027ef99,
-  0x875cf28, 0xe032d6b8, 0x86f91b7, 0xe03dbf11,
-  0x869566a, 0xe048a8a4, 0x8631d42, 0xe053936f,
-  0x85ce63e, 0xe05e7f74, 0x856b160, 0xe0696cb0,
-  0x8507ea7, 0xe0745b24, 0x84a4e14, 0xe07f4acf,
-  0x8441fa6, 0xe08a3bb2, 0x83df35f, 0xe0952dcb,
-  0x837c93e, 0xe0a0211a, 0x831a143, 0xe0ab159e,
-  0x82b7b70, 0xe0b60b58, 0x82557c3, 0xe0c10247,
-  0x81f363d, 0xe0cbfa6a, 0x81916df, 0xe0d6f3c1,
-  0x812f9a9, 0xe0e1ee4b, 0x80cde9b, 0xe0ecea09,
-  0x806c5b5, 0xe0f7e6f9, 0x800aef7, 0xe102e51c,
-  0x7fa9a62, 0xe10de470, 0x7f487f6, 0xe118e4f6,
-  0x7ee77b3, 0xe123e6ad, 0x7e8699a, 0xe12ee995,
-  0x7e25daa, 0xe139edac, 0x7dc53e3, 0xe144f2f3,
-  0x7d64c47, 0xe14ff96a, 0x7d046d6, 0xe15b0110,
-  0x7ca438f, 0xe16609e3, 0x7c44272, 0xe17113e5,
-  0x7be4381, 0xe17c1f15, 0x7b846ba, 0xe1872b72,
-  0x7b24c20, 0xe19238fb, 0x7ac53b1, 0xe19d47b1,
-  0x7a65d6e, 0xe1a85793, 0x7a06957, 0xe1b368a0,
-  0x79a776c, 0xe1be7ad8, 0x79487ae, 0xe1c98e3b,
-  0x78e9a1d, 0xe1d4a2c8, 0x788aeb9, 0xe1dfb87f,
-  0x782c582, 0xe1eacf5f, 0x77cde79, 0xe1f5e768,
-  0x776f99d, 0xe2010099, 0x77116f0, 0xe20c1af3,
-  0x76b3671, 0xe2173674, 0x7655820, 0xe222531c,
-  0x75f7bfe, 0xe22d70eb, 0x759a20a, 0xe2388fe1,
-  0x753ca46, 0xe243affc, 0x74df4b1, 0xe24ed13d,
-  0x748214c, 0xe259f3a3, 0x7425016, 0xe265172e,
-  0x73c8111, 0xe2703bdc, 0x736b43c, 0xe27b61af,
-  0x730e997, 0xe28688a4, 0x72b2123, 0xe291b0bd,
-  0x7255ae0, 0xe29cd9f8, 0x71f96ce, 0xe2a80456,
-  0x719d4ed, 0xe2b32fd4, 0x714153e, 0xe2be5c74,
-  0x70e57c0, 0xe2c98a35, 0x7089c75, 0xe2d4b916,
-  0x702e35c, 0xe2dfe917, 0x6fd2c75, 0xe2eb1a37,
-  0x6f777c1, 0xe2f64c77, 0x6f1c540, 0xe3017fd5,
-  0x6ec14f2, 0xe30cb451, 0x6e666d7, 0xe317e9eb,
-  0x6e0baf0, 0xe32320a2, 0x6db113d, 0xe32e5876,
-  0x6d569be, 0xe3399167, 0x6cfc472, 0xe344cb73,
-  0x6ca215c, 0xe350069b, 0x6c4807a, 0xe35b42df,
-  0x6bee1cd, 0xe366803c, 0x6b94554, 0xe371beb5,
-  0x6b3ab12, 0xe37cfe47, 0x6ae1304, 0xe3883ef2,
-  0x6a87d2d, 0xe39380b6, 0x6a2e98b, 0xe39ec393,
-  0x69d5820, 0xe3aa0788, 0x697c8eb, 0xe3b54c95,
-  0x6923bec, 0xe3c092b9, 0x68cb124, 0xe3cbd9f4,
-  0x6872894, 0xe3d72245, 0x681a23a, 0xe3e26bac,
-  0x67c1e18, 0xe3edb628, 0x6769c2e, 0xe3f901ba,
-  0x6711c7b, 0xe4044e60, 0x66b9f01, 0xe40f9c1a,
-  0x66623be, 0xe41aeae8, 0x660aab5, 0xe4263ac9,
-  0x65b33e4, 0xe4318bbe, 0x655bf4c, 0xe43cddc4,
-  0x6504ced, 0xe44830dd, 0x64adcc7, 0xe4538507,
-  0x6456edb, 0xe45eda43, 0x6400329, 0xe46a308f,
-  0x63a99b1, 0xe47587eb, 0x6353273, 0xe480e057,
-  0x62fcd6f, 0xe48c39d3, 0x62a6aa6, 0xe497945d,
-  0x6250a18, 0xe4a2eff6, 0x61fabc4, 0xe4ae4c9d,
-  0x61a4fac, 0xe4b9aa52, 0x614f5cf, 0xe4c50914,
-  0x60f9e2e, 0xe4d068e2, 0x60a48c9, 0xe4dbc9bd,
-  0x604f5a0, 0xe4e72ba4, 0x5ffa4b3, 0xe4f28e96,
-  0x5fa5603, 0xe4fdf294, 0x5f5098f, 0xe509579b,
-  0x5efbf58, 0xe514bdad, 0x5ea775e, 0xe52024c9,
-  0x5e531a1, 0xe52b8cee, 0x5dfee22, 0xe536f61b,
-  0x5daace1, 0xe5426051, 0x5d56ddd, 0xe54dcb8f,
-  0x5d03118, 0xe55937d5, 0x5caf690, 0xe564a521,
-  0x5c5be47, 0xe5701374, 0x5c0883d, 0xe57b82cd,
-  0x5bb5472, 0xe586f32c, 0x5b622e6, 0xe5926490,
-  0x5b0f399, 0xe59dd6f9, 0x5abc68c, 0xe5a94a67,
-  0x5a69bbe, 0xe5b4bed8, 0x5a17330, 0xe5c0344d,
-  0x59c4ce3, 0xe5cbaac5, 0x59728d5, 0xe5d72240,
-  0x5920708, 0xe5e29abc, 0x58ce77c, 0xe5ee143b,
-  0x587ca31, 0xe5f98ebb, 0x582af26, 0xe6050a3b,
-  0x57d965d, 0xe61086bc, 0x5787fd6, 0xe61c043d,
-  0x5736b90, 0xe62782be, 0x56e598c, 0xe633023e,
-  0x56949ca, 0xe63e82bc, 0x5643c4a, 0xe64a0438,
-  0x55f310d, 0xe65586b3, 0x55a2812, 0xe6610a2a,
-  0x555215a, 0xe66c8e9f, 0x5501ce5, 0xe6781410,
-  0x54b1ab4, 0xe6839a7c, 0x5461ac6, 0xe68f21e5,
-  0x5411d1b, 0xe69aaa48, 0x53c21b4, 0xe6a633a6,
-  0x5372891, 0xe6b1bdff, 0x53231b3, 0xe6bd4951,
-  0x52d3d18, 0xe6c8d59c, 0x5284ac3, 0xe6d462e1,
-  0x5235ab2, 0xe6dff11d, 0x51e6ce6, 0xe6eb8052,
-  0x519815f, 0xe6f7107e, 0x514981d, 0xe702a1a1,
-  0x50fb121, 0xe70e33bb, 0x50acc6b, 0xe719c6cb,
-  0x505e9fb, 0xe7255ad1, 0x50109d0, 0xe730efcc,
-  0x4fc2bec, 0xe73c85bc, 0x4f7504e, 0xe7481ca1,
-  0x4f276f7, 0xe753b479, 0x4ed9fe7, 0xe75f4d45,
-  0x4e8cb1e, 0xe76ae704, 0x4e3f89c, 0xe77681b6,
-  0x4df2862, 0xe7821d59, 0x4da5a6f, 0xe78db9ef,
-  0x4d58ec3, 0xe7995776, 0x4d0c560, 0xe7a4f5ed,
-  0x4cbfe45, 0xe7b09555, 0x4c73972, 0xe7bc35ad,
-  0x4c276e8, 0xe7c7d6f4, 0x4bdb6a6, 0xe7d3792b,
-  0x4b8f8ad, 0xe7df1c50, 0x4b43cfd, 0xe7eac063,
-  0x4af8397, 0xe7f66564, 0x4aacc7a, 0xe8020b52,
-  0x4a617a6, 0xe80db22d, 0x4a1651c, 0xe81959f4,
-  0x49cb4dd, 0xe82502a7, 0x49806e7, 0xe830ac45,
-  0x4935b3c, 0xe83c56cf, 0x48eb1db, 0xe8480243,
-  0x48a0ac4, 0xe853aea1, 0x48565f9, 0xe85f5be9,
-  0x480c379, 0xe86b0a1a, 0x47c2344, 0xe876b934,
-  0x477855a, 0xe8826936, 0x472e9bc, 0xe88e1a20,
-  0x46e5069, 0xe899cbf1, 0x469b963, 0xe8a57ea9,
-  0x46524a9, 0xe8b13248, 0x460923b, 0xe8bce6cd,
-  0x45c0219, 0xe8c89c37, 0x4577444, 0xe8d45286,
-  0x452e8bc, 0xe8e009ba, 0x44e5f80, 0xe8ebc1d3,
-  0x449d892, 0xe8f77acf, 0x44553f2, 0xe90334af,
-  0x440d19e, 0xe90eef71, 0x43c5199, 0xe91aab16,
-  0x437d3e1, 0xe926679c, 0x4335877, 0xe9322505,
-  0x42edf5c, 0xe93de34e, 0x42a688f, 0xe949a278,
-  0x425f410, 0xe9556282, 0x42181e0, 0xe961236c,
-  0x41d11ff, 0xe96ce535, 0x418a46d, 0xe978a7dd,
-  0x414392b, 0xe9846b63, 0x40fd037, 0xe9902fc7,
-  0x40b6994, 0xe99bf509, 0x4070540, 0xe9a7bb28,
-  0x402a33c, 0xe9b38223, 0x3fe4388, 0xe9bf49fa,
-  0x3f9e624, 0xe9cb12ad, 0x3f58b10, 0xe9d6dc3b,
-  0x3f1324e, 0xe9e2a6a3, 0x3ecdbdc, 0xe9ee71e6,
-  0x3e887bb, 0xe9fa3e03, 0x3e435ea, 0xea060af9,
-  0x3dfe66c, 0xea11d8c8, 0x3db993e, 0xea1da770,
-  0x3d74e62, 0xea2976ef, 0x3d305d8, 0xea354746,
-  0x3cebfa0, 0xea411874, 0x3ca7bba, 0xea4cea79,
-  0x3c63a26, 0xea58bd54, 0x3c1fae5, 0xea649105,
-  0x3bdbdf6, 0xea70658a, 0x3b9835a, 0xea7c3ae5,
-  0x3b54b11, 0xea881114, 0x3b1151b, 0xea93e817,
-  0x3ace178, 0xea9fbfed, 0x3a8b028, 0xeaab9896,
-  0x3a4812c, 0xeab77212, 0x3a05484, 0xeac34c60,
-  0x39c2a2f, 0xeacf277f, 0x398022f, 0xeadb0370,
-  0x393dc82, 0xeae6e031, 0x38fb92a, 0xeaf2bdc3,
-  0x38b9827, 0xeafe9c24, 0x3877978, 0xeb0a7b54,
-  0x3835d1e, 0xeb165b54, 0x37f4319, 0xeb223c22,
-  0x37b2b6a, 0xeb2e1dbe, 0x377160f, 0xeb3a0027,
-  0x373030a, 0xeb45e35d, 0x36ef25b, 0xeb51c760,
-  0x36ae401, 0xeb5dac2f, 0x366d7fd, 0xeb6991ca,
-  0x362ce50, 0xeb75782f, 0x35ec6f8, 0xeb815f60,
-  0x35ac1f7, 0xeb8d475b, 0x356bf4d, 0xeb99301f,
-  0x352bef9, 0xeba519ad, 0x34ec0fc, 0xebb10404,
-  0x34ac556, 0xebbcef23, 0x346cc07, 0xebc8db0b,
-  0x342d510, 0xebd4c7ba, 0x33ee070, 0xebe0b52f,
-  0x33aee27, 0xebeca36c, 0x336fe37, 0xebf8926f,
-  0x333109e, 0xec048237, 0x32f255e, 0xec1072c4,
-  0x32b3c75, 0xec1c6417, 0x32755e5, 0xec28562d,
-  0x32371ae, 0xec344908, 0x31f8fcf, 0xec403ca5,
-  0x31bb049, 0xec4c3106, 0x317d31c, 0xec582629,
-  0x313f848, 0xec641c0e, 0x3101fce, 0xec7012b5,
-  0x30c49ad, 0xec7c0a1d, 0x30875e5, 0xec880245,
-  0x304a477, 0xec93fb2e, 0x300d563, 0xec9ff4d6,
-  0x2fd08a9, 0xecabef3d, 0x2f93e4a, 0xecb7ea63,
-  0x2f57644, 0xecc3e648, 0x2f1b099, 0xeccfe2ea,
-  0x2eded49, 0xecdbe04a, 0x2ea2c53, 0xece7de66,
-  0x2e66db8, 0xecf3dd3f, 0x2e2b178, 0xecffdcd4,
-  0x2def794, 0xed0bdd25, 0x2db400a, 0xed17de31,
-  0x2d78add, 0xed23dff7, 0x2d3d80a, 0xed2fe277,
-  0x2d02794, 0xed3be5b1, 0x2cc7979, 0xed47e9a5,
-  0x2c8cdbb, 0xed53ee51, 0x2c52459, 0xed5ff3b5,
-  0x2c17d52, 0xed6bf9d1, 0x2bdd8a9, 0xed7800a5,
-  0x2ba365c, 0xed84082f, 0x2b6966c, 0xed901070,
-  0x2b2f8d8, 0xed9c1967, 0x2af5da2, 0xeda82313,
-  0x2abc4c9, 0xedb42d74, 0x2a82e4d, 0xedc0388a,
-  0x2a49a2e, 0xedcc4454, 0x2a1086d, 0xedd850d2,
-  0x29d790a, 0xede45e03, 0x299ec05, 0xedf06be6,
-  0x296615d, 0xedfc7a7c, 0x292d914, 0xee0889c4,
-  0x28f5329, 0xee1499bd, 0x28bcf9c, 0xee20aa67,
-  0x2884e6e, 0xee2cbbc1, 0x284cf9f, 0xee38cdcb,
-  0x281532e, 0xee44e084, 0x27dd91c, 0xee50f3ed,
-  0x27a616a, 0xee5d0804, 0x276ec16, 0xee691cc9,
-  0x2737922, 0xee75323c, 0x270088e, 0xee81485c,
-  0x26c9a58, 0xee8d5f29, 0x2692e83, 0xee9976a1,
-  0x265c50e, 0xeea58ec6, 0x2625df8, 0xeeb1a796,
-  0x25ef943, 0xeebdc110, 0x25b96ee, 0xeec9db35,
-  0x25836f9, 0xeed5f604, 0x254d965, 0xeee2117c,
-  0x2517e31, 0xeeee2d9d, 0x24e255e, 0xeefa4a67,
-  0x24aceed, 0xef0667d9, 0x2477adc, 0xef1285f2,
-  0x244292c, 0xef1ea4b2, 0x240d9de, 0xef2ac419,
-  0x23d8cf1, 0xef36e426, 0x23a4265, 0xef4304d8,
-  0x236fa3b, 0xef4f2630, 0x233b473, 0xef5b482d,
-  0x230710d, 0xef676ace, 0x22d3009, 0xef738e12,
-  0x229f167, 0xef7fb1fa, 0x226b528, 0xef8bd685,
-  0x2237b4b, 0xef97fbb2, 0x22043d0, 0xefa42181,
-  0x21d0eb8, 0xefb047f2, 0x219dc03, 0xefbc6f03,
-  0x216abb1, 0xefc896b5, 0x2137dc2, 0xefd4bf08,
-  0x2105236, 0xefe0e7f9, 0x20d290d, 0xefed118a,
-  0x20a0248, 0xeff93bba, 0x206dde6, 0xf0056687,
-  0x203bbe8, 0xf01191f3, 0x2009c4e, 0xf01dbdfb,
-  0x1fd7f17, 0xf029eaa1, 0x1fa6445, 0xf03617e2,
-  0x1f74bd6, 0xf04245c0, 0x1f435cc, 0xf04e7438,
-  0x1f12227, 0xf05aa34c, 0x1ee10e5, 0xf066d2fa,
-  0x1eb0209, 0xf0730342, 0x1e7f591, 0xf07f3424,
-  0x1e4eb7e, 0xf08b659f, 0x1e1e3d0, 0xf09797b2,
-  0x1dede87, 0xf0a3ca5d, 0x1dbdba3, 0xf0affda0,
-  0x1d8db25, 0xf0bc317a, 0x1d5dd0c, 0xf0c865ea,
-  0x1d2e158, 0xf0d49af1, 0x1cfe80a, 0xf0e0d08d,
-  0x1ccf122, 0xf0ed06bf, 0x1c9fca0, 0xf0f93d86,
-  0x1c70a84, 0xf10574e0, 0x1c41ace, 0xf111accf,
-  0x1c12d7e, 0xf11de551, 0x1be4294, 0xf12a1e66,
-  0x1bb5a11, 0xf136580d, 0x1b873f5, 0xf1429247,
-  0x1b5903f, 0xf14ecd11, 0x1b2aef0, 0xf15b086d,
-  0x1afd007, 0xf1674459, 0x1acf386, 0xf17380d6,
-  0x1aa196c, 0xf17fbde2, 0x1a741b9, 0xf18bfb7d,
-  0x1a46c6e, 0xf19839a6, 0x1a1998a, 0xf1a4785e,
-  0x19ec90d, 0xf1b0b7a4, 0x19bfaf9, 0xf1bcf777,
-  0x1992f4c, 0xf1c937d6, 0x1966606, 0xf1d578c2,
-  0x1939f29, 0xf1e1ba3a, 0x190dab4, 0xf1edfc3d,
-  0x18e18a7, 0xf1fa3ecb, 0x18b5903, 0xf20681e3,
-  0x1889bc6, 0xf212c585, 0x185e0f3, 0xf21f09b1,
-  0x1832888, 0xf22b4e66, 0x1807285, 0xf23793a3,
-  0x17dbeec, 0xf243d968, 0x17b0dbb, 0xf2501fb5,
-  0x1785ef4, 0xf25c6688, 0x175b296, 0xf268ade3,
-  0x17308a1, 0xf274f5c3, 0x1706115, 0xf2813e2a,
-  0x16dbbf3, 0xf28d8715, 0x16b193a, 0xf299d085,
-  0x16878eb, 0xf2a61a7a, 0x165db05, 0xf2b264f2,
-  0x1633f8a, 0xf2beafed, 0x160a678, 0xf2cafb6b,
-  0x15e0fd1, 0xf2d7476c, 0x15b7b94, 0xf2e393ef,
-  0x158e9c1, 0xf2efe0f2, 0x1565a58, 0xf2fc2e77,
-  0x153cd5a, 0xf3087c7d, 0x15142c6, 0xf314cb02,
-  0x14eba9d, 0xf3211a07, 0x14c34df, 0xf32d698a,
-  0x149b18b, 0xf339b98d, 0x14730a3, 0xf3460a0d,
-  0x144b225, 0xf3525b0b, 0x1423613, 0xf35eac86,
-  0x13fbc6c, 0xf36afe7e, 0x13d4530, 0xf37750f2,
-  0x13ad060, 0xf383a3e2, 0x1385dfb, 0xf38ff74d,
-  0x135ee02, 0xf39c4b32, 0x1338075, 0xf3a89f92,
-  0x1311553, 0xf3b4f46c, 0x12eac9d, 0xf3c149bf,
-  0x12c4653, 0xf3cd9f8b, 0x129e276, 0xf3d9f5cf,
-  0x1278104, 0xf3e64c8c, 0x12521ff, 0xf3f2a3bf,
-  0x122c566, 0xf3fefb6a, 0x1206b39, 0xf40b538b,
-  0x11e1379, 0xf417ac22, 0x11bbe26, 0xf424052f,
-  0x1196b3f, 0xf4305eb0, 0x1171ac6, 0xf43cb8a7,
-  0x114ccb9, 0xf4491311, 0x1128119, 0xf4556def,
-  0x11037e6, 0xf461c940, 0x10df120, 0xf46e2504,
-  0x10bacc8, 0xf47a8139, 0x1096add, 0xf486dde1,
-  0x1072b5f, 0xf4933afa, 0x104ee4f, 0xf49f9884,
-  0x102b3ac, 0xf4abf67e, 0x1007b77, 0xf4b854e7,
-  0xfe45b0, 0xf4c4b3c0, 0xfc1257, 0xf4d11308,
-  0xf9e16b, 0xf4dd72be, 0xf7b2ee, 0xf4e9d2e3,
-  0xf586df, 0xf4f63374, 0xf35d3e, 0xf5029473,
-  0xf1360b, 0xf50ef5de, 0xef1147, 0xf51b57b5,
-  0xeceef1, 0xf527b9f7, 0xeacf09, 0xf5341ca5,
-  0xe8b190, 0xf5407fbd, 0xe69686, 0xf54ce33f,
-  0xe47deb, 0xf559472b, 0xe267be, 0xf565ab80,
-  0xe05401, 0xf572103d, 0xde42b2, 0xf57e7563,
-  0xdc33d2, 0xf58adaf0, 0xda2762, 0xf59740e5,
-  0xd81d61, 0xf5a3a740, 0xd615cf, 0xf5b00e02,
-  0xd410ad, 0xf5bc7529, 0xd20dfa, 0xf5c8dcb6,
-  0xd00db6, 0xf5d544a7, 0xce0fe3, 0xf5e1acfd,
-  0xcc147f, 0xf5ee15b7, 0xca1b8a, 0xf5fa7ed4,
-  0xc82506, 0xf606e854, 0xc630f2, 0xf6135237,
-  0xc43f4d, 0xf61fbc7b, 0xc25019, 0xf62c2721,
-  0xc06355, 0xf6389228, 0xbe7901, 0xf644fd8f,
-  0xbc911d, 0xf6516956, 0xbaabaa, 0xf65dd57d,
-  0xb8c8a7, 0xf66a4203, 0xb6e815, 0xf676aee8,
-  0xb509f3, 0xf6831c2b, 0xb32e42, 0xf68f89cb,
-  0xb15502, 0xf69bf7c9, 0xaf7e33, 0xf6a86623,
-  0xada9d4, 0xf6b4d4d9, 0xabd7e6, 0xf6c143ec,
-  0xaa086a, 0xf6cdb359, 0xa83b5e, 0xf6da2321,
-  0xa670c4, 0xf6e69344, 0xa4a89b, 0xf6f303c0,
-  0xa2e2e3, 0xf6ff7496, 0xa11f9d, 0xf70be5c4,
-  0x9f5ec8, 0xf718574b, 0x9da065, 0xf724c92a,
-  0x9be473, 0xf7313b60, 0x9a2af3, 0xf73daded,
-  0x9873e4, 0xf74a20d0, 0x96bf48, 0xf756940a,
-  0x950d1d, 0xf7630799, 0x935d64, 0xf76f7b7d,
-  0x91b01d, 0xf77befb5, 0x900548, 0xf7886442,
-  0x8e5ce5, 0xf794d922, 0x8cb6f5, 0xf7a14e55,
-  0x8b1376, 0xf7adc3db, 0x89726a, 0xf7ba39b3,
-  0x87d3d0, 0xf7c6afdc, 0x8637a9, 0xf7d32657,
-  0x849df4, 0xf7df9d22, 0x8306b2, 0xf7ec143e,
-  0x8171e2, 0xf7f88ba9, 0x7fdf85, 0xf8050364,
-  0x7e4f9b, 0xf8117b6d, 0x7cc223, 0xf81df3c5,
-  0x7b371e, 0xf82a6c6a, 0x79ae8c, 0xf836e55d,
-  0x78286e, 0xf8435e9d, 0x76a4c2, 0xf84fd829,
-  0x752389, 0xf85c5201, 0x73a4c3, 0xf868cc24,
-  0x722871, 0xf8754692, 0x70ae92, 0xf881c14b,
-  0x6f3726, 0xf88e3c4d, 0x6dc22e, 0xf89ab799,
-  0x6c4fa8, 0xf8a7332e, 0x6adf97, 0xf8b3af0c,
-  0x6971f9, 0xf8c02b31, 0x6806ce, 0xf8cca79e,
-  0x669e18, 0xf8d92452, 0x6537d4, 0xf8e5a14d,
-  0x63d405, 0xf8f21e8e, 0x6272aa, 0xf8fe9c15,
-  0x6113c2, 0xf90b19e0, 0x5fb74e, 0xf91797f0,
-  0x5e5d4e, 0xf9241645, 0x5d05c3, 0xf93094dd,
-  0x5bb0ab, 0xf93d13b8, 0x5a5e07, 0xf94992d7,
-  0x590dd8, 0xf9561237, 0x57c01d, 0xf96291d9,
-  0x5674d6, 0xf96f11bc, 0x552c03, 0xf97b91e1,
-  0x53e5a5, 0xf9881245, 0x52a1bb, 0xf99492ea,
-  0x516045, 0xf9a113cd, 0x502145, 0xf9ad94f0,
-  0x4ee4b8, 0xf9ba1651, 0x4daaa1, 0xf9c697f0,
-  0x4c72fe, 0xf9d319cc, 0x4b3dcf, 0xf9df9be6,
-  0x4a0b16, 0xf9ec1e3b, 0x48dad1, 0xf9f8a0cd,
-  0x47ad01, 0xfa05239a, 0x4681a6, 0xfa11a6a3,
-  0x4558c0, 0xfa1e29e5, 0x44324f, 0xfa2aad62,
-  0x430e53, 0xfa373119, 0x41eccc, 0xfa43b508,
-  0x40cdba, 0xfa503930, 0x3fb11d, 0xfa5cbd91,
-  0x3e96f6, 0xfa694229, 0x3d7f44, 0xfa75c6f8,
-  0x3c6a07, 0xfa824bfd, 0x3b573f, 0xfa8ed139,
-  0x3a46ed, 0xfa9b56ab, 0x393910, 0xfaa7dc52,
-  0x382da8, 0xfab4622d, 0x3724b6, 0xfac0e83d,
-  0x361e3a, 0xfacd6e81, 0x351a33, 0xfad9f4f8,
-  0x3418a2, 0xfae67ba2, 0x331986, 0xfaf3027e,
-  0x321ce0, 0xfaff898c, 0x3122b0, 0xfb0c10cb,
-  0x302af5, 0xfb18983b, 0x2f35b1, 0xfb251fdc,
-  0x2e42e2, 0xfb31a7ac, 0x2d5289, 0xfb3e2fac,
-  0x2c64a6, 0xfb4ab7db, 0x2b7939, 0xfb574039,
-  0x2a9042, 0xfb63c8c4, 0x29a9c1, 0xfb70517d,
-  0x28c5b6, 0xfb7cda63, 0x27e421, 0xfb896375,
-  0x270502, 0xfb95ecb4, 0x262859, 0xfba2761e,
-  0x254e27, 0xfbaeffb3, 0x24766a, 0xfbbb8973,
-  0x23a124, 0xfbc8135c, 0x22ce54, 0xfbd49d70,
-  0x21fdfb, 0xfbe127ac, 0x213018, 0xfbedb212,
-  0x2064ab, 0xfbfa3c9f, 0x1f9bb5, 0xfc06c754,
-  0x1ed535, 0xfc135231, 0x1e112b, 0xfc1fdd34,
-  0x1d4f99, 0xfc2c685d, 0x1c907c, 0xfc38f3ac,
-  0x1bd3d6, 0xfc457f21, 0x1b19a7, 0xfc520aba,
-  0x1a61ee, 0xfc5e9678, 0x19acac, 0xfc6b2259,
-  0x18f9e1, 0xfc77ae5e, 0x18498c, 0xfc843a85,
-  0x179bae, 0xfc90c6cf, 0x16f047, 0xfc9d533b,
-  0x164757, 0xfca9dfc8, 0x15a0dd, 0xfcb66c77,
-  0x14fcda, 0xfcc2f945, 0x145b4e, 0xfccf8634,
-  0x13bc39, 0xfcdc1342, 0x131f9b, 0xfce8a06f,
-  0x128574, 0xfcf52dbb, 0x11edc3, 0xfd01bb24,
-  0x11588a, 0xfd0e48ab, 0x10c5c7, 0xfd1ad650,
-  0x10357c, 0xfd276410, 0xfa7a8, 0xfd33f1ed,
-  0xf1c4a, 0xfd407fe6, 0xe9364, 0xfd4d0df9,
-  0xe0cf5, 0xfd599c28, 0xd88fd, 0xfd662a70,
-  0xd077c, 0xfd72b8d2, 0xc8872, 0xfd7f474d,
-  0xc0be0, 0xfd8bd5e1, 0xb91c4, 0xfd98648d,
-  0xb1a20, 0xfda4f351, 0xaa4f3, 0xfdb1822c,
-  0xa323d, 0xfdbe111e, 0x9c1ff, 0xfdcaa027,
-  0x95438, 0xfdd72f45, 0x8e8e8, 0xfde3be78,
-  0x8800f, 0xfdf04dc0, 0x819ae, 0xfdfcdd1d,
-  0x7b5c4, 0xfe096c8d, 0x75452, 0xfe15fc11,
-  0x6f556, 0xfe228ba7, 0x698d3, 0xfe2f1b50,
-  0x63ec6, 0xfe3bab0b, 0x5e731, 0xfe483ad8,
-  0x59214, 0xfe54cab5, 0x53f6e, 0xfe615aa3,
-  0x4ef3f, 0xfe6deaa1, 0x4a188, 0xfe7a7aae,
-  0x45648, 0xfe870aca, 0x40d80, 0xfe939af5,
-  0x3c72f, 0xfea02b2e, 0x38356, 0xfeacbb74,
-  0x341f4, 0xfeb94bc8, 0x3030a, 0xfec5dc28,
-  0x2c697, 0xfed26c94, 0x28c9c, 0xfedefd0c,
-  0x25519, 0xfeeb8d8f, 0x2200d, 0xfef81e1d,
-  0x1ed78, 0xff04aeb5, 0x1bd5c, 0xff113f56,
-  0x18fb6, 0xff1dd001, 0x16489, 0xff2a60b4,
-  0x13bd3, 0xff36f170, 0x11594, 0xff438234,
-  0xf1ce, 0xff5012fe, 0xd07e, 0xff5ca3d0,
-  0xb1a7, 0xff6934a8, 0x9547, 0xff75c585,
-  0x7b5f, 0xff825668, 0x63ee, 0xff8ee750,
-  0x4ef5, 0xff9b783c, 0x3c74, 0xffa8092c,
-  0x2c6a, 0xffb49a1f, 0x1ed8, 0xffc12b16,
-  0x13bd, 0xffcdbc0f, 0xb1a, 0xffda4d09,
-  0x4ef, 0xffe6de05, 0x13c, 0xfff36f02,
-  0x0, 0x0, 0x13c, 0xc90fe,
-  0x4ef, 0x1921fb, 0xb1a, 0x25b2f7,
-  0x13bd, 0x3243f1, 0x1ed8, 0x3ed4ea,
-  0x2c6a, 0x4b65e1, 0x3c74, 0x57f6d4,
-  0x4ef5, 0x6487c4, 0x63ee, 0x7118b0,
-  0x7b5f, 0x7da998, 0x9547, 0x8a3a7b,
-  0xb1a7, 0x96cb58, 0xd07e, 0xa35c30,
-  0xf1ce, 0xafed02, 0x11594, 0xbc7dcc,
-  0x13bd3, 0xc90e90, 0x16489, 0xd59f4c,
-  0x18fb6, 0xe22fff, 0x1bd5c, 0xeec0aa,
-  0x1ed78, 0xfb514b, 0x2200d, 0x107e1e3,
-  0x25519, 0x1147271, 0x28c9c, 0x12102f4,
-  0x2c697, 0x12d936c, 0x3030a, 0x13a23d8,
-  0x341f4, 0x146b438, 0x38356, 0x153448c,
-  0x3c72f, 0x15fd4d2, 0x40d80, 0x16c650b,
-  0x45648, 0x178f536, 0x4a188, 0x1858552,
-  0x4ef3f, 0x192155f, 0x53f6e, 0x19ea55d,
-  0x59214, 0x1ab354b, 0x5e731, 0x1b7c528,
-  0x63ec6, 0x1c454f5, 0x698d3, 0x1d0e4b0,
-  0x6f556, 0x1dd7459, 0x75452, 0x1ea03ef,
-  0x7b5c4, 0x1f69373, 0x819ae, 0x20322e3,
-  0x8800f, 0x20fb240, 0x8e8e8, 0x21c4188,
-  0x95438, 0x228d0bb, 0x9c1ff, 0x2355fd9,
-  0xa323d, 0x241eee2, 0xaa4f3, 0x24e7dd4,
-  0xb1a20, 0x25b0caf, 0xb91c4, 0x2679b73,
-  0xc0be0, 0x2742a1f, 0xc8872, 0x280b8b3,
-  0xd077c, 0x28d472e, 0xd88fd, 0x299d590,
-  0xe0cf5, 0x2a663d8, 0xe9364, 0x2b2f207,
-  0xf1c4a, 0x2bf801a, 0xfa7a8, 0x2cc0e13,
-  0x10357c, 0x2d89bf0, 0x10c5c7, 0x2e529b0,
-  0x11588a, 0x2f1b755, 0x11edc3, 0x2fe44dc,
-  0x128574, 0x30ad245, 0x131f9b, 0x3175f91,
-  0x13bc39, 0x323ecbe, 0x145b4e, 0x33079cc,
-  0x14fcda, 0x33d06bb, 0x15a0dd, 0x3499389,
-  0x164757, 0x3562038, 0x16f047, 0x362acc5,
-  0x179bae, 0x36f3931, 0x18498c, 0x37bc57b,
-  0x18f9e1, 0x38851a2, 0x19acac, 0x394dda7,
-  0x1a61ee, 0x3a16988, 0x1b19a7, 0x3adf546,
-  0x1bd3d6, 0x3ba80df, 0x1c907c, 0x3c70c54,
-  0x1d4f99, 0x3d397a3, 0x1e112b, 0x3e022cc,
-  0x1ed535, 0x3ecadcf, 0x1f9bb5, 0x3f938ac,
-  0x2064ab, 0x405c361, 0x213018, 0x4124dee,
-  0x21fdfb, 0x41ed854, 0x22ce54, 0x42b6290,
-  0x23a124, 0x437eca4, 0x24766a, 0x444768d,
-  0x254e27, 0x451004d, 0x262859, 0x45d89e2,
-  0x270502, 0x46a134c, 0x27e421, 0x4769c8b,
-  0x28c5b6, 0x483259d, 0x29a9c1, 0x48fae83,
-  0x2a9042, 0x49c373c, 0x2b7939, 0x4a8bfc7,
-  0x2c64a6, 0x4b54825, 0x2d5289, 0x4c1d054,
-  0x2e42e2, 0x4ce5854, 0x2f35b1, 0x4dae024,
-  0x302af5, 0x4e767c5, 0x3122b0, 0x4f3ef35,
-  0x321ce0, 0x5007674, 0x331986, 0x50cfd82,
-  0x3418a2, 0x519845e, 0x351a33, 0x5260b08,
-  0x361e3a, 0x532917f, 0x3724b6, 0x53f17c3,
-  0x382da8, 0x54b9dd3, 0x393910, 0x55823ae,
-  0x3a46ed, 0x564a955, 0x3b573f, 0x5712ec7,
-  0x3c6a07, 0x57db403, 0x3d7f44, 0x58a3908,
-  0x3e96f6, 0x596bdd7, 0x3fb11d, 0x5a3426f,
-  0x40cdba, 0x5afc6d0, 0x41eccc, 0x5bc4af8,
-  0x430e53, 0x5c8cee7, 0x44324f, 0x5d5529e,
-  0x4558c0, 0x5e1d61b, 0x4681a6, 0x5ee595d,
-  0x47ad01, 0x5fadc66, 0x48dad1, 0x6075f33,
-  0x4a0b16, 0x613e1c5, 0x4b3dcf, 0x620641a,
-  0x4c72fe, 0x62ce634, 0x4daaa1, 0x6396810,
-  0x4ee4b8, 0x645e9af, 0x502145, 0x6526b10,
-  0x516045, 0x65eec33, 0x52a1bb, 0x66b6d16,
-  0x53e5a5, 0x677edbb, 0x552c03, 0x6846e1f,
-  0x5674d6, 0x690ee44, 0x57c01d, 0x69d6e27,
-  0x590dd8, 0x6a9edc9, 0x5a5e07, 0x6b66d29,
-  0x5bb0ab, 0x6c2ec48, 0x5d05c3, 0x6cf6b23,
-  0x5e5d4e, 0x6dbe9bb, 0x5fb74e, 0x6e86810,
-  0x6113c2, 0x6f4e620, 0x6272aa, 0x70163eb,
-  0x63d405, 0x70de172, 0x6537d4, 0x71a5eb3,
-  0x669e18, 0x726dbae, 0x6806ce, 0x7335862,
-  0x6971f9, 0x73fd4cf, 0x6adf97, 0x74c50f4,
-  0x6c4fa8, 0x758ccd2, 0x6dc22e, 0x7654867,
-  0x6f3726, 0x771c3b3, 0x70ae92, 0x77e3eb5,
-  0x722871, 0x78ab96e, 0x73a4c3, 0x79733dc,
-  0x752389, 0x7a3adff, 0x76a4c2, 0x7b027d7,
-  0x78286e, 0x7bca163, 0x79ae8c, 0x7c91aa3,
-  0x7b371e, 0x7d59396, 0x7cc223, 0x7e20c3b,
-  0x7e4f9b, 0x7ee8493, 0x7fdf85, 0x7fafc9c,
-  0x8171e2, 0x8077457, 0x8306b2, 0x813ebc2,
-  0x849df4, 0x82062de, 0x8637a9, 0x82cd9a9,
-  0x87d3d0, 0x8395024, 0x89726a, 0x845c64d,
-  0x8b1376, 0x8523c25, 0x8cb6f5, 0x85eb1ab,
-  0x8e5ce5, 0x86b26de, 0x900548, 0x8779bbe,
-  0x91b01d, 0x884104b, 0x935d64, 0x8908483,
-  0x950d1d, 0x89cf867, 0x96bf48, 0x8a96bf6,
-  0x9873e4, 0x8b5df30, 0x9a2af3, 0x8c25213,
-  0x9be473, 0x8cec4a0, 0x9da065, 0x8db36d6,
-  0x9f5ec8, 0x8e7a8b5, 0xa11f9d, 0x8f41a3c,
-  0xa2e2e3, 0x9008b6a, 0xa4a89b, 0x90cfc40,
-  0xa670c4, 0x9196cbc, 0xa83b5e, 0x925dcdf,
-  0xaa086a, 0x9324ca7, 0xabd7e6, 0x93ebc14,
-  0xada9d4, 0x94b2b27, 0xaf7e33, 0x95799dd,
-  0xb15502, 0x9640837, 0xb32e42, 0x9707635,
-  0xb509f3, 0x97ce3d5, 0xb6e815, 0x9895118,
-  0xb8c8a7, 0x995bdfd, 0xbaabaa, 0x9a22a83,
-  0xbc911d, 0x9ae96aa, 0xbe7901, 0x9bb0271,
-  0xc06355, 0x9c76dd8, 0xc25019, 0x9d3d8df,
-  0xc43f4d, 0x9e04385, 0xc630f2, 0x9ecadc9,
-  0xc82506, 0x9f917ac, 0xca1b8a, 0xa05812c,
-  0xcc147f, 0xa11ea49, 0xce0fe3, 0xa1e5303,
-  0xd00db6, 0xa2abb59, 0xd20dfa, 0xa37234a,
-  0xd410ad, 0xa438ad7, 0xd615cf, 0xa4ff1fe,
-  0xd81d61, 0xa5c58c0, 0xda2762, 0xa68bf1b,
-  0xdc33d2, 0xa752510, 0xde42b2, 0xa818a9d,
-  0xe05401, 0xa8defc3, 0xe267be, 0xa9a5480,
-  0xe47deb, 0xaa6b8d5, 0xe69686, 0xab31cc1,
-  0xe8b190, 0xabf8043, 0xeacf09, 0xacbe35b,
-  0xeceef1, 0xad84609, 0xef1147, 0xae4a84b,
-  0xf1360b, 0xaf10a22, 0xf35d3e, 0xafd6b8d,
-  0xf586df, 0xb09cc8c, 0xf7b2ee, 0xb162d1d,
-  0xf9e16b, 0xb228d42, 0xfc1257, 0xb2eecf8,
-  0xfe45b0, 0xb3b4c40, 0x1007b77, 0xb47ab19,
-  0x102b3ac, 0xb540982, 0x104ee4f, 0xb60677c,
-  0x1072b5f, 0xb6cc506, 0x1096add, 0xb79221f,
-  0x10bacc8, 0xb857ec7, 0x10df120, 0xb91dafc,
-  0x11037e6, 0xb9e36c0, 0x1128119, 0xbaa9211,
-  0x114ccb9, 0xbb6ecef, 0x1171ac6, 0xbc34759,
-  0x1196b3f, 0xbcfa150, 0x11bbe26, 0xbdbfad1,
-  0x11e1379, 0xbe853de, 0x1206b39, 0xbf4ac75,
-  0x122c566, 0xc010496, 0x12521ff, 0xc0d5c41,
-  0x1278104, 0xc19b374, 0x129e276, 0xc260a31,
-  0x12c4653, 0xc326075, 0x12eac9d, 0xc3eb641,
-  0x1311553, 0xc4b0b94, 0x1338075, 0xc57606e,
-  0x135ee02, 0xc63b4ce, 0x1385dfb, 0xc7008b3,
-  0x13ad060, 0xc7c5c1e, 0x13d4530, 0xc88af0e,
-  0x13fbc6c, 0xc950182, 0x1423613, 0xca1537a,
-  0x144b225, 0xcada4f5, 0x14730a3, 0xcb9f5f3,
-  0x149b18b, 0xcc64673, 0x14c34df, 0xcd29676,
-  0x14eba9d, 0xcdee5f9, 0x15142c6, 0xceb34fe,
-  0x153cd5a, 0xcf78383, 0x1565a58, 0xd03d189,
-  0x158e9c1, 0xd101f0e, 0x15b7b94, 0xd1c6c11,
-  0x15e0fd1, 0xd28b894, 0x160a678, 0xd350495,
-  0x1633f8a, 0xd415013, 0x165db05, 0xd4d9b0e,
-  0x16878eb, 0xd59e586, 0x16b193a, 0xd662f7b,
-  0x16dbbf3, 0xd7278eb, 0x1706115, 0xd7ec1d6,
-  0x17308a1, 0xd8b0a3d, 0x175b296, 0xd97521d,
-  0x1785ef4, 0xda39978, 0x17b0dbb, 0xdafe04b,
-  0x17dbeec, 0xdbc2698, 0x1807285, 0xdc86c5d,
-  0x1832888, 0xdd4b19a, 0x185e0f3, 0xde0f64f,
-  0x1889bc6, 0xded3a7b, 0x18b5903, 0xdf97e1d,
-  0x18e18a7, 0xe05c135, 0x190dab4, 0xe1203c3,
-  0x1939f29, 0xe1e45c6, 0x1966606, 0xe2a873e,
-  0x1992f4c, 0xe36c82a, 0x19bfaf9, 0xe430889,
-  0x19ec90d, 0xe4f485c, 0x1a1998a, 0xe5b87a2,
-  0x1a46c6e, 0xe67c65a, 0x1a741b9, 0xe740483,
-  0x1aa196c, 0xe80421e, 0x1acf386, 0xe8c7f2a,
-  0x1afd007, 0xe98bba7, 0x1b2aef0, 0xea4f793,
-  0x1b5903f, 0xeb132ef, 0x1b873f5, 0xebd6db9,
-  0x1bb5a11, 0xec9a7f3, 0x1be4294, 0xed5e19a,
-  0x1c12d7e, 0xee21aaf, 0x1c41ace, 0xeee5331,
-  0x1c70a84, 0xefa8b20, 0x1c9fca0, 0xf06c27a,
-  0x1ccf122, 0xf12f941, 0x1cfe80a, 0xf1f2f73,
-  0x1d2e158, 0xf2b650f, 0x1d5dd0c, 0xf379a16,
-  0x1d8db25, 0xf43ce86, 0x1dbdba3, 0xf500260,
-  0x1dede87, 0xf5c35a3, 0x1e1e3d0, 0xf68684e,
-  0x1e4eb7e, 0xf749a61, 0x1e7f591, 0xf80cbdc,
-  0x1eb0209, 0xf8cfcbe, 0x1ee10e5, 0xf992d06,
-  0x1f12227, 0xfa55cb4, 0x1f435cc, 0xfb18bc8,
-  0x1f74bd6, 0xfbdba40, 0x1fa6445, 0xfc9e81e,
-  0x1fd7f17, 0xfd6155f, 0x2009c4e, 0xfe24205,
-  0x203bbe8, 0xfee6e0d, 0x206dde6, 0xffa9979,
-  0x20a0248, 0x1006c446, 0x20d290d, 0x1012ee76,
-  0x2105236, 0x101f1807, 0x2137dc2, 0x102b40f8,
-  0x216abb1, 0x1037694b, 0x219dc03, 0x104390fd,
-  0x21d0eb8, 0x104fb80e, 0x22043d0, 0x105bde7f,
-  0x2237b4b, 0x1068044e, 0x226b528, 0x1074297b,
-  0x229f167, 0x10804e06, 0x22d3009, 0x108c71ee,
-  0x230710d, 0x10989532, 0x233b473, 0x10a4b7d3,
-  0x236fa3b, 0x10b0d9d0, 0x23a4265, 0x10bcfb28,
-  0x23d8cf1, 0x10c91bda, 0x240d9de, 0x10d53be7,
-  0x244292c, 0x10e15b4e, 0x2477adc, 0x10ed7a0e,
-  0x24aceed, 0x10f99827, 0x24e255e, 0x1105b599,
-  0x2517e31, 0x1111d263, 0x254d965, 0x111dee84,
-  0x25836f9, 0x112a09fc, 0x25b96ee, 0x113624cb,
-  0x25ef943, 0x11423ef0, 0x2625df8, 0x114e586a,
-  0x265c50e, 0x115a713a, 0x2692e83, 0x1166895f,
-  0x26c9a58, 0x1172a0d7, 0x270088e, 0x117eb7a4,
-  0x2737922, 0x118acdc4, 0x276ec16, 0x1196e337,
-  0x27a616a, 0x11a2f7fc, 0x27dd91c, 0x11af0c13,
-  0x281532e, 0x11bb1f7c, 0x284cf9f, 0x11c73235,
-  0x2884e6e, 0x11d3443f, 0x28bcf9c, 0x11df5599,
-  0x28f5329, 0x11eb6643, 0x292d914, 0x11f7763c,
-  0x296615d, 0x12038584, 0x299ec05, 0x120f941a,
-  0x29d790a, 0x121ba1fd, 0x2a1086d, 0x1227af2e,
-  0x2a49a2e, 0x1233bbac, 0x2a82e4d, 0x123fc776,
-  0x2abc4c9, 0x124bd28c, 0x2af5da2, 0x1257dced,
-  0x2b2f8d8, 0x1263e699, 0x2b6966c, 0x126fef90,
-  0x2ba365c, 0x127bf7d1, 0x2bdd8a9, 0x1287ff5b,
-  0x2c17d52, 0x1294062f, 0x2c52459, 0x12a00c4b,
-  0x2c8cdbb, 0x12ac11af, 0x2cc7979, 0x12b8165b,
-  0x2d02794, 0x12c41a4f, 0x2d3d80a, 0x12d01d89,
-  0x2d78add, 0x12dc2009, 0x2db400a, 0x12e821cf,
-  0x2def794, 0x12f422db, 0x2e2b178, 0x1300232c,
-  0x2e66db8, 0x130c22c1, 0x2ea2c53, 0x1318219a,
-  0x2eded49, 0x13241fb6, 0x2f1b099, 0x13301d16,
-  0x2f57644, 0x133c19b8, 0x2f93e4a, 0x1348159d,
-  0x2fd08a9, 0x135410c3, 0x300d563, 0x13600b2a,
-  0x304a477, 0x136c04d2, 0x30875e5, 0x1377fdbb,
-  0x30c49ad, 0x1383f5e3, 0x3101fce, 0x138fed4b,
-  0x313f848, 0x139be3f2, 0x317d31c, 0x13a7d9d7,
-  0x31bb049, 0x13b3cefa, 0x31f8fcf, 0x13bfc35b,
-  0x32371ae, 0x13cbb6f8, 0x32755e5, 0x13d7a9d3,
-  0x32b3c75, 0x13e39be9, 0x32f255e, 0x13ef8d3c,
-  0x333109e, 0x13fb7dc9, 0x336fe37, 0x14076d91,
-  0x33aee27, 0x14135c94, 0x33ee070, 0x141f4ad1,
-  0x342d510, 0x142b3846, 0x346cc07, 0x143724f5,
-  0x34ac556, 0x144310dd, 0x34ec0fc, 0x144efbfc,
-  0x352bef9, 0x145ae653, 0x356bf4d, 0x1466cfe1,
-  0x35ac1f7, 0x1472b8a5, 0x35ec6f8, 0x147ea0a0,
-  0x362ce50, 0x148a87d1, 0x366d7fd, 0x14966e36,
-  0x36ae401, 0x14a253d1, 0x36ef25b, 0x14ae38a0,
-  0x373030a, 0x14ba1ca3, 0x377160f, 0x14c5ffd9,
-  0x37b2b6a, 0x14d1e242, 0x37f4319, 0x14ddc3de,
-  0x3835d1e, 0x14e9a4ac, 0x3877978, 0x14f584ac,
-  0x38b9827, 0x150163dc, 0x38fb92a, 0x150d423d,
-  0x393dc82, 0x15191fcf, 0x398022f, 0x1524fc90,
-  0x39c2a2f, 0x1530d881, 0x3a05484, 0x153cb3a0,
-  0x3a4812c, 0x15488dee, 0x3a8b028, 0x1554676a,
-  0x3ace178, 0x15604013, 0x3b1151b, 0x156c17e9,
-  0x3b54b11, 0x1577eeec, 0x3b9835a, 0x1583c51b,
-  0x3bdbdf6, 0x158f9a76, 0x3c1fae5, 0x159b6efb,
-  0x3c63a26, 0x15a742ac, 0x3ca7bba, 0x15b31587,
-  0x3cebfa0, 0x15bee78c, 0x3d305d8, 0x15cab8ba,
-  0x3d74e62, 0x15d68911, 0x3db993e, 0x15e25890,
-  0x3dfe66c, 0x15ee2738, 0x3e435ea, 0x15f9f507,
-  0x3e887bb, 0x1605c1fd, 0x3ecdbdc, 0x16118e1a,
-  0x3f1324e, 0x161d595d, 0x3f58b10, 0x162923c5,
-  0x3f9e624, 0x1634ed53, 0x3fe4388, 0x1640b606,
-  0x402a33c, 0x164c7ddd, 0x4070540, 0x165844d8,
-  0x40b6994, 0x16640af7, 0x40fd037, 0x166fd039,
-  0x414392b, 0x167b949d, 0x418a46d, 0x16875823,
-  0x41d11ff, 0x16931acb, 0x42181e0, 0x169edc94,
-  0x425f410, 0x16aa9d7e, 0x42a688f, 0x16b65d88,
-  0x42edf5c, 0x16c21cb2, 0x4335877, 0x16cddafb,
-  0x437d3e1, 0x16d99864, 0x43c5199, 0x16e554ea,
-  0x440d19e, 0x16f1108f, 0x44553f2, 0x16fccb51,
-  0x449d892, 0x17088531, 0x44e5f80, 0x17143e2d,
-  0x452e8bc, 0x171ff646, 0x4577444, 0x172bad7a,
-  0x45c0219, 0x173763c9, 0x460923b, 0x17431933,
-  0x46524a9, 0x174ecdb8, 0x469b963, 0x175a8157,
-  0x46e5069, 0x1766340f, 0x472e9bc, 0x1771e5e0,
-  0x477855a, 0x177d96ca, 0x47c2344, 0x178946cc,
-  0x480c379, 0x1794f5e6, 0x48565f9, 0x17a0a417,
-  0x48a0ac4, 0x17ac515f, 0x48eb1db, 0x17b7fdbd,
-  0x4935b3c, 0x17c3a931, 0x49806e7, 0x17cf53bb,
-  0x49cb4dd, 0x17dafd59, 0x4a1651c, 0x17e6a60c,
-  0x4a617a6, 0x17f24dd3, 0x4aacc7a, 0x17fdf4ae,
-  0x4af8397, 0x18099a9c, 0x4b43cfd, 0x18153f9d,
-  0x4b8f8ad, 0x1820e3b0, 0x4bdb6a6, 0x182c86d5,
-  0x4c276e8, 0x1838290c, 0x4c73972, 0x1843ca53,
-  0x4cbfe45, 0x184f6aab, 0x4d0c560, 0x185b0a13,
-  0x4d58ec3, 0x1866a88a, 0x4da5a6f, 0x18724611,
-  0x4df2862, 0x187de2a7, 0x4e3f89c, 0x18897e4a,
-  0x4e8cb1e, 0x189518fc, 0x4ed9fe7, 0x18a0b2bb,
-  0x4f276f7, 0x18ac4b87, 0x4f7504e, 0x18b7e35f,
-  0x4fc2bec, 0x18c37a44, 0x50109d0, 0x18cf1034,
-  0x505e9fb, 0x18daa52f, 0x50acc6b, 0x18e63935,
-  0x50fb121, 0x18f1cc45, 0x514981d, 0x18fd5e5f,
-  0x519815f, 0x1908ef82, 0x51e6ce6, 0x19147fae,
-  0x5235ab2, 0x19200ee3, 0x5284ac3, 0x192b9d1f,
-  0x52d3d18, 0x19372a64, 0x53231b3, 0x1942b6af,
-  0x5372891, 0x194e4201, 0x53c21b4, 0x1959cc5a,
-  0x5411d1b, 0x196555b8, 0x5461ac6, 0x1970de1b,
-  0x54b1ab4, 0x197c6584, 0x5501ce5, 0x1987ebf0,
-  0x555215a, 0x19937161, 0x55a2812, 0x199ef5d6,
-  0x55f310d, 0x19aa794d, 0x5643c4a, 0x19b5fbc8,
-  0x56949ca, 0x19c17d44, 0x56e598c, 0x19ccfdc2,
-  0x5736b90, 0x19d87d42, 0x5787fd6, 0x19e3fbc3,
-  0x57d965d, 0x19ef7944, 0x582af26, 0x19faf5c5,
-  0x587ca31, 0x1a067145, 0x58ce77c, 0x1a11ebc5,
-  0x5920708, 0x1a1d6544, 0x59728d5, 0x1a28ddc0,
-  0x59c4ce3, 0x1a34553b, 0x5a17330, 0x1a3fcbb3,
-  0x5a69bbe, 0x1a4b4128, 0x5abc68c, 0x1a56b599,
-  0x5b0f399, 0x1a622907, 0x5b622e6, 0x1a6d9b70,
-  0x5bb5472, 0x1a790cd4, 0x5c0883d, 0x1a847d33,
-  0x5c5be47, 0x1a8fec8c, 0x5caf690, 0x1a9b5adf,
-  0x5d03118, 0x1aa6c82b, 0x5d56ddd, 0x1ab23471,
-  0x5daace1, 0x1abd9faf, 0x5dfee22, 0x1ac909e5,
-  0x5e531a1, 0x1ad47312, 0x5ea775e, 0x1adfdb37,
-  0x5efbf58, 0x1aeb4253, 0x5f5098f, 0x1af6a865,
-  0x5fa5603, 0x1b020d6c, 0x5ffa4b3, 0x1b0d716a,
-  0x604f5a0, 0x1b18d45c, 0x60a48c9, 0x1b243643,
-  0x60f9e2e, 0x1b2f971e, 0x614f5cf, 0x1b3af6ec,
-  0x61a4fac, 0x1b4655ae, 0x61fabc4, 0x1b51b363,
-  0x6250a18, 0x1b5d100a, 0x62a6aa6, 0x1b686ba3,
-  0x62fcd6f, 0x1b73c62d, 0x6353273, 0x1b7f1fa9,
-  0x63a99b1, 0x1b8a7815, 0x6400329, 0x1b95cf71,
-  0x6456edb, 0x1ba125bd, 0x64adcc7, 0x1bac7af9,
-  0x6504ced, 0x1bb7cf23, 0x655bf4c, 0x1bc3223c,
-  0x65b33e4, 0x1bce7442, 0x660aab5, 0x1bd9c537,
-  0x66623be, 0x1be51518, 0x66b9f01, 0x1bf063e6,
-  0x6711c7b, 0x1bfbb1a0, 0x6769c2e, 0x1c06fe46,
-  0x67c1e18, 0x1c1249d8, 0x681a23a, 0x1c1d9454,
-  0x6872894, 0x1c28ddbb, 0x68cb124, 0x1c34260c,
-  0x6923bec, 0x1c3f6d47, 0x697c8eb, 0x1c4ab36b,
-  0x69d5820, 0x1c55f878, 0x6a2e98b, 0x1c613c6d,
-  0x6a87d2d, 0x1c6c7f4a, 0x6ae1304, 0x1c77c10e,
-  0x6b3ab12, 0x1c8301b9, 0x6b94554, 0x1c8e414b,
-  0x6bee1cd, 0x1c997fc4, 0x6c4807a, 0x1ca4bd21,
-  0x6ca215c, 0x1caff965, 0x6cfc472, 0x1cbb348d,
-  0x6d569be, 0x1cc66e99, 0x6db113d, 0x1cd1a78a,
-  0x6e0baf0, 0x1cdcdf5e, 0x6e666d7, 0x1ce81615,
-  0x6ec14f2, 0x1cf34baf, 0x6f1c540, 0x1cfe802b,
-  0x6f777c1, 0x1d09b389, 0x6fd2c75, 0x1d14e5c9,
-  0x702e35c, 0x1d2016e9, 0x7089c75, 0x1d2b46ea,
-  0x70e57c0, 0x1d3675cb, 0x714153e, 0x1d41a38c,
-  0x719d4ed, 0x1d4cd02c, 0x71f96ce, 0x1d57fbaa,
-  0x7255ae0, 0x1d632608, 0x72b2123, 0x1d6e4f43,
-  0x730e997, 0x1d79775c, 0x736b43c, 0x1d849e51,
-  0x73c8111, 0x1d8fc424, 0x7425016, 0x1d9ae8d2,
-  0x748214c, 0x1da60c5d, 0x74df4b1, 0x1db12ec3,
-  0x753ca46, 0x1dbc5004, 0x759a20a, 0x1dc7701f,
-  0x75f7bfe, 0x1dd28f15, 0x7655820, 0x1dddace4,
-  0x76b3671, 0x1de8c98c, 0x77116f0, 0x1df3e50d,
-  0x776f99d, 0x1dfeff67, 0x77cde79, 0x1e0a1898,
-  0x782c582, 0x1e1530a1, 0x788aeb9, 0x1e204781,
-  0x78e9a1d, 0x1e2b5d38, 0x79487ae, 0x1e3671c5,
-  0x79a776c, 0x1e418528, 0x7a06957, 0x1e4c9760,
-  0x7a65d6e, 0x1e57a86d, 0x7ac53b1, 0x1e62b84f,
-  0x7b24c20, 0x1e6dc705, 0x7b846ba, 0x1e78d48e,
-  0x7be4381, 0x1e83e0eb, 0x7c44272, 0x1e8eec1b,
-  0x7ca438f, 0x1e99f61d, 0x7d046d6, 0x1ea4fef0,
-  0x7d64c47, 0x1eb00696, 0x7dc53e3, 0x1ebb0d0d,
-  0x7e25daa, 0x1ec61254, 0x7e8699a, 0x1ed1166b,
-  0x7ee77b3, 0x1edc1953, 0x7f487f6, 0x1ee71b0a,
-  0x7fa9a62, 0x1ef21b90, 0x800aef7, 0x1efd1ae4,
-  0x806c5b5, 0x1f081907, 0x80cde9b, 0x1f1315f7,
-  0x812f9a9, 0x1f1e11b5, 0x81916df, 0x1f290c3f,
-  0x81f363d, 0x1f340596, 0x82557c3, 0x1f3efdb9,
-  0x82b7b70, 0x1f49f4a8, 0x831a143, 0x1f54ea62,
-  0x837c93e, 0x1f5fdee6, 0x83df35f, 0x1f6ad235,
-  0x8441fa6, 0x1f75c44e, 0x84a4e14, 0x1f80b531,
-  0x8507ea7, 0x1f8ba4dc, 0x856b160, 0x1f969350,
-  0x85ce63e, 0x1fa1808c, 0x8631d42, 0x1fac6c91,
-  0x869566a, 0x1fb7575c, 0x86f91b7, 0x1fc240ef,
-  0x875cf28, 0x1fcd2948, 0x87c0ebd, 0x1fd81067,
-  0x8825077, 0x1fe2f64c, 0x8889454, 0x1feddaf6,
-  0x88eda54, 0x1ff8be65, 0x8952278, 0x2003a099,
-  0x89b6cbf, 0x200e8190, 0x8a1b928, 0x2019614c,
-  0x8a807b4, 0x20243fca, 0x8ae5862, 0x202f1d0b,
-  0x8b4ab32, 0x2039f90f, 0x8bb0023, 0x2044d3d4,
-  0x8c15736, 0x204fad5b, 0x8c7b06b, 0x205a85a3,
-  0x8ce0bc0, 0x20655cac, 0x8d46936, 0x20703275,
-  0x8dac8cd, 0x207b06fe, 0x8e12a84, 0x2085da46,
-  0x8e78e5b, 0x2090ac4d, 0x8edf452, 0x209b7d13,
-  0x8f45c68, 0x20a64c97, 0x8fac69e, 0x20b11ad9,
-  0x90132f2, 0x20bbe7d8, 0x907a166, 0x20c6b395,
-  0x90e11f7, 0x20d17e0d, 0x91484a8, 0x20dc4742,
-  0x91af976, 0x20e70f32, 0x9217062, 0x20f1d5de,
-  0x927e96b, 0x20fc9b44, 0x92e6492, 0x21075f65,
-  0x934e1d6, 0x21122240, 0x93b6137, 0x211ce3d5,
-  0x941e2b4, 0x2127a423, 0x948664d, 0x21326329,
-  0x94eec03, 0x213d20e8, 0x95573d4, 0x2147dd5f,
-  0x95bfdc1, 0x2152988d, 0x96289c9, 0x215d5273,
-  0x96917ec, 0x21680b0f, 0x96fa82a, 0x2172c262,
-  0x9763a83, 0x217d786a, 0x97ccef5, 0x21882d28,
-  0x9836582, 0x2192e09b, 0x989fe29, 0x219d92c2,
-  0x99098e9, 0x21a8439e, 0x99735c2, 0x21b2f32e,
-  0x99dd4b4, 0x21bda171, 0x9a475bf, 0x21c84e67,
-  0x9ab18e3, 0x21d2fa0f, 0x9b1be1e, 0x21dda46a,
-  0x9b86572, 0x21e84d76, 0x9bf0edd, 0x21f2f534,
-  0x9c5ba60, 0x21fd9ba3, 0x9cc67fa, 0x220840c2,
-  0x9d317ab, 0x2212e492, 0x9d9c973, 0x221d8711,
-  0x9e07d51, 0x2228283f, 0x9e73346, 0x2232c81c,
-  0x9edeb50, 0x223d66a8, 0x9f4a570, 0x224803e2,
-  0x9fb61a5, 0x22529fca, 0xa021fef, 0x225d3a5e,
-  0xa08e04f, 0x2267d3a0, 0xa0fa2c3, 0x22726b8e,
-  0xa16674b, 0x227d0228, 0xa1d2de7, 0x2287976e,
-  0xa23f698, 0x22922b5e, 0xa2ac15b, 0x229cbdfa,
-  0xa318e32, 0x22a74f40, 0xa385d1d, 0x22b1df30,
-  0xa3f2e19, 0x22bc6dca, 0xa460129, 0x22c6fb0c,
-  0xa4cd64b, 0x22d186f8, 0xa53ad7e, 0x22dc118c,
-  0xa5a86c4, 0x22e69ac8, 0xa61621b, 0x22f122ab,
-  0xa683f83, 0x22fba936, 0xa6f1efc, 0x23062e67,
-  0xa760086, 0x2310b23e, 0xa7ce420, 0x231b34bc,
-  0xa83c9ca, 0x2325b5df, 0xa8ab184, 0x233035a7,
-  0xa919b4e, 0x233ab414, 0xa988727, 0x23453125,
-  0xa9f750f, 0x234facda, 0xaa66506, 0x235a2733,
-  0xaad570c, 0x2364a02e, 0xab44b1f, 0x236f17cc,
-  0xabb4141, 0x23798e0d, 0xac23971, 0x238402ef,
-  0xac933ae, 0x238e7673, 0xad02ff8, 0x2398e898,
-  0xad72e4f, 0x23a3595e, 0xade2eb3, 0x23adc8c4,
-  0xae53123, 0x23b836ca, 0xaec35a0, 0x23c2a36f,
-  0xaf33c28, 0x23cd0eb3, 0xafa44bc, 0x23d77896,
-  0xb014f5b, 0x23e1e117, 0xb085c05, 0x23ec4837,
-  0xb0f6aba, 0x23f6adf3, 0xb167b79, 0x2401124d,
-  0xb1d8e43, 0x240b7543, 0xb24a316, 0x2415d6d5,
-  0xb2bb9f4, 0x24203704, 0xb32d2da, 0x242a95ce,
-  0xb39edca, 0x2434f332, 0xb410ac3, 0x243f4f32,
-  0xb4829c4, 0x2449a9cc, 0xb4f4acd, 0x245402ff,
-  0xb566ddf, 0x245e5acc, 0xb5d92f8, 0x2468b132,
-  0xb64ba19, 0x24730631, 0xb6be341, 0x247d59c8,
-  0xb730e70, 0x2487abf7, 0xb7a3ba5, 0x2491fcbe,
-  0xb816ae1, 0x249c4c1b, 0xb889c23, 0x24a69a0f,
-  0xb8fcf6b, 0x24b0e699, 0xb9704b9, 0x24bb31ba,
-  0xb9e3c0b, 0x24c57b6f, 0xba57563, 0x24cfc3ba,
-  0xbacb0bf, 0x24da0a9a, 0xbb3ee20, 0x24e4500e,
-  0xbbb2d85, 0x24ee9415, 0xbc26eee, 0x24f8d6b0,
-  0xbc9b25a, 0x250317df, 0xbd0f7ca, 0x250d57a0,
-  0xbd83f3d, 0x251795f3, 0xbdf88b3, 0x2521d2d8,
-  0xbe6d42b, 0x252c0e4f, 0xbee21a5, 0x25364857,
-  0xbf57121, 0x254080ef, 0xbfcc29f, 0x254ab818,
-  0xc04161e, 0x2554edd1, 0xc0b6b9e, 0x255f2219,
-  0xc12c31f, 0x256954f1, 0xc1a1ca0, 0x25738657,
-  0xc217822, 0x257db64c, 0xc28d5a3, 0x2587e4cf,
-  0xc303524, 0x259211df, 0xc3796a5, 0x259c3d7c,
-  0xc3efa25, 0x25a667a7, 0xc465fa3, 0x25b0905d,
-  0xc4dc720, 0x25bab7a0, 0xc55309b, 0x25c4dd6e,
-  0xc5c9c14, 0x25cf01c8, 0xc64098b, 0x25d924ac,
-  0xc6b78ff, 0x25e3461b, 0xc72ea70, 0x25ed6614,
-  0xc7a5dde, 0x25f78497, 0xc81d349, 0x2601a1a2,
-  0xc894aaf, 0x260bbd37, 0xc90c412, 0x2615d754,
-  0xc983f70, 0x261feffa, 0xc9fbcca, 0x262a0727,
-  0xca73c1e, 0x26341cdb, 0xcaebd6e, 0x263e3117,
-  0xcb640b8, 0x264843d9, 0xcbdc5fc, 0x26525521,
-  0xcc54d3a, 0x265c64ef, 0xcccd671, 0x26667342,
-  0xcd461a2, 0x2670801a, 0xcdbeecc, 0x267a8b77,
-  0xce37def, 0x26849558, 0xceb0f0a, 0x268e9dbd,
-  0xcf2a21d, 0x2698a4a6, 0xcfa3729, 0x26a2aa11,
-  0xd01ce2b, 0x26acadff, 0xd096725, 0x26b6b070,
-  0xd110216, 0x26c0b162, 0xd189efe, 0x26cab0d6,
-  0xd203ddc, 0x26d4aecb, 0xd27deb0, 0x26deab41,
-  0xd2f817b, 0x26e8a637, 0xd37263a, 0x26f29fad,
-  0xd3eccef, 0x26fc97a3, 0xd467599, 0x27068e18,
-  0xd4e2037, 0x2710830c, 0xd55ccca, 0x271a767e,
-  0xd5d7b50, 0x2724686e, 0xd652bcb, 0x272e58dc,
-  0xd6cde39, 0x273847c8, 0xd74929a, 0x27423530,
-  0xd7c48ee, 0x274c2115, 0xd840134, 0x27560b76,
-  0xd8bbb6d, 0x275ff452, 0xd937798, 0x2769dbaa,
-  0xd9b35b4, 0x2773c17d, 0xda2f5c2, 0x277da5cb,
-  0xdaab7c0, 0x27878893, 0xdb27bb0, 0x279169d5,
-  0xdba4190, 0x279b4990, 0xdc20960, 0x27a527c4,
-  0xdc9d320, 0x27af0472, 0xdd19ed0, 0x27b8df97,
-  0xdd96c6f, 0x27c2b934, 0xde13bfd, 0x27cc9149,
-  0xde90d79, 0x27d667d5, 0xdf0e0e4, 0x27e03cd8,
-  0xdf8b63d, 0x27ea1052, 0xe008d84, 0x27f3e241,
-  0xe0866b8, 0x27fdb2a7, 0xe1041d9, 0x28078181,
-  0xe181ee8, 0x28114ed0, 0xe1ffde2, 0x281b1a94,
-  0xe27dec9, 0x2824e4cc, 0xe2fc19c, 0x282ead78,
-  0xe37a65b, 0x28387498, 0xe3f8d05, 0x28423a2a,
-  0xe47759a, 0x284bfe2f, 0xe4f6019, 0x2855c0a6,
-  0xe574c84, 0x285f8190, 0xe5f3ad8, 0x286940ea,
-  0xe672b16, 0x2872feb6, 0xe6f1d3d, 0x287cbaf3,
-  0xe77114e, 0x288675a0, 0xe7f0748, 0x28902ebd,
-  0xe86ff2a, 0x2899e64a, 0xe8ef8f4, 0x28a39c46,
-  0xe96f4a7, 0x28ad50b1, 0xe9ef241, 0x28b7038b,
-  0xea6f1c2, 0x28c0b4d2, 0xeaef32b, 0x28ca6488,
-  0xeb6f67a, 0x28d412ab, 0xebefbb0, 0x28ddbf3b,
-  0xec702cb, 0x28e76a37, 0xecf0bcd, 0x28f113a0,
-  0xed716b4, 0x28fabb75, 0xedf2380, 0x290461b5,
-  0xee73231, 0x290e0661, 0xeef42c7, 0x2917a977,
-  0xef75541, 0x29214af8, 0xeff699f, 0x292aeae3,
-  0xf077fe1, 0x29348937, 0xf0f9805, 0x293e25f5,
-  0xf17b20d, 0x2947c11c, 0xf1fcdf8, 0x29515aab,
-  0xf27ebc5, 0x295af2a3, 0xf300b74, 0x29648902,
-  0xf382d05, 0x296e1dc9, 0xf405077, 0x2977b0f7,
-  0xf4875ca, 0x2981428c, 0xf509cfe, 0x298ad287,
-  0xf58c613, 0x299460e8, 0xf60f108, 0x299dedaf,
-  0xf691ddd, 0x29a778db, 0xf714c91, 0x29b1026c,
-  0xf797d24, 0x29ba8a61, 0xf81af97, 0x29c410ba,
-  0xf89e3e8, 0x29cd9578, 0xf921a17, 0x29d71899,
-  0xf9a5225, 0x29e09a1c, 0xfa28c10, 0x29ea1a03,
-  0xfaac7d8, 0x29f3984c, 0xfb3057d, 0x29fd14f6,
-  0xfbb4500, 0x2a069003, 0xfc3865e, 0x2a100970,
-  0xfcbc999, 0x2a19813f, 0xfd40eaf, 0x2a22f76e,
-  0xfdc55a1, 0x2a2c6bfd, 0xfe49e6d, 0x2a35deeb,
-  0xfece915, 0x2a3f503a, 0xff53597, 0x2a48bfe7,
-  0xffd83f4, 0x2a522df3, 0x1005d42a, 0x2a5b9a5d,
-  0x100e2639, 0x2a650525, 0x10167a22, 0x2a6e6e4b,
-  0x101ecfe4, 0x2a77d5ce, 0x1027277e, 0x2a813bae,
-  0x102f80f1, 0x2a8a9fea, 0x1037dc3b, 0x2a940283,
-  0x1040395d, 0x2a9d6377, 0x10489856, 0x2aa6c2c6,
-  0x1050f926, 0x2ab02071, 0x10595bcd, 0x2ab97c77,
-  0x1061c04a, 0x2ac2d6d6, 0x106a269d, 0x2acc2f90,
-  0x10728ec6, 0x2ad586a3, 0x107af8c4, 0x2adedc10,
-  0x10836497, 0x2ae82fd5, 0x108bd23f, 0x2af181f3,
-  0x109441bb, 0x2afad269, 0x109cb30b, 0x2b042137,
-  0x10a5262f, 0x2b0d6e5c, 0x10ad9b26, 0x2b16b9d9,
-  0x10b611f1, 0x2b2003ac, 0x10be8a8d, 0x2b294bd5,
-  0x10c704fd, 0x2b329255, 0x10cf813e, 0x2b3bd72a,
-  0x10d7ff51, 0x2b451a55, 0x10e07f36, 0x2b4e5bd4,
-  0x10e900ec, 0x2b579ba8, 0x10f18472, 0x2b60d9d0,
-  0x10fa09c9, 0x2b6a164d, 0x110290f0, 0x2b73511c,
-  0x110b19e7, 0x2b7c8a3f, 0x1113a4ad, 0x2b85c1b5,
-  0x111c3142, 0x2b8ef77d, 0x1124bfa6, 0x2b982b97,
-  0x112d4fd9, 0x2ba15e03, 0x1135e1d9, 0x2baa8ec0,
-  0x113e75a8, 0x2bb3bdce, 0x11470b44, 0x2bbceb2d,
-  0x114fa2ad, 0x2bc616dd, 0x11583be2, 0x2bcf40dc,
-  0x1160d6e5, 0x2bd8692b, 0x116973b3, 0x2be18fc9,
-  0x1172124d, 0x2beab4b6, 0x117ab2b3, 0x2bf3d7f2,
-  0x118354e4, 0x2bfcf97c, 0x118bf8e0, 0x2c061953,
-  0x11949ea6, 0x2c0f3779, 0x119d4636, 0x2c1853eb,
-  0x11a5ef90, 0x2c216eaa, 0x11ae9ab4, 0x2c2a87b6,
-  0x11b747a0, 0x2c339f0e, 0x11bff656, 0x2c3cb4b1,
-  0x11c8a6d4, 0x2c45c8a0, 0x11d1591a, 0x2c4edada,
-  0x11da0d28, 0x2c57eb5e, 0x11e2c2fd, 0x2c60fa2d,
-  0x11eb7a9a, 0x2c6a0746, 0x11f433fd, 0x2c7312a9,
-  0x11fcef27, 0x2c7c1c55, 0x1205ac17, 0x2c85244a,
-  0x120e6acc, 0x2c8e2a87, 0x12172b48, 0x2c972f0d,
-  0x121fed88, 0x2ca031da, 0x1228b18d, 0x2ca932ef,
-  0x12317756, 0x2cb2324c, 0x123a3ee4, 0x2cbb2fef,
-  0x12430835, 0x2cc42bd9, 0x124bd34a, 0x2ccd2609,
-  0x1254a021, 0x2cd61e7f, 0x125d6ebc, 0x2cdf153a,
-  0x12663f19, 0x2ce80a3a, 0x126f1138, 0x2cf0fd80,
-  0x1277e518, 0x2cf9ef09, 0x1280babb, 0x2d02ded7,
-  0x1289921e, 0x2d0bcce8, 0x12926b41, 0x2d14b93d,
-  0x129b4626, 0x2d1da3d5, 0x12a422ca, 0x2d268cb0,
-  0x12ad012e, 0x2d2f73cd, 0x12b5e151, 0x2d38592c,
-  0x12bec333, 0x2d413ccd, 0x12c7a6d4, 0x2d4a1eaf,
-  0x12d08c33, 0x2d52fed2, 0x12d97350, 0x2d5bdd36,
-  0x12e25c2b, 0x2d64b9da, 0x12eb46c3, 0x2d6d94bf,
-  0x12f43318, 0x2d766de2, 0x12fd2129, 0x2d7f4545,
-  0x130610f7, 0x2d881ae8, 0x130f0280, 0x2d90eec8,
-  0x1317f5c6, 0x2d99c0e7, 0x1320eac6, 0x2da29144,
-  0x1329e181, 0x2dab5fdf, 0x1332d9f7, 0x2db42cb6,
-  0x133bd427, 0x2dbcf7cb, 0x1344d011, 0x2dc5c11c,
-  0x134dcdb4, 0x2dce88aa, 0x1356cd11, 0x2dd74e73,
-  0x135fce26, 0x2de01278, 0x1368d0f3, 0x2de8d4b8,
-  0x1371d579, 0x2df19534, 0x137adbb6, 0x2dfa53e9,
-  0x1383e3ab, 0x2e0310d9, 0x138ced57, 0x2e0bcc03,
-  0x1395f8ba, 0x2e148566, 0x139f05d3, 0x2e1d3d03,
-  0x13a814a2, 0x2e25f2d8, 0x13b12526, 0x2e2ea6e6,
-  0x13ba3760, 0x2e37592c, 0x13c34b4f, 0x2e4009aa,
-  0x13cc60f2, 0x2e48b860, 0x13d5784a, 0x2e51654c,
-  0x13de9156, 0x2e5a1070, 0x13e7ac15, 0x2e62b9ca,
-  0x13f0c887, 0x2e6b615a, 0x13f9e6ad, 0x2e740720,
-  0x14030684, 0x2e7cab1c, 0x140c280e, 0x2e854d4d,
-  0x14154b4a, 0x2e8dedb3, 0x141e7037, 0x2e968c4d,
-  0x142796d5, 0x2e9f291b, 0x1430bf24, 0x2ea7c41e,
-  0x1439e923, 0x2eb05d53, 0x144314d3, 0x2eb8f4bc,
-  0x144c4232, 0x2ec18a58, 0x14557140, 0x2eca1e27,
-  0x145ea1fd, 0x2ed2b027, 0x1467d469, 0x2edb405a,
-  0x14710883, 0x2ee3cebe, 0x147a3e4b, 0x2eec5b53,
-  0x148375c1, 0x2ef4e619, 0x148caee4, 0x2efd6f10,
-  0x1495e9b3, 0x2f05f637, 0x149f2630, 0x2f0e7b8e,
-  0x14a86458, 0x2f16ff14, 0x14b1a42c, 0x2f1f80ca,
-  0x14bae5ab, 0x2f2800af, 0x14c428d6, 0x2f307ec2,
-  0x14cd6dab, 0x2f38fb03, 0x14d6b42b, 0x2f417573,
-  0x14dffc54, 0x2f49ee0f, 0x14e94627, 0x2f5264da,
-  0x14f291a4, 0x2f5ad9d1, 0x14fbdec9, 0x2f634cf5,
-  0x15052d97, 0x2f6bbe45, 0x150e7e0d, 0x2f742dc1,
-  0x1517d02b, 0x2f7c9b69, 0x152123f0, 0x2f85073c,
-  0x152a795d, 0x2f8d713a, 0x1533d070, 0x2f95d963,
-  0x153d292a, 0x2f9e3fb6, 0x15468389, 0x2fa6a433,
-  0x154fdf8f, 0x2faf06da, 0x15593d3a, 0x2fb767aa,
-  0x15629c89, 0x2fbfc6a3, 0x156bfd7d, 0x2fc823c5,
-  0x15756016, 0x2fd07f0f, 0x157ec452, 0x2fd8d882,
-  0x15882a32, 0x2fe1301c, 0x159191b5, 0x2fe985de,
-  0x159afadb, 0x2ff1d9c7, 0x15a465a3, 0x2ffa2bd6,
-  0x15add20d, 0x30027c0c, 0x15b74019, 0x300aca69,
-  0x15c0afc6, 0x301316eb, 0x15ca2115, 0x301b6193,
-  0x15d39403, 0x3023aa5f, 0x15dd0892, 0x302bf151,
-  0x15e67ec1, 0x30343667, 0x15eff690, 0x303c79a2,
-  0x15f96ffd, 0x3044bb00, 0x1602eb0a, 0x304cfa83,
-  0x160c67b4, 0x30553828, 0x1615e5fd, 0x305d73f0,
-  0x161f65e4, 0x3065addb, 0x1628e767, 0x306de5e9,
-  0x16326a88, 0x30761c18, 0x163bef46, 0x307e5069,
-  0x1645759f, 0x308682dc, 0x164efd94, 0x308eb36f,
-  0x16588725, 0x3096e223, 0x16621251, 0x309f0ef8,
-  0x166b9f18, 0x30a739ed, 0x16752d79, 0x30af6302,
-  0x167ebd74, 0x30b78a36, 0x16884f09, 0x30bfaf89,
-  0x1691e237, 0x30c7d2fb, 0x169b76fe, 0x30cff48c,
-  0x16a50d5d, 0x30d8143b, 0x16aea555, 0x30e03208,
-  0x16b83ee4, 0x30e84df3, 0x16c1da0b, 0x30f067fb,
-  0x16cb76c9, 0x30f8801f, 0x16d5151d, 0x31009661,
-  0x16deb508, 0x3108aabf, 0x16e85689, 0x3110bd39,
-  0x16f1f99f, 0x3118cdcf, 0x16fb9e4b, 0x3120dc80,
-  0x1705448b, 0x3128e94c, 0x170eec60, 0x3130f433,
-  0x171895c9, 0x3138fd35, 0x172240c5, 0x31410450,
-  0x172bed55, 0x31490986, 0x17359b78, 0x31510cd5,
-  0x173f4b2e, 0x31590e3e, 0x1748fc75, 0x31610dbf,
-  0x1752af4f, 0x31690b59, 0x175c63ba, 0x3171070c,
-  0x176619b6, 0x317900d6, 0x176fd143, 0x3180f8b8,
-  0x17798a60, 0x3188eeb2, 0x1783450d, 0x3190e2c3,
-  0x178d014a, 0x3198d4ea, 0x1796bf16, 0x31a0c528,
-  0x17a07e70, 0x31a8b37c, 0x17aa3f5a, 0x31b09fe7,
-  0x17b401d1, 0x31b88a66, 0x17bdc5d6, 0x31c072fb,
-  0x17c78b68, 0x31c859a5, 0x17d15288, 0x31d03e64,
-  0x17db1b34, 0x31d82137, 0x17e4e56c, 0x31e0021e,
-  0x17eeb130, 0x31e7e118, 0x17f87e7f, 0x31efbe27,
-  0x18024d59, 0x31f79948, 0x180c1dbf, 0x31ff727c,
-  0x1815efae, 0x320749c3, 0x181fc328, 0x320f1f1c,
-  0x1829982b, 0x3216f287, 0x18336eb7, 0x321ec403,
-  0x183d46cc, 0x32269391, 0x18472069, 0x322e6130,
-  0x1850fb8e, 0x32362ce0, 0x185ad83c, 0x323df6a0,
-  0x1864b670, 0x3245be70, 0x186e962b, 0x324d8450,
-  0x1878776d, 0x32554840, 0x18825a35, 0x325d0a3e,
-  0x188c3e83, 0x3264ca4c, 0x18962456, 0x326c8868,
-  0x18a00bae, 0x32744493, 0x18a9f48a, 0x327bfecc,
-  0x18b3deeb, 0x3283b712, 0x18bdcad0, 0x328b6d66,
-  0x18c7b838, 0x329321c7, 0x18d1a724, 0x329ad435,
-  0x18db9792, 0x32a284b0, 0x18e58982, 0x32aa3336,
-  0x18ef7cf4, 0x32b1dfc9, 0x18f971e8, 0x32b98a67,
-  0x1903685d, 0x32c13311, 0x190d6053, 0x32c8d9c6,
-  0x191759c9, 0x32d07e85, 0x192154bf, 0x32d82150,
-  0x192b5135, 0x32dfc224, 0x19354f2a, 0x32e76102,
-  0x193f4e9e, 0x32eefdea, 0x19494f90, 0x32f698db,
-  0x19535201, 0x32fe31d5, 0x195d55ef, 0x3305c8d7,
-  0x19675b5a, 0x330d5de3, 0x19716243, 0x3314f0f6,
-  0x197b6aa8, 0x331c8211, 0x19857489, 0x33241134,
-  0x198f7fe6, 0x332b9e5e, 0x19998cbe, 0x3333298f,
-  0x19a39b11, 0x333ab2c6, 0x19adaadf, 0x33423a04,
-  0x19b7bc27, 0x3349bf48, 0x19c1cee9, 0x33514292,
-  0x19cbe325, 0x3358c3e2, 0x19d5f8d9, 0x33604336,
-  0x19e01006, 0x3367c090, 0x19ea28ac, 0x336f3bee,
-  0x19f442c9, 0x3376b551, 0x19fe5e5e, 0x337e2cb7,
-  0x1a087b69, 0x3385a222, 0x1a1299ec, 0x338d1590,
-  0x1a1cb9e5, 0x33948701, 0x1a26db54, 0x339bf675,
-  0x1a30fe38, 0x33a363ec, 0x1a3b2292, 0x33aacf65,
-  0x1a454860, 0x33b238e0, 0x1a4f6fa3, 0x33b9a05d,
-  0x1a599859, 0x33c105db, 0x1a63c284, 0x33c8695b,
-  0x1a6dee21, 0x33cfcadc, 0x1a781b31, 0x33d72a5d,
-  0x1a8249b4, 0x33de87de, 0x1a8c79a9, 0x33e5e360,
-  0x1a96ab0f, 0x33ed3ce1, 0x1aa0dde7, 0x33f49462,
-  0x1aab122f, 0x33fbe9e2, 0x1ab547e8, 0x34033d61,
-  0x1abf7f11, 0x340a8edf, 0x1ac9b7a9, 0x3411de5b,
-  0x1ad3f1b1, 0x34192bd5, 0x1ade2d28, 0x3420774d,
-  0x1ae86a0d, 0x3427c0c3, 0x1af2a860, 0x342f0836,
-  0x1afce821, 0x34364da6, 0x1b072950, 0x343d9112,
-  0x1b116beb, 0x3444d27b, 0x1b1baff2, 0x344c11e0,
-  0x1b25f566, 0x34534f41, 0x1b303c46, 0x345a8a9d,
-  0x1b3a8491, 0x3461c3f5, 0x1b44ce46, 0x3468fb47,
-  0x1b4f1967, 0x34703095, 0x1b5965f1, 0x347763dd,
-  0x1b63b3e5, 0x347e951f, 0x1b6e0342, 0x3485c45b,
-  0x1b785409, 0x348cf190, 0x1b82a638, 0x34941cbf,
-  0x1b8cf9cf, 0x349b45e7, 0x1b974ece, 0x34a26d08,
-  0x1ba1a534, 0x34a99221, 0x1babfd01, 0x34b0b533,
-  0x1bb65634, 0x34b7d63c, 0x1bc0b0ce, 0x34bef53d,
-  0x1bcb0cce, 0x34c61236, 0x1bd56a32, 0x34cd2d26,
-  0x1bdfc8fc, 0x34d4460c, 0x1bea292b, 0x34db5cea,
-  0x1bf48abd, 0x34e271bd, 0x1bfeedb3, 0x34e98487,
-  0x1c09520d, 0x34f09546, 0x1c13b7c9, 0x34f7a3fb,
-  0x1c1e1ee9, 0x34feb0a5, 0x1c28876a, 0x3505bb44,
-  0x1c32f14d, 0x350cc3d8, 0x1c3d5c91, 0x3513ca60,
-  0x1c47c936, 0x351acedd, 0x1c52373c, 0x3521d14d,
-  0x1c5ca6a2, 0x3528d1b1, 0x1c671768, 0x352fd008,
-  0x1c71898d, 0x3536cc52, 0x1c7bfd11, 0x353dc68f,
-  0x1c8671f3, 0x3544bebf, 0x1c90e834, 0x354bb4e1,
-  0x1c9b5fd2, 0x3552a8f4, 0x1ca5d8cd, 0x35599afa,
-  0x1cb05326, 0x35608af1, 0x1cbacedb, 0x356778d9,
-  0x1cc54bec, 0x356e64b2, 0x1ccfca59, 0x35754e7c,
-  0x1cda4a21, 0x357c3636, 0x1ce4cb44, 0x35831be0,
-  0x1cef4dc2, 0x3589ff7a, 0x1cf9d199, 0x3590e104,
-  0x1d0456ca, 0x3597c07d, 0x1d0edd55, 0x359e9de5,
-  0x1d196538, 0x35a5793c, 0x1d23ee74, 0x35ac5282,
-  0x1d2e7908, 0x35b329b5, 0x1d3904f4, 0x35b9fed7,
-  0x1d439236, 0x35c0d1e7, 0x1d4e20d0, 0x35c7a2e3,
-  0x1d58b0c0, 0x35ce71ce, 0x1d634206, 0x35d53ea5,
-  0x1d6dd4a2, 0x35dc0968, 0x1d786892, 0x35e2d219,
-  0x1d82fdd8, 0x35e998b5, 0x1d8d9472, 0x35f05d3d,
-  0x1d982c60, 0x35f71fb1, 0x1da2c5a2, 0x35fde011,
-  0x1dad6036, 0x36049e5b, 0x1db7fc1e, 0x360b5a90,
-  0x1dc29958, 0x361214b0, 0x1dcd37e4, 0x3618ccba,
-  0x1dd7d7c1, 0x361f82af, 0x1de278ef, 0x3626368d,
-  0x1ded1b6e, 0x362ce855, 0x1df7bf3e, 0x36339806,
-  0x1e02645d, 0x363a45a0, 0x1e0d0acc, 0x3640f123,
-  0x1e17b28a, 0x36479a8e, 0x1e225b96, 0x364e41e2,
-  0x1e2d05f1, 0x3654e71d, 0x1e37b199, 0x365b8a41,
-  0x1e425e8f, 0x36622b4c, 0x1e4d0cd2, 0x3668ca3e,
-  0x1e57bc62, 0x366f6717, 0x1e626d3e, 0x367601d7,
-  0x1e6d1f65, 0x367c9a7e, 0x1e77d2d8, 0x3683310b,
-  0x1e828796, 0x3689c57d, 0x1e8d3d9e, 0x369057d6,
-  0x1e97f4f1, 0x3696e814, 0x1ea2ad8d, 0x369d7637,
-  0x1ead6773, 0x36a4023f, 0x1eb822a1, 0x36aa8c2c,
-  0x1ec2df18, 0x36b113fd, 0x1ecd9cd7, 0x36b799b3,
-  0x1ed85bdd, 0x36be1d4c, 0x1ee31c2b, 0x36c49ec9,
-  0x1eedddc0, 0x36cb1e2a, 0x1ef8a09b, 0x36d19b6e,
-  0x1f0364bc, 0x36d81695, 0x1f0e2a22, 0x36de8f9e,
-  0x1f18f0ce, 0x36e5068a, 0x1f23b8be, 0x36eb7b58,
-  0x1f2e81f3, 0x36f1ee09, 0x1f394c6b, 0x36f85e9a,
-  0x1f441828, 0x36fecd0e, 0x1f4ee527, 0x37053962,
-  0x1f59b369, 0x370ba398, 0x1f6482ed, 0x37120bae,
-  0x1f6f53b3, 0x371871a5, 0x1f7a25ba, 0x371ed57c,
-  0x1f84f902, 0x37253733, 0x1f8fcd8b, 0x372b96ca,
-  0x1f9aa354, 0x3731f440, 0x1fa57a5d, 0x37384f95,
-  0x1fb052a5, 0x373ea8ca, 0x1fbb2c2c, 0x3744ffdd,
-  0x1fc606f1, 0x374b54ce, 0x1fd0e2f5, 0x3751a79e,
-  0x1fdbc036, 0x3757f84c, 0x1fe69eb4, 0x375e46d8,
-  0x1ff17e70, 0x37649341, 0x1ffc5f67, 0x376add88,
-  0x2007419b, 0x377125ac, 0x2012250a, 0x37776bac,
-  0x201d09b4, 0x377daf89, 0x2027ef99, 0x3783f143,
-  0x2032d6b8, 0x378a30d8, 0x203dbf11, 0x37906e49,
-  0x2048a8a4, 0x3796a996, 0x2053936f, 0x379ce2be,
-  0x205e7f74, 0x37a319c2, 0x20696cb0, 0x37a94ea0,
-  0x20745b24, 0x37af8159, 0x207f4acf, 0x37b5b1ec,
-  0x208a3bb2, 0x37bbe05a, 0x20952dcb, 0x37c20ca1,
-  0x20a0211a, 0x37c836c2, 0x20ab159e, 0x37ce5ebd,
-  0x20b60b58, 0x37d48490, 0x20c10247, 0x37daa83d,
-  0x20cbfa6a, 0x37e0c9c3, 0x20d6f3c1, 0x37e6e921,
-  0x20e1ee4b, 0x37ed0657, 0x20ecea09, 0x37f32165,
-  0x20f7e6f9, 0x37f93a4b, 0x2102e51c, 0x37ff5109,
-  0x210de470, 0x3805659e, 0x2118e4f6, 0x380b780a,
-  0x2123e6ad, 0x3811884d, 0x212ee995, 0x38179666,
-  0x2139edac, 0x381da256, 0x2144f2f3, 0x3823ac1d,
-  0x214ff96a, 0x3829b3b9, 0x215b0110, 0x382fb92a,
-  0x216609e3, 0x3835bc71, 0x217113e5, 0x383bbd8e,
-  0x217c1f15, 0x3841bc7f, 0x21872b72, 0x3847b946,
-  0x219238fb, 0x384db3e0, 0x219d47b1, 0x3853ac4f,
-  0x21a85793, 0x3859a292, 0x21b368a0, 0x385f96a9,
-  0x21be7ad8, 0x38658894, 0x21c98e3b, 0x386b7852,
-  0x21d4a2c8, 0x387165e3, 0x21dfb87f, 0x38775147,
-  0x21eacf5f, 0x387d3a7e, 0x21f5e768, 0x38832187,
-  0x22010099, 0x38890663, 0x220c1af3, 0x388ee910,
-  0x22173674, 0x3894c98f, 0x2222531c, 0x389aa7e0,
-  0x222d70eb, 0x38a08402, 0x22388fe1, 0x38a65df6,
-  0x2243affc, 0x38ac35ba, 0x224ed13d, 0x38b20b4f,
-  0x2259f3a3, 0x38b7deb4, 0x2265172e, 0x38bdafea,
-  0x22703bdc, 0x38c37eef, 0x227b61af, 0x38c94bc4,
-  0x228688a4, 0x38cf1669, 0x2291b0bd, 0x38d4dedd,
-  0x229cd9f8, 0x38daa520, 0x22a80456, 0x38e06932,
-  0x22b32fd4, 0x38e62b13, 0x22be5c74, 0x38ebeac2,
-  0x22c98a35, 0x38f1a840, 0x22d4b916, 0x38f7638b,
-  0x22dfe917, 0x38fd1ca4, 0x22eb1a37, 0x3902d38b,
-  0x22f64c77, 0x3908883f, 0x23017fd5, 0x390e3ac0,
-  0x230cb451, 0x3913eb0e, 0x2317e9eb, 0x39199929,
-  0x232320a2, 0x391f4510, 0x232e5876, 0x3924eec3,
-  0x23399167, 0x392a9642, 0x2344cb73, 0x39303b8e,
-  0x2350069b, 0x3935dea4, 0x235b42df, 0x393b7f86,
-  0x2366803c, 0x39411e33, 0x2371beb5, 0x3946baac,
-  0x237cfe47, 0x394c54ee, 0x23883ef2, 0x3951ecfc,
-  0x239380b6, 0x395782d3, 0x239ec393, 0x395d1675,
-  0x23aa0788, 0x3962a7e0, 0x23b54c95, 0x39683715,
-  0x23c092b9, 0x396dc414, 0x23cbd9f4, 0x39734edc,
-  0x23d72245, 0x3978d76c, 0x23e26bac, 0x397e5dc6,
-  0x23edb628, 0x3983e1e8, 0x23f901ba, 0x398963d2,
-  0x24044e60, 0x398ee385, 0x240f9c1a, 0x399460ff,
-  0x241aeae8, 0x3999dc42, 0x24263ac9, 0x399f554b,
-  0x24318bbe, 0x39a4cc1c, 0x243cddc4, 0x39aa40b4,
-  0x244830dd, 0x39afb313, 0x24538507, 0x39b52339,
-  0x245eda43, 0x39ba9125, 0x246a308f, 0x39bffcd7,
-  0x247587eb, 0x39c5664f, 0x2480e057, 0x39cacd8d,
-  0x248c39d3, 0x39d03291, 0x2497945d, 0x39d5955a,
-  0x24a2eff6, 0x39daf5e8, 0x24ae4c9d, 0x39e0543c,
-  0x24b9aa52, 0x39e5b054, 0x24c50914, 0x39eb0a31,
-  0x24d068e2, 0x39f061d2, 0x24dbc9bd, 0x39f5b737,
-  0x24e72ba4, 0x39fb0a60, 0x24f28e96, 0x3a005b4d,
-  0x24fdf294, 0x3a05a9fd, 0x2509579b, 0x3a0af671,
-  0x2514bdad, 0x3a1040a8, 0x252024c9, 0x3a1588a2,
-  0x252b8cee, 0x3a1ace5f, 0x2536f61b, 0x3a2011de,
-  0x25426051, 0x3a25531f, 0x254dcb8f, 0x3a2a9223,
-  0x255937d5, 0x3a2fcee8, 0x2564a521, 0x3a350970,
-  0x25701374, 0x3a3a41b9, 0x257b82cd, 0x3a3f77c3,
-  0x2586f32c, 0x3a44ab8e, 0x25926490, 0x3a49dd1a,
-  0x259dd6f9, 0x3a4f0c67, 0x25a94a67, 0x3a543974,
-  0x25b4bed8, 0x3a596442, 0x25c0344d, 0x3a5e8cd0,
-  0x25cbaac5, 0x3a63b31d, 0x25d72240, 0x3a68d72b,
-  0x25e29abc, 0x3a6df8f8, 0x25ee143b, 0x3a731884,
-  0x25f98ebb, 0x3a7835cf, 0x26050a3b, 0x3a7d50da,
-  0x261086bc, 0x3a8269a3, 0x261c043d, 0x3a87802a,
-  0x262782be, 0x3a8c9470, 0x2633023e, 0x3a91a674,
-  0x263e82bc, 0x3a96b636, 0x264a0438, 0x3a9bc3b6,
-  0x265586b3, 0x3aa0cef3, 0x26610a2a, 0x3aa5d7ee,
-  0x266c8e9f, 0x3aaadea6, 0x26781410, 0x3aafe31b,
-  0x26839a7c, 0x3ab4e54c, 0x268f21e5, 0x3ab9e53a,
-  0x269aaa48, 0x3abee2e5, 0x26a633a6, 0x3ac3de4c,
-  0x26b1bdff, 0x3ac8d76f, 0x26bd4951, 0x3acdce4d,
-  0x26c8d59c, 0x3ad2c2e8, 0x26d462e1, 0x3ad7b53d,
-  0x26dff11d, 0x3adca54e, 0x26eb8052, 0x3ae1931a,
-  0x26f7107e, 0x3ae67ea1, 0x2702a1a1, 0x3aeb67e3,
-  0x270e33bb, 0x3af04edf, 0x2719c6cb, 0x3af53395,
-  0x27255ad1, 0x3afa1605, 0x2730efcc, 0x3afef630,
-  0x273c85bc, 0x3b03d414, 0x27481ca1, 0x3b08afb2,
-  0x2753b479, 0x3b0d8909, 0x275f4d45, 0x3b126019,
-  0x276ae704, 0x3b1734e2, 0x277681b6, 0x3b1c0764,
-  0x27821d59, 0x3b20d79e, 0x278db9ef, 0x3b25a591,
-  0x27995776, 0x3b2a713d, 0x27a4f5ed, 0x3b2f3aa0,
-  0x27b09555, 0x3b3401bb, 0x27bc35ad, 0x3b38c68e,
-  0x27c7d6f4, 0x3b3d8918, 0x27d3792b, 0x3b42495a,
-  0x27df1c50, 0x3b470753, 0x27eac063, 0x3b4bc303,
-  0x27f66564, 0x3b507c69, 0x28020b52, 0x3b553386,
-  0x280db22d, 0x3b59e85a, 0x281959f4, 0x3b5e9ae4,
-  0x282502a7, 0x3b634b23, 0x2830ac45, 0x3b67f919,
-  0x283c56cf, 0x3b6ca4c4, 0x28480243, 0x3b714e25,
-  0x2853aea1, 0x3b75f53c, 0x285f5be9, 0x3b7a9a07,
-  0x286b0a1a, 0x3b7f3c87, 0x2876b934, 0x3b83dcbc,
-  0x28826936, 0x3b887aa6, 0x288e1a20, 0x3b8d1644,
-  0x2899cbf1, 0x3b91af97, 0x28a57ea9, 0x3b96469d,
-  0x28b13248, 0x3b9adb57, 0x28bce6cd, 0x3b9f6dc5,
-  0x28c89c37, 0x3ba3fde7, 0x28d45286, 0x3ba88bbc,
-  0x28e009ba, 0x3bad1744, 0x28ebc1d3, 0x3bb1a080,
-  0x28f77acf, 0x3bb6276e, 0x290334af, 0x3bbaac0e,
-  0x290eef71, 0x3bbf2e62, 0x291aab16, 0x3bc3ae67,
-  0x2926679c, 0x3bc82c1f, 0x29322505, 0x3bcca789,
-  0x293de34e, 0x3bd120a4, 0x2949a278, 0x3bd59771,
-  0x29556282, 0x3bda0bf0, 0x2961236c, 0x3bde7e20,
-  0x296ce535, 0x3be2ee01, 0x2978a7dd, 0x3be75b93,
-  0x29846b63, 0x3bebc6d5, 0x29902fc7, 0x3bf02fc9,
-  0x299bf509, 0x3bf4966c, 0x29a7bb28, 0x3bf8fac0,
-  0x29b38223, 0x3bfd5cc4, 0x29bf49fa, 0x3c01bc78,
-  0x29cb12ad, 0x3c0619dc, 0x29d6dc3b, 0x3c0a74f0,
-  0x29e2a6a3, 0x3c0ecdb2, 0x29ee71e6, 0x3c132424,
-  0x29fa3e03, 0x3c177845, 0x2a060af9, 0x3c1bca16,
-  0x2a11d8c8, 0x3c201994, 0x2a1da770, 0x3c2466c2,
-  0x2a2976ef, 0x3c28b19e, 0x2a354746, 0x3c2cfa28,
-  0x2a411874, 0x3c314060, 0x2a4cea79, 0x3c358446,
-  0x2a58bd54, 0x3c39c5da, 0x2a649105, 0x3c3e051b,
-  0x2a70658a, 0x3c42420a, 0x2a7c3ae5, 0x3c467ca6,
-  0x2a881114, 0x3c4ab4ef, 0x2a93e817, 0x3c4eeae5,
-  0x2a9fbfed, 0x3c531e88, 0x2aab9896, 0x3c574fd8,
-  0x2ab77212, 0x3c5b7ed4, 0x2ac34c60, 0x3c5fab7c,
-  0x2acf277f, 0x3c63d5d1, 0x2adb0370, 0x3c67fdd1,
-  0x2ae6e031, 0x3c6c237e, 0x2af2bdc3, 0x3c7046d6,
-  0x2afe9c24, 0x3c7467d9, 0x2b0a7b54, 0x3c788688,
-  0x2b165b54, 0x3c7ca2e2, 0x2b223c22, 0x3c80bce7,
-  0x2b2e1dbe, 0x3c84d496, 0x2b3a0027, 0x3c88e9f1,
-  0x2b45e35d, 0x3c8cfcf6, 0x2b51c760, 0x3c910da5,
-  0x2b5dac2f, 0x3c951bff, 0x2b6991ca, 0x3c992803,
-  0x2b75782f, 0x3c9d31b0, 0x2b815f60, 0x3ca13908,
-  0x2b8d475b, 0x3ca53e09, 0x2b99301f, 0x3ca940b3,
-  0x2ba519ad, 0x3cad4107, 0x2bb10404, 0x3cb13f04,
-  0x2bbcef23, 0x3cb53aaa, 0x2bc8db0b, 0x3cb933f9,
-  0x2bd4c7ba, 0x3cbd2af0, 0x2be0b52f, 0x3cc11f90,
-  0x2beca36c, 0x3cc511d9, 0x2bf8926f, 0x3cc901c9,
-  0x2c048237, 0x3cccef62, 0x2c1072c4, 0x3cd0daa2,
-  0x2c1c6417, 0x3cd4c38b, 0x2c28562d, 0x3cd8aa1b,
-  0x2c344908, 0x3cdc8e52, 0x2c403ca5, 0x3ce07031,
-  0x2c4c3106, 0x3ce44fb7, 0x2c582629, 0x3ce82ce4,
-  0x2c641c0e, 0x3cec07b8, 0x2c7012b5, 0x3cefe032,
-  0x2c7c0a1d, 0x3cf3b653, 0x2c880245, 0x3cf78a1b,
-  0x2c93fb2e, 0x3cfb5b89, 0x2c9ff4d6, 0x3cff2a9d,
-  0x2cabef3d, 0x3d02f757, 0x2cb7ea63, 0x3d06c1b6,
-  0x2cc3e648, 0x3d0a89bc, 0x2ccfe2ea, 0x3d0e4f67,
-  0x2cdbe04a, 0x3d1212b7, 0x2ce7de66, 0x3d15d3ad,
-  0x2cf3dd3f, 0x3d199248, 0x2cffdcd4, 0x3d1d4e88,
-  0x2d0bdd25, 0x3d21086c, 0x2d17de31, 0x3d24bff6,
-  0x2d23dff7, 0x3d287523, 0x2d2fe277, 0x3d2c27f6,
-  0x2d3be5b1, 0x3d2fd86c, 0x2d47e9a5, 0x3d338687,
-  0x2d53ee51, 0x3d373245, 0x2d5ff3b5, 0x3d3adba7,
-  0x2d6bf9d1, 0x3d3e82ae, 0x2d7800a5, 0x3d422757,
-  0x2d84082f, 0x3d45c9a4, 0x2d901070, 0x3d496994,
-  0x2d9c1967, 0x3d4d0728, 0x2da82313, 0x3d50a25e,
-  0x2db42d74, 0x3d543b37, 0x2dc0388a, 0x3d57d1b3,
-  0x2dcc4454, 0x3d5b65d2, 0x2dd850d2, 0x3d5ef793,
-  0x2de45e03, 0x3d6286f6, 0x2df06be6, 0x3d6613fb,
-  0x2dfc7a7c, 0x3d699ea3, 0x2e0889c4, 0x3d6d26ec,
-  0x2e1499bd, 0x3d70acd7, 0x2e20aa67, 0x3d743064,
-  0x2e2cbbc1, 0x3d77b192, 0x2e38cdcb, 0x3d7b3061,
-  0x2e44e084, 0x3d7eacd2, 0x2e50f3ed, 0x3d8226e4,
-  0x2e5d0804, 0x3d859e96, 0x2e691cc9, 0x3d8913ea,
-  0x2e75323c, 0x3d8c86de, 0x2e81485c, 0x3d8ff772,
-  0x2e8d5f29, 0x3d9365a8, 0x2e9976a1, 0x3d96d17d,
-  0x2ea58ec6, 0x3d9a3af2, 0x2eb1a796, 0x3d9da208,
-  0x2ebdc110, 0x3da106bd, 0x2ec9db35, 0x3da46912,
-  0x2ed5f604, 0x3da7c907, 0x2ee2117c, 0x3dab269b,
-  0x2eee2d9d, 0x3dae81cf, 0x2efa4a67, 0x3db1daa2,
-  0x2f0667d9, 0x3db53113, 0x2f1285f2, 0x3db88524,
-  0x2f1ea4b2, 0x3dbbd6d4, 0x2f2ac419, 0x3dbf2622,
-  0x2f36e426, 0x3dc2730f, 0x2f4304d8, 0x3dc5bd9b,
-  0x2f4f2630, 0x3dc905c5, 0x2f5b482d, 0x3dcc4b8d,
-  0x2f676ace, 0x3dcf8ef3, 0x2f738e12, 0x3dd2cff7,
-  0x2f7fb1fa, 0x3dd60e99, 0x2f8bd685, 0x3dd94ad8,
-  0x2f97fbb2, 0x3ddc84b5, 0x2fa42181, 0x3ddfbc30,
-  0x2fb047f2, 0x3de2f148, 0x2fbc6f03, 0x3de623fd,
-  0x2fc896b5, 0x3de9544f, 0x2fd4bf08, 0x3dec823e,
-  0x2fe0e7f9, 0x3defadca, 0x2fed118a, 0x3df2d6f3,
-  0x2ff93bba, 0x3df5fdb8, 0x30056687, 0x3df9221a,
-  0x301191f3, 0x3dfc4418, 0x301dbdfb, 0x3dff63b2,
-  0x3029eaa1, 0x3e0280e9, 0x303617e2, 0x3e059bbb,
-  0x304245c0, 0x3e08b42a, 0x304e7438, 0x3e0bca34,
-  0x305aa34c, 0x3e0eddd9, 0x3066d2fa, 0x3e11ef1b,
-  0x30730342, 0x3e14fdf7, 0x307f3424, 0x3e180a6f,
-  0x308b659f, 0x3e1b1482, 0x309797b2, 0x3e1e1c30,
-  0x30a3ca5d, 0x3e212179, 0x30affda0, 0x3e24245d,
-  0x30bc317a, 0x3e2724db, 0x30c865ea, 0x3e2a22f4,
-  0x30d49af1, 0x3e2d1ea8, 0x30e0d08d, 0x3e3017f6,
-  0x30ed06bf, 0x3e330ede, 0x30f93d86, 0x3e360360,
-  0x310574e0, 0x3e38f57c, 0x3111accf, 0x3e3be532,
-  0x311de551, 0x3e3ed282, 0x312a1e66, 0x3e41bd6c,
-  0x3136580d, 0x3e44a5ef, 0x31429247, 0x3e478c0b,
-  0x314ecd11, 0x3e4a6fc1, 0x315b086d, 0x3e4d5110,
-  0x31674459, 0x3e502ff9, 0x317380d6, 0x3e530c7a,
-  0x317fbde2, 0x3e55e694, 0x318bfb7d, 0x3e58be47,
-  0x319839a6, 0x3e5b9392, 0x31a4785e, 0x3e5e6676,
-  0x31b0b7a4, 0x3e6136f3, 0x31bcf777, 0x3e640507,
-  0x31c937d6, 0x3e66d0b4, 0x31d578c2, 0x3e6999fa,
-  0x31e1ba3a, 0x3e6c60d7, 0x31edfc3d, 0x3e6f254c,
-  0x31fa3ecb, 0x3e71e759, 0x320681e3, 0x3e74a6fd,
-  0x3212c585, 0x3e77643a, 0x321f09b1, 0x3e7a1f0d,
-  0x322b4e66, 0x3e7cd778, 0x323793a3, 0x3e7f8d7b,
-  0x3243d968, 0x3e824114, 0x32501fb5, 0x3e84f245,
-  0x325c6688, 0x3e87a10c, 0x3268ade3, 0x3e8a4d6a,
-  0x3274f5c3, 0x3e8cf75f, 0x32813e2a, 0x3e8f9eeb,
-  0x328d8715, 0x3e92440d, 0x3299d085, 0x3e94e6c6,
-  0x32a61a7a, 0x3e978715, 0x32b264f2, 0x3e9a24fb,
-  0x32beafed, 0x3e9cc076, 0x32cafb6b, 0x3e9f5988,
-  0x32d7476c, 0x3ea1f02f, 0x32e393ef, 0x3ea4846c,
-  0x32efe0f2, 0x3ea7163f, 0x32fc2e77, 0x3ea9a5a8,
-  0x33087c7d, 0x3eac32a6, 0x3314cb02, 0x3eaebd3a,
-  0x33211a07, 0x3eb14563, 0x332d698a, 0x3eb3cb21,
-  0x3339b98d, 0x3eb64e75, 0x33460a0d, 0x3eb8cf5d,
-  0x33525b0b, 0x3ebb4ddb, 0x335eac86, 0x3ebdc9ed,
-  0x336afe7e, 0x3ec04394, 0x337750f2, 0x3ec2bad0,
-  0x3383a3e2, 0x3ec52fa0, 0x338ff74d, 0x3ec7a205,
-  0x339c4b32, 0x3eca11fe, 0x33a89f92, 0x3ecc7f8b,
-  0x33b4f46c, 0x3eceeaad, 0x33c149bf, 0x3ed15363,
-  0x33cd9f8b, 0x3ed3b9ad, 0x33d9f5cf, 0x3ed61d8a,
-  0x33e64c8c, 0x3ed87efc, 0x33f2a3bf, 0x3edade01,
-  0x33fefb6a, 0x3edd3a9a, 0x340b538b, 0x3edf94c7,
-  0x3417ac22, 0x3ee1ec87, 0x3424052f, 0x3ee441da,
-  0x34305eb0, 0x3ee694c1, 0x343cb8a7, 0x3ee8e53a,
-  0x34491311, 0x3eeb3347, 0x34556def, 0x3eed7ee7,
-  0x3461c940, 0x3eefc81a, 0x346e2504, 0x3ef20ee0,
-  0x347a8139, 0x3ef45338, 0x3486dde1, 0x3ef69523,
-  0x34933afa, 0x3ef8d4a1, 0x349f9884, 0x3efb11b1,
-  0x34abf67e, 0x3efd4c54, 0x34b854e7, 0x3eff8489,
-  0x34c4b3c0, 0x3f01ba50, 0x34d11308, 0x3f03eda9,
-  0x34dd72be, 0x3f061e95, 0x34e9d2e3, 0x3f084d12,
-  0x34f63374, 0x3f0a7921, 0x35029473, 0x3f0ca2c2,
-  0x350ef5de, 0x3f0ec9f5, 0x351b57b5, 0x3f10eeb9,
-  0x3527b9f7, 0x3f13110f, 0x35341ca5, 0x3f1530f7,
-  0x35407fbd, 0x3f174e70, 0x354ce33f, 0x3f19697a,
-  0x3559472b, 0x3f1b8215, 0x3565ab80, 0x3f1d9842,
-  0x3572103d, 0x3f1fabff, 0x357e7563, 0x3f21bd4e,
-  0x358adaf0, 0x3f23cc2e, 0x359740e5, 0x3f25d89e,
-  0x35a3a740, 0x3f27e29f, 0x35b00e02, 0x3f29ea31,
-  0x35bc7529, 0x3f2bef53, 0x35c8dcb6, 0x3f2df206,
-  0x35d544a7, 0x3f2ff24a, 0x35e1acfd, 0x3f31f01d,
-  0x35ee15b7, 0x3f33eb81, 0x35fa7ed4, 0x3f35e476,
-  0x3606e854, 0x3f37dafa, 0x36135237, 0x3f39cf0e,
-  0x361fbc7b, 0x3f3bc0b3, 0x362c2721, 0x3f3dafe7,
-  0x36389228, 0x3f3f9cab, 0x3644fd8f, 0x3f4186ff,
-  0x36516956, 0x3f436ee3, 0x365dd57d, 0x3f455456,
-  0x366a4203, 0x3f473759, 0x3676aee8, 0x3f4917eb,
-  0x36831c2b, 0x3f4af60d, 0x368f89cb, 0x3f4cd1be,
-  0x369bf7c9, 0x3f4eaafe, 0x36a86623, 0x3f5081cd,
-  0x36b4d4d9, 0x3f52562c, 0x36c143ec, 0x3f54281a,
-  0x36cdb359, 0x3f55f796, 0x36da2321, 0x3f57c4a2,
-  0x36e69344, 0x3f598f3c, 0x36f303c0, 0x3f5b5765,
-  0x36ff7496, 0x3f5d1d1d, 0x370be5c4, 0x3f5ee063,
-  0x3718574b, 0x3f60a138, 0x3724c92a, 0x3f625f9b,
-  0x37313b60, 0x3f641b8d, 0x373daded, 0x3f65d50d,
-  0x374a20d0, 0x3f678c1c, 0x3756940a, 0x3f6940b8,
-  0x37630799, 0x3f6af2e3, 0x376f7b7d, 0x3f6ca29c,
-  0x377befb5, 0x3f6e4fe3, 0x37886442, 0x3f6ffab8,
-  0x3794d922, 0x3f71a31b, 0x37a14e55, 0x3f73490b,
-  0x37adc3db, 0x3f74ec8a, 0x37ba39b3, 0x3f768d96,
-  0x37c6afdc, 0x3f782c30, 0x37d32657, 0x3f79c857,
-  0x37df9d22, 0x3f7b620c, 0x37ec143e, 0x3f7cf94e,
-  0x37f88ba9, 0x3f7e8e1e, 0x38050364, 0x3f80207b,
-  0x38117b6d, 0x3f81b065, 0x381df3c5, 0x3f833ddd,
-  0x382a6c6a, 0x3f84c8e2, 0x3836e55d, 0x3f865174,
-  0x38435e9d, 0x3f87d792, 0x384fd829, 0x3f895b3e,
-  0x385c5201, 0x3f8adc77, 0x3868cc24, 0x3f8c5b3d,
-  0x38754692, 0x3f8dd78f, 0x3881c14b, 0x3f8f516e,
-  0x388e3c4d, 0x3f90c8da, 0x389ab799, 0x3f923dd2,
-  0x38a7332e, 0x3f93b058, 0x38b3af0c, 0x3f952069,
-  0x38c02b31, 0x3f968e07, 0x38cca79e, 0x3f97f932,
-  0x38d92452, 0x3f9961e8, 0x38e5a14d, 0x3f9ac82c,
-  0x38f21e8e, 0x3f9c2bfb, 0x38fe9c15, 0x3f9d8d56,
-  0x390b19e0, 0x3f9eec3e, 0x391797f0, 0x3fa048b2,
-  0x39241645, 0x3fa1a2b2, 0x393094dd, 0x3fa2fa3d,
-  0x393d13b8, 0x3fa44f55, 0x394992d7, 0x3fa5a1f9,
-  0x39561237, 0x3fa6f228, 0x396291d9, 0x3fa83fe3,
-  0x396f11bc, 0x3fa98b2a, 0x397b91e1, 0x3faad3fd,
-  0x39881245, 0x3fac1a5b, 0x399492ea, 0x3fad5e45,
-  0x39a113cd, 0x3fae9fbb, 0x39ad94f0, 0x3fafdebb,
-  0x39ba1651, 0x3fb11b48, 0x39c697f0, 0x3fb2555f,
-  0x39d319cc, 0x3fb38d02, 0x39df9be6, 0x3fb4c231,
-  0x39ec1e3b, 0x3fb5f4ea, 0x39f8a0cd, 0x3fb7252f,
-  0x3a05239a, 0x3fb852ff, 0x3a11a6a3, 0x3fb97e5a,
-  0x3a1e29e5, 0x3fbaa740, 0x3a2aad62, 0x3fbbcdb1,
-  0x3a373119, 0x3fbcf1ad, 0x3a43b508, 0x3fbe1334,
-  0x3a503930, 0x3fbf3246, 0x3a5cbd91, 0x3fc04ee3,
-  0x3a694229, 0x3fc1690a, 0x3a75c6f8, 0x3fc280bc,
-  0x3a824bfd, 0x3fc395f9, 0x3a8ed139, 0x3fc4a8c1,
-  0x3a9b56ab, 0x3fc5b913, 0x3aa7dc52, 0x3fc6c6f0,
-  0x3ab4622d, 0x3fc7d258, 0x3ac0e83d, 0x3fc8db4a,
-  0x3acd6e81, 0x3fc9e1c6, 0x3ad9f4f8, 0x3fcae5cd,
-  0x3ae67ba2, 0x3fcbe75e, 0x3af3027e, 0x3fcce67a,
-  0x3aff898c, 0x3fcde320, 0x3b0c10cb, 0x3fcedd50,
-  0x3b18983b, 0x3fcfd50b, 0x3b251fdc, 0x3fd0ca4f,
-  0x3b31a7ac, 0x3fd1bd1e, 0x3b3e2fac, 0x3fd2ad77,
-  0x3b4ab7db, 0x3fd39b5a, 0x3b574039, 0x3fd486c7,
-  0x3b63c8c4, 0x3fd56fbe, 0x3b70517d, 0x3fd6563f,
-  0x3b7cda63, 0x3fd73a4a, 0x3b896375, 0x3fd81bdf,
-  0x3b95ecb4, 0x3fd8fafe, 0x3ba2761e, 0x3fd9d7a7,
-  0x3baeffb3, 0x3fdab1d9, 0x3bbb8973, 0x3fdb8996,
-  0x3bc8135c, 0x3fdc5edc, 0x3bd49d70, 0x3fdd31ac,
-  0x3be127ac, 0x3fde0205, 0x3bedb212, 0x3fdecfe8,
-  0x3bfa3c9f, 0x3fdf9b55, 0x3c06c754, 0x3fe0644b,
-  0x3c135231, 0x3fe12acb, 0x3c1fdd34, 0x3fe1eed5,
-  0x3c2c685d, 0x3fe2b067, 0x3c38f3ac, 0x3fe36f84,
-  0x3c457f21, 0x3fe42c2a, 0x3c520aba, 0x3fe4e659,
-  0x3c5e9678, 0x3fe59e12, 0x3c6b2259, 0x3fe65354,
-  0x3c77ae5e, 0x3fe7061f, 0x3c843a85, 0x3fe7b674,
-  0x3c90c6cf, 0x3fe86452, 0x3c9d533b, 0x3fe90fb9,
-  0x3ca9dfc8, 0x3fe9b8a9, 0x3cb66c77, 0x3fea5f23,
-  0x3cc2f945, 0x3feb0326, 0x3ccf8634, 0x3feba4b2,
-  0x3cdc1342, 0x3fec43c7, 0x3ce8a06f, 0x3fece065,
-  0x3cf52dbb, 0x3fed7a8c, 0x3d01bb24, 0x3fee123d,
-  0x3d0e48ab, 0x3feea776, 0x3d1ad650, 0x3fef3a39,
-  0x3d276410, 0x3fefca84, 0x3d33f1ed, 0x3ff05858,
-  0x3d407fe6, 0x3ff0e3b6, 0x3d4d0df9, 0x3ff16c9c,
-  0x3d599c28, 0x3ff1f30b, 0x3d662a70, 0x3ff27703,
-  0x3d72b8d2, 0x3ff2f884, 0x3d7f474d, 0x3ff3778e,
-  0x3d8bd5e1, 0x3ff3f420, 0x3d98648d, 0x3ff46e3c,
-  0x3da4f351, 0x3ff4e5e0, 0x3db1822c, 0x3ff55b0d,
-  0x3dbe111e, 0x3ff5cdc3, 0x3dcaa027, 0x3ff63e01,
-  0x3dd72f45, 0x3ff6abc8, 0x3de3be78, 0x3ff71718,
-  0x3df04dc0, 0x3ff77ff1, 0x3dfcdd1d, 0x3ff7e652,
-  0x3e096c8d, 0x3ff84a3c, 0x3e15fc11, 0x3ff8abae,
-  0x3e228ba7, 0x3ff90aaa, 0x3e2f1b50, 0x3ff9672d,
-  0x3e3bab0b, 0x3ff9c13a, 0x3e483ad8, 0x3ffa18cf,
-  0x3e54cab5, 0x3ffa6dec, 0x3e615aa3, 0x3ffac092,
-  0x3e6deaa1, 0x3ffb10c1, 0x3e7a7aae, 0x3ffb5e78,
-  0x3e870aca, 0x3ffba9b8, 0x3e939af5, 0x3ffbf280,
-  0x3ea02b2e, 0x3ffc38d1, 0x3eacbb74, 0x3ffc7caa,
-  0x3eb94bc8, 0x3ffcbe0c, 0x3ec5dc28, 0x3ffcfcf6,
-  0x3ed26c94, 0x3ffd3969, 0x3edefd0c, 0x3ffd7364,
-  0x3eeb8d8f, 0x3ffdaae7, 0x3ef81e1d, 0x3ffddff3,
-  0x3f04aeb5, 0x3ffe1288, 0x3f113f56, 0x3ffe42a4,
-  0x3f1dd001, 0x3ffe704a, 0x3f2a60b4, 0x3ffe9b77,
-  0x3f36f170, 0x3ffec42d, 0x3f438234, 0x3ffeea6c,
-  0x3f5012fe, 0x3fff0e32, 0x3f5ca3d0, 0x3fff2f82,
-  0x3f6934a8, 0x3fff4e59, 0x3f75c585, 0x3fff6ab9,
-  0x3f825668, 0x3fff84a1, 0x3f8ee750, 0x3fff9c12,
-  0x3f9b783c, 0x3fffb10b, 0x3fa8092c, 0x3fffc38c,
-  0x3fb49a1f, 0x3fffd396, 0x3fc12b16, 0x3fffe128,
-  0x3fcdbc0f, 0x3fffec43, 0x3fda4d09, 0x3ffff4e6,
-  0x3fe6de05, 0x3ffffb11, 0x3ff36f02, 0x3ffffec4,
-};
-
-
-/**    
-* \par   
-* Generation of realCoefBQ31 array:    
-* \par    
-*  n = 4096        
-* 
for (i = 0; i < n; i++)    
-* {    
-*    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));    
-*    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));    
-* } 
    
-* \par    
-* Convert to fixed point Q31 format    
-*     round(pBTable[i] * pow(2, 31))    
-*    
-*/
-
-static const q31_t realCoefBQ31[8192] = {
-  0x40000000, 0x40000000, 0x400c90fe, 0x3ffffec4,
-  0x401921fb, 0x3ffffb11, 0x4025b2f7, 0x3ffff4e6,
-  0x403243f1, 0x3fffec43, 0x403ed4ea, 0x3fffe128,
-  0x404b65e1, 0x3fffd396, 0x4057f6d4, 0x3fffc38c,
-  0x406487c4, 0x3fffb10b, 0x407118b0, 0x3fff9c12,
-  0x407da998, 0x3fff84a1, 0x408a3a7b, 0x3fff6ab9,
-  0x4096cb58, 0x3fff4e59, 0x40a35c30, 0x3fff2f82,
-  0x40afed02, 0x3fff0e32, 0x40bc7dcc, 0x3ffeea6c,
-  0x40c90e90, 0x3ffec42d, 0x40d59f4c, 0x3ffe9b77,
-  0x40e22fff, 0x3ffe704a, 0x40eec0aa, 0x3ffe42a4,
-  0x40fb514b, 0x3ffe1288, 0x4107e1e3, 0x3ffddff3,
-  0x41147271, 0x3ffdaae7, 0x412102f4, 0x3ffd7364,
-  0x412d936c, 0x3ffd3969, 0x413a23d8, 0x3ffcfcf6,
-  0x4146b438, 0x3ffcbe0c, 0x4153448c, 0x3ffc7caa,
-  0x415fd4d2, 0x3ffc38d1, 0x416c650b, 0x3ffbf280,
-  0x4178f536, 0x3ffba9b8, 0x41858552, 0x3ffb5e78,
-  0x4192155f, 0x3ffb10c1, 0x419ea55d, 0x3ffac092,
-  0x41ab354b, 0x3ffa6dec, 0x41b7c528, 0x3ffa18cf,
-  0x41c454f5, 0x3ff9c13a, 0x41d0e4b0, 0x3ff9672d,
-  0x41dd7459, 0x3ff90aaa, 0x41ea03ef, 0x3ff8abae,
-  0x41f69373, 0x3ff84a3c, 0x420322e3, 0x3ff7e652,
-  0x420fb240, 0x3ff77ff1, 0x421c4188, 0x3ff71718,
-  0x4228d0bb, 0x3ff6abc8, 0x42355fd9, 0x3ff63e01,
-  0x4241eee2, 0x3ff5cdc3, 0x424e7dd4, 0x3ff55b0d,
-  0x425b0caf, 0x3ff4e5e0, 0x42679b73, 0x3ff46e3c,
-  0x42742a1f, 0x3ff3f420, 0x4280b8b3, 0x3ff3778e,
-  0x428d472e, 0x3ff2f884, 0x4299d590, 0x3ff27703,
-  0x42a663d8, 0x3ff1f30b, 0x42b2f207, 0x3ff16c9c,
-  0x42bf801a, 0x3ff0e3b6, 0x42cc0e13, 0x3ff05858,
-  0x42d89bf0, 0x3fefca84, 0x42e529b0, 0x3fef3a39,
-  0x42f1b755, 0x3feea776, 0x42fe44dc, 0x3fee123d,
-  0x430ad245, 0x3fed7a8c, 0x43175f91, 0x3fece065,
-  0x4323ecbe, 0x3fec43c7, 0x433079cc, 0x3feba4b2,
-  0x433d06bb, 0x3feb0326, 0x43499389, 0x3fea5f23,
-  0x43562038, 0x3fe9b8a9, 0x4362acc5, 0x3fe90fb9,
-  0x436f3931, 0x3fe86452, 0x437bc57b, 0x3fe7b674,
-  0x438851a2, 0x3fe7061f, 0x4394dda7, 0x3fe65354,
-  0x43a16988, 0x3fe59e12, 0x43adf546, 0x3fe4e659,
-  0x43ba80df, 0x3fe42c2a, 0x43c70c54, 0x3fe36f84,
-  0x43d397a3, 0x3fe2b067, 0x43e022cc, 0x3fe1eed5,
-  0x43ecadcf, 0x3fe12acb, 0x43f938ac, 0x3fe0644b,
-  0x4405c361, 0x3fdf9b55, 0x44124dee, 0x3fdecfe8,
-  0x441ed854, 0x3fde0205, 0x442b6290, 0x3fdd31ac,
-  0x4437eca4, 0x3fdc5edc, 0x4444768d, 0x3fdb8996,
-  0x4451004d, 0x3fdab1d9, 0x445d89e2, 0x3fd9d7a7,
-  0x446a134c, 0x3fd8fafe, 0x44769c8b, 0x3fd81bdf,
-  0x4483259d, 0x3fd73a4a, 0x448fae83, 0x3fd6563f,
-  0x449c373c, 0x3fd56fbe, 0x44a8bfc7, 0x3fd486c7,
-  0x44b54825, 0x3fd39b5a, 0x44c1d054, 0x3fd2ad77,
-  0x44ce5854, 0x3fd1bd1e, 0x44dae024, 0x3fd0ca4f,
-  0x44e767c5, 0x3fcfd50b, 0x44f3ef35, 0x3fcedd50,
-  0x45007674, 0x3fcde320, 0x450cfd82, 0x3fcce67a,
-  0x4519845e, 0x3fcbe75e, 0x45260b08, 0x3fcae5cd,
-  0x4532917f, 0x3fc9e1c6, 0x453f17c3, 0x3fc8db4a,
-  0x454b9dd3, 0x3fc7d258, 0x455823ae, 0x3fc6c6f0,
-  0x4564a955, 0x3fc5b913, 0x45712ec7, 0x3fc4a8c1,
-  0x457db403, 0x3fc395f9, 0x458a3908, 0x3fc280bc,
-  0x4596bdd7, 0x3fc1690a, 0x45a3426f, 0x3fc04ee3,
-  0x45afc6d0, 0x3fbf3246, 0x45bc4af8, 0x3fbe1334,
-  0x45c8cee7, 0x3fbcf1ad, 0x45d5529e, 0x3fbbcdb1,
-  0x45e1d61b, 0x3fbaa740, 0x45ee595d, 0x3fb97e5a,
-  0x45fadc66, 0x3fb852ff, 0x46075f33, 0x3fb7252f,
-  0x4613e1c5, 0x3fb5f4ea, 0x4620641a, 0x3fb4c231,
-  0x462ce634, 0x3fb38d02, 0x46396810, 0x3fb2555f,
-  0x4645e9af, 0x3fb11b48, 0x46526b10, 0x3fafdebb,
-  0x465eec33, 0x3fae9fbb, 0x466b6d16, 0x3fad5e45,
-  0x4677edbb, 0x3fac1a5b, 0x46846e1f, 0x3faad3fd,
-  0x4690ee44, 0x3fa98b2a, 0x469d6e27, 0x3fa83fe3,
-  0x46a9edc9, 0x3fa6f228, 0x46b66d29, 0x3fa5a1f9,
-  0x46c2ec48, 0x3fa44f55, 0x46cf6b23, 0x3fa2fa3d,
-  0x46dbe9bb, 0x3fa1a2b2, 0x46e86810, 0x3fa048b2,
-  0x46f4e620, 0x3f9eec3e, 0x470163eb, 0x3f9d8d56,
-  0x470de172, 0x3f9c2bfb, 0x471a5eb3, 0x3f9ac82c,
-  0x4726dbae, 0x3f9961e8, 0x47335862, 0x3f97f932,
-  0x473fd4cf, 0x3f968e07, 0x474c50f4, 0x3f952069,
-  0x4758ccd2, 0x3f93b058, 0x47654867, 0x3f923dd2,
-  0x4771c3b3, 0x3f90c8da, 0x477e3eb5, 0x3f8f516e,
-  0x478ab96e, 0x3f8dd78f, 0x479733dc, 0x3f8c5b3d,
-  0x47a3adff, 0x3f8adc77, 0x47b027d7, 0x3f895b3e,
-  0x47bca163, 0x3f87d792, 0x47c91aa3, 0x3f865174,
-  0x47d59396, 0x3f84c8e2, 0x47e20c3b, 0x3f833ddd,
-  0x47ee8493, 0x3f81b065, 0x47fafc9c, 0x3f80207b,
-  0x48077457, 0x3f7e8e1e, 0x4813ebc2, 0x3f7cf94e,
-  0x482062de, 0x3f7b620c, 0x482cd9a9, 0x3f79c857,
-  0x48395024, 0x3f782c30, 0x4845c64d, 0x3f768d96,
-  0x48523c25, 0x3f74ec8a, 0x485eb1ab, 0x3f73490b,
-  0x486b26de, 0x3f71a31b, 0x48779bbe, 0x3f6ffab8,
-  0x4884104b, 0x3f6e4fe3, 0x48908483, 0x3f6ca29c,
-  0x489cf867, 0x3f6af2e3, 0x48a96bf6, 0x3f6940b8,
-  0x48b5df30, 0x3f678c1c, 0x48c25213, 0x3f65d50d,
-  0x48cec4a0, 0x3f641b8d, 0x48db36d6, 0x3f625f9b,
-  0x48e7a8b5, 0x3f60a138, 0x48f41a3c, 0x3f5ee063,
-  0x49008b6a, 0x3f5d1d1d, 0x490cfc40, 0x3f5b5765,
-  0x49196cbc, 0x3f598f3c, 0x4925dcdf, 0x3f57c4a2,
-  0x49324ca7, 0x3f55f796, 0x493ebc14, 0x3f54281a,
-  0x494b2b27, 0x3f52562c, 0x495799dd, 0x3f5081cd,
-  0x49640837, 0x3f4eaafe, 0x49707635, 0x3f4cd1be,
-  0x497ce3d5, 0x3f4af60d, 0x49895118, 0x3f4917eb,
-  0x4995bdfd, 0x3f473759, 0x49a22a83, 0x3f455456,
-  0x49ae96aa, 0x3f436ee3, 0x49bb0271, 0x3f4186ff,
-  0x49c76dd8, 0x3f3f9cab, 0x49d3d8df, 0x3f3dafe7,
-  0x49e04385, 0x3f3bc0b3, 0x49ecadc9, 0x3f39cf0e,
-  0x49f917ac, 0x3f37dafa, 0x4a05812c, 0x3f35e476,
-  0x4a11ea49, 0x3f33eb81, 0x4a1e5303, 0x3f31f01d,
-  0x4a2abb59, 0x3f2ff24a, 0x4a37234a, 0x3f2df206,
-  0x4a438ad7, 0x3f2bef53, 0x4a4ff1fe, 0x3f29ea31,
-  0x4a5c58c0, 0x3f27e29f, 0x4a68bf1b, 0x3f25d89e,
-  0x4a752510, 0x3f23cc2e, 0x4a818a9d, 0x3f21bd4e,
-  0x4a8defc3, 0x3f1fabff, 0x4a9a5480, 0x3f1d9842,
-  0x4aa6b8d5, 0x3f1b8215, 0x4ab31cc1, 0x3f19697a,
-  0x4abf8043, 0x3f174e70, 0x4acbe35b, 0x3f1530f7,
-  0x4ad84609, 0x3f13110f, 0x4ae4a84b, 0x3f10eeb9,
-  0x4af10a22, 0x3f0ec9f5, 0x4afd6b8d, 0x3f0ca2c2,
-  0x4b09cc8c, 0x3f0a7921, 0x4b162d1d, 0x3f084d12,
-  0x4b228d42, 0x3f061e95, 0x4b2eecf8, 0x3f03eda9,
-  0x4b3b4c40, 0x3f01ba50, 0x4b47ab19, 0x3eff8489,
-  0x4b540982, 0x3efd4c54, 0x4b60677c, 0x3efb11b1,
-  0x4b6cc506, 0x3ef8d4a1, 0x4b79221f, 0x3ef69523,
-  0x4b857ec7, 0x3ef45338, 0x4b91dafc, 0x3ef20ee0,
-  0x4b9e36c0, 0x3eefc81a, 0x4baa9211, 0x3eed7ee7,
-  0x4bb6ecef, 0x3eeb3347, 0x4bc34759, 0x3ee8e53a,
-  0x4bcfa150, 0x3ee694c1, 0x4bdbfad1, 0x3ee441da,
-  0x4be853de, 0x3ee1ec87, 0x4bf4ac75, 0x3edf94c7,
-  0x4c010496, 0x3edd3a9a, 0x4c0d5c41, 0x3edade01,
-  0x4c19b374, 0x3ed87efc, 0x4c260a31, 0x3ed61d8a,
-  0x4c326075, 0x3ed3b9ad, 0x4c3eb641, 0x3ed15363,
-  0x4c4b0b94, 0x3eceeaad, 0x4c57606e, 0x3ecc7f8b,
-  0x4c63b4ce, 0x3eca11fe, 0x4c7008b3, 0x3ec7a205,
-  0x4c7c5c1e, 0x3ec52fa0, 0x4c88af0e, 0x3ec2bad0,
-  0x4c950182, 0x3ec04394, 0x4ca1537a, 0x3ebdc9ed,
-  0x4cada4f5, 0x3ebb4ddb, 0x4cb9f5f3, 0x3eb8cf5d,
-  0x4cc64673, 0x3eb64e75, 0x4cd29676, 0x3eb3cb21,
-  0x4cdee5f9, 0x3eb14563, 0x4ceb34fe, 0x3eaebd3a,
-  0x4cf78383, 0x3eac32a6, 0x4d03d189, 0x3ea9a5a8,
-  0x4d101f0e, 0x3ea7163f, 0x4d1c6c11, 0x3ea4846c,
-  0x4d28b894, 0x3ea1f02f, 0x4d350495, 0x3e9f5988,
-  0x4d415013, 0x3e9cc076, 0x4d4d9b0e, 0x3e9a24fb,
-  0x4d59e586, 0x3e978715, 0x4d662f7b, 0x3e94e6c6,
-  0x4d7278eb, 0x3e92440d, 0x4d7ec1d6, 0x3e8f9eeb,
-  0x4d8b0a3d, 0x3e8cf75f, 0x4d97521d, 0x3e8a4d6a,
-  0x4da39978, 0x3e87a10c, 0x4dafe04b, 0x3e84f245,
-  0x4dbc2698, 0x3e824114, 0x4dc86c5d, 0x3e7f8d7b,
-  0x4dd4b19a, 0x3e7cd778, 0x4de0f64f, 0x3e7a1f0d,
-  0x4ded3a7b, 0x3e77643a, 0x4df97e1d, 0x3e74a6fd,
-  0x4e05c135, 0x3e71e759, 0x4e1203c3, 0x3e6f254c,
-  0x4e1e45c6, 0x3e6c60d7, 0x4e2a873e, 0x3e6999fa,
-  0x4e36c82a, 0x3e66d0b4, 0x4e430889, 0x3e640507,
-  0x4e4f485c, 0x3e6136f3, 0x4e5b87a2, 0x3e5e6676,
-  0x4e67c65a, 0x3e5b9392, 0x4e740483, 0x3e58be47,
-  0x4e80421e, 0x3e55e694, 0x4e8c7f2a, 0x3e530c7a,
-  0x4e98bba7, 0x3e502ff9, 0x4ea4f793, 0x3e4d5110,
-  0x4eb132ef, 0x3e4a6fc1, 0x4ebd6db9, 0x3e478c0b,
-  0x4ec9a7f3, 0x3e44a5ef, 0x4ed5e19a, 0x3e41bd6c,
-  0x4ee21aaf, 0x3e3ed282, 0x4eee5331, 0x3e3be532,
-  0x4efa8b20, 0x3e38f57c, 0x4f06c27a, 0x3e360360,
-  0x4f12f941, 0x3e330ede, 0x4f1f2f73, 0x3e3017f6,
-  0x4f2b650f, 0x3e2d1ea8, 0x4f379a16, 0x3e2a22f4,
-  0x4f43ce86, 0x3e2724db, 0x4f500260, 0x3e24245d,
-  0x4f5c35a3, 0x3e212179, 0x4f68684e, 0x3e1e1c30,
-  0x4f749a61, 0x3e1b1482, 0x4f80cbdc, 0x3e180a6f,
-  0x4f8cfcbe, 0x3e14fdf7, 0x4f992d06, 0x3e11ef1b,
-  0x4fa55cb4, 0x3e0eddd9, 0x4fb18bc8, 0x3e0bca34,
-  0x4fbdba40, 0x3e08b42a, 0x4fc9e81e, 0x3e059bbb,
-  0x4fd6155f, 0x3e0280e9, 0x4fe24205, 0x3dff63b2,
-  0x4fee6e0d, 0x3dfc4418, 0x4ffa9979, 0x3df9221a,
-  0x5006c446, 0x3df5fdb8, 0x5012ee76, 0x3df2d6f3,
-  0x501f1807, 0x3defadca, 0x502b40f8, 0x3dec823e,
-  0x5037694b, 0x3de9544f, 0x504390fd, 0x3de623fd,
-  0x504fb80e, 0x3de2f148, 0x505bde7f, 0x3ddfbc30,
-  0x5068044e, 0x3ddc84b5, 0x5074297b, 0x3dd94ad8,
-  0x50804e06, 0x3dd60e99, 0x508c71ee, 0x3dd2cff7,
-  0x50989532, 0x3dcf8ef3, 0x50a4b7d3, 0x3dcc4b8d,
-  0x50b0d9d0, 0x3dc905c5, 0x50bcfb28, 0x3dc5bd9b,
-  0x50c91bda, 0x3dc2730f, 0x50d53be7, 0x3dbf2622,
-  0x50e15b4e, 0x3dbbd6d4, 0x50ed7a0e, 0x3db88524,
-  0x50f99827, 0x3db53113, 0x5105b599, 0x3db1daa2,
-  0x5111d263, 0x3dae81cf, 0x511dee84, 0x3dab269b,
-  0x512a09fc, 0x3da7c907, 0x513624cb, 0x3da46912,
-  0x51423ef0, 0x3da106bd, 0x514e586a, 0x3d9da208,
-  0x515a713a, 0x3d9a3af2, 0x5166895f, 0x3d96d17d,
-  0x5172a0d7, 0x3d9365a8, 0x517eb7a4, 0x3d8ff772,
-  0x518acdc4, 0x3d8c86de, 0x5196e337, 0x3d8913ea,
-  0x51a2f7fc, 0x3d859e96, 0x51af0c13, 0x3d8226e4,
-  0x51bb1f7c, 0x3d7eacd2, 0x51c73235, 0x3d7b3061,
-  0x51d3443f, 0x3d77b192, 0x51df5599, 0x3d743064,
-  0x51eb6643, 0x3d70acd7, 0x51f7763c, 0x3d6d26ec,
-  0x52038584, 0x3d699ea3, 0x520f941a, 0x3d6613fb,
-  0x521ba1fd, 0x3d6286f6, 0x5227af2e, 0x3d5ef793,
-  0x5233bbac, 0x3d5b65d2, 0x523fc776, 0x3d57d1b3,
-  0x524bd28c, 0x3d543b37, 0x5257dced, 0x3d50a25e,
-  0x5263e699, 0x3d4d0728, 0x526fef90, 0x3d496994,
-  0x527bf7d1, 0x3d45c9a4, 0x5287ff5b, 0x3d422757,
-  0x5294062f, 0x3d3e82ae, 0x52a00c4b, 0x3d3adba7,
-  0x52ac11af, 0x3d373245, 0x52b8165b, 0x3d338687,
-  0x52c41a4f, 0x3d2fd86c, 0x52d01d89, 0x3d2c27f6,
-  0x52dc2009, 0x3d287523, 0x52e821cf, 0x3d24bff6,
-  0x52f422db, 0x3d21086c, 0x5300232c, 0x3d1d4e88,
-  0x530c22c1, 0x3d199248, 0x5318219a, 0x3d15d3ad,
-  0x53241fb6, 0x3d1212b7, 0x53301d16, 0x3d0e4f67,
-  0x533c19b8, 0x3d0a89bc, 0x5348159d, 0x3d06c1b6,
-  0x535410c3, 0x3d02f757, 0x53600b2a, 0x3cff2a9d,
-  0x536c04d2, 0x3cfb5b89, 0x5377fdbb, 0x3cf78a1b,
-  0x5383f5e3, 0x3cf3b653, 0x538fed4b, 0x3cefe032,
-  0x539be3f2, 0x3cec07b8, 0x53a7d9d7, 0x3ce82ce4,
-  0x53b3cefa, 0x3ce44fb7, 0x53bfc35b, 0x3ce07031,
-  0x53cbb6f8, 0x3cdc8e52, 0x53d7a9d3, 0x3cd8aa1b,
-  0x53e39be9, 0x3cd4c38b, 0x53ef8d3c, 0x3cd0daa2,
-  0x53fb7dc9, 0x3cccef62, 0x54076d91, 0x3cc901c9,
-  0x54135c94, 0x3cc511d9, 0x541f4ad1, 0x3cc11f90,
-  0x542b3846, 0x3cbd2af0, 0x543724f5, 0x3cb933f9,
-  0x544310dd, 0x3cb53aaa, 0x544efbfc, 0x3cb13f04,
-  0x545ae653, 0x3cad4107, 0x5466cfe1, 0x3ca940b3,
-  0x5472b8a5, 0x3ca53e09, 0x547ea0a0, 0x3ca13908,
-  0x548a87d1, 0x3c9d31b0, 0x54966e36, 0x3c992803,
-  0x54a253d1, 0x3c951bff, 0x54ae38a0, 0x3c910da5,
-  0x54ba1ca3, 0x3c8cfcf6, 0x54c5ffd9, 0x3c88e9f1,
-  0x54d1e242, 0x3c84d496, 0x54ddc3de, 0x3c80bce7,
-  0x54e9a4ac, 0x3c7ca2e2, 0x54f584ac, 0x3c788688,
-  0x550163dc, 0x3c7467d9, 0x550d423d, 0x3c7046d6,
-  0x55191fcf, 0x3c6c237e, 0x5524fc90, 0x3c67fdd1,
-  0x5530d881, 0x3c63d5d1, 0x553cb3a0, 0x3c5fab7c,
-  0x55488dee, 0x3c5b7ed4, 0x5554676a, 0x3c574fd8,
-  0x55604013, 0x3c531e88, 0x556c17e9, 0x3c4eeae5,
-  0x5577eeec, 0x3c4ab4ef, 0x5583c51b, 0x3c467ca6,
-  0x558f9a76, 0x3c42420a, 0x559b6efb, 0x3c3e051b,
-  0x55a742ac, 0x3c39c5da, 0x55b31587, 0x3c358446,
-  0x55bee78c, 0x3c314060, 0x55cab8ba, 0x3c2cfa28,
-  0x55d68911, 0x3c28b19e, 0x55e25890, 0x3c2466c2,
-  0x55ee2738, 0x3c201994, 0x55f9f507, 0x3c1bca16,
-  0x5605c1fd, 0x3c177845, 0x56118e1a, 0x3c132424,
-  0x561d595d, 0x3c0ecdb2, 0x562923c5, 0x3c0a74f0,
-  0x5634ed53, 0x3c0619dc, 0x5640b606, 0x3c01bc78,
-  0x564c7ddd, 0x3bfd5cc4, 0x565844d8, 0x3bf8fac0,
-  0x56640af7, 0x3bf4966c, 0x566fd039, 0x3bf02fc9,
-  0x567b949d, 0x3bebc6d5, 0x56875823, 0x3be75b93,
-  0x56931acb, 0x3be2ee01, 0x569edc94, 0x3bde7e20,
-  0x56aa9d7e, 0x3bda0bf0, 0x56b65d88, 0x3bd59771,
-  0x56c21cb2, 0x3bd120a4, 0x56cddafb, 0x3bcca789,
-  0x56d99864, 0x3bc82c1f, 0x56e554ea, 0x3bc3ae67,
-  0x56f1108f, 0x3bbf2e62, 0x56fccb51, 0x3bbaac0e,
-  0x57088531, 0x3bb6276e, 0x57143e2d, 0x3bb1a080,
-  0x571ff646, 0x3bad1744, 0x572bad7a, 0x3ba88bbc,
-  0x573763c9, 0x3ba3fde7, 0x57431933, 0x3b9f6dc5,
-  0x574ecdb8, 0x3b9adb57, 0x575a8157, 0x3b96469d,
-  0x5766340f, 0x3b91af97, 0x5771e5e0, 0x3b8d1644,
-  0x577d96ca, 0x3b887aa6, 0x578946cc, 0x3b83dcbc,
-  0x5794f5e6, 0x3b7f3c87, 0x57a0a417, 0x3b7a9a07,
-  0x57ac515f, 0x3b75f53c, 0x57b7fdbd, 0x3b714e25,
-  0x57c3a931, 0x3b6ca4c4, 0x57cf53bb, 0x3b67f919,
-  0x57dafd59, 0x3b634b23, 0x57e6a60c, 0x3b5e9ae4,
-  0x57f24dd3, 0x3b59e85a, 0x57fdf4ae, 0x3b553386,
-  0x58099a9c, 0x3b507c69, 0x58153f9d, 0x3b4bc303,
-  0x5820e3b0, 0x3b470753, 0x582c86d5, 0x3b42495a,
-  0x5838290c, 0x3b3d8918, 0x5843ca53, 0x3b38c68e,
-  0x584f6aab, 0x3b3401bb, 0x585b0a13, 0x3b2f3aa0,
-  0x5866a88a, 0x3b2a713d, 0x58724611, 0x3b25a591,
-  0x587de2a7, 0x3b20d79e, 0x58897e4a, 0x3b1c0764,
-  0x589518fc, 0x3b1734e2, 0x58a0b2bb, 0x3b126019,
-  0x58ac4b87, 0x3b0d8909, 0x58b7e35f, 0x3b08afb2,
-  0x58c37a44, 0x3b03d414, 0x58cf1034, 0x3afef630,
-  0x58daa52f, 0x3afa1605, 0x58e63935, 0x3af53395,
-  0x58f1cc45, 0x3af04edf, 0x58fd5e5f, 0x3aeb67e3,
-  0x5908ef82, 0x3ae67ea1, 0x59147fae, 0x3ae1931a,
-  0x59200ee3, 0x3adca54e, 0x592b9d1f, 0x3ad7b53d,
-  0x59372a64, 0x3ad2c2e8, 0x5942b6af, 0x3acdce4d,
-  0x594e4201, 0x3ac8d76f, 0x5959cc5a, 0x3ac3de4c,
-  0x596555b8, 0x3abee2e5, 0x5970de1b, 0x3ab9e53a,
-  0x597c6584, 0x3ab4e54c, 0x5987ebf0, 0x3aafe31b,
-  0x59937161, 0x3aaadea6, 0x599ef5d6, 0x3aa5d7ee,
-  0x59aa794d, 0x3aa0cef3, 0x59b5fbc8, 0x3a9bc3b6,
-  0x59c17d44, 0x3a96b636, 0x59ccfdc2, 0x3a91a674,
-  0x59d87d42, 0x3a8c9470, 0x59e3fbc3, 0x3a87802a,
-  0x59ef7944, 0x3a8269a3, 0x59faf5c5, 0x3a7d50da,
-  0x5a067145, 0x3a7835cf, 0x5a11ebc5, 0x3a731884,
-  0x5a1d6544, 0x3a6df8f8, 0x5a28ddc0, 0x3a68d72b,
-  0x5a34553b, 0x3a63b31d, 0x5a3fcbb3, 0x3a5e8cd0,
-  0x5a4b4128, 0x3a596442, 0x5a56b599, 0x3a543974,
-  0x5a622907, 0x3a4f0c67, 0x5a6d9b70, 0x3a49dd1a,
-  0x5a790cd4, 0x3a44ab8e, 0x5a847d33, 0x3a3f77c3,
-  0x5a8fec8c, 0x3a3a41b9, 0x5a9b5adf, 0x3a350970,
-  0x5aa6c82b, 0x3a2fcee8, 0x5ab23471, 0x3a2a9223,
-  0x5abd9faf, 0x3a25531f, 0x5ac909e5, 0x3a2011de,
-  0x5ad47312, 0x3a1ace5f, 0x5adfdb37, 0x3a1588a2,
-  0x5aeb4253, 0x3a1040a8, 0x5af6a865, 0x3a0af671,
-  0x5b020d6c, 0x3a05a9fd, 0x5b0d716a, 0x3a005b4d,
-  0x5b18d45c, 0x39fb0a60, 0x5b243643, 0x39f5b737,
-  0x5b2f971e, 0x39f061d2, 0x5b3af6ec, 0x39eb0a31,
-  0x5b4655ae, 0x39e5b054, 0x5b51b363, 0x39e0543c,
-  0x5b5d100a, 0x39daf5e8, 0x5b686ba3, 0x39d5955a,
-  0x5b73c62d, 0x39d03291, 0x5b7f1fa9, 0x39cacd8d,
-  0x5b8a7815, 0x39c5664f, 0x5b95cf71, 0x39bffcd7,
-  0x5ba125bd, 0x39ba9125, 0x5bac7af9, 0x39b52339,
-  0x5bb7cf23, 0x39afb313, 0x5bc3223c, 0x39aa40b4,
-  0x5bce7442, 0x39a4cc1c, 0x5bd9c537, 0x399f554b,
-  0x5be51518, 0x3999dc42, 0x5bf063e6, 0x399460ff,
-  0x5bfbb1a0, 0x398ee385, 0x5c06fe46, 0x398963d2,
-  0x5c1249d8, 0x3983e1e8, 0x5c1d9454, 0x397e5dc6,
-  0x5c28ddbb, 0x3978d76c, 0x5c34260c, 0x39734edc,
-  0x5c3f6d47, 0x396dc414, 0x5c4ab36b, 0x39683715,
-  0x5c55f878, 0x3962a7e0, 0x5c613c6d, 0x395d1675,
-  0x5c6c7f4a, 0x395782d3, 0x5c77c10e, 0x3951ecfc,
-  0x5c8301b9, 0x394c54ee, 0x5c8e414b, 0x3946baac,
-  0x5c997fc4, 0x39411e33, 0x5ca4bd21, 0x393b7f86,
-  0x5caff965, 0x3935dea4, 0x5cbb348d, 0x39303b8e,
-  0x5cc66e99, 0x392a9642, 0x5cd1a78a, 0x3924eec3,
-  0x5cdcdf5e, 0x391f4510, 0x5ce81615, 0x39199929,
-  0x5cf34baf, 0x3913eb0e, 0x5cfe802b, 0x390e3ac0,
-  0x5d09b389, 0x3908883f, 0x5d14e5c9, 0x3902d38b,
-  0x5d2016e9, 0x38fd1ca4, 0x5d2b46ea, 0x38f7638b,
-  0x5d3675cb, 0x38f1a840, 0x5d41a38c, 0x38ebeac2,
-  0x5d4cd02c, 0x38e62b13, 0x5d57fbaa, 0x38e06932,
-  0x5d632608, 0x38daa520, 0x5d6e4f43, 0x38d4dedd,
-  0x5d79775c, 0x38cf1669, 0x5d849e51, 0x38c94bc4,
-  0x5d8fc424, 0x38c37eef, 0x5d9ae8d2, 0x38bdafea,
-  0x5da60c5d, 0x38b7deb4, 0x5db12ec3, 0x38b20b4f,
-  0x5dbc5004, 0x38ac35ba, 0x5dc7701f, 0x38a65df6,
-  0x5dd28f15, 0x38a08402, 0x5dddace4, 0x389aa7e0,
-  0x5de8c98c, 0x3894c98f, 0x5df3e50d, 0x388ee910,
-  0x5dfeff67, 0x38890663, 0x5e0a1898, 0x38832187,
-  0x5e1530a1, 0x387d3a7e, 0x5e204781, 0x38775147,
-  0x5e2b5d38, 0x387165e3, 0x5e3671c5, 0x386b7852,
-  0x5e418528, 0x38658894, 0x5e4c9760, 0x385f96a9,
-  0x5e57a86d, 0x3859a292, 0x5e62b84f, 0x3853ac4f,
-  0x5e6dc705, 0x384db3e0, 0x5e78d48e, 0x3847b946,
-  0x5e83e0eb, 0x3841bc7f, 0x5e8eec1b, 0x383bbd8e,
-  0x5e99f61d, 0x3835bc71, 0x5ea4fef0, 0x382fb92a,
-  0x5eb00696, 0x3829b3b9, 0x5ebb0d0d, 0x3823ac1d,
-  0x5ec61254, 0x381da256, 0x5ed1166b, 0x38179666,
-  0x5edc1953, 0x3811884d, 0x5ee71b0a, 0x380b780a,
-  0x5ef21b90, 0x3805659e, 0x5efd1ae4, 0x37ff5109,
-  0x5f081907, 0x37f93a4b, 0x5f1315f7, 0x37f32165,
-  0x5f1e11b5, 0x37ed0657, 0x5f290c3f, 0x37e6e921,
-  0x5f340596, 0x37e0c9c3, 0x5f3efdb9, 0x37daa83d,
-  0x5f49f4a8, 0x37d48490, 0x5f54ea62, 0x37ce5ebd,
-  0x5f5fdee6, 0x37c836c2, 0x5f6ad235, 0x37c20ca1,
-  0x5f75c44e, 0x37bbe05a, 0x5f80b531, 0x37b5b1ec,
-  0x5f8ba4dc, 0x37af8159, 0x5f969350, 0x37a94ea0,
-  0x5fa1808c, 0x37a319c2, 0x5fac6c91, 0x379ce2be,
-  0x5fb7575c, 0x3796a996, 0x5fc240ef, 0x37906e49,
-  0x5fcd2948, 0x378a30d8, 0x5fd81067, 0x3783f143,
-  0x5fe2f64c, 0x377daf89, 0x5feddaf6, 0x37776bac,
-  0x5ff8be65, 0x377125ac, 0x6003a099, 0x376add88,
-  0x600e8190, 0x37649341, 0x6019614c, 0x375e46d8,
-  0x60243fca, 0x3757f84c, 0x602f1d0b, 0x3751a79e,
-  0x6039f90f, 0x374b54ce, 0x6044d3d4, 0x3744ffdd,
-  0x604fad5b, 0x373ea8ca, 0x605a85a3, 0x37384f95,
-  0x60655cac, 0x3731f440, 0x60703275, 0x372b96ca,
-  0x607b06fe, 0x37253733, 0x6085da46, 0x371ed57c,
-  0x6090ac4d, 0x371871a5, 0x609b7d13, 0x37120bae,
-  0x60a64c97, 0x370ba398, 0x60b11ad9, 0x37053962,
-  0x60bbe7d8, 0x36fecd0e, 0x60c6b395, 0x36f85e9a,
-  0x60d17e0d, 0x36f1ee09, 0x60dc4742, 0x36eb7b58,
-  0x60e70f32, 0x36e5068a, 0x60f1d5de, 0x36de8f9e,
-  0x60fc9b44, 0x36d81695, 0x61075f65, 0x36d19b6e,
-  0x61122240, 0x36cb1e2a, 0x611ce3d5, 0x36c49ec9,
-  0x6127a423, 0x36be1d4c, 0x61326329, 0x36b799b3,
-  0x613d20e8, 0x36b113fd, 0x6147dd5f, 0x36aa8c2c,
-  0x6152988d, 0x36a4023f, 0x615d5273, 0x369d7637,
-  0x61680b0f, 0x3696e814, 0x6172c262, 0x369057d6,
-  0x617d786a, 0x3689c57d, 0x61882d28, 0x3683310b,
-  0x6192e09b, 0x367c9a7e, 0x619d92c2, 0x367601d7,
-  0x61a8439e, 0x366f6717, 0x61b2f32e, 0x3668ca3e,
-  0x61bda171, 0x36622b4c, 0x61c84e67, 0x365b8a41,
-  0x61d2fa0f, 0x3654e71d, 0x61dda46a, 0x364e41e2,
-  0x61e84d76, 0x36479a8e, 0x61f2f534, 0x3640f123,
-  0x61fd9ba3, 0x363a45a0, 0x620840c2, 0x36339806,
-  0x6212e492, 0x362ce855, 0x621d8711, 0x3626368d,
-  0x6228283f, 0x361f82af, 0x6232c81c, 0x3618ccba,
-  0x623d66a8, 0x361214b0, 0x624803e2, 0x360b5a90,
-  0x62529fca, 0x36049e5b, 0x625d3a5e, 0x35fde011,
-  0x6267d3a0, 0x35f71fb1, 0x62726b8e, 0x35f05d3d,
-  0x627d0228, 0x35e998b5, 0x6287976e, 0x35e2d219,
-  0x62922b5e, 0x35dc0968, 0x629cbdfa, 0x35d53ea5,
-  0x62a74f40, 0x35ce71ce, 0x62b1df30, 0x35c7a2e3,
-  0x62bc6dca, 0x35c0d1e7, 0x62c6fb0c, 0x35b9fed7,
-  0x62d186f8, 0x35b329b5, 0x62dc118c, 0x35ac5282,
-  0x62e69ac8, 0x35a5793c, 0x62f122ab, 0x359e9de5,
-  0x62fba936, 0x3597c07d, 0x63062e67, 0x3590e104,
-  0x6310b23e, 0x3589ff7a, 0x631b34bc, 0x35831be0,
-  0x6325b5df, 0x357c3636, 0x633035a7, 0x35754e7c,
-  0x633ab414, 0x356e64b2, 0x63453125, 0x356778d9,
-  0x634facda, 0x35608af1, 0x635a2733, 0x35599afa,
-  0x6364a02e, 0x3552a8f4, 0x636f17cc, 0x354bb4e1,
-  0x63798e0d, 0x3544bebf, 0x638402ef, 0x353dc68f,
-  0x638e7673, 0x3536cc52, 0x6398e898, 0x352fd008,
-  0x63a3595e, 0x3528d1b1, 0x63adc8c4, 0x3521d14d,
-  0x63b836ca, 0x351acedd, 0x63c2a36f, 0x3513ca60,
-  0x63cd0eb3, 0x350cc3d8, 0x63d77896, 0x3505bb44,
-  0x63e1e117, 0x34feb0a5, 0x63ec4837, 0x34f7a3fb,
-  0x63f6adf3, 0x34f09546, 0x6401124d, 0x34e98487,
-  0x640b7543, 0x34e271bd, 0x6415d6d5, 0x34db5cea,
-  0x64203704, 0x34d4460c, 0x642a95ce, 0x34cd2d26,
-  0x6434f332, 0x34c61236, 0x643f4f32, 0x34bef53d,
-  0x6449a9cc, 0x34b7d63c, 0x645402ff, 0x34b0b533,
-  0x645e5acc, 0x34a99221, 0x6468b132, 0x34a26d08,
-  0x64730631, 0x349b45e7, 0x647d59c8, 0x34941cbf,
-  0x6487abf7, 0x348cf190, 0x6491fcbe, 0x3485c45b,
-  0x649c4c1b, 0x347e951f, 0x64a69a0f, 0x347763dd,
-  0x64b0e699, 0x34703095, 0x64bb31ba, 0x3468fb47,
-  0x64c57b6f, 0x3461c3f5, 0x64cfc3ba, 0x345a8a9d,
-  0x64da0a9a, 0x34534f41, 0x64e4500e, 0x344c11e0,
-  0x64ee9415, 0x3444d27b, 0x64f8d6b0, 0x343d9112,
-  0x650317df, 0x34364da6, 0x650d57a0, 0x342f0836,
-  0x651795f3, 0x3427c0c3, 0x6521d2d8, 0x3420774d,
-  0x652c0e4f, 0x34192bd5, 0x65364857, 0x3411de5b,
-  0x654080ef, 0x340a8edf, 0x654ab818, 0x34033d61,
-  0x6554edd1, 0x33fbe9e2, 0x655f2219, 0x33f49462,
-  0x656954f1, 0x33ed3ce1, 0x65738657, 0x33e5e360,
-  0x657db64c, 0x33de87de, 0x6587e4cf, 0x33d72a5d,
-  0x659211df, 0x33cfcadc, 0x659c3d7c, 0x33c8695b,
-  0x65a667a7, 0x33c105db, 0x65b0905d, 0x33b9a05d,
-  0x65bab7a0, 0x33b238e0, 0x65c4dd6e, 0x33aacf65,
-  0x65cf01c8, 0x33a363ec, 0x65d924ac, 0x339bf675,
-  0x65e3461b, 0x33948701, 0x65ed6614, 0x338d1590,
-  0x65f78497, 0x3385a222, 0x6601a1a2, 0x337e2cb7,
-  0x660bbd37, 0x3376b551, 0x6615d754, 0x336f3bee,
-  0x661feffa, 0x3367c090, 0x662a0727, 0x33604336,
-  0x66341cdb, 0x3358c3e2, 0x663e3117, 0x33514292,
-  0x664843d9, 0x3349bf48, 0x66525521, 0x33423a04,
-  0x665c64ef, 0x333ab2c6, 0x66667342, 0x3333298f,
-  0x6670801a, 0x332b9e5e, 0x667a8b77, 0x33241134,
-  0x66849558, 0x331c8211, 0x668e9dbd, 0x3314f0f6,
-  0x6698a4a6, 0x330d5de3, 0x66a2aa11, 0x3305c8d7,
-  0x66acadff, 0x32fe31d5, 0x66b6b070, 0x32f698db,
-  0x66c0b162, 0x32eefdea, 0x66cab0d6, 0x32e76102,
-  0x66d4aecb, 0x32dfc224, 0x66deab41, 0x32d82150,
-  0x66e8a637, 0x32d07e85, 0x66f29fad, 0x32c8d9c6,
-  0x66fc97a3, 0x32c13311, 0x67068e18, 0x32b98a67,
-  0x6710830c, 0x32b1dfc9, 0x671a767e, 0x32aa3336,
-  0x6724686e, 0x32a284b0, 0x672e58dc, 0x329ad435,
-  0x673847c8, 0x329321c7, 0x67423530, 0x328b6d66,
-  0x674c2115, 0x3283b712, 0x67560b76, 0x327bfecc,
-  0x675ff452, 0x32744493, 0x6769dbaa, 0x326c8868,
-  0x6773c17d, 0x3264ca4c, 0x677da5cb, 0x325d0a3e,
-  0x67878893, 0x32554840, 0x679169d5, 0x324d8450,
-  0x679b4990, 0x3245be70, 0x67a527c4, 0x323df6a0,
-  0x67af0472, 0x32362ce0, 0x67b8df97, 0x322e6130,
-  0x67c2b934, 0x32269391, 0x67cc9149, 0x321ec403,
-  0x67d667d5, 0x3216f287, 0x67e03cd8, 0x320f1f1c,
-  0x67ea1052, 0x320749c3, 0x67f3e241, 0x31ff727c,
-  0x67fdb2a7, 0x31f79948, 0x68078181, 0x31efbe27,
-  0x68114ed0, 0x31e7e118, 0x681b1a94, 0x31e0021e,
-  0x6824e4cc, 0x31d82137, 0x682ead78, 0x31d03e64,
-  0x68387498, 0x31c859a5, 0x68423a2a, 0x31c072fb,
-  0x684bfe2f, 0x31b88a66, 0x6855c0a6, 0x31b09fe7,
-  0x685f8190, 0x31a8b37c, 0x686940ea, 0x31a0c528,
-  0x6872feb6, 0x3198d4ea, 0x687cbaf3, 0x3190e2c3,
-  0x688675a0, 0x3188eeb2, 0x68902ebd, 0x3180f8b8,
-  0x6899e64a, 0x317900d6, 0x68a39c46, 0x3171070c,
-  0x68ad50b1, 0x31690b59, 0x68b7038b, 0x31610dbf,
-  0x68c0b4d2, 0x31590e3e, 0x68ca6488, 0x31510cd5,
-  0x68d412ab, 0x31490986, 0x68ddbf3b, 0x31410450,
-  0x68e76a37, 0x3138fd35, 0x68f113a0, 0x3130f433,
-  0x68fabb75, 0x3128e94c, 0x690461b5, 0x3120dc80,
-  0x690e0661, 0x3118cdcf, 0x6917a977, 0x3110bd39,
-  0x69214af8, 0x3108aabf, 0x692aeae3, 0x31009661,
-  0x69348937, 0x30f8801f, 0x693e25f5, 0x30f067fb,
-  0x6947c11c, 0x30e84df3, 0x69515aab, 0x30e03208,
-  0x695af2a3, 0x30d8143b, 0x69648902, 0x30cff48c,
-  0x696e1dc9, 0x30c7d2fb, 0x6977b0f7, 0x30bfaf89,
-  0x6981428c, 0x30b78a36, 0x698ad287, 0x30af6302,
-  0x699460e8, 0x30a739ed, 0x699dedaf, 0x309f0ef8,
-  0x69a778db, 0x3096e223, 0x69b1026c, 0x308eb36f,
-  0x69ba8a61, 0x308682dc, 0x69c410ba, 0x307e5069,
-  0x69cd9578, 0x30761c18, 0x69d71899, 0x306de5e9,
-  0x69e09a1c, 0x3065addb, 0x69ea1a03, 0x305d73f0,
-  0x69f3984c, 0x30553828, 0x69fd14f6, 0x304cfa83,
-  0x6a069003, 0x3044bb00, 0x6a100970, 0x303c79a2,
-  0x6a19813f, 0x30343667, 0x6a22f76e, 0x302bf151,
-  0x6a2c6bfd, 0x3023aa5f, 0x6a35deeb, 0x301b6193,
-  0x6a3f503a, 0x301316eb, 0x6a48bfe7, 0x300aca69,
-  0x6a522df3, 0x30027c0c, 0x6a5b9a5d, 0x2ffa2bd6,
-  0x6a650525, 0x2ff1d9c7, 0x6a6e6e4b, 0x2fe985de,
-  0x6a77d5ce, 0x2fe1301c, 0x6a813bae, 0x2fd8d882,
-  0x6a8a9fea, 0x2fd07f0f, 0x6a940283, 0x2fc823c5,
-  0x6a9d6377, 0x2fbfc6a3, 0x6aa6c2c6, 0x2fb767aa,
-  0x6ab02071, 0x2faf06da, 0x6ab97c77, 0x2fa6a433,
-  0x6ac2d6d6, 0x2f9e3fb6, 0x6acc2f90, 0x2f95d963,
-  0x6ad586a3, 0x2f8d713a, 0x6adedc10, 0x2f85073c,
-  0x6ae82fd5, 0x2f7c9b69, 0x6af181f3, 0x2f742dc1,
-  0x6afad269, 0x2f6bbe45, 0x6b042137, 0x2f634cf5,
-  0x6b0d6e5c, 0x2f5ad9d1, 0x6b16b9d9, 0x2f5264da,
-  0x6b2003ac, 0x2f49ee0f, 0x6b294bd5, 0x2f417573,
-  0x6b329255, 0x2f38fb03, 0x6b3bd72a, 0x2f307ec2,
-  0x6b451a55, 0x2f2800af, 0x6b4e5bd4, 0x2f1f80ca,
-  0x6b579ba8, 0x2f16ff14, 0x6b60d9d0, 0x2f0e7b8e,
-  0x6b6a164d, 0x2f05f637, 0x6b73511c, 0x2efd6f10,
-  0x6b7c8a3f, 0x2ef4e619, 0x6b85c1b5, 0x2eec5b53,
-  0x6b8ef77d, 0x2ee3cebe, 0x6b982b97, 0x2edb405a,
-  0x6ba15e03, 0x2ed2b027, 0x6baa8ec0, 0x2eca1e27,
-  0x6bb3bdce, 0x2ec18a58, 0x6bbceb2d, 0x2eb8f4bc,
-  0x6bc616dd, 0x2eb05d53, 0x6bcf40dc, 0x2ea7c41e,
-  0x6bd8692b, 0x2e9f291b, 0x6be18fc9, 0x2e968c4d,
-  0x6beab4b6, 0x2e8dedb3, 0x6bf3d7f2, 0x2e854d4d,
-  0x6bfcf97c, 0x2e7cab1c, 0x6c061953, 0x2e740720,
-  0x6c0f3779, 0x2e6b615a, 0x6c1853eb, 0x2e62b9ca,
-  0x6c216eaa, 0x2e5a1070, 0x6c2a87b6, 0x2e51654c,
-  0x6c339f0e, 0x2e48b860, 0x6c3cb4b1, 0x2e4009aa,
-  0x6c45c8a0, 0x2e37592c, 0x6c4edada, 0x2e2ea6e6,
-  0x6c57eb5e, 0x2e25f2d8, 0x6c60fa2d, 0x2e1d3d03,
-  0x6c6a0746, 0x2e148566, 0x6c7312a9, 0x2e0bcc03,
-  0x6c7c1c55, 0x2e0310d9, 0x6c85244a, 0x2dfa53e9,
-  0x6c8e2a87, 0x2df19534, 0x6c972f0d, 0x2de8d4b8,
-  0x6ca031da, 0x2de01278, 0x6ca932ef, 0x2dd74e73,
-  0x6cb2324c, 0x2dce88aa, 0x6cbb2fef, 0x2dc5c11c,
-  0x6cc42bd9, 0x2dbcf7cb, 0x6ccd2609, 0x2db42cb6,
-  0x6cd61e7f, 0x2dab5fdf, 0x6cdf153a, 0x2da29144,
-  0x6ce80a3a, 0x2d99c0e7, 0x6cf0fd80, 0x2d90eec8,
-  0x6cf9ef09, 0x2d881ae8, 0x6d02ded7, 0x2d7f4545,
-  0x6d0bcce8, 0x2d766de2, 0x6d14b93d, 0x2d6d94bf,
-  0x6d1da3d5, 0x2d64b9da, 0x6d268cb0, 0x2d5bdd36,
-  0x6d2f73cd, 0x2d52fed2, 0x6d38592c, 0x2d4a1eaf,
-  0x6d413ccd, 0x2d413ccd, 0x6d4a1eaf, 0x2d38592c,
-  0x6d52fed2, 0x2d2f73cd, 0x6d5bdd36, 0x2d268cb0,
-  0x6d64b9da, 0x2d1da3d5, 0x6d6d94bf, 0x2d14b93d,
-  0x6d766de2, 0x2d0bcce8, 0x6d7f4545, 0x2d02ded7,
-  0x6d881ae8, 0x2cf9ef09, 0x6d90eec8, 0x2cf0fd80,
-  0x6d99c0e7, 0x2ce80a3a, 0x6da29144, 0x2cdf153a,
-  0x6dab5fdf, 0x2cd61e7f, 0x6db42cb6, 0x2ccd2609,
-  0x6dbcf7cb, 0x2cc42bd9, 0x6dc5c11c, 0x2cbb2fef,
-  0x6dce88aa, 0x2cb2324c, 0x6dd74e73, 0x2ca932ef,
-  0x6de01278, 0x2ca031da, 0x6de8d4b8, 0x2c972f0d,
-  0x6df19534, 0x2c8e2a87, 0x6dfa53e9, 0x2c85244a,
-  0x6e0310d9, 0x2c7c1c55, 0x6e0bcc03, 0x2c7312a9,
-  0x6e148566, 0x2c6a0746, 0x6e1d3d03, 0x2c60fa2d,
-  0x6e25f2d8, 0x2c57eb5e, 0x6e2ea6e6, 0x2c4edada,
-  0x6e37592c, 0x2c45c8a0, 0x6e4009aa, 0x2c3cb4b1,
-  0x6e48b860, 0x2c339f0e, 0x6e51654c, 0x2c2a87b6,
-  0x6e5a1070, 0x2c216eaa, 0x6e62b9ca, 0x2c1853eb,
-  0x6e6b615a, 0x2c0f3779, 0x6e740720, 0x2c061953,
-  0x6e7cab1c, 0x2bfcf97c, 0x6e854d4d, 0x2bf3d7f2,
-  0x6e8dedb3, 0x2beab4b6, 0x6e968c4d, 0x2be18fc9,
-  0x6e9f291b, 0x2bd8692b, 0x6ea7c41e, 0x2bcf40dc,
-  0x6eb05d53, 0x2bc616dd, 0x6eb8f4bc, 0x2bbceb2d,
-  0x6ec18a58, 0x2bb3bdce, 0x6eca1e27, 0x2baa8ec0,
-  0x6ed2b027, 0x2ba15e03, 0x6edb405a, 0x2b982b97,
-  0x6ee3cebe, 0x2b8ef77d, 0x6eec5b53, 0x2b85c1b5,
-  0x6ef4e619, 0x2b7c8a3f, 0x6efd6f10, 0x2b73511c,
-  0x6f05f637, 0x2b6a164d, 0x6f0e7b8e, 0x2b60d9d0,
-  0x6f16ff14, 0x2b579ba8, 0x6f1f80ca, 0x2b4e5bd4,
-  0x6f2800af, 0x2b451a55, 0x6f307ec2, 0x2b3bd72a,
-  0x6f38fb03, 0x2b329255, 0x6f417573, 0x2b294bd5,
-  0x6f49ee0f, 0x2b2003ac, 0x6f5264da, 0x2b16b9d9,
-  0x6f5ad9d1, 0x2b0d6e5c, 0x6f634cf5, 0x2b042137,
-  0x6f6bbe45, 0x2afad269, 0x6f742dc1, 0x2af181f3,
-  0x6f7c9b69, 0x2ae82fd5, 0x6f85073c, 0x2adedc10,
-  0x6f8d713a, 0x2ad586a3, 0x6f95d963, 0x2acc2f90,
-  0x6f9e3fb6, 0x2ac2d6d6, 0x6fa6a433, 0x2ab97c77,
-  0x6faf06da, 0x2ab02071, 0x6fb767aa, 0x2aa6c2c6,
-  0x6fbfc6a3, 0x2a9d6377, 0x6fc823c5, 0x2a940283,
-  0x6fd07f0f, 0x2a8a9fea, 0x6fd8d882, 0x2a813bae,
-  0x6fe1301c, 0x2a77d5ce, 0x6fe985de, 0x2a6e6e4b,
-  0x6ff1d9c7, 0x2a650525, 0x6ffa2bd6, 0x2a5b9a5d,
-  0x70027c0c, 0x2a522df3, 0x700aca69, 0x2a48bfe7,
-  0x701316eb, 0x2a3f503a, 0x701b6193, 0x2a35deeb,
-  0x7023aa5f, 0x2a2c6bfd, 0x702bf151, 0x2a22f76e,
-  0x70343667, 0x2a19813f, 0x703c79a2, 0x2a100970,
-  0x7044bb00, 0x2a069003, 0x704cfa83, 0x29fd14f6,
-  0x70553828, 0x29f3984c, 0x705d73f0, 0x29ea1a03,
-  0x7065addb, 0x29e09a1c, 0x706de5e9, 0x29d71899,
-  0x70761c18, 0x29cd9578, 0x707e5069, 0x29c410ba,
-  0x708682dc, 0x29ba8a61, 0x708eb36f, 0x29b1026c,
-  0x7096e223, 0x29a778db, 0x709f0ef8, 0x299dedaf,
-  0x70a739ed, 0x299460e8, 0x70af6302, 0x298ad287,
-  0x70b78a36, 0x2981428c, 0x70bfaf89, 0x2977b0f7,
-  0x70c7d2fb, 0x296e1dc9, 0x70cff48c, 0x29648902,
-  0x70d8143b, 0x295af2a3, 0x70e03208, 0x29515aab,
-  0x70e84df3, 0x2947c11c, 0x70f067fb, 0x293e25f5,
-  0x70f8801f, 0x29348937, 0x71009661, 0x292aeae3,
-  0x7108aabf, 0x29214af8, 0x7110bd39, 0x2917a977,
-  0x7118cdcf, 0x290e0661, 0x7120dc80, 0x290461b5,
-  0x7128e94c, 0x28fabb75, 0x7130f433, 0x28f113a0,
-  0x7138fd35, 0x28e76a37, 0x71410450, 0x28ddbf3b,
-  0x71490986, 0x28d412ab, 0x71510cd5, 0x28ca6488,
-  0x71590e3e, 0x28c0b4d2, 0x71610dbf, 0x28b7038b,
-  0x71690b59, 0x28ad50b1, 0x7171070c, 0x28a39c46,
-  0x717900d6, 0x2899e64a, 0x7180f8b8, 0x28902ebd,
-  0x7188eeb2, 0x288675a0, 0x7190e2c3, 0x287cbaf3,
-  0x7198d4ea, 0x2872feb6, 0x71a0c528, 0x286940ea,
-  0x71a8b37c, 0x285f8190, 0x71b09fe7, 0x2855c0a6,
-  0x71b88a66, 0x284bfe2f, 0x71c072fb, 0x28423a2a,
-  0x71c859a5, 0x28387498, 0x71d03e64, 0x282ead78,
-  0x71d82137, 0x2824e4cc, 0x71e0021e, 0x281b1a94,
-  0x71e7e118, 0x28114ed0, 0x71efbe27, 0x28078181,
-  0x71f79948, 0x27fdb2a7, 0x71ff727c, 0x27f3e241,
-  0x720749c3, 0x27ea1052, 0x720f1f1c, 0x27e03cd8,
-  0x7216f287, 0x27d667d5, 0x721ec403, 0x27cc9149,
-  0x72269391, 0x27c2b934, 0x722e6130, 0x27b8df97,
-  0x72362ce0, 0x27af0472, 0x723df6a0, 0x27a527c4,
-  0x7245be70, 0x279b4990, 0x724d8450, 0x279169d5,
-  0x72554840, 0x27878893, 0x725d0a3e, 0x277da5cb,
-  0x7264ca4c, 0x2773c17d, 0x726c8868, 0x2769dbaa,
-  0x72744493, 0x275ff452, 0x727bfecc, 0x27560b76,
-  0x7283b712, 0x274c2115, 0x728b6d66, 0x27423530,
-  0x729321c7, 0x273847c8, 0x729ad435, 0x272e58dc,
-  0x72a284b0, 0x2724686e, 0x72aa3336, 0x271a767e,
-  0x72b1dfc9, 0x2710830c, 0x72b98a67, 0x27068e18,
-  0x72c13311, 0x26fc97a3, 0x72c8d9c6, 0x26f29fad,
-  0x72d07e85, 0x26e8a637, 0x72d82150, 0x26deab41,
-  0x72dfc224, 0x26d4aecb, 0x72e76102, 0x26cab0d6,
-  0x72eefdea, 0x26c0b162, 0x72f698db, 0x26b6b070,
-  0x72fe31d5, 0x26acadff, 0x7305c8d7, 0x26a2aa11,
-  0x730d5de3, 0x2698a4a6, 0x7314f0f6, 0x268e9dbd,
-  0x731c8211, 0x26849558, 0x73241134, 0x267a8b77,
-  0x732b9e5e, 0x2670801a, 0x7333298f, 0x26667342,
-  0x733ab2c6, 0x265c64ef, 0x73423a04, 0x26525521,
-  0x7349bf48, 0x264843d9, 0x73514292, 0x263e3117,
-  0x7358c3e2, 0x26341cdb, 0x73604336, 0x262a0727,
-  0x7367c090, 0x261feffa, 0x736f3bee, 0x2615d754,
-  0x7376b551, 0x260bbd37, 0x737e2cb7, 0x2601a1a2,
-  0x7385a222, 0x25f78497, 0x738d1590, 0x25ed6614,
-  0x73948701, 0x25e3461b, 0x739bf675, 0x25d924ac,
-  0x73a363ec, 0x25cf01c8, 0x73aacf65, 0x25c4dd6e,
-  0x73b238e0, 0x25bab7a0, 0x73b9a05d, 0x25b0905d,
-  0x73c105db, 0x25a667a7, 0x73c8695b, 0x259c3d7c,
-  0x73cfcadc, 0x259211df, 0x73d72a5d, 0x2587e4cf,
-  0x73de87de, 0x257db64c, 0x73e5e360, 0x25738657,
-  0x73ed3ce1, 0x256954f1, 0x73f49462, 0x255f2219,
-  0x73fbe9e2, 0x2554edd1, 0x74033d61, 0x254ab818,
-  0x740a8edf, 0x254080ef, 0x7411de5b, 0x25364857,
-  0x74192bd5, 0x252c0e4f, 0x7420774d, 0x2521d2d8,
-  0x7427c0c3, 0x251795f3, 0x742f0836, 0x250d57a0,
-  0x74364da6, 0x250317df, 0x743d9112, 0x24f8d6b0,
-  0x7444d27b, 0x24ee9415, 0x744c11e0, 0x24e4500e,
-  0x74534f41, 0x24da0a9a, 0x745a8a9d, 0x24cfc3ba,
-  0x7461c3f5, 0x24c57b6f, 0x7468fb47, 0x24bb31ba,
-  0x74703095, 0x24b0e699, 0x747763dd, 0x24a69a0f,
-  0x747e951f, 0x249c4c1b, 0x7485c45b, 0x2491fcbe,
-  0x748cf190, 0x2487abf7, 0x74941cbf, 0x247d59c8,
-  0x749b45e7, 0x24730631, 0x74a26d08, 0x2468b132,
-  0x74a99221, 0x245e5acc, 0x74b0b533, 0x245402ff,
-  0x74b7d63c, 0x2449a9cc, 0x74bef53d, 0x243f4f32,
-  0x74c61236, 0x2434f332, 0x74cd2d26, 0x242a95ce,
-  0x74d4460c, 0x24203704, 0x74db5cea, 0x2415d6d5,
-  0x74e271bd, 0x240b7543, 0x74e98487, 0x2401124d,
-  0x74f09546, 0x23f6adf3, 0x74f7a3fb, 0x23ec4837,
-  0x74feb0a5, 0x23e1e117, 0x7505bb44, 0x23d77896,
-  0x750cc3d8, 0x23cd0eb3, 0x7513ca60, 0x23c2a36f,
-  0x751acedd, 0x23b836ca, 0x7521d14d, 0x23adc8c4,
-  0x7528d1b1, 0x23a3595e, 0x752fd008, 0x2398e898,
-  0x7536cc52, 0x238e7673, 0x753dc68f, 0x238402ef,
-  0x7544bebf, 0x23798e0d, 0x754bb4e1, 0x236f17cc,
-  0x7552a8f4, 0x2364a02e, 0x75599afa, 0x235a2733,
-  0x75608af1, 0x234facda, 0x756778d9, 0x23453125,
-  0x756e64b2, 0x233ab414, 0x75754e7c, 0x233035a7,
-  0x757c3636, 0x2325b5df, 0x75831be0, 0x231b34bc,
-  0x7589ff7a, 0x2310b23e, 0x7590e104, 0x23062e67,
-  0x7597c07d, 0x22fba936, 0x759e9de5, 0x22f122ab,
-  0x75a5793c, 0x22e69ac8, 0x75ac5282, 0x22dc118c,
-  0x75b329b5, 0x22d186f8, 0x75b9fed7, 0x22c6fb0c,
-  0x75c0d1e7, 0x22bc6dca, 0x75c7a2e3, 0x22b1df30,
-  0x75ce71ce, 0x22a74f40, 0x75d53ea5, 0x229cbdfa,
-  0x75dc0968, 0x22922b5e, 0x75e2d219, 0x2287976e,
-  0x75e998b5, 0x227d0228, 0x75f05d3d, 0x22726b8e,
-  0x75f71fb1, 0x2267d3a0, 0x75fde011, 0x225d3a5e,
-  0x76049e5b, 0x22529fca, 0x760b5a90, 0x224803e2,
-  0x761214b0, 0x223d66a8, 0x7618ccba, 0x2232c81c,
-  0x761f82af, 0x2228283f, 0x7626368d, 0x221d8711,
-  0x762ce855, 0x2212e492, 0x76339806, 0x220840c2,
-  0x763a45a0, 0x21fd9ba3, 0x7640f123, 0x21f2f534,
-  0x76479a8e, 0x21e84d76, 0x764e41e2, 0x21dda46a,
-  0x7654e71d, 0x21d2fa0f, 0x765b8a41, 0x21c84e67,
-  0x76622b4c, 0x21bda171, 0x7668ca3e, 0x21b2f32e,
-  0x766f6717, 0x21a8439e, 0x767601d7, 0x219d92c2,
-  0x767c9a7e, 0x2192e09b, 0x7683310b, 0x21882d28,
-  0x7689c57d, 0x217d786a, 0x769057d6, 0x2172c262,
-  0x7696e814, 0x21680b0f, 0x769d7637, 0x215d5273,
-  0x76a4023f, 0x2152988d, 0x76aa8c2c, 0x2147dd5f,
-  0x76b113fd, 0x213d20e8, 0x76b799b3, 0x21326329,
-  0x76be1d4c, 0x2127a423, 0x76c49ec9, 0x211ce3d5,
-  0x76cb1e2a, 0x21122240, 0x76d19b6e, 0x21075f65,
-  0x76d81695, 0x20fc9b44, 0x76de8f9e, 0x20f1d5de,
-  0x76e5068a, 0x20e70f32, 0x76eb7b58, 0x20dc4742,
-  0x76f1ee09, 0x20d17e0d, 0x76f85e9a, 0x20c6b395,
-  0x76fecd0e, 0x20bbe7d8, 0x77053962, 0x20b11ad9,
-  0x770ba398, 0x20a64c97, 0x77120bae, 0x209b7d13,
-  0x771871a5, 0x2090ac4d, 0x771ed57c, 0x2085da46,
-  0x77253733, 0x207b06fe, 0x772b96ca, 0x20703275,
-  0x7731f440, 0x20655cac, 0x77384f95, 0x205a85a3,
-  0x773ea8ca, 0x204fad5b, 0x7744ffdd, 0x2044d3d4,
-  0x774b54ce, 0x2039f90f, 0x7751a79e, 0x202f1d0b,
-  0x7757f84c, 0x20243fca, 0x775e46d8, 0x2019614c,
-  0x77649341, 0x200e8190, 0x776add88, 0x2003a099,
-  0x777125ac, 0x1ff8be65, 0x77776bac, 0x1feddaf6,
-  0x777daf89, 0x1fe2f64c, 0x7783f143, 0x1fd81067,
-  0x778a30d8, 0x1fcd2948, 0x77906e49, 0x1fc240ef,
-  0x7796a996, 0x1fb7575c, 0x779ce2be, 0x1fac6c91,
-  0x77a319c2, 0x1fa1808c, 0x77a94ea0, 0x1f969350,
-  0x77af8159, 0x1f8ba4dc, 0x77b5b1ec, 0x1f80b531,
-  0x77bbe05a, 0x1f75c44e, 0x77c20ca1, 0x1f6ad235,
-  0x77c836c2, 0x1f5fdee6, 0x77ce5ebd, 0x1f54ea62,
-  0x77d48490, 0x1f49f4a8, 0x77daa83d, 0x1f3efdb9,
-  0x77e0c9c3, 0x1f340596, 0x77e6e921, 0x1f290c3f,
-  0x77ed0657, 0x1f1e11b5, 0x77f32165, 0x1f1315f7,
-  0x77f93a4b, 0x1f081907, 0x77ff5109, 0x1efd1ae4,
-  0x7805659e, 0x1ef21b90, 0x780b780a, 0x1ee71b0a,
-  0x7811884d, 0x1edc1953, 0x78179666, 0x1ed1166b,
-  0x781da256, 0x1ec61254, 0x7823ac1d, 0x1ebb0d0d,
-  0x7829b3b9, 0x1eb00696, 0x782fb92a, 0x1ea4fef0,
-  0x7835bc71, 0x1e99f61d, 0x783bbd8e, 0x1e8eec1b,
-  0x7841bc7f, 0x1e83e0eb, 0x7847b946, 0x1e78d48e,
-  0x784db3e0, 0x1e6dc705, 0x7853ac4f, 0x1e62b84f,
-  0x7859a292, 0x1e57a86d, 0x785f96a9, 0x1e4c9760,
-  0x78658894, 0x1e418528, 0x786b7852, 0x1e3671c5,
-  0x787165e3, 0x1e2b5d38, 0x78775147, 0x1e204781,
-  0x787d3a7e, 0x1e1530a1, 0x78832187, 0x1e0a1898,
-  0x78890663, 0x1dfeff67, 0x788ee910, 0x1df3e50d,
-  0x7894c98f, 0x1de8c98c, 0x789aa7e0, 0x1dddace4,
-  0x78a08402, 0x1dd28f15, 0x78a65df6, 0x1dc7701f,
-  0x78ac35ba, 0x1dbc5004, 0x78b20b4f, 0x1db12ec3,
-  0x78b7deb4, 0x1da60c5d, 0x78bdafea, 0x1d9ae8d2,
-  0x78c37eef, 0x1d8fc424, 0x78c94bc4, 0x1d849e51,
-  0x78cf1669, 0x1d79775c, 0x78d4dedd, 0x1d6e4f43,
-  0x78daa520, 0x1d632608, 0x78e06932, 0x1d57fbaa,
-  0x78e62b13, 0x1d4cd02c, 0x78ebeac2, 0x1d41a38c,
-  0x78f1a840, 0x1d3675cb, 0x78f7638b, 0x1d2b46ea,
-  0x78fd1ca4, 0x1d2016e9, 0x7902d38b, 0x1d14e5c9,
-  0x7908883f, 0x1d09b389, 0x790e3ac0, 0x1cfe802b,
-  0x7913eb0e, 0x1cf34baf, 0x79199929, 0x1ce81615,
-  0x791f4510, 0x1cdcdf5e, 0x7924eec3, 0x1cd1a78a,
-  0x792a9642, 0x1cc66e99, 0x79303b8e, 0x1cbb348d,
-  0x7935dea4, 0x1caff965, 0x793b7f86, 0x1ca4bd21,
-  0x79411e33, 0x1c997fc4, 0x7946baac, 0x1c8e414b,
-  0x794c54ee, 0x1c8301b9, 0x7951ecfc, 0x1c77c10e,
-  0x795782d3, 0x1c6c7f4a, 0x795d1675, 0x1c613c6d,
-  0x7962a7e0, 0x1c55f878, 0x79683715, 0x1c4ab36b,
-  0x796dc414, 0x1c3f6d47, 0x79734edc, 0x1c34260c,
-  0x7978d76c, 0x1c28ddbb, 0x797e5dc6, 0x1c1d9454,
-  0x7983e1e8, 0x1c1249d8, 0x798963d2, 0x1c06fe46,
-  0x798ee385, 0x1bfbb1a0, 0x799460ff, 0x1bf063e6,
-  0x7999dc42, 0x1be51518, 0x799f554b, 0x1bd9c537,
-  0x79a4cc1c, 0x1bce7442, 0x79aa40b4, 0x1bc3223c,
-  0x79afb313, 0x1bb7cf23, 0x79b52339, 0x1bac7af9,
-  0x79ba9125, 0x1ba125bd, 0x79bffcd7, 0x1b95cf71,
-  0x79c5664f, 0x1b8a7815, 0x79cacd8d, 0x1b7f1fa9,
-  0x79d03291, 0x1b73c62d, 0x79d5955a, 0x1b686ba3,
-  0x79daf5e8, 0x1b5d100a, 0x79e0543c, 0x1b51b363,
-  0x79e5b054, 0x1b4655ae, 0x79eb0a31, 0x1b3af6ec,
-  0x79f061d2, 0x1b2f971e, 0x79f5b737, 0x1b243643,
-  0x79fb0a60, 0x1b18d45c, 0x7a005b4d, 0x1b0d716a,
-  0x7a05a9fd, 0x1b020d6c, 0x7a0af671, 0x1af6a865,
-  0x7a1040a8, 0x1aeb4253, 0x7a1588a2, 0x1adfdb37,
-  0x7a1ace5f, 0x1ad47312, 0x7a2011de, 0x1ac909e5,
-  0x7a25531f, 0x1abd9faf, 0x7a2a9223, 0x1ab23471,
-  0x7a2fcee8, 0x1aa6c82b, 0x7a350970, 0x1a9b5adf,
-  0x7a3a41b9, 0x1a8fec8c, 0x7a3f77c3, 0x1a847d33,
-  0x7a44ab8e, 0x1a790cd4, 0x7a49dd1a, 0x1a6d9b70,
-  0x7a4f0c67, 0x1a622907, 0x7a543974, 0x1a56b599,
-  0x7a596442, 0x1a4b4128, 0x7a5e8cd0, 0x1a3fcbb3,
-  0x7a63b31d, 0x1a34553b, 0x7a68d72b, 0x1a28ddc0,
-  0x7a6df8f8, 0x1a1d6544, 0x7a731884, 0x1a11ebc5,
-  0x7a7835cf, 0x1a067145, 0x7a7d50da, 0x19faf5c5,
-  0x7a8269a3, 0x19ef7944, 0x7a87802a, 0x19e3fbc3,
-  0x7a8c9470, 0x19d87d42, 0x7a91a674, 0x19ccfdc2,
-  0x7a96b636, 0x19c17d44, 0x7a9bc3b6, 0x19b5fbc8,
-  0x7aa0cef3, 0x19aa794d, 0x7aa5d7ee, 0x199ef5d6,
-  0x7aaadea6, 0x19937161, 0x7aafe31b, 0x1987ebf0,
-  0x7ab4e54c, 0x197c6584, 0x7ab9e53a, 0x1970de1b,
-  0x7abee2e5, 0x196555b8, 0x7ac3de4c, 0x1959cc5a,
-  0x7ac8d76f, 0x194e4201, 0x7acdce4d, 0x1942b6af,
-  0x7ad2c2e8, 0x19372a64, 0x7ad7b53d, 0x192b9d1f,
-  0x7adca54e, 0x19200ee3, 0x7ae1931a, 0x19147fae,
-  0x7ae67ea1, 0x1908ef82, 0x7aeb67e3, 0x18fd5e5f,
-  0x7af04edf, 0x18f1cc45, 0x7af53395, 0x18e63935,
-  0x7afa1605, 0x18daa52f, 0x7afef630, 0x18cf1034,
-  0x7b03d414, 0x18c37a44, 0x7b08afb2, 0x18b7e35f,
-  0x7b0d8909, 0x18ac4b87, 0x7b126019, 0x18a0b2bb,
-  0x7b1734e2, 0x189518fc, 0x7b1c0764, 0x18897e4a,
-  0x7b20d79e, 0x187de2a7, 0x7b25a591, 0x18724611,
-  0x7b2a713d, 0x1866a88a, 0x7b2f3aa0, 0x185b0a13,
-  0x7b3401bb, 0x184f6aab, 0x7b38c68e, 0x1843ca53,
-  0x7b3d8918, 0x1838290c, 0x7b42495a, 0x182c86d5,
-  0x7b470753, 0x1820e3b0, 0x7b4bc303, 0x18153f9d,
-  0x7b507c69, 0x18099a9c, 0x7b553386, 0x17fdf4ae,
-  0x7b59e85a, 0x17f24dd3, 0x7b5e9ae4, 0x17e6a60c,
-  0x7b634b23, 0x17dafd59, 0x7b67f919, 0x17cf53bb,
-  0x7b6ca4c4, 0x17c3a931, 0x7b714e25, 0x17b7fdbd,
-  0x7b75f53c, 0x17ac515f, 0x7b7a9a07, 0x17a0a417,
-  0x7b7f3c87, 0x1794f5e6, 0x7b83dcbc, 0x178946cc,
-  0x7b887aa6, 0x177d96ca, 0x7b8d1644, 0x1771e5e0,
-  0x7b91af97, 0x1766340f, 0x7b96469d, 0x175a8157,
-  0x7b9adb57, 0x174ecdb8, 0x7b9f6dc5, 0x17431933,
-  0x7ba3fde7, 0x173763c9, 0x7ba88bbc, 0x172bad7a,
-  0x7bad1744, 0x171ff646, 0x7bb1a080, 0x17143e2d,
-  0x7bb6276e, 0x17088531, 0x7bbaac0e, 0x16fccb51,
-  0x7bbf2e62, 0x16f1108f, 0x7bc3ae67, 0x16e554ea,
-  0x7bc82c1f, 0x16d99864, 0x7bcca789, 0x16cddafb,
-  0x7bd120a4, 0x16c21cb2, 0x7bd59771, 0x16b65d88,
-  0x7bda0bf0, 0x16aa9d7e, 0x7bde7e20, 0x169edc94,
-  0x7be2ee01, 0x16931acb, 0x7be75b93, 0x16875823,
-  0x7bebc6d5, 0x167b949d, 0x7bf02fc9, 0x166fd039,
-  0x7bf4966c, 0x16640af7, 0x7bf8fac0, 0x165844d8,
-  0x7bfd5cc4, 0x164c7ddd, 0x7c01bc78, 0x1640b606,
-  0x7c0619dc, 0x1634ed53, 0x7c0a74f0, 0x162923c5,
-  0x7c0ecdb2, 0x161d595d, 0x7c132424, 0x16118e1a,
-  0x7c177845, 0x1605c1fd, 0x7c1bca16, 0x15f9f507,
-  0x7c201994, 0x15ee2738, 0x7c2466c2, 0x15e25890,
-  0x7c28b19e, 0x15d68911, 0x7c2cfa28, 0x15cab8ba,
-  0x7c314060, 0x15bee78c, 0x7c358446, 0x15b31587,
-  0x7c39c5da, 0x15a742ac, 0x7c3e051b, 0x159b6efb,
-  0x7c42420a, 0x158f9a76, 0x7c467ca6, 0x1583c51b,
-  0x7c4ab4ef, 0x1577eeec, 0x7c4eeae5, 0x156c17e9,
-  0x7c531e88, 0x15604013, 0x7c574fd8, 0x1554676a,
-  0x7c5b7ed4, 0x15488dee, 0x7c5fab7c, 0x153cb3a0,
-  0x7c63d5d1, 0x1530d881, 0x7c67fdd1, 0x1524fc90,
-  0x7c6c237e, 0x15191fcf, 0x7c7046d6, 0x150d423d,
-  0x7c7467d9, 0x150163dc, 0x7c788688, 0x14f584ac,
-  0x7c7ca2e2, 0x14e9a4ac, 0x7c80bce7, 0x14ddc3de,
-  0x7c84d496, 0x14d1e242, 0x7c88e9f1, 0x14c5ffd9,
-  0x7c8cfcf6, 0x14ba1ca3, 0x7c910da5, 0x14ae38a0,
-  0x7c951bff, 0x14a253d1, 0x7c992803, 0x14966e36,
-  0x7c9d31b0, 0x148a87d1, 0x7ca13908, 0x147ea0a0,
-  0x7ca53e09, 0x1472b8a5, 0x7ca940b3, 0x1466cfe1,
-  0x7cad4107, 0x145ae653, 0x7cb13f04, 0x144efbfc,
-  0x7cb53aaa, 0x144310dd, 0x7cb933f9, 0x143724f5,
-  0x7cbd2af0, 0x142b3846, 0x7cc11f90, 0x141f4ad1,
-  0x7cc511d9, 0x14135c94, 0x7cc901c9, 0x14076d91,
-  0x7cccef62, 0x13fb7dc9, 0x7cd0daa2, 0x13ef8d3c,
-  0x7cd4c38b, 0x13e39be9, 0x7cd8aa1b, 0x13d7a9d3,
-  0x7cdc8e52, 0x13cbb6f8, 0x7ce07031, 0x13bfc35b,
-  0x7ce44fb7, 0x13b3cefa, 0x7ce82ce4, 0x13a7d9d7,
-  0x7cec07b8, 0x139be3f2, 0x7cefe032, 0x138fed4b,
-  0x7cf3b653, 0x1383f5e3, 0x7cf78a1b, 0x1377fdbb,
-  0x7cfb5b89, 0x136c04d2, 0x7cff2a9d, 0x13600b2a,
-  0x7d02f757, 0x135410c3, 0x7d06c1b6, 0x1348159d,
-  0x7d0a89bc, 0x133c19b8, 0x7d0e4f67, 0x13301d16,
-  0x7d1212b7, 0x13241fb6, 0x7d15d3ad, 0x1318219a,
-  0x7d199248, 0x130c22c1, 0x7d1d4e88, 0x1300232c,
-  0x7d21086c, 0x12f422db, 0x7d24bff6, 0x12e821cf,
-  0x7d287523, 0x12dc2009, 0x7d2c27f6, 0x12d01d89,
-  0x7d2fd86c, 0x12c41a4f, 0x7d338687, 0x12b8165b,
-  0x7d373245, 0x12ac11af, 0x7d3adba7, 0x12a00c4b,
-  0x7d3e82ae, 0x1294062f, 0x7d422757, 0x1287ff5b,
-  0x7d45c9a4, 0x127bf7d1, 0x7d496994, 0x126fef90,
-  0x7d4d0728, 0x1263e699, 0x7d50a25e, 0x1257dced,
-  0x7d543b37, 0x124bd28c, 0x7d57d1b3, 0x123fc776,
-  0x7d5b65d2, 0x1233bbac, 0x7d5ef793, 0x1227af2e,
-  0x7d6286f6, 0x121ba1fd, 0x7d6613fb, 0x120f941a,
-  0x7d699ea3, 0x12038584, 0x7d6d26ec, 0x11f7763c,
-  0x7d70acd7, 0x11eb6643, 0x7d743064, 0x11df5599,
-  0x7d77b192, 0x11d3443f, 0x7d7b3061, 0x11c73235,
-  0x7d7eacd2, 0x11bb1f7c, 0x7d8226e4, 0x11af0c13,
-  0x7d859e96, 0x11a2f7fc, 0x7d8913ea, 0x1196e337,
-  0x7d8c86de, 0x118acdc4, 0x7d8ff772, 0x117eb7a4,
-  0x7d9365a8, 0x1172a0d7, 0x7d96d17d, 0x1166895f,
-  0x7d9a3af2, 0x115a713a, 0x7d9da208, 0x114e586a,
-  0x7da106bd, 0x11423ef0, 0x7da46912, 0x113624cb,
-  0x7da7c907, 0x112a09fc, 0x7dab269b, 0x111dee84,
-  0x7dae81cf, 0x1111d263, 0x7db1daa2, 0x1105b599,
-  0x7db53113, 0x10f99827, 0x7db88524, 0x10ed7a0e,
-  0x7dbbd6d4, 0x10e15b4e, 0x7dbf2622, 0x10d53be7,
-  0x7dc2730f, 0x10c91bda, 0x7dc5bd9b, 0x10bcfb28,
-  0x7dc905c5, 0x10b0d9d0, 0x7dcc4b8d, 0x10a4b7d3,
-  0x7dcf8ef3, 0x10989532, 0x7dd2cff7, 0x108c71ee,
-  0x7dd60e99, 0x10804e06, 0x7dd94ad8, 0x1074297b,
-  0x7ddc84b5, 0x1068044e, 0x7ddfbc30, 0x105bde7f,
-  0x7de2f148, 0x104fb80e, 0x7de623fd, 0x104390fd,
-  0x7de9544f, 0x1037694b, 0x7dec823e, 0x102b40f8,
-  0x7defadca, 0x101f1807, 0x7df2d6f3, 0x1012ee76,
-  0x7df5fdb8, 0x1006c446, 0x7df9221a, 0xffa9979,
-  0x7dfc4418, 0xfee6e0d, 0x7dff63b2, 0xfe24205,
-  0x7e0280e9, 0xfd6155f, 0x7e059bbb, 0xfc9e81e,
-  0x7e08b42a, 0xfbdba40, 0x7e0bca34, 0xfb18bc8,
-  0x7e0eddd9, 0xfa55cb4, 0x7e11ef1b, 0xf992d06,
-  0x7e14fdf7, 0xf8cfcbe, 0x7e180a6f, 0xf80cbdc,
-  0x7e1b1482, 0xf749a61, 0x7e1e1c30, 0xf68684e,
-  0x7e212179, 0xf5c35a3, 0x7e24245d, 0xf500260,
-  0x7e2724db, 0xf43ce86, 0x7e2a22f4, 0xf379a16,
-  0x7e2d1ea8, 0xf2b650f, 0x7e3017f6, 0xf1f2f73,
-  0x7e330ede, 0xf12f941, 0x7e360360, 0xf06c27a,
-  0x7e38f57c, 0xefa8b20, 0x7e3be532, 0xeee5331,
-  0x7e3ed282, 0xee21aaf, 0x7e41bd6c, 0xed5e19a,
-  0x7e44a5ef, 0xec9a7f3, 0x7e478c0b, 0xebd6db9,
-  0x7e4a6fc1, 0xeb132ef, 0x7e4d5110, 0xea4f793,
-  0x7e502ff9, 0xe98bba7, 0x7e530c7a, 0xe8c7f2a,
-  0x7e55e694, 0xe80421e, 0x7e58be47, 0xe740483,
-  0x7e5b9392, 0xe67c65a, 0x7e5e6676, 0xe5b87a2,
-  0x7e6136f3, 0xe4f485c, 0x7e640507, 0xe430889,
-  0x7e66d0b4, 0xe36c82a, 0x7e6999fa, 0xe2a873e,
-  0x7e6c60d7, 0xe1e45c6, 0x7e6f254c, 0xe1203c3,
-  0x7e71e759, 0xe05c135, 0x7e74a6fd, 0xdf97e1d,
-  0x7e77643a, 0xded3a7b, 0x7e7a1f0d, 0xde0f64f,
-  0x7e7cd778, 0xdd4b19a, 0x7e7f8d7b, 0xdc86c5d,
-  0x7e824114, 0xdbc2698, 0x7e84f245, 0xdafe04b,
-  0x7e87a10c, 0xda39978, 0x7e8a4d6a, 0xd97521d,
-  0x7e8cf75f, 0xd8b0a3d, 0x7e8f9eeb, 0xd7ec1d6,
-  0x7e92440d, 0xd7278eb, 0x7e94e6c6, 0xd662f7b,
-  0x7e978715, 0xd59e586, 0x7e9a24fb, 0xd4d9b0e,
-  0x7e9cc076, 0xd415013, 0x7e9f5988, 0xd350495,
-  0x7ea1f02f, 0xd28b894, 0x7ea4846c, 0xd1c6c11,
-  0x7ea7163f, 0xd101f0e, 0x7ea9a5a8, 0xd03d189,
-  0x7eac32a6, 0xcf78383, 0x7eaebd3a, 0xceb34fe,
-  0x7eb14563, 0xcdee5f9, 0x7eb3cb21, 0xcd29676,
-  0x7eb64e75, 0xcc64673, 0x7eb8cf5d, 0xcb9f5f3,
-  0x7ebb4ddb, 0xcada4f5, 0x7ebdc9ed, 0xca1537a,
-  0x7ec04394, 0xc950182, 0x7ec2bad0, 0xc88af0e,
-  0x7ec52fa0, 0xc7c5c1e, 0x7ec7a205, 0xc7008b3,
-  0x7eca11fe, 0xc63b4ce, 0x7ecc7f8b, 0xc57606e,
-  0x7eceeaad, 0xc4b0b94, 0x7ed15363, 0xc3eb641,
-  0x7ed3b9ad, 0xc326075, 0x7ed61d8a, 0xc260a31,
-  0x7ed87efc, 0xc19b374, 0x7edade01, 0xc0d5c41,
-  0x7edd3a9a, 0xc010496, 0x7edf94c7, 0xbf4ac75,
-  0x7ee1ec87, 0xbe853de, 0x7ee441da, 0xbdbfad1,
-  0x7ee694c1, 0xbcfa150, 0x7ee8e53a, 0xbc34759,
-  0x7eeb3347, 0xbb6ecef, 0x7eed7ee7, 0xbaa9211,
-  0x7eefc81a, 0xb9e36c0, 0x7ef20ee0, 0xb91dafc,
-  0x7ef45338, 0xb857ec7, 0x7ef69523, 0xb79221f,
-  0x7ef8d4a1, 0xb6cc506, 0x7efb11b1, 0xb60677c,
-  0x7efd4c54, 0xb540982, 0x7eff8489, 0xb47ab19,
-  0x7f01ba50, 0xb3b4c40, 0x7f03eda9, 0xb2eecf8,
-  0x7f061e95, 0xb228d42, 0x7f084d12, 0xb162d1d,
-  0x7f0a7921, 0xb09cc8c, 0x7f0ca2c2, 0xafd6b8d,
-  0x7f0ec9f5, 0xaf10a22, 0x7f10eeb9, 0xae4a84b,
-  0x7f13110f, 0xad84609, 0x7f1530f7, 0xacbe35b,
-  0x7f174e70, 0xabf8043, 0x7f19697a, 0xab31cc1,
-  0x7f1b8215, 0xaa6b8d5, 0x7f1d9842, 0xa9a5480,
-  0x7f1fabff, 0xa8defc3, 0x7f21bd4e, 0xa818a9d,
-  0x7f23cc2e, 0xa752510, 0x7f25d89e, 0xa68bf1b,
-  0x7f27e29f, 0xa5c58c0, 0x7f29ea31, 0xa4ff1fe,
-  0x7f2bef53, 0xa438ad7, 0x7f2df206, 0xa37234a,
-  0x7f2ff24a, 0xa2abb59, 0x7f31f01d, 0xa1e5303,
-  0x7f33eb81, 0xa11ea49, 0x7f35e476, 0xa05812c,
-  0x7f37dafa, 0x9f917ac, 0x7f39cf0e, 0x9ecadc9,
-  0x7f3bc0b3, 0x9e04385, 0x7f3dafe7, 0x9d3d8df,
-  0x7f3f9cab, 0x9c76dd8, 0x7f4186ff, 0x9bb0271,
-  0x7f436ee3, 0x9ae96aa, 0x7f455456, 0x9a22a83,
-  0x7f473759, 0x995bdfd, 0x7f4917eb, 0x9895118,
-  0x7f4af60d, 0x97ce3d5, 0x7f4cd1be, 0x9707635,
-  0x7f4eaafe, 0x9640837, 0x7f5081cd, 0x95799dd,
-  0x7f52562c, 0x94b2b27, 0x7f54281a, 0x93ebc14,
-  0x7f55f796, 0x9324ca7, 0x7f57c4a2, 0x925dcdf,
-  0x7f598f3c, 0x9196cbc, 0x7f5b5765, 0x90cfc40,
-  0x7f5d1d1d, 0x9008b6a, 0x7f5ee063, 0x8f41a3c,
-  0x7f60a138, 0x8e7a8b5, 0x7f625f9b, 0x8db36d6,
-  0x7f641b8d, 0x8cec4a0, 0x7f65d50d, 0x8c25213,
-  0x7f678c1c, 0x8b5df30, 0x7f6940b8, 0x8a96bf6,
-  0x7f6af2e3, 0x89cf867, 0x7f6ca29c, 0x8908483,
-  0x7f6e4fe3, 0x884104b, 0x7f6ffab8, 0x8779bbe,
-  0x7f71a31b, 0x86b26de, 0x7f73490b, 0x85eb1ab,
-  0x7f74ec8a, 0x8523c25, 0x7f768d96, 0x845c64d,
-  0x7f782c30, 0x8395024, 0x7f79c857, 0x82cd9a9,
-  0x7f7b620c, 0x82062de, 0x7f7cf94e, 0x813ebc2,
-  0x7f7e8e1e, 0x8077457, 0x7f80207b, 0x7fafc9c,
-  0x7f81b065, 0x7ee8493, 0x7f833ddd, 0x7e20c3b,
-  0x7f84c8e2, 0x7d59396, 0x7f865174, 0x7c91aa3,
-  0x7f87d792, 0x7bca163, 0x7f895b3e, 0x7b027d7,
-  0x7f8adc77, 0x7a3adff, 0x7f8c5b3d, 0x79733dc,
-  0x7f8dd78f, 0x78ab96e, 0x7f8f516e, 0x77e3eb5,
-  0x7f90c8da, 0x771c3b3, 0x7f923dd2, 0x7654867,
-  0x7f93b058, 0x758ccd2, 0x7f952069, 0x74c50f4,
-  0x7f968e07, 0x73fd4cf, 0x7f97f932, 0x7335862,
-  0x7f9961e8, 0x726dbae, 0x7f9ac82c, 0x71a5eb3,
-  0x7f9c2bfb, 0x70de172, 0x7f9d8d56, 0x70163eb,
-  0x7f9eec3e, 0x6f4e620, 0x7fa048b2, 0x6e86810,
-  0x7fa1a2b2, 0x6dbe9bb, 0x7fa2fa3d, 0x6cf6b23,
-  0x7fa44f55, 0x6c2ec48, 0x7fa5a1f9, 0x6b66d29,
-  0x7fa6f228, 0x6a9edc9, 0x7fa83fe3, 0x69d6e27,
-  0x7fa98b2a, 0x690ee44, 0x7faad3fd, 0x6846e1f,
-  0x7fac1a5b, 0x677edbb, 0x7fad5e45, 0x66b6d16,
-  0x7fae9fbb, 0x65eec33, 0x7fafdebb, 0x6526b10,
-  0x7fb11b48, 0x645e9af, 0x7fb2555f, 0x6396810,
-  0x7fb38d02, 0x62ce634, 0x7fb4c231, 0x620641a,
-  0x7fb5f4ea, 0x613e1c5, 0x7fb7252f, 0x6075f33,
-  0x7fb852ff, 0x5fadc66, 0x7fb97e5a, 0x5ee595d,
-  0x7fbaa740, 0x5e1d61b, 0x7fbbcdb1, 0x5d5529e,
-  0x7fbcf1ad, 0x5c8cee7, 0x7fbe1334, 0x5bc4af8,
-  0x7fbf3246, 0x5afc6d0, 0x7fc04ee3, 0x5a3426f,
-  0x7fc1690a, 0x596bdd7, 0x7fc280bc, 0x58a3908,
-  0x7fc395f9, 0x57db403, 0x7fc4a8c1, 0x5712ec7,
-  0x7fc5b913, 0x564a955, 0x7fc6c6f0, 0x55823ae,
-  0x7fc7d258, 0x54b9dd3, 0x7fc8db4a, 0x53f17c3,
-  0x7fc9e1c6, 0x532917f, 0x7fcae5cd, 0x5260b08,
-  0x7fcbe75e, 0x519845e, 0x7fcce67a, 0x50cfd82,
-  0x7fcde320, 0x5007674, 0x7fcedd50, 0x4f3ef35,
-  0x7fcfd50b, 0x4e767c5, 0x7fd0ca4f, 0x4dae024,
-  0x7fd1bd1e, 0x4ce5854, 0x7fd2ad77, 0x4c1d054,
-  0x7fd39b5a, 0x4b54825, 0x7fd486c7, 0x4a8bfc7,
-  0x7fd56fbe, 0x49c373c, 0x7fd6563f, 0x48fae83,
-  0x7fd73a4a, 0x483259d, 0x7fd81bdf, 0x4769c8b,
-  0x7fd8fafe, 0x46a134c, 0x7fd9d7a7, 0x45d89e2,
-  0x7fdab1d9, 0x451004d, 0x7fdb8996, 0x444768d,
-  0x7fdc5edc, 0x437eca4, 0x7fdd31ac, 0x42b6290,
-  0x7fde0205, 0x41ed854, 0x7fdecfe8, 0x4124dee,
-  0x7fdf9b55, 0x405c361, 0x7fe0644b, 0x3f938ac,
-  0x7fe12acb, 0x3ecadcf, 0x7fe1eed5, 0x3e022cc,
-  0x7fe2b067, 0x3d397a3, 0x7fe36f84, 0x3c70c54,
-  0x7fe42c2a, 0x3ba80df, 0x7fe4e659, 0x3adf546,
-  0x7fe59e12, 0x3a16988, 0x7fe65354, 0x394dda7,
-  0x7fe7061f, 0x38851a2, 0x7fe7b674, 0x37bc57b,
-  0x7fe86452, 0x36f3931, 0x7fe90fb9, 0x362acc5,
-  0x7fe9b8a9, 0x3562038, 0x7fea5f23, 0x3499389,
-  0x7feb0326, 0x33d06bb, 0x7feba4b2, 0x33079cc,
-  0x7fec43c7, 0x323ecbe, 0x7fece065, 0x3175f91,
-  0x7fed7a8c, 0x30ad245, 0x7fee123d, 0x2fe44dc,
-  0x7feea776, 0x2f1b755, 0x7fef3a39, 0x2e529b0,
-  0x7fefca84, 0x2d89bf0, 0x7ff05858, 0x2cc0e13,
-  0x7ff0e3b6, 0x2bf801a, 0x7ff16c9c, 0x2b2f207,
-  0x7ff1f30b, 0x2a663d8, 0x7ff27703, 0x299d590,
-  0x7ff2f884, 0x28d472e, 0x7ff3778e, 0x280b8b3,
-  0x7ff3f420, 0x2742a1f, 0x7ff46e3c, 0x2679b73,
-  0x7ff4e5e0, 0x25b0caf, 0x7ff55b0d, 0x24e7dd4,
-  0x7ff5cdc3, 0x241eee2, 0x7ff63e01, 0x2355fd9,
-  0x7ff6abc8, 0x228d0bb, 0x7ff71718, 0x21c4188,
-  0x7ff77ff1, 0x20fb240, 0x7ff7e652, 0x20322e3,
-  0x7ff84a3c, 0x1f69373, 0x7ff8abae, 0x1ea03ef,
-  0x7ff90aaa, 0x1dd7459, 0x7ff9672d, 0x1d0e4b0,
-  0x7ff9c13a, 0x1c454f5, 0x7ffa18cf, 0x1b7c528,
-  0x7ffa6dec, 0x1ab354b, 0x7ffac092, 0x19ea55d,
-  0x7ffb10c1, 0x192155f, 0x7ffb5e78, 0x1858552,
-  0x7ffba9b8, 0x178f536, 0x7ffbf280, 0x16c650b,
-  0x7ffc38d1, 0x15fd4d2, 0x7ffc7caa, 0x153448c,
-  0x7ffcbe0c, 0x146b438, 0x7ffcfcf6, 0x13a23d8,
-  0x7ffd3969, 0x12d936c, 0x7ffd7364, 0x12102f4,
-  0x7ffdaae7, 0x1147271, 0x7ffddff3, 0x107e1e3,
-  0x7ffe1288, 0xfb514b, 0x7ffe42a4, 0xeec0aa,
-  0x7ffe704a, 0xe22fff, 0x7ffe9b77, 0xd59f4c,
-  0x7ffec42d, 0xc90e90, 0x7ffeea6c, 0xbc7dcc,
-  0x7fff0e32, 0xafed02, 0x7fff2f82, 0xa35c30,
-  0x7fff4e59, 0x96cb58, 0x7fff6ab9, 0x8a3a7b,
-  0x7fff84a1, 0x7da998, 0x7fff9c12, 0x7118b0,
-  0x7fffb10b, 0x6487c4, 0x7fffc38c, 0x57f6d4,
-  0x7fffd396, 0x4b65e1, 0x7fffe128, 0x3ed4ea,
-  0x7fffec43, 0x3243f1, 0x7ffff4e6, 0x25b2f7,
-  0x7ffffb11, 0x1921fb, 0x7ffffec4, 0xc90fe,
-  0x7fffffff, 0x0, 0x7ffffec4, 0xfff36f02,
-  0x7ffffb11, 0xffe6de05, 0x7ffff4e6, 0xffda4d09,
-  0x7fffec43, 0xffcdbc0f, 0x7fffe128, 0xffc12b16,
-  0x7fffd396, 0xffb49a1f, 0x7fffc38c, 0xffa8092c,
-  0x7fffb10b, 0xff9b783c, 0x7fff9c12, 0xff8ee750,
-  0x7fff84a1, 0xff825668, 0x7fff6ab9, 0xff75c585,
-  0x7fff4e59, 0xff6934a8, 0x7fff2f82, 0xff5ca3d0,
-  0x7fff0e32, 0xff5012fe, 0x7ffeea6c, 0xff438234,
-  0x7ffec42d, 0xff36f170, 0x7ffe9b77, 0xff2a60b4,
-  0x7ffe704a, 0xff1dd001, 0x7ffe42a4, 0xff113f56,
-  0x7ffe1288, 0xff04aeb5, 0x7ffddff3, 0xfef81e1d,
-  0x7ffdaae7, 0xfeeb8d8f, 0x7ffd7364, 0xfedefd0c,
-  0x7ffd3969, 0xfed26c94, 0x7ffcfcf6, 0xfec5dc28,
-  0x7ffcbe0c, 0xfeb94bc8, 0x7ffc7caa, 0xfeacbb74,
-  0x7ffc38d1, 0xfea02b2e, 0x7ffbf280, 0xfe939af5,
-  0x7ffba9b8, 0xfe870aca, 0x7ffb5e78, 0xfe7a7aae,
-  0x7ffb10c1, 0xfe6deaa1, 0x7ffac092, 0xfe615aa3,
-  0x7ffa6dec, 0xfe54cab5, 0x7ffa18cf, 0xfe483ad8,
-  0x7ff9c13a, 0xfe3bab0b, 0x7ff9672d, 0xfe2f1b50,
-  0x7ff90aaa, 0xfe228ba7, 0x7ff8abae, 0xfe15fc11,
-  0x7ff84a3c, 0xfe096c8d, 0x7ff7e652, 0xfdfcdd1d,
-  0x7ff77ff1, 0xfdf04dc0, 0x7ff71718, 0xfde3be78,
-  0x7ff6abc8, 0xfdd72f45, 0x7ff63e01, 0xfdcaa027,
-  0x7ff5cdc3, 0xfdbe111e, 0x7ff55b0d, 0xfdb1822c,
-  0x7ff4e5e0, 0xfda4f351, 0x7ff46e3c, 0xfd98648d,
-  0x7ff3f420, 0xfd8bd5e1, 0x7ff3778e, 0xfd7f474d,
-  0x7ff2f884, 0xfd72b8d2, 0x7ff27703, 0xfd662a70,
-  0x7ff1f30b, 0xfd599c28, 0x7ff16c9c, 0xfd4d0df9,
-  0x7ff0e3b6, 0xfd407fe6, 0x7ff05858, 0xfd33f1ed,
-  0x7fefca84, 0xfd276410, 0x7fef3a39, 0xfd1ad650,
-  0x7feea776, 0xfd0e48ab, 0x7fee123d, 0xfd01bb24,
-  0x7fed7a8c, 0xfcf52dbb, 0x7fece065, 0xfce8a06f,
-  0x7fec43c7, 0xfcdc1342, 0x7feba4b2, 0xfccf8634,
-  0x7feb0326, 0xfcc2f945, 0x7fea5f23, 0xfcb66c77,
-  0x7fe9b8a9, 0xfca9dfc8, 0x7fe90fb9, 0xfc9d533b,
-  0x7fe86452, 0xfc90c6cf, 0x7fe7b674, 0xfc843a85,
-  0x7fe7061f, 0xfc77ae5e, 0x7fe65354, 0xfc6b2259,
-  0x7fe59e12, 0xfc5e9678, 0x7fe4e659, 0xfc520aba,
-  0x7fe42c2a, 0xfc457f21, 0x7fe36f84, 0xfc38f3ac,
-  0x7fe2b067, 0xfc2c685d, 0x7fe1eed5, 0xfc1fdd34,
-  0x7fe12acb, 0xfc135231, 0x7fe0644b, 0xfc06c754,
-  0x7fdf9b55, 0xfbfa3c9f, 0x7fdecfe8, 0xfbedb212,
-  0x7fde0205, 0xfbe127ac, 0x7fdd31ac, 0xfbd49d70,
-  0x7fdc5edc, 0xfbc8135c, 0x7fdb8996, 0xfbbb8973,
-  0x7fdab1d9, 0xfbaeffb3, 0x7fd9d7a7, 0xfba2761e,
-  0x7fd8fafe, 0xfb95ecb4, 0x7fd81bdf, 0xfb896375,
-  0x7fd73a4a, 0xfb7cda63, 0x7fd6563f, 0xfb70517d,
-  0x7fd56fbe, 0xfb63c8c4, 0x7fd486c7, 0xfb574039,
-  0x7fd39b5a, 0xfb4ab7db, 0x7fd2ad77, 0xfb3e2fac,
-  0x7fd1bd1e, 0xfb31a7ac, 0x7fd0ca4f, 0xfb251fdc,
-  0x7fcfd50b, 0xfb18983b, 0x7fcedd50, 0xfb0c10cb,
-  0x7fcde320, 0xfaff898c, 0x7fcce67a, 0xfaf3027e,
-  0x7fcbe75e, 0xfae67ba2, 0x7fcae5cd, 0xfad9f4f8,
-  0x7fc9e1c6, 0xfacd6e81, 0x7fc8db4a, 0xfac0e83d,
-  0x7fc7d258, 0xfab4622d, 0x7fc6c6f0, 0xfaa7dc52,
-  0x7fc5b913, 0xfa9b56ab, 0x7fc4a8c1, 0xfa8ed139,
-  0x7fc395f9, 0xfa824bfd, 0x7fc280bc, 0xfa75c6f8,
-  0x7fc1690a, 0xfa694229, 0x7fc04ee3, 0xfa5cbd91,
-  0x7fbf3246, 0xfa503930, 0x7fbe1334, 0xfa43b508,
-  0x7fbcf1ad, 0xfa373119, 0x7fbbcdb1, 0xfa2aad62,
-  0x7fbaa740, 0xfa1e29e5, 0x7fb97e5a, 0xfa11a6a3,
-  0x7fb852ff, 0xfa05239a, 0x7fb7252f, 0xf9f8a0cd,
-  0x7fb5f4ea, 0xf9ec1e3b, 0x7fb4c231, 0xf9df9be6,
-  0x7fb38d02, 0xf9d319cc, 0x7fb2555f, 0xf9c697f0,
-  0x7fb11b48, 0xf9ba1651, 0x7fafdebb, 0xf9ad94f0,
-  0x7fae9fbb, 0xf9a113cd, 0x7fad5e45, 0xf99492ea,
-  0x7fac1a5b, 0xf9881245, 0x7faad3fd, 0xf97b91e1,
-  0x7fa98b2a, 0xf96f11bc, 0x7fa83fe3, 0xf96291d9,
-  0x7fa6f228, 0xf9561237, 0x7fa5a1f9, 0xf94992d7,
-  0x7fa44f55, 0xf93d13b8, 0x7fa2fa3d, 0xf93094dd,
-  0x7fa1a2b2, 0xf9241645, 0x7fa048b2, 0xf91797f0,
-  0x7f9eec3e, 0xf90b19e0, 0x7f9d8d56, 0xf8fe9c15,
-  0x7f9c2bfb, 0xf8f21e8e, 0x7f9ac82c, 0xf8e5a14d,
-  0x7f9961e8, 0xf8d92452, 0x7f97f932, 0xf8cca79e,
-  0x7f968e07, 0xf8c02b31, 0x7f952069, 0xf8b3af0c,
-  0x7f93b058, 0xf8a7332e, 0x7f923dd2, 0xf89ab799,
-  0x7f90c8da, 0xf88e3c4d, 0x7f8f516e, 0xf881c14b,
-  0x7f8dd78f, 0xf8754692, 0x7f8c5b3d, 0xf868cc24,
-  0x7f8adc77, 0xf85c5201, 0x7f895b3e, 0xf84fd829,
-  0x7f87d792, 0xf8435e9d, 0x7f865174, 0xf836e55d,
-  0x7f84c8e2, 0xf82a6c6a, 0x7f833ddd, 0xf81df3c5,
-  0x7f81b065, 0xf8117b6d, 0x7f80207b, 0xf8050364,
-  0x7f7e8e1e, 0xf7f88ba9, 0x7f7cf94e, 0xf7ec143e,
-  0x7f7b620c, 0xf7df9d22, 0x7f79c857, 0xf7d32657,
-  0x7f782c30, 0xf7c6afdc, 0x7f768d96, 0xf7ba39b3,
-  0x7f74ec8a, 0xf7adc3db, 0x7f73490b, 0xf7a14e55,
-  0x7f71a31b, 0xf794d922, 0x7f6ffab8, 0xf7886442,
-  0x7f6e4fe3, 0xf77befb5, 0x7f6ca29c, 0xf76f7b7d,
-  0x7f6af2e3, 0xf7630799, 0x7f6940b8, 0xf756940a,
-  0x7f678c1c, 0xf74a20d0, 0x7f65d50d, 0xf73daded,
-  0x7f641b8d, 0xf7313b60, 0x7f625f9b, 0xf724c92a,
-  0x7f60a138, 0xf718574b, 0x7f5ee063, 0xf70be5c4,
-  0x7f5d1d1d, 0xf6ff7496, 0x7f5b5765, 0xf6f303c0,
-  0x7f598f3c, 0xf6e69344, 0x7f57c4a2, 0xf6da2321,
-  0x7f55f796, 0xf6cdb359, 0x7f54281a, 0xf6c143ec,
-  0x7f52562c, 0xf6b4d4d9, 0x7f5081cd, 0xf6a86623,
-  0x7f4eaafe, 0xf69bf7c9, 0x7f4cd1be, 0xf68f89cb,
-  0x7f4af60d, 0xf6831c2b, 0x7f4917eb, 0xf676aee8,
-  0x7f473759, 0xf66a4203, 0x7f455456, 0xf65dd57d,
-  0x7f436ee3, 0xf6516956, 0x7f4186ff, 0xf644fd8f,
-  0x7f3f9cab, 0xf6389228, 0x7f3dafe7, 0xf62c2721,
-  0x7f3bc0b3, 0xf61fbc7b, 0x7f39cf0e, 0xf6135237,
-  0x7f37dafa, 0xf606e854, 0x7f35e476, 0xf5fa7ed4,
-  0x7f33eb81, 0xf5ee15b7, 0x7f31f01d, 0xf5e1acfd,
-  0x7f2ff24a, 0xf5d544a7, 0x7f2df206, 0xf5c8dcb6,
-  0x7f2bef53, 0xf5bc7529, 0x7f29ea31, 0xf5b00e02,
-  0x7f27e29f, 0xf5a3a740, 0x7f25d89e, 0xf59740e5,
-  0x7f23cc2e, 0xf58adaf0, 0x7f21bd4e, 0xf57e7563,
-  0x7f1fabff, 0xf572103d, 0x7f1d9842, 0xf565ab80,
-  0x7f1b8215, 0xf559472b, 0x7f19697a, 0xf54ce33f,
-  0x7f174e70, 0xf5407fbd, 0x7f1530f7, 0xf5341ca5,
-  0x7f13110f, 0xf527b9f7, 0x7f10eeb9, 0xf51b57b5,
-  0x7f0ec9f5, 0xf50ef5de, 0x7f0ca2c2, 0xf5029473,
-  0x7f0a7921, 0xf4f63374, 0x7f084d12, 0xf4e9d2e3,
-  0x7f061e95, 0xf4dd72be, 0x7f03eda9, 0xf4d11308,
-  0x7f01ba50, 0xf4c4b3c0, 0x7eff8489, 0xf4b854e7,
-  0x7efd4c54, 0xf4abf67e, 0x7efb11b1, 0xf49f9884,
-  0x7ef8d4a1, 0xf4933afa, 0x7ef69523, 0xf486dde1,
-  0x7ef45338, 0xf47a8139, 0x7ef20ee0, 0xf46e2504,
-  0x7eefc81a, 0xf461c940, 0x7eed7ee7, 0xf4556def,
-  0x7eeb3347, 0xf4491311, 0x7ee8e53a, 0xf43cb8a7,
-  0x7ee694c1, 0xf4305eb0, 0x7ee441da, 0xf424052f,
-  0x7ee1ec87, 0xf417ac22, 0x7edf94c7, 0xf40b538b,
-  0x7edd3a9a, 0xf3fefb6a, 0x7edade01, 0xf3f2a3bf,
-  0x7ed87efc, 0xf3e64c8c, 0x7ed61d8a, 0xf3d9f5cf,
-  0x7ed3b9ad, 0xf3cd9f8b, 0x7ed15363, 0xf3c149bf,
-  0x7eceeaad, 0xf3b4f46c, 0x7ecc7f8b, 0xf3a89f92,
-  0x7eca11fe, 0xf39c4b32, 0x7ec7a205, 0xf38ff74d,
-  0x7ec52fa0, 0xf383a3e2, 0x7ec2bad0, 0xf37750f2,
-  0x7ec04394, 0xf36afe7e, 0x7ebdc9ed, 0xf35eac86,
-  0x7ebb4ddb, 0xf3525b0b, 0x7eb8cf5d, 0xf3460a0d,
-  0x7eb64e75, 0xf339b98d, 0x7eb3cb21, 0xf32d698a,
-  0x7eb14563, 0xf3211a07, 0x7eaebd3a, 0xf314cb02,
-  0x7eac32a6, 0xf3087c7d, 0x7ea9a5a8, 0xf2fc2e77,
-  0x7ea7163f, 0xf2efe0f2, 0x7ea4846c, 0xf2e393ef,
-  0x7ea1f02f, 0xf2d7476c, 0x7e9f5988, 0xf2cafb6b,
-  0x7e9cc076, 0xf2beafed, 0x7e9a24fb, 0xf2b264f2,
-  0x7e978715, 0xf2a61a7a, 0x7e94e6c6, 0xf299d085,
-  0x7e92440d, 0xf28d8715, 0x7e8f9eeb, 0xf2813e2a,
-  0x7e8cf75f, 0xf274f5c3, 0x7e8a4d6a, 0xf268ade3,
-  0x7e87a10c, 0xf25c6688, 0x7e84f245, 0xf2501fb5,
-  0x7e824114, 0xf243d968, 0x7e7f8d7b, 0xf23793a3,
-  0x7e7cd778, 0xf22b4e66, 0x7e7a1f0d, 0xf21f09b1,
-  0x7e77643a, 0xf212c585, 0x7e74a6fd, 0xf20681e3,
-  0x7e71e759, 0xf1fa3ecb, 0x7e6f254c, 0xf1edfc3d,
-  0x7e6c60d7, 0xf1e1ba3a, 0x7e6999fa, 0xf1d578c2,
-  0x7e66d0b4, 0xf1c937d6, 0x7e640507, 0xf1bcf777,
-  0x7e6136f3, 0xf1b0b7a4, 0x7e5e6676, 0xf1a4785e,
-  0x7e5b9392, 0xf19839a6, 0x7e58be47, 0xf18bfb7d,
-  0x7e55e694, 0xf17fbde2, 0x7e530c7a, 0xf17380d6,
-  0x7e502ff9, 0xf1674459, 0x7e4d5110, 0xf15b086d,
-  0x7e4a6fc1, 0xf14ecd11, 0x7e478c0b, 0xf1429247,
-  0x7e44a5ef, 0xf136580d, 0x7e41bd6c, 0xf12a1e66,
-  0x7e3ed282, 0xf11de551, 0x7e3be532, 0xf111accf,
-  0x7e38f57c, 0xf10574e0, 0x7e360360, 0xf0f93d86,
-  0x7e330ede, 0xf0ed06bf, 0x7e3017f6, 0xf0e0d08d,
-  0x7e2d1ea8, 0xf0d49af1, 0x7e2a22f4, 0xf0c865ea,
-  0x7e2724db, 0xf0bc317a, 0x7e24245d, 0xf0affda0,
-  0x7e212179, 0xf0a3ca5d, 0x7e1e1c30, 0xf09797b2,
-  0x7e1b1482, 0xf08b659f, 0x7e180a6f, 0xf07f3424,
-  0x7e14fdf7, 0xf0730342, 0x7e11ef1b, 0xf066d2fa,
-  0x7e0eddd9, 0xf05aa34c, 0x7e0bca34, 0xf04e7438,
-  0x7e08b42a, 0xf04245c0, 0x7e059bbb, 0xf03617e2,
-  0x7e0280e9, 0xf029eaa1, 0x7dff63b2, 0xf01dbdfb,
-  0x7dfc4418, 0xf01191f3, 0x7df9221a, 0xf0056687,
-  0x7df5fdb8, 0xeff93bba, 0x7df2d6f3, 0xefed118a,
-  0x7defadca, 0xefe0e7f9, 0x7dec823e, 0xefd4bf08,
-  0x7de9544f, 0xefc896b5, 0x7de623fd, 0xefbc6f03,
-  0x7de2f148, 0xefb047f2, 0x7ddfbc30, 0xefa42181,
-  0x7ddc84b5, 0xef97fbb2, 0x7dd94ad8, 0xef8bd685,
-  0x7dd60e99, 0xef7fb1fa, 0x7dd2cff7, 0xef738e12,
-  0x7dcf8ef3, 0xef676ace, 0x7dcc4b8d, 0xef5b482d,
-  0x7dc905c5, 0xef4f2630, 0x7dc5bd9b, 0xef4304d8,
-  0x7dc2730f, 0xef36e426, 0x7dbf2622, 0xef2ac419,
-  0x7dbbd6d4, 0xef1ea4b2, 0x7db88524, 0xef1285f2,
-  0x7db53113, 0xef0667d9, 0x7db1daa2, 0xeefa4a67,
-  0x7dae81cf, 0xeeee2d9d, 0x7dab269b, 0xeee2117c,
-  0x7da7c907, 0xeed5f604, 0x7da46912, 0xeec9db35,
-  0x7da106bd, 0xeebdc110, 0x7d9da208, 0xeeb1a796,
-  0x7d9a3af2, 0xeea58ec6, 0x7d96d17d, 0xee9976a1,
-  0x7d9365a8, 0xee8d5f29, 0x7d8ff772, 0xee81485c,
-  0x7d8c86de, 0xee75323c, 0x7d8913ea, 0xee691cc9,
-  0x7d859e96, 0xee5d0804, 0x7d8226e4, 0xee50f3ed,
-  0x7d7eacd2, 0xee44e084, 0x7d7b3061, 0xee38cdcb,
-  0x7d77b192, 0xee2cbbc1, 0x7d743064, 0xee20aa67,
-  0x7d70acd7, 0xee1499bd, 0x7d6d26ec, 0xee0889c4,
-  0x7d699ea3, 0xedfc7a7c, 0x7d6613fb, 0xedf06be6,
-  0x7d6286f6, 0xede45e03, 0x7d5ef793, 0xedd850d2,
-  0x7d5b65d2, 0xedcc4454, 0x7d57d1b3, 0xedc0388a,
-  0x7d543b37, 0xedb42d74, 0x7d50a25e, 0xeda82313,
-  0x7d4d0728, 0xed9c1967, 0x7d496994, 0xed901070,
-  0x7d45c9a4, 0xed84082f, 0x7d422757, 0xed7800a5,
-  0x7d3e82ae, 0xed6bf9d1, 0x7d3adba7, 0xed5ff3b5,
-  0x7d373245, 0xed53ee51, 0x7d338687, 0xed47e9a5,
-  0x7d2fd86c, 0xed3be5b1, 0x7d2c27f6, 0xed2fe277,
-  0x7d287523, 0xed23dff7, 0x7d24bff6, 0xed17de31,
-  0x7d21086c, 0xed0bdd25, 0x7d1d4e88, 0xecffdcd4,
-  0x7d199248, 0xecf3dd3f, 0x7d15d3ad, 0xece7de66,
-  0x7d1212b7, 0xecdbe04a, 0x7d0e4f67, 0xeccfe2ea,
-  0x7d0a89bc, 0xecc3e648, 0x7d06c1b6, 0xecb7ea63,
-  0x7d02f757, 0xecabef3d, 0x7cff2a9d, 0xec9ff4d6,
-  0x7cfb5b89, 0xec93fb2e, 0x7cf78a1b, 0xec880245,
-  0x7cf3b653, 0xec7c0a1d, 0x7cefe032, 0xec7012b5,
-  0x7cec07b8, 0xec641c0e, 0x7ce82ce4, 0xec582629,
-  0x7ce44fb7, 0xec4c3106, 0x7ce07031, 0xec403ca5,
-  0x7cdc8e52, 0xec344908, 0x7cd8aa1b, 0xec28562d,
-  0x7cd4c38b, 0xec1c6417, 0x7cd0daa2, 0xec1072c4,
-  0x7cccef62, 0xec048237, 0x7cc901c9, 0xebf8926f,
-  0x7cc511d9, 0xebeca36c, 0x7cc11f90, 0xebe0b52f,
-  0x7cbd2af0, 0xebd4c7ba, 0x7cb933f9, 0xebc8db0b,
-  0x7cb53aaa, 0xebbcef23, 0x7cb13f04, 0xebb10404,
-  0x7cad4107, 0xeba519ad, 0x7ca940b3, 0xeb99301f,
-  0x7ca53e09, 0xeb8d475b, 0x7ca13908, 0xeb815f60,
-  0x7c9d31b0, 0xeb75782f, 0x7c992803, 0xeb6991ca,
-  0x7c951bff, 0xeb5dac2f, 0x7c910da5, 0xeb51c760,
-  0x7c8cfcf6, 0xeb45e35d, 0x7c88e9f1, 0xeb3a0027,
-  0x7c84d496, 0xeb2e1dbe, 0x7c80bce7, 0xeb223c22,
-  0x7c7ca2e2, 0xeb165b54, 0x7c788688, 0xeb0a7b54,
-  0x7c7467d9, 0xeafe9c24, 0x7c7046d6, 0xeaf2bdc3,
-  0x7c6c237e, 0xeae6e031, 0x7c67fdd1, 0xeadb0370,
-  0x7c63d5d1, 0xeacf277f, 0x7c5fab7c, 0xeac34c60,
-  0x7c5b7ed4, 0xeab77212, 0x7c574fd8, 0xeaab9896,
-  0x7c531e88, 0xea9fbfed, 0x7c4eeae5, 0xea93e817,
-  0x7c4ab4ef, 0xea881114, 0x7c467ca6, 0xea7c3ae5,
-  0x7c42420a, 0xea70658a, 0x7c3e051b, 0xea649105,
-  0x7c39c5da, 0xea58bd54, 0x7c358446, 0xea4cea79,
-  0x7c314060, 0xea411874, 0x7c2cfa28, 0xea354746,
-  0x7c28b19e, 0xea2976ef, 0x7c2466c2, 0xea1da770,
-  0x7c201994, 0xea11d8c8, 0x7c1bca16, 0xea060af9,
-  0x7c177845, 0xe9fa3e03, 0x7c132424, 0xe9ee71e6,
-  0x7c0ecdb2, 0xe9e2a6a3, 0x7c0a74f0, 0xe9d6dc3b,
-  0x7c0619dc, 0xe9cb12ad, 0x7c01bc78, 0xe9bf49fa,
-  0x7bfd5cc4, 0xe9b38223, 0x7bf8fac0, 0xe9a7bb28,
-  0x7bf4966c, 0xe99bf509, 0x7bf02fc9, 0xe9902fc7,
-  0x7bebc6d5, 0xe9846b63, 0x7be75b93, 0xe978a7dd,
-  0x7be2ee01, 0xe96ce535, 0x7bde7e20, 0xe961236c,
-  0x7bda0bf0, 0xe9556282, 0x7bd59771, 0xe949a278,
-  0x7bd120a4, 0xe93de34e, 0x7bcca789, 0xe9322505,
-  0x7bc82c1f, 0xe926679c, 0x7bc3ae67, 0xe91aab16,
-  0x7bbf2e62, 0xe90eef71, 0x7bbaac0e, 0xe90334af,
-  0x7bb6276e, 0xe8f77acf, 0x7bb1a080, 0xe8ebc1d3,
-  0x7bad1744, 0xe8e009ba, 0x7ba88bbc, 0xe8d45286,
-  0x7ba3fde7, 0xe8c89c37, 0x7b9f6dc5, 0xe8bce6cd,
-  0x7b9adb57, 0xe8b13248, 0x7b96469d, 0xe8a57ea9,
-  0x7b91af97, 0xe899cbf1, 0x7b8d1644, 0xe88e1a20,
-  0x7b887aa6, 0xe8826936, 0x7b83dcbc, 0xe876b934,
-  0x7b7f3c87, 0xe86b0a1a, 0x7b7a9a07, 0xe85f5be9,
-  0x7b75f53c, 0xe853aea1, 0x7b714e25, 0xe8480243,
-  0x7b6ca4c4, 0xe83c56cf, 0x7b67f919, 0xe830ac45,
-  0x7b634b23, 0xe82502a7, 0x7b5e9ae4, 0xe81959f4,
-  0x7b59e85a, 0xe80db22d, 0x7b553386, 0xe8020b52,
-  0x7b507c69, 0xe7f66564, 0x7b4bc303, 0xe7eac063,
-  0x7b470753, 0xe7df1c50, 0x7b42495a, 0xe7d3792b,
-  0x7b3d8918, 0xe7c7d6f4, 0x7b38c68e, 0xe7bc35ad,
-  0x7b3401bb, 0xe7b09555, 0x7b2f3aa0, 0xe7a4f5ed,
-  0x7b2a713d, 0xe7995776, 0x7b25a591, 0xe78db9ef,
-  0x7b20d79e, 0xe7821d59, 0x7b1c0764, 0xe77681b6,
-  0x7b1734e2, 0xe76ae704, 0x7b126019, 0xe75f4d45,
-  0x7b0d8909, 0xe753b479, 0x7b08afb2, 0xe7481ca1,
-  0x7b03d414, 0xe73c85bc, 0x7afef630, 0xe730efcc,
-  0x7afa1605, 0xe7255ad1, 0x7af53395, 0xe719c6cb,
-  0x7af04edf, 0xe70e33bb, 0x7aeb67e3, 0xe702a1a1,
-  0x7ae67ea1, 0xe6f7107e, 0x7ae1931a, 0xe6eb8052,
-  0x7adca54e, 0xe6dff11d, 0x7ad7b53d, 0xe6d462e1,
-  0x7ad2c2e8, 0xe6c8d59c, 0x7acdce4d, 0xe6bd4951,
-  0x7ac8d76f, 0xe6b1bdff, 0x7ac3de4c, 0xe6a633a6,
-  0x7abee2e5, 0xe69aaa48, 0x7ab9e53a, 0xe68f21e5,
-  0x7ab4e54c, 0xe6839a7c, 0x7aafe31b, 0xe6781410,
-  0x7aaadea6, 0xe66c8e9f, 0x7aa5d7ee, 0xe6610a2a,
-  0x7aa0cef3, 0xe65586b3, 0x7a9bc3b6, 0xe64a0438,
-  0x7a96b636, 0xe63e82bc, 0x7a91a674, 0xe633023e,
-  0x7a8c9470, 0xe62782be, 0x7a87802a, 0xe61c043d,
-  0x7a8269a3, 0xe61086bc, 0x7a7d50da, 0xe6050a3b,
-  0x7a7835cf, 0xe5f98ebb, 0x7a731884, 0xe5ee143b,
-  0x7a6df8f8, 0xe5e29abc, 0x7a68d72b, 0xe5d72240,
-  0x7a63b31d, 0xe5cbaac5, 0x7a5e8cd0, 0xe5c0344d,
-  0x7a596442, 0xe5b4bed8, 0x7a543974, 0xe5a94a67,
-  0x7a4f0c67, 0xe59dd6f9, 0x7a49dd1a, 0xe5926490,
-  0x7a44ab8e, 0xe586f32c, 0x7a3f77c3, 0xe57b82cd,
-  0x7a3a41b9, 0xe5701374, 0x7a350970, 0xe564a521,
-  0x7a2fcee8, 0xe55937d5, 0x7a2a9223, 0xe54dcb8f,
-  0x7a25531f, 0xe5426051, 0x7a2011de, 0xe536f61b,
-  0x7a1ace5f, 0xe52b8cee, 0x7a1588a2, 0xe52024c9,
-  0x7a1040a8, 0xe514bdad, 0x7a0af671, 0xe509579b,
-  0x7a05a9fd, 0xe4fdf294, 0x7a005b4d, 0xe4f28e96,
-  0x79fb0a60, 0xe4e72ba4, 0x79f5b737, 0xe4dbc9bd,
-  0x79f061d2, 0xe4d068e2, 0x79eb0a31, 0xe4c50914,
-  0x79e5b054, 0xe4b9aa52, 0x79e0543c, 0xe4ae4c9d,
-  0x79daf5e8, 0xe4a2eff6, 0x79d5955a, 0xe497945d,
-  0x79d03291, 0xe48c39d3, 0x79cacd8d, 0xe480e057,
-  0x79c5664f, 0xe47587eb, 0x79bffcd7, 0xe46a308f,
-  0x79ba9125, 0xe45eda43, 0x79b52339, 0xe4538507,
-  0x79afb313, 0xe44830dd, 0x79aa40b4, 0xe43cddc4,
-  0x79a4cc1c, 0xe4318bbe, 0x799f554b, 0xe4263ac9,
-  0x7999dc42, 0xe41aeae8, 0x799460ff, 0xe40f9c1a,
-  0x798ee385, 0xe4044e60, 0x798963d2, 0xe3f901ba,
-  0x7983e1e8, 0xe3edb628, 0x797e5dc6, 0xe3e26bac,
-  0x7978d76c, 0xe3d72245, 0x79734edc, 0xe3cbd9f4,
-  0x796dc414, 0xe3c092b9, 0x79683715, 0xe3b54c95,
-  0x7962a7e0, 0xe3aa0788, 0x795d1675, 0xe39ec393,
-  0x795782d3, 0xe39380b6, 0x7951ecfc, 0xe3883ef2,
-  0x794c54ee, 0xe37cfe47, 0x7946baac, 0xe371beb5,
-  0x79411e33, 0xe366803c, 0x793b7f86, 0xe35b42df,
-  0x7935dea4, 0xe350069b, 0x79303b8e, 0xe344cb73,
-  0x792a9642, 0xe3399167, 0x7924eec3, 0xe32e5876,
-  0x791f4510, 0xe32320a2, 0x79199929, 0xe317e9eb,
-  0x7913eb0e, 0xe30cb451, 0x790e3ac0, 0xe3017fd5,
-  0x7908883f, 0xe2f64c77, 0x7902d38b, 0xe2eb1a37,
-  0x78fd1ca4, 0xe2dfe917, 0x78f7638b, 0xe2d4b916,
-  0x78f1a840, 0xe2c98a35, 0x78ebeac2, 0xe2be5c74,
-  0x78e62b13, 0xe2b32fd4, 0x78e06932, 0xe2a80456,
-  0x78daa520, 0xe29cd9f8, 0x78d4dedd, 0xe291b0bd,
-  0x78cf1669, 0xe28688a4, 0x78c94bc4, 0xe27b61af,
-  0x78c37eef, 0xe2703bdc, 0x78bdafea, 0xe265172e,
-  0x78b7deb4, 0xe259f3a3, 0x78b20b4f, 0xe24ed13d,
-  0x78ac35ba, 0xe243affc, 0x78a65df6, 0xe2388fe1,
-  0x78a08402, 0xe22d70eb, 0x789aa7e0, 0xe222531c,
-  0x7894c98f, 0xe2173674, 0x788ee910, 0xe20c1af3,
-  0x78890663, 0xe2010099, 0x78832187, 0xe1f5e768,
-  0x787d3a7e, 0xe1eacf5f, 0x78775147, 0xe1dfb87f,
-  0x787165e3, 0xe1d4a2c8, 0x786b7852, 0xe1c98e3b,
-  0x78658894, 0xe1be7ad8, 0x785f96a9, 0xe1b368a0,
-  0x7859a292, 0xe1a85793, 0x7853ac4f, 0xe19d47b1,
-  0x784db3e0, 0xe19238fb, 0x7847b946, 0xe1872b72,
-  0x7841bc7f, 0xe17c1f15, 0x783bbd8e, 0xe17113e5,
-  0x7835bc71, 0xe16609e3, 0x782fb92a, 0xe15b0110,
-  0x7829b3b9, 0xe14ff96a, 0x7823ac1d, 0xe144f2f3,
-  0x781da256, 0xe139edac, 0x78179666, 0xe12ee995,
-  0x7811884d, 0xe123e6ad, 0x780b780a, 0xe118e4f6,
-  0x7805659e, 0xe10de470, 0x77ff5109, 0xe102e51c,
-  0x77f93a4b, 0xe0f7e6f9, 0x77f32165, 0xe0ecea09,
-  0x77ed0657, 0xe0e1ee4b, 0x77e6e921, 0xe0d6f3c1,
-  0x77e0c9c3, 0xe0cbfa6a, 0x77daa83d, 0xe0c10247,
-  0x77d48490, 0xe0b60b58, 0x77ce5ebd, 0xe0ab159e,
-  0x77c836c2, 0xe0a0211a, 0x77c20ca1, 0xe0952dcb,
-  0x77bbe05a, 0xe08a3bb2, 0x77b5b1ec, 0xe07f4acf,
-  0x77af8159, 0xe0745b24, 0x77a94ea0, 0xe0696cb0,
-  0x77a319c2, 0xe05e7f74, 0x779ce2be, 0xe053936f,
-  0x7796a996, 0xe048a8a4, 0x77906e49, 0xe03dbf11,
-  0x778a30d8, 0xe032d6b8, 0x7783f143, 0xe027ef99,
-  0x777daf89, 0xe01d09b4, 0x77776bac, 0xe012250a,
-  0x777125ac, 0xe007419b, 0x776add88, 0xdffc5f67,
-  0x77649341, 0xdff17e70, 0x775e46d8, 0xdfe69eb4,
-  0x7757f84c, 0xdfdbc036, 0x7751a79e, 0xdfd0e2f5,
-  0x774b54ce, 0xdfc606f1, 0x7744ffdd, 0xdfbb2c2c,
-  0x773ea8ca, 0xdfb052a5, 0x77384f95, 0xdfa57a5d,
-  0x7731f440, 0xdf9aa354, 0x772b96ca, 0xdf8fcd8b,
-  0x77253733, 0xdf84f902, 0x771ed57c, 0xdf7a25ba,
-  0x771871a5, 0xdf6f53b3, 0x77120bae, 0xdf6482ed,
-  0x770ba398, 0xdf59b369, 0x77053962, 0xdf4ee527,
-  0x76fecd0e, 0xdf441828, 0x76f85e9a, 0xdf394c6b,
-  0x76f1ee09, 0xdf2e81f3, 0x76eb7b58, 0xdf23b8be,
-  0x76e5068a, 0xdf18f0ce, 0x76de8f9e, 0xdf0e2a22,
-  0x76d81695, 0xdf0364bc, 0x76d19b6e, 0xdef8a09b,
-  0x76cb1e2a, 0xdeedddc0, 0x76c49ec9, 0xdee31c2b,
-  0x76be1d4c, 0xded85bdd, 0x76b799b3, 0xdecd9cd7,
-  0x76b113fd, 0xdec2df18, 0x76aa8c2c, 0xdeb822a1,
-  0x76a4023f, 0xdead6773, 0x769d7637, 0xdea2ad8d,
-  0x7696e814, 0xde97f4f1, 0x769057d6, 0xde8d3d9e,
-  0x7689c57d, 0xde828796, 0x7683310b, 0xde77d2d8,
-  0x767c9a7e, 0xde6d1f65, 0x767601d7, 0xde626d3e,
-  0x766f6717, 0xde57bc62, 0x7668ca3e, 0xde4d0cd2,
-  0x76622b4c, 0xde425e8f, 0x765b8a41, 0xde37b199,
-  0x7654e71d, 0xde2d05f1, 0x764e41e2, 0xde225b96,
-  0x76479a8e, 0xde17b28a, 0x7640f123, 0xde0d0acc,
-  0x763a45a0, 0xde02645d, 0x76339806, 0xddf7bf3e,
-  0x762ce855, 0xdded1b6e, 0x7626368d, 0xdde278ef,
-  0x761f82af, 0xddd7d7c1, 0x7618ccba, 0xddcd37e4,
-  0x761214b0, 0xddc29958, 0x760b5a90, 0xddb7fc1e,
-  0x76049e5b, 0xddad6036, 0x75fde011, 0xdda2c5a2,
-  0x75f71fb1, 0xdd982c60, 0x75f05d3d, 0xdd8d9472,
-  0x75e998b5, 0xdd82fdd8, 0x75e2d219, 0xdd786892,
-  0x75dc0968, 0xdd6dd4a2, 0x75d53ea5, 0xdd634206,
-  0x75ce71ce, 0xdd58b0c0, 0x75c7a2e3, 0xdd4e20d0,
-  0x75c0d1e7, 0xdd439236, 0x75b9fed7, 0xdd3904f4,
-  0x75b329b5, 0xdd2e7908, 0x75ac5282, 0xdd23ee74,
-  0x75a5793c, 0xdd196538, 0x759e9de5, 0xdd0edd55,
-  0x7597c07d, 0xdd0456ca, 0x7590e104, 0xdcf9d199,
-  0x7589ff7a, 0xdcef4dc2, 0x75831be0, 0xdce4cb44,
-  0x757c3636, 0xdcda4a21, 0x75754e7c, 0xdccfca59,
-  0x756e64b2, 0xdcc54bec, 0x756778d9, 0xdcbacedb,
-  0x75608af1, 0xdcb05326, 0x75599afa, 0xdca5d8cd,
-  0x7552a8f4, 0xdc9b5fd2, 0x754bb4e1, 0xdc90e834,
-  0x7544bebf, 0xdc8671f3, 0x753dc68f, 0xdc7bfd11,
-  0x7536cc52, 0xdc71898d, 0x752fd008, 0xdc671768,
-  0x7528d1b1, 0xdc5ca6a2, 0x7521d14d, 0xdc52373c,
-  0x751acedd, 0xdc47c936, 0x7513ca60, 0xdc3d5c91,
-  0x750cc3d8, 0xdc32f14d, 0x7505bb44, 0xdc28876a,
-  0x74feb0a5, 0xdc1e1ee9, 0x74f7a3fb, 0xdc13b7c9,
-  0x74f09546, 0xdc09520d, 0x74e98487, 0xdbfeedb3,
-  0x74e271bd, 0xdbf48abd, 0x74db5cea, 0xdbea292b,
-  0x74d4460c, 0xdbdfc8fc, 0x74cd2d26, 0xdbd56a32,
-  0x74c61236, 0xdbcb0cce, 0x74bef53d, 0xdbc0b0ce,
-  0x74b7d63c, 0xdbb65634, 0x74b0b533, 0xdbabfd01,
-  0x74a99221, 0xdba1a534, 0x74a26d08, 0xdb974ece,
-  0x749b45e7, 0xdb8cf9cf, 0x74941cbf, 0xdb82a638,
-  0x748cf190, 0xdb785409, 0x7485c45b, 0xdb6e0342,
-  0x747e951f, 0xdb63b3e5, 0x747763dd, 0xdb5965f1,
-  0x74703095, 0xdb4f1967, 0x7468fb47, 0xdb44ce46,
-  0x7461c3f5, 0xdb3a8491, 0x745a8a9d, 0xdb303c46,
-  0x74534f41, 0xdb25f566, 0x744c11e0, 0xdb1baff2,
-  0x7444d27b, 0xdb116beb, 0x743d9112, 0xdb072950,
-  0x74364da6, 0xdafce821, 0x742f0836, 0xdaf2a860,
-  0x7427c0c3, 0xdae86a0d, 0x7420774d, 0xdade2d28,
-  0x74192bd5, 0xdad3f1b1, 0x7411de5b, 0xdac9b7a9,
-  0x740a8edf, 0xdabf7f11, 0x74033d61, 0xdab547e8,
-  0x73fbe9e2, 0xdaab122f, 0x73f49462, 0xdaa0dde7,
-  0x73ed3ce1, 0xda96ab0f, 0x73e5e360, 0xda8c79a9,
-  0x73de87de, 0xda8249b4, 0x73d72a5d, 0xda781b31,
-  0x73cfcadc, 0xda6dee21, 0x73c8695b, 0xda63c284,
-  0x73c105db, 0xda599859, 0x73b9a05d, 0xda4f6fa3,
-  0x73b238e0, 0xda454860, 0x73aacf65, 0xda3b2292,
-  0x73a363ec, 0xda30fe38, 0x739bf675, 0xda26db54,
-  0x73948701, 0xda1cb9e5, 0x738d1590, 0xda1299ec,
-  0x7385a222, 0xda087b69, 0x737e2cb7, 0xd9fe5e5e,
-  0x7376b551, 0xd9f442c9, 0x736f3bee, 0xd9ea28ac,
-  0x7367c090, 0xd9e01006, 0x73604336, 0xd9d5f8d9,
-  0x7358c3e2, 0xd9cbe325, 0x73514292, 0xd9c1cee9,
-  0x7349bf48, 0xd9b7bc27, 0x73423a04, 0xd9adaadf,
-  0x733ab2c6, 0xd9a39b11, 0x7333298f, 0xd9998cbe,
-  0x732b9e5e, 0xd98f7fe6, 0x73241134, 0xd9857489,
-  0x731c8211, 0xd97b6aa8, 0x7314f0f6, 0xd9716243,
-  0x730d5de3, 0xd9675b5a, 0x7305c8d7, 0xd95d55ef,
-  0x72fe31d5, 0xd9535201, 0x72f698db, 0xd9494f90,
-  0x72eefdea, 0xd93f4e9e, 0x72e76102, 0xd9354f2a,
-  0x72dfc224, 0xd92b5135, 0x72d82150, 0xd92154bf,
-  0x72d07e85, 0xd91759c9, 0x72c8d9c6, 0xd90d6053,
-  0x72c13311, 0xd903685d, 0x72b98a67, 0xd8f971e8,
-  0x72b1dfc9, 0xd8ef7cf4, 0x72aa3336, 0xd8e58982,
-  0x72a284b0, 0xd8db9792, 0x729ad435, 0xd8d1a724,
-  0x729321c7, 0xd8c7b838, 0x728b6d66, 0xd8bdcad0,
-  0x7283b712, 0xd8b3deeb, 0x727bfecc, 0xd8a9f48a,
-  0x72744493, 0xd8a00bae, 0x726c8868, 0xd8962456,
-  0x7264ca4c, 0xd88c3e83, 0x725d0a3e, 0xd8825a35,
-  0x72554840, 0xd878776d, 0x724d8450, 0xd86e962b,
-  0x7245be70, 0xd864b670, 0x723df6a0, 0xd85ad83c,
-  0x72362ce0, 0xd850fb8e, 0x722e6130, 0xd8472069,
-  0x72269391, 0xd83d46cc, 0x721ec403, 0xd8336eb7,
-  0x7216f287, 0xd829982b, 0x720f1f1c, 0xd81fc328,
-  0x720749c3, 0xd815efae, 0x71ff727c, 0xd80c1dbf,
-  0x71f79948, 0xd8024d59, 0x71efbe27, 0xd7f87e7f,
-  0x71e7e118, 0xd7eeb130, 0x71e0021e, 0xd7e4e56c,
-  0x71d82137, 0xd7db1b34, 0x71d03e64, 0xd7d15288,
-  0x71c859a5, 0xd7c78b68, 0x71c072fb, 0xd7bdc5d6,
-  0x71b88a66, 0xd7b401d1, 0x71b09fe7, 0xd7aa3f5a,
-  0x71a8b37c, 0xd7a07e70, 0x71a0c528, 0xd796bf16,
-  0x7198d4ea, 0xd78d014a, 0x7190e2c3, 0xd783450d,
-  0x7188eeb2, 0xd7798a60, 0x7180f8b8, 0xd76fd143,
-  0x717900d6, 0xd76619b6, 0x7171070c, 0xd75c63ba,
-  0x71690b59, 0xd752af4f, 0x71610dbf, 0xd748fc75,
-  0x71590e3e, 0xd73f4b2e, 0x71510cd5, 0xd7359b78,
-  0x71490986, 0xd72bed55, 0x71410450, 0xd72240c5,
-  0x7138fd35, 0xd71895c9, 0x7130f433, 0xd70eec60,
-  0x7128e94c, 0xd705448b, 0x7120dc80, 0xd6fb9e4b,
-  0x7118cdcf, 0xd6f1f99f, 0x7110bd39, 0xd6e85689,
-  0x7108aabf, 0xd6deb508, 0x71009661, 0xd6d5151d,
-  0x70f8801f, 0xd6cb76c9, 0x70f067fb, 0xd6c1da0b,
-  0x70e84df3, 0xd6b83ee4, 0x70e03208, 0xd6aea555,
-  0x70d8143b, 0xd6a50d5d, 0x70cff48c, 0xd69b76fe,
-  0x70c7d2fb, 0xd691e237, 0x70bfaf89, 0xd6884f09,
-  0x70b78a36, 0xd67ebd74, 0x70af6302, 0xd6752d79,
-  0x70a739ed, 0xd66b9f18, 0x709f0ef8, 0xd6621251,
-  0x7096e223, 0xd6588725, 0x708eb36f, 0xd64efd94,
-  0x708682dc, 0xd645759f, 0x707e5069, 0xd63bef46,
-  0x70761c18, 0xd6326a88, 0x706de5e9, 0xd628e767,
-  0x7065addb, 0xd61f65e4, 0x705d73f0, 0xd615e5fd,
-  0x70553828, 0xd60c67b4, 0x704cfa83, 0xd602eb0a,
-  0x7044bb00, 0xd5f96ffd, 0x703c79a2, 0xd5eff690,
-  0x70343667, 0xd5e67ec1, 0x702bf151, 0xd5dd0892,
-  0x7023aa5f, 0xd5d39403, 0x701b6193, 0xd5ca2115,
-  0x701316eb, 0xd5c0afc6, 0x700aca69, 0xd5b74019,
-  0x70027c0c, 0xd5add20d, 0x6ffa2bd6, 0xd5a465a3,
-  0x6ff1d9c7, 0xd59afadb, 0x6fe985de, 0xd59191b5,
-  0x6fe1301c, 0xd5882a32, 0x6fd8d882, 0xd57ec452,
-  0x6fd07f0f, 0xd5756016, 0x6fc823c5, 0xd56bfd7d,
-  0x6fbfc6a3, 0xd5629c89, 0x6fb767aa, 0xd5593d3a,
-  0x6faf06da, 0xd54fdf8f, 0x6fa6a433, 0xd5468389,
-  0x6f9e3fb6, 0xd53d292a, 0x6f95d963, 0xd533d070,
-  0x6f8d713a, 0xd52a795d, 0x6f85073c, 0xd52123f0,
-  0x6f7c9b69, 0xd517d02b, 0x6f742dc1, 0xd50e7e0d,
-  0x6f6bbe45, 0xd5052d97, 0x6f634cf5, 0xd4fbdec9,
-  0x6f5ad9d1, 0xd4f291a4, 0x6f5264da, 0xd4e94627,
-  0x6f49ee0f, 0xd4dffc54, 0x6f417573, 0xd4d6b42b,
-  0x6f38fb03, 0xd4cd6dab, 0x6f307ec2, 0xd4c428d6,
-  0x6f2800af, 0xd4bae5ab, 0x6f1f80ca, 0xd4b1a42c,
-  0x6f16ff14, 0xd4a86458, 0x6f0e7b8e, 0xd49f2630,
-  0x6f05f637, 0xd495e9b3, 0x6efd6f10, 0xd48caee4,
-  0x6ef4e619, 0xd48375c1, 0x6eec5b53, 0xd47a3e4b,
-  0x6ee3cebe, 0xd4710883, 0x6edb405a, 0xd467d469,
-  0x6ed2b027, 0xd45ea1fd, 0x6eca1e27, 0xd4557140,
-  0x6ec18a58, 0xd44c4232, 0x6eb8f4bc, 0xd44314d3,
-  0x6eb05d53, 0xd439e923, 0x6ea7c41e, 0xd430bf24,
-  0x6e9f291b, 0xd42796d5, 0x6e968c4d, 0xd41e7037,
-  0x6e8dedb3, 0xd4154b4a, 0x6e854d4d, 0xd40c280e,
-  0x6e7cab1c, 0xd4030684, 0x6e740720, 0xd3f9e6ad,
-  0x6e6b615a, 0xd3f0c887, 0x6e62b9ca, 0xd3e7ac15,
-  0x6e5a1070, 0xd3de9156, 0x6e51654c, 0xd3d5784a,
-  0x6e48b860, 0xd3cc60f2, 0x6e4009aa, 0xd3c34b4f,
-  0x6e37592c, 0xd3ba3760, 0x6e2ea6e6, 0xd3b12526,
-  0x6e25f2d8, 0xd3a814a2, 0x6e1d3d03, 0xd39f05d3,
-  0x6e148566, 0xd395f8ba, 0x6e0bcc03, 0xd38ced57,
-  0x6e0310d9, 0xd383e3ab, 0x6dfa53e9, 0xd37adbb6,
-  0x6df19534, 0xd371d579, 0x6de8d4b8, 0xd368d0f3,
-  0x6de01278, 0xd35fce26, 0x6dd74e73, 0xd356cd11,
-  0x6dce88aa, 0xd34dcdb4, 0x6dc5c11c, 0xd344d011,
-  0x6dbcf7cb, 0xd33bd427, 0x6db42cb6, 0xd332d9f7,
-  0x6dab5fdf, 0xd329e181, 0x6da29144, 0xd320eac6,
-  0x6d99c0e7, 0xd317f5c6, 0x6d90eec8, 0xd30f0280,
-  0x6d881ae8, 0xd30610f7, 0x6d7f4545, 0xd2fd2129,
-  0x6d766de2, 0xd2f43318, 0x6d6d94bf, 0xd2eb46c3,
-  0x6d64b9da, 0xd2e25c2b, 0x6d5bdd36, 0xd2d97350,
-  0x6d52fed2, 0xd2d08c33, 0x6d4a1eaf, 0xd2c7a6d4,
-  0x6d413ccd, 0xd2bec333, 0x6d38592c, 0xd2b5e151,
-  0x6d2f73cd, 0xd2ad012e, 0x6d268cb0, 0xd2a422ca,
-  0x6d1da3d5, 0xd29b4626, 0x6d14b93d, 0xd2926b41,
-  0x6d0bcce8, 0xd289921e, 0x6d02ded7, 0xd280babb,
-  0x6cf9ef09, 0xd277e518, 0x6cf0fd80, 0xd26f1138,
-  0x6ce80a3a, 0xd2663f19, 0x6cdf153a, 0xd25d6ebc,
-  0x6cd61e7f, 0xd254a021, 0x6ccd2609, 0xd24bd34a,
-  0x6cc42bd9, 0xd2430835, 0x6cbb2fef, 0xd23a3ee4,
-  0x6cb2324c, 0xd2317756, 0x6ca932ef, 0xd228b18d,
-  0x6ca031da, 0xd21fed88, 0x6c972f0d, 0xd2172b48,
-  0x6c8e2a87, 0xd20e6acc, 0x6c85244a, 0xd205ac17,
-  0x6c7c1c55, 0xd1fcef27, 0x6c7312a9, 0xd1f433fd,
-  0x6c6a0746, 0xd1eb7a9a, 0x6c60fa2d, 0xd1e2c2fd,
-  0x6c57eb5e, 0xd1da0d28, 0x6c4edada, 0xd1d1591a,
-  0x6c45c8a0, 0xd1c8a6d4, 0x6c3cb4b1, 0xd1bff656,
-  0x6c339f0e, 0xd1b747a0, 0x6c2a87b6, 0xd1ae9ab4,
-  0x6c216eaa, 0xd1a5ef90, 0x6c1853eb, 0xd19d4636,
-  0x6c0f3779, 0xd1949ea6, 0x6c061953, 0xd18bf8e0,
-  0x6bfcf97c, 0xd18354e4, 0x6bf3d7f2, 0xd17ab2b3,
-  0x6beab4b6, 0xd172124d, 0x6be18fc9, 0xd16973b3,
-  0x6bd8692b, 0xd160d6e5, 0x6bcf40dc, 0xd1583be2,
-  0x6bc616dd, 0xd14fa2ad, 0x6bbceb2d, 0xd1470b44,
-  0x6bb3bdce, 0xd13e75a8, 0x6baa8ec0, 0xd135e1d9,
-  0x6ba15e03, 0xd12d4fd9, 0x6b982b97, 0xd124bfa6,
-  0x6b8ef77d, 0xd11c3142, 0x6b85c1b5, 0xd113a4ad,
-  0x6b7c8a3f, 0xd10b19e7, 0x6b73511c, 0xd10290f0,
-  0x6b6a164d, 0xd0fa09c9, 0x6b60d9d0, 0xd0f18472,
-  0x6b579ba8, 0xd0e900ec, 0x6b4e5bd4, 0xd0e07f36,
-  0x6b451a55, 0xd0d7ff51, 0x6b3bd72a, 0xd0cf813e,
-  0x6b329255, 0xd0c704fd, 0x6b294bd5, 0xd0be8a8d,
-  0x6b2003ac, 0xd0b611f1, 0x6b16b9d9, 0xd0ad9b26,
-  0x6b0d6e5c, 0xd0a5262f, 0x6b042137, 0xd09cb30b,
-  0x6afad269, 0xd09441bb, 0x6af181f3, 0xd08bd23f,
-  0x6ae82fd5, 0xd0836497, 0x6adedc10, 0xd07af8c4,
-  0x6ad586a3, 0xd0728ec6, 0x6acc2f90, 0xd06a269d,
-  0x6ac2d6d6, 0xd061c04a, 0x6ab97c77, 0xd0595bcd,
-  0x6ab02071, 0xd050f926, 0x6aa6c2c6, 0xd0489856,
-  0x6a9d6377, 0xd040395d, 0x6a940283, 0xd037dc3b,
-  0x6a8a9fea, 0xd02f80f1, 0x6a813bae, 0xd027277e,
-  0x6a77d5ce, 0xd01ecfe4, 0x6a6e6e4b, 0xd0167a22,
-  0x6a650525, 0xd00e2639, 0x6a5b9a5d, 0xd005d42a,
-  0x6a522df3, 0xcffd83f4, 0x6a48bfe7, 0xcff53597,
-  0x6a3f503a, 0xcfece915, 0x6a35deeb, 0xcfe49e6d,
-  0x6a2c6bfd, 0xcfdc55a1, 0x6a22f76e, 0xcfd40eaf,
-  0x6a19813f, 0xcfcbc999, 0x6a100970, 0xcfc3865e,
-  0x6a069003, 0xcfbb4500, 0x69fd14f6, 0xcfb3057d,
-  0x69f3984c, 0xcfaac7d8, 0x69ea1a03, 0xcfa28c10,
-  0x69e09a1c, 0xcf9a5225, 0x69d71899, 0xcf921a17,
-  0x69cd9578, 0xcf89e3e8, 0x69c410ba, 0xcf81af97,
-  0x69ba8a61, 0xcf797d24, 0x69b1026c, 0xcf714c91,
-  0x69a778db, 0xcf691ddd, 0x699dedaf, 0xcf60f108,
-  0x699460e8, 0xcf58c613, 0x698ad287, 0xcf509cfe,
-  0x6981428c, 0xcf4875ca, 0x6977b0f7, 0xcf405077,
-  0x696e1dc9, 0xcf382d05, 0x69648902, 0xcf300b74,
-  0x695af2a3, 0xcf27ebc5, 0x69515aab, 0xcf1fcdf8,
-  0x6947c11c, 0xcf17b20d, 0x693e25f5, 0xcf0f9805,
-  0x69348937, 0xcf077fe1, 0x692aeae3, 0xceff699f,
-  0x69214af8, 0xcef75541, 0x6917a977, 0xceef42c7,
-  0x690e0661, 0xcee73231, 0x690461b5, 0xcedf2380,
-  0x68fabb75, 0xced716b4, 0x68f113a0, 0xcecf0bcd,
-  0x68e76a37, 0xcec702cb, 0x68ddbf3b, 0xcebefbb0,
-  0x68d412ab, 0xceb6f67a, 0x68ca6488, 0xceaef32b,
-  0x68c0b4d2, 0xcea6f1c2, 0x68b7038b, 0xce9ef241,
-  0x68ad50b1, 0xce96f4a7, 0x68a39c46, 0xce8ef8f4,
-  0x6899e64a, 0xce86ff2a, 0x68902ebd, 0xce7f0748,
-  0x688675a0, 0xce77114e, 0x687cbaf3, 0xce6f1d3d,
-  0x6872feb6, 0xce672b16, 0x686940ea, 0xce5f3ad8,
-  0x685f8190, 0xce574c84, 0x6855c0a6, 0xce4f6019,
-  0x684bfe2f, 0xce47759a, 0x68423a2a, 0xce3f8d05,
-  0x68387498, 0xce37a65b, 0x682ead78, 0xce2fc19c,
-  0x6824e4cc, 0xce27dec9, 0x681b1a94, 0xce1ffde2,
-  0x68114ed0, 0xce181ee8, 0x68078181, 0xce1041d9,
-  0x67fdb2a7, 0xce0866b8, 0x67f3e241, 0xce008d84,
-  0x67ea1052, 0xcdf8b63d, 0x67e03cd8, 0xcdf0e0e4,
-  0x67d667d5, 0xcde90d79, 0x67cc9149, 0xcde13bfd,
-  0x67c2b934, 0xcdd96c6f, 0x67b8df97, 0xcdd19ed0,
-  0x67af0472, 0xcdc9d320, 0x67a527c4, 0xcdc20960,
-  0x679b4990, 0xcdba4190, 0x679169d5, 0xcdb27bb0,
-  0x67878893, 0xcdaab7c0, 0x677da5cb, 0xcda2f5c2,
-  0x6773c17d, 0xcd9b35b4, 0x6769dbaa, 0xcd937798,
-  0x675ff452, 0xcd8bbb6d, 0x67560b76, 0xcd840134,
-  0x674c2115, 0xcd7c48ee, 0x67423530, 0xcd74929a,
-  0x673847c8, 0xcd6cde39, 0x672e58dc, 0xcd652bcb,
-  0x6724686e, 0xcd5d7b50, 0x671a767e, 0xcd55ccca,
-  0x6710830c, 0xcd4e2037, 0x67068e18, 0xcd467599,
-  0x66fc97a3, 0xcd3eccef, 0x66f29fad, 0xcd37263a,
-  0x66e8a637, 0xcd2f817b, 0x66deab41, 0xcd27deb0,
-  0x66d4aecb, 0xcd203ddc, 0x66cab0d6, 0xcd189efe,
-  0x66c0b162, 0xcd110216, 0x66b6b070, 0xcd096725,
-  0x66acadff, 0xcd01ce2b, 0x66a2aa11, 0xccfa3729,
-  0x6698a4a6, 0xccf2a21d, 0x668e9dbd, 0xcceb0f0a,
-  0x66849558, 0xcce37def, 0x667a8b77, 0xccdbeecc,
-  0x6670801a, 0xccd461a2, 0x66667342, 0xccccd671,
-  0x665c64ef, 0xccc54d3a, 0x66525521, 0xccbdc5fc,
-  0x664843d9, 0xccb640b8, 0x663e3117, 0xccaebd6e,
-  0x66341cdb, 0xcca73c1e, 0x662a0727, 0xcc9fbcca,
-  0x661feffa, 0xcc983f70, 0x6615d754, 0xcc90c412,
-  0x660bbd37, 0xcc894aaf, 0x6601a1a2, 0xcc81d349,
-  0x65f78497, 0xcc7a5dde, 0x65ed6614, 0xcc72ea70,
-  0x65e3461b, 0xcc6b78ff, 0x65d924ac, 0xcc64098b,
-  0x65cf01c8, 0xcc5c9c14, 0x65c4dd6e, 0xcc55309b,
-  0x65bab7a0, 0xcc4dc720, 0x65b0905d, 0xcc465fa3,
-  0x65a667a7, 0xcc3efa25, 0x659c3d7c, 0xcc3796a5,
-  0x659211df, 0xcc303524, 0x6587e4cf, 0xcc28d5a3,
-  0x657db64c, 0xcc217822, 0x65738657, 0xcc1a1ca0,
-  0x656954f1, 0xcc12c31f, 0x655f2219, 0xcc0b6b9e,
-  0x6554edd1, 0xcc04161e, 0x654ab818, 0xcbfcc29f,
-  0x654080ef, 0xcbf57121, 0x65364857, 0xcbee21a5,
-  0x652c0e4f, 0xcbe6d42b, 0x6521d2d8, 0xcbdf88b3,
-  0x651795f3, 0xcbd83f3d, 0x650d57a0, 0xcbd0f7ca,
-  0x650317df, 0xcbc9b25a, 0x64f8d6b0, 0xcbc26eee,
-  0x64ee9415, 0xcbbb2d85, 0x64e4500e, 0xcbb3ee20,
-  0x64da0a9a, 0xcbacb0bf, 0x64cfc3ba, 0xcba57563,
-  0x64c57b6f, 0xcb9e3c0b, 0x64bb31ba, 0xcb9704b9,
-  0x64b0e699, 0xcb8fcf6b, 0x64a69a0f, 0xcb889c23,
-  0x649c4c1b, 0xcb816ae1, 0x6491fcbe, 0xcb7a3ba5,
-  0x6487abf7, 0xcb730e70, 0x647d59c8, 0xcb6be341,
-  0x64730631, 0xcb64ba19, 0x6468b132, 0xcb5d92f8,
-  0x645e5acc, 0xcb566ddf, 0x645402ff, 0xcb4f4acd,
-  0x6449a9cc, 0xcb4829c4, 0x643f4f32, 0xcb410ac3,
-  0x6434f332, 0xcb39edca, 0x642a95ce, 0xcb32d2da,
-  0x64203704, 0xcb2bb9f4, 0x6415d6d5, 0xcb24a316,
-  0x640b7543, 0xcb1d8e43, 0x6401124d, 0xcb167b79,
-  0x63f6adf3, 0xcb0f6aba, 0x63ec4837, 0xcb085c05,
-  0x63e1e117, 0xcb014f5b, 0x63d77896, 0xcafa44bc,
-  0x63cd0eb3, 0xcaf33c28, 0x63c2a36f, 0xcaec35a0,
-  0x63b836ca, 0xcae53123, 0x63adc8c4, 0xcade2eb3,
-  0x63a3595e, 0xcad72e4f, 0x6398e898, 0xcad02ff8,
-  0x638e7673, 0xcac933ae, 0x638402ef, 0xcac23971,
-  0x63798e0d, 0xcabb4141, 0x636f17cc, 0xcab44b1f,
-  0x6364a02e, 0xcaad570c, 0x635a2733, 0xcaa66506,
-  0x634facda, 0xca9f750f, 0x63453125, 0xca988727,
-  0x633ab414, 0xca919b4e, 0x633035a7, 0xca8ab184,
-  0x6325b5df, 0xca83c9ca, 0x631b34bc, 0xca7ce420,
-  0x6310b23e, 0xca760086, 0x63062e67, 0xca6f1efc,
-  0x62fba936, 0xca683f83, 0x62f122ab, 0xca61621b,
-  0x62e69ac8, 0xca5a86c4, 0x62dc118c, 0xca53ad7e,
-  0x62d186f8, 0xca4cd64b, 0x62c6fb0c, 0xca460129,
-  0x62bc6dca, 0xca3f2e19, 0x62b1df30, 0xca385d1d,
-  0x62a74f40, 0xca318e32, 0x629cbdfa, 0xca2ac15b,
-  0x62922b5e, 0xca23f698, 0x6287976e, 0xca1d2de7,
-  0x627d0228, 0xca16674b, 0x62726b8e, 0xca0fa2c3,
-  0x6267d3a0, 0xca08e04f, 0x625d3a5e, 0xca021fef,
-  0x62529fca, 0xc9fb61a5, 0x624803e2, 0xc9f4a570,
-  0x623d66a8, 0xc9edeb50, 0x6232c81c, 0xc9e73346,
-  0x6228283f, 0xc9e07d51, 0x621d8711, 0xc9d9c973,
-  0x6212e492, 0xc9d317ab, 0x620840c2, 0xc9cc67fa,
-  0x61fd9ba3, 0xc9c5ba60, 0x61f2f534, 0xc9bf0edd,
-  0x61e84d76, 0xc9b86572, 0x61dda46a, 0xc9b1be1e,
-  0x61d2fa0f, 0xc9ab18e3, 0x61c84e67, 0xc9a475bf,
-  0x61bda171, 0xc99dd4b4, 0x61b2f32e, 0xc99735c2,
-  0x61a8439e, 0xc99098e9, 0x619d92c2, 0xc989fe29,
-  0x6192e09b, 0xc9836582, 0x61882d28, 0xc97ccef5,
-  0x617d786a, 0xc9763a83, 0x6172c262, 0xc96fa82a,
-  0x61680b0f, 0xc96917ec, 0x615d5273, 0xc96289c9,
-  0x6152988d, 0xc95bfdc1, 0x6147dd5f, 0xc95573d4,
-  0x613d20e8, 0xc94eec03, 0x61326329, 0xc948664d,
-  0x6127a423, 0xc941e2b4, 0x611ce3d5, 0xc93b6137,
-  0x61122240, 0xc934e1d6, 0x61075f65, 0xc92e6492,
-  0x60fc9b44, 0xc927e96b, 0x60f1d5de, 0xc9217062,
-  0x60e70f32, 0xc91af976, 0x60dc4742, 0xc91484a8,
-  0x60d17e0d, 0xc90e11f7, 0x60c6b395, 0xc907a166,
-  0x60bbe7d8, 0xc90132f2, 0x60b11ad9, 0xc8fac69e,
-  0x60a64c97, 0xc8f45c68, 0x609b7d13, 0xc8edf452,
-  0x6090ac4d, 0xc8e78e5b, 0x6085da46, 0xc8e12a84,
-  0x607b06fe, 0xc8dac8cd, 0x60703275, 0xc8d46936,
-  0x60655cac, 0xc8ce0bc0, 0x605a85a3, 0xc8c7b06b,
-  0x604fad5b, 0xc8c15736, 0x6044d3d4, 0xc8bb0023,
-  0x6039f90f, 0xc8b4ab32, 0x602f1d0b, 0xc8ae5862,
-  0x60243fca, 0xc8a807b4, 0x6019614c, 0xc8a1b928,
-  0x600e8190, 0xc89b6cbf, 0x6003a099, 0xc8952278,
-  0x5ff8be65, 0xc88eda54, 0x5feddaf6, 0xc8889454,
-  0x5fe2f64c, 0xc8825077, 0x5fd81067, 0xc87c0ebd,
-  0x5fcd2948, 0xc875cf28, 0x5fc240ef, 0xc86f91b7,
-  0x5fb7575c, 0xc869566a, 0x5fac6c91, 0xc8631d42,
-  0x5fa1808c, 0xc85ce63e, 0x5f969350, 0xc856b160,
-  0x5f8ba4dc, 0xc8507ea7, 0x5f80b531, 0xc84a4e14,
-  0x5f75c44e, 0xc8441fa6, 0x5f6ad235, 0xc83df35f,
-  0x5f5fdee6, 0xc837c93e, 0x5f54ea62, 0xc831a143,
-  0x5f49f4a8, 0xc82b7b70, 0x5f3efdb9, 0xc82557c3,
-  0x5f340596, 0xc81f363d, 0x5f290c3f, 0xc81916df,
-  0x5f1e11b5, 0xc812f9a9, 0x5f1315f7, 0xc80cde9b,
-  0x5f081907, 0xc806c5b5, 0x5efd1ae4, 0xc800aef7,
-  0x5ef21b90, 0xc7fa9a62, 0x5ee71b0a, 0xc7f487f6,
-  0x5edc1953, 0xc7ee77b3, 0x5ed1166b, 0xc7e8699a,
-  0x5ec61254, 0xc7e25daa, 0x5ebb0d0d, 0xc7dc53e3,
-  0x5eb00696, 0xc7d64c47, 0x5ea4fef0, 0xc7d046d6,
-  0x5e99f61d, 0xc7ca438f, 0x5e8eec1b, 0xc7c44272,
-  0x5e83e0eb, 0xc7be4381, 0x5e78d48e, 0xc7b846ba,
-  0x5e6dc705, 0xc7b24c20, 0x5e62b84f, 0xc7ac53b1,
-  0x5e57a86d, 0xc7a65d6e, 0x5e4c9760, 0xc7a06957,
-  0x5e418528, 0xc79a776c, 0x5e3671c5, 0xc79487ae,
-  0x5e2b5d38, 0xc78e9a1d, 0x5e204781, 0xc788aeb9,
-  0x5e1530a1, 0xc782c582, 0x5e0a1898, 0xc77cde79,
-  0x5dfeff67, 0xc776f99d, 0x5df3e50d, 0xc77116f0,
-  0x5de8c98c, 0xc76b3671, 0x5dddace4, 0xc7655820,
-  0x5dd28f15, 0xc75f7bfe, 0x5dc7701f, 0xc759a20a,
-  0x5dbc5004, 0xc753ca46, 0x5db12ec3, 0xc74df4b1,
-  0x5da60c5d, 0xc748214c, 0x5d9ae8d2, 0xc7425016,
-  0x5d8fc424, 0xc73c8111, 0x5d849e51, 0xc736b43c,
-  0x5d79775c, 0xc730e997, 0x5d6e4f43, 0xc72b2123,
-  0x5d632608, 0xc7255ae0, 0x5d57fbaa, 0xc71f96ce,
-  0x5d4cd02c, 0xc719d4ed, 0x5d41a38c, 0xc714153e,
-  0x5d3675cb, 0xc70e57c0, 0x5d2b46ea, 0xc7089c75,
-  0x5d2016e9, 0xc702e35c, 0x5d14e5c9, 0xc6fd2c75,
-  0x5d09b389, 0xc6f777c1, 0x5cfe802b, 0xc6f1c540,
-  0x5cf34baf, 0xc6ec14f2, 0x5ce81615, 0xc6e666d7,
-  0x5cdcdf5e, 0xc6e0baf0, 0x5cd1a78a, 0xc6db113d,
-  0x5cc66e99, 0xc6d569be, 0x5cbb348d, 0xc6cfc472,
-  0x5caff965, 0xc6ca215c, 0x5ca4bd21, 0xc6c4807a,
-  0x5c997fc4, 0xc6bee1cd, 0x5c8e414b, 0xc6b94554,
-  0x5c8301b9, 0xc6b3ab12, 0x5c77c10e, 0xc6ae1304,
-  0x5c6c7f4a, 0xc6a87d2d, 0x5c613c6d, 0xc6a2e98b,
-  0x5c55f878, 0xc69d5820, 0x5c4ab36b, 0xc697c8eb,
-  0x5c3f6d47, 0xc6923bec, 0x5c34260c, 0xc68cb124,
-  0x5c28ddbb, 0xc6872894, 0x5c1d9454, 0xc681a23a,
-  0x5c1249d8, 0xc67c1e18, 0x5c06fe46, 0xc6769c2e,
-  0x5bfbb1a0, 0xc6711c7b, 0x5bf063e6, 0xc66b9f01,
-  0x5be51518, 0xc66623be, 0x5bd9c537, 0xc660aab5,
-  0x5bce7442, 0xc65b33e4, 0x5bc3223c, 0xc655bf4c,
-  0x5bb7cf23, 0xc6504ced, 0x5bac7af9, 0xc64adcc7,
-  0x5ba125bd, 0xc6456edb, 0x5b95cf71, 0xc6400329,
-  0x5b8a7815, 0xc63a99b1, 0x5b7f1fa9, 0xc6353273,
-  0x5b73c62d, 0xc62fcd6f, 0x5b686ba3, 0xc62a6aa6,
-  0x5b5d100a, 0xc6250a18, 0x5b51b363, 0xc61fabc4,
-  0x5b4655ae, 0xc61a4fac, 0x5b3af6ec, 0xc614f5cf,
-  0x5b2f971e, 0xc60f9e2e, 0x5b243643, 0xc60a48c9,
-  0x5b18d45c, 0xc604f5a0, 0x5b0d716a, 0xc5ffa4b3,
-  0x5b020d6c, 0xc5fa5603, 0x5af6a865, 0xc5f5098f,
-  0x5aeb4253, 0xc5efbf58, 0x5adfdb37, 0xc5ea775e,
-  0x5ad47312, 0xc5e531a1, 0x5ac909e5, 0xc5dfee22,
-  0x5abd9faf, 0xc5daace1, 0x5ab23471, 0xc5d56ddd,
-  0x5aa6c82b, 0xc5d03118, 0x5a9b5adf, 0xc5caf690,
-  0x5a8fec8c, 0xc5c5be47, 0x5a847d33, 0xc5c0883d,
-  0x5a790cd4, 0xc5bb5472, 0x5a6d9b70, 0xc5b622e6,
-  0x5a622907, 0xc5b0f399, 0x5a56b599, 0xc5abc68c,
-  0x5a4b4128, 0xc5a69bbe, 0x5a3fcbb3, 0xc5a17330,
-  0x5a34553b, 0xc59c4ce3, 0x5a28ddc0, 0xc59728d5,
-  0x5a1d6544, 0xc5920708, 0x5a11ebc5, 0xc58ce77c,
-  0x5a067145, 0xc587ca31, 0x59faf5c5, 0xc582af26,
-  0x59ef7944, 0xc57d965d, 0x59e3fbc3, 0xc5787fd6,
-  0x59d87d42, 0xc5736b90, 0x59ccfdc2, 0xc56e598c,
-  0x59c17d44, 0xc56949ca, 0x59b5fbc8, 0xc5643c4a,
-  0x59aa794d, 0xc55f310d, 0x599ef5d6, 0xc55a2812,
-  0x59937161, 0xc555215a, 0x5987ebf0, 0xc5501ce5,
-  0x597c6584, 0xc54b1ab4, 0x5970de1b, 0xc5461ac6,
-  0x596555b8, 0xc5411d1b, 0x5959cc5a, 0xc53c21b4,
-  0x594e4201, 0xc5372891, 0x5942b6af, 0xc53231b3,
-  0x59372a64, 0xc52d3d18, 0x592b9d1f, 0xc5284ac3,
-  0x59200ee3, 0xc5235ab2, 0x59147fae, 0xc51e6ce6,
-  0x5908ef82, 0xc519815f, 0x58fd5e5f, 0xc514981d,
-  0x58f1cc45, 0xc50fb121, 0x58e63935, 0xc50acc6b,
-  0x58daa52f, 0xc505e9fb, 0x58cf1034, 0xc50109d0,
-  0x58c37a44, 0xc4fc2bec, 0x58b7e35f, 0xc4f7504e,
-  0x58ac4b87, 0xc4f276f7, 0x58a0b2bb, 0xc4ed9fe7,
-  0x589518fc, 0xc4e8cb1e, 0x58897e4a, 0xc4e3f89c,
-  0x587de2a7, 0xc4df2862, 0x58724611, 0xc4da5a6f,
-  0x5866a88a, 0xc4d58ec3, 0x585b0a13, 0xc4d0c560,
-  0x584f6aab, 0xc4cbfe45, 0x5843ca53, 0xc4c73972,
-  0x5838290c, 0xc4c276e8, 0x582c86d5, 0xc4bdb6a6,
-  0x5820e3b0, 0xc4b8f8ad, 0x58153f9d, 0xc4b43cfd,
-  0x58099a9c, 0xc4af8397, 0x57fdf4ae, 0xc4aacc7a,
-  0x57f24dd3, 0xc4a617a6, 0x57e6a60c, 0xc4a1651c,
-  0x57dafd59, 0xc49cb4dd, 0x57cf53bb, 0xc49806e7,
-  0x57c3a931, 0xc4935b3c, 0x57b7fdbd, 0xc48eb1db,
-  0x57ac515f, 0xc48a0ac4, 0x57a0a417, 0xc48565f9,
-  0x5794f5e6, 0xc480c379, 0x578946cc, 0xc47c2344,
-  0x577d96ca, 0xc477855a, 0x5771e5e0, 0xc472e9bc,
-  0x5766340f, 0xc46e5069, 0x575a8157, 0xc469b963,
-  0x574ecdb8, 0xc46524a9, 0x57431933, 0xc460923b,
-  0x573763c9, 0xc45c0219, 0x572bad7a, 0xc4577444,
-  0x571ff646, 0xc452e8bc, 0x57143e2d, 0xc44e5f80,
-  0x57088531, 0xc449d892, 0x56fccb51, 0xc44553f2,
-  0x56f1108f, 0xc440d19e, 0x56e554ea, 0xc43c5199,
-  0x56d99864, 0xc437d3e1, 0x56cddafb, 0xc4335877,
-  0x56c21cb2, 0xc42edf5c, 0x56b65d88, 0xc42a688f,
-  0x56aa9d7e, 0xc425f410, 0x569edc94, 0xc42181e0,
-  0x56931acb, 0xc41d11ff, 0x56875823, 0xc418a46d,
-  0x567b949d, 0xc414392b, 0x566fd039, 0xc40fd037,
-  0x56640af7, 0xc40b6994, 0x565844d8, 0xc4070540,
-  0x564c7ddd, 0xc402a33c, 0x5640b606, 0xc3fe4388,
-  0x5634ed53, 0xc3f9e624, 0x562923c5, 0xc3f58b10,
-  0x561d595d, 0xc3f1324e, 0x56118e1a, 0xc3ecdbdc,
-  0x5605c1fd, 0xc3e887bb, 0x55f9f507, 0xc3e435ea,
-  0x55ee2738, 0xc3dfe66c, 0x55e25890, 0xc3db993e,
-  0x55d68911, 0xc3d74e62, 0x55cab8ba, 0xc3d305d8,
-  0x55bee78c, 0xc3cebfa0, 0x55b31587, 0xc3ca7bba,
-  0x55a742ac, 0xc3c63a26, 0x559b6efb, 0xc3c1fae5,
-  0x558f9a76, 0xc3bdbdf6, 0x5583c51b, 0xc3b9835a,
-  0x5577eeec, 0xc3b54b11, 0x556c17e9, 0xc3b1151b,
-  0x55604013, 0xc3ace178, 0x5554676a, 0xc3a8b028,
-  0x55488dee, 0xc3a4812c, 0x553cb3a0, 0xc3a05484,
-  0x5530d881, 0xc39c2a2f, 0x5524fc90, 0xc398022f,
-  0x55191fcf, 0xc393dc82, 0x550d423d, 0xc38fb92a,
-  0x550163dc, 0xc38b9827, 0x54f584ac, 0xc3877978,
-  0x54e9a4ac, 0xc3835d1e, 0x54ddc3de, 0xc37f4319,
-  0x54d1e242, 0xc37b2b6a, 0x54c5ffd9, 0xc377160f,
-  0x54ba1ca3, 0xc373030a, 0x54ae38a0, 0xc36ef25b,
-  0x54a253d1, 0xc36ae401, 0x54966e36, 0xc366d7fd,
-  0x548a87d1, 0xc362ce50, 0x547ea0a0, 0xc35ec6f8,
-  0x5472b8a5, 0xc35ac1f7, 0x5466cfe1, 0xc356bf4d,
-  0x545ae653, 0xc352bef9, 0x544efbfc, 0xc34ec0fc,
-  0x544310dd, 0xc34ac556, 0x543724f5, 0xc346cc07,
-  0x542b3846, 0xc342d510, 0x541f4ad1, 0xc33ee070,
-  0x54135c94, 0xc33aee27, 0x54076d91, 0xc336fe37,
-  0x53fb7dc9, 0xc333109e, 0x53ef8d3c, 0xc32f255e,
-  0x53e39be9, 0xc32b3c75, 0x53d7a9d3, 0xc32755e5,
-  0x53cbb6f8, 0xc32371ae, 0x53bfc35b, 0xc31f8fcf,
-  0x53b3cefa, 0xc31bb049, 0x53a7d9d7, 0xc317d31c,
-  0x539be3f2, 0xc313f848, 0x538fed4b, 0xc3101fce,
-  0x5383f5e3, 0xc30c49ad, 0x5377fdbb, 0xc30875e5,
-  0x536c04d2, 0xc304a477, 0x53600b2a, 0xc300d563,
-  0x535410c3, 0xc2fd08a9, 0x5348159d, 0xc2f93e4a,
-  0x533c19b8, 0xc2f57644, 0x53301d16, 0xc2f1b099,
-  0x53241fb6, 0xc2eded49, 0x5318219a, 0xc2ea2c53,
-  0x530c22c1, 0xc2e66db8, 0x5300232c, 0xc2e2b178,
-  0x52f422db, 0xc2def794, 0x52e821cf, 0xc2db400a,
-  0x52dc2009, 0xc2d78add, 0x52d01d89, 0xc2d3d80a,
-  0x52c41a4f, 0xc2d02794, 0x52b8165b, 0xc2cc7979,
-  0x52ac11af, 0xc2c8cdbb, 0x52a00c4b, 0xc2c52459,
-  0x5294062f, 0xc2c17d52, 0x5287ff5b, 0xc2bdd8a9,
-  0x527bf7d1, 0xc2ba365c, 0x526fef90, 0xc2b6966c,
-  0x5263e699, 0xc2b2f8d8, 0x5257dced, 0xc2af5da2,
-  0x524bd28c, 0xc2abc4c9, 0x523fc776, 0xc2a82e4d,
-  0x5233bbac, 0xc2a49a2e, 0x5227af2e, 0xc2a1086d,
-  0x521ba1fd, 0xc29d790a, 0x520f941a, 0xc299ec05,
-  0x52038584, 0xc296615d, 0x51f7763c, 0xc292d914,
-  0x51eb6643, 0xc28f5329, 0x51df5599, 0xc28bcf9c,
-  0x51d3443f, 0xc2884e6e, 0x51c73235, 0xc284cf9f,
-  0x51bb1f7c, 0xc281532e, 0x51af0c13, 0xc27dd91c,
-  0x51a2f7fc, 0xc27a616a, 0x5196e337, 0xc276ec16,
-  0x518acdc4, 0xc2737922, 0x517eb7a4, 0xc270088e,
-  0x5172a0d7, 0xc26c9a58, 0x5166895f, 0xc2692e83,
-  0x515a713a, 0xc265c50e, 0x514e586a, 0xc2625df8,
-  0x51423ef0, 0xc25ef943, 0x513624cb, 0xc25b96ee,
-  0x512a09fc, 0xc25836f9, 0x511dee84, 0xc254d965,
-  0x5111d263, 0xc2517e31, 0x5105b599, 0xc24e255e,
-  0x50f99827, 0xc24aceed, 0x50ed7a0e, 0xc2477adc,
-  0x50e15b4e, 0xc244292c, 0x50d53be7, 0xc240d9de,
-  0x50c91bda, 0xc23d8cf1, 0x50bcfb28, 0xc23a4265,
-  0x50b0d9d0, 0xc236fa3b, 0x50a4b7d3, 0xc233b473,
-  0x50989532, 0xc230710d, 0x508c71ee, 0xc22d3009,
-  0x50804e06, 0xc229f167, 0x5074297b, 0xc226b528,
-  0x5068044e, 0xc2237b4b, 0x505bde7f, 0xc22043d0,
-  0x504fb80e, 0xc21d0eb8, 0x504390fd, 0xc219dc03,
-  0x5037694b, 0xc216abb1, 0x502b40f8, 0xc2137dc2,
-  0x501f1807, 0xc2105236, 0x5012ee76, 0xc20d290d,
-  0x5006c446, 0xc20a0248, 0x4ffa9979, 0xc206dde6,
-  0x4fee6e0d, 0xc203bbe8, 0x4fe24205, 0xc2009c4e,
-  0x4fd6155f, 0xc1fd7f17, 0x4fc9e81e, 0xc1fa6445,
-  0x4fbdba40, 0xc1f74bd6, 0x4fb18bc8, 0xc1f435cc,
-  0x4fa55cb4, 0xc1f12227, 0x4f992d06, 0xc1ee10e5,
-  0x4f8cfcbe, 0xc1eb0209, 0x4f80cbdc, 0xc1e7f591,
-  0x4f749a61, 0xc1e4eb7e, 0x4f68684e, 0xc1e1e3d0,
-  0x4f5c35a3, 0xc1dede87, 0x4f500260, 0xc1dbdba3,
-  0x4f43ce86, 0xc1d8db25, 0x4f379a16, 0xc1d5dd0c,
-  0x4f2b650f, 0xc1d2e158, 0x4f1f2f73, 0xc1cfe80a,
-  0x4f12f941, 0xc1ccf122, 0x4f06c27a, 0xc1c9fca0,
-  0x4efa8b20, 0xc1c70a84, 0x4eee5331, 0xc1c41ace,
-  0x4ee21aaf, 0xc1c12d7e, 0x4ed5e19a, 0xc1be4294,
-  0x4ec9a7f3, 0xc1bb5a11, 0x4ebd6db9, 0xc1b873f5,
-  0x4eb132ef, 0xc1b5903f, 0x4ea4f793, 0xc1b2aef0,
-  0x4e98bba7, 0xc1afd007, 0x4e8c7f2a, 0xc1acf386,
-  0x4e80421e, 0xc1aa196c, 0x4e740483, 0xc1a741b9,
-  0x4e67c65a, 0xc1a46c6e, 0x4e5b87a2, 0xc1a1998a,
-  0x4e4f485c, 0xc19ec90d, 0x4e430889, 0xc19bfaf9,
-  0x4e36c82a, 0xc1992f4c, 0x4e2a873e, 0xc1966606,
-  0x4e1e45c6, 0xc1939f29, 0x4e1203c3, 0xc190dab4,
-  0x4e05c135, 0xc18e18a7, 0x4df97e1d, 0xc18b5903,
-  0x4ded3a7b, 0xc1889bc6, 0x4de0f64f, 0xc185e0f3,
-  0x4dd4b19a, 0xc1832888, 0x4dc86c5d, 0xc1807285,
-  0x4dbc2698, 0xc17dbeec, 0x4dafe04b, 0xc17b0dbb,
-  0x4da39978, 0xc1785ef4, 0x4d97521d, 0xc175b296,
-  0x4d8b0a3d, 0xc17308a1, 0x4d7ec1d6, 0xc1706115,
-  0x4d7278eb, 0xc16dbbf3, 0x4d662f7b, 0xc16b193a,
-  0x4d59e586, 0xc16878eb, 0x4d4d9b0e, 0xc165db05,
-  0x4d415013, 0xc1633f8a, 0x4d350495, 0xc160a678,
-  0x4d28b894, 0xc15e0fd1, 0x4d1c6c11, 0xc15b7b94,
-  0x4d101f0e, 0xc158e9c1, 0x4d03d189, 0xc1565a58,
-  0x4cf78383, 0xc153cd5a, 0x4ceb34fe, 0xc15142c6,
-  0x4cdee5f9, 0xc14eba9d, 0x4cd29676, 0xc14c34df,
-  0x4cc64673, 0xc149b18b, 0x4cb9f5f3, 0xc14730a3,
-  0x4cada4f5, 0xc144b225, 0x4ca1537a, 0xc1423613,
-  0x4c950182, 0xc13fbc6c, 0x4c88af0e, 0xc13d4530,
-  0x4c7c5c1e, 0xc13ad060, 0x4c7008b3, 0xc1385dfb,
-  0x4c63b4ce, 0xc135ee02, 0x4c57606e, 0xc1338075,
-  0x4c4b0b94, 0xc1311553, 0x4c3eb641, 0xc12eac9d,
-  0x4c326075, 0xc12c4653, 0x4c260a31, 0xc129e276,
-  0x4c19b374, 0xc1278104, 0x4c0d5c41, 0xc12521ff,
-  0x4c010496, 0xc122c566, 0x4bf4ac75, 0xc1206b39,
-  0x4be853de, 0xc11e1379, 0x4bdbfad1, 0xc11bbe26,
-  0x4bcfa150, 0xc1196b3f, 0x4bc34759, 0xc1171ac6,
-  0x4bb6ecef, 0xc114ccb9, 0x4baa9211, 0xc1128119,
-  0x4b9e36c0, 0xc11037e6, 0x4b91dafc, 0xc10df120,
-  0x4b857ec7, 0xc10bacc8, 0x4b79221f, 0xc1096add,
-  0x4b6cc506, 0xc1072b5f, 0x4b60677c, 0xc104ee4f,
-  0x4b540982, 0xc102b3ac, 0x4b47ab19, 0xc1007b77,
-  0x4b3b4c40, 0xc0fe45b0, 0x4b2eecf8, 0xc0fc1257,
-  0x4b228d42, 0xc0f9e16b, 0x4b162d1d, 0xc0f7b2ee,
-  0x4b09cc8c, 0xc0f586df, 0x4afd6b8d, 0xc0f35d3e,
-  0x4af10a22, 0xc0f1360b, 0x4ae4a84b, 0xc0ef1147,
-  0x4ad84609, 0xc0eceef1, 0x4acbe35b, 0xc0eacf09,
-  0x4abf8043, 0xc0e8b190, 0x4ab31cc1, 0xc0e69686,
-  0x4aa6b8d5, 0xc0e47deb, 0x4a9a5480, 0xc0e267be,
-  0x4a8defc3, 0xc0e05401, 0x4a818a9d, 0xc0de42b2,
-  0x4a752510, 0xc0dc33d2, 0x4a68bf1b, 0xc0da2762,
-  0x4a5c58c0, 0xc0d81d61, 0x4a4ff1fe, 0xc0d615cf,
-  0x4a438ad7, 0xc0d410ad, 0x4a37234a, 0xc0d20dfa,
-  0x4a2abb59, 0xc0d00db6, 0x4a1e5303, 0xc0ce0fe3,
-  0x4a11ea49, 0xc0cc147f, 0x4a05812c, 0xc0ca1b8a,
-  0x49f917ac, 0xc0c82506, 0x49ecadc9, 0xc0c630f2,
-  0x49e04385, 0xc0c43f4d, 0x49d3d8df, 0xc0c25019,
-  0x49c76dd8, 0xc0c06355, 0x49bb0271, 0xc0be7901,
-  0x49ae96aa, 0xc0bc911d, 0x49a22a83, 0xc0baabaa,
-  0x4995bdfd, 0xc0b8c8a7, 0x49895118, 0xc0b6e815,
-  0x497ce3d5, 0xc0b509f3, 0x49707635, 0xc0b32e42,
-  0x49640837, 0xc0b15502, 0x495799dd, 0xc0af7e33,
-  0x494b2b27, 0xc0ada9d4, 0x493ebc14, 0xc0abd7e6,
-  0x49324ca7, 0xc0aa086a, 0x4925dcdf, 0xc0a83b5e,
-  0x49196cbc, 0xc0a670c4, 0x490cfc40, 0xc0a4a89b,
-  0x49008b6a, 0xc0a2e2e3, 0x48f41a3c, 0xc0a11f9d,
-  0x48e7a8b5, 0xc09f5ec8, 0x48db36d6, 0xc09da065,
-  0x48cec4a0, 0xc09be473, 0x48c25213, 0xc09a2af3,
-  0x48b5df30, 0xc09873e4, 0x48a96bf6, 0xc096bf48,
-  0x489cf867, 0xc0950d1d, 0x48908483, 0xc0935d64,
-  0x4884104b, 0xc091b01d, 0x48779bbe, 0xc0900548,
-  0x486b26de, 0xc08e5ce5, 0x485eb1ab, 0xc08cb6f5,
-  0x48523c25, 0xc08b1376, 0x4845c64d, 0xc089726a,
-  0x48395024, 0xc087d3d0, 0x482cd9a9, 0xc08637a9,
-  0x482062de, 0xc0849df4, 0x4813ebc2, 0xc08306b2,
-  0x48077457, 0xc08171e2, 0x47fafc9c, 0xc07fdf85,
-  0x47ee8493, 0xc07e4f9b, 0x47e20c3b, 0xc07cc223,
-  0x47d59396, 0xc07b371e, 0x47c91aa3, 0xc079ae8c,
-  0x47bca163, 0xc078286e, 0x47b027d7, 0xc076a4c2,
-  0x47a3adff, 0xc0752389, 0x479733dc, 0xc073a4c3,
-  0x478ab96e, 0xc0722871, 0x477e3eb5, 0xc070ae92,
-  0x4771c3b3, 0xc06f3726, 0x47654867, 0xc06dc22e,
-  0x4758ccd2, 0xc06c4fa8, 0x474c50f4, 0xc06adf97,
-  0x473fd4cf, 0xc06971f9, 0x47335862, 0xc06806ce,
-  0x4726dbae, 0xc0669e18, 0x471a5eb3, 0xc06537d4,
-  0x470de172, 0xc063d405, 0x470163eb, 0xc06272aa,
-  0x46f4e620, 0xc06113c2, 0x46e86810, 0xc05fb74e,
-  0x46dbe9bb, 0xc05e5d4e, 0x46cf6b23, 0xc05d05c3,
-  0x46c2ec48, 0xc05bb0ab, 0x46b66d29, 0xc05a5e07,
-  0x46a9edc9, 0xc0590dd8, 0x469d6e27, 0xc057c01d,
-  0x4690ee44, 0xc05674d6, 0x46846e1f, 0xc0552c03,
-  0x4677edbb, 0xc053e5a5, 0x466b6d16, 0xc052a1bb,
-  0x465eec33, 0xc0516045, 0x46526b10, 0xc0502145,
-  0x4645e9af, 0xc04ee4b8, 0x46396810, 0xc04daaa1,
-  0x462ce634, 0xc04c72fe, 0x4620641a, 0xc04b3dcf,
-  0x4613e1c5, 0xc04a0b16, 0x46075f33, 0xc048dad1,
-  0x45fadc66, 0xc047ad01, 0x45ee595d, 0xc04681a6,
-  0x45e1d61b, 0xc04558c0, 0x45d5529e, 0xc044324f,
-  0x45c8cee7, 0xc0430e53, 0x45bc4af8, 0xc041eccc,
-  0x45afc6d0, 0xc040cdba, 0x45a3426f, 0xc03fb11d,
-  0x4596bdd7, 0xc03e96f6, 0x458a3908, 0xc03d7f44,
-  0x457db403, 0xc03c6a07, 0x45712ec7, 0xc03b573f,
-  0x4564a955, 0xc03a46ed, 0x455823ae, 0xc0393910,
-  0x454b9dd3, 0xc0382da8, 0x453f17c3, 0xc03724b6,
-  0x4532917f, 0xc0361e3a, 0x45260b08, 0xc0351a33,
-  0x4519845e, 0xc03418a2, 0x450cfd82, 0xc0331986,
-  0x45007674, 0xc0321ce0, 0x44f3ef35, 0xc03122b0,
-  0x44e767c5, 0xc0302af5, 0x44dae024, 0xc02f35b1,
-  0x44ce5854, 0xc02e42e2, 0x44c1d054, 0xc02d5289,
-  0x44b54825, 0xc02c64a6, 0x44a8bfc7, 0xc02b7939,
-  0x449c373c, 0xc02a9042, 0x448fae83, 0xc029a9c1,
-  0x4483259d, 0xc028c5b6, 0x44769c8b, 0xc027e421,
-  0x446a134c, 0xc0270502, 0x445d89e2, 0xc0262859,
-  0x4451004d, 0xc0254e27, 0x4444768d, 0xc024766a,
-  0x4437eca4, 0xc023a124, 0x442b6290, 0xc022ce54,
-  0x441ed854, 0xc021fdfb, 0x44124dee, 0xc0213018,
-  0x4405c361, 0xc02064ab, 0x43f938ac, 0xc01f9bb5,
-  0x43ecadcf, 0xc01ed535, 0x43e022cc, 0xc01e112b,
-  0x43d397a3, 0xc01d4f99, 0x43c70c54, 0xc01c907c,
-  0x43ba80df, 0xc01bd3d6, 0x43adf546, 0xc01b19a7,
-  0x43a16988, 0xc01a61ee, 0x4394dda7, 0xc019acac,
-  0x438851a2, 0xc018f9e1, 0x437bc57b, 0xc018498c,
-  0x436f3931, 0xc0179bae, 0x4362acc5, 0xc016f047,
-  0x43562038, 0xc0164757, 0x43499389, 0xc015a0dd,
-  0x433d06bb, 0xc014fcda, 0x433079cc, 0xc0145b4e,
-  0x4323ecbe, 0xc013bc39, 0x43175f91, 0xc0131f9b,
-  0x430ad245, 0xc0128574, 0x42fe44dc, 0xc011edc3,
-  0x42f1b755, 0xc011588a, 0x42e529b0, 0xc010c5c7,
-  0x42d89bf0, 0xc010357c, 0x42cc0e13, 0xc00fa7a8,
-  0x42bf801a, 0xc00f1c4a, 0x42b2f207, 0xc00e9364,
-  0x42a663d8, 0xc00e0cf5, 0x4299d590, 0xc00d88fd,
-  0x428d472e, 0xc00d077c, 0x4280b8b3, 0xc00c8872,
-  0x42742a1f, 0xc00c0be0, 0x42679b73, 0xc00b91c4,
-  0x425b0caf, 0xc00b1a20, 0x424e7dd4, 0xc00aa4f3,
-  0x4241eee2, 0xc00a323d, 0x42355fd9, 0xc009c1ff,
-  0x4228d0bb, 0xc0095438, 0x421c4188, 0xc008e8e8,
-  0x420fb240, 0xc008800f, 0x420322e3, 0xc00819ae,
-  0x41f69373, 0xc007b5c4, 0x41ea03ef, 0xc0075452,
-  0x41dd7459, 0xc006f556, 0x41d0e4b0, 0xc00698d3,
-  0x41c454f5, 0xc0063ec6, 0x41b7c528, 0xc005e731,
-  0x41ab354b, 0xc0059214, 0x419ea55d, 0xc0053f6e,
-  0x4192155f, 0xc004ef3f, 0x41858552, 0xc004a188,
-  0x4178f536, 0xc0045648, 0x416c650b, 0xc0040d80,
-  0x415fd4d2, 0xc003c72f, 0x4153448c, 0xc0038356,
-  0x4146b438, 0xc00341f4, 0x413a23d8, 0xc003030a,
-  0x412d936c, 0xc002c697, 0x412102f4, 0xc0028c9c,
-  0x41147271, 0xc0025519, 0x4107e1e3, 0xc002200d,
-  0x40fb514b, 0xc001ed78, 0x40eec0aa, 0xc001bd5c,
-  0x40e22fff, 0xc0018fb6, 0x40d59f4c, 0xc0016489,
-  0x40c90e90, 0xc0013bd3, 0x40bc7dcc, 0xc0011594,
-  0x40afed02, 0xc000f1ce, 0x40a35c30, 0xc000d07e,
-  0x4096cb58, 0xc000b1a7, 0x408a3a7b, 0xc0009547,
-  0x407da998, 0xc0007b5f, 0x407118b0, 0xc00063ee,
-  0x406487c4, 0xc0004ef5, 0x4057f6d4, 0xc0003c74,
-  0x404b65e1, 0xc0002c6a, 0x403ed4ea, 0xc0001ed8,
-  0x403243f1, 0xc00013bd, 0x4025b2f7, 0xc0000b1a,
-  0x401921fb, 0xc00004ef, 0x400c90fe, 0xc000013c,
-};
-
-/**    
-* @brief  Initialization function for the Q31 RFFT/RIFFT.   
-* @param[in, out] *S             points to an instance of the Q31 RFFT/RIFFT structure.   
-* @param[in, out] *S_CFFT        points to an instance of the Q31 CFFT/CIFFT structure.   
-* @param[in]      fftLenReal     length of the FFT.   
-* @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.   
-* @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.   
-* @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.   
-*    
-* \par Description:   
-* \par   
-* The parameter fftLenReal	Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048.    
-* \par    
-* The parameter ifftFlagR controls whether a forward or inverse transform is computed.    
-* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.    
-* \par    
-* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.    
-* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
-* \par    
-* This function also initializes Twiddle factor table.    
-*/
-
-arm_status arm_rfft_init_q31(
-  arm_rfft_instance_q31 * S,
-  arm_cfft_radix4_instance_q31 * S_CFFT,
-  uint32_t fftLenReal,
-  uint32_t ifftFlagR,
-  uint32_t bitReverseFlag)
-{
-  /*  Initialise the default arm status */
-  arm_status status = ARM_MATH_SUCCESS;
-
-  /*  Initialize the Real FFT length */
-  S->fftLenReal = (uint16_t) fftLenReal;
-
-  /*  Initialize the Complex FFT length */
-  S->fftLenBy2 = (uint16_t) fftLenReal / 2u;
-
-  /*  Initialize the Twiddle coefficientA pointer */
-  S->pTwiddleAReal = (q31_t *) realCoefAQ31;
-
-  /*  Initialize the Twiddle coefficientB pointer */
-  S->pTwiddleBReal = (q31_t *) realCoefBQ31;
-
-  /*  Initialize the Flag for selection of RFFT or RIFFT */
-  S->ifftFlagR = (uint8_t) ifftFlagR;
-
-  /*  Initialize the Flag for calculation Bit reversal or not */
-  S->bitReverseFlagR = (uint8_t) bitReverseFlag;
-
-  /*  Initialization of coef modifier depending on the FFT length */
-  switch (S->fftLenReal)
-  {
-  case 8192:
-    S->twidCoefRModifier = 1u;
-    break;
-  case 2048u:
-    S->twidCoefRModifier = 4u;
-    break;
-  case 512u:
-    S->twidCoefRModifier = 16u;
-    break;
-  case 128u:
-    S->twidCoefRModifier = 64u;
-    break;
-  default:
-    /*  Reporting argument error if rfftSize is not valid value */
-    status = ARM_MATH_ARGUMENT_ERROR;
-    break;
-  }
-
-  /* Init Complex FFT Instance */
-  S->pCfft = S_CFFT;
-
-  if(S->ifftFlagR)
-  {
-    /* Initializes the CIFFT Module for fftLenreal/2 length */
-    arm_cfft_radix4_init_q31(S->pCfft, (uint16_t) S->fftLenBy2, 1u, 1u);
-  }
-  else
-  {
-    /* Initializes the CFFT Module for fftLenreal/2 length */
-    arm_cfft_radix4_init_q31(S->pCfft, (uint16_t) S->fftLenBy2, 0u, 1u);
-  }
-
-  /* return the status of RFFT Init function */
-  return (status);
-
-}
-
-  /**    
-   * @} end of RFFT_RIFFT group    
-   */
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q15.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q15.c
deleted file mode 100644
index a307ecd215..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q15.c
+++ /dev/null
@@ -1,460 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_rfft_q15.c    
-*    
-* Description:	RFFT & RIFFT Q15 process function    
-*    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* -------------------------------------------------------------------- */
-
-
-#include "arm_math.h"
-
-/*--------------------------------------------------------------------    
-*		Internal functions prototypes    
---------------------------------------------------------------------*/
-
-void arm_split_rfft_q15(
-  q15_t * pSrc,
-  uint32_t fftLen,
-  q15_t * pATable,
-  q15_t * pBTable,
-  q15_t * pDst,
-  uint32_t modifier);
-
-void arm_split_rifft_q15(
-  q15_t * pSrc,
-  uint32_t fftLen,
-  q15_t * pATable,
-  q15_t * pBTable,
-  q15_t * pDst,
-  uint32_t modifier);
-
-/**    
- * @addtogroup RFFT_RIFFT    
- * @{    
- */
-
-/**    
- * @brief Processing function for the Q15 RFFT/RIFFT.   
- * @param[in]  *S    points to an instance of the Q15 RFFT/RIFFT structure.   
- * @param[in]  *pSrc points to the input buffer.   
- * @param[out] *pDst points to the output buffer.   
- * @return none.   
- *    
- * \par Input an output formats:   
- * \par    
- * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.    
- * Hence the output format is different for different RFFT sizes.    
- * The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT:   
- * \par    
- * \image html RFFTQ15.gif "Input and Output Formats for Q15 RFFT"    
- * \par    
- * \image html RIFFTQ15.gif "Input and Output Formats for Q15 RIFFT"    
- */
-
-void arm_rfft_q15(
-  const arm_rfft_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst)
-{
-  const arm_cfft_radix4_instance_q15 *S_CFFT = S->pCfft;
-
-  /* Calculation of RIFFT of input */
-  if(S->ifftFlagR == 1u)
-  {
-    /*  Real IFFT core process */
-    arm_split_rifft_q15(pSrc, S->fftLenBy2, S->pTwiddleAReal,
-                        S->pTwiddleBReal, pDst, S->twidCoefRModifier);
-
-    /* Complex readix-4 IFFT process */
-    arm_radix4_butterfly_inverse_q15(pDst, S_CFFT->fftLen,
-                                     S_CFFT->pTwiddle,
-                                     S_CFFT->twidCoefModifier);
-
-    /* Bit reversal process */
-    if(S->bitReverseFlagR == 1u)
-    {
-      arm_bitreversal_q15(pDst, S_CFFT->fftLen,
-                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
-    }
-  }
-  else
-  {
-    /* Calculation of RFFT of input */
-
-    /* Complex readix-4 FFT process */
-    arm_radix4_butterfly_q15(pSrc, S_CFFT->fftLen,
-                             S_CFFT->pTwiddle, S_CFFT->twidCoefModifier);
-
-    /* Bit reversal process */
-    if(S->bitReverseFlagR == 1u)
-    {
-      arm_bitreversal_q15(pSrc, S_CFFT->fftLen,
-                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
-    }
-
-    arm_split_rfft_q15(pSrc, S->fftLenBy2, S->pTwiddleAReal,
-                       S->pTwiddleBReal, pDst, S->twidCoefRModifier);
-  }
-
-}
-
-  /**    
-   * @} end of RFFT_RIFFT group    
-   */
-
-/**    
- * @brief  Core Real FFT process    
- * @param  *pSrc 				points to the input buffer.   
- * @param  fftLen  				length of FFT.   
- * @param  *pATable 			points to the A twiddle Coef buffer.    
- * @param  *pBTable 			points to the B twiddle Coef buffer.   
- * @param  *pDst 				points to the output buffer.   
- * @param  modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
- * @return none.    
- * The function implements a Real FFT    
- */
-
-void arm_split_rfft_q15(
-  q15_t * pSrc,
-  uint32_t fftLen,
-  q15_t * pATable,
-  q15_t * pBTable,
-  q15_t * pDst,
-  uint32_t modifier)
-{
-  uint32_t i;                                    /* Loop Counter */
-  q31_t outR, outI;                              /* Temporary variables for output */
-  q15_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
-  q15_t *pSrc1, *pSrc2;
-
-
-//  pSrc[2u * fftLen] = pSrc[0]; 
-//  pSrc[(2u * fftLen) + 1u] = pSrc[1]; 
-
-  pCoefA = &pATable[modifier * 2u];
-  pCoefB = &pBTable[modifier * 2u];
-
-  pSrc1 = &pSrc[2];
-  pSrc2 = &pSrc[(2u * fftLen) - 2u];
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  i = 1u;
-
-  while(i < fftLen)
-  {
-    /*    
-       outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]    
-       + pSrc[2 * n - 2 * i] * pBTable[2 * i] +    
-       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
-     */
-
-    /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +    
-       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
-       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
-
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    /* pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1] */
-    outR = __SMUSD(*__SIMD32(pSrc1), *__SIMD32(pCoefA));
-
-#else
-
-    /* -(pSrc[2 * i + 1] * pATable[2 * i + 1] - pSrc[2 * i] * pATable[2 * i]) */
-    outR = -(__SMUSD(*__SIMD32(pSrc1), *__SIMD32(pCoefA)));
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-    /* pSrc[2 * n - 2 * i] * pBTable[2 * i] +    
-       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */
-    outR = __SMLAD(*__SIMD32(pSrc2), *__SIMD32(pCoefB), outR) >> 15u;
-
-    /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
-       pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    outI = __SMUSDX(*__SIMD32(pSrc2)--, *__SIMD32(pCoefB));
-
-#else
-
-    outI = __SMUSDX(*__SIMD32(pCoefB), *__SIMD32(pSrc2)--);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-    /* (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] */
-    outI = __SMLADX(*__SIMD32(pSrc1)++, *__SIMD32(pCoefA), outI);
-
-    /* write output */
-    pDst[2u * i] = (q15_t) outR;
-    pDst[(2u * i) + 1u] = outI >> 15u;
-
-    /* write complex conjugate output */
-    pDst[(4u * fftLen) - (2u * i)] = (q15_t) outR;
-    pDst[((4u * fftLen) - (2u * i)) + 1u] = -(outI >> 15u);
-
-    /* update coefficient pointer */
-    pCoefB = pCoefB + (2u * modifier);
-    pCoefA = pCoefA + (2u * modifier);
-
-    i++;
-
-  }
-
-  pDst[2u * fftLen] = pSrc[0] - pSrc[1];
-  pDst[(2u * fftLen) + 1u] = 0;
-
-  pDst[0] = pSrc[0] + pSrc[1];
-  pDst[1] = 0;
-
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  i = 1u;
-
-  while(i < fftLen)
-  {
-    /*    
-       outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]    
-       + pSrc[2 * n - 2 * i] * pBTable[2 * i] +    
-       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
-     */
-
-    outR = *pSrc1 * *pCoefA;
-    outR = outR - (*(pSrc1 + 1) * *(pCoefA + 1));
-    outR = outR + (*pSrc2 * *pCoefB);
-    outR = (outR + (*(pSrc2 + 1) * *(pCoefB + 1))) >> 15;
-
-
-    /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +    
-       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
-       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);   
-     */
-
-    outI = *pSrc2 * *(pCoefB + 1);
-    outI = outI - (*(pSrc2 + 1) * *pCoefB);
-    outI = outI + (*(pSrc1 + 1) * *pCoefA);
-    outI = outI + (*pSrc1 * *(pCoefA + 1));
-
-    /* update input pointers */
-    pSrc1 += 2u;
-    pSrc2 -= 2u;
-
-    /* write output */
-    pDst[2u * i] = (q15_t) outR;
-    pDst[(2u * i) + 1u] = outI >> 15u;
-
-    /* write complex conjugate output */
-    pDst[(4u * fftLen) - (2u * i)] = (q15_t) outR;
-    pDst[((4u * fftLen) - (2u * i)) + 1u] = -(outI >> 15u);
-
-    /* update coefficient pointer */
-    pCoefB = pCoefB + (2u * modifier);
-    pCoefA = pCoefA + (2u * modifier);
-
-    i++;
-
-  }
-
-  pDst[2u * fftLen] = pSrc[0] - pSrc[1];
-  pDst[(2u * fftLen) + 1u] = 0;
-
-  pDst[0] = pSrc[0] + pSrc[1];
-  pDst[1] = 0;
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-}
-
-
-/**    
- * @brief  Core Real IFFT process    
- * @param[in]   *pSrc 				points to the input buffer.    
- * @param[in]   fftLen  		    length of FFT.   
- * @param[in]   *pATable 			points to the twiddle Coef A buffer.   
- * @param[in]   *pBTable 			points to the twiddle Coef B buffer.    
- * @param[out]  *pDst 				points to the output buffer.   
- * @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
- * @return none.    
- * The function implements a Real IFFT    
- */
-void arm_split_rifft_q15(
-  q15_t * pSrc,
-  uint32_t fftLen,
-  q15_t * pATable,
-  q15_t * pBTable,
-  q15_t * pDst,
-  uint32_t modifier)
-{
-  uint32_t i;                                    /* Loop Counter */
-  q31_t outR, outI;                              /* Temporary variables for output */
-  q15_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
-  q15_t *pSrc1, *pSrc2;
-  q15_t *pDst1 = &pDst[0];
-
-  pCoefA = &pATable[0];
-  pCoefB = &pBTable[0];
-
-  pSrc1 = &pSrc[0];
-  pSrc2 = &pSrc[2u * fftLen];
-
-#ifndef ARM_MATH_CM0
-
-  /* Run the below code for Cortex-M4 and Cortex-M3 */
-
-  i = fftLen;
-
-  while(i > 0u)
-  {
-
-    /*    
-       outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +    
-       pIn[2 * n - 2 * i] * pBTable[2 * i] -    
-       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
-
-       outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -    
-       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
-       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);    
-
-     */
-
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    /* pIn[2 * n - 2 * i] * pBTable[2 * i] -    
-       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */
-    outR = __SMUSD(*__SIMD32(pSrc2), *__SIMD32(pCoefB));
-
-#else
-
-    /* -(-pIn[2 * n - 2 * i] * pBTable[2 * i] +  
-       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1])) */
-    outR = -(__SMUSD(*__SIMD32(pSrc2), *__SIMD32(pCoefB)));
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-    /* pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +    
-       pIn[2 * n - 2 * i] * pBTable[2 * i] */
-    outR = __SMLAD(*__SIMD32(pSrc1), *__SIMD32(pCoefA), outR) >> 15u;
-
-    /*    
-       -pIn[2 * n - 2 * i] * pBTable[2 * i + 1] +    
-       pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
-    outI = __SMUADX(*__SIMD32(pSrc2)--, *__SIMD32(pCoefB));
-
-    /* pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    outI = __SMLSDX(*__SIMD32(pCoefA), *__SIMD32(pSrc1)++, -outI);
-
-#else
-
-    outI = __SMLSDX(*__SIMD32(pSrc1)++, *__SIMD32(pCoefA), -outI);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-    /* write output */
-
-#ifndef ARM_MATH_BIG_ENDIAN
-
-    *__SIMD32(pDst1)++ = __PKHBT(outR, (outI >> 15u), 16);
-
-#else
-
-    *__SIMD32(pDst1)++ = __PKHBT((outI >> 15u), outR, 16);
-
-#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
-
-    /* update coefficient pointer */
-    pCoefB = pCoefB + (2u * modifier);
-    pCoefA = pCoefA + (2u * modifier);
-
-    i--;
-
-  }
-
-
-#else
-
-  /* Run the below code for Cortex-M0 */
-
-  i = fftLen;
-
-  while(i > 0u)
-  {
-
-    /*    
-       outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +    
-       pIn[2 * n - 2 * i] * pBTable[2 * i] -    
-       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
-     */
-
-    outR = *pSrc2 * *pCoefB;
-    outR = outR - (*(pSrc2 + 1) * *(pCoefB + 1));
-    outR = outR + (*pSrc1 * *pCoefA);
-    outR = (outR + (*(pSrc1 + 1) * *(pCoefA + 1))) >> 15;
-
-    /*   
-       outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -   
-       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -   
-       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);   
-     */
-
-    outI = *(pSrc1 + 1) * *pCoefA;
-    outI = outI - (*pSrc1 * *(pCoefA + 1));
-    outI = outI - (*pSrc2 * *(pCoefB + 1));
-    outI = outI - (*(pSrc2 + 1) * *(pCoefB));
-
-    /* update input pointers */
-    pSrc1 += 2u;
-    pSrc2 -= 2u;
-
-    /* write output */
-    *pDst1++ = (q15_t) outR;
-    *pDst1++ = (q15_t) (outI >> 15);
-
-    /* update coefficient pointer */
-    pCoefB = pCoefB + (2u * modifier);
-    pCoefA = pCoefA + (2u * modifier);
-
-    i--;
-
-  }
-
-#endif /* #ifndef ARM_MATH_CM0 */
-
-}
diff --git a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q31.c b/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q31.c
deleted file mode 100644
index c50c2951a5..0000000000
--- a/bsp/efm32/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q31.c
+++ /dev/null
@@ -1,326 +0,0 @@
-/* ----------------------------------------------------------------------    
-* Copyright (C) 2010 ARM Limited. All rights reserved.    
-*    
-* $Date:        15. February 2012  
-* $Revision: 	V1.1.0  
-*    
-* Project: 	    CMSIS DSP Library    
-* Title:	    arm_rfft_q31.c    
-*    
-* Description:	RFFT & RIFFT Q31 process function    
-*    
-*    
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*  
-* Version 1.1.0 2012/02/15 
-*    Updated with more optimizations, bug fixes and minor API changes.  
-*   
-* Version 1.0.10 2011/7/15  
-*    Big Endian support added and Merged M0 and M3/M4 Source code.   
-*    
-* Version 1.0.3 2010/11/29   
-*    Re-organized the CMSIS folders and updated documentation.    
-*     
-* Version 1.0.2 2010/11/11    
-*    Documentation updated.     
-*    
-* Version 1.0.1 2010/10/05     
-*    Production release and review comments incorporated.    
-*    
-* Version 1.0.0 2010/09/20     
-*    Production release and review comments incorporated.    
-*    
-* Version 0.0.7  2010/06/10     
-*    Misra-C changes done    
-* -------------------------------------------------------------------- */
-
-#include "arm_math.h"
-
-/*--------------------------------------------------------------------    
-*		Internal functions prototypes    
---------------------------------------------------------------------*/
-
-void arm_split_rfft_q31(
-  q31_t * pSrc,
-  uint32_t fftLen,
-  q31_t * pATable,
-  q31_t * pBTable,
-  q31_t * pDst,
-  uint32_t modifier);
-
-void arm_split_rifft_q31(
-  q31_t * pSrc,
-  uint32_t fftLen,
-  q31_t * pATable,
-  q31_t * pBTable,
-  q31_t * pDst,
-  uint32_t modifier);
-
-/**    
- * @addtogroup RFFT_RIFFT    
- * @{    
- */
-
-/**    
- * @brief Processing function for the Q31 RFFT/RIFFT.   
- * @param[in]  *S    points to an instance of the Q31 RFFT/RIFFT structure.   
- * @param[in]  *pSrc points to the input buffer.   
- * @param[out] *pDst points to the output buffer.   
- * @return none.   
- *    
- * \par Input an output formats:   
- * \par    
- * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.   
- * Hence the output format is different for different RFFT sizes.    
- * The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT:   
- * \par    
- * \image html RFFTQ31.gif "Input and Output Formats for Q31 RFFT"    
- *    
- * \par    
- * \image html RIFFTQ31.gif "Input and Output Formats for Q31 RIFFT"    
- */
-
-void arm_rfft_q31(
-  const arm_rfft_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst)
-{
-  const arm_cfft_radix4_instance_q31 *S_CFFT = S->pCfft;
-
-  /* Calculation of RIFFT of input */
-  if(S->ifftFlagR == 1u)
-  {
-    /*  Real IFFT core process */
-    arm_split_rifft_q31(pSrc, S->fftLenBy2, S->pTwiddleAReal,
-                        S->pTwiddleBReal, pDst, S->twidCoefRModifier);
-
-    /* Complex readix-4 IFFT process */
-    arm_radix4_butterfly_inverse_q31(pDst, S_CFFT->fftLen,
-                                     S_CFFT->pTwiddle,
-                                     S_CFFT->twidCoefModifier);
-    /* Bit reversal process */
-    if(S->bitReverseFlagR == 1u)
-    {
-      arm_bitreversal_q31(pDst, S_CFFT->fftLen,
-                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
-    }
-  }
-  else
-  {
-    /* Calculation of RFFT of input */
-
-    /* Complex readix-4 FFT process */
-    arm_radix4_butterfly_q31(pSrc, S_CFFT->fftLen,
-                             S_CFFT->pTwiddle, S_CFFT->twidCoefModifier);
-
-    /* Bit reversal process */
-    if(S->bitReverseFlagR == 1u)
-    {
-      arm_bitreversal_q31(pSrc, S_CFFT->fftLen,
-                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
-    }
-
-    /*  Real FFT core process */
-    arm_split_rfft_q31(pSrc, S->fftLenBy2, S->pTwiddleAReal,
-                       S->pTwiddleBReal, pDst, S->twidCoefRModifier);
-  }
-
-}
-
-
-  /**    
-   * @} end of RFFT_RIFFT group    
-   */
-
-/**    
- * @brief  Core Real FFT process    
- * @param[in]   *pSrc 				points to the input buffer.    
- * @param[in]   fftLen  			length of FFT.   
- * @param[in]   *pATable 			points to the twiddle Coef A buffer.    
- * @param[in]   *pBTable 			points to the twiddle Coef B buffer.    
- * @param[out]  *pDst 				points to the output buffer.    
- * @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
- * @return none.    
- */
-
-void arm_split_rfft_q31(
-  q31_t * pSrc,
-  uint32_t fftLen,
-  q31_t * pATable,
-  q31_t * pBTable,
-  q31_t * pDst,
-  uint32_t modifier)
-{
-  uint32_t i;                                    /* Loop Counter */
-  q31_t outR, outI;                              /* Temporary variables for output */
-  q31_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
-  q31_t CoefA1, CoefA2, CoefB1;                  /* Temporary variables for twiddle coefficients */
-  q31_t *pOut1 = &pDst[2], *pOut2 = &pDst[(4u * fftLen) - 1u];
-  q31_t *pIn1 = &pSrc[2], *pIn2 = &pSrc[(2u * fftLen) - 1u];
-
-  /* Init coefficient pointers */
-  pCoefA = &pATable[modifier * 2u];
-  pCoefB = &pBTable[modifier * 2u];
-
-  i = fftLen - 1u;
-
-  while(i > 0u)
-  {
-    /*    
-       outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]    
-       + pSrc[2 * n - 2 * i] * pBTable[2 * i] +    
-       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
-     */
-
-    /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +    
-       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
-       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
-
-    CoefA1 = *pCoefA++;
-    CoefA2 = *pCoefA;
-
-    /* outR = (pSrc[2 * i] * pATable[2 * i] */
-    outR = ((int32_t) (((q63_t) * pIn1 * CoefA1) >> 32));
-
-    /* outI = pIn[2 * i] * pATable[2 * i + 1] */
-    outI = ((int32_t) (((q63_t) * pIn1++ * CoefA2) >> 32));
-
-    /* - pSrc[2 * i + 1] * pATable[2 * i + 1] */
-    outR =
-      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn1 * (-CoefA2))) >> 32);
-
-    /* (pIn[2 * i + 1] * pATable[2 * i] */
-    outI =
-      (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn1++ * (CoefA1))) >> 32);
-
-    /* pSrc[2 * n - 2 * i] * pBTable[2 * i]  */
-    outR =
-      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (-CoefA2))) >> 32);
-    CoefB1 = *pCoefB;
-
-    /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */
-    outI =
-      (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn2-- * (-CoefB1))) >> 32);
-
-    /* pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */
-    outR =
-      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (CoefB1))) >> 32);
-
-    /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
-    outI =
-      (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn2-- * (-CoefA2))) >> 32);
-
-    /* write output */
-    *pOut1++ = (outR << 1u);
-    *pOut1++ = (outI << 1u);
-
-    /* write complex conjugate output */
-    *pOut2-- = -(outI << 1u);
-    *pOut2-- = (outR << 1u);
-
-    /* update coefficient pointer */
-    pCoefB = pCoefB + (modifier * 2u);
-    pCoefA = pCoefA + ((modifier * 2u) - 1u);
-
-    i--;
-
-  }
-
-  pDst[2u * fftLen] = pSrc[0] - pSrc[1];
-  pDst[(2u * fftLen) + 1u] = 0;
-
-  pDst[0] = pSrc[0] + pSrc[1];
-  pDst[1] = 0;
-
-}
-
-
-/**    
- * @brief  Core Real IFFT process    
- * @param[in]   *pSrc 				points to the input buffer.   
- * @param[in]   fftLen  			length of FFT.    
- * @param[in]   *pATable 			points to the twiddle Coef A buffer.   
- * @param[in]   *pBTable 			points to the twiddle Coef B buffer.    
- * @param[out]  *pDst 				points to the output buffer.   
- * @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
- * @return none.    
- */
-
-void arm_split_rifft_q31(
-  q31_t * pSrc,
-  uint32_t fftLen,
-  q31_t * pATable,
-  q31_t * pBTable,
-  q31_t * pDst,
-  uint32_t modifier)
-{
-  q31_t outR, outI;                              /* Temporary variables for output */
-  q31_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
-  q31_t CoefA1, CoefA2, CoefB1;                  /* Temporary variables for twiddle coefficients */
-  q31_t *pIn1 = &pSrc[0], *pIn2 = &pSrc[(2u * fftLen) + 1u];
-
-  pCoefA = &pATable[0];
-  pCoefB = &pBTable[0];
-
-  while(fftLen > 0u)
-  {
-    /*    
-       outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +    
-       pIn[2 * n - 2 * i] * pBTable[2 * i] -    
-       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);    
-
-       outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -    
-       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -    
-       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);    
-
-     */
-    CoefA1 = *pCoefA++;
-    CoefA2 = *pCoefA;
-
-    /* outR = (pIn[2 * i] * pATable[2 * i] */
-    outR = ((int32_t) (((q63_t) * pIn1 * CoefA1) >> 32));
-
-    /* - pIn[2 * i] * pATable[2 * i + 1] */
-    outI = -((int32_t) (((q63_t) * pIn1++ * CoefA2) >> 32));
-
-    /* pIn[2 * i + 1] * pATable[2 * i + 1] */
-    outR =
-      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn1 * (CoefA2))) >> 32);
-
-    /* pIn[2 * i + 1] * pATable[2 * i] */
-    outI =
-      (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn1++ * (CoefA1))) >> 32);
-
-    /* pIn[2 * n - 2 * i] * pBTable[2 * i] */
-    outR =
-      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (CoefA2))) >> 32);
-
-    CoefB1 = *pCoefB;
-
-    /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */
-    outI =
-      (q31_t) ((((q63_t) outI << 32) - ((q63_t) * pIn2-- * (CoefB1))) >> 32);
-
-    /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */
-    outR =
-      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (CoefB1))) >> 32);
-
-    /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
-    outI =
-      (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn2-- * (CoefA2))) >> 32);
-
-    /* write output */
-    *pDst++ = (outR << 1u);
-    *pDst++ = (outI << 1u);
-
-    /* update coefficient pointer */
-    pCoefB = pCoefB + (modifier * 2u);
-    pCoefA = pCoefA + ((modifier * 2u) - 1u);
-
-    /* Decrement loop count */
-    fftLen--;
-
-  }
-
-
-}
diff --git a/bsp/efm32/Libraries/CMSIS/Include/arm_common_tables.h b/bsp/efm32/Libraries/CMSIS/Include/arm_common_tables.h
index 8c35ef2bd5..ee55e5dc79 100644
--- a/bsp/efm32/Libraries/CMSIS/Include/arm_common_tables.h
+++ b/bsp/efm32/Libraries/CMSIS/Include/arm_common_tables.h
@@ -1,24 +1,24 @@
-/* ---------------------------------------------------------------------- 
-* Copyright (C) 2010 ARM Limited. All rights reserved. 
-* 
-* $Date:        11. November 2010  
-* $Revision: 	V1.0.2  
-* 
-* Project: 	    CMSIS DSP Library 
-* Title:	    arm_common_tables.h 
-* 
-* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions 
-* 
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010 ARM Limited. All rights reserved.
+*
+* $Date:        11. November 2010
+* $Revision:    V1.0.2
+*
+* Project:      CMSIS DSP Library
+* Title:        arm_common_tables.h
+*
+* Description:  This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
 * Target Processor: Cortex-M4/Cortex-M3
-*  
-* Version 1.0.2 2010/11/11 
-*    Documentation updated.  
-* 
-* Version 1.0.1 2010/10/05  
-*    Production release and review comments incorporated. 
-* 
-* Version 1.0.0 2010/09/20  
-*    Production release and review comments incorporated. 
+*
+* Version 1.0.2 2010/11/11
+*    Documentation updated.
+*
+* Version 1.0.1 2010/10/05
+*    Production release and review comments incorporated.
+*
+* Version 1.0.0 2010/09/20
+*    Production release and review comments incorporated.
 * -------------------------------------------------------------------- */
 
 #ifndef _ARM_COMMON_TABLES_H
diff --git a/bsp/efm32/Libraries/CMSIS/Include/arm_math.h b/bsp/efm32/Libraries/CMSIS/Include/arm_math.h
index 7266c3efb3..96e0b65a01 100644
--- a/bsp/efm32/Libraries/CMSIS/Include/arm_math.h
+++ b/bsp/efm32/Libraries/CMSIS/Include/arm_math.h
@@ -1,33 +1,33 @@
-/* ----------------------------------------------------------------------   
- * Copyright (C) 2010-2011 ARM Limited. All rights reserved.   
- *   
- * $Date:        15. February 2012  
- * $Revision: 	V1.1.0  
- *   
- * Project: 	    CMSIS DSP Library   
- * Title:	     	arm_math.h
- *   
- * Description:	 Public header file for CMSIS DSP Library
- *   
+/* ----------------------------------------------------------------------
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * $Date:        15. February 2012
+ * $Revision:   V1.1.0
+ *
+ * Project:         CMSIS DSP Library
+ * Title:           arm_math.h
+ *
+ * Description:  Public header file for CMSIS DSP Library
+ *
  * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
- *  
- * Version 1.1.0 2012/02/15 
- *    Updated with more optimizations, bug fixes and minor API changes.  
- *  
- * Version 1.0.10 2011/7/15 
- *    Big Endian support added and Merged M0 and M3/M4 Source code.  
- *   
- * Version 1.0.3 2010/11/29  
- *    Re-organized the CMSIS folders and updated documentation.   
- *    
- * Version 1.0.2 2010/11/11   
- *    Documentation updated.    
- *   
- * Version 1.0.1 2010/10/05    
- *    Production release and review comments incorporated.   
- *   
- * Version 1.0.0 2010/09/20    
- *    Production release and review comments incorporated.   
+ *
+ * Version 1.1.0 2012/02/15
+ *    Updated with more optimizations, bug fixes and minor API changes.
+ *
+ * Version 1.0.10 2011/7/15
+ *    Big Endian support added and Merged M0 and M3/M4 Source code.
+ *
+ * Version 1.0.3 2010/11/29
+ *    Re-organized the CMSIS folders and updated documentation.
+ *
+ * Version 1.0.2 2010/11/11
+ *    Documentation updated.
+ *
+ * Version 1.0.1 2010/10/05
+ *    Production release and review comments incorporated.
+ *
+ * Version 1.0.0 2010/09/20
+ *    Production release and review comments incorporated.
  * -------------------------------------------------------------------- */
 
 /**
@@ -35,10 +35,10 @@
    *
    * Introduction
    *
-   * This user manual describes the CMSIS DSP software library, 
+   * This user manual describes the CMSIS DSP software library,
    * a suite of common signal processing functions for use on Cortex-M processor based devices.
    *
-   * The library is divided into a number of functions each covering a specific category:  
+   * The library is divided into a number of functions each covering a specific category:
    * - Basic math functions
    * - Fast math functions
    * - Complex math functions
@@ -51,40 +51,40 @@
    * - Interpolation functions
    *
    * The library has separate functions for operating on 8-bit integers, 16-bit integers,
-   * 32-bit integer and 32-bit floating-point values. 
+   * 32-bit integer and 32-bit floating-point values.
+   *
+   * Pre-processor Macros
+   *
+   * Each library project have differant pre-processor macros.
+   *
+   * - UNALIGNED_SUPPORT_DISABLE:
+   *
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_MATH_MATRIX_CHECK:
+   *
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
+   * - ARM_MATH_ROUNDING:
    *
-   * Pre-processor Macros 
-   * 
-   * Each library project have differant pre-processor macros. 
-   * 
-   * - UNALIGNED_SUPPORT_DISABLE: 
-   * 
-   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access    
-   * 
-   * - ARM_MATH_BIG_ENDIAN: 
-   * 
-   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. 
-   * 
-   * - ARM_MATH_MATRIX_CHECK: 
-   * 
-   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices 
-   * 
-   * - ARM_MATH_ROUNDING: 
-   * 
    * Define macro ARM_MATH_ROUNDING for rounding on support functions
    *
    * - ARM_MATH_CMx:
    *
    * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
    * and ARM_MATH_CM0 for building library on cortex-M0 target.
-   * 
+   *
    * - __FPU_PRESENT:
    *
-   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries 
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
    *
    * Toolchain Support
    *
-   * The library has been developed and tested with MDK-ARM version 4.23. 
+   * The library has been developed and tested with MDK-ARM version 4.23.
    * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
    *
    * Using the Library
@@ -100,9 +100,9 @@
    * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
    *
    * The library functions are declared in the public file arm_math.h which is placed in the Include folder.
-   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single 
-   * public header file  arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. 
-   * Define the appropriate pre processor MACRO ARM_MATH_CM4 or  ARM_MATH_CM3 or 
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+   * public header file  arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+   * Define the appropriate pre processor MACRO ARM_MATH_CM4 or  ARM_MATH_CM3 or
    * ARM_MATH_CM0 depending on the target processor in the application.
    *
    * Examples
@@ -115,7 +115,7 @@
    * - arm_cortexM0b_math.uvproj
    * - arm_cortexM0l_math.uvproj
    * - arm_cortexM3b_math.uvproj
-   * - arm_cortexM3l_math.uvproj  
+   * - arm_cortexM3l_math.uvproj
    * - arm_cortexM4b_math.uvproj
    * - arm_cortexM4l_math.uvproj
    * - arm_cortexM4bf_math.uvproj
@@ -272,7 +272,7 @@
 #undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
 #include "string.h"
 #include "math.h"
-#ifdef	__cplusplus
+#ifdef  __cplusplus
 extern "C"
 {
 #endif
@@ -282,27 +282,27 @@ extern "C"
    * @brief Macros required for reciprocal calculation in Normalized LMS
    */
 
-#define DELTA_Q31 			(0x100)
-#define DELTA_Q15 			0x5
-#define INDEX_MASK 			0x0000003F
+#define DELTA_Q31           (0x100)
+#define DELTA_Q15           0x5
+#define INDEX_MASK          0x0000003F
 #ifndef PI
-#define PI					3.14159265358979f
+#define PI                  3.14159265358979f
 #endif
 
   /**
    * @brief Macros required for SINE and COSINE Fast math approximations
    */
 
-#define TABLE_SIZE			256
-#define TABLE_SPACING_Q31	0x800000
-#define TABLE_SPACING_Q15	0x80
+#define TABLE_SIZE          256
+#define TABLE_SPACING_Q31   0x800000
+#define TABLE_SPACING_Q15   0x80
 
   /**
    * @brief Macros required for SINE and COSINE Controller functions
    */
   /* 1.31(q31) Fixed value of 2/360 */
   /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
-#define INPUT_SPACING			0xB60B61
+#define INPUT_SPACING           0xB60B61
 
   /**
    * @brief Macro for Unaligned Support
@@ -315,7 +315,7 @@ extern "C"
   #else
     #define ALIGN4 __align(4)
   #endif
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+#endif  /*  #ifndef UNALIGNED_SUPPORT_DISABLE   */
 
   /**
    * @brief Error status returned by some functions in the library.
@@ -371,7 +371,7 @@ extern "C"
 #else
   #define __SIMD32(addr)         (*(__packed                    int32_t **) & (addr))
   #define  _SIMD32_OFFSET(addr)  (*(__packed                    int32_t * )   (addr))
-#endif 
+#endif
 
   #define __SIMD64(addr)  (*(int64_t **) & (addr))
 
@@ -392,16 +392,16 @@ extern "C"
    */
 #ifndef ARM_MATH_BIG_ENDIAN
 
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |	\
-                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) |	\
-							    (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |	\
-							    (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) | \
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
 #else
 
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) |	\
-                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) |	\
-							    (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |	\
-							    (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) | \
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
 
 #endif
 
@@ -1169,11 +1169,11 @@ extern "C"
   /**
    * @brief  Initialization function for the Q31 FIR filter.
    * @param[in,out] *S points to an instance of the Q31 FIR structure.
-   * @param[in] 	numTaps  Number of filter coefficients in the filter.
-   * @param[in] 	*pCoeffs points to the filter coefficients.
-   * @param[in] 	*pState points to the state buffer.
-   * @param[in] 	blockSize number of samples that are processed at a time.
-   * @return 		none.
+   * @param[in]     numTaps  Number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs points to the filter coefficients.
+   * @param[in]     *pState points to the state buffer.
+   * @param[in]     blockSize number of samples that are processed at a time.
+   * @return        none.
    */
   void arm_fir_init_q31(
   arm_fir_instance_q31 * S,
@@ -1199,11 +1199,11 @@ extern "C"
   /**
    * @brief  Initialization function for the floating-point FIR filter.
    * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
-   * @param[in] 	numTaps  Number of filter coefficients in the filter.
-   * @param[in] 	*pCoeffs points to the filter coefficients.
-   * @param[in] 	*pState points to the state buffer.
-   * @param[in] 	blockSize number of samples that are processed at a time.
-   * @return    	none.
+   * @param[in]     numTaps  Number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs points to the filter coefficients.
+   * @param[in]     *pState points to the state buffer.
+   * @param[in]     blockSize number of samples that are processed at a time.
+   * @return        none.
    */
   void arm_fir_init_f32(
   arm_fir_instance_f32 * S,
@@ -1463,7 +1463,7 @@ extern "C"
    * @brief Floating-point matrix transpose.
    * @param[in]  *pSrc points to the input matrix
    * @param[out] *pDst points to the output matrix
-   * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH
+   * @return    The function returns either  ARM_MATH_SIZE_MISMATCH
    * or ARM_MATH_SUCCESS based on the outcome of size checking.
    */
 
@@ -1476,7 +1476,7 @@ extern "C"
    * @brief Q15 matrix transpose.
    * @param[in]  *pSrc points to the input matrix
    * @param[out] *pDst points to the output matrix
-   * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH
+   * @return    The function returns either  ARM_MATH_SIZE_MISMATCH
    * or ARM_MATH_SUCCESS based on the outcome of size checking.
    */
 
@@ -1488,7 +1488,7 @@ extern "C"
    * @brief Q31 matrix transpose.
    * @param[in]  *pSrc points to the input matrix
    * @param[out] *pDst points to the output matrix
-   * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH
+   * @return    The function returns either  ARM_MATH_SIZE_MISMATCH
    * or ARM_MATH_SUCCESS based on the outcome of size checking.
    */
 
@@ -1531,7 +1531,7 @@ extern "C"
    * @param[in]       *pSrcA  points to the first input matrix structure
    * @param[in]       *pSrcB  points to the second input matrix structure
    * @param[out]      *pDst   points to output matrix structure
-   * @param[in]		  *pState points to the array for storing intermediate results  
+   * @param[in]       *pState points to the array for storing intermediate results
    * @return     The function returns either
    * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
    */
@@ -1665,7 +1665,7 @@ extern "C"
    * @param[in,out] *S             points to an instance of the floating-point matrix structure.
    * @param[in]     nRows          number of rows in the matrix.
    * @param[in]     nColumns       number of columns in the matrix.
-   * @param[in]     *pData	       points to the matrix data array.
+   * @param[in]     *pData         points to the matrix data array.
    * @return        none
    */
 
@@ -1680,7 +1680,7 @@ extern "C"
    * @param[in,out] *S             points to an instance of the floating-point matrix structure.
    * @param[in]     nRows          number of rows in the matrix.
    * @param[in]     nColumns       number of columns in the matrix.
-   * @param[in]     *pData	       points to the matrix data array.
+   * @param[in]     *pData         points to the matrix data array.
    * @return        none
    */
 
@@ -1695,7 +1695,7 @@ extern "C"
    * @param[in,out] *S             points to an instance of the floating-point matrix structure.
    * @param[in]     nRows          number of rows in the matrix.
    * @param[in]     nColumns       number of columns in the matrix.
-   * @param[in]     *pData	       points to the matrix data array.
+   * @param[in]     *pData         points to the matrix data array.
    * @return        none
    */
 
@@ -2187,7 +2187,7 @@ extern "C"
 
 
   /*----------------------------------------------------------------------
-   *		Internal functions prototypes FFT function
+   *        Internal functions prototypes FFT function
    ----------------------------------------------------------------------*/
 
   /**
@@ -2256,7 +2256,7 @@ extern "C"
    * @brief  Core function for the f32 FFT butterfly process.
    * @param[in, out] *pSrc            points to the in-place buffer of f32 data type.
    * @param[in]      fftLen           length of the FFT.
-   * @param[in]      *pCoef        	  points to Twiddle coefficient buffer.
+   * @param[in]      *pCoef           points to Twiddle coefficient buffer.
    * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
    * @return none.
    */
@@ -2267,14 +2267,14 @@ extern "C"
   float32_t * pCoef,
   uint16_t twidCoefModifier);
 
-        /**  
-	 * @brief  Core function for the Radix-2 Q31 CFFT butterfly process. 
-	 * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type. 
-	 * @param[in]      fftLen           length of the FFT. 
-	 * @param[in]      *pCoef         	points to Twiddle coefficient buffer.
-	 * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
-	 * @return none. 
-	 */
+        /**
+     * @brief  Core function for the Radix-2 Q31 CFFT butterfly process.
+     * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.
+     * @param[in]      fftLen           length of the FFT.
+     * @param[in]      *pCoef           points to Twiddle coefficient buffer.
+     * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+     * @return none.
+     */
 
   void arm_radix2_butterfly_q31(
   q31_t * pSrc,
@@ -2282,14 +2282,14 @@ extern "C"
   q31_t * pCoef,
   uint16_t twidCoefModifier);
 
-        /**  
-	 * @brief  Core function for the Radix-2 Q15 CFFT butterfly process. 
-	 * @param[in, out] *pSrc            points to the in-place buffer of Q15 data type. 
-	 * @param[in]      fftLen           length of the FFT. 
-	 * @param[in]      *pCoef           points to Twiddle coefficient buffer.
-	 * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
-	 * @return none. 
-	 */
+        /**
+     * @brief  Core function for the Radix-2 Q15 CFFT butterfly process.
+     * @param[in, out] *pSrc            points to the in-place buffer of Q15 data type.
+     * @param[in]      fftLen           length of the FFT.
+     * @param[in]      *pCoef           points to Twiddle coefficient buffer.
+     * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+     * @return none.
+     */
 
   void arm_radix2_butterfly_q15(
   q15_t * pSrc,
@@ -2297,14 +2297,14 @@ extern "C"
   q15_t * pCoef,
   uint16_t twidCoefModifier);
 
-        /**  
-	 * @brief  Core function for the Radix-2 Q15 CFFT Inverse butterfly process. 
-	 * @param[in, out] *pSrc            points to the in-place buffer of Q15 data type. 
-	 * @param[in]      fftLen           length of the FFT. 
-	 * @param[in]      *pCoef       	points to Twiddle coefficient buffer.
-	 * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
-	 * @return none. 
-	 */
+        /**
+     * @brief  Core function for the Radix-2 Q15 CFFT Inverse butterfly process.
+     * @param[in, out] *pSrc            points to the in-place buffer of Q15 data type.
+     * @param[in]      fftLen           length of the FFT.
+     * @param[in]      *pCoef           points to Twiddle coefficient buffer.
+     * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+     * @return none.
+     */
 
   void arm_radix2_butterfly_inverse_q15(
   q15_t * pSrc,
@@ -2312,14 +2312,14 @@ extern "C"
   q15_t * pCoef,
   uint16_t twidCoefModifier);
 
-        /**  
-	 * @brief  Core function for the Radix-2 Q31 CFFT Inverse butterfly process. 
-	 * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type. 
-	 * @param[in]      fftLen           length of the FFT. 
-	 * @param[in]      *pCoef         	points to Twiddle coefficient buffer.
-	 * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. 
-	 * @return none. 
-	 */
+        /**
+     * @brief  Core function for the Radix-2 Q31 CFFT Inverse butterfly process.
+     * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.
+     * @param[in]      fftLen           length of the FFT.
+     * @param[in]      *pCoef           points to Twiddle coefficient buffer.
+     * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+     * @return none.
+     */
 
   void arm_radix2_butterfly_inverse_q31(
   q31_t * pSrc,
@@ -2331,9 +2331,9 @@ extern "C"
    * @brief  Core function for the f32 IFFT butterfly process.
    * @param[in, out] *pSrc            points to the in-place buffer of f32 data type.
    * @param[in]      fftLen           length of the FFT.
-   * @param[in]      *pCoef        	  points to Twiddle coefficient buffer.
+   * @param[in]      *pCoef           points to Twiddle coefficient buffer.
    * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
-   * @param[in]		 onebyfftLen	  1/fftLenfth
+   * @param[in]      onebyfftLen      1/fftLenfth
    * @return none.
    */
 
@@ -2489,7 +2489,7 @@ extern "C"
    * @param[in]      fftLenReal     length of the FFT.
    * @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
    * @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-   * @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
    */
 
   arm_status arm_rfft_init_q15(
@@ -2519,7 +2519,7 @@ extern "C"
    * @param[in]      fftLenReal     length of the FFT.
    * @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
    * @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-   * @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
    */
 
   arm_status arm_rfft_init_q31(
@@ -2536,7 +2536,7 @@ extern "C"
    * @param[in]     fftLenReal     length of the FFT.
    * @param[in]     ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
    * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-   * @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
    */
 
   arm_status arm_rfft_init_f32(
@@ -2582,7 +2582,7 @@ extern "C"
    * @param[in]     N          length of the DCT4.
    * @param[in]     Nby2       half of the length of the DCT4.
    * @param[in]     normalize  normalizing factor.
-   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.
+   * @return        arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.
    */
 
   arm_status arm_dct4_init_f32(
@@ -2629,7 +2629,7 @@ extern "C"
    * @param[in]     N          length of the DCT4.
    * @param[in]     Nby2       half of the length of the DCT4.
    * @param[in]     normalize  normalizing factor.
-   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+   * @return        arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
    */
 
   arm_status arm_dct4_init_q31(
@@ -2676,7 +2676,7 @@ extern "C"
    * @param[in]     N          length of the DCT4.
    * @param[in]     Nby2       half of the length of the DCT4.
    * @param[in]     normalize  normalizing factor.
-   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+   * @return        arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
    */
 
   arm_status arm_dct4_init_q15(
@@ -3155,7 +3155,7 @@ extern "C"
   q31_t * pDst,
   uint32_t blockSize);
   /**
-   * @brief  Copies the elements of a floating-point vector. 
+   * @brief  Copies the elements of a floating-point vector.
    * @param[in]  *pSrc input pointer
    * @param[out]  *pDst output pointer
    * @param[in]  blockSize number of samples to process
@@ -3167,7 +3167,7 @@ extern "C"
   uint32_t blockSize);
 
   /**
-   * @brief  Copies the elements of a Q7 vector. 
+   * @brief  Copies the elements of a Q7 vector.
    * @param[in]  *pSrc input pointer
    * @param[out]  *pDst output pointer
    * @param[in]  blockSize number of samples to process
@@ -3179,7 +3179,7 @@ extern "C"
   uint32_t blockSize);
 
   /**
-   * @brief  Copies the elements of a Q15 vector. 
+   * @brief  Copies the elements of a Q15 vector.
    * @param[in]  *pSrc input pointer
    * @param[out]  *pDst output pointer
    * @param[in]  blockSize number of samples to process
@@ -3191,7 +3191,7 @@ extern "C"
   uint32_t blockSize);
 
   /**
-   * @brief  Copies the elements of a Q31 vector. 
+   * @brief  Copies the elements of a Q31 vector.
    * @param[in]  *pSrc input pointer
    * @param[out]  *pDst output pointer
    * @param[in]  blockSize number of samples to process
@@ -3202,7 +3202,7 @@ extern "C"
   q31_t * pDst,
   uint32_t blockSize);
   /**
-   * @brief  Fills a constant value into a floating-point vector. 
+   * @brief  Fills a constant value into a floating-point vector.
    * @param[in]  value input value to be filled
    * @param[out]  *pDst output pointer
    * @param[in]  blockSize number of samples to process
@@ -3214,7 +3214,7 @@ extern "C"
   uint32_t blockSize);
 
   /**
-   * @brief  Fills a constant value into a Q7 vector. 
+   * @brief  Fills a constant value into a Q7 vector.
    * @param[in]  value input value to be filled
    * @param[out]  *pDst output pointer
    * @param[in]  blockSize number of samples to process
@@ -3226,7 +3226,7 @@ extern "C"
   uint32_t blockSize);
 
   /**
-   * @brief  Fills a constant value into a Q15 vector. 
+   * @brief  Fills a constant value into a Q15 vector.
    * @param[in]  value input value to be filled
    * @param[out]  *pDst output pointer
    * @param[in]  blockSize number of samples to process
@@ -3238,7 +3238,7 @@ extern "C"
   uint32_t blockSize);
 
   /**
-   * @brief  Fills a constant value into a Q31 vector. 
+   * @brief  Fills a constant value into a Q31 vector.
    * @param[in]  value input value to be filled
    * @param[out]  *pDst output pointer
    * @param[in]  blockSize number of samples to process
@@ -3249,14 +3249,14 @@ extern "C"
   q31_t * pDst,
   uint32_t blockSize);
 
-/**  
- * @brief Convolution of floating-point sequences.  
- * @param[in] *pSrcA points to the first input sequence.  
- * @param[in] srcALen length of the first input sequence.  
- * @param[in] *pSrcB points to the second input sequence.  
- * @param[in] srcBLen length of the second input sequence.  
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.  
- * @return none.  
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
  */
 
   void arm_conv_f32(
@@ -3266,17 +3266,17 @@ extern "C"
   uint32_t srcBLen,
   float32_t * pDst);
 
-  
-  /**   
-   * @brief Convolution of Q15 sequences.   
-   * @param[in] *pSrcA points to the first input sequence.   
-   * @param[in] srcALen length of the first input sequence.   
-   * @param[in] *pSrcB points to the second input sequence.   
-   * @param[in] srcBLen length of the second input sequence.   
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.   
-   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
-   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).   
-   * @return none.   
+
+  /**
+   * @brief Convolution of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
    */
 
 
@@ -3290,14 +3290,14 @@ extern "C"
   q15_t * pScratch2);
 
 
-/**  
- * @brief Convolution of Q15 sequences.  
- * @param[in] *pSrcA points to the first input sequence.  
- * @param[in] srcALen length of the first input sequence.  
- * @param[in] *pSrcB points to the second input sequence.  
- * @param[in] srcBLen length of the second input sequence.  
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.  
- * @return none.  
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
  */
 
   void arm_conv_q15(
@@ -3318,11 +3318,11 @@ extern "C"
    */
 
   void arm_conv_fast_q15(
-			  q15_t * pSrcA,
-			 uint32_t srcALen,
-			  q15_t * pSrcB,
-			 uint32_t srcBLen,
-			 q15_t * pDst);
+              q15_t * pSrcA,
+             uint32_t srcALen,
+              q15_t * pSrcB,
+             uint32_t srcBLen,
+             q15_t * pDst);
 
   /**
    * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
@@ -3331,9 +3331,9 @@ extern "C"
    * @param[in] *pSrcB points to the second input sequence.
    * @param[in] srcBLen length of the second input sequence.
    * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
-   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).   
-   * @return none.   
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
    */
 
   void arm_conv_fast_opt_q15(
@@ -3382,16 +3382,16 @@ extern "C"
   q31_t * pDst);
 
 
-    /**   
-   * @brief Convolution of Q7 sequences.   
-   * @param[in] *pSrcA points to the first input sequence.   
-   * @param[in] srcALen length of the first input sequence.   
-   * @param[in] *pSrcB points to the second input sequence.   
-   * @param[in] srcBLen length of the second input sequence.   
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.   
-   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
-   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).   
-   * @return none.   
+    /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
    */
 
   void arm_conv_opt_q7(
@@ -3444,18 +3444,18 @@ extern "C"
   uint32_t firstIndex,
   uint32_t numPoints);
 
-    /**   
-   * @brief Partial convolution of Q15 sequences.   
-   * @param[in]       *pSrcA points to the first input sequence.   
-   * @param[in]       srcALen length of the first input sequence.   
-   * @param[in]       *pSrcB points to the second input sequence.   
-   * @param[in]       srcBLen length of the second input sequence.   
-   * @param[out]      *pDst points to the block of output data   
-   * @param[in]       firstIndex is the first output sample to start with.   
-   * @param[in]       numPoints is the number of output points to be computed.   
-   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
-   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).   
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+    /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
    */
 
   arm_status arm_conv_partial_opt_q15(
@@ -3504,13 +3504,13 @@ extern "C"
    */
 
   arm_status arm_conv_partial_fast_q15(
-				        q15_t * pSrcA,
-				       uint32_t srcALen,
-				        q15_t * pSrcB,
-				       uint32_t srcBLen,
-				       q15_t * pDst,
-				       uint32_t firstIndex,
-				       uint32_t numPoints);
+                        q15_t * pSrcA,
+                       uint32_t srcALen,
+                        q15_t * pSrcB,
+                       uint32_t srcBLen,
+                       q15_t * pDst,
+                       uint32_t firstIndex,
+                       uint32_t numPoints);
 
 
   /**
@@ -3522,9 +3522,9 @@ extern "C"
    * @param[out]      *pDst points to the block of output data
    * @param[in]       firstIndex is the first output sample to start with.
    * @param[in]       numPoints is the number of output points to be computed.
-   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
-   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).   
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
    */
 
   arm_status arm_conv_partial_fast_opt_q15(
@@ -3583,18 +3583,18 @@ extern "C"
   uint32_t numPoints);
 
 
-  /**   
-   * @brief Partial convolution of Q7 sequences   
-   * @param[in]       *pSrcA points to the first input sequence.   
-   * @param[in]       srcALen length of the first input sequence.   
-   * @param[in]       *pSrcB points to the second input sequence.   
-   * @param[in]       srcBLen length of the second input sequence.   
-   * @param[out]      *pDst points to the block of output data   
-   * @param[in]       firstIndex is the first output sample to start with.   
-   * @param[in]       numPoints is the number of output points to be computed.   
-   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
-   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).   
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+  /**
+   * @brief Partial convolution of Q7 sequences
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
    */
 
   arm_status arm_conv_partial_opt_q7(
@@ -4086,8 +4086,8 @@ extern "C"
    * @brief Initialization function for the Q15 FIR lattice filter.
    * @param[in] *S points to an instance of the Q15 FIR lattice structure.
    * @param[in] numStages  number of filter stages.
-   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages. 
-   * @param[in] *pState points to the state buffer.  The array is of length numStages. 
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages.
    * @return none.
    */
 
@@ -4654,15 +4654,15 @@ extern "C"
   float32_t * pDst);
 
 
-   /**   
-   * @brief Correlation of Q15 sequences   
-   * @param[in] *pSrcA points to the first input sequence.   
-   * @param[in] srcALen length of the first input sequence.   
-   * @param[in] *pSrcB points to the second input sequence.   
-   * @param[in] srcBLen length of the second input sequence.   
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.   
-   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
-   * @return none.   
+   /**
+   * @brief Correlation of Q15 sequences
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
    */
   void arm_correlate_opt_q15(
   q15_t * pSrcA,
@@ -4701,11 +4701,11 @@ extern "C"
    */
 
   void arm_correlate_fast_q15(
-			       q15_t * pSrcA,
-			      uint32_t srcALen,
-			       q15_t * pSrcB,
-			      uint32_t srcBLen,
-			      q15_t * pDst);
+                   q15_t * pSrcA,
+                  uint32_t srcALen,
+                   q15_t * pSrcB,
+                  uint32_t srcBLen,
+                  q15_t * pDst);
 
 
 
@@ -4716,7 +4716,7 @@ extern "C"
    * @param[in] *pSrcB points to the second input sequence.
    * @param[in] srcBLen length of the second input sequence.
    * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
    * @return none.
    */
 
@@ -4764,16 +4764,16 @@ extern "C"
 
 
 
- /**   
-   * @brief Correlation of Q7 sequences.   
-   * @param[in] *pSrcA points to the first input sequence.   
-   * @param[in] srcALen length of the first input sequence.   
-   * @param[in] *pSrcB points to the second input sequence.   
-   * @param[in] srcBLen length of the second input sequence.   
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.   
-   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.   
-   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).   
-   * @return none.   
+ /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
    */
 
   void arm_correlate_opt_q7(
@@ -5019,9 +5019,9 @@ extern "C"
 
   /*
    * @brief  Floating-point sin_cos function.
-   * @param[in]  theta    input value in degrees 
-   * @param[out] *pSinVal points to the processed sine output. 
-   * @param[out] *pCosVal points to the processed cos output. 
+   * @param[in]  theta    input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cos output.
    * @return none.
    */
 
@@ -5032,9 +5032,9 @@ extern "C"
 
   /*
    * @brief  Q31 sin_cos function.
-   * @param[in]  theta    scaled input value in degrees 
-   * @param[out] *pSinVal points to the processed sine output. 
-   * @param[out] *pCosVal points to the processed cosine output. 
+   * @param[in]  theta    scaled input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cosine output.
    * @return none.
    */
 
@@ -5132,7 +5132,7 @@ extern "C"
   /**
    * @defgroup PID PID Motor Control
    *
-   * A Proportional Integral Derivative (PID) controller is a generic feedback control 
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control
    * loop mechanism widely used in industrial control systems.
    * A PID controller is the most commonly used type of feedback controller.
    *
@@ -5151,39 +5151,39 @@ extern "C"
    *
    * \par
    * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
-   * 
-   * \par 
-   * \image html PID.gif "Proportional Integral Derivative Controller" 
+   *
+   * \par
+   * \image html PID.gif "Proportional Integral Derivative Controller"
    *
    * \par
    * The PID controller calculates an "error" value as the difference between
    * the measured output and the reference input.
-   * The controller attempts to minimize the error by adjusting the process control inputs.  
-   * The proportional value determines the reaction to the current error, 
-   * the integral value determines the reaction based on the sum of recent errors, 
+   * The controller attempts to minimize the error by adjusting the process control inputs.
+   * The proportional value determines the reaction to the current error,
+   * the integral value determines the reaction based on the sum of recent errors,
    * and the derivative value determines the reaction based on the rate at which the error has been changing.
    *
-   * \par Instance Structure 
-   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. 
-   * A separate instance structure must be defined for each PID Controller. 
-   * There are separate instance structure declarations for each of the 3 supported data types. 
-   * 
-   * \par Reset Functions 
-   * There is also an associated reset function for each data type which clears the state array. 
+   * \par Instance Structure
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+   * A separate instance structure must be defined for each PID Controller.
+   * There are separate instance structure declarations for each of the 3 supported data types.
    *
-   * \par Initialization Functions 
-   * There is also an associated initialization function for each data type. 
-   * The initialization function performs the following operations: 
+   * \par Reset Functions
+   * There is also an associated reset function for each data type which clears the state array.
+   *
+   * \par Initialization Functions
+   * There is also an associated initialization function for each data type.
+   * The initialization function performs the following operations:
    * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
-   * - Zeros out the values in the state buffer.   
-   * 
-   * \par 
-   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. 
+   * - Zeros out the values in the state buffer.
    *
-   * \par Fixed-Point Behavior 
-   * Care must be taken when using the fixed-point versions of the PID Controller functions. 
-   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. 
-   * Refer to the function specific documentation below for usage guidelines. 
+   * \par
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+   *
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the fixed-point versions of the PID Controller functions.
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
    */
 
   /**
@@ -5225,13 +5225,13 @@ extern "C"
    * @param[in] in input sample to process
    * @return out processed output sample.
    *
-   * Scaling and Overflow Behavior: 
-   * \par 
-   * The function is implemented using an internal 64-bit accumulator. 
-   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. 
-   * Thus, if the accumulator result overflows it wraps around rather than clip. 
-   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. 
-   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. 
+   * Scaling and Overflow Behavior:
+   * \par
+   * The function is implemented using an internal 64-bit accumulator.
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+   * Thus, if the accumulator result overflows it wraps around rather than clip.
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
    */
 
   __STATIC_INLINE q31_t arm_pid_q31(
@@ -5272,13 +5272,13 @@ extern "C"
    * @param[in] in input sample to process
    * @return out processed output sample.
    *
-   * Scaling and Overflow Behavior: 
-   * \par 
-   * The function is implemented using a 64-bit internal accumulator. 
-   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. 
-   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. 
-   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. 
-   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. 
+   * Scaling and Overflow Behavior:
+   * \par
+   * The function is implemented using a 64-bit internal accumulator.
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
    * Lastly, the accumulator is saturated to yield a result in 1.15 format.
    */
 
@@ -5366,7 +5366,7 @@ extern "C"
    * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta
    * can be calculated using only Ia and Ib.
    *
-   * The function operates on a single sample of data and each call to the function returns the processed output. 
+   * The function operates on a single sample of data and each call to the function returns the processed output.
    * The library provides separate functions for Q31 and floating-point data types.
    * \par Algorithm
    * \image html clarkeFormula.gif
@@ -5470,8 +5470,8 @@ extern "C"
   /**
    * @defgroup inv_clarke Vector Inverse Clarke Transform
    * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
-   * 
-   * The function operates on a single sample of data and each call to the function returns the processed output. 
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
    * The library provides separate functions for Q31 and floating-point data types.
    * \par Algorithm
    * \image html clarkeInvFormula.gif
@@ -5513,7 +5513,7 @@ extern "C"
   }
 
   /**
-   * @brief  Inverse Clarke transform for Q31 version 
+   * @brief  Inverse Clarke transform for Q31 version
    * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
    * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
    * @param[out]      *pIa    points to output three-phase coordinate a
@@ -5575,19 +5575,19 @@ extern "C"
    * @defgroup park Vector Park Transform
    *
    * Forward Park transform converts the input two-coordinate vector to flux and torque components.
-   * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents 
-   * from the stationary to the moving reference frame and control the spatial relationship between 
+   * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents
+   * from the stationary to the moving reference frame and control the spatial relationship between
    * the stator vector current and rotor flux vector.
-   * If we consider the d axis aligned with the rotor flux, the diagram below shows the 
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
    * current vector and the relationship from the two reference frames:
    * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
    *
-   * The function operates on a single sample of data and each call to the function returns the processed output. 
+   * The function operates on a single sample of data and each call to the function returns the processed output.
    * The library provides separate functions for Q31 and floating-point data types.
    * \par Algorithm
    * \image html parkFormula.gif
-   * where Ialpha and Ibeta are the stator vector components,  
-   * pId and pIq are rotor vector components and cosVal and sinVal are the 
+   * where Ialpha and Ibeta are the stator vector components,
+   * pId and pIq are rotor vector components and cosVal and sinVal are the
    * cosine and sine values of theta (rotor flux position).
    * \par Fixed-Point Behavior
    * Care must be taken when using the Q31 version of the Park transform.
@@ -5604,8 +5604,8 @@ extern "C"
    * @brief Floating-point Park transform
    * @param[in]       Ialpha input two-phase vector coordinate alpha
    * @param[in]       Ibeta  input two-phase vector coordinate beta
-   * @param[out]      *pId   points to output	rotor reference frame d
-   * @param[out]      *pIq   points to output	rotor reference frame q
+   * @param[out]      *pId   points to output   rotor reference frame d
+   * @param[out]      *pIq   points to output   rotor reference frame q
    * @param[in]       sinVal sine value of rotation angle theta
    * @param[in]       cosVal cosine value of rotation angle theta
    * @return none.
@@ -5631,7 +5631,7 @@ extern "C"
   }
 
   /**
-   * @brief  Park transform for Q31 version 
+   * @brief  Park transform for Q31 version
    * @param[in]       Ialpha input two-phase vector coordinate alpha
    * @param[in]       Ibeta  input two-phase vector coordinate beta
    * @param[out]      *pId   points to output rotor reference frame d
@@ -5704,12 +5704,12 @@ extern "C"
    * @defgroup inv_park Vector Inverse Park transform
    * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
    *
-   * The function operates on a single sample of data and each call to the function returns the processed output. 
+   * The function operates on a single sample of data and each call to the function returns the processed output.
    * The library provides separate functions for Q31 and floating-point data types.
    * \par Algorithm
    * \image html parkInvFormula.gif
-   * where pIalpha and pIbeta are the stator vector components,  
-   * Id and Iq are rotor vector components and cosVal and sinVal are the 
+   * where pIalpha and pIbeta are the stator vector components,
+   * Id and Iq are rotor vector components and cosVal and sinVal are the
    * cosine and sine values of theta (rotor flux position).
    * \par Fixed-Point Behavior
    * Care must be taken when using the Q31 version of the Park transform.
@@ -5751,7 +5751,7 @@ extern "C"
 
 
   /**
-   * @brief  Inverse Park transform for	Q31 version 
+   * @brief  Inverse Park transform for Q31 version
    * @param[in]       Id        input coordinate of rotor reference frame d
    * @param[in]       Iq        input coordinate of rotor reference frame q
    * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
@@ -5827,7 +5827,7 @@ extern "C"
    * Linear interpolation is a method of curve fitting using linear polynomials.
    * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
    *
-   * \par 
+   * \par
    * \image html LinearInterp.gif "Linear interpolation"
    *
    * \par
@@ -5847,10 +5847,10 @@ extern "C"
    * sample of data and each call to the function returns a single processed value.
    * S points to an instance of the Linear Interpolate function data structure.
    * x is the input sample value. The functions returns the output value.
-   * 
+   *
    * \par
-   * if x is outside of the table boundary, Linear interpolation returns first value of the table 
-   * if x is below input range and returns last value of table if x is above range.  
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table
+   * if x is below input range and returns last value of table if x is above range.
    */
 
   /**
@@ -5982,7 +5982,7 @@ extern "C"
    *
    * \par
    * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12. 
+   * This function can support maximum of table size 2^12.
    *
    */
 
@@ -6162,7 +6162,7 @@ extern "C"
    * @defgroup SQRT Square Root
    *
    * Computes the square root of a number.
-   * There are separate functions for Q15, Q31, and floating-point data types.  
+   * There are separate functions for Q15, Q31, and floating-point data types.
    * The square root function is computed using the Newton-Raphson algorithm.
    * This is an iterative algorithm of the form:
    * 
@@ -7072,11 +7072,11 @@ extern "C"
   uint32_t numSamples);
 
   /**
-   * @brief Converts the elements of the floating-point vector to Q31 vector. 
-   * @param[in]       *pSrc points to the floating-point input vector 
+   * @brief Converts the elements of the floating-point vector to Q31 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
    * @param[out]      *pDst points to the Q31 output vector
-   * @param[in]       blockSize length of the input vector 
-   * @return none. 
+   * @param[in]       blockSize length of the input vector
+   * @return none.
    */
   void arm_float_to_q31(
   float32_t * pSrc,
@@ -7084,10 +7084,10 @@ extern "C"
   uint32_t blockSize);
 
   /**
-   * @brief Converts the elements of the floating-point vector to Q15 vector. 
-   * @param[in]       *pSrc points to the floating-point input vector 
+   * @brief Converts the elements of the floating-point vector to Q15 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
    * @param[out]      *pDst points to the Q15 output vector
-   * @param[in]       blockSize length of the input vector 
+   * @param[in]       blockSize length of the input vector
    * @return          none
    */
   void arm_float_to_q15(
@@ -7096,10 +7096,10 @@ extern "C"
   uint32_t blockSize);
 
   /**
-   * @brief Converts the elements of the floating-point vector to Q7 vector. 
-   * @param[in]       *pSrc points to the floating-point input vector 
+   * @brief Converts the elements of the floating-point vector to Q7 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
    * @param[out]      *pDst points to the Q7 output vector
-   * @param[in]       blockSize length of the input vector 
+   * @param[in]       blockSize length of the input vector
    * @return          none
    */
   void arm_float_to_q7(
@@ -7219,12 +7219,12 @@ extern "C"
    *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
    *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
    * 

-   * Note that the coordinates (x, y) contain integer and fractional components.  
+   * Note that the coordinates (x, y) contain integer and fractional components.
    * The integer components specify which portion of the table to use while the
    * fractional components control the interpolation processor.
    *
    * \par
-   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. 
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
    */
 
   /**
@@ -7543,7 +7543,7 @@ extern "C"
 
 
 
-#ifdef	__cplusplus
+#ifdef  __cplusplus
 }
 #endif
 
diff --git a/bsp/efm32/Libraries/CMSIS/Include/core_cm3.h b/bsp/efm32/Libraries/CMSIS/Include/core_cm3.h
index 0173893fbd..350d452093 100644
--- a/bsp/efm32/Libraries/CMSIS/Include/core_cm3.h
+++ b/bsp/efm32/Libraries/CMSIS/Include/core_cm3.h
@@ -636,14 +636,14 @@ typedef struct
   __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
        uint32_t RESERVED2[15];
   __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
-       uint32_t RESERVED3[29];                                  
+       uint32_t RESERVED3[29];
   __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
   __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
   __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
-       uint32_t RESERVED4[43];                                  
+       uint32_t RESERVED4[43];
   __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
   __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
-       uint32_t RESERVED5[6];                                   
+       uint32_t RESERVED5[6];
   __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
   __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
   __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
diff --git a/bsp/efm32/Libraries/CMSIS/Include/core_cm4.h b/bsp/efm32/Libraries/CMSIS/Include/core_cm4.h
index a965537402..2a67fa2a41 100644
--- a/bsp/efm32/Libraries/CMSIS/Include/core_cm4.h
+++ b/bsp/efm32/Libraries/CMSIS/Include/core_cm4.h
@@ -669,14 +669,14 @@ typedef struct
   __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
        uint32_t RESERVED2[15];
   __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
-       uint32_t RESERVED3[29];                                  
+       uint32_t RESERVED3[29];
   __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
   __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
   __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
-       uint32_t RESERVED4[43];                                  
+       uint32_t RESERVED4[43];
   __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
   __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
-       uint32_t RESERVED5[6];                                   
+       uint32_t RESERVED5[6];
   __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
   __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
   __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
diff --git a/bsp/efm32/Libraries/CMSIS/Include/core_sc300.h b/bsp/efm32/Libraries/CMSIS/Include/core_sc300.h
index 7e56b0f332..4176fe8d5d 100644
--- a/bsp/efm32/Libraries/CMSIS/Include/core_sc300.h
+++ b/bsp/efm32/Libraries/CMSIS/Include/core_sc300.h
@@ -607,14 +607,14 @@ typedef struct
   __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
        uint32_t RESERVED2[15];
   __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
-       uint32_t RESERVED3[29];                                  
+       uint32_t RESERVED3[29];
   __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
   __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
   __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
-       uint32_t RESERVED4[43];                                  
+       uint32_t RESERVED4[43];
   __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
   __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
-       uint32_t RESERVED5[6];                                   
+       uint32_t RESERVED5[6];
   __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
   __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
   __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
diff --git a/bsp/efm32/Libraries/CMSIS/Lib/GCC/libarm_cortexM0l_math.a b/bsp/efm32/Libraries/CMSIS/Lib/GCC/libarm_cortexM0l_math.a
deleted file mode 100644
index 30c034f577..0000000000
Binary files a/bsp/efm32/Libraries/CMSIS/Lib/GCC/libarm_cortexM0l_math.a and /dev/null differ
diff --git a/bsp/efm32/Libraries/CMSIS/Lib/GCC/libarm_cortexM3l_math.a b/bsp/efm32/Libraries/CMSIS/Lib/GCC/libarm_cortexM3l_math.a
deleted file mode 100644
index b90e307b54..0000000000
Binary files a/bsp/efm32/Libraries/CMSIS/Lib/GCC/libarm_cortexM3l_math.a and /dev/null differ
diff --git a/bsp/efm32/Libraries/CMSIS/Lib/GCC/libarm_cortexM4l_math.a b/bsp/efm32/Libraries/CMSIS/Lib/GCC/libarm_cortexM4l_math.a
deleted file mode 100644
index 8135948545..0000000000
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diff --git a/bsp/efm32/Libraries/CMSIS/Lib/GCC/libarm_cortexM4lf_math.a b/bsp/efm32/Libraries/CMSIS/Lib/GCC/libarm_cortexM4lf_math.a
deleted file mode 100644
index 2b48514757..0000000000
Binary files a/bsp/efm32/Libraries/CMSIS/Lib/GCC/libarm_cortexM4lf_math.a and /dev/null differ
diff --git a/bsp/efm32/Libraries/CMSIS/RTOS/cmsis_os.h b/bsp/efm32/Libraries/CMSIS/RTOS/cmsis_os.h
index 2ccfd17504..db29415c55 100644
--- a/bsp/efm32/Libraries/CMSIS/RTOS/cmsis_os.h
+++ b/bsp/efm32/Libraries/CMSIS/RTOS/cmsis_os.h
@@ -1,20 +1,20 @@
-/* ----------------------------------------------------------------------  
- * Copyright (C) 2012 ARM Limited. All rights reserved.  
- *  
+/* ----------------------------------------------------------------------
+ * Copyright (C) 2012 ARM Limited. All rights reserved.
+ *
  * $Date:        5. March 2012
  * $Revision:    V0.03
- *  
+ *
  * Project:      CMSIS-RTOS API
  * Title:        cmsis_os.h template header file
- *  
+ *
  * Version 0.02
- *    Initial Proposal Phase 
+ *    Initial Proposal Phase
  * Version 0.03
  *    osKernelStart added, optional feature: main started as thread
  *    osSemaphores have standard behaviour
  *    osTimerCreate does not start the timer, added osTimerStart
- *    osThreadPass is renamed to osThreadYield 
- * -------------------------------------------------------------------- */ 
+ *    osThreadPass is renamed to osThreadYield
+ * -------------------------------------------------------------------- */
 
 /**
 \page cmsis_os_h Header File Template: cmsis_os.h
@@ -35,8 +35,8 @@ The file cmsis_os.h contains:
 All definitions are prefixed with \b os to give an unique name space for CMSIS-RTOS functions.
 Definitions that are prefixed \b os_ are not used in the application code but local to this header file.
 All definitions and functions that belong to a module are grouped and have a common prefix, i.e. \b osThread.
- 
-Definitions that are marked with CAN BE CHANGED can be adapted towards the needs of the actual CMSIS-RTOS implementation. 
+
+Definitions that are marked with CAN BE CHANGED can be adapted towards the needs of the actual CMSIS-RTOS implementation.
 These definitions can be specific to the underlying RTOS kernel.
 
 Definitions that are marked with MUST REMAIN UNCHANGED cannot be altered. Otherwise the CMSIS-RTOS implementation is no longer
@@ -52,7 +52,7 @@ The following CMSIS-RTOS functions can be called from threads and interrupt serv
   - \ref osMessagePut, \ref osMessageGet
   - \ref osMailAlloc, \ref osMailCAlloc, \ref osMailGet, \ref osMailPut, \ref osMailFree
 
-Functions that cannot be called from an ISR are verifying the interrupt status and return in case that they are called 
+Functions that cannot be called from an ISR are verifying the interrupt status and return in case that they are called
 from an ISR context the status code \b osErrorISR. In some implementations this condition might be caught using the HARD FAULT vector.
 
 Some CMSIS-RTOS implementations support CMSIS-RTOS function calls from multiple ISR at the same time.
@@ -73,11 +73,11 @@ extern void thread_sample (void const *argument);             // function protot
 osThreadDef (thread_sample, osPriorityBelowNormal, 1, 100);
 
 // Pool definition
-osPoolDef(MyPool, 10, long);                      
+osPoolDef(MyPool, 10, long);
 \endcode
 
 
-This header file defines all objects when included in a C/C++ source file. When \#define osObjectsExternal is 
+This header file defines all objects when included in a C/C++ source file. When \#define osObjectsExternal is
 present before the header file, the objects are defined as external symbols. A single consistent header file can therefore be
 used throughout the whole project.
 
@@ -92,7 +92,7 @@ used throughout the whole project.
 \endcode
 
 */
- 
+
 #ifndef _CMSIS_OS_H
 #define _CMSIS_OS_H
 
@@ -100,7 +100,7 @@ used throughout the whole project.
 #define osCMSIS           0x00003      ///< API version (main [31:16] .sub [15:0])
 
 /// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlaying RTOS kernel and version number.
-#define osCMSIS_KERNEL    0x10000	   ///< RTOS identification and version (main [31:16] .sub [15:0])
+#define osCMSIS_KERNEL    0x10000      ///< RTOS identification and version (main [31:16] .sub [15:0])
 
 /// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS.
 #define osKernelSystemId "KERNEL V1.00"   ///< RTOS identification string
@@ -113,7 +113,7 @@ used throughout the whole project.
 #define osFeature_Signals      8       ///< maximum number of Signal Flags available per thread
 #define osFeature_Semaphore    30      ///< maximum count for SemaphoreInit function
 #define osFeature_Wait         1       ///< osWait function: 1=available, 0=not available
-                                    
+
 #include 
 #include 
 
@@ -133,7 +133,7 @@ typedef enum  {
   osPriorityBelowNormal   = -1,          ///< priority: below normal
   osPriorityNormal        =  0,          ///< priority: normal (default)
   osPriorityAboveNormal   = +1,          ///< priority: above normal
-  osPriorityHigh          = +2,          ///< priority: high 
+  osPriorityHigh          = +2,          ///< priority: high
   osPriorityRealtime      = +3,          ///< priority: realtime (highest)
   osPriorityError         =  0x84        ///< system cannot determine priority or thread has illegal priority
 } osPriority;
@@ -160,23 +160,23 @@ typedef enum  {
   osErrorValue            =  0x86,       ///< value of a parameter is out of range.
   osErrorOS               =  0xFF,       ///< unspecified RTOS error: run-time error but no other error message fits.
   os_status_reserved      =  0x7FFFFFFF  ///< prevent from enum down-size compiler optimization.
-} osStatus; 
+} osStatus;
 
 
 /// Timer type value for the timer definition
 /// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS.
 typedef enum  {
-  osTimerOnce             =     0,       ///< one-shot timer 
-  osTimerPeriodic         =     1        ///< repeating timer 
-} os_timer_type; 
+  osTimerOnce             =     0,       ///< one-shot timer
+  osTimerPeriodic         =     1        ///< repeating timer
+} os_timer_type;
 
 /// Entry point of a thread.
 /// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS.
-typedef void (*os_pthread) (void const *argument); 
+typedef void (*os_pthread) (void const *argument);
 
 /// Entry point of a timer call back function.
 /// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS.
-typedef void (*os_ptimer) (void const *argument); 
+typedef void (*os_ptimer) (void const *argument);
 
 // >>> the following data type definitions may shall adapted towards a specific RTOS
 
@@ -240,7 +240,7 @@ typedef const struct os_semaphore_def  {
 /// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS.
 typedef const struct os_pool_def  {
   uint32_t                 pool_sz;    ///< number of items (elements) in the pool
-  uint32_t                 item_sz;    ///< size of an item 
+  uint32_t                 item_sz;    ///< size of an item
   void                       *pool;    ///< pointer to memory for pool
 } osPoolDef_t;
 
@@ -248,7 +248,7 @@ typedef const struct os_pool_def  {
 /// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS.
 typedef const struct os_messageQ_def  {
   uint32_t                queue_sz;    ///< number of elements in the queue
-  uint32_t                 item_sz;    ///< size of an item 
+  uint32_t                 item_sz;    ///< size of an item
   void                       *pool;    ///< memory array for messages
 } osMessageQDef_t;
 
@@ -256,23 +256,23 @@ typedef const struct os_messageQ_def  {
 /// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS.
 typedef const struct os_mailQ_def  {
   uint32_t                queue_sz;    ///< number of elements in the queue
-  uint32_t                 item_sz;    ///< size of an item 
+  uint32_t                 item_sz;    ///< size of an item
   void                       *pool;    ///< memory array for mail
 } osMailQDef_t;
 
-/// Event structure contains detailed information about an event. 
-/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS. 
+/// Event structure contains detailed information about an event.
+/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS.
 ///       However the struct may be extended at the end.
 typedef struct  {
   osStatus                 status;     ///< status code: event or error information
   union  {
-    uint32_t                    v;     ///< message as 32-bit value 
+    uint32_t                    v;     ///< message as 32-bit value
     void                       *p;     ///< message or mail as void pointer
-    int32_t               signals;     ///< signal flags 
+    int32_t               signals;     ///< signal flags
   } value;                             ///< event value
   union  {
-    osMailQId             mail_id;     ///< mail id obtained by \ref osMailCreate 
-    osMessageQId       message_id;     ///< message id obtained by \ref osMessageCreate 
+    osMailQId             mail_id;     ///< mail id obtained by \ref osMailCreate
+    osMessageQId       message_id;     ///< message id obtained by \ref osMessageCreate
   } def;                               ///< event definition
 } osEvent;
 
@@ -283,11 +283,11 @@ typedef struct  {
 /// \param[in]     thread_def    thread definition referenced with \ref osThread.
 /// \param[in]     argument      pointer that is passed to the thread function as start argument.
 /// \return status code that indicates the execution status of the function.
-/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS. 
+/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS.
 osStatus osKernelStart (osThreadDef_t *thread_def, void *argument);
-   
+
 /// Check if the RTOS kernel is already started.
-/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS. 
+/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS.
 /// \return 0 RTOS is not started, 1 RTOS is started.
 int32_t osKernelRunning(void);
 
@@ -299,7 +299,7 @@ int32_t osKernelRunning(void);
 /// \param         priority     initial priority of the thread function.
 /// \param         instances    number of possible thread instances.
 /// \param         stacksz      stack size (in bytes) requirements for the thread function.
-/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the 
+/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #if defined (osObjectsExternal)  // object is external
 #define osThreadDef(name, priority, instances, stacksz)  \
@@ -312,7 +312,7 @@ osThreadDef_t os_thread_def_##name = \
 
 /// Access a Thread defintion.
 /// \param         name          name of the thread definition object.
-/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the 
+/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #define osThread(name)  \
 &os_thread_def_##name
@@ -341,7 +341,7 @@ osStatus osThreadTerminate (osThreadId thread_id);
 /// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS.
 osStatus osThreadYield (void);
 
-/// Change priority of an active thread.  
+/// Change priority of an active thread.
 /// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
 /// \param[in]     priority      new priority value for the thread function.
 /// \return status code that indicates the execution status of the function.
@@ -359,7 +359,7 @@ osPriority osThreadGetPriority (osThreadId thread_id);
 //  ==== Generic Wait Functions ====
 
 /// Wait for Timeout (Time Delay)
-/// \param[in]     millisec      time delay value 
+/// \param[in]     millisec      time delay value
 /// \return status code that indicates the execution status of the function.
 osStatus osDelay (uint32_t millisec);
 
@@ -378,7 +378,7 @@ osEvent osWait (uint32_t millisec);
 /// Define a Timer object.
 /// \param         name          name of the timer object.
 /// \param         function      name of the timer call back function.
-/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the 
+/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #if defined (osObjectsExternal)  // object is external
 #define osTimerDef(name, function)  \
@@ -391,7 +391,7 @@ osTimerDef_t os_timer_def_##name = \
 
 /// Access a Timer definition.
 /// \param         name          name of the timer object.
-/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the 
+/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #define osTimer(name) \
 &os_timer_def_##name
@@ -452,7 +452,7 @@ osEvent osSignalWait (int32_t signals, uint32_t millisec);
 
 /// Define a Mutex.
 /// \param         name          name of the mutex object.
-/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the 
+/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #if defined (osObjectsExternal)  // object is external
 #define osMutexDef(name)  \
@@ -464,7 +464,7 @@ osMutexDef_t os_mutex_def_##name = { 0 }
 
 /// Access a Mutex defintion.
 /// \param         name          name of the mutex object.
-/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the 
+/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #define osMutex(name)  \
 &os_mutex_def_##name
@@ -495,7 +495,7 @@ osStatus osMutexRelease (osMutexId mutex_id);
 
 /// Define a Semaphore object.
 /// \param         name          name of the semaphore object.
-/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the 
+/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #if defined (osObjectsExternal)  // object is external
 #define osSemaphoreDef(name)  \
@@ -507,7 +507,7 @@ osSemaphoreDef_t os_semaphore_def_##name = { 0 }
 
 /// Access a Semaphore definition.
 /// \param         name          name of the semaphore object.
-/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the 
+/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #define osSemaphore(name)  \
 &os_semaphore_def_##name
@@ -533,7 +533,7 @@ int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);
 osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
 
 #endif     // Semaphore available
- 
+
 //  ==== Memory Pool Management Functions ====
 
 #if (defined (osFeature_Pool)  &&  (osFeature_Pool != 0))  // Memory Pool Management available
@@ -542,7 +542,7 @@ osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
 /// \param         name          name of the memory pool.
 /// \param         no            maximum number of objects (elements) in the memory pool.
 /// \param         type          data type of a single object (element).
-/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the 
+/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #if defined (osObjectsExternal)  // object is external
 #define osPoolDef(name, no, type)   \
@@ -555,7 +555,7 @@ osPoolDef_t os_pool_def_##name = \
 
 /// \brief Access a Memory Pool definition.
 /// \param         name          name of the memory pool
-/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the 
+/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #define osPool(name) \
 &os_pool_def_##name
@@ -572,7 +572,7 @@ osPoolId osPoolCreate (osPoolDef_t *pool_def);
 /// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS.
 void *osPoolAlloc (osPoolId pool_id);
 
-/// Allocate a memory block from a memory pool and set memory block to zero 
+/// Allocate a memory block from a memory pool and set memory block to zero
 /// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
 /// \return address of the allocated memory block or NULL in case of no memory available.
 /// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS.
@@ -596,7 +596,7 @@ osStatus osPoolFree (osPoolId pool_id, void *block);
 /// \param         name          name of the queue.
 /// \param         queue_sz      maximum number of messages in the queue.
 /// \param         type          data type of a single message element (for debugger).
-/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the 
+/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #if defined (osObjectsExternal)  // object is external
 #define osMessageQDef(name, queue_sz, type)   \
@@ -609,7 +609,7 @@ osMessageQDef_t os_messageQ_def_##name = \
 
 /// \brief Access a Message Queue Definition.
 /// \param         name          name of the queue
-/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the 
+/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #define osMessageQ(name) \
 &os_messageQ_def_##name
@@ -647,7 +647,7 @@ osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
 /// \param         name          name of the queue
 /// \param         queue_sz      maximum number of messages in queue
 /// \param         type          data type of a single message element
-/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the 
+/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #if defined (osObjectsExternal)  // object is external
 #define osMailQDef(name, queue_sz, type) \
@@ -657,10 +657,10 @@ extern osMailQDef_t os_mailQ_def_##name
 osMailQDef_t os_mailQ_def_##name =  \
 { (queue_sz), sizeof (type) }
 #endif
-     
+
 /// \brief Access a Mail Queue Definition
 /// \param         name          name of the queue
-/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the 
+/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the
 ///       macro body is implementation specific in every CMSIS-RTOS.
 #define osMailQ(name)  \
 &os_mailQ_def_##name
@@ -706,7 +706,7 @@ osEvent osMailGet (osMailQId queue_id, uint32_t millisec);
 /// \return status code that indicates the execution status of the function.
 /// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS.
 osStatus osMailFree (osMailQId queue_id, void *mail);
-                            
+
 #endif  // Mail Queues available
 
 
diff --git a/bsp/efm32/Libraries/Device/EnergyMicro/EFM32G/Source/IAR/startup_efm32g.c b/bsp/efm32/Libraries/Device/EnergyMicro/EFM32G/Source/IAR/startup_efm32g.c
index 1713a1aed5..2328977341 100644
--- a/bsp/efm32/Libraries/Device/EnergyMicro/EFM32G/Source/IAR/startup_efm32g.c
+++ b/bsp/efm32/Libraries/Device/EnergyMicro/EFM32G/Source/IAR/startup_efm32g.c
@@ -39,7 +39,7 @@ extern void __iar_program_start(void);
 extern void SystemInit(void);
 
 /* Auto defined by linker */
-extern unsigned char CSTACK$$Limit; 
+extern unsigned char CSTACK$$Limit;
 
 __weak void Reset_Handler(void)
 {
diff --git a/bsp/efm32/Libraries/Device/EnergyMicro/EFM32G/Source/system_efm32g.c b/bsp/efm32/Libraries/Device/EnergyMicro/EFM32G/Source/system_efm32g.c
index d343bd4357..a11e3de7a2 100644
--- a/bsp/efm32/Libraries/Device/EnergyMicro/EFM32G/Source/system_efm32g.c
+++ b/bsp/efm32/Libraries/Device/EnergyMicro/EFM32G/Source/system_efm32g.c
@@ -64,18 +64,18 @@
 /* Do not define variable if HF crystal oscillator not present */
 #if (EFM32_HFXO_FREQ > 0)
 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
-/** System HFXO clock. */ 
+/** System HFXO clock. */
 static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ;
 /** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
 #endif
 
-#ifndef EFM32_LFXO_FREQ 
+#ifndef EFM32_LFXO_FREQ
 #define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ)
 #endif
 /* Do not define variable if LF crystal oscillator not present */
 #if (EFM32_LFXO_FREQ > 0)
 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
-/** System LFXO clock. */ 
+/** System LFXO clock. */
 static uint32_t SystemLFXOClock = EFM32_LFXO_FREQ;
 /** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
 #endif
@@ -118,13 +118,13 @@ uint32_t SystemCoreClock;
 uint32_t SystemCoreClockGet(void)
 {
   uint32_t ret;
-  
+
   ret = SystemHFClockGet();
 #if defined (_EFM32_GIANT_FAMILY)
   /* Leopard/Giant Gecko has an additional divider */
   ret =  ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)>>_CMU_CTRL_HFCLKDIV_SHIFT));
 #endif
-  ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >> 
+  ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >>
           _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT;
 
   /* Keep CMSIS variable up-to-date just in case */
@@ -147,7 +147,7 @@ uint32_t SystemCoreClockGet(void)
 uint32_t SystemHFClockGet(void)
 {
   uint32_t ret;
-  
+
   switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL |
                          CMU_STATUS_LFRCOSEL | CMU_STATUS_LFXOSEL))
   {
@@ -160,11 +160,11 @@ uint32_t SystemHFClockGet(void)
       ret = 0;
 #endif
       break;
-      
+
     case CMU_STATUS_LFRCOSEL:
       ret = EFM32_LFRCO_FREQ;
       break;
-      
+
     case CMU_STATUS_HFXOSEL:
 #if (EFM32_HFXO_FREQ > 0)
       ret = SystemHFXOClock;
@@ -174,7 +174,7 @@ uint32_t SystemHFClockGet(void)
       ret = 0;
 #endif
       break;
-      
+
     default: /* CMU_STATUS_HFRCOSEL */
       switch (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK)
       {
diff --git a/bsp/efm32/Libraries/Device/EnergyMicro/EFM32GG/Source/IAR/startup_efm32gg.c b/bsp/efm32/Libraries/Device/EnergyMicro/EFM32GG/Source/IAR/startup_efm32gg.c
index 0e3124dcea..356dec376b 100644
--- a/bsp/efm32/Libraries/Device/EnergyMicro/EFM32GG/Source/IAR/startup_efm32gg.c
+++ b/bsp/efm32/Libraries/Device/EnergyMicro/EFM32GG/Source/IAR/startup_efm32gg.c
@@ -39,7 +39,7 @@ extern void __iar_program_start(void);
 extern void SystemInit(void);
 
 /* Auto defined by linker */
-extern unsigned char CSTACK$$Limit; 
+extern unsigned char CSTACK$$Limit;
 
 __weak void Reset_Handler(void)
 {
diff --git a/bsp/efm32/Libraries/Device/EnergyMicro/EFM32GG/Source/system_efm32gg.c b/bsp/efm32/Libraries/Device/EnergyMicro/EFM32GG/Source/system_efm32gg.c
index c7709f9a64..841ac171b6 100644
--- a/bsp/efm32/Libraries/Device/EnergyMicro/EFM32GG/Source/system_efm32gg.c
+++ b/bsp/efm32/Libraries/Device/EnergyMicro/EFM32GG/Source/system_efm32gg.c
@@ -64,18 +64,18 @@
 /* Do not define variable if HF crystal oscillator not present */
 #if (EFM32_HFXO_FREQ > 0)
 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
-/** System HFXO clock. */ 
+/** System HFXO clock. */
 static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ;
 /** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
 #endif
 
-#ifndef EFM32_LFXO_FREQ 
+#ifndef EFM32_LFXO_FREQ
 #define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ)
 #endif
 /* Do not define variable if LF crystal oscillator not present */
 #if (EFM32_LFXO_FREQ > 0)
 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
-/** System LFXO clock. */ 
+/** System LFXO clock. */
 static uint32_t SystemLFXOClock = EFM32_LFXO_FREQ;
 /** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
 #endif
@@ -118,13 +118,13 @@ uint32_t SystemCoreClock;
 uint32_t SystemCoreClockGet(void)
 {
   uint32_t ret;
-  
+
   ret = SystemHFClockGet();
 #if defined (_EFM32_GIANT_FAMILY)
   /* Leopard/Giant Gecko has an additional divider */
   ret =  ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)>>_CMU_CTRL_HFCLKDIV_SHIFT));
 #endif
-  ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >> 
+  ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >>
           _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT;
 
   /* Keep CMSIS variable up-to-date just in case */
@@ -147,7 +147,7 @@ uint32_t SystemCoreClockGet(void)
 uint32_t SystemHFClockGet(void)
 {
   uint32_t ret;
-  
+
   switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL |
                          CMU_STATUS_LFRCOSEL | CMU_STATUS_LFXOSEL))
   {
@@ -160,11 +160,11 @@ uint32_t SystemHFClockGet(void)
       ret = 0;
 #endif
       break;
-      
+
     case CMU_STATUS_LFRCOSEL:
       ret = EFM32_LFRCO_FREQ;
       break;
-      
+
     case CMU_STATUS_HFXOSEL:
 #if (EFM32_HFXO_FREQ > 0)
       ret = SystemHFXOClock;
@@ -174,7 +174,7 @@ uint32_t SystemHFClockGet(void)
       ret = 0;
 #endif
       break;
-      
+
     default: /* CMU_STATUS_HFRCOSEL */
       switch (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK)
       {
diff --git a/bsp/efm32/Libraries/emlib/inc/em_acmp.h b/bsp/efm32/Libraries/emlib/inc/em_acmp.h
index 0c20ead97f..bc36e3c618 100644
--- a/bsp/efm32/Libraries/emlib/inc/em_acmp.h
+++ b/bsp/efm32/Libraries/emlib/inc/em_acmp.h
@@ -173,7 +173,7 @@ typedef struct
    *  power used by the VDD and bandgap references. */
   bool                          lowPowerReferenceEnabled;
 
-  /** Vdd reference value. VDD_SCALED = VDD  VDDLEVEL  50mV/3.8V.
+  /** Vdd reference value. VDD_SCALED = VDD × VDDLEVEL × 50mV/3.8V.
    *  Valid values are in the range 0-63. */
   uint32_t                      vddLevel;
 
@@ -229,7 +229,7 @@ typedef struct
    *  power used by the VDD and bandgap references. */
   bool                         lowPowerReferenceEnabled;
 
-  /** Vdd reference value. VDD_SCALED = VDD  VDDLEVEL  50mV/3.8V.
+  /** Vdd reference value. VDD_SCALED = VDD × VDDLEVEL × 50mV/3.8V.
    *  Valid values are in the range 0-63. */
   uint32_t                     vddLevel;
 
diff --git a/bsp/efm32/Libraries/emlib/inc/em_burtc.h b/bsp/efm32/Libraries/emlib/inc/em_burtc.h
index 3f7233a5c5..8e6d11ec6a 100644
--- a/bsp/efm32/Libraries/emlib/inc/em_burtc.h
+++ b/bsp/efm32/Libraries/emlib/inc/em_burtc.h
@@ -289,8 +289,8 @@ __STATIC_INLINE void BURTC_Enable(bool enable)
   if( enable )
   {
     BITBAND_Peripheral(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 0);
-  } 
-  else 
+  }
+  else
   {
     BITBAND_Peripheral(&BURTC->CTRL, _BURTC_CTRL_RSTEN_SHIFT, 1);
   }
diff --git a/bsp/efm32/Libraries/emlib/inc/em_cmu.h b/bsp/efm32/Libraries/emlib/inc/em_cmu.h
index 7f0a3fbd4c..881fd77174 100644
--- a/bsp/efm32/Libraries/emlib/inc/em_cmu.h
+++ b/bsp/efm32/Libraries/emlib/inc/em_cmu.h
@@ -432,7 +432,7 @@ typedef enum
 #endif
 
 #if defined(USB_PRESENT)
-  cmuClock_USBC = (CMU_NODIV_REG << CMU_DIV_REG_POS) | 
+  cmuClock_USBC = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
                   (CMU_USBCCLKSEL_REG << CMU_SEL_REG_POS) |
                   (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
                   (_CMU_HFCORECLKEN0_USBC_SHIFT << CMU_EN_BIT_POS) |
@@ -441,7 +441,7 @@ typedef enum
 #endif
 
 #if defined(USB_PRESENT)
-  cmuClock_USB = (CMU_NODIV_REG << CMU_DIV_REG_POS) | 
+  cmuClock_USB = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
                  (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
                  (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
                  (_CMU_HFCORECLKEN0_USB_SHIFT << CMU_EN_BIT_POS) |
diff --git a/bsp/efm32/Libraries/emlib/inc/em_dma.h b/bsp/efm32/Libraries/emlib/inc/em_dma.h
index 5ce256296f..544ccb5bc3 100644
--- a/bsp/efm32/Libraries/emlib/inc/em_dma.h
+++ b/bsp/efm32/Libraries/emlib/inc/em_dma.h
@@ -251,7 +251,7 @@ typedef struct
   /** Enable repeated loop */
   bool      enable;
   /** Width of transfer, reload value for nMinus1 */
-  uint16_t  nMinus1;  
+  uint16_t  nMinus1;
 } DMA_CfgLoop_TypeDef;
 
 
@@ -335,20 +335,20 @@ typedef struct
    * Pointer to the controlblock in memory holding descriptors (channel
    * control data structures). This memory must be properly aligned
    * according to requirements.
-   * 
+   *
    * Alignment requirements are
    *   a) 5 bits base requirement, bits [4:0]
    *   b) Add the number of bits needed to represent the wanted number
    *      of channels
    *   c) Align structure with this number of bits set to zero
-   *  
+   *
    * Examples: 4 channels, 5 + 2 (channels 0 to 3) = 7 bits
    *           7 bit alignment, 64 byte address alignment
    *           8 channels, 5 + 3 (channels 0 to 7) = 8 bits
    *           8 bit alignment, 256 byte address alignment
    *           12 channels, 5 + 4 (channels 0 to 11) = 9 bits
    *           9 bit alignment, 512 byte address alignment
-   * 
+   *
    * Please refer to the reference manual, DMA chapter for more details.
    *
    * It is possible to provide a smaller memory block, only covering
diff --git a/bsp/efm32/Libraries/emlib/inc/em_ebi.h b/bsp/efm32/Libraries/emlib/inc/em_ebi.h
index 43bf58de2c..dbfe09e74e 100644
--- a/bsp/efm32/Libraries/emlib/inc/em_ebi.h
+++ b/bsp/efm32/Libraries/emlib/inc/em_ebi.h
@@ -157,7 +157,7 @@ typedef enum
 } EBI_ALow_TypeDef;
 
 /** Adress Pin Enable, high limit - higher limit of pins to enable */
-typedef enum 
+typedef enum
 {
   /** All EBI_A pins are disabled */
   ebiAHighA0 = EBI_ROUTE_APEN_A0,
@@ -218,9 +218,9 @@ typedef enum {
   /** EBI PIN I/O Location 1 */
   ebiLocation1 = EBI_ROUTE_LOCATION_LOC1,
   /** EBI PIN I/O Location 2 */
-  ebiLocation2 = EBI_ROUTE_LOCATION_LOC2,  
+  ebiLocation2 = EBI_ROUTE_LOCATION_LOC2,
   /** EBI PIN I/O Location 3 */
-  // ebiLocation3 = EBI_ROUTE_LOCATION_LOC3,  
+  // ebiLocation3 = EBI_ROUTE_LOCATION_LOC3,
 } EBI_Location_TypeDef;
 #endif
 
@@ -626,7 +626,7 @@ __STATIC_INLINE void EBI_TFTPixelSet(int pixel, uint32_t color)
  ******************************************************************************/
 __STATIC_INLINE void EBI_TFTMaskBlendMode(EBI_TFTMaskBlend_TypeDef maskBlend)
 {
-  EBI->TFTCTRL = (EBI->TFTCTRL & (~_EBI_TFTCTRL_MASKBLEND_MASK))|maskBlend;                  
+  EBI->TFTCTRL = (EBI->TFTCTRL & (~_EBI_TFTCTRL_MASKBLEND_MASK))|maskBlend;
 }
 
 
@@ -676,7 +676,7 @@ __STATIC_INLINE uint32_t EBI_TFTHCount(void)
 
 
 /***************************************************************************//**
- * @brief Set Frame Buffer Trigger  
+ * @brief Set Frame Buffer Trigger
  *   Frame buffer pointer will be updated either on each horizontal line (hsync)
  *   or vertical update (vsync)(
  ******************************************************************************/
diff --git a/bsp/efm32/Libraries/emlib/inc/em_emu.h b/bsp/efm32/Libraries/emlib/inc/em_emu.h
index ea000c6c2f..c6687d41a0 100644
--- a/bsp/efm32/Libraries/emlib/inc/em_emu.h
+++ b/bsp/efm32/Libraries/emlib/inc/em_emu.h
@@ -62,8 +62,8 @@ typedef enum
   /** Select ULFRCO as duty oscillator in EM4 */
   emuEM4Osc_ULFRCO = EMU_EM4CONF_OSC_ULFRCO,
   /** Select LFXO as duty oscillator in EM4 */
-  emuEM4Osc_LFXO = EMU_EM4CONF_OSC_LFXO, 
-  /** Select LFRCO as duty oscillator in EM4 */    
+  emuEM4Osc_LFXO = EMU_EM4CONF_OSC_LFXO,
+  /** Select LFRCO as duty oscillator in EM4 */
   emuEM4Osc_LFRCO = EMU_EM4CONF_OSC_LFRCO
 } EMU_EM4Osc_TypeDef;
 
@@ -124,15 +124,15 @@ typedef enum
 
 #if defined(_EFM32_GIANT_FAMILY)
 /** Energy Mode 4 initialization structure  */
-typedef struct 
+typedef struct
 {
   /** Lock configuration of regulator, BOD and oscillator */
   bool               lockConfig;
   /** EM4 duty oscillator */
-  EMU_EM4Osc_TypeDef osc;  
+  EMU_EM4Osc_TypeDef osc;
   /** Wake up on EM4 BURTC interrupt */
   bool               buRtcWakeup;
-  /** Enable EM4 voltage regulator */  
+  /** Enable EM4 voltage regulator */
   bool               vreg;
 } EMU_EM4Init_TypeDef;
 
@@ -145,7 +145,7 @@ typedef struct
   }
 
 /** Backup Power Domain Initialization structure */
-typedef struct 
+typedef struct
 {
   /* Backup Power Domain power configuration */
 
@@ -153,7 +153,7 @@ typedef struct
   EMU_Probe_TypeDef probe;
   /** Enable BOD calibration mode */
   bool              bodCal;
-  /** Enable BU_STAT status pin for active BU mode */ 
+  /** Enable BU_STAT status pin for active BU mode */
   bool              statusPinEnable;
 
   /* Backup Power Domain connection configuration */
diff --git a/bsp/efm32/Libraries/emlib/inc/em_msc.h b/bsp/efm32/Libraries/emlib/inc/em_msc.h
index 0af96f9271..ac00aac98a 100644
--- a/bsp/efm32/Libraries/emlib/inc/em_msc.h
+++ b/bsp/efm32/Libraries/emlib/inc/em_msc.h
@@ -88,7 +88,7 @@ typedef enum
 
 #if defined (_EFM32_GIANT_FAMILY)
 /** Strategy for prioritized bus access */
-typedef enum { 
+typedef enum {
   mscBusStrategyCPU = MSC_READCTRL_BUSSTRATEGY_CPU, /**< Prioritize CPU bus accesses */
   mscBusStrategyDMA = MSC_READCTRL_BUSSTRATEGY_DMA, /**< Prioritize DMA bus accesses */
   mscBusStrategyDMAEM1 = MSC_READCTRL_BUSSTRATEGY_DMAEM1, /**< Prioritize DMAEM1 for bus accesses */
diff --git a/bsp/efm32/Libraries/emlib/inc/em_rmu.h b/bsp/efm32/Libraries/emlib/inc/em_rmu.h
index c180344616..8ee5ebec33 100644
--- a/bsp/efm32/Libraries/emlib/inc/em_rmu.h
+++ b/bsp/efm32/Libraries/emlib/inc/em_rmu.h
@@ -59,10 +59,10 @@ typedef enum
 {
 #if defined(_EFM32_GIANT_FAMILY)
   /** Reset control over Backup Power Domain */
-  rmuResetBU = _RMU_CTRL_BURSTEN_SHIFT,        
+  rmuResetBU = _RMU_CTRL_BURSTEN_SHIFT,
 #endif
   /** Allow Cortex-M3 lock up signal */
-  rmuResetLockUp = _RMU_CTRL_LOCKUPRDIS_SHIFT 
+  rmuResetLockUp = _RMU_CTRL_LOCKUPRDIS_SHIFT
 } RMU_Reset_TypeDef;
 
 /*******************************************************************************
diff --git a/bsp/efm32/Libraries/emlib/inc/em_usart.h b/bsp/efm32/Libraries/emlib/inc/em_usart.h
index e30d75c7fe..d36209bc37 100644
--- a/bsp/efm32/Libraries/emlib/inc/em_usart.h
+++ b/bsp/efm32/Libraries/emlib/inc/em_usart.h
@@ -276,7 +276,7 @@ typedef struct
 
 #if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY)
 /** USART PRS trigger enable */
-typedef struct 
+typedef struct
 {
 #if defined(_EFM32_GIANT_FAMILY)
   /** Enable AUTOTX */
diff --git a/bsp/efm32/Libraries/emlib/src/em_burtc.c b/bsp/efm32/Libraries/emlib/src/em_burtc.c
index 005c7770fb..dac6645c67 100644
--- a/bsp/efm32/Libraries/emlib/src/em_burtc.c
+++ b/bsp/efm32/Libraries/emlib/src/em_burtc.c
@@ -87,7 +87,7 @@ __STATIC_INLINE uint32_t BURTC_DivToLog2(uint32_t div)
  *    Configures the BURTC peripheral.
  *
  * @note
- *   Before initialization, BURTC module must first be enabled by clearing the 
+ *   Before initialization, BURTC module must first be enabled by clearing the
  *   reset bit in the RMU, i.e.
  * @verbatim
  *   RMU_ResetControl(rmuResetBU, false);
@@ -123,7 +123,7 @@ void BURTC_Init(const BURTC_Init_TypeDef *burtcInit)
   presc = BURTC_DivToLog2(burtcInit->clkDiv);
 
   /* Make sure all registers are updated simultaneously */
-  if (burtcInit->enable) 
+  if (burtcInit->enable)
   {
     BURTC_FreezeEnable(true);
   }
@@ -132,7 +132,7 @@ void BURTC_Init(const BURTC_Init_TypeDef *burtcInit)
   BURTC->LPMODE = (uint32_t)(burtcInit->lowPowerMode);
 
   /* New configuration */
-  ctrl = ((BURTC_CTRL_RSTEN) | 
+  ctrl = ((BURTC_CTRL_RSTEN) |
           (burtcInit->mode) |
           (burtcInit->debugRun << _BURTC_CTRL_DEBUGRUN_SHIFT) |
           (burtcInit->compare0Top << _BURTC_CTRL_COMP0TOP_SHIFT) |
diff --git a/bsp/efm32/Libraries/emlib/src/em_cmu.c b/bsp/efm32/Libraries/emlib/src/em_cmu.c
index 974ff932d6..516f7b68ca 100644
--- a/bsp/efm32/Libraries/emlib/src/em_cmu.c
+++ b/bsp/efm32/Libraries/emlib/src/em_cmu.c
@@ -1377,14 +1377,14 @@ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref)
       /* frequencies above 32MHz */
       if(SystemHFXOClockGet() > CMU_MAX_FREQ_HFLE)
       {
-        CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) | 
-          CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ | 
+        CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) |
+          CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ |
           /* Must have HFLE enabled to access some LE peripherals >=32MHz */
           CMU_CTRL_HFLE;
       } else {
         /* This can happen if the user configures the EFM32_HFXO_FREQ to */
         /* use another oscillator frequency */
-        CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) | 
+        CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) |
           CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ;
       }
 #endif
@@ -1475,7 +1475,7 @@ void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref)
         BITBAND_Peripheral(&(CMU->CTRL), _CMU_CTRL_HFLE_SHIFT, 1);
 
         /* Enable DIV4 factor for peripheral clock */
-        BITBAND_Peripheral(&(CMU->HFCORECLKDIV), 
+        BITBAND_Peripheral(&(CMU->HFCORECLKDIV),
                            _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);
       }
 #endif
diff --git a/bsp/efm32/Libraries/emlib/src/em_ebi.c b/bsp/efm32/Libraries/emlib/src/em_ebi.c
index 8f8439e7fa..52ef36716b 100644
--- a/bsp/efm32/Libraries/emlib/src/em_ebi.c
+++ b/bsp/efm32/Libraries/emlib/src/em_ebi.c
@@ -105,7 +105,7 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit)
     ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTODIS_SHIFT);
     ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL_SHIFT);
     ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE_SHIFT);
-    if ( ebiInit->enable) 
+    if ( ebiInit->enable)
     {
       ctrl |= EBI_CTRL_BANK0EN;
     }
@@ -117,13 +117,13 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit)
               _EBI_CTRL_ARDY1EN_MASK|
               _EBI_CTRL_ARDYTO1DIS_MASK|
               _EBI_CTRL_NOIDLE1_MASK|
-              _EBI_CTRL_BANK1EN_MASK); 
+              _EBI_CTRL_BANK1EN_MASK);
     ctrl |= (ebiInit->mode << _EBI_CTRL_MODE1_SHIFT);
     ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY1EN_SHIFT);
     ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO1DIS_SHIFT);
     ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL1_SHIFT);
     ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE1_SHIFT);
-    if ( ebiInit->enable) 
+    if ( ebiInit->enable)
     {
       ctrl |= EBI_CTRL_BANK1EN;
     }
@@ -141,7 +141,7 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit)
     ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO2DIS_SHIFT);
     ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL2_SHIFT);
     ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE2_SHIFT);
-    if ( ebiInit->enable) 
+    if ( ebiInit->enable)
     {
       ctrl |= EBI_CTRL_BANK2EN;
     }
@@ -153,13 +153,13 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit)
               _EBI_CTRL_ARDY3EN_MASK|
               _EBI_CTRL_ARDYTO3DIS_MASK|
               _EBI_CTRL_NOIDLE3_MASK|
-              _EBI_CTRL_BANK3EN_MASK); 
+              _EBI_CTRL_BANK3EN_MASK);
     ctrl |= (ebiInit->mode << _EBI_CTRL_MODE3_SHIFT);
     ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY3EN_SHIFT);
     ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO3DIS_SHIFT);
     ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL3_SHIFT);
     ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE3_SHIFT);
-    if ( ebiInit->enable) 
+    if ( ebiInit->enable)
     {
       ctrl |= EBI_CTRL_BANK3EN;
     }
@@ -172,7 +172,7 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit)
             _EBI_CTRL_BANK1EN_MASK|
             _EBI_CTRL_BANK2EN_MASK|
             _EBI_CTRL_BANK3EN_MASK);
-  if ( ebiInit->enable) 
+  if ( ebiInit->enable)
   {
     if ( ebiInit->banks & EBI_BANK0 )
     {
@@ -265,7 +265,7 @@ void EBI_Init(const EBI_Init_TypeDef *ebiInit)
   EBI_ChipSelectEnable(ebiInit->csLines, true);
 
   /* Activate new configuration */
-  EBI->CTRL = ctrl;  
+  EBI->CTRL = ctrl;
 }
 
 
diff --git a/bsp/efm32/Libraries/emlib/src/em_emu.c b/bsp/efm32/Libraries/emlib/src/em_emu.c
index fc8587636c..5df9fb577a 100644
--- a/bsp/efm32/Libraries/emlib/src/em_emu.c
+++ b/bsp/efm32/Libraries/emlib/src/em_emu.c
@@ -402,16 +402,16 @@ void EMU_EM4Init(EMU_EM4Init_TypeDef *em4init)
     _EMU_EM4CONF_OSC_MASK|
     _EMU_EM4CONF_BURTCWU_MASK|
     _EMU_EM4CONF_VREGEN_MASK);
-  
+
   /* Configure new settings */
   em4conf |= (
     (em4init->lockConfig << _EMU_EM4CONF_LOCKCONF_SHIFT)|
     (em4init->osc)|
     (em4init->buRtcWakeup << _EMU_EM4CONF_BURTCWU_SHIFT)|
     (em4init->vreg << _EMU_EM4CONF_VREGEN_SHIFT));
-  
+
   /* Apply configuration. Note that lock can be set after this stage. */
-  EMU->EM4CONF = em4conf;    
+  EMU->EM4CONF = em4conf;
 }
 
 
@@ -432,15 +432,15 @@ void EMU_BUPDInit(EMU_BUPDInit_TypeDef *bupdInit)
     _EMU_PWRCONF_VOUTSTRONG_MASK|
     _EMU_PWRCONF_VOUTMED_MASK|
     _EMU_PWRCONF_VOUTWEAK_MASK);
-  
+
   reg |= (bupdInit->resistor|
          (bupdInit->voutStrong << _EMU_PWRCONF_VOUTSTRONG_SHIFT)|
          (bupdInit->voutMed    << _EMU_PWRCONF_VOUTMED_SHIFT)|
-         (bupdInit->voutWeak   << _EMU_PWRCONF_VOUTWEAK_SHIFT)); 
-  
+         (bupdInit->voutWeak   << _EMU_PWRCONF_VOUTWEAK_SHIFT));
+
   EMU->PWRCONF = reg;
 
-  /* Set backup domain inactive mode configuration */ 
+  /* Set backup domain inactive mode configuration */
   reg = EMU->BUINACT & ~(_EMU_BUINACT_PWRCON_MASK);
   reg |= (bupdInit->inactivePower);
   EMU->BUINACT = reg;
@@ -456,14 +456,14 @@ void EMU_BUPDInit(EMU_BUPDInit_TypeDef *bupdInit)
     _EMU_BUCTRL_BODCAL_MASK|
     _EMU_BUCTRL_STATEN_MASK|
     _EMU_BUCTRL_EN_MASK);
-             
-  /* Note use of ->enable to both enable BUPD, use BU_VIN pin input and 
+
+  /* Note use of ->enable to both enable BUPD, use BU_VIN pin input and
      release reset */
   reg |= (bupdInit->probe|
          (bupdInit->bodCal          << _EMU_BUCTRL_BODCAL_SHIFT)|
          (bupdInit->statusPinEnable << _EMU_BUCTRL_STATEN_SHIFT)|
          (bupdInit->enable          << _EMU_BUCTRL_EN_SHIFT));
-  
+
   /* Enable configuration */
   EMU->BUCTRL = reg;
 
@@ -479,14 +479,14 @@ void EMU_BUPDInit(EMU_BUPDInit_TypeDef *bupdInit)
  * @brief
  *   Configure Backup Power Domain BOD Threshold value
  * @note
- *   These values are precalibrated 
+ *   These values are precalibrated
  * @param[in] mode Active or Inactive mode
  * @param[in] value
  ******************************************************************************/
 void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value)
 {
   EFM_ASSERT(value<4);
-  
+
   switch(mode)
   {
   case emuBODMode_Active:
@@ -503,7 +503,7 @@ void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value)
  * @brief
  *  Configure Backup Power Domain BOD Threshold Range
  * @note
- *  These values are precalibrated 
+ *  These values are precalibrated
  * @param[in] mode Active or Inactive mode
  * @param[in] value
  ******************************************************************************/
diff --git a/bsp/efm32/Libraries/emlib/src/em_lesense.c b/bsp/efm32/Libraries/emlib/src/em_lesense.c
index 8dc9c1ec7d..4482b20cce 100644
--- a/bsp/efm32/Libraries/emlib/src/em_lesense.c
+++ b/bsp/efm32/Libraries/emlib/src/em_lesense.c
@@ -533,7 +533,7 @@ void LESENSE_ChannelConfig(LESENSE_ChDesc_TypeDef const *confCh,
   /* Channel specific configuration of clocks, sample mode, excitation pin mode
    * alternate excitation usage and interrupt mode on scan channel chIdx in
    * LESENSE_CHchIdx_INTERACT. */
-  LESENSE->CH[chIdx].INTERACT = ((uint32_t)confCh->exClk << 
+  LESENSE->CH[chIdx].INTERACT = ((uint32_t)confCh->exClk <<
                                  _LESENSE_CH_INTERACT_EXCLK_SHIFT) |
                                 ((uint32_t)confCh->sampleClk <<
                                  _LESENSE_CH_INTERACT_SAMPLECLK_SHIFT) |
diff --git a/bsp/efm32/Libraries/emlib/src/em_msc.c b/bsp/efm32/Libraries/emlib/src/em_msc.c
index f42811219e..47f01e6168 100644
--- a/bsp/efm32/Libraries/emlib/src/em_msc.c
+++ b/bsp/efm32/Libraries/emlib/src/em_msc.c
@@ -55,7 +55,7 @@
  * @brief
  *   Enables the flash controller for writing.
  * @note
- *   IMPORTANT: This function must be called before flash operations when 
+ *   IMPORTANT: This function must be called before flash operations when
  *   AUXHFRCO clock has been changed from default 14MHz band.
  ******************************************************************************/
 void MSC_Init(void)
diff --git a/bsp/efm32/Libraries/emlib/src/em_opamp.c b/bsp/efm32/Libraries/emlib/src/em_opamp.c
index f12551430f..c44ab9c4a6 100644
--- a/bsp/efm32/Libraries/emlib/src/em_opamp.c
+++ b/bsp/efm32/Libraries/emlib/src/em_opamp.c
@@ -243,7 +243,7 @@ void OPAMP_Disable( DAC_TypeDef *dac, OPAMP_TypeDef opa )
 void OPAMP_Enable( DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef *init )
 {
   uint32_t offset;
-  
+
   EFM_ASSERT( DAC_REF_VALID( dac ) );
   EFM_ASSERT( DAC_OPA_VALID( opa ) );
   EFM_ASSERT( init->bias <= ( _DAC_BIASPROG_BIASPROG_MASK  >>
@@ -267,13 +267,13 @@ void OPAMP_Enable( DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef
     }
     else
     {
-      EFM_ASSERT( init->offset <= ( _DAC_CAL_CH0OFFSET_MASK >> 
+      EFM_ASSERT( init->offset <= ( _DAC_CAL_CH0OFFSET_MASK >>
                                     _DAC_CAL_CH0OFFSET_SHIFT   ) );
-      
+
       dac->CAL = ( dac->CAL      & ~_DAC_CAL_CH0OFFSET_MASK  ) |
-                 ( init->offset <<  _DAC_CAL_CH0OFFSET_SHIFT );        
+                 ( init->offset <<  _DAC_CAL_CH0OFFSET_SHIFT );
     }
-    
+
     dac->OPA0MUX  = (uint32_t)init->resSel                                |
                     (uint32_t)init->outMode                               |
                     init->outPen                                          |
@@ -315,11 +315,11 @@ void OPAMP_Enable( DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef
     }
     else
     {
-      EFM_ASSERT( init->offset <= ( _DAC_CAL_CH1OFFSET_MASK >> 
+      EFM_ASSERT( init->offset <= ( _DAC_CAL_CH1OFFSET_MASK >>
                                     _DAC_CAL_CH1OFFSET_SHIFT   ) );
-      
+
       dac->CAL = ( dac->CAL      & ~_DAC_CAL_CH1OFFSET_MASK  ) |
-                 ( init->offset <<  _DAC_CAL_CH1OFFSET_SHIFT );        
+                 ( init->offset <<  _DAC_CAL_CH1OFFSET_SHIFT );
     }
 
     dac->OPA1MUX  = (uint32_t)init->resSel                                |
@@ -370,11 +370,11 @@ void OPAMP_Enable( DAC_TypeDef *dac, OPAMP_TypeDef opa, const OPAMP_Init_TypeDef
     }
     else
     {
-      EFM_ASSERT( init->offset <= ( _DAC_OPAOFFSET_OPA2OFFSET_MASK >> 
+      EFM_ASSERT( init->offset <= ( _DAC_OPAOFFSET_OPA2OFFSET_MASK >>
                                     _DAC_OPAOFFSET_OPA2OFFSET_SHIFT   ) );
-      
+
       dac->CAL = ( dac->CAL      & ~_DAC_OPAOFFSET_OPA2OFFSET_MASK  ) |
-                 ( init->offset <<  _DAC_OPAOFFSET_OPA2OFFSET_SHIFT );        
+                 ( init->offset <<  _DAC_OPAOFFSET_OPA2OFFSET_SHIFT );
     }
 
     dac->OPA2MUX  = (uint32_t)init->resSel                                |
diff --git a/bsp/efm32/Libraries/emlib/src/em_rmu.c b/bsp/efm32/Libraries/emlib/src/em_rmu.c
index 93da92dee0..8a45d668cf 100644
--- a/bsp/efm32/Libraries/emlib/src/em_rmu.c
+++ b/bsp/efm32/Libraries/emlib/src/em_rmu.c
@@ -1,7 +1,7 @@
 /***************************************************************************//**
  * @file
  * @brief Reset Management Unit (RMU) peripheral module peripheral API
- *  
+ *
  * @author Energy Micro AS
  * @version 3.0.0
  *******************************************************************************
diff --git a/bsp/efm32/Libraries/emlib/src/em_timer.c b/bsp/efm32/Libraries/emlib/src/em_timer.c
index b7d8c8930e..cdca54573f 100644
--- a/bsp/efm32/Libraries/emlib/src/em_timer.c
+++ b/bsp/efm32/Libraries/emlib/src/em_timer.c
@@ -136,7 +136,7 @@ void TIMER_Init(TIMER_TypeDef *timer, const TIMER_Init_TypeDef *init)
   {
     timer->CMD = TIMER_CMD_STOP;
   }
-  
+
   /* Reset counter */
   timer->CNT = _TIMER_CNT_RESETVALUE;
 
diff --git a/bsp/efm32/Libraries/emlib/src/em_usart.c b/bsp/efm32/Libraries/emlib/src/em_usart.c
index d33fe9e30c..33a944f216 100644
--- a/bsp/efm32/Libraries/emlib/src/em_usart.c
+++ b/bsp/efm32/Libraries/emlib/src/em_usart.c
@@ -82,7 +82,7 @@
 #endif
 
 #if (UART_COUNT == 1)
-#define UART_REF_VALID(ref)     ((ref)==UART0) 
+#define UART_REF_VALID(ref)     ((ref)==UART0)
 #elif (UART_COUNT == 2)
 #define UART_REF_VALID(ref)     (((ref)==UART0) || ((ref)==UART1))
 #else
@@ -733,8 +733,8 @@ void USART_InitI2s(USART_TypeDef *usart, USART_InitI2s_TypeDef *init)
  * @brief
  *   Initialize automatic transmissions using PRS channel as trigger
  * @note
- *   Initialize USART with USART_Init() before setting up PRS configuration 
- * 
+ *   Initialize USART with USART_Init() before setting up PRS configuration
+ *
  * @param[in] usart Pointer to USART to configure
  * @param[in] init Pointer to initialization structure
  ******************************************************************************/
diff --git a/bsp/efm32/Libraries/emlib/src/em_vcmp.c b/bsp/efm32/Libraries/emlib/src/em_vcmp.c
index 6a83a22ae8..2e0d33da03 100644
--- a/bsp/efm32/Libraries/emlib/src/em_vcmp.c
+++ b/bsp/efm32/Libraries/emlib/src/em_vcmp.c
@@ -133,7 +133,7 @@ void VCMP_Init(const VCMP_Init_TypeDef *vcmpInit)
     while(!VCMP_Ready());
     VCMP_LowPowerRefSet(vcmpInit->lowPowerRef);
   }
-  
+
   /* Clear edge interrupt */
   VCMP_IntClear(VCMP_IF_EDGE);
 }
diff --git a/bsp/efm32/board.c b/bsp/efm32/board.c
index cdd44767f1..ea8b0640d2 100644
--- a/bsp/efm32/board.c
+++ b/bsp/efm32/board.c
@@ -1,8 +1,8 @@
 /***************************************************************************//**
- * @file 	board.c
- * @brief 	Board support of RT-Thread RTOS for EFM32
+ * @file    board.c
+ * @brief   Board support of RT-Thread RTOS for EFM32
  *  COPYRIGHT (C) 2012, RT-Thread Development Team
- * @author 	onelife
+ * @author  onelife
  * @version 1.0
  *******************************************************************************
  * @section License
@@ -10,12 +10,12 @@
  * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
  *******************************************************************************
  * @section Change Logs
- * Date			Author		Notes
- * 2010-12-21	onelife		Initial creation for EFM32
- * 2011-05-06	onelife		Add EFM32 development kit and SPI Flash support
- * 2011-07-12	onelife		Add SWO output enable function
- * 2011-12-08	onelife		Add giant gecko development kit support
- * 2011-12-09	onelife		Add giant gecko support
+ * Date         Author      Notes
+ * 2010-12-21   onelife     Initial creation for EFM32
+ * 2011-05-06   onelife     Add EFM32 development kit and SPI Flash support
+ * 2011-07-12   onelife     Add SWO output enable function
+ * 2011-12-08   onelife     Add giant gecko development kit support
+ * 2011-12-09   onelife     Add giant gecko support
  * 2011-12-09   onelife     Add LEUART module support
  * 2011-12-14   onelife     Add LFXO enabling routine in driver initialization
  *  function
@@ -37,19 +37,19 @@
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
-#define IS_NVIC_VECTTAB(VECTTAB) 		(((VECTTAB) == RAM_MEM_BASE) || \
-										((VECTTAB) == FLASH_MEM_BASE))
-#define IS_NVIC_OFFSET(OFFSET) 			((OFFSET) < 0x000FFFFF)
+#define IS_NVIC_VECTTAB(VECTTAB)        (((VECTTAB) == RAM_MEM_BASE) || \
+                                        ((VECTTAB) == FLASH_MEM_BASE))
+#define IS_NVIC_OFFSET(OFFSET)          ((OFFSET) < 0x000FFFFF)
 
 /***************************************************************************//**
  * @addtogroup SysTick_clock_source
  * @{
  ******************************************************************************/
 #define SysTick_CLKSource_MASK          ((rt_uint32_t)0x00000004)
-#define SysTick_CLKSource_RTC		    ((rt_uint32_t)0x00000000)
-#define SysTick_CLKSource_HFCORECLK		((rt_uint32_t)0x00000004)
-#define IS_SYSTICK_CLK_SOURCE(SOURCE)	(((SOURCE) == SysTick_CLKSource_RTC) || \
-										((SOURCE) == SysTick_CLKSource_HFCORECLK))
+#define SysTick_CLKSource_RTC           ((rt_uint32_t)0x00000000)
+#define SysTick_CLKSource_HFCORECLK     ((rt_uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE)   (((SOURCE) == SysTick_CLKSource_RTC) || \
+                                        ((SOURCE) == SysTick_CLKSource_HFCORECLK))
 /***************************************************************************//**
  * @}
  ******************************************************************************/
@@ -67,20 +67,20 @@
  * @note
  *
  * @param[in] NVIC_VectTab
- *	 Indicate the vector table is allocated in RAM or ROM
+ *   Indicate the vector table is allocated in RAM or ROM
  *
  * @param[in] Offset
  *   The vector table offset
  ******************************************************************************/
 static void NVIC_SetVectorTable(
-	rt_uint32_t NVIC_VectTab,
-	rt_uint32_t Offset)
+    rt_uint32_t NVIC_VectTab,
+    rt_uint32_t Offset)
 {
-	/* Check the parameters */
-	RT_ASSERT(IS_NVIC_VECTTAB(NVIC_VectTab));
-	RT_ASSERT(IS_NVIC_OFFSET(Offset));
+    /* Check the parameters */
+    RT_ASSERT(IS_NVIC_VECTTAB(NVIC_VectTab));
+    RT_ASSERT(IS_NVIC_OFFSET(Offset));
 
-	SCB->VTOR = NVIC_VectTab | (Offset & (rt_uint32_t)0x1FFFFF80);
+    SCB->VTOR = NVIC_VectTab | (Offset & (rt_uint32_t)0x1FFFFF80);
 }
 
 /***************************************************************************//**
@@ -95,19 +95,19 @@ static void NVIC_SetVectorTable(
 static void NVIC_Configuration(void)
 {
 #ifdef  VECT_TAB_RAM
-	/* Set the vector table allocated at 0x20000000 */
-	NVIC_SetVectorTable(RAM_MEM_BASE, 0x0);
+    /* Set the vector table allocated at 0x20000000 */
+    NVIC_SetVectorTable(RAM_MEM_BASE, 0x0);
 #else  /* VECT_TAB_FLASH  */
-	/* Set the vector table allocated at 0x00000000 */
-	NVIC_SetVectorTable(FLASH_MEM_BASE, 0x0);
+    /* Set the vector table allocated at 0x00000000 */
+    NVIC_SetVectorTable(FLASH_MEM_BASE, 0x0);
 #endif
 
-	/* Set NVIC Preemption Priority Bits: 0 bit for pre-emption, 4 bits for
-	   subpriority */
-	NVIC_SetPriorityGrouping(0x7UL);
+    /* Set NVIC Preemption Priority Bits: 0 bit for pre-emption, 4 bits for
+       subpriority */
+    NVIC_SetPriorityGrouping(0x7UL);
 
-	/* Set Base Priority Mask Register */
-	__set_BASEPRI(EFM32_BASE_PRI_DEFAULT);
+    /* Set Base Priority Mask Register */
+    __set_BASEPRI(EFM32_BASE_PRI_DEFAULT);
 }
 
 /***************************************************************************//**
@@ -119,13 +119,13 @@ static void NVIC_Configuration(void)
  * @note
  *
  * @param[in] SysTick_CLKSource
- *	 Specifies the SysTick clock source.
+ *   Specifies the SysTick clock source.
  *
  * @arg SysTick_CLKSource_HCLK_Div8
- * 	 AHB clock divided by 8 selected as SysTick clock source.
+ *   AHB clock divided by 8 selected as SysTick clock source.
  *
  * @arg SysTick_CLKSource_HCLK
- *	 AHB clock selected as SysTick clock source.
+ *   AHB clock selected as SysTick clock source.
  ******************************************************************************/
 static void SysTick_CLKSourceConfig(rt_uint32_t SysTick_CLKSource)
 {
@@ -184,14 +184,14 @@ static void  SysTick_Configuration(void)
     /* Start LETIMER0 */
     LETIMER_Init(LETIMER0, &letimerInit);
 #else
-	rt_uint32_t 	coreClk;
-	rt_uint32_t 	cnts;
+    rt_uint32_t     coreClk;
+    rt_uint32_t     cnts;
 
-	coreClk = SystemCoreClockGet();
-	cnts = coreClk / RT_TICK_PER_SECOND;
+    coreClk = SystemCoreClockGet();
+    cnts = coreClk / RT_TICK_PER_SECOND;
 
-	SysTick_Config(cnts);
-	SysTick_CLKSourceConfig(SysTick_CLKSource_HFCORECLK);
+    SysTick_Config(cnts);
+    SysTick_CLKSourceConfig(SysTick_CLKSource_HFCORECLK);
 #endif
 }
 
@@ -206,9 +206,9 @@ static void  SysTick_Configuration(void)
  ******************************************************************************/
 void Swo_Configuration(void)
 {
-	rt_uint32_t *dwt_ctrl = (rt_uint32_t *) 0xE0001000;
-	rt_uint32_t *tpiu_prescaler = (rt_uint32_t *) 0xE0040010;
-	rt_uint32_t *tpiu_protocol = (rt_uint32_t *) 0xE00400F0;
+    rt_uint32_t *dwt_ctrl = (rt_uint32_t *) 0xE0001000;
+    rt_uint32_t *tpiu_prescaler = (rt_uint32_t *) 0xE0040010;
+    rt_uint32_t *tpiu_protocol = (rt_uint32_t *) 0xE00400F0;
 
     CMU->HFPERCLKEN0 |= CMU_HFPERCLKEN0_GPIO;
     /* Enable Serial wire output pin */
@@ -258,12 +258,12 @@ void Swo_Configuration(void)
  ******************************************************************************/
 void rt_hw_board_init(void)
 {
-	/* Chip errata */
-	CHIP_Init();
+    /* Chip errata */
+    CHIP_Init();
 
     /* Initialize DVK board register access */
 #if defined(EFM32_GXXX_DK)
-	DVK_init();
+    DVK_init();
 #elif defined(EFM32GG_DK3750)
     DVK_init(DVK_Init_EBI);
 
@@ -272,12 +272,12 @@ void rt_hw_board_init(void)
     DVK_clearInterruptFlags(BC_INTFLAG_MASK);
 #endif
 
-	/* config NVIC Configuration */
-	NVIC_Configuration();
+    /* config NVIC Configuration */
+    NVIC_Configuration();
 
 #if defined(EFM32_USING_HFXO)
-	/* Configure external oscillator */
-	SystemHFXOClockSet(EFM32_HFXO_FREQUENCY);
+    /* Configure external oscillator */
+    SystemHFXOClockSet(EFM32_HFXO_FREQUENCY);
 
     /* Switching the CPU clock source to HFXO */
     CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO);
@@ -293,15 +293,15 @@ void rt_hw_board_init(void)
 
 #if defined(EFM32_SWO_ENABLE)
     /* Enable SWO */
-	Swo_Configuration();
+    Swo_Configuration();
 #endif
 
-	/* Enable high frequency peripheral clock */
-	CMU_ClockEnable(cmuClock_HFPER, true);
-	/* Enabling clock to the interface of the low energy modules */
-	CMU_ClockEnable(cmuClock_CORELE, true);
+    /* Enable high frequency peripheral clock */
+    CMU_ClockEnable(cmuClock_HFPER, true);
+    /* Enabling clock to the interface of the low energy modules */
+    CMU_ClockEnable(cmuClock_CORELE, true);
     /* Enable GPIO clock */
-	CMU_ClockEnable(cmuClock_GPIO, true);
+    CMU_ClockEnable(cmuClock_GPIO, true);
 
     /* Configure the SysTick */
     SysTick_Configuration();
@@ -318,8 +318,8 @@ void rt_hw_board_init(void)
  ******************************************************************************/
 void rt_hw_driver_init(void)
 {
-	/* Initialize DMA */
-	rt_hw_dma_init();
+    /* Initialize DMA */
+    rt_hw_dma_init();
 
     /* Select LFXO for specified module (and wait for it to stabilize) */
 #if (!defined(EFM32_USING_LFXO) && defined(RT_USING_RTC))
@@ -331,11 +331,11 @@ void rt_hw_driver_init(void)
 #error "Low frequency clock source is needed for using LEUART"
 #endif
 
-	/* Initialize USART */
+    /* Initialize USART */
 #if (defined(RT_USING_USART0) || defined(RT_USING_USART1) || \
     defined(RT_USING_USART2) || defined(RT_USING_UART0) || \
     defined(RT_USING_UART1))
-	rt_hw_usart_init();
+    rt_hw_usart_init();
 #endif
 
     /* Initialize LEUART */
@@ -343,7 +343,7 @@ void rt_hw_driver_init(void)
     rt_hw_leuart_init();
 #endif
 
-	/* Setup Console */
+    /* Setup Console */
 #if defined(EFM32_GXXX_DK)
     DVK_enablePeripheral(DVK_RS232A);
     DVK_enablePeripheral(DVK_SPI);
@@ -354,31 +354,31 @@ void rt_hw_driver_init(void)
     DVK_enablePeripheral(DVK_RS232_LEUART);
  #endif
 #endif
-	rt_console_set_device(CONSOLE_DEVICE);
+    rt_console_set_device(CONSOLE_DEVICE);
 
-	/* Initialize Timer */
+    /* Initialize Timer */
 #if (defined(RT_USING_TIMER0) || defined(RT_USING_TIMER1) || defined(RT_USING_TIMER2))
-	rt_hw_timer_init();
+    rt_hw_timer_init();
 #endif
 
-	/* Initialize ADC */
+    /* Initialize ADC */
 #if defined(RT_USING_ADC0)
-	rt_hw_adc_init();
+    rt_hw_adc_init();
 #endif
 
-	/* Initialize ACMP */
+    /* Initialize ACMP */
 #if (defined(RT_USING_ACMP0) || defined(RT_USING_ACMP1))
-	rt_hw_acmp_init();
+    rt_hw_acmp_init();
 #endif
 
-	/* Initialize IIC */
+    /* Initialize IIC */
 #if (defined(RT_USING_IIC0) || defined(RT_USING_IIC1))
-	rt_hw_iic_init();
+    rt_hw_iic_init();
 #endif
 
-	/* Initialize RTC */
+    /* Initialize RTC */
 #if defined(RT_USING_RTC)
-	rt_hw_rtc_init();
+    rt_hw_rtc_init();
 #endif
 
     /* Enable SPI access to MicroSD card */
diff --git a/bsp/efm32/board.h b/bsp/efm32/board.h
index a97b0d9bc0..b92e10194b 100644
--- a/bsp/efm32/board.h
+++ b/bsp/efm32/board.h
@@ -1,8 +1,8 @@
 /***************************************************************************//**
- * @file 	board.h
- * @brief 	Board support of RT-Thread RTOS for EFM32
+ * @file    board.h
+ * @brief   Board support of RT-Thread RTOS for EFM32
  *  COPYRIGHT (C) 2012, RT-Thread Development Team
- * @author 	onelife
+ * @author  onelife
  * @version 1.0
  *******************************************************************************
  * @section License
@@ -10,18 +10,18 @@
  * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
  *******************************************************************************
  * @section Change Logs
- * Date			Author		Notes
- * 2010-12-21	onelife		Initial creation for EFM32
- * 2011-05-06	onelife		Add EFM32 development kit and SPI Flash support
- * 2011-07-12	onelife		Add prototype for SWO output enable and interrupt
+ * Date         Author      Notes
+ * 2010-12-21   onelife     Initial creation for EFM32
+ * 2011-05-06   onelife     Add EFM32 development kit and SPI Flash support
+ * 2011-07-12   onelife     Add prototype for SWO output enable and interrupt
  *  context check functions
- * 2011-12-08	onelife		Add giant gecko development kit support
- * 2011-12-09	onelife		Add giant gecko support
+ * 2011-12-08   onelife     Add giant gecko development kit support
+ * 2011-12-09   onelife     Add giant gecko support
  * 2011-12-09   onelife     Add LEUART module support
  * 2011-12-14   onelife     Add LFXO enabling routine in driver initialization
  *  function
  * 2011-12-20   onelife     Move SPI Auto-CS setting to "rtconfig.h"
- * 2012-05-15	onelife		Modified to compatible with CMSIS v3
+ * 2012-05-15   onelife     Modified to compatible with CMSIS v3
  ******************************************************************************/
 #ifndef __BOARD_H__
 #define __BOARD_H__
@@ -72,15 +72,15 @@ extern volatile rt_uint32_t rt_system_status;
 #define EFM32_SWO_ENABLE
 #endif
 
-#define EFM32_NO_DATA				(0)
-#define EFM32_NO_POINTER			(RT_NULL)
-#define EFM32_NO_OFFSET				(-1)
-#define EFM32_NO_DMA				(-1)
+#define EFM32_NO_DATA               (0)
+#define EFM32_NO_POINTER            (RT_NULL)
+#define EFM32_NO_OFFSET             (-1)
+#define EFM32_NO_DMA                (-1)
 
 /* SECTION: SPI Flash */
 #if defined(EFM32_USING_SFLASH)
-#define SFLASH_CS_PORT 				(gpioPortC)
-#define SFLASH_CS_PIN 				(8)
+#define SFLASH_CS_PORT              (gpioPortC)
+#define SFLASH_CS_PIN               (8)
 #endif
 
 /* SECTION: Micro SD */
@@ -114,9 +114,9 @@ extern volatile rt_uint32_t rt_system_status;
 #endif
 
 /* SECTION: SYSTEM */
-#define EFM32_SRAM_END 				(SRAM_BASE + SRAM_SIZE)
-#define EFM32_BASE_PRI_DEFAULT 		(0x0UL << 5)
-#define EFM32_IRQ_PRI_DEFAULT 		(0x4UL << 5)
+#define EFM32_SRAM_END              (SRAM_BASE + SRAM_SIZE)
+#define EFM32_BASE_PRI_DEFAULT      (0x0UL << 5)
+#define EFM32_IRQ_PRI_DEFAULT       (0x4UL << 5)
 
 /* SECTION: CLOCK */
 #define EFM32_USING_HFXO
@@ -125,9 +125,9 @@ extern volatile rt_uint32_t rt_system_status;
  #if (defined(EFM32_G8XX_STK) || defined(EFM32_GXXX_DK))
  #define EFM32_HFXO_FREQUENCY       (32000000)
  #elif defined(EFM32GG_DK3750)
- #define EFM32_HFXO_FREQUENCY 		(48000000)
+ #define EFM32_HFXO_FREQUENCY       (48000000)
  #else
- #define EFM32_HFXO_FREQUENCY		(00000000)
+ #define EFM32_HFXO_FREQUENCY       (00000000)
  #endif
 #endif
 #if defined(EFM32_USING_LFXO)
@@ -141,8 +141,8 @@ extern volatile rt_uint32_t rt_system_status;
 #endif
 
 /* SECTION: USART */
-#define USART_RX_BUFFER_SIZE		(64)
-#define LEUART_RX_BUFFER_SIZE		(64)
+#define USART_RX_BUFFER_SIZE        (64)
+#define LEUART_RX_BUFFER_SIZE       (64)
 /* Location count (start from 0) */
 #if defined(_EFM32_GECKO_FAMILY)
 #define EFM32_USART_LOCATION_COUNT  (3)
@@ -155,14 +155,14 @@ extern volatile rt_uint32_t rt_system_status;
 #endif
 
 /* SUBSECTION: UART */
-#define UART_BAUDRATE				(115200)
+#define UART_BAUDRATE               (115200)
 
 /* SUBSECTION: SPI */
 /* Max SPI clock: HFPERCLK/2 for master, HFPERCLK/8 for slave */
-#define SPI_BAUDRATE				(4000000)
+#define SPI_BAUDRATE                (4000000)
 
 /* SECTION: I2C */
-#define IIC_RX_BUFFER_SIZE			(32)
+#define IIC_RX_BUFFER_SIZE          (32)
 #if defined(_EFM32_GECKO_FAMILY)
 #define EFM32_IIC_LOCATION_COUNT    (4)
 #elif defined(_EFM32_GIANT_FAMILY)
@@ -170,61 +170,61 @@ extern volatile rt_uint32_t rt_system_status;
 #endif
 
 /* SECTION: ADC */
-#define ADC_CALI_REF				(adcRef2V5)
-#define ADC_CALI_CH 				(adcSingleInpCh5)
-#define ADC_CONVERT_FREQUENCY 		(7000000)
+#define ADC_CALI_REF                (adcRef2V5)
+#define ADC_CALI_CH                 (adcSingleInpCh5)
+#define ADC_CONVERT_FREQUENCY       (7000000)
 
 #if (RT_CONSOLE_DEVICE == EFM_USART0)
-#define CONSOLE_DEVICE 				RT_USART0_NAME
+#define CONSOLE_DEVICE              RT_USART0_NAME
 #elif (RT_CONSOLE_DEVICE == EFM_USART1)
-#define CONSOLE_DEVICE 				RT_USART1_NAME
+#define CONSOLE_DEVICE              RT_USART1_NAME
 #elif (RT_CONSOLE_DEVICE == EFM_USART2)
-#define CONSOLE_DEVICE 				RT_USART2_NAME
+#define CONSOLE_DEVICE              RT_USART2_NAME
 #elif (RT_CONSOLE_DEVICE == EFM_UART0)
-#define CONSOLE_DEVICE 				RT_UART0_NAME
+#define CONSOLE_DEVICE              RT_UART0_NAME
 #elif (RT_CONSOLE_DEVICE == EFM_UART1)
-#define CONSOLE_DEVICE 				RT_UART1_NAME
+#define CONSOLE_DEVICE              RT_UART1_NAME
 #elif (RT_CONSOLE_DEVICE == EFM_LEUART0)
-#define CONSOLE_DEVICE 				RT_LEUART0_NAME
+#define CONSOLE_DEVICE              RT_LEUART0_NAME
 #elif (RT_CONSOLE_DEVICE == EFM_LEUART1)
-#define CONSOLE_DEVICE 				RT_LEUART1_NAME
+#define CONSOLE_DEVICE              RT_LEUART1_NAME
 #else
-#define CONSOLE_DEVICE 				"NONE"
+#define CONSOLE_DEVICE              "NONE"
 #endif
 
 
 /* The following defines should be consistent with those in diskio.h */
-#define CTRL_SYNC						0
-#define GET_SECTOR_COUNT				1
-#define GET_SECTOR_SIZE					2
-#define GET_BLOCK_SIZE					3
-#define MMC_GET_TYPE					10
-#define MMC_GET_CSD						11
-#define MMC_GET_CID						12
-#define MMC_GET_OCR						13
-#define MMC_GET_SDSTAT					14
+#define CTRL_SYNC                       0
+#define GET_SECTOR_COUNT                1
+#define GET_SECTOR_SIZE                 2
+#define GET_BLOCK_SIZE                  3
+#define MMC_GET_TYPE                    10
+#define MMC_GET_CSD                     11
+#define MMC_GET_CID                     12
+#define MMC_GET_OCR                     13
+#define MMC_GET_SDSTAT                  14
 /* The above defines should be consistent with those in diskio.h */
 
 /* I/O control options */
-#define RT_DEVICE_CTRL_SD_SYNC 			CTRL_SYNC
-#define RT_DEVICE_CTRL_SD_GET_SCOUNT 	GET_SECTOR_COUNT
-#define RT_DEVICE_CTRL_SD_GET_SSIZE		GET_SECTOR_SIZE
-#define RT_DEVICE_CTRL_SD_GET_BSIZE 	GET_BLOCK_SIZE
-#define RT_DEVICE_CTRL_SD_GET_TYPE 		MMC_GET_TYPE
-#define RT_DEVICE_CTRL_SD_GET_CSD		MMC_GET_CSD
-#define RT_DEVICE_CTRL_SD_GET_CID 		MMC_GET_CID
-#define RT_DEVICE_CTRL_SD_GET_OCR 		MMC_GET_OCR
-#define RT_DEVICE_CTRL_SD_GET_SDSTAT	MMC_GET_SDSTAT
+#define RT_DEVICE_CTRL_SD_SYNC          CTRL_SYNC
+#define RT_DEVICE_CTRL_SD_GET_SCOUNT    GET_SECTOR_COUNT
+#define RT_DEVICE_CTRL_SD_GET_SSIZE     GET_SECTOR_SIZE
+#define RT_DEVICE_CTRL_SD_GET_BSIZE     GET_BLOCK_SIZE
+#define RT_DEVICE_CTRL_SD_GET_TYPE      MMC_GET_TYPE
+#define RT_DEVICE_CTRL_SD_GET_CSD       MMC_GET_CSD
+#define RT_DEVICE_CTRL_SD_GET_CID       MMC_GET_CID
+#define RT_DEVICE_CTRL_SD_GET_OCR       MMC_GET_OCR
+#define RT_DEVICE_CTRL_SD_GET_SDSTAT    MMC_GET_SDSTAT
 
 /*! fixme: move the following define to Rtdef.h */
-#define RT_DEVICE_CTRL_USART_RBUFFER	(0xF1)		/*!< set USART/UART rx buffer */
-#define RT_DEVICE_CTRL_LEUART_RBUFFER	(0xF2)		/*!< set LEUART rx buffer */
-#define RT_DEVICE_CTRL_IIC_SETTING		(0xF3)		/*!< change IIC setting */
-#define RT_DEVICE_CTRL_TIMER_PERIOD		(0xF4)		/*!< set Timer timeout period */
-#define RT_DEVICE_CTRL_ADC_MODE			(0xF5)		/*!< change ADC mode */
-#define RT_DEVICE_CTRL_ADC_RESULT		(0xF6)		/*!< get ADC result */
-#define RT_DEVICE_CTRL_ACMP_INIT		(0xF7)		/*!< Initialize ACMP */
-#define RT_DEVICE_CTRL_ACMP_OUTPUT		(0xF8)		/*!< get ACMP output */
+#define RT_DEVICE_CTRL_USART_RBUFFER    (0xF1)      /*!< set USART/UART rx buffer */
+#define RT_DEVICE_CTRL_LEUART_RBUFFER   (0xF2)      /*!< set LEUART rx buffer */
+#define RT_DEVICE_CTRL_IIC_SETTING      (0xF3)      /*!< change IIC setting */
+#define RT_DEVICE_CTRL_TIMER_PERIOD     (0xF4)      /*!< set Timer timeout period */
+#define RT_DEVICE_CTRL_ADC_MODE         (0xF5)      /*!< change ADC mode */
+#define RT_DEVICE_CTRL_ADC_RESULT       (0xF6)      /*!< get ADC result */
+#define RT_DEVICE_CTRL_ACMP_INIT        (0xF7)      /*!< Initialize ACMP */
+#define RT_DEVICE_CTRL_ACMP_OUTPUT      (0xF8)      /*!< get ACMP output */
 
 /* Exported functions ------------------------------------------------------- */
 void rt_hw_board_init(void);
diff --git a/bsp/efm32/copy_this_file_dfs_elm.c b/bsp/efm32/copy_this_file_dfs_elm.c
deleted file mode 100644
index c726d0c355..0000000000
--- a/bsp/efm32/copy_this_file_dfs_elm.c
+++ /dev/null
@@ -1,964 +0,0 @@
-/*
- * File      : dfs_elm.c
- * This file is part of Device File System in RT-Thread RTOS
- * COPYRIGHT (C) 2008-2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2008-02-22     QiuYi        The first version.
- * 2011-10-08     Bernard      fixed the block size in statfs.
- * 2011-11-23     Bernard      fixed the rename issue.
- */
- 
-#include 
-#include "ffconf.h"
-#include "ff.h"
-
-/* ELM FatFs provide a DIR struct */
-#define HAVE_DIR_STRUCTURE
-
-#include 
-#include 
-
-#ifdef DFS_ELMFAT_INTERFACE_EFM
-#include "diskio.h"
-
-/* Disk status */
-static volatile DSTATUS diskStat[_VOLUMES];
-#endif
-static rt_device_t disk[_VOLUMES] = {0};
-
-static int elm_result_to_dfs(FRESULT result)
-{
-	int status = DFS_STATUS_OK;
-
-	switch (result)
-	{
-	case FR_OK:
-		break;
-
-	case FR_NO_FILE:
-	case FR_NO_PATH:
-	case FR_NO_FILESYSTEM:
-		status = -DFS_STATUS_ENOENT;
-		break;
-
-	case FR_INVALID_NAME:
-		status = -DFS_STATUS_EINVAL;
-		break;
-
-	case FR_EXIST:
-	case FR_INVALID_OBJECT:
-		status = -DFS_STATUS_EEXIST;
-		break;
-
-	case FR_DISK_ERR:
-	case FR_NOT_READY:
-	case FR_INT_ERR:
-		status = -DFS_STATUS_EIO;
-		break;
-
-	case FR_WRITE_PROTECTED:
-	case FR_DENIED:
-		status = -DFS_STATUS_EROFS;
-		break;
-
-	case FR_MKFS_ABORTED:
-		status = -DFS_STATUS_EINVAL;
-		break;
-
-	default:
-		status = -1;
-		break;
-	}
-
-	return status;
-}
-
-int dfs_elm_mount(struct dfs_filesystem *fs, unsigned long rwflag, const void *data)
-{
-	FATFS *fat;
-	FRESULT result;
-	rt_uint32_t index;
-
-	/* handle RT-Thread device routine */
-	for (index = 0; index < _VOLUMES; index ++)
-	{
-		if (disk[index] == RT_NULL)
-		{
-			break;
-		}
-	}
-	if (index == _VOLUMES)
-		return -DFS_STATUS_ENOSPC;
-
-	/* get device */
-	disk[index] = fs->dev_id;
-
-	fat = (FATFS *)rt_malloc(sizeof(FATFS));
-	if (fat == RT_NULL)
-	{
-		return -1;
-	}
-
-	/* mount fatfs, always 0 logic driver */
-	result = f_mount(index, fat);
-	if (result == FR_OK)
-		fs->data = fat;
-	else
-	{
-		rt_free(fat);
-		return elm_result_to_dfs(result);
-	}
-
-	return 0;
-}
-
-int dfs_elm_unmount(struct dfs_filesystem *fs)
-{
-	FATFS *fat;
-	FRESULT result;
-	rt_uint32_t index;
-
-	fat = (FATFS *)fs->data;
-
-	RT_ASSERT(fat != RT_NULL);
-
-	/* find the device index and then umount it */
-	for (index = 0; index < _VOLUMES; index ++)
-	{
-		if (disk[index] == fs->dev_id)
-		{
-			result = f_mount(index, RT_NULL);
-
-			if (result == FR_OK)
-			{
-				fs->data = RT_NULL;
-				disk[index] = RT_NULL;
-				rt_free(fat);
-				return DFS_STATUS_OK;
-			}
-		}
-	}
-
-	return -DFS_STATUS_ENOENT;
-}
-
-int dfs_elm_mkfs(const char *device_name)
-{
-	BYTE drv;
-	rt_device_t dev;
-	FRESULT result;
-
-	/* find device name */
-	for (drv = 0; drv < _VOLUMES; drv ++)
-	{
-		dev = disk[drv];
-		if (rt_strncmp(dev->parent.name, device_name, RT_NAME_MAX) == 0)
-		{
-			/* 1: no partition table */
-			/* 0: auto selection of cluster size */
-			result = f_mkfs(drv, 1, 0);
-			if (result != FR_OK)
-			{
-				rt_kprintf("format error\n");
-				return elm_result_to_dfs(result);
-			}
-
-			return DFS_STATUS_OK;
-		}
-	}
-
-	/* can't find device driver */
-	rt_kprintf("can not find device driver: %s\n", device_name);
-	return -DFS_STATUS_EIO;
-}
-
-int dfs_elm_statfs(struct dfs_filesystem *fs, struct statfs *buf)
-{
-	FATFS *f;
-	FRESULT res;
-	char driver[4];
-	DWORD fre_clust, fre_sect, tot_sect;
-
-	RT_ASSERT(fs != RT_NULL);
-	RT_ASSERT(buf != RT_NULL);
-
-	f = (FATFS *)fs->data;
-
-	rt_snprintf(driver, sizeof(driver), "%d:", f->drv);
-	res = f_getfree(driver, &fre_clust, &f);
-	if (res) 
-		return elm_result_to_dfs(res);
-
-	/* Get total sectors and free sectors */
-	tot_sect = (f->n_fatent - 2) * f->csize;
-	fre_sect = fre_clust * f->csize;
-
-	buf->f_bfree = fre_sect;
-	buf->f_blocks = tot_sect;
-#if _MAX_SS != 512
-	buf->f_bsize = f->ssize;
-#else
-    buf->f_bsize = 512;
-#endif
-
-	return 0;
-}
-
-int dfs_elm_open(struct dfs_fd *file)
-{
-	FIL *fd;
-	BYTE mode;
-	FRESULT result;
-	char *drivers_fn;
-
-#if (_VOLUMES > 1)
-	int vol;
-	extern int elm_get_vol(FATFS *fat);
-
-	/* add path for ELM FatFS driver support */
-	vol = elm_get_vol((FATFS *)file->fs->data);
-	if (vol < 0)
-		return -DFS_STATUS_ENOENT;
-	drivers_fn = rt_malloc(256);
-	if (drivers_fn == RT_NULL)
-		return -DFS_STATUS_ENOMEM;
-
-	rt_snprintf(drivers_fn, 256, "%d:%s", vol, file->path);
-#else
-	drivers_fn = file->path;
-#endif
-
-	if (file->flags & DFS_O_DIRECTORY)
-	{
-		DIR *dir;
-
-		if (file->flags & DFS_O_CREAT)
-		{
-			result = f_mkdir(drivers_fn);
-			if (result != FR_OK)
-			{
-#if _VOLUMES > 1
-				rt_free(drivers_fn);
-#endif
-				return elm_result_to_dfs(result);
-			}
-		}
-
-		/* open directory */
-		dir = (DIR *)rt_malloc(sizeof(DIR));
-		if (dir == RT_NULL)
-		{
-#if _VOLUMES > 1
-			rt_free(drivers_fn);
-#endif
-			return -DFS_STATUS_ENOMEM;
-		}
-
-		result = f_opendir(dir, drivers_fn);
-#if _VOLUMES > 1
-		rt_free(drivers_fn);
-#endif
-		if (result != FR_OK)
-		{
-			rt_free(dir);
-			return elm_result_to_dfs(result);
-		}
-
-		file->data = dir;
-		return DFS_STATUS_OK;
-	}
-	else
-	{
-		mode = FA_READ;
-
-		if (file->flags & DFS_O_WRONLY)
-			mode |= FA_WRITE;
-		if ((file->flags & DFS_O_ACCMODE) & DFS_O_RDWR)
-			mode |= FA_WRITE;
-		/* Opens the file, if it is existing. If not, a new file is created. */
-		if (file->flags & DFS_O_CREAT)
-			mode |= FA_OPEN_ALWAYS;
-		/* Creates a new file. If the file is existing, it is truncated and overwritten. */
-		if (file->flags & DFS_O_TRUNC)
-			mode |= FA_CREATE_ALWAYS;
-		/* Creates a new file. The function fails if the file is already existing. */
-		if (file->flags & DFS_O_EXCL)
-			mode |= FA_CREATE_NEW;
-
-		/* allocate a fd */
-		fd = (FIL *)rt_malloc(sizeof(FIL));
-		if (fd == RT_NULL)
-		{
-			return -DFS_STATUS_ENOMEM;
-		}
-
-		result = f_open(fd, drivers_fn, mode);
-#if _VOLUMES > 1
-		rt_free(drivers_fn);
-#endif
-		if (result == FR_OK)
-		{
-			file->pos  = fd->fptr;
-			file->size = fd->fsize;
-			file->data = fd;
-
-			if (file->flags & DFS_O_APPEND)
-			{
-				file->pos = f_lseek(fd, fd->fsize);
-			}
-		}
-		else
-		{
-			/* open failed, return */
-			rt_free(fd);
-			return elm_result_to_dfs(result);
-		}
-	}
-
-	return DFS_STATUS_OK;
-}
-
-int dfs_elm_close(struct dfs_fd *file)
-{
-	FRESULT result;
-
-	result = FR_OK;
-	if (file->type == FT_DIRECTORY)
-	{
-		DIR *dir;
-
-		dir = (DIR *)(file->data);
-		RT_ASSERT(dir != RT_NULL);
-
-		/* release memory */
-		rt_free(dir);
-	}
-	else if (file->type == FT_REGULAR)
-	{
-		FIL *fd;
-		fd = (FIL *)(file->data);
-		RT_ASSERT(fd != RT_NULL);
-
-		result = f_close(fd);
-		if (result == FR_OK)
-		{
-			/* release memory */
-			rt_free(fd);
-		}
-	}
-
-	return elm_result_to_dfs(result);
-}
-
-int dfs_elm_ioctl(struct dfs_fd *file, int cmd,	void *args)
-{
-	return -DFS_STATUS_ENOSYS;
-}
-
-int dfs_elm_read(struct dfs_fd *file, void *buf, rt_size_t len)
-{
-	FIL *fd;
-	FRESULT result;
-	UINT byte_read;
-
-	if (file->type == FT_DIRECTORY)
-	{
-		return -DFS_STATUS_EISDIR;
-	}
-
-	fd = (FIL *)(file->data);
-	RT_ASSERT(fd != RT_NULL);
-
-	result = f_read(fd, buf, len, &byte_read);
-	/* update position */
-	file->pos  = fd->fptr;
-	if (result == FR_OK)
-		return byte_read;
-
-	return elm_result_to_dfs(result);
-}
-
-int dfs_elm_write(struct dfs_fd *file, const void *buf, rt_size_t len)
-{
-	FIL *fd;
-	FRESULT result;
-	UINT byte_write;
-
-	if (file->type == FT_DIRECTORY)
-	{
-		return -DFS_STATUS_EISDIR;
-	}
-
-	fd = (FIL *)(file->data);
-	RT_ASSERT(fd != RT_NULL);
-
-	result = f_write(fd, buf, len, &byte_write);
-	/* update position and file size */
-	file->pos  = fd->fptr;
-	file->size = fd->fsize;
-	if (result == FR_OK)
-		return byte_write;
-
-	return elm_result_to_dfs(result);
-}
-
-int dfs_elm_flush(struct dfs_fd *file)
-{
-	FIL *fd;
-	FRESULT result;
-
-	fd = (FIL *)(file->data);
-	RT_ASSERT(fd != RT_NULL);
-
-	result = f_sync(fd);
-	return elm_result_to_dfs(result);
-}
-
-int dfs_elm_lseek(struct dfs_fd *file, rt_off_t offset)
-{
-	FRESULT result = FR_OK;
-	if (file->type == FT_REGULAR)
-	{
-		FIL *fd;
-
-		/* regular file type */
-		fd = (FIL *)(file->data);
-		RT_ASSERT(fd != RT_NULL);
-		
-		result = f_lseek(fd, offset);
-		if (result == FR_OK)
-		{
-			/* return current position */
-			return fd->fptr;
-		}
-	}
-	else if (file->type == FT_DIRECTORY)
-	{
-		/* which is a directory */
-		DIR *dir;
-
-		dir = (DIR *)(file->data);
-		RT_ASSERT(dir != RT_NULL);
-
-		result = f_seekdir(dir, offset / sizeof(struct dirent));
-		if (result == FR_OK)
-		{
-			/* update file position */
-			file->pos = offset;
-			return file->pos;
-		}
-	}
-
-	return elm_result_to_dfs(result);
-}
-
-int dfs_elm_getdents(struct dfs_fd *file, struct dirent *dirp, rt_uint32_t count)
-{
-	DIR *dir;
-	FILINFO fno;
-	FRESULT result;
-	rt_uint32_t index;
-	struct dirent *d;
-
-	dir = (DIR *)(file->data);
-	RT_ASSERT(dir != RT_NULL);
-
-	/* make integer count */
-	count = (count / sizeof(struct dirent)) * sizeof(struct dirent);
-	if (count == 0)
-		return -DFS_STATUS_EINVAL;
-
-#if _USE_LFN
-	/* allocate long file name */
-	fno.lfname = rt_malloc(256);
-	fno.lfsize = 256;
-#endif
-
-	index = 0;
-	while (1)
-	{
-		char *fn;
-
-		d = dirp + index;
-
-		result = f_readdir(dir, &fno);
-		if (result != FR_OK || fno.fname[0] == 0)
-			break;
-
-#if _USE_LFN
-		fn = *fno.lfname? fno.lfname : fno.fname;
-#else
-		fn = fno.fname;
-#endif
-
-		d->d_type = DFS_DT_UNKNOWN;
-		if (fno.fattrib & AM_DIR)
-			d->d_type = DFS_DT_DIR;
-		else
-			d->d_type = DFS_DT_REG;
-
-		d->d_namlen = rt_strlen(fn);
-		d->d_reclen = (rt_uint16_t)sizeof(struct dirent);
-		rt_strncpy(d->d_name, fn, rt_strlen(fn) + 1);
-
-		index ++;
-		if (index * sizeof(struct dirent) >= count)
-			break;
-	}
-
-#if _USE_LFN
-	rt_free(fno.lfname);
-#endif
-
-	if (index == 0)
-		return elm_result_to_dfs(result);
-
-	file->pos += index * sizeof(struct dirent);
-
-	return index * sizeof(struct dirent);
-}
-
-int dfs_elm_unlink(struct dfs_filesystem *fs, const char *path)
-{
-	FRESULT result;
-
-#if _VOLUMES > 1
-	int vol;
-	char *drivers_fn;
-	extern int elm_get_vol(FATFS *fat);
-
-	/* add path for ELM FatFS driver support */
-	vol = elm_get_vol((FATFS *)fs->data);
-	if (vol < 0)
-		return -DFS_STATUS_ENOENT;
-	drivers_fn = rt_malloc(256);
-	if (drivers_fn == RT_NULL)
-		return -DFS_STATUS_ENOMEM;
-
-	rt_snprintf(drivers_fn, 256, "%d:%s", vol, path);
-#else
-	const char *drivers_fn;
-	drivers_fn = path;
-#endif
-
-	result = f_unlink(drivers_fn);
-#if _VOLUMES > 1
-	rt_free(drivers_fn);
-#endif
-	return elm_result_to_dfs(result);
-}
-
-int dfs_elm_rename(struct dfs_filesystem *fs, const char *oldpath, const char *newpath)
-{
-	FRESULT result;
-
-#if _VOLUMES > 1
-	char *drivers_oldfn;
-	const char *drivers_newfn;
-	int vol;
-	extern int elm_get_vol(FATFS *fat);
-
-	/* add path for ELM FatFS driver support */
-	vol = elm_get_vol((FATFS *)fs->data);
-	if (vol < 0)
-		return -DFS_STATUS_ENOENT;
-
-	drivers_oldfn = rt_malloc(256);
-	if (drivers_oldfn == RT_NULL)
-		return -DFS_STATUS_ENOMEM;
-	drivers_newfn = newpath;
-
-	rt_snprintf(drivers_oldfn, 256, "%d:%s", vol, oldpath);
-#else
-	const char *drivers_oldfn, *drivers_newfn;
-
-	drivers_oldfn = oldpath;
-	drivers_newfn = newpath;
-#endif
-
-	result = f_rename(drivers_oldfn, drivers_newfn);
-#if _VOLUMES > 1
-	rt_free(drivers_oldfn);
-#endif
-	return elm_result_to_dfs(result);
-}
-
-int dfs_elm_stat(struct dfs_filesystem *fs, const char *path, struct stat *st)
-{
-	FILINFO file_info;
-	FRESULT result;
-
-
-#if _VOLUMES > 1
-	int vol;
-	char *drivers_fn;
-	extern int elm_get_vol(FATFS *fat);
-
-	/* add path for ELM FatFS driver support */
-	vol = elm_get_vol((FATFS *)fs->data);
-	if (vol < 0)
-		return -DFS_STATUS_ENOENT;
-	drivers_fn = rt_malloc(256);
-	if (drivers_fn == RT_NULL)
-		return -DFS_STATUS_ENOMEM;
-
-	rt_snprintf(drivers_fn, 256, "%d:%s", vol, path);
-#else
-	const char *drivers_fn;
-	drivers_fn = path;
-#endif
-
-#if _USE_LFN
-	/* allocate long file name */
-	file_info.lfname = rt_malloc(256);
-	file_info.lfsize = 256;
-#endif
-
-	result = f_stat(drivers_fn, &file_info);
-#if _VOLUMES > 1
-	rt_free(drivers_fn);
-#endif
-	if (result == FR_OK)
-	{
-		/* convert to dfs stat structure */
-		st->st_dev = 0;
-
-		st->st_mode = DFS_S_IFREG | DFS_S_IRUSR | DFS_S_IRGRP | DFS_S_IROTH |
-		DFS_S_IWUSR | DFS_S_IWGRP | DFS_S_IWOTH;
-		if (file_info.fattrib & AM_DIR)
-		{
-			st->st_mode &= ~DFS_S_IFREG;
-			st->st_mode |= DFS_S_IFDIR | DFS_S_IXUSR | DFS_S_IXGRP | DFS_S_IXOTH;
-		}
-		if (file_info.fattrib & AM_RDO)
-			st->st_mode &= ~(DFS_S_IWUSR | DFS_S_IWGRP | DFS_S_IWOTH);
-
-		st->st_size  = file_info.fsize;
-		st->st_mtime = file_info.ftime;
-	}
-
-#if _USE_LFN
-	rt_free(file_info.lfname);
-#endif
-
-	return elm_result_to_dfs(result);
-}
-
-static const struct dfs_filesystem_operation dfs_elm =
-{
-	"elm",
-	dfs_elm_mount,
-	dfs_elm_unmount,
-	dfs_elm_mkfs,
-	dfs_elm_statfs,
-
-	dfs_elm_open,
-	dfs_elm_close,
-	dfs_elm_ioctl,
-	dfs_elm_read,
-	dfs_elm_write,
-	dfs_elm_flush,
-	dfs_elm_lseek,
-	dfs_elm_getdents,
-	dfs_elm_unlink,
-	dfs_elm_stat,
-	dfs_elm_rename,
-};
-
-int elm_init(void)
-{
-#ifdef DFS_ELMFAT_INTERFACE_EFM
-	int i;
-
-	for (i = 0; i < _VOLUMES; i++)
-	{
-		diskStat[i] = STA_NOINIT;
-	}
-#endif
-
-    /* register fatfs file system */
-    dfs_register(&dfs_elm);
-
-	return 0;
-}
-
-/*
- * RT-Thread Device Interface for ELM FatFs
- */
-#ifdef DFS_ELMFAT_INTERFACE_EFM
-/*-----------------------------------------------------------------------*/
-/* Initialize Disk Drive                                                 */
-/*-----------------------------------------------------------------------*/
-DSTATUS disk_initialize (
-	BYTE drv				/* Physical drive nmuber */
-	)
-{
-	rt_device_t device = disk[drv];
-
-	if (!device)
-	{
-		return RES_ERROR;
-	}
-	if (diskStat[drv] & STA_NODISK) 
-	{
-		/* No card in the socket */
-		return diskStat[drv];
-	}
-
-	/* Initialize hardware: the actual operation is performed in dfs_mount() */
-	diskStat[drv] &= ~STA_NOINIT;
-
-	return diskStat[drv];
-}
-
-/*-----------------------------------------------------------------------*/
-/* Get Disk Status                                                       */
-/*-----------------------------------------------------------------------*/
-DSTATUS disk_status (
-	BYTE drv				/* Physical drive nmuber */
-	)
-{
-	return diskStat[drv];
-}
-
-/*-----------------------------------------------------------------------*/
-/* Read Sector(s)                                                        */
-/*-----------------------------------------------------------------------*/
-DRESULT disk_read (
-	BYTE drv,				/* Physical drive nmuber */
-	BYTE *buff,				/* Pointer to the data buffer to store read data */
-	DWORD sector,			/* Start sector number (LBA) */
-	BYTE count				/* Sector count (1..255) */
-	)
-{
-	rt_device_t device = disk[drv];
-
-	if (!device)
-	{
-		return RES_ERROR;
-	}
-	if (!count)
-	{
-		return RES_PARERR;
-	}
-	if (diskStat[drv] & STA_NOINIT)
-	{
-		return RES_NOTRDY;
-	}
-
-	if (rt_device_read(device, sector, buff, count) != count)
-	{
-		return RES_ERROR;
-	}
-	else
-	{
-		return RES_OK;
-	}
-}
-
-/*-----------------------------------------------------------------------*/
-/* Write Sector(s)                                                       */
-/*-----------------------------------------------------------------------*/
-#if _READONLY == 0
-DRESULT disk_write (
-	BYTE drv,				/* Physical drive nmuber */
-	const BYTE *buff,		/* Pointer to the data to be written */
-	DWORD sector,			/* Start sector number (LBA) */
-	BYTE count				/* Sector count (1..255) */
-	)
-{
-	rt_device_t device = disk[drv];
-
-	if (!device)
-	{
-		return RES_ERROR;
-	}
-	if (!count)
-	{
-		return RES_PARERR;
-	}
-	if (diskStat[drv] & STA_NOINIT)
-	{
-		return RES_NOTRDY;
-	}
-	if (diskStat[drv] & STA_PROTECT)
-	{
-		return RES_WRPRT;
-	}
-
-	if (rt_device_write(device, sector, buff, count) != count)
-	{
-		return RES_ERROR;
-	}
-	else
-	{
-		return RES_OK;
-	}
-}
-#endif /* _READONLY */
-
-/*-----------------------------------------------------------------------*/
-/* Miscellaneous Functions                                               */
-/*-----------------------------------------------------------------------*/
-DRESULT disk_ioctl (
-	BYTE drv,		/* Physical drive nmuber */
-	BYTE ctrl,		/* Control code */
-	void *buff		/* Buffer to send/receive data block */
-)
-{
-	rt_device_t device = disk[drv];
-
-	if (!device)
-	{
-		return RES_ERROR;
-	}
-	if (diskStat[drv] & STA_NOINIT) 
-	{
-		return RES_NOTRDY;
-	}
-
-	if (rt_device_control(device, ctrl, buff) != RT_EOK)
-	{
-		return RES_ERROR;
-	}
-	else
-	{
-		return RES_OK;
-	}
-}
-#else
-#include "diskio.h"
-
-/* Inidialize a Drive */
-DSTATUS disk_initialize(BYTE drv)
-{
-	return 0;
-}
-
-/* Return Disk Status */
-DSTATUS disk_status(BYTE drv)
-{
-	return 0;
-}
-
-/* Read Sector(s) */
-DRESULT disk_read(BYTE drv, BYTE *buff, DWORD sector, BYTE count)
-{
-	rt_size_t result;
-	rt_device_t device = disk[drv];
-
-	result = rt_device_read(device, sector, buff, count);
-	if (result == count)
-	{
-		return RES_OK;
-	}
-
-	return RES_ERROR;
-}
-
-/* Write Sector(s) */
-DRESULT disk_write(BYTE drv, const BYTE *buff, DWORD sector, BYTE count)
-{
-	rt_size_t result;
-	rt_device_t device = disk[drv];
-
-	result = rt_device_write(device, sector, buff, count);
-	if (result == count)
-	{
-		return RES_OK;
-	}
-
-	return RES_ERROR;
-}
-
-/* Miscellaneous Functions */
-DRESULT disk_ioctl(BYTE drv, BYTE ctrl, void *buff)
-{
-	rt_device_t device = disk[drv];
-
-	if (device == RT_NULL)
-		return RES_ERROR;
-
-	if (ctrl == GET_SECTOR_COUNT)
-	{
-		struct rt_device_blk_geometry geometry;
-
-		rt_memset(&geometry, 0, sizeof(geometry));
-		rt_device_control(device, RT_DEVICE_CTRL_BLK_GETGEOME, &geometry);
-
-		*(DWORD *)buff = geometry.sector_count;
-		if (geometry.sector_count == 0)
-			return RES_ERROR;
-	}
-	else if (ctrl == GET_SECTOR_SIZE)
-	{
-		struct rt_device_blk_geometry geometry;
-
-		rt_memset(&geometry, 0, sizeof(geometry));
-		rt_device_control(device, RT_DEVICE_CTRL_BLK_GETGEOME, &geometry);
-
-		*(WORD *)buff = geometry.bytes_per_sector;
-	}
-	else if (ctrl == GET_BLOCK_SIZE) /* Get erase block size in unit of sectors (DWORD) */
-	{
-		struct rt_device_blk_geometry geometry;
-
-		rt_memset(&geometry, 0, sizeof(geometry));
-		rt_device_control(device, RT_DEVICE_CTRL_BLK_GETGEOME, &geometry);
-
-		*(DWORD *)buff = geometry.block_size/geometry.bytes_per_sector;
-	}
-
-	return RES_OK;
-}
-#endif
-
-rt_time_t get_fattime(void)
-{
-	return 0;
-}
-
-#if _FS_REENTRANT
-int ff_cre_syncobj(BYTE drv, _SYNC_t *m)
-{
-    char name[8];
-    rt_mutex_t mutex;
-
-    rt_snprintf(name, sizeof(name), "fat%d", drv);
-    mutex = rt_mutex_create(name, RT_IPC_FLAG_FIFO);
-    if (mutex != RT_NULL)
-    {
-        *m = mutex;
-        return RT_TRUE;
-    }
-
-    return RT_FALSE;
-}
-
-int ff_del_syncobj(_SYNC_t m)
-{
-    rt_mutex_delete(m);
-
-    return RT_TRUE;
-}
-
-int ff_req_grant(_SYNC_t m)
-{
-    if (rt_mutex_take(m, _FS_TIMEOUT) == RT_EOK)
-		return RT_TRUE;
-
-    return RT_FALSE;
-}
-
-void ff_rel_grant(_SYNC_t m)
-{
-	rt_mutex_release(m);
-}
-
-#endif
diff --git a/bsp/efm32/copy_this_file_shell.c b/bsp/efm32/copy_this_file_shell.c
deleted file mode 100644
index 45ce3cb45a..0000000000
--- a/bsp/efm32/copy_this_file_shell.c
+++ /dev/null
@@ -1,521 +0,0 @@
-/*
- * File      : shell.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2006-04-30     Bernard      the first verion for FinSH
- * 2006-05-08     Bernard      change finsh thread stack to 2048
- * 2006-06-03     Bernard      add support for skyeye
- * 2006-09-24     Bernard      remove the code related with hardware
- * 2010-01-18     Bernard      fix down then up key bug.
- * 2010-03-19     Bernard      fix backspace issue and fix device read in shell.
- * 2010-04-01     Bernard      add prompt output when start and remove the empty history
- * 2011-02-23     Bernard      fix variable section end issue of finsh shell
- *                             initialization when use GNU GCC compiler.
- */
-
-#include 
-#include 
-
-#include "finsh.h"
-#include "shell.h"
-
-/* finsh thread */
-static struct rt_thread finsh_thread;
-ALIGN(RT_ALIGN_SIZE)
-static char finsh_thread_stack[FINSH_THREAD_STACK_SIZE];
-struct finsh_shell* shell;
-
-#if !defined (RT_USING_NEWLIB) && !defined (RT_USING_MINILIBC)
-int strcmp (const char *s1, const char *s2)
-{
-	while (*s1 && *s1 == *s2) s1++, s2++;
-
-	return (*s1 - *s2);
-}
-
-#ifdef RT_USING_HEAP
-char *strdup(const char *s)
-{
-	size_t len = strlen(s) + 1;
-	char *tmp = (char *)rt_malloc(len);
-
-	if(!tmp) return NULL;
-
-	rt_memcpy(tmp, s, len);
-	return tmp;
-}
-#endif
-
-#if !defined(__CC_ARM) && !defined(__IAR_SYSTEMS_ICC__)
-int isalpha( int ch )
-{
-	return (unsigned int)((ch | 0x20) - 'a') < 26u;
-}
-
-int atoi(const char* s)
-{
-	long int v=0;
-	int sign=1;
-	while ( *s == ' '  ||  (unsigned int)(*s - 9) < 5u) s++;
-
-	switch (*s)
-	{
-	case '-': sign=-1;
-	case '+': ++s;
-	}
-
-	while ((unsigned int) (*s - '0') < 10u)
-	{
-		v=v*10+*s-'0'; ++s;
-	}
-
-	return sign==-1?-v:v;
-}
-
-int isprint(unsigned char ch)
-{
-    return (unsigned int)(ch - ' ') < 127u - ' ';
-}
-#endif
-#endif
-
-#if defined(RT_USING_DFS) && defined(DFS_USING_WORKDIR)
-#include 
-const char* finsh_get_prompt(void)
-{
-	#define _PROMPT "finsh "
-	static char finsh_prompt[RT_CONSOLEBUF_SIZE + 1] = {_PROMPT};
-	
-	/* get current working directory */
-	getcwd(&finsh_prompt[6], RT_CONSOLEBUF_SIZE - 8);
-	strcat(finsh_prompt, ">");
-
-	return finsh_prompt;
-}
-#endif
-
-static rt_err_t finsh_rx_ind(rt_device_t dev, rt_size_t size)
-{
-	RT_ASSERT(shell != RT_NULL);
-
-	/* release semaphore to let finsh thread rx data */
-	rt_sem_release(&shell->rx_sem);
-
-	return RT_EOK;
-}
-
-/**
- * @ingroup finsh
- *
- * This function sets the input device of finsh shell.
- *
- * @param device_name the name of new input device.
- */
-void finsh_set_device(const char* device_name)
-{
-	rt_device_t dev = RT_NULL;
-
-	RT_ASSERT(shell != RT_NULL);
-	dev = rt_device_find(device_name);
-	if (dev != RT_NULL && rt_device_open(dev, RT_DEVICE_OFLAG_RDWR) == RT_EOK)
-	{
-		if (shell->device != RT_NULL)
-		{
-			/* close old finsh device */
-			rt_device_close(shell->device);
-		}
-
-		shell->device = dev;
-		rt_device_set_rx_indicate(dev, finsh_rx_ind);
-	}
-	else
-	{
-		rt_kprintf("finsh: can not find device:%s\n", device_name);
-	}
-}
-
-/**
- * @ingroup finsh
- *
- * This function returns current finsh shell input device.
- *
- * @return the finsh shell input device name is returned.
- */
-const char* finsh_get_device()
-{
-	RT_ASSERT(shell != RT_NULL);
-	return shell->device->parent.name;
-}
-
-/**
- * @ingroup finsh
- *
- * This function set the echo mode of finsh shell.
- *
- * FINSH_OPTION_ECHO=0x01 is echo mode, other values are none-echo mode.
- *
- * @param echo the echo mode
- */
-void finsh_set_echo(rt_uint32_t echo)
-{
-	RT_ASSERT(shell != RT_NULL);
-	shell->echo_mode = echo;
-}
-
-/**
- * @ingroup finsh
- *
- * This function gets the echo mode of finsh shell.
- *
- * @return the echo mode
- */
-rt_uint32_t finsh_get_echo()
-{
-	RT_ASSERT(shell != RT_NULL);
-
-	return shell->echo_mode;
-}
-
-void finsh_auto_complete(char* prefix)
-{
-	extern void list_prefix(char* prefix);
-
-	rt_kprintf("\n");
-	list_prefix(prefix);
-	rt_kprintf("%s%s", FINSH_PROMPT, prefix);
-}
-
-void finsh_run_line(struct finsh_parser* parser, const char *line)
-{
-	const char* err_str;
-
-	rt_kprintf("\n");
-	finsh_parser_run(parser, (unsigned char*)line);
-
-	/* compile node root */
-	if (finsh_errno() == 0)
-	{
-		finsh_compiler_run(parser->root);
-	}
-	else
-	{
-		err_str = finsh_error_string(finsh_errno());
-		rt_kprintf("%s\n", err_str);
-	}
-
-	/* run virtual machine */
-	if (finsh_errno() == 0)
-	{
-		char ch;
-		finsh_vm_run();
-
-		ch = (unsigned char)finsh_stack_bottom();
-		if (ch > 0x20 && ch < 0x7e)
-		{
-			rt_kprintf("\t'%c', %d, 0x%08x\n",
-				(unsigned char)finsh_stack_bottom(),
-				(unsigned int)finsh_stack_bottom(),
-				(unsigned int)finsh_stack_bottom());
-		}
-		else
-		{
-			rt_kprintf("\t%d, 0x%08x\n",
-				(unsigned int)finsh_stack_bottom(),
-				(unsigned int)finsh_stack_bottom());
-		}
-	}
-
-    finsh_flush(parser);
-}
-
-#ifdef FINSH_USING_HISTORY
-rt_bool_t finsh_handle_history(struct finsh_shell* shell, char ch)
-{
-	/*
-	 * handle up and down key
-	 * up key  : 0x1b 0x5b 0x41
-	 * down key: 0x1b 0x5b 0x42
-	 */
-	if (ch == 0x1b)
-	{
-		shell->stat = WAIT_SPEC_KEY;
-		return RT_TRUE;
-	}
-
-	if ((shell->stat == WAIT_SPEC_KEY))
-	{
-		if (ch == 0x5b)
-		{
-			shell->stat = WAIT_FUNC_KEY;
-			return RT_TRUE;
-		}
-
-		shell->stat = WAIT_NORMAL;
-		return RT_FALSE;
-	}
-
-	if (shell->stat == WAIT_FUNC_KEY)
-	{
-		shell->stat = WAIT_NORMAL;
-
-		if (ch == 0x41) /* up key */
-		{
-			/* prev history */
-			if (shell->current_history > 0)shell->current_history --;
-			else
-			{
-				shell->current_history = 0;
-				return RT_TRUE;
-			}
-
-			/* copy the history command */
-			memcpy(shell->line, &shell->cmd_history[shell->current_history][0],
-				FINSH_CMD_SIZE);
-			shell->line_position = strlen(shell->line);
-			shell->use_history = 1;
-		}
-		else if (ch == 0x42) /* down key */
-		{
-			/* next history */
-			if (shell->current_history < shell->history_count - 1)
-				shell->current_history ++;
-			else
-			{
-				/* set to the end of history */
-				if (shell->history_count != 0)
-				{
-					shell->current_history = shell->history_count - 1;
-				}
-				else return RT_TRUE;
-			}
-
-			memcpy(shell->line, &shell->cmd_history[shell->current_history][0],
-				FINSH_CMD_SIZE);
-			shell->line_position = strlen(shell->line);
-			shell->use_history = 1;
-		}
-
-		if (shell->use_history)
-		{
-			rt_kprintf("\033[2K\r");
-			rt_kprintf("%s%s", FINSH_PROMPT, shell->line);
-			return RT_TRUE;;
-		}
-	}
-
-	return RT_FALSE;
-}
-
-void finsh_push_history(struct finsh_shell* shell)
-{
-	if ((shell->use_history == 0) && (shell->line_position != 0))
-	{
-		/* push history */
-		if (shell->history_count >= FINSH_HISTORY_LINES)
-		{
-			/* move history */
-			int index;
-			for (index = 0; index < FINSH_HISTORY_LINES - 1; index ++)
-			{
-				memcpy(&shell->cmd_history[index][0],
-					&shell->cmd_history[index + 1][0], FINSH_CMD_SIZE);
-			}
-			memset(&shell->cmd_history[index][0], 0, FINSH_CMD_SIZE);
-			memcpy(&shell->cmd_history[index][0], shell->line, shell->line_position);
-
-			/* it's the maximum history */
-			shell->history_count = FINSH_HISTORY_LINES;
-		}
-		else
-		{
-			memset(&shell->cmd_history[shell->history_count][0], 0, FINSH_CMD_SIZE);
-			memcpy(&shell->cmd_history[shell->history_count][0], shell->line, shell->line_position);
-
-			/* increase count and set current history position */
-			shell->history_count ++;
-		}
-	}
-	shell->current_history = shell->history_count;
-}
-#endif
-
-#ifndef RT_USING_HEAP
-struct finsh_shell _shell;
-#endif
-void finsh_thread_entry(void* parameter)
-{
-    char ch;
-
-	/* test: for efm32 low power mode */
-    emu_all_disable();
-
-	/* normal is echo mode */
-	shell->echo_mode = 1;
-
-    finsh_init(&shell->parser);
-	rt_kprintf(FINSH_PROMPT);
-
-	while (1)
-	{
-		/* test: for efm32 low power mode */
-        emu_em2_enable();
-
-		/* wait receive */
-		if (rt_sem_take(&shell->rx_sem, RT_WAITING_FOREVER) != RT_EOK) continue;
-
-	 	/* test: for efm32 low power mode */
-       emu_em2_disable();
-
-		/* read one character from device */
-		while (rt_device_read(shell->device, 0, &ch, 1) == 1)
-		{
-			/* handle history key */
-			#ifdef FINSH_USING_HISTORY
-			if (finsh_handle_history(shell, ch) == RT_TRUE) continue;
-			#endif
-
-			/* handle CR key */
-			if (ch == '\r')
-			{
-				char next;
-
-				if (rt_device_read(shell->device, 0, &next, 1) == 1)
-					ch = next;
-				else ch = '\r';
-			}
-			/* handle tab key */
-			else if (ch == '\t')
-			{
-				/* auto complete */
-				finsh_auto_complete(&shell->line[0]);
-				/* re-calculate position */
-				shell->line_position = strlen(shell->line);
-				continue;
-			}
-			/* handle backspace key */
-			else if (ch == 0x7f || ch == 0x08)
-			{
-				if (shell->line_position != 0)
-				{
-					rt_kprintf("%c %c", ch, ch);
-				}
-				if (shell->line_position <= 0) shell->line_position = 0;
-				else shell->line_position --;
-				shell->line[shell->line_position] = 0;
-				continue;
-			}
-
-			/* handle end of line, break */
-			if (ch == '\r' || ch == '\n')
-			{
-				/* change to ';' and break */
-				shell->line[shell->line_position] = ';';
-
-				#ifdef FINSH_USING_HISTORY
-				finsh_push_history(shell);
-				#endif
-
-				if (shell->line_position != 0) finsh_run_line(&shell->parser, shell->line);
-				else rt_kprintf("\n");
-
-				rt_kprintf(FINSH_PROMPT);
-				memset(shell->line, 0, sizeof(shell->line));
-				shell->line_position = 0;
-
-				break;
-			}
-
-			/* it's a large line, discard it */
-			if (shell->line_position >= FINSH_CMD_SIZE) shell->line_position = 0;
-
-			/* normal character */
-			shell->line[shell->line_position] = ch; ch = 0;
-			if (shell->echo_mode) rt_kprintf("%c", shell->line[shell->line_position]);
-			shell->line_position ++;
-			shell->use_history = 0; /* it's a new command */
-		} /* end of device read */
-	}
-}
-
-void finsh_system_function_init(const void* begin, const void* end)
-{
-	_syscall_table_begin = (struct finsh_syscall*) begin;
-	_syscall_table_end = (struct finsh_syscall*) end;
-}
-
-void finsh_system_var_init(const void* begin, const void* end)
-{
-	_sysvar_table_begin = (struct finsh_sysvar*) begin;
-	_sysvar_table_end = (struct finsh_sysvar*) end;
-}
-
-#if defined(__ICCARM__)               /* for IAR compiler */
-  #ifdef FINSH_USING_SYMTAB
-    #pragma section="FSymTab"
-    #pragma section="VSymTab"
-  #endif
-#endif
-
-/*
- * @ingroup finsh
- *
- * This function will initialize finsh shell
- */
-int finsh_system_init(void)
-{
-	rt_err_t result;
-
-#ifdef FINSH_USING_SYMTAB
-#ifdef __CC_ARM                 /* ARM C Compiler */
-    extern const int FSymTab$$Base;
-    extern const int FSymTab$$Limit;
-    extern const int VSymTab$$Base;
-    extern const int VSymTab$$Limit;
-	finsh_system_function_init(&FSymTab$$Base, &FSymTab$$Limit);
-	finsh_system_var_init(&VSymTab$$Base, &VSymTab$$Limit);
-#elif defined (__ICCARM__)      /* for IAR Compiler */
-    finsh_system_function_init(__section_begin("FSymTab"),
-                               __section_end("FSymTab"));
-    finsh_system_var_init(__section_begin("VSymTab"),
-                          __section_end("VSymTab"));
-#elif defined (__GNUC__)        /* GNU GCC Compiler */
-	extern const int __fsymtab_start;
-	extern const int __fsymtab_end;
-	extern const int __vsymtab_start;
-	extern const int __vsymtab_end;
-	finsh_system_function_init(&__fsymtab_start, &__fsymtab_end);
-	finsh_system_var_init(&__vsymtab_start, &__vsymtab_end);
-#endif
-#endif
-
-	/* create or set shell structure */
-#ifdef RT_USING_HEAP
-	shell = (struct finsh_shell*)rt_malloc(sizeof(struct finsh_shell));
-#else
-	shell = &_shell;
-#endif
-	if (shell == RT_NULL)
-	{
-		rt_kprintf("no memory for shell\n");
-		return;
-	}
-	
-	memset(shell, 0, sizeof(struct finsh_shell));
-
-	rt_sem_init(&(shell->rx_sem), "shrx", 0, 0);
-	result = rt_thread_init(&finsh_thread,
-		"tshell",
-		finsh_thread_entry, RT_NULL,
-		&finsh_thread_stack[0], sizeof(finsh_thread_stack),
-		FINSH_THREAD_PRIORITY, 10);
-
-	if (result == RT_EOK)
-		rt_thread_startup(&finsh_thread);
-}
diff --git a/bsp/efm32/dev_accel.c b/bsp/efm32/dev_accel.c
index fb2c05174b..07fcc25ded 100644
--- a/bsp/efm32/dev_accel.c
+++ b/bsp/efm32/dev_accel.c
@@ -1,8 +1,8 @@
 /***************************************************************************//**
- * @file 	dev_accel.c
- * @brief 	Accelerometer driver of RT-Thread RTOS for EFM32
+ * @file    dev_accel.c
+ * @brief   Accelerometer driver of RT-Thread RTOS for EFM32
  *  COPYRIGHT (C) 2012, RT-Thread Development Team
- * @author 	onelife
+ * @author  onelife
  * @version 1.0
  *******************************************************************************
  * @section License
@@ -10,10 +10,10 @@
  * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
  *******************************************************************************
  * @section Change Logs
- * Date			Author		Notes
- * 2011-07-13	onelife		Initial creation for using EFM32 ADC module to
+ * Date         Author      Notes
+ * 2011-07-13   onelife     Initial creation for using EFM32 ADC module to
  *  interface the Freescale MMA7361L
- * 2011-08-02	onelife		Add digital interface support of using EFM32 IIC
+ * 2011-08-02   onelife     Add digital interface support of using EFM32 IIC
  *  module for the Freescale MMA7455L
  ******************************************************************************/
 
@@ -38,23 +38,23 @@
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
 #ifdef EFM32_ACCEL_DEBUG
-#define accel_debug(format,args...) 		rt_kprintf(format, ##args)
+#define accel_debug(format,args...)         rt_kprintf(format, ##args)
 #else
 #define accel_debug(format,args...)
 #endif
 
 /* Private constants ---------------------------------------------------------*/
-static rt_device_t 						accel;
+static rt_device_t                      accel;
 #if (EFM32_USING_ACCEL == EFM32_INTERFACE_ADC)
-static struct efm32_adc_control_t 		control = \
-	{ADC_MODE_SCAN, {3, ACCEL_USING_DMA}, {}};
-static struct efm32_accel_result_t 		accelOffset = {0};
+static struct efm32_adc_control_t       control = \
+    {ADC_MODE_SCAN, {3, ACCEL_USING_DMA}, {}};
+static struct efm32_accel_result_t      accelOffset = {0};
 #elif (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC)
-static const struct efm32_iic_control_t	control = \
-	{IIC_STATE_MASTER, 0x0000};
+static const struct efm32_iic_control_t control = \
+    {IIC_STATE_MASTER, 0x0000};
 #endif
-static rt_bool_t 						accelInTime = true;
-static rt_uint32_t 						accelConfig = 0;
+static rt_bool_t                        accelInTime = true;
+static rt_uint32_t                      accelConfig = 0;
 
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
@@ -68,99 +68,99 @@ static rt_uint32_t 						accelConfig = 0;
  * @note
  *
  * @param[out] data
- *	Pointer to output buffer
+ *  Pointer to output buffer
  *
  * @param[in] lowResolution
- *	Resolution selection
+ *  Resolution selection
  *
  * @return
- *	 Error code
+ *   Error code
  ******************************************************************************/
 rt_err_t efm_accel_get_data(struct efm32_accel_result_t *data,
-	rt_bool_t lowResolution)
+    rt_bool_t lowResolution)
 {
-	RT_ASSERT(accel != RT_NULL);
+    RT_ASSERT(accel != RT_NULL);
 
-	rt_err_t ret;
+    rt_err_t ret;
 
-	if (data == RT_NULL)
-	{
-		return -RT_ERROR;
-	}
+    if (data == RT_NULL)
+    {
+        return -RT_ERROR;
+    }
 
-	ret = RT_EOK;
-	do
-	{
-		/* --------- ADC interface --------- */
+    ret = RT_EOK;
+    do
+    {
+        /* --------- ADC interface --------- */
 #if (EFM32_USING_ACCEL == EFM32_INTERFACE_ADC)
-		struct efm32_adc_result_t result;
+        struct efm32_adc_result_t result;
 
-		result.mode = control.mode;
-		result.buffer = (void *)data;
-		if ((ret = accel->control(accel, RT_DEVICE_CTRL_RESUME,
-			(void *)&result)) != RT_EOK)
-		{
-			break;
-		}
-		if ((ret = accel->control(accel, RT_DEVICE_CTRL_ADC_RESULT, \
-			(void *)&result)) != RT_EOK)
-		{
-			break;
-		}
+        result.mode = control.mode;
+        result.buffer = (void *)data;
+        if ((ret = accel->control(accel, RT_DEVICE_CTRL_RESUME,
+            (void *)&result)) != RT_EOK)
+        {
+            break;
+        }
+        if ((ret = accel->control(accel, RT_DEVICE_CTRL_ADC_RESULT, \
+            (void *)&result)) != RT_EOK)
+        {
+            break;
+        }
 
-		data->x += accelOffset.x - 0x800;
-		data->y += accelOffset.y - 0x800;
-		data->z += accelOffset.z - 0x800;
-		if (lowResolution)
-		{
-			data->x >>= 4;
-			data->y >>= 4;
-			data->z >>= 4;
-		}
+        data->x += accelOffset.x - 0x800;
+        data->y += accelOffset.y - 0x800;
+        data->z += accelOffset.z - 0x800;
+        if (lowResolution)
+        {
+            data->x >>= 4;
+            data->y >>= 4;
+            data->z >>= 4;
+        }
 
-		/* --------- IIC interface --------- */
+        /* --------- IIC interface --------- */
 #elif (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC)
-		if (lowResolution || \
-			((accelConfig & ACCEL_MASK_RANGE) != MCTL_RANGE_8G))
-		{
-			rt_int8_t buf[3];
+        if (lowResolution || \
+            ((accelConfig & ACCEL_MASK_RANGE) != MCTL_RANGE_8G))
+        {
+            rt_int8_t buf[3];
 
-			buf[0] = XOUT8;
-			if (accel->read(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, \
-				sizeof(buf)) == 0)
-			{
-				ret = -RT_ERROR;
-				break;
-			}
-			data->x = buf[0];
-			data->y = buf[1];
-			data->z = buf[2];
-		}
-		else
-		{
-			rt_uint8_t buf[6];
-			rt_uint16_t *temp = (rt_uint16_t *)&buf;
+            buf[0] = XOUT8;
+            if (accel->read(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, \
+                sizeof(buf)) == 0)
+            {
+                ret = -RT_ERROR;
+                break;
+            }
+            data->x = buf[0];
+            data->y = buf[1];
+            data->z = buf[2];
+        }
+        else
+        {
+            rt_uint8_t buf[6];
+            rt_uint16_t *temp = (rt_uint16_t *)&buf;
 
-			buf[0] = XOUTL;
-			if (accel->read(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, \
-				sizeof(buf)) == 0)
-			{
-				ret = -RT_ERROR;
-				break;
-			}
-			data->x = (*temp & 0x200) ? ((rt_uint32_t)*temp | ~0x3FF) : \
-				((rt_uint32_t)*temp & 0x3FF);
-			data->y = (*++temp & 0x200) ? ((rt_uint32_t)*temp | ~0x3FF) : \
-				((rt_uint32_t)*temp & 0x3FF);
-			data->z = (*++temp & 0x200) ? ((rt_uint32_t)*temp | ~0x3FF) : \
-				((rt_uint32_t)*temp & 0x3FF);
-		}
+            buf[0] = XOUTL;
+            if (accel->read(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, \
+                sizeof(buf)) == 0)
+            {
+                ret = -RT_ERROR;
+                break;
+            }
+            data->x = (*temp & 0x200) ? ((rt_uint32_t)*temp | ~0x3FF) : \
+                ((rt_uint32_t)*temp & 0x3FF);
+            data->y = (*++temp & 0x200) ? ((rt_uint32_t)*temp | ~0x3FF) : \
+                ((rt_uint32_t)*temp & 0x3FF);
+            data->z = (*++temp & 0x200) ? ((rt_uint32_t)*temp | ~0x3FF) : \
+                ((rt_uint32_t)*temp & 0x3FF);
+        }
 #endif
-		return RT_EOK;
-	} while (0);
+        return RT_EOK;
+    } while (0);
 
-	accel_debug("Accel err: Get data failed!\n");
-	return ret;
+    accel_debug("Accel err: Get data failed!\n");
+    return ret;
 }
 
 /***************************************************************************//**
@@ -172,357 +172,357 @@ rt_err_t efm_accel_get_data(struct efm32_accel_result_t *data,
  * @note
  *
  * @param[in] parameter
- *	Parameter
+ *  Parameter
  ******************************************************************************/
 static void efm_accel_timer(void* parameter)
 {
-	accelInTime = false;
+    accelInTime = false;
 }
 
 #if (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC)
 /***************************************************************************//**
  * @brief
- *	Accelerometer level and pulse detection interrupts handler
+ *  Accelerometer level and pulse detection interrupts handler
  *
  * @details
  *
  * @note
  *
  * @param[in] device
- *	Pointer to device descriptor
+ *  Pointer to device descriptor
  ******************************************************************************/
 static void efm_accel_isr(rt_device_t device)
 {
-	rt_uint8_t buf[2];
+    rt_uint8_t buf[2];
 
-	if ((accelConfig & ACCEL_MASK_MODE) != ACCEL_MODE_MEASUREMENT)
-	{
-		/* Read detection source */
-		buf[0] = DETSRC;
-		if (accel->read(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 1) != 1)
-		{
-			accel_debug("Accel: read error\n");
-			return;
-		}
-		accel_debug("Accel: DETSRC %x\n", buf[0]);
+    if ((accelConfig & ACCEL_MASK_MODE) != ACCEL_MODE_MEASUREMENT)
+    {
+        /* Read detection source */
+        buf[0] = DETSRC;
+        if (accel->read(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 1) != 1)
+        {
+            accel_debug("Accel: read error\n");
+            return;
+        }
+        accel_debug("Accel: DETSRC %x\n", buf[0]);
 
-		/* Reset the interrupt flags: Part 1 */
-		buf[0] = INTRST;
-		buf[1] = INTRST_INT_1 | INTRST_INT_2;
-		accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2);
+        /* Reset the interrupt flags: Part 1 */
+        buf[0] = INTRST;
+        buf[1] = INTRST_INT_1 | INTRST_INT_2;
+        accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2);
 
-		/* Read status to waste some time */
-		buf[0] = STATUS;
-		if (accel->read(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 1) != 1)
-		{
-			accel_debug("Accel: read error\n");
-			return;
-		}
-		accel_debug("Accel: STATUS %x\n", buf[0]);
+        /* Read status to waste some time */
+        buf[0] = STATUS;
+        if (accel->read(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 1) != 1)
+        {
+            accel_debug("Accel: read error\n");
+            return;
+        }
+        accel_debug("Accel: STATUS %x\n", buf[0]);
 
-		/* Reset the interrupt flags: Part 2 */
-		buf[0] = INTRST;
-		buf[1] = 0x00;
-		accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2);
-	}
+        /* Reset the interrupt flags: Part 2 */
+        buf[0] = INTRST;
+        buf[1] = 0x00;
+        accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2);
+    }
 }
 
 /***************************************************************************//**
  * @brief
- *	Accelerometer configuration function
+ *  Accelerometer configuration function
  *
  * @details
  *
  * @note
  *
  * @param[in] config
- *	Configuration options
+ *  Configuration options
  *
  * @param[in] level_threshold
- *	Level detection threshold
+ *  Level detection threshold
  *
  * @param[in] pulse_threshold
- *	Pulse detection threshold
+ *  Pulse detection threshold
  *
  * @param[in] pulse_duration
- *	Time window for 1st pulse
+ *  Time window for 1st pulse
  *
  * @param[in] pulse_latency
- *	Pulse latency Time
+ *  Pulse latency Time
  *
  * @param[in] pulse_duration2
- *	Time window for 2nd pulse
+ *  Time window for 2nd pulse
  *
  * @return
- *	 Error code
+ *   Error code
  ******************************************************************************/
 rt_err_t efm_accel_config(rt_uint32_t config,
-	rt_uint8_t level_threshold,
-	rt_uint8_t pulse_threshold,
-	rt_uint8_t pulse_duration,
-	rt_uint8_t pulse_latency,
-	rt_uint8_t pulse_duration2)
+    rt_uint8_t level_threshold,
+    rt_uint8_t pulse_threshold,
+    rt_uint8_t pulse_duration,
+    rt_uint8_t pulse_latency,
+    rt_uint8_t pulse_duration2)
 {
-	rt_err_t ret;
-	rt_uint8_t buf[2];
-	rt_uint8_t mode, mctl_reg, ctl1_reg, ctl2_reg;
+    rt_err_t ret;
+    rt_uint8_t buf[2];
+    rt_uint8_t mode, mctl_reg, ctl1_reg, ctl2_reg;
 
-	ret = RT_EOK;
-	mctl_reg = 0;
-	ctl1_reg = 0;
-	ctl2_reg = 0;
+    ret = RT_EOK;
+    mctl_reg = 0;
+    ctl1_reg = 0;
+    ctl2_reg = 0;
 
-	/* Modify MCTL */
-	mode = config & ACCEL_MASK_MODE;
-	switch (mode)
-	{
-	case ACCEL_MODE_STANDBY:
-		mctl_reg |= MCTL_MODE_STANDBY;
-		break;
-	case ACCEL_MODE_MEASUREMENT:
-		mctl_reg |= MCTL_MODE_MEASUREMENT;
-		break;
-	case ACCEL_MODE_LEVEL:
-		mctl_reg |= MCTL_MODE_LEVEL;
-		break;
-	case ACCEL_MODE_PULSE:
-		mctl_reg |= MCTL_MODE_PULSE;
-		break;
-	default:
-		return -RT_ERROR;
-	}
+    /* Modify MCTL */
+    mode = config & ACCEL_MASK_MODE;
+    switch (mode)
+    {
+    case ACCEL_MODE_STANDBY:
+        mctl_reg |= MCTL_MODE_STANDBY;
+        break;
+    case ACCEL_MODE_MEASUREMENT:
+        mctl_reg |= MCTL_MODE_MEASUREMENT;
+        break;
+    case ACCEL_MODE_LEVEL:
+        mctl_reg |= MCTL_MODE_LEVEL;
+        break;
+    case ACCEL_MODE_PULSE:
+        mctl_reg |= MCTL_MODE_PULSE;
+        break;
+    default:
+        return -RT_ERROR;
+    }
 
-	switch (config & ACCEL_MASK_RANGE)
-	{
-	case ACCEL_RANGE_8G:
-		mctl_reg |= MCTL_RANGE_8G;
-		break;
-	case ACCEL_RANGE_4G:
-		mctl_reg |= MCTL_RANGE_4G;
-		break;
-	case ACCEL_RANGE_2G:
-		mctl_reg |= MCTL_RANGE_2G;
-		break;
-	default:
-		return -RT_ERROR;
-	}
+    switch (config & ACCEL_MASK_RANGE)
+    {
+    case ACCEL_RANGE_8G:
+        mctl_reg |= MCTL_RANGE_8G;
+        break;
+    case ACCEL_RANGE_4G:
+        mctl_reg |= MCTL_RANGE_4G;
+        break;
+    case ACCEL_RANGE_2G:
+        mctl_reg |= MCTL_RANGE_2G;
+        break;
+    default:
+        return -RT_ERROR;
+    }
 
-	if ((mode == ACCEL_MODE_LEVEL) || (mode == ACCEL_MODE_PULSE))
-	{
-		mctl_reg |= MCTL_PIN_INT1;
-	}
+    if ((mode == ACCEL_MODE_LEVEL) || (mode == ACCEL_MODE_PULSE))
+    {
+        mctl_reg |= MCTL_PIN_INT1;
+    }
 
-	/* Modify CTL1 */
-	if (config & ACCEL_INTPIN_INVERSE)
-	{
-		ctl1_reg |= CTL1_INTPIN_INVERSE;
-	}
+    /* Modify CTL1 */
+    if (config & ACCEL_INTPIN_INVERSE)
+    {
+        ctl1_reg |= CTL1_INTPIN_INVERSE;
+    }
 
-	switch (config & ACCEL_MASK_INT)
-	{
-	case ACCEL_INT_LEVEL_PULSE:
-		ctl1_reg |= CTL1_INT_LEVEL_PULSE;
-		break;
-	case ACCEL_INT_PULSE_LEVEL:
-		ctl1_reg |= CTL1_INT_PULSE_LEVEL;
-		break;
-	case ACCEL_INT_SINGLE_DOUBLE:
-		ctl1_reg |= CTL1_INT_SINGLE_DOUBLE;
-		break;
-	default:
-		break;
-	}
+    switch (config & ACCEL_MASK_INT)
+    {
+    case ACCEL_INT_LEVEL_PULSE:
+        ctl1_reg |= CTL1_INT_LEVEL_PULSE;
+        break;
+    case ACCEL_INT_PULSE_LEVEL:
+        ctl1_reg |= CTL1_INT_PULSE_LEVEL;
+        break;
+    case ACCEL_INT_SINGLE_DOUBLE:
+        ctl1_reg |= CTL1_INT_SINGLE_DOUBLE;
+        break;
+    default:
+        break;
+    }
 
-	switch (config & ACCEL_MASK_DISABLE)
-	{
-	case ACCEL_DISABLE_X:
-		ctl1_reg |= CTL1_X_DISABLE;
-		break;
-	case ACCEL_DISABLE_Y:
-		ctl1_reg |= CTL1_Y_DISABLE;
-		break;
-	case ACCEL_DISABLE_Z:
-		ctl1_reg |= CTL1_Z_DISABLE;
-		break;
-	default:
-		break;
-	}
+    switch (config & ACCEL_MASK_DISABLE)
+    {
+    case ACCEL_DISABLE_X:
+        ctl1_reg |= CTL1_X_DISABLE;
+        break;
+    case ACCEL_DISABLE_Y:
+        ctl1_reg |= CTL1_Y_DISABLE;
+        break;
+    case ACCEL_DISABLE_Z:
+        ctl1_reg |= CTL1_Z_DISABLE;
+        break;
+    default:
+        break;
+    }
 
-	if (config & ACCEL_THRESHOLD_INTEGER)
-	{
-		ctl1_reg |= CTL1_THRESHOLD_INTEGER;
-	}
+    if (config & ACCEL_THRESHOLD_INTEGER)
+    {
+        ctl1_reg |= CTL1_THRESHOLD_INTEGER;
+    }
 
-	if (config & ACCEL_BANDWIDTH_125HZ)
-	{
-		ctl1_reg |= CTL1_BANDWIDTH_125HZ;
-	}
+    if (config & ACCEL_BANDWIDTH_125HZ)
+    {
+        ctl1_reg |= CTL1_BANDWIDTH_125HZ;
+    }
 
-	/* Modify CTL2 */
-	if (config & ACCEL_LEVEL_AND)
-	{
-		ctl2_reg |= CTL2_LEVEL_AND;
-	}
-	if (config & ACCEL_PULSE_AND)
-	{
-		ctl2_reg |= CTL2_PULSE_AND;
-	}
-	if (config & ACCEL_DRIVE_STRONG)
-	{
-		ctl2_reg |= CTL2_DRIVE_STRONG;
-	}
+    /* Modify CTL2 */
+    if (config & ACCEL_LEVEL_AND)
+    {
+        ctl2_reg |= CTL2_LEVEL_AND;
+    }
+    if (config & ACCEL_PULSE_AND)
+    {
+        ctl2_reg |= CTL2_PULSE_AND;
+    }
+    if (config & ACCEL_DRIVE_STRONG)
+    {
+        ctl2_reg |= CTL2_DRIVE_STRONG;
+    }
 
-	do
-	{
-		/* Write registers */
-		buf[0] = MCTL;
-		buf[1] = mctl_reg;
-		if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0)
-		{
-			ret = -RT_ERROR;
-			break;
-		}
-		accel_debug("Accel: MCTL %x\n", mctl_reg);
+    do
+    {
+        /* Write registers */
+        buf[0] = MCTL;
+        buf[1] = mctl_reg;
+        if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0)
+        {
+            ret = -RT_ERROR;
+            break;
+        }
+        accel_debug("Accel: MCTL %x\n", mctl_reg);
 
-		buf[0] = CTL1;
-		buf[1] = ctl1_reg;
-		if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0)
-		{
-			ret = -RT_ERROR;
-			break;
-		}
-		accel_debug("Accel: CTL1 %x\n", ctl1_reg);
+        buf[0] = CTL1;
+        buf[1] = ctl1_reg;
+        if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0)
+        {
+            ret = -RT_ERROR;
+            break;
+        }
+        accel_debug("Accel: CTL1 %x\n", ctl1_reg);
 
-		buf[0] = CTL2;
-		buf[1] = ctl2_reg;
-		if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0)
-		{
-			ret = -RT_ERROR;
-			break;
-		}
-		accel_debug("Accel: CTL2 %x\n", ctl2_reg);
-		accelConfig = config;
+        buf[0] = CTL2;
+        buf[1] = ctl2_reg;
+        if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0)
+        {
+            ret = -RT_ERROR;
+            break;
+        }
+        accel_debug("Accel: CTL2 %x\n", ctl2_reg);
+        accelConfig = config;
 
-		if (mode == ACCEL_MODE_PULSE)
-		{
-			buf[0] = PDTH;
-			buf[1] = pulse_threshold;
-			if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0)
-			{
-				ret = -RT_ERROR;
-				break;
-			}
-			accel_debug("Accel: PDTH %x\n", buf[1]);
+        if (mode == ACCEL_MODE_PULSE)
+        {
+            buf[0] = PDTH;
+            buf[1] = pulse_threshold;
+            if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0)
+            {
+                ret = -RT_ERROR;
+                break;
+            }
+            accel_debug("Accel: PDTH %x\n", buf[1]);
 
-			buf[0] = PW;
-			buf[1] = pulse_duration;
-			if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0)
-			{
-				ret = -RT_ERROR;
-				break;
-			}
-			accel_debug("Accel: PW %x\n", buf[1]);
+            buf[0] = PW;
+            buf[1] = pulse_duration;
+            if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0)
+            {
+                ret = -RT_ERROR;
+                break;
+            }
+            accel_debug("Accel: PW %x\n", buf[1]);
 
-			buf[0] = LT;
-			buf[1] = pulse_latency;
-			if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0)
-			{
-				ret = -RT_ERROR;
-				break;
-			}
-			accel_debug("Accel: LT %x\n", buf[1]);
+            buf[0] = LT;
+            buf[1] = pulse_latency;
+            if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0)
+            {
+                ret = -RT_ERROR;
+                break;
+            }
+            accel_debug("Accel: LT %x\n", buf[1]);
 
-			buf[0] = TW;
-			buf[1] = pulse_duration2;
-			if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0)
-			{
-				ret = -RT_ERROR;
-				break;
-			}
-			accel_debug("Accel: TW %x\n", buf[1]);
-		}
+            buf[0] = TW;
+            buf[1] = pulse_duration2;
+            if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0)
+            {
+                ret = -RT_ERROR;
+                break;
+            }
+            accel_debug("Accel: TW %x\n", buf[1]);
+        }
 
-		if ((mode == ACCEL_MODE_LEVEL) || (mode == ACCEL_MODE_PULSE))
-		{
-			efm32_irq_hook_init_t hook;
+        if ((mode == ACCEL_MODE_LEVEL) || (mode == ACCEL_MODE_PULSE))
+        {
+            efm32_irq_hook_init_t hook;
 
-			/* Reset the interrupt flags: Part 1 */
-			buf[0] = INTRST;
-			buf[1] = INTRST_INT_1 | INTRST_INT_2;
-			if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0)
-			{
-				ret = -RT_ERROR;
-				break;
-			}
+            /* Reset the interrupt flags: Part 1 */
+            buf[0] = INTRST;
+            buf[1] = INTRST_INT_1 | INTRST_INT_2;
+            if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0)
+            {
+                ret = -RT_ERROR;
+                break;
+            }
 
-			/* Set level detection threshold */
-			buf[0] = LDTH;
-			if (config & ACCEL_THRESHOLD_INTEGER)
-			{
-				buf[1] = level_threshold;
-			}
-			else
-			{
-				buf[1] = level_threshold & 0x7f;
-			}
-			if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0)
-			{
-				ret = -RT_ERROR;
-				break;
-			}
-			accel_debug("Accel: LDTH %x\n", buf[1]);
+            /* Set level detection threshold */
+            buf[0] = LDTH;
+            if (config & ACCEL_THRESHOLD_INTEGER)
+            {
+                buf[1] = level_threshold;
+            }
+            else
+            {
+                buf[1] = level_threshold & 0x7f;
+            }
+            if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0)
+            {
+                ret = -RT_ERROR;
+                break;
+            }
+            accel_debug("Accel: LDTH %x\n", buf[1]);
 
-			/* Config interrupt */
-			hook.type		= efm32_irq_type_gpio;
-			hook.unit		= ACCEL_INT1_PIN;
-			hook.cbFunc 	= efm_accel_isr;
-			hook.userPtr	= RT_NULL;
-			efm32_irq_hook_register(&hook);
-			hook.unit		= ACCEL_INT2_PIN;
-			efm32_irq_hook_register(&hook);
-			/* Clear pending interrupt */
-			BITBAND_Peripheral(&(GPIO->IFC), ACCEL_INT1_PIN, 0x1UL);
-			BITBAND_Peripheral(&(GPIO->IFC), ACCEL_INT2_PIN, 0x1UL);
-			/* Set raising edge interrupt and clear/enable it */
-			GPIO_IntConfig(
-				ACCEL_INT1_PORT,
-				ACCEL_INT1_PIN,
-				true,
-				false,
-				true);
-			GPIO_IntConfig(
-				ACCEL_INT2_PORT,
-				ACCEL_INT2_PIN,
-				true,
-				false,
-				true);
-			if (((rt_uint8_t)ACCEL_INT1_PORT % 2) || \
-				((rt_uint8_t)ACCEL_INT2_PORT % 2))
-			{
-				NVIC_ClearPendingIRQ(GPIO_ODD_IRQn);
-				NVIC_SetPriority(GPIO_ODD_IRQn, EFM32_IRQ_PRI_DEFAULT);
-				NVIC_EnableIRQ(GPIO_ODD_IRQn);
-			}
-			if (!((rt_uint8_t)ACCEL_INT1_PORT % 2) || \
-				!((rt_uint8_t)ACCEL_INT2_PORT % 2))
-			{
-				NVIC_ClearPendingIRQ(GPIO_EVEN_IRQn);
-				NVIC_SetPriority(GPIO_EVEN_IRQn, EFM32_IRQ_PRI_DEFAULT);
-				NVIC_EnableIRQ(GPIO_EVEN_IRQn);
-			}
+            /* Config interrupt */
+            hook.type       = efm32_irq_type_gpio;
+            hook.unit       = ACCEL_INT1_PIN;
+            hook.cbFunc     = efm_accel_isr;
+            hook.userPtr    = RT_NULL;
+            efm32_irq_hook_register(&hook);
+            hook.unit       = ACCEL_INT2_PIN;
+            efm32_irq_hook_register(&hook);
+            /* Clear pending interrupt */
+            BITBAND_Peripheral(&(GPIO->IFC), ACCEL_INT1_PIN, 0x1UL);
+            BITBAND_Peripheral(&(GPIO->IFC), ACCEL_INT2_PIN, 0x1UL);
+            /* Set raising edge interrupt and clear/enable it */
+            GPIO_IntConfig(
+                ACCEL_INT1_PORT,
+                ACCEL_INT1_PIN,
+                true,
+                false,
+                true);
+            GPIO_IntConfig(
+                ACCEL_INT2_PORT,
+                ACCEL_INT2_PIN,
+                true,
+                false,
+                true);
+            if (((rt_uint8_t)ACCEL_INT1_PORT % 2) || \
+                ((rt_uint8_t)ACCEL_INT2_PORT % 2))
+            {
+                NVIC_ClearPendingIRQ(GPIO_ODD_IRQn);
+                NVIC_SetPriority(GPIO_ODD_IRQn, EFM32_IRQ_PRI_DEFAULT);
+                NVIC_EnableIRQ(GPIO_ODD_IRQn);
+            }
+            if (!((rt_uint8_t)ACCEL_INT1_PORT % 2) || \
+                !((rt_uint8_t)ACCEL_INT2_PORT % 2))
+            {
+                NVIC_ClearPendingIRQ(GPIO_EVEN_IRQn);
+                NVIC_SetPriority(GPIO_EVEN_IRQn, EFM32_IRQ_PRI_DEFAULT);
+                NVIC_EnableIRQ(GPIO_EVEN_IRQn);
+            }
 
-			/* Reset the interrupt flags: Part 2 */
-			buf[0] = INTRST;
-			buf[1] = 0x00;
-			if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0)
-			{
-				ret = -RT_ERROR;
-				break;
-			}
-		}
-	} while (0);
+            /* Reset the interrupt flags: Part 2 */
+            buf[0] = INTRST;
+            buf[1] = 0x00;
+            if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, (void *)buf, 2) == 0)
+            {
+                ret = -RT_ERROR;
+                break;
+            }
+        }
+    } while (0);
 
-	return ret;
+    return ret;
 }
 
 #endif
@@ -536,203 +536,203 @@ rt_err_t efm_accel_config(rt_uint32_t config,
  * @note
  *
  * @param[in] mode
- *	0, simple mode (assuming the device is placed on flat surface)
- *	1, interaction method
+ *  0, simple mode (assuming the device is placed on flat surface)
+ *  1, interaction method
  *
  * @param[in] period
- *	Time period to perform auto-zero calibration
+ *  Time period to perform auto-zero calibration
  *
  * @return
- *	 Error code
+ *   Error code
  ******************************************************************************/
 rt_err_t efm_accel_auto_zero(rt_uint8_t mode, rt_tick_t period)
 {
-	RT_ASSERT(accel != RT_NULL);
+    RT_ASSERT(accel != RT_NULL);
 
-	rt_timer_t calTimer;
-	struct efm32_accel_result_t min = {0, 0, 0};
-	struct efm32_accel_result_t max = {0, 0, 0};
-	struct efm32_accel_result_t temp, sum;
-	rt_int32_t simpleOffset[] = ACCEL_CAL_1G_VALUE;
-	rt_uint8_t cmd[7] = {0};
-	rt_uint8_t i, j;
+    rt_timer_t calTimer;
+    struct efm32_accel_result_t min = {0, 0, 0};
+    struct efm32_accel_result_t max = {0, 0, 0};
+    struct efm32_accel_result_t temp, sum;
+    rt_int32_t simpleOffset[] = ACCEL_CAL_1G_VALUE;
+    rt_uint8_t cmd[7] = {0};
+    rt_uint8_t i, j;
 
-	/* Reset offset */
+    /* Reset offset */
 #if (EFM32_USING_ACCEL == EFM32_INTERFACE_ADC)
-	accelOffset.x = 0;
-	accelOffset.y = 0;
-	accelOffset.z = 0;
+    accelOffset.x = 0;
+    accelOffset.y = 0;
+    accelOffset.z = 0;
 
 #elif (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC)
-	cmd[0] = XOFFL;
-	if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, cmd, sizeof(cmd)) == 0)
-	{
-		return -RT_ERROR;
-	}
+    cmd[0] = XOFFL;
+    if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, cmd, sizeof(cmd)) == 0)
+    {
+        return -RT_ERROR;
+    }
 #endif
 
-	if (mode == ACCEL_CAL_SIMPLE)
-	{
-		/* Simple mode */
-		for (j = 0; j < ACCEL_CAL_ROUND; j++)
-		{
-			sum.x = 0x0;
-			sum.y = 0x0;
-			sum.z = 0x0;
+    if (mode == ACCEL_CAL_SIMPLE)
+    {
+        /* Simple mode */
+        for (j = 0; j < ACCEL_CAL_ROUND; j++)
+        {
+            sum.x = 0x0;
+            sum.y = 0x0;
+            sum.z = 0x0;
 
-			for (i = 0; i < ACCEL_CAL_SAMPLES; i++)
-			{
+            for (i = 0; i < ACCEL_CAL_SAMPLES; i++)
+            {
 #if (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC)
-				/* Waiting for data ready */
-				while(!GPIO_PinInGet(ACCEL_INT1_PORT, ACCEL_INT1_PIN));
+                /* Waiting for data ready */
+                while(!GPIO_PinInGet(ACCEL_INT1_PORT, ACCEL_INT1_PIN));
 #endif
-				if (efm_accel_get_data(&temp, false) != RT_EOK)
-				{
-					return -RT_ERROR;
-				}
-				sum.x += temp.x;
-				sum.y += temp.y;
-				sum.z += temp.z;
-			}
+                if (efm_accel_get_data(&temp, false) != RT_EOK)
+                {
+                    return -RT_ERROR;
+                }
+                sum.x += temp.x;
+                sum.y += temp.y;
+                sum.z += temp.z;
+            }
 
 #if (EFM32_USING_ACCEL == EFM32_INTERFACE_ADC)
-			temp.x = sum.x / ACCEL_CAL_SAMPLES;
-			temp.y = sum.y / ACCEL_CAL_SAMPLES;
-			temp.z = sum.z / ACCEL_CAL_SAMPLES - simpleOffset[ACCEL_G_SELECT];
-			if ((temp.x == 0) && (temp.y == 0) && \
-				(temp.z == 0))
-			{
-				accel_debug("Accel: Offset %+d %+d %+d\n",
-					accelOffset.x, accelOffset.y, accelOffset.z);
-				break;
-			}
-			accelOffset.x -= temp.x;
-			accelOffset.y -= temp.y;
-			accelOffset.z -= temp.z;
+            temp.x = sum.x / ACCEL_CAL_SAMPLES;
+            temp.y = sum.y / ACCEL_CAL_SAMPLES;
+            temp.z = sum.z / ACCEL_CAL_SAMPLES - simpleOffset[ACCEL_G_SELECT];
+            if ((temp.x == 0) && (temp.y == 0) && \
+                (temp.z == 0))
+            {
+                accel_debug("Accel: Offset %+d %+d %+d\n",
+                    accelOffset.x, accelOffset.y, accelOffset.z);
+                break;
+            }
+            accelOffset.x -= temp.x;
+            accelOffset.y -= temp.y;
+            accelOffset.z -= temp.z;
 
 #elif (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC)
-			temp.x = sum.x / (ACCEL_CAL_SAMPLES >> 1);
-			temp.y = sum.y / (ACCEL_CAL_SAMPLES >> 1);
-			temp.z = sum.z / (ACCEL_CAL_SAMPLES >> 1) \
-				- (simpleOffset[ACCEL_G_SELECT] << 1);
-			if ((temp.x == 0) && (temp.y == 0) && \
-				(temp.z == 0))
-			{
-				break;
-			}
+            temp.x = sum.x / (ACCEL_CAL_SAMPLES >> 1);
+            temp.y = sum.y / (ACCEL_CAL_SAMPLES >> 1);
+            temp.z = sum.z / (ACCEL_CAL_SAMPLES >> 1) \
+                - (simpleOffset[ACCEL_G_SELECT] << 1);
+            if ((temp.x == 0) && (temp.y == 0) && \
+                (temp.z == 0))
+            {
+                break;
+            }
 
-			/* Set offset drift registers */
-			max.x -= temp.x;
-			max.y -= temp.y;
-			max.z -= temp.z;
-			*(rt_int16_t *)&cmd[1] = (rt_int16_t)max.x;
-			*(rt_int16_t *)&cmd[3] = (rt_int16_t)max.y;
-			*(rt_int16_t *)&cmd[5] = (rt_int16_t)max.z;
-			if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, cmd, sizeof(cmd)) == 0)
-			{
-				return -RT_ERROR;
-			}
-			accel_debug("Accel: Offset %+d %+d %+d\n", *(rt_int16_t *)&cmd[1], \
-				*(rt_int16_t *)&cmd[3], *(rt_int16_t *)&cmd[5]);
+            /* Set offset drift registers */
+            max.x -= temp.x;
+            max.y -= temp.y;
+            max.z -= temp.z;
+            *(rt_int16_t *)&cmd[1] = (rt_int16_t)max.x;
+            *(rt_int16_t *)&cmd[3] = (rt_int16_t)max.y;
+            *(rt_int16_t *)&cmd[5] = (rt_int16_t)max.z;
+            if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, cmd, sizeof(cmd)) == 0)
+            {
+                return -RT_ERROR;
+            }
+            accel_debug("Accel: Offset %+d %+d %+d\n", *(rt_int16_t *)&cmd[1], \
+                *(rt_int16_t *)&cmd[3], *(rt_int16_t *)&cmd[5]);
 #endif
-			rt_thread_sleep(1);
-		}
-	}
-	else
-	{
-		/* Interact mode */
-		if ((calTimer = rt_timer_create(
-			"cal_tmr",
-			efm_accel_timer,
-			RT_NULL,
-			period,
-			RT_TIMER_FLAG_ONE_SHOT)) == RT_NULL)
-		{
-			accel_debug("Accel err: Create timer failed!\n");
-			return -RT_ERROR;
-		}
+            rt_thread_sleep(1);
+        }
+    }
+    else
+    {
+        /* Interact mode */
+        if ((calTimer = rt_timer_create(
+            "cal_tmr",
+            efm_accel_timer,
+            RT_NULL,
+            period,
+            RT_TIMER_FLAG_ONE_SHOT)) == RT_NULL)
+        {
+            accel_debug("Accel err: Create timer failed!\n");
+            return -RT_ERROR;
+        }
 
-		accelInTime = true;
-		rt_timer_start(calTimer);
-		do
-		{
-			sum.x = 0x0;
-			sum.y = 0x0;
-			sum.z = 0x0;
+        accelInTime = true;
+        rt_timer_start(calTimer);
+        do
+        {
+            sum.x = 0x0;
+            sum.y = 0x0;
+            sum.z = 0x0;
 
-			for (i = 0; i < ACCEL_CAL_SAMPLES; i++)
-			{
+            for (i = 0; i < ACCEL_CAL_SAMPLES; i++)
+            {
 #if (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC)
-				/* Waiting for data ready */
-				while(!GPIO_PinInGet(ACCEL_INT1_PORT, ACCEL_INT1_PIN));
+                /* Waiting for data ready */
+                while(!GPIO_PinInGet(ACCEL_INT1_PORT, ACCEL_INT1_PIN));
 #endif
-				if (efm_accel_get_data(&temp, false) != RT_EOK)
-				{
-					return -RT_ERROR;
-				}
-				sum.x += temp.x;
-				sum.y += temp.y;
-				sum.z += temp.z;
-			}
-			sum.x /= ACCEL_CAL_SAMPLES;
-			sum.y /= ACCEL_CAL_SAMPLES;
-			sum.z /= ACCEL_CAL_SAMPLES;
-			if (sum.x < min.x)
-			{
-				min.x = sum.x;
-			}
-			if (sum.y < min.y)
-			{
-				min.y = sum.y;
-			}
-			if (sum.z < min.z)
-			{
-				min.z = sum.z;
-			}
-			if (sum.x > max.x)
-			{
-				max.x = sum.x;
-			}
-			if (sum.y > max.y)
-			{
-				max.y = sum.y;
-			}
-			if (sum.z > max.z)
-			{
-				max.z = sum.z;
-			}
-			rt_thread_sleep(1);
-		} while (accelInTime);
+                if (efm_accel_get_data(&temp, false) != RT_EOK)
+                {
+                    return -RT_ERROR;
+                }
+                sum.x += temp.x;
+                sum.y += temp.y;
+                sum.z += temp.z;
+            }
+            sum.x /= ACCEL_CAL_SAMPLES;
+            sum.y /= ACCEL_CAL_SAMPLES;
+            sum.z /= ACCEL_CAL_SAMPLES;
+            if (sum.x < min.x)
+            {
+                min.x = sum.x;
+            }
+            if (sum.y < min.y)
+            {
+                min.y = sum.y;
+            }
+            if (sum.z < min.z)
+            {
+                min.z = sum.z;
+            }
+            if (sum.x > max.x)
+            {
+                max.x = sum.x;
+            }
+            if (sum.y > max.y)
+            {
+                max.y = sum.y;
+            }
+            if (sum.z > max.z)
+            {
+                max.z = sum.z;
+            }
+            rt_thread_sleep(1);
+        } while (accelInTime);
 
-		accel_debug("Accel: Min %+d %+d %+d, max %+d %+d %+d\n",
-			min.x, min.y, min.z, max.x, max.y, max.z);
+        accel_debug("Accel: Min %+d %+d %+d, max %+d %+d %+d\n",
+            min.x, min.y, min.z, max.x, max.y, max.z);
 
 #if (EFM32_USING_ACCEL == EFM32_INTERFACE_ADC)
-		accelOffset.x = -((min.x + max.x) >> 1);
-		accelOffset.y = -((min.y + max.y) >> 1);
-		accelOffset.z = -((min.z + max.z) >> 1);
+        accelOffset.x = -((min.x + max.x) >> 1);
+        accelOffset.y = -((min.y + max.y) >> 1);
+        accelOffset.z = -((min.z + max.z) >> 1);
 
-	accel_debug("Accel: Offset %+d %+d %+d\n",
-		accelOffset.x, accelOffset.y, accelOffset.z);
+    accel_debug("Accel: Offset %+d %+d %+d\n",
+        accelOffset.x, accelOffset.y, accelOffset.z);
 
 #elif (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC)
-		/* Set offset drift registers */
-		*(rt_int16_t *)&cmd[1] = (rt_int16_t)-(min.x + max.x);
-		*(rt_int16_t *)&cmd[3] = (rt_int16_t)-(min.y + max.y);
-		*(rt_int16_t *)&cmd[5] = (rt_int16_t)-(min.z + max.z);
-		if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, cmd, sizeof(cmd)) == 0)
-		{
-			return -RT_ERROR;
-		}
+        /* Set offset drift registers */
+        *(rt_int16_t *)&cmd[1] = (rt_int16_t)-(min.x + max.x);
+        *(rt_int16_t *)&cmd[3] = (rt_int16_t)-(min.y + max.y);
+        *(rt_int16_t *)&cmd[5] = (rt_int16_t)-(min.z + max.z);
+        if (accel->write(accel, ACCEL_IIC_SLAVE_ADDRESS, cmd, sizeof(cmd)) == 0)
+        {
+            return -RT_ERROR;
+        }
 
-	accel_debug("Accel: Offset %+d %+d %+d\n",
-		*(rt_int16_t *)&cmd[1], *(rt_int16_t *)&cmd[3], *(rt_int16_t *)&cmd[5]);
+    accel_debug("Accel: Offset %+d %+d %+d\n",
+        *(rt_int16_t *)&cmd[1], *(rt_int16_t *)&cmd[3], *(rt_int16_t *)&cmd[5]);
 #endif
 
-		rt_timer_delete(calTimer);
-	}
+        rt_timer_delete(calTimer);
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 /***************************************************************************//**
@@ -744,147 +744,147 @@ rt_err_t efm_accel_auto_zero(rt_uint8_t mode, rt_tick_t period)
  * @note
  *
  * @return
- *	 Error code
+ *   Error code
  ******************************************************************************/
 rt_err_t efm_accel_init(void)
 {
-	rt_err_t ret;
+    rt_err_t ret;
 
-	ret = RT_EOK;
-	do
-	{
-		/* Find ADC device */
-		accel = rt_device_find(ACCEL_USING_DEVICE_NAME);
-		if (accel == RT_NULL)
-		{
-			accel_debug("Accel err: Can't find device: %s!\n", ACCEL_USING_DEVICE_NAME);
-			ret = -RT_ERROR;
-			break;
-		}
-		accel_debug("Accel: Find device %s\n", ACCEL_USING_DEVICE_NAME);
+    ret = RT_EOK;
+    do
+    {
+        /* Find ADC device */
+        accel = rt_device_find(ACCEL_USING_DEVICE_NAME);
+        if (accel == RT_NULL)
+        {
+            accel_debug("Accel err: Can't find device: %s!\n", ACCEL_USING_DEVICE_NAME);
+            ret = -RT_ERROR;
+            break;
+        }
+        accel_debug("Accel: Find device %s\n", ACCEL_USING_DEVICE_NAME);
 
-		/* --------- ADC interface --------- */
+        /* --------- ADC interface --------- */
 #if (EFM32_USING_ACCEL == EFM32_INTERFACE_ADC)
-		ADC_InitScan_TypeDef scanInit = ADC_INITSCAN_DEFAULT;
+        ADC_InitScan_TypeDef scanInit = ADC_INITSCAN_DEFAULT;
 
  #if defined(EFM32_GXXX_DK)
-		/* Enable accelerometer */
-		DVK_enablePeripheral(DVK_ACCEL);
-			/* Select g-range */
+        /* Enable accelerometer */
+        DVK_enablePeripheral(DVK_ACCEL);
+            /* Select g-range */
   #if (ACCEL_G_SELECT == 0)
-		DVK_disablePeripheral(DVK_ACCEL_GSEL);
+        DVK_disablePeripheral(DVK_ACCEL_GSEL);
   #elif (ACCEL_G_SELECT == 1)
-		DVK_enablePeripheral(DVK_ACCEL_GSEL);
+        DVK_enablePeripheral(DVK_ACCEL_GSEL);
   #else
   #error "Wrong value for ACCEL_G_SELECT"
   #endif
  #endif
-		/* Init ADC for scan mode */
-		scanInit.reference = adcRefVDD;
-		scanInit.input = ACCEL_X_ADC_CH | ACCEL_Y_ADC_CH | ACCEL_Z_ADC_CH;
+        /* Init ADC for scan mode */
+        scanInit.reference = adcRefVDD;
+        scanInit.input = ACCEL_X_ADC_CH | ACCEL_Y_ADC_CH | ACCEL_Z_ADC_CH;
 
-		control.scan.init = &scanInit;
-		if ((ret = accel->control(accel, RT_DEVICE_CTRL_ADC_MODE, \
-			(void *)&control)) != RT_EOK)
-		{
-			break;
-		}
+        control.scan.init = &scanInit;
+        if ((ret = accel->control(accel, RT_DEVICE_CTRL_ADC_MODE, \
+            (void *)&control)) != RT_EOK)
+        {
+            break;
+        }
 
-		/* --------- IIC interface --------- */
+        /* --------- IIC interface --------- */
 #elif (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC)
-		rt_uint8_t cmd[2];
+        rt_uint8_t cmd[2];
 
-		/* Initialize */
-		if ((ret = accel->control(accel, RT_DEVICE_CTRL_IIC_SETTING, \
-			(void *)&control)) != RT_EOK)
-		{
-			break;
-		}
+        /* Initialize */
+        if ((ret = accel->control(accel, RT_DEVICE_CTRL_IIC_SETTING, \
+            (void *)&control)) != RT_EOK)
+        {
+            break;
+        }
 
-		if (efm_accel_config(
-			ACCEL_MODE_MEASUREMENT | ACCEL_RANGE_2G,
-			EFM32_NO_DATA,
-			EFM32_NO_DATA,
-			EFM32_NO_DATA,
-			EFM32_NO_DATA,
-			EFM32_NO_DATA) != RT_EOK)
-		{
-			break;
-		}
+        if (efm_accel_config(
+            ACCEL_MODE_MEASUREMENT | ACCEL_RANGE_2G,
+            EFM32_NO_DATA,
+            EFM32_NO_DATA,
+            EFM32_NO_DATA,
+            EFM32_NO_DATA,
+            EFM32_NO_DATA) != RT_EOK)
+        {
+            break;
+        }
 
-		/* Config interrupt pin1 */
-		GPIO_PinModeSet(ACCEL_INT1_PORT, ACCEL_INT1_PIN, gpioModeInput, 0);
-		/* Config interrupt pin2 */
-		GPIO_PinModeSet(ACCEL_INT2_PORT, ACCEL_INT2_PIN, gpioModeInput, 0);
+        /* Config interrupt pin1 */
+        GPIO_PinModeSet(ACCEL_INT1_PORT, ACCEL_INT1_PIN, gpioModeInput, 0);
+        /* Config interrupt pin2 */
+        GPIO_PinModeSet(ACCEL_INT2_PORT, ACCEL_INT2_PIN, gpioModeInput, 0);
 #endif
 
-		accel_debug("Accel: Init OK\n");
-		return RT_EOK;
-	} while (0);
+        accel_debug("Accel: Init OK\n");
+        return RT_EOK;
+    } while (0);
 
-	accel_debug("Accel err: Init failed!\n");
-	return -RT_ERROR;
+    accel_debug("Accel err: Init failed!\n");
+    return -RT_ERROR;
 }
 
 /*******************************************************************************
- * 	Export to FINSH
+ *  Export to FINSH
  ******************************************************************************/
 #ifdef RT_USING_FINSH
 #include 
 
 void accel_cal(rt_uint8_t mode, rt_uint32_t second)
 {
-	if (efm_accel_auto_zero(mode, RT_TICK_PER_SECOND * second) != RT_EOK)
-	{
-		rt_kprintf("Error occurred.");
-		return;
-	}
+    if (efm_accel_auto_zero(mode, RT_TICK_PER_SECOND * second) != RT_EOK)
+    {
+        rt_kprintf("Error occurred.");
+        return;
+    }
 
-	rt_kprintf("Calibration done.\n");
+    rt_kprintf("Calibration done.\n");
 }
 FINSH_FUNCTION_EXPORT(accel_cal, auto-zero calibration.)
 
 void list_accel(void)
 {
-	struct efm32_accel_result_t data;
+    struct efm32_accel_result_t data;
 
-	efm_accel_get_data(&data, false);
-	rt_kprintf("X: %d, Y: %d, Z: %d\n", data.x, data.y, data.z);
+    efm_accel_get_data(&data, false);
+    rt_kprintf("X: %d, Y: %d, Z: %d\n", data.x, data.y, data.z);
 }
 FINSH_FUNCTION_EXPORT(list_accel, list accelerometer info.)
 
 void test_accel(rt_uint8_t mode)
 {
-	if (mode == 0)
-	{
-		if (efm_accel_config(
-			ACCEL_MODE_LEVEL | ACCEL_RANGE_8G | ACCEL_INT_LEVEL_PULSE | \
-			ACCEL_SOURCE_LEVEL_X | ACCEL_SOURCE_LEVEL_Y,
-			0x1f,
-			EFM32_NO_DATA,
-			EFM32_NO_DATA,
-			EFM32_NO_DATA,
-			EFM32_NO_DATA) != RT_EOK)
-		{
-			rt_kprintf("efm_accel_config(): error\n");
-			return;
-		}
-	}
-	else
-	{
-		if (efm_accel_config(
-			ACCEL_MODE_PULSE | ACCEL_RANGE_8G | ACCEL_INT_SINGLE_DOUBLE | \
-			ACCEL_SOURCE_PULSE_X | ACCEL_SOURCE_PULSE_Y,
-			0x1f,
-			0x1f,
-			200,
-			255,
-			255) != RT_EOK)
-		{
-			rt_kprintf("efm_accel_config(): error\n");
-			return;
-		}
-	}
+    if (mode == 0)
+    {
+        if (efm_accel_config(
+            ACCEL_MODE_LEVEL | ACCEL_RANGE_8G | ACCEL_INT_LEVEL_PULSE | \
+            ACCEL_SOURCE_LEVEL_X | ACCEL_SOURCE_LEVEL_Y,
+            0x1f,
+            EFM32_NO_DATA,
+            EFM32_NO_DATA,
+            EFM32_NO_DATA,
+            EFM32_NO_DATA) != RT_EOK)
+        {
+            rt_kprintf("efm_accel_config(): error\n");
+            return;
+        }
+    }
+    else
+    {
+        if (efm_accel_config(
+            ACCEL_MODE_PULSE | ACCEL_RANGE_8G | ACCEL_INT_SINGLE_DOUBLE | \
+            ACCEL_SOURCE_PULSE_X | ACCEL_SOURCE_PULSE_Y,
+            0x1f,
+            0x1f,
+            200,
+            255,
+            255) != RT_EOK)
+        {
+            rt_kprintf("efm_accel_config(): error\n");
+            return;
+        }
+    }
 }
 FINSH_FUNCTION_EXPORT(test_accel, list accelerometer info.)
 #endif
diff --git a/bsp/efm32/dev_accel.h b/bsp/efm32/dev_accel.h
index 2e12d797d3..cc75631834 100644
--- a/bsp/efm32/dev_accel.h
+++ b/bsp/efm32/dev_accel.h
@@ -1,8 +1,8 @@
 /***************************************************************************//**
- * @file 	dev_accel.h
- * @brief 	Accelerometer driver of RT-Thread RTOS for EFM32
+ * @file    dev_accel.h
+ * @brief   Accelerometer driver of RT-Thread RTOS for EFM32
  *  COPYRIGHT (C) 2012, RT-Thread Development Team
- * @author 	onelife
+ * @author  onelife
  * @version 1.0
  *******************************************************************************
  * @section License
@@ -10,10 +10,10 @@
  * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
  *******************************************************************************
  * @section Change Logs
- * Date			Author		Notes
- * 2011-07-13	onelife		Initial creation for using EFM32 ADC module to
+ * Date         Author      Notes
+ * 2011-07-13   onelife     Initial creation for using EFM32 ADC module to
  *  interface the Freescale MMA7361L
- * 2011-08-02	onelife		Add digital interface support of using EFM32 IIC
+ * 2011-08-02   onelife     Add digital interface support of using EFM32 IIC
  *  module for the Freescale MMA7455L
  ******************************************************************************/
 #ifndef __DEV_ACCEL_H__
@@ -27,95 +27,95 @@
 /* Exported types ------------------------------------------------------------*/
 struct efm32_accel_result_t
 {
-	rt_int32_t 				x;
-	rt_int32_t 				y;
-	rt_int32_t 				z;
+    rt_int32_t              x;
+    rt_int32_t              y;
+    rt_int32_t              z;
 };
 
 /* Exported constants --------------------------------------------------------*/
 /* Exported macro ------------------------------------------------------------*/
-/* 	MMA7361LC
- 	g-Select 	g-Range 	Sensitivity
- 	0 			1.5 g 		800 mV/g
- 	1 			6 g 		206 mV/g
+/*  MMA7361LC
+    g-Select    g-Range     Sensitivity
+    0           1.5 g       800 mV/g
+    1           6 g         206 mV/g
 
- 	MMA7455L
- 	g-Select 	g-Range 	Sensitivity
- 	0 			2 g 		64 LSB/g
- 	1 			4 g 		32 LSB/g
-	2			8 g 		16 LSB/g
+    MMA7455L
+    g-Select    g-Range     Sensitivity
+    0           2 g         64 LSB/g
+    1           4 g         32 LSB/g
+    2           8 g         16 LSB/g
 */
-#define ACCEL_G_SELECT 			(0)
+#define ACCEL_G_SELECT          (0)
 
-#define ACCEL_CAL_SAMPLES 		(4) 	/* Must be multiple of 2 */
-#define ACCEL_CAL_ROUND 		(50)
-#define ACCEL_CAL_SIMPLE 		(0)
-#define ACCEL_CAL_INTERACT 		(1)
+#define ACCEL_CAL_SAMPLES       (4)     /* Must be multiple of 2 */
+#define ACCEL_CAL_ROUND         (50)
+#define ACCEL_CAL_SIMPLE        (0)
+#define ACCEL_CAL_INTERACT      (1)
 
 #if (EFM32_USING_ACCEL == EFM32_INTERFACE_ADC)
 /* Reading_at_1g = Sensitivity * Max_reading / Refference_voltage */
-#define ACCEL_CAL_1G_VALUE 		{993, 256}
+#define ACCEL_CAL_1G_VALUE      {993, 256}
 
-#define ACCEL_X_ADC_CH 			ADC_SCANCTRL_INPUTMASK_CH2
-#define ACCEL_Y_ADC_CH 			ADC_SCANCTRL_INPUTMASK_CH3
-#define ACCEL_Z_ADC_CH 			ADC_SCANCTRL_INPUTMASK_CH4
+#define ACCEL_X_ADC_CH          ADC_SCANCTRL_INPUTMASK_CH2
+#define ACCEL_Y_ADC_CH          ADC_SCANCTRL_INPUTMASK_CH3
+#define ACCEL_Z_ADC_CH          ADC_SCANCTRL_INPUTMASK_CH4
 #elif (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC)
-#define ACCEL_CAL_1G_VALUE 		{0x3f, 0x1f, 0x0f}
+#define ACCEL_CAL_1G_VALUE      {0x3f, 0x1f, 0x0f}
 #define ACCEL_IIC_SLAVE_ADDRESS (0x1d)
 
-#define ACCEL_INT1_PORT			(gpioPortD)
-#define ACCEL_INT1_PIN			(13)
-#define ACCEL_INT2_PORT 		(gpioPortD)
-#define ACCEL_INT2_PIN 			(12)
+#define ACCEL_INT1_PORT         (gpioPortD)
+#define ACCEL_INT1_PIN          (13)
+#define ACCEL_INT2_PORT         (gpioPortD)
+#define ACCEL_INT2_PIN          (12)
 
-#define ACCEL_MODE_STANDBY 		(1 << 0)
-#define ACCEL_MODE_MEASUREMENT	(1 << 1)
-#define ACCEL_MODE_LEVEL		(1 << 2)
-#define ACCEL_MODE_PULSE 		(1 << 3)
-#define ACCEL_RANGE_8G 			(1 << 4)
-#define ACCEL_RANGE_4G 			(1 << 5)
-#define ACCEL_RANGE_2G 			(1 << 6)
-#define ACCEL_INTPIN_INVERSE 	(1 << 7)
-#define ACCEL_INT_LEVEL_PULSE 	(1 << 8)
-#define ACCEL_INT_PULSE_LEVEL 	(1 << 9)
-#define ACCEL_INT_SINGLE_DOUBLE	(1 << 10)
-#define ACCEL_DISABLE_X 		(1 << 11)
-#define ACCEL_DISABLE_Y 		(1 << 12)
-#define ACCEL_DISABLE_Z 		(1 << 13)
-#define ACCEL_THRESHOLD_INTEGER	(1 << 14) 	/* For level detection only */
-#define ACCEL_BANDWIDTH_125HZ	(1 << 15)
-#define ACCEL_LEVEL_AND			(1 << 16)
-#define ACCEL_PULSE_AND			(1 << 17)
-#define ACCEL_DRIVE_STRONG		(1 << 18)
-#define ACCEL_SOURCE_LEVEL_X 	(1 << 19)
-#define ACCEL_SOURCE_LEVEL_Y 	(1 << 20)
-#define ACCEL_SOURCE_LEVEL_Z 	(1 << 21)
-#define ACCEL_SOURCE_PULSE_X 	(1 << 22)
-#define ACCEL_SOURCE_PULSE_Y 	(1 << 23)
-#define ACCEL_SOURCE_PULSE_Z 	(1 << 24)
+#define ACCEL_MODE_STANDBY      (1 << 0)
+#define ACCEL_MODE_MEASUREMENT  (1 << 1)
+#define ACCEL_MODE_LEVEL        (1 << 2)
+#define ACCEL_MODE_PULSE        (1 << 3)
+#define ACCEL_RANGE_8G          (1 << 4)
+#define ACCEL_RANGE_4G          (1 << 5)
+#define ACCEL_RANGE_2G          (1 << 6)
+#define ACCEL_INTPIN_INVERSE    (1 << 7)
+#define ACCEL_INT_LEVEL_PULSE   (1 << 8)
+#define ACCEL_INT_PULSE_LEVEL   (1 << 9)
+#define ACCEL_INT_SINGLE_DOUBLE (1 << 10)
+#define ACCEL_DISABLE_X         (1 << 11)
+#define ACCEL_DISABLE_Y         (1 << 12)
+#define ACCEL_DISABLE_Z         (1 << 13)
+#define ACCEL_THRESHOLD_INTEGER (1 << 14)   /* For level detection only */
+#define ACCEL_BANDWIDTH_125HZ   (1 << 15)
+#define ACCEL_LEVEL_AND         (1 << 16)
+#define ACCEL_PULSE_AND         (1 << 17)
+#define ACCEL_DRIVE_STRONG      (1 << 18)
+#define ACCEL_SOURCE_LEVEL_X    (1 << 19)
+#define ACCEL_SOURCE_LEVEL_Y    (1 << 20)
+#define ACCEL_SOURCE_LEVEL_Z    (1 << 21)
+#define ACCEL_SOURCE_PULSE_X    (1 << 22)
+#define ACCEL_SOURCE_PULSE_Y    (1 << 23)
+#define ACCEL_SOURCE_PULSE_Z    (1 << 24)
 
-#define ACCEL_SHIFT_MODE 		(0)
-#define ACCEL_SHIFT_RANGE 		(4)
-#define ACCEL_SHIFT_INT 		(8)
-#define ACCEL_SHIFT_DISABLE		(11)
-#define ACCEL_SHIFT_SOURCE		(19)
+#define ACCEL_SHIFT_MODE        (0)
+#define ACCEL_SHIFT_RANGE       (4)
+#define ACCEL_SHIFT_INT         (8)
+#define ACCEL_SHIFT_DISABLE     (11)
+#define ACCEL_SHIFT_SOURCE      (19)
 
-#define ACCEL_MASK_MODE 		(0X0000000f << ACCEL_SHIFT_MODE)
-#define ACCEL_MASK_RANGE 		(0X00000007 << ACCEL_SHIFT_RANGE)
-#define ACCEL_MASK_INT 			(0X00000007 << ACCEL_SHIFT_INT)
-#define ACCEL_MASK_DISABLE 		(0X00000007 << ACCEL_SHIFT_DISABLE)
-#define ACCEL_MASK_SOURCE 		(0X0000003f << ACCEL_SHIFT_SOURCE)
+#define ACCEL_MASK_MODE         (0X0000000f << ACCEL_SHIFT_MODE)
+#define ACCEL_MASK_RANGE        (0X00000007 << ACCEL_SHIFT_RANGE)
+#define ACCEL_MASK_INT          (0X00000007 << ACCEL_SHIFT_INT)
+#define ACCEL_MASK_DISABLE      (0X00000007 << ACCEL_SHIFT_DISABLE)
+#define ACCEL_MASK_SOURCE       (0X0000003f << ACCEL_SHIFT_SOURCE)
 #endif
 
 /* Exported functions ------------------------------------------------------- */
 rt_err_t efm_accel_get_data(struct efm32_accel_result_t *data,
-	rt_bool_t lowResolution);
+    rt_bool_t lowResolution);
 rt_err_t efm_accel_config(rt_uint32_t config,
-	rt_uint8_t level_threshold,
-	rt_uint8_t pulse_threshold,
-	rt_uint8_t pulse_duration,
-	rt_uint8_t pulse_latency,
-	rt_uint8_t pulse_duration2);
+    rt_uint8_t level_threshold,
+    rt_uint8_t pulse_threshold,
+    rt_uint8_t pulse_duration,
+    rt_uint8_t pulse_latency,
+    rt_uint8_t pulse_duration2);
 rt_err_t efm_accel_auto_zero(rt_uint8_t mode, rt_tick_t period);
 rt_err_t efm_accel_init(void);
 
diff --git a/bsp/efm32/dev_keys.c b/bsp/efm32/dev_keys.c
index a7a58ff20f..15d306b36b 100644
--- a/bsp/efm32/dev_keys.c
+++ b/bsp/efm32/dev_keys.c
@@ -1,8 +1,8 @@
 /***************************************************************************//**
- * @file 	dev_keys.c
- * @brief 	Keys driver of RT-Thread RTOS for EFM32
+ * @file    dev_keys.c
+ * @brief   Keys driver of RT-Thread RTOS for EFM32
  *  COPYRIGHT (C) 2012, RT-Thread Development Team
- * @author 	onelife
+ * @author  onelife
  * @version 1.0
  *******************************************************************************
  * @section License
@@ -10,7 +10,7 @@
  *  LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
  *******************************************************************************
  * @section Change Logs
- * Date			Author		Notes
+ * Date         Author      Notes
  * 2011-12-29   onelife     Initial creation for EFM32GG_DK3750 board
  ******************************************************************************/
 
@@ -48,14 +48,14 @@ static rt_bool_t                            click;
 /* Private functions ---------------------------------------------------------*/
 /***************************************************************************//**
  * @brief
- *	Keys interrupt handler
+ *  Keys interrupt handler
  *
  * @details
  *
  * @note
  *
  * @param[in] device
- *	Pointer to device descriptor
+ *  Pointer to device descriptor
  ******************************************************************************/
 static void efm32_keys_isr(rt_device_t dev)
 {
@@ -158,18 +158,18 @@ static void efm32_keys_isr(rt_device_t dev)
 
 /***************************************************************************//**
  * @brief
- *	Keys timeout handler
+ *  Keys timeout handler
  *
  * @details
  *
  * @note
  *
  * @param[in] param
- *	Parameter
+ *  Parameter
  ******************************************************************************/
 static void efm32_keys_timer_isr(void *param)
 {
-	rt_uint16_t joystick;
+    rt_uint16_t joystick;
 
     joystick = DVK_getJoystick();
 
@@ -277,11 +277,11 @@ void efm32_hw_keys_init(void)
     GPIO_IntConfig(KEYS_INT_PORT, KEYS_INT_PIN, true, true, true);
 
     efm32_irq_hook_init_t hook;
-	hook.type       = efm32_irq_type_gpio;
-	hook.unit       = KEYS_INT_PIN;
-	hook.cbFunc     = efm32_keys_isr;
-	hook.userPtr    = RT_NULL;
-	efm32_irq_hook_register(&hook);
+    hook.type       = efm32_irq_type_gpio;
+    hook.unit       = KEYS_INT_PIN;
+    hook.cbFunc     = efm32_keys_isr;
+    hook.userPtr    = RT_NULL;
+    efm32_irq_hook_register(&hook);
 
     if ((rt_uint8_t)KEYS_INT_PIN % 2)
     {
@@ -299,12 +299,12 @@ void efm32_hw_keys_init(void)
     /* Enable DVK joystick interrupt */
     DVK_enableInterrupt(BC_INTEN_JOYSTICK);
 
-	rt_timer_init(&joy.timer,
-		"joy_tmr",
-		efm32_keys_timer_isr,
-		RT_NULL,
-		KEYS_POLL_TIME,
-		RT_TIMER_FLAG_PERIODIC);
+    rt_timer_init(&joy.timer,
+        "joy_tmr",
+        efm32_keys_timer_isr,
+        RT_NULL,
+        KEYS_POLL_TIME,
+        RT_TIMER_FLAG_PERIODIC);
 
     joy_dev.init        = efm32_keys_init;
     joy_dev.open        = RT_NULL;
diff --git a/bsp/efm32/dev_keys.h b/bsp/efm32/dev_keys.h
index 6e66617331..87f8fe95fd 100644
--- a/bsp/efm32/dev_keys.h
+++ b/bsp/efm32/dev_keys.h
@@ -1,8 +1,8 @@
 /***************************************************************************//**
- * @file 	dev_keys.h
- * @brief 	Keys driver of RT-Thread RTOS for EFM32
+ * @file    dev_keys.h
+ * @brief   Keys driver of RT-Thread RTOS for EFM32
  *  COPYRIGHT (C) 2012, RT-Thread Development Team
- * @author 	onelife
+ * @author  onelife
  * @version 1.0
  *******************************************************************************
  * @section License
@@ -10,7 +10,7 @@
  *  LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
  *******************************************************************************
  * @section Change Logs
- * Date			Author		Notes
+ * Date         Author      Notes
  * 2011-12-29   onelife     Initial creation for EFM32GG_DK3750 board
  ******************************************************************************/
 #ifndef __DEV_KEYS_H__
diff --git a/bsp/efm32/dev_lcd.c b/bsp/efm32/dev_lcd.c
index 0a2d469d78..c4cbbcce21 100644
--- a/bsp/efm32/dev_lcd.c
+++ b/bsp/efm32/dev_lcd.c
@@ -1,8 +1,8 @@
 /***************************************************************************//**
- * @file 	dev_lcd.c
- * @brief 	LCD driver of RT-Thread RTOS for EFM32
+ * @file    dev_lcd.c
+ * @brief   LCD driver of RT-Thread RTOS for EFM32
  *  COPYRIGHT (C) 2012, RT-Thread Development Team
- * @author 	onelife
+ * @author  onelife
  * @version 1.0
  *******************************************************************************
  * @section License
@@ -10,7 +10,7 @@
  *  LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
  *******************************************************************************
  * @section Change Logs
- * Date			Author		Notes
+ * Date         Author      Notes
  * 2011-12-16   onelife     Initial creation of address mapped method (pixel
  *  drive) for EFM32GG_DK3750 board
  * 2011-12-29   onelife     Add direct drive method (frame buffer) support
@@ -451,48 +451,48 @@ rt_err_t efm32_spiLcd_writeRegister(rt_uint8_t reg, rt_uint16_t data)
 
 /***************************************************************************//**
  * @brief
- *	Register LCD device
+ *  Register LCD device
  *
  * @details
  *
  * @note
  *
  * @param[in] device
- *	Pointer to device descriptor
+ *  Pointer to device descriptor
  *
  * @param[in] name
- *	Device name
+ *  Device name
  *
  * @param[in] flag
- *	Configuration flags
+ *  Configuration flags
  *
  * @param[in] iic
- *	Pointer to IIC device descriptor
+ *  Pointer to IIC device descriptor
  *
  * @return
- *	Error code
+ *  Error code
  ******************************************************************************/
 rt_err_t efm32_spiLcd_register(
-	rt_device_t		                device,
-	const char		                *name,
-	rt_uint32_t		                flag,
-	void                            *data)
+    rt_device_t                     device,
+    const char                      *name,
+    rt_uint32_t                     flag,
+    void                            *data)
 {
-	RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(device != RT_NULL);
 
-	device->type 		= RT_Device_Class_Graphic;
-	device->rx_indicate = RT_NULL;
-	device->tx_complete = RT_NULL;
-	device->init 		= RT_NULL;
-	device->open		= RT_NULL;
-	device->close		= RT_NULL;
-	device->read 		= RT_NULL;
-	device->write 		= RT_NULL;
-	device->control 	= efm32_spiLcd_control;
-	device->user_data	= data;
+    device->type        = RT_Device_Class_Graphic;
+    device->rx_indicate = RT_NULL;
+    device->tx_complete = RT_NULL;
+    device->init        = RT_NULL;
+    device->open        = RT_NULL;
+    device->close       = RT_NULL;
+    device->read        = RT_NULL;
+    device->write       = RT_NULL;
+    device->control     = efm32_spiLcd_control;
+    device->user_data   = data;
 
-	/* register a character device */
-	return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
+    /* register a character device */
+    return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
 }
 
 /***************************************************************************//**
@@ -511,18 +511,18 @@ void efm32_spiLcd_init(void)
     DMD_DisplayGeometry         *geometry;
     rt_uint32_t                 ret;
 
-	do
-	{
+    do
+    {
         USART_InitSync_TypeDef init = USART_INITSYNC_DEFAULT;
 
-		/* Find SPI device */
-		lcd = rt_device_find(LCD_USING_DEVICE_NAME);
-		if (lcd == RT_NULL)
-		{
-			lcd_debug("LCD err: Can't find %s!\n", LCD_USING_DEVICE_NAME);
-			break;
-		}
-		lcd_debug("LCD: Find device %s\n", LCD_USING_DEVICE_NAME);
+        /* Find SPI device */
+        lcd = rt_device_find(LCD_USING_DEVICE_NAME);
+        if (lcd == RT_NULL)
+        {
+            lcd_debug("LCD err: Can't find %s!\n", LCD_USING_DEVICE_NAME);
+            break;
+        }
+        lcd_debug("LCD: Find device %s\n", LCD_USING_DEVICE_NAME);
 
         /* Config CS pin */
         usart = (struct efm32_usart_device_t *)(lcd->user_data);
@@ -647,7 +647,7 @@ void efm32_spiLcd_init(void)
         }
 
         /* Init LCD info */
-		flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_DMA_TX;
+        flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_DMA_TX;
         lcd_info.pixel_format       = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
         lcd_info.bits_per_pixel     = 16;
         lcd_info.width              = geometry->xSize;
diff --git a/bsp/efm32/dev_lcd.h b/bsp/efm32/dev_lcd.h
index 075bed64ba..4c59286ef6 100644
--- a/bsp/efm32/dev_lcd.h
+++ b/bsp/efm32/dev_lcd.h
@@ -1,8 +1,8 @@
 /***************************************************************************//**
- * @file 	dev_lcd.h
- * @brief 	LCD driver of RT-Thread RTOS for EFM32
+ * @file    dev_lcd.h
+ * @brief   LCD driver of RT-Thread RTOS for EFM32
  *  COPYRIGHT (C) 2012, RT-Thread Development Team
- * @author 	onelife
+ * @author  onelife
  * @version 1.0
  *******************************************************************************
  * @section License
@@ -10,7 +10,7 @@
  *  LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
  *******************************************************************************
  * @section Change Logs
- * Date			Author		Notes
+ * Date         Author      Notes
  * 2011-12-16   onelife     Initial creation of address mapped method (pixel
  *  drive) for EFM32GG_DK3750 board
  ******************************************************************************/
diff --git a/bsp/efm32/dev_sflash.h b/bsp/efm32/dev_sflash.h
index ae72ec678a..b7d2860f0d 100644
--- a/bsp/efm32/dev_sflash.h
+++ b/bsp/efm32/dev_sflash.h
@@ -20,85 +20,85 @@
 /* Exported types ------------------------------------------------------------*/
 enum sflash_inst_type_t
 {
-	/* Instruction only */
-	sflash_inst_wren = 0x00,
-	sflash_inst_wrdi,
-	sflash_inst_rdid_l,
-	sflash_inst_rdid_s,
-	sflash_inst_rdsr,
-	sflash_inst_wrsr,
-	sflash_inst_be,
-	sflash_inst_dp,
-	sflash_inst_rdp,
-	/* Instruction and address */
-	sflash_inst_wrlr,
-	sflash_inst_rdlr,
-	sflash_inst_read,
-	sflash_inst_potp,
-	sflash_inst_pp,
-	sflash_inst_difp,
-	sflash_inst_sse,
-	sflash_inst_se,
-	/* Instruction, address and dummy read */
-	sflash_inst_read_f,
-	sflash_inst_dofr,
-	sflash_inst_rotp
+    /* Instruction only */
+    sflash_inst_wren = 0x00,
+    sflash_inst_wrdi,
+    sflash_inst_rdid_l,
+    sflash_inst_rdid_s,
+    sflash_inst_rdsr,
+    sflash_inst_wrsr,
+    sflash_inst_be,
+    sflash_inst_dp,
+    sflash_inst_rdp,
+    /* Instruction and address */
+    sflash_inst_wrlr,
+    sflash_inst_rdlr,
+    sflash_inst_read,
+    sflash_inst_potp,
+    sflash_inst_pp,
+    sflash_inst_difp,
+    sflash_inst_sse,
+    sflash_inst_se,
+    /* Instruction, address and dummy read */
+    sflash_inst_read_f,
+    sflash_inst_dofr,
+    sflash_inst_rotp
 };
 
 /* Exported constants --------------------------------------------------------*/
 /* Exported macro ------------------------------------------------------------*/
-#define SFLASH_SPI_COMMAND_SKIP 	(1)
-#define SFLASH_SPI_READ_SKIP 		(2)
+#define SFLASH_SPI_COMMAND_SKIP     (1)
+#define SFLASH_SPI_READ_SKIP        (2)
 
-#define SFLASH_INST_CODE_WREN 		(0x06)
-#define SFLASH_INST_CODE_WRDI 		(0x04)
-#define SFLASH_INST_CODE_RDID_L 	(0x9F)
-#define SFLASH_INST_CODE_RDID_S 	(0x9E)
-#define SFLASH_INST_CODE_RDSR 		(0x05)
-#define SFLASH_INST_CODE_WRSR 		(0x01)
-#define SFLASH_INST_CODE_WRLR 		(0xE5)
-#define SFLASH_INST_CODE_RDLR 		(0xE8)
-#define SFLASH_INST_CODE_READ 		(0x03)
-#define SFLASH_INST_CODE_READ_F 	(0x0B)
-#define SFLASH_INST_CODE_DOFR 		(0x3B)
-#define SFLASH_INST_CODE_ROTP 		(0x4B)
-#define SFLASH_INST_CODE_POTP 		(0x42)
-#define SFLASH_INST_CODE_PP 		(0x02)
-#define SFLASH_INST_CODE_DIFP 		(0xA2)
-#define SFLASH_INST_CODE_SSE 		(0x20)
-#define SFLASH_INST_CODE_SE 		(0xD8)
-#define SFLASH_INST_CODE_BE 		(0xC7)
-#define SFLASH_INST_CODE_DP 		(0xB9)
-#define SFLASH_INST_CODE_RDP 		(0xAB)
+#define SFLASH_INST_CODE_WREN       (0x06)
+#define SFLASH_INST_CODE_WRDI       (0x04)
+#define SFLASH_INST_CODE_RDID_L     (0x9F)
+#define SFLASH_INST_CODE_RDID_S     (0x9E)
+#define SFLASH_INST_CODE_RDSR       (0x05)
+#define SFLASH_INST_CODE_WRSR       (0x01)
+#define SFLASH_INST_CODE_WRLR       (0xE5)
+#define SFLASH_INST_CODE_RDLR       (0xE8)
+#define SFLASH_INST_CODE_READ       (0x03)
+#define SFLASH_INST_CODE_READ_F     (0x0B)
+#define SFLASH_INST_CODE_DOFR       (0x3B)
+#define SFLASH_INST_CODE_ROTP       (0x4B)
+#define SFLASH_INST_CODE_POTP       (0x42)
+#define SFLASH_INST_CODE_PP         (0x02)
+#define SFLASH_INST_CODE_DIFP       (0xA2)
+#define SFLASH_INST_CODE_SSE        (0x20)
+#define SFLASH_INST_CODE_SE         (0xD8)
+#define SFLASH_INST_CODE_BE         (0xC7)
+#define SFLASH_INST_CODE_DP         (0xB9)
+#define SFLASH_INST_CODE_RDP        (0xAB)
 
-#define SFLASH_REPLY_LEN_WREN 		(0)
-#define SFLASH_REPLY_LEN_WRDI 		(0)
-#define SFLASH_REPLY_LEN_RDID_L 	(20)
-#define SFLASH_REPLY_LEN_RDID_S 	(3)
-#define SFLASH_REPLY_LEN_RDSR 		(1)
-#define SFLASH_REPLY_LEN_WRSR 		(1)
-#define SFLASH_REPLY_LEN_WRLR 		(1)
-#define SFLASH_REPLY_LEN_RDLR 		(1)
-#define SFLASH_REPLY_LEN_READ 		(-1)
-#define SFLASH_REPLY_LEN_READ_F 	(-1)
-#define SFLASH_REPLY_LEN_DOFR 		(-1)
-#define SFLASH_REPLY_LEN_ROTP 		(65)
-#define SFLASH_REPLY_LEN_POTP 		(65)
-#define SFLASH_REPLY_LEN_PP 		(256)
-#define SFLASH_REPLY_LEN_DIFP 		(256)
-#define SFLASH_REPLY_LEN_SSE 		(0)
-#define SFLASH_REPLY_LEN_SE 		(0)
-#define SFLASH_REPLY_LEN_BE 		(0)
-#define SFLASH_REPLY_LEN_DP 		(0)
-#define SFLASH_REPLY_LEN_RDP 		(0)
+#define SFLASH_REPLY_LEN_WREN       (0)
+#define SFLASH_REPLY_LEN_WRDI       (0)
+#define SFLASH_REPLY_LEN_RDID_L     (20)
+#define SFLASH_REPLY_LEN_RDID_S     (3)
+#define SFLASH_REPLY_LEN_RDSR       (1)
+#define SFLASH_REPLY_LEN_WRSR       (1)
+#define SFLASH_REPLY_LEN_WRLR       (1)
+#define SFLASH_REPLY_LEN_RDLR       (1)
+#define SFLASH_REPLY_LEN_READ       (-1)
+#define SFLASH_REPLY_LEN_READ_F     (-1)
+#define SFLASH_REPLY_LEN_DOFR       (-1)
+#define SFLASH_REPLY_LEN_ROTP       (65)
+#define SFLASH_REPLY_LEN_POTP       (65)
+#define SFLASH_REPLY_LEN_PP         (256)
+#define SFLASH_REPLY_LEN_DIFP       (256)
+#define SFLASH_REPLY_LEN_SSE        (0)
+#define SFLASH_REPLY_LEN_SE         (0)
+#define SFLASH_REPLY_LEN_BE         (0)
+#define SFLASH_REPLY_LEN_DP         (0)
+#define SFLASH_REPLY_LEN_RDP        (0)
 
 /* Exported functions ------------------------------------------------------- */
 rt_err_t efm_spiFlash_init(void);
 rt_err_t efm_spiFlash_deinit(void);
 rt_uint32_t efm_spiFlash_cmd(
-	enum sflash_inst_type_t command,
-	rt_uint32_t address,
-	rt_uint8_t *buffer,
-	rt_uint32_t size);
+    enum sflash_inst_type_t command,
+    rt_uint32_t address,
+    rt_uint8_t *buffer,
+    rt_uint32_t size);
 
 #endif /* __DEV_SFLASH_H__ */
diff --git a/bsp/efm32/drv_acmp.c b/bsp/efm32/drv_acmp.c
index 1961fc4695..b9d24e8ebd 100644
--- a/bsp/efm32/drv_acmp.c
+++ b/bsp/efm32/drv_acmp.c
@@ -30,18 +30,18 @@
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
 #ifdef RT_ACMP_DEBUG
-#define acmp_debug(format,args...) 			rt_kprintf(format, ##args)
+#define acmp_debug(format,args...)          rt_kprintf(format, ##args)
 #else
 #define acmp_debug(format,args...)
 #endif
 
 /* Private variables ---------------------------------------------------------*/
 #ifdef RT_USING_ACMP0
-	static struct rt_device acmp0_device;
+    static struct rt_device acmp0_device;
 #endif
 
 #ifdef RT_USING_ACMP1
-	static struct rt_device acmp1_device;
+    static struct rt_device acmp1_device;
 #endif
 
 /* Private function prototypes -----------------------------------------------*/
@@ -64,169 +64,169 @@ ACMP_WarmTime_TypeDef efm32_acmp_WarmTimeCalc(rt_uint32_t hfperFreq);
  ******************************************************************************/
  static rt_err_t rt_acmp_init(rt_device_t dev)
 {
-	RT_ASSERT(dev != RT_NULL);
+    RT_ASSERT(dev != RT_NULL);
 
-	struct efm32_acmp_device_t *acmp;
+    struct efm32_acmp_device_t *acmp;
 
-	acmp = (struct efm32_acmp_device_t *)(dev->user_data);
+    acmp = (struct efm32_acmp_device_t *)(dev->user_data);
 
-	acmp->hook.cbFunc 	= RT_NULL;
-	acmp->hook.userPtr 	= RT_NULL;
+    acmp->hook.cbFunc   = RT_NULL;
+    acmp->hook.userPtr  = RT_NULL;
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 /***************************************************************************//**
  * @brief
- *	Configure ACMP device
+ *  Configure ACMP device
  *
  * @details
  *
  * @note
  *
  * @param[in] dev
- *	Pointer to device descriptor
+ *  Pointer to device descriptor
  *
  * @param[in] cmd
- *	ACMP control command
+ *  ACMP control command
  *
  * @param[in] args
- *	Arguments
+ *  Arguments
  *
  * @return
- *	Error code
+ *  Error code
  ******************************************************************************/
 static rt_err_t rt_acmp_control(
-	rt_device_t 	dev,
-	rt_uint8_t 		cmd,
-	void 			*args)
+    rt_device_t     dev,
+    rt_uint8_t      cmd,
+    void            *args)
 {
-	RT_ASSERT(dev != RT_NULL);
+    RT_ASSERT(dev != RT_NULL);
 
-	struct efm32_acmp_device_t *acmp;
+    struct efm32_acmp_device_t *acmp;
 
-	acmp = (struct efm32_acmp_device_t *)(dev->user_data);
+    acmp = (struct efm32_acmp_device_t *)(dev->user_data);
 
-	switch (cmd)
-	{
-	case RT_DEVICE_CTRL_SUSPEND:
-		/* Suspend device */
-		dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
-		ACMP_Disable(acmp->acmp_device);
-		break;
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_SUSPEND:
+        /* Suspend device */
+        dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
+        ACMP_Disable(acmp->acmp_device);
+        break;
 
-	case RT_DEVICE_CTRL_RESUME:
-		/* Resume device */
-		dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
-		ACMP_Enable(acmp->acmp_device);
-		break;
+    case RT_DEVICE_CTRL_RESUME:
+        /* Resume device */
+        dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
+        ACMP_Enable(acmp->acmp_device);
+        break;
 
-	case RT_DEVICE_CTRL_ACMP_INIT:
-		{
-			rt_bool_t int_en = false;
-			struct efm32_acmp_control_t *control;
+    case RT_DEVICE_CTRL_ACMP_INIT:
+        {
+            rt_bool_t int_en = false;
+            struct efm32_acmp_control_t *control;
 
-			control = (struct efm32_acmp_control_t *)args;
-			acmp_debug("ACMP: control -> init start\n");
+            control = (struct efm32_acmp_control_t *)args;
+            acmp_debug("ACMP: control -> init start\n");
 
-			/* Configure ACMPn */
-			if (control->init == RT_NULL)
-			{
-				return -RT_ERROR;
-			}
-			ACMP_Init(acmp->acmp_device, control->init);
-			ACMP_ChannelSet(acmp->acmp_device, control->negInput, control->posInput);
-			if (control->output != RT_NULL)
-			{
-				ACMP_GPIOSetup(
-					acmp->acmp_device,
-					control->output->location,
-					control->output->enable,
-					control->output->invert);
-				int_en = true;
-			}
-			if (control->hook.cbFunc != RT_NULL)
-			{
-				acmp->hook.cbFunc = control->hook.cbFunc;
-				acmp->hook.userPtr = control->hook.userPtr;
-				int_en = true;
-			}
+            /* Configure ACMPn */
+            if (control->init == RT_NULL)
+            {
+                return -RT_ERROR;
+            }
+            ACMP_Init(acmp->acmp_device, control->init);
+            ACMP_ChannelSet(acmp->acmp_device, control->negInput, control->posInput);
+            if (control->output != RT_NULL)
+            {
+                ACMP_GPIOSetup(
+                    acmp->acmp_device,
+                    control->output->location,
+                    control->output->enable,
+                    control->output->invert);
+                int_en = true;
+            }
+            if (control->hook.cbFunc != RT_NULL)
+            {
+                acmp->hook.cbFunc = control->hook.cbFunc;
+                acmp->hook.userPtr = control->hook.userPtr;
+                int_en = true;
+            }
 
-			if (int_en)
-			{
-				/* Enable edge interrupt */
-				ACMP_IntEnable(acmp->acmp_device, ACMP_IEN_EDGE);
-				ACMP_IntClear(acmp->acmp_device, ACMP_IFC_EDGE);
+            if (int_en)
+            {
+                /* Enable edge interrupt */
+                ACMP_IntEnable(acmp->acmp_device, ACMP_IEN_EDGE);
+                ACMP_IntClear(acmp->acmp_device, ACMP_IFC_EDGE);
 
-				/* Enable ACMP0/1 interrupt vector in NVIC */
-				NVIC_ClearPendingIRQ(ACMP0_IRQn);
-				NVIC_SetPriority(ACMP0_IRQn, EFM32_IRQ_PRI_DEFAULT);
-				NVIC_EnableIRQ(ACMP0_IRQn);
-			}
-		}
-		break;
+                /* Enable ACMP0/1 interrupt vector in NVIC */
+                NVIC_ClearPendingIRQ(ACMP0_IRQn);
+                NVIC_SetPriority(ACMP0_IRQn, EFM32_IRQ_PRI_DEFAULT);
+                NVIC_EnableIRQ(ACMP0_IRQn);
+            }
+        }
+        break;
 
-	case RT_DEVICE_CTRL_ACMP_OUTPUT:
-		*((rt_bool_t *)args) = \
-			(acmp->acmp_device->STATUS & ACMP_STATUS_ACMPOUT) ? true : false;
-		break;
+    case RT_DEVICE_CTRL_ACMP_OUTPUT:
+        *((rt_bool_t *)args) = \
+            (acmp->acmp_device->STATUS & ACMP_STATUS_ACMPOUT) ? true : false;
+        break;
 
-		default:
-			return -RT_ERROR;
-	}
+        default:
+            return -RT_ERROR;
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 /***************************************************************************//**
  * @brief
- *	Register ACMP device
+ *  Register ACMP device
  *
  * @details
  *
  * @note
  *
  * @param[in] device
- *	Pointer to device descriptor
+ *  Pointer to device descriptor
  *
  * @param[in] name
- *	Device name
+ *  Device name
  *
  * @param[in] flag
- *	Configuration flags
+ *  Configuration flags
  *
  * @param[in] acmp
- *	Pointer to ACMP device descriptor
+ *  Pointer to ACMP device descriptor
  *
  * @return
- *	Error code
+ *  Error code
  ******************************************************************************/
 rt_err_t rt_hw_acmp_register(
-	rt_device_t		device,
-	const char		*name,
-	rt_uint32_t		flag,
-	struct efm32_acmp_device_t *acmp)
+    rt_device_t     device,
+    const char      *name,
+    rt_uint32_t     flag,
+    struct efm32_acmp_device_t *acmp)
 {
-	RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(device != RT_NULL);
 
-	device->type 		= RT_Device_Class_Char; /* fixme: should be acmp type */
-	device->rx_indicate = RT_NULL;
-	device->tx_complete = RT_NULL;
-	device->init 		= rt_acmp_init;
-	device->open		= RT_NULL;
-	device->close		= RT_NULL;
-	device->read 		= RT_NULL;
-	device->write 		= RT_NULL;
-	device->control 	= rt_acmp_control;
-	device->user_data	= acmp;
+    device->type        = RT_Device_Class_Char; /* fixme: should be acmp type */
+    device->rx_indicate = RT_NULL;
+    device->tx_complete = RT_NULL;
+    device->init        = rt_acmp_init;
+    device->open        = RT_NULL;
+    device->close       = RT_NULL;
+    device->read        = RT_NULL;
+    device->write       = RT_NULL;
+    device->control     = rt_acmp_control;
+    device->user_data   = acmp;
 
-	/* register a character device */
-	return rt_device_register(device, name, flag);
+    /* register a character device */
+    return rt_device_register(device, name, flag);
 }
 
 /***************************************************************************//**
  * @brief
- *	ACMP edge trigger interrupt handler
+ *  ACMP edge trigger interrupt handler
  *
  * @details
  *
@@ -234,96 +234,96 @@ rt_err_t rt_hw_acmp_register(
  ******************************************************************************/
 void rt_hw_acmp_isr(rt_device_t dev)
 {
-	RT_ASSERT(dev != RT_NULL);
+    RT_ASSERT(dev != RT_NULL);
 
-	struct efm32_acmp_device_t *acmp;
+    struct efm32_acmp_device_t *acmp;
 
-	acmp = (struct efm32_acmp_device_t *)(dev->user_data);
+    acmp = (struct efm32_acmp_device_t *)(dev->user_data);
 
-	if (acmp->hook.cbFunc != RT_NULL)
-	{
-		(acmp->hook.cbFunc)(acmp->hook.userPtr);
-	}
+    if (acmp->hook.cbFunc != RT_NULL)
+    {
+        (acmp->hook.cbFunc)(acmp->hook.userPtr);
+    }
 }
 
 /***************************************************************************//**
  * @brief
- *	Initialize the specified ACMP unit
+ *  Initialize the specified ACMP unit
  *
  * @details
  *
  * @note
  *
  * @param[in] device
- *	Pointer to device descriptor
+ *  Pointer to device descriptor
  *
  * @param[in] unitNumber
- *	Unit number
+ *  Unit number
  *
  * @return
- *	Pointer to ACMP device
+ *  Pointer to ACMP device
  ******************************************************************************/
 static struct efm32_acmp_device_t *rt_hw_acmp_unit_init(
-	rt_device_t device,
-	rt_uint8_t 	unitNumber)
+    rt_device_t device,
+    rt_uint8_t  unitNumber)
 {
-	struct efm32_acmp_device_t 		*acmp;
-	efm32_irq_hook_init_t			hook;
-	CMU_Clock_TypeDef				acmpClock;
+    struct efm32_acmp_device_t      *acmp;
+    efm32_irq_hook_init_t           hook;
+    CMU_Clock_TypeDef               acmpClock;
 
-	do
-	{
-		/* Allocate device */
-		acmp = rt_malloc(sizeof(struct efm32_acmp_device_t));
-		if (acmp == RT_NULL)
-		{
-			acmp_debug("ACMP err: no mem for ACMP%d\n", unitNumber);
-			break;
-		}
+    do
+    {
+        /* Allocate device */
+        acmp = rt_malloc(sizeof(struct efm32_acmp_device_t));
+        if (acmp == RT_NULL)
+        {
+            acmp_debug("ACMP err: no mem for ACMP%d\n", unitNumber);
+            break;
+        }
 
-		/* Initialization */
-		if (unitNumber >= ACMP_COUNT)
-		{
-			break;
-		}
-		switch (unitNumber)
-		{
-		case 0:
-			acmp->acmp_device	= ACMP0;
-			acmpClock 			= (CMU_Clock_TypeDef)cmuClock_ACMP0;
-			break;
+        /* Initialization */
+        if (unitNumber >= ACMP_COUNT)
+        {
+            break;
+        }
+        switch (unitNumber)
+        {
+        case 0:
+            acmp->acmp_device   = ACMP0;
+            acmpClock           = (CMU_Clock_TypeDef)cmuClock_ACMP0;
+            break;
 
-		case 1:
-			acmp->acmp_device	= ACMP1;
-			acmpClock 			= (CMU_Clock_TypeDef)cmuClock_ACMP1;
-			break;
+        case 1:
+            acmp->acmp_device   = ACMP1;
+            acmpClock           = (CMU_Clock_TypeDef)cmuClock_ACMP1;
+            break;
 
-		default:
-			break;
-		}
+        default:
+            break;
+        }
 
-		/* Enable ACMP clock */
-		CMU_ClockEnable(acmpClock, true);
+        /* Enable ACMP clock */
+        CMU_ClockEnable(acmpClock, true);
 
-		/* Reset */
-		ACMP_Reset(acmp->acmp_device);
+        /* Reset */
+        ACMP_Reset(acmp->acmp_device);
 
-		/* Config interrupt and NVIC */
-		hook.type			= efm32_irq_type_acmp;
-		hook.unit			= unitNumber;
-		hook.cbFunc 		= rt_hw_acmp_isr;
-		hook.userPtr		= device;
-		efm32_irq_hook_register(&hook);
+        /* Config interrupt and NVIC */
+        hook.type           = efm32_irq_type_acmp;
+        hook.unit           = unitNumber;
+        hook.cbFunc         = rt_hw_acmp_isr;
+        hook.userPtr        = device;
+        efm32_irq_hook_register(&hook);
 
-		return acmp;
-	} while(0);
+        return acmp;
+    } while(0);
 
-	if (acmp)
-	{
-		rt_free(acmp);
-	}
-	rt_kprintf("ACMP: Init failed!\n");
-	return RT_NULL;
+    if (acmp)
+    {
+        rt_free(acmp);
+    }
+    rt_kprintf("ACMP: Init failed!\n");
+    return RT_NULL;
 }
 
 /***************************************************************************//**
@@ -338,20 +338,20 @@ static struct efm32_acmp_device_t *rt_hw_acmp_unit_init(
  ******************************************************************************/
 void rt_hw_acmp_init(void)
 {
-	struct efm32_acmp_device_t 	*acmp;
+    struct efm32_acmp_device_t  *acmp;
 
 #ifdef RT_USING_ACMP0
-	if ((acmp = rt_hw_acmp_unit_init(&acmp0_device, 0)) != RT_NULL)
-	{
-		rt_hw_acmp_register(&acmp0_device, RT_ACMP0_NAME, EFM32_NO_DATA, acmp);
-	}
+    if ((acmp = rt_hw_acmp_unit_init(&acmp0_device, 0)) != RT_NULL)
+    {
+        rt_hw_acmp_register(&acmp0_device, RT_ACMP0_NAME, EFM32_NO_DATA, acmp);
+    }
 #endif
 
 #ifdef RT_USING_ACMP1
-	if ((acmp = rt_hw_acmp_unit_init(&acmp1_device, 1)) != RT_NULL)
-	{
-		rt_hw_acmp_register(&acmp1_device, RT_ACMP1_NAME, EFM32_NO_DATA, acmp);
-	}
+    if ((acmp = rt_hw_acmp_unit_init(&acmp1_device, 1)) != RT_NULL)
+    {
+        rt_hw_acmp_register(&acmp1_device, RT_ACMP1_NAME, EFM32_NO_DATA, acmp);
+    }
 #endif
 
 }
@@ -369,50 +369,50 @@ void rt_hw_acmp_init(void)
  ******************************************************************************/
 ACMP_WarmTime_TypeDef efm32_acmp_WarmTimeCalc(rt_uint32_t hfperFreq)
 {
-	if (!hfperFreq)
-	{
-		hfperFreq = CMU_ClockFreqGet(cmuClock_HFPER);
+    if (!hfperFreq)
+    {
+        hfperFreq = CMU_ClockFreqGet(cmuClock_HFPER);
 
-		/* Just in case, make sure we get non-zero freq for below calculation */
-		if (!hfperFreq)
-		{
-		  hfperFreq = 1;
-		}
-	}
+        /* Just in case, make sure we get non-zero freq for below calculation */
+        if (!hfperFreq)
+        {
+          hfperFreq = 1;
+        }
+    }
 
-	/* Determine number of HFPERCLK cycle >= 10us */
-	if (4 * 1000000 / hfperFreq > 10)
-	{
-		return acmpWarmTime4;
-	}
-	else if (8 * 1000000 / hfperFreq > 10)
-	{
-		return acmpWarmTime8;
-	}
-	else if (16 * 1000000 / hfperFreq > 10)
-	{
-		return acmpWarmTime16;
-	}
-	else if (32 * 1000000 / hfperFreq > 10)
-	{
-		return acmpWarmTime32;
-	}
-	else if (64 * 1000000 / hfperFreq > 10)
-	{
-		return acmpWarmTime64;
-	}
-	else if (128 * 1000000 / hfperFreq > 10)
-	{
-		return acmpWarmTime128;
-	}
-	else if (256 * 1000000 / hfperFreq > 10)
-	{
-		return acmpWarmTime256;
-	}
-	else if (512 * 1000000 / hfperFreq > 10)
-	{
-		return acmpWarmTime512;
-	}
+    /* Determine number of HFPERCLK cycle >= 10us */
+    if (4 * 1000000 / hfperFreq > 10)
+    {
+        return acmpWarmTime4;
+    }
+    else if (8 * 1000000 / hfperFreq > 10)
+    {
+        return acmpWarmTime8;
+    }
+    else if (16 * 1000000 / hfperFreq > 10)
+    {
+        return acmpWarmTime16;
+    }
+    else if (32 * 1000000 / hfperFreq > 10)
+    {
+        return acmpWarmTime32;
+    }
+    else if (64 * 1000000 / hfperFreq > 10)
+    {
+        return acmpWarmTime64;
+    }
+    else if (128 * 1000000 / hfperFreq > 10)
+    {
+        return acmpWarmTime128;
+    }
+    else if (256 * 1000000 / hfperFreq > 10)
+    {
+        return acmpWarmTime256;
+    }
+    else if (512 * 1000000 / hfperFreq > 10)
+    {
+        return acmpWarmTime512;
+    }
 }
 
 #endif
diff --git a/bsp/efm32/drv_acmp.h b/bsp/efm32/drv_acmp.h
index 50b4738afc..fd7f858669 100644
--- a/bsp/efm32/drv_acmp.h
+++ b/bsp/efm32/drv_acmp.h
@@ -23,24 +23,24 @@
 /* Exported types ------------------------------------------------------------*/
 struct efm32_acmp_device_t
 {
-	ACMP_TypeDef 		*acmp_device;
-	efm32_irq_hook_t 	hook;
+    ACMP_TypeDef        *acmp_device;
+    efm32_irq_hook_t    hook;
 };
 
 struct efm32_acmp_output_t
 {
-	rt_uint32_t 		location;
-	rt_bool_t 			enable;
-	rt_bool_t 			invert;
+    rt_uint32_t         location;
+    rt_bool_t           enable;
+    rt_bool_t           invert;
 };
 
 struct efm32_acmp_control_t
 {
-	ACMP_Init_TypeDef			*init;
-	ACMP_Channel_TypeDef		posInput;
-	ACMP_Channel_TypeDef		negInput;
-	struct efm32_acmp_output_t 	*output;
-	efm32_irq_hook_t 			hook;
+    ACMP_Init_TypeDef           *init;
+    ACMP_Channel_TypeDef        posInput;
+    ACMP_Channel_TypeDef        negInput;
+    struct efm32_acmp_output_t  *output;
+    efm32_irq_hook_t            hook;
 };
 
 /* Exported constants --------------------------------------------------------*/
diff --git a/bsp/efm32/drv_adc.c b/bsp/efm32/drv_adc.c
index e1eeafb36e..2a072507e0 100644
--- a/bsp/efm32/drv_adc.c
+++ b/bsp/efm32/drv_adc.c
@@ -1,8 +1,8 @@
 /***************************************************************************//**
- * @file 	drv_adc.c
- * @brief 	ADC driver of RT-Thread RTOS for EFM32
+ * @file    drv_adc.c
+ * @brief   ADC driver of RT-Thread RTOS for EFM32
  *  COPYRIGHT (C) 2012, RT-Thread Development Team
- * @author 	onelife
+ * @author  onelife
  * @version 1.0
  *******************************************************************************
  * @section License
@@ -10,9 +10,9 @@
  * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
  *******************************************************************************
  * @section Change Logs
- * Date			Author		Notes
- * 2011-02-21	onelife		Initial creation for EFM32
- * 2011-07-14	onelife		Add multiple channels support for scan mode
+ * Date         Author      Notes
+ * 2011-02-21   onelife     Initial creation for EFM32
+ * 2011-07-14   onelife     Add multiple channels support for scan mode
  ******************************************************************************/
 
 /***************************************************************************//**
@@ -29,7 +29,7 @@
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
 #ifdef RT_ADC_DEBUG
-#define adc_debug(format,args...) 			rt_kprintf(format, ##args)
+#define adc_debug(format,args...)           rt_kprintf(format, ##args)
 #else
 #define adc_debug(format,args...)
 #endif
@@ -71,132 +71,132 @@ static rt_uint32_t adcErrataShift = 0;
  *   No need to load the calibration values after the function returns.
  ******************************************************************************/
 rt_uint32_t efm32_adc_calibration(
-	ADC_TypeDef 			*adc,
-	ADC_Ref_TypeDef			ref,
-	ADC_SingleInput_TypeDef	input)
+    ADC_TypeDef             *adc,
+    ADC_Ref_TypeDef         ref,
+    ADC_SingleInput_TypeDef input)
 {
-	rt_uint32_t 	cal;
-	rt_int32_t 		sample;
-	rt_int8_t 		high, mid, low, tmp;
-	ADC_InitSingle_TypeDef singleInit 	= ADC_INITSINGLE_DEFAULT;
+    rt_uint32_t     cal;
+    rt_int32_t      sample;
+    rt_int8_t       high, mid, low, tmp;
+    ADC_InitSingle_TypeDef singleInit   = ADC_INITSINGLE_DEFAULT;
 
-	/* Init for single conversion use, measure diff 0 with selected reference. */
-	singleInit.reference 	= ref;
-	singleInit.input 		= adcSingleInpDiff0;
-	singleInit.acqTime 		= adcAcqTime32;
-	singleInit.diff 		= true;
-	/* Enable oversampling rate */
-	singleInit.resolution	= adcResOVS;
-	ADC_InitSingle(adc, &singleInit);
+    /* Init for single conversion use, measure diff 0 with selected reference. */
+    singleInit.reference    = ref;
+    singleInit.input        = adcSingleInpDiff0;
+    singleInit.acqTime      = adcAcqTime32;
+    singleInit.diff         = true;
+    /* Enable oversampling rate */
+    singleInit.resolution   = adcResOVS;
+    ADC_InitSingle(adc, &singleInit);
 
-	/* ADC is now set up for offset calibration */
-	/* Offset calibration register is a 7 bit signed 2's complement value. */
-	/* Use unsigned indexes for binary search, and convert when calibration */
-	/* register is written to. */
-	high = 63;
-	low = -64;
+    /* ADC is now set up for offset calibration */
+    /* Offset calibration register is a 7 bit signed 2's complement value. */
+    /* Use unsigned indexes for binary search, and convert when calibration */
+    /* register is written to. */
+    high = 63;
+    low = -64;
 
-	/* Do binary search for offset calibration*/
-	while (low < high)
-	{
-		/* Calculate midpoint */
-		mid = low + (high - low) / 2;
+    /* Do binary search for offset calibration*/
+    while (low < high)
+    {
+        /* Calculate midpoint */
+        mid = low + (high - low) / 2;
 
-		/* Midpoint is converted to 2's complement and written to both scan and */
-		/* single calibration registers */
-		cal = adc->CAL & ~(_ADC_CAL_SINGLEOFFSET_MASK | _ADC_CAL_SCANOFFSET_MASK);
-		tmp = mid < 0 ? (((mid & 0x3F) ^ 0x3F) | 0x40) + 1 : mid;
-		cal |= tmp << _ADC_CAL_SINGLEOFFSET_SHIFT;
-		cal |= tmp << _ADC_CAL_SCANOFFSET_SHIFT;
-		adc_debug("adc->CAL = %x, cal = %x, tmp = %x\n", adc->CAL, cal, tmp);
-		adc->CAL = cal;
+        /* Midpoint is converted to 2's complement and written to both scan and */
+        /* single calibration registers */
+        cal = adc->CAL & ~(_ADC_CAL_SINGLEOFFSET_MASK | _ADC_CAL_SCANOFFSET_MASK);
+        tmp = mid < 0 ? (((mid & 0x3F) ^ 0x3F) | 0x40) + 1 : mid;
+        cal |= tmp << _ADC_CAL_SINGLEOFFSET_SHIFT;
+        cal |= tmp << _ADC_CAL_SCANOFFSET_SHIFT;
+        adc_debug("adc->CAL = %x, cal = %x, tmp = %x\n", adc->CAL, cal, tmp);
+        adc->CAL = cal;
 
-		/* Do a conversion */
-		ADC_Start(adc, adcStartSingle);
+        /* Do a conversion */
+        ADC_Start(adc, adcStartSingle);
 
-		/* Wait while conversion is active */
-		while (adc->STATUS & ADC_STATUS_SINGLEACT) ;
+        /* Wait while conversion is active */
+        while (adc->STATUS & ADC_STATUS_SINGLEACT) ;
 
-		/* Get ADC result */
-		sample = ADC_DataSingleGet(adc);
+        /* Get ADC result */
+        sample = ADC_DataSingleGet(adc);
 
-		/* Check result and decide in which part of to repeat search */
-		/* Calibration register has negative effect on result */
-		if (sample < 0)
-		{
-			/* Repeat search in bottom half. */
-			high = mid;
-		}
-		else if (sample > 0)
-		{
-			/* Repeat search in top half. */
-			low = mid + 1;
-		}
-		else
-		{
-			/* Found it, exit while loop */
-			break;
-		}
-	}
-	adc_debug("adc->CAL = %x\n", adc->CAL);
+        /* Check result and decide in which part of to repeat search */
+        /* Calibration register has negative effect on result */
+        if (sample < 0)
+        {
+            /* Repeat search in bottom half. */
+            high = mid;
+        }
+        else if (sample > 0)
+        {
+            /* Repeat search in top half. */
+            low = mid + 1;
+        }
+        else
+        {
+            /* Found it, exit while loop */
+            break;
+        }
+    }
+    adc_debug("adc->CAL = %x\n", adc->CAL);
 
-	/* Now do gain calibration, only input and diff settings needs to be changed */
-	adc->SINGLECTRL &= ~(_ADC_SINGLECTRL_INPUTSEL_MASK | _ADC_SINGLECTRL_DIFF_MASK);
-	adc->SINGLECTRL |= (input << _ADC_SINGLECTRL_INPUTSEL_SHIFT);
-	adc->SINGLECTRL |= (false << _ADC_SINGLECTRL_DIFF_SHIFT);
+    /* Now do gain calibration, only input and diff settings needs to be changed */
+    adc->SINGLECTRL &= ~(_ADC_SINGLECTRL_INPUTSEL_MASK | _ADC_SINGLECTRL_DIFF_MASK);
+    adc->SINGLECTRL |= (input << _ADC_SINGLECTRL_INPUTSEL_SHIFT);
+    adc->SINGLECTRL |= (false << _ADC_SINGLECTRL_DIFF_SHIFT);
 
-	/* ADC is now set up for gain calibration */
-	/* Gain calibration register is a 7 bit unsigned value. */
-	high = 127;
-	low = 0;
+    /* ADC is now set up for gain calibration */
+    /* Gain calibration register is a 7 bit unsigned value. */
+    high = 127;
+    low = 0;
 
-	/* Do binary search for gain calibration */
-	while (low < high)
-	{
-		/* Calculate midpoint and write to calibration register */
-		mid = low + (high - low) / 2;
+    /* Do binary search for gain calibration */
+    while (low < high)
+    {
+        /* Calculate midpoint and write to calibration register */
+        mid = low + (high - low) / 2;
 
-		/* Midpoint is converted to 2's complement */
-		cal      = adc->CAL & ~(_ADC_CAL_SINGLEGAIN_MASK | _ADC_CAL_SCANGAIN_MASK);
-		cal     |= mid << _ADC_CAL_SINGLEGAIN_SHIFT;
-		cal     |= mid << _ADC_CAL_SCANGAIN_SHIFT;
-		adc_debug("adc->CAL = %x, cal = %x, mid = %x\n", adc->CAL, cal, mid);
-		adc->CAL = cal;
+        /* Midpoint is converted to 2's complement */
+        cal      = adc->CAL & ~(_ADC_CAL_SINGLEGAIN_MASK | _ADC_CAL_SCANGAIN_MASK);
+        cal     |= mid << _ADC_CAL_SINGLEGAIN_SHIFT;
+        cal     |= mid << _ADC_CAL_SCANGAIN_SHIFT;
+        adc_debug("adc->CAL = %x, cal = %x, mid = %x\n", adc->CAL, cal, mid);
+        adc->CAL = cal;
 
-		/* Do a conversion */
-		ADC_Start(adc, adcStartSingle);
+        /* Do a conversion */
+        ADC_Start(adc, adcStartSingle);
 
-		/* Wait while conversion is active */
-		while (adc->STATUS & ADC_STATUS_SINGLEACT) ;
+        /* Wait while conversion is active */
+        while (adc->STATUS & ADC_STATUS_SINGLEACT) ;
 
-		/* Get ADC result */
-		sample = ADC_DataSingleGet(adc);
+        /* Get ADC result */
+        sample = ADC_DataSingleGet(adc);
 
-		/* Check result and decide in which part to repeat search */
-		/* Compare with a value atleast one LSB's less than top to avoid overshooting */
-		/* Since oversampling is used, the result is 16 bits, but a couple of lsb's */
-		/* applies to the 12 bit result value, if 0xffe is the top value in 12 bit, this */
-		/* is in turn 0xffe0 in the 16 bit result. */
-		/* Calibration register has positive effect on result */
-		if (sample > 0xffd0)
-		{
-		  /* Repeat search in bottom half. */
-		  high = mid;
-		}
-		else if (sample < 0xffd0)
-		{
-		  /* Repeat search in top half. */
-		  low = mid + 1;
-		}
-		else
-		{
-		  /* Found it, exit while loop */
-		  break;
-		}
-	}
-	adc_debug("adc->CAL = %x\n", adc->CAL);
+        /* Check result and decide in which part to repeat search */
+        /* Compare with a value atleast one LSB's less than top to avoid overshooting */
+        /* Since oversampling is used, the result is 16 bits, but a couple of lsb's */
+        /* applies to the 12 bit result value, if 0xffe is the top value in 12 bit, this */
+        /* is in turn 0xffe0 in the 16 bit result. */
+        /* Calibration register has positive effect on result */
+        if (sample > 0xffd0)
+        {
+          /* Repeat search in bottom half. */
+          high = mid;
+        }
+        else if (sample < 0xffd0)
+        {
+          /* Repeat search in top half. */
+          low = mid + 1;
+        }
+        else
+        {
+          /* Found it, exit while loop */
+          break;
+        }
+    }
+    adc_debug("adc->CAL = %x\n", adc->CAL);
 
-	return adc->CAL;
+    return adc->CAL;
 }
 
 /***************************************************************************//**
@@ -217,52 +217,52 @@ rt_uint32_t efm32_adc_calibration(
  *   DMA channel
  ******************************************************************************/
 void efm32_adc_cfg_dma(
-		ADC_TypeDef 			*adc_device,
-		rt_uint8_t 				mode,
-		rt_uint8_t 				channel)
+        ADC_TypeDef             *adc_device,
+        rt_uint8_t              mode,
+        rt_uint8_t              channel)
 {
-	DMA_CfgChannel_TypeDef	chnlCfg;
-	DMA_CfgDescr_TypeDef	descrCfg;
+    DMA_CfgChannel_TypeDef  chnlCfg;
+    DMA_CfgDescr_TypeDef    descrCfg;
 
-	if (channel == (rt_uint8_t)EFM32_NO_DMA)
-	{
-		return;
-	}
+    if (channel == (rt_uint8_t)EFM32_NO_DMA)
+    {
+        return;
+    }
 
-	/* Set up DMA channel */
-	chnlCfg.highPri 	= false;
-	chnlCfg.enableInt	= false;
-	if (adc_device == ADC0)
-	{
-		switch (mode & ADC_MASK_MODE)
-		{
-		case ADC_MODE_SINGLE:
-			chnlCfg.select = DMAREQ_ADC0_SINGLE;
-			break;
+    /* Set up DMA channel */
+    chnlCfg.highPri     = false;
+    chnlCfg.enableInt   = false;
+    if (adc_device == ADC0)
+    {
+        switch (mode & ADC_MASK_MODE)
+        {
+        case ADC_MODE_SINGLE:
+            chnlCfg.select = DMAREQ_ADC0_SINGLE;
+            break;
 
-		case ADC_MODE_SCAN:
-			chnlCfg.select = DMAREQ_ADC0_SCAN;
-			break;
+        case ADC_MODE_SCAN:
+            chnlCfg.select = DMAREQ_ADC0_SCAN;
+            break;
 
-		default:
-			return;
-		}
-	}
-	else
-	{
-		// TODO: Any other channel?
-		return;
-	}
-	chnlCfg.cb			= RT_NULL;
-	DMA_CfgChannel((rt_uint32_t)channel, &chnlCfg);
+        default:
+            return;
+        }
+    }
+    else
+    {
+        // TODO: Any other channel?
+        return;
+    }
+    chnlCfg.cb          = RT_NULL;
+    DMA_CfgChannel((rt_uint32_t)channel, &chnlCfg);
 
-	/* Setting up DMA channel descriptor */
-	descrCfg.dstInc 	= dmaDataInc4;
-	descrCfg.srcInc 	= dmaDataIncNone;
-	descrCfg.size		= dmaDataSize4;
-	descrCfg.arbRate	= dmaArbitrate1;
-	descrCfg.hprot		= 0;
-	DMA_CfgDescr((rt_uint32_t)channel, true, &descrCfg);
+    /* Setting up DMA channel descriptor */
+    descrCfg.dstInc     = dmaDataInc4;
+    descrCfg.srcInc     = dmaDataIncNone;
+    descrCfg.size       = dmaDataSize4;
+    descrCfg.arbRate    = dmaArbitrate1;
+    descrCfg.hprot      = 0;
+    DMA_CfgDescr((rt_uint32_t)channel, true, &descrCfg);
 }
 
 /***************************************************************************//**
@@ -289,38 +289,38 @@ void efm32_adc_cfg_dma(
  *   Pointer to ADC results buffer
  ******************************************************************************/
 void efm32_adc_on_dma(
-		ADC_TypeDef 			*adc_device,
-		rt_uint8_t 				mode,
-		rt_uint8_t 				count,
-		rt_uint8_t 				channel,
-		void 					*buffer)
+        ADC_TypeDef             *adc_device,
+        rt_uint8_t              mode,
+        rt_uint8_t              count,
+        rt_uint8_t              channel,
+        void                    *buffer)
 {
-	switch (mode & ADC_MASK_MODE)
-	{
-	case ADC_MODE_SINGLE:
-		/* Activate DMA */
-		DMA_ActivateBasic(
-			(rt_uint32_t)channel,
-			true,
-			false,
-			buffer,
-			(void *)&(adc_device->SINGLEDATA),
-			count - 1);
-		break;
+    switch (mode & ADC_MASK_MODE)
+    {
+    case ADC_MODE_SINGLE:
+        /* Activate DMA */
+        DMA_ActivateBasic(
+            (rt_uint32_t)channel,
+            true,
+            false,
+            buffer,
+            (void *)&(adc_device->SINGLEDATA),
+            count - 1);
+        break;
 
-	case ADC_MODE_SCAN:
-		DMA_ActivateBasic(
-			(rt_uint32_t)channel,
-			true,
-			false,
-			buffer,
-			(void *)&(adc_device->SCANDATA),
-			count - 1);
-		break;
+    case ADC_MODE_SCAN:
+        DMA_ActivateBasic(
+            (rt_uint32_t)channel,
+            true,
+            false,
+            buffer,
+            (void *)&(adc_device->SCANDATA),
+            count - 1);
+        break;
 
-	default:
-		return;
-	}
+    default:
+        return;
+    }
 }
 
 /***************************************************************************//**
@@ -339,468 +339,468 @@ void efm32_adc_on_dma(
  ******************************************************************************/
  static rt_err_t rt_adc_init(rt_device_t dev)
 {
-	RT_ASSERT(dev != RT_NULL);
+    RT_ASSERT(dev != RT_NULL);
 
-	rt_uint32_t temp;
+    rt_uint32_t temp;
 
-	struct efm32_adc_device_t *adc;
+    struct efm32_adc_device_t *adc;
 
-	adc = (struct efm32_adc_device_t *)(dev->user_data);
+    adc = (struct efm32_adc_device_t *)(dev->user_data);
 
-	temp = efm32_adc_calibration(adc->adc_device, ADC_CALI_REF, ADC_CALI_CH);
+    temp = efm32_adc_calibration(adc->adc_device, ADC_CALI_REF, ADC_CALI_CH);
 
-	adc_debug("adc->CAL = %x\n", temp);
-	return RT_EOK;
+    adc_debug("adc->CAL = %x\n", temp);
+    return RT_EOK;
 }
 
 /***************************************************************************//**
  * @brief
- *	Configure ADC device
+ *  Configure ADC device
  *
  * @details
  *
  * @note
  *
  * @param[in] dev
- *	Pointer to device descriptor
+ *  Pointer to device descriptor
  *
  * @param[in] cmd
- *	ADC control command
+ *  ADC control command
  *
  * @param[in] args
- *	Arguments
+ *  Arguments
  *
  * @return
- *	Error code
+ *  Error code
  ******************************************************************************/
 static rt_err_t rt_adc_control(
-	rt_device_t 	dev,
-	rt_uint8_t 		cmd,
-	void 			*args)
+    rt_device_t     dev,
+    rt_uint8_t      cmd,
+    void            *args)
 {
-	RT_ASSERT(dev != RT_NULL);
+    RT_ASSERT(dev != RT_NULL);
 
-	struct efm32_adc_device_t *adc;
+    struct efm32_adc_device_t *adc;
 
-	adc = (struct efm32_adc_device_t *)(dev->user_data);
+    adc = (struct efm32_adc_device_t *)(dev->user_data);
 
-	switch (cmd)
-	{
-	case RT_DEVICE_CTRL_SUSPEND:
-		/* Suspend device */
-		dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
-		adc->adc_device->CMD = ADC_CMD_SINGLESTOP | ADC_CMD_SCANSTOP;
-		break;
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_SUSPEND:
+        /* Suspend device */
+        dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
+        adc->adc_device->CMD = ADC_CMD_SINGLESTOP | ADC_CMD_SCANSTOP;
+        break;
 
-	case RT_DEVICE_CTRL_RESUME:
-		{
-			/* Resume device */
-			struct efm32_adc_result_t *control = \
-				(struct efm32_adc_result_t *)args;
+    case RT_DEVICE_CTRL_RESUME:
+        {
+            /* Resume device */
+            struct efm32_adc_result_t *control = \
+                (struct efm32_adc_result_t *)args;
 
-			dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
+            dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
 
-			switch (control->mode)
-			{
-			case ADC_MODE_SINGLE:
-				if (adc->singleDmaChannel != (rt_uint8_t)EFM32_NO_DMA)
-				{
-					efm32_adc_on_dma(
-						adc->adc_device,
-						control->mode,
-						adc->singleCount,
-						adc->singleDmaChannel,
-						control->buffer);
-				}
-				ADC_Start(adc->adc_device, adcStartSingle);
-				break;
+            switch (control->mode)
+            {
+            case ADC_MODE_SINGLE:
+                if (adc->singleDmaChannel != (rt_uint8_t)EFM32_NO_DMA)
+                {
+                    efm32_adc_on_dma(
+                        adc->adc_device,
+                        control->mode,
+                        adc->singleCount,
+                        adc->singleDmaChannel,
+                        control->buffer);
+                }
+                ADC_Start(adc->adc_device, adcStartSingle);
+                break;
 
-			case ADC_MODE_SCAN:
-				if (adc->scanDmaChannel != (rt_uint8_t)EFM32_NO_DMA)
-				{
-					efm32_adc_on_dma(
-						adc->adc_device,
-						control->mode,
-						adc->scanCount,
-						adc->scanDmaChannel,
-						control->buffer);
-				}
-				ADC_Start(adc->adc_device, adcStartScan);
-				break;
+            case ADC_MODE_SCAN:
+                if (adc->scanDmaChannel != (rt_uint8_t)EFM32_NO_DMA)
+                {
+                    efm32_adc_on_dma(
+                        adc->adc_device,
+                        control->mode,
+                        adc->scanCount,
+                        adc->scanDmaChannel,
+                        control->buffer);
+                }
+                ADC_Start(adc->adc_device, adcStartScan);
+                break;
 
-			case ADC_MODE_TAILGATE:
-				{
-					void *index = control->buffer;
+            case ADC_MODE_TAILGATE:
+                {
+                    void *index = control->buffer;
 
-					if (adc->scanDmaChannel != (rt_uint8_t)EFM32_NO_DMA)
-					{
-						efm32_adc_on_dma(
-							adc->adc_device,
-							control->mode,
-							adc->scanCount,
-							adc->scanDmaChannel,
-							index);
-						index += adc->scanCount;
-					}
-					if (adc->singleDmaChannel != (rt_uint8_t)EFM32_NO_DMA)
-					{
-						efm32_adc_on_dma(
-							adc->adc_device,
-							control->mode,
-							adc->singleCount,
-							adc->singleDmaChannel,
-							index);
-						index += adc->singleCount;
-					}
-					ADC_Start(adc->adc_device, adcStartScanAndSingle);
-				}
+                    if (adc->scanDmaChannel != (rt_uint8_t)EFM32_NO_DMA)
+                    {
+                        efm32_adc_on_dma(
+                            adc->adc_device,
+                            control->mode,
+                            adc->scanCount,
+                            adc->scanDmaChannel,
+                            index);
+                        index += adc->scanCount;
+                    }
+                    if (adc->singleDmaChannel != (rt_uint8_t)EFM32_NO_DMA)
+                    {
+                        efm32_adc_on_dma(
+                            adc->adc_device,
+                            control->mode,
+                            adc->singleCount,
+                            adc->singleDmaChannel,
+                            index);
+                        index += adc->singleCount;
+                    }
+                    ADC_Start(adc->adc_device, adcStartScanAndSingle);
+                }
 
-				break;
+                break;
 
-			default:
-				return -RT_ERROR;
-			}
-		}
-		break;
+            default:
+                return -RT_ERROR;
+            }
+        }
+        break;
 
-	case RT_DEVICE_CTRL_ADC_MODE:
-		{
-			/* change device setting */
-			struct efm32_adc_control_t *control = \
-				(struct efm32_adc_control_t *)args;
+    case RT_DEVICE_CTRL_ADC_MODE:
+        {
+            /* change device setting */
+            struct efm32_adc_control_t *control = \
+                (struct efm32_adc_control_t *)args;
 
-			switch (control->mode)
-			{
-			case ADC_MODE_SINGLE:
-				ADC_InitSingle(adc->adc_device, control->single.init);
-				break;
+            switch (control->mode)
+            {
+            case ADC_MODE_SINGLE:
+                ADC_InitSingle(adc->adc_device, control->single.init);
+                break;
 
-			case ADC_MODE_SCAN:
-				ADC_InitScan(adc->adc_device, control->scan.init);
-				break;
+            case ADC_MODE_SCAN:
+                ADC_InitScan(adc->adc_device, control->scan.init);
+                break;
 
-			case ADC_MODE_TAILGATE:
-				ADC_InitSingle(adc->adc_device, control->single.init);
-				ADC_InitScan(adc->adc_device, control->scan.init);
-				break;
+            case ADC_MODE_TAILGATE:
+                ADC_InitSingle(adc->adc_device, control->single.init);
+                ADC_InitScan(adc->adc_device, control->scan.init);
+                break;
 
-			default:
-				return -RT_ERROR;
-			}
+            default:
+                return -RT_ERROR;
+            }
 
-			if (control->mode == ADC_MODE_TAILGATE)
-			{
-				adc->mode = ADC_MODE_TAILGATE;
-			}
-			else
-			{
-				adc->mode &= ~(rt_uint8_t)ADC_MODE_TAILGATE;
-				adc->mode |= control->mode;
-			}
-			if ((control->mode == ADC_MODE_TAILGATE) || \
-				(control->mode == ADC_MODE_SINGLE))
-			{
-				if (control->single.init->rep)
-				{
-					adc->mode |= ADC_OP_SINGLE_REPEAT;
-				}
-				adc->singleCount = control->single.count;
-				adc->singleDmaChannel = control->single.dmaChannel;
-				efm32_adc_cfg_dma(adc->adc_device, control->mode, adc->singleDmaChannel);
-			}
-			if ((control->mode == ADC_MODE_TAILGATE) || \
-				(control->mode == ADC_MODE_SCAN))
-			{
-				if (control->scan.init->rep)
-				{
-					adc->mode |= ADC_OP_SCAN_REPEAT;
-				}
-				adc->scanCount = control->scan.count;
-				adc->scanDmaChannel = control->scan.dmaChannel;
-				efm32_adc_cfg_dma(adc->adc_device, control->mode, adc->scanDmaChannel);
-			}
-		}
-		break;
+            if (control->mode == ADC_MODE_TAILGATE)
+            {
+                adc->mode = ADC_MODE_TAILGATE;
+            }
+            else
+            {
+                adc->mode &= ~(rt_uint8_t)ADC_MODE_TAILGATE;
+                adc->mode |= control->mode;
+            }
+            if ((control->mode == ADC_MODE_TAILGATE) || \
+                (control->mode == ADC_MODE_SINGLE))
+            {
+                if (control->single.init->rep)
+                {
+                    adc->mode |= ADC_OP_SINGLE_REPEAT;
+                }
+                adc->singleCount = control->single.count;
+                adc->singleDmaChannel = control->single.dmaChannel;
+                efm32_adc_cfg_dma(adc->adc_device, control->mode, adc->singleDmaChannel);
+            }
+            if ((control->mode == ADC_MODE_TAILGATE) || \
+                (control->mode == ADC_MODE_SCAN))
+            {
+                if (control->scan.init->rep)
+                {
+                    adc->mode |= ADC_OP_SCAN_REPEAT;
+                }
+                adc->scanCount = control->scan.count;
+                adc->scanDmaChannel = control->scan.dmaChannel;
+                efm32_adc_cfg_dma(adc->adc_device, control->mode, adc->scanDmaChannel);
+            }
+        }
+        break;
 
-	case RT_DEVICE_CTRL_ADC_RESULT:
-		{
-			struct efm32_adc_result_t *control = \
-				(struct efm32_adc_result_t *)args;
+    case RT_DEVICE_CTRL_ADC_RESULT:
+        {
+            struct efm32_adc_result_t *control = \
+                (struct efm32_adc_result_t *)args;
 
-			switch (control->mode)
-			{
-			case ADC_MODE_SINGLE:
-				if (adc->singleDmaChannel != (rt_uint8_t)EFM32_NO_DMA)
-				{
-					if (adc->mode & ADC_OP_SINGLE_REPEAT)
-					{
-						if (!(DMA->IF & (1 << adc->singleDmaChannel)))
-						{
-							efm32_adc_on_dma(
-								adc->adc_device,
-								control->mode,
-								adc->singleCount,
-								adc->singleDmaChannel,
-								control->buffer);
-						}
-						while (!(DMA->IF & (1 << adc->singleDmaChannel)));
-					}
-					else
-					{
-						while (adc->adc_device->STATUS & ADC_STATUS_SINGLEACT);
-					}
-				}
-				else
-				{
-					while (adc->adc_device->STATUS & ADC_STATUS_SINGLEACT);
-					*((rt_uint32_t *)control->buffer) = \
-						ADC_DataSingleGet(adc->adc_device) << adcErrataShift;
-				}
-				break;
+            switch (control->mode)
+            {
+            case ADC_MODE_SINGLE:
+                if (adc->singleDmaChannel != (rt_uint8_t)EFM32_NO_DMA)
+                {
+                    if (adc->mode & ADC_OP_SINGLE_REPEAT)
+                    {
+                        if (!(DMA->IF & (1 << adc->singleDmaChannel)))
+                        {
+                            efm32_adc_on_dma(
+                                adc->adc_device,
+                                control->mode,
+                                adc->singleCount,
+                                adc->singleDmaChannel,
+                                control->buffer);
+                        }
+                        while (!(DMA->IF & (1 << adc->singleDmaChannel)));
+                    }
+                    else
+                    {
+                        while (adc->adc_device->STATUS & ADC_STATUS_SINGLEACT);
+                    }
+                }
+                else
+                {
+                    while (adc->adc_device->STATUS & ADC_STATUS_SINGLEACT);
+                    *((rt_uint32_t *)control->buffer) = \
+                        ADC_DataSingleGet(adc->adc_device) << adcErrataShift;
+                }
+                break;
 
-			case ADC_MODE_SCAN:
-				if (adc->scanDmaChannel != (rt_uint8_t)EFM32_NO_DMA)
-				{
-					if (adc->mode & ADC_OP_SCAN_REPEAT)
-					{
-						if (!(DMA->IF & (1 << adc->scanDmaChannel)))
-						{
-							efm32_adc_on_dma(
-								adc->adc_device,
-								control->mode,
-								adc->scanCount,
-								adc->scanDmaChannel,
-								control->buffer);
-						}
-						while (!(DMA->IF & (1 << adc->scanDmaChannel)));
-					}
-					else
-					{
-						while (adc->adc_device->STATUS & ADC_STATUS_SCANACT);
-					}
-				}
-				else
-				{
-					while (adc->adc_device->STATUS & ADC_STATUS_SCANACT);
-					*((rt_uint32_t *)control->buffer) = \
-						ADC_DataScanGet(adc->adc_device) << adcErrataShift;
-				}
-				break;
+            case ADC_MODE_SCAN:
+                if (adc->scanDmaChannel != (rt_uint8_t)EFM32_NO_DMA)
+                {
+                    if (adc->mode & ADC_OP_SCAN_REPEAT)
+                    {
+                        if (!(DMA->IF & (1 << adc->scanDmaChannel)))
+                        {
+                            efm32_adc_on_dma(
+                                adc->adc_device,
+                                control->mode,
+                                adc->scanCount,
+                                adc->scanDmaChannel,
+                                control->buffer);
+                        }
+                        while (!(DMA->IF & (1 << adc->scanDmaChannel)));
+                    }
+                    else
+                    {
+                        while (adc->adc_device->STATUS & ADC_STATUS_SCANACT);
+                    }
+                }
+                else
+                {
+                    while (adc->adc_device->STATUS & ADC_STATUS_SCANACT);
+                    *((rt_uint32_t *)control->buffer) = \
+                        ADC_DataScanGet(adc->adc_device) << adcErrataShift;
+                }
+                break;
 
-			case ADC_MODE_TAILGATE:
-				{
-					void *index = control->buffer;
+            case ADC_MODE_TAILGATE:
+                {
+                    void *index = control->buffer;
 
-					if ((adc->scanDmaChannel != (rt_uint8_t)EFM32_NO_DMA) && \
-						!(adc->mode & ADC_OP_SCAN_REPEAT))
-					{
-						index += adc->scanCount;
-					}
-					if ((adc->singleDmaChannel != (rt_uint8_t)EFM32_NO_DMA) && \
-						!(adc->mode & ADC_OP_SINGLE_REPEAT))
-					{
-						index += adc->singleCount;
-					}
+                    if ((adc->scanDmaChannel != (rt_uint8_t)EFM32_NO_DMA) && \
+                        !(adc->mode & ADC_OP_SCAN_REPEAT))
+                    {
+                        index += adc->scanCount;
+                    }
+                    if ((adc->singleDmaChannel != (rt_uint8_t)EFM32_NO_DMA) && \
+                        !(adc->mode & ADC_OP_SINGLE_REPEAT))
+                    {
+                        index += adc->singleCount;
+                    }
 
-					if (adc->scanDmaChannel != (rt_uint8_t)EFM32_NO_DMA)
-					{
-						if (adc->mode & ADC_OP_SCAN_REPEAT)
-						{
-							if (!(DMA->IF & (1 << adc->scanDmaChannel)))
-							{
-								efm32_adc_on_dma(
-									adc->adc_device,
-									control->mode,
-									adc->scanCount,
-									adc->scanDmaChannel,
-									index);
-								index += adc->scanCount;
-							}
-							while (!(DMA->IF & (1 << adc->scanDmaChannel)));
-						}
-						else
-						{
-							while (adc->adc_device->STATUS & ADC_STATUS_SCANACT);
-						}
-					}
-					else
-					{
-						while (adc->adc_device->STATUS & ADC_STATUS_SCANACT);
-						*(rt_uint32_t *)(index++) = \
-							ADC_DataScanGet(adc->adc_device) << adcErrataShift;
-					}
-					if (adc->singleDmaChannel != (rt_uint8_t)EFM32_NO_DMA)
-					{
-						if (adc->mode & ADC_OP_SINGLE_REPEAT)
-						{
-							if (!(DMA->IF & (1 << adc->singleDmaChannel)))
-							{
-								efm32_adc_on_dma(
-									adc->adc_device,
-									control->mode,
-									adc->singleCount,
-									adc->singleDmaChannel,
-									index);
-								index += adc->singleCount;
-							}
-							while (!(DMA->IF & (1 << adc->singleDmaChannel)));
-						}
-						else
-						{
-							while (adc->adc_device->STATUS & ADC_STATUS_SINGLEACT);
-						}
-					}
-					else
-					{
-						while (adc->adc_device->STATUS & ADC_STATUS_SINGLEACT);
-						*(rt_uint32_t *)(index++) = \
-							ADC_DataSingleGet(adc->adc_device) << adcErrataShift;
-					}
-				}
-				break;
+                    if (adc->scanDmaChannel != (rt_uint8_t)EFM32_NO_DMA)
+                    {
+                        if (adc->mode & ADC_OP_SCAN_REPEAT)
+                        {
+                            if (!(DMA->IF & (1 << adc->scanDmaChannel)))
+                            {
+                                efm32_adc_on_dma(
+                                    adc->adc_device,
+                                    control->mode,
+                                    adc->scanCount,
+                                    adc->scanDmaChannel,
+                                    index);
+                                index += adc->scanCount;
+                            }
+                            while (!(DMA->IF & (1 << adc->scanDmaChannel)));
+                        }
+                        else
+                        {
+                            while (adc->adc_device->STATUS & ADC_STATUS_SCANACT);
+                        }
+                    }
+                    else
+                    {
+                        while (adc->adc_device->STATUS & ADC_STATUS_SCANACT);
+                        *(rt_uint32_t *)(index++) = \
+                            ADC_DataScanGet(adc->adc_device) << adcErrataShift;
+                    }
+                    if (adc->singleDmaChannel != (rt_uint8_t)EFM32_NO_DMA)
+                    {
+                        if (adc->mode & ADC_OP_SINGLE_REPEAT)
+                        {
+                            if (!(DMA->IF & (1 << adc->singleDmaChannel)))
+                            {
+                                efm32_adc_on_dma(
+                                    adc->adc_device,
+                                    control->mode,
+                                    adc->singleCount,
+                                    adc->singleDmaChannel,
+                                    index);
+                                index += adc->singleCount;
+                            }
+                            while (!(DMA->IF & (1 << adc->singleDmaChannel)));
+                        }
+                        else
+                        {
+                            while (adc->adc_device->STATUS & ADC_STATUS_SINGLEACT);
+                        }
+                    }
+                    else
+                    {
+                        while (adc->adc_device->STATUS & ADC_STATUS_SINGLEACT);
+                        *(rt_uint32_t *)(index++) = \
+                            ADC_DataSingleGet(adc->adc_device) << adcErrataShift;
+                    }
+                }
+                break;
 
-			default:
-				return -RT_ERROR;
-			}
-		}
-		break;
+            default:
+                return -RT_ERROR;
+            }
+        }
+        break;
 
-	default:
-		return -RT_ERROR;
-	}
+    default:
+        return -RT_ERROR;
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 /***************************************************************************//**
  * @brief
- *	Register ADC device
+ *  Register ADC device
  *
  * @details
  *
  * @note
  *
  * @param[in] device
- *	Pointer to device descriptor
+ *  Pointer to device descriptor
  *
  * @param[in] name
- *	Device name
+ *  Device name
  *
  * @param[in] flag
- *	Configuration flags
+ *  Configuration flags
  *
  * @param[in] adc
- *	Pointer to ADC device descriptor
+ *  Pointer to ADC device descriptor
  *
  * @return
- *	Error code
+ *  Error code
  ******************************************************************************/
 rt_err_t rt_hw_adc_register(
-	rt_device_t		device,
-	const char		*name,
-	rt_uint32_t		flag,
-	struct efm32_adc_device_t *adc)
+    rt_device_t     device,
+    const char      *name,
+    rt_uint32_t     flag,
+    struct efm32_adc_device_t *adc)
 {
-	RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(device != RT_NULL);
 
-	device->type 		= RT_Device_Class_Char; /* fixme: should be adc type */
-	device->rx_indicate = RT_NULL;
-	device->tx_complete = RT_NULL;
-	device->init 		= rt_adc_init;
-	device->open		= RT_NULL;
-	device->close		= RT_NULL;
-	device->read 		= RT_NULL;
-	device->write 		= RT_NULL;
-	device->control 	= rt_adc_control;
-	device->user_data	= adc;
+    device->type        = RT_Device_Class_Char; /* fixme: should be adc type */
+    device->rx_indicate = RT_NULL;
+    device->tx_complete = RT_NULL;
+    device->init        = rt_adc_init;
+    device->open        = RT_NULL;
+    device->close       = RT_NULL;
+    device->read        = RT_NULL;
+    device->write       = RT_NULL;
+    device->control     = rt_adc_control;
+    device->user_data   = adc;
 
-	/* register a character device */
-	return rt_device_register(device, name, flag);
+    /* register a character device */
+    return rt_device_register(device, name, flag);
 }
 
 /***************************************************************************//**
  * @brief
- *	Initialize the specified ADC unit
+ *  Initialize the specified ADC unit
  *
  * @details
  *
  * @note
  *
  * @param[in] device
- *	Pointer to device descriptor
+ *  Pointer to device descriptor
  *
  * @param[in] unitNumber
- *	Unit number
+ *  Unit number
  *
  * @return
- *	Pointer to ADC device
+ *  Pointer to ADC device
  ******************************************************************************/
 static struct efm32_adc_device_t *rt_hw_adc_unit_init(
-	rt_device_t device,
-	rt_uint8_t 	unitNumber)
+    rt_device_t device,
+    rt_uint8_t  unitNumber)
 {
-	struct efm32_adc_device_t 		*adc;
-	CMU_Clock_TypeDef				adcClock;
-	ADC_Init_TypeDef 				init = ADC_INIT_DEFAULT;
+    struct efm32_adc_device_t       *adc;
+    CMU_Clock_TypeDef               adcClock;
+    ADC_Init_TypeDef                init = ADC_INIT_DEFAULT;
 
-	do
-	{
-		/* Allocate device and set default value */
-		adc = rt_malloc(sizeof(struct efm32_adc_device_t));
-		if (adc == RT_NULL)
-		{
-			adc_debug("no memory for ADC%d driver\n", unitNumber);
-			break;
-		}
-		adc->mode 				= 0;
-		adc->singleCount 		= 0;
-		adc->singleDmaChannel 	= (rt_uint8_t)EFM32_NO_DMA;
-		adc->scanCount 			= 0;
-		adc->scanDmaChannel 	= (rt_uint8_t)EFM32_NO_DMA;
+    do
+    {
+        /* Allocate device and set default value */
+        adc = rt_malloc(sizeof(struct efm32_adc_device_t));
+        if (adc == RT_NULL)
+        {
+            adc_debug("no memory for ADC%d driver\n", unitNumber);
+            break;
+        }
+        adc->mode               = 0;
+        adc->singleCount        = 0;
+        adc->singleDmaChannel   = (rt_uint8_t)EFM32_NO_DMA;
+        adc->scanCount          = 0;
+        adc->scanDmaChannel     = (rt_uint8_t)EFM32_NO_DMA;
 
-		/* Initialization */
-		if (unitNumber >= ADC_COUNT)
-		{
-			break;
-		}
-		switch (unitNumber)
-		{
-		case 0:
-			adc->adc_device 	= ADC0;
-			adcClock 			= (CMU_Clock_TypeDef)cmuClock_ADC0;
-			break;
+        /* Initialization */
+        if (unitNumber >= ADC_COUNT)
+        {
+            break;
+        }
+        switch (unitNumber)
+        {
+        case 0:
+            adc->adc_device     = ADC0;
+            adcClock            = (CMU_Clock_TypeDef)cmuClock_ADC0;
+            break;
 
-		default:
-			break;
-		}
+        default:
+            break;
+        }
 
-		/* Enable ADC clock */
-		CMU_ClockEnable(adcClock, true);
+        /* Enable ADC clock */
+        CMU_ClockEnable(adcClock, true);
 
-		/* Reset */
-		ADC_Reset(adc->adc_device);
+        /* Reset */
+        ADC_Reset(adc->adc_device);
 
-		/* Configure ADC */
-		// TODO: Fixed oversampling rate?
-		init.ovsRateSel 		= adcOvsRateSel4096;
-		init.timebase			= ADC_TimebaseCalc(0);
-		init.prescale			= ADC_PrescaleCalc(ADC_CONVERT_FREQUENCY, 0);
-		ADC_Init(adc->adc_device, &init);
+        /* Configure ADC */
+        // TODO: Fixed oversampling rate?
+        init.ovsRateSel         = adcOvsRateSel4096;
+        init.timebase           = ADC_TimebaseCalc(0);
+        init.prescale           = ADC_PrescaleCalc(ADC_CONVERT_FREQUENCY, 0);
+        ADC_Init(adc->adc_device, &init);
 
-		return adc;
-	} while(0);
+        return adc;
+    } while(0);
 
-	if (adc)
-	{
-		rt_free(adc);
-	}
-	rt_kprintf("ADC: Init failed!\n");
-	return RT_NULL;
+    if (adc)
+    {
+        rt_free(adc);
+    }
+    rt_kprintf("ADC: Init failed!\n");
+    return RT_NULL;
 }
 
 /***************************************************************************//**
  * @brief
- *	Initialize all ADC module related hardware and register ADC device to kernel
+ *  Initialize all ADC module related hardware and register ADC device to kernel
  *
  * @details
  *
@@ -809,23 +809,23 @@ static struct efm32_adc_device_t *rt_hw_adc_unit_init(
  ******************************************************************************/
 void rt_hw_adc_init(void)
 {
-	SYSTEM_ChipRevision_TypeDef	chipRev;
-	struct efm32_adc_device_t 	*adc;
+    SYSTEM_ChipRevision_TypeDef chipRev;
+    struct efm32_adc_device_t   *adc;
 
 #ifdef RT_USING_ADC0
-	if ((adc = rt_hw_adc_unit_init(&adc0_device, 0)) != RT_NULL)
-	{
-		rt_hw_adc_register(&adc0_device, RT_ADC0_NAME, EFM32_NO_DATA, adc);
-	}
+    if ((adc = rt_hw_adc_unit_init(&adc0_device, 0)) != RT_NULL)
+    {
+        rt_hw_adc_register(&adc0_device, RT_ADC0_NAME, EFM32_NO_DATA, adc);
+    }
 #endif
 
-	/* ADC errata for rev B when using VDD as reference, need to multiply */
-	/* result by 2 */
-	SYSTEM_ChipRevisionGet(&chipRev);
-	if ((chipRev.major == 0x01) && (chipRev.minor == 0x01))
-	{
-	  adcErrataShift = 1;
-	}
+    /* ADC errata for rev B when using VDD as reference, need to multiply */
+    /* result by 2 */
+    SYSTEM_ChipRevisionGet(&chipRev);
+    if ((chipRev.major == 0x01) && (chipRev.minor == 0x01))
+    {
+      adcErrataShift = 1;
+    }
 }
 
 #endif
diff --git a/bsp/efm32/drv_adc.h b/bsp/efm32/drv_adc.h
index b3b81d94e1..f15d074835 100644
--- a/bsp/efm32/drv_adc.h
+++ b/bsp/efm32/drv_adc.h
@@ -1,8 +1,8 @@
 /***************************************************************************//**
- * @file 	drv_adc.h
- * @brief 	ADC driver of RT-Thread RTOS for EFM32
+ * @file    drv_adc.h
+ * @brief   ADC driver of RT-Thread RTOS for EFM32
  *  COPYRIGHT (C) 2012, RT-Thread Development Team
- * @author 	onelife
+ * @author  onelife
  * @version 1.0
  *******************************************************************************
  * @section License
@@ -10,9 +10,9 @@
  * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
  *******************************************************************************
  * @section Change Logs
- * Date			Author		Notes
- * 2011-02-21	onelife		Initial creation for EFM32
- * 2011-07-14	onelife		Add multiple channels support for scan mode
+ * Date         Author      Notes
+ * 2011-02-21   onelife     Initial creation for EFM32
+ * 2011-07-14   onelife     Add multiple channels support for scan mode
  ******************************************************************************/
 #ifndef __DRV_ADC_H__
 #define __DRV_ADC_H__
@@ -21,50 +21,50 @@
 /* Exported types ------------------------------------------------------------*/
 struct efm32_adc_device_t
 {
-	ADC_TypeDef 			*adc_device;
-	rt_uint8_t 				mode;
-	rt_uint8_t 				singleCount;
-	rt_uint8_t 				singleDmaChannel;
-	rt_uint8_t 				scanCount;
-	rt_uint8_t 				scanDmaChannel;
+    ADC_TypeDef             *adc_device;
+    rt_uint8_t              mode;
+    rt_uint8_t              singleCount;
+    rt_uint8_t              singleDmaChannel;
+    rt_uint8_t              scanCount;
+    rt_uint8_t              scanDmaChannel;
 };
 
 struct efm32_adc_control_single_t
 {
-	rt_uint8_t				count;
-	rt_uint8_t 				dmaChannel;
-	ADC_InitSingle_TypeDef	*init;
+    rt_uint8_t              count;
+    rt_uint8_t              dmaChannel;
+    ADC_InitSingle_TypeDef  *init;
 };
 
 struct efm32_adc_control_scan_t
 {
-	rt_uint8_t				count;
-	rt_uint8_t 				dmaChannel;
-	ADC_InitScan_TypeDef	*init;
+    rt_uint8_t              count;
+    rt_uint8_t              dmaChannel;
+    ADC_InitScan_TypeDef    *init;
 };
 
 struct efm32_adc_control_t
 {
-	rt_uint8_t 				mode;
-	struct efm32_adc_control_scan_t 	scan;
-	struct efm32_adc_control_single_t 	single;
+    rt_uint8_t              mode;
+    struct efm32_adc_control_scan_t     scan;
+    struct efm32_adc_control_single_t   single;
 };
 
 struct efm32_adc_result_t
 {
-	rt_uint8_t 				mode;
-	void 					*buffer;
+    rt_uint8_t              mode;
+    void                    *buffer;
 };
 
 /* Exported constants --------------------------------------------------------*/
 /* Exported macro ------------------------------------------------------------*/
-#define ADC_MODE_SINGLE 		(0x01)
-#define ADC_MODE_SCAN 			(0x02)
-#define ADC_MODE_TAILGATE		(0x04)
-#define ADC_OP_SINGLE_REPEAT	(0x10)
-#define ADC_OP_SCAN_REPEAT		(0x20)
-#define ADC_MASK_MODE			(0x0f)
-#define ADC_MASK_OP				(0xf0)
+#define ADC_MODE_SINGLE         (0x01)
+#define ADC_MODE_SCAN           (0x02)
+#define ADC_MODE_TAILGATE       (0x04)
+#define ADC_OP_SINGLE_REPEAT    (0x10)
+#define ADC_OP_SCAN_REPEAT      (0x20)
+#define ADC_MASK_MODE           (0x0f)
+#define ADC_MASK_OP             (0xf0)
 
 /* Exported functions ------------------------------------------------------- */
 void rt_hw_adc_init(void);
diff --git a/bsp/efm32/drv_emu.c b/bsp/efm32/drv_emu.c
index 9a5fc8e97e..18eeca1a43 100644
--- a/bsp/efm32/drv_emu.c
+++ b/bsp/efm32/drv_emu.c
@@ -1,8 +1,8 @@
 /***************************************************************************//**
- * @file 	drv_emu.c
- * @brief 	EMU driver of RT-Thread RTOS for EFM32
+ * @file    drv_emu.c
+ * @brief   EMU driver of RT-Thread RTOS for EFM32
  *  COPYRIGHT (C) 2012, RT-Thread Development Team
- * @author 	onelife
+ * @author  onelife
  * @version 1.0
  *******************************************************************************
  * @section License
@@ -10,8 +10,8 @@
  * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
  *******************************************************************************
  * @section Change Logs
- * Date			Author		Notes
- * 2012-02-21	onelife		Initial creation for EFM32
+ * Date         Author      Notes
+ * 2012-02-21   onelife     Initial creation for EFM32
  ******************************************************************************/
 
 /***************************************************************************//**
@@ -27,7 +27,7 @@
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
 #ifdef EFM32_EMU_DEBUG
-#define emu_debug(format,args...) 			rt_kprintf(format, ##args)
+#define emu_debug(format,args...)           rt_kprintf(format, ##args)
 #else
 #define emu_debug(format,args...)
 #endif
@@ -176,7 +176,7 @@ void emu_em4_enable(void)
 
 /***************************************************************************//**
  * @brief
- *	Initialize EMU module related hardware
+ *  Initialize EMU module related hardware
  *
  * @details
  *
@@ -213,22 +213,22 @@ void efm32_emu_init(void)
             break;
         }
 
-    	/* init thread */
+        /* init thread */
         if (rt_thread_init(
             &emu_task.thread,
             "EMU",
-    		emu_task_main_loop, (void *)&emu_task,
+            emu_task_main_loop, (void *)&emu_task,
             (void *)&emu_task.stack, sizeof(emu_task.stack),
-    		RT_THREAD_PRIORITY_MAX - 2, RT_TICK_PER_SECOND) != RT_EOK)
+            RT_THREAD_PRIORITY_MAX - 2, RT_TICK_PER_SECOND) != RT_EOK)
         {
             break;
         }
 
-    	/* startup */
-    	if (rt_thread_startup(&emu_task.thread) != RT_EOK)
-    	{
+        /* startup */
+        if (rt_thread_startup(&emu_task.thread) != RT_EOK)
+        {
             break;
-    	}
+        }
     } while (0);
 
     rt_kprintf("EMU err: init failed!\n");
diff --git a/bsp/efm32/drv_emu.h b/bsp/efm32/drv_emu.h
index 3e491665ba..df46264295 100644
--- a/bsp/efm32/drv_emu.h
+++ b/bsp/efm32/drv_emu.h
@@ -1,8 +1,8 @@
 /***************************************************************************//**
- * @file 	drv_emu.h
- * @brief 	EMU driver of RT-Thread RTOS for EFM32
+ * @file    drv_emu.h
+ * @brief   EMU driver of RT-Thread RTOS for EFM32
  *  COPYRIGHT (C) 2012, RT-Thread Development Team
- * @author 	onelife
+ * @author  onelife
  * @version 1.0
  *******************************************************************************
  * @section License
@@ -10,9 +10,9 @@
  * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
  *******************************************************************************
  * @section Change Logs
- * Date			Author		Notes
- * 2011-02-21	onelife		Initial creation for EFM32
- * 2011-07-14	onelife		Add multiple channels support for scan mode
+ * Date         Author      Notes
+ * 2011-02-21   onelife     Initial creation for EFM32
+ * 2011-07-14   onelife     Add multiple channels support for scan mode
  ******************************************************************************/
 #ifndef __DRV_EMU_H__
 #define __DRV_EMU_H__
diff --git a/bsp/efm32/drv_ethernet.c b/bsp/efm32/drv_ethernet.c
index e6bc25bbcc..db99de583a 100644
--- a/bsp/efm32/drv_ethernet.c
+++ b/bsp/efm32/drv_ethernet.c
@@ -1,11 +1,11 @@
 /***************************************************************************//**
- * @file 	drv_ethernet.c
- * @brief 	Ethernet driver (SPI mode) of RT-Thread RTOS for using EFM32 USART
+ * @file    drv_ethernet.c
+ * @brief   Ethernet driver (SPI mode) of RT-Thread RTOS for using EFM32 USART
  *  module
- * 	 This driver is tested by using the Microchip ENC28J60 stand-alone Ethernet
+ *   This driver is tested by using the Microchip ENC28J60 stand-alone Ethernet
  *  controller with SPI interface.
  *  COPYRIGHT (C) 2012, RT-Thread Development Team
- * @author 	onelife
+ * @author  onelife
  * @version 1.0
  *******************************************************************************
  * @section License
@@ -13,11 +13,11 @@
  *  LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
  *******************************************************************************
  * @section Change Logs
- * Date			Author		Notes
- * 2011-06-22	onelife		Initial creation for using EFM32 USART module
- * 2011-07-25	onelife		Add lock (semaphore) to prevent simultaneously
+ * Date         Author      Notes
+ * 2011-06-22   onelife     Initial creation for using EFM32 USART module
+ * 2011-07-25   onelife     Add lock (semaphore) to prevent simultaneously
  *  access
- * 2011-07-28	onelife		Add get_ip() and update_ip() utilities
+ * 2011-07-28   onelife     Add get_ip() and update_ip() utilities
  ******************************************************************************/
 
 /***************************************************************************//**
@@ -38,21 +38,21 @@
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
 #ifdef EFM32_ETHERNET_DEBUG
-#define eth_debug(format,args...) 			rt_kprintf(format, ##args)
+#define eth_debug(format,args...)           rt_kprintf(format, ##args)
 #else
 #define eth_debug(format,args...)
 #endif
 
 /* Private constants ---------------------------------------------------------*/
-static const rt_uint8_t 	eth_addr[ETH_ADDR_LEN] = ETH_ADDR_DEFAULT;
+static const rt_uint8_t     eth_addr[ETH_ADDR_LEN] = ETH_ADDR_DEFAULT;
 
 /* Private variables ---------------------------------------------------------*/
-static struct eth_device 	eth_dev;
-static struct rt_semaphore 	ethLock;
-static rt_uint8_t 			ethBank;
-static rt_uint16_t 			ethNxtPkt;
-static rt_device_t 			spi 			= RT_NULL;
-static rt_bool_t 			ethAutoCs 		= true;
+static struct eth_device    eth_dev;
+static struct rt_semaphore  ethLock;
+static rt_uint8_t           ethBank;
+static rt_uint16_t          ethNxtPkt;
+static rt_device_t          spi             = RT_NULL;
+static rt_bool_t            ethAutoCs       = true;
 
 /* Private function prototypes -----------------------------------------------*/
 /* Private functions ---------------------------------------------------------*/
@@ -69,17 +69,17 @@ static rt_bool_t 			ethAutoCs 		= true;
  ******************************************************************************/
 static void efm_eth_cs(rt_uint8_t enable)
 {
-	if (!ethAutoCs)
-	{
-		if (enable)
-		{
-			GPIO_PinOutClear(ETH_CS_PORT, ETH_CS_PIN);
-		}
-		else
-		{
-			GPIO_PinOutSet(ETH_CS_PORT, ETH_CS_PIN);
-		}
-	}
+    if (!ethAutoCs)
+    {
+        if (enable)
+        {
+            GPIO_PinOutClear(ETH_CS_PORT, ETH_CS_PIN);
+        }
+        else
+        {
+            GPIO_PinOutSet(ETH_CS_PORT, ETH_CS_PIN);
+        }
+    }
 }
 
 /***************************************************************************//**
@@ -103,93 +103,93 @@ static void efm_eth_cs(rt_uint8_t enable)
  *   Error code
  ******************************************************************************/
 static rt_err_t efm_eth_cmd(
-	rt_uint8_t cmd,
-	rt_uint8_t addr,
-	rt_uint8_t *data)
+    rt_uint8_t cmd,
+    rt_uint8_t addr,
+    rt_uint8_t *data)
 {
-	RT_ASSERT(spi != RT_NULL);
+    RT_ASSERT(spi != RT_NULL);
 
-	rt_uint8_t buf_ins[6], buf_res[2];
-	rt_uint8_t len_ins, len_res;
+    rt_uint8_t buf_ins[6], buf_res[2];
+    rt_uint8_t len_ins, len_res;
 
-	len_ins = 0;
-	do
-	{
-		/* Build instruction buffer */
-		/* Check if need to read back */
-		if (cmd == ENC28J60_READ_CTRL_REG)
-		{
-			buf_ins[len_ins++] = 1; 						/* Instruction length */
-		}
-		/* Byte 0: Check if no address section */
-		if (cmd == ENC28J60_READ_BUF_MEM || cmd == ENC28J60_WRITE_BUF_MEM || \
-			cmd == ENC28J60_SOFT_RESET)
-		{
-			buf_ins[len_ins++] = cmd;
-		}
-		else
-		{
-			buf_ins[len_ins++] = cmd | (addr & ADDR_MASK);
-		}
-		/* Byte 1: Check if data section is present */
-		if (cmd == ENC28J60_WRITE_CTRL_REG || cmd == ENC28J60_BIT_FIELD_SET || \
-			cmd == ENC28J60_BIT_FIELD_CLR || cmd == ENC28J60_WRITE_BUF_MEM)
-		{
-			buf_ins[len_ins++] = *data;
-		}
+    len_ins = 0;
+    do
+    {
+        /* Build instruction buffer */
+        /* Check if need to read back */
+        if (cmd == ENC28J60_READ_CTRL_REG)
+        {
+            buf_ins[len_ins++] = 1;                         /* Instruction length */
+        }
+        /* Byte 0: Check if no address section */
+        if (cmd == ENC28J60_READ_BUF_MEM || cmd == ENC28J60_WRITE_BUF_MEM || \
+            cmd == ENC28J60_SOFT_RESET)
+        {
+            buf_ins[len_ins++] = cmd;
+        }
+        else
+        {
+            buf_ins[len_ins++] = cmd | (addr & ADDR_MASK);
+        }
+        /* Byte 1: Check if data section is present */
+        if (cmd == ENC28J60_WRITE_CTRL_REG || cmd == ENC28J60_BIT_FIELD_SET || \
+            cmd == ENC28J60_BIT_FIELD_CLR || cmd == ENC28J60_WRITE_BUF_MEM)
+        {
+            buf_ins[len_ins++] = *data;
+        }
 
-		/* Check if reading */
-		if (cmd == ENC28J60_READ_CTRL_REG)
-		{
-			*(rt_uint8_t **)(&buf_ins[len_ins]) = buf_res; 	/* Pointer to RX buffer */
-			len_ins += 4;
+        /* Check if reading */
+        if (cmd == ENC28J60_READ_CTRL_REG)
+        {
+            *(rt_uint8_t **)(&buf_ins[len_ins]) = buf_res;  /* Pointer to RX buffer */
+            len_ins += 4;
 
-			/* Check if MAC or MII register */
-			if (addr & SPRD_MASK)
-			{
-				len_res = 2;
-			}
-			else
-			{
-				len_res = 1;
-			}
+            /* Check if MAC or MII register */
+            if (addr & SPRD_MASK)
+            {
+                len_res = 2;
+            }
+            else
+            {
+                len_res = 1;
+            }
 
-			/* Send command and get response */
-			efm_eth_cs(1);
-			if (spi->read(spi, ETH_SPI_RX_SKIP, buf_ins, len_res) == 0)
-			{
-				break;
-			}
-			*data = buf_res[len_res - 1];
-//			eth_debug("ETH: read RX %x %x (%d)\n", buf_res[0], buf_res[1], len_res);
-//			eth_debug("ETH: ** read RX %x %x (%d)\n",
-//				buf_res[0], buf_res[1], buf_res[2], buf_res[3], buf_res[4],
-//				buf_res[5], buf_res[6], buf_res[7], buf_res[8], buf_res[9],
-//				len_res);
-		}
-		else
-		{
-//			eth_debug("ETH: ** write TX %x %x %x %x %x %x (%d) \n", buf_ins[0],
-//				buf_ins[1], buf_ins[2], buf_ins[3], buf_ins[4], buf_ins[5],
-//				len_ins);
-			/* Send command and get response */
-			efm_eth_cs(1);
-			if (spi->write(spi, EFM32_NO_DATA, buf_ins, len_ins) == 0)
-			{
-				break;
-			}
-		}
+            /* Send command and get response */
+            efm_eth_cs(1);
+            if (spi->read(spi, ETH_SPI_RX_SKIP, buf_ins, len_res) == 0)
+            {
+                break;
+            }
+            *data = buf_res[len_res - 1];
+//          eth_debug("ETH: read RX %x %x (%d)\n", buf_res[0], buf_res[1], len_res);
+//          eth_debug("ETH: ** read RX %x %x (%d)\n",
+//              buf_res[0], buf_res[1], buf_res[2], buf_res[3], buf_res[4],
+//              buf_res[5], buf_res[6], buf_res[7], buf_res[8], buf_res[9],
+//              len_res);
+        }
+        else
+        {
+//          eth_debug("ETH: ** write TX %x %x %x %x %x %x (%d) \n", buf_ins[0],
+//              buf_ins[1], buf_ins[2], buf_ins[3], buf_ins[4], buf_ins[5],
+//              len_ins);
+            /* Send command and get response */
+            efm_eth_cs(1);
+            if (spi->write(spi, EFM32_NO_DATA, buf_ins, len_ins) == 0)
+            {
+                break;
+            }
+        }
 
-		if (!(cmd == ENC28J60_READ_BUF_MEM || cmd == ENC28J60_WRITE_BUF_MEM))
-		{
-			efm_eth_cs(0);
-		}
-		return RT_EOK;
-	} while(0);
+        if (!(cmd == ENC28J60_READ_BUF_MEM || cmd == ENC28J60_WRITE_BUF_MEM))
+        {
+            efm_eth_cs(0);
+        }
+        return RT_EOK;
+    } while(0);
 
-	eth_debug("ETH: Send command failed!\n");
-	efm_eth_cs(0);
-	return -RT_ERROR;
+    eth_debug("ETH: Send command failed!\n");
+    efm_eth_cs(0);
+    return -RT_ERROR;
 }
 
 /***************************************************************************//**
@@ -213,37 +213,37 @@ static rt_err_t efm_eth_cmd(
  *   Error code
  ******************************************************************************/
 static rt_err_t efm_eth_sendCmd(
-	rt_uint8_t cmd,
-	rt_uint8_t addr,
-	rt_uint8_t *data)
+    rt_uint8_t cmd,
+    rt_uint8_t addr,
+    rt_uint8_t *data)
 {
-	rt_err_t ret;
+    rt_err_t ret;
 
-	eth_debug("ETH: Send command %x (%x %x)\n", cmd, addr, *data);
-	do
-	{
-		/* Change bank */
-		if(((addr & BANK_MASK) != ethBank) && ((addr < EIE) || (addr > ECON1)))
-		{
-			rt_uint8_t temp;
+    eth_debug("ETH: Send command %x (%x %x)\n", cmd, addr, *data);
+    do
+    {
+        /* Change bank */
+        if(((addr & BANK_MASK) != ethBank) && ((addr < EIE) || (addr > ECON1)))
+        {
+            rt_uint8_t temp;
 
-			if ((ret = efm_eth_cmd(ENC28J60_READ_CTRL_REG, ECON1, &temp)) != RT_EOK)
-			{
-				break;
-			}
-			temp &= 0xFC;
-			ethBank = (addr & BANK_MASK);
-			temp |= ethBank >> BANK_SHIFT;
-			if ((ret = efm_eth_cmd(ENC28J60_WRITE_CTRL_REG, ECON1, &temp)) != RT_EOK)
-			{
-				break;
-			}
-		}
-		/* Send command */
-		ret = efm_eth_cmd(cmd, addr, data);
-	} while(0);
+            if ((ret = efm_eth_cmd(ENC28J60_READ_CTRL_REG, ECON1, &temp)) != RT_EOK)
+            {
+                break;
+            }
+            temp &= 0xFC;
+            ethBank = (addr & BANK_MASK);
+            temp |= ethBank >> BANK_SHIFT;
+            if ((ret = efm_eth_cmd(ENC28J60_WRITE_CTRL_REG, ECON1, &temp)) != RT_EOK)
+            {
+                break;
+            }
+        }
+        /* Send command */
+        ret = efm_eth_cmd(cmd, addr, data);
+    } while(0);
 
-	return ret;
+    return ret;
 }
 
 /***************************************************************************//**
@@ -262,11 +262,11 @@ static rt_err_t efm_eth_sendCmd(
  ******************************************************************************/
 static rt_uint8_t efm_eth_readReg(rt_uint8_t addr)
 {
-	rt_uint8_t data;
+    rt_uint8_t data;
 
-	efm_eth_sendCmd(ENC28J60_READ_CTRL_REG, addr, &data);
+    efm_eth_sendCmd(ENC28J60_READ_CTRL_REG, addr, &data);
 
-	return data;
+    return data;
 }
 
 /***************************************************************************//**
@@ -285,7 +285,7 @@ static rt_uint8_t efm_eth_readReg(rt_uint8_t addr)
  ******************************************************************************/
 static void efm_eth_writeReg(rt_uint8_t addr, rt_uint8_t data)
 {
-	efm_eth_sendCmd(ENC28J60_WRITE_CTRL_REG, addr, &data);
+    efm_eth_sendCmd(ENC28J60_WRITE_CTRL_REG, addr, &data);
 }
 
 /***************************************************************************//**
@@ -304,25 +304,25 @@ static void efm_eth_writeReg(rt_uint8_t addr, rt_uint8_t data)
  ******************************************************************************/
 static rt_uint16_t efm_eth_readPhy(rt_uint8_t addr)
 {
-	rt_uint16_t ret;
+    rt_uint16_t ret;
 
-	eth_debug("ETH: *** read PHY %x\n", addr);
+    eth_debug("ETH: *** read PHY %x\n", addr);
 
-	/* Set PHY register address */
-	efm_eth_writeReg(MIREGADR, addr);
+    /* Set PHY register address */
+    efm_eth_writeReg(MIREGADR, addr);
 
-	/* Start read operation */
-	efm_eth_writeReg(MICMD, MICMD_MIIRD);
-	/* Waiting for at least 10.24 uS */
-	while(efm_eth_readReg(MISTAT) & MISTAT_BUSY);
+    /* Start read operation */
+    efm_eth_writeReg(MICMD, MICMD_MIIRD);
+    /* Waiting for at least 10.24 uS */
+    while(efm_eth_readReg(MISTAT) & MISTAT_BUSY);
 
-	/* Stop read operation */
-	efm_eth_writeReg(MICMD, 0x00);
+    /* Stop read operation */
+    efm_eth_writeReg(MICMD, 0x00);
 
-	/* Get the result */
-	ret = (rt_uint16_t)efm_eth_readReg(MIRDL);
-	ret |= (rt_uint16_t)efm_eth_readReg(MIRDH) << 8;
-	return ret;
+    /* Get the result */
+    ret = (rt_uint16_t)efm_eth_readReg(MIRDL);
+    ret |= (rt_uint16_t)efm_eth_readReg(MIRDH) << 8;
+    return ret;
 }
 
 /***************************************************************************//**
@@ -341,82 +341,82 @@ static rt_uint16_t efm_eth_readPhy(rt_uint8_t addr)
  ******************************************************************************/
 static void efm_eth_writePhy(rt_uint8_t addr, rt_uint16_t data)
 {
-	eth_debug("ETH: *** write PHY %x (%x)\n", addr, data);
+    eth_debug("ETH: *** write PHY %x (%x)\n", addr, data);
 
-	/* Set PHY register address */
-	efm_eth_writeReg(MIREGADR, addr);
+    /* Set PHY register address */
+    efm_eth_writeReg(MIREGADR, addr);
 
-	/* Set data */
-	efm_eth_writeReg(MIWRL, data);
-	efm_eth_writeReg(MIWRH, data >> 8);
-	/* Waiting for at least 10.24 uS */
-	while(efm_eth_readReg(MISTAT) & MISTAT_BUSY);
+    /* Set data */
+    efm_eth_writeReg(MIWRL, data);
+    efm_eth_writeReg(MIWRH, data >> 8);
+    /* Waiting for at least 10.24 uS */
+    while(efm_eth_readReg(MISTAT) & MISTAT_BUSY);
 }
 
 /***************************************************************************//**
  * @brief
- *	Interrupt handler of Ethernet device
+ *  Interrupt handler of Ethernet device
  *
  * @details
  *
  * @note
  *
  * @param[in] dev
- *	Pointer to device descriptor
+ *  Pointer to device descriptor
  ******************************************************************************/
 void efm_eth_isr(rt_device_t dev)
 {
-	rt_uint8_t reg_eir, data;
-	volatile rt_uint8_t cnt;
+    rt_uint8_t reg_eir, data;
+    volatile rt_uint8_t cnt;
 
-	/* Disable RX and other interrutps */
-	data = EIE_PKTIE | EIE_INTIE;
-	efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIE, &data);
+    /* Disable RX and other interrutps */
+    data = EIE_PKTIE | EIE_INTIE;
+    efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIE, &data);
 
-	/* Get interrupt flag */
-	efm_eth_sendCmd(ENC28J60_READ_CTRL_REG, EIR, ®_eir);
+    /* Get interrupt flag */
+    efm_eth_sendCmd(ENC28J60_READ_CTRL_REG, EIR, ®_eir);
 
-	data = 0;
-	/* DMA completed */
-	if (reg_eir & EIR_DMAIF)
-	{
-		data |= (rt_uint8_t)EIR_DMAIF;
-	}
-	/* Link Changed */
-	if (reg_eir & EIR_LINKIF)
-	{
-		/* Read PHIR to clear the flag */
-		efm_eth_readPhy(PHIR);
-	}
-	/* TX done */
-	if (reg_eir & EIR_TXIF)
-	{
-		data |= (rt_uint8_t)EIR_TXIF;
-	}
-	/* TX error */
-	if (reg_eir & EIR_TXERIF)
-	{
-		data |= (rt_uint8_t)EIR_TXERIF;
-	}
-	/* RX error */
-	if (reg_eir & EIR_RXERIF)
-	{
-		data |= (rt_uint8_t)EIR_RXERIF;
-	}
-	/* Clear flags */
-	efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIR, &data);
+    data = 0;
+    /* DMA completed */
+    if (reg_eir & EIR_DMAIF)
+    {
+        data |= (rt_uint8_t)EIR_DMAIF;
+    }
+    /* Link Changed */
+    if (reg_eir & EIR_LINKIF)
+    {
+        /* Read PHIR to clear the flag */
+        efm_eth_readPhy(PHIR);
+    }
+    /* TX done */
+    if (reg_eir & EIR_TXIF)
+    {
+        data |= (rt_uint8_t)EIR_TXIF;
+    }
+    /* TX error */
+    if (reg_eir & EIR_TXERIF)
+    {
+        data |= (rt_uint8_t)EIR_TXERIF;
+    }
+    /* RX error */
+    if (reg_eir & EIR_RXERIF)
+    {
+        data |= (rt_uint8_t)EIR_RXERIF;
+    }
+    /* Clear flags */
+    efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIR, &data);
 
-	/* Get packet counter (Errata 6) */
-	efm_eth_sendCmd(ENC28J60_READ_CTRL_REG, EPKTCNT, (rt_uint8_t *)&cnt);
-	if (cnt)
-	{
-	    /* Inform Ethernet thread */
-		eth_device_ready(ð_dev);
-	}
+    /* Get packet counter (Errata 6) */
+    efm_eth_sendCmd(ENC28J60_READ_CTRL_REG, EPKTCNT, (rt_uint8_t *)&cnt);
+    if (cnt)
+    {
+        /* Inform Ethernet thread */
+        eth_device_ready(ð_dev);
+    }
 
-	/* Enable other interrupts */
-	data = EIE_INTIE;
-	efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, EIE, &data);
+    /* Enable other interrupts */
+    data = EIE_INTIE;
+    efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, EIE, &data);
 }
 
 /***************************************************************************//**
@@ -435,119 +435,119 @@ void efm_eth_isr(rt_device_t dev)
  ******************************************************************************/
 static rt_err_t efm_eth_init(rt_device_t dev)
 {
-	rt_uint16_t reg_phy;
-	rt_uint8_t data;
+    rt_uint16_t reg_phy;
+    rt_uint8_t data;
 
-	/* Reset chip select */
-	efm_eth_cs(0);
-	/* Software reset */
-	efm_eth_sendCmd(ENC28J60_SOFT_RESET, EFM32_NO_DATA, EFM32_NO_POINTER);
-	/* Waiting for at least 1 ms (Errata 2) */
-	rt_thread_delay(ETH_PERIOD_WAIT_INIT);
-	ethNxtPkt = RXSTART_INIT;
-	ethBank = 0;
+    /* Reset chip select */
+    efm_eth_cs(0);
+    /* Software reset */
+    efm_eth_sendCmd(ENC28J60_SOFT_RESET, EFM32_NO_DATA, EFM32_NO_POINTER);
+    /* Waiting for at least 1 ms (Errata 2) */
+    rt_thread_delay(ETH_PERIOD_WAIT_INIT);
+    ethNxtPkt = RXSTART_INIT;
+    ethBank = 0;
 
-	/* Init RX buffer */
-	efm_eth_writeReg(ERXSTL, RXSTART_INIT & 0xFF);
-	efm_eth_writeReg(ERXSTH, RXSTART_INIT >> 8);
-	efm_eth_writeReg(ERXNDL, RXSTOP_INIT & 0xFF);
-	efm_eth_writeReg(ERXNDH, RXSTOP_INIT >> 8);
-	efm_eth_writeReg(ERXRDPTL, RXSTOP_INIT & 0xFF);
-	efm_eth_writeReg(ERXRDPTH, RXSTOP_INIT >> 8);
+    /* Init RX buffer */
+    efm_eth_writeReg(ERXSTL, RXSTART_INIT & 0xFF);
+    efm_eth_writeReg(ERXSTH, RXSTART_INIT >> 8);
+    efm_eth_writeReg(ERXNDL, RXSTOP_INIT & 0xFF);
+    efm_eth_writeReg(ERXNDH, RXSTOP_INIT >> 8);
+    efm_eth_writeReg(ERXRDPTL, RXSTOP_INIT & 0xFF);
+    efm_eth_writeReg(ERXRDPTH, RXSTOP_INIT >> 8);
 
-	/* Init TX buffer */
-	efm_eth_writeReg(ETXSTL, TXSTART_INIT & 0xFF);
-	efm_eth_writeReg(ETXSTH, TXSTART_INIT >> 8);
-	efm_eth_writeReg(ETXNDL, TXSTOP_INIT & 0xFF);
-	efm_eth_writeReg(ETXNDH, TXSTOP_INIT >> 8);
-	efm_eth_writeReg(EWRPTL, TXSTART_INIT & 0xFF);
-	efm_eth_writeReg(EWRPTH, TXSTART_INIT >> 8);
+    /* Init TX buffer */
+    efm_eth_writeReg(ETXSTL, TXSTART_INIT & 0xFF);
+    efm_eth_writeReg(ETXSTH, TXSTART_INIT >> 8);
+    efm_eth_writeReg(ETXNDL, TXSTOP_INIT & 0xFF);
+    efm_eth_writeReg(ETXNDH, TXSTOP_INIT >> 8);
+    efm_eth_writeReg(EWRPTL, TXSTART_INIT & 0xFF);
+    efm_eth_writeReg(EWRPTH, TXSTART_INIT >> 8);
 
-	/* Init RX filters */
-	/* For broadcast packets we allow only ARP packtets
-	   All other packets should be unicast only for our mac (MAADR)
+    /* Init RX filters */
+    /* For broadcast packets we allow only ARP packtets
+       All other packets should be unicast only for our mac (MAADR)
 
-	   The pattern to match on is therefore
-	   Type                    ETH.DST
-	   ARP                     BROADCAST
-	   06 08 -- -- -- -- -- -- ff ff ff ff ff ff
-	   These poitions are: 11 0000 0011 1111 in binary and 30 3f in hex
-	   Checksum for theses bytes is: f7 f9 */
-	efm_eth_writeReg(EPMM0, 0x3f);
-	efm_eth_writeReg(EPMM1, 0x30);
-	efm_eth_writeReg(EPMCSL, 0xf9);
-	efm_eth_writeReg(EPMCSH, 0xf7);
-	efm_eth_writeReg(ERXFCON, ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_PMEN);
-	//efm_eth_writeReg(ERXFCON, ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN);
-	/* Waiting For OST: The OST does not expire until 7500 OSC1 clock cycles (300 uS)
-	    pass after Power-on Reset or wake-up from Power-Down mode occurs */
+       The pattern to match on is therefore
+       Type                    ETH.DST
+       ARP                     BROADCAST
+       06 08 -- -- -- -- -- -- ff ff ff ff ff ff
+       These poitions are: 11 0000 0011 1111 in binary and 30 3f in hex
+       Checksum for theses bytes is: f7 f9 */
+    efm_eth_writeReg(EPMM0, 0x3f);
+    efm_eth_writeReg(EPMM1, 0x30);
+    efm_eth_writeReg(EPMCSL, 0xf9);
+    efm_eth_writeReg(EPMCSH, 0xf7);
+    efm_eth_writeReg(ERXFCON, ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_PMEN);
+    //efm_eth_writeReg(ERXFCON, ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN);
+    /* Waiting For OST: The OST does not expire until 7500 OSC1 clock cycles (300 uS)
+        pass after Power-on Reset or wake-up from Power-Down mode occurs */
 
-	/* Init MAC */
-	/* Enable RX, IEEE defined flow control */
-	efm_eth_writeReg(MACON1, MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS);
-	/* Enable padding to 60 bytes, CRC and frame length status reporting */
+    /* Init MAC */
+    /* Enable RX, IEEE defined flow control */
+    efm_eth_writeReg(MACON1, MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS);
+    /* Enable padding to 60 bytes, CRC and frame length status reporting */
 #if defined(ETH_HALF_DUPLEX)
-	efm_eth_writeReg(MACON3, MACON3_PADCFG0 | MACON3_TXCRCEN | MACON3_FRMLNEN);
-	efm_eth_writeReg(MACON4, MACON4_DEFER);
+    efm_eth_writeReg(MACON3, MACON3_PADCFG0 | MACON3_TXCRCEN | MACON3_FRMLNEN);
+    efm_eth_writeReg(MACON4, MACON4_DEFER);
 #else
-	efm_eth_writeReg(MACON3, \
-		MACON3_PADCFG0 | MACON3_TXCRCEN | MACON3_FRMLNEN | MACON3_FULDPX);
+    efm_eth_writeReg(MACON3, \
+        MACON3_PADCFG0 | MACON3_TXCRCEN | MACON3_FRMLNEN | MACON3_FULDPX);
 #endif
-	/* Set the maximum packet length */
-	efm_eth_writeReg(MAMXFLL, MAX_FRAMELEN & 0xFF);
-	efm_eth_writeReg(MAMXFLH, MAX_FRAMELEN >> 8);
-	/* Set inter-packet gap (back-to-back). Full-Duplex: 0x15, Half-Duplex: 0x12 */
+    /* Set the maximum packet length */
+    efm_eth_writeReg(MAMXFLL, MAX_FRAMELEN & 0xFF);
+    efm_eth_writeReg(MAMXFLH, MAX_FRAMELEN >> 8);
+    /* Set inter-packet gap (back-to-back). Full-Duplex: 0x15, Half-Duplex: 0x12 */
 #if defined(ETH_HALF_DUPLEX)
-	efm_eth_writeReg(MABBIPG, 0x12);
+    efm_eth_writeReg(MABBIPG, 0x12);
 #else
-	efm_eth_writeReg(MABBIPG, 0x15);
+    efm_eth_writeReg(MABBIPG, 0x15);
 #endif
-	/* Set inter-packet gap (non-back-to-back).
-	    Full-Duplex: 0x0012, Half-Duplex: 0x0C12 */
-	efm_eth_writeReg(MAIPGL, 0x12);
+    /* Set inter-packet gap (non-back-to-back).
+        Full-Duplex: 0x0012, Half-Duplex: 0x0C12 */
+    efm_eth_writeReg(MAIPGL, 0x12);
 #if defined(ETH_HALF_DUPLEX)
-	efm_eth_writeReg(MAIPGH, 0x0C);
-	/* Set retransmission and collision window */
-	efm_eth_writeReg(MACLCON1, 0x0F);
-	efm_eth_writeReg(MACLCON2, 0x37);
+    efm_eth_writeReg(MAIPGH, 0x0C);
+    /* Set retransmission and collision window */
+    efm_eth_writeReg(MACLCON1, 0x0F);
+    efm_eth_writeReg(MACLCON2, 0x37);
 #endif
-	/* Set MAC address
-	    NOTE: MAC address in ENC28J60 is byte-backward */
-	efm_eth_writeReg(MAADR1, eth_addr[0]);
-	efm_eth_writeReg(MAADR2, eth_addr[1]);
-	efm_eth_writeReg(MAADR3, eth_addr[2]);
-	efm_eth_writeReg(MAADR4, eth_addr[3]);
-	efm_eth_writeReg(MAADR5, eth_addr[4]);
-	efm_eth_writeReg(MAADR6, eth_addr[5]);
+    /* Set MAC address
+        NOTE: MAC address in ENC28J60 is byte-backward */
+    efm_eth_writeReg(MAADR1, eth_addr[0]);
+    efm_eth_writeReg(MAADR2, eth_addr[1]);
+    efm_eth_writeReg(MAADR3, eth_addr[2]);
+    efm_eth_writeReg(MAADR4, eth_addr[3]);
+    efm_eth_writeReg(MAADR5, eth_addr[4]);
+    efm_eth_writeReg(MAADR6, eth_addr[5]);
 
-	/* Init PHY */
+    /* Init PHY */
 #if defined(ETH_HALF_DUPLEX)
-	reg_phy = efm_eth_readPhy(PHCON2);
-	efm_eth_writePhy(PHCON2, reg_phy | PHCON2_HDLDIS);
+    reg_phy = efm_eth_readPhy(PHCON2);
+    efm_eth_writePhy(PHCON2, reg_phy | PHCON2_HDLDIS);
 #else
-	reg_phy = efm_eth_readPhy(PHCON1);
-	efm_eth_writePhy(PHCON1, reg_phy | PHCON1_PDPXMD);
+    reg_phy = efm_eth_readPhy(PHCON1);
+    efm_eth_writePhy(PHCON1, reg_phy | PHCON1_PDPXMD);
 #endif
-	/* LEDA: Display link status;
-	   LEDB: Display transmit and receive activity */
-	reg_phy = efm_eth_readPhy(PHLCON);
-	efm_eth_writePhy(PHLCON, (reg_phy & 0xF00F) | 0x0470);
+    /* LEDA: Display link status;
+       LEDB: Display transmit and receive activity */
+    reg_phy = efm_eth_readPhy(PHLCON);
+    efm_eth_writePhy(PHLCON, (reg_phy & 0xF00F) | 0x0470);
 
-	/* Disable clock output */
-	efm_eth_writeReg(ECOCON, 0x00);
+    /* Disable clock output */
+    efm_eth_writeReg(ECOCON, 0x00);
 
-	/* Clear interrutp flags */
-	data = EIR_DMAIF | EIR_TXIF | EIR_TXERIF | EIR_RXERIF;
-	efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIR, &data);
-	/* Enable interrutps */
-	data = EIE_INTIE | EIE_PKTIE | EIE_TXIE;
-	efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, EIE, &data);
-	/* Enable RX */
-	data = ECON1_RXEN;
-	efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, ECON1, &data);
+    /* Clear interrutp flags */
+    data = EIR_DMAIF | EIR_TXIF | EIR_TXERIF | EIR_RXERIF;
+    efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIR, &data);
+    /* Enable interrutps */
+    data = EIE_INTIE | EIE_PKTIE | EIE_TXIE;
+    efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, EIE, &data);
+    /* Enable RX */
+    data = ECON1_RXEN;
+    efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, ECON1, &data);
 
-	eth_debug("ETH: Init OK\n");
-	return RT_EOK;
+    eth_debug("ETH: Init OK\n");
+    return RT_EOK;
 }
 
 /***************************************************************************//**
@@ -569,8 +569,8 @@ static rt_err_t efm_eth_init(rt_device_t dev)
  ******************************************************************************/
 static rt_err_t efm_eth_open(rt_device_t dev, rt_uint16_t oflag)
 {
-	eth_debug("ETH: Open, flag %x\n", eth_dev.parent.flag);
-	return RT_EOK;
+    eth_debug("ETH: Open, flag %x\n", eth_dev.parent.flag);
+    return RT_EOK;
 }
 
 /***************************************************************************//**
@@ -589,8 +589,8 @@ static rt_err_t efm_eth_open(rt_device_t dev, rt_uint16_t oflag)
  ******************************************************************************/
 static rt_err_t efm_eth_close(rt_device_t dev)
 {
-	eth_debug("ETH: Close, flag %x\n", eth_dev.parent.flag);
-	return RT_EOK;
+    eth_debug("ETH: Close, flag %x\n", eth_dev.parent.flag);
+    return RT_EOK;
 }
 
 /***************************************************************************//**
@@ -617,10 +617,10 @@ static rt_err_t efm_eth_close(rt_device_t dev)
  *   Number of read bytes
  ******************************************************************************/
 static rt_size_t efm_eth_read(
-	rt_device_t 	dev,
-	rt_off_t 		pos,
-	void 			*buffer,
-	rt_size_t 		size)
+    rt_device_t     dev,
+    rt_off_t        pos,
+    void            *buffer,
+    rt_size_t       size)
 {
     rt_set_errno(-RT_ENOSYS);
     return 0;
@@ -650,10 +650,10 @@ static rt_size_t efm_eth_read(
  *   Number of written bytes
  ******************************************************************************/
 static rt_size_t efm_eth_write (
-	rt_device_t 	dev,
-	rt_off_t 		pos,
-	const void 		*buffer,
-	rt_size_t 		size)
+    rt_device_t     dev,
+    rt_off_t        pos,
+    const void      *buffer,
+    rt_size_t       size)
 {
     rt_set_errno(-RT_ENOSYS);
     return 0;
@@ -674,35 +674,35 @@ static rt_size_t efm_eth_write (
 *   Ethernet control command
 *
 * @param[in] args
-*	Arguments
+*   Arguments
 *
 * @return
 *   Error code
 ******************************************************************************/
 static rt_err_t efm_eth_control (
-	rt_device_t 	dev,
-	rt_uint8_t 		cmd,
-	void 			*args)
+    rt_device_t     dev,
+    rt_uint8_t      cmd,
+    void            *args)
 {
-	rt_err_t ret;
+    rt_err_t ret;
 
-	ret = -RT_ERROR;
-	switch(cmd)
-	{
-	case NIOCTL_GADDR:
-		/* Get MAC address */
-		if(args)
-		{
-			rt_memcpy(args, eth_addr, sizeof(eth_addr));
-			ret = RT_EOK;
-		}
-		break;
+    ret = -RT_ERROR;
+    switch(cmd)
+    {
+    case NIOCTL_GADDR:
+        /* Get MAC address */
+        if(args)
+        {
+            rt_memcpy(args, eth_addr, sizeof(eth_addr));
+            ret = RT_EOK;
+        }
+        break;
 
-	default :
-		break;
-	}
+    default :
+        break;
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 /***************************************************************************//**
@@ -721,43 +721,43 @@ static rt_err_t efm_eth_control (
 ******************************************************************************/
 struct pbuf *efm_eth_rx(rt_device_t dev)
 {
-	rt_uint8_t buf_ins[5], buf_read[6];
-	rt_uint8_t data, reg_eie;
-	rt_uint16_t len_rx, sta_rx;
-	struct pbuf* p;
+    rt_uint8_t buf_ins[5], buf_read[6];
+    rt_uint8_t data, reg_eie;
+    rt_uint16_t len_rx, sta_rx;
+    struct pbuf* p;
 
     /* Lock device */
     rt_sem_take(ðLock, RT_WAITING_FOREVER);
 
     /* Disable interrupts */
-	data = EIE_INTIE;
-	efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIE, &data);
+    data = EIE_INTIE;
+    efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIE, &data);
 
-	p = RT_NULL;
-	reg_eie = 0;
+    p = RT_NULL;
+    reg_eie = 0;
     if (efm_eth_readReg(EPKTCNT))
     {
         /* Set read pointer to the start of RX packet */
         efm_eth_writeReg(ERDPTL, ethNxtPkt & 0xFF);
         efm_eth_writeReg(ERDPTH, ethNxtPkt >> 8);
 
-		/* Send read buffer command */
-		efm_eth_sendCmd(ENC28J60_READ_BUF_MEM, EFM32_NO_DATA, EFM32_NO_POINTER);
-		/* Build instruction buffer */
-		buf_ins[0] = 0x00;
-		*(rt_uint8_t **)(&buf_ins[1]) = buf_read;
-		/* Read packet header */
-		if (spi->read(spi, EFM32_NO_DATA, buf_ins, sizeof(buf_read)) == 0)
-		{
-			eth_debug("ETH: RX header failed!\n");
-		}
+        /* Send read buffer command */
+        efm_eth_sendCmd(ENC28J60_READ_BUF_MEM, EFM32_NO_DATA, EFM32_NO_POINTER);
+        /* Build instruction buffer */
+        buf_ins[0] = 0x00;
+        *(rt_uint8_t **)(&buf_ins[1]) = buf_read;
+        /* Read packet header */
+        if (spi->read(spi, EFM32_NO_DATA, buf_ins, sizeof(buf_read)) == 0)
+        {
+            eth_debug("ETH: RX header failed!\n");
+        }
 
-		ethNxtPkt = buf_read[0] | (buf_read[1] << 8);
-		len_rx = buf_read[2] | (buf_read[3] << 8);
-		sta_rx = buf_read[4] | (buf_read[5] << 8);
-		eth_debug("ETH: RX header ethNxtPkt %x, len_rx %x, sta_rx %x\n",
-			ethNxtPkt, len_rx, sta_rx);
-		/* Check if OK */
+        ethNxtPkt = buf_read[0] | (buf_read[1] << 8);
+        len_rx = buf_read[2] | (buf_read[3] << 8);
+        sta_rx = buf_read[4] | (buf_read[5] << 8);
+        eth_debug("ETH: RX header ethNxtPkt %x, len_rx %x, sta_rx %x\n",
+            ethNxtPkt, len_rx, sta_rx);
+        /* Check if OK */
         if (sta_rx & 0x80)
         {
             /* Allocate pbuf */
@@ -768,67 +768,67 @@ struct pbuf *efm_eth_rx(rt_device_t dev)
 
                 for (q = p; q != RT_NULL; q= q->next)
                 {
-					/* Build instruction buffer */
-					buf_ins[0] = 0x00;
-					*(rt_uint8_t **)(&buf_ins[1]) = q->payload;
-					/* Read packet header */
-					if (spi->read(spi, EFM32_NO_DATA, buf_ins, q->len) == 0)
-					{
-						eth_debug("ETH: RX payload failed!\n");
-					}
+                    /* Build instruction buffer */
+                    buf_ins[0] = 0x00;
+                    *(rt_uint8_t **)(&buf_ins[1]) = q->payload;
+                    /* Read packet header */
+                    if (spi->read(spi, EFM32_NO_DATA, buf_ins, q->len) == 0)
+                    {
+                        eth_debug("ETH: RX payload failed!\n");
+                    }
 #ifdef EFM32_ETHERNET_DEBUG
-					{
-						rt_uint8_t *temp = (rt_uint8_t *)q->payload;
-						rt_uint32_t i;
+                    {
+                        rt_uint8_t *temp = (rt_uint8_t *)q->payload;
+                        rt_uint32_t i;
 
-						eth_debug("ETH: ***** read RX (q->len %x) *****\n", q->len);
-						for (i = 0; i < q->len; i += 8)
-						{
-							eth_debug("%02x %02x %02x %02x %02x %02x %02x %02x | %c %c %c %c %c %c %c %c\n",
-								temp[i], temp[i + 1], temp[i + 2], temp[i + 3],
-								temp[i + 4], temp[i + 5], temp[i + 6], temp[i + 7],
-								temp[i], temp[i + 1], temp[i + 2], temp[i + 3],
-								temp[i + 4], temp[i + 5], temp[i + 6], temp[i + 7]);
-						}
-					}
+                        eth_debug("ETH: ***** read RX (q->len %x) *****\n", q->len);
+                        for (i = 0; i < q->len; i += 8)
+                        {
+                            eth_debug("%02x %02x %02x %02x %02x %02x %02x %02x | %c %c %c %c %c %c %c %c\n",
+                                temp[i], temp[i + 1], temp[i + 2], temp[i + 3],
+                                temp[i + 4], temp[i + 5], temp[i + 6], temp[i + 7],
+                                temp[i], temp[i + 1], temp[i + 2], temp[i + 3],
+                                temp[i + 4], temp[i + 5], temp[i + 6], temp[i + 7]);
+                        }
+                    }
 #endif
                 }
             }
-			else
-			{
-				eth_debug("ETH: No memory for pbuf!!!\n");
-			}
+            else
+            {
+                eth_debug("ETH: No memory for pbuf!!!\n");
+            }
         }
-		else
-		{
+        else
+        {
             eth_debug("ETH: Invalid CRC or symbol error occurred!\n");
         }
-		efm_eth_cs(0);
+        efm_eth_cs(0);
 
         /* Free buffer */
         efm_eth_writeReg(ERXRDPTL, ethNxtPkt & 0xFF);
         efm_eth_writeReg(ERXRDPTH, ethNxtPkt >> 8);
 
         /* Decrease counter */
-		data = ECON2_PKTDEC;
+        data = ECON2_PKTDEC;
         efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, ECON2, &data);
     }
-	else
-	{
-		/* Enable RX */
-		data = ECON1_RXEN;
-		efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, ECON1, &data);
+    else
+    {
+        /* Enable RX */
+        data = ECON1_RXEN;
+        efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, ECON1, &data);
 
-	    reg_eie |= EIE_PKTIE;
-		eth_debug("ETH: Enable RX interrupt\n");
-	}
-	eth_debug("ETH: RX counter %x\n", efm_eth_readReg(EPKTCNT));
+        reg_eie |= EIE_PKTIE;
+        eth_debug("ETH: Enable RX interrupt\n");
+    }
+    eth_debug("ETH: RX counter %x\n", efm_eth_readReg(EPKTCNT));
 
     /* Enable interrupts */
-	reg_eie |= EIE_INTIE;
-	efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, EIE, ®_eie);
+    reg_eie |= EIE_INTIE;
+    efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, EIE, ®_eie);
 
-	/* Unlock device */
+    /* Unlock device */
     rt_sem_release(ðLock);
 
     return p;
@@ -849,76 +849,76 @@ struct pbuf *efm_eth_rx(rt_device_t dev)
 *   Pointer to packet buffer
 *
 * @return
-*	Error code
+*   Error code
 ******************************************************************************/
 rt_err_t efm_eth_tx(rt_device_t dev, struct pbuf* p)
 {
-	rt_uint8_t data;
-	struct pbuf* q;
+    rt_uint8_t data;
+    struct pbuf* q;
 
     /* Lock device */
     rt_sem_take(ðLock, RT_WAITING_FOREVER);
 
     /* Disable interrupts */
-	data = EIE_INTIE;
-	efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIE, &data);
+    data = EIE_INTIE;
+    efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIE, &data);
 
-	/* Set write pointer to the start of TX buffer */
-	efm_eth_writeReg(EWRPTL, TXSTART_INIT & 0xFF);
-	efm_eth_writeReg(EWRPTH, TXSTART_INIT >> 8);
-	/* Set buffer end pointer according to the packet size */
-	efm_eth_writeReg(ETXNDL, (TXSTART_INIT + p->tot_len + 1) & 0xFF);
-	efm_eth_writeReg(ETXNDH, (TXSTART_INIT + p->tot_len + 1) >> 8);
+    /* Set write pointer to the start of TX buffer */
+    efm_eth_writeReg(EWRPTL, TXSTART_INIT & 0xFF);
+    efm_eth_writeReg(EWRPTH, TXSTART_INIT >> 8);
+    /* Set buffer end pointer according to the packet size */
+    efm_eth_writeReg(ETXNDL, (TXSTART_INIT + p->tot_len + 1) & 0xFF);
+    efm_eth_writeReg(ETXNDH, (TXSTART_INIT + p->tot_len + 1) >> 8);
 
-	/* Send write buffer command */
-	data = 0x00; 	/* Control byte */
-	efm_eth_sendCmd(ENC28J60_WRITE_BUF_MEM, EFM32_NO_DATA, &data);
-	/* Send data */
-	for (q = p; q != NULL; q = q->next)
-	{
-		if (spi->write(spi, EFM32_NO_DATA, q->payload, q->len) == 0)
-		{
-			eth_debug("ETH: TX failed!\n");
-			return -RT_ERROR;
-		}
+    /* Send write buffer command */
+    data = 0x00;    /* Control byte */
+    efm_eth_sendCmd(ENC28J60_WRITE_BUF_MEM, EFM32_NO_DATA, &data);
+    /* Send data */
+    for (q = p; q != NULL; q = q->next)
+    {
+        if (spi->write(spi, EFM32_NO_DATA, q->payload, q->len) == 0)
+        {
+            eth_debug("ETH: TX failed!\n");
+            return -RT_ERROR;
+        }
 #ifdef EFM32_ETHERNET_DEBUG
-		{
-			rt_uint8_t *temp = (rt_uint8_t *)q->payload;
-			rt_uint32_t i;
+        {
+            rt_uint8_t *temp = (rt_uint8_t *)q->payload;
+            rt_uint32_t i;
 
-			eth_debug("ETH: ***** write TX (len %d) *****\n", p->len);
-			for (i = 0; i < q->len; i += 8)
-			{
-				eth_debug("%02x %02x %02x %02x %02x %02x %02x %02x | %c %c %c %c %c %c %c %c\n",
-					temp[i], temp[i + 1], temp[i + 2], temp[i + 3],
-					temp[i + 4], temp[i + 5], temp[i + 6], temp[i + 7],
-					temp[i], temp[i + 1], temp[i + 2], temp[i + 3],
-					temp[i + 4], temp[i + 5], temp[i + 6], temp[i + 7]);
-			}
-		}
+            eth_debug("ETH: ***** write TX (len %d) *****\n", p->len);
+            for (i = 0; i < q->len; i += 8)
+            {
+                eth_debug("%02x %02x %02x %02x %02x %02x %02x %02x | %c %c %c %c %c %c %c %c\n",
+                    temp[i], temp[i + 1], temp[i + 2], temp[i + 3],
+                    temp[i + 4], temp[i + 5], temp[i + 6], temp[i + 7],
+                    temp[i], temp[i + 1], temp[i + 2], temp[i + 3],
+                    temp[i + 4], temp[i + 5], temp[i + 6], temp[i + 7]);
+            }
+        }
 #endif
-	}
-	efm_eth_cs(0);
-	/* Start TX */
-	data = ECON1_TXRTS;
-	efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, ECON1, &data);
-	/* Errata 12 */
-	if (efm_eth_readReg(EIR) & EIR_TXERIF)
-	{
-		efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, ECON1, &data);
-		data = EIR_TXERIF;
-		efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIR, &data);
-		data = ECON1_TXRTS;
-		efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, ECON1, &data);
-	}
+    }
+    efm_eth_cs(0);
+    /* Start TX */
+    data = ECON1_TXRTS;
+    efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, ECON1, &data);
+    /* Errata 12 */
+    if (efm_eth_readReg(EIR) & EIR_TXERIF)
+    {
+        efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, ECON1, &data);
+        data = EIR_TXERIF;
+        efm_eth_sendCmd(ENC28J60_BIT_FIELD_CLR, EIR, &data);
+        data = ECON1_TXRTS;
+        efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, ECON1, &data);
+    }
 
-	/* Waiting for a while */
-	rt_thread_delay(ETH_PERIOD_WAIT_INIT);
+    /* Waiting for a while */
+    rt_thread_delay(ETH_PERIOD_WAIT_INIT);
     /* Enable interrupts */
-	data = EIE_INTIE;
-	efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, EIE, &data);
+    data = EIE_INTIE;
+    efm_eth_sendCmd(ENC28J60_BIT_FIELD_SET, EIE, &data);
 
-	/* Unlock device */
+    /* Unlock device */
     rt_sem_release(ðLock);
 
     return RT_EOK;
@@ -926,164 +926,164 @@ rt_err_t efm_eth_tx(rt_device_t dev, struct pbuf* p)
 
 /***************************************************************************//**
 * @brief
-*	Initialize all Ethernet related hardware and register the device to kernel
+*   Initialize all Ethernet related hardware and register the device to kernel
 *
 * @details
 *
 * @note
 *
 * @return
-*	Error code
+*   Error code
 ******************************************************************************/
 rt_err_t efm_hw_eth_init(void)
 {
-	struct efm32_usart_device_t *usart;
-	efm32_irq_hook_init_t 		hook;
+    struct efm32_usart_device_t *usart;
+    efm32_irq_hook_init_t       hook;
 
-	do
-	{
-		/* Find SPI device */
-		spi = rt_device_find(ETH_USING_DEVICE_NAME);
-		if (spi == RT_NULL)
-		{
-			eth_debug("ETH: Can't find device %s!\n",
-				ETH_USING_DEVICE_NAME);
-			break;
-		}
-		eth_debug("ETH: Find device %s\n", ETH_USING_DEVICE_NAME);
+    do
+    {
+        /* Find SPI device */
+        spi = rt_device_find(ETH_USING_DEVICE_NAME);
+        if (spi == RT_NULL)
+        {
+            eth_debug("ETH: Can't find device %s!\n",
+                ETH_USING_DEVICE_NAME);
+            break;
+        }
+        eth_debug("ETH: Find device %s\n", ETH_USING_DEVICE_NAME);
 
-		/* Config chip slect pin */
-		usart = (struct efm32_usart_device_t *)(spi->user_data);
-		if (!(usart->state & USART_STATE_AUTOCS))
-		{
-			GPIO_PinModeSet(ETH_CS_PORT, ETH_CS_PIN, gpioModePushPull, 1);
-			ethAutoCs = false;
-		}
-		/* Config reset pin */
-		GPIO_PinModeSet(ETH_RESET_PORT, ETH_RESET_PIN, gpioModePushPull, 0);
-		/* Config interrupt pin */
-		GPIO_PinModeSet(ETH_INT_PORT, ETH_INT_PIN, gpioModeInput, 1);
+        /* Config chip slect pin */
+        usart = (struct efm32_usart_device_t *)(spi->user_data);
+        if (!(usart->state & USART_STATE_AUTOCS))
+        {
+            GPIO_PinModeSet(ETH_CS_PORT, ETH_CS_PIN, gpioModePushPull, 1);
+            ethAutoCs = false;
+        }
+        /* Config reset pin */
+        GPIO_PinModeSet(ETH_RESET_PORT, ETH_RESET_PIN, gpioModePushPull, 0);
+        /* Config interrupt pin */
+        GPIO_PinModeSet(ETH_INT_PORT, ETH_INT_PIN, gpioModeInput, 1);
 
-		/* Config interrupt */
-		hook.type		= efm32_irq_type_gpio;
-		hook.unit		= ETH_INT_PIN;
-		hook.cbFunc 	= efm_eth_isr;
-		hook.userPtr	= RT_NULL;
-		efm32_irq_hook_register(&hook);
-		/* Clear pending interrupt */
-		BITBAND_Peripheral(&(GPIO->IFC), ETH_INT_PIN, 0x1UL);
-		/* Set falling edge interrupt and clear/enable it */
-		GPIO_IntConfig(
-			ETH_INT_PORT,
-			ETH_INT_PIN,
-			false,
-			true,
-			true);
-		if ((rt_uint8_t)ETH_INT_PIN % 2)
-		{
-			NVIC_ClearPendingIRQ(GPIO_ODD_IRQn);
-			NVIC_SetPriority(GPIO_ODD_IRQn, EFM32_IRQ_PRI_DEFAULT);
-			NVIC_EnableIRQ(GPIO_ODD_IRQn);
-		}
-		else
-		{
-			NVIC_ClearPendingIRQ(GPIO_EVEN_IRQn);
-			NVIC_SetPriority(GPIO_EVEN_IRQn, EFM32_IRQ_PRI_DEFAULT);
-			NVIC_EnableIRQ(GPIO_EVEN_IRQn);
-		}
+        /* Config interrupt */
+        hook.type       = efm32_irq_type_gpio;
+        hook.unit       = ETH_INT_PIN;
+        hook.cbFunc     = efm_eth_isr;
+        hook.userPtr    = RT_NULL;
+        efm32_irq_hook_register(&hook);
+        /* Clear pending interrupt */
+        BITBAND_Peripheral(&(GPIO->IFC), ETH_INT_PIN, 0x1UL);
+        /* Set falling edge interrupt and clear/enable it */
+        GPIO_IntConfig(
+            ETH_INT_PORT,
+            ETH_INT_PIN,
+            false,
+            true,
+            true);
+        if ((rt_uint8_t)ETH_INT_PIN % 2)
+        {
+            NVIC_ClearPendingIRQ(GPIO_ODD_IRQn);
+            NVIC_SetPriority(GPIO_ODD_IRQn, EFM32_IRQ_PRI_DEFAULT);
+            NVIC_EnableIRQ(GPIO_ODD_IRQn);
+        }
+        else
+        {
+            NVIC_ClearPendingIRQ(GPIO_EVEN_IRQn);
+            NVIC_SetPriority(GPIO_EVEN_IRQn, EFM32_IRQ_PRI_DEFAULT);
+            NVIC_EnableIRQ(GPIO_EVEN_IRQn);
+        }
 
-		/* Set SPI speed */
-		USART_BaudrateSyncSet(usart->usart_device, 0, ETH_CLK_MAX);
+        /* Set SPI speed */
+        USART_BaudrateSyncSet(usart->usart_device, 0, ETH_CLK_MAX);
 
-		/* Initialize semaphore */
-		rt_sem_init(ðLock, ETH_DEVICE_NAME, 1, RT_IPC_FLAG_FIFO);
+        /* Initialize semaphore */
+        rt_sem_init(ðLock, ETH_DEVICE_NAME, 1, RT_IPC_FLAG_FIFO);
 
-		/* Register Ethernet device */
-		eth_dev.parent.init 	= efm_eth_init;
-		eth_dev.parent.open 	= efm_eth_open;
-		eth_dev.parent.close 	= efm_eth_close;
-		eth_dev.parent.read 	= efm_eth_read;
-		eth_dev.parent.write 	= efm_eth_write;
-		eth_dev.parent.control 	= efm_eth_control;
-		eth_dev.eth_rx 			= efm_eth_rx;
-		eth_dev.eth_tx 			= efm_eth_tx;
-		eth_device_init(ð_dev, ETH_DEVICE_NAME);
+        /* Register Ethernet device */
+        eth_dev.parent.init     = efm_eth_init;
+        eth_dev.parent.open     = efm_eth_open;
+        eth_dev.parent.close    = efm_eth_close;
+        eth_dev.parent.read     = efm_eth_read;
+        eth_dev.parent.write    = efm_eth_write;
+        eth_dev.parent.control  = efm_eth_control;
+        eth_dev.eth_rx          = efm_eth_rx;
+        eth_dev.eth_tx          = efm_eth_tx;
+        eth_device_init(ð_dev, ETH_DEVICE_NAME);
 
-		/* Start device */
-		GPIO_PinOutSet(ETH_RESET_PORT, ETH_RESET_PIN);
+        /* Start device */
+        GPIO_PinOutSet(ETH_RESET_PORT, ETH_RESET_PIN);
 
-		eth_debug("ETH: HW init OK\n");
-		return RT_EOK;
-	} while (0);
+        eth_debug("ETH: HW init OK\n");
+        return RT_EOK;
+    } while (0);
 
-	/* Release buffer */
-	rt_kprintf("ETH: HW init failed!\n");
-	return -RT_ERROR;
+    /* Release buffer */
+    rt_kprintf("ETH: HW init failed!\n");
+    return -RT_ERROR;
 }
 
 /*******************************************************************************
- * 	Export to FINSH
+ *  Export to FINSH
  ******************************************************************************/
-#if	defined(EFM32_USING_ETH_UTILS)
+#if defined(EFM32_USING_ETH_UTILS)
 #ifdef RT_USING_FINSH
 #include 
 
 void list_eth(void)
 {
-	rt_uint16_t reg_phy;
-	rt_uint8_t data;
+    rt_uint16_t reg_phy;
+    rt_uint8_t data;
 
-	rt_kprintf("    ENC28J60 on %s\n", ETH_USING_DEVICE_NAME);
-	rt_kprintf(" ------------------------------\n");
-	reg_phy = efm_eth_readPhy(PHSTAT2);
-	if (reg_phy & PHSTAT2_PLRITY)
-	{
-		rt_kprintf(" Cable polarity is reversed\n");
-	}
-	else
-	{
-		rt_kprintf(" Cable polarity is correct\n");
-	}
-	if (reg_phy & PHSTAT2_DPXSTAT)
-	{
-		rt_kprintf(" Full-duplex mode\n");
-	}
-	else
-	{
-		rt_kprintf(" Half-duplex mode\n");
-	}
-	if (reg_phy & PHSTAT2_LSTAT)
-	{
-		rt_kprintf(" Link is up\n");
-	}
-	else
-	{
-		rt_kprintf(" Link is down\n");
-	}
-	if (reg_phy & PHSTAT2_COLSTAT)
-	{
-		rt_kprintf(" Collision is occuring\n");
-	}
-	else
-	{
-		rt_kprintf(" No collision\n");
-	}
-	if (reg_phy & PHSTAT2_RXSTAT)
-	{
-		rt_kprintf(" RX is busy\n");
-	}
-	else
-	{
-		rt_kprintf(" RX is idle\n");
-	}
-	if (reg_phy & PHSTAT2_TXSTAT)
-	{
-		rt_kprintf(" TX is busy\n");
-	}
-	else
-	{
-		rt_kprintf(" TX is idle\n");
-	}
+    rt_kprintf("    ENC28J60 on %s\n", ETH_USING_DEVICE_NAME);
+    rt_kprintf(" ------------------------------\n");
+    reg_phy = efm_eth_readPhy(PHSTAT2);
+    if (reg_phy & PHSTAT2_PLRITY)
+    {
+        rt_kprintf(" Cable polarity is reversed\n");
+    }
+    else
+    {
+        rt_kprintf(" Cable polarity is correct\n");
+    }
+    if (reg_phy & PHSTAT2_DPXSTAT)
+    {
+        rt_kprintf(" Full-duplex mode\n");
+    }
+    else
+    {
+        rt_kprintf(" Half-duplex mode\n");
+    }
+    if (reg_phy & PHSTAT2_LSTAT)
+    {
+        rt_kprintf(" Link is up\n");
+    }
+    else
+    {
+        rt_kprintf(" Link is down\n");
+    }
+    if (reg_phy & PHSTAT2_COLSTAT)
+    {
+        rt_kprintf(" Collision is occuring\n");
+    }
+    else
+    {
+        rt_kprintf(" No collision\n");
+    }
+    if (reg_phy & PHSTAT2_RXSTAT)
+    {
+        rt_kprintf(" RX is busy\n");
+    }
+    else
+    {
+        rt_kprintf(" RX is idle\n");
+    }
+    if (reg_phy & PHSTAT2_TXSTAT)
+    {
+        rt_kprintf(" TX is busy\n");
+    }
+    else
+    {
+        rt_kprintf(" TX is idle\n");
+    }
 }
 FINSH_FUNCTION_EXPORT(list_eth, list the Ethernet device status.)
 
@@ -1091,108 +1091,108 @@ FINSH_FUNCTION_EXPORT(list_eth, list the Ethernet device status.)
 
 rt_err_t get_ip(char *ip)
 {
-	err_t ret;
-	struct ip_addr server_ip;
-	struct netconn *conn;
-	struct netbuf *buf;
-	char *rq, *rq2;
-	u16_t len;
-	const char query[] = "GET / HTTP/1.0\r\nHOST: checkip.dyndns.com\r\n\r\n";
-	const char find[] = "body";
+    err_t ret;
+    struct ip_addr server_ip;
+    struct netconn *conn;
+    struct netbuf *buf;
+    char *rq, *rq2;
+    u16_t len;
+    const char query[] = "GET / HTTP/1.0\r\nHOST: checkip.dyndns.com\r\n\r\n";
+    const char find[] = "body";
 
-	do
-	{
+    do
+    {
 #if defined(RT_LWIP_DNS)
-		ret = netconn_gethostbyname("checkip.dyndns.com", &server_ip);
-		if (ret != ERR_OK)
-		{
-			break;
-		}
+        ret = netconn_gethostbyname("checkip.dyndns.com", &server_ip);
+        if (ret != ERR_OK)
+        {
+            break;
+        }
 #else
-		IP4_ADDR(&server_ip, 216,146,38,70);	// IP address of "checkip.dyndns.com"
+        IP4_ADDR(&server_ip, 216,146,38,70);    // IP address of "checkip.dyndns.com"
 #endif
 
-		conn = netconn_new(NETCONN_TCP);
-		if (conn == NULL)
-		{
-			break;
-		}
+        conn = netconn_new(NETCONN_TCP);
+        if (conn == NULL)
+        {
+            break;
+        }
 
-		ret = netconn_connect(conn, &server_ip, 80);
-		if (ret != ERR_OK)
-		{
-			break;
-		}
+        ret = netconn_connect(conn, &server_ip, 80);
+        if (ret != ERR_OK)
+        {
+            break;
+        }
 
-		/* Send the query */
-		ret = netconn_write(conn, query, sizeof(query) - 1, 0);
-		if (ret != ERR_OK)
-		{
-			break;
-		}
+        /* Send the query */
+        ret = netconn_write(conn, query, sizeof(query) - 1, 0);
+        if (ret != ERR_OK)
+        {
+            break;
+        }
 
-		buf = netconn_recv(conn);
-		if (buf != NULL)
-		{
-			/* Get the response */
-			ret = netbuf_data(buf, (void **)&rq, &len);
-			if (ret != ERR_OK)
-			{
-				break;
-			}
+        buf = netconn_recv(conn);
+        if (buf != NULL)
+        {
+            /* Get the response */
+            ret = netbuf_data(buf, (void **)&rq, &len);
+            if (ret != ERR_OK)
+            {
+                break;
+            }
 
-			/* Find the IP address */
-			rq = rt_strstr(rq, find);
-			if (rq == RT_NULL)
-			{
-				break;
-			}
-			rq += 5;
-			rq2 = rq;
-			rq2 = rt_strstr(rq2, find);
-			if (rq2 == RT_NULL)
-			{
-				break;
-			}
-			rq2 -= 2;
-			*rq2 = 0x0;
-//			rt_kprintf("[%s]\n", rq);
-		}
-		else
-		{
-			break;
-		}
+            /* Find the IP address */
+            rq = rt_strstr(rq, find);
+            if (rq == RT_NULL)
+            {
+                break;
+            }
+            rq += 5;
+            rq2 = rq;
+            rq2 = rt_strstr(rq2, find);
+            if (rq2 == RT_NULL)
+            {
+                break;
+            }
+            rq2 -= 2;
+            *rq2 = 0x0;
+//          rt_kprintf("[%s]\n", rq);
+        }
+        else
+        {
+            break;
+        }
 
-		/* Copy the IP address to buffer */
-		if (ip != NULL)
-		{
-			while(*rq < '0' || *rq > '9')
-			{
-				rq++;
-			}
-			rt_memcpy(ip, rq, rq2 - rq + 1);
-		}
-		netconn_delete(conn);
-		netbuf_delete(buf);
-		return RT_EOK;
-	} while (0);
+        /* Copy the IP address to buffer */
+        if (ip != NULL)
+        {
+            while(*rq < '0' || *rq > '9')
+            {
+                rq++;
+            }
+            rt_memcpy(ip, rq, rq2 - rq + 1);
+        }
+        netconn_delete(conn);
+        netbuf_delete(buf);
+        return RT_EOK;
+    } while (0);
 
-	netconn_delete(conn);
-	netbuf_delete(buf);
-	return -RT_ERROR;
+    netconn_delete(conn);
+    netbuf_delete(buf);
+    return -RT_ERROR;
 }
 
 void list_myip(void)
 {
-	rt_uint8_t ip[20];
+    rt_uint8_t ip[20];
 
-	if (get_ip(ip) != RT_EOK)
-	{
-		rt_kprintf("Get IP failed!\n");
-		return;
-	}
+    if (get_ip(ip) != RT_EOK)
+    {
+        rt_kprintf("Get IP failed!\n");
+        return;
+    }
 
-	rt_kprintf("Current IP: [%s]\n", ip);
+    rt_kprintf("Current IP: [%s]\n", ip);
 }
 FINSH_FUNCTION_EXPORT(list_myip, list the current IP address.)
 
@@ -1202,122 +1202,122 @@ FINSH_FUNCTION_EXPORT(list_myip, list the current IP address.)
 
 rt_err_t update_ip(char *ip)
 {
-	err_t ret;
-	struct ip_addr server_ip;
-	struct netconn *conn;
-	struct netbuf *buf;
-	char *rq;
-	u16_t len, len2;
-	char query[200] = "GET /nic/update?hostname=";
-	const char query2[] = "&myip=";
-	const char query3[] = " HTTP/1.0\r\nHost: members.dyndns.org\r\nAuthorization: Basic ";
-	const char query4[] = "\r\nUser-Agent: onelife - EFM32 - 0.4\r\n\r\n";
-	const char find[] = "good";
+    err_t ret;
+    struct ip_addr server_ip;
+    struct netconn *conn;
+    struct netbuf *buf;
+    char *rq;
+    u16_t len, len2;
+    char query[200] = "GET /nic/update?hostname=";
+    const char query2[] = "&myip=";
+    const char query3[] = " HTTP/1.0\r\nHost: members.dyndns.org\r\nAuthorization: Basic ";
+    const char query4[] = "\r\nUser-Agent: onelife - EFM32 - 0.4\r\n\r\n";
+    const char find[] = "good";
 
-	/* Make the query */
-	len = rt_strlen(query);
-	len2 = sizeof(hostName) - 1;
-	rt_memcpy(&query[len], hostName, len2);
-	len += len2;
+    /* Make the query */
+    len = rt_strlen(query);
+    len2 = sizeof(hostName) - 1;
+    rt_memcpy(&query[len], hostName, len2);
+    len += len2;
 
-	len2 = sizeof(query2) - 1;
-	rt_memcpy(&query[len], query2, len2);
-	len += len2;
+    len2 = sizeof(query2) - 1;
+    rt_memcpy(&query[len], query2, len2);
+    len += len2;
 
-	len2 = rt_strlen(ip);
-	rt_memcpy(&query[len], ip, len2);
-	len += len2;
+    len2 = rt_strlen(ip);
+    rt_memcpy(&query[len], ip, len2);
+    len += len2;
 
-	len2 = sizeof(query3) - 1;
-	rt_memcpy(&query[len], query3, len2);
-	len += len2;
+    len2 = sizeof(query3) - 1;
+    rt_memcpy(&query[len], query3, len2);
+    len += len2;
 
-	len2 = sizeof(userPwdB64) - 1;
-	rt_memcpy(&query[len], userPwdB64, len2);
-	len += len2;
+    len2 = sizeof(userPwdB64) - 1;
+    rt_memcpy(&query[len], userPwdB64, len2);
+    len += len2;
 
-	len2 = sizeof(query4) - 1;
-	rt_memcpy(&query[len], query4, len2);
-	len += len2;
+    len2 = sizeof(query4) - 1;
+    rt_memcpy(&query[len], query4, len2);
+    len += len2;
 
-	query[len] = 0x0;
-//	rt_kprintf("Query: %s\n", &query[100]);
+    query[len] = 0x0;
+//  rt_kprintf("Query: %s\n", &query[100]);
 
-	do
-	{
+    do
+    {
 #if defined(RT_LWIP_DNS)
-		ret = netconn_gethostbyname("members.dyndns.org", &server_ip);
-		if (ret != ERR_OK)
-		{
-			break;
-		}
+        ret = netconn_gethostbyname("members.dyndns.org", &server_ip);
+        if (ret != ERR_OK)
+        {
+            break;
+        }
 #else
-		IP4_ADDR(&server_ip, 204,13,248,112);	// IP address of "members.dyndns.org"
+        IP4_ADDR(&server_ip, 204,13,248,112);   // IP address of "members.dyndns.org"
 #endif
 
-		conn = netconn_new(NETCONN_TCP);
-		if (conn == NULL)
-		{
-			break;
-		}
+        conn = netconn_new(NETCONN_TCP);
+        if (conn == NULL)
+        {
+            break;
+        }
 
-		ret = netconn_connect(conn, &server_ip, 80);
-		if (ret != ERR_OK)
-		{
-			break;
-		}
+        ret = netconn_connect(conn, &server_ip, 80);
+        if (ret != ERR_OK)
+        {
+            break;
+        }
 
-		/* Send the query */
-		ret = netconn_write(conn, query, len, 0);
-		if (ret != ERR_OK)
-		{
-			break;
-		}
+        /* Send the query */
+        ret = netconn_write(conn, query, len, 0);
+        if (ret != ERR_OK)
+        {
+            break;
+        }
 
-		/* Get the response */
-		buf = netconn_recv(conn);
-		if (buf != NULL)
-		{
-			ret = netbuf_data(buf, (void **)&rq, &len);
-			if (ret != ERR_OK)
-			{
-				break;
-			}
+        /* Get the response */
+        buf = netconn_recv(conn);
+        if (buf != NULL)
+        {
+            ret = netbuf_data(buf, (void **)&rq, &len);
+            if (ret != ERR_OK)
+            {
+                break;
+            }
 
-			/* Find the result */
-			rq = rt_strstr(rq, find);
-			if (rq == RT_NULL)
-			{
-				break;
-			}
-//			rt_kprintf("[%s]\n", rq);
-		}
-		else
-		{
-			break;
-		}
+            /* Find the result */
+            rq = rt_strstr(rq, find);
+            if (rq == RT_NULL)
+            {
+                break;
+            }
+//          rt_kprintf("[%s]\n", rq);
+        }
+        else
+        {
+            break;
+        }
 
-		netconn_delete(conn);
-		netbuf_delete(buf);
-		return RT_EOK;
-	} while (0);
+        netconn_delete(conn);
+        netbuf_delete(buf);
+        return RT_EOK;
+    } while (0);
 
-	netconn_delete(conn);
-	netbuf_delete(buf);
-	return -RT_ERROR;
+    netconn_delete(conn);
+    netbuf_delete(buf);
+    return -RT_ERROR;
 }
 
 void update_myip(char *ip)
 {
-	rt_kprintf("Update host, \"%s\", to new IP address %s: ", hostName, ip);
+    rt_kprintf("Update host, \"%s\", to new IP address %s: ", hostName, ip);
 
-	if (update_ip(ip) != RT_EOK)
-	{
-		rt_kprintf("failed!\n");
-		return;
-	}
+    if (update_ip(ip) != RT_EOK)
+    {
+        rt_kprintf("failed!\n");
+        return;
+    }
 
-	rt_kprintf("succeeded.\n", ip);
+    rt_kprintf("succeeded.\n", ip);
 }
 FINSH_FUNCTION_EXPORT(update_myip, update DDNS with specified IP address.)
 
diff --git a/bsp/efm32/drv_ethernet.h b/bsp/efm32/drv_ethernet.h
index 146182f86d..87e12493f6 100644
--- a/bsp/efm32/drv_ethernet.h
+++ b/bsp/efm32/drv_ethernet.h
@@ -1,11 +1,11 @@
 /***************************************************************************//**
- * @file 	drv_ethernet.h
- * @brief 	Ethernet driver (SPI mode) of RT-Thread RTOS for using EFM32 USART
+ * @file    drv_ethernet.h
+ * @brief   Ethernet driver (SPI mode) of RT-Thread RTOS for using EFM32 USART
  *  module
- * 	 This driver is tested by using the Microchip ENC28J60 stand-alone Ethernet
+ *   This driver is tested by using the Microchip ENC28J60 stand-alone Ethernet
  *  controller with SPI interface.
  *  COPYRIGHT (C) 2012, RT-Thread Development Team
- * @author 	onelife
+ * @author  onelife
  * @version 1.0
  *******************************************************************************
  * @section License
@@ -13,8 +13,8 @@
  *  LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
  *******************************************************************************
  * @section Change Logs
- * Date			Author		Notes
- * 2011-06-22	onelife		Initial creation for using EFM32 USART module
+ * Date         Author      Notes
+ * 2011-06-22   onelife     Initial creation for using EFM32 USART module
  ******************************************************************************/
 #ifndef __DEV_ETHERNET_H__
 #define __DEV_ETHERNET_H__
@@ -25,18 +25,18 @@
 /* Exported types ------------------------------------------------------------*/
 /* Exported constants --------------------------------------------------------*/
 /* Exported macro ------------------------------------------------------------*/
-#define ETH_ADDR_LEN 			(6)
-#define ETH_CLK_MAX 			(10000000) 	/* Should be more than 8 Mz (Errata 1) */
+#define ETH_ADDR_LEN            (6)
+#define ETH_CLK_MAX             (10000000)  /* Should be more than 8 Mz (Errata 1) */
 //#define ETH_HALF_DUPLEX
 
-#define ETH_PERIOD_WAIT_INIT 	(RT_TICK_PER_SECOND/100)
-#define ETH_PERIOD_WAIT_TX 		(RT_TICK_PER_SECOND/100)
-#define ETH_SPI_RX_SKIP 		(1)
+#define ETH_PERIOD_WAIT_INIT    (RT_TICK_PER_SECOND/100)
+#define ETH_PERIOD_WAIT_TX      (RT_TICK_PER_SECOND/100)
+#define ETH_SPI_RX_SKIP         (1)
 
-#define ETH_RESET_PORT 			(gpioPortB)
-#define ETH_RESET_PIN 			(9)
-#define ETH_INT_PORT 			(gpioPortB)
-#define ETH_INT_PIN 			(10)
+#define ETH_RESET_PORT          (gpioPortB)
+#define ETH_RESET_PIN           (9)
+#define ETH_INT_PORT            (gpioPortB)
+#define ETH_INT_PIN             (10)
 
 /* Exported functions ------------------------------------------------------- */
 rt_err_t efm_hw_eth_init(void);
diff --git a/bsp/efm32/drv_leuart.c b/bsp/efm32/drv_leuart.c
index 23addb48a9..7422956003 100644
--- a/bsp/efm32/drv_leuart.c
+++ b/bsp/efm32/drv_leuart.c
@@ -1,8 +1,8 @@
 /***************************************************************************//**
- * @file 	drv_leuart.c
- * @brief 	LEUART driver of RT-Thread RTOS for EFM32
+ * @file    drv_leuart.c
+ * @brief   LEUART driver of RT-Thread RTOS for EFM32
  *  COPYRIGHT (C) 2012, RT-Thread Development Team
- * @author 	onelife
+ * @author  onelife
  * @version 1.0
  *******************************************************************************
  * @section License
@@ -10,9 +10,9 @@
  *  LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
  *******************************************************************************
  * @section Change Logs
- * Date			Author		Notes
- * 2011-12-09	onelife		Initial creation for EFM32
- * 2011-12-27	onelife		Utilize "LEUART_PRESENT" and "LEUART_COUNT"
+ * Date         Author      Notes
+ * 2011-12-09   onelife     Initial creation for EFM32
+ * 2011-12-27   onelife     Utilize "LEUART_PRESENT" and "LEUART_COUNT"
  ******************************************************************************/
 
 /***************************************************************************//**
@@ -41,10 +41,10 @@
 /* Private variables ---------------------------------------------------------*/
 #if defined(RT_USING_LEUART0)
  #if (RT_USING_LEUART0 >= EFM32_LEUART_LOCATION_COUNT)
- 	#error "Wrong location number"
+    #error "Wrong location number"
  #endif
-	struct rt_device leuart0_device;
-	static struct rt_semaphore leuart0_lock;
+    struct rt_device leuart0_device;
+    static struct rt_semaphore leuart0_lock;
 #endif
 
 #if defined(RT_USING_LEUART1)
@@ -52,10 +52,10 @@
  #error "Wrong unit number"
  #endif
  #if (RT_USING_LEUART1 >= EFM32_LEUART_LOCATION_COUNT)
- 	#error "Wrong location number"
+    #error "Wrong location number"
  #endif
-	struct rt_device leuart1_device;
-	static struct rt_semaphore leuart1_lock;
+    struct rt_device leuart1_device;
+    static struct rt_semaphore leuart1_lock;
 #endif
 
 /* Private function prototypes -----------------------------------------------*/
@@ -76,37 +76,37 @@
  ******************************************************************************/
 static rt_err_t rt_leuart_init (rt_device_t dev)
 {
-	struct efm32_leuart_device_t *leuart;
+    struct efm32_leuart_device_t *leuart;
 
-	leuart = (struct efm32_leuart_device_t *)(dev->user_data);
+    leuart = (struct efm32_leuart_device_t *)(dev->user_data);
 
-	if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
-	{
-		if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
-		{
-			struct efm32_leuart_dma_mode_t *dma_tx;
+    if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
+    {
+        if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
+        {
+            struct efm32_leuart_dma_mode_t *dma_tx;
 
-			dma_tx = (struct efm32_leuart_dma_mode_t *)(leuart->tx_mode);
+            dma_tx = (struct efm32_leuart_dma_mode_t *)(leuart->tx_mode);
 
-			leuart->state |= LEUART_STATE_RX_BUSY;
-		}
+            leuart->state |= LEUART_STATE_RX_BUSY;
+        }
 
-		if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-		{
-			struct efm32_leuart_int_mode_t *int_rx;
+        if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+        {
+            struct efm32_leuart_int_mode_t *int_rx;
 
-			int_rx = (struct efm32_leuart_int_mode_t *)(leuart->rx_mode);
+            int_rx = (struct efm32_leuart_int_mode_t *)(leuart->rx_mode);
 
-			int_rx->data_ptr = RT_NULL;
-		}
+            int_rx->data_ptr = RT_NULL;
+        }
 
-		/* Enable LEUART */
-		LEUART_Enable(leuart->leuart_device, leuartEnable);
+        /* Enable LEUART */
+        LEUART_Enable(leuart->leuart_device, leuartEnable);
 
-		dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
-	}
+        dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 /***************************************************************************//**
@@ -128,68 +128,68 @@ static rt_err_t rt_leuart_init (rt_device_t dev)
  ******************************************************************************/
 static rt_err_t rt_leuart_open(rt_device_t dev, rt_uint16_t oflag)
 {
-	RT_ASSERT(dev != RT_NULL);
+    RT_ASSERT(dev != RT_NULL);
 
-	struct efm32_leuart_device_t	*leuart;
+    struct efm32_leuart_device_t    *leuart;
 
-	leuart = (struct efm32_leuart_device_t *)(dev->user_data);
+    leuart = (struct efm32_leuart_device_t *)(dev->user_data);
 
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		IRQn_Type 					rxIrq;
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        IRQn_Type                   rxIrq;
 
-		//if (leuart->state & LEUART_STATE_CONSOLE)
-		{	/* Allocate new RX buffer */
-			struct efm32_leuart_int_mode_t	*int_mode;
+        //if (leuart->state & LEUART_STATE_CONSOLE)
+        {   /* Allocate new RX buffer */
+            struct efm32_leuart_int_mode_t  *int_mode;
 
-			int_mode = (struct efm32_leuart_int_mode_t *)(leuart->rx_mode);
+            int_mode = (struct efm32_leuart_int_mode_t *)(leuart->rx_mode);
 
-			if ((int_mode->data_ptr = rt_malloc(LEUART_RX_BUFFER_SIZE)) == RT_NULL)
-			{
-				leuart_debug("LEUART%d err: no mem for RX BUF\n", leuart->unit);
-				return -RT_ENOMEM;
-			}
-			rt_memset(int_mode->data_ptr, 0, LEUART_RX_BUFFER_SIZE);
-			int_mode->data_size = LEUART_RX_BUFFER_SIZE;
-			int_mode->read_index = 0;
-			int_mode->save_index = 0;
-		}
+            if ((int_mode->data_ptr = rt_malloc(LEUART_RX_BUFFER_SIZE)) == RT_NULL)
+            {
+                leuart_debug("LEUART%d err: no mem for RX BUF\n", leuart->unit);
+                return -RT_ENOMEM;
+            }
+            rt_memset(int_mode->data_ptr, 0, LEUART_RX_BUFFER_SIZE);
+            int_mode->data_size = LEUART_RX_BUFFER_SIZE;
+            int_mode->read_index = 0;
+            int_mode->save_index = 0;
+        }
 
-		/* Enable RX interrupt */
-        leuart->leuart_device->IEN 	= LEUART_IEN_RXDATAV;
+        /* Enable RX interrupt */
+        leuart->leuart_device->IEN  = LEUART_IEN_RXDATAV;
 
-		/* Enable IRQ */
-		switch (leuart->unit)
-		{
-		case 0:
+        /* Enable IRQ */
+        switch (leuart->unit)
+        {
+        case 0:
             rxIrq   = LEUART0_IRQn;
-			break;
+            break;
 #if (LEUART_COUNT > 1)
-		case 1:
+        case 1:
             rxIrq   = LEUART1_IRQn;
-			break;
+            break;
 #endif
         }
-		if (oflag != RT_DEVICE_OFLAG_WRONLY)
-		{
-			NVIC_ClearPendingIRQ(rxIrq);
-			NVIC_SetPriority(rxIrq, EFM32_IRQ_PRI_DEFAULT);
-			NVIC_EnableIRQ(rxIrq);
-		}
-	}
+        if (oflag != RT_DEVICE_OFLAG_WRONLY)
+        {
+            NVIC_ClearPendingIRQ(rxIrq);
+            NVIC_SetPriority(rxIrq, EFM32_IRQ_PRI_DEFAULT);
+            NVIC_EnableIRQ(rxIrq);
+        }
+    }
 
     /* Clear Flag */
     leuart->leuart_device->IFC      = _LEUART_IFC_MASK;
 
-	if ((dev->flag & RT_DEVICE_FLAG_DMA_TX) && (oflag != RT_DEVICE_OFLAG_RDONLY))
-	{
-		/* DMA IRQ is enabled by DMA_Init() */
-		NVIC_SetPriority(DMA_IRQn, EFM32_IRQ_PRI_DEFAULT);
-	}
+    if ((dev->flag & RT_DEVICE_FLAG_DMA_TX) && (oflag != RT_DEVICE_OFLAG_RDONLY))
+    {
+        /* DMA IRQ is enabled by DMA_Init() */
+        NVIC_SetPriority(DMA_IRQn, EFM32_IRQ_PRI_DEFAULT);
+    }
 
-	leuart->counter++;
-	leuart_debug("LEUART%d: Open with flag %x\n", leuart->unit, oflag);
-	return RT_EOK;
+    leuart->counter++;
+    leuart_debug("LEUART%d: Open with flag %x\n", leuart->unit, oflag);
+    return RT_EOK;
 }
 
 /***************************************************************************//**
@@ -208,26 +208,26 @@ static rt_err_t rt_leuart_open(rt_device_t dev, rt_uint16_t oflag)
  ******************************************************************************/
 static rt_err_t rt_leuart_close(rt_device_t dev)
 {
-	RT_ASSERT(dev != RT_NULL);
+    RT_ASSERT(dev != RT_NULL);
 
-	struct efm32_leuart_device_t    *leuart;
+    struct efm32_leuart_device_t    *leuart;
 
-	leuart = (struct efm32_leuart_device_t *)(dev->user_data);
+    leuart = (struct efm32_leuart_device_t *)(dev->user_data);
 
-	if (--leuart->counter == 0)
-	{
-		if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-		{
-			struct efm32_leuart_int_mode_t *int_rx;
+    if (--leuart->counter == 0)
+    {
+        if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+        {
+            struct efm32_leuart_int_mode_t *int_rx;
 
-			int_rx = (struct efm32_leuart_int_mode_t *)leuart->rx_mode;
+            int_rx = (struct efm32_leuart_int_mode_t *)leuart->rx_mode;
 
-			rt_free(int_rx->data_ptr);
-			int_rx->data_ptr = RT_NULL;
-		}
-	}
+            rt_free(int_rx->data_ptr);
+            int_rx->data_ptr = RT_NULL;
+        }
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 /***************************************************************************//**
@@ -254,105 +254,105 @@ static rt_err_t rt_leuart_close(rt_device_t dev)
  *   Number of read bytes
  ******************************************************************************/
 static rt_size_t rt_leuart_read (
-	rt_device_t 	dev,
-	rt_off_t 		pos,
-	void 			*buffer,
-	rt_size_t 		size)
+    rt_device_t     dev,
+    rt_off_t        pos,
+    void            *buffer,
+    rt_size_t       size)
 {
-	struct efm32_leuart_device_t *leuart;
-	rt_uint8_t 	*ptr;
-	rt_err_t 	err_code;
-	rt_size_t 	read_len;
+    struct efm32_leuart_device_t *leuart;
+    rt_uint8_t  *ptr;
+    rt_err_t    err_code;
+    rt_size_t   read_len;
 
-	leuart = (struct efm32_leuart_device_t *)(dev->user_data);
+    leuart = (struct efm32_leuart_device_t *)(dev->user_data);
 
-	/* Lock device */
-	if (rt_hw_interrupt_check())
-	{
-		err_code = rt_sem_take(leuart->lock, RT_WAITING_NO);
-	}
-	else
-	{
-		err_code = rt_sem_take(leuart->lock, RT_WAITING_FOREVER);
-	}
-	if (err_code != RT_EOK)
-	{
-		rt_set_errno(err_code);
-		return 0;
-	}
+    /* Lock device */
+    if (rt_hw_interrupt_check())
+    {
+        err_code = rt_sem_take(leuart->lock, RT_WAITING_NO);
+    }
+    else
+    {
+        err_code = rt_sem_take(leuart->lock, RT_WAITING_FOREVER);
+    }
+    if (err_code != RT_EOK)
+    {
+        rt_set_errno(err_code);
+        return 0;
+    }
 
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		ptr = buffer;
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        ptr = buffer;
 
-		/* interrupt mode Rx */
-		while (size)
-		{
-			rt_base_t level;
-			struct efm32_leuart_int_mode_t *int_rx;
+        /* interrupt mode Rx */
+        while (size)
+        {
+            rt_base_t level;
+            struct efm32_leuart_int_mode_t *int_rx;
 
-			int_rx = (struct efm32_leuart_int_mode_t *)\
-				(((struct efm32_leuart_device_t *)(dev->user_data))->rx_mode);
+            int_rx = (struct efm32_leuart_int_mode_t *)\
+                (((struct efm32_leuart_device_t *)(dev->user_data))->rx_mode);
 
-			/* disable interrupt */
-			level = rt_hw_interrupt_disable();
+            /* disable interrupt */
+            level = rt_hw_interrupt_disable();
 
-			if (int_rx->read_index != int_rx->save_index)
-			{
-				/* read a character */
-				*ptr++ = int_rx->data_ptr[int_rx->read_index];
-				size--;
+            if (int_rx->read_index != int_rx->save_index)
+            {
+                /* read a character */
+                *ptr++ = int_rx->data_ptr[int_rx->read_index];
+                size--;
 
-				/* move to next position */
-				int_rx->read_index ++;
-				if (int_rx->read_index >= LEUART_RX_BUFFER_SIZE)
-				{
-					int_rx->read_index = 0;
-				}
-			}
-			else
-			{
-				/* set error code */
-				err_code = -RT_EEMPTY;
+                /* move to next position */
+                int_rx->read_index ++;
+                if (int_rx->read_index >= LEUART_RX_BUFFER_SIZE)
+                {
+                    int_rx->read_index = 0;
+                }
+            }
+            else
+            {
+                /* set error code */
+                err_code = -RT_EEMPTY;
 
-				/* enable interrupt */
-				rt_hw_interrupt_enable(level);
-				break;
-			}
+                /* enable interrupt */
+                rt_hw_interrupt_enable(level);
+                break;
+            }
 
-			/* enable interrupt */
-			rt_hw_interrupt_enable(level);
-		}
+            /* enable interrupt */
+            rt_hw_interrupt_enable(level);
+        }
 
-		read_len = (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-	}
-	else
-	{
-		LEUART_TypeDef *leuart_device;
+        read_len = (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+    }
+    else
+    {
+        LEUART_TypeDef *leuart_device;
 
-		leuart = (struct efm32_leuart_device_t *)(dev->user_data);
-		leuart_device = ((struct efm32_leuart_device_t *)(dev->user_data))->leuart_device;
-		ptr = buffer;
+        leuart = (struct efm32_leuart_device_t *)(dev->user_data);
+        leuart_device = ((struct efm32_leuart_device_t *)(dev->user_data))->leuart_device;
+        ptr = buffer;
 
-		/* polling mode */
-		while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
-		{
-			while (leuart_device->STATUS & LEUART_STATUS_RXDATAV)
-			{
-				*ptr = leuart_device->RXDATA & 0xff;
-				ptr ++;
-			}
-		}
+        /* polling mode */
+        while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
+        {
+            while (leuart_device->STATUS & LEUART_STATUS_RXDATAV)
+            {
+                *ptr = leuart_device->RXDATA & 0xff;
+                ptr ++;
+            }
+        }
 
-		read_len = size;
-	}
+        read_len = size;
+    }
 
-	/* Unlock device */
-	rt_sem_release(leuart->lock);
+    /* Unlock device */
+    rt_sem_release(leuart->lock);
 
-	/* set error code */
-	rt_set_errno(err_code);
-	return read_len;
+    /* set error code */
+    rt_set_errno(err_code);
+    return read_len;
 }
 
 /***************************************************************************//**
@@ -379,504 +379,504 @@ static rt_size_t rt_leuart_read (
  *   Number of written bytes
  ******************************************************************************/
 static rt_size_t rt_leuart_write (
-	rt_device_t 	dev,
-	rt_off_t 		pos,
-	const void* 	buffer,
-	rt_size_t 		size)
+    rt_device_t     dev,
+    rt_off_t        pos,
+    const void*     buffer,
+    rt_size_t       size)
 {
-	rt_err_t 						err_code;
-	rt_size_t 						write_size;
-	struct efm32_leuart_device_t* 	leuart;
+    rt_err_t                        err_code;
+    rt_size_t                       write_size;
+    struct efm32_leuart_device_t*   leuart;
 
-	write_size = 0;
-	leuart = (struct efm32_leuart_device_t*)(dev->user_data);
+    write_size = 0;
+    leuart = (struct efm32_leuart_device_t*)(dev->user_data);
 
-	/* Lock device */
-	if (rt_hw_interrupt_check())
-	{
-		err_code = rt_sem_take(leuart->lock, RT_WAITING_NO);
-	}
-	else
-	{
-		err_code = rt_sem_take(leuart->lock, RT_WAITING_FOREVER);
-	}
-	if (err_code != RT_EOK)
-	{
-		rt_set_errno(err_code);
-		return 0;
-	}
+    /* Lock device */
+    if (rt_hw_interrupt_check())
+    {
+        err_code = rt_sem_take(leuart->lock, RT_WAITING_NO);
+    }
+    else
+    {
+        err_code = rt_sem_take(leuart->lock, RT_WAITING_FOREVER);
+    }
+    if (err_code != RT_EOK)
+    {
+        rt_set_errno(err_code);
+        return 0;
+    }
 
-	if ((dev->flag & RT_DEVICE_FLAG_DMA_TX) && (size > 2))
-	{	/* DMA mode Tx */
-		struct efm32_leuart_dma_mode_t *dma_tx;
+    if ((dev->flag & RT_DEVICE_FLAG_DMA_TX) && (size > 2))
+    {   /* DMA mode Tx */
+        struct efm32_leuart_dma_mode_t *dma_tx;
 
-		if (dev->flag & RT_DEVICE_FLAG_STREAM)
-		{
-			if (*((rt_uint8_t *)buffer + size - 1) == '\n')
-			{
-				*((rt_uint8_t *)buffer + size - 1) = '\r';
-				*((rt_uint8_t *)buffer + size++) = '\n';
-				*((rt_uint8_t *)buffer + size) = 0;
-			}
-		}
+        if (dev->flag & RT_DEVICE_FLAG_STREAM)
+        {
+            if (*((rt_uint8_t *)buffer + size - 1) == '\n')
+            {
+                *((rt_uint8_t *)buffer + size - 1) = '\r';
+                *((rt_uint8_t *)buffer + size++) = '\n';
+                *((rt_uint8_t *)buffer + size) = 0;
+            }
+        }
 
-		dma_tx = (struct efm32_leuart_dma_mode_t *)(leuart->tx_mode);
-		dma_tx->data_ptr = (rt_uint32_t *)buffer;
-		dma_tx->data_size = size;
+        dma_tx = (struct efm32_leuart_dma_mode_t *)(leuart->tx_mode);
+        dma_tx->data_ptr = (rt_uint32_t *)buffer;
+        dma_tx->data_size = size;
 
-		leuart->state |= LEUART_STATE_TX_BUSY;
+        leuart->state |= LEUART_STATE_TX_BUSY;
 
-		DMA_ActivateBasic(
-			dma_tx->dma_channel,
-			true,
-			false,
-			(void *)&(leuart->leuart_device->TXDATA),
-			(void *)buffer,
-			(rt_uint32_t)(size - 1));
+        DMA_ActivateBasic(
+            dma_tx->dma_channel,
+            true,
+            false,
+            (void *)&(leuart->leuart_device->TXDATA),
+            (void *)buffer,
+            (rt_uint32_t)(size - 1));
 
-		/* Wait, otherwise the TX buffer is overwrite */
-//		if (leuart->state & LEUART_STATE_CONSOLE)
-//		{
-			while(leuart->state & LEUART_STATE_TX_BUSY);
-//		}
-//		else
-//		{
-//			while(leuart->state & LEUART_STATE_TX_BUSY)
-//			{
-//				rt_thread_sleep(LEUART_WAIT_TIME_TX);
-//			}
-//		}
+        /* Wait, otherwise the TX buffer is overwrite */
+//      if (leuart->state & LEUART_STATE_CONSOLE)
+//      {
+            while(leuart->state & LEUART_STATE_TX_BUSY);
+//      }
+//      else
+//      {
+//          while(leuart->state & LEUART_STATE_TX_BUSY)
+//          {
+//              rt_thread_sleep(LEUART_WAIT_TIME_TX);
+//          }
+//      }
 // TODO: This function blocks the process
-		write_size = size;
-	}
-	else
-	{	/* polling mode */
-		rt_uint8_t *ptr = (rt_uint8_t *)buffer;
+        write_size = size;
+    }
+    else
+    {   /* polling mode */
+        rt_uint8_t *ptr = (rt_uint8_t *)buffer;
 
-		if (dev->flag & RT_DEVICE_FLAG_STREAM)
-		{
-			/* stream mode */
-			while (size)
-			{
-				if (*ptr == '\n')
-				{
-					while (!(leuart->leuart_device->STATUS & LEUART_STATUS_TXBL));
-					leuart->leuart_device->TXDATA = '\r';
-				}
+        if (dev->flag & RT_DEVICE_FLAG_STREAM)
+        {
+            /* stream mode */
+            while (size)
+            {
+                if (*ptr == '\n')
+                {
+                    while (!(leuart->leuart_device->STATUS & LEUART_STATUS_TXBL));
+                    leuart->leuart_device->TXDATA = '\r';
+                }
 
-				while (!(leuart->leuart_device->STATUS & LEUART_STATUS_TXBL));
-				leuart->leuart_device->TXDATA = (rt_uint32_t)*ptr;
-				++ptr; --size;
-			}
-		}
-		else
-		{
-			/* write data directly */
-			while (size)
-			{
-				while (!(leuart->leuart_device->STATUS & LEUART_STATUS_TXBL));
-				leuart->leuart_device->TXDATA = (rt_uint32_t)*ptr;
-				++ptr; --size;
-			}
-		}
+                while (!(leuart->leuart_device->STATUS & LEUART_STATUS_TXBL));
+                leuart->leuart_device->TXDATA = (rt_uint32_t)*ptr;
+                ++ptr; --size;
+            }
+        }
+        else
+        {
+            /* write data directly */
+            while (size)
+            {
+                while (!(leuart->leuart_device->STATUS & LEUART_STATUS_TXBL));
+                leuart->leuart_device->TXDATA = (rt_uint32_t)*ptr;
+                ++ptr; --size;
+            }
+        }
 
-		write_size = (rt_size_t)ptr - (rt_size_t)buffer;
-	}
+        write_size = (rt_size_t)ptr - (rt_size_t)buffer;
+    }
 
-	/* Unlock device */
-	rt_sem_release(leuart->lock);
+    /* Unlock device */
+    rt_sem_release(leuart->lock);
 
-	/* set error code */
-	rt_set_errno(err_code);
-	return write_size;
+    /* set error code */
+    rt_set_errno(err_code);
+    return write_size;
 }
 
 /***************************************************************************//**
 * @brief
-*	Configure LEUART device
+*   Configure LEUART device
 *
 * @details
 *
 * @note
 *
 * @param[in] dev
-*	Pointer to device descriptor
+*   Pointer to device descriptor
 *
 * @param[in] cmd
-*	IIC control command
+*   IIC control command
 *
 * @param[in] args
-*	Arguments
+*   Arguments
 *
 * @return
-*	Error code
+*   Error code
 ******************************************************************************/
 static rt_err_t rt_leuart_control (
-	rt_device_t 	dev,
-	rt_uint8_t 		cmd,
-	void 			*args)
+    rt_device_t     dev,
+    rt_uint8_t      cmd,
+    void            *args)
 {
-	RT_ASSERT(dev != RT_NULL);
+    RT_ASSERT(dev != RT_NULL);
 
-	rt_err_t	err_code;
-	struct efm32_leuart_device_t *leuart;
+    rt_err_t    err_code;
+    struct efm32_leuart_device_t *leuart;
 
-	leuart = (struct efm32_leuart_device_t *)(dev->user_data);
+    leuart = (struct efm32_leuart_device_t *)(dev->user_data);
 
-	/* Lock device */
-	if (rt_hw_interrupt_check())
-	{
-		err_code = rt_sem_take(leuart->lock, RT_WAITING_NO);
-	}
-	else
-	{
-		err_code = rt_sem_take(leuart->lock, RT_WAITING_FOREVER);
-	}
-	if (err_code != RT_EOK)
-	{
-		return err_code;
-	}
+    /* Lock device */
+    if (rt_hw_interrupt_check())
+    {
+        err_code = rt_sem_take(leuart->lock, RT_WAITING_NO);
+    }
+    else
+    {
+        err_code = rt_sem_take(leuart->lock, RT_WAITING_FOREVER);
+    }
+    if (err_code != RT_EOK)
+    {
+        return err_code;
+    }
 
-	switch (cmd)
-	{
-	case RT_DEVICE_CTRL_SUSPEND:
-		/* Suspend device */
-		dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
-		LEUART_Enable(leuart->leuart_device, leuartDisable);
-		break;
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_SUSPEND:
+        /* Suspend device */
+        dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
+        LEUART_Enable(leuart->leuart_device, leuartDisable);
+        break;
 
-	case RT_DEVICE_CTRL_RESUME:
-		/* Resume device */
-		dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
-		LEUART_Enable(leuart->leuart_device, leuartEnable);
-		break;
+    case RT_DEVICE_CTRL_RESUME:
+        /* Resume device */
+        dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
+        LEUART_Enable(leuart->leuart_device, leuartEnable);
+        break;
 
-	case RT_DEVICE_CTRL_LEUART_RBUFFER:
-		/* Set RX buffer */
-		{
-			struct efm32_leuart_int_mode_t *int_rx;
-			rt_uint8_t size;
+    case RT_DEVICE_CTRL_LEUART_RBUFFER:
+        /* Set RX buffer */
+        {
+            struct efm32_leuart_int_mode_t *int_rx;
+            rt_uint8_t size;
 
-			int_rx = (struct efm32_leuart_int_mode_t *)(leuart->rx_mode);
-			size = (rt_uint8_t)((rt_uint32_t)args & 0xFFUL);
+            int_rx = (struct efm32_leuart_int_mode_t *)(leuart->rx_mode);
+            size = (rt_uint8_t)((rt_uint32_t)args & 0xFFUL);
 
-			/* Free previous RX buffer */
-			if (int_rx->data_ptr != RT_NULL)
-			{
-				if (size == 0)
-				{	/* Free RX buffer */
-					rt_free(int_rx->data_ptr);
-					int_rx->data_ptr = RT_NULL;
-				}
-				else if (size != int_rx->data_size)
-				{
-					/* Re-allocate RX buffer */
-					if ((int_rx->data_ptr = rt_realloc(int_rx->data_ptr, size)) \
-						== RT_NULL)
-					{
-						leuart_debug("LEUART%d err: no mem for RX BUF\n", leuart->unit);
-						err_code = -RT_ENOMEM;
-						break;
-					}
-					// TODO: Is the following line necessary?
-					//rt_memset(int_rx->data_ptr, 0, size);
-				}
-			}
-			else
-			{
-				/* Allocate new RX buffer */
-				if ((int_rx->data_ptr = rt_malloc(size)) == RT_NULL)
-				{
-					leuart_debug("LEUART%d err: no mem for RX BUF\n", leuart->unit);
-					err_code = -RT_ENOMEM;
-					break;
-				}
-			}
-			int_rx->data_size = size;
-			int_rx->read_index = 0;
-			int_rx->save_index = 0;
-		}
-		break;
+            /* Free previous RX buffer */
+            if (int_rx->data_ptr != RT_NULL)
+            {
+                if (size == 0)
+                {   /* Free RX buffer */
+                    rt_free(int_rx->data_ptr);
+                    int_rx->data_ptr = RT_NULL;
+                }
+                else if (size != int_rx->data_size)
+                {
+                    /* Re-allocate RX buffer */
+                    if ((int_rx->data_ptr = rt_realloc(int_rx->data_ptr, size)) \
+                        == RT_NULL)
+                    {
+                        leuart_debug("LEUART%d err: no mem for RX BUF\n", leuart->unit);
+                        err_code = -RT_ENOMEM;
+                        break;
+                    }
+                    // TODO: Is the following line necessary?
+                    //rt_memset(int_rx->data_ptr, 0, size);
+                }
+            }
+            else
+            {
+                /* Allocate new RX buffer */
+                if ((int_rx->data_ptr = rt_malloc(size)) == RT_NULL)
+                {
+                    leuart_debug("LEUART%d err: no mem for RX BUF\n", leuart->unit);
+                    err_code = -RT_ENOMEM;
+                    break;
+                }
+            }
+            int_rx->data_size = size;
+            int_rx->read_index = 0;
+            int_rx->save_index = 0;
+        }
+        break;
 
-	}
+    }
 
-	/* Unlock device */
-	rt_sem_release(leuart->lock);
+    /* Unlock device */
+    rt_sem_release(leuart->lock);
 
-	return err_code;
+    return err_code;
 }
 
 /***************************************************************************//**
  * @brief
- *	LEUART RX data valid interrupt handler
+ *  LEUART RX data valid interrupt handler
  *
  * @details
  *
  * @note
  *
  * @param[in] dev
- *	Pointer to device descriptor
+ *  Pointer to device descriptor
  ******************************************************************************/
 void rt_hw_leuart_rx_isr(rt_device_t dev)
 {
-	struct efm32_leuart_device_t 	*leuart;
-	struct efm32_leuart_int_mode_t 	*int_rx;
+    struct efm32_leuart_device_t    *leuart;
+    struct efm32_leuart_int_mode_t  *int_rx;
     rt_uint32_t                     flag;
 
-	/* interrupt mode receive */
-	RT_ASSERT(dev->flag & RT_DEVICE_FLAG_INT_RX);
+    /* interrupt mode receive */
+    RT_ASSERT(dev->flag & RT_DEVICE_FLAG_INT_RX);
 
-	leuart = (struct efm32_leuart_device_t *)(dev->user_data);
-	int_rx = (struct efm32_leuart_int_mode_t *)(leuart->rx_mode);
+    leuart = (struct efm32_leuart_device_t *)(dev->user_data);
+    int_rx = (struct efm32_leuart_int_mode_t *)(leuart->rx_mode);
 
-	RT_ASSERT(int_rx->data_ptr != RT_NULL);
+    RT_ASSERT(int_rx->data_ptr != RT_NULL);
 
-	/* Set status */
-	leuart->state |= LEUART_STATE_RX_BUSY;
+    /* Set status */
+    leuart->state |= LEUART_STATE_RX_BUSY;
 
-	/* save into rx buffer */
-	while (leuart->leuart_device->STATUS & LEUART_STATUS_RXDATAV)
-	{
-		rt_base_t level;
+    /* save into rx buffer */
+    while (leuart->leuart_device->STATUS & LEUART_STATUS_RXDATAV)
+    {
+        rt_base_t level;
 
-		/* disable interrupt */
-		level = rt_hw_interrupt_disable();
+        /* disable interrupt */
+        level = rt_hw_interrupt_disable();
 
-		/* save character */
-		int_rx->data_ptr[int_rx->save_index] = \
-			(rt_uint8_t)(leuart->leuart_device->RXDATA & 0xFFUL);
-		int_rx->save_index ++;
-		if (int_rx->save_index >= LEUART_RX_BUFFER_SIZE)
-			int_rx->save_index = 0;
+        /* save character */
+        int_rx->data_ptr[int_rx->save_index] = \
+            (rt_uint8_t)(leuart->leuart_device->RXDATA & 0xFFUL);
+        int_rx->save_index ++;
+        if (int_rx->save_index >= LEUART_RX_BUFFER_SIZE)
+            int_rx->save_index = 0;
 
-		/* if the next position is read index, discard this 'read char' */
-		if (int_rx->save_index == int_rx->read_index)
-		{
-			int_rx->read_index ++;
-			if (int_rx->read_index >= LEUART_RX_BUFFER_SIZE)
-			{
-				int_rx->read_index = 0;
-			}
-		}
+        /* if the next position is read index, discard this 'read char' */
+        if (int_rx->save_index == int_rx->read_index)
+        {
+            int_rx->read_index ++;
+            if (int_rx->read_index >= LEUART_RX_BUFFER_SIZE)
+            {
+                int_rx->read_index = 0;
+            }
+        }
 
-		/* enable interrupt */
-		rt_hw_interrupt_enable(level);
-	}
+        /* enable interrupt */
+        rt_hw_interrupt_enable(level);
+    }
 
-	/* invoke callback */
-	if (dev->rx_indicate != RT_NULL)
-	{
-		rt_size_t rx_length;
+    /* invoke callback */
+    if (dev->rx_indicate != RT_NULL)
+    {
+        rt_size_t rx_length;
 
-		/* get rx length */
-		rx_length = int_rx->read_index > int_rx->save_index ?
-			LEUART_RX_BUFFER_SIZE - int_rx->read_index + int_rx->save_index : \
-			int_rx->save_index - int_rx->read_index;
+        /* get rx length */
+        rx_length = int_rx->read_index > int_rx->save_index ?
+            LEUART_RX_BUFFER_SIZE - int_rx->read_index + int_rx->save_index : \
+            int_rx->save_index - int_rx->read_index;
 
-		dev->rx_indicate(dev, rx_length);
-	}
+        dev->rx_indicate(dev, rx_length);
+    }
 }
 
 /***************************************************************************//**
  * @brief
- *	DMA for LEUART TX interrupt handler
+ *  DMA for LEUART TX interrupt handler
  *
  * @details
  *
  * @note
  *
  * @param[in] dev
- *	Pointer to device descriptor
+ *  Pointer to device descriptor
  ******************************************************************************/
 void rt_hw_leuart_dma_tx_isr(rt_device_t dev)
 {
-	/* DMA mode receive */
-	struct efm32_leuart_device_t 	*leuart;
-	struct efm32_leuart_dma_mode_t 	*dma_tx;
+    /* DMA mode receive */
+    struct efm32_leuart_device_t    *leuart;
+    struct efm32_leuart_dma_mode_t  *dma_tx;
 
-	RT_ASSERT(dev->flag & RT_DEVICE_FLAG_DMA_TX);
+    RT_ASSERT(dev->flag & RT_DEVICE_FLAG_DMA_TX);
 
-	leuart = (struct efm32_leuart_device_t *)(dev->user_data);
-	dma_tx = (struct efm32_leuart_dma_mode_t *)(leuart->tx_mode);
+    leuart = (struct efm32_leuart_device_t *)(dev->user_data);
+    dma_tx = (struct efm32_leuart_dma_mode_t *)(leuart->tx_mode);
 
-	/* invoke call to notify tx complete */
-	if (dev->tx_complete != RT_NULL)
-	{
-		dev->tx_complete(dev, dma_tx->data_ptr);
-	}
+    /* invoke call to notify tx complete */
+    if (dev->tx_complete != RT_NULL)
+    {
+        dev->tx_complete(dev, dma_tx->data_ptr);
+    }
 
-	/* Set status */
-	leuart->state &= ~(rt_uint32_t)LEUART_STATE_TX_BUSY;
+    /* Set status */
+    leuart->state &= ~(rt_uint32_t)LEUART_STATE_TX_BUSY;
 }
 
 /***************************************************************************//**
 * @brief
-*	Register LEUART device
+*   Register LEUART device
 *
 * @details
 *
 * @note
 *
 * @param[in] device
-*	Pointer to device descriptor
+*   Pointer to device descriptor
 *
 * @param[in] name
-*	Device name
+*   Device name
 *
 * @param[in] flag
-*	Configuration flags
+*   Configuration flags
 *
 * @param[in] leuart
-*	Pointer to LEUART device descriptor
+*   Pointer to LEUART device descriptor
 *
 * @return
-*	Error code
+*   Error code
 ******************************************************************************/
 rt_err_t rt_hw_leuart_register(
-	rt_device_t		device,
-	const char		*name,
-	rt_uint32_t		flag,
-	struct efm32_leuart_device_t *leuart)
+    rt_device_t     device,
+    const char      *name,
+    rt_uint32_t     flag,
+    struct efm32_leuart_device_t *leuart)
 {
-	RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(device != RT_NULL);
 
-	if ((flag & RT_DEVICE_FLAG_DMA_RX) ||
-		(flag & RT_DEVICE_FLAG_INT_TX))
-	{
-		RT_ASSERT(0);
-	}
+    if ((flag & RT_DEVICE_FLAG_DMA_RX) ||
+        (flag & RT_DEVICE_FLAG_INT_TX))
+    {
+        RT_ASSERT(0);
+    }
 
-	device->type 		= RT_Device_Class_Char;
-	device->rx_indicate = RT_NULL;
-	device->tx_complete = RT_NULL;
-	device->init 		= rt_leuart_init;
-	device->open		= rt_leuart_open;
-	device->close		= rt_leuart_close;
-	device->read 		= rt_leuart_read;
-	device->write 		= rt_leuart_write;
-	device->control 	= rt_leuart_control;
-	device->user_data	= leuart;
+    device->type        = RT_Device_Class_Char;
+    device->rx_indicate = RT_NULL;
+    device->tx_complete = RT_NULL;
+    device->init        = rt_leuart_init;
+    device->open        = rt_leuart_open;
+    device->close       = rt_leuart_close;
+    device->read        = rt_leuart_read;
+    device->write       = rt_leuart_write;
+    device->control     = rt_leuart_control;
+    device->user_data   = leuart;
 
-	/* register a character device */
-	return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
+    /* register a character device */
+    return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
 }
 
 /***************************************************************************//**
 * @brief
-*	Initialize the specified LEUART unit
+*   Initialize the specified LEUART unit
 *
 * @details
 *
 * @note
 *
 * @param[in] device
-*	Pointer to device descriptor
+*   Pointer to device descriptor
 *
 * @param[in] unitNumber
-*	Unit number
+*   Unit number
 *
 * @param[in] location
-*	Pin location number
+*   Pin location number
 *
 * @param[in] flag
-*	Configuration flag
+*   Configuration flag
 *
 * @param[in] dmaChannel
-*	DMA channel number for TX
+*   DMA channel number for TX
 *
 * @param[in] console
-*	Indicate if using as console
+*   Indicate if using as console
 *
 * @return
-*	Pointer to LEUART device
+*   Pointer to LEUART device
 ******************************************************************************/
 static struct efm32_leuart_device_t *rt_hw_leuart_unit_init(
-	rt_device_t device,
-	rt_uint8_t 	unitNumber,
-	rt_uint8_t 	location,
-	rt_uint32_t flag,
-	rt_uint32_t	dmaChannel,
-	rt_uint8_t 	config)
+    rt_device_t device,
+    rt_uint8_t  unitNumber,
+    rt_uint8_t  location,
+    rt_uint32_t flag,
+    rt_uint32_t dmaChannel,
+    rt_uint8_t  config)
 {
-	struct efm32_leuart_device_t 	*leuart;
-	struct efm32_leuart_dma_mode_t	*dma_mode;
-	DMA_CB_TypeDef					*callback;
-	CMU_Clock_TypeDef				leuartClock;
-	rt_uint32_t						txDmaSelect;
-	GPIO_Port_TypeDef 				port_tx, port_rx, port_clk, port_cs;
-	rt_uint32_t 					pin_tx, pin_rx, pin_clk, pin_cs;
+    struct efm32_leuart_device_t    *leuart;
+    struct efm32_leuart_dma_mode_t  *dma_mode;
+    DMA_CB_TypeDef                  *callback;
+    CMU_Clock_TypeDef               leuartClock;
+    rt_uint32_t                     txDmaSelect;
+    GPIO_Port_TypeDef               port_tx, port_rx, port_clk, port_cs;
+    rt_uint32_t                     pin_tx, pin_rx, pin_clk, pin_cs;
     LEUART_Init_TypeDef             init = LEUART_INIT_DEFAULT;
-	efm32_irq_hook_init_t			hook;
+    efm32_irq_hook_init_t           hook;
 
-	do
-	{
-		/* Allocate device */
-		leuart = rt_malloc(sizeof(struct efm32_leuart_device_t));
-		if (leuart == RT_NULL)
-		{
-			leuart_debug("LEUART%d err: no mem\n", unitNumber);
-			break;
-		}
-		leuart->counter = 0;
-		leuart->unit    = unitNumber;
-		leuart->state   = config;
-		leuart->tx_mode = RT_NULL;
-		leuart->rx_mode = RT_NULL;
+    do
+    {
+        /* Allocate device */
+        leuart = rt_malloc(sizeof(struct efm32_leuart_device_t));
+        if (leuart == RT_NULL)
+        {
+            leuart_debug("LEUART%d err: no mem\n", unitNumber);
+            break;
+        }
+        leuart->counter = 0;
+        leuart->unit    = unitNumber;
+        leuart->state   = config;
+        leuart->tx_mode = RT_NULL;
+        leuart->rx_mode = RT_NULL;
 
-		/* Allocate TX */
-		dma_mode = RT_NULL;
-		if (flag & RT_DEVICE_FLAG_DMA_TX)
-		{
-			leuart->tx_mode = dma_mode = rt_malloc(sizeof(struct efm32_leuart_dma_mode_t));
-			if (dma_mode == RT_NULL)
-			{
-				leuart_debug("LEUART%d err: no mem for DMA TX\n", unitNumber);
-				break;
-			}
-			dma_mode->dma_channel = dmaChannel;
-		}
+        /* Allocate TX */
+        dma_mode = RT_NULL;
+        if (flag & RT_DEVICE_FLAG_DMA_TX)
+        {
+            leuart->tx_mode = dma_mode = rt_malloc(sizeof(struct efm32_leuart_dma_mode_t));
+            if (dma_mode == RT_NULL)
+            {
+                leuart_debug("LEUART%d err: no mem for DMA TX\n", unitNumber);
+                break;
+            }
+            dma_mode->dma_channel = dmaChannel;
+        }
 
-		/* Allocate RX */
-		if (flag & RT_DEVICE_FLAG_INT_RX)
-		{
-			leuart->rx_mode = rt_malloc(sizeof(struct efm32_leuart_int_mode_t));
-			if (leuart->rx_mode == RT_NULL)
-			{
-				leuart_debug("LEUART%d err: no mem for INT RX\n, unitNumber");
-				break;
-			}
-		}
+        /* Allocate RX */
+        if (flag & RT_DEVICE_FLAG_INT_RX)
+        {
+            leuart->rx_mode = rt_malloc(sizeof(struct efm32_leuart_int_mode_t));
+            if (leuart->rx_mode == RT_NULL)
+            {
+                leuart_debug("LEUART%d err: no mem for INT RX\n, unitNumber");
+                break;
+            }
+        }
 
-		/* Initialization */
-		if (unitNumber >= LEUART_COUNT)
-		{
-			break;
-		}
-		switch (unitNumber)
-		{
-		case 0:
-			leuart->leuart_device    = LEUART0;
-			leuartClock             = (CMU_Clock_TypeDef)cmuClock_LEUART0;
-			txDmaSelect             = DMAREQ_LEUART0_TXBL;
-			port_tx                 = AF_LEUART0_TX_PORT(location);
-			pin_tx                  = AF_LEUART0_TX_PIN(location);
-			port_rx                 = AF_LEUART0_RX_PORT(location);
-			pin_rx                  = AF_LEUART0_RX_PIN(location);
-			break;
+        /* Initialization */
+        if (unitNumber >= LEUART_COUNT)
+        {
+            break;
+        }
+        switch (unitNumber)
+        {
+        case 0:
+            leuart->leuart_device    = LEUART0;
+            leuartClock             = (CMU_Clock_TypeDef)cmuClock_LEUART0;
+            txDmaSelect             = DMAREQ_LEUART0_TXBL;
+            port_tx                 = AF_LEUART0_TX_PORT(location);
+            pin_tx                  = AF_LEUART0_TX_PIN(location);
+            port_rx                 = AF_LEUART0_RX_PORT(location);
+            pin_rx                  = AF_LEUART0_RX_PIN(location);
+            break;
 #if (LEUART_COUNT > 1)
-		case 1:
-			leuart->leuart_device    = LEUART1;
-			leuartClock             = (CMU_Clock_TypeDef)cmuClock_LEUART1;
-			txDmaSelect             = DMAREQ_LEUART1_TXBL;
-			port_tx                 = AF_LEUART1_TX_PORT(location);
-			pin_tx                  = AF_LEUART1_TX_PIN(location);
-			port_rx                 = AF_LEUART1_RX_PORT(location);
-			pin_rx                  = AF_LEUART1_RX_PIN(location);
-			break;
+        case 1:
+            leuart->leuart_device    = LEUART1;
+            leuartClock             = (CMU_Clock_TypeDef)cmuClock_LEUART1;
+            txDmaSelect             = DMAREQ_LEUART1_TXBL;
+            port_tx                 = AF_LEUART1_TX_PORT(location);
+            pin_tx                  = AF_LEUART1_TX_PIN(location);
+            port_rx                 = AF_LEUART1_RX_PORT(location);
+            pin_rx                  = AF_LEUART1_RX_PIN(location);
+            break;
 #endif
-		default:
-			break;
-		}
+        default:
+            break;
+        }
 
         /* Do not prescale clock */
         CMU_ClockDivSet(leuartClock, cmuClkDiv_1);
@@ -884,98 +884,98 @@ static struct efm32_leuart_device_t *rt_hw_leuart_unit_init(
         /* Enable LEUART clock */
         CMU_ClockEnable(leuartClock, true);
 
-		/* Config GPIO */
-		GPIO_PinModeSet(
-			port_tx,
-			pin_tx,
-			gpioModePushPull,
-			0);
-		GPIO_PinModeSet(
-			port_rx,
-			pin_rx,
-			gpioModeInputPull,
-			1);
+        /* Config GPIO */
+        GPIO_PinModeSet(
+            port_tx,
+            pin_tx,
+            gpioModePushPull,
+            0);
+        GPIO_PinModeSet(
+            port_rx,
+            pin_rx,
+            gpioModeInputPull,
+            1);
 
-		/* Config interrupt and NVIC */
-		if (flag & RT_DEVICE_FLAG_INT_RX)
-		{
-			hook.type		= efm32_irq_type_leuart;
-			hook.unit		= unitNumber;
-			hook.cbFunc 	= rt_hw_leuart_rx_isr;
-			hook.userPtr	= device;
-			efm32_irq_hook_register(&hook);
-		}
+        /* Config interrupt and NVIC */
+        if (flag & RT_DEVICE_FLAG_INT_RX)
+        {
+            hook.type       = efm32_irq_type_leuart;
+            hook.unit       = unitNumber;
+            hook.cbFunc     = rt_hw_leuart_rx_isr;
+            hook.userPtr    = device;
+            efm32_irq_hook_register(&hook);
+        }
 
-		/* Config DMA */
-		if (flag & RT_DEVICE_FLAG_DMA_TX)
-		{
-			DMA_CfgChannel_TypeDef	chnlCfg;
-			DMA_CfgDescr_TypeDef	descrCfg;
+        /* Config DMA */
+        if (flag & RT_DEVICE_FLAG_DMA_TX)
+        {
+            DMA_CfgChannel_TypeDef  chnlCfg;
+            DMA_CfgDescr_TypeDef    descrCfg;
 
-			hook.type 			= efm32_irq_type_dma;
-			hook.unit 			= dmaChannel;
-			hook.cbFunc			= rt_hw_leuart_dma_tx_isr;
-			hook.userPtr 		= device;
-			efm32_irq_hook_register(&hook);
+            hook.type           = efm32_irq_type_dma;
+            hook.unit           = dmaChannel;
+            hook.cbFunc         = rt_hw_leuart_dma_tx_isr;
+            hook.userPtr        = device;
+            efm32_irq_hook_register(&hook);
 
-			callback = (DMA_CB_TypeDef *)rt_malloc(sizeof(DMA_CB_TypeDef));
-			if (callback == RT_NULL)
-			{
-				leuart_debug("LEUART%d err: no mem for callback\n", unitNumber);
-				break;
-			}
-			callback->cbFunc	= DMA_IRQHandler_All;
-			callback->userPtr	= RT_NULL;
-			callback->primary	= 0;
+            callback = (DMA_CB_TypeDef *)rt_malloc(sizeof(DMA_CB_TypeDef));
+            if (callback == RT_NULL)
+            {
+                leuart_debug("LEUART%d err: no mem for callback\n", unitNumber);
+                break;
+            }
+            callback->cbFunc    = DMA_IRQHandler_All;
+            callback->userPtr   = RT_NULL;
+            callback->primary   = 0;
 
-			/* Setting up DMA channel */
-			chnlCfg.highPri		= false;	/* Can't use with peripherals */
-			chnlCfg.enableInt 	= true;		/* Interrupt for callback function */
-			chnlCfg.select 		= txDmaSelect;
-			chnlCfg.cb			= callback;
-			DMA_CfgChannel(dmaChannel, &chnlCfg);
+            /* Setting up DMA channel */
+            chnlCfg.highPri     = false;    /* Can't use with peripherals */
+            chnlCfg.enableInt   = true;     /* Interrupt for callback function */
+            chnlCfg.select      = txDmaSelect;
+            chnlCfg.cb          = callback;
+            DMA_CfgChannel(dmaChannel, &chnlCfg);
 
-			/* Setting up DMA channel descriptor */
-			descrCfg.dstInc 	= dmaDataIncNone;
-			descrCfg.srcInc 	= dmaDataInc1;
-			descrCfg.size 		= dmaDataSize1;
-			descrCfg.arbRate 	= dmaArbitrate1;
-			descrCfg.hprot 		= 0;
-			DMA_CfgDescr(dmaChannel, true, &descrCfg);
-		}
+            /* Setting up DMA channel descriptor */
+            descrCfg.dstInc     = dmaDataIncNone;
+            descrCfg.srcInc     = dmaDataInc1;
+            descrCfg.size       = dmaDataSize1;
+            descrCfg.arbRate    = dmaArbitrate1;
+            descrCfg.hprot      = 0;
+            DMA_CfgDescr(dmaChannel, true, &descrCfg);
+        }
 
-		/* Init specified LEUART unit */
+        /* Init specified LEUART unit */
         LEUART_Init(leuart->leuart_device, &init);
 
-		/* Enable RX and TX pins and set location */
-		leuart->leuart_device->ROUTE = LEUART_ROUTE_RXPEN | LEUART_ROUTE_TXPEN | \
-						(location << _LEUART_ROUTE_LOCATION_SHIFT);
+        /* Enable RX and TX pins and set location */
+        leuart->leuart_device->ROUTE = LEUART_ROUTE_RXPEN | LEUART_ROUTE_TXPEN | \
+                        (location << _LEUART_ROUTE_LOCATION_SHIFT);
 
-		/* Clear RX/TX buffers */
-		leuart->leuart_device->CMD = LEUART_CMD_CLEARRX | LEUART_CMD_CLEARTX;
+        /* Clear RX/TX buffers */
+        leuart->leuart_device->CMD = LEUART_CMD_CLEARRX | LEUART_CMD_CLEARTX;
 
-		return leuart;
-	} while(0);
+        return leuart;
+    } while(0);
 
-	if (leuart->rx_mode)
-	{
-		rt_free(leuart->rx_mode);
-	}
-	if (leuart->tx_mode)
-	{
-		rt_free(leuart->tx_mode);
-	}
-	if (leuart)
-	{
-		rt_free(leuart);
-	}
-	if (callback)
-	{
-		rt_free(leuart);
-	}
+    if (leuart->rx_mode)
+    {
+        rt_free(leuart->rx_mode);
+    }
+    if (leuart->tx_mode)
+    {
+        rt_free(leuart->tx_mode);
+    }
+    if (leuart)
+    {
+        rt_free(leuart);
+    }
+    if (callback)
+    {
+        rt_free(leuart);
+    }
 
     leuart_debug("LEUART%d err: init failed!\n", unitNumber);
-	return RT_NULL;
+    return RT_NULL;
 }
 
 /***************************************************************************//**
@@ -989,12 +989,12 @@ static struct efm32_leuart_device_t *rt_hw_leuart_unit_init(
 ******************************************************************************/
 void rt_hw_leuart_init(void)
 {
-	struct efm32_leuart_device_t    *leuart;
-	rt_uint32_t 				    flag;
-	rt_uint8_t					    config;
+    struct efm32_leuart_device_t    *leuart;
+    rt_uint32_t                     flag;
+    rt_uint8_t                      config;
 
-	do
-	{
+    do
+    {
 #ifdef RT_USING_LEUART0
         config = 0;
         flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX;
@@ -1073,11 +1073,11 @@ void rt_hw_leuart_init(void)
         }
 #endif
 
-		leuart_debug("LEUART: H/W init OK!\n");
-		return;
-	} while (0);
+        leuart_debug("LEUART: H/W init OK!\n");
+        return;
+    } while (0);
 
-	rt_kprintf("LEUART: H/W init failed!\n");
+    rt_kprintf("LEUART: H/W init failed!\n");
 }
 
 #endif /* (defined(RT_USING_LEUART0) || defined(RT_USING_LEUART1)) */
diff --git a/bsp/efm32/drv_leuart.h b/bsp/efm32/drv_leuart.h
index 692ff0d520..b7c24bb025 100644
--- a/bsp/efm32/drv_leuart.h
+++ b/bsp/efm32/drv_leuart.h
@@ -1,8 +1,8 @@
 /***************************************************************************//**
- * @file 	drv_leuart.h
- * @brief 	LEUART driver of RT-Thread RTOS for EFM32
+ * @file    drv_leuart.h
+ * @brief   LEUART driver of RT-Thread RTOS for EFM32
  *  COPYRIGHT (C) 2012, RT-Thread Development Team
- * @author 	onelife
+ * @author  onelife
  * @version 1.0
  *******************************************************************************
  * @section License
@@ -10,8 +10,8 @@
  *  LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
  *******************************************************************************
  * @section Change Logs
- * Date			Author		Notes
- * 2011-12-09	onelife		Initial creation for EFM32
+ * Date         Author      Notes
+ * 2011-12-09   onelife     Initial creation for EFM32
  ******************************************************************************/
 #ifndef __DRV_LEUSART_H__
 #define __DRV_LEUSART_H__
@@ -20,37 +20,37 @@
 /* Exported types ------------------------------------------------------------*/
 struct efm32_leuart_int_mode_t
 {
-	rt_uint8_t  		*data_ptr;
-	rt_uint8_t  		data_size;
-	rt_uint32_t 		read_index, save_index;
+    rt_uint8_t          *data_ptr;
+    rt_uint8_t          data_size;
+    rt_uint32_t         read_index, save_index;
 };
 
 struct efm32_leuart_dma_mode_t
 {
-	/* DMA Channel */
-	rt_uint32_t 		dma_channel;
+    /* DMA Channel */
+    rt_uint32_t         dma_channel;
 
-	/* buffer info */
-	rt_uint32_t 		*data_ptr;
-	rt_uint8_t  		data_size;
+    /* buffer info */
+    rt_uint32_t         *data_ptr;
+    rt_uint8_t          data_size;
 };
 
 struct efm32_leuart_device_t
 {
-	/* Counter */
-	rt_uint32_t 		counter;
-	/* Lock */
-	struct rt_semaphore	*lock;
-	/* Unit number */
-	rt_uint8_t 			unit;
-	/* State */
-	volatile rt_uint8_t	state;
-	/*  Pointer to LEUART device structure */
-	LEUART_TypeDef 		*leuart_device;
-	/* Pointer to RX structure */
-	void 				*rx_mode;
-	/* Pointer to TX structure */
-	void 				*tx_mode;
+    /* Counter */
+    rt_uint32_t         counter;
+    /* Lock */
+    struct rt_semaphore *lock;
+    /* Unit number */
+    rt_uint8_t          unit;
+    /* State */
+    volatile rt_uint8_t state;
+    /*  Pointer to LEUART device structure */
+    LEUART_TypeDef      *leuart_device;
+    /* Pointer to RX structure */
+    void                *rx_mode;
+    /* Pointer to TX structure */
+    void                *tx_mode;
 };
 
 /* Exported constants --------------------------------------------------------*/
diff --git a/bsp/efm32/drv_rtc.c b/bsp/efm32/drv_rtc.c
index 16604a3919..75713fe3b4 100644
--- a/bsp/efm32/drv_rtc.c
+++ b/bsp/efm32/drv_rtc.c
@@ -10,7 +10,7 @@
  *  LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
  *******************************************************************************
  * @section Change Logs
- * Date			Author		Notes
+ * Date         Author      Notes
  * 2009-01-05   Bernard     the first version
  * 2010-12-27   onelife     Modify for EFM32
  * 2011-06-16   onelife     Modify init function for efm32lib v2 upgrading
@@ -33,7 +33,7 @@
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
 #ifdef RT_RTC_DEBUG
-#define rtc_debug(format,args...) 			rt_kprintf(format, ##args)
+#define rtc_debug(format,args...)           rt_kprintf(format, ##args)
 #else
 #define rtc_debug(format,args...)
 #endif
@@ -55,10 +55,10 @@ static rt_err_t rt_rtc_open(rt_device_t dev, rt_uint16_t oflag)
 }
 
 static rt_size_t rt_rtc_read(
-	rt_device_t 	dev,
-	rt_off_t 		pos,
-	void* 			buffer,
-	rt_size_t 		size)
+    rt_device_t     dev,
+    rt_off_t        pos,
+    void*           buffer,
+    rt_size_t       size)
 {
     return 0;
 }
@@ -91,16 +91,16 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args)
     {
     case RT_DEVICE_CTRL_RTC_GET_TIME:
         *(rt_uint32_t *)args = rtc_time + RTC_CounterGet();
-		rtc_debug("RTC: get rtc_time %x + %x\n", rtc_time, RTC_CounterGet());
+        rtc_debug("RTC: get rtc_time %x + %x\n", rtc_time, RTC_CounterGet());
         break;
 
     case RT_DEVICE_CTRL_RTC_SET_TIME:
     {
         rtc_time = *(rt_uint32_t *)args;
-		rtc_debug("RTC: set rtc_time %x\n", rtc_time);
+        rtc_debug("RTC: set rtc_time %x\n", rtc_time);
 
-		/* Reset counter */
-		RTC_CounterReset();
+        /* Reset counter */
+        RTC_CounterReset();
     }
     break;
     }
@@ -118,12 +118,12 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args)
  ******************************************************************************/
 void rt_hw_rtc_isr(rt_device_t device)
 {
-	if (RTC->IF & RTC_IFC_OF)
-	{
-		rtc_time += _RTC_CNT_MASK;
-	}
+    if (RTC->IF & RTC_IFC_OF)
+    {
+        rtc_time += _RTC_CNT_MASK;
+    }
 
-	RTC->IFC = _RTC_IFC_MASK;
+    RTC->IFC = _RTC_IFC_MASK;
 }
 
 /***************************************************************************//**
@@ -147,25 +147,25 @@ void rt_hw_rtc_isr(rt_device_t device)
  *  Error code
  ******************************************************************************/
 rt_err_t rt_hw_rtc_register(
-	rt_device_t		device,
-	const char		*name,
-	rt_uint32_t		flag)
+    rt_device_t     device,
+    const char      *name,
+    rt_uint32_t     flag)
 {
-	RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(device != RT_NULL);
 
-	device->type 		= RT_Device_Class_RTC;
-	device->rx_indicate = RT_NULL;
-	device->tx_complete = RT_NULL;
-	device->init 		= RT_NULL;
-	device->open		= rt_rtc_open;
-	device->close		= RT_NULL;
-	device->read 		= rt_rtc_read;
-	device->write 		= RT_NULL;
-	device->control 	= rt_rtc_control;
-	device->user_data	= RT_NULL; /* no private */
+    device->type        = RT_Device_Class_RTC;
+    device->rx_indicate = RT_NULL;
+    device->tx_complete = RT_NULL;
+    device->init        = RT_NULL;
+    device->open        = rt_rtc_open;
+    device->close       = RT_NULL;
+    device->read        = rt_rtc_read;
+    device->write       = RT_NULL;
+    device->control     = rt_rtc_control;
+    device->user_data   = RT_NULL; /* no private */
 
-	/* register a character device */
-	return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
+    /* register a character device */
+    return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
 }
 
 
@@ -179,50 +179,50 @@ rt_err_t rt_hw_rtc_register(
  ******************************************************************************/
 void rt_hw_rtc_init(void)
 {
-	rt_uint32_t reset;
+    rt_uint32_t reset;
 
-	reset = RMU_ResetCauseGet();
+    reset = RMU_ResetCauseGet();
 
-	// TODO: What is the current reset mode?
-	if (reset & RMU_RSTCAUSE_PORST || reset & RMU_RSTCAUSE_EXTRST)
+    // TODO: What is the current reset mode?
+    if (reset & RMU_RSTCAUSE_PORST || reset & RMU_RSTCAUSE_EXTRST)
     {
-    	RTC_Init_TypeDef rtcInit;
-		efm32_irq_hook_init_t hook;
+        RTC_Init_TypeDef rtcInit;
+        efm32_irq_hook_init_t hook;
 
-		rtcInit.enable = true;
-		rtcInit.debugRun = false;
-		rtcInit.comp0Top = false;
+        rtcInit.enable = true;
+        rtcInit.debugRun = false;
+        rtcInit.comp0Top = false;
 
-		rtc_time = 0UL;
+        rtc_time = 0UL;
 
         rt_kprintf("rtc is not configured\n");
         rt_kprintf("please configure with set_date and set_time\n");
 
-		/* Configuring clock */
+        /* Configuring clock */
         CMU_ClockDivSet(cmuClock_RTC,cmuClkDiv_32768);
         CMU_ClockEnable(cmuClock_RTC, true);
 
-		/* Initialize and enable RTC */
-		RTC_Reset();
-		RTC_Init(&rtcInit);
+        /* Initialize and enable RTC */
+        RTC_Reset();
+        RTC_Init(&rtcInit);
 
-		hook.type		= efm32_irq_type_rtc;
-		hook.unit		= 0;
-		hook.cbFunc 	= rt_hw_rtc_isr;
-		hook.userPtr	= RT_NULL;
-		efm32_irq_hook_register(&hook);
+        hook.type       = efm32_irq_type_rtc;
+        hook.unit       = 0;
+        hook.cbFunc     = rt_hw_rtc_isr;
+        hook.userPtr    = RT_NULL;
+        efm32_irq_hook_register(&hook);
 
-		/* Enabling Interrupt from RTC */
-		RTC_IntEnable(RTC_IFC_OF);
-		RTC_IntClear(RTC_IFC_OF);
+        /* Enabling Interrupt from RTC */
+        RTC_IntEnable(RTC_IFC_OF);
+        RTC_IntClear(RTC_IFC_OF);
 
-		NVIC_ClearPendingIRQ(RTC_IRQn);
-		NVIC_SetPriority(RTC_IRQn, EFM32_IRQ_PRI_DEFAULT);
-		NVIC_EnableIRQ(RTC_IRQn);
+        NVIC_ClearPendingIRQ(RTC_IRQn);
+        NVIC_SetPriority(RTC_IRQn, EFM32_IRQ_PRI_DEFAULT);
+        NVIC_EnableIRQ(RTC_IRQn);
     }
 
     /* register rtc device */
-	rt_hw_rtc_register(&rtc, RT_RTC_NAME, EFM32_NO_DATA);
+    rt_hw_rtc_register(&rtc, RT_RTC_NAME, EFM32_NO_DATA);
 }
 
 #endif
diff --git a/bsp/efm32/drv_rtc.h b/bsp/efm32/drv_rtc.h
index 492fc59d56..7e33c03896 100644
--- a/bsp/efm32/drv_rtc.h
+++ b/bsp/efm32/drv_rtc.h
@@ -10,7 +10,7 @@
  *  LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
  *******************************************************************************
  * @section Change Logs
- * Date			Author		Notes
+ * Date         Author      Notes
  * 2009-01-05   Bernard     the first version
  * 2010-12-27   onelife     Modification for EFM32
  *********************************************************************/
diff --git a/bsp/efm32/drv_sdcard.h b/bsp/efm32/drv_sdcard.h
index 17c94209c9..2c9a1bfc39 100644
--- a/bsp/efm32/drv_sdcard.h
+++ b/bsp/efm32/drv_sdcard.h
@@ -1,9 +1,9 @@
 /***************************************************************************//**
- * @file 	drv_sdcard.h
- * @brief 	Memory card driver (SPI mode) of RT-Thread RTOS for using EFM32
+ * @file    drv_sdcard.h
+ * @brief   Memory card driver (SPI mode) of RT-Thread RTOS for using EFM32
  *  USART module
  *  COPYRIGHT (C) 2012, RT-Thread Development Team
- * @author 	onelife
+ * @author  onelife
  * @version 1.0
  *******************************************************************************
  * @section License
@@ -11,9 +11,9 @@
  *  LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
  *******************************************************************************
  * @section Change Logs
- * Date			Author		Notes
- * 2011-05-13	onelife		Initial creation for using EFM32 USART module
- * 2011-07-07	onelife		Modify initialization function to return error code
+ * Date         Author      Notes
+ * 2011-05-13   onelife     Initial creation for using EFM32 USART module
+ * 2011-07-07   onelife     Modify initialization function to return error code
  ******************************************************************************/
 #ifndef __DEV_SDCARD_H__
 #define __DEV_SDCARD_H__
@@ -33,43 +33,43 @@
 #error "EFM32 SPI clock should not be more than (EFM32_HFXO_FREQUENCY/2)"
 #endif
 
-#define SD_SPEED_LOW 			(0)
-#define SD_SPEED_HIGH 			(1)
-#define SD_WAIT_PERIOD 			(RT_TICK_PER_SECOND)
+#define SD_SPEED_LOW            (0)
+#define SD_SPEED_HIGH           (1)
+#define SD_WAIT_PERIOD          (RT_TICK_PER_SECOND)
 
-#define SD_SECTOR_SIZE_SHIFT	(9)
-#define SD_SECTOR_SIZE 			(1 << SD_SECTOR_SIZE_SHIFT)
-#define SD_BLOCK_SIZE_CSD 		(16)
-#define SD_BLOCK_SIZE_CID 		(16)
-#define SD_BLOCK_SIZE_OCR 		(4)
-#define SD_BLOCK_SIZE_SDSTAT 	(64)
+#define SD_SECTOR_SIZE_SHIFT    (9)
+#define SD_SECTOR_SIZE          (1 << SD_SECTOR_SIZE_SHIFT)
+#define SD_BLOCK_SIZE_CSD       (16)
+#define SD_BLOCK_SIZE_CID       (16)
+#define SD_BLOCK_SIZE_OCR       (4)
+#define SD_BLOCK_SIZE_SDSTAT    (64)
 
 /* Card type definitions (CardType) */
-#define CT_MMC					(0x01)
-#define CT_SD1					(0x02)
-#define CT_SD2					(0x04)
-#define CT_SDC					(CT_SD1|CT_SD2)
-#define CT_BLOCK				(0x08)
+#define CT_MMC                  (0x01)
+#define CT_SD1                  (0x02)
+#define CT_SD2                  (0x04)
+#define CT_SDC                  (CT_SD1|CT_SD2)
+#define CT_BLOCK                (0x08)
 
 /* Definitions for MMC/SDC command */
-#define CMD0 					(0) 		/* GO_IDLE_STATE */
-#define CMD1 					(1) 		/* SEND_OP_COND */
-#define ACMD41 					(41|0x80) 	/* SEND_OP_COND (SDC) */
-#define CMD8 					(8) 		/* SEND_IF_COND */
-#define CMD9 					(9) 		/* SEND_CSD */
-#define CMD10 					(10) 		/* SEND_CID */
-#define CMD12 					(12) 		/* STOP_TRANSMISSION */
-#define ACMD13 					(13|0x80) 	/* SD_STATUS (SDC) */
-#define CMD16 					(16) 		/* SET_BLOCKLEN */
-#define CMD17 					(17) 		/* READ_SINGLE_BLOCK */
-#define CMD18 					(18) 		/* READ_MULTIPLE_BLOCK */
-#define CMD23 					(23) 		/* SET_BLOCK_COUNT */
-#define ACMD23 					(23|0x80) 	/* SET_WR_BLK_ERASE_COUNT (SDC) */
-#define CMD24 					(24) 		/* WRITE_BLOCK */
-#define CMD25 					(25) 		/* WRITE_MULTIPLE_BLOCK */
-#define CMD41 					(41) 		/* SEND_OP_COND (ACMD) */
-#define CMD55 					(55) 		/* APP_CMD */
-#define CMD58 					(58) 		/* READ_OCR */
+#define CMD0                    (0)         /* GO_IDLE_STATE */
+#define CMD1                    (1)         /* SEND_OP_COND */
+#define ACMD41                  (41|0x80)   /* SEND_OP_COND (SDC) */
+#define CMD8                    (8)         /* SEND_IF_COND */
+#define CMD9                    (9)         /* SEND_CSD */
+#define CMD10                   (10)        /* SEND_CID */
+#define CMD12                   (12)        /* STOP_TRANSMISSION */
+#define ACMD13                  (13|0x80)   /* SD_STATUS (SDC) */
+#define CMD16                   (16)        /* SET_BLOCKLEN */
+#define CMD17                   (17)        /* READ_SINGLE_BLOCK */
+#define CMD18                   (18)        /* READ_MULTIPLE_BLOCK */
+#define CMD23                   (23)        /* SET_BLOCK_COUNT */
+#define ACMD23                  (23|0x80)   /* SET_WR_BLK_ERASE_COUNT (SDC) */
+#define CMD24                   (24)        /* WRITE_BLOCK */
+#define CMD25                   (25)        /* WRITE_MULTIPLE_BLOCK */
+#define CMD41                   (41)        /* SEND_OP_COND (ACMD) */
+#define CMD55                   (55)        /* APP_CMD */
+#define CMD58                   (58)        /* READ_OCR */
 
 /* Exported functions ------------------------------------------------------- */
 rt_err_t efm_spiSd_init(void);
diff --git a/bsp/efm32/drv_timer.c b/bsp/efm32/drv_timer.c
index ccfb96ab0e..12e347544c 100644
--- a/bsp/efm32/drv_timer.c
+++ b/bsp/efm32/drv_timer.c
@@ -10,7 +10,7 @@
  * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
  *******************************************************************************
  * @section Change Logs
- * Date			Author		Notes
+ * Date         Author      Notes
  * 2011-01-18   onelife     Initial creation for EFM32
  * 2011-06-17   onelife     Modify init function for efm32lib v2 upgrading
  ******************************************************************************/
diff --git a/bsp/efm32/drv_usart.c b/bsp/efm32/drv_usart.c
index 7cfb50b0a7..c511a31475 100644
--- a/bsp/efm32/drv_usart.c
+++ b/bsp/efm32/drv_usart.c
@@ -34,9 +34,9 @@
  * 2011-12-20   onelife     Add 9-bit SPI mode support
  * 2011-12-20   onelife     Change SPI write format (same as SPI read)
  * 2011-12-20   onelife     Change USART status format
- * 2011-12-27	onelife		Utilize "USART_PRESENT", "USART_COUNT",
+ * 2011-12-27   onelife     Utilize "USART_PRESENT", "USART_COUNT",
  *  "UART_PRESENT" and "UART_COUNT"
- * 2012-05-16	onelife		Fix a bug in rt_hw_usart_init()
+ * 2012-05-16   onelife     Fix a bug in rt_hw_usart_init()
  ******************************************************************************/
 
 /***************************************************************************//**
diff --git a/bsp/efm32/enc28j60.h b/bsp/efm32/enc28j60.h
index 1351e145a3..5955c603e7 100644
--- a/bsp/efm32/enc28j60.h
+++ b/bsp/efm32/enc28j60.h
@@ -1,11 +1,7 @@
 /*
- * File      : enc28j60.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -197,9 +193,9 @@
 #define MACON3_FRMLNEN   0x02
 #define MACON3_FULDPX    0x01
 // ENC28J60 MACON4 Register Bit Definitions
-#define	MACON4_DEFER	(1<<6)
-#define	MACON4_BPEN		(1<<5)
-#define	MACON4_NOBKOFF	(1<<4)
+#define MACON4_DEFER    (1<<6)
+#define MACON4_BPEN     (1<<5)
+#define MACON4_NOBKOFF  (1<<4)
 // ENC28J60 MICMD Register Bit Definitions
 #define MICMD_MIISCAN    0x02
 #define MICMD_MIIRD      0x01
@@ -218,12 +214,12 @@
 #define PHSTAT1_LLSTAT   0x0004
 #define PHSTAT1_JBSTAT   0x0002
 /* ENC28J60 PHY PHSTAT2 Register Bit Definitions */
-#define PHSTAT2_TXSTAT	(1 << 13)
-#define PHSTAT2_RXSTAT	(1 << 12)
-#define PHSTAT2_COLSTAT	(1 << 11)
-#define PHSTAT2_LSTAT	(1 << 10)
-#define PHSTAT2_DPXSTAT	(1 << 9)
-#define PHSTAT2_PLRITY	(1 << 5)
+#define PHSTAT2_TXSTAT  (1 << 13)
+#define PHSTAT2_RXSTAT  (1 << 12)
+#define PHSTAT2_COLSTAT (1 << 11)
+#define PHSTAT2_LSTAT   (1 << 10)
+#define PHSTAT2_DPXSTAT (1 << 9)
+#define PHSTAT2_PLRITY  (1 << 5)
 // ENC28J60 PHY PHCON2 Register Bit Definitions
 #define PHCON2_FRCLINK   0x4000
 #define PHCON2_TXDIS     0x2000
@@ -282,13 +278,13 @@
 #define RSV_GETBIT(x, y)        (((x) & RSV_BITMASK(y)) ? 1 : 0)
 
 // SPI operation codes
-#define ENC28J60_READ_CTRL_REG 		(0x00)
-#define ENC28J60_READ_BUF_MEM 		(0x20 | 0x1A)
-#define ENC28J60_WRITE_CTRL_REG 	(0x40)
-#define ENC28J60_WRITE_BUF_MEM 		(0x60 | 0x1A)
-#define ENC28J60_BIT_FIELD_SET 		(0x80)
-#define ENC28J60_BIT_FIELD_CLR 		(0xA0)
-#define ENC28J60_SOFT_RESET 		(0xE0 | 0x1F)
+#define ENC28J60_READ_CTRL_REG      (0x00)
+#define ENC28J60_READ_BUF_MEM       (0x20 | 0x1A)
+#define ENC28J60_WRITE_CTRL_REG     (0x40)
+#define ENC28J60_WRITE_BUF_MEM      (0x60 | 0x1A)
+#define ENC28J60_BIT_FIELD_SET      (0x80)
+#define ENC28J60_BIT_FIELD_CLR      (0xA0)
+#define ENC28J60_SOFT_RESET         (0xE0 | 0x1F)
 
 // The RXSTART_INIT should be zero. See Rev. B4 Silicon Errata
 // buffer boundaries applied to internal 8K ram
@@ -296,17 +292,17 @@
 //
 
 // start with recbuf at 0/
-#define RXSTART_INIT	0x0
+#define RXSTART_INIT    0x0
 // receive buffer end
-#define RXSTOP_INIT		(0x1FFF - 0x0600 - 1)
+#define RXSTOP_INIT     (0x1FFF - 0x0600 - 1)
 // start TX buffer at 0x1FFF-0x0600, pace for one full ethernet frame (~1500 bytes)
 
-#define TXSTART_INIT	(0x1FFF - 0x0600)
+#define TXSTART_INIT    (0x1FFF - 0x0600)
 // stp TX buffer at end of mem
-#define TXSTOP_INIT		0x1FFF
+#define TXSTOP_INIT     0x1FFF
 
 // max frame length which the conroller will accept:
-#define MAX_FRAMELEN	1518
+#define MAX_FRAMELEN    1518
 
 void rt_hw_enc28j60_init(void);
 
diff --git a/bsp/efm32/graphics/dmd/ssd2119/dmd_ssd2119.h b/bsp/efm32/graphics/dmd/ssd2119/dmd_ssd2119.h
index bb7b7b571b..f6a53d04f9 100644
--- a/bsp/efm32/graphics/dmd/ssd2119/dmd_ssd2119.h
+++ b/bsp/efm32/graphics/dmd/ssd2119/dmd_ssd2119.h
@@ -127,11 +127,11 @@ EMSTATUS DMD_setClippingArea(uint16_t xStart, uint16_t yStart,
                              uint16_t width, uint16_t height);
 EMSTATUS DMD_writeData(uint16_t x, uint16_t y,
                        const uint8_t data[], uint32_t numPixels);
-EMSTATUS DMD_writeDataRLE(uint16_t x, uint16_t y, uint16_t xlen, uint16_t ylen, 
+EMSTATUS DMD_writeDataRLE(uint16_t x, uint16_t y, uint16_t xlen, uint16_t ylen,
                           const uint8_t *data);
-EMSTATUS DMD_writeDataRLEFade(uint16_t x, uint16_t y, uint16_t xlen, uint16_t ylen, 
-			      const uint8_t *data,
-			      int red, int green, int blue, int weight);
+EMSTATUS DMD_writeDataRLEFade(uint16_t x, uint16_t y, uint16_t xlen, uint16_t ylen,
+                  const uint8_t *data,
+                  int red, int green, int blue, int weight);
 EMSTATUS DMD_readData(uint16_t x, uint16_t y,
                       uint8_t data[], uint32_t numPixels);
 EMSTATUS DMD_writeColor(uint16_t x, uint16_t y, uint8_t red,
diff --git a/bsp/efm32/graphics/dmd/ssd2119/dmd_ssd2119_16bit.c b/bsp/efm32/graphics/dmd/ssd2119/dmd_ssd2119_16bit.c
index 73ba5b4ab5..7925891f95 100644
--- a/bsp/efm32/graphics/dmd/ssd2119/dmd_ssd2119_16bit.c
+++ b/bsp/efm32/graphics/dmd/ssd2119/dmd_ssd2119_16bit.c
@@ -425,8 +425,8 @@ EMSTATUS DMD_writeData(uint16_t x, uint16_t y, const uint8_t data[],
 *  DMD_OK on success, otherwise error code
 ******************************************************************************/
 EMSTATUS DMD_writeDataRLEFade(uint16_t x, uint16_t y, uint16_t xlen, uint16_t ylen,
-			      const uint8_t *data,
-			      int red, int green, int blue, int weight)
+                  const uint8_t *data,
+                  int red, int green, int blue, int weight)
 {
    uint32_t color = 0;
    int xpos, ypos;
diff --git a/bsp/efm32/graphics/tftspi.h b/bsp/efm32/graphics/tftspi.h
index 1399fc552e..27e8ce8078 100644
--- a/bsp/efm32/graphics/tftspi.h
+++ b/bsp/efm32/graphics/tftspi.h
@@ -1,8 +1,8 @@
 /***************************************************************************//**
- * @file 	tftspi.h
- * @brief 	Stub functions of EFM32 LCD driver
+ * @file    tftspi.h
+ * @brief   Stub functions of EFM32 LCD driver
  *  COPYRIGHT (C) 2012, RT-Thread Development Team
- * @author 	onelife
+ * @author  onelife
  * @version 1.0
  *******************************************************************************
  * @section License
@@ -10,7 +10,7 @@
  *  LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
  *******************************************************************************
  * @section Change Logs
- * Date			Author		Notes
+ * Date         Author      Notes
  * 2011-12-20   onelife     Initial creation for EFM32
  ******************************************************************************/
 #ifndef __TFTSPI_H__
diff --git a/bsp/efm32/hdl_interrupt.c b/bsp/efm32/hdl_interrupt.c
index de91a9f9a0..8017414e55 100644
--- a/bsp/efm32/hdl_interrupt.c
+++ b/bsp/efm32/hdl_interrupt.c
@@ -13,10 +13,10 @@
  * Date         Author      Notes
  * 2010-12-29   onelife     Initial creation for EFM32
  * 2011-07-12   onelife     Disable interrupts in GPIO handler
- * 2011-12-09	onelife		Add giant gecko support
+ * 2011-12-09   onelife     Add giant gecko support
  * 2011-12-09   onelife     Add UART module support
  * 2011-12-09   onelife     Add LEUART module support
- * 2011-12-27	onelife		Utilize "XXX_PRESENT" and "XXX_COUNT"
+ * 2011-12-27   onelife     Utilize "XXX_PRESENT" and "XXX_COUNT"
  ******************************************************************************/
 
 /* Includes ------------------------------------------------------------------*/
@@ -32,20 +32,20 @@
 /* Private define ------------------------------------------------------------*/
 /* Private macro -------------------------------------------------------------*/
 #ifdef RT_IRQHDL_DEBUG
-#define hdl_debug(format,args...) 			rt_kprintf(format, ##args)
+#define hdl_debug(format,args...)           rt_kprintf(format, ##args)
 #else
 #define hdl_debug(format,args...)
 #endif
 
 /* Private variables ---------------------------------------------------------*/
-efm32_irq_hook_t dmaCbTable[DMA_CHAN_COUNT * 2]	= {RT_NULL};
-efm32_irq_hook_t timerCbTable[TIMER_COUNT] 		= {RT_NULL};
+efm32_irq_hook_t dmaCbTable[DMA_CHAN_COUNT * 2] = {RT_NULL};
+efm32_irq_hook_t timerCbTable[TIMER_COUNT]      = {RT_NULL};
 #if defined(LETIMER_PRESENT)
 efm32_irq_hook_t letimerCbTable[LETIMER_COUNT]  = {RT_NULL};
 #endif
-efm32_irq_hook_t rtcCbTable[RTC_COUNT] 			= {RT_NULL};
-efm32_irq_hook_t gpioCbTable[16] 				= {RT_NULL};
-efm32_irq_hook_t acmpCbTable[ACMP_COUNT] 		= {RT_NULL};
+efm32_irq_hook_t rtcCbTable[RTC_COUNT]          = {RT_NULL};
+efm32_irq_hook_t gpioCbTable[16]                = {RT_NULL};
+efm32_irq_hook_t acmpCbTable[ACMP_COUNT]        = {RT_NULL};
 #if defined(USART_PRESENT)
  #if defined(UART_PRESENT)
 efm32_irq_hook_t usartCbTable[USART_COUNT * 2 + UART_COUNT * 2] = {RT_NULL};
@@ -57,7 +57,7 @@ efm32_irq_hook_t usartCbTable[USART_COUNT * 2]  = {RT_NULL};
 efm32_irq_hook_t leuartCbTable[LEUART_COUNT]    = {RT_NULL};
 #endif
 #if defined(I2C_PRESENT)
-efm32_irq_hook_t iicCbTable[I2C_COUNT] 			= {RT_NULL};
+efm32_irq_hook_t iicCbTable[I2C_COUNT]          = {RT_NULL};
 #endif
 
 /* Private function prototypes -----------------------------------------------*/
@@ -65,7 +65,7 @@ efm32_irq_hook_t iicCbTable[I2C_COUNT] 			= {RT_NULL};
 
 /***************************************************************************//**
  * @brief
- *	NMI exception handler
+ *  NMI exception handler
  *
  * @details
  *
@@ -73,12 +73,12 @@ efm32_irq_hook_t iicCbTable[I2C_COUNT] 			= {RT_NULL};
  ******************************************************************************/
 void NMI_Handler(void)
 {
-	hdl_debug("[NMI_Handler: NOP]\n");
+    hdl_debug("[NMI_Handler: NOP]\n");
 }
 
 /***************************************************************************//**
  * @brief
- *	Memory manage exception handler
+ *  Memory manage exception handler
  *
  * @details
  *
@@ -86,13 +86,13 @@ void NMI_Handler(void)
  ******************************************************************************/
 void MemManage_Handler(void)
 {
-	hdl_debug("[MemManage_Handler: infinite loop]\n");
-	while (1);
+    hdl_debug("[MemManage_Handler: infinite loop]\n");
+    while (1);
 }
 
 /***************************************************************************//**
  * @brief
- *	Bus fault exception handler
+ *  Bus fault exception handler
  *
  * @details
  *
@@ -100,13 +100,13 @@ void MemManage_Handler(void)
  ******************************************************************************/
 void BusFault_Handler(void)
 {
-	hdl_debug("[BusFault_Handler: infinite loop]\n");
-	while (1);
+    hdl_debug("[BusFault_Handler: infinite loop]\n");
+    while (1);
 }
 
 /***************************************************************************//**
  * @brief
- *	Usage fault exception handler
+ *  Usage fault exception handler
  *
  * @details
  *
@@ -114,13 +114,13 @@ void BusFault_Handler(void)
  ******************************************************************************/
 void UsageFault_Handler(void)
 {
-	hdl_debug("[UsageFault_Handler: infinite loop]\n");
-	while (1);
+    hdl_debug("[UsageFault_Handler: infinite loop]\n");
+    while (1);
 }
 
 /***************************************************************************//**
  * @brief
- *	Supervisor call exception handler
+ *  Supervisor call exception handler
  *
  * @details
  *
@@ -128,12 +128,12 @@ void UsageFault_Handler(void)
  ******************************************************************************/
 void SVC_Handler(void)
 {
-	hdl_debug("[SVC_Handler: NOP]\n");
+    hdl_debug("[SVC_Handler: NOP]\n");
 }
 
 /***************************************************************************//**
  * @brief
- *	 Debug monitor exception handler
+ *   Debug monitor exception handler
  *
  * @details
  *
@@ -141,12 +141,12 @@ void SVC_Handler(void)
  ******************************************************************************/
 void DebugMon_Handler(void)
 {
-	hdl_debug("[DebugMon_Handler: NOP]\n");
+    hdl_debug("[DebugMon_Handler: NOP]\n");
 }
 
 /***************************************************************************//**
  * @brief
- * 	System tick timer interrupt handler
+ *  System tick timer interrupt handler
  *
  * @details
  *
@@ -155,13 +155,13 @@ void DebugMon_Handler(void)
  ******************************************************************************/
 void SysTick_Handler(void)
 {
-	/* enter interrupt */
-	rt_interrupt_enter();
+    /* enter interrupt */
+    rt_interrupt_enter();
 
-	rt_tick_increase();
+    rt_tick_increase();
 
-	/* leave interrupt */
-	rt_interrupt_leave();
+    /* leave interrupt */
+    rt_interrupt_leave();
 }
 
 /*******************************************************************************
@@ -173,7 +173,7 @@ void SysTick_Handler(void)
 
 /***************************************************************************//**
  * @brief
- * 	Common DMA interrupt handler
+ *  Common DMA interrupt handler
  *
  * @details
  *
@@ -185,11 +185,11 @@ void DMA_IRQHandler_All(rt_uint32_t channel, rt_bool_t primary, void *user)
     /* enter interrupt */
     rt_interrupt_enter();
 
-	/* invoke callback function */
-	if (dmaCbTable[channel].cbFunc != RT_NULL)
-	{
-		(dmaCbTable[channel].cbFunc)(dmaCbTable[channel].userPtr);
-	}
+    /* invoke callback function */
+    if (dmaCbTable[channel].cbFunc != RT_NULL)
+    {
+        (dmaCbTable[channel].cbFunc)(dmaCbTable[channel].userPtr);
+    }
 
     /* leave interrupt */
     rt_interrupt_leave();
@@ -197,95 +197,95 @@ void DMA_IRQHandler_All(rt_uint32_t channel, rt_bool_t primary, void *user)
 
 /***************************************************************************//**
  * @brief
- * 	Common Timer0 interrupt handler
+ *  Common Timer0 interrupt handler
  *
  * @details
- * 	This function handles Timer0 counter overflow interrupt request
+ *  This function handles Timer0 counter overflow interrupt request
  *
  * @note
  *
  ******************************************************************************/
 void TIMER0_IRQHandler(void)
 {
-	if (TIMER0->IF & TIMER_IF_OF)
-	{
-		/* invoke callback function */
-		if (timerCbTable[0].cbFunc != RT_NULL)
-		{
-			(timerCbTable[0].cbFunc)(timerCbTable[0].userPtr);
-		}
+    if (TIMER0->IF & TIMER_IF_OF)
+    {
+        /* invoke callback function */
+        if (timerCbTable[0].cbFunc != RT_NULL)
+        {
+            (timerCbTable[0].cbFunc)(timerCbTable[0].userPtr);
+        }
 
-		/* clear interrupt */
-		BITBAND_Peripheral(&(TIMER0->IFC), _TIMER_IF_OF_SHIFT, 0x1UL);
-	}
+        /* clear interrupt */
+        BITBAND_Peripheral(&(TIMER0->IFC), _TIMER_IF_OF_SHIFT, 0x1UL);
+    }
 }
 
 
 /***************************************************************************//**
  * @brief
- * 	Common Timer1 interrupt handler
+ *  Common Timer1 interrupt handler
  *
  * @details
- * 	This function handles Timer1 counter overflow interrupt request
+ *  This function handles Timer1 counter overflow interrupt request
  *
  * @note
  *
  ******************************************************************************/
 void TIMER1_IRQHandler(void)
 {
-	if (TIMER1->IF & TIMER_IF_OF)
-	{
-		/* invoke callback function */
-		if (timerCbTable[1].cbFunc != RT_NULL)
-		{
-			(timerCbTable[1].cbFunc)(timerCbTable[1].userPtr);
-		}
+    if (TIMER1->IF & TIMER_IF_OF)
+    {
+        /* invoke callback function */
+        if (timerCbTable[1].cbFunc != RT_NULL)
+        {
+            (timerCbTable[1].cbFunc)(timerCbTable[1].userPtr);
+        }
 
-		/* clear interrupt */
-		BITBAND_Peripheral(&(TIMER1->IFC), _TIMER_IF_OF_SHIFT, 0x1UL);
-	}
+        /* clear interrupt */
+        BITBAND_Peripheral(&(TIMER1->IFC), _TIMER_IF_OF_SHIFT, 0x1UL);
+    }
 }
 
 /***************************************************************************//**
  * @brief
- * 	Common Timer2 interrupt handler
+ *  Common Timer2 interrupt handler
  *
  * @details
- * 	This function handles Timer2 counter overflow interrupt request
+ *  This function handles Timer2 counter overflow interrupt request
  *
  * @note
  *
  ******************************************************************************/
 void TIMER2_IRQHandler(void)
 {
-	if (TIMER2->IF & TIMER_IF_OF)
-	{
-		/* invoke callback function */
-		if (timerCbTable[2].cbFunc != RT_NULL)
-		{
-			(timerCbTable[2].cbFunc)(timerCbTable[2].userPtr);
-		}
+    if (TIMER2->IF & TIMER_IF_OF)
+    {
+        /* invoke callback function */
+        if (timerCbTable[2].cbFunc != RT_NULL)
+        {
+            (timerCbTable[2].cbFunc)(timerCbTable[2].userPtr);
+        }
 
-		/* clear interrupt */
-		BITBAND_Peripheral(&(TIMER2->IFC), _TIMER_IF_OF_SHIFT, 0x1UL);
-	}
+        /* clear interrupt */
+        BITBAND_Peripheral(&(TIMER2->IFC), _TIMER_IF_OF_SHIFT, 0x1UL);
+    }
 }
 
 #if defined(LETIMER_PRESENT)
 /***************************************************************************//**
  * @brief
- * 	Common Low Energy Timer0 interrupt handler
+ *  Common Low Energy Timer0 interrupt handler
  *
  * @details
- * 	This function handles Timer0 counter overflow interrupt request
+ *  This function handles Timer0 counter overflow interrupt request
  *
  * @note
  *
  ******************************************************************************/
 void LETIMER0_IRQHandler(void)
 {
-	if (LETIMER0->IF & LETIMER_IF_UF)
-	{
+    if (LETIMER0->IF & LETIMER_IF_UF)
+    {
         /* enter interrupt */
         rt_interrupt_enter();
 
@@ -294,24 +294,24 @@ void LETIMER0_IRQHandler(void)
         /* leave interrupt */
         rt_interrupt_leave();
 
-		/* invoke callback function */
-/*		if (letimerCbTable[0].cbFunc != RT_NULL)
-		{
-			(letimerCbTable[0].cbFunc)(letimerCbTable[0].userPtr);
-		}
+        /* invoke callback function */
+/*      if (letimerCbTable[0].cbFunc != RT_NULL)
+        {
+            (letimerCbTable[0].cbFunc)(letimerCbTable[0].userPtr);
+        }
 */
-		/* clear interrupt */
-		BITBAND_Peripheral(&(LETIMER0->IFC), _LETIMER_IF_UF_SHIFT, 0x1UL);
-	}
+        /* clear interrupt */
+        BITBAND_Peripheral(&(LETIMER0->IFC), _LETIMER_IF_UF_SHIFT, 0x1UL);
+    }
 }
 #endif
 
 /***************************************************************************//**
  * @brief
- * 	Common RTC interrupt handler
+ *  Common RTC interrupt handler
  *
  * @details
- * 	This function handles RTC counter overflow interrupt request
+ *  This function handles RTC counter overflow interrupt request
  *
  * @note
  *
@@ -321,14 +321,14 @@ void RTC_IRQHandler(void)
     /* enter interrupt */
     rt_interrupt_enter();
 
-	if (RTC->IF & RTC_IF_OF)
-	{
-		/* invoke callback function */
-		if (rtcCbTable[0].cbFunc != RT_NULL)
-		{
-			(rtcCbTable[0].cbFunc)(rtcCbTable[0].userPtr);
-		}
-	}
+    if (RTC->IF & RTC_IF_OF)
+    {
+        /* invoke callback function */
+        if (rtcCbTable[0].cbFunc != RT_NULL)
+        {
+            (rtcCbTable[0].cbFunc)(rtcCbTable[0].userPtr);
+        }
+    }
 
     /* leave interrupt */
     rt_interrupt_leave();
@@ -336,7 +336,7 @@ void RTC_IRQHandler(void)
 
 /***************************************************************************//**
  * @brief
- * 	Common even number GPIO interrupt handler
+ *  Common even number GPIO interrupt handler
  *
  * @details
  *
@@ -345,36 +345,36 @@ void RTC_IRQHandler(void)
  ******************************************************************************/
 void GPIO_EVEN_IRQHandler(void)
 {
-	rt_uint16_t flag, n;
-	rt_base_t level;
+    rt_uint16_t flag, n;
+    rt_base_t level;
 
-	/* Disable interrupt */
-	level = rt_hw_interrupt_disable();
+    /* Disable interrupt */
+    level = rt_hw_interrupt_disable();
     /* Enter ISR */
     rt_interrupt_enter();
 
-	 /* invoke callback function */
-	flag = (rt_uint16_t)(GPIO->IF & 0xFFFF);
-	for ( n = 0; flag > 0; flag = flag >> 2, n = n + 2)
-	{
-		if ((flag & 0x0001) && (gpioCbTable[n].cbFunc != RT_NULL))
-		{
-			(gpioCbTable[n].cbFunc)(gpioCbTable[n].userPtr);
-		}
-	}
+     /* invoke callback function */
+    flag = (rt_uint16_t)(GPIO->IF & 0xFFFF);
+    for ( n = 0; flag > 0; flag = flag >> 2, n = n + 2)
+    {
+        if ((flag & 0x0001) && (gpioCbTable[n].cbFunc != RT_NULL))
+        {
+            (gpioCbTable[n].cbFunc)(gpioCbTable[n].userPtr);
+        }
+    }
 
-	/* clear interrupt */
-	GPIO->IFC = 0x5555UL;
+    /* clear interrupt */
+    GPIO->IFC = 0x5555UL;
 
     /* Leave ISR */
-	rt_interrupt_leave();
-	/* Enable interrupt */
+    rt_interrupt_leave();
+    /* Enable interrupt */
     rt_hw_interrupt_enable(level);
 }
 
 /***************************************************************************//**
  * @brief
- * 	Common odd number GPIO interrupt handler
+ *  Common odd number GPIO interrupt handler
  *
  * @details
  *
@@ -383,39 +383,39 @@ void GPIO_EVEN_IRQHandler(void)
  ******************************************************************************/
 void GPIO_ODD_IRQHandler(void)
 {
-	rt_uint16_t flag, n;
-	rt_base_t level;
+    rt_uint16_t flag, n;
+    rt_base_t level;
 
-	/* Disable interrupt */
-	level = rt_hw_interrupt_disable();
-	/* Enter ISR */
+    /* Disable interrupt */
+    level = rt_hw_interrupt_disable();
+    /* Enter ISR */
     rt_interrupt_enter();
 
-	 /* invoke callback function */
-	flag = (rt_uint16_t)(GPIO->IF & 0xFFFF) >> 1;
-	for ( n = 1; flag > 0; flag = flag >> 2, n = n + 2)
-	{
-		if ((flag & 0x0001) && (gpioCbTable[n].cbFunc != RT_NULL))
-		{
-			(gpioCbTable[n].cbFunc)(gpioCbTable[n].userPtr);
-		}
-	}
+     /* invoke callback function */
+    flag = (rt_uint16_t)(GPIO->IF & 0xFFFF) >> 1;
+    for ( n = 1; flag > 0; flag = flag >> 2, n = n + 2)
+    {
+        if ((flag & 0x0001) && (gpioCbTable[n].cbFunc != RT_NULL))
+        {
+            (gpioCbTable[n].cbFunc)(gpioCbTable[n].userPtr);
+        }
+    }
 
-	/* clear interrupt */
-	GPIO->IFC = 0xAAAAUL;
+    /* clear interrupt */
+    GPIO->IFC = 0xAAAAUL;
 
     /* Leave ISR */
-	rt_interrupt_leave();
-	/* Enable interrupt */
+    rt_interrupt_leave();
+    /* Enable interrupt */
     rt_hw_interrupt_enable(level);
 }
 
 /***************************************************************************//**
  * @brief
- * 	Common ACMP interrupt handler
+ *  Common ACMP interrupt handler
  *
  * @details
- * 	This function handles ACMP edge trigger interrupt request
+ *  This function handles ACMP edge trigger interrupt request
  *
  * @note
  *
@@ -425,29 +425,29 @@ void ACMP0_IRQHandler(void)
     /* enter interrupt */
     rt_interrupt_enter();
 
-	if (ACMP0->IF & ACMP_IF_EDGE)
-	{
-		/* invoke callback function */
-		if (acmpCbTable[0].cbFunc != RT_NULL)
-		{
-			(acmpCbTable[0].cbFunc)(acmpCbTable[0].userPtr);
-		}
+    if (ACMP0->IF & ACMP_IF_EDGE)
+    {
+        /* invoke callback function */
+        if (acmpCbTable[0].cbFunc != RT_NULL)
+        {
+            (acmpCbTable[0].cbFunc)(acmpCbTable[0].userPtr);
+        }
 
-		/* clear interrupt */
-		BITBAND_Peripheral(&(ACMP0->IFC), _ACMP_IF_EDGE_SHIFT, 0x1UL);
-	}
+        /* clear interrupt */
+        BITBAND_Peripheral(&(ACMP0->IFC), _ACMP_IF_EDGE_SHIFT, 0x1UL);
+    }
 
-	if (ACMP1->IF & ACMP_IF_EDGE)
-	{
-		/* invoke callback function */
-		if (acmpCbTable[1].cbFunc != RT_NULL)
-		{
-			(acmpCbTable[1].cbFunc)(acmpCbTable[1].userPtr);
-		}
+    if (ACMP1->IF & ACMP_IF_EDGE)
+    {
+        /* invoke callback function */
+        if (acmpCbTable[1].cbFunc != RT_NULL)
+        {
+            (acmpCbTable[1].cbFunc)(acmpCbTable[1].userPtr);
+        }
 
-		/* clear interrupt */
-		BITBAND_Peripheral(&(ACMP1->IFC), _ACMP_IF_EDGE_SHIFT, 0x1UL);
-	}
+        /* clear interrupt */
+        BITBAND_Peripheral(&(ACMP1->IFC), _ACMP_IF_EDGE_SHIFT, 0x1UL);
+    }
 
     /* leave interrupt */
     rt_interrupt_leave();
@@ -456,10 +456,10 @@ void ACMP0_IRQHandler(void)
 #if defined(USART_PRESENT)
 /***************************************************************************//**
  * @brief
- * 	Common USART0 TX interrupt handler
+ *  Common USART0 TX interrupt handler
  *
  * @details
- * 	This function handles USART0 TX complete interrupt request
+ *  This function handles USART0 TX complete interrupt request
  *
  * @note
  *
@@ -469,17 +469,17 @@ void USART0_TX_IRQHandler(void)
     /* enter interrupt */
     rt_interrupt_enter();
 
-	if (USART0->IF & USART_IF_TXC)
-	{
-		/* invoke callback function */
-		if (usartCbTable[0].cbFunc != RT_NULL)
-		{
-			(usartCbTable[0].cbFunc)(usartCbTable[0].userPtr);
-		}
+    if (USART0->IF & USART_IF_TXC)
+    {
+        /* invoke callback function */
+        if (usartCbTable[0].cbFunc != RT_NULL)
+        {
+            (usartCbTable[0].cbFunc)(usartCbTable[0].userPtr);
+        }
 
-		/* clear interrupt */
-		BITBAND_Peripheral(&(USART0->IFC), _USART_IF_TXC_SHIFT, 0x1UL);
-	}
+        /* clear interrupt */
+        BITBAND_Peripheral(&(USART0->IFC), _USART_IF_TXC_SHIFT, 0x1UL);
+    }
 
     /* leave interrupt */
     rt_interrupt_leave();
@@ -487,34 +487,34 @@ void USART0_TX_IRQHandler(void)
 
 /***************************************************************************//**
  * @brief
- * 	Common USART0 RX interrupt handler
+ *  Common USART0 RX interrupt handler
  *
  * @details
- * 	This function handles USART0 RX data valid interrupt request
+ *  This function handles USART0 RX data valid interrupt request
  *
  * @note
  *
  ******************************************************************************/
 void USART0_RX_IRQHandler(void)
 {
-	if (USART0->IF & USART_IF_RXDATAV)
-	{
-		/* invoke callback function */
-		if (usartCbTable[1].cbFunc != RT_NULL)
-		{
-			(usartCbTable[1].cbFunc)(usartCbTable[1].userPtr);
-		}
-	}
+    if (USART0->IF & USART_IF_RXDATAV)
+    {
+        /* invoke callback function */
+        if (usartCbTable[1].cbFunc != RT_NULL)
+        {
+            (usartCbTable[1].cbFunc)(usartCbTable[1].userPtr);
+        }
+    }
 }
 #endif
 
 #if (defined(USART_PRESENT) && (USART_COUNT > 1))
 /***************************************************************************//**
  * @brief
- * 	Common USART1 TX interrupt handler
+ *  Common USART1 TX interrupt handler
  *
  * @details
- * 	This function handles USART1 TX complete interrupt request
+ *  This function handles USART1 TX complete interrupt request
  *
  * @note
  *
@@ -524,17 +524,17 @@ void USART1_TX_IRQHandler(void)
     /* enter interrupt */
     rt_interrupt_enter();
 
-	if (USART1->IF & USART_IF_TXC)
-	{
-		/* invoke callback function */
-		if (usartCbTable[2].cbFunc != RT_NULL)
-		{
-			(usartCbTable[2].cbFunc)(usartCbTable[2].userPtr);
-		}
+    if (USART1->IF & USART_IF_TXC)
+    {
+        /* invoke callback function */
+        if (usartCbTable[2].cbFunc != RT_NULL)
+        {
+            (usartCbTable[2].cbFunc)(usartCbTable[2].userPtr);
+        }
 
-		/* clear interrupt */
-		BITBAND_Peripheral(&(USART1->IFC), _USART_IF_TXC_SHIFT, 0x1UL);
-	}
+        /* clear interrupt */
+        BITBAND_Peripheral(&(USART1->IFC), _USART_IF_TXC_SHIFT, 0x1UL);
+    }
 
     /* leave interrupt */
     rt_interrupt_leave();
@@ -542,34 +542,34 @@ void USART1_TX_IRQHandler(void)
 
 /***************************************************************************//**
  * @brief
- * 	Common USART1 RX interrupt handler
+ *  Common USART1 RX interrupt handler
  *
  * @details
- * 	This function handles USART1 RX data valid interrupt request
+ *  This function handles USART1 RX data valid interrupt request
  *
  * @note
  *
  ******************************************************************************/
 void USART1_RX_IRQHandler(void)
 {
-	if (USART1->IF & USART_IF_RXDATAV)
-	{
-		/* invoke callback function */
-		if (usartCbTable[3].cbFunc != RT_NULL)
-		{
-			(usartCbTable[3].cbFunc)(usartCbTable[3].userPtr);
-		}
-	}
+    if (USART1->IF & USART_IF_RXDATAV)
+    {
+        /* invoke callback function */
+        if (usartCbTable[3].cbFunc != RT_NULL)
+        {
+            (usartCbTable[3].cbFunc)(usartCbTable[3].userPtr);
+        }
+    }
 }
 #endif
 
 #if (defined(USART_PRESENT) && (USART_COUNT > 2))
 /***************************************************************************//**
  * @brief
- * 	Common USART2 TX interrupt handler
+ *  Common USART2 TX interrupt handler
  *
  * @details
- * 	This function handles USART2 TX complete interrupt request
+ *  This function handles USART2 TX complete interrupt request
  *
  * @note
  *
@@ -579,17 +579,17 @@ void USART2_TX_IRQHandler(void)
     /* enter interrupt */
     rt_interrupt_enter();
 
-	if (USART2->IF & USART_IF_TXC)
-	{
-		/* invoke callback function */
-		if (usartCbTable[4].cbFunc != RT_NULL)
-		{
-			(usartCbTable[4].cbFunc)(usartCbTable[4].userPtr);
-		}
+    if (USART2->IF & USART_IF_TXC)
+    {
+        /* invoke callback function */
+        if (usartCbTable[4].cbFunc != RT_NULL)
+        {
+            (usartCbTable[4].cbFunc)(usartCbTable[4].userPtr);
+        }
 
-		/* clear interrupt */
-		BITBAND_Peripheral(&(USART2->IFC), _USART_IF_TXC_SHIFT, 0x1UL);
-	}
+        /* clear interrupt */
+        BITBAND_Peripheral(&(USART2->IFC), _USART_IF_TXC_SHIFT, 0x1UL);
+    }
 
     /* leave interrupt */
     rt_interrupt_leave();
@@ -597,34 +597,34 @@ void USART2_TX_IRQHandler(void)
 
 /***************************************************************************//**
  * @brief
- * 	Common USART2 RX interrupt handler
+ *  Common USART2 RX interrupt handler
  *
  * @details
- * 	This function handles USART2 RX data valid interrupt request
+ *  This function handles USART2 RX data valid interrupt request
  *
  * @note
  *
  ******************************************************************************/
 void USART2_RX_IRQHandler(void)
 {
-	if (USART2->IF & USART_IF_RXDATAV)
-	{
-		/* invoke callback function */
-		if (usartCbTable[5].cbFunc != RT_NULL)
-		{
-			(usartCbTable[5].cbFunc)(usartCbTable[5].userPtr);
-		}
-	}
+    if (USART2->IF & USART_IF_RXDATAV)
+    {
+        /* invoke callback function */
+        if (usartCbTable[5].cbFunc != RT_NULL)
+        {
+            (usartCbTable[5].cbFunc)(usartCbTable[5].userPtr);
+        }
+    }
 }
 #endif
 
 #if defined(UART_PRESENT)
 /***************************************************************************//**
  * @brief
- * 	Common UART0 TX interrupt handler
+ *  Common UART0 TX interrupt handler
  *
  * @details
- * 	This function handles UART0 TX complete interrupt request
+ *  This function handles UART0 TX complete interrupt request
  *
  * @note
  *
@@ -634,17 +634,17 @@ void UART0_TX_IRQHandler(void)
     /* enter interrupt */
     rt_interrupt_enter();
 
-	if (UART0->IF & UART_IF_TXC)
-	{
-		/* invoke callback function */
-		if (usartCbTable[USART_COUNT * 2].cbFunc != RT_NULL)
-		{
-			(usartCbTable[USART_COUNT * 2].cbFunc)(usartCbTable[USART_COUNT * 2].userPtr);
-		}
+    if (UART0->IF & UART_IF_TXC)
+    {
+        /* invoke callback function */
+        if (usartCbTable[USART_COUNT * 2].cbFunc != RT_NULL)
+        {
+            (usartCbTable[USART_COUNT * 2].cbFunc)(usartCbTable[USART_COUNT * 2].userPtr);
+        }
 
-		/* clear interrupt */
-		BITBAND_Peripheral(&(UART0->IFC), _UART_IF_TXC_SHIFT, 0x1UL);
-	}
+        /* clear interrupt */
+        BITBAND_Peripheral(&(UART0->IFC), _UART_IF_TXC_SHIFT, 0x1UL);
+    }
 
     /* leave interrupt */
     rt_interrupt_leave();
@@ -652,34 +652,34 @@ void UART0_TX_IRQHandler(void)
 
 /***************************************************************************//**
  * @brief
- * 	Common UART0 RX interrupt handler
+ *  Common UART0 RX interrupt handler
  *
  * @details
- * 	This function handles UART0 RX data valid interrupt request
+ *  This function handles UART0 RX data valid interrupt request
  *
  * @note
  *
  ******************************************************************************/
 void UART0_RX_IRQHandler(void)
 {
-	if (UART0->IF & UART_IF_RXDATAV)
-	{
-		/* invoke callback function */
-		if (usartCbTable[USART_COUNT * 2 + 1].cbFunc != RT_NULL)
-		{
-			(usartCbTable[USART_COUNT * 2 + 1].cbFunc)(usartCbTable[USART_COUNT * 2 + 1].userPtr);
-		}
-	}
+    if (UART0->IF & UART_IF_RXDATAV)
+    {
+        /* invoke callback function */
+        if (usartCbTable[USART_COUNT * 2 + 1].cbFunc != RT_NULL)
+        {
+            (usartCbTable[USART_COUNT * 2 + 1].cbFunc)(usartCbTable[USART_COUNT * 2 + 1].userPtr);
+        }
+    }
 }
 #endif
 
 #if (defined(UART_PRESENT) && (UART_COUNT > 1))
 /***************************************************************************//**
  * @brief
- * 	Common UART1 TX interrupt handler
+ *  Common UART1 TX interrupt handler
  *
  * @details
- * 	This function handles UART1 TX complete interrupt request
+ *  This function handles UART1 TX complete interrupt request
  *
  * @note
  *
@@ -689,17 +689,17 @@ void UART1_TX_IRQHandler(void)
     /* enter interrupt */
     rt_interrupt_enter();
 
-	if (UART1->IF & UART_IF_TXC)
-	{
-		/* invoke callback function */
-		if (usartCbTable[USART_COUNT * 2 + 2].cbFunc != RT_NULL)
-		{
-			(usartCbTable[USART_COUNT * 2 + 2].cbFunc)(usartCbTable[USART_COUNT * 2 + 2].userPtr);
-		}
+    if (UART1->IF & UART_IF_TXC)
+    {
+        /* invoke callback function */
+        if (usartCbTable[USART_COUNT * 2 + 2].cbFunc != RT_NULL)
+        {
+            (usartCbTable[USART_COUNT * 2 + 2].cbFunc)(usartCbTable[USART_COUNT * 2 + 2].userPtr);
+        }
 
-		/* clear interrupt */
-		BITBAND_Peripheral(&(UART1->IFC), _UART_IF_TXC_SHIFT, 0x1UL);
-	}
+        /* clear interrupt */
+        BITBAND_Peripheral(&(UART1->IFC), _UART_IF_TXC_SHIFT, 0x1UL);
+    }
 
     /* leave interrupt */
     rt_interrupt_leave();
@@ -707,106 +707,106 @@ void UART1_TX_IRQHandler(void)
 
 /***************************************************************************//**
  * @brief
- * 	Common UART1 RX interrupt handler
+ *  Common UART1 RX interrupt handler
  *
  * @details
- * 	This function handles UART1 RX data valid interrupt request
+ *  This function handles UART1 RX data valid interrupt request
  *
  * @note
  *
  ******************************************************************************/
 void UART1_RX_IRQHandler(void)
 {
-	if (UART1->IF & UART_IF_RXDATAV)
-	{
-		/* invoke callback function */
-		if (usartCbTable[USART_COUNT * 2 + 3].cbFunc != RT_NULL)
-		{
-			(usartCbTable[USART_COUNT * 2 + 3].cbFunc)(usartCbTable[USART_COUNT * 2 + 3].userPtr);
-		}
-	}
+    if (UART1->IF & UART_IF_RXDATAV)
+    {
+        /* invoke callback function */
+        if (usartCbTable[USART_COUNT * 2 + 3].cbFunc != RT_NULL)
+        {
+            (usartCbTable[USART_COUNT * 2 + 3].cbFunc)(usartCbTable[USART_COUNT * 2 + 3].userPtr);
+        }
+    }
 }
 #endif
 
 #if defined(LEUART_PRESENT)
 /***************************************************************************//**
  * @brief
- * 	Common LEUART0 interrupt handler
+ *  Common LEUART0 interrupt handler
  *
  * @details
- * 	This function handles LEUART0 interrupt request
+ *  This function handles LEUART0 interrupt request
  *
  * @note
  *
  ******************************************************************************/
 void LEUART0_IRQHandler(void)
 {
-	if (LEUART0->IF & LEUART_IF_RXDATAV)
-	{
-		/* invoke callback function */
-		if (leuartCbTable[0].cbFunc != RT_NULL)
-		{
-			(leuartCbTable[0].cbFunc)(leuartCbTable[0].userPtr);
-		}
-	}
+    if (LEUART0->IF & LEUART_IF_RXDATAV)
+    {
+        /* invoke callback function */
+        if (leuartCbTable[0].cbFunc != RT_NULL)
+        {
+            (leuartCbTable[0].cbFunc)(leuartCbTable[0].userPtr);
+        }
+    }
 }
 #endif
 
 #if (defined(LEUART_PRESENT) && (LEUART_COUNT > 1))
 /***************************************************************************//**
  * @brief
- * 	Common LEUART1 interrupt handler
+ *  Common LEUART1 interrupt handler
  *
  * @details
- * 	This function handles LEUART1 interrupt request
+ *  This function handles LEUART1 interrupt request
  *
  * @note
  *
  ******************************************************************************/
 void LEUART1_IRQHandler(void)
 {
-	if (LEUART1->IF & LEUART_IF_RXDATAV)
-	{
-		/* invoke callback function */
-		if (leuartCbTable[1].cbFunc != RT_NULL)
-		{
-			(leuartCbTable[1].cbFunc)(leuartCbTable[1].userPtr);
-		}
-	}
+    if (LEUART1->IF & LEUART_IF_RXDATAV)
+    {
+        /* invoke callback function */
+        if (leuartCbTable[1].cbFunc != RT_NULL)
+        {
+            (leuartCbTable[1].cbFunc)(leuartCbTable[1].userPtr);
+        }
+    }
 }
 #endif
 
 #if defined(I2C_PRESENT)
 /***************************************************************************//**
  * @brief
- * 	Common IIC0 interrupt handler
+ *  Common IIC0 interrupt handler
  *
  * @details
- * 	This function handles IIC0 slave mode interrupt requests
+ *  This function handles IIC0 slave mode interrupt requests
  *
  * @note
  *
  ******************************************************************************/
 void I2C0_IRQHandler(void)
 {
-	if ((I2C0->IF & I2C_IF_ADDR) || \
-		(I2C0->IF & I2C_IF_RXDATAV) || \
-		(I2C0->IF & I2C_IF_SSTOP))
-	{
-		/* invoke callback function */
-		if (iicCbTable[0].cbFunc != RT_NULL)
-		{
-			(iicCbTable[0].cbFunc)(iicCbTable[0].userPtr);
-		}
-	}
+    if ((I2C0->IF & I2C_IF_ADDR) || \
+        (I2C0->IF & I2C_IF_RXDATAV) || \
+        (I2C0->IF & I2C_IF_SSTOP))
+    {
+        /* invoke callback function */
+        if (iicCbTable[0].cbFunc != RT_NULL)
+        {
+            (iicCbTable[0].cbFunc)(iicCbTable[0].userPtr);
+        }
+    }
 
-	I2C_IntClear(I2C0, I2C_IFC_ADDR | I2C_IFC_SSTOP);
+    I2C_IntClear(I2C0, I2C_IFC_ADDR | I2C_IFC_SSTOP);
 }
 #endif
 
 /***************************************************************************//**
  * @brief
- * 	EFM32 common interrupt handlers register function
+ *  EFM32 common interrupt handlers register function
  *
  * @details
  *
@@ -815,42 +815,42 @@ void I2C0_IRQHandler(void)
  ******************************************************************************/
 void efm32_irq_hook_register(efm32_irq_hook_init_t *hook)
 {
-	switch (hook->type)
-	{
-	case efm32_irq_type_dma:
-		dmaCbTable[hook->unit].cbFunc = hook->cbFunc;
-		dmaCbTable[hook->unit].userPtr = hook->userPtr;
-		break;
+    switch (hook->type)
+    {
+    case efm32_irq_type_dma:
+        dmaCbTable[hook->unit].cbFunc = hook->cbFunc;
+        dmaCbTable[hook->unit].userPtr = hook->userPtr;
+        break;
 
-	case efm32_irq_type_rtc:
-		rtcCbTable[hook->unit].cbFunc = hook->cbFunc;
-		rtcCbTable[hook->unit].userPtr = hook->userPtr;
-		break;
+    case efm32_irq_type_rtc:
+        rtcCbTable[hook->unit].cbFunc = hook->cbFunc;
+        rtcCbTable[hook->unit].userPtr = hook->userPtr;
+        break;
 
-	case efm32_irq_type_timer:
-		timerCbTable[hook->unit].cbFunc = hook->cbFunc;
-		timerCbTable[hook->unit].userPtr = hook->userPtr;
-		break;
+    case efm32_irq_type_timer:
+        timerCbTable[hook->unit].cbFunc = hook->cbFunc;
+        timerCbTable[hook->unit].userPtr = hook->userPtr;
+        break;
 
-	case efm32_irq_type_letimer:
-		letimerCbTable[hook->unit].cbFunc = hook->cbFunc;
-		letimerCbTable[hook->unit].userPtr = hook->userPtr;
-		break;
+    case efm32_irq_type_letimer:
+        letimerCbTable[hook->unit].cbFunc = hook->cbFunc;
+        letimerCbTable[hook->unit].userPtr = hook->userPtr;
+        break;
 
-	case efm32_irq_type_gpio:
-		gpioCbTable[hook->unit].cbFunc = hook->cbFunc;
-		gpioCbTable[hook->unit].userPtr = hook->userPtr;
-		break;
+    case efm32_irq_type_gpio:
+        gpioCbTable[hook->unit].cbFunc = hook->cbFunc;
+        gpioCbTable[hook->unit].userPtr = hook->userPtr;
+        break;
 
-	case efm32_irq_type_acmp:
-		acmpCbTable[hook->unit].cbFunc = hook->cbFunc;
-		acmpCbTable[hook->unit].userPtr = hook->userPtr;
-		break;
+    case efm32_irq_type_acmp:
+        acmpCbTable[hook->unit].cbFunc = hook->cbFunc;
+        acmpCbTable[hook->unit].userPtr = hook->userPtr;
+        break;
 #if defined(USART_PRESENT)
-	case efm32_irq_type_usart:
-		usartCbTable[hook->unit].cbFunc = hook->cbFunc;
-		usartCbTable[hook->unit].userPtr = hook->userPtr;
-		break;
+    case efm32_irq_type_usart:
+        usartCbTable[hook->unit].cbFunc = hook->cbFunc;
+        usartCbTable[hook->unit].userPtr = hook->userPtr;
+        break;
 #endif
 #if defined(LEUART_PRESENT)
     case efm32_irq_type_leuart:
@@ -859,17 +859,17 @@ void efm32_irq_hook_register(efm32_irq_hook_init_t *hook)
         break;
 #endif
 #if defined(I2C_PRESENT)
-	case efm32_irq_type_iic:
-		iicCbTable[hook->unit].cbFunc = hook->cbFunc;
-		iicCbTable[hook->unit].userPtr = hook->userPtr;
-		break;
+    case efm32_irq_type_iic:
+        iicCbTable[hook->unit].cbFunc = hook->cbFunc;
+        iicCbTable[hook->unit].userPtr = hook->userPtr;
+        break;
 #endif
-	default:
-		break;
-	}
+    default:
+        break;
+    }
 
-	hdl_debug("Hook Registered: type: %s, unit: %x, cbFunc: %x, userPtr: %x\n", \
-		hook->type, hook->unit, hook->cbFunc, hook->userPtr);
+    hdl_debug("Hook Registered: type: %s, unit: %x, cbFunc: %x, userPtr: %x\n", \
+        hook->type, hook->unit, hook->cbFunc, hook->userPtr);
 }
 
 /***************************************************************************//**
diff --git a/bsp/efm32/hdl_interrupt.h b/bsp/efm32/hdl_interrupt.h
index 01f7adf9f8..d2f73bda57 100644
--- a/bsp/efm32/hdl_interrupt.h
+++ b/bsp/efm32/hdl_interrupt.h
@@ -21,31 +21,31 @@
 /* Exported types ------------------------------------------------------------*/
 enum efm32_irq_hook_type_t
 {
-	efm32_irq_type_dma = 0,
-	efm32_irq_type_rtc,
-	efm32_irq_type_timer,
+    efm32_irq_type_dma = 0,
+    efm32_irq_type_rtc,
+    efm32_irq_type_timer,
     efm32_irq_type_letimer,
-	efm32_irq_type_gpio,
-	efm32_irq_type_acmp,
-	efm32_irq_type_usart,
-	efm32_irq_type_leuart,
-	efm32_irq_type_iic
+    efm32_irq_type_gpio,
+    efm32_irq_type_acmp,
+    efm32_irq_type_usart,
+    efm32_irq_type_leuart,
+    efm32_irq_type_iic
 };
 
 typedef void (*efm32_irq_callback_t)(rt_device_t device);
 
 typedef struct
 {
-	enum efm32_irq_hook_type_t type;
-	rt_uint8_t unit;
-	efm32_irq_callback_t cbFunc;
-	void *userPtr;
+    enum efm32_irq_hook_type_t type;
+    rt_uint8_t unit;
+    efm32_irq_callback_t cbFunc;
+    void *userPtr;
 } efm32_irq_hook_init_t;
 
 typedef struct
 {
-	efm32_irq_callback_t cbFunc;
-	void *userPtr;
+    efm32_irq_callback_t cbFunc;
+    void *userPtr;
 } efm32_irq_hook_t;
 
 /* Exported constants --------------------------------------------------------*/
diff --git a/bsp/efm32/httpd.c b/bsp/efm32/httpd.c
index c7094d509a..02c81be84d 100644
--- a/bsp/efm32/httpd.c
+++ b/bsp/efm32/httpd.c
@@ -1,8 +1,8 @@
 /***************************************************************************//**
- * @file 	httpd.c
- * @brief 	Simple http server demo application
+ * @file    httpd.c
+ * @brief   Simple http server demo application
  *  COPYRIGHT (C) 2012, RT-Thread Development Team
- * @author 	onelife
+ * @author  onelife
  * @version 1.0
  *******************************************************************************
  * @section License
@@ -10,8 +10,8 @@
  * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
  *******************************************************************************
  * @section Change Logs
- * Date			Author		Notes
- * 2011-07-04	onelife		Derive from Energy Micro demo application
+ * Date         Author      Notes
+ * 2011-07-04   onelife     Derive from Energy Micro demo application
  ******************************************************************************/
 
 /**************************************************************************//**
@@ -94,29 +94,29 @@
 static int temp, vdd;
 static char indexdata[700];
 static const char indexdata1[] =
-	"HTTP/1.0 200 OK\r\n\
-	Content-type: text/html\r\n\
-	Pragma: no-cache\r\n\
-	Refresh: 5\r\n\
-	\r\n\
-	\
-	EFM32 HTTPD DEMO\
-	\
-	
This is a simple http server
\
-	

Ethernet controller: ENC28J60\
-	

Refreshing timers: ";
+    "HTTP/1.0 200 OK\r\n\
+    Content-type: text/html\r\n\
+    Pragma: no-cache\r\n\
+    Refresh: 5\r\n\
+    \r\n\
+    \
+    EFM32 HTTPD DEMO\
+    \
+    
This is a simple http server
\
+    

Ethernet controller: ENC28J60\
+    

Refreshing timers: ";
 
 static const char indexdata2[] =
-	"

Current Vdd: ";
+    "

Current Vdd: ";
 
 static const char indexdata3[] =
-	" V\
-	

Current temperature: ";
+    " V\
+    

Current temperature: ";
 
 static const char indexdata4[] =
-	" C\
-	\
-	";
+    " C\
+    \
+    ";
 
 /* Private function prototypes -----------------------------------------------*/
 /* Private functions ---------------------------------------------------------*/
@@ -169,9 +169,9 @@ static err_t http_recv(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err
         counter++;
       }
 
-	  vdd = rt_hw_get_vdd();
-	  rt_sprintf(&indexdata[counter], "%1d.%02d", vdd / 100, vdd % 100);
-	  counter += 4;
+      vdd = rt_hw_get_vdd();
+      rt_sprintf(&indexdata[counter], "%1d.%02d", vdd / 100, vdd % 100);
+      counter += 4;
 
       for (i = 0; i < sizeof(indexdata3) - 1; i++)
       {
@@ -179,15 +179,15 @@ static err_t http_recv(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err
         counter++;
       }
 
-	  temp = rt_hw_get_temp();
+      temp = rt_hw_get_temp();
       /*Set temperature sign*/
       if (temp < 0)
       {
         indexdata[counter] = '-';
         counter++;
       }
-	  rt_sprintf(&indexdata[counter], "%02d.%02d\n", temp / 100, temp % 100);
-	  counter += 5;
+      rt_sprintf(&indexdata[counter], "%02d.%02d\n", temp / 100, temp % 100);
+      counter += 5;
 
       for (i = 0; i < sizeof(indexdata4); i++)
       {
diff --git a/bsp/efm32/mma7455l.h b/bsp/efm32/mma7455l.h
index 2ea2cdf34e..c746fd45da 100644
--- a/bsp/efm32/mma7455l.h
+++ b/bsp/efm32/mma7455l.h
@@ -1,9 +1,9 @@
 /***************************************************************************//**
- * @file 	mma7455l.c
- * @brief 	Header file of Freescale MMA7455L 3 axis Low-g digital output
+ * @file    mma7455l.c
+ * @brief   Header file of Freescale MMA7455L 3 axis Low-g digital output
  *  accelerometer
  *  COPYRIGHT (C) 2012, RT-Thread Development Team
- * @author 	onelife
+ * @author  onelife
  * @version 1.0
  *******************************************************************************
  * @section License
@@ -11,101 +11,101 @@
  * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
  *******************************************************************************
  * @section Change Logs
- * Date			Author		Notes
- * 2011-08-02	onelife		Initial creation
+ * Date         Author      Notes
+ * 2011-08-02   onelife     Initial creation
  ******************************************************************************/
 #ifndef __MMA7455L_H__
 #define __MMA7455L_H__
 
-#define XOUTL 		0x00 	//00  10 bits output value X LSB (Read only)
-#define XOUTH 		0x01 	//01  10 bits output value X MSB (Read only)
-#define YOUTL 		0x02 	//02  10 bits output value Y LSB (Read only)
-#define YOUTH 		0x03 	//03  10 bits output value Y MSB (Read only)
-#define ZOUTL 		0x04 	//04  10 bits output value Z LSB (Read only)
-#define ZOUTH 		0x05 	//05  10 bits output value Z MSB (Read only)
-#define XOUT8 		0x06 	//06   8 bits Output value X (Read only)
-#define YOUT8 		0x07 	//07   8 bits Output value Y (Read only)
-#define ZOUT8 		0x08 	//08   8 bits Output value Z (Read only)
-#define STATUS 		0x09 	//09  Status registers (Read only)
-#define DETSRC 		0x0A 	//10  Detection source registers (Read only)
-#define TOUT 		0x0B 	//11  Temperature output value (Optional)
-#define RESERVED1 	0x0C 	//12  Reserved
-#define I2CAD 		0x0D 	//13  I2C device address (Bit[6:0]: Read only, Bit[7]: Read/Write)
-#define USRINF 		0x0E 	//14  User information  (Optional, Read only)
-#define WHOAMI 		0x0F 	//15  Who am I value (Optional, Read only)
-#define XOFFL 		0x10 	//16  Offset drift X value (LSB) (Read/Write)
-#define XOFFH 		0x11 	//17  Offset drift X value (MSB) (Read/Write)
-#define YOFFL 		0x12 	//18  Offset drift Y value (LSB) (Read/Write)
-#define YOFFH 		0x13 	//19  Offset drift Y value (MSB) (Read/Write)
-#define ZOFFL 		0x14 	//20  Offset drift Z value (LSB) (Read/Write)
-#define ZOFFH 		0x15 	//21  Offset drift Z value (MSB) (Read/Write)
-#define MCTL  		0x16 	//22  Mode control (Read/Write)
-#define INTRST 		0x17 	//23  Interrupt latch reset (Read/Write)
-#define CTL1 		0x18 	//24  Control 1 (Read/Write)
-#define CTL2 		0x19 	//25  Control 2 (Read/Write)
-#define LDTH 		0x1A 	//26  Level detection threshold limit value (Read/Write)
-#define PDTH 		0x1B 	//27  Pulse detection threshold limit value (Read/Write)
-#define PW 			0x1C 	//28  Pulse duration value (Read/Write)
-#define LT 			0x1D 	//29  Latency time value  (Read/Write)
-#define TW 			0x1E 	//30  Time window for second pulse value(Read/Write)
-#define RESERVED2 	0x1F 	//31 Reserved
+#define XOUTL       0x00    //00  10 bits output value X LSB (Read only)
+#define XOUTH       0x01    //01  10 bits output value X MSB (Read only)
+#define YOUTL       0x02    //02  10 bits output value Y LSB (Read only)
+#define YOUTH       0x03    //03  10 bits output value Y MSB (Read only)
+#define ZOUTL       0x04    //04  10 bits output value Z LSB (Read only)
+#define ZOUTH       0x05    //05  10 bits output value Z MSB (Read only)
+#define XOUT8       0x06    //06   8 bits Output value X (Read only)
+#define YOUT8       0x07    //07   8 bits Output value Y (Read only)
+#define ZOUT8       0x08    //08   8 bits Output value Z (Read only)
+#define STATUS      0x09    //09  Status registers (Read only)
+#define DETSRC      0x0A    //10  Detection source registers (Read only)
+#define TOUT        0x0B    //11  Temperature output value (Optional)
+#define RESERVED1   0x0C    //12  Reserved
+#define I2CAD       0x0D    //13  I2C device address (Bit[6:0]: Read only, Bit[7]: Read/Write)
+#define USRINF      0x0E    //14  User information  (Optional, Read only)
+#define WHOAMI      0x0F    //15  Who am I value (Optional, Read only)
+#define XOFFL       0x10    //16  Offset drift X value (LSB) (Read/Write)
+#define XOFFH       0x11    //17  Offset drift X value (MSB) (Read/Write)
+#define YOFFL       0x12    //18  Offset drift Y value (LSB) (Read/Write)
+#define YOFFH       0x13    //19  Offset drift Y value (MSB) (Read/Write)
+#define ZOFFL       0x14    //20  Offset drift Z value (LSB) (Read/Write)
+#define ZOFFH       0x15    //21  Offset drift Z value (MSB) (Read/Write)
+#define MCTL        0x16    //22  Mode control (Read/Write)
+#define INTRST      0x17    //23  Interrupt latch reset (Read/Write)
+#define CTL1        0x18    //24  Control 1 (Read/Write)
+#define CTL2        0x19    //25  Control 2 (Read/Write)
+#define LDTH        0x1A    //26  Level detection threshold limit value (Read/Write)
+#define PDTH        0x1B    //27  Pulse detection threshold limit value (Read/Write)
+#define PW          0x1C    //28  Pulse duration value (Read/Write)
+#define LT          0x1D    //29  Latency time value  (Read/Write)
+#define TW          0x1E    //30  Time window for second pulse value(Read/Write)
+#define RESERVED2   0x1F    //31 Reserved
 
 /* For DETSRC */
-#define DETSRC_INT_1		 		(0x01 << 0)
-#define DETSRC_INT_2		 		(0x01 << 1)
-#define DETSRC_PULSE_Z		 		(0x01 << 2)
-#define DETSRC_PULSE_Y		 		(0x01 << 3)
-#define DETSRC_PULSE_X		 		(0x01 << 4)
-#define DETSRC_LEVEL_Z		 		(0x01 << 5)
-#define DETSRC_LEVEL_Y		 		(0x01 << 6)
-#define DETSRC_LEVEL_X		 		(0x01 << 7)
+#define DETSRC_INT_1                (0x01 << 0)
+#define DETSRC_INT_2                (0x01 << 1)
+#define DETSRC_PULSE_Z              (0x01 << 2)
+#define DETSRC_PULSE_Y              (0x01 << 3)
+#define DETSRC_PULSE_X              (0x01 << 4)
+#define DETSRC_LEVEL_Z              (0x01 << 5)
+#define DETSRC_LEVEL_Y              (0x01 << 6)
+#define DETSRC_LEVEL_X              (0x01 << 7)
 
 /* For MCTL */
-#define MCTL_SHIFT_MODE 			(0)
-#define MCTL_SHIFT_G 				(2)
-#define MCTL_MASK_MODE 				(0x03)
-#define MCTL_MASK_G 				(0x0c)
-#define MCTL_MODE_STANDBY 			(0x00 << MCTL_SHIFT_MODE)
-#define MCTL_MODE_MEASUREMENT 		(0x01 << MCTL_SHIFT_MODE)
-#define MCTL_MODE_LEVEL 			(0x02 << MCTL_SHIFT_MODE)
-#define MCTL_MODE_PULSE 			(0x03 << MCTL_SHIFT_MODE)
-#define MCTL_RANGE_8G				(0x00 << MCTL_SHIFT_G)
-#define MCTL_RANGE_4G				(0x02 << MCTL_SHIFT_G)
-#define MCTL_RANGE_2G				(0x01 << MCTL_SHIFT_G)
-#define MCTL_PIN_INT1				(0x01 << 6)
+#define MCTL_SHIFT_MODE             (0)
+#define MCTL_SHIFT_G                (2)
+#define MCTL_MASK_MODE              (0x03)
+#define MCTL_MASK_G                 (0x0c)
+#define MCTL_MODE_STANDBY           (0x00 << MCTL_SHIFT_MODE)
+#define MCTL_MODE_MEASUREMENT       (0x01 << MCTL_SHIFT_MODE)
+#define MCTL_MODE_LEVEL             (0x02 << MCTL_SHIFT_MODE)
+#define MCTL_MODE_PULSE             (0x03 << MCTL_SHIFT_MODE)
+#define MCTL_RANGE_8G               (0x00 << MCTL_SHIFT_G)
+#define MCTL_RANGE_4G               (0x02 << MCTL_SHIFT_G)
+#define MCTL_RANGE_2G               (0x01 << MCTL_SHIFT_G)
+#define MCTL_PIN_INT1               (0x01 << 6)
 
 /* For INTRST */
-#define INTRST_INT_1 				(0x01 << 0)
-#define INTRST_INT_2 				(0x01 << 1)
+#define INTRST_INT_1                (0x01 << 0)
+#define INTRST_INT_2                (0x01 << 1)
 
 /* For CTL1 */
-#define CTL1_SHIFT_INTPIN 			(0)
-#define CTL1_SHIFT_INT 				(1)
-#define CTL1_SHIFT_AXES 			(3)
-#define CTL1_SHIFT_THRESHOLD 		(6)
-#define CTL1_SHIFT_BANDWIDTH 		(7)
-#define CTL1_MASK_AXES 				(0x38)
-#define CTL1_INTPIN_INVERSE 		(0x01 << CTL1_SHIFT_INTPIN)
-#define CTL1_INT_LEVEL_PULSE 		(0x00 << CTL1_SHIFT_INT)
-#define CTL1_INT_PULSE_LEVEL 		(0x01 << CTL1_SHIFT_INT)
-#define CTL1_INT_SINGLE_DOUBLE 		(0x02 << CTL1_SHIFT_INT)
-#define CTL1_X_DISABLE 				(0x01 << CTL1_SHIFT_AXES)
-#define CTL1_Y_DISABLE 				(0x02 << CTL1_SHIFT_AXES)
-#define CTL1_Z_DISABLE 				(0x04 << CTL1_SHIFT_AXES)
-#define CTL1_THRESHOLD_ABSOLUTE		(0x00 << CTL1_SHIFT_THRESHOLD)
-#define CTL1_THRESHOLD_INTEGER		(0x01 << CTL1_SHIFT_THRESHOLD)
-#define CTL1_BANDWIDTH_62_5HZ 		(0x00 << CTL1_SHIFT_BANDWIDTH)
-#define CTL1_BANDWIDTH_125HZ 		(0x01 << CTL1_SHIFT_BANDWIDTH)
+#define CTL1_SHIFT_INTPIN           (0)
+#define CTL1_SHIFT_INT              (1)
+#define CTL1_SHIFT_AXES             (3)
+#define CTL1_SHIFT_THRESHOLD        (6)
+#define CTL1_SHIFT_BANDWIDTH        (7)
+#define CTL1_MASK_AXES              (0x38)
+#define CTL1_INTPIN_INVERSE         (0x01 << CTL1_SHIFT_INTPIN)
+#define CTL1_INT_LEVEL_PULSE        (0x00 << CTL1_SHIFT_INT)
+#define CTL1_INT_PULSE_LEVEL        (0x01 << CTL1_SHIFT_INT)
+#define CTL1_INT_SINGLE_DOUBLE      (0x02 << CTL1_SHIFT_INT)
+#define CTL1_X_DISABLE              (0x01 << CTL1_SHIFT_AXES)
+#define CTL1_Y_DISABLE              (0x02 << CTL1_SHIFT_AXES)
+#define CTL1_Z_DISABLE              (0x04 << CTL1_SHIFT_AXES)
+#define CTL1_THRESHOLD_ABSOLUTE     (0x00 << CTL1_SHIFT_THRESHOLD)
+#define CTL1_THRESHOLD_INTEGER      (0x01 << CTL1_SHIFT_THRESHOLD)
+#define CTL1_BANDWIDTH_62_5HZ       (0x00 << CTL1_SHIFT_BANDWIDTH)
+#define CTL1_BANDWIDTH_125HZ        (0x01 << CTL1_SHIFT_BANDWIDTH)
 
 /* For CTL2 */
-#define CTL1_SHIFT_LEVEL			(0)
-#define CTL1_SHIFT_PULSE			(1)
-#define CTL1_SHIFT_DRIVE			(2)
-#define CTL2_LEVEL_OR		 		(0x00 << CTL1_SHIFT_LEVEL)
-#define CTL2_LEVEL_AND		 		(0x01 << CTL1_SHIFT_LEVEL)
-#define CTL2_PULSE_OR		 		(0x00 << CTL1_SHIFT_PULSE)
-#define CTL2_PULSE_AND		 		(0x01 << CTL1_SHIFT_PULSE)
-#define CTL2_DRIVE_STANDARD	 		(0x00 << CTL1_SHIFT_DRIVE)
-#define CTL2_DRIVE_STRONG	 		(0x01 << CTL1_SHIFT_DRIVE)
+#define CTL1_SHIFT_LEVEL            (0)
+#define CTL1_SHIFT_PULSE            (1)
+#define CTL1_SHIFT_DRIVE            (2)
+#define CTL2_LEVEL_OR               (0x00 << CTL1_SHIFT_LEVEL)
+#define CTL2_LEVEL_AND              (0x01 << CTL1_SHIFT_LEVEL)
+#define CTL2_PULSE_OR               (0x00 << CTL1_SHIFT_PULSE)
+#define CTL2_PULSE_AND              (0x01 << CTL1_SHIFT_PULSE)
+#define CTL2_DRIVE_STANDARD         (0x00 << CTL1_SHIFT_DRIVE)
+#define CTL2_DRIVE_STRONG           (0x01 << CTL1_SHIFT_DRIVE)
 
 #endif /* __MMA7455L_H__ */
diff --git a/bsp/efm32/rtconfig.h b/bsp/efm32/rtconfig.h
index 040f07fa02..3f62ec7195 100644
--- a/bsp/efm32/rtconfig.h
+++ b/bsp/efm32/rtconfig.h
@@ -1,7 +1,7 @@
 /***************************************************************************//**
  * @file    rtconfig.h
  * @brief   RT-Thread config file
- * 	COPYRIGHT (C) 2009, RT-Thread Development Team
+ *  COPYRIGHT (C) 2009, RT-Thread Development Team
  * @author
  * @version 1.0
  *******************************************************************************
@@ -22,23 +22,23 @@
 #define EFM32GG_DK3750
 
 /* RT_NAME_MAX */
-#define RT_NAME_MAX					(8)
+#define RT_NAME_MAX                 (8)
 
 /* RT_ALIGN_SIZE */
-#define RT_ALIGN_SIZE				(4)
+#define RT_ALIGN_SIZE               (4)
 
 /* PRIORITY_MAX */
-#define RT_THREAD_PRIORITY_MAX		(32)
+#define RT_THREAD_PRIORITY_MAX      (32)
 
 /* Tick per Second */
-#define RT_TICK_PER_SECOND			(100)
+#define RT_TICK_PER_SECOND          (100)
 
 /* SECTION: RT_DEBUG */
 #define RT_DEBUG
 #define RT_DEBUG_COLOR
-//#define RT_DEBUG_MEM 				(1)
-//#define RT_DEBUG_SCHEDULER 			(1)
-//#define RT_DEBUG_IPC 				(1)
+//#define RT_DEBUG_MEM              (1)
+//#define RT_DEBUG_SCHEDULER            (1)
+//#define RT_DEBUG_IPC              (1)
 //#define THREAD_DEBUG
 //#define IRQ_DEBUG
 #define RT_USING_OVERFLOW_CHECK
@@ -69,9 +69,9 @@
 
 /* Using Software Timer */
 /* #define RT_USING_TIMER_SOFT */
-#define RT_TIMER_THREAD_PRIO		(4)
-#define RT_TIMER_THREAD_STACK_SIZE	(512)
-#define RT_TIMER_TICK_PER_SECOND	(10)
+#define RT_TIMER_THREAD_PRIO        (4)
+#define RT_TIMER_THREAD_STACK_SIZE  (512)
+#define RT_TIMER_TICK_PER_SECOND    (10)
 
 /* SECTION: IPC */
 /* Using Semaphore*/
@@ -134,10 +134,10 @@
 #define EFM32_SPI_CLK_MODE(mode)    (mode << 3) /* clock mode */
 
 #if defined(EFM32_G8XX_STK)
-//#define RT_USING_USART0				(0x0UL)
-//#define RT_USART0_SYNC_MODE			(EFM32_SPI_MASTER)
-//#define RT_USART0_NAME				"spi0"
-//#define RT_USART0_USING_DMA			(0x1UL)
+//#define RT_USING_USART0               (0x0UL)
+//#define RT_USART0_SYNC_MODE           (EFM32_SPI_MASTER)
+//#define RT_USART0_NAME                "spi0"
+//#define RT_USART0_USING_DMA           (0x1UL)
 #elif defined(EFM32_GXXX_DK)
 #define RT_USING_USART0             (0x2UL)
 #define RT_USART0_SYNC_MODE         (EFM32_SPI_MASTER | EFM32_SPI_AUTOCS | \
@@ -165,28 +165,28 @@
 #endif
 
 /* SECTION: IIC options */
-//#define RT_USING_IIC0				0x3UL
-#define RT_IIC0_NAME				"iic0"
+//#define RT_USING_IIC0             0x3UL
+#define RT_IIC0_NAME                "iic0"
 
 /* SECTION: ACMP options */
 //#define RT_USING_ACMP0
-#define RT_ACMP0_NAME 				"acmp0"
+#define RT_ACMP0_NAME               "acmp0"
 
 /* SECTION: ADC options */
 #define RT_USING_ADC0
-#define RT_ADC0_NAME 				"adc0"
+#define RT_ADC0_NAME                "adc0"
 #if defined(RT_USING_ADC0)
 #define RT_USING_MISC
 #endif
 
 /* SECTION: TIMER options */
-//#define RT_USING_TIMER2				(0x00) 		/* Continuous mode */
-#define RT_TIMER2_NAME				"tmr2"
+//#define RT_USING_TIMER2               (0x00)      /* Continuous mode */
+#define RT_TIMER2_NAME              "tmr2"
 
 /* SECTION: RTC options */
 #if (defined(EFM32_G8XX_STK) || defined(EFM32_GXXX_DK) || defined(EFM32GG_DK3750))
 #define RT_USING_RTC
-#define RT_RTC_NAME 				"rtc"
+#define RT_RTC_NAME                 "rtc"
 #endif
 
 /* SECTION: Serial options */
@@ -199,9 +199,9 @@
 #define EFM_LEUART1                 (0x21UL)
 
 #if defined(EFM32_G8XX_STK)
-#define RT_CONSOLE_DEVICE			(EFM_USART1)
+#define RT_CONSOLE_DEVICE           (EFM_USART1)
 #elif defined(EFM32_GXXX_DK)
-#define RT_CONSOLE_DEVICE			(EFM_USART1)
+#define RT_CONSOLE_DEVICE           (EFM_USART1)
 #elif defined(EFM32GG_DK3750)
  #if defined(EFM32GG_DK3750_USING_LEUART1)
  #define RT_CONSOLE_DEVICE          (EFM_LEUART1)
@@ -211,14 +211,13 @@
 #endif
 
 /* SECTION: Runtime library */
-// #define RT_USING_NOLIBC
 // #define RT_USING_NEWLIB
 #define RT_LIBC_USING_TIME
 
 /* SECTION: Console options */
 #define RT_USING_CONSOLE
 /* the buffer size of console*/
-#define RT_CONSOLEBUF_SIZE			(128)
+#define RT_CONSOLEBUF_SIZE          (128)
 
 /* SECTION: finsh, a C-Express shell */
 #define RT_USING_FINSH
@@ -227,12 +226,12 @@
 #define FINSH_USING_DESCRIPTION
 
 /* SECTION: Peripheral devices */
-#define EFM32_INTERFACE_ADC 		(0)
-#define EFM32_INTERFACE_IIC 		(1)
-#define EFM32_INTERFACE_SPI 		(2)
+#define EFM32_INTERFACE_ADC         (0)
+#define EFM32_INTERFACE_IIC         (1)
+#define EFM32_INTERFACE_SPI         (2)
 #if (defined(EFM32_GXXX_DK) || defined(EFM32GG_DK3750))
-//#define EFM32_USING_ACCEL 			EFM32_INTERFACE_IIC	/* Three axis accelerometer */
-//#define EFM32_USING_SFLASH 							/* SPI Flash */
+//#define EFM32_USING_ACCEL             EFM32_INTERFACE_IIC /* Three axis accelerometer */
+//#define EFM32_USING_SFLASH                            /* SPI Flash */
 #define EFM32_USING_SPISD                       /* MicroSD card */
 //#define EFM32_USING_ETHERNET                    /* Ethernet controller */
 //#define EFM32_USING_LCD                         /* TFT LCD */
@@ -241,30 +240,30 @@
 
 #if defined(EFM32_USING_ACCEL)
 #if (EFM32_USING_ACCEL == EFM32_INTERFACE_ADC)
-#define ACCEL_USING_DEVICE_NAME 	RT_ADC0_NAME
-#define ACCEL_USING_DMA				(0x3UL) 			/* For multiple channels scan mode */
+#define ACCEL_USING_DEVICE_NAME     RT_ADC0_NAME
+#define ACCEL_USING_DMA             (0x3UL)             /* For multiple channels scan mode */
 #elif (EFM32_USING_ACCEL == EFM32_INTERFACE_IIC)
-#define ACCEL_USING_DEVICE_NAME 	RT_IIC0_NAME
+#define ACCEL_USING_DEVICE_NAME     RT_IIC0_NAME
 #endif
 #endif
 
 #if defined(EFM32_USING_SFLASH)
-#define SFLASH_USING_DEVICE_NAME 	RT_USART0_NAME
+#define SFLASH_USING_DEVICE_NAME    RT_USART0_NAME
 #endif
 
 #if defined(EFM32_USING_SPISD)
-#define SPISD_USING_DEVICE_NAME 	RT_USART0_NAME
-#define SPISD_DEVICE_NAME 			"spiSd"
+#define SPISD_USING_DEVICE_NAME     RT_USART0_NAME
+#define SPISD_DEVICE_NAME           "spiSd"
 #endif
 
 #if defined(EFM32_USING_ETHERNET)
  #if defined(EFM32_GXXX_DK)
- #define ETH_USING_DEVICE_NAME 		RT_USART2_NAME
+ #define ETH_USING_DEVICE_NAME      RT_USART2_NAME
  #elif defined(EFM32GG_DK3750)
- #define ETH_USING_DEVICE_NAME 		RT_USART1_NAME
+ #define ETH_USING_DEVICE_NAME      RT_USART1_NAME
  #endif
-#define ETH_DEVICE_NAME 			"spiEth"
-#define ETH_ADDR_DEFAULT 			{0x00, 0x01, 0x02, 0x03, 0x04, 0x05}
+#define ETH_DEVICE_NAME             "spiEth"
+#define ETH_ADDR_DEFAULT            {0x00, 0x01, 0x02, 0x03, 0x04, 0x05}
 #endif
 
 /* SECTION: device filesystem */
@@ -272,9 +271,9 @@
 #define RT_USING_DFS
 /* the max number of mounted filesystem */
 #define DFS_FILESYSTEMS_MAX         (2)
-/* the max number of opened files 		*/
+/* the max number of opened files       */
 #define DFS_FD_MAX                  (4)
-/* the max number of cached sector 		*/
+/* the max number of cached sector      */
 #define DFS_CACHE_MAX_NUM           (4)
 #endif /* defined(RT_USING_NEWLIB) || defined(EFM32_USING_SPISD) */
 #if defined(EFM32_USING_SPISD)
@@ -289,8 +288,8 @@
 #if defined(EFM32_USING_ETHERNET)
 #define EFM32_USING_ETH_HTTPD
 //#define EFM32_USING_ETH_UTILS
-//#define hostName 					"onelife.dyndns.org"
-//#define userPwdB64 					"dXNlcjpwYXNzd2Q="
+//#define hostName                  "onelife.dyndns.org"
+//#define userPwdB64                    "dXNlcjpwYXNzd2Q="
 
 //#define RT_USING_LWIP
 //#define RT_USING_NETUTILS
@@ -309,37 +308,37 @@
 //#define RT_LWIP_DNS
 
 /* the number of simulatenously active TCP connections*/
-#define RT_LWIP_TCP_PCB_NUM			(2)
+#define RT_LWIP_TCP_PCB_NUM         (2)
 
 /* ip address of target*/
-#define RT_LWIP_IPADDR0				(192)
-#define RT_LWIP_IPADDR1				(168)
-#define RT_LWIP_IPADDR2				(1)
-#define RT_LWIP_IPADDR3				(118)
+#define RT_LWIP_IPADDR0             (192)
+#define RT_LWIP_IPADDR1             (168)
+#define RT_LWIP_IPADDR2             (1)
+#define RT_LWIP_IPADDR3             (118)
 /* gateway address of target*/
-#define RT_LWIP_GWADDR0				(192)
-#define RT_LWIP_GWADDR1				(168)
-#define RT_LWIP_GWADDR2				(1)
-#define RT_LWIP_GWADDR3				(1)
+#define RT_LWIP_GWADDR0             (192)
+#define RT_LWIP_GWADDR1             (168)
+#define RT_LWIP_GWADDR2             (1)
+#define RT_LWIP_GWADDR3             (1)
 /* mask address of target*/
-#define RT_LWIP_MSKADDR0 			(255)
-#define RT_LWIP_MSKADDR1 			(255)
-#define RT_LWIP_MSKADDR2 			(255)
-#define RT_LWIP_MSKADDR3 			(0)
+#define RT_LWIP_MSKADDR0            (255)
+#define RT_LWIP_MSKADDR1            (255)
+#define RT_LWIP_MSKADDR2            (255)
+#define RT_LWIP_MSKADDR3            (0)
 
 /* tcp thread options */
-#define RT_LWIP_TCPTHREAD_PRIORITY	(12)
-#define RT_LWIP_TCPTHREAD_MBOX_SIZE	(4)
-#define RT_LWIP_TCPTHREAD_STACKSIZE	(1024)
+#define RT_LWIP_TCPTHREAD_PRIORITY  (12)
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE (4)
+#define RT_LWIP_TCPTHREAD_STACKSIZE (1024)
 /* ethernet if thread options */
-#define RT_LWIP_ETHTHREAD_PRIORITY 	(15)
-#define RT_LWIP_ETHTHREAD_MBOX_SIZE	(4)
-#define RT_LWIP_ETHTHREAD_STACKSIZE	(512)
+#define RT_LWIP_ETHTHREAD_PRIORITY  (15)
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE (4)
+#define RT_LWIP_ETHTHREAD_STACKSIZE (512)
 #endif /* defined(EFM32_USING_ETHERNET) */
 
 /* SECTION: RTGUI support */
 #if defined(EFM32_USING_LCD)
-#define LCD_USING_DEVICE_NAME 	    RT_USART1_NAME
+#define LCD_USING_DEVICE_NAME       RT_USART1_NAME
 #define LCD_DEVICE_NAME             "lcd"
 /* using RTGUI support */
 // #define RT_USING_RTGUI
diff --git a/bsp/efm32/startup.c b/bsp/efm32/startup.c
index 9a70f1278a..d769bbf99c 100644
--- a/bsp/efm32/startup.c
+++ b/bsp/efm32/startup.c
@@ -10,12 +10,12 @@
  * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
  *******************************************************************************
  * @section Change Logs
- * Date			Author		Notes
+ * Date         Author      Notes
  * 2006-08-31   Bernard     first implementation
  * 2010-12-29   onelife     Modify for EFM32
  * 2011-12-20   onelife     Add RTGUI initialization routine
  * 2012-02-21   onelife     Add energy management initialization routine
- * 2012-05-15	onelife		Modified to compatible with CMSIS v3
+ * 2012-05-15   onelife     Modified to compatible with CMSIS v3
  ******************************************************************************/
 
 /***************************************************************************//**
diff --git a/bsp/fh8620/applications/main.c b/bsp/fh8620/applications/main.c
index fe690504d1..366245b48a 100644
--- a/bsp/fh8620/applications/main.c
+++ b/bsp/fh8620/applications/main.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
@@ -27,18 +27,18 @@
 
 void init_thread(void *parameter)
 {
-	rt_components_init();
+    rt_components_init();
 
-	return ;
+    return ;
 }
 
 int rt_application_init(void)
 {
-	rt_thread_t tid;
+    rt_thread_t tid;
 
-	tid = rt_thread_create("init", init_thread, RT_NULL, 
-		4096, RT_THREAD_PRIORITY_MAX/3, 20);
-	if (tid) rt_thread_startup(tid);
+    tid = rt_thread_create("init", init_thread, RT_NULL,
+        4096, RT_THREAD_PRIORITY_MAX/3, 20);
+    if (tid) rt_thread_startup(tid);
 
-	return 0;
+    return 0;
 }
diff --git a/bsp/fh8620/drivers/acw.c b/bsp/fh8620/drivers/acw.c
index 49e10a3bda..6099ff0aa3 100644
--- a/bsp/fh8620/drivers/acw.c
+++ b/bsp/fh8620/drivers/acw.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
@@ -30,12 +30,12 @@
 #include "dma.h"
 #ifdef RT_USING_FH_ACW
 #if 1
-typedef struct 
+typedef struct
 {
-	unsigned int 			base;
-	void 					*vbase;
-	unsigned int 			size;
-	unsigned int 			align;
+    unsigned int            base;
+    void                    *vbase;
+    unsigned int            size;
+    unsigned int            align;
 }MEM_DESC;
 #define ACW_SELFTEST 0
 int buffer_malloc_withname(MEM_DESC *mem, int size, int align,  char* name);
@@ -222,9 +222,9 @@ void fh_acw_stop_playback(struct fh_audio_cfg *audio_config)
     audio_config->playback.state = stopping;
     writel(0, audio_dev.reg_base + ACW_TXFIFO_CTRL);//tx fifo disable
     if(audio_config->plauback_trans->channel_number != ACW_PLY_DMA_CHAN)
-    	goto free_mem;
+        goto free_mem;
     if(!audio_config->plauback_trans->first_lli)
-    	goto free_channel;
+        goto free_channel;
     audio_config->playback_dma->ops->control(audio_config->playback_dma,RT_DEVICE_CTRL_DMA_CYCLIC_STOP,audio_config->plauback_trans);
     audio_config->playback_dma->ops->control(audio_config->playback_dma,RT_DEVICE_CTRL_DMA_CYCLIC_FREE,audio_config->plauback_trans);
 free_channel:
@@ -259,9 +259,9 @@ void fh_acw_stop_capture(struct fh_audio_cfg *audio_config)
 
     writel(0, audio_dev.reg_base + 8);//rx fifo disable
     if(audio_config->capture_trans->channel_number != ACW_CAP_DMA_CHAN)
-    	goto free_mem;
+        goto free_mem;
     if(!audio_config->capture_trans->first_lli)
-    	goto free_channel;
+        goto free_channel;
     audio_config->capture_dma->ops->control(audio_config->capture_dma,RT_DEVICE_CTRL_DMA_CYCLIC_STOP,audio_config->capture_trans);
 
     audio_config->capture_dma->ops->control(audio_config->capture_dma,RT_DEVICE_CTRL_DMA_CYCLIC_FREE,audio_config->capture_trans);
@@ -286,10 +286,10 @@ void switch_io_type(enum audio_type type, enum io_select io_type)
         {
             rt_kprintf("audio input changed to mic_in\n");
             writel( reg & (~(1<<1)),audio_dev.reg_base + ACW_ADC_PATH_CTRL);
-        	reg = readl(audio_dev.reg_base + ACW_ADC_PATH_CTRL);
-       	    reg = reg & (~(1<<3));
-       	    reg |=(0x1<<3);
-       	    writel(reg, audio_dev.reg_base + ACW_ADC_PATH_CTRL);
+            reg = readl(audio_dev.reg_base + ACW_ADC_PATH_CTRL);
+            reg = reg & (~(1<<3));
+            reg |=(0x1<<3);
+            writel(reg, audio_dev.reg_base + ACW_ADC_PATH_CTRL);
         }
         else if (line_in == io_type)
         {
@@ -397,7 +397,7 @@ void switch_input_volume(int volume)
     param = get_param_from_volume(volume);
     if (param < 0)
     {
-    	rt_kprintf("capture volume error\n");
+        rt_kprintf("capture volume error\n");
         return;
     }
 
@@ -511,25 +511,25 @@ int register_tx_dma(struct fh_audio_cfg  *audio_config)
 
     if(playback_trans->channel_number == ACW_PLY_DMA_CHAN){
 
-    	ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_CYCLIC_PREPARE,playback_trans);
-    	if(ret){
-    		rt_kprintf("can't playback cyclic prepare \n");
-    		return RT_ERROR;
-    	}
-    	ret = 	rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_CYCLIC_START,playback_trans);
-    	if(ret){
-    		rt_kprintf("can't playback cyclic start \n");
-    		return RT_ERROR;
-    	}
+        ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_CYCLIC_PREPARE,playback_trans);
+        if(ret){
+            rt_kprintf("can't playback cyclic prepare \n");
+            return RT_ERROR;
+        }
+        ret =   rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_CYCLIC_START,playback_trans);
+        if(ret){
+            rt_kprintf("can't playback cyclic start \n");
+            return RT_ERROR;
+        }
     }
     else
-    	return RT_ERROR;
+        return RT_ERROR;
     return 0;
 }
 
 int register_rx_dma( struct fh_audio_cfg  *audio_config)
 {
-	int ret;
+    int ret;
     struct dma_transfer *capture_slave;
     capture_slave = audio_config->capture_trans;
     struct rt_dma_device *rt_dma_dev;
@@ -546,19 +546,19 @@ int register_rx_dma( struct fh_audio_cfg  *audio_config)
         return RT_ERROR;
     }
     if(capture_slave->channel_number==ACW_CAP_DMA_CHAN){
-    	ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_CYCLIC_PREPARE,capture_slave);
-    	if(ret){
-    		rt_kprintf("can't capture cyclic prepare \n");
-    		return RT_ERROR;
-    	}
-    	ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_CYCLIC_START,capture_slave);
-    	if(ret){
-    		rt_kprintf("can't capture cyclic start \n");
-    		return RT_ERROR;
-    	}
+        ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_CYCLIC_PREPARE,capture_slave);
+        if(ret){
+            rt_kprintf("can't capture cyclic prepare \n");
+            return RT_ERROR;
+        }
+        ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_CYCLIC_START,capture_slave);
+        if(ret){
+            rt_kprintf("can't capture cyclic start \n");
+            return RT_ERROR;
+        }
     }
     else
-    	return RT_ERROR;
+        return RT_ERROR;
     writel(0x11,audio_dev.reg_base  + ACW_RXFIFO_CTRL);//clear rx fifo
     writel(0x30029,audio_dev.reg_base + ACW_RXFIFO_CTRL);/*enable rx fifo*/
 
@@ -614,13 +614,13 @@ int fh_acw_start_playback(struct fh_audio_cfg *audio_config)
     audio_config->playback.state = running;
     ret =  audio_request_playback_channel(audio_config);
     if(ret){
-    	rt_kprintf("can't request playback channel\n");
-    	return ret;
+        rt_kprintf("can't request playback channel\n");
+        return ret;
     }
     ret = register_tx_dma(audio_config);
     if (ret < 0)
     {
-    	rt_kprintf("can't register tx dma\n");
+        rt_kprintf("can't register tx dma\n");
         return ret;
     }
     rt_list_init(&(playback_wq.list));
@@ -638,7 +638,7 @@ int fh_acw_start_playback(struct fh_audio_cfg *audio_config)
 
 int fh_acw_start_capture(struct fh_audio_cfg *audio_config)
 {
-	int ret;
+    int ret;
     if(audio_config->capture.state == running)
     {
         return 0;
@@ -654,8 +654,8 @@ int fh_acw_start_capture(struct fh_audio_cfg *audio_config)
     audio_config->capture.state = running;
     ret = audio_request_capture_channel(audio_config);
     if(ret){
-    	rt_kprintf("can't request capture channel \n");
-    	return ret;
+        rt_kprintf("can't request capture channel \n");
+        return ret;
     }
 
     return register_rx_dma(audio_config);
@@ -698,12 +698,12 @@ static void fh_acw_tx_dma_done(void *arg)
         audio_config->playback.hw_ptr = audio_config->playback.hw_ptr - audio_config->playback.size;
     }
 
-	int avail = avail_data_len(playback,audio_config);
-	if (avail > audio_config->playback.cfg.period_bytes)
-	{
+    int avail = avail_data_len(playback,audio_config);
+    if (avail > audio_config->playback.cfg.period_bytes)
+    {
 
-		rt_sem_release(&audio_config->sem_playback);
-	}
+        rt_sem_release(&audio_config->sem_playback);
+    }
 
 #endif
 }
@@ -719,12 +719,12 @@ int arg_config_support(struct fh_audio_cfg_arg * cfg)
 
     ret = get_param_from_volume(cfg->volume);
     if (ret < 0) {
-    	rt_kprintf("invalid volume\n");
+        rt_kprintf("invalid volume\n");
         return -EINVAL;
     }
     ret = get_factor_from_table(cfg->rate);
     if (ret < 0) {
-    	rt_kprintf("invalid rate\n");
+        rt_kprintf("invalid rate\n");
         return -EINVAL;
     }
     return 0;
@@ -1084,7 +1084,7 @@ static void fh_audio_interrupt(int irq, void *param)
 void audio_prealloc_dma_buffer(int aiaotype,struct fh_audio_cfg  *audio_config)
 {
 
-	 if(aiaotype == mic_in || aiaotype == line_in){
+     if(aiaotype == mic_in || aiaotype == line_in){
     audio_config->capture.area  = (void *)fh_dma_mem_malloc(audio_config->capture.cfg.buffer_bytes \
             + audio_config->capture.cfg.period_bytes);
 
@@ -1093,8 +1093,8 @@ void audio_prealloc_dma_buffer(int aiaotype,struct fh_audio_cfg  *audio_config)
         rt_kprintf("no enough mem for capture  buffer alloc\n");
         return ;
     }
-	 }
-	 if(aiaotype == speaker_out || aiaotype == line_out){
+     }
+     if(aiaotype == speaker_out || aiaotype == line_out){
     audio_config->playback.area  = (void *)fh_dma_mem_malloc(audio_config->playback.cfg.buffer_bytes \
             + audio_config->playback.cfg.period_bytes);
 
@@ -1169,9 +1169,9 @@ int audio_request_capture_channel(struct fh_audio_cfg  *audio_config){
     rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_OPEN,dma_rx_transfer);
     ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL,dma_rx_transfer);
     if(ret){
-    	rt_kprintf("can't request capture channel\n");
-    	dma_rx_transfer->channel_number =0xff;
-    	return -ret;
+        rt_kprintf("can't request capture channel\n");
+        dma_rx_transfer->channel_number =0xff;
+        return -ret;
     }
 
 }
@@ -1219,9 +1219,9 @@ int audio_request_playback_channel(struct fh_audio_cfg  *audio_config)
     rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_OPEN,dma_tx_transfer);
     ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL,dma_tx_transfer);
     if(ret){
-    	rt_kprintf("can't request playbak channel\n");
-    	dma_tx_transfer->channel_number = 0xff;
-    	return -ret;
+        rt_kprintf("can't request playbak channel\n");
+        dma_tx_transfer->channel_number = 0xff;
+        return -ret;
     }
     return 0;
 
@@ -1320,7 +1320,7 @@ void fh_acw_test(){
     cfg.frame_bit = 16;
 
     cfg.io_type = mic_in;
-    
+
     cfg.period_size = BUFF_SIZE/8;
     cfg.rate = 8000;
     cfg.volume = 80;
@@ -1344,18 +1344,18 @@ void fh_acw_test(){
 
     ret = acw_dev->control(acw_dev,AC_AI_EN,&cfg);
     if(ret)
-    	acw_dev->control(acw_dev,AC_AI_DISABLE,&cfg);
+        acw_dev->control(acw_dev,AC_AI_DISABLE,&cfg);
     cfg.io_type = line_out;
     acw_dev->control(acw_dev,AC_INIT_PLAYBACK_MEM,&cfg);
     ret = acw_dev->control(acw_dev,AC_AO_EN,&cfg);
     if(ret){
-    	acw_dev->control(acw_dev,AC_AO_DISABLE,&cfg);
+        acw_dev->control(acw_dev,AC_AO_DISABLE,&cfg);
    // acw_dev->control(acw_dev,AC_SET_OUTPUT_MODE,&output);
-    	return ;
+        return ;
     }
 
 
-	 for(i=0;i<100;i++)
+     for(i=0;i<100;i++)
  {
 
 rx:
@@ -1374,7 +1374,7 @@ tx:
         acw_dev->write(acw_dev,0,&rx_buff[0],1024*8);
 
     }
- 	acw_dev->close(acw_dev);
+    acw_dev->close(acw_dev);
 
 }
 #ifdef RT_USING_FINSH
diff --git a/bsp/fh8620/drivers/acw.h b/bsp/fh8620/drivers/acw.h
index 2156d343f4..82fce3b9ff 100644
--- a/bsp/fh8620/drivers/acw.h
+++ b/bsp/fh8620/drivers/acw.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #ifndef ACW_H_
 #define ACW_H_
 #include 
@@ -37,86 +37,86 @@
 typedef unsigned long long dma_addr_t;
 struct scatterlist {
 #ifdef CONFIG_DEBUG_SG
-	unsigned long	sg_magic;
+    unsigned long   sg_magic;
 #endif
-	unsigned long	page_link;
-	unsigned int	offset;
-	unsigned int	length;
-	dma_addr_t	dma_address;
+    unsigned long   page_link;
+    unsigned int    offset;
+    unsigned int    length;
+    dma_addr_t  dma_address;
 #ifdef CONFIG_NEED_SG_DMA_LENGTH
-	unsigned int	dma_length;
+    unsigned int    dma_length;
 #endif
 };
 #define readl(a)          (*(volatile rt_uint32_t   *)(a))
-#define rkqueue_struct		rt_workqueue
-#define work_struct				rt_work
-#define INIT_WORK(work,func)	rt_work_init(work,func,RT_NULL);
-#define queue_work				rt_workqueue_dowork
+#define rkqueue_struct      rt_workqueue
+#define work_struct             rt_work
+#define INIT_WORK(work,func)    rt_work_init(work,func,RT_NULL);
+#define queue_work              rt_workqueue_dowork
 
 
 //timer
-#define timer_list				rt_timer
-#define wait_queue_head_t				struct rt_event
-#define init_waitqueue_head(event_t) 		rt_event_init(event_t, "audio_event", RT_IPC_FLAG_FIFO)
+#define timer_list              rt_timer
+#define wait_queue_head_t               struct rt_event
+#define init_waitqueue_head(event_t)        rt_event_init(event_t, "audio_event", RT_IPC_FLAG_FIFO)
 typedef enum{
-	AC_SR_8K   = 8000,
-	AC_SR_16K  = 16000,
-	AC_SR_32K  = 32000,
-	AC_SR_441K = 44100,
-	AC_SR_48K  = 48000,
+    AC_SR_8K   = 8000,
+    AC_SR_16K  = 16000,
+    AC_SR_32K  = 32000,
+    AC_SR_441K = 44100,
+    AC_SR_48K  = 48000,
 } FH_AC_SAMPLE_RATE_E;
 
 typedef enum{
-	AC_BW_8  = 8,
-	AC_BW_16 = 16,
-	AC_BW_24 = 24,
+    AC_BW_8  = 8,
+    AC_BW_16 = 16,
+    AC_BW_24 = 24,
 } FH_AC_BIT_WIDTH_E;
 
 enum io_select{
-	mic_in = 0,
-	line_in = 1,
-	speaker_out = 2,
-	line_out = 3,
+    mic_in = 0,
+    line_in = 1,
+    speaker_out = 2,
+    line_out = 3,
 };
 
 struct fh_audio_cfg_arg{
-	enum io_select io_type;
-	int volume;
-	int rate;
-	int frame_bit;
-	int channels;
-	int buffer_size;
-	int period_size;
+    enum io_select io_type;
+    int volume;
+    int rate;
+    int frame_bit;
+    int channels;
+    int buffer_size;
+    int period_size;
 };
 typedef struct{
-	unsigned int len;
-	unsigned char *data;
+    unsigned int len;
+    unsigned char *data;
 }FH_AC_FRAME_S;
 
 typedef enum{
-	FH_AC_MIC_IN = 0,
-	FH_AC_LINE_IN = 1,
-	FH_AC_SPK_OUT = 2,
-	FH_AC_LINE_OUT = 3
+    FH_AC_MIC_IN = 0,
+    FH_AC_LINE_IN = 1,
+    FH_AC_SPK_OUT = 2,
+    FH_AC_LINE_OUT = 3
 }FH_AC_IO_TYPE_E;
 
 
 typedef struct {
-	FH_AC_IO_TYPE_E io_type;
-	FH_AC_SAMPLE_RATE_E sample_rate;
-	FH_AC_BIT_WIDTH_E bit_width;
-	unsigned int channels;
-	unsigned int period_size;
-	unsigned int volume;
+    FH_AC_IO_TYPE_E io_type;
+    FH_AC_SAMPLE_RATE_E sample_rate;
+    FH_AC_BIT_WIDTH_E bit_width;
+    unsigned int channels;
+    unsigned int period_size;
+    unsigned int volume;
 } FH_AC_CONFIG;
 
 struct device_dma_parameters {
-	/*
-	 * a low level driver may set these to teach IOMMU code about
-	 * sg limitations.
-	 */
-	unsigned int max_segment_size;
-	unsigned long segment_boundary_mask;
+    /*
+     * a low level driver may set these to teach IOMMU code about
+     * sg limitations.
+     */
+    unsigned int max_segment_size;
+    unsigned long segment_boundary_mask;
 };
 
 struct list_head {
@@ -124,32 +124,32 @@ struct list_head {
     struct list_head *prev;
 };
 struct dma_coherent_mem {
-	void		*virt_base;
-	dma_addr_t	device_base;
-	int		size;
-	int		flags;
-	unsigned long	*bitmap;
+    void        *virt_base;
+    dma_addr_t  device_base;
+    int     size;
+    int     flags;
+    unsigned long   *bitmap;
 };
 struct device_acw{
-	unsigned long long		*dma_mask;	/* dma mask (if dma'able device) */
-	unsigned long long		coherent_dma_mask;/* Like dma_mask, but for
-					     alloc_coherent mappings as
-					     not all hardware supports
-					     64 bit addresses for consistent
-					     allocations such descriptors. */
-	struct device_dma_parameters *dma_parms;
+    unsigned long long      *dma_mask;  /* dma mask (if dma'able device) */
+    unsigned long long      coherent_dma_mask;/* Like dma_mask, but for
+                         alloc_coherent mappings as
+                         not all hardware supports
+                         64 bit addresses for consistent
+                         allocations such descriptors. */
+    struct device_dma_parameters *dma_parms;
 
-	struct list_head	dma_pools;
+    struct list_head    dma_pools;
 
-	struct dma_coherent_mem	*dma_mem;
+    struct dma_coherent_mem *dma_mem;
 };
 #define false 0
 #define true  1
 
 
 
-#define	AC_INIT_CAPTURE_MEM    	    0x10
-#define	AC_INIT_PLAYBACK_MEM        0x11
+#define AC_INIT_CAPTURE_MEM         0x10
+#define AC_INIT_PLAYBACK_MEM        0x11
 
 
 #define AC_SET_VOL                  0x12
@@ -160,73 +160,73 @@ struct device_acw{
 #define AC_AI_EN                    0x15
 #define AC_AO_EN                    0x16
 #define AC_AI_DISABLE               0x17
-#define AC_AO_DISABLE       		0x18
-#define AC_AI_PAUSE               	0x19
-#define AC_AI_RESUME          		0x1a
-#define AC_AO_PAUSE              	0x1b
-#define AC_AO_RESUME          		0x1c
-#define AC_MIC_BOOST          		0x1d
+#define AC_AO_DISABLE               0x18
+#define AC_AI_PAUSE                 0x19
+#define AC_AI_RESUME                0x1a
+#define AC_AO_PAUSE                 0x1b
+#define AC_AO_RESUME                0x1c
+#define AC_MIC_BOOST                0x1d
 
-#define POLLIN		0x001		/* There is data to read.  */
-#define POLLPRI		0x002		/* There is urgent data to read.  */
-#define POLLOUT		0x004		/* Writing now will not block.  */
+#define POLLIN      0x001       /* There is data to read.  */
+#define POLLPRI     0x002       /* There is urgent data to read.  */
+#define POLLOUT     0x004       /* Writing now will not block.  */
 
 
 /* These values are defined in XPG4.2.  */
-# define POLLRDNORM	0x040		/* Normal data may be read.  */
-# define POLLRDBAND	0x080		/* Priority data may be read.  */
-# define POLLWRNORM	0x100		/* Writing now will not block.  */
-# define POLLWRBAND	0x200		/* Priority data may be written.  */
+# define POLLRDNORM 0x040       /* Normal data may be read.  */
+# define POLLRDBAND 0x080       /* Priority data may be read.  */
+# define POLLWRNORM 0x100       /* Writing now will not block.  */
+# define POLLWRBAND 0x200       /* Priority data may be written.  */
 
 
 
 /* These are extensions for Linux.  */
-# define POLLMSG	0x400
-# define POLLREMOVE	0x1000
-# define POLLRDHUP	0x2000
+# define POLLMSG    0x400
+# define POLLREMOVE 0x1000
+# define POLLRDHUP  0x2000
 
 
 /* Event types always implicitly polled for.  These bits need not be set in
    `events', but they will appear in `revents' to indicate the status of
    the file descriptor.  */
-#define POLLERR		0x008		/* Error condition.  */
-#define POLLHUP		0x010		/* Hung up.  */
-#define POLLNVAL	0x020		/* Invalid polling request.  */
+#define POLLERR     0x008       /* Error condition.  */
+#define POLLHUP     0x010       /* Hung up.  */
+#define POLLNVAL    0x020       /* Invalid polling request.  */
 
-#define	EPERM		 1	/* Operation not permitted */
-#define	ENOENT		 2	/* No such file or directory */
-#define	ESRCH		 3	/* No such process */
-#define	EINTR		 4	/* Interrupted system call */
-#define	EIO		 5	/* I/O error */
-#define	ENXIO		 6	/* No such device or address */
-#define	E2BIG		 7	/* Argument list too long */
-#define	ENOEXEC		 8	/* Exec format error */
-#define	EBADF		 9	/* Bad file number */
-#define	ECHILD		10	/* No child processes */
-#define	EAGAIN		11	/* Try again */
-#define	ENOMEM		12	/* Out of memory */
-#define	EACCES		13	/* Permission denied */
-#define	EFAULT		14	/* Bad address */
-#define	ENOTBLK		15	/* Block device required */
-#define	EBUSY		16	/* Device or resource busy */
-#define	EEXIST		17	/* File exists */
-#define	EXDEV		18	/* Cross-device link */
-#define	ENODEV		19	/* No such device */
-#define	ENOTDIR		20	/* Not a directory */
-#define	EISDIR		21	/* Is a directory */
-#define	EINVAL		22	/* Invalid argument */
-#define	ENFILE		23	/* File table overflow */
-#define	EMFILE		24	/* Too many open files */
-#define	ENOTTY		25	/* Not a typewriter */
-#define	ETXTBSY		26	/* Text file busy */
-#define	EFBIG		27	/* File too large */
-#define	ENOSPC		28	/* No space left on device */
-#define	ESPIPE		29	/* Illegal seek */
-#define	EROFS		30	/* Read-only file system */
-#define	EMLINK		31	/* Too many links */
-#define	EPIPE		32	/* Broken pipe */
-#define	EDOM		33	/* Math argument out of domain of func */
-#define	ERANGE		34	/* Math result not representable */
+#define EPERM        1  /* Operation not permitted */
+#define ENOENT       2  /* No such file or directory */
+#define ESRCH        3  /* No such process */
+#define EINTR        4  /* Interrupted system call */
+#define EIO      5  /* I/O error */
+#define ENXIO        6  /* No such device or address */
+#define E2BIG        7  /* Argument list too long */
+#define ENOEXEC      8  /* Exec format error */
+#define EBADF        9  /* Bad file number */
+#define ECHILD      10  /* No child processes */
+#define EAGAIN      11  /* Try again */
+#define ENOMEM      12  /* Out of memory */
+#define EACCES      13  /* Permission denied */
+#define EFAULT      14  /* Bad address */
+#define ENOTBLK     15  /* Block device required */
+#define EBUSY       16  /* Device or resource busy */
+#define EEXIST      17  /* File exists */
+#define EXDEV       18  /* Cross-device link */
+#define ENODEV      19  /* No such device */
+#define ENOTDIR     20  /* Not a directory */
+#define EISDIR      21  /* Is a directory */
+#define EINVAL      22  /* Invalid argument */
+#define ENFILE      23  /* File table overflow */
+#define EMFILE      24  /* Too many open files */
+#define ENOTTY      25  /* Not a typewriter */
+#define ETXTBSY     26  /* Text file busy */
+#define EFBIG       27  /* File too large */
+#define ENOSPC      28  /* No space left on device */
+#define ESPIPE      29  /* Illegal seek */
+#define EROFS       30  /* Read-only file system */
+#define EMLINK      31  /* Too many links */
+#define EPIPE       32  /* Broken pipe */
+#define EDOM        33  /* Math argument out of domain of func */
+#define ERANGE      34  /* Math result not representable */
 extern void  fh_audio_init(void);
 extern void fh_acw_test();
 #endif
diff --git a/bsp/fh8620/drivers/dma.c b/bsp/fh8620/drivers/dma.c
index 394ac2a6a3..3105f9261b 100644
--- a/bsp/fh8620/drivers/dma.c
+++ b/bsp/fh8620/drivers/dma.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 /*****************************************************************************
  *  Include Section
  *  add all #include here
@@ -88,7 +88,7 @@ static rt_err_t rt_dma_control(struct rt_device *dev,
  *****************************************************************************/
 static rt_err_t rt_dma_init(struct rt_device *dev)
 {
-	struct rt_dma_device *dma;
+    struct rt_dma_device *dma;
 
     RT_ASSERT(dev != RT_NULL);
     dma = (struct rt_dma_device *)dev;
@@ -107,7 +107,7 @@ static rt_err_t rt_dma_open(struct rt_device *dev, rt_uint16_t oflag)
 
 static rt_err_t rt_dma_close(struct rt_device *dev)
 {
-	struct rt_dma_device *dma;
+    struct rt_dma_device *dma;
 
     RT_ASSERT(dev != RT_NULL);
     dma = (struct rt_dma_device *)dev;
@@ -124,7 +124,7 @@ static rt_err_t rt_dma_control(struct rt_device *dev,
                                     rt_uint8_t        cmd,
                                     void             *args)
 {
-	struct rt_dma_device *dma;
+    struct rt_dma_device *dma;
 
     RT_ASSERT(dev != RT_NULL);
     dma = (struct rt_dma_device *)dev;
@@ -141,7 +141,7 @@ rt_err_t rt_hw_dma_register(struct rt_dma_device *dma,
                                  rt_uint32_t                flag,
                                  void                      *data)
 {
-	rt_uint32_t ret;
+    rt_uint32_t ret;
     struct rt_device *device;
     RT_ASSERT(dma != RT_NULL);
 
diff --git a/bsp/fh8620/drivers/dma.h b/bsp/fh8620/drivers/dma.h
index c8c3fbf574..2ef3253196 100644
--- a/bsp/fh8620/drivers/dma.h
+++ b/bsp/fh8620/drivers/dma.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
@@ -29,31 +29,31 @@
 #include 
 /****************************************************************************
 * #include section
-*	add #include here if any
+*   add #include here if any
 ***************************************************************************/
 
 
 /****************************************************************************
 * #define section
-*	add constant #define here if any
+*   add constant #define here if any
 ***************************************************************************/
-#define RT_DEVICE_CTRL_DMA_OPEN						(1)
-#define RT_DEVICE_CTRL_DMA_CLOSE					(2)
-#define RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL    		(3)
-#define RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL   	 	(4)
-#define RT_DEVICE_CTRL_DMA_SINGLE_TRANSFER			(5)
+#define RT_DEVICE_CTRL_DMA_OPEN                     (1)
+#define RT_DEVICE_CTRL_DMA_CLOSE                    (2)
+#define RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL          (3)
+#define RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL          (4)
+#define RT_DEVICE_CTRL_DMA_SINGLE_TRANSFER          (5)
 
 
 //cyclic add func below....
 
 
-#define RT_DEVICE_CTRL_DMA_CYCLIC_PREPARE			(6)
-#define RT_DEVICE_CTRL_DMA_CYCLIC_START				(7)
-#define RT_DEVICE_CTRL_DMA_CYCLIC_STOP				(8)
-#define RT_DEVICE_CTRL_DMA_CYCLIC_FREE				(9)
+#define RT_DEVICE_CTRL_DMA_CYCLIC_PREPARE           (6)
+#define RT_DEVICE_CTRL_DMA_CYCLIC_START             (7)
+#define RT_DEVICE_CTRL_DMA_CYCLIC_STOP              (8)
+#define RT_DEVICE_CTRL_DMA_CYCLIC_FREE              (9)
 
 
-//#define RT_DEVICE_CTRL_  	 (3) /* get the left time before reboot(in seconds) */
+//#define RT_DEVICE_CTRL_    (3) /* get the left time before reboot(in seconds) */
 //#define RT_DEVICE_CTRL_      (4) /* refresh watchdog */
 //#define RT_DEVICE_CTRL_      (5) /* start watchdog */
 //#define RT_DEVICE_CTRL_      (6) /* stop watchdog */
@@ -64,13 +64,13 @@
 
 /****************************************************************************
 * ADT section
-*	add Abstract Data Type definition here
+*   add Abstract Data Type definition here
 ***************************************************************************/
 
 struct rt_dma_ops;
 struct rt_dma_device
 {
-	// the parent must be the fitst para..
+    // the parent must be the fitst para..
     struct rt_device parent;
     struct rt_dma_ops *ops;
 };
@@ -91,7 +91,7 @@ struct rt_dma_ops
 
 /****************************************************************************
 *  section
-*	add function prototype here if any
+*   add function prototype here if any
 ***************************************************************************/
 rt_err_t rt_hw_dma_register(struct rt_dma_device *dma,
                                  const char    *name,
diff --git a/bsp/fh8620/drivers/dma_mem.c b/bsp/fh8620/drivers/dma_mem.c
index 52c9e56b4a..9360ab5b81 100644
--- a/bsp/fh8620/drivers/dma_mem.c
+++ b/bsp/fh8620/drivers/dma_mem.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 /*****************************************************************************
  *  Include Section
  *  add all #include here
@@ -86,27 +86,27 @@ static struct rt_memheap dma_heap = {0};
  *      what does this function returned?
  *****************************************************************************/
 rt_err_t fh_dma_mem_init(rt_uint32_t *mem_start,rt_uint32_t size){
-	return rt_memheap_init(&dma_heap,"dma_heap",mem_start,size);
+    return rt_memheap_init(&dma_heap,"dma_heap",mem_start,size);
 }
 
 
 void *fh_dma_mem_malloc(rt_uint32_t size){
-	return rt_memheap_alloc(&dma_heap, size);
+    return rt_memheap_alloc(&dma_heap, size);
 }
 
 
 void fh_dma_mem_free(void *ptr){
-	rt_memheap_free(ptr);
+    rt_memheap_free(ptr);
 }
 
 #ifdef FH_TEST_DMA_MEM
 int dma_mem_debug(void *ptr){
-	//rt_memheap_free(ptr);
-	rt_kprintf("dma mem start 0x%08x\n",(rt_uint32_t)dma_heap.start_addr);
-	rt_kprintf("dma mem total size 0x%08x\n",dma_heap.pool_size);
-	rt_kprintf("dma mem left size 0x%08x\n",dma_heap.available_size);
-	rt_kprintf("dma mem max use size 0x%08x\n",dma_heap.max_used_size);
-	return 0;
+    //rt_memheap_free(ptr);
+    rt_kprintf("dma mem start 0x%08x\n",(rt_uint32_t)dma_heap.start_addr);
+    rt_kprintf("dma mem total size 0x%08x\n",dma_heap.pool_size);
+    rt_kprintf("dma mem left size 0x%08x\n",dma_heap.available_size);
+    rt_kprintf("dma mem max use size 0x%08x\n",dma_heap.max_used_size);
+    return 0;
 }
 #endif
 
diff --git a/bsp/fh8620/drivers/dma_mem.h b/bsp/fh8620/drivers/dma_mem.h
index b431703a4a..fea4222432 100644
--- a/bsp/fh8620/drivers/dma_mem.h
+++ b/bsp/fh8620/drivers/dma_mem.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #ifndef DMA_MEM_H_
 #define DMA_MEM_H_
 
@@ -36,20 +36,20 @@
 #include 
 /****************************************************************************
 * #include section
-*	add #include here if any
+*   add #include here if any
 ***************************************************************************/
 
 
 /****************************************************************************
 * #define section
-*	add constant #define here if any
+*   add constant #define here if any
 ***************************************************************************/
 
 
 
 /****************************************************************************
 * ADT section
-*	add Abstract Data Type definition here
+*   add Abstract Data Type definition here
 ***************************************************************************/
 
 
@@ -61,7 +61,7 @@
 
 /****************************************************************************
 *  section
-*	add function prototype here if any
+*   add function prototype here if any
 ***************************************************************************/
 #ifdef RT_USING_DMA_MEM
 rt_err_t fh_dma_mem_init(rt_uint32_t *mem_start,rt_uint32_t size);
diff --git a/bsp/fh8620/drivers/fh_dma.c b/bsp/fh8620/drivers/fh_dma.c
index c50ae1e1df..d44ecf4e1f 100644
--- a/bsp/fh8620/drivers/fh_dma.c
+++ b/bsp/fh8620/drivers/fh_dma.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 /*****************************************************************************
  *  Include Section
  *  add all #include here
@@ -45,187 +45,187 @@
 //#define DMA_DEBUG
 #ifdef DMA_DEBUG
 
-#define FH_DMA_DEBUG(fmt, args...)	    		\
-			rt_kprintf(fmt,##args);
+#define FH_DMA_DEBUG(fmt, args...)              \
+            rt_kprintf(fmt,##args);
 #else
 #define FH_DMA_DEBUG(fmt, args...)
 #endif
 
 
-#define		DMA_REG_BASE		(0xEE000000)
-#define 	DMA_CONTROLLER_NUMBER		(1)
+#define     DMA_REG_BASE        (0xEE000000)
+#define     DMA_CONTROLLER_NUMBER       (1)
 
 
 
-#define WORK_QUEUE_STACK_SIZE		512
-#define WORK_QUEUE_PRIORITY			12
+#define WORK_QUEUE_STACK_SIZE       512
+#define WORK_QUEUE_PRIORITY         12
 
 
-#define TEST_PER_NO			(10)
+#define TEST_PER_NO         (10)
 
-#define DESC_MAX_SIZE			(20)
+#define DESC_MAX_SIZE           (20)
 /*********************************
  *
  * copy from the linux core start
  *
  *********************************/
 //this is the ip reg offset....don't change!!!!!!!
-#define DW_DMA_MAX_NR_CHANNELS	8
+#define DW_DMA_MAX_NR_CHANNELS  8
 
 /*
  * Redefine this macro to handle differences between 32- and 64-bit
  * addressing, big vs. little endian, etc.
  */
-#define DW_REG(name)		rt_uint32_t name; rt_uint32_t __pad_##name
+#define DW_REG(name)        rt_uint32_t name; rt_uint32_t __pad_##name
 
 /* Hardware register definitions. */
 struct dw_dma_chan_regs {
-	DW_REG(SAR);		/* Source Address Register */
-	DW_REG(DAR);		/* Destination Address Register */
-	DW_REG(LLP);		/* Linked List Pointer */
-	rt_uint32_t	CTL_LO;		/* Control Register Low */
-	rt_uint32_t	CTL_HI;		/* Control Register High */
-	DW_REG(SSTAT);
-	DW_REG(DSTAT);
-	DW_REG(SSTATAR);
-	DW_REG(DSTATAR);
-	rt_uint32_t	CFG_LO;		/* Configuration Register Low */
-	rt_uint32_t	CFG_HI;		/* Configuration Register High */
-	DW_REG(SGR);
-	DW_REG(DSR);
+    DW_REG(SAR);        /* Source Address Register */
+    DW_REG(DAR);        /* Destination Address Register */
+    DW_REG(LLP);        /* Linked List Pointer */
+    rt_uint32_t CTL_LO;     /* Control Register Low */
+    rt_uint32_t CTL_HI;     /* Control Register High */
+    DW_REG(SSTAT);
+    DW_REG(DSTAT);
+    DW_REG(SSTATAR);
+    DW_REG(DSTATAR);
+    rt_uint32_t CFG_LO;     /* Configuration Register Low */
+    rt_uint32_t CFG_HI;     /* Configuration Register High */
+    DW_REG(SGR);
+    DW_REG(DSR);
 };
 
 struct dw_dma_irq_regs {
-	DW_REG(XFER);
-	DW_REG(BLOCK);
-	DW_REG(SRC_TRAN);
-	DW_REG(DST_TRAN);
-	DW_REG(ERROR);
+    DW_REG(XFER);
+    DW_REG(BLOCK);
+    DW_REG(SRC_TRAN);
+    DW_REG(DST_TRAN);
+    DW_REG(ERROR);
 };
 
 struct dw_dma_regs {
-	/* per-channel registers */
-	struct dw_dma_chan_regs	CHAN[DW_DMA_MAX_NR_CHANNELS];
+    /* per-channel registers */
+    struct dw_dma_chan_regs CHAN[DW_DMA_MAX_NR_CHANNELS];
 
-	/* irq handling */
-	struct dw_dma_irq_regs	RAW;		/* r */
-	struct dw_dma_irq_regs	STATUS;		/* r (raw & mask) */
-	struct dw_dma_irq_regs	MASK;		/* rw (set = irq enabled) */
-	struct dw_dma_irq_regs	CLEAR;		/* w (ack, affects "raw") */
+    /* irq handling */
+    struct dw_dma_irq_regs  RAW;        /* r */
+    struct dw_dma_irq_regs  STATUS;     /* r (raw & mask) */
+    struct dw_dma_irq_regs  MASK;       /* rw (set = irq enabled) */
+    struct dw_dma_irq_regs  CLEAR;      /* w (ack, affects "raw") */
 
-	DW_REG(STATUS_INT);			/* r */
+    DW_REG(STATUS_INT);         /* r */
 
-	/* software handshaking */
-	DW_REG(REQ_SRC);
-	DW_REG(REQ_DST);
-	DW_REG(SGL_REQ_SRC);
-	DW_REG(SGL_REQ_DST);
-	DW_REG(LAST_SRC);
-	DW_REG(LAST_DST);
+    /* software handshaking */
+    DW_REG(REQ_SRC);
+    DW_REG(REQ_DST);
+    DW_REG(SGL_REQ_SRC);
+    DW_REG(SGL_REQ_DST);
+    DW_REG(LAST_SRC);
+    DW_REG(LAST_DST);
 
-	/* miscellaneous */
-	DW_REG(CFG);
-	DW_REG(CH_EN);
-	DW_REG(ID);
-	DW_REG(TEST);
+    /* miscellaneous */
+    DW_REG(CFG);
+    DW_REG(CH_EN);
+    DW_REG(ID);
+    DW_REG(TEST);
 
-	/* optional encoded params, 0x3c8..0x3 */
+    /* optional encoded params, 0x3c8..0x3 */
 };
 
 
 
 
 /* Bitfields in CTL_LO */
-#define DWC_CTLL_INT_EN			(1 << 0)	/* irqs enabled? */
-#define DWC_CTLL_DST_WIDTH(n)	((n)<<1)	/* bytes per element */
-#define DWC_CTLL_SRC_WIDTH(n)	((n)<<4)
+#define DWC_CTLL_INT_EN         (1 << 0)    /* irqs enabled? */
+#define DWC_CTLL_DST_WIDTH(n)   ((n)<<1)    /* bytes per element */
+#define DWC_CTLL_SRC_WIDTH(n)   ((n)<<4)
 
 #define DWC_CTLL_DST_INC_MODE(n) ((n)<<7)
 
-#define DWC_CTLL_DST_INC		(0<<7)		/* DAR update/not */
-#define DWC_CTLL_DST_DEC		(1<<7)
-#define DWC_CTLL_DST_FIX		(2<<7)
+#define DWC_CTLL_DST_INC        (0<<7)      /* DAR update/not */
+#define DWC_CTLL_DST_DEC        (1<<7)
+#define DWC_CTLL_DST_FIX        (2<<7)
 
 
 #define DWC_CTLL_SRC_INC_MODE(n) ((n)<<9)
 
 
-#define DWC_CTLL_SRC_INC		(0<<9)		/* SAR update/not */
-#define DWC_CTLL_SRC_DEC		(1<<9)
-#define DWC_CTLL_SRC_FIX		(2<<9)
-#define DWC_CTLL_DST_MSIZE(n)	((n)<<11)	/* burst, #elements */
-#define DWC_CTLL_SRC_MSIZE(n)	((n)<<14)
-#define DWC_CTLL_S_GATH_EN		(1 << 17)	/* src gather, !FIX */
-#define DWC_CTLL_D_SCAT_EN		(1 << 18)	/* dst scatter, !FIX */
-#define DWC_CTLL_FC(n)			((n) << 20)
-#define DWC_CTLL_FC_M2M			(0 << 20)	/* mem-to-mem */
-#define DWC_CTLL_FC_M2P			(1 << 20)	/* mem-to-periph */
-#define DWC_CTLL_FC_P2M			(2 << 20)	/* periph-to-mem */
-#define DWC_CTLL_FC_P2P			(3 << 20)	/* periph-to-periph */
+#define DWC_CTLL_SRC_INC        (0<<9)      /* SAR update/not */
+#define DWC_CTLL_SRC_DEC        (1<<9)
+#define DWC_CTLL_SRC_FIX        (2<<9)
+#define DWC_CTLL_DST_MSIZE(n)   ((n)<<11)   /* burst, #elements */
+#define DWC_CTLL_SRC_MSIZE(n)   ((n)<<14)
+#define DWC_CTLL_S_GATH_EN      (1 << 17)   /* src gather, !FIX */
+#define DWC_CTLL_D_SCAT_EN      (1 << 18)   /* dst scatter, !FIX */
+#define DWC_CTLL_FC(n)          ((n) << 20)
+#define DWC_CTLL_FC_M2M         (0 << 20)   /* mem-to-mem */
+#define DWC_CTLL_FC_M2P         (1 << 20)   /* mem-to-periph */
+#define DWC_CTLL_FC_P2M         (2 << 20)   /* periph-to-mem */
+#define DWC_CTLL_FC_P2P         (3 << 20)   /* periph-to-periph */
 /* plus 4 transfer types for peripheral-as-flow-controller */
-#define DWC_CTLL_DMS(n)			((n)<<23)	/* dst master select */
-#define DWC_CTLL_SMS(n)			((n)<<25)	/* src master select */
-#define DWC_CTLL_LLP_D_EN		(1 << 27)	/* dest block chain */
-#define DWC_CTLL_LLP_S_EN		(1 << 28)	/* src block chain */
+#define DWC_CTLL_DMS(n)         ((n)<<23)   /* dst master select */
+#define DWC_CTLL_SMS(n)         ((n)<<25)   /* src master select */
+#define DWC_CTLL_LLP_D_EN       (1 << 27)   /* dest block chain */
+#define DWC_CTLL_LLP_S_EN       (1 << 28)   /* src block chain */
 
 /* Bitfields in CTL_HI */
-#define DWC_CTLH_DONE			0x00001000
-#define DWC_CTLH_BLOCK_TS_MASK	0x00000fff
+#define DWC_CTLH_DONE           0x00001000
+#define DWC_CTLH_BLOCK_TS_MASK  0x00000fff
 
 /* Bitfields in CFG_LO. Platform-configurable bits are in  */
-#define DWC_CFGL_CH_PRIOR_MASK	(0x7 << 5)	/* priority mask */
-#define DWC_CFGL_CH_PRIOR(x)	((x) << 5)	/* priority */
-#define DWC_CFGL_CH_SUSP		(1 << 8)	/* pause xfer */
-#define DWC_CFGL_FIFO_EMPTY		(1 << 9)	/* pause xfer */
+#define DWC_CFGL_CH_PRIOR_MASK  (0x7 << 5)  /* priority mask */
+#define DWC_CFGL_CH_PRIOR(x)    ((x) << 5)  /* priority */
+#define DWC_CFGL_CH_SUSP        (1 << 8)    /* pause xfer */
+#define DWC_CFGL_FIFO_EMPTY     (1 << 9)    /* pause xfer */
 
 
-#define DWC_CFGL_HS_DST			(1 << 10)	/* handshake w/dst */
-#define DWC_CFGL_HS_SRC			(1 << 11)	/* handshake w/src */
-#define DWC_CFGL_MAX_BURST(x)	((x) << 20)
-#define DWC_CFGL_RELOAD_SAR		(1 << 30)
-#define DWC_CFGL_RELOAD_DAR		(1 << 31)
+#define DWC_CFGL_HS_DST         (1 << 10)   /* handshake w/dst */
+#define DWC_CFGL_HS_SRC         (1 << 11)   /* handshake w/src */
+#define DWC_CFGL_MAX_BURST(x)   ((x) << 20)
+#define DWC_CFGL_RELOAD_SAR     (1 << 30)
+#define DWC_CFGL_RELOAD_DAR     (1 << 31)
 
 /* Bitfields in CFG_HI. Platform-configurable bits are in  */
-#define DWC_CFGH_DS_UPD_EN		(1 << 5)
-#define DWC_CFGH_SS_UPD_EN		(1 << 6)
+#define DWC_CFGH_DS_UPD_EN      (1 << 5)
+#define DWC_CFGH_SS_UPD_EN      (1 << 6)
 
 /* Bitfields in SGR */
-#define DWC_SGR_SGI(x)			((x) << 0)
-#define DWC_SGR_SGC(x)			((x) << 20)
+#define DWC_SGR_SGI(x)          ((x) << 0)
+#define DWC_SGR_SGC(x)          ((x) << 20)
 
 /* Bitfields in DSR */
-#define DWC_DSR_DSI(x)			((x) << 0)
-#define DWC_DSR_DSC(x)			((x) << 20)
+#define DWC_DSR_DSI(x)          ((x) << 0)
+#define DWC_DSR_DSC(x)          ((x) << 20)
 
 /* Bitfields in CFG */
-#define DW_CFG_DMA_EN			(1 << 0)
+#define DW_CFG_DMA_EN           (1 << 0)
 
-#define DW_REGLEN				0x400
+#define DW_REGLEN               0x400
 
 
 /* Platform-configurable bits in CFG_HI */
-#define DWC_CFGH_FCMODE		(1 << 0)
-#define DWC_CFGH_FIFO_MODE	(1 << 1)
-#define DWC_CFGH_PROTCTL(x)	((x) << 2)
-#define DWC_CFGH_SRC_PER(x)	((x) << 7)
-#define DWC_CFGH_DST_PER(x)	((x) << 11)
+#define DWC_CFGH_FCMODE     (1 << 0)
+#define DWC_CFGH_FIFO_MODE  (1 << 1)
+#define DWC_CFGH_PROTCTL(x) ((x) << 2)
+#define DWC_CFGH_SRC_PER(x) ((x) << 7)
+#define DWC_CFGH_DST_PER(x) ((x) << 11)
 
 /* Platform-configurable bits in CFG_LO */
-#define DWC_CFGL_LOCK_CH_XFER	(0 << 12)	/* scope of LOCK_CH */
-#define DWC_CFGL_LOCK_CH_BLOCK	(1 << 12)
-#define DWC_CFGL_LOCK_CH_XACT	(2 << 12)
-#define DWC_CFGL_LOCK_BUS_XFER	(0 << 14)	/* scope of LOCK_BUS */
-#define DWC_CFGL_LOCK_BUS_BLOCK	(1 << 14)
-#define DWC_CFGL_LOCK_BUS_XACT	(2 << 14)
-#define DWC_CFGL_LOCK_CH	(1 << 15)	/* channel lockout */
-#define DWC_CFGL_LOCK_BUS	(1 << 16)	/* busmaster lockout */
-#define DWC_CFGL_HS_DST_POL	(1 << 18)	/* dst handshake active low */
-#define DWC_CFGL_HS_SRC_POL	(1 << 19)	/* src handshake active low */
+#define DWC_CFGL_LOCK_CH_XFER   (0 << 12)   /* scope of LOCK_CH */
+#define DWC_CFGL_LOCK_CH_BLOCK  (1 << 12)
+#define DWC_CFGL_LOCK_CH_XACT   (2 << 12)
+#define DWC_CFGL_LOCK_BUS_XFER  (0 << 14)   /* scope of LOCK_BUS */
+#define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
+#define DWC_CFGL_LOCK_BUS_XACT  (2 << 14)
+#define DWC_CFGL_LOCK_CH    (1 << 15)   /* channel lockout */
+#define DWC_CFGL_LOCK_BUS   (1 << 16)   /* busmaster lockout */
+#define DWC_CFGL_HS_DST_POL (1 << 18)   /* dst handshake active low */
+#define DWC_CFGL_HS_SRC_POL (1 << 19)   /* src handshake active low */
 
 
 
 
-#define lift_shift_bit_num(bit_num)			(1<regs)->name))
+    __raw_readl(&(((struct dw_dma_regs *)dw->regs)->name))
 #define dw_writel(dw, name, val) \
-	__raw_writel((val), &(((struct dw_dma_regs *)dw->regs)->name))
+    __raw_writel((val), &(((struct dw_dma_regs *)dw->regs)->name))
 #define dw_readw(dw, name) \
-	__raw_readw(&(((struct dw_dma_regs *)dw->regs)->name))
+    __raw_readw(&(((struct dw_dma_regs *)dw->regs)->name))
 #define dw_writew(dw, name, val) \
-	__raw_writew((val), &(((struct dw_dma_regs *)dw->regs)->name))
+    __raw_writew((val), &(((struct dw_dma_regs *)dw->regs)->name))
 
 
 
 
 
 
-#define CHANNEL0		(lift_shift_bit_num(0))
-#define CHANNEL1		(lift_shift_bit_num(1))
-#define CHANNEL2		(lift_shift_bit_num(2))
-#define CHANNEL3		(lift_shift_bit_num(3))
+#define CHANNEL0        (lift_shift_bit_num(0))
+#define CHANNEL1        (lift_shift_bit_num(1))
+#define CHANNEL2        (lift_shift_bit_num(2))
+#define CHANNEL3        (lift_shift_bit_num(3))
 
 #define channel_set_bit(dw, reg, mask) \
-	dw_writel(dw, reg, ((mask) << 8) | (mask))
+    dw_writel(dw, reg, ((mask) << 8) | (mask))
 #define channel_clear_bit(dw, reg, mask) \
-	dw_writel(dw, reg, ((mask) << 8) | 0)
+    dw_writel(dw, reg, ((mask) << 8) | 0)
 
 
 
@@ -275,83 +275,83 @@ struct dw_dma_regs {
  ***************************************************************************/
 
 struct dw_dma{
-	//vadd
-	void 				*regs;
-	//padd
-	rt_uint32_t			paddr;
-	rt_uint32_t			irq;
-	rt_uint32_t			channel_max_number;
+    //vadd
+    void                *regs;
+    //padd
+    rt_uint32_t         paddr;
+    rt_uint32_t         irq;
+    rt_uint32_t         channel_max_number;
 
-#define CONTROLLER_STATUS_CLOSED		(0)
-#define CONTROLLER_STATUS_OPEN			(1)
-	rt_uint32_t			controller_status;
-#define FH81_DMA_INIT_NOT_YET		(0)
-#define FH81_DMA_INIT_ALREADY		(1)
-	rt_uint32_t			init;
-	rt_uint32_t			id;
-	char	 *name;
-	rt_uint32_t channel_work_done;
+#define CONTROLLER_STATUS_CLOSED        (0)
+#define CONTROLLER_STATUS_OPEN          (1)
+    rt_uint32_t         controller_status;
+#define FH81_DMA_INIT_NOT_YET       (0)
+#define FH81_DMA_INIT_ALREADY       (1)
+    rt_uint32_t         init;
+    rt_uint32_t         id;
+    char     *name;
+    rt_uint32_t channel_work_done;
 };
 
 
 struct dma_channel {
-#define CHANNEL_STATUS_CLOSED	(0)
-#define CHANNEL_STATUS_OPEN		(1)
-#define CHANNEL_STATUS_IDLE		(2)
-#define CHANNEL_STATUS_BUSY		(3)
+#define CHANNEL_STATUS_CLOSED   (0)
+#define CHANNEL_STATUS_OPEN     (1)
+#define CHANNEL_STATUS_IDLE     (2)
+#define CHANNEL_STATUS_BUSY     (3)
 
-	rt_uint32_t channel_status;	//open, busy ,closed
-	rt_uint32_t	desc_trans_size;
+    rt_uint32_t channel_status; //open, busy ,closed
+    rt_uint32_t desc_trans_size;
 
-	//isr will set it complete.
-	struct rt_completion transfer_completion;
-	//add lock,when set the channel.lock it
-	struct rt_semaphore channel_lock;
-	//struct rt_mutex                 lock;
-	//rt_enter_critical();
-	rt_list_t queue;
-	//active transfer now!!!
-	struct dma_transfer *active_trans;
+    //isr will set it complete.
+    struct rt_completion transfer_completion;
+    //add lock,when set the channel.lock it
+    struct rt_semaphore channel_lock;
+    //struct rt_mutex                 lock;
+    //rt_enter_critical();
+    rt_list_t queue;
+    //active transfer now!!!
+    struct dma_transfer *active_trans;
 
-#define SINGLE_TRANSFER			(0)
-#define CYCLIC_TRANSFER			(1)
-#define DEFAULT_TRANSFER		SINGLE_TRANSFER
-	rt_uint32_t open_flag;
-	//
+#define SINGLE_TRANSFER         (0)
+#define CYCLIC_TRANSFER         (1)
+#define DEFAULT_TRANSFER        SINGLE_TRANSFER
+    rt_uint32_t open_flag;
+    //
 
 
 
-	//new add para...
-	rt_uint32_t desc_total_no;
-	rt_uint32_t free_index;
-	rt_uint32_t used_index;
-	rt_uint32_t desc_left_cnt;
+    //new add para...
+    rt_uint32_t desc_total_no;
+    rt_uint32_t free_index;
+    rt_uint32_t used_index;
+    rt_uint32_t desc_left_cnt;
 
-	rt_uint32_t allign_malloc;
-	struct dw_lli *base_lli;
+    rt_uint32_t allign_malloc;
+    struct dw_lli *base_lli;
 };
 
 
 struct fh81_dma{
-	//core use ,this must be the first para!!!!
-	struct rt_dma_device parent;
-	//myown
-	struct dw_dma dwc;
-	//channel obj
-	struct dma_channel dma_channel[FH81_MAX_CHANNEL];
+    //core use ,this must be the first para!!!!
+    struct rt_dma_device parent;
+    //myown
+    struct dw_dma dwc;
+    //channel obj
+    struct dma_channel dma_channel[FH81_MAX_CHANNEL];
 
-	//struct rt_workqueue* isr_workqueue;
-	//struct rt_work *isr_work;
+    //struct rt_workqueue* isr_workqueue;
+    //struct rt_work *isr_work;
 
 };
 
 
 
-#define list_for_each_entry_safe(pos, n, head, member)			\
-	for (pos = rt_list_entry((head)->next, typeof(*pos), member),	\
-		n = rt_list_entry(pos->member.next, typeof(*pos), member);	\
-	     &pos->member != (head); 					\
-	     pos = n, n = rt_list_entry(n->member.next, typeof(*n), member))
+#define list_for_each_entry_safe(pos, n, head, member)          \
+    for (pos = rt_list_entry((head)->next, typeof(*pos), member),   \
+        n = rt_list_entry(pos->member.next, typeof(*pos), member);  \
+         &pos->member != (head);                    \
+         pos = n, n = rt_list_entry(n->member.next, typeof(*n), member))
 
 
 /******************************************************************************
@@ -384,8 +384,8 @@ static void rt_fh_dma_cyclic_free(struct dma_transfer *p);
 
 static struct rt_dma_ops fh81_dma_ops =
 {
-		init,
-		control
+        init,
+        control
 };
 
 
@@ -398,7 +398,7 @@ static struct rt_dma_ops fh81_dma_ops =
  * e.g.
  *  static uint8_t ufoo;
  *****************************************************************************/
-static struct fh81_dma	fh81_dma_controller[DMA_CONTROLLER_NUMBER] = {0};
+static struct fh81_dma  fh81_dma_controller[DMA_CONTROLLER_NUMBER] = {0};
 
 /* function body */
 /*****************************************************************************
@@ -411,80 +411,80 @@ static struct fh81_dma	fh81_dma_controller[DMA_CONTROLLER_NUMBER] = {0};
  *****************************************************************************/
 
 static rt_uint32_t allign_func(rt_uint32_t in_addr,rt_uint32_t allign_size){
-	return (in_addr + allign_size-1) & (~(allign_size - 1));
+    return (in_addr + allign_size-1) & (~(allign_size - 1));
 }
 
 
 struct dw_lli * get_desc(struct fh81_dma  *p_dma,struct dma_transfer *p_transfer,rt_uint32_t lli_size){
-	struct dw_lli * ret_lli;
-	rt_uint32_t free_index;
-	rt_uint32_t allign_left;
-	rt_uint32_t totoal_desc;
-	rt_uint32_t actual_get_desc;
-	rt_uint32_t totoal_free_desc;
-	totoal_free_desc = p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt;
-	free_index = p_dma->dma_channel[p_transfer->channel_number].free_index;
-	totoal_desc = p_dma->dma_channel[p_transfer->channel_number].desc_total_no;
-	allign_left = totoal_desc - free_index;
+    struct dw_lli * ret_lli;
+    rt_uint32_t free_index;
+    rt_uint32_t allign_left;
+    rt_uint32_t totoal_desc;
+    rt_uint32_t actual_get_desc;
+    rt_uint32_t totoal_free_desc;
+    totoal_free_desc = p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt;
+    free_index = p_dma->dma_channel[p_transfer->channel_number].free_index;
+    totoal_desc = p_dma->dma_channel[p_transfer->channel_number].desc_total_no;
+    allign_left = totoal_desc - free_index;
 
-	//check first..
-	if(totoal_free_desc < lli_size){
-		rt_kprintf("not enough desc to get...\n");
-		rt_kprintf("get size is %d,left is %d\n",lli_size,totoal_free_desc);
-		return RT_NULL;
-	}
-	//rt_kprintf("get desc in...\n");
+    //check first..
+    if(totoal_free_desc < lli_size){
+        rt_kprintf("not enough desc to get...\n");
+        rt_kprintf("get size is %d,left is %d\n",lli_size,totoal_free_desc);
+        return RT_NULL;
+    }
+    //rt_kprintf("get desc in...\n");
 
-	//rt_kprintf("lli size is %d\n",lli_size);
-	if(lli_size > allign_left){
-		//if allign desc not enough...just reset null....
-		if((totoal_free_desc - allign_left) < lli_size){
-			rt_kprintf("not enough desc to get...\n");
-			rt_kprintf("app need size is %d, totoal left is %d, allign left is %d\n",lli_size,totoal_free_desc,allign_left);
-			rt_kprintf("from head to get desc size is %d, actual get is %d\n",(totoal_free_desc - allign_left),(allign_left +lli_size));
-			return RT_NULL;
-		}
-		else{
-			actual_get_desc = allign_left +lli_size;
-			free_index = 0;
-		}
-	}
+    //rt_kprintf("lli size is %d\n",lli_size);
+    if(lli_size > allign_left){
+        //if allign desc not enough...just reset null....
+        if((totoal_free_desc - allign_left) < lli_size){
+            rt_kprintf("not enough desc to get...\n");
+            rt_kprintf("app need size is %d, totoal left is %d, allign left is %d\n",lli_size,totoal_free_desc,allign_left);
+            rt_kprintf("from head to get desc size is %d, actual get is %d\n",(totoal_free_desc - allign_left),(allign_left +lli_size));
+            return RT_NULL;
+        }
+        else{
+            actual_get_desc = allign_left +lli_size;
+            free_index = 0;
+        }
+    }
 
 
-	//ret_lli = &p_dma->dma_channel[p_transfer->channel_number].base_lli[free_index];
+    //ret_lli = &p_dma->dma_channel[p_transfer->channel_number].base_lli[free_index];
 
-	ret_lli = &p_dma->dma_channel[p_transfer->channel_number].base_lli[free_index];
-//	rt_kprintf("get desc base index addr:%08x\n",(rt_uint32_t)&p_dma->dma_channel[p_transfer->channel_number].base_lli[0]);
-//	rt_kprintf("get desc free index addr:%08x\n",(rt_uint32_t)ret_lli);
-//	rt_kprintf("get desc request size:%08x\n",lli_size);
-//	rt_kprintf("get desc total size:%08x\n",p_dma->dma_channel[p_transfer->channel_number].desc_total_no);
-//	rt_kprintf("one desc size is:%08x\n",sizeof(	struct dw_lli));
+    ret_lli = &p_dma->dma_channel[p_transfer->channel_number].base_lli[free_index];
+//  rt_kprintf("get desc base index addr:%08x\n",(rt_uint32_t)&p_dma->dma_channel[p_transfer->channel_number].base_lli[0]);
+//  rt_kprintf("get desc free index addr:%08x\n",(rt_uint32_t)ret_lli);
+//  rt_kprintf("get desc request size:%08x\n",lli_size);
+//  rt_kprintf("get desc total size:%08x\n",p_dma->dma_channel[p_transfer->channel_number].desc_total_no);
+//  rt_kprintf("one desc size is:%08x\n",sizeof(    struct dw_lli));
 
-	p_dma->dma_channel[p_transfer->channel_number].free_index += actual_get_desc;
+    p_dma->dma_channel[p_transfer->channel_number].free_index += actual_get_desc;
 
-	//rt_kprintf("get desc free index addr:%08x\n",(rt_uint32_t)&p_dma->dma_channel[p_transfer->channel_number].base_lli[p_dma->dma_channel[p_transfer->channel_number].free_index]);
+    //rt_kprintf("get desc free index addr:%08x\n",(rt_uint32_t)&p_dma->dma_channel[p_transfer->channel_number].base_lli[p_dma->dma_channel[p_transfer->channel_number].free_index]);
 
-	p_dma->dma_channel[p_transfer->channel_number].free_index %= p_dma->dma_channel[p_transfer->channel_number].desc_total_no;
-	p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt -= actual_get_desc;
-	p_transfer->lli_size = lli_size;
-	p_transfer->actual_lli_size = actual_get_desc;
-	return ret_lli;
+    p_dma->dma_channel[p_transfer->channel_number].free_index %= p_dma->dma_channel[p_transfer->channel_number].desc_total_no;
+    p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt -= actual_get_desc;
+    p_transfer->lli_size = lli_size;
+    p_transfer->actual_lli_size = actual_get_desc;
+    return ret_lli;
 }
 
 
 rt_uint32_t put_desc(struct fh81_dma  *p_dma,struct dma_transfer *p_transfer){
-	struct dw_lli * ret_lli;
-	rt_uint32_t used_index;
-	rt_uint32_t lli_size;
-	//rt_kprintf("put desc in...\n");
-	used_index = p_dma->dma_channel[p_transfer->channel_number].used_index;
-	lli_size = p_transfer->actual_lli_size;
-	p_dma->dma_channel[p_transfer->channel_number].used_index += lli_size;
-	p_dma->dma_channel[p_transfer->channel_number].used_index %= p_dma->dma_channel[p_transfer->channel_number].desc_total_no;
-	p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt += lli_size;
-	p_transfer->lli_size  = 0;
-	p_transfer->actual_lli_size = 0;
-	return 0;
+    struct dw_lli * ret_lli;
+    rt_uint32_t used_index;
+    rt_uint32_t lli_size;
+    //rt_kprintf("put desc in...\n");
+    used_index = p_dma->dma_channel[p_transfer->channel_number].used_index;
+    lli_size = p_transfer->actual_lli_size;
+    p_dma->dma_channel[p_transfer->channel_number].used_index += lli_size;
+    p_dma->dma_channel[p_transfer->channel_number].used_index %= p_dma->dma_channel[p_transfer->channel_number].desc_total_no;
+    p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt += lli_size;
+    p_transfer->lli_size  = 0;
+    p_transfer->actual_lli_size = 0;
+    return 0;
 }
 
 /*****************************************************************************
@@ -499,17 +499,17 @@ rt_uint32_t put_desc(struct fh81_dma  *p_dma,struct dma_transfer *p_transfer){
 static rt_err_t init (struct rt_dma_device *dma){
 
 
-	//init the clk table
+    //init the clk table
 
 
-	struct fh81_dma *my_own = (struct  fh81_dma *)dma->parent.user_data;
+    struct fh81_dma *my_own = (struct  fh81_dma *)dma->parent.user_data;
 
-	FH_DMA_DEBUG("my_own value:0x%x\n",(rt_uint32_t)my_own);
+    FH_DMA_DEBUG("my_own value:0x%x\n",(rt_uint32_t)my_own);
 
-	//check the user data
-	RT_ASSERT(my_own != RT_NULL);
+    //check the user data
+    RT_ASSERT(my_own != RT_NULL);
 
-	return RT_EOK;
+    return RT_EOK;
 
 }
 
@@ -528,12 +528,12 @@ static rt_err_t init (struct rt_dma_device *dma){
 
 static void handle_dma_open(struct fh81_dma  *p_dma){
 
-	rt_uint32_t i;
-	struct dw_dma *temp_dwc;
-	temp_dwc = &p_dma->dwc;
+    rt_uint32_t i;
+    struct dw_dma *temp_dwc;
+    temp_dwc = &p_dma->dwc;
 
-	dw_writel(temp_dwc, CFG, 1);
-	p_dma->dwc.controller_status = CONTROLLER_STATUS_OPEN;
+    dw_writel(temp_dwc, CFG, 1);
+    p_dma->dwc.controller_status = CONTROLLER_STATUS_OPEN;
 
 }
 
@@ -549,27 +549,27 @@ static void handle_dma_open(struct fh81_dma  *p_dma){
 static void handle_dma_close(struct fh81_dma  *p_dma){
 
 
-	rt_uint32_t i;
-	struct dw_dma *temp_dwc;
-	temp_dwc = &p_dma->dwc;
+    rt_uint32_t i;
+    struct dw_dma *temp_dwc;
+    temp_dwc = &p_dma->dwc;
 
-	//take lock
-	for(i=0;idwc.channel_max_number;i++){
-		rt_sem_take(&p_dma->dma_channel[i].channel_lock, RT_WAITING_FOREVER);
+    //take lock
+    for(i=0;idwc.channel_max_number;i++){
+        rt_sem_take(&p_dma->dma_channel[i].channel_lock, RT_WAITING_FOREVER);
 
-		channel_clear_bit(temp_dwc, CH_EN, lift_shift_bit_num(i));
-		p_dma->dma_channel[i].channel_status = CHANNEL_STATUS_CLOSED;
-	}
-	dw_writel(temp_dwc, CFG, 0);
-	p_dma->dwc.controller_status = CONTROLLER_STATUS_CLOSED;
+        channel_clear_bit(temp_dwc, CH_EN, lift_shift_bit_num(i));
+        p_dma->dma_channel[i].channel_status = CHANNEL_STATUS_CLOSED;
+    }
+    dw_writel(temp_dwc, CFG, 0);
+    p_dma->dwc.controller_status = CONTROLLER_STATUS_CLOSED;
 
-	//release lock
-	for(i=0;idwc.channel_max_number;i++){
-		rt_sem_release(&p_dma->dma_channel[i].channel_lock);
-	}
+    //release lock
+    for(i=0;idwc.channel_max_number;i++){
+        rt_sem_release(&p_dma->dma_channel[i].channel_lock);
+    }
 
-	//destroy the workqueue..
-	//rt_workqueue_destroy(p_dma->isr_workqueue);
+    //destroy the workqueue..
+    //rt_workqueue_destroy(p_dma->isr_workqueue);
 
 
 }
@@ -584,26 +584,26 @@ static void handle_dma_close(struct fh81_dma  *p_dma){
  *      what does this function returned?
  *****************************************************************************/
 
-#define CHANNEL_REAL_FREE			(0)
-#define CHANNEL_NOT_FREE			(1)
+#define CHANNEL_REAL_FREE           (0)
+#define CHANNEL_NOT_FREE            (1)
 
 static rt_uint32_t check_channel_real_free(struct fh81_dma  *p_dma,rt_uint32_t channel_number){
 
 
-	struct dw_dma *temp_dwc;
-	temp_dwc = &p_dma->dwc;
-	rt_uint32_t ret_status;
+    struct dw_dma *temp_dwc;
+    temp_dwc = &p_dma->dwc;
+    rt_uint32_t ret_status;
 
 
-	RT_ASSERT(channel_number < p_dma->dwc.channel_max_number);
+    RT_ASSERT(channel_number < p_dma->dwc.channel_max_number);
 
-	ret_status = dw_readl(temp_dwc, CH_EN);
-	if(ret_status & lift_shift_bit_num(channel_number)){
-		//the channel is still busy!!!error here
-		//FH_DMA_DEBUG("auto request channel error\n");
-		return CHANNEL_NOT_FREE;
-	}
-	return CHANNEL_REAL_FREE;
+    ret_status = dw_readl(temp_dwc, CH_EN);
+    if(ret_status & lift_shift_bit_num(channel_number)){
+        //the channel is still busy!!!error here
+        //FH_DMA_DEBUG("auto request channel error\n");
+        return CHANNEL_NOT_FREE;
+    }
+    return CHANNEL_REAL_FREE;
 
 }
 
@@ -620,110 +620,110 @@ static rt_uint32_t check_channel_real_free(struct fh81_dma  *p_dma,rt_uint32_t c
 
 static rt_err_t handle_request_channel(struct fh81_dma  *p_dma,struct dma_transfer *p_transfer){
 
-	rt_uint32_t i;
-	struct dw_dma *temp_dwc;
-	temp_dwc = &p_dma->dwc;
-	rt_err_t ret_status = RT_EOK;
+    rt_uint32_t i;
+    struct dw_dma *temp_dwc;
+    temp_dwc = &p_dma->dwc;
+    rt_err_t ret_status = RT_EOK;
 
-	//handle if auto check channel...
-	if(p_transfer->channel_number == AUTO_FIND_CHANNEL){
-		//check each channel lock,find a free channel...
-		for(i=0;idwc.channel_max_number;i++){
-			ret_status = rt_sem_trytake(&p_dma->dma_channel[i].channel_lock);
-			if(ret_status == RT_EOK){
-				break;
-			}
-		}
+    //handle if auto check channel...
+    if(p_transfer->channel_number == AUTO_FIND_CHANNEL){
+        //check each channel lock,find a free channel...
+        for(i=0;idwc.channel_max_number;i++){
+            ret_status = rt_sem_trytake(&p_dma->dma_channel[i].channel_lock);
+            if(ret_status == RT_EOK){
+                break;
+            }
+        }
 
-		if(i < p_dma->dwc.channel_max_number){
-			ret_status = check_channel_real_free(p_dma,i);
-			if(ret_status!= CHANNEL_REAL_FREE){
-				FH_DMA_DEBUG("auto request channel error\n");
-				RT_ASSERT(ret_status == CHANNEL_REAL_FREE);
-			}
-			//caution : channel is already locked here....
-			p_transfer->channel_number = i;
-			//bind to the controller.
-			//p_transfer->dma_controller = p_dma;
-			p_dma->dma_channel[i].channel_status = CHANNEL_STATUS_OPEN;
-		}
-		else
-			return -RT_ENOMEM;
+        if(i < p_dma->dwc.channel_max_number){
+            ret_status = check_channel_real_free(p_dma,i);
+            if(ret_status!= CHANNEL_REAL_FREE){
+                FH_DMA_DEBUG("auto request channel error\n");
+                RT_ASSERT(ret_status == CHANNEL_REAL_FREE);
+            }
+            //caution : channel is already locked here....
+            p_transfer->channel_number = i;
+            //bind to the controller.
+            //p_transfer->dma_controller = p_dma;
+            p_dma->dma_channel[i].channel_status = CHANNEL_STATUS_OPEN;
+        }
+        else
+            return -RT_ENOMEM;
 
-	}
+    }
 
-	// request channel by user
-	else{
-		//
+    // request channel by user
+    else{
+        //
 
-		RT_ASSERT(p_transfer->channel_number < p_dma->dwc.channel_max_number);
-		ret_status = rt_sem_take(&p_dma->dma_channel[p_transfer->channel_number].channel_lock, RT_TICK_PER_SECOND*50);
-		if(ret_status != RT_EOK)
-			return -RT_ENOMEM;
-		//rt_enter_critical();
-		ret_status = check_channel_real_free(p_dma,p_transfer->channel_number);
-		if(ret_status!= CHANNEL_REAL_FREE){
-			FH_DMA_DEBUG("user request channel error\n");
-			RT_ASSERT(ret_status == CHANNEL_REAL_FREE);
-		}
+        RT_ASSERT(p_transfer->channel_number < p_dma->dwc.channel_max_number);
+        ret_status = rt_sem_take(&p_dma->dma_channel[p_transfer->channel_number].channel_lock, RT_TICK_PER_SECOND*50);
+        if(ret_status != RT_EOK)
+            return -RT_ENOMEM;
+        //rt_enter_critical();
+        ret_status = check_channel_real_free(p_dma,p_transfer->channel_number);
+        if(ret_status!= CHANNEL_REAL_FREE){
+            FH_DMA_DEBUG("user request channel error\n");
+            RT_ASSERT(ret_status == CHANNEL_REAL_FREE);
+        }
 
-		//bind to the controller
-		//p_transfer->dma_controller = p_dma;
-		p_dma->dma_channel[p_transfer->channel_number].channel_status = CHANNEL_STATUS_OPEN;
-		//rt_exit_critical();
-	}
+        //bind to the controller
+        //p_transfer->dma_controller = p_dma;
+        p_dma->dma_channel[p_transfer->channel_number].channel_status = CHANNEL_STATUS_OPEN;
+        //rt_exit_critical();
+    }
 
 
-	//malloc desc for this one channel...
-	//fix me....
+    //malloc desc for this one channel...
+    //fix me....
 
-	p_dma->dma_channel[p_transfer->channel_number].allign_malloc =	(rt_uint32_t) rt_malloc(
-			(p_dma->dma_channel[p_transfer->channel_number].desc_total_no
-					* sizeof(struct dw_lli)) + CACHE_LINE_SIZE);
+    p_dma->dma_channel[p_transfer->channel_number].allign_malloc =  (rt_uint32_t) rt_malloc(
+            (p_dma->dma_channel[p_transfer->channel_number].desc_total_no
+                    * sizeof(struct dw_lli)) + CACHE_LINE_SIZE);
 
 
-	if(!p_dma->dma_channel[p_transfer->channel_number].allign_malloc){
-		//release channel
-		rt_kprintf("[dma]: no mem to malloc channel%d desc..\n",p_transfer->channel_number);
-		p_dma->dma_channel[p_transfer->channel_number].channel_status = CHANNEL_STATUS_CLOSED;
-		rt_sem_release(&p_dma->dma_channel[p_transfer->channel_number].channel_lock);
-		return -RT_ENOMEM;
-	}
+    if(!p_dma->dma_channel[p_transfer->channel_number].allign_malloc){
+        //release channel
+        rt_kprintf("[dma]: no mem to malloc channel%d desc..\n",p_transfer->channel_number);
+        p_dma->dma_channel[p_transfer->channel_number].channel_status = CHANNEL_STATUS_CLOSED;
+        rt_sem_release(&p_dma->dma_channel[p_transfer->channel_number].channel_lock);
+        return -RT_ENOMEM;
+    }
 
 
-	p_dma->dma_channel[p_transfer->channel_number].base_lli =
-			(struct dw_lli *) allign_func(
-					p_dma->dma_channel[p_transfer->channel_number].allign_malloc,
-					CACHE_LINE_SIZE);
+    p_dma->dma_channel[p_transfer->channel_number].base_lli =
+            (struct dw_lli *) allign_func(
+                    p_dma->dma_channel[p_transfer->channel_number].allign_malloc,
+                    CACHE_LINE_SIZE);
 
-	FH_DMA_DEBUG("dma desc addr is %x\n",(rt_uint32_t)p_dma->dma_channel[p_transfer->channel_number].base_lli);
-	//t1 = (UINT32)rt_malloc(GMAC_TX_RING_SIZE * sizeof(Gmac_Tx_DMA_Descriptors) + CACHE_LINE_SIZE);
+    FH_DMA_DEBUG("dma desc addr is %x\n",(rt_uint32_t)p_dma->dma_channel[p_transfer->channel_number].base_lli);
+    //t1 = (UINT32)rt_malloc(GMAC_TX_RING_SIZE * sizeof(Gmac_Tx_DMA_Descriptors) + CACHE_LINE_SIZE);
 
 
-	if(!p_dma->dma_channel[p_transfer->channel_number].base_lli){
-		FH_DMA_DEBUG("request desc failed..\n");
-		RT_ASSERT(p_dma->dma_channel[p_transfer->channel_number].base_lli != RT_NULL);
-	}
+    if(!p_dma->dma_channel[p_transfer->channel_number].base_lli){
+        FH_DMA_DEBUG("request desc failed..\n");
+        RT_ASSERT(p_dma->dma_channel[p_transfer->channel_number].base_lli != RT_NULL);
+    }
 
-	if((rt_uint32_t)p_dma->dma_channel[p_transfer->channel_number].base_lli % 32){
-		rt_kprintf("malloc is not cache allign..");
+    if((rt_uint32_t)p_dma->dma_channel[p_transfer->channel_number].base_lli % 32){
+        rt_kprintf("malloc is not cache allign..");
 
-	}
+    }
 
 
 
-	//rt_memset((void *)dma_trans_desc->first_lli, 0, lli_size * sizeof(struct dw_lli));
-	rt_memset((void *) p_dma->dma_channel[p_transfer->channel_number].base_lli,
-			0,
-			p_dma->dma_channel[p_transfer->channel_number].desc_total_no
-					* sizeof(struct dw_lli));
+    //rt_memset((void *)dma_trans_desc->first_lli, 0, lli_size * sizeof(struct dw_lli));
+    rt_memset((void *) p_dma->dma_channel[p_transfer->channel_number].base_lli,
+            0,
+            p_dma->dma_channel[p_transfer->channel_number].desc_total_no
+                    * sizeof(struct dw_lli));
 
-	p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt = p_dma->dma_channel[p_transfer->channel_number].desc_total_no;
-	p_dma->dma_channel[p_transfer->channel_number].free_index = 0;
-	p_dma->dma_channel[p_transfer->channel_number].used_index = 0;
+    p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt = p_dma->dma_channel[p_transfer->channel_number].desc_total_no;
+    p_dma->dma_channel[p_transfer->channel_number].free_index = 0;
+    p_dma->dma_channel[p_transfer->channel_number].used_index = 0;
 
 
-	return RT_EOK;
+    return RT_EOK;
 
 }
 
@@ -747,40 +747,40 @@ static rt_err_t handle_request_channel(struct fh81_dma  *p_dma,struct dma_transf
 static rt_uint32_t handle_release_channel(struct fh81_dma  *p_dma,struct dma_transfer *p_transfer){
 
 
-	rt_uint32_t i;
-	struct dw_dma *temp_dwc;
-	temp_dwc = &p_dma->dwc;
-	rt_uint32_t ret_status;
+    rt_uint32_t i;
+    struct dw_dma *temp_dwc;
+    temp_dwc = &p_dma->dwc;
+    rt_uint32_t ret_status;
 
-	//rt_enter_critical();
-	ret_status = p_dma->dma_channel[p_transfer->channel_number].channel_status;
+    //rt_enter_critical();
+    ret_status = p_dma->dma_channel[p_transfer->channel_number].channel_status;
 
 
-	RT_ASSERT(p_transfer->channel_number < p_dma->dwc.channel_max_number);
+    RT_ASSERT(p_transfer->channel_number < p_dma->dwc.channel_max_number);
 
 
-	if(ret_status == CHANNEL_STATUS_CLOSED){
-		FH_DMA_DEBUG("release channel error,reason: release a closed channel!!\n");
-		RT_ASSERT(ret_status != CHANNEL_STATUS_CLOSED);
-	}
+    if(ret_status == CHANNEL_STATUS_CLOSED){
+        FH_DMA_DEBUG("release channel error,reason: release a closed channel!!\n");
+        RT_ASSERT(ret_status != CHANNEL_STATUS_CLOSED);
+    }
 
-	channel_clear_bit(temp_dwc, CH_EN, lift_shift_bit_num(p_transfer->channel_number));
-	rt_sem_release(&p_dma->dma_channel[p_transfer->channel_number].channel_lock);
-	//p_transfer->dma_controller = RT_NULL;
-	p_dma->dma_channel[p_transfer->channel_number].channel_status = CHANNEL_STATUS_CLOSED;
-	p_dma->dma_channel[p_transfer->channel_number].open_flag = DEFAULT_TRANSFER;
-	//rt_exit_critical();
+    channel_clear_bit(temp_dwc, CH_EN, lift_shift_bit_num(p_transfer->channel_number));
+    rt_sem_release(&p_dma->dma_channel[p_transfer->channel_number].channel_lock);
+    //p_transfer->dma_controller = RT_NULL;
+    p_dma->dma_channel[p_transfer->channel_number].channel_status = CHANNEL_STATUS_CLOSED;
+    p_dma->dma_channel[p_transfer->channel_number].open_flag = DEFAULT_TRANSFER;
+    //rt_exit_critical();
 
-	//release this channel malloc mem...
-	//fix me.....
-	rt_free((void *)p_dma->dma_channel[p_transfer->channel_number].allign_malloc);
-	p_dma->dma_channel[p_transfer->channel_number].allign_malloc = RT_NULL;
-	p_dma->dma_channel[p_transfer->channel_number].base_lli = RT_NULL;
-	p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt = p_dma->dma_channel[p_transfer->channel_number].desc_total_no;
-	p_dma->dma_channel[p_transfer->channel_number].free_index = 0;
-	p_dma->dma_channel[p_transfer->channel_number].used_index = 0;
+    //release this channel malloc mem...
+    //fix me.....
+    rt_free((void *)p_dma->dma_channel[p_transfer->channel_number].allign_malloc);
+    p_dma->dma_channel[p_transfer->channel_number].allign_malloc = RT_NULL;
+    p_dma->dma_channel[p_transfer->channel_number].base_lli = RT_NULL;
+    p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt = p_dma->dma_channel[p_transfer->channel_number].desc_total_no;
+    p_dma->dma_channel[p_transfer->channel_number].free_index = 0;
+    p_dma->dma_channel[p_transfer->channel_number].used_index = 0;
 
-	return RT_EOK;
+    return RT_EOK;
 
 
 }
@@ -788,26 +788,26 @@ static rt_uint32_t handle_release_channel(struct fh81_dma  *p_dma,struct dma_tra
 
 
 static rt_uint32_t cal_lli_size(struct dma_transfer *p_transfer){
-	RT_ASSERT(p_transfer != RT_NULL);
-	RT_ASSERT(p_transfer->dma_controller != RT_NULL);
-	RT_ASSERT(p_transfer->src_width <= DW_DMA_SLAVE_WIDTH_32BIT);
-	rt_uint32_t lli_number = 0;
-	rt_uint32_t channel_max_trans_per_lli = 0;
-	channel_max_trans_per_lli = p_transfer->dma_controller->dma_channel[p_transfer->channel_number].desc_trans_size;
+    RT_ASSERT(p_transfer != RT_NULL);
+    RT_ASSERT(p_transfer->dma_controller != RT_NULL);
+    RT_ASSERT(p_transfer->src_width <= DW_DMA_SLAVE_WIDTH_32BIT);
+    rt_uint32_t lli_number = 0;
+    rt_uint32_t channel_max_trans_per_lli = 0;
+    channel_max_trans_per_lli = p_transfer->dma_controller->dma_channel[p_transfer->channel_number].desc_trans_size;
 
 
-	lli_number = (p_transfer->trans_len % channel_max_trans_per_lli) ? 1:0;
-	lli_number += p_transfer->trans_len / channel_max_trans_per_lli;
+    lli_number = (p_transfer->trans_len % channel_max_trans_per_lli) ? 1:0;
+    lli_number += p_transfer->trans_len / channel_max_trans_per_lli;
 
-	return lli_number;
+    return lli_number;
 
 }
 
 
 static void dump_lli(struct dw_lli *p_lli){
-	FH_DMA_DEBUG("link_mem padd:0x%x\n sar:0x%x\n dar:0x%x\n llp:0x%x\n ctllo:0x%x\n ctlhi:0x%x\n sstat:0x%x\n dstat:0x%x\n",
-			(rt_uint32_t)p_lli,p_lli->sar, p_lli->dar, p_lli->llp,
-			p_lli->ctllo, p_lli->ctlhi,p_lli->sstat,p_lli->dstat);
+    FH_DMA_DEBUG("link_mem padd:0x%x\n sar:0x%x\n dar:0x%x\n llp:0x%x\n ctllo:0x%x\n ctlhi:0x%x\n sstat:0x%x\n dstat:0x%x\n",
+            (rt_uint32_t)p_lli,p_lli->sar, p_lli->dar, p_lli->llp,
+            p_lli->ctllo, p_lli->ctlhi,p_lli->sstat,p_lli->dstat);
 }
 /*****************************************************************************
  * Description:
@@ -820,296 +820,296 @@ static void dump_lli(struct dw_lli *p_lli){
 static void handle_single_transfer(struct fh81_dma  *p_dma,struct dma_transfer *p_transfer){
 
 
-	rt_uint32_t i;
-	struct dw_dma *temp_dwc;
-	temp_dwc = &p_dma->dwc;
-	volatile rt_uint32_t ret_status;
-	rt_list_t *p_controller_list;
-	rt_uint32_t lli_size,max_trans_size;
-	struct dw_lli  *p_lli = RT_NULL;
-	struct dma_transfer *dma_trans_desc;
-	struct dma_transfer *_dma_trans_desc;
+    rt_uint32_t i;
+    struct dw_dma *temp_dwc;
+    temp_dwc = &p_dma->dwc;
+    volatile rt_uint32_t ret_status;
+    rt_list_t *p_controller_list;
+    rt_uint32_t lli_size,max_trans_size;
+    struct dw_lli  *p_lli = RT_NULL;
+    struct dma_transfer *dma_trans_desc;
+    struct dma_transfer *_dma_trans_desc;
 
 
-	rt_uint32_t temp_src_add;
-	rt_uint32_t temp_dst_add;
-	rt_uint32_t trans_total_len = 0;
-	rt_uint32_t temp_trans_size = 0;
-	//rt_uint32_t dma_channl_no = 0;
+    rt_uint32_t temp_src_add;
+    rt_uint32_t temp_dst_add;
+    rt_uint32_t trans_total_len = 0;
+    rt_uint32_t temp_trans_size = 0;
+    //rt_uint32_t dma_channl_no = 0;
 
-	RT_ASSERT(p_transfer->channel_number < p_dma->dwc.channel_max_number);
-	RT_ASSERT(p_transfer->dma_number < DMA_CONTROLLER_NUMBER);
-	RT_ASSERT(&fh81_dma_controller[p_transfer->dma_number] == p_dma);
-	//when the dma transfer....the lock should be 0!!!!
-	//or user may not request the channel...
-	RT_ASSERT(p_dma->dma_channel[p_transfer->channel_number].channel_lock.value == 0);
+    RT_ASSERT(p_transfer->channel_number < p_dma->dwc.channel_max_number);
+    RT_ASSERT(p_transfer->dma_number < DMA_CONTROLLER_NUMBER);
+    RT_ASSERT(&fh81_dma_controller[p_transfer->dma_number] == p_dma);
+    //when the dma transfer....the lock should be 0!!!!
+    //or user may not request the channel...
+    RT_ASSERT(p_dma->dma_channel[p_transfer->channel_number].channel_lock.value == 0);
 
 
-	ret_status = p_dma->dma_channel[p_transfer->channel_number].channel_status;
-	if(ret_status == CHANNEL_STATUS_CLOSED){
-		FH_DMA_DEBUG("transfer error,reason: use a closed channel..\n");
-		RT_ASSERT(ret_status != CHANNEL_STATUS_CLOSED);
-	}
-	p_transfer->dma_controller = p_dma;
+    ret_status = p_dma->dma_channel[p_transfer->channel_number].channel_status;
+    if(ret_status == CHANNEL_STATUS_CLOSED){
+        FH_DMA_DEBUG("transfer error,reason: use a closed channel..\n");
+        RT_ASSERT(ret_status != CHANNEL_STATUS_CLOSED);
+    }
+    p_transfer->dma_controller = p_dma;
 
 
 
-	rt_list_init(&p_transfer->transfer_list);
-	max_trans_size = p_transfer->dma_controller->dma_channel[p_transfer->channel_number].desc_trans_size;
-	//add transfer to the controller's queue list
-	//here should  insert before and handle after....this could be a fifo...
-	rt_list_insert_before(&p_dma->dma_channel[p_transfer->channel_number].queue , &p_transfer->transfer_list);
+    rt_list_init(&p_transfer->transfer_list);
+    max_trans_size = p_transfer->dma_controller->dma_channel[p_transfer->channel_number].desc_trans_size;
+    //add transfer to the controller's queue list
+    //here should  insert before and handle after....this could be a fifo...
+    rt_list_insert_before(&p_dma->dma_channel[p_transfer->channel_number].queue , &p_transfer->transfer_list);
 
 
-	p_controller_list = &p_dma->dma_channel[p_transfer->channel_number].queue;
+    p_controller_list = &p_dma->dma_channel[p_transfer->channel_number].queue;
 
 
-	//here the driver could make a queue to cache the transfer and kick a thread to handle the queue~~~
-	//but now,this is a easy version...,just handle the transfer now!!!
-	list_for_each_entry_safe(dma_trans_desc, _dma_trans_desc, p_controller_list, transfer_list) {
+    //here the driver could make a queue to cache the transfer and kick a thread to handle the queue~~~
+    //but now,this is a easy version...,just handle the transfer now!!!
+    list_for_each_entry_safe(dma_trans_desc, _dma_trans_desc, p_controller_list, transfer_list) {
 
-		//the dma controller could see the active transfer .....
-		p_transfer->dma_controller->dma_channel[p_transfer->channel_number].active_trans = dma_trans_desc;
+        //the dma controller could see the active transfer .....
+        p_transfer->dma_controller->dma_channel[p_transfer->channel_number].active_trans = dma_trans_desc;
 
 
-		trans_total_len = p_transfer->trans_len;
+        trans_total_len = p_transfer->trans_len;
 
 
-		//handle desc
-		//step1:cal lli size...
-		lli_size = cal_lli_size(dma_trans_desc);
-		//step2:malloc lli_size  mem
-		//dma_trans_desc->first_lli = (struct dw_lli *)rt_malloc(lli_size * sizeof(struct dw_lli));
+        //handle desc
+        //step1:cal lli size...
+        lli_size = cal_lli_size(dma_trans_desc);
+        //step2:malloc lli_size  mem
+        //dma_trans_desc->first_lli = (struct dw_lli *)rt_malloc(lli_size * sizeof(struct dw_lli));
 
-		dma_trans_desc->first_lli = get_desc(p_dma,p_transfer,lli_size);
+        dma_trans_desc->first_lli = get_desc(p_dma,p_transfer,lli_size);
 
-		//not enough mem..
-		if(dma_trans_desc->first_lli == RT_NULL){
+        //not enough mem..
+        if(dma_trans_desc->first_lli == RT_NULL){
 
-			FH_DMA_DEBUG("transfer error,reason: not enough mem..\n");
-			RT_ASSERT(dma_trans_desc->first_lli != RT_NULL);
-		}
+            FH_DMA_DEBUG("transfer error,reason: not enough mem..\n");
+            RT_ASSERT(dma_trans_desc->first_lli != RT_NULL);
+        }
 
 
-		//bug here....
-		rt_memset((void *)dma_trans_desc->first_lli, 0, lli_size * sizeof(struct dw_lli));
+        //bug here....
+        rt_memset((void *)dma_trans_desc->first_lli, 0, lli_size * sizeof(struct dw_lli));
 
-		p_lli = dma_trans_desc->first_lli;
+        p_lli = dma_trans_desc->first_lli;
 
-		//warnning!!!!must check if the add is 32bits ally...
-		RT_ASSERT(((rt_uint32_t)p_lli & 0x03) == 0);
+        //warnning!!!!must check if the add is 32bits ally...
+        RT_ASSERT(((rt_uint32_t)p_lli & 0x03) == 0);
 
-		RT_ASSERT(dma_trans_desc->dst_inc_mode <=DW_DMA_SLAVE_FIX);
-		RT_ASSERT(dma_trans_desc->src_inc_mode <=DW_DMA_SLAVE_FIX);
-		//step3: set the mem..
-		for(i=0;idst_inc_mode <=DW_DMA_SLAVE_FIX);
+        RT_ASSERT(dma_trans_desc->src_inc_mode <=DW_DMA_SLAVE_FIX);
+        //step3: set the mem..
+        for(i=0;idst_inc_mode){
-			case DW_DMA_SLAVE_INC:
-				temp_dst_add = dma_trans_desc->dst_add + i * max_trans_size * (1<dst_width);
-				break;
-			case DW_DMA_SLAVE_DEC:
-				temp_dst_add = dma_trans_desc->dst_add - i * max_trans_size * (1<dst_width);
-				break;
-			case DW_DMA_SLAVE_FIX:
-				temp_dst_add = dma_trans_desc->dst_add;
-				break;
+            switch(dma_trans_desc->dst_inc_mode){
+            case DW_DMA_SLAVE_INC:
+                temp_dst_add = dma_trans_desc->dst_add + i * max_trans_size * (1<dst_width);
+                break;
+            case DW_DMA_SLAVE_DEC:
+                temp_dst_add = dma_trans_desc->dst_add - i * max_trans_size * (1<dst_width);
+                break;
+            case DW_DMA_SLAVE_FIX:
+                temp_dst_add = dma_trans_desc->dst_add;
+                break;
 
-			}
+            }
 
 
-			switch(dma_trans_desc->src_inc_mode){
-			case DW_DMA_SLAVE_INC:
-				temp_src_add = dma_trans_desc->src_add + i * max_trans_size * (1<src_width);
-				break;
-			case DW_DMA_SLAVE_DEC:
-				temp_src_add = dma_trans_desc->src_add - i * max_trans_size * (1<src_width);
-				break;
-			case DW_DMA_SLAVE_FIX:
-				temp_src_add = dma_trans_desc->src_add ;
-				break;
+            switch(dma_trans_desc->src_inc_mode){
+            case DW_DMA_SLAVE_INC:
+                temp_src_add = dma_trans_desc->src_add + i * max_trans_size * (1<src_width);
+                break;
+            case DW_DMA_SLAVE_DEC:
+                temp_src_add = dma_trans_desc->src_add - i * max_trans_size * (1<src_width);
+                break;
+            case DW_DMA_SLAVE_FIX:
+                temp_src_add = dma_trans_desc->src_add ;
+                break;
 
-			}
+            }
 
 
-			p_lli[i].sar = temp_src_add;
-			p_lli[i].dar = temp_dst_add;
+            p_lli[i].sar = temp_src_add;
+            p_lli[i].dar = temp_dst_add;
 
-			//para ctl
-			temp_trans_size = (trans_total_len / max_trans_size)? max_trans_size : (trans_total_len % max_trans_size);
-			trans_total_len -= temp_trans_size;
+            //para ctl
+            temp_trans_size = (trans_total_len / max_trans_size)? max_trans_size : (trans_total_len % max_trans_size);
+            trans_total_len -= temp_trans_size;
 
-			RT_ASSERT(dma_trans_desc->dst_width <=DW_DMA_SLAVE_WIDTH_32BIT);
-			RT_ASSERT(dma_trans_desc->src_width <=DW_DMA_SLAVE_WIDTH_32BIT);
+            RT_ASSERT(dma_trans_desc->dst_width <=DW_DMA_SLAVE_WIDTH_32BIT);
+            RT_ASSERT(dma_trans_desc->src_width <=DW_DMA_SLAVE_WIDTH_32BIT);
 
-			RT_ASSERT(dma_trans_desc->dst_msize <=DW_DMA_SLAVE_MSIZE_256);
-			RT_ASSERT(dma_trans_desc->src_msize <=DW_DMA_SLAVE_MSIZE_256);
-			RT_ASSERT(dma_trans_desc->fc_mode <=DMA_P2P);
+            RT_ASSERT(dma_trans_desc->dst_msize <=DW_DMA_SLAVE_MSIZE_256);
+            RT_ASSERT(dma_trans_desc->src_msize <=DW_DMA_SLAVE_MSIZE_256);
+            RT_ASSERT(dma_trans_desc->fc_mode <=DMA_P2P);
 
 
 
-			p_lli[i].ctllo = DWC_CTLL_INT_EN|DWC_CTLL_DST_WIDTH(dma_trans_desc->dst_width)|DWC_CTLL_SRC_WIDTH(dma_trans_desc->src_width)
-					|DWC_CTLL_DST_INC_MODE(dma_trans_desc->dst_inc_mode)|DWC_CTLL_SRC_INC_MODE(dma_trans_desc->src_inc_mode)
-					|DWC_CTLL_DST_MSIZE(dma_trans_desc->dst_msize)|DWC_CTLL_SRC_MSIZE(dma_trans_desc->src_msize)|DWC_CTLL_FC(dma_trans_desc->fc_mode)
-					|DWC_CTLL_DMS(0)|DWC_CTLL_SMS(0);
-			//block size
-			p_lli[i].ctlhi = temp_trans_size;
+            p_lli[i].ctllo = DWC_CTLL_INT_EN|DWC_CTLL_DST_WIDTH(dma_trans_desc->dst_width)|DWC_CTLL_SRC_WIDTH(dma_trans_desc->src_width)
+                    |DWC_CTLL_DST_INC_MODE(dma_trans_desc->dst_inc_mode)|DWC_CTLL_SRC_INC_MODE(dma_trans_desc->src_inc_mode)
+                    |DWC_CTLL_DST_MSIZE(dma_trans_desc->dst_msize)|DWC_CTLL_SRC_MSIZE(dma_trans_desc->src_msize)|DWC_CTLL_FC(dma_trans_desc->fc_mode)
+                    |DWC_CTLL_DMS(0)|DWC_CTLL_SMS(0);
+            //block size
+            p_lli[i].ctlhi = temp_trans_size;
 
 
-			if(trans_total_len > 0){
-				p_lli[i].llp = (rt_uint32_t)&p_lli[i+1];
-				p_lli[i].ctllo |= DWC_CTLL_LLP_D_EN|DWC_CTLL_LLP_S_EN;
-			}
+            if(trans_total_len > 0){
+                p_lli[i].llp = (rt_uint32_t)&p_lli[i+1];
+                p_lli[i].ctllo |= DWC_CTLL_LLP_D_EN|DWC_CTLL_LLP_S_EN;
+            }
 
-			//flush cache to mem
-			mmu_clean_invalidated_dcache((rt_uint32_t)&p_lli[i],sizeof(struct dw_lli));
+            //flush cache to mem
+            mmu_clean_invalidated_dcache((rt_uint32_t)&p_lli[i],sizeof(struct dw_lli));
 
-			dump_lli(&p_lli[i]);
-		}
+            dump_lli(&p_lli[i]);
+        }
 
-		//clear the isr status
+        //clear the isr status
 
 
 
 
-		//set the dma config reg
-		//clear cfg reload reg
-		//ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO);
-		//ret_status &= ~(DWC_CFGL_RELOAD_SAR|DWC_CFGL_RELOAD_DAR);
-		dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,0);
+        //set the dma config reg
+        //clear cfg reload reg
+        //ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO);
+        //ret_status &= ~(DWC_CFGL_RELOAD_SAR|DWC_CFGL_RELOAD_DAR);
+        dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,0);
 
-		//set the first link add
-		//ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].LLP);
-		ret_status = 0;
-		ret_status = (rt_uint32_t)&p_lli[0];
-		dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].LLP,ret_status);
+        //set the first link add
+        //ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].LLP);
+        ret_status = 0;
+        ret_status = (rt_uint32_t)&p_lli[0];
+        dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].LLP,ret_status);
 
-		//set link enable
-		//ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CTL_LO);
-		ret_status = 0;
-		ret_status =DWC_CTLL_LLP_D_EN|DWC_CTLL_LLP_S_EN;
-		dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CTL_LO,ret_status);
+        //set link enable
+        //ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CTL_LO);
+        ret_status = 0;
+        ret_status =DWC_CTLL_LLP_D_EN|DWC_CTLL_LLP_S_EN;
+        dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CTL_LO,ret_status);
 
-		dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CTL_HI,0);
-		//set handshaking
+        dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CTL_HI,0);
+        //set handshaking
 
-		RT_ASSERT(dma_trans_desc->dst_hs <=	DMA_SW_HANDSHAKING);
-		RT_ASSERT(dma_trans_desc->src_hs <=	DMA_SW_HANDSHAKING);
+        RT_ASSERT(dma_trans_desc->dst_hs <= DMA_SW_HANDSHAKING);
+        RT_ASSERT(dma_trans_desc->src_hs <= DMA_SW_HANDSHAKING);
 
-		if(dma_trans_desc->dst_hs == DMA_SW_HANDSHAKING){
-			ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO);
-			ret_status |= DWC_CFGL_HS_DST;
-			dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status);
-		}
-		else{
-			ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO);
-			ret_status &= ~DWC_CFGL_HS_DST;
-			dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status);
-		}
+        if(dma_trans_desc->dst_hs == DMA_SW_HANDSHAKING){
+            ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO);
+            ret_status |= DWC_CFGL_HS_DST;
+            dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status);
+        }
+        else{
+            ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO);
+            ret_status &= ~DWC_CFGL_HS_DST;
+            dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status);
+        }
 
-		if(dma_trans_desc->src_hs == DMA_SW_HANDSHAKING){
-			ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO);
-			ret_status |= DWC_CFGL_HS_SRC;
-			dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status);
-		}
-		else{
-			ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO);
-			ret_status &= ~DWC_CFGL_HS_SRC;
-			dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status);
-		}
+        if(dma_trans_desc->src_hs == DMA_SW_HANDSHAKING){
+            ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO);
+            ret_status |= DWC_CFGL_HS_SRC;
+            dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status);
+        }
+        else{
+            ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO);
+            ret_status &= ~DWC_CFGL_HS_SRC;
+            dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status);
+        }
 
 
-		//only hw handshaking need this..
-		switch(dma_trans_desc->fc_mode){
-		case	DMA_M2M:
-			break;
-		case	DMA_M2P:
-			//set dst per...
-			RT_ASSERT(dma_trans_desc->dst_per <	DMA_HW_HS_END);
+        //only hw handshaking need this..
+        switch(dma_trans_desc->fc_mode){
+        case    DMA_M2M:
+            break;
+        case    DMA_M2P:
+            //set dst per...
+            RT_ASSERT(dma_trans_desc->dst_per < DMA_HW_HS_END);
 
-			ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI);
+            ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI);
 
-			//clear 43 ~ 46 bit
-			ret_status &= ~0x7800;
+            //clear 43 ~ 46 bit
+            ret_status &= ~0x7800;
 
-			ret_status |= DWC_CFGH_DST_PER(dma_trans_desc->dst_per);
-			dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status);
-			//DWC_CFGH_SRC_PER
+            ret_status |= DWC_CFGH_DST_PER(dma_trans_desc->dst_per);
+            dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status);
+            //DWC_CFGH_SRC_PER
 
 
-			break;
-		case 	DMA_P2M:
-			//set src per...
-			RT_ASSERT(dma_trans_desc->src_per <	DMA_HW_HS_END);
+            break;
+        case    DMA_P2M:
+            //set src per...
+            RT_ASSERT(dma_trans_desc->src_per < DMA_HW_HS_END);
 
 
-			ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI);
+            ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI);
 
-			//clear 39 ~ 42 bit
-			ret_status &= ~0x780;
+            //clear 39 ~ 42 bit
+            ret_status &= ~0x780;
 
 
-			ret_status |= DWC_CFGH_SRC_PER(dma_trans_desc->src_per);
-			dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status);
+            ret_status |= DWC_CFGH_SRC_PER(dma_trans_desc->src_per);
+            dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status);
 
-			break;
-		case 	DMA_P2P:
-			//set src and dst..
-			RT_ASSERT(dma_trans_desc->dst_per <	DMA_HW_HS_END);
-			RT_ASSERT(dma_trans_desc->src_per <	DMA_HW_HS_END);
+            break;
+        case    DMA_P2P:
+            //set src and dst..
+            RT_ASSERT(dma_trans_desc->dst_per < DMA_HW_HS_END);
+            RT_ASSERT(dma_trans_desc->src_per < DMA_HW_HS_END);
 
-			ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI);
-			ret_status &= ~0x7800;
-			ret_status &= ~0x780;
-			ret_status |= DWC_CFGH_SRC_PER(dma_trans_desc->src_per) | DWC_CFGH_DST_PER(dma_trans_desc->dst_per);
-			dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status);
+            ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI);
+            ret_status &= ~0x7800;
+            ret_status &= ~0x780;
+            ret_status |= DWC_CFGH_SRC_PER(dma_trans_desc->src_per) | DWC_CFGH_DST_PER(dma_trans_desc->dst_per);
+            dw_writel(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status);
 
-			break;
-		default:
-			break;
-		}
+            break;
+        default:
+            break;
+        }
 
 
-		dma_trans_desc->dma_controller->dma_channel[dma_trans_desc->channel_number].channel_status = CHANNEL_STATUS_BUSY;
-		//enable isr...
-		channel_set_bit(temp_dwc, MASK.XFER, lift_shift_bit_num(dma_trans_desc->channel_number));
-		channel_set_bit(temp_dwc, MASK.ERROR, lift_shift_bit_num(dma_trans_desc->channel_number));
-		//close
-		channel_clear_bit(temp_dwc, MASK.BLOCK, lift_shift_bit_num(dma_trans_desc->channel_number));
+        dma_trans_desc->dma_controller->dma_channel[dma_trans_desc->channel_number].channel_status = CHANNEL_STATUS_BUSY;
+        //enable isr...
+        channel_set_bit(temp_dwc, MASK.XFER, lift_shift_bit_num(dma_trans_desc->channel_number));
+        channel_set_bit(temp_dwc, MASK.ERROR, lift_shift_bit_num(dma_trans_desc->channel_number));
+        //close
+        channel_clear_bit(temp_dwc, MASK.BLOCK, lift_shift_bit_num(dma_trans_desc->channel_number));
 
-		dw_writel(temp_dwc, CLEAR.XFER, 1<<(dma_trans_desc->channel_number));
-		dw_writel(temp_dwc, CLEAR.BLOCK, 1<<(dma_trans_desc->channel_number));
-		dw_writel(temp_dwc, CLEAR.SRC_TRAN, 1<<(dma_trans_desc->channel_number));
-		dw_writel(temp_dwc, CLEAR.DST_TRAN, 1<<(dma_trans_desc->channel_number));
-		dw_writel(temp_dwc, CLEAR.ERROR, 1<<(dma_trans_desc->channel_number));
+        dw_writel(temp_dwc, CLEAR.XFER, 1<<(dma_trans_desc->channel_number));
+        dw_writel(temp_dwc, CLEAR.BLOCK, 1<<(dma_trans_desc->channel_number));
+        dw_writel(temp_dwc, CLEAR.SRC_TRAN, 1<<(dma_trans_desc->channel_number));
+        dw_writel(temp_dwc, CLEAR.DST_TRAN, 1<<(dma_trans_desc->channel_number));
+        dw_writel(temp_dwc, CLEAR.ERROR, 1<<(dma_trans_desc->channel_number));
 
 
-		ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI);
-		FH_DMA_DEBUG("cfg_hi value:0x%x\n",ret_status);
+        ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_HI);
+        FH_DMA_DEBUG("cfg_hi value:0x%x\n",ret_status);
 
-		ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO);
-		FH_DMA_DEBUG("cfg_low value:0x%x\n",ret_status);
+        ret_status = dw_readl(temp_dwc,CHAN[dma_trans_desc->channel_number].CFG_LO);
+        FH_DMA_DEBUG("cfg_low value:0x%x\n",ret_status);
 
 
-		ret_status = dw_readl(temp_dwc, MASK.BLOCK);
-		FH_DMA_DEBUG("mask block value:0x%x\n",ret_status);
+        ret_status = dw_readl(temp_dwc, MASK.BLOCK);
+        FH_DMA_DEBUG("mask block value:0x%x\n",ret_status);
 
-		ret_status = dw_readl(temp_dwc, MASK.XFER);
-		FH_DMA_DEBUG("mask xfer value:0x%x\n",ret_status);
+        ret_status = dw_readl(temp_dwc, MASK.XFER);
+        FH_DMA_DEBUG("mask xfer value:0x%x\n",ret_status);
 
 
 
-		if(dma_trans_desc->prepare_callback){
-				dma_trans_desc->prepare_callback(dma_trans_desc->prepare_para);
-		}
-		//enable the channle to transfer
-		channel_set_bit(temp_dwc, CH_EN, lift_shift_bit_num(dma_trans_desc->channel_number));
+        if(dma_trans_desc->prepare_callback){
+                dma_trans_desc->prepare_callback(dma_trans_desc->prepare_para);
+        }
+        //enable the channle to transfer
+        channel_set_bit(temp_dwc, CH_EN, lift_shift_bit_num(dma_trans_desc->channel_number));
 
 
 
-	}
+    }
 
 }
 
@@ -1124,85 +1124,85 @@ static void handle_single_transfer(struct fh81_dma  *p_dma,struct dma_transfer *
 static rt_err_t control (struct rt_dma_device *dma, int cmd, void *arg){
 
 
-	struct fh81_dma *my_own = (struct fh81_dma *)dma->parent.user_data;
-	rt_uint32_t i;
-	struct dw_dma *dwc;
-	dwc = &my_own->dwc;
+    struct fh81_dma *my_own = (struct fh81_dma *)dma->parent.user_data;
+    rt_uint32_t i;
+    struct dw_dma *dwc;
+    dwc = &my_own->dwc;
 
-	rt_err_t ret = RT_EOK;
+    rt_err_t ret = RT_EOK;
 
-	struct dma_transfer *p_dma_transfer = (struct dma_transfer *)arg;
+    struct dma_transfer *p_dma_transfer = (struct dma_transfer *)arg;
 
-	//FH_DMA_DEBUG("p_dma_transfer value:0x%x\n",(rt_uint32_t)p_dma_transfer);
+    //FH_DMA_DEBUG("p_dma_transfer value:0x%x\n",(rt_uint32_t)p_dma_transfer);
 
 
-	RT_ASSERT(my_own != RT_NULL);
-	RT_ASSERT(dwc != RT_NULL);
+    RT_ASSERT(my_own != RT_NULL);
+    RT_ASSERT(dwc != RT_NULL);
 
 
 
-	switch(cmd){
-	case RT_DEVICE_CTRL_DMA_OPEN:
+    switch(cmd){
+    case RT_DEVICE_CTRL_DMA_OPEN:
 
-		//open the controller..
-		handle_dma_open(my_own);
-		break;
-	case RT_DEVICE_CTRL_DMA_CLOSE:
+        //open the controller..
+        handle_dma_open(my_own);
+        break;
+    case RT_DEVICE_CTRL_DMA_CLOSE:
 
-		//close the controller..
-		handle_dma_close(my_own);
-		break;
-	case RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL:
-		//request a channel for the user
-		RT_ASSERT(p_dma_transfer != RT_NULL);
-		ret = handle_request_channel(my_own,p_dma_transfer);
+        //close the controller..
+        handle_dma_close(my_own);
+        break;
+    case RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL:
+        //request a channel for the user
+        RT_ASSERT(p_dma_transfer != RT_NULL);
+        ret = handle_request_channel(my_own,p_dma_transfer);
 
-		break;
-	case RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL:
-		//release a channel
-		RT_ASSERT(p_dma_transfer != RT_NULL);
+        break;
+    case RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL:
+        //release a channel
+        RT_ASSERT(p_dma_transfer != RT_NULL);
 
-		ret = handle_release_channel(my_own,p_dma_transfer);
+        ret = handle_release_channel(my_own,p_dma_transfer);
 
 
-		break;
+        break;
 
-	case RT_DEVICE_CTRL_DMA_SINGLE_TRANSFER:
-		//make a channel to transfer data.
-		RT_ASSERT(p_dma_transfer != RT_NULL);
-		//check if the dma channel is open,or return error.
+    case RT_DEVICE_CTRL_DMA_SINGLE_TRANSFER:
+        //make a channel to transfer data.
+        RT_ASSERT(p_dma_transfer != RT_NULL);
+        //check if the dma channel is open,or return error.
 
-		my_own->dma_channel[p_dma_transfer->channel_number].open_flag = SINGLE_TRANSFER;
-		handle_single_transfer(my_own,p_dma_transfer);
-		//then wait for the channel is complete..
-		//caution that::we should be in the "rt_enter_critical()"when set the dma to work.
-		break;
+        my_own->dma_channel[p_dma_transfer->channel_number].open_flag = SINGLE_TRANSFER;
+        handle_single_transfer(my_own,p_dma_transfer);
+        //then wait for the channel is complete..
+        //caution that::we should be in the "rt_enter_critical()"when set the dma to work.
+        break;
 
 
-	case RT_DEVICE_CTRL_DMA_CYCLIC_PREPARE:
-		RT_ASSERT(p_dma_transfer != RT_NULL);
-		my_own->dma_channel[p_dma_transfer->channel_number].open_flag = CYCLIC_TRANSFER;
-		rt_fh_dma_cyclic_prep(my_own,p_dma_transfer);
-		break;
+    case RT_DEVICE_CTRL_DMA_CYCLIC_PREPARE:
+        RT_ASSERT(p_dma_transfer != RT_NULL);
+        my_own->dma_channel[p_dma_transfer->channel_number].open_flag = CYCLIC_TRANSFER;
+        rt_fh_dma_cyclic_prep(my_own,p_dma_transfer);
+        break;
 
-	case RT_DEVICE_CTRL_DMA_CYCLIC_START:
-		rt_fh_dma_cyclic_start(p_dma_transfer);
-		break;
+    case RT_DEVICE_CTRL_DMA_CYCLIC_START:
+        rt_fh_dma_cyclic_start(p_dma_transfer);
+        break;
 
-	case RT_DEVICE_CTRL_DMA_CYCLIC_STOP:
-		rt_fh_dma_cyclic_stop(p_dma_transfer);
-		break;
+    case RT_DEVICE_CTRL_DMA_CYCLIC_STOP:
+        rt_fh_dma_cyclic_stop(p_dma_transfer);
+        break;
 
-	case RT_DEVICE_CTRL_DMA_CYCLIC_FREE:
-		rt_fh_dma_cyclic_free(p_dma_transfer);
-		break;
+    case RT_DEVICE_CTRL_DMA_CYCLIC_FREE:
+        rt_fh_dma_cyclic_free(p_dma_transfer);
+        break;
 
-	default:
-		break;
+    default:
+        break;
 
-	}
+    }
 
-	return ret;
+    return ret;
 
 
 }
@@ -1213,55 +1213,55 @@ static void rt_fh81_dma_isr(int irq, void *param)
 {
 
 
-	RT_ASSERT(irq == DMAC_IRQn);
-	rt_uint32_t isr_channel_x,i,error,isr_channel_b;
-	struct fh81_dma *my_own = (struct fh81_dma *)param;
-	struct dw_dma *dwc;
-	struct dma_transfer *p_transfer;
-	dwc = &my_own->dwc;
-	//p_transfer =
-	//rt_kprintf("dma isr get in~~~\n");
-	error = dw_readl(dwc,STATUS.ERROR);
-	if(error != 0){
-		FH_DMA_DEBUG("dma isr error!!!!\n");
-		RT_ASSERT(error == RT_NULL);
-	}
+    RT_ASSERT(irq == DMAC_IRQn);
+    rt_uint32_t isr_channel_x,i,error,isr_channel_b;
+    struct fh81_dma *my_own = (struct fh81_dma *)param;
+    struct dw_dma *dwc;
+    struct dma_transfer *p_transfer;
+    dwc = &my_own->dwc;
+    //p_transfer =
+    //rt_kprintf("dma isr get in~~~\n");
+    error = dw_readl(dwc,STATUS.ERROR);
+    if(error != 0){
+        FH_DMA_DEBUG("dma isr error!!!!\n");
+        RT_ASSERT(error == RT_NULL);
+    }
 
-	isr_channel_x = dw_readl(dwc,STATUS.XFER);
-	isr_channel_b = dw_readl(dwc,STATUS.BLOCK);
-	//for single check the transfer status
-	//check which channel...
+    isr_channel_x = dw_readl(dwc,STATUS.XFER);
+    isr_channel_b = dw_readl(dwc,STATUS.BLOCK);
+    //for single check the transfer status
+    //check which channel...
 
-	for(i=0;idwc.channel_max_number;i++){
+    for(i=0;idwc.channel_max_number;i++){
 
-		if(my_own->dma_channel[i].open_flag == SINGLE_TRANSFER){
-			if(isr_channel_x & 1<dma_channel[i].open_flag == SINGLE_TRANSFER){
+            if(isr_channel_x & 1<dma_channel[i].active_trans;
+                p_transfer = my_own->dma_channel[i].active_trans;
 
-				if(p_transfer->complete_callback){
-						p_transfer->complete_callback(p_transfer->complete_para);
-				}
-				p_transfer->dma_controller->dma_channel[p_transfer->channel_number].channel_status = CHANNEL_STATUS_IDLE;
-				//here is a bug...do not free here
-				//rt_free(p_transfer->first_lli);
-				put_desc(my_own,p_transfer);
-				rt_list_remove(&p_transfer->transfer_list);
-			}
+                if(p_transfer->complete_callback){
+                        p_transfer->complete_callback(p_transfer->complete_para);
+                }
+                p_transfer->dma_controller->dma_channel[p_transfer->channel_number].channel_status = CHANNEL_STATUS_IDLE;
+                //here is a bug...do not free here
+                //rt_free(p_transfer->first_lli);
+                put_desc(my_own,p_transfer);
+                rt_list_remove(&p_transfer->transfer_list);
+            }
 
-		}
+        }
 
-		else if(my_own->dma_channel[i].open_flag == CYCLIC_TRANSFER){
-			if(isr_channel_b & 1<dma_channel[i].active_trans;
-				dw_writel(dwc, CLEAR.BLOCK, 1<<(p_transfer->channel_number));
-				if(p_transfer->complete_callback){
-						p_transfer->complete_callback(p_transfer->complete_para);
-				}
-			}
-		}
-	}
+        else if(my_own->dma_channel[i].open_flag == CYCLIC_TRANSFER){
+            if(isr_channel_b & 1<dma_channel[i].active_trans;
+                dw_writel(dwc, CLEAR.BLOCK, 1<<(p_transfer->channel_number));
+                if(p_transfer->complete_callback){
+                        p_transfer->complete_callback(p_transfer->complete_para);
+                }
+            }
+        }
+    }
 
 
 }
@@ -1278,55 +1278,55 @@ static void rt_fh81_dma_isr(int irq, void *param)
  *****************************************************************************/
 
 const char *channel_lock_name[FH81_MAX_CHANNEL] = {
-		"channel_0_lock",
-		"channel_1_lock",
-		"channel_2_lock",
-		"channel_3_lock",
+        "channel_0_lock",
+        "channel_1_lock",
+        "channel_2_lock",
+        "channel_3_lock",
 };
 
 rt_err_t fh81_dma_register(struct fh81_dma * fh81_dma_p,
                              char * dma_name){
 
-	rt_uint32_t i;
+    rt_uint32_t i;
 
-	RT_ASSERT(fh81_dma_p != RT_NULL);
-	RT_ASSERT(dma_name != RT_NULL);
-	//RT_ASSERT(fh81_dma_p->dwc.init != FH81_DMA_INIT_ALREADY);
+    RT_ASSERT(fh81_dma_p != RT_NULL);
+    RT_ASSERT(dma_name != RT_NULL);
+    //RT_ASSERT(fh81_dma_p->dwc.init != FH81_DMA_INIT_ALREADY);
 
 
-	if(fh81_dma_p->dwc.init == FH81_DMA_INIT_ALREADY)
-		return 0;
+    if(fh81_dma_p->dwc.init == FH81_DMA_INIT_ALREADY)
+        return 0;
 
-	struct rt_dma_device *rt_dma;
-	rt_dma = &fh81_dma_p->parent;
-	rt_dma->ops = &fh81_dma_ops;
+    struct rt_dma_device *rt_dma;
+    rt_dma = &fh81_dma_p->parent;
+    rt_dma->ops = &fh81_dma_ops;
 
 
-	//soc para set
-	fh81_dma_p->dwc.name = dma_name;
-	fh81_dma_p->dwc.regs =(void *)DMA_REG_BASE;
-	fh81_dma_p->dwc.paddr =	DMA_REG_BASE;
-	fh81_dma_p->dwc.irq = DMAC_IRQn;
-	fh81_dma_p->dwc.channel_max_number = FH81_MAX_CHANNEL;
-	fh81_dma_p->dwc.controller_status = CONTROLLER_STATUS_CLOSED;
-	fh81_dma_p->dwc.init = FH81_DMA_INIT_ALREADY;
-	fh81_dma_p->dwc.id = 0;
-	//channel set
-	for(i=0;idma_channel[i].channel_status = CHANNEL_STATUS_CLOSED;
-		fh81_dma_p->dma_channel[i].desc_total_no = DESC_MAX_SIZE;
-		//rt_completion_init(&(fh81_dma_p->dma_channel[i].transfer_completion));
-		rt_list_init(&(fh81_dma_p->dma_channel[i].queue));
-		fh81_dma_p->dma_channel[i].desc_trans_size = FH81_CHANNEL_MAX_TRANSFER_SIZE;
-		rt_sem_init(&fh81_dma_p->dma_channel[i].channel_lock, channel_lock_name[i], 1, RT_IPC_FLAG_FIFO);
-	}
+    //soc para set
+    fh81_dma_p->dwc.name = dma_name;
+    fh81_dma_p->dwc.regs =(void *)DMA_REG_BASE;
+    fh81_dma_p->dwc.paddr = DMA_REG_BASE;
+    fh81_dma_p->dwc.irq = DMAC_IRQn;
+    fh81_dma_p->dwc.channel_max_number = FH81_MAX_CHANNEL;
+    fh81_dma_p->dwc.controller_status = CONTROLLER_STATUS_CLOSED;
+    fh81_dma_p->dwc.init = FH81_DMA_INIT_ALREADY;
+    fh81_dma_p->dwc.id = 0;
+    //channel set
+    for(i=0;idma_channel[i].channel_status = CHANNEL_STATUS_CLOSED;
+        fh81_dma_p->dma_channel[i].desc_total_no = DESC_MAX_SIZE;
+        //rt_completion_init(&(fh81_dma_p->dma_channel[i].transfer_completion));
+        rt_list_init(&(fh81_dma_p->dma_channel[i].queue));
+        fh81_dma_p->dma_channel[i].desc_trans_size = FH81_CHANNEL_MAX_TRANSFER_SIZE;
+        rt_sem_init(&fh81_dma_p->dma_channel[i].channel_lock, channel_lock_name[i], 1, RT_IPC_FLAG_FIFO);
+    }
 
-	//isr
-	rt_hw_interrupt_install(fh81_dma_p->dwc.irq, rt_fh81_dma_isr,
-							(void *)fh81_dma_p, "dma_isr");
-	rt_hw_interrupt_umask(fh81_dma_p->dwc.irq);
+    //isr
+    rt_hw_interrupt_install(fh81_dma_p->dwc.irq, rt_fh81_dma_isr,
+                            (void *)fh81_dma_p, "dma_isr");
+    rt_hw_interrupt_umask(fh81_dma_p->dwc.irq);
 
-	return	rt_hw_dma_register(rt_dma,dma_name,RT_DEVICE_FLAG_RDWR,fh81_dma_p);
+    return  rt_hw_dma_register(rt_dma,dma_name,RT_DEVICE_FLAG_RDWR,fh81_dma_p);
 
 
 }
@@ -1334,10 +1334,10 @@ rt_err_t fh81_dma_register(struct fh81_dma * fh81_dma_p,
 
 static void rt_fh_dma_cyclic_stop(struct dma_transfer *p){
 
-	struct fh81_dma *my_own = p->dma_controller;
-	struct dw_dma *dwc;
-	dwc = &my_own->dwc;
-	channel_clear_bit(dwc, CH_EN, 1<<(p->channel_number));
+    struct fh81_dma *my_own = p->dma_controller;
+    struct dw_dma *dwc;
+    dwc = &my_own->dwc;
+    channel_clear_bit(dwc, CH_EN, 1<<(p->channel_number));
 }
 
 
@@ -1345,45 +1345,45 @@ static void rt_fh_dma_cyclic_stop(struct dma_transfer *p){
 
 static void rt_fh_dma_cyclic_start(struct dma_transfer *p){
 
-	struct fh81_dma *my_own = p->dma_controller;
-	struct dw_dma *dwc;
-	dwc = &my_own->dwc;
-	volatile uint32_t ret_status;
-	struct dw_lli  *p_lli = RT_NULL;
-	p_lli = p->first_lli;
+    struct fh81_dma *my_own = p->dma_controller;
+    struct dw_dma *dwc;
+    dwc = &my_own->dwc;
+    volatile uint32_t ret_status;
+    struct dw_lli  *p_lli = RT_NULL;
+    p_lli = p->first_lli;
 
-	//32bit ally
-	RT_ASSERT(((uint32_t)p_lli & 0x03) == 0);
+    //32bit ally
+    RT_ASSERT(((uint32_t)p_lli & 0x03) == 0);
 
-	dw_writel(dwc, CLEAR.XFER, 1<<(p->channel_number));
-	dw_writel(dwc, CLEAR.BLOCK, 1<<(p->channel_number));
-	dw_writel(dwc, CLEAR.ERROR, 1<<(p->channel_number));
+    dw_writel(dwc, CLEAR.XFER, 1<<(p->channel_number));
+    dw_writel(dwc, CLEAR.BLOCK, 1<<(p->channel_number));
+    dw_writel(dwc, CLEAR.ERROR, 1<<(p->channel_number));
 
 
-	//enable isr
-	channel_set_bit(dwc, MASK.BLOCK, lift_shift_bit_num(p->channel_number));
-	//disable isr
-	channel_clear_bit(dwc, MASK.XFER, lift_shift_bit_num(p->channel_number));
+    //enable isr
+    channel_set_bit(dwc, MASK.BLOCK, lift_shift_bit_num(p->channel_number));
+    //disable isr
+    channel_clear_bit(dwc, MASK.XFER, lift_shift_bit_num(p->channel_number));
 
-	ret_status = dw_readl(dwc,CHAN[p->channel_number].CFG_LO);
-	ret_status &= ~(DWC_CFGL_RELOAD_SAR|DWC_CFGL_RELOAD_DAR);
-	dw_writel(dwc,CHAN[p->channel_number].CFG_LO,ret_status);
+    ret_status = dw_readl(dwc,CHAN[p->channel_number].CFG_LO);
+    ret_status &= ~(DWC_CFGL_RELOAD_SAR|DWC_CFGL_RELOAD_DAR);
+    dw_writel(dwc,CHAN[p->channel_number].CFG_LO,ret_status);
 
-	//set the first link add
-	ret_status = dw_readl(dwc,CHAN[p->channel_number].LLP);
-	ret_status = (uint32_t)&p_lli[0];
-	dw_writel(dwc,CHAN[p->channel_number].LLP,ret_status);
+    //set the first link add
+    ret_status = dw_readl(dwc,CHAN[p->channel_number].LLP);
+    ret_status = (uint32_t)&p_lli[0];
+    dw_writel(dwc,CHAN[p->channel_number].LLP,ret_status);
 
-	//set link enable
-	//ret_status = dw_readl(dwc,CHAN[p->channel_number].CTL_LO);
-	ret_status =DWC_CTLL_LLP_D_EN|DWC_CTLL_LLP_S_EN;
-	dw_writel(dwc,CHAN[p->channel_number].CTL_LO,ret_status);
+    //set link enable
+    //ret_status = dw_readl(dwc,CHAN[p->channel_number].CTL_LO);
+    ret_status =DWC_CTLL_LLP_D_EN|DWC_CTLL_LLP_S_EN;
+    dw_writel(dwc,CHAN[p->channel_number].CTL_LO,ret_status);
 
-	//clear ctl_hi
-	dw_writel(dwc,CHAN[p->channel_number].CTL_HI,0);
+    //clear ctl_hi
+    dw_writel(dwc,CHAN[p->channel_number].CTL_HI,0);
 
-	//enable channle
-	channel_set_bit(dwc, CH_EN, 1<<(p->channel_number));
+    //enable channle
+    channel_set_bit(dwc, CH_EN, 1<<(p->channel_number));
 
 
 }
@@ -1391,228 +1391,228 @@ static void rt_fh_dma_cyclic_start(struct dma_transfer *p){
 
 static void rt_fh_dma_cyclic_prep(struct fh81_dma * fh81_dma_p,struct dma_transfer *p) {
 
-	//bind the controller to the transfer
-	p->dma_controller = fh81_dma_p;
-	//bind active transfer
-	fh81_dma_p->dma_channel[p->channel_number].active_trans = p;
-	//p_transfer->dma_controller->dma_channel[p_transfer->channel_number].active_trans = dma_trans_desc;
-	struct fh81_dma *my_own = p->dma_controller;
-	struct dw_dma *dwc;
-	dwc = &my_own->dwc;
-	volatile uint32_t ret_status;
-	struct dw_lli  *p_lli = RT_NULL;
-	uint32_t periods,i;
-	uint32_t temp_src_add;
-	uint32_t temp_dst_add;
-	uint32_t buf_len = p->trans_len;
-	uint32_t period_len = p->period_len;
+    //bind the controller to the transfer
+    p->dma_controller = fh81_dma_p;
+    //bind active transfer
+    fh81_dma_p->dma_channel[p->channel_number].active_trans = p;
+    //p_transfer->dma_controller->dma_channel[p_transfer->channel_number].active_trans = dma_trans_desc;
+    struct fh81_dma *my_own = p->dma_controller;
+    struct dw_dma *dwc;
+    dwc = &my_own->dwc;
+    volatile uint32_t ret_status;
+    struct dw_lli  *p_lli = RT_NULL;
+    uint32_t periods,i;
+    uint32_t temp_src_add;
+    uint32_t temp_dst_add;
+    uint32_t buf_len = p->trans_len;
+    uint32_t period_len = p->period_len;
 
-	struct dma_transfer * dma_trans_desc = p;
-	//check first...
-	RT_ASSERT(buf_len % period_len == 0);
+    struct dma_transfer * dma_trans_desc = p;
+    //check first...
+    RT_ASSERT(buf_len % period_len == 0);
 
-	//cal the periods...
-	periods = buf_len / period_len;
+    //cal the periods...
+    periods = buf_len / period_len;
 
 
-	//get desc....
-	//dma_trans_desc->first_lli = (struct dw_lli *)rt_malloc(periods * sizeof(struct dw_lli));
-	dma_trans_desc->first_lli  = get_desc(fh81_dma_p,dma_trans_desc,periods);
+    //get desc....
+    //dma_trans_desc->first_lli = (struct dw_lli *)rt_malloc(periods * sizeof(struct dw_lli));
+    dma_trans_desc->first_lli  = get_desc(fh81_dma_p,dma_trans_desc,periods);
 
-	if(dma_trans_desc->first_lli == RT_NULL){
+    if(dma_trans_desc->first_lli == RT_NULL){
 
-		FH_DMA_DEBUG("transfer error,reason: not enough mem..\n");
-		RT_ASSERT(dma_trans_desc->first_lli != RT_NULL);
-	}
+        FH_DMA_DEBUG("transfer error,reason: not enough mem..\n");
+        RT_ASSERT(dma_trans_desc->first_lli != RT_NULL);
+    }
 
-	rt_memset((void *)dma_trans_desc->first_lli, 0, periods * sizeof(struct dw_lli));
-	p_lli = dma_trans_desc->first_lli;
+    rt_memset((void *)dma_trans_desc->first_lli, 0, periods * sizeof(struct dw_lli));
+    p_lli = dma_trans_desc->first_lli;
 
-	RT_ASSERT(((uint32_t)p_lli & 0x03) == 0);
+    RT_ASSERT(((uint32_t)p_lli & 0x03) == 0);
 
 
-	RT_ASSERT(dma_trans_desc->dst_inc_mode <=DW_DMA_SLAVE_FIX);
-	RT_ASSERT(dma_trans_desc->src_inc_mode <=DW_DMA_SLAVE_FIX);
-	//step3: set the mem..
-	for(i=0;idst_inc_mode){
-		case DW_DMA_SLAVE_INC:
-			temp_dst_add = dma_trans_desc->dst_add + i * period_len * (1<dst_width);
-			break;
-		case DW_DMA_SLAVE_DEC:
-			temp_dst_add = dma_trans_desc->dst_add - i * period_len * (1<dst_width);
-			break;
-		case DW_DMA_SLAVE_FIX:
-			temp_dst_add = dma_trans_desc->dst_add;
-			break;
+    RT_ASSERT(dma_trans_desc->dst_inc_mode <=DW_DMA_SLAVE_FIX);
+    RT_ASSERT(dma_trans_desc->src_inc_mode <=DW_DMA_SLAVE_FIX);
+    //step3: set the mem..
+    for(i=0;idst_inc_mode){
+        case DW_DMA_SLAVE_INC:
+            temp_dst_add = dma_trans_desc->dst_add + i * period_len * (1<dst_width);
+            break;
+        case DW_DMA_SLAVE_DEC:
+            temp_dst_add = dma_trans_desc->dst_add - i * period_len * (1<dst_width);
+            break;
+        case DW_DMA_SLAVE_FIX:
+            temp_dst_add = dma_trans_desc->dst_add;
+            break;
 
-		}
+        }
 
 
-		switch(dma_trans_desc->src_inc_mode){
-		case DW_DMA_SLAVE_INC:
-			temp_src_add = dma_trans_desc->src_add + i * period_len * (1<src_width);
-			break;
-		case DW_DMA_SLAVE_DEC:
-			temp_src_add = dma_trans_desc->src_add - i * period_len * (1<src_width);
-			break;
-		case DW_DMA_SLAVE_FIX:
-			temp_src_add = dma_trans_desc->src_add ;
-			break;
+        switch(dma_trans_desc->src_inc_mode){
+        case DW_DMA_SLAVE_INC:
+            temp_src_add = dma_trans_desc->src_add + i * period_len * (1<src_width);
+            break;
+        case DW_DMA_SLAVE_DEC:
+            temp_src_add = dma_trans_desc->src_add - i * period_len * (1<src_width);
+            break;
+        case DW_DMA_SLAVE_FIX:
+            temp_src_add = dma_trans_desc->src_add ;
+            break;
 
-		}
+        }
 
 
-		p_lli[i].sar = temp_src_add;
-		p_lli[i].dar = temp_dst_add;
+        p_lli[i].sar = temp_src_add;
+        p_lli[i].dar = temp_dst_add;
 
-		//para ctl
+        //para ctl
 
 
-		RT_ASSERT(dma_trans_desc->dst_width <=DW_DMA_SLAVE_WIDTH_32BIT);
-		RT_ASSERT(dma_trans_desc->src_width <=DW_DMA_SLAVE_WIDTH_32BIT);
+        RT_ASSERT(dma_trans_desc->dst_width <=DW_DMA_SLAVE_WIDTH_32BIT);
+        RT_ASSERT(dma_trans_desc->src_width <=DW_DMA_SLAVE_WIDTH_32BIT);
 
-		RT_ASSERT(dma_trans_desc->dst_msize <=DW_DMA_SLAVE_MSIZE_256);
-		RT_ASSERT(dma_trans_desc->src_msize <=DW_DMA_SLAVE_MSIZE_256);
-		RT_ASSERT(dma_trans_desc->fc_mode <=DMA_P2P);
+        RT_ASSERT(dma_trans_desc->dst_msize <=DW_DMA_SLAVE_MSIZE_256);
+        RT_ASSERT(dma_trans_desc->src_msize <=DW_DMA_SLAVE_MSIZE_256);
+        RT_ASSERT(dma_trans_desc->fc_mode <=DMA_P2P);
 
 
 
-		p_lli[i].ctllo = DWC_CTLL_INT_EN|DWC_CTLL_DST_WIDTH(dma_trans_desc->dst_width)|DWC_CTLL_SRC_WIDTH(dma_trans_desc->src_width)
-				|DWC_CTLL_DST_INC_MODE(dma_trans_desc->dst_inc_mode)|DWC_CTLL_SRC_INC_MODE(dma_trans_desc->src_inc_mode)
-				|DWC_CTLL_DST_MSIZE(dma_trans_desc->dst_msize)|DWC_CTLL_SRC_MSIZE(dma_trans_desc->src_msize)|DWC_CTLL_FC(dma_trans_desc->fc_mode)
-				|DWC_CTLL_DMS(0)|DWC_CTLL_SMS(0);
-		//block size
-		p_lli[i].ctlhi = period_len;
+        p_lli[i].ctllo = DWC_CTLL_INT_EN|DWC_CTLL_DST_WIDTH(dma_trans_desc->dst_width)|DWC_CTLL_SRC_WIDTH(dma_trans_desc->src_width)
+                |DWC_CTLL_DST_INC_MODE(dma_trans_desc->dst_inc_mode)|DWC_CTLL_SRC_INC_MODE(dma_trans_desc->src_inc_mode)
+                |DWC_CTLL_DST_MSIZE(dma_trans_desc->dst_msize)|DWC_CTLL_SRC_MSIZE(dma_trans_desc->src_msize)|DWC_CTLL_FC(dma_trans_desc->fc_mode)
+                |DWC_CTLL_DMS(0)|DWC_CTLL_SMS(0);
+        //block size
+        p_lli[i].ctlhi = period_len;
 
 
 
-		p_lli[i].llp = (uint32_t)&p_lli[i+1];
-		p_lli[i].ctllo |= DWC_CTLL_LLP_D_EN|DWC_CTLL_LLP_S_EN;
+        p_lli[i].llp = (uint32_t)&p_lli[i+1];
+        p_lli[i].ctllo |= DWC_CTLL_LLP_D_EN|DWC_CTLL_LLP_S_EN;
 
 
-		//flush cache to mem
-		mmu_clean_invalidated_dcache((uint32_t)&p_lli[i],sizeof(struct dw_lli));
+        //flush cache to mem
+        mmu_clean_invalidated_dcache((uint32_t)&p_lli[i],sizeof(struct dw_lli));
 
-		dump_lli(&p_lli[i]);
-	}
-	//make a ring here
-	p_lli[periods -1 ].llp = (uint32_t)&p_lli[0];
+        dump_lli(&p_lli[i]);
+    }
+    //make a ring here
+    p_lli[periods -1 ].llp = (uint32_t)&p_lli[0];
 
-	mmu_clean_invalidated_dcache((uint32_t)&p_lli[periods -1 ],sizeof(struct dw_lli));
+    mmu_clean_invalidated_dcache((uint32_t)&p_lli[periods -1 ],sizeof(struct dw_lli));
 
 
 
-	//parse the handshake
-	RT_ASSERT(dma_trans_desc->dst_hs <=	DMA_SW_HANDSHAKING);
-	RT_ASSERT(dma_trans_desc->src_hs <=	DMA_SW_HANDSHAKING);
+    //parse the handshake
+    RT_ASSERT(dma_trans_desc->dst_hs <= DMA_SW_HANDSHAKING);
+    RT_ASSERT(dma_trans_desc->src_hs <= DMA_SW_HANDSHAKING);
 
-	//dst handshake
-	dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,0);
-	ret_status = 0;
-	if(dma_trans_desc->dst_hs == DMA_SW_HANDSHAKING){
-		ret_status |= DWC_CFGL_HS_DST;
-	}
-	else{
-		ret_status &= ~DWC_CFGL_HS_DST;
-	}
-	dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status);
+    //dst handshake
+    dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,0);
+    ret_status = 0;
+    if(dma_trans_desc->dst_hs == DMA_SW_HANDSHAKING){
+        ret_status |= DWC_CFGL_HS_DST;
+    }
+    else{
+        ret_status &= ~DWC_CFGL_HS_DST;
+    }
+    dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status);
 
 
 
-	//src handshake
-	ret_status = dw_readl(dwc,CHAN[dma_trans_desc->channel_number].CFG_LO);
-	if(dma_trans_desc->src_hs == DMA_SW_HANDSHAKING){
-		ret_status |= DWC_CFGL_HS_SRC;
-	}
-	else{
-		ret_status &= ~DWC_CFGL_HS_SRC;
-	}
-	dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status);
+    //src handshake
+    ret_status = dw_readl(dwc,CHAN[dma_trans_desc->channel_number].CFG_LO);
+    if(dma_trans_desc->src_hs == DMA_SW_HANDSHAKING){
+        ret_status |= DWC_CFGL_HS_SRC;
+    }
+    else{
+        ret_status &= ~DWC_CFGL_HS_SRC;
+    }
+    dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_LO,ret_status);
 
 
-	//only hw handshaking need this..
-	switch(dma_trans_desc->fc_mode){
-	case	DMA_M2M:
-		break;
-	case	DMA_M2P:
-		//set dst per...
-		RT_ASSERT(dma_trans_desc->dst_per <	DMA_HW_HS_END);
-		ret_status = dw_readl(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI);
-		//clear 43 ~ 46 bit
-		ret_status &= ~0x7800;
-		ret_status |= DWC_CFGH_DST_PER(dma_trans_desc->dst_per);
-		dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status);
-		//DWC_CFGH_SRC_PER
+    //only hw handshaking need this..
+    switch(dma_trans_desc->fc_mode){
+    case    DMA_M2M:
+        break;
+    case    DMA_M2P:
+        //set dst per...
+        RT_ASSERT(dma_trans_desc->dst_per < DMA_HW_HS_END);
+        ret_status = dw_readl(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI);
+        //clear 43 ~ 46 bit
+        ret_status &= ~0x7800;
+        ret_status |= DWC_CFGH_DST_PER(dma_trans_desc->dst_per);
+        dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status);
+        //DWC_CFGH_SRC_PER
 
-		break;
-	case 	DMA_P2M:
-		//set src per...
-		RT_ASSERT(dma_trans_desc->src_per <	DMA_HW_HS_END);
-		ret_status = dw_readl(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI);
-		//clear 39 ~ 42 bit
-		ret_status &= ~0x780;
-		ret_status |= DWC_CFGH_SRC_PER(dma_trans_desc->src_per);
-		dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status);
+        break;
+    case    DMA_P2M:
+        //set src per...
+        RT_ASSERT(dma_trans_desc->src_per < DMA_HW_HS_END);
+        ret_status = dw_readl(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI);
+        //clear 39 ~ 42 bit
+        ret_status &= ~0x780;
+        ret_status |= DWC_CFGH_SRC_PER(dma_trans_desc->src_per);
+        dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status);
 
-		break;
-	case 	DMA_P2P:
-		//set src and dst..
-		RT_ASSERT(dma_trans_desc->dst_per <	DMA_HW_HS_END);
-		RT_ASSERT(dma_trans_desc->src_per <	DMA_HW_HS_END);
+        break;
+    case    DMA_P2P:
+        //set src and dst..
+        RT_ASSERT(dma_trans_desc->dst_per < DMA_HW_HS_END);
+        RT_ASSERT(dma_trans_desc->src_per < DMA_HW_HS_END);
 
-		ret_status = dw_readl(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI);
-		ret_status &= ~0x7800;
-		ret_status &= ~0x780;
-		ret_status |= DWC_CFGH_SRC_PER(dma_trans_desc->src_per) | DWC_CFGH_DST_PER(dma_trans_desc->dst_per);
-		dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status);
+        ret_status = dw_readl(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI);
+        ret_status &= ~0x7800;
+        ret_status &= ~0x780;
+        ret_status |= DWC_CFGH_SRC_PER(dma_trans_desc->src_per) | DWC_CFGH_DST_PER(dma_trans_desc->dst_per);
+        dw_writel(dwc,CHAN[dma_trans_desc->channel_number].CFG_HI,ret_status);
 
-		break;
-	default:
-		break;
-	}
+        break;
+    default:
+        break;
+    }
 
-	dma_trans_desc->dma_controller->dma_channel[dma_trans_desc->channel_number].channel_status = CHANNEL_STATUS_BUSY;
+    dma_trans_desc->dma_controller->dma_channel[dma_trans_desc->channel_number].channel_status = CHANNEL_STATUS_BUSY;
 
-	if(dma_trans_desc->prepare_callback){
-			dma_trans_desc->prepare_callback(dma_trans_desc->prepare_para);
-	}
+    if(dma_trans_desc->prepare_callback){
+            dma_trans_desc->prepare_callback(dma_trans_desc->prepare_para);
+    }
 
 }
 
 
 static void rt_fh_dma_cyclic_free(struct dma_transfer *p){
 
-	struct fh81_dma *my_own = p->dma_controller;
-	struct dw_dma *dwc;
-	dwc = &my_own->dwc;
-	volatile uint32_t ret_status;
-	struct dw_lli  *p_lli = RT_NULL;
-	p_lli = p->first_lli;
+    struct fh81_dma *my_own = p->dma_controller;
+    struct dw_dma *dwc;
+    dwc = &my_own->dwc;
+    volatile uint32_t ret_status;
+    struct dw_lli  *p_lli = RT_NULL;
+    p_lli = p->first_lli;
 
 
-	//close channel first..
-	channel_clear_bit(dwc, CH_EN, 1<<(p->channel_number));
+    //close channel first..
+    channel_clear_bit(dwc, CH_EN, 1<<(p->channel_number));
 
-	//check if close really
-	while (dw_readl(dwc, CH_EN) & 1<<(p->channel_number));
+    //check if close really
+    while (dw_readl(dwc, CH_EN) & 1<<(p->channel_number));
 
-	dw_writel(dwc, CLEAR.XFER, 1<<(p->channel_number));
-	dw_writel(dwc, CLEAR.BLOCK, 1<<(p->channel_number));
-	dw_writel(dwc, CLEAR.ERROR, 1<<(p->channel_number));
+    dw_writel(dwc, CLEAR.XFER, 1<<(p->channel_number));
+    dw_writel(dwc, CLEAR.BLOCK, 1<<(p->channel_number));
+    dw_writel(dwc, CLEAR.ERROR, 1<<(p->channel_number));
 
 
 
 
-	//rt_free(p->first_lli);
-	put_desc(my_own,p);
+    //rt_free(p->first_lli);
+    put_desc(my_own,p);
 
 }
 
 
 void rt_fh_dma_init(void){
-	fh81_dma_register(&fh81_dma_controller[0],"fh81_dma");
+    fh81_dma_register(&fh81_dma_controller[0],"fh81_dma");
 
 }
diff --git a/bsp/fh8620/drivers/fh_dma.h b/bsp/fh8620/drivers/fh_dma.h
index faceac2deb..477718d0a5 100644
--- a/bsp/fh8620/drivers/fh_dma.h
+++ b/bsp/fh8620/drivers/fh_dma.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,19 +18,19 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #ifndef FH_DMA_H_
 #define FH_DMA_H_
 
 
 /****************************************************************************
 * #include section
-*	add #include here if any
+*   add #include here if any
 ***************************************************************************/
 
 #include 
@@ -43,24 +43,24 @@
  *********************************/
 
 
-#define FH81_MAX_CHANNEL					(4)
-#define FH81_CHANNEL_MAX_TRANSFER_SIZE		(4095)
+#define FH81_MAX_CHANNEL                    (4)
+#define FH81_CHANNEL_MAX_TRANSFER_SIZE      (4095)
 
 
 
 
 enum DMA_HW_HS_MAP{
-	ACODEC_RX = 0,
-	ACODEC_TX,
-	SPI0_RX,
-	SPI0_TX,
-	SPI1_RX,
-	SPI1_TX,
-	UART0_RX,
-	UART0_TX,
-	UART1_RX,
-	UART1_TX,
-	DMA_HW_HS_END,
+    ACODEC_RX = 0,
+    ACODEC_TX,
+    SPI0_RX,
+    SPI0_TX,
+    SPI1_RX,
+    SPI1_TX,
+    UART0_RX,
+    UART0_TX,
+    UART1_RX,
+    UART1_TX,
+    DMA_HW_HS_END,
 };
 
 /*********************************
@@ -76,7 +76,7 @@ typedef void (*user_prepare)(void *prepare_para);
 
 
 
-/****************************		i'm cut-off line		************************************/
+/****************************       i'm cut-off line        ************************************/
 
 
 
@@ -88,128 +88,128 @@ struct fh81_dma;
 
 
 struct dw_lli {
-	/* values that are not changed by hardware */
-	rt_uint32_t	sar;
-	rt_uint32_t	dar;
-	rt_uint32_t	llp;		/* chain to next lli */
-	rt_uint32_t		ctllo;
-	/* values that may get written back: */
-	rt_uint32_t		ctlhi;
-	/* sstat and dstat can snapshot peripheral register state.
-	 * silicon config may discard either or both...
-	 */
-	rt_uint32_t		sstat;
-	rt_uint32_t		dstat;
-	rt_uint32_t reserve;
+    /* values that are not changed by hardware */
+    rt_uint32_t sar;
+    rt_uint32_t dar;
+    rt_uint32_t llp;        /* chain to next lli */
+    rt_uint32_t     ctllo;
+    /* values that may get written back: */
+    rt_uint32_t     ctlhi;
+    /* sstat and dstat can snapshot peripheral register state.
+     * silicon config may discard either or both...
+     */
+    rt_uint32_t     sstat;
+    rt_uint32_t     dstat;
+    rt_uint32_t reserve;
 
 };
 
 //transfer use below
 struct dma_transfer{
-	//this is private for the dma drive....app don't touch it,the driver will manger it
-	//link interface for more transfer to the controller...
-	rt_list_t transfer_list;
-	struct fh81_dma *dma_controller;
-	//this the mem add....the dma controller will load the setting to move data ....
-	//user don't touch it
-	struct dw_lli *first_lli;
-	rt_uint32_t lli_size;
-	//new add for allign get desc...
-	rt_uint32_t actual_lli_size;
+    //this is private for the dma drive....app don't touch it,the driver will manger it
+    //link interface for more transfer to the controller...
+    rt_list_t transfer_list;
+    struct fh81_dma *dma_controller;
+    //this the mem add....the dma controller will load the setting to move data ....
+    //user don't touch it
+    struct dw_lli *first_lli;
+    rt_uint32_t lli_size;
+    //new add for allign get desc...
+    rt_uint32_t actual_lli_size;
 
 
-	//user could set paras below~~~
-#define AUTO_FIND_CHANNEL		(0xff)
-	//transfer with which dma channel...if the data is 0xff, the driver will auto find a free channel.
-	rt_uint32_t		channel_number;
-	//which dma you want to use...for fh81....only 0!!!
-	rt_uint32_t		dma_number;
+    //user could set paras below~~~
+#define AUTO_FIND_CHANNEL       (0xff)
+    //transfer with which dma channel...if the data is 0xff, the driver will auto find a free channel.
+    rt_uint32_t     channel_number;
+    //which dma you want to use...for fh81....only 0!!!
+    rt_uint32_t     dma_number;
 
 
-	//user should set the para below
-#define	DMA_M2M 			(0)		//	MEM <=> MEM
-#define	DMA_M2P 			(1)		//	MEM => peripheral A
-#define	DMA_P2M 			(2)		//	MEM <= peripheral A
-#define	DMA_P2P 			(3)		//	peripheral A <=> peripheral B
-	rt_uint32_t			fc_mode;//ip->mem. mem->mem. mem->ip
+    //user should set the para below
+#define DMA_M2M             (0)     //  MEM <=> MEM
+#define DMA_M2P             (1)     //  MEM => peripheral A
+#define DMA_P2M             (2)     //  MEM <= peripheral A
+#define DMA_P2P             (3)     //  peripheral A <=> peripheral B
+    rt_uint32_t         fc_mode;//ip->mem. mem->mem. mem->ip
 
 
 
 
-#define DMA_HW_HANDSHAKING	(0)
-#define DMA_SW_HANDSHAKING	(1)
-	rt_uint32_t			src_hs;			//src
-	//if use hw handshaking ,you need to set the hw handshaking number, this SOC defined
-	rt_uint32_t			src_per;		//src hw handshake number
-	//rt_uint32_t			irq_mode;//for each transfer,irq maybe not same. suggest for the default(transfer isr)
+#define DMA_HW_HANDSHAKING  (0)
+#define DMA_SW_HANDSHAKING  (1)
+    rt_uint32_t         src_hs;         //src
+    //if use hw handshaking ,you need to set the hw handshaking number, this SOC defined
+    rt_uint32_t         src_per;        //src hw handshake number
+    //rt_uint32_t           irq_mode;//for each transfer,irq maybe not same. suggest for the default(transfer isr)
 
-#define	DW_DMA_SLAVE_WIDTH_8BIT 	(0)
-#define	DW_DMA_SLAVE_WIDTH_16BIT 	(1)
-#define	DW_DMA_SLAVE_WIDTH_32BIT 	(2)
-	rt_uint32_t			src_width;
+#define DW_DMA_SLAVE_WIDTH_8BIT     (0)
+#define DW_DMA_SLAVE_WIDTH_16BIT    (1)
+#define DW_DMA_SLAVE_WIDTH_32BIT    (2)
+    rt_uint32_t         src_width;
 
-	//the user should reference the hw handshaking watermark..
-#define DW_DMA_SLAVE_MSIZE_1		 (0)
-#define DW_DMA_SLAVE_MSIZE_4		 (1)
-#define DW_DMA_SLAVE_MSIZE_8		 (2)
-#define DW_DMA_SLAVE_MSIZE_16		 (3)
-#define DW_DMA_SLAVE_MSIZE_32		 (4)
-#define DW_DMA_SLAVE_MSIZE_64		 (5)
-#define DW_DMA_SLAVE_MSIZE_128		 (6)
-#define DW_DMA_SLAVE_MSIZE_256		 (7)
-	rt_uint32_t			src_msize;
-	rt_uint32_t			src_add;
-#define DW_DMA_SLAVE_INC		(0)
-#define DW_DMA_SLAVE_DEC		(1)
-#define DW_DMA_SLAVE_FIX		(2)
-	rt_uint32_t			src_inc_mode;	//increase mode: increase or not change
+    //the user should reference the hw handshaking watermark..
+#define DW_DMA_SLAVE_MSIZE_1         (0)
+#define DW_DMA_SLAVE_MSIZE_4         (1)
+#define DW_DMA_SLAVE_MSIZE_8         (2)
+#define DW_DMA_SLAVE_MSIZE_16        (3)
+#define DW_DMA_SLAVE_MSIZE_32        (4)
+#define DW_DMA_SLAVE_MSIZE_64        (5)
+#define DW_DMA_SLAVE_MSIZE_128       (6)
+#define DW_DMA_SLAVE_MSIZE_256       (7)
+    rt_uint32_t         src_msize;
+    rt_uint32_t         src_add;
+#define DW_DMA_SLAVE_INC        (0)
+#define DW_DMA_SLAVE_DEC        (1)
+#define DW_DMA_SLAVE_FIX        (2)
+    rt_uint32_t         src_inc_mode;   //increase mode: increase or not change
 
 
-//#define DMA_DST_HW_HANDSHAKING	(0)
-//#define DMA_DST_SW_HANDSHAKING	(1)
-	rt_uint32_t			dst_hs;			//src
-	//if use hw handshaking ,you need to set the hw handshaking number, this SOC defined
-	rt_uint32_t			dst_per;		//dst hw handshake number
-//#define	DW_DMA_SLAVE_WIDTH_8BIT 	(0)
-//#define	DW_DMA_SLAVE_WIDTH_16BIT 	(1)
-//#define	DW_DMA_SLAVE_WIDTH_32BIT 	(2)
-	rt_uint32_t			dst_width;
-//#define DW_DMA_SLAVE_MSIZE_1		 (0)
-//#define DW_DMA_SLAVE_MSIZE_4		 (1)
-//#define DW_DMA_SLAVE_MSIZE_8		 (2)
-//#define DW_DMA_SLAVE_MSIZE_16		 (3)
-//#define DW_DMA_SLAVE_MSIZE_32		 (4)
-//#define DW_DMA_SLAVE_MSIZE_64		 (5)
-//#define DW_DMA_SLAVE_MSIZE_128		 (6)
-//#define DW_DMA_SLAVE_MSIZE_256		 (7)
-	rt_uint32_t			dst_msize;
-	rt_uint32_t			dst_add;
-//#define DW_DMA_SLAVE_INC		(0)
-//#define DW_DMA_SLAVE_DEC		(1)
-//#define DW_DMA_SLAVE_FIX		(2)
-	rt_uint32_t			dst_inc_mode;	//increase mode: increase or not change
+//#define DMA_DST_HW_HANDSHAKING    (0)
+//#define DMA_DST_SW_HANDSHAKING    (1)
+    rt_uint32_t         dst_hs;         //src
+    //if use hw handshaking ,you need to set the hw handshaking number, this SOC defined
+    rt_uint32_t         dst_per;        //dst hw handshake number
+//#define   DW_DMA_SLAVE_WIDTH_8BIT     (0)
+//#define   DW_DMA_SLAVE_WIDTH_16BIT    (1)
+//#define   DW_DMA_SLAVE_WIDTH_32BIT    (2)
+    rt_uint32_t         dst_width;
+//#define DW_DMA_SLAVE_MSIZE_1       (0)
+//#define DW_DMA_SLAVE_MSIZE_4       (1)
+//#define DW_DMA_SLAVE_MSIZE_8       (2)
+//#define DW_DMA_SLAVE_MSIZE_16      (3)
+//#define DW_DMA_SLAVE_MSIZE_32      (4)
+//#define DW_DMA_SLAVE_MSIZE_64      (5)
+//#define DW_DMA_SLAVE_MSIZE_128         (6)
+//#define DW_DMA_SLAVE_MSIZE_256         (7)
+    rt_uint32_t         dst_msize;
+    rt_uint32_t         dst_add;
+//#define DW_DMA_SLAVE_INC      (0)
+//#define DW_DMA_SLAVE_DEC      (1)
+//#define DW_DMA_SLAVE_FIX      (2)
+    rt_uint32_t         dst_inc_mode;   //increase mode: increase or not change
 
 
-	//total sizes, unit: src_width/DW_DMA_SLAVE_WIDTH_8BIT...
-	//exg: src_width = DW_DMA_SLAVE_WIDTH_32BIT. trans_len = 2...means that: the dma will transfer 2*4 bytes..
-	//exg: src_width = DW_DMA_SLAVE_WIDTH_8BIT. trans_len = 6...means that: the dma will transfer 1*6 bytes..
-	rt_uint32_t			trans_len;
+    //total sizes, unit: src_width/DW_DMA_SLAVE_WIDTH_8BIT...
+    //exg: src_width = DW_DMA_SLAVE_WIDTH_32BIT. trans_len = 2...means that: the dma will transfer 2*4 bytes..
+    //exg: src_width = DW_DMA_SLAVE_WIDTH_8BIT. trans_len = 6...means that: the dma will transfer 1*6 bytes..
+    rt_uint32_t         trans_len;
 
 
 
-	//this is used when dma finish transfer job
-	dma_complete_callback complete_callback;
-	void				*complete_para; //for the driver data use the dma driver.
+    //this is used when dma finish transfer job
+    dma_complete_callback complete_callback;
+    void                *complete_para; //for the driver data use the dma driver.
 
 
-	//this is used when dma before work..the user maybe need to set his own private para..
-	user_prepare	prepare_callback;
-	void				*prepare_para;
+    //this is used when dma before work..the user maybe need to set his own private para..
+    user_prepare    prepare_callback;
+    void                *prepare_para;
 
 
-	//add cyclic para...
-	//period len..
-	rt_uint32_t period_len;
+    //add cyclic para...
+    //period len..
+    rt_uint32_t period_len;
 
 
 };
@@ -223,13 +223,13 @@ struct dma_transfer{
 
 /****************************************************************************
 * #define section
-*	add constant #define here if any
+*   add constant #define here if any
 ***************************************************************************/
 
 
 /****************************************************************************
 * ADT section
-*	add Abstract Data Type definition here
+*   add Abstract Data Type definition here
 ***************************************************************************/
 
 
@@ -240,7 +240,7 @@ struct dma_transfer{
 
 /****************************************************************************
 *  section
-*	add function prototype here if any
+*   add function prototype here if any
 ***************************************************************************/
 rt_err_t fh81_dma_register(struct fh81_dma * fh81_dma_p,
                              char * dma_name);
diff --git a/bsp/fh8620/drivers/gpio.c b/bsp/fh8620/drivers/gpio.c
index fc3fff639e..7a0dca36df 100644
--- a/bsp/fh8620/drivers/gpio.c
+++ b/bsp/fh8620/drivers/gpio.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
@@ -410,10 +410,10 @@ int fh_gpio_probe(void *priv_data)
     int i;
 
     if(gpio_obj->id == 0){
-    	  rt_hw_interrupt_install(gpio_obj->irq, fh_gpio_interrupt, (void *)gpio_obj, "gpio_0");
+          rt_hw_interrupt_install(gpio_obj->irq, fh_gpio_interrupt, (void *)gpio_obj, "gpio_0");
     }
     else if(gpio_obj->id == 1){
-    	rt_hw_interrupt_install(gpio_obj->irq, fh_gpio_interrupt, (void *)gpio_obj, "gpio_1");
+        rt_hw_interrupt_install(gpio_obj->irq, fh_gpio_interrupt, (void *)gpio_obj, "gpio_1");
     }
 
 
diff --git a/bsp/fh8620/drivers/gpio.h b/bsp/fh8620/drivers/gpio.h
index 7fe4d236b7..97b613871b 100644
--- a/bsp/fh8620/drivers/gpio.h
+++ b/bsp/fh8620/drivers/gpio.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #ifndef GPIO_H_
 #define GPIO_H_
 
diff --git a/bsp/fh8620/drivers/i2c.c b/bsp/fh8620/drivers/i2c.c
index 0f9636853d..66931666ea 100644
--- a/bsp/fh8620/drivers/i2c.c
+++ b/bsp/fh8620/drivers/i2c.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #include 
 #include 
 #include "i2c.h"
@@ -50,25 +50,25 @@ static void fh_i2c_xfer_init(struct rt_i2c_bus_device *dev, struct rt_i2c_msg ms
 {
     struct i2c_driver *i2c_drv = (struct i2c_driver *)dev->priv;
     struct fh_i2c_obj *i2c_obj = (struct fh_i2c_obj *)i2c_drv->priv;
-	rt_uint32_t ic_con;
+    rt_uint32_t ic_con;
 
-	/* if the slave address is ten bit address, ERROR*/
+    /* if the slave address is ten bit address, ERROR*/
     if (msgs[i2c_drv->msg_write_idx].flags & I2C_M_TEN)
     {
         rt_kprintf("ERROR: %s, ten bit address is NOT supported\n", __func__);
         return;
     }
 
-	/* Disable the adapter */
-	I2C_WaitMasterIdle(i2c_obj);
+    /* Disable the adapter */
+    I2C_WaitMasterIdle(i2c_obj);
 
-	I2C_Enable(i2c_obj, RT_FALSE);
+    I2C_Enable(i2c_obj, RT_FALSE);
 
-	/* set the slave (target) address */
-	I2C_SetSlaveAddress(i2c_obj, msgs[i2c_drv->msg_write_idx].addr);
+    /* set the slave (target) address */
+    I2C_SetSlaveAddress(i2c_obj, msgs[i2c_drv->msg_write_idx].addr);
 
-	/* Enable interrupts */
-	I2C_SetInterruptMask(i2c_obj, DW_IC_INTR_DEFAULT_MASK);
+    /* Enable interrupts */
+    I2C_SetInterruptMask(i2c_obj, DW_IC_INTR_DEFAULT_MASK);
 
     /* Enable the adapter */
     I2C_Enable(i2c_obj, RT_TRUE);
@@ -76,30 +76,30 @@ static void fh_i2c_xfer_init(struct rt_i2c_bus_device *dev, struct rt_i2c_msg ms
 
 
 static rt_size_t fh_i2c_xfer(struct rt_i2c_bus_device *dev,
-		struct rt_i2c_msg msgs[], rt_uint32_t num)
+        struct rt_i2c_msg msgs[], rt_uint32_t num)
 {
     struct i2c_driver *i2c_drv = (struct i2c_driver *)dev->priv;
     struct fh_i2c_obj *i2c_obj = (struct fh_i2c_obj *)i2c_drv->priv;
     int ret;
-	struct rt_i2c_msg *pmsg = RT_NULL;
+    struct rt_i2c_msg *pmsg = RT_NULL;
 
-	PRINT_I2C_DBG(">>>>>>>>>>>>>%s start\n", __func__);
+    PRINT_I2C_DBG(">>>>>>>>>>>>>%s start\n", __func__);
 
     rt_completion_init(&i2c_drv->transfer_completion);
 
     ret = rt_mutex_take(i2c_drv->lock, RT_WAITING_FOREVER);
-	if (ret != RT_EOK) {
-		goto done;
-	}
+    if (ret != RT_EOK) {
+        goto done;
+    }
 
-	i2c_drv->msgs = msgs;
-	i2c_drv->msgs_num = num;
-	i2c_drv->msg_read_idx = 0;
-	i2c_drv->msg_write_idx = 0;
-	i2c_drv->cmd_err = 0;
-	i2c_drv->msg_err = 0;
-	i2c_drv->status = STATUS_IDLE;
-	i2c_obj->abort_source = 0;
+    i2c_drv->msgs = msgs;
+    i2c_drv->msgs_num = num;
+    i2c_drv->msg_read_idx = 0;
+    i2c_drv->msg_write_idx = 0;
+    i2c_drv->cmd_err = 0;
+    i2c_drv->msg_err = 0;
+    i2c_drv->status = STATUS_IDLE;
+    i2c_obj->abort_source = 0;
 
     ret = I2C_WaitDeviceIdle(i2c_obj);
     if (ret < 0)
@@ -108,51 +108,51 @@ static rt_size_t fh_i2c_xfer(struct rt_i2c_bus_device *dev,
         //goto done;
     }
 
-	fh_i2c_xfer_init(dev, msgs, num);
+    fh_i2c_xfer_init(dev, msgs, num);
 
-	ret = rt_completion_wait(&i2c_drv->transfer_completion, RT_TICK_PER_SECOND);
-	PRINT_I2C_DBG("%s transfer finished\n", "rt_completion_wait");
+    ret = rt_completion_wait(&i2c_drv->transfer_completion, RT_TICK_PER_SECOND);
+    PRINT_I2C_DBG("%s transfer finished\n", "rt_completion_wait");
     if(ret)
-	{
+    {
         rt_kprintf("ERROR: %s, transfer timeout\n", __func__);
         I2C_SetDataCmd(i2c_obj, 0x200);
         I2C_Init(i2c_obj);
-		ret = -RT_ETIMEOUT;
-		goto done;
-	}
+        ret = -RT_ETIMEOUT;
+        goto done;
+    }
 
-	if (i2c_drv->msg_err)
-	{
-		rt_kprintf("i2c_priv->msg_err: %d\n", i2c_drv->msg_err);
-		ret = i2c_drv->msg_err;
-		goto done;
-	}
+    if (i2c_drv->msg_err)
+    {
+        rt_kprintf("i2c_priv->msg_err: %d\n", i2c_drv->msg_err);
+        ret = i2c_drv->msg_err;
+        goto done;
+    }
 
-	/* no error */
-	if (!i2c_drv->cmd_err)
-	{
-		/* Disable the adapter */
-	    I2C_WaitMasterIdle(i2c_obj);
-	    I2C_Enable(i2c_obj, RT_FALSE);
-		ret = num;
-		goto done;
-	}
+    /* no error */
+    if (!i2c_drv->cmd_err)
+    {
+        /* Disable the adapter */
+        I2C_WaitMasterIdle(i2c_obj);
+        I2C_Enable(i2c_obj, RT_FALSE);
+        ret = num;
+        goto done;
+    }
 
-	/* We have an error */
-	if (i2c_drv->cmd_err == DW_IC_ERR_TX_ABRT)
-	{
-		rt_kprintf("ERROR: %s, i2c_priv>cmd_err == DW_IC_ERR_TX_ABRT\n", __func__);
-		ret = I2C_HandleTxAbort(i2c_obj);
-		goto done;
-	}
+    /* We have an error */
+    if (i2c_drv->cmd_err == DW_IC_ERR_TX_ABRT)
+    {
+        rt_kprintf("ERROR: %s, i2c_priv>cmd_err == DW_IC_ERR_TX_ABRT\n", __func__);
+        ret = I2C_HandleTxAbort(i2c_obj);
+        goto done;
+    }
 
-	ret = 1;
+    ret = 1;
 
 done:
     I2C_Enable(i2c_obj, RT_FALSE);
     rt_mutex_release(i2c_drv->lock);
     PRINT_I2C_DBG(">>>>>>>>>>>>>%s end\n", __func__);
-	return ret;
+    return ret;
 
 }
 
@@ -167,164 +167,164 @@ static void i2c_fh_xfer_msg(struct rt_i2c_bus_device *dev)
 {
     struct i2c_driver *i2c_drv = (struct i2c_driver *)dev->priv;
     struct fh_i2c_obj *i2c_obj = (struct fh_i2c_obj *)i2c_drv->priv;
-	struct rt_i2c_msg *msgs = i2c_drv->msgs;
-	rt_uint32_t intr_mask, cmd;
-	int tx_limit, rx_limit;
-	rt_uint32_t addr = msgs[i2c_drv->msg_write_idx].addr;
-	rt_uint32_t buf_len = i2c_drv->tx_buf_len;
-	rt_uint8_t *buf = i2c_drv->tx_buf;
+    struct rt_i2c_msg *msgs = i2c_drv->msgs;
+    rt_uint32_t intr_mask, cmd;
+    int tx_limit, rx_limit;
+    rt_uint32_t addr = msgs[i2c_drv->msg_write_idx].addr;
+    rt_uint32_t buf_len = i2c_drv->tx_buf_len;
+    rt_uint8_t *buf = i2c_drv->tx_buf;
 
-	PRINT_I2C_DBG("%s start, msgs_num: %d, write_idx: %d\n", __func__, i2c_drv->msgs_num, i2c_drv->msg_write_idx);
+    PRINT_I2C_DBG("%s start, msgs_num: %d, write_idx: %d\n", __func__, i2c_drv->msgs_num, i2c_drv->msg_write_idx);
 
-	intr_mask = DW_IC_INTR_DEFAULT_MASK;
+    intr_mask = DW_IC_INTR_DEFAULT_MASK;
 
-	for (; i2c_drv->msg_write_idx < i2c_drv->msgs_num; i2c_drv->msg_write_idx++)
-	{
-		/*
-		 * if target address has changed, we need to
-		 * reprogram the target address in the i2c
-		 * adapter when we are done with this transfer
-		 */
-		if (msgs[i2c_drv->msg_write_idx].addr != addr) {
-			rt_kprintf(
-					"ERROR: %s, invalid target address\n", __func__);
-			i2c_drv->msg_err = 1;
-			break;
-		}
+    for (; i2c_drv->msg_write_idx < i2c_drv->msgs_num; i2c_drv->msg_write_idx++)
+    {
+        /*
+         * if target address has changed, we need to
+         * reprogram the target address in the i2c
+         * adapter when we are done with this transfer
+         */
+        if (msgs[i2c_drv->msg_write_idx].addr != addr) {
+            rt_kprintf(
+                    "ERROR: %s, invalid target address\n", __func__);
+            i2c_drv->msg_err = 1;
+            break;
+        }
 
-		if (msgs[i2c_drv->msg_write_idx].len == 0) {
-			rt_kprintf(
-					"ERROR: %s, invalid message length\n", __func__);
-			i2c_drv->msg_err = 1;
-			break;
-		}
+        if (msgs[i2c_drv->msg_write_idx].len == 0) {
+            rt_kprintf(
+                    "ERROR: %s, invalid message length\n", __func__);
+            i2c_drv->msg_err = 1;
+            break;
+        }
 
-		if (!(i2c_drv->status & STATUS_WRITE_IN_PROGRESS))
-		{
-			/* new i2c_msg */
-			buf = msgs[i2c_drv->msg_write_idx].buf;
-			buf_len = msgs[i2c_drv->msg_write_idx].len;
+        if (!(i2c_drv->status & STATUS_WRITE_IN_PROGRESS))
+        {
+            /* new i2c_msg */
+            buf = msgs[i2c_drv->msg_write_idx].buf;
+            buf_len = msgs[i2c_drv->msg_write_idx].len;
 
-			PRINT_I2C_DBG("new msg: len: %d, buf: 0x%x\n", buf_len, buf[0]);
-		}
+            PRINT_I2C_DBG("new msg: len: %d, buf: 0x%x\n", buf_len, buf[0]);
+        }
 
-		tx_limit = i2c_obj->config.tx_fifo_depth - I2C_GetTransmitFifoLevel(i2c_obj);
-		rx_limit = i2c_obj->config.rx_fifo_depth - I2C_GetReceiveFifoLevel(i2c_obj);
+        tx_limit = i2c_obj->config.tx_fifo_depth - I2C_GetTransmitFifoLevel(i2c_obj);
+        rx_limit = i2c_obj->config.rx_fifo_depth - I2C_GetReceiveFifoLevel(i2c_obj);
 
-		while (buf_len > 0 && tx_limit > 0 && rx_limit > 0)
-		{
-			if (msgs[i2c_drv->msg_write_idx].flags & RT_I2C_RD)
-			{
-				cmd = 0x100;
-				rx_limit--;
-			}
-			else
-			{
-				cmd = *buf++;
-			}
+        while (buf_len > 0 && tx_limit > 0 && rx_limit > 0)
+        {
+            if (msgs[i2c_drv->msg_write_idx].flags & RT_I2C_RD)
+            {
+                cmd = 0x100;
+                rx_limit--;
+            }
+            else
+            {
+                cmd = *buf++;
+            }
 
-			tx_limit--; buf_len--;
+            tx_limit--; buf_len--;
 
-			if(!buf_len)
-			{
-			    //2015-11-8 ar0130 bug fixed
-			    while(I2C_GetTransmitFifoLevel(i2c_obj));
-			    cmd |= 0x200;
-			}
+            if(!buf_len)
+            {
+                //2015-11-8 ar0130 bug fixed
+                while(I2C_GetTransmitFifoLevel(i2c_obj));
+                cmd |= 0x200;
+            }
 
-			I2C_SetDataCmd(i2c_obj, cmd);
-		}
+            I2C_SetDataCmd(i2c_obj, cmd);
+        }
 
-		i2c_drv->tx_buf = buf;
-		i2c_drv->tx_buf_len = buf_len;
+        i2c_drv->tx_buf = buf;
+        i2c_drv->tx_buf_len = buf_len;
 
-		if (buf_len > 0)
-		{
-			/* more bytes to be written */
-		    i2c_drv->status |= STATUS_WRITE_IN_PROGRESS;
-			break;
-		}
-		else
-		{
-		    i2c_drv->status &= ~STATUS_WRITE_IN_PROGRESS;
-		}
-	}
+        if (buf_len > 0)
+        {
+            /* more bytes to be written */
+            i2c_drv->status |= STATUS_WRITE_IN_PROGRESS;
+            break;
+        }
+        else
+        {
+            i2c_drv->status &= ~STATUS_WRITE_IN_PROGRESS;
+        }
+    }
 
-	/*
-	 * If i2c_msg index search is completed, we don't need TX_EMPTY
-	 * interrupt any more.
-	 */
+    /*
+     * If i2c_msg index search is completed, we don't need TX_EMPTY
+     * interrupt any more.
+     */
 
-	if (i2c_drv->msg_write_idx == i2c_drv->msgs_num)
-	    intr_mask &= ~DW_IC_INTR_TX_EMPTY;
+    if (i2c_drv->msg_write_idx == i2c_drv->msgs_num)
+        intr_mask &= ~DW_IC_INTR_TX_EMPTY;
 
-	if (i2c_drv->msg_err)
-	{
-	    rt_kprintf("ERROR: %s, msg_err: %d\n", __func__, i2c_drv->msg_err);
-	    intr_mask = 0;
-	}
+    if (i2c_drv->msg_err)
+    {
+        rt_kprintf("ERROR: %s, msg_err: %d\n", __func__, i2c_drv->msg_err);
+        intr_mask = 0;
+    }
 
-	I2C_SetInterruptMask(i2c_obj, intr_mask);
+    I2C_SetInterruptMask(i2c_obj, intr_mask);
 
-	PRINT_I2C_DBG("%s end\n", __func__);
+    PRINT_I2C_DBG("%s end\n", __func__);
 }
 
 static void i2c_fh_read(struct rt_i2c_bus_device *dev)
 {
-	struct i2c_driver *i2c_drv = (struct i2c_driver *)dev->priv;
-	struct fh_i2c_obj *i2c_obj = (struct fh_i2c_obj *)i2c_drv->priv;
-	struct rt_i2c_msg *msgs = i2c_drv->msgs;
-	int rx_valid;
+    struct i2c_driver *i2c_drv = (struct i2c_driver *)dev->priv;
+    struct fh_i2c_obj *i2c_obj = (struct fh_i2c_obj *)i2c_drv->priv;
+    struct rt_i2c_msg *msgs = i2c_drv->msgs;
+    int rx_valid;
 
-	PRINT_I2C_DBG("%s start, msgs_num: %d, read_idx: %d\n", __func__, i2c_drv->msgs_num, i2c_drv->msg_read_idx);
+    PRINT_I2C_DBG("%s start, msgs_num: %d, read_idx: %d\n", __func__, i2c_drv->msgs_num, i2c_drv->msg_read_idx);
 
-	for (; i2c_drv->msg_read_idx < i2c_drv->msgs_num; i2c_drv->msg_read_idx++)
-	{
-		rt_uint32_t len;
-		rt_uint8_t *buf;
+    for (; i2c_drv->msg_read_idx < i2c_drv->msgs_num; i2c_drv->msg_read_idx++)
+    {
+        rt_uint32_t len;
+        rt_uint8_t *buf;
 
-		if (!(msgs[i2c_drv->msg_read_idx].flags & RT_I2C_RD))
-		    continue;
+        if (!(msgs[i2c_drv->msg_read_idx].flags & RT_I2C_RD))
+            continue;
 
-		if (!(i2c_drv->status & STATUS_READ_IN_PROGRESS))
-		{
-			len = msgs[i2c_drv->msg_read_idx].len;
-			buf = msgs[i2c_drv->msg_read_idx].buf;
-		}
-		else
-		{
-		    PRINT_I2C_DBG("STATUS_READ_IN_PROGRESS\n");
-			len = i2c_drv->rx_buf_len;
-			buf = i2c_drv->rx_buf;
-		}
+        if (!(i2c_drv->status & STATUS_READ_IN_PROGRESS))
+        {
+            len = msgs[i2c_drv->msg_read_idx].len;
+            buf = msgs[i2c_drv->msg_read_idx].buf;
+        }
+        else
+        {
+            PRINT_I2C_DBG("STATUS_READ_IN_PROGRESS\n");
+            len = i2c_drv->rx_buf_len;
+            buf = i2c_drv->rx_buf;
+        }
 
-		rx_valid = I2C_GetReceiveFifoLevel(i2c_obj);
+        rx_valid = I2C_GetReceiveFifoLevel(i2c_obj);
 
-		if(rx_valid == 0)
-		{
-			rt_kprintf("ERROR: %s, rx_valid == 0\n", __func__);
-		}
-		PRINT_I2C_DBG("%s, len=%d, rx_valid=%d\n", __func__, len, rx_valid);
-		for (; len > 0 && rx_valid > 0; len--, rx_valid--)
-		{
-			*buf++ = I2C_GetData(i2c_obj);
-		}
+        if(rx_valid == 0)
+        {
+            rt_kprintf("ERROR: %s, rx_valid == 0\n", __func__);
+        }
+        PRINT_I2C_DBG("%s, len=%d, rx_valid=%d\n", __func__, len, rx_valid);
+        for (; len > 0 && rx_valid > 0; len--, rx_valid--)
+        {
+            *buf++ = I2C_GetData(i2c_obj);
+        }
 
-		PRINT_I2C_DBG("i2c_fh_read, len: %d, buf[0]: 0x%x\n", msgs[i2c_drv->msg_read_idx].len, msgs[i2c_drv->msg_read_idx].buf[0]);
+        PRINT_I2C_DBG("i2c_fh_read, len: %d, buf[0]: 0x%x\n", msgs[i2c_drv->msg_read_idx].len, msgs[i2c_drv->msg_read_idx].buf[0]);
 
-		if (len > 0)
-		{
-		    PRINT_I2C_DBG("len > 0\n");
-			i2c_drv->status |= STATUS_READ_IN_PROGRESS;
-			i2c_drv->rx_buf_len = len;
-			i2c_drv->rx_buf = buf;
-			return;
-		}
-		else
-		    i2c_drv->status &= ~STATUS_READ_IN_PROGRESS;
-	}
+        if (len > 0)
+        {
+            PRINT_I2C_DBG("len > 0\n");
+            i2c_drv->status |= STATUS_READ_IN_PROGRESS;
+            i2c_drv->rx_buf_len = len;
+            i2c_drv->rx_buf = buf;
+            return;
+        }
+        else
+            i2c_drv->status &= ~STATUS_READ_IN_PROGRESS;
+    }
 
-	PRINT_I2C_DBG("%s end\n", __func__);
+    PRINT_I2C_DBG("%s end\n", __func__);
 }
 
 /*
@@ -336,44 +336,44 @@ static void fh_i2c_interrupt(int this_irq, void *dev_id)
     struct i2c_driver *i2c_drv = dev_id;
     struct rt_i2c_bus_device *i2c_bus_dev = i2c_drv->i2c_bus_dev;
     struct fh_i2c_obj *i2c_obj = (struct fh_i2c_obj *)i2c_drv->priv;
-	rt_uint32_t stat;
+    rt_uint32_t stat;
 
-	stat = I2C_ClearAndGetInterrupts(i2c_obj);
-	PRINT_I2C_DBG("status: 0x%x, mask: 0x%x\n", stat, I2C_GetInterruptMask(i2c_obj));
+    stat = I2C_ClearAndGetInterrupts(i2c_obj);
+    PRINT_I2C_DBG("status: 0x%x, mask: 0x%x\n", stat, I2C_GetInterruptMask(i2c_obj));
 
-	if (stat & DW_IC_INTR_TX_ABRT)
-	{
-	    PRINT_I2C_DBG("DW_IC_INTR_TX_ABRT\n");
-		i2c_drv->cmd_err |= DW_IC_ERR_TX_ABRT;
-		i2c_drv->status = STATUS_IDLE;
+    if (stat & DW_IC_INTR_TX_ABRT)
+    {
+        PRINT_I2C_DBG("DW_IC_INTR_TX_ABRT\n");
+        i2c_drv->cmd_err |= DW_IC_ERR_TX_ABRT;
+        i2c_drv->status = STATUS_IDLE;
 
-		/*
-		 * Anytime TX_ABRT is set, the contents of the tx/rx
-		 * buffers are flushed.  Make sure to skip them.
-		 */
-		I2C_SetInterruptMask(i2c_obj, 0);
-		goto tx_aborted;
-	}
+        /*
+         * Anytime TX_ABRT is set, the contents of the tx/rx
+         * buffers are flushed.  Make sure to skip them.
+         */
+        I2C_SetInterruptMask(i2c_obj, 0);
+        goto tx_aborted;
+    }
 
-	if (stat & DW_IC_INTR_RX_FULL)
-	{
-		i2c_fh_read(i2c_bus_dev);
-	}
+    if (stat & DW_IC_INTR_RX_FULL)
+    {
+        i2c_fh_read(i2c_bus_dev);
+    }
 
-	if (stat & DW_IC_INTR_TX_EMPTY)
-	{
-		i2c_fh_xfer_msg(i2c_bus_dev);
-	}
+    if (stat & DW_IC_INTR_TX_EMPTY)
+    {
+        i2c_fh_xfer_msg(i2c_bus_dev);
+    }
 
-	/*
-	 * No need to modify or disable the interrupt mask here.
-	 * i2c_fh_xfer_msg() will take care of it according to
-	 * the current transmit status.
-	 */
+    /*
+     * No need to modify or disable the interrupt mask here.
+     * i2c_fh_xfer_msg() will take care of it according to
+     * the current transmit status.
+     */
 
 tx_aborted:
-	if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || i2c_drv->msg_err)
-	    rt_completion_done(&i2c_drv->transfer_completion);
+    if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || i2c_drv->msg_err)
+        rt_completion_done(&i2c_drv->transfer_completion);
 
 }
 
@@ -464,64 +464,64 @@ void rt_hw_i2c_init(void)
 }
 
 static rt_err_t fh_i2c_read_reg(struct rt_i2c_bus_device *fh81_i2c,
-		rt_uint16_t reg, rt_uint8_t *data) {
-	struct rt_i2c_msg msg[2];
-	rt_uint8_t send_buf[2];
-	rt_uint8_t recv_buf[1] = {0};
+        rt_uint16_t reg, rt_uint8_t *data) {
+    struct rt_i2c_msg msg[2];
+    rt_uint8_t send_buf[2];
+    rt_uint8_t recv_buf[1] = {0};
 
-	PRINT_I2C_DBG("%s start\n", __func__);
+    PRINT_I2C_DBG("%s start\n", __func__);
 
-	//  send_buf[0] = ((reg >> 8) & 0xff);
-	send_buf[0] = (reg & 0xFF);
+    //  send_buf[0] = ((reg >> 8) & 0xff);
+    send_buf[0] = (reg & 0xFF);
 
-	msg[0].addr = 0x51;
-	msg[0].flags = RT_I2C_WR;
-	msg[0].len = 1;
-	msg[0].buf = send_buf;
+    msg[0].addr = 0x51;
+    msg[0].flags = RT_I2C_WR;
+    msg[0].len = 1;
+    msg[0].buf = send_buf;
 
-	msg[1].addr = 0x51;
-	msg[1].flags = RT_I2C_RD;
-	msg[1].len = 1;
-	msg[1].buf = recv_buf;
+    msg[1].addr = 0x51;
+    msg[1].flags = RT_I2C_RD;
+    msg[1].len = 1;
+    msg[1].buf = recv_buf;
 
-	rt_i2c_transfer(fh81_i2c, msg, 2);
-	*data = recv_buf[0];
-	return RT_EOK;
+    rt_i2c_transfer(fh81_i2c, msg, 2);
+    *data = recv_buf[0];
+    return RT_EOK;
 }
 static rt_err_t fh_i2c_write_reg(struct rt_i2c_bus_device *fh81_i2c,
-		rt_uint16_t reg, rt_uint8_t data) {
-	struct rt_i2c_msg msg;
-	rt_uint8_t send_buf[3];
+        rt_uint16_t reg, rt_uint8_t data) {
+    struct rt_i2c_msg msg;
+    rt_uint8_t send_buf[3];
 
-	PRINT_I2C_DBG("%s start\n", __func__);
+    PRINT_I2C_DBG("%s start\n", __func__);
 
-	// send_buf[0] = ((reg >> 8) & 0xff);
-	send_buf[1] = (reg & 0xFF);
-	send_buf[2] = data;
+    // send_buf[0] = ((reg >> 8) & 0xff);
+    send_buf[1] = (reg & 0xFF);
+    send_buf[2] = data;
 
-	msg.addr = 0x51;
-	msg.flags = RT_I2C_WR;
-	msg.len = 2;
-	msg.buf = send_buf;
+    msg.addr = 0x51;
+    msg.flags = RT_I2C_WR;
+    msg.len = 2;
+    msg.buf = send_buf;
 
-	rt_i2c_transfer(fh81_i2c, &msg, 1);
-	PRINT_I2C_DBG("%s end\n", __func__);
-	return RT_EOK;
+    rt_i2c_transfer(fh81_i2c, &msg, 1);
+    PRINT_I2C_DBG("%s end\n", __func__);
+    return RT_EOK;
 }
 
 void i2c_test_sensor() {
-	struct rt_i2c_bus_device *fh81_i2c;
-	struct rt_i2c_msg msg[2];
-	rt_uint8_t data[1] = { 0x00 };
+    struct rt_i2c_bus_device *fh81_i2c;
+    struct rt_i2c_msg msg[2];
+    rt_uint8_t data[1] = { 0x00 };
 
-	fh81_i2c = rt_i2c_bus_device_find("i2c1");
+    fh81_i2c = rt_i2c_bus_device_find("i2c1");
 
-	fh_i2c_write_reg(fh81_i2c, 0x04, 0x02);
+    fh_i2c_write_reg(fh81_i2c, 0x04, 0x02);
 
-	fh_i2c_read_reg(fh81_i2c, 0x02, data);
+    fh_i2c_read_reg(fh81_i2c, 0x02, data);
 
-	rt_kprintf("data read from 0x3038 is 0x%x\r\n", data[0]);
-	PRINT_I2C_DBG("%s end\n", __func__);
+    rt_kprintf("data read from 0x3038 is 0x%x\r\n", data[0]);
+    PRINT_I2C_DBG("%s end\n", __func__);
 }
 #ifdef RT_USING_FINSH
 #include 
diff --git a/bsp/fh8620/drivers/i2c.h b/bsp/fh8620/drivers/i2c.h
index 9046bd81cb..15e4d7e8f2 100644
--- a/bsp/fh8620/drivers/i2c.h
+++ b/bsp/fh8620/drivers/i2c.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/fh8620/drivers/interrupt.c b/bsp/fh8620/drivers/interrupt.c
index ab522fab70..4cb250d8e5 100644
--- a/bsp/fh8620/drivers/interrupt.c
+++ b/bsp/fh8620/drivers/interrupt.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
@@ -105,10 +105,10 @@ void rt_hw_interrupt_init(void)
 {
     rt_int32_t i;
     register rt_uint32_t idx;
-	fh_intc *p = (fh_intc *)INTC_REG_BASE;
+    fh_intc *p = (fh_intc *)INTC_REG_BASE;
 
 
-	ictl_close_all_isr(p);
+    ictl_close_all_isr(p);
     /* init exceptions table */
     for(idx=0; idx < MAX_HANDLERS; idx++)
     {
@@ -137,27 +137,27 @@ void rt_hw_interrupt_init(void)
 void rt_hw_interrupt_mask(int irq)
 {
 
-	fh_intc *p = (fh_intc *)INTC_REG_BASE;
+    fh_intc *p = (fh_intc *)INTC_REG_BASE;
     /* Disable irq on AIC */
-	ictl_mask_isr(p,irq);
+    ictl_mask_isr(p,irq);
 
-//	if (irq < 32)
-//    	p->IRQ_EN_L &= ~(1 << irq);
-//	else
-//		p->IRQ_EN_H &= ~(1 << (irq - 32));
+//  if (irq < 32)
+//      p->IRQ_EN_L &= ~(1 << irq);
+//  else
+//      p->IRQ_EN_H &= ~(1 << (irq - 32));
 }
 
 
 void rt_hw_interrupt_umask(int irq)
 {
 
-	fh_intc *p = (fh_intc *)INTC_REG_BASE;
+    fh_intc *p = (fh_intc *)INTC_REG_BASE;
     /* Enable irq on AIC */
-	ictl_unmask_isr(p,irq);
+    ictl_unmask_isr(p,irq);
 //    if (irq < 32)
-//    	p->IRQ_EN_L |= 1 << irq;
-//	else
-//		p->IRQ_EN_H |= 1 << (irq - 32);
+//      p->IRQ_EN_L |= 1 << irq;
+//  else
+//      p->IRQ_EN_H |= 1 << (irq - 32);
 }
 
 /**
@@ -168,7 +168,7 @@ void rt_hw_interrupt_umask(int irq)
  * @param name the interrupt name
  * @return old handler
  */
-rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, 
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
                                     void *param, const char *name)
 {
     rt_isr_handler_t old_handler = RT_NULL;
@@ -182,7 +182,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
             irq_desc[vector].param = param;
 #ifdef RT_USING_INTERRUPT_INFO
             rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
-			irq_desc[vector].counter = 0;
+            irq_desc[vector].counter = 0;
 #endif
         }
     }
@@ -195,7 +195,7 @@ void list_irq(void)
 {
 
 #ifdef RT_USING_INTERRUPT_INFO
-	int irq;
+    int irq;
     rt_kprintf("number\tcount\tname\n");
     for (irq = 0; irq < MAX_HANDLERS; irq++)
     {
diff --git a/bsp/fh8620/drivers/interrupt.h b/bsp/fh8620/drivers/interrupt.h
index fd4283b95c..6f62b0d95a 100644
--- a/bsp/fh8620/drivers/interrupt.h
+++ b/bsp/fh8620/drivers/interrupt.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
@@ -35,6 +35,6 @@ void rt_hw_interrupt_init(void);
 void rt_hw_interrupt_mask(int irq);
 void rt_hw_interrupt_umask(int irq);
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-		void *param, const char *name);
+        void *param, const char *name);
 
 #endif /* INTERRUPT_H_ */
diff --git a/bsp/fh8620/drivers/mem_process.c b/bsp/fh8620/drivers/mem_process.c
index 4ef7e2d599..e1424bd6ac 100644
--- a/bsp/fh8620/drivers/mem_process.c
+++ b/bsp/fh8620/drivers/mem_process.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
@@ -28,52 +28,52 @@
 #include 
 #include "mmu.h"
 
-#define CHANGLINE_SIZE		(1)
+#define CHANGLINE_SIZE      (1)
 
 //#define FH_DBG_MEM_PROCESS
 
 #ifdef FH_DBG_MEM_PROCESS
 void mem_input(rt_uint32_t t_addr, rt_uint32_t t_size, rt_uint8_t t_value) {
 
-	rt_kprintf("mem process add:%x \tsize:%x\tvalue:%x\n", t_addr, t_size,
-			t_value);
+    rt_kprintf("mem process add:%x \tsize:%x\tvalue:%x\n", t_addr, t_size,
+            t_value);
 
-	rt_memset((void *) t_addr, t_value, t_size);
+    rt_memset((void *) t_addr, t_value, t_size);
 
-	mmu_clean_invalidated_dcache(t_addr, t_size);
+    mmu_clean_invalidated_dcache(t_addr, t_size);
 
 }
 
 void mem_output(rt_uint32_t t_addr, rt_uint32_t t_size) {
 
-	rt_uint32_t i;
-	rt_uint32_t cnt = 0;
-	rt_uint32_t value;
-	rt_uint32_t addr, size;
+    rt_uint32_t i;
+    rt_uint32_t cnt = 0;
+    rt_uint32_t value;
+    rt_uint32_t addr, size;
 
-	addr = t_addr;
-	if (t_size % 4) {
-		rt_kprintf("mem must be alligned\n");
-	}
-	size = t_size / 4;
-	rt_int32_t *p = (rt_uint32_t *) t_addr;
+    addr = t_addr;
+    if (t_size % 4) {
+        rt_kprintf("mem must be alligned\n");
+    }
+    size = t_size / 4;
+    rt_int32_t *p = (rt_uint32_t *) t_addr;
 
-	//mmu_clean_invalidated_dcache(addr,t_size);
-	rt_kprintf("mem process add:0x%x \tsize:0x%x\n", addr, t_size);
-	rt_kprintf("0x%08x:", addr);
-	for (i = 0; i < size; i++) {
-		value = *p++;
-		if ((cnt / CHANGLINE_SIZE) && (cnt % CHANGLINE_SIZE == 0)) {
-			rt_kprintf("\n");
-		}
-		if (cnt / CHANGLINE_SIZE && (cnt % CHANGLINE_SIZE) == 0) {
-			rt_kprintf("0x%08x:", addr + i * 4);
-		}
-		rt_kprintf("\t%08x", value);
-		cnt++;
+    //mmu_clean_invalidated_dcache(addr,t_size);
+    rt_kprintf("mem process add:0x%x \tsize:0x%x\n", addr, t_size);
+    rt_kprintf("0x%08x:", addr);
+    for (i = 0; i < size; i++) {
+        value = *p++;
+        if ((cnt / CHANGLINE_SIZE) && (cnt % CHANGLINE_SIZE == 0)) {
+            rt_kprintf("\n");
+        }
+        if (cnt / CHANGLINE_SIZE && (cnt % CHANGLINE_SIZE) == 0) {
+            rt_kprintf("0x%08x:", addr + i * 4);
+        }
+        rt_kprintf("\t%08x", value);
+        cnt++;
 
-	}
-	rt_kprintf("\n");
+    }
+    rt_kprintf("\n");
 
 }
 #endif
diff --git a/bsp/fh8620/drivers/mmc.c b/bsp/fh8620/drivers/mmc.c
index 399efd5829..1b10974975 100644
--- a/bsp/fh8620/drivers/mmc.c
+++ b/bsp/fh8620/drivers/mmc.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/fh8620/drivers/mmc.h b/bsp/fh8620/drivers/mmc.h
index 5de1f5643f..1a0a6c66dc 100644
--- a/bsp/fh8620/drivers/mmc.h
+++ b/bsp/fh8620/drivers/mmc.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/fh8620/drivers/pwm.c b/bsp/fh8620/drivers/pwm.c
index 58c9703d78..497527a2f4 100644
--- a/bsp/fh8620/drivers/pwm.c
+++ b/bsp/fh8620/drivers/pwm.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
@@ -193,7 +193,7 @@ int fh_pwm_probe(void *priv_data)
         rt_kprintf("ERROR: %s rt_device calloc failed\n", __func__);
         return -RT_ENOMEM;
     }
-    
+
     pwm_dev->user_data = &pwm_drv;
     pwm_dev->open =fh_pwm_open;
     pwm_dev->close = fh_pwm_close;
diff --git a/bsp/fh8620/drivers/pwm.h b/bsp/fh8620/drivers/pwm.h
index 3693ab7973..b40fa89ff9 100644
--- a/bsp/fh8620/drivers/pwm.h
+++ b/bsp/fh8620/drivers/pwm.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #ifndef PWM_H_
 #define PWM_H_
 
diff --git a/bsp/fh8620/drivers/sadc.c b/bsp/fh8620/drivers/sadc.c
index b1654d295c..403b92cd71 100644
--- a/bsp/fh8620/drivers/sadc.c
+++ b/bsp/fh8620/drivers/sadc.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
@@ -50,123 +50,123 @@
 
 
 
-#define __raw_writeb(v,a)	( *(volatile unsigned char  *)(a) = (v))
-#define __raw_writew(v,a)	( *(volatile unsigned short *)(a) = (v))
-#define __raw_writel(v,a)	( *(volatile unsigned int   *)(a) = (v))
+#define __raw_writeb(v,a)   ( *(volatile unsigned char  *)(a) = (v))
+#define __raw_writew(v,a)   ( *(volatile unsigned short *)(a) = (v))
+#define __raw_writel(v,a)   ( *(volatile unsigned int   *)(a) = (v))
 
-#define __raw_readb(a)		( *(volatile unsigned char   *)(a))
-#define __raw_readw(a)		( *(volatile unsigned short  *)(a))
-#define __raw_readl(a)		( *(volatile unsigned int    *)(a))
+#define __raw_readb(a)      ( *(volatile unsigned char   *)(a))
+#define __raw_readw(a)      ( *(volatile unsigned short  *)(a))
+#define __raw_readl(a)      ( *(volatile unsigned int    *)(a))
 
 
 #define wrap_readl(wrap, name) \
-	__raw_readl(&(((struct wrap_sadc_reg *)wrap->regs)->name))
+    __raw_readl(&(((struct wrap_sadc_reg *)wrap->regs)->name))
 
 #define wrap_writel(wrap, name, val) \
-	__raw_writel((val), &(((struct wrap_sadc_reg *)wrap->regs)->name))
+    __raw_writel((val), &(((struct wrap_sadc_reg *)wrap->regs)->name))
 
 #define wrap_readw(wrap, name) \
-	__raw_readw(&(((struct wrap_sadc_reg *)wrap->regs)->name))
+    __raw_readw(&(((struct wrap_sadc_reg *)wrap->regs)->name))
 
 #define wrap_writew(wrap, name, val) \
-	__raw_writew((val), &(((struct wrap_sadc_reg *)wrap->regs)->name))
+    __raw_writew((val), &(((struct wrap_sadc_reg *)wrap->regs)->name))
 
 #define wrap_readb(wrap, name) \
-	__raw_readb(&(((struct wrap_sadc_reg *)wrap->regs)->name))
+    __raw_readb(&(((struct wrap_sadc_reg *)wrap->regs)->name))
 
 #define wrap_writeb(wrap, name, val) \
-	__raw_writeb((val), &(((struct wrap_sadc_reg *)wrap->regs)->name))
+    __raw_writeb((val), &(((struct wrap_sadc_reg *)wrap->regs)->name))
 
 
 
-#define IOCTL_GET_SADC_DATA 	1
-#define IOCTL_SADC_POWER_DOWN 	0xff
-#define SADC_WRAP_BASE			(0xf1200000)
-#define SADC_IRQn         		(23)
-#define SADC_MAX_CONTROLLER		(1)
-#define SADC_STATUS_COLESD		(0)
-#define SADC_STATUS_OPEN		(1)
+#define IOCTL_GET_SADC_DATA     1
+#define IOCTL_SADC_POWER_DOWN   0xff
+#define SADC_WRAP_BASE          (0xf1200000)
+#define SADC_IRQn               (23)
+#define SADC_MAX_CONTROLLER     (1)
+#define SADC_STATUS_COLESD      (0)
+#define SADC_STATUS_OPEN        (1)
 
 
 
 rt_err_t fh_sadc_isr_read_data(struct wrap_sadc_obj *sadc, rt_uint32_t channel,
-		rt_uint16_t *buf) {
-	rt_uint32_t xainsel = 1 << channel;
-	rt_uint32_t xversel = 0;
-	rt_uint32_t xpwdb = 1;
-	//cnt
-	rt_uint32_t sel2sam_pre_cnt = 2;
-	rt_uint32_t sam_cnt = 2;
-	rt_uint32_t sam2sel_pos_cnt = 2;
-	//time out
-	rt_uint32_t eoc_tos = 0xff;
-	rt_uint32_t eoc_toe = 0xff;
-	rt_uint32_t time_out = 0xffff;
-	//set isr en..
-	rt_uint32_t sadc_isr = 0x01;
-	//start
-	rt_uint32_t sadc_cmd = 0x01;
-	//get data
-	rt_uint32_t temp_data = 0;
-	rt_err_t ret;
+        rt_uint16_t *buf) {
+    rt_uint32_t xainsel = 1 << channel;
+    rt_uint32_t xversel = 0;
+    rt_uint32_t xpwdb = 1;
+    //cnt
+    rt_uint32_t sel2sam_pre_cnt = 2;
+    rt_uint32_t sam_cnt = 2;
+    rt_uint32_t sam2sel_pos_cnt = 2;
+    //time out
+    rt_uint32_t eoc_tos = 0xff;
+    rt_uint32_t eoc_toe = 0xff;
+    rt_uint32_t time_out = 0xffff;
+    //set isr en..
+    rt_uint32_t sadc_isr = 0x01;
+    //start
+    rt_uint32_t sadc_cmd = 0x01;
+    //get data
+    rt_uint32_t temp_data = 0;
+    rt_err_t ret;
 
 
-	//control...
-	wrap_writel(sadc, sadc_control, xainsel | (xversel << 8) | (xpwdb << 12));
+    //control...
+    wrap_writel(sadc, sadc_control, xainsel | (xversel << 8) | (xpwdb << 12));
 
 
-	wrap_writel(sadc, sadc_cnt,
-			sel2sam_pre_cnt | (sam_cnt << 8) | (sam2sel_pos_cnt << 16));
+    wrap_writel(sadc, sadc_cnt,
+            sel2sam_pre_cnt | (sam_cnt << 8) | (sam2sel_pos_cnt << 16));
 
-	wrap_writel(sadc, sadc_timeout,
-			eoc_tos | (eoc_toe << 8) | (time_out << 16));
+    wrap_writel(sadc, sadc_timeout,
+            eoc_tos | (eoc_toe << 8) | (time_out << 16));
 
-	wrap_writel(sadc, sadc_ier, sadc_isr);
+    wrap_writel(sadc, sadc_ier, sadc_isr);
 
-	wrap_writel(sadc, sadc_cmd, sadc_cmd);
+    wrap_writel(sadc, sadc_cmd, sadc_cmd);
 
 
    // ret = rt_completion_wait(&sadc->completion, RT_TICK_PER_SECOND / 2);
 
-	ret = rt_sem_take(&sadc->completion, 5000);
-	if(ret != RT_EOK)
-		return ret;
+    ret = rt_sem_take(&sadc->completion, 5000);
+    if(ret != RT_EOK)
+        return ret;
 
-	switch (channel) {
-	case 0:
-	case 1:
-		//read channel 0 1
-		temp_data = wrap_readl(sadc, sadc_dout0);
-		break;
+    switch (channel) {
+    case 0:
+    case 1:
+        //read channel 0 1
+        temp_data = wrap_readl(sadc, sadc_dout0);
+        break;
 
-	case 2:
-	case 3:
-		//read channel 2 3
-		temp_data = wrap_readl(sadc, sadc_dout1);
-		break;
+    case 2:
+    case 3:
+        //read channel 2 3
+        temp_data = wrap_readl(sadc, sadc_dout1);
+        break;
 
-	case 4:
-	case 5:
-		//read channel 4 5
-		temp_data = wrap_readl(sadc, sadc_dout2);
-		break;
+    case 4:
+    case 5:
+        //read channel 4 5
+        temp_data = wrap_readl(sadc, sadc_dout2);
+        break;
 
-	case 6:
-	case 7:
-		//read channel 6 7
-		temp_data = wrap_readl(sadc, sadc_dout3);
-		break;
-	default:
-		break;
-	}
-	if (channel % 2) {
-		//read low 16bit
-		*buf = (rt_uint16_t) (temp_data & 0xffff);
-	} else {
-		//read high 16bit
-		*buf = (rt_uint16_t) (temp_data >> 16);
-	}
-	return RT_EOK;
+    case 6:
+    case 7:
+        //read channel 6 7
+        temp_data = wrap_readl(sadc, sadc_dout3);
+        break;
+    default:
+        break;
+    }
+    if (channel % 2) {
+        //read low 16bit
+        *buf = (rt_uint16_t) (temp_data & 0xffff);
+    } else {
+        //read high 16bit
+        *buf = (rt_uint16_t) (temp_data >> 16);
+    }
+    return RT_EOK;
 
 }
 
@@ -204,41 +204,41 @@ static rt_err_t fh_sadc_close(rt_device_t dev)
 static rt_err_t fh_sadc_ioctl(rt_device_t dev, int cmd, void *arg)
 {
 
-	rt_uint32_t control_reg;
-	struct wrap_sadc_obj *sadc_pri =(struct wrap_sadc_obj *)dev->user_data;
-	rt_uint32_t ad_data;
-	rt_uint16_t ad_raw_data;
+    rt_uint32_t control_reg;
+    struct wrap_sadc_obj *sadc_pri =(struct wrap_sadc_obj *)dev->user_data;
+    rt_uint32_t ad_data;
+    rt_uint16_t ad_raw_data;
 
-	SADC_INFO *sadc_info = (SADC_INFO *)arg;
-	rt_err_t ret;
-	switch(cmd){
-	case SADC_CMD_READ_RAW_DATA:
-		ret = fh_sadc_isr_read_data(sadc_pri, sadc_info->channel, &ad_raw_data);
-		if(ret != RT_EOK)
-			return ret;
-		sadc_info->sadc_data = ad_raw_data;
+    SADC_INFO *sadc_info = (SADC_INFO *)arg;
+    rt_err_t ret;
+    switch(cmd){
+    case SADC_CMD_READ_RAW_DATA:
+        ret = fh_sadc_isr_read_data(sadc_pri, sadc_info->channel, &ad_raw_data);
+        if(ret != RT_EOK)
+            return ret;
+        sadc_info->sadc_data = ad_raw_data;
 
-		break;
-	case SADC_CMD_READ_VOLT:
-		ret = fh_sadc_isr_read_data(sadc_pri, sadc_info->channel, &ad_raw_data);
-		if(ret != RT_EOK)
-			return ret;
+        break;
+    case SADC_CMD_READ_VOLT:
+        ret = fh_sadc_isr_read_data(sadc_pri, sadc_info->channel, &ad_raw_data);
+        if(ret != RT_EOK)
+            return ret;
 
-		ad_data = ad_raw_data * SADC_REF;
-		ad_data /= SADC_MAX_AD_VALUE;
-		sadc_info->sadc_data = ad_data;
+        ad_data = ad_raw_data * SADC_REF;
+        ad_data /= SADC_MAX_AD_VALUE;
+        sadc_info->sadc_data = ad_data;
 
-		break;
-	case SADC_CMD_DISABLE:
-		control_reg = wrap_readl(sadc_pri, sadc_control);
-		control_reg &= ~(1 << 12);
-		wrap_writel(sadc_pri, sadc_control, control_reg);
+        break;
+    case SADC_CMD_DISABLE:
+        control_reg = wrap_readl(sadc_pri, sadc_control);
+        control_reg &= ~(1 << 12);
+        wrap_writel(sadc_pri, sadc_control, control_reg);
 
-		break;
-	default :
-		rt_kprintf("wrong para...\n");
-		return RT_EIO;
-	}
+        break;
+    default :
+        rt_kprintf("wrong para...\n");
+        return RT_EIO;
+    }
 
     return RT_EOK;
 }
@@ -249,25 +249,25 @@ static void fh_sadc_interrupt(int irq, void *param)
 {
 
     rt_uint32_t isr_status;
-	struct wrap_sadc_obj *sadc = (struct wrap_sadc_obj *) param;
+    struct wrap_sadc_obj *sadc = (struct wrap_sadc_obj *) param;
 
-	isr_status = wrap_readl(sadc, sadc_int_status);
+    isr_status = wrap_readl(sadc, sadc_int_status);
 
-	if (isr_status & 0x01) {
-		//close isr
-		rt_uint32_t sadc_isr = 0x00;
+    if (isr_status & 0x01) {
+        //close isr
+        rt_uint32_t sadc_isr = 0x00;
 
-		wrap_writel(sadc, sadc_ier, sadc_isr);
-		//clear status..
+        wrap_writel(sadc, sadc_ier, sadc_isr);
+        //clear status..
 
-		wrap_writel(sadc, sadc_int_status, isr_status);
+        wrap_writel(sadc, sadc_int_status, isr_status);
 
-		rt_sem_release(&sadc->completion);
-	   // rt_completion_done(&sadc->completion);
-	} else {
-		//add error handle process
-		rt_kprintf("sadc maybe error!\n");
-	}
+        rt_sem_release(&sadc->completion);
+       // rt_completion_done(&sadc->completion);
+    } else {
+        //add error handle process
+        rt_kprintf("sadc maybe error!\n");
+    }
 
 
 }
@@ -282,13 +282,13 @@ int fh_sadc_probe(void *priv_data)
     //caution this is a read only data...if the driver want to use.malloc and copy it..
     struct wrap_sadc_obj *sadc_obj = (struct wrap_sadc_obj *)priv_data;
     if(sadc_obj->init_flag == SADC_INIT_ALREADY)
-     	return RT_EFULL;
+        return RT_EFULL;
 
 
     //malloc a rt device..
     sadc_dev = RT_KERNEL_MALLOC(sizeof(struct rt_device));
     if(!sadc_dev){
-    	return RT_ENOMEM;
+        return RT_ENOMEM;
     }
     rt_memset(sadc_dev, 0, sizeof(struct rt_device));
     PRINT_SADC_DBG("id:%d,\treg:%x,\tirq:%d\n",sadc_obj->id,(rt_uint32_t)sadc_obj->regs,sadc_obj->irq_no);
@@ -304,8 +304,8 @@ int fh_sadc_probe(void *priv_data)
     struct wrap_sadc_obj *sadc_pri = RT_KERNEL_MALLOC(sizeof(struct wrap_sadc_obj));
     if(!sadc_pri){
 
-    	RT_KERNEL_FREE(sadc_dev);
-    	return RT_ENOMEM;
+        RT_KERNEL_FREE(sadc_dev);
+        return RT_ENOMEM;
     }
 
     //copy platform data to pri data..
@@ -349,23 +349,23 @@ int fh_sadc_probe(void *priv_data)
 int fh_sadc_exit(void *priv_data)
 {
 
-	PRINT_SADC_DBG("%s\n",__func__);
-	struct wrap_sadc_obj *sadc_obj = (struct wrap_sadc_obj *)priv_data;
+    PRINT_SADC_DBG("%s\n",__func__);
+    struct wrap_sadc_obj *sadc_obj = (struct wrap_sadc_obj *)priv_data;
 
-	struct wrap_sadc_obj *sadc_pri = sadc_obj->rt_dev->user_data;
-	//release sem;
-	rt_sem_detach(&sadc_pri->completion);
-	//sadc_pri->completion = RT_NULL;
+    struct wrap_sadc_obj *sadc_pri = sadc_obj->rt_dev->user_data;
+    //release sem;
+    rt_sem_detach(&sadc_pri->completion);
+    //sadc_pri->completion = RT_NULL;
 
-	//release lock;
-	rt_mutex_detach(&sadc_pri->lock);
+    //release lock;
+    rt_mutex_detach(&sadc_pri->lock);
 
-	RT_KERNEL_FREE(sadc_obj->rt_dev->user_data);
+    RT_KERNEL_FREE(sadc_obj->rt_dev->user_data);
 
 
-	sadc_obj->rt_dev->user_data = RT_NULL;
-	RT_KERNEL_FREE(sadc_obj->rt_dev);
-	sadc_obj->rt_dev = RT_NULL;
+    sadc_obj->rt_dev->user_data = RT_NULL;
+    RT_KERNEL_FREE(sadc_obj->rt_dev);
+    sadc_obj->rt_dev = RT_NULL;
 
     return 0;
 }
@@ -386,23 +386,23 @@ void rt_hw_sadc_init(void)
 #ifdef FH_TEST_SADC
 int fh_sadc_test(void){
 
-	rt_device_t sadc_dev;
-	SADC_INFO info;
-	info.channel = 0;
-	info.sadc_data = 0;
-	sadc_dev = rt_device_find("sadc");
-	if(!sadc_dev){
-		rt_kprintf("cann't find the sadc dev\n");
-	}
-	sadc_dev->init(sadc_dev);
-	sadc_dev->open(sadc_dev,0);
-	while(1)
-	{
-		sadc_dev->control(sadc_dev,SADC_CMD_READ_VOLT,&info);
-		rt_kprintf("channel:%d,volt:%dmv\n",info.channel,info.sadc_data);
-	}
+    rt_device_t sadc_dev;
+    SADC_INFO info;
+    info.channel = 0;
+    info.sadc_data = 0;
+    sadc_dev = rt_device_find("sadc");
+    if(!sadc_dev){
+        rt_kprintf("cann't find the sadc dev\n");
+    }
+    sadc_dev->init(sadc_dev);
+    sadc_dev->open(sadc_dev,0);
+    while(1)
+    {
+        sadc_dev->control(sadc_dev,SADC_CMD_READ_VOLT,&info);
+        rt_kprintf("channel:%d,volt:%dmv\n",info.channel,info.sadc_data);
+    }
 
-	return 0;
+    return 0;
 }
 #endif
 
diff --git a/bsp/fh8620/drivers/sadc.h b/bsp/fh8620/drivers/sadc.h
index d28ed9ba24..afe168bd2e 100644
--- a/bsp/fh8620/drivers/sadc.h
+++ b/bsp/fh8620/drivers/sadc.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #ifndef SADC_H_
 #define SADC_H_
 
@@ -33,57 +33,57 @@
 
 /****************************************************************************
  * #define section
- *	add constant #define here if any
+ *  add constant #define here if any
  ***************************************************************************/
 //#define FH_SADC_PROC_FILE    "driver/sadc"
-#define MAX_CHANNEL_NO		(8)
-#define SADC_REF			(3300)
-#define SADC_MAX_AD_VALUE	(0x3ff)
-#define LOOP_MODE			(0x55)
-#define ISR_MODE			(0xAA)
+#define MAX_CHANNEL_NO      (8)
+#define SADC_REF            (3300)
+#define SADC_MAX_AD_VALUE   (0x3ff)
+#define LOOP_MODE           (0x55)
+#define ISR_MODE            (0xAA)
 
 
-#define SADC_INIT_ALREADY		(0x33)
-#define SADC_INIT_NOT_YET		(0)
+#define SADC_INIT_ALREADY       (0x33)
+#define SADC_INIT_NOT_YET       (0)
 
 
-#define SADC_CMD_READ_RAW_DATA			(0x22)
-#define SADC_CMD_READ_VOLT				(0x33)
-#define SADC_CMD_DISABLE				(0x44)
+#define SADC_CMD_READ_RAW_DATA          (0x22)
+#define SADC_CMD_READ_VOLT              (0x33)
+#define SADC_CMD_DISABLE                (0x44)
 
 /****************************************************************************
  * ADT section
- *	add Abstract Data Type definition here
+ *  add Abstract Data Type definition here
  ***************************************************************************/
 
 struct wrap_sadc_reg {
-	rt_uint32_t sadc_cmd;
-	rt_uint32_t sadc_control;
-	rt_uint32_t sadc_ier;
-	rt_uint32_t sadc_int_status;
-	rt_uint32_t sadc_dout0;
-	rt_uint32_t sadc_dout1;
-	rt_uint32_t sadc_dout2;
-	rt_uint32_t sadc_dout3;
-	rt_uint32_t sadc_debuge0;
-	rt_uint32_t sadc_status;
-	rt_uint32_t sadc_cnt;
-	rt_uint32_t sadc_timeout;
+    rt_uint32_t sadc_cmd;
+    rt_uint32_t sadc_control;
+    rt_uint32_t sadc_ier;
+    rt_uint32_t sadc_int_status;
+    rt_uint32_t sadc_dout0;
+    rt_uint32_t sadc_dout1;
+    rt_uint32_t sadc_dout2;
+    rt_uint32_t sadc_dout3;
+    rt_uint32_t sadc_debuge0;
+    rt_uint32_t sadc_status;
+    rt_uint32_t sadc_cnt;
+    rt_uint32_t sadc_timeout;
 };
 
 struct wrap_sadc_obj {
-	rt_uint32_t id;
-	void *regs;
-	rt_uint32_t irq_no;
-	rt_uint32_t init_flag;
-	rt_uint32_t active_channel_no;
-	rt_uint32_t active_channel_status;
-	rt_uint16_t channel_data[MAX_CHANNEL_NO];
-	rt_uint32_t error_rec;
-	rt_uint32_t en_isr;
-	rt_uint32_t sample_mode;
-	struct rt_mutex lock;
-	struct rt_semaphore completion;
+    rt_uint32_t id;
+    void *regs;
+    rt_uint32_t irq_no;
+    rt_uint32_t init_flag;
+    rt_uint32_t active_channel_no;
+    rt_uint32_t active_channel_status;
+    rt_uint16_t channel_data[MAX_CHANNEL_NO];
+    rt_uint32_t error_rec;
+    rt_uint32_t en_isr;
+    rt_uint32_t sample_mode;
+    struct rt_mutex lock;
+    struct rt_semaphore completion;
 
     //bind to the rtdev..
     rt_device_t rt_dev;
@@ -91,8 +91,8 @@ struct wrap_sadc_obj {
 };
 
 typedef struct{
-	rt_uint32_t channel;
-	rt_uint32_t sadc_data;
+    rt_uint32_t channel;
+    rt_uint32_t sadc_data;
 }SADC_INFO;
 
 
@@ -102,7 +102,7 @@ typedef struct{
 
 /****************************************************************************
  *  section
- *	add function prototype here if any
+ *  add function prototype here if any
  ***************************************************************************/
 void rt_hw_sadc_init(void);
 #endif
diff --git a/bsp/fh8620/drivers/spi_fh_adapt.c b/bsp/fh8620/drivers/spi_fh_adapt.c
index 291fe9a4f9..437b30d1c9 100644
--- a/bsp/fh8620/drivers/spi_fh_adapt.c
+++ b/bsp/fh8620/drivers/spi_fh_adapt.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
  /*
  * spi_fh_adapt.c
  *
@@ -60,9 +60,9 @@
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
 
 
-#define WX_MANU_ID		0xEF
+#define WX_MANU_ID      0xEF
 #define AT_MANU_ID      0x1F /* atmel */
-#define SST_MANU_ID		0xBF
+#define SST_MANU_ID     0xBF
 #define GD_MANU_ID      0xC8
 
 
@@ -70,50 +70,50 @@
 #define SPI_ADAPT_DEBUG
 #ifdef SPI_ADAPT_DEBUG
 
-#define CMD_JEDEC_ID 			0x9f
+#define CMD_JEDEC_ID            0x9f
 
 
-#define FH_SPI_ADAPT_DEBUG(fmt, args...)	    		\
-			rt_kprintf(fmt,##args);
+#define FH_SPI_ADAPT_DEBUG(fmt, args...)                \
+            rt_kprintf(fmt,##args);
 #else
 #define FH_SPI_ADAPT_DEBUG(fmt, args...)
 #endif
 struct fh_flash_id{
-	unsigned char id;
-	rt_err_t (*fh_flash_init)(struct flash_platform_data *plat_flash);
-	char *name;
+    unsigned char id;
+    rt_err_t (*fh_flash_init)(struct flash_platform_data *plat_flash);
+    char *name;
 };
 const struct fh_flash_id id_map[] = {
 
 #ifdef RT_USING_W25QXX
-		WX_MANU_ID,w25qxx_init,"winbond",
+        WX_MANU_ID,w25qxx_init,"winbond",
 #endif
 
 #ifdef RT_USING_AT45DBXX
-		AT_MANU_ID,at45dbxx_init,"atmel",
+        AT_MANU_ID,at45dbxx_init,"atmel",
 #endif
 
 #ifdef RT_USING_SST25VFXX
-		SST_MANU_ID,sst25vfxx_init,"SST",
+        SST_MANU_ID,sst25vfxx_init,"SST",
 #endif
 
 #ifdef RT_USING_GD
-		GD_MANU_ID,gd_init,"GD",
+        GD_MANU_ID,gd_init,"GD",
 #endif
 
 };
 
 
 struct fh_flash_id * fh_flash_check_id_map(unsigned char id){
-	struct fh_flash_id *p_map = RT_NULL;
-	unsigned int i;
-	for (i = 0; i < ARRAY_SIZE(id_map); i++) {
-		p_map = (struct fh_flash_id *)&id_map[i];
-		if (p_map->id == id){
-			return p_map;
-		}
-	}
-	return RT_NULL;
+    struct fh_flash_id *p_map = RT_NULL;
+    unsigned int i;
+    for (i = 0; i < ARRAY_SIZE(id_map); i++) {
+        p_map = (struct fh_flash_id *)&id_map[i];
+        if (p_map->id == id){
+            return p_map;
+        }
+    }
+    return RT_NULL;
 }
 
 
@@ -144,50 +144,50 @@ int fh_flash_adapt_probe(void *priv_data)
 
     /* init flash */
 
-	rt_uint8_t cmd;
-	rt_uint8_t id_recv[3];
-	uint16_t memory_type_capacity;
-	rt_err_t ret;
+    rt_uint8_t cmd;
+    rt_uint8_t id_recv[3];
+    uint16_t memory_type_capacity;
+    rt_err_t ret;
 
-	cmd = 0xFF; /* reset SPI FLASH, cancel all cmd in processing. */
-	rt_spi_send(rt_spi_device, &cmd, 1);
-	/* read flash id */
-	cmd = CMD_JEDEC_ID;
-	rt_spi_send_then_recv(rt_spi_device, &cmd, 1, id_recv, 3);
+    cmd = 0xFF; /* reset SPI FLASH, cancel all cmd in processing. */
+    rt_spi_send(rt_spi_device, &cmd, 1);
+    /* read flash id */
+    cmd = CMD_JEDEC_ID;
+    rt_spi_send_then_recv(rt_spi_device, &cmd, 1, id_recv, 3);
 
-	//if the flash is already connect.
-	if(id_recv[0] != 0xff){
-		flash_model =fh_flash_check_id_map(id_recv[0]);
-		if(flash_model){
-			ret = flash_model->fh_flash_init(plat_flash);
-			if(ret != RT_EOK){
-				rt_kprintf("flash:%s init error\n",flash_model->name);
-				rt_kprintf("use default flash ops..\n");
-				//flash_model->fh_flash_adapt_init =flash_default_init;
-				ret = flash_default_init(plat_flash);
-			}
-		}
-		else{
-			rt_kprintf(
-					"use default flash ops...\nunrecognized flash id is :%02X %02X %02X\n",
-					id_recv[0], id_recv[1], id_recv[2]);
-			ret = flash_default_init(plat_flash);
+    //if the flash is already connect.
+    if(id_recv[0] != 0xff){
+        flash_model =fh_flash_check_id_map(id_recv[0]);
+        if(flash_model){
+            ret = flash_model->fh_flash_init(plat_flash);
+            if(ret != RT_EOK){
+                rt_kprintf("flash:%s init error\n",flash_model->name);
+                rt_kprintf("use default flash ops..\n");
+                //flash_model->fh_flash_adapt_init =flash_default_init;
+                ret = flash_default_init(plat_flash);
+            }
+        }
+        else{
+            rt_kprintf(
+                    "use default flash ops...\nunrecognized flash id is :%02X %02X %02X\n",
+                    id_recv[0], id_recv[1], id_recv[2]);
+            ret = flash_default_init(plat_flash);
 
-		}
+        }
 
-		int i;
-		for(i=0; inr_parts; i++)
-		{
-		    fh_spi_partition_register(plat_flash->flash_name, &plat_flash->parts[i]);
-		}
+        int i;
+        for(i=0; inr_parts; i++)
+        {
+            fh_spi_partition_register(plat_flash->flash_name, &plat_flash->parts[i]);
+        }
 
-		return ret;
+        return ret;
 
-	}
-	else{
-		rt_kprintf("please check if you connect the flash already...\n");
-		return RT_ENOSYS;
-	}
+    }
+    else{
+        rt_kprintf("please check if you connect the flash already...\n");
+        return RT_ENOSYS;
+    }
 
 
 }
diff --git a/bsp/fh8620/drivers/spi_fh_adapt.h b/bsp/fh8620/drivers/spi_fh_adapt.h
index 171fdf7184..3e3cc365ab 100644
--- a/bsp/fh8620/drivers/spi_fh_adapt.h
+++ b/bsp/fh8620/drivers/spi_fh_adapt.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
  /*
  * spi_fh_adapt.h
  *
diff --git a/bsp/fh8620/drivers/ssi.c b/bsp/fh8620/drivers/ssi.c
index e5cb99042e..c87a4352ae 100644
--- a/bsp/fh8620/drivers/ssi.c
+++ b/bsp/fh8620/drivers/ssi.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #include 
 #include 
 #include "fh_arch.h"
@@ -49,20 +49,20 @@
 #endif
 
 
-#define RX_DMA_CHANNEL	AUTO_FIND_CHANNEL
-#define TX_DMA_CHANNEL	AUTO_FIND_CHANNEL
+#define RX_DMA_CHANNEL  AUTO_FIND_CHANNEL
+#define TX_DMA_CHANNEL  AUTO_FIND_CHANNEL
 
-#define DMA_OR_ISR_THRESHOLD		20
-#define MALLOC_DMA_MEM_SIZE			0x1000
+#define DMA_OR_ISR_THRESHOLD        20
+#define MALLOC_DMA_MEM_SIZE         0x1000
 
 
 //static rt_uint32_t allign_func(rt_uint32_t in_addr,rt_uint32_t allign_size){
-//	return (in_addr + allign_size-1) & (~(allign_size - 1));
+//  return (in_addr + allign_size-1) & (~(allign_size - 1));
 //}
 
 
 void * fh_get_spi_dev_pri_data(struct rt_spi_device* device){
-	return device->parent.user_data;
+    return device->parent.user_data;
 }
 
 static rt_err_t fh_spi_configure(struct rt_spi_device* device,
@@ -87,54 +87,54 @@ static rt_err_t fh_spi_configure(struct rt_spi_device* device,
     PRINT_SPI_DBG("\tmax_hz: 0x%x\n", configuration->max_hz);
 
     do{
-	  status = SPI_ReadStatus(spi_obj);
-	}
+      status = SPI_ReadStatus(spi_obj);
+    }
     while(status & SPI_STATUS_BUSY);
 
 
-	/* data_width */
-	if(configuration->data_width <= 8){
-	  config->data_size = SPI_DATA_SIZE_8BIT;
-	}
-	else if(configuration->data_width <= 16){
-	  config->data_size = SPI_DATA_SIZE_16BIT;
-	}
-	else{
-	  return -RT_ERROR;
-	}
+    /* data_width */
+    if(configuration->data_width <= 8){
+      config->data_size = SPI_DATA_SIZE_8BIT;
+    }
+    else if(configuration->data_width <= 16){
+      config->data_size = SPI_DATA_SIZE_16BIT;
+    }
+    else{
+      return -RT_ERROR;
+    }
 
-	if(configuration->max_hz > spi_control->max_hz)
-		spi_hz = spi_control->max_hz;
-	else
-		spi_hz = configuration->max_hz;
+    if(configuration->max_hz > spi_control->max_hz)
+        spi_hz = spi_control->max_hz;
+    else
+        spi_hz = configuration->max_hz;
 
-	//fixme: div
-	config->clk_div = spi_control->clk_in/spi_hz;
-	//config->clk_div = 8;
-	PRINT_SPI_DBG("config hz:%d spi div:%d\n",spi_hz,config->clk_div);
-	/* CPOL */
-	if(configuration->mode & RT_SPI_CPOL){
-	  config->clk_polarity = SPI_POLARITY_HIGH;
-	}
-	else{
-	  config->clk_polarity = SPI_POLARITY_LOW;
-	}
+    //fixme: div
+    config->clk_div = spi_control->clk_in/spi_hz;
+    //config->clk_div = 8;
+    PRINT_SPI_DBG("config hz:%d spi div:%d\n",spi_hz,config->clk_div);
+    /* CPOL */
+    if(configuration->mode & RT_SPI_CPOL){
+      config->clk_polarity = SPI_POLARITY_HIGH;
+    }
+    else{
+      config->clk_polarity = SPI_POLARITY_LOW;
+    }
 
-	/* CPHA */
-	if(configuration->mode & RT_SPI_CPHA){
-	  config->clk_phase = SPI_PHASE_TX_FIRST;
-	}
-	else{
-	  config->clk_phase = SPI_PHASE_RX_FIRST;
-	}
+    /* CPHA */
+    if(configuration->mode & RT_SPI_CPHA){
+      config->clk_phase = SPI_PHASE_TX_FIRST;
+    }
+    else{
+      config->clk_phase = SPI_PHASE_RX_FIRST;
+    }
 
-	config->frame_format = SPI_FORMAT_MOTOROLA;
-	config->transfer_mode = SPI_MODE_TX_RX;
+    config->frame_format = SPI_FORMAT_MOTOROLA;
+    config->transfer_mode = SPI_MODE_TX_RX;
 
-	SPI_Enable(spi_obj, 0);
-	SPI_SetParameter(spi_obj);
-	SPI_DisableInterrupt(spi_obj, SPI_IRQ_ALL);
-	SPI_Enable(spi_obj, 1);
+    SPI_Enable(spi_obj, 0);
+    SPI_SetParameter(spi_obj);
+    SPI_DisableInterrupt(spi_obj, SPI_IRQ_ALL);
+    SPI_Enable(spi_obj, 1);
 
     return RT_EOK;
 }
@@ -142,8 +142,8 @@ static rt_err_t fh_spi_configure(struct rt_spi_device* device,
 
 static void xfer_dma_done(void *arg)
 {
-	struct spi_controller *spi_control = (struct spi_controller *)arg;
-	spi_control->dma_complete_times++;
+    struct spi_controller *spi_control = (struct spi_controller *)arg;
+    spi_control->dma_complete_times++;
 
     struct fh_spi_obj *spi_obj;
     int ret;
@@ -151,72 +151,72 @@ static void xfer_dma_done(void *arg)
     spi_obj = &spi_control->obj;
 
 
-	//rt_kprintf("spi dma isr done.....\n");
-	if (spi_control->dma_complete_times == 2) {
-		spi_control->dma_complete_times = 0;
+    //rt_kprintf("spi dma isr done.....\n");
+    if (spi_control->dma_complete_times == 2) {
+        spi_control->dma_complete_times = 0;
 
-		//add memcpy to user buff
-		if(spi_control->current_message->recv_buf){
-			rt_memcpy((void*)spi_control->current_message->recv_buf,(void*)spi_control->dma.rx_dummy_buff,spi_control->current_message->length);
-		}
+        //add memcpy to user buff
+        if(spi_control->current_message->recv_buf){
+            rt_memcpy((void*)spi_control->current_message->recv_buf,(void*)spi_control->dma.rx_dummy_buff,spi_control->current_message->length);
+        }
 
-		SPI_Enable(spi_obj,0);
-		SPI_DisableDma(spi_obj,SPI_TX_DMA|SPI_RX_DMA);
-		SPI_Enable(spi_obj,1);
+        SPI_Enable(spi_obj,0);
+        SPI_DisableDma(spi_obj,SPI_TX_DMA|SPI_RX_DMA);
+        SPI_Enable(spi_obj,1);
 
-		rt_completion_done(&spi_control->transfer_completion);
-	}
+        rt_completion_done(&spi_control->transfer_completion);
+    }
 
 }
 
 void dma_set_tx_data(struct spi_controller *spi_control){
 
-	struct dma_transfer *trans;
-	rt_uint32_t hs_no;
-	struct rt_spi_message* current_message = spi_control->current_message;
-	trans = &spi_control->dma.tx_trans;
-	hs_no = spi_control->dma.tx_hs;
+    struct dma_transfer *trans;
+    rt_uint32_t hs_no;
+    struct rt_spi_message* current_message = spi_control->current_message;
+    trans = &spi_control->dma.tx_trans;
+    hs_no = spi_control->dma.tx_hs;
 
-	struct fh_spi_obj *spi_obj;
-	spi_obj = &spi_control->obj;
+    struct fh_spi_obj *spi_obj;
+    spi_obj = &spi_control->obj;
 
 
 
-	if(current_message->length > MALLOC_DMA_MEM_SIZE){
-		rt_kprintf("[spi_dma]message len too large..\n");
-		rt_kprintf("[spi_dma] message len is %d,max len is %d\n",current_message->length,MALLOC_DMA_MEM_SIZE);
-		RT_ASSERT(current_message->length <= MALLOC_DMA_MEM_SIZE);
-	}
+    if(current_message->length > MALLOC_DMA_MEM_SIZE){
+        rt_kprintf("[spi_dma]message len too large..\n");
+        rt_kprintf("[spi_dma] message len is %d,max len is %d\n",current_message->length,MALLOC_DMA_MEM_SIZE);
+        RT_ASSERT(current_message->length <= MALLOC_DMA_MEM_SIZE);
+    }
 
 
-	rt_memset((void*)spi_control->dma.tx_dummy_buff,0xff,current_message->length);
-	//copy tx data....
-	if(current_message->send_buf){
-		rt_memcpy(spi_control->dma.tx_dummy_buff,current_message->send_buf,current_message->length);
-	}
+    rt_memset((void*)spi_control->dma.tx_dummy_buff,0xff,current_message->length);
+    //copy tx data....
+    if(current_message->send_buf){
+        rt_memcpy(spi_control->dma.tx_dummy_buff,current_message->send_buf,current_message->length);
+    }
 
 
-	trans->dma_number = 0;
-	trans->dst_add = (rt_uint32_t)(spi_obj->base + OFFSET_SPI_DR);
+    trans->dma_number = 0;
+    trans->dst_add = (rt_uint32_t)(spi_obj->base + OFFSET_SPI_DR);
 
-	trans->dst_hs = DMA_HW_HANDSHAKING;
-	trans->dst_inc_mode = DW_DMA_SLAVE_FIX;
-	trans->dst_msize = DW_DMA_SLAVE_MSIZE_1;
-	trans->dst_per = hs_no;
-	trans->dst_width = DW_DMA_SLAVE_WIDTH_8BIT;
-	trans->fc_mode = DMA_M2P;
+    trans->dst_hs = DMA_HW_HANDSHAKING;
+    trans->dst_inc_mode = DW_DMA_SLAVE_FIX;
+    trans->dst_msize = DW_DMA_SLAVE_MSIZE_1;
+    trans->dst_per = hs_no;
+    trans->dst_width = DW_DMA_SLAVE_WIDTH_8BIT;
+    trans->fc_mode = DMA_M2P;
 
-	trans->src_add = (rt_uint32_t)spi_control->dma.tx_dummy_buff;
+    trans->src_add = (rt_uint32_t)spi_control->dma.tx_dummy_buff;
 
-	trans->src_inc_mode = DW_DMA_SLAVE_INC;
-	trans->src_msize = DW_DMA_SLAVE_MSIZE_1;
+    trans->src_inc_mode = DW_DMA_SLAVE_INC;
+    trans->src_msize = DW_DMA_SLAVE_MSIZE_1;
 
-	trans->src_width = DW_DMA_SLAVE_WIDTH_8BIT;
-	trans->trans_len = current_message->length;
+    trans->src_width = DW_DMA_SLAVE_WIDTH_8BIT;
+    trans->trans_len = current_message->length;
 
 
-	trans->complete_callback = (void *)xfer_dma_done;
-	trans->complete_para = (void *)spi_control;
+    trans->complete_callback = (void *)xfer_dma_done;
+    trans->complete_para = (void *)spi_control;
 
 
 
@@ -225,153 +225,153 @@ void dma_set_tx_data(struct spi_controller *spi_control){
 
 void dma_set_rx_data(struct spi_controller *spi_control){
 
-	struct dma_transfer *trans;
-	rt_uint32_t hs_no;
-	struct rt_spi_message* current_message = spi_control->current_message;
-	trans = &spi_control->dma.rx_trans;
-	hs_no = spi_control->dma.rx_hs;
+    struct dma_transfer *trans;
+    rt_uint32_t hs_no;
+    struct rt_spi_message* current_message = spi_control->current_message;
+    trans = &spi_control->dma.rx_trans;
+    hs_no = spi_control->dma.rx_hs;
 
-	struct fh_spi_obj *spi_obj;
-	spi_obj = &spi_control->obj;
+    struct fh_spi_obj *spi_obj;
+    spi_obj = &spi_control->obj;
 
-	if(current_message->length > MALLOC_DMA_MEM_SIZE){
-		rt_kprintf("[spi_dma]message len too large..len is %d\n",current_message->length);
-		RT_ASSERT(current_message->length <= MALLOC_DMA_MEM_SIZE);
-	}
+    if(current_message->length > MALLOC_DMA_MEM_SIZE){
+        rt_kprintf("[spi_dma]message len too large..len is %d\n",current_message->length);
+        RT_ASSERT(current_message->length <= MALLOC_DMA_MEM_SIZE);
+    }
 
 
-	//rt_memset((void *)spi_control->dma.rx_dummy_buff,0,MALLOC_DMA_MEM_SIZE);
+    //rt_memset((void *)spi_control->dma.rx_dummy_buff,0,MALLOC_DMA_MEM_SIZE);
 
-	trans->dma_number = 0;
-	trans->fc_mode = DMA_P2M;
+    trans->dma_number = 0;
+    trans->fc_mode = DMA_P2M;
 
-	trans->dst_add = (rt_uint32_t)spi_control->dma.rx_dummy_buff;
-	trans->dst_inc_mode = DW_DMA_SLAVE_INC;
-	trans->dst_msize = DW_DMA_SLAVE_MSIZE_1;
-	trans->dst_width = DW_DMA_SLAVE_WIDTH_8BIT;
+    trans->dst_add = (rt_uint32_t)spi_control->dma.rx_dummy_buff;
+    trans->dst_inc_mode = DW_DMA_SLAVE_INC;
+    trans->dst_msize = DW_DMA_SLAVE_MSIZE_1;
+    trans->dst_width = DW_DMA_SLAVE_WIDTH_8BIT;
 
 
 
-	trans->src_add = (rt_uint32_t)(spi_obj->base + OFFSET_SPI_DR);
-	trans->src_inc_mode = DW_DMA_SLAVE_FIX;
-	trans->src_msize = DW_DMA_SLAVE_MSIZE_1;
-	trans->src_width = DW_DMA_SLAVE_WIDTH_8BIT;
-	trans->src_hs = DMA_HW_HANDSHAKING;
-	trans->src_per = hs_no;
-	trans->trans_len = current_message->length;
+    trans->src_add = (rt_uint32_t)(spi_obj->base + OFFSET_SPI_DR);
+    trans->src_inc_mode = DW_DMA_SLAVE_FIX;
+    trans->src_msize = DW_DMA_SLAVE_MSIZE_1;
+    trans->src_width = DW_DMA_SLAVE_WIDTH_8BIT;
+    trans->src_hs = DMA_HW_HANDSHAKING;
+    trans->src_per = hs_no;
+    trans->trans_len = current_message->length;
 
 
 
-	trans->complete_callback = (void *)xfer_dma_done;
-	trans->complete_para = (void *)spi_control;
+    trans->complete_callback = (void *)xfer_dma_done;
+    trans->complete_para = (void *)spi_control;
 
 
 }
 
 
 rt_uint32_t xfer_data_dma(struct spi_controller *spi_control){
-	int ret;
+    int ret;
 
-	struct fh_spi_obj *spi_obj;
-	spi_obj = &spi_control->obj;
+    struct fh_spi_obj *spi_obj;
+    spi_obj = &spi_control->obj;
 
-	struct rt_dma_device *dma_dev = spi_control->dma.dma_dev;
+    struct rt_dma_device *dma_dev = spi_control->dma.dma_dev;
 
 
-	//tx data prepare
-	dma_set_tx_data(spi_control);
-	//rx data prepare
-	dma_set_rx_data(spi_control);
-	//dma go...
+    //tx data prepare
+    dma_set_tx_data(spi_control);
+    //rx data prepare
+    dma_set_rx_data(spi_control);
+    //dma go...
 
 
-	SPI_Enable(spi_obj,0);
+    SPI_Enable(spi_obj,0);
 
-	//SPI_WriteTxDmaLevel(spi_obj,SPI_FIFO_DEPTH / 4);
-	SPI_WriteTxDmaLevel(spi_obj,1);
-	//SPI_WriteTxDmaLevel(spi_obj,0);
-	SPI_WriteRxDmaLevel(spi_obj,0);
-	SPI_EnableDma(spi_obj,SPI_TX_DMA|SPI_RX_DMA);
-	SPI_Enable(spi_obj,1);
+    //SPI_WriteTxDmaLevel(spi_obj,SPI_FIFO_DEPTH / 4);
+    SPI_WriteTxDmaLevel(spi_obj,1);
+    //SPI_WriteTxDmaLevel(spi_obj,0);
+    SPI_WriteRxDmaLevel(spi_obj,0);
+    SPI_EnableDma(spi_obj,SPI_TX_DMA|SPI_RX_DMA);
+    SPI_Enable(spi_obj,1);
 
-	dma_dev->ops->control(dma_dev,RT_DEVICE_CTRL_DMA_SINGLE_TRANSFER,(void *)&spi_control->dma.rx_trans);
-	dma_dev->ops->control(dma_dev,RT_DEVICE_CTRL_DMA_SINGLE_TRANSFER,(void *)&spi_control->dma.tx_trans);
+    dma_dev->ops->control(dma_dev,RT_DEVICE_CTRL_DMA_SINGLE_TRANSFER,(void *)&spi_control->dma.rx_trans);
+    dma_dev->ops->control(dma_dev,RT_DEVICE_CTRL_DMA_SINGLE_TRANSFER,(void *)&spi_control->dma.tx_trans);
 
-	ret = rt_completion_wait(&spi_control->transfer_completion, RT_TICK_PER_SECOND*50);
-	//release channel..
+    ret = rt_completion_wait(&spi_control->transfer_completion, RT_TICK_PER_SECOND*50);
+    //release channel..
 
-	//dma_dev->ops->control(dma_dev,RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL,(void *)&spi_control->dma.tx_trans);
-	//dma_dev->ops->control(dma_dev,RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL,(void *)&spi_control->dma.rx_trans);
+    //dma_dev->ops->control(dma_dev,RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL,(void *)&spi_control->dma.tx_trans);
+    //dma_dev->ops->control(dma_dev,RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL,(void *)&spi_control->dma.rx_trans);
 
-	if(ret)
-	{
-		rt_kprintf("ERROR: %s, transfer timeout\n", __func__);
-		return -RT_ETIMEOUT;
-	}
+    if(ret)
+    {
+        rt_kprintf("ERROR: %s, transfer timeout\n", __func__);
+        return -RT_ETIMEOUT;
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 rt_uint32_t xfer_data_isr(struct spi_controller *spi_control){
 
-	int ret;
-	struct fh_spi_obj *spi_obj;
-	spi_obj = &spi_control->obj;
+    int ret;
+    struct fh_spi_obj *spi_obj;
+    spi_obj = &spi_control->obj;
     SPI_SetTxLevel(spi_obj, SPI_FIFO_DEPTH / 2);
     SPI_EnableInterrupt(spi_obj, SPI_IRQ_TXEIM);
-	ret = rt_completion_wait(&spi_control->transfer_completion, RT_TICK_PER_SECOND*50);
-	if(ret)
-	{
-		rt_kprintf("ERROR: %s, transfer timeout\n", __func__);
-		return -RT_ETIMEOUT;
-	}
+    ret = rt_completion_wait(&spi_control->transfer_completion, RT_TICK_PER_SECOND*50);
+    if(ret)
+    {
+        rt_kprintf("ERROR: %s, transfer timeout\n", __func__);
+        return -RT_ETIMEOUT;
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 
 void fix_spi_xfer_mode(struct spi_controller *spi_control){
-	 //switch dma or isr....first check dma ...is error .use isr xfer...
-	struct rt_dma_device * rt_dma_dev;
-	struct dma_transfer *tx_trans;
-	struct dma_transfer *rx_trans;
-	int ret;
-	//retry to check if the dma status...
-	if(spi_control->dma.dma_flag == DMA_BIND_OK){
-		//if transfer data too short...use isr..
-		if(spi_control->current_message->length < DMA_OR_ISR_THRESHOLD){
-			spi_control->xfer_mode = XFER_USE_ISR;
-			return;
-		}
+     //switch dma or isr....first check dma ...is error .use isr xfer...
+    struct rt_dma_device * rt_dma_dev;
+    struct dma_transfer *tx_trans;
+    struct dma_transfer *rx_trans;
+    int ret;
+    //retry to check if the dma status...
+    if(spi_control->dma.dma_flag == DMA_BIND_OK){
+        //if transfer data too short...use isr..
+        if(spi_control->current_message->length < DMA_OR_ISR_THRESHOLD){
+            spi_control->xfer_mode = XFER_USE_ISR;
+            return;
+        }
 #if(0)
-		rt_dma_dev = spi_control->dma.dma_dev;
-		//first request channel
+        rt_dma_dev = spi_control->dma.dma_dev;
+        //first request channel
 
-		tx_trans = &spi_control->dma.tx_trans;
-		rx_trans = &spi_control->dma.rx_trans;
-		tx_trans->channel_number = TX_DMA_CHANNEL;
-		rx_trans->channel_number = RX_DMA_CHANNEL;
+        tx_trans = &spi_control->dma.tx_trans;
+        rx_trans = &spi_control->dma.rx_trans;
+        tx_trans->channel_number = TX_DMA_CHANNEL;
+        rx_trans->channel_number = RX_DMA_CHANNEL;
 
 
-		ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL,(void *)tx_trans);
-		if(ret != RT_EOK){
-			spi_control->xfer_mode = XFER_USE_ISR;
-			return;
-		}
+        ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL,(void *)tx_trans);
+        if(ret != RT_EOK){
+            spi_control->xfer_mode = XFER_USE_ISR;
+            return;
+        }
 
-		ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL,(void *)rx_trans);
-		if(ret != RT_EOK){
-			//release tx channel...
-			rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL,(void *)&tx_trans);
-			spi_control->xfer_mode = XFER_USE_ISR;
-			return;
-		}
+        ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL,(void *)rx_trans);
+        if(ret != RT_EOK){
+            //release tx channel...
+            rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL,(void *)&tx_trans);
+            spi_control->xfer_mode = XFER_USE_ISR;
+            return;
+        }
 #endif
-		spi_control->xfer_mode = XFER_USE_DMA;
-		//if error use isr mode
-	}
-	else
-		spi_control->xfer_mode = XFER_USE_ISR;
+        spi_control->xfer_mode = XFER_USE_DMA;
+        //if error use isr mode
+    }
+    else
+        spi_control->xfer_mode = XFER_USE_ISR;
 
 
 
@@ -392,7 +392,7 @@ static rt_uint32_t fh_spi_xfer(struct rt_spi_device* device, struct rt_spi_messa
     spi_control->transfered_len = 0;
     spi_control->received_len = 0;
 
-	rt_sem_take(&spi_control->xfer_lock, RT_WAITING_FOREVER);
+    rt_sem_take(&spi_control->xfer_lock, RT_WAITING_FOREVER);
 
     rt_completion_init(&spi_control->transfer_completion);
 
@@ -400,52 +400,52 @@ static rt_uint32_t fh_spi_xfer(struct rt_spi_device* device, struct rt_spi_messa
     /* take CS */
     if(message->cs_take)
     {
-    	if(spi_slave->plat_slave.actice_level == ACTIVE_LOW)
-    		gpio_direction_output(spi_slave->plat_slave.cs_pin, 0);
-    	else
-    		gpio_direction_output(spi_slave->plat_slave.cs_pin, 1);
+        if(spi_slave->plat_slave.actice_level == ACTIVE_LOW)
+            gpio_direction_output(spi_slave->plat_slave.cs_pin, 0);
+        else
+            gpio_direction_output(spi_slave->plat_slave.cs_pin, 1);
 
-    	//here will always use the slave_0 because that the cs is gpio...
-    	SPI_EnableSlaveen(spi_obj, 0);
+        //here will always use the slave_0 because that the cs is gpio...
+        SPI_EnableSlaveen(spi_obj, 0);
     }
 
     //fix transfer mode .....
     fix_spi_xfer_mode(spi_control);
 
 
-	switch(spi_control->xfer_mode){
-	case XFER_USE_DMA:
-		PRINT_SPI_DBG("use dma xfer.....###############\n");
-		ret = xfer_data_dma(spi_control);
-		if(ret == RT_EOK){
-			break;
-		}
-		else{
-			//use the isr mode to transfer
-			spi_control->xfer_mode = XFER_USE_ISR;
-			rt_kprintf("%s dma transfer error no:%x\n",__func__,ret);
-		}
-	case XFER_USE_ISR:
-		PRINT_SPI_DBG("use isr xfer.....&&&&&&&&&&&&&\n");
-		ret = xfer_data_isr(spi_control);
-		if(ret != RT_EOK)
-			rt_kprintf("%s isr transfer error no:%x\n",__func__,ret);
-		break;
+    switch(spi_control->xfer_mode){
+    case XFER_USE_DMA:
+        PRINT_SPI_DBG("use dma xfer.....###############\n");
+        ret = xfer_data_dma(spi_control);
+        if(ret == RT_EOK){
+            break;
+        }
+        else{
+            //use the isr mode to transfer
+            spi_control->xfer_mode = XFER_USE_ISR;
+            rt_kprintf("%s dma transfer error no:%x\n",__func__,ret);
+        }
+    case XFER_USE_ISR:
+        PRINT_SPI_DBG("use isr xfer.....&&&&&&&&&&&&&\n");
+        ret = xfer_data_isr(spi_control);
+        if(ret != RT_EOK)
+            rt_kprintf("%s isr transfer error no:%x\n",__func__,ret);
+        break;
 
-	default:
-		rt_kprintf("%s unknow xfer func...\n",__func__);
-		while(1)
-			;
-	}
+    default:
+        rt_kprintf("%s unknow xfer func...\n",__func__);
+        while(1)
+            ;
+    }
 
     /* release CS */
     if(message->cs_release)
     {
-    	if(spi_slave->plat_slave.actice_level == ACTIVE_LOW)
-    		gpio_direction_output(spi_slave->plat_slave.cs_pin, 1);
-    	else
-    		gpio_direction_output(spi_slave->plat_slave.cs_pin, 0);
-    	SPI_DisableSlaveen(spi_obj, 0);
+        if(spi_slave->plat_slave.actice_level == ACTIVE_LOW)
+            gpio_direction_output(spi_slave->plat_slave.cs_pin, 1);
+        else
+            gpio_direction_output(spi_slave->plat_slave.cs_pin, 0);
+        SPI_DisableSlaveen(spi_obj, 0);
     }
 
     rt_sem_release(&spi_control->xfer_lock);
@@ -479,73 +479,73 @@ static void fh_spi_interrupt(int irq, void *param)
 
 //
 
-	if(spi_control->current_message == RT_NULL){
-		rt_kprintf("ERROR: %s, current_message is incorrect\n", __func__);
-	}
+    if(spi_control->current_message == RT_NULL){
+        rt_kprintf("ERROR: %s, current_message is incorrect\n", __func__);
+    }
 
-	status =  SPI_InterruptStatus(spi_obj);
-	PRINT_SPI_DBG("status: 0x%x\n", status);
-	//fixme: ??recv overflow, underflow; tran overflow??
-	if(status & SPI_ISR_ERROR){
-		rt_kprintf("ERROR: %s, status=%d\n", __func__, status);
-		SPI_ClearInterrupt(spi_obj);
-		//fixme: handle error
-		return;
-	}
+    status =  SPI_InterruptStatus(spi_obj);
+    PRINT_SPI_DBG("status: 0x%x\n", status);
+    //fixme: ??recv overflow, underflow; tran overflow??
+    if(status & SPI_ISR_ERROR){
+        rt_kprintf("ERROR: %s, status=%d\n", __func__, status);
+        SPI_ClearInterrupt(spi_obj);
+        //fixme: handle error
+        return;
+    }
 
-	rx_fifo_capability = SPI_ReadRxFifoLevel(spi_obj);
-	tx_fifo_capability = MIN(
-			(SPI_FIFO_DEPTH - SPI_ReadTxFifoLevel(spi_obj)) / 2,
-			(spi_control->current_message->length - spi_control->transfered_len));
+    rx_fifo_capability = SPI_ReadRxFifoLevel(spi_obj);
+    tx_fifo_capability = MIN(
+            (SPI_FIFO_DEPTH - SPI_ReadTxFifoLevel(spi_obj)) / 2,
+            (spi_control->current_message->length - spi_control->transfered_len));
 
 
-	PRINT_SPI_DBG("rx_fifo_capability=%d\n", rx_fifo_capability);
+    PRINT_SPI_DBG("rx_fifo_capability=%d\n", rx_fifo_capability);
 
-	//rx
-	spi_control->received_len += rx_fifo_capability;
-	while(rx_fifo_capability)
-	{
-		data = SPI_ReadData(spi_obj);
-		if(spi_control->current_message->recv_buf){
-			*(rt_uint8_t *)spi_control->current_message->recv_buf++ = data;
-		}
-		PRINT_SPI_DBG("rx, data: 0x%x\n", data);
-		//rt_kprintf("rx, data: 0x%x\n", data);
-		rx_fifo_capability--;
-	}
+    //rx
+    spi_control->received_len += rx_fifo_capability;
+    while(rx_fifo_capability)
+    {
+        data = SPI_ReadData(spi_obj);
+        if(spi_control->current_message->recv_buf){
+            *(rt_uint8_t *)spi_control->current_message->recv_buf++ = data;
+        }
+        PRINT_SPI_DBG("rx, data: 0x%x\n", data);
+        //rt_kprintf("rx, data: 0x%x\n", data);
+        rx_fifo_capability--;
+    }
 
-	if(spi_control->received_len == spi_control->current_message->length)
-	{
+    if(spi_control->received_len == spi_control->current_message->length)
+    {
 
-		//rt_kprintf("asdasdq4902834908dklfkldjsdhgkljshfgljkhsgfkljhsdfkljghklj");
-		SPI_DisableInterrupt(spi_obj, SPI_ISR_FLAG);
-		PRINT_SPI_DBG("finished, length=%d, received_len=%d\n", spi_control->current_message->length, spi_control->received_len);
-		rt_completion_done(&spi_control->transfer_completion);
+        //rt_kprintf("asdasdq4902834908dklfkldjsdhgkljshfgljkhsgfkljhsdfkljghklj");
+        SPI_DisableInterrupt(spi_obj, SPI_ISR_FLAG);
+        PRINT_SPI_DBG("finished, length=%d, received_len=%d\n", spi_control->current_message->length, spi_control->received_len);
+        rt_completion_done(&spi_control->transfer_completion);
 
 
-		return;
-	}
+        return;
+    }
 
-	//tx
+    //tx
 
-	spi_control->transfered_len +=tx_fifo_capability;
-	if(spi_control->current_message->send_buf){
-		p = (rt_uint8_t *)spi_control->current_message->send_buf;
-		while(tx_fifo_capability){
-			PRINT_SPI_DBG("tx, data: 0x%x\n", *p);
-			//rt_kprintf("tx, data: 0x%x\n", *p);
-			SPI_WriteData(spi_obj, *p++);
-			tx_fifo_capability--;
-		}
-		spi_control->current_message->send_buf = p;
-	}
-	else{
-		while(tx_fifo_capability){
+    spi_control->transfered_len +=tx_fifo_capability;
+    if(spi_control->current_message->send_buf){
+        p = (rt_uint8_t *)spi_control->current_message->send_buf;
+        while(tx_fifo_capability){
+            PRINT_SPI_DBG("tx, data: 0x%x\n", *p);
+            //rt_kprintf("tx, data: 0x%x\n", *p);
+            SPI_WriteData(spi_obj, *p++);
+            tx_fifo_capability--;
+        }
+        spi_control->current_message->send_buf = p;
+    }
+    else{
+        while(tx_fifo_capability){
 
-			SPI_WriteData(spi_obj, 0xff);
-			tx_fifo_capability--;
-		}
-	}
+            SPI_WriteData(spi_obj, 0xff);
+            tx_fifo_capability--;
+        }
+    }
 
 
 
@@ -568,28 +568,28 @@ int fh_spi_probe(void *priv_data)
     struct spi_control_platform_data *plat_data;
     int i,ret;
 
-	struct rt_dma_device * rt_dma_dev;
-	struct dma_transfer *tx_trans;
-	struct dma_transfer *rx_trans;
+    struct rt_dma_device * rt_dma_dev;
+    struct dma_transfer *tx_trans;
+    struct dma_transfer *rx_trans;
 
     //check data...
     plat_data = (struct spi_control_platform_data *)priv_data;
 
     if(!plat_data){
-		rt_kprintf("ERROR:platform data null...\n");
-		return -RT_ENOMEM;
+        rt_kprintf("ERROR:platform data null...\n");
+        return -RT_ENOMEM;
     }
     if(plat_data->slave_no > FH_SPI_SLAVE_MAX_NO){
-    	rt_kprintf("ERROR:spi controller not support %d slave..\n",plat_data->slave_no);
-    	return -RT_ENOMEM;
+        rt_kprintf("ERROR:spi controller not support %d slave..\n",plat_data->slave_no);
+        return -RT_ENOMEM;
     }
 
 
     //malloc data
     spi_control = (struct spi_controller*)rt_malloc(sizeof(struct spi_controller));
     if(!spi_control){
-    	rt_kprintf("ERROR:no mem for malloc the spi controller..\n");
-    	goto error_malloc_bus;
+        rt_kprintf("ERROR:no mem for malloc the spi controller..\n");
+        goto error_malloc_bus;
     }
 
     rt_memset(spi_control, 0, sizeof(struct spi_controller));
@@ -624,77 +624,77 @@ int fh_spi_probe(void *priv_data)
     if(plat_data->transfer_mode == USE_DMA_TRANSFER){
 
         spi_control->dma.dma_dev = (struct rt_dma_device *)rt_device_find(plat_data->dma_name);
-    	if(spi_control->dma.dma_dev == RT_NULL){
-    		rt_kprintf("can't find dma dev\n");
-    		//goto error_malloc_slave;
-    		//spi_control->dma_xfer_flag = USE_ISR_TRANSFER;
-//    		spi_control->dma.dma_flag = DMA_BIND_ERROR;
-//    		spi_control->xfer_mode = XFER_USE_ISR;
-    		goto BIND_DMA_ERROR;
-    	}
-    	else{
+        if(spi_control->dma.dma_dev == RT_NULL){
+            rt_kprintf("can't find dma dev\n");
+            //goto error_malloc_slave;
+            //spi_control->dma_xfer_flag = USE_ISR_TRANSFER;
+//          spi_control->dma.dma_flag = DMA_BIND_ERROR;
+//          spi_control->xfer_mode = XFER_USE_ISR;
+            goto BIND_DMA_ERROR;
+        }
+        else{
 
-			spi_control->dma.control = spi_control;
-			spi_control->dma.rx_hs = plat_data->rx_hs_no;
-			spi_control->dma.tx_hs = plat_data->tx_hs_no;
-			spi_control->dma.dma_name = plat_data->dma_name;
+            spi_control->dma.control = spi_control;
+            spi_control->dma.rx_hs = plat_data->rx_hs_no;
+            spi_control->dma.tx_hs = plat_data->tx_hs_no;
+            spi_control->dma.dma_name = plat_data->dma_name;
 
-			spi_control->dma.rx_dummy_buff = fh_dma_mem_malloc(MALLOC_DMA_MEM_SIZE);
-			if(!spi_control->dma.rx_dummy_buff){
-				rt_kprintf("malloc rx dma buff failed...\n");
-				//spi_control->xfer_mode = XFER_USE_ISR;
-				goto BIND_DMA_ERROR;
-			}
+            spi_control->dma.rx_dummy_buff = fh_dma_mem_malloc(MALLOC_DMA_MEM_SIZE);
+            if(!spi_control->dma.rx_dummy_buff){
+                rt_kprintf("malloc rx dma buff failed...\n");
+                //spi_control->xfer_mode = XFER_USE_ISR;
+                goto BIND_DMA_ERROR;
+            }
 
 
 
-			spi_control->dma.tx_dummy_buff = fh_dma_mem_malloc(MALLOC_DMA_MEM_SIZE);
-			if(!spi_control->dma.tx_dummy_buff){
-				rt_kprintf("malloc tx dma buff failed...\n");
-				fh_dma_mem_free(spi_control->dma.rx_dummy_buff);
-				//spi_control->xfer_mode = XFER_USE_ISR;
-				goto BIND_DMA_ERROR;
-			}
+            spi_control->dma.tx_dummy_buff = fh_dma_mem_malloc(MALLOC_DMA_MEM_SIZE);
+            if(!spi_control->dma.tx_dummy_buff){
+                rt_kprintf("malloc tx dma buff failed...\n");
+                fh_dma_mem_free(spi_control->dma.rx_dummy_buff);
+                //spi_control->xfer_mode = XFER_USE_ISR;
+                goto BIND_DMA_ERROR;
+            }
 
-			if(((rt_uint32_t)spi_control->dma.tx_dummy_buff % 4)||((rt_uint32_t)spi_control->dma.rx_dummy_buff % 4)){
-				rt_kprintf("dma malloc buff not allign..\n");
-				fh_dma_mem_free(spi_control->dma.rx_dummy_buff);
-				fh_dma_mem_free(spi_control->dma.tx_dummy_buff);
-				goto BIND_DMA_ERROR;
-			}
+            if(((rt_uint32_t)spi_control->dma.tx_dummy_buff % 4)||((rt_uint32_t)spi_control->dma.rx_dummy_buff % 4)){
+                rt_kprintf("dma malloc buff not allign..\n");
+                fh_dma_mem_free(spi_control->dma.rx_dummy_buff);
+                fh_dma_mem_free(spi_control->dma.tx_dummy_buff);
+                goto BIND_DMA_ERROR;
+            }
 
-	    	//open dma dev.
-	    	spi_control->dma.dma_dev->ops->control(spi_control->dma.dma_dev,RT_DEVICE_CTRL_DMA_OPEN,RT_NULL);
+            //open dma dev.
+            spi_control->dma.dma_dev->ops->control(spi_control->dma.dma_dev,RT_DEVICE_CTRL_DMA_OPEN,RT_NULL);
 
-	    	//request channel
-	    	rt_dma_dev = spi_control->dma.dma_dev;
-			//first request channel
-			tx_trans = &spi_control->dma.tx_trans;
-			rx_trans = &spi_control->dma.rx_trans;
-			tx_trans->channel_number = TX_DMA_CHANNEL;
-			rx_trans->channel_number = RX_DMA_CHANNEL;
+            //request channel
+            rt_dma_dev = spi_control->dma.dma_dev;
+            //first request channel
+            tx_trans = &spi_control->dma.tx_trans;
+            rx_trans = &spi_control->dma.rx_trans;
+            tx_trans->channel_number = TX_DMA_CHANNEL;
+            rx_trans->channel_number = RX_DMA_CHANNEL;
 
-			ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL,(void *)tx_trans);
-			if(ret != RT_EOK){
-				goto BIND_DMA_ERROR;
-			}
+            ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL,(void *)tx_trans);
+            if(ret != RT_EOK){
+                goto BIND_DMA_ERROR;
+            }
 
-			ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL,(void *)rx_trans);
-			if(ret != RT_EOK){
-				//release tx channel...
-				rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL,(void *)&tx_trans);
-				goto BIND_DMA_ERROR;
-			}
+            ret = rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_REQUEST_CHANNEL,(void *)rx_trans);
+            if(ret != RT_EOK){
+                //release tx channel...
+                rt_dma_dev->ops->control(rt_dma_dev,RT_DEVICE_CTRL_DMA_RELEASE_CHANNEL,(void *)&tx_trans);
+                goto BIND_DMA_ERROR;
+            }
 
-	    	//spi_control->xfer_mode = XFER_USE_DMA;
-	    	spi_control->dma.dma_flag = DMA_BIND_OK;
-    	}
+            //spi_control->xfer_mode = XFER_USE_DMA;
+            spi_control->dma.dma_flag = DMA_BIND_OK;
+        }
     }
     else{
 
 BIND_DMA_ERROR:
-			spi_control->dma.dma_flag = DMA_BIND_ERROR;
-			//spi_control->xfer_mode = XFER_USE_ISR;
+            spi_control->dma.dma_flag = DMA_BIND_ERROR;
+            //spi_control->xfer_mode = XFER_USE_ISR;
     }
 
 
@@ -702,80 +702,80 @@ BIND_DMA_ERROR:
 
     control_slave = &spi_control->spi_slave;
     for(i=0;islave_no;i++){
-    	spi_slave = (struct spi_slave_info*)rt_malloc(sizeof(struct spi_slave_info));
-    	if(!spi_slave){
-    		rt_kprintf("ERROR:no mem for malloc the spi_slave%d..\n",i);
-    		goto error_malloc_slave;
-    	}
-    	rt_memset(spi_slave, 0, sizeof(struct spi_slave_info));
+        spi_slave = (struct spi_slave_info*)rt_malloc(sizeof(struct spi_slave_info));
+        if(!spi_slave){
+            rt_kprintf("ERROR:no mem for malloc the spi_slave%d..\n",i);
+            goto error_malloc_slave;
+        }
+        rt_memset(spi_slave, 0, sizeof(struct spi_slave_info));
 
-    	//parse platform data...
-    	spi_slave->id = i;
-    	//bind to the spi control....will easy to find all the data...
-    	spi_slave->control = spi_control;
-    	spi_slave->plat_slave.cs_pin = plat_data->plat_slave[i].cs_pin;
-    	spi_slave->plat_slave.actice_level = plat_data->plat_slave[i].actice_level;
-    	rt_sprintf(spi_dev_name, "%s%d%s%d", "ssi", spi_control->id,"_",spi_slave->id);
+        //parse platform data...
+        spi_slave->id = i;
+        //bind to the spi control....will easy to find all the data...
+        spi_slave->control = spi_control;
+        spi_slave->plat_slave.cs_pin = plat_data->plat_slave[i].cs_pin;
+        spi_slave->plat_slave.actice_level = plat_data->plat_slave[i].actice_level;
+        rt_sprintf(spi_dev_name, "%s%d%s%d", "ssi", spi_control->id,"_",spi_slave->id);
 
-    	*control_slave = spi_slave;
-    	control_slave = &spi_slave->next;
+        *control_slave = spi_slave;
+        control_slave = &spi_slave->next;
 
-    	//register slave dev...
-    	ret = rt_spi_bus_attach_device(&spi_slave->spi_device,spi_dev_name,spi_bus_name,spi_slave);
-    	if(ret != RT_EOK){
-    		rt_kprintf("register dev to bus failed...\n");
-    		goto error_malloc_slave;
-    	}
+        //register slave dev...
+        ret = rt_spi_bus_attach_device(&spi_slave->spi_device,spi_dev_name,spi_bus_name,spi_slave);
+        if(ret != RT_EOK){
+            rt_kprintf("register dev to bus failed...\n");
+            goto error_malloc_slave;
+        }
 
     }
 
 
 
     //request gpio...
-	spi_slave = spi_control->spi_slave;
-	while(spi_slave != RT_NULL)
-	{
-		next_slave = spi_slave->next;
+    spi_slave = spi_control->spi_slave;
+    while(spi_slave != RT_NULL)
+    {
+        next_slave = spi_slave->next;
 
-		ret = gpio_request(spi_slave->plat_slave.cs_pin);
-		if(ret!=0){
-			rt_kprintf("request gpio_%d failed...\n",spi_slave->plat_slave.cs_pin);
-			goto error_malloc_slave;
-		}
+        ret = gpio_request(spi_slave->plat_slave.cs_pin);
+        if(ret!=0){
+            rt_kprintf("request gpio_%d failed...\n",spi_slave->plat_slave.cs_pin);
+            goto error_malloc_slave;
+        }
 
 
-		PRINT_SPI_DBG("spi_slave info addr:%x,id:%d,cs:%d,active:%d\n",(rt_uint32_t)spi_slave, spi_slave->id,
-				spi_slave->plat_slave.cs_pin,
-				spi_slave->plat_slave.actice_level);
-		spi_slave = next_slave;
-	}
+        PRINT_SPI_DBG("spi_slave info addr:%x,id:%d,cs:%d,active:%d\n",(rt_uint32_t)spi_slave, spi_slave->id,
+                spi_slave->plat_slave.cs_pin,
+                spi_slave->plat_slave.actice_level);
+        spi_slave = next_slave;
+    }
 
-	//this will be used in platform exit..
-	plat_data->control = spi_control;
+    //this will be used in platform exit..
+    plat_data->control = spi_control;
     return RT_EOK;
 
 error_malloc_slave:
-	//free the slaveinfo already malloc
-	spi_slave = spi_control->spi_slave;
-	while(spi_slave != RT_NULL)
-	{
-		next_slave = spi_slave->next;
-		gpio_release(spi_slave->plat_slave.cs_pin);
-		rt_free(spi_slave);
-		spi_slave = next_slave;
-	}
-	//mask isr
-	rt_hw_interrupt_mask(spi_control->irq);
-	//release sem ..
-	rt_sem_detach(&spi_control->xfer_lock);
+    //free the slaveinfo already malloc
+    spi_slave = spi_control->spi_slave;
+    while(spi_slave != RT_NULL)
+    {
+        next_slave = spi_slave->next;
+        gpio_release(spi_slave->plat_slave.cs_pin);
+        rt_free(spi_slave);
+        spi_slave = next_slave;
+    }
+    //mask isr
+    rt_hw_interrupt_mask(spi_control->irq);
+    //release sem ..
+    rt_sem_detach(&spi_control->xfer_lock);
 
-	//free the control malloc .
-	rt_free(spi_control);
+    //free the control malloc .
+    rt_free(spi_control);
 
-	//fixme:unregister spi_bus...
+    //fixme:unregister spi_bus...
 
 error_malloc_bus:
-	return -RT_ENOMEM;
+    return -RT_ENOMEM;
 
 
 
@@ -793,22 +793,22 @@ int fh_spi_exit(void *priv_data)
 
     plat_data = (struct spi_control_platform_data *)priv_data;
     spi_control = plat_data->control;
-	spi_slave = spi_control->spi_slave;
+    spi_slave = spi_control->spi_slave;
 
-	while(spi_slave != RT_NULL)
-	{
-		next_slave = spi_slave->next;
-		gpio_release(spi_slave->plat_slave.cs_pin);
-		rt_free(spi_slave);
-		spi_slave = next_slave;
-	}
-	//mask isr
-	rt_hw_interrupt_mask(spi_control->irq);
-	//release sem ..
-	rt_sem_detach(&spi_control->xfer_lock);
+    while(spi_slave != RT_NULL)
+    {
+        next_slave = spi_slave->next;
+        gpio_release(spi_slave->plat_slave.cs_pin);
+        rt_free(spi_slave);
+        spi_slave = next_slave;
+    }
+    //mask isr
+    rt_hw_interrupt_mask(spi_control->irq);
+    //release sem ..
+    rt_sem_detach(&spi_control->xfer_lock);
 
-	//free the control malloc .
-	rt_free(spi_control);
+    //free the control malloc .
+    rt_free(spi_control);
     //fixme free all the malloc data ...
 
     return 0;
@@ -835,20 +835,20 @@ void rt_hw_spi_init(void)
 
 }
 #if(0)
-#define TEST_SPI_BUFF_SIZE			0x100
+#define TEST_SPI_BUFF_SIZE          0x100
 static rt_uint8_t tx_buf[TEST_SPI_BUFF_SIZE] = {0};
 static rt_uint8_t rx_buf[TEST_SPI_BUFF_SIZE] = {0};
 int ssi_test(void){
-	struct rt_spi_device * rt_spi_device;
+    struct rt_spi_device * rt_spi_device;
 
-	int ret;
-	rt_spi_device = (struct rt_spi_device *)rt_device_find("ssi1_0");
+    int ret;
+    rt_spi_device = (struct rt_spi_device *)rt_device_find("ssi1_0");
 
-	if(rt_spi_device == RT_NULL)
-	{
-		rt_kprintf("%s spi device %s not found!\r\n",__func__ ,"ssi1_0");
-		return -RT_ENOSYS;
-	}
+    if(rt_spi_device == RT_NULL)
+    {
+        rt_kprintf("%s spi device %s not found!\r\n",__func__ ,"ssi1_0");
+        return -RT_ENOSYS;
+    }
 
     /* config spi */
     {
@@ -865,7 +865,7 @@ int ssi_test(void){
 
     ret = rt_memcmp(tx_buf,rx_buf,TEST_SPI_BUFF_SIZE);
     if(ret != 0){
-    	rt_kprintf("compare error ..error data %x\n",ret);
+        rt_kprintf("compare error ..error data %x\n",ret);
     }
     rt_kprintf("test done \n");
     return 0;
diff --git a/bsp/fh8620/drivers/ssi.h b/bsp/fh8620/drivers/ssi.h
index 3559729ca3..bad2df8381 100644
--- a/bsp/fh8620/drivers/ssi.h
+++ b/bsp/fh8620/drivers/ssi.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #ifndef SSI_H_
 #define SSI_H_
 #include "libraries/inc/fh_driverlib.h"
@@ -32,37 +32,37 @@
 #include "fh_dma.h"
 #define SPI_PRIV(drv)   ( (struct fh_spi_obj)(drv->priv) )
 
-#define FH_SPI_SLAVE_MAX_NO			2
+#define FH_SPI_SLAVE_MAX_NO         2
 
 struct spi_controller;
 //platform use below
 struct spi_slave_platform_data{
 
-	rt_uint32_t cs_pin;
-#define ACTIVE_LOW			1
-#define ACTIVE_HIGH			2
-	rt_uint32_t actice_level;
+    rt_uint32_t cs_pin;
+#define ACTIVE_LOW          1
+#define ACTIVE_HIGH         2
+    rt_uint32_t actice_level;
 };
 
 
 struct spi_control_platform_data{
-	rt_uint32_t id;
-	rt_uint32_t irq;
-	rt_uint32_t base;
-	rt_uint32_t max_hz;
-	rt_uint32_t slave_no;
-	rt_uint32_t clk_in;
-	//handshake no...
-	rt_uint32_t rx_hs_no;
-	rt_uint32_t tx_hs_no;
+    rt_uint32_t id;
+    rt_uint32_t irq;
+    rt_uint32_t base;
+    rt_uint32_t max_hz;
+    rt_uint32_t slave_no;
+    rt_uint32_t clk_in;
+    //handshake no...
+    rt_uint32_t rx_hs_no;
+    rt_uint32_t tx_hs_no;
 
-	char *dma_name;
-	//isr will be the default...
-#define USE_ISR_TRANSFER			0
-#define USE_DMA_TRANSFER			1
-	rt_uint32_t transfer_mode;
-	struct spi_controller *control;
-	struct spi_slave_platform_data plat_slave[FH_SPI_SLAVE_MAX_NO];
+    char *dma_name;
+    //isr will be the default...
+#define USE_ISR_TRANSFER            0
+#define USE_DMA_TRANSFER            1
+    rt_uint32_t transfer_mode;
+    struct spi_controller *control;
+    struct spi_slave_platform_data plat_slave[FH_SPI_SLAVE_MAX_NO];
 
 };
 
@@ -81,15 +81,15 @@ struct spi_slave_info
 
 struct spi_dma
 {
-	char *dma_name;
-#define DMA_BIND_OK			0
-#define DMA_BIND_ERROR		1
-	rt_uint32_t dma_flag;
+    char *dma_name;
+#define DMA_BIND_OK         0
+#define DMA_BIND_ERROR      1
+    rt_uint32_t dma_flag;
     //bind to the dma dev..
-	rt_uint32_t rx_hs;
-	rt_uint32_t tx_hs;
-	rt_uint8_t *rx_dummy_buff;
-	rt_uint8_t *tx_dummy_buff;
+    rt_uint32_t rx_hs;
+    rt_uint32_t tx_hs;
+    rt_uint8_t *rx_dummy_buff;
+    rt_uint8_t *tx_dummy_buff;
     struct rt_dma_device *dma_dev;
     struct dma_transfer tx_trans;
     struct dma_transfer rx_trans;
@@ -98,28 +98,28 @@ struct spi_dma
 
 struct spi_controller
 {
-	rt_uint32_t id;
-	rt_uint32_t irq;
-	rt_uint32_t base;
-	rt_uint32_t max_hz;
-	rt_uint32_t slave_no;
-	rt_uint32_t clk_in;
-	//bind to the platform data....
-	struct spi_control_platform_data *plat_data;
+    rt_uint32_t id;
+    rt_uint32_t irq;
+    rt_uint32_t base;
+    rt_uint32_t max_hz;
+    rt_uint32_t slave_no;
+    rt_uint32_t clk_in;
+    //bind to the platform data....
+    struct spi_control_platform_data *plat_data;
 
-	//rt_uint32_t dma_xfer_flag;
+    //rt_uint32_t dma_xfer_flag;
 
-#define XFER_USE_ISR		0
-#define XFER_USE_DMA		1
-	rt_uint32_t xfer_mode;
+#define XFER_USE_ISR        0
+#define XFER_USE_DMA        1
+    rt_uint32_t xfer_mode;
 
-	struct spi_dma dma;
-	rt_uint32_t dma_complete_times;
+    struct spi_dma dma;
+    rt_uint32_t dma_complete_times;
     struct rt_spi_bus spi_bus;
     struct spi_slave_info *spi_slave;
     struct rt_spi_message* current_message;
     struct rt_completion transfer_completion;
-	struct rt_semaphore xfer_lock;
+    struct rt_semaphore xfer_lock;
     struct fh_spi_obj obj;
     rt_uint32_t received_len;
     rt_uint32_t transfered_len;
diff --git a/bsp/fh8620/drivers/trap.c b/bsp/fh8620/drivers/trap.c
index 7d81057956..b12004918a 100644
--- a/bsp/fh8620/drivers/trap.c
+++ b/bsp/fh8620/drivers/trap.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #include 
 #include 
 #include "fh_arch.h"
@@ -47,13 +47,13 @@ extern long list_thread(void);
 
 void rt_hw_show_register (struct rt_hw_register *regs)
 {
-	rt_kprintf("Execption:\n");
-	rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
-	rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
-	rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
-	rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
-	rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
-	rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
+    rt_kprintf("Execption:\n");
+    rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
+    rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
+    rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
+    rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
+    rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
+    rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
 }
 
 /**
@@ -66,15 +66,15 @@ void rt_hw_show_register (struct rt_hw_register *regs)
  */
 void rt_hw_trap_udef(struct rt_hw_register *regs)
 {
-	rt_hw_show_register(regs);
+    rt_hw_show_register(regs);
 
-	rt_kprintf("undefined instruction\n");
-	rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
+    rt_kprintf("undefined instruction\n");
+    rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
 
 #ifdef RT_USING_FINSH
-	list_thread();
+    list_thread();
 #endif
-	rt_hw_cpu_shutdown();
+    rt_hw_cpu_shutdown();
 }
 
 /**
@@ -88,10 +88,10 @@ void rt_hw_trap_udef(struct rt_hw_register *regs)
  */
 void rt_hw_trap_swi(struct rt_hw_register *regs)
 {
-	rt_hw_show_register(regs);
+    rt_hw_show_register(regs);
 
-	rt_kprintf("software interrupt\n");
-	rt_hw_cpu_shutdown();
+    rt_kprintf("software interrupt\n");
+    rt_hw_cpu_shutdown();
 }
 
 /**
@@ -104,15 +104,15 @@ void rt_hw_trap_swi(struct rt_hw_register *regs)
  */
 void rt_hw_trap_pabt(struct rt_hw_register *regs)
 {
-	rt_hw_show_register(regs);
+    rt_hw_show_register(regs);
 
-	rt_kprintf("prefetch abort\n");
-	rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
+    rt_kprintf("prefetch abort\n");
+    rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
 
 #ifdef RT_USING_FINSH
-	list_thread();
+    list_thread();
 #endif
-	rt_hw_cpu_shutdown();
+    rt_hw_cpu_shutdown();
 }
 
 /**
@@ -125,15 +125,15 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs)
  */
 void rt_hw_trap_dabt(struct rt_hw_register *regs)
 {
-	rt_hw_show_register(regs);
+    rt_hw_show_register(regs);
 
-	rt_kprintf("data abort\n");
-	rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
+    rt_kprintf("data abort\n");
+    rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
 
 #ifdef RT_USING_FINSH
-	list_thread();
+    list_thread();
 #endif
-	rt_hw_cpu_shutdown();
+    rt_hw_cpu_shutdown();
 }
 
 /**
@@ -145,45 +145,45 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs)
  */
 void rt_hw_trap_resv(struct rt_hw_register *regs)
 {
-	rt_kprintf("not used\n");
-	rt_hw_show_register(regs);
-	rt_hw_cpu_shutdown();
+    rt_kprintf("not used\n");
+    rt_hw_show_register(regs);
+    rt_hw_cpu_shutdown();
 }
 
 extern struct rt_irq_desc irq_desc[];
 
 void rt_hw_trap_irq()
 {
-	rt_isr_handler_t isr_func;
-	rt_uint32_t irqstat_l, irqstat_h, irq;
-	void *param;
+    rt_isr_handler_t isr_func;
+    rt_uint32_t irqstat_l, irqstat_h, irq;
+    void *param;
 
-	fh_intc *p = (fh_intc *)INTC_REG_BASE;
+    fh_intc *p = (fh_intc *)INTC_REG_BASE;
 
-	irqstat_l = p->IRQ_FINALSTATUS_L;
-	irqstat_h = p->IRQ_FINALSTATUS_H;
-	if (irqstat_l)
-	{
-		irq = __rt_ffs(irqstat_l) - 1;
-	}
-	else if(irqstat_h)
-	{
-		irq = __rt_ffs(irqstat_h) - 1 + 32;
-	}
-	else
-	{
-		rt_kprintf("No interrupt occur\n");
-		return;
-	}
+    irqstat_l = p->IRQ_FINALSTATUS_L;
+    irqstat_h = p->IRQ_FINALSTATUS_H;
+    if (irqstat_l)
+    {
+        irq = __rt_ffs(irqstat_l) - 1;
+    }
+    else if(irqstat_h)
+    {
+        irq = __rt_ffs(irqstat_h) - 1 + 32;
+    }
+    else
+    {
+        rt_kprintf("No interrupt occur\n");
+        return;
+    }
 
-	/* get interrupt service routine */
-	isr_func = irq_desc[irq].handler;
-	param = irq_desc[irq].param;
+    /* get interrupt service routine */
+    isr_func = irq_desc[irq].handler;
+    param = irq_desc[irq].param;
 
-	/* turn to interrupt service routine */
-	if(isr_func){
-		isr_func(irq, param);
-	}
+    /* turn to interrupt service routine */
+    if(isr_func){
+        isr_func(irq, param);
+    }
 #ifdef RT_USING_INTERRUPT_INFO
     irq_desc[irq].counter ++;
 #endif
@@ -191,7 +191,7 @@ void rt_hw_trap_irq()
 
 void rt_hw_trap_fiq()
 {
-	rt_kprintf("fast interrupt request\n");
+    rt_kprintf("fast interrupt request\n");
 }
 
 /*@}*/
diff --git a/bsp/fh8620/drivers/uart.c b/bsp/fh8620/drivers/uart.c
index 4b264d9206..89df32d753 100644
--- a/bsp/fh8620/drivers/uart.c
+++ b/bsp/fh8620/drivers/uart.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #include 
 #include 
 #include "fh_arch.h"
@@ -32,35 +32,35 @@
 
 void rt_fh_uart_handler(int vector, void *param)
 {
-	int status;
-	unsigned int ret;
-	struct fh_uart *uart;
-	unsigned int reg_status;
-	rt_device_t dev = (rt_device_t)param;
-	uart = (struct fh_uart *)dev->user_data;
-	status = uart_get_iir_status(uart->uart_port);
-	if (status & UART_IIR_NOINT)
-	{
-		return;
-	}
-	if(status & UART_IIR_THREMPTY){
-		//first close tx isr
-		uart_disable_irq(uart->uart_port,UART_IER_ETBEI);
+    int status;
+    unsigned int ret;
+    struct fh_uart *uart;
+    unsigned int reg_status;
+    rt_device_t dev = (rt_device_t)param;
+    uart = (struct fh_uart *)dev->user_data;
+    status = uart_get_iir_status(uart->uart_port);
+    if (status & UART_IIR_NOINT)
+    {
+        return;
+    }
+    if(status & UART_IIR_THREMPTY){
+        //first close tx isr
+        uart_disable_irq(uart->uart_port,UART_IER_ETBEI);
 
-		rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_TX_DONE);
-	}
-	else if((status & UART_IIR_CHRTOUT)==UART_IIR_CHRTOUT){
-		//bug....
-		//if no data in rx fifo
-		reg_status = uart_get_status(uart->uart_port);
-		if((reg_status & 1<<3) == 0)
-			ret = uart_getc(uart->uart_port);
-	}
-	else{
-		rt_interrupt_enter();
-		rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND);
-		rt_interrupt_leave();
-	}
+        rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_TX_DONE);
+    }
+    else if((status & UART_IIR_CHRTOUT)==UART_IIR_CHRTOUT){
+        //bug....
+        //if no data in rx fifo
+        reg_status = uart_get_status(uart->uart_port);
+        if((reg_status & 1<<3) == 0)
+            ret = uart_getc(uart->uart_port);
+    }
+    else{
+        rt_interrupt_enter();
+        rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND);
+        rt_interrupt_leave();
+    }
 }
 
 /**
@@ -69,67 +69,67 @@ void rt_fh_uart_handler(int vector, void *param)
 static rt_err_t fh_uart_configure(struct rt_serial_device *serial,
                                 struct serial_configure *cfg)
 {
-	int div;
-	enum data_bits data_mode;
-	enum stop_bits stop_mode;
-	enum parity parity_mode;
-	struct fh_uart *uart;
+    int div;
+    enum data_bits data_mode;
+    enum stop_bits stop_mode;
+    enum parity parity_mode;
+    struct fh_uart *uart;
 
-	RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(serial != RT_NULL);
     RT_ASSERT(cfg != RT_NULL);
-	uart = (struct fh_uart *)serial->parent.user_data;
+    uart = (struct fh_uart *)serial->parent.user_data;
 
-	switch (cfg->data_bits)
-	{
-	case DATA_BITS_8:
-		data_mode = UART_DATA_BIT8;
-		break;
-	case DATA_BITS_7:
-		data_mode = UART_DATA_BIT7;
-		break;
-	case DATA_BITS_6:
-		data_mode = UART_DATA_BIT6;
-		break;
-	case DATA_BITS_5:
-		data_mode = UART_DATA_BIT5;
-		break;
-	default:
-		data_mode = UART_DATA_BIT8;
-		break;
-	}
+    switch (cfg->data_bits)
+    {
+    case DATA_BITS_8:
+        data_mode = UART_DATA_BIT8;
+        break;
+    case DATA_BITS_7:
+        data_mode = UART_DATA_BIT7;
+        break;
+    case DATA_BITS_6:
+        data_mode = UART_DATA_BIT6;
+        break;
+    case DATA_BITS_5:
+        data_mode = UART_DATA_BIT5;
+        break;
+    default:
+        data_mode = UART_DATA_BIT8;
+        break;
+    }
 
-	switch (cfg->stop_bits)
-	{
-	case STOP_BITS_2:
-		stop_mode = UART_STOP_BIT2;
-		break;
-	case STOP_BITS_1:
-	default:
-		stop_mode = UART_STOP_BIT1;
-		break;
-	}
+    switch (cfg->stop_bits)
+    {
+    case STOP_BITS_2:
+        stop_mode = UART_STOP_BIT2;
+        break;
+    case STOP_BITS_1:
+    default:
+        stop_mode = UART_STOP_BIT1;
+        break;
+    }
 
-	switch (cfg->parity)
-	{
-	case PARITY_ODD:
-		parity_mode = UART_PARITY_ODD;
-		break;
-	case PARITY_EVEN:
-		parity_mode = UART_PARITY_EVEN;
-		break;
-	case PARITY_NONE:
-	default:
-		parity_mode = UART_PARITY_NONE;
-		break;
-	}
+    switch (cfg->parity)
+    {
+    case PARITY_ODD:
+        parity_mode = UART_PARITY_ODD;
+        break;
+    case PARITY_EVEN:
+        parity_mode = UART_PARITY_EVEN;
+        break;
+    case PARITY_NONE:
+    default:
+        parity_mode = UART_PARITY_NONE;
+        break;
+    }
 
     uart_disable_irq(uart->uart_port, UART_IER_ERBFI);
 
-	uart_configure(uart->uart_port, data_mode,
-					stop_mode, parity_mode,
-					cfg->baud_rate, UART_CLOCK_FREQ);
+    uart_configure(uart->uart_port, data_mode,
+                    stop_mode, parity_mode,
+                    cfg->baud_rate, UART_CLOCK_FREQ);
 
-	uart_enable_irq(uart->uart_port, UART_IER_ERBFI);
+    uart_enable_irq(uart->uart_port, UART_IER_ERBFI);
 
     return RT_EOK;
 }
@@ -146,13 +146,13 @@ static rt_err_t fh_uart_control(struct rt_serial_device *serial,
     {
     case RT_DEVICE_CTRL_CLR_INT:
         /* disable rx irq */
-		rt_hw_interrupt_mask(uart->irq);
-		uart_disable_irq(uart->uart_port,UART_IER_ERBFI);
+        rt_hw_interrupt_mask(uart->irq);
+        uart_disable_irq(uart->uart_port,UART_IER_ERBFI);
         break;
     case RT_DEVICE_CTRL_SET_INT:
         /* enable rx irq */
-		rt_hw_interrupt_umask(uart->irq);
-		uart_enable_irq(uart->uart_port,UART_IER_ERBFI);
+        rt_hw_interrupt_umask(uart->irq);
+        uart_enable_irq(uart->uart_port,UART_IER_ERBFI);
         break;
     }
 
@@ -161,33 +161,33 @@ static rt_err_t fh_uart_control(struct rt_serial_device *serial,
 
 static int fh_uart_putc(struct rt_serial_device *serial, char c)
 {
-	struct fh_uart *uart = serial->parent.user_data;
-	unsigned int ret;
-	ret = uart_get_status(uart->uart_port);
-	if(serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX){
-		//RT_DEVICE_FLAG_INT_TX
+    struct fh_uart *uart = serial->parent.user_data;
+    unsigned int ret;
+    ret = uart_get_status(uart->uart_port);
+    if(serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX){
+        //RT_DEVICE_FLAG_INT_TX
 
-		if(c == '\n'){
-			fh_uart_putc(serial,'\r');
-		}
-		if(ret & UART_USR_TFNF){
-			uart_putc(uart->uart_port, c);
-			return 1;
-		}
-		//open tx isr here..
-		uart_enable_irq(uart->uart_port,UART_IER_ETBEI);
-	    return -1;
-	}
-	//poll mode
-	else{
+        if(c == '\n'){
+            fh_uart_putc(serial,'\r');
+        }
+        if(ret & UART_USR_TFNF){
+            uart_putc(uart->uart_port, c);
+            return 1;
+        }
+        //open tx isr here..
+        uart_enable_irq(uart->uart_port,UART_IER_ETBEI);
+        return -1;
+    }
+    //poll mode
+    else{
 
-		while(!(uart_get_status(uart->uart_port) & UART_USR_TFNF))
-			;
-		uart_putc(uart->uart_port, c);
-		return 1;
+        while(!(uart_get_status(uart->uart_port) & UART_USR_TFNF))
+            ;
+        uart_putc(uart->uart_port, c);
+        return 1;
 
 
-	}
+    }
 
 
 
@@ -196,16 +196,16 @@ static int fh_uart_putc(struct rt_serial_device *serial, char c)
 static int fh_uart_getc(struct rt_serial_device *serial)
 {
     int result;
-	struct fh_uart *uart = serial->parent.user_data;
+    struct fh_uart *uart = serial->parent.user_data;
 
-	if (uart_is_rx_ready(uart->uart_port))
-	{
-		result = uart_getc(uart->uart_port);
-	}
-	else
-	{
-		result = -1;
-	}
+    if (uart_is_rx_ready(uart->uart_port))
+    {
+        result = uart_getc(uart->uart_port);
+    }
+    else
+    {
+        result = -1;
+    }
 
     return result;
 }
@@ -222,8 +222,8 @@ static const struct rt_uart_ops fh_uart_ops =
 #if defined(RT_USING_UART0)
 static struct rt_serial_device serial0;
 struct fh_uart uart0 = {
-	(uart *)UART0_REG_BASE,
-	UART0_IRQn
+    (uart *)UART0_REG_BASE,
+    UART0_IRQn
 };
 
 #endif
@@ -231,8 +231,8 @@ struct fh_uart uart0 = {
 #if defined(RT_USING_UART1)
 static struct rt_serial_device serial1;
 struct fh_uart uart1 = {
-	(uart *)UART1_REG_BASE,
-	UART1_IRQn
+    (uart *)UART1_REG_BASE,
+    UART1_IRQn
 };
 
 #endif
@@ -245,45 +245,45 @@ struct fh_uart uart1 = {
  */
 void rt_hw_uart_init(void)
 {
-	struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
 
 #if defined(RT_USING_UART0)
 #if(0)
-	serial0.ops = &fh_uart_ops;
-	serial0.config = config;
+    serial0.ops = &fh_uart_ops;
+    serial0.config = config;
 
-	/* register vcom device */
-	rt_hw_serial_register(&serial0, "uart0",
-			RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_STANDALONE,
-			&uart0);
-	rt_hw_interrupt_install(uart0.irq, rt_fh_uart_handler,
-			(void *)&(serial0.parent), "UART0");
-	rt_hw_interrupt_umask(uart0.irq);
+    /* register vcom device */
+    rt_hw_serial_register(&serial0, "uart0",
+            RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_STANDALONE,
+            &uart0);
+    rt_hw_interrupt_install(uart0.irq, rt_fh_uart_handler,
+            (void *)&(serial0.parent), "UART0");
+    rt_hw_interrupt_umask(uart0.irq);
 #endif
-	serial0.ops = &fh_uart_ops;
-	serial0.config = config;
+    serial0.ops = &fh_uart_ops;
+    serial0.config = config;
 
-	/* register vcom device */
-	rt_hw_serial_register(&serial0, "uart0",
-			RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM ,
-			&uart0);
-	rt_hw_interrupt_install(uart0.irq, rt_fh_uart_handler,
-			(void *)&(serial0.parent), "UART0");
-	rt_hw_interrupt_umask(uart0.irq);
+    /* register vcom device */
+    rt_hw_serial_register(&serial0, "uart0",
+            RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM ,
+            &uart0);
+    rt_hw_interrupt_install(uart0.irq, rt_fh_uart_handler,
+            (void *)&(serial0.parent), "UART0");
+    rt_hw_interrupt_umask(uart0.irq);
 
 #endif
 
 #if defined(RT_USING_UART1)
-	serial1.ops = &fh_uart_ops;
-	serial1.config = config;
+    serial1.ops = &fh_uart_ops;
+    serial1.config = config;
 
-	/* register vcom device */
-	rt_hw_serial_register(&serial1, "uart1",
-			RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM ,
-			&uart1);
-	rt_hw_interrupt_install(uart1.irq, rt_fh_uart_handler,
-			(void *)&(serial1.parent), "UART1");
-	rt_hw_interrupt_umask(uart1.irq);
+    /* register vcom device */
+    rt_hw_serial_register(&serial1, "uart1",
+            RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM ,
+            &uart1);
+    rt_hw_interrupt_install(uart1.irq, rt_fh_uart_handler,
+            (void *)&(serial1.parent), "UART1");
+    rt_hw_interrupt_umask(uart1.irq);
 
 #endif
 
diff --git a/bsp/fh8620/drivers/uart.h b/bsp/fh8620/drivers/uart.h
index d4459f02f8..c7af24523b 100644
--- a/bsp/fh8620/drivers/uart.h
+++ b/bsp/fh8620/drivers/uart.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #ifndef UART_H_
 #define UART_H_
 
diff --git a/bsp/fh8620/drivers/wdt.c b/bsp/fh8620/drivers/wdt.c
index 1d67007a6a..f7f292df86 100644
--- a/bsp/fh8620/drivers/wdt.c
+++ b/bsp/fh8620/drivers/wdt.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #include "fh_def.h"
 #include "wdt.h"
 #include "interrupt.h"
diff --git a/bsp/fh8620/drivers/wdt.h b/bsp/fh8620/drivers/wdt.h
index 768a2e0739..71673d24aa 100644
--- a/bsp/fh8620/drivers/wdt.h
+++ b/bsp/fh8620/drivers/wdt.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #ifndef WDT_H_
 #define WDT_H_
 
diff --git a/bsp/fh8620/libraries/driverlib/fh_gpio.c b/bsp/fh8620/libraries/driverlib/fh_gpio.c
index e3e58f9a1f..7c39386968 100644
--- a/bsp/fh8620/libraries/driverlib/fh_gpio.c
+++ b/bsp/fh8620/libraries/driverlib/fh_gpio.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,10 +18,10 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
- 
\ No newline at end of file
+
+
diff --git a/bsp/fh8620/libraries/driverlib/fh_i2c.c b/bsp/fh8620/libraries/driverlib/fh_i2c.c
index 661703e71c..cc91561b9f 100644
--- a/bsp/fh8620/libraries/driverlib/fh_i2c.c
+++ b/bsp/fh8620/libraries/driverlib/fh_i2c.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #include "inc/fh_driverlib.h"
 
 int I2C_WaitMasterIdle(struct fh_i2c_obj *i2c_obj)
diff --git a/bsp/fh8620/libraries/driverlib/fh_ictl.c b/bsp/fh8620/libraries/driverlib/fh_ictl.c
index a53c8dba34..10edbb27ff 100644
--- a/bsp/fh8620/libraries/driverlib/fh_ictl.c
+++ b/bsp/fh8620/libraries/driverlib/fh_ictl.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,25 +18,25 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #include "inc/fh_driverlib.h"
 
 
 
 void ictl_close_all_isr(fh_intc *p){
-	if(p){
-		//enable all interrupts
-		p->IRQ_EN_L = 0xffffffff;
-		p->IRQ_EN_H = 0xffffffff;
-		//mask all  interrupts
-		p->IRQ_MASK_L = 0xffffffff;
-		p->IRQ_MASK_H = 0xffffffff;
-	}
+    if(p){
+        //enable all interrupts
+        p->IRQ_EN_L = 0xffffffff;
+        p->IRQ_EN_H = 0xffffffff;
+        //mask all  interrupts
+        p->IRQ_MASK_L = 0xffffffff;
+        p->IRQ_MASK_H = 0xffffffff;
+    }
 
 }
 
@@ -44,13 +44,13 @@ void ictl_close_all_isr(fh_intc *p){
 
 
 void ictl_mask_isr(fh_intc *p,int irq){
-	if(p){
+    if(p){
 
-		if (irq < 32)
-	    	p->IRQ_MASK_L |= (1 << irq);
-		else
-			p->IRQ_MASK_H |= (1 << (irq - 32));
-	}
+        if (irq < 32)
+            p->IRQ_MASK_L |= (1 << irq);
+        else
+            p->IRQ_MASK_H |= (1 << (irq - 32));
+    }
 }
 
 
@@ -58,12 +58,12 @@ void ictl_mask_isr(fh_intc *p,int irq){
 
 
 void ictl_unmask_isr(fh_intc *p,int irq){
-	if(p){
-	    if (irq < 32)
-	    	p->IRQ_MASK_L &= ~(1 << irq);
-		else
-			p->IRQ_MASK_H &= ~(1 << (irq - 32));
+    if(p){
+        if (irq < 32)
+            p->IRQ_MASK_L &= ~(1 << irq);
+        else
+            p->IRQ_MASK_H &= ~(1 << (irq - 32));
 
-	}
+    }
 
 }
diff --git a/bsp/fh8620/libraries/driverlib/fh_mmc.c b/bsp/fh8620/libraries/driverlib/fh_mmc.c
index 4a4370b9fa..0b644d29e5 100644
--- a/bsp/fh8620/libraries/driverlib/fh_mmc.c
+++ b/bsp/fh8620/libraries/driverlib/fh_mmc.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
@@ -194,7 +194,6 @@ int MMC_SetCardWidth(struct fh_mmc_obj *mmc_obj, int width)
     default:
         rt_kprintf("ERROR: %s, card width %d is not supported\n", __func__, width);
         return -RT_ERROR;
-        break;
     }
     return 0;
 }
diff --git a/bsp/fh8620/libraries/driverlib/fh_pwm.c b/bsp/fh8620/libraries/driverlib/fh_pwm.c
index af19110a46..7b71e78f2b 100644
--- a/bsp/fh8620/libraries/driverlib/fh_pwm.c
+++ b/bsp/fh8620/libraries/driverlib/fh_pwm.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/fh8620/libraries/driverlib/fh_sdio.c b/bsp/fh8620/libraries/driverlib/fh_sdio.c
index 8c9e69e07d..edc4151068 100644
--- a/bsp/fh8620/libraries/driverlib/fh_sdio.c
+++ b/bsp/fh8620/libraries/driverlib/fh_sdio.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
@@ -34,15 +34,15 @@
 #define SDC_USE_IDMA
 
 #define INSTRUCTIONS_PER_USEC          1000
-#define CMD_TIMEOUT_USEC 	               100000 
-#define DATA_READY_TIMEOUT_USEC 	200000
+#define CMD_TIMEOUT_USEC                   100000
+#define DATA_READY_TIMEOUT_USEC     200000
 #define DMA_TRANSFER_TIMEOUT_TICKS 300
 #define DATA_TRANSFER_OVER_TIMEOUT_USEC 1000
 #define ACMD41_RETRY_COUNT                             1000//100000
 
-#define CIU_CLK		       50000//25000//25000 //27MHz
-#define MMC_FOD_VALUE  125	/* 125 KHz */
-#define NORM_FOD_VALUE  25000//5000//25000	/* 25 MHz */
+#define CIU_CLK            50000//25000//25000 //27MHz
+#define MMC_FOD_VALUE  125  /* 125 KHz */
+#define NORM_FOD_VALUE  25000//5000//25000  /* 25 MHz */
 #define MMC_FOD_DIVIDER_VALUE   (((CIU_CLK+MMC_FOD_VALUE*2-1)/(MMC_FOD_VALUE*2)))
 #ifdef SDCARD_CLK_DIVIDER
 #define ONE_BIT_BUS_FREQ   SDCARD_CLK_DIVIDER
@@ -56,1118 +56,1118 @@ static sdc_t sdc_array[2];
 
 static void plat_loop(unsigned int macrosecond)
 {
-	unsigned int clk;
-	
-	while (macrosecond-- > 0) {
-		for(clk=INSTRUCTIONS_PER_USEC; clk>0; clk--);
-	}
+    unsigned int clk;
+
+    while (macrosecond-- > 0) {
+        for(clk=INSTRUCTIONS_PER_USEC; clk>0; clk--);
+    }
 }
 
 static int synopmob_execute_command(unsigned int base, unsigned int cmd_register, unsigned int arg_register)
 {
-	unsigned int retries = CMD_TIMEOUT_USEC;
+    unsigned int retries = CMD_TIMEOUT_USEC;
 
-	synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts, FIXME
-	synopmob_set_register(base+CMDARG, arg_register);
-	synopmob_set_register(base+CMD, cmd_register | (0x80000000|0x20000000/*fixed to use hold*/));
+    synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts, FIXME
+    synopmob_set_register(base+CMDARG, arg_register);
+    synopmob_set_register(base+CMD, cmd_register | (0x80000000|0x20000000/*fixed to use hold*/));
 
-	while (retries-- > 0) {
-		if (!(synopmob_read_register(base+CMD) & 0x80000000/*CMD done bit*/))
-			return 0;
-		plat_loop(1);
-	}
-	
-	return ERRCMDRETRIESOVER;
+    while (retries-- > 0) {
+        if (!(synopmob_read_register(base+CMD) & 0x80000000/*CMD done bit*/))
+            return 0;
+        plat_loop(1);
+    }
+
+    return ERRCMDRETRIESOVER;
 }
 
 static int synopmob_wait_command_done(unsigned int base, unsigned int* inst, unsigned int flag)
 {
-	unsigned int retries = CMD_TIMEOUT_USEC;
-	unsigned int sts;
+    unsigned int retries = CMD_TIMEOUT_USEC;
+    unsigned int sts;
 
-	while (retries-- > 0) {
-		sts = synopmob_read_register(base+RINTSTS);
-		if (sts && ((sts & flag) == flag) ) {
-			*inst = sts;
-			return 0;
-		}
-		plat_loop(1);
-	}
-	return ERRCMDRETRIESOVER;
+    while (retries-- > 0) {
+        sts = synopmob_read_register(base+RINTSTS);
+        if (sts && ((sts & flag) == flag) ) {
+            *inst = sts;
+            return 0;
+        }
+        plat_loop(1);
+    }
+    return ERRCMDRETRIESOVER;
 }
 
 static int synopmob_wait_data_ready(unsigned int base)
 {
-	unsigned int retries = DATA_READY_TIMEOUT_USEC;
+    unsigned int retries = DATA_READY_TIMEOUT_USEC;
 
-	while (retries-- > 0) {
-		if  (!((synopmob_read_register(base+STATUS)) & 0x00000200)) {
-			return 0;
-		}
-		
-		plat_loop(1);
-	}
-	return ERRDATANOTREADY;
+    while (retries-- > 0) {
+        if  (!((synopmob_read_register(base+STATUS)) & 0x00000200)) {
+            return 0;
+        }
+
+        plat_loop(1);
+    }
+    return ERRDATANOTREADY;
 }
 
 static int synopmob_handle_standard_rinsts(unsigned int raw_int_stat)
 {
-	int error_status = 0;
-	
-	if ( raw_int_stat &  INTMASK_ERROR) {
-		if (raw_int_stat & INTMSK_RESP_ERR) {
-			error_status = ERRRESPRECEP;
-		}
-		if (raw_int_stat & INTMSK_RCRC) {
-			error_status = ERRRESPCRC;
-		}
-		if (raw_int_stat & INTMSK_DCRC) {
-			error_status = ERRDCRC;
-		}		
-		if (raw_int_stat & INTMSK_RTO) {
-			error_status = ERRRESPTIMEOUT;
-		}		
-		if (raw_int_stat & INTMSK_DTO) {
-			error_status = ERRDRTIMEOUT;
-		}
-		if (raw_int_stat & INTMSK_HTO) {
-			error_status = ERRUNDERWRITE;
-		}
-		if (raw_int_stat & INTMSK_FRUN) {
-			error_status = ERROVERREAD;
-		}
-		if (raw_int_stat & INTMSK_HLE) {
-			error_status = ERRHLE;
-		}
-		if (raw_int_stat & INTMSK_SBE) {
-			error_status = ERRSTARTBIT;
-		}		
-		if (raw_int_stat & INTMSK_EBE) {
-			error_status = ERRENDBITERR;
-		}
-	}
+    int error_status = 0;
+
+    if ( raw_int_stat &  INTMASK_ERROR) {
+        if (raw_int_stat & INTMSK_RESP_ERR) {
+            error_status = ERRRESPRECEP;
+        }
+        if (raw_int_stat & INTMSK_RCRC) {
+            error_status = ERRRESPCRC;
+        }
+        if (raw_int_stat & INTMSK_DCRC) {
+            error_status = ERRDCRC;
+        }
+        if (raw_int_stat & INTMSK_RTO) {
+            error_status = ERRRESPTIMEOUT;
+        }
+        if (raw_int_stat & INTMSK_DTO) {
+            error_status = ERRDRTIMEOUT;
+        }
+        if (raw_int_stat & INTMSK_HTO) {
+            error_status = ERRUNDERWRITE;
+        }
+        if (raw_int_stat & INTMSK_FRUN) {
+            error_status = ERROVERREAD;
+        }
+        if (raw_int_stat & INTMSK_HLE) {
+            error_status = ERRHLE;
+        }
+        if (raw_int_stat & INTMSK_SBE) {
+            error_status = ERRSTARTBIT;
+        }
+        if (raw_int_stat & INTMSK_EBE) {
+            error_status = ERRENDBITERR;
+        }
+    }
 
 //SDIO_PRINTF("------- %s, line %d raw_int_stat = %08x-------\n", __FUNCTION__, __LINE__, raw_int_stat);
-	return error_status;
+    return error_status;
 }
 
 static int synopmob_check_r1_resp(unsigned int the_response)
 {
-	int retval = 0;
-	
-	if (the_response & R1CS_ERROR_OCCURED_MAP) {
-		if (the_response & R1CS_ADDRESS_OUT_OF_RANGE) {
-			retval = ERRADDRESSRANGE;
-		} else if (the_response & R1CS_ADDRESS_MISALIGN) {
-			retval = ERRADDRESSMISALIGN;
-		} else if (the_response & R1CS_BLOCK_LEN_ERR) {
-			retval = ERRBLOCKLEN;
-		} else if (the_response & R1CS_ERASE_SEQ_ERR) {
-			retval = ERRERASESEQERR;
-		} else if (the_response & R1CS_ERASE_PARAM) {
-			retval = ERRERASEPARAM;
-		} else if (the_response & R1CS_WP_VIOLATION) {
-			retval = ERRPROT;
-		} else if (the_response & R1CS_CARD_IS_LOCKED) {
-			retval = ERRCARDLOCKED;
-		} else if (the_response & R1CS_LCK_UNLCK_FAILED) {
-			retval = ERRCARDLOCKED;
-		} else if (the_response & R1CS_COM_CRC_ERROR) {
-			retval = ERRCRC;
-		} else if (the_response & R1CS_ILLEGAL_COMMAND) {
-			retval = ERRILLEGALCOMMAND;
-		} else if (the_response & R1CS_CARD_ECC_FAILED) {
-			retval = ERRECCFAILED;
-		} else if (the_response & R1CS_CC_ERROR) {
-			retval = ERRCCERR;
-		} else if (the_response & R1CS_ERROR) {
-			retval = ERRUNKNOWN;
-		} else if (the_response & R1CS_UNDERRUN) {
-			retval = ERRUNDERRUN;
-		} else if (the_response & R1CS_OVERRUN) {
-			retval = ERROVERRUN;
-		} else if (the_response & R1CS_CSD_OVERWRITE) {
-			retval = ERRCSDOVERWRITE;
-		} else if (the_response & R1CS_WP_ERASE_SKIP) {
-			retval = ERRPROT;
-		} else if (the_response & R1CS_ERASE_RESET) {
-			retval = ERRERASERESET;
-		} else if (the_response & R1CS_SWITCH_ERROR) {
-			retval = ERRFSMSTATE;
-		}
-	}
-	
-	return retval;
+    int retval = 0;
+
+    if (the_response & R1CS_ERROR_OCCURED_MAP) {
+        if (the_response & R1CS_ADDRESS_OUT_OF_RANGE) {
+            retval = ERRADDRESSRANGE;
+        } else if (the_response & R1CS_ADDRESS_MISALIGN) {
+            retval = ERRADDRESSMISALIGN;
+        } else if (the_response & R1CS_BLOCK_LEN_ERR) {
+            retval = ERRBLOCKLEN;
+        } else if (the_response & R1CS_ERASE_SEQ_ERR) {
+            retval = ERRERASESEQERR;
+        } else if (the_response & R1CS_ERASE_PARAM) {
+            retval = ERRERASEPARAM;
+        } else if (the_response & R1CS_WP_VIOLATION) {
+            retval = ERRPROT;
+        } else if (the_response & R1CS_CARD_IS_LOCKED) {
+            retval = ERRCARDLOCKED;
+        } else if (the_response & R1CS_LCK_UNLCK_FAILED) {
+            retval = ERRCARDLOCKED;
+        } else if (the_response & R1CS_COM_CRC_ERROR) {
+            retval = ERRCRC;
+        } else if (the_response & R1CS_ILLEGAL_COMMAND) {
+            retval = ERRILLEGALCOMMAND;
+        } else if (the_response & R1CS_CARD_ECC_FAILED) {
+            retval = ERRECCFAILED;
+        } else if (the_response & R1CS_CC_ERROR) {
+            retval = ERRCCERR;
+        } else if (the_response & R1CS_ERROR) {
+            retval = ERRUNKNOWN;
+        } else if (the_response & R1CS_UNDERRUN) {
+            retval = ERRUNDERRUN;
+        } else if (the_response & R1CS_OVERRUN) {
+            retval = ERROVERRUN;
+        } else if (the_response & R1CS_CSD_OVERWRITE) {
+            retval = ERRCSDOVERWRITE;
+        } else if (the_response & R1CS_WP_ERASE_SKIP) {
+            retval = ERRPROT;
+        } else if (the_response & R1CS_ERASE_RESET) {
+            retval = ERRERASERESET;
+        } else if (the_response & R1CS_SWITCH_ERROR) {
+            retval = ERRFSMSTATE;
+        }
+    }
+
+    return retval;
 }
 
 
 static int synopmob_check_r5_resp(unsigned int the_resp)
 {
-	int ret = 0;
-	
-	if (the_resp & R5_IO_ERR_BITS) {
-		if (the_resp & R5_IO_CRC_ERR) {
-			ret = ERRDCRC;
-		} else if (the_resp & R5_IO_BAD_CMD) {
-			ret = ERRILLEGALCOMMAND;
-		} else if (the_resp & R5_IO_GEN_ERR) {
-			ret = ERRUNKNOWN;
-		} else if (the_resp & R5_IO_FUNC_ERR) {
-			ret = ERRBADFUNC;
-		} else if (the_resp & R5_IO_OUT_RANGE) {
-			ret = ERRADDRESSRANGE;
-		}
-	}
-	
-	return ret;
+    int ret = 0;
+
+    if (the_resp & R5_IO_ERR_BITS) {
+        if (the_resp & R5_IO_CRC_ERR) {
+            ret = ERRDCRC;
+        } else if (the_resp & R5_IO_BAD_CMD) {
+            ret = ERRILLEGALCOMMAND;
+        } else if (the_resp & R5_IO_GEN_ERR) {
+            ret = ERRUNKNOWN;
+        } else if (the_resp & R5_IO_FUNC_ERR) {
+            ret = ERRBADFUNC;
+        } else if (the_resp & R5_IO_OUT_RANGE) {
+            ret = ERRADDRESSRANGE;
+        }
+    }
+
+    return ret;
 }
 
 static int sd_send_cmd0(sdc_t* sdc)
 {
-	int   ret;
-	unsigned int intst;
-	unsigned int base = sdc->ip_base;
+    int   ret;
+    unsigned int intst;
+    unsigned int base = sdc->ip_base;
 
-	ret = synopmob_execute_command(base, 0x4000, 0);
-	if (!ret) {
-		ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE);
-		if (!ret) {
-			synopmob_set_register(base+RINTSTS, intst);
-			return synopmob_handle_standard_rinsts(intst);
-		}
-	}
+    ret = synopmob_execute_command(base, 0x4000, 0);
+    if (!ret) {
+        ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE);
+        if (!ret) {
+            synopmob_set_register(base+RINTSTS, intst);
+            return synopmob_handle_standard_rinsts(intst);
+        }
+    }
 
-	return ret;
+    return ret;
 }
 
 static int sd_send_cmd2(sdc_t* sdc)
 {
-	int   ret;
-	unsigned int intst;
-	unsigned int base = sdc->ip_base;
+    int   ret;
+    unsigned int intst;
+    unsigned int base = sdc->ip_base;
 
-	ret = synopmob_execute_command(base, 0xC2, 0);
-	if (!ret) {
-		ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE);
-		if (!ret) {
-			synopmob_set_register(base+RINTSTS, intst);
-			return synopmob_handle_standard_rinsts(intst);
-		}
-	}
+    ret = synopmob_execute_command(base, 0xC2, 0);
+    if (!ret) {
+        ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE);
+        if (!ret) {
+            synopmob_set_register(base+RINTSTS, intst);
+            return synopmob_handle_standard_rinsts(intst);
+        }
+    }
 
-	return ret;
+    return ret;
 }
 
 static int sd_send_cmd3(sdc_t* sdc)
 {
-	int   ret;
-	unsigned int intst;
-	unsigned int resp;
-	unsigned int base = sdc->ip_base;
+    int   ret;
+    unsigned int intst;
+    unsigned int resp;
+    unsigned int base = sdc->ip_base;
 
-	ret = synopmob_execute_command(base, 0x43, 0);
-	if (!ret) {
-		ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE);
-		if (!ret) {
-			synopmob_set_register(base+RINTSTS, intst);
-			ret = synopmob_handle_standard_rinsts(intst);
-			if (!ret) {
-				resp = synopmob_read_register(base+RESP0);
-				sdc->rca = resp >> 16;
-				resp = (resp & 0x1fff) | (((resp>>13)&1)<<19) | (((resp>>14)&3)<<22);
-				return synopmob_check_r1_resp(resp);
-			}
-		}		
-	}
+    ret = synopmob_execute_command(base, 0x43, 0);
+    if (!ret) {
+        ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE);
+        if (!ret) {
+            synopmob_set_register(base+RINTSTS, intst);
+            ret = synopmob_handle_standard_rinsts(intst);
+            if (!ret) {
+                resp = synopmob_read_register(base+RESP0);
+                sdc->rca = resp >> 16;
+                resp = (resp & 0x1fff) | (((resp>>13)&1)<<19) | (((resp>>14)&3)<<22);
+                return synopmob_check_r1_resp(resp);
+            }
+        }
+    }
 
-	return ret;
+    return ret;
 }
 
 static int sd_send_cmd_r1(sdc_t* sdc, unsigned int cmd, unsigned int arg, unsigned int buzy)
 {
-	int   ret;
-	unsigned int intst;
-	unsigned int resp;
-	unsigned int base = sdc->ip_base;
-	
-	ret = synopmob_execute_command(base, cmd,  arg);
-	if (!ret) {
-		ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE);
-		if (!ret) {
-			synopmob_set_register(base+RINTSTS, intst);
-			ret = synopmob_handle_standard_rinsts(intst);
-			if (!ret) {
-				resp = synopmob_read_register(base+RESP0);
-				ret = synopmob_check_r1_resp(resp);
-				if (buzy && !ret) {
-					ret = synopmob_wait_data_ready(base);
-				}
-			}
-		}
-	}
+    int   ret;
+    unsigned int intst;
+    unsigned int resp;
+    unsigned int base = sdc->ip_base;
 
-	return ret;
+    ret = synopmob_execute_command(base, cmd,  arg);
+    if (!ret) {
+        ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE);
+        if (!ret) {
+            synopmob_set_register(base+RINTSTS, intst);
+            ret = synopmob_handle_standard_rinsts(intst);
+            if (!ret) {
+                resp = synopmob_read_register(base+RESP0);
+                ret = synopmob_check_r1_resp(resp);
+                if (buzy && !ret) {
+                    ret = synopmob_wait_data_ready(base);
+                }
+            }
+        }
+    }
+
+    return ret;
 }
 
 static int sd_send_cmd7(sdc_t* sdc)
 {
-	return sd_send_cmd_r1(sdc, 0x47, sdc->rca<<16, 1);
+    return sd_send_cmd_r1(sdc, 0x47, sdc->rca<<16, 1);
 }
 
 static int sd_send_uncmd7(sdc_t* sdc)
 {
-	int   ret;
-	unsigned int intst;
-	unsigned int base = sdc->ip_base;
+    int   ret;
+    unsigned int intst;
+    unsigned int base = sdc->ip_base;
 
-	ret = synopmob_execute_command(base, 0x7, 0);
-	if (!ret) {
-		ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE);
-		if (!ret) {
-			synopmob_set_register(base+RINTSTS, intst);
-			ret = synopmob_handle_standard_rinsts(intst);
-		}
-	}
+    ret = synopmob_execute_command(base, 0x7, 0);
+    if (!ret) {
+        ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE);
+        if (!ret) {
+            synopmob_set_register(base+RINTSTS, intst);
+            ret = synopmob_handle_standard_rinsts(intst);
+        }
+    }
 
-	return ret;
+    return ret;
 }
 
 static int sd_send_cmd16(sdc_t* sdc)
 {
-	return sd_send_cmd_r1(sdc, 0x50, 512, 0);
+    return sd_send_cmd_r1(sdc, 0x50, 512, 0);
 }
 
 static int sd_send_cmd55(sdc_t* sdc)
 {
-	return sd_send_cmd_r1(sdc, 0x77, sdc->rca<<16, 0);
+    return sd_send_cmd_r1(sdc, 0x77, sdc->rca<<16, 0);
 }
 
 static int sd_send_acmd6(sdc_t* sdc, unsigned int bitwidth)
 {
-	unsigned int cmd_arg;
-	int   ret;
-	unsigned int base = sdc->ip_base;
+    unsigned int cmd_arg;
+    int   ret;
+    unsigned int base = sdc->ip_base;
 
-	ret = sd_send_cmd55(sdc);
-	if (!ret) {	
-		cmd_arg = 0; //default to 1bit mode
-		if (bitwidth == 4) {
-			cmd_arg = 2; // 4bit mode
-		}
-		ret = sd_send_cmd_r1(sdc, 0x2046, cmd_arg, 0);
-		if (!ret) {
-			if (bitwidth == 4) {
-				synopmob_set_register(base+CTYPE, FOUR_BIT_MODE);
-			}
-			else {
-				synopmob_set_register(base+CTYPE, ONE_BIT_MODE);
-			}
-		}
-	}
+    ret = sd_send_cmd55(sdc);
+    if (!ret) {
+        cmd_arg = 0; //default to 1bit mode
+        if (bitwidth == 4) {
+            cmd_arg = 2; // 4bit mode
+        }
+        ret = sd_send_cmd_r1(sdc, 0x2046, cmd_arg, 0);
+        if (!ret) {
+            if (bitwidth == 4) {
+                synopmob_set_register(base+CTYPE, FOUR_BIT_MODE);
+            }
+            else {
+                synopmob_set_register(base+CTYPE, ONE_BIT_MODE);
+            }
+        }
+    }
 
-	return ret;
+    return ret;
 }
 
 #ifdef SDC_USE_IDMA
 static int sdc_read_write_block(HSDC handle, unsigned int rw, unsigned int blk, unsigned int num, unsigned char* buffer)
 {
-	sdc_t* sdc = (sdc_t*)handle;
-	volatile DmaDesc *pDmaDesc = sdc->pDmaDesc;
-	int   ret;
-	unsigned int intsts = 0;
-	unsigned int cmd;
-	unsigned int multi = 0;
-	unsigned int base = sdc->ip_base;
-	int   loop_for_command_done_check = DATA_TRANSFER_OVER_TIMEOUT_USEC;
-	rt_err_t err;	
+    sdc_t* sdc = (sdc_t*)handle;
+    volatile DmaDesc *pDmaDesc = sdc->pDmaDesc;
+    int   ret;
+    unsigned int intsts = 0;
+    unsigned int cmd;
+    unsigned int multi = 0;
+    unsigned int base = sdc->ip_base;
+    int   loop_for_command_done_check = DATA_TRANSFER_OVER_TIMEOUT_USEC;
+    rt_err_t err;
 
-	// valid check
-	if (synopmob_read_register(base+CDETECT) & 1) {
-		return ERRCARDNOTCONN;
-	}
-	if (!num || num > 16) {
-		return ERRNOTSUPPORTED;
-	}
-	if (blk + num > sdc->sectors) {
-		return ERRADDRESSRANGE;
-	}
-
-	if ( rw ) {
-		flush_dcache_range((unsigned long)buffer, num << 9);
-	}
-	else {
-	    // to avoid memset bug?
-		inv_dcache_range((unsigned long)buffer, num << 9);
+    // valid check
+    if (synopmob_read_register(base+CDETECT) & 1) {
+        return ERRCARDNOTCONN;
+    }
+    if (!num || num > 16) {
+        return ERRNOTSUPPORTED;
+    }
+    if (blk + num > sdc->sectors) {
+        return ERRADDRESSRANGE;
     }
 
-	err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER);
-	if (err != RT_EOK) {
-		return ERRNORES;
-	}
+    if ( rw ) {
+        flush_dcache_range((unsigned long)buffer, num << 9);
+    }
+    else {
+        // to avoid memset bug?
+        inv_dcache_range((unsigned long)buffer, num << 9);
+    }
 
-	// reset
-	synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO
-	while (synopmob_read_register(base+CTRL) & FIFO_RESET);
-	synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts
+    err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER);
+    if (err != RT_EOK) {
+        return ERRNORES;
+    }
 
-	cmd = 0x2658; // write
-	if ( !rw ) {
-		cmd = 0x2251; //read
-	}
-	//if (num > 1) {
-	if (num >= 1) { // some card fail on sigle-block mode, so use multi-block instead of sigle-block mode.
-		cmd++;
-		multi++;
-	}
-	if (sdc->card_type == SD_TYPE) {
-		blk <<= 9; //SD stadand capability card use 512 unit.
-	}
-	num <<= 9;
-	
-	pDmaDesc->desc0 |= DescOwnByDma | DescFirstDesc | DescLastDesc;
-	pDmaDesc->desc1 = ((num << DescBuf1SizeShift) & DescBuf1SizMsk);
-	pDmaDesc->desc2 = (unsigned int)buffer;
-	flush_dcache_range((unsigned long)pDmaDesc, sizeof(DmaDesc)); // add SZ_ADJUST
-	synopmob_set_register(base + DBADDR, (unsigned int)(pDmaDesc)); // add SZ_ADJUST
-	synopmob_set_register(base+BLKSIZ, 512);
-	synopmob_set_register(base+BYTCNT, num);
-	synopmob_set_bits(base + CTRL, CTRL_USE_IDMAC);
-	synopmob_set_bits(base + BMOD,BMOD_DE);
-	
-	ret = synopmob_execute_command(base, cmd,  blk);
-	if ( !ret ) {
-		ret = ERRIDMA;
-		synopmob_set_bits(base+CTRL, INT_ENABLE);
-		err = rt_sem_take(sdc->sem, DMA_TRANSFER_TIMEOUT_TICKS);
-		if ( !err ) {
-			while (--loop_for_command_done_check > 0) {
-				intsts = synopmob_read_register(base+RINTSTS);
-				if ((intsts & (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) == (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) {
-					break;
-				}
-				plat_loop(1);
-			}
-			ret = synopmob_handle_standard_rinsts(intsts);
-			if (!ret ) {
-				if( !loop_for_command_done_check || !(sdc->idsts & 0x100)) { //normal interrupt
-					ret = ERRIDMA;
-				}
-			}
-		}
-	}
+    // reset
+    synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO
+    while (synopmob_read_register(base+CTRL) & FIFO_RESET);
+    synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts
 
-	if (ret) {
-	   	char* op = "read";
-	   	if (rw) 
-	   		op = "write";
-	   		
-	        SDIO_PRINTF("sdc_read_write_block(%s) fail:, ret = %d\n", op, ret);
-	}
+    cmd = 0x2658; // write
+    if ( !rw ) {
+        cmd = 0x2251; //read
+    }
+    //if (num > 1) {
+    if (num >= 1) { // some card fail on sigle-block mode, so use multi-block instead of sigle-block mode.
+        cmd++;
+        multi++;
+    }
+    if (sdc->card_type == SD_TYPE) {
+        blk <<= 9; //SD stadand capability card use 512 unit.
+    }
+    num <<= 9;
 
-	synopmob_clear_bits(base+CTRL, INT_ENABLE);
-	synopmob_clear_bits(base + CTRL, CTRL_USE_IDMAC);
-	synopmob_clear_bits(base + BMOD,BMOD_DE);
+    pDmaDesc->desc0 |= DescOwnByDma | DescFirstDesc | DescLastDesc;
+    pDmaDesc->desc1 = ((num << DescBuf1SizeShift) & DescBuf1SizMsk);
+    pDmaDesc->desc2 = (unsigned int)buffer;
+    flush_dcache_range((unsigned long)pDmaDesc, sizeof(DmaDesc)); // add SZ_ADJUST
+    synopmob_set_register(base + DBADDR, (unsigned int)(pDmaDesc)); // add SZ_ADJUST
+    synopmob_set_register(base+BLKSIZ, 512);
+    synopmob_set_register(base+BYTCNT, num);
+    synopmob_set_bits(base + CTRL, CTRL_USE_IDMAC);
+    synopmob_set_bits(base + BMOD,BMOD_DE);
 
-	synopmob_set_register(base+BLKSIZ, 512);
-	synopmob_set_register(base+BYTCNT, 512);
+    ret = synopmob_execute_command(base, cmd,  blk);
+    if ( !ret ) {
+        ret = ERRIDMA;
+        synopmob_set_bits(base+CTRL, INT_ENABLE);
+        err = rt_sem_take(sdc->sem, DMA_TRANSFER_TIMEOUT_TICKS);
+        if ( !err ) {
+            while (--loop_for_command_done_check > 0) {
+                intsts = synopmob_read_register(base+RINTSTS);
+                if ((intsts & (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) == (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) {
+                    break;
+                }
+                plat_loop(1);
+            }
+            ret = synopmob_handle_standard_rinsts(intsts);
+            if (!ret ) {
+                if( !loop_for_command_done_check || !(sdc->idsts & 0x100)) { //normal interrupt
+                    ret = ERRIDMA;
+                }
+            }
+        }
+    }
 
-	synopmob_set_register(base + RINTSTS, 0xfffe);
+    if (ret) {
+        char* op = "read";
+        if (rw)
+            op = "write";
 
-	if ( !ret && rw) {
-		ret = synopmob_wait_data_ready(base);
-	}
+            SDIO_PRINTF("sdc_read_write_block(%s) fail:, ret = %d\n", op, ret);
+    }
 
-	if (!ret && multi ) { //send STOP_TRANSACTION command
-		ret = sd_send_cmd_r1(sdc, 0x404c, 0, 1);
-	}
+    synopmob_clear_bits(base+CTRL, INT_ENABLE);
+    synopmob_clear_bits(base + CTRL, CTRL_USE_IDMAC);
+    synopmob_clear_bits(base + BMOD,BMOD_DE);
 
-	rt_sem_release(sdc->mutex);
-	
-	if ( !rw && !ret ) { //read
-		inv_dcache_range((unsigned long)buffer, num);
-	}
-	
-	return ret;
+    synopmob_set_register(base+BLKSIZ, 512);
+    synopmob_set_register(base+BYTCNT, 512);
+
+    synopmob_set_register(base + RINTSTS, 0xfffe);
+
+    if ( !ret && rw) {
+        ret = synopmob_wait_data_ready(base);
+    }
+
+    if (!ret && multi ) { //send STOP_TRANSACTION command
+        ret = sd_send_cmd_r1(sdc, 0x404c, 0, 1);
+    }
+
+    rt_sem_release(sdc->mutex);
+
+    if ( !rw && !ret ) { //read
+        inv_dcache_range((unsigned long)buffer, num);
+    }
+
+    return ret;
 }
 #else  //no IDMA
 static int sdc_read_write_block(HSDC handle, unsigned int rw, unsigned int blk, unsigned int num, unsigned char* buffer)
 {
-	sdc_t* sdc = (sdc_t*)handle;
-	volatile DmaDesc *pDmaDesc = sdc->pDmaDesc;
-	int   ret;
-	unsigned int intsts = 0;
-	unsigned int entries;
-	unsigned int cmd;
-	unsigned int multi = 0;
-	unsigned int base = sdc->ip_base;
-	int   loop_for_command_done_check = DATA_TRANSFER_OVER_TIMEOUT_USEC;
-	rt_err_t err;	
+    sdc_t* sdc = (sdc_t*)handle;
+    volatile DmaDesc *pDmaDesc = sdc->pDmaDesc;
+    int   ret;
+    unsigned int intsts = 0;
+    unsigned int entries;
+    unsigned int cmd;
+    unsigned int multi = 0;
+    unsigned int base = sdc->ip_base;
+    int   loop_for_command_done_check = DATA_TRANSFER_OVER_TIMEOUT_USEC;
+    rt_err_t err;
 
-	// valid check
-	if (synopmob_read_register(base+CDETECT) & 1) {
-		return ERRCARDNOTCONN;
-	}
-	if (!num || num > 16) {
-		return ERRNOTSUPPORTED;
-	}
-	if (blk + num > sdc->sectors) {
-		return ERRADDRESSRANGE;
-	}
-
-	if ( rw ) {
-		flush_dcache_range((unsigned long)buffer, num << 9);
-	}
-	else {
-	    // to avoid memset bug?
-		inv_dcache_range((unsigned long)buffer, num << 9);
+    // valid check
+    if (synopmob_read_register(base+CDETECT) & 1) {
+        return ERRCARDNOTCONN;
+    }
+    if (!num || num > 16) {
+        return ERRNOTSUPPORTED;
+    }
+    if (blk + num > sdc->sectors) {
+        return ERRADDRESSRANGE;
     }
 
-	err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER);
-	if (err != RT_EOK) {
-		return ERRNORES;
-	}
+    if ( rw ) {
+        flush_dcache_range((unsigned long)buffer, num << 9);
+    }
+    else {
+        // to avoid memset bug?
+        inv_dcache_range((unsigned long)buffer, num << 9);
+    }
 
-	// reset
-	synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO
-	while (synopmob_read_register(base+CTRL) & FIFO_RESET);
-	synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts
+    err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER);
+    if (err != RT_EOK) {
+        return ERRNORES;
+    }
 
-	cmd = 0x2658; // write
-	if ( !rw ) {
-		cmd = 0x2251; //read
-	}
-	if (num > 1) {
-		cmd++;
-		multi++;
-	}
-	if (sdc->card_type == SD_TYPE) {
-		blk <<= 9; //SD stadand capability card use 512 unit.
-	}
-	num <<= 9;
-	
-	synopmob_set_register(base+BLKSIZ, 512);
-	synopmob_set_register(base+BYTCNT, num);
-	
-	ret = synopmob_execute_command(base, cmd,  blk);
-	if ( !ret ) {
-		while (1) {
-			ret = synopmob_wait_command_done(base, &intsts, 0);
-			if (ret)
-				break;
+    // reset
+    synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO
+    while (synopmob_read_register(base+CTRL) & FIFO_RESET);
+    synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts
 
-			ret = synopmob_handle_standard_rinsts(intsts);
-			if (ret)
-				break;
+    cmd = 0x2658; // write
+    if ( !rw ) {
+        cmd = 0x2251; //read
+    }
+    if (num > 1) {
+        cmd++;
+        multi++;
+    }
+    if (sdc->card_type == SD_TYPE) {
+        blk <<= 9; //SD stadand capability card use 512 unit.
+    }
+    num <<= 9;
 
-			if (!rw && (intsts & (INTMSK_RXDR|INTMSK_DAT_OVER)) ){
-				while (num > 0 ) {
-					entries = synopmob_read_register(base + STATUS);
-					if (!GET_FIFO_COUNT(entries))
-						break;
-					*((volatile unsigned int*)buffer) = synopmob_read_register(base + FIFODAT);
-					buffer += 4;
-					num -= 4;
-				}
-			}
-			
-			if (rw && ( intsts & INTMSK_TXDR ) ) {
-				while (num > 0) {
-					entries = synopmob_read_register(base+STATUS);
-					if ( entries & 8 ) { //FIFO is full
-						break;
-					}
-					synopmob_set_register(base+FIFODAT, *((volatile unsigned int*)buffer));
-					buffer += 4;
-					num -= 4;
-				}
-			}
-			
-			if ( intsts & INTMSK_DAT_OVER ) {
-				break;
-			}
+    synopmob_set_register(base+BLKSIZ, 512);
+    synopmob_set_register(base+BYTCNT, num);
 
-			if (intsts & INTMSK_CMD_DONE) {
-				entries = synopmob_read_register(base+RESP0);
-				ret = synopmob_check_r1_resp(entries);
-				if (ret) {
-					break;
-				}
-			}
+    ret = synopmob_execute_command(base, cmd,  blk);
+    if ( !ret ) {
+        while (1) {
+            ret = synopmob_wait_command_done(base, &intsts, 0);
+            if (ret)
+                break;
 
-			synopmob_set_register(base+RINTSTS, intsts); //write to clear
-			intsts = 0;
-		}		
-		
-		if (intsts) {
-			synopmob_set_register(base+RINTSTS, intsts); //write to clear
-		}
-	}
+            ret = synopmob_handle_standard_rinsts(intsts);
+            if (ret)
+                break;
 
-	synopmob_set_register(base+BLKSIZ, 512);
-	synopmob_set_register(base+BYTCNT, 512);
-	synopmob_set_register(base + RINTSTS, 0xfffe);
+            if (!rw && (intsts & (INTMSK_RXDR|INTMSK_DAT_OVER)) ){
+                while (num > 0 ) {
+                    entries = synopmob_read_register(base + STATUS);
+                    if (!GET_FIFO_COUNT(entries))
+                        break;
+                    *((volatile unsigned int*)buffer) = synopmob_read_register(base + FIFODAT);
+                    buffer += 4;
+                    num -= 4;
+                }
+            }
 
-	if ( !ret && rw) {
-		ret = synopmob_wait_data_ready(base);
-	}
+            if (rw && ( intsts & INTMSK_TXDR ) ) {
+                while (num > 0) {
+                    entries = synopmob_read_register(base+STATUS);
+                    if ( entries & 8 ) { //FIFO is full
+                        break;
+                    }
+                    synopmob_set_register(base+FIFODAT, *((volatile unsigned int*)buffer));
+                    buffer += 4;
+                    num -= 4;
+                }
+            }
 
-	if (!ret && multi ) { //send STOP_TRANSACTION command
-		ret = sd_send_cmd_r1(sdc, 0x404c, 0, 1);
-	}
+            if ( intsts & INTMSK_DAT_OVER ) {
+                break;
+            }
 
-	rt_sem_release(sdc->mutex);
-	
-	if ( !rw && !ret ) { //read
-		inv_dcache_range((unsigned long)buffer, num);
-	}
-	
-	return ret;
+            if (intsts & INTMSK_CMD_DONE) {
+                entries = synopmob_read_register(base+RESP0);
+                ret = synopmob_check_r1_resp(entries);
+                if (ret) {
+                    break;
+                }
+            }
+
+            synopmob_set_register(base+RINTSTS, intsts); //write to clear
+            intsts = 0;
+        }
+
+        if (intsts) {
+            synopmob_set_register(base+RINTSTS, intsts); //write to clear
+        }
+    }
+
+    synopmob_set_register(base+BLKSIZ, 512);
+    synopmob_set_register(base+BYTCNT, 512);
+    synopmob_set_register(base + RINTSTS, 0xfffe);
+
+    if ( !ret && rw) {
+        ret = synopmob_wait_data_ready(base);
+    }
+
+    if (!ret && multi ) { //send STOP_TRANSACTION command
+        ret = sd_send_cmd_r1(sdc, 0x404c, 0, 1);
+    }
+
+    rt_sem_release(sdc->mutex);
+
+    if ( !rw && !ret ) { //read
+        inv_dcache_range((unsigned long)buffer, num);
+    }
+
+    return ret;
 }
 #endif //SDC_USE_IDMA
 
 int sdc_write_block(HSDC handle, unsigned int blk, unsigned int num, unsigned char* buffer)
 {
-	return sdc_read_write_block(handle, 1, blk, num, buffer);
+    return sdc_read_write_block(handle, 1, blk, num, buffer);
 }
 
 int sdc_read_block(HSDC handle, unsigned int blk, unsigned int num, unsigned char* buffer)
 {
-	return sdc_read_write_block(handle, 0, blk, num, buffer);
+    return sdc_read_write_block(handle, 0, blk, num, buffer);
 }
 
 int sdc_erase_block(HSDC handle, unsigned int blk, unsigned int num)
 {
-	int   ret;
-	sdc_t* sdc = (sdc_t*)handle;
-	
-	if (sdc->card_type == SD_TYPE) {
-		blk <<= 9; //SD stadand capability card use 512 unit.
-		num = ((num-1)<<9) + blk;
-	}
-	else {
-		num = blk + num - 1;
-	}
-	
-	ret = sd_send_cmd_r1(sdc, 0x40|32, blk, 0); // cmd32
-	if (!ret) {
-		ret = sd_send_cmd_r1(sdc, 0x40|33, num, 0); // cmd33
-		if (!ret) {
-			ret = sd_send_cmd_r1(sdc, 0x40|38, 0, 1); // cmd38
-		}
-	}
+    int   ret;
+    sdc_t* sdc = (sdc_t*)handle;
 
-	return ret;
+    if (sdc->card_type == SD_TYPE) {
+        blk <<= 9; //SD stadand capability card use 512 unit.
+        num = ((num-1)<<9) + blk;
+    }
+    else {
+        num = blk + num - 1;
+    }
+
+    ret = sd_send_cmd_r1(sdc, 0x40|32, blk, 0); // cmd32
+    if (!ret) {
+        ret = sd_send_cmd_r1(sdc, 0x40|33, num, 0); // cmd33
+        if (!ret) {
+            ret = sd_send_cmd_r1(sdc, 0x40|38, 0, 1); // cmd38
+        }
+    }
+
+    return ret;
 }
 
 int sdc_get_sector_num(HSDC handle)
 {
-	return ((sdc_t*)handle)->sectors;
+    return ((sdc_t*)handle)->sectors;
 }
 
 static int sd_send_cmd9(sdc_t* sdc)
 {
-	int   ret;
-	unsigned int intst;
-	unsigned int resp0;
-	unsigned int resp1;
-	unsigned int resp2;
-	unsigned int resp3;
-	unsigned int base = sdc->ip_base;
-	unsigned int C_SIZE;
-	unsigned int C_SIZE_MULT;
-	unsigned int READ_BL_LEN;
+    int   ret;
+    unsigned int intst;
+    unsigned int resp0;
+    unsigned int resp1;
+    unsigned int resp2;
+    unsigned int resp3;
+    unsigned int base = sdc->ip_base;
+    unsigned int C_SIZE;
+    unsigned int C_SIZE_MULT;
+    unsigned int READ_BL_LEN;
 
-	ret = synopmob_execute_command(base, 0xC9, sdc->rca<<16);
-	if (!ret) {
-		ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE);
-		if (!ret) {
-			synopmob_set_register(base+RINTSTS, intst);
-			ret = synopmob_handle_standard_rinsts(intst);
-			if (!ret) {
-				sdc->csd[0] = resp0 = synopmob_read_register(base+RESP0);
-				sdc->csd[1] = resp1 = synopmob_read_register(base+RESP1);
-				sdc->csd[2] = resp2 = synopmob_read_register(base+RESP2);
-				sdc->csd[3] = resp3 = synopmob_read_register(base+RESP3);
-				
-				if ((resp3>>30) == 0) { //CSD version 1.0
-					C_SIZE = (resp1 >> 30) | ((resp2 & 0x3ff)<<2);
-					C_SIZE_MULT = ((resp1 >> 15) & 0x07);				
-					READ_BL_LEN = ((resp2 >> 16) & 0xf);
-					sdc->sectors = ((((C_SIZE+1)<<(C_SIZE_MULT+2))<<(READ_BL_LEN))>>9);
-				}
-				else { //CSD version 2.0
-					sdc->sectors = (((resp1 >> 16)+1)<<10);
-				}
-			}
-		}		
-	}
+    ret = synopmob_execute_command(base, 0xC9, sdc->rca<<16);
+    if (!ret) {
+        ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE);
+        if (!ret) {
+            synopmob_set_register(base+RINTSTS, intst);
+            ret = synopmob_handle_standard_rinsts(intst);
+            if (!ret) {
+                sdc->csd[0] = resp0 = synopmob_read_register(base+RESP0);
+                sdc->csd[1] = resp1 = synopmob_read_register(base+RESP1);
+                sdc->csd[2] = resp2 = synopmob_read_register(base+RESP2);
+                sdc->csd[3] = resp3 = synopmob_read_register(base+RESP3);
 
-	return ret;
+                if ((resp3>>30) == 0) { //CSD version 1.0
+                    C_SIZE = (resp1 >> 30) | ((resp2 & 0x3ff)<<2);
+                    C_SIZE_MULT = ((resp1 >> 15) & 0x07);
+                    READ_BL_LEN = ((resp2 >> 16) & 0xf);
+                    sdc->sectors = ((((C_SIZE+1)<<(C_SIZE_MULT+2))<<(READ_BL_LEN))>>9);
+                }
+                else { //CSD version 2.0
+                    sdc->sectors = (((resp1 >> 16)+1)<<10);
+                }
+            }
+        }
+    }
+
+    return ret;
 }
 
 static int sd_send_cmd5(sdc_t* sdc, unsigned int arg, unsigned int* resp)
 {
-	unsigned int cmd_reg = 0x45;
-	unsigned int intst;
-	int   ret;
-	unsigned int base = sdc->ip_base;
+    unsigned int cmd_reg = 0x45;
+    unsigned int intst;
+    int   ret;
+    unsigned int base = sdc->ip_base;
 
-	ret = synopmob_execute_command(base, cmd_reg, arg);
-	if (!ret) {
-		ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE);
-		if (!ret) {
-			synopmob_set_register(base+RINTSTS, intst);
-			ret = synopmob_handle_standard_rinsts(intst);
-			if (!ret) {
-				*resp = synopmob_read_register(base+RESP0);
-			}
-		}
-	}
-	
-	return ret;	
+    ret = synopmob_execute_command(base, cmd_reg, arg);
+    if (!ret) {
+        ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE);
+        if (!ret) {
+            synopmob_set_register(base+RINTSTS, intst);
+            ret = synopmob_handle_standard_rinsts(intst);
+            if (!ret) {
+                *resp = synopmob_read_register(base+RESP0);
+            }
+        }
+    }
+
+    return ret;
 }
 
 static int sd_send_cmd8(sdc_t* sdc)
 {
-	int   ret;
-	unsigned int cmd_reg = 0x48;
-	unsigned int intst;
-	unsigned int err = 0;
-	unsigned int base = sdc->ip_base;
-	
-	ret = synopmob_execute_command(base, cmd_reg, 0x000001A5);
-	if (!ret) {
-		while (1) {
-			ret = synopmob_wait_command_done(base, &intst, 0);
-			if (!ret) {
-				synopmob_set_register(base+RINTSTS, intst);
-				err |= synopmob_handle_standard_rinsts(intst);
-				if (intst & INTMSK_CMD_DONE) {
-					break;
-				}
-			}
-		}
-	}
+    int   ret;
+    unsigned int cmd_reg = 0x48;
+    unsigned int intst;
+    unsigned int err = 0;
+    unsigned int base = sdc->ip_base;
 
-	return err;
+    ret = synopmob_execute_command(base, cmd_reg, 0x000001A5);
+    if (!ret) {
+        while (1) {
+            ret = synopmob_wait_command_done(base, &intst, 0);
+            if (!ret) {
+                synopmob_set_register(base+RINTSTS, intst);
+                err |= synopmob_handle_standard_rinsts(intst);
+                if (intst & INTMSK_CMD_DONE) {
+                    break;
+                }
+            }
+        }
+    }
+
+    return err;
 }
 
 static int sd_send_acmd41(sdc_t* sdc, int* hcs)
 {
-	unsigned int cmd_reg = 0x69;
-	unsigned int resp;
-	int   ret = 0;
-	unsigned int count = ACMD41_RETRY_COUNT;
-	unsigned int cmd_arg = 0xff8000;
-	unsigned int base = sdc->ip_base;
+    unsigned int cmd_reg = 0x69;
+    unsigned int resp;
+    int   ret = 0;
+    unsigned int count = ACMD41_RETRY_COUNT;
+    unsigned int cmd_arg = 0xff8000;
+    unsigned int base = sdc->ip_base;
 
-	if (*hcs) {
-		cmd_arg |= (1<<30);
-	}
-	while ( count > 0) {
-		SDC_WHERE();
-		ret = sd_send_cmd55(sdc);
-		if (ret)
-			break;
+    if (*hcs) {
+        cmd_arg |= (1<<30);
+    }
+    while ( count > 0) {
+        SDC_WHERE();
+        ret = sd_send_cmd55(sdc);
+        if (ret)
+            break;
 
-		SDC_WHERE();
-		ret = synopmob_execute_command(base, cmd_reg, cmd_arg);
-		if (ret)
-			break;
+        SDC_WHERE();
+        ret = synopmob_execute_command(base, cmd_reg, cmd_arg);
+        if (ret)
+            break;
 
-		SDC_WHERE();
-		ret = synopmob_wait_command_done(base, &resp, INTMSK_CMD_DONE);
-		if ( ret ) 
-			break;
+        SDC_WHERE();
+        ret = synopmob_wait_command_done(base, &resp, INTMSK_CMD_DONE);
+        if ( ret )
+            break;
 
-		SDC_WHERE();
-		synopmob_set_register(base+RINTSTS, resp);
-		ret = synopmob_handle_standard_rinsts(resp);
-		if (!ret) {
-			SDC_WHERE();
-			resp = synopmob_read_register(base+RESP0);
-			if (resp & 0x80000000) { //card is ready.
-				SDC_WHERE();
-				if ( !(resp & (1<<30)) ) {
-					SDC_WHERE();
-					*hcs = 0;
-				}
-				if ( (resp & 0x00ff8000) != 0x00ff8000 ) { //not supported voltage
-					ret = ERRHARDWARE;
-				}
-				break;
-			}
-		}
+        SDC_WHERE();
+        synopmob_set_register(base+RINTSTS, resp);
+        ret = synopmob_handle_standard_rinsts(resp);
+        if (!ret) {
+            SDC_WHERE();
+            resp = synopmob_read_register(base+RESP0);
+            if (resp & 0x80000000) { //card is ready.
+                SDC_WHERE();
+                if ( !(resp & (1<<30)) ) {
+                    SDC_WHERE();
+                    *hcs = 0;
+                }
+                if ( (resp & 0x00ff8000) != 0x00ff8000 ) { //not supported voltage
+                    ret = ERRHARDWARE;
+                }
+                break;
+            }
+        }
 
-		--count;
-		plat_loop(1);
-	}
+        --count;
+        plat_loop(1);
+    }
 
-	if (!count)
-		ret = ERRACMD41TIMEOUT;
-	
-	return ret;
+    if (!count)
+        ret = ERRACMD41TIMEOUT;
+
+    return ret;
 }
 
 static int sd_send_acmd51(sdc_t* sdc) //Send SCR
 {
-	unsigned int cmd_reg = 0x2273;
-	unsigned int resp;
-	int   ret;
-	unsigned int intst = 0;
-	unsigned int entries;
-	int   count = 1;
-	unsigned int base = sdc->ip_base;
+    unsigned int cmd_reg = 0x2273;
+    unsigned int resp;
+    int   ret;
+    unsigned int intst = 0;
+    unsigned int entries;
+    int   count = 1;
+    unsigned int base = sdc->ip_base;
 
-	ret = sd_send_cmd55(sdc);
-	if (!ret) {	
-		synopmob_set_register(base+BLKSIZ, 8);
-		synopmob_set_register(base+BYTCNT, 8);
-		ret = synopmob_execute_command(base, cmd_reg, 0);
-		if (!ret) {
-			while (1) {
-				ret = synopmob_wait_command_done(base, &intst, 0);
-				if (ret) {
-					break;
-				}
+    ret = sd_send_cmd55(sdc);
+    if (!ret) {
+        synopmob_set_register(base+BLKSIZ, 8);
+        synopmob_set_register(base+BYTCNT, 8);
+        ret = synopmob_execute_command(base, cmd_reg, 0);
+        if (!ret) {
+            while (1) {
+                ret = synopmob_wait_command_done(base, &intst, 0);
+                if (ret) {
+                    break;
+                }
 
-				ret = synopmob_handle_standard_rinsts(intst);
-				if (ret) {
-					break;
-				}
-				
-				if (intst & INTMSK_CMD_DONE) {
-					resp = synopmob_read_register(base+RESP0);
-					ret = synopmob_check_r1_resp(resp);
-					if (ret) 
-						break;
-				}
+                ret = synopmob_handle_standard_rinsts(intst);
+                if (ret) {
+                    break;
+                }
 
-				if (intst & INTMSK_DAT_OVER) {
-					entries = synopmob_read_register(base + STATUS);
-					if (GET_FIFO_COUNT(entries) == 2) {
-						while (count >= 0) {
-							entries = synopmob_read_register(base + FIFODAT);
-							sdc->scr[count--] = BE32_TO_CPU(entries);
-						}
-					}
-					break;
-				}
+                if (intst & INTMSK_CMD_DONE) {
+                    resp = synopmob_read_register(base+RESP0);
+                    ret = synopmob_check_r1_resp(resp);
+                    if (ret)
+                        break;
+                }
 
-				synopmob_set_register(base+RINTSTS, intst);
-				intst = 0;
-			}
+                if (intst & INTMSK_DAT_OVER) {
+                    entries = synopmob_read_register(base + STATUS);
+                    if (GET_FIFO_COUNT(entries) == 2) {
+                        while (count >= 0) {
+                            entries = synopmob_read_register(base + FIFODAT);
+                            sdc->scr[count--] = BE32_TO_CPU(entries);
+                        }
+                    }
+                    break;
+                }
 
-			if (intst) {
-				synopmob_set_register(base+RINTSTS, intst);
-			}
-		}
+                synopmob_set_register(base+RINTSTS, intst);
+                intst = 0;
+            }
 
-		synopmob_set_register(base+BLKSIZ, 512);
-		synopmob_set_register(base+BYTCNT, 512);
-	}
+            if (intst) {
+                synopmob_set_register(base+RINTSTS, intst);
+            }
+        }
 
-	return ret;
+        synopmob_set_register(base+BLKSIZ, 512);
+        synopmob_set_register(base+BYTCNT, 512);
+    }
+
+    return ret;
 }
 
 
-static int sd_send_cmd6(sdc_t* sdc, unsigned int cmd_arg, unsigned int* data_buff) 
+static int sd_send_cmd6(sdc_t* sdc, unsigned int cmd_arg, unsigned int* data_buff)
 {
-	unsigned int cmd_reg = 0x2246;
-	unsigned int resp;
-	int   ret;
-	unsigned int intst = 0;
-	unsigned int entries;
-	int   count = 64;
-	unsigned int base = sdc->ip_base;
+    unsigned int cmd_reg = 0x2246;
+    unsigned int resp;
+    int   ret;
+    unsigned int intst = 0;
+    unsigned int entries;
+    int   count = 64;
+    unsigned int base = sdc->ip_base;
 
-	synopmob_set_register(base+BLKSIZ, 64);
-	synopmob_set_register(base+BYTCNT, 64);
-	ret = synopmob_execute_command(base, cmd_reg, cmd_arg);
-	if (!ret) {
-		while (1) {
-			ret = synopmob_wait_command_done(base, &intst, 0);
-			if (ret) {
-				break;
-			}
+    synopmob_set_register(base+BLKSIZ, 64);
+    synopmob_set_register(base+BYTCNT, 64);
+    ret = synopmob_execute_command(base, cmd_reg, cmd_arg);
+    if (!ret) {
+        while (1) {
+            ret = synopmob_wait_command_done(base, &intst, 0);
+            if (ret) {
+                break;
+            }
 
-			ret = synopmob_handle_standard_rinsts(intst);
-			if (ret) {
-				break;
-			}
-				
-			if (intst & INTMSK_CMD_DONE) {
-				resp = synopmob_read_register(base+RESP0);
-				ret = synopmob_check_r1_resp(resp);
-				if (ret) 
-					break;
-			}
+            ret = synopmob_handle_standard_rinsts(intst);
+            if (ret) {
+                break;
+            }
 
-			while (count > 0) {
-				entries = synopmob_read_register(base + STATUS);
-				if ( !GET_FIFO_COUNT(entries) ) {
-					break;
-				}
-				*(data_buff++) = synopmob_read_register(base + FIFODAT);
-				count -= 4;
-			}
+            if (intst & INTMSK_CMD_DONE) {
+                resp = synopmob_read_register(base+RESP0);
+                ret = synopmob_check_r1_resp(resp);
+                if (ret)
+                    break;
+            }
 
-			if (intst & INTMSK_DAT_OVER) {
-				break;
-			}
+            while (count > 0) {
+                entries = synopmob_read_register(base + STATUS);
+                if ( !GET_FIFO_COUNT(entries) ) {
+                    break;
+                }
+                *(data_buff++) = synopmob_read_register(base + FIFODAT);
+                count -= 4;
+            }
 
-			synopmob_set_register(base+RINTSTS, intst); //write to clear
-			intst = 0;
-		}
+            if (intst & INTMSK_DAT_OVER) {
+                break;
+            }
 
-		if (intst) {
-			synopmob_set_register(base+RINTSTS, intst); //write to clear
-		}
-	}
+            synopmob_set_register(base+RINTSTS, intst); //write to clear
+            intst = 0;
+        }
 
-	synopmob_set_register(base+BLKSIZ, 512);
-	synopmob_set_register(base+BYTCNT, 512);
+        if (intst) {
+            synopmob_set_register(base+RINTSTS, intst); //write to clear
+        }
+    }
 
-	return ret;
+    synopmob_set_register(base+BLKSIZ, 512);
+    synopmob_set_register(base+BYTCNT, 512);
+
+    return ret;
 }
 
 static int synopmob_send_clock_only_cmd(unsigned int base)
 {
-	return synopmob_execute_command(base, 0x202000, 0);
+    return synopmob_execute_command(base, 0x202000, 0);
 }
 
 
 static int synopmob_disable_all_clocks(unsigned int base)
 {
-	synopmob_set_register(base+CLKENA, 0);
-	return synopmob_send_clock_only_cmd(base);
+    synopmob_set_register(base+CLKENA, 0);
+    return synopmob_send_clock_only_cmd(base);
 }
 
 static int synopmob_enable_clocks_with_val(unsigned int base, unsigned int val)
 {
-	synopmob_set_register(base+CLKENA, val);
-	return synopmob_send_clock_only_cmd(base);
+    synopmob_set_register(base+CLKENA, val);
+    return synopmob_send_clock_only_cmd(base);
 }
 
 
 static int synopmob_set_clk_freq(sdc_t* sdc, unsigned int divider)
 {
-	#define MAX_DIVIDER_VALUE      0xff
-	
-	unsigned int orig_clkena;
-	int  retval;
-	unsigned int base = sdc->ip_base;
+    #define MAX_DIVIDER_VALUE      0xff
 
-	if (divider > MAX_DIVIDER_VALUE) {
-		return 0xffffffff;
-	}
+    unsigned int orig_clkena;
+    int  retval;
+    unsigned int base = sdc->ip_base;
 
-	/* To make sure we dont disturb enable/disable settings of the cards*/
-	orig_clkena = synopmob_read_register(base+CLKENA);
+    if (divider > MAX_DIVIDER_VALUE) {
+        return 0xffffffff;
+    }
 
-	/* Disable all clocks before changing frequency the of card clocks */
-	if ((retval = synopmob_disable_all_clocks(base)) != 0) {
-		return retval;
-	}
-	/* Program the clock divider in our case it is divider 0 */
-	synopmob_clear_bits(base+CLKDIV, MAX_DIVIDER_VALUE);
-	synopmob_set_bits(base+CLKDIV, divider);
-	
-	/*Send the command to CIU using synopmob_send_clock_only_cmd and enable the clocks in CLKENA register */
-	if ((retval = synopmob_send_clock_only_cmd(base)) != 0) {
-		synopmob_enable_clocks_with_val(base, orig_clkena);
-		return retval;
-	}
+    /* To make sure we dont disturb enable/disable settings of the cards*/
+    orig_clkena = synopmob_read_register(base+CLKENA);
 
-	return synopmob_enable_clocks_with_val(base, orig_clkena);
+    /* Disable all clocks before changing frequency the of card clocks */
+    if ((retval = synopmob_disable_all_clocks(base)) != 0) {
+        return retval;
+    }
+    /* Program the clock divider in our case it is divider 0 */
+    synopmob_clear_bits(base+CLKDIV, MAX_DIVIDER_VALUE);
+    synopmob_set_bits(base+CLKDIV, divider);
+
+    /*Send the command to CIU using synopmob_send_clock_only_cmd and enable the clocks in CLKENA register */
+    if ((retval = synopmob_send_clock_only_cmd(base)) != 0) {
+        synopmob_enable_clocks_with_val(base, orig_clkena);
+        return retval;
+    }
+
+    return synopmob_enable_clocks_with_val(base, orig_clkena);
 }
 
 static int enum_sd_card(sdc_t* sdc)
 {
-	int ret;
-	int count = 1000;
-	int hcs = 0;
-	unsigned int buffer[16];
-	unsigned int base = sdc->ip_base;
+    int ret;
+    int count = 1000;
+    int hcs = 0;
+    unsigned int buffer[16];
+    unsigned int base = sdc->ip_base;
 
-	if (synopmob_read_register(base+CDETECT) & 1) {
-		return ERRCARDNOTCONN;
-	}
-	
-	#if 0
-	synopmob_set_bits(0x98500004, (1<<24)); //set to output mode
-	synopmob_set_bits(0x98500000, (1<<24)); //power off
-	plat_loop(1000000/5); //Lets give some ramp down period
-	synopmob_clear_bits(0x98500000, (1<<24)); //power on
-	plat_loop(1000000/5);//Lets give some ramp down period
-	#endif
-	
-	synopmob_set_register(base+CTYPE, ONE_BIT_MODE);
+    if (synopmob_read_register(base+CDETECT) & 1) {
+        return ERRCARDNOTCONN;
+    }
 
-	synopmob_set_register(base+CLKENA, 0x00000001); /*enable clock, non-low-power mode*/
-	ret = synopmob_set_clk_freq(sdc, MMC_FOD_DIVIDER_VALUE);
-	
-	if ( !ret ) {
-		plat_loop(1000); //enough for 74 clock.	
-		SDC_WHERE();
-		ret = sd_send_cmd0(sdc); //CMD0 has no response
-	}
-	
-	if ( !ret ) {
-		SDC_WHERE();
-		ret = sd_send_cmd8(sdc); //even if CMD8 get response, it may be V1.0 card.
-		if (!ret) {
-			hcs = 1;
-		}
-		SDC_WHERE();
-		ret = sd_send_acmd41(sdc, &hcs);
-	}
+    #if 0
+    synopmob_set_bits(0x98500004, (1<<24)); //set to output mode
+    synopmob_set_bits(0x98500000, (1<<24)); //power off
+    plat_loop(1000000/5); //Lets give some ramp down period
+    synopmob_clear_bits(0x98500000, (1<<24)); //power on
+    plat_loop(1000000/5);//Lets give some ramp down period
+    #endif
 
-	if (!ret) {
-		SDC_WHERE();
-		ret = sd_send_cmd2(sdc); //CID
-	}
+    synopmob_set_register(base+CTYPE, ONE_BIT_MODE);
 
-	if (!ret) {
-		SDC_WHERE();
-		ret = sd_send_cmd3(sdc); //get RCA
-	}
+    synopmob_set_register(base+CLKENA, 0x00000001); /*enable clock, non-low-power mode*/
+    ret = synopmob_set_clk_freq(sdc, MMC_FOD_DIVIDER_VALUE);
 
-	if (!ret) {
-		SDC_WHERE();
-		ret = sd_send_cmd9(sdc); //CSD
-	}
+    if ( !ret ) {
+        plat_loop(1000); //enough for 74 clock.
+        SDC_WHERE();
+        ret = sd_send_cmd0(sdc); //CMD0 has no response
+    }
 
-	if (!ret) {
-		SDC_WHERE();
-		ret = sd_send_cmd7(sdc); //select the card
-	}
+    if ( !ret ) {
+        SDC_WHERE();
+        ret = sd_send_cmd8(sdc); //even if CMD8 get response, it may be V1.0 card.
+        if (!ret) {
+            hcs = 1;
+        }
+        SDC_WHERE();
+        ret = sd_send_acmd41(sdc, &hcs);
+    }
 
-	if (!ret && (sdc->wkmod & SDC_WKMOD_4WIRE) ) {
-		SDC_WHERE();
-		ret = sd_send_acmd51(sdc); //SCR
-		if (!ret && (sdc->scr[1] & 0x00040000)) { // 4bit mode supported?
-			ret = sd_send_acmd6(sdc, 4); //switch to 4bit mode
-		}
-	}
-	
-	if (!ret && (sdc->wkmod & SDC_WKMOD_50M_HI_SPEED) && (sdc->csd[2] & 0x40000000) ) { //judge whether class10 is supported? CMD6 is belonging to class10.
-		SDC_WHERE();
-		ret = sd_send_cmd6(sdc, 0x00fffff1, buffer); //switch to high speed mode.
-		if ( !ret &&  (*(((unsigned char*)buffer)+13)&0x02) ) { //the card support high speed mode?
-			SDC_WHERE();
-			ret = sd_send_cmd6(sdc, 0x80fffff1, buffer); //switch to high speed mode.
-			if (!ret && ((*(((unsigned char*)buffer)+16) & 0xf) == 1) ) {
-				//switch to high speed mode sucess.
-				sd_send_uncmd7(sdc); //deselect the card
-				sd_send_cmd9(sdc); //CSD
-				ret = sd_send_cmd7(sdc); //select the card
-			}
-		}
-	}
-	
-	if (!ret && (sdc->wkmod & (SDC_WKMOD_50M_HI_SPEED|SDC_WKMOD_25M_STAND_SPEED))) {
-		if ( (sdc->csd[3] & 0xff) == 0x5A ) { //50MHz high speed mode.			
-			SDC_WHERE();
-			ret = synopmob_set_clk_freq(sdc, (((CIU_CLK)/(50000*2))));
-		}
-		else if ( (sdc->csd[3] & 0xff) == 0x32 ) {
-			SDC_WHERE(); //25MHz standard speed mode.
-			ret = synopmob_set_clk_freq(sdc, sdc_clk_divider/*ONE_BIT_BUS_FREQ*/);
-		}
-	}
+    if (!ret) {
+        SDC_WHERE();
+        ret = sd_send_cmd2(sdc); //CID
+    }
 
-	if (!ret) {
-		sdc->card_type = SD_TYPE;
-		if (hcs) {
-			sdc->card_type = SD_2_0_TYPE;
-		}
-	}
+    if (!ret) {
+        SDC_WHERE();
+        ret = sd_send_cmd3(sdc); //get RCA
+    }
 
-	return ret;
+    if (!ret) {
+        SDC_WHERE();
+        ret = sd_send_cmd9(sdc); //CSD
+    }
+
+    if (!ret) {
+        SDC_WHERE();
+        ret = sd_send_cmd7(sdc); //select the card
+    }
+
+    if (!ret && (sdc->wkmod & SDC_WKMOD_4WIRE) ) {
+        SDC_WHERE();
+        ret = sd_send_acmd51(sdc); //SCR
+        if (!ret && (sdc->scr[1] & 0x00040000)) { // 4bit mode supported?
+            ret = sd_send_acmd6(sdc, 4); //switch to 4bit mode
+        }
+    }
+
+    if (!ret && (sdc->wkmod & SDC_WKMOD_50M_HI_SPEED) && (sdc->csd[2] & 0x40000000) ) { //judge whether class10 is supported? CMD6 is belonging to class10.
+        SDC_WHERE();
+        ret = sd_send_cmd6(sdc, 0x00fffff1, buffer); //switch to high speed mode.
+        if ( !ret &&  (*(((unsigned char*)buffer)+13)&0x02) ) { //the card support high speed mode?
+            SDC_WHERE();
+            ret = sd_send_cmd6(sdc, 0x80fffff1, buffer); //switch to high speed mode.
+            if (!ret && ((*(((unsigned char*)buffer)+16) & 0xf) == 1) ) {
+                //switch to high speed mode sucess.
+                sd_send_uncmd7(sdc); //deselect the card
+                sd_send_cmd9(sdc); //CSD
+                ret = sd_send_cmd7(sdc); //select the card
+            }
+        }
+    }
+
+    if (!ret && (sdc->wkmod & (SDC_WKMOD_50M_HI_SPEED|SDC_WKMOD_25M_STAND_SPEED))) {
+        if ( (sdc->csd[3] & 0xff) == 0x5A ) { //50MHz high speed mode.
+            SDC_WHERE();
+            ret = synopmob_set_clk_freq(sdc, (((CIU_CLK)/(50000*2))));
+        }
+        else if ( (sdc->csd[3] & 0xff) == 0x32 ) {
+            SDC_WHERE(); //25MHz standard speed mode.
+            ret = synopmob_set_clk_freq(sdc, sdc_clk_divider/*ONE_BIT_BUS_FREQ*/);
+        }
+    }
+
+    if (!ret) {
+        sdc->card_type = SD_TYPE;
+        if (hcs) {
+            sdc->card_type = SD_2_0_TYPE;
+        }
+    }
+
+    return ret;
 }
 
 int sdio_drv_creg_read(HSDC handle, int addr, int fn, unsigned int *resp)
 {
-	sdc_t* sdc = (sdc_t*)handle;
-	unsigned int arg;
-	unsigned int cmd_reg = 0x74;
-	unsigned int intst;
-	int   ret;
-	unsigned int base = sdc->ip_base;
-	rt_err_t err;
+    sdc_t* sdc = (sdc_t*)handle;
+    unsigned int arg;
+    unsigned int cmd_reg = 0x74;
+    unsigned int intst;
+    int   ret;
+    unsigned int base = sdc->ip_base;
+    rt_err_t err;
 
     if(resp) {
         *resp = 0;
     }
-    
-	err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER);
-	if (err != RT_EOK) {
-		return ERRNORES;
-	}
 
-	arg = (fn << 28) | (addr << 9);
-	ret = synopmob_execute_command(base, cmd_reg, arg);
-	if (!ret) {
-		ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE);
-		if (!ret) {
-			synopmob_set_register(base+RINTSTS, intst); //write to clear
-			ret = synopmob_handle_standard_rinsts(intst);
-			if (!ret) {
-				*resp = synopmob_read_register(base+RESP0);
-				ret = synopmob_check_r5_resp(*resp);
-			}
-		}
-	}
+    err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER);
+    if (err != RT_EOK) {
+        return ERRNORES;
+    }
 
-	rt_sem_release(sdc->mutex);
-	
-	if (ret) {
-		ret++;
-		ret--;
-		SDIO_PRINTF("sdio_drv_creg_read fail:, ret = %d\n", ret);
-	}
-	
-	return ret;
+    arg = (fn << 28) | (addr << 9);
+    ret = synopmob_execute_command(base, cmd_reg, arg);
+    if (!ret) {
+        ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE);
+        if (!ret) {
+            synopmob_set_register(base+RINTSTS, intst); //write to clear
+            ret = synopmob_handle_standard_rinsts(intst);
+            if (!ret) {
+                *resp = synopmob_read_register(base+RESP0);
+                ret = synopmob_check_r5_resp(*resp);
+            }
+        }
+    }
+
+    rt_sem_release(sdc->mutex);
+
+    if (ret) {
+        ret++;
+        ret--;
+        SDIO_PRINTF("sdio_drv_creg_read fail:, ret = %d\n", ret);
+    }
+
+    return ret;
 }
 
 int sdio_drv_creg_write(HSDC handle, int addr, int fn, unsigned char data, unsigned int *resp)
 {
-	sdc_t* sdc = (sdc_t*)handle;
-	unsigned int arg;
-	unsigned int cmd_reg = 0x74;
-	unsigned int intst;
-	int   ret;
-	unsigned int base = sdc->ip_base;
-	rt_err_t err;
+    sdc_t* sdc = (sdc_t*)handle;
+    unsigned int arg;
+    unsigned int cmd_reg = 0x74;
+    unsigned int intst;
+    int   ret;
+    unsigned int base = sdc->ip_base;
+    rt_err_t err;
 
-	err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER);
-	if (err != RT_EOK) {
-		return ERRNORES;
-	}
-	
-	arg = (1 << 31) | (fn << 28) | (1 << 27) | (addr << 9) | data;
-	ret = synopmob_execute_command(base, cmd_reg, arg);
-	if (!ret) {
-		ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE);
-		if (!ret) {
-			synopmob_set_register(base+RINTSTS, intst); //write to clear
-			ret = synopmob_handle_standard_rinsts(intst);
-			if (!ret) {
-				*resp = synopmob_read_register(base+RESP0);
-				ret = synopmob_check_r5_resp(*resp);
-			}
-		}
-	}
+    err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER);
+    if (err != RT_EOK) {
+        return ERRNORES;
+    }
 
-	rt_sem_release(sdc->mutex);
-	if (ret) {
-		ret++;
-		ret--;
-		SDIO_PRINTF("sdio_drv_creg_write fail:, ret = %d\n", ret);
-	}
-	
-	return ret;
+    arg = (1 << 31) | (fn << 28) | (1 << 27) | (addr << 9) | data;
+    ret = synopmob_execute_command(base, cmd_reg, arg);
+    if (!ret) {
+        ret = synopmob_wait_command_done(base, &intst, INTMSK_CMD_DONE);
+        if (!ret) {
+            synopmob_set_register(base+RINTSTS, intst); //write to clear
+            ret = synopmob_handle_standard_rinsts(intst);
+            if (!ret) {
+                *resp = synopmob_read_register(base+RESP0);
+                ret = synopmob_check_r5_resp(*resp);
+            }
+        }
+    }
+
+    rt_sem_release(sdc->mutex);
+    if (ret) {
+        ret++;
+        ret--;
+        SDIO_PRINTF("sdio_drv_creg_write fail:, ret = %d\n", ret);
+    }
+
+    return ret;
 }
 
 #define ARC_REG_DC_IVDL 0x4A
@@ -1184,153 +1184,153 @@ extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size);
 extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size);
 void inv_dcache_range(unsigned long start, unsigned long len)
 {
-	mmu_invalidate_dcache(start, len);
+    mmu_invalidate_dcache(start, len);
 }
 
 void flush_dcache_range(unsigned long start, unsigned long len)
 {
-	mmu_clean_dcache(start, len);
+    mmu_clean_dcache(start, len);
 }
 
 int g_use_bcm43362 = 0;
 static int sdio_drv_read_write(sdc_t* sdc, unsigned int rw, unsigned int addr, unsigned int fn, unsigned int bcnt,
-								   unsigned int bsize, unsigned char *buf)
+                                   unsigned int bsize, unsigned char *buf)
 {
-	volatile DmaDesc *pDmaDesc = sdc->pDmaDesc;
-	int   ret;	
-	unsigned int intsts = 0;
-	unsigned int cmd = 0x2275;
-	unsigned int base = sdc->ip_base;
-	unsigned int arg;
-	unsigned int num;
-	int   loop_for_command_done_check = 10000;//DATA_TRANSFER_OVER_TIMEOUT_USEC;	
-	rt_err_t err;	
+    volatile DmaDesc *pDmaDesc = sdc->pDmaDesc;
+    int   ret;
+    unsigned int intsts = 0;
+    unsigned int cmd = 0x2275;
+    unsigned int base = sdc->ip_base;
+    unsigned int arg;
+    unsigned int num;
+    int   loop_for_command_done_check = 10000;//DATA_TRANSFER_OVER_TIMEOUT_USEC;
+    rt_err_t err;
 
 //SDIO_PRINTF("------- %s, line %d buf = %08x size = %d -------\n", __FUNCTION__, __LINE__, buf, bsize);
-	arg = (fn << 28) | (addr << 9);
+    arg = (fn << 28) | (addr << 9);
 
-	if (g_use_bcm43362) {
-		arg |= (1 << 26); //OPcode = 1............, for AP6181.
-	}
-
-	if (bcnt == 1 && bsize <= 512)
-		arg |= (bsize & 0x1ff);
-	else
-		arg |= ((1 << 27) | bcnt);	
-	if ( rw ) {
-		cmd |= 0x400;
-		arg |= (1 << 31);
-	}
-	num = bsize*bcnt;
-
-	if ( rw ) {
-		flush_dcache_range((unsigned long)buf, num);
-	}
-	else {
-		inv_dcache_range((unsigned long)buf, num);
+    if (g_use_bcm43362) {
+        arg |= (1 << 26); //OPcode = 1............, for AP6181.
     }
 
-	err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER);
-	if (err != RT_EOK) {
-	return ERRNORES;
-	}
+    if (bcnt == 1 && bsize <= 512)
+        arg |= (bsize & 0x1ff);
+    else
+        arg |= ((1 << 27) | bcnt);
+    if ( rw ) {
+        cmd |= 0x400;
+        arg |= (1 << 31);
+    }
+    num = bsize*bcnt;
+
+    if ( rw ) {
+        flush_dcache_range((unsigned long)buf, num);
+    }
+    else {
+        inv_dcache_range((unsigned long)buf, num);
+    }
+
+    err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER);
+    if (err != RT_EOK) {
+    return ERRNORES;
+    }
 
 //synopmob_set_bits(base+FIFOTH, 0x2 << 28);
-	// reset
-	synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO
-	while (synopmob_read_register(base+CTRL) & FIFO_RESET);
-	synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts
+    // reset
+    synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO
+    while (synopmob_read_register(base+CTRL) & FIFO_RESET);
+    synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts
 
-	//pDmaDesc->desc0 = 0;
-	pDmaDesc->desc0 |= DescOwnByDma | DescFirstDesc | DescLastDesc;
-	pDmaDesc->desc1 = ((num << DescBuf1SizeShift) & DescBuf1SizMsk);
-	pDmaDesc->desc2 = (unsigned int)buf;
-	//pDmaDesc->desc3 = 0;
-	flush_dcache_range((unsigned int)pDmaDesc, sizeof(DmaDesc));
-	synopmob_set_register(base+DBADDR, (unsigned int)pDmaDesc);
-	synopmob_set_register(base+BLKSIZ, bsize);
-	synopmob_set_register(base+BYTCNT, num);
-	synopmob_set_bits(base + CTRL, CTRL_USE_IDMAC);
-	synopmob_set_bits(base + BMOD,BMOD_DE);
+    //pDmaDesc->desc0 = 0;
+    pDmaDesc->desc0 |= DescOwnByDma | DescFirstDesc | DescLastDesc;
+    pDmaDesc->desc1 = ((num << DescBuf1SizeShift) & DescBuf1SizMsk);
+    pDmaDesc->desc2 = (unsigned int)buf;
+    //pDmaDesc->desc3 = 0;
+    flush_dcache_range((unsigned int)pDmaDesc, sizeof(DmaDesc));
+    synopmob_set_register(base+DBADDR, (unsigned int)pDmaDesc);
+    synopmob_set_register(base+BLKSIZ, bsize);
+    synopmob_set_register(base+BYTCNT, num);
+    synopmob_set_bits(base + CTRL, CTRL_USE_IDMAC);
+    synopmob_set_bits(base + BMOD,BMOD_DE);
 
 //SDIO_PRINTF("pDmaDesc = %08x, %08x / %08x / %08x / %08x\n", pDmaDesc, pDmaDesc->desc0, pDmaDesc->desc1, pDmaDesc->desc2, pDmaDesc->desc3);
-	ret = synopmob_execute_command(base, cmd,  arg);
-	if ( !ret ) {
-		ret = ERRIDMA;
-		err = rt_sem_take(sdc->sem, DMA_TRANSFER_TIMEOUT_TICKS);
-		if ( !err ) {
-			while (--loop_for_command_done_check > 0) {
-				intsts = synopmob_read_register(base+RINTSTS);
-				if ((intsts & (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) == (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) {
-					break;
-				}
-				plat_loop(1);
-			}
-			ret = synopmob_handle_standard_rinsts(intsts);
-			if (!ret ) {
-				if( !loop_for_command_done_check || !(sdc->idsts & 0x100)) { //normal interrupt
+    ret = synopmob_execute_command(base, cmd,  arg);
+    if ( !ret ) {
+        ret = ERRIDMA;
+        err = rt_sem_take(sdc->sem, DMA_TRANSFER_TIMEOUT_TICKS);
+        if ( !err ) {
+            while (--loop_for_command_done_check > 0) {
+                intsts = synopmob_read_register(base+RINTSTS);
+                if ((intsts & (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) == (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) {
+                    break;
+                }
+                plat_loop(1);
+            }
+            ret = synopmob_handle_standard_rinsts(intsts);
+            if (!ret ) {
+                if( !loop_for_command_done_check || !(sdc->idsts & 0x100)) { //normal interrupt
 SDIO_PRINTF("------- %s, line %d idsts = %08x check = %d -------\n", __FUNCTION__, __LINE__, sdc->idsts, loop_for_command_done_check);
-					ret = ERRIDMA;
-				}
-			}
-			else
+                    ret = ERRIDMA;
+                }
+            }
+            else
                 SDIO_PRINTF("------- %s, line %d intsts = %08x buf = %08x -------\n", __FUNCTION__, __LINE__, intsts, buf);
-		}
-	}
+        }
+    }
+
+    if (!ret) {
+        synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts
+        synopmob_clear_bits(base + CTRL, CTRL_USE_IDMAC);
+        synopmob_clear_bits(base + BMOD,BMOD_DE);
+        synopmob_set_register(base+BLKSIZ, 512);
+        synopmob_set_register(base+BYTCNT, 512);
+    }
+    else {
+        char* op = "read";
+        if (rw)
+            op = "write";
 
-	if (!ret) {
-		synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts
-		synopmob_clear_bits(base + CTRL, CTRL_USE_IDMAC);
-		synopmob_clear_bits(base + BMOD,BMOD_DE);
-		synopmob_set_register(base+BLKSIZ, 512);
-		synopmob_set_register(base+BYTCNT, 512);
-	}
-	else {
-   		char* op = "read";
-   		if (rw) 
-   			op = "write";
-   		
         SDIO_PRINTF("sdio_drv_read_write1(%s) fail:, ret = %d\n", op, ret);
-	}
-		
-	if ( rw && !ret ) { //write
-		ret = synopmob_wait_data_ready(base);
-	}
+    }
 
-	rt_sem_release(sdc->mutex);
+    if ( rw && !ret ) { //write
+        ret = synopmob_wait_data_ready(base);
+    }
+
+    rt_sem_release(sdc->mutex);
+
+    if ( !rw && !ret ) { //read
+        inv_dcache_range((unsigned long)buf, num);
+    }
 
-	if ( !rw && !ret ) { //read
-		inv_dcache_range((unsigned long)buf, num);
-	}
-	
        if (ret) {
-       		char* op = "read";
-       		if (rw) 
-       			op = "write";
-       		
-	        SDIO_PRINTF("sdio_drv_read_write2(%s) fail:, ret = %d\n", op, ret);
+            char* op = "read";
+            if (rw)
+                op = "write";
+
+            SDIO_PRINTF("sdio_drv_read_write2(%s) fail:, ret = %d\n", op, ret);
        }
-	return ret;
-	//return ret ? 0/*false*/ : 1/*true*/;
+    return ret;
+    //return ret ? 0/*false*/ : 1/*true*/;
 }
 
 int sdio_drv_read(HSDC handle, unsigned int addr, unsigned int fn, unsigned int bcnt,
-		   unsigned int bsize, unsigned char *buf)
+           unsigned int bsize, unsigned char *buf)
 {
-	return sdio_drv_read_write((sdc_t*)handle, 0, addr, fn, bcnt, bsize, buf);
+    return sdio_drv_read_write((sdc_t*)handle, 0, addr, fn, bcnt, bsize, buf);
 }
 
 int sdio_drv_write(HSDC handle, unsigned int addr, unsigned int fn, unsigned int bcnt,
-		   unsigned int bsize, unsigned char *buf)
+           unsigned int bsize, unsigned char *buf)
 {
-	return sdio_drv_read_write((sdc_t*)handle, 1, addr, fn, bcnt, bsize, buf);
+    return sdio_drv_read_write((sdc_t*)handle, 1, addr, fn, bcnt, bsize, buf);
 }
 
 static void dumpchain(DmaDesc *pChain)
 {
     int i = 0;
     DmaDesc *tmp_pChain = pChain;
-    
+
     while(tmp_pChain && i < 10)
     {
         SDIO_PRINTF("[%d]: chain =%p, buf = %p, size = %d, csi = %08x, next = %p\n", i, tmp_pChain, (DmaDesc *)tmp_pChain->desc2, tmp_pChain->desc1, tmp_pChain->desc0, (DmaDesc *)tmp_pChain->desc3);
@@ -1346,711 +1346,711 @@ static void dumpchain(DmaDesc *pChain)
 #if 1
 int sdio_drv_chain_write(sdc_t* sdc, unsigned int addr, unsigned int fn, unsigned int bcnt, unsigned int bsize, buf_chain_t *chain)
 {
-	int   ret;	
-	unsigned int intsts = 0;
-	unsigned int cmd = 0x2275;
-	unsigned int base = sdc->ip_base;
-	unsigned int arg;
-	unsigned int num;
-	unsigned int chain_len = 0;
-	int   loop_for_command_done_check = DATA_TRANSFER_OVER_TIMEOUT_USEC;	
-	rt_err_t err;	
-	unsigned int rw = 1;
-	DmaDesc *tmpDesc = (DmaDesc *)chain;
-	DmaDesc *lastDesc = (void*)0;
+    int   ret;
+    unsigned int intsts = 0;
+    unsigned int cmd = 0x2275;
+    unsigned int base = sdc->ip_base;
+    unsigned int arg;
+    unsigned int num;
+    unsigned int chain_len = 0;
+    int   loop_for_command_done_check = DATA_TRANSFER_OVER_TIMEOUT_USEC;
+    rt_err_t err;
+    unsigned int rw = 1;
+    DmaDesc *tmpDesc = (DmaDesc *)chain;
+    DmaDesc *lastDesc = (void*)0;
 
-	arg = (fn << 28) | (addr << 9);
-	if (bcnt == 1 && bsize <= 512)
-		arg |= (bsize & 0x1ff);
-	else
-		arg |= ((1 << 27) | bcnt);	
-	if ( rw ) {
-		cmd |= 0x400;
-		arg |= (1 << 31);
-	}
-	num = bsize*bcnt;
+    arg = (fn << 28) | (addr << 9);
+    if (bcnt == 1 && bsize <= 512)
+        arg |= (bsize & 0x1ff);
+    else
+        arg |= ((1 << 27) | bcnt);
+    if ( rw ) {
+        cmd |= 0x400;
+        arg |= (1 << 31);
+    }
+    num = bsize*bcnt;
+
+    err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER);
+    if (err != RT_EOK) {
+        return ERRNORES;
+    }
+
+    // reset
+    synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO
+    while (synopmob_read_register(base+CTRL) & FIFO_RESET);
+        synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts
 
-	err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER);
-	if (err != RT_EOK) {
-		return ERRNORES;
-	}
-	
-	// reset
-	synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO
-	while (synopmob_read_register(base+CTRL) & FIFO_RESET);
-    	synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts
-	
     while(tmpDesc != 0) {
         // make sure size is little than DescBuf1SizMsk
         if(tmpDesc->desc1 > (DescBuf1SizMsk >> DescBuf1SizeShift)) {
-            // TBD... fix me 
+            // TBD... fix me
             rt_sem_release(sdc->mutex);
             return 0;
         }
         // TBD... fix me, we must align tmpDesc->desc2 to 4 ?
-        
+
         tmpDesc->desc0 = DescOwnByDma | DescSecAddrChained;
-        
+
         // is it last node?
         if(tmpDesc->desc3 == 0 || tmpDesc->desc3 == (unsigned int)chain) {
-    		tmpDesc->desc0 |= DescLastDesc;
-    		lastDesc = tmpDesc;
+            tmpDesc->desc0 |= DescLastDesc;
+            lastDesc = tmpDesc;
         }
         else {
-        	tmpDesc->desc0 |= DescDisInt; //disable interrupt...        	
+            tmpDesc->desc0 |= DescDisInt; //disable interrupt...
         }
-        
+
         // is it first node?
         if((char *)tmpDesc == (char *)chain) {
-    		tmpDesc->desc0 |= DescFirstDesc;
-        } 
+            tmpDesc->desc0 |= DescFirstDesc;
+        }
 
         flush_dcache_range(tmpDesc->desc2, tmpDesc->desc1);
-        
+
         tmpDesc = (DmaDesc *)tmpDesc->desc3;
         chain_len += sizeof(buf_chain_t);
 
         if((char *)tmpDesc == (char *)chain) {
-        	break;
+            break;
         }
     }
 
     lastDesc->desc3 = (unsigned int)chain;
 
-	//FIXME, chain must be continuous arrry.
-	flush_dcache_range((unsigned long)chain, chain_len);
+    //FIXME, chain must be continuous arrry.
+    flush_dcache_range((unsigned long)chain, chain_len);
 
-	synopmob_set_register(base+DBADDR, (unsigned int)(chain));
-    
-	synopmob_set_register(base+BLKSIZ, bsize);
-	synopmob_set_register(base+BYTCNT, num);
-	synopmob_set_bits(base + CTRL, CTRL_USE_IDMAC);
-	synopmob_set_bits(base + BMOD,BMOD_DE);
-	
-	ret = synopmob_execute_command(base, cmd,  arg);
-	if ( !ret ) {
-		ret = ERRIDMA;
-		err = rt_sem_take(sdc->sem, DMA_TRANSFER_TIMEOUT_TICKS);
-		if ( !err ) {
-			while (--loop_for_command_done_check > 0) {
-				intsts = synopmob_read_register(base+RINTSTS);
-				if ((intsts & (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) == (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) {
-					break;
-				}
-				plat_loop(1);
-			}
-			ret = synopmob_handle_standard_rinsts(intsts);
-			if (!ret ) {
-				if( !loop_for_command_done_check || !(sdc->idsts & 0x100)) { //normal interrupt
-					ret = ERRIDMA;
-				}
-			}
-		}
-	}
+    synopmob_set_register(base+DBADDR, (unsigned int)(chain));
 
-	if (!ret) {
-		synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts
-		synopmob_clear_bits(base + CTRL, CTRL_USE_IDMAC);
-		synopmob_clear_bits(base + BMOD,BMOD_DE);
-		synopmob_set_register(base+BLKSIZ, 512);
-		synopmob_set_register(base+BYTCNT, 512);
-	}
-	else {
-	   		char* op = "read";
-	   		if (rw) 
-	   			op = "write";
-	   		
-	        SDIO_PRINTF("sdio_drv_chain_write1(%s) fail:, ret = %d, bsize = %d * %d\n", op, ret, bsize, bcnt);
-	        dumpchain((DmaDesc *)chain);
-	}
+    synopmob_set_register(base+BLKSIZ, bsize);
+    synopmob_set_register(base+BYTCNT, num);
+    synopmob_set_bits(base + CTRL, CTRL_USE_IDMAC);
+    synopmob_set_bits(base + BMOD,BMOD_DE);
 
-	if ( rw && !ret ) {
-		ret = synopmob_wait_data_ready(base);
-	}
+    ret = synopmob_execute_command(base, cmd,  arg);
+    if ( !ret ) {
+        ret = ERRIDMA;
+        err = rt_sem_take(sdc->sem, DMA_TRANSFER_TIMEOUT_TICKS);
+        if ( !err ) {
+            while (--loop_for_command_done_check > 0) {
+                intsts = synopmob_read_register(base+RINTSTS);
+                if ((intsts & (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) == (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) {
+                    break;
+                }
+                plat_loop(1);
+            }
+            ret = synopmob_handle_standard_rinsts(intsts);
+            if (!ret ) {
+                if( !loop_for_command_done_check || !(sdc->idsts & 0x100)) { //normal interrupt
+                    ret = ERRIDMA;
+                }
+            }
+        }
+    }
 
-	rt_sem_release(sdc->mutex);
+    if (!ret) {
+        synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts
+        synopmob_clear_bits(base + CTRL, CTRL_USE_IDMAC);
+        synopmob_clear_bits(base + BMOD,BMOD_DE);
+        synopmob_set_register(base+BLKSIZ, 512);
+        synopmob_set_register(base+BYTCNT, 512);
+    }
+    else {
+            char* op = "read";
+            if (rw)
+                op = "write";
 
-	if (ret) {
-		ret++;
-		ret--;
-	        SDIO_PRINTF("sdio_drv_chain_write2, fail:, ret = %d\n", ret);
-	}
+            SDIO_PRINTF("sdio_drv_chain_write1(%s) fail:, ret = %d, bsize = %d * %d\n", op, ret, bsize, bcnt);
+            dumpchain((DmaDesc *)chain);
+    }
 
-	return ret;
-	//return ret ? 0/*false*/ : 1/*true*/;
+    if ( rw && !ret ) {
+        ret = synopmob_wait_data_ready(base);
+    }
+
+    rt_sem_release(sdc->mutex);
+
+    if (ret) {
+        ret++;
+        ret--;
+            SDIO_PRINTF("sdio_drv_chain_write2, fail:, ret = %d\n", ret);
+    }
+
+    return ret;
+    //return ret ? 0/*false*/ : 1/*true*/;
 }
 #elif 0
 int sdio_drv_chain_write(sdc_t* sdc, unsigned int addr, unsigned int fn, unsigned int bcnt, unsigned int bsize, buf_chain_t *chain)
 {
-	//static volatile DmaDesc __attribute__ ((aligned(32))) st_pchain[4];
-	volatile DmaDesc *st_pchain = (DmaDesc *)0x9a700000;
-		
-	int   ret;	
-	unsigned int intsts = 0;
-	unsigned int cmd = 0x2275;
-	unsigned int base = sdc->ip_base;
-	unsigned int arg;
-	unsigned int num;
-	unsigned int chain_len = 0;
-	int   loop_for_command_done_check = DATA_TRANSFER_OVER_TIMEOUT_USEC;	
-	char err;	
-	unsigned int rw = 1;
+    //static volatile DmaDesc __attribute__ ((aligned(32))) st_pchain[4];
+    volatile DmaDesc *st_pchain = (DmaDesc *)0x9a700000;
 
-	buf_chain_t *usrchain;
-	unsigned int desc0;
-	unsigned int length = 0;
+    int   ret;
+    unsigned int intsts = 0;
+    unsigned int cmd = 0x2275;
+    unsigned int base = sdc->ip_base;
+    unsigned int arg;
+    unsigned int num;
+    unsigned int chain_len = 0;
+    int   loop_for_command_done_check = DATA_TRANSFER_OVER_TIMEOUT_USEC;
+    char err;
+    unsigned int rw = 1;
 
-	if (!chain) {
-		return 0;
-	}
+    buf_chain_t *usrchain;
+    unsigned int desc0;
+    unsigned int length = 0;
 
-	arg = (fn << 28) | (addr << 9);
-	if (bcnt == 1 && bsize <= 512)
-		arg |= (bsize & 0x1ff);
-	else
-		arg |= ((1 << 27) | bcnt);	
-	if ( rw ) {
-		cmd |= 0x400;
-		arg |= (1 << 31);
-	}
-	num = bsize*bcnt;
+    if (!chain) {
+        return 0;
+    }
 
-	OSSemPend(sdc->mutex, 0, &err);
-	if (err != OS_NO_ERR) {
-		return ERRNORES;
-	}
-	
-	// reset
-	synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO
-	while (synopmob_read_register(base+CTRL) & FIFO_RESET);
-    	synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts
+    arg = (fn << 28) | (addr << 9);
+    if (bcnt == 1 && bsize <= 512)
+        arg |= (bsize & 0x1ff);
+    else
+        arg |= ((1 << 27) | bcnt);
+    if ( rw ) {
+        cmd |= 0x400;
+        arg |= (1 << 31);
+    }
+    num = bsize*bcnt;
 
-	usrchain = chain;
-    	while (1) {
-		if(usrchain->size > (DescBuf1SizMsk >> DescBuf1SizeShift)) {
-            		// TBD... fix me 
-	            OSSemPost (sdc->mutex);
-        	    return 0;
-		}
-		length += usrchain->size;
-    		desc0 = DescOwnByDma | DescSecAddrChained;
-    		if (!usrchain->next || usrchain->next == chain) {
-    			desc0 |= DescLastDesc;
-    		}
-		else {
-        		desc0 |= DescDisInt; //disable interrupt...        	
-		}        
+    OSSemPend(sdc->mutex, 0, &err);
+    if (err != OS_NO_ERR) {
+        return ERRNORES;
+    }
 
-		if(usrchain == chain) {
-			desc0 |= DescFirstDesc;
-		}
+    // reset
+    synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO
+    while (synopmob_read_register(base+CTRL) & FIFO_RESET);
+        synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts
 
-    		st_pchain[chain_len].desc0 = desc0;
-		st_pchain[chain_len].desc1 = (unsigned int)usrchain->size;
-		st_pchain[chain_len].desc2 = (unsigned int)usrchain->buf;
-		st_pchain[chain_len].desc3 = (unsigned int)(&st_pchain[chain_len+1]);
-		flush_dcache_range((unsigned int)usrchain->buf, usrchain->size);
-		
-		usrchain = usrchain->next;
-		if( !usrchain || usrchain == chain) {
-	        	break;
-		}
-		if (++chain_len >= 4) {
-			while(1) SDIO_PRINTF("sdio_drv_chain_write:long chain!\n");
-		}
-    	}
-	st_pchain[chain_len].desc3 = (unsigned int)(&st_pchain[0]);
+    usrchain = chain;
+        while (1) {
+        if(usrchain->size > (DescBuf1SizMsk >> DescBuf1SizeShift)) {
+                    // TBD... fix me
+                OSSemPost (sdc->mutex);
+                return 0;
+        }
+        length += usrchain->size;
+            desc0 = DescOwnByDma | DescSecAddrChained;
+            if (!usrchain->next || usrchain->next == chain) {
+                desc0 |= DescLastDesc;
+            }
+        else {
+                desc0 |= DescDisInt; //disable interrupt...
+        }
 
-	if (length != num) {
-		while (1) SDIO_PRINTF("sdio_drv_chain_write:too long packet!\n");
-	}
+        if(usrchain == chain) {
+            desc0 |= DescFirstDesc;
+        }
 
-	synopmob_set_register(base+DBADDR, (unsigned int)(st_pchain));
-    
-	synopmob_set_register(base+BLKSIZ, bsize);
-	synopmob_set_register(base+BYTCNT, num);
-	synopmob_set_bits(base + CTRL, CTRL_USE_IDMAC);
-	synopmob_set_bits(base + BMOD,BMOD_DE);
-	
-	ret = synopmob_execute_command(base, cmd,  arg);
-	if ( !ret ) {
-		ret = ERRIDMA;
-		OSSemPend(sdc->sem, DMA_TRANSFER_TIMEOUT_TICKS, &err);
-		if ( !err ) {
-			while (--loop_for_command_done_check > 0) {
-				intsts = synopmob_read_register(base+RINTSTS);
-				if ((intsts & (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) == (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) {
-					break;
-				}
-				plat_loop(1);
-			}
-			ret = synopmob_handle_standard_rinsts(intsts);
-			if (!ret ) {
-				if( !loop_for_command_done_check || !(sdc->idsts & 0x100)) { //normal interrupt
-					ret = ERRIDMA;
-				}
-			}
-		}
-	}
+            st_pchain[chain_len].desc0 = desc0;
+        st_pchain[chain_len].desc1 = (unsigned int)usrchain->size;
+        st_pchain[chain_len].desc2 = (unsigned int)usrchain->buf;
+        st_pchain[chain_len].desc3 = (unsigned int)(&st_pchain[chain_len+1]);
+        flush_dcache_range((unsigned int)usrchain->buf, usrchain->size);
 
-	if (!ret) {
-		synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts
-		synopmob_clear_bits(base + CTRL, CTRL_USE_IDMAC);
-		synopmob_clear_bits(base + BMOD,BMOD_DE);
-		synopmob_set_register(base+BLKSIZ, 512);
-		synopmob_set_register(base+BYTCNT, 512);
-	}
-	else {
-	   	char* op = "read";
-	   	if (rw) 
-	   		op = "write";
-	   		
-	        SDIO_PRINTF("sdio_drv_chain_write1(%s) fail:, ret = %d\n", op, ret);
-	}
+        usrchain = usrchain->next;
+        if( !usrchain || usrchain == chain) {
+                break;
+        }
+        if (++chain_len >= 4) {
+            while(1) SDIO_PRINTF("sdio_drv_chain_write:long chain!\n");
+        }
+        }
+    st_pchain[chain_len].desc3 = (unsigned int)(&st_pchain[0]);
 
-	if ( rw && !ret ) {
-		ret = synopmob_wait_data_ready(base);
-	}
+    if (length != num) {
+        while (1) SDIO_PRINTF("sdio_drv_chain_write:too long packet!\n");
+    }
 
-	OSSemPost (sdc->mutex);
+    synopmob_set_register(base+DBADDR, (unsigned int)(st_pchain));
 
-	return ret;
-	//return ret ? 0/*false*/ : 1/*true*/;
+    synopmob_set_register(base+BLKSIZ, bsize);
+    synopmob_set_register(base+BYTCNT, num);
+    synopmob_set_bits(base + CTRL, CTRL_USE_IDMAC);
+    synopmob_set_bits(base + BMOD,BMOD_DE);
+
+    ret = synopmob_execute_command(base, cmd,  arg);
+    if ( !ret ) {
+        ret = ERRIDMA;
+        OSSemPend(sdc->sem, DMA_TRANSFER_TIMEOUT_TICKS, &err);
+        if ( !err ) {
+            while (--loop_for_command_done_check > 0) {
+                intsts = synopmob_read_register(base+RINTSTS);
+                if ((intsts & (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) == (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) {
+                    break;
+                }
+                plat_loop(1);
+            }
+            ret = synopmob_handle_standard_rinsts(intsts);
+            if (!ret ) {
+                if( !loop_for_command_done_check || !(sdc->idsts & 0x100)) { //normal interrupt
+                    ret = ERRIDMA;
+                }
+            }
+        }
+    }
+
+    if (!ret) {
+        synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts
+        synopmob_clear_bits(base + CTRL, CTRL_USE_IDMAC);
+        synopmob_clear_bits(base + BMOD,BMOD_DE);
+        synopmob_set_register(base+BLKSIZ, 512);
+        synopmob_set_register(base+BYTCNT, 512);
+    }
+    else {
+        char* op = "read";
+        if (rw)
+            op = "write";
+
+            SDIO_PRINTF("sdio_drv_chain_write1(%s) fail:, ret = %d\n", op, ret);
+    }
+
+    if ( rw && !ret ) {
+        ret = synopmob_wait_data_ready(base);
+    }
+
+    OSSemPost (sdc->mutex);
+
+    return ret;
+    //return ret ? 0/*false*/ : 1/*true*/;
 }
 #else
 static unsigned char __attribute__ ((aligned(32))) st_net_buf[2*1024];
 int sdio_drv_chain_write(sdc_t* sdc, unsigned int addr, unsigned int fn, unsigned int bcnt, unsigned int bsize, buf_chain_t *chain)
 {
-	static volatile DmaDesc __attribute__ ((aligned(32))) st_pchain;
-		
-	int   ret;	
-	unsigned int intsts = 0;
-	unsigned int cmd = 0x2275;
-	unsigned int base = sdc->ip_base;
-	unsigned int arg;
-	unsigned int num;
-	int   loop_for_command_done_check = DATA_TRANSFER_OVER_TIMEOUT_USEC;	
-	rt_err_t err;	
-	unsigned int rw = 1;
+    static volatile DmaDesc __attribute__ ((aligned(32))) st_pchain;
 
-	buf_chain_t *usrchain;
-	unsigned int length = 0;
+    int   ret;
+    unsigned int intsts = 0;
+    unsigned int cmd = 0x2275;
+    unsigned int base = sdc->ip_base;
+    unsigned int arg;
+    unsigned int num;
+    int   loop_for_command_done_check = DATA_TRANSFER_OVER_TIMEOUT_USEC;
+    rt_err_t err;
+    unsigned int rw = 1;
 
-	if (!chain) {
-		return 0;
-	}
+    buf_chain_t *usrchain;
+    unsigned int length = 0;
 
-	arg = (fn << 28) | (addr << 9);
-	if (bcnt == 1 && bsize <= 512)
-		arg |= (bsize & 0x1ff);
-	else
-		arg |= ((1 << 27) | bcnt);	
-	if ( rw ) {
-		cmd |= 0x400;
-		arg |= (1 << 31);
-	}
-	num = bsize*bcnt;
+    if (!chain) {
+        return 0;
+    }
 
-	err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER);
-	if (err != RT_EOK) {
-		return ERRNORES;
-	}
-	
-	
-	// reset
-	synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO
-	while (synopmob_read_register(base+CTRL) & FIFO_RESET);
-    	synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts
+    arg = (fn << 28) | (addr << 9);
+    if (bcnt == 1 && bsize <= 512)
+        arg |= (bsize & 0x1ff);
+    else
+        arg |= ((1 << 27) | bcnt);
+    if ( rw ) {
+        cmd |= 0x400;
+        arg |= (1 << 31);
+    }
+    num = bsize*bcnt;
 
-	usrchain = chain;
-    	while (1) {    		
-    		if (length + usrchain->size >= sizeof(st_net_buf)) {
-    			while(1) SDIO_PRINTF("too long net pkt\n");
-    		}
-    		
-    		memcpy(st_net_buf + length, usrchain->buf, usrchain->size);
-    		length += usrchain->size;
-    		usrchain = usrchain->next;
-    		if (!usrchain || usrchain->next == chain) {
-    			break;
-    		}
-    	}
-    	
-    	st_pchain.desc0 = DescOwnByDma | DescSecAddrChained | DescLastDesc | DescFirstDesc;
-    	st_pchain.desc1 = length;
-    	st_pchain.desc2 = (unsigned int)st_net_buf;
- 	st_pchain.desc3 = (unsigned int)&st_pchain;
-	flush_dcache_range((unsigned long)st_net_buf, length);	
-	
-	if (length != num) {
-		while (1) SDIO_PRINTF("sdio_drv_chain_write:too long packet!\n");
-	}
+    err = rt_sem_take(sdc->mutex, RT_WAITING_FOREVER);
+    if (err != RT_EOK) {
+        return ERRNORES;
+    }
 
-	synopmob_set_register(base+DBADDR, (unsigned int)(&st_pchain));
-    
-	synopmob_set_register(base+BLKSIZ, bsize);
-	synopmob_set_register(base+BYTCNT, num);
-	synopmob_set_bits(base + CTRL, CTRL_USE_IDMAC);
-	synopmob_set_bits(base + BMOD,BMOD_DE);
-	
-	ret = synopmob_execute_command(base, cmd,  arg);
-	if ( !ret ) {
-		ret = ERRIDMA;
-		err = rt_sem_take(sdc->sem, DMA_TRANSFER_TIMEOUT_TICKS);
-		if ( !err ) {
-			while (--loop_for_command_done_check > 0) {
-				intsts = synopmob_read_register(base+RINTSTS);
-				if ((intsts & (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) == (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) {
-					break;
-				}
-				plat_loop(1);
-			}
-			ret = synopmob_handle_standard_rinsts(intsts);
-			if (!ret ) {
-				if( !loop_for_command_done_check || !(sdc->idsts & 0x100)) { //normal interrupt
-					ret = ERRIDMA;
-				}
-			}
-		}
-	}
 
-	if (!ret) {
-		synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts
-		synopmob_clear_bits(base + CTRL, CTRL_USE_IDMAC);
-		synopmob_clear_bits(base + BMOD,BMOD_DE);
-		synopmob_set_register(base+BLKSIZ, 512);
-		synopmob_set_register(base+BYTCNT, 512);
-	}
-	else {
-	   	char* op = "read";
-	   	if (rw) 
-	   		op = "write";
-	   		
-	        SDIO_PRINTF("sdio_drv_chain_write1(%s) fail:, ret = %d\n", op, ret);
-	}
+    // reset
+    synopmob_set_bits(base+CTRL, FIFO_RESET); //reset FIFO
+    while (synopmob_read_register(base+CTRL) & FIFO_RESET);
+        synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts
 
-	if ( rw && !ret ) {
-		ret = synopmob_wait_data_ready(base);
-	}
+    usrchain = chain;
+        while (1) {
+            if (length + usrchain->size >= sizeof(st_net_buf)) {
+                while(1) SDIO_PRINTF("too long net pkt\n");
+            }
 
-	rt_sem_release(sdc->mutex);
+            memcpy(st_net_buf + length, usrchain->buf, usrchain->size);
+            length += usrchain->size;
+            usrchain = usrchain->next;
+            if (!usrchain || usrchain->next == chain) {
+                break;
+            }
+        }
 
-	return ret;
-	//return ret ? 0/*false*/ : 1/*true*/;
+        st_pchain.desc0 = DescOwnByDma | DescSecAddrChained | DescLastDesc | DescFirstDesc;
+        st_pchain.desc1 = length;
+        st_pchain.desc2 = (unsigned int)st_net_buf;
+    st_pchain.desc3 = (unsigned int)&st_pchain;
+    flush_dcache_range((unsigned long)st_net_buf, length);
+
+    if (length != num) {
+        while (1) SDIO_PRINTF("sdio_drv_chain_write:too long packet!\n");
+    }
+
+    synopmob_set_register(base+DBADDR, (unsigned int)(&st_pchain));
+
+    synopmob_set_register(base+BLKSIZ, bsize);
+    synopmob_set_register(base+BYTCNT, num);
+    synopmob_set_bits(base + CTRL, CTRL_USE_IDMAC);
+    synopmob_set_bits(base + BMOD,BMOD_DE);
+
+    ret = synopmob_execute_command(base, cmd,  arg);
+    if ( !ret ) {
+        ret = ERRIDMA;
+        err = rt_sem_take(sdc->sem, DMA_TRANSFER_TIMEOUT_TICKS);
+        if ( !err ) {
+            while (--loop_for_command_done_check > 0) {
+                intsts = synopmob_read_register(base+RINTSTS);
+                if ((intsts & (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) == (INTMSK_CMD_DONE|INTMSK_DAT_OVER)) {
+                    break;
+                }
+                plat_loop(1);
+            }
+            ret = synopmob_handle_standard_rinsts(intsts);
+            if (!ret ) {
+                if( !loop_for_command_done_check || !(sdc->idsts & 0x100)) { //normal interrupt
+                    ret = ERRIDMA;
+                }
+            }
+        }
+    }
+
+    if (!ret) {
+        synopmob_set_register(base + RINTSTS, 0xfffe); //clear interrupts
+        synopmob_clear_bits(base + CTRL, CTRL_USE_IDMAC);
+        synopmob_clear_bits(base + BMOD,BMOD_DE);
+        synopmob_set_register(base+BLKSIZ, 512);
+        synopmob_set_register(base+BYTCNT, 512);
+    }
+    else {
+        char* op = "read";
+        if (rw)
+            op = "write";
+
+            SDIO_PRINTF("sdio_drv_chain_write1(%s) fail:, ret = %d\n", op, ret);
+    }
+
+    if ( rw && !ret ) {
+        ret = synopmob_wait_data_ready(base);
+    }
+
+    rt_sem_release(sdc->mutex);
+
+    return ret;
+    //return ret ? 0/*false*/ : 1/*true*/;
 }
 #endif
 #endif
 
 static int sdio_card_reset(sdc_t* sdc)
 {
-	unsigned int resp;
-	int ret;
+    unsigned int resp;
+    int ret;
 
-	/* Soft Reset card */
+    /* Soft Reset card */
     sdio_drv_creg_write(sdc, 0x6, 0, 0x8, &resp);
 
-	return 0;
+    return 0;
 }
 
 static int enum_sdio_card(sdc_t* sdc)
 {
-	int ret;
-	unsigned int resp;
-	unsigned int base = sdc->ip_base;
+    int ret;
+    unsigned int resp;
+    unsigned int base = sdc->ip_base;
 
-	#if 0
-	synopmob_set_bits(0x98500004, (1<<24)); //set to output mode
-	synopmob_set_bits(0x98500000, (1<<24)); //power off
-	plat_loop(1000000/5); //Lets give some ramp down period
-	synopmob_clear_bits(0x98500000, (1<<24)); //power on
-	plat_loop(1000000/5);//Lets give some ramp down period
-	#endif
+    #if 0
+    synopmob_set_bits(0x98500004, (1<<24)); //set to output mode
+    synopmob_set_bits(0x98500000, (1<<24)); //power off
+    plat_loop(1000000/5); //Lets give some ramp down period
+    synopmob_clear_bits(0x98500000, (1<<24)); //power on
+    plat_loop(1000000/5);//Lets give some ramp down period
+    #endif
 
-	synopmob_set_register(base+CTYPE, ONE_BIT_MODE);
+    synopmob_set_register(base+CTYPE, ONE_BIT_MODE);
 
-	synopmob_set_register(base+CLKENA, 0x00000001); /*enable clock, non-low-power mode*/
-	ret = synopmob_set_clk_freq(sdc, MMC_FOD_DIVIDER_VALUE);
-	
-	if ( !ret ) {
-		plat_loop(100); //enough for 74 clock.	
-		#if 0
-		sdio_card_reset(sdc);
-		plat_loop(100000);
-		#endif
-		ret = sd_send_cmd5(sdc, 0, &resp);
-		if (!ret) {
-			resp &= 0x00ffffff;
-			ret = sd_send_cmd5(sdc, resp, &resp);
-		}
-	}
+    synopmob_set_register(base+CLKENA, 0x00000001); /*enable clock, non-low-power mode*/
+    ret = synopmob_set_clk_freq(sdc, MMC_FOD_DIVIDER_VALUE);
 
-	if (!ret) {
-		ret = sd_send_cmd3(sdc); //get RCA
-	}
-	
-	if (!ret) {
-		ret = sd_send_cmd7(sdc); //select the card
-	}
+    if ( !ret ) {
+        plat_loop(100); //enough for 74 clock.
+        #if 0
+        sdio_card_reset(sdc);
+        plat_loop(100000);
+        #endif
+        ret = sd_send_cmd5(sdc, 0, &resp);
+        if (!ret) {
+            resp &= 0x00ffffff;
+            ret = sd_send_cmd5(sdc, resp, &resp);
+        }
+    }
+
+    if (!ret) {
+        ret = sd_send_cmd3(sdc); //get RCA
+    }
+
+    if (!ret) {
+        ret = sd_send_cmd7(sdc); //select the card
+    }
 
 
-	if (!g_use_bcm43362)
-	{
-	sdio_drv_creg_read(sdc, 0x13, 0, &resp);
-	if ((resp & 1) && (sdc->wkmod & (SDC_WKMOD_4WIRE|SDC_WKMOD_25M_STAND_SPEED|SDC_WKMOD_50M_HI_SPEED))){ //high speed support?
-		if (sdc->wkmod & SDC_WKMOD_4WIRE) {
-			sdio_drv_creg_read(sdc, 0x7, 0, &resp);
-			resp &= 0xfc;
-			resp |= (1 << 1);
-			sdio_drv_creg_write(sdc, 0x7, 0, resp, &resp); //switch to 4bit mode
-			sdio_drv_creg_read(sdc, 0x7, 0, &resp);
-			if ((resp & 0x3) != 0x2) {
-				return  ERRCARDINTERNAL; // 4bit mode failed
-			}
-			synopmob_set_register(base+CTYPE, FOUR_BIT_MODE);
-		}
-		if (sdc->wkmod & (SDC_WKMOD_25M_STAND_SPEED|SDC_WKMOD_50M_HI_SPEED)) {
-			ret = synopmob_set_clk_freq(sdc, ONE_BIT_BUS_FREQ);
-			//ret = synopmob_set_clk_freq(sdc, 0);
-		}
-	}
+    if (!g_use_bcm43362)
+    {
+    sdio_drv_creg_read(sdc, 0x13, 0, &resp);
+    if ((resp & 1) && (sdc->wkmod & (SDC_WKMOD_4WIRE|SDC_WKMOD_25M_STAND_SPEED|SDC_WKMOD_50M_HI_SPEED))){ //high speed support?
+        if (sdc->wkmod & SDC_WKMOD_4WIRE) {
+            sdio_drv_creg_read(sdc, 0x7, 0, &resp);
+            resp &= 0xfc;
+            resp |= (1 << 1);
+            sdio_drv_creg_write(sdc, 0x7, 0, resp, &resp); //switch to 4bit mode
+            sdio_drv_creg_read(sdc, 0x7, 0, &resp);
+            if ((resp & 0x3) != 0x2) {
+                return  ERRCARDINTERNAL; // 4bit mode failed
+            }
+            synopmob_set_register(base+CTYPE, FOUR_BIT_MODE);
+        }
+        if (sdc->wkmod & (SDC_WKMOD_25M_STAND_SPEED|SDC_WKMOD_50M_HI_SPEED)) {
+            ret = synopmob_set_clk_freq(sdc, ONE_BIT_BUS_FREQ);
+            //ret = synopmob_set_clk_freq(sdc, 0);
+        }
+    }
 
-	sdio_drv_creg_read(sdc, 0x3, 0, &resp); 
-	if (!ret) {
-		sdio_drv_creg_read(sdc, 0x0, 0, &resp); //card version
-		sdio_drv_creg_write(sdc, 0x4, 0, 0x3, &resp); //enable interrupts in card
-		sdio_drv_creg_write(sdc, 0x2, 0, 0x2, &resp); //Eable IO in card
-		do {
-			sdio_drv_creg_read(sdc, 0x3, 0, &resp); 
-		} while (!(resp & 2));
-	}
-	} //g_use_bcm43362
+    sdio_drv_creg_read(sdc, 0x3, 0, &resp);
+    if (!ret) {
+        sdio_drv_creg_read(sdc, 0x0, 0, &resp); //card version
+        sdio_drv_creg_write(sdc, 0x4, 0, 0x3, &resp); //enable interrupts in card
+        sdio_drv_creg_write(sdc, 0x2, 0, 0x2, &resp); //Eable IO in card
+        do {
+            sdio_drv_creg_read(sdc, 0x3, 0, &resp);
+        } while (!(resp & 2));
+    }
+    } //g_use_bcm43362
 
-	sdc->card_type = SDIO_TYPE;
+    sdc->card_type = SDIO_TYPE;
 
-	synopmob_set_bits(base+CTRL, INT_ENABLE);
-	
-	return ret;
+    synopmob_set_bits(base+CTRL, INT_ENABLE);
+
+    return ret;
 }
 
 int sdio_high_speed_mode(HSDC handle, int bitwidth, int freq)
 {
-	int ret;
-	sdc_t* sdc = (sdc_t*)handle;
+    int ret;
+    sdc_t* sdc = (sdc_t*)handle;
 
-	if (bitwidth == 4)
-	{
-		synopmob_set_register(sdc->ip_base+CTYPE, FOUR_BIT_MODE);
-	}
+    if (bitwidth == 4)
+    {
+        synopmob_set_register(sdc->ip_base+CTYPE, FOUR_BIT_MODE);
+    }
 
-	ret = synopmob_set_clk_freq(sdc, /*ONE_BIT_BUS_FREQ*/1);
-	if (ret != 0)
-	{
-		SDIO_PRINTF("sdio_high_speed_mode fail:, ret = %d\n", ret);
-	}
+    ret = synopmob_set_clk_freq(sdc, /*ONE_BIT_BUS_FREQ*/1);
+    if (ret != 0)
+    {
+        SDIO_PRINTF("sdio_high_speed_mode fail:, ret = %d\n", ret);
+    }
 
-	return ret;
+    return ret;
 }
 
 static int common_init(unsigned int which, unsigned int sdio, unsigned int wkmod, unsigned int* dma_desc, HSDC* phandle)
 {
-	int    ret = ERRNORES;
-	sdc_t* sdc;
-	unsigned int  base;
-	unsigned int  temp;
-	unsigned int  fifo_thresh;
-	volatile DmaDesc *pDmaDesc;
-	rt_sem_t sem;
-	rt_sem_t mutex;
-	
-	base = SDC0_REG_BASE;
-	temp = PMU_SDC0_RST_BIT;
-	if (which > 0) {
-		base = SDC1_REG_BASE;
-		temp = PMU_SDC1_RST_BIT;
-	}
-	
+    int    ret = ERRNORES;
+    sdc_t* sdc;
+    unsigned int  base;
+    unsigned int  temp;
+    unsigned int  fifo_thresh;
+    volatile DmaDesc *pDmaDesc;
+    rt_sem_t sem;
+    rt_sem_t mutex;
+
+    base = SDC0_REG_BASE;
+    temp = PMU_SDC0_RST_BIT;
+    if (which > 0) {
+        base = SDC1_REG_BASE;
+        temp = PMU_SDC1_RST_BIT;
+    }
+
 #if 0
-	//PMU_RST_MODULE(temp); plat_loop(1);
-	temp = synopmob_read_register(PMU_REG_CLK_DIV3);
-	temp &= (~(0x0f<<8));
-	temp |= (0xf<<8);
-	synopmob_set_register(PMU_REG_CLK_DIV3, temp);
+    //PMU_RST_MODULE(temp); plat_loop(1);
+    temp = synopmob_read_register(PMU_REG_CLK_DIV3);
+    temp &= (~(0x0f<<8));
+    temp |= (0xf<<8);
+    synopmob_set_register(PMU_REG_CLK_DIV3, temp);
 #endif
-	*phandle = (HSDC)0;
-	
-	sdc = &sdc_array[which];
-	sem = sdc->sem;
-	mutex = sdc->mutex;
-	memset((void *)sdc, 0, sizeof(*sdc));
-	sdc->wkmod = wkmod;
-	sdc->idma_support = 0;
-	sdc->ip_base = base;
-	sdc->rca = 0;
-	sdc->card_type = NONE_TYPE;
-	if (!sem) {
-		sem = rt_sem_create("fh_sdio_sem", 0, RT_IPC_FLAG_PRIO);//OSSemCreate (0);
-		if ( !sem ) {
-			return ret;
-		}
-	}
-	sdc->sem = sem;
+    *phandle = (HSDC)0;
 
-	if (!mutex) {
-		mutex = rt_sem_create("fh_sdio_mutex", 1, RT_IPC_FLAG_PRIO);//OSSemCreate (1);
-		if ( !mutex ) {
-			return ret;
-		}
-	}
-	sdc->mutex = mutex;
-	
-	synopmob_set_bits(base + CTRL, CTRL_RESET); //reset host controller
-	plat_loop(100);
+    sdc = &sdc_array[which];
+    sem = sdc->sem;
+    mutex = sdc->mutex;
+    memset((void *)sdc, 0, sizeof(*sdc));
+    sdc->wkmod = wkmod;
+    sdc->idma_support = 0;
+    sdc->ip_base = base;
+    sdc->rca = 0;
+    sdc->card_type = NONE_TYPE;
+    if (!sem) {
+        sem = rt_sem_create("fh_sdio_sem", 0, RT_IPC_FLAG_PRIO);//OSSemCreate (0);
+        if ( !sem ) {
+            return ret;
+        }
+    }
+    sdc->sem = sem;
 
-	synopmob_clear_bits(base + CTRL,CTRL_USE_IDMAC);
-	sdc->idma_support = 1; //fixed to support IDMA
+    if (!mutex) {
+        mutex = rt_sem_create("fh_sdio_mutex", 1, RT_IPC_FLAG_PRIO);//OSSemCreate (1);
+        if ( !mutex ) {
+            return ret;
+        }
+    }
+    sdc->mutex = mutex;
 
-	pDmaDesc = (volatile DmaDesc *)dma_desc;
-	sdc->pDmaDesc = pDmaDesc;
-	if (sdc->idma_support) {
-		synopmob_set_bits(base + CTRL, DMA_RESET);
-		plat_loop(100);
-		synopmob_set_bits(base + CTRL, FIFO_RESET);
-		plat_loop(100);
-		synopmob_set_bits(base + BMOD, BMOD_SWR);
-		plat_loop(100);
-		
-		//synopmob_set_bits(base + BMOD,BMOD_DE);		
-		pDmaDesc->desc0 = DescSecAddrChained;
-		pDmaDesc->desc1 = 0;
-		pDmaDesc->desc2 = 0;
-		pDmaDesc->desc3 = (unsigned int)(pDmaDesc);
-		synopmob_set_register(base + DBADDR, (unsigned int)(pDmaDesc));
-	}
+    synopmob_set_bits(base + CTRL, CTRL_RESET); //reset host controller
+    plat_loop(100);
 
-	synopmob_set_register(base+CTYPE, ONE_BIT_MODE);
+    synopmob_clear_bits(base + CTRL,CTRL_USE_IDMAC);
+    sdc->idma_support = 1; //fixed to support IDMA
 
-	synopmob_set_register(base+RINTSTS, 0xffffffff);//clear interrupt.
-	synopmob_clear_bits(base+CTRL, INT_ENABLE);
-	synopmob_set_register(base+INTMSK, 0); // mask all INTR
-	synopmob_set_register(base+IDINTEN, IDMAINTBITS); //Enable DMA INTR
+    pDmaDesc = (volatile DmaDesc *)dma_desc;
+    sdc->pDmaDesc = pDmaDesc;
+    if (sdc->idma_support) {
+        synopmob_set_bits(base + CTRL, DMA_RESET);
+        plat_loop(100);
+        synopmob_set_bits(base + CTRL, FIFO_RESET);
+        plat_loop(100);
+        synopmob_set_bits(base + BMOD, BMOD_SWR);
+        plat_loop(100);
+
+        //synopmob_set_bits(base + BMOD,BMOD_DE);
+        pDmaDesc->desc0 = DescSecAddrChained;
+        pDmaDesc->desc1 = 0;
+        pDmaDesc->desc2 = 0;
+        pDmaDesc->desc3 = (unsigned int)(pDmaDesc);
+        synopmob_set_register(base + DBADDR, (unsigned int)(pDmaDesc));
+    }
+
+    synopmob_set_register(base+CTYPE, ONE_BIT_MODE);
+
+    synopmob_set_register(base+RINTSTS, 0xffffffff);//clear interrupt.
+    synopmob_clear_bits(base+CTRL, INT_ENABLE);
+    synopmob_set_register(base+INTMSK, 0); // mask all INTR
+    synopmob_set_register(base+IDINTEN, IDMAINTBITS); //Enable DMA INTR
 
 
-	synopmob_set_register(base+TMOUT, 0xffffffff); /* Set Data and Response timeout to Maximum Value*/
+    synopmob_set_register(base+TMOUT, 0xffffffff); /* Set Data and Response timeout to Maximum Value*/
 
-	/* Set the card Debounce to allow the CDETECT fluctuations to settle down*/	
-	synopmob_set_register(base+DEBNCE, 0x0FFFFF);
+    /* Set the card Debounce to allow the CDETECT fluctuations to settle down*/
+    synopmob_set_register(base+DEBNCE, 0x0FFFFF);
 
-	fifo_thresh = synopmob_read_register(base+FIFOTH);
-	//fifo_thresh = GET_FIFO_DEPTH(fifo_thresh) / 2;
-	fifo_thresh = (GET_FIFO_DEPTH(fifo_thresh) + 1) / 2;
-	sdc->fifo_depth = fifo_thresh * 2;	
-	sdc->fifo_threth = fifo_thresh;
-	/* Tx Watermark */
-	synopmob_clear_bits(base+FIFOTH, 0xfff);
-	synopmob_set_bits(base+FIFOTH, fifo_thresh);
-	/* Rx Watermark */
-	synopmob_clear_bits(base+FIFOTH, 0x0fff0000);
-	synopmob_set_bits(base+FIFOTH, (fifo_thresh-1) << 16);
-	//synopmob_set_bits(base+FIFOTH, 2<< 28);
+    fifo_thresh = synopmob_read_register(base+FIFOTH);
+    //fifo_thresh = GET_FIFO_DEPTH(fifo_thresh) / 2;
+    fifo_thresh = (GET_FIFO_DEPTH(fifo_thresh) + 1) / 2;
+    sdc->fifo_depth = fifo_thresh * 2;
+    sdc->fifo_threth = fifo_thresh;
+    /* Tx Watermark */
+    synopmob_clear_bits(base+FIFOTH, 0xfff);
+    synopmob_set_bits(base+FIFOTH, fifo_thresh);
+    /* Rx Watermark */
+    synopmob_clear_bits(base+FIFOTH, 0x0fff0000);
+    synopmob_set_bits(base+FIFOTH, (fifo_thresh-1) << 16);
+    //synopmob_set_bits(base+FIFOTH, 2<< 28);
 
-	if (!sdio) {
-		ret = enum_sd_card(sdc);
-	}
-	else {
-		ret = enum_sdio_card(sdc);
-	}
+    if (!sdio) {
+        ret = enum_sd_card(sdc);
+    }
+    else {
+        ret = enum_sdio_card(sdc);
+    }
 
-	if (!ret) {
-		*phandle = (HSDC)sdc;
-	}
+    if (!ret) {
+        *phandle = (HSDC)sdc;
+    }
 
-	return ret;
+    return ret;
 }
 
 int sdc_is_connected(unsigned int which)
 {
-	unsigned int base = SDC0_REG_BASE;
-	
-	if (which > 0)
-		base = SDC1_REG_BASE;
+    unsigned int base = SDC0_REG_BASE;
 
-	return !(synopmob_read_register(base+CDETECT) & 1);
+    if (which > 0)
+        base = SDC1_REG_BASE;
+
+    return !(synopmob_read_register(base+CDETECT) & 1);
 }
 
 int sdc_init(unsigned int which, unsigned int wkmod, unsigned int* dma_desc, HSDC* phandle)
 {
-	return common_init(which, 0, wkmod, dma_desc, phandle);
+    return common_init(which, 0, wkmod, dma_desc, phandle);
 }
 
 int sdio_init(unsigned int which, unsigned int wkmod, unsigned int* dma_desc, HSDC* phandle)
 {
-	return common_init(which, 1, wkmod, dma_desc, phandle);
+    return common_init(which, 1, wkmod, dma_desc, phandle);
 }
 
 int sdio_enable_card_int(HSDC handle, int enable)
 {
-	unsigned int base = ((sdc_t*)handle)->ip_base;
+    unsigned int base = ((sdc_t*)handle)->ip_base;
 
-	if (enable) {
-		//synopmob_set_register(base+INTMSK, INTMSK_SDIO);
-		synopmob_set_register(base+INTMSK, (synopmob_read_register(base+INTMSK) | INTMSK_SDIO ));
-	}
-	else {
-		//synopmob_set_register(base+INTMSK, 0);
-		synopmob_set_register(base+INTMSK, (synopmob_read_register(base+INTMSK) & ~INTMSK_SDIO ));
-	}
+    if (enable) {
+        //synopmob_set_register(base+INTMSK, INTMSK_SDIO);
+        synopmob_set_register(base+INTMSK, (synopmob_read_register(base+INTMSK) | INTMSK_SDIO ));
+    }
+    else {
+        //synopmob_set_register(base+INTMSK, 0);
+        synopmob_set_register(base+INTMSK, (synopmob_read_register(base+INTMSK) & ~INTMSK_SDIO ));
+    }
 
-	return 0;
+    return 0;
 }
 
 int sdio_set_card_int_cb(HSDC handle, void (*cb)(void))
 {
-	((sdc_t*)handle)->cb = cb;
+    ((sdc_t*)handle)->cb = cb;
 
-	return 0;
+    return 0;
 }
 
 static void OSSDCISR(sdc_t* sdc)
 {
-	unsigned int sts;
-	unsigned int base;
+    unsigned int sts;
+    unsigned int base;
 
-	base = sdc->ip_base;
-	sts = synopmob_read_register(base+IDSTS);
-	if ( sts ) {
-		synopmob_set_register(base+IDSTS, sts);
-		sdc->idsts = sts;
-		rt_sem_release(sdc->sem);
-	}
+    base = sdc->ip_base;
+    sts = synopmob_read_register(base+IDSTS);
+    if ( sts ) {
+        synopmob_set_register(base+IDSTS, sts);
+        sdc->idsts = sts;
+        rt_sem_release(sdc->sem);
+    }
 
-	//sts = synopmob_read_register(base+RINTSTS);
-	sts = synopmob_read_register(base+MINTSTS);
-	sts &= INTMSK_SDIO;
-	if ( sts ) { //interrupt from WIFI card.
-		//synopmob_set_register(base+INTMSK, 0); //mask all the interrupt	
-		synopmob_set_register(base+INTMSK, synopmob_read_register(base+INTMSK) & ~INTMSK_SDIO ); //mask sdio interrupt	
-		synopmob_set_register(base+RINTSTS, sts);
-		synopmob_set_register(base+MINTSTS, sts);
-		if (sdc->cb) {
-			sdc->cb();
-		}
-	}
+    //sts = synopmob_read_register(base+RINTSTS);
+    sts = synopmob_read_register(base+MINTSTS);
+    sts &= INTMSK_SDIO;
+    if ( sts ) { //interrupt from WIFI card.
+        //synopmob_set_register(base+INTMSK, 0); //mask all the interrupt
+        synopmob_set_register(base+INTMSK, synopmob_read_register(base+INTMSK) & ~INTMSK_SDIO ); //mask sdio interrupt
+        synopmob_set_register(base+RINTSTS, sts);
+        synopmob_set_register(base+MINTSTS, sts);
+        if (sdc->cb) {
+            sdc->cb();
+        }
+    }
 }
 
 void OSSDCINTR_0(int vector, void *param)
 {
-	OSSDCISR(&sdc_array[0]);
+    OSSDCISR(&sdc_array[0]);
 }
 
 void OSSDCINTR_1(int vector, void *param)
 {
-	OSSDCISR(&sdc_array[1]);
+    OSSDCISR(&sdc_array[1]);
 }
 
 void fh_sdio0_init(void)
 {
     int sd0_irq = SDC0_IRQn;
-    
+
     rt_hw_interrupt_install(sd0_irq, OSSDCINTR_0, NULL, NULL);
     rt_hw_interrupt_umask(sd0_irq);
 }
@@ -2058,7 +2058,7 @@ void fh_sdio0_init(void)
 void fh_sdio1_init(void)
 {
     int sd1_irq = SDC1_IRQn;
-    
+
     rt_hw_interrupt_install(sd1_irq, OSSDCINTR_1, NULL, NULL);
     rt_hw_interrupt_umask(sd1_irq);
 }
@@ -2071,14 +2071,14 @@ void fh_sdio_init(void)
 
 int sdc_deinit(HSDC handle)
 {
-	return -1;  // TBD... fix me
+    return -1;  // TBD... fix me
 }
 
 int sdc_set_clk_divider(unsigned int divider)
 {
     if(divider > 255)
         return -1;
-    
+
     sdc_clk_divider = divider;
     return 0;
 }
diff --git a/bsp/fh8620/libraries/driverlib/fh_spi.c b/bsp/fh8620/libraries/driverlib/fh_spi.c
index 14d8039732..14e47ad73b 100644
--- a/bsp/fh8620/libraries/driverlib/fh_spi.c
+++ b/bsp/fh8620/libraries/driverlib/fh_spi.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/fh8620/libraries/driverlib/fh_timer.c b/bsp/fh8620/libraries/driverlib/fh_timer.c
index f3034adeaa..eab30888a5 100644
--- a/bsp/fh8620/libraries/driverlib/fh_timer.c
+++ b/bsp/fh8620/libraries/driverlib/fh_timer.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 /*****************************************************************************
  *  Include Section
  *  add all #include here
@@ -79,66 +79,66 @@
  *****************************************************************************/
 int timer_init(timer *tim)
 {
-	tim->TIMER_CTRL_REG = 0;
+    tim->TIMER_CTRL_REG = 0;
 }
 
 int timer_set_mode(timer *tim, enum timer_mode mode)
 {
-	switch (mode)
-	{
-		case TIMER_MODE_PERIODIC:
-			tim->TIMER_CTRL_REG |= TIMER_CTRL_MODE;
-			break;
-		case TIMER_MODE_ONESHOT:
-			tim->TIMER_CTRL_REG |= TIMER_CTRL_MODE;
-			break;
-		default:
-			rt_kprintf("Not support TIMER mode\n");
-			return -1;
-			break;
-	}
+    switch (mode)
+    {
+        case TIMER_MODE_PERIODIC:
+            tim->TIMER_CTRL_REG |= TIMER_CTRL_MODE;
+            break;
+        case TIMER_MODE_ONESHOT:
+            tim->TIMER_CTRL_REG |= TIMER_CTRL_MODE;
+            break;
+        default:
+            rt_kprintf("Not support TIMER mode\n");
+            return -1;
+            break;
+    }
 
-	return 0;
+    return 0;
 }
 
 void timer_set_period(timer *tim, UINT32 period, UINT32 clock)
 {
-	tim->TIMER_LOAD_COUNT = clock/period;
+    tim->TIMER_LOAD_COUNT = clock/period;
 }
 
 
 
 void timer_enable(timer *tim)
 {
-	tim->TIMER_CTRL_REG |= TIMER_CTRL_ENABLE;
+    tim->TIMER_CTRL_REG |= TIMER_CTRL_ENABLE;
 }
 
 void timer_disable(timer *tim)
 {
-	tim->TIMER_CTRL_REG &= ~TIMER_CTRL_ENABLE;
+    tim->TIMER_CTRL_REG &= ~TIMER_CTRL_ENABLE;
 }
 
 void timer_enable_irq(timer *tim)
 {
-	tim->TIMER_CTRL_REG &= ~TIMER_CTRL_INTMASK;
+    tim->TIMER_CTRL_REG &= ~TIMER_CTRL_INTMASK;
 }
 
 void timer_disable_irq(timer *tim)
 {
-	tim->TIMER_CTRL_REG |= TIMER_CTRL_INTMASK;
+    tim->TIMER_CTRL_REG |= TIMER_CTRL_INTMASK;
 }
 
 UINT32 timer_get_status(timer *tim)
 {
-	return tim->TIMER_INT_STATUS;
+    return tim->TIMER_INT_STATUS;
 }
 
 UINT32 timer_get_eoi(timer *tim)
 {
-	return tim->TIMER_EOI;
+    return tim->TIMER_EOI;
 }
 
 UINT32 timer_get_value(timer *tim)
 {
-	return tim->TIMER_LOAD_COUNT - tim->TIMER_CURRENT_VALUE;
+    return tim->TIMER_LOAD_COUNT - tim->TIMER_CURRENT_VALUE;
 }
diff --git a/bsp/fh8620/libraries/driverlib/fh_uart.c b/bsp/fh8620/libraries/driverlib/fh_uart.c
index 0d9ad1f35d..75b453c9fb 100644
--- a/bsp/fh8620/libraries/driverlib/fh_uart.c
+++ b/bsp/fh8620/libraries/driverlib/fh_uart.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 /*****************************************************************************
  *  Include Section
  *  add all #include here
@@ -79,33 +79,33 @@
 
 int uart_init(uart *port)
 {
-	port->UART_IER = 0;
-	port->UART_LCR = 0;
-	//port->UART_DLL = 0;
-	//port->UART_DLH = 0;
+    port->UART_IER = 0;
+    port->UART_LCR = 0;
+    //port->UART_DLL = 0;
+    //port->UART_DLH = 0;
 }
 
 UINT32 uart_get_status(uart *port)
 {
-	return port->UART_USR;
+    return port->UART_USR;
 }
 
 
 void uart_configure(uart *port, enum data_bits data_bit,
-					enum stop_bits stop_bit, enum parity parity,
-					UINT32 buard_rate, UINT32 uart_clk)
+                    enum stop_bits stop_bit, enum parity parity,
+                    UINT32 buard_rate, UINT32 uart_clk)
 {
-	UINT32 divisor;
-	UINT32 freq;
-	UINT32 baud_div;
-	UINT32 lcr_reg = 0;
-	UINT32 ret;
+    UINT32 divisor;
+    UINT32 freq;
+    UINT32 baud_div;
+    UINT32 lcr_reg = 0;
+    UINT32 ret;
 
-	/*divisor = DIV(buard_rate);
-	port->UART_LCR |= UART_LCR_DLAB;
-	port->UART_DLL = divisor & 0xFF;
-	port->UART_DLH = (divisor >> 8) & 0xFF;
-	port->UART_LCR &= ~UART_LCR_DLAB;*/
+    /*divisor = DIV(buard_rate);
+    port->UART_LCR |= UART_LCR_DLAB;
+    port->UART_DLL = divisor & 0xFF;
+    port->UART_DLH = (divisor >> 8) & 0xFF;
+    port->UART_LCR &= ~UART_LCR_DLAB;*/
 
     do{
         //clear fifo...
@@ -113,141 +113,141 @@ void uart_configure(uart *port, enum data_bits data_bit,
         //read status..
         ret = uart_get_status(port);
     }while(ret & UART_USR_BUSY);
-	switch (data_bit) {
-		case UART_DATA_BIT5:
-			lcr_reg |= UART_LCR_DLS5;
-			break;
-		case UART_DATA_BIT6:
-			lcr_reg |= UART_LCR_DLS6;
-			break;
-		case UART_DATA_BIT7:
-			lcr_reg |= UART_LCR_DLS7;
-			break;
-		case UART_DATA_BIT8:
-			lcr_reg |= UART_LCR_DLS8;
-			break;
-		default:
-			lcr_reg |= UART_LCR_DLS8;
-			break;
-	}
+    switch (data_bit) {
+        case UART_DATA_BIT5:
+            lcr_reg |= UART_LCR_DLS5;
+            break;
+        case UART_DATA_BIT6:
+            lcr_reg |= UART_LCR_DLS6;
+            break;
+        case UART_DATA_BIT7:
+            lcr_reg |= UART_LCR_DLS7;
+            break;
+        case UART_DATA_BIT8:
+            lcr_reg |= UART_LCR_DLS8;
+            break;
+        default:
+            lcr_reg |= UART_LCR_DLS8;
+            break;
+    }
 
-	switch (stop_bit) {
-		case UART_STOP_BIT1:
-			lcr_reg |= UART_LCR_STOP1;
-			break;
-		case UART_STOP_BIT2:
-			lcr_reg |= UART_LCR_STOP2;
-			break;
-		default:
-			lcr_reg |= UART_LCR_STOP1;
-			break;
-	}
+    switch (stop_bit) {
+        case UART_STOP_BIT1:
+            lcr_reg |= UART_LCR_STOP1;
+            break;
+        case UART_STOP_BIT2:
+            lcr_reg |= UART_LCR_STOP2;
+            break;
+        default:
+            lcr_reg |= UART_LCR_STOP1;
+            break;
+    }
 
-	switch (parity) {
-		case UART_PARITY_EVEN:
-			lcr_reg |= UART_LCR_EVEN | UART_LCR_PEN;
-			break;
-		case UART_PARITY_ODD:
-			lcr_reg |= UART_LCR_PEN;
-			break;
-		case UART_PARITY_ST:
-			lcr_reg |= UART_LCR_SP;
-			break;
-		case UART_PARITY_NONE:
-		default:
-			break;
-	}
+    switch (parity) {
+        case UART_PARITY_EVEN:
+            lcr_reg |= UART_LCR_EVEN | UART_LCR_PEN;
+            break;
+        case UART_PARITY_ODD:
+            lcr_reg |= UART_LCR_PEN;
+            break;
+        case UART_PARITY_ST:
+            lcr_reg |= UART_LCR_SP;
+            break;
+        case UART_PARITY_NONE:
+        default:
+            break;
+    }
 
 
 
-	switch (buard_rate) {
-		case 115200:
-			baud_div =  BAUDRATE_115200;
-			break;
-		case 57600:
-			baud_div =  BAUDRATE_57600;
-			break;
-		case 38400:
-			baud_div =  BAUDRATE_38400;
-			break;
-		case 19200:
-			baud_div =  BAUDRATE_19200;
-			break;
-		case 9600:
-			baud_div =  BAUDRATE_9600;
-			break;
-		default:
-			baud_div = BAUDRATE_115200;
-			break;
-	}
+    switch (buard_rate) {
+        case 115200:
+            baud_div =  BAUDRATE_115200;
+            break;
+        case 57600:
+            baud_div =  BAUDRATE_57600;
+            break;
+        case 38400:
+            baud_div =  BAUDRATE_38400;
+            break;
+        case 19200:
+            baud_div =  BAUDRATE_19200;
+            break;
+        case 9600:
+            baud_div =  BAUDRATE_9600;
+            break;
+        default:
+            baud_div = BAUDRATE_115200;
+            break;
+    }
 
-	//clear fifo
-	port->UART_FCR = UART_FCR_RFIFOR | UART_FCR_XFIFOR;
+    //clear fifo
+    port->UART_FCR = UART_FCR_RFIFOR | UART_FCR_XFIFOR;
 
-	//div
-	ret = port->UART_LCR;
-	ret |= UART_LCR_DLAB;
-	port->UART_LCR = ret;
-	port->RBRTHRDLL = baud_div & 0x00ff;
-	port->DLHIER = (baud_div & 0x00ff)>>8;
-	/* clear DLAB */
-	ret = ret & 0x7f;
-	port->UART_LCR = ret;
+    //div
+    ret = port->UART_LCR;
+    ret |= UART_LCR_DLAB;
+    port->UART_LCR = ret;
+    port->RBRTHRDLL = baud_div & 0x00ff;
+    port->DLHIER = (baud_div & 0x00ff)>>8;
+    /* clear DLAB */
+    ret = ret & 0x7f;
+    port->UART_LCR = ret;
 
-	//line control
-	port->UART_LCR = lcr_reg;
-	//fifo control
-	port->UART_FCR = UART_FCR_FIFOE | UART_FCR_RFIFOR | UART_FCR_XFIFOR | UART_FCR_TET_1_4 | UART_FCR_RT_ONE;
+    //line control
+    port->UART_LCR = lcr_reg;
+    //fifo control
+    port->UART_FCR = UART_FCR_FIFOE | UART_FCR_RFIFOR | UART_FCR_XFIFOR | UART_FCR_TET_1_4 | UART_FCR_RT_ONE;
 
 }
 
 
 int uart_enable_irq(uart *port, UINT32 mode)
 {
-	unsigned int ret;
-	ret = port->UART_IER;
-	ret |= mode;
-	port->UART_IER = ret;
+    unsigned int ret;
+    ret = port->UART_IER;
+    ret |= mode;
+    port->UART_IER = ret;
 }
 
 int uart_disable_irq(uart *port, UINT32 mode)
 {
-	unsigned int ret;
-	ret = port->UART_IER;
-	ret &= ~mode;
+    unsigned int ret;
+    ret = port->UART_IER;
+    ret &= ~mode;
 
-	port->UART_IER = ret;
+    port->UART_IER = ret;
 }
 
 UINT32 uart_get_iir_status(uart *port)
 {
-	return port->UART_IIR;
+    return port->UART_IIR;
 }
 
 UINT32 uart_get_line_status(uart *port)
 {
-	return port->UART_LSR;
+    return port->UART_LSR;
 }
 
 UINT32 uart_is_rx_ready(uart *port)
 {
-	return port->UART_LSR & UART_LSR_DR;
+    return port->UART_LSR & UART_LSR_DR;
 }
 
 UINT8 uart_getc(uart *port)
 {
-	return port->UART_RBR & 0xFF;
+    return port->UART_RBR & 0xFF;
 }
 
 void uart_putc(uart *port, UINT8 c)
 {
-	//while(!(port->UART_USR & UART_USR_TFNF));
-	port->UART_THR = c;
+    //while(!(port->UART_USR & UART_USR_TFNF));
+    port->UART_THR = c;
 }
 
 void uart_set_fifo_mode(uart *port, UINT32 fifo_mode)
 {
-	port->UART_FCR = fifo_mode;
+    port->UART_FCR = fifo_mode;
 }
 
 
diff --git a/bsp/fh8620/libraries/driverlib/fh_wdt.c b/bsp/fh8620/libraries/driverlib/fh_wdt.c
index 002a929bba..33e3defa1e 100644
--- a/bsp/fh8620/libraries/driverlib/fh_wdt.c
+++ b/bsp/fh8620/libraries/driverlib/fh_wdt.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/fh8620/libraries/inc/fh_driverlib.h b/bsp/fh8620/libraries/inc/fh_driverlib.h
index 9bb6b8c75d..9f45eb836f 100644
--- a/bsp/fh8620/libraries/inc/fh_driverlib.h
+++ b/bsp/fh8620/libraries/inc/fh_driverlib.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #include 
 #include 
 #include "fh_def.h"
diff --git a/bsp/fh8620/libraries/inc/fh_gpio.h b/bsp/fh8620/libraries/inc/fh_gpio.h
index 62d1823eba..3d98a44be3 100644
--- a/bsp/fh8620/libraries/inc/fh_gpio.h
+++ b/bsp/fh8620/libraries/inc/fh_gpio.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #ifndef FH_GPIO_H_
 #define FH_GPIO_H_
 
diff --git a/bsp/fh8620/libraries/inc/fh_i2c.h b/bsp/fh8620/libraries/inc/fh_i2c.h
index 4debd9926d..069aa8f275 100644
--- a/bsp/fh8620/libraries/inc/fh_i2c.h
+++ b/bsp/fh8620/libraries/inc/fh_i2c.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #ifndef FH_I2C_H_
 #define FH_I2C_H_
 
diff --git a/bsp/fh8620/libraries/inc/fh_ictl.h b/bsp/fh8620/libraries/inc/fh_ictl.h
index 9796c99afc..6959715377 100644
--- a/bsp/fh8620/libraries/inc/fh_ictl.h
+++ b/bsp/fh8620/libraries/inc/fh_ictl.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
@@ -30,21 +30,21 @@
 #include "fh_def.h"
 
 typedef struct {
-	RwReg IRQ_EN_L;
-	RwReg IRQ_EN_H;
-	RwReg IRQ_MASK_L;
-	RwReg IRQ_MASK_H;
-	RwReg IRQ_FORCE_L;
-	RwReg IRQ_FORCE_H;
-	RwReg IRQ_RAWSTARUS_L;
-	RwReg IRQ_RAWSTARUS_H;
-	RwReg IRQ_STATUS_L;
-	RwReg IRQ_STATUS_H;
-	RwReg IRQ_MASKSTATUS_L;
-	RwReg IRQ_MASKSTATUS_H;
-	RwReg IRQ_FINALSTATUS_L;
-	RwReg IRQ_FINALSTATUS_H;
-	RwReg IRQ_VECTOR;
+    RwReg IRQ_EN_L;
+    RwReg IRQ_EN_H;
+    RwReg IRQ_MASK_L;
+    RwReg IRQ_MASK_H;
+    RwReg IRQ_FORCE_L;
+    RwReg IRQ_FORCE_H;
+    RwReg IRQ_RAWSTARUS_L;
+    RwReg IRQ_RAWSTARUS_H;
+    RwReg IRQ_STATUS_L;
+    RwReg IRQ_STATUS_H;
+    RwReg IRQ_MASKSTATUS_L;
+    RwReg IRQ_MASKSTATUS_H;
+    RwReg IRQ_FINALSTATUS_L;
+    RwReg IRQ_FINALSTATUS_H;
+    RwReg IRQ_VECTOR;
 }fh_intc;
 
 
diff --git a/bsp/fh8620/libraries/inc/fh_mmc.h b/bsp/fh8620/libraries/inc/fh_mmc.h
index 4aaf416ce6..d999ecf7dd 100644
--- a/bsp/fh8620/libraries/inc/fh_mmc.h
+++ b/bsp/fh8620/libraries/inc/fh_mmc.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/fh8620/libraries/inc/fh_pwm.h b/bsp/fh8620/libraries/inc/fh_pwm.h
index 011da43905..6281a5f128 100644
--- a/bsp/fh8620/libraries/inc/fh_pwm.h
+++ b/bsp/fh8620/libraries/inc/fh_pwm.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/fh8620/libraries/inc/fh_sdio.h b/bsp/fh8620/libraries/inc/fh_sdio.h
index b268dbd322..f4791605e1 100644
--- a/bsp/fh8620/libraries/inc/fh_sdio.h
+++ b/bsp/fh8620/libraries/inc/fh_sdio.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
@@ -32,53 +32,53 @@
 //#define __ASIC_BRANCH__
 
 enum {
-	CTRL        = 0x0, 	/** Control */
-	PWREN    = 0x4, 	/** Power-enable */
-	CLKDIV   = 0x8, 	/** Clock divider */
-	CLKSRC   = 0xC, 	/** Clock source */
-	CLKENA   = 0x10,    /** Clock enable */
-	TMOUT    = 0x14,    /** Timeout */
-	CTYPE    = 0x18,    /** Card type */
-	BLKSIZ   = 0x1C,    /** Block Size */
-	BYTCNT   = 0x20,    /** Byte count */
-	INTMSK   = 0x24,    /** Interrupt Mask */
-	CMDARG   = 0x28,    /** Command Argument */
-	CMD      = 0x2C,    /** Command */
-	RESP0    = 0x30,    /** Response 0 */
-	RESP1    = 0x34,    /** Response 1 */
-	RESP2    = 0x38,    /** Response 2 */
-	RESP3    = 0x3C,    /** Response 3 */
-	MINTSTS  = 0x40,    /** Masked interrupt status */
-	RINTSTS  = 0x44,    /** Raw interrupt status */
-	STATUS   = 0x48,    /** Status */
-	FIFOTH   = 0x4C,    /** FIFO threshold */
-	CDETECT  = 0x50,    /** Card detect */
-	WRTPRT   = 0x54,    /** Write protect */
-	GPIO     = 0x58,    /** General Purpose IO */
-	TCBCNT   = 0x5C,    /** Transferred CIU byte count */
-	TBBCNT   = 0x60,    /** Transferred host/DMA to/from byte count */
-	DEBNCE   = 0x64,    /** Card detect debounce */
-	USRID    = 0x68,    /** User ID */
-	VERID    = 0x6C,    /** Version ID */
-	HCON     = 0x70,    /** Hardware Configuration */
-	UHSREG   = 0x74,    /** Reserved */
- 	BMOD	 = 0x80,    /** Bus mode Register */
-	PLDMND	 = 0x84,    /** Poll Demand */
-	DBADDR	 = 0x88,    /** Descriptor Base Address */
-	IDSTS	 = 0x8C,    /** Internal DMAC Status */
-	IDINTEN  = 0x90,    /** Internal DMAC Interrupt Enable */
-	DSCADDR  = 0x94,    /** Current Host Descriptor Address */
-	BUFADDR	 = 0x98,    /** Current Host Buffer Address */
-	FIFODAT  = 0x200,   /** FIFO data read write */
+    CTRL        = 0x0,  /** Control */
+    PWREN    = 0x4,     /** Power-enable */
+    CLKDIV   = 0x8,     /** Clock divider */
+    CLKSRC   = 0xC,     /** Clock source */
+    CLKENA   = 0x10,    /** Clock enable */
+    TMOUT    = 0x14,    /** Timeout */
+    CTYPE    = 0x18,    /** Card type */
+    BLKSIZ   = 0x1C,    /** Block Size */
+    BYTCNT   = 0x20,    /** Byte count */
+    INTMSK   = 0x24,    /** Interrupt Mask */
+    CMDARG   = 0x28,    /** Command Argument */
+    CMD      = 0x2C,    /** Command */
+    RESP0    = 0x30,    /** Response 0 */
+    RESP1    = 0x34,    /** Response 1 */
+    RESP2    = 0x38,    /** Response 2 */
+    RESP3    = 0x3C,    /** Response 3 */
+    MINTSTS  = 0x40,    /** Masked interrupt status */
+    RINTSTS  = 0x44,    /** Raw interrupt status */
+    STATUS   = 0x48,    /** Status */
+    FIFOTH   = 0x4C,    /** FIFO threshold */
+    CDETECT  = 0x50,    /** Card detect */
+    WRTPRT   = 0x54,    /** Write protect */
+    GPIO     = 0x58,    /** General Purpose IO */
+    TCBCNT   = 0x5C,    /** Transferred CIU byte count */
+    TBBCNT   = 0x60,    /** Transferred host/DMA to/from byte count */
+    DEBNCE   = 0x64,    /** Card detect debounce */
+    USRID    = 0x68,    /** User ID */
+    VERID    = 0x6C,    /** Version ID */
+    HCON     = 0x70,    /** Hardware Configuration */
+    UHSREG   = 0x74,    /** Reserved */
+    BMOD     = 0x80,    /** Bus mode Register */
+    PLDMND   = 0x84,    /** Poll Demand */
+    DBADDR   = 0x88,    /** Descriptor Base Address */
+    IDSTS    = 0x8C,    /** Internal DMAC Status */
+    IDINTEN  = 0x90,    /** Internal DMAC Interrupt Enable */
+    DSCADDR  = 0x94,    /** Current Host Descriptor Address */
+    BUFADDR  = 0x98,    /** Current Host Buffer Address */
+    FIFODAT  = 0x200,   /** FIFO data read write */
 };
 
 /* Control register definitions */
-#define CTRL_RESET	          0x00000001
+#define CTRL_RESET            0x00000001
 #define FIFO_RESET              0x00000002
-#define DMA_RESET	          0x00000004
-#define INT_ENABLE	          0x00000010
-#define READ_WAIT	          0x00000040
-#define CTRL_USE_IDMAC	   0x02000000
+#define DMA_RESET             0x00000004
+#define INT_ENABLE            0x00000010
+#define READ_WAIT             0x00000040
+#define CTRL_USE_IDMAC     0x02000000
 
 /* Interrupt mask defines */
 #define INTMSK_CDETECT        0x00000001
@@ -102,11 +102,11 @@ enum {
 #define INTMASK_ERROR        (INTMSK_RESP_ERR|INTMSK_RCRC|INTMSK_DCRC|INTMSK_RTO|INTMSK_DTO|INTMSK_HTO|INTMSK_FRUN|INTMSK_HLE|INTMSK_SBE|INTMSK_EBE)
 
 /*BMOD register define */
-#define  BMOD_SWR 	  	   0x00000001
-#define  BMOD_DE 		   0x00000080
+#define  BMOD_SWR          0x00000001
+#define  BMOD_DE           0x00000080
 
 /* for STATUS register */
-#define GET_FIFO_COUNT(x)           	(((x)&0x3ffe0000)>>17)
+#define GET_FIFO_COUNT(x)               (((x)&0x3ffe0000)>>17)
 #define GET_FIFO_DEPTH(x)       ((((x)&0x0FFF0000)>>16)+1)
 
 /* for IDMA intr register */
@@ -122,62 +122,62 @@ enum {
 
 /* Define Card status bits (R1 response) */
 #define R1CS_ADDRESS_OUT_OF_RANGE       0x80000000
-#define R1CS_ADDRESS_MISALIGN		    0x40000000
-#define R1CS_BLOCK_LEN_ERR       		0x20000000
-#define R1CS_ERASE_SEQ_ERR	           	0x10000000
-#define R1CS_ERASE_PARAM	            0x08000000
-#define R1CS_WP_VIOLATION		        0x04000000
-#define R1CS_CARD_IS_LOCKED	            0x02000000
-#define R1CS_LCK_UNLCK_FAILED		    0x01000000
-#define R1CS_COM_CRC_ERROR		        0x00800000
-#define R1CS_ILLEGAL_COMMAND		    0x00400000
-#define R1CS_CARD_ECC_FAILED		    0x00200000
-#define R1CS_CC_ERROR		        	0x00100000
-#define R1CS_ERROR		            	0x00080000
-#define R1CS_UNDERRUN		        	0x00040000
-#define R1CS_OVERRUN		        	0x00020000
-#define R1CS_CSD_OVERWRITE	        	0x00010000
-#define R1CS_WP_ERASE_SKIP	        	0x00008000
-#define R1CS_RESERVED_0	        		0x00004000
-#define R1CS_ERASE_RESET        		0x00002000
-#define R1CS_CURRENT_STATE_MASK    		0x00001e00
-#define R1CS_READY_FOR_DATA	        	0x00000100
-#define R1CS_SWITCH_ERROR        		0x00000080
-#define R1CS_RESERVED_1		        	0x00000040
-#define R1CS_APP_CMD		        	0x00000020
-#define R1CS_RESERVED_2		        	0x00000010
-#define R1CS_APP_SPECIFIC_MASK	    	0x0000000c
-#define R1CS_MANUFAC_TEST_MASK    		0x00000003
-#define R1CS_ERROR_OCCURED_MAP	    	0xfdffa080
-#define R1CS_CURRENT_STATE(x)	    	(((x)&R1CS_CURRENT_STATE_MASK)>>9)
+#define R1CS_ADDRESS_MISALIGN           0x40000000
+#define R1CS_BLOCK_LEN_ERR              0x20000000
+#define R1CS_ERASE_SEQ_ERR              0x10000000
+#define R1CS_ERASE_PARAM                0x08000000
+#define R1CS_WP_VIOLATION               0x04000000
+#define R1CS_CARD_IS_LOCKED             0x02000000
+#define R1CS_LCK_UNLCK_FAILED           0x01000000
+#define R1CS_COM_CRC_ERROR              0x00800000
+#define R1CS_ILLEGAL_COMMAND            0x00400000
+#define R1CS_CARD_ECC_FAILED            0x00200000
+#define R1CS_CC_ERROR                   0x00100000
+#define R1CS_ERROR                      0x00080000
+#define R1CS_UNDERRUN                   0x00040000
+#define R1CS_OVERRUN                    0x00020000
+#define R1CS_CSD_OVERWRITE              0x00010000
+#define R1CS_WP_ERASE_SKIP              0x00008000
+#define R1CS_RESERVED_0                 0x00004000
+#define R1CS_ERASE_RESET                0x00002000
+#define R1CS_CURRENT_STATE_MASK         0x00001e00
+#define R1CS_READY_FOR_DATA             0x00000100
+#define R1CS_SWITCH_ERROR               0x00000080
+#define R1CS_RESERVED_1                 0x00000040
+#define R1CS_APP_CMD                    0x00000020
+#define R1CS_RESERVED_2                 0x00000010
+#define R1CS_APP_SPECIFIC_MASK          0x0000000c
+#define R1CS_MANUFAC_TEST_MASK          0x00000003
+#define R1CS_ERROR_OCCURED_MAP          0xfdffa080
+#define R1CS_CURRENT_STATE(x)           (((x)&R1CS_CURRENT_STATE_MASK)>>9)
 
 /* R5 response */
-#define R5_IO_CRC_ERR	  0x00008000
-#define R5_IO_BAD_CMD	  0x00004000
-#define R5_IO_GEN_ERR	  0x00000800
-#define R5_IO_FUNC_ERR	  0x00000200
+#define R5_IO_CRC_ERR     0x00008000
+#define R5_IO_BAD_CMD     0x00004000
+#define R5_IO_GEN_ERR     0x00000800
+#define R5_IO_FUNC_ERR    0x00000200
 #define R5_IO_OUT_RANGE 0x00000100
-#define R5_IO_ERR_BITS	  0x0000cb00
+#define R5_IO_ERR_BITS    0x0000cb00
 
 enum {
-	NONE_TYPE = 0,
-	SD_TYPE,
-	SD_2_0_TYPE,
-	SDIO_TYPE,
+    NONE_TYPE = 0,
+    SD_TYPE,
+    SD_2_0_TYPE,
+    SDIO_TYPE,
 };
 
 enum {
-	CARD_STATE_EMPTY = -1,
-	CARD_STATE_IDLE = 0,
-	CARD_STATE_READY = 1,
-	CARD_STATE_IDENT = 2,
-	CARD_STATE_STBY = 3,
-	CARD_STATE_TRAN = 4,
-	CARD_STATE_DATA = 5,
-	CARD_STATE_RCV = 6,
-	CARD_STATE_PRG = 7,
-	CARD_STATE_DIS = 8,
-	CARD_STATE_INA = 9
+    CARD_STATE_EMPTY = -1,
+    CARD_STATE_IDLE = 0,
+    CARD_STATE_READY = 1,
+    CARD_STATE_IDENT = 2,
+    CARD_STATE_STBY = 3,
+    CARD_STATE_TRAN = 4,
+    CARD_STATE_DATA = 5,
+    CARD_STATE_RCV = 6,
+    CARD_STATE_PRG = 7,
+    CARD_STATE_DIS = 8,
+    CARD_STATE_INA = 9
 };
 
 enum DmaDescriptorDES1    // Buffer's size field of Descriptor
@@ -204,28 +204,28 @@ enum DmaDescriptorDES0    // Control and status word of DMA descriptor DES0
 };
 
 typedef struct DmaDescStruct {
-		unsigned int desc0;   	 /* control and status information of descriptor */
-		unsigned int desc1;   	 /* buffer sizes                                 */
-		unsigned int desc2;   	 /* physical address of the buffer 1             */
-		unsigned int desc3;    	 /* physical address of the buffer 2             */
+        unsigned int desc0;      /* control and status information of descriptor */
+        unsigned int desc1;      /* buffer sizes                                 */
+        unsigned int desc2;      /* physical address of the buffer 1             */
+        unsigned int desc3;      /* physical address of the buffer 2             */
 }DmaDesc;
 
 typedef struct {
-	unsigned int wkmod;
-	volatile DmaDesc *pDmaDesc;
-	unsigned int idma_support;
-	unsigned int rca;
-	unsigned int ip_base;
-	unsigned int card_type;
-	unsigned int fifo_depth;
-	unsigned int fifo_threth;
-	unsigned int sectors;
-	unsigned int scr[2];
-	unsigned int csd[4];
-	unsigned int idsts;
-	rt_sem_t sem;
-	rt_sem_t mutex;
-	void (*cb)(void);
+    unsigned int wkmod;
+    volatile DmaDesc *pDmaDesc;
+    unsigned int idma_support;
+    unsigned int rca;
+    unsigned int ip_base;
+    unsigned int card_type;
+    unsigned int fifo_depth;
+    unsigned int fifo_threth;
+    unsigned int sectors;
+    unsigned int scr[2];
+    unsigned int csd[4];
+    unsigned int idsts;
+    rt_sem_t sem;
+    rt_sem_t mutex;
+    void (*cb)(void);
 } sdc_t;
 
 #define ONE_BIT_MODE     (0)
@@ -244,55 +244,55 @@ typedef struct {
 
 
 enum {
-	ERRNOERROR = 0,
-		
-	// for raw interrupt status error
-	ERRRESPRECEP,    // 1
-	ERRRESPCRC,
-	ERRDCRC,
-	ERRRESPTIMEOUT,
-	ERRDRTIMEOUT,
-	ERRUNDERWRITE,
-	ERROVERREAD,
-	ERRHLE,
-	ERRSTARTBIT,
-	ERRENDBITERR,  // 10
+    ERRNOERROR = 0,
 
-	// for R1 response
-	ERRADDRESSRANGE,  // 11
-	ERRADDRESSMISALIGN,
-	ERRBLOCKLEN,
-	ERRERASESEQERR,
-	ERRERASEPARAM,
-	ERRPROT,
-	ERRCARDLOCKED,
-	ERRCRC,
-	ERRILLEGALCOMMAND,
-	ERRECCFAILED,
-	ERRCCERR,
-	ERRUNKNOWN,
-	ERRUNDERRUN,
-	ERROVERRUN,
-	ERRCSDOVERWRITE,
-	ERRERASERESET,
-	ERRFSMSTATE,  // 27
+    // for raw interrupt status error
+    ERRRESPRECEP,    // 1
+    ERRRESPCRC,
+    ERRDCRC,
+    ERRRESPTIMEOUT,
+    ERRDRTIMEOUT,
+    ERRUNDERWRITE,
+    ERROVERREAD,
+    ERRHLE,
+    ERRSTARTBIT,
+    ERRENDBITERR,  // 10
 
-	// for R5 response
-	ERRBADFUNC,   // 28
+    // for R1 response
+    ERRADDRESSRANGE,  // 11
+    ERRADDRESSMISALIGN,
+    ERRBLOCKLEN,
+    ERRERASESEQERR,
+    ERRERASEPARAM,
+    ERRPROT,
+    ERRCARDLOCKED,
+    ERRCRC,
+    ERRILLEGALCOMMAND,
+    ERRECCFAILED,
+    ERRCCERR,
+    ERRUNKNOWN,
+    ERRUNDERRUN,
+    ERROVERRUN,
+    ERRCSDOVERWRITE,
+    ERRERASERESET,
+    ERRFSMSTATE,  // 27
 
-	// others
-	ERRCARDNOTCONN,  // 29
-	ERRCARDWPROTECT,
-	ERRCMDRETRIESOVER,
-	ERRNOTSUPPORTED,
-	ERRHARDWARE,
-	ERRDATANOTREADY,
-	ERRCARDINTERNAL,
-	ERRACMD41TIMEOUT,
-	ERRIDMA,
-	ERRNORES,
+    // for R5 response
+    ERRBADFUNC,   // 28
 
-	ERRNOTEQUAL,
+    // others
+    ERRCARDNOTCONN,  // 29
+    ERRCARDWPROTECT,
+    ERRCMDRETRIESOVER,
+    ERRNOTSUPPORTED,
+    ERRHARDWARE,
+    ERRDATANOTREADY,
+    ERRCARDINTERNAL,
+    ERRACMD41TIMEOUT,
+    ERRIDMA,
+    ERRNORES,
+
+    ERRNOTEQUAL,
 };
 
 #ifdef __ASIC_BRANCH__
@@ -352,5 +352,5 @@ extern int sdio_drv_creg_write(HSDC handle, int addr, int fn, unsigned char data
 
 extern void inv_dcache_range(unsigned long start, unsigned long len);
 extern void flush_dcache_range(unsigned long start, unsigned long len);
- 
+
 #endif //__sdcard_h__
diff --git a/bsp/fh8620/libraries/inc/fh_spi.h b/bsp/fh8620/libraries/inc/fh_spi.h
index d81c2428bc..689a85b3f4 100644
--- a/bsp/fh8620/libraries/inc/fh_spi.h
+++ b/bsp/fh8620/libraries/inc/fh_spi.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #ifndef FH_SPI_H_
 #define FH_SPI_H_
 
@@ -97,8 +97,8 @@
 #define SPI_STATUS_BUSY             (1)
 
 
-#define SPI_TX_DMA			(1<<1)
-#define SPI_RX_DMA			(1<<0)
+#define SPI_TX_DMA          (1<<1)
+#define SPI_RX_DMA          (1<<0)
 
 
 struct spi_config
diff --git a/bsp/fh8620/libraries/inc/fh_timer.h b/bsp/fh8620/libraries/inc/fh_timer.h
index 715a73b252..9f88bff22e 100644
--- a/bsp/fh8620/libraries/inc/fh_timer.h
+++ b/bsp/fh8620/libraries/inc/fh_timer.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
@@ -29,7 +29,7 @@
 
  /****************************************************************************
  * #include section
- *	add #include here if any
+ *  add #include here if any
  ***************************************************************************/
 #include "fh_def.h"
 
@@ -38,7 +38,7 @@
 
  /****************************************************************************
  * #define section
- *	add constant #define here if any
+ *  add constant #define here if any
  ***************************************************************************/
 #define TIMER_CTRL_ENABLE   (1u << 0)
 #define TIMER_CTRL_MODE     (1u << 1)
@@ -49,19 +49,19 @@
 
  /****************************************************************************
  * ADT section
- *	add Abstract Data Type definition here
+ *  add Abstract Data Type definition here
  ***************************************************************************/
 typedef struct {
-	RwReg TIMER_LOAD_COUNT;
-	RwReg TIMER_CURRENT_VALUE;
-	RwReg TIMER_CTRL_REG;
-	RwReg TIMER_EOI;
-	RwReg TIMER_INT_STATUS;
+    RwReg TIMER_LOAD_COUNT;
+    RwReg TIMER_CURRENT_VALUE;
+    RwReg TIMER_CTRL_REG;
+    RwReg TIMER_EOI;
+    RwReg TIMER_INT_STATUS;
 }timer;
 
  enum timer_mode {
- 	TIMER_MODE_PERIODIC = 0,
- 	TIMER_MODE_ONESHOT = 1,
+    TIMER_MODE_PERIODIC = 0,
+    TIMER_MODE_ONESHOT = 1,
  };
 
 
@@ -73,7 +73,7 @@ typedef struct {
 
 /****************************************************************************
 *  section
-*	add function prototype here if any
+*   add function prototype here if any
 ***************************************************************************/
 
 
diff --git a/bsp/fh8620/libraries/inc/fh_uart.h b/bsp/fh8620/libraries/inc/fh_uart.h
index 87da9ee2f7..34d2a9bb9a 100644
--- a/bsp/fh8620/libraries/inc/fh_uart.h
+++ b/bsp/fh8620/libraries/inc/fh_uart.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
@@ -29,13 +29,13 @@
 
  /****************************************************************************
  * #include section
- *	add #include here if any
+ *  add #include here if any
  ***************************************************************************/
 #include "fh_def.h"
 
  /****************************************************************************
  * #define section
- *	add constant #define here if any
+ *  add constant #define here if any
  ***************************************************************************/
 
 #define UART_RBR RBRTHRDLL
@@ -120,53 +120,53 @@
 #define UART_IIR_FIFOSE  (0x03 << 6)
 
 //uart baudrate cofig
-//#define 	UART_CLOCK_FREQ   	(27000000)   //27MHZ
+//#define   UART_CLOCK_FREQ     (27000000)   //27MHZ
 //
-//#define DIV(n)	(((UART_CLOCK_FREQ/(n))+8)/16)
+//#define DIV(n)    (((UART_CLOCK_FREQ/(n))+8)/16)
 
 
  /****************************************************************************
  * ADT section
- *	add Abstract Data Type definition here
+ *  add Abstract Data Type definition here
  ***************************************************************************/
 
 
 
 
 typedef struct {
-	RwReg RBRTHRDLL; /* UART_RBR, UART_THR, UART_DLL */
-	RwReg DLHIER;    /* UART_DLH, UART_IER */
-	RwReg IIRFCR;    /* UART_IIR, UART_FCR */
-	RwReg UART_LCR; /*(0x000c) */
-	RwReg UART_MCR; /*(0x0010) */
-	RwReg UART_LSR; /*(0x0014) */
-	RwReg UART_MSR; /*(0x0018) */
-	RwReg UART_SCR; /*(0x001c) */
-	RwReg reserved[20];
-	RwReg UART_FAR; /* (0x0070) */
-	RwReg UART_TFR; /* (0x0074) */
-	RwReg UART_RFW; /* (0x0078) */
-	RwReg UART_USR; /* (0x007c) */
-	RwReg UART_TFL; /* (0x0080) */
-	RwReg UART_RFL; /* (0x0084) */
-	RwReg UART_SRR; /* (0x0088) */
-	RwReg reserved1[3];
-	RwReg UART_SFE;  /* (0x0098) */
-	RwReg UART_SRT;  /* (0x009c) */
-	RwReg UART_STET; /* (0x00a0) */
-	RwReg UART_HTX;  /* (0x00a4) */
-	RwReg UART_DMASA; /* (0x00a8) */
-	RwReg reserved2[18];
-	RwReg UART_CPR;  /* (0x00f4) */
-	RwReg UART_UCV;  /* (0x00f8) */
-	RwReg UART_CTR;  /* (0x00fc) */
+    RwReg RBRTHRDLL; /* UART_RBR, UART_THR, UART_DLL */
+    RwReg DLHIER;    /* UART_DLH, UART_IER */
+    RwReg IIRFCR;    /* UART_IIR, UART_FCR */
+    RwReg UART_LCR; /*(0x000c) */
+    RwReg UART_MCR; /*(0x0010) */
+    RwReg UART_LSR; /*(0x0014) */
+    RwReg UART_MSR; /*(0x0018) */
+    RwReg UART_SCR; /*(0x001c) */
+    RwReg reserved[20];
+    RwReg UART_FAR; /* (0x0070) */
+    RwReg UART_TFR; /* (0x0074) */
+    RwReg UART_RFW; /* (0x0078) */
+    RwReg UART_USR; /* (0x007c) */
+    RwReg UART_TFL; /* (0x0080) */
+    RwReg UART_RFL; /* (0x0084) */
+    RwReg UART_SRR; /* (0x0088) */
+    RwReg reserved1[3];
+    RwReg UART_SFE;  /* (0x0098) */
+    RwReg UART_SRT;  /* (0x009c) */
+    RwReg UART_STET; /* (0x00a0) */
+    RwReg UART_HTX;  /* (0x00a4) */
+    RwReg UART_DMASA; /* (0x00a8) */
+    RwReg reserved2[18];
+    RwReg UART_CPR;  /* (0x00f4) */
+    RwReg UART_UCV;  /* (0x00f8) */
+    RwReg UART_CTR;  /* (0x00fc) */
 }uart;
 
 
 
 struct fh_uart {
-	uart *uart_port;
-	int irq;
+    uart *uart_port;
+    int irq;
 };
 
 
@@ -174,34 +174,34 @@ struct fh_uart {
 
 
 enum data_bits {
-	UART_DATA_BIT5 = 0,
-	UART_DATA_BIT6 = 1,
-	UART_DATA_BIT7 = 2,
-	UART_DATA_BIT8 = 3
+    UART_DATA_BIT5 = 0,
+    UART_DATA_BIT6 = 1,
+    UART_DATA_BIT7 = 2,
+    UART_DATA_BIT8 = 3
 };
 
 enum stop_bits {
-	UART_STOP_BIT1   = 0,
-	UART_STOP_BIT1_5 = 1,
-	UART_STOP_BIT2   = 2
+    UART_STOP_BIT1   = 0,
+    UART_STOP_BIT1_5 = 1,
+    UART_STOP_BIT2   = 2
 };
 
 enum parity {
-	UART_PARITY_NONE = 0,
-	UART_PARITY_EVEN = 1,
-	UART_PARITY_ODD  = 2,
-	UART_PARITY_ST   = 3 /* Stick Parity */
+    UART_PARITY_NONE = 0,
+    UART_PARITY_EVEN = 1,
+    UART_PARITY_ODD  = 2,
+    UART_PARITY_ST   = 3 /* Stick Parity */
 };
 
 
-#define 	UART_CLOCK_FREQ   	(30000000)   //30MHZ
+#define     UART_CLOCK_FREQ     (30000000)   //30MHZ
 typedef enum enum_uart_baudrate{
-	BAUDRATE_9600 	= (((UART_CLOCK_FREQ/9600)+8)/16),
-	BAUDRATE_19200 	= (((UART_CLOCK_FREQ/19200)+8)/16),
-	BAUDRATE_38400  = (((UART_CLOCK_FREQ/38400)+8)/16),
-	BAUDRATE_57600  = (((UART_CLOCK_FREQ/57600)+8)/16),
-	BAUDRATE_115200 = (((UART_CLOCK_FREQ/115200)+8)/16),
-	BAUDRATE_194000 = (((UART_CLOCK_FREQ/194000)+8)/16),
+    BAUDRATE_9600   = (((UART_CLOCK_FREQ/9600)+8)/16),
+    BAUDRATE_19200  = (((UART_CLOCK_FREQ/19200)+8)/16),
+    BAUDRATE_38400  = (((UART_CLOCK_FREQ/38400)+8)/16),
+    BAUDRATE_57600  = (((UART_CLOCK_FREQ/57600)+8)/16),
+    BAUDRATE_115200 = (((UART_CLOCK_FREQ/115200)+8)/16),
+    BAUDRATE_194000 = (((UART_CLOCK_FREQ/194000)+8)/16),
 }uart_baudrate_e;
 
 /****************************************************************************
@@ -213,8 +213,8 @@ extern int uart_init(uart *port);
 extern UINT32 uart_get_status(uart *port);
 
 extern void uart_configure(uart *port, enum data_bits data_bit,
-					enum stop_bits stop_bit, enum parity parity,
-					UINT32 buard_rate, UINT32 uart_clk);
+                    enum stop_bits stop_bit, enum parity parity,
+                    UINT32 buard_rate, UINT32 uart_clk);
 
 
 extern int uart_enable_irq(uart *port, UINT32 mode);
@@ -235,7 +235,7 @@ extern void uart_set_fifo_mode(uart *port, UINT32 fifo_mode);
 
 /****************************************************************************
 *  section
-*	add function prototype here if any
+*   add function prototype here if any
 ***************************************************************************/
 
 
diff --git a/bsp/fh8620/libraries/inc/fh_wdt.h b/bsp/fh8620/libraries/inc/fh_wdt.h
index a90331dbd5..7804a3a536 100644
--- a/bsp/fh8620/libraries/inc/fh_wdt.h
+++ b/bsp/fh8620/libraries/inc/fh_wdt.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #ifndef FH_WDT_H_
 #define FH_WDT_H_
 
diff --git a/bsp/fh8620/platform/board.h b/bsp/fh8620/platform/board.h
index 46b276b052..ac8708ec9e 100644
--- a/bsp/fh8620/platform/board.h
+++ b/bsp/fh8620/platform/board.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #ifndef __BOARD_H__
 #define __BOARD_H__
 #include "platform_def.h"
diff --git a/bsp/fh8620/platform/board_info.h b/bsp/fh8620/platform/board_info.h
index 71f8d3c19e..d86907621f 100644
--- a/bsp/fh8620/platform/board_info.h
+++ b/bsp/fh8620/platform/board_info.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #ifndef __BOARD_INFO_H__
 #define __BOARD_INFO_H__
 
@@ -33,32 +33,32 @@ extern "C" {
 
 /****************************************************************************
  * #include section
- *	add #include here if any
+ *  add #include here if any
  ***************************************************************************/
 
 /****************************************************************************
  * #define section
- *	add constant #define here if any
+ *  add constant #define here if any
  ***************************************************************************/
 
 /****************************************************************************
  * ADT section
- *	add Abstract Data Type definition here
+ *  add Abstract Data Type definition here
  ***************************************************************************/
 
 typedef int (*probe_p)(void *);
 typedef int (*exit_p)(void *);
 
 struct fh_board_ops {
-	//void *ops_data;
-	probe_p probe;
-	probe_p exit;
+    //void *ops_data;
+    probe_p probe;
+    probe_p exit;
 };
 
 struct fh_board_info {
-	char *name;
-	void *data;
-	struct fh_board_ops *ops;
+    char *name;
+    void *data;
+    struct fh_board_ops *ops;
 
 };
 
@@ -73,7 +73,7 @@ void fh_print_all_board_info(void);
 void fh_free_all_info(void);
 /****************************************************************************
  *  section
- *	add function prototype here if any
+ *  add function prototype here if any
  ***************************************************************************/
 
 #ifdef __cplusplus
diff --git a/bsp/fh8620/platform/common/board_info.c b/bsp/fh8620/platform/common/board_info.c
index aa56cbac62..6bb95bfaa9 100644
--- a/bsp/fh8620/platform/common/board_info.c
+++ b/bsp/fh8620/platform/common/board_info.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 /*****************************************************************************
  *  Include Section
  *  add all #include here
@@ -36,27 +36,27 @@
  * add all #define here
  *****************************************************************************/
 struct fh_board_info_list_node {
-	struct fh_board_info obj;
-	rt_list_t list;
+    struct fh_board_info obj;
+    rt_list_t list;
 };
 
-#define CHECK_TEST_LIST_EMPTY		\
-		if(rt_list_isempty(&board_info_head.list)) \
-		rt_kprintf("board info is null...please register first..\n")
+#define CHECK_TEST_LIST_EMPTY       \
+        if(rt_list_isempty(&board_info_head.list)) \
+        rt_kprintf("board info is null...please register first..\n")
 
 /****************************************************************************
  * ADT section
  *  add definition of user defined Data Type that only be used in this file  here
  ***************************************************************************/
 
-#define list_for_each_entry_safe(pos, n, head, member)			\
-	for (pos = rt_list_entry((head)->next, typeof(*pos), member),	\
-		n = rt_list_entry(pos->member.next, typeof(*pos), member);	\
-	     &pos->member != (head); 					\
-	     pos = n, n = rt_list_entry(n->member.next, typeof(*n), member))
+#define list_for_each_entry_safe(pos, n, head, member)          \
+    for (pos = rt_list_entry((head)->next, typeof(*pos), member),   \
+        n = rt_list_entry(pos->member.next, typeof(*pos), member);  \
+         &pos->member != (head);                    \
+         pos = n, n = rt_list_entry(n->member.next, typeof(*n), member))
 
-#define PARA_ERROR			(-1)
-#define PROBE_FUNC_MISS		(-2)
+#define PARA_ERROR          (-1)
+#define PROBE_FUNC_MISS     (-2)
 
 /******************************************************************************
  * Function prototype section
@@ -104,45 +104,45 @@ static struct fh_board_info_list_node board_info_head;
 
 int fh_board_info_init(void) {
 
-	memset(&board_info_head, 0x0, sizeof(struct fh_board_info_list_node));
-	rt_list_init(&board_info_head.list);
-	board_info_head.obj.name = "NO INFO";
-	return 0;
+    memset(&board_info_head, 0x0, sizeof(struct fh_board_info_list_node));
+    rt_list_init(&board_info_head.list);
+    board_info_head.obj.name = "NO INFO";
+    return 0;
 }
 
 void fh_free_all_info(void) {
-	rt_list_t *p_list;
-	struct fh_board_info_list_node *info_node;
-	struct fh_board_info_list_node *_info_node;
-	p_list = &board_info_head.list;
+    rt_list_t *p_list;
+    struct fh_board_info_list_node *info_node;
+    struct fh_board_info_list_node *_info_node;
+    p_list = &board_info_head.list;
 
-	CHECK_TEST_LIST_EMPTY;
+    CHECK_TEST_LIST_EMPTY;
 
-	list_for_each_entry_safe(info_node, _info_node, p_list, list)
-	{
+    list_for_each_entry_safe(info_node, _info_node, p_list, list)
+    {
 
-		if (info_node->obj.ops->exit) {
-			info_node->obj.ops->exit(info_node->obj.data);
-		}
-		rt_kprintf("soc free list name:(%s)\n", info_node->obj.name);
-		rt_free(info_node);
-	}
-	fh_board_info_init();
+        if (info_node->obj.ops->exit) {
+            info_node->obj.ops->exit(info_node->obj.data);
+        }
+        rt_kprintf("soc free list name:(%s)\n", info_node->obj.name);
+        rt_free(info_node);
+    }
+    fh_board_info_init();
 }
 
 void fh_print_all_board_info(void) {
-	rt_list_t *p_list;
+    rt_list_t *p_list;
 
-	struct fh_board_info_list_node *info_node;
-	struct fh_board_info_list_node *_info_node;
-	p_list = &board_info_head.list;
+    struct fh_board_info_list_node *info_node;
+    struct fh_board_info_list_node *_info_node;
+    p_list = &board_info_head.list;
 
-	CHECK_TEST_LIST_EMPTY;
+    CHECK_TEST_LIST_EMPTY;
 
-	list_for_each_entry_safe(info_node, _info_node, p_list, list)
-	{
-		rt_kprintf("%s\n", info_node->obj.name);
-	}
+    list_for_each_entry_safe(info_node, _info_node, p_list, list)
+    {
+        rt_kprintf("%s\n", info_node->obj.name);
+    }
 }
 
 /*****************************************************************************
@@ -157,94 +157,94 @@ void fh_print_all_board_info(void) {
 //register the platform info such as base add,isr no..
 //caution:do not free the name and data because of here not copy
 struct fh_board_info *fh_board_info_register(char *info_name, void *data) {
-	rt_list_t *p_list;
-	struct fh_board_info_list_node *new_node;
-	struct fh_board_info_list_node *info_node;
-	struct fh_board_info_list_node *_info_node;
-	p_list = &board_info_head.list;
+    rt_list_t *p_list;
+    struct fh_board_info_list_node *new_node;
+    struct fh_board_info_list_node *info_node;
+    struct fh_board_info_list_node *_info_node;
+    p_list = &board_info_head.list;
 
-	if (RT_NULL == info_name || RT_NULL == data) {
-		rt_kprintf("info name or info data is NULL!\n");
-		return RT_NULL;
-	}
+    if (RT_NULL == info_name || RT_NULL == data) {
+        rt_kprintf("info name or info data is NULL!\n");
+        return RT_NULL;
+    }
 
-	//check if the func is already in the test list....
+    //check if the func is already in the test list....
 #if(0)
-	list_for_each_entry_safe(info_node, _info_node, p_list, list) {
-		if (!memcmp(info_node->obj.name, info_name, strlen(info_name))) {
-			rt_kprintf("info_name(%s) is already registered\n", info_name);
-			return RT_NULL;
-		}
-	}
+    list_for_each_entry_safe(info_node, _info_node, p_list, list) {
+        if (!memcmp(info_node->obj.name, info_name, strlen(info_name))) {
+            rt_kprintf("info_name(%s) is already registered\n", info_name);
+            return RT_NULL;
+        }
+    }
 #endif
 
-	new_node = (struct fh_board_info_list_node *) rt_malloc(
-			sizeof(struct fh_board_info_list_node));
-	if (!new_node) {
-		rt_kprintf("malloc new_list_node failed~\n");
-		return RT_NULL;
-	}
+    new_node = (struct fh_board_info_list_node *) rt_malloc(
+            sizeof(struct fh_board_info_list_node));
+    if (!new_node) {
+        rt_kprintf("malloc new_list_node failed~\n");
+        return RT_NULL;
+    }
 
-	new_node->obj.name = info_name;
-	new_node->obj.data = data;
-	//here insert "before" and test is "after" will make the list like a fifo...
-	rt_list_insert_before(&board_info_head.list, &new_node->list);
-	return &new_node->obj;
+    new_node->obj.name = info_name;
+    new_node->obj.data = data;
+    //here insert "before" and test is "after" will make the list like a fifo...
+    rt_list_insert_before(&board_info_head.list, &new_node->list);
+    return &new_node->obj;
 }
 
 //back the platform info
 static void *fh_get_board_info_data(char *info_name) {
 
-	rt_list_t *p_list;
-	struct fh_board_info_list_node *info_node;
-	struct fh_board_info_list_node *_info_node;
-	p_list = &board_info_head.list;
+    rt_list_t *p_list;
+    struct fh_board_info_list_node *info_node;
+    struct fh_board_info_list_node *_info_node;
+    p_list = &board_info_head.list;
 
-	//check info name
-	if (RT_NULL == info_name) {
-		rt_kprintf("info name is NULL!\n");
-		return RT_NULL;
-	}
+    //check info name
+    if (RT_NULL == info_name) {
+        rt_kprintf("info name is NULL!\n");
+        return RT_NULL;
+    }
 
-	CHECK_TEST_LIST_EMPTY;
+    CHECK_TEST_LIST_EMPTY;
 
-	list_for_each_entry_safe(info_node, _info_node, p_list, list)
-	{
-		if (!strcmp(info_node->obj.name, info_name)) {
-			return info_node->obj.data;
-		}
-	}
+    list_for_each_entry_safe(info_node, _info_node, p_list, list)
+    {
+        if (!strcmp(info_node->obj.name, info_name)) {
+            return info_node->obj.data;
+        }
+    }
 
-	rt_kprintf("Can't find the board info name:%s\n", info_name);
+    rt_kprintf("Can't find the board info name:%s\n", info_name);
 }
 
 int fh_board_driver_register(char *info_name, struct fh_board_ops *ops) {
 
-	rt_list_t *p_list;
-	struct fh_board_info_list_node *new_node;
-	struct fh_board_info_list_node *info_node;
-	struct fh_board_info_list_node *_info_node;
-	p_list = &board_info_head.list;
+    rt_list_t *p_list;
+    struct fh_board_info_list_node *new_node;
+    struct fh_board_info_list_node *info_node;
+    struct fh_board_info_list_node *_info_node;
+    p_list = &board_info_head.list;
 
-	if (RT_NULL == info_name || RT_NULL == ops) {
-		rt_kprintf("info name or ops func is NULL!\n");
-		return PARA_ERROR;
-	}
+    if (RT_NULL == info_name || RT_NULL == ops) {
+        rt_kprintf("info name or ops func is NULL!\n");
+        return PARA_ERROR;
+    }
 
-	list_for_each_entry_safe(info_node, _info_node, p_list, list)
-	{
-		if (!strcmp(info_node->obj.name, info_name)) {
+    list_for_each_entry_safe(info_node, _info_node, p_list, list)
+    {
+        if (!strcmp(info_node->obj.name, info_name)) {
 
-			info_node->obj.ops = ops;
-			if (info_node->obj.ops->probe) {
-				info_node->obj.ops->probe(info_node->obj.data);
-			}
+            info_node->obj.ops = ops;
+            if (info_node->obj.ops->probe) {
+                info_node->obj.ops->probe(info_node->obj.data);
+            }
 
-			//return info_node->obj.data;
-		}
-	}
+            //return info_node->obj.data;
+        }
+    }
 
-	//rt_kprintf("Can't find the board info name:%s\n",info_name);
+    //rt_kprintf("Can't find the board info name:%s\n",info_name);
 
-	return 0;
+    return 0;
 }
diff --git a/bsp/fh8620/platform/common/chkenv.c b/bsp/fh8620/platform/common/chkenv.c
index 563b5bb55a..e2d8f18b22 100644
--- a/bsp/fh8620/platform/common/chkenv.c
+++ b/bsp/fh8620/platform/common/chkenv.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 /*****************************************************************************
  *  Include Section
  *  add all #include here
@@ -47,11 +47,11 @@
  *
  *
  **************************/
-#if RT_NAME_MAX	!= 16
+#if RT_NAME_MAX != 16
 #error "define RT_NAME_MAX 16"
 #endif
 
-#if RT_TICK_PER_SECOND	!= 100
+#if RT_TICK_PER_SECOND  != 100
 #warning "RT_TICK_PER_SECOND = 100"
 #endif
 
diff --git a/bsp/fh8620/platform/fh8620/arch.h b/bsp/fh8620/platform/fh8620/arch.h
index df0e7f1965..306c1239e8 100644
--- a/bsp/fh8620/platform/fh8620/arch.h
+++ b/bsp/fh8620/platform/fh8620/arch.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #ifndef ARCH_H_
 #define ARCH_H_
 
@@ -31,37 +31,37 @@
 /*****************************/
 /* BSP CONTROLLER BASE       */
 /*****************************/
-#define		INTC_REG_BASE		(0xE0200000)
-#define		SDC0_REG_BASE		(0xE2000000)
-#define		SDC1_REG_BASE		(0xE2100000)
-#define		TVE_REG_BASE		(0xE8000000)
-#define		VOU_REG_BASE		(0xE8100000)
-#define		AES_REG_BASE		(0xE8200000)
-#define		JPEG_REG_BASE		(0xE8300000)
-#define		ISPB_REG_BASE		(0xEA000000)
-#define		ISPF_REG_BASE		(0xEA100000)
-#define		VPU_REG_BASE		(0xEC000000)
-#define		VCU_REG_BASE		(0xEC100000)
-#define		DDRC_REG_BASE		(0xED000000)
-#define 	DMAC_REG_BASE		(0xEE000000)
-#define 	GMAC_REG_BASE		(0xEF000000)
-#define 	PMU_REG_BASE		(0xF0000000)
-#define 	I2C0_REG_BASE		(0xF0200000)
-#define 	GPIO0_REG_BASE		(0xF0300000)
+#define     INTC_REG_BASE       (0xE0200000)
+#define     SDC0_REG_BASE       (0xE2000000)
+#define     SDC1_REG_BASE       (0xE2100000)
+#define     TVE_REG_BASE        (0xE8000000)
+#define     VOU_REG_BASE        (0xE8100000)
+#define     AES_REG_BASE        (0xE8200000)
+#define     JPEG_REG_BASE       (0xE8300000)
+#define     ISPB_REG_BASE       (0xEA000000)
+#define     ISPF_REG_BASE       (0xEA100000)
+#define     VPU_REG_BASE        (0xEC000000)
+#define     VCU_REG_BASE        (0xEC100000)
+#define     DDRC_REG_BASE       (0xED000000)
+#define     DMAC_REG_BASE       (0xEE000000)
+#define     GMAC_REG_BASE       (0xEF000000)
+#define     PMU_REG_BASE        (0xF0000000)
+#define     I2C0_REG_BASE       (0xF0200000)
+#define     GPIO0_REG_BASE      (0xF0300000)
 #define     GPIO1_REG_BASE      (0xf4000000)
-#define 	PWM_REG_BASE		(0xF0400000)
-#define 	SPI0_REG_BASE		(0xF0500000)
-#define 	SPI1_REG_BASE		(0xF0600000)
-#define		UART0_REG_BASE		(0xF0700000)
-#define		UART1_REG_BASE		(0xF0800000)
-#define		I2S_REG_BASE		(0xF0900000)
-#define		ACODEC_REG_BASE		(0xF0A00000)
-#define		I2C1_REG_BASE		(0xF0B00000)
-#define		TMR_REG_BASE		(0xF0C00000)
-#define		WDT_REG_BASE		(0xF0D00000)
-#define		DPHY_REG_BASE		(0xF1000000)
-#define		MIPIC_REG_BASE		(0xF1100000)
-#define		SADC_REG_BASE		(0xF1200000)
+#define     PWM_REG_BASE        (0xF0400000)
+#define     SPI0_REG_BASE       (0xF0500000)
+#define     SPI1_REG_BASE       (0xF0600000)
+#define     UART0_REG_BASE      (0xF0700000)
+#define     UART1_REG_BASE      (0xF0800000)
+#define     I2S_REG_BASE        (0xF0900000)
+#define     ACODEC_REG_BASE     (0xF0A00000)
+#define     I2C1_REG_BASE       (0xF0B00000)
+#define     TMR_REG_BASE        (0xF0C00000)
+#define     WDT_REG_BASE        (0xF0D00000)
+#define     DPHY_REG_BASE       (0xF1000000)
+#define     MIPIC_REG_BASE      (0xF1100000)
+#define     SADC_REG_BASE       (0xF1200000)
 
 
 
diff --git a/bsp/fh8620/platform/fh8620/iot_cam/board.c b/bsp/fh8620/platform/fh8620/iot_cam/board.c
index 8e45b9be90..a726ce5efe 100644
--- a/bsp/fh8620/platform/fh8620/iot_cam/board.c
+++ b/bsp/fh8620/platform/fh8620/iot_cam/board.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 /*****************************************************************************
  *  Include Section
  *  add all #include here
@@ -67,15 +67,15 @@
 
 
 #ifndef HW_SDCARD_POWER_GPIO
-	#define HW_SDCARD_POWER_GPIO  63   //not used
+    #define HW_SDCARD_POWER_GPIO  63   //not used
 #endif
 /****************************************************************************
  * ADT section
  *  add definition of user defined Data Type that only be used in this file  here
  ***************************************************************************/
 struct st_platform_info {
-	char *name;
-	void *private_data;
+    char *name;
+    void *private_data;
 };
 
 /******************************************************************************
@@ -101,14 +101,14 @@ struct st_platform_info {
 
 void fh_mmc_reset(struct fh_mmc_obj *mmc_obj)
 {
-	rt_uint32_t value;
-	if (mmc_obj->id)
-		fh_pmu_write(REG_PMU_SWRST_AHB_CTRL, 0xfffffffd);
-	else
-		fh_pmu_write(REG_PMU_SWRST_AHB_CTRL, 0xfffffffb);
-	do {
-		fh_pmu_read(REG_PMU_SWRST_AHB_CTRL, &value);
-	} while (value != 0xffffffff);
+    rt_uint32_t value;
+    if (mmc_obj->id)
+        fh_pmu_write(REG_PMU_SWRST_AHB_CTRL, 0xfffffffd);
+    else
+        fh_pmu_write(REG_PMU_SWRST_AHB_CTRL, 0xfffffffb);
+    do {
+        fh_pmu_read(REG_PMU_SWRST_AHB_CTRL, &value);
+    } while (value != 0xffffffff);
 }
 
 static struct fh_mmc_obj mmc0_obj =
@@ -130,8 +130,8 @@ static struct fh_mmc_obj mmc1_obj =
 };
 
 #ifdef RT_USING_SPI
-#define SPI0_CLK_IN					(50000000)
-#define SPI0_MAX_BAUD				(SPI0_CLK_IN/2)
+#define SPI0_CLK_IN                 (50000000)
+#define SPI0_MAX_BAUD               (SPI0_CLK_IN/2)
 
 static struct spi_control_platform_data spi0_platform_data =
 {
@@ -152,8 +152,8 @@ static struct spi_control_platform_data spi0_platform_data =
 };
 
 
-#define SPI1_CLK_IN					(50000000)
-#define SPI1_MAX_BAUD				(SPI1_CLK_IN/2)
+#define SPI1_CLK_IN                 (50000000)
+#define SPI1_MAX_BAUD               (SPI1_CLK_IN/2)
 
 static struct spi_control_platform_data spi1_platform_data =
 {
@@ -217,10 +217,10 @@ static struct fh_wdt_obj wdt_obj =
 #ifdef RT_USING_SADC
 static struct wrap_sadc_obj sadc_obj =
 {
-		.id = 0,
-		.regs = (void *)SADC_REG_BASE,
-		.irq_no = SADC_IRQn,
-		.sample_mode = ISR_MODE,
+        .id = 0,
+        .regs = (void *)SADC_REG_BASE,
+        .irq_no = SADC_IRQn,
+        .sample_mode = ISR_MODE,
 };
 #endif
 
@@ -366,8 +366,8 @@ struct st_platform_info plat_sadc =
 #endif
 
 const static struct st_platform_info *platform_info[] = {
-		&plat_mmc0,
-		//&plat_mmc1,//by PeterJiang, wifi don't use SDIO framework...
+        &plat_mmc0,
+        //&plat_mmc1,//by PeterJiang, wifi don't use SDIO framework...
 #ifdef RT_USING_SPI
         &plat_spi0,
 #endif
@@ -400,168 +400,168 @@ const static struct st_platform_info *platform_info[] = {
 
  void clock_init(void)
  {
- 	//UINT32 reg;
- 	//gate enable, spi0, gmac, uart0, timer0, wdt, pts
+    //UINT32 reg;
+    //gate enable, spi0, gmac, uart0, timer0, wdt, pts
 #ifdef YG_TEK
-	fh_pmu_write_mask(REG_PMU_PAD_MAC_TXER_CFG, 0x100000, 0x100000);
+    fh_pmu_write_mask(REG_PMU_PAD_MAC_TXER_CFG, 0x100000, 0x100000);
 #endif
- 	//SPI0
-	fh_pmu_write_mask(REG_PMU_CLK_DIV3, 0xb, 0xff);
+    //SPI0
+    fh_pmu_write_mask(REG_PMU_CLK_DIV3, 0xb, 0xff);
 
- 	//GMAC
-	fh_pmu_write_mask(REG_PMU_CLK_DIV6, 0x5000000, 0xf000000);
+    //GMAC
+    fh_pmu_write_mask(REG_PMU_CLK_DIV6, 0x5000000, 0xf000000);
 
- 	//UART0
-	fh_pmu_write_mask(REG_PMU_CLK_DIV4, 0x1, 0xf);
+    //UART0
+    fh_pmu_write_mask(REG_PMU_CLK_DIV4, 0x1, 0xf);
 
- 	//TIMER0
-	fh_pmu_write_mask(REG_PMU_CLK_DIV5, 0x1d0000, 0x3f0000);
+    //TIMER0
+    fh_pmu_write_mask(REG_PMU_CLK_DIV5, 0x1d0000, 0x3f0000);
 
- 	//PTS
-	fh_pmu_write_mask(REG_PMU_CLK_DIV2, 0x23, 0x3f);
+    //PTS
+    fh_pmu_write_mask(REG_PMU_CLK_DIV2, 0x23, 0x3f);
 
- 	//WDT
-	//fh_pmu_write_mask(REG_PMU_CLK_DIV5, 0x1d00, 0x3f00);
-	fh_pmu_write_mask(REG_PMU_CLK_DIV5, 0x3500, 0x3f00);
+    //WDT
+    //fh_pmu_write_mask(REG_PMU_CLK_DIV5, 0x1d00, 0x3f00);
+    fh_pmu_write_mask(REG_PMU_CLK_DIV5, 0x3500, 0x3f00);
 
- 	//clock enable
-	fh_pmu_write_mask(REG_PMU_CLK_GATE, 0, 0x720ba080);
+    //clock enable
+    fh_pmu_write_mask(REG_PMU_CLK_GATE, 0, 0x720ba080);
 
     //sd0_drv_sel
-	fh_pmu_write_mask(REG_PMU_CLK_SEL, 0x200000, 0x300000);
+    fh_pmu_write_mask(REG_PMU_CLK_SEL, 0x200000, 0x300000);
     //sd0_sample_sel
-	fh_pmu_write_mask(REG_PMU_CLK_SEL, 0x00000, 0x30000);
+    fh_pmu_write_mask(REG_PMU_CLK_SEL, 0x00000, 0x30000);
 
- 	//sd1_drv_sel
-	fh_pmu_write_mask(REG_PMU_CLK_SEL, 0x2000, 0x3000);
- 	//sd1_sample_sel
-	fh_pmu_write_mask(REG_PMU_CLK_SEL, 0x000, 0x300);
+    //sd1_drv_sel
+    fh_pmu_write_mask(REG_PMU_CLK_SEL, 0x2000, 0x3000);
+    //sd1_sample_sel
+    fh_pmu_write_mask(REG_PMU_CLK_SEL, 0x000, 0x300);
 
  }
 
 
 void fh_platform_info_register(void){
-	struct fh_board_info *test_info;
-	int i;
+    struct fh_board_info *test_info;
+    int i;
 
-	for(i=0;iname,platform_info[i]->private_data);
-		if(!test_info){
-			rt_kprintf("info_name(%s) failed registered\n", platform_info[i]->name);
-		}
-	}
+    for(i=0;iname,platform_info[i]->private_data);
+        if(!test_info){
+            rt_kprintf("info_name(%s) failed registered\n", platform_info[i]->name);
+        }
+    }
 }
 
 void rt_hw_board_init()
 {
-	/* initialize the system clock */
-	rt_hw_clock_init();
-	//add iomux init 2015-3-11 by yu.zhang for fh81(fullhan)
-	//iomux_init();
+    /* initialize the system clock */
+    rt_hw_clock_init();
+    //add iomux init 2015-3-11 by yu.zhang for fh81(fullhan)
+    //iomux_init();
     fh_iomux_init(PMU_REG_BASE + 0x5c);
-	//add clk init  2015-3-11 by yu.zhang for fh81(fullhan)
-	clock_init();
-	/* initialize uart */
-	rt_hw_uart_init();
-	rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
-	/* initialize timer1 */
-	rt_hw_timer_init();
-	//board data info init...
-	fh_board_info_init();
-	fh_platform_info_register();
+    //add clk init  2015-3-11 by yu.zhang for fh81(fullhan)
+    clock_init();
+    /* initialize uart */
+    rt_hw_uart_init();
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+    /* initialize timer1 */
+    rt_hw_timer_init();
+    //board data info init...
+    fh_board_info_init();
+    fh_platform_info_register();
 
 }
 
 void rt_board_driver_init(){
 
-	//add board init lock here...
-	/*rt_show_version();*/
-	int ret;
+    //add board init lock here...
+    /*rt_show_version();*/
+    int ret;
 
 /* Filesystem Initialization */
 #ifdef RT_USING_DFS
-	{
-		/* init the device filesystem */
-		dfs_init();
-		rt_kprintf("DFS initialized!\n");
+    {
+        /* init the device filesystem */
+        dfs_init();
+        rt_kprintf("DFS initialized!\n");
 #if defined(RT_USING_DFS_ELMFAT)
-		/* init the elm chan FatFs filesystam*/
-		elm_init();
-		rt_kprintf("ELM initialized!\n");
+        /* init the elm chan FatFs filesystam*/
+        elm_init();
+        rt_kprintf("ELM initialized!\n");
 #endif
 
 #if defined(RT_USING_DFS_ROMFS)
-		dfs_romfs_init();
-		if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0)
-		{
-			rt_kprintf("ROM File System initialized!\n");
-		}
-		else
-			rt_kprintf("ROM File System initialzation failed!\n");
+        dfs_romfs_init();
+        if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0)
+        {
+            rt_kprintf("ROM File System initialized!\n");
+        }
+        else
+            rt_kprintf("ROM File System initialzation failed!\n");
 #endif
 
 #if defined(RT_USING_DFS_DEVFS)
-		devfs_init();
-		if (dfs_mount(RT_NULL, "/dev", "devfs", 0, 0) == 0)
-			rt_kprintf("Device File System initialized!\n");
-		else
-			rt_kprintf("Device File System initialzation failed!\n");
+        devfs_init();
+        if (dfs_mount(RT_NULL, "/dev", "devfs", 0, 0) == 0)
+            rt_kprintf("Device File System initialized!\n");
+        else
+            rt_kprintf("Device File System initialzation failed!\n");
 
-		#ifdef RT_USING_NEWLIB
-		/* init libc */
-		libc_system_init(RT_CONSOLE_DEVICE_NAME);
-		#endif
+        #ifdef RT_USING_NEWLIB
+        /* init libc */
+        libc_system_init(RT_CONSOLE_DEVICE_NAME);
+        #endif
 #endif
 
 #if defined(RT_USING_DFS_UFFS)
-	{
-		/* init the uffs filesystem */
-		dfs_uffs_init();
+    {
+        /* init the uffs filesystem */
+        dfs_uffs_init();
 
-		/* mount flash device as flash directory */
-		if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0)
-			rt_kprintf("UFFS File System initialized!\n");
-		else
-			rt_kprintf("UFFS File System initialzation failed!\n");
-	}
+        /* mount flash device as flash directory */
+        if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0)
+            rt_kprintf("UFFS File System initialized!\n");
+        else
+            rt_kprintf("UFFS File System initialzation failed!\n");
+    }
 #endif
 
 
 #ifdef RT_USING_DFS_RAMFS
-	dfs_ramfs_init();
-	{
-		rt_uint8_t *ramfs_pool = RT_NULL;
-		struct dfs_ramfs* ramfs;
-		ramfs_pool = rt_malloc(0x800000);
-		if(ramfs_pool)
-		{
-			ramfs =(struct dfs_ramfs*) dfs_ramfs_create((rt_uint8_t*)ramfs_pool, 0x800000);
-			if (ramfs != RT_NULL)
-			{
-				if (dfs_mount(RT_NULL, "/", "ram", 0, ramfs) == 0)
-				{
-					rt_kprintf("Mount RAMDisk done!\n");
-				}
-				else
-				{
-					rt_kprintf("Mount RAMDisk failed.\n");
-				}
-			}
-		}
-		else
-		{
-			rt_kprintf("alloc ramfs poll failed\n");
-		}
-	}
+    dfs_ramfs_init();
+    {
+        rt_uint8_t *ramfs_pool = RT_NULL;
+        struct dfs_ramfs* ramfs;
+        ramfs_pool = rt_malloc(0x800000);
+        if(ramfs_pool)
+        {
+            ramfs =(struct dfs_ramfs*) dfs_ramfs_create((rt_uint8_t*)ramfs_pool, 0x800000);
+            if (ramfs != RT_NULL)
+            {
+                if (dfs_mount(RT_NULL, "/", "ram", 0, ramfs) == 0)
+                {
+                    rt_kprintf("Mount RAMDisk done!\n");
+                }
+                else
+                {
+                    rt_kprintf("Mount RAMDisk failed.\n");
+                }
+            }
+        }
+        else
+        {
+            rt_kprintf("alloc ramfs poll failed\n");
+        }
+    }
 #endif
-	}
+    }
 #endif
 /* Filesystem Initialization end*/
 
 #ifdef RT_USING_GPIO
     {
         rt_hw_gpio_init();
-	rt_kprintf("GPIO initialized!\n");
+    rt_kprintf("GPIO initialized!\n");
 
 #ifdef RT_USING_SDIO
         //wifi
@@ -572,7 +572,7 @@ void rt_board_driver_init(){
         //micro sd
         gpio_request(HW_SDCARD_POWER_GPIO);
         gpio_direction_output(HW_SDCARD_POWER_GPIO, 0);
-	rt_kprintf("SDIO initialized!\n");
+    rt_kprintf("SDIO initialized!\n");
 #endif
         //sensor
         gpio_request(HW_CIS_RST_GPIO);
@@ -585,7 +585,7 @@ void rt_board_driver_init(){
 #ifdef RT_USING_SDIO
 #ifndef RT_USING_WIFI_MARVEL
     rt_hw_mmc_init();
-	rt_kprintf("MMC initialized!\n");
+    rt_kprintf("MMC initialized!\n");
     rt_thread_delay(RT_TICK_PER_SECOND*2);
     /* mount sd card fat partition 1 as root directory */
     #ifdef RT_USING_DFS_ELMFAT
@@ -601,56 +601,56 @@ void rt_board_driver_init(){
 
 
 #ifdef RT_USING_FH_DMA
-	{
+    {
         rt_fh_dma_init();
-	rt_kprintf("DMA initialized!\n");
-	}
+    rt_kprintf("DMA initialized!\n");
+    }
 #endif
 
 
 
 #ifdef RT_USING_FH_ACW
-	{
-		 fh_audio_init();
-			rt_kprintf("AUDIO initialized!\n");
-	}
+    {
+         fh_audio_init();
+            rt_kprintf("AUDIO initialized!\n");
+    }
 #endif
 
 #ifdef RT_USING_LWIP
-	{
-		/* init lwip system */
-		lwip_sys_init();
-		rt_kprintf("LWIP SYS initialized!\n");
-		eth_system_device_init();
-		rt_kprintf("ETH initialized!\n");
-	}
+    {
+        /* init lwip system */
+        lwip_sys_init();
+        rt_kprintf("LWIP SYS initialized!\n");
+        eth_system_device_init();
+        rt_kprintf("ETH initialized!\n");
+    }
 #endif
 
 #ifdef RT_USING_GMAC
         /* register ethernetif device */
         rt_app_fh_gmac_init();
-	rt_kprintf("GMAC initialized!\n");
+    rt_kprintf("GMAC initialized!\n");
 #endif
 
 
 #ifdef RT_USING_I2C
-	{
-	    rt_hw_i2c_init();
-		rt_kprintf("I2C initialized!\n");
-	}
+    {
+        rt_hw_i2c_init();
+        rt_kprintf("I2C initialized!\n");
+    }
 #endif
 
 #ifdef RT_USING_PWM
     {
         rt_hw_pwm_init();
-	rt_kprintf("PWM initialized!\n");
+    rt_kprintf("PWM initialized!\n");
 }
 #endif
 
 #ifdef RT_USING_WDT
     {
         rt_hw_wdt_init();
-	rt_kprintf("WDT initialized!\n");
+    rt_kprintf("WDT initialized!\n");
 }
 #endif
 
@@ -658,7 +658,7 @@ void rt_board_driver_init(){
 #ifdef RT_USING_SPI
     {
         rt_hw_spi_init();
-	rt_kprintf("SPI initialized!\n");
+    rt_kprintf("SPI initialized!\n");
     }
 #endif
 
@@ -668,21 +668,21 @@ void rt_board_driver_init(){
     rt_kprintf("FLASH initialized!\n");
 #endif
 
-	rt_kprintf("init done\n");
+    rt_kprintf("init done\n");
 #ifdef RT_USING_SADC
     rt_hw_sadc_init();
-	rt_kprintf("SADC initialized!\n");
+    rt_kprintf("SADC initialized!\n");
 #endif
 
 #ifdef RT_USING_ENC28J60
-	gpio_request(ENC28J60_INT);
-	gpio_direction_input(ENC28J60_INT);
-	gpio_set_irq_type(ENC28J60_INT, IRQ_TYPE_EDGE_FALLING);
-	rt_hw_interrupt_install(gpio_to_irq(ENC28J60_INT), (void *)enc28j60_isr, RT_NULL, RT_NULL);
-	gpio_irq_enable(gpio_to_irq(ENC28J60_INT));
-	gpio_release(ENC28J60_INT);
+    gpio_request(ENC28J60_INT);
+    gpio_direction_input(ENC28J60_INT);
+    gpio_set_irq_type(ENC28J60_INT, IRQ_TYPE_EDGE_FALLING);
+    rt_hw_interrupt_install(gpio_to_irq(ENC28J60_INT), (void *)enc28j60_isr, RT_NULL, RT_NULL);
+    gpio_irq_enable(gpio_to_irq(ENC28J60_INT));
+    gpio_release(ENC28J60_INT);
 
-	enc28j60_attach(ENC28J60_SPI_DEV);
+    enc28j60_attach(ENC28J60_SPI_DEV);
 #endif
 }
 
diff --git a/bsp/fh8620/platform/fh8620/iot_cam/board_def.h b/bsp/fh8620/platform/fh8620/iot_cam/board_def.h
index 48551b7095..902375f429 100644
--- a/bsp/fh8620/platform/fh8620/iot_cam/board_def.h
+++ b/bsp/fh8620/platform/fh8620/iot_cam/board_def.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,18 +18,18 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #ifndef BOARD_DEF_H_
 #define BOARD_DEF_H_
 
 
 /* ***********************
- * SECTION:	DRIVE
+ * SECTION: DRIVE
  * ***********************/
 // Basic drive..
 #define RT_USING_UART1
@@ -49,22 +49,22 @@
 #define CONFIG_PLAT_V2
 
 #ifndef FH_DDR_START
-#define	FH_DDR_START		0xA0000000
-#define FH_DDR_END		0xA1000000
+#define FH_DDR_START        0xA0000000
+#define FH_DDR_END      0xA1000000
 
-#define FH_RTT_OS_MEM_SIZE	0x00600000
-#define FH_DMA_MEM_SIZE		0x20000 /* 128k */
+#define FH_RTT_OS_MEM_SIZE  0x00600000
+#define FH_DMA_MEM_SIZE     0x20000 /* 128k */
 
-#define FH_RTT_OS_MEM_END	(FH_DDR_START + FH_RTT_OS_MEM_SIZE)
-#define FH_SDK_MEM_START	(FH_RTT_OS_MEM_END + FH_DMA_MEM_SIZE)
-#define FH_RTT_OS_HEAP_END	FH_SDK_MEM_START
-#define FH_SDK_MEM_SIZE		(FH_DDR_END - FH_SDK_MEM_START)
+#define FH_RTT_OS_MEM_END   (FH_DDR_START + FH_RTT_OS_MEM_SIZE)
+#define FH_SDK_MEM_START    (FH_RTT_OS_MEM_END + FH_DMA_MEM_SIZE)
+#define FH_RTT_OS_HEAP_END  FH_SDK_MEM_START
+#define FH_SDK_MEM_SIZE     (FH_DDR_END - FH_SDK_MEM_START)
 #endif /* end of FH_DDR_START*/
- 
+
 /* ***********************
- * SECTION:	DRIVE COMPONENT
+ * SECTION: DRIVE COMPONENT
  * ***********************/
-#define UART_NAME 						"uart1"
+#define UART_NAME                       "uart1"
 #define RT_USING_DMA_MEM
 
 #define RT_USING_MCI0
diff --git a/bsp/fh8620/platform/fh8620/iot_cam/iomux.c b/bsp/fh8620/platform/fh8620/iot_cam/iomux.c
index ee0bb63260..dc699c4450 100644
--- a/bsp/fh8620/platform/fh8620/iot_cam/iomux.c
+++ b/bsp/fh8620/platform/fh8620/iot_cam/iomux.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,650 +18,650 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #include "rtdef.h"
 #include "iomux.h"
 #include "rtconfig.h"
 
 
 Iomux_Pad fh_iomux_cfg[] = {
-		{
-			.func_name = { "RESETN", "", "", "", },
-			.reg_type  = 9,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_UP,
-			.drv_cur   = -1,
-		},
-		{
-			.func_name = { "TEST", "", "", "", },
-			.reg_type  = 9,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = -1,
-		},
-		{
-			.func_name = { "CIS_CLK", "", "", "", },
-			.reg_type  = 5,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_NONE,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "CIS_HSYNC", "GPIO20", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "CIS_VSYNC", "GPIO21", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "CIS_PCLK", "", "", "", },
-			.reg_type  = 9,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 0,
-		},
-		{
-			.func_name = { "CIS_D0", "GPIO22", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "CIS_D1", "GPIO23", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "CIS_D2", "GPIO24", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "CIS_D3", "GPIO25", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "CIS_D4", "GPIO26", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "CIS_D5", "GPIO27", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "CIS_D6", "GPIO28", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "CIS_D7", "GPIO29", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "CIS_D8", "GPIO30", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "CIS_D9", "GPIO31", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "CIS_D10", "GPIO32", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "CIS_D11", "GPIO33", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "MAC_REF_CLK", "", "", "", },
-			.reg_type  = 17,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_NONE,
-			.drv_cur   = 3,
-		},
-		{
-			.func_name = { "MAC_MDC", "GPIO34", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 1,
-			.pupd 	   = IOMUX_PUPD_NONE,
-			.drv_cur   = 0,
-		},
-		{
-			.func_name = { "MAC_MDIO", "", "", "", },
-			.reg_type  = 17,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "MAC_COL", "GPIO35", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 1,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "MAC_CRS", "GPIO36", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 1,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "MAC_RXCK", "", "", "", },
-			.reg_type  = 9,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = -1,
-		},
-		{
-			.func_name = { "MAC_RXD0", "", "", "", },
-			.reg_type  = 17,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = -1,
-		},
+        {
+            .func_name = { "RESETN", "", "", "", },
+            .reg_type  = 9,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_UP,
+            .drv_cur   = -1,
+        },
+        {
+            .func_name = { "TEST", "", "", "", },
+            .reg_type  = 9,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = -1,
+        },
+        {
+            .func_name = { "CIS_CLK", "", "", "", },
+            .reg_type  = 5,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_NONE,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "CIS_HSYNC", "GPIO20", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "CIS_VSYNC", "GPIO21", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "CIS_PCLK", "", "", "", },
+            .reg_type  = 9,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 0,
+        },
+        {
+            .func_name = { "CIS_D0", "GPIO22", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "CIS_D1", "GPIO23", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "CIS_D2", "GPIO24", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "CIS_D3", "GPIO25", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "CIS_D4", "GPIO26", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "CIS_D5", "GPIO27", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "CIS_D6", "GPIO28", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "CIS_D7", "GPIO29", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "CIS_D8", "GPIO30", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "CIS_D9", "GPIO31", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "CIS_D10", "GPIO32", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "CIS_D11", "GPIO33", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "MAC_REF_CLK", "", "", "", },
+            .reg_type  = 17,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_NONE,
+            .drv_cur   = 3,
+        },
+        {
+            .func_name = { "MAC_MDC", "GPIO34", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 1,
+            .pupd      = IOMUX_PUPD_NONE,
+            .drv_cur   = 0,
+        },
+        {
+            .func_name = { "MAC_MDIO", "", "", "", },
+            .reg_type  = 17,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "MAC_COL", "GPIO35", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 1,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "MAC_CRS", "GPIO36", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 1,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "MAC_RXCK", "", "", "", },
+            .reg_type  = 9,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = -1,
+        },
+        {
+            .func_name = { "MAC_RXD0", "", "", "", },
+            .reg_type  = 17,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = -1,
+        },
 
-		{
-			.func_name = { "MAC_RXD1", "GPIO38", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 1,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "MAC_RXD2", "GPIO39", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 1,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "MAC_RXD3", "GPIO40", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 1,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "MAC_RXDV", "GPIO41", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 1,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "MAC_TXCK", "", "", "", },
-			.reg_type  = 9,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = -1,
-		},
-		{
-			.func_name = { "MAC_TXD0", "GPIO42", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 1,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "MAC_TXD1", "GPIO43", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 1,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "MAC_TXD2", "GPIO44", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 1,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "MAC_TXD3", "GPIO45", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 1,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "MAC_TXEN", "GPIO46", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 1,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "MAC_RXER", "GPIO47", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 1,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "GPIO0", "ARC_JTAG_TCK", "GPIO0", "CIS_SSI0_CSN1", },
-			.reg_type  = 21,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_NONE,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "GPIO1", "ARC_JTAG_TRSTN", "GPIO1", "CIS_SSI0_RXD", },
-			.reg_type  = 21,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_NONE,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "GPIO2", "ARC_JTAG_TMS", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_NONE,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "GPIO3", "ARC_JTAG_TDI", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_NONE,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "GPIO4", "ARC_JTAG_TDO", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_NONE,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "JTAG_TCK", "GPIO5", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 1,
-			.pupd 	   = IOMUX_PUPD_NONE,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "JTAG_TRSTN", "GPIO6", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 1,
-			.pupd 	   = IOMUX_PUPD_NONE,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "JTAG_TMS", "GPIO7", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 1,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "JTAG_TDI", "GPIO8", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 1,
-			.pupd 	   = IOMUX_PUPD_NONE,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "JTAG_TDO", "GPIO9", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 1,
-			.pupd 	   = IOMUX_PUPD_NONE,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "GPIO10", "UART1_OUT", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 1,
-			.pupd 	   = IOMUX_PUPD_UP,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "GPIO11", "UART1_IN", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 1,
-			.pupd 	   = IOMUX_PUPD_UP,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "GPIO12", "PWM_OUT0", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 1,
-			.pupd 	   = IOMUX_PUPD_NONE,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "GPIO13", "PWM_OUT1", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_NONE,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "GPIO14", "PWM_OUT2", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_NONE,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "RESERVED", "", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-		},
-		{
-			.func_name = { "RESERVED", "", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-		},
-		{
-			.func_name = { "RESERVED", "", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-		},
-		{
-			.func_name = { "RESERVED", "", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-		},
-		{
-			.func_name = { "RESERVED", "", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-		},
-		{
-			.func_name = { "UART0_IN", "GPIO48", "UART0_IN", " I2S_WS", },
-			.reg_type  = 21,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_UP,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "UART0_OUT", "GPIO49", "UART0_OUT", "I2S_CLK", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "CIS_SCL", "GPIO56", "CIS_SCL", "CIS_SSI0_CLK", },
-			.reg_type  = 13,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_NONE,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "CIS_SDA", "GPIO57", "CIS_SDA", "CIS_SSI0_TXD", },
-			.reg_type  = 13,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_NONE,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "SCL1", "GPIO50", "SCL1", "I2S_DI", },
-			.reg_type  = 21,
-			.func_sel  = 1,
-			.pupd 	   = IOMUX_PUPD_NONE,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "SDA1", "GPIO51", "I2S_DO", "", },
-			.reg_type  = 21,
-			.func_sel  = 1,
-			.pupd 	   = IOMUX_PUPD_NONE,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "SSI0_CLK", "", "", "", },
-			.reg_type  = 5,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_NONE,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "SSI0_TXD", "", "", "", },
-			.reg_type  = 5,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_NONE,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "SSI0_CSN0", "GPIO54", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 1,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "SSI0_CSN1", "GPIO55", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 1,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "SSI0_RXD", "", "", "", },
-			.reg_type  = 17,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = -1,
-		},
-		{
-			.func_name = { "SD0_CD", "GPIO52", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "SD0_WP", "GPIO53", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "SD0_CLK", "", "", "", },
-			.reg_type  = 5,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_NONE,
-			.drv_cur   = 3,
-		},
-		{
-			.func_name = { "SD0_CMD_RSP", "", "", "", },
-			.reg_type  = 17,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_UP,
-			.drv_cur   = 3,
-		},
-		{
-			.func_name = { "SD0_DATA0", "", "", "", },
-			.reg_type  = 17,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_UP,
-			.drv_cur   = 3,
-		},
-		{
-			.func_name = { "SD0_DATA1", "", "", "", },
-			.reg_type  = 17,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_UP,
-			.drv_cur   = 2,
-		},
-		{
-			.func_name = { "SD0_DATA2", "", "", "", },
-			.reg_type  = 17,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_UP,
-			.drv_cur   = 3,
-		},
-		{
-			.func_name = { "SD0_DATA3", "", "", "", },
-			.reg_type  = 17,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_UP,
-			.drv_cur   = 3,
-		},
-		{
-			.func_name = { "SD1_CLK", "SSI1_CLK", "", "", },
-			.reg_type  = 8,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_NONE,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "SD1_CD", "GPIO_58", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "SD1_WP", "GPIO_59", "", "", },
-			.reg_type  = 20,
-	        .func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
-		{
-			.func_name = { "SD1_DATA0", "SSI1_TXD", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_UP,
-			.drv_cur   = 3,
-		},
-		{
-			.func_name = { "SD1_DATA1", "SSI1_CSN0", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_UP,
-			.drv_cur   = 3,
-		},
-		{
-			.func_name = { "SD1_DATA2", "SSI1_CSN1", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_UP,
-			.drv_cur   = 3,
-		},
-		{
-			.func_name = { "SD1_DATA3", "", "", "", },
-			.reg_type  = 17,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_UP,
-			.drv_cur   = 3,
-		},
-		{
-			.func_name = { "SD1_CMD_RSP", "SSI1_RXD", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_UP,
-			.drv_cur   = 3,
-		},
-		{
-			.func_name = { "RESERVED", "", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-		},
-		{
-			.func_name = { "RESERVED", "", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-		},
-		{
-			.func_name = { "RESERVED", "", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-		},
-		{
-			.func_name = { "RESERVED", "", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-		},
-		{
-			.func_name = { "CLK_SW0", "", "", "", },
-			.reg_type  = 9,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_UP,
-			.drv_cur   = -1,
-		},
-		{
-			.func_name = { "CLK_SW1", "", "", "", },
-			.reg_type  = 9,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_UP,
-			.drv_cur   = -1,
-		},
-		{
-			.func_name = { "CLK_SW2", "", "", "", },
-			.reg_type  = 9,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_UP,
-			.drv_cur   = -1,
-		},
-		{
-			.func_name = { "CLK_SW3", "", "", "", },
-			.reg_type  = 9,
-			.func_sel  = 0,
-			.pupd 	   = IOMUX_PUPD_UP,
-			.drv_cur   = -1,
-		},
-		{
-			.func_name = { "RESERVED", "", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 0,
-		},
-		{
-			.func_name = { "MAC_TXER", "GPIO37", "", "", },
-			.reg_type  = 20,
-			.func_sel  = 1,
-			.pupd 	   = IOMUX_PUPD_DOWN,
-			.drv_cur   = 1,
-		},
+        {
+            .func_name = { "MAC_RXD1", "GPIO38", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 1,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "MAC_RXD2", "GPIO39", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 1,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "MAC_RXD3", "GPIO40", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 1,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "MAC_RXDV", "GPIO41", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 1,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "MAC_TXCK", "", "", "", },
+            .reg_type  = 9,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = -1,
+        },
+        {
+            .func_name = { "MAC_TXD0", "GPIO42", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 1,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "MAC_TXD1", "GPIO43", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 1,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "MAC_TXD2", "GPIO44", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 1,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "MAC_TXD3", "GPIO45", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 1,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "MAC_TXEN", "GPIO46", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 1,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "MAC_RXER", "GPIO47", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 1,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "GPIO0", "ARC_JTAG_TCK", "GPIO0", "CIS_SSI0_CSN1", },
+            .reg_type  = 21,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_NONE,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "GPIO1", "ARC_JTAG_TRSTN", "GPIO1", "CIS_SSI0_RXD", },
+            .reg_type  = 21,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_NONE,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "GPIO2", "ARC_JTAG_TMS", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_NONE,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "GPIO3", "ARC_JTAG_TDI", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_NONE,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "GPIO4", "ARC_JTAG_TDO", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_NONE,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "JTAG_TCK", "GPIO5", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 1,
+            .pupd      = IOMUX_PUPD_NONE,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "JTAG_TRSTN", "GPIO6", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 1,
+            .pupd      = IOMUX_PUPD_NONE,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "JTAG_TMS", "GPIO7", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 1,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "JTAG_TDI", "GPIO8", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 1,
+            .pupd      = IOMUX_PUPD_NONE,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "JTAG_TDO", "GPIO9", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 1,
+            .pupd      = IOMUX_PUPD_NONE,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "GPIO10", "UART1_OUT", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 1,
+            .pupd      = IOMUX_PUPD_UP,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "GPIO11", "UART1_IN", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 1,
+            .pupd      = IOMUX_PUPD_UP,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "GPIO12", "PWM_OUT0", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 1,
+            .pupd      = IOMUX_PUPD_NONE,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "GPIO13", "PWM_OUT1", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_NONE,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "GPIO14", "PWM_OUT2", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_NONE,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "RESERVED", "", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+        },
+        {
+            .func_name = { "RESERVED", "", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+        },
+        {
+            .func_name = { "RESERVED", "", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+        },
+        {
+            .func_name = { "RESERVED", "", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+        },
+        {
+            .func_name = { "RESERVED", "", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+        },
+        {
+            .func_name = { "UART0_IN", "GPIO48", "UART0_IN", " I2S_WS", },
+            .reg_type  = 21,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_UP,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "UART0_OUT", "GPIO49", "UART0_OUT", "I2S_CLK", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "CIS_SCL", "GPIO56", "CIS_SCL", "CIS_SSI0_CLK", },
+            .reg_type  = 13,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_NONE,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "CIS_SDA", "GPIO57", "CIS_SDA", "CIS_SSI0_TXD", },
+            .reg_type  = 13,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_NONE,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "SCL1", "GPIO50", "SCL1", "I2S_DI", },
+            .reg_type  = 21,
+            .func_sel  = 1,
+            .pupd      = IOMUX_PUPD_NONE,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "SDA1", "GPIO51", "I2S_DO", "", },
+            .reg_type  = 21,
+            .func_sel  = 1,
+            .pupd      = IOMUX_PUPD_NONE,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "SSI0_CLK", "", "", "", },
+            .reg_type  = 5,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_NONE,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "SSI0_TXD", "", "", "", },
+            .reg_type  = 5,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_NONE,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "SSI0_CSN0", "GPIO54", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 1,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "SSI0_CSN1", "GPIO55", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 1,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "SSI0_RXD", "", "", "", },
+            .reg_type  = 17,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = -1,
+        },
+        {
+            .func_name = { "SD0_CD", "GPIO52", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "SD0_WP", "GPIO53", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "SD0_CLK", "", "", "", },
+            .reg_type  = 5,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_NONE,
+            .drv_cur   = 3,
+        },
+        {
+            .func_name = { "SD0_CMD_RSP", "", "", "", },
+            .reg_type  = 17,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_UP,
+            .drv_cur   = 3,
+        },
+        {
+            .func_name = { "SD0_DATA0", "", "", "", },
+            .reg_type  = 17,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_UP,
+            .drv_cur   = 3,
+        },
+        {
+            .func_name = { "SD0_DATA1", "", "", "", },
+            .reg_type  = 17,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_UP,
+            .drv_cur   = 2,
+        },
+        {
+            .func_name = { "SD0_DATA2", "", "", "", },
+            .reg_type  = 17,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_UP,
+            .drv_cur   = 3,
+        },
+        {
+            .func_name = { "SD0_DATA3", "", "", "", },
+            .reg_type  = 17,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_UP,
+            .drv_cur   = 3,
+        },
+        {
+            .func_name = { "SD1_CLK", "SSI1_CLK", "", "", },
+            .reg_type  = 8,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_NONE,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "SD1_CD", "GPIO_58", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "SD1_WP", "GPIO_59", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
+        {
+            .func_name = { "SD1_DATA0", "SSI1_TXD", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_UP,
+            .drv_cur   = 3,
+        },
+        {
+            .func_name = { "SD1_DATA1", "SSI1_CSN0", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_UP,
+            .drv_cur   = 3,
+        },
+        {
+            .func_name = { "SD1_DATA2", "SSI1_CSN1", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_UP,
+            .drv_cur   = 3,
+        },
+        {
+            .func_name = { "SD1_DATA3", "", "", "", },
+            .reg_type  = 17,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_UP,
+            .drv_cur   = 3,
+        },
+        {
+            .func_name = { "SD1_CMD_RSP", "SSI1_RXD", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_UP,
+            .drv_cur   = 3,
+        },
+        {
+            .func_name = { "RESERVED", "", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+        },
+        {
+            .func_name = { "RESERVED", "", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+        },
+        {
+            .func_name = { "RESERVED", "", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+        },
+        {
+            .func_name = { "RESERVED", "", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+        },
+        {
+            .func_name = { "CLK_SW0", "", "", "", },
+            .reg_type  = 9,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_UP,
+            .drv_cur   = -1,
+        },
+        {
+            .func_name = { "CLK_SW1", "", "", "", },
+            .reg_type  = 9,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_UP,
+            .drv_cur   = -1,
+        },
+        {
+            .func_name = { "CLK_SW2", "", "", "", },
+            .reg_type  = 9,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_UP,
+            .drv_cur   = -1,
+        },
+        {
+            .func_name = { "CLK_SW3", "", "", "", },
+            .reg_type  = 9,
+            .func_sel  = 0,
+            .pupd      = IOMUX_PUPD_UP,
+            .drv_cur   = -1,
+        },
+        {
+            .func_name = { "RESERVED", "", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 0,
+        },
+        {
+            .func_name = { "MAC_TXER", "GPIO37", "", "", },
+            .reg_type  = 20,
+            .func_sel  = 1,
+            .pupd      = IOMUX_PUPD_DOWN,
+            .drv_cur   = 1,
+        },
 };
 
 
diff --git a/bsp/fh8620/platform/fh8620/iot_cam/startup.c b/bsp/fh8620/platform/fh8620/iot_cam/startup.c
index ebadf0677b..6787dc7f37 100644
--- a/bsp/fh8620/platform/fh8620/iot_cam/startup.c
+++ b/bsp/fh8620/platform/fh8620/iot_cam/startup.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #include 
 #include 
 #include 
@@ -50,13 +50,13 @@ extern void rt_system_heap_init(void*, void*);
 extern void rt_hw_finsh_init(void);
 extern void rt_application_init(void);
 
-static struct mem_desc fh_mem_desc[] = 
+static struct mem_desc fh_mem_desc[] =
 {
-		{ 0xA0000000, FH_RTT_OS_MEM_END-1, 0xA0000000, SECT_RWX_CB, 0, SECT_MAPPED },
-		{ FH_RTT_OS_MEM_END, FH_DDR_END-1, FH_RTT_OS_MEM_END, SECT_RWNX_NCNB, 0, SECT_MAPPED },
-		{ 0xFFFF0000, 0xFFFF1000-1, 0xA0000000, SECT_TO_PAGE, PAGE_ROX_CB, PAGE_MAPPED }, /* isr vector table */
-		{ 0xE0000000, 0xF1300000-1, 0xE0000000, SECT_RWNX_NCNB, 0, SECT_MAPPED },       /* io table */
-		{ 0xF4000000, 0xF4100000-1, 0xF4000000, SECT_RWNX_NCNB, 0, SECT_MAPPED },       /* GPIO#1 io table */
+        { 0xA0000000, FH_RTT_OS_MEM_END-1, 0xA0000000, SECT_RWX_CB, 0, SECT_MAPPED },
+        { FH_RTT_OS_MEM_END, FH_DDR_END-1, FH_RTT_OS_MEM_END, SECT_RWNX_NCNB, 0, SECT_MAPPED },
+        { 0xFFFF0000, 0xFFFF1000-1, 0xA0000000, SECT_TO_PAGE, PAGE_ROX_CB, PAGE_MAPPED }, /* isr vector table */
+        { 0xE0000000, 0xF1300000-1, 0xE0000000, SECT_RWNX_NCNB, 0, SECT_MAPPED },       /* io table */
+        { 0xF4000000, 0xF4100000-1, 0xF4000000, SECT_RWNX_NCNB, 0, SECT_MAPPED },       /* GPIO#1 io table */
 };
 
 rt_uint8_t _irq_stack_start[1024];
@@ -72,46 +72,46 @@ extern unsigned char __bss_end;
  */
 void rtthread_startup(void)
 {
-	/* disable interrupt first */
-	rt_hw_interrupt_disable();
-	/* initialize hardware interrupt */
-	rt_hw_interrupt_init();
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
+    /* initialize hardware interrupt */
+    rt_hw_interrupt_init();
 
-	/* initialize mmu */
-	rt_hw_mmu_init(fh_mem_desc, sizeof(fh_mem_desc)/sizeof(fh_mem_desc[0]));
+    /* initialize mmu */
+    rt_hw_mmu_init(fh_mem_desc, sizeof(fh_mem_desc)/sizeof(fh_mem_desc[0]));
 
-	rt_system_heap_init((void*)&__bss_end, (void*)FH_RTT_OS_MEM_END);
+    rt_system_heap_init((void*)&__bss_end, (void*)FH_RTT_OS_MEM_END);
 
 #ifdef RT_USING_DMA_MEM
-	//just use the last 100KB
-	fh_dma_mem_init((rt_uint32_t *)FH_RTT_OS_MEM_END, FH_DMA_MEM_SIZE);
+    //just use the last 100KB
+    fh_dma_mem_init((rt_uint32_t *)FH_RTT_OS_MEM_END, FH_DMA_MEM_SIZE);
 #endif
 
-	/* initialize board */
-	rt_hw_board_init();
+    /* initialize board */
+    rt_hw_board_init();
 
-	/* show version */
-	rt_show_version();
+    /* show version */
+    rt_show_version();
 
-	/* initialize timer system */
-	rt_system_timer_init();
+    /* initialize timer system */
+    rt_system_timer_init();
 
-	/* initialize scheduler system */
-	rt_system_scheduler_init();
+    /* initialize scheduler system */
+    rt_system_scheduler_init();
 
-	/* initialize application */
-	rt_application_init();
+    /* initialize application */
+    rt_application_init();
 
-	/* initialize system timer thread */
-	rt_system_timer_thread_init();
+    /* initialize system timer thread */
+    rt_system_timer_thread_init();
 
-	/* initialize idle thread */
-	rt_thread_idle_init();
+    /* initialize idle thread */
+    rt_thread_idle_init();
 
-	/* start scheduler */
-	rt_system_scheduler_start();
+    /* start scheduler */
+    rt_system_scheduler_start();
 
-	/* never reach here */
+    /* never reach here */
 
-	return ;
+    return ;
 }
diff --git a/bsp/fh8620/platform/fh_arch.h b/bsp/fh8620/platform/fh_arch.h
index 2cbe36718a..a8360cda54 100644
--- a/bsp/fh8620/platform/fh_arch.h
+++ b/bsp/fh8620/platform/fh_arch.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #ifndef FH_ARCH_H_
 #define FH_ARCH_H_
 
diff --git a/bsp/fh8620/platform/fh_def.h b/bsp/fh8620/platform/fh_def.h
index 57bedcb9e7..4a97709d54 100644
--- a/bsp/fh8620/platform/fh_def.h
+++ b/bsp/fh8620/platform/fh_def.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #ifndef FH_DEF_H_
 #define FH_DEF_H_
 
@@ -32,29 +32,29 @@
 #define MIN(a,b) ((a) < (b) ? (a) : (b))
 #define MAX(a,b) ((a) > (b) ? (a) : (b))
 
-typedef char				SINT8;
-typedef short				SINT16;
-typedef int					SINT32;
-typedef long long			SINT64;
-typedef unsigned char		UINT8;
-typedef unsigned short		UINT16;
-typedef unsigned int		UINT32;
-typedef unsigned long long	UINT64;
+typedef char                SINT8;
+typedef short               SINT16;
+typedef int                 SINT32;
+typedef long long           SINT64;
+typedef unsigned char       UINT8;
+typedef unsigned short      UINT16;
+typedef unsigned int        UINT32;
+typedef unsigned long long  UINT64;
 
 #ifndef TYPE_DEFINED
-typedef	unsigned char		uchar;
-typedef signed   char		int8;
-typedef unsigned char		uint8;
-typedef signed   short		int16;
-typedef unsigned short		uint16;
-typedef signed   int		int32;
-typedef unsigned int		uint32;
-typedef signed   long  long	int64;
-typedef unsigned long long	uint64;
-typedef float        		ieee_single;
-typedef double       		ieee_double;
+typedef unsigned char       uchar;
+typedef signed   char       int8;
+typedef unsigned char       uint8;
+typedef signed   short      int16;
+typedef unsigned short      uint16;
+typedef signed   int        int32;
+typedef unsigned int        uint32;
+typedef signed   long  long int64;
+typedef unsigned long long  uint64;
+typedef float               ieee_single;
+typedef double              ieee_double;
 
-typedef unsigned long  		boolean;
+typedef unsigned long       boolean;
 
 #define TYPE_DEFINED
 
diff --git a/bsp/fh8620/platform/plat-v2/arch.h b/bsp/fh8620/platform/plat-v2/arch.h
index bb32d96ea4..c8d23c0163 100644
--- a/bsp/fh8620/platform/plat-v2/arch.h
+++ b/bsp/fh8620/platform/plat-v2/arch.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,53 +18,53 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #ifndef ARCH_H_
 #define ARCH_H_
 
 /*****************************/
 /* BSP CONTROLLER BASE       */
 /*****************************/
-#define		INTC_REG_BASE		(0xE0200000)
-#define		SDC0_REG_BASE		(0xE2000000)
-#define		SDC1_REG_BASE		(0xE2100000)
-#define		TVE_REG_BASE		(0xE8000000)
-#define		VOU_REG_BASE		(0xE8100000)
-#define		AES_REG_BASE		(0xE8200000)
+#define     INTC_REG_BASE       (0xE0200000)
+#define     SDC0_REG_BASE       (0xE2000000)
+#define     SDC1_REG_BASE       (0xE2100000)
+#define     TVE_REG_BASE        (0xE8000000)
+#define     VOU_REG_BASE        (0xE8100000)
+#define     AES_REG_BASE        (0xE8200000)
 /*
-#define		JPEG_REG_BASE		(0xE8300000)
-#define		ISPB_REG_BASE		(0xEA000000)
-#define		ISPF_REG_BASE		(0xEA100000)
-#define		VPU_REG_BASE		(0xEC000000)
-#define		VCU_REG_BASE		(0xEC100000)
-#define		DDRC_REG_BASE		(0xED000000)
+#define     JPEG_REG_BASE       (0xE8300000)
+#define     ISPB_REG_BASE       (0xEA000000)
+#define     ISPF_REG_BASE       (0xEA100000)
+#define     VPU_REG_BASE        (0xEC000000)
+#define     VCU_REG_BASE        (0xEC100000)
+#define     DDRC_REG_BASE       (0xED000000)
 */
-#define 	DMAC_REG_BASE		(0xEE000000)
-#define 	GMAC_REG_BASE		(0xEF000000)
-#define 	PMU_REG_BASE		(0xF0000000)
-#define 	I2C0_REG_BASE		(0xF0200000)
-#define 	GPIO0_REG_BASE		(0xF0300000)
+#define     DMAC_REG_BASE       (0xEE000000)
+#define     GMAC_REG_BASE       (0xEF000000)
+#define     PMU_REG_BASE        (0xF0000000)
+#define     I2C0_REG_BASE       (0xF0200000)
+#define     GPIO0_REG_BASE      (0xF0300000)
 #define     GPIO1_REG_BASE      (0xf4000000)
-#define 	PWM_REG_BASE		(0xF0400000)
-#define 	SPI0_REG_BASE		(0xF0500000)
-#define 	SPI1_REG_BASE		(0xF0600000)
-#define		UART0_REG_BASE		(0xF0700000)
-#define		UART1_REG_BASE		(0xF0800000)
-/*#define		I2S_REG_BASE		(0xF0900000)*/
-#define		ACODEC_REG_BASE		(0xF0A00000)
-#define		I2C1_REG_BASE		(0xF0B00000)
-#define		TMR_REG_BASE		(0xF0C00000)
-#define		WDT_REG_BASE		(0xF0D00000)
+#define     PWM_REG_BASE        (0xF0400000)
+#define     SPI0_REG_BASE       (0xF0500000)
+#define     SPI1_REG_BASE       (0xF0600000)
+#define     UART0_REG_BASE      (0xF0700000)
+#define     UART1_REG_BASE      (0xF0800000)
+/*#define       I2S_REG_BASE        (0xF0900000)*/
+#define     ACODEC_REG_BASE     (0xF0A00000)
+#define     I2C1_REG_BASE       (0xF0B00000)
+#define     TMR_REG_BASE        (0xF0C00000)
+#define     WDT_REG_BASE        (0xF0D00000)
 /*
-#define		DPHY_REG_BASE		(0xF1000000)
-#define		MIPIC_REG_BASE		(0xF1100000)
+#define     DPHY_REG_BASE       (0xF1000000)
+#define     MIPIC_REG_BASE      (0xF1100000)
 */
-#define		SADC_REG_BASE		(0xF1200000)
+#define     SADC_REG_BASE       (0xF1200000)
 
 typedef enum IRQn
 {
diff --git a/bsp/fh8620/platform/plat-v2/clock.c b/bsp/fh8620/platform/plat-v2/clock.c
index 1c82348c7f..335b4c3ce9 100644
--- a/bsp/fh8620/platform/plat-v2/clock.c
+++ b/bsp/fh8620/platform/plat-v2/clock.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #include "clock.h"
 #include 
 #include "fh_arch.h"
@@ -40,8 +40,8 @@
 
 //#define FH_DBG_CLK
 
-#define FH_CLK_DIV_DEFAULT_VALUE			0x55aaaa55
-#define FH_CLK_GATE_DEFAULT_VALUE			0xaa5555aa
+#define FH_CLK_DIV_DEFAULT_VALUE            0x55aaaa55
+#define FH_CLK_GATE_DEFAULT_VALUE           0xaa5555aa
 
 #define CONFIG_PAE_PTS_CLOCK   (1000000)
 #define TICKS_PER_USEC         (CONFIG_PAE_PTS_CLOCK / 1000000)
@@ -50,15 +50,15 @@
 
 
 #define fh_clk_err(p,fmt,args...)\
-		rt_kprintf("clk_err: %s->\t"fmt,p->name, ##args)
+        rt_kprintf("clk_err: %s->\t"fmt,p->name, ##args)
 
 #ifdef FH_CLK_DEBUG
 #define fh_clk_debug(p,fmt,args...)\
-		rt_kprintf("%s:\t\t"fmt,p->name, ##args)
+        rt_kprintf("%s:\t\t"fmt,p->name, ##args)
 
 
 #define fh_clk_debug_no_handle(fmt,args...)\
-		rt_kprintf(fmt, ##args)
+        rt_kprintf(fmt, ##args)
 #else
 //#define fh_clk_err(p,fmt,args...)
 #define fh_clk_debug(p,fmt,args...)
@@ -77,48 +77,48 @@ static struct fh_clk_tree fh_clk_tree;
 
 
 
-#define FH_TIMER_WRITEL(offset,value)		__raw_writel(value,(fh_clk_tree.c_base_addr + offset))
-#define FH_TIMER_READL(offset)				__raw_readl((fh_clk_tree.c_base_addr + offset))
+#define FH_TIMER_WRITEL(offset,value)       __raw_writel(value,(fh_clk_tree.c_base_addr + offset))
+#define FH_TIMER_READL(offset)              __raw_readl((fh_clk_tree.c_base_addr + offset))
 
 
 
 
 
 enum clk_gate_enum{
-#define CLK_GATE			(1)
-#define CLK_UNGATE			(0)
-	ISP_ACLK_GATE = (1<<0),
-	HCLK_GATE = (1<<1),
-	CPU_FCLK0_GATE = (1<<3),
-	VCU_CLK_GATE = (1<<4),
-	VOU_CLK_GATE = (1<<5),
-	MCLK_GATE = (1<<6),
-	SPI0_CLK_GATE = (1<<7),
-	SPI1_CLK_GATE = (1<<8),
-	SDC0_CLK_GATE = (1<<9),
-	SDC1_CLK_GATE = (1<<10),
-	AC_MCLK_GATE = (1<<11),  /////
-	I2C0_CLK_GATE = (1<<12),
-	UART0_CLK_GATE = (1<<13),
-	UART1_CLK_GATE = (1<<14),
-	//can't change
-	WDT_CLK_GATE = (1<<15),
+#define CLK_GATE            (1)
+#define CLK_UNGATE          (0)
+    ISP_ACLK_GATE = (1<<0),
+    HCLK_GATE = (1<<1),
+    CPU_FCLK0_GATE = (1<<3),
+    VCU_CLK_GATE = (1<<4),
+    VOU_CLK_GATE = (1<<5),
+    MCLK_GATE = (1<<6),
+    SPI0_CLK_GATE = (1<<7),
+    SPI1_CLK_GATE = (1<<8),
+    SDC0_CLK_GATE = (1<<9),
+    SDC1_CLK_GATE = (1<<10),
+    AC_MCLK_GATE = (1<<11),  /////
+    I2C0_CLK_GATE = (1<<12),
+    UART0_CLK_GATE = (1<<13),
+    UART1_CLK_GATE = (1<<14),
+    //can't change
+    WDT_CLK_GATE = (1<<15),
 
-	PWM_CLK_GATE = (1<<16),
-	TMR0_CLK_GATE = (1<<17),
-	TMR1_CLK_GATE = (1<<18),
-	PTS_CLK_GATE = (1<<19),
-	MIPI_DPHY_CLK20M_GATE = (1<<20),
-	MIPI_P32_CLK_GATE = (1<<21),
-	PIX_CLK_GATE = (1<<22),			////
-	CIS_CLK_OUT_GATE = (1<<23),
-	I2S_SCLK_GATE = (1<<24),		//////
-	ETH_REF_CLK_GATE = (1<<25),
-	SADC_CLK_GATE = (1<<26),
-	I2C1_CLK_GATE = (1<<27),
-	ETH_RX_CLK_GATE = (1<<28), /////
-	ETH_TX_CLK_GATE = (1<<29), /////
-	ETH_RMII_CLK_GATE = (1<<30),////
+    PWM_CLK_GATE = (1<<16),
+    TMR0_CLK_GATE = (1<<17),
+    TMR1_CLK_GATE = (1<<18),
+    PTS_CLK_GATE = (1<<19),
+    MIPI_DPHY_CLK20M_GATE = (1<<20),
+    MIPI_P32_CLK_GATE = (1<<21),
+    PIX_CLK_GATE = (1<<22),         ////
+    CIS_CLK_OUT_GATE = (1<<23),
+    I2S_SCLK_GATE = (1<<24),        //////
+    ETH_REF_CLK_GATE = (1<<25),
+    SADC_CLK_GATE = (1<<26),
+    I2C1_CLK_GATE = (1<<27),
+    ETH_RX_CLK_GATE = (1<<28), /////
+    ETH_TX_CLK_GATE = (1<<29), /////
+    ETH_RMII_CLK_GATE = (1<<30),////
 
 
 };
@@ -130,96 +130,96 @@ enum clk_gate_enum{
 typedef void (*clk_update)(struct fh_clk* p_clk);
 
 //update func...
-void 	clk_in_update(struct fh_clk* p_clk);
-void 	pll1_clk_update(struct fh_clk* p_clk);
-void	pll0_clk_update(struct fh_clk* p_clk);
+void    clk_in_update(struct fh_clk* p_clk);
+void    pll1_clk_update(struct fh_clk* p_clk);
+void    pll0_clk_update(struct fh_clk* p_clk);
 void    cis_pclk_update(struct fh_clk* p_clk);
-void	ddr_clk_update(struct fh_clk* p_clk);
-void	ddr_clk_update(struct fh_clk* p_clk);
-void	fclk_update(struct fh_clk* p_clk);
-void	aclk_update(struct fh_clk* p_clk);
-void	hclk_update(struct fh_clk* p_clk);
-void	pclk_update(struct fh_clk* p_clk);
-void	isp_aclk_update(struct fh_clk* p_clk);
-void	vcu_clk_update(struct fh_clk* p_clk);
-void	vou_clk_update(struct fh_clk* p_clk);
-void	mipi_p32_clk_update(struct fh_clk* p_clk);
-void	cis_clk_out_update(struct fh_clk* p_clk);
-void	pts_update(struct fh_clk* p_clk);
-void 	mipi_pix_clk_update(struct fh_clk* p_clk);
-void	spi0_clk_update(struct fh_clk* p_clk);
-void	spi1_clk_update(struct fh_clk* p_clk);
-void	mipi_dphy_clk20m_update(struct fh_clk* p_clk);
-void	i2c0_clk_update(struct fh_clk* p_clk);
-void	i2c1_clk_update(struct fh_clk* p_clk);
-void	uart0_clk_update(struct fh_clk* p_clk);
-void	uart1_clk_update(struct fh_clk* p_clk);
-void	pwm_clk_update(struct fh_clk* p_clk);
-void	time0_clk_update(struct fh_clk* p_clk);
-void	time1_clk_update(struct fh_clk* p_clk);
-void	sadc_clk_update(struct fh_clk* p_clk);
-void	sdc0_clk2x_update(struct fh_clk* p_clk);
-void	sdc0_clk_update(struct fh_clk* p_clk);
-void	sdc0_clk_out_update(struct fh_clk* p_clk);
-void	sdc0_clk_sample_update(struct fh_clk* p_clk);
-void	sdc0_clk_drv_update(struct fh_clk* p_clk);
-void	sdc1_clk2x_update(struct fh_clk* p_clk);
-void	sdc1_clk_update(struct fh_clk* p_clk);
-void	sdc1_clk_out_update(struct fh_clk* p_clkt);
-void	sdc1_clk_sample_update(struct fh_clk* p_clk);
-void	sdc1_clk_drv_update(struct fh_clk* p_clk);
-void 	eth_ref_clk_update(struct fh_clk* p_clk);
-void	wdt_clk_update(struct fh_clk* p_clk);
+void    ddr_clk_update(struct fh_clk* p_clk);
+void    ddr_clk_update(struct fh_clk* p_clk);
+void    fclk_update(struct fh_clk* p_clk);
+void    aclk_update(struct fh_clk* p_clk);
+void    hclk_update(struct fh_clk* p_clk);
+void    pclk_update(struct fh_clk* p_clk);
+void    isp_aclk_update(struct fh_clk* p_clk);
+void    vcu_clk_update(struct fh_clk* p_clk);
+void    vou_clk_update(struct fh_clk* p_clk);
+void    mipi_p32_clk_update(struct fh_clk* p_clk);
+void    cis_clk_out_update(struct fh_clk* p_clk);
+void    pts_update(struct fh_clk* p_clk);
+void    mipi_pix_clk_update(struct fh_clk* p_clk);
+void    spi0_clk_update(struct fh_clk* p_clk);
+void    spi1_clk_update(struct fh_clk* p_clk);
+void    mipi_dphy_clk20m_update(struct fh_clk* p_clk);
+void    i2c0_clk_update(struct fh_clk* p_clk);
+void    i2c1_clk_update(struct fh_clk* p_clk);
+void    uart0_clk_update(struct fh_clk* p_clk);
+void    uart1_clk_update(struct fh_clk* p_clk);
+void    pwm_clk_update(struct fh_clk* p_clk);
+void    time0_clk_update(struct fh_clk* p_clk);
+void    time1_clk_update(struct fh_clk* p_clk);
+void    sadc_clk_update(struct fh_clk* p_clk);
+void    sdc0_clk2x_update(struct fh_clk* p_clk);
+void    sdc0_clk_update(struct fh_clk* p_clk);
+void    sdc0_clk_out_update(struct fh_clk* p_clk);
+void    sdc0_clk_sample_update(struct fh_clk* p_clk);
+void    sdc0_clk_drv_update(struct fh_clk* p_clk);
+void    sdc1_clk2x_update(struct fh_clk* p_clk);
+void    sdc1_clk_update(struct fh_clk* p_clk);
+void    sdc1_clk_out_update(struct fh_clk* p_clkt);
+void    sdc1_clk_sample_update(struct fh_clk* p_clk);
+void    sdc1_clk_drv_update(struct fh_clk* p_clk);
+void    eth_ref_clk_update(struct fh_clk* p_clk);
+void    wdt_clk_update(struct fh_clk* p_clk);
 
 rt_int32_t check_pix_clk_source(rt_uint32_t offset,rt_uint32_t mask,rt_uint32_t *value);
-void	 pix_update(struct fh_clk* p_clk);
+void     pix_update(struct fh_clk* p_clk);
 
 struct fh_clk_div{
 //some has prediv....
 //this two could have or......
-#define PRE_DIV_CAL_ALREADY		(0x80000000)
-#define PRE_DIV_ENABLE		(0x01)
-#define DIV_ENABLE			(0x10)
-	rt_uint32_t div_flag;
+#define PRE_DIV_CAL_ALREADY     (0x80000000)
+#define PRE_DIV_ENABLE      (0x01)
+#define DIV_ENABLE          (0x10)
+    rt_uint32_t div_flag;
 
-	rt_uint32_t pdiv_value;
+    rt_uint32_t pdiv_value;
 
-	//rt_uint32_t hw_div_value;
-	rt_uint32_t sw_div_value;
-	rt_uint32_t sw_div_multi;
-	//rt_uint32_t clk_in_hz;
-	rt_uint32_t reg_offset;
-	rt_uint32_t reg_mask;
-	//rt_uint32_t rate;
+    //rt_uint32_t hw_div_value;
+    rt_uint32_t sw_div_value;
+    rt_uint32_t sw_div_multi;
+    //rt_uint32_t clk_in_hz;
+    rt_uint32_t reg_offset;
+    rt_uint32_t reg_mask;
+    //rt_uint32_t rate;
 };
 
 struct fh_clk_mux{
-//#define MUX_LEVEL_1		(1)
-//#define MUX_LEVEL_2		(2)
-//#define MAX_MUX_LEVEL	MUX_LEVEL_2
-//	rt_uint32_t lev;
-#define HAS_MUX				(0)
-#define HAS_NO_MUX			(1)
-	rt_uint32_t mux_flag;
-	rt_uint32_t hw_mux_value;
-	rt_uint32_t sw_mux_value;
-	rt_uint32_t reg_offset;
-	rt_uint32_t reg_mask;
+//#define MUX_LEVEL_1       (1)
+//#define MUX_LEVEL_2       (2)
+//#define MAX_MUX_LEVEL MUX_LEVEL_2
+//  rt_uint32_t lev;
+#define HAS_MUX             (0)
+#define HAS_NO_MUX          (1)
+    rt_uint32_t mux_flag;
+    rt_uint32_t hw_mux_value;
+    rt_uint32_t sw_mux_value;
+    rt_uint32_t reg_offset;
+    rt_uint32_t reg_mask;
 };
 
 struct fh_clk_gate{
 
-#define HAS_GATE			(0)
-#define HAS_NO_GATE			(1)
-	rt_uint32_t gate_flag;
-#define CLK_UNGATE			(0)
-#define CLK_GATE			(1)
-	//rt_uint32_t	hw_status;
-	rt_uint32_t	sw_status;
-	//rt_uint32_t value;
+#define HAS_GATE            (0)
+#define HAS_NO_GATE         (1)
+    rt_uint32_t gate_flag;
+#define CLK_UNGATE          (0)
+#define CLK_GATE            (1)
+    //rt_uint32_t   hw_status;
+    rt_uint32_t sw_status;
+    //rt_uint32_t value;
 
-	rt_uint32_t reg_offset;
-	rt_uint32_t reg_mask;
+    rt_uint32_t reg_offset;
+    rt_uint32_t reg_mask;
 
 };
 
@@ -234,7 +234,7 @@ struct fh_clk_gate{
  *
  ***************/
 struct fh_clk_level_1{
-	rt_uint32_t clk_in_out;
+    rt_uint32_t clk_in_out;
 };
 
 
@@ -244,7 +244,7 @@ struct fh_clk_level_1{
  *
  ***************/
 struct fh_clk_level_2{
-	rt_uint32_t clk_in_out;
+    rt_uint32_t clk_in_out;
 };
 
 /***************
@@ -253,19 +253,19 @@ struct fh_clk_level_2{
  *
  ***************/
 struct fh_clk_level_3_ddr{
-	//rt_uint32_t mux_level;
+    //rt_uint32_t mux_level;
 
-	struct fh_clk_mux mux[2];
-	struct fh_clk_gate gate;
-	struct fh_clk_div div;
+    struct fh_clk_mux mux[2];
+    struct fh_clk_gate gate;
+    struct fh_clk_div div;
 };
 
 struct fh_clk_level_3_sdc{
-#define DIFF_REFERENCE				(0x80000000)
+#define DIFF_REFERENCE              (0x80000000)
 
-	rt_uint32_t phase_diff;
-	rt_uint32_t reg_offset;
-	rt_uint32_t reg_mask;
+    rt_uint32_t phase_diff;
+    rt_uint32_t reg_offset;
+    rt_uint32_t reg_mask;
 
 };
 
@@ -274,26 +274,26 @@ struct fh_clk_level_3_gmac{
 };
 
 struct fh_clk_level_3_normal{
-	struct fh_clk_mux mux;
-	struct fh_clk_gate gate;
-	struct fh_clk_div div;
+    struct fh_clk_mux mux;
+    struct fh_clk_gate gate;
+    struct fh_clk_div div;
 };
 
 
 struct fh_clk_level_3 {
 
-#define LEVEL_PERI_NORMAL		(0x301)
-#define LEVEL_PERI_DDR			(0x302)
-#define LEVEL_PERI_SDC			(0x303)
-#define LEVEL_PERI_GMAC			(0x304)
-	rt_uint32_t peri_flag;
-	union
-	{
-		struct fh_clk_level_3_ddr ddr;
-		struct fh_clk_level_3_sdc sdc;
-		struct fh_clk_level_3_gmac gmac;
-		struct fh_clk_level_3_normal normal;
-	}obj;
+#define LEVEL_PERI_NORMAL       (0x301)
+#define LEVEL_PERI_DDR          (0x302)
+#define LEVEL_PERI_SDC          (0x303)
+#define LEVEL_PERI_GMAC         (0x304)
+    rt_uint32_t peri_flag;
+    union
+    {
+        struct fh_clk_level_3_ddr ddr;
+        struct fh_clk_level_3_sdc sdc;
+        struct fh_clk_level_3_gmac gmac;
+        struct fh_clk_level_3_normal normal;
+    }obj;
 
 };
 
@@ -301,34 +301,34 @@ struct fh_clk_level_3 {
 
 
 struct fh_clk {
-	char *name;
-#define LEVEL_CRYSTAL			(0x100)
-#define LEVEL_PLL				(0x200)
-#define LEVEL_PERIPHERAL		(0x300)
-	rt_uint32_t level;
+    char *name;
+#define LEVEL_CRYSTAL           (0x100)
+#define LEVEL_PLL               (0x200)
+#define LEVEL_PERIPHERAL        (0x300)
+    rt_uint32_t level;
 
-#define ROOT_NODE			(RT_NULL)
-	struct fh_clk *parent;
+#define ROOT_NODE           (RT_NULL)
+    struct fh_clk *parent;
 
-	union
-	{
-		struct fh_clk_level_1 crystal;
-		struct fh_clk_level_2 pll;
-		struct fh_clk_level_3 peri;
-	}clk;
+    union
+    {
+        struct fh_clk_level_1 crystal;
+        struct fh_clk_level_2 pll;
+        struct fh_clk_level_3 peri;
+    }clk;
 
-	rt_uint32_t clk_out_rate;
-#define CLK_HAS_NO_GATE				(0x80000000)
-	rt_uint32_t gate;
+    rt_uint32_t clk_out_rate;
+#define CLK_HAS_NO_GATE             (0x80000000)
+    rt_uint32_t gate;
 
-	clk_update update_func;
+    clk_update update_func;
 
-	//struct fh_clk_tree *p_tree;
+    //struct fh_clk_tree *p_tree;
 };
 
 struct fh_clk_tree{
-	rt_uint32_t c_base_addr;
-	struct fh_clk **clk_head;
+    rt_uint32_t c_base_addr;
+    struct fh_clk **clk_head;
 };
 
 
@@ -340,105 +340,105 @@ struct fh_clk_tree{
  *
  *
  ********/
-#define CRYSTAL_HZ			(24000000)
+#define CRYSTAL_HZ          (24000000)
 struct fh_clk clk_in = {
-	.name = "clk_in",
-	.level = LEVEL_CRYSTAL,
-	.parent = ROOT_NODE,
-	.clk.crystal.clk_in_out = CRYSTAL_HZ,
-	//.clk_out_rate = clk_in.clk.crystal.clk_in_out,
-	.clk_out_rate = CRYSTAL_HZ,
-	.update_func = clk_in_update,
+    .name = "clk_in",
+    .level = LEVEL_CRYSTAL,
+    .parent = ROOT_NODE,
+    .clk.crystal.clk_in_out = CRYSTAL_HZ,
+    //.clk_out_rate = clk_in.clk.crystal.clk_in_out,
+    .clk_out_rate = CRYSTAL_HZ,
+    .update_func = clk_in_update,
 };
 
 
 
-#define CIS_PCLK_HZ			(108000000)
+#define CIS_PCLK_HZ         (108000000)
 struct fh_clk cis_pclk = {
-	.name = "cis_pclk",
-	.level = LEVEL_CRYSTAL,
-	.parent = ROOT_NODE,
-	.clk.crystal.clk_in_out = CIS_PCLK_HZ,
-	//.clk_out_rate = clk_in.clk.crystal.clk_in_out,
-	.clk_out_rate = CIS_PCLK_HZ,
-	.update_func = cis_pclk_update,
+    .name = "cis_pclk",
+    .level = LEVEL_CRYSTAL,
+    .parent = ROOT_NODE,
+    .clk.crystal.clk_in_out = CIS_PCLK_HZ,
+    //.clk_out_rate = clk_in.clk.crystal.clk_in_out,
+    .clk_out_rate = CIS_PCLK_HZ,
+    .update_func = cis_pclk_update,
 };
 
 
-#define PLL0_HZ				(864000000)
+#define PLL0_HZ             (864000000)
 struct fh_clk pll0 = {
-	.name = "pll0",
-	.level = LEVEL_PLL,
-	.parent = &clk_in,
-	.clk.crystal.clk_in_out = PLL0_HZ,
-	//.clk_out_rate = pll0.clk.crystal.clk_in_out,
-	.clk_out_rate = PLL0_HZ,
-	.update_func = pll0_clk_update,
+    .name = "pll0",
+    .level = LEVEL_PLL,
+    .parent = &clk_in,
+    .clk.crystal.clk_in_out = PLL0_HZ,
+    //.clk_out_rate = pll0.clk.crystal.clk_in_out,
+    .clk_out_rate = PLL0_HZ,
+    .update_func = pll0_clk_update,
 };
 
 
-#define PLL1_HZ				(600000000)
+#define PLL1_HZ             (600000000)
 struct fh_clk pll1 = {
-	.name = "pll1",
-	.level = LEVEL_PLL,
-	.parent = &clk_in,
-	.clk.crystal.clk_in_out = PLL1_HZ,
-	.clk_out_rate  = PLL1_HZ,
-	.update_func = pll1_clk_update,
+    .name = "pll1",
+    .level = LEVEL_PLL,
+    .parent = &clk_in,
+    .clk.crystal.clk_in_out = PLL1_HZ,
+    .clk_out_rate  = PLL1_HZ,
+    .update_func = pll1_clk_update,
 
 };
 
 
 //NEED_CAUTION   parent not fix...
 static struct fh_clk ddr_clk_normal = {
-	.name = "ddr_normal",
-	.level = LEVEL_PERIPHERAL,
-	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_DDR,
-	//0:xtal_clk
-	//1:pll0_clk
-#define MUX0_XTAL_CLK				(0)
-#define MUX0_PLL0_CLK				(1)
+    .name = "ddr_normal",
+    .level = LEVEL_PERIPHERAL,
+    //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_DDR,
+    //0:xtal_clk
+    //1:pll0_clk
+#define MUX0_XTAL_CLK               (0)
+#define MUX0_PLL0_CLK               (1)
 
-	.clk.peri.obj.ddr.mux[0].reg_offset = REG_PMU_SYS_CTRL,
-	.clk.peri.obj.ddr.mux[0].reg_mask = 1<<0,
+    .clk.peri.obj.ddr.mux[0].reg_offset = REG_PMU_SYS_CTRL,
+    .clk.peri.obj.ddr.mux[0].reg_mask = 1<<0,
 
-	//0:pll0 clk  default 864/2M
-	//1:pll1 clk  default 600M
-#define MUX1_PLL0_CLK				(0)
-#define MUX1_PLL1_CLK				(1)
-	.clk.peri.obj.ddr.mux[1].reg_offset = REG_PMU_CLK_SEL,
-	.clk.peri.obj.ddr.mux[1].reg_mask = 1<<24,
+    //0:pll0 clk  default 864/2M
+    //1:pll1 clk  default 600M
+#define MUX1_PLL0_CLK               (0)
+#define MUX1_PLL1_CLK               (1)
+    .clk.peri.obj.ddr.mux[1].reg_offset = REG_PMU_CLK_SEL,
+    .clk.peri.obj.ddr.mux[1].reg_mask = 1<<24,
 
-	//gate
-	//.clk.peri.obj.ddr.gate.enable_status = CLK_ENABLE,
+    //gate
+    //.clk.peri.obj.ddr.gate.enable_status = CLK_ENABLE,
 
 #ifdef FH_CLK_GATE_DEFAULT
-	.clk.peri.obj.ddr.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
+    .clk.peri.obj.ddr.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.ddr.gate.sw_status = CLK_UNGATE,
+    .clk.peri.obj.ddr.gate.sw_status = CLK_UNGATE,
 #endif
-	.clk.peri.obj.ddr.gate.gate_flag = HAS_GATE,
-	.clk.peri.obj.ddr.gate.reg_offset = REG_PMU_CLK_GATE,
-	.clk.peri.obj.ddr.gate.reg_mask = MCLK_GATE,
+    .clk.peri.obj.ddr.gate.gate_flag = HAS_GATE,
+    .clk.peri.obj.ddr.gate.reg_offset = REG_PMU_CLK_GATE,
+    .clk.peri.obj.ddr.gate.reg_mask = MCLK_GATE,
 
 
 
-	//div
-	//clk in maybe cry or pll
-	.clk.peri.obj.ddr.div.div_flag = DIV_ENABLE,
-	//.clk.peri.obj.ddr.div.pdiv_value = 2,
+    //div
+    //clk in maybe cry or pll
+    .clk.peri.obj.ddr.div.div_flag = DIV_ENABLE,
+    //.clk.peri.obj.ddr.div.pdiv_value = 2,
 
 #ifdef FH_CLK_DIV_DEFAULT
-	.clk.peri.obj.ddr.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
+    .clk.peri.obj.ddr.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.ddr.div.sw_div_value = 1,
+    .clk.peri.obj.ddr.div.sw_div_value = 1,
 #endif
-	.clk.peri.obj.ddr.div.sw_div_multi =1,
-	.clk.peri.obj.ddr.div.reg_offset = REG_PMU_CLK_DIV1,
-	.clk.peri.obj.ddr.div.reg_mask = 0xff <<0,
+    .clk.peri.obj.ddr.div.sw_div_multi =1,
+    .clk.peri.obj.ddr.div.reg_offset = REG_PMU_CLK_DIV1,
+    .clk.peri.obj.ddr.div.reg_mask = 0xff <<0,
 
-	.update_func = ddr_clk_update,
+    .update_func = ddr_clk_update,
 };
 
 
@@ -450,121 +450,121 @@ static struct fh_clk ddr_clk_normal = {
 
 //NEED_CAUTION   parent not fix...
 static struct fh_clk ddr_clk_div2 = {
-	.name = "ddr_div2",
-	.level = LEVEL_PERIPHERAL,
-	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_DDR,
-	//0:xtal_clk
-	//1:pll0_clk
-	.clk.peri.obj.ddr.mux[0].reg_offset = REG_PMU_SYS_CTRL,
-	.clk.peri.obj.ddr.mux[0].reg_mask = 1<<0,
+    .name = "ddr_div2",
+    .level = LEVEL_PERIPHERAL,
+    //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_DDR,
+    //0:xtal_clk
+    //1:pll0_clk
+    .clk.peri.obj.ddr.mux[0].reg_offset = REG_PMU_SYS_CTRL,
+    .clk.peri.obj.ddr.mux[0].reg_mask = 1<<0,
 
-	//0:pll0 clk  default 864/2M
-	//1:pll1 clk  default 600M
-	.clk.peri.obj.ddr.mux[1].reg_offset = REG_PMU_CLK_SEL,
-	.clk.peri.obj.ddr.mux[1].reg_mask = 1<<24,
+    //0:pll0 clk  default 864/2M
+    //1:pll1 clk  default 600M
+    .clk.peri.obj.ddr.mux[1].reg_offset = REG_PMU_CLK_SEL,
+    .clk.peri.obj.ddr.mux[1].reg_mask = 1<<24,
 
-	//gate
-	//.clk.peri.obj.ddr.gate.enable_status = CLK_ENABLE,
+    //gate
+    //.clk.peri.obj.ddr.gate.enable_status = CLK_ENABLE,
 
 #ifdef FH_CLK_GATE_DEFAULT
-	.clk.peri.obj.ddr.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
+    .clk.peri.obj.ddr.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.ddr.gate.sw_status = CLK_UNGATE,
+    .clk.peri.obj.ddr.gate.sw_status = CLK_UNGATE,
 #endif
-	.clk.peri.obj.ddr.gate.gate_flag = HAS_GATE,
-	.clk.peri.obj.ddr.gate.reg_offset = REG_PMU_CLK_GATE,
-	.clk.peri.obj.ddr.gate.reg_mask = MCLK_GATE,
+    .clk.peri.obj.ddr.gate.gate_flag = HAS_GATE,
+    .clk.peri.obj.ddr.gate.reg_offset = REG_PMU_CLK_GATE,
+    .clk.peri.obj.ddr.gate.reg_mask = MCLK_GATE,
 
-	//div
-	//clk in maybe cry or pll
-	.clk.peri.obj.ddr.div.div_flag = PRE_DIV_ENABLE | DIV_ENABLE,
-	.clk.peri.obj.ddr.div.pdiv_value = 2,
+    //div
+    //clk in maybe cry or pll
+    .clk.peri.obj.ddr.div.div_flag = PRE_DIV_ENABLE | DIV_ENABLE,
+    .clk.peri.obj.ddr.div.pdiv_value = 2,
 #ifdef FH_CLK_DIV_DEFAULT
-	.clk.peri.obj.ddr.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
+    .clk.peri.obj.ddr.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.ddr.div.sw_div_value = 1,
+    .clk.peri.obj.ddr.div.sw_div_value = 1,
 #endif
-	.clk.peri.obj.ddr.div.sw_div_multi =1,
-	.clk.peri.obj.ddr.div.reg_offset = REG_PMU_CLK_DIV1,
-	.clk.peri.obj.ddr.div.reg_mask = 0xff <<0,
+    .clk.peri.obj.ddr.div.sw_div_multi =1,
+    .clk.peri.obj.ddr.div.reg_offset = REG_PMU_CLK_DIV1,
+    .clk.peri.obj.ddr.div.reg_mask = 0xff <<0,
 
 
-	.update_func = ddr_clk_update,
+    .update_func = ddr_clk_update,
 };
 
 
 
 static struct fh_clk cpu_fclk = {
-	.name = "cpu_fclk",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_NORMAL,
+    .name = "cpu_fclk",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
 
-	//0:xtal_clk
-	//1:pll0_clk
-	.clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL,
-	.clk.peri.obj.normal.mux.reg_mask = 1<<0,
+    //0:xtal_clk
+    //1:pll0_clk
+    .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL,
+    .clk.peri.obj.normal.mux.reg_mask = 1<<0,
 
-	//gate
-	.clk.peri.obj.normal.gate.gate_flag = HAS_NO_GATE,
-	//.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
-	//.clk.peri.obj.normal.gate.reg_mask = CPU_FCLK0_GATE,
+    //gate
+    .clk.peri.obj.normal.gate.gate_flag = HAS_NO_GATE,
+    //.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
+    //.clk.peri.obj.normal.gate.reg_mask = CPU_FCLK0_GATE,
 
 
-	//div
-	.clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
+    //div
+    .clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
 
 #ifdef FH_CLK_DIV_DEFAULT
-	.clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
+    .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.div.sw_div_value = 0,
+    .clk.peri.obj.normal.div.sw_div_value = 0,
 #endif
 
-	.clk.peri.obj.normal.div.sw_div_multi =1,
-	.clk.peri.obj.normal.div.reg_offset =REG_PMU_CLK_DIV0,
-	.clk.peri.obj.normal.div.reg_mask = 0xff << 0,
+    .clk.peri.obj.normal.div.sw_div_multi =1,
+    .clk.peri.obj.normal.div.reg_offset =REG_PMU_CLK_DIV0,
+    .clk.peri.obj.normal.div.reg_mask = 0xff << 0,
 
-	.update_func = fclk_update,
+    .update_func = fclk_update,
 
 };
 
 
 //NEED_CAUTION   parent not fix...
 static struct fh_clk cpu_aclk = {
-	.name = "cpu_aclk",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_NORMAL,
+    .name = "cpu_aclk",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
 
-	//0:xtal_clk
-	//1:pll0_clk
-	.clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
-//	.clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL,
-//	.clk.peri.obj.normal.mux.reg_mask = 1<<0,
+    //0:xtal_clk
+    //1:pll0_clk
+    .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
+//  .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL,
+//  .clk.peri.obj.normal.mux.reg_mask = 1<<0,
 
-	//gate
-	.clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
+    //gate
+    .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
 
 
 #ifdef FH_CLK_GATE_DEFAULT
-	.clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
+    .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
+    .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
 #endif
 
 
-	.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
-	.clk.peri.obj.normal.gate.reg_mask = CPU_FCLK0_GATE,
+    .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
+    .clk.peri.obj.normal.gate.reg_mask = CPU_FCLK0_GATE,
 
 
-	//div
-	.clk.peri.obj.normal.div.div_flag = PRE_DIV_ENABLE,
-	.clk.peri.obj.normal.div.pdiv_value = 2,
-//	.clk.peri.obj.normal.div.reg_offset =REG_PMU_CLK_DIV0,
-//	.clk.peri.obj.normal.div.reg_mask = 0xff << 0,
+    //div
+    .clk.peri.obj.normal.div.div_flag = PRE_DIV_ENABLE,
+    .clk.peri.obj.normal.div.pdiv_value = 2,
+//  .clk.peri.obj.normal.div.reg_offset =REG_PMU_CLK_DIV0,
+//  .clk.peri.obj.normal.div.reg_mask = 0xff << 0,
 
-	.update_func = aclk_update,
+    .update_func = aclk_update,
 
 };
 
@@ -572,282 +572,282 @@ static struct fh_clk cpu_aclk = {
 
 
 static struct fh_clk cpu_hclk = {
-	.name = "cpu_hclk",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_NORMAL,
+    .name = "cpu_hclk",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
 
-	//0:xtal_clk
-	//1:pll0_clk
-	.clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL,
-	.clk.peri.obj.normal.mux.reg_mask = 1<<0,
+    //0:xtal_clk
+    //1:pll0_clk
+    .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL,
+    .clk.peri.obj.normal.mux.reg_mask = 1<<0,
 
-	//gate
-	.clk.peri.obj.normal.gate.gate_flag = HAS_NO_GATE,
-	//.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
-	//.clk.peri.obj.normal.gate.reg_mask = CPU_FCLK0_GATE,
+    //gate
+    .clk.peri.obj.normal.gate.gate_flag = HAS_NO_GATE,
+    //.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
+    //.clk.peri.obj.normal.gate.reg_mask = CPU_FCLK0_GATE,
 
 
-	//div
-	.clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
+    //div
+    .clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
 
 #ifdef FH_CLK_DIV_DEFAULT
-	.clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
+    .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.div.sw_div_value = 1,
+    .clk.peri.obj.normal.div.sw_div_value = 1,
 #endif
-	.clk.peri.obj.normal.div.sw_div_multi =1,
-	.clk.peri.obj.normal.div.reg_offset =REG_PMU_CLK_DIV0,
-	.clk.peri.obj.normal.div.reg_mask = 0xff << 16,
+    .clk.peri.obj.normal.div.sw_div_multi =1,
+    .clk.peri.obj.normal.div.reg_offset =REG_PMU_CLK_DIV0,
+    .clk.peri.obj.normal.div.reg_mask = 0xff << 16,
 
-	.update_func = hclk_update,
+    .update_func = hclk_update,
 };
 //NEED_CAUTION   parent not fix...
 
 static struct fh_clk cpu_pclk = {
-	.name = "cpu_pclk",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_NORMAL,
+    .name = "cpu_pclk",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
 
-	//0:xtal_clk
-	//1:pll0_clk
-	.clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
+    //0:xtal_clk
+    //1:pll0_clk
+    .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
 
-	//gate
-	.clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
+    //gate
+    .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
 
 
 #ifdef FH_CLK_GATE_DEFAULT
-	.clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
+    .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
+    .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
 #endif
 
 
-	.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
-	.clk.peri.obj.normal.gate.reg_mask = HCLK_GATE,
+    .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
+    .clk.peri.obj.normal.gate.reg_mask = HCLK_GATE,
 
 
-	//div
-	.clk.peri.obj.normal.div.div_flag = PRE_DIV_ENABLE,
-	.clk.peri.obj.normal.div.pdiv_value = 2,
-//	.clk.peri.obj.normal.div.reg_offset =REG_PMU_CLK_DIV0,
-//	.clk.peri.obj.normal.div.reg_mask = 0xff << 0,
+    //div
+    .clk.peri.obj.normal.div.div_flag = PRE_DIV_ENABLE,
+    .clk.peri.obj.normal.div.pdiv_value = 2,
+//  .clk.peri.obj.normal.div.reg_offset =REG_PMU_CLK_DIV0,
+//  .clk.peri.obj.normal.div.reg_mask = 0xff << 0,
 
-	.update_func = pclk_update,
+    .update_func = pclk_update,
 
 };
 
 
 //NEED_CAUTION   parent not fix...
 static struct fh_clk isp_aclk = {
-	.name = "isp_aclk",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_NORMAL,
+    .name = "isp_aclk",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
 
-	//0:xtal_clk
-	//1:pll0_clk
-	.clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL,
-	.clk.peri.obj.normal.mux.reg_mask = 1<<0,
+    //0:xtal_clk
+    //1:pll0_clk
+    .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL,
+    .clk.peri.obj.normal.mux.reg_mask = 1<<0,
 
-	//gate
-	.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
-	.clk.peri.obj.normal.gate.reg_mask = ISP_ACLK_GATE,
-	.clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
+    //gate
+    .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
+    .clk.peri.obj.normal.gate.reg_mask = ISP_ACLK_GATE,
+    .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
 
 #ifdef FH_CLK_GATE_DEFAULT
-	.clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
+    .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
+    .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
 #endif
 
-	//div
-	.clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
-	.clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV0,
-	.clk.peri.obj.normal.div.reg_mask = 0x03 << 8,
-	.clk.peri.obj.normal.div.sw_div_multi =1,
+    //div
+    .clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
+    .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV0,
+    .clk.peri.obj.normal.div.reg_mask = 0x03 << 8,
+    .clk.peri.obj.normal.div.sw_div_multi =1,
 
 
 #ifdef FH_CLK_DIV_DEFAULT
-	.clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
+    .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.div.sw_div_value = 1,
+    .clk.peri.obj.normal.div.sw_div_value = 1,
 #endif
 
-	.update_func = isp_aclk_update,
+    .update_func = isp_aclk_update,
 
 };
 
 //
 ////NEED_CAUTION   parent not fix...
 static struct fh_clk vcu_clk = {
-	.name = "vcu_clk",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_NORMAL,
+    .name = "vcu_clk",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
 
-	//0:xtal_clk
-	//1:pll0_clk
-	.clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL,
-	.clk.peri.obj.normal.mux.reg_mask = 1<<0,
+    //0:xtal_clk
+    //1:pll0_clk
+    .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL,
+    .clk.peri.obj.normal.mux.reg_mask = 1<<0,
 
-	//gate
-	.clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
-	.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
-	.clk.peri.obj.normal.gate.reg_mask = VCU_CLK_GATE,
+    //gate
+    .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
+    .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
+    .clk.peri.obj.normal.gate.reg_mask = VCU_CLK_GATE,
 
 #ifdef FH_CLK_GATE_DEFAULT
-	.clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
+    .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
+    .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
 #endif
 
 
-	//div
-	.clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
-	.clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV0,
-	.clk.peri.obj.normal.div.reg_mask = 0x03 << 24,
-	.clk.peri.obj.normal.div.sw_div_multi =1,
+    //div
+    .clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
+    .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV0,
+    .clk.peri.obj.normal.div.reg_mask = 0x03 << 24,
+    .clk.peri.obj.normal.div.sw_div_multi =1,
 
 
 
 #ifdef FH_CLK_DIV_DEFAULT
-	.clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
+    .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.div.sw_div_value = 1,
+    .clk.peri.obj.normal.div.sw_div_value = 1,
 #endif
 
 
-	.update_func = vcu_clk_update,
+    .update_func = vcu_clk_update,
 
 };
 
 static struct fh_clk vou_clk = {
-	.name = "vou_clk",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_NORMAL,
+    .name = "vou_clk",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
 
-	//0:xtal_clk
-	//1:pll0_clk
-	.clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL,
-	.clk.peri.obj.normal.mux.reg_mask = 1<<0,
+    //0:xtal_clk
+    //1:pll0_clk
+    .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL,
+    .clk.peri.obj.normal.mux.reg_mask = 1<<0,
 
-	//gate
-	.clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
-	.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
-	.clk.peri.obj.normal.gate.reg_mask = VOU_CLK_GATE,
+    //gate
+    .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
+    .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
+    .clk.peri.obj.normal.gate.reg_mask = VOU_CLK_GATE,
 
 
 #ifdef FH_CLK_GATE_DEFAULT
-	.clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
+    .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
+    .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
 #endif
 
 
-	//div
-	.clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
-	.clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV1,
-	.clk.peri.obj.normal.div.reg_mask = 0x3f << 8,
-	.clk.peri.obj.normal.div.sw_div_multi =1,
+    //div
+    .clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
+    .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV1,
+    .clk.peri.obj.normal.div.reg_mask = 0x3f << 8,
+    .clk.peri.obj.normal.div.sw_div_multi =1,
 
 
 #ifdef FH_CLK_DIV_DEFAULT
-	.clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
+    .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.div.sw_div_value = 1,
+    .clk.peri.obj.normal.div.sw_div_value = 1,
 #endif
 
-	.update_func = vou_clk_update,
+    .update_func = vou_clk_update,
 };
 
 
 
 static struct fh_clk mipi_p32_clk = {
-	.name = "mipi_p32_clk",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_NORMAL,
+    .name = "mipi_p32_clk",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
 
-	//0:xtal_clk
-	//1:pll0_clk
-	.clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL,
-	.clk.peri.obj.normal.mux.reg_mask = 1<<0,
+    //0:xtal_clk
+    //1:pll0_clk
+    .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL,
+    .clk.peri.obj.normal.mux.reg_mask = 1<<0,
 
-	//gate
-	.clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
-	.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
-	.clk.peri.obj.normal.gate.reg_mask = MIPI_P32_CLK_GATE,
+    //gate
+    .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
+    .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
+    .clk.peri.obj.normal.gate.reg_mask = MIPI_P32_CLK_GATE,
 
 
 #ifdef FH_CLK_GATE_DEFAULT
-	.clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
+    .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
+    .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
 #endif
 
-	//div
-	.clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
-	.clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV2,
-	.clk.peri.obj.normal.div.reg_mask = 0x0f << 16,
-	.clk.peri.obj.normal.div.sw_div_multi =1,
+    //div
+    .clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
+    .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV2,
+    .clk.peri.obj.normal.div.reg_mask = 0x0f << 16,
+    .clk.peri.obj.normal.div.sw_div_multi =1,
 
 
 #ifdef FH_CLK_DIV_DEFAULT
-	.clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
+    .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.div.sw_div_value = 1,
+    .clk.peri.obj.normal.div.sw_div_value = 1,
 #endif
 
 
-	.update_func = mipi_p32_clk_update,
+    .update_func = mipi_p32_clk_update,
 
 };
 
 
 
 static struct fh_clk cis_clk_out = {
-	.name = "cis_clk_out",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_NORMAL,
+    .name = "cis_clk_out",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
 
-	//0:xtal_clk
-	//1:pll0_clk
-	.clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL,
-	.clk.peri.obj.normal.mux.reg_mask = 1<<0,
+    //0:xtal_clk
+    //1:pll0_clk
+    .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL,
+    .clk.peri.obj.normal.mux.reg_mask = 1<<0,
 
-	//gate
-	.clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
-	.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
-	.clk.peri.obj.normal.gate.reg_mask = CIS_CLK_OUT_GATE,
+    //gate
+    .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
+    .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
+    .clk.peri.obj.normal.gate.reg_mask = CIS_CLK_OUT_GATE,
 
 
 #ifdef FH_CLK_GATE_DEFAULT
-	.clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
+    .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
+    .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
 #endif
 
 
 
-	//div
-	.clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
-	.clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV1,
-	.clk.peri.obj.normal.div.reg_mask = 0xff << 16,
-	.clk.peri.obj.normal.div.sw_div_multi =1,
+    //div
+    .clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
+    .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV1,
+    .clk.peri.obj.normal.div.reg_mask = 0xff << 16,
+    .clk.peri.obj.normal.div.sw_div_multi =1,
 
 
 #ifdef FH_CLK_DIV_DEFAULT
-	.clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
+    .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.div.sw_div_value = 3,
+    .clk.peri.obj.normal.div.sw_div_value = 3,
 #endif
 
-	.update_func = cis_clk_out_update,
+    .update_func = cis_clk_out_update,
 
 };
 
@@ -855,43 +855,43 @@ static struct fh_clk cis_clk_out = {
 
 
 static struct fh_clk pts_clk = {
-	.name = "pts_clk",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_NORMAL,
+    .name = "pts_clk",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
 
-	//0:xtal_clk
-	//1:pll0_clk
-	.clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL,
-	.clk.peri.obj.normal.mux.reg_mask = 1<<0,
+    //0:xtal_clk
+    //1:pll0_clk
+    .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL,
+    .clk.peri.obj.normal.mux.reg_mask = 1<<0,
 
-	//gate
-	.clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
-	.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
-	.clk.peri.obj.normal.gate.reg_mask = PTS_CLK_GATE,
+    //gate
+    .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
+    .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
+    .clk.peri.obj.normal.gate.reg_mask = PTS_CLK_GATE,
 
 
 #ifdef FH_CLK_GATE_DEFAULT
-	.clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
+    .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
+    .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
 #endif
 
 
-	//div
-	.clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
-	.clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV2,
-	.clk.peri.obj.normal.div.reg_mask = 0xff << 0,
-	.clk.peri.obj.normal.div.sw_div_multi =1,
+    //div
+    .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
+    .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV2,
+    .clk.peri.obj.normal.div.reg_mask = 0xff << 0,
+    .clk.peri.obj.normal.div.sw_div_multi =1,
 #ifdef FH_CLK_DIV_DEFAULT
-	.clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
+    .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.div.sw_div_value = 35,
+    .clk.peri.obj.normal.div.sw_div_value = 35,
 #endif
 
-	.clk.peri.obj.normal.div.pdiv_value = 12,
+    .clk.peri.obj.normal.div.pdiv_value = 12,
 
-	.update_func = pts_update,
+    .update_func = pts_update,
 
 };
 
@@ -899,31 +899,31 @@ static struct fh_clk pts_clk = {
 
 
 static struct fh_clk mipi_pix_clk = {
-	.name = "mipi_pix_clk_i",
-	.level = LEVEL_PERIPHERAL,
-	.clk.peri.peri_flag = LEVEL_PERI_NORMAL,
+    .name = "mipi_pix_clk_i",
+    .level = LEVEL_PERIPHERAL,
+    .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
 
-	//0:xtal_clk
-	//1:pll0_clk
-	.clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL,
-	.clk.peri.obj.normal.mux.reg_mask = 1<<0,
+    //0:xtal_clk
+    //1:pll0_clk
+    .clk.peri.obj.normal.mux.reg_offset = REG_PMU_SYS_CTRL,
+    .clk.peri.obj.normal.mux.reg_mask = 1<<0,
 
-	//gate
-	.clk.peri.obj.normal.gate.gate_flag = HAS_NO_GATE,
+    //gate
+    .clk.peri.obj.normal.gate.gate_flag = HAS_NO_GATE,
 
 
-	//div
-	.clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
-	.clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV2,
-	.clk.peri.obj.normal.div.reg_mask = 0x0f << 24,
-	.clk.peri.obj.normal.div.sw_div_multi =1,
+    //div
+    .clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
+    .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV2,
+    .clk.peri.obj.normal.div.reg_mask = 0x0f << 24,
+    .clk.peri.obj.normal.div.sw_div_multi =1,
 #ifdef FH_CLK_DIV_DEFAULT
-	.clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
+    .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.div.sw_div_value = 3,
+    .clk.peri.obj.normal.div.sw_div_value = 3,
 #endif
 
-	.update_func = mipi_pix_clk_update,
+    .update_func = mipi_pix_clk_update,
 
 
 };
@@ -931,37 +931,37 @@ static struct fh_clk mipi_pix_clk = {
 
 
 static struct fh_clk pix_clk = {
-	.name = "pix_clk",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_NORMAL,
+    .name = "pix_clk",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
 
-	//0:xtal_clk
-	//1:pll0_clk
-#define CIS_PIX_CLK				(0)
-#define CIS_PIX_CLK_OPPOSITE	(1)
-#define MIPI_PIX_CLK			(2)
+    //0:xtal_clk
+    //1:pll0_clk
+#define CIS_PIX_CLK             (0)
+#define CIS_PIX_CLK_OPPOSITE    (1)
+#define MIPI_PIX_CLK            (2)
 
-	.clk.peri.obj.normal.mux.reg_offset = REG_PMU_CLK_SEL,
-	.clk.peri.obj.normal.mux.reg_mask = 3<<4,
+    .clk.peri.obj.normal.mux.reg_offset = REG_PMU_CLK_SEL,
+    .clk.peri.obj.normal.mux.reg_mask = 3<<4,
 
-	//gate
-	.clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
-	.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
-	.clk.peri.obj.normal.gate.reg_mask = PIX_CLK_GATE,
+    //gate
+    .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
+    .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
+    .clk.peri.obj.normal.gate.reg_mask = PIX_CLK_GATE,
 
 #ifdef FH_CLK_GATE_DEFAULT
-	.clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
+    .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
+    .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
 #endif
 
-	//div
-	.clk.peri.obj.normal.div.div_flag = 0,
+    //div
+    .clk.peri.obj.normal.div.div_flag = 0,
 
 
 
-	.update_func = pix_update,
+    .update_func = pix_update,
 
 };
 
@@ -971,41 +971,41 @@ static struct fh_clk pix_clk = {
 
 
 static struct fh_clk spi0_clk = {
-	.name = "spi0_clk",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_NORMAL,
+    .name = "spi0_clk",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
 
 
 
-	.clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
+    .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
 
 
-	//gate
-	.clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
-	.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
-	.clk.peri.obj.normal.gate.reg_mask = SPI0_CLK_GATE,
+    //gate
+    .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
+    .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
+    .clk.peri.obj.normal.gate.reg_mask = SPI0_CLK_GATE,
 
 #ifdef FH_CLK_GATE_DEFAULT
-	.clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
+    .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
+    .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
 #endif
 
-	//div
-	.clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
-	.clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3,
-	.clk.peri.obj.normal.div.reg_mask = 0xff << 0,
-	.clk.peri.obj.normal.div.sw_div_multi =1,
+    //div
+    .clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
+    .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3,
+    .clk.peri.obj.normal.div.reg_mask = 0xff << 0,
+    .clk.peri.obj.normal.div.sw_div_multi =1,
 
 
 #ifdef FH_CLK_DIV_DEFAULT
-	.clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
+    .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.div.sw_div_value = 11,
+    .clk.peri.obj.normal.div.sw_div_value = 11,
 #endif
 
-	.update_func = spi0_clk_update,
+    .update_func = spi0_clk_update,
 
 };
 
@@ -1013,46 +1013,46 @@ static struct fh_clk spi0_clk = {
 
 
 static struct fh_clk spi1_clk = {
-	.name = "spi1_clk",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_NORMAL,
+    .name = "spi1_clk",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
 
 
-	.clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
-	//gate
-	.clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
-	.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
-	.clk.peri.obj.normal.gate.reg_mask = SPI1_CLK_GATE,
+    .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
+    //gate
+    .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
+    .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
+    .clk.peri.obj.normal.gate.reg_mask = SPI1_CLK_GATE,
 
 
 #ifdef FH_CLK_GATE_DEFAULT
-	.clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
+    .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
+    .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
 #endif
 
 
 
-	//div
-	.clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
-	.clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3,
-	.clk.peri.obj.normal.div.reg_mask = 0xff << 16,
-	.clk.peri.obj.normal.div.sw_div_multi =1,
+    //div
+    .clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
+    .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3,
+    .clk.peri.obj.normal.div.reg_mask = 0xff << 16,
+    .clk.peri.obj.normal.div.sw_div_multi =1,
 
 
 
 #ifdef FH_CLK_DIV_DEFAULT
-	.clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
+    .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.div.sw_div_value = 11,
+    .clk.peri.obj.normal.div.sw_div_value = 11,
 #endif
 
 #ifdef RT_USING_SPI1
-	.clk.peri.obj.normal.div.sw_div_value = 11,
+    .clk.peri.obj.normal.div.sw_div_value = 11,
 #endif
 
-	.update_func = spi1_clk_update,
+    .update_func = spi1_clk_update,
 
 };
 
@@ -1060,200 +1060,200 @@ static struct fh_clk spi1_clk = {
 
 
 static struct fh_clk mipi_dphy_clk20m = {
-	.name = "mipi_dphy_clk20m",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_NORMAL,
+    .name = "mipi_dphy_clk20m",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
 
-	.clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
+    .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
 
-	//gate
-	.clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
-	.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
-	.clk.peri.obj.normal.gate.reg_mask = MIPI_DPHY_CLK20M_GATE,
+    //gate
+    .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
+    .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
+    .clk.peri.obj.normal.gate.reg_mask = MIPI_DPHY_CLK20M_GATE,
 
 #ifdef FH_CLK_GATE_DEFAULT
-	.clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
+    .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
+    .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
 #endif
 
 
 
 
-	//div
-	.clk.peri.obj.normal.div.div_flag = PRE_DIV_ENABLE,
-//	.clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3,
-//	.clk.peri.obj.normal.div.reg_mask = 0xff << 16,
-	.clk.peri.obj.normal.div.sw_div_multi =1,
-	.clk.peri.obj.normal.div.pdiv_value = 30,
-//	.clk.peri.obj.normal.div.sw_div_value = 11,
+    //div
+    .clk.peri.obj.normal.div.div_flag = PRE_DIV_ENABLE,
+//  .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3,
+//  .clk.peri.obj.normal.div.reg_mask = 0xff << 16,
+    .clk.peri.obj.normal.div.sw_div_multi =1,
+    .clk.peri.obj.normal.div.pdiv_value = 30,
+//  .clk.peri.obj.normal.div.sw_div_value = 11,
 
-	.update_func = mipi_dphy_clk20m_update,
+    .update_func = mipi_dphy_clk20m_update,
 };
 
 
 
 static struct fh_clk i2c0_clk = {
-	.name = "i2c0_clk",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_NORMAL,
+    .name = "i2c0_clk",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
 
-	.clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
+    .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
 
-	//gate
-	.clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
-	.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
-	.clk.peri.obj.normal.gate.reg_mask = I2C0_CLK_GATE,
+    //gate
+    .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
+    .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
+    .clk.peri.obj.normal.gate.reg_mask = I2C0_CLK_GATE,
 
 
 #ifdef FH_CLK_GATE_DEFAULT
-	.clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
+    .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
+    .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
 #endif
 
 
 
 
-	//div
-	.clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
-	.clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV4,
-	.clk.peri.obj.normal.div.reg_mask = 0x3f << 16,
-	.clk.peri.obj.normal.div.sw_div_multi = 1,
+    //div
+    .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
+    .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV4,
+    .clk.peri.obj.normal.div.reg_mask = 0x3f << 16,
+    .clk.peri.obj.normal.div.sw_div_multi = 1,
 
 #ifdef FH_CLK_DIV_DEFAULT
-	.clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
+    .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.div.sw_div_value = 1,
+    .clk.peri.obj.normal.div.sw_div_value = 1,
 #endif
 
-	.clk.peri.obj.normal.div.pdiv_value = 20,
+    .clk.peri.obj.normal.div.pdiv_value = 20,
 
-	.update_func = i2c0_clk_update,
+    .update_func = i2c0_clk_update,
 
 };
 
 
 static struct fh_clk i2c1_clk = {
-	.name = "i2c1_clk",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_NORMAL,
+    .name = "i2c1_clk",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
 
-	.clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
+    .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
 
-	//gate
-	.clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
-	.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
-	.clk.peri.obj.normal.gate.reg_mask = I2C1_CLK_GATE,
+    //gate
+    .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
+    .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
+    .clk.peri.obj.normal.gate.reg_mask = I2C1_CLK_GATE,
 
 #ifdef FH_CLK_GATE_DEFAULT
-	.clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
+    .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
+    .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
 #endif
 
 
-	//div
-	.clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
-	.clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV4,
-	.clk.peri.obj.normal.div.reg_mask = 0x3f << 24,
-	.clk.peri.obj.normal.div.sw_div_multi = 1,
+    //div
+    .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
+    .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV4,
+    .clk.peri.obj.normal.div.reg_mask = 0x3f << 24,
+    .clk.peri.obj.normal.div.sw_div_multi = 1,
 
 #ifdef FH_CLK_DIV_DEFAULT
-	.clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
+    .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.div.sw_div_value = 1,
+    .clk.peri.obj.normal.div.sw_div_value = 1,
 #endif
-	.clk.peri.obj.normal.div.pdiv_value = 20,
+    .clk.peri.obj.normal.div.pdiv_value = 20,
 
 
-	.update_func = i2c1_clk_update,
+    .update_func = i2c1_clk_update,
 };
 
 
 static struct fh_clk uart0_clk = {
-	.name = "uart0_clk",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_NORMAL,
+    .name = "uart0_clk",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
 
-	.clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
+    .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
 
-	//gate
-	.clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
-	.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
-	.clk.peri.obj.normal.gate.reg_mask = UART0_CLK_GATE,
+    //gate
+    .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
+    .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
+    .clk.peri.obj.normal.gate.reg_mask = UART0_CLK_GATE,
 
 #ifdef FH_CLK_GATE_DEFAULT
-	.clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
+    .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
+    .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
 #endif
 
 
 
-	//div
-	.clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
-	.clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV4,
-	.clk.peri.obj.normal.div.reg_mask = 0x1f << 0,
-	.clk.peri.obj.normal.div.sw_div_multi = 1,
+    //div
+    .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
+    .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV4,
+    .clk.peri.obj.normal.div.reg_mask = 0x1f << 0,
+    .clk.peri.obj.normal.div.sw_div_multi = 1,
 
 #ifdef FH_CLK_DIV_DEFAULT
-	.clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
+    .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.div.sw_div_value = 1,
+    .clk.peri.obj.normal.div.sw_div_value = 1,
 #endif
 
 
-	.clk.peri.obj.normal.div.pdiv_value = 10,
+    .clk.peri.obj.normal.div.pdiv_value = 10,
 
 
-	.update_func = uart0_clk_update,
+    .update_func = uart0_clk_update,
 
 };
 
 static struct fh_clk uart1_clk = {
-	.name = "uart1_clk",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_NORMAL,
+    .name = "uart1_clk",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
 
-	.clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
+    .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
 
-	//gate
-	.clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
-	.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
-	.clk.peri.obj.normal.gate.reg_mask = UART1_CLK_GATE,
+    //gate
+    .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
+    .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
+    .clk.peri.obj.normal.gate.reg_mask = UART1_CLK_GATE,
 
 #ifdef FH_CLK_GATE_DEFAULT
-	.clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
+    .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
+    .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
 #endif
 
 
 
 
-	//div
-	.clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
-	.clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV4,
-	.clk.peri.obj.normal.div.reg_mask = 0x1f << 8,
-	.clk.peri.obj.normal.div.sw_div_multi = 1,
+    //div
+    .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
+    .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV4,
+    .clk.peri.obj.normal.div.reg_mask = 0x1f << 8,
+    .clk.peri.obj.normal.div.sw_div_multi = 1,
 
 #ifdef FH_CLK_DIV_DEFAULT
-	.clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
+    .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.div.sw_div_value = 1,
+    .clk.peri.obj.normal.div.sw_div_value = 1,
 #endif
 
 
 
-	.clk.peri.obj.normal.div.pdiv_value = 10,
+    .clk.peri.obj.normal.div.pdiv_value = 10,
 
-	.update_func = uart1_clk_update,
+    .update_func = uart1_clk_update,
 
 };
 
@@ -1261,131 +1261,131 @@ static struct fh_clk uart1_clk = {
 
 
 static struct fh_clk pwm_clk = {
-	.name = "pwm_clk",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_NORMAL,
+    .name = "pwm_clk",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
 
-	.clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
+    .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
 
-	//gate
-	.clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
-	.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
-	.clk.peri.obj.normal.gate.reg_mask = PWM_CLK_GATE,
+    //gate
+    .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
+    .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
+    .clk.peri.obj.normal.gate.reg_mask = PWM_CLK_GATE,
 
 
 #ifdef FH_CLK_GATE_DEFAULT
-	.clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
+    .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
+    .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
 #endif
 
 
 
 
-	//div
-	.clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
-	.clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV5,
-	.clk.peri.obj.normal.div.reg_mask = 0x3f << 0,
-	.clk.peri.obj.normal.div.sw_div_multi = 1,
+    //div
+    .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
+    .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV5,
+    .clk.peri.obj.normal.div.reg_mask = 0x3f << 0,
+    .clk.peri.obj.normal.div.sw_div_multi = 1,
 
 #ifdef FH_CLK_DIV_DEFAULT
-	.clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
+    .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.div.sw_div_value = 29,
+    .clk.peri.obj.normal.div.sw_div_value = 29,
 #endif
 
 
 
-	.clk.peri.obj.normal.div.pdiv_value = 20,
+    .clk.peri.obj.normal.div.pdiv_value = 20,
 
-	.update_func = pwm_clk_update,
+    .update_func = pwm_clk_update,
 };
 
 
 
 static struct fh_clk time0_clk = {
-	.name = "time0_clk",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_NORMAL,
+    .name = "time0_clk",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
 
-	.clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
-	//gate
-	.clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
-	.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
-	.clk.peri.obj.normal.gate.reg_mask = TMR0_CLK_GATE,
+    .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
+    //gate
+    .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
+    .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
+    .clk.peri.obj.normal.gate.reg_mask = TMR0_CLK_GATE,
 
 
 #ifdef FH_CLK_GATE_DEFAULT
-	.clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
+    .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
+    .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
 #endif
 
 
 
-	//div
-	.clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
-	.clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV5,
-	.clk.peri.obj.normal.div.reg_mask = 0x3f << 16,
-	.clk.peri.obj.normal.div.sw_div_multi = 1,
+    //div
+    .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
+    .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV5,
+    .clk.peri.obj.normal.div.reg_mask = 0x3f << 16,
+    .clk.peri.obj.normal.div.sw_div_multi = 1,
 
 #ifdef FH_CLK_DIV_DEFAULT
-	.clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
+    .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.div.sw_div_value = 29,
+    .clk.peri.obj.normal.div.sw_div_value = 29,
 #endif
 
 
 
-	.clk.peri.obj.normal.div.pdiv_value = 20,
+    .clk.peri.obj.normal.div.pdiv_value = 20,
 
 
-	.update_func = time0_clk_update,
+    .update_func = time0_clk_update,
 
 };
 
 
 static struct fh_clk time1_clk = {
-	.name = "time1_clk",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
+    .name = "time1_clk",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
 
-	.clk.peri.peri_flag = LEVEL_PERI_NORMAL,
+    .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
 
-	.clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
+    .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
 
-	//gate
-	.clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
-	.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
-	.clk.peri.obj.normal.gate.reg_mask = TMR1_CLK_GATE,
+    //gate
+    .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
+    .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
+    .clk.peri.obj.normal.gate.reg_mask = TMR1_CLK_GATE,
 
 #ifdef FH_CLK_GATE_DEFAULT
-	.clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
+    .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
+    .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
 #endif
 
 
 
 
-	//div
-	.clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
-	.clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV5,
-	.clk.peri.obj.normal.div.reg_mask = 0x3f << 24,
-	.clk.peri.obj.normal.div.sw_div_multi = 1,
+    //div
+    .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
+    .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV5,
+    .clk.peri.obj.normal.div.reg_mask = 0x3f << 24,
+    .clk.peri.obj.normal.div.sw_div_multi = 1,
 
 #ifdef FH_CLK_DIV_DEFAULT
-	.clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
+    .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.div.sw_div_value = 29,
+    .clk.peri.obj.normal.div.sw_div_value = 29,
 #endif
 
 
-	.clk.peri.obj.normal.div.pdiv_value = 20,
+    .clk.peri.obj.normal.div.pdiv_value = 20,
 
-	.update_func = time1_clk_update,
+    .update_func = time1_clk_update,
 
 };
 
@@ -1393,227 +1393,227 @@ static struct fh_clk time1_clk = {
 
 
 static struct fh_clk sadc_clk = {
-	.name = "sadc_clk",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_NORMAL,
+    .name = "sadc_clk",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
 
-	.clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
+    .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
 
-	//gate
-	.clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
-	.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
-	.clk.peri.obj.normal.gate.reg_mask = SADC_CLK_GATE,
+    //gate
+    .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
+    .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
+    .clk.peri.obj.normal.gate.reg_mask = SADC_CLK_GATE,
 
 #ifdef FH_CLK_GATE_DEFAULT
-	.clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
+    .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
+    .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
 #endif
 
 
 
-	//div
-	.clk.peri.obj.normal.div.div_flag = PRE_DIV_ENABLE,
-	.clk.peri.obj.normal.div.sw_div_multi = 1,
-	.clk.peri.obj.normal.div.pdiv_value = 120,
+    //div
+    .clk.peri.obj.normal.div.div_flag = PRE_DIV_ENABLE,
+    .clk.peri.obj.normal.div.sw_div_multi = 1,
+    .clk.peri.obj.normal.div.pdiv_value = 120,
 
-	.update_func = sadc_clk_update,
+    .update_func = sadc_clk_update,
 
 };
 
 
 
 static struct fh_clk sdc0_clk2x = {
-	.name = "sdc0_clk2x",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_NORMAL,
+    .name = "sdc0_clk2x",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
 
-	.clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
+    .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
 
-	//gate
-	.clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
+    //gate
+    .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
 
-	.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
-	.clk.peri.obj.normal.gate.reg_mask = SDC0_CLK_GATE,
+    .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
+    .clk.peri.obj.normal.gate.reg_mask = SDC0_CLK_GATE,
 
 #ifdef FH_CLK_GATE_DEFAULT
-	.clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
+    .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
+    .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
 #endif
 
-	//div
-	.clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
-	.clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3,
-	.clk.peri.obj.normal.div.reg_mask = 0x0f << 8,
-	.clk.peri.obj.normal.div.sw_div_multi = 1,
+    //div
+    .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
+    .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3,
+    .clk.peri.obj.normal.div.reg_mask = 0x0f << 8,
+    .clk.peri.obj.normal.div.sw_div_multi = 1,
 
 #ifdef FH_CLK_DIV_DEFAULT
-	.clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
+    .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.div.sw_div_value = 5,
+    .clk.peri.obj.normal.div.sw_div_value = 5,
 #endif
 
 
-	.clk.peri.obj.normal.div.pdiv_value = 2,
+    .clk.peri.obj.normal.div.pdiv_value = 2,
 
-	.update_func = sdc0_clk2x_update,
+    .update_func = sdc0_clk2x_update,
 
 };
 
 
 
 static struct fh_clk sdc0_clk = {
-	.name = "sdc0_clk",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_SDC,
-	.clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0 | DIFF_REFERENCE,
-//	.clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL,
-//	.clk.peri.obj.sdc.reg_mask = 0x0,
+    .name = "sdc0_clk",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_SDC,
+    .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0 | DIFF_REFERENCE,
+//  .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL,
+//  .clk.peri.obj.sdc.reg_mask = 0x0,
 
-	.update_func = sdc0_clk_update,
+    .update_func = sdc0_clk_update,
 
 };
 
 
 
 static struct fh_clk sdc0_clk_out = {
-	.name = "sdc0_clk_out",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_SDC,
-	.clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0,
-//	.clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL,
-//	.clk.peri.obj.sdc.reg_mask = 0x0,
+    .name = "sdc0_clk_out",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_SDC,
+    .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0,
+//  .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL,
+//  .clk.peri.obj.sdc.reg_mask = 0x0,
 
-	.update_func = sdc0_clk_out_update,
+    .update_func = sdc0_clk_out_update,
 };
 
 
 
 static struct fh_clk sdc0_clk_sample = {
-	.name = "sdc0_clk_sample",
-	.level = LEVEL_PERIPHERAL,
+    .name = "sdc0_clk_sample",
+    .level = LEVEL_PERIPHERAL,
 
-	.clk.peri.peri_flag = LEVEL_PERI_SDC,
-	.clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0,
-	.clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL,
-	.clk.peri.obj.sdc.reg_mask = 3<16,
+    .clk.peri.peri_flag = LEVEL_PERI_SDC,
+    .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0,
+    .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL,
+    .clk.peri.obj.sdc.reg_mask = 3<16,
 
 
-	.update_func = sdc0_clk_sample_update,
+    .update_func = sdc0_clk_sample_update,
 };
 
 static struct fh_clk sdc0_clk_drive = {
-	.name = "sdc0_clk_drive",
-	.level = LEVEL_PERIPHERAL,
+    .name = "sdc0_clk_drive",
+    .level = LEVEL_PERIPHERAL,
 
-	.clk.peri.peri_flag = LEVEL_PERI_SDC,
-	.clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0,
-	.clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL,
-	.clk.peri.obj.sdc.reg_mask = 3<20,
+    .clk.peri.peri_flag = LEVEL_PERI_SDC,
+    .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0,
+    .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL,
+    .clk.peri.obj.sdc.reg_mask = 3<20,
 
 
-	.update_func = sdc0_clk_drv_update,
+    .update_func = sdc0_clk_drv_update,
 };
 
 
 
 
 static struct fh_clk sdc1_clk2x = {
-	.name = "sdc1_clk2x",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_NORMAL,
+    .name = "sdc1_clk2x",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
 
-	.clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
+    .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
 
-	//gate
-	.clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
-	.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
-	.clk.peri.obj.normal.gate.reg_mask = SDC1_CLK_GATE,
+    //gate
+    .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
+    .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
+    .clk.peri.obj.normal.gate.reg_mask = SDC1_CLK_GATE,
 
 #ifdef FH_CLK_GATE_DEFAULT
-	.clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
+    .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
+    .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
 #endif
 
 
 
-	//div
-	.clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
-	.clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3,
-	.clk.peri.obj.normal.div.reg_mask = 0x0f << 24,
-	.clk.peri.obj.normal.div.sw_div_multi = 1,
+    //div
+    .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
+    .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV3,
+    .clk.peri.obj.normal.div.reg_mask = 0x0f << 24,
+    .clk.peri.obj.normal.div.sw_div_multi = 1,
 #ifdef FH_CLK_DIV_DEFAULT
-	.clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
+    .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.div.sw_div_value = 5,
+    .clk.peri.obj.normal.div.sw_div_value = 5,
 #endif
 
 
-	.clk.peri.obj.normal.div.pdiv_value = 2,
+    .clk.peri.obj.normal.div.pdiv_value = 2,
 
 
-	.update_func = sdc1_clk2x_update,
+    .update_func = sdc1_clk2x_update,
 };
 
 
 
 static struct fh_clk sdc1_clk = {
-	.name = "sdc1_clk",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_SDC,
-	.clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0 | DIFF_REFERENCE,
-//	.clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL,
-//	.clk.peri.obj.sdc.reg_mask = 0x0,
+    .name = "sdc1_clk",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_SDC,
+    .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0 | DIFF_REFERENCE,
+//  .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL,
+//  .clk.peri.obj.sdc.reg_mask = 0x0,
 
-	.update_func = sdc1_clk_update,
+    .update_func = sdc1_clk_update,
 };
 
 
 
 static struct fh_clk sdc1_clk_out = {
-	.name = "sdc1_clk_out",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_SDC,
-	.clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0,
-//	.clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL,
-//	.clk.peri.obj.sdc.reg_mask = 0x0,
+    .name = "sdc1_clk_out",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_SDC,
+    .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0,
+//  .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL,
+//  .clk.peri.obj.sdc.reg_mask = 0x0,
 
-	.update_func = sdc1_clk_out_update,
+    .update_func = sdc1_clk_out_update,
 };
 
 
 
 static struct fh_clk sdc1_clk_sample = {
-	.name = "sdc1_clk_sample",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_SDC,
-	.clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0,
-	.clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL,
-	.clk.peri.obj.sdc.reg_mask = 3<8,
+    .name = "sdc1_clk_sample",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_SDC,
+    .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0,
+    .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL,
+    .clk.peri.obj.sdc.reg_mask = 3<8,
 
-	.update_func = sdc1_clk_sample_update,
+    .update_func = sdc1_clk_sample_update,
 };
 
 static struct fh_clk sdc1_clk_drive = {
-	.name = "sdc1_clk_drive",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_SDC,
-	.clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0,
-	.clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL,
-	.clk.peri.obj.sdc.reg_mask = 3<12,
+    .name = "sdc1_clk_drive",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_SDC,
+    .clk.peri.obj.sdc.phase_diff = DIFF_SDC_REFCLK_0,
+    .clk.peri.obj.sdc.reg_offset = REG_PMU_CLK_SEL,
+    .clk.peri.obj.sdc.reg_mask = 3<12,
 
-	.update_func = sdc1_clk_drv_update,
+    .update_func = sdc1_clk_drv_update,
 };
 
 
@@ -1621,826 +1621,826 @@ static struct fh_clk sdc1_clk_drive = {
 
 
 static struct fh_clk eth_ref_clk = {
-	.name = "eth_ref_clk",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_NORMAL,
+    .name = "eth_ref_clk",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
 
-	.clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
+    .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
 
-	//gate
-	.clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
-	.clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
-	.clk.peri.obj.normal.gate.reg_mask = ETH_REF_CLK_GATE,
+    //gate
+    .clk.peri.obj.normal.gate.gate_flag = HAS_GATE,
+    .clk.peri.obj.normal.gate.reg_offset = REG_PMU_CLK_GATE,
+    .clk.peri.obj.normal.gate.reg_mask = ETH_REF_CLK_GATE,
 
 
 #ifdef FH_CLK_GATE_DEFAULT
-	.clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
+    .clk.peri.obj.normal.gate.sw_status = FH_CLK_GATE_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
+    .clk.peri.obj.normal.gate.sw_status = CLK_UNGATE,
 #endif
 
 
-	//div
-	.clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
-	.clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV6,
-	.clk.peri.obj.normal.div.reg_mask = 0x0f << 24,
-	.clk.peri.obj.normal.div.sw_div_multi = 1,
+    //div
+    .clk.peri.obj.normal.div.div_flag = DIV_ENABLE | PRE_DIV_ENABLE,
+    .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV6,
+    .clk.peri.obj.normal.div.reg_mask = 0x0f << 24,
+    .clk.peri.obj.normal.div.sw_div_multi = 1,
 
 
 #ifdef FH_CLK_DIV_DEFAULT
-	.clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
+    .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.div.sw_div_value = 5,
+    .clk.peri.obj.normal.div.sw_div_value = 5,
 #endif
 
 
 
 
-	.clk.peri.obj.normal.div.pdiv_value = 2,
+    .clk.peri.obj.normal.div.pdiv_value = 2,
 
 
-	.update_func = eth_ref_clk_update,
+    .update_func = eth_ref_clk_update,
 };
 
 
 
 
 static struct fh_clk wdt_clk = {
-	.name = "wdt_clk",
-	.level = LEVEL_PERIPHERAL,
-//	//.parent = &clk_in,
-	.clk.peri.peri_flag = LEVEL_PERI_NORMAL,
-	.clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
+    .name = "wdt_clk",
+    .level = LEVEL_PERIPHERAL,
+//  //.parent = &clk_in,
+    .clk.peri.peri_flag = LEVEL_PERI_NORMAL,
+    .clk.peri.obj.normal.mux.mux_flag = HAS_NO_MUX,
 
-	//gate
-	.clk.peri.obj.normal.gate.gate_flag = HAS_NO_GATE,
+    //gate
+    .clk.peri.obj.normal.gate.gate_flag = HAS_NO_GATE,
 
 
-	//div
-	.clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
-	.clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV5,
-	.clk.peri.obj.normal.div.reg_mask = 0x3f << 8,
-	.clk.peri.obj.normal.div.sw_div_multi = 1,
+    //div
+    .clk.peri.obj.normal.div.div_flag = DIV_ENABLE,
+    .clk.peri.obj.normal.div.reg_offset = REG_PMU_CLK_DIV5,
+    .clk.peri.obj.normal.div.reg_mask = 0x3f << 8,
+    .clk.peri.obj.normal.div.sw_div_multi = 1,
 
 
 
 #ifdef FH_CLK_DIV_DEFAULT
-	.clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
+    .clk.peri.obj.normal.div.sw_div_value = FH_CLK_DIV_DEFAULT_VALUE,
 #else
-	.clk.peri.obj.normal.div.sw_div_value = 29,
+    .clk.peri.obj.normal.div.sw_div_value = 29,
 #endif
 
 
-	.update_func = wdt_clk_update,
+    .update_func = wdt_clk_update,
 };
 
 
 
 struct fh_clk *fh_clk_array[] = {
-		&clk_in,
-		&cis_pclk,
-		&pll0,
-		&pll1,
-		&ddr_clk_normal,
-		&ddr_clk_div2,
-		&cpu_fclk,
-		&cpu_aclk,
-		&cpu_hclk,
-		&cpu_pclk,
-		&isp_aclk,
-		&vcu_clk,
-		&vou_clk,
-		&mipi_p32_clk,
-		&cis_clk_out,
-		&pts_clk,
-		&mipi_pix_clk,
-		&pix_clk,
+        &clk_in,
+        &cis_pclk,
+        &pll0,
+        &pll1,
+        &ddr_clk_normal,
+        &ddr_clk_div2,
+        &cpu_fclk,
+        &cpu_aclk,
+        &cpu_hclk,
+        &cpu_pclk,
+        &isp_aclk,
+        &vcu_clk,
+        &vou_clk,
+        &mipi_p32_clk,
+        &cis_clk_out,
+        &pts_clk,
+        &mipi_pix_clk,
+        &pix_clk,
 
-		//pll1
-		&sdc0_clk2x,
-		&sdc0_clk,
-		&sdc0_clk_out,
-		&sdc0_clk_sample,
-		&sdc0_clk_drive,
+        //pll1
+        &sdc0_clk2x,
+        &sdc0_clk,
+        &sdc0_clk_out,
+        &sdc0_clk_sample,
+        &sdc0_clk_drive,
 
-		&sdc1_clk2x,
-		&sdc1_clk,
-		&sdc1_clk_out,
-		&sdc1_clk_sample,
-		&sdc1_clk_drive,
+        &sdc1_clk2x,
+        &sdc1_clk,
+        &sdc1_clk_out,
+        &sdc1_clk_sample,
+        &sdc1_clk_drive,
 
 
-		&spi0_clk,
-		&spi1_clk,
-		&mipi_dphy_clk20m,
-		&i2c0_clk,
-		&i2c1_clk,
-		&uart0_clk,
-		&uart1_clk,
-		&pwm_clk,
-		&time0_clk,
-		&time1_clk,
-		&sadc_clk,
-		ð_ref_clk,
+        &spi0_clk,
+        &spi1_clk,
+        &mipi_dphy_clk20m,
+        &i2c0_clk,
+        &i2c1_clk,
+        &uart0_clk,
+        &uart1_clk,
+        &pwm_clk,
+        &time0_clk,
+        &time1_clk,
+        &sadc_clk,
+        ð_ref_clk,
 
-		&wdt_clk,
+        &wdt_clk,
 
 
 };
 
 static inline rt_int32_t wrap_read_reg(rt_uint32_t offset, rt_uint32_t mask,
-		rt_uint32_t *value)
+        rt_uint32_t *value)
 {
-	rt_uint32_t temp_v, temp_shift;
+    rt_uint32_t temp_v, temp_shift;
 
-	/*	if(fh_pmu_status() == PMU_STATUS_CLOSE)
-	 return -1;*/
-	temp_v = FH_TIMER_READL(offset);
-	temp_v &= mask;
-	temp_shift = __rt_ffs(mask);
-	temp_v = temp_v >> (temp_shift - 1);
-	*value = temp_v;
-	return 0;
+    /*  if(fh_pmu_status() == PMU_STATUS_CLOSE)
+     return -1;*/
+    temp_v = FH_TIMER_READL(offset);
+    temp_v &= mask;
+    temp_shift = __rt_ffs(mask);
+    temp_v = temp_v >> (temp_shift - 1);
+    *value = temp_v;
+    return 0;
 }
 
 static inline rt_int32_t wrap_write_reg(rt_uint32_t offset, rt_uint32_t mask,
-		rt_uint32_t value)
+        rt_uint32_t value)
 {
-	rt_uint32_t temp_v, temp_shift;
+    rt_uint32_t temp_v, temp_shift;
 
-	/*
-	 if(fh_pmu_status() == PMU_STATUS_CLOSE)
-	 return -1;
-	 */
+    /*
+     if(fh_pmu_status() == PMU_STATUS_CLOSE)
+     return -1;
+     */
 
-	temp_v = FH_TIMER_READL(offset);
-	temp_v &= ~mask;
-	temp_shift = __rt_ffs(mask);
-	temp_v |= value << (temp_shift - 1);
-	FH_TIMER_WRITEL(offset, temp_v);
-	return 0;
+    temp_v = FH_TIMER_READL(offset);
+    temp_v &= ~mask;
+    temp_shift = __rt_ffs(mask);
+    temp_v |= value << (temp_shift - 1);
+    FH_TIMER_WRITEL(offset, temp_v);
+    return 0;
 }
 
 rt_int32_t check_pix_clk_source(rt_uint32_t offset, rt_uint32_t mask,
-		rt_uint32_t *value)
+        rt_uint32_t *value)
 {
-	rt_uint32_t mux0;
-	rt_int32_t ret;
-	ret = wrap_read_reg(offset, mask, &mux0);
+    rt_uint32_t mux0;
+    rt_int32_t ret;
+    ret = wrap_read_reg(offset, mask, &mux0);
 
-	if (ret != 0) {
-		return ret;
-	}
+    if (ret != 0) {
+        return ret;
+    }
 
-	*value = mux0;
-	return 0;
+    *value = mux0;
+    return 0;
 }
 
 rt_int32_t check_xtal_pll0(rt_uint32_t offset, rt_uint32_t mask,
-		rt_uint32_t *value)
+        rt_uint32_t *value)
 {
-	rt_uint32_t mux0;
-	rt_int32_t ret;
-	ret = wrap_read_reg(offset, mask, &mux0);
+    rt_uint32_t mux0;
+    rt_int32_t ret;
+    ret = wrap_read_reg(offset, mask, &mux0);
 
-	if (ret != 0) {
-		return ret;
-	}
-	if (mux0 == MUX0_PLL0_CLK)
-		*value = MUX0_PLL0_CLK;
-	else
-		*value = MUX0_XTAL_CLK;
+    if (ret != 0) {
+        return ret;
+    }
+    if (mux0 == MUX0_PLL0_CLK)
+        *value = MUX0_PLL0_CLK;
+    else
+        *value = MUX0_XTAL_CLK;
 
-	return 0;
+    return 0;
 }
 
 void cal_pll0_prediv(rt_uint32_t *div_flag, rt_uint32_t *pre_value)
 {
 
-	if (!(*div_flag & PRE_DIV_CAL_ALREADY)) {
-		//before has got the prediv value..
-		if (*div_flag & PRE_DIV_ENABLE) {
+    if (!(*div_flag & PRE_DIV_CAL_ALREADY)) {
+        //before has got the prediv value..
+        if (*div_flag & PRE_DIV_ENABLE) {
 
-			*pre_value *= 2;
-		} else {
-			*pre_value = 2;
-		}
-		*div_flag |= PRE_DIV_ENABLE | PRE_DIV_CAL_ALREADY;
-	}
+            *pre_value *= 2;
+        } else {
+            *pre_value = 2;
+        }
+        *div_flag |= PRE_DIV_ENABLE | PRE_DIV_CAL_ALREADY;
+    }
 
 }
 
 rt_int32_t sw_div_process(rt_uint32_t div_flag, rt_uint32_t offset,
-		rt_uint32_t mask, rt_uint32_t *div_value)
+        rt_uint32_t mask, rt_uint32_t *div_value)
 {
 
-	//rt_kprintf("----------div go----------\n");
-	rt_uint32_t div;
-	rt_int32_t ret;
-	if (div_flag & DIV_ENABLE) {
-		ret = wrap_read_reg(offset, mask, &div);
-		if (ret != 0) {
-			return ret;
-		}
+    //rt_kprintf("----------div go----------\n");
+    rt_uint32_t div;
+    rt_int32_t ret;
+    if (div_flag & DIV_ENABLE) {
+        ret = wrap_read_reg(offset, mask, &div);
+        if (ret != 0) {
+            return ret;
+        }
 
 //
-//		rt_kprintf("hw value is %x\n",div);
-//		rt_kprintf("sw value is %x\n",div_value);
+//      rt_kprintf("hw value is %x\n",div);
+//      rt_kprintf("sw value is %x\n",div_value);
 //
-//		rt_kprintf("offset is %x,value :%x\n",offset + 0xf0000000,*(rt_uint32_t*)(offset + 0xf0000000));
-//		rt_kprintf("mask is %x\n",mask);
+//      rt_kprintf("offset is %x,value :%x\n",offset + 0xf0000000,*(rt_uint32_t*)(offset + 0xf0000000));
+//      rt_kprintf("mask is %x\n",mask);
 
-		//if use the hw default value....
+        //if use the hw default value....
 
-		if (*div_value == FH_CLK_DIV_DEFAULT_VALUE) {
-			*div_value = div;
-			return 0;
-		}
+        if (*div_value == FH_CLK_DIV_DEFAULT_VALUE) {
+            *div_value = div;
+            return 0;
+        }
 
-		if (div != *div_value) {
-			ret = wrap_write_reg(offset, mask, *div_value);
-			if (ret != 0) {
-				return ret;
-			}
-		}
-	}
-	//rt_kprintf("----------div done----------\n");
-	return 0;
-	//*div_flag |= PRE_DIV_ENABLE;
+        if (div != *div_value) {
+            ret = wrap_write_reg(offset, mask, *div_value);
+            if (ret != 0) {
+                return ret;
+            }
+        }
+    }
+    //rt_kprintf("----------div done----------\n");
+    return 0;
+    //*div_flag |= PRE_DIV_ENABLE;
 }
 
 void cal_baud_hz(rt_uint32_t clk_in, rt_uint32_t div_flag, rt_uint32_t pre_div,
-		rt_uint32_t div, rt_uint32_t div_multi, rt_uint32_t *baud_out)
+        rt_uint32_t div, rt_uint32_t div_multi, rt_uint32_t *baud_out)
 {
-	//div += 1;
-	if (div_flag & PRE_DIV_ENABLE) {
-		*baud_out = (clk_in / pre_div);
-	} else {
-		*baud_out = clk_in;
-	}
+    //div += 1;
+    if (div_flag & PRE_DIV_ENABLE) {
+        *baud_out = (clk_in / pre_div);
+    } else {
+        *baud_out = clk_in;
+    }
 
-	if (div_flag & DIV_ENABLE) {
-		*baud_out /= ((div + 1) * div_multi);
-	}
+    if (div_flag & DIV_ENABLE) {
+        *baud_out /= ((div + 1) * div_multi);
+    }
 
 }
 
 void cal_baud_div(rt_uint32_t clk_in, rt_uint32_t div_flag, rt_uint32_t pre_div,
-		rt_uint32_t *div, rt_uint32_t div_multi, rt_uint32_t baud_out)
+        rt_uint32_t *div, rt_uint32_t div_multi, rt_uint32_t baud_out)
 {
-	//div += 1;
-	rt_uint32_t temp_baud_hz, temp_baud_div;
+    //div += 1;
+    rt_uint32_t temp_baud_hz, temp_baud_div;
 
-	if (div_flag & DIV_ENABLE) {
-		if (div_flag & PRE_DIV_ENABLE) {
-			temp_baud_hz = (clk_in / pre_div);
-		} else {
-			temp_baud_hz = clk_in;
-		}
-		temp_baud_div = temp_baud_hz / baud_out;
-		*div = temp_baud_div - 1;
-	}
+    if (div_flag & DIV_ENABLE) {
+        if (div_flag & PRE_DIV_ENABLE) {
+            temp_baud_hz = (clk_in / pre_div);
+        } else {
+            temp_baud_hz = clk_in;
+        }
+        temp_baud_div = temp_baud_hz / baud_out;
+        *div = temp_baud_div - 1;
+    }
 
 }
 
 rt_int32_t process_gate(rt_uint32_t gate_flag, rt_uint32_t reg_offset,
-		rt_uint32_t reg_mask, rt_uint32_t *sw_status,
-		rt_uint32_t *pclk_status)
+        rt_uint32_t reg_mask, rt_uint32_t *sw_status,
+        rt_uint32_t *pclk_status)
 {
-	//rt_kprintf("----------gate go----------\n");
-	rt_uint32_t hw_gate;
-	rt_int32_t ret;
-	if (gate_flag == HAS_GATE) {
-		ret = wrap_read_reg(reg_offset, reg_mask, &hw_gate);
-		if (ret != 0) {
-			return ret;
-		}
+    //rt_kprintf("----------gate go----------\n");
+    rt_uint32_t hw_gate;
+    rt_int32_t ret;
+    if (gate_flag == HAS_GATE) {
+        ret = wrap_read_reg(reg_offset, reg_mask, &hw_gate);
+        if (ret != 0) {
+            return ret;
+        }
 
-		if (*sw_status == FH_CLK_GATE_DEFAULT_VALUE) {
-			*sw_status = hw_gate;
-			*pclk_status = *sw_status;
-			return 0;
-		}
+        if (*sw_status == FH_CLK_GATE_DEFAULT_VALUE) {
+            *sw_status = hw_gate;
+            *pclk_status = *sw_status;
+            return 0;
+        }
 
-//		rt_kprintf("gate hw is :%x\n",hw_gate);
-//		rt_kprintf("gate sw is :%x\n",sw_status);
-		if (hw_gate != *sw_status) {
-			//update the gate..
-//			rt_kprintf("gate reg offset is :%x\n",reg_offset);
-//			rt_kprintf("gate reg mask is :%x\n",reg_mask);
-//			rt_kprintf("gate reg write is :%x\n",sw_status);
-			ret = wrap_write_reg(reg_offset, reg_mask, *sw_status);
-			if (ret != 0) {
-				return ret;
-			}
-		}
+//      rt_kprintf("gate hw is :%x\n",hw_gate);
+//      rt_kprintf("gate sw is :%x\n",sw_status);
+        if (hw_gate != *sw_status) {
+            //update the gate..
+//          rt_kprintf("gate reg offset is :%x\n",reg_offset);
+//          rt_kprintf("gate reg mask is :%x\n",reg_mask);
+//          rt_kprintf("gate reg write is :%x\n",sw_status);
+            ret = wrap_write_reg(reg_offset, reg_mask, *sw_status);
+            if (ret != 0) {
+                return ret;
+            }
+        }
 
-		*pclk_status = *sw_status;
-	}
+        *pclk_status = *sw_status;
+    }
 
-	else {
-		*pclk_status |= CLK_HAS_NO_GATE;
-	}
-	//rt_kprintf("---------gate done---------\n");
-	return 0;
+    else {
+        *pclk_status |= CLK_HAS_NO_GATE;
+    }
+    //rt_kprintf("---------gate done---------\n");
+    return 0;
 
 }
 
 void clk_handle(struct fh_clk* p_clk, struct fh_clk *parent)
 {
-	//rt_uint32_t div;
-	//rt_uint32_t sw_gate;
-	rt_uint32_t phase;
-	rt_int32_t ret;
-	p_clk->parent = parent;
-//	switch
-	//fh_clk_debug(p_clk,"----parent----\t ----clk out rate----\n ");
-	if (p_clk->parent)
-		//rt_kprintf("%-8.*s 0x%02x", RT_NAME_MAX, thread->name, thread->current_priority);
-		fh_clk_debug(p_clk, "parent:'%s'\n", p_clk->parent->name);
-	else
-		fh_clk_debug(p_clk, "'root node'\n");
+    //rt_uint32_t div;
+    //rt_uint32_t sw_gate;
+    rt_uint32_t phase;
+    rt_int32_t ret;
+    p_clk->parent = parent;
+//  switch
+    //fh_clk_debug(p_clk,"----parent----\t ----clk out rate----\n ");
+    if (p_clk->parent)
+        //rt_kprintf("%-8.*s 0x%02x", RT_NAME_MAX, thread->name, thread->current_priority);
+        fh_clk_debug(p_clk, "parent:'%s'\n", p_clk->parent->name);
+    else
+        fh_clk_debug(p_clk, "'root node'\n");
 
-	switch (p_clk->level) {
+    switch (p_clk->level) {
 
-	case LEVEL_CRYSTAL:
-		//fh_clk_debug(p_clk,"clk out:%d\n",p_clk->clk_out_rate);
-		break;
-	case LEVEL_PLL:
-		//fh_clk_debug(p_clk,"%d\n",p_clk->clk_out_rate);
-		break;
-	case LEVEL_PERIPHERAL:
+    case LEVEL_CRYSTAL:
+        //fh_clk_debug(p_clk,"clk out:%d\n",p_clk->clk_out_rate);
+        break;
+    case LEVEL_PLL:
+        //fh_clk_debug(p_clk,"%d\n",p_clk->clk_out_rate);
+        break;
+    case LEVEL_PERIPHERAL:
 
-		switch (p_clk->clk.peri.peri_flag) {
+        switch (p_clk->clk.peri.peri_flag) {
 
-		case LEVEL_PERI_NORMAL:
-			//div = p_clk->clk.peri.obj.normal.div.sw_div_value;
-			ret =
-					sw_div_process(
-							p_clk->clk.peri.obj.normal.div.div_flag,
-							p_clk->clk.peri.obj.normal.div.reg_offset,
-							p_clk->clk.peri.obj.normal.div.reg_mask,
-							&p_clk->clk.peri.obj.normal.div.sw_div_value);
+        case LEVEL_PERI_NORMAL:
+            //div = p_clk->clk.peri.obj.normal.div.sw_div_value;
+            ret =
+                    sw_div_process(
+                            p_clk->clk.peri.obj.normal.div.div_flag,
+                            p_clk->clk.peri.obj.normal.div.reg_offset,
+                            p_clk->clk.peri.obj.normal.div.reg_mask,
+                            &p_clk->clk.peri.obj.normal.div.sw_div_value);
 
-			if (ret != 0) {
-				fh_clk_err(p_clk,
-						"div process failed.error no:%x\n",
-						ret);
-				break;
-			}
+            if (ret != 0) {
+                fh_clk_err(p_clk,
+                        "div process failed.error no:%x\n",
+                        ret);
+                break;
+            }
 
-			//fh_clk_debug(p_clk,"hw div is %d\n",p_clk->clk.peri.obj.ddr.div.hw_div_value);
-//			fh_clk_debug(p_clk,"sw div is %d\n",p_clk->clk.peri.obj.normal.div.sw_div_value);
-//			fh_clk_debug(p_clk,"pre div is %d\n",p_clk->clk.peri.obj.normal.div.pdiv_value);
-//			fh_clk_debug(p_clk,"clk in is %d\n",p_clk->parent->clk_out_rate);
-//			fh_clk_debug(p_clk,"peri flag is %x\n",p_clk->clk.peri.obj.normal.div.div_flag);
-			//hw will self add 1..
+            //fh_clk_debug(p_clk,"hw div is %d\n",p_clk->clk.peri.obj.ddr.div.hw_div_value);
+//          fh_clk_debug(p_clk,"sw div is %d\n",p_clk->clk.peri.obj.normal.div.sw_div_value);
+//          fh_clk_debug(p_clk,"pre div is %d\n",p_clk->clk.peri.obj.normal.div.pdiv_value);
+//          fh_clk_debug(p_clk,"clk in is %d\n",p_clk->parent->clk_out_rate);
+//          fh_clk_debug(p_clk,"peri flag is %x\n",p_clk->clk.peri.obj.normal.div.div_flag);
+            //hw will self add 1..
 
-			cal_baud_hz(p_clk->parent->clk_out_rate,
-					p_clk->clk.peri.obj.normal.div.div_flag,
-					p_clk->clk.peri.obj.normal.div.pdiv_value,
-					p_clk->clk.peri.obj.normal.div.sw_div_value,
-					p_clk->clk.peri.obj.normal.div.sw_div_multi,
-					&p_clk->clk_out_rate);
+            cal_baud_hz(p_clk->parent->clk_out_rate,
+                    p_clk->clk.peri.obj.normal.div.div_flag,
+                    p_clk->clk.peri.obj.normal.div.pdiv_value,
+                    p_clk->clk.peri.obj.normal.div.sw_div_value,
+                    p_clk->clk.peri.obj.normal.div.sw_div_multi,
+                    &p_clk->clk_out_rate);
 
-			//fh_clk_debug_no_handle("%d\n",p_clk->clk_out_rate);
-			//fix the gate..
-			//sw_gate = p_clk->clk.peri.obj.normal.gate.sw_status;
-			ret =
-					process_gate(
-							p_clk->clk.peri.obj.normal.gate.gate_flag,
-							p_clk->clk.peri.obj.normal.gate.reg_offset,
-							p_clk->clk.peri.obj.normal.gate.reg_mask,
-							&p_clk->clk.peri.obj.normal.gate.sw_status,
-							&p_clk->gate);
+            //fh_clk_debug_no_handle("%d\n",p_clk->clk_out_rate);
+            //fix the gate..
+            //sw_gate = p_clk->clk.peri.obj.normal.gate.sw_status;
+            ret =
+                    process_gate(
+                            p_clk->clk.peri.obj.normal.gate.gate_flag,
+                            p_clk->clk.peri.obj.normal.gate.reg_offset,
+                            p_clk->clk.peri.obj.normal.gate.reg_mask,
+                            &p_clk->clk.peri.obj.normal.gate.sw_status,
+                            &p_clk->gate);
 
-			if (ret != 0) {
-				fh_clk_err(p_clk,
-						"gate process failed.error no:%x\n",
-						ret);
-				break;
-			}
+            if (ret != 0) {
+                fh_clk_err(p_clk,
+                        "gate process failed.error no:%x\n",
+                        ret);
+                break;
+            }
 
-			break;
-		case LEVEL_PERI_DDR:
-			//rt_uint32_t mux0,mux1;
-			//div = p_clk->clk.peri.obj.ddr.div.sw_div_value;
+            break;
+        case LEVEL_PERI_DDR:
+            //rt_uint32_t mux0,mux1;
+            //div = p_clk->clk.peri.obj.ddr.div.sw_div_value;
 
-			ret =
-					sw_div_process(
-							p_clk->clk.peri.obj.ddr.div.div_flag,
-							p_clk->clk.peri.obj.ddr.div.reg_offset,
-							p_clk->clk.peri.obj.ddr.div.reg_mask,
-							&p_clk->clk.peri.obj.ddr.div.sw_div_value);
+            ret =
+                    sw_div_process(
+                            p_clk->clk.peri.obj.ddr.div.div_flag,
+                            p_clk->clk.peri.obj.ddr.div.reg_offset,
+                            p_clk->clk.peri.obj.ddr.div.reg_mask,
+                            &p_clk->clk.peri.obj.ddr.div.sw_div_value);
 
-			if (ret != 0) {
-				fh_clk_err(p_clk,
-						"div process failed.error no:%x\n",
-						ret);
-				break;
-			}
+            if (ret != 0) {
+                fh_clk_err(p_clk,
+                        "div process failed.error no:%x\n",
+                        ret);
+                break;
+            }
 
-//			fh_clk_debug(p_clk,"sw div is %d\n",p_clk->clk.peri.obj.ddr.div.sw_div_value);
-//			fh_clk_debug(p_clk,"pre div is %d\n",p_clk->clk.peri.obj.ddr.div.pdiv_value);
-//			fh_clk_debug(p_clk,"clk in is %d\n",p_clk->parent->clk_out_rate);
-//			fh_clk_debug(p_clk,"peri flag is %x\n",p_clk->clk.peri.obj.ddr.div.div_flag);
+//          fh_clk_debug(p_clk,"sw div is %d\n",p_clk->clk.peri.obj.ddr.div.sw_div_value);
+//          fh_clk_debug(p_clk,"pre div is %d\n",p_clk->clk.peri.obj.ddr.div.pdiv_value);
+//          fh_clk_debug(p_clk,"clk in is %d\n",p_clk->parent->clk_out_rate);
+//          fh_clk_debug(p_clk,"peri flag is %x\n",p_clk->clk.peri.obj.ddr.div.div_flag);
 
-			cal_baud_hz(p_clk->parent->clk_out_rate,
-					p_clk->clk.peri.obj.ddr.div.div_flag,
-					p_clk->clk.peri.obj.ddr.div.pdiv_value,
-					p_clk->clk.peri.obj.ddr.div.sw_div_value,
-					p_clk->clk.peri.obj.ddr.div.sw_div_multi,
-					&p_clk->clk_out_rate);
+            cal_baud_hz(p_clk->parent->clk_out_rate,
+                    p_clk->clk.peri.obj.ddr.div.div_flag,
+                    p_clk->clk.peri.obj.ddr.div.pdiv_value,
+                    p_clk->clk.peri.obj.ddr.div.sw_div_value,
+                    p_clk->clk.peri.obj.ddr.div.sw_div_multi,
+                    &p_clk->clk_out_rate);
 
-			//fh_clk_debug_no_handle("%d\n",p_clk->clk_out_rate);
-			//fix the gate..
-			//fh_clk_debug(p_clk,"gate reg add is:%x\t mask is:%x\n",p_clk->clk.peri.obj.ddr.gate.reg_offset,p_clk->clk.peri.obj.ddr.gate.reg_mask);
-			//sw_gate = p_clk->clk.peri.obj.ddr.gate.sw_status;
+            //fh_clk_debug_no_handle("%d\n",p_clk->clk_out_rate);
+            //fix the gate..
+            //fh_clk_debug(p_clk,"gate reg add is:%x\t mask is:%x\n",p_clk->clk.peri.obj.ddr.gate.reg_offset,p_clk->clk.peri.obj.ddr.gate.reg_mask);
+            //sw_gate = p_clk->clk.peri.obj.ddr.gate.sw_status;
 
-			ret = process_gate(
-					p_clk->clk.peri.obj.ddr.gate.gate_flag,
-					p_clk->clk.peri.obj.ddr.gate.reg_offset,
-					p_clk->clk.peri.obj.ddr.gate.reg_mask,
-					&p_clk->clk.peri.obj.ddr.gate.sw_status,
-					&p_clk->gate);
+            ret = process_gate(
+                    p_clk->clk.peri.obj.ddr.gate.gate_flag,
+                    p_clk->clk.peri.obj.ddr.gate.reg_offset,
+                    p_clk->clk.peri.obj.ddr.gate.reg_mask,
+                    &p_clk->clk.peri.obj.ddr.gate.sw_status,
+                    &p_clk->gate);
 
-			if (ret != 0) {
-				fh_clk_err(p_clk,
-						"gate process failed.error no:%x\n",
-						ret);
-				break;
-			}
+            if (ret != 0) {
+                fh_clk_err(p_clk,
+                        "gate process failed.error no:%x\n",
+                        ret);
+                break;
+            }
 
-			break;
-		case LEVEL_PERI_SDC:
-			//just need to handle the phase....
-			p_clk->clk_out_rate = p_clk->parent->clk_out_rate;
-			if (p_clk->clk.peri.obj.sdc.phase_diff & DIFF_REFERENCE) {
-				//fh_clk_debug(p_clk,"this is the reference..no need to process..\n");
-				break;
-			}
+            break;
+        case LEVEL_PERI_SDC:
+            //just need to handle the phase....
+            p_clk->clk_out_rate = p_clk->parent->clk_out_rate;
+            if (p_clk->clk.peri.obj.sdc.phase_diff & DIFF_REFERENCE) {
+                //fh_clk_debug(p_clk,"this is the reference..no need to process..\n");
+                break;
+            }
 
-			//baud ...
+            //baud ...
 
-			//phase..
-			//fh_clk_debug_no_handle("%d\n",p_clk->clk_out_rate);
-			//hw status..
-			ret = wrap_read_reg(p_clk->clk.peri.obj.sdc.reg_offset,
-					p_clk->clk.peri.obj.sdc.reg_mask,
-					&phase);
+            //phase..
+            //fh_clk_debug_no_handle("%d\n",p_clk->clk_out_rate);
+            //hw status..
+            ret = wrap_read_reg(p_clk->clk.peri.obj.sdc.reg_offset,
+                    p_clk->clk.peri.obj.sdc.reg_mask,
+                    &phase);
 
-			if (ret != 0) {
-				fh_clk_err(p_clk,
-						"read pmu failed.error no:%x\n",
-						ret);
-				break;
-			}
+            if (ret != 0) {
+                fh_clk_err(p_clk,
+                        "read pmu failed.error no:%x\n",
+                        ret);
+                break;
+            }
 
-//			fh_clk_debug(p_clk,"hw phase is :%x\n",phase);
-//			fh_clk_debug(p_clk,"sw phase is :%x\n",p_clk->clk.peri.obj.sdc.phase_diff);
-			if (phase != p_clk->clk.peri.obj.sdc.phase_diff) {
-				//update the hw para..
-				ret =
-						wrap_write_reg(
-								p_clk->clk.peri.obj.sdc.reg_offset,
-								p_clk->clk.peri.obj.sdc.reg_mask,
-								p_clk->clk.peri.obj.sdc.phase_diff);
-				if (ret != 0) {
-					fh_clk_err(p_clk,
-							"write pmu failed.error no:%x\n",
-							ret);
-					break;
-				}
-			}
+//          fh_clk_debug(p_clk,"hw phase is :%x\n",phase);
+//          fh_clk_debug(p_clk,"sw phase is :%x\n",p_clk->clk.peri.obj.sdc.phase_diff);
+            if (phase != p_clk->clk.peri.obj.sdc.phase_diff) {
+                //update the hw para..
+                ret =
+                        wrap_write_reg(
+                                p_clk->clk.peri.obj.sdc.reg_offset,
+                                p_clk->clk.peri.obj.sdc.reg_mask,
+                                p_clk->clk.peri.obj.sdc.phase_diff);
+                if (ret != 0) {
+                    fh_clk_err(p_clk,
+                            "write pmu failed.error no:%x\n",
+                            ret);
+                    break;
+                }
+            }
 
-			break;
-		case LEVEL_PERI_GMAC:
-			break;
-		default:
-			break;
+            break;
+        case LEVEL_PERI_GMAC:
+            break;
+        default:
+            break;
 
-		}
-	}
+        }
+    }
 
-	fh_clk_debug(p_clk, "clk out:%d\n", p_clk->clk_out_rate);
+    fh_clk_debug(p_clk, "clk out:%d\n", p_clk->clk_out_rate);
 
 }
 
 //
 void clk_in_update(struct fh_clk* p_clk)
 {
-	clk_handle(p_clk, RT_NULL);
+    clk_handle(p_clk, RT_NULL);
 }
 
 void cis_pclk_update(struct fh_clk* p_clk)
 {
-	clk_handle(p_clk, RT_NULL);
+    clk_handle(p_clk, RT_NULL);
 }
 
 void pll1_clk_update(struct fh_clk* p_clk)
 {
-	clk_handle(p_clk, &clk_in);
+    clk_handle(p_clk, &clk_in);
 }
 
 void pll0_clk_update(struct fh_clk* p_clk)
 {
-	clk_handle(p_clk, &clk_in);
+    clk_handle(p_clk, &clk_in);
 }
 
 void ddr_clk_update(struct fh_clk* p_clk)
 {
 
-	//check if pll0 or pll1
-	rt_uint32_t mux0, mux1;
-	rt_int32_t ret;
-	struct fh_clk* parent;
-	//1 step: fix the parent..
-	ret = wrap_read_reg(p_clk->clk.peri.obj.ddr.mux[1].reg_offset,
-			p_clk->clk.peri.obj.ddr.mux[1].reg_mask, &mux1);
-	if (ret != 0) {
-		fh_clk_err(p_clk, "read pmu failed.error no:%x\n", ret);
-		return;
-	}
+    //check if pll0 or pll1
+    rt_uint32_t mux0, mux1;
+    rt_int32_t ret;
+    struct fh_clk* parent;
+    //1 step: fix the parent..
+    ret = wrap_read_reg(p_clk->clk.peri.obj.ddr.mux[1].reg_offset,
+            p_clk->clk.peri.obj.ddr.mux[1].reg_mask, &mux1);
+    if (ret != 0) {
+        fh_clk_err(p_clk, "read pmu failed.error no:%x\n", ret);
+        return;
+    }
 
-	if (mux1 == MUX1_PLL0_CLK) {
-		ret = check_xtal_pll0(p_clk->clk.peri.obj.ddr.mux[0].reg_offset,
-				p_clk->clk.peri.obj.ddr.mux[0].reg_mask, &mux0);
-		if (ret != 0) {
-			fh_clk_err(p_clk, "read pmu failed.error no:%x\n", ret);
-			return;
-		}
-		if (mux0 == MUX0_PLL0_CLK) {
-			//ddr normal parent is pll0
-			parent = &pll0;
-		} else {
-			//ddr normal parent is xtal
-			parent = &clk_in;
-		}
-	} else {
-		//ddr normal parent is pll1
-		parent = &pll1;
-	}
-	p_clk->clk.peri.obj.ddr.mux[0].mux_flag = HAS_MUX;
-	p_clk->clk.peri.obj.ddr.mux[1].mux_flag = HAS_MUX;
-	clk_handle(p_clk, parent);
+    if (mux1 == MUX1_PLL0_CLK) {
+        ret = check_xtal_pll0(p_clk->clk.peri.obj.ddr.mux[0].reg_offset,
+                p_clk->clk.peri.obj.ddr.mux[0].reg_mask, &mux0);
+        if (ret != 0) {
+            fh_clk_err(p_clk, "read pmu failed.error no:%x\n", ret);
+            return;
+        }
+        if (mux0 == MUX0_PLL0_CLK) {
+            //ddr normal parent is pll0
+            parent = &pll0;
+        } else {
+            //ddr normal parent is xtal
+            parent = &clk_in;
+        }
+    } else {
+        //ddr normal parent is pll1
+        parent = &pll1;
+    }
+    p_clk->clk.peri.obj.ddr.mux[0].mux_flag = HAS_MUX;
+    p_clk->clk.peri.obj.ddr.mux[1].mux_flag = HAS_MUX;
+    clk_handle(p_clk, parent);
 
 }
 
 void fclk_update(struct fh_clk* p_clk)
 {
 
-	//check if pll0 or xtal
-	rt_uint32_t mux0;
-	rt_int32_t ret;
-	struct fh_clk* parent;	//1 step: fix the parent..
+    //check if pll0 or xtal
+    rt_uint32_t mux0;
+    rt_int32_t ret;
+    struct fh_clk* parent;  //1 step: fix the parent..
 
-	//mux0 = check_xtal_pll0(p_clk->clk.peri.obj.ddr.mux[0].reg_offset,p_clk->clk.peri.obj.ddr.mux[0].reg_mask);
-	ret = check_xtal_pll0(p_clk->clk.peri.obj.normal.mux.reg_offset,
-			p_clk->clk.peri.obj.normal.mux.reg_mask, &mux0);
-	if (ret != 0) {
-		fh_clk_err(p_clk, "read pmu failed.error no:%x\n", ret);
-		return;
-	}
+    //mux0 = check_xtal_pll0(p_clk->clk.peri.obj.ddr.mux[0].reg_offset,p_clk->clk.peri.obj.ddr.mux[0].reg_mask);
+    ret = check_xtal_pll0(p_clk->clk.peri.obj.normal.mux.reg_offset,
+            p_clk->clk.peri.obj.normal.mux.reg_mask, &mux0);
+    if (ret != 0) {
+        fh_clk_err(p_clk, "read pmu failed.error no:%x\n", ret);
+        return;
+    }
 
-	//fh_clk_debug(p_clk,"mux0 wrap value is %x\n",mux0);
-	if (mux0 == MUX0_PLL0_CLK) {
-		//ddr normal parent is pll0
-		parent = &pll0;
-	} else {
-		//ddr normal parent is xtal
-		parent = &clk_in;
-	}
-	p_clk->clk.peri.obj.normal.mux.mux_flag = HAS_MUX;
-	//2 step:fix the div...
-	if (mux0 == MUX0_PLL0_CLK) {
-		//cal_pll0_prediv(&p_clk->clk.peri.obj.ddr.div.div_flag,&p_clk->clk.peri.obj.ddr.div.pdiv_value);
-		cal_pll0_prediv(&p_clk->clk.peri.obj.normal.div.div_flag,
-				&p_clk->clk.peri.obj.normal.div.pdiv_value);
-	}
-	clk_handle(p_clk, parent);
+    //fh_clk_debug(p_clk,"mux0 wrap value is %x\n",mux0);
+    if (mux0 == MUX0_PLL0_CLK) {
+        //ddr normal parent is pll0
+        parent = &pll0;
+    } else {
+        //ddr normal parent is xtal
+        parent = &clk_in;
+    }
+    p_clk->clk.peri.obj.normal.mux.mux_flag = HAS_MUX;
+    //2 step:fix the div...
+    if (mux0 == MUX0_PLL0_CLK) {
+        //cal_pll0_prediv(&p_clk->clk.peri.obj.ddr.div.div_flag,&p_clk->clk.peri.obj.ddr.div.pdiv_value);
+        cal_pll0_prediv(&p_clk->clk.peri.obj.normal.div.div_flag,
+                &p_clk->clk.peri.obj.normal.div.pdiv_value);
+    }
+    clk_handle(p_clk, parent);
 }
 
 void pix_update(struct fh_clk* p_clk)
 {
 
-	//check if pll0 or xtal
-	rt_uint32_t mux0;
-	rt_int32_t ret;
-	struct fh_clk* parent;	//1 step: fix the parent..
+    //check if pll0 or xtal
+    rt_uint32_t mux0;
+    rt_int32_t ret;
+    struct fh_clk* parent;  //1 step: fix the parent..
 #if(1)
-	//mux0 = check_xtal_pll0(p_clk->clk.peri.obj.ddr.mux[0].reg_offset,p_clk->clk.peri.obj.ddr.mux[0].reg_mask);
-	ret = check_pix_clk_source(p_clk->clk.peri.obj.normal.mux.reg_offset,
-			p_clk->clk.peri.obj.normal.mux.reg_mask, &mux0);
-	if (ret != 0) {
-		fh_clk_err(p_clk, "read pmu failed.error no:%x\n", ret);
-		return;
-	}
-//#define CIS_PIX_CLK				(0)
-//#define CIS_PIX_CLK_OPPOSITE	(1)
-//#define MIPI_PIX_CLK			(2)
+    //mux0 = check_xtal_pll0(p_clk->clk.peri.obj.ddr.mux[0].reg_offset,p_clk->clk.peri.obj.ddr.mux[0].reg_mask);
+    ret = check_pix_clk_source(p_clk->clk.peri.obj.normal.mux.reg_offset,
+            p_clk->clk.peri.obj.normal.mux.reg_mask, &mux0);
+    if (ret != 0) {
+        fh_clk_err(p_clk, "read pmu failed.error no:%x\n", ret);
+        return;
+    }
+//#define CIS_PIX_CLK               (0)
+//#define CIS_PIX_CLK_OPPOSITE  (1)
+//#define MIPI_PIX_CLK          (2)
 
-	//fh_clk_debug(p_clk,"mux0 wrap value is %x\n",mux0);
-	if (mux0 == CIS_PIX_CLK || mux0 == CIS_PIX_CLK_OPPOSITE) {
-		//ddr normal parent is pll0
-		parent = &cis_pclk;
-	} else {
-		parent = &mipi_pix_clk;
-	}
-	p_clk->clk.peri.obj.normal.mux.mux_flag = HAS_MUX;
+    //fh_clk_debug(p_clk,"mux0 wrap value is %x\n",mux0);
+    if (mux0 == CIS_PIX_CLK || mux0 == CIS_PIX_CLK_OPPOSITE) {
+        //ddr normal parent is pll0
+        parent = &cis_pclk;
+    } else {
+        parent = &mipi_pix_clk;
+    }
+    p_clk->clk.peri.obj.normal.mux.mux_flag = HAS_MUX;
 
 #endif
-	clk_handle(p_clk, parent);
+    clk_handle(p_clk, parent);
 }
 
 void aclk_update(struct fh_clk* p_clk)
 {
-	clk_handle(p_clk, &cpu_fclk);
+    clk_handle(p_clk, &cpu_fclk);
 
 }
 
 void hclk_update(struct fh_clk* p_clk)
 {
 
-	fclk_update(p_clk);
+    fclk_update(p_clk);
 }
 
 void pclk_update(struct fh_clk* p_clk)
 {
 
-	clk_handle(p_clk, &cpu_hclk);
+    clk_handle(p_clk, &cpu_hclk);
 }
 
 void isp_aclk_update(struct fh_clk* p_clk)
 {
 
-	fclk_update(p_clk);
+    fclk_update(p_clk);
 }
 
 void vcu_clk_update(struct fh_clk* p_clk)
 {
-	fclk_update(p_clk);
+    fclk_update(p_clk);
 }
 
 void vou_clk_update(struct fh_clk* p_clk)
 {
-	fclk_update(p_clk);
+    fclk_update(p_clk);
 }
 
 void mipi_p32_clk_update(struct fh_clk* p_clk)
 {
-	fclk_update(p_clk);
+    fclk_update(p_clk);
 }
 
 void cis_clk_out_update(struct fh_clk* p_clk)
 {
-	fclk_update(p_clk);
+    fclk_update(p_clk);
 }
 
 void pts_update(struct fh_clk* p_clk)
 {
-	fclk_update(p_clk);
+    fclk_update(p_clk);
 }
 
 void mipi_pix_clk_update(struct fh_clk* p_clk)
 {
-	fclk_update(p_clk);
+    fclk_update(p_clk);
 }
 
 void spi0_clk_update(struct fh_clk* p_clk)
 {
-	clk_handle(p_clk, &pll1);
+    clk_handle(p_clk, &pll1);
 }
 
 void spi1_clk_update(struct fh_clk* p_clk)
 {
-	clk_handle(p_clk, &pll1);
+    clk_handle(p_clk, &pll1);
 }
 
 void mipi_dphy_clk20m_update(struct fh_clk* p_clk)
 {
-	clk_handle(p_clk, &pll1);
+    clk_handle(p_clk, &pll1);
 }
 
 void i2c0_clk_update(struct fh_clk* p_clk)
 {
-	clk_handle(p_clk, &pll1);
+    clk_handle(p_clk, &pll1);
 }
 
 void i2c1_clk_update(struct fh_clk* p_clk)
 {
-	clk_handle(p_clk, &pll1);
+    clk_handle(p_clk, &pll1);
 }
 
 void uart0_clk_update(struct fh_clk* p_clk)
 {
-	clk_handle(p_clk, &pll1);
+    clk_handle(p_clk, &pll1);
 }
 
 void pwm_clk_update(struct fh_clk* p_clk)
 {
-	clk_handle(p_clk, &pll1);
+    clk_handle(p_clk, &pll1);
 }
 
 void time0_clk_update(struct fh_clk* p_clk)
 {
-	clk_handle(p_clk, &pll1);
+    clk_handle(p_clk, &pll1);
 }
 
 void time1_clk_update(struct fh_clk* p_clk)
 {
-	clk_handle(p_clk, &pll1);
+    clk_handle(p_clk, &pll1);
 }
 
 void uart1_clk_update(struct fh_clk* p_clk)
 {
-	clk_handle(p_clk, &pll1);
+    clk_handle(p_clk, &pll1);
 }
 
 void sadc_clk_update(struct fh_clk* p_clk)
 {
-	clk_handle(p_clk, &pll1);
+    clk_handle(p_clk, &pll1);
 }
 
 //sdc0...
 void sdc0_clk2x_update(struct fh_clk* p_clk)
 {
-	clk_handle(p_clk, &pll1);
+    clk_handle(p_clk, &pll1);
 }
 
 void sdc0_clk_update(struct fh_clk* p_clk)
 {
-	clk_handle(p_clk, &sdc0_clk2x);
+    clk_handle(p_clk, &sdc0_clk2x);
 }
 
 void sdc0_clk_out_update(struct fh_clk* p_clk)
 {
-	clk_handle(p_clk, &sdc0_clk);
+    clk_handle(p_clk, &sdc0_clk);
 }
 
 void sdc0_clk_sample_update(struct fh_clk* p_clk)
 {
-	clk_handle(p_clk, &sdc0_clk2x);
+    clk_handle(p_clk, &sdc0_clk2x);
 }
 
 void sdc0_clk_drv_update(struct fh_clk* p_clk)
 {
-	clk_handle(p_clk, &sdc0_clk2x);
+    clk_handle(p_clk, &sdc0_clk2x);
 }
 
 void sdc1_clk2x_update(struct fh_clk* p_clk)
 {
-	clk_handle(p_clk, &pll1);
+    clk_handle(p_clk, &pll1);
 }
 
 void sdc1_clk_update(struct fh_clk* p_clk)
 {
-	clk_handle(p_clk, &sdc1_clk2x);
+    clk_handle(p_clk, &sdc1_clk2x);
 }
 
 void sdc1_clk_out_update(struct fh_clk* p_clk)
 {
-	clk_handle(p_clk, &sdc1_clk);
+    clk_handle(p_clk, &sdc1_clk);
 }
 
 void sdc1_clk_sample_update(struct fh_clk* p_clk)
 {
-	clk_handle(p_clk, &sdc1_clk2x);
+    clk_handle(p_clk, &sdc1_clk2x);
 }
 
 void sdc1_clk_drv_update(struct fh_clk* p_clk)
 {
-	clk_handle(p_clk, &sdc1_clk2x);
+    clk_handle(p_clk, &sdc1_clk2x);
 }
 
 void eth_ref_clk_update(struct fh_clk* p_clk)
 {
-	clk_handle(p_clk, &pll1);
+    clk_handle(p_clk, &pll1);
 }
 
 void wdt_clk_update(struct fh_clk* p_clk)
 {
-	clk_handle(p_clk, &cpu_pclk);
+    clk_handle(p_clk, &cpu_pclk);
 }
 
 /**
  * @brief System Clock Configuration
  */
-#define CLK_CONTROL_BASE			PMU_REG_BASE
+#define CLK_CONTROL_BASE            PMU_REG_BASE
 void rt_hw_clock_init(void)
 {
-	struct fh_clk *p;
-	int i;
-	fh_clk_tree.c_base_addr = CLK_CONTROL_BASE;
-	fh_clk_tree.clk_head = fh_clk_array;
+    struct fh_clk *p;
+    int i;
+    fh_clk_tree.c_base_addr = CLK_CONTROL_BASE;
+    fh_clk_tree.clk_head = fh_clk_array;
 
-	//first open all the clock..
-	FH_TIMER_WRITEL(REG_PMU_CLK_GATE, 0x0);
-	for (i = 0; i < sizeof(fh_clk_array) / sizeof(struct fh_clk *); i++) {
-		p = fh_clk_tree.clk_head[i];
-		if (p->update_func)
-			p->update_func(p);
-	}
+    //first open all the clock..
+    FH_TIMER_WRITEL(REG_PMU_CLK_GATE, 0x0);
+    for (i = 0; i < sizeof(fh_clk_array) / sizeof(struct fh_clk *); i++) {
+        p = fh_clk_tree.clk_head[i];
+        if (p->update_func)
+            p->update_func(p);
+    }
 }
 
 /***************
@@ -2453,196 +2453,196 @@ void rt_hw_clock_init(void)
 struct fh_clk *clk_get(const char *name)
 {
 
-	struct fh_clk *p;
-	int i;
+    struct fh_clk *p;
+    int i;
 
-	for (i = 0; i < sizeof(fh_clk_array) / sizeof(struct fh_clk *); i++) {
-		p = fh_clk_tree.clk_head[i];
-		if (!strcmp(p->name, name)) {
-			return p;
-		}
-	}
+    for (i = 0; i < sizeof(fh_clk_array) / sizeof(struct fh_clk *); i++) {
+        p = fh_clk_tree.clk_head[i];
+        if (!strcmp(p->name, name)) {
+            return p;
+        }
+    }
 
-	return RT_NULL;
+    return RT_NULL;
 }
 
 //
-//#define HAS_GATE			(0)
-//#define HAS_NO_GATE			(1)
-//	rt_uint32_t gate_flag;
-//#define CLK_UNGATE			(0)
-//#define CLK_GATE			(1)
+//#define HAS_GATE          (0)
+//#define HAS_NO_GATE           (1)
+//  rt_uint32_t gate_flag;
+//#define CLK_UNGATE            (0)
+//#define CLK_GATE          (1)
 
 void clk_gate_control(struct fh_clk *p_clk, rt_uint32_t status)
 {
 
-	if (status > CLK_GATE)
-		return;
+    if (status > CLK_GATE)
+        return;
 
-	if (p_clk->level == LEVEL_PERIPHERAL) {
+    if (p_clk->level == LEVEL_PERIPHERAL) {
 
-		switch (p_clk->clk.peri.peri_flag) {
-		case LEVEL_PERI_NORMAL:
+        switch (p_clk->clk.peri.peri_flag) {
+        case LEVEL_PERI_NORMAL:
 
-			if (p_clk->clk.peri.obj.normal.gate.gate_flag
-					== HAS_GATE) {
-				p_clk->clk.peri.obj.normal.gate.sw_status =
-						status;
-			} else {
-				rt_kprintf("[%-16.15s]: no gate...\t\n",
-						p_clk->name);
-			}
+            if (p_clk->clk.peri.obj.normal.gate.gate_flag
+                    == HAS_GATE) {
+                p_clk->clk.peri.obj.normal.gate.sw_status =
+                        status;
+            } else {
+                rt_kprintf("[%-16.15s]: no gate...\t\n",
+                        p_clk->name);
+            }
 
-			break;
-		case LEVEL_PERI_DDR:
-			if (p_clk->clk.peri.obj.ddr.gate.gate_flag == HAS_GATE) {
-				p_clk->clk.peri.obj.ddr.gate.sw_status = status;
-			} else {
-				rt_kprintf("[%-16.15s]: no gate...\t\n",
-						p_clk->name);
-			}
+            break;
+        case LEVEL_PERI_DDR:
+            if (p_clk->clk.peri.obj.ddr.gate.gate_flag == HAS_GATE) {
+                p_clk->clk.peri.obj.ddr.gate.sw_status = status;
+            } else {
+                rt_kprintf("[%-16.15s]: no gate...\t\n",
+                        p_clk->name);
+            }
 
-			break;
+            break;
 
-		default:
-			break;
-		}
+        default:
+            break;
+        }
 
-		p_clk->update_func(p_clk);
+        p_clk->update_func(p_clk);
 
-	}
+    }
 
 }
 
 void clk_gate(struct fh_clk *p_clk)
 {
-	clk_gate_control(p_clk, CLK_GATE);
+    clk_gate_control(p_clk, CLK_GATE);
 }
 
 void clk_ungate(struct fh_clk *p_clk)
 {
-	clk_gate_control(p_clk, CLK_UNGATE);
+    clk_gate_control(p_clk, CLK_UNGATE);
 }
 
 rt_uint32_t clk_get_rate(struct fh_clk *p_clk)
 {
-	rt_uint32_t rate;
-	//first update the status
-	p_clk->update_func(p_clk);
-	rate = p_clk->clk_out_rate;
-	return rate;
+    rt_uint32_t rate;
+    //first update the status
+    p_clk->update_func(p_clk);
+    rate = p_clk->clk_out_rate;
+    return rate;
 }
 
 void clk_set_rate(struct fh_clk *p_clk, rt_uint32_t rate_value)
 {
 
-	rt_uint32_t clk_in, div_flag, pre_div, div_multi, baud_out;
+    rt_uint32_t clk_in, div_flag, pre_div, div_multi, baud_out;
 
-	if (p_clk->level == LEVEL_PERIPHERAL) {
+    if (p_clk->level == LEVEL_PERIPHERAL) {
 
-		switch (p_clk->clk.peri.peri_flag) {
-		case LEVEL_PERI_NORMAL:
+        switch (p_clk->clk.peri.peri_flag) {
+        case LEVEL_PERI_NORMAL:
 
-			clk_in = p_clk->parent->clk_out_rate;
-			div_flag = p_clk->clk.peri.obj.normal.div.div_flag;
-			pre_div = p_clk->clk.peri.obj.normal.div.pdiv_value;
-			div_multi = p_clk->clk.peri.obj.normal.div.sw_div_multi;
-			baud_out = rate_value;
+            clk_in = p_clk->parent->clk_out_rate;
+            div_flag = p_clk->clk.peri.obj.normal.div.div_flag;
+            pre_div = p_clk->clk.peri.obj.normal.div.pdiv_value;
+            div_multi = p_clk->clk.peri.obj.normal.div.sw_div_multi;
+            baud_out = rate_value;
 
-			cal_baud_div(clk_in, div_flag, pre_div,
-					&p_clk->clk.peri.obj.normal.div.sw_div_value,
-					div_multi, baud_out);
+            cal_baud_div(clk_in, div_flag, pre_div,
+                    &p_clk->clk.peri.obj.normal.div.sw_div_value,
+                    div_multi, baud_out);
 
-			break;
-		case LEVEL_PERI_DDR:
-			//rt_uint32_t mux0,mux1;
-			clk_in = p_clk->parent->clk_out_rate;
-			div_flag = p_clk->clk.peri.obj.ddr.div.div_flag;
-			pre_div = p_clk->clk.peri.obj.ddr.div.pdiv_value;
-			div_multi = p_clk->clk.peri.obj.ddr.div.sw_div_multi;
-			baud_out = rate_value;
+            break;
+        case LEVEL_PERI_DDR:
+            //rt_uint32_t mux0,mux1;
+            clk_in = p_clk->parent->clk_out_rate;
+            div_flag = p_clk->clk.peri.obj.ddr.div.div_flag;
+            pre_div = p_clk->clk.peri.obj.ddr.div.pdiv_value;
+            div_multi = p_clk->clk.peri.obj.ddr.div.sw_div_multi;
+            baud_out = rate_value;
 
-			cal_baud_div(clk_in, div_flag, pre_div,
-					&p_clk->clk.peri.obj.ddr.div.sw_div_value,
-					div_multi, baud_out);
-			break;
-		case LEVEL_PERI_SDC:
-			fh_clk_debug(p_clk,
-					"sdc can't set baud,please set the 'sdcx_clk2x'\n");
-			break;
-		case LEVEL_PERI_GMAC:
-			fh_clk_debug(p_clk, "gmac not support set baud\n");
-			break;
-		default:
-			break;
-		}
-		p_clk->update_func(p_clk);
+            cal_baud_div(clk_in, div_flag, pre_div,
+                    &p_clk->clk.peri.obj.ddr.div.sw_div_value,
+                    div_multi, baud_out);
+            break;
+        case LEVEL_PERI_SDC:
+            fh_clk_debug(p_clk,
+                    "sdc can't set baud,please set the 'sdcx_clk2x'\n");
+            break;
+        case LEVEL_PERI_GMAC:
+            fh_clk_debug(p_clk, "gmac not support set baud\n");
+            break;
+        default:
+            break;
+        }
+        p_clk->update_func(p_clk);
 
-	}
+    }
 
 }
 
 rt_uint32_t sdc_get_phase(struct fh_clk *p_clk)
 {
 
-	if (p_clk->level == LEVEL_PERIPHERAL) {
-		if (p_clk->clk.peri.peri_flag == LEVEL_PERI_SDC) {
+    if (p_clk->level == LEVEL_PERIPHERAL) {
+        if (p_clk->clk.peri.peri_flag == LEVEL_PERI_SDC) {
 
-			p_clk->update_func(p_clk);
-			return p_clk->clk.peri.obj.sdc.phase_diff;
-		}
-	}
-	return SDC_CLK_PARA_ERROR;
+            p_clk->update_func(p_clk);
+            return p_clk->clk.peri.obj.sdc.phase_diff;
+        }
+    }
+    return SDC_CLK_PARA_ERROR;
 
 }
 
 rt_uint32_t sdc_set_phase(struct fh_clk *p_clk, rt_uint32_t phase)
 {
 
-	if (phase > DIFF_SDC_REFCLK_270)
-		return SDC_CLK_PARA_ERROR;
+    if (phase > DIFF_SDC_REFCLK_270)
+        return SDC_CLK_PARA_ERROR;
 
-	if (p_clk->level == LEVEL_PERIPHERAL) {
-		if (p_clk->clk.peri.peri_flag == LEVEL_PERI_SDC) {
-			p_clk->clk.peri.obj.sdc.phase_diff = phase;
-			p_clk->update_func(p_clk);
-			return SDC_CLK_PARA_OK;
-		}
-	}
-	return SDC_CLK_PARA_ERROR;
+    if (p_clk->level == LEVEL_PERIPHERAL) {
+        if (p_clk->clk.peri.peri_flag == LEVEL_PERI_SDC) {
+            p_clk->clk.peri.obj.sdc.phase_diff = phase;
+            p_clk->update_func(p_clk);
+            return SDC_CLK_PARA_OK;
+        }
+    }
+    return SDC_CLK_PARA_ERROR;
 
 }
 
 #ifdef FH_DBG_CLK
 int fh_clk_nlist()
 {
-	struct fh_clk *p;
-	int i;
+    struct fh_clk *p;
+    int i;
 
-	for(i = 0;iupdate_func(p);
-		rt_kprintf("[%-16.15s]:\t\t[baud]:%d\t\n",p->name,p->clk_out_rate);
-	}
+    for(i = 0;iupdate_func(p);
+        rt_kprintf("[%-16.15s]:\t\t[baud]:%d\t\n",p->name,p->clk_out_rate);
+    }
 
-	return 0;
+    return 0;
 }
 
 int fh_clk_glist()
 {
-	struct fh_clk *p;
-	int i;
-	rt_kprintf("first bit set means has no gate..\n");
-	for(i = 0;iupdate_func(p);
-		if(!(p->gate & CLK_HAS_NO_GATE))
-		rt_kprintf("[%-16.15s]:\t\t[gate]:%d\t\n",p->name,p->gate);
-		else
-		rt_kprintf("[%-16.15s]:\t\t[gate]:no gate..\t\n",p->name);
-	}
+    struct fh_clk *p;
+    int i;
+    rt_kprintf("first bit set means has no gate..\n");
+    for(i = 0;iupdate_func(p);
+        if(!(p->gate & CLK_HAS_NO_GATE))
+        rt_kprintf("[%-16.15s]:\t\t[gate]:%d\t\n",p->name,p->gate);
+        else
+        rt_kprintf("[%-16.15s]:\t\t[gate]:no gate..\t\n",p->name);
+    }
 
-	return 0;
+    return 0;
 }
 #endif
 
diff --git a/bsp/fh8620/platform/plat-v2/clock.h b/bsp/fh8620/platform/plat-v2/clock.h
index 60b0ed6538..cdf94b017a 100644
--- a/bsp/fh8620/platform/plat-v2/clock.h
+++ b/bsp/fh8620/platform/plat-v2/clock.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #ifndef TIMER_H_
 #define TIMER_H_
 
@@ -43,12 +43,12 @@ void fh_pmu_open(void);
 void fh_pmu_close(void);
 */
 
-#define DIFF_SDC_REFCLK_0			(0)
-#define DIFF_SDC_REFCLK_90			(1)
-#define DIFF_SDC_REFCLK_180			(2)
-#define DIFF_SDC_REFCLK_270			(3)
-#define SDC_CLK_PARA_ERROR		(0xffff0000)
-#define SDC_CLK_PARA_OK			(0)
+#define DIFF_SDC_REFCLK_0           (0)
+#define DIFF_SDC_REFCLK_90          (1)
+#define DIFF_SDC_REFCLK_180         (2)
+#define DIFF_SDC_REFCLK_270         (3)
+#define SDC_CLK_PARA_ERROR      (0xffff0000)
+#define SDC_CLK_PARA_OK         (0)
 
 
 void clk_gate(struct fh_clk *p_clk);
diff --git a/bsp/fh8620/platform/plat-v2/fh_pmu.c b/bsp/fh8620/platform/plat-v2/fh_pmu.c
index 8f518efd94..d17f215a17 100644
--- a/bsp/fh8620/platform/plat-v2/fh_pmu.c
+++ b/bsp/fh8620/platform/plat-v2/fh_pmu.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,45 +18,45 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #include "rtdebug.h"
 #include "arch.h"
 #include "fh_pmu.h"
 #include "fh_def.h"
 
-#define FH_PMU_WRITEL(offset,value)		SET_REG((PMU_REG_BASE + offset),value)
-#define FH_PMU_WRITEL_MASK(offset,value, mask)	SET_REG_M((PMU_REG_BASE + offset), value, mask)
-#define FH_PMU_READL(offset)			GET_REG((PMU_REG_BASE + offset))
+#define FH_PMU_WRITEL(offset,value)     SET_REG((PMU_REG_BASE + offset),value)
+#define FH_PMU_WRITEL_MASK(offset,value, mask)  SET_REG_M((PMU_REG_BASE + offset), value, mask)
+#define FH_PMU_READL(offset)            GET_REG((PMU_REG_BASE + offset))
 
-#define PMU_OFFSET_MAX		0x1d0
+#define PMU_OFFSET_MAX      0x1d0
 
 int fh_pmu_read(rt_uint32_t offset, rt_uint32_t *value)
 {
-	RT_ASSERT(offset < PMU_OFFSET_MAX);
+    RT_ASSERT(offset < PMU_OFFSET_MAX);
 
-	*value = FH_PMU_READL(offset);
-	return 0;
+    *value = FH_PMU_READL(offset);
+    return 0;
 }
 
 int  fh_pmu_write(rt_uint32_t offset, const rt_uint32_t value)
 {
-	RT_ASSERT(offset < PMU_OFFSET_MAX);
+    RT_ASSERT(offset < PMU_OFFSET_MAX);
 
-	FH_PMU_WRITEL(offset, value);
-	return 0;
+    FH_PMU_WRITEL(offset, value);
+    return 0;
 }
 
 int fh_pmu_write_mask(rt_uint32_t offset, const rt_uint32_t value,
-		      const rt_uint32_t mask)
+              const rt_uint32_t mask)
 {
-	RT_ASSERT(offset < PMU_OFFSET_MAX);
+    RT_ASSERT(offset < PMU_OFFSET_MAX);
 
-	FH_PMU_WRITEL_MASK(offset, value, mask);
-	return 0;
+    FH_PMU_WRITEL_MASK(offset, value, mask);
+    return 0;
 
 }
diff --git a/bsp/fh8620/platform/plat-v2/fh_pmu.h b/bsp/fh8620/platform/plat-v2/fh_pmu.h
index 19a6279d1a..4ecedd2fd4 100644
--- a/bsp/fh8620/platform/plat-v2/fh_pmu.h
+++ b/bsp/fh8620/platform/plat-v2/fh_pmu.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #ifndef FH_PMU_H_
 #define FH_PMU_H_
 
@@ -36,7 +36,7 @@
 #define     REG_PMU_PLL0_CTRL           (0x010)
 #define     REG_PMU_PLL1_CTRL           (0x014)
 #define     REG_PMU_ARC_CLK_GATE        (0x018)
-#define     REG_PMU_CLK_GATE        	(0x01c)
+#define     REG_PMU_CLK_GATE            (0x01c)
 #define     REG_PMU_CLK_SEL             (0x020)
 #define     REG_PMU_CLK_DIV0            (0x024)
 #define     REG_PMU_CLK_DIV1            (0x028)
diff --git a/bsp/fh8620/platform/plat-v2/iomux.c b/bsp/fh8620/platform/plat-v2/iomux.c
index 67acf6ca75..51b14f5937 100644
--- a/bsp/fh8620/platform/plat-v2/iomux.c
+++ b/bsp/fh8620/platform/plat-v2/iomux.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,34 +18,34 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #include "rtdebug.h"
 #include "iomux.h"
 
 static void fh_iomux_setmfs(Iomux_Pad *pad)
 {
 
-	switch (pad->reg_type) {
-	case 8:
-		(IOMUX_PADTYPE(8)pad->reg)->bit.mfs = pad->func_sel;
-		break;
-	case 13:
-		(IOMUX_PADTYPE(13)pad->reg)->bit.mfs = pad->func_sel;
-		break;
-	case 20:
-		(IOMUX_PADTYPE(20)pad->reg)->bit.mfs = pad->func_sel;
-		break;
-	case 21:
-		(IOMUX_PADTYPE(21)pad->reg)->bit.mfs = pad->func_sel;
-		break;
-	default:
-		break;
-	}
+    switch (pad->reg_type) {
+    case 8:
+        (IOMUX_PADTYPE(8)pad->reg)->bit.mfs = pad->func_sel;
+        break;
+    case 13:
+        (IOMUX_PADTYPE(13)pad->reg)->bit.mfs = pad->func_sel;
+        break;
+    case 20:
+        (IOMUX_PADTYPE(20)pad->reg)->bit.mfs = pad->func_sel;
+        break;
+    case 21:
+        (IOMUX_PADTYPE(21)pad->reg)->bit.mfs = pad->func_sel;
+        break;
+    default:
+        break;
+    }
 
 }
 
@@ -53,50 +53,50 @@ static void fh_iomux_setmfs(Iomux_Pad *pad)
 
 static int fh_iomux_getmfs(Iomux_Pad *pad)
 {
-	int mfs;
+    int mfs;
 
-	switch (pad->reg_type) {
-	case 8:
-		mfs = (IOMUX_PADTYPE(8)pad->reg)->bit.mfs;
-		break;
-	case 13:
-		mfs = (IOMUX_PADTYPE(13)pad->reg)->bit.mfs;
-		break;
-	case 20:
-		mfs = (IOMUX_PADTYPE(20)pad->reg)->bit.mfs;
-		break;
-	case 21:
-		mfs = (IOMUX_PADTYPE(21)pad->reg)->bit.mfs;
-		break;
-	default:
-		mfs = -1;
-		break;
+    switch (pad->reg_type) {
+    case 8:
+        mfs = (IOMUX_PADTYPE(8)pad->reg)->bit.mfs;
+        break;
+    case 13:
+        mfs = (IOMUX_PADTYPE(13)pad->reg)->bit.mfs;
+        break;
+    case 20:
+        mfs = (IOMUX_PADTYPE(20)pad->reg)->bit.mfs;
+        break;
+    case 21:
+        mfs = (IOMUX_PADTYPE(21)pad->reg)->bit.mfs;
+        break;
+    default:
+        mfs = -1;
+        break;
 
-	}
-	return mfs;
+    }
+    return mfs;
 }
 
 
 static void fh_iomux_print()
 {
-	int i;
-	UINT32 reg;
+    int i;
+    UINT32 reg;
 
 
-	for (i = 0; i < ARRAY_SIZE(fh81_iomux_cfg); i++) {
-		int curr_func;
+    for (i = 0; i < ARRAY_SIZE(fh81_iomux_cfg); i++) {
+        int curr_func;
 
-		curr_func = fh81_iomux_getmfs(iomux_obj, &iomux_obj.pads[i]);
-		reg = readl((UINT32)iomux_obj.pads[i].reg);
+        curr_func = fh81_iomux_getmfs(iomux_obj, &iomux_obj.pads[i]);
+        reg = readl((UINT32)iomux_obj.pads[i].reg);
 
-		if (curr_func < 0)
-			rt_kprintf("\t%d\t\t%-8s(no mfs)\t0x%08x\n", i, iomux_obj.pads[i].func_name[0],
-				   reg);
-		else
-			rt_kprintf("\t%d\t\t%-16s\t0x%08x\n", i, iomux_obj.pads[i].func_name[curr_func],
-				   reg);
+        if (curr_func < 0)
+            rt_kprintf("\t%d\t\t%-8s(no mfs)\t0x%08x\n", i, iomux_obj.pads[i].func_name[0],
+                   reg);
+        else
+            rt_kprintf("\t%d\t\t%-16s\t0x%08x\n", i, iomux_obj.pads[i].func_name[curr_func],
+                   reg);
 
-	}
+    }
 
 }
 
@@ -105,90 +105,90 @@ static void fh_iomux_print()
 static void fh_iomux_setcur(Iomux_Pad *pad)
 {
 
-	switch (pad->reg_type) {
-	case 5:
-		(IOMUX_PADTYPE(5)pad->reg)->bit.e8_e4 = pad->drv_cur;
-		break;
-	case 8:
-		(IOMUX_PADTYPE(8)pad->reg)->bit.e8_e4 = pad->drv_cur;
-		break;
-	case 13:
-		(IOMUX_PADTYPE(13)pad->reg)->bit.e4_e2 = pad->drv_cur;
-		break;
-	case 17:
-		(IOMUX_PADTYPE(17)pad->reg)->bit.e8_e4 = pad->drv_cur;
-		break;
-	case 20:
-		(IOMUX_PADTYPE(20)pad->reg)->bit.e4_e2 = pad->drv_cur;
-		break;
-	case 21:
-		(IOMUX_PADTYPE(21)pad->reg)->bit.e4_e2 = pad->drv_cur;
-		break;
-	default:
-		break;
-	}
+    switch (pad->reg_type) {
+    case 5:
+        (IOMUX_PADTYPE(5)pad->reg)->bit.e8_e4 = pad->drv_cur;
+        break;
+    case 8:
+        (IOMUX_PADTYPE(8)pad->reg)->bit.e8_e4 = pad->drv_cur;
+        break;
+    case 13:
+        (IOMUX_PADTYPE(13)pad->reg)->bit.e4_e2 = pad->drv_cur;
+        break;
+    case 17:
+        (IOMUX_PADTYPE(17)pad->reg)->bit.e8_e4 = pad->drv_cur;
+        break;
+    case 20:
+        (IOMUX_PADTYPE(20)pad->reg)->bit.e4_e2 = pad->drv_cur;
+        break;
+    case 21:
+        (IOMUX_PADTYPE(21)pad->reg)->bit.e4_e2 = pad->drv_cur;
+        break;
+    default:
+        break;
+    }
 
 }
 
 static void fh_iomux_setpupd(Iomux_Pad *pad)
 {
 
-	switch (pad->reg_type) {
-	case 9:
-		(IOMUX_PADTYPE(9)pad->reg)->bit.pu_pd = pad->pupd;
-		break;
-	case 17:
-		(IOMUX_PADTYPE(17)pad->reg)->bit.pu_pd = pad->pupd;
-		break;
-	case 20:
-		(IOMUX_PADTYPE(20)pad->reg)->bit.pu_pd = pad->pupd;
-		break;
-	case 21:
-		(IOMUX_PADTYPE(21)pad->reg)->bit.pu_pd = pad->pupd;
-		break;
-	default:
-		break;
-	}
+    switch (pad->reg_type) {
+    case 9:
+        (IOMUX_PADTYPE(9)pad->reg)->bit.pu_pd = pad->pupd;
+        break;
+    case 17:
+        (IOMUX_PADTYPE(17)pad->reg)->bit.pu_pd = pad->pupd;
+        break;
+    case 20:
+        (IOMUX_PADTYPE(20)pad->reg)->bit.pu_pd = pad->pupd;
+        break;
+    case 21:
+        (IOMUX_PADTYPE(21)pad->reg)->bit.pu_pd = pad->pupd;
+        break;
+    default:
+        break;
+    }
 
 }
 
 static void fh_iomux_setrest(Iomux_Pad *pad)
 {
 
-	switch (pad->reg_type) {
-	case 5:
-		(IOMUX_PADTYPE(5)pad->reg)->bit.sr = 0;
-		break;
-	case 8:
-		(IOMUX_PADTYPE(8)pad->reg)->bit.sr = 0;
-		break;
-	case 9:
-		(IOMUX_PADTYPE(9)pad->reg)->bit.ie = 1;
-		(IOMUX_PADTYPE(9)pad->reg)->bit.smt = 1;
-		break;
-	case 13:
-		(IOMUX_PADTYPE(13)pad->reg)->bit.ie = 1;
-		(IOMUX_PADTYPE(13)pad->reg)->bit.smt = 1;
-		break;
-	case 17:
-		(IOMUX_PADTYPE(17)pad->reg)->bit.sr = 0;
-		(IOMUX_PADTYPE(17)pad->reg)->bit.ie = 1;
-		(IOMUX_PADTYPE(17)pad->reg)->bit.e = 1;
-		(IOMUX_PADTYPE(17)pad->reg)->bit.smt = 1;
-		break;
-	case 20:
-		(IOMUX_PADTYPE(20)pad->reg)->bit.sr = 0;
-		(IOMUX_PADTYPE(20)pad->reg)->bit.ie = 1;
-		(IOMUX_PADTYPE(20)pad->reg)->bit.smt = 1;
-		break;
-	case 21:
-		(IOMUX_PADTYPE(21)pad->reg)->bit.sr = 0;
-		(IOMUX_PADTYPE(21)pad->reg)->bit.ie = 1;
-		(IOMUX_PADTYPE(21)pad->reg)->bit.smt = 1;
-		break;
-	default:
-		break;
-	}
+    switch (pad->reg_type) {
+    case 5:
+        (IOMUX_PADTYPE(5)pad->reg)->bit.sr = 0;
+        break;
+    case 8:
+        (IOMUX_PADTYPE(8)pad->reg)->bit.sr = 0;
+        break;
+    case 9:
+        (IOMUX_PADTYPE(9)pad->reg)->bit.ie = 1;
+        (IOMUX_PADTYPE(9)pad->reg)->bit.smt = 1;
+        break;
+    case 13:
+        (IOMUX_PADTYPE(13)pad->reg)->bit.ie = 1;
+        (IOMUX_PADTYPE(13)pad->reg)->bit.smt = 1;
+        break;
+    case 17:
+        (IOMUX_PADTYPE(17)pad->reg)->bit.sr = 0;
+        (IOMUX_PADTYPE(17)pad->reg)->bit.ie = 1;
+        (IOMUX_PADTYPE(17)pad->reg)->bit.e = 1;
+        (IOMUX_PADTYPE(17)pad->reg)->bit.smt = 1;
+        break;
+    case 20:
+        (IOMUX_PADTYPE(20)pad->reg)->bit.sr = 0;
+        (IOMUX_PADTYPE(20)pad->reg)->bit.ie = 1;
+        (IOMUX_PADTYPE(20)pad->reg)->bit.smt = 1;
+        break;
+    case 21:
+        (IOMUX_PADTYPE(21)pad->reg)->bit.sr = 0;
+        (IOMUX_PADTYPE(21)pad->reg)->bit.ie = 1;
+        (IOMUX_PADTYPE(21)pad->reg)->bit.smt = 1;
+        break;
+    default:
+        break;
+    }
 
 }
 
@@ -198,13 +198,13 @@ extern const int fh_iomux_cfg_count;
 
 void __fh_setiomux(Iomux_Pad *pad, void *iobase)
 {
-	UINT32 regvalue = 0;
-	pad->reg = ®value;
-	fh_iomux_setmfs(pad);
-	fh_iomux_setcur(pad);
-	fh_iomux_setpupd(pad);
-	fh_iomux_setrest(pad);
-	SET_REG(iobase, regvalue);
+    UINT32 regvalue = 0;
+    pad->reg = ®value;
+    fh_iomux_setmfs(pad);
+    fh_iomux_setcur(pad);
+    fh_iomux_setpupd(pad);
+    fh_iomux_setrest(pad);
+    SET_REG(iobase, regvalue);
 }
 
 static UINT32 g_iomux_base;
@@ -212,73 +212,73 @@ static UINT32 g_iomux_base;
 void fh_iomux_init(UINT32 base)
 {
 
-//	return;
-	int i;
-//	int test_cnt = 0;
-	UINT32 reg;
-	g_iomux_base = base;
+//  return;
+    int i;
+//  int test_cnt = 0;
+    UINT32 reg;
+    g_iomux_base = base;
 
-	iomux_obj.pbase = (void *)base;
+    iomux_obj.pbase = (void *)base;
 
-//	iomux_obj.vbase = (UINT32 *)rt_malloc(1024);
-	iomux_obj.pads = fh_iomux_cfg;
+//  iomux_obj.vbase = (UINT32 *)rt_malloc(1024);
+    iomux_obj.pads = fh_iomux_cfg;
 
-	for (i = 0; i < fh_iomux_cfg_count; i++) {
+    for (i = 0; i < fh_iomux_cfg_count; i++) {
 #if (1)
-		iomux_obj.pads[i].id = i;
-		iomux_obj.pads[i].reg_offset = i * 4;
-		iomux_obj.pads[i].reg = ®//(UINT32 *)(iomux_obj.vbase + iomux_obj.pads[i].reg_offset);
-		fh_iomux_setmfs(&fh_iomux_cfg[i]);
-		fh_iomux_setcur(&fh_iomux_cfg[i]);
-		fh_iomux_setpupd(&fh_iomux_cfg[i]);
-		fh_iomux_setrest(&fh_iomux_cfg[i]);
-		SET_REG(iomux_obj.pbase + iomux_obj.pads[i].reg_offset, reg);
-//			*((UINT32 *)(iomux_obj.vbase + iomux_obj.pads[i].reg_offset)));
-		//rt_kprintf("addr: 0x%x, pmu data: 0x%x\n", iomux_obj.pbase + iomux_obj.pads[i].reg_offset, GET_REG(iomux_obj.pbase + iomux_obj.pads[i].reg_offset));
-//		test_cnt++;
+        iomux_obj.pads[i].id = i;
+        iomux_obj.pads[i].reg_offset = i * 4;
+        iomux_obj.pads[i].reg = ®//(UINT32 *)(iomux_obj.vbase + iomux_obj.pads[i].reg_offset);
+        fh_iomux_setmfs(&fh_iomux_cfg[i]);
+        fh_iomux_setcur(&fh_iomux_cfg[i]);
+        fh_iomux_setpupd(&fh_iomux_cfg[i]);
+        fh_iomux_setrest(&fh_iomux_cfg[i]);
+        SET_REG(iomux_obj.pbase + iomux_obj.pads[i].reg_offset, reg);
+//          *((UINT32 *)(iomux_obj.vbase + iomux_obj.pads[i].reg_offset)));
+        //rt_kprintf("addr: 0x%x, pmu data: 0x%x\n", iomux_obj.pbase + iomux_obj.pads[i].reg_offset, GET_REG(iomux_obj.pbase + iomux_obj.pads[i].reg_offset));
+//      test_cnt++;
 #else
 #ifdef FH_USING_JTAG
-		if (strncmp(fh_iomux_cfg[i].func_name[0], "JTAG", 4) == 0)
-			continue;
+        if (strncmp(fh_iomux_cfg[i].func_name[0], "JTAG", 4) == 0)
+            continue;
 #endif
 /*
-		if (strncmp(fh_iomux_cfg[i].func_name[1], "UART1", 5) == 0)
-			break;
+        if (strncmp(fh_iomux_cfg[i].func_name[1], "UART1", 5) == 0)
+            break;
 */
 
-		__fh_setiomux(&fh_iomux_cfg[i], (void *) base + i * 4);
+        __fh_setiomux(&fh_iomux_cfg[i], (void *) base + i * 4);
 #endif
-	}
+    }
 
 #ifdef CONFIG_RMII
-	//(IOMUX_PADTYPE(17)(iomux_obj.pads[18]).reg)->bit.e = 1;
-	reg = GET_REG(0xf00000a4);
-	reg |= (1 << 13);
-	SET_REG(0xf00000a4, reg);
+    //(IOMUX_PADTYPE(17)(iomux_obj.pads[18]).reg)->bit.e = 1;
+    reg = GET_REG(0xf00000a4);
+    reg |= (1 << 13);
+    SET_REG(0xf00000a4, reg);
 #else
-	//(IOMUX_PADTYPE(17)(iomux_obj.pads[18]).reg)->bit.e = 0;
-	reg = GET_REG(0xf00000a4);
-	reg &= ~(1 << 13);
-	SET_REG(0xf00000a4, reg);
+    //(IOMUX_PADTYPE(17)(iomux_obj.pads[18]).reg)->bit.e = 0;
+    reg = GET_REG(0xf00000a4);
+    reg &= ~(1 << 13);
+    SET_REG(0xf00000a4, reg);
 #endif
 #ifdef IOMUX_DEBUG
-	fh_iomux_print(iomux_obj);
+    fh_iomux_print(iomux_obj);
 #endif
 
 
-	//rt_free(iomux_obj.vbase);
-	//iomux_obj.vbase = 0;
+    //rt_free(iomux_obj.vbase);
+    //iomux_obj.vbase = 0;
 
 }
 
 void fh_iomux_pin_switch(int pin_num, int func_num)
 {
-	RT_ASSERT(pin_num < fh_iomux_cfg_count);
-	__fh_setiomux(&fh_iomux_cfg[pin_num], (void *)g_iomux_base + pin_num * 4);
-	/*
-	   fh_iomux_cfg[pin_num].func_sel = func_num;
-	    fh_iomux_setmfs(&fh_iomux_cfg[pin_num]);
-	    SET_REG(iomux_obj.pbase + iomux_obj.pads[pin_num].reg_offset, *((UINT32 *)(iomux_obj.vbase + iomux_obj.pads[pin_num].reg_offset)));
-	*/
+    RT_ASSERT(pin_num < fh_iomux_cfg_count);
+    __fh_setiomux(&fh_iomux_cfg[pin_num], (void *)g_iomux_base + pin_num * 4);
+    /*
+       fh_iomux_cfg[pin_num].func_sel = func_num;
+        fh_iomux_setmfs(&fh_iomux_cfg[pin_num]);
+        SET_REG(iomux_obj.pbase + iomux_obj.pads[pin_num].reg_offset, *((UINT32 *)(iomux_obj.vbase + iomux_obj.pads[pin_num].reg_offset)));
+    */
 }
 
diff --git a/bsp/fh8620/platform/plat-v2/iomux.h b/bsp/fh8620/platform/plat-v2/iomux.h
index e03273b2b8..a0aa8d338e 100644
--- a/bsp/fh8620/platform/plat-v2/iomux.h
+++ b/bsp/fh8620/platform/plat-v2/iomux.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #ifndef IOMUX_H_
 #define IOMUX_H_
 
@@ -126,179 +126,179 @@
 #define PMU_PAD_MAC_TXER         (92)
 
 
-#define IOMUX_PADTYPE(n)		(Iomux_PadType##n *)
-#define IOMUX_PUPD_NONE			0
-#define IOMUX_PUPD_DOWN			1
-#define IOMUX_PUPD_UP			2
-#define IOMUX_PUPD_KEEPER		3
+#define IOMUX_PADTYPE(n)        (Iomux_PadType##n *)
+#define IOMUX_PUPD_NONE         0
+#define IOMUX_PUPD_DOWN         1
+#define IOMUX_PUPD_UP           2
+#define IOMUX_PUPD_KEEPER       3
 //#define IOMUX_DEBUG
 
 
 typedef union
 {
-	struct
-	{
-		UINT32	sr								:1;
-		UINT32	reserved_3_1					:3;
+    struct
+    {
+        UINT32  sr                              :1;
+        UINT32  reserved_3_1                    :3;
 
-		UINT32	e8_e4							:2;
-		UINT32	reserved_31_6					:24;
+        UINT32  e8_e4                           :2;
+        UINT32  reserved_31_6                   :24;
 
-	}bit;
-	UINT32 dw;
+    }bit;
+    UINT32 dw;
 }Iomux_PadType5;
 
 typedef union
 {
-	struct
-	{
-		UINT32	sr								:1;
-		UINT32	reserved_3_1					:3;
+    struct
+    {
+        UINT32  sr                              :1;
+        UINT32  reserved_3_1                    :3;
 
-		UINT32	e8_e4							:2;
-		UINT32	reserved_7_6					:2;
+        UINT32  e8_e4                           :2;
+        UINT32  reserved_7_6                    :2;
 
-		UINT32	mfs								:1;
-		UINT32	reserved_31_9					:23;
+        UINT32  mfs                             :1;
+        UINT32  reserved_31_9                   :23;
 
-	}bit;
-	UINT32 dw;
+    }bit;
+    UINT32 dw;
 }Iomux_PadType8;
 
 
 typedef union
 {
-	struct
-	{
-		UINT32	smt								:1;
-		UINT32	reserved_3_1					:3;
+    struct
+    {
+        UINT32  smt                             :1;
+        UINT32  reserved_3_1                    :3;
 
-		UINT32	ie								:1;
-		UINT32	reserved_7_5					:3;
+        UINT32  ie                              :1;
+        UINT32  reserved_7_5                    :3;
 
-		UINT32	pu_pd							:2;
-		UINT32	reserved_31_10					:22;
+        UINT32  pu_pd                           :2;
+        UINT32  reserved_31_10                  :22;
 
-	}bit;
-	UINT32 dw;
+    }bit;
+    UINT32 dw;
 }Iomux_PadType9;
 
 
 typedef union
 {
-	struct
-	{
-		UINT32	e4_e2							:2;
-		UINT32	reserved_3_2					:2;
+    struct
+    {
+        UINT32  e4_e2                           :2;
+        UINT32  reserved_3_2                    :2;
 
-		UINT32	smt								:1;
-		UINT32	reserved_7_5					:3;
+        UINT32  smt                             :1;
+        UINT32  reserved_7_5                    :3;
 
-		UINT32	ie								:1;
-		UINT32	reserved_11_9					:3;
+        UINT32  ie                              :1;
+        UINT32  reserved_11_9                   :3;
 
-		UINT32	mfs								:2;
-		UINT32	reserved_31_14					:18;
+        UINT32  mfs                             :2;
+        UINT32  reserved_31_14                  :18;
 
-	}bit;
-	UINT32 dw;
+    }bit;
+    UINT32 dw;
 }Iomux_PadType13;
 
 typedef union
 {
-	struct
-	{
-		UINT32	sr								:1;
-		UINT32	reserved_3_1					:3;
+    struct
+    {
+        UINT32  sr                              :1;
+        UINT32  reserved_3_1                    :3;
 
-		UINT32	e8_e4							:2;
-		UINT32	reserved_7_6					:2;
+        UINT32  e8_e4                           :2;
+        UINT32  reserved_7_6                    :2;
 
-		UINT32	smt								:1;
-		UINT32	reserved_11_9					:3;
+        UINT32  smt                             :1;
+        UINT32  reserved_11_9                   :3;
 
-		UINT32	ie								:1;
-		UINT32	e								:1;	//only for PAD_MAC_REF_CLK_CFG (0x00a4)
-		UINT32	reserved_15_12					:2;
+        UINT32  ie                              :1;
+        UINT32  e                               :1; //only for PAD_MAC_REF_CLK_CFG (0x00a4)
+        UINT32  reserved_15_12                  :2;
 
-		UINT32	pu_pd							:2;
-		UINT32	reserved_31_18					:14;
+        UINT32  pu_pd                           :2;
+        UINT32  reserved_31_18                  :14;
 
-	}bit;
-	UINT32 dw;
+    }bit;
+    UINT32 dw;
 }Iomux_PadType17;
 
 typedef union
 {
-	struct
-	{
-		UINT32	sr								:1;
-		UINT32	reserved_3_1					:3;
+    struct
+    {
+        UINT32  sr                              :1;
+        UINT32  reserved_3_1                    :3;
 
-		UINT32	e4_e2							:2;
-		UINT32	reserved_7_6					:2;
+        UINT32  e4_e2                           :2;
+        UINT32  reserved_7_6                    :2;
 
-		UINT32	smt								:1;
-		UINT32	reserved_11_9					:3;
+        UINT32  smt                             :1;
+        UINT32  reserved_11_9                   :3;
 
-		UINT32	ie								:1;
-		UINT32	reserved_15_13					:3;
+        UINT32  ie                              :1;
+        UINT32  reserved_15_13                  :3;
 
-		UINT32	pu_pd							:2;
-		UINT32	reserved_19_18					:2;
+        UINT32  pu_pd                           :2;
+        UINT32  reserved_19_18                  :2;
 
-		UINT32	mfs								:1;
-		UINT32	reserved_31_21					:11;
+        UINT32  mfs                             :1;
+        UINT32  reserved_31_21                  :11;
 
-	}bit;
-	UINT32 dw;
+    }bit;
+    UINT32 dw;
 }Iomux_PadType20;
 
 
 typedef union
 {
-	struct
-	{
-		UINT32	sr								:1;
-		UINT32	reserved_3_1					:3;
+    struct
+    {
+        UINT32  sr                              :1;
+        UINT32  reserved_3_1                    :3;
 
-		UINT32	e4_e2							:2;
-		UINT32	reserved_7_6					:2;
+        UINT32  e4_e2                           :2;
+        UINT32  reserved_7_6                    :2;
 
-		UINT32	smt								:1;
-		UINT32	reserved_11_9					:3;
+        UINT32  smt                             :1;
+        UINT32  reserved_11_9                   :3;
 
-		UINT32	ie								:1;
-		UINT32	reserved_15_13					:3;
+        UINT32  ie                              :1;
+        UINT32  reserved_15_13                  :3;
 
-		UINT32	pu_pd							:2;
-		UINT32	reserved_19_18					:2;
+        UINT32  pu_pd                           :2;
+        UINT32  reserved_19_18                  :2;
 
-		UINT32	mfs								:2;
-		UINT32	reserved_31_21					:10;
+        UINT32  mfs                             :2;
+        UINT32  reserved_31_21                  :10;
 
-	}bit;
-	UINT32 dw;
+    }bit;
+    UINT32 dw;
 }Iomux_PadType21;
 
 typedef struct
 {
     int id;
-	UINT32* reg;
-	UINT32 reg_offset;
-	char* func_name[4];
-	int reg_type;
-	int func_sel;
-	int drv_cur;
-	int pupd;
-	//UINT32 value;
+    UINT32* reg;
+    UINT32 reg_offset;
+    char* func_name[4];
+    int reg_type;
+    int func_sel;
+    int drv_cur;
+    int pupd;
+    //UINT32 value;
 }Iomux_Pad;
 
 typedef struct
 {
-	void  *vbase;
-	void  *pbase;
-	Iomux_Pad *pads;
+    void  *vbase;
+    void  *pbase;
+    Iomux_Pad *pads;
 }Iomux_Object;
 
 
diff --git a/bsp/fh8620/platform/plat-v2/reset.c b/bsp/fh8620/platform/plat-v2/reset.c
index 654a0745e9..aa7024169f 100644
--- a/bsp/fh8620/platform/plat-v2/reset.c
+++ b/bsp/fh8620/platform/plat-v2/reset.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #include 
 #include 
 #include "fh_pmu.h"
@@ -32,13 +32,13 @@
 
 void machine_reset(void)
 {
-	fh_pmu_write(REG_PMU_SWRST_MAIN_CTRL, 0x7fffffff);
+    fh_pmu_write(REG_PMU_SWRST_MAIN_CTRL, 0x7fffffff);
 }
 
 void machine_shutdown(void)
 {
-	while(1)
-		;
+    while(1)
+        ;
 
 }
 
diff --git a/bsp/fh8620/platform/plat-v2/timer.c b/bsp/fh8620/platform/plat-v2/timer.c
index de831db3c6..96bcc6f39d 100644
--- a/bsp/fh8620/platform/plat-v2/timer.c
+++ b/bsp/fh8620/platform/plat-v2/timer.c
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,7 +18,7 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
@@ -43,48 +43,48 @@ static unsigned long long timestamp;
 
 rt_uint32_t read_pts(void)
 {
-	return GET_REG(REG_PAE_PTS_REG);
+    return GET_REG(REG_PAE_PTS_REG);
 }
 
 unsigned long long get_ticks(void)
 {
-	rt_uint32_t now = read_pts();
-	if (now >= lastdec) {
-		/* normal mode */
-		timestamp += now - lastdec;
-	} else {
-		now = read_pts();
-		if (now >= lastdec)
-			timestamp += now - lastdec;
-		else {
-			/* we have an overflow ... */
-			timestamp += now + 0xffffffff - lastdec;
-		}
-	}
-	lastdec = now;
-	return timestamp / (TICKS_PER_USEC * 10);
+    rt_uint32_t now = read_pts();
+    if (now >= lastdec) {
+        /* normal mode */
+        timestamp += now - lastdec;
+    } else {
+        now = read_pts();
+        if (now >= lastdec)
+            timestamp += now - lastdec;
+        else {
+            /* we have an overflow ... */
+            timestamp += now + 0xffffffff - lastdec;
+        }
+    }
+    lastdec = now;
+    return timestamp / (TICKS_PER_USEC * 10);
 }
 
 void udelay(unsigned long usec)
 {
-	unsigned long long tmp;
-	rt_uint32_t tmo;
-	tmo = (usec + 9) / 10;
-	tmp = get_ticks() + tmo; /* get current timestamp */
+    unsigned long long tmp;
+    rt_uint32_t tmo;
+    tmo = (usec + 9) / 10;
+    tmp = get_ticks() + tmo; /* get current timestamp */
 
-	while (get_ticks() < tmp)
-		/* loop till event */
-		/*NOP*/;
+    while (get_ticks() < tmp)
+        /* loop till event */
+        /*NOP*/;
 }
 
 void rt_timer_handler(int vector, void *param)
 {
-	timer *tim = param;
+    timer *tim = param;
 
-	rt_interrupt_enter();
-	timer_get_eoi(tim);
-	rt_tick_increase();
-	rt_interrupt_leave();
+    rt_interrupt_enter();
+    timer_get_eoi(tim);
+    rt_tick_increase();
+    rt_interrupt_leave();
 }
 
 /**
@@ -92,18 +92,18 @@ void rt_timer_handler(int vector, void *param)
  */
 void rt_hw_timer_init()
 {
-	timer *tim = (timer *) TMR_REG_BASE;
-	timer_init(tim);
-	/* install interrupt handler */
-	rt_hw_interrupt_install(TMR0_IRQn, rt_timer_handler, (void *) tim,
-				"sys_tick");
-	rt_hw_interrupt_umask(TMR0_IRQn);
+    timer *tim = (timer *) TMR_REG_BASE;
+    timer_init(tim);
+    /* install interrupt handler */
+    rt_hw_interrupt_install(TMR0_IRQn, rt_timer_handler, (void *) tim,
+                "sys_tick");
+    rt_hw_interrupt_umask(TMR0_IRQn);
 
-	timer_set_mode(tim, TIMER_MODE_PERIODIC);
-	timer_set_period(tim, RT_TICK_PER_SECOND, TIMER_CLOCK);
-	//timer_set_period(tim, RT_TIMER_TICK_PER_SECOND, TIMER_CLOCK);
-	timer_enable_irq(tim);
-	timer_enable(tim);
+    timer_set_mode(tim, TIMER_MODE_PERIODIC);
+    timer_set_period(tim, RT_TICK_PER_SECOND, TIMER_CLOCK);
+    //timer_set_period(tim, RT_TIMER_TICK_PER_SECOND, TIMER_CLOCK);
+    timer_enable_irq(tim);
+    timer_enable(tim);
 
 }
 
diff --git a/bsp/fh8620/platform/plat-v2/timer.h b/bsp/fh8620/platform/plat-v2/timer.h
index 5ee024a094..bbccdfa826 100644
--- a/bsp/fh8620/platform/plat-v2/timer.h
+++ b/bsp/fh8620/platform/plat-v2/timer.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #ifndef TIMER_H_
 #define TIMER_H_
 
diff --git a/bsp/fh8620/platform/platform_def.h b/bsp/fh8620/platform/platform_def.h
index b511863981..a576220f3e 100644
--- a/bsp/fh8620/platform/platform_def.h
+++ b/bsp/fh8620/platform/platform_def.h
@@ -1,8 +1,8 @@
 /*
  *  This file is part of FH8620 BSP for RT-Thread distribution.
  *
- *	Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. 
- *	All rights reserved
+ *  Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
+ *  All rights reserved
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,12 +18,12 @@
  *  with this program; if not, write to the Free Software Foundation, Inc.,
  *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  *
- *	Visit http://www.fullhan.com to get contact with Fullhan.
+ *  Visit http://www.fullhan.com to get contact with Fullhan.
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #ifndef PLATFORM_DEF_H_
 #define PLATFORM_DEF_H_
 
diff --git a/bsp/fh8620/rtconfig.h b/bsp/fh8620/rtconfig.h
index ea210a4703..78749abdfa 100644
--- a/bsp/fh8620/rtconfig.h
+++ b/bsp/fh8620/rtconfig.h
@@ -5,19 +5,19 @@
 // 
 
 // 
-#define RT_NAME_MAX	16
+#define RT_NAME_MAX 16
 // 
-#define RT_ALIGN_SIZE	4
+#define RT_ALIGN_SIZE   4
 // 
 // 8
 // 32
 // 256
 // 
-#define RT_THREAD_PRIORITY_MAX	256
+#define RT_THREAD_PRIORITY_MAX  256
 // 
-#define RT_TICK_PER_SECOND	100
+#define RT_TICK_PER_SECOND  100
 // 
-#define IDLE_THREAD_STACK_SIZE	512
+#define IDLE_THREAD_STACK_SIZE  512
 // 
 // #define RT_USING_MODULE
 // 
@@ -36,11 +36,11 @@
 // 

 // #define RT_USING_TIMER_SOFT
 // 
-#define RT_TIMER_THREAD_PRIO	4
+#define RT_TIMER_THREAD_PRIO    4
 // 
-#define RT_TIMER_THREAD_STACK_SIZE	512
+#define RT_TIMER_THREAD_STACK_SIZE  512
 // 
-#define RT_TIMER_TICK_PER_SECOND	100
+#define RT_TIMER_TICK_PER_SECOND    100
 // 

 
 // 

@@ -86,13 +86,13 @@
 // 
 //#define RT_USING_RTC
 // 
-#define RT_MMCSD_THREAD_PREORITY	15
+#define RT_MMCSD_THREAD_PREORITY    15
 // 

 #define RT_USING_CONSOLE
 // 
-#define RT_CONSOLEBUF_SIZE	128
+#define RT_CONSOLEBUF_SIZE  128
 // 
-#define RT_CONSOLE_DEVICE_NAME	"uart1"
+#define RT_CONSOLE_DEVICE_NAME  "uart1"
 // 

 
 // 
@@ -105,12 +105,14 @@
 // 
 #define FINSH_USING_DESCRIPTION
 // 
-#define FINSH_THREAD_STACK_SIZE	4096
+#define FINSH_THREAD_STACK_SIZE 4096
 // 

 
 // 

 // 
 #define RT_USING_LIBC
+// 
+#define RT_USING_POSIX
 // 
 #define RT_USING_PTHREADS
 // 
@@ -118,13 +120,13 @@
 // 

 
 // 

-//#define RT_USING_DFS
+#define RT_USING_DFS
 // 
 #define DFS_USING_WORKDIR
 // 
-#define DFS_FILESYSTEMS_MAX	2
+#define DFS_FILESYSTEMS_MAX 2
 // 
-#define DFS_FD_MAX	16
+#define DFS_FD_MAX  16
 // 
 #define RT_USING_DFS_ELMFAT
 // 
@@ -136,13 +138,13 @@
 // 2
 // 3
 // 
-#define RT_DFS_ELM_USE_LFN	3
+#define RT_DFS_ELM_USE_LFN  3
 // 
-#define RT_DFS_ELM_CODE_PAGE	936
+#define RT_DFS_ELM_CODE_PAGE    936
 // 
 #define RT_DFS_ELM_CODE_PAGE_FILE
 // 
-#define RT_DFS_ELM_MAX_LFN	255
+#define RT_DFS_ELM_MAX_LFN  255
 // 
 #define RT_DFS_ELM_MAX_SECTOR_SIZE  4096
 // 
@@ -172,19 +174,19 @@
 // 
 #define RT_LWIP_DHCP
 // 
-#define RT_LWIP_TCPTHREAD_PRIORITY	12
+#define RT_LWIP_TCPTHREAD_PRIORITY  12
 // 
-#define RT_LWIP_TCPTHREAD_MBOX_SIZE	8
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
 // 
-#define RT_LWIP_TCPTHREAD_STACKSIZE	4096
+#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
 // 
-#define RT_LWIP_ETHTHREAD_PRIORITY	14
+#define RT_LWIP_ETHTHREAD_PRIORITY  14
 // 
-#define RT_LWIP_ETHTHREAD_MBOX_SIZE	8
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
 // 
-#define RT_LWIP_ETHTHREAD_STACKSIZE	512
+#define RT_LWIP_ETHTHREAD_STACKSIZE 512
 // 
-#define    RT_LWIP_IPADDR    "192.168.1.30"  
+#define    RT_LWIP_IPADDR    "192.168.1.30"
 // 
 #define    RT_LWIP_GWADDR    "192.168.1.1"
 // 
diff --git a/bsp/frdm-k64f/applications/startup.c b/bsp/frdm-k64f/applications/startup.c
index d16aefddb2..e558cd8cbf 100644
--- a/bsp/frdm-k64f/applications/startup.c
+++ b/bsp/frdm-k64f/applications/startup.c
@@ -73,9 +73,6 @@ void rtthread_startup(void)
     /* init scheduler system */
     rt_system_scheduler_init();
 
-    /* init all device */
-    rt_device_init_all();
-
     /* init application */
     rt_application_init();
 
diff --git a/bsp/frdm-k64f/board/drv_emac.c b/bsp/frdm-k64f/board/drv_emac.c
index 606c141545..6770b0d281 100644
--- a/bsp/frdm-k64f/board/drv_emac.c
+++ b/bsp/frdm-k64f/board/drv_emac.c
@@ -1,7 +1,8 @@
 /*
  * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd
- * 
+ *
  * SPDX-License-Identifier: Apache-2.0
+ *
  * Change Logs:
  * Date           Author       Notes
  * 2015-07-15     Bernard      The first version
@@ -33,7 +34,7 @@
 #define DEBUG_PRINTF(...)
 #endif
 
-#define MAX_ADDR_LEN                6    
+#define MAX_ADDR_LEN                6
 #define ENET_RX_RING_LEN            (16)
 #define ENET_TX_RING_LEN            (8)
 
@@ -45,17 +46,17 @@
 #define ENET_RXBUFF_SIZE            (ENET_FRAME_MAX_FRAMELEN)
 #define ENET_TXBUFF_SIZE            (ENET_FRAME_MAX_FRAMELEN)
 #define ENET_ETH_MAX_FLEN           (1522) // recommended size for a VLAN frame
-    
+
 struct emac_device
 {
     /* inherit from Ethernet device */
     struct eth_device parent;
-    
-	ALIGN(64) enet_rx_bd_struct_t RxBuffDescrip[ENET_RX_RING_LEN];
-	ALIGN(64) enet_tx_bd_struct_t TxBuffDescrip[ENET_TX_RING_LEN];
-	ALIGN(64) uint8_t RxDataBuff[ENET_RX_RING_LEN * ENET_ALIGN(ENET_RXBUFF_SIZE)];
-	ALIGN(64) uint8_t TxDataBuff[ENET_TX_RING_LEN * ENET_ALIGN(ENET_TXBUFF_SIZE)];
-    
+
+    ALIGN(64) enet_rx_bd_struct_t RxBuffDescrip[ENET_RX_RING_LEN];
+    ALIGN(64) enet_tx_bd_struct_t TxBuffDescrip[ENET_TX_RING_LEN];
+    ALIGN(64) uint8_t RxDataBuff[ENET_RX_RING_LEN * ENET_ALIGN(ENET_RXBUFF_SIZE)];
+    ALIGN(64) uint8_t TxDataBuff[ENET_TX_RING_LEN * ENET_ALIGN(ENET_TXBUFF_SIZE)];
+
     enet_handle_t enet_handle;
     rt_uint8_t  dev_addr[MAX_ADDR_LEN];         /* MAC address  */
     struct rt_semaphore tx_wait;
@@ -112,7 +113,7 @@ static void setup_enet_clock_init(void)
 {
     CLOCK_EnableClock(kCLOCK_PortC);
     CLOCK_EnableClock(kCLOCK_PortB);
-    
+
     /* Select the Ethernet timestamp clock source */
     CLOCK_SetEnetTime0Clock(0x2);
 }
@@ -120,7 +121,7 @@ static void setup_enet_clock_init(void)
 static void enet_mac_rx_isr(struct emac_device* emac)
 {
     rt_err_t result;
-    
+
     result = eth_device_ready(&(_emac.parent));
     if( result != RT_EOK )
     {
@@ -136,7 +137,7 @@ static void enet_mac_tx_isr(struct emac_device* emac)
 static void ethernet_callback(ENET_Type *base, enet_handle_t *handle, enet_event_t event, void *param)
 {
     struct emac_device* emac = param;
-    
+
     switch (event)
     {
       case kENET_RxEvent:
@@ -154,7 +155,7 @@ static rt_err_t k64_emac_init(rt_device_t dev)
 {
     struct emac_device* emac = K64_EMAC_DEVICE(dev);
     enet_handle_t * enet_handle = &emac->enet_handle;
-    
+
     bool link = false;
     uint32_t phyAddr = 0;
     phy_speed_t phy_speed;
@@ -167,7 +168,7 @@ static rt_err_t k64_emac_init(rt_device_t dev)
     setup_enet_clock_init();
     /* enable iomux and clock */
     setup_k64_io_enet();
-    
+
     /* prepare the buffer configuration. */
     buffCfg.rxBdNumber = ENET_RX_RING_LEN;                     /* Receive buffer descriptor number. */
     buffCfg.txBdNumber = ENET_TX_RING_LEN;                     /* Transmit buffer descriptor number. */
@@ -177,12 +178,12 @@ static rt_err_t k64_emac_init(rt_device_t dev)
     buffCfg.txBdStartAddrAlign = emac->TxBuffDescrip; /* Aligned transmit buffer descriptor start address. */
     buffCfg.rxBufferAlign = emac->RxDataBuff; /* Receive data buffer start address. */
     buffCfg.txBufferAlign = emac->TxDataBuff; /* Transmit data buffer start address. */
-    
+
     sysClock = CLOCK_GetFreq(kCLOCK_CoreSysClk);
     DEBUG_PRINTF("sysClock: %d\n", sysClock);
-    
+
     ENET_GetDefaultConfig(&config);
-    
+
     PHY_Init(ENET, 0, CLOCK_GetFreq(kCLOCK_CoreSysClk));
     if (PHY_GetLinkStatus(ENET, phyAddr, &link) == kStatus_Success)
     {
@@ -191,7 +192,7 @@ static rt_err_t k64_emac_init(rt_device_t dev)
             DEBUG_PRINTF("phy link up\n");
             /* Get link information from PHY */
             PHY_GetLinkSpeedDuplex(ENET, phyAddr, &phy_speed, &phy_duplex);
-            
+
             /* Change the MII speed and duplex for actual link status. */
             config.miiSpeed = (enet_mii_speed_t)phy_speed;
             config.miiDuplex = (enet_mii_duplex_t)phy_duplex;
@@ -205,7 +206,7 @@ static rt_err_t k64_emac_init(rt_device_t dev)
         config.macSpecialConfig = kENET_ControlFlowControlEnable;
         config.txAccelerConfig = 0;
         config.rxAccelerConfig = kENET_RxAccelMacCheckEnabled;
-        
+
         ENET_Init(ENET, enet_handle, &config, &buffCfg, emac->dev_addr, sysClock);
         ENET_SetCallback(enet_handle, ethernet_callback, emac);
         ENET_ActiveRead(ENET);
@@ -214,7 +215,7 @@ static rt_err_t k64_emac_init(rt_device_t dev)
     {
         DEBUG_PRINTF("read phy failed\n");
     }
-    
+
     return RT_EOK;
 }
 
@@ -244,7 +245,7 @@ static rt_err_t k64_emac_control(rt_device_t dev, int cmd, void *args)
 {
     struct emac_device *emac;
 
-	DEBUG_PRINTF("k64_emac_control\n");
+    DEBUG_PRINTF("k64_emac_control\n");
 
     emac = K64_EMAC_DEVICE(dev);
     RT_ASSERT(emac != RT_NULL);
@@ -270,14 +271,14 @@ static rt_err_t k64_emac_tx(rt_device_t dev, struct pbuf* p)
 
     struct emac_device *emac = K64_EMAC_DEVICE(dev);
     enet_handle_t * enet_handle = &emac->enet_handle;
-    
+
     RT_ASSERT(p != NULL);
 
-	DEBUG_PRINTF("k64_emac_tx: %d\n", p->len);
+    DEBUG_PRINTF("k64_emac_tx: %d\n", p->len);
 
     emac = K64_EMAC_DEVICE(dev);
     RT_ASSERT(emac != RT_NULL);
-    
+
 #ifdef DRV_EMAC_RX_DUMP
     {
         int i;
@@ -290,10 +291,10 @@ static rt_err_t k64_emac_tx(rt_device_t dev, struct pbuf* p)
                 DEBUG_PRINTF("\n");
         }
         DEBUG_PRINTF("\n");
-    }    
+    }
 
 #endif
-    
+
     do
     {
         result = ENET_SendFrame(ENET, enet_handle, p->payload, p->len);
@@ -313,17 +314,17 @@ struct pbuf *k64_emac_rx(rt_device_t dev)
     uint32_t length = 0;
     status_t status;
     enet_data_error_stats_t eErrStatic;
-        
+
     struct pbuf* p = RT_NULL;
     struct emac_device *emac = K64_EMAC_DEVICE(dev);
     enet_handle_t * enet_handle = &emac->enet_handle;
 
     RT_ASSERT(emac != RT_NULL);
     DEBUG_PRINTF("k64_emac_rx\n");
-    
+
     /* Get the Frame size */
     status = ENET_GetRxFrameSize(enet_handle, &length);
-    
+
     if (status == kStatus_ENET_RxFrameError)
     {
         /* Update the received buffer when error happened. */
@@ -331,19 +332,19 @@ struct pbuf *k64_emac_rx(rt_device_t dev)
         ENET_GetRxErrBeforeReadFrame(enet_handle, &eErrStatic);
         /* update the receive buffer. */
         ENET_ReadFrame(ENET, enet_handle, NULL, 0);
-        
+
         DEBUG_PRINTF("receive frame faild\n");
-        
+
         return p;
     }
-    
+
     /* Call ENET_ReadFrame when there is a received frame. */
     if (length != 0)
     {
         /* Received valid frame. Deliver the rx buffer with the size equal to length. */
         p = pbuf_alloc(PBUF_RAW, length, PBUF_POOL);
     }
-    
+
     if (p != NULL)
     {
         status = ENET_ReadFrame(ENET, enet_handle, p->payload, length);
@@ -370,7 +371,7 @@ struct pbuf *k64_emac_rx(rt_device_t dev)
             pbuf_free(p);
         }
     }
- 
+
     return p;
 }
 
@@ -397,7 +398,7 @@ int drv_emac_hw_init(void)
 
     /* init tx semaphore */
     rt_sem_init(&_emac.tx_wait, "tx_wait", ENET_TX_RING_LEN - 1, RT_IPC_FLAG_FIFO);
-    
+
     /* register ETH device */
     eth_device_init(&(_emac.parent), "e0");
 
@@ -409,15 +410,15 @@ INIT_DEVICE_EXPORT(drv_emac_hw_init);
 
 long k64_dump_tx_bd(void)
 {
-	int i;
+    int i;
 
-	enet_tx_bd_struct_t *txbd = _emac.TxBuffDescrip;
+    enet_tx_bd_struct_t *txbd = _emac.TxBuffDescrip;
+
+    for (i = 0; i < ENET_RX_RING_LEN; i++)
+    {
+        DEBUG_PRINTF("status: %04X,  length: %04X, data: %08X\n", txbd[i].control, txbd[i].length, (uint32_t)txbd[i].buffer);
+    }
 
-	for (i = 0; i < ENET_RX_RING_LEN; i++)
-	{
-		DEBUG_PRINTF("status: %04X,  length: %04X, data: %08X\n", txbd[i].control, txbd[i].length, (uint32_t)txbd[i].buffer);
-	}
-    
     return 0;
 }
 FINSH_FUNCTION_EXPORT(k64_dump_tx_bd, dump all receive buffer descriptor);
@@ -425,21 +426,21 @@ MSH_CMD_EXPORT(k64_dump_tx_bd, dump all receive buffer descriptor);
 
 long k64_dump_rx_bd(void)
 {
-	int i;
-	enet_rx_bd_struct_t *rxbd = _emac.RxBuffDescrip;
+    int i;
+    enet_rx_bd_struct_t *rxbd = _emac.RxBuffDescrip;
 
-	for (i = 0; i < ENET_RX_RING_LEN; i++)
-	{
-		DEBUG_PRINTF("bd:%08X, ", (void *)&rxbd[i]);
-		//rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, (void *)&rxbd[i], sizeof(enet_rx_bd_struct_t));
-		DEBUG_PRINTF("status:%04X,  length:%04X, data:%08X ", rxbd[i].control, rxbd[i].length, (uint32_t)rxbd[i].buffer);
+    for (i = 0; i < ENET_RX_RING_LEN; i++)
+    {
+        DEBUG_PRINTF("bd:%08X, ", (void *)&rxbd[i]);
+        //rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, (void *)&rxbd[i], sizeof(enet_rx_bd_struct_t));
+        DEBUG_PRINTF("status:%04X,  length:%04X, data:%08X ", rxbd[i].control, rxbd[i].length, (uint32_t)rxbd[i].buffer);
 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
-		DEBUG_PRINTF("ce:%04X/%04X/%04X ", rxbd[i].controlExtend0, rxbd[i].controlExtend1, rxbd[i].controlExtend2);
-		DEBUG_PRINTF("crc:%04X, len:%04X, type:%04X, ts:%04X", rxbd[i].payloadCheckSum, rxbd[i].headerLength, rxbd[i].protocolTyte, rxbd[i].timestamp);
+        DEBUG_PRINTF("ce:%04X/%04X/%04X ", rxbd[i].controlExtend0, rxbd[i].controlExtend1, rxbd[i].controlExtend2);
+        DEBUG_PRINTF("crc:%04X, len:%04X, type:%04X, ts:%04X", rxbd[i].payloadCheckSum, rxbd[i].headerLength, rxbd[i].protocolTyte, rxbd[i].timestamp);
 #endif
-		DEBUG_PRINTF("\n");
-	}
-    
+        DEBUG_PRINTF("\n");
+    }
+
     return 0;
 }
 FINSH_FUNCTION_EXPORT(k64_dump_rx_bd, dump all receive buffer descriptor);
diff --git a/bsp/frdm-k64f/board/drv_emac.h b/bsp/frdm-k64f/board/drv_emac.h
index e2d0ec8c8c..7cc0a3f09a 100644
--- a/bsp/frdm-k64f/board/drv_emac.h
+++ b/bsp/frdm-k64f/board/drv_emac.h
@@ -1,7 +1,8 @@
 /*
  * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd
- * 
+ *
  * SPDX-License-Identifier: Apache-2.0
+ *
  * Change Logs:
  * Date           Author       Notes
  * 2015-07-15     Bernard      The first version
diff --git a/bsp/gd32103c-eval/Kconfig b/bsp/gd32103c-eval/Kconfig
index 07915b7895..97fb8f2b2c 100644
--- a/bsp/gd32103c-eval/Kconfig
+++ b/bsp/gd32103c-eval/Kconfig
@@ -96,5 +96,14 @@ menu "On-chip Peripheral Drivers"
                 bool "using hwtimer7"
                 default n
         endif
+    config BSP_USING_WDT
+        bool "Enable Watchdog Timer"
+        select RT_USING_WDT
+        default n
+
+    config BSP_USING_RTC
+        bool "using internal rtc"
+        default n
+        select RT_USING_RTC
 
 endmenu
diff --git a/bsp/gd32103c-eval/README.md b/bsp/gd32103c-eval/README.md
index 1f3c3d3425..d55bccd908 100644
--- a/bsp/gd32103c-eval/README.md
+++ b/bsp/gd32103c-eval/README.md
@@ -48,6 +48,8 @@ msh />
 | GPIO      | 支持     |          GPIOA~G           |
 | ADC       | 支持     |          ADC0~1            |
 | HWTIMER   | 支持     |          TIMER0~7          |
+| RTC       | 支持     |          RTC               |
+| WDT       | 支持     |    Free watchdog timer     |
 | IIC       | 未支持   |          I2C0~1            |
 | SPI       | 未支持   |          SPI0~2            |
 | ETH       | 未支持   |                            |
diff --git a/bsp/gd32103c-eval/drivers/SConscript b/bsp/gd32103c-eval/drivers/SConscript
index 35734e9d10..30a1a338d0 100644
--- a/bsp/gd32103c-eval/drivers/SConscript
+++ b/bsp/gd32103c-eval/drivers/SConscript
@@ -24,6 +24,12 @@ if GetDepend('RT_USING_ADC'):
 if GetDepend('RT_USING_HWTIMER'):
     src += ['drv_hwtimer.c']
 
+if GetDepend('RT_USING_RTC'):
+    src += ['drv_rtc.c']
+
+if GetDepend('RT_USING_WDT'):
+    src += ['drv_iwdt.c']
+
 group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
 
 Return('group')
diff --git a/bsp/gd32103c-eval/drivers/drv_gpio.h b/bsp/gd32103c-eval/drivers/drv_gpio.h
index 1240cc4cb2..34d30d63d4 100644
--- a/bsp/gd32103c-eval/drivers/drv_gpio.h
+++ b/bsp/gd32103c-eval/drivers/drv_gpio.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/gd32103c-eval/drivers/drv_iwdt.c b/bsp/gd32103c-eval/drivers/drv_iwdt.c
new file mode 100644
index 0000000000..f218f46104
--- /dev/null
+++ b/bsp/gd32103c-eval/drivers/drv_iwdt.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-03-03     iysheng           first version
+ */
+
+#include 
+
+#define DBG_TAG             "drv.wdt"
+#define DBG_LVL             DBG_INFO
+#include 
+
+#ifdef RT_USING_WDT
+
+typedef struct {
+    struct rt_watchdog_device wdt;
+    rt_uint32_t min_threshold_s;
+    rt_uint32_t max_threshold_s;
+    rt_uint32_t current_threshold_s;
+} gd32_wdt_device_t;
+
+static gd32_wdt_device_t g_wdt_dev;
+
+static rt_err_t gd32_iwdt_init(rt_watchdog_t *wdt)
+{
+    rcu_osci_on(RCU_IRC40K);
+    if (ERROR == rcu_osci_stab_wait(RCU_IRC40K))
+    {
+        LOG_E("failed init IRC40K clock for free watchdog.");
+        return -EINVAL;
+    }
+
+    g_wdt_dev.min_threshold_s = 1;
+    g_wdt_dev.max_threshold_s = (0xfff << 8) / 40000;
+    LOG_I("threshold section [%u, %d]", \
+        g_wdt_dev.min_threshold_s, g_wdt_dev.max_threshold_s);
+
+    IWDG_Write_Enable(IWDG_WRITEACCESS_ENABLE);
+    IWDG_SetPrescaler(IWDG_PRESCALER_256);
+    IWDG_SetReloadValue(0xfff);
+    IWDG_Write_Enable(IWDG_WRITEACCESS_DISABLE);
+
+    return 0;
+}
+
+static rt_err_t gd32_iwdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
+{
+    rt_uint32_t param;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_WDT_KEEPALIVE:
+        IWDG_ReloadCounter();
+        break;
+    case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
+        param = *(rt_uint32_t *) arg;
+        if ((param > g_wdt_dev.max_threshold_s) || \
+            (param < g_wdt_dev.min_threshold_s))
+        {
+            LOG_E("invalid param@%u.", param);
+            return -E2BIG;
+        }
+        else
+        {
+            g_wdt_dev.current_threshold_s = param;
+        }
+        IWDG_Write_Enable(IWDG_WRITEACCESS_ENABLE);
+        IWDG_SetReloadValue(param * 40000 >> 8);
+        IWDG_Write_Enable(IWDG_WRITEACCESS_DISABLE);
+        break;
+    case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
+        *(rt_uint32_t *)arg = g_wdt_dev.current_threshold_s;
+        break;
+    case RT_DEVICE_CTRL_WDT_START:
+        IWDG_Enable();
+        break;
+    default:
+        LOG_W("This command is not supported.");
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+static struct rt_watchdog_ops g_wdt_ops = {
+    gd32_iwdt_init,
+    gd32_iwdt_control,
+};
+
+static int rt_hw_iwdt_init(void)
+{
+    rt_err_t ret;
+
+    g_wdt_dev.wdt.ops = &g_wdt_ops;
+    /* register watchdog device */
+    if (rt_hw_watchdog_register(&g_wdt_dev.wdt, "iwdt", \
+        RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK)
+    {
+        LOG_E("wdt device register failed.");
+        return -RT_ERROR;
+    }
+    LOG_D("wdt device register success.");
+
+    return ret;
+}
+INIT_BOARD_EXPORT(rt_hw_iwdt_init);
+#endif
diff --git a/bsp/gd32103c-eval/drivers/drv_rtc.c b/bsp/gd32103c-eval/drivers/drv_rtc.c
new file mode 100644
index 0000000000..95c6e56e9d
--- /dev/null
+++ b/bsp/gd32103c-eval/drivers/drv_rtc.c
@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-02-20     iysheng           first version
+ */
+
+#include 
+#include 
+#include 
+
+#define DBG_TAG             "drv.rtc"
+#define DBG_LVL             DBG_INFO
+
+#include 
+
+#ifdef RT_USING_RTC
+
+typedef struct {
+    struct rt_device rtc_dev;
+} gd32_rtc_device;
+
+static gd32_rtc_device g_gd32_rtc_dev;
+
+static time_t get_rtc_timestamp(void)
+{
+    time_t rtc_counter;
+
+    rtc_counter = (time_t)RTC_GetCounter();
+
+    return rtc_counter;
+}
+
+static rt_err_t set_rtc_timestamp(time_t time_stamp)
+{
+    uint32_t rtc_counter;
+
+    rtc_counter = (uint32_t)time_stamp;
+
+    /* wait until LWOFF bit in RTC_CTL to 1 */
+    RTC_WaitLWOFF();
+    /* enter configure mode */
+    RTC_EnterConfigMode();
+    /* write data to rtc register */
+    RTC_SetCounter(rtc_counter);
+    /* exit configure mode */
+    RTC_ExitConfigMode();
+    /* wait until LWOFF bit in RTC_CTL to 1 */
+    RTC_WaitLWOFF();
+
+    return RT_EOK;
+}
+
+static rt_err_t rt_gd32_rtc_control(rt_device_t dev, int cmd, void *args)
+{
+    rt_err_t result = RT_EOK;
+
+    RT_ASSERT(dev != RT_NULL);
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_RTC_GET_TIME:
+        *(rt_uint32_t *)args = get_rtc_timestamp();
+        break;
+
+    case RT_DEVICE_CTRL_RTC_SET_TIME:
+        if (set_rtc_timestamp(*(rt_uint32_t *)args))
+        {
+            result = -RT_ERROR;
+        }
+        break;
+    }
+
+    return result;
+}
+
+#ifdef RT_USING_DEVICE_OPS
+const static struct rt_device_ops g_gd32_rtc_ops =
+{
+    RT_NULL,
+    RT_NULL,
+    RT_NULL,
+    RT_NULL,
+    RT_NULL,
+    rt_gd32_rtc_control
+};
+#endif
+
+static int rt_hw_rtc_init(void)
+{
+    rt_err_t ret;
+    time_t rtc_counter;
+
+    rcu_periph_clock_enable(RCU_PMU);
+    PWR_BackupAccess_Enable(ENABLE);
+    rcu_periph_clock_enable(RCU_BKPI);
+
+    rtc_counter = get_rtc_timestamp();
+    /* once the rtc clock source has been selected, if can't be changed
+     * anymore unless the Backup domain is reset */
+    rcu_bkp_reset_enable();
+    rcu_bkp_reset_disable();
+    rcu_periph_clock_enable(RCU_RTC);
+    rcu_osci_on(RCU_LXTAL);
+    if (SUCCESS == rcu_osci_stab_wait(RCU_LXTAL))
+    {
+        /* set lxtal as rtc clock source */
+        rcu_rtc_clock_config(RCU_RTCSRC_LXTAL);
+    }
+    set_rtc_timestamp(rtc_counter);
+
+#ifdef RT_USING_DEVICE_OPS
+    g_gd32_rtc_dev.rtc_dev.ops         = &g_gd32_rtc_ops;
+#else
+    g_gd32_rtc_dev.rtc_dev.init        = RT_NULL;
+    g_gd32_rtc_dev.rtc_dev.open        = RT_NULL;
+    g_gd32_rtc_dev.rtc_dev.close       = RT_NULL;
+    g_gd32_rtc_dev.rtc_dev.read        = RT_NULL;
+    g_gd32_rtc_dev.rtc_dev.write       = RT_NULL;
+    g_gd32_rtc_dev.rtc_dev.control     = rt_gd32_rtc_control;
+#endif
+    g_gd32_rtc_dev.rtc_dev.type        = RT_Device_Class_RTC;
+    g_gd32_rtc_dev.rtc_dev.rx_indicate = RT_NULL;
+    g_gd32_rtc_dev.rtc_dev.tx_complete = RT_NULL;
+    g_gd32_rtc_dev.rtc_dev.user_data   = RT_NULL;
+
+    ret = rt_device_register(&g_gd32_rtc_dev.rtc_dev, "rtc", \
+        RT_DEVICE_FLAG_RDWR);
+    if (ret != RT_EOK)
+    {
+        LOG_E("failed register internal rtc device, err=%d", ret);
+    }
+
+    return ret;
+}
+INIT_DEVICE_EXPORT(rt_hw_rtc_init);
+#endif
diff --git a/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/GCC/startup_gd32f30x_hd.S b/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/GCC/startup_gd32f30x_hd.S
index 123c92182c..9d88020123 100644
--- a/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/GCC/startup_gd32f30x_hd.S
+++ b/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/GCC/startup_gd32f30x_hd.S
@@ -1,21 +1,7 @@
 ;/*
-; * File      : startup_gd32f30x_hd.s
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
+; * Copyright (c) 2006-2021, RT-Thread Development Team
 ; *
-; *  This program is free software; you can redistribute it and/or modify
-; *  it under the terms of the GNU General Public License as published by
-; *  the Free Software Foundation; either version 2 of the License, or
-; *  (at your option) any later version.
-; *
-; *  This program is distributed in the hope that it will be useful,
-; *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-; *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-; *  GNU General Public License for more details.
-; *
-; *  You should have received a copy of the GNU General Public License along
-; *  with this program; if not, write to the Free Software Foundation, Inc.,
-; *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
@@ -34,7 +20,7 @@
     .type  g_pfnVectors, %object
 
 g_pfnVectors:
-    .word     _estack                      	// Top of Stack
+    .word     _estack                       // Top of Stack
     .word     Reset_Handler                     // Reset Handler
     .word     NMI_Handler                       // NMI Handler
     .word     HardFault_Handler                 // Hard Fault Handler
@@ -78,7 +64,7 @@ g_pfnVectors:
     .word     EXTI5_9_IRQHandler                // 39:EXTI5 to EXTI9
     .word     TIMER0_BRK_IRQHandler             // 40:TIMER0 Break
     .word     TIMER0_UP_IRQHandler              // 41:TIMER0 Update
-    .word     TIMER0_TRG_CMT_IRQHandler         // 42:TIMER0 Trigger and Commutation 
+    .word     TIMER0_TRG_CMT_IRQHandler         // 42:TIMER0 Trigger and Commutation
     .word     TIMER0_Channel_IRQHandler         // 43:TIMER0 Channel Capture Compare
     .word     TIMER1_IRQHandler                 // 44:TIMER1
     .word     TIMER2_IRQHandler                 // 45:TIMER2
@@ -95,8 +81,8 @@ g_pfnVectors:
     .word     EXTI10_15_IRQHandler              // 56:EXTI10 to EXTI15
     .word     RTC_Alarm_IRQHandler              // 57:RTC Alarm
     .word     USBD_WKUP_IRQHandler              // 58:USBD Wakeup
-    .word     TIMER7_BRK_IRQHandler             // 59:TIMER7 Break 
-    .word     TIMER7_UP_IRQHandler              // 60:TIMER7 Update 
+    .word     TIMER7_BRK_IRQHandler             // 59:TIMER7 Break
+    .word     TIMER7_UP_IRQHandler              // 60:TIMER7 Update
     .word     TIMER7_TRG_CMT_IRQHandler         // 61:TIMER7 Trigger and Commutation
     .word     TIMER7_Channel_IRQHandler         // 62:TIMER7 Channel Capture Compare
     .word     ADC2_IRQHandler                   // 63:ADC2
@@ -106,7 +92,7 @@ g_pfnVectors:
     .word     SPI2_IRQHandler                   // 67:SPI2
     .word     UART3_IRQHandler                  // 68:UART3
     .word     UART4_IRQHandler                  // 69:UART4
-    .word     TIMER5_IRQHandler                 // 70:TIMER5 
+    .word     TIMER5_IRQHandler                 // 70:TIMER5
     .word     TIMER6_IRQHandler                 // 71:TIMER6
     .word     DMA1_Channel0_IRQHandler          // 72:DMA1 Channel0
     .word     DMA1_Channel1_IRQHandler          // 73:DMA1 Channel1
@@ -166,13 +152,13 @@ MemManage_Handler:
 BusFault_Handler:
     b       .
     .size   BusFault_Handler, . - BusFault_Handler
-    
+
     .weak   UsageFault_Handler
     .type   UsageFault_Handler, %function
 UsageFault_Handler:
     b       .
     .size   UsageFault_Handler, . - UsageFault_Handler
-    
+
     .weak   SVC_Handler
     .type   SVC_Handler, %function
 SVC_Handler:
@@ -190,13 +176,13 @@ DebugMon_Handler:
 PendSV_Handler:
     b       .
     .size   PendSV_Handler, . - PendSV_Handler
-    
+
     .weak   SysTick_Handler
     .type   SysTick_Handler, %function
 SysTick_Handler:
     b       .
     .size   SysTick_Handler, . - SysTick_Handler
-    
+
     /* IQR Handler */
     .section  .text.Default_Handler,"ax",%progbits
     .type  Default_Handler, %function
diff --git a/bsp/gd32303e-eval/applications/main.c b/bsp/gd32303e-eval/applications/main.c
index 6e190ae3cc..e9947e89d3 100644
--- a/bsp/gd32303e-eval/applications/main.c
+++ b/bsp/gd32303e-eval/applications/main.c
@@ -1,11 +1,7 @@
 /*
- * File      : main.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/gd32303e-eval/drivers/board.c b/bsp/gd32303e-eval/drivers/board.c
index 9ca024ec48..5910ec4124 100644
--- a/bsp/gd32303e-eval/drivers/board.c
+++ b/bsp/gd32303e-eval/drivers/board.c
@@ -1,11 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -79,7 +75,7 @@ void rt_hw_board_init()
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
 
-#ifdef RT_USING_HEAP   
+#ifdef RT_USING_HEAP
     rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END);
 #endif
 }
diff --git a/bsp/gd32303e-eval/drivers/board.h b/bsp/gd32303e-eval/drivers/board.h
index 5e1f15cd5d..208f3f4c6a 100644
--- a/bsp/gd32303e-eval/drivers/board.h
+++ b/bsp/gd32303e-eval/drivers/board.h
@@ -1,11 +1,7 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -19,7 +15,7 @@
 #include 
 
 //  Internal SRAM memory size[Kbytes] <8-64>
-//	Default: 64
+//  Default: 64
 #ifdef __ICCARM__
 // Use *.icf ram symbal, to avoid hardcode.
 extern char __ICFEDIT_region_RAM_end__;
diff --git a/bsp/gd32303e-eval/drivers/drv_gpio.c b/bsp/gd32303e-eval/drivers/drv_gpio.c
index b7285513d3..a96cecc13e 100644
--- a/bsp/gd32303e-eval/drivers/drv_gpio.c
+++ b/bsp/gd32303e-eval/drivers/drv_gpio.c
@@ -1,11 +1,7 @@
 /*
- * File      : drv_gpio.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2015, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author            Notes
@@ -261,7 +257,7 @@ void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
     /* GPIO Periph clock enable */
     rcu_periph_clock_enable(index->clk);
     pin_mode = GPIO_MODE_OUT_PP;
-    
+
    switch(mode)
    {
    case PIN_MODE_OUTPUT:
@@ -442,7 +438,7 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_
             return RT_EINVAL;
         }
         irqmap = &pin_irq_map[hdr_index];
-   
+
         switch (pin_irq_hdr_tab[hdr_index].mode)
         {
             case PIN_IRQ_MODE_RISING:
@@ -463,14 +459,14 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_
 
         /* enable and set interrupt priority */
         nvic_irq_enable(irqmap->irqno, 5U, 0U);
-        
+
         /* connect EXTI line to  GPIO pin */
         gpio_exti_source_select(index->port_src, index->pin_src);
 
         /* configure EXTI line */
         exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode);
         exti_interrupt_flag_clear((exti_line_enum)(index->pin));
-        
+
         rt_hw_interrupt_enable(level);
     }
     else if (enabled == PIN_IRQ_DISABLE)
@@ -505,7 +501,7 @@ int rt_hw_pin_init(void)
     int result;
 
     result = rt_device_pin_register("pin", &_gd32_pin_ops, RT_NULL);
-    
+
     return result;
 }
 INIT_BOARD_EXPORT(rt_hw_pin_init);
@@ -524,7 +520,7 @@ void GD32_GPIO_EXTI_IRQHandler(rt_int8_t exti_line)
     {
         pin_irq_hdr(exti_line);
         exti_interrupt_flag_clear((exti_line_enum)(1 << exti_line));
-    } 
+    }
 }
 void EXTI0_IRQHandler(void)
 {
diff --git a/bsp/gd32303e-eval/drivers/drv_gpio.h b/bsp/gd32303e-eval/drivers/drv_gpio.h
index bca532ff2d..ae9bda7dce 100644
--- a/bsp/gd32303e-eval/drivers/drv_gpio.h
+++ b/bsp/gd32303e-eval/drivers/drv_gpio.h
@@ -1,11 +1,7 @@
 /*
- * File      : drv_gpio.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2015, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/gd32303e-eval/drivers/drv_i2c.c b/bsp/gd32303e-eval/drivers/drv_i2c.c
index 059b211c01..e7587618fe 100644
--- a/bsp/gd32303e-eval/drivers/drv_i2c.c
+++ b/bsp/gd32303e-eval/drivers/drv_i2c.c
@@ -1,21 +1,7 @@
 /*
- * File      : drv_i2c.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -168,7 +154,7 @@ static int gd32_i2c_read(rt_uint32_t i2c_periph, rt_uint16_t slave_address, rt_u
             *p_buffer = i2c_data_receive(i2c_periph);
 
             /* point to the next location where the byte read will be saved */
-            p_buffer++; 
+            p_buffer++;
 
             /* decrement the read bytes counter */
             data_byte--;
@@ -277,7 +263,7 @@ static rt_size_t gd32_i2c_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg
             }
         }
     }
-    
+
     ret = i;
 
 out:
@@ -287,7 +273,7 @@ out:
 }
 
 static const struct rt_i2c_bus_device_ops i2c_ops =
-{ 
+{
     gd32_i2c_xfer,
     RT_NULL,
     RT_NULL
@@ -324,7 +310,7 @@ int rt_hw_i2c_init(void)
 
         i2c_device.priv = (void *)&_i2c_bit_ops;
         rt_i2c_bit_add_bus(&i2c_device, I2C_BUS_NAME);
-    } 
+    }
 
 #else   /* register hardware I2C */
 
diff --git a/bsp/gd32303e-eval/drivers/drv_i2c.h b/bsp/gd32303e-eval/drivers/drv_i2c.h
index 2cc86ace3c..c4b321594c 100644
--- a/bsp/gd32303e-eval/drivers/drv_i2c.h
+++ b/bsp/gd32303e-eval/drivers/drv_i2c.h
@@ -1,21 +1,7 @@
 /*
- * File      : drv_i2c.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/gd32303e-eval/drivers/drv_spi.c b/bsp/gd32303e-eval/drivers/drv_spi.c
index e5df557ae8..96f53b5019 100644
--- a/bsp/gd32303e-eval/drivers/drv_spi.c
+++ b/bsp/gd32303e-eval/drivers/drv_spi.c
@@ -1,11 +1,7 @@
 /*
- * File      : drv_spi.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017 RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -119,7 +115,7 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat
             spi_init_struct.prescale = SPI_PSC_256;
         }
     } /* baudrate */
-    
+
     switch(configuration->mode & RT_SPI_MODE_3)
     {
     case RT_SPI_MODE_0:
@@ -135,7 +131,7 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat
         spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE;
         break;
     }
-    
+
     /* MSB or LSB */
     if(configuration->mode & RT_SPI_MSB)
     {
@@ -145,7 +141,7 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat
     {
         spi_init_struct.endian = SPI_ENDIAN_LSB;
     }
-    
+
     spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX;
     spi_init_struct.device_mode = SPI_MASTER;
     spi_init_struct.nss = SPI_NSS_SOFT;
@@ -181,7 +177,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
             const rt_uint8_t * send_ptr = message->send_buf;
             rt_uint8_t * recv_ptr = message->recv_buf;
             rt_uint32_t size = message->length;
-            
+
             DEBUG_PRINTF("spi poll transfer start: %d\n", size);
 
             while(size--)
@@ -192,7 +188,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
                 {
                     data = *send_ptr++;
                 }
-                
+
                 // Todo: replace register read/write by gd32f3 lib
                 //Wait until the transmit buffer is empty
                 while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE));
@@ -267,8 +263,8 @@ int gd32_hw_spi_init(void)
     rcu_periph_clock_enable(RCU_SPI0);
     /* SPI0_SCK(PA5), SPI0_MISO(PA6) and SPI0_MOSI(PA7) GPIO pin configuration */
     gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_5 | GPIO_PIN_7);
-    gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_6); 
-    
+    gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_6);
+
 #endif
 #ifdef RT_USING_SPI1
     static struct rt_spi_bus spi_bus1;
@@ -287,7 +283,7 @@ int gd32_hw_spi_init(void)
     static struct rt_spi_bus spi_bus2;
     spi_bus2.parent.user_data = (void *)SPI2;
 
-    result = rt_spi_bus_register(&spi_bus2, "spi2", &gd32_spi_ops); 
+    result = rt_spi_bus_register(&spi_bus2, "spi2", &gd32_spi_ops);
 
     rcu_periph_clock_enable(RCU_SPI2);
     rcu_periph_clock_enable(RCU_GPIOB);
diff --git a/bsp/gd32303e-eval/drivers/drv_spi.h b/bsp/gd32303e-eval/drivers/drv_spi.h
index 69b07b70af..ba8e55916a 100644
--- a/bsp/gd32303e-eval/drivers/drv_spi.h
+++ b/bsp/gd32303e-eval/drivers/drv_spi.h
@@ -1,11 +1,7 @@
 /*
- * File      : gd32f30x_spi.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/gd32303e-eval/drivers/drv_spi_flash.c b/bsp/gd32303e-eval/drivers/drv_spi_flash.c
index 54e6be30ef..64d4b32be3 100644
--- a/bsp/gd32303e-eval/drivers/drv_spi_flash.c
+++ b/bsp/gd32303e-eval/drivers/drv_spi_flash.c
@@ -1,11 +1,7 @@
 /*
- * File      : stm32f20x_40x_spi.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -30,7 +26,7 @@ static int rt_hw_gd25q40_init(void)
     static rt_base_t gd25q_cs_pin;                       /* SPI设备CS片选引脚 */
 
     gd25q_cs_pin = GD25Q_SPI_CS_PIN;
-    
+
     rt_pin_mode(GD25Q_SPI_CS_PIN, GPIO_MODE_OUT_PP);
 
     res = rt_spi_bus_attach_device(&spi_dev_gd25q, SPI_DEVICE_NAME, SPI_BUS_NAME, (void*)gd25q_cs_pin);
diff --git a/bsp/gd32303e-eval/drivers/drv_usart.c b/bsp/gd32303e-eval/drivers/drv_usart.c
index 436f86fcb6..07077f5cba 100644
--- a/bsp/gd32303e-eval/drivers/drv_usart.c
+++ b/bsp/gd32303e-eval/drivers/drv_usart.c
@@ -1,11 +1,7 @@
 /*
- * File      : drv_usart.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -44,7 +40,7 @@ struct gd32_uart
     uint32_t tx_port;
     uint16_t tx_pin;
     uint32_t rx_port;
-    uint16_t rx_pin; 
+    uint16_t rx_pin;
 
     struct rt_serial_device * serial;
     char *device_name;
@@ -143,7 +139,7 @@ static const struct gd32_uart uarts[] = {
         "uart0",
     },
     #endif
-    
+
     #ifdef RT_USING_USART1
     {
         USART1,                                 // uart peripheral index
@@ -155,7 +151,7 @@ static const struct gd32_uart uarts[] = {
         "uart1",
     },
     #endif
-    
+
     #ifdef RT_USING_USART2
     {
         USART2,                                 // uart peripheral index
@@ -167,7 +163,7 @@ static const struct gd32_uart uarts[] = {
         "uart2",
     },
     #endif
-    
+
     #ifdef RT_USING_UART3
     {
         UART3,                                 // uart peripheral index
@@ -179,7 +175,7 @@ static const struct gd32_uart uarts[] = {
         "uart3",
     },
     #endif
-    
+
     #ifdef RT_USING_UART4
     {
         UART4,                                 // uart peripheral index
@@ -228,9 +224,9 @@ static rt_err_t gd32_configure(struct rt_serial_device *serial, struct serial_co
     RT_ASSERT(cfg != RT_NULL);
 
     uart = (struct gd32_uart *)serial->parent.user_data;
-    
+
     gd32_uart_gpio_init(uart);
-    
+
     usart_baudrate_set(uart->uart_periph, cfg->baud_rate);
 
     switch (cfg->data_bits)
@@ -310,7 +306,7 @@ static int gd32_putc(struct rt_serial_device *serial, char ch)
 
     usart_data_transmit(uart->uart_periph, ch);
     while((usart_flag_get(uart->uart_periph, USART_FLAG_TC) == RESET));
-    
+
     return 1;
 }
 
diff --git a/bsp/gd32303e-eval/drivers/drv_usart.h b/bsp/gd32303e-eval/drivers/drv_usart.h
index 2158016272..4059092706 100644
--- a/bsp/gd32303e-eval/drivers/drv_usart.h
+++ b/bsp/gd32303e-eval/drivers/drv_usart.h
@@ -1,11 +1,7 @@
 /*
- * File      : drv_usart.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/gd32303e-eval/drivers/gd32f303e_eval.c b/bsp/gd32303e-eval/drivers/gd32f303e_eval.c
index 0829f0bf00..c8982455a2 100644
--- a/bsp/gd32303e-eval/drivers/gd32f303e_eval.c
+++ b/bsp/gd32303e-eval/drivers/gd32f303e_eval.c
@@ -23,15 +23,15 @@ static uint32_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN};
 static uint32_t COM_GPIO_PORT[COMn] = {EVAL_COM1_GPIO_PORT, EVAL_COM2_GPIO_PORT};
 static rcu_periph_enum COM_GPIO_CLK[COMn] = {EVAL_COM1_GPIO_CLK, EVAL_COM2_GPIO_CLK};
 
-static rcu_periph_enum GPIO_CLK[LEDn] = {LED2_GPIO_CLK, LED3_GPIO_CLK, 
+static rcu_periph_enum GPIO_CLK[LEDn] = {LED2_GPIO_CLK, LED3_GPIO_CLK,
                                          LED4_GPIO_CLK, LED5_GPIO_CLK};
 
-static uint32_t KEY_PORT[KEYn] = {WAKEUP_KEY_GPIO_PORT, 
+static uint32_t KEY_PORT[KEYn] = {WAKEUP_KEY_GPIO_PORT,
                                   TAMPER_KEY_GPIO_PORT,
                                   USER_KEY1_GPIO_PORT,
                                   USER_KEY2_GPIO_PORT};
 static uint32_t KEY_PIN[KEYn] = {WAKEUP_KEY_PIN, TAMPER_KEY_PIN,USER_KEY1_PIN,USER_KEY2_PIN};
-static rcu_periph_enum KEY_CLK[KEYn] = {WAKEUP_KEY_GPIO_CLK, 
+static rcu_periph_enum KEY_CLK[KEYn] = {WAKEUP_KEY_GPIO_CLK,
                                         TAMPER_KEY_GPIO_CLK,
                                         USER_KEY1_GPIO_CLK,
                                         USER_KEY2_GPIO_CLK};
@@ -47,7 +47,7 @@ static uint8_t KEY_PIN_SOURCE[KEYn] = {WAKEUP_KEY_EXTI_PIN_SOURCE,
                                        TAMPER_KEY_EXTI_PIN_SOURCE,
                                        USER_KEY1_EXTI_PIN_SOURCE,
                                        USER_KEY2_EXTI_PIN_SOURCE};
-static uint8_t KEY_IRQn[KEYn] = {WAKEUP_KEY_EXTI_IRQn, 
+static uint8_t KEY_IRQn[KEYn] = {WAKEUP_KEY_EXTI_IRQn,
                                  TAMPER_KEY_EXTI_IRQn,
                                  USER_KEY1_EXTI_IRQn,
                                  USER_KEY2_EXTI_IRQn};
@@ -66,7 +66,7 @@ void  gd_eval_led_init (led_typedef_enum lednum)
 {
     /* enable the led clock */
     rcu_periph_clock_enable(GPIO_CLK[lednum]);
-    /* configure led GPIO port */ 
+    /* configure led GPIO port */
     gpio_init(GPIO_PORT[lednum], GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ,GPIO_PIN[lednum]);
 
     GPIO_BC(GPIO_PORT[lednum]) = GPIO_PIN[lednum];
@@ -114,7 +114,7 @@ void gd_eval_led_off(led_typedef_enum lednum)
 */
 void gd_eval_led_toggle(led_typedef_enum lednum)
 {
-    gpio_bit_write(GPIO_PORT[lednum], GPIO_PIN[lednum], 
+    gpio_bit_write(GPIO_PORT[lednum], GPIO_PIN[lednum],
                     (bit_status)(1-gpio_input_bit_get(GPIO_PORT[lednum], GPIO_PIN[lednum])));
 }
 
@@ -184,7 +184,7 @@ void gd_eval_com_init(uint32_t com)
     }else if(EVAL_COM2 == com){
         com_id = 1U;
     }
-    
+
     /* enable GPIO clock */
     rcu_periph_clock_enable(COM_GPIO_CLK[com_id]);
 
diff --git a/bsp/gd32303e-eval/drivers/gd32f303e_eval.h b/bsp/gd32303e-eval/drivers/gd32f303e_eval.h
index e841fb00f4..932102cbd7 100644
--- a/bsp/gd32303e-eval/drivers/gd32f303e_eval.h
+++ b/bsp/gd32303e-eval/drivers/gd32f303e_eval.h
@@ -17,9 +17,9 @@
 #endif
 
 #include "gd32f30x.h"
-     
+
 /* exported types */
-typedef enum 
+typedef enum
 {
     LED2 = 0,
     LED3 = 1,
@@ -27,7 +27,7 @@ typedef enum
     LED5 = 3
 } led_typedef_enum;
 
-typedef enum 
+typedef enum
 {
     KEY_WAKEUP = 0,
     KEY_TAMPER = 1,
@@ -35,7 +35,7 @@ typedef enum
     KEY_USER2 = 3
 } key_typedef_enum;
 
-typedef enum 
+typedef enum
 {
     KEY_MODE_GPIO = 0,
     KEY_MODE_EXTI = 1
@@ -47,15 +47,15 @@ typedef enum
 #define LED2_PIN                         GPIO_PIN_0
 #define LED2_GPIO_PORT                   GPIOF
 #define LED2_GPIO_CLK                    RCU_GPIOF
-  
+
 #define LED3_PIN                         GPIO_PIN_1
 #define LED3_GPIO_PORT                   GPIOF
 #define LED3_GPIO_CLK                    RCU_GPIOF
-  
+
 #define LED4_PIN                         GPIO_PIN_2
 #define LED4_GPIO_PORT                   GPIOF
 #define LED4_GPIO_CLK                    RCU_GPIOF
-  
+
 #define LED5_PIN                         GPIO_PIN_3
 #define LED5_GPIO_PORT                   GPIOF
 #define LED5_GPIO_CLK                    RCU_GPIOF
@@ -85,7 +85,7 @@ typedef enum
 #define WAKEUP_KEY_EXTI_LINE             EXTI_0
 #define WAKEUP_KEY_EXTI_PORT_SOURCE      GPIO_PORT_SOURCE_GPIOA
 #define WAKEUP_KEY_EXTI_PIN_SOURCE       GPIO_PIN_SOURCE_0
-#define WAKEUP_KEY_EXTI_IRQn             EXTI0_IRQn  
+#define WAKEUP_KEY_EXTI_IRQn             EXTI0_IRQn
 
 /* tamper push-button */
 #define TAMPER_KEY_PIN                   GPIO_PIN_13
diff --git a/bsp/gd32303e-eval/drivers/gd32f303e_lcd_eval.c b/bsp/gd32303e-eval/drivers/gd32f303e_lcd_eval.c
index 228feafdf8..3ca126e87e 100644
--- a/bsp/gd32303e-eval/drivers/gd32f303e_lcd_eval.c
+++ b/bsp/gd32303e-eval/drivers/gd32f303e_lcd_eval.c
@@ -15,7 +15,7 @@
 
 /*!
     \brief      lcd peripheral initialize
-    \param[in]  none 
+    \param[in]  none
     \param[out] none
     \retval     none
 */
@@ -37,15 +37,15 @@ void exmc_lcd_init(void)
     gpio_init(GPIOD, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_1| GPIO_PIN_8 | GPIO_PIN_9 |
                                                          GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15);
 
-    /* PE7(EXMC_D4), PE8(EXMC_D5), PE9(EXMC_D6), PE10(EXMC_D7), PE11(EXMC_D8), PE12(EXMC_D9), 
+    /* PE7(EXMC_D4), PE8(EXMC_D5), PE9(EXMC_D6), PE10(EXMC_D7), PE11(EXMC_D8), PE12(EXMC_D9),
        PE13(EXMC_D10), PE14(EXMC_D11), PE15(EXMC_D12) */
-    gpio_init(GPIOE, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | 
-                                                         GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | 
+    gpio_init(GPIOE, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 |
+                                                         GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 |
                                                          GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15);
 
-    /* configure PE2(EXMC_A23) */ 
+    /* configure PE2(EXMC_A23) */
     gpio_init(GPIOE, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_2);
-    
+
     /* configure NOE and NWE */
     gpio_init(GPIOD, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_4 | GPIO_PIN_5);
 
@@ -106,7 +106,7 @@ uint16_t lcd_register_read(uint8_t register_id)
 {
     uint16_t data;
     *(__IO uint16_t *) (BANK0_LCD_C)= register_id;
-    data = *(__IO uint16_t *) (BANK0_LCD_D); 
+    data = *(__IO uint16_t *) (BANK0_LCD_D);
     return  data;
 }
 
@@ -154,13 +154,13 @@ void lcd_gram_write(uint16_t rgb_code)
 uint16_t lcd_gram_read(void)
 {
   uint16_t data;
-    
+
   /* write GRAM register (R22h) */
   *(__IO uint16_t *) (BANK0_LCD_C) = 0x0022;
   /* dummy read (invalid data) */
-  *(__IO uint16_t *) (BANK0_LCD_D); 
+  *(__IO uint16_t *) (BANK0_LCD_D);
 
-  data = *(__IO uint16_t *) (BANK0_LCD_D); 
+  data = *(__IO uint16_t *) (BANK0_LCD_D);
   return data;
 }
 
@@ -219,7 +219,7 @@ void lcd_init(void)
     }else{
         return;
     }
-    
+
     for(i=50000;i>0;i--);
 }
 
@@ -277,16 +277,16 @@ void lcd_point_set(uint16_t x,uint16_t y,uint16_t point)
     \param[in]  x: the row-coordinate
     \param[in]  y: the column-coordinate
     \param[out] none
-    \retval     GRAM value of point 
+    \retval     GRAM value of point
 */
 uint16_t lcd_point_get(uint16_t x,uint16_t y)
 {
     uint16_t data;
-    
+
     if ((x > 240)||(y > 320)){
         return 0;
     }
-    
+
     lcd_cursor_set(x,y);
     data = lcd_gram_read();
 
@@ -410,7 +410,7 @@ void lcd_picture_draw(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t
     y = start_y;
 
     total = (end_x - start_x + 1) * (end_y - start_y + 1);
-    
+
     for(i = 0; i < total; i ++){
         /* set point according to the specified position and color */
         lcd_point_set(x,y,*picturepointer++);
@@ -441,7 +441,7 @@ void lcd_char_display(uint16_t x,uint16_t y,uint8_t c,char_format_struct c_forma
     uint16_t i = 0, j = 0;
     uint8_t temp_char = 0;
     uint16_t temp_char_16 = 0;
-    
+
     if(CHAR_FONT_8_16 == c_format.font){ /* 8x16 ASCII */
         for (i = 0; i < 16; i++) {
             temp_char = ascii_8x16[((c - 0x20) * 16) + i];
diff --git a/bsp/gd32303e-eval/drivers/gd32f303e_lcd_eval.h b/bsp/gd32303e-eval/drivers/gd32f303e_lcd_eval.h
index 800a02c8c5..db76bc17d5 100644
--- a/bsp/gd32303e-eval/drivers/gd32f303e_lcd_eval.h
+++ b/bsp/gd32303e-eval/drivers/gd32f303e_lcd_eval.h
@@ -155,7 +155,7 @@
 
 /* char format struct definitions */
 typedef struct
-{   
+{
     uint16_t font;              /*!< the type of font */
     uint16_t direction;         /*!< the direction of char */
     uint16_t char_color;        /*!< the color of char */
diff --git a/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/GCC/startup_gd32f4xx.S b/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/GCC/startup_gd32f4xx.S
index d3b0023b0a..149472da00 100644
--- a/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/GCC/startup_gd32f4xx.S
+++ b/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/GCC/startup_gd32f4xx.S
@@ -1,21 +1,7 @@
 ;/*
-; * File      : startup_gd32f4xx.c
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
+; * Copyright (c) 2006-2021, RT-Thread Development Team
 ; *
-; *  This program is free software; you can redistribute it and/or modify
-; *  it under the terms of the GNU General Public License as published by
-; *  the Free Software Foundation; either version 2 of the License, or
-; *  (at your option) any later version.
-; *
-; *  This program is distributed in the hope that it will be useful,
-; *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-; *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-; *  GNU General Public License for more details.
-; *
-; *  You should have received a copy of the GNU General Public License along
-; *  with this program; if not, write to the Free Software Foundation, Inc.,
-; *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
@@ -34,7 +20,7 @@
     .type  g_pfnVectors, %object
 
 g_pfnVectors:
-    .word     _estack                      	// Top of Stack
+    .word     _estack                       // Top of Stack
     .word     Reset_Handler                     // Reset Handler
     .word     NMI_Handler                       // NMI Handler
     .word     HardFault_Handler                 // Hard Fault Handler
@@ -195,13 +181,13 @@ MemManage_Handler:
 BusFault_Handler:
     b       .
     .size   BusFault_Handler, . - BusFault_Handler
-    
+
     .weak   UsageFault_Handler
     .type   UsageFault_Handler, %function
 UsageFault_Handler:
     b       .
     .size   UsageFault_Handler, . - UsageFault_Handler
-    
+
     .weak   SVC_Handler
     .type   SVC_Handler, %function
 SVC_Handler:
@@ -219,13 +205,13 @@ DebugMon_Handler:
 PendSV_Handler:
     b       .
     .size   PendSV_Handler, . - PendSV_Handler
-    
+
     .weak   SysTick_Handler
     .type   SysTick_Handler, %function
 SysTick_Handler:
     b       .
     .size   SysTick_Handler, . - SysTick_Handler
-    
+
     /* IQR Handler */
     .section  .text.Default_Handler,"ax",%progbits
     .type  Default_Handler, %function
diff --git a/bsp/gd32450z-eval/applications/main.c b/bsp/gd32450z-eval/applications/main.c
index 9b0ba13a45..5c74d95c06 100644
--- a/bsp/gd32450z-eval/applications/main.c
+++ b/bsp/gd32450z-eval/applications/main.c
@@ -1,21 +1,7 @@
 /*
- * File      : main.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/gd32450z-eval/applications/rtgui_demo.h b/bsp/gd32450z-eval/applications/rtgui_demo.h
index e27f7b5609..d2d073b75d 100644
--- a/bsp/gd32450z-eval/applications/rtgui_demo.h
+++ b/bsp/gd32450z-eval/applications/rtgui_demo.h
@@ -1,11 +1,7 @@
 /*
- * File      : dc.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2009, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/gd32450z-eval/drivers/board.c b/bsp/gd32450z-eval/drivers/board.c
index f7628dae9b..fb17c159eb 100644
--- a/bsp/gd32450z-eval/drivers/board.c
+++ b/bsp/gd32450z-eval/drivers/board.c
@@ -1,11 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/gd32450z-eval/drivers/board.h b/bsp/gd32450z-eval/drivers/board.h
index d6384ae820..ea7dd83acd 100644
--- a/bsp/gd32450z-eval/drivers/board.h
+++ b/bsp/gd32450z-eval/drivers/board.h
@@ -1,11 +1,7 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -22,7 +18,7 @@
 #define EXT_SDRAM_END      (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */
 
 //  Internal SRAM memory size[Kbytes] <8-64>
-//	Default: 64
+//  Default: 64
 #ifdef __ICCARM__
 // Use *.icf ram symbal, to avoid hardcode.
 extern char __ICFEDIT_region_RAM_end__;
diff --git a/bsp/gd32450z-eval/drivers/drv_enet.c b/bsp/gd32450z-eval/drivers/drv_enet.c
index b1bf632f54..f461b50fba 100644
--- a/bsp/gd32450z-eval/drivers/drv_enet.c
+++ b/bsp/gd32450z-eval/drivers/drv_enet.c
@@ -1,11 +1,7 @@
 /*
- * File      : eth_driver.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -35,16 +31,16 @@
 //#define EMAC_TX_DUMP
 
 #ifdef EMAC_DEBUG
-#define EMAC_TRACE	        rt_kprintf
+#define EMAC_TRACE          rt_kprintf
 #else
 #define EMAC_TRACE(...)
 #endif
 
-#define EMAC_RXBUFNB        	4
-#define EMAC_TXBUFNB        	2
+#define EMAC_RXBUFNB            4
+#define EMAC_TXBUFNB            2
 
-#define EMAC_PHY_AUTO		    0
-#define EMAC_PHY_10MBIT		    1
+#define EMAC_PHY_AUTO           0
+#define EMAC_PHY_10MBIT         1
 #define EMAC_PHY_100MBIT        2
 
 #define MAX_ADDR_LEN 6
@@ -55,14 +51,14 @@ struct gd32_emac
 
     rt_uint8_t phy_mode;
     /* interface address info. */
-    rt_uint8_t  dev_addr[MAX_ADDR_LEN];		/* hw address	*/
+    rt_uint8_t  dev_addr[MAX_ADDR_LEN];     /* hw address   */
 
     struct rt_synopsys_eth * ETHERNET_MAC;
     IRQn_Type ETHER_MAC_IRQ;
-    
+
     EMAC_DMADESCTypeDef  *DMATxDescToSet;
     EMAC_DMADESCTypeDef  *DMARxDescToGet;
-    
+
 #pragma pack(4)
     EMAC_DMADESCTypeDef DMARxDscrTab[EMAC_RXBUFNB];
 #pragma pack(4)
@@ -71,7 +67,7 @@ struct gd32_emac
     rt_uint8_t Rx_Buff[EMAC_RXBUFNB][EMAC_MAX_PACKET_SIZE];
 #pragma pack(4)
     rt_uint8_t Tx_Buff[EMAC_TXBUFNB][EMAC_MAX_PACKET_SIZE];
-    
+
     struct rt_semaphore tx_buf_free;
 };
 
@@ -548,14 +544,14 @@ static void enet_gpio_config(void)
     rcu_periph_clock_enable(RCU_GPIOG);
     rcu_periph_clock_enable(RCU_GPIOH);
     rcu_periph_clock_enable(RCU_GPIOI);
-  
+
     gpio_af_set(GPIOA, GPIO_AF_0, GPIO_PIN_8);
     gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_8);
     gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_8);
-  
+
     /* enable SYSCFG clock */
     rcu_periph_clock_enable(RCU_SYSCFG);
-  
+
     /* choose DIV2 to get 50MHz from 200MHz on CKOUT0 pin (PA8) to clock the PHY */
     rcu_ckout0_config(RCU_CKOUT0SRC_PLLP, RCU_CKOUT0_DIV4);
     syscfg_enet_phy_interface_config(SYSCFG_ENET_PHY_RMII);
@@ -563,31 +559,31 @@ static void enet_gpio_config(void)
     /* PA1: ETH_RMII_REF_CLK */
     gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_1);
     gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_1);
-    
+
     /* PA2: ETH_MDIO */
     gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_2);
     gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_2);
-    
+
     /* PA7: ETH_RMII_CRS_DV */
     gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_7);
-    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_7);   
-    
+    gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_7);
+
     gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_1);
     gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_2);
     gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_7);
-    
+
     /* PB11: ETH_RMII_TX_EN */
     gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_11);
     gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_11);
-    
+
     /* PB12: ETH_RMII_TXD0 */
     gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_12);
     gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_12);
-    
+
     /* PB13: ETH_RMII_TXD1 */
     gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_13);
-    gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_13);   
-    
+    gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_13);
+
     gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_11);
     gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_12);
     gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_13);
@@ -599,11 +595,11 @@ static void enet_gpio_config(void)
     /* PC4: ETH_RMII_RXD0 */
     gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_4);
     gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_4);
-    
+
     /* PC5: ETH_RMII_RXD1 */
     gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_5);
-    gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_5); 
-    
+    gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_5);
+
     gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_1);
     gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_4);
     gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_5);
@@ -613,17 +609,17 @@ static void enet_gpio_config(void)
 int rt_hw_gd32_eth_init(void)
 {
     rt_kprintf("rt_gd32_eth_init...\n");
-    
+
     /* enable ethernet clock  */
     rcu_periph_clock_enable(RCU_ENET);
     rcu_periph_clock_enable(RCU_ENETTX);
     rcu_periph_clock_enable(RCU_ENETRX);
-    
+
     nvic_configuration();
-  
+
     /* configure the GPIO ports for ethernet pins */
     enet_gpio_config();
-    
+
     /* set autonegotiation mode */
     gd32_emac_device0.phy_mode = EMAC_PHY_AUTO;
     gd32_emac_device0.ETHERNET_MAC = ETHERNET_MAC0;
@@ -638,16 +634,16 @@ int rt_hw_gd32_eth_init(void)
     gd32_emac_device0.dev_addr[4] = 0x34;
     gd32_emac_device0.dev_addr[5] = 0x56;
 
-    gd32_emac_device0.parent.parent.init		 = gd32_emac_init;
-    gd32_emac_device0.parent.parent.open		 = gd32_emac_open;
-    gd32_emac_device0.parent.parent.close	 = gd32_emac_close;
-    gd32_emac_device0.parent.parent.read		 = gd32_emac_read;
-    gd32_emac_device0.parent.parent.write	 = gd32_emac_write;
-    gd32_emac_device0.parent.parent.control	 = gd32_emac_control;
+    gd32_emac_device0.parent.parent.init         = gd32_emac_init;
+    gd32_emac_device0.parent.parent.open         = gd32_emac_open;
+    gd32_emac_device0.parent.parent.close    = gd32_emac_close;
+    gd32_emac_device0.parent.parent.read         = gd32_emac_read;
+    gd32_emac_device0.parent.parent.write    = gd32_emac_write;
+    gd32_emac_device0.parent.parent.control  = gd32_emac_control;
     gd32_emac_device0.parent.parent.user_data = RT_NULL;
 
-    gd32_emac_device0.parent.eth_rx			 = gd32_emac_rx;
-    gd32_emac_device0.parent.eth_tx			 = gd32_emac_tx;
+    gd32_emac_device0.parent.eth_rx          = gd32_emac_rx;
+    gd32_emac_device0.parent.eth_tx          = gd32_emac_tx;
 
     /* init tx buffer free semaphore */
     rt_sem_init(&gd32_emac_device0.tx_buf_free, "tx_buf0", EMAC_TXBUFNB, RT_IPC_FLAG_FIFO);
diff --git a/bsp/gd32450z-eval/drivers/drv_exmc_sdram.c b/bsp/gd32450z-eval/drivers/drv_exmc_sdram.c
index 41355987b5..3fe8866dfb 100644
--- a/bsp/gd32450z-eval/drivers/drv_exmc_sdram.c
+++ b/bsp/gd32450z-eval/drivers/drv_exmc_sdram.c
@@ -47,7 +47,7 @@ static void delay_1ms(volatile uint32_t count)
 
 /*!
     \brief      sdram peripheral initialize
-    \param[in]  sdram_device: specifie the SDRAM device 
+    \param[in]  sdram_device: specifie the SDRAM device
     \param[out] none
     \retval     none
 */
@@ -71,7 +71,7 @@ void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device)
     rcu_periph_clock_enable(RCU_GPIOH);
 
     /* common GPIO configuration */
-    /* SDNWE(PC0),SDNE0(PC2),SDCKE0(PC3) pin configuration */ 
+    /* SDNWE(PC0),SDNE0(PC2),SDCKE0(PC3) pin configuration */
     gpio_af_set(GPIOC, GPIO_AF_12, GPIO_PIN_0 | GPIO_PIN_2 | GPIO_PIN_3);
     gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_0 | GPIO_PIN_2 | GPIO_PIN_3);
     gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_2 | GPIO_PIN_3);
@@ -107,11 +107,11 @@ void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device)
                                                                      GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15);
 
     /* A10(PG0),A11(PG1),A12(PG2),A14(PG4),A15(PG5),SDCLK(PG8),NCAS(PG15) pin configuration */
-    gpio_af_set(GPIOG, GPIO_AF_12, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 | 
+    gpio_af_set(GPIOG, GPIO_AF_12, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 |
                                    GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15);
-    gpio_mode_set(GPIOG, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 | 
+    gpio_mode_set(GPIOG, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 |
                                                          GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15);
-    gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 | 
+    gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 |
                                                                      GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15);
 
     /* specify which SDRAM to read and write */
@@ -126,7 +126,7 @@ void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device)
     /* LMRD: 2 clock cycles */
     sdram_timing_init_struct.load_mode_register_delay = 2;
     /* XSRD: min = 67ns */
-    sdram_timing_init_struct.exit_selfrefresh_delay = 7; 
+    sdram_timing_init_struct.exit_selfrefresh_delay = 7;
     /* RASD: min=42ns , max=120k (ns) */
     sdram_timing_init_struct.row_address_select_delay = 5;
     /* ARFD: min=60ns */
@@ -144,9 +144,9 @@ void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device)
     sdram_init_struct.row_address_width = EXMC_SDRAM_ROW_ADDRESS_13;
     sdram_init_struct.data_width = EXMC_SDRAM_DATABUS_WIDTH_16B;
     sdram_init_struct.internal_bank_number = EXMC_SDRAM_4_INTER_BANK;
-    sdram_init_struct.cas_latency = EXMC_CAS_LATENCY_3_SDCLK; 
+    sdram_init_struct.cas_latency = EXMC_CAS_LATENCY_3_SDCLK;
     sdram_init_struct.write_protection = DISABLE;
-    sdram_init_struct.sdclock_config = EXMC_SDCLK_PERIODS_2_HCLK;  
+    sdram_init_struct.sdclock_config = EXMC_SDCLK_PERIODS_2_HCLK;
     sdram_init_struct.brust_read_switch = ENABLE;
     sdram_init_struct.pipeline_read_delay = EXMC_PIPELINE_DELAY_1_HCLK;
     sdram_init_struct.timing  = &sdram_timing_init_struct;
@@ -158,7 +158,7 @@ void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device)
     sdram_command_init_struct.bank_select = bank_select;
     sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_1_SDCLK;
     sdram_command_init_struct.mode_register_content = 0;
-    /* wait until the SDRAM controller is ready */ 
+    /* wait until the SDRAM controller is ready */
     while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)){
         timeout--;
     }
@@ -174,7 +174,7 @@ void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device)
     sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_1_SDCLK;
     sdram_command_init_struct.mode_register_content = 0;
     /* wait until the SDRAM controller is ready */
-    timeout = SDRAM_TIMEOUT; 
+    timeout = SDRAM_TIMEOUT;
     while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)){
         timeout--;
     }
@@ -186,8 +186,8 @@ void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device)
     sdram_command_init_struct.bank_select = bank_select;
     sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_8_SDCLK;
     sdram_command_init_struct.mode_register_content = 0;
-    /* wait until the SDRAM controller is ready */ 
-    timeout = SDRAM_TIMEOUT; 
+    /* wait until the SDRAM controller is ready */
+    timeout = SDRAM_TIMEOUT;
     while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)){
         timeout--;
     }
@@ -207,8 +207,8 @@ void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device)
     sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_1_SDCLK;
     sdram_command_init_struct.mode_register_content = command_content;
 
-    /* wait until the SDRAM controller is ready */ 
-    timeout = SDRAM_TIMEOUT; 
+    /* wait until the SDRAM controller is ready */
+    timeout = SDRAM_TIMEOUT;
     while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)){
         timeout--;
     }
@@ -221,8 +221,8 @@ void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device)
     /* (7.81 us * SDCLK_Freq) - 20 */
     exmc_sdram_refresh_count_set(761);
 
-    /* wait until the SDRAM controller is ready */ 
-    timeout = SDRAM_TIMEOUT; 
+    /* wait until the SDRAM controller is ready */
+    timeout = SDRAM_TIMEOUT;
     while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)){
         timeout--;
     }
@@ -258,20 +258,20 @@ void fill_buffer(uint8_t *pbuffer, uint16_t buffer_lengh, uint16_t offset)
 void sdram_writebuffer_8(uint32_t sdram_device,uint8_t* pbuffer, uint32_t writeaddr, uint32_t numbytetowrite)
 {
     uint32_t temp_addr;
-    
+
     /* Select the base address according to EXMC_Bank */
     if(sdram_device == EXMC_SDRAM_DEVICE0){
         temp_addr = SDRAM_DEVICE0_ADDR;
     }else{
         temp_addr = SDRAM_DEVICE1_ADDR;
     }
-    
+
      /* While there is data to write */
     for(; numbytetowrite != 0; numbytetowrite--) {
         /* Transfer data to the memory */
         *(uint8_t *) (temp_addr + writeaddr) = *pbuffer++;
 
-        /* Increment the address*/  
+        /* Increment the address*/
         writeaddr += 1;
     }
 }
@@ -288,19 +288,19 @@ void sdram_writebuffer_8(uint32_t sdram_device,uint8_t* pbuffer, uint32_t writea
 void sdram_readbuffer_8(uint32_t sdram_device,uint8_t* pbuffer, uint32_t readaddr, uint32_t numbytetoread)
 {
     uint32_t temp_addr;
-    
+
     /* select the base address according to EXMC_Bank */
     if(sdram_device == EXMC_SDRAM_DEVICE0){
         temp_addr = SDRAM_DEVICE0_ADDR;
     }else{
         temp_addr = SDRAM_DEVICE1_ADDR;
     }
-    
+
     /* while there is data to read */
     for(; numbytetoread != 0; numbytetoread--){
         /* read a byte from the memory */
         *pbuffer++ = *(uint8_t*) (temp_addr + readaddr);
-    
+
         /* increment the address */
         readaddr += 1;
     }
diff --git a/bsp/gd32450z-eval/drivers/drv_lcd.c b/bsp/gd32450z-eval/drivers/drv_lcd.c
index 50d5c685c5..3cbae2ac84 100644
--- a/bsp/gd32450z-eval/drivers/drv_lcd.c
+++ b/bsp/gd32450z-eval/drivers/drv_lcd.c
@@ -1,11 +1,7 @@
 /*
- * File      : usart.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -41,7 +37,7 @@ static struct rt_device_graphic_info _lcd_info;
 static struct rt_device lcd;
 
 /*!
-    \brief      configure TLI GPIO  
+    \brief      configure TLI GPIO
     \param[in]  none
     \param[out] none
     \retval     none
@@ -57,34 +53,34 @@ static void tli_gpio_config(void)
     rcu_periph_clock_enable(RCU_GPIOG);
 
     /* configure HSYNC(PC6), VSYNC(PA4), PCLK(PG7), DE(PF10) */
-    /* configure LCD_R7(PG6), LCD_R6(PA8), LCD_R5(PA12), LCD_R4(PA11), LCD_R3(PB0), 
+    /* configure LCD_R7(PG6), LCD_R6(PA8), LCD_R5(PA12), LCD_R4(PA11), LCD_R3(PB0),
                  LCD_G7(PD3), LCD_G6(PC7), LCD_G5(PB11), LCD_G4(PB10), LCD_G3(PG10), LCD_G2(PA6),
                  LCD_B7(PB9), LCD_B6(PB8), LCD_B5(PA3), LCD_B4(PG12), LCD_B3(PG11) */
-    gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_3);  
+    gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_3);
     gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_4);
-    gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_6);  
-    gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_12); 
-    gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_11);  
-    gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_8); 
-    
-    gpio_af_set(GPIOB,GPIO_AF_9,GPIO_PIN_0);  
-    gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_10);     
-    //gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_11);
-    gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_8);     
-    gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_9);
-    
-    gpio_af_set(GPIOC,GPIO_AF_14,GPIO_PIN_6);     
-    gpio_af_set(GPIOC,GPIO_AF_14,GPIO_PIN_7);
-    
-    gpio_af_set(GPIOD,GPIO_AF_14,GPIO_PIN_3);     
+    gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_6);
+    gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_12);
+    gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_11);
+    gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_8);
 
-    gpio_af_set(GPIOF,GPIO_AF_14,GPIO_PIN_10);     
-    
-    gpio_af_set(GPIOG,GPIO_AF_14,GPIO_PIN_6);     
+    gpio_af_set(GPIOB,GPIO_AF_9,GPIO_PIN_0);
+    gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_10);
+    //gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_11);
+    gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_8);
+    gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_9);
+
+    gpio_af_set(GPIOC,GPIO_AF_14,GPIO_PIN_6);
+    gpio_af_set(GPIOC,GPIO_AF_14,GPIO_PIN_7);
+
+    gpio_af_set(GPIOD,GPIO_AF_14,GPIO_PIN_3);
+
+    gpio_af_set(GPIOF,GPIO_AF_14,GPIO_PIN_10);
+
+    gpio_af_set(GPIOG,GPIO_AF_14,GPIO_PIN_6);
     gpio_af_set(GPIOG,GPIO_AF_14,GPIO_PIN_7);
     gpio_af_set(GPIOG,GPIO_AF_9,GPIO_PIN_10);
-    gpio_af_set(GPIOG,GPIO_AF_14,GPIO_PIN_11);     
-    gpio_af_set(GPIOG,GPIO_AF_9,GPIO_PIN_12);    
+    gpio_af_set(GPIOG,GPIO_AF_14,GPIO_PIN_11);
+    gpio_af_set(GPIOG,GPIO_AF_9,GPIO_PIN_12);
 
     gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_6
     |GPIO_PIN_8|GPIO_PIN_11|GPIO_PIN_12);
@@ -123,15 +119,15 @@ static void lcd_config(void)
     lcd_ctrl_line_config();
     lcd_disable();
     lcd_enable();
-    
+
     /* configure the GPIO of TLI */
     tli_gpio_config();
     /* configure the LCD_SPI */
-    lcd_spi_config(); 
+    lcd_spi_config();
 
     /* power on the LCD */
     //lcd_power_on();
-	lcd_power_on3();  //New Version 3.5" TFT RGB Hardware needs use this initilize funtion  ---By xufei 2016.10.21
+    lcd_power_on3();  //New Version 3.5" TFT RGB Hardware needs use this initilize funtion  ---By xufei 2016.10.21
 }
 
 /*!
@@ -144,7 +140,7 @@ static void tli_config(void)
 {
     tli_parameter_struct               tli_init_struct;
     tli_layer_parameter_struct         tli_layer_init_struct;
- 
+
     rcu_periph_clock_enable(RCU_TLI);
 
     /* configure the PLLSAI clock to generate lcd clock */
@@ -156,52 +152,52 @@ static void tli_config(void)
     if(ERROR == rcu_osci_stab_wait(RCU_PLLSAI_CK)){
         while(1);
     }
-    
+
     /* TLI initialization */
     tli_init_struct.signalpolarity_hs = TLI_HSYN_ACTLIVE_LOW;
     tli_init_struct.signalpolarity_vs = TLI_VSYN_ACTLIVE_LOW;
     tli_init_struct.signalpolarity_de = TLI_DE_ACTLIVE_LOW;
     tli_init_struct.signalpolarity_pixelck = TLI_PIXEL_CLOCK_TLI;
-    
+
     /* LCD display timing configuration */
     tli_init_struct.synpsz_hpsz   = LCD_480_320_HSYNC;
     tli_init_struct.synpsz_vpsz   = LCD_480_320_VSYNC;
-    tli_init_struct.backpsz_hbpsz = LCD_480_320_HSYNC + LCD_480_320_HBP; 
-    tli_init_struct.backpsz_vbpsz = LCD_480_320_VSYNC + LCD_480_320_VBP;  
+    tli_init_struct.backpsz_hbpsz = LCD_480_320_HSYNC + LCD_480_320_HBP;
+    tli_init_struct.backpsz_vbpsz = LCD_480_320_VSYNC + LCD_480_320_VBP;
     tli_init_struct.activesz_hasz = RT_HW_LCD_WIDTH + LCD_480_320_HSYNC + LCD_480_320_HBP;
     tli_init_struct.activesz_vasz = RT_HW_LCD_HEIGHT + LCD_480_320_VSYNC + LCD_480_320_VBP;
-    tli_init_struct.totalsz_htsz  = RT_HW_LCD_WIDTH + LCD_480_320_HSYNC + LCD_480_320_HBP + LCD_480_320_HFP; 
+    tli_init_struct.totalsz_htsz  = RT_HW_LCD_WIDTH + LCD_480_320_HSYNC + LCD_480_320_HBP + LCD_480_320_HFP;
     tli_init_struct.totalsz_vtsz  = RT_HW_LCD_HEIGHT + LCD_480_320_VSYNC + LCD_480_320_VBP + LCD_480_320_VFP;
-    
+
     /* LCD background color configure*/
     tli_init_struct.backcolor_red   = 0x00;
     tli_init_struct.backcolor_green = 0x00;
-    tli_init_struct.backcolor_blue  = 0x00; 
+    tli_init_struct.backcolor_blue  = 0x00;
     tli_init(&tli_init_struct);
-    
+
     lcd_framebuffer = rt_malloc(sizeof(rt_uint16_t) * RT_HW_LCD_HEIGHT * RT_HW_LCD_WIDTH);
     RT_ASSERT(lcd_framebuffer != NULL);
     rt_memset(lcd_framebuffer, 0, sizeof(rt_uint16_t) * RT_HW_LCD_WIDTH * RT_HW_LCD_HEIGHT);
 
     /* TLI layer0 configuration */
     tli_layer_init_struct.layer_window_leftpos          = tli_init_struct.backpsz_hbpsz + 1;
-    tli_layer_init_struct.layer_window_rightpos         = tli_init_struct.backpsz_hbpsz + RT_HW_LCD_WIDTH; 
+    tli_layer_init_struct.layer_window_rightpos         = tli_init_struct.backpsz_hbpsz + RT_HW_LCD_WIDTH;
     tli_layer_init_struct.layer_window_toppos           = tli_init_struct.backpsz_vbpsz + 1;
     tli_layer_init_struct.layer_window_bottompos        = tli_init_struct.backpsz_vbpsz + RT_HW_LCD_HEIGHT;
-    
+
     tli_layer_init_struct.layer_ppf                     = LAYER_PPF_RGB565;
     tli_layer_init_struct.layer_sa                      = 0xFF;
-    tli_layer_init_struct.layer_default_blue            = 0x00;        
-    tli_layer_init_struct.layer_default_green           = 0x00;       
-    tli_layer_init_struct.layer_default_red             = 0x00;         
+    tli_layer_init_struct.layer_default_blue            = 0x00;
+    tli_layer_init_struct.layer_default_green           = 0x00;
+    tli_layer_init_struct.layer_default_red             = 0x00;
     tli_layer_init_struct.layer_default_alpha           = 0x00;
-    tli_layer_init_struct.layer_acf1                    = LAYER_ACF1_PASA;    
+    tli_layer_init_struct.layer_acf1                    = LAYER_ACF1_PASA;
     tli_layer_init_struct.layer_acf2                    = LAYER_ACF2_PASA;
-    tli_layer_init_struct.layer_frame_bufaddr           = (uint32_t)lcd_framebuffer;    
-    tli_layer_init_struct.layer_frame_line_length       = ((RT_HW_LCD_WIDTH * 2) + 3); 
+    tli_layer_init_struct.layer_frame_bufaddr           = (uint32_t)lcd_framebuffer;
+    tli_layer_init_struct.layer_frame_line_length       = ((RT_HW_LCD_WIDTH * 2) + 3);
     tli_layer_init_struct.layer_frame_buf_stride_offset = (RT_HW_LCD_WIDTH * 2);
-    tli_layer_init_struct.layer_frame_total_line_number = RT_HW_LCD_HEIGHT; 
-    
+    tli_layer_init_struct.layer_frame_total_line_number = RT_HW_LCD_HEIGHT;
+
     tli_layer_init(LAYER0, &tli_layer_init_struct);
 }
 
@@ -210,21 +206,21 @@ static rt_err_t rt_lcd_control(rt_device_t dev, int cmd, void *args)
     switch (cmd)
     {
     case RTGRAPHIC_CTRL_RECT_UPDATE:
-    {        
+    {
         memcpy((void *)lcd_framebuffer, _rt_framebuffer, sizeof(rt_uint16_t)*RT_HW_LCD_HEIGHT * RT_HW_LCD_WIDTH);
     }
     break;
-    
+
     case RTGRAPHIC_CTRL_POWERON:
         break;
-    
+
     case RTGRAPHIC_CTRL_POWEROFF:
         break;
-    
+
     case RTGRAPHIC_CTRL_GET_INFO:
         memcpy(args, &_lcd_info, sizeof(_lcd_info));
         break;
-    
+
     case RTGRAPHIC_CTRL_SET_MODE:
         break;
     }
@@ -235,21 +231,21 @@ static rt_err_t rt_lcd_control(rt_device_t dev, int cmd, void *args)
 int gd32_hw_lcd_init(void)
 {
     _rt_framebuffer = rt_malloc_align(sizeof(rt_uint16_t) * RT_HW_LCD_WIDTH * RT_HW_LCD_HEIGHT, 32);
-    if (_rt_framebuffer == RT_NULL) 
+    if (_rt_framebuffer == RT_NULL)
         return -1; /* no memory yet */
-    
+
     lcd_config();
     tli_config();
-    tli_layer_enable(LAYER0);  
+    tli_layer_enable(LAYER0);
     tli_reload_config(TLI_FRAME_BLANK_RELOAD_EN);
     tli_enable();
-    
+
     _lcd_info.bits_per_pixel = LCD_BITS_PER_PIXEL;
     _lcd_info.pixel_format   = RTGRAPHIC_PIXEL_FORMAT_RGB565;
     _lcd_info.framebuffer    = (void *)_rt_framebuffer;
     _lcd_info.width          = RT_HW_LCD_WIDTH;
     _lcd_info.height         = RT_HW_LCD_HEIGHT;
-    
+
     lcd.type    = RT_Device_Class_Graphic;
     lcd.init    = NULL;
     lcd.open    = NULL;
@@ -258,10 +254,10 @@ int gd32_hw_lcd_init(void)
     lcd.write   = NULL;
     lcd.control = rt_lcd_control;
     lcd.user_data = (void *)&_lcd_info;
-    
+
     /* register lcd device to RT-Thread */
     rt_device_register(&lcd, "lcd", RT_DEVICE_FLAG_RDWR);
-    
+
     return 0;
 }
 INIT_DEVICE_EXPORT(gd32_hw_lcd_init);
diff --git a/bsp/gd32450z-eval/drivers/drv_spi.c b/bsp/gd32450z-eval/drivers/drv_spi.c
index f4e56e1a8c..acd4f7198f 100644
--- a/bsp/gd32450z-eval/drivers/drv_spi.c
+++ b/bsp/gd32450z-eval/drivers/drv_spi.c
@@ -1,17 +1,13 @@
 /*
- * File      : drv_spi.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017 RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2017-06-05     tanek        first implementation.
  */
- 
+
 #include "drv_spi.h"
 
 #include 
@@ -32,7 +28,7 @@
 #ifdef DEBUG
 #define DEBUG_PRINTF(...)   rt_kprintf(__VA_ARGS__)
 #else
-#define DEBUG_PRINTF(...)   
+#define DEBUG_PRINTF(...)
 #endif
 
 /* private rt-thread spi ops function */
@@ -48,16 +44,16 @@ static struct rt_spi_ops gd32_spi_ops =
 static rt_err_t configure(struct rt_spi_device* device,
                           struct rt_spi_configuration* configuration)
 {
-    struct rt_spi_bus * spi_bus = (struct rt_spi_bus *)device->bus;	
+    struct rt_spi_bus * spi_bus = (struct rt_spi_bus *)device->bus;
     struct gd32f4_spi *f4_spi = (struct gd32f4_spi *)spi_bus->parent.user_data;
-    
+
     spi_parameter_struct spi_init_struct;
 
     uint32_t spi_periph = f4_spi->spi_periph;
 
 
-	RT_ASSERT(device != RT_NULL);
-	RT_ASSERT(configuration != RT_NULL);
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(configuration != RT_NULL);
 
     /* data_width */
     if(configuration->data_width <= 8)
@@ -129,7 +125,7 @@ static rt_err_t configure(struct rt_spi_device* device,
             spi_init_struct.prescale = SPI_PSC_256;
         }
     } /* baudrate */
-    
+
     switch(configuration->mode & RT_SPI_MODE_3)
     {
     case RT_SPI_MODE_0:
@@ -137,15 +133,15 @@ static rt_err_t configure(struct rt_spi_device* device,
         break;
     case RT_SPI_MODE_1:
         spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_2EDGE;
-        break;        
+        break;
     case RT_SPI_MODE_2:
         spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_1EDGE;
-        break;    
+        break;
     case RT_SPI_MODE_3:
         spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE;
         break;
     }
-    
+
     /* MSB or LSB */
     if(configuration->mode & RT_SPI_MSB)
     {
@@ -155,18 +151,18 @@ static rt_err_t configure(struct rt_spi_device* device,
     {
         spi_init_struct.endian = SPI_ENDIAN_LSB;
     }
-    
+
     spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX;
     spi_init_struct.device_mode = SPI_MASTER;
     spi_init_struct.nss = SPI_NSS_SOFT;
-    
+
     spi_crc_off(spi_periph);
 
     /* init SPI */
     spi_init(spi_periph, &spi_init_struct);
     /* Enable SPI_MASTER */
-	spi_enable(spi_periph);
-    
+    spi_enable(spi_periph);
+
     return RT_EOK;
 };
 
@@ -178,9 +174,9 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
     struct gd32_spi_cs * gd32_spi_cs = device->parent.user_data;
     uint32_t spi_periph = f4_spi->spi_periph;
 
-	RT_ASSERT(device != NULL);
-	RT_ASSERT(message != NULL);
-	
+    RT_ASSERT(device != NULL);
+    RT_ASSERT(message != NULL);
+
     /* take CS */
     if(message->cs_take)
     {
@@ -194,7 +190,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
             const rt_uint8_t * send_ptr = message->send_buf;
             rt_uint8_t * recv_ptr = message->recv_buf;
             rt_uint32_t size = message->length;
-            
+
             DEBUG_PRINTF("spi poll transfer start: %d\n", size);
 
             while(size--)
@@ -205,12 +201,12 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
                 {
                     data = *send_ptr++;
                 }
-                
+
                 // Todo: replace register read/write by gd32f4 lib
                 //Wait until the transmit buffer is empty
                 while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE));
                 // Send the byte
-				spi_i2s_data_transmit(spi_periph, data);
+                spi_i2s_data_transmit(spi_periph, data);
 
                 //Wait until a data is received
                 while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE));
@@ -242,7 +238,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
                 //Wait until the transmit buffer is empty
                 while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE));
                 // Send the byte
-				spi_i2s_data_transmit(spi_periph, data);
+                spi_i2s_data_transmit(spi_periph, data);
 
                 //Wait until a data is received
                 while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE));
@@ -260,7 +256,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
     /* release CS */
     if(message->cs_release)
     {
-		gpio_bit_set(gd32_spi_cs->GPIOx, gd32_spi_cs->GPIO_Pin);
+        gpio_bit_set(gd32_spi_cs->GPIOx, gd32_spi_cs->GPIO_Pin);
         DEBUG_PRINTF("spi release cs\n");
     }
 
@@ -274,7 +270,7 @@ static const struct gd32f4_spi spis[] = {
 #ifdef RT_USING_SPI0
     {SPI0, RCU_SPI0, &spi_bus[0]},
 #endif
-    
+
 #ifdef RT_USING_SPI1
     {SPI1, RCU_SPI1, &spi_bus[1]},
 #endif
@@ -286,11 +282,11 @@ static const struct gd32f4_spi spis[] = {
 #ifdef RT_USING_SPI3
     {SPI3, RCU_SPI3, &spi_bus[3]},
 #endif
-    
+
 #ifdef RT_USING_SPI4
     {SPI4, RCU_SPI4, &spi_bus[4]},
 #endif
-    
+
 #ifdef RT_USING_SPI5
     {SPI5, RCU_SPI5, &spi_bus[5]},
 #endif
@@ -310,9 +306,9 @@ rt_err_t gd32_spi_bus_register(uint32_t spi_periph,
                             const char * spi_bus_name)
 {
     int i;
-    
+
     RT_ASSERT(spi_bus_name != RT_NULL);
-    
+
     for (i = 0; i < ARR_LEN(spis); i++)
     {
         if (spi_periph == spis[i].spi_periph)
@@ -323,7 +319,7 @@ rt_err_t gd32_spi_bus_register(uint32_t spi_periph,
             return RT_EOK;
         }
     }
-    
+
     return RT_ERROR;
 }
 #endif
diff --git a/bsp/gd32450z-eval/drivers/drv_spi.h b/bsp/gd32450z-eval/drivers/drv_spi.h
index c97cbba880..51bae441ca 100644
--- a/bsp/gd32450z-eval/drivers/drv_spi.h
+++ b/bsp/gd32450z-eval/drivers/drv_spi.h
@@ -1,11 +1,7 @@
 /*
- * File      : gd32f20x_40x_spi.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -36,7 +32,7 @@ struct gd32_spi_cs
 
 /* public function */
 rt_err_t gd32_spi_bus_register(uint32_t spi_periph,
-								//struct gd32_spi_bus * gd32_spi,
-								const char * spi_bus_name);
+                                //struct gd32_spi_bus * gd32_spi,
+                                const char * spi_bus_name);
 
 #endif // gd32F20X_40X_SPI_H_INCLUDED
diff --git a/bsp/gd32450z-eval/drivers/drv_spi_flash.c b/bsp/gd32450z-eval/drivers/drv_spi_flash.c
index 9b60753472..7f95d59314 100644
--- a/bsp/gd32450z-eval/drivers/drv_spi_flash.c
+++ b/bsp/gd32450z-eval/drivers/drv_spi_flash.c
@@ -1,11 +1,7 @@
 /*
- * File      : gd32f20x_40x_spi.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -32,8 +28,8 @@ static int rt_hw_spi5_init(void)
 {
     /* register spi bus */
     {
-		rt_err_t result;
-        
+        rt_err_t result;
+
         rcu_periph_clock_enable(RCU_GPIOG);
         rcu_periph_clock_enable(RCU_SPI5);
 
@@ -42,36 +38,36 @@ static int rt_hw_spi5_init(void)
         gpio_mode_set(GPIOG, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_10|GPIO_PIN_11| GPIO_PIN_12|GPIO_PIN_13| GPIO_PIN_14);
         gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ, GPIO_PIN_10|GPIO_PIN_11| GPIO_PIN_12|GPIO_PIN_13| GPIO_PIN_14);
 
-		result = gd32_spi_bus_register(SPI5, SPI_BUS_NAME);
+        result = gd32_spi_bus_register(SPI5, SPI_BUS_NAME);
         if (result != RT_EOK)
-		{
-			return result;
-		}
+        {
+            return result;
+        }
     }
 
     /* attach cs */
     {
         static struct rt_spi_device spi_device;
         static struct gd32_spi_cs  spi_cs;
-		rt_err_t result;
-        
+        rt_err_t result;
+
         spi_cs.GPIOx = GPIOG;
         spi_cs.GPIO_Pin = GPIO_PIN_9;
-        
+
         /* SPI5_CS(PG9) GPIO pin configuration */
         gpio_mode_set(GPIOG, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO_PIN_9);
         gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_9);
-        
+
         gpio_bit_set(GPIOG,GPIO_PIN_9);
 
         result = rt_spi_bus_attach_device(&spi_device, SPI_FLASH_DEVICE_NAME, SPI_BUS_NAME, (void*)&spi_cs);
-		if (result != RT_EOK)
-		{
-			return result;
-		}
+        if (result != RT_EOK)
+        {
+            return result;
+        }
     }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 INIT_DEVICE_EXPORT(rt_hw_spi5_init);
 
@@ -83,7 +79,7 @@ static int rt_hw_spi_flash_with_sfud_init(void)
         return RT_ERROR;
     };
 
-	return RT_EOK;
+    return RT_EOK;
 }
 INIT_COMPONENT_EXPORT(rt_hw_spi_flash_with_sfud_init)
 #endif
diff --git a/bsp/gd32450z-eval/drivers/drv_usart.c b/bsp/gd32450z-eval/drivers/drv_usart.c
index 2b0b9c84b0..fa691a42b9 100644
--- a/bsp/gd32450z-eval/drivers/drv_usart.c
+++ b/bsp/gd32450z-eval/drivers/drv_usart.c
@@ -1,11 +1,7 @@
 /*
- * File      : usart.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -37,7 +33,7 @@
 struct gd32_uart
 {
     uint32_t uart_periph;           //Todo: 3bits
-    IRQn_Type irqn;                 //Todo: 7bits    
+    IRQn_Type irqn;                 //Todo: 7bits
     rcu_periph_enum per_clk;        //Todo: 5bits
     rcu_periph_enum tx_gpio_clk;    //Todo: 5bits
     rcu_periph_enum rx_gpio_clk;    //Todo: 5bits
@@ -48,7 +44,7 @@ struct gd32_uart
     uint16_t rx_af;                 //Todo: 4bits
     uint16_t rx_pin;                //Todo: 4bits
 
-    struct rt_serial_device * serial;    
+    struct rt_serial_device * serial;
     char *device_name;
 };
 
@@ -193,7 +189,7 @@ static const struct gd32_uart uarts[] = {
         "uart0",
     },
     #endif
-    
+
     #ifdef BSP_USING_UART1
     {
         USART1,                                 // uart peripheral index
@@ -205,7 +201,7 @@ static const struct gd32_uart uarts[] = {
         "uart1",
     },
     #endif
-    
+
     #ifdef BSP_USING_UART2
     {
         USART2,                                 // uart peripheral index
@@ -217,7 +213,7 @@ static const struct gd32_uart uarts[] = {
         "uart2",
     },
     #endif
-    
+
     #ifdef BSP_USING_UART3
     {
         UART3,                                 // uart peripheral index
@@ -229,7 +225,7 @@ static const struct gd32_uart uarts[] = {
         "uart3",
     },
     #endif
-    
+
     #ifdef BSP_USING_UART4
     {
         UART4,                                 // uart peripheral index
@@ -253,7 +249,7 @@ static const struct gd32_uart uarts[] = {
         "uart5",
     },
     #endif
-    
+
     #ifdef BSP_USING_UART6
     {
         UART6,                                 // uart peripheral index
@@ -309,7 +305,7 @@ void gd32_uart_gpio_init(struct gd32_uart *uart)
     /* configure USART Rx as alternate function push-pull */
     gpio_mode_set(uart->rx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, uart->rx_pin);
     gpio_output_options_set(uart->rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, uart->rx_pin);
-    
+
     NVIC_SetPriority(uart->irqn, 0);
     NVIC_EnableIRQ(uart->irqn);
 }
@@ -322,9 +318,9 @@ static rt_err_t gd32_configure(struct rt_serial_device *serial, struct serial_co
     RT_ASSERT(cfg != RT_NULL);
 
     uart = (struct gd32_uart *)serial->parent.user_data;
-    
+
     gd32_uart_gpio_init(uart);
-    
+
     usart_baudrate_set(uart->uart_periph, cfg->baud_rate);
 
     switch (cfg->data_bits)
@@ -404,7 +400,7 @@ static int gd32_putc(struct rt_serial_device *serial, char ch)
 
     usart_data_transmit(uart->uart_periph, ch);
     while((usart_flag_get(uart->uart_periph, USART_FLAG_TC) == RESET));
-    
+
     return 1;
 }
 
@@ -456,7 +452,7 @@ int gd32_hw_usart_init(void)
     struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
     int i;
 
-    
+
     for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++)
     {
         uarts[i].serial->ops    = &gd32_uart_ops;
diff --git a/bsp/gd32450z-eval/drivers/drv_usart.h b/bsp/gd32450z-eval/drivers/drv_usart.h
index 79c7ed6d90..547384efec 100644
--- a/bsp/gd32450z-eval/drivers/drv_usart.h
+++ b/bsp/gd32450z-eval/drivers/drv_usart.h
@@ -1,11 +1,7 @@
 /*
- * File      : usart.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/gd32450z-eval/drivers/gd32f450z_eval.h b/bsp/gd32450z-eval/drivers/gd32f450z_eval.h
index 73ea9baaa4..6eb91aee01 100644
--- a/bsp/gd32450z-eval/drivers/gd32f450z_eval.h
+++ b/bsp/gd32450z-eval/drivers/gd32f450z_eval.h
@@ -17,23 +17,23 @@
 #endif
 
 #include "gd32f4xx.h"
-     
+
 /* exported types */
-typedef enum 
+typedef enum
 {
     LED1 = 0,
     LED2 = 1,
     LED3 = 2
 } led_typedef_enum;
 
-typedef enum 
+typedef enum
 {
     KEY_WAKEUP = 0,
     KEY_TAMPER = 1,
     KEY_USER = 2
 } key_typedef_enum;
 
-typedef enum 
+typedef enum
 {
     KEY_MODE_GPIO = 0,
     KEY_MODE_EXTI = 1
@@ -45,11 +45,11 @@ typedef enum
 #define LED1_PIN                         GPIO_PIN_4
 #define LED1_GPIO_PORT                   GPIOD
 #define LED1_GPIO_CLK                    RCU_GPIOD
-  
+
 #define LED2_PIN                         GPIO_PIN_5
 #define LED2_GPIO_PORT                   GPIOD
 #define LED2_GPIO_CLK                    RCU_GPIOD
-  
+
 #define LED3_PIN                         GPIO_PIN_3
 #define LED3_GPIO_PORT                   GPIOG
 #define LED3_GPIO_CLK                    RCU_GPIOG
@@ -83,7 +83,7 @@ typedef enum
 #define WAKEUP_KEY_EXTI_LINE             EXTI_0
 #define WAKEUP_KEY_EXTI_PORT_SOURCE      EXTI_SOURCE_GPIOA
 #define WAKEUP_KEY_EXTI_PIN_SOURCE       EXTI_SOURCE_PIN0
-#define WAKEUP_KEY_EXTI_IRQn             EXTI0_IRQn  
+#define WAKEUP_KEY_EXTI_IRQn             EXTI0_IRQn
 
 /* user push-button */
 #define USER_KEY_PIN                     GPIO_PIN_14
diff --git a/bsp/gd32450z-eval/drivers/gd32f450z_lcd_eval.c b/bsp/gd32450z-eval/drivers/gd32f450z_lcd_eval.c
index 8a309a1a75..b71005b6dd 100644
--- a/bsp/gd32450z-eval/drivers/gd32f450z_lcd_eval.c
+++ b/bsp/gd32450z-eval/drivers/gd32f450z_lcd_eval.c
@@ -108,8 +108,8 @@ void lcd_spi_config(void)
     gpio_mode_set(GPIOG, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_13|GPIO_PIN_14);
     gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_13|GPIO_PIN_14);
     spi_i2s_deinit(SPI5);
-    
-    if(0 == (SPI_CTL0(LCD_SPI) & SPI_CTL0_SPIEN)){    
+
+    if(0 == (SPI_CTL0(LCD_SPI) & SPI_CTL0_SPIEN)){
         spi_init_struct.trans_mode           = SPI_TRANSMODE_FULLDUPLEX;
         spi_init_struct.device_mode          = SPI_MASTER;
         spi_init_struct.frame_size           = SPI_FRAMESIZE_8BIT;
@@ -155,7 +155,7 @@ void lcd_data_write(uint8_t value)
     /* set LCD_RS to send data */
     lcd_ctrl_line_set(LCD_RS_GPIO_PORT, LCD_RS_PIN);
 
-    /* reset LCD control line and send data */  
+    /* reset LCD control line and send data */
     lcd_disable();
     while(RESET == spi_i2s_flag_get(LCD_SPI, SPI_FLAG_TBE)) ;
 
@@ -228,80 +228,80 @@ void lcd_power_on(void)
 }
 /**
   * @brief  New Version 3.5" TFT RGB Hardware needs add this initilize funtion  ---By xufei 2016.10.21
-						Modified by GAO HAIYANG, test pass, 17, Nov, 2016
+                        Modified by GAO HAIYANG, test pass, 17, Nov, 2016
   * @param  None
   * @retval None
   */
 void lcd_power_on3(void)
 {
-		lcd_command_write(0xC0);//power control1 command/w/
-		lcd_data_write(0x0A); // P-Gamma level//4.1875v
-		lcd_data_write(0x0A); // N-Gamma level
-		lcd_command_write(0xC1); // BT & VC Setting//power contrl2 command/w/
-		lcd_data_write(0x41);
-		lcd_data_write(0x07); // VCI1 = 2.5V
-		lcd_command_write(0xC2); // DC1.DC0 Setting//power control3 for normal mode
-		lcd_data_write(0x33);
-		lcd_command_write(0xC5);//VCOM control
-		lcd_data_write(0x00);  //NV memory is not programmed
-		lcd_data_write(0x42); // VCM Setting
-		lcd_data_write(0x80); // VCM Register Enable
-		lcd_command_write(0xB0);      //interface mode control //Polarity Setting
-		lcd_data_write(0x02);
-		lcd_command_write(0xB1);//frame rate control for normal mode
-		lcd_data_write(0xB0); // Frame Rate Setting//70 frame per second//no division for internal clocks
-		lcd_data_write(0x11);//17 clocks per line period for idle mode at cpu interface
-		lcd_command_write(0xB4);//dispaly inversion control
-		lcd_data_write(0x00); // disable Z-inversion , column inversion
-		lcd_command_write(0xB6); //display function control// RM.DM Setting
-		lcd_data_write(0x70);////0xF0
-		lcd_data_write(0x02);//direction of gate scan: G1->G480 one by one, source scan: S1->S960, scan cycle if interval scan in non-display area
-		lcd_data_write(0x3B); // number of lines to drive LCD: 8*(0x3C) = 480
-		lcd_command_write(0xB7); // Entry Mode
-		lcd_data_write(0x07); // disable low voltage detection, normal display, 
-		lcd_command_write(0xF0); // Enter ENG , must be set before gamma setting
-		lcd_data_write(0x36);
-		lcd_data_write(0xA5);
-		lcd_data_write(0xD3);
-		lcd_command_write(0xE5); // Open gamma function , must be set before gamma setting
-		lcd_data_write(0x80);
-		lcd_command_write(0xE5); // Page 1
-		lcd_data_write(0x01);
-		lcd_command_write(0XB3); // WEMODE=0(Page 1) , pixels over window setting will be ignored.//frame rate control in partial mode/full colors
-		lcd_data_write(0x00);
-		lcd_command_write(0xE5); // Page 0
-		lcd_data_write(0x00);
-		lcd_command_write(0xF0); // Exit ENG , must be set before gamma setting
-		lcd_data_write(0x36);
-		lcd_data_write(0xA5);
-		lcd_data_write(0x53);
-		lcd_command_write(0xE0); // Gamma setting
-		//y fine adjustment register for positive polarity
-		lcd_data_write(0x00);
-		lcd_data_write(0x35);
-		lcd_data_write(0x33);
-		//y gradient adjustment register for positive polarity
-		lcd_data_write(0x00);
-		//y amplitude adjustment register for positive polarity
-		lcd_data_write(0x00);
-		lcd_data_write(0x00);
-		//y fine adjustment register for negative polarity
-		lcd_data_write(0x00);
-		lcd_data_write(0x35);
-		lcd_data_write(0x33);
-		//y gradient adjustment register for negative polarity
-		lcd_data_write(0x00);
-		//y amplitude adjustment register for negative polarity
-		lcd_data_write(0x00);
-		lcd_data_write(0x00);
-		lcd_command_write(0x36); // memory data access control //
-		lcd_data_write(0x48);//
-		lcd_command_write(0x3A); // interface pixel format setting
-		lcd_data_write(0x55);//16-bits
-		lcd_command_write(0x11); // Exit sleep mode
-		lcd_command_write(0x29); // Display on 
+        lcd_command_write(0xC0);//power control1 command/w/
+        lcd_data_write(0x0A); // P-Gamma level//4.1875v
+        lcd_data_write(0x0A); // N-Gamma level
+        lcd_command_write(0xC1); // BT & VC Setting//power contrl2 command/w/
+        lcd_data_write(0x41);
+        lcd_data_write(0x07); // VCI1 = 2.5V
+        lcd_command_write(0xC2); // DC1.DC0 Setting//power control3 for normal mode
+        lcd_data_write(0x33);
+        lcd_command_write(0xC5);//VCOM control
+        lcd_data_write(0x00);  //NV memory is not programmed
+        lcd_data_write(0x42); // VCM Setting
+        lcd_data_write(0x80); // VCM Register Enable
+        lcd_command_write(0xB0);      //interface mode control //Polarity Setting
+        lcd_data_write(0x02);
+        lcd_command_write(0xB1);//frame rate control for normal mode
+        lcd_data_write(0xB0); // Frame Rate Setting//70 frame per second//no division for internal clocks
+        lcd_data_write(0x11);//17 clocks per line period for idle mode at cpu interface
+        lcd_command_write(0xB4);//dispaly inversion control
+        lcd_data_write(0x00); // disable Z-inversion , column inversion
+        lcd_command_write(0xB6); //display function control// RM.DM Setting
+        lcd_data_write(0x70);////0xF0
+        lcd_data_write(0x02);//direction of gate scan: G1->G480 one by one, source scan: S1->S960, scan cycle if interval scan in non-display area
+        lcd_data_write(0x3B); // number of lines to drive LCD: 8*(0x3C) = 480
+        lcd_command_write(0xB7); // Entry Mode
+        lcd_data_write(0x07); // disable low voltage detection, normal display,
+        lcd_command_write(0xF0); // Enter ENG , must be set before gamma setting
+        lcd_data_write(0x36);
+        lcd_data_write(0xA5);
+        lcd_data_write(0xD3);
+        lcd_command_write(0xE5); // Open gamma function , must be set before gamma setting
+        lcd_data_write(0x80);
+        lcd_command_write(0xE5); // Page 1
+        lcd_data_write(0x01);
+        lcd_command_write(0XB3); // WEMODE=0(Page 1) , pixels over window setting will be ignored.//frame rate control in partial mode/full colors
+        lcd_data_write(0x00);
+        lcd_command_write(0xE5); // Page 0
+        lcd_data_write(0x00);
+        lcd_command_write(0xF0); // Exit ENG , must be set before gamma setting
+        lcd_data_write(0x36);
+        lcd_data_write(0xA5);
+        lcd_data_write(0x53);
+        lcd_command_write(0xE0); // Gamma setting
+        //y fine adjustment register for positive polarity
+        lcd_data_write(0x00);
+        lcd_data_write(0x35);
+        lcd_data_write(0x33);
+        //y gradient adjustment register for positive polarity
+        lcd_data_write(0x00);
+        //y amplitude adjustment register for positive polarity
+        lcd_data_write(0x00);
+        lcd_data_write(0x00);
+        //y fine adjustment register for negative polarity
+        lcd_data_write(0x00);
+        lcd_data_write(0x35);
+        lcd_data_write(0x33);
+        //y gradient adjustment register for negative polarity
+        lcd_data_write(0x00);
+        //y amplitude adjustment register for negative polarity
+        lcd_data_write(0x00);
+        lcd_data_write(0x00);
+        lcd_command_write(0x36); // memory data access control //
+        lcd_data_write(0x48);//
+        lcd_command_write(0x3A); // interface pixel format setting
+        lcd_data_write(0x55);//16-bits
+        lcd_command_write(0x11); // Exit sleep mode
+        lcd_command_write(0x29); // Display on
 
-		delay(10);
+        delay(10);
 }
 /*!
     \brief      insert a delay time
diff --git a/bsp/gd32450z-eval/drivers/gd32f450z_lcd_eval.h b/bsp/gd32450z-eval/drivers/gd32f450z_lcd_eval.h
index 815925a170..00b7f51cb2 100644
--- a/bsp/gd32450z-eval/drivers/gd32f450z_lcd_eval.h
+++ b/bsp/gd32450z-eval/drivers/gd32f450z_lcd_eval.h
@@ -13,10 +13,10 @@
 #define GD32F450Z_LCD_EVAL_H
 
 #include "gd32f450z_eval.h"
-   
+
 #define LCD_CS_PIN                   GPIO_PIN_11
 #define LCD_CS_GPIO_PORT             GPIOD
-#define LCD_CS_GPIO_CLK              RCU_GPIOD 
+#define LCD_CS_GPIO_CLK              RCU_GPIOD
 
 #define LCD_RS_PIN                   GPIO_PIN_3
 #define LCD_RS_GPIO_PORT             GPIOE
@@ -28,7 +28,7 @@
 
 #define LCD_SPI_MOSI_PIN             GPIO_PIN_14
 #define LCD_SPI_MOSI_GPIO_PORT       GPIOG
-#define LCD_SPI_MOSI_GPIO_CLK        RCU_GPIOG 
+#define LCD_SPI_MOSI_GPIO_CLK        RCU_GPIOG
 
 #define LCD_SPI                      SPI5
 #define LCD_SPI_CLK                  RCU_SPI5
@@ -52,4 +52,4 @@ void lcd_data_write(uint8_t value);
 /* configure the LCD based on the power on sequence */
 void lcd_power_on(void);
 void lcd_power_on3(void);
-#endif /* GD32F450Z_LCD_EVAL_H */ 
+#endif /* GD32F450Z_LCD_EVAL_H */
diff --git a/bsp/gd32450z-eval/drivers/synopsys_emac.c b/bsp/gd32450z-eval/drivers/synopsys_emac.c
index dfe1dd39b6..1894792d82 100644
--- a/bsp/gd32450z-eval/drivers/synopsys_emac.c
+++ b/bsp/gd32450z-eval/drivers/synopsys_emac.c
@@ -1,21 +1,7 @@
 /*
- * File      : rthw.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  */
 #include "synopsys_emac.h"
 #include "gd32f4xx_enet.h"
diff --git a/bsp/gd32450z-eval/drivers/synopsys_emac.h b/bsp/gd32450z-eval/drivers/synopsys_emac.h
index cb0d62122f..f6c303ce7f 100644
--- a/bsp/gd32450z-eval/drivers/synopsys_emac.h
+++ b/bsp/gd32450z-eval/drivers/synopsys_emac.h
@@ -1,28 +1,14 @@
 /*
- * File      : rtdef.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 #ifndef __SYNOPSYS_EMAC_H__
 #define __SYNOPSYS_EMAC_H__
 
 #include 
-     
+
 
 /******************************************************************************/
 /*                Ethernet MAC Registers bits definitions                     */
@@ -48,8 +34,8 @@
 #define EMAC_MACCR_RD           ((rt_uint32_t)0x00000200)  /* Retry disable */
 #define EMAC_MACCR_APCS         ((rt_uint32_t)0x00000080)  /* Automatic Pad/CRC stripping */
 #define EMAC_MACCR_BL           ((rt_uint32_t)0x00000060)  /* Back-off limit: random integer number (r) of slot time delays before rescheduling
-															a transmission attempt during retries after a collision: 0 =< r <2^k */
-#define EMAC_MACCR_BL_10     	((rt_uint32_t)0x00000000)  /* k = min (n, 10) */
+                                                            a transmission attempt during retries after a collision: 0 =< r <2^k */
+#define EMAC_MACCR_BL_10        ((rt_uint32_t)0x00000000)  /* k = min (n, 10) */
 #define EMAC_MACCR_BL_8         ((rt_uint32_t)0x00000020)  /* k = min (n, 8) */
 #define EMAC_MACCR_BL_4         ((rt_uint32_t)0x00000040)  /* k = min (n, 4) */
 #define EMAC_MACCR_BL_1         ((rt_uint32_t)0x00000060)  /* k = min (n, 1) */
@@ -60,45 +46,45 @@
 /* Bit definition for Ethernet MAC Frame Filter Register */
 #define EMAC_MACFFR_RA          ((rt_uint32_t)0x80000000)  /* Receive all */
 #define EMAC_MACFFR_HPF         ((rt_uint32_t)0x00000400)  /* Hash or perfect filter */
-#define EMAC_MACFFR_SAF      	((rt_uint32_t)0x00000200)  /* Source address filter enable */
+#define EMAC_MACFFR_SAF         ((rt_uint32_t)0x00000200)  /* Source address filter enable */
 #define EMAC_MACFFR_SAIF        ((rt_uint32_t)0x00000100)  /* SA inverse filtering */
 #define EMAC_MACFFR_PCF         ((rt_uint32_t)0x000000C0)  /* Pass control frames: 3 cases */
 #define EMAC_MACFFR_PCF_BlockAll                ((rt_uint32_t)0x00000040)  /* MAC filters all control frames from reaching the application */
 #define EMAC_MACFFR_PCF_ForwardAll              ((rt_uint32_t)0x00000080)  /* MAC forwards all control frames to application even if they fail the Address Filter */
 #define EMAC_MACFFR_PCF_ForwardPassedAddrFilter ((rt_uint32_t)0x000000C0)  /* MAC forwards control frames that pass the Address Filter. */
 #define EMAC_MACFFR_BFD         ((rt_uint32_t)0x00000020)  /* Broadcast frame disable */
-#define EMAC_MACFFR_PAM       	((rt_uint32_t)0x00000010)  /* Pass all mutlicast */
+#define EMAC_MACFFR_PAM         ((rt_uint32_t)0x00000010)  /* Pass all mutlicast */
 #define EMAC_MACFFR_DAIF        ((rt_uint32_t)0x00000008)  /* DA Inverse filtering */
-#define EMAC_MACFFR_HM     	    ((rt_uint32_t)0x00000004)  /* Hash multicast */
-#define EMAC_MACFFR_HU     	    ((rt_uint32_t)0x00000002)  /* Hash unicast */
-#define EMAC_MACFFR_PM     	    ((rt_uint32_t)0x00000001)  /* Promiscuous mode */
+#define EMAC_MACFFR_HM          ((rt_uint32_t)0x00000004)  /* Hash multicast */
+#define EMAC_MACFFR_HU          ((rt_uint32_t)0x00000002)  /* Hash unicast */
+#define EMAC_MACFFR_PM          ((rt_uint32_t)0x00000001)  /* Promiscuous mode */
 
 /* Bit definition for Ethernet MAC Hash Table High Register */
-#define EMAC_MACHTHR_HTH   	    ((rt_uint32_t)0xFFFFFFFF)  /* Hash table high */
+#define EMAC_MACHTHR_HTH        ((rt_uint32_t)0xFFFFFFFF)  /* Hash table high */
 
 /* Bit definition for Ethernet MAC Hash Table Low Register */
-#define EMAC_MACHTLR_HTL  	    ((rt_uint32_t)0xFFFFFFFF)  /* Hash table low */
+#define EMAC_MACHTLR_HTL        ((rt_uint32_t)0xFFFFFFFF)  /* Hash table low */
 
 /* Bit definition for Ethernet MAC MII Address Register */
-#define EMAC_MACMIIAR_PA  	    ((rt_uint32_t)0x0000F800)  /* Physical layer address */
-#define EMAC_MACMIIAR_MR 	   	((rt_uint32_t)0x000007C0)  /* MII register in the selected PHY */
-#define EMAC_MACMIIAR_CR 	    ((rt_uint32_t)0x0000001C)  /* CR clock range: 6 cases */
+#define EMAC_MACMIIAR_PA        ((rt_uint32_t)0x0000F800)  /* Physical layer address */
+#define EMAC_MACMIIAR_MR        ((rt_uint32_t)0x000007C0)  /* MII register in the selected PHY */
+#define EMAC_MACMIIAR_CR        ((rt_uint32_t)0x0000001C)  /* CR clock range: 6 cases */
 #define EMAC_MACMIIAR_CR_Div42  ((rt_uint32_t)0x00000000)  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
 #define EMAC_MACMIIAR_CR_Div62  ((rt_uint32_t)0x00000004)  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
 #define EMAC_MACMIIAR_CR_Div16  ((rt_uint32_t)0x00000008)  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
 #define EMAC_MACMIIAR_CR_Div26  ((rt_uint32_t)0x0000000C)  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
 #define EMAC_MACMIIAR_CR_Div102 ((rt_uint32_t)0x00000010)  /* HCLK:150-250 MHz; MDC clock= HCLK/102 */
 #define EMAC_MACMIIAR_CR_Div122 ((rt_uint32_t)0x00000014)  /* HCLK:250-300 MHz; MDC clock= HCLK/122*/
-#define EMAC_MACMIIAR_MW   	  	((rt_uint32_t)0x00000002)  /* MII write */
-#define EMAC_MACMIIAR_MB   		((rt_uint32_t)0x00000001)  /* MII busy */
+#define EMAC_MACMIIAR_MW        ((rt_uint32_t)0x00000002)  /* MII write */
+#define EMAC_MACMIIAR_MB        ((rt_uint32_t)0x00000001)  /* MII busy */
 
 /* Bit definition for Ethernet MAC MII Data Register */
-#define EMAC_MACMIIDR_MD  	 	((rt_uint32_t)0x0000FFFF)  /* MII data: read/write data from/to PHY */
+#define EMAC_MACMIIDR_MD        ((rt_uint32_t)0x0000FFFF)  /* MII data: read/write data from/to PHY */
 
 /* Bit definition for Ethernet MAC Flow Control Register */
-#define EMAC_MACFCR_PT    		((rt_uint32_t)0xFFFF0000)  /* Pause time */
-#define EMAC_MACFCR_ZQPD   		((rt_uint32_t)0x00000080)  /* Zero-quanta pause disable */
-#define EMAC_MACFCR_PLT    		((rt_uint32_t)0x00000030)  /* Pause low threshold: 4 cases */
+#define EMAC_MACFCR_PT          ((rt_uint32_t)0xFFFF0000)  /* Pause time */
+#define EMAC_MACFCR_ZQPD        ((rt_uint32_t)0x00000080)  /* Zero-quanta pause disable */
+#define EMAC_MACFCR_PLT         ((rt_uint32_t)0x00000030)  /* Pause low threshold: 4 cases */
 #define EMAC_MACFCR_PLT_Minus4   ((rt_uint32_t)0x00000000)  /* Pause time minus 4 slot times */
 #define EMAC_MACFCR_PLT_Minus28  ((rt_uint32_t)0x00000010)  /* Pause time minus 28 slot times */
 #define EMAC_MACFCR_PLT_Minus144 ((rt_uint32_t)0x00000020)  /* Pause time minus 144 slot times */
@@ -441,7 +427,7 @@
 #define EMAC_DMACHRBAR_HRBAP  ((rt_uint32_t)0xFFFFFFFF)  /* Host receive buffer address pointer */
 
 //typedef enum {
-//	RESET = 0, SET = !RESET
+//  RESET = 0, SET = !RESET
 //} FlagStatus, ITStatus;
 //typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
 
@@ -450,165 +436,165 @@
  */
 typedef struct
 {
-	/**
-	 * MAC
-	 */
-	rt_uint32_t             EMAC_AutoNegotiation;           /* Selects or not the AutoNegotiation mode for the external PHY
-															The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
-															and the mode (half/full-duplex).
-															This parameter can be a value of @ref EMAC_AutoNegotiation */
+    /**
+     * MAC
+     */
+    rt_uint32_t             EMAC_AutoNegotiation;           /* Selects or not the AutoNegotiation mode for the external PHY
+                                                            The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
+                                                            and the mode (half/full-duplex).
+                                                            This parameter can be a value of @ref EMAC_AutoNegotiation */
 
-	rt_uint32_t             EMAC_Watchdog;                  /* Selects or not the Watchdog timer
-															When enabled, the MAC allows no more then 2048 bytes to be received.
-															When disabled, the MAC can receive up to 16384 bytes.
-															This parameter can be a value of @ref EMAC_watchdog */
+    rt_uint32_t             EMAC_Watchdog;                  /* Selects or not the Watchdog timer
+                                                            When enabled, the MAC allows no more then 2048 bytes to be received.
+                                                            When disabled, the MAC can receive up to 16384 bytes.
+                                                            This parameter can be a value of @ref EMAC_watchdog */
 
-	rt_uint32_t             EMAC_Jabber;                    /* Selects or not Jabber timer
-															When enabled, the MAC allows no more then 2048 bytes to be sent.
-															When disabled, the MAC can send up to 16384 bytes.
-															This parameter can be a value of @ref EMAC_Jabber */
+    rt_uint32_t             EMAC_Jabber;                    /* Selects or not Jabber timer
+                                                            When enabled, the MAC allows no more then 2048 bytes to be sent.
+                                                            When disabled, the MAC can send up to 16384 bytes.
+                                                            This parameter can be a value of @ref EMAC_Jabber */
 
-	rt_uint32_t             EMAC_InterFrameGap;             /* Selects the minimum IFG between frames during transmission
-															This parameter can be a value of @ref EMAC_Inter_Frame_Gap */
+    rt_uint32_t             EMAC_InterFrameGap;             /* Selects the minimum IFG between frames during transmission
+                                                            This parameter can be a value of @ref EMAC_Inter_Frame_Gap */
 
-	rt_uint32_t             EMAC_CarrierSense;              /* Selects or not the Carrier Sense
-															This parameter can be a value of @ref EMAC_Carrier_Sense */
+    rt_uint32_t             EMAC_CarrierSense;              /* Selects or not the Carrier Sense
+                                                            This parameter can be a value of @ref EMAC_Carrier_Sense */
 
-	rt_uint32_t             EMAC_Speed;                     /* Sets the Ethernet speed: 10/100 Mbps
-															This parameter can be a value of @ref EMAC_Speed */
+    rt_uint32_t             EMAC_Speed;                     /* Sets the Ethernet speed: 10/100 Mbps
+                                                            This parameter can be a value of @ref EMAC_Speed */
 
-	rt_uint32_t             EMAC_ReceiveOwn;                /* Selects or not the ReceiveOwn
-															ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
-															in Half-Duplex mode
-															This parameter can be a value of @ref EMAC_Receive_Own */
+    rt_uint32_t             EMAC_ReceiveOwn;                /* Selects or not the ReceiveOwn
+                                                            ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
+                                                            in Half-Duplex mode
+                                                            This parameter can be a value of @ref EMAC_Receive_Own */
 
-	rt_uint32_t             EMAC_LoopbackMode;              /* Selects or not the internal MAC MII Loopback mode
-															This parameter can be a value of @ref EMAC_Loop_Back_Mode */
+    rt_uint32_t             EMAC_LoopbackMode;              /* Selects or not the internal MAC MII Loopback mode
+                                                            This parameter can be a value of @ref EMAC_Loop_Back_Mode */
 
-	rt_uint32_t             EMAC_Mode;                      /* Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
-															This parameter can be a value of @ref EMAC_Duplex_Mode */
+    rt_uint32_t             EMAC_Mode;                      /* Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
+                                                            This parameter can be a value of @ref EMAC_Duplex_Mode */
 
-	rt_uint32_t             EMAC_ChecksumOffload;           /* Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
-															This parameter can be a value of @ref EMAC_Checksum_Offload */
+    rt_uint32_t             EMAC_ChecksumOffload;           /* Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
+                                                            This parameter can be a value of @ref EMAC_Checksum_Offload */
 
-	rt_uint32_t             EMAC_RetryTransmission;         /* Selects or not the MAC attempt retries transmission, based on the settings of BL,
-															when a colision occurs (Half-Duplex mode)
-															This parameter can be a value of @ref EMAC_Retry_Transmission */
+    rt_uint32_t             EMAC_RetryTransmission;         /* Selects or not the MAC attempt retries transmission, based on the settings of BL,
+                                                            when a colision occurs (Half-Duplex mode)
+                                                            This parameter can be a value of @ref EMAC_Retry_Transmission */
 
-	rt_uint32_t             EMAC_AutomaticPadCRCStrip;      /* Selects or not the Automatic MAC Pad/CRC Stripping
-															This parameter can be a value of @ref EMAC_Automatic_Pad_CRC_Strip */
+    rt_uint32_t             EMAC_AutomaticPadCRCStrip;      /* Selects or not the Automatic MAC Pad/CRC Stripping
+                                                            This parameter can be a value of @ref EMAC_Automatic_Pad_CRC_Strip */
 
-	rt_uint32_t             EMAC_BackOffLimit;              /* Selects the BackOff limit value
-															This parameter can be a value of @ref EMAC_Back_Off_Limit */
+    rt_uint32_t             EMAC_BackOffLimit;              /* Selects the BackOff limit value
+                                                            This parameter can be a value of @ref EMAC_Back_Off_Limit */
 
-	rt_uint32_t             EMAC_DeferralCheck;             /* Selects or not the deferral check function (Half-Duplex mode)
-															This parameter can be a value of @ref EMAC_Deferral_Check */
+    rt_uint32_t             EMAC_DeferralCheck;             /* Selects or not the deferral check function (Half-Duplex mode)
+                                                            This parameter can be a value of @ref EMAC_Deferral_Check */
 
-	rt_uint32_t             EMAC_ReceiveAll;                /* Selects or not all frames reception by the MAC (No fitering)
-															This parameter can be a value of @ref EMAC_Receive_All */
+    rt_uint32_t             EMAC_ReceiveAll;                /* Selects or not all frames reception by the MAC (No fitering)
+                                                            This parameter can be a value of @ref EMAC_Receive_All */
 
-	rt_uint32_t             EMAC_SourceAddrFilter;          /* Selects the Source Address Filter mode
-															This parameter can be a value of @ref EMAC_Source_Addr_Filter */
+    rt_uint32_t             EMAC_SourceAddrFilter;          /* Selects the Source Address Filter mode
+                                                            This parameter can be a value of @ref EMAC_Source_Addr_Filter */
 
-	rt_uint32_t             EMAC_PassControlFrames;         /* Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
-															This parameter can be a value of @ref EMAC_Pass_Control_Frames */
+    rt_uint32_t             EMAC_PassControlFrames;         /* Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
+                                                            This parameter can be a value of @ref EMAC_Pass_Control_Frames */
 
-	rt_uint32_t             EMAC_BroadcastFramesReception;  /* Selects or not the reception of Broadcast Frames
-															This parameter can be a value of @ref EMAC_Broadcast_Frames_Reception */
+    rt_uint32_t             EMAC_BroadcastFramesReception;  /* Selects or not the reception of Broadcast Frames
+                                                            This parameter can be a value of @ref EMAC_Broadcast_Frames_Reception */
 
-	rt_uint32_t             EMAC_DestinationAddrFilter;     /* Sets the destination filter mode for both unicast and multicast frames
-															This parameter can be a value of @ref EMAC_Destination_Addr_Filter */
+    rt_uint32_t             EMAC_DestinationAddrFilter;     /* Sets the destination filter mode for both unicast and multicast frames
+                                                            This parameter can be a value of @ref EMAC_Destination_Addr_Filter */
 
-	rt_uint32_t             EMAC_PromiscuousMode;           /* Selects or not the Promiscuous Mode
-															This parameter can be a value of @ref EMAC_Promiscuous_Mode */
+    rt_uint32_t             EMAC_PromiscuousMode;           /* Selects or not the Promiscuous Mode
+                                                            This parameter can be a value of @ref EMAC_Promiscuous_Mode */
 
-	rt_uint32_t             EMAC_MulticastFramesFilter;     /* Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter
-															This parameter can be a value of @ref EMAC_Multicast_Frames_Filter */
+    rt_uint32_t             EMAC_MulticastFramesFilter;     /* Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter
+                                                            This parameter can be a value of @ref EMAC_Multicast_Frames_Filter */
 
-	rt_uint32_t             EMAC_UnicastFramesFilter;       /* Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter
-															This parameter can be a value of @ref EMAC_Unicast_Frames_Filter */
+    rt_uint32_t             EMAC_UnicastFramesFilter;       /* Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter
+                                                            This parameter can be a value of @ref EMAC_Unicast_Frames_Filter */
 
-	rt_uint32_t             EMAC_HashTableHigh;             /* This field holds the higher 32 bits of Hash table.  */
+    rt_uint32_t             EMAC_HashTableHigh;             /* This field holds the higher 32 bits of Hash table.  */
 
-	rt_uint32_t             EMAC_HashTableLow;              /* This field holds the lower 32 bits of Hash table.  */
+    rt_uint32_t             EMAC_HashTableLow;              /* This field holds the lower 32 bits of Hash table.  */
 
-	rt_uint32_t             EMAC_PauseTime;                 /* This field holds the value to be used in the Pause Time field in the
-															transmit control frame */
+    rt_uint32_t             EMAC_PauseTime;                 /* This field holds the value to be used in the Pause Time field in the
+                                                            transmit control frame */
 
-	rt_uint32_t             EMAC_ZeroQuantaPause;           /* Selects or not the automatic generation of Zero-Quanta Pause Control frames
-															This parameter can be a value of @ref EMAC_Zero_Quanta_Pause */
+    rt_uint32_t             EMAC_ZeroQuantaPause;           /* Selects or not the automatic generation of Zero-Quanta Pause Control frames
+                                                            This parameter can be a value of @ref EMAC_Zero_Quanta_Pause */
 
-	rt_uint32_t             EMAC_PauseLowThreshold;         /* This field configures the threshold of the PAUSE to be checked for
-															automatic retransmission of PAUSE Frame
-															This parameter can be a value of @ref EMAC_Pause_Low_Threshold */
+    rt_uint32_t             EMAC_PauseLowThreshold;         /* This field configures the threshold of the PAUSE to be checked for
+                                                            automatic retransmission of PAUSE Frame
+                                                            This parameter can be a value of @ref EMAC_Pause_Low_Threshold */
 
-	rt_uint32_t             EMAC_UnicastPauseFrameDetect;   /* Selects or not the MAC detection of the Pause frames (with MAC Address0
-															unicast address and unique multicast address)
-															This parameter can be a value of @ref EMAC_Unicast_Pause_Frame_Detect */
+    rt_uint32_t             EMAC_UnicastPauseFrameDetect;   /* Selects or not the MAC detection of the Pause frames (with MAC Address0
+                                                            unicast address and unique multicast address)
+                                                            This parameter can be a value of @ref EMAC_Unicast_Pause_Frame_Detect */
 
-	rt_uint32_t             EMAC_ReceiveFlowControl;        /* Enables or disables the MAC to decode the received Pause frame and
-															disable its transmitter for a specified time (Pause Time)
-															This parameter can be a value of @ref EMAC_Receive_Flow_Control */
+    rt_uint32_t             EMAC_ReceiveFlowControl;        /* Enables or disables the MAC to decode the received Pause frame and
+                                                            disable its transmitter for a specified time (Pause Time)
+                                                            This parameter can be a value of @ref EMAC_Receive_Flow_Control */
 
-	rt_uint32_t             EMAC_TransmitFlowControl;       /* Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
-															or the MAC back-pressure operation (Half-Duplex mode)
-															This parameter can be a value of @ref EMAC_Transmit_Flow_Control */
+    rt_uint32_t             EMAC_TransmitFlowControl;       /* Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
+                                                            or the MAC back-pressure operation (Half-Duplex mode)
+                                                            This parameter can be a value of @ref EMAC_Transmit_Flow_Control */
 
-	rt_uint32_t             EMAC_VLANTagComparison;         /* Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
-															comparison and filtering
-															This parameter can be a value of @ref EMAC_VLAN_Tag_Comparison */
+    rt_uint32_t             EMAC_VLANTagComparison;         /* Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
+                                                            comparison and filtering
+                                                            This parameter can be a value of @ref EMAC_VLAN_Tag_Comparison */
 
-	rt_uint32_t             EMAC_VLANTagIdentifier;         /* Holds the VLAN tag identifier for receive frames */
+    rt_uint32_t             EMAC_VLANTagIdentifier;         /* Holds the VLAN tag identifier for receive frames */
 
-	/**
-	 * DMA
-	 */
+    /**
+     * DMA
+     */
 
-	rt_uint32_t             EMAC_DropTCPIPChecksumErrorFrame; /* Selects or not the Dropping of TCP/IP Checksum Error Frames
-															  This parameter can be a value of @ref EMAC_Drop_TCP_IP_Checksum_Error_Frame */
+    rt_uint32_t             EMAC_DropTCPIPChecksumErrorFrame; /* Selects or not the Dropping of TCP/IP Checksum Error Frames
+                                                              This parameter can be a value of @ref EMAC_Drop_TCP_IP_Checksum_Error_Frame */
 
-	rt_uint32_t             EMAC_ReceiveStoreForward;         /* Enables or disables the Receive store and forward mode
-															  This parameter can be a value of @ref EMAC_Receive_Store_Forward */
+    rt_uint32_t             EMAC_ReceiveStoreForward;         /* Enables or disables the Receive store and forward mode
+                                                              This parameter can be a value of @ref EMAC_Receive_Store_Forward */
 
-	rt_uint32_t             EMAC_FlushReceivedFrame;          /* Enables or disables the flushing of received frames
-															  This parameter can be a value of @ref EMAC_Flush_Received_Frame */
+    rt_uint32_t             EMAC_FlushReceivedFrame;          /* Enables or disables the flushing of received frames
+                                                              This parameter can be a value of @ref EMAC_Flush_Received_Frame */
 
-	rt_uint32_t             EMAC_TransmitStoreForward;        /* Enables or disables Transmit store and forward mode
-															  This parameter can be a value of @ref EMAC_Transmit_Store_Forward */
+    rt_uint32_t             EMAC_TransmitStoreForward;        /* Enables or disables Transmit store and forward mode
+                                                              This parameter can be a value of @ref EMAC_Transmit_Store_Forward */
 
-	rt_uint32_t             EMAC_TransmitThresholdControl;    /* Selects or not the Transmit Threshold Control
-															  This parameter can be a value of @ref EMAC_Transmit_Threshold_Control */
+    rt_uint32_t             EMAC_TransmitThresholdControl;    /* Selects or not the Transmit Threshold Control
+                                                              This parameter can be a value of @ref EMAC_Transmit_Threshold_Control */
 
-	rt_uint32_t             EMAC_ForwardErrorFrames;          /* Selects or not the forward to the DMA of erroneous frames
-															  This parameter can be a value of @ref EMAC_Forward_Error_Frames */
+    rt_uint32_t             EMAC_ForwardErrorFrames;          /* Selects or not the forward to the DMA of erroneous frames
+                                                              This parameter can be a value of @ref EMAC_Forward_Error_Frames */
 
-	rt_uint32_t             EMAC_ForwardUndersizedGoodFrames; /* Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
-															  and length less than 64 bytes) including pad-bytes and CRC)
-															  This parameter can be a value of @ref EMAC_Forward_Undersized_Good_Frames */
+    rt_uint32_t             EMAC_ForwardUndersizedGoodFrames; /* Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
+                                                              and length less than 64 bytes) including pad-bytes and CRC)
+                                                              This parameter can be a value of @ref EMAC_Forward_Undersized_Good_Frames */
 
-	rt_uint32_t             EMAC_ReceiveThresholdControl;     /* Selects the threshold level of the Receive FIFO
-															  This parameter can be a value of @ref EMAC_Receive_Threshold_Control */
+    rt_uint32_t             EMAC_ReceiveThresholdControl;     /* Selects the threshold level of the Receive FIFO
+                                                              This parameter can be a value of @ref EMAC_Receive_Threshold_Control */
 
-	rt_uint32_t             EMAC_SecondFrameOperate;          /* Selects or not the Operate on second frame mode, which allows the DMA to process a second
-															  frame of Transmit data even before obtaining the status for the first frame.
-															  This parameter can be a value of @ref EMAC_Second_Frame_Operate */
+    rt_uint32_t             EMAC_SecondFrameOperate;          /* Selects or not the Operate on second frame mode, which allows the DMA to process a second
+                                                              frame of Transmit data even before obtaining the status for the first frame.
+                                                              This parameter can be a value of @ref EMAC_Second_Frame_Operate */
 
-	rt_uint32_t             EMAC_AddressAlignedBeats;         /* Enables or disables the Address Aligned Beats
-															  This parameter can be a value of @ref EMAC_Address_Aligned_Beats */
+    rt_uint32_t             EMAC_AddressAlignedBeats;         /* Enables or disables the Address Aligned Beats
+                                                              This parameter can be a value of @ref EMAC_Address_Aligned_Beats */
 
-	rt_uint32_t             EMAC_FixedBurst;                  /* Enables or disables the AHB Master interface fixed burst transfers
-															  This parameter can be a value of @ref EMAC_Fixed_Burst */
+    rt_uint32_t             EMAC_FixedBurst;                  /* Enables or disables the AHB Master interface fixed burst transfers
+                                                              This parameter can be a value of @ref EMAC_Fixed_Burst */
 
-	rt_uint32_t             EMAC_RxDMABurstLength;            /* Indicates the maximum number of beats to be transferred in one Rx DMA transaction
-															  This parameter can be a value of @ref EMAC_Rx_DMA_Burst_Length */
+    rt_uint32_t             EMAC_RxDMABurstLength;            /* Indicates the maximum number of beats to be transferred in one Rx DMA transaction
+                                                              This parameter can be a value of @ref EMAC_Rx_DMA_Burst_Length */
 
-	rt_uint32_t             EMAC_TxDMABurstLength;            /* Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction
-															  This parameter can be a value of @ref EMAC_Tx_DMA_Burst_Length */
+    rt_uint32_t             EMAC_TxDMABurstLength;            /* Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction
+                                                              This parameter can be a value of @ref EMAC_Tx_DMA_Burst_Length */
 
-	rt_uint32_t             EMAC_DescriptorSkipLength;        /* Specifies the number of word to skip between two unchained int (Ring mode) */
+    rt_uint32_t             EMAC_DescriptorSkipLength;        /* Specifies the number of word to skip between two unchained int (Ring mode) */
 
-	rt_uint32_t             EMAC_DMAArbitration;              /* Selects the DMA Tx/Rx arbitration
-															  This parameter can be a value of @ref EMAC_DMA_Arbitration */
+    rt_uint32_t             EMAC_DMAArbitration;              /* Selects the DMA Tx/Rx arbitration
+                                                              This parameter can be a value of @ref EMAC_DMA_Arbitration */
 } EMAC_InitTypeDef;
 
 /**--------------------------------------------------------------------------**/
@@ -622,10 +608,10 @@ typedef struct
  */
 typedef struct
 {
-	rt_uint32_t   Status;                /* Status */
-	rt_uint32_t   ControlBufferSize;     /* Control and Buffer1, Buffer2 lengths */
-	rt_uint32_t   Buffer1Addr;           /* Buffer1 address pointer */
-	rt_uint32_t   Buffer2NextDescAddr;   /* Buffer2 or next descriptor address pointer */
+    rt_uint32_t   Status;                /* Status */
+    rt_uint32_t   ControlBufferSize;     /* Control and Buffer1, Buffer2 lengths */
+    rt_uint32_t   Buffer1Addr;           /* Buffer1 address pointer */
+    rt_uint32_t   Buffer2NextDescAddr;   /* Buffer2 or next descriptor address pointer */
 } EMAC_DMADESCTypeDef;
 
 /**--------------------------------------------------------------------------**/
@@ -634,14 +620,14 @@ typedef struct
  */
 /**--------------------------------------------------------------------------**/
 
-#define EMAC_MAX_PACKET_SIZE    	1520    /* EMAC_HEADER + EMAC_EXTRA + MAX_EMAC_PAYLOAD + EMAC_CRC */
-#define EMAC_HEADER               	14    	/* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
-#define EMAC_CRC                   	4    	/* Ethernet CRC */
-#define EMAC_EXTRA                 	2    	/* Extra bytes in some cases */
-#define VLAN_TAG                  	4    	/* optional 802.1q VLAN Tag */
-#define MIN_EMAC_PAYLOAD          	46    	/* Minimum Ethernet payload size */
-#define MAX_EMAC_PAYLOAD        	1500    /* Maximum Ethernet payload size */
-#define JUMBO_FRAME_PAYLOAD    		9000    /* Jumbo frame payload size */
+#define EMAC_MAX_PACKET_SIZE        1520    /* EMAC_HEADER + EMAC_EXTRA + MAX_EMAC_PAYLOAD + EMAC_CRC */
+#define EMAC_HEADER                 14      /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
+#define EMAC_CRC                    4       /* Ethernet CRC */
+#define EMAC_EXTRA                  2       /* Extra bytes in some cases */
+#define VLAN_TAG                    4       /* optional 802.1q VLAN Tag */
+#define MIN_EMAC_PAYLOAD            46      /* Minimum Ethernet payload size */
+#define MAX_EMAC_PAYLOAD            1500    /* Maximum Ethernet payload size */
+#define JUMBO_FRAME_PAYLOAD         9000    /* Jumbo frame payload size */
 
 /**--------------------------------------------------------------------------**/
 /**
@@ -1098,7 +1084,7 @@ struct rt_synopsys_eth
     volatile rt_uint32_t FCR;
     volatile rt_uint32_t VTR;
                rt_uint8_t RESERVED0[8];
-    
+
     volatile rt_uint32_t RWFFR;
     volatile rt_uint32_t PMTR;
     volatile rt_uint32_t LPICSR;
diff --git a/bsp/gd32e230k-start/applications/main.c b/bsp/gd32e230k-start/applications/main.c
index cabddf36d6..999becd329 100644
--- a/bsp/gd32e230k-start/applications/main.c
+++ b/bsp/gd32e230k-start/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/gd32e230k-start/drivers/board.c b/bsp/gd32e230k-start/drivers/board.c
index ea91fd7eb8..5910ec4124 100644
--- a/bsp/gd32e230k-start/drivers/board.c
+++ b/bsp/gd32e230k-start/drivers/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -75,7 +75,7 @@ void rt_hw_board_init()
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
 
-#ifdef RT_USING_HEAP   
+#ifdef RT_USING_HEAP
     rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END);
 #endif
 }
diff --git a/bsp/gd32e230k-start/drivers/board.h b/bsp/gd32e230k-start/drivers/board.h
index abc8743562..7d491aeaa8 100644
--- a/bsp/gd32e230k-start/drivers/board.h
+++ b/bsp/gd32e230k-start/drivers/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,7 +15,7 @@
 #include 
 
 //  Internal SRAM memory size[Kbytes] <8-64>
-//	Default: 64
+//  Default: 64
 #ifdef __ICCARM__
 // Use *.icf ram symbal, to avoid hardcode.
 extern char __ICFEDIT_region_RAM_end__;
diff --git a/bsp/gd32e230k-start/drivers/drv_gpio.c b/bsp/gd32e230k-start/drivers/drv_gpio.c
index 4176798cfd..752f1489d7 100644
--- a/bsp/gd32e230k-start/drivers/drv_gpio.c
+++ b/bsp/gd32e230k-start/drivers/drv_gpio.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -29,8 +29,8 @@ struct pin_index
     rcu_periph_enum clk;
     rt_uint32_t gpio_periph;
     rt_uint32_t pin;
-	  rt_uint32_t port_src;
-	  rt_uint32_t pin_src;
+      rt_uint32_t port_src;
+      rt_uint32_t pin_src;
 };
 
 static const struct pin_index pins[] =
@@ -38,8 +38,8 @@ static const struct pin_index pins[] =
     __GD32_PIN_DEFAULT,
     __GD32_PIN(2, F, 0),
     __GD32_PIN(3, F, 1),
-	  __GD32_PIN_DEFAULT,
-		__GD32_PIN_DEFAULT,
+      __GD32_PIN_DEFAULT,
+        __GD32_PIN_DEFAULT,
     __GD32_PIN(6, A, 0),
     __GD32_PIN(7, A, 1),
     __GD32_PIN(8, A, 2),
@@ -51,7 +51,7 @@ static const struct pin_index pins[] =
     __GD32_PIN(14, B, 0),
     __GD32_PIN(15, B, 1),
     __GD32_PIN(16, B, 2),
-		__GD32_PIN_DEFAULT,
+        __GD32_PIN_DEFAULT,
     __GD32_PIN(18, A, 8),
     __GD32_PIN(19, A, 9),
     __GD32_PIN(20, A, 10),
@@ -136,8 +136,8 @@ void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
 {
     const struct pin_index *index;
     rt_uint32_t pin_mode;
-	  rt_uint32_t otype;
-	  rt_uint32_t pull_up_down;
+      rt_uint32_t otype;
+      rt_uint32_t pull_up_down;
     index = get_pin(pin);
     if (index == RT_NULL)
     {
@@ -147,9 +147,9 @@ void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
     /* GPIO Periph clock enable */
     rcu_periph_clock_enable(index->clk);
     pin_mode = GPIO_MODE_OUTPUT;
-		otype = GPIO_OTYPE_PP;
-		pull_up_down = GPIO_PUPD_NONE;
-    
+        otype = GPIO_OTYPE_PP;
+        pull_up_down = GPIO_PUPD_NONE;
+
    switch(mode)
    {
    case PIN_MODE_OUTPUT:
@@ -157,7 +157,7 @@ void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
         break;
    case PIN_MODE_OUTPUT_OD:
         /* output setting: od. */
-		    otype = GPIO_OTYPE_OD;
+            otype = GPIO_OTYPE_OD;
         break;
    case PIN_MODE_INPUT:
         /* input setting: not pull. */
@@ -166,20 +166,20 @@ void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
    case PIN_MODE_INPUT_PULLUP:
         /* input setting: pull up. */
         pin_mode = GPIO_MODE_INPUT;
-	      pull_up_down = GPIO_PUPD_PULLUP;
+          pull_up_down = GPIO_PUPD_PULLUP;
         break;
    case PIN_MODE_INPUT_PULLDOWN:
         /* input setting: pull down. */
-	      pin_mode = GPIO_MODE_INPUT;
-	      pull_up_down = GPIO_PUPD_PULLDOWN;
+          pin_mode = GPIO_MODE_INPUT;
+          pull_up_down = GPIO_PUPD_PULLDOWN;
         break;
    default:
         break;
    }
 
-	  gpio_mode_set(index->gpio_periph, pin_mode, pull_up_down, index->pin);
+      gpio_mode_set(index->gpio_periph, pin_mode, pull_up_down, index->pin);
     gpio_output_options_set(index->gpio_periph, otype, GPIO_OSPEED_50MHZ, index->pin);
-	 
+
 }
 
 void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
@@ -333,7 +333,7 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_
             return RT_EINVAL;
         }
         irqmap = &pin_irq_map[hdr_index];
-   
+
         switch (pin_irq_hdr_tab[hdr_index].mode)
         {
             case PIN_IRQ_MODE_RISING:
@@ -354,14 +354,14 @@ rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_
 
         /* enable and set interrupt priority */
         nvic_irq_enable(irqmap->irqno, 5U);
-        
+
         /* connect EXTI line to  GPIO pin */
-				syscfg_exti_line_config(index->port_src, index->pin_src);
+                syscfg_exti_line_config(index->port_src, index->pin_src);
 
         /* configure EXTI line */
         exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode);
         exti_interrupt_flag_clear((exti_line_enum)(index->pin));
-        
+
         rt_hw_interrupt_enable(level);
     }
     else if (enabled == PIN_IRQ_DISABLE)
@@ -396,7 +396,7 @@ int rt_hw_pin_init(void)
     int result;
 
     result = rt_device_pin_register("pin", &_gd32_pin_ops, RT_NULL);
-    
+
     return result;
 }
 INIT_BOARD_EXPORT(rt_hw_pin_init);
@@ -415,7 +415,7 @@ void GD32_GPIO_EXTI_IRQHandler(rt_int8_t exti_line)
     {
         pin_irq_hdr(exti_line);
         exti_interrupt_flag_clear((exti_line_enum)(1 << exti_line));
-    } 
+    }
 }
 void EXTI0_IRQHandler(void)
 {
diff --git a/bsp/gd32e230k-start/drivers/drv_gpio.h b/bsp/gd32e230k-start/drivers/drv_gpio.h
index 3c758b2713..ae9bda7dce 100644
--- a/bsp/gd32e230k-start/drivers/drv_gpio.h
+++ b/bsp/gd32e230k-start/drivers/drv_gpio.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/gd32e230k-start/drivers/drv_i2c.c b/bsp/gd32e230k-start/drivers/drv_i2c.c
index 57f49e4633..62cd4eb973 100644
--- a/bsp/gd32e230k-start/drivers/drv_i2c.c
+++ b/bsp/gd32e230k-start/drivers/drv_i2c.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -155,7 +155,7 @@ static int gd32_i2c_read(rt_uint32_t i2c_periph, rt_uint16_t slave_address, rt_u
             *p_buffer = i2c_data_receive(i2c_periph);
 
             /* point to the next location where the byte read will be saved */
-            p_buffer++; 
+            p_buffer++;
 
             /* decrement the read bytes counter */
             data_byte--;
@@ -264,7 +264,7 @@ static rt_size_t gd32_i2c_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg
             }
         }
     }
-    
+
     ret = i;
 
 out:
@@ -274,7 +274,7 @@ out:
 }
 
 static const struct rt_i2c_bus_device_ops i2c_ops =
-{ 
+{
     gd32_i2c_xfer,
     RT_NULL,
     RT_NULL
@@ -311,7 +311,7 @@ int rt_hw_i2c_init(void)
 
         i2c_device.priv = (void *)&_i2c_bit_ops;
         rt_i2c_bit_add_bus(&i2c_device, I2C_BUS_NAME);
-    } 
+    }
 
 #else   /* register hardware I2C */
 
diff --git a/bsp/gd32e230k-start/drivers/drv_i2c.h b/bsp/gd32e230k-start/drivers/drv_i2c.h
index 6e7de45260..c4b321594c 100644
--- a/bsp/gd32e230k-start/drivers/drv_i2c.h
+++ b/bsp/gd32e230k-start/drivers/drv_i2c.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/gd32e230k-start/drivers/drv_spi.c b/bsp/gd32e230k-start/drivers/drv_spi.c
index 706756d3de..8efc2a4664 100644
--- a/bsp/gd32e230k-start/drivers/drv_spi.c
+++ b/bsp/gd32e230k-start/drivers/drv_spi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -115,7 +115,7 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat
             spi_init_struct.prescale = SPI_PSC_256;
         }
     } /* baudrate */
-    
+
     switch(configuration->mode & RT_SPI_MODE_3)
     {
     case RT_SPI_MODE_0:
@@ -131,7 +131,7 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat
         spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE;
         break;
     }
-    
+
     /* MSB or LSB */
     if(configuration->mode & RT_SPI_MSB)
     {
@@ -141,7 +141,7 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat
     {
         spi_init_struct.endian = SPI_ENDIAN_LSB;
     }
-    
+
     spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX;
     spi_init_struct.device_mode = SPI_MASTER;
     spi_init_struct.nss = SPI_NSS_SOFT;
@@ -177,7 +177,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
             const rt_uint8_t * send_ptr = message->send_buf;
             rt_uint8_t * recv_ptr = message->recv_buf;
             rt_uint32_t size = message->length;
-            
+
             DEBUG_PRINTF("spi poll transfer start: %d\n", size);
 
             while(size--)
@@ -188,7 +188,7 @@ static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* mes
                 {
                     data = *send_ptr++;
                 }
-                
+
                 // Todo: replace register read/write by gd32f3 lib
                 //Wait until the transmit buffer is empty
                 while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE));
diff --git a/bsp/gd32e230k-start/drivers/drv_spi.h b/bsp/gd32e230k-start/drivers/drv_spi.h
index 01bafb9964..ba8e55916a 100644
--- a/bsp/gd32e230k-start/drivers/drv_spi.h
+++ b/bsp/gd32e230k-start/drivers/drv_spi.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/gd32e230k-start/drivers/drv_usart.c b/bsp/gd32e230k-start/drivers/drv_usart.c
index bf1f6b68a7..204ffa1ca1 100644
--- a/bsp/gd32e230k-start/drivers/drv_usart.c
+++ b/bsp/gd32e230k-start/drivers/drv_usart.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -41,7 +41,7 @@ struct gd32_uart
     uint16_t tx_pin;
     uint32_t rx_port;
     uint32_t rx_af;
-    uint16_t rx_pin; 
+    uint16_t rx_pin;
 
     struct rt_serial_device * serial;
     char *device_name;
@@ -93,7 +93,7 @@ static const struct gd32_uart uarts[] = {
         "uart0",
     },
     #endif
-    
+
     #ifdef RT_USING_USART1
     {
         USART1,                                 // uart peripheral index
@@ -122,18 +122,18 @@ void gd32_uart_gpio_init(struct gd32_uart *uart)
     /* enable USART clock */
     rcu_periph_clock_enable(uart->tx_gpio_clk);
     rcu_periph_clock_enable(uart->rx_gpio_clk);
-    rcu_periph_clock_enable(uart->per_clk);    
+    rcu_periph_clock_enable(uart->per_clk);
 
     /* connect port to USARTx_Tx */
     gpio_af_set(uart->tx_port, uart->tx_af, uart->tx_pin);
     gpio_mode_set(uart->tx_port, GPIO_MODE_AF, GPIO_PUPD_NONE, uart->tx_pin);
     gpio_output_options_set(uart->tx_port, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, uart->tx_pin);
-	
+
     /* connect port to USARTx_Rx */
     gpio_af_set(uart->rx_port, uart->rx_af, uart->rx_pin);
     gpio_mode_set(uart->rx_port, GPIO_MODE_AF, GPIO_PUPD_NONE, uart->rx_pin);
     gpio_output_options_set(uart->rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, uart->rx_pin);
-	
+
     NVIC_SetPriority(uart->irqn, 0);
     NVIC_EnableIRQ(uart->irqn);
 }
@@ -146,9 +146,9 @@ static rt_err_t gd32_configure(struct rt_serial_device *serial, struct serial_co
     RT_ASSERT(cfg != RT_NULL);
 
     uart = (struct gd32_uart *)serial->parent.user_data;
-    
+
     gd32_uart_gpio_init(uart);
-    
+
     usart_baudrate_set(uart->uart_periph, cfg->baud_rate);
 
     switch (cfg->data_bits)
@@ -228,7 +228,7 @@ static int gd32_putc(struct rt_serial_device *serial, char ch)
 
     usart_data_transmit(uart->uart_periph, ch);
     while((usart_flag_get(uart->uart_periph, USART_FLAG_TC) == RESET));
-    
+
     return 1;
 }
 
diff --git a/bsp/gd32e230k-start/drivers/drv_usart.h b/bsp/gd32e230k-start/drivers/drv_usart.h
index 0fb15bee6f..4059092706 100644
--- a/bsp/gd32e230k-start/drivers/drv_usart.h
+++ b/bsp/gd32e230k-start/drivers/drv_usart.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/gd32e230k-start/drivers/gd32e230_libopt.h b/bsp/gd32e230k-start/drivers/gd32e230_libopt.h
index 61010d794f..767e929d8f 100644
--- a/bsp/gd32e230k-start/drivers/gd32e230_libopt.h
+++ b/bsp/gd32e230k-start/drivers/gd32e230_libopt.h
@@ -1,7 +1,7 @@
 /*!
     \file    gd32e230_libopt.h
     \brief   library optional for gd32e230
-    
+
     \version 2018-06-19, V1.0.0, firmware for GD32E230
 */
 
@@ -10,27 +10,27 @@
 
     All rights reserved.
 
-    Redistribution and use in source and binary forms, with or without modification, 
+    Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
 
-    1. Redistributions of source code must retain the above copyright notice, this 
+    1. Redistributions of source code must retain the above copyright notice, this
        list of conditions and the following disclaimer.
-    2. Redistributions in binary form must reproduce the above copyright notice, 
-       this list of conditions and the following disclaimer in the documentation 
+    2. Redistributions in binary form must reproduce the above copyright notice,
+       this list of conditions and the following disclaimer in the documentation
        and/or other materials provided with the distribution.
-    3. Neither the name of the copyright holder nor the names of its contributors 
-       may be used to endorse or promote products derived from this software without 
+    3. Neither the name of the copyright holder nor the names of its contributors
+       may be used to endorse or promote products derived from this software without
        specific prior written permission.
 
-    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
-INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
-NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
 OF SUCH DAMAGE.
 */
 
diff --git a/bsp/gd32vf103v-eval/applications/main.c b/bsp/gd32vf103v-eval/applications/main.c
index c411937c18..9d7d2edafe 100644
--- a/bsp/gd32vf103v-eval/applications/main.c
+++ b/bsp/gd32vf103v-eval/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/gd32vf103v-eval/board/board.c b/bsp/gd32vf103v-eval/board/board.c
index de2907c79b..5df6fa722f 100644
--- a/bsp/gd32vf103v-eval/board/board.c
+++ b/bsp/gd32vf103v-eval/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/gd32vf103v-eval/board/board.h b/bsp/gd32vf103v-eval/board/board.h
index 422634fc38..860d71698b 100644
--- a/bsp/gd32vf103v-eval/board/board.h
+++ b/bsp/gd32vf103v-eval/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/gd32vf103v-eval/board/gd32vf103_libopt.h b/bsp/gd32vf103v-eval/board/gd32vf103_libopt.h
index ca292d2659..58ef886900 100644
--- a/bsp/gd32vf103v-eval/board/gd32vf103_libopt.h
+++ b/bsp/gd32vf103v-eval/board/gd32vf103_libopt.h
@@ -8,27 +8,27 @@
 /*
  Copyright (c) 2019, GigaDevice Semiconductor Inc.
 
- Redistribution and use in source and binary forms, with or without modification, 
+ Redistribution and use in source and binary forms, with or without modification,
  are permitted provided that the following conditions are met:
 
- 1. Redistributions of source code must retain the above copyright notice, this 
+ 1. Redistributions of source code must retain the above copyright notice, this
  list of conditions and the following disclaimer.
- 2. Redistributions in binary form must reproduce the above copyright notice, 
- this list of conditions and the following disclaimer in the documentation 
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
  and/or other materials provided with the distribution.
- 3. Neither the name of the copyright holder nor the names of its contributors 
- may be used to endorse or promote products derived from this software without 
+ 3. Neither the name of the copyright holder nor the names of its contributors
+ may be used to endorse or promote products derived from this software without
  specific prior written permission.
 
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
- IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
- NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
  OF SUCH DAMAGE.
  */
 
diff --git a/bsp/gd32vf103v-eval/drivers/drv_gpio.c b/bsp/gd32vf103v-eval/drivers/drv_gpio.c
index 95393cd4f2..ca56bf54a2 100644
--- a/bsp/gd32vf103v-eval/drivers/drv_gpio.c
+++ b/bsp/gd32vf103v-eval/drivers/drv_gpio.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,7 +15,7 @@
 
 #define EXTI_(x)  BIT(x)
 
-static const struct pin_index pins[] = 
+static const struct pin_index pins[] =
 {
 #if defined(GPIOA)
     __GD32VF_PIN(0 ,  A, 0 ),
@@ -126,7 +126,7 @@ static const struct pin_irq_map pin_irq_map[] =
     {GPIO_PIN_12, EXTI10_15_IRQn},
     {GPIO_PIN_13, EXTI10_15_IRQn},
     {GPIO_PIN_14, EXTI10_15_IRQn},
-    {GPIO_PIN_15, EXTI10_15_IRQn}, 
+    {GPIO_PIN_15, EXTI10_15_IRQn},
 };
 
 static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
@@ -406,11 +406,11 @@ static rt_err_t gd32vf_pin_irq_enable(struct rt_device *device, rt_base_t pin,
         gpio_bit_reset(index->gpio_periph, index->pin);
 
         pin_irq_enable_mask &= ~irqmap->pinbit;
- 
+
         eclic_irq_disable(irqmap->irqno);
         exti_interrupt_flag_clear(EXTI_(index->pin));
-         
-        rt_hw_interrupt_enable(level);  
+
+        rt_hw_interrupt_enable(level);
     }
     else
     {
diff --git a/bsp/gd32vf103v-eval/drivers/drv_gpio.h b/bsp/gd32vf103v-eval/drivers/drv_gpio.h
index ccb8ea92a3..af1094e97d 100644
--- a/bsp/gd32vf103v-eval/drivers/drv_gpio.h
+++ b/bsp/gd32vf103v-eval/drivers/drv_gpio.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -38,4 +38,4 @@ int rt_hw_gpio_init(void);
 
 #endif /* __DRV_GPIO__H__ */
 
-/******************* end of file *******************/
\ No newline at end of file
+/******************* end of file *******************/
diff --git a/bsp/gd32vf103v-eval/drivers/drv_usart.c b/bsp/gd32vf103v-eval/drivers/drv_usart.c
index 9a15eca933..313440329c 100644
--- a/bsp/gd32vf103v-eval/drivers/drv_usart.c
+++ b/bsp/gd32vf103v-eval/drivers/drv_usart.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,7 +15,7 @@
 #if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) \
     && !defined(BSP_USING_UART3) && !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5)
     #error "Please define at least one BSP_USING_UARTx"
-    /* this driver can be disabled at menuconfig  RT-Thread Components  Device Drivers */
+    /* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */
 #endif
 
 struct gd32_usart {
diff --git a/bsp/gkipc/applications/main.c b/bsp/gkipc/applications/main.c
index 0d9fd0ebcf..971e404459 100644
--- a/bsp/gkipc/applications/main.c
+++ b/bsp/gkipc/applications/main.c
@@ -1,21 +1,7 @@
 /*
- * File      : main.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/gkipc/armv6/context_gcc.s b/bsp/gkipc/armv6/context_gcc.s
index 2980654f3f..69813d521b 100644
--- a/bsp/gkipc/armv6/context_gcc.s
+++ b/bsp/gkipc/armv6/context_gcc.s
@@ -1,50 +1,36 @@
 /*
- * File      : context.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2011-01-13     weety    copy from mini2440
  */
 
-#define NOINT			0xc0
+#define NOINT           0xc0
 
 .globl __delay
 __delay:
-		subs	r0, r0, #1
+        subs    r0, r0, #1
 #if 1
-		movls	pc, lr
-		subs	r0, r0, #1
-		movls	pc, lr
-		subs	r0, r0, #1
-		movls	pc, lr
-		subs	r0, r0, #1
-		movls	pc, lr
-		subs	r0, r0, #1
-		movls	pc, lr
-		subs	r0, r0, #1
-		movls	pc, lr
-		subs	r0, r0, #1
-		movls	pc, lr
-		subs	r0, r0, #1
+        movls   pc, lr
+        subs    r0, r0, #1
+        movls   pc, lr
+        subs    r0, r0, #1
+        movls   pc, lr
+        subs    r0, r0, #1
+        movls   pc, lr
+        subs    r0, r0, #1
+        movls   pc, lr
+        subs    r0, r0, #1
+        movls   pc, lr
+        subs    r0, r0, #1
+        movls   pc, lr
+        subs    r0, r0, #1
 #endif
-		bhi	__delay
-		mov	pc, lr
+        bhi __delay
+        mov pc, lr
 
 
 /*
@@ -52,52 +38,52 @@ __delay:
  */
 .globl rt_hw_interrupt_disable
 rt_hw_interrupt_disable:
-	mrs r0, cpsr
-	orr r1, r0, #NOINT
-	msr cpsr_c, r1
-	mov pc, lr
+    mrs r0, cpsr
+    orr r1, r0, #NOINT
+    msr cpsr_c, r1
+    mov pc, lr
 
 /*
  * void rt_hw_interrupt_enable(rt_base_t level);
  */
 .globl rt_hw_interrupt_enable
 rt_hw_interrupt_enable:
-	msr cpsr, r0
-	mov pc, lr
+    msr cpsr, r0
+    mov pc, lr
 
 
     .globl  restore_context
     @.func   restore_context
-    
+
     .globl  save_context
     @.func   save_context
 
 save_context:
-    stmfd	sp!, {lr}		@ push pc (lr should be pushed in place of PC)
-	stmfd	sp!, {r0-r12, lr}	@ push lr & register file
+    stmfd   sp!, {lr}       @ push pc (lr should be pushed in place of PC)
+    stmfd   sp!, {r0-r12, lr}   @ push lr & register file
 
-	mrs	r4, cpsr
-	stmfd	sp!, {r4}		@ push cpsr
-	mrs	r4, spsr
-	stmfd	sp!, {r4}		@ push spsr
+    mrs r4, cpsr
+    stmfd   sp!, {r4}       @ push cpsr
+    mrs r4, spsr
+    stmfd   sp!, {r4}       @ push spsr
 
-	str	sp, [r0]			@ store sp in preempted tasks TCB
-	mov pc, lr
+    str sp, [r0]            @ store sp in preempted tasks TCB
+    mov pc, lr
     bx lr                 @ branch back to caller
 
 
 restore_context:
-    ldr	sp, [r0]			@ get new task stack pointer
+    ldr sp, [r0]            @ get new task stack pointer
+
+    ldmfd   sp!, {r4}       @ pop new task spsr
+    msr spsr_cxsf, r4
+    ldmfd   sp!, {r4}       @ pop new task cpsr
+    msr spsr_cxsf, r4
+
+    ldmfd   sp!, {r0-r12, lr, pc}^  @ pop new task r0-r12, lr & pc
 
-	ldmfd	sp!, {r4}		@ pop new task spsr
-	msr	spsr_cxsf, r4
-	ldmfd	sp!, {r4}		@ pop new task cpsr
-	msr	spsr_cxsf, r4
 
-	ldmfd	sp!, {r0-r12, lr, pc}^	@ pop new task r0-r12, lr & pc
 
-    
-    
 /*
  * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
  * r0 --> from
@@ -105,23 +91,23 @@ restore_context:
  */
 .globl rt_hw_context_switch
 rt_hw_context_switch:
-	stmfd	sp!, {lr}		@ push pc (lr should be pushed in place of PC)
-	stmfd	sp!, {r0-r12, lr}	@ push lr & register file
+    stmfd   sp!, {lr}       @ push pc (lr should be pushed in place of PC)
+    stmfd   sp!, {r0-r12, lr}   @ push lr & register file
 
-	mrs	r4, cpsr
-	stmfd	sp!, {r4}		@ push cpsr
-	mrs	r4, spsr
-	stmfd	sp!, {r4}		@ push spsr
+    mrs r4, cpsr
+    stmfd   sp!, {r4}       @ push cpsr
+    mrs r4, spsr
+    stmfd   sp!, {r4}       @ push spsr
 
-	str	sp, [r0]			@ store sp in preempted tasks TCB
-	ldr	sp, [r1]			@ get new task stack pointer
+    str sp, [r0]            @ store sp in preempted tasks TCB
+    ldr sp, [r1]            @ get new task stack pointer
 
-	ldmfd	sp!, {r4}		@ pop new task spsr
-	msr	spsr_cxsf, r4
-	ldmfd	sp!, {r4}		@ pop new task cpsr
-	msr	spsr_cxsf, r4
+    ldmfd   sp!, {r4}       @ pop new task spsr
+    msr spsr_cxsf, r4
+    ldmfd   sp!, {r4}       @ pop new task cpsr
+    msr spsr_cxsf, r4
 
-	ldmfd	sp!, {r0-r12, lr, pc}^	@ pop new task r0-r12, lr & pc
+    ldmfd   sp!, {r0-r12, lr, pc}^  @ pop new task r0-r12, lr & pc
 
 /*
  * void rt_hw_context_switch_to(rt_uint32 to);
@@ -129,14 +115,14 @@ rt_hw_context_switch:
  */
 .globl rt_hw_context_switch_to
 rt_hw_context_switch_to:
-	ldr	sp, [r0]		@ get new task stack pointer
+    ldr sp, [r0]        @ get new task stack pointer
 
-	ldmfd	sp!, {r4}		@ pop new task spsr
-	msr	spsr_cxsf, r4
-	ldmfd	sp!, {r4}		@ pop new task cpsr
-	msr	cpsr_cxsf, r4
+    ldmfd   sp!, {r4}       @ pop new task spsr
+    msr spsr_cxsf, r4
+    ldmfd   sp!, {r4}       @ pop new task cpsr
+    msr cpsr_cxsf, r4
 
-	ldmfd	sp!, {r0-r12, lr, pc}	@ pop new task r0-r12, lr & pc
+    ldmfd   sp!, {r0-r12, lr, pc}   @ pop new task r0-r12, lr & pc
 
 /*
  * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
@@ -146,15 +132,15 @@ rt_hw_context_switch_to:
 .globl rt_interrupt_to_thread
 .globl rt_hw_context_switch_interrupt
 rt_hw_context_switch_interrupt:
-	ldr r2, =rt_thread_switch_interrupt_flag
-	ldr r3, [r2]
-	cmp r3, #1
-	beq _reswitch
-	mov r3, #1				@ set rt_thread_switch_interrupt_flag to 1
-	str r3, [r2]
-	ldr r2, =rt_interrupt_from_thread	@ set rt_interrupt_from_thread
-	str r0, [r2]
+    ldr r2, =rt_thread_switch_interrupt_flag
+    ldr r3, [r2]
+    cmp r3, #1
+    beq _reswitch
+    mov r3, #1              @ set rt_thread_switch_interrupt_flag to 1
+    str r3, [r2]
+    ldr r2, =rt_interrupt_from_thread   @ set rt_interrupt_from_thread
+    str r0, [r2]
 _reswitch:
-	ldr r2, =rt_interrupt_to_thread		@ set rt_interrupt_to_thread
-	str r1, [r2]
-	mov pc, lr
+    ldr r2, =rt_interrupt_to_thread     @ set rt_interrupt_to_thread
+    str r1, [r2]
+    mov pc, lr
diff --git a/bsp/gkipc/armv6/cpuport.c b/bsp/gkipc/armv6/cpuport.c
index 08e7f9315b..21235e825b 100644
--- a/bsp/gkipc/armv6/cpuport.c
+++ b/bsp/gkipc/armv6/cpuport.c
@@ -1,21 +1,7 @@
 /*
- * File      : cpu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/gkipc/armv6/gk7101.h b/bsp/gkipc/armv6/gk7101.h
index 8614dab4da..bcf7f110f1 100644
--- a/bsp/gkipc/armv6/gk7101.h
+++ b/bsp/gkipc/armv6/gk7101.h
@@ -1,21 +1,7 @@
 /*
- * File      : at91sam926x.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -36,35 +22,35 @@ extern "C" {
 /*****************************/
 /* CPU Mode                  */
 /*****************************/
-#define USERMODE		0x10
-#define FIQMODE			0x11
-#define IRQMODE			0x12
-#define SVCMODE			0x13
-#define ABORTMODE		0x17
-#define UNDEFMODE		0x1b
-#define MODEMASK		0x1f
-#define NOINT			0xc0
+#define USERMODE        0x10
+#define FIQMODE         0x11
+#define IRQMODE         0x12
+#define SVCMODE         0x13
+#define ABORTMODE       0x17
+#define UNDEFMODE       0x1b
+#define MODEMASK        0x1f
+#define NOINT           0xc0
 
 struct rt_hw_register
 {
-	rt_uint32_t r0;
-	rt_uint32_t r1;
-	rt_uint32_t r2;
-	rt_uint32_t r3;
-	rt_uint32_t r4;
-	rt_uint32_t r5;
-	rt_uint32_t r6;
-	rt_uint32_t r7;
-	rt_uint32_t r8;
-	rt_uint32_t r9;
-	rt_uint32_t r10;
-	rt_uint32_t fp;
-	rt_uint32_t ip;
-	rt_uint32_t sp;
-	rt_uint32_t lr;
-	rt_uint32_t pc;
-	rt_uint32_t cpsr;
-	rt_uint32_t ORIG_r0;
+    rt_uint32_t r0;
+    rt_uint32_t r1;
+    rt_uint32_t r2;
+    rt_uint32_t r3;
+    rt_uint32_t r4;
+    rt_uint32_t r5;
+    rt_uint32_t r6;
+    rt_uint32_t r7;
+    rt_uint32_t r8;
+    rt_uint32_t r9;
+    rt_uint32_t r10;
+    rt_uint32_t fp;
+    rt_uint32_t ip;
+    rt_uint32_t sp;
+    rt_uint32_t lr;
+    rt_uint32_t pc;
+    rt_uint32_t cpsr;
+    rt_uint32_t ORIG_r0;
 };
 
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
diff --git a/bsp/gkipc/armv6/interrupt.c b/bsp/gkipc/armv6/interrupt.c
index 0eb03c9b2c..f276f3ee3c 100644
--- a/bsp/gkipc/armv6/interrupt.c
+++ b/bsp/gkipc/armv6/interrupt.c
@@ -1,21 +1,7 @@
 /*
- * File      : interrupt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/gkipc/armv6/mmu.c b/bsp/gkipc/armv6/mmu.c
index 9f331c7147..0085113f3d 100644
--- a/bsp/gkipc/armv6/mmu.c
+++ b/bsp/gkipc/armv6/mmu.c
@@ -1,21 +1,7 @@
 /*
- * File      : mmu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -27,22 +13,22 @@
 #ifdef __CC_ARM
 void mmu_setttbase(rt_uint32_t i)
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
    /* Invalidates all TLBs.Domain access is selected as
     * client by configuring domain access register,
     * in that case access controlled by permission value
     * set by page table entry
     */
-	value = 0;
+    value = 0;
     __asm
     {
         mcr p15, 0, value, c8, c7, 0
-	}
+    }
 
-	value = 0x55555555;
-	__asm
-	{
+    value = 0x55555555;
+    __asm
+    {
         mcr p15, 0, value, c3, c0, 0
         mcr p15, 0, i, c2, c0, 0
     }
@@ -168,44 +154,44 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
     while(ptr < buffer + size)
     {
-    	__asm
-    	{
-    		MCR p15, 0, ptr, c7, c14, 1
-    	}
+        __asm
+        {
+            MCR p15, 0, ptr, c7, c14, 1
+        }
         ptr += CACHE_LINE_SIZE;
     }
 }
 
 void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
 {
-	unsigned int ptr;
+    unsigned int ptr;
 
-	ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+    ptr = buffer & ~(CACHE_LINE_SIZE - 1);
 
-	while (ptr < buffer + size)
-	{
-		__asm
-		{
-			MCR p15, 0, ptr, c7, c10, 1
-		}
-		ptr += CACHE_LINE_SIZE;
-	}
+    while (ptr < buffer + size)
+    {
+        __asm
+        {
+            MCR p15, 0, ptr, c7, c10, 1
+        }
+        ptr += CACHE_LINE_SIZE;
+    }
 }
 
 void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
 {
-	unsigned int ptr;
+    unsigned int ptr;
 
-	ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+    ptr = buffer & ~(CACHE_LINE_SIZE - 1);
 
-	while (ptr < buffer + size)
-	{
-		__asm
-		{
-			MCR p15, 0, ptr, c7, c6, 1
-		}
-		ptr += CACHE_LINE_SIZE;
-	}
+    while (ptr < buffer + size)
+    {
+        __asm
+        {
+            MCR p15, 0, ptr, c7, c6, 1
+        }
+        ptr += CACHE_LINE_SIZE;
+    }
 }
 
 void mmu_invalidate_tlb()
@@ -246,7 +232,7 @@ void mmu_invalidate_dcache_all()
 #elif defined(__GNUC__)
 void mmu_setttbase(register rt_uint32_t i)
 {
-	//register rt_uint32_t value;
+    //register rt_uint32_t value;
 
    /* Invalidates all TLBs.Domain access is selected as
     * client by configuring domain access register,
@@ -254,18 +240,18 @@ void mmu_setttbase(register rt_uint32_t i)
     * set by page table entry
     */
 #if 0
-	value = 0;
-	asm ("mcr p15, 0, %0, c8,c7, 0"::"r"(value));
+    value = 0;
+    asm ("mcr p15, 0, %0, c8,c7, 0"::"r"(value));
 
-	value = 0x55555555;
-	asm ("mcr p15, 0, %0, c3,c0, 0"::"r"(value));
-	asm ("mcr p15, 0, %0, c2,c0, 0"::"r"(i));
+    value = 0x55555555;
+    asm ("mcr p15, 0, %0, c3,c0, 0"::"r"(value));
+    asm ("mcr p15, 0, %0, c2,c0, 0"::"r"(i));
 #endif
 
-	asm (
-    	"mrc p15,0,r0,c1,c0,0 \r\n"
+    asm (
+        "mrc p15,0,r0,c1,c0,0 \r\n"
         "mov r1,#0x800000  \r\n"
-        "orr r0,r0,r1	 @ disable Subpage AP bits  \r\n"
+        "orr r0,r0,r1    @ disable Subpage AP bits  \r\n"
         "mcr p15,0,r0,c1,c0,0 @ write value back  \r\n"
         "mov r0,#0x0  \r\n"
         "mcr p15,0,r0,c2,c0,2 @ W  \r\n"
@@ -275,116 +261,116 @@ void mmu_setttbase(register rt_uint32_t i)
 
 void mmu_set_domain(register rt_uint32_t i)
 {
-	asm ("mcr p15,0, %0, c3, c0,  0": :"r" (i));
+    asm ("mcr p15,0, %0, c3, c0,  0": :"r" (i));
 }
 
 void mmu_enable()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i |= 0x1;
+    i |= 0x1;
 
-	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i &= ~0x1;
+    i &= ~0x1;
 
-	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_enable_icache()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i |= (1 << 12);
+    i |= (1 << 12);
 
-	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_enable_dcache()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i |= (1 << 2);
+    i |= (1 << 2);
 
-	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable_icache()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i &= ~(1 << 12);
+    i &= ~(1 << 12);
 
-	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable_dcache()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i &= ~(1 << 2);
+    i &= ~(1 << 2);
 
-	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_enable_alignfault()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i |= (1 << 1);
+    i |= (1 << 1);
 
-	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable_alignfault()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i &= ~(1 << 1);
+    i &= ~(1 << 1);
 
-	/* write back to control register */
-	asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_clean_invalidated_cache_index(int index)
 {
-	asm ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
+    asm ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
 }
 
 void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
@@ -395,7 +381,7 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
     while(ptr < buffer + size)
     {
-    	asm ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr));
+        asm ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr));
         ptr += CACHE_LINE_SIZE;
     }
 }
@@ -403,38 +389,38 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
 void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
 {
-	unsigned int ptr;
+    unsigned int ptr;
 
-	ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+    ptr = buffer & ~(CACHE_LINE_SIZE - 1);
 
-	while (ptr < buffer + size)
-	{
-		asm ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
-		ptr += CACHE_LINE_SIZE;
-	}
+    while (ptr < buffer + size)
+    {
+        asm ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
+        ptr += CACHE_LINE_SIZE;
+    }
 }
 
 void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
 {
-	unsigned int ptr;
+    unsigned int ptr;
 
-	ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+    ptr = buffer & ~(CACHE_LINE_SIZE - 1);
 
-	while (ptr < buffer + size)
-	{
-		asm ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
-		ptr += CACHE_LINE_SIZE;
-	}
+    while (ptr < buffer + size)
+    {
+        asm ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
+        ptr += CACHE_LINE_SIZE;
+    }
 }
 
 void mmu_invalidate_tlb()
 {
-	asm ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
+    asm ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
 }
 
 void mmu_invalidate_icache()
 {
-	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
+    asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
 }
 
 void mmu_invalidate_dcache_all()
@@ -458,8 +444,8 @@ void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd, rt_uint32_t paddrS
     nSec=(vaddrEnd>>20)-(vaddrStart>>20);
     for(i=0;i<=nSec;i++)
     {
-		*pTT = attr |(((paddrStart>>20)+i)<<20);
-		pTT++;
+        *pTT = attr |(((paddrStart>>20)+i)<<20);
+        pTT++;
     }
 }
 
@@ -528,22 +514,22 @@ void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb)
 
 void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size)
 {
-	/* disable I/D cache */
-	mmu_disable_dcache();
-	mmu_disable_icache();
-	mmu_disable();
-	mmu_invalidate_tlb();
+    /* disable I/D cache */
+    mmu_disable_dcache();
+    mmu_disable_icache();
+    mmu_disable();
+    mmu_invalidate_tlb();
 
-	/* set page table */
-	for (; size > 0; size--)
-	{
-		mmu_setmtt(mdesc->vaddr_start, mdesc->vaddr_end,
-			mdesc->paddr_start, mdesc->attr);
-		mdesc++;
-	}
+    /* set page table */
+    for (; size > 0; size--)
+    {
+        mmu_setmtt(mdesc->vaddr_start, mdesc->vaddr_end,
+            mdesc->paddr_start, mdesc->attr);
+        mdesc++;
+    }
 
-	/* set MMU table address */
-	mmu_setttbase((rt_uint32_t)_page_table);
+    /* set MMU table address */
+    mmu_setttbase((rt_uint32_t)_page_table);
 
     /* enables MMU */
     mmu_enable();
diff --git a/bsp/gkipc/armv6/mmu.h b/bsp/gkipc/armv6/mmu.h
index 2ca3d03817..7476dc42ab 100644
--- a/bsp/gkipc/armv6/mmu.h
+++ b/bsp/gkipc/armv6/mmu.h
@@ -1,21 +1,7 @@
 /*
- * File      : mmu.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -26,29 +12,29 @@
 
 #include 
 
-#define CACHE_LINE_SIZE	32
+#define CACHE_LINE_SIZE 32
 
-#define DESC_SEC		(0x2|(1<<4))
-#define CB				(3<<2)  //cache_on, write_back
-#define CNB				(2<<2)  //cache_on, write_through
-#define NCB				(1<<2)  //cache_off,WR_BUF on
-#define NCNB			(0<<2)  //cache_off,WR_BUF off
-#define AP_RW			(3<<10) //supervisor=RW, user=RW
-#define AP_RO			(2<<10) //supervisor=RW, user=RO
+#define DESC_SEC        (0x2|(1<<4))
+#define CB              (3<<2)  //cache_on, write_back
+#define CNB             (2<<2)  //cache_on, write_through
+#define NCB             (1<<2)  //cache_off,WR_BUF on
+#define NCNB            (0<<2)  //cache_off,WR_BUF off
+#define AP_RW           (3<<10) //supervisor=RW, user=RW
+#define AP_RO           (2<<10) //supervisor=RW, user=RO
 
-#define DOMAIN_FAULT	(0x0)
-#define DOMAIN_CHK		(0x1)
-#define DOMAIN_NOTCHK	(0x3)
-#define DOMAIN0			(0x0<<5)
-#define DOMAIN1			(0x1<<5)
+#define DOMAIN_FAULT    (0x0)
+#define DOMAIN_CHK      (0x1)
+#define DOMAIN_NOTCHK   (0x3)
+#define DOMAIN0         (0x0<<5)
+#define DOMAIN1         (0x1<<5)
 
-#define DOMAIN0_ATTR	(DOMAIN_CHK<<0)
-#define DOMAIN1_ATTR	(DOMAIN_FAULT<<2)
+#define DOMAIN0_ATTR    (DOMAIN_CHK<<0)
+#define DOMAIN1_ATTR    (DOMAIN_FAULT<<2)
 
-#define RW_CB		(AP_RW|DOMAIN0|CB|DESC_SEC)		/* Read/Write, cache, write back */
-#define RW_CNB		(AP_RW|DOMAIN0|CNB|DESC_SEC)	/* Read/Write, cache, write through */
-#define RW_NCNB		(AP_RW|DOMAIN0|NCNB|DESC_SEC)	/* Read/Write without cache and write buffer */
-#define RW_FAULT	(AP_RW|DOMAIN1|NCNB|DESC_SEC)	/* Read/Write without cache and write buffer */
+#define RW_CB       (AP_RW|DOMAIN0|CB|DESC_SEC)     /* Read/Write, cache, write back */
+#define RW_CNB      (AP_RW|DOMAIN0|CNB|DESC_SEC)    /* Read/Write, cache, write through */
+#define RW_NCNB     (AP_RW|DOMAIN0|NCNB|DESC_SEC)   /* Read/Write without cache and write buffer */
+#define RW_FAULT    (AP_RW|DOMAIN1|NCNB|DESC_SEC)   /* Read/Write without cache and write buffer */
 
 #define ARM1176_1MB_NOCACHE_BUFFER      0x00000DE6  // non-cachable/bufferable
 #define ARM1176_1MB_CACHE_NOBUFFER      0x00000DEA  // cachable/non-bufferable
@@ -60,10 +46,10 @@
 
 
 struct mem_desc {
-	rt_uint32_t vaddr_start;
-	rt_uint32_t vaddr_end;
-	rt_uint32_t paddr_start;
-	rt_uint32_t attr;
+    rt_uint32_t vaddr_start;
+    rt_uint32_t vaddr_end;
+    rt_uint32_t paddr_start;
+    rt_uint32_t attr;
 };
 
 void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size);
diff --git a/bsp/gkipc/armv6/reset.c b/bsp/gkipc/armv6/reset.c
index b7bc58f664..a2adc17499 100644
--- a/bsp/gkipc/armv6/reset.c
+++ b/bsp/gkipc/armv6/reset.c
@@ -1,21 +1,7 @@
 /*
- * File      : reset.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/gkipc/armv6/stack.c b/bsp/gkipc/armv6/stack.c
index 8167923856..bfaf18ba70 100644
--- a/bsp/gkipc/armv6/stack.c
+++ b/bsp/gkipc/armv6/stack.c
@@ -1,21 +1,7 @@
 /*
- * File      : stack.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -25,29 +11,29 @@
 /*****************************/
 /* CPU Mode                  */
 /*****************************/
-#define USERMODE		0x10
-#define FIQMODE			0x11
-#define IRQMODE			0x12
-#define SVCMODE			0x13
-#define ABORTMODE		0x17
-#define UNDEFMODE		0x1b
-#define MODEMASK		0x1f
-#define NOINT			0xc0
+#define USERMODE        0x10
+#define FIQMODE         0x11
+#define IRQMODE         0x12
+#define SVCMODE         0x13
+#define ABORTMODE       0x17
+#define UNDEFMODE       0x1b
+#define MODEMASK        0x1f
+#define NOINT           0xc0
 
 /**
  * This function will initialize thread stack
  *
  * @param tentry the entry of thread
- * @param parameter the parameter of entry 
+ * @param parameter the parameter of entry
  * @param stack_addr the beginning stack address
  * @param texit the function will be called when thread exit
  *
  * @return stack address
  */
 rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
-	rt_uint8_t *stack_addr, void *texit)
+    rt_uint8_t *stack_addr, void *texit)
 {
-	rt_uint32_t *stk;
+    rt_uint32_t *stk;
 
     stack_addr += sizeof(rt_uint32_t);
     stack_addr  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
@@ -68,10 +54,10 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
     *(--stk) = 0xdeadbeef;                  /* r2 */
     *(--stk) = 0xdeadbeef;                  /* r1 */
     *(--stk) = (rt_uint32_t)parameter;      /* r0 : argument */
-	*(--stk) = SVCMODE;						/* cpsr */
-	*(--stk) = SVCMODE;						/* spsr */
+    *(--stk) = SVCMODE;                     /* cpsr */
+    *(--stk) = SVCMODE;                     /* spsr */
 
-	/* return task's current stack address */
-	return (rt_uint8_t *)stk;
+    /* return task's current stack address */
+    return (rt_uint8_t *)stk;
 }
 
diff --git a/bsp/gkipc/armv6/start_gcc.s b/bsp/gkipc/armv6/start_gcc.s
index 6f9da355e3..684ff81eab 100644
--- a/bsp/gkipc/armv6/start_gcc.s
+++ b/bsp/gkipc/armv6/start_gcc.s
@@ -1,21 +1,7 @@
 /*
- * File      : start.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date                 Author          Notes
@@ -183,7 +169,7 @@ reset:
     mrc p15, 0, r1, c0, c0, 1     @/* Read cache type {0x1d152152}*/
     mrc p15, 0, r2, c0, c0, 2     @/* Read TCM status {0x10001}*/
 
-#ifdef GK7102C    
+#ifdef GK7102C
     @mrc    p15, 0, r0, c15,c14,0  @ read CP15 register c15 into r0
     @orr    r0,  r0,#0x80000000    @ system bit enabled
     @bic    r0,  r0,#0x00000077    @
@@ -194,7 +180,7 @@ reset:
     orr     r0,  r0,#0x00000040    @CZ bit enabled
     mcr     p15, 0, r0, c1, c0, 1  @read CP15 register c1 into r0
 #endif
-    
+
     @/* Turn on instrucion cache and disable MMU */
     mrc p15, 0, r0, c1, c0, 0     @/* Read control register {0x5327d}*/
     @bic r0, r0, #0x1000          @ Turn off bit 12 - I-cache
diff --git a/bsp/gkipc/armv6/system_clock.c b/bsp/gkipc/armv6/system_clock.c
index 17c072fdfe..ad11201c93 100644
--- a/bsp/gkipc/armv6/system_clock.c
+++ b/bsp/gkipc/armv6/system_clock.c
@@ -1,21 +1,7 @@
 /*
- * File      : clock.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/gkipc/armv6/trap.c b/bsp/gkipc/armv6/trap.c
index 602badff39..1c239f1d8c 100644
--- a/bsp/gkipc/armv6/trap.c
+++ b/bsp/gkipc/armv6/trap.c
@@ -1,21 +1,7 @@
 /*
- * File      : trap.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -112,16 +98,16 @@ int g_wifi_input = 0;
 int g_wifi_output = 0;
 void rt_hw_show_register (struct rt_hw_register *regs)
 {
-	rt_kprintf("Execption:\n");
-	rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
-	rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
-	rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
-	rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
-	rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
-	rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
-	rt_kprintf("eth info : in = %d out = %d\n", g_eth_input, g_eth_output);
-	rt_kprintf("wifi info: in = %d out = %d\n", g_wifi_input, g_wifi_output);
-	_rtt_statistics();
+    rt_kprintf("Execption:\n");
+    rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
+    rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
+    rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
+    rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
+    rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
+    rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
+    rt_kprintf("eth info : in = %d out = %d\n", g_eth_input, g_eth_output);
+    rt_kprintf("wifi info: in = %d out = %d\n", g_wifi_input, g_wifi_output);
+    _rtt_statistics();
 }
 
 /**
@@ -134,15 +120,15 @@ void rt_hw_show_register (struct rt_hw_register *regs)
  */
 void rt_hw_trap_udef(struct rt_hw_register *regs)
 {
-	rt_hw_show_register(regs);
+    rt_hw_show_register(regs);
 
-	rt_kprintf("undefined instruction\n");
-	rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
+    rt_kprintf("undefined instruction\n");
+    rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
 
 #ifdef RT_USING_FINSH
-	list_thread();
+    list_thread();
 #endif
-	rt_hw_cpu_shutdown();
+    rt_hw_cpu_shutdown();
 }
 
 /**
@@ -156,10 +142,10 @@ void rt_hw_trap_udef(struct rt_hw_register *regs)
  */
 void rt_hw_trap_swi(struct rt_hw_register *regs)
 {
-	rt_hw_show_register(regs);
+    rt_hw_show_register(regs);
 
-	rt_kprintf("software interrupt\n");
-	rt_hw_cpu_shutdown();
+    rt_kprintf("software interrupt\n");
+    rt_hw_cpu_shutdown();
 }
 
 /**
@@ -172,15 +158,15 @@ void rt_hw_trap_swi(struct rt_hw_register *regs)
  */
 void rt_hw_trap_pabt(struct rt_hw_register *regs)
 {
-	rt_hw_show_register(regs);
+    rt_hw_show_register(regs);
 
-	rt_kprintf("prefetch abort\n");
-	rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
+    rt_kprintf("prefetch abort\n");
+    rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
 
 #ifdef RT_USING_FINSH
-	list_thread();
+    list_thread();
 #endif
-	rt_hw_cpu_shutdown();
+    rt_hw_cpu_shutdown();
 }
 
 /**
@@ -194,16 +180,16 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs)
 void rt_hw_trap_dabt(struct rt_hw_register *regs)
 {
 
-	rt_kprintf(">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
-	rt_kprintf("data abort\n");
-	rt_kprintf("thread - [%s] stack:\n", rt_current_thread->name);
+    rt_kprintf(">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
+    rt_kprintf("data abort\n");
+    rt_kprintf("thread - [%s] stack:\n", rt_current_thread->name);
 
-	rt_hw_show_register(regs);
+    rt_hw_show_register(regs);
 
 #ifdef RT_USING_FINSH
-	list_thread();
+    list_thread();
 #endif
-	rt_hw_cpu_shutdown();
+    rt_hw_cpu_shutdown();
 }
 
 /**
@@ -215,9 +201,9 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs)
  */
 void rt_hw_trap_resv(struct rt_hw_register *regs)
 {
-	rt_kprintf("not used\n");
-	rt_hw_show_register(regs);
-	rt_hw_cpu_shutdown();
+    rt_kprintf("not used\n");
+    rt_hw_show_register(regs);
+    rt_hw_cpu_shutdown();
 }
 
 extern struct rt_irq_desc irq_desc[];
@@ -225,26 +211,26 @@ extern struct rt_irq_desc irq_desc[];
 void rt_hw_trap_irq()
 {
     int index;
-	//rt_kprintf("irq interrupt request\n");
+    //rt_kprintf("irq interrupt request\n");
     GD_IRQ_ISR();
 
-	if(gkosHookData)
-	{
-	    for( index=0; index < gkosHookData->timerFunctionCount; index++ )
-	    {
-	        if( gkosHookData->timerFunctionArray[index] )
-	        {
-	            (*gkosHookData->timerFunctionArray[index])(NULL);
-	        }
-	    }
-	}
+    if(gkosHookData)
+    {
+        for( index=0; index < gkosHookData->timerFunctionCount; index++ )
+        {
+            if( gkosHookData->timerFunctionArray[index] )
+            {
+                (*gkosHookData->timerFunctionArray[index])(NULL);
+            }
+        }
+    }
 }
 
 void rt_hw_trap_fiq()
 {
-	//rt_kprintf("fast interrupt request\n");
-	GD_FIQ_ISR();
-	//rt_tick_increase();
+    //rt_kprintf("fast interrupt request\n");
+    GD_FIQ_ISR();
+    //rt_tick_increase();
 }
 
 /*@}*/
diff --git a/bsp/gkipc/drivers/board.h b/bsp/gkipc/drivers/board.h
index 9e7659e77b..815a1f981d 100644
--- a/bsp/gkipc/drivers/board.h
+++ b/bsp/gkipc/drivers/board.h
@@ -1,21 +1,7 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/hc32f4a0/board/board.h b/bsp/hc32f4a0/board/board.h
index 927f7d78f2..a35747f13c 100644
--- a/bsp/hc32f4a0/board/board.h
+++ b/bsp/hc32f4a0/board/board.h
@@ -6,8 +6,8 @@
  * Change Logs:
  * Date           Author       Notes
  * 2020-10-30     CDT          first version
+ * 2021-01-18     CDT          MOdify SRAM_SIZE
  */
- 
 
 #ifndef __BOARD_H__
 #define __BOARD_H__
@@ -18,7 +18,7 @@
 
 /* board configuration */
 #define SRAM_BASE 0x1FFE0000
-#define SRAM_SIZE 0x20000
+#define SRAM_SIZE 0x80000
 #define SRAM_END (SRAM_BASE + SRAM_SIZE)
 
 /* High speed sram. */
diff --git a/bsp/hc32f4a0/drivers/drv_soft_i2c.c b/bsp/hc32f4a0/drivers/drv_soft_i2c.c
index 38258ba7ee..4ee69b8de2 100644
--- a/bsp/hc32f4a0/drivers/drv_soft_i2c.c
+++ b/bsp/hc32f4a0/drivers/drv_soft_i2c.c
@@ -6,9 +6,9 @@
  * Change Logs:
  * Date           Author       Notes
  * 2020-10-30     CDT          first version
+ * 2021-01-18     CDT          modify i2c gpio init
  */
 
-
 /*******************************************************************************
  * Include files
  ******************************************************************************/
@@ -65,10 +65,8 @@ static const struct hc32_soft_i2c_config soft_i2c_config[] =
 #endif
 };
 
-
 static struct hc32_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0])];
 
-
 /*******************************************************************************
  * Function implementation - global ('extern') and local ('static')
  ******************************************************************************/
@@ -81,8 +79,8 @@ static void hc32_i2c_gpio_init(struct hc32_i2c *i2c)
 {
     struct hc32_soft_i2c_config* cfg = (struct hc32_soft_i2c_config*)i2c->ops.data;
 
-    rt_pin_mode(cfg->scl_pin, PIN_MODE_OUTPUT);
-    rt_pin_mode(cfg->sda_pin, PIN_MODE_OUTPUT);
+    rt_pin_mode(cfg->scl_pin, PIN_MODE_OUTPUT_OD);
+    rt_pin_mode(cfg->sda_pin, PIN_MODE_OUTPUT_OD);
 
     rt_pin_write(cfg->scl_pin, PIN_HIGH);
     rt_pin_write(cfg->sda_pin, PIN_HIGH);
@@ -98,8 +96,6 @@ static void hc32_set_sda(void *data, rt_int32_t state)
 {
     struct hc32_soft_i2c_config* cfg = (struct hc32_soft_i2c_config*)data;
 
-    rt_pin_mode(cfg->sda_pin, PIN_MODE_OUTPUT);
-
     if (state)
         rt_pin_write(cfg->sda_pin, PIN_HIGH);
     else
@@ -116,8 +112,6 @@ static void hc32_set_scl(void *data, rt_int32_t state)
 {
     struct hc32_soft_i2c_config* cfg = (struct hc32_soft_i2c_config*)data;
 
-    rt_pin_mode(cfg->scl_pin, PIN_MODE_OUTPUT);
-
     if (state)
         rt_pin_write(cfg->scl_pin, PIN_HIGH);
     else
@@ -133,8 +127,6 @@ static rt_int32_t hc32_get_sda(void *data)
 {
     struct hc32_soft_i2c_config* cfg = (struct hc32_soft_i2c_config*)data;
 
-    rt_pin_mode(cfg->sda_pin, PIN_MODE_INPUT);
-
     return rt_pin_read(cfg->sda_pin);
 }
 
@@ -147,8 +139,6 @@ static rt_int32_t hc32_get_scl(void *data)
 {
     struct hc32_soft_i2c_config* cfg = (struct hc32_soft_i2c_config*)data;
 
-    rt_pin_mode(cfg->scl_pin, PIN_MODE_INPUT);
-
     return rt_pin_read(cfg->scl_pin);
 }
 
@@ -210,7 +200,6 @@ int hc32_hw_i2c_init(void)
 }
 INIT_BOARD_EXPORT(hc32_hw_i2c_init);
 
-
 #endif /* RT_USING_I2C */
 
 /*******************************************************************************
diff --git a/bsp/hifive1/applications/main.c b/bsp/hifive1/applications/main.c
index 9fdfde2334..e3cd69f303 100644
--- a/bsp/hifive1/applications/main.c
+++ b/bsp/hifive1/applications/main.c
@@ -1,21 +1,7 @@
 /*
- * File      : main.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -28,5 +14,5 @@
 
 int main(void)
 {
-	return 0;
+    return 0;
 }
diff --git a/bsp/hifive1/drivers/board.c b/bsp/hifive1/drivers/board.c
index 80a425309b..273901b93e 100644
--- a/bsp/hifive1/drivers/board.c
+++ b/bsp/hifive1/drivers/board.c
@@ -1,21 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/hifive1/drivers/board.h b/bsp/hifive1/drivers/board.h
index 698f316267..a708115374 100644
--- a/bsp/hifive1/drivers/board.h
+++ b/bsp/hifive1/drivers/board.h
@@ -1,21 +1,7 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/hifive1/drivers/drv_usart.c b/bsp/hifive1/drivers/drv_usart.c
index 6588892ae9..935d39105f 100644
--- a/bsp/hifive1/drivers/drv_usart.c
+++ b/bsp/hifive1/drivers/drv_usart.c
@@ -1,21 +1,7 @@
 /*
- * File      : drv_usart.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -37,7 +23,7 @@ static rt_err_t usart_configure(struct rt_serial_device *serial,
 {
     RT_ASSERT(serial != RT_NULL);
     RT_ASSERT(cfg != RT_NULL);
- 
+
     GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
     GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;
 
diff --git a/bsp/hifive1/drivers/interrupt.c b/bsp/hifive1/drivers/interrupt.c
index 506e80f451..75e8e8ac59 100644
--- a/bsp/hifive1/drivers/interrupt.c
+++ b/bsp/hifive1/drivers/interrupt.c
@@ -1,21 +1,7 @@
 /*
- * File      : interrupt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -62,13 +48,13 @@ rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector, void *param)
 void rt_hw_interrupt_init(void)
 {
     int idx;
-    
+
     /*  config interrupt vector*/
     asm volatile(
         "la t0, trap_entry\n"
         "csrw mtvec, t0"
     );
-    
+
     /*  enable global interrupt*/
     PLIC_init(&g_plic,
             PLIC_CTRL_ADDR,
@@ -86,8 +72,8 @@ void rt_hw_interrupt_init(void)
         irq_desc[idx].counter = 0;
 #endif
     }
-    
-    // enable machine external interrupt 
+
+    // enable machine external interrupt
     set_csr(mie, MIP_MEIP);
 }
 
@@ -132,7 +118,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
 }
 
 /**
- * This function will be call when external machine-level 
+ * This function will be call when external machine-level
  * interrupt from PLIC occurred.
  */
 void handle_m_ext_interrupt(void)
diff --git a/bsp/hifive1/drivers/interrupt.h b/bsp/hifive1/drivers/interrupt.h
index 506634e667..52d378233a 100644
--- a/bsp/hifive1/drivers/interrupt.h
+++ b/bsp/hifive1/drivers/interrupt.h
@@ -1,21 +1,7 @@
 /*
- * File      : interrupt.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -33,5 +19,5 @@ rt_uint32_t rt_hw_interrupt_get_active(rt_uint32_t fiq_irq);
 void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id);
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
         void *param, const char *name);
-        
+
 #endif
diff --git a/bsp/imx6sx/cortex-a9/drivers/emac_drv.c b/bsp/imx6sx/cortex-a9/drivers/emac_drv.c
index af5ca009cf..ff8a579435 100644
--- a/bsp/imx6sx/cortex-a9/drivers/emac_drv.c
+++ b/bsp/imx6sx/cortex-a9/drivers/emac_drv.c
@@ -1,7 +1,8 @@
 /*
  * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd
- * 
+ *
  * SPDX-License-Identifier: Apache-2.0
+ *
  * Change Logs:
  * Date           Author       Notes
  * 2015-07-15     Bernard      The first version
@@ -16,17 +17,17 @@
 #include 
 #include "emac_drv.h"
 
-#define MAX_ADDR_LEN 			6
-#define IMX_EMAC_DEVICE(eth)	(struct emac_device*)(eth)
+#define MAX_ADDR_LEN            6
+#define IMX_EMAC_DEVICE(eth)    (struct emac_device*)(eth)
 
 struct emac_device
 {
-	/* inherit from Ethernet device */
-	struct eth_device parent;
+    /* inherit from Ethernet device */
+    struct eth_device parent;
 
-	imx_enet_priv_t enet_priv;
-	/* interface address info. */
-	rt_uint8_t  dev_addr[MAX_ADDR_LEN];			/* MAC address	*/
+    imx_enet_priv_t enet_priv;
+    /* interface address info. */
+    rt_uint8_t  dev_addr[MAX_ADDR_LEN];         /* MAC address  */
 };
 static struct emac_device _emac;
 
@@ -54,7 +55,7 @@ void init_enet(struct emac_device* emac)
     // Check PHY link status.
     if (!(emac->enet_priv.status & ENET_STATUS_LINK_ON))
     {
-		rt_kprintf("ENET link status check fail\n");
+        rt_kprintf("ENET link status check fail\n");
     }
 
     imx_enet_start(&emac->enet_priv, emac->dev_addr);
@@ -62,69 +63,69 @@ void init_enet(struct emac_device* emac)
 
 void imx_enet_isr(int vector, void *param)
 {
-	unsigned int value = 0;
-	imx_enet_priv_t * dev = &(_emac.enet_priv);
-	volatile hw_enet_t *enet_reg = dev->enet_reg;
+    unsigned int value = 0;
+    imx_enet_priv_t * dev = &(_emac.enet_priv);
+    volatile hw_enet_t *enet_reg = dev->enet_reg;
 
     value = enet_reg->EIR.U;
     enet_reg->EIR.U = value & (~ENET_EVENT_MII);
 
     if (value & ENET_EVENT_TX_ERR)
-	{
+    {
         dev->tx_busy = 0;
     }
-	else if (value & ENET_EVENT_TX)
-	{
+    else if (value & ENET_EVENT_TX)
+    {
         dev->tx_busy = 0;
     }
 
     if (value & ENET_EVENT_RX)
-	{
-		eth_device_ready(&(_emac.parent));
+    {
+        eth_device_ready(&(_emac.parent));
     }
 
     if (value & ENET_EVENT_HBERR)
-	{
+    {
         // printf("WARNGING[POLL]: Hearbeat error!\n");
     }
 
     if (value & ENET_EVENT_EBERR)
-	{
+    {
         // printf("WARNING[POLL]: Ethernet Bus Error!\n");
     }
 }
 
 static rt_err_t imx_emac_init(rt_device_t dev)
 {
-	struct emac_device *emac;
+    struct emac_device *emac;
 
-	emac = IMX_EMAC_DEVICE(dev);
+    emac = IMX_EMAC_DEVICE(dev);
 
-	/* initialize enet */
-	init_enet(emac);
-	return RT_EOK;
+    /* initialize enet */
+    init_enet(emac);
+    return RT_EOK;
 }
 
 static rt_err_t imx_emac_open(rt_device_t dev, rt_uint16_t oflag)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t imx_emac_close(rt_device_t dev)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_size_t imx_emac_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
 {
-	rt_set_errno(-RT_ENOSYS);
-	return 0;
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
 }
 
 static rt_size_t imx_emac_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
 {
-	rt_set_errno(-RT_ENOSYS);
-	return 0;
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
 }
 
 static rt_err_t imx_emac_control(rt_device_t dev, int cmd, void *args)
@@ -134,19 +135,19 @@ static rt_err_t imx_emac_control(rt_device_t dev, int cmd, void *args)
     emac = IMX_EMAC_DEVICE(dev);
     RT_ASSERT(emac != RT_NULL);
 
-	switch(cmd)
-	{
-	case NIOCTL_GADDR:
-		/* get MAC address */
-		if(args) rt_memcpy(args, emac->dev_addr, 6);
-		else return -RT_ERROR;
-		break;
+    switch(cmd)
+    {
+    case NIOCTL_GADDR:
+        /* get MAC address */
+        if(args) rt_memcpy(args, emac->dev_addr, 6);
+        else return -RT_ERROR;
+        break;
 
-	default :
-		break;
-	}
+    default :
+        break;
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 /* Ethernet device interface */
@@ -161,8 +162,8 @@ rt_err_t imx_emac_tx(rt_device_t dev, struct pbuf* p)
 
     /* copy pbuf to a whole ETH frame */
     pbuf_copy_partial(p, s_pkt_send, p->tot_len, 0);
-	/* send to the enet */
-	imx_enet_send(&emac->enet_priv, s_pkt_send, p->tot_len, 1);
+    /* send to the enet */
+    imx_enet_send(&emac->enet_priv, s_pkt_send, p->tot_len, 1);
 
     return result;
 }
@@ -170,23 +171,23 @@ rt_err_t imx_emac_tx(rt_device_t dev, struct pbuf* p)
 /* reception packet. */
 struct pbuf *imx_emac_rx(rt_device_t dev)
 {
-	int len;
+    int len;
     struct pbuf* p = RT_NULL;
     struct emac_device *emac;
 
     emac = IMX_EMAC_DEVICE(dev);
     RT_ASSERT(emac != RT_NULL);
 
-	imx_enet_recv(&emac->enet_priv, s_pkt_recv, &len);
-	if (len > 0)
-	{
-		/* We allocate a pbuf chain of pbufs from the pool. */
-		p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
-		if (p != RT_NULL)
-		{
-			pbuf_take(p, s_pkt_recv, len);
-		}
-	}
+    imx_enet_recv(&emac->enet_priv, s_pkt_recv, &len);
+    if (len > 0)
+    {
+        /* We allocate a pbuf chain of pbufs from the pool. */
+        p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
+        if (p != RT_NULL)
+        {
+            pbuf_take(p, s_pkt_recv, len);
+        }
+    }
 
     return p;
 }
@@ -194,27 +195,27 @@ struct pbuf *imx_emac_rx(rt_device_t dev)
 int imx_emac_hw_init(void)
 {
     /* test MAC address */
-	_emac.dev_addr[0] = 0x00;
-	_emac.dev_addr[1] = 0x11;
-	_emac.dev_addr[2] = 0x22;
-	_emac.dev_addr[3] = 0x33;
-	_emac.dev_addr[4] = 0x44;
-	_emac.dev_addr[5] = 0x55;
+    _emac.dev_addr[0] = 0x00;
+    _emac.dev_addr[1] = 0x11;
+    _emac.dev_addr[2] = 0x22;
+    _emac.dev_addr[3] = 0x33;
+    _emac.dev_addr[4] = 0x44;
+    _emac.dev_addr[5] = 0x55;
 
-	_emac.parent.parent.init       = imx_emac_init;
-	_emac.parent.parent.open       = imx_emac_open;
-	_emac.parent.parent.close      = imx_emac_close;
-	_emac.parent.parent.read       = imx_emac_read;
-	_emac.parent.parent.write      = imx_emac_write;
-	_emac.parent.parent.control    = imx_emac_control;
-	_emac.parent.parent.user_data  = RT_NULL;
+    _emac.parent.parent.init       = imx_emac_init;
+    _emac.parent.parent.open       = imx_emac_open;
+    _emac.parent.parent.close      = imx_emac_close;
+    _emac.parent.parent.read       = imx_emac_read;
+    _emac.parent.parent.write      = imx_emac_write;
+    _emac.parent.parent.control    = imx_emac_control;
+    _emac.parent.parent.user_data  = RT_NULL;
 
-	_emac.parent.eth_rx     = imx_emac_rx;
-	_emac.parent.eth_tx     = imx_emac_tx;
+    _emac.parent.eth_rx     = imx_emac_rx;
+    _emac.parent.eth_tx     = imx_emac_tx;
 
     /* register ETH device */
     eth_device_init(&(_emac.parent), "e0");
 
-	return 0;
+    return 0;
 }
 INIT_DEVICE_EXPORT(imx_emac_hw_init);
diff --git a/bsp/imx6sx/cortex-a9/drivers/emac_drv.h b/bsp/imx6sx/cortex-a9/drivers/emac_drv.h
index face875283..455fa496e7 100644
--- a/bsp/imx6sx/cortex-a9/drivers/emac_drv.h
+++ b/bsp/imx6sx/cortex-a9/drivers/emac_drv.h
@@ -1,7 +1,8 @@
 /*
  * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd
- * 
+ *
  * SPDX-License-Identifier: Apache-2.0
+ *
  * Change Logs:
  * Date           Author       Notes
  * 2015-07-15     Bernard      The first version
diff --git a/bsp/imx6sx/cortex-a9/drivers/serial.c b/bsp/imx6sx/cortex-a9/drivers/serial.c
index a2d4e2338a..5a9e8121e1 100644
--- a/bsp/imx6sx/cortex-a9/drivers/serial.c
+++ b/bsp/imx6sx/cortex-a9/drivers/serial.c
@@ -1,7 +1,8 @@
 /*
  * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd
- * 
+ *
  * SPDX-License-Identifier: Apache-2.0
+ *
  * Change Logs:
  * Date           Author       Notes
  * 2013-03-30     Bernard      the first verion
diff --git a/bsp/imx6sx/cortex-a9/drivers/serial.h b/bsp/imx6sx/cortex-a9/drivers/serial.h
index 00d464bde0..862ba65ef7 100644
--- a/bsp/imx6sx/cortex-a9/drivers/serial.h
+++ b/bsp/imx6sx/cortex-a9/drivers/serial.h
@@ -1,7 +1,8 @@
 /*
  * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd
- * 
+ *
  * SPDX-License-Identifier: Apache-2.0
+ *
  * Change Logs:
  * Date           Author       Notes
  * 2013-03-30     Bernard      the first verion
diff --git a/bsp/imx6ul/drivers/serial.c b/bsp/imx6ul/drivers/serial.c
index 0f6943cfbd..ce46050c92 100644
--- a/bsp/imx6ul/drivers/serial.c
+++ b/bsp/imx6ul/drivers/serial.c
@@ -1,7 +1,8 @@
 /*
  * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd
- * 
+ *
  * SPDX-License-Identifier: Apache-2.0
+ *
  * Change Logs:
  * Date           Author       Notes
  * 2013-03-30     Bernard      the first verion
diff --git a/bsp/imx6ul/drivers/serial.h b/bsp/imx6ul/drivers/serial.h
index 00d464bde0..862ba65ef7 100644
--- a/bsp/imx6ul/drivers/serial.h
+++ b/bsp/imx6ul/drivers/serial.h
@@ -1,7 +1,8 @@
 /*
  * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd
- * 
+ *
  * SPDX-License-Identifier: Apache-2.0
+ *
  * Change Logs:
  * Date           Author       Notes
  * 2013-03-30     Bernard      the first verion
diff --git a/bsp/imxrt/libraries/MIMXRT1050/SConscript b/bsp/imxrt/libraries/MIMXRT1050/SConscript
index 6f871d6610..7f8f971b82 100644
--- a/bsp/imxrt/libraries/MIMXRT1050/SConscript
+++ b/bsp/imxrt/libraries/MIMXRT1050/SConscript
@@ -34,6 +34,7 @@ if GetDepend(['BSP_USING_HWTIMER']) or GetDepend(['BSP_USING_PWM']):
 
 if GetDepend(['BSP_USING_PWM']):
     src += ['MIMXRT1052/drivers/fsl_pwm.c']
+    src += ['MIMXRT1052/drivers/fsl_qtmr.c']
 
 if GetDepend(['BSP_USING_RTC']):
     src += ['MIMXRT1052/drivers/fsl_snvs_hp.c']
@@ -52,9 +53,6 @@ if GetDepend(['BSP_USING_SDRAM']):
 if GetDepend(['BSP_USING_LCD']):
     src += ['MIMXRT1052/drivers/fsl_elcdif.c']
 
-if GetDepend(['RT_USING_USB_HOST']) or GetDepend(['RT_USING_USB_DEVICE']):
-    src += ['MIMXRT1052/drivers/fsl_usdhc.c']
-
 if GetDepend(['BSP_USING_CAN']):
     src += ['MIMXRT1052/drivers/fsl_flexcan.c']
 
@@ -78,6 +76,9 @@ if GetDepend(['BSP_USING_DMA']):
     src += ['MIMXRT1052/drivers/fsl_lpspi_edma.c']
     
 
-group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path)
+if rtconfig.CROSS_TOOL == 'gcc':
+    group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, ASFLAGS = '$ASFLAGS -D __STARTUP_CLEAR_BSS')
+else:
+    group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path)
 
 Return('group')
diff --git a/bsp/imxrt/libraries/MIMXRT1064/SConscript b/bsp/imxrt/libraries/MIMXRT1064/SConscript
index 2035ca530f..c83546f0eb 100644
--- a/bsp/imxrt/libraries/MIMXRT1064/SConscript
+++ b/bsp/imxrt/libraries/MIMXRT1064/SConscript
@@ -49,9 +49,6 @@ if GetDepend(['BSP_USING_ADC']):
 if GetDepend(['BSP_USING_SDRAM']):
     src += ['MIMXRT1064/drivers/fsl_semc.c']
 
-if GetDepend(['RT_USING_USB_HOST']) or GetDepend(['RT_USING_USB_DEVICE']):
-    src += ['MIMXRT1064/drivers/fsl_usdhc.c']
-
 if GetDepend(['RT_USING_CAN']):
     src += ['MIMXRT1064/drivers/fsl_flexcan.c']
 
@@ -77,6 +74,9 @@ if GetDepend(['RT_SERIAL_USING_DMA']):
     src += ['MIMXRT1064/drivers/fsl_lpuart_edma.c']
     src += ['MIMXRT1064/drivers/fsl_lpspi_edma.c']
 
-group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path)
+if rtconfig.CROSS_TOOL == 'gcc':
+    group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, ASFLAGS = '$ASFLAGS -D __STARTUP_CLEAR_BSS')
+else:
+    group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path)
 
 Return('group')
diff --git a/bsp/imxrt/libraries/drivers/drv_lcd.c b/bsp/imxrt/libraries/drivers/drv_lcd.c
index 3d2ca8a055..f386e082cc 100644
--- a/bsp/imxrt/libraries/drivers/drv_lcd.c
+++ b/bsp/imxrt/libraries/drivers/drv_lcd.c
@@ -1,18 +1,14 @@
 /*
- * File      : drv_lcd.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2013, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2017-10-30     Tanek        the first version
  * 2018-04-05     Liu2guang    export LCD config parameters.
  */
- 
+
 #include 
 
 #ifdef BSP_USING_LCD
diff --git a/bsp/imxrt/libraries/drivers/drv_lcd.h b/bsp/imxrt/libraries/drivers/drv_lcd.h
index 8dd6ab9031..a67c8c3250 100644
--- a/bsp/imxrt/libraries/drivers/drv_lcd.h
+++ b/bsp/imxrt/libraries/drivers/drv_lcd.h
@@ -1,11 +1,7 @@
 /*
- * File      : drv_lcd2.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2013, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/imxrt/libraries/drivers/drv_pwm.c b/bsp/imxrt/libraries/drivers/drv_pwm.c
index fdfb8907f6..3f2a11b4e6 100644
--- a/bsp/imxrt/libraries/drivers/drv_pwm.c
+++ b/bsp/imxrt/libraries/drivers/drv_pwm.c
@@ -16,8 +16,12 @@
 #if !defined(BSP_USING_PWM1_CH0) && !defined(BSP_USING_PWM1_CH1) && !defined(BSP_USING_PWM1_CH2) && !defined(BSP_USING_PWM1_CH3) && \
     !defined(BSP_USING_PWM2_CH0) && !defined(BSP_USING_PWM2_CH1) && !defined(BSP_USING_PWM2_CH2) && !defined(BSP_USING_PWM2_CH3) && \
     !defined(BSP_USING_PWM3_CH0) && !defined(BSP_USING_PWM3_CH1) && !defined(BSP_USING_PWM3_CH2) && !defined(BSP_USING_PWM3_CH3) && \
-    !defined(BSP_USING_PWM4_CH0) && !defined(BSP_USING_PWM4_CH1) && !defined(BSP_USING_PWM4_CH2) && !defined(BSP_USING_PWM4_CH3)
-#error "Please define at least one BSP_USING_PWMx_CHx"
+    !defined(BSP_USING_PWM4_CH0) && !defined(BSP_USING_PWM4_CH1) && !defined(BSP_USING_PWM4_CH2) && !defined(BSP_USING_PWM4_CH3) && \
+    !defined(BSP_USING_QTMR1_CH0) && !defined(BSP_USING_QTMR1_CH1) && !defined(BSP_USING_QTMR1_CH2) && !defined(BSP_USING_QTMR1_CH3) && \
+    !defined(BSP_USING_QTMR2_CH0) && !defined(BSP_USING_QTMR2_CH1) && !defined(BSP_USING_QTMR2_CH2) && !defined(BSP_USING_QTMR2_CH3) && \
+    !defined(BSP_USING_QTMR3_CH0) && !defined(BSP_USING_QTMR3_CH1) && !defined(BSP_USING_QTMR3_CH2) && !defined(BSP_USING_QTMR3_CH3) && \
+    !defined(BSP_USING_QTMR4_CH0) && !defined(BSP_USING_QTMR4_CH1) && !defined(BSP_USING_QTMR4_CH2) && !defined(BSP_USING_QTMR4_CH3)
+#error "Please define at least one BSP_USING_PWMx_CHx or BSP_USING_QTMRx_CHx"
 #endif
 
 #define LOG_TAG             "drv.pwm"
@@ -25,6 +29,9 @@
 
 #include 
 #include "fsl_pwm.h"
+#if defined(FSL_FEATURE_SOC_TMR_COUNT) && FSL_FEATURE_SOC_TMR_COUNT > 0
+    #include "fsl_qtmr.h"
+#endif
 #include "drv_pwm.h"
 
 #define DEFAULT_PRE                   5
@@ -153,7 +160,7 @@ static rt_err_t imxrt_drv_pwm_init(PWM_Type *base, pwm_submodule_t pwm_submodule
     if (PWM_Init(base, pwm_submodule, &PwmConfig) == kStatus_Fail)
     {
         LOG_E("init pwm failed \n");
-        return RT_ERROR;
+        return -RT_ERROR;
     }
 
     base->SM[fault_input].DISMAP[0] = 0x00;
@@ -176,28 +183,28 @@ static rt_err_t imxrt_pwm1_init(PWM_Type *base)
 #ifdef BSP_USING_PWM1_CH0
     if (imxrt_drv_pwm_init(base, kPWM_Module_0, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
     {
-        return RT_ERROR;
+        return -RT_ERROR;
     }
 #endif /* BSP_USING_PWM1_CH0 */
 
 #ifdef BSP_USING_PWM1_CH1
     if (imxrt_drv_pwm_init(base, kPWM_Module_1, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
     {
-        return RT_ERROR;
+        return -RT_ERROR;
     }
 #endif /* BSP_USING_PWM1_CH1 */
 
 #ifdef BSP_USING_PWM1_CH2
     if (imxrt_drv_pwm_init(base, kPWM_Module_2, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
     {
-        return RT_ERROR;
+        return -RT_ERROR;
     }
 #endif /*BSP_USING_PWM1_CH2 */
 
 #ifdef BSP_USING_PWM1_CH3
     if (imxrt_drv_pwm_init(base, kPWM_Module_3, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
     {
-        return RT_ERROR;
+        return -RT_ERROR;
     }
 #endif /* BSP_USING_PWM1_CH3 */
 
@@ -213,28 +220,28 @@ static rt_err_t imxrt_pwm2_init(PWM_Type *base)
 #ifdef BSP_USING_PWM2_CH0
     if (imxrt_drv_pwm_init(base, kPWM_Module_0, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
     {
-        return RT_ERROR;
+        return -RT_ERROR;
     }
 #endif /* BSP_USING_PWM2_CH0 */
 
 #ifdef BSP_USING_PWM2_CH1
     if (imxrt_drv_pwm_init(base, kPWM_Module_1, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
     {
-        return RT_ERROR;
+        return -RT_ERROR;
     }
 #endif /* BSP_USING_PWM2_CH1 */
 
 #ifdef BSP_USING_PWM2_CH2
     if (imxrt_drv_pwm_init(base, kPWM_Module_2, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
     {
-        return RT_ERROR;
+        return -RT_ERROR;
     }
 #endif /*BSP_USING_PWM2_CH2 */
 
 #ifdef BSP_USING_PWM2_CH3
     if (imxrt_drv_pwm_init(base, kPWM_Module_3, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
     {
-        return RT_ERROR;
+        return -RT_ERROR;
     }
 #endif /* BSP_USING_PWM2_CH3 */
 
@@ -250,28 +257,28 @@ static rt_err_t imxrt_pwm3_init(PWM_Type *base)
 #ifdef BSP_USING_PWM3_CH0
     if (imxrt_drv_pwm_init(base, kPWM_Module_0, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
     {
-        return RT_ERROR;
+        return -RT_ERROR;
     }
 #endif /* BSP_USING_PWM3_CH0 */
 
 #ifdef BSP_USING_PWM3_CH1
     if (imxrt_drv_pwm_init(base, kPWM_Module_1, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
     {
-        return RT_ERROR;
+        return -RT_ERROR;
     }
 #endif /* BSP_USING_PWM3_CH1 */
 
 #ifdef BSP_USING_PWM3_CH2
     if (imxrt_drv_pwm_init(base, kPWM_Module_2, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
     {
-        return RT_ERROR;
+        return -RT_ERROR;
     }
 #endif /*BSP_USING_PWM3_CH2 */
 
 #ifdef BSP_USING_PWM3_CH3
     if (imxrt_drv_pwm_init(base, kPWM_Module_3, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
     {
-        return RT_ERROR;
+        return -RT_ERROR;
     }
 #endif /* BSP_USING_PWM3_CH3 */
 
@@ -287,28 +294,28 @@ static rt_err_t imxrt_pwm4_init(PWM_Type *base)
 #ifdef BSP_USING_PWM4_CH0
     if (imxrt_drv_pwm_init(base, kPWM_Module_0, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
     {
-        return RT_ERROR;
+        return -RT_ERROR;
     }
 #endif /* BSP_USING_PWM4_CH0 */
 
 #ifdef BSP_USING_PWM4_CH1
     if (imxrt_drv_pwm_init(base, kPWM_Module_1, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
     {
-        return RT_ERROR;
+        return -RT_ERROR;
     }
 #endif /* BSP_USING_PWM4_CH1 */
 
 #ifdef BSP_USING_PWM4_CH2
     if (imxrt_drv_pwm_init(base, kPWM_Module_2, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
     {
-        return RT_ERROR;
+        return -RT_ERROR;
     }
 #endif /*BSP_USING_PWM4_CH2 */
 
 #ifdef BSP_USING_PWM4_CH3
     if (imxrt_drv_pwm_init(base, kPWM_Module_3, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
     {
-        return RT_ERROR;
+        return -RT_ERROR;
     }
 #endif /* BSP_USING_PWM4_CH3 */
 
@@ -317,6 +324,224 @@ static rt_err_t imxrt_pwm4_init(PWM_Type *base)
 
 #endif /* BSP_USING_PWM4 */
 
+static rt_err_t imxrt_drv_qtmr_control(struct rt_device_pwm *device, int cmd, void *arg);
+
+static struct rt_pwm_ops imxrt_drv_qtmr_ops =
+{
+    .control = imxrt_drv_qtmr_control
+};
+
+static rt_err_t imxrt_drv_qtmr_enable(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration, rt_bool_t enable)
+{
+    TMR_Type *base;
+    base = (TMR_Type *)device->parent.user_data;
+
+    if (!enable)
+    {
+        QTMR_StopTimer(base, configuration->channel);
+        base->CHANNEL[configuration->channel].SCTRL |= (TMR_SCTRL_FORCE_MASK | TMR_SCTRL_OEN_MASK);
+    }
+    else
+    {
+        QTMR_StartTimer(base, configuration->channel, kQTMR_PriSrcRiseEdge);
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t imxrt_drv_qtmr_get(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration)
+{
+    TMR_Type *base;
+    rt_uint32_t high_count, low_count, clk_divider, clk_freq;
+
+    base = (TMR_Type *)device->parent.user_data;
+
+    low_count = base->CHANNEL[configuration->channel].COMP1;
+    high_count = base->CHANNEL[configuration->channel].COMP2;
+    clk_divider = 1 << (((base->CHANNEL[configuration->channel].CTRL & TMR_CTRL_PCS_MASK) >> TMR_CTRL_PCS_SHIFT) - 8);
+    clk_freq = CLOCK_GetFreq(kCLOCK_IpgClk) / clk_divider;
+
+    configuration->period = 1000000000 / clk_freq * (high_count + low_count);
+    configuration->pulse = 1000000000 / clk_freq * high_count;
+
+    return RT_EOK;
+}
+
+static rt_err_t imxrt_drv_qtmr_set(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration)
+{
+    RT_ASSERT(configuration->period > 0);
+    RT_ASSERT(configuration->pulse <= configuration->period);
+
+    TMR_Type *base = (TMR_Type *)device->parent.user_data;
+
+    rt_size_t clk_freq = CLOCK_GetFreq(kCLOCK_IpgClk) / (1 << (((base->CHANNEL[configuration->channel].CTRL & TMR_CTRL_PCS_MASK) >> TMR_CTRL_PCS_SHIFT) - 8));
+    rt_size_t current_period_count = base->CHANNEL[configuration->channel].CMPLD1 + base->CHANNEL[configuration->channel].CMPLD2;
+    rt_size_t period_count = clk_freq / (1000000000 / configuration->period);
+    if (current_period_count == period_count)
+    {
+        rt_size_t high_count   = period_count * configuration->pulse / configuration->period;
+        rt_size_t low_count    = period_count - high_count;
+        base->CHANNEL[configuration->channel].CMPLD1 = (uint16_t)low_count;
+        base->CHANNEL[configuration->channel].CMPLD2 = (uint16_t)high_count;
+    }
+    else
+    {
+        rt_bool_t timer_is_on = base->CHANNEL[configuration->channel].CTRL & TMR_CTRL_CM_MASK;
+        rt_uint8_t duty = configuration->pulse * 100 / configuration->period;
+        QTMR_StopTimer(base, configuration->channel);
+        if (kStatus_Success != QTMR_SetupPwm(base, configuration->channel, 1000000000 / configuration->period, duty, DEFAULT_POLARITY, clk_freq))
+        {
+            LOG_E(LOG_TAG" setup pwm failed \n");
+            return -RT_ERROR;
+        }
+        if (timer_is_on)
+        {
+            QTMR_StartTimer(base, configuration->channel, kQTMR_PriSrcRiseEdge);
+        }
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t imxrt_drv_qtmr_control(struct rt_device_pwm *device, int cmd, void *arg)
+{
+    struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
+
+    switch (cmd)
+    {
+    case PWM_CMD_ENABLE:
+        return imxrt_drv_qtmr_enable(device, configuration, RT_TRUE);
+    case PWM_CMD_DISABLE:
+        return imxrt_drv_qtmr_enable(device, configuration, RT_FALSE);
+    case PWM_CMD_SET:
+        return imxrt_drv_qtmr_set(device, configuration);
+    case PWM_CMD_GET:
+        return imxrt_drv_qtmr_get(device, configuration);
+    default:
+        return RT_EINVAL;
+    }
+}
+
+static rt_err_t imxrt_drv_qtmr_init(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t psc, uint32_t fre, uint8_t duty)
+{
+    qtmr_config_t qtmr_config;
+    rt_uint32_t qtmr_clock_freq;
+    QTMR_GetDefaultConfig(&qtmr_config);
+
+    qtmr_config.primarySource = (qtmr_primary_count_source_t)(psc + 8);
+    qtmr_clock_freq = CLOCK_GetFreq(kCLOCK_IpgClk) / (1 << psc);
+
+    QTMR_Init(base, channel, &qtmr_config);
+
+    if (kStatus_Success != QTMR_SetupPwm(base, channel, fre, duty, DEFAULT_POLARITY, qtmr_clock_freq))
+    {
+        LOG_E(LOG_TAG" setup pwm failed \n");
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t imxrt_qtmr_init()
+{
+    TMR_Type *base_list[] =
+    {
+#ifdef BSP_USING_QTMR1
+        TMR1,
+#endif
+#ifdef BSP_USING_QTMR2
+        TMR2,
+#endif
+#ifdef BSP_USING_QTMR3
+        TMR3,
+#endif
+#ifdef BSP_USING_QTMR4
+        TMR4,
+#endif
+    };
+
+    rt_uint8_t channel_list[] =
+    {
+#ifdef BSP_USING_QTMR1
+#ifdef BSP_USING_QTMR1_CH0
+        1 << 0 |
+#endif
+#ifdef BSP_USING_QTMR1_CH1
+        1 << 1 |
+#endif
+#ifdef BSP_USING_QTMR1_CH2
+        1 << 2 |
+#endif
+#ifdef BSP_USING_QTMR1_CH3
+        1 << 3 |
+#endif
+        0,
+#endif
+#ifdef BSP_USING_QTMR2
+#ifdef BSP_USING_QTMR2_CH0
+        1 << 0 |
+#endif
+#ifdef BSP_USING_QTMR2_CH1
+        1 << 1 |
+#endif
+#ifdef BSP_USING_QTMR2_CH2
+        1 << 2 |
+#endif
+#ifdef BSP_USING_QTMR2_CH3
+        1 << 3 |
+#endif
+        0,
+#endif
+#ifdef BSP_USING_QTMR3
+#ifdef BSP_USING_QTMR3_CH0
+        1 << 0 |
+#endif
+#ifdef BSP_USING_QTMR3_CH1
+        1 << 1 |
+#endif
+#ifdef BSP_USING_QTMR3_CH2
+        1 << 2 |
+#endif
+#ifdef BSP_USING_QTMR3_CH3
+        1 << 3 |
+#endif
+        0,
+#endif
+#ifdef BSP_USING_QTMR4
+#ifdef BSP_USING_QTMR4_CH0
+        1 << 0 |
+#endif
+#ifdef BSP_USING_QTMR4_CH1
+        1 << 1 |
+#endif
+#ifdef BSP_USING_QTMR4_CH2
+        1 << 2 |
+#endif
+#ifdef BSP_USING_QTMR4_CH3
+        1 << 3 |
+#endif
+        0,
+#endif
+    };
+
+    for (rt_uint8_t i = 0; i < sizeof(base_list)/sizeof(TMR_Type *); ++i)
+    {
+        for (rt_uint8_t j = 0; j < 8; ++j)
+        {
+            if ((channel_list[i] >> j) & 1)
+            {
+                if (imxrt_drv_qtmr_init(base_list[i], j, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
+                {
+                    return -RT_ERROR;
+                }
+            }
+        }
+    }
+    return RT_EOK;
+}
+
+
+
 int rt_hw_pwm_init(void)
 {
     rt_err_t ret = RT_EOK;
@@ -391,9 +616,52 @@ int rt_hw_pwm_init(void)
     }
 #endif /* BSP_USING_PWM4 */
 
+#if defined(BSP_USING_QTMR1) || defined(BSP_USING_QTMR2) || defined(BSP_USING_QTMR3) || defined(BSP_USING_QTMR4)
+    if (imxrt_qtmr_init() != RT_EOK)
+    {
+        LOG_E(LOG_TAG" init qtmr failed");
+    }
+#endif
+
+#ifdef BSP_USING_QTMR1
+    static struct rt_device_pwm qtmr1_device;
+    ret = rt_device_pwm_register(&qtmr1_device, "pwm5", &imxrt_drv_qtmr_ops, TMR1);
+    if (ret != RT_EOK)
+    {
+        LOG_E("%s register failed", "pwm5");
+    }
+#endif /* BSP_USING_QTMR1 */
+
+#ifdef BSP_USING_QTMR2
+    static struct rt_device_pwm qtmr2_device;
+    ret = rt_device_pwm_register(&qtmr2_device, "pwm6", &imxrt_drv_qtmr_ops, TMR2);
+    if (ret != RT_EOK)
+    {
+        LOG_E("%s register failed", "pwm6");
+    }
+#endif /* BSP_USING_QTMR2 */
+
+#ifdef BSP_USING_QTMR3
+    static struct rt_device_pwm qtmr3_device;
+    ret = rt_device_pwm_register(&qtmr3_device, "pwm7", &imxrt_drv_qtmr_ops, TMR3);
+    if (ret != RT_EOK)
+    {
+        LOG_E("%s register failed", "pwm7");
+    }
+#endif /* BSP_USING_QTMR3 */
+
+#ifdef BSP_USING_QTMR4
+    static struct rt_device_pwm qtmr4_device;
+    ret = rt_device_pwm_register(&qtmr4_device, "pwm8", &imxrt_drv_qtmr_ops, TMR4);
+    if (ret != RT_EOK)
+    {
+        LOG_E("%s register failed", "pwm8");
+    }
+#endif /* BSP_USING_QTMR4 */
+
     return ret;
 }
 
-INIT_DEVICE_EXPORT(rt_hw_pwm_init);
+INIT_BOARD_EXPORT(rt_hw_pwm_init);
 
 #endif /* BSP_USING_PWM */
diff --git a/bsp/imxrt/libraries/drivers/drv_spi.c b/bsp/imxrt/libraries/drivers/drv_spi.c
index e0375166a2..04c9e94020 100644
--- a/bsp/imxrt/libraries/drivers/drv_spi.c
+++ b/bsp/imxrt/libraries/drivers/drv_spi.c
@@ -64,6 +64,8 @@ struct imxrt_spi
     char *bus_name;
     LPSPI_Type *base;
     struct rt_spi_bus spi_bus;
+    rt_sem_t xfer_sem;
+    lpspi_master_handle_t spi_normal;
     struct dma_config *dma;
     rt_uint8_t dma_flag;
 };
@@ -159,9 +161,18 @@ static void spi_get_dma_config(void)
 #endif
 }
 
+void normal_xfer_callback(LPSPI_Type *base, lpspi_master_handle_t *handle, status_t status, void *userData)
+{
+    /* xfer complete callback */
+    struct imxrt_spi *spi = (struct imxrt_spi *)userData;
+    rt_sem_release(spi->xfer_sem);
+}
+
 void edma_xfer_callback(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, status_t status, void *userData)
 {
     /* xfer complete callback */
+    struct imxrt_spi *spi = (struct imxrt_spi *)userData;
+    rt_sem_release(spi->xfer_sem);
 }
 
 rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint32_t pin)
@@ -217,6 +228,17 @@ static uint32_t imxrt_get_lpspi_freq(void)
     return freq;
 }
 
+static void lpspi_normal_config(struct imxrt_spi *spi)
+{
+    RT_ASSERT(spi != RT_NULL);
+
+    LPSPI_MasterTransferCreateHandle(spi->base,
+                                    &spi->spi_normal,
+                                    normal_xfer_callback,
+                                    spi);
+    LOG_D(LOG_TAG" %s normal config done\n", spi->bus_name);
+}
+
 static void lpspi_dma_config(struct imxrt_spi *spi)
 {
     RT_ASSERT(spi != RT_NULL);
@@ -325,12 +347,17 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
 
     if(RT_FALSE == spi->dma_flag)
     {
+#ifdef BSP_USING_BLOCKING_SPI
         status = LPSPI_MasterTransferBlocking(spi->base, &transfer);
+#else
+        status = LPSPI_MasterTransferNonBlocking(spi->base, &spi->spi_normal, &transfer);
+#endif
     }
     else
     {
         status = LPSPI_MasterTransferEDMA(spi->base,&spi->dma->spi_edma,&transfer);
     }
+    rt_sem_take(spi->xfer_sem, RT_WAITING_FOREVER);
 
     if(message->cs_release)
     {
@@ -369,6 +396,13 @@ int rt_hw_spi_bus_init(void)
         {
             lpspi_dma_config(&lpspis[i]);
         }
+        else
+        {
+            lpspi_normal_config(&lpspis[i]);
+        }
+        char sem_name[RT_NAME_MAX];
+        rt_sprintf(sem_name, "%s_s", lpspis[i].bus_name);
+        lpspis[i].xfer_sem = rt_sem_create(sem_name, 0, RT_IPC_FLAG_PRIO);
     }
 
     return ret; 
diff --git a/bsp/lpc1114/driver/board.c b/bsp/lpc1114/driver/board.c
index 6f2a4c85a3..03aa631e71 100644
--- a/bsp/lpc1114/driver/board.c
+++ b/bsp/lpc1114/driver/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -33,7 +33,7 @@
 #define NVIC_ISPR       HWREG32(SCB_BASE + 0x200)
 #define NVIC_ICPR       HWREG32(SCB_BASE + 0x280)
 #define NVIC_IPR(irqno) HWREG32(SCB_BASE + 0x400 + (((irqno) / 4) << 2))
-#define SCB_SHPR3       HWREG32(SCB_BASE + 0xd20) 
+#define SCB_SHPR3       HWREG32(SCB_BASE + 0xd20)
 
 extern unsigned char __bss_end__[];
 extern unsigned char _ram_end[];
diff --git a/bsp/lpc1114/driver/drv_uart.c b/bsp/lpc1114/driver/drv_uart.c
index 96cf6f760d..10956140c1 100644
--- a/bsp/lpc1114/driver/drv_uart.c
+++ b/bsp/lpc1114/driver/drv_uart.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc1114/rtconfig.py b/bsp/lpc1114/rtconfig.py
index 4eb53465df..0fc441cee6 100644
--- a/bsp/lpc1114/rtconfig.py
+++ b/bsp/lpc1114/rtconfig.py
@@ -17,7 +17,7 @@ if  CROSS_TOOL == 'gcc':
     PLATFORM    = 'gcc'
     EXEC_PATH   = r'/usr/bin'
 else:
-    print 'Please make sure your toolchains is GNU GCC!'
+    print ('Please make sure your toolchains is GNU GCC!')
     exit(0)
 
 if os.getenv('RTT_EXEC_PATH'):
diff --git a/bsp/lpc176x/applications/application.c b/bsp/lpc176x/applications/application.c
index 9facb30aa8..173e2df1bb 100644
--- a/bsp/lpc176x/applications/application.c
+++ b/bsp/lpc176x/applications/application.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -38,44 +38,44 @@ extern int lwip_system_init(void);
 /* thread phase init */
 void rt_init_thread_entry(void *parameter)
 {
-	/* initialize platform */
-	platform_init();
+    /* initialize platform */
+    platform_init();
 
 #ifdef RT_USING_LWIP
     /* register Ethernet interface device */
     lpc17xx_emac_hw_init();
 
     /* initialize lwip stack */
-	/* register ethernetif device */
-	eth_system_device_init();
+    /* register ethernetif device */
+    eth_system_device_init();
 
-	/* initialize lwip system */
-	lwip_system_init();
-	rt_kprintf("TCP/IP initialized!\n");
+    /* initialize lwip system */
+    lwip_system_init();
+    rt_kprintf("TCP/IP initialized!\n");
 #endif
 
     /* Filesystem Initialization */
 #ifdef RT_USING_DFS
     rt_hw_sdcard_init();
 
-	/* initialize the device file system */
-	dfs_init();
+    /* initialize the device file system */
+    dfs_init();
 
 #ifdef RT_USING_DFS_ELMFAT
-	/* initialize the elm chan FatFS file system*/
-	elm_init();
+    /* initialize the elm chan FatFS file system*/
+    elm_init();
 #endif
 
     /* mount sd card fat partition 1 as root directory */
     if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
-    	rt_kprintf("File System initialized!\n");
+        rt_kprintf("File System initialized!\n");
     else
-    	rt_kprintf("File System init failed!\n");
+        rt_kprintf("File System init failed!\n");
 #endif
 
 #ifdef RT_USING_FINSH
-	/* initialize finsh */
-	finsh_system_init();
+    /* initialize finsh */
+    finsh_system_init();
 #endif
 }
 
@@ -84,8 +84,8 @@ int rt_application_init()
     rt_thread_t tid;
 
     tid = rt_thread_create("init",
-    		rt_init_thread_entry, RT_NULL,
-    		2048, RT_THREAD_PRIORITY_MAX/3, 20);
+            rt_init_thread_entry, RT_NULL,
+            2048, RT_THREAD_PRIORITY_MAX/3, 20);
     if (tid != RT_NULL) rt_thread_startup(tid);
 
     return 0;
diff --git a/bsp/lpc176x/applications/platform.c b/bsp/lpc176x/applications/platform.c
index 4bab858aa4..05ff436e8d 100644
--- a/bsp/lpc176x/applications/platform.c
+++ b/bsp/lpc176x/applications/platform.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,11 +16,11 @@ static struct rt_memheap _memheap;
 void platform_init(void)
 {
 #ifdef RT_USING_MEMHEAP
-	/* create memory heap object on 0x2007 C000 - 0x2008 4000*/
+    /* create memory heap object on 0x2007 C000 - 0x2008 4000*/
 #ifdef RT_USING_LWIP
-	rt_memheap_init(&_memheap, "system", (void*)0x2007C000, 16*1024);
+    rt_memheap_init(&_memheap, "system", (void*)0x2007C000, 16*1024);
 #else
-	rt_memheap_init(&_memheap, "system", (void*)0x2007C000, 32*1024);
+    rt_memheap_init(&_memheap, "system", (void*)0x2007C000, 32*1024);
 #endif
 #endif
 }
diff --git a/bsp/lpc176x/applications/platform.h b/bsp/lpc176x/applications/platform.h
index e52e4066c2..25a97d8666 100644
--- a/bsp/lpc176x/applications/platform.h
+++ b/bsp/lpc176x/applications/platform.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc176x/applications/startup.c b/bsp/lpc176x/applications/startup.c
index 63d5b0f9a5..b9db54c429 100644
--- a/bsp/lpc176x/applications/startup.c
+++ b/bsp/lpc176x/applications/startup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -33,28 +33,28 @@ extern int __bss_end;
  */
 void rtthread_startup(void)
 {
-	/* initialize board */
-	rt_hw_board_init();
+    /* initialize board */
+    rt_hw_board_init();
 
-	/* show version */
-	rt_show_version();
+    /* show version */
+    rt_show_version();
 
 #ifdef RT_USING_HEAP
-	/* initialize memory system */
-	#ifdef __CC_ARM
-		rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x10008000);
-	#elif __ICCARM__
-	    rt_system_heap_init(__segment_end("HEAP"), (void*)0x10008000);
-	#else
-		rt_system_heap_init((void*)&__bss_end, (void*)0x10008000);
-	#endif
+    /* initialize memory system */
+    #ifdef __CC_ARM
+        rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x10008000);
+    #elif __ICCARM__
+        rt_system_heap_init(__segment_end("HEAP"), (void*)0x10008000);
+    #else
+        rt_system_heap_init((void*)&__bss_end, (void*)0x10008000);
+    #endif
 #endif
 
-	/* initialize scheduler system */
-	rt_system_scheduler_init();
+    /* initialize scheduler system */
+    rt_system_scheduler_init();
 
-	/* initialize application */
-	rt_application_init();
+    /* initialize application */
+    rt_application_init();
 
     /* initialize timer */
     rt_system_timer_init();
@@ -62,25 +62,25 @@ void rtthread_startup(void)
     /* initialize timer thread */
     rt_system_timer_thread_init();
 
-	/* initialize idle thread */
-	rt_thread_idle_init();
+    /* initialize idle thread */
+    rt_thread_idle_init();
 
-	/* start scheduler */
-	rt_system_scheduler_start();
+    /* start scheduler */
+    rt_system_scheduler_start();
 
-	/* never reach here */
-	return ;
+    /* never reach here */
+    return ;
 }
 
 int main(void)
 {
-	/* disable interrupt first */
-	rt_hw_interrupt_disable();
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
 
-	/* startup RT-Thread RTOS */
-	rtthread_startup();
+    /* startup RT-Thread RTOS */
+    rtthread_startup();
 
-	return 0;
+    return 0;
 }
 
 /*@}*/
diff --git a/bsp/lpc176x/drivers/board.c b/bsp/lpc176x/drivers/board.c
index c636462a2e..de3e476d55 100644
--- a/bsp/lpc176x/drivers/board.c
+++ b/bsp/lpc176x/drivers/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -29,13 +29,13 @@
  */
 void rt_hw_timer_handler(void)
 {
-	/* enter interrupt */
-	rt_interrupt_enter();
+    /* enter interrupt */
+    rt_interrupt_enter();
 
-	rt_tick_increase();
+    rt_tick_increase();
 
-	/* leave interrupt */
-	rt_interrupt_leave();
+    /* leave interrupt */
+    rt_interrupt_leave();
 }
 
 void SysTick_Handler(void)
@@ -48,24 +48,24 @@ void SysTick_Handler(void)
  */
 void rt_hw_board_init()
 {
-	/* NVIC Configuration */
+    /* NVIC Configuration */
 #define NVIC_VTOR_MASK              0x3FFFFF80
 #ifdef  VECT_TAB_RAM
-	/* Set the Vector Table base location at 0x10000000 */
-	SCB->VTOR  = (0x10000000 & NVIC_VTOR_MASK);
+    /* Set the Vector Table base location at 0x10000000 */
+    SCB->VTOR  = (0x10000000 & NVIC_VTOR_MASK);
 #else  /* VECT_TAB_FLASH  */
-	/* Set the Vector Table base location at 0x00000000 */
-	SCB->VTOR  = (0x00000000 & NVIC_VTOR_MASK);
+    /* Set the Vector Table base location at 0x00000000 */
+    SCB->VTOR  = (0x00000000 & NVIC_VTOR_MASK);
 #endif
 
-	/* initialize systick */
-	SysTick_Config( SystemCoreClock/RT_TICK_PER_SECOND);
-	/* set pend exception priority */
-	NVIC_SetPriority(PendSV_IRQn, (1<<__NVIC_PRIO_BITS) - 1);
+    /* initialize systick */
+    SysTick_Config( SystemCoreClock/RT_TICK_PER_SECOND);
+    /* set pend exception priority */
+    NVIC_SetPriority(PendSV_IRQn, (1<<__NVIC_PRIO_BITS) - 1);
 
 #ifdef RT_USING_UART0
-	rt_hw_uart_init();
-	rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+    rt_hw_uart_init();
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
 }
 
diff --git a/bsp/lpc176x/drivers/board.h b/bsp/lpc176x/drivers/board.h
index 951a2c4cda..1e51e87615 100644
--- a/bsp/lpc176x/drivers/board.h
+++ b/bsp/lpc176x/drivers/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc176x/drivers/emac.c b/bsp/lpc176x/drivers/emac.c
index 27fc55397a..e4f0363626 100644
--- a/bsp/lpc176x/drivers/emac.c
+++ b/bsp/lpc176x/drivers/emac.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -11,20 +11,20 @@
 #include "lwipopts.h"
 #include 
 
-#define EMAC_PHY_AUTO		0
-#define EMAC_PHY_10MBIT		1
-#define EMAC_PHY_100MBIT	2
+#define EMAC_PHY_AUTO       0
+#define EMAC_PHY_10MBIT     1
+#define EMAC_PHY_100MBIT    2
 
 #define MAX_ADDR_LEN 6
 struct lpc17xx_emac
 {
-	/* inherit from ethernet device */
-	struct eth_device parent;
+    /* inherit from ethernet device */
+    struct eth_device parent;
 
-	rt_uint8_t phy_mode;
+    rt_uint8_t phy_mode;
 
-	/* interface address info. */
-	rt_uint8_t  dev_addr[MAX_ADDR_LEN];		/* hw address	*/
+    /* interface address info. */
+    rt_uint8_t  dev_addr[MAX_ADDR_LEN];     /* hw address   */
 };
 static struct lpc17xx_emac lpc17xx_emac_device;
 static struct rt_semaphore sem_lock;
@@ -36,40 +36,40 @@ static rt_uint16_t read_PHY (rt_uint8_t PhyReg) ;
 
 void ENET_IRQHandler(void)
 {
-	rt_uint32_t status;
+    rt_uint32_t status;
 
     /* enter interrupt */
     rt_interrupt_enter();
 
-	status = LPC_EMAC->IntStatus;
+    status = LPC_EMAC->IntStatus;
 
-	if (status & INT_RX_DONE)
-	{
-		/* Disable EMAC RxDone interrupts. */
-		LPC_EMAC->IntEnable = INT_TX_DONE;
+    if (status & INT_RX_DONE)
+    {
+        /* Disable EMAC RxDone interrupts. */
+        LPC_EMAC->IntEnable = INT_TX_DONE;
 
-		/* a frame has been received */
-		eth_device_ready(&(lpc17xx_emac_device.parent));
-	}
-	else if (status & INT_TX_DONE)
-	{
-		/* set event */
-		rt_event_send(&tx_event, 0x01);
-	}
+        /* a frame has been received */
+        eth_device_ready(&(lpc17xx_emac_device.parent));
+    }
+    else if (status & INT_TX_DONE)
+    {
+        /* set event */
+        rt_event_send(&tx_event, 0x01);
+    }
 
-	if (status & INT_RX_OVERRUN)
-	{
-		rt_kprintf("rx overrun\n");
-	}
+    if (status & INT_RX_OVERRUN)
+    {
+        rt_kprintf("rx overrun\n");
+    }
 
-	if (status & INT_TX_UNDERRUN)
-	{
-		rt_kprintf("tx underrun\n");
-	}
+    if (status & INT_TX_UNDERRUN)
+    {
+        rt_kprintf("tx underrun\n");
+    }
+
+    /* Clear the interrupt. */
+    LPC_EMAC->IntClear = status;
 
-	/* Clear the interrupt. */ 
-	LPC_EMAC->IntClear = status; 
- 
     /* leave interrupt */
     rt_interrupt_leave();
 }
@@ -77,440 +77,440 @@ void ENET_IRQHandler(void)
 /* phy write */
 static void write_PHY (rt_uint32_t PhyReg, rt_uint32_t Value)
 {
-	unsigned int tout;
+    unsigned int tout;
 
-	LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
-	LPC_EMAC->MWTD = Value;
+    LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
+    LPC_EMAC->MWTD = Value;
 
-	/* Wait utill operation completed */
-	tout = 0;
-	for (tout = 0; tout < MII_WR_TOUT; tout++)
-	{
-		if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
-		{
-			break;
-		}
-	}
+    /* Wait utill operation completed */
+    tout = 0;
+    for (tout = 0; tout < MII_WR_TOUT; tout++)
+    {
+        if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
+        {
+            break;
+        }
+    }
 }
 
 /* phy read */
 static rt_uint16_t read_PHY (rt_uint8_t PhyReg)
 {
-	rt_uint32_t tout;
+    rt_uint32_t tout;
 
-	LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
-	LPC_EMAC->MCMD = MCMD_READ;
+    LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
+    LPC_EMAC->MCMD = MCMD_READ;
 
-	/* Wait until operation completed */
-	tout = 0;
-	for (tout = 0; tout < MII_RD_TOUT; tout++)
-	{
-		if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
-		{
-			break;
-		}
-	}
-	LPC_EMAC->MCMD = 0;
-	return (LPC_EMAC->MRDD);
+    /* Wait until operation completed */
+    tout = 0;
+    for (tout = 0; tout < MII_RD_TOUT; tout++)
+    {
+        if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
+        {
+            break;
+        }
+    }
+    LPC_EMAC->MCMD = 0;
+    return (LPC_EMAC->MRDD);
 }
 
 /* init rx descriptor */
 rt_inline void rx_descr_init (void)
 {
-	rt_uint32_t i;
+    rt_uint32_t i;
 
-	for (i = 0; i < NUM_RX_FRAG; i++)
-	{
-		RX_DESC_PACKET(i)  = RX_BUF(i);
-		RX_DESC_CTRL(i)    = RCTRL_INT | (ETH_FRAG_SIZE-1);
-		RX_STAT_INFO(i)    = 0;
-		RX_STAT_HASHCRC(i) = 0;
-	}
+    for (i = 0; i < NUM_RX_FRAG; i++)
+    {
+        RX_DESC_PACKET(i)  = RX_BUF(i);
+        RX_DESC_CTRL(i)    = RCTRL_INT | (ETH_FRAG_SIZE-1);
+        RX_STAT_INFO(i)    = 0;
+        RX_STAT_HASHCRC(i) = 0;
+    }
 
-	/* Set EMAC Receive Descriptor Registers. */
-	LPC_EMAC->RxDescriptor    = RX_DESC_BASE;
-	LPC_EMAC->RxStatus        = RX_STAT_BASE;
-	LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1;
+    /* Set EMAC Receive Descriptor Registers. */
+    LPC_EMAC->RxDescriptor    = RX_DESC_BASE;
+    LPC_EMAC->RxStatus        = RX_STAT_BASE;
+    LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1;
 
-	/* Rx Descriptors Point to 0 */
-	LPC_EMAC->RxConsumeIndex  = 0;
+    /* Rx Descriptors Point to 0 */
+    LPC_EMAC->RxConsumeIndex  = 0;
 }
 
 /* init tx descriptor */
 rt_inline void tx_descr_init (void)
 {
-	rt_uint32_t i;
+    rt_uint32_t i;
 
-	for (i = 0; i < NUM_TX_FRAG; i++)
-	{
-		TX_DESC_PACKET(i) = TX_BUF(i);
-		TX_DESC_CTRL(i)   = (1ul<<31) | (1ul<<30) | (1ul<<29) | (1ul<<28) | (1ul<<26) | (ETH_FRAG_SIZE-1);
-		TX_STAT_INFO(i)   = 0;
-	}
+    for (i = 0; i < NUM_TX_FRAG; i++)
+    {
+        TX_DESC_PACKET(i) = TX_BUF(i);
+        TX_DESC_CTRL(i)   = (1ul<<31) | (1ul<<30) | (1ul<<29) | (1ul<<28) | (1ul<<26) | (ETH_FRAG_SIZE-1);
+        TX_STAT_INFO(i)   = 0;
+    }
 
-	/* Set EMAC Transmit Descriptor Registers. */
-	LPC_EMAC->TxDescriptor    = TX_DESC_BASE;
-	LPC_EMAC->TxStatus        = TX_STAT_BASE;
-	LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1;
+    /* Set EMAC Transmit Descriptor Registers. */
+    LPC_EMAC->TxDescriptor    = TX_DESC_BASE;
+    LPC_EMAC->TxStatus        = TX_STAT_BASE;
+    LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1;
 
-	/* Tx Descriptors Point to 0 */
-	LPC_EMAC->TxProduceIndex  = 0;
+    /* Tx Descriptors Point to 0 */
+    LPC_EMAC->TxProduceIndex  = 0;
 }
 
 static rt_err_t lpc17xx_emac_init(rt_device_t dev)
 {
-	/* Initialize the EMAC ethernet controller. */
-	rt_uint32_t regv, tout, id1, id2;
+    /* Initialize the EMAC ethernet controller. */
+    rt_uint32_t regv, tout, id1, id2;
 
-	/* Power Up the EMAC controller. */
-	LPC_SC->PCONP |= 0x40000000;
+    /* Power Up the EMAC controller. */
+    LPC_SC->PCONP |= 0x40000000;
 
-	/* Enable P1 Ethernet Pins. */
-	LPC_PINCON->PINSEL2 = 0x50150105;
-	LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005;
+    /* Enable P1 Ethernet Pins. */
+    LPC_PINCON->PINSEL2 = 0x50150105;
+    LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005;
 
-	/* Reset all EMAC internal modules. */
-	LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
-				 MAC1_SIM_RES | MAC1_SOFT_RES;
-	LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
+    /* Reset all EMAC internal modules. */
+    LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
+                 MAC1_SIM_RES | MAC1_SOFT_RES;
+    LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
 
-	/* A short delay after reset. */
-	for (tout = 100; tout; tout--);
+    /* A short delay after reset. */
+    for (tout = 100; tout; tout--);
 
-	/* Initialize MAC control registers. */
-	LPC_EMAC->MAC1 = MAC1_PASS_ALL;
-	LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
-	LPC_EMAC->MAXF = ETH_MAX_FLEN;
-	LPC_EMAC->CLRT = CLRT_DEF;
-	LPC_EMAC->IPGR = IPGR_DEF;
+    /* Initialize MAC control registers. */
+    LPC_EMAC->MAC1 = MAC1_PASS_ALL;
+    LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
+    LPC_EMAC->MAXF = ETH_MAX_FLEN;
+    LPC_EMAC->CLRT = CLRT_DEF;
+    LPC_EMAC->IPGR = IPGR_DEF;
 
-	/* PCLK=18MHz, clock select=6, MDC=18/6=3MHz */
-	/* Enable Reduced MII interface. */
-	LPC_EMAC->MCFG = MCFG_CLK_DIV20 | MCFG_RES_MII;
-	for (tout = 100; tout; tout--);
-	LPC_EMAC->MCFG = MCFG_CLK_DIV20;
+    /* PCLK=18MHz, clock select=6, MDC=18/6=3MHz */
+    /* Enable Reduced MII interface. */
+    LPC_EMAC->MCFG = MCFG_CLK_DIV20 | MCFG_RES_MII;
+    for (tout = 100; tout; tout--);
+    LPC_EMAC->MCFG = MCFG_CLK_DIV20;
 
-	/* Enable Reduced MII interface. */
-	LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM | CR_PASS_RX_FILT;
+    /* Enable Reduced MII interface. */
+    LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM | CR_PASS_RX_FILT;
 
-	/* Reset Reduced MII Logic. */
-	LPC_EMAC->SUPP = SUPP_RES_RMII | SUPP_SPEED;
-	for (tout = 100; tout; tout--);
-	LPC_EMAC->SUPP = SUPP_SPEED;
+    /* Reset Reduced MII Logic. */
+    LPC_EMAC->SUPP = SUPP_RES_RMII | SUPP_SPEED;
+    for (tout = 100; tout; tout--);
+    LPC_EMAC->SUPP = SUPP_SPEED;
 
-	/* Put the PHY in reset mode */
-	write_PHY (PHY_REG_BMCR, 0x8000);
-	for (tout = 1000; tout; tout--);
+    /* Put the PHY in reset mode */
+    write_PHY (PHY_REG_BMCR, 0x8000);
+    for (tout = 1000; tout; tout--);
 
-	/* Wait for hardware reset to end. */
-	for (tout = 0; tout < 10000; tout++)
-	{
-		regv = read_PHY (PHY_REG_BMCR);
-		if (!(regv & 0x8000))
-		{
-			/* Reset complete */
-			break;
-		}
-	}
-	if (tout >= 10000) 
-	{
-		//return -RT_ERROR; /* reset failed */
-		rt_kprintf("\tPHY Read PHY_REG_BMSR,Reset timeout,tout: %d.\n",tout);
-	}
+    /* Wait for hardware reset to end. */
+    for (tout = 0; tout < 10000; tout++)
+    {
+        regv = read_PHY (PHY_REG_BMCR);
+        if (!(regv & 0x8000))
+        {
+            /* Reset complete */
+            break;
+        }
+    }
+    if (tout >= 10000)
+    {
+        //return -RT_ERROR; /* reset failed */
+        rt_kprintf("\tPHY Read PHY_REG_BMSR,Reset timeout,tout: %d.\n",tout);
+    }
 
-	/* Check if this is a DP83848C PHY. */
-	id1 = read_PHY (PHY_REG_IDR1);
-	id2 = read_PHY (PHY_REG_IDR2);
+    /* Check if this is a DP83848C PHY. */
+    id1 = read_PHY (PHY_REG_IDR1);
+    id2 = read_PHY (PHY_REG_IDR2);
 
-	if (((id1 << 16) | (id2 & 0xFFF0)) != DP83848C_ID)
-	{
-	//	return -RT_ERROR;
-		rt_kprintf("\tPHY Read PHY_REG_IDRx,PHY chip isn't DP83848C,Chip ID is %d.\n",((id1 << 16) | (id2 & 0xFFF0)));
-	}
-	else
-	{
-		/* Configure the PHY device */
-		/* Configure the PHY device */
-		switch (lpc17xx_emac_device.phy_mode)
-		{
-			case EMAC_PHY_AUTO:
-				/* Use auto negotiation about the link speed. */
-				write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG);
-				/* Wait to complete Auto_Negotiation. */
-				for (tout = 0; tout < 200000; tout++)
-				{
-					regv = read_PHY (PHY_REG_BMSR);
-					if (regv & 0x0020)
-					{
-						/* Auto negotiation Complete. */
-						break;
-					}
-				}
-				if(tout >= 200000)
-		                {
-		                    rt_kprintf("\tPHY Read PHY_REG_BMSR,Auto nego timeout,tout: %d.\n",tout);
-		                }
-				break;
-			case EMAC_PHY_10MBIT:
-				/* Connect at 10MBit */
-				write_PHY (PHY_REG_BMCR, PHY_FULLD_10M);
-				break;
-			case EMAC_PHY_100MBIT:
-				/* Connect at 100MBit */
-				write_PHY (PHY_REG_BMCR, PHY_FULLD_100M);
-				break;
-		}
-	}
-	//if (tout >= 0x100000) return -RT_ERROR; // auto_neg failed
+    if (((id1 << 16) | (id2 & 0xFFF0)) != DP83848C_ID)
+    {
+    //  return -RT_ERROR;
+        rt_kprintf("\tPHY Read PHY_REG_IDRx,PHY chip isn't DP83848C,Chip ID is %d.\n",((id1 << 16) | (id2 & 0xFFF0)));
+    }
+    else
+    {
+        /* Configure the PHY device */
+        /* Configure the PHY device */
+        switch (lpc17xx_emac_device.phy_mode)
+        {
+            case EMAC_PHY_AUTO:
+                /* Use auto negotiation about the link speed. */
+                write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG);
+                /* Wait to complete Auto_Negotiation. */
+                for (tout = 0; tout < 200000; tout++)
+                {
+                    regv = read_PHY (PHY_REG_BMSR);
+                    if (regv & 0x0020)
+                    {
+                        /* Auto negotiation Complete. */
+                        break;
+                    }
+                }
+                if(tout >= 200000)
+                        {
+                            rt_kprintf("\tPHY Read PHY_REG_BMSR,Auto nego timeout,tout: %d.\n",tout);
+                        }
+                break;
+            case EMAC_PHY_10MBIT:
+                /* Connect at 10MBit */
+                write_PHY (PHY_REG_BMCR, PHY_FULLD_10M);
+                break;
+            case EMAC_PHY_100MBIT:
+                /* Connect at 100MBit */
+                write_PHY (PHY_REG_BMCR, PHY_FULLD_100M);
+                break;
+        }
+    }
+    //if (tout >= 0x100000) return -RT_ERROR; // auto_neg failed
 
-	/* Check the link status. */
-	for (tout = 0; tout < 100; tout++)
-	{
-		regv = read_PHY (PHY_REG_STS);
-		if (regv & 0x0001)
-		{
-			/* Link is on. */
-			break;
-		}
-	}
-	if (tout >= 100) 
-	{
-		//return -RT_ERROR;
-		rt_kprintf("\tPHY Read PHY_REG_BMSR,Link on timeout,tout: %d.\n",tout);
-	}
-	/* Configure Full/Half Duplex mode. */
-	if (regv & 0x0004)
-	{
-		/* Full duplex is enabled. */
-		LPC_EMAC->MAC2    |= MAC2_FULL_DUP;
-		LPC_EMAC->Command |= CR_FULL_DUP;
-		LPC_EMAC->IPGT     = IPGT_FULL_DUP;
-	}
-	else
-	{
-		/* Half duplex mode. */
-		LPC_EMAC->IPGT = IPGT_HALF_DUP;
-	}
+    /* Check the link status. */
+    for (tout = 0; tout < 100; tout++)
+    {
+        regv = read_PHY (PHY_REG_STS);
+        if (regv & 0x0001)
+        {
+            /* Link is on. */
+            break;
+        }
+    }
+    if (tout >= 100)
+    {
+        //return -RT_ERROR;
+        rt_kprintf("\tPHY Read PHY_REG_BMSR,Link on timeout,tout: %d.\n",tout);
+    }
+    /* Configure Full/Half Duplex mode. */
+    if (regv & 0x0004)
+    {
+        /* Full duplex is enabled. */
+        LPC_EMAC->MAC2    |= MAC2_FULL_DUP;
+        LPC_EMAC->Command |= CR_FULL_DUP;
+        LPC_EMAC->IPGT     = IPGT_FULL_DUP;
+    }
+    else
+    {
+        /* Half duplex mode. */
+        LPC_EMAC->IPGT = IPGT_HALF_DUP;
+    }
 
-	/* Configure 100MBit/10MBit mode. */
-	if (regv & 0x0002)
-	{
-		/* 10MBit mode. */
-		LPC_EMAC->SUPP = 0;
-	}
-	else
-	{
-		/* 100MBit mode. */
-		LPC_EMAC->SUPP = SUPP_SPEED;
-	}
+    /* Configure 100MBit/10MBit mode. */
+    if (regv & 0x0002)
+    {
+        /* 10MBit mode. */
+        LPC_EMAC->SUPP = 0;
+    }
+    else
+    {
+        /* 100MBit mode. */
+        LPC_EMAC->SUPP = SUPP_SPEED;
+    }
 
-	/* Set the Ethernet MAC Address registers */
-	LPC_EMAC->SA0 = (lpc17xx_emac_device.dev_addr[1]<<8) | lpc17xx_emac_device.dev_addr[0];
-	LPC_EMAC->SA1 = (lpc17xx_emac_device.dev_addr[3]<<8) | lpc17xx_emac_device.dev_addr[2];
-	LPC_EMAC->SA2 = (lpc17xx_emac_device.dev_addr[5]<<8) | lpc17xx_emac_device.dev_addr[4];
+    /* Set the Ethernet MAC Address registers */
+    LPC_EMAC->SA0 = (lpc17xx_emac_device.dev_addr[1]<<8) | lpc17xx_emac_device.dev_addr[0];
+    LPC_EMAC->SA1 = (lpc17xx_emac_device.dev_addr[3]<<8) | lpc17xx_emac_device.dev_addr[2];
+    LPC_EMAC->SA2 = (lpc17xx_emac_device.dev_addr[5]<<8) | lpc17xx_emac_device.dev_addr[4];
 
-	/* Initialize Tx and Rx DMA Descriptors */
-	rx_descr_init ();
-	tx_descr_init ();
+    /* Initialize Tx and Rx DMA Descriptors */
+    rx_descr_init ();
+    tx_descr_init ();
 
-	/* Receive Broadcast and Perfect Match Packets */
-	LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN;
+    /* Receive Broadcast and Perfect Match Packets */
+    LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN;
 
-	/* Reset all interrupts */
-	LPC_EMAC->IntClear  = 0xFFFF;
+    /* Reset all interrupts */
+    LPC_EMAC->IntClear  = 0xFFFF;
 
-	/* Enable EMAC interrupts. */
-	LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
+    /* Enable EMAC interrupts. */
+    LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
 
-	/* Enable receive and transmit mode of MAC Ethernet core */
-	LPC_EMAC->Command  |= (CR_RX_EN | CR_TX_EN);
-	LPC_EMAC->MAC1     |= MAC1_REC_EN;
+    /* Enable receive and transmit mode of MAC Ethernet core */
+    LPC_EMAC->Command  |= (CR_RX_EN | CR_TX_EN);
+    LPC_EMAC->MAC1     |= MAC1_REC_EN;
 
-	/* Enable the ENET Interrupt */
-	NVIC_EnableIRQ(ENET_IRQn);
+    /* Enable the ENET Interrupt */
+    NVIC_EnableIRQ(ENET_IRQn);
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t lpc17xx_emac_open(rt_device_t dev, rt_uint16_t oflag)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t lpc17xx_emac_close(rt_device_t dev)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_size_t lpc17xx_emac_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
 {
-	rt_set_errno(-RT_ENOSYS);
-	return 0;
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
 }
 
 static rt_size_t lpc17xx_emac_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
 {
-	rt_set_errno(-RT_ENOSYS);
-	return 0;
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
 }
 
 static rt_err_t lpc17xx_emac_control(rt_device_t dev, int cmd, void *args)
 {
-	switch (cmd)
-	{
-	case NIOCTL_GADDR:
-		/* get mac address */
-		if (args) rt_memcpy(args, lpc17xx_emac_device.dev_addr, 6);
-		else return -RT_ERROR;
-		break;
+    switch (cmd)
+    {
+    case NIOCTL_GADDR:
+        /* get mac address */
+        if (args) rt_memcpy(args, lpc17xx_emac_device.dev_addr, 6);
+        else return -RT_ERROR;
+        break;
 
-	default :
-		break;
-	}
+    default :
+        break;
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 /* EtherNet Device Interface */
 /* transmit packet. */
 rt_err_t lpc17xx_emac_tx( rt_device_t dev, struct pbuf* p)
 {
-	rt_uint32_t Index, IndexNext;
-	struct pbuf *q;
-	rt_uint8_t *ptr;
+    rt_uint32_t Index, IndexNext;
+    struct pbuf *q;
+    rt_uint8_t *ptr;
 
-	/* calculate next index */
-	IndexNext = LPC_EMAC->TxProduceIndex + 1;
-	if(IndexNext > LPC_EMAC->TxDescriptorNumber) IndexNext = 0;
+    /* calculate next index */
+    IndexNext = LPC_EMAC->TxProduceIndex + 1;
+    if(IndexNext > LPC_EMAC->TxDescriptorNumber) IndexNext = 0;
 
-	/* check whether block is full */
-	while (IndexNext == LPC_EMAC->TxConsumeIndex)
-	{
-		rt_err_t result;
-		rt_uint32_t recved;
-		
-		/* there is no block yet, wait a flag */
-		result = rt_event_recv(&tx_event, 0x01, 
-			RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &recved);
+    /* check whether block is full */
+    while (IndexNext == LPC_EMAC->TxConsumeIndex)
+    {
+        rt_err_t result;
+        rt_uint32_t recved;
 
-		RT_ASSERT(result == RT_EOK);
-	}
+        /* there is no block yet, wait a flag */
+        result = rt_event_recv(&tx_event, 0x01,
+            RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &recved);
 
-	/* lock EMAC device */
-	rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
+        RT_ASSERT(result == RT_EOK);
+    }
 
-	/* get produce index */
-	Index = LPC_EMAC->TxProduceIndex;
+    /* lock EMAC device */
+    rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
 
-	/* calculate next index */
-	IndexNext = LPC_EMAC->TxProduceIndex + 1;
-	if(IndexNext > LPC_EMAC->TxDescriptorNumber)
-		IndexNext = 0;
+    /* get produce index */
+    Index = LPC_EMAC->TxProduceIndex;
 
-	/* copy data to tx buffer */
-	q = p;
-	ptr = (rt_uint8_t*)TX_BUF(Index);
-	while (q)
-	{
-		memcpy(ptr, q->payload, q->len);
-		ptr += q->len;
-		q = q->next;
-	}
+    /* calculate next index */
+    IndexNext = LPC_EMAC->TxProduceIndex + 1;
+    if(IndexNext > LPC_EMAC->TxDescriptorNumber)
+        IndexNext = 0;
 
-	TX_DESC_CTRL(Index) &= ~0x7ff;
-	TX_DESC_CTRL(Index) |= (p->tot_len - 1) & 0x7ff;
+    /* copy data to tx buffer */
+    q = p;
+    ptr = (rt_uint8_t*)TX_BUF(Index);
+    while (q)
+    {
+        memcpy(ptr, q->payload, q->len);
+        ptr += q->len;
+        q = q->next;
+    }
 
-	/* change index to the next */
-	LPC_EMAC->TxProduceIndex = IndexNext;
+    TX_DESC_CTRL(Index) &= ~0x7ff;
+    TX_DESC_CTRL(Index) |= (p->tot_len - 1) & 0x7ff;
 
-	/* unlock EMAC device */
-	rt_sem_release(&sem_lock);
+    /* change index to the next */
+    LPC_EMAC->TxProduceIndex = IndexNext;
 
-	return RT_EOK;
+    /* unlock EMAC device */
+    rt_sem_release(&sem_lock);
+
+    return RT_EOK;
 }
 
 /* reception packet. */
 struct pbuf *lpc17xx_emac_rx(rt_device_t dev)
 {
-	struct pbuf* p;
-	rt_uint32_t size;
-	rt_uint32_t Index;
+    struct pbuf* p;
+    rt_uint32_t size;
+    rt_uint32_t Index;
 
-	/* init p pointer */
-	p = RT_NULL;
+    /* init p pointer */
+    p = RT_NULL;
 
-	/* lock EMAC device */
-	rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
+    /* lock EMAC device */
+    rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
 
-	Index = LPC_EMAC->RxConsumeIndex;
-	if(Index != LPC_EMAC->RxProduceIndex)
-	{
-		size = (RX_STAT_INFO(Index) & 0x7ff)+1;
-		if (size > ETH_FRAG_SIZE) size = ETH_FRAG_SIZE;
+    Index = LPC_EMAC->RxConsumeIndex;
+    if(Index != LPC_EMAC->RxProduceIndex)
+    {
+        size = (RX_STAT_INFO(Index) & 0x7ff)+1;
+        if (size > ETH_FRAG_SIZE) size = ETH_FRAG_SIZE;
 
-		/* allocate buffer */
-		p = pbuf_alloc(PBUF_LINK, size, PBUF_RAM);
-		if (p != RT_NULL)
-		{
-			struct pbuf* q;
-			rt_uint8_t *ptr;
+        /* allocate buffer */
+        p = pbuf_alloc(PBUF_LINK, size, PBUF_RAM);
+        if (p != RT_NULL)
+        {
+            struct pbuf* q;
+            rt_uint8_t *ptr;
 
-			ptr = (rt_uint8_t*)RX_BUF(Index);
-			for (q = p; q != RT_NULL; q= q->next)
-			{
-				memcpy(q->payload, ptr, q->len);
-				ptr += q->len;
-			}
-		}
-		
-		/* move Index to the next */
-		if(++Index > LPC_EMAC->RxDescriptorNumber)
-			Index = 0;
+            ptr = (rt_uint8_t*)RX_BUF(Index);
+            for (q = p; q != RT_NULL; q= q->next)
+            {
+                memcpy(q->payload, ptr, q->len);
+                ptr += q->len;
+            }
+        }
 
-		/* set consume index */
-		LPC_EMAC->RxConsumeIndex = Index;
-	}
-	else
-	{
-		/* Enable RxDone interrupt */
-		LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
-	}
+        /* move Index to the next */
+        if(++Index > LPC_EMAC->RxDescriptorNumber)
+            Index = 0;
 
-	/* unlock EMAC device */
-	rt_sem_release(&sem_lock);
+        /* set consume index */
+        LPC_EMAC->RxConsumeIndex = Index;
+    }
+    else
+    {
+        /* Enable RxDone interrupt */
+        LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
+    }
 
-	return p;
+    /* unlock EMAC device */
+    rt_sem_release(&sem_lock);
+
+    return p;
 }
 
 int lpc17xx_emac_hw_init(void)
 {
-	rt_event_init(&tx_event, "tx_event", RT_IPC_FLAG_FIFO);
-	rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
+    rt_event_init(&tx_event, "tx_event", RT_IPC_FLAG_FIFO);
+    rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
 
-	/* set auto negotiation mode */
-	lpc17xx_emac_device.phy_mode = EMAC_PHY_AUTO;
+    /* set auto negotiation mode */
+    lpc17xx_emac_device.phy_mode = EMAC_PHY_AUTO;
 
-	// OUI 00-60-37 NXP Semiconductors
-	lpc17xx_emac_device.dev_addr[0] = 0x00;
-	lpc17xx_emac_device.dev_addr[1] = 0x60;
-	lpc17xx_emac_device.dev_addr[2] = 0x37;
-	/* set mac address: (only for test) */
-	lpc17xx_emac_device.dev_addr[3] = 0x12;
-	lpc17xx_emac_device.dev_addr[4] = 0x34;
-	lpc17xx_emac_device.dev_addr[5] = 0x56;
+    // OUI 00-60-37 NXP Semiconductors
+    lpc17xx_emac_device.dev_addr[0] = 0x00;
+    lpc17xx_emac_device.dev_addr[1] = 0x60;
+    lpc17xx_emac_device.dev_addr[2] = 0x37;
+    /* set mac address: (only for test) */
+    lpc17xx_emac_device.dev_addr[3] = 0x12;
+    lpc17xx_emac_device.dev_addr[4] = 0x34;
+    lpc17xx_emac_device.dev_addr[5] = 0x56;
 
-	lpc17xx_emac_device.parent.parent.init		= lpc17xx_emac_init;
-	lpc17xx_emac_device.parent.parent.open		= lpc17xx_emac_open;
-	lpc17xx_emac_device.parent.parent.close		= lpc17xx_emac_close;
-	lpc17xx_emac_device.parent.parent.read		= lpc17xx_emac_read;
-	lpc17xx_emac_device.parent.parent.write		= lpc17xx_emac_write;
-	lpc17xx_emac_device.parent.parent.control	= lpc17xx_emac_control;
-	lpc17xx_emac_device.parent.parent.user_data	= RT_NULL;
+    lpc17xx_emac_device.parent.parent.init      = lpc17xx_emac_init;
+    lpc17xx_emac_device.parent.parent.open      = lpc17xx_emac_open;
+    lpc17xx_emac_device.parent.parent.close     = lpc17xx_emac_close;
+    lpc17xx_emac_device.parent.parent.read      = lpc17xx_emac_read;
+    lpc17xx_emac_device.parent.parent.write     = lpc17xx_emac_write;
+    lpc17xx_emac_device.parent.parent.control   = lpc17xx_emac_control;
+    lpc17xx_emac_device.parent.parent.user_data = RT_NULL;
 
-	lpc17xx_emac_device.parent.eth_rx			= lpc17xx_emac_rx;
-	lpc17xx_emac_device.parent.eth_tx			= lpc17xx_emac_tx;
+    lpc17xx_emac_device.parent.eth_rx           = lpc17xx_emac_rx;
+    lpc17xx_emac_device.parent.eth_tx           = lpc17xx_emac_tx;
 
-	eth_device_init(&(lpc17xx_emac_device.parent), "e0");
-	return 0;
+    eth_device_init(&(lpc17xx_emac_device.parent), "e0");
+    return 0;
 }
 INIT_DEVICE_EXPORT(lpc17xx_emac_hw_init);
diff --git a/bsp/lpc176x/drivers/emac.h b/bsp/lpc176x/drivers/emac.h
index d0edd25d63..1fc8973249 100644
--- a/bsp/lpc176x/drivers/emac.h
+++ b/bsp/lpc176x/drivers/emac.h
@@ -1,3 +1,12 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
 #ifndef __LPC17XX_EMAC_H
 #define __LPC17XX_EMAC_H
 
@@ -11,7 +20,7 @@
 #define ETH_MAX_FLEN        1536        /* Max. Ethernet Frame Size          */
 
 /* EMAC variables located in 16K Ethernet SRAM */
-#define RX_DESC_BASE		0x20080000
+#define RX_DESC_BASE        0x20080000
 #define RX_STAT_BASE        (RX_DESC_BASE + NUM_RX_FRAG*8)
 #define TX_DESC_BASE        (RX_STAT_BASE + NUM_RX_FRAG*8)
 #define TX_STAT_BASE        (TX_DESC_BASE + NUM_TX_FRAG*8)
diff --git a/bsp/lpc176x/drivers/led.h b/bsp/lpc176x/drivers/led.h
index 658ed16d1c..92f6ff4ffd 100644
--- a/bsp/lpc176x/drivers/led.h
+++ b/bsp/lpc176x/drivers/led.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc176x/drivers/sd.c b/bsp/lpc176x/drivers/sd.c
index 61e34ba43a..53b57676de 100644
--- a/bsp/lpc176x/drivers/sd.c
+++ b/bsp/lpc176x/drivers/sd.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -467,12 +467,12 @@ static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args)
     if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME)
     {
         struct rt_device_blk_geometry *geometry;
-        
+
         geometry = (struct rt_device_blk_geometry *)args;
-        
+
         if (geometry == RT_NULL) return -RT_ERROR;
         if (dev->user_data == RT_NULL) return -RT_ERROR;
-        
+
         geometry->bytes_per_sector = ((SDCFG *)dev->user_data)->sectorsize;
         geometry->block_size = ((SDCFG *)dev->user_data)->blocksize;
         geometry->sector_count = ((SDCFG *)dev->user_data)->sectorcnt;
diff --git a/bsp/lpc176x/drivers/spi.c b/bsp/lpc176x/drivers/spi.c
index a6561195c5..ef328bc793 100644
--- a/bsp/lpc176x/drivers/spi.c
+++ b/bsp/lpc176x/drivers/spi.c
@@ -1,3 +1,12 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
 #include "LPC17xx.h"                              /* LPC17xx definitions    */
 #include "spi.h"
 
@@ -21,98 +30,98 @@ static uint8_t LPC17xx_SPI_SendRecvByte (uint8_t byte_s);
 /* Initialize the SSP0, SSP0_PCLK=CCLK=72MHz */
 void LPC17xx_SPI_Init (void)
 {
-	uint32_t dummy;
+    uint32_t dummy;
 
-	dummy = dummy; // avoid warning
+    dummy = dummy; // avoid warning
 
 #if 0
-	/* Initialize and enable the SSP0 Interface module. */
-	LPC_SC->PCONP |= (1 << 21);          /* Enable power to SSPI0 block  */
+    /* Initialize and enable the SSP0 Interface module. */
+    LPC_SC->PCONP |= (1 << 21);          /* Enable power to SSPI0 block  */
 
-	/* SSEL is GPIO, output set to high. */
-	LPC_GPIO0->FIODIR  |=  (1<<16);             /* P0.16 is output */
-	LPC_PINCON->PINSEL1 &= ~(3<<0);             /* P0.16 SSEL (used as GPIO) */
-	LPC17xx_SPI_DeSelect ();					/* set P0.16 high (SSEL inactiv) */
+    /* SSEL is GPIO, output set to high. */
+    LPC_GPIO0->FIODIR  |=  (1<<16);             /* P0.16 is output */
+    LPC_PINCON->PINSEL1 &= ~(3<<0);             /* P0.16 SSEL (used as GPIO) */
+    LPC17xx_SPI_DeSelect ();                    /* set P0.16 high (SSEL inactiv) */
 
-	/* SCK, MISO, MOSI are SSP pins. */
-	LPC_PINCON->PINSEL0 &= ~(3UL<<30);          /* P0.15 cleared */
-	LPC_PINCON->PINSEL0 |=  (2UL<<30);          /* P0.15 SCK0 */
-	LPC_PINCON->PINSEL1 &= ~((3<<2) | (3<<4));  /* P0.17, P0.18 cleared */
-	LPC_PINCON->PINSEL1 |=  ((2<<2) | (2<<4));  /* P0.17 MISO0, P0.18 MOSI0 */
+    /* SCK, MISO, MOSI are SSP pins. */
+    LPC_PINCON->PINSEL0 &= ~(3UL<<30);          /* P0.15 cleared */
+    LPC_PINCON->PINSEL0 |=  (2UL<<30);          /* P0.15 SCK0 */
+    LPC_PINCON->PINSEL1 &= ~((3<<2) | (3<<4));  /* P0.17, P0.18 cleared */
+    LPC_PINCON->PINSEL1 |=  ((2<<2) | (2<<4));  /* P0.17 MISO0, P0.18 MOSI0 */
 #else
-	LPC_SC->PCONP       |= (1 << 21);           /* Enable power to SSPI0 block */
+    LPC_SC->PCONP       |= (1 << 21);           /* Enable power to SSPI0 block */
 
-	/* SSEL is GPIO, output set to high. */
-	LPC_GPIO1->FIODIR   |=  (1<<21);            /* P1.21 is output             */
-	LPC_GPIO1->FIOPIN   |=  (1<<21);            /* set P1.21 high (SSEL inact.)*/
-	LPC_PINCON->PINSEL3 &= ~(0<<10);             /* P1.21 SSEL (used as GPIO)   */
+    /* SSEL is GPIO, output set to high. */
+    LPC_GPIO1->FIODIR   |=  (1<<21);            /* P1.21 is output             */
+    LPC_GPIO1->FIOPIN   |=  (1<<21);            /* set P1.21 high (SSEL inact.)*/
+    LPC_PINCON->PINSEL3 &= ~(0<<10);             /* P1.21 SSEL (used as GPIO)   */
 
-	/* P3.26 is SD Card Power Supply Enable Pin */
-	LPC_GPIO3->FIODIR   |=  (1<<26);            /* P3.26 is output             */
-	LPC_GPIO3->FIOPIN   &= ~(1<<26);            /* set P3.26 low(enable power) */
+    /* P3.26 is SD Card Power Supply Enable Pin */
+    LPC_GPIO3->FIODIR   |=  (1<<26);            /* P3.26 is output             */
+    LPC_GPIO3->FIOPIN   &= ~(1<<26);            /* set P3.26 low(enable power) */
 
-	/* SCK, MISO, MOSI are SSP pins. */
-	LPC_PINCON->PINSEL3 &= ~(3UL<<8);          /* P1.20 cleared               */
-	LPC_PINCON->PINSEL3 |=  (3UL<<8);          /* P1.20 SCK0                  */
-	LPC_PINCON->PINSEL3 &= ~((3<<14) | (3<<16));  /* P1.23, P1.24 cleared        */
-	LPC_PINCON->PINSEL3 |=  ((3<<14) | (3<<16));  /* P1.23 MISO0, P1.24 MOSI0    */
+    /* SCK, MISO, MOSI are SSP pins. */
+    LPC_PINCON->PINSEL3 &= ~(3UL<<8);          /* P1.20 cleared               */
+    LPC_PINCON->PINSEL3 |=  (3UL<<8);          /* P1.20 SCK0                  */
+    LPC_PINCON->PINSEL3 &= ~((3<<14) | (3<<16));  /* P1.23, P1.24 cleared        */
+    LPC_PINCON->PINSEL3 |=  ((3<<14) | (3<<16));  /* P1.23 MISO0, P1.24 MOSI0    */
 #endif
 
-	/* PCLK_SSP0=CCLK */
-	LPC_SC->PCLKSEL1 &= ~(3<<10);               /* PCLKSP0 = CCLK/4 (18MHz) */
-	LPC_SC->PCLKSEL1 |=  (1<<10);               /* PCLKSP0 = CCLK   (72MHz) */
+    /* PCLK_SSP0=CCLK */
+    LPC_SC->PCLKSEL1 &= ~(3<<10);               /* PCLKSP0 = CCLK/4 (18MHz) */
+    LPC_SC->PCLKSEL1 |=  (1<<10);               /* PCLKSP0 = CCLK   (72MHz) */
 
-	LPC_SSP0->CR0  = 0x0007;                    /* 8Bit, CPOL=0, CPHA=0         */
-	LPC_SSP0->CR1  = 0x0002;                    /* SSP0 enable, master          */
+    LPC_SSP0->CR0  = 0x0007;                    /* 8Bit, CPOL=0, CPHA=0         */
+    LPC_SSP0->CR1  = 0x0002;                    /* SSP0 enable, master          */
 
-	LPC17xx_SPI_SetSpeed (SPI_SPEED_400kHz);
+    LPC17xx_SPI_SetSpeed (SPI_SPEED_400kHz);
 
-	/* wait for busy gone */
-	while( LPC_SSP0->SR & ( 1 << SSPSR_BSY ) );
+    /* wait for busy gone */
+    while( LPC_SSP0->SR & ( 1 << SSPSR_BSY ) );
 
-	/* drain SPI RX FIFO */
-	while( LPC_SSP0->SR & ( 1 << SSPSR_RNE ) )
-	{
-		dummy = LPC_SSP0->DR;
-	}
+    /* drain SPI RX FIFO */
+    while( LPC_SSP0->SR & ( 1 << SSPSR_RNE ) )
+    {
+        dummy = LPC_SSP0->DR;
+    }
 }
 
 /* Close SSP0 */
 void LPC17xx_SPI_DeInit( void )
 {
-	// disable SPI
-	LPC_SSP0->CR1  = 0;
+    // disable SPI
+    LPC_SSP0->CR1  = 0;
 
 #if 0
-	// Pins to GPIO
-	LPC_PINCON->PINSEL0 &= ~(3UL<<30);
-	LPC_PINCON->PINSEL1 &= ~((3<<2) | (3<<4));
+    // Pins to GPIO
+    LPC_PINCON->PINSEL0 &= ~(3UL<<30);
+    LPC_PINCON->PINSEL1 &= ~((3<<2) | (3<<4));
 #else
-	LPC_PINCON->PINSEL3 &= ~(3UL<<8);          /* P1.20 cleared               */
-	LPC_PINCON->PINSEL3 &= ~((3<<14) | (3<<16));  /* P1.23, P1.24 cleared        */
+    LPC_PINCON->PINSEL3 &= ~(3UL<<8);          /* P1.20 cleared               */
+    LPC_PINCON->PINSEL3 &= ~((3<<14) | (3<<16));  /* P1.23, P1.24 cleared        */
 #endif
 
-	// disable SSP power
-	LPC_SC->PCONP &= ~(1 << 21);
+    // disable SSP power
+    LPC_SC->PCONP &= ~(1 << 21);
 }
 
 /* Set a SSP0 clock speed to desired value. */
 void LPC17xx_SPI_SetSpeed (uint8_t speed)
 {
-	speed &= 0xFE;
-	if ( speed < 2  ) {
-		speed = 2 ;
-	}
-	LPC_SSP0->CPSR = speed;
+    speed &= 0xFE;
+    if ( speed < 2  ) {
+        speed = 2 ;
+    }
+    LPC_SSP0->CPSR = speed;
 }
 
 /* SSEL: low */
 void LPC17xx_SPI_Select ()
 {
 #if 0
-	LPC_GPIO0->FIOPIN &= ~(1<<16);
+    LPC_GPIO0->FIOPIN &= ~(1<<16);
 #else
-	LPC_GPIO1->FIOPIN &= ~(1<<21);            /* SSEL is GPIO, set to high.  */
+    LPC_GPIO1->FIOPIN &= ~(1<<21);            /* SSEL is GPIO, set to high.  */
 #endif
 }
 
@@ -120,41 +129,41 @@ void LPC17xx_SPI_Select ()
 void LPC17xx_SPI_DeSelect ()
 {
 #if 0
-	LPC_GPIO0->FIOPIN |= (1<<16);
+    LPC_GPIO0->FIOPIN |= (1<<16);
 #else
-	LPC_GPIO1->FIOPIN |= (1<<21);             /* SSEL is GPIO, set to high.  */
+    LPC_GPIO1->FIOPIN |= (1<<21);             /* SSEL is GPIO, set to high.  */
 #endif
 }
 
 /* Send one byte then recv one byte of response. */
 static uint8_t LPC17xx_SPI_SendRecvByte (uint8_t byte_s)
 {
-	uint8_t byte_r;
+    uint8_t byte_r;
 
-	LPC_SSP0->DR = byte_s;
-	while (LPC_SSP0->SR & (1 << SSPSR_BSY) /*BSY*/); 	/* Wait for transfer to finish */
-	byte_r = LPC_SSP0->DR;
+    LPC_SSP0->DR = byte_s;
+    while (LPC_SSP0->SR & (1 << SSPSR_BSY) /*BSY*/);    /* Wait for transfer to finish */
+    byte_r = LPC_SSP0->DR;
 
-	return byte_r;                      /* Return received value */
+    return byte_r;                      /* Return received value */
 }
 
 /* Send one byte */
 void LPC17xx_SPI_SendByte (uint8_t data)
 {
-	LPC17xx_SPI_SendRecvByte (data);
+    LPC17xx_SPI_SendRecvByte (data);
 }
 
 /* Recv one byte */
 uint8_t LPC17xx_SPI_RecvByte ()
 {
-	return LPC17xx_SPI_SendRecvByte (0xFF);
+    return LPC17xx_SPI_SendRecvByte (0xFF);
 }
 
 /* Release SSP0 */
 void LPC17xx_SPI_Release (void)
 {
-	LPC17xx_SPI_DeSelect ();
-	LPC17xx_SPI_RecvByte ();
+    LPC17xx_SPI_DeSelect ();
+    LPC17xx_SPI_RecvByte ();
 }
 
 
@@ -163,66 +172,66 @@ void LPC17xx_SPI_Release (void)
 #define FIFO_ELEM 8
 
 /* Receive btr (must be multiple of 4) bytes of data and store in buff. */
-void LPC17xx_SPI_RecvBlock_FIFO (uint8_t *buff,	uint32_t btr)
+void LPC17xx_SPI_RecvBlock_FIFO (uint8_t *buff, uint32_t btr)
 {
-	uint32_t hwtr, startcnt, i, rec;
+    uint32_t hwtr, startcnt, i, rec;
 
-	hwtr = btr/2;  /* byte number in unit of short */
-	if ( btr < FIFO_ELEM ) {
-		startcnt = hwtr;
-	} else {
-		startcnt = FIFO_ELEM;
-	}
+    hwtr = btr/2;  /* byte number in unit of short */
+    if ( btr < FIFO_ELEM ) {
+        startcnt = hwtr;
+    } else {
+        startcnt = FIFO_ELEM;
+    }
 
-	LPC_SSP0 -> CR0 |= 0x0f;  /* DSS to 16 bit */
+    LPC_SSP0 -> CR0 |= 0x0f;  /* DSS to 16 bit */
 
-	for ( i = startcnt; i; i-- ) {
-		LPC_SSP0 -> DR = 0xffff;  /* fill TX FIFO, prepare clk for receive */
-	}
+    for ( i = startcnt; i; i-- ) {
+        LPC_SSP0 -> DR = 0xffff;  /* fill TX FIFO, prepare clk for receive */
+    }
 
-	do {
-		while ( !(LPC_SSP0->SR & ( 1 << SSPSR_RNE ) ) ) {
-			// wait for data in RX FIFO (RNE set)
-		}
-		rec = LPC_SSP0->DR;
-		if ( i < ( hwtr - startcnt ) ) {
-			LPC_SSP0->DR = 0xffff;	/* fill TX FIFO, prepare clk for receive */
-		}
-		*buff++ = (uint8_t)(rec>>8);
-		*buff++ = (uint8_t)(rec);
-		i++;
-	} while ( i < hwtr );
+    do {
+        while ( !(LPC_SSP0->SR & ( 1 << SSPSR_RNE ) ) ) {
+            // wait for data in RX FIFO (RNE set)
+        }
+        rec = LPC_SSP0->DR;
+        if ( i < ( hwtr - startcnt ) ) {
+            LPC_SSP0->DR = 0xffff;  /* fill TX FIFO, prepare clk for receive */
+        }
+        *buff++ = (uint8_t)(rec>>8);
+        *buff++ = (uint8_t)(rec);
+        i++;
+    } while ( i < hwtr );
 
-	LPC_SSP0->CR0 &= ~0x08;  /* DSS to 8 bit */
+    LPC_SSP0->CR0 &= ~0x08;  /* DSS to 8 bit */
 }
 
 /* Send 512 bytes of data block (stored in buff). */
 void LPC17xx_SPI_SendBlock_FIFO (const uint8_t *buff)
 {
-	uint32_t cnt;
-	uint16_t data;
+    uint32_t cnt;
+    uint16_t data;
 
-	LPC_SSP0->CR0 |= 0x0f;  /* DSS to 16 bit */
+    LPC_SSP0->CR0 |= 0x0f;  /* DSS to 16 bit */
 
-	/* fill the FIFO unless it is full */
-	for ( cnt = 0; cnt < ( 512 / 2 ); cnt++ )
-	{
-		/* wait for TX FIFO not full (TNF) */
-		while ( !( LPC_SSP0->SR & ( 1 << SSPSR_TNF ) ) );
+    /* fill the FIFO unless it is full */
+    for ( cnt = 0; cnt < ( 512 / 2 ); cnt++ )
+    {
+        /* wait for TX FIFO not full (TNF) */
+        while ( !( LPC_SSP0->SR & ( 1 << SSPSR_TNF ) ) );
 
-		data  = (*buff++) << 8;
-		data |= *buff++;
-		LPC_SSP0->DR = data;
-	}
+        data  = (*buff++) << 8;
+        data |= *buff++;
+        LPC_SSP0->DR = data;
+    }
 
-	/* wait for BSY gone */
-	while ( LPC_SSP0->SR & ( 1 << SSPSR_BSY ) );
+    /* wait for BSY gone */
+    while ( LPC_SSP0->SR & ( 1 << SSPSR_BSY ) );
 
-	/* drain receive FIFO */
-	while ( LPC_SSP0->SR & ( 1 << SSPSR_RNE ) ) {
-		data = LPC_SSP0->DR;
-	}
+    /* drain receive FIFO */
+    while ( LPC_SSP0->SR & ( 1 << SSPSR_RNE ) ) {
+        data = LPC_SSP0->DR;
+    }
 
-	LPC_SSP0->CR0 &= ~0x08;  /* DSS to 8 bit */
+    LPC_SSP0->CR0 &= ~0x08;  /* DSS to 8 bit */
 }
 #endif /* USE_FIFO */
diff --git a/bsp/lpc176x/drivers/spi.h b/bsp/lpc176x/drivers/spi.h
index d1d9c14732..bad75d38b4 100644
--- a/bsp/lpc176x/drivers/spi.h
+++ b/bsp/lpc176x/drivers/spi.h
@@ -1,17 +1,26 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
 #ifndef __LPC17XX_SPI_H__
 #define __LPC17XX_SPI_H__
 
 #include 
 #include 
 
-// if not use FIFO, 	R: 600kB/s, W: 500kB/s
-// if     use FIFO,   	R: 1.2MB/s, W: 800kB/s
+// if not use FIFO,     R: 600kB/s, W: 500kB/s
+// if     use FIFO,     R: 1.2MB/s, W: 800kB/s
 #define USE_FIFO        1
 
-/* bit-frequency = PCLK / (CPSDVSR * [SCR+1]), here SCR=0, PCLK=72MHz, must be even	*/
-#define SPI_SPEED_20MHz		4	/* => 18MHz */
-#define SPI_SPEED_25MHz		4	/* => 18MHz */
-#define SPI_SPEED_400kHz  180	/* => 400kHz */
+/* bit-frequency = PCLK / (CPSDVSR * [SCR+1]), here SCR=0, PCLK=72MHz, must be even */
+#define SPI_SPEED_20MHz     4   /* => 18MHz */
+#define SPI_SPEED_25MHz     4   /* => 18MHz */
+#define SPI_SPEED_400kHz  180   /* => 400kHz */
 
 /* external functions */
 void LPC17xx_SPI_Init (void);
@@ -24,8 +33,8 @@ void LPC17xx_SPI_SendByte (uint8_t data);
 uint8_t LPC17xx_SPI_RecvByte (void);
 
 #if USE_FIFO
-void LPC17xx_SPI_RecvBlock_FIFO (uint8_t *buff,	uint32_t btr);
+void LPC17xx_SPI_RecvBlock_FIFO (uint8_t *buff, uint32_t btr);
 void LPC17xx_SPI_SendBlock_FIFO (const uint8_t *buff);
 #endif
 
-#endif	// __LPC17XX_SPI_H__
+#endif  // __LPC17XX_SPI_H__
diff --git a/bsp/lpc176x/drivers/uart.c b/bsp/lpc176x/drivers/uart.c
index 231eccb10a..a32952124b 100644
--- a/bsp/lpc176x/drivers/uart.c
+++ b/bsp/lpc176x/drivers/uart.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -56,8 +56,8 @@ void UART0_IRQHandler(void)
 {
     rt_ubase_t level, iir;
     struct rt_uart_lpc *uart = &uart_device;
-	/* enter interrupt */ 
- 	rt_interrupt_enter();
+    /* enter interrupt */
+    rt_interrupt_enter();
     /* read IIR and clear it */
     iir = LPC_UART->IIR;
 
@@ -91,8 +91,8 @@ void UART0_IRQHandler(void)
     {
         iir = LPC_UART->LSR;    //oe pe fe oe read for clear interrupt
     }
-	/* leave interrupt */ 
- 	rt_interrupt_leave();
+    /* leave interrupt */
+    rt_interrupt_leave();
     return;
 }
 
diff --git a/bsp/lpc176x/rtconfig.h b/bsp/lpc176x/rtconfig.h
index 6b28d64d32..5096b2f71d 100644
--- a/bsp/lpc176x/rtconfig.h
+++ b/bsp/lpc176x/rtconfig.h
@@ -4,17 +4,17 @@
 // 
 
 // 
-#define RT_NAME_MAX	6
+#define RT_NAME_MAX 6
 // 
-#define RT_ALIGN_SIZE	4
+#define RT_ALIGN_SIZE   4
 // 
 // 8
 // 32
 // 256
 // 
-#define RT_THREAD_PRIORITY_MAX	32
+#define RT_THREAD_PRIORITY_MAX  32
 // 
-#define RT_TICK_PER_SECOND	100
+#define RT_TICK_PER_SECOND  100
 // 

 #define RT_DEBUG
 #define RT_DEBUG_COLOR
@@ -29,11 +29,11 @@
 // 

 // #define RT_USING_TIMER_SOFT
 // 
-#define RT_TIMER_THREAD_PRIO	4
+#define RT_TIMER_THREAD_PRIO    4
 // 
-#define RT_TIMER_THREAD_STACK_SIZE	512
+#define RT_TIMER_THREAD_STACK_SIZE  512
 // 
-#define RT_TIMER_TICK_PER_SECOND	10
+#define RT_TIMER_TICK_PER_SECOND    10
 // 

 
 // 

@@ -67,15 +67,15 @@
 // 
 #define RT_USING_UART0
 // 
-#define RT_UART_RX_BUFFER_SIZE	64
+#define RT_UART_RX_BUFFER_SIZE  64
 // 

 
 // 

 #define RT_USING_CONSOLE
 // 
-#define RT_CONSOLEBUF_SIZE	128
+#define RT_CONSOLEBUF_SIZE  128
 // 
-#define RT_CONSOLE_DEVICE_NAME	"uart0"
+#define RT_CONSOLE_DEVICE_NAME  "uart0"
 // 

 
 // 
@@ -87,7 +87,7 @@
 // 
 #define FINSH_USING_DESCRIPTION
 // 
-#define FINSH_THREAD_STACK_SIZE	4096
+#define FINSH_THREAD_STACK_SIZE 4096
 // 

 
 // 

@@ -102,16 +102,16 @@
 // 
 #define DFS_USING_WORKDIR
 // 
-#define DFS_FILESYSTEMS_MAX	2
+#define DFS_FILESYSTEMS_MAX 2
 // 
-#define DFS_FD_MAX	4
+#define DFS_FD_MAX  4
 // 
 #define RT_USING_DFS_ELMFAT
 // 
 // 1
 // 2
 // 
-#define RT_DFS_ELM_USE_LFN	1
+#define RT_DFS_ELM_USE_LFN  1
 // 
 // 932
 // 936
@@ -142,7 +142,7 @@
 // 
 #define RT_DFS_ELM_CODE_PAGE 437
 // 
-#define RT_DFS_ELM_MAX_LFN	64
+#define RT_DFS_ELM_MAX_LFN  64
 // 
 // #define RT_USING_DFS_YAFFS2
 // 
@@ -152,7 +152,7 @@
 // 
 // #define RT_USING_DFS_NFS
 // 
-#define RT_NFS_HOST_EXPORT	"192.168.1.5:/"
+#define RT_NFS_HOST_EXPORT  "192.168.1.5:/"
 // 

 
 // 

@@ -168,29 +168,29 @@
 // 
 #define RT_LWIP_DNS
 // 
-#define RT_LWIP_PBUF_NUM	4
+#define RT_LWIP_PBUF_NUM    4
 // 
-#define RT_LWIP_TCP_PCB_NUM	3
+#define RT_LWIP_TCP_PCB_NUM 3
 // 
-#define RT_LWIP_TCP_SND_BUF	(2 * TCP_MSS)
+#define RT_LWIP_TCP_SND_BUF (2 * TCP_MSS)
 // 
-#define RT_LWIP_TCP_WND	2048
+#define RT_LWIP_TCP_WND 2048
 // 
 // #define RT_LWIP_SNMP
 // 
 // #define RT_LWIP_DHCP
 // 
-#define RT_LWIP_TCPTHREAD_PRIORITY	12
+#define RT_LWIP_TCPTHREAD_PRIORITY  12
 // 
-#define RT_LWIP_TCPTHREAD_MBOX_SIZE	8
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
 // 
-#define RT_LWIP_TCPTHREAD_STACKSIZE	4096
+#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
 // 
-#define RT_LWIP_ETHTHREAD_PRIORITY	14
+#define RT_LWIP_ETHTHREAD_PRIORITY  14
 // 
-#define RT_LWIP_ETHTHREAD_MBOX_SIZE	8
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
 // 
-#define RT_LWIP_ETHTHREAD_STACKSIZE	512
+#define RT_LWIP_ETHTHREAD_STACKSIZE 512
 // 
 #define RT_LWIP_IPADDR "192.168.1.30"
 // 
diff --git a/bsp/lpc178x/applications/application.c b/bsp/lpc178x/applications/application.c
index 9780d42154..b4f437405b 100644
--- a/bsp/lpc178x/applications/application.c
+++ b/bsp/lpc178x/applications/application.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -75,33 +75,33 @@ void rt_init_thread_entry(void *parameter)
 
 #ifdef RT_USING_RTGUI
     {
-    	extern void rtgui_system_server_init(void);
-		extern void application_init(void);
+        extern void rtgui_system_server_init(void);
+        extern void application_init(void);
 
-		rt_device_t lcd;
+        rt_device_t lcd;
 
-		/* init lcd */
-		rt_hw_lcd_init();
+        /* init lcd */
+        rt_hw_lcd_init();
 
-		/* find lcd device */
-		lcd = rt_device_find("lcd");
-		if (lcd != RT_NULL)
-		{
-			/* set lcd device as rtgui graphic driver */
-			rtgui_graphic_set_device(lcd);
+        /* find lcd device */
+        lcd = rt_device_find("lcd");
+        if (lcd != RT_NULL)
+        {
+            /* set lcd device as rtgui graphic driver */
+            rtgui_graphic_set_device(lcd);
 
-			/* init rtgui system server */
-			rtgui_system_server_init();
+            /* init rtgui system server */
+            rtgui_system_server_init();
 
-			/* startup rtgui in demo of RT-Thread/GUI examples */
-			application_init();
-		}
+            /* startup rtgui in demo of RT-Thread/GUI examples */
+            application_init();
+        }
     }
 #endif
 
 #ifdef RT_USING_FINSH
-	/* initialize finsh */
-	finsh_system_init();
+    /* initialize finsh */
+    finsh_system_init();
 #endif
 }
 
@@ -143,22 +143,22 @@ static void rt_thread_entry_led(void* parameter)
 
 int rt_application_init(void)
 {
-	rt_thread_t tid;
+    rt_thread_t tid;
 
-	rt_thread_init(&thread_led,
-			"led",
-			rt_thread_entry_led,
-			RT_NULL,
-			&thread_led_stack[0],
-			sizeof(thread_led_stack),11,5);
-	rt_thread_startup(&thread_led);
+    rt_thread_init(&thread_led,
+            "led",
+            rt_thread_entry_led,
+            RT_NULL,
+            &thread_led_stack[0],
+            sizeof(thread_led_stack),11,5);
+    rt_thread_startup(&thread_led);
 
-	tid = rt_thread_create("init",
-			rt_init_thread_entry, RT_NULL,
-			2048, RT_THREAD_PRIORITY_MAX/3, 20);
-	if (tid != RT_NULL) rt_thread_startup(tid);
+    tid = rt_thread_create("init",
+            rt_init_thread_entry, RT_NULL,
+            2048, RT_THREAD_PRIORITY_MAX/3, 20);
+    if (tid != RT_NULL) rt_thread_startup(tid);
 
-	return 0;
+    return 0;
 }
 
 #if defined(RT_USING_RTGUI) && defined(RT_USING_FINSH)
@@ -170,20 +170,20 @@ int rt_application_init(void)
 
 void key(rt_uint32_t key)
 {
-	struct rtgui_event_kbd ekbd;
+    struct rtgui_event_kbd ekbd;
 
-	RTGUI_EVENT_KBD_INIT(&ekbd);
-	ekbd.mod  = RTGUI_KMOD_NONE;
-	ekbd.unicode = 0;
-	ekbd.key = key;
+    RTGUI_EVENT_KBD_INIT(&ekbd);
+    ekbd.mod  = RTGUI_KMOD_NONE;
+    ekbd.unicode = 0;
+    ekbd.key = key;
 
-	ekbd.type = RTGUI_KEYDOWN;
-	rtgui_server_post_event((struct rtgui_event*)&ekbd, sizeof(ekbd));
+    ekbd.type = RTGUI_KEYDOWN;
+    rtgui_server_post_event((struct rtgui_event*)&ekbd, sizeof(ekbd));
 
-	rt_thread_delay(2);
+    rt_thread_delay(2);
 
-	ekbd.type = RTGUI_KEYUP;
-	rtgui_server_post_event((struct rtgui_event*)&ekbd, sizeof(ekbd));
+    ekbd.type = RTGUI_KEYUP;
+    rtgui_server_post_event((struct rtgui_event*)&ekbd, sizeof(ekbd));
 }
 FINSH_FUNCTION_EXPORT(key, send a key to gui server);
 #endif
diff --git a/bsp/lpc178x/applications/startup.c b/bsp/lpc178x/applications/startup.c
index 07698574b5..8b25e7d405 100644
--- a/bsp/lpc178x/applications/startup.c
+++ b/bsp/lpc178x/applications/startup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -37,11 +37,11 @@ extern int __bss_end;
 *******************************************************************************/
 void assert_failed(u8* file, u32 line)
 {
-	rt_kprintf("\n\r Wrong parameter value detected on\r\n");
-	rt_kprintf("       file  %s\r\n", file);
-	rt_kprintf("       line  %d\r\n", line);
+    rt_kprintf("\n\r Wrong parameter value detected on\r\n");
+    rt_kprintf("       file  %s\r\n", file);
+    rt_kprintf("       line  %d\r\n", line);
 
-	while (1) ;
+    while (1) ;
 }
 #endif
 
@@ -50,28 +50,28 @@ void assert_failed(u8* file, u32 line)
  */
 void rtthread_startup(void)
 {
-	/* initialize board */
-	rt_hw_board_init();
+    /* initialize board */
+    rt_hw_board_init();
 
-	/* show version */
-	rt_show_version();
+    /* show version */
+    rt_show_version();
 
 #ifdef RT_USING_HEAP
-	/* initialize memory system */
-	#ifdef __CC_ARM
-		rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)(0x10000000 + 1024*64));
-	#elif __ICCARM__
-	    rt_system_heap_init(__segment_end("HEAP"), (void*)(0x10000000 + 1024*64));
-	#else
-		rt_system_heap_init((void*)&__bss_end, (void*)(0x10000000 + 1024*64));
-	#endif
+    /* initialize memory system */
+    #ifdef __CC_ARM
+        rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)(0x10000000 + 1024*64));
+    #elif __ICCARM__
+        rt_system_heap_init(__segment_end("HEAP"), (void*)(0x10000000 + 1024*64));
+    #else
+        rt_system_heap_init((void*)&__bss_end, (void*)(0x10000000 + 1024*64));
+    #endif
 #endif
 
-	/* initialize scheduler system */
-	rt_system_scheduler_init();
+    /* initialize scheduler system */
+    rt_system_scheduler_init();
 
-	/* initialize application */
-	rt_application_init();
+    /* initialize application */
+    rt_application_init();
 
     /* initialize timer */
     rt_system_timer_init();
@@ -79,23 +79,23 @@ void rtthread_startup(void)
     /* initialize timer thread */
     rt_system_timer_thread_init();
 
-	/* initialize idle thread */
-	rt_thread_idle_init();
+    /* initialize idle thread */
+    rt_thread_idle_init();
 
-	/* start scheduler */
-	rt_system_scheduler_start();
+    /* start scheduler */
+    rt_system_scheduler_start();
 
-	/* never reach here */
-	return ;
+    /* never reach here */
+    return ;
 }
 
 int main(void)
 {
-	/* disable interrupt first */
-	rt_hw_interrupt_disable();
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
 
-	/* startup RT-Thread RTOS */
-	rtthread_startup();
+    /* startup RT-Thread RTOS */
+    rtthread_startup();
 
-	return 0;
+    return 0;
 }
diff --git a/bsp/lpc178x/drivers/board.c b/bsp/lpc178x/drivers/board.c
index df06d7f2f8..c07150e525 100644
--- a/bsp/lpc178x/drivers/board.c
+++ b/bsp/lpc178x/drivers/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc178x/drivers/board.h b/bsp/lpc178x/drivers/board.h
index 1a6d82e4b7..3c0a7fad71 100644
--- a/bsp/lpc178x/drivers/board.h
+++ b/bsp/lpc178x/drivers/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -31,7 +31,7 @@
 //#define RT_USING_UART2
 
 // 
-#define RT_CONSOLE_DEVICE_NAME	"uart0"
+#define RT_CONSOLE_DEVICE_NAME  "uart0"
 
 // 
 
diff --git a/bsp/lpc178x/drivers/drv_glcd.c b/bsp/lpc178x/drivers/drv_glcd.c
index ba02efeb67..6fa9c7b84e 100644
--- a/bsp/lpc178x/drivers/drv_glcd.c
+++ b/bsp/lpc178x/drivers/drv_glcd.c
@@ -37,14 +37,14 @@
 #define C_GLCD_LINES_PER_FRAME  (C_GLCD_V_SIZE + C_GLCD_V_PULSE + C_GLCD_V_FRONT_PORCH + C_GLCD_V_BACK_PORCH)
 #define C_GLCD_PIX_CLK          (C_GLCD_CLK_PER_LINE * C_GLCD_LINES_PER_FRAME)
 
-//LPC_LCD_TypeDef 	* const g_pLCD = ((LPC_LCD_TypeDef*) LPC_LCD_BASE);
+//LPC_LCD_TypeDef   * const g_pLCD = ((LPC_LCD_TypeDef*) LPC_LCD_BASE);
 //LPC_SC_TypeDef * const g_pSC = ((LPC_SC_TypeDef*) LPC_SC_BASE);
 
-#define SDRAM_BASE			0xA0000000	   /* CS0 */
-#define SDRAM_BASE_ADDR		SDRAM_BASE
+#define SDRAM_BASE          0xA0000000     /* CS0 */
+#define SDRAM_BASE_ADDR     SDRAM_BASE
 
-#define LCD_VRAM_BASE_ADDR 	((unsigned long)SDRAM_BASE_ADDR + 0x00000000)
-#define LCD_CURSOR_BASE_ADDR 	((unsigned long)0x20088800)
+#define LCD_VRAM_BASE_ADDR  ((unsigned long)SDRAM_BASE_ADDR + 0x00000000)
+#define LCD_CURSOR_BASE_ADDR    ((unsigned long)0x20088800)
 
 
 static pFontType_t pCurrFont = NULL;
@@ -155,18 +155,18 @@ void GLCD_Move_Cursor(int x, int y)
  *************************************************************************/
 void GLCD_Copy_Cursor (const unsigned long *pCursor, int cursor, int size)
 {
-   	unsigned long i ;
-   	unsigned long * pDst = (unsigned long *)LCD_CURSOR_BASE_ADDR;
+    unsigned long i ;
+    unsigned long * pDst = (unsigned long *)LCD_CURSOR_BASE_ADDR;
 
-   	pDst += cursor*64;
+    pDst += cursor*64;
 
-   	for(i = 0; i < size ; i++)
-//	   *pDst++ = *pCursor++;
-	{
-		*pDst = *pCursor;
-		pDst++;
-		pCursor++;
-	}
+    for(i = 0; i < size ; i++)
+//     *pDst++ = *pCursor++;
+    {
+        *pDst = *pCursor;
+        pDst++;
+        pCursor++;
+    }
 }
 /*************************************************************************
  * Function Name: GLCD_Init
@@ -179,101 +179,101 @@ void GLCD_Copy_Cursor (const unsigned long *pCursor, int cursor, int size)
  *************************************************************************/
 void GLCD_Init (void* VRAMBase)
 {
-	// unsigned long i;
-	// Assign pins
-	LPC_IOCON->P2_9 	= 0x06;	// VD3, 	R0
-	LPC_IOCON->P2_6 	= 0x07;	// VD4,		R1
-	LPC_IOCON->P2_7 	= 0x07;	// VD5,		R2
-	LPC_IOCON->P4_28	= 0x05;	// VD6,		R3
-	LPC_IOCON->P4_29 = 0x05;	// VD7,		R4
+    // unsigned long i;
+    // Assign pins
+    LPC_IOCON->P2_9     = 0x06; // VD3,     R0
+    LPC_IOCON->P2_6     = 0x07; // VD4,     R1
+    LPC_IOCON->P2_7     = 0x07; // VD5,     R2
+    LPC_IOCON->P4_28    = 0x05; // VD6,     R3
+    LPC_IOCON->P4_29 = 0x05;    // VD7,     R4
 
-	LPC_IOCON->P1_20	= 0x07;	// VD10,	G0
-	LPC_IOCON->P1_21	= 0x07;	// VD11,	G1
-	LPC_IOCON->P1_22	= 0x07;	// VD12,	G2
-	LPC_IOCON->P1_23	= 0x07;	// VD13,	G3
-	LPC_IOCON->P1_24	= 0x07;	// VD14,	G4
-	LPC_IOCON->P1_25	= 0x07;	// VD15,	G5
+    LPC_IOCON->P1_20    = 0x07; // VD10,    G0
+    LPC_IOCON->P1_21    = 0x07; // VD11,    G1
+    LPC_IOCON->P1_22    = 0x07; // VD12,    G2
+    LPC_IOCON->P1_23    = 0x07; // VD13,    G3
+    LPC_IOCON->P1_24    = 0x07; // VD14,    G4
+    LPC_IOCON->P1_25    = 0x07; // VD15,    G5
 
-	LPC_IOCON->P2_13	= 0x07;	// VD19,	B0
-	LPC_IOCON->P1_26 = 0x07;	// VD20,	B1
-	LPC_IOCON->P1_27 = 0x07;	// VD21,	B2
-	LPC_IOCON->P1_28 = 0x07;	// VD22,	B3
-	LPC_IOCON->P1_29 = 0x07;	// VD23,	B4
+    LPC_IOCON->P2_13    = 0x07; // VD19,    B0
+    LPC_IOCON->P1_26 = 0x07;    // VD20,    B1
+    LPC_IOCON->P1_27 = 0x07;    // VD21,    B2
+    LPC_IOCON->P1_28 = 0x07;    // VD22,    B3
+    LPC_IOCON->P1_29 = 0x07;    // VD23,    B4
 
-	LPC_IOCON->P2_2	= 0x07;	// DCLK
-	LPC_IOCON->P2_0	= 0x07;	// DSIP(power)
-	LPC_IOCON->P2_5	= 0x07;	// HSYNC
-	LPC_IOCON->P2_3	= 0x07;	// VSYNC
-	LPC_IOCON->P2_4	= 0x07;	// DataEn
+    LPC_IOCON->P2_2 = 0x07; // DCLK
+    LPC_IOCON->P2_0 = 0x07; // DSIP(power)
+    LPC_IOCON->P2_5 = 0x07; // HSYNC
+    LPC_IOCON->P2_3 = 0x07; // VSYNC
+    LPC_IOCON->P2_4 = 0x07; // DataEn
 
-//	LPC_IOCON->P5_4	= 0x00;	// Backlight
+//  LPC_IOCON->P5_4 = 0x00; // Backlight
 
-	// >>> debug >>>
+    // >>> debug >>>
 
-	// <<< debug <<<
+    // <<< debug <<<
 
-	/*Back light enable*/
-//	LPC_GPIO5->DIR = (1<<4);
-//	LPC_GPIO5->SET= (5<<4);
+    /*Back light enable*/
+//  LPC_GPIO5->DIR = (1<<4);
+//  LPC_GPIO5->SET= (5<<4);
 
-	//Turn on LCD clock
-	CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCLCD, ENABLE);
+    //Turn on LCD clock
+    CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCLCD, ENABLE);
 
-	// Disable cursor
-	LPC_LCD->CRSR_CTRL &=~(1<<0);
+    // Disable cursor
+    LPC_LCD->CRSR_CTRL &=~(1<<0);
 
-	// disable GLCD controller
-	LPC_LCD->CTRL = 0;
-	// RGB888
-	LPC_LCD->CTRL &= ~(0x07 <<1);
-	LPC_LCD->CTRL |= (6<<1);
+    // disable GLCD controller
+    LPC_LCD->CTRL = 0;
+    // RGB888
+    LPC_LCD->CTRL &= ~(0x07 <<1);
+    LPC_LCD->CTRL |= (6<<1);
 
-	// TFT panel
-	LPC_LCD->CTRL |= (1<<5);
-	// single panel
-	LPC_LCD->CTRL &= ~(1<<7);
-	// notmal output
-	LPC_LCD->CTRL &= ~(1<<8);
-	// little endian byte order
-	LPC_LCD->CTRL &= ~(1<<9);
-	// little endian pix order
-	LPC_LCD->CTRL &= ~(1<<10);
-	// disable power
-	LPC_LCD->CTRL &= ~(1<<11);
-	// init pixel clock
-//	g_pSC->LCD_CFG = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER) / ((unsigned long)C_GLCD_PIX_CLK);
-	LPC_SC->LCD_CFG = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER) / ((unsigned long)C_GLCD_PIX_CLK);
-	// bypass inrenal clk divider
-	LPC_LCD->POL |=(1<<26);
-	// clock source for the LCD block is HCLK
-	LPC_LCD->POL &= ~(1<<5);
-	// LCDFP pin is active LOW and inactive HIGH
-	LPC_LCD->POL |= (1<<11);
-	// LCDLP pin is active LOW and inactive HIGH
-	LPC_LCD->POL |= (1<<12);
-	// data is driven out into the LCD on the falling edge
-	LPC_LCD->POL &= ~(1<<13);
-	// active high
-	LPC_LCD->POL &= ~(1<<14);
-	LPC_LCD->POL &= ~(0x3FF <<16);
-	LPC_LCD->POL |= (C_GLCD_H_SIZE-1)<<16;
+    // TFT panel
+    LPC_LCD->CTRL |= (1<<5);
+    // single panel
+    LPC_LCD->CTRL &= ~(1<<7);
+    // notmal output
+    LPC_LCD->CTRL &= ~(1<<8);
+    // little endian byte order
+    LPC_LCD->CTRL &= ~(1<<9);
+    // little endian pix order
+    LPC_LCD->CTRL &= ~(1<<10);
+    // disable power
+    LPC_LCD->CTRL &= ~(1<<11);
+    // init pixel clock
+//  g_pSC->LCD_CFG = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER) / ((unsigned long)C_GLCD_PIX_CLK);
+    LPC_SC->LCD_CFG = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER) / ((unsigned long)C_GLCD_PIX_CLK);
+    // bypass inrenal clk divider
+    LPC_LCD->POL |=(1<<26);
+    // clock source for the LCD block is HCLK
+    LPC_LCD->POL &= ~(1<<5);
+    // LCDFP pin is active LOW and inactive HIGH
+    LPC_LCD->POL |= (1<<11);
+    // LCDLP pin is active LOW and inactive HIGH
+    LPC_LCD->POL |= (1<<12);
+    // data is driven out into the LCD on the falling edge
+    LPC_LCD->POL &= ~(1<<13);
+    // active high
+    LPC_LCD->POL &= ~(1<<14);
+    LPC_LCD->POL &= ~(0x3FF <<16);
+    LPC_LCD->POL |= (C_GLCD_H_SIZE-1)<<16;
 
-	// init Horizontal Timing
-	LPC_LCD->TIMH = 0; //reset TIMH before set value
-	LPC_LCD->TIMH |= (C_GLCD_H_BACK_PORCH - 1)<<24;
-	LPC_LCD->TIMH |= (C_GLCD_H_FRONT_PORCH - 1)<<16;
-	LPC_LCD->TIMH |= (C_GLCD_H_PULSE - 1)<<8;
-	LPC_LCD->TIMH |= ((C_GLCD_H_SIZE/16) - 1)<<2;
+    // init Horizontal Timing
+    LPC_LCD->TIMH = 0; //reset TIMH before set value
+    LPC_LCD->TIMH |= (C_GLCD_H_BACK_PORCH - 1)<<24;
+    LPC_LCD->TIMH |= (C_GLCD_H_FRONT_PORCH - 1)<<16;
+    LPC_LCD->TIMH |= (C_GLCD_H_PULSE - 1)<<8;
+    LPC_LCD->TIMH |= ((C_GLCD_H_SIZE/16) - 1)<<2;
 
-	// init Vertical Timing
-	LPC_LCD->TIMV = 0;  //reset TIMV value before setting
-	LPC_LCD->TIMV |= (C_GLCD_V_BACK_PORCH)<<24;
-	LPC_LCD->TIMV |= (C_GLCD_V_FRONT_PORCH)<<16;
-	LPC_LCD->TIMV |= (C_GLCD_V_PULSE - 1)<<10;
-	LPC_LCD->TIMV |= C_GLCD_V_SIZE - 1;
-	// Frame Base Address doubleword aligned
-	LPC_LCD->UPBASE = (unsigned long)VRAMBase & ~7UL ;
-	LPC_LCD->LPBASE = (unsigned long)VRAMBase & ~7UL ;
+    // init Vertical Timing
+    LPC_LCD->TIMV = 0;  //reset TIMV value before setting
+    LPC_LCD->TIMV |= (C_GLCD_V_BACK_PORCH)<<24;
+    LPC_LCD->TIMV |= (C_GLCD_V_FRONT_PORCH)<<16;
+    LPC_LCD->TIMV |= (C_GLCD_V_PULSE - 1)<<10;
+    LPC_LCD->TIMV |= C_GLCD_V_SIZE - 1;
+    // Frame Base Address doubleword aligned
+    LPC_LCD->UPBASE = (unsigned long)VRAMBase & ~7UL ;
+    LPC_LCD->LPBASE = (unsigned long)VRAMBase & ~7UL ;
 }
 
 /*************************************************************************
@@ -287,13 +287,13 @@ void GLCD_Init (void* VRAMBase)
  *************************************************************************/
 void GLCD_SetPallet (const unsigned long * pPallete)
 {
-	unsigned long i;
-	unsigned long * pDst = (unsigned long *)LPC_LCD->PAL;
-	// //assert(pPallete);
-	for (i = 0; i < 128; i++)
-	{
-	*pDst++ = *pPallete++;
-	}
+    unsigned long i;
+    unsigned long * pDst = (unsigned long *)LPC_LCD->PAL;
+    // //assert(pPallete);
+    for (i = 0; i < 128; i++)
+    {
+    *pDst++ = *pPallete++;
+    }
 }
 
 /*************************************************************************
@@ -307,7 +307,7 @@ void GLCD_SetPallet (const unsigned long * pPallete)
  *************************************************************************/
 void GLCD_Ctrl (Bool bEna)
 {
-	volatile unsigned long i;
+    volatile unsigned long i;
   if (bEna)
   {
 //    LCD_CTRL_bit.LcdEn = 1;
@@ -473,7 +473,7 @@ Bool GLCD_TextCalcWindow (unsigned long * pXL, unsigned long * pXR,
   *pXR   = XL_Win + ((TextX_Pos+1)*pCurrFont->H_Size) - 1;
   if(*pXR > XR_Win)
   {
-  	*pH_Size -= *pXR - XR_Win;
+    *pH_Size -= *pXR - XR_Win;
     *pXR = XR_Win;
   }
 
@@ -514,19 +514,19 @@ unsigned long i, j, k;
     ++TextY_Pos;
     break;
   case '\r':  // go to begin of this line (Carriage Return)
-  	// clear from current position to end of line
-  	while(GLCD_TextCalcWindow(&xl,&xr,&yu,&yd,&H_Size,&V_Size))
-  	{
+    // clear from current position to end of line
+    while(GLCD_TextCalcWindow(&xl,&xr,&yu,&yd,&H_Size,&V_Size))
+    {
       LCD_SET_WINDOW(xl,xr,yu,yd);
-	    for(i = 0; i < V_Size; ++i)
-	    {
-	      for(j = 0; j < H_Size; ++j)
-	      {
-	        LCD_WRITE_PIXEL(TextBackgndColour);
-	      }
-	    }
-  		++TextX_Pos;
-  	}
+        for(i = 0; i < V_Size; ++i)
+        {
+          for(j = 0; j < H_Size; ++j)
+          {
+            LCD_WRITE_PIXEL(TextBackgndColour);
+          }
+        }
+        ++TextX_Pos;
+    }
     TextX_Pos = 0;
     break;
   case '\b': // go back one position (BackSpace)
@@ -534,45 +534,45 @@ unsigned long i, j, k;
     {
       --TextX_Pos;
       // del current position
-	  	if(GLCD_TextCalcWindow(&xl,&xr,&yu,&yd,&H_Size,&V_Size))
-	  	{
+        if(GLCD_TextCalcWindow(&xl,&xr,&yu,&yd,&H_Size,&V_Size))
+        {
         LCD_SET_WINDOW(xl,xr,yu,yd);
-		    for(i = 0; i < V_Size; ++i)
-		    {
-		      for(j = 0; j < H_Size; ++j)
-		      {
-		        LCD_WRITE_PIXEL(TextBackgndColour);
-		      }
-		    }
-	  	}
+            for(i = 0; i < V_Size; ++i)
+            {
+              for(j = 0; j < H_Size; ++j)
+              {
+                LCD_WRITE_PIXEL(TextBackgndColour);
+              }
+            }
+        }
     }
     break;
   case '\t':  // go to next Horizontal Tab stop
-  	WhiteSpaceNumb = TabSize - (TextX_Pos%TabSize);
-  	for(k = 0; k < WhiteSpaceNumb; ++k)
-  	{
+    WhiteSpaceNumb = TabSize - (TextX_Pos%TabSize);
+    for(k = 0; k < WhiteSpaceNumb; ++k)
+    {
       LCD_SET_WINDOW(xl,xr,yu,yd);
-	  	if(GLCD_TextCalcWindow(&xl,&xr,&yu,&yd,&H_Size,&V_Size))
-	  	{
-		    for(i = 0; i < V_Size; ++i)
-		    {
-		      for(j = 0; j < H_Size; ++j)
-		      {
-		        LCD_WRITE_PIXEL(TextBackgndColour);
-		      }
-		    }
-		    ++TextX_Pos;
-	  	}
-	  	else
-	  	{
-	  		break;
-	  	}
-  	}
+        if(GLCD_TextCalcWindow(&xl,&xr,&yu,&yd,&H_Size,&V_Size))
+        {
+            for(i = 0; i < V_Size; ++i)
+            {
+              for(j = 0; j < H_Size; ++j)
+              {
+                LCD_WRITE_PIXEL(TextBackgndColour);
+              }
+            }
+            ++TextX_Pos;
+        }
+        else
+        {
+            break;
+        }
+    }
     break;
   case '\f':  // go to top of page (Form Feed)
-  	// clear entire window
-  	H_Size = XR_Win - XL_Win;
-  	V_Size = YD_Win - YU_Win;
+    // clear entire window
+    H_Size = XR_Win - XL_Win;
+    V_Size = YD_Win - YU_Win;
     // set character window X left, Y right
     LCD_SET_WINDOW(XL_Win,XR_Win,YU_Win,YD_Win);
     // Fill window with background font color
@@ -584,7 +584,7 @@ unsigned long i, j, k;
       }
     }
 
-  	TextX_Pos = TextY_Pos = 0;
+    TextX_Pos = TextY_Pos = 0;
     break;
   case '\a':  // signal an alert (BELl)
     TEXT_BEL1_FUNC();
@@ -593,37 +593,37 @@ unsigned long i, j, k;
     // Calculate the current character base address from stream
     // and the character position
     if((c <  pCurrFont->CharacterOffset) &&
-    	 (c >= pCurrFont->CharactersNuber))
-   	{
-   		c = 0;
+         (c >= pCurrFont->CharactersNuber))
+    {
+        c = 0;
     }
     else
     {
-    	c -= pCurrFont->CharacterOffset;
+        c -= pCurrFont->CharacterOffset;
     }
     pSrc = pCurrFont->pFontStream + (H_Line * pCurrFont->V_Size * c);
     // Calculate character window and fit it in the text window
     if(GLCD_TextCalcWindow(&xl,&xr,&yu,&yd,&H_Size,&V_Size))
     {
-	    // set character window X left, Y right
-	    LCD_SET_WINDOW(xl,xr,yu,yd);
-	    // Send char data
-	    for(i = 0; i < V_Size; ++i)
-	    {
+        // set character window X left, Y right
+        LCD_SET_WINDOW(xl,xr,yu,yd);
+        // Send char data
+        for(i = 0; i < V_Size; ++i)
+        {
         SrcInc = H_Line;
         for(j = 0; j < H_Size; ++j)
-	      {
-	        Temp = (*pSrc & (1UL << (j&0x7)))?TextColour:TextBackgndColour;
-	        LCD_WRITE_PIXEL(Temp);
-	        if((j&0x7) == 7)
-	        {
-	          ++pSrc;
+          {
+            Temp = (*pSrc & (1UL << (j&0x7)))?TextColour:TextBackgndColour;
+            LCD_WRITE_PIXEL(Temp);
+            if((j&0x7) == 7)
+            {
+              ++pSrc;
             --SrcInc;
-	        }
-	      }
+            }
+          }
         // next line of character
-	      pSrc += SrcInc;
-	    }
+          pSrc += SrcInc;
+        }
     }
     ++TextX_Pos;
   }
diff --git a/bsp/lpc178x/drivers/drv_glcd.h b/bsp/lpc178x/drivers/drv_glcd.h
index 1453bd4782..5a28ceb6b3 100644
--- a/bsp/lpc178x/drivers/drv_glcd.h
+++ b/bsp/lpc178x/drivers/drv_glcd.h
@@ -33,7 +33,7 @@ typedef unsigned long Boolean;
 /**
  * @brief A struct for Bitmap on LCD screen
  */
-typedef struct _Bmp_t 
+typedef struct _Bmp_t
 {
   U32  H_Size;
   U32  V_Size;
@@ -47,8 +47,8 @@ typedef struct _Bmp_t
 /**
  * @brief A struct for Font Type on LCD screen
  */
- 
-typedef struct _FontType_t 
+
+typedef struct _FontType_t
 {
   U32 H_Size;
   U32 V_Size;
@@ -62,9 +62,9 @@ typedef U32 LdcPixel_t, *pLdcPixel_t;
 
 #define C_GLCD_REFRESH_FREQ     (60HZ)
 #define C_GLCD_H_SIZE           480
-#define C_GLCD_H_PULSE          2	//
-#define C_GLCD_H_FRONT_PORCH    5	//
-#define C_GLCD_H_BACK_PORCH     40 	//
+#define C_GLCD_H_PULSE          2   //
+#define C_GLCD_H_FRONT_PORCH    5   //
+#define C_GLCD_H_BACK_PORCH     40  //
 #define C_GLCD_V_SIZE           272
 #define C_GLCD_V_PULSE          2
 #define C_GLCD_V_FRONT_PORCH    8
diff --git a/bsp/lpc178x/drivers/emac.c b/bsp/lpc178x/drivers/emac.c
index a16dc49770..ec48ea8833 100644
--- a/bsp/lpc178x/drivers/emac.c
+++ b/bsp/lpc178x/drivers/emac.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -14,20 +14,20 @@
 #include "lwipopts.h"
 #include 
 
-#define EMAC_PHY_AUTO		0
-#define EMAC_PHY_10MBIT		1
-#define EMAC_PHY_100MBIT	2
+#define EMAC_PHY_AUTO       0
+#define EMAC_PHY_10MBIT     1
+#define EMAC_PHY_100MBIT    2
 
 #define MAX_ADDR_LEN 6
 struct lpc17xx_emac
 {
-	/* inherit from ethernet device */
-	struct eth_device parent;
+    /* inherit from ethernet device */
+    struct eth_device parent;
 
-	rt_uint8_t phy_mode;
+    rt_uint8_t phy_mode;
 
-	/* interface address info. */
-	rt_uint8_t  dev_addr[MAX_ADDR_LEN];		/* hw address	*/
+    /* interface address info. */
+    rt_uint8_t  dev_addr[MAX_ADDR_LEN];     /* hw address   */
 };
 static struct lpc17xx_emac lpc17xx_emac_device;
 static struct rt_semaphore sem_lock;
@@ -39,39 +39,39 @@ static rt_uint16_t read_PHY (rt_uint8_t PhyReg) ;
 
 void ENET_IRQHandler(void)
 {
-	rt_uint32_t status;
+    rt_uint32_t status;
 
     /* enter interrupt */
     rt_interrupt_enter();
 
-	status = LPC_EMAC->IntStatus;
+    status = LPC_EMAC->IntStatus;
 
-	if (status & INT_RX_DONE)
-	{
-		/* Disable EMAC RxDone interrupts. */
-		LPC_EMAC->IntEnable = INT_TX_DONE;
+    if (status & INT_RX_DONE)
+    {
+        /* Disable EMAC RxDone interrupts. */
+        LPC_EMAC->IntEnable = INT_TX_DONE;
 
-		/* a frame has been received */
-		eth_device_ready(&(lpc17xx_emac_device.parent));
-	}
-	else if (status & INT_TX_DONE)
-	{
-		/* set event */
-		rt_event_send(&tx_event, 0x01);
-	}
+        /* a frame has been received */
+        eth_device_ready(&(lpc17xx_emac_device.parent));
+    }
+    else if (status & INT_TX_DONE)
+    {
+        /* set event */
+        rt_event_send(&tx_event, 0x01);
+    }
 
-	if (status & INT_RX_OVERRUN)
-	{
-		rt_kprintf("rx overrun\n");
-	}
+    if (status & INT_RX_OVERRUN)
+    {
+        rt_kprintf("rx overrun\n");
+    }
 
-	if (status & INT_TX_UNDERRUN)
-	{
-		rt_kprintf("tx underrun\n");
-	}
+    if (status & INT_TX_UNDERRUN)
+    {
+        rt_kprintf("tx underrun\n");
+    }
 
-	/* Clear the interrupt. */
-	LPC_EMAC->IntClear = status;
+    /* Clear the interrupt. */
+    LPC_EMAC->IntClear = status;
 
     /* leave interrupt */
     rt_interrupt_leave();
@@ -80,84 +80,84 @@ void ENET_IRQHandler(void)
 /* phy write */
 static void write_PHY (rt_uint32_t PhyReg, rt_uint32_t Value)
 {
-	unsigned int tout;
+    unsigned int tout;
 
-	LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
-	LPC_EMAC->MWTD = Value;
+    LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
+    LPC_EMAC->MWTD = Value;
 
-	/* Wait utill operation completed */
-	tout = 0;
-	for (tout = 0; tout < MII_WR_TOUT; tout++)
-	{
-		if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
-		{
-			break;
-		}
-	}
+    /* Wait utill operation completed */
+    tout = 0;
+    for (tout = 0; tout < MII_WR_TOUT; tout++)
+    {
+        if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
+        {
+            break;
+        }
+    }
 }
 
 /* phy read */
 static rt_uint16_t read_PHY (rt_uint8_t PhyReg)
 {
-	rt_uint32_t tout;
+    rt_uint32_t tout;
 
-	LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
-	LPC_EMAC->MCMD = MCMD_READ;
+    LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
+    LPC_EMAC->MCMD = MCMD_READ;
 
-	/* Wait until operation completed */
-	tout = 0;
-	for (tout = 0; tout < MII_RD_TOUT; tout++)
-	{
-		if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
-		{
-			break;
-		}
-	}
-	LPC_EMAC->MCMD = 0;
-	return (LPC_EMAC->MRDD);
+    /* Wait until operation completed */
+    tout = 0;
+    for (tout = 0; tout < MII_RD_TOUT; tout++)
+    {
+        if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
+        {
+            break;
+        }
+    }
+    LPC_EMAC->MCMD = 0;
+    return (LPC_EMAC->MRDD);
 }
 
 /* init rx descriptor */
 rt_inline void rx_descr_init (void)
 {
-	rt_uint32_t i;
+    rt_uint32_t i;
 
-	for (i = 0; i < NUM_RX_FRAG; i++)
-	{
-		RX_DESC_PACKET(i)  = RX_BUF(i);
-		RX_DESC_CTRL(i)    = RCTRL_INT | (ETH_FRAG_SIZE-1);
-		RX_STAT_INFO(i)    = 0;
-		RX_STAT_HASHCRC(i) = 0;
-	}
+    for (i = 0; i < NUM_RX_FRAG; i++)
+    {
+        RX_DESC_PACKET(i)  = RX_BUF(i);
+        RX_DESC_CTRL(i)    = RCTRL_INT | (ETH_FRAG_SIZE-1);
+        RX_STAT_INFO(i)    = 0;
+        RX_STAT_HASHCRC(i) = 0;
+    }
 
-	/* Set EMAC Receive Descriptor Registers. */
-	LPC_EMAC->RxDescriptor    = RX_DESC_BASE;
-	LPC_EMAC->RxStatus        = RX_STAT_BASE;
-	LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1;
+    /* Set EMAC Receive Descriptor Registers. */
+    LPC_EMAC->RxDescriptor    = RX_DESC_BASE;
+    LPC_EMAC->RxStatus        = RX_STAT_BASE;
+    LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1;
 
-	/* Rx Descriptors Point to 0 */
-	LPC_EMAC->RxConsumeIndex  = 0;
+    /* Rx Descriptors Point to 0 */
+    LPC_EMAC->RxConsumeIndex  = 0;
 }
 
 /* init tx descriptor */
 rt_inline void tx_descr_init (void)
 {
-	rt_uint32_t i;
+    rt_uint32_t i;
 
-	for (i = 0; i < NUM_TX_FRAG; i++)
-	{
-		TX_DESC_PACKET(i) = TX_BUF(i);
-		TX_DESC_CTRL(i)   = (1ul<<31) | (1ul<<30) | (1ul<<29) | (1ul<<28) | (1ul<<26) | (ETH_FRAG_SIZE-1);
-		TX_STAT_INFO(i)   = 0;
-	}
+    for (i = 0; i < NUM_TX_FRAG; i++)
+    {
+        TX_DESC_PACKET(i) = TX_BUF(i);
+        TX_DESC_CTRL(i)   = (1ul<<31) | (1ul<<30) | (1ul<<29) | (1ul<<28) | (1ul<<26) | (ETH_FRAG_SIZE-1);
+        TX_STAT_INFO(i)   = 0;
+    }
 
-	/* Set EMAC Transmit Descriptor Registers. */
-	LPC_EMAC->TxDescriptor    = TX_DESC_BASE;
-	LPC_EMAC->TxStatus        = TX_STAT_BASE;
-	LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1;
+    /* Set EMAC Transmit Descriptor Registers. */
+    LPC_EMAC->TxDescriptor    = TX_DESC_BASE;
+    LPC_EMAC->TxStatus        = TX_STAT_BASE;
+    LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1;
 
-	/* Tx Descriptors Point to 0 */
-	LPC_EMAC->TxProduceIndex  = 0;
+    /* Tx Descriptors Point to 0 */
+    LPC_EMAC->TxProduceIndex  = 0;
 }
 
 /*
@@ -178,375 +178,375 @@ REF_CLK   P1_15
 */
 static rt_err_t lpc17xx_emac_init(rt_device_t dev)
 {
-	/* Initialize the EMAC ethernet controller. */
-	rt_uint32_t regv, tout;
+    /* Initialize the EMAC ethernet controller. */
+    rt_uint32_t regv, tout;
 
-	/* Power Up the EMAC controller. */
-	LPC_SC->PCONP |= (1UL<<30);
+    /* Power Up the EMAC controller. */
+    LPC_SC->PCONP |= (1UL<<30);
 
-	/* config RESET */
-	PINSEL_ConfigPin(3, 19, 0);
-	PINSEL_SetPinMode(3, 19, IOCON_MODE_PLAIN);
-	LPC_GPIO3->DIR |= 1<<19;
-	LPC_GPIO3->CLR = 1<<19;
+    /* config RESET */
+    PINSEL_ConfigPin(3, 19, 0);
+    PINSEL_SetPinMode(3, 19, IOCON_MODE_PLAIN);
+    LPC_GPIO3->DIR |= 1<<19;
+    LPC_GPIO3->CLR = 1<<19;
 
-	/* Enable P1 Ethernet Pins. */
-	PINSEL_ConfigPin(1, 0, 1);  /**< P1_0  ENET_TXD0 */
-	PINSEL_ConfigPin(1, 1, 1);  /**< P1_1  ENET_TXD1 */
-	PINSEL_ConfigPin(1, 4, 1);  /**< P1_4  ENET_TX_EN */
-	PINSEL_ConfigPin(1, 8, 1);  /**< P1_8  ENET_CRS_DV */
-	PINSEL_ConfigPin(1, 9, 1);  /**< P1_9  ENET_RXD0 */
-	PINSEL_ConfigPin(1, 10, 1); /**< P1_10 ENET_RXD1 */
-	PINSEL_ConfigPin(1, 14, 1); /**< P1_14 ENET_RX_ER */
-	PINSEL_ConfigPin(1, 15, 1); /**< P1_15 ENET_REF_CLK */
-	PINSEL_ConfigPin(1, 16, 1); /**< P1_16 ENET_MDC */
-	PINSEL_ConfigPin(1, 17, 1); /**< P1_17 ENET_MDIO */
+    /* Enable P1 Ethernet Pins. */
+    PINSEL_ConfigPin(1, 0, 1);  /**< P1_0  ENET_TXD0 */
+    PINSEL_ConfigPin(1, 1, 1);  /**< P1_1  ENET_TXD1 */
+    PINSEL_ConfigPin(1, 4, 1);  /**< P1_4  ENET_TX_EN */
+    PINSEL_ConfigPin(1, 8, 1);  /**< P1_8  ENET_CRS_DV */
+    PINSEL_ConfigPin(1, 9, 1);  /**< P1_9  ENET_RXD0 */
+    PINSEL_ConfigPin(1, 10, 1); /**< P1_10 ENET_RXD1 */
+    PINSEL_ConfigPin(1, 14, 1); /**< P1_14 ENET_RX_ER */
+    PINSEL_ConfigPin(1, 15, 1); /**< P1_15 ENET_REF_CLK */
+    PINSEL_ConfigPin(1, 16, 1); /**< P1_16 ENET_MDC */
+    PINSEL_ConfigPin(1, 17, 1); /**< P1_17 ENET_MDIO */
 
-	LPC_GPIO3->SET = 1<<19;
+    LPC_GPIO3->SET = 1<<19;
 
-	/* Reset all EMAC internal modules. */
-	LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
-				 MAC1_SIM_RES | MAC1_SOFT_RES;
-	LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
+    /* Reset all EMAC internal modules. */
+    LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
+                 MAC1_SIM_RES | MAC1_SOFT_RES;
+    LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
 
-	/* A short delay after reset. */
-	for (tout = 100; tout; tout--);
+    /* A short delay after reset. */
+    for (tout = 100; tout; tout--);
 
-	/* Initialize MAC control registers. */
-	LPC_EMAC->MAC1 = MAC1_PASS_ALL;
-	LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
-	LPC_EMAC->MAXF = ETH_MAX_FLEN;
-	LPC_EMAC->CLRT = CLRT_DEF;
-	LPC_EMAC->IPGR = IPGR_DEF;
+    /* Initialize MAC control registers. */
+    LPC_EMAC->MAC1 = MAC1_PASS_ALL;
+    LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
+    LPC_EMAC->MAXF = ETH_MAX_FLEN;
+    LPC_EMAC->CLRT = CLRT_DEF;
+    LPC_EMAC->IPGR = IPGR_DEF;
 
-	/* PCLK=18MHz, clock select=6, MDC=18/6=3MHz */
-	/* Enable Reduced MII interface. */
-	LPC_EMAC->MCFG = MCFG_CLK_DIV20 | MCFG_RES_MII;
-	for (tout = 100; tout; tout--);
-	LPC_EMAC->MCFG = MCFG_CLK_DIV20;
+    /* PCLK=18MHz, clock select=6, MDC=18/6=3MHz */
+    /* Enable Reduced MII interface. */
+    LPC_EMAC->MCFG = MCFG_CLK_DIV20 | MCFG_RES_MII;
+    for (tout = 100; tout; tout--);
+    LPC_EMAC->MCFG = MCFG_CLK_DIV20;
 
-	/* Enable Reduced MII interface. */
-	LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM | CR_PASS_RX_FILT;
+    /* Enable Reduced MII interface. */
+    LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM | CR_PASS_RX_FILT;
 
-	/* Reset Reduced MII Logic. */
-	LPC_EMAC->SUPP = SUPP_RES_RMII | SUPP_SPEED;
-	for (tout = 100; tout; tout--);
-	LPC_EMAC->SUPP = SUPP_SPEED;
+    /* Reset Reduced MII Logic. */
+    LPC_EMAC->SUPP = SUPP_RES_RMII | SUPP_SPEED;
+    for (tout = 100; tout; tout--);
+    LPC_EMAC->SUPP = SUPP_SPEED;
 
-	/* Put the PHY in reset mode */
-	write_PHY (PHY_REG_BMCR, 0x8000);
-	for (tout = 1000; tout; tout--);
+    /* Put the PHY in reset mode */
+    write_PHY (PHY_REG_BMCR, 0x8000);
+    for (tout = 1000; tout; tout--);
 
-//	/* Wait for hardware reset to end. */
-//	for (tout = 0; tout < 0x100000; tout++)
-//	{
-//		regv = read_PHY (PHY_REG_BMCR);
-//		if (!(regv & 0x8000))
-//		{
-//			/* Reset complete */
-//			break;
-//		}
-//	}
-//	if (tout >= 0x100000)
+//  /* Wait for hardware reset to end. */
+//  for (tout = 0; tout < 0x100000; tout++)
+//  {
+//      regv = read_PHY (PHY_REG_BMCR);
+//      if (!(regv & 0x8000))
+//      {
+//          /* Reset complete */
+//          break;
+//      }
+//  }
+//  if (tout >= 0x100000)
 //    {
 //        rt_kprintf("reset failed\r\n");
 //        return -RT_ERROR; /* reset failed */
 //    }
 
-//	/* Check if this is a DP83848C PHY. */
-//	id1 = read_PHY (PHY_REG_IDR1);
-//	id2 = read_PHY (PHY_REG_IDR2);
+//  /* Check if this is a DP83848C PHY. */
+//  id1 = read_PHY (PHY_REG_IDR1);
+//  id2 = read_PHY (PHY_REG_IDR2);
 //
-//	if (((id1 << 16) | (id2 & 0xFFF0)) != DP83848C_ID)
-//		return -RT_ERROR;
+//  if (((id1 << 16) | (id2 & 0xFFF0)) != DP83848C_ID)
+//      return -RT_ERROR;
 
-	/* Configure the PHY device */
-	/* Configure the PHY device */
-	switch (lpc17xx_emac_device.phy_mode)
-	{
-	case EMAC_PHY_AUTO:
-		/* Use autonegotiation about the link speed. */
-		write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG);
-		/* Wait to complete Auto_Negotiation. */
-//		for (tout = 0; tout < 0x100000; tout++)
-//		{
-//			regv = read_PHY (PHY_REG_BMSR);
-//			if (regv & 0x0020)
-//			{
-//				/* Autonegotiation Complete. */
-//				break;
-//			}
-//		}
-		break;
-	case EMAC_PHY_10MBIT:
-		/* Connect at 10MBit */
-		write_PHY (PHY_REG_BMCR, PHY_FULLD_10M);
-		break;
-	case EMAC_PHY_100MBIT:
-		/* Connect at 100MBit */
-		write_PHY (PHY_REG_BMCR, PHY_FULLD_100M);
-		break;
-	}
-	if (tout >= 0x100000) return -RT_ERROR; // auto_neg failed
+    /* Configure the PHY device */
+    /* Configure the PHY device */
+    switch (lpc17xx_emac_device.phy_mode)
+    {
+    case EMAC_PHY_AUTO:
+        /* Use autonegotiation about the link speed. */
+        write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG);
+        /* Wait to complete Auto_Negotiation. */
+//      for (tout = 0; tout < 0x100000; tout++)
+//      {
+//          regv = read_PHY (PHY_REG_BMSR);
+//          if (regv & 0x0020)
+//          {
+//              /* Autonegotiation Complete. */
+//              break;
+//          }
+//      }
+        break;
+    case EMAC_PHY_10MBIT:
+        /* Connect at 10MBit */
+        write_PHY (PHY_REG_BMCR, PHY_FULLD_10M);
+        break;
+    case EMAC_PHY_100MBIT:
+        /* Connect at 100MBit */
+        write_PHY (PHY_REG_BMCR, PHY_FULLD_100M);
+        break;
+    }
+    if (tout >= 0x100000) return -RT_ERROR; // auto_neg failed
 
-//	/* Check the link status. */
-//	for (tout = 0; tout < 0x10000; tout++)
-//	{
-//		regv = read_PHY (PHY_REG_STS);
-//		if (regv & 0x0001)
-//		{
-//			/* Link is on. */
-//			break;
-//		}
-//	}
-//	if (tout >= 0x10000) return -RT_ERROR;
+//  /* Check the link status. */
+//  for (tout = 0; tout < 0x10000; tout++)
+//  {
+//      regv = read_PHY (PHY_REG_STS);
+//      if (regv & 0x0001)
+//      {
+//          /* Link is on. */
+//          break;
+//      }
+//  }
+//  if (tout >= 0x10000) return -RT_ERROR;
 
-	regv = 0x0004;
-	/* Configure Full/Half Duplex mode. */
-	if (regv & 0x0004)
-	{
-		/* Full duplex is enabled. */
-		LPC_EMAC->MAC2    |= MAC2_FULL_DUP;
-		LPC_EMAC->Command |= CR_FULL_DUP;
-		LPC_EMAC->IPGT     = IPGT_FULL_DUP;
-	}
-	else
-	{
-		/* Half duplex mode. */
-		LPC_EMAC->IPGT = IPGT_HALF_DUP;
-	}
+    regv = 0x0004;
+    /* Configure Full/Half Duplex mode. */
+    if (regv & 0x0004)
+    {
+        /* Full duplex is enabled. */
+        LPC_EMAC->MAC2    |= MAC2_FULL_DUP;
+        LPC_EMAC->Command |= CR_FULL_DUP;
+        LPC_EMAC->IPGT     = IPGT_FULL_DUP;
+    }
+    else
+    {
+        /* Half duplex mode. */
+        LPC_EMAC->IPGT = IPGT_HALF_DUP;
+    }
 
-	/* Configure 100MBit/10MBit mode. */
-	if (regv & 0x0002)
-	{
-		/* 10MBit mode. */
-		LPC_EMAC->SUPP = 0;
-	}
-	else
-	{
-		/* 100MBit mode. */
-		LPC_EMAC->SUPP = SUPP_SPEED;
-	}
+    /* Configure 100MBit/10MBit mode. */
+    if (regv & 0x0002)
+    {
+        /* 10MBit mode. */
+        LPC_EMAC->SUPP = 0;
+    }
+    else
+    {
+        /* 100MBit mode. */
+        LPC_EMAC->SUPP = SUPP_SPEED;
+    }
 
-	/* Set the Ethernet MAC Address registers */
-	LPC_EMAC->SA0 = (lpc17xx_emac_device.dev_addr[1]<<8) | lpc17xx_emac_device.dev_addr[0];
-	LPC_EMAC->SA1 = (lpc17xx_emac_device.dev_addr[3]<<8) | lpc17xx_emac_device.dev_addr[2];
-	LPC_EMAC->SA2 = (lpc17xx_emac_device.dev_addr[5]<<8) | lpc17xx_emac_device.dev_addr[4];
+    /* Set the Ethernet MAC Address registers */
+    LPC_EMAC->SA0 = (lpc17xx_emac_device.dev_addr[1]<<8) | lpc17xx_emac_device.dev_addr[0];
+    LPC_EMAC->SA1 = (lpc17xx_emac_device.dev_addr[3]<<8) | lpc17xx_emac_device.dev_addr[2];
+    LPC_EMAC->SA2 = (lpc17xx_emac_device.dev_addr[5]<<8) | lpc17xx_emac_device.dev_addr[4];
 
-	/* Initialize Tx and Rx DMA Descriptors */
-	rx_descr_init ();
-	tx_descr_init ();
+    /* Initialize Tx and Rx DMA Descriptors */
+    rx_descr_init ();
+    tx_descr_init ();
 
-	/* Receive Broadcast and Perfect Match Packets */
-	LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN;
+    /* Receive Broadcast and Perfect Match Packets */
+    LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN;
 
-	/* Reset all interrupts */
-	LPC_EMAC->IntClear  = 0xFFFF;
+    /* Reset all interrupts */
+    LPC_EMAC->IntClear  = 0xFFFF;
 
-	/* Enable EMAC interrupts. */
-	LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
+    /* Enable EMAC interrupts. */
+    LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
 
-	/* Enable receive and transmit mode of MAC Ethernet core */
-	LPC_EMAC->Command  |= (CR_RX_EN | CR_TX_EN);
-	LPC_EMAC->MAC1     |= MAC1_REC_EN;
+    /* Enable receive and transmit mode of MAC Ethernet core */
+    LPC_EMAC->Command  |= (CR_RX_EN | CR_TX_EN);
+    LPC_EMAC->MAC1     |= MAC1_REC_EN;
 
-	/* Enable the ENET Interrupt */
-	NVIC_EnableIRQ(ENET_IRQn);
+    /* Enable the ENET Interrupt */
+    NVIC_EnableIRQ(ENET_IRQn);
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t lpc17xx_emac_open(rt_device_t dev, rt_uint16_t oflag)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t lpc17xx_emac_close(rt_device_t dev)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_size_t lpc17xx_emac_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
 {
-	rt_set_errno(-RT_ENOSYS);
-	return 0;
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
 }
 
 static rt_size_t lpc17xx_emac_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
 {
-	rt_set_errno(-RT_ENOSYS);
-	return 0;
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
 }
 
 static rt_err_t lpc17xx_emac_control(rt_device_t dev, int cmd, void *args)
 {
-	switch (cmd)
-	{
-	case NIOCTL_GADDR:
-		/* get mac address */
-		if (args) rt_memcpy(args, lpc17xx_emac_device.dev_addr, 6);
-		else return -RT_ERROR;
-		break;
+    switch (cmd)
+    {
+    case NIOCTL_GADDR:
+        /* get mac address */
+        if (args) rt_memcpy(args, lpc17xx_emac_device.dev_addr, 6);
+        else return -RT_ERROR;
+        break;
 
-	default :
-		break;
-	}
+    default :
+        break;
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 /* EtherNet Device Interface */
 /* transmit packet. */
 rt_err_t lpc17xx_emac_tx( rt_device_t dev, struct pbuf* p)
 {
-	rt_uint32_t Index, IndexNext;
-	struct pbuf *q;
-	rt_uint8_t *ptr;
+    rt_uint32_t Index, IndexNext;
+    struct pbuf *q;
+    rt_uint8_t *ptr;
 
-	/* calculate next index */
-	IndexNext = LPC_EMAC->TxProduceIndex + 1;
-	if(IndexNext > LPC_EMAC->TxDescriptorNumber) IndexNext = 0;
+    /* calculate next index */
+    IndexNext = LPC_EMAC->TxProduceIndex + 1;
+    if(IndexNext > LPC_EMAC->TxDescriptorNumber) IndexNext = 0;
 
-	/* check whether block is full */
-	while (IndexNext == LPC_EMAC->TxConsumeIndex)
-	{
-		rt_err_t result;
-		rt_uint32_t recved;
+    /* check whether block is full */
+    while (IndexNext == LPC_EMAC->TxConsumeIndex)
+    {
+        rt_err_t result;
+        rt_uint32_t recved;
 
-		/* there is no block yet, wait a flag */
-		result = rt_event_recv(&tx_event, 0x01,
-			RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &recved);
+        /* there is no block yet, wait a flag */
+        result = rt_event_recv(&tx_event, 0x01,
+            RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &recved);
 
-		RT_ASSERT(result == RT_EOK);
-	}
+        RT_ASSERT(result == RT_EOK);
+    }
 
-	/* lock EMAC device */
-	rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
+    /* lock EMAC device */
+    rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
 
-	/* get produce index */
-	Index = LPC_EMAC->TxProduceIndex;
+    /* get produce index */
+    Index = LPC_EMAC->TxProduceIndex;
 
-	/* calculate next index */
-	IndexNext = LPC_EMAC->TxProduceIndex + 1;
-	if(IndexNext > LPC_EMAC->TxDescriptorNumber)
-		IndexNext = 0;
+    /* calculate next index */
+    IndexNext = LPC_EMAC->TxProduceIndex + 1;
+    if(IndexNext > LPC_EMAC->TxDescriptorNumber)
+        IndexNext = 0;
 
-	/* copy data to tx buffer */
-	q = p;
-	ptr = (rt_uint8_t*)TX_BUF(Index);
-	while (q)
-	{
-		memcpy(ptr, q->payload, q->len);
-		ptr += q->len;
-		q = q->next;
-	}
+    /* copy data to tx buffer */
+    q = p;
+    ptr = (rt_uint8_t*)TX_BUF(Index);
+    while (q)
+    {
+        memcpy(ptr, q->payload, q->len);
+        ptr += q->len;
+        q = q->next;
+    }
 
-	TX_DESC_CTRL(Index) &= ~0x7ff;
-	TX_DESC_CTRL(Index) |= (p->tot_len - 1) & 0x7ff;
+    TX_DESC_CTRL(Index) &= ~0x7ff;
+    TX_DESC_CTRL(Index) |= (p->tot_len - 1) & 0x7ff;
 
-	/* change index to the next */
-	LPC_EMAC->TxProduceIndex = IndexNext;
+    /* change index to the next */
+    LPC_EMAC->TxProduceIndex = IndexNext;
 
-	/* unlock EMAC device */
-	rt_sem_release(&sem_lock);
+    /* unlock EMAC device */
+    rt_sem_release(&sem_lock);
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 /* reception packet. */
 struct pbuf *lpc17xx_emac_rx(rt_device_t dev)
 {
-	struct pbuf* p;
-	rt_uint32_t size;
-	rt_uint32_t Index;
+    struct pbuf* p;
+    rt_uint32_t size;
+    rt_uint32_t Index;
 
-	/* init p pointer */
-	p = RT_NULL;
+    /* init p pointer */
+    p = RT_NULL;
 
-	/* lock EMAC device */
-	rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
+    /* lock EMAC device */
+    rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
 
-	Index = LPC_EMAC->RxConsumeIndex;
-	if(Index != LPC_EMAC->RxProduceIndex)
-	{
-		size = (RX_STAT_INFO(Index) & 0x7ff)+1;
-		if (size > ETH_FRAG_SIZE) size = ETH_FRAG_SIZE;
+    Index = LPC_EMAC->RxConsumeIndex;
+    if(Index != LPC_EMAC->RxProduceIndex)
+    {
+        size = (RX_STAT_INFO(Index) & 0x7ff)+1;
+        if (size > ETH_FRAG_SIZE) size = ETH_FRAG_SIZE;
 
-		/* allocate buffer */
-		p = pbuf_alloc(PBUF_LINK, size, PBUF_RAM);
-		if (p != RT_NULL)
-		{
-			struct pbuf* q;
-			rt_uint8_t *ptr;
+        /* allocate buffer */
+        p = pbuf_alloc(PBUF_LINK, size, PBUF_RAM);
+        if (p != RT_NULL)
+        {
+            struct pbuf* q;
+            rt_uint8_t *ptr;
 
-			ptr = (rt_uint8_t*)RX_BUF(Index);
-			for (q = p; q != RT_NULL; q= q->next)
-			{
-				memcpy(q->payload, ptr, q->len);
-				ptr += q->len;
-			}
-		}
+            ptr = (rt_uint8_t*)RX_BUF(Index);
+            for (q = p; q != RT_NULL; q= q->next)
+            {
+                memcpy(q->payload, ptr, q->len);
+                ptr += q->len;
+            }
+        }
 
-		/* move Index to the next */
-		if(++Index > LPC_EMAC->RxDescriptorNumber)
-			Index = 0;
+        /* move Index to the next */
+        if(++Index > LPC_EMAC->RxDescriptorNumber)
+            Index = 0;
 
-		/* set consume index */
-		LPC_EMAC->RxConsumeIndex = Index;
-	}
-	else
-	{
-		/* Enable RxDone interrupt */
-		LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
-	}
+        /* set consume index */
+        LPC_EMAC->RxConsumeIndex = Index;
+    }
+    else
+    {
+        /* Enable RxDone interrupt */
+        LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
+    }
 
-	/* unlock EMAC device */
-	rt_sem_release(&sem_lock);
+    /* unlock EMAC device */
+    rt_sem_release(&sem_lock);
 
-	return p;
+    return p;
 }
 
 void lpc17xx_emac_hw_init(void)
 {
-	rt_event_init(&tx_event, "tx_event", RT_IPC_FLAG_FIFO);
-	rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
+    rt_event_init(&tx_event, "tx_event", RT_IPC_FLAG_FIFO);
+    rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
 
-	/* set autonegotiation mode */
-	lpc17xx_emac_device.phy_mode = EMAC_PHY_AUTO;
+    /* set autonegotiation mode */
+    lpc17xx_emac_device.phy_mode = EMAC_PHY_AUTO;
 
-	// OUI 00-60-37 NXP Semiconductors
-	lpc17xx_emac_device.dev_addr[0] = 0x00;
-	lpc17xx_emac_device.dev_addr[1] = 0x60;
-	lpc17xx_emac_device.dev_addr[2] = 0x37;
-	/* set mac address: (only for test) */
-	lpc17xx_emac_device.dev_addr[3] = 0x12;
-	lpc17xx_emac_device.dev_addr[4] = 0x34;
-	lpc17xx_emac_device.dev_addr[5] = 0x56;
+    // OUI 00-60-37 NXP Semiconductors
+    lpc17xx_emac_device.dev_addr[0] = 0x00;
+    lpc17xx_emac_device.dev_addr[1] = 0x60;
+    lpc17xx_emac_device.dev_addr[2] = 0x37;
+    /* set mac address: (only for test) */
+    lpc17xx_emac_device.dev_addr[3] = 0x12;
+    lpc17xx_emac_device.dev_addr[4] = 0x34;
+    lpc17xx_emac_device.dev_addr[5] = 0x56;
 
-	lpc17xx_emac_device.parent.parent.init		= lpc17xx_emac_init;
-	lpc17xx_emac_device.parent.parent.open		= lpc17xx_emac_open;
-	lpc17xx_emac_device.parent.parent.close		= lpc17xx_emac_close;
-	lpc17xx_emac_device.parent.parent.read		= lpc17xx_emac_read;
-	lpc17xx_emac_device.parent.parent.write		= lpc17xx_emac_write;
-	lpc17xx_emac_device.parent.parent.control	= lpc17xx_emac_control;
-	lpc17xx_emac_device.parent.parent.user_data	= RT_NULL;
+    lpc17xx_emac_device.parent.parent.init      = lpc17xx_emac_init;
+    lpc17xx_emac_device.parent.parent.open      = lpc17xx_emac_open;
+    lpc17xx_emac_device.parent.parent.close     = lpc17xx_emac_close;
+    lpc17xx_emac_device.parent.parent.read      = lpc17xx_emac_read;
+    lpc17xx_emac_device.parent.parent.write     = lpc17xx_emac_write;
+    lpc17xx_emac_device.parent.parent.control   = lpc17xx_emac_control;
+    lpc17xx_emac_device.parent.parent.user_data = RT_NULL;
 
-	lpc17xx_emac_device.parent.eth_rx			= lpc17xx_emac_rx;
-	lpc17xx_emac_device.parent.eth_tx			= lpc17xx_emac_tx;
+    lpc17xx_emac_device.parent.eth_rx           = lpc17xx_emac_rx;
+    lpc17xx_emac_device.parent.eth_tx           = lpc17xx_emac_tx;
 
-	eth_device_init(&(lpc17xx_emac_device.parent), "e0");
+    eth_device_init(&(lpc17xx_emac_device.parent), "e0");
 }
 
 #ifdef RT_USING_FINSH
 #include 
 void emac_dump()
 {
-	rt_kprintf("Command  : %08x\n", LPC_EMAC->Command);
-	rt_kprintf("Status   : %08x\n", LPC_EMAC->Status);
-	rt_kprintf("RxStatus : %08x\n", LPC_EMAC->RxStatus);
-	rt_kprintf("TxStatus : %08x\n", LPC_EMAC->TxStatus);
-	rt_kprintf("IntEnable: %08x\n", LPC_EMAC->IntEnable);
-	rt_kprintf("IntStatus: %08x\n", LPC_EMAC->IntStatus);
+    rt_kprintf("Command  : %08x\n", LPC_EMAC->Command);
+    rt_kprintf("Status   : %08x\n", LPC_EMAC->Status);
+    rt_kprintf("RxStatus : %08x\n", LPC_EMAC->RxStatus);
+    rt_kprintf("TxStatus : %08x\n", LPC_EMAC->TxStatus);
+    rt_kprintf("IntEnable: %08x\n", LPC_EMAC->IntEnable);
+    rt_kprintf("IntStatus: %08x\n", LPC_EMAC->IntStatus);
 }
 FINSH_FUNCTION_EXPORT(emac_dump, dump emac register);
 #endif
diff --git a/bsp/lpc178x/drivers/emac.h b/bsp/lpc178x/drivers/emac.h
index dafcd36e9b..4b89c8ca82 100644
--- a/bsp/lpc178x/drivers/emac.h
+++ b/bsp/lpc178x/drivers/emac.h
@@ -1,3 +1,12 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
 #ifndef __LPC17XX_EMAC_H
 #define __LPC17XX_EMAC_H
 
@@ -11,7 +20,7 @@
 #define ETH_MAX_FLEN        1536        /* Max. Ethernet Frame Size          */
 
 /* EMAC variables located in 16K Ethernet SRAM */
-#define RX_DESC_BASE		0x20000000
+#define RX_DESC_BASE        0x20000000
 #define RX_STAT_BASE        (RX_DESC_BASE + NUM_RX_FRAG*8)
 #define TX_DESC_BASE        (RX_STAT_BASE + NUM_RX_FRAG*8)
 #define TX_STAT_BASE        (TX_DESC_BASE + NUM_TX_FRAG*8)
diff --git a/bsp/lpc178x/drivers/lpc177x_8x_clkpwr.c b/bsp/lpc178x/drivers/lpc177x_8x_clkpwr.c
index ad9bfffeba..3e7abe8b3b 100644
--- a/bsp/lpc178x/drivers/lpc177x_8x_clkpwr.c
+++ b/bsp/lpc178x/drivers/lpc177x_8x_clkpwr.c
@@ -1,13 +1,13 @@
 /**********************************************************************
-* $Id$		lpc177x_8x_clkpwr.c			2011-06-02
+* $Id$      lpc177x_8x_clkpwr.c         2011-06-02
 *//**
-* @file		lpc177x_8x_clkpwr.c
-* @brief	Contains all functions support for Clock and Power Control
-*			firmware library on LPC177x_8x
-* @version	1.0
-* @date		02. June. 2011
-* @author	NXP MCU SW Application Team
-* 
+* @file     lpc177x_8x_clkpwr.c
+* @brief    Contains all functions support for Clock and Power Control
+*           firmware library on LPC177x_8x
+* @version  1.0
+* @date     02. June. 2011
+* @author   NXP MCU SW Application Team
+*
 * Copyright(C) 2011, NXP Semiconductor
 * All rights reserved.
 *
@@ -41,253 +41,253 @@ uint32_t SPIFIFrequency = 0;
  */
 
 /*********************************************************************//**
- * @brief 		Set value of each Peripheral Clock Selection
- * @param[in]	ClkType clock type that will be divided, should be:
- * 				- CLKPWR_CLKTYPE_CPU 		: CPU clock
- * 				- CLKPWR_CLKTYPE_PER		: Peripheral clock
- * 				- CLKPWR_CLKTYPE_EMC 		: EMC clock
- * 				- CLKPWR_CLKTYPE_USB 		: USB clock
- * @param[in]	DivVal	Value of divider. This value should be set as follows:
- * 					- CPU clock: DivVal must be in range: 0..31
- * 					- Peripheral clock: DivVal must be in range: 0..31
- * 					- EMC clock: DivVal must be:
- * 							+ 0: The EMC uses the same clock as the CPU
- * 							+ 1: The EMC uses a clock at half the rate of the CPU
- *   				- USB clock: DivVal must be:
- * 							+ 0: the divider is turned off, no clock will
- * 								 be provided to the USB subsystem
- * 							+ 4: PLL0 output is divided by 4. PLL0 output must be 192MHz
- * 							+ 6: PLL0 output is divided by 6. PLL0 output must be 288MHz
+ * @brief       Set value of each Peripheral Clock Selection
+ * @param[in]   ClkType clock type that will be divided, should be:
+ *              - CLKPWR_CLKTYPE_CPU        : CPU clock
+ *              - CLKPWR_CLKTYPE_PER        : Peripheral clock
+ *              - CLKPWR_CLKTYPE_EMC        : EMC clock
+ *              - CLKPWR_CLKTYPE_USB        : USB clock
+ * @param[in]   DivVal  Value of divider. This value should be set as follows:
+ *                  - CPU clock: DivVal must be in range: 0..31
+ *                  - Peripheral clock: DivVal must be in range: 0..31
+ *                  - EMC clock: DivVal must be:
+ *                          + 0: The EMC uses the same clock as the CPU
+ *                          + 1: The EMC uses a clock at half the rate of the CPU
+ *                  - USB clock: DivVal must be:
+ *                          + 0: the divider is turned off, no clock will
+ *                               be provided to the USB subsystem
+ *                          + 4: PLL0 output is divided by 4. PLL0 output must be 192MHz
+ *                          + 6: PLL0 output is divided by 6. PLL0 output must be 288MHz
  * @return none
  * Note: Pls assign right DivVal, this function will not check if it is illegal.
  **********************************************************************/
 void CLKPWR_SetCLKDiv (uint8_t ClkType, uint8_t DivVal)
 {
-	switch(ClkType)
-	{
-	case CLKPWR_CLKTYPE_CPU:
-		LPC_SC->CCLKSEL = DivVal;
-		SystemCoreClockUpdate(); //Update clock
-		break;
-	case CLKPWR_CLKTYPE_PER:
-		LPC_SC->PCLKSEL = DivVal;
-		SystemCoreClockUpdate(); //Update clock
-		break;
-	case CLKPWR_CLKTYPE_EMC:
-		LPC_SC->EMCCLKSEL = DivVal;
-		SystemCoreClockUpdate(); //Update clock
-		break;
-	case CLKPWR_CLKTYPE_USB:
-		LPC_SC->USBCLKSEL &= ~(0x0000001F);
-		LPC_SC->USBCLKSEL |= DivVal;
-		break;
-	default:
-		while(1);//Error Loop;
-	}
+    switch(ClkType)
+    {
+    case CLKPWR_CLKTYPE_CPU:
+        LPC_SC->CCLKSEL = DivVal;
+        SystemCoreClockUpdate(); //Update clock
+        break;
+    case CLKPWR_CLKTYPE_PER:
+        LPC_SC->PCLKSEL = DivVal;
+        SystemCoreClockUpdate(); //Update clock
+        break;
+    case CLKPWR_CLKTYPE_EMC:
+        LPC_SC->EMCCLKSEL = DivVal;
+        SystemCoreClockUpdate(); //Update clock
+        break;
+    case CLKPWR_CLKTYPE_USB:
+        LPC_SC->USBCLKSEL &= ~(0x0000001F);
+        LPC_SC->USBCLKSEL |= DivVal;
+        break;
+    default:
+        while(1);//Error Loop;
+    }
 }
 
 /*********************************************************************//**
- * @brief 		Get current clock value
- * @param[in]	ClkType clock type that will be divided, should be:
- * 				- CLKPWR_CLKTYPE_CPU 		: CPU clock
- * 				- CLKPWR_CLKTYPE_PER		: Peripheral clock
- * 				- CLKPWR_CLKTYPE_EMC 		: EMC clock
- * 				- CLKPWR_CLKTYPE_USB 		: USB clock
+ * @brief       Get current clock value
+ * @param[in]   ClkType clock type that will be divided, should be:
+ *              - CLKPWR_CLKTYPE_CPU        : CPU clock
+ *              - CLKPWR_CLKTYPE_PER        : Peripheral clock
+ *              - CLKPWR_CLKTYPE_EMC        : EMC clock
+ *              - CLKPWR_CLKTYPE_USB        : USB clock
  **********************************************************************/
 uint32_t CLKPWR_GetCLK (uint8_t ClkType)
 {
-	switch(ClkType)
-	{
-		case CLKPWR_CLKTYPE_CPU:
-			return SystemCoreClock;
+    switch(ClkType)
+    {
+        case CLKPWR_CLKTYPE_CPU:
+            return SystemCoreClock;
 
-		case CLKPWR_CLKTYPE_PER:
-			return PeripheralClock;
+        case CLKPWR_CLKTYPE_PER:
+            return PeripheralClock;
 
-		case CLKPWR_CLKTYPE_EMC:
-			return EMCClock;
+        case CLKPWR_CLKTYPE_EMC:
+            return EMCClock;
 
-		case CLKPWR_CLKTYPE_USB:
-			return USBClock;
+        case CLKPWR_CLKTYPE_USB:
+            return USBClock;
 
-		default:
-			while(1);//error loop
-	}
+        default:
+            while(1);//error loop
+    }
 }
 
 /*********************************************************************//**
- * @brief 		Configure power supply for each peripheral according to NewState
- * @param[in]	PPType	Type of peripheral used to enable power,
- *     			should be one of the following:
- *     			-  CLKPWR_PCONP_PCLCD		: LCD
- *     			-  CLKPWR_PCONP_PCTIM0 		: Timer 0
-				-  CLKPWR_PCONP_PCTIM1 		: Timer 1
-				-  CLKPWR_PCONP_PCUART0  	: UART 0
-				-  CLKPWR_PCONP_PCUART1   	: UART 1
-				-  CLKPWR_PCONP_PCPWM0		: PWM 0
-				-  CLKPWR_PCONP_PCPWM1 		: PWM 1
-				-  CLKPWR_PCONP_PCI2C0 		: I2C 0
-				-  CLKPWR_PCONP_PCUART4		: UART4
-				-  CLKPWR_PCONP_PCRTC   	: RTC
-				-  CLKPWR_PCONP_PCSSP1 		: SSP 1
-				-  CLKPWR_PCONP_PCEMC		: EMC
-				-  CLKPWR_PCONP_PCADC   		: ADC
-				-  CLKPWR_PCONP_PCAN1   	: CAN 1
-				-  CLKPWR_PCONP_PCAN2   	: CAN 2
-				-  CLKPWR_PCONP_PCGPIO 		: GPIO
-				-  CLKPWR_PCONP_PCMC 		: MCPWM
-				-  CLKPWR_PCONP_PCQEI 		: QEI
-				-  CLKPWR_PCONP_PCI2C1   	: I2C 1
-				-  CLKPWR_PCONP_PCSSP2		: SSP 2
-				-  CLKPWR_PCONP_PCSSP0 		: SSP 0
-				-  CLKPWR_PCONP_PCTIM2 		: Timer 2
-				-  CLKPWR_PCONP_PCTIM3 		: Timer 3
-				-  CLKPWR_PCONP_PCUART2  	: UART 2
-				-  CLKPWR_PCONP_PCUART3   	: UART 3
-				-  CLKPWR_PCONP_PCI2C2 		: I2C 2
-				-  CLKPWR_PCONP_PCI2S   	: I2S
-				-  CLKPWR_PCONP_PCSDC		: SDC
-				-  CLKPWR_PCONP_PCGPDMA   	: GPDMA
-				-  CLKPWR_PCONP_PCENET 		: Ethernet
-				-  CLKPWR_PCONP_PCUSB   	: USB
+ * @brief       Configure power supply for each peripheral according to NewState
+ * @param[in]   PPType  Type of peripheral used to enable power,
+ *              should be one of the following:
+ *              -  CLKPWR_PCONP_PCLCD       : LCD
+ *              -  CLKPWR_PCONP_PCTIM0      : Timer 0
+                -  CLKPWR_PCONP_PCTIM1      : Timer 1
+                -  CLKPWR_PCONP_PCUART0     : UART 0
+                -  CLKPWR_PCONP_PCUART1     : UART 1
+                -  CLKPWR_PCONP_PCPWM0      : PWM 0
+                -  CLKPWR_PCONP_PCPWM1      : PWM 1
+                -  CLKPWR_PCONP_PCI2C0      : I2C 0
+                -  CLKPWR_PCONP_PCUART4     : UART4
+                -  CLKPWR_PCONP_PCRTC       : RTC
+                -  CLKPWR_PCONP_PCSSP1      : SSP 1
+                -  CLKPWR_PCONP_PCEMC       : EMC
+                -  CLKPWR_PCONP_PCADC           : ADC
+                -  CLKPWR_PCONP_PCAN1       : CAN 1
+                -  CLKPWR_PCONP_PCAN2       : CAN 2
+                -  CLKPWR_PCONP_PCGPIO      : GPIO
+                -  CLKPWR_PCONP_PCMC        : MCPWM
+                -  CLKPWR_PCONP_PCQEI       : QEI
+                -  CLKPWR_PCONP_PCI2C1      : I2C 1
+                -  CLKPWR_PCONP_PCSSP2      : SSP 2
+                -  CLKPWR_PCONP_PCSSP0      : SSP 0
+                -  CLKPWR_PCONP_PCTIM2      : Timer 2
+                -  CLKPWR_PCONP_PCTIM3      : Timer 3
+                -  CLKPWR_PCONP_PCUART2     : UART 2
+                -  CLKPWR_PCONP_PCUART3     : UART 3
+                -  CLKPWR_PCONP_PCI2C2      : I2C 2
+                -  CLKPWR_PCONP_PCI2S       : I2S
+                -  CLKPWR_PCONP_PCSDC       : SDC
+                -  CLKPWR_PCONP_PCGPDMA     : GPDMA
+                -  CLKPWR_PCONP_PCENET      : Ethernet
+                -  CLKPWR_PCONP_PCUSB       : USB
  *
- * @param[in]	NewState	New state of Peripheral Power, should be:
- * 				- ENABLE	: Enable power for this peripheral
- * 				- DISABLE	: Disable power for this peripheral
+ * @param[in]   NewState    New state of Peripheral Power, should be:
+ *              - ENABLE    : Enable power for this peripheral
+ *              - DISABLE   : Disable power for this peripheral
  *
  * @return none
  **********************************************************************/
 void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState)
 {
-	if (NewState == ENABLE)
-	{
-		LPC_SC->PCONP |= PPType;
-	}
-	else if (NewState == DISABLE)
-	{
-		LPC_SC->PCONP &= ~PPType;
-	}
+    if (NewState == ENABLE)
+    {
+        LPC_SC->PCONP |= PPType;
+    }
+    else if (NewState == DISABLE)
+    {
+        LPC_SC->PCONP &= ~PPType;
+    }
 }
 
 #if 0
 // nxp21346
 /*********************************************************************//**
- * @brief 		Configure hardware reset for each peripheral according to NewState
- * @param[in]	PPType	Type of peripheral used to enable power,
- *     			should be one of the following:
- *     			-  CLKPWR_RSTCON0_LCD		: LCD
- *     			-  CLKPWR_RSTCON0_TIM0 		: Timer 0
-				-  CLKPWR_RSTCON0_TIM1 		: Timer 1
-				-  CLKPWR_RSTCON0_UART0  	: UART 0
-				-  CLKPWR_RSTCON0_UART1   	: UART 1
-				-  CLKPWR_RSTCON0_PWM0 		: PWM 0
-				-  CLKPWR_RSTCON0_PWM1 		: PWM 1
-				-  CLKPWR_RSTCON0_I2C0		: I2C 0
-				-  CLKPWR_RSTCON0_UART4   	: UART 4
-				-  CLKPWR_RSTCON0_RTC 		: RTC
-				-  CLKPWR_RSTCON0_SSP1		: SSP 1
-				-  CLKPWR_RSTCON0_EMC   	: EMC
-				-  CLKPWR_RSTCON0_ADC   	: ADC
-				-  CLKPWR_RSTCON0_CAN1   	: CAN 1
-				-  CLKPWR_RSTCON0_CAN2 		: CAN 2
-				-  CLKPWR_RSTCON0_GPIO 		: GPIO
-				-  CLKPWR_RSTCON0_MCPWM 	: MCPWM
-				-  CLKPWR_RSTCON0_QEI   	: QEI
-				-  CLKPWR_RSTCON0_I2C1		: I2C 1
-				-  CLKPWR_RSTCON0_SSP2 		: SSP 2
-				-  CLKPWR_RSTCON0_SSP0 		: SSP 0
-				-  CLKPWR_RSTCON0_TIM2 		: Timer 2
-				-  CLKPWR_RSTCON0_TIM3  	: Timer 3
-				-  CLKPWR_RSTCON0_UART2  	: UART 2
-				-  CLKPWR_RSTCON0_UART3   	: UART 3
-				-  CLKPWR_RSTCON0_I2C2 		: I2C 2
-				-  CLKPWR_RSTCON0_I2S   	: I2S
-				-  CLKPWR_RSTCON0_SDC		: SDC
-				-  CLKPWR_RSTCON0_GPDMA   	: GPDMA
-				-  CLKPWR_RSTCON0_ENET 		: Ethernet
-				-  CLKPWR_RSTCON0_USB   	: USB
+ * @brief       Configure hardware reset for each peripheral according to NewState
+ * @param[in]   PPType  Type of peripheral used to enable power,
+ *              should be one of the following:
+ *              -  CLKPWR_RSTCON0_LCD       : LCD
+ *              -  CLKPWR_RSTCON0_TIM0      : Timer 0
+                -  CLKPWR_RSTCON0_TIM1      : Timer 1
+                -  CLKPWR_RSTCON0_UART0     : UART 0
+                -  CLKPWR_RSTCON0_UART1     : UART 1
+                -  CLKPWR_RSTCON0_PWM0      : PWM 0
+                -  CLKPWR_RSTCON0_PWM1      : PWM 1
+                -  CLKPWR_RSTCON0_I2C0      : I2C 0
+                -  CLKPWR_RSTCON0_UART4     : UART 4
+                -  CLKPWR_RSTCON0_RTC       : RTC
+                -  CLKPWR_RSTCON0_SSP1      : SSP 1
+                -  CLKPWR_RSTCON0_EMC       : EMC
+                -  CLKPWR_RSTCON0_ADC       : ADC
+                -  CLKPWR_RSTCON0_CAN1      : CAN 1
+                -  CLKPWR_RSTCON0_CAN2      : CAN 2
+                -  CLKPWR_RSTCON0_GPIO      : GPIO
+                -  CLKPWR_RSTCON0_MCPWM     : MCPWM
+                -  CLKPWR_RSTCON0_QEI       : QEI
+                -  CLKPWR_RSTCON0_I2C1      : I2C 1
+                -  CLKPWR_RSTCON0_SSP2      : SSP 2
+                -  CLKPWR_RSTCON0_SSP0      : SSP 0
+                -  CLKPWR_RSTCON0_TIM2      : Timer 2
+                -  CLKPWR_RSTCON0_TIM3      : Timer 3
+                -  CLKPWR_RSTCON0_UART2     : UART 2
+                -  CLKPWR_RSTCON0_UART3     : UART 3
+                -  CLKPWR_RSTCON0_I2C2      : I2C 2
+                -  CLKPWR_RSTCON0_I2S       : I2S
+                -  CLKPWR_RSTCON0_SDC       : SDC
+                -  CLKPWR_RSTCON0_GPDMA     : GPDMA
+                -  CLKPWR_RSTCON0_ENET      : Ethernet
+                -  CLKPWR_RSTCON0_USB       : USB
  *
- * @param[in]	NewState	New state of Peripheral Power, should be:
- * 				- ENABLE	: Enable power for this peripheral
- * 				- DISABLE	: Disable power for this peripheral
+ * @param[in]   NewState    New state of Peripheral Power, should be:
+ *              - ENABLE    : Enable power for this peripheral
+ *              - DISABLE   : Disable power for this peripheral
  *
  * @return none
  **********************************************************************/
 void CLKPWR_ConfigReset(uint8_t PType, FunctionalState NewState)
 {
-	if(PType < 32)
-	{
-		if(NewState == ENABLE)
-			LPC_SC->RSTCON0 |=(1<RSTCON0 &=~(1<RSTCON1 |= (1<<(PType - 31));
-		else
-			LPC_SC->RSTCON1 &= ~(1<<(PType - 31));
-	}
+    if(PType < 32)
+    {
+        if(NewState == ENABLE)
+            LPC_SC->RSTCON0 |=(1<RSTCON0 &=~(1<RSTCON1 |= (1<<(PType - 31));
+        else
+            LPC_SC->RSTCON1 &= ~(1<<(PType - 31));
+    }
 }
 // nxp21346
 #endif
 
 /*********************************************************************//**
- * @brief 		Enter Sleep mode with co-operated instruction by the Cortex-M3.
- * @param[in]	None
- * @return		None
+ * @brief       Enter Sleep mode with co-operated instruction by the Cortex-M3.
+ * @param[in]   None
+ * @return      None
  **********************************************************************/
 void CLKPWR_Sleep(void)
 {
-	LPC_SC->PCON = 0x00;
-	/* Sleep Mode*/
-	__WFI();
+    LPC_SC->PCON = 0x00;
+    /* Sleep Mode*/
+    __WFI();
 }
 
 
 /*********************************************************************//**
- * @brief 		Enter Deep Sleep mode with co-operated instruction by the Cortex-M3.
- * @param[in]	None
- * @return		None
+ * @brief       Enter Deep Sleep mode with co-operated instruction by the Cortex-M3.
+ * @param[in]   None
+ * @return      None
  **********************************************************************/
 void CLKPWR_DeepSleep(void)
 {
     /* Deep-Sleep Mode, set SLEEPDEEP bit */
-	SCB->SCR = 0x4;
-	LPC_SC->PCON = 0x8;
-	/* Deep Sleep Mode*/
-	__WFI();
+    SCB->SCR = 0x4;
+    LPC_SC->PCON = 0x8;
+    /* Deep Sleep Mode*/
+    __WFI();
 }
 
 
 /*********************************************************************//**
- * @brief 		Enter Power Down mode with co-operated instruction by the Cortex-M3.
- * @param[in]	None
- * @return		None
+ * @brief       Enter Power Down mode with co-operated instruction by the Cortex-M3.
+ * @param[in]   None
+ * @return      None
  **********************************************************************/
 void CLKPWR_PowerDown(void)
 {
     /* Deep-Sleep Mode, set SLEEPDEEP bit */
-	SCB->SCR = 0x4;
-	LPC_SC->PCON = 0x09;
-	/* Power Down Mode*/
-	__WFI();
+    SCB->SCR = 0x4;
+    LPC_SC->PCON = 0x09;
+    /* Power Down Mode*/
+    __WFI();
 }
 
 
 /*********************************************************************//**
- * @brief 		Enter Deep Power Down mode with co-operated instruction by the Cortex-M3.
- * @param[in]	None
- * @return		None
+ * @brief       Enter Deep Power Down mode with co-operated instruction by the Cortex-M3.
+ * @param[in]   None
+ * @return      None
  **********************************************************************/
 void CLKPWR_DeepPowerDown(void)
 {
     /* Deep-Sleep Mode, set SLEEPDEEP bit */
-	SCB->SCR = 0x4;
-	LPC_SC->PCON = 0x03;
-	/* Deep Power Down Mode*/
-	__WFI();
+    SCB->SCR = 0x4;
+    LPC_SC->PCON = 0x03;
+    /* Deep Power Down Mode*/
+    __WFI();
 }
 
 /**
diff --git a/bsp/lpc178x/drivers/lpc177x_8x_clkpwr.h b/bsp/lpc178x/drivers/lpc177x_8x_clkpwr.h
index 427ccc0279..b1bf670b52 100644
--- a/bsp/lpc178x/drivers/lpc177x_8x_clkpwr.h
+++ b/bsp/lpc178x/drivers/lpc177x_8x_clkpwr.h
@@ -1,14 +1,14 @@
 /**********************************************************************
-* $Id$		lpc177x_8x_clkpwr.h			2011-06-02
+* $Id$      lpc177x_8x_clkpwr.h         2011-06-02
 *//**
-* @file		lpc177x_8x_clkpwr.h
-* @brief	Contains all macro definitions and function prototypes
-*			support for Clock and Power Control firmware library on 
-*			LPC177x_8x
-* @version	1.0
-* @date		02. June. 2011
-* @author	NXP MCU SW Application Team
-* 
+* @file     lpc177x_8x_clkpwr.h
+* @brief    Contains all macro definitions and function prototypes
+*           support for Clock and Power Control firmware library on
+*           LPC177x_8x
+* @version  1.0
+* @date     02. June. 2011
+* @author   NXP MCU SW Application Team
+*
 * Copyright(C) 2011, NXP Semiconductor
 * All rights reserved.
 *
@@ -26,7 +26,7 @@
 **********************************************************************/
 
 /* Peripheral group ----------------------------------------------------------- */
-/** @defgroup CLKPWR	Clock Power
+/** @defgroup CLKPWR    Clock Power
  * @ingroup LPC177x_8xCMSIS_FwLib_Drivers
  * @{
  */
@@ -52,163 +52,163 @@ extern "C"
 /********************************************************************
 * Clock Source Selection Definitions
 **********************************************************************/
-#define CLKPWR_CLKSRCSEL_IRCOSC		((uint32_t)(0))
-#define CLKPWR_CLKSRCSEL_MAINOSC	((uint32_t)(1))
+#define CLKPWR_CLKSRCSEL_IRCOSC     ((uint32_t)(0))
+#define CLKPWR_CLKSRCSEL_MAINOSC    ((uint32_t)(1))
 
 /********************************************************************
 * Clock type/domain Definitions (calculated from input and pre-configuration
 * parameter(s)
 **********************************************************************/
-#define CLKPWR_CLKTYPE_CPU			((uint32_t)(0))
-#define CLKPWR_CLKTYPE_PER			((uint32_t)(1))
-#define CLKPWR_CLKTYPE_EMC			((uint32_t)(2))
-#define CLKPWR_CLKTYPE_USB			((uint32_t)(3))
+#define CLKPWR_CLKTYPE_CPU          ((uint32_t)(0))
+#define CLKPWR_CLKTYPE_PER          ((uint32_t)(1))
+#define CLKPWR_CLKTYPE_EMC          ((uint32_t)(2))
+#define CLKPWR_CLKTYPE_USB          ((uint32_t)(3))
 
 /********************************************************************
 * Power Control for Peripherals Definitions
 **********************************************************************/
 /** LCD controller power/clock control bit */
-#define CLKPWR_PCONP_PCLCD		((uint32_t)(1<<0))
+#define CLKPWR_PCONP_PCLCD      ((uint32_t)(1<<0))
 
 /** Timer/Counter 0 power/clock control bit */
-#define	CLKPWR_PCONP_PCTIM0		((uint32_t)(1<<1))
+#define CLKPWR_PCONP_PCTIM0     ((uint32_t)(1<<1))
 
 /* Timer/Counter 1 power/clock control bit */
-#define	CLKPWR_PCONP_PCTIM1		((uint32_t)(1<<2))
+#define CLKPWR_PCONP_PCTIM1     ((uint32_t)(1<<2))
 
 /** UART0 power/clock control bit */
-#define	CLKPWR_PCONP_PCUART0  	((uint32_t)(1<<3))
+#define CLKPWR_PCONP_PCUART0    ((uint32_t)(1<<3))
 
 /** UART1 power/clock control bit */
-#define	CLKPWR_PCONP_PCUART1  	((uint32_t)(1<<4))
+#define CLKPWR_PCONP_PCUART1    ((uint32_t)(1<<4))
 
 /** PWM0 power/clock control bit */
-#define CLKPWR_PCONP_PCPWM0		((uint32_t)(1<<5))
+#define CLKPWR_PCONP_PCPWM0     ((uint32_t)(1<<5))
 
 /** PWM1 power/clock control bit */
-#define	CLKPWR_PCONP_PCPWM1		((uint32_t)(1<<6))
+#define CLKPWR_PCONP_PCPWM1     ((uint32_t)(1<<6))
 
 /** The I2C0 interface power/clock control bit */
-#define	CLKPWR_PCONP_PCI2C0		((uint32_t)(1<<7))
+#define CLKPWR_PCONP_PCI2C0     ((uint32_t)(1<<7))
 
 /** UART4 power/clock control bit */
-#define CLKPWR_PCONP_PCUART4	((uint32_t)(1<<8))
+#define CLKPWR_PCONP_PCUART4    ((uint32_t)(1<<8))
 
 /** The RTC power/clock control bit */
-#define	CLKPWR_PCONP_PCRTC  	((uint32_t)(1<<9))
+#define CLKPWR_PCONP_PCRTC      ((uint32_t)(1<<9))
 
 /** The SSP1 interface power/clock control bit */
-#define	CLKPWR_PCONP_PCSSP1	 	((uint32_t)(1<<10))
+#define CLKPWR_PCONP_PCSSP1     ((uint32_t)(1<<10))
 
 /** External Memory controller power/clock control bit */
-#define CLKPWR_PCONP_PCEMC		((uint32_t)(1<<11))
+#define CLKPWR_PCONP_PCEMC      ((uint32_t)(1<<11))
 
 /** A/D converter 0 (ADC0) power/clock control bit */
-#define	CLKPWR_PCONP_PCADC  	((uint32_t)(1<<12))
+#define CLKPWR_PCONP_PCADC      ((uint32_t)(1<<12))
 
 /** CAN Controller 1 power/clock control bit */
-#define	CLKPWR_PCONP_PCAN1  	((uint32_t)(1<<13))
+#define CLKPWR_PCONP_PCAN1      ((uint32_t)(1<<13))
 
 /** CAN Controller 2 power/clock control bit */
-#define	CLKPWR_PCONP_PCAN2 	((uint32_t)(1<<14))
+#define CLKPWR_PCONP_PCAN2  ((uint32_t)(1<<14))
 
 /** GPIO power/clock control bit */
-#define	CLKPWR_PCONP_PCGPIO 	((uint32_t)(1<<15))
+#define CLKPWR_PCONP_PCGPIO     ((uint32_t)(1<<15))
 
 /** Motor Control PWM */
-#define CLKPWR_PCONP_PCMCPWM 	((uint32_t)(1<<17))
+#define CLKPWR_PCONP_PCMCPWM    ((uint32_t)(1<<17))
 
 /** Quadrature Encoder Interface power/clock control bit */
-#define CLKPWR_PCONP_PCQEI 		((uint32_t)(1<<18))
+#define CLKPWR_PCONP_PCQEI      ((uint32_t)(1<<18))
 
 /** The I2C1 interface power/clock control bit */
-#define	CLKPWR_PCONP_PCI2C1  	((uint32_t)(1<<19))
+#define CLKPWR_PCONP_PCI2C1     ((uint32_t)(1<<19))
 
 /** The SSP2 interface power/clock control bit */
-#define CLKPWR_PCONP_PCSSP2		((uint32_t)(1<<20))
+#define CLKPWR_PCONP_PCSSP2     ((uint32_t)(1<<20))
 
 /** The SSP0 interface power/clock control bit */
-#define	CLKPWR_PCONP_PCSSP0		((uint32_t)(1<<21))
+#define CLKPWR_PCONP_PCSSP0     ((uint32_t)(1<<21))
 
 /** Timer 2 power/clock control bit */
-#define	CLKPWR_PCONP_PCTIM2	((uint32_t)(1<<22))
+#define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22))
 
 /** Timer 3 power/clock control bit */
-#define	CLKPWR_PCONP_PCTIM3	((uint32_t)(1<<23))
+#define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23))
 
 /** UART 2 power/clock control bit */
-#define	CLKPWR_PCONP_PCUART2  	((uint32_t)(1<<24))
+#define CLKPWR_PCONP_PCUART2    ((uint32_t)(1<<24))
 
 /** UART 3 power/clock control bit */
-#define	CLKPWR_PCONP_PCUART3  	((uint32_t)(1<<25))
+#define CLKPWR_PCONP_PCUART3    ((uint32_t)(1<<25))
 
 /** I2C interface 2 power/clock control bit */
-#define	CLKPWR_PCONP_PCI2C2	((uint32_t)(1<<26))
+#define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26))
 
 /** I2S interface power/clock control bit*/
-#define	CLKPWR_PCONP_PCI2S  	((uint32_t)(1<<27))
+#define CLKPWR_PCONP_PCI2S      ((uint32_t)(1<<27))
 
 /** SD card interface power/clock control bit */
-#define CLKPWR_PCONP_PCSDC		((uint32_t)(1<<28))
+#define CLKPWR_PCONP_PCSDC      ((uint32_t)(1<<28))
 
 /** GP DMA function power/clock control bit*/
-#define	 CLKPWR_PCONP_PCGPDMA  	((uint32_t)(1<<29))
+#define  CLKPWR_PCONP_PCGPDMA   ((uint32_t)(1<<29))
 
 /** Ethernet block power/clock control bit*/
-#define	 CLKPWR_PCONP_PCENET	((uint32_t)(1<<30))
+#define  CLKPWR_PCONP_PCENET    ((uint32_t)(1<<30))
 
 /** USB interface power/clock control bit*/
-#define	 CLKPWR_PCONP_PCUSB  	((uint32_t)(1<<31))
+#define  CLKPWR_PCONP_PCUSB     ((uint32_t)(1<<31))
 
 /********************************************************************
 * Power Control for Peripherals Definitions
 **********************************************************************/
-#define CLKPWR_RSTCON0_LCD		((uint32_t)(0))
-#define CLKPWR_RSTCON0_TIM0		((uint32_t)(1))
-#define CLKPWR_RSTCON0_TIM1		((uint32_t)(2))
-#define CLKPWR_RSTCON0_UART0	((uint32_t)(3))
-#define CLKPWR_RSTCON0_UART1	((uint32_t)(4))
-#define CLKPWR_RSTCON0_PWM0		((uint32_t)(5))
-#define CLKPWR_RSTCON0_PWM1		((uint32_t)(6))
-#define CLKPWR_RSTCON0_I2C0		((uint32_t)(7))
-#define CLKPWR_RSTCON0_UART4	((uint32_t)(8))
-#define CLKPWR_RSTCON0_RTC		((uint32_t)(9))
-#define CLKPWR_RSTCON0_SSP1		((uint32_t)(10))
-#define CLKPWR_RSTCON0_EMC		((uint32_t)(11))
-#define CLKPWR_RSTCON0_ADC		((uint32_t)(12))
-#define CLKPWR_RSTCON0_CAN1		((uint32_t)(13))
-#define CLKPWR_RSTCON0_CAN2		((uint32_t)(14))
-#define CLKPWR_RSTCON0_GPIO		((uint32_t)(15))
-#define CLKPWR_RSTCON0_MCPWM	((uint32_t)(17))
-#define CLKPWR_RSTCON0_QEI		((uint32_t)(18))
-#define CLKPWR_RSTCON0_I2C1		((uint32_t)(19))
-#define CLKPWR_RSTCON0_SSP2		((uint32_t)(20))
-#define CLKPWR_RSTCON0_SSP0		((uint32_t)(21))
-#define CLKPWR_RSTCON0_TIM2		((uint32_t)(22))
-#define CLKPWR_RSTCON0_TIM3		((uint32_t)(23))
-#define CLKPWR_RSTCON0_UART2	((uint32_t)(24))
-#define CLKPWR_RSTCON0_UART3	((uint32_t)(25))
-#define CLKPWR_RSTCON0_I2C2		((uint32_t)(26))
-#define CLKPWR_RSTCON0_I2S		((uint32_t)(27))
-#define CLKPWR_RSTCON0_SDC		((uint32_t)(28))
-#define CLKPWR_RSTCON0_GPDMA	((uint32_t)(29))
-#define CLKPWR_RSTCON0_ENET		((uint32_t)(30))
-#define CLKPWR_RSTCON0_USB		((uint32_t)(31))
+#define CLKPWR_RSTCON0_LCD      ((uint32_t)(0))
+#define CLKPWR_RSTCON0_TIM0     ((uint32_t)(1))
+#define CLKPWR_RSTCON0_TIM1     ((uint32_t)(2))
+#define CLKPWR_RSTCON0_UART0    ((uint32_t)(3))
+#define CLKPWR_RSTCON0_UART1    ((uint32_t)(4))
+#define CLKPWR_RSTCON0_PWM0     ((uint32_t)(5))
+#define CLKPWR_RSTCON0_PWM1     ((uint32_t)(6))
+#define CLKPWR_RSTCON0_I2C0     ((uint32_t)(7))
+#define CLKPWR_RSTCON0_UART4    ((uint32_t)(8))
+#define CLKPWR_RSTCON0_RTC      ((uint32_t)(9))
+#define CLKPWR_RSTCON0_SSP1     ((uint32_t)(10))
+#define CLKPWR_RSTCON0_EMC      ((uint32_t)(11))
+#define CLKPWR_RSTCON0_ADC      ((uint32_t)(12))
+#define CLKPWR_RSTCON0_CAN1     ((uint32_t)(13))
+#define CLKPWR_RSTCON0_CAN2     ((uint32_t)(14))
+#define CLKPWR_RSTCON0_GPIO     ((uint32_t)(15))
+#define CLKPWR_RSTCON0_MCPWM    ((uint32_t)(17))
+#define CLKPWR_RSTCON0_QEI      ((uint32_t)(18))
+#define CLKPWR_RSTCON0_I2C1     ((uint32_t)(19))
+#define CLKPWR_RSTCON0_SSP2     ((uint32_t)(20))
+#define CLKPWR_RSTCON0_SSP0     ((uint32_t)(21))
+#define CLKPWR_RSTCON0_TIM2     ((uint32_t)(22))
+#define CLKPWR_RSTCON0_TIM3     ((uint32_t)(23))
+#define CLKPWR_RSTCON0_UART2    ((uint32_t)(24))
+#define CLKPWR_RSTCON0_UART3    ((uint32_t)(25))
+#define CLKPWR_RSTCON0_I2C2     ((uint32_t)(26))
+#define CLKPWR_RSTCON0_I2S      ((uint32_t)(27))
+#define CLKPWR_RSTCON0_SDC      ((uint32_t)(28))
+#define CLKPWR_RSTCON0_GPDMA    ((uint32_t)(29))
+#define CLKPWR_RSTCON0_ENET     ((uint32_t)(30))
+#define CLKPWR_RSTCON0_USB      ((uint32_t)(31))
 
-#define CLKPWR_RSTCON1_IOCON	((uint32_t)(32))
-#define CLKPWR_RSTCON1_DAC		((uint32_t)(33))
-#define CLKPWR_RSTCON1_CANACC	((uint32_t)(34))
+#define CLKPWR_RSTCON1_IOCON    ((uint32_t)(32))
+#define CLKPWR_RSTCON1_DAC      ((uint32_t)(33))
+#define CLKPWR_RSTCON1_CANACC   ((uint32_t)(34))
 /**
  * @}
  */
- 
+
 /* External clock variable from system_LPC177x_8x.h */
-extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  	*/
-extern uint32_t PeripheralClock;	 /*!< Peripheral Clock Frequency (Pclk) 	*/
-extern uint32_t EMCClock;		 /*!< EMC Clock Frequency                   	*/
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)   */
+extern uint32_t PeripheralClock;     /*!< Peripheral Clock Frequency (Pclk)     */
+extern uint32_t EMCClock;        /*!< EMC Clock Frequency                       */
 
 /* External clock variable from lpc177x_8x_clkpwr.h */
-extern uint32_t USBClock;		/*!< USB Frequency 								*/
+extern uint32_t USBClock;       /*!< USB Frequency                              */
 
 /* Public Functions ----------------------------------------------------------- */
 /** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions
diff --git a/bsp/lpc178x/drivers/lpc177x_8x_emc.c b/bsp/lpc178x/drivers/lpc177x_8x_emc.c
index c3009589a3..4047dbf623 100644
--- a/bsp/lpc178x/drivers/lpc177x_8x_emc.c
+++ b/bsp/lpc178x/drivers/lpc177x_8x_emc.c
@@ -1,13 +1,13 @@
 /**********************************************************************
-* $Id$		lpc177x_8x_emc.c			2011-06-02
+* $Id$      lpc177x_8x_emc.c            2011-06-02
 *//**
-* @file		lpc177x_8x_emc.c
-* @brief	Contains all functions support for EMC firmware library
-*			on LPC177x_8x
-* @version	1.0
-* @date		02. June. 2011
-* @author	NXP MCU SW Application Team
-* 
+* @file     lpc177x_8x_emc.c
+* @brief    Contains all functions support for EMC firmware library
+*           on LPC177x_8x
+* @version  1.0
+* @date     02. June. 2011
+* @author   NXP MCU SW Application Team
+*
 * Copyright(C) 2011, NXP Semiconductor
 * All rights reserved.
 *
@@ -30,23 +30,23 @@
 
 
 /*********************************************************************//**
- * @brief 		EMC initialize
- * @param[in]	None
- * @return 		None
+ * @brief       EMC initialize
+ * @param[in]   None
+ * @return      None
  **********************************************************************/
 void EMC_Init(void)
 {
-	uint8_t i;
+    uint8_t i;
 
-	/* Enable clock for EMC */
-//	CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCEMC, ENABLE);
-//	LPC_EMC->Control 	= 0x00000001;
-// 	LPC_EMC->Config  	= 0x00000000;
+    /* Enable clock for EMC */
+//  CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCEMC, ENABLE);
+//  LPC_EMC->Control    = 0x00000001;
+//  LPC_EMC->Config     = 0x00000000;
 
-	  LPC_SC->PCONP   	|= 0x00000800;
-	  LPC_SC->EMCDLYCTL   = 0x00001010;
-	  LPC_EMC->Control 	= 0x00000001;
-	  LPC_EMC->Config  	= 0x00000000;
+      LPC_SC->PCONP     |= 0x00000800;
+      LPC_SC->EMCDLYCTL   = 0x00001010;
+      LPC_EMC->Control  = 0x00000001;
+      LPC_EMC->Config   = 0x00000000;
 
   /* Pin configuration:
    * P2.14 - /EMC_CS2
@@ -81,40 +81,40 @@ void EMC_Init(void)
    * P4.30 - /EMC_CS0
    * P4.31 - /EMC_CS1
    */
-	PINSEL_ConfigPin(2,14,1);
-	PINSEL_ConfigPin(2,15,1);
-	PINSEL_ConfigPin(2,16,1);
-	PINSEL_ConfigPin(2,17,1);
-	PINSEL_ConfigPin(2,18,1);
-	PINSEL_ConfigPin(2,19,1);
-	PINSEL_ConfigPin(2,20,1);
-	PINSEL_ConfigPin(2,21,1);
-   	PINSEL_ConfigPin(2,22,1);
-	PINSEL_ConfigPin(2,23,1);
-	PINSEL_ConfigPin(2,24,1);
-	PINSEL_ConfigPin(2,25,1);
-	PINSEL_ConfigPin(2,26,1);
-	PINSEL_ConfigPin(2,27,1);
-	PINSEL_ConfigPin(2,28,1);
-	PINSEL_ConfigPin(2,29,1);
-	PINSEL_ConfigPin(2,30,1);
-	PINSEL_ConfigPin(2,31,1);
+    PINSEL_ConfigPin(2,14,1);
+    PINSEL_ConfigPin(2,15,1);
+    PINSEL_ConfigPin(2,16,1);
+    PINSEL_ConfigPin(2,17,1);
+    PINSEL_ConfigPin(2,18,1);
+    PINSEL_ConfigPin(2,19,1);
+    PINSEL_ConfigPin(2,20,1);
+    PINSEL_ConfigPin(2,21,1);
+    PINSEL_ConfigPin(2,22,1);
+    PINSEL_ConfigPin(2,23,1);
+    PINSEL_ConfigPin(2,24,1);
+    PINSEL_ConfigPin(2,25,1);
+    PINSEL_ConfigPin(2,26,1);
+    PINSEL_ConfigPin(2,27,1);
+    PINSEL_ConfigPin(2,28,1);
+    PINSEL_ConfigPin(2,29,1);
+    PINSEL_ConfigPin(2,30,1);
+    PINSEL_ConfigPin(2,31,1);
 
-	PINSEL_ConfigPin(5,0,1);
-	PINSEL_ConfigPin(5,1,1);
+    PINSEL_ConfigPin(5,0,1);
+    PINSEL_ConfigPin(5,1,1);
 
-	for(i = 0; i < 32; i++)
-	{
-		PINSEL_ConfigPin(3,i,1);
-		PINSEL_ConfigPin(4,i,1);
-	}
+    for(i = 0; i < 32; i++)
+    {
+        PINSEL_ConfigPin(3,i,1);
+        PINSEL_ConfigPin(4,i,1);
+    }
 }
 /*********************************************************************//**
- * @brief 		Configure Little Endian/Big Endian mode for EMC
- * @param[in]	endia_mode	Endian mode, should be:
- * 				- EMC_LITTLE_ENDIAN_MODE:	Little-endian mode
- * 				- EMC_BIG_ENDIAN_MODE	:	Big-endian mode
- * @return 		None
+ * @brief       Configure Little Endian/Big Endian mode for EMC
+ * @param[in]   endia_mode  Endian mode, should be:
+ *              - EMC_LITTLE_ENDIAN_MODE:   Little-endian mode
+ *              - EMC_BIG_ENDIAN_MODE   :   Big-endian mode
+ * @return      None
  **********************************************************************/
 void EMC_ConfigEndianMode(uint32_t endian_mode)
 {
@@ -123,12 +123,12 @@ void EMC_ConfigEndianMode(uint32_t endian_mode)
 
 /****************** Group of Dynamic control functions************************/
 /*********************************************************************//**
- * @brief 		Set the value for dynamic clock enable bit
- * @param[in]	clock_enable	clock enable mode, should be:
- * 					- 0: Clock enable of idle devices are deasserted to
- * 						save power
- * 					- 1: All clock enables are driven HIGH continuously
- * @return 		None
+ * @brief       Set the value for dynamic clock enable bit
+ * @param[in]   clock_enable    clock enable mode, should be:
+ *                  - 0: Clock enable of idle devices are deasserted to
+ *                      save power
+ *                  - 1: All clock enables are driven HIGH continuously
+ * @return      None
  **********************************************************************/
 void EMC_DynCtrlClockEnable(uint32_t clock_enable)
 {
@@ -136,13 +136,13 @@ void EMC_DynCtrlClockEnable(uint32_t clock_enable)
 }
 
 /*********************************************************************//**
- * @brief 		Set the value for dynamic memory clock control:
- * 				stops or runs continuously
- * @param[in]	clock_control	clock control mode, should be:
- * 					- 0: CLKOUT stops when all SDRAMs are idle and
- * 						during self-refresh mode
- * 					- 1: CLKOUT runs continuously
- * @return 		None
+ * @brief       Set the value for dynamic memory clock control:
+ *              stops or runs continuously
+ * @param[in]   clock_control   clock control mode, should be:
+ *                  - 0: CLKOUT stops when all SDRAMs are idle and
+ *                      during self-refresh mode
+ *                  - 1: CLKOUT runs continuously
+ * @return      None
  **********************************************************************/
 void EMC_DynCtrlClockControl(int32_t clock_control)
 {
@@ -151,11 +151,11 @@ void EMC_DynCtrlClockControl(int32_t clock_control)
 }
 
 /*********************************************************************//**
- * @brief 		Switch the Self-refresh mode between normal and self-refresh mode
- * @param[in]	self_refresh_mode	self refresh mode, should be:
- * 					- 0: Normal mode
- * 					- 1: Enter self-refresh mode
- * @return 		None
+ * @brief       Switch the Self-refresh mode between normal and self-refresh mode
+ * @param[in]   self_refresh_mode   self refresh mode, should be:
+ *                  - 0: Normal mode
+ *                  - 1: Enter self-refresh mode
+ * @return      None
  **********************************************************************/
 void EMC_DynCtrlSelfRefresh(uint32_t self_refresh_mode)
 {
@@ -164,11 +164,11 @@ void EMC_DynCtrlSelfRefresh(uint32_t self_refresh_mode)
 }
 
 /*********************************************************************//**
- * @brief 		Enable/disable CLKOUT
- * @param[in]	MMC_val	Memory clock control mode, should be:
- * 					- 0: CLKOUT enabled
- * 					- 1: CLKOUT disabled
- * @return 		None
+ * @brief       Enable/disable CLKOUT
+ * @param[in]   MMC_val Memory clock control mode, should be:
+ *                  - 0: CLKOUT enabled
+ *                  - 1: CLKOUT disabled
+ * @return      None
  **********************************************************************/
 void EMC_DynCtrlMMC(uint32_t MMC_val)
 {
@@ -177,13 +177,13 @@ void EMC_DynCtrlMMC(uint32_t MMC_val)
 }
 
 /*********************************************************************//**
- * @brief 		Issue SDRAM command
- * @param[in]	SDRAM_command	Command mode, should be:
- * 					- 0x00: Issue SDRAM NORMAL operation command
- * 					- 0x01: Issue SDRAM MODE command
- * 					- 0x02: Issue SDRAM PALL (precharge all) command
- * 					- 0x03: Issue SRAM NOP (no operation) command
- * @return 		None
+ * @brief       Issue SDRAM command
+ * @param[in]   SDRAM_command   Command mode, should be:
+ *                  - 0x00: Issue SDRAM NORMAL operation command
+ *                  - 0x01: Issue SDRAM MODE command
+ *                  - 0x02: Issue SDRAM PALL (precharge all) command
+ *                  - 0x03: Issue SRAM NOP (no operation) command
+ * @return      None
  **********************************************************************/
 void EMC_DynCtrlSDRAMInit(uint32_t SDRAM_command)
 {
@@ -192,11 +192,11 @@ void EMC_DynCtrlSDRAMInit(uint32_t SDRAM_command)
 }
 
 /*********************************************************************//**
- * @brief 		Switch between Normal operation and deep sleep power mode
- * @param[in]	Power_command	Low-power SDRAM deep-sleep mode, should be:
- *					- 0: Normal operation
- *					- 1: Enter deep-sleep mode
- * @return 		None
+ * @brief       Switch between Normal operation and deep sleep power mode
+ * @param[in]   Power_command   Low-power SDRAM deep-sleep mode, should be:
+ *                  - 0: Normal operation
+ *                  - 1: Enter deep-sleep mode
+ * @return      None
  **********************************************************************/
 void EMC_DynCtrlPowerDownMode(uint32_t Power_command)
 {
@@ -205,22 +205,22 @@ void EMC_DynCtrlPowerDownMode(uint32_t Power_command)
 }
 
 /*********************************************************************//**
- * @brief 		Set the value of EMC dynamic memory registers
- * @param[in]	par	EMC register that will set value, should be:
- *					- EMC_DYN_MEM_REFRESH_TIMER: Dynamic Refresh register
- *					- EMC_DYN_MEM_READ_CONFIG: Dynamic Read Config register
- *					- EMC_DYN_MEM_TRP: Dynamic RP register
- *					- EMC_DYN_MEM_TRAS: Dynamic RAS register
- *					- EMC_DYN_MEM_TSREX: Dynamic SREX register
- *					- EMC_DYN_MEM_TAPR: Dynamic APR register
- *					- EMC_DYN_MEM_TDAL: Dynamic DAL register
- *					- EMC_DYN_MEM_TWR: Dynamic WR register
- *					- EMC_DYN_MEM_TRC: Dynamic RC register
- *					- EMC_DYN_MEM_TRFC: Dynamic RFC register
- *					- EMC_DYN_MEM_TXSR: Dynamic XSR register
- *					- EMC_DYN_MEM_TRRD: Dynamic RRD register
- *					- EMC_DYN_MEM_TMRD: Dynamic MRD register
- * @return 		None
+ * @brief       Set the value of EMC dynamic memory registers
+ * @param[in]   par EMC register that will set value, should be:
+ *                  - EMC_DYN_MEM_REFRESH_TIMER: Dynamic Refresh register
+ *                  - EMC_DYN_MEM_READ_CONFIG: Dynamic Read Config register
+ *                  - EMC_DYN_MEM_TRP: Dynamic RP register
+ *                  - EMC_DYN_MEM_TRAS: Dynamic RAS register
+ *                  - EMC_DYN_MEM_TSREX: Dynamic SREX register
+ *                  - EMC_DYN_MEM_TAPR: Dynamic APR register
+ *                  - EMC_DYN_MEM_TDAL: Dynamic DAL register
+ *                  - EMC_DYN_MEM_TWR: Dynamic WR register
+ *                  - EMC_DYN_MEM_TRC: Dynamic RC register
+ *                  - EMC_DYN_MEM_TRFC: Dynamic RFC register
+ *                  - EMC_DYN_MEM_TXSR: Dynamic XSR register
+ *                  - EMC_DYN_MEM_TRRD: Dynamic RRD register
+ *                  - EMC_DYN_MEM_TMRD: Dynamic MRD register
+ * @return      None
  **********************************************************************/
 void EMC_SetDynMemoryParameter(EMC_DYN_MEM_PAR par, uint32_t val)
 {
@@ -269,9 +269,9 @@ void EMC_SetDynMemoryParameter(EMC_DYN_MEM_PAR par, uint32_t val)
 }
 
 /*********************************************************************//**
- * @brief 		Set extended wait time out for accessing static memory
- * @param[in]	Extended_wait_time_out timeout value that will be set
- * @return 		None
+ * @brief       Set extended wait time out for accessing static memory
+ * @param[in]   Extended_wait_time_out timeout value that will be set
+ * @return      None
  **********************************************************************/
 void EMC_StaticExtendedWait(uint32_t Extended_wait_time_out)
 {
@@ -279,13 +279,13 @@ void EMC_StaticExtendedWait(uint32_t Extended_wait_time_out)
 }
 
 /*********************************************************************//**
- * @brief 		Configure the memory device
- * @param[in]	index index number, should be from 0 to 3
- * @param[in]	mem_dev Memory device, should be:
- *					- 0x00: SDRAM
- *					- 0x01: Low-power SDRAM
- *					- 0x02: Micron Syncflash
- * @return 		None
+ * @brief       Configure the memory device
+ * @param[in]   index index number, should be from 0 to 3
+ * @param[in]   mem_dev Memory device, should be:
+ *                  - 0x00: SDRAM
+ *                  - 0x01: Low-power SDRAM
+ *                  - 0x02: Micron Syncflash
+ * @return      None
  **********************************************************************/
 void EMC_DynMemConfigMD(uint32_t index , uint32_t mem_dev)
 {
@@ -294,24 +294,24 @@ void EMC_DynMemConfigMD(uint32_t index , uint32_t mem_dev)
    {
       case 0:
          LPC_EMC->DynamicConfig0 = (LPC_EMC->DynamicConfig0 & mask) | mem_dev;
-	   break;
+       break;
       case 1:
          LPC_EMC->DynamicConfig1 = (LPC_EMC->DynamicConfig1 & mask) | mem_dev;
-	   break;
+       break;
       case 2:
          LPC_EMC->DynamicConfig2 =(LPC_EMC->DynamicConfig2 & mask) | mem_dev;
-	   break;
+       break;
       case 3:
          LPC_EMC->DynamicConfig3 = (LPC_EMC->DynamicConfig3 & mask) | mem_dev;
-	   break;
+       break;
    }
 }
 
 /*********************************************************************//**
- * @brief 		Map the address for the memory device
- * @param[in]	index index number, should be from 0 to 3
- * @param[in] 	add_mapped address where the memory will be mapped
- * @return 		None
+ * @brief       Map the address for the memory device
+ * @param[in]   index index number, should be from 0 to 3
+ * @param[in]   add_mapped address where the memory will be mapped
+ * @return      None
  **********************************************************************/
 void EMC_DynMemConfigAM(uint32_t index , uint32_t add_mapped)
 {
@@ -321,26 +321,26 @@ void EMC_DynMemConfigAM(uint32_t index , uint32_t add_mapped)
    {
       case 0:
          LPC_EMC->DynamicConfig0 = ( LPC_EMC->DynamicConfig0 & mask) | add_mapped;
-	   break;
+       break;
       case 1:
          LPC_EMC->DynamicConfig1 = (LPC_EMC->DynamicConfig1 & mask) | add_mapped;
-	   break;
+       break;
       case 2:
          LPC_EMC->DynamicConfig2 = (LPC_EMC->DynamicConfig2 & mask) | add_mapped;
-	   break;
+       break;
       case 3:
          LPC_EMC->DynamicConfig3 = (LPC_EMC->DynamicConfig3 & mask) | add_mapped;
-	   break;
+       break;
    }
 }
 
 /*********************************************************************//**
- * @brief 		Enable/disable the buffer
- * @param[in]	index index number, should be from 0 to 3
- * @param[in] 	buff_control buffer control mode, should be:
- * 					- ENABLE
- * 					- DISABLE
- * @return 		None
+ * @brief       Enable/disable the buffer
+ * @param[in]   index index number, should be from 0 to 3
+ * @param[in]   buff_control buffer control mode, should be:
+ *                  - ENABLE
+ *                  - DISABLE
+ * @return      None
  **********************************************************************/
 void EMC_DynMemConfigB(uint32_t index , uint32_t buff_control)
 {
@@ -349,27 +349,27 @@ void EMC_DynMemConfigB(uint32_t index , uint32_t buff_control)
    {
       case 0:
          LPC_EMC->DynamicConfig0 = (LPC_EMC->DynamicConfig0 & mask) | buff_control;
-	   break;
+       break;
       case 1:
          LPC_EMC->DynamicConfig1 = ( LPC_EMC->DynamicConfig1 & mask) | buff_control;
-	   break;
+       break;
       case 2:
          LPC_EMC->DynamicConfig2 = (LPC_EMC->DynamicConfig2 & mask)| buff_control;
-	   break;
+       break;
       case 3:
          LPC_EMC->DynamicConfig3 = (LPC_EMC->DynamicConfig3 & mask) | buff_control;
-	   break;
+       break;
    }
 }
 
 
 /*********************************************************************//**
- * @brief 		Configure write permission: protect or not
- * @param[in]	index index number, should be from 0 to 3
- * @param[in] 	permission  permission mode, should be:
- * 					- ENABLE: protect
- * 					- DISABLE: not protect
- * @return 		None
+ * @brief       Configure write permission: protect or not
+ * @param[in]   index index number, should be from 0 to 3
+ * @param[in]   permission  permission mode, should be:
+ *                  - ENABLE: protect
+ *                  - DISABLE: not protect
+ * @return      None
  **********************************************************************/
 void EMC_DynMemConfigP(uint32_t index , uint32_t permission)
 {
@@ -378,24 +378,24 @@ void EMC_DynMemConfigP(uint32_t index , uint32_t permission)
    {
       case 0:
          LPC_EMC->DynamicConfig0 = (LPC_EMC->DynamicConfig0 & mask) | permission;
-	   break;
+       break;
       case 1:
          LPC_EMC->DynamicConfig1 = (LPC_EMC->DynamicConfig1 & mask) | permission;
-	   break;
+       break;
       case 2:
          LPC_EMC->DynamicConfig2 = ( LPC_EMC->DynamicConfig2 & mask) | permission;
-	   break;
+       break;
       case 3:
          LPC_EMC->DynamicConfig3 = (LPC_EMC->DynamicConfig3 & mask) | permission;
-	   break;
+       break;
    }
 }
 
 /*********************************************************************//**
- * @brief 		Set value for RAS latency
- * @param[in]	index index number, should be from 0 to 3
- * @param[in] 	ras_val  RAS value should be in range: 0..3
- * @return 		None
+ * @brief       Set value for RAS latency
+ * @param[in]   index index number, should be from 0 to 3
+ * @param[in]   ras_val  RAS value should be in range: 0..3
+ * @return      None
  **********************************************************************/
 void EMC_DynMemRAS(uint32_t index , uint32_t ras_val)
 {
@@ -405,24 +405,24 @@ void EMC_DynMemRAS(uint32_t index , uint32_t ras_val)
    {
       case 0:
          LPC_EMC->DynamicRasCas0 = (LPC_EMC->DynamicRasCas0 & mask) | ras_val;
-	   break;
+       break;
       case 1:
          LPC_EMC->DynamicRasCas1 = (LPC_EMC->DynamicRasCas1 & mask) | ras_val;
-	   break;
+       break;
       case 2:
          LPC_EMC->DynamicRasCas2 = (LPC_EMC->DynamicRasCas2 & mask) | ras_val;
-	   break;
+       break;
       case 3:
          LPC_EMC->DynamicRasCas3 = (LPC_EMC->DynamicRasCas3 & mask) | ras_val;
-	   break;
+       break;
    }
 }
 
 /*********************************************************************//**
- * @brief 		Set value for CAS latency
- * @param[in]	index index number, should be from 0 to 3
- * @param[in] 	ras_val  CAS value should be in range: 0..3
- * @return 		None
+ * @brief       Set value for CAS latency
+ * @param[in]   index index number, should be from 0 to 3
+ * @param[in]   ras_val  CAS value should be in range: 0..3
+ * @return      None
  **********************************************************************/
 void EMC_DynMemCAS(uint32_t index , uint32_t cas_val)
 {
@@ -431,26 +431,26 @@ void EMC_DynMemCAS(uint32_t index , uint32_t cas_val)
    {
       case 0:
          LPC_EMC->DynamicRasCas0 = (LPC_EMC->DynamicRasCas0 & mask) | cas_val;
-	   break;
+       break;
       case 1:
          LPC_EMC->DynamicRasCas1 = (LPC_EMC->DynamicRasCas1 & mask) | cas_val;
-	   break;
+       break;
       case 2:
          LPC_EMC->DynamicRasCas2 = (LPC_EMC->DynamicRasCas2 & mask )| cas_val;
-	   break;
+       break;
       case 3:
          LPC_EMC->DynamicRasCas3 = ( LPC_EMC->DynamicRasCas3 & mask) | cas_val;
-	   break;
+       break;
    }
 }
 /*********************************************************************//**
- * @brief 		Configure the memory width
- * @param[in]	index index number, should be from 0 to 3
- * @param[in] 	mem_width  memory width, should be:
- * 					- 0x00: 8-bits
- * 					- 0x01: 16-bits
- * 					- 0x02: 32-bits
- * @return 		None
+ * @brief       Configure the memory width
+ * @param[in]   index index number, should be from 0 to 3
+ * @param[in]   mem_width  memory width, should be:
+ *                  - 0x00: 8-bits
+ *                  - 0x01: 16-bits
+ *                  - 0x02: 32-bits
+ * @return      None
  **********************************************************************/
 void EMC_StaMemConfigMW(uint32_t index , uint32_t mem_width)
 {
@@ -459,25 +459,25 @@ void EMC_StaMemConfigMW(uint32_t index , uint32_t mem_width)
    {
       case 0:
          LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | mem_width;
-	   break;
+       break;
       case 1:
          LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask) | mem_width;
-	   break;
+       break;
       case 2:
          LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask)| mem_width;
-	   break;
+       break;
       case 3:
          LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask) | mem_width;
-	   break;
+       break;
    }
 }
 /*********************************************************************//**
- * @brief 		Configure the page mode
- * @param[in]	index index number, should be from 0 to 3
- * @param[in] 	page_mode  page mode, should be:
- * 					- 0: disable
- * 					- 1: asynchronous page mode enable
- * @return 		None
+ * @brief       Configure the page mode
+ * @param[in]   index index number, should be from 0 to 3
+ * @param[in]   page_mode  page mode, should be:
+ *                  - 0: disable
+ *                  - 1: asynchronous page mode enable
+ * @return      None
  **********************************************************************/
 void EMC_StaMemConfigPM(uint32_t index , uint32_t page_mode)
 {
@@ -486,25 +486,25 @@ void EMC_StaMemConfigPM(uint32_t index , uint32_t page_mode)
    {
       case 0:
          LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | page_mode;
-	   break;
+       break;
       case 1:
          LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask) | page_mode;
-	   break;
+       break;
       case 2:
          LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2  & mask)| page_mode;
-	   break;
+       break;
       case 3:
          LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3  & mask)| page_mode;
-	   break;
+       break;
    }
 }
 /*********************************************************************//**
- * @brief 		Configure the chip select polarity
- * @param[in]	index index number, should be from 0 to 3
- * @param[in] 	pagepol_val_mode  page mode, should be:
- * 					- 0: Active LOW ship select
- * 					- 1: Active HIGH chip select
- * @return 		None
+ * @brief       Configure the chip select polarity
+ * @param[in]   index index number, should be from 0 to 3
+ * @param[in]   pagepol_val_mode  page mode, should be:
+ *                  - 0: Active LOW ship select
+ *                  - 1: Active HIGH chip select
+ * @return      None
  **********************************************************************/
 void EMC_StaMemConfigPC(uint32_t index , uint32_t pol_val)
 {
@@ -513,26 +513,26 @@ void EMC_StaMemConfigPC(uint32_t index , uint32_t pol_val)
    {
       case 0:
          LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | pol_val;
-	   break;
+       break;
       case 1:
          LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1  & mask)| pol_val;
-	   break;
+       break;
       case 2:
          LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask) | pol_val;
-	   break;
+       break;
       case 3:
          LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask) | pol_val;
-	   break;
+       break;
    }
 }
 
 /*********************************************************************//**
- * @brief 		Configure the byte lane state
- * @param[in]	index index number, should be from 0 to 3
- * @param[in] 	pb_val  Byte lane state, should be:
- * 					- 0: For reads all bits in BLSn[3:0] are HIGH.
- * 					- 1: For reads all bits in BLSn[3:0] are LOW.
- * @return 		None
+ * @brief       Configure the byte lane state
+ * @param[in]   index index number, should be from 0 to 3
+ * @param[in]   pb_val  Byte lane state, should be:
+ *                  - 0: For reads all bits in BLSn[3:0] are HIGH.
+ *                  - 1: For reads all bits in BLSn[3:0] are LOW.
+ * @return      None
  **********************************************************************/
 void EMC_StaMemConfigPB(uint32_t index , uint32_t pb_val)
 {
@@ -541,26 +541,26 @@ void EMC_StaMemConfigPB(uint32_t index , uint32_t pb_val)
    {
       case 0:
          LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0  & mask)| pb_val;
-	   break;
+       break;
       case 1:
          LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1  & mask)| pb_val;
-	   break;
+       break;
       case 2:
          LPC_EMC->StaticConfig2 =( LPC_EMC->StaticConfig2  & mask)| pb_val;
-	   break;
+       break;
       case 3:
          LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3  & mask)| pb_val;
-	   break;
+       break;
    }
 }
 
 /*********************************************************************//**
- * @brief 		Configure the extended wait value
- * @param[in]	index index number, should be from 0 to 3
- * @param[in] 	ex_wait  Extended wait mode, should be:
- * 					- 0: Extended wait disabled.
- * 					- 1: Extended wait enabled.
- * @return 		None
+ * @brief       Configure the extended wait value
+ * @param[in]   index index number, should be from 0 to 3
+ * @param[in]   ex_wait  Extended wait mode, should be:
+ *                  - 0: Extended wait disabled.
+ *                  - 1: Extended wait enabled.
+ * @return      None
  **********************************************************************/
 void EMC_StaMemConfigEW(uint32_t index , uint32_t ex_wait)
 {
@@ -569,26 +569,26 @@ void EMC_StaMemConfigEW(uint32_t index , uint32_t ex_wait)
    {
       case 0:
          LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | ex_wait;
-	   break;
+       break;
       case 1:
          LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask) | ex_wait;
-	   break;
+       break;
       case 2:
          LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask) | ex_wait;
-	   break;
+       break;
       case 3:
          LPC_EMC->StaticConfig3 =( LPC_EMC->StaticConfig3 & mask) | ex_wait;
-	   break;
+       break;
    }
 }
 
 /*********************************************************************//**
- * @brief 		Configure the buffer enable value
- * @param[in]	index index number, should be from 0 to 3
- * @param[in] 	buf_val  Buffer mode, should be:
- * 					- 0: Buffer disabled.
- * 					- 1: Buffer enabled.
- * @return 		None
+ * @brief       Configure the buffer enable value
+ * @param[in]   index index number, should be from 0 to 3
+ * @param[in]   buf_val  Buffer mode, should be:
+ *                  - 0: Buffer disabled.
+ *                  - 1: Buffer enabled.
+ * @return      None
  **********************************************************************/
 void EMC_StaMemConfigB(uint32_t index , uint32_t buf_val)
 {
@@ -597,26 +597,26 @@ void EMC_StaMemConfigB(uint32_t index , uint32_t buf_val)
    {
       case 0:
          LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask) | buf_val;
-	   break;
+       break;
       case 1:
          LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask) | buf_val;
-	   break;
+       break;
       case 2:
          LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask) | buf_val;
-	   break;
+       break;
       case 3:
          LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask) | buf_val;
-	   break;
+       break;
    }
 }
 
 /*********************************************************************//**
- * @brief 		Configure the write permission
- * @param[in]	index index number, should be from 0 to 3
- * @param[in] 	per_val  Permission mode, should be:
- * 					- 0: Write not protected.
- * 					- 1: Write protected.
- * @return 		None
+ * @brief       Configure the write permission
+ * @param[in]   index index number, should be from 0 to 3
+ * @param[in]   per_val  Permission mode, should be:
+ *                  - 0: Write not protected.
+ *                  - 1: Write protected.
+ * @return      None
  **********************************************************************/
 void EMC_StaMemConfigpP(uint32_t index , uint32_t per_val)
 {
@@ -625,36 +625,36 @@ void EMC_StaMemConfigpP(uint32_t index , uint32_t per_val)
    {
       case 0:
          LPC_EMC->StaticConfig0 = (LPC_EMC->StaticConfig0 & mask)  | per_val;
-	   break;
+       break;
       case 1:
          LPC_EMC->StaticConfig1 = (LPC_EMC->StaticConfig1 & mask)  | per_val;
-	   break;
+       break;
       case 2:
          LPC_EMC->StaticConfig2 = (LPC_EMC->StaticConfig2 & mask)  | per_val;
-	   break;
+       break;
       case 3:
          LPC_EMC->StaticConfig3 = (LPC_EMC->StaticConfig3 & mask)  | per_val;
-	   break;
+       break;
    }
 }
 
 /*********************************************************************//**
- * @brief 		Set the value of LPC_EMC static memory registers
- * @param[in]	index index number, should be from 0 to 3
- * @param[in] 	EMC_STA_MEM_PAR  Static register, should be:
- * 					- EMC_STA_MEM_WAITWEN: StaticWaitWen0 register
- * 					- EMC_STA_MEM_WAITOEN: StaticWaitOen0 register
- * 					- EMC_STA_MEM_WAITRD: StaticWaitRd0 register
- * 					- EMC_STA_MEM_WAITPAGE: StaticWaitPage0 register
- * 					- EMC_STA_MEM_WAITWR: StaticWaitWr0 register
- * 					- EMC_STA_MEM_WAITTURN: StaticWaitTurn0 register
- * @return 		None
+ * @brief       Set the value of LPC_EMC static memory registers
+ * @param[in]   index index number, should be from 0 to 3
+ * @param[in]   EMC_STA_MEM_PAR  Static register, should be:
+ *                  - EMC_STA_MEM_WAITWEN: StaticWaitWen0 register
+ *                  - EMC_STA_MEM_WAITOEN: StaticWaitOen0 register
+ *                  - EMC_STA_MEM_WAITRD: StaticWaitRd0 register
+ *                  - EMC_STA_MEM_WAITPAGE: StaticWaitPage0 register
+ *                  - EMC_STA_MEM_WAITWR: StaticWaitWr0 register
+ *                  - EMC_STA_MEM_WAITTURN: StaticWaitTurn0 register
+ * @return      None
  **********************************************************************/
 void EMC_SetStaMemoryParameter(uint32_t index ,EMC_STA_MEM_PAR par, uint32_t val)
 {
    switch (index)
    {
-   	case 0:
+    case 0:
          switch ( par)
          {
             case EMC_STA_MEM_WAITWEN:
@@ -676,8 +676,8 @@ void EMC_SetStaMemoryParameter(uint32_t index ,EMC_STA_MEM_PAR par, uint32_t val
                LPC_EMC->StaticWaitTurn0 = val;
                break;
          }
-	   break;
-   	case 1:
+       break;
+    case 1:
          switch ( par)
          {
             case EMC_STA_MEM_WAITWEN:
@@ -699,8 +699,8 @@ void EMC_SetStaMemoryParameter(uint32_t index ,EMC_STA_MEM_PAR par, uint32_t val
                LPC_EMC->StaticWaitTurn1 = val;
                break;
          }
-	   break;
-   	case 2:
+       break;
+    case 2:
          switch ( par)
          {
             case EMC_STA_MEM_WAITWEN:
@@ -722,8 +722,8 @@ void EMC_SetStaMemoryParameter(uint32_t index ,EMC_STA_MEM_PAR par, uint32_t val
                LPC_EMC->StaticWaitTurn2 = val;
                break;
          }
-	   break;
-   	case 3:
+       break;
+    case 3:
          switch ( par)
          {
             case EMC_STA_MEM_WAITWEN:
@@ -745,7 +745,7 @@ void EMC_SetStaMemoryParameter(uint32_t index ,EMC_STA_MEM_PAR par, uint32_t val
                LPC_EMC->StaticWaitTurn3 = val;
                break;
          }
-	   break;
+       break;
    }
 }
 
diff --git a/bsp/lpc178x/drivers/lpc177x_8x_emc.h b/bsp/lpc178x/drivers/lpc177x_8x_emc.h
index 41d9cbfcc1..497521edb8 100644
--- a/bsp/lpc178x/drivers/lpc177x_8x_emc.h
+++ b/bsp/lpc178x/drivers/lpc177x_8x_emc.h
@@ -1,13 +1,13 @@
 /**********************************************************************
-* $Id$		lpc177x_8x_emc.h			2011-06-02
+* $Id$      lpc177x_8x_emc.h            2011-06-02
 *//**
-* @file		lpc177x_8x_emc.h
-* @brief	Contains all macro definitions and function prototypes
-*			support for EMC firmware library on LPC177x_8x
-* @version	1.0
-* @date		02. June. 2011
-* @author	NXP MCU SW Application Team
-* 
+* @file     lpc177x_8x_emc.h
+* @brief    Contains all macro definitions and function prototypes
+*           support for EMC firmware library on LPC177x_8x
+* @version  1.0
+* @date     02. June. 2011
+* @author   NXP MCU SW Application Team
+*
 * Copyright(C) 2011, NXP Semiconductor
 * All rights reserved.
 *
@@ -25,7 +25,7 @@
 **********************************************************************/
 
 /* Peripheral group ----------------------------------------------------------- */
-/** @defgroup EMC	EMC (External Memory Controller)
+/** @defgroup EMC   EMC (External Memory Controller)
  * @ingroup LPC177x_8xCMSIS_FwLib_Drivers
  * @{
  */
@@ -45,233 +45,233 @@
  * EMC Control Register (EMCControl)
  **********************************************************************/
 /* Control register mask */
-#define EMC_Control_MASK			((uint32_t )0x07)
+#define EMC_Control_MASK            ((uint32_t )0x07)
 /* Control register EMC: Enable control. */
-#define EMC_Control_E				((uint32_t )(1<<0))
+#define EMC_Control_E               ((uint32_t )(1<<0))
 /* Control register EMC: Address mirror control. */
-#define EMC_Control_M				((uint32_t )(1<<1))
+#define EMC_Control_M               ((uint32_t )(1<<1))
 /* Control register EMC: Low-power mode control. */
-#define EMC_Control_L				((uint32_t )(1<<2))
+#define EMC_Control_L               ((uint32_t )(1<<2))
 
 /***********************************************************************
  * EMC Status Register (EMCStatus)
  **********************************************************************/
 /* Status register mask */
-#define EMC_Status_MASK				((uint32_t )0x07)
+#define EMC_Status_MASK             ((uint32_t )0x07)
 /* Status register EMC: Busy. */
-#define EMC_Status_B				((uint32_t )(1<<0))
+#define EMC_Status_B                ((uint32_t )(1<<0))
 /* Status register EMC: Write buffer status. */
-#define EMC_Status_S				((uint32_t )(1<<1))
+#define EMC_Status_S                ((uint32_t )(1<<1))
 /* Status register EMC: Self-refresh acknowledge.. */
-#define EMC_Status_SA				((uint32_t )(1<<2))
+#define EMC_Status_SA               ((uint32_t )(1<<2))
 
 /***********************************************************************
  * EMC Configuration register (EMCConfig)
  **********************************************************************/
 /* EMC Configuration register : Enable control. */
-#define EMC_Config_Endian_Mode		((uint32_t )(1<<0))
+#define EMC_Config_Endian_Mode      ((uint32_t )(1<<0))
 /* EMC Configuration register: CCLK. */
-#define EMC_Config_CCLK				((uinr32_t)(1<<8))
+#define EMC_Config_CCLK             ((uinr32_t)(1<<8))
 /* EMC Configuration register mask */
-#define EMC_Config_MASK				((uint32_t)(0x101))
+#define EMC_Config_MASK             ((uint32_t)(0x101))
 
 
 /***********************************************************************
  * Dynamic Memory Control register (EMCDynamicControl)
  **********************************************************************/
 /* Dynamic Memory Control register EMC: Dynamic memory clock enable. */
-#define EMC_DynamicControl_CE			((uint32_t )(1<<0))
+#define EMC_DynamicControl_CE           ((uint32_t )(1<<0))
 /* Dynamic Memory Control register EMC: Dynamic memory clock control */
-#define EMC_DynamicControl_CS			((uint32_t )(1<<1))
+#define EMC_DynamicControl_CS           ((uint32_t )(1<<1))
 /* Dynamic Memory Control register EMC: Self-refresh request, EMCSREFREQ*/
-#define EMC_DynamicControl_SR			((uint32_t )(1<<2))
+#define EMC_DynamicControl_SR           ((uint32_t )(1<<2))
 /* Dynamic Memory Control register EMC: Memory clock control (MMC)*/
-#define EMC_DynamicControl_MMC			((uint32_t )(1<<5))
+#define EMC_DynamicControl_MMC          ((uint32_t )(1<<5))
 /* Dynamic Memory Control register EMC: SDRAM initialization*/
-#define EMC_DynamicControl_I(n)			((uint32_t )(n<<7))
+#define EMC_DynamicControl_I(n)         ((uint32_t )(n<<7))
 /* Dynamic Memory Control register EMC: Low-power SDRAM deep-sleep mode (DP)*/
-#define EMC_DynamicControl_DP			((uint32_t ) (1<<13))
+#define EMC_DynamicControl_DP           ((uint32_t ) (1<<13))
 
 /***********************************************************************
  * Dynamic Memory Refresh Timer register (EMCDynamicRefresh)
  **********************************************************************/
 /* Dynamic Memory Refresh Timer register EMC: Refresh timer (REFRESH) */
-#define EMC_DynamicRefresh_REFRESH(n)	((uint32_t ) (n & 0x3ff))
+#define EMC_DynamicRefresh_REFRESH(n)   ((uint32_t ) (n & 0x3ff))
 
 /***********************************************************************
  * Dynamic Memory Read Configuration register (EMCDynamicReadConfig)
  **********************************************************************/
 /* EMCDynamicReadConfig register EMC:Read data strategy (RD) */
-#define EMC_DynamicReadConfig_RD(n)		((uint32_t )(n & 0x03))
+#define EMC_DynamicReadConfig_RD(n)     ((uint32_t )(n & 0x03))
 
 /***********************************************************************
  * Dynamic Memory Percentage Command Period register (EMCDynamictRP)
  **********************************************************************/
 /* EMCDynamictRP register EMC: Precharge command period (tRP). */
-#define EMC_DynamictRP_tRP(n)			((uint32_t )(n & 0x0f))
+#define EMC_DynamictRP_tRP(n)           ((uint32_t )(n & 0x0f))
 
 /***********************************************************************
  * Dynamic Memory Active to Precharge Command Period register (EMCDynamictRAS)
  **********************************************************************/
 /* EMCDynamictRAS register EMC: Active to precharge command period (tRAS) */
-#define EMC_DynamictRP_tRAS(n)			((uint32_t )(n & 0x0f))
+#define EMC_DynamictRP_tRAS(n)          ((uint32_t )(n & 0x0f))
 
 /***********************************************************************
  * Dynamic Memory Last Data Out to Active Time register (EMCDynamictAPR)
  **********************************************************************/
 /* EMCDynamictAPR register EMC: Last-data-out to active command time (tAPR) */
-#define EMC_DynamictAPR_tAPR(n)			((uint32_t )(n & 0x0f))
+#define EMC_DynamictAPR_tAPR(n)         ((uint32_t )(n & 0x0f))
 
 /***********************************************************************
  * Dynamic Memory Data-in to Active Command Time register (EMCDynamictDAL)
  **********************************************************************/
 /* EMCDynamictDAL register EMC: Data-in to active command (tDAL)*/
-#define EMC_DynamictDAL_tDAL(n)			((uint32_t )(n & 0x0f))
+#define EMC_DynamictDAL_tDAL(n)         ((uint32_t )(n & 0x0f))
 
 /***********************************************************************
  * Dynamic Memory Write Recovery Time register (EMCDynamictWR)
  **********************************************************************/
 /* EMCDynamictWR register EMC: Write recovery time (tWR)*/
-#define EMC_DynamictWR_tWR(n)			(uint32_t )(n & 0x0f)
+#define EMC_DynamictWR_tWR(n)           (uint32_t )(n & 0x0f)
 
 /***********************************************************************
  * Dynamic Memory Active to Active Command Period register (EMCDynamictRC)
  **********************************************************************/
 /* EMCDynamictRC register EMC: Active to active command period (tRC)*/
-#define EMC_DynamictRC_tRC(n)			(uint32_t )(n & 0x1f)
+#define EMC_DynamictRC_tRC(n)           (uint32_t )(n & 0x1f)
 
 /***********************************************************************
  * Dynamic Memory Auto-refresh Period register (EMCDynamictRFC)
  **********************************************************************/
 /* EMCDynamictRFC register EMC: Auto-refresh period and auto-refresh to active command period (tRFC)*/
-#define EMC_DynamictRFC_tRFC(n)			((uint32_t )(n & 0x1f))
+#define EMC_DynamictRFC_tRFC(n)         ((uint32_t )(n & 0x1f))
 
 /***********************************************************************
  * Dynamic Memory Exit Self-refresh register (EMCDynamictXSR)
  **********************************************************************/
 /* EMCDynamictXSR register EMC: Exit self-refresh to active command time (tXSR)*/
-#define EMC_DynamictXSR_tXSR(n)			((uint32_t )(n & 0x1f))
+#define EMC_DynamictXSR_tXSR(n)         ((uint32_t )(n & 0x1f))
 
 /***********************************************************************
  * Dynamic Memory Active Bank A to Active Bank B Time register (EMCDynamictRRD)
  **********************************************************************/
 /* EMCDynamictRRD register EMC: Active bank A to active bank B latency (tRRD )*/
-#define EMC_DynamictRRD_tRRD(n)			((uint32_t )(n & 0x0f))
+#define EMC_DynamictRRD_tRRD(n)         ((uint32_t )(n & 0x0f))
 
 /***********************************************************************
  Dynamic Memory Load Mode register to Active Command Time (EMCDynamictMRD)
  **********************************************************************/
 /* EMCDynamictMRD register EMC: Load mode register to active command time (tMRD)*/
-#define EMC_DynamictMRD_tMRD(n)			((uint32_t )(n & 0x1f))
+#define EMC_DynamictMRD_tMRD(n)         ((uint32_t )(n & 0x1f))
 
 /***********************************************************************
  * Static Memory Extended Wait Register (EMCStaticExtendedWait)
  **********************************************************************/
 /* StaticExtendedWait register EMC: External wait time out. */
-#define EMC_StaticExtendedWait_EXTENDEDWAIT(n)			((uint32_t )(n & 0x3ff))
+#define EMC_StaticExtendedWait_EXTENDEDWAIT(n)          ((uint32_t )(n & 0x3ff))
 
 
 /***********************************************************************
  * Dynamic Memory Configuration registers (EMCDynamicConfig0-3)
  **********************************************************************/
 /* DynamicConfig register EMC: Memory device (MD). */
-#define EMC_DynamicConfig_MD(n)			((uint32_t )(n << 3))
+#define EMC_DynamicConfig_MD(n)         ((uint32_t )(n << 3))
 /* DynamicConfig register EMC: Address mapping (AM) */
-#define EMC_DynamicConfig_AM1(n)		((uint32_t )(n << 7))
+#define EMC_DynamicConfig_AM1(n)        ((uint32_t )(n << 7))
 /* DynamicConfig register EMC: Address mapping (AM) */
-#define EMC_DynamicConfig_AM2(n)		((uint32_t )(1 << 14))
+#define EMC_DynamicConfig_AM2(n)        ((uint32_t )(1 << 14))
 /* DynamicConfig register EMC: Buffer enable */
-#define EMC_DynamicConfig_B				((uint32_t )(1 << 19))
+#define EMC_DynamicConfig_B             ((uint32_t )(1 << 19))
 /* DynamicConfig register EMC: Write protect (P) */
-#define EMC_DynamicConfig_P				((uint32_t )(1 << 20))
+#define EMC_DynamicConfig_P             ((uint32_t )(1 << 20))
 
 /***********************************************************************
  * Dynamic Memory RAS & CAS Delay registers (EMCDynamicRASCAS0-3)
  **********************************************************************/
 /* DynamicRASCAS register EMC: RAS latency (active to read/write delay) (RAS). */
-#define EMC_DynamicConfig_RAS(n)			((uint32_t )(n & 0x03))
+#define EMC_DynamicConfig_RAS(n)            ((uint32_t )(n & 0x03))
 /* DynamicRASCAS register EMC: CAS latency (CAS)*/
-#define EMC_DynamicConfig_CAS(n)			((uint32_t )(n << 8))
+#define EMC_DynamicConfig_CAS(n)            ((uint32_t )(n << 8))
 
 /***********************************************************************
  * Static Memory Configuration registers (EMCStaticConfig0-3)
  **********************************************************************/
 /* StaticConfig register EMC: Memory width (MW). */
-#define EMC_StaticConfig_MW(n)			((uint32_t )(n & 0x03))
+#define EMC_StaticConfig_MW(n)          ((uint32_t )(n & 0x03))
 /* StaticConfig register EMC: Memory width 8bit . */
-#define EMC_StaticConfig_MW_8BITS		(EMC_StaticConfig_MW(0))
+#define EMC_StaticConfig_MW_8BITS       (EMC_StaticConfig_MW(0))
 /* StaticConfig register EMC: Memory width 16bit . */
-#define EMC_StaticConfig_MW_16BITS		(EMC_StaticConfig_MW(1))
+#define EMC_StaticConfig_MW_16BITS      (EMC_StaticConfig_MW(1))
 /* StaticConfig register EMC: Memory width 32bit . */
-#define EMC_StaticConfig_MW_32BITS		(EMC_StaticConfig_MW(2))
+#define EMC_StaticConfig_MW_32BITS      (EMC_StaticConfig_MW(2))
 /* StaticConfig register EMC: Page mode (PM) */
-#define EMC_StaticConfig_PM				((uint32_t )(1 << 3))
+#define EMC_StaticConfig_PM             ((uint32_t )(1 << 3))
 /* StaticConfig register EMC: Chip select polarity (PC) */
-#define EMC_StaticConfig_PC				((uint32_t )(1 << 6))
+#define EMC_StaticConfig_PC             ((uint32_t )(1 << 6))
 /* StaticConfig register EMC: Byte lane state (PB) */
-#define EMC_StaticConfig_PB				((uint32_t )(1 << 7))
+#define EMC_StaticConfig_PB             ((uint32_t )(1 << 7))
 /* StaticConfig register EMC: Extended wait (EW) */
-#define EMC_StaticConfig_EW				((uint32_t )(1 << 8))
+#define EMC_StaticConfig_EW             ((uint32_t )(1 << 8))
 /* StaticConfig register EMC: Buffer enable (B) */
-#define EMC_StaticConfig_B				((uint32_t )(1 << 19))
+#define EMC_StaticConfig_B              ((uint32_t )(1 << 19))
 /* StaticConfig register EMC: Write protect (P) */
-#define EMC_StaticConfig_P				((uint32_t )(1 << 20))
+#define EMC_StaticConfig_P              ((uint32_t )(1 << 20))
 
 /***********************************************************************
  * Static Memory Write Enable Delay registers (EMCStaticWaitWen0-3)
  **********************************************************************/
 /* StaticWaitWen register EMC: Wait write enable (WAITWEN). */
-#define EMC_StaticWaitWen_WAITWEN(n)	((uint32_t )(n & 0x0f))
+#define EMC_StaticWaitWen_WAITWEN(n)    ((uint32_t )(n & 0x0f))
 
 /***********************************************************************
  * Static Memory Output Enable Delay registers (EMCStaticWaitOen0-3)
  **********************************************************************/
 /* StaticWaitOen register EMC: Wait output enable (WAITOEN). */
-#define EMC_StaticWaitOen_WAITOEN(n)	((uint32_t )(n & 0x0f))
+#define EMC_StaticWaitOen_WAITOEN(n)    ((uint32_t )(n & 0x0f))
 
 /***********************************************************************
  * Static Memory Read Delay registers (EMCStaticWaitRd0-3)
  **********************************************************************/
 /* StaticWaitRd register EMC: Non-page mode read wait states or asynchronous page mode
 read first access wait state (WAITRD) */
-#define EMC_StaticWaitRd_WAITRD(n)		((uint32_t )(n & 0x1f))
+#define EMC_StaticWaitRd_WAITRD(n)      ((uint32_t )(n & 0x1f))
 
 /***********************************************************************
  * Static Memory Page Mode Read Delay registers (EMCStaticwaitPage0-3)
  **********************************************************************/
 /* StaticwaitPage register EMC: Asynchronous page mode read after the first
 read wait states (WAITPAGE). */
-#define EMC_StaticwaitPage_WAITPAGE(n)	((uint32_t )(n & 0x1f))
+#define EMC_StaticwaitPage_WAITPAGE(n)  ((uint32_t )(n & 0x1f))
 
 /***********************************************************************
  * Static Memory Write Delay registers (EMCStaticWaitwr0-3)
  **********************************************************************/
 /* StaticWaitwr register EMC: Write wait states (WAITWR). */
-#define EMC_StaticWaitwr_WAITWR(n)		((uint32_t )(n & 0x1f))
+#define EMC_StaticWaitwr_WAITWR(n)      ((uint32_t )(n & 0x1f))
 
 /***********************************************************************
  * Static Memory Turn Round Delay registers (EMCStaticWaitTurn0-3)
  **********************************************************************/
 /* StaticWaitTurn register EMC: Bus turnaround cycles (WAITTURN). */
-#define EMC_StaticWaitTurn_WAITTURN(n)	((uint32_t )(n & 0x0f))
+#define EMC_StaticWaitTurn_WAITTURN(n)  ((uint32_t )(n & 0x0f))
 
 /***********************************************************************
  * Delay Control register (EMCDLYCTL)
  **********************************************************************/
-#define EMC_DLYCTL_CMDDLY(n)		((uint32_t)(n&0x1F))
-#define EMC_DLYCTL_FBCLKDLY(n)		((uint32_t)((n&0x1F)<<8))
-#define EMC_DLYCTL_CLKOUT0DLY(n)	((uint32_t)((n&0x1F)<<16))
-#define EMC_DLYCTL_CLKOUT1DLY(n)	((uint32_t)((n&0x1F)<<24))
+#define EMC_DLYCTL_CMDDLY(n)        ((uint32_t)(n&0x1F))
+#define EMC_DLYCTL_FBCLKDLY(n)      ((uint32_t)((n&0x1F)<<8))
+#define EMC_DLYCTL_CLKOUT0DLY(n)    ((uint32_t)((n&0x1F)<<16))
+#define EMC_DLYCTL_CLKOUT1DLY(n)    ((uint32_t)((n&0x1F)<<24))
 
 /***********************************************************************
  * EMC Calibration register (EMCCAL)
  **********************************************************************/
-#define EMC_CAL_CALVALUE(n)			((uint32_t)(n&0xFF))
-#define EMC_CAL_START				((uint32_t)(1<<14))
-#define EMC_CAL_DONE				((uint32_t)(1<<15))
+#define EMC_CAL_CALVALUE(n)         ((uint32_t)(n&0xFF))
+#define EMC_CAL_START               ((uint32_t)(1<<14))
+#define EMC_CAL_DONE                ((uint32_t)(1<<15))
 
-#define EMC_LITTLE_ENDIAN_MODE		((uint32_t)(0))
-#define EMC_BIG_ENDIAN_MODE			((uint32_t)(1))
+#define EMC_LITTLE_ENDIAN_MODE      ((uint32_t)(0))
+#define EMC_BIG_ENDIAN_MODE         ((uint32_t)(1))
 
 /**
  * @}
diff --git a/bsp/lpc178x/drivers/lpc177x_8x_pinsel.c b/bsp/lpc178x/drivers/lpc177x_8x_pinsel.c
index d767af1180..062224decf 100644
--- a/bsp/lpc178x/drivers/lpc177x_8x_pinsel.c
+++ b/bsp/lpc178x/drivers/lpc177x_8x_pinsel.c
@@ -1,13 +1,13 @@
 /**********************************************************************
-* $Id$		lpc177x_8x_pinsel.c			2011-06-02
+* $Id$      lpc177x_8x_pinsel.c         2011-06-02
 *//**
-* @file		lpc177x_8x_pinsel.c
-* @brief	Contains all functions support for Pin-connection block
-*			firmware library on LPC177x_8x
-* @version	1.0
-* @date		02. June. 2011
-* @author	NXP MCU SW Application Team
-* 
+* @file     lpc177x_8x_pinsel.c
+* @brief    Contains all functions support for Pin-connection block
+*           firmware library on LPC177x_8x
+* @version  1.0
+* @date     02. June. 2011
+* @author   NXP MCU SW Application Team
+*
 * Copyright(C) 2011, NXP Semiconductor
 * All rights reserved.
 *
@@ -32,39 +32,39 @@
 /* Includes ------------------------------------------------------------------- */
 #include "lpc177x_8x_pinsel.h"
 
-#define PINSEL_I2C_MODE_POS				(8)
-#define PINSEL_I2C_MODE_NUMBITS			(2)
-#define PINSEL_I2C_MODE_BITMASK			(0x03)
+#define PINSEL_I2C_MODE_POS             (8)
+#define PINSEL_I2C_MODE_NUMBITS         (2)
+#define PINSEL_I2C_MODE_BITMASK         (0x03)
 
-#define PINSEL_BASIC_MODE_POS			(3)
-#define PINSEL_BASIC_MODE_NUMBITS		(2)
-#define PINSEL_BASIC_MODE_BITMASK		(0x03)
+#define PINSEL_BASIC_MODE_POS           (3)
+#define PINSEL_BASIC_MODE_NUMBITS       (2)
+#define PINSEL_BASIC_MODE_BITMASK       (0x03)
 
-#define PINSEL_DACEN_POS				(16)
-#define PINSEL_DACEN_BITMASK			(0x01)
-#define PINSEL_DACEN_NUMBITS			(1)
+#define PINSEL_DACEN_POS                (16)
+#define PINSEL_DACEN_BITMASK            (0x01)
+#define PINSEL_DACEN_NUMBITS            (1)
 
-#define PINSEL_GLITCH_FILTER_POS				(8)
-#define PINSEL_GLITCH_FILTER_BITMASK			(0x01)
-#define PINSEL_GLITCH_FILTER_NUMBITS			(1)
+#define PINSEL_GLITCH_FILTER_POS                (8)
+#define PINSEL_GLITCH_FILTER_BITMASK            (0x01)
+#define PINSEL_GLITCH_FILTER_NUMBITS            (1)
 
-#define PINSEL_ADMODE_POS				(7)
-#define PINSEL_ADMODE_BITMASK			(0x01)
-#define PINSEL_ADMODE_NUMBITS			(1)
+#define PINSEL_ADMODE_POS               (7)
+#define PINSEL_ADMODE_BITMASK           (0x01)
+#define PINSEL_ADMODE_NUMBITS           (1)
 
 /* Private Functions ---------------------------------------------------------- */
 
 /*********************************************************************//**
- * @brief		Get pointer to GPIO peripheral due to GPIO port
- * @param[in]	portnum		Port Number value, should be in range from 0..3.
- * @param[in]	pinnum		Pin number value, should be in range from 0..31
- * @return		Pointer to GPIO peripheral
+ * @brief       Get pointer to GPIO peripheral due to GPIO port
+ * @param[in]   portnum     Port Number value, should be in range from 0..3.
+ * @param[in]   pinnum      Pin number value, should be in range from 0..31
+ * @return      Pointer to GPIO peripheral
  **********************************************************************/
 static uint32_t * PIN_GetPointer(uint8_t portnum, uint8_t pinnum)
 {
-	uint32_t *pPIN = NULL;
-	pPIN = (uint32_t *)(LPC_IOCON_BASE + ((portnum * 32 + pinnum)*sizeof(uint32_t)));
-	return pPIN;
+    uint32_t *pPIN = NULL;
+    pPIN = (uint32_t *)(LPC_IOCON_BASE + ((portnum * 32 + pinnum)*sizeof(uint32_t)));
+    return pPIN;
 }
 
 /* Public Functions ----------------------------------------------------------- */
@@ -73,268 +73,268 @@ static uint32_t * PIN_GetPointer(uint8_t portnum, uint8_t pinnum)
  */
 
 /*********************************************************************//**
- * @brief 		Setup the pin selection function
- * @param[in]	portnum PORT number, should be in range: 0..3
- * @param[in]	pinnum	Pin number, should be in range: 0..31
- * @param[in] 	funcnum Function number, should be range: 0..7
- * 				- 0: Select GPIO (Default)
- * 				- 1: Selects the 1st alternate function
- * 				- 2: Selects the 2nd alternate function
- * 				...
- *				- 7: Selects the 7th alternate function
- * @return 		None
+ * @brief       Setup the pin selection function
+ * @param[in]   portnum PORT number, should be in range: 0..3
+ * @param[in]   pinnum  Pin number, should be in range: 0..31
+ * @param[in]   funcnum Function number, should be range: 0..7
+ *              - 0: Select GPIO (Default)
+ *              - 1: Selects the 1st alternate function
+ *              - 2: Selects the 2nd alternate function
+ *              ...
+ *              - 7: Selects the 7th alternate function
+ * @return      None
  **********************************************************************/
 void PINSEL_ConfigPin ( uint8_t portnum, uint8_t pinnum, uint8_t funcnum)
 {
-	uint32_t *pPIN = NULL;
-	pPIN = PIN_GetPointer(portnum, pinnum);
-	*pPIN &= 0x00000007;//Clear function bits
-	*pPIN |= funcnum;
+    uint32_t *pPIN = NULL;
+    pPIN = PIN_GetPointer(portnum, pinnum);
+    *pPIN &= 0x00000007;//Clear function bits
+    *pPIN |= funcnum;
 }
 
 
 /*********************************************************************//**
- * @brief 		Setup resistor mode for each pin
- * @param[in]	portnum PORT number, should be in range: 0..3
- * @param[in]	pinnum	Pin number, should be in range: 0..31
- * @param[in] 	modenum: Mode number, should be in range: 0..3
-				- IOCON_MODE_PLAIN: Plain output
-				- IOCON_MODE_PULLDOWN: Pull-down enable
-				- IOCON_MODE_PULLUP: Pull-up enable
-				- IOCON_MODE_REPEATER: Repeater mode
- * @return 		None
+ * @brief       Setup resistor mode for each pin
+ * @param[in]   portnum PORT number, should be in range: 0..3
+ * @param[in]   pinnum  Pin number, should be in range: 0..31
+ * @param[in]   modenum: Mode number, should be in range: 0..3
+                - IOCON_MODE_PLAIN: Plain output
+                - IOCON_MODE_PULLDOWN: Pull-down enable
+                - IOCON_MODE_PULLUP: Pull-up enable
+                - IOCON_MODE_REPEATER: Repeater mode
+ * @return      None
  **********************************************************************/
 void PINSEL_SetPinMode ( uint8_t portnum, uint8_t pinnum, PinSel_BasicMode modenum)
 {
-	uint32_t *pPIN = NULL;
-	pPIN = PIN_GetPointer(portnum, pinnum);
-	*(uint32_t *)pPIN &= ~(3<<3);//Clear function bits
-	*(uint32_t *)pPIN |= modenum;
+    uint32_t *pPIN = NULL;
+    pPIN = PIN_GetPointer(portnum, pinnum);
+    *(uint32_t *)pPIN &= ~(3<<3);//Clear function bits
+    *(uint32_t *)pPIN |= modenum;
 }
 
 /*********************************************************************//**
- * @brief 		Setup hysteresis for each pin
- * @param[in]	portnum Port number, should be in range: 0..3
- * @param[in]	pinnum	Pin number, should be in range: 0..31
- * @param[in] 	NewState new state of Hysteresis mode, should be:
- * 				- ENABLE: Hysteresis enable
- * 				- DISABLE: Hysteresis disable
- * @return 		None
+ * @brief       Setup hysteresis for each pin
+ * @param[in]   portnum Port number, should be in range: 0..3
+ * @param[in]   pinnum  Pin number, should be in range: 0..31
+ * @param[in]   NewState new state of Hysteresis mode, should be:
+ *              - ENABLE: Hysteresis enable
+ *              - DISABLE: Hysteresis disable
+ * @return      None
  **********************************************************************/
 void PINSEL_SetHysMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState)
 {
-	uint32_t *pPIN = NULL;
-	pPIN = PIN_GetPointer(portnum, pinnum);
-	if(NewState == DISABLE)
-	{
-		*(uint32_t *)pPIN &= ~IOCON_HYS;//Clear hys bits
-	}
-	else
-		*(uint32_t *)pPIN |= IOCON_HYS;
+    uint32_t *pPIN = NULL;
+    pPIN = PIN_GetPointer(portnum, pinnum);
+    if(NewState == DISABLE)
+    {
+        *(uint32_t *)pPIN &= ~IOCON_HYS;//Clear hys bits
+    }
+    else
+        *(uint32_t *)pPIN |= IOCON_HYS;
 }
 
 /*********************************************************************//**
- * @brief 		Setup Slew rate for each pin
- * @param[in]	portnum Port number, should be in range: 0..3
- * @param[in]	pinnum	Pin number, should be in range: 0..31
- * @param[in] 	NewState new state of Slew rate control, should be:
- * 				- ENABLE: Output slew rate control is enable
- * 				- DISABLE: Output slew rate control is disable
- * @return 		None
+ * @brief       Setup Slew rate for each pin
+ * @param[in]   portnum Port number, should be in range: 0..3
+ * @param[in]   pinnum  Pin number, should be in range: 0..31
+ * @param[in]   NewState new state of Slew rate control, should be:
+ *              - ENABLE: Output slew rate control is enable
+ *              - DISABLE: Output slew rate control is disable
+ * @return      None
  **********************************************************************/
 void PINSEL_SetSlewMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState)
 {
-	uint32_t *pPIN = NULL;
-	pPIN = PIN_GetPointer(portnum, pinnum);
-	if(NewState == DISABLE)
-	{
-		*(uint32_t *)pPIN &= ~IOCON_SLEW;//Clear hys bits
-	}
-	else
-		*(uint32_t *)pPIN |= IOCON_SLEW;
+    uint32_t *pPIN = NULL;
+    pPIN = PIN_GetPointer(portnum, pinnum);
+    if(NewState == DISABLE)
+    {
+        *(uint32_t *)pPIN &= ~IOCON_SLEW;//Clear hys bits
+    }
+    else
+        *(uint32_t *)pPIN |= IOCON_SLEW;
 }
 
 /*********************************************************************//**
- * @brief 		Setup Input Buffer for each pin
- * @param[in]	portnum Port number, should be in range: 0..3
- * @param[in]	pinnum	Pin number, should be in range: 0..31
- * @param[in] 	NewState new state of Input buffer mode, should be:
- * 				- ENABLE: The input buffer is enable
- * 				- DISABLE: The input buffer is disable
- * @return 		None
+ * @brief       Setup Input Buffer for each pin
+ * @param[in]   portnum Port number, should be in range: 0..3
+ * @param[in]   pinnum  Pin number, should be in range: 0..31
+ * @param[in]   NewState new state of Input buffer mode, should be:
+ *              - ENABLE: The input buffer is enable
+ *              - DISABLE: The input buffer is disable
+ * @return      None
  **********************************************************************/
 void PINSEL_SetInBufMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState)
 {
-	uint32_t *pPIN = NULL;
-	pPIN = PIN_GetPointer(portnum, pinnum);
-	if(NewState == DISABLE)
-	{
-		*(uint32_t *)pPIN &= ~IOCON_INBUF;//Clear hys bits
-	}
-	else
-		*(uint32_t *)pPIN |= IOCON_INBUF;
+    uint32_t *pPIN = NULL;
+    pPIN = PIN_GetPointer(portnum, pinnum);
+    if(NewState == DISABLE)
+    {
+        *(uint32_t *)pPIN &= ~IOCON_INBUF;//Clear hys bits
+    }
+    else
+        *(uint32_t *)pPIN |= IOCON_INBUF;
 }
 
 /*********************************************************************//**
- * @brief 		Setup I2CMode for only pins that provide special I2C functionality
- * @param[in]	portnum Port number, should be in range: 0..3
- * @param[in]	pinnum	Pin number, should be in range: 0..31
- * @param[in] 	I2CMode I2C mode, should be:
- * 				- IOCON_I2CMODE_FAST: Fast mode and standard I2C mode
- * 				- IOCON_I2CMODE_OPENDRAIN: Open drain I/O
- * 				- IOCON_I2CMODE_FASTPLUS: Fast Mode Plus I/O
- * 				- IOCON_I2CMODE_HIGHOPENDRAIN: High drive open drain I/O
- * @return 		None
+ * @brief       Setup I2CMode for only pins that provide special I2C functionality
+ * @param[in]   portnum Port number, should be in range: 0..3
+ * @param[in]   pinnum  Pin number, should be in range: 0..31
+ * @param[in]   I2CMode I2C mode, should be:
+ *              - IOCON_I2CMODE_FAST: Fast mode and standard I2C mode
+ *              - IOCON_I2CMODE_OPENDRAIN: Open drain I/O
+ *              - IOCON_I2CMODE_FASTPLUS: Fast Mode Plus I/O
+ *              - IOCON_I2CMODE_HIGHOPENDRAIN: High drive open drain I/O
+ * @return      None
  **********************************************************************/
 void PINSEL_SetI2CMode(uint8_t portnum, uint8_t pinnum, PinSel_I2cMode I2CMode)
 {
-	uint32_t *pPIN = NULL;
-	pPIN = PIN_GetPointer(portnum, pinnum);
+    uint32_t *pPIN = NULL;
+    pPIN = PIN_GetPointer(portnum, pinnum);
 
-	*(uint32_t *)pPIN &= ~(PINSEL_I2C_MODE_BITMASK<< PINSEL_I2C_MODE_POS);
-	*(uint32_t *)pPIN |= (I2CMode << PINSEL_I2C_MODE_POS);
+    *(uint32_t *)pPIN &= ~(PINSEL_I2C_MODE_BITMASK<< PINSEL_I2C_MODE_POS);
+    *(uint32_t *)pPIN |= (I2CMode << PINSEL_I2C_MODE_POS);
 }
 
 /*********************************************************************//**
- * @brief 		Setup Open-drain mode in each pin
- * @param[in]	portnum Port number, should be in range: 0..3
- * @param[in]	pinnum	Pin number, should be in range: 0..31
- * @param[in] 	NewState new state of Open-drain mode:
- * 				- DISABLE: Normal pin I/O mode
- * 				- ENABLE: Open-drain enable
- * @return 		None
+ * @brief       Setup Open-drain mode in each pin
+ * @param[in]   portnum Port number, should be in range: 0..3
+ * @param[in]   pinnum  Pin number, should be in range: 0..31
+ * @param[in]   NewState new state of Open-drain mode:
+ *              - DISABLE: Normal pin I/O mode
+ *              - ENABLE: Open-drain enable
+ * @return      None
  **********************************************************************/
 void PINSEL_SetOpenDrainMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState)
 {
-	uint32_t *pPIN = NULL;
-	pPIN = PIN_GetPointer(portnum, pinnum);
-	if(NewState == DISABLE)
-	{
-		*(uint32_t *)pPIN &= ~IOCON_ODMODE;//Clear hys bits
-	}
-	else
-	{
-		*(uint32_t *)pPIN |= IOCON_ODMODE;
-	}
+    uint32_t *pPIN = NULL;
+    pPIN = PIN_GetPointer(portnum, pinnum);
+    if(NewState == DISABLE)
+    {
+        *(uint32_t *)pPIN &= ~IOCON_ODMODE;//Clear hys bits
+    }
+    else
+    {
+        *(uint32_t *)pPIN |= IOCON_ODMODE;
+    }
 }
 
 /*********************************************************************//**
- * @brief 		Enable the Analog mode for each pin (default is as Digital pins)
- * @param[in]	portnum PORT number, should be in range: 0..3
- * @param[in]	pinnum	Pin number, should be in range: 0..31
- * @param[in] 	enable: the state of the pin that is expected to run
-				- ENABLE: Enable the DAC mode of the pin
-				- DISABLE: Disable the DAC mode
- * @return 		None
+ * @brief       Enable the Analog mode for each pin (default is as Digital pins)
+ * @param[in]   portnum PORT number, should be in range: 0..3
+ * @param[in]   pinnum  Pin number, should be in range: 0..31
+ * @param[in]   enable: the state of the pin that is expected to run
+                - ENABLE: Enable the DAC mode of the pin
+                - DISABLE: Disable the DAC mode
+ * @return      None
  **********************************************************************/
 void PINSEL_SetAnalogPinMode (uint8_t portnum, uint8_t pinnum, uint8_t enable)
 {
-	uint32_t *pPIN = NULL;
+    uint32_t *pPIN = NULL;
 
-	uint8_t condition = 0;
+    uint8_t condition = 0;
 
-	condition = ((portnum == 0) && (pinnum == 12)) || ((portnum == 0) && (pinnum == 13))
-					| ((portnum == 0) && (pinnum <= 26) && (pinnum >= 23))
-					| ((portnum == 1) && (pinnum == 30)) || ((portnum == 1) && (pinnum == 31));
+    condition = ((portnum == 0) && (pinnum == 12)) || ((portnum == 0) && (pinnum == 13))
+                    | ((portnum == 0) && (pinnum <= 26) && (pinnum >= 23))
+                    | ((portnum == 1) && (pinnum == 30)) || ((portnum == 1) && (pinnum == 31));
 
-	if(!condition)
-	{
-		return;
-	}
+    if(!condition)
+    {
+        return;
+    }
 
-	pPIN = PIN_GetPointer(portnum, pinnum);
+    pPIN = PIN_GetPointer(portnum, pinnum);
 
-	//Clear this bit to set the pin to Analog mode
-	*(uint32_t *)pPIN &= ~(PINSEL_ADMODE_BITMASK << PINSEL_ADMODE_POS);
+    //Clear this bit to set the pin to Analog mode
+    *(uint32_t *)pPIN &= ~(PINSEL_ADMODE_BITMASK << PINSEL_ADMODE_POS);
 
-	if(enable)
-	{
+    if(enable)
+    {
 
-	}
-	else
-	{
-		*(uint32_t *)pPIN |= (1 << PINSEL_ADMODE_POS);//Set 16th bit to one
-	}
+    }
+    else
+    {
+        *(uint32_t *)pPIN |= (1 << PINSEL_ADMODE_POS);//Set 16th bit to one
+    }
 
-	return;
+    return;
 }
 
 
 
 /*********************************************************************//**
- * @brief 		Choose the DAC mode for each pin
- * @param[in]	portnum PORT number, should be in range: 0..3
- * @param[in]	pinnum	Pin number, should be in range: 0..31
- * @param[in] 	enable: the state of the pin that is expected to run
-				- ENABLE: Enable the DAC mode of the pin
-				- DISABLE: Disable the DAC mode
- * @return 		None
+ * @brief       Choose the DAC mode for each pin
+ * @param[in]   portnum PORT number, should be in range: 0..3
+ * @param[in]   pinnum  Pin number, should be in range: 0..31
+ * @param[in]   enable: the state of the pin that is expected to run
+                - ENABLE: Enable the DAC mode of the pin
+                - DISABLE: Disable the DAC mode
+ * @return      None
  **********************************************************************/
 void PINSEL_DacEnable (uint8_t portnum, uint8_t pinnum, uint8_t enable)
 {
-	uint32_t *pPIN = NULL;
+    uint32_t *pPIN = NULL;
 
-	// This setting is only for DAC pin (output pin)
-	if(!((portnum == 0) && (pinnum == 26)))
-	{
-		return;
-	}
+    // This setting is only for DAC pin (output pin)
+    if(!((portnum == 0) && (pinnum == 26)))
+    {
+        return;
+    }
 
-	pPIN = PIN_GetPointer(portnum, pinnum);
+    pPIN = PIN_GetPointer(portnum, pinnum);
 
-	//Clear DAC Enable function bits
-	*(uint32_t *)pPIN &= ~(PINSEL_DACEN_BITMASK << PINSEL_DACEN_POS);
+    //Clear DAC Enable function bits
+    *(uint32_t *)pPIN &= ~(PINSEL_DACEN_BITMASK << PINSEL_DACEN_POS);
 
-	if(enable)
-	{
-		*(uint32_t *)pPIN |= (1 << PINSEL_DACEN_POS);//Set 16th bit to one
-	}
-	else
-	{
+    if(enable)
+    {
+        *(uint32_t *)pPIN |= (1 << PINSEL_DACEN_POS);//Set 16th bit to one
+    }
+    else
+    {
 
-	}
+    }
 
-	return;
+    return;
 }
 
 /*********************************************************************//**
- * @brief 		Control the glitch filter for each pin
- * @param[in]	portnum PORT number, should be in range: 0..3
- * @param[in]	pinnum	Pin number, should be in range: 0..31
- * @param[in] 	enable: the state of the pin that is expected to run
-				- ENABLE: The noise pulses below approximately 10ns are filtered out
-				- DISABLE: No input filtering is done.
- * @return 		None
+ * @brief       Control the glitch filter for each pin
+ * @param[in]   portnum PORT number, should be in range: 0..3
+ * @param[in]   pinnum  Pin number, should be in range: 0..31
+ * @param[in]   enable: the state of the pin that is expected to run
+                - ENABLE: The noise pulses below approximately 10ns are filtered out
+                - DISABLE: No input filtering is done.
+ * @return      None
  **********************************************************************/
 void PINSEL_SetFilter (uint8_t portnum, uint8_t pinnum, uint8_t enable)
 {
-	uint32_t *pPIN = NULL;
+    uint32_t *pPIN = NULL;
 
-	// This setting is only for DAC pin (output pin)
-	if(!((portnum == 0) && ((pinnum == 7) || (pinnum == 8) || (pinnum == 9))))
-	{
-		return;
-	}
+    // This setting is only for DAC pin (output pin)
+    if(!((portnum == 0) && ((pinnum == 7) || (pinnum == 8) || (pinnum == 9))))
+    {
+        return;
+    }
 
-	pPIN = PIN_GetPointer(portnum, pinnum);
+    pPIN = PIN_GetPointer(portnum, pinnum);
 
-	*(uint32_t *)pPIN |= (1 << 7);//Set 7th bit for normal operation following the UM1.0
+    *(uint32_t *)pPIN |= (1 << 7);//Set 7th bit for normal operation following the UM1.0
 
-	//Clear Filter bits
-	*(uint32_t *)pPIN &= ~(PINSEL_GLITCH_FILTER_BITMASK << PINSEL_GLITCH_FILTER_POS);
+    //Clear Filter bits
+    *(uint32_t *)pPIN &= ~(PINSEL_GLITCH_FILTER_BITMASK << PINSEL_GLITCH_FILTER_POS);
 
-	if(!enable)
-	{
-		*(uint32_t *)pPIN |= (1 << PINSEL_GLITCH_FILTER_POS);//Set 8th bit to one
-	}
-	else
-	{
+    if(!enable)
+    {
+        *(uint32_t *)pPIN |= (1 << PINSEL_GLITCH_FILTER_POS);//Set 8th bit to one
+    }
+    else
+    {
 
-	}
+    }
 
-	*pPIN = *pPIN;
+    *pPIN = *pPIN;
 
-	return;
+    return;
 }
 
 /**
diff --git a/bsp/lpc178x/drivers/lpc177x_8x_pinsel.h b/bsp/lpc178x/drivers/lpc177x_8x_pinsel.h
index ca83c91fc5..d7a291cff7 100644
--- a/bsp/lpc178x/drivers/lpc177x_8x_pinsel.h
+++ b/bsp/lpc178x/drivers/lpc177x_8x_pinsel.h
@@ -1,13 +1,13 @@
 /**********************************************************************
-* $Id$		lpc177x_8x_pinsel.h			2011-06-02
+* $Id$      lpc177x_8x_pinsel.h         2011-06-02
 *//**
-* @file		lpc177x_8x_pinsel.h
-* @brief	Contains all macro definitions and function prototypes
-*			support for Pin-connection block firmware library on LPC177x_8x
-* @version	1.0
-* @date		02. June. 2011
-* @author	NXP MCU SW Application Team
-* 
+* @file     lpc177x_8x_pinsel.h
+* @brief    Contains all macro definitions and function prototypes
+*           support for Pin-connection block firmware library on LPC177x_8x
+* @version  1.0
+* @date     02. June. 2011
+* @author   NXP MCU SW Application Team
+*
 * Copyright(C) 2011, NXP Semiconductor
 * All rights reserved.
 *
@@ -25,7 +25,7 @@
 **********************************************************************/
 
 /* Peripheral group ----------------------------------------------------------- */
-/** @defgroup PINSEL	Pin Selection
+/** @defgroup PINSEL    Pin Selection
  * @ingroup LPC177x_8xCMSIS_FwLib_Drivers
  * @{
  */
@@ -44,160 +44,160 @@
  */
 
 /* Macros define IOCON bits */
-#define IOCON_MODE_PLAIN			((0<<3))
-#define IOCON_MODE_PULLDOWN			((1<<3))
-#define IOCON_MODE_PULLUP			((2<<3))
-#define IOCON_MODE_REPEATER			((3<<3))
-#define IOCON_HYS					((1<<5))
-#define IOCON_SLEW					((1<<6))
-#define IOCON_INBUF					((1<<7))
-#define IOCON_I2CMODE_FAST			((0<<8))
-#define IOCON_I2CMODE_OPENDRAIN		((1<<8))
-#define IOCON_I2CMODE_FASTPLUS		((2<<8))
-#define IOCON_I2CMODE_HIGHOPENDRAIN	((3<<8))
-#define IOCON_ODMODE				((1<<10))
+#define IOCON_MODE_PLAIN            ((0<<3))
+#define IOCON_MODE_PULLDOWN         ((1<<3))
+#define IOCON_MODE_PULLUP           ((2<<3))
+#define IOCON_MODE_REPEATER         ((3<<3))
+#define IOCON_HYS                   ((1<<5))
+#define IOCON_SLEW                  ((1<<6))
+#define IOCON_INBUF                 ((1<<7))
+#define IOCON_I2CMODE_FAST          ((0<<8))
+#define IOCON_I2CMODE_OPENDRAIN     ((1<<8))
+#define IOCON_I2CMODE_FASTPLUS      ((2<<8))
+#define IOCON_I2CMODE_HIGHOPENDRAIN ((3<<8))
+#define IOCON_ODMODE                ((1<<10))
 
 
 /* Macros define for LOC registers */
-#define LOC_CAN_RD_1_P0_0			((0))	/**< Input for CAN_RD_1 comes from P0.0 */
-#define LOC_CAN_RD_1_P0_21			((1))	/**< Input for CAN_RD_1 comes from P0.21 */
-#define LOC_CAN_RD_2_P2_7			((0))	/**< Input for CAN_RD_2 comes from P2.7 */
-#define LOC_CAN_RD_2_P0_4			((1))	/**< Input for CAN_RD_2 comes from P0.4 */
-#define LOC_ENET_MDIO_P2_9			((0))	/**< Input for ENET_MDIO comes from P2.9 */
-#define LOC_ENET_MDIO_P1_17			((1))	/**< Input for ENET_MDIO comes from P1.17 */
-#define LOC_EINT_0_P0_29			((0))	/**< Input for EINT_0 comes from P0.29 */
-#define LOC_EINT_0_P2_10			((1))	/**< Input for EINT_0 comes from P2.10 */
-#define LOC_EINT_1_P0_30			((0))	/**< Input for EINT_1 comes from P0.30 */
-#define LOC_EINT_1_P2_11			((1))	/**< Input for EINT_1 comes from P2.11 */
-#define LOC_I2C0_SCL_P1_31			((0))	/**< Input for I2C0_SCL comes from P1.31 */
-#define LOC_I2C0_SCL_P0_28			((1))	/**< Input for I2C0_SCL comes from P0.28 */
-#define LOC_I2C0_SCL_P5_3			((2))	/**< Input for I2C0_SCL comes from P5.3 */
-#define LOC_I2C0_SDA_P1_30			((0))	/**< Input for I2C0_SDA comes from P1.30 */
-#define LOC_I2C0_SDA_P0_27			((1))	/**< Input for I2C0_SDA comes from P0.27 */
-#define LOC_I2C0_SDA_P5_2			((2))	/**< Input for I2C0_SDA comes from P5.2 */
-#define LOC_I2C1_SCL_P0_1			((0))	/**< Input for I2C1_SCL comes from P0.1 */
-#define LOC_I2C1_SCL_P2_15			((1))	/**< Input for I2C1_SCL comes from P2.15 */
-#define LOC_I2C1_SCL_P0_20			((2))	/**< Input for I2C1_SCL comes from P0.20 */
-#define LOC_I2C1_SDA_P2_14			((0))	/**< Input for I2C1_SDA comes from P2.14 */
-#define LOC_I2C1_SDA_P0_0			((1))	/**< Input for I2C1_SDA comes from P0.0 */
-#define LOC_I2C1_SDA_P0_19			((2))	/**< Input for I2C1_SDA comes from P0.19 */
-#define LOC_I2C2_SCL_P2_31			((0))	/**< Input for I2C2_SCL comes from P2.31 */
-#define LOC_I2C2_SCL_P0_11			((1))	/**< Input for I2C2_SCL comes from P0.11 */
-#define LOC_I2C2_SCL_P4_21			((2))	/**< Input for I2C2_SCL comes from P4.21 */
-#define LOC_I2C2_SCL_P4_29			((3))	/**< Input for I2C2_SCL comes from P4.29 */
-#define LOC_I2C2_SDA_P2_30			((0))	/**< Input for I2C2_SDA comes from P2.30 */
-#define LOC_I2C2_SDA_P0_10			((1))	/**< Input for I2C2_SDA comes from P0.10 */
-#define LOC_I2C2_SDA_P4_20			((2))	/**< Input for I2C2_SDA comes from P4.20 */
-#define LOC_I2C2_SDA_P1_15			((3))	/**< Input for I2C2_SDA comes from P1.15 */
-#define LOC_I2S_RX_SCK_P0_23		((0))	/**< Input for I2S_RX_SCK comes from P0.23 */
-#define LOC_I2S_RX_SCK_P0_4			((1))	/**< Input for I2S_RX_SCK comes from P0.4 */
-#define LOC_I2S_RX_SDA_P0_25		((0))	/**< Input for I2S_RX_SDA comes from P0.25 */
-#define LOC_I2S_RX_SDA_P0_6			((1))	/**< Input for I2S_RX_SDA comes from P0.6 */
-#define LOC_I2S_RX_WS_P0_24			((0))	/**< Input for I2S_RX_WS comes from P0.24 */
-#define LOC_I2S_RX_WS_P0_5			((1))	/**< Input for I2S_RX_WS comes from P0.5 */
-#define LOC_I2S_TX_SCK_P2_11		((0))	/**< Input for I2S_TX_SCK comes from P2.11 */
-#define LOC_I2S_TX_SCK_P0_7			((1))	/**< Input for I2S_TX_SCK comes from P0.7 */
-#define LOC_I2S_TX_WS_P2_12			((0))	/**< Input for I2S_TX_WS comes from P2.12 */
-#define LOC_I2S_TX_WS_P0_8			((1))	/**< Input for I2S_TX_WS comes from P0.8 */
-#define LOC_PWM0_CAP_0_P1_12		((0))	/**< Input for PWM0_CAP_0 comes from P1.12 */
-#define LOC_PWM0_CAP_0_P3_22		((1))	/**< Input for PWM0_CAP_0 comes from P3.22 */
-#define LOC_PWM1_CAP_0_P3_23		((0))	/**< Input for PWM1_CAP_0 comes from P3.23 */
-#define LOC_PWM1_CAP_0_P1_28		((1))	/**< Input for PWM1_CAP_0 comes from P1.28 */
-#define LOC_PWM1_CAP_0_P2_6			((2))	/**< Input for PWM1_CAP_0 comes from P2.6 */
-#define LOC_SD_CMD_P0_20			((0))	/**< Input for SD_CMD comes from P0.20 */
-#define LOC_SD_CMD_P1_3				((1))	/**< Input for SD_CMD comes from P1.3 */
-#define LOC_SD_DAT_0_P0_22			((0))	/**< Input for SD_DAT_0 comes from P0.22 */
-#define LOC_SD_DAT_0_P1_6			((1))	/**< Input for SD_DAT_0 comes from P1.6 */
-#define LOC_SD_DAT_1_P2_11			((0))	/**< Input for SD_DAT_1 comes from P2.11 */
-#define LOC_SD_DAT_1_P1_7			((1))	/**< Input for SD_DAT_1 comes from P1.7 */
-#define LOC_SD_DAT_2_P2_12			((0))	/**< Input for SD_DAT_2 comes from P2.12 */
-#define LOC_SD_DAT_2_P1_11			((1))	/**< Input for SD_DAT_2 comes from P1.11 */
-#define LOC_SD_DAT_3_P2_13			((0))	/**< Input for SD_DAT_3 comes from P2.13 */
-#define LOC_SD_DAT_3_P1_12			((1))	/**< Input for SD_DAT_3 comes from P1.12 */
-#define LOC_SSP0_MISO_P2_26			((0))	/**< Input for SSP0_MISO comes from P2.26 */
-#define LOC_SSP0_MISO_P1_23			((1))	/**< Input for SSP0_MISO comes from P1_23 */
-#define LOC_SSP0_MISO_P0_17			((2))	/**< Input for SSP0_MISO comes from P0_17 */
-#define LOC_SSP0_MOSI_P2_27			((0))	/**< Input for SSP0_MOSI comes from P2.27 */
-#define LOC_SSP0_MOSI_P1_24			((1))	/**< Input for SSP0_MOSI comes from P1.24 */
-#define LOC_SSP0_MOSI_P0_18			((2))	/**< Input for SSP0_MOSI comes from P0.18 */
-#define LOC_SSP0_SCK_P1_20			((0))	/**< Input for SSP0_SCK comes from P1.20 */
-#define LOC_SSP0_SCK_P2_22			((1))	/**< Input for SSP0_SCK comes from P2.22 */
-#define LOC_SSP0_SCK_P0_15			((2))	/**< Input for SSP0_SCK comes from P0_15 */
-#define LOC_SSP0_SSEL_P2_23			((0))	/**< Input for SSP0_SSEL comes from P2.23 */
-#define LOC_SSP0_SSEL_P1_21			((1))	/**< Input for SSP0_SSEL comes from P1.21 */
-#define LOC_SSP0_SSEL_P1_28			((2))	/**< Input for SSP0_SSEL comes from P1.28 */
-#define LOC_SSP0_SSEL_P0_16			((3))	/**< Input for SSP0_SSEL comes from P0.16 */
-#define LOC_SSP1_MISO_P0_12			((0))	/**< Input for SSP1_MISO comes from P0.12 */
-#define LOC_SSP1_MISO_P1_18			((1))	/**< Input for SSP1_MISO comes from P1.18 */
-#define LOC_SSP1_MISO_P4_22			((2))	/**< Input for SSP1_MISO comes from P4_22 */
-#define LOC_SSP1_MISO_P0_8			((3))	/**< Input for SSP1_MISO comes from P0.8 */
-#define LOC_SSP1_MOSI_P0_13			((0))	/**< Input for SSP1_MOSI comes from P0.13 */
-#define LOC_SSP1_MOSI_P1_22			((1))	/**< Input for SSP1_MOSI comes from P1.22 */
-#define LOC_SSP1_MOSI_P4_23			((2))	/**< Input for SSP1_MOSI comes from P4.23 */
-#define LOC_SSP1_MOSI_P0_9			((3))	/**< Input for SSP1_MOSI comes from P0.9 */
-#define LOC_SSP1_SCK_P1_31			((0))	/**< Input for SSP1_SCK comes from P1.31 */
-#define LOC_SSP1_SCK_P1_19			((1))	/**< Input for SSP1_SCK comes from P1.19 */
-#define LOC_SSP1_SCK_P4_20			((2))	/**< Input for SSP1_SCK comes from P4_20 */
-#define LOC_SSP1_SCK_P0_7			((3))	/**< Input for SSP1_SCK comes from P0_7 */
-#define LOC_SSP1_SSEL_P0_14			((0))	/**< Input for SSP1_SSEL comes from P0.14 */
-#define LOC_SSP1_SSEL_P1_26			((1))	/**< Input for SSP1_SSEL comes from P1.26 */
-#define LOC_SSP1_SSEL_P4_21			((2))	/**< Input for SSP1_SSEL comes from P4.21 */
-#define LOC_SSP1_SSEL_P0_6			((3))	/**< Input for SSP1_SSEL comes from P0.6 */
-#define LOC_SSP2_MISO_P1_4			((1))	/**< Input for SSP2_MISO comes from P1.4 */
-#define LOC_SSP2_MOSI_P1_1			((1))	/**< Input for SSP2_MOSI comes from P1.1 */
-#define LOC_SSP2_SCK_P1_0			((1))	/**< Input for SSP2_SCK comes from P1.0 */
-#define LOC_SSP2_SSEL_P1_8			((1))	/**< Input for SSP2_SSEL comes from P1.8 */
-#define LOC_T0_CAP_0_P3_23			((0))	/**< Input for T0_CAP_0 comes from P3.23 */
-#define LOC_T0_CAP_0_P1_26			((1))	/**< Input for T0_CAP_0 comes from P1.26 */
-#define LOC_T0_CAP_1_P3_24			((0))	/**< Input for T0_CAP_1 comes from P3.24 */
-#define LOC_T0_CAP_1_P1_27			((1))	/**< Input for T0_CAP_1 comes from P1.27 */
-#define LOC_T1_CAP_0_P1_18			((0))	/**< Input for T1_CAP_0 comes from P1.18 */
-#define LOC_T1_CAP_0_P3_27			((1))	/**< Input for T1_CAP_0 comes from P3.27 */
-#define LOC_T1_CAP_1_P3_28			((0))	/**< Input for T1_CAP_1 comes from P3.28 */
-#define LOC_T1_CAP_1_P1_19			((1))	/**< Input for T1_CAP_1 comes from P1.19 */
-#define LOC_T2_CAP_0_P2_14			((0))	/**< Input for T2_CAP_0 comes from P2.14 */
-#define LOC_T2_CAP_0_P2_6			((1))	/**< Input for T2_CAP_0 comes from P2.6 */
-#define LOC_T2_CAP_0_P0_4			((2))	/**< Input for T2_CAP_0 comes from P0.4 */
-#define LOC_T2_CAP_0_P1_14			((3))	/**< Input for T2_CAP_0 comes from P1.14 */
-#define LOC_T2_CAP_1_P2_15			((0))	/**< Input for T2_CAP_1 comes from P2.15 */
-#define LOC_T2_CAP_1_P0_5			((1))	/**< Input for T2_CAP_1 comes from P0.5 */
-#define LOC_T3_CAP_0_P0_23			((0))	/**< Input for T3_CAP_0 comes from P0.23 */
-#define LOC_T3_CAP_0_P2_22			((1))	/**< Input for T3_CAP_0 comes from P2.22 */
-#define LOC_T3_CAP_0_P1_10			((2))	/**< Input for T3_CAP_0 comes from P1.10 */
-#define LOC_T3_CAP_1_P0_24			((0))	/**< Input for T3_CAP_1 comes from P0.24 */
-#define LOC_T3_CAP_1_P2_23			((1))	/**< Input for T3_CAP_1 comes from P2.23 */
-#define LOC_T3_CAP_1_P1_0			((2))	/**< Input for T3_CAP_1 comes from P1.0 */
-#define LOC_U0_RXD_P0_1				((0))	/**< Input for U0_RXD comes from P0.1 */
-#define LOC_U0_RXD_P0_3				((1))	/**< Input for U0_RXD comes from P0.3 */
-#define LOC_U1_CTS_P0_17			((0))	/**< Input for U1_CTS comes from P0.17 */
-#define LOC_U1_CTS_P2_8				((1))	/**< Input for U1_CTS comes from P2.8 */
-#define LOC_U1_CTS_P2_2				((2))	/**< Input for U1_CTS comes from P2.2 */
-#define LOC_U1_CTS_P3_18			((3))	/**< Input for U1_CTS comes from P3.18 */
-#define LOC_U1_DCD_P0_18			((0))	/**< Input for U1_DCD comes from P0.18 */
-#define LOC_U1_DCD_P2_3				((1))	/**< Input for U1_DCD comes from P2.3 */
-#define LOC_U1_DCD_P3_19			((2))	/**< Input for U1_DCD comes from P3_19 */
-#define LOC_U1_DSR_P0_19			((0))	/**< Input for U1_DSR comes from P0.19 */
-#define LOC_U1_DSR_P2_4				((1))	/**< Input for U1_DSR comes from P2.4 */
-#define LOC_U1_DSR_P3_20			((2))	/**< Input for U1_DSR comes from P0.19 */
-#define LOC_U1_RI_P0_21				((0))	/**< Input for U1_RI comes from P0.21 */
-#define LOC_U1_RI_P2_6				((1))	/**< Input for U1_RI comes from P2.6 */
-#define LOC_U1_RI_P3_22				((2))	/**< Input for U1_RI comes from P3.22 */
-#define LOC_U1_RXD_P0_16			((0))	/**< Input for U1_RXD comes from P0.16 */
-#define LOC_U1_RXD_P3_17			((1))	/**< Input for U1_RXD comes from P3.17 */
-#define LOC_U1_RXD_P2_1				((2))	/**< Input for U1_RXD comes from P2.1 */
-#define LOC_U2_RXD_P0_11			((0))	/**< Input for U2_RXD comes from P0.11 */
-#define LOC_U2_RXD_P4_23			((1))	/**< Input for U2_RXD comes from P4.23 */
-#define LOC_U2_RXD_P2_9				((2))	/**< Input for U2_RXD comes from P2.9 */
-#define LOC_U3_RXD_P0_26			((0))	/**< Input for U3_RXD comes from P0.26 */
-#define LOC_U3_RXD_P0_1				((1))	/**< Input for U3_RXD comes from P0.1 */
-#define LOC_U3_RXD_P4_29			((2))	/**< Input for U3_RXD comes from P4.29 */
-#define LOC_U3_RXD_P0_3				((3))	/**< Input for U3_RXD comes from P0.3 */
-#define LOC_U4_RXD_P2_9				((0))	/**< Input for U4_RXD comes from P2.9 */
-#define LOC_U4_RXD_P5_3				((1))	/**< Input for U4_RXD comes from P5.3 */
-#define LOC_USB_SCL_P0_28			((0))	/**< Input for USB_SCL comes from P0.28 */
-#define LOC_USB_SCL_P1_28			((1))	/**< Input for USB_SCL comes from P1.28 */
-#define LOC_USB_SDA_P0_27			((0))	/**< Input for USB_SDA comes from P0.27 */
-#define LOC_USB_SDA_P1_29			((1))	/**< Input for USB_SDA comes from P1.29 */
+#define LOC_CAN_RD_1_P0_0           ((0))   /**< Input for CAN_RD_1 comes from P0.0 */
+#define LOC_CAN_RD_1_P0_21          ((1))   /**< Input for CAN_RD_1 comes from P0.21 */
+#define LOC_CAN_RD_2_P2_7           ((0))   /**< Input for CAN_RD_2 comes from P2.7 */
+#define LOC_CAN_RD_2_P0_4           ((1))   /**< Input for CAN_RD_2 comes from P0.4 */
+#define LOC_ENET_MDIO_P2_9          ((0))   /**< Input for ENET_MDIO comes from P2.9 */
+#define LOC_ENET_MDIO_P1_17         ((1))   /**< Input for ENET_MDIO comes from P1.17 */
+#define LOC_EINT_0_P0_29            ((0))   /**< Input for EINT_0 comes from P0.29 */
+#define LOC_EINT_0_P2_10            ((1))   /**< Input for EINT_0 comes from P2.10 */
+#define LOC_EINT_1_P0_30            ((0))   /**< Input for EINT_1 comes from P0.30 */
+#define LOC_EINT_1_P2_11            ((1))   /**< Input for EINT_1 comes from P2.11 */
+#define LOC_I2C0_SCL_P1_31          ((0))   /**< Input for I2C0_SCL comes from P1.31 */
+#define LOC_I2C0_SCL_P0_28          ((1))   /**< Input for I2C0_SCL comes from P0.28 */
+#define LOC_I2C0_SCL_P5_3           ((2))   /**< Input for I2C0_SCL comes from P5.3 */
+#define LOC_I2C0_SDA_P1_30          ((0))   /**< Input for I2C0_SDA comes from P1.30 */
+#define LOC_I2C0_SDA_P0_27          ((1))   /**< Input for I2C0_SDA comes from P0.27 */
+#define LOC_I2C0_SDA_P5_2           ((2))   /**< Input for I2C0_SDA comes from P5.2 */
+#define LOC_I2C1_SCL_P0_1           ((0))   /**< Input for I2C1_SCL comes from P0.1 */
+#define LOC_I2C1_SCL_P2_15          ((1))   /**< Input for I2C1_SCL comes from P2.15 */
+#define LOC_I2C1_SCL_P0_20          ((2))   /**< Input for I2C1_SCL comes from P0.20 */
+#define LOC_I2C1_SDA_P2_14          ((0))   /**< Input for I2C1_SDA comes from P2.14 */
+#define LOC_I2C1_SDA_P0_0           ((1))   /**< Input for I2C1_SDA comes from P0.0 */
+#define LOC_I2C1_SDA_P0_19          ((2))   /**< Input for I2C1_SDA comes from P0.19 */
+#define LOC_I2C2_SCL_P2_31          ((0))   /**< Input for I2C2_SCL comes from P2.31 */
+#define LOC_I2C2_SCL_P0_11          ((1))   /**< Input for I2C2_SCL comes from P0.11 */
+#define LOC_I2C2_SCL_P4_21          ((2))   /**< Input for I2C2_SCL comes from P4.21 */
+#define LOC_I2C2_SCL_P4_29          ((3))   /**< Input for I2C2_SCL comes from P4.29 */
+#define LOC_I2C2_SDA_P2_30          ((0))   /**< Input for I2C2_SDA comes from P2.30 */
+#define LOC_I2C2_SDA_P0_10          ((1))   /**< Input for I2C2_SDA comes from P0.10 */
+#define LOC_I2C2_SDA_P4_20          ((2))   /**< Input for I2C2_SDA comes from P4.20 */
+#define LOC_I2C2_SDA_P1_15          ((3))   /**< Input for I2C2_SDA comes from P1.15 */
+#define LOC_I2S_RX_SCK_P0_23        ((0))   /**< Input for I2S_RX_SCK comes from P0.23 */
+#define LOC_I2S_RX_SCK_P0_4         ((1))   /**< Input for I2S_RX_SCK comes from P0.4 */
+#define LOC_I2S_RX_SDA_P0_25        ((0))   /**< Input for I2S_RX_SDA comes from P0.25 */
+#define LOC_I2S_RX_SDA_P0_6         ((1))   /**< Input for I2S_RX_SDA comes from P0.6 */
+#define LOC_I2S_RX_WS_P0_24         ((0))   /**< Input for I2S_RX_WS comes from P0.24 */
+#define LOC_I2S_RX_WS_P0_5          ((1))   /**< Input for I2S_RX_WS comes from P0.5 */
+#define LOC_I2S_TX_SCK_P2_11        ((0))   /**< Input for I2S_TX_SCK comes from P2.11 */
+#define LOC_I2S_TX_SCK_P0_7         ((1))   /**< Input for I2S_TX_SCK comes from P0.7 */
+#define LOC_I2S_TX_WS_P2_12         ((0))   /**< Input for I2S_TX_WS comes from P2.12 */
+#define LOC_I2S_TX_WS_P0_8          ((1))   /**< Input for I2S_TX_WS comes from P0.8 */
+#define LOC_PWM0_CAP_0_P1_12        ((0))   /**< Input for PWM0_CAP_0 comes from P1.12 */
+#define LOC_PWM0_CAP_0_P3_22        ((1))   /**< Input for PWM0_CAP_0 comes from P3.22 */
+#define LOC_PWM1_CAP_0_P3_23        ((0))   /**< Input for PWM1_CAP_0 comes from P3.23 */
+#define LOC_PWM1_CAP_0_P1_28        ((1))   /**< Input for PWM1_CAP_0 comes from P1.28 */
+#define LOC_PWM1_CAP_0_P2_6         ((2))   /**< Input for PWM1_CAP_0 comes from P2.6 */
+#define LOC_SD_CMD_P0_20            ((0))   /**< Input for SD_CMD comes from P0.20 */
+#define LOC_SD_CMD_P1_3             ((1))   /**< Input for SD_CMD comes from P1.3 */
+#define LOC_SD_DAT_0_P0_22          ((0))   /**< Input for SD_DAT_0 comes from P0.22 */
+#define LOC_SD_DAT_0_P1_6           ((1))   /**< Input for SD_DAT_0 comes from P1.6 */
+#define LOC_SD_DAT_1_P2_11          ((0))   /**< Input for SD_DAT_1 comes from P2.11 */
+#define LOC_SD_DAT_1_P1_7           ((1))   /**< Input for SD_DAT_1 comes from P1.7 */
+#define LOC_SD_DAT_2_P2_12          ((0))   /**< Input for SD_DAT_2 comes from P2.12 */
+#define LOC_SD_DAT_2_P1_11          ((1))   /**< Input for SD_DAT_2 comes from P1.11 */
+#define LOC_SD_DAT_3_P2_13          ((0))   /**< Input for SD_DAT_3 comes from P2.13 */
+#define LOC_SD_DAT_3_P1_12          ((1))   /**< Input for SD_DAT_3 comes from P1.12 */
+#define LOC_SSP0_MISO_P2_26         ((0))   /**< Input for SSP0_MISO comes from P2.26 */
+#define LOC_SSP0_MISO_P1_23         ((1))   /**< Input for SSP0_MISO comes from P1_23 */
+#define LOC_SSP0_MISO_P0_17         ((2))   /**< Input for SSP0_MISO comes from P0_17 */
+#define LOC_SSP0_MOSI_P2_27         ((0))   /**< Input for SSP0_MOSI comes from P2.27 */
+#define LOC_SSP0_MOSI_P1_24         ((1))   /**< Input for SSP0_MOSI comes from P1.24 */
+#define LOC_SSP0_MOSI_P0_18         ((2))   /**< Input for SSP0_MOSI comes from P0.18 */
+#define LOC_SSP0_SCK_P1_20          ((0))   /**< Input for SSP0_SCK comes from P1.20 */
+#define LOC_SSP0_SCK_P2_22          ((1))   /**< Input for SSP0_SCK comes from P2.22 */
+#define LOC_SSP0_SCK_P0_15          ((2))   /**< Input for SSP0_SCK comes from P0_15 */
+#define LOC_SSP0_SSEL_P2_23         ((0))   /**< Input for SSP0_SSEL comes from P2.23 */
+#define LOC_SSP0_SSEL_P1_21         ((1))   /**< Input for SSP0_SSEL comes from P1.21 */
+#define LOC_SSP0_SSEL_P1_28         ((2))   /**< Input for SSP0_SSEL comes from P1.28 */
+#define LOC_SSP0_SSEL_P0_16         ((3))   /**< Input for SSP0_SSEL comes from P0.16 */
+#define LOC_SSP1_MISO_P0_12         ((0))   /**< Input for SSP1_MISO comes from P0.12 */
+#define LOC_SSP1_MISO_P1_18         ((1))   /**< Input for SSP1_MISO comes from P1.18 */
+#define LOC_SSP1_MISO_P4_22         ((2))   /**< Input for SSP1_MISO comes from P4_22 */
+#define LOC_SSP1_MISO_P0_8          ((3))   /**< Input for SSP1_MISO comes from P0.8 */
+#define LOC_SSP1_MOSI_P0_13         ((0))   /**< Input for SSP1_MOSI comes from P0.13 */
+#define LOC_SSP1_MOSI_P1_22         ((1))   /**< Input for SSP1_MOSI comes from P1.22 */
+#define LOC_SSP1_MOSI_P4_23         ((2))   /**< Input for SSP1_MOSI comes from P4.23 */
+#define LOC_SSP1_MOSI_P0_9          ((3))   /**< Input for SSP1_MOSI comes from P0.9 */
+#define LOC_SSP1_SCK_P1_31          ((0))   /**< Input for SSP1_SCK comes from P1.31 */
+#define LOC_SSP1_SCK_P1_19          ((1))   /**< Input for SSP1_SCK comes from P1.19 */
+#define LOC_SSP1_SCK_P4_20          ((2))   /**< Input for SSP1_SCK comes from P4_20 */
+#define LOC_SSP1_SCK_P0_7           ((3))   /**< Input for SSP1_SCK comes from P0_7 */
+#define LOC_SSP1_SSEL_P0_14         ((0))   /**< Input for SSP1_SSEL comes from P0.14 */
+#define LOC_SSP1_SSEL_P1_26         ((1))   /**< Input for SSP1_SSEL comes from P1.26 */
+#define LOC_SSP1_SSEL_P4_21         ((2))   /**< Input for SSP1_SSEL comes from P4.21 */
+#define LOC_SSP1_SSEL_P0_6          ((3))   /**< Input for SSP1_SSEL comes from P0.6 */
+#define LOC_SSP2_MISO_P1_4          ((1))   /**< Input for SSP2_MISO comes from P1.4 */
+#define LOC_SSP2_MOSI_P1_1          ((1))   /**< Input for SSP2_MOSI comes from P1.1 */
+#define LOC_SSP2_SCK_P1_0           ((1))   /**< Input for SSP2_SCK comes from P1.0 */
+#define LOC_SSP2_SSEL_P1_8          ((1))   /**< Input for SSP2_SSEL comes from P1.8 */
+#define LOC_T0_CAP_0_P3_23          ((0))   /**< Input for T0_CAP_0 comes from P3.23 */
+#define LOC_T0_CAP_0_P1_26          ((1))   /**< Input for T0_CAP_0 comes from P1.26 */
+#define LOC_T0_CAP_1_P3_24          ((0))   /**< Input for T0_CAP_1 comes from P3.24 */
+#define LOC_T0_CAP_1_P1_27          ((1))   /**< Input for T0_CAP_1 comes from P1.27 */
+#define LOC_T1_CAP_0_P1_18          ((0))   /**< Input for T1_CAP_0 comes from P1.18 */
+#define LOC_T1_CAP_0_P3_27          ((1))   /**< Input for T1_CAP_0 comes from P3.27 */
+#define LOC_T1_CAP_1_P3_28          ((0))   /**< Input for T1_CAP_1 comes from P3.28 */
+#define LOC_T1_CAP_1_P1_19          ((1))   /**< Input for T1_CAP_1 comes from P1.19 */
+#define LOC_T2_CAP_0_P2_14          ((0))   /**< Input for T2_CAP_0 comes from P2.14 */
+#define LOC_T2_CAP_0_P2_6           ((1))   /**< Input for T2_CAP_0 comes from P2.6 */
+#define LOC_T2_CAP_0_P0_4           ((2))   /**< Input for T2_CAP_0 comes from P0.4 */
+#define LOC_T2_CAP_0_P1_14          ((3))   /**< Input for T2_CAP_0 comes from P1.14 */
+#define LOC_T2_CAP_1_P2_15          ((0))   /**< Input for T2_CAP_1 comes from P2.15 */
+#define LOC_T2_CAP_1_P0_5           ((1))   /**< Input for T2_CAP_1 comes from P0.5 */
+#define LOC_T3_CAP_0_P0_23          ((0))   /**< Input for T3_CAP_0 comes from P0.23 */
+#define LOC_T3_CAP_0_P2_22          ((1))   /**< Input for T3_CAP_0 comes from P2.22 */
+#define LOC_T3_CAP_0_P1_10          ((2))   /**< Input for T3_CAP_0 comes from P1.10 */
+#define LOC_T3_CAP_1_P0_24          ((0))   /**< Input for T3_CAP_1 comes from P0.24 */
+#define LOC_T3_CAP_1_P2_23          ((1))   /**< Input for T3_CAP_1 comes from P2.23 */
+#define LOC_T3_CAP_1_P1_0           ((2))   /**< Input for T3_CAP_1 comes from P1.0 */
+#define LOC_U0_RXD_P0_1             ((0))   /**< Input for U0_RXD comes from P0.1 */
+#define LOC_U0_RXD_P0_3             ((1))   /**< Input for U0_RXD comes from P0.3 */
+#define LOC_U1_CTS_P0_17            ((0))   /**< Input for U1_CTS comes from P0.17 */
+#define LOC_U1_CTS_P2_8             ((1))   /**< Input for U1_CTS comes from P2.8 */
+#define LOC_U1_CTS_P2_2             ((2))   /**< Input for U1_CTS comes from P2.2 */
+#define LOC_U1_CTS_P3_18            ((3))   /**< Input for U1_CTS comes from P3.18 */
+#define LOC_U1_DCD_P0_18            ((0))   /**< Input for U1_DCD comes from P0.18 */
+#define LOC_U1_DCD_P2_3             ((1))   /**< Input for U1_DCD comes from P2.3 */
+#define LOC_U1_DCD_P3_19            ((2))   /**< Input for U1_DCD comes from P3_19 */
+#define LOC_U1_DSR_P0_19            ((0))   /**< Input for U1_DSR comes from P0.19 */
+#define LOC_U1_DSR_P2_4             ((1))   /**< Input for U1_DSR comes from P2.4 */
+#define LOC_U1_DSR_P3_20            ((2))   /**< Input for U1_DSR comes from P0.19 */
+#define LOC_U1_RI_P0_21             ((0))   /**< Input for U1_RI comes from P0.21 */
+#define LOC_U1_RI_P2_6              ((1))   /**< Input for U1_RI comes from P2.6 */
+#define LOC_U1_RI_P3_22             ((2))   /**< Input for U1_RI comes from P3.22 */
+#define LOC_U1_RXD_P0_16            ((0))   /**< Input for U1_RXD comes from P0.16 */
+#define LOC_U1_RXD_P3_17            ((1))   /**< Input for U1_RXD comes from P3.17 */
+#define LOC_U1_RXD_P2_1             ((2))   /**< Input for U1_RXD comes from P2.1 */
+#define LOC_U2_RXD_P0_11            ((0))   /**< Input for U2_RXD comes from P0.11 */
+#define LOC_U2_RXD_P4_23            ((1))   /**< Input for U2_RXD comes from P4.23 */
+#define LOC_U2_RXD_P2_9             ((2))   /**< Input for U2_RXD comes from P2.9 */
+#define LOC_U3_RXD_P0_26            ((0))   /**< Input for U3_RXD comes from P0.26 */
+#define LOC_U3_RXD_P0_1             ((1))   /**< Input for U3_RXD comes from P0.1 */
+#define LOC_U3_RXD_P4_29            ((2))   /**< Input for U3_RXD comes from P4.29 */
+#define LOC_U3_RXD_P0_3             ((3))   /**< Input for U3_RXD comes from P0.3 */
+#define LOC_U4_RXD_P2_9             ((0))   /**< Input for U4_RXD comes from P2.9 */
+#define LOC_U4_RXD_P5_3             ((1))   /**< Input for U4_RXD comes from P5.3 */
+#define LOC_USB_SCL_P0_28           ((0))   /**< Input for USB_SCL comes from P0.28 */
+#define LOC_USB_SCL_P1_28           ((1))   /**< Input for USB_SCL comes from P1.28 */
+#define LOC_USB_SDA_P0_27           ((0))   /**< Input for USB_SDA comes from P0.27 */
+#define LOC_USB_SDA_P1_29           ((1))   /**< Input for USB_SDA comes from P1.29 */
 
 /**
  * @}
@@ -206,32 +206,32 @@
 /** @defgroup PINSEL_Public_Types PINSEL Public Types
  * @{
  */
- 
+
 
 typedef enum
 {
-	PINSEL_BASICMODE_PLAINOUT  = 0,	/**< Plain output */
-	PINSEL_BASICMODE_PULLDOWN,		/**< Pull-down enabled */
-  	PINSEL_BASICMODE_PULLUP,		/**< Pull-up enabled (default) */
-	PINSEL_BASICMODE_REPEATER		/**< Repeater mode */
+    PINSEL_BASICMODE_PLAINOUT  = 0, /**< Plain output */
+    PINSEL_BASICMODE_PULLDOWN,      /**< Pull-down enabled */
+    PINSEL_BASICMODE_PULLUP,        /**< Pull-up enabled (default) */
+    PINSEL_BASICMODE_REPEATER       /**< Repeater mode */
 }PinSel_BasicMode;
 
 typedef enum
 {
-	/** Fast mode (400 kHz clock rate) and standard (100 kHz clock rate) */
-	PINSEL_I2CMODE_FAST_STANDARD  = 0,
-	/** Open drain I/O (not I2C). No glitch filter, 3 mA typical output drive */
-	PINSEL_I2CMODE_OPENDRAINIO,
-	/** Fast Mode Plus I2C. This includes a filter for <50 ns glitches */
-	PINSEL_I2CMODE_FASTMODEPLUS,
-	/** High drive open drain I/O (not I2C). No glitch filter, 20 mA typical output drive */
-	PINSEL_I2CMODE_HIDRIVE_OPENDRAIN
+    /** Fast mode (400 kHz clock rate) and standard (100 kHz clock rate) */
+    PINSEL_I2CMODE_FAST_STANDARD  = 0,
+    /** Open drain I/O (not I2C). No glitch filter, 3 mA typical output drive */
+    PINSEL_I2CMODE_OPENDRAINIO,
+    /** Fast Mode Plus I2C. This includes a filter for <50 ns glitches */
+    PINSEL_I2CMODE_FASTMODEPLUS,
+    /** High drive open drain I/O (not I2C). No glitch filter, 20 mA typical output drive */
+    PINSEL_I2CMODE_HIDRIVE_OPENDRAIN
 }PinSel_I2cMode;
 
 /**
  * @}
  */
- 
+
 
 /* Public Functions ----------------------------------------------------------- */
 /** @defgroup PINSEL_Public_Functions
diff --git a/bsp/lpc178x/drivers/lpc177x_8x_uart.c b/bsp/lpc178x/drivers/lpc177x_8x_uart.c
index 4e0f4e1d7c..7661a32b13 100644
--- a/bsp/lpc178x/drivers/lpc177x_8x_uart.c
+++ b/bsp/lpc178x/drivers/lpc177x_8x_uart.c
@@ -1,13 +1,13 @@
 /**********************************************************************
-* $Id$		lpc177x_8x_uart.c			2011-06-02
+* $Id$      lpc177x_8x_uart.c           2011-06-02
 *//**
-* @file		lpc177x_8x_uart.c
-* @brief	Contains all functions support for UART firmware library
-*			on LPC177x_8x
-* @version	1.0
-* @date		02. June. 2011
-* @author	NXP MCU SW Application Team
-* 
+* @file     lpc177x_8x_uart.c
+* @brief    Contains all functions support for UART firmware library
+*           on LPC177x_8x
+* @version  1.0
+* @date     02. June. 2011
+* @author   NXP MCU SW Application Team
+*
 * Copyright(C) 2011, NXP Semiconductor
 * All rights reserved.
 *
@@ -39,127 +39,127 @@ static Status uart_set_divisors(LPC_UART_TypeDef *UARTx, uint32_t baudrate);
 
 
 /*********************************************************************//**
- * @brief		Determines best dividers to get a target clock rate
- * @param[in]	UARTx	Pointer to selected UART peripheral, should be:
- * 				- LPC_UART0: UART0 peripheral
- * 				- LPC_UART1: UART1 peripheral
- * 				- LPC_UART2: UART2 peripheral
- * 				- LPC_UART3: UART3 peripheral
- * @param[in]	baudrate Desired UART baud rate.
- * @return 		Error status, could be:
- * 				- SUCCESS
- * 				- ERROR
+ * @brief       Determines best dividers to get a target clock rate
+ * @param[in]   UARTx   Pointer to selected UART peripheral, should be:
+ *              - LPC_UART0: UART0 peripheral
+ *              - LPC_UART1: UART1 peripheral
+ *              - LPC_UART2: UART2 peripheral
+ *              - LPC_UART3: UART3 peripheral
+ * @param[in]   baudrate Desired UART baud rate.
+ * @return      Error status, could be:
+ *              - SUCCESS
+ *              - ERROR
  **********************************************************************/
 static Status uart_set_divisors(LPC_UART_TypeDef *UARTx, uint32_t baudrate)
 {
-	Status errorStatus = ERROR;
+    Status errorStatus = ERROR;
 
-	uint32_t uClk;
-	uint32_t d, m, bestd, bestm, tmp;
-	uint64_t best_divisor, divisor;
-	uint32_t current_error, best_error;
-	uint32_t recalcbaud;
+    uint32_t uClk;
+    uint32_t d, m, bestd, bestm, tmp;
+    uint64_t best_divisor, divisor;
+    uint32_t current_error, best_error;
+    uint32_t recalcbaud;
 
-	/* get UART block clock */
-	uClk = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER);
+    /* get UART block clock */
+    uClk = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER);
 
-	/* In the Uart IP block, baud rate is calculated using FDR and DLL-DLM registers
-	* The formula is :
-	* BaudRate= uClk * (mulFracDiv/(mulFracDiv+dividerAddFracDiv) / (16 * (DLL)
-	* It involves floating point calculations. That's the reason the formulae are adjusted with
-	* Multiply and divide method.*/
-	
-	/* The value of mulFracDiv and dividerAddFracDiv should comply to the following expressions:
-	* 0 < mulFracDiv <= 15, 0 <= dividerAddFracDiv <= 15 */
-	best_error = 0xFFFFFFFF; /* Worst case */
-	bestd = 0;
-	bestm = 0;
-	best_divisor = 0;
-	
-	for (m = 1 ; m <= 15 ;m++)
-	{
-		for (d = 0 ; d < m ; d++)
-		{
-			divisor = ((uint64_t)uClk << 28)*m / (baudrate*(m+d));
-			current_error = divisor & 0xFFFFFFFF;
+    /* In the Uart IP block, baud rate is calculated using FDR and DLL-DLM registers
+    * The formula is :
+    * BaudRate= uClk * (mulFracDiv/(mulFracDiv+dividerAddFracDiv) / (16 * (DLL)
+    * It involves floating point calculations. That's the reason the formulae are adjusted with
+    * Multiply and divide method.*/
 
-			tmp = divisor>>32;
+    /* The value of mulFracDiv and dividerAddFracDiv should comply to the following expressions:
+    * 0 < mulFracDiv <= 15, 0 <= dividerAddFracDiv <= 15 */
+    best_error = 0xFFFFFFFF; /* Worst case */
+    bestd = 0;
+    bestm = 0;
+    best_divisor = 0;
 
-			/* Adjust error */
-			if(current_error > ((uint32_t)1<<31))
-			{
-				current_error = -current_error;
-				tmp++;
-			}
+    for (m = 1 ; m <= 15 ;m++)
+    {
+        for (d = 0 ; d < m ; d++)
+        {
+            divisor = ((uint64_t)uClk << 28)*m / (baudrate*(m+d));
+            current_error = divisor & 0xFFFFFFFF;
 
-			/* Out of range */
-			if(tmp < 1 || tmp > 65536)
-				continue;
+            tmp = divisor>>32;
 
-			if( current_error < best_error)
-			{
-				best_error = current_error;
-				best_divisor = tmp;
-				bestd = d;
-				bestm = m;
-				
-				if(best_error == 0) 
-					break;
-			}
-		} /* end of inner for loop */
+            /* Adjust error */
+            if(current_error > ((uint32_t)1<<31))
+            {
+                current_error = -current_error;
+                tmp++;
+            }
 
-		if (best_error == 0)
-			break;
-	} /* end of outer for loop  */
+            /* Out of range */
+            if(tmp < 1 || tmp > 65536)
+                continue;
 
-	/* can not find best match */
-	if(best_divisor == 0) 
-		return ERROR;
+            if( current_error < best_error)
+            {
+                best_error = current_error;
+                best_divisor = tmp;
+                bestd = d;
+                bestm = m;
 
-	recalcbaud = (uClk >> 4) * bestm / (best_divisor * (bestm + bestd));
+                if(best_error == 0)
+                    break;
+            }
+        } /* end of inner for loop */
 
-	/* reuse best_error to evaluate baud error*/
-	if(baudrate > recalcbaud) 
-		best_error = baudrate - recalcbaud;
-	else 
-		best_error = recalcbaud -baudrate;
+        if (best_error == 0)
+            break;
+    } /* end of outer for loop  */
 
-	best_error = best_error * 100 / baudrate;
+    /* can not find best match */
+    if(best_divisor == 0)
+        return ERROR;
 
-	if (best_error < UART_ACCEPTED_BAUDRATE_ERROR)
-	{
-		if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
-		{
-			((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_DLAB_EN;
-			
-			((LPC_UART1_TypeDef *)UARTx)->DLM = UART_LOAD_DLM(best_divisor);
-			
-			((LPC_UART1_TypeDef *)UARTx)->DLL = UART_LOAD_DLL(best_divisor);
-			
-			/* Then reset DLAB bit */
-			((LPC_UART1_TypeDef *)UARTx)->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK;
-			
-			((LPC_UART1_TypeDef *)UARTx)->FDR = (UART_FDR_MULVAL(bestm)
-													| UART_FDR_DIVADDVAL(bestd)) & UART_FDR_BITMASK;
-		}
-		else
-		{
-			UARTx->LCR |= UART_LCR_DLAB_EN;
-			
-			UARTx->DLM = UART_LOAD_DLM(best_divisor);
-			
-			UARTx->DLL = UART_LOAD_DLL(best_divisor);
-			
-			/* Then reset DLAB bit */
-			UARTx->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK;
-			
-			UARTx->FDR = (UART_FDR_MULVAL(bestm) \
-							| UART_FDR_DIVADDVAL(bestd)) & UART_FDR_BITMASK;
-		}
-		errorStatus = SUCCESS;
-	}
+    recalcbaud = (uClk >> 4) * bestm / (best_divisor * (bestm + bestd));
 
-	return errorStatus;
+    /* reuse best_error to evaluate baud error*/
+    if(baudrate > recalcbaud)
+        best_error = baudrate - recalcbaud;
+    else
+        best_error = recalcbaud -baudrate;
+
+    best_error = best_error * 100 / baudrate;
+
+    if (best_error < UART_ACCEPTED_BAUDRATE_ERROR)
+    {
+        if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+        {
+            ((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_DLAB_EN;
+
+            ((LPC_UART1_TypeDef *)UARTx)->DLM = UART_LOAD_DLM(best_divisor);
+
+            ((LPC_UART1_TypeDef *)UARTx)->DLL = UART_LOAD_DLL(best_divisor);
+
+            /* Then reset DLAB bit */
+            ((LPC_UART1_TypeDef *)UARTx)->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK;
+
+            ((LPC_UART1_TypeDef *)UARTx)->FDR = (UART_FDR_MULVAL(bestm)
+                                                    | UART_FDR_DIVADDVAL(bestd)) & UART_FDR_BITMASK;
+        }
+        else
+        {
+            UARTx->LCR |= UART_LCR_DLAB_EN;
+
+            UARTx->DLM = UART_LOAD_DLM(best_divisor);
+
+            UARTx->DLL = UART_LOAD_DLL(best_divisor);
+
+            /* Then reset DLAB bit */
+            UARTx->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK;
+
+            UARTx->FDR = (UART_FDR_MULVAL(bestm) \
+                            | UART_FDR_DIVADDVAL(bestd)) & UART_FDR_BITMASK;
+        }
+        errorStatus = SUCCESS;
+    }
+
+    return errorStatus;
 }
 
 /* End of Private Functions ---------------------------------------------------- */
@@ -171,1192 +171,1192 @@ static Status uart_set_divisors(LPC_UART_TypeDef *UARTx, uint32_t baudrate)
  */
 /* UART Init/DeInit functions -------------------------------------------------*/
 /********************************************************************//**
- * @brief		Initializes the UARTx peripheral according to the specified
+ * @brief       Initializes the UARTx peripheral according to the specified
  *               parameters in the UART_ConfigStruct.
- * @param[in]	UARTx	UART peripheral selected, should be:
- *   			- LPC_UART0: UART0 peripheral
- * 				- LPC_UART1: UART1 peripheral
- * 				- LPC_UART2: UART2 peripheral
- * 				- LPC_UART3: UART3 peripheral
- *				- LPC_UART4: UART4 peripheral
- * @param[in]	UART_ConfigStruct Pointer to a UART_CFG_Type structure
+ * @param[in]   UARTx   UART peripheral selected, should be:
+ *              - LPC_UART0: UART0 peripheral
+ *              - LPC_UART1: UART1 peripheral
+ *              - LPC_UART2: UART2 peripheral
+ *              - LPC_UART3: UART3 peripheral
+ *              - LPC_UART4: UART4 peripheral
+ * @param[in]   UART_ConfigStruct Pointer to a UART_CFG_Type structure
 *                    that contains the configuration information for the
 *                    specified UART peripheral.
- * @return 		None
+ * @return      None
  *********************************************************************/
 void UART_Init(LPC_UART_TypeDef *UARTx, UART_CFG_Type *UART_ConfigStruct)
 {
-	uint32_t tmp;
+    uint32_t tmp;
 
-	if(UARTx == LPC_UART0)
-	{
-		/* Set up clock and power for UART module */
-		CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART0, ENABLE);
-	}
-	if(((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
-	{
-		/* Set up clock and power for UART module */
-		CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART1, ENABLE);
-	}
-	if(UARTx == LPC_UART2)
-	{
-		/* Set up clock and power for UART module */
-		CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART2, ENABLE);
-	}
-	if(UARTx == LPC_UART3)
-	{
-		/* Set up clock and power for UART module */
-		CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART3, ENABLE);
-	}
+    if(UARTx == LPC_UART0)
+    {
+        /* Set up clock and power for UART module */
+        CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART0, ENABLE);
+    }
+    if(((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+    {
+        /* Set up clock and power for UART module */
+        CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART1, ENABLE);
+    }
+    if(UARTx == LPC_UART2)
+    {
+        /* Set up clock and power for UART module */
+        CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART2, ENABLE);
+    }
+    if(UARTx == LPC_UART3)
+    {
+        /* Set up clock and power for UART module */
+        CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART3, ENABLE);
+    }
 
-	/* FIFOs are empty */
-	UARTx->FCR = ( UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS);
+    /* FIFOs are empty */
+    UARTx->FCR = ( UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS);
 
-	// Disable FIFO
-	UARTx->FCR = 0;
+    // Disable FIFO
+    UARTx->FCR = 0;
 
-	// Dummy reading
-	while (UARTx->LSR & UART_LSR_RDR)
-	{
-		tmp = UARTx->RBR;
-	}
+    // Dummy reading
+    while (UARTx->LSR & UART_LSR_RDR)
+    {
+        tmp = UARTx->RBR;
+    }
 
-	UARTx->TER = UART_TER_TXEN;
+    UARTx->TER = UART_TER_TXEN;
 
-	// Wait for current transmit complete
-	while (!(UARTx->LSR & UART_LSR_THRE));
+    // Wait for current transmit complete
+    while (!(UARTx->LSR & UART_LSR_THRE));
 
-	// Disable Tx
-	UARTx->TER = 0;
+    // Disable Tx
+    UARTx->TER = 0;
 
-	// Disable interrupt
-	UARTx->IER = 0;
+    // Disable interrupt
+    UARTx->IER = 0;
 
-	// Set LCR to default state
-	UARTx->LCR = 0;
+    // Set LCR to default state
+    UARTx->LCR = 0;
 
-	// Set ACR to default state
-	UARTx->ACR = 0;
+    // Set ACR to default state
+    UARTx->ACR = 0;
 
-	// Set RS485 control to default state
-	UARTx->RS485CTRL = 0;
+    // Set RS485 control to default state
+    UARTx->RS485CTRL = 0;
 
-	// Set RS485 delay timer to default state
-	UARTx->RS485DLY = 0;
+    // Set RS485 delay timer to default state
+    UARTx->RS485DLY = 0;
 
-	// Set RS485 addr match to default state
-	UARTx->ADRMATCH = 0;
+    // Set RS485 addr match to default state
+    UARTx->ADRMATCH = 0;
 
-	// Dummy reading
-	tmp = UARTx->LSR;
+    // Dummy reading
+    tmp = UARTx->LSR;
 
-	if(((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
-	{
-		// Set Modem Control to default state
-		((LPC_UART1_TypeDef *)UARTx)->MCR = 0;
+    if(((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+    {
+        // Set Modem Control to default state
+        ((LPC_UART1_TypeDef *)UARTx)->MCR = 0;
 
-		//Dummy Reading to Clear Status
-		tmp = ((LPC_UART1_TypeDef *)UARTx)->MSR;
-	}
-	else
-	{
-		// Set IrDA to default state for all UART other than UART1
-		UARTx->ICR = 0;
-	}
+        //Dummy Reading to Clear Status
+        tmp = ((LPC_UART1_TypeDef *)UARTx)->MSR;
+    }
+    else
+    {
+        // Set IrDA to default state for all UART other than UART1
+        UARTx->ICR = 0;
+    }
 
-	// Set Line Control register ----------------------------
+    // Set Line Control register ----------------------------
 
-	uart_set_divisors(UARTx, (UART_ConfigStruct->Baud_rate));
+    uart_set_divisors(UARTx, (UART_ConfigStruct->Baud_rate));
 
-	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
-	{
-		tmp = (((LPC_UART1_TypeDef *)UARTx)->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) \
-													& UART_LCR_BITMASK;
-	}
-	else
-	{
-		tmp = (UARTx->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) & UART_LCR_BITMASK;
-	}
+    if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+    {
+        tmp = (((LPC_UART1_TypeDef *)UARTx)->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) \
+                                                    & UART_LCR_BITMASK;
+    }
+    else
+    {
+        tmp = (UARTx->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) & UART_LCR_BITMASK;
+    }
 
-	switch (UART_ConfigStruct->Databits)
-	{
-		case UART_DATABIT_5:
-			tmp |= UART_LCR_WLEN5;
-			break;
+    switch (UART_ConfigStruct->Databits)
+    {
+        case UART_DATABIT_5:
+            tmp |= UART_LCR_WLEN5;
+            break;
 
-		case UART_DATABIT_6:
-			tmp |= UART_LCR_WLEN6;
-			break;
+        case UART_DATABIT_6:
+            tmp |= UART_LCR_WLEN6;
+            break;
 
-		case UART_DATABIT_7:
-			tmp |= UART_LCR_WLEN7;
-			break;
+        case UART_DATABIT_7:
+            tmp |= UART_LCR_WLEN7;
+            break;
 
-		case UART_DATABIT_8:
+        case UART_DATABIT_8:
 
-		default:
-			tmp |= UART_LCR_WLEN8;
-			break;
-	}
+        default:
+            tmp |= UART_LCR_WLEN8;
+            break;
+    }
 
-	if (UART_ConfigStruct->Parity == UART_PARITY_NONE)
-	{
-		// Do nothing...
-	}
-	else
-	{
-		tmp |= UART_LCR_PARITY_EN;
-		switch (UART_ConfigStruct->Parity)
-		{
-			case UART_PARITY_ODD:
-				tmp |= UART_LCR_PARITY_ODD;
-				break;
+    if (UART_ConfigStruct->Parity == UART_PARITY_NONE)
+    {
+        // Do nothing...
+    }
+    else
+    {
+        tmp |= UART_LCR_PARITY_EN;
+        switch (UART_ConfigStruct->Parity)
+        {
+            case UART_PARITY_ODD:
+                tmp |= UART_LCR_PARITY_ODD;
+                break;
 
-			case UART_PARITY_EVEN:
-				tmp |= UART_LCR_PARITY_EVEN;
-				break;
+            case UART_PARITY_EVEN:
+                tmp |= UART_LCR_PARITY_EVEN;
+                break;
 
-			case UART_PARITY_SP_1:
-				tmp |= UART_LCR_PARITY_F_1;
-				break;
+            case UART_PARITY_SP_1:
+                tmp |= UART_LCR_PARITY_F_1;
+                break;
 
-			case UART_PARITY_SP_0:
-				tmp |= UART_LCR_PARITY_F_0;
-				break;
+            case UART_PARITY_SP_0:
+                tmp |= UART_LCR_PARITY_F_0;
+                break;
 
-			default:
-				break;
-		}
-	}
+            default:
+                break;
+        }
+    }
 
-	switch (UART_ConfigStruct->Stopbits)
-	{
-		case UART_STOPBIT_2:
-			tmp |= UART_LCR_STOPBIT_SEL;
-			break;
+    switch (UART_ConfigStruct->Stopbits)
+    {
+        case UART_STOPBIT_2:
+            tmp |= UART_LCR_STOPBIT_SEL;
+            break;
 
-		case UART_STOPBIT_1:
+        case UART_STOPBIT_1:
 
-		default:
-			// Do no thing
-			break;
-	}
+        default:
+            // Do no thing
+            break;
+    }
 
 
-	// Write back to LCR, configure FIFO and Disable Tx
-	if (((LPC_UART1_TypeDef *)UARTx) ==  LPC_UART1)
-	{
-		((LPC_UART1_TypeDef *)UARTx)->LCR = (uint8_t)(tmp & UART_LCR_BITMASK);
-	}
-	else
-	{
-		UARTx->LCR = (uint8_t)(tmp & UART_LCR_BITMASK);
-	}
+    // Write back to LCR, configure FIFO and Disable Tx
+    if (((LPC_UART1_TypeDef *)UARTx) ==  LPC_UART1)
+    {
+        ((LPC_UART1_TypeDef *)UARTx)->LCR = (uint8_t)(tmp & UART_LCR_BITMASK);
+    }
+    else
+    {
+        UARTx->LCR = (uint8_t)(tmp & UART_LCR_BITMASK);
+    }
 }
 
 /*********************************************************************//**
- * @brief		De-initializes the UARTx peripheral registers to their
+ * @brief       De-initializes the UARTx peripheral registers to their
  *                  default reset values.
- * @param[in]	UARTx	UART peripheral selected, should be:
- *   			- LPC_UART0: UART0 peripheral
- * 				- LPC_UART1: UART1 peripheral
- * 				- LPC_UART2: UART2 peripheral
- * 				- LPC_UART3: UART3 peripheral
- * @return 		None
+ * @param[in]   UARTx   UART peripheral selected, should be:
+ *              - LPC_UART0: UART0 peripheral
+ *              - LPC_UART1: UART1 peripheral
+ *              - LPC_UART2: UART2 peripheral
+ *              - LPC_UART3: UART3 peripheral
+ * @return      None
  **********************************************************************/
 void UART_DeInit(LPC_UART_TypeDef* UARTx)
 {
-	UART_TxCmd(UARTx, DISABLE);
+    UART_TxCmd(UARTx, DISABLE);
 
-	if (UARTx == LPC_UART0)
-	{
-		/* Set up clock and power for UART module */
-		CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART0, DISABLE);
-	}
+    if (UARTx == LPC_UART0)
+    {
+        /* Set up clock and power for UART module */
+        CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART0, DISABLE);
+    }
 
-	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
-	{
-		/* Set up clock and power for UART module */
-		CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART1, DISABLE);
-	}
+    if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+    {
+        /* Set up clock and power for UART module */
+        CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART1, DISABLE);
+    }
 
-	if (UARTx == LPC_UART2)
-	{
-		/* Set up clock and power for UART module */
-		CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART2, DISABLE);
-	}
+    if (UARTx == LPC_UART2)
+    {
+        /* Set up clock and power for UART module */
+        CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART2, DISABLE);
+    }
 
-	if (UARTx == LPC_UART3)
-	{
-		/* Set up clock and power for UART module */
-		CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART3, DISABLE);
-	}
+    if (UARTx == LPC_UART3)
+    {
+        /* Set up clock and power for UART module */
+        CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART3, DISABLE);
+    }
 }
 
 /*****************************************************************************//**
-* @brief		Fills each UART_InitStruct member with its default value:
-* 				- 9600 bps
-* 				- 8-bit data
-* 				- 1 Stopbit
-* 				- None Parity
-* @param[in]	UART_InitStruct Pointer to a UART_CFG_Type structure
+* @brief        Fills each UART_InitStruct member with its default value:
+*               - 9600 bps
+*               - 8-bit data
+*               - 1 Stopbit
+*               - None Parity
+* @param[in]    UART_InitStruct Pointer to a UART_CFG_Type structure
 *                    which will be initialized.
-* @return		None
+* @return       None
 *******************************************************************************/
 void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct)
 {
-	UART_InitStruct->Baud_rate = 9600;
+    UART_InitStruct->Baud_rate = 9600;
 
-	UART_InitStruct->Databits = UART_DATABIT_8;
+    UART_InitStruct->Databits = UART_DATABIT_8;
 
-	UART_InitStruct->Parity = UART_PARITY_NONE;
+    UART_InitStruct->Parity = UART_PARITY_NONE;
 
-	UART_InitStruct->Stopbits = UART_STOPBIT_1;
+    UART_InitStruct->Stopbits = UART_STOPBIT_1;
 }
 
 /* UART Send/Recieve functions -------------------------------------------------*/
 /*********************************************************************//**
- * @brief		Transmit a single data through UART peripheral
- * @param[in]	UARTx	UART peripheral selected, should be:
- *   			- LPC_UART0: UART0 peripheral
- * 				- LPC_UART1: UART1 peripheral
- * 				- LPC_UART2: UART2 peripheral
- * 				- LPC_UART3: UART3 peripheral
- * @param[in]	Data	Data to transmit (must be 8-bit long)
- * @return 		None
+ * @brief       Transmit a single data through UART peripheral
+ * @param[in]   UARTx   UART peripheral selected, should be:
+ *              - LPC_UART0: UART0 peripheral
+ *              - LPC_UART1: UART1 peripheral
+ *              - LPC_UART2: UART2 peripheral
+ *              - LPC_UART3: UART3 peripheral
+ * @param[in]   Data    Data to transmit (must be 8-bit long)
+ * @return      None
  **********************************************************************/
 void UART_SendByte(LPC_UART_TypeDef* UARTx, uint8_t Data)
 {
-	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
-	{
-		((LPC_UART1_TypeDef *)UARTx)->THR = Data & UART_THR_MASKBIT;
-	}
-	else
-	{
-		UARTx->THR = Data & UART_THR_MASKBIT;
-	}
+    if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+    {
+        ((LPC_UART1_TypeDef *)UARTx)->THR = Data & UART_THR_MASKBIT;
+    }
+    else
+    {
+        UARTx->THR = Data & UART_THR_MASKBIT;
+    }
 
 }
 
 
 /*********************************************************************//**
- * @brief		Receive a single data from UART peripheral
- * @param[in]	UARTx	UART peripheral selected, should be:
- *  			- LPC_UART0: UART0 peripheral
- * 				- LPC_UART1: UART1 peripheral
- * 				- LPC_UART2: UART2 peripheral
- * 				- LPC_UART3: UART3 peripheral
- * @return 		Data received
+ * @brief       Receive a single data from UART peripheral
+ * @param[in]   UARTx   UART peripheral selected, should be:
+ *              - LPC_UART0: UART0 peripheral
+ *              - LPC_UART1: UART1 peripheral
+ *              - LPC_UART2: UART2 peripheral
+ *              - LPC_UART3: UART3 peripheral
+ * @return      Data received
  **********************************************************************/
 uint8_t UART_ReceiveByte(LPC_UART_TypeDef* UARTx)
 {
-	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
-	{
-		return (((LPC_UART1_TypeDef *)UARTx)->RBR & UART_RBR_MASKBIT);
-	}
-	else
-	{
-		return (UARTx->RBR & UART_RBR_MASKBIT);
-	}
+    if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+    {
+        return (((LPC_UART1_TypeDef *)UARTx)->RBR & UART_RBR_MASKBIT);
+    }
+    else
+    {
+        return (UARTx->RBR & UART_RBR_MASKBIT);
+    }
 }
 
 /*********************************************************************//**
- * @brief		Send a block of data via UART peripheral
- * @param[in]	UARTx	Selected UART peripheral used to send data, should be:
- *   			- LPC_UART0: UART0 peripheral
- * 				- LPC_UART1: UART1 peripheral
- * 				- LPC_UART2: UART2 peripheral
- * 				- LPC_UART3: UART3 peripheral
- * @param[in]	txbuf 	Pointer to Transmit buffer
- * @param[in]	buflen 	Length of Transmit buffer
- * @param[in] 	flag 	Flag used in  UART transfer, should be
- * 						NONE_BLOCKING or BLOCKING
- * @return 		Number of bytes sent.
+ * @brief       Send a block of data via UART peripheral
+ * @param[in]   UARTx   Selected UART peripheral used to send data, should be:
+ *              - LPC_UART0: UART0 peripheral
+ *              - LPC_UART1: UART1 peripheral
+ *              - LPC_UART2: UART2 peripheral
+ *              - LPC_UART3: UART3 peripheral
+ * @param[in]   txbuf   Pointer to Transmit buffer
+ * @param[in]   buflen  Length of Transmit buffer
+ * @param[in]   flag    Flag used in  UART transfer, should be
+ *                      NONE_BLOCKING or BLOCKING
+ * @return      Number of bytes sent.
  *
  * Note: when using UART in BLOCKING mode, a time-out condition is used
  * via defined symbol UART_BLOCKING_TIMEOUT.
  **********************************************************************/
 uint32_t UART_Send(LPC_UART_TypeDef *UARTx, uint8_t *txbuf,
-							uint32_t buflen, TRANSFER_BLOCK_Type flag)
+                            uint32_t buflen, TRANSFER_BLOCK_Type flag)
 {
-	uint32_t bToSend, bSent, timeOut, fifo_cnt;
-	uint8_t *pChar = txbuf;
+    uint32_t bToSend, bSent, timeOut, fifo_cnt;
+    uint8_t *pChar = txbuf;
 
-	bToSend = buflen;
+    bToSend = buflen;
 
-	// blocking mode
-	if (flag == BLOCKING)
-	{
-		bSent = 0;
-		while (bToSend)
-		{
-			timeOut = UART_BLOCKING_TIMEOUT;
+    // blocking mode
+    if (flag == BLOCKING)
+    {
+        bSent = 0;
+        while (bToSend)
+        {
+            timeOut = UART_BLOCKING_TIMEOUT;
 
-			// Wait for THR empty with timeout
-			while (!(UARTx->LSR & UART_LSR_THRE))
-			{
-				if (timeOut == 0)
-					break;
+            // Wait for THR empty with timeout
+            while (!(UARTx->LSR & UART_LSR_THRE))
+            {
+                if (timeOut == 0)
+                    break;
 
-				timeOut--;
-			}
+                timeOut--;
+            }
 
-			// Time out!
-			if(timeOut == 0)
-				break;
+            // Time out!
+            if(timeOut == 0)
+                break;
 
-			fifo_cnt = UART_TX_FIFO_SIZE;
+            fifo_cnt = UART_TX_FIFO_SIZE;
 
-			while (fifo_cnt && bToSend)
-			{
-				UART_SendByte(UARTx, (*pChar++));
+            while (fifo_cnt && bToSend)
+            {
+                UART_SendByte(UARTx, (*pChar++));
 
-				fifo_cnt--;
+                fifo_cnt--;
 
-				bToSend--;
+                bToSend--;
 
-				bSent++;
-			}
-		}
-	}
+                bSent++;
+            }
+        }
+    }
 
-	// None blocking mode
-	else
-	{
-		bSent = 0;
-		while (bToSend)
-		{
-			if (bToSend == 0)
-				break;
+    // None blocking mode
+    else
+    {
+        bSent = 0;
+        while (bToSend)
+        {
+            if (bToSend == 0)
+                break;
 
-			if (!(UARTx->LSR & UART_LSR_THRE))
-			{
-				break;
-			}
+            if (!(UARTx->LSR & UART_LSR_THRE))
+            {
+                break;
+            }
 
-			fifo_cnt = UART_TX_FIFO_SIZE;
+            fifo_cnt = UART_TX_FIFO_SIZE;
 
-			while (fifo_cnt && bToSend)
-			{
-				UART_SendByte(UARTx, (*pChar++));
+            while (fifo_cnt && bToSend)
+            {
+                UART_SendByte(UARTx, (*pChar++));
 
-				bToSend--;
+                bToSend--;
 
-				fifo_cnt--;
+                fifo_cnt--;
 
-				bSent++;
-			}
-		}
-	}
+                bSent++;
+            }
+        }
+    }
 
-	return bSent;
+    return bSent;
 }
 
 /*********************************************************************//**
- * @brief		Receive a block of data via UART peripheral
- * @param[in]	UARTx	Selected UART peripheral used to send data,
- * 				should be:
- *   			- LPC_UART0: UART0 peripheral
- * 				- LPC_UART1: UART1 peripheral
- * 				- LPC_UART2: UART2 peripheral
- * 				- LPC_UART3: UART3 peripheral
- * @param[out]	rxbuf 	Pointer to Received buffer
- * @param[in]	buflen 	Length of Received buffer
- * @param[in] 	flag 	Flag mode, should be NONE_BLOCKING or BLOCKING
+ * @brief       Receive a block of data via UART peripheral
+ * @param[in]   UARTx   Selected UART peripheral used to send data,
+ *              should be:
+ *              - LPC_UART0: UART0 peripheral
+ *              - LPC_UART1: UART1 peripheral
+ *              - LPC_UART2: UART2 peripheral
+ *              - LPC_UART3: UART3 peripheral
+ * @param[out]  rxbuf   Pointer to Received buffer
+ * @param[in]   buflen  Length of Received buffer
+ * @param[in]   flag    Flag mode, should be NONE_BLOCKING or BLOCKING
 
- * @return 		Number of bytes received
+ * @return      Number of bytes received
  *
  * Note: when using UART in BLOCKING mode, a time-out condition is used
  * via defined symbol UART_BLOCKING_TIMEOUT.
  **********************************************************************/
 uint32_t UART_Receive(LPC_UART_TypeDef *UARTx, uint8_t *rxbuf,
-								uint32_t buflen, TRANSFER_BLOCK_Type flag)
+                                uint32_t buflen, TRANSFER_BLOCK_Type flag)
 {
-	uint32_t bToRecv, bRecv, timeOut;
-	uint8_t *pChar = rxbuf;
+    uint32_t bToRecv, bRecv, timeOut;
+    uint8_t *pChar = rxbuf;
 
-	bToRecv = buflen;
+    bToRecv = buflen;
 
-	// Blocking mode
-	if (flag == BLOCKING)
-	{
-		bRecv = 0;
-		while (bToRecv)
-		{
-			timeOut = UART_BLOCKING_TIMEOUT;
-			while (!(UARTx->LSR & UART_LSR_RDR))
-			{
-				if (timeOut == 0)
-					break;
+    // Blocking mode
+    if (flag == BLOCKING)
+    {
+        bRecv = 0;
+        while (bToRecv)
+        {
+            timeOut = UART_BLOCKING_TIMEOUT;
+            while (!(UARTx->LSR & UART_LSR_RDR))
+            {
+                if (timeOut == 0)
+                    break;
 
-				timeOut--;
-			}
+                timeOut--;
+            }
 
-			// Time out!
-			if(timeOut == 0)
-				break;
+            // Time out!
+            if(timeOut == 0)
+                break;
 
-			// Get data from the buffer
-			(*pChar++) = UART_ReceiveByte(UARTx);
+            // Get data from the buffer
+            (*pChar++) = UART_ReceiveByte(UARTx);
 
-			bToRecv--;
+            bToRecv--;
 
-			bRecv++;
-		}
-	}
-	// None blocking mode
-	else
-	{
-		bRecv = 0;
-		while (bToRecv)
-		{
-			if (!(UARTx->LSR & UART_LSR_RDR))
-			{
-				break;
-			}
-			else
-			{
-				(*pChar++) = UART_ReceiveByte(UARTx);
+            bRecv++;
+        }
+    }
+    // None blocking mode
+    else
+    {
+        bRecv = 0;
+        while (bToRecv)
+        {
+            if (!(UARTx->LSR & UART_LSR_RDR))
+            {
+                break;
+            }
+            else
+            {
+                (*pChar++) = UART_ReceiveByte(UARTx);
 
-				bRecv++;
+                bRecv++;
 
-				bToRecv--;
-			}
-		}
-	}
+                bToRecv--;
+            }
+        }
+    }
 
-	return bRecv;
+    return bRecv;
 }
 
 /*********************************************************************//**
- * @brief		Force BREAK character on UART line, output pin UARTx TXD is
-				forced to logic 0.
- * @param[in]	UARTx	UART peripheral selected, should be:
- *  			- LPC_UART0: UART0 peripheral
- * 				- LPC_UART1: UART1 peripheral
- * 				- LPC_UART2: UART2 peripheral
- * 				- LPC_UART3: UART3 peripheral
- * @return 		None
+ * @brief       Force BREAK character on UART line, output pin UARTx TXD is
+                forced to logic 0.
+ * @param[in]   UARTx   UART peripheral selected, should be:
+ *              - LPC_UART0: UART0 peripheral
+ *              - LPC_UART1: UART1 peripheral
+ *              - LPC_UART2: UART2 peripheral
+ *              - LPC_UART3: UART3 peripheral
+ * @return      None
  **********************************************************************/
 void UART_ForceBreak(LPC_UART_TypeDef* UARTx)
 {
-	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
-	{
-		((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_BREAK_EN;
-	}
-	else
-	{
-		UARTx->LCR |= UART_LCR_BREAK_EN;
-	}
+    if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+    {
+        ((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_BREAK_EN;
+    }
+    else
+    {
+        UARTx->LCR |= UART_LCR_BREAK_EN;
+    }
 }
 
 
 /********************************************************************//**
- * @brief 		Enable or disable specified UART interrupt.
- * @param[in]	UARTx	UART peripheral selected, should be
- *  			- LPC_UART0: UART0 peripheral
- * 				- LPC_UART1: UART1 peripheral
- * 				- LPC_UART2: UART2 peripheral
- * 				- LPC_UART3: UART3 peripheral
- * @param[in]	UARTIntCfg	Specifies the interrupt flag,
- * 				should be one of the following:
-				- UART_INTCFG_RBR 	:  RBR Interrupt enable
-				- UART_INTCFG_THRE 	:  THR Interrupt enable
-				- UART_INTCFG_RLS 	:  RX line status interrupt enable
-				- UART1_INTCFG_MS	:  Modem status interrupt enable (UART1 only)
-				- UART1_INTCFG_CTS	:  CTS1 signal transition interrupt enable (UART1 only)
-				- UART_INTCFG_ABEO 	:  Enables the end of auto-baud interrupt
-				- UART_INTCFG_ABTO 	:  Enables the auto-baud time-out interrupt
- * @param[in]	NewState New state of specified UART interrupt type,
- * 				should be:
- * 				- ENALBE: Enable this UART interrupt type.
-* 				- DISALBE: Disable this UART interrupt type.
- * @return 		None
+ * @brief       Enable or disable specified UART interrupt.
+ * @param[in]   UARTx   UART peripheral selected, should be
+ *              - LPC_UART0: UART0 peripheral
+ *              - LPC_UART1: UART1 peripheral
+ *              - LPC_UART2: UART2 peripheral
+ *              - LPC_UART3: UART3 peripheral
+ * @param[in]   UARTIntCfg  Specifies the interrupt flag,
+ *              should be one of the following:
+                - UART_INTCFG_RBR   :  RBR Interrupt enable
+                - UART_INTCFG_THRE  :  THR Interrupt enable
+                - UART_INTCFG_RLS   :  RX line status interrupt enable
+                - UART1_INTCFG_MS   :  Modem status interrupt enable (UART1 only)
+                - UART1_INTCFG_CTS  :  CTS1 signal transition interrupt enable (UART1 only)
+                - UART_INTCFG_ABEO  :  Enables the end of auto-baud interrupt
+                - UART_INTCFG_ABTO  :  Enables the auto-baud time-out interrupt
+ * @param[in]   NewState New state of specified UART interrupt type,
+ *              should be:
+ *              - ENALBE: Enable this UART interrupt type.
+*               - DISALBE: Disable this UART interrupt type.
+ * @return      None
  *********************************************************************/
 void UART_IntConfig(LPC_UART_TypeDef *UARTx, UART_INT_Type UARTIntCfg, FunctionalState NewState)
 {
-	uint32_t tmp;
+    uint32_t tmp;
 
-	switch(UARTIntCfg)
-	{
-		case UART_INTCFG_RBR:
-			tmp = UART_IER_RBRINT_EN;
-			break;
+    switch(UARTIntCfg)
+    {
+        case UART_INTCFG_RBR:
+            tmp = UART_IER_RBRINT_EN;
+            break;
 
-		case UART_INTCFG_THRE:
-			tmp = UART_IER_THREINT_EN;
-			break;
+        case UART_INTCFG_THRE:
+            tmp = UART_IER_THREINT_EN;
+            break;
 
-		case UART_INTCFG_RLS:
-			tmp = UART_IER_RLSINT_EN;
-			break;
+        case UART_INTCFG_RLS:
+            tmp = UART_IER_RLSINT_EN;
+            break;
 
-		case UART1_INTCFG_MS:
-			tmp = UART1_IER_MSINT_EN;
-			break;
+        case UART1_INTCFG_MS:
+            tmp = UART1_IER_MSINT_EN;
+            break;
 
-		case UART1_INTCFG_CTS:
-			tmp = UART1_IER_CTSINT_EN;
-			break;
+        case UART1_INTCFG_CTS:
+            tmp = UART1_IER_CTSINT_EN;
+            break;
 
-		case UART_INTCFG_ABEO:
-			tmp = UART_IER_ABEOINT_EN;
-			break;
+        case UART_INTCFG_ABEO:
+            tmp = UART_IER_ABEOINT_EN;
+            break;
 
-		case UART_INTCFG_ABTO:
-			tmp = UART_IER_ABTOINT_EN;
-			break;
-	}
+        case UART_INTCFG_ABTO:
+            tmp = UART_IER_ABTOINT_EN;
+            break;
+    }
 
-	if (NewState == ENABLE)
-	{
-		if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1)
-		{
-			((LPC_UART1_TypeDef *)UARTx)->IER |= tmp;
-		}
-		else
-		{
-			UARTx->IER |= tmp;
-		}
-	}
-	else
-	{
-		if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1)
-		{
-			((LPC_UART1_TypeDef *)UARTx)->IER &= (~tmp) & UART1_IER_BITMASK;
-		}
-		else
-		{
-			UARTx->IER &= (~tmp) & UART_IER_BITMASK;
-		}
-	}
+    if (NewState == ENABLE)
+    {
+        if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1)
+        {
+            ((LPC_UART1_TypeDef *)UARTx)->IER |= tmp;
+        }
+        else
+        {
+            UARTx->IER |= tmp;
+        }
+    }
+    else
+    {
+        if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1)
+        {
+            ((LPC_UART1_TypeDef *)UARTx)->IER &= (~tmp) & UART1_IER_BITMASK;
+        }
+        else
+        {
+            UARTx->IER &= (~tmp) & UART_IER_BITMASK;
+        }
+    }
 }
 
 
 /********************************************************************//**
- * @brief 		Get current value of Line Status register in UART peripheral.
- * @param[in]	UARTx	UART peripheral selected, should be:
- *  			- LPC_UART0: UART0 peripheral
- * 				- LPC_UART1: UART1 peripheral
- * 				- LPC_UART2: UART2 peripheral
- * 				- LPC_UART3: UART3 peripheral
- * @return		Current value of Line Status register in UART peripheral.
- * Note:	The return value of this function must be ANDed with each member in
- * 			UART_LS_Type enumeration to determine current flag status
- * 			corresponding to each Line status type. Because some flags in
- * 			Line Status register will be cleared after reading, the next reading
- * 			Line Status register could not be correct. So this function used to
- * 			read Line status register in one time only, then the return value
- * 			used to check all flags.
+ * @brief       Get current value of Line Status register in UART peripheral.
+ * @param[in]   UARTx   UART peripheral selected, should be:
+ *              - LPC_UART0: UART0 peripheral
+ *              - LPC_UART1: UART1 peripheral
+ *              - LPC_UART2: UART2 peripheral
+ *              - LPC_UART3: UART3 peripheral
+ * @return      Current value of Line Status register in UART peripheral.
+ * Note:    The return value of this function must be ANDed with each member in
+ *          UART_LS_Type enumeration to determine current flag status
+ *          corresponding to each Line status type. Because some flags in
+ *          Line Status register will be cleared after reading, the next reading
+ *          Line Status register could not be correct. So this function used to
+ *          read Line status register in one time only, then the return value
+ *          used to check all flags.
  *********************************************************************/
 uint8_t UART_GetLineStatus(LPC_UART_TypeDef* UARTx)
 {
-	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
-	{
-		return ((((LPC_UART1_TypeDef *)LPC_UART1)->LSR) & UART_LSR_BITMASK);
-	}
-	else
-	{
-		return ((UARTx->LSR) & UART_LSR_BITMASK);
-	}
+    if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+    {
+        return ((((LPC_UART1_TypeDef *)LPC_UART1)->LSR) & UART_LSR_BITMASK);
+    }
+    else
+    {
+        return ((UARTx->LSR) & UART_LSR_BITMASK);
+    }
 }
 
 /********************************************************************//**
- * @brief 		Get Interrupt Identification value
- * @param[in]	UARTx	UART peripheral selected, should be:
- *  			- LPC_UART0: UART0 peripheral
- * 				- LPC_UART1: UART1 peripheral
- * 				- LPC_UART2: UART2 peripheral
- * 				- LPC_UART3: UART3 peripheral
- * @return		Current value of UART UIIR register in UART peripheral.
+ * @brief       Get Interrupt Identification value
+ * @param[in]   UARTx   UART peripheral selected, should be:
+ *              - LPC_UART0: UART0 peripheral
+ *              - LPC_UART1: UART1 peripheral
+ *              - LPC_UART2: UART2 peripheral
+ *              - LPC_UART3: UART3 peripheral
+ * @return      Current value of UART UIIR register in UART peripheral.
  *********************************************************************/
 uint32_t UART_GetIntId(LPC_UART_TypeDef* UARTx)
 {
-	return (UARTx->IIR & 0x03CF);
+    return (UARTx->IIR & 0x03CF);
 }
 
 /*********************************************************************//**
- * @brief		Check whether if UART is busy or not
- * @param[in]	UARTx	UART peripheral selected, should be:
- *  			- LPC_UART0: UART0 peripheral
- * 				- LPC_UART1: UART1 peripheral
- * 				- LPC_UART2: UART2 peripheral
- * 				- LPC_UART3: UART3 peripheral
- * @return		RESET if UART is not busy, otherwise return SET.
+ * @brief       Check whether if UART is busy or not
+ * @param[in]   UARTx   UART peripheral selected, should be:
+ *              - LPC_UART0: UART0 peripheral
+ *              - LPC_UART1: UART1 peripheral
+ *              - LPC_UART2: UART2 peripheral
+ *              - LPC_UART3: UART3 peripheral
+ * @return      RESET if UART is not busy, otherwise return SET.
  **********************************************************************/
 FlagStatus UART_CheckBusy(LPC_UART_TypeDef *UARTx)
 {
-	if (UARTx->LSR & UART_LSR_TEMT)
-	{
-		return RESET;
-	}
-	else
-	{
-		return SET;
-	}
+    if (UARTx->LSR & UART_LSR_TEMT)
+    {
+        return RESET;
+    }
+    else
+    {
+        return SET;
+    }
 }
 
 
 /*********************************************************************//**
- * @brief		Configure FIFO function on selected UART peripheral
- * @param[in]	UARTx	UART peripheral selected, should be:
- *  			- LPC_UART0: UART0 peripheral
- * 				- LPC_UART1: UART1 peripheral
- * 				- LPC_UART2: UART2 peripheral
- * 				- LPC_UART3: UART3 peripheral
- * @param[in]	FIFOCfg	Pointer to a UART_FIFO_CFG_Type Structure that
- * 						contains specified information about FIFO configuration
- * @return 		none
+ * @brief       Configure FIFO function on selected UART peripheral
+ * @param[in]   UARTx   UART peripheral selected, should be:
+ *              - LPC_UART0: UART0 peripheral
+ *              - LPC_UART1: UART1 peripheral
+ *              - LPC_UART2: UART2 peripheral
+ *              - LPC_UART3: UART3 peripheral
+ * @param[in]   FIFOCfg Pointer to a UART_FIFO_CFG_Type Structure that
+ *                      contains specified information about FIFO configuration
+ * @return      none
  **********************************************************************/
 void UART_FIFOConfig(LPC_UART_TypeDef *UARTx, UART_FIFO_CFG_Type *FIFOCfg)
 {
-	uint8_t tmp = 0;
+    uint8_t tmp = 0;
 
-	tmp |= UART_FCR_FIFO_EN;
+    tmp |= UART_FCR_FIFO_EN;
 
-	switch (FIFOCfg->FIFO_Level)
-	{
-		case UART_FIFO_TRGLEV0:
-			tmp |= UART_FCR_TRG_LEV0;
-			break;
+    switch (FIFOCfg->FIFO_Level)
+    {
+        case UART_FIFO_TRGLEV0:
+            tmp |= UART_FCR_TRG_LEV0;
+            break;
 
-		case UART_FIFO_TRGLEV1:
-			tmp |= UART_FCR_TRG_LEV1;
-			break;
+        case UART_FIFO_TRGLEV1:
+            tmp |= UART_FCR_TRG_LEV1;
+            break;
 
-		case UART_FIFO_TRGLEV2:
-			tmp |= UART_FCR_TRG_LEV2;
-			break;
+        case UART_FIFO_TRGLEV2:
+            tmp |= UART_FCR_TRG_LEV2;
+            break;
 
-		case UART_FIFO_TRGLEV3:
+        case UART_FIFO_TRGLEV3:
 
-		default:
-			tmp |= UART_FCR_TRG_LEV3;
-			break;
-	}
+        default:
+            tmp |= UART_FCR_TRG_LEV3;
+            break;
+    }
 
-	if (FIFOCfg->FIFO_ResetTxBuf == ENABLE)
-	{
-		tmp |= UART_FCR_TX_RS;
-	}
+    if (FIFOCfg->FIFO_ResetTxBuf == ENABLE)
+    {
+        tmp |= UART_FCR_TX_RS;
+    }
 
-	if (FIFOCfg->FIFO_ResetRxBuf == ENABLE)
-	{
-		tmp |= UART_FCR_RX_RS;
-	}
+    if (FIFOCfg->FIFO_ResetRxBuf == ENABLE)
+    {
+        tmp |= UART_FCR_RX_RS;
+    }
 
-	if (FIFOCfg->FIFO_DMAMode == ENABLE)
-	{
-		tmp |= UART_FCR_DMAMODE_SEL;
-	}
+    if (FIFOCfg->FIFO_DMAMode == ENABLE)
+    {
+        tmp |= UART_FCR_DMAMODE_SEL;
+    }
 
 
-	//write to FIFO control register
-	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
-	{
-		((LPC_UART1_TypeDef *)UARTx)->FCR = tmp & UART_FCR_BITMASK;
-	}
-	else
-	{
-		UARTx->FCR = tmp & UART_FCR_BITMASK;
-	}
+    //write to FIFO control register
+    if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+    {
+        ((LPC_UART1_TypeDef *)UARTx)->FCR = tmp & UART_FCR_BITMASK;
+    }
+    else
+    {
+        UARTx->FCR = tmp & UART_FCR_BITMASK;
+    }
 }
 
 /*****************************************************************************//**
-* @brief		Fills each UART_FIFOInitStruct member with its default value:
-* 				- FIFO_DMAMode = DISABLE
-* 				- FIFO_Level = UART_FIFO_TRGLEV0
-* 				- FIFO_ResetRxBuf = ENABLE
-* 				- FIFO_ResetTxBuf = ENABLE
-* 				- FIFO_State = ENABLE
+* @brief        Fills each UART_FIFOInitStruct member with its default value:
+*               - FIFO_DMAMode = DISABLE
+*               - FIFO_Level = UART_FIFO_TRGLEV0
+*               - FIFO_ResetRxBuf = ENABLE
+*               - FIFO_ResetTxBuf = ENABLE
+*               - FIFO_State = ENABLE
 
-* @param[in]	UART_FIFOInitStruct Pointer to a UART_FIFO_CFG_Type structure
+* @param[in]    UART_FIFOInitStruct Pointer to a UART_FIFO_CFG_Type structure
 *                    which will be initialized.
-* @return		None
+* @return       None
 *******************************************************************************/
 void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct)
 {
-	UART_FIFOInitStruct->FIFO_DMAMode = DISABLE;
+    UART_FIFOInitStruct->FIFO_DMAMode = DISABLE;
 
-	UART_FIFOInitStruct->FIFO_Level = UART_FIFO_TRGLEV0;
+    UART_FIFOInitStruct->FIFO_Level = UART_FIFO_TRGLEV0;
 
-	UART_FIFOInitStruct->FIFO_ResetRxBuf = ENABLE;
+    UART_FIFOInitStruct->FIFO_ResetRxBuf = ENABLE;
 
-	UART_FIFOInitStruct->FIFO_ResetTxBuf = ENABLE;
+    UART_FIFOInitStruct->FIFO_ResetTxBuf = ENABLE;
 }
 
 
 /*********************************************************************//**
- * @brief		Start/Stop Auto Baudrate activity
- * @param[in]	UARTx	UART peripheral selected, should be
- *   			- LPC_UART0: UART0 peripheral
- * 				- LPC_UART1: UART1 peripheral
- * 				- LPC_UART2: UART2 peripheral
- * 				- LPC_UART3: UART3 peripheral
- * @param[in]	ABConfigStruct	A pointer to UART_AB_CFG_Type structure that
- * 								contains specified information about UART
- * 								auto baudrate configuration
- * @param[in]	NewState New State of Auto baudrate activity, should be:
- * 				- ENABLE: Start this activity
- *				- DISABLE: Stop this activity
- * Note:		Auto-baudrate mode enable bit will be cleared once this mode
- * 				completed.
- * @return 		none
+ * @brief       Start/Stop Auto Baudrate activity
+ * @param[in]   UARTx   UART peripheral selected, should be
+ *              - LPC_UART0: UART0 peripheral
+ *              - LPC_UART1: UART1 peripheral
+ *              - LPC_UART2: UART2 peripheral
+ *              - LPC_UART3: UART3 peripheral
+ * @param[in]   ABConfigStruct  A pointer to UART_AB_CFG_Type structure that
+ *                              contains specified information about UART
+ *                              auto baudrate configuration
+ * @param[in]   NewState New State of Auto baudrate activity, should be:
+ *              - ENABLE: Start this activity
+ *              - DISABLE: Stop this activity
+ * Note:        Auto-baudrate mode enable bit will be cleared once this mode
+ *              completed.
+ * @return      none
  **********************************************************************/
 void UART_ABCmd(LPC_UART_TypeDef *UARTx, UART_AB_CFG_Type *ABConfigStruct,
-							FunctionalState NewState)
+                            FunctionalState NewState)
 {
-	uint32_t tmp;
+    uint32_t tmp;
 
-	tmp = 0;
-	if (NewState == ENABLE)
-	{
-		if (ABConfigStruct->ABMode == UART_AUTOBAUD_MODE1)
-		{
-			tmp |= UART_ACR_MODE;
-		}
-		if (ABConfigStruct->AutoRestart == ENABLE)
-		{
-			tmp |= UART_ACR_AUTO_RESTART;
-		}
-	}
+    tmp = 0;
+    if (NewState == ENABLE)
+    {
+        if (ABConfigStruct->ABMode == UART_AUTOBAUD_MODE1)
+        {
+            tmp |= UART_ACR_MODE;
+        }
+        if (ABConfigStruct->AutoRestart == ENABLE)
+        {
+            tmp |= UART_ACR_AUTO_RESTART;
+        }
+    }
 
-	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
-	{
-		if (NewState == ENABLE)
-		{
-			// Clear DLL and DLM value
-			((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_DLAB_EN;
+    if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+    {
+        if (NewState == ENABLE)
+        {
+            // Clear DLL and DLM value
+            ((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_DLAB_EN;
 
-			((LPC_UART1_TypeDef *)UARTx)->DLL = 0;
+            ((LPC_UART1_TypeDef *)UARTx)->DLL = 0;
 
-			((LPC_UART1_TypeDef *)UARTx)->DLM = 0;
+            ((LPC_UART1_TypeDef *)UARTx)->DLM = 0;
 
-			((LPC_UART1_TypeDef *)UARTx)->LCR &= ~UART_LCR_DLAB_EN;
+            ((LPC_UART1_TypeDef *)UARTx)->LCR &= ~UART_LCR_DLAB_EN;
 
-			// FDR value must be reset to default value
-			((LPC_UART1_TypeDef *)UARTx)->FDR = 0x10;
+            // FDR value must be reset to default value
+            ((LPC_UART1_TypeDef *)UARTx)->FDR = 0x10;
 
-			((LPC_UART1_TypeDef *)UARTx)->ACR = UART_ACR_START | tmp;
-		}
-		else
-		{
-			((LPC_UART1_TypeDef *)UARTx)->ACR = 0;
-		}
-	}
-	else
-	{
-		if (NewState == ENABLE)
-		{
-			// Clear DLL and DLM value
-			UARTx->LCR |= UART_LCR_DLAB_EN;
+            ((LPC_UART1_TypeDef *)UARTx)->ACR = UART_ACR_START | tmp;
+        }
+        else
+        {
+            ((LPC_UART1_TypeDef *)UARTx)->ACR = 0;
+        }
+    }
+    else
+    {
+        if (NewState == ENABLE)
+        {
+            // Clear DLL and DLM value
+            UARTx->LCR |= UART_LCR_DLAB_EN;
 
-			UARTx->DLL = 0;
+            UARTx->DLL = 0;
 
-			UARTx->DLM = 0;
+            UARTx->DLM = 0;
 
-			UARTx->LCR &= ~UART_LCR_DLAB_EN;
+            UARTx->LCR &= ~UART_LCR_DLAB_EN;
 
-			// FDR value must be reset to default value
-			UARTx->FDR = 0x10;
+            // FDR value must be reset to default value
+            UARTx->FDR = 0x10;
 
-			UARTx->ACR = UART_ACR_START | tmp;
-		}
-		else
-		{
-			UARTx->ACR = 0;
-		}
-	}
+            UARTx->ACR = UART_ACR_START | tmp;
+        }
+        else
+        {
+            UARTx->ACR = 0;
+        }
+    }
 }
 
 /*********************************************************************//**
- * @brief		Clear Autobaud Interrupt Pending
- * @param[in]	UARTx	UART peripheral selected, should be
- *   			- LPC_UART0: UART0 peripheral
- * 				- LPC_UART1: UART1 peripheral
- * 				- LPC_UART2: UART2 peripheral
- * 				- LPC_UART3: UART3 peripheral
- * @param[in]	ABIntType	type of auto-baud interrupt, should be:
- * 				- UART_AUTOBAUD_INTSTAT_ABEO: End of Auto-baud interrupt
- * 				- UART_AUTOBAUD_INTSTAT_ABTO: Auto-baud time out interrupt
- * @return 		none
+ * @brief       Clear Autobaud Interrupt Pending
+ * @param[in]   UARTx   UART peripheral selected, should be
+ *              - LPC_UART0: UART0 peripheral
+ *              - LPC_UART1: UART1 peripheral
+ *              - LPC_UART2: UART2 peripheral
+ *              - LPC_UART3: UART3 peripheral
+ * @param[in]   ABIntType   type of auto-baud interrupt, should be:
+ *              - UART_AUTOBAUD_INTSTAT_ABEO: End of Auto-baud interrupt
+ *              - UART_AUTOBAUD_INTSTAT_ABTO: Auto-baud time out interrupt
+ * @return      none
  **********************************************************************/
 void UART_ABClearIntPending(LPC_UART_TypeDef *UARTx, UART_ABEO_Type ABIntType)
 {
-	if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
-	{
-		UARTx->ACR |= ABIntType;
-	}
-	else
-		UARTx->ACR |= ABIntType;
+    if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+    {
+        UARTx->ACR |= ABIntType;
+    }
+    else
+        UARTx->ACR |= ABIntType;
 }
 
 /*********************************************************************//**
- * @brief		Enable/Disable transmission on UART TxD pin
- * @param[in]	UARTx	UART peripheral selected, should be:
- *   			- LPC_UART0: UART0 peripheral
- * 				- LPC_UART1: UART1 peripheral
- * 				- LPC_UART2: UART2 peripheral
- * 				- LPC_UART3: UART3 peripheral
- * @param[in]	NewState New State of Tx transmission function, should be:
- * 				- ENABLE: Enable this function
-				- DISABLE: Disable this function
+ * @brief       Enable/Disable transmission on UART TxD pin
+ * @param[in]   UARTx   UART peripheral selected, should be:
+ *              - LPC_UART0: UART0 peripheral
+ *              - LPC_UART1: UART1 peripheral
+ *              - LPC_UART2: UART2 peripheral
+ *              - LPC_UART3: UART3 peripheral
+ * @param[in]   NewState New State of Tx transmission function, should be:
+ *              - ENABLE: Enable this function
+                - DISABLE: Disable this function
  * @return none
  **********************************************************************/
 void UART_TxCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState)
 {
-	if (NewState == ENABLE)
-	{
-		if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
-		{
-			((LPC_UART1_TypeDef *)UARTx)->TER |= UART_TER_TXEN;
-		}
-		else
-		{
-			UARTx->TER |= UART_TER_TXEN;
-		}
-	}
-	else
-	{
-		if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
-		{
-			((LPC_UART1_TypeDef *)UARTx)->TER &= (~UART_TER_TXEN) & UART_TER_BITMASK;
-		}
-		else
-		{
-			UARTx->TER &= (~UART_TER_TXEN) & UART_TER_BITMASK;
-		}
-	}
+    if (NewState == ENABLE)
+    {
+        if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+        {
+            ((LPC_UART1_TypeDef *)UARTx)->TER |= UART_TER_TXEN;
+        }
+        else
+        {
+            UARTx->TER |= UART_TER_TXEN;
+        }
+    }
+    else
+    {
+        if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+        {
+            ((LPC_UART1_TypeDef *)UARTx)->TER &= (~UART_TER_TXEN) & UART_TER_BITMASK;
+        }
+        else
+        {
+            UARTx->TER &= (~UART_TER_TXEN) & UART_TER_BITMASK;
+        }
+    }
 }
 
 /* UART IrDA functions ---------------------------------------------------*/
 /*********************************************************************//**
- * @brief		Enable or disable inverting serial input function of IrDA
- * 				on UART peripheral.
- * @param[in]	UARTx UART peripheral selected, should be LPC_UART3 (only)
- * @param[in]	NewState New state of inverting serial input, should be:
- * 				- ENABLE: Enable this function.
- * 				- DISABLE: Disable this function.
+ * @brief       Enable or disable inverting serial input function of IrDA
+ *              on UART peripheral.
+ * @param[in]   UARTx UART peripheral selected, should be LPC_UART3 (only)
+ * @param[in]   NewState New state of inverting serial input, should be:
+ *              - ENABLE: Enable this function.
+ *              - DISABLE: Disable this function.
  * @return none
  **********************************************************************/
 void UART_IrDAInvtInputCmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState)
 {
-	if (NewState == ENABLE)
-	{
-		UARTx->ICR |= UART_ICR_IRDAINV;
-	}
-	else if (NewState == DISABLE)
-	{
-		UARTx->ICR &= (~UART_ICR_IRDAINV) & UART_ICR_BITMASK;
-	}
+    if (NewState == ENABLE)
+    {
+        UARTx->ICR |= UART_ICR_IRDAINV;
+    }
+    else if (NewState == DISABLE)
+    {
+        UARTx->ICR &= (~UART_ICR_IRDAINV) & UART_ICR_BITMASK;
+    }
 }
 
 
 /*********************************************************************//**
- * @brief		Enable or disable IrDA function on UART peripheral.
- * @param[in]	UARTx UART peripheral selected, should be LPC_UART3 (only)
- * @param[in]	NewState New state of IrDA function, should be:
- * 				- ENABLE: Enable this function.
- * 				- DISABLE: Disable this function.
+ * @brief       Enable or disable IrDA function on UART peripheral.
+ * @param[in]   UARTx UART peripheral selected, should be LPC_UART3 (only)
+ * @param[in]   NewState New state of IrDA function, should be:
+ *              - ENABLE: Enable this function.
+ *              - DISABLE: Disable this function.
  * @return none
  **********************************************************************/
 void UART_IrDACmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState)
 {
-	if (NewState == ENABLE)
-	{
-		UARTx->ICR |= UART_ICR_IRDAEN;
-	}
-	else
-	{
-		UARTx->ICR &= (~UART_ICR_IRDAEN) & UART_ICR_BITMASK;
-	}
+    if (NewState == ENABLE)
+    {
+        UARTx->ICR |= UART_ICR_IRDAEN;
+    }
+    else
+    {
+        UARTx->ICR &= (~UART_ICR_IRDAEN) & UART_ICR_BITMASK;
+    }
 }
 
 
 /*********************************************************************//**
- * @brief		Configure Pulse divider for IrDA function on UART peripheral.
- * @param[in]	UARTx UART peripheral selected, should be LPC_UART3 (only)
- * @param[in]	PulseDiv Pulse Divider value from Peripheral clock,
- * 				should be one of the following:
-				- UART_IrDA_PULSEDIV2 	: Pulse width = 2 * Tpclk
-				- UART_IrDA_PULSEDIV4 	: Pulse width = 4 * Tpclk
-				- UART_IrDA_PULSEDIV8 	: Pulse width = 8 * Tpclk
-				- UART_IrDA_PULSEDIV16 	: Pulse width = 16 * Tpclk
-				- UART_IrDA_PULSEDIV32 	: Pulse width = 32 * Tpclk
-				- UART_IrDA_PULSEDIV64 	: Pulse width = 64 * Tpclk
-				- UART_IrDA_PULSEDIV128 : Pulse width = 128 * Tpclk
-				- UART_IrDA_PULSEDIV256 : Pulse width = 256 * Tpclk
+ * @brief       Configure Pulse divider for IrDA function on UART peripheral.
+ * @param[in]   UARTx UART peripheral selected, should be LPC_UART3 (only)
+ * @param[in]   PulseDiv Pulse Divider value from Peripheral clock,
+ *              should be one of the following:
+                - UART_IrDA_PULSEDIV2   : Pulse width = 2 * Tpclk
+                - UART_IrDA_PULSEDIV4   : Pulse width = 4 * Tpclk
+                - UART_IrDA_PULSEDIV8   : Pulse width = 8 * Tpclk
+                - UART_IrDA_PULSEDIV16  : Pulse width = 16 * Tpclk
+                - UART_IrDA_PULSEDIV32  : Pulse width = 32 * Tpclk
+                - UART_IrDA_PULSEDIV64  : Pulse width = 64 * Tpclk
+                - UART_IrDA_PULSEDIV128 : Pulse width = 128 * Tpclk
+                - UART_IrDA_PULSEDIV256 : Pulse width = 256 * Tpclk
 
  * @return none
  **********************************************************************/
 void UART_IrDAPulseDivConfig(LPC_UART_TypeDef *UARTx, UART_IrDA_PULSE_Type PulseDiv)
 {
-	uint32_t tmp, tmp1;
+    uint32_t tmp, tmp1;
 
-	tmp1 = UART_ICR_PULSEDIV(PulseDiv);
+    tmp1 = UART_ICR_PULSEDIV(PulseDiv);
 
-	tmp = UARTx->ICR & (~ UART_ICR_PULSEDIV(7));
+    tmp = UARTx->ICR & (~ UART_ICR_PULSEDIV(7));
 
-	tmp |= tmp1 | UART_ICR_FIXPULSE_EN;
+    tmp |= tmp1 | UART_ICR_FIXPULSE_EN;
 
-	UARTx->ICR = tmp & UART_ICR_BITMASK;
+    UARTx->ICR = tmp & UART_ICR_BITMASK;
 }
 
 /* UART1 FullModem function ---------------------------------------------*/
 
 /*********************************************************************//**
- * @brief		Force pin DTR/RTS corresponding to given state (Full modem mode)
- * @param[in]	UARTx	LPC_UART1 (only)
- * @param[in]	Pin	Pin that NewState will be applied to, should be:
- * 				- UART1_MODEM_PIN_DTR: DTR pin.
- * 				- UART1_MODEM_PIN_RTS: RTS pin.
- * @param[in]	NewState New State of DTR/RTS pin, should be:
- * 				- INACTIVE: Force the pin to inactive signal.
-				- ACTIVE: Force the pin to active signal.
+ * @brief       Force pin DTR/RTS corresponding to given state (Full modem mode)
+ * @param[in]   UARTx   LPC_UART1 (only)
+ * @param[in]   Pin Pin that NewState will be applied to, should be:
+ *              - UART1_MODEM_PIN_DTR: DTR pin.
+ *              - UART1_MODEM_PIN_RTS: RTS pin.
+ * @param[in]   NewState New State of DTR/RTS pin, should be:
+ *              - INACTIVE: Force the pin to inactive signal.
+                - ACTIVE: Force the pin to active signal.
  * @return none
  **********************************************************************/
 void UART_FullModemForcePinState(LPC_UART1_TypeDef *UARTx,
-													UART_MODEM_PIN_Type Pin,
-													UART1_SignalState NewState)
+                                                    UART_MODEM_PIN_Type Pin,
+                                                    UART1_SignalState NewState)
 {
-	uint8_t tmp = 0;
+    uint8_t tmp = 0;
 
-	switch (Pin)
-	{
-		case UART1_MODEM_PIN_DTR:
-			tmp = UART1_MCR_DTR_CTRL;
-			break;
+    switch (Pin)
+    {
+        case UART1_MODEM_PIN_DTR:
+            tmp = UART1_MCR_DTR_CTRL;
+            break;
 
-		case UART1_MODEM_PIN_RTS:
-			tmp = UART1_MCR_RTS_CTRL;
-			break;
+        case UART1_MODEM_PIN_RTS:
+            tmp = UART1_MCR_RTS_CTRL;
+            break;
 
-		default:
-			break;
-	}
+        default:
+            break;
+    }
 
-	if (NewState == ACTIVE)
-	{
-		UARTx->MCR |= tmp;
-	}
-	else
-	{
-		UARTx->MCR &= (~tmp) & UART1_MCR_BITMASK;
-	}
+    if (NewState == ACTIVE)
+    {
+        UARTx->MCR |= tmp;
+    }
+    else
+    {
+        UARTx->MCR &= (~tmp) & UART1_MCR_BITMASK;
+    }
 }
 
 
 /*********************************************************************//**
- * @brief		Configure Full Modem mode for UART peripheral
- * @param[in]	UARTx	LPC_UART1 (only)
- * @param[in]	Mode Full Modem mode, should be:
- * 				- UART1_MODEM_MODE_LOOPBACK: Loop back mode.
- * 				- UART1_MODEM_MODE_AUTO_RTS: Auto-RTS mode.
- * 				- UART1_MODEM_MODE_AUTO_CTS: Auto-CTS mode.
- * @param[in]	NewState New State of this mode, should be:
- * 				- ENABLE: Enable this mode.
-				- DISABLE: Disable this mode.
+ * @brief       Configure Full Modem mode for UART peripheral
+ * @param[in]   UARTx   LPC_UART1 (only)
+ * @param[in]   Mode Full Modem mode, should be:
+ *              - UART1_MODEM_MODE_LOOPBACK: Loop back mode.
+ *              - UART1_MODEM_MODE_AUTO_RTS: Auto-RTS mode.
+ *              - UART1_MODEM_MODE_AUTO_CTS: Auto-CTS mode.
+ * @param[in]   NewState New State of this mode, should be:
+ *              - ENABLE: Enable this mode.
+                - DISABLE: Disable this mode.
  * @return none
  **********************************************************************/
 void UART_FullModemConfigMode(LPC_UART1_TypeDef *UARTx, UART_MODEM_MODE_Type Mode,
-											FunctionalState NewState)
+                                            FunctionalState NewState)
 {
-	uint8_t tmp;
+    uint8_t tmp;
 
-	switch(Mode)
-	{
-		case UART1_MODEM_MODE_LOOPBACK:
-			tmp = UART1_MCR_LOOPB_EN;
-			break;
+    switch(Mode)
+    {
+        case UART1_MODEM_MODE_LOOPBACK:
+            tmp = UART1_MCR_LOOPB_EN;
+            break;
 
-		case UART1_MODEM_MODE_AUTO_RTS:
-			tmp = UART1_MCR_AUTO_RTS_EN;
-			break;
+        case UART1_MODEM_MODE_AUTO_RTS:
+            tmp = UART1_MCR_AUTO_RTS_EN;
+            break;
 
-		case UART1_MODEM_MODE_AUTO_CTS:
-			tmp = UART1_MCR_AUTO_CTS_EN;
-			break;
+        case UART1_MODEM_MODE_AUTO_CTS:
+            tmp = UART1_MCR_AUTO_CTS_EN;
+            break;
 
-		default:
-			break;
-	}
+        default:
+            break;
+    }
 
-	if (NewState == ENABLE)
-	{
-		UARTx->MCR |= tmp;
-	}
-	else
-	{
-		UARTx->MCR &= (~tmp) & UART1_MCR_BITMASK;
-	}
+    if (NewState == ENABLE)
+    {
+        UARTx->MCR |= tmp;
+    }
+    else
+    {
+        UARTx->MCR &= (~tmp) & UART1_MCR_BITMASK;
+    }
 }
 
 
 /*********************************************************************//**
- * @brief		Get current status of modem status register
- * @param[in]	UARTx	LPC_UART1 (only)
- * @return 		Current value of modem status register
- * Note:	The return value of this function must be ANDed with each member
- * 			UART_MODEM_STAT_type enumeration to determine current flag status
- * 			corresponding to each modem flag status. Because some flags in
- * 			modem status register will be cleared after reading, the next reading
- * 			modem register could not be correct. So this function used to
- * 			read modem status register in one time only, then the return value
- * 			used to check all flags.
+ * @brief       Get current status of modem status register
+ * @param[in]   UARTx   LPC_UART1 (only)
+ * @return      Current value of modem status register
+ * Note:    The return value of this function must be ANDed with each member
+ *          UART_MODEM_STAT_type enumeration to determine current flag status
+ *          corresponding to each modem flag status. Because some flags in
+ *          modem status register will be cleared after reading, the next reading
+ *          modem register could not be correct. So this function used to
+ *          read modem status register in one time only, then the return value
+ *          used to check all flags.
  **********************************************************************/
 uint8_t UART_FullModemGetStatus(LPC_UART1_TypeDef *UARTx)
 {
-	return ((UARTx->MSR) & UART1_MSR_BITMASK);
+    return ((UARTx->MSR) & UART1_MSR_BITMASK);
 }
 
 
 /* UART RS485 functions --------------------------------------------------------------*/
 
 /*********************************************************************//**
- * @brief		Configure UART peripheral in RS485 mode according to the specified
+ * @brief       Configure UART peripheral in RS485 mode according to the specified
 *               parameters in the RS485ConfigStruct.
- * @param[in]	UARTx	LPC_UART1 (only)
- * @param[in]	RS485ConfigStruct Pointer to a UART1_RS485_CTRLCFG_Type structure
+ * @param[in]   UARTx   LPC_UART1 (only)
+ * @param[in]   RS485ConfigStruct Pointer to a UART1_RS485_CTRLCFG_Type structure
 *                    that contains the configuration information for specified UART
 *                    in RS485 mode.
- * @return		None
+ * @return      None
  **********************************************************************/
 void UART_RS485Config(LPC_UART_TypeDef *UARTx, UART1_RS485_CTRLCFG_Type *RS485ConfigStruct)
 {
-	uint32_t tmp;
+    uint32_t tmp;
 
-	tmp = 0;
+    tmp = 0;
 
-	// If Auto Direction Control is enabled -  This function is used in Master mode
-	if (RS485ConfigStruct->AutoDirCtrl_State == ENABLE)
-	{
-		tmp |= UART1_RS485CTRL_DCTRL_EN;
+    // If Auto Direction Control is enabled -  This function is used in Master mode
+    if (RS485ConfigStruct->AutoDirCtrl_State == ENABLE)
+    {
+        tmp |= UART1_RS485CTRL_DCTRL_EN;
 
-		// Set polar
-		if (RS485ConfigStruct->DirCtrlPol_Level == SET)
-		{
-			tmp |= UART1_RS485CTRL_OINV_1;
-		}
+        // Set polar
+        if (RS485ConfigStruct->DirCtrlPol_Level == SET)
+        {
+            tmp |= UART1_RS485CTRL_OINV_1;
+        }
 
-		// Set pin according to. This condition is only with UART1. The others are used
-		// OE pin as default for control the direction of RS485 buffer IC
-		if ((RS485ConfigStruct->DirCtrlPin == UART1_RS485_DIRCTRL_DTR)
-								&& ((LPC_UART1_TypeDef *)UARTx == LPC_UART1))
-		{
-			tmp |= UART1_RS485CTRL_SEL_DTR;
-		}
+        // Set pin according to. This condition is only with UART1. The others are used
+        // OE pin as default for control the direction of RS485 buffer IC
+        if ((RS485ConfigStruct->DirCtrlPin == UART1_RS485_DIRCTRL_DTR)
+                                && ((LPC_UART1_TypeDef *)UARTx == LPC_UART1))
+        {
+            tmp |= UART1_RS485CTRL_SEL_DTR;
+        }
 
-		// Fill delay time
-		UARTx->RS485DLY = RS485ConfigStruct->DelayValue & UART1_RS485DLY_BITMASK;
-	}
+        // Fill delay time
+        UARTx->RS485DLY = RS485ConfigStruct->DelayValue & UART1_RS485DLY_BITMASK;
+    }
 
-	// MultiDrop mode is enable
-	if (RS485ConfigStruct->NormalMultiDropMode_State == ENABLE)
-	{
-		tmp |= UART1_RS485CTRL_NMM_EN;
-	}
+    // MultiDrop mode is enable
+    if (RS485ConfigStruct->NormalMultiDropMode_State == ENABLE)
+    {
+        tmp |= UART1_RS485CTRL_NMM_EN;
+    }
 
-	// Auto Address Detect function
-	if (RS485ConfigStruct->AutoAddrDetect_State == ENABLE)
-	{
-		tmp |= UART1_RS485CTRL_AADEN;
+    // Auto Address Detect function
+    if (RS485ConfigStruct->AutoAddrDetect_State == ENABLE)
+    {
+        tmp |= UART1_RS485CTRL_AADEN;
 
-		// Fill Match Address
-		UARTx->ADRMATCH = RS485ConfigStruct->MatchAddrValue & UART1_RS485ADRMATCH_BITMASK;
-	}
+        // Fill Match Address
+        UARTx->ADRMATCH = RS485ConfigStruct->MatchAddrValue & UART1_RS485ADRMATCH_BITMASK;
+    }
 
-	// Receiver is disable
-	if (RS485ConfigStruct->Rx_State == DISABLE)
-	{
-		tmp |= UART1_RS485CTRL_RX_DIS;
-	}
+    // Receiver is disable
+    if (RS485ConfigStruct->Rx_State == DISABLE)
+    {
+        tmp |= UART1_RS485CTRL_RX_DIS;
+    }
 
-	// write back to RS485 control register
-	UARTx->RS485CTRL = tmp & UART1_RS485CTRL_BITMASK;
+    // write back to RS485 control register
+    UARTx->RS485CTRL = tmp & UART1_RS485CTRL_BITMASK;
 
-	// Enable Parity function and leave parity in stick '0' parity as default
-	UARTx->LCR |= (UART_LCR_PARITY_F_0 | UART_LCR_PARITY_EN);
+    // Enable Parity function and leave parity in stick '0' parity as default
+    UARTx->LCR |= (UART_LCR_PARITY_F_0 | UART_LCR_PARITY_EN);
 }
 
 /*********************************************************************//**
- * @brief		Enable/Disable receiver in RS485 module in UART1
- * @param[in]	UARTx	LPC_UART1 (only)
- * @param[in]	NewState	New State of command, should be:
- * 							- ENABLE: Enable this function.
- * 							- DISABLE: Disable this function.
- * @return		None
+ * @brief       Enable/Disable receiver in RS485 module in UART1
+ * @param[in]   UARTx   LPC_UART1 (only)
+ * @param[in]   NewState    New State of command, should be:
+ *                          - ENABLE: Enable this function.
+ *                          - DISABLE: Disable this function.
+ * @return      None
  **********************************************************************/
 void UART_RS485ReceiverCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState)
 {
-	if (NewState == ENABLE)
-	{
-		UARTx->RS485CTRL &= ~UART1_RS485CTRL_RX_DIS;
-	}
-	else
-	{
-		UARTx->RS485CTRL |= UART1_RS485CTRL_RX_DIS;
-	}
+    if (NewState == ENABLE)
+    {
+        UARTx->RS485CTRL &= ~UART1_RS485CTRL_RX_DIS;
+    }
+    else
+    {
+        UARTx->RS485CTRL |= UART1_RS485CTRL_RX_DIS;
+    }
 }
 
 /*********************************************************************//**
- * @brief		Send data on RS485 bus with specified parity stick value (9-bit mode).
- * @param[in]	UARTx	LPC_UART1 (only)
- * @param[in]	pDatFrm 	Pointer to data frame.
- * @param[in]	size		Size of data.
- * @param[in]	ParityStick	Parity Stick value, should be 0 or 1.
- * @return		None
+ * @brief       Send data on RS485 bus with specified parity stick value (9-bit mode).
+ * @param[in]   UARTx   LPC_UART1 (only)
+ * @param[in]   pDatFrm     Pointer to data frame.
+ * @param[in]   size        Size of data.
+ * @param[in]   ParityStick Parity Stick value, should be 0 or 1.
+ * @return      None
  **********************************************************************/
 uint32_t UART_RS485Send(LPC_UART_TypeDef *UARTx, uint8_t *pDatFrm,
-											uint32_t size, uint8_t ParityStick)
+                                            uint32_t size, uint8_t ParityStick)
 {
-	uint8_t tmp, save;
-	uint32_t cnt;
+    uint8_t tmp, save;
+    uint32_t cnt;
 
-	if (ParityStick)
-	{
-		save = tmp = UARTx->LCR & UART_LCR_BITMASK;
+    if (ParityStick)
+    {
+        save = tmp = UARTx->LCR & UART_LCR_BITMASK;
 
-		tmp &= ~(UART_LCR_PARITY_EVEN);
+        tmp &= ~(UART_LCR_PARITY_EVEN);
 
-		UARTx->LCR = tmp;
+        UARTx->LCR = tmp;
 
-		cnt = UART_Send((LPC_UART_TypeDef *)UARTx, pDatFrm, size, BLOCKING);
+        cnt = UART_Send((LPC_UART_TypeDef *)UARTx, pDatFrm, size, BLOCKING);
 
-		while (!(UARTx->LSR & UART_LSR_TEMT));
+        while (!(UARTx->LSR & UART_LSR_TEMT));
 
-		UARTx->LCR = save;
-	}
-	else
-	{
-		cnt = UART_Send((LPC_UART_TypeDef *)UARTx, pDatFrm, size, BLOCKING);
+        UARTx->LCR = save;
+    }
+    else
+    {
+        cnt = UART_Send((LPC_UART_TypeDef *)UARTx, pDatFrm, size, BLOCKING);
 
-		while (!(UARTx->LSR & UART_LSR_TEMT));
-	}
+        while (!(UARTx->LSR & UART_LSR_TEMT));
+    }
 
-	return cnt;
+    return cnt;
 }
 
 /*********************************************************************//**
- * @brief		Send Slave address frames on RS485 bus.
- * @param[in]	UARTx	LPC_UART1 (only)
- * @param[in]	SlvAddr Slave Address.
- * @return		None
+ * @brief       Send Slave address frames on RS485 bus.
+ * @param[in]   UARTx   LPC_UART1 (only)
+ * @param[in]   SlvAddr Slave Address.
+ * @return      None
  **********************************************************************/
 void UART_RS485SendSlvAddr(LPC_UART_TypeDef *UARTx, uint8_t SlvAddr)
 {
-	UART_RS485Send(UARTx, &SlvAddr, 1, 1);
+    UART_RS485Send(UARTx, &SlvAddr, 1, 1);
 }
 
 /*********************************************************************//**
- * @brief		Send Data frames on RS485 bus.
- * @param[in]	UARTx	LPC_UART1 (only)
- * @param[in]	pData Pointer to data to be sent.
- * @param[in]	size Size of data frame to be sent.
- * @return		None
+ * @brief       Send Data frames on RS485 bus.
+ * @param[in]   UARTx   LPC_UART1 (only)
+ * @param[in]   pData Pointer to data to be sent.
+ * @param[in]   size Size of data frame to be sent.
+ * @return      None
  **********************************************************************/
 uint32_t UART_RS485SendData(LPC_UART_TypeDef *UARTx, uint8_t *pData, uint32_t size)
 {
-	return (UART_RS485Send(UARTx, pData, size, 0));
+    return (UART_RS485Send(UARTx, pData, size, 0));
 }
 
 /**
diff --git a/bsp/lpc178x/drivers/lpc177x_8x_uart.h b/bsp/lpc178x/drivers/lpc177x_8x_uart.h
index 2b8a6f85cb..35c756d0c7 100644
--- a/bsp/lpc178x/drivers/lpc177x_8x_uart.h
+++ b/bsp/lpc178x/drivers/lpc177x_8x_uart.h
@@ -1,13 +1,13 @@
 /**********************************************************************
-* $Id$		lpc177x_8x_uart.h			2011-06-02
+* $Id$      lpc177x_8x_uart.h           2011-06-02
 *//**
-* @file		lpc177x_8x_uart.h
-* @brief	Contains all macro definitions and function prototypes
-*			support for UART firmware library on LPC177x_8x
-* @version	1.0
-* @date		02. June. 2011
-* @author	NXP MCU SW Application Team
-* 
+* @file     lpc177x_8x_uart.h
+* @brief    Contains all macro definitions and function prototypes
+*           support for UART firmware library on LPC177x_8x
+* @version  1.0
+* @date     02. June. 2011
+* @author   NXP MCU SW Application Team
+*
 * Copyright(C) 2011, NXP Semiconductor
 * All rights reserved.
 *
@@ -25,7 +25,7 @@
 **********************************************************************/
 
 /* Peripheral group ----------------------------------------------------------- */
-/** @defgroup UART	UART (Universal Asynchronous Receiver/Transmitter)
+/** @defgroup UART  UART (Universal Asynchronous Receiver/Transmitter)
  * @ingroup LPC177x_8xCMSIS_FwLib_Drivers
  * @{
  */
@@ -51,7 +51,7 @@ extern "C"
 /** UART time-out definitions in case of using Read() and Write function
  * with Blocking Flag mode
  */
-#define UART_BLOCKING_TIMEOUT			(0xFFFFFFFFUL)
+#define UART_BLOCKING_TIMEOUT           (0xFFFFFFFFUL)
 
 /**
  * @}
@@ -63,7 +63,7 @@ extern "C"
  */
 
 /* Accepted Error baud rate value (in percent unit) */
-#define UART_ACCEPTED_BAUDRATE_ERROR	(3)			/*!< Acceptable UART baudrate error */
+#define UART_ACCEPTED_BAUDRATE_ERROR    (3)         /*!< Acceptable UART baudrate error */
 
 
 /* --------------------- BIT DEFINITIONS -------------------------------------- */
@@ -71,27 +71,27 @@ extern "C"
  * Macro defines for Macro defines for UARTn Receiver Buffer Register
  **********************************************************************/
 /** UART Received Buffer mask bit (8 bits) */
-#define UART_RBR_MASKBIT   	((uint8_t)0xFF)
+#define UART_RBR_MASKBIT    ((uint8_t)0xFF)
 
 /*********************************************************************//**
  * Macro defines for Macro defines for UARTn Transmit Holding Register
  **********************************************************************/
 /** UART Transmit Holding mask bit (8 bits) */
-#define UART_THR_MASKBIT   	((uint8_t)0xFF)
+#define UART_THR_MASKBIT    ((uint8_t)0xFF)
 
 /*********************************************************************//**
  * Macro defines for Macro defines for UARTn Divisor Latch LSB register
  **********************************************************************/
 /** Macro for loading least significant halfs of divisors */
-#define UART_LOAD_DLL(div)	((div) & 0xFF)
+#define UART_LOAD_DLL(div)  ((div) & 0xFF)
 /** Divisor latch LSB bit mask */
-#define UART_DLL_MASKBIT	((uint8_t)0xFF)
+#define UART_DLL_MASKBIT    ((uint8_t)0xFF)
 
 /*********************************************************************//**
  * Macro defines for Macro defines for UARTn Divisor Latch MSB register
  **********************************************************************/
 /** Divisor latch MSB bit mask */
-#define UART_DLM_MASKBIT	((uint8_t)0xFF)
+#define UART_DLM_MASKBIT    ((uint8_t)0xFF)
 /** Macro for loading most significant halfs of divisors */
 #define UART_LOAD_DLM(div)  (((div) >> 8) & 0xFF)
 
@@ -99,258 +99,258 @@ extern "C"
  * Macro defines for Macro defines for UART interrupt enable register
  **********************************************************************/
 /** RBR Interrupt enable*/
-#define UART_IER_RBRINT_EN		((uint32_t)(1<<0))
+#define UART_IER_RBRINT_EN      ((uint32_t)(1<<0))
 /** THR Interrupt enable*/
-#define UART_IER_THREINT_EN		((uint32_t)(1<<1))
+#define UART_IER_THREINT_EN     ((uint32_t)(1<<1))
 /** RX line status interrupt enable*/
-#define UART_IER_RLSINT_EN		((uint32_t)(1<<2))
+#define UART_IER_RLSINT_EN      ((uint32_t)(1<<2))
 /** Modem status interrupt enable */
-#define UART1_IER_MSINT_EN		((uint32_t)(1<<3))
+#define UART1_IER_MSINT_EN      ((uint32_t)(1<<3))
 /** CTS1 signal transition interrupt enable */
-#define UART1_IER_CTSINT_EN		((uint32_t)(1<<7))
+#define UART1_IER_CTSINT_EN     ((uint32_t)(1<<7))
 /** Enables the end of auto-baud interrupt */
-#define UART_IER_ABEOINT_EN		((uint32_t)(1<<8))
+#define UART_IER_ABEOINT_EN     ((uint32_t)(1<<8))
 /** Enables the auto-baud time-out interrupt */
-#define UART_IER_ABTOINT_EN		((uint32_t)(1<<9))
+#define UART_IER_ABTOINT_EN     ((uint32_t)(1<<9))
 /** UART interrupt enable register bit mask */
-#define UART_IER_BITMASK		((uint32_t)(0x307))
+#define UART_IER_BITMASK        ((uint32_t)(0x307))
 /** UART1 interrupt enable register bit mask */
-#define UART1_IER_BITMASK		((uint32_t)(0x38F))
+#define UART1_IER_BITMASK       ((uint32_t)(0x38F))
 
 /*********************************************************************//**
  * Macro defines for Macro defines for UART interrupt identification register
  **********************************************************************/
 /** Interrupt Status - Active low */
-#define UART_IIR_INTSTAT_PEND	((uint32_t)(1<<0))
+#define UART_IIR_INTSTAT_PEND   ((uint32_t)(1<<0))
 /** Interrupt identification: Receive line status*/
-#define UART_IIR_INTID_RLS		((uint32_t)(3<<1))
+#define UART_IIR_INTID_RLS      ((uint32_t)(3<<1))
 /** Interrupt identification: Receive data available*/
-#define UART_IIR_INTID_RDA		((uint32_t)(2<<1))
+#define UART_IIR_INTID_RDA      ((uint32_t)(2<<1))
 /** Interrupt identification: Character time-out indicator*/
-#define UART_IIR_INTID_CTI		((uint32_t)(6<<1))
+#define UART_IIR_INTID_CTI      ((uint32_t)(6<<1))
 /** Interrupt identification: THRE interrupt*/
-#define UART_IIR_INTID_THRE		((uint32_t)(1<<1))
+#define UART_IIR_INTID_THRE     ((uint32_t)(1<<1))
 /** Interrupt identification: Modem interrupt*/
-#define UART1_IIR_INTID_MODEM	((uint32_t)(0<<1))
+#define UART1_IIR_INTID_MODEM   ((uint32_t)(0<<1))
 /** Interrupt identification: Interrupt ID mask */
-#define UART_IIR_INTID_MASK		((uint32_t)(7<<1))
+#define UART_IIR_INTID_MASK     ((uint32_t)(7<<1))
 /** These bits are equivalent to UnFCR[0] */
-#define UART_IIR_FIFO_EN		((uint32_t)(3<<6))
+#define UART_IIR_FIFO_EN        ((uint32_t)(3<<6))
 /** End of auto-baud interrupt */
-#define UART_IIR_ABEO_INT		((uint32_t)(1<<8))
+#define UART_IIR_ABEO_INT       ((uint32_t)(1<<8))
 /** Auto-baud time-out interrupt */
-#define UART_IIR_ABTO_INT		((uint32_t)(1<<9))
+#define UART_IIR_ABTO_INT       ((uint32_t)(1<<9))
 /** UART interrupt identification register bit mask */
-#define UART_IIR_BITMASK		((uint32_t)(0x3CF))
+#define UART_IIR_BITMASK        ((uint32_t)(0x3CF))
 
 /*********************************************************************//**
  * Macro defines for Macro defines for UART FIFO control register
  **********************************************************************/
 /** UART FIFO enable */
-#define UART_FCR_FIFO_EN		((uint8_t)(1<<0))
+#define UART_FCR_FIFO_EN        ((uint8_t)(1<<0))
 /** UART FIFO RX reset */
-#define UART_FCR_RX_RS			((uint8_t)(1<<1))
+#define UART_FCR_RX_RS          ((uint8_t)(1<<1))
 /** UART FIFO TX reset */
-#define UART_FCR_TX_RS			((uint8_t)(1<<2))
+#define UART_FCR_TX_RS          ((uint8_t)(1<<2))
 /** UART DMA mode selection */
-#define UART_FCR_DMAMODE_SEL 	((uint8_t)(1<<3))
+#define UART_FCR_DMAMODE_SEL    ((uint8_t)(1<<3))
 /** UART FIFO trigger level 0: 1 character */
-#define UART_FCR_TRG_LEV0		((uint8_t)(0))
+#define UART_FCR_TRG_LEV0       ((uint8_t)(0))
 /** UART FIFO trigger level 1: 4 character */
-#define UART_FCR_TRG_LEV1		((uint8_t)(1<<6))
+#define UART_FCR_TRG_LEV1       ((uint8_t)(1<<6))
 /** UART FIFO trigger level 2: 8 character */
-#define UART_FCR_TRG_LEV2		((uint8_t)(2<<6))
+#define UART_FCR_TRG_LEV2       ((uint8_t)(2<<6))
 /** UART FIFO trigger level 3: 14 character */
-#define UART_FCR_TRG_LEV3		((uint8_t)(3<<6))
+#define UART_FCR_TRG_LEV3       ((uint8_t)(3<<6))
 /** UART FIFO control bit mask */
-#define UART_FCR_BITMASK		((uint8_t)(0xCF))
+#define UART_FCR_BITMASK        ((uint8_t)(0xCF))
 
-#define UART_TX_FIFO_SIZE		(16)
+#define UART_TX_FIFO_SIZE       (16)
 
 /*********************************************************************//**
  * Macro defines for Macro defines for UART line control register
  **********************************************************************/
 /** UART 5 bit data mode */
-#define UART_LCR_WLEN5     		((uint8_t)(0))
+#define UART_LCR_WLEN5          ((uint8_t)(0))
 /** UART 6 bit data mode */
-#define UART_LCR_WLEN6     		((uint8_t)(1<<0))
+#define UART_LCR_WLEN6          ((uint8_t)(1<<0))
 /** UART 7 bit data mode */
-#define UART_LCR_WLEN7     		((uint8_t)(2<<0))
+#define UART_LCR_WLEN7          ((uint8_t)(2<<0))
 /** UART 8 bit data mode */
-#define UART_LCR_WLEN8     		((uint8_t)(3<<0))
+#define UART_LCR_WLEN8          ((uint8_t)(3<<0))
 /** UART Two Stop Bits Select */
-#define UART_LCR_STOPBIT_SEL	((uint8_t)(1<<2))
+#define UART_LCR_STOPBIT_SEL    ((uint8_t)(1<<2))
 /** UART Parity Enable */
-#define UART_LCR_PARITY_EN		((uint8_t)(1<<3))
+#define UART_LCR_PARITY_EN      ((uint8_t)(1<<3))
 /** UART Odd Parity Select */
-#define UART_LCR_PARITY_ODD		((uint8_t)(0))
+#define UART_LCR_PARITY_ODD     ((uint8_t)(0))
 /** UART Even Parity Select */
-#define UART_LCR_PARITY_EVEN	((uint8_t)(1<<4))
+#define UART_LCR_PARITY_EVEN    ((uint8_t)(1<<4))
 /** UART force 1 stick parity */
-#define UART_LCR_PARITY_F_1		((uint8_t)(2<<4))
+#define UART_LCR_PARITY_F_1     ((uint8_t)(2<<4))
 /** UART force 0 stick parity */
-#define UART_LCR_PARITY_F_0		((uint8_t)(3<<4))
+#define UART_LCR_PARITY_F_0     ((uint8_t)(3<<4))
 /** UART Transmission Break enable */
-#define UART_LCR_BREAK_EN		((uint8_t)(1<<6))
+#define UART_LCR_BREAK_EN       ((uint8_t)(1<<6))
 /** UART Divisor Latches Access bit enable */
-#define UART_LCR_DLAB_EN		((uint8_t)(1<<7))
+#define UART_LCR_DLAB_EN        ((uint8_t)(1<<7))
 /** UART line control bit mask */
-#define UART_LCR_BITMASK		((uint8_t)(0xFF))
+#define UART_LCR_BITMASK        ((uint8_t)(0xFF))
 
 /*********************************************************************//**
  * Macro defines for Macro defines for UART1 Modem Control Register
  **********************************************************************/
 /** Source for modem output pin DTR */
-#define UART1_MCR_DTR_CTRL		((uint8_t)(1<<0))
+#define UART1_MCR_DTR_CTRL      ((uint8_t)(1<<0))
 /** Source for modem output pin RTS */
-#define UART1_MCR_RTS_CTRL		((uint8_t)(1<<1))
+#define UART1_MCR_RTS_CTRL      ((uint8_t)(1<<1))
 /** Loop back mode select */
-#define UART1_MCR_LOOPB_EN		((uint8_t)(1<<4))
+#define UART1_MCR_LOOPB_EN      ((uint8_t)(1<<4))
 /** Enable Auto RTS flow-control */
-#define UART1_MCR_AUTO_RTS_EN	((uint8_t)(1<<6))
+#define UART1_MCR_AUTO_RTS_EN   ((uint8_t)(1<<6))
 /** Enable Auto CTS flow-control */
-#define UART1_MCR_AUTO_CTS_EN	((uint8_t)(1<<7))
+#define UART1_MCR_AUTO_CTS_EN   ((uint8_t)(1<<7))
 /** UART1 bit mask value */
-#define UART1_MCR_BITMASK		((uint8_t)(0x0F3))
+#define UART1_MCR_BITMASK       ((uint8_t)(0x0F3))
 
 /*********************************************************************//**
  * Macro defines for Macro defines for UART line status register
  **********************************************************************/
 /** Line status register: Receive data ready*/
-#define UART_LSR_RDR		((uint8_t)(1<<0))
+#define UART_LSR_RDR        ((uint8_t)(1<<0))
 /** Line status register: Overrun error*/
-#define UART_LSR_OE			((uint8_t)(1<<1))
+#define UART_LSR_OE         ((uint8_t)(1<<1))
 /** Line status register: Parity error*/
-#define UART_LSR_PE			((uint8_t)(1<<2))
+#define UART_LSR_PE         ((uint8_t)(1<<2))
 /** Line status register: Framing error*/
-#define UART_LSR_FE			((uint8_t)(1<<3))
+#define UART_LSR_FE         ((uint8_t)(1<<3))
 /** Line status register: Break interrupt*/
-#define UART_LSR_BI			((uint8_t)(1<<4))
+#define UART_LSR_BI         ((uint8_t)(1<<4))
 /** Line status register: Transmit holding register empty*/
-#define UART_LSR_THRE		((uint8_t)(1<<5))
+#define UART_LSR_THRE       ((uint8_t)(1<<5))
 /** Line status register: Transmitter empty*/
-#define UART_LSR_TEMT		((uint8_t)(1<<6))
+#define UART_LSR_TEMT       ((uint8_t)(1<<6))
 /** Error in RX FIFO*/
-#define UART_LSR_RXFE		((uint8_t)(1<<7))
+#define UART_LSR_RXFE       ((uint8_t)(1<<7))
 /** UART Line status bit mask */
-#define UART_LSR_BITMASK	((uint8_t)(0xFF))
+#define UART_LSR_BITMASK    ((uint8_t)(0xFF))
 
 /*********************************************************************//**
  * Macro defines for Macro defines for UART Modem (UART1 only) status register
  **********************************************************************/
 /** Set upon state change of input CTS */
-#define UART1_MSR_DELTA_CTS		((uint8_t)(1<<0))
+#define UART1_MSR_DELTA_CTS     ((uint8_t)(1<<0))
 /** Set upon state change of input DSR */
-#define UART1_MSR_DELTA_DSR		((uint8_t)(1<<1))
+#define UART1_MSR_DELTA_DSR     ((uint8_t)(1<<1))
 /** Set upon low to high transition of input RI */
-#define UART1_MSR_LO2HI_RI		((uint8_t)(1<<2))
+#define UART1_MSR_LO2HI_RI      ((uint8_t)(1<<2))
 /** Set upon state change of input DCD */
-#define UART1_MSR_DELTA_DCD		((uint8_t)(1<<3))
+#define UART1_MSR_DELTA_DCD     ((uint8_t)(1<<3))
 /** Clear To Send State */
-#define UART1_MSR_CTS			((uint8_t)(1<<4))
+#define UART1_MSR_CTS           ((uint8_t)(1<<4))
 /** Data Set Ready State */
-#define UART1_MSR_DSR			((uint8_t)(1<<5))
+#define UART1_MSR_DSR           ((uint8_t)(1<<5))
 /** Ring Indicator State */
-#define UART1_MSR_RI			((uint8_t)(1<<6))
+#define UART1_MSR_RI            ((uint8_t)(1<<6))
 /** Data Carrier Detect State */
-#define UART1_MSR_DCD			((uint8_t)(1<<7))
+#define UART1_MSR_DCD           ((uint8_t)(1<<7))
 /** MSR register bit-mask value */
-#define UART1_MSR_BITMASK		((uint8_t)(0xFF))
+#define UART1_MSR_BITMASK       ((uint8_t)(0xFF))
 
 /*********************************************************************//**
  * Macro defines for Macro defines for UART Scratch Pad Register
  **********************************************************************/
 /** UART Scratch Pad bit mask */
-#define UART_SCR_BIMASK		((uint8_t)(0xFF))
+#define UART_SCR_BIMASK     ((uint8_t)(0xFF))
 
 /*********************************************************************//**
  * Macro defines for Macro defines for UART Auto baudrate control register
  **********************************************************************/
 /** UART Auto-baud start */
-#define UART_ACR_START				((uint32_t)(1<<0))
+#define UART_ACR_START              ((uint32_t)(1<<0))
 /** UART Auto baudrate Mode 1 */
-#define UART_ACR_MODE				((uint32_t)(1<<1))
+#define UART_ACR_MODE               ((uint32_t)(1<<1))
 /** UART Auto baudrate restart */
-#define UART_ACR_AUTO_RESTART		((uint32_t)(1<<2))
+#define UART_ACR_AUTO_RESTART       ((uint32_t)(1<<2))
 /** UART End of auto-baud interrupt clear */
-#define UART_ACR_ABEOINT_CLR		((uint32_t)(1<<8))
+#define UART_ACR_ABEOINT_CLR        ((uint32_t)(1<<8))
 /** UART Auto-baud time-out interrupt clear */
-#define UART_ACR_ABTOINT_CLR		((uint32_t)(1<<9))
+#define UART_ACR_ABTOINT_CLR        ((uint32_t)(1<<9))
 /** UART Auto Baudrate register bit mask */
-#define UART_ACR_BITMASK			((uint32_t)(0x307))
+#define UART_ACR_BITMASK            ((uint32_t)(0x307))
 
 /*********************************************************************//**
  * Macro defines for Macro defines for UART IrDA control register
  **********************************************************************/
 /** IrDA mode enable */
-#define UART_ICR_IRDAEN			((uint32_t)(1<<0))
+#define UART_ICR_IRDAEN         ((uint32_t)(1<<0))
 /** IrDA serial input inverted */
-#define UART_ICR_IRDAINV		((uint32_t)(1<<1))
+#define UART_ICR_IRDAINV        ((uint32_t)(1<<1))
 /** IrDA fixed pulse width mode */
-#define UART_ICR_FIXPULSE_EN	((uint32_t)(1<<2))
+#define UART_ICR_FIXPULSE_EN    ((uint32_t)(1<<2))
 /** PulseDiv - Configures the pulse when FixPulseEn = 1 */
-#define UART_ICR_PULSEDIV(n)	((uint32_t)((n&0x07)<<3))
+#define UART_ICR_PULSEDIV(n)    ((uint32_t)((n&0x07)<<3))
 /** UART IRDA bit mask */
-#define UART_ICR_BITMASK		((uint32_t)(0x3F))
+#define UART_ICR_BITMASK        ((uint32_t)(0x3F))
 
 /*********************************************************************//**
  * Macro defines for Macro defines for UART Fractional divider register
  **********************************************************************/
 /** Baud-rate generation pre-scaler divisor */
-#define UART_FDR_DIVADDVAL(n)	((uint32_t)(n&0x0F))
+#define UART_FDR_DIVADDVAL(n)   ((uint32_t)(n&0x0F))
 /** Baud-rate pre-scaler multiplier value */
-#define UART_FDR_MULVAL(n)		((uint32_t)((n<<4)&0xF0))
+#define UART_FDR_MULVAL(n)      ((uint32_t)((n<<4)&0xF0))
 /** UART Fractional Divider register bit mask */
-#define UART_FDR_BITMASK		((uint32_t)(0xFF))
+#define UART_FDR_BITMASK        ((uint32_t)(0xFF))
 
 /*********************************************************************//**
  * Macro defines for Macro defines for UART Tx Enable register
  **********************************************************************/
 /** Transmit enable bit */
-#define UART_TER_TXEN			((uint8_t)(1<<7))
+#define UART_TER_TXEN           ((uint8_t)(1<<7))
 /** UART Transmit Enable Register bit mask */
-#define UART_TER_BITMASK		((uint8_t)(0x80))
+#define UART_TER_BITMASK        ((uint8_t)(0x80))
 
 /*********************************************************************//**
  * Macro defines for Macro defines for UART1 RS485 Control register
  **********************************************************************/
 /** RS-485/EIA-485 Normal Multi-drop Mode (NMM) is disabled */
-#define UART1_RS485CTRL_NMM_EN		((uint32_t)(1<<0))
+#define UART1_RS485CTRL_NMM_EN      ((uint32_t)(1<<0))
 /** The receiver is disabled */
-#define UART1_RS485CTRL_RX_DIS		((uint32_t)(1<<1))
+#define UART1_RS485CTRL_RX_DIS      ((uint32_t)(1<<1))
 /** Auto Address Detect (AAD) is enabled */
-#define UART1_RS485CTRL_AADEN		((uint32_t)(1<<2))
+#define UART1_RS485CTRL_AADEN       ((uint32_t)(1<<2))
 /** If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control */
-#define UART1_RS485CTRL_SEL_DTR		((uint32_t)(1<<3))
+#define UART1_RS485CTRL_SEL_DTR     ((uint32_t)(1<<3))
 /** Enable Auto Direction Control */
-#define UART1_RS485CTRL_DCTRL_EN	((uint32_t)(1<<4))
-/** This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin. 
+#define UART1_RS485CTRL_DCTRL_EN    ((uint32_t)(1<<4))
+/** This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.
 The direction control pin will be driven to logic "1" when the transmitter has data to be sent */
-#define UART1_RS485CTRL_OINV_1		((uint32_t)(1<<5))
+#define UART1_RS485CTRL_OINV_1      ((uint32_t)(1<<5))
 
 /** RS485 control bit-mask value */
-#define UART1_RS485CTRL_BITMASK		((uint32_t)(0x3F))
+#define UART1_RS485CTRL_BITMASK     ((uint32_t)(0x3F))
 
 /*********************************************************************//**
  * Macro defines for Macro defines for UART1 RS-485 Address Match register
  **********************************************************************/
-#define UART1_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF)) 	/**< Bit mask value */
+#define UART1_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF))   /**< Bit mask value */
 
 /*********************************************************************//**
  * Macro defines for Macro defines for UART1 RS-485 Delay value register
  **********************************************************************/
 /* Macro defines for UART1 RS-485 Delay value register */
-#define UART1_RS485DLY_BITMASK		((uint8_t)(0xFF)) 	/** Bit mask value */
+#define UART1_RS485DLY_BITMASK      ((uint8_t)(0xFF))   /** Bit mask value */
 
 /*********************************************************************//**
  * Macro defines for Macro defines for UART FIFO Level register
  **********************************************************************/
 /** Reflects the current level of the UART receiver FIFO */
-#define UART_FIFOLVL_RXFIFOLVL(n)	((uint32_t)(n&0x0F))
+#define UART_FIFOLVL_RXFIFOLVL(n)   ((uint32_t)(n&0x0F))
 /** Reflects the current level of the UART transmitter FIFO */
-#define UART_FIFOLVL_TXFIFOLVL(n)	((uint32_t)((n>>8)&0x0F))
+#define UART_FIFOLVL_TXFIFOLVL(n)   ((uint32_t)((n>>8)&0x0F))
 /** UART FIFO Level Register bit mask */
-#define UART_FIFOLVL_BITMASK		((uint32_t)(0x0F0F))
+#define UART_FIFOLVL_BITMASK        ((uint32_t)(0x0F0F))
 
 
 /**
@@ -367,199 +367,199 @@ The direction control pin will be driven to logic "1" when the transmitter has d
  * @brief UART Databit type definitions
  */
 typedef enum {
-	UART_DATABIT_5		= 0,     		/*!< UART 5 bit data mode */
-	UART_DATABIT_6,		     			/*!< UART 6 bit data mode */
-	UART_DATABIT_7,		     			/*!< UART 7 bit data mode */
-	UART_DATABIT_8		     			/*!< UART 8 bit data mode */
+    UART_DATABIT_5      = 0,            /*!< UART 5 bit data mode */
+    UART_DATABIT_6,                     /*!< UART 6 bit data mode */
+    UART_DATABIT_7,                     /*!< UART 7 bit data mode */
+    UART_DATABIT_8                      /*!< UART 8 bit data mode */
 } UART_DATABIT_Type;
 
 /**
  * @brief UART Stop bit type definitions
  */
 typedef enum {
-	UART_STOPBIT_1		= (0),   					/*!< UART 1 Stop Bits Select */
-	UART_STOPBIT_2,		 							/*!< UART Two Stop Bits Select */
+    UART_STOPBIT_1      = (0),                      /*!< UART 1 Stop Bits Select */
+    UART_STOPBIT_2,                                 /*!< UART Two Stop Bits Select */
 } UART_STOPBIT_Type;
 
 /**
  * @brief UART Parity type definitions
  */
 typedef enum {
-	UART_PARITY_NONE 	= 0,					/*!< No parity */
-	UART_PARITY_ODD,	 						/*!< Odd parity */
-	UART_PARITY_EVEN, 							/*!< Even parity */
-	UART_PARITY_SP_1, 							/*!< Forced "1" stick parity */
-	UART_PARITY_SP_0 							/*!< Forced "0" stick parity */
+    UART_PARITY_NONE    = 0,                    /*!< No parity */
+    UART_PARITY_ODD,                            /*!< Odd parity */
+    UART_PARITY_EVEN,                           /*!< Even parity */
+    UART_PARITY_SP_1,                           /*!< Forced "1" stick parity */
+    UART_PARITY_SP_0                            /*!< Forced "0" stick parity */
 } UART_PARITY_Type;
 
 /**
  * @brief FIFO Level type definitions
  */
 typedef enum {
-	UART_FIFO_TRGLEV0 = 0,	/*!< UART FIFO trigger level 0: 1 character */
-	UART_FIFO_TRGLEV1, 		/*!< UART FIFO trigger level 1: 4 character */
-	UART_FIFO_TRGLEV2,		/*!< UART FIFO trigger level 2: 8 character */
-	UART_FIFO_TRGLEV3		/*!< UART FIFO trigger level 3: 14 character */
+    UART_FIFO_TRGLEV0 = 0,  /*!< UART FIFO trigger level 0: 1 character */
+    UART_FIFO_TRGLEV1,      /*!< UART FIFO trigger level 1: 4 character */
+    UART_FIFO_TRGLEV2,      /*!< UART FIFO trigger level 2: 8 character */
+    UART_FIFO_TRGLEV3       /*!< UART FIFO trigger level 3: 14 character */
 } UART_FITO_LEVEL_Type;
 
 /********************************************************************//**
 * @brief UART Interrupt Type definitions
 **********************************************************************/
 typedef enum {
-	UART_INTCFG_RBR = 0,	/*!< RBR Interrupt enable*/
-	UART_INTCFG_THRE,		/*!< THR Interrupt enable*/
-	UART_INTCFG_RLS,		/*!< RX line status interrupt enable*/
-	UART1_INTCFG_MS,		/*!< Modem status interrupt enable (UART1 only) */
-	UART1_INTCFG_CTS,		/*!< CTS1 signal transition interrupt enable (UART1 only) */
-	UART_INTCFG_ABEO,		/*!< Enables the end of auto-baud interrupt */
-	UART_INTCFG_ABTO		/*!< Enables the auto-baud time-out interrupt */
+    UART_INTCFG_RBR = 0,    /*!< RBR Interrupt enable*/
+    UART_INTCFG_THRE,       /*!< THR Interrupt enable*/
+    UART_INTCFG_RLS,        /*!< RX line status interrupt enable*/
+    UART1_INTCFG_MS,        /*!< Modem status interrupt enable (UART1 only) */
+    UART1_INTCFG_CTS,       /*!< CTS1 signal transition interrupt enable (UART1 only) */
+    UART_INTCFG_ABEO,       /*!< Enables the end of auto-baud interrupt */
+    UART_INTCFG_ABTO        /*!< Enables the auto-baud time-out interrupt */
 } UART_INT_Type;
 
 /**
  * @brief UART Line Status Type definition
  */
 typedef enum {
-	UART_LINESTAT_RDR	= UART_LSR_RDR,			/*!DIR |= 1<<4;
-	LPC_GPIO5->CLR  = 1<<4;
-	LPC_GPIO5->SET  = 1<<4;
+    LPC_GPIO5->DIR |= 1<<4;
+    LPC_GPIO5->CLR  = 1<<4;
+    LPC_GPIO5->SET  = 1<<4;
 
-	/*Disable LCD controller*/
-	GLCD_Ctrl (FALSE);
-	/*Init LCD and copy picture in video RAM*/
-	GLCD_Init (_lcd_info.framebuffer);
-	/*Enable LCD*/
-	GLCD_Ctrl (TRUE);
+    /*Disable LCD controller*/
+    GLCD_Ctrl (FALSE);
+    /*Init LCD and copy picture in video RAM*/
+    GLCD_Init (_lcd_info.framebuffer);
+    /*Enable LCD*/
+    GLCD_Ctrl (TRUE);
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args)
 {
-	switch (cmd)
-	{
-	case RTGRAPHIC_CTRL_RECT_UPDATE:
-		break;
-	case RTGRAPHIC_CTRL_POWERON:
-		break;
-	case RTGRAPHIC_CTRL_POWEROFF:
-		break;
-	case RTGRAPHIC_CTRL_GET_INFO:
-		rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
-		break;
-	case RTGRAPHIC_CTRL_SET_MODE:
-		break;
-	}
+    switch (cmd)
+    {
+    case RTGRAPHIC_CTRL_RECT_UPDATE:
+        break;
+    case RTGRAPHIC_CTRL_POWERON:
+        break;
+    case RTGRAPHIC_CTRL_POWEROFF:
+        break;
+    case RTGRAPHIC_CTRL_GET_INFO:
+        rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
+        break;
+    case RTGRAPHIC_CTRL_SET_MODE:
+        break;
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 
@@ -63,27 +63,27 @@ void rt_hw_lcd_init(void)
 {
     rt_uint16_t * _rt_framebuffer = RT_NULL;
 
-	// _rt_framebuffer = rt_malloc_align(sizeof(rt_uint16_t)*RT_HW_LCD_HEIGHT*RT_HW_LCD_WIDTH, 8);
-	// if (_rt_framebuffer == RT_NULL) return; /* no memory yet */
+    // _rt_framebuffer = rt_malloc_align(sizeof(rt_uint16_t)*RT_HW_LCD_HEIGHT*RT_HW_LCD_WIDTH, 8);
+    // if (_rt_framebuffer == RT_NULL) return; /* no memory yet */
 
-	_rt_framebuffer = (rt_uint16_t *)0xA0000000;
+    _rt_framebuffer = (rt_uint16_t *)0xA0000000;
 
-	_lcd_info.bits_per_pixel = 16;
-	_lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565;
-	_lcd_info.framebuffer = (void*)_rt_framebuffer;
-	_lcd_info.width = RT_HW_LCD_WIDTH;
-	_lcd_info.height = RT_HW_LCD_HEIGHT;
+    _lcd_info.bits_per_pixel = 16;
+    _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565;
+    _lcd_info.framebuffer = (void*)_rt_framebuffer;
+    _lcd_info.width = RT_HW_LCD_WIDTH;
+    _lcd_info.height = RT_HW_LCD_HEIGHT;
 
-	/* init device structure */
-	lcd.type = RT_Device_Class_Graphic;
-	lcd.init = rt_lcd_init;
-	lcd.open = RT_NULL;
-	lcd.close = RT_NULL;
-	lcd.control = rt_lcd_control;
-	lcd.user_data = (void*)&_lcd_info;
+    /* init device structure */
+    lcd.type = RT_Device_Class_Graphic;
+    lcd.init = rt_lcd_init;
+    lcd.open = RT_NULL;
+    lcd.close = RT_NULL;
+    lcd.control = rt_lcd_control;
+    lcd.user_data = (void*)&_lcd_info;
 
-	/* register lcd device to RT-Thread */
-	rt_device_register(&lcd, "lcd", RT_DEVICE_FLAG_RDWR);
+    /* register lcd device to RT-Thread */
+    rt_device_register(&lcd, "lcd", RT_DEVICE_FLAG_RDWR);
 }
 
 void lcd_fill(uint8_t * start, uint8_t * end, uint8_t pixel)
diff --git a/bsp/lpc178x/drivers/lpc_types.h b/bsp/lpc178x/drivers/lpc_types.h
index 9cc511a135..a36624baf4 100644
--- a/bsp/lpc178x/drivers/lpc_types.h
+++ b/bsp/lpc178x/drivers/lpc_types.h
@@ -1,15 +1,15 @@
 /**********************************************************************
-* $Id$		lpc_types.h			2011-06-02
+* $Id$      lpc_types.h         2011-06-02
 *//**
-* @file		lpc_types.h
-* @brief	Contains the NXP ABL typedefs for C standard types.
-*			It is intended to be used in ISO C conforming development
-*			environments and checks for this insofar as it is possible
-*			to do so.
-* @version	1.0
-* @date		02. June. 2011
-* @author	NXP MCU SW Application Team
-* 
+* @file     lpc_types.h
+* @brief    Contains the NXP ABL typedefs for C standard types.
+*           It is intended to be used in ISO C conforming development
+*           environments and checks for this insofar as it is possible
+*           to do so.
+* @version  1.0
+* @date     02. June. 2011
+* @author   NXP MCU SW Application Team
+*
 * Copyright(C) 2011, NXP Semiconductor
 * All rights reserved.
 *
@@ -37,7 +37,7 @@
  * @ingroup LPC177x_8xCMSIS_FwLib_Drivers
  * @{
  */
- 
+
 /* Public Types --------------------------------------------------------------- */
 /** @defgroup LPC_Types_Public_Types Basic Public Data Types
  * @{
@@ -71,8 +71,8 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
  */
 typedef enum
 {
-	NONE_BLOCKING = 0,		/**< None Blocking type */
-	BLOCKING,				/**< Blocking type */
+    NONE_BLOCKING = 0,      /**< None Blocking type */
+    BLOCKING,               /**< Blocking type */
 } TRANSFER_BLOCK_Type;
 
 
@@ -98,7 +98,7 @@ typedef int32_t(*PFI)();
  */
 #undef _BIT
 /** Set bit macro */
-#define _BIT(n)	(1<TCR = 0x02;		/* reset timer */
-//	LPC_TIM0->PR  = 0x00;		/* set prescaler to zero */
-//	LPC_TIM0->MR0 = delayInMs * (PeripheralClock / 1000 - 1);
-//	LPC_TIM0->IR  = 0xff;		/* reset all interrrupts */
-//	LPC_TIM0->MCR = 0x04;		/* stop timer on match */
-//	LPC_TIM0->TCR = 0x01;		/* start timer */
+//  LPC_TIM0->TCR = 0x02;       /* reset timer */
+//  LPC_TIM0->PR  = 0x00;       /* set prescaler to zero */
+//  LPC_TIM0->MR0 = delayInMs * (PeripheralClock / 1000 - 1);
+//  LPC_TIM0->IR  = 0xff;       /* reset all interrrupts */
+//  LPC_TIM0->MCR = 0x04;       /* stop timer on match */
+//  LPC_TIM0->TCR = 0x01;       /* start timer */
 //
-//	/* wait until delay time has elapsed */
-//	while (LPC_TIM0->TCR & 0x01);
+//  /* wait until delay time has elapsed */
+//  while (LPC_TIM0->TCR & 0x01);
 //  }
 //  else if ( timer_num == 1 )
 //  {
-//	LPC_TIM1->TCR = 0x02;		/* reset timer */
-//	LPC_TIM1->PR  = 0x00;		/* set prescaler to zero */
-//	LPC_TIM1->MR0 = delayInMs * (PeripheralClock / 1000 - 1);
-//	LPC_TIM1->IR  = 0xff;		/* reset all interrrupts */
-//	LPC_TIM1->MCR = 0x04;		/* stop timer on match */
-//	LPC_TIM1->TCR = 0x01;		/* start timer */
+//  LPC_TIM1->TCR = 0x02;       /* reset timer */
+//  LPC_TIM1->PR  = 0x00;       /* set prescaler to zero */
+//  LPC_TIM1->MR0 = delayInMs * (PeripheralClock / 1000 - 1);
+//  LPC_TIM1->IR  = 0xff;       /* reset all interrrupts */
+//  LPC_TIM1->MCR = 0x04;       /* stop timer on match */
+//  LPC_TIM1->TCR = 0x01;       /* start timer */
 //
-//	/* wait until delay time has elapsed */
-//	while (LPC_TIM1->TCR & 0x01);
+//  /* wait until delay time has elapsed */
+//  while (LPC_TIM1->TCR & 0x01);
 //  }
 //  else if ( timer_num == 2 )
 //  {
-//	LPC_TIM2->TCR = 0x02;		/* reset timer */
-//	LPC_TIM2->PR  = 0x00;		/* set prescaler to zero */
-//	LPC_TIM2->MR0 = delayInMs * (PeripheralClock / 1000 - 1);
-//	LPC_TIM2->IR  = 0xff;		/* reset all interrrupts */
-//	LPC_TIM2->MCR = 0x04;		/* stop timer on match */
-//	LPC_TIM2->TCR = 0x01;		/* start timer */
+//  LPC_TIM2->TCR = 0x02;       /* reset timer */
+//  LPC_TIM2->PR  = 0x00;       /* set prescaler to zero */
+//  LPC_TIM2->MR0 = delayInMs * (PeripheralClock / 1000 - 1);
+//  LPC_TIM2->IR  = 0xff;       /* reset all interrrupts */
+//  LPC_TIM2->MCR = 0x04;       /* stop timer on match */
+//  LPC_TIM2->TCR = 0x01;       /* start timer */
 //
-//	/* wait until delay time has elapsed */
-//	while (LPC_TIM2->TCR & 0x01);
+//  /* wait until delay time has elapsed */
+//  while (LPC_TIM2->TCR & 0x01);
 //  }
 //  else if ( timer_num == 3 )
 //  {
-//	LPC_TIM3->TCR = 0x02;		/* reset timer */
-//	LPC_TIM3->PR  = 0x00;		/* set prescaler to zero */
-//	LPC_TIM3->MR0 = delayInMs * (PeripheralClock / 1000 - 1);
-//	LPC_TIM3->IR  = 0xff;		/* reset all interrrupts */
-//	LPC_TIM3->MCR = 0x04;		/* stop timer on match */
-//	LPC_TIM3->TCR = 0x01;		/* start timer */
+//  LPC_TIM3->TCR = 0x02;       /* reset timer */
+//  LPC_TIM3->PR  = 0x00;       /* set prescaler to zero */
+//  LPC_TIM3->MR0 = delayInMs * (PeripheralClock / 1000 - 1);
+//  LPC_TIM3->IR  = 0xff;       /* reset all interrrupts */
+//  LPC_TIM3->MCR = 0x04;       /* stop timer on match */
+//  LPC_TIM3->TCR = 0x01;       /* start timer */
 //
-//	/* wait until delay time has elapsed */
-//	while (LPC_TIM3->TCR & 0x01);
+//  /* wait until delay time has elapsed */
+//  while (LPC_TIM3->TCR & 0x01);
 //  }
 //  return;
 //}
@@ -204,7 +204,7 @@ void SDRAM_Init (void)
 {
     uint32_t i, dwtemp = dwtemp;
     uint16_t wtemp = wtemp;
-	uint32_t mhz, nsPerClk;
+    uint32_t mhz, nsPerClk;
     /* Enable External Memory Controller power/clock */
     LPC_SC->PCONP      |= 0x00000800;
     LPC_SC->EMCDLYCTL   = 0x00001010;
@@ -213,10 +213,10 @@ void SDRAM_Init (void)
 
     EMC_GPIO_Init();
 
-	mhz = SystemCoreClock / 1000000;
-	if (LPC_SC->EMCCLKSEL)
-		mhz >>= 1;
-	nsPerClk = 1000 / mhz;
+    mhz = SystemCoreClock / 1000000;
+    if (LPC_SC->EMCCLKSEL)
+        mhz >>= 1;
+    nsPerClk = 1000 / mhz;
     LPC_EMC->DynamicRP         = EMC_NS2CLK(20, nsPerClk); /* 20ns,  */
     LPC_EMC->DynamicRAS        = /*EMC_NS2CLK(42, nsPerClk);*/ 15; /* 42ns to 100K ns,  */
     LPC_EMC->DynamicSREX       = 1 - 1; /* tSRE, 1clk, */
@@ -225,7 +225,7 @@ void SDRAM_Init (void)
     LPC_EMC->DynamicWR         = 2 - 1; /* 2CLK,  */
     LPC_EMC->DynamicRC         = EMC_NS2CLK(63, nsPerClk); /* H57V2562GTR-75C tRC=63ns(min)*/
     LPC_EMC->DynamicRFC        = EMC_NS2CLK(63, nsPerClk); /* H57V2562GTR-75C tRFC=tRC */
-    LPC_EMC->DynamicXSR        = 0x0000000F; /* exit self-refresh to active, ֪Ϊ  */
+    LPC_EMC->DynamicXSR        = 0x0000000F; /* exit self-refresh to active, 不知道，设为最久  */
     LPC_EMC->DynamicRRD        = EMC_NS2CLK(63, nsPerClk); /* 3clk, tRRD=15ns(min) */
     LPC_EMC->DynamicMRD        = 2 - 1; /* 2clk, tMRD=2clk(min) */
 
@@ -249,22 +249,22 @@ void SDRAM_Init (void)
 #ifdef SDRAM_CONFIG_16BIT
     LPC_EMC->DynamicConfig0    = 0x680; /* 256Mb, 16Mx16, 4 banks, row=13, column=9, RBC */
 #elif defined SDRAM_CONFIG_32BIT
-    LPC_EMC->DynamicConfig0	= 0x4680; /* 256Mb, 16Mx16, 4 banks, row=13, column=9, RBC */
+    LPC_EMC->DynamicConfig0 = 0x4680; /* 256Mb, 16Mx16, 4 banks, row=13, column=9, RBC */
 #endif
     delayMs(0, 100);
 
     LPC_EMC->DynamicControl    = 0x00000183; /* Issue NOP command */
-    delayMs(0, 200);							  /* wait 200ms */
+    delayMs(0, 200);                              /* wait 200ms */
 
     LPC_EMC->DynamicControl    = 0x00000103; /* Issue PALL command */
 
     LPC_EMC->DynamicRefresh    = 0x00000002; /* ( n * 16 ) -> 32 clock cycles */
-    for(i = 0; i < 0x80; i++);	              /* wait 128 AHB clock cycles */
+    for(i = 0; i < 0x80; i++);                /* wait 128 AHB clock cycles */
     /* 64ms/8192=7.8125us, nx16x8.33ns<7.8125us, n<58.6*/
-	wtemp = 64000000 / (1 << 13);
-	wtemp -= 16;
-	wtemp >>= 4;
-	wtemp = wtemp * mhz / 1000;
+    wtemp = 64000000 / (1 << 13);
+    wtemp -= 16;
+    wtemp >>= 4;
+    wtemp = wtemp * mhz / 1000;
     LPC_EMC->DynamicRefresh    = wtemp;
 
     LPC_EMC->DynamicControl    = 0x00000083; /* Issue MODE command */
@@ -273,7 +273,7 @@ void SDRAM_Init (void)
 
     wtemp = *((volatile uint16_t *)(SDRAM_BASE | (0x33<<12))); /* 8 burst, 3 CAS latency */
 #elif defined SDRAM_CONFIG_32BIT
-    dwtemp = *((volatile uint32_t *)(SDRAM_BASE | (0x32<<13)));	/* 4 burst, 3 CAS latency */
+    dwtemp = *((volatile uint32_t *)(SDRAM_BASE | (0x32<<13))); /* 4 burst, 3 CAS latency */
 #endif
 
     LPC_EMC->DynamicControl    = 0x00000000; /* Issue NORMAL command */
diff --git a/bsp/lpc178x/drivers/sdram.h b/bsp/lpc178x/drivers/sdram.h
index d89e515ebb..b627bed75e 100644
--- a/bsp/lpc178x/drivers/sdram.h
+++ b/bsp/lpc178x/drivers/sdram.h
@@ -1,3 +1,12 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
 #ifndef SDRAM_H_INCLUDED
 #define SDRAM_H_INCLUDED
 
diff --git a/bsp/lpc178x/drivers/uart.c b/bsp/lpc178x/drivers/uart.c
index 0d92eb1fca..cb8e68d30c 100644
--- a/bsp/lpc178x/drivers/uart.c
+++ b/bsp/lpc178x/drivers/uart.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -25,14 +25,14 @@
 
 struct rt_uart_lpc
 {
-	struct rt_device parent;
+    struct rt_device parent;
 
-	LPC_UART_TypeDef * UART;
-	IRQn_Type UART_IRQn;
+    LPC_UART_TypeDef * UART;
+    IRQn_Type UART_IRQn;
 
-	/* buffer for reception */
-	rt_uint8_t read_index, save_index;
-	rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
+    /* buffer for reception */
+    rt_uint8_t read_index, save_index;
+    rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
 };
 
 #ifdef RT_USING_UART0
@@ -45,96 +45,96 @@ struct rt_uart_lpc uart1_device;
 #ifdef RT_USING_UART0
 void UART0_IRQHandler(void)
 {
-	rt_ubase_t level, iir;
+    rt_ubase_t level, iir;
     struct rt_uart_lpc* uart = &uart0_device;
 
-	/* enter interrupt */
-	rt_interrupt_enter();
+    /* enter interrupt */
+    rt_interrupt_enter();
 
     /* read IIR and clear it */
-	iir = uart->UART->IIR;
+    iir = uart->UART->IIR;
 
-	if (iir == UART_IIR_INTID_RDA)	    /* Receive Data Available */
-	{
-		/* Receive Data Available */
+    if (iir == UART_IIR_INTID_RDA)      /* Receive Data Available */
+    {
+        /* Receive Data Available */
         uart->rx_buffer[uart->save_index] = uart->UART->RBR;
 
         level = rt_hw_interrupt_disable();
-		uart->save_index ++;
+        uart->save_index ++;
         if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
             uart->save_index = 0;
         rt_hw_interrupt_enable(level);
 
-		/* invoke callback */
-		if(uart->parent.rx_indicate != RT_NULL)
-		{
-		    rt_size_t length;
-		    if (uart->read_index > uart->save_index)
+        /* invoke callback */
+        if(uart->parent.rx_indicate != RT_NULL)
+        {
+            rt_size_t length;
+            if (uart->read_index > uart->save_index)
                 length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
             else
                 length = uart->save_index - uart->read_index;
 
             uart->parent.rx_indicate(&uart->parent, length);
-		}
-	}
+        }
+    }
 
-	/* leave interrupt */
-	rt_interrupt_leave();
+    /* leave interrupt */
+    rt_interrupt_leave();
 
-	return;
+    return;
 }
 #endif
 
 #ifdef RT_USING_UART1
 void UART1_IRQHandler(void)
 {
-	rt_ubase_t level, iir;
+    rt_ubase_t level, iir;
     struct rt_uart_lpc* uart = &uart1_device;
 
-	/* enter interrupt */
-	rt_interrupt_enter();
+    /* enter interrupt */
+    rt_interrupt_enter();
 
     /* read IIR and clear it */
-	iir = uart->UART->IIR;
+    iir = uart->UART->IIR;
 
-	if (iir == UART_IIR_INTID_RDA)	    /* Receive Data Available */
-	{
-		/* Receive Data Available */
+    if (iir == UART_IIR_INTID_RDA)      /* Receive Data Available */
+    {
+        /* Receive Data Available */
         uart->rx_buffer[uart->save_index] = uart->UART->RBR;
 
         level = rt_hw_interrupt_disable();
-		uart->save_index ++;
+        uart->save_index ++;
         if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
             uart->save_index = 0;
         rt_hw_interrupt_enable(level);
 
-		/* invoke callback */
-		if(uart->parent.rx_indicate != RT_NULL)
-		{
-		    rt_size_t length;
-		    if (uart->read_index > uart->save_index)
+        /* invoke callback */
+        if(uart->parent.rx_indicate != RT_NULL)
+        {
+            rt_size_t length;
+            if (uart->read_index > uart->save_index)
                 length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
             else
                 length = uart->save_index - uart->read_index;
 
             uart->parent.rx_indicate(&uart->parent, length);
-		}
-	}
+        }
+    }
 
-	/* leave interrupt */
-	rt_interrupt_leave();
+    /* leave interrupt */
+    rt_interrupt_leave();
 
-	return;
+    return;
 }
 #endif
 
 static rt_err_t rt_uart_init (rt_device_t dev)
 {
-	struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
-	UART_CFG_Type UART_ConfigStruct;
+    struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
+    UART_CFG_Type UART_ConfigStruct;
 
 #ifdef RT_USING_UART0
-	if( uart->UART == LPC_UART0 )
+    if( uart->UART == LPC_UART0 )
     {
         /*
          * Initialize UART0 pin connect
@@ -184,170 +184,170 @@ static rt_err_t rt_uart_init (rt_device_t dev)
 #endif
 
 #ifdef RT_USING_UART2
-	if( uart->UART == LPC_UART2 )
+    if( uart->UART == LPC_UART2 )
     {
     }
 #endif
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
 {
     struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
 
-	RT_ASSERT(dev != RT_NULL);
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* Enable the UART Interrupt */
-		NVIC_EnableIRQ( uart->UART_IRQn );
-	}
+    RT_ASSERT(dev != RT_NULL);
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* Enable the UART Interrupt */
+        NVIC_EnableIRQ( uart->UART_IRQn );
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_uart_close(rt_device_t dev)
 {
     struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
 
-	RT_ASSERT(dev != RT_NULL);
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* Disable the UART Interrupt */
-		NVIC_DisableIRQ( uart->UART_IRQn );
-	}
+    RT_ASSERT(dev != RT_NULL);
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* Disable the UART Interrupt */
+        NVIC_DisableIRQ( uart->UART_IRQn );
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
 {
-	rt_uint8_t* ptr;
-	struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
-	RT_ASSERT(uart != RT_NULL);
+    rt_uint8_t* ptr;
+    struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
+    RT_ASSERT(uart != RT_NULL);
 
-	/* point to buffer */
-	ptr = (rt_uint8_t*) buffer;
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		while (size)
-		{
-			/* interrupt receive */
-			rt_base_t level;
+    /* point to buffer */
+    ptr = (rt_uint8_t*) buffer;
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        while (size)
+        {
+            /* interrupt receive */
+            rt_base_t level;
 
-			/* disable interrupt */
-			level = rt_hw_interrupt_disable();
-			if (uart->read_index != uart->save_index)
-			{
-				*ptr = uart->rx_buffer[uart->read_index];
+            /* disable interrupt */
+            level = rt_hw_interrupt_disable();
+            if (uart->read_index != uart->save_index)
+            {
+                *ptr = uart->rx_buffer[uart->read_index];
 
-				uart->read_index ++;
-				if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
-					uart->read_index = 0;
-			}
-			else
-			{
-				/* no data in rx buffer */
+                uart->read_index ++;
+                if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
+                    uart->read_index = 0;
+            }
+            else
+            {
+                /* no data in rx buffer */
 
-				/* enable interrupt */
-				rt_hw_interrupt_enable(level);
-				break;
-			}
+                /* enable interrupt */
+                rt_hw_interrupt_enable(level);
+                break;
+            }
 
-			/* enable interrupt */
-			rt_hw_interrupt_enable(level);
+            /* enable interrupt */
+            rt_hw_interrupt_enable(level);
 
-			ptr ++;
-			size --;
-		}
+            ptr ++;
+            size --;
+        }
 
-		return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-	}
+        return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+    }
 
-	return 0;
+    return 0;
 }
 
 static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
 {
-	struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
-	char *ptr;
-	ptr = (char*)buffer;
+    struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
+    char *ptr;
+    ptr = (char*)buffer;
 
-	if (dev->flag & RT_DEVICE_FLAG_STREAM)
-	{
-		/* stream mode */
-		while (size)
-		{
-			if (*ptr == '\n')
-			{
-			    while (!(uart->UART->LSR & UART_LSR_THRE));
+    if (dev->flag & RT_DEVICE_FLAG_STREAM)
+    {
+        /* stream mode */
+        while (size)
+        {
+            if (*ptr == '\n')
+            {
+                while (!(uart->UART->LSR & UART_LSR_THRE));
                 UART_SendByte( uart->UART,'\r');
-			}
+            }
 
-			while (!(uart->UART->LSR & UART_LSR_THRE));
-			UART_SendByte( uart->UART,*ptr);
-			ptr ++;
-			size --;
-		}
-	}
-	else
-	{
+            while (!(uart->UART->LSR & UART_LSR_THRE));
+            UART_SendByte( uart->UART,*ptr);
+            ptr ++;
+            size --;
+        }
+    }
+    else
+    {
         UART_Send( uart->UART, (uint8_t *)buffer, size, BLOCKING);
     }
 
-	return (rt_size_t) ptr - (rt_size_t) buffer;
+    return (rt_size_t) ptr - (rt_size_t) buffer;
 }
 
 void rt_hw_uart_init(void)
 {
-	struct rt_uart_lpc* uart;
+    struct rt_uart_lpc* uart;
 
 #ifdef RT_USING_UART0
-	/* get uart device */
-	uart = &uart0_device;
-	uart0_device.UART = LPC_UART0;
-	uart0_device.UART_IRQn = UART0_IRQn;
+    /* get uart device */
+    uart = &uart0_device;
+    uart0_device.UART = LPC_UART0;
+    uart0_device.UART_IRQn = UART0_IRQn;
 
-	/* device initialization */
-	uart->parent.type = RT_Device_Class_Char;
-	rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
-	uart->read_index = uart->save_index = 0;
+    /* device initialization */
+    uart->parent.type = RT_Device_Class_Char;
+    rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
+    uart->read_index = uart->save_index = 0;
 
-	/* device interface */
-	uart->parent.init 	    = rt_uart_init;
-	uart->parent.open 	    = rt_uart_open;
-	uart->parent.close      = rt_uart_close;
-	uart->parent.read 	    = rt_uart_read;
-	uart->parent.write      = rt_uart_write;
-	uart->parent.control    = RT_NULL;
-	uart->parent.user_data  = RT_NULL;
+    /* device interface */
+    uart->parent.init       = rt_uart_init;
+    uart->parent.open       = rt_uart_open;
+    uart->parent.close      = rt_uart_close;
+    uart->parent.read       = rt_uart_read;
+    uart->parent.write      = rt_uart_write;
+    uart->parent.control    = RT_NULL;
+    uart->parent.user_data  = RT_NULL;
 
-	rt_device_register(&uart->parent,
-		"uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
+    rt_device_register(&uart->parent,
+        "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
 #endif
 
 #ifdef RT_USING_UART1
-	/* get uart device */
-	uart = &uart1_device;
-	uart1_device.UART = (LPC_UART_TypeDef *)LPC_UART1;
-	uart1_device.UART_IRQn = UART1_IRQn;
+    /* get uart device */
+    uart = &uart1_device;
+    uart1_device.UART = (LPC_UART_TypeDef *)LPC_UART1;
+    uart1_device.UART_IRQn = UART1_IRQn;
 
-	/* device initialization */
-	uart->parent.type = RT_Device_Class_Char;
-	rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
-	uart->read_index = uart->save_index = 0;
+    /* device initialization */
+    uart->parent.type = RT_Device_Class_Char;
+    rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
+    uart->read_index = uart->save_index = 0;
 
-	/* device interface */
-	uart->parent.init 	    = rt_uart_init;
-	uart->parent.open 	    = rt_uart_open;
-	uart->parent.close      = rt_uart_close;
-	uart->parent.read 	    = rt_uart_read;
-	uart->parent.write      = rt_uart_write;
-	uart->parent.control    = RT_NULL;
-	uart->parent.user_data  = RT_NULL;
+    /* device interface */
+    uart->parent.init       = rt_uart_init;
+    uart->parent.open       = rt_uart_open;
+    uart->parent.close      = rt_uart_close;
+    uart->parent.read       = rt_uart_read;
+    uart->parent.write      = rt_uart_write;
+    uart->parent.control    = RT_NULL;
+    uart->parent.user_data  = RT_NULL;
 
-	rt_device_register(&uart->parent,
-		"uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
+    rt_device_register(&uart->parent,
+        "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
 #endif
 }
 
diff --git a/bsp/lpc178x/rtconfig.h b/bsp/lpc178x/rtconfig.h
index 25f99888f7..ce51ba355f 100644
--- a/bsp/lpc178x/rtconfig.h
+++ b/bsp/lpc178x/rtconfig.h
@@ -5,17 +5,17 @@
 // 
 
 // 
-#define RT_NAME_MAX	6
+#define RT_NAME_MAX 6
 // 
-#define RT_ALIGN_SIZE	4
+#define RT_ALIGN_SIZE   4
 // 
 // 8
 // 32
 // 256
 // 
-#define RT_THREAD_PRIORITY_MAX	32
+#define RT_THREAD_PRIORITY_MAX  32
 // 
-#define RT_TICK_PER_SECOND	100
+#define RT_TICK_PER_SECOND  100
 // 

 #define RT_DEBUG
 #define RT_DEBUG_COLOR
@@ -30,11 +30,11 @@
 // 

 // #define RT_USING_TIMER_SOFT
 // 
-#define RT_TIMER_THREAD_PRIO	4
+#define RT_TIMER_THREAD_PRIO    4
 // 
-#define RT_TIMER_THREAD_STACK_SIZE	512
+#define RT_TIMER_THREAD_STACK_SIZE  512
 // 
-#define RT_TIMER_TICK_PER_SECOND	10
+#define RT_TIMER_TICK_PER_SECOND    10
 // 

 
 // 

@@ -66,13 +66,13 @@
 // 

 #define RT_USING_DEVICE
 // 
-#define RT_UART_RX_BUFFER_SIZE	64
+#define RT_UART_RX_BUFFER_SIZE  64
 // 

 
 // 

 #define RT_USING_CONSOLE
 // 
-#define RT_CONSOLEBUF_SIZE	128
+#define RT_CONSOLEBUF_SIZE  128
 // 

 
 // 
@@ -84,7 +84,7 @@
 // 
 #define FINSH_USING_DESCRIPTION
 // 
-#define FINSH_THREAD_STACK_SIZE	4096
+#define FINSH_THREAD_STACK_SIZE 4096
 // 

 
 // 

@@ -99,18 +99,18 @@
 // 
 // #define DFS_USING_WORKDIR
 // 
-#define DFS_FILESYSTEMS_MAX	2
+#define DFS_FILESYSTEMS_MAX 2
 // 
-#define DFS_FD_MAX	4
+#define DFS_FD_MAX  4
 // 
 #define RT_USING_DFS_ELMFAT
 // 
 // 1
 // 2
 // 
-#define RT_DFS_ELM_USE_LFN	1
+#define RT_DFS_ELM_USE_LFN  1
 // 
-#define RT_DFS_ELM_MAX_LFN	64
+#define RT_DFS_ELM_MAX_LFN  64
 // 
 // #define RT_USING_DFS_YAFFS2
 // 
@@ -120,7 +120,7 @@
 // 
 // #define RT_USING_DFS_NFS
 // 
-#define RT_NFS_HOST_EXPORT	"192.168.1.5:/"
+#define RT_NFS_HOST_EXPORT  "192.168.1.5:/"
 // 

 
 // 

@@ -136,31 +136,31 @@
 // 
 #define RT_LWIP_DNS
 // 
-#define RT_LWIP_PBUF_NUM	4
+#define RT_LWIP_PBUF_NUM    4
 // 
-#define RT_LWIP_TCP_PCB_NUM	3
+#define RT_LWIP_TCP_PCB_NUM 3
 // 
-#define RT_LWIP_TCP_SND_BUF	2048
+#define RT_LWIP_TCP_SND_BUF 2048
 // 
-#define RT_LWIP_TCP_WND	2048
+#define RT_LWIP_TCP_WND 2048
 // 
 // #define RT_LWIP_SNMP
 // 
 // #define RT_LWIP_DHCP
 // 
-#define RT_LWIP_TCP_SEG_NUM	4
+#define RT_LWIP_TCP_SEG_NUM 4
 // 
-#define RT_LWIP_TCPTHREAD_PRIORITY	12
+#define RT_LWIP_TCPTHREAD_PRIORITY  12
 // 
-#define RT_LWIP_TCPTHREAD_MBOX_SIZE	8
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
 // 
-#define RT_LWIP_TCPTHREAD_STACKSIZE	4096
+#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
 // 
-#define RT_LWIP_ETHTHREAD_PRIORITY	14
+#define RT_LWIP_ETHTHREAD_PRIORITY  14
 // 
-#define RT_LWIP_ETHTHREAD_MBOX_SIZE	8
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
 // 
-#define RT_LWIP_ETHTHREAD_STACKSIZE	512
+#define RT_LWIP_ETHTHREAD_STACKSIZE 512
 // 
 #define RT_LWIP_IPADDR0 192
 #define RT_LWIP_IPADDR1 168
@@ -181,7 +181,7 @@
 // 

 // #define RT_USING_RTGUI
 // 
-#define RTGUI_NAME_MAX	12
+#define RTGUI_NAME_MAX  12
 // 
 #define RTGUI_USING_SMALL_SIZE
 // 
@@ -191,7 +191,7 @@
 // 
 #define RTGUI_USING_FONTHZ
 // 
-#define RTGUI_DEFAULT_FONT_SIZE	16
+#define RTGUI_DEFAULT_FONT_SIZE 16
 // 
 // #define RTGUI_USING_DFS_FILERW
 // 
diff --git a/bsp/lpc2148/applications/application.c b/bsp/lpc2148/applications/application.c
index fd07f22f05..731b30a510 100644
--- a/bsp/lpc2148/applications/application.c
+++ b/bsp/lpc2148/applications/application.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc2148/applications/startup.c b/bsp/lpc2148/applications/startup.c
index cc16a5c12b..a3229083ac 100644
--- a/bsp/lpc2148/applications/startup.c
+++ b/bsp/lpc2148/applications/startup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc2148/drivers/board.c b/bsp/lpc2148/drivers/board.c
index 96a4aa62f4..757e1cb8f0 100644
--- a/bsp/lpc2148/drivers/board.c
+++ b/bsp/lpc2148/drivers/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -25,13 +25,13 @@
  */
 void rt_hw_timer_handler(int vector, void *param)
 {
-	rt_tick_increase();
+    rt_tick_increase();
 
-	/* clear interrupt flag */
-	T0IR |= 0x01;
+    /* clear interrupt flag */
+    T0IR |= 0x01;
 
-	/* acknowledge Interrupt */
-	VICVectAddr = 0;
+    /* acknowledge Interrupt */
+    VICVectAddr = 0;
 }
 
 /**
@@ -42,37 +42,37 @@ void rt_hw_timer_handler(int vector, void *param)
  */
 void rt_hw_console_output(const char* str)
 {
-	while (*str)
-	{
-		if (*str=='\n')
-		{
-			while (!(U0LSR & 0x20));
-			U0THR = '\r';
-		}
+    while (*str)
+    {
+        if (*str=='\n')
+        {
+            while (!(U0LSR & 0x20));
+            U0THR = '\r';
+        }
 
-		while (!(U0LSR & 0x20));
-		U0THR = *str;
+        while (!(U0LSR & 0x20));
+        U0THR = *str;
 
-		str ++;
-	}
+        str ++;
+    }
 }
 
-#define BAUD_RATE	115200
-#define U0PINS		0x05
+#define BAUD_RATE   115200
+#define U0PINS      0x05
 void rt_hw_console_init()
 {
-	/* Enable RxD and TxD pins */
-  	PINSEL0 = U0PINS;
+    /* Enable RxD and TxD pins */
+    PINSEL0 = U0PINS;
 
-	/* 8 bits, no Parity, 1 Stop bit */
-	U0LCR = 0x83;
+    /* 8 bits, no Parity, 1 Stop bit */
+    U0LCR = 0x83;
 
-	/* Setup Baudrate */
-	U0DLL = (PCLK/16/BAUD_RATE) & 0xFF;
-	U0DLM = ((PCLK/16/BAUD_RATE) >> 8) & 0xFF;
+    /* Setup Baudrate */
+    U0DLL = (PCLK/16/BAUD_RATE) & 0xFF;
+    U0DLM = ((PCLK/16/BAUD_RATE) >> 8) & 0xFF;
 
-	/* DLAB = 0 */
-	U0LCR = 0x03;
+    /* DLAB = 0 */
+    U0LCR = 0x03;
 }
 
 /**
@@ -80,23 +80,23 @@ void rt_hw_console_init()
  */
 void rt_hw_board_init(void)
 {
-	/* console init */
-	rt_hw_console_init();
+    /* console init */
+    rt_hw_console_init();
 
-	/* prescaler = 0*/
-   	T0PR = 0;
-   	T0PC = 0;
+    /* prescaler = 0*/
+    T0PR = 0;
+    T0PC = 0;
 
-	/* reset and enable MR0 interrupt */
-	T0MCR = 0x3;
-	T0MR0 = PCLK / RT_TICK_PER_SECOND;
+    /* reset and enable MR0 interrupt */
+    T0MCR = 0x3;
+    T0MR0 = PCLK / RT_TICK_PER_SECOND;
 
-	/* enable timer 0 */
-	T0TCR = 1;
+    /* enable timer 0 */
+    T0TCR = 1;
 
-	/* install timer handler */
-	rt_hw_interrupt_install(TIMER0_INT, rt_hw_timer_handler, RT_NULL, "TIMER0");
-	rt_hw_interrupt_umask(TIMER0_INT);
+    /* install timer handler */
+    rt_hw_interrupt_install(TIMER0_INT, rt_hw_timer_handler, RT_NULL, "TIMER0");
+    rt_hw_interrupt_umask(TIMER0_INT);
 }
 
 /*@}*/
diff --git a/bsp/lpc2148/drivers/board.h b/bsp/lpc2148/drivers/board.h
index 346f10182f..957f360652 100644
--- a/bsp/lpc2148/drivers/board.h
+++ b/bsp/lpc2148/drivers/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -12,13 +12,13 @@
 #define __BOARD_H__
 #include 
 
-#define CCLK	60000000	/* Fosc = 12MHz, M = 5 */
-#define PCLK	15000000	/* CCLK/4, use default */
+#define CCLK    60000000    /* Fosc = 12MHz, M = 5 */
+#define PCLK    15000000    /* CCLK/4, use default */
 
 /* RT_USING_UART */
 #define RT_USING_UART1
 #define RT_USING_UART2
-#define RT_UART_RX_BUFFER_SIZE	64
+#define RT_UART_RX_BUFFER_SIZE  64
 
 void rt_hw_board_init(void);
 
diff --git a/bsp/lpc2148/drivers/dm9000.c b/bsp/lpc2148/drivers/dm9000.c
index 169be59f12..9bc8d445f9 100644
--- a/bsp/lpc2148/drivers/dm9000.c
+++ b/bsp/lpc2148/drivers/dm9000.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,11 +15,11 @@
 #define MAX_ADDR_LEN 6
 struct rt_dm9000_eth
 {
-	/* inherit from ethernet device */
-	struct eth_device parent;
+    /* inherit from ethernet device */
+    struct eth_device parent;
 
-	/* interface address info. */
-	rt_uint8_t  dev_addr[MAX_ADDR_LEN];			/* hw address	*/
+    /* interface address info. */
+    rt_uint8_t  dev_addr[MAX_ADDR_LEN];         /* hw address   */
 };
 static struct rt_dm9000_eth dm9000_device;
 
@@ -52,67 +52,67 @@ static rt_err_t rt_dm9000_init(rt_device_t dev)
 
 static rt_err_t rt_dm9000_open(rt_device_t dev, rt_uint16_t oflag)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_dm9000_close(rt_device_t dev)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_size_t rt_dm9000_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
 {
-	rt_set_errno(-RT_ENOSYS);
-	return 0;
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
 }
 
 static rt_size_t rt_dm9000_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
 {
-	rt_set_errno(-RT_ENOSYS);
-	return 0;
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
 }
 
 static rt_err_t rt_dm9000_control(rt_device_t dev, int cmd, void *args)
 {
-	switch(cmd)
-	{
-	case NIOCTL_GADDR:
-		/* get mac address */
-		if(args) rt_memcpy(args, dm9000_device.dev_addr, 6);
-		else return -RT_ERROR;
-		break;
+    switch(cmd)
+    {
+    case NIOCTL_GADDR:
+        /* get mac address */
+        if(args) rt_memcpy(args, dm9000_device.dev_addr, 6);
+        else return -RT_ERROR;
+        break;
 
-	default :
-		break;
-	}
+    default :
+        break;
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 /* ethernet device interface */
 /* transmit packet. */
 rt_err_t rt_dm9000_tx( rt_device_t dev, struct pbuf* p)
 {
-	struct pbuf* q;
-	rt_uint32_t len;
-	rt_uint8_t* ptr;
+    struct pbuf* q;
+    rt_uint32_t len;
+    rt_uint8_t* ptr;
 
-	for (q = p; q != NULL; q = q->next)
-	{
-		len = q->len;
-		ptr = q->payload;
+    for (q = p; q != NULL; q = q->next)
+    {
+        len = q->len;
+        ptr = q->payload;
 
-		/* write data to device */
-	}
+        /* write data to device */
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 /* reception packet. */
 struct pbuf *rt_dm9000_rx(rt_device_t dev)
 {
     struct pbuf* p;
-	rt_uint32_t len;
+    rt_uint32_t len;
 
     /* init p pointer */
     p = RT_NULL;
@@ -149,17 +149,17 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev)
 
 void rt_hw_dm9000_init()
 {
-	dm9000_device.parent.parent.init       = rt_dm9000_init;
-	dm9000_device.parent.parent.open       = rt_dm9000_open;
-	dm9000_device.parent.parent.close      = rt_dm9000_close;
-	dm9000_device.parent.parent.read       = rt_dm9000_read;
-	dm9000_device.parent.parent.write      = rt_dm9000_write;
-	dm9000_device.parent.parent.control    = rt_dm9000_control;
-	dm9000_device.parent.parent.user_data  = RT_NULL;
+    dm9000_device.parent.parent.init       = rt_dm9000_init;
+    dm9000_device.parent.parent.open       = rt_dm9000_open;
+    dm9000_device.parent.parent.close      = rt_dm9000_close;
+    dm9000_device.parent.parent.read       = rt_dm9000_read;
+    dm9000_device.parent.parent.write      = rt_dm9000_write;
+    dm9000_device.parent.parent.control    = rt_dm9000_control;
+    dm9000_device.parent.parent.user_data  = RT_NULL;
 
-	dm9000_device.parent.eth_rx     = rt_dm9000_rx;
-	dm9000_device.parent.eth_tx     = rt_dm9000_tx;
+    dm9000_device.parent.eth_rx     = rt_dm9000_rx;
+    dm9000_device.parent.eth_tx     = rt_dm9000_tx;
 
-	rt_device_register((rt_device_t)&dm9000_device,
-		"E0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_INT_TX);
+    rt_device_register((rt_device_t)&dm9000_device,
+        "E0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_INT_TX);
 }
diff --git a/bsp/lpc2148/drivers/sd.c b/bsp/lpc2148/drivers/sd.c
index d7b6769621..144c9f2ff5 100644
--- a/bsp/lpc2148/drivers/sd.c
+++ b/bsp/lpc2148/drivers/sd.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -22,12 +22,12 @@ static rt_err_t rt_sdcard_init(rt_device_t dev)
 
 static rt_err_t rt_sdcard_open(rt_device_t dev, rt_uint16_t oflag)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_sdcard_close(rt_device_t dev)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_size_t rt_sdcard_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
@@ -48,54 +48,54 @@ static rt_size_t rt_sdcard_write (rt_device_t dev, rt_off_t pos, const void* buf
 
 static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 void rt_hw_sdcard_init()
 {
     rt_size_t length;
-	rt_uint8_t* sector;
+    rt_uint8_t* sector;
 
     /* sdcard hardware init */
 
-	sd.type     = RT_Device_Class_Block;
-	sd.init 	= rt_sdcard_init;
-	sd.open 	= rt_sdcard_open;
-	sd.close    = rt_sdcard_close;
-	sd.read 	= rt_sdcard_read;
-	sd.write    = rt_sdcard_write;
-	sd.control  = rt_sdcard_control;
-	sd.user_data  = RT_NULL;
+    sd.type     = RT_Device_Class_Block;
+    sd.init     = rt_sdcard_init;
+    sd.open     = rt_sdcard_open;
+    sd.close    = rt_sdcard_close;
+    sd.read     = rt_sdcard_read;
+    sd.write    = rt_sdcard_write;
+    sd.control  = rt_sdcard_control;
+    sd.user_data  = RT_NULL;
 
-	/* get the first sector to read partition table */
-	sector = (rt_uint8_t*) rt_malloc (512);
-	if (sector == RT_NULL)
-	{
-		rt_kprintf("allocate partition sector buffer failed\n");
-		return;
-	}
+    /* get the first sector to read partition table */
+    sector = (rt_uint8_t*) rt_malloc (512);
+    if (sector == RT_NULL)
+    {
+        rt_kprintf("allocate partition sector buffer failed\n");
+        return;
+    }
 
-	length = rt_sdcard_read((rt_device_t)&sd, 0, sector, 512);
-	if (length == 512)
-	{
-		rt_err_t status;
+    length = rt_sdcard_read((rt_device_t)&sd, 0, sector, 512);
+    if (length == 512)
+    {
+        rt_err_t status;
 
-		/* get the first partition */
-		status = dfs_filesystem_get_partition(&part, sector, 0);
-		if (status != RT_EOK)
-		{
-			/* there is no partition table */
-			part.offset = 0;
-			part.size   = 0;
-		}
-	}
-	else
-	{
-		/* there is no partition table */
-		part.offset = 0;
-		part.size   = 0;
-	}
+        /* get the first partition */
+        status = dfs_filesystem_get_partition(&part, sector, 0);
+        if (status != RT_EOK)
+        {
+            /* there is no partition table */
+            part.offset = 0;
+            part.size   = 0;
+        }
+    }
+    else
+    {
+        /* there is no partition table */
+        part.offset = 0;
+        part.size   = 0;
+    }
 
-	rt_device_register(&sd,
-		"sd", RT_DEVICE_FLAG_RDWR);
+    rt_device_register(&sd,
+        "sd", RT_DEVICE_FLAG_RDWR);
 }
diff --git a/bsp/lpc2148/drivers/serial.c b/bsp/lpc2148/drivers/serial.c
index 0c78ecc026..36bbcbd608 100644
--- a/bsp/lpc2148/drivers/serial.c
+++ b/bsp/lpc2148/drivers/serial.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,8 +15,8 @@
 #include "board.h"
 
 /* serial hardware register */
-#define REG8(d)			(*((volatile unsigned char *)(d)))
-#define REG32(d)		(*((volatile unsigned long *)(d)))
+#define REG8(d)         (*((volatile unsigned char *)(d)))
+#define REG32(d)        (*((volatile unsigned long *)(d)))
 
 #define UART_RBR(base)  REG8(base + 0x00)
 #define UART_THR(base)  REG8(base + 0x00)
@@ -37,16 +37,16 @@
 /* LPC serial device */
 struct rt_lpcserial
 {
-	/* inherit from device */
-	struct rt_device parent;
+    /* inherit from device */
+    struct rt_device parent;
 
-	rt_uint32_t hw_base;
-	rt_uint32_t irqno;
-	rt_uint32_t baudrate;
+    rt_uint32_t hw_base;
+    rt_uint32_t irqno;
+    rt_uint32_t baudrate;
 
-	/* reception field */
-	rt_uint16_t save_index, read_index;
-	rt_uint8_t  rx_buffer[RT_UART_RX_BUFFER_SIZE];
+    /* reception field */
+    rt_uint16_t save_index, read_index;
+    rt_uint8_t  rx_buffer[RT_UART_RX_BUFFER_SIZE];
 };
 
 #ifdef RT_USING_UART1
@@ -58,70 +58,70 @@ struct rt_lpcserial serial2;
 
 void rt_hw_serial_init(void);
 
-#define U0PINS  	0x00000005
+#define U0PINS      0x00000005
 
 void rt_hw_uart_isr(struct rt_lpcserial* lpc_serial)
 {
-	RT_UNUSED rt_uint32_t iir;
+    RT_UNUSED rt_uint32_t iir;
 
-	RT_ASSERT(lpc_serial != RT_NULL)
+    RT_ASSERT(lpc_serial != RT_NULL)
 
-	if (UART_LSR(lpc_serial->hw_base) & 0x01)
-	{
-		rt_base_t level;
+    if (UART_LSR(lpc_serial->hw_base) & 0x01)
+    {
+        rt_base_t level;
 
-		while (UART_LSR(lpc_serial->hw_base) & 0x01)
-		{
-			/* disable interrupt */
-			level = rt_hw_interrupt_disable();
+        while (UART_LSR(lpc_serial->hw_base) & 0x01)
+        {
+            /* disable interrupt */
+            level = rt_hw_interrupt_disable();
 
-			/* read character */
-			lpc_serial->rx_buffer[lpc_serial->save_index] =
-				UART_RBR(lpc_serial->hw_base);
-			lpc_serial->save_index ++;
-			if (lpc_serial->save_index >= RT_UART_RX_BUFFER_SIZE)
-				lpc_serial->save_index = 0;
+            /* read character */
+            lpc_serial->rx_buffer[lpc_serial->save_index] =
+                UART_RBR(lpc_serial->hw_base);
+            lpc_serial->save_index ++;
+            if (lpc_serial->save_index >= RT_UART_RX_BUFFER_SIZE)
+                lpc_serial->save_index = 0;
 
-			/* if the next position is read index, discard this 'read char' */
-			if (lpc_serial->save_index == lpc_serial->read_index)
-			{
-				lpc_serial->read_index ++;
-				if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
-					lpc_serial->read_index = 0;
-			}
+            /* if the next position is read index, discard this 'read char' */
+            if (lpc_serial->save_index == lpc_serial->read_index)
+            {
+                lpc_serial->read_index ++;
+                if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
+                    lpc_serial->read_index = 0;
+            }
 
-			/* enable interrupt */
-			rt_hw_interrupt_enable(level);
-		}
+            /* enable interrupt */
+            rt_hw_interrupt_enable(level);
+        }
 
-		/* invoke callback */
-		if(lpc_serial->parent.rx_indicate != RT_NULL)
-		{
-		  lpc_serial->parent.rx_indicate(&lpc_serial->parent, 1);
-		}
-	}
+        /* invoke callback */
+        if(lpc_serial->parent.rx_indicate != RT_NULL)
+        {
+          lpc_serial->parent.rx_indicate(&lpc_serial->parent, 1);
+        }
+    }
 
-	/* clear interrupt source */
-	iir = UART_IIR(lpc_serial->hw_base);
+    /* clear interrupt source */
+    iir = UART_IIR(lpc_serial->hw_base);
 
-	/* acknowledge Interrupt */
-	VICVectAddr = 0;
+    /* acknowledge Interrupt */
+    VICVectAddr = 0;
 }
 
 #ifdef RT_USING_UART1
 void rt_hw_uart_isr_1(int irqno, void *param)
 {
-	/* get lpc serial device */
-	rt_hw_uart_isr(&serial1);
-}	
+    /* get lpc serial device */
+    rt_hw_uart_isr(&serial1);
+}
 #endif
 
 #ifdef RT_USING_UART2
 void rt_hw_uart_isr_2(int irqno, void *param)
 {
-	/* get lpc serial device */
-	rt_hw_uart_isr(&serial2);
-}	
+    /* get lpc serial device */
+    rt_hw_uart_isr(&serial2);
+}
 #endif
 
 /**
@@ -131,256 +131,256 @@ void rt_hw_uart_isr_2(int irqno, void *param)
 
 static rt_err_t rt_serial_init (rt_device_t dev)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
 {
-	struct rt_lpcserial* lpc_serial;
-	lpc_serial = (struct rt_lpcserial*) dev;
-	
-	RT_ASSERT(lpc_serial != RT_NULL);
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-	    /* init UART rx interrupt */
-    	UART_IER(lpc_serial->hw_base) = 0x01;
+    struct rt_lpcserial* lpc_serial;
+    lpc_serial = (struct rt_lpcserial*) dev;
 
-		/* install ISR */
-		if (lpc_serial->irqno == UART0_INT)
-		{
+    RT_ASSERT(lpc_serial != RT_NULL);
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* init UART rx interrupt */
+        UART_IER(lpc_serial->hw_base) = 0x01;
+
+        /* install ISR */
+        if (lpc_serial->irqno == UART0_INT)
+        {
 #ifdef RT_USING_UART1
-		    rt_hw_interrupt_install(lpc_serial->irqno,
+            rt_hw_interrupt_install(lpc_serial->irqno,
                               rt_hw_uart_isr_1, &serial1, "UART1");
 #endif
-		}
-		else
-		{
+        }
+        else
+        {
 #ifdef RT_USING_UART2
-		    rt_hw_interrupt_install(lpc_serial->irqno,
+            rt_hw_interrupt_install(lpc_serial->irqno,
                               rt_hw_uart_isr_2, &serial2, "UART2");
 #endif
-		}
+        }
 
-	    rt_hw_interrupt_umask(lpc_serial->irqno);
-	}
+        rt_hw_interrupt_umask(lpc_serial->irqno);
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_serial_close(rt_device_t dev)
 {
-	struct rt_lpcserial* lpc_serial;
-	lpc_serial = (struct rt_lpcserial*) dev;
+    struct rt_lpcserial* lpc_serial;
+    lpc_serial = (struct rt_lpcserial*) dev;
 
-	RT_ASSERT(lpc_serial != RT_NULL);
+    RT_ASSERT(lpc_serial != RT_NULL);
 
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* disable UART rx interrupt */
-		UART_IER(lpc_serial->hw_base) = 0x00;
-	}
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* disable UART rx interrupt */
+        UART_IER(lpc_serial->hw_base) = 0x00;
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_serial_control(rt_device_t dev, int cmd, void *args)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
 {
-	rt_uint8_t* ptr;
-	struct rt_lpcserial *lpc_serial = (struct rt_lpcserial*)dev;
-	RT_ASSERT(lpc_serial != RT_NULL);
+    rt_uint8_t* ptr;
+    struct rt_lpcserial *lpc_serial = (struct rt_lpcserial*)dev;
+    RT_ASSERT(lpc_serial != RT_NULL);
 
-	/* point to buffer */
-	ptr = (rt_uint8_t*) buffer;
+    /* point to buffer */
+    ptr = (rt_uint8_t*) buffer;
 
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		while (size)
-		{
-			/* interrupt receive */
-			rt_base_t level;
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        while (size)
+        {
+            /* interrupt receive */
+            rt_base_t level;
 
-			/* disable interrupt */
-			level = rt_hw_interrupt_disable();
-			if (lpc_serial->read_index != lpc_serial->save_index)
-			{
-				*ptr = lpc_serial->rx_buffer[lpc_serial->read_index];
+            /* disable interrupt */
+            level = rt_hw_interrupt_disable();
+            if (lpc_serial->read_index != lpc_serial->save_index)
+            {
+                *ptr = lpc_serial->rx_buffer[lpc_serial->read_index];
 
-				lpc_serial->read_index ++;
-				if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
-					lpc_serial->read_index = 0;
-			}
-			else
-			{
-				/* no data in rx buffer */
+                lpc_serial->read_index ++;
+                if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
+                    lpc_serial->read_index = 0;
+            }
+            else
+            {
+                /* no data in rx buffer */
 
-				/* enable interrupt */
-				rt_hw_interrupt_enable(level);
-				break;
-			}
+                /* enable interrupt */
+                rt_hw_interrupt_enable(level);
+                break;
+            }
 
-			/* enable interrupt */
-			rt_hw_interrupt_enable(level);
+            /* enable interrupt */
+            rt_hw_interrupt_enable(level);
 
-			ptr ++; size --;
-		}
+            ptr ++; size --;
+        }
 
-		return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-	}
-	else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
-	{
-		/* not support right now */
-		RT_ASSERT(0);
-	}
+        return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+    }
+    else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
+    {
+        /* not support right now */
+        RT_ASSERT(0);
+    }
 
-	/* polling mode */
-	while (size && (UART_LSR(lpc_serial->hw_base) & 0x01))
-	{
-		/* Read Character */
-		*ptr = UART_RBR(lpc_serial->hw_base);
+    /* polling mode */
+    while (size && (UART_LSR(lpc_serial->hw_base) & 0x01))
+    {
+        /* Read Character */
+        *ptr = UART_RBR(lpc_serial->hw_base);
 
-		ptr  ++;
-		size --;
-	}
+        ptr  ++;
+        size --;
+    }
 
-	return (rt_size_t)ptr - (rt_size_t)buffer;
+    return (rt_size_t)ptr - (rt_size_t)buffer;
 }
 
 static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
 {
-	struct rt_lpcserial* lpc_serial;
-	char *ptr;
+    struct rt_lpcserial* lpc_serial;
+    char *ptr;
 
-	lpc_serial = (struct rt_lpcserial*) dev;
-	if (dev->flag & RT_DEVICE_FLAG_INT_TX)
-	{
-		/* not support */
-		RT_ASSERT(0);
-	}
-	else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
-	{
-		/* not support */
-		RT_ASSERT(0);
-	}
+    lpc_serial = (struct rt_lpcserial*) dev;
+    if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+    {
+        /* not support */
+        RT_ASSERT(0);
+    }
+    else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
+    {
+        /* not support */
+        RT_ASSERT(0);
+    }
 
-	/* polling write */
-	ptr = (char *)buffer;
+    /* polling write */
+    ptr = (char *)buffer;
 
-	if (dev->flag & RT_DEVICE_FLAG_STREAM)
-	{
-		/* stream mode */
-		while (size)
-		{
-			if (*ptr == '\n')
-			{
-				while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
-				UART_THR(lpc_serial->hw_base) = '\r';
-			}
+    if (dev->flag & RT_DEVICE_FLAG_STREAM)
+    {
+        /* stream mode */
+        while (size)
+        {
+            if (*ptr == '\n')
+            {
+                while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
+                UART_THR(lpc_serial->hw_base) = '\r';
+            }
 
-			while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
-			UART_THR(lpc_serial->hw_base) = *ptr;
+            while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
+            UART_THR(lpc_serial->hw_base) = *ptr;
 
-			ptr ++;
-			size --;
-		}
-	}
-	else
-	{
-		while (size)
-		{
-			while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
-			UART_THR(lpc_serial->hw_base) = *ptr;
+            ptr ++;
+            size --;
+        }
+    }
+    else
+    {
+        while (size)
+        {
+            while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
+            UART_THR(lpc_serial->hw_base) = *ptr;
 
-			ptr ++;
-			size --;
-		}
-	}
+            ptr ++;
+            size --;
+        }
+    }
 
-	return (rt_size_t) ptr - (rt_size_t) buffer;
+    return (rt_size_t) ptr - (rt_size_t) buffer;
 }
 
 void rt_hw_serial_init(void)
 {
-	struct rt_lpcserial* lpc_serial;
+    struct rt_lpcserial* lpc_serial;
 
 #ifdef RT_USING_UART1
-	lpc_serial = &serial1;
+    lpc_serial = &serial1;
 
-	lpc_serial->parent.type = RT_Device_Class_Char;
+    lpc_serial->parent.type = RT_Device_Class_Char;
 
-	lpc_serial->hw_base = 0xE000C000;
-	lpc_serial->baudrate = 115200;
-	lpc_serial->irqno = UART0_INT;
+    lpc_serial->hw_base = 0xE000C000;
+    lpc_serial->baudrate = 115200;
+    lpc_serial->irqno = UART0_INT;
 
-	rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
-	lpc_serial->read_index = lpc_serial->save_index = 0;
+    rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
+    lpc_serial->read_index = lpc_serial->save_index = 0;
 
-	/* Enable UART0 RxD and TxD pins */
+    /* Enable UART0 RxD and TxD pins */
     PINSEL0 |= 0x05;
 
-	/* 8 bits, no Parity, 1 Stop bit */
-	UART_LCR(lpc_serial->hw_base) = 0x83;
+    /* 8 bits, no Parity, 1 Stop bit */
+    UART_LCR(lpc_serial->hw_base) = 0x83;
 
-	/* Setup Baudrate */
-	UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
-	UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
+    /* Setup Baudrate */
+    UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
+    UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
 
-	/* DLAB = 0 */
-	UART_LCR(lpc_serial->hw_base) = 0x03;
+    /* DLAB = 0 */
+    UART_LCR(lpc_serial->hw_base) = 0x03;
 
-	lpc_serial->parent.type     = RT_Device_Class_Char;
-	lpc_serial->parent.init 	= rt_serial_init;
-	lpc_serial->parent.open 	= rt_serial_open;
-	lpc_serial->parent.close    = rt_serial_close;
-	lpc_serial->parent.read 	= rt_serial_read;
-	lpc_serial->parent.write    = rt_serial_write;
-	lpc_serial->parent.control  = rt_serial_control;
-	lpc_serial->parent.user_data  = RT_NULL;
+    lpc_serial->parent.type     = RT_Device_Class_Char;
+    lpc_serial->parent.init     = rt_serial_init;
+    lpc_serial->parent.open     = rt_serial_open;
+    lpc_serial->parent.close    = rt_serial_close;
+    lpc_serial->parent.read     = rt_serial_read;
+    lpc_serial->parent.write    = rt_serial_write;
+    lpc_serial->parent.control  = rt_serial_control;
+    lpc_serial->parent.user_data  = RT_NULL;
 
-	rt_device_register(&lpc_serial->parent,
-		"uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
+    rt_device_register(&lpc_serial->parent,
+        "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
 #endif
 
 #ifdef RT_USING_UART2
-	lpc_serial = &serial2;
+    lpc_serial = &serial2;
 
-	lpc_serial->parent.type = RT_Device_Class_Char;
+    lpc_serial->parent.type = RT_Device_Class_Char;
 
-	lpc_serial->hw_base = 0xE0010000;
-	lpc_serial->baudrate = 115200;
-	lpc_serial->irqno = UART1_INT;
+    lpc_serial->hw_base = 0xE0010000;
+    lpc_serial->baudrate = 115200;
+    lpc_serial->irqno = UART1_INT;
 
-	rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
-	lpc_serial->read_index = lpc_serial->save_index = 0;
+    rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
+    lpc_serial->read_index = lpc_serial->save_index = 0;
 
-	/* Enable UART1 RxD and TxD pins */
-  	PINSEL0 |= 0x05 << 16;
+    /* Enable UART1 RxD and TxD pins */
+    PINSEL0 |= 0x05 << 16;
 
-	/* 8 bits, no Parity, 1 Stop bit */
-	UART_LCR(lpc_serial->hw_base) = 0x83;
+    /* 8 bits, no Parity, 1 Stop bit */
+    UART_LCR(lpc_serial->hw_base) = 0x83;
 
-	/* Setup Baudrate */
-	UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
-	UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
+    /* Setup Baudrate */
+    UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
+    UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
 
-	/* DLAB = 0 */
-	UART_LCR(lpc_serial->hw_base) = 0x03;
+    /* DLAB = 0 */
+    UART_LCR(lpc_serial->hw_base) = 0x03;
 
-	lpc_serial->parent.type     = RT_Device_Class_Char;
-	lpc_serial->parent.init 	= rt_serial_init;
-	lpc_serial->parent.open 	= rt_serial_open;
-	lpc_serial->parent.close    = rt_serial_close;
-	lpc_serial->parent.read 	= rt_serial_read;
-	lpc_serial->parent.write    = rt_serial_write;
-	lpc_serial->parent.control  = rt_serial_control;
-	lpc_serial->parent.user_data  = RT_NULL;
+    lpc_serial->parent.type     = RT_Device_Class_Char;
+    lpc_serial->parent.init     = rt_serial_init;
+    lpc_serial->parent.open     = rt_serial_open;
+    lpc_serial->parent.close    = rt_serial_close;
+    lpc_serial->parent.read     = rt_serial_read;
+    lpc_serial->parent.write    = rt_serial_write;
+    lpc_serial->parent.control  = rt_serial_control;
+    lpc_serial->parent.user_data  = RT_NULL;
 
-	rt_device_register(&lpc_serial->parent,
-		"uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
+    rt_device_register(&lpc_serial->parent,
+        "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
 #endif
 }
 
diff --git a/bsp/lpc2148/rtconfig.h b/bsp/lpc2148/rtconfig.h
index 70a6ef0325..220742ce41 100644
--- a/bsp/lpc2148/rtconfig.h
+++ b/bsp/lpc2148/rtconfig.h
@@ -3,16 +3,16 @@
 #define __RTTHREAD_CFG_H__
 
 /* RT_NAME_MAX*/
-#define RT_NAME_MAX	8
+#define RT_NAME_MAX 8
 
 /* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE	4
+#define RT_ALIGN_SIZE   4
 
 /* PRIORITY_MAX*/
-#define RT_THREAD_PRIORITY_MAX	32
+#define RT_THREAD_PRIORITY_MAX  32
 
 /* Tick per Second*/
-#define RT_TICK_PER_SECOND	100
+#define RT_TICK_PER_SECOND  100
 
 /* SECTION: RT_DEBUG */
 /* Thread Debug */
@@ -62,12 +62,12 @@
 #define RT_USING_DEVICE
 #define RT_USING_UART1
 #define RT_USING_UART2
-#define RT_UART_RX_BUFFER_SIZE	64
+#define RT_UART_RX_BUFFER_SIZE  64
 
 /* SECTION: Console options */
 #define RT_USING_CONSOLE
 /* the buffer size of console*/
-#define RT_CONSOLEBUF_SIZE	128
+#define RT_CONSOLEBUF_SIZE  128
 
 /* SECTION: FinSH shell options */
 /* Using FinSH as Shell*/
@@ -80,10 +80,6 @@
 /* Using QEMU or SkyEye*/
 /* #define RT_USING_EMULATOR */
 
-/* SECTION: a mini libc */
-/* Using mini libc library*/
-/* #define RT_USING_MINILIBC */
-
 /* SECTION: C++ support */
 /* Using C++ support*/
 /* #define RT_USING_CPLUSPLUS */
@@ -91,11 +87,11 @@
 /* SECTION: DFS options */
 /* #define RT_USING_DFS */
 /* the max number of mounted filesystem */
-#define DFS_FILESYSTEMS_MAX			2
-/* the max number of opened files 		*/
-#define DFS_FD_MAX					4
-/* the max number of cached sector 		*/
-#define DFS_CACHE_MAX_NUM   		8
+#define DFS_FILESYSTEMS_MAX         2
+/* the max number of opened files       */
+#define DFS_FD_MAX                  4
+/* the max number of cached sector      */
+#define DFS_CACHE_MAX_NUM           8
 
 /* SECTION: lwip, a lighwight TCP/IP protocol stack */
 /* Using lighweight TCP/IP protocol stack*/
@@ -123,21 +119,21 @@
 /* #define RT_LWIP_DHCP */
 
 /* ip address of target*/
-#define RT_LWIP_IPADDR0	192
-#define RT_LWIP_IPADDR1	168
-#define RT_LWIP_IPADDR2	0
-#define RT_LWIP_IPADDR3	30
+#define RT_LWIP_IPADDR0 192
+#define RT_LWIP_IPADDR1 168
+#define RT_LWIP_IPADDR2 0
+#define RT_LWIP_IPADDR3 30
 
 /* gateway address of target*/
-#define RT_LWIP_GWADDR0	192
-#define RT_LWIP_GWADDR1	168
-#define RT_LWIP_GWADDR2	0
-#define RT_LWIP_GWADDR3	1
+#define RT_LWIP_GWADDR0 192
+#define RT_LWIP_GWADDR1 168
+#define RT_LWIP_GWADDR2 0
+#define RT_LWIP_GWADDR3 1
 
 /* mask address of target*/
-#define RT_LWIP_MSKADDR0	255
-#define RT_LWIP_MSKADDR1	255
-#define RT_LWIP_MSKADDR2	255
-#define RT_LWIP_MSKADDR3	0
+#define RT_LWIP_MSKADDR0    255
+#define RT_LWIP_MSKADDR1    255
+#define RT_LWIP_MSKADDR2    255
+#define RT_LWIP_MSKADDR3    0
 
 #endif
diff --git a/bsp/lpc2478/applications/application.c b/bsp/lpc2478/applications/application.c
index 64dbf3c807..fa10f80d56 100644
--- a/bsp/lpc2478/applications/application.c
+++ b/bsp/lpc2478/applications/application.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc2478/applications/startup.c b/bsp/lpc2478/applications/startup.c
index 0b961e4f94..05dee0ef8e 100644
--- a/bsp/lpc2478/applications/startup.c
+++ b/bsp/lpc2478/applications/startup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc2478/drivers/board.c b/bsp/lpc2478/drivers/board.c
index 65ff918711..956ec5c03f 100644
--- a/bsp/lpc2478/drivers/board.c
+++ b/bsp/lpc2478/drivers/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -14,7 +14,7 @@
 #include 
 #include "board.h"
 
-#define DATA_COUNT 14400000/RT_TICK_PER_SECOND	/* T0MR0 = delayInMs * (Fpclk / 1000); */
+#define DATA_COUNT 14400000/RT_TICK_PER_SECOND  /* T0MR0 = delayInMs * (Fpclk / 1000); */
 
 extern void rt_hw_serial_init(void);
 
@@ -25,9 +25,9 @@ extern void rt_hw_serial_init(void);
 
 void rt_timer_handler(int vector, void* param)
 {
-	T0IR |= 0x01;			/* clear interrupt flag */
-	rt_tick_increase();
-	VICVectAddr = 0;		/* Acknowledge Interrupt */
+    T0IR |= 0x01;           /* clear interrupt flag */
+    rt_tick_increase();
+    VICVectAddr = 0;        /* Acknowledge Interrupt */
 }
 
 /**
@@ -36,19 +36,19 @@ void rt_timer_handler(int vector, void* param)
 void rt_hw_board_init(void)
 {
 #if defined(RT_USING_DEVICE) && defined(RT_USING_UART1)
-	rt_hw_serial_init();
-	rt_console_set_device("uart1");
+    rt_hw_serial_init();
+    rt_console_set_device("uart1");
 #endif
 
-	T0IR 	= 0xff; 
-	T0TC 	= 0;
-	T0MCR 	= 0x03; 
-	T0MR0 	= (DATA_COUNT);
+    T0IR    = 0xff;
+    T0TC    = 0;
+    T0MCR   = 0x03;
+    T0MR0   = (DATA_COUNT);
 
-	rt_hw_interrupt_install(TIMER0_INT, rt_timer_handler, RT_NULL, "tick");	
-	rt_hw_interrupt_umask(TIMER0_INT);
+    rt_hw_interrupt_install(TIMER0_INT, rt_timer_handler, RT_NULL, "tick");
+    rt_hw_interrupt_umask(TIMER0_INT);
 
-	T0TCR = 0x01; //enable timer0 counter
+    T0TCR = 0x01; //enable timer0 counter
 }
 
 /*@}*/
diff --git a/bsp/lpc2478/drivers/board.h b/bsp/lpc2478/drivers/board.h
index 6386c19ba8..075fe354b8 100644
--- a/bsp/lpc2478/drivers/board.h
+++ b/bsp/lpc2478/drivers/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -14,7 +14,7 @@
 /* RT_USING_UART */
 #define RT_USING_UART1
 #define RT_USING_UART2
-#define RT_UART_RX_BUFFER_SIZE	64
+#define RT_UART_RX_BUFFER_SIZE  64
 void rt_hw_board_init(void);
 void rt_hw_led_set(rt_uint32_t led);
 void rt_hw_led_flash(void);
@@ -23,93 +23,93 @@ void rt_hw_led_flash(void);
 void rt_hw_finsh_init(void);
 #endif
 
-#define	USE_USB					0
+#define USE_USB                 0
 
-#if USE_USB		/* 1 is USB, 0 is non-USB related */  
-#define PLL_MValue			11
-#define PLL_NValue			0
-#define CCLKDivValue		4
-#define USBCLKDivValue		5
+#if USE_USB     /* 1 is USB, 0 is non-USB related */
+#define PLL_MValue          11
+#define PLL_NValue          0
+#define CCLKDivValue        4
+#define USBCLKDivValue      5
 
-#define Fosc	12000000
-#define Fcclk	57600000
-#define Fcco	288000000
+#define Fosc    12000000
+#define Fcclk   57600000
+#define Fcco    288000000
 #else
 
-#define PLL_MValue			12
-#define PLL_NValue			1
-#define CCLKDivValue		5
+#define PLL_MValue          12
+#define PLL_NValue          1
+#define CCLKDivValue        5
 
-#define Fosc	12000000
-#define Fcclk	72000000
-#define Fcco	360000000
+#define Fosc    12000000
+#define Fcclk   72000000
+#define Fcco    360000000
 
 #endif
 
 #if USE_USB
-#define Fpclk	(Fcclk / 2)
+#define Fpclk   (Fcclk / 2)
 #else
-#define Fpclk	(Fcclk / 4)
+#define Fpclk   (Fcclk / 4)
 #endif
 
 /* IRQ define */
-#define SYS32Mode		0x1F
-#define IRQ32Mode		0x12
-#define FIQ32Mode		0x11
+#define SYS32Mode       0x1F
+#define IRQ32Mode       0x12
+#define FIQ32Mode       0x11
 
-#define HIGHEST_PRIORITY	0x01
-#define LOWEST_PRIORITY		0x0F
+#define HIGHEST_PRIORITY    0x01
+#define LOWEST_PRIORITY     0x0F
 
-#define	WDT_INT			0
-#define SWI_INT			1
-#define ARM_CORE0_INT	2
-#define	ARM_CORE1_INT	3
-#define	TIMER0_INT		4
-#define TIMER1_INT		5
-#define UART0_INT		6
-#define	UART1_INT		7
-#define	PWM0_1_INT		8
-#define I2C0_INT		9
-#define SPI0_INT		10			/* SPI and SSP0 share VIC slot */
-#define SSP0_INT		10
-#define	SSP1_INT		11
-#define	PLL_INT			12
-#define RTC_INT			13
-#define EINT0_INT		14
-#define EINT1_INT		15
-#define EINT2_INT		16
-#define EINT3_INT		17
-#define	ADC0_INT		18
-#define I2C1_INT		19
-#define BOD_INT			20
-#define EMAC_INT		21
-#define USB_INT			22
-#define CAN_INT			23
-#define MCI_INT			24
-#define GPDMA_INT		25
-#define TIMER2_INT		26
-#define TIMER3_INT		27
-#define UART2_INT		28
-#define UART3_INT		29
-#define I2C2_INT		30
-#define I2S_INT			31
+#define WDT_INT         0
+#define SWI_INT         1
+#define ARM_CORE0_INT   2
+#define ARM_CORE1_INT   3
+#define TIMER0_INT      4
+#define TIMER1_INT      5
+#define UART0_INT       6
+#define UART1_INT       7
+#define PWM0_1_INT      8
+#define I2C0_INT        9
+#define SPI0_INT        10          /* SPI and SSP0 share VIC slot */
+#define SSP0_INT        10
+#define SSP1_INT        11
+#define PLL_INT         12
+#define RTC_INT         13
+#define EINT0_INT       14
+#define EINT1_INT       15
+#define EINT2_INT       16
+#define EINT3_INT       17
+#define ADC0_INT        18
+#define I2C1_INT        19
+#define BOD_INT         20
+#define EMAC_INT        21
+#define USB_INT         22
+#define CAN_INT         23
+#define MCI_INT         24
+#define GPDMA_INT       25
+#define TIMER2_INT      26
+#define TIMER3_INT      27
+#define UART2_INT       28
+#define UART3_INT       29
+#define I2C2_INT        30
+#define I2S_INT         31
 
-#define VIC_SIZE		32
+#define VIC_SIZE        32
 
-#define VECT_ADDR_INDEX	0x100
+#define VECT_ADDR_INDEX 0x100
 #define VECT_CNTL_INDEX 0x200
 
-#define CCLK	60000000	/* Fosc = 12MHz, M = 5 */
-#define PCLK	15000000	/* CCLK/4, use default */
+#define CCLK    60000000    /* Fosc = 12MHz, M = 5 */
+#define PCLK    15000000    /* CCLK/4, use default */
 
 /******************************************************************************
-** Function name:		TargetInit
+** Function name:       TargetInit
 **
-** Descriptions:		Initialize the target board; it is called in a 
-**				necessary place, change it as needed
+** Descriptions:        Initialize the target board; it is called in a
+**              necessary place, change it as needed
 **
-** parameters:			None
-** Returned value:		None
+** parameters:          None
+** Returned value:      None
 **
 ******************************************************************************/
 extern void TargetInit(void);
diff --git a/bsp/lpc2478/drivers/serial.c b/bsp/lpc2478/drivers/serial.c
index dff575c7cc..8e1fe1f91f 100644
--- a/bsp/lpc2478/drivers/serial.c
+++ b/bsp/lpc2478/drivers/serial.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,8 +15,8 @@
 #include "board.h"
 
 /* serial hardware register */
-#define REG8(d)			(*((volatile unsigned char *)(d)))
-#define REG32(d)		(*((volatile unsigned long *)(d)))
+#define REG8(d)         (*((volatile unsigned char *)(d)))
+#define REG32(d)        (*((volatile unsigned long *)(d)))
 
 #define UART_RBR(base)  REG8(base + 0x00)
 #define UART_THR(base)  REG8(base + 0x00)
@@ -37,16 +37,16 @@
 /* LPC serial device */
 struct rt_lpcserial
 {
-	/* inherit from device */
-	struct rt_device parent;
+    /* inherit from device */
+    struct rt_device parent;
 
-	rt_uint32_t hw_base;
-	rt_uint32_t irqno;
-	rt_uint32_t baudrate;
+    rt_uint32_t hw_base;
+    rt_uint32_t irqno;
+    rt_uint32_t baudrate;
 
-	/* reception field */
-	rt_uint16_t save_index, read_index;
-	rt_uint8_t  rx_buffer[RT_UART_RX_BUFFER_SIZE];
+    /* reception field */
+    rt_uint16_t save_index, read_index;
+    rt_uint8_t  rx_buffer[RT_UART_RX_BUFFER_SIZE];
 };
 
 #ifdef RT_USING_UART1
@@ -58,55 +58,55 @@ struct rt_lpcserial serial2;
 
 void rt_hw_serial_init(void);
 
-#define U0PINS  	0x00000005
+#define U0PINS      0x00000005
 
 void rt_hw_uart_isr(int irqno, void *param)
 {
-	RT_UNUSED rt_uint32_t iir;
-	struct rt_lpcserial* lpc_serial = (struct rt_lpcserial*)param;
+    RT_UNUSED rt_uint32_t iir;
+    struct rt_lpcserial* lpc_serial = (struct rt_lpcserial*)param;
 
-	RT_ASSERT(lpc_serial != RT_NULL)
-		
-	if (UART_LSR(lpc_serial->hw_base) & 0x01)
-	{
-		rt_base_t level;
+    RT_ASSERT(lpc_serial != RT_NULL)
 
-		while (UART_LSR(lpc_serial->hw_base) & 0x01)
-		{
-			/* disable interrupt */
-			level = rt_hw_interrupt_disable();
+    if (UART_LSR(lpc_serial->hw_base) & 0x01)
+    {
+        rt_base_t level;
 
-			/* read character */
-			lpc_serial->rx_buffer[lpc_serial->save_index] = 
-				UART_RBR(lpc_serial->hw_base);
-			lpc_serial->save_index ++;
-			if (lpc_serial->save_index >= RT_UART_RX_BUFFER_SIZE)
-				lpc_serial->save_index = 0;
-			
-			/* if the next position is read index, discard this 'read char' */
-			if (lpc_serial->save_index == lpc_serial->read_index)
-			{
-				lpc_serial->read_index ++;
-				if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
-					lpc_serial->read_index = 0;
-			}
+        while (UART_LSR(lpc_serial->hw_base) & 0x01)
+        {
+            /* disable interrupt */
+            level = rt_hw_interrupt_disable();
 
-			/* enable interrupt */
-			rt_hw_interrupt_enable(level);
-		}
+            /* read character */
+            lpc_serial->rx_buffer[lpc_serial->save_index] =
+                UART_RBR(lpc_serial->hw_base);
+            lpc_serial->save_index ++;
+            if (lpc_serial->save_index >= RT_UART_RX_BUFFER_SIZE)
+                lpc_serial->save_index = 0;
 
-		/* invoke callback */
-		if(lpc_serial->parent.rx_indicate != RT_NULL)
-		{
-		  lpc_serial->parent.rx_indicate(&lpc_serial->parent, 1);
-		}
-	}
+            /* if the next position is read index, discard this 'read char' */
+            if (lpc_serial->save_index == lpc_serial->read_index)
+            {
+                lpc_serial->read_index ++;
+                if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
+                    lpc_serial->read_index = 0;
+            }
 
-	/* clear interrupt source */
-	iir = UART_IIR(lpc_serial->hw_base);
+            /* enable interrupt */
+            rt_hw_interrupt_enable(level);
+        }
 
-	/* acknowledge Interrupt */
-	VICVectAddr = 0;
+        /* invoke callback */
+        if(lpc_serial->parent.rx_indicate != RT_NULL)
+        {
+          lpc_serial->parent.rx_indicate(&lpc_serial->parent, 1);
+        }
+    }
+
+    /* clear interrupt source */
+    iir = UART_IIR(lpc_serial->hw_base);
+
+    /* acknowledge Interrupt */
+    VICVectAddr = 0;
 }
 
 
@@ -117,243 +117,243 @@ void rt_hw_uart_isr(int irqno, void *param)
 
 static rt_err_t rt_serial_init (rt_device_t dev)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
 {
-	struct rt_lpcserial* lpc_serial;
-	lpc_serial = (struct rt_lpcserial*) dev;
-	
-	RT_ASSERT(lpc_serial != RT_NULL);
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-	    /* init UART rx interrupt */
-    	UART_IER(lpc_serial->hw_base) = 0x01;
+    struct rt_lpcserial* lpc_serial;
+    lpc_serial = (struct rt_lpcserial*) dev;
 
-		/* install ISR */
-	    rt_hw_interrupt_install(lpc_serial->irqno,
+    RT_ASSERT(lpc_serial != RT_NULL);
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* init UART rx interrupt */
+        UART_IER(lpc_serial->hw_base) = 0x01;
+
+        /* install ISR */
+        rt_hw_interrupt_install(lpc_serial->irqno,
                                 rt_hw_uart_isr, lpc_serial, RT_NULL);
-	    rt_hw_interrupt_umask(lpc_serial->irqno);
-	}
+        rt_hw_interrupt_umask(lpc_serial->irqno);
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_serial_close(rt_device_t dev)
 {
-	struct rt_lpcserial* lpc_serial;
-	lpc_serial = (struct rt_lpcserial*) dev;
-	
-	RT_ASSERT(lpc_serial != RT_NULL);
+    struct rt_lpcserial* lpc_serial;
+    lpc_serial = (struct rt_lpcserial*) dev;
 
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* disable UART rx interrupt */
-		UART_IER(lpc_serial->hw_base) = 0x00;
-	}
+    RT_ASSERT(lpc_serial != RT_NULL);
 
-	return RT_EOK;
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* disable UART rx interrupt */
+        UART_IER(lpc_serial->hw_base) = 0x00;
+    }
+
+    return RT_EOK;
 }
 
 static rt_err_t rt_serial_control(rt_device_t dev, int cmd, void *args)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
 {
-	rt_uint8_t* ptr;
-	struct rt_lpcserial *lpc_serial = (struct rt_lpcserial*)dev;
-	RT_ASSERT(lpc_serial != RT_NULL);
+    rt_uint8_t* ptr;
+    struct rt_lpcserial *lpc_serial = (struct rt_lpcserial*)dev;
+    RT_ASSERT(lpc_serial != RT_NULL);
 
-	/* point to buffer */
-	ptr = (rt_uint8_t*) buffer;
+    /* point to buffer */
+    ptr = (rt_uint8_t*) buffer;
 
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		while (size)
-		{
-			/* interrupt receive */
-			rt_base_t level;
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        while (size)
+        {
+            /* interrupt receive */
+            rt_base_t level;
 
-			/* disable interrupt */
-			level = rt_hw_interrupt_disable();
-			if (lpc_serial->read_index != lpc_serial->save_index)
-			{
-				*ptr = lpc_serial->rx_buffer[lpc_serial->read_index];
+            /* disable interrupt */
+            level = rt_hw_interrupt_disable();
+            if (lpc_serial->read_index != lpc_serial->save_index)
+            {
+                *ptr = lpc_serial->rx_buffer[lpc_serial->read_index];
 
-				lpc_serial->read_index ++;
-				if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
-					lpc_serial->read_index = 0;
-			}
-			else
-			{
-				/* no data in rx buffer */
+                lpc_serial->read_index ++;
+                if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
+                    lpc_serial->read_index = 0;
+            }
+            else
+            {
+                /* no data in rx buffer */
 
-				/* enable interrupt */
-				rt_hw_interrupt_enable(level);
-				break;
-			}
+                /* enable interrupt */
+                rt_hw_interrupt_enable(level);
+                break;
+            }
 
-			/* enable interrupt */
-			rt_hw_interrupt_enable(level);
+            /* enable interrupt */
+            rt_hw_interrupt_enable(level);
 
-			ptr ++; size --;
-		}
+            ptr ++; size --;
+        }
 
-		return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-	}
-	else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
-	{
-		/* not support right now */
-		RT_ASSERT(0);
-	}
+        return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+    }
+    else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
+    {
+        /* not support right now */
+        RT_ASSERT(0);
+    }
 
-	/* polling mode */
-	while (size && (UART_LSR(lpc_serial->hw_base) & 0x01))
-	{
-		/* Read Character */
-		*ptr = UART_RBR(lpc_serial->hw_base);
-		
-		ptr  ++;
-		size --;
-	}
+    /* polling mode */
+    while (size && (UART_LSR(lpc_serial->hw_base) & 0x01))
+    {
+        /* Read Character */
+        *ptr = UART_RBR(lpc_serial->hw_base);
 
-	return (rt_size_t)ptr - (rt_size_t)buffer;
+        ptr  ++;
+        size --;
+    }
+
+    return (rt_size_t)ptr - (rt_size_t)buffer;
 }
 
 static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
 {
-	struct rt_lpcserial* lpc_serial;
-	char *ptr;
+    struct rt_lpcserial* lpc_serial;
+    char *ptr;
 
-	lpc_serial = (struct rt_lpcserial*) dev;
-	if (dev->flag & RT_DEVICE_FLAG_INT_TX)
-	{
-		/* not support */
-		RT_ASSERT(0);
-	}
-	else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
-	{
-		/* not support */
-		RT_ASSERT(0);
-	}
+    lpc_serial = (struct rt_lpcserial*) dev;
+    if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+    {
+        /* not support */
+        RT_ASSERT(0);
+    }
+    else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
+    {
+        /* not support */
+        RT_ASSERT(0);
+    }
 
-	/* polling write */
-	ptr = (char *)buffer;
-	
-	if (dev->flag & RT_DEVICE_FLAG_STREAM)
-	{
-		/* stream mode */
-		while (size)
-		{
-			if (*ptr == '\n')
-			{
-				while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
-				UART_THR(lpc_serial->hw_base) = '\r';
-			}
+    /* polling write */
+    ptr = (char *)buffer;
 
-			while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
-			UART_THR(lpc_serial->hw_base) = *ptr;
-			
-			ptr ++;
-			size --;
-		}
-	}
-	else
-	{
-		while (size)
-		{
-			while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
-			UART_THR(lpc_serial->hw_base) = *ptr;
-			
-			ptr ++;
-			size --;
-		}
-	}
-	
-	return (rt_size_t) ptr - (rt_size_t) buffer;
+    if (dev->flag & RT_DEVICE_FLAG_STREAM)
+    {
+        /* stream mode */
+        while (size)
+        {
+            if (*ptr == '\n')
+            {
+                while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
+                UART_THR(lpc_serial->hw_base) = '\r';
+            }
+
+            while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
+            UART_THR(lpc_serial->hw_base) = *ptr;
+
+            ptr ++;
+            size --;
+        }
+    }
+    else
+    {
+        while (size)
+        {
+            while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
+            UART_THR(lpc_serial->hw_base) = *ptr;
+
+            ptr ++;
+            size --;
+        }
+    }
+
+    return (rt_size_t) ptr - (rt_size_t) buffer;
 }
 
 void rt_hw_serial_init(void)
 {
-	struct rt_lpcserial* lpc_serial;
-	
+    struct rt_lpcserial* lpc_serial;
+
 #ifdef RT_USING_UART1
-	lpc_serial = &serial1;
-	
-	lpc_serial->parent.type = RT_Device_Class_Char;
-	
-	lpc_serial->hw_base = 0xE000C000;
-	lpc_serial->baudrate = 115200;
-	lpc_serial->irqno = UART0_INT;
-	
-	rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
-	lpc_serial->read_index = lpc_serial->save_index = 0;
+    lpc_serial = &serial1;
 
-	/* Enable UART0 RxD and TxD pins */
-  	PINSEL0 |= 0x50;
+    lpc_serial->parent.type = RT_Device_Class_Char;
 
-	/* 8 bits, no Parity, 1 Stop bit */
-	UART_LCR(lpc_serial->hw_base) = 0x83;
-	
-	/* Setup Baudrate */
-	UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
-	UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
+    lpc_serial->hw_base = 0xE000C000;
+    lpc_serial->baudrate = 115200;
+    lpc_serial->irqno = UART0_INT;
 
-	/* DLAB = 0 */
-	UART_LCR(lpc_serial->hw_base) = 0x03;
+    rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
+    lpc_serial->read_index = lpc_serial->save_index = 0;
 
-	lpc_serial->parent.type     = RT_Device_Class_Char;
-	lpc_serial->parent.init 	= rt_serial_init;
-	lpc_serial->parent.open 	= rt_serial_open;
-	lpc_serial->parent.close    = rt_serial_close;
-	lpc_serial->parent.read 	= rt_serial_read;
-	lpc_serial->parent.write    = rt_serial_write;
-	lpc_serial->parent.control  = rt_serial_control;
-	lpc_serial->parent.user_data  = RT_NULL;
+    /* Enable UART0 RxD and TxD pins */
+    PINSEL0 |= 0x50;
 
-	rt_device_register(&lpc_serial->parent, 
-		"uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM);
+    /* 8 bits, no Parity, 1 Stop bit */
+    UART_LCR(lpc_serial->hw_base) = 0x83;
+
+    /* Setup Baudrate */
+    UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
+    UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
+
+    /* DLAB = 0 */
+    UART_LCR(lpc_serial->hw_base) = 0x03;
+
+    lpc_serial->parent.type     = RT_Device_Class_Char;
+    lpc_serial->parent.init     = rt_serial_init;
+    lpc_serial->parent.open     = rt_serial_open;
+    lpc_serial->parent.close    = rt_serial_close;
+    lpc_serial->parent.read     = rt_serial_read;
+    lpc_serial->parent.write    = rt_serial_write;
+    lpc_serial->parent.control  = rt_serial_control;
+    lpc_serial->parent.user_data  = RT_NULL;
+
+    rt_device_register(&lpc_serial->parent,
+        "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM);
 #endif
 
 #ifdef RT_USING_UART2
-	lpc_serial = &serial2;
-	
-	lpc_serial->parent.type = RT_Device_Class_Char;
+    lpc_serial = &serial2;
 
-	lpc_serial->hw_base = 0xE0010000;
-	lpc_serial->baudrate = 115200;
-	lpc_serial->irqno = UART1_INT;
+    lpc_serial->parent.type = RT_Device_Class_Char;
 
-	rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
-	lpc_serial->read_index = lpc_serial->save_index = 0;
+    lpc_serial->hw_base = 0xE0010000;
+    lpc_serial->baudrate = 115200;
+    lpc_serial->irqno = UART1_INT;
 
-	/* Enable UART1 RxD and TxD pins */
-  	PINSEL0 |= 0x05 << 16;
+    rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
+    lpc_serial->read_index = lpc_serial->save_index = 0;
 
-	/* 8 bits, no Parity, 1 Stop bit */
-	UART_LCR(lpc_serial->hw_base) = 0x83;
-	
-	/* Setup Baudrate */
-	UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
-	UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
+    /* Enable UART1 RxD and TxD pins */
+    PINSEL0 |= 0x05 << 16;
 
-	/* DLAB = 0 */
-	UART_LCR(lpc_serial->hw_base) = 0x03;
+    /* 8 bits, no Parity, 1 Stop bit */
+    UART_LCR(lpc_serial->hw_base) = 0x83;
 
-	lpc_serial->parent.type     = RT_Device_Class_Char;
-	lpc_serial->parent.init 	= rt_serial_init;
-	lpc_serial->parent.open 	= rt_serial_open;
-	lpc_serial->parent.close    = rt_serial_close;
-	lpc_serial->parent.read 	= rt_serial_read;
-	lpc_serial->parent.write    = rt_serial_write;
-	lpc_serial->parent.control  = rt_serial_control;
-	lpc_serial->parent.user_data  = RT_NULL;
+    /* Setup Baudrate */
+    UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
+    UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
 
-	rt_device_register(&lpc_serial->parent, 
-		"uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
+    /* DLAB = 0 */
+    UART_LCR(lpc_serial->hw_base) = 0x03;
+
+    lpc_serial->parent.type     = RT_Device_Class_Char;
+    lpc_serial->parent.init     = rt_serial_init;
+    lpc_serial->parent.open     = rt_serial_open;
+    lpc_serial->parent.close    = rt_serial_close;
+    lpc_serial->parent.read     = rt_serial_read;
+    lpc_serial->parent.write    = rt_serial_write;
+    lpc_serial->parent.control  = rt_serial_control;
+    lpc_serial->parent.user_data  = RT_NULL;
+
+    rt_device_register(&lpc_serial->parent,
+        "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
 #endif
 }
 
diff --git a/bsp/lpc2478/rtconfig.h b/bsp/lpc2478/rtconfig.h
index c35691aa80..d0c419d9ff 100644
--- a/bsp/lpc2478/rtconfig.h
+++ b/bsp/lpc2478/rtconfig.h
@@ -3,22 +3,22 @@
 #define __RTTHREAD_CFG_H__
 
 /* RT_NAME_MAX*/
-#define RT_NAME_MAX	8
+#define RT_NAME_MAX 8
 
 /* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE	4
+#define RT_ALIGN_SIZE   4
 
 /* PRIORITY_MAX*/
-#define RT_THREAD_PRIORITY_MAX	256
+#define RT_THREAD_PRIORITY_MAX  256
 
 /* Tick per Second*/
-#define RT_TICK_PER_SECOND	100
+#define RT_TICK_PER_SECOND  100
 
-#define RT_TIMER_THREAD_STACK_SIZE	   512
+#define RT_TIMER_THREAD_STACK_SIZE     512
 
 #define RT_TIMER_THREAD_PRIO       1
  /*     Rate at which timer management task runs (Hz)            */
-#define RT_TIMER_EX_TICKS_PER_SEC   10   
+#define RT_TIMER_EX_TICKS_PER_SEC   10
 
 
 /* SECTION: RT_DEBUG */
@@ -67,7 +67,7 @@
 /* SECTION: Console options */
 #define RT_USING_CONSOLE
 /* the buffer size of console*/
-#define RT_CONSOLEBUF_SIZE	128
+#define RT_CONSOLEBUF_SIZE  128
 
 /* SECTION: FinSH shell options */
 /* Using FinSH as Shell*/
@@ -102,21 +102,21 @@
 /* #define RT_LWIP_DHCP */
 
 /* ip address of target*/
-#define RT_LWIP_IPADDR0	192
-#define RT_LWIP_IPADDR1	168
-#define RT_LWIP_IPADDR2	0
-#define RT_LWIP_IPADDR3	30
+#define RT_LWIP_IPADDR0 192
+#define RT_LWIP_IPADDR1 168
+#define RT_LWIP_IPADDR2 0
+#define RT_LWIP_IPADDR3 30
 
 /* gateway address of target*/
-#define RT_LWIP_GWADDR0	192
-#define RT_LWIP_GWADDR1	168
-#define RT_LWIP_GWADDR2	0
-#define RT_LWIP_GWADDR3	1
+#define RT_LWIP_GWADDR0 192
+#define RT_LWIP_GWADDR1 168
+#define RT_LWIP_GWADDR2 0
+#define RT_LWIP_GWADDR3 1
 
 /* mask address of target*/
-#define RT_LWIP_MSKADDR0	255
-#define RT_LWIP_MSKADDR1	255
-#define RT_LWIP_MSKADDR2	255
-#define RT_LWIP_MSKADDR3	0
+#define RT_LWIP_MSKADDR0    255
+#define RT_LWIP_MSKADDR1    255
+#define RT_LWIP_MSKADDR2    255
+#define RT_LWIP_MSKADDR3    0
 
 #endif
diff --git a/bsp/lpc408x/applications/main.c b/bsp/lpc408x/applications/main.c
index 7874a25073..93495ce8c0 100644
--- a/bsp/lpc408x/applications/main.c
+++ b/bsp/lpc408x/applications/main.c
@@ -1,11 +1,11 @@
 /*
- * Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2018-12-10     armink    first version
+ * 2018-12-10     armink       first version
  */
 
 #include 
@@ -14,6 +14,6 @@
 int main(void)
 {
     rt_kprintf("Hello RT-Thread!\n");
-    
+
     return RT_EOK;
-} 
+}
diff --git a/bsp/lpc408x/drivers/board.c b/bsp/lpc408x/drivers/board.c
index 8db9473876..23e0ec07ac 100644
--- a/bsp/lpc408x/drivers/board.c
+++ b/bsp/lpc408x/drivers/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc408x/drivers/board.h b/bsp/lpc408x/drivers/board.h
index 1cc74d0fd6..0b4946ced7 100644
--- a/bsp/lpc408x/drivers/board.h
+++ b/bsp/lpc408x/drivers/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc408x/drivers/drv_emac.c b/bsp/lpc408x/drivers/drv_emac.c
index 7ea47d52ed..0bae0f1456 100644
--- a/bsp/lpc408x/drivers/drv_emac.c
+++ b/bsp/lpc408x/drivers/drv_emac.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc408x/drivers/drv_emac.h b/bsp/lpc408x/drivers/drv_emac.h
index 7d67eae178..ce5ca7d9e3 100644
--- a/bsp/lpc408x/drivers/drv_emac.h
+++ b/bsp/lpc408x/drivers/drv_emac.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc408x/drivers/drv_hwtimer.c b/bsp/lpc408x/drivers/drv_hwtimer.c
index fa09f87d76..0357c2c1f9 100644
--- a/bsp/lpc408x/drivers/drv_hwtimer.c
+++ b/bsp/lpc408x/drivers/drv_hwtimer.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc408x/drivers/drv_hwtimer.h b/bsp/lpc408x/drivers/drv_hwtimer.h
index 21c5a25eeb..ca34816a77 100644
--- a/bsp/lpc408x/drivers/drv_hwtimer.h
+++ b/bsp/lpc408x/drivers/drv_hwtimer.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc408x/drivers/drv_led.c b/bsp/lpc408x/drivers/drv_led.c
index d7df12ba82..29c74af1af 100644
--- a/bsp/lpc408x/drivers/drv_led.c
+++ b/bsp/lpc408x/drivers/drv_led.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc408x/drivers/drv_led.h b/bsp/lpc408x/drivers/drv_led.h
index f3a958c9b5..d006ac7ee6 100644
--- a/bsp/lpc408x/drivers/drv_led.h
+++ b/bsp/lpc408x/drivers/drv_led.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc408x/drivers/drv_sdram.c b/bsp/lpc408x/drivers/drv_sdram.c
index 0bb9ec6eb3..a0473bae01 100644
--- a/bsp/lpc408x/drivers/drv_sdram.c
+++ b/bsp/lpc408x/drivers/drv_sdram.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc408x/drivers/drv_sdram.h b/bsp/lpc408x/drivers/drv_sdram.h
index 74ceab2d18..0722e02d9d 100644
--- a/bsp/lpc408x/drivers/drv_sdram.h
+++ b/bsp/lpc408x/drivers/drv_sdram.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc408x/drivers/drv_uart.c b/bsp/lpc408x/drivers/drv_uart.c
index 09a518f4ab..3b11a851db 100644
--- a/bsp/lpc408x/drivers/drv_uart.c
+++ b/bsp/lpc408x/drivers/drv_uart.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc408x/drivers/drv_uart.h b/bsp/lpc408x/drivers/drv_uart.h
index 6fbe0535a5..3d8988e3ac 100644
--- a/bsp/lpc408x/drivers/drv_uart.h
+++ b/bsp/lpc408x/drivers/drv_uart.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc43xx/M0/SConstruct b/bsp/lpc43xx/M0/SConstruct
index 3a52eb9a43..145b29d70f 100644
--- a/bsp/lpc43xx/M0/SConstruct
+++ b/bsp/lpc43xx/M0/SConstruct
@@ -35,12 +35,12 @@ if rtconfig.CROSS_TOOL == 'gcc':
 
     if sys.platform.startswith('linux'):
         import glob
-        ocwd = os.getcwdu()
+        ocwd = os.getcwd()
         res = os.system('cd ../Libraries/; find -name \*.o -exec rm {} \;')
         os.chdir(ocwd)
     else:
         # Assume Windows.
-        ocwd = os.getcwdu()
+        ocwd = os.getcwd()
         print('TODO: remove the object files in ../Libraries')
         os.chdir(ocwd)
 
diff --git a/bsp/lpc43xx/M0/applications/application.c b/bsp/lpc43xx/M0/applications/application.c
index 2a9cec5103..1b14f82cd7 100644
--- a/bsp/lpc43xx/M0/applications/application.c
+++ b/bsp/lpc43xx/M0/applications/application.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc43xx/M0/applications/board.c b/bsp/lpc43xx/M0/applications/board.c
index cd1cf62df0..26d9cd404c 100644
--- a/bsp/lpc43xx/M0/applications/board.c
+++ b/bsp/lpc43xx/M0/applications/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc43xx/M0/applications/board.h b/bsp/lpc43xx/M0/applications/board.h
index 24dfee67d4..8462dad0f6 100644
--- a/bsp/lpc43xx/M0/applications/board.h
+++ b/bsp/lpc43xx/M0/applications/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc43xx/M0/applications/startup.c b/bsp/lpc43xx/M0/applications/startup.c
index df9cb7a211..65d430d64a 100644
--- a/bsp/lpc43xx/M0/applications/startup.c
+++ b/bsp/lpc43xx/M0/applications/startup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc43xx/M0/applications/vbus_drv.c b/bsp/lpc43xx/M0/applications/vbus_drv.c
index 696535247f..43b4b22aee 100644
--- a/bsp/lpc43xx/M0/applications/vbus_drv.c
+++ b/bsp/lpc43xx/M0/applications/vbus_drv.c
@@ -1,7 +1,8 @@
 /*
- * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd
- * 
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
  * SPDX-License-Identifier: Apache-2.0
+ *
  * Change Logs:
  * Date           Author       Notes
  * 2015-01-07     Grissiom     add comment
diff --git a/bsp/lpc43xx/M0/applications/vbus_hw.h b/bsp/lpc43xx/M0/applications/vbus_hw.h
index 850466cc45..0466d2339c 100644
--- a/bsp/lpc43xx/M0/applications/vbus_hw.h
+++ b/bsp/lpc43xx/M0/applications/vbus_hw.h
@@ -1,7 +1,8 @@
 /*
- * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd
- * 
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
  * SPDX-License-Identifier: Apache-2.0
+ *
  * Change Logs:
  * Date           Author       Notes
  * 2015-01-07     Grissiom     init commit
diff --git a/bsp/lpc43xx/M4/SConstruct b/bsp/lpc43xx/M4/SConstruct
index bcdc7f03eb..261af3765b 100644
--- a/bsp/lpc43xx/M4/SConstruct
+++ b/bsp/lpc43xx/M4/SConstruct
@@ -30,7 +30,7 @@ if rtconfig.CROSS_TOOL == 'gcc':
     print('build M0 code first')
     if sys.platform.startswith('linux'):
         import glob
-        ocwd = os.getcwdu()
+        ocwd = os.getcwd()
         os.chdir('../M0')
         res = os.system('scons')
         if res:
@@ -41,7 +41,7 @@ if rtconfig.CROSS_TOOL == 'gcc':
         os.chdir(ocwd)
     else:
         # Assume Windows.
-        ocwd = os.getcwdu()
+        ocwd = os.getcwd()
         os.chdir('..\M0')
         os.system('scons.bat')
         os.chdir(ocwd)
diff --git a/bsp/lpc43xx/M4/applications/application.c b/bsp/lpc43xx/M4/applications/application.c
index 8fb1a4ae83..03e56fa955 100644
--- a/bsp/lpc43xx/M4/applications/application.c
+++ b/bsp/lpc43xx/M4/applications/application.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -32,10 +32,10 @@ static void _boot_M0(void)
 
     LPC_CREG->M0APPMEMMAP = (uint32_t)&_M0_CODE[0];
 
-    // Release Slave from reset,  first read status 
+    // Release Slave from reset,  first read status
     u32REG = LPC_RGU->RESET_ACTIVE_STATUS1;
 
-    // If the M0 is being held in reset,  release it... 
+    // If the M0 is being held in reset,  release it...
     // 1 = no reset,  0 = reset
     while(!(u32REG & (1u << 24)))
     {
diff --git a/bsp/lpc43xx/M4/applications/board.c b/bsp/lpc43xx/M4/applications/board.c
index c6bfa10574..2f815060d5 100644
--- a/bsp/lpc43xx/M4/applications/board.c
+++ b/bsp/lpc43xx/M4/applications/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc43xx/M4/applications/board.h b/bsp/lpc43xx/M4/applications/board.h
index 0450724e53..faf2930854 100644
--- a/bsp/lpc43xx/M4/applications/board.h
+++ b/bsp/lpc43xx/M4/applications/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc43xx/M4/applications/startup.c b/bsp/lpc43xx/M4/applications/startup.c
index df9cb7a211..65d430d64a 100644
--- a/bsp/lpc43xx/M4/applications/startup.c
+++ b/bsp/lpc43xx/M4/applications/startup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc43xx/M4/applications/vbus_drv.c b/bsp/lpc43xx/M4/applications/vbus_drv.c
index 09fd2373c4..c2f41881a9 100644
--- a/bsp/lpc43xx/M4/applications/vbus_drv.c
+++ b/bsp/lpc43xx/M4/applications/vbus_drv.c
@@ -1,7 +1,8 @@
 /*
- * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd
- * 
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
  * SPDX-License-Identifier: Apache-2.0
+ *
  * Change Logs:
  * Date           Author       Notes
  * 2015-01-07     Grissiom     add comment
diff --git a/bsp/lpc43xx/M4/applications/vbus_hw.h b/bsp/lpc43xx/M4/applications/vbus_hw.h
index 850466cc45..0466d2339c 100644
--- a/bsp/lpc43xx/M4/applications/vbus_hw.h
+++ b/bsp/lpc43xx/M4/applications/vbus_hw.h
@@ -1,7 +1,8 @@
 /*
- * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd
- * 
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
  * SPDX-License-Identifier: Apache-2.0
+ *
  * Change Logs:
  * Date           Author       Notes
  * 2015-01-07     Grissiom     init commit
diff --git a/bsp/lpc43xx/drivers/drv_emac.c b/bsp/lpc43xx/drivers/drv_emac.c
index b8875c340c..a2df5dfd4d 100644
--- a/bsp/lpc43xx/drivers/drv_emac.c
+++ b/bsp/lpc43xx/drivers/drv_emac.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc43xx/drivers/drv_emac.h b/bsp/lpc43xx/drivers/drv_emac.h
index efaa0ac8e3..cde6d2742e 100644
--- a/bsp/lpc43xx/drivers/drv_emac.h
+++ b/bsp/lpc43xx/drivers/drv_emac.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc43xx/drivers/drv_led.c b/bsp/lpc43xx/drivers/drv_led.c
index 73128c243c..464ddb4f9f 100644
--- a/bsp/lpc43xx/drivers/drv_led.c
+++ b/bsp/lpc43xx/drivers/drv_led.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc43xx/drivers/drv_uart.c b/bsp/lpc43xx/drivers/drv_uart.c
index e1b203a359..f15f6fb760 100644
--- a/bsp/lpc43xx/drivers/drv_uart.c
+++ b/bsp/lpc43xx/drivers/drv_uart.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -179,7 +179,7 @@ void rt_hw_uart_init(void)
     config.parity    = PARITY_NONE;
     config.stop_bits = STOP_BITS_1;
     config.invert    = NRZ_NORMAL;
-    config.bufsz	 = RT_SERIAL_RB_BUFSZ;
+    config.bufsz     = RT_SERIAL_RB_BUFSZ;
 
     serial0.ops    = &lpc_uart_ops;
     serial0.config = config;
@@ -230,7 +230,7 @@ void rt_hw_uart_init(void)
     config.parity    = PARITY_NONE;
     config.stop_bits = STOP_BITS_1;
     config.invert    = NRZ_NORMAL;
-    config.bufsz	 = RT_SERIAL_RB_BUFSZ;
+    config.bufsz     = RT_SERIAL_RB_BUFSZ;
 
     serial2.ops    = &lpc_uart_ops;
     serial2.config = config;
@@ -282,7 +282,7 @@ void rt_hw_uart_init(void)
     config.parity    = PARITY_NONE;
     config.stop_bits = STOP_BITS_1;
     config.invert    = NRZ_NORMAL;
-    config.bufsz	 = RT_SERIAL_RB_BUFSZ;
+    config.bufsz     = RT_SERIAL_RB_BUFSZ;
 
     serial3.ops    = &lpc_uart_ops;
     serial3.config = config;
diff --git a/bsp/lpc5410x/applications/application.c b/bsp/lpc5410x/applications/application.c
index bad0922693..b99155b09d 100644
--- a/bsp/lpc5410x/applications/application.c
+++ b/bsp/lpc5410x/applications/application.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc5410x/applications/board.c b/bsp/lpc5410x/applications/board.c
index 0fb09e6574..ff451b2f1c 100644
--- a/bsp/lpc5410x/applications/board.c
+++ b/bsp/lpc5410x/applications/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -46,7 +46,7 @@ void rt_hw_board_init()
     SCB->VTOR  = (0x00000000 & NVIC_VTOR_MASK);
 #endif
     SystemCoreClockUpdate();
-    /* init systick  1 systick = 1/(100M / 100) 100systick = 1s*/
+    /* init systick  1 systick = 1/(100M / 100) 100个systick = 1s*/
     SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
     /* set pend exception priority */
     NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
diff --git a/bsp/lpc5410x/applications/board.h b/bsp/lpc5410x/applications/board.h
index 5bbf8bc235..03f6a284e7 100644
--- a/bsp/lpc5410x/applications/board.h
+++ b/bsp/lpc5410x/applications/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc5410x/applications/demo_thread.c b/bsp/lpc5410x/applications/demo_thread.c
index 6acb8ae0ef..0d7ce2d2b8 100644
--- a/bsp/lpc5410x/applications/demo_thread.c
+++ b/bsp/lpc5410x/applications/demo_thread.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -10,47 +10,47 @@
 #include "drv_led.h"
 #include "drv_uart.h"
 
-static void thread1_entry(void* parameter)					
+static void thread1_entry(void* parameter)
 {
     while(1)
     {
-			Led_Control(0,1);
-			rt_thread_delay(RT_TICK_PER_SECOND);
-			Led_Control(0,0);
-			rt_thread_delay(RT_TICK_PER_SECOND);
+            Led_Control(0,1);
+            rt_thread_delay(RT_TICK_PER_SECOND);
+            Led_Control(0,0);
+            rt_thread_delay(RT_TICK_PER_SECOND);
     }
 }
 
-static void thread2_entry(void* parameter)					
+static void thread2_entry(void* parameter)
 {
     while(1)
     {
-			Led_Control(1,1);
-			rt_thread_delay(RT_TICK_PER_SECOND);
-			Led_Control(1,0);
-			rt_thread_delay(RT_TICK_PER_SECOND);
-    }        
+            Led_Control(1,1);
+            rt_thread_delay(RT_TICK_PER_SECOND);
+            Led_Control(1,0);
+            rt_thread_delay(RT_TICK_PER_SECOND);
+    }
 }
 
 
 int demo_init(void)
 {
-	rt_thread_t  thread1 = RT_NULL;
-	rt_thread_t  thread2 = RT_NULL;
-	
-	
-	rt_led_hw_init();
-	
-	
-  thread1 = rt_thread_create("t1",thread1_entry, RT_NULL,512,10,5);                             
-  if (thread1 != RT_NULL)                 
-			rt_thread_startup(thread1);
+    rt_thread_t  thread1 = RT_NULL;
+    rt_thread_t  thread2 = RT_NULL;
 
-	thread2 = rt_thread_create("t2",thread2_entry, RT_NULL,512,10,5); 	
-	if (thread2 != RT_NULL)                 
-			rt_thread_startup(thread2);
 
-	
-	return 0;
-	
+    rt_led_hw_init();
+
+
+  thread1 = rt_thread_create("t1",thread1_entry, RT_NULL,512,10,5);
+  if (thread1 != RT_NULL)
+            rt_thread_startup(thread1);
+
+    thread2 = rt_thread_create("t2",thread2_entry, RT_NULL,512,10,5);
+    if (thread2 != RT_NULL)
+            rt_thread_startup(thread2);
+
+
+    return 0;
+
 }
diff --git a/bsp/lpc5410x/applications/startup.c b/bsp/lpc5410x/applications/startup.c
index 6f4ab94e82..0f50596ab1 100644
--- a/bsp/lpc5410x/applications/startup.c
+++ b/bsp/lpc5410x/applications/startup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc5410x/drivers/drv_led.c b/bsp/lpc5410x/drivers/drv_led.c
index 8923e3fda4..108707aee1 100644
--- a/bsp/lpc5410x/drivers/drv_led.c
+++ b/bsp/lpc5410x/drivers/drv_led.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc5410x/drivers/drv_led.h b/bsp/lpc5410x/drivers/drv_led.h
index 9ce2fea7be..87208c0e99 100644
--- a/bsp/lpc5410x/drivers/drv_led.h
+++ b/bsp/lpc5410x/drivers/drv_led.h
@@ -1,3 +1,12 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
 #ifndef __DRV_LED_H__
 #define __DRV_LED_H__
 
diff --git a/bsp/lpc5410x/drivers/drv_uart.c b/bsp/lpc5410x/drivers/drv_uart.c
index d348921740..826e659eb4 100644
--- a/bsp/lpc5410x/drivers/drv_uart.c
+++ b/bsp/lpc5410x/drivers/drv_uart.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc5410x/drivers/drv_uart.h b/bsp/lpc5410x/drivers/drv_uart.h
index 4ff948e746..6fa6e193d8 100644
--- a/bsp/lpc5410x/drivers/drv_uart.h
+++ b/bsp/lpc5410x/drivers/drv_uart.h
@@ -1,3 +1,12 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
 #ifndef __DRV_UART_H_
 #define __DRV_UART_H_
 
diff --git a/bsp/lpc5410x/rtconfig.h b/bsp/lpc5410x/rtconfig.h
index 387f1e75e6..c45f7094f6 100644
--- a/bsp/lpc5410x/rtconfig.h
+++ b/bsp/lpc5410x/rtconfig.h
@@ -5,17 +5,17 @@
 // 
 
 // 
-#define RT_NAME_MAX	8
+#define RT_NAME_MAX 8
 // 
-#define RT_ALIGN_SIZE	4
+#define RT_ALIGN_SIZE   4
 // 
 // 8
 // 32
 // 256
 // 
-#define RT_THREAD_PRIORITY_MAX	32
+#define RT_THREAD_PRIORITY_MAX  32
 // 
-#define RT_TICK_PER_SECOND	100
+#define RT_TICK_PER_SECOND  100
 // 

 #define RT_DEBUG
 #define RT_DEBUG_COLOR
@@ -30,11 +30,11 @@
 // 

 // #define RT_USING_TIMER_SOFT
 // 
-#define RT_TIMER_THREAD_PRIO	4
+#define RT_TIMER_THREAD_PRIO    4
 // 
-#define RT_TIMER_THREAD_STACK_SIZE	512
+#define RT_TIMER_THREAD_STACK_SIZE  512
 // 
-#define RT_TIMER_TICK_PER_SECOND	10
+#define RT_TIMER_TICK_PER_SECOND    10
 // 

 
 // 

@@ -75,7 +75,7 @@
 // 

 #define RT_USING_CONSOLE
 // 
-#define RT_CONSOLEBUF_SIZE	128
+#define RT_CONSOLEBUF_SIZE  128
 // 

 
 // 
@@ -87,7 +87,7 @@
 // 
 #define FINSH_USING_DESCRIPTION
 // 
-#define FINSH_THREAD_STACK_SIZE	4096
+#define FINSH_THREAD_STACK_SIZE 4096
 // 

 
 // 

@@ -102,18 +102,18 @@
 // 
 // #define DFS_USING_WORKDIR
 // 
-#define DFS_FILESYSTEMS_MAX	2
+#define DFS_FILESYSTEMS_MAX 2
 // 
-#define DFS_FD_MAX	4
+#define DFS_FD_MAX  4
 // 
 #define RT_USING_DFS_ELMFAT
 // 
 // 1
 // 2
 // 
-#define RT_DFS_ELM_USE_LFN	1
+#define RT_DFS_ELM_USE_LFN  1
 // 
-#define RT_DFS_ELM_MAX_LFN	64
+#define RT_DFS_ELM_MAX_LFN  64
 // 
 // #define RT_USING_DFS_YAFFS2
 // 
@@ -123,7 +123,7 @@
 // 
 // #define RT_USING_DFS_NFS
 // 
-#define RT_NFS_HOST_EXPORT	"192.168.1.5:/"
+#define RT_NFS_HOST_EXPORT  "192.168.1.5:/"
 // 

 
 // 

@@ -139,29 +139,29 @@
 // 
 #define RT_LWIP_DNS
 // 
-#define RT_LWIP_PBUF_NUM	4
+#define RT_LWIP_PBUF_NUM    4
 // 
-#define RT_LWIP_TCP_PCB_NUM	3
+#define RT_LWIP_TCP_PCB_NUM 3
 // 
-#define RT_LWIP_TCP_SND_BUF	2048
+#define RT_LWIP_TCP_SND_BUF 2048
 // 
-#define RT_LWIP_TCP_WND	2048
+#define RT_LWIP_TCP_WND 2048
 // 
 // #define RT_LWIP_SNMP
 // 
 // #define RT_LWIP_DHCP
 // 
-#define RT_LWIP_TCPTHREAD_PRIORITY	12
+#define RT_LWIP_TCPTHREAD_PRIORITY  12
 // 
-#define RT_LWIP_TCPTHREAD_MBOX_SIZE	8
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
 // 
-#define RT_LWIP_TCPTHREAD_STACKSIZE	4096
+#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
 // 
-#define RT_LWIP_ETHTHREAD_PRIORITY	14
+#define RT_LWIP_ETHTHREAD_PRIORITY  14
 // 
-#define RT_LWIP_ETHTHREAD_MBOX_SIZE	8
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
 // 
-#define RT_LWIP_ETHTHREAD_STACKSIZE	512
+#define RT_LWIP_ETHTHREAD_STACKSIZE 512
 // 
 #define RT_LWIP_IPADDR0 192
 #define RT_LWIP_IPADDR1 168
@@ -182,7 +182,7 @@
 // 

 // #define RT_USING_RTGUI
 // 
-#define RTGUI_NAME_MAX	12
+#define RTGUI_NAME_MAX  12
 // 
 #define RTGUI_USING_SMALL_SIZE
 // 
@@ -192,7 +192,7 @@
 // 
 #define RTGUI_USING_FONTHZ
 // 
-#define RTGUI_DEFAULT_FONT_SIZE	16
+#define RTGUI_DEFAULT_FONT_SIZE 16
 // 
 // #define RTGUI_USING_DFS_FILERW
 // 
diff --git a/bsp/lpc54114-lite/applications/main.c b/bsp/lpc54114-lite/applications/main.c
index 5c13ff5166..f3490dd40b 100644
--- a/bsp/lpc54114-lite/applications/main.c
+++ b/bsp/lpc54114-lite/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -14,9 +14,9 @@
 
 int main(void)
 {
-    /* user app entry */ 
+    /* user app entry */
     rt_pin_mode(LED4_PIN, PIN_MODE_OUTPUT);
-    
+
     while (1)
     {
         rt_pin_write(LED4_PIN, !rt_pin_read(LED4_PIN));
diff --git a/bsp/lpc54114-lite/applications/mnt.c b/bsp/lpc54114-lite/applications/mnt.c
index 7942e159ed..49852b2025 100644
--- a/bsp/lpc54114-lite/applications/mnt.c
+++ b/bsp/lpc54114-lite/applications/mnt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -24,15 +24,15 @@ int mnt_init(void)
     {
         rt_kprintf("spi flash mount '%s' failed.\n", BSP_FLASH_MOUNT_PATH);
     }
-#endif 
-    
+#endif
+
 #if defined(BSP_USING_SDCARD)
     if(dfs_mount("sd0", BSP_SDCARD_MOUNT_PATH, "elm", 0, 0) != 0)
     {
         rt_kprintf("sdcard mount '%s' failed.\n", BSP_SDCARD_MOUNT_PATH);
     }
-#endif 
+#endif
 
     return 0;
 }
-INIT_APP_EXPORT(mnt_init); 
+INIT_APP_EXPORT(mnt_init);
diff --git a/bsp/lpc54114-lite/drivers/audio/drv_mic.c b/bsp/lpc54114-lite/drivers/audio/drv_mic.c
index d8219b504d..37bab8e125 100644
--- a/bsp/lpc54114-lite/drivers/audio/drv_mic.c
+++ b/bsp/lpc54114-lite/drivers/audio/drv_mic.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -160,4 +160,4 @@ int rt_hw_mic_init(void)
 
     return RT_EOK;
 }
-INIT_DEVICE_EXPORT(rt_hw_mic_init);
\ No newline at end of file
+INIT_DEVICE_EXPORT(rt_hw_mic_init);
diff --git a/bsp/lpc54114-lite/drivers/audio/drv_mic.h b/bsp/lpc54114-lite/drivers/audio/drv_mic.h
index 1ce777d87d..7364999df5 100644
--- a/bsp/lpc54114-lite/drivers/audio/drv_mic.h
+++ b/bsp/lpc54114-lite/drivers/audio/drv_mic.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc54114-lite/drivers/audio/drv_sound.c b/bsp/lpc54114-lite/drivers/audio/drv_sound.c
index b6cf0ca2f0..409403facb 100644
--- a/bsp/lpc54114-lite/drivers/audio/drv_sound.c
+++ b/bsp/lpc54114-lite/drivers/audio/drv_sound.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -358,4 +358,4 @@ int rt_hw_sound_init(void)
     rt_audio_register(&snd_dev.audio, "sound0", RT_DEVICE_FLAG_WRONLY, &snd_dev);
     return RT_EOK;
 }
-INIT_DEVICE_EXPORT(rt_hw_sound_init);
\ No newline at end of file
+INIT_DEVICE_EXPORT(rt_hw_sound_init);
diff --git a/bsp/lpc54114-lite/drivers/audio/drv_sound.h b/bsp/lpc54114-lite/drivers/audio/drv_sound.h
index aa997983ae..b50fe66593 100644
--- a/bsp/lpc54114-lite/drivers/audio/drv_sound.h
+++ b/bsp/lpc54114-lite/drivers/audio/drv_sound.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc54114-lite/drivers/board.c b/bsp/lpc54114-lite/drivers/board.c
index 61652d1c78..f8dc23a34b 100644
--- a/bsp/lpc54114-lite/drivers/board.c
+++ b/bsp/lpc54114-lite/drivers/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -57,15 +57,15 @@ void rt_hw_board_init()
     SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
     /* set pend exception priority */
     NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
-    
+
 #ifdef RT_USING_HEAP
     rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
 #endif
 #ifdef RT_USING_COMPONENTS_INIT
     /* initialization board with RT-Thread Components */
     rt_components_board_init();
-#endif    
-#ifdef RT_USING_CONSOLE    
+#endif
+#ifdef RT_USING_CONSOLE
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
 }
diff --git a/bsp/lpc54114-lite/drivers/board.h b/bsp/lpc54114-lite/drivers/board.h
index 78c6d7c8c3..4e07415919 100644
--- a/bsp/lpc54114-lite/drivers/board.h
+++ b/bsp/lpc54114-lite/drivers/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc54114-lite/drivers/drv_gpio.c b/bsp/lpc54114-lite/drivers/drv_gpio.c
index 978fa2898e..9b8b4d5da4 100644
--- a/bsp/lpc54114-lite/drivers/drv_gpio.c
+++ b/bsp/lpc54114-lite/drivers/drv_gpio.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -35,7 +35,7 @@ struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
     {-1, 0, RT_NULL, RT_NULL},
     {-1, 0, RT_NULL, RT_NULL},
     {-1, 0, RT_NULL, RT_NULL},
-    {-1, 0, RT_NULL, RT_NULL},    
+    {-1, 0, RT_NULL, RT_NULL},
 };
 
 static rt_base_t lpc_pin_get(const char *name)
@@ -85,46 +85,46 @@ static void lpc_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
 {
     int portx, piny, dir;
     uint32_t pin_cfg;
-    
+
     if(pin > PIN_MAX_VAL)
         return;
-    
+
     portx = get_port(pin);
-    piny  = get_pin(pin);    
-    
+    piny  = get_pin(pin);
+
     switch(mode)
     {
-    case PIN_MODE_OUTPUT: 
+    case PIN_MODE_OUTPUT:
         dir = kGPIO_DigitalOutput;
         pin_cfg = IOCON_FUNC0 | IOCON_DIGITAL_EN;
         break;
     case PIN_MODE_OUTPUT_OD:
-        dir = kGPIO_DigitalOutput;        
-        pin_cfg = IOCON_FUNC0 | IOCON_OPENDRAIN_EN | IOCON_DIGITAL_EN;        
+        dir = kGPIO_DigitalOutput;
+        pin_cfg = IOCON_FUNC0 | IOCON_OPENDRAIN_EN | IOCON_DIGITAL_EN;
         break;
-    
-    case PIN_MODE_INPUT:   
+
+    case PIN_MODE_INPUT:
         dir = kGPIO_DigitalInput;
         pin_cfg = IOCON_FUNC0 | IOCON_INPFILT_OFF | IOCON_DIGITAL_EN;
-        break;        
+        break;
     case PIN_MODE_INPUT_PULLUP:
-        dir = kGPIO_DigitalInput;        
+        dir = kGPIO_DigitalInput;
         pin_cfg = IOCON_FUNC0 | IOCON_INPFILT_OFF | IOCON_DIGITAL_EN | IOCON_MODE_PULLUP;
         break;
-    case PIN_MODE_INPUT_PULLDOWN: 
+    case PIN_MODE_INPUT_PULLDOWN:
         dir = kGPIO_DigitalInput;
-        pin_cfg = IOCON_FUNC0 | IOCON_INPFILT_OFF | IOCON_DIGITAL_EN | IOCON_MODE_PULLDOWN;        
+        pin_cfg = IOCON_FUNC0 | IOCON_INPFILT_OFF | IOCON_DIGITAL_EN | IOCON_MODE_PULLDOWN;
         break;
     default: break;
-    }      
-    
-    CLOCK_EnableClock(kCLOCK_Iocon); 
-    
-    IOCON_PinMuxSet(IOCON, portx, piny, pin_cfg);        
-    GPIO_PortInit(GPIO, portx);    
-    
+    }
+
+    CLOCK_EnableClock(kCLOCK_Iocon);
+
+    IOCON_PinMuxSet(IOCON, portx, piny, pin_cfg);
+    GPIO_PortInit(GPIO, portx);
+
     gpio_pin_config_t pin_config = {(gpio_pin_direction_t)dir, 0};
-    GPIO_PinInit(GPIO, portx, piny, &pin_config); 
+    GPIO_PinInit(GPIO, portx, piny, &pin_config);
 
     CLOCK_DisableClock(kCLOCK_Iocon);
 }
@@ -133,27 +133,27 @@ static void lpc_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
 {
     int portx, piny;
     portx = get_port(pin);
-    piny  = get_pin(pin);   
+    piny  = get_pin(pin);
 
     if(pin > PIN_MAX_VAL)
        return;
 
-    GPIO_PinWrite(GPIO, portx, piny, value);        
+    GPIO_PinWrite(GPIO, portx, piny, value);
 }
 
 static int lpc_pin_read(rt_device_t dev, rt_base_t pin)
 {
-    int  portx, piny, value;    
-    
+    int  portx, piny, value;
+
     if(pin > PIN_MAX_VAL)
-        return RT_ERROR; 
-    
+        return RT_ERROR;
+
     portx = get_port(pin);
-    piny  = get_pin(pin);  
-    
+    piny  = get_pin(pin);
+
     value = (int)(GPIO_PinRead(GPIO, portx, piny));
-    
-    return value;    
+
+    return value;
 }
 
 static void pin_irq_hdr(pint_pin_int_t pintr, uint32_t pmatch_status)
@@ -166,10 +166,10 @@ static void pin_irq_hdr(pint_pin_int_t pintr, uint32_t pmatch_status)
             break;
         }
     }
-    
+
     if(irqno >= IRQ_MAX_VAL)
         return;
-    
+
     if (pin_irq_hdr_tab[irqno].hdr)
     {
         pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
@@ -184,14 +184,14 @@ void callback(pint_pin_int_t pintr, uint32_t pmatch_status)
 static rt_err_t lpc_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
                                    rt_uint32_t mode, void (*hdr)(void *args), void *args)
 {
-    int portx, piny, trigger_mode, pin_initx, pintsel, pin_cfg, i;    
-    
+    int portx, piny, trigger_mode, pin_initx, pintsel, pin_cfg, i;
+
     if(pin > PIN_MAX_VAL)
-        return RT_ERROR; 
-    
+        return RT_ERROR;
+
     portx = get_port(pin);
-    piny  = get_pin(pin); 
-    
+    piny  = get_pin(pin);
+
     switch (mode)
         {
         case PIN_IRQ_MODE_RISING:
@@ -210,10 +210,10 @@ static rt_err_t lpc_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
             trigger_mode = kPINT_PinIntEnableLowLevel;
             break;
         }
-     
-    /* Get inputmux_connection_t */        
+
+    /* Get inputmux_connection_t */
     pintsel = (pin + (0xC0U << 20));
-    
+
     for(i = 0; i < IRQ_MAX_VAL; i++)
     {
         if(pin_irq_hdr_tab[i].pin == -1)
@@ -226,40 +226,40 @@ static rt_err_t lpc_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
             break;
         }
     }
-        
+
     if(i >= IRQ_MAX_VAL)
         return RT_ERROR;
-    
+
     /* open clk */
     CLOCK_EnableClock(kCLOCK_InputMux);
     CLOCK_EnableClock(kCLOCK_Iocon);
-    
-    /* AttachSignal */    
+
+    /* AttachSignal */
     INPUTMUX_AttachSignal(INPUTMUX, i, (inputmux_connection_t)pintsel);
     pin_cfg = ((IOCON->PIO[portx][piny] &
               (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK | IOCON_PIO_FILTEROFF_MASK))) /* Mask bits to zero which are setting */
               | IOCON_PIO_FUNC(0)                /* Selects pin function.: PORT18 (pin 28) is configured as PIO1_8 */
               | IOCON_PIO_DIGIMODE(1)            /* Select Analog/Digital mode.: Digital mode. */
               | IOCON_PIO_FILTEROFF(0));         /* Controls input glitch filter.: Filter enabled. Noise pulses below approximately 10 ns are filtered out. */
-                   
-    IOCON_PinMuxSet(IOCON, portx, piny, pin_cfg);    
-    
+
+    IOCON_PinMuxSet(IOCON, portx, piny, pin_cfg);
+
     /* PINT_PinInterruptConfig */
-    PINT_PinInterruptConfig(PINT, (pint_pin_int_t)pin_initx, (pint_pin_enable_t)(pin_irq_hdr_tab[i].mode), callback);    
-    
+    PINT_PinInterruptConfig(PINT, (pint_pin_int_t)pin_initx, (pint_pin_enable_t)(pin_irq_hdr_tab[i].mode), callback);
+
     CLOCK_DisableClock(kCLOCK_InputMux);
     CLOCK_DisableClock(kCLOCK_Iocon);
-    
+
     return RT_EOK;
 }
 
 static rt_err_t lpc_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
 {
-    int i;    
-    
+    int i;
+
     if(pin > PIN_MAX_VAL)
-        return RT_ERROR; 
-    
+        return RT_ERROR;
+
     for(i = 0; i < IRQ_MAX_VAL; i++)
     {
         if(pin_irq_hdr_tab[i].pin == pin)
@@ -270,18 +270,18 @@ static rt_err_t lpc_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
             pin_irq_hdr_tab[i].args = RT_NULL;
             break;
         }
-    }        
+    }
     return RT_EOK;
 }
 
 static rt_err_t lpc_pin_irq_enable(struct rt_device *device, rt_base_t pin,
                                    rt_uint32_t enabled)
-{  
+{
     int irqn_type, i;
-    
+
     if(pin > PIN_MAX_VAL)
-        return RT_ERROR; 
-    
+        return RT_ERROR;
+
     for(i = 0; i < IRQ_MAX_VAL; i++)
     {
         if(pin_irq_hdr_tab[i].pin == pin)
@@ -315,8 +315,8 @@ static rt_err_t lpc_pin_irq_enable(struct rt_device *device, rt_base_t pin,
             }
             break;
         }
-    }  
-        
+    }
+
     if(i >= IRQ_MAX_VAL)
         return RT_ERROR;
 
diff --git a/bsp/lpc54114-lite/drivers/drv_gpio.h b/bsp/lpc54114-lite/drivers/drv_gpio.h
index 0c98e82298..41e4c45724 100644
--- a/bsp/lpc54114-lite/drivers/drv_gpio.h
+++ b/bsp/lpc54114-lite/drivers/drv_gpio.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -13,4 +13,4 @@
 
 extern int rt_hw_pin_init(void);
 
-#endif 
+#endif
diff --git a/bsp/lpc54114-lite/drivers/drv_i2c.c b/bsp/lpc54114-lite/drivers/drv_i2c.c
index 81be945067..cba87c8aec 100644
--- a/bsp/lpc54114-lite/drivers/drv_i2c.c
+++ b/bsp/lpc54114-lite/drivers/drv_i2c.c
@@ -1,21 +1,21 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  */
- 
-#include "drv_i2c.h" 
 
-#include "fsl_common.h" 
+#include "drv_i2c.h"
+
+#include "fsl_common.h"
 #include "fsl_iocon.h"
 #include "fsl_i2c.h"
 
 struct lpc_i2c
 {
-    struct rt_i2c_bus_device bus; 
-    
+    struct rt_i2c_bus_device bus;
+
     I2C_Type *base;
-    
+
     char *device_name;
 };
 
@@ -28,9 +28,9 @@ static uint32_t get_i2c_freq(I2C_Type *base)
     {
         freq = CLOCK_GetFreq(kCLOCK_Flexcomm4);
     }
-#endif 
+#endif
 
-    return freq; 
+    return freq;
 }
 
 static rt_size_t master_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num)
@@ -43,7 +43,7 @@ static rt_size_t master_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg ms
     i2c_direction_t direction;
     status_t result = kStatus_Success;
 
-    RT_ASSERT(bus != RT_NULL); 
+    RT_ASSERT(bus != RT_NULL);
 
     lpc_i2c = (struct lpc_i2c *)bus;
 
@@ -94,13 +94,13 @@ static rt_err_t i2c_bus_control(struct rt_i2c_bus_device *bus, rt_uint32_t cmd,
 
 static const struct rt_i2c_bus_device_ops ops =
 {
-    master_xfer, 
+    master_xfer,
     slave_xfer,
     i2c_bus_control,
-}; 
+};
 
 #if defined(BSP_USING_I2C4)
-static struct lpc_i2c i2c4 = {0}; 
+static struct lpc_i2c i2c4 = {0};
 #endif
 
 int rt_hw_i2c_init(void)
@@ -110,11 +110,11 @@ int rt_hw_i2c_init(void)
 #if defined(BSP_USING_I2C4)
     CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
     RESET_PeripheralReset(kFC4_RST_SHIFT_RSTn);
-    
+
     i2c4.base = I2C4;
-    i2c4.device_name = "i2c4"; 
-    i2c4.bus.ops = &ops; 
-    
+    i2c4.device_name = "i2c4";
+    i2c4.bus.ops = &ops;
+
     IOCON_PinMuxSet(IOCON, 1, 1, IOCON_MODE_PULLUP | IOCON_FUNC5 | IOCON_DIGITAL_EN | IOCON_INPFILT_OFF);
     IOCON_PinMuxSet(IOCON, 1, 2, IOCON_MODE_PULLUP | IOCON_FUNC5 | IOCON_DIGITAL_EN | IOCON_INPFILT_OFF);
 
@@ -122,12 +122,12 @@ int rt_hw_i2c_init(void)
 
     I2C_MasterGetDefaultConfig(&masterConfig);
     masterConfig.baudRate_Bps = 100*1000U;
-    
+
     I2C_MasterInit(I2C4, &masterConfig, get_i2c_freq(I2C4));
 
     rt_i2c_bus_device_register(&i2c4.bus, i2c4.device_name);
 #endif
 
-    return RT_EOK; 
+    return RT_EOK;
 }
-INIT_BOARD_EXPORT(rt_hw_i2c_init); 
+INIT_BOARD_EXPORT(rt_hw_i2c_init);
diff --git a/bsp/lpc54114-lite/drivers/drv_i2c.h b/bsp/lpc54114-lite/drivers/drv_i2c.h
index 468ac3c0dc..c5073237a8 100644
--- a/bsp/lpc54114-lite/drivers/drv_i2c.h
+++ b/bsp/lpc54114-lite/drivers/drv_i2c.h
@@ -1,14 +1,14 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  */
- 
-#ifndef __DRV_I2C_H__ 
-#define __DRV_I2C_H__ 
 
-#include  
-#include  
+#ifndef __DRV_I2C_H__
+#define __DRV_I2C_H__
+
+#include 
+#include 
 
 int rt_hw_i2c_init(void);
 
diff --git a/bsp/lpc54114-lite/drivers/drv_romfs.c b/bsp/lpc54114-lite/drivers/drv_romfs.c
index 7c444af03f..d488b163fc 100644
--- a/bsp/lpc54114-lite/drivers/drv_romfs.c
+++ b/bsp/lpc54114-lite/drivers/drv_romfs.c
@@ -2,49 +2,49 @@
 #include 
 #include 
 
-static const rt_uint8_t _romfs_root_license[] = 
+static const rt_uint8_t _romfs_root_license[] =
 {
     0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x41, 0x70, 0x61, 0x63, 0x68, 0x65, 0x20, 0x4c, 0x69, 0x63, 0x65, 0x6e, 0x73, 0x65, 0x0d, 0x0a, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x56, 0x65, 0x72, 0x73, 0x69, 0x6f, 0x6e, 0x20, 0x32, 0x2e, 0x30, 0x2c, 0x20, 0x4a, 0x61, 0x6e, 0x75, 0x61, 0x72, 0x79, 0x20, 0x32, 0x30, 0x30, 0x34, 0x0d, 0x0a, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x68, 0x74, 0x74, 0x70, 0x3a, 0x2f, 0x2f, 0x77, 0x77, 0x77, 0x2e, 0x61, 0x70, 0x61, 0x63, 0x68, 0x65, 0x2e, 0x6f, 0x72, 0x67, 0x2f, 0x6c, 0x69, 0x63, 0x65, 0x6e, 0x73, 0x65, 0x73, 0x2f, 0x0d, 0x0a, 0x0d, 0x0a, 0x20, 0x20, 0x20, 0x54, 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 };
 
-static const rt_uint8_t _romfs_root_mnt_flash__keep[] = 
+static const rt_uint8_t _romfs_root_mnt_flash__keep[] =
 {
     0x2e, 0x6b, 0x65, 0x65, 0x70, 0x20, 0x0d, 0x0a
 };
 
-static const struct romfs_dirent _romfs_root_mnt_flash[] = 
+static const struct romfs_dirent _romfs_root_mnt_flash[] =
 {
     {ROMFS_DIRENT_FILE, ".keep", (rt_uint8_t *)_romfs_root_mnt_flash__keep, sizeof(_romfs_root_mnt_flash__keep) / sizeof(_romfs_root_mnt_flash__keep[0])}
 };
 
-static const rt_uint8_t _romfs_root_mnt_sd__keep[] = 
+static const rt_uint8_t _romfs_root_mnt_sd__keep[] =
 {
     0x2e, 0x6b, 0x65, 0x65, 0x70, 0x20, 0x0d, 0x0a
 };
 
-static const struct romfs_dirent _romfs_root_mnt_sd[] = 
+static const struct romfs_dirent _romfs_root_mnt_sd[] =
 {
     {ROMFS_DIRENT_FILE, ".keep", (rt_uint8_t *)_romfs_root_mnt_sd__keep, sizeof(_romfs_root_mnt_sd__keep) / sizeof(_romfs_root_mnt_sd__keep[0])}
 };
 
-static const rt_uint8_t _romfs_root_mnt_tmp__keep[] = 
+static const rt_uint8_t _romfs_root_mnt_tmp__keep[] =
 {
     0x2e, 0x6b, 0x65, 0x65, 0x70, 0x20, 0x0d, 0x0a
 };
 
-static const struct romfs_dirent _romfs_root_mnt_tmp[] = 
+static const struct romfs_dirent _romfs_root_mnt_tmp[] =
 {
     {ROMFS_DIRENT_FILE, ".keep", (rt_uint8_t *)_romfs_root_mnt_tmp__keep, sizeof(_romfs_root_mnt_tmp__keep) / sizeof(_romfs_root_mnt_tmp__keep[0])}
 };
 
-static const struct romfs_dirent _romfs_root_mnt[] = 
+static const struct romfs_dirent _romfs_root_mnt[] =
 {
     {ROMFS_DIRENT_DIR, "flash", (rt_uint8_t *)_romfs_root_mnt_flash, sizeof(_romfs_root_mnt_flash) / sizeof(_romfs_root_mnt_flash[0])},
     {ROMFS_DIRENT_DIR, "sd", (rt_uint8_t *)_romfs_root_mnt_sd, sizeof(_romfs_root_mnt_sd) / sizeof(_romfs_root_mnt_sd[0])},
     {ROMFS_DIRENT_DIR, "tmp", (rt_uint8_t *)_romfs_root_mnt_tmp, sizeof(_romfs_root_mnt_tmp) / sizeof(_romfs_root_mnt_tmp[0])}
 };
 
-static const struct romfs_dirent _romfs_root[] = 
+static const struct romfs_dirent _romfs_root[] =
 {
     {ROMFS_DIRENT_FILE, "license", (rt_uint8_t *)_romfs_root_license, sizeof(_romfs_root_license) / sizeof(_romfs_root_license[0])},
     {ROMFS_DIRENT_DIR, "mnt", (rt_uint8_t *)_romfs_root_mnt, sizeof(_romfs_root_mnt) / sizeof(_romfs_root_mnt[0])}
diff --git a/bsp/lpc54114-lite/drivers/drv_sdcard.c b/bsp/lpc54114-lite/drivers/drv_sdcard.c
index 3ef5081aa7..7ca47a1932 100644
--- a/bsp/lpc54114-lite/drivers/drv_sdcard.c
+++ b/bsp/lpc54114-lite/drivers/drv_sdcard.c
@@ -1,27 +1,27 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  */
- 
+
 #include "drv_sdcard.h"
-#include "drv_spi.h" 
+#include "drv_spi.h"
 #include "spi_msd.h"
 
 #define RT_SDCARD_CS_PIN (3)
 
 int rt_hw_sdcard_init(void)
 {
-    rt_err_t ret; 
-    
-    ret = lpc_spi_bus_attach_device("spi2", "spi21", RT_SDCARD_CS_PIN); 
-    if(ret != RT_EOK) 
+    rt_err_t ret;
+
+    ret = lpc_spi_bus_attach_device("spi2", "spi21", RT_SDCARD_CS_PIN);
+    if(ret != RT_EOK)
     {
-        return ret; 
+        return ret;
     }
-    
+
     ret = msd_init("sd0", "spi21");
 
-    return ret; 
+    return ret;
 }
-INIT_DEVICE_EXPORT(rt_hw_sdcard_init); 
+INIT_DEVICE_EXPORT(rt_hw_sdcard_init);
diff --git a/bsp/lpc54114-lite/drivers/drv_sdcard.h b/bsp/lpc54114-lite/drivers/drv_sdcard.h
index 1ba77cf2b2..a225433b15 100644
--- a/bsp/lpc54114-lite/drivers/drv_sdcard.h
+++ b/bsp/lpc54114-lite/drivers/drv_sdcard.h
@@ -1,14 +1,14 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  */
- 
-#ifndef __DRV_SDCARD_H__ 
-#define __DRV_SDCARD_H__ 
 
-#include  
-#include  
+#ifndef __DRV_SDCARD_H__
+#define __DRV_SDCARD_H__
+
+#include 
+#include 
 
 int rt_hw_sdcard_init(void);
 
diff --git a/bsp/lpc54114-lite/drivers/drv_spi.c b/bsp/lpc54114-lite/drivers/drv_spi.c
index 0843e0baab..c83aaf03ee 100644
--- a/bsp/lpc54114-lite/drivers/drv_spi.c
+++ b/bsp/lpc54114-lite/drivers/drv_spi.c
@@ -1,12 +1,12 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #include "drv_spi.h"
 
-#include "fsl_common.h" 
+#include "fsl_common.h"
 #include "fsl_iocon.h"
 #include "fsl_spi.h"
 
@@ -25,23 +25,23 @@ static uint32_t get_spi_freq(SPI_Type *base)
     {
         freq = CLOCK_GetFreq(kCLOCK_Flexcomm2);
     }
-#endif 
+#endif
 
-    return freq; 
+    return freq;
 }
 
 static rt_err_t spi_init(SPI_Type *base, struct rt_spi_configuration *cfg)
 {
     spi_master_config_t masterConfig = {0};
 
-    RT_ASSERT(cfg != RT_NULL); 
+    RT_ASSERT(cfg != RT_NULL);
 
     if(cfg->data_width != 8 && cfg->data_width != 16)
     {
-        return (-RT_EINVAL); 
+        return (-RT_EINVAL);
     }
 
-    SPI_MasterGetDefaultConfig(&masterConfig); 
+    SPI_MasterGetDefaultConfig(&masterConfig);
 
     if(cfg->max_hz > 12*1000*1000)
     {
@@ -51,124 +51,124 @@ static rt_err_t spi_init(SPI_Type *base, struct rt_spi_configuration *cfg)
 
     if(cfg->data_width == 8)
     {
-        masterConfig.dataWidth = kSPI_Data8Bits; 
+        masterConfig.dataWidth = kSPI_Data8Bits;
     }
     else if(cfg->data_width == 16)
     {
-        masterConfig.dataWidth = kSPI_Data16Bits; 
+        masterConfig.dataWidth = kSPI_Data16Bits;
     }
 
     if(cfg->mode & RT_SPI_MSB)
     {
-        masterConfig.direction = kSPI_MsbFirst; 
+        masterConfig.direction = kSPI_MsbFirst;
     }
     else
     {
-        masterConfig.direction = kSPI_LsbFirst; 
+        masterConfig.direction = kSPI_LsbFirst;
     }
 
     if(cfg->mode & RT_SPI_CPHA)
     {
-        masterConfig.phase = kSPI_ClockPhaseSecondEdge; 
+        masterConfig.phase = kSPI_ClockPhaseSecondEdge;
     }
     else
     {
-        masterConfig.phase = kSPI_ClockPhaseFirstEdge; 
+        masterConfig.phase = kSPI_ClockPhaseFirstEdge;
     }
 
     if(cfg->mode & RT_SPI_CPOL)
     {
-        masterConfig.polarity = kSPI_ClockPolarityActiveLow; 
+        masterConfig.polarity = kSPI_ClockPolarityActiveLow;
     }
     else
     {
-        masterConfig.polarity = kSPI_ClockPolarityActiveHigh; 
+        masterConfig.polarity = kSPI_ClockPolarityActiveHigh;
     }
 
-    masterConfig.txWatermark = kSPI_TxFifo0, 
-    masterConfig.rxWatermark = kSPI_RxFifo1, 
-    
-    // masterConfig.sselNum = kSPI_Ssel3; 
-    SPI_MasterInit(base, &masterConfig, get_spi_freq(base)); 
+    masterConfig.txWatermark = kSPI_TxFifo0,
+    masterConfig.rxWatermark = kSPI_RxFifo1,
 
-    return RT_EOK; 
+    // masterConfig.sselNum = kSPI_Ssel3;
+    SPI_MasterInit(base, &masterConfig, get_spi_freq(base));
+
+    return RT_EOK;
 }
 
 rt_err_t lpc_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin)
 {
-    rt_err_t ret = RT_EOK; 
-    
-    struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); 
-    RT_ASSERT(spi_device != RT_NULL); 
-    
-    struct lpc_sw_spi_cs *cs_pin = (struct lpc_sw_spi_cs *)rt_malloc(sizeof(struct lpc_sw_spi_cs)); 
+    rt_err_t ret = RT_EOK;
+
+    struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
+    RT_ASSERT(spi_device != RT_NULL);
+
+    struct lpc_sw_spi_cs *cs_pin = (struct lpc_sw_spi_cs *)rt_malloc(sizeof(struct lpc_sw_spi_cs));
     RT_ASSERT(cs_pin != RT_NULL);
-    
+
     cs_pin->pin = pin;
-    rt_pin_mode(pin, PIN_MODE_OUTPUT); 
-    rt_pin_write(pin, PIN_HIGH); 
-    
-    ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); 
-    
-    return ret; 
+    rt_pin_mode(pin, PIN_MODE_OUTPUT);
+    rt_pin_write(pin, PIN_HIGH);
+
+    ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
+
+    return ret;
 }
 
 static rt_err_t configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg)
 {
-    rt_err_t ret = RT_EOK; 
-    struct lpc_spi *spi = RT_NULL; 
-    
+    rt_err_t ret = RT_EOK;
+    struct lpc_spi *spi = RT_NULL;
+
     RT_ASSERT(cfg != RT_NULL);
     RT_ASSERT(device != RT_NULL);
-    
-    spi = (struct lpc_spi *)(device->bus->parent.user_data); 
-    spi->cfg = cfg; 
-    ret = spi_init(spi->base, cfg); 
-    
+
+    spi = (struct lpc_spi *)(device->bus->parent.user_data);
+    spi->cfg = cfg;
+    ret = spi_init(spi->base, cfg);
+
     return ret;
 }
 
 static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
 {
-    spi_transfer_t transfer = {0}; 
-    
+    spi_transfer_t transfer = {0};
+
     RT_ASSERT(device != RT_NULL);
     RT_ASSERT(device->bus != RT_NULL);
     RT_ASSERT(device->bus->parent.user_data != RT_NULL);
-    
-    struct lpc_spi *spi = (struct lpc_spi *)(device->bus->parent.user_data); 
-    struct lpc_sw_spi_cs *cs = device->parent.user_data; 
-    
+
+    struct lpc_spi *spi = (struct lpc_spi *)(device->bus->parent.user_data);
+    struct lpc_sw_spi_cs *cs = device->parent.user_data;
+
     if(message->cs_take)
     {
         rt_pin_write(cs->pin, PIN_LOW);
     }
-    
-    transfer.dataSize = message->length; 
-    transfer.rxData   = (uint8_t *)(message->recv_buf); 
-    transfer.txData   = (uint8_t *)(message->send_buf); 
+
+    transfer.dataSize = message->length;
+    transfer.rxData   = (uint8_t *)(message->recv_buf);
+    transfer.txData   = (uint8_t *)(message->send_buf);
     transfer.configFlags |= kSPI_FrameAssert;
-    
-    SPI_MasterTransferBlocking(spi->base, &transfer); 
-    
+
+    SPI_MasterTransferBlocking(spi->base, &transfer);
+
     if(message->cs_release)
     {
         rt_pin_write(cs->pin, PIN_HIGH);
     }
-    
-    return message->length; 
+
+    return message->length;
 }
 
 #if defined(BSP_USING_SPI2)
-static struct lpc_spi spi2 = {0}; 
-static struct rt_spi_bus spi2_bus = {0}; 
+static struct lpc_spi spi2 = {0};
+static struct rt_spi_bus spi2_bus = {0};
 #endif
 
-static struct rt_spi_ops lpc_spi_ops = 
+static struct rt_spi_ops lpc_spi_ops =
 {
-    configure, 
+    configure,
     spixfer
-}; 
+};
 
 int rt_hw_spi_init(void)
 {
@@ -178,17 +178,17 @@ int rt_hw_spi_init(void)
     CLOCK_AttachClk(kFRO12M_to_FLEXCOMM2);
     RESET_PeripheralReset(kFC2_RST_SHIFT_RSTn);
 
-    spi2.base = SPI2; 
-    spi2.cfg = RT_NULL; 
-    spi2_bus.parent.user_data = &spi2; 
-    
+    spi2.base = SPI2;
+    spi2.cfg = RT_NULL;
+    spi2_bus.parent.user_data = &spi2;
+
     IOCON_PinMuxSet(IOCON, 0,  8, (IOCON_FUNC1 | IOCON_MODE_PULLUP | IOCON_GPIO_MODE | IOCON_DIGITAL_EN));  /* SPI2_MOSI */
     IOCON_PinMuxSet(IOCON, 0,  9, (IOCON_FUNC1 | IOCON_MODE_PULLUP | IOCON_GPIO_MODE | IOCON_DIGITAL_EN));  /* SPI2_MISO */
     IOCON_PinMuxSet(IOCON, 0, 10, (IOCON_FUNC1 | IOCON_MODE_PULLUP | IOCON_GPIO_MODE | IOCON_DIGITAL_EN));  /* SPI2_SCK  */
 
-    rt_spi_bus_register(&spi2_bus, "spi2", &lpc_spi_ops); 
+    rt_spi_bus_register(&spi2_bus, "spi2", &lpc_spi_ops);
 #endif
 
-    return RT_EOK; 
+    return RT_EOK;
 }
-INIT_BOARD_EXPORT(rt_hw_spi_init); 
+INIT_BOARD_EXPORT(rt_hw_spi_init);
diff --git a/bsp/lpc54114-lite/drivers/drv_spi.h b/bsp/lpc54114-lite/drivers/drv_spi.h
index c269cb9892..2938716aa4 100644
--- a/bsp/lpc54114-lite/drivers/drv_spi.h
+++ b/bsp/lpc54114-lite/drivers/drv_spi.h
@@ -1,21 +1,21 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  */
- 
-#ifndef __DRV_SPI_H__ 
-#define __DRV_SPI_H__ 
 
-#include  
-#include  
+#ifndef __DRV_SPI_H__
+#define __DRV_SPI_H__
+
+#include 
+#include 
 
 struct lpc_sw_spi_cs
 {
     rt_uint32_t pin;
-}; 
+};
 
 int rt_hw_spi_init(void);
-rt_err_t lpc_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin); 
+rt_err_t lpc_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin);
 
 #endif
diff --git a/bsp/lpc54114-lite/drivers/drv_spi_flash.c b/bsp/lpc54114-lite/drivers/drv_spi_flash.c
index 65433ce30c..11098636f9 100644
--- a/bsp/lpc54114-lite/drivers/drv_spi_flash.c
+++ b/bsp/lpc54114-lite/drivers/drv_spi_flash.c
@@ -1,14 +1,14 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  */
- 
-#include "drv_spi.h" 
+
+#include "drv_spi.h"
 #include "drv_spi_flash.h"
 
-#include "rtthread.h" 
-#include "rtdevice.h" 
+#include "rtthread.h"
+#include "rtdevice.h"
 #include "spi_flash.h"
 #include "spi_flash_sfud.h"
 
@@ -16,19 +16,19 @@
 
 int rt_hw_flash_init(void)
 {
-    rt_err_t result; 
-    
-    result = lpc_spi_bus_attach_device("spi2", "spi20", RT_SPI_FLASH_CS_PIN); 
-    if(result != RT_EOK) 
+    rt_err_t result;
+
+    result = lpc_spi_bus_attach_device("spi2", "spi20", RT_SPI_FLASH_CS_PIN);
+    if(result != RT_EOK)
     {
-        return result; 
+        return result;
     }
-    
-    if(rt_sfud_flash_probe("flash0", "spi20") == RT_NULL) 
+
+    if(rt_sfud_flash_probe("flash0", "spi20") == RT_NULL)
     {
         return RT_ERROR;
     }
 
-    return RT_EOK; 
+    return RT_EOK;
 }
-INIT_DEVICE_EXPORT(rt_hw_flash_init); 
+INIT_DEVICE_EXPORT(rt_hw_flash_init);
diff --git a/bsp/lpc54114-lite/drivers/drv_spi_flash.h b/bsp/lpc54114-lite/drivers/drv_spi_flash.h
index f3c71e06c2..50b941449e 100644
--- a/bsp/lpc54114-lite/drivers/drv_spi_flash.h
+++ b/bsp/lpc54114-lite/drivers/drv_spi_flash.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -10,6 +10,6 @@
 #ifndef __DRV_SPI_FLASH_H_
 #define __DRV_SPI_FLASH_H_
 
-int rt_hw_w25qxx_init(void); 
+int rt_hw_w25qxx_init(void);
 
 #endif
diff --git a/bsp/lpc54114-lite/drivers/drv_uart.c b/bsp/lpc54114-lite/drivers/drv_uart.c
index fc0999d4a4..0ccce7632c 100644
--- a/bsp/lpc54114-lite/drivers/drv_uart.c
+++ b/bsp/lpc54114-lite/drivers/drv_uart.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -42,14 +42,14 @@ static rt_err_t lpc_configure(struct rt_serial_device *serial, struct serial_con
      * config.enableRx = false;
      */
     USART_GetDefaultConfig(&u0_config);
-    
-    u0_config.baudRate_Bps = cfg->baud_rate;    
+
+    u0_config.baudRate_Bps = cfg->baud_rate;
     u0_config.parityMode = kUSART_ParityDisabled,
     u0_config.stopBitCount = kUSART_OneStopBit,
     u0_config.bitCountPerChar = kUSART_8BitsPerChar,
     u0_config.loopback = false,
     u0_config.txWatermark = kUSART_TxFifo0,
-    u0_config.rxWatermark = kUSART_RxFifo1,    
+    u0_config.rxWatermark = kUSART_RxFifo1,
     u0_config.enableTx = true;
     u0_config.enableRx = true;
 
@@ -143,7 +143,7 @@ int rt_hw_uart_init(void)
     struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
 
 #ifdef BSP_USING_UART0
-    
+
     uart = &uart0;
 
     serial0.ops    = &lpc_uart_ops;
@@ -152,40 +152,40 @@ int rt_hw_uart_init(void)
 
     /* attach 12 MHz clock to FLEXCOMM0 (debug console) */
     CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0);
-    
+
     /* reset FLEXCOMM for USART */
     RESET_PeripheralReset(kFC0_RST_SHIFT_RSTn);
-    
+
     /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */
     CLOCK_EnableClock(kCLOCK_Iocon);
-    
+
     const uint32_t port0_pin0_config = ((IOCON->PIO[PORT0_IDX][PIN0_IDX] &
-                                        (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK)))    /* Mask bits to zero which are setting */                                            
-                                        | IOCON_PIO_FUNC(1)                   /* Selects pin function: PORT00 (pin 31) is configured as FC0_RXD_SDA_MOSI. */                                            
-                                        | IOCON_PIO_DIGIMODE(1));             /* Select Analog/Digital mode : Digital mode. */              
-                    
-    IOCON_PinMuxSet(IOCON, PORT0_IDX, PIN0_IDX, port0_pin0_config);           /* PORT0 PIN0 (coords: 31) is configured as FC0_RXD_SDA_MOSI */
-    
-    const uint32_t port0_pin1_config = ((IOCON->PIO[PORT0_IDX][PIN1_IDX] &                                             
-                                        (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK)))    /* Mask bits to zero which are setting */                                            
-                                        | IOCON_PIO_FUNC(1)                   /* Selects pin function: PORT01 (pin 32) is configured as FC0_TXD_SCL_MISO. */                                            
+                                        (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK)))    /* Mask bits to zero which are setting */
+                                        | IOCON_PIO_FUNC(1)                   /* Selects pin function: PORT00 (pin 31) is configured as FC0_RXD_SDA_MOSI. */
                                         | IOCON_PIO_DIGIMODE(1));             /* Select Analog/Digital mode : Digital mode. */
-    
+
+    IOCON_PinMuxSet(IOCON, PORT0_IDX, PIN0_IDX, port0_pin0_config);           /* PORT0 PIN0 (coords: 31) is configured as FC0_RXD_SDA_MOSI */
+
+    const uint32_t port0_pin1_config = ((IOCON->PIO[PORT0_IDX][PIN1_IDX] &
+                                        (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK)))    /* Mask bits to zero which are setting */
+                                        | IOCON_PIO_FUNC(1)                   /* Selects pin function: PORT01 (pin 32) is configured as FC0_TXD_SCL_MISO. */
+                                        | IOCON_PIO_DIGIMODE(1));             /* Select Analog/Digital mode : Digital mode. */
+
     IOCON_PinMuxSet(IOCON, PORT0_IDX, PIN1_IDX, port0_pin1_config);           /* PORT0 PIN1 (coords: 32) is configured as FC0_TXD_SCL_MISO */
-    
+
     /* Enable RX interrupt. */
     USART_EnableInterrupts(uart->UART, kUSART_RxLevelInterruptEnable | kUSART_RxErrorInterruptEnable);
     EnableIRQ(uart->UART_IRQn);
-     
-    CLOCK_DisableClock(kCLOCK_Iocon);    
-    
+
+    CLOCK_DisableClock(kCLOCK_Iocon);
+
     /* register UART0 device */
     rt_hw_serial_register(&serial0, "uart0",
                           RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
                           uart);
 
-#endif    
-    
+#endif
+
     return 0;
 }
 INIT_BOARD_EXPORT(rt_hw_uart_init);
diff --git a/bsp/lpc54114-lite/drivers/drv_uart.h b/bsp/lpc54114-lite/drivers/drv_uart.h
index e066448d24..1bef2e50a6 100644
--- a/bsp/lpc54114-lite/drivers/drv_uart.h
+++ b/bsp/lpc54114-lite/drivers/drv_uart.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -13,4 +13,4 @@
 
 extern int rt_hw_uart_init(void);
 
-#endif 
+#endif
diff --git a/bsp/lpc54608-LPCXpresso/applications/application.c b/bsp/lpc54608-LPCXpresso/applications/application.c
index b85de95df6..bfb039472d 100644
--- a/bsp/lpc54608-LPCXpresso/applications/application.c
+++ b/bsp/lpc54608-LPCXpresso/applications/application.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -47,10 +47,10 @@ void link_dump(void)
 
     extern unsigned int _sbss;
     extern unsigned int _ebss;
-    
+
     #define DUMP_VAR(__VAR) \
         rt_kprintf("%-20s %p\n", #__VAR, &__VAR)
-    
+
     DUMP_VAR(_sdata);
     DUMP_VAR(_edata);
     DUMP_VAR(_sidata);
@@ -62,10 +62,10 @@ void link_dump(void)
 int rt_application_init(void)
 {
     rt_thread_t tid;
-    
+
     build_dump();
     link_dump();
-    
+
     tid = rt_thread_create("init",
                            rt_init_thread_entry, RT_NULL,
                            2048, RT_THREAD_PRIORITY_MAX / 3, 20);
diff --git a/bsp/lpc54608-LPCXpresso/applications/mnt.c b/bsp/lpc54608-LPCXpresso/applications/mnt.c
index dd1f862ea5..4a865340d9 100644
--- a/bsp/lpc54608-LPCXpresso/applications/mnt.c
+++ b/bsp/lpc54608-LPCXpresso/applications/mnt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -33,7 +33,7 @@ int mnt_init(void)
     dfs_romfs_init();
 
     /* mount rom file system */
-	if (dfs_mount(RT_NULL, "/", "rom", 0, &(romfs_root)) == 0)
+    if (dfs_mount(RT_NULL, "/", "rom", 0, &(romfs_root)) == 0)
     {
         rt_kprintf("ROM file system initializated!\n");
     }
@@ -44,14 +44,14 @@ int mnt_init(void)
      mci_hw_init("sd0");
 #endif
 
-#ifdef RT_DFS_ELM_REENTRANT    
+#ifdef RT_DFS_ELM_REENTRANT
     /* mount sd card fat partition 1 as root directory */
     if (dfs_mount("sd0", SD_ROOT, "elm", 0, 0) == 0)
         rt_kprintf("File System initialized!\n");
     else
         rt_kprintf("File System init failed!\n");
 #endif
-    
+
     return 0;
 }
 INIT_ENV_EXPORT(mnt_init);
diff --git a/bsp/lpc54608-LPCXpresso/applications/startup.c b/bsp/lpc54608-LPCXpresso/applications/startup.c
index 687cc0f864..fcd836cdac 100644
--- a/bsp/lpc54608-LPCXpresso/applications/startup.c
+++ b/bsp/lpc54608-LPCXpresso/applications/startup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -39,10 +39,10 @@ void rtthread_startup(void)
 
     /* initialize scheduler system */
     rt_system_scheduler_init();
-	
+
     /* initialize system timer*/
     rt_system_timer_init();
-	
+
     /* initialize application */
     rt_application_init();
 
diff --git a/bsp/lpc54608-LPCXpresso/drivers/board.c b/bsp/lpc54608-LPCXpresso/drivers/board.c
index 51c72ec3f5..decd9adfa3 100644
--- a/bsp/lpc54608-LPCXpresso/drivers/board.c
+++ b/bsp/lpc54608-LPCXpresso/drivers/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -41,7 +41,7 @@ void rt_hw_board_init()
 {
     /* Hardware Initialization */
     CLOCK_EnableClock(kCLOCK_InputMux);
-	CLOCK_EnableClock(kCLOCK_Iocon);
+    CLOCK_EnableClock(kCLOCK_Iocon);
 
     /* NVIC Configuration */
 #define NVIC_VTOR_MASK              0x3FFFFF80
@@ -54,15 +54,15 @@ void rt_hw_board_init()
 #endif
 
     BOARD_BootClockFROHF48M();
-    /* init systick  1 systick = 1/(100M / 100) 100systick = 1s*/
+    /* init systick  1 systick = 1/(100M / 100) 100个systick = 1s*/
     SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
     /* set pend exception priority */
     NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
 
     /*init uart device*/
     rt_hw_uart_init();
-    
-#ifdef RT_USING_CONSOLE    
+
+#ifdef RT_USING_CONSOLE
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
 
diff --git a/bsp/lpc54608-LPCXpresso/drivers/board.h b/bsp/lpc54608-LPCXpresso/drivers/board.h
index 679f33682f..db2ac831c5 100644
--- a/bsp/lpc54608-LPCXpresso/drivers/board.h
+++ b/bsp/lpc54608-LPCXpresso/drivers/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.c b/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.c
index c6c5d114e4..7e220327cb 100644
--- a/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.c
+++ b/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -26,9 +26,9 @@ int rt_hw_mpu_init(void)
 {
     uint32_t rbar;
     uint32_t rasr;
-    
+
     MPU_PRINT("\nnumber of regions: %d\n", (MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos);
-    
+
     /* Disable MPU */
     ARM_MPU_Disable();
 
diff --git a/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.h b/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.h
index ff34c225e7..782f6fce08 100644
--- a/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.h
+++ b/bsp/lpc54608-LPCXpresso/drivers/drt_mpu.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_emac.c b/bsp/lpc54608-LPCXpresso/drivers/drv_emac.c
index b432aea70e..394ad22cca 100644
--- a/bsp/lpc54608-LPCXpresso/drivers/drv_emac.c
+++ b/bsp/lpc54608-LPCXpresso/drivers/drv_emac.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -73,14 +73,14 @@ struct lpc_emac
     /* inherit from ethernet device */
     struct eth_device parent;
     struct rt_semaphore tx_wait;
-    
+
     ENET_Type *base;
     enet_handle_t handle;
-    
+
     /* interface address info. */
     rt_uint8_t  dev_addr[MAX_ADDR_LEN];     /* hw address   */
     uint32_t phyAddr;
-    
+
     uint8_t RxBuffDescrip[ENET_RXBD_NUM * sizeof(enet_rx_bd_struct_t) + ENET_BUFF_ALIGNMENT];
     uint8_t TxBuffDescrip[ENET_TXBD_NUM * sizeof(enet_tx_bd_struct_t) + ENET_BUFF_ALIGNMENT];
     uint8_t RxDataBuff[ENET_RXBD_NUM * ENET_ALIGN(ENET_RXBUFF_SIZE) + ENET_BUFF_ALIGNMENT];
@@ -273,7 +273,7 @@ static rt_err_t lpc_emac_phy_init(phy_speed_t * speed, phy_duplex_t * duplex)
 {
     bool link = false;
     int32_t status;
-    
+
     RT_ASSERT(speed != NULL);
     RT_ASSERT(duplex != NULL);
 
@@ -284,9 +284,9 @@ static rt_err_t lpc_emac_phy_init(phy_speed_t * speed, phy_duplex_t * duplex)
         *duplex = kPHY_HalfDuplex;
         /* 10M speed. */
         *speed = kPHY_Speed10M;
-        
+
         eth_device_linkchange(&lpc_emac_device.parent, RT_FALSE);
-        
+
         ETH_PRINTF("PHY_Init failed!\n");
         return RT_ERROR;
     }
@@ -305,7 +305,7 @@ static rt_err_t lpc_emac_phy_init(phy_speed_t * speed, phy_duplex_t * duplex)
     }
 
     PHY_GetLinkSpeedDuplex(lpc_emac_device.base, lpc_emac_device.phyAddr, speed, duplex);
-    
+
     eth_device_linkchange(&lpc_emac_device.parent, RT_TRUE);
 
     return RT_EOK;
@@ -338,19 +338,19 @@ static rt_err_t lpc_emac_init(rt_device_t dev)
     buffCfg.rxDescTailAddrAlign  = get_rx_desc(ENET_RXBD_NUM);
     buffCfg.rxBufferStartAddr    = rxBufferStartAddr;
     buffCfg.rxBuffSizeAlign      = ENET_ALIGN(ENET_RXBUFF_SIZE);
-    
+
     /* Get default configuration 100M RMII. */
     ENET_GetDefaultConfig(&config);
     /* Use the actual speed and duplex when phy success to finish the autonegotiation. */
     config.miiSpeed = (enet_mii_speed_t)speed;
     config.miiDuplex = (enet_mii_duplex_t)duplex;
-    
+
     ETH_PRINTF("Auto negotiation, Speed: ");
     if (config.miiSpeed == kENET_MiiSpeed100M)
         ETH_PRINTF("100M");
     else
         ETH_PRINTF("10M");
-    
+
     ETH_PRINTF(", Duplex: ");
     if (config.miiSpeed == kENET_MiiSpeed100M)
         ETH_PRINTF("Full\n");
@@ -363,10 +363,10 @@ static rt_err_t lpc_emac_init(rt_device_t dev)
     /* Enable the tx/rx interrupt. */
     ENET_EnableInterrupts(lpc_emac_device.base, (kENET_DmaTx | kENET_DmaRx));
     ENET_CreateHandler(lpc_emac_device.base, &lpc_emac_device.handle, &config, &buffCfg, ethernet_callback, NULL);
-    
+
     /* Initialize Descriptor. */
     ENET_DescriptorInit(lpc_emac_device.base, &config, &buffCfg);
-    
+
     /* Active TX/RX. */
     ENET_StartRxTx(lpc_emac_device.base, 1, 1);
 
@@ -416,23 +416,23 @@ static rt_err_t lpc_emac_control(rt_device_t dev, int cmd, void *args)
 /* transmit packet. */
 rt_err_t lpc_emac_tx(rt_device_t dev, struct pbuf *p)
 {
-	rt_err_t result = RT_EOK;
-	enet_handle_t * enet_handle = &lpc_emac_device.handle;
+    rt_err_t result = RT_EOK;
+    enet_handle_t * enet_handle = &lpc_emac_device.handle;
     ENET_Type *enet_base = lpc_emac_device.base;
     uint8_t * data;
-	
-	uint16_t 	len;
 
-	RT_ASSERT(p != NULL);
+    uint16_t    len;
+
+    RT_ASSERT(p != NULL);
     RT_ASSERT(enet_handle != RT_NULL);
 
     if (p->tot_len > ENET_TXBUFF_SIZE)
     {
         return RT_ERROR;
     }
-    
+
     packet_dump("TX dump", p);
-    
+
     /* get free tx buffer */
     {
         rt_err_t result;
@@ -442,18 +442,18 @@ rt_err_t lpc_emac_tx(rt_device_t dev, struct pbuf *p)
             return RT_ERROR;
         }
     }
-    
-	//	fix RxDataBuff -> TxDataBuff, ENET_RXBUFF_SIZE -> ENET_TXBUFF_SIZE
+
+    //  fix RxDataBuff -> TxDataBuff, ENET_RXBUFF_SIZE -> ENET_TXBUFF_SIZE
     data = (uint8_t *)ENET_ALIGN(&lpc_emac_device.TxDataBuff[lpc_emac_device.txIdx * ENET_ALIGN(ENET_TXBUFF_SIZE)]);
     len = pbuf_copy_partial(p, data, p->tot_len, 0);
     lpc_emac_device.txIdx = (lpc_emac_device.txIdx + 1) / ENET_TXBD_NUM;
-    
-	// fix 'p->len' to 'len', avoid send wrong partial packet.
+
+    // fix 'p->len' to 'len', avoid send wrong partial packet.
     result = ENET_SendFrame(enet_base, enet_handle, data, len);
-        
+
     if ((result == kStatus_ENET_TxFrameFail) || (result == kStatus_ENET_TxFrameOverLen) || (result == kStatus_ENET_TxFrameBusy))
     {
-        return RT_ERROR; 
+        return RT_ERROR;
     }
 
     return RT_EOK;
@@ -462,22 +462,22 @@ rt_err_t lpc_emac_tx(rt_device_t dev, struct pbuf *p)
 /* reception packet. */
 struct pbuf *lpc_emac_rx(rt_device_t dev)
 {
-  	uint32_t length = 0;
-	status_t status;
-    
-	struct pbuf* p = RT_NULL;
-	enet_handle_t * enet_handle = &lpc_emac_device.handle;
-    ENET_Type *enet_base = lpc_emac_device.base;
-    
-	/* Get the Frame size */
-	status = ENET_GetRxFrameSize(enet_base, enet_handle, &length, 0);
+    uint32_t length = 0;
+    status_t status;
+
+    struct pbuf* p = RT_NULL;
+    enet_handle_t * enet_handle = &lpc_emac_device.handle;
+    ENET_Type *enet_base = lpc_emac_device.base;
+
+    /* Get the Frame size */
+    status = ENET_GetRxFrameSize(enet_base, enet_handle, &length, 0);
+
+    /* Call ENET_ReadFrame when there is a received frame. */
+    if (length != 0)
+    {
+        /* Received valid frame. Deliver the rx buffer with the size equal to length. */
+        p = pbuf_alloc(PBUF_RAW, length, PBUF_POOL);
 
-	/* Call ENET_ReadFrame when there is a received frame. */
-	if (length != 0)
-	{
-		/* Received valid frame. Deliver the rx buffer with the size equal to length. */
-		p = pbuf_alloc(PBUF_RAW, length, PBUF_POOL);
-        
         if (p != NULL)
         {
             status = ENET_ReadFrame(enet_base, enet_handle, p->payload, length, 0);
@@ -496,12 +496,12 @@ struct pbuf *lpc_emac_rx(rt_device_t dev)
         {
             ETH_PRINTF(" pbuf_alloc faild\n");
         }
-	}
-	else if (status == kStatus_ENET_RxFrameError)
-	{
-		ETH_PRINTF("ENET_GetRxFrameSize: kStatus_ENET_RxFrameError\n");
-		ENET_ReadFrame(enet_base, enet_handle, NULL, 0, 0);
-	}
+    }
+    else if (status == kStatus_ENET_RxFrameError)
+    {
+        ETH_PRINTF("ENET_GetRxFrameSize: kStatus_ENET_RxFrameError\n");
+        ENET_ReadFrame(enet_base, enet_handle, NULL, 0, 0);
+    }
 
     return NULL;
 }
@@ -510,11 +510,11 @@ int lpc_emac_hw_init(void)
 {
     /* init tx semaphore */
     rt_sem_init(&lpc_emac_device.tx_wait, "tx_wait", ENET_TXBD_NUM, RT_IPC_FLAG_FIFO);
-    
+
     lpc_emac_device.phyAddr = 0;
     lpc_emac_device.txIdx = 0;
     lpc_emac_device.base = ENET;
-    
+
     // OUI 00-60-37 NXP Semiconductors
     lpc_emac_device.dev_addr[0] = 0x00;
     lpc_emac_device.dev_addr[1] = 0x60;
@@ -536,7 +536,7 @@ int lpc_emac_hw_init(void)
     lpc_emac_device.parent.eth_tx           = lpc_emac_tx;
 
     eth_device_init(&(lpc_emac_device.parent), "e0");
-    
+
     return 0;
 }
 INIT_DEVICE_EXPORT(lpc_emac_hw_init);
@@ -546,7 +546,7 @@ int emac_stat(void)
 {
     rt_kprintf("enter rx isr coutner : %d\n", isr_rx_counter);
     rt_kprintf("enter tx isr coutner : %d\n", isr_tx_counter);
-    
+
     return 0;
 }
 #endif
@@ -556,14 +556,14 @@ void phy_dump(void)
     status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr);
 
     int i;
-    
+
     for (i = 0; i < 31; i++)
     {
         status_t result = kStatus_Success;
         uint32_t reg;
-        
+
         result = PHY_Read(lpc_emac_device.base, lpc_emac_device.phyAddr, i, ®);
-        
+
         if (result == kStatus_Success)
         {
             rt_kprintf("%02d: %08d\n", i, reg);
@@ -630,7 +630,7 @@ void emac_dump(void)
     DUMP_REG(DMA_SYSBUS_MODE);
     DUMP_REG(DMA_INTR_STAT);
     DUMP_REG(DMA_DBG_STAT);
-    
+
     DUMP_REG(MTL_QUEUE[0].MTL_TXQX_OP_MODE);
     DUMP_REG(MTL_QUEUE[0].MTL_TXQX_UNDRFLW);
     DUMP_REG(MTL_QUEUE[0].MTL_TXQX_DBG);
@@ -660,7 +660,7 @@ void emac_dump(void)
     DUMP_REG(MTL_QUEUE[1].MTL_RXQX_MISSPKT_OVRFLW_CNT);
     DUMP_REG(MTL_QUEUE[1].MTL_RXQX_DBG);
     DUMP_REG(MTL_QUEUE[1].MTL_RXQX_CTRL);
-                                      
+
     DUMP_REG(DMA_CH[0].DMA_CHX_CTRL);
     DUMP_REG(DMA_CH[0].DMA_CHX_TX_CTRL);
     DUMP_REG(DMA_CH[0].DMA_CHX_RX_CTRL);
@@ -678,7 +678,7 @@ void emac_dump(void)
     DUMP_REG(DMA_CH[0].DMA_CHX_CUR_HST_TXBUF);
     DUMP_REG(DMA_CH[0].DMA_CHX_CUR_HST_RXBUF);
     DUMP_REG(DMA_CH[0].DMA_CHX_STAT);
-    
+
     DUMP_REG(DMA_CH[1].DMA_CHX_CTRL);
     DUMP_REG(DMA_CH[1].DMA_CHX_TX_CTRL);
     DUMP_REG(DMA_CH[1].DMA_CHX_RX_CTRL);
@@ -701,23 +701,23 @@ void emac_dump(void)
 void emac_bd_dump(void)
 {
     int i;
-    
+
     rt_kprintf("rx bd dump: \n");
     for (i = 0; i < ENET_RXBD_NUM; i++)
     {
         enet_rx_bd_struct_t * rx_bd = get_rx_desc(i);
-        rt_kprintf("buf1: %p, buf2: %p, ctrl: %08x\n", 
-                        rx_bd->buff1Addr, 
+        rt_kprintf("buf1: %p, buf2: %p, ctrl: %08x\n",
+                        rx_bd->buff1Addr,
                         rx_bd->buff2Addr,
                         rx_bd->control);
     }
-    
+
     rt_kprintf("tx bd dump: \n");
     for (i = 0; i < ENET_TXBD_NUM; i++)
     {
         enet_tx_bd_struct_t * tx_bd = get_tx_desc(i);
-        rt_kprintf("buf1: %p, buf2: %p, len: %08x, ctrl: %08x\n", 
-                        tx_bd->buff1Addr, 
+        rt_kprintf("buf1: %p, buf2: %p, len: %08x, ctrl: %08x\n",
+                        tx_bd->buff1Addr,
                         tx_bd->buff2Addr,
                         tx_bd->buffLen,
                         tx_bd->controlStat);
diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_emac.h b/bsp/lpc54608-LPCXpresso/drivers/drv_emac.h
index efaa0ac8e3..cde6d2742e 100644
--- a/bsp/lpc54608-LPCXpresso/drivers/drv_emac.h
+++ b/bsp/lpc54608-LPCXpresso/drivers/drv_emac.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_ft5406.c b/bsp/lpc54608-LPCXpresso/drivers/drv_ft5406.c
index fd46a199c0..c87d2039f3 100644
--- a/bsp/lpc54608-LPCXpresso/drivers/drv_ft5406.c
+++ b/bsp/lpc54608-LPCXpresso/drivers/drv_ft5406.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2017-08-08     Yang        the first version
  */
- 
+
 #include 
 #include 
 #include 
diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_i2c.c b/bsp/lpc54608-LPCXpresso/drivers/drv_i2c.c
index 39e08af2d3..1a6b5ff3b8 100644
--- a/bsp/lpc54608-LPCXpresso/drivers/drv_i2c.c
+++ b/bsp/lpc54608-LPCXpresso/drivers/drv_i2c.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2017-08-08     Yang        the first version
  */
- 
+
 #include 
 #include 
 #include "board.h"
diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_lcd.c b/bsp/lpc54608-LPCXpresso/drivers/drv_lcd.c
index c1a6660819..260fb09f0e 100644
--- a/bsp/lpc54608-LPCXpresso/drivers/drv_lcd.c
+++ b/bsp/lpc54608-LPCXpresso/drivers/drv_lcd.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2017-08-08     Yang        the first version
  */
- 
+
 #include 
 #include 
 #include 
@@ -427,7 +427,7 @@ void rt_hw_lcd_init(void)
     _rt_framebuffer = rt_malloc_align(sizeof(rt_uint16_t) * RT_HW_LCD_HEIGHT * RT_HW_LCD_WIDTH, 32);
     if (_rt_framebuffer == RT_NULL) return; /* no memory yet */
     _lcd_info.bits_per_pixel = LCD_BITS_PER_PIXEL;
-    _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565;		// RTGRAPHIC_PIXEL_FORMAT_ARGB888
+    _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565;     // RTGRAPHIC_PIXEL_FORMAT_ARGB888
     _lcd_info.framebuffer = (void *)_rt_framebuffer;
     _lcd_info.width = RT_HW_LCD_WIDTH;
     _lcd_info.height = RT_HW_LCD_HEIGHT;
diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_sd.c b/bsp/lpc54608-LPCXpresso/drivers/drv_sd.c
index e1239b7899..f5efc2a9d7 100644
--- a/bsp/lpc54608-LPCXpresso/drivers/drv_sd.c
+++ b/bsp/lpc54608-LPCXpresso/drivers/drv_sd.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -394,22 +394,22 @@ rt_err_t mci_hw_init(const char *device_name)
         rt_kprintf("SD_Init failed!\n");
         return -RT_ERROR;
     }
-	
-	/*
-	follow the page: https://community.nxp.com/thread/454769
-	
-	The issue concerns sdmmc library bug (I finally solved) in SD_Init() in the file sdmmc/src/fsl_sd.c:SD_SelectBusTiming() 
-	calls SD_SwitchFunction() which sets block size to 64bytes (512bits).Therefore SD_SetBlockSize(card, FSL_SDMMC_DEFAULT_BLOCK_SIZE)
-	should be called again before SD_Init() exits.
-	*/
-	
-	if (kStatus_Success != SDMMC_SetBlockSize(_mci_device->card.host.base, _mci_device->card.host.transfer, FSL_SDMMC_DEFAULT_BLOCK_SIZE))
-	{
+
+    /*
+    follow the page: https://community.nxp.com/thread/454769
+
+    The issue concerns sdmmc library bug (I finally solved) in SD_Init() in the file sdmmc/src/fsl_sd.c:SD_SelectBusTiming()
+    calls SD_SwitchFunction() which sets block size to 64bytes (512bits).Therefore SD_SetBlockSize(card, FSL_SDMMC_DEFAULT_BLOCK_SIZE)
+    should be called again before SD_Init() exits.
+    */
+
+    if (kStatus_Success != SDMMC_SetBlockSize(_mci_device->card.host.base, _mci_device->card.host.transfer, FSL_SDMMC_DEFAULT_BLOCK_SIZE))
+    {
         SD_Deinit(&_mci_device->card);
         memset(&_mci_device->card, 0U, sizeof(_mci_device->card));
         rt_kprintf("SD_Init failed!\n");
-        return -RT_ERROR;		
-	}
+        return -RT_ERROR;
+    }
 
     /* initialize mutex lock */
     rt_mutex_init(&_mci_device->lock, device_name, RT_IPC_FLAG_FIFO);
diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_sd.h b/bsp/lpc54608-LPCXpresso/drivers/drv_sd.h
index d36134eaa4..1fc53a7459 100644
--- a/bsp/lpc54608-LPCXpresso/drivers/drv_sd.h
+++ b/bsp/lpc54608-LPCXpresso/drivers/drv_sd.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -50,7 +50,7 @@ struct mci_device
 {
     struct rt_device                parent;      /**< RT-Thread device struct */
     struct rt_device_blk_geometry   geometry;    /**< sector size, sector count */
-    sd_card_t                   	card;   	 /**< Card descriptor */
+    sd_card_t                       card;        /**< Card descriptor */
     rt_event_t finish_event;                     /**< data send finish event*/
     rt_bool_t data_error;                        /**< data send error*/
     struct rt_mutex lock;
diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_sdram.c b/bsp/lpc54608-LPCXpresso/drivers/drv_sdram.c
index 9b6438c4d2..2270e7ed72 100644
--- a/bsp/lpc54608-LPCXpresso/drivers/drv_sdram.c
+++ b/bsp/lpc54608-LPCXpresso/drivers/drv_sdram.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2017-08-02     Yang        the first version
  */
- 
+
 #include "drv_sdram.h"
 
 #include 
@@ -15,10 +15,10 @@
 
 
 /*******************************************************************************************
-* @sdram_gpio_config()
-* @  void
-* @ֵvoid
-* @  SDRAMܽúڲ
+* @函数名：sdram_gpio_config()
+* @参数  ：void
+* @返回值：void
+* @描述  ：SDRAM管脚配置函数，内部调用
 *********************************************************************************************/
 static void  sdram_gpio_config(void)
 {
diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_sdram.h b/bsp/lpc54608-LPCXpresso/drivers/drv_sdram.h
index 4de79410b0..1d9a9db4aa 100644
--- a/bsp/lpc54608-LPCXpresso/drivers/drv_sdram.h
+++ b/bsp/lpc54608-LPCXpresso/drivers/drv_sdram.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_sram.c b/bsp/lpc54608-LPCXpresso/drivers/drv_sram.c
index 81f4ba6e9c..4b27d23fa1 100644
--- a/bsp/lpc54608-LPCXpresso/drivers/drv_sram.c
+++ b/bsp/lpc54608-LPCXpresso/drivers/drv_sram.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_sram.h b/bsp/lpc54608-LPCXpresso/drivers/drv_sram.h
index 14c87054ff..7abc19420f 100644
--- a/bsp/lpc54608-LPCXpresso/drivers/drv_sram.h
+++ b/bsp/lpc54608-LPCXpresso/drivers/drv_sram.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc54608-LPCXpresso/drivers/drv_uart.c b/bsp/lpc54608-LPCXpresso/drivers/drv_uart.c
index 7c9bd9fc7f..ce9e48fdad 100644
--- a/bsp/lpc54608-LPCXpresso/drivers/drv_uart.c
+++ b/bsp/lpc54608-LPCXpresso/drivers/drv_uart.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -146,7 +146,7 @@ void rt_hw_uart_init(void)
     struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
 
 #ifdef RT_USING_UART0
-    
+
     uart = &uart0;
 
     serial0.ops    = &lpc_uart_ops;
@@ -188,5 +188,5 @@ void rt_hw_uart_init(void)
     rt_hw_serial_register(&serial0, "uart0",
                           RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
                           uart);
-#endif    
+#endif
 }
diff --git a/bsp/lpc54608-LPCXpresso/drivers/fsl_phy.c b/bsp/lpc54608-LPCXpresso/drivers/fsl_phy.c
index 70fa7b3dc8..6a522d7ad7 100644
--- a/bsp/lpc54608-LPCXpresso/drivers/fsl_phy.c
+++ b/bsp/lpc54608-LPCXpresso/drivers/fsl_phy.c
@@ -87,7 +87,7 @@ status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
     while ((idReg != PHY_CONTROL_ID1) && (delay != 0))
     {
         PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg);
-        delay --;       
+        delay --;
     }
 
     if (!delay)
@@ -224,7 +224,7 @@ status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status)
         else
         {
             *status = false;
-        }        
+        }
     }
     return result;
 }
@@ -260,7 +260,7 @@ status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *
         else
         { /* 10M speed. */
             *speed = kPHY_Speed10M;
-        }        
+        }
     }
     return result;
 }
diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_adc.c b/bsp/lpc55sxx/Libraries/drivers/drv_adc.c
index e1f79c2429..d7d29f0728 100644
--- a/bsp/lpc55sxx/Libraries/drivers/drv_adc.c
+++ b/bsp/lpc55sxx/Libraries/drivers/drv_adc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -34,7 +34,7 @@ static rt_err_t lpc_lpadc_convert(struct rt_adc_device *device, rt_uint32_t chan
     lpadc_conv_trigger_config_t mLpadcTriggerConfigStruct;
     lpadc_conv_command_config_t mLpadcCommandConfigStruct;
     lpadc_conv_result_t mLpadcResultConfigStruct;
-    
+
     ADC_Type *base;
     base = (ADC_Type *)(device->parent.user_data);
 
@@ -42,13 +42,13 @@ static rt_err_t lpc_lpadc_convert(struct rt_adc_device *device, rt_uint32_t chan
     LPADC_GetDefaultConvCommandConfig(&mLpadcCommandConfigStruct);
     mLpadcCommandConfigStruct.channelNumber = channel;
     LPADC_SetConvCommandConfig(base, 1U, &mLpadcCommandConfigStruct);
-    
+
     /* Set trigger configuration. */
     LPADC_GetDefaultConvTriggerConfig(&mLpadcTriggerConfigStruct);
     mLpadcTriggerConfigStruct.targetCommandId       = 1U;
     mLpadcTriggerConfigStruct.enableHardwareTrigger = false;
     LPADC_SetConvTriggerConfig(base, 0U, &mLpadcTriggerConfigStruct); /* Configurate the trigger0. */
-    
+
     LPADC_DoSoftwareTrigger(base, 1U); /* 1U is trigger0 mask. */
     while (!LPADC_GetConvResult(base, &mLpadcResultConfigStruct, 0U));
 
@@ -74,12 +74,12 @@ int rt_hw_adc_init(void)
 
 #if defined(BSP_USING_ADC0_CH0)
     lpadc_config_t mLpadcConfigStruct;
-    
+
     CLOCK_SetClkDiv(kCLOCK_DivAdcAsyncClk, 16U, true);
     CLOCK_AttachClk(kMAIN_CLK_to_ADC_CLK);
     /* Disable LDOGPADC power down */
     POWER_DisablePD(kPDRUNCFG_PD_LDOGPADC);
-    
+
     LPADC_GetDefaultConfig(&mLpadcConfigStruct);
     mLpadcConfigStruct.enableAnalogPreliminary = true;
     mLpadcConfigStruct.referenceVoltageSource = kLPADC_ReferenceVoltageAlt2;
@@ -91,7 +91,7 @@ int rt_hw_adc_init(void)
     LPADC_SetOffsetValue(ADC0, 10U, 10U);
     /* Request gain calibration. */
     LPADC_DoAutoCalibration(ADC0);
-    
+
     result = rt_hw_adc_register(&adc0_device, "adc0", &lpc_adc_ops, ADC0);
 
     if (result != RT_EOK)
diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_adc.h b/bsp/lpc55sxx/Libraries/drivers/drv_adc.h
index 0113b54f3e..412b5f3cd2 100644
--- a/bsp/lpc55sxx/Libraries/drivers/drv_adc.h
+++ b/bsp/lpc55sxx/Libraries/drivers/drv_adc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_hwtimer.c b/bsp/lpc55sxx/Libraries/drivers/drv_hwtimer.c
index bbaf2d6704..6014317b63 100644
--- a/bsp/lpc55sxx/Libraries/drivers/drv_hwtimer.c
+++ b/bsp/lpc55sxx/Libraries/drivers/drv_hwtimer.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -31,15 +31,15 @@ static void NVIC_Configuration(void)
 #ifdef BSP_USING_CTIMER1
     EnableIRQ(CTIMER1_IRQn);
 #endif
-    
+
 #ifdef BSP_USING_CTIMER2
     EnableIRQ(CTIMER2_IRQn);
 #endif
-    
+
 #ifdef BSP_USING_CTIMER3
     EnableIRQ(CTIMER3_IRQn);
 #endif
-    
+
 #ifdef BSP_USING_CTIMER4
     EnableIRQ(CTIMER4_IRQn);
 #endif
@@ -64,9 +64,9 @@ static rt_err_t lpc_ctimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *a
         if(hwtimer_dev == CTIMER2) clk = CLOCK_GetFreq(kCLOCK_CTimer2);
         if(hwtimer_dev == CTIMER3) clk = CLOCK_GetFreq(kCLOCK_CTimer3);
         if(hwtimer_dev == CTIMER4) clk = CLOCK_GetFreq(kCLOCK_CTimer4);
-        
+
         pre = clk / *((uint32_t *)args) - 1;
-        
+
         hwtimer_dev->PR = pre;
     }
     break;
@@ -97,16 +97,16 @@ static void lpc_ctimer_init(rt_hwtimer_t *timer, rt_uint32_t state)
     hwtimer_dev = (CTIMER_Type *)timer->parent.user_data;
 
     RT_ASSERT(timer != RT_NULL);
-    
+
     /* Use Main clock for some of the Ctimers */
     if(hwtimer_dev == CTIMER0) CLOCK_AttachClk(kMAIN_CLK_to_CTIMER0);
     if(hwtimer_dev == CTIMER1) CLOCK_AttachClk(kMAIN_CLK_to_CTIMER1);
     if(hwtimer_dev == CTIMER2) CLOCK_AttachClk(kMAIN_CLK_to_CTIMER2);
     if(hwtimer_dev == CTIMER3) CLOCK_AttachClk(kMAIN_CLK_to_CTIMER3);
     if(hwtimer_dev == CTIMER4) CLOCK_AttachClk(kMAIN_CLK_to_CTIMER4);
-    
+
     CTIMER_Deinit(hwtimer_dev);
-    
+
     if (state == 1)
     {
         NVIC_Configuration();
@@ -121,7 +121,7 @@ static rt_err_t lpc_ctimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtime
     hwtimer_dev = (CTIMER_Type *)timer->parent.user_data;
     /* Match Configuration for Channel 0 */
     ctimer_match_config_t matchCfg;
-    
+
     RT_ASSERT(timer != RT_NULL);
 
     /* Configuration*/
@@ -131,13 +131,13 @@ static rt_err_t lpc_ctimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtime
     matchCfg.outControl         = kCTIMER_Output_NoAction;
     matchCfg.outPinInitState    = false;
     matchCfg.enableInterrupt    = true;
-    
+
     CTIMER_SetupMatch(hwtimer_dev, kCTIMER_Match_1, &matchCfg);
-    
+
     NVIC_Configuration();
 
     CTIMER_StartTimer(hwtimer_dev);
-    
+
     return RT_EOK;
 }
 
@@ -213,7 +213,7 @@ int rt_hw_hwtimer_init(void)
         LOG_E("CTIMER1 register failed\n");
     }
 #endif
-    
+
 #ifdef BSP_USING_CTIMER2
     CTimer2.info = &lpc_hwtimer_info;
     CTimer2.ops  = &lpc_hwtimer_ops;
@@ -224,7 +224,7 @@ int rt_hw_hwtimer_init(void)
         LOG_E("CTIMER2 register failed\n");
     }
 #endif
-    
+
 #ifdef BSP_USING_CTIMER3
     CTimer3.info = &lpc_hwtimer_info;
     CTimer3.ops  = &lpc_hwtimer_ops;
@@ -235,7 +235,7 @@ int rt_hw_hwtimer_init(void)
         LOG_E("CTIMER3 register failed\n");
     }
 #endif
-    
+
 #ifdef BSP_USING_CTIMER4
     CTimer4.info = &lpc_hwtimer_info;
     CTimer4.ops  = &lpc_hwtimer_ops;
@@ -246,7 +246,7 @@ int rt_hw_hwtimer_init(void)
         LOG_E("CTIMER4 register failed\n");
     }
 #endif
-    
+
     return ret;
 }
 
diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_hwtimer.h b/bsp/lpc55sxx/Libraries/drivers/drv_hwtimer.h
index 441665c6e8..04d64d79e4 100644
--- a/bsp/lpc55sxx/Libraries/drivers/drv_hwtimer.h
+++ b/bsp/lpc55sxx/Libraries/drivers/drv_hwtimer.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_i2c.c b/bsp/lpc55sxx/Libraries/drivers/drv_i2c.c
index 45273f1552..53361bdd40 100644
--- a/bsp/lpc55sxx/Libraries/drivers/drv_i2c.c
+++ b/bsp/lpc55sxx/Libraries/drivers/drv_i2c.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2019-07-15     Magicoe      The first version for LPC55S6x
  */
- 
+
 #include 
 #include 
 #include "board.h"
@@ -86,7 +86,7 @@ out:
 }
 
 static const struct rt_i2c_bus_device_ops i2c_ops =
-{    
+{
 
     lpc_i2c_xfer,
     RT_NULL,
@@ -115,7 +115,7 @@ int rt_hw_i2c_init(void)
     lpc_i2c1.device_name = "LPC Flexcomm1 as I2C";
     rt_i2c_bus_device_register(&lpc_i2c1.parent, "i2c1");
 #endif /* BSP_USING_I2C1 */
-    
+
 #ifdef BSP_USING_I2C4
     static struct lpc_i2c_bus lpc_i2c4;
     /* attach 12 MHz clock to FLEXCOMM2 (I2C master for touch controller) */
diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_i2c.h b/bsp/lpc55sxx/Libraries/drivers/drv_i2c.h
index ac303c7367..87b576f30d 100644
--- a/bsp/lpc55sxx/Libraries/drivers/drv_i2c.h
+++ b/bsp/lpc55sxx/Libraries/drivers/drv_i2c.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -8,12 +8,12 @@
  * 2018-03-15     Liuguang     the first version.
  * 2019-07-19     Magicoe      The first version for LPC55S6x
  */
- 
+
 #ifndef __DRV_RTC_H__
 #define __DRV_RTC_H__
 
-#include  
-#include  
+#include 
+#include 
 
 extern int rt_hw_i2c_init(void);
 
diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_key.c b/bsp/lpc55sxx/Libraries/drivers/drv_key.c
index 3f8188febe..930c2c706b 100644
--- a/bsp/lpc55sxx/Libraries/drivers/drv_key.c
+++ b/bsp/lpc55sxx/Libraries/drivers/drv_key.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -47,11 +47,11 @@ int my_button_register(struct my_button *button)
     {
         rt_pin_mode(button->pin, PIN_MODE_INPUT_PULLDOWN);
     }
-    
+
     button->cnt = 0;
     button->event = BUTTON_EVENT_NONE;
     button_manage.button_list[button_manage.num++] = button;
-    
+
     return 0;
 }
 
@@ -100,7 +100,7 @@ static void my_button_scan(void *param)
             else if (cnt_old >= MY_BUTTON_HOLD_MS / MY_BUTTON_SCAN_SPACE_MS) /* BUTTON_HOLD_UP */
             {
                 LOG_D("BUTTON_HOLD_UP");
-                button_manage.button_list[i]->event = BUTTON_EVENT_HOLD_UP; 
+                button_manage.button_list[i]->event = BUTTON_EVENT_HOLD_UP;
                 MY_BUTTON_CALL(button_manage.button_list[i]->cb, (button_manage.button_list[i]));
             }
         }
@@ -117,7 +117,7 @@ int my_button_start(void)
                              my_button_scan,        /* Timeout callback func */
                              RT_NULL,               /* Timeout func entry */
                              RT_TICK_PER_SECOND * MY_BUTTON_SCAN_SPACE_MS / 1000,
-                             RT_TIMER_FLAG_PERIODIC | RT_TIMER_FLAG_SOFT_TIMER); 
+                             RT_TIMER_FLAG_PERIODIC | RT_TIMER_FLAG_SOFT_TIMER);
     /* Start Timer */
     if (button_manage.timer != RT_NULL)
         rt_timer_start(button_manage.timer);
@@ -159,7 +159,7 @@ void key_test(rt_uint32_t led_num, rt_uint32_t value)
     key.pin = KEY_PIN;
 
     my_button_register(&key);
-    
+
     my_button_start();
 }
 MSH_CMD_EXPORT(key_test, key_test);
diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_key.h b/bsp/lpc55sxx/Libraries/drivers/drv_key.h
index b0fb9d4095..f8a65370f0 100644
--- a/bsp/lpc55sxx/Libraries/drivers/drv_key.h
+++ b/bsp/lpc55sxx/Libraries/drivers/drv_key.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,12 +7,12 @@
  * Date           Author       Notes
  * 2019-07-19     Magicoe      The first version for LPC55S6x, refered github.com/Guozhanxin/RTT-BeepPlayer-pkg
  */
- 
+
 #ifndef __DRV_KEY_H__
 #define __DRV_KEY_H__
 
-#include  
-#include  
+#include 
+#include 
 
 #define MY_BUTTON_DOWN_MS        50
 #define MY_BUTTON_HOLD_MS        700
diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_led.c b/bsp/lpc55sxx/Libraries/drivers/drv_led.c
index d7c5a32ef7..922982f654 100644
--- a/bsp/lpc55sxx/Libraries/drivers/drv_led.c
+++ b/bsp/lpc55sxx/Libraries/drivers/drv_led.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_led.h b/bsp/lpc55sxx/Libraries/drivers/drv_led.h
index de45db9063..65f55668b6 100644
--- a/bsp/lpc55sxx/Libraries/drivers/drv_led.h
+++ b/bsp/lpc55sxx/Libraries/drivers/drv_led.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,12 +7,12 @@
  * Date           Author       Notes
  * 2019-07-19     Magicoe      The first version for LPC55S6x
  */
- 
+
 #ifndef __DRV_LED_H__
 #define __DRV_LED_H__
 
-#include  
-#include  
+#include 
+#include 
 
 int rt_hw_led_init(void);
 
diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_log.h b/bsp/lpc55sxx/Libraries/drivers/drv_log.h
index 7e0bfee5b4..3fe511789b 100644
--- a/bsp/lpc55sxx/Libraries/drivers/drv_log.h
+++ b/bsp/lpc55sxx/Libraries/drivers/drv_log.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_mma8562.c b/bsp/lpc55sxx/Libraries/drivers/drv_mma8562.c
index e009c86842..80b3b2671b 100644
--- a/bsp/lpc55sxx/Libraries/drivers/drv_mma8562.c
+++ b/bsp/lpc55sxx/Libraries/drivers/drv_mma8562.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -35,7 +35,7 @@ rt_err_t mma8562_read_reg(rt_uint8_t reg, rt_uint8_t len, rt_uint8_t *buf)
     struct rt_i2c_msg msgs[2];
 
     msgs[0].addr  = kMMA8562_ADDR;
-    msgs[0].flags = RT_I2C_WR; 
+    msgs[0].flags = RT_I2C_WR;
     msgs[0].buf   = ®
     msgs[0].len   = 1;
 
@@ -60,7 +60,7 @@ rt_err_t mma8562_write_reg(rt_uint8_t reg, rt_uint8_t data)
 
     buf[0] = reg;
     buf[1] = data;
-       
+
     if (rt_i2c_master_send(mma8562_i2c_bus, kMMA8562_ADDR, 0, buf ,2) == 2)
     {
         return RT_EOK;
@@ -78,15 +78,15 @@ rt_err_t mma8562_write_reg(rt_uint8_t reg, rt_uint8_t data)
 void get_mma8562(uint8_t data)
 {
     volatile acceleration_t accel;
-    
+
     uint8_t ucVal1 = 0;
     uint8_t ucVal2 = 0;
     uint8_t ucStatus = 0;
-    
+
     do {
        mma8562_read_reg(kMMA8562_STATUS, 1, &ucStatus);
     } while (!(ucStatus & 0x08));
-    
+
     mma8562_read_reg(kMMA8562_OUT_X_MSB, 1, &ucVal1);
     mma8562_read_reg(kMMA8562_OUT_X_LSB, 1, &ucVal2);
 
@@ -150,7 +150,7 @@ int mma8562_hw_init(void)
     /*   databyte = 0x0D; */
     val = 0x0D;
     mma8562_write_reg(kMMA8562_CTRL_REG1, val);
-    
+
     return 0;
 }
 
diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_pin.c b/bsp/lpc55sxx/Libraries/drivers/drv_pin.c
index 48d26a5825..d38a7ead9a 100644
--- a/bsp/lpc55sxx/Libraries/drivers/drv_pin.c
+++ b/bsp/lpc55sxx/Libraries/drivers/drv_pin.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -83,8 +83,8 @@ static struct lpc_pin lpc_pin_map[] =
     __LPC55S69_PIN(30, GPIO, 0, 29),    /* PIO0_29 */
     __LPC55S69_PIN(31, GPIO, 0, 30),    /* PIO0_30 */
     __LPC55S69_PIN(32, GPIO, 0, 31),    /* PIO0_31 */
-    
-    
+
+
     /* PIO1 / GPIO, 1 */
     __LPC55S69_PIN(33, GPIO, 1,  0),    /* PIO1_00 */
     __LPC55S69_PIN(34, GPIO, 1,  1),    /* PIO1_01 */
@@ -129,7 +129,7 @@ struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
     {-1, 0, RT_NULL, RT_NULL},
     {-1, 0, RT_NULL, RT_NULL},
     {-1, 0, RT_NULL, RT_NULL},
-    {-1, 0, RT_NULL, RT_NULL},    
+    {-1, 0, RT_NULL, RT_NULL},
 };
 
 static void lpc_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
@@ -179,15 +179,15 @@ static void lpc_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
         }
         break;
     }
-    
+
     /* Enable IOCON Clock */
     CLOCK_EnableClock(kCLOCK_Iocon);
-    IOCON->PIO[lpc_pin_map[pin].gpio_port][lpc_pin_map[pin].gpio_pin] = pin_cfg;       
+    IOCON->PIO[lpc_pin_map[pin].gpio_port][lpc_pin_map[pin].gpio_pin] = pin_cfg;
     /* Disable IOCON Clock -- To Save Power */
     CLOCK_DisableClock(kCLOCK_Iocon);
-    
+
     gpio_pin_config_t pin_config = {(gpio_pin_direction_t)dir, 1};
-    GPIO_PinInit(GPIO, lpc_pin_map[pin].gpio_port, lpc_pin_map[pin].gpio_pin, &pin_config); 
+    GPIO_PinInit(GPIO, lpc_pin_map[pin].gpio_port, lpc_pin_map[pin].gpio_pin, &pin_config);
 }
 
 
@@ -197,20 +197,20 @@ static void lpc_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     {
         return;
     }
-    
+
     GPIO_PinWrite(lpc_pin_map[pin].gpio, lpc_pin_map[pin].gpio_port, lpc_pin_map[pin].gpio_pin, value);
 }
 
 static int lpc_pin_read(rt_device_t dev, rt_base_t pin)
 {
-    int value;   
+    int value;
     if ((pin > __ARRAY_LEN(lpc_pin_map)) || (pin == 0))
     {
         return RT_ERROR;
     }
 
     value = GPIO_PinRead(lpc_pin_map[pin].gpio, lpc_pin_map[pin].gpio_port, lpc_pin_map[pin].gpio_pin);
-    
+
     return value;
 }
 
@@ -225,10 +225,10 @@ static void pin_irq_hdr(pint_pin_int_t pintr, uint32_t pmatch_status)
             break;
         }
     }
-    
+
     if(irqno >= IRQ_MAX_VAL)
         return;
-    
+
     if (pin_irq_hdr_tab[irqno].hdr)
     {
         pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
@@ -250,7 +250,7 @@ void PIN_INT0_IRQHandler(void)
     pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
 
     pin_irq_hdr(kPINT_PinInt0, pmstatus);
-    
+
     if ((PINT->ISEL & 0x1U) == 0x0U)
     {
         /* Edge sensitive: clear Pin interrupt after callback */
@@ -264,8 +264,8 @@ static rt_err_t lpc_pin_attach_irq(struct rt_device *device,
                                    void (*hdr)(void *args),
                                    void *args)
 {
-    int trigger_mode, pin_initx, pintsel, pin_cfg, i;    
-    
+    int trigger_mode, pin_initx, pintsel, pin_cfg, i;
+
     if ((pin > __ARRAY_LEN(lpc_pin_map)) || (pin == 0))
     {
         return RT_ERROR;
@@ -289,10 +289,10 @@ static rt_err_t lpc_pin_attach_irq(struct rt_device *device,
             trigger_mode = kPINT_PinIntEnableLowLevel;
             break;
     }
-    
-    /* Get inputmux_connection_t */        
+
+    /* Get inputmux_connection_t */
     pintsel = (pin - 1 + (0xC0U << 20));
-    
+
     for(i = 0; i < IRQ_MAX_VAL; i++)
     {
         if(pin_irq_hdr_tab[i].pin == -1)
@@ -308,43 +308,43 @@ static rt_err_t lpc_pin_attach_irq(struct rt_device *device,
 
     if(i >= IRQ_MAX_VAL)
         return RT_ERROR;
-    
+
     /* Initialize PINT */
     PINT_Init(PINT);
-    
+
     /* Enable Input and IOCon clk */
-    /* AttachSignal */    
+    /* AttachSignal */
     /* Connect trigger sources to PINT */
     INPUTMUX_Init(INPUTMUX);
     INPUTMUX_AttachSignal(INPUTMUX, i, (inputmux_connection_t)pintsel);
     /* Turnoff clock to inputmux to save power. Clock is only needed to make changes */
     INPUTMUX_Deinit(INPUTMUX);
-    
+
     pin_cfg = ((IOCON->PIO[lpc_pin_map[pin].gpio_port][lpc_pin_map[pin].gpio_pin] &
               (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK | IOCON_PIO_FILTEROFF_MASK))) /* Mask bits to zero which are setting */
               | IOCON_PIO_FUNC(0)                /* Selects pin function.: PORT18 (pin 28) is configured as PIO1_8 */
               | IOCON_PIO_DIGIMODE(1)            /* Select Analog/Digital mode.: Digital mode. */
               | IOCON_PIO_FILTEROFF(0));         /* Controls input glitch filter.: Filter enabled. Noise pulses below approximately 10 ns are filtered out. */
-                   
-    IOCON_PinMuxSet(IOCON, lpc_pin_map[pin].gpio_port, lpc_pin_map[pin].gpio_pin, pin_cfg);    
-    
+
+    IOCON_PinMuxSet(IOCON, lpc_pin_map[pin].gpio_port, lpc_pin_map[pin].gpio_pin, pin_cfg);
+
     /* PINT_PinInterruptConfig */
-    PINT_PinInterruptConfig(PINT, (pint_pin_int_t)pin_initx, (pint_pin_enable_t)(pin_irq_hdr_tab[i].mode), callback);    
+    PINT_PinInterruptConfig(PINT, (pint_pin_int_t)pin_initx, (pint_pin_enable_t)(pin_irq_hdr_tab[i].mode), callback);
     /* Enable callbacks for PINTx by Index */
     PINT_EnableCallbackByIndex(PINT, (pint_pin_int_t)pin_initx);
-    
+
     return RT_EOK;
 }
 
 static rt_err_t lpc_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
 {
-    int i;    
+    int i;
 
     if ((pin > __ARRAY_LEN(lpc_pin_map)) || (pin == 0))
     {
         return RT_ERROR;
     }
-    
+
     for(i = 0; i < IRQ_MAX_VAL; i++)
     {
         if(pin_irq_hdr_tab[i].pin == pin)
@@ -355,19 +355,19 @@ static rt_err_t lpc_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
             pin_irq_hdr_tab[i].args = RT_NULL;
             break;
         }
-    }        
+    }
     return RT_EOK;
 }
 
 static rt_err_t lpc_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
 {
     int irqn_type, i;
-    
+
     if ((pin > __ARRAY_LEN(lpc_pin_map)) || (pin == 0))
     {
         return RT_ERROR;
     }
-    
+
     for(i = 0; i < IRQ_MAX_VAL; i++)
     {
         if(pin_irq_hdr_tab[i].pin == pin)
@@ -401,8 +401,8 @@ static rt_err_t lpc_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_u
             }
             break;
         }
-    }  
-        
+    }
+
     if(i >= IRQ_MAX_VAL)
         return RT_ERROR;
 
diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_pin.h b/bsp/lpc55sxx/Libraries/drivers/drv_pin.h
index 0c69698e67..21ebf56051 100644
--- a/bsp/lpc55sxx/Libraries/drivers/drv_pin.h
+++ b/bsp/lpc55sxx/Libraries/drivers/drv_pin.h
@@ -1,19 +1,19 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2018-03-13     Liuguang     the first version. 
+ * 2018-03-13     Liuguang     the first version.
  * 2018-03-19     Liuguang     add GPIO interrupt mode support.
  * 2019-07-15     Magicoe      The first version for LPC55S6x
  */
- 
+
 #ifndef __DRV_PIN_H__
 #define __DRV_PIN_H__
 
-#include  
+#include 
 #include 
 
 #define GET_PINS(PORTx, PINx)      (32 * PORTx + PINx + 1)    /* PORTx:0,1, PINx:0,1...31 */
diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_pwm.c b/bsp/lpc55sxx/Libraries/drivers/drv_pwm.c
index 64d6cfd00a..e2fa7f05b6 100644
--- a/bsp/lpc55sxx/Libraries/drivers/drv_pwm.c
+++ b/bsp/lpc55sxx/Libraries/drivers/drv_pwm.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -40,7 +40,7 @@ static struct rt_pwm_ops lpc_drv_ops =
 static rt_err_t lpc_drv_pwm_enable(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration, rt_bool_t enable)
 {
     CTIMER_Type *base;
-    
+
     base = (CTIMER_Type *)device->parent.user_data;
 
     if (!enable)
@@ -63,14 +63,14 @@ static rt_err_t lpc_drv_pwm_get(struct rt_device_pwm *device, struct rt_pwm_conf
     uint32_t get_frequence;
     uint32_t pwmClock = 0;
     CTIMER_Type *base;
-    
+
     base = (CTIMER_Type *)device->parent.user_data;
-    
+
 #ifdef BSP_USING_CTIMER2
     /* get frequence */
     pwmClock = CLOCK_GetFreq(kCLOCK_CTimer2) ;
 #endif
-    
+
     get_frequence = pwmClock / (base->MR[kCTIMER_Match_3] + 1);
 
     if(configuration->channel == 1)
@@ -85,7 +85,7 @@ static rt_err_t lpc_drv_pwm_get(struct rt_device_pwm *device, struct rt_pwm_conf
     configuration->pulse = get_duty * configuration->period / 100;
 
     rt_kprintf("*** PWM period %d, pulse %d\r\n", configuration->period, configuration->pulse);
-    
+
     return RT_EOK;
 }
 
@@ -97,7 +97,7 @@ static rt_err_t lpc_drv_pwm_set(struct rt_device_pwm *device, struct rt_pwm_conf
     ctimer_config_t config;
     CTIMER_Type *base;
     base = (CTIMER_Type *)device->parent.user_data;
-    
+
     uint32_t pwmPeriod, pulsePeriod;
     /* Run as a timer */
     config.mode = kCTIMER_TimerMode;
@@ -105,7 +105,7 @@ static rt_err_t lpc_drv_pwm_set(struct rt_device_pwm *device, struct rt_pwm_conf
     config.input = kCTIMER_Capture_0;
     /* Timer counter is incremented on every APB bus clock */
     config.prescale = 0;
-    
+
     if(configuration->channel == 1)
     {
         /* Get the PWM period match value and pulse width match value of DEFAULT_FREQ PWM signal with DEFAULT_DUTY dutycycle */
@@ -159,17 +159,17 @@ int rt_hw_pwm_init(void)
     static struct rt_device_pwm pwm1_device;
     ctimer_config_t config;
     uint32_t pwmPeriod, pulsePeriod;
-    
+
     /* Use 12 MHz clock for some of the Ctimers */
     CLOCK_AttachClk(kMAIN_CLK_to_CTIMER2);
-    
+
     /* Run as a timer */
     config.mode = kCTIMER_TimerMode;
     /* This field is ignored when mode is timer */
     config.input = kCTIMER_Capture_0;
     /* Timer counter is incremented on every APB bus clock */
     config.prescale = 0;
-    
+
     CTIMER_Init(CTIMER2, &config);
 
 #ifdef BSP_USING_CTIMER2_MAT1
@@ -243,7 +243,7 @@ static int pwm_get(int argc, char **argv)
         result = -RT_EIO;
         goto _exit;
     }
-    
+
     result = rt_pwm_get(device, atoi(argv[2]));
 
 _exit:
diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_pwm.h b/bsp/lpc55sxx/Libraries/drivers/drv_pwm.h
index 7260c0c587..47e50a435b 100644
--- a/bsp/lpc55sxx/Libraries/drivers/drv_pwm.h
+++ b/bsp/lpc55sxx/Libraries/drivers/drv_pwm.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_rtc.c b/bsp/lpc55sxx/Libraries/drivers/drv_rtc.c
index c277d82079..fc49389566 100644
--- a/bsp/lpc55sxx/Libraries/drivers/drv_rtc.c
+++ b/bsp/lpc55sxx/Libraries/drivers/drv_rtc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -8,12 +8,12 @@
  * 2018-03-15     Liuguang     the first version.
  * 2019-07-19     Magicoe      The first version for LPC55S6x
  */
- 
+
 #include 
 #include 
 #include 
-#include "drv_rtc.h" 
-#include "fsl_common.h" 
+#include "drv_rtc.h"
+#include "fsl_common.h"
 #include "fsl_rtc.h"
 
 #ifdef RT_USING_RTC
@@ -22,21 +22,21 @@
     #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
 #endif
 
-static time_t get_timestamp(void) 
+static time_t get_timestamp(void)
 {
-    struct tm tm_new = {0}; 
-    rtc_datetime_t rtcDate; 
-    
+    struct tm tm_new = {0};
+    rtc_datetime_t rtcDate;
+
     /* Get date time */
     RTC_GetDatetime(RTC, &rtcDate);
-    
-    tm_new.tm_sec  = rtcDate.second; 
-    tm_new.tm_min  = rtcDate.minute; 
+
+    tm_new.tm_sec  = rtcDate.second;
+    tm_new.tm_min  = rtcDate.minute;
     tm_new.tm_hour = rtcDate.hour;
-    
-    tm_new.tm_mday = rtcDate.day; 
-    tm_new.tm_mon  = rtcDate.month - 1; 
-    tm_new.tm_year = rtcDate.year - 1900; 
+
+    tm_new.tm_mday = rtcDate.day;
+    tm_new.tm_mon  = rtcDate.month - 1;
+    tm_new.tm_year = rtcDate.year - 1900;
 
     return timegm(&tm_new);
 }
@@ -44,27 +44,27 @@ static time_t get_timestamp(void)
 static int set_timestamp(time_t timestamp)
 {
     struct tm *p_tm;
-    rtc_datetime_t rtcDate; 
-    
-    p_tm = gmtime(×tamp);
-    
-    rtcDate.second = p_tm->tm_sec ; 
-    rtcDate.minute = p_tm->tm_min ; 
-    rtcDate.hour   = p_tm->tm_hour; 
+    rtc_datetime_t rtcDate;
+
+    p_tm = gmtime(×tamp);
+
+    rtcDate.second = p_tm->tm_sec ;
+    rtcDate.minute = p_tm->tm_min ;
+    rtcDate.hour   = p_tm->tm_hour;
+
+    rtcDate.day    = p_tm->tm_mday;
+    rtcDate.month  = p_tm->tm_mon  + 1;
+    rtcDate.year   = p_tm->tm_year + 1900;
 
-    rtcDate.day    = p_tm->tm_mday; 
-    rtcDate.month  = p_tm->tm_mon  + 1;  
-    rtcDate.year   = p_tm->tm_year + 1900; 
-    
     /* RTC time counter has to be stopped before setting the date & time in the TSR register */
     RTC_StopTimer(RTC);
-    
+
     /* Set RTC time to default */
     RTC_SetDatetime(RTC, &rtcDate);
 
     /* Start the RTC time counter */
     RTC_StartTimer(RTC);
-    
+
     return RT_EOK;
 }
 
@@ -72,83 +72,83 @@ static rt_err_t lpc_rtc_init(rt_device_t dev)
 {
     /* Init RTC */
     RTC_Init(RTC);
-    
+
     /* Start the RTC time counter */
     RTC_StartTimer(RTC);
-    
-    return RT_EOK; 
+
+    return RT_EOK;
 }
 
 static rt_err_t lpc_rtc_open(rt_device_t dev, rt_uint16_t oflag)
 {
-    return RT_EOK; 
+    return RT_EOK;
 }
 
-static rt_err_t lpc_rtc_close(rt_device_t dev) 
+static rt_err_t lpc_rtc_close(rt_device_t dev)
 {
-    return RT_EOK; 
-} 
+    return RT_EOK;
+}
 
 static rt_size_t lpc_rtc_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
 {
-    return 0; 
+    return 0;
 }
 
 static rt_size_t lpc_rtc_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
 {
-    return 0; 
+    return 0;
 }
 
 static rt_err_t lpc_rtc_control(rt_device_t dev, int cmd, void *args)
 {
     RT_ASSERT(dev != RT_NULL);
-    
+
     switch(cmd)
     {
-        case RT_DEVICE_CTRL_RTC_GET_TIME: 
+        case RT_DEVICE_CTRL_RTC_GET_TIME:
         {
-            *(uint32_t *)args = get_timestamp(); 
+            *(uint32_t *)args = get_timestamp();
         }
         break;
-            
-        case RT_DEVICE_CTRL_RTC_SET_TIME: 
+
+        case RT_DEVICE_CTRL_RTC_SET_TIME:
         {
-            set_timestamp(*(time_t *)args); 
+            set_timestamp(*(time_t *)args);
         }
         break;
-            
+
         default:
-            return RT_EINVAL; 
+            return RT_EINVAL;
     }
-    
-    return RT_EOK; 
+
+    return RT_EOK;
 }
 
-static struct rt_device device = 
+static struct rt_device device =
 {
-    .type    = RT_Device_Class_RTC, 
-    .init    = lpc_rtc_init, 
-    .open    = lpc_rtc_open, 
-    .close   = lpc_rtc_close, 
+    .type    = RT_Device_Class_RTC,
+    .init    = lpc_rtc_init,
+    .open    = lpc_rtc_open,
+    .close   = lpc_rtc_close,
     .read    = lpc_rtc_read,
     .write   = lpc_rtc_write,
-    .control = lpc_rtc_control, 
+    .control = lpc_rtc_control,
 };
 
 int rt_hw_rtc_init(void)
 {
     rt_err_t ret = RT_EOK;
-    
-    ret = rt_device_register(&device, "rtc", RT_DEVICE_FLAG_RDWR); 
+
+    ret = rt_device_register(&device, "rtc", RT_DEVICE_FLAG_RDWR);
     if(ret != RT_EOK)
     {
-        return ret; 
+        return ret;
     }
-    
-    rt_device_open(&device, RT_DEVICE_OFLAG_RDWR); 
-    
-    return RT_EOK; 
+
+    rt_device_open(&device, RT_DEVICE_OFLAG_RDWR);
+
+    return RT_EOK;
 }
-INIT_DEVICE_EXPORT(rt_hw_rtc_init); 
+INIT_DEVICE_EXPORT(rt_hw_rtc_init);
 
 #endif /*RT_USING_RTC */
diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_rtc.h b/bsp/lpc55sxx/Libraries/drivers/drv_rtc.h
index a0623308ad..a905b177ae 100644
--- a/bsp/lpc55sxx/Libraries/drivers/drv_rtc.h
+++ b/bsp/lpc55sxx/Libraries/drivers/drv_rtc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -8,12 +8,12 @@
  * 2018-03-15     Liuguang     the first version.
  * 2019-07-19     Magicoe      The first version for LPC55S6x
  */
- 
+
 #ifndef __DRV_RTC_H__
 #define __DRV_RTC_H__
 
-#include  
-#include  
+#include 
+#include 
 
 int rt_hw_rtc_init(void);
 
diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_sd.c b/bsp/lpc55sxx/Libraries/drivers/drv_sd.c
index 66385a7056..597e49aa7b 100644
--- a/bsp/lpc55sxx/Libraries/drivers/drv_sd.c
+++ b/bsp/lpc55sxx/Libraries/drivers/drv_sd.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -12,7 +12,7 @@
 #include 
 #include 
 
-#include "fsl_common.h" 
+#include "fsl_common.h"
 #include "fsl_iocon.h"
 
 #include "fsl_sdif.h"
@@ -177,14 +177,14 @@ int rt_hw_mci_init(void)
         return -RT_ERROR;
     }
     rt_memset(_mci_device, 0, sizeof(struct mci_device));
-    
+
     /* attach main clock to SDIF */
     CLOCK_AttachClk(kMAIN_CLK_to_SDIO_CLK);
     /* need call this function to clear the halt bit in clock divider register */
     CLOCK_SetClkDiv(kCLOCK_DivSdioClk, (uint32_t)(SystemCoreClock / FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK + 1U), true);
 
     _mci_device->card = g_sd;
-    
+
     /* Save host information. */
     _mci_device->card.host.base = SDIF;
     _mci_device->card.host.sourceClock_Hz = CLOCK_GetFreq(kCLOCK_SDio);
@@ -202,14 +202,14 @@ int rt_hw_mci_init(void)
 
     /* power off card */
     SD_PowerOffCard(_mci_device->card.host.base, _mci_device->card.usrParam.pwr);
-    
+
     /* check SD card insert */
     if(BOARD_SDIF_CD_STATUS() == true)
     {
         rt_kprintf("\r\nCard detect fail.\r\n");
         return kStatus_Fail;
     }
-    
+
     /* wait card insert */
     if (SD_WaitCardDetectStatus(_mci_device->card.host.base, &s_sdCardDetect, true) == kStatus_Success)
     {
@@ -223,7 +223,7 @@ int rt_hw_mci_init(void)
         rt_kprintf("\r\nCard detect fail.\r\n");
         return kStatus_Fail;
     }
-    
+
     /* Init card. */
     if (SD_CardInit(&_mci_device->card))
     {
diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_sd.h b/bsp/lpc55sxx/Libraries/drivers/drv_sd.h
index 125f2b9a47..e604787c16 100644
--- a/bsp/lpc55sxx/Libraries/drivers/drv_sd.h
+++ b/bsp/lpc55sxx/Libraries/drivers/drv_sd.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -18,7 +18,7 @@ struct mci_device
 {
     struct rt_device                parent;      /**< RT-Thread device struct */
     struct rt_device_blk_geometry   geometry;    /**< sector size, sector count */
-    sd_card_t                   	card;   	 /**< Card descriptor */
+    sd_card_t                       card;        /**< Card descriptor */
     rt_event_t finish_event;                     /**< data send finish event*/
     rt_bool_t data_error;                        /**< data send error*/
     struct rt_mutex lock;
diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_spi.c b/bsp/lpc55sxx/Libraries/drivers/drv_spi.c
index 53c4c3730f..332b20ac5e 100644
--- a/bsp/lpc55sxx/Libraries/drivers/drv_spi.c
+++ b/bsp/lpc55sxx/Libraries/drivers/drv_spi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -9,7 +9,7 @@
  */
 #include "drv_spi.h"
 
-#include "fsl_common.h" 
+#include "fsl_common.h"
 #include "fsl_iocon.h"
 #include "fsl_spi.h"
 
@@ -23,7 +23,7 @@
     defined(BSP_USING_SPIBUS6) || \
     defined(BSP_USING_SPIBUS7) || \
     defined(BSP_USING_SPIBUS8)
-    
+
 #if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
     #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
 #endif
@@ -44,14 +44,14 @@ struct lpc_sw_spi_cs
 static uint32_t lpc_get_spi_freq(SPI_Type *base)
 {
     uint32_t freq = 0;
-    
+
 #if defined(BSP_USING_SPIBUS0)
     if(base == SPI0)
     {
         freq = CLOCK_GetFreq(kCLOCK_Flexcomm0);
     }
-#endif 
-    
+#endif
+
 #if defined(BSP_USING_SPIBUS1)
     if(base == SPI1)
     {
@@ -72,7 +72,7 @@ static uint32_t lpc_get_spi_freq(SPI_Type *base)
         freq = CLOCK_GetFreq(kCLOCK_Flexcomm3);
     }
 #endif
- 
+
 #if defined(BSP_USING_SPIBUS4)
     if(base == SPI4)
     {
@@ -116,15 +116,15 @@ static rt_err_t lpc_spi_init(SPI_Type *base, struct rt_spi_configuration *cfg)
 {
     spi_master_config_t masterConfig = {0};
 
-    RT_ASSERT(cfg != RT_NULL); 
+    RT_ASSERT(cfg != RT_NULL);
 
     if(cfg->data_width != 8 && cfg->data_width != 16)
     {
-        return (-RT_EINVAL); 
+        return (-RT_EINVAL);
     }
 
-    
-    SPI_MasterGetDefaultConfig(&masterConfig); 
+
+    SPI_MasterGetDefaultConfig(&masterConfig);
 
 #if defined(BSP_USING_SPIBUS8)
     if(base == SPI8)
@@ -140,81 +140,81 @@ static rt_err_t lpc_spi_init(SPI_Type *base, struct rt_spi_configuration *cfg)
         cfg->max_hz = 12*1000*1000;
     }
 #endif
-    
+
     masterConfig.baudRate_Bps = cfg->max_hz;
 
     if(cfg->data_width == 8)
     {
-        masterConfig.dataWidth = kSPI_Data8Bits; 
+        masterConfig.dataWidth = kSPI_Data8Bits;
     }
     else if(cfg->data_width == 16)
     {
-        masterConfig.dataWidth = kSPI_Data16Bits; 
+        masterConfig.dataWidth = kSPI_Data16Bits;
     }
 
     if(cfg->mode & RT_SPI_MSB)
     {
-        masterConfig.direction = kSPI_MsbFirst; 
+        masterConfig.direction = kSPI_MsbFirst;
     }
     else
     {
-        masterConfig.direction = kSPI_LsbFirst; 
+        masterConfig.direction = kSPI_LsbFirst;
     }
 
     if(cfg->mode & RT_SPI_CPHA)
     {
-        masterConfig.phase = kSPI_ClockPhaseSecondEdge; 
+        masterConfig.phase = kSPI_ClockPhaseSecondEdge;
     }
     else
     {
-        masterConfig.phase = kSPI_ClockPhaseFirstEdge; 
+        masterConfig.phase = kSPI_ClockPhaseFirstEdge;
     }
 
     if(cfg->mode & RT_SPI_CPOL)
     {
-        masterConfig.polarity = kSPI_ClockPolarityActiveLow; 
+        masterConfig.polarity = kSPI_ClockPolarityActiveLow;
     }
     else
     {
-        masterConfig.polarity = kSPI_ClockPolarityActiveHigh; 
+        masterConfig.polarity = kSPI_ClockPolarityActiveHigh;
     }
 
-    SPI_MasterInit(base, &masterConfig, lpc_get_spi_freq(base)); 
+    SPI_MasterInit(base, &masterConfig, lpc_get_spi_freq(base));
 
-    return RT_EOK; 
+    return RT_EOK;
 }
 
 rt_err_t lpc_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin)
 {
-    rt_err_t ret = RT_EOK; 
-    
-    struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); 
-    RT_ASSERT(spi_device != RT_NULL); 
-    
-    struct lpc_sw_spi_cs *cs_pin = (struct lpc_sw_spi_cs *)rt_malloc(sizeof(struct lpc_sw_spi_cs)); 
+    rt_err_t ret = RT_EOK;
+
+    struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
+    RT_ASSERT(spi_device != RT_NULL);
+
+    struct lpc_sw_spi_cs *cs_pin = (struct lpc_sw_spi_cs *)rt_malloc(sizeof(struct lpc_sw_spi_cs));
     RT_ASSERT(cs_pin != RT_NULL);
-    
+
     cs_pin->pin = pin;
-    rt_pin_mode(pin, PIN_MODE_OUTPUT); 
-    rt_pin_write(pin, PIN_HIGH); 
-    
-    ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); 
-    
-    return ret; 
+    rt_pin_mode(pin, PIN_MODE_OUTPUT);
+    rt_pin_write(pin, PIN_HIGH);
+
+    ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
+
+    return ret;
 }
 
 static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg)
 {
-    rt_err_t ret = RT_EOK; 
-    struct lpc_spi *spi = RT_NULL; 
-    
+    rt_err_t ret = RT_EOK;
+    struct lpc_spi *spi = RT_NULL;
+
     RT_ASSERT(cfg != RT_NULL);
     RT_ASSERT(device != RT_NULL);
-    
-    spi = (struct lpc_spi *)(device->bus->parent.user_data); 
-    spi->cfg = cfg; 
-    ret = lpc_spi_init(spi->base, cfg); 
-    
+
+    spi = (struct lpc_spi *)(device->bus->parent.user_data);
+    spi->cfg = cfg;
+    ret = lpc_spi_init(spi->base, cfg);
+
     return ret;
 }
 
@@ -222,23 +222,23 @@ static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_config
 static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
 {
     uint32_t length;
-    
+
     RT_ASSERT(device != RT_NULL);
     RT_ASSERT(device->bus != RT_NULL);
     RT_ASSERT(device->bus->parent.user_data != RT_NULL);
-  
-    struct lpc_spi *spi = (struct lpc_spi *)(device->bus->parent.user_data); 
-    struct lpc_sw_spi_cs *cs = device->parent.user_data; 
-    
+
+    struct lpc_spi *spi = (struct lpc_spi *)(device->bus->parent.user_data);
+    struct lpc_sw_spi_cs *cs = device->parent.user_data;
+
     if(message->cs_take)
     {
         rt_pin_write(cs->pin, PIN_LOW);
     }
-    
+
     length = message->length;
-    const rt_uint8_t *txData  = (uint8_t *)(message->send_buf); 
-    rt_uint8_t *rxData  = (uint8_t *)(message->recv_buf); 
-    
+    const rt_uint8_t *txData  = (uint8_t *)(message->send_buf);
+    rt_uint8_t *rxData  = (uint8_t *)(message->recv_buf);
+
     rt_kprintf("*** spi send %d\r\n", length);
 
     while (length)
@@ -257,181 +257,181 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
         }
         txData += SPISTEP(spi->cfg->data_width);;
         length--;
-    }    
-    
+    }
+
     if(message->cs_release)
     {
         rt_pin_write(cs->pin, PIN_HIGH);
     }
-    
-    return (message->length - length); 
+
+    return (message->length - length);
 }
 
 #if defined(BSP_USING_SPIBUS0)
-static struct lpc_spi spi0 = 
+static struct lpc_spi spi0 =
 {
     .base = SPI0
-}; 
-static struct rt_spi_bus spi0_bus = 
+};
+static struct rt_spi_bus spi0_bus =
 {
     .parent.user_data = &spi0
-}; 
+};
 #endif
 
 #if defined(BSP_USING_SPIBUS1)
-static struct lpc_spi spi1 = 
+static struct lpc_spi spi1 =
 {
     .base = SPI1
-}; 
-static struct rt_spi_bus spi1_bus = 
+};
+static struct rt_spi_bus spi1_bus =
 {
     .parent.user_data = &spi1
-}; 
+};
 #endif
 
 #if defined(BSP_USING_SPIBUS2)
-static struct lpc_spi spi2 = 
+static struct lpc_spi spi2 =
 {
     .base = SPI2
-}; 
-static struct rt_spi_bus spi2_bus = 
+};
+static struct rt_spi_bus spi2_bus =
 {
     .parent.user_data = &spi2
-}; 
+};
 #endif
 
 #if defined(BSP_USING_SPIBUS3)
-static struct lpc_spi spi3 = 
+static struct lpc_spi spi3 =
 {
     .base = SPI3
-}; 
-static struct rt_spi_bus spi3_bus = 
+};
+static struct rt_spi_bus spi3_bus =
 {
     .parent.user_data = &spi3
-}; 
+};
 #endif
 
 #if defined(BSP_USING_SPIBUS4)
-static struct lpc_spi spi4 = 
+static struct lpc_spi spi4 =
 {
     .base = SPI4
-}; 
-static struct rt_spi_bus spi4_bus = 
+};
+static struct rt_spi_bus spi4_bus =
 {
     .parent.user_data = &spi4
-}; 
+};
 #endif
 
 #if defined(BSP_USING_SPIBUS5)
-static struct lpc_spi spi5 = 
+static struct lpc_spi spi5 =
 {
     .base = SPI5
-}; 
-static struct rt_spi_bus spi5_bus = 
+};
+static struct rt_spi_bus spi5_bus =
 {
     .parent.user_data = &spi5
-}; 
+};
 #endif
 
 #if defined(BSP_USING_SPIBUS6)
-static struct lpc_spi spi6 = 
+static struct lpc_spi spi6 =
 {
     .base = SPI6
-}; 
-static struct rt_spi_bus spi6_bus = 
+};
+static struct rt_spi_bus spi6_bus =
 {
     .parent.user_data = &spi6
-}; 
+};
 #endif
 
 #if defined(BSP_USING_SPIBUS7)
-static struct lpc_spi spi7 = 
+static struct lpc_spi spi7 =
 {
     .base = SPI7
-}; 
-static struct rt_spi_bus spi7_bus = 
+};
+static struct rt_spi_bus spi7_bus =
 {
     .parent.user_data = &spi7
-}; 
+};
 #endif
 
 #if defined(BSP_USING_SPIBUS8)
-static struct lpc_spi spi8 = 
+static struct lpc_spi spi8 =
 {
     .base = SPI8
-}; 
-static struct rt_spi_bus spi8_bus = 
+};
+static struct rt_spi_bus spi8_bus =
 {
     .parent.user_data = &spi8
-}; 
+};
 #endif
 
 
-static struct rt_spi_ops lpc_spi_ops = 
+static struct rt_spi_ops lpc_spi_ops =
 {
-    .configure = spi_configure, 
+    .configure = spi_configure,
     .xfer      = spixfer
-}; 
+};
 
 int rt_hw_spi_init(void)
 {
 #if defined(BSP_USING_SPIBUS0)
     CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0);
     RESET_PeripheralReset(kFC0_RST_SHIFT_RSTn);
-    spi0.cfg = RT_NULL; 
-    rt_spi_bus_register(&spi0_bus, "spi0", &lpc_spi_ops); 
+    spi0.cfg = RT_NULL;
+    rt_spi_bus_register(&spi0_bus, "spi0", &lpc_spi_ops);
 #endif
 
 #if defined(BSP_USING_SPIBUS1)
     CLOCK_AttachClk(kFRO12M_to_FLEXCOMM1);
     RESET_PeripheralReset(kFC1_RST_SHIFT_RSTn);
 
-    spi1.cfg = RT_NULL; 
-    rt_spi_bus_register(&spi1_bus, "spi1", &lpc_spi_ops); 
+    spi1.cfg = RT_NULL;
+    rt_spi_bus_register(&spi1_bus, "spi1", &lpc_spi_ops);
 #endif
 
 #if defined(BSP_USING_SPIBUS2)
     CLOCK_AttachClk(kFRO12M_to_FLEXCOMM2);
     RESET_PeripheralReset(kFC2_RST_SHIFT_RSTn);
-    spi2.cfg = RT_NULL; 
-    rt_spi_bus_register(&spi2_bus, "spi2", &lpc_spi_ops); 
+    spi2.cfg = RT_NULL;
+    rt_spi_bus_register(&spi2_bus, "spi2", &lpc_spi_ops);
 #endif
 
 #if defined(BSP_USING_SPIBUS3)
     CLOCK_AttachClk(kFRO12M_to_FLEXCOMM3);
     RESET_PeripheralReset(kFC3_RST_SHIFT_RSTn);
-    spi3.cfg = RT_NULL; 
-    rt_spi_bus_register(&spi3_bus, "spi3", &lpc_spi_ops); 
+    spi3.cfg = RT_NULL;
+    rt_spi_bus_register(&spi3_bus, "spi3", &lpc_spi_ops);
 #endif
 
 #if defined(BSP_USING_SPIBUS4)
     CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
     RESET_PeripheralReset(kFC4_RST_SHIFT_RSTn);
-    spi4.cfg = RT_NULL; 
-    rt_spi_bus_register(&spi4_bus, "spi4", &lpc_spi_ops); 
+    spi4.cfg = RT_NULL;
+    rt_spi_bus_register(&spi4_bus, "spi4", &lpc_spi_ops);
 #endif
-    
+
 #if defined(BSP_USING_SPIBUS5)
     CLOCK_AttachClk(kFRO12M_to_FLEXCOMM5);
     RESET_PeripheralReset(kFC5_RST_SHIFT_RSTn);
-    spi5.cfg = RT_NULL; 
-    rt_spi_bus_register(&spi5_bus, "spi5", &lpc_spi_ops); 
+    spi5.cfg = RT_NULL;
+    rt_spi_bus_register(&spi5_bus, "spi5", &lpc_spi_ops);
 #endif
 
 #if defined(BSP_USING_SPIBUS6)
     CLOCK_AttachClk(kFRO12M_to_FLEXCOMM6);
     RESET_PeripheralReset(kFC6_RST_SHIFT_RSTn);
-    spi6.cfg = RT_NULL; 
-    rt_spi_bus_register(&spi6_bus, "spi6", &lpc_spi_ops); 
+    spi6.cfg = RT_NULL;
+    rt_spi_bus_register(&spi6_bus, "spi6", &lpc_spi_ops);
 #endif
 
 #if defined(BSP_USING_SPIBUS7)
     CLOCK_AttachClk(kFRO12M_to_FLEXCOMM7);
     RESET_PeripheralReset(kFC7_RST_SHIFT_RSTn);
-    spi7.cfg = RT_NULL; 
-    rt_spi_bus_register(&spi7_bus, "spi7", &lpc_spi_ops); 
+    spi7.cfg = RT_NULL;
+    rt_spi_bus_register(&spi7_bus, "spi7", &lpc_spi_ops);
 #endif
-    
+
 #if defined(BSP_USING_SPIBUS8)
     CLOCK_AttachClk(kMAIN_CLK_to_HSLSPI);
     RESET_PeripheralReset(kHSLSPI_RST_SHIFT_RSTn);
@@ -440,7 +440,7 @@ int rt_hw_spi_init(void)
     rt_spi_bus_register(&spi8_bus, "spi8", &lpc_spi_ops);
 #endif
 
-    return RT_EOK; 
+    return RT_EOK;
 }
 
 INIT_BOARD_EXPORT(rt_hw_spi_init);
diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_spi.h b/bsp/lpc55sxx/Libraries/drivers/drv_spi.h
index 6aeb91256e..d361637c60 100644
--- a/bsp/lpc55sxx/Libraries/drivers/drv_spi.h
+++ b/bsp/lpc55sxx/Libraries/drivers/drv_spi.h
@@ -1,16 +1,16 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  */
- 
-#ifndef __DRV_SPI_H__ 
-#define __DRV_SPI_H__ 
 
-#include  
-#include  
+#ifndef __DRV_SPI_H__
+#define __DRV_SPI_H__
+
+#include 
+#include 
 
 int rt_hw_spi_init(void);
-rt_err_t lpc_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin); 
+rt_err_t lpc_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin);
 
 #endif
diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_uart.c b/bsp/lpc55sxx/Libraries/drivers/drv_uart.c
index d9c325971f..c9bf72eb8d 100644
--- a/bsp/lpc55sxx/Libraries/drivers/drv_uart.c
+++ b/bsp/lpc55sxx/Libraries/drivers/drv_uart.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -40,7 +40,7 @@ struct lpc_uart
     USART_Type *uart_base;
     IRQn_Type irqn;
     clock_name_t clock_src;
-    
+
     struct rt_serial_device *serial;
     char *device_name;
 };
@@ -133,7 +133,7 @@ static const struct lpc_uart uarts[] =
         USART0,
         FLEXCOMM0_IRQn,
         kCLOCK_Flexcomm0,
-        
+
         &serial0,
         "uart",
     },
@@ -143,7 +143,7 @@ static const struct lpc_uart uarts[] =
         USART1,
         FLEXCOMM1_IRQn,
         kCLOCK_Flexcomm1,
-        
+
         &serial1,
         "uart1",
     },
@@ -153,7 +153,7 @@ static const struct lpc_uart uarts[] =
         USART2,
         FLEXCOMM2_IRQn,
         kCLOCK_Flexcomm2,
-        
+
         &serial2,
         "uart2",
     },
@@ -163,7 +163,7 @@ static const struct lpc_uart uarts[] =
         USART3,
         FLEXCOMM3_IRQn,
         kCLOCK_Flexcomm3,
-        
+
         &serial3,
         "uart3",
     },
@@ -173,7 +173,7 @@ static const struct lpc_uart uarts[] =
         USART4,
         FLEXCOMM4_IRQn,
         kCLOCK_Flexcomm4,
-        
+
         &serial4,
         "uart4",
     },
@@ -183,7 +183,7 @@ static const struct lpc_uart uarts[] =
         USART5,
         FLEXCOMM5_IRQn,
         kCLOCK_Flexcomm5,
-        
+
         &serial5,
         "uart5",
     },
@@ -193,7 +193,7 @@ static const struct lpc_uart uarts[] =
         USART6,
         FLEXCOMM6_IRQn,
         kCLOCK_Flexcomm6,
-        
+
         &serial6,
         "uart6",
     },
@@ -203,7 +203,7 @@ static const struct lpc_uart uarts[] =
         USART7,
         FLEXCOMM7_IRQn,
         kCLOCK_Flexcomm7,
-        
+
         &serial7,
         "uart7",
     },
@@ -270,11 +270,11 @@ static rt_err_t lpc_configure(struct rt_serial_device *serial, struct serial_con
 
     RT_ASSERT(serial != RT_NULL);
     RT_ASSERT(cfg != RT_NULL);
-    
+
     uart = (struct lpc_uart *)serial->parent.user_data;
 
     lpc_uart_gpio_init(uart);
-    
+
     /*
      * config.baudRate_Bps = 115200U;
      * config.parityMode = kUSART_ParityDisabled;
@@ -285,7 +285,7 @@ static rt_err_t lpc_configure(struct rt_serial_device *serial, struct serial_con
      */
     USART_GetDefaultConfig(&config);
     config.baudRate_Bps = cfg->baud_rate;
-    
+
     switch (cfg->data_bits)
     {
         case DATA_BITS_7:
@@ -296,7 +296,7 @@ static rt_err_t lpc_configure(struct rt_serial_device *serial, struct serial_con
             config.bitCountPerChar = kUSART_8BitsPerChar;
             break;
     }
-    
+
     switch (cfg->stop_bits)
     {
         case STOP_BITS_2:
@@ -306,7 +306,7 @@ static rt_err_t lpc_configure(struct rt_serial_device *serial, struct serial_con
             config.stopBitCount = kUSART_OneStopBit;
             break;
     }
-    
+
     switch (cfg->parity)
     {
         case PARITY_ODD:
@@ -319,7 +319,7 @@ static rt_err_t lpc_configure(struct rt_serial_device *serial, struct serial_con
             config.parityMode = kUSART_ParityDisabled;
             break;
     }
-    
+
     config.enableTx = true;
     config.enableRx = true;
 
@@ -399,7 +399,7 @@ static void uart_isr(struct rt_serial_device *serial)
 
     /* UART in mode Receiver -------------------------------------------------*/
     rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
-    
+
     /* leave interrupt */
     rt_interrupt_leave();
 }
@@ -416,7 +416,7 @@ int rt_hw_uart_init(void)
 {
     struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
     int i;
-    
+
     for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++)
     {
         uarts[i].serial->ops    = &lpc_uart_ops;
diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_uart.h b/bsp/lpc55sxx/Libraries/drivers/drv_uart.h
index 603e2a248b..b0dffa8e70 100644
--- a/bsp/lpc55sxx/Libraries/drivers/drv_uart.h
+++ b/bsp/lpc55sxx/Libraries/drivers/drv_uart.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_wdt.c b/bsp/lpc55sxx/Libraries/drivers/drv_wdt.c
index 65150a42fb..095c3f0665 100644
--- a/bsp/lpc55sxx/Libraries/drivers/drv_wdt.c
+++ b/bsp/lpc55sxx/Libraries/drivers/drv_wdt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -43,7 +43,7 @@ static wwdt_config_t WWDT1_config =
     /* No warning is provided */
     .warningValue = 0,
     /* Set clock frequency. */
-    .clockFreq_Hz = 0U, 
+    .clockFreq_Hz = 0U,
 };
 
 void WDT_BOD_IRQHandler(void)
@@ -109,9 +109,9 @@ static rt_err_t lpc_wwdt_init(rt_watchdog_t *wdt)
     SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK;
     /* Set clock divider for WWDT clock source. */
     CLOCK_SetClkDiv(kCLOCK_DivWdtClk, 1U, true);
-    
+
     WWDT_GetDefaultConfig(&WWDT1_config);
-    
+
     /*
      * Set watchdog feed time constant to approximately 4s
      * Set watchdog warning time to 512 ticks after feed time constant
@@ -125,7 +125,7 @@ static rt_err_t lpc_wwdt_init(rt_watchdog_t *wdt)
     WWDT1_config.enableWatchdogReset = true;
     /* Setup watchdog clock frequency(Hz). */
     WWDT1_config.clockFreq_Hz = CLOCK_GetFreq(kCLOCK_WdtClk);
-    
+
     WWDT_Init(base, &WWDT1_config);
     lpc_wwdt_close(wdt);
 
@@ -175,11 +175,11 @@ static rt_err_t lpc_wwdt_control(rt_watchdog_t *wdt, int cmd, void *args)
     case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
     {
         RT_ASSERT(*(uint16_t *)args != 0);
-        
+
         WWDT1_config.timeoutValue = (CLOCK_GetFreq(kCLOCK_WdtClk) / 4) * (*(uint16_t *)args) * 2;
         WWDT1_config.warningValue = 512;
         WWDT1_config.windowValue  = (CLOCK_GetFreq(kCLOCK_WdtClk) / 4) * (*(uint16_t *)args) * 2 / 4;
-        
+
         base->TC = WWDT_TC_COUNT(WWDT1_config.timeoutValue);
         base->WINDOW  = WWDT_WINDOW_WINDOW(WWDT1_config.windowValue);
         base->WARNINT = WWDT_WARNINT_WARNINT(WWDT1_config.warningValue);
diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_wdt.h b/bsp/lpc55sxx/Libraries/drivers/drv_wdt.h
index 2517fb81d9..1b34934cf2 100644
--- a/bsp/lpc55sxx/Libraries/drivers/drv_wdt.h
+++ b/bsp/lpc55sxx/Libraries/drivers/drv_wdt.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/applications/main.c b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/applications/main.c
index e03a8c6336..ef4393ba39 100644
--- a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/applications/main.c
+++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -27,7 +27,7 @@ int main(void)
 #elif defined(__GNUC__)
     rt_kprintf("using gcc, version: %d.%d\n", __GNUC__, __GNUC_MINOR__);
 #endif
-  
+
     rt_pin_mode(LEDB_PIN, PIN_MODE_OUTPUT);  /* Set GPIO as Output */
     while (1)
     {
diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/board.c b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/board.c
index 4a7fb3f885..42a08bcb34 100644
--- a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/board.c
+++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -41,15 +41,15 @@ void rt_hw_board_init()
 {
     /* Hardware Initialization */
     BOARD_InitPins();
-    
+
     CLOCK_EnableClock(kCLOCK_InputMux);
-    
+
     CLOCK_EnableClock(kCLOCK_Gpio0);
     CLOCK_EnableClock(kCLOCK_Gpio1);
-    
+
     GPIO_PortInit(GPIO, 0);
     GPIO_PortInit(GPIO, 1);
-    
+
     /* NVIC Configuration */
 #define NVIC_VTOR_MASK              0x3FFFFF80
 #ifdef  VECT_TAB_RAM
@@ -62,16 +62,16 @@ void rt_hw_board_init()
 
     BOARD_BootClockPLL150M();
     //BOARD_BootClockFROHF96M();
-    
-    /* init systick  1 systick = 1/(100M / 100) 100systick = 1s*/
+
+    /* init systick  1 systick = 1/(100M / 100) 100个systick = 1s*/
     SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
     /* set pend exception priority */
     NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
 
     /*init uart device*/
     rt_hw_uart_init();
-    
-#ifdef RT_USING_CONSOLE    
+
+#ifdef RT_USING_CONSOLE
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
 
diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/board.h b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/board.h
index f2fce5c093..1899798c13 100644
--- a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/board.h
+++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/applications/main.c b/bsp/lpc55sxx/lpc55s69_nxp_evk/applications/main.c
index e0a2e3171f..64689741de 100644
--- a/bsp/lpc55sxx/lpc55s69_nxp_evk/applications/main.c
+++ b/bsp/lpc55sxx/lpc55s69_nxp_evk/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.c b/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.c
index b81bc8e616..0b71b508e7 100644
--- a/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.c
+++ b/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
@@ -43,15 +43,15 @@ void rt_hw_board_init()
 {
     /* Hardware Initialization */
     BOARD_InitPins();
-    
+
     CLOCK_EnableClock(kCLOCK_InputMux);
-    
+
     CLOCK_EnableClock(kCLOCK_Gpio0);
     CLOCK_EnableClock(kCLOCK_Gpio1);
-    
+
     GPIO_PortInit(GPIO, 0);
     GPIO_PortInit(GPIO, 1);
-    
+
     /* NVIC Configuration */
 #define NVIC_VTOR_MASK              0x3FFFFF80
 #ifdef  VECT_TAB_RAM
@@ -73,16 +73,16 @@ void rt_hw_board_init()
     BOARD_BootClockPLL150M();
 #endif
     //BOARD_BootClockFROHF96M();
-    
-    /* init systick  1 systick = 1/(100M / 100) 100systick = 1s*/
+
+    /* init systick  1 systick = 1/(100M / 100) 100个systick = 1s*/
     SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
     /* set pend exception priority */
     NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
 
     /*init uart device*/
     rt_hw_uart_init();
-    
-#ifdef RT_USING_CONSOLE    
+
+#ifdef RT_USING_CONSOLE
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
 
diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.h b/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.h
index 32afed7da3..d2deccda88 100644
--- a/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.h
+++ b/bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc824/applications/application.c b/bsp/lpc824/applications/application.c
index f8ef7f40e3..ed7972b4d2 100644
--- a/bsp/lpc824/applications/application.c
+++ b/bsp/lpc824/applications/application.c
@@ -1,12 +1,12 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2009-01-05     Bernard      the first version
- * 2014-04-27     Bernard      make code cleanup. 
+ * 2014-04-27     Bernard      make code cleanup.
  */
 
 #include 
@@ -29,26 +29,26 @@ static struct rt_thread led_thread;
 #endif
 
 void rt_init_thread_entry(void* parameter)
-{    
+{
      /* initialization RT-Thread Components */
 #ifdef RT_USING_COMPONENTS_INIT
     rt_components_init();
 #endif
-    
+
 }
 
 void rt_led_thread_entry(void *parameter)
 {
     /* Initialize GPIO */
-	Chip_GPIO_Init(LPC_GPIO_PORT);
+    Chip_GPIO_Init(LPC_GPIO_PORT);
     Chip_GPIO_PinSetDIR(LPC_GPIO_PORT, 0, 7, 1);
     Chip_GPIO_PinSetState(LPC_GPIO_PORT, 0, 7, true);
-    
+
     while (1)
     {
         Chip_GPIO_PinSetState(LPC_GPIO_PORT, 0, 7, true);
         rt_thread_delay(RT_TICK_PER_SECOND / 2);
-        
+
         Chip_GPIO_PinSetState(LPC_GPIO_PORT, 0, 7, false);
         rt_thread_delay(RT_TICK_PER_SECOND / 2);
     }
@@ -64,7 +64,7 @@ int rt_application_init()
         INIT_STACK_SIZE, RT_THREAD_PRIORITY_MAX/3, 20);
 #else
     {
-        
+
         rt_err_t result;
 
         tid = &init_thread;
@@ -75,14 +75,14 @@ int rt_application_init()
 #endif
     if (tid != RT_NULL)
         rt_thread_startup(tid);
-    
+
 #ifdef RT_USING_HEAP
     tid = rt_thread_create("led",
         rt_led_thread_entry, RT_NULL,
         LED_STACK_SIZE, RT_THREAD_PRIORITY_MAX/3, 20);
 #else
     {
-        
+
         rt_err_t result;
 
         tid = &led_thread;
diff --git a/bsp/lpc824/applications/startup.c b/bsp/lpc824/applications/startup.c
index e165242f86..d25c76e723 100644
--- a/bsp/lpc824/applications/startup.c
+++ b/bsp/lpc824/applications/startup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -58,7 +58,7 @@ void rtthread_startup(void)
 #ifdef RT_USING_HEAP
     rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END);
 #endif
-    
+
     /* init scheduler system */
     rt_system_scheduler_init();
 
diff --git a/bsp/lpc824/drivers/board.c b/bsp/lpc824/drivers/board.c
index 51656718b8..0817a3b7e8 100644
--- a/bsp/lpc824/drivers/board.c
+++ b/bsp/lpc824/drivers/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -62,7 +62,7 @@ void rt_hw_board_init()
 #ifdef RT_USING_COMPONENTS_INIT
     rt_components_board_init();
 #endif
-    
+
 #ifdef RT_USING_CONSOLE
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
diff --git a/bsp/lpc824/drivers/board.h b/bsp/lpc824/drivers/board.h
index c8d21d94b5..d86369ce31 100644
--- a/bsp/lpc824/drivers/board.h
+++ b/bsp/lpc824/drivers/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc824/drivers/usart.c b/bsp/lpc824/drivers/usart.c
index 5109164a9a..54a56501c9 100644
--- a/bsp/lpc824/drivers/usart.c
+++ b/bsp/lpc824/drivers/usart.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,7 +28,7 @@ struct lpc8xx_uart
     LPC_USART_T * uart_base;
     IRQn_Type uart_irq;
     rt_uint8_t rx_buffer[UART_RX_BUFSZ];
-    
+
 };
 #ifdef RT_USING_UART0
 struct lpc8xx_uart uart0_device;
@@ -45,10 +45,10 @@ struct lpc8xx_uart uart2_device;
 void uart_irq_handler(struct lpc8xx_uart* uart)
 {
     uint32_t status;
-    
+
     /* enter interrupt */
     rt_interrupt_enter();
-    
+
     status = Chip_UART_GetStatus(uart->uart_base);
     if(status & UART_STAT_RXRDY)    // RXIRQ
     {
@@ -57,9 +57,9 @@ void uart_irq_handler(struct lpc8xx_uart* uart)
         if(uart->parent.rx_indicate != RT_NULL)
         {
             uart->parent.rx_indicate(&uart->parent, rt_ringbuffer_data_len(&uart->rx_rb));
-        }    
+        }
     }
-    
+
     /* leave interrupt */
     rt_interrupt_leave();
 }
@@ -88,15 +88,15 @@ void UART2_IRQHandler(void)
 static void uart1_io_init(LPC_USART_T * uart_base)
 {
     /* Enable the clock to the Switch Matrix */
-	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SWM);
-    
+    Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SWM);
+
     Chip_Clock_SetUARTClockDiv(1);
-    
+
 #ifdef RT_USING_UART0
     if (uart_base == LPC_USART0)
     {
-		Chip_SWM_MovablePinAssign(SWM_U0_TXD_O, 4);
-		Chip_SWM_MovablePinAssign(SWM_U0_RXD_I, 0);
+        Chip_SWM_MovablePinAssign(SWM_U0_TXD_O, 4);
+        Chip_SWM_MovablePinAssign(SWM_U0_RXD_I, 0);
     }
     else
 #endif
@@ -104,8 +104,8 @@ static void uart1_io_init(LPC_USART_T * uart_base)
 #ifdef RT_USING_UART1
     if (uart_base == LPC_USART1)
     {
-		Chip_SWM_MovablePinAssign(SWM_U1_TXD_O, 4);
-		Chip_SWM_MovablePinAssign(SWM_U1_RXD_I, 0);
+        Chip_SWM_MovablePinAssign(SWM_U1_TXD_O, 4);
+        Chip_SWM_MovablePinAssign(SWM_U1_RXD_I, 0);
     }
     else
 #endif
@@ -113,32 +113,32 @@ static void uart1_io_init(LPC_USART_T * uart_base)
 #ifdef RT_USING_UART2
     if (uart_base == LPC_USART2)
     {
-		Chip_SWM_MovablePinAssign(SWM_U2_TXD_O, 4);
-		Chip_SWM_MovablePinAssign(SWM_U2_RXD_I, 0);
+        Chip_SWM_MovablePinAssign(SWM_U2_TXD_O, 4);
+        Chip_SWM_MovablePinAssign(SWM_U2_RXD_I, 0);
     }
     else
 #endif
     {
         RT_ASSERT((uart_base == USART0) || (uart_base == USART2) || (uart_base == USART2));
     }
-    
-	/* Disable the clock to the Switch Matrix to save power */
-	Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_SWM);
+
+    /* Disable the clock to the Switch Matrix to save power */
+    Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_SWM);
 }
 
 static void uart_ll_init(LPC_USART_T * uart)
 {
     Chip_UART_Init(uart);
     Chip_UART_ConfigData(uart, UART_CFG_DATALEN_8 | UART_CFG_PARITY_NONE | UART_CFG_STOPLEN_1);
-	Chip_Clock_SetUSARTNBaseClockRate((115200 * 6 * 16), true);
-	Chip_UART_SetBaud(uart, 115200);
-	Chip_UART_Enable(uart);
-	Chip_UART_TXEnable(uart);
-    
-	// we must NOT enable TX ready/idle IRQ before we want to write data
-	// otherwise the IRQs will happen as soon as Uart IRQ is enabled in NVIC
-	Chip_UART_IntDisable(uart, UART_INTEN_TXRDY | UART_INTEN_TXIDLE);
-	Chip_UART_IntEnable(uart, UART_INTEN_RXRDY);
+    Chip_Clock_SetUSARTNBaseClockRate((115200 * 6 * 16), true);
+    Chip_UART_SetBaud(uart, 115200);
+    Chip_UART_Enable(uart);
+    Chip_UART_TXEnable(uart);
+
+    // we must NOT enable TX ready/idle IRQ before we want to write data
+    // otherwise the IRQs will happen as soon as Uart IRQ is enabled in NVIC
+    Chip_UART_IntDisable(uart, UART_INTEN_TXRDY | UART_INTEN_TXIDLE);
+    Chip_UART_IntEnable(uart, UART_INTEN_RXRDY);
 }
 
 static rt_err_t rt_uart_init (rt_device_t dev)
@@ -146,7 +146,7 @@ static rt_err_t rt_uart_init (rt_device_t dev)
     struct lpc8xx_uart* uart;
     RT_ASSERT(dev != RT_NULL);
     uart = (struct lpc8xx_uart *)dev;
-    
+
     uart1_io_init(uart->uart_base);
     uart_ll_init(uart->uart_base);
 
@@ -220,11 +220,11 @@ static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer
             if (*ptr == '\n')
             {
                 while (!(Chip_UART_GetStatus(uart->uart_base) & UART_STAT_TXRDY));
-                Chip_UART_SendByte(uart->uart_base, '\r');   
+                Chip_UART_SendByte(uart->uart_base, '\r');
             }
 
                 while (!(Chip_UART_GetStatus(uart->uart_base) & UART_STAT_TXRDY));
-            Chip_UART_SendByte(uart->uart_base, *ptr); 
+            Chip_UART_SendByte(uart->uart_base, *ptr);
 
             ptr ++;
             size --;
@@ -235,7 +235,7 @@ static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer
         while (size)
         {
             while (!(Chip_UART_GetStatus(uart->uart_base) & UART_STAT_TXRDY));
-            Chip_UART_SendByte(uart->uart_base, *ptr); 
+            Chip_UART_SendByte(uart->uart_base, *ptr);
 
             ptr++;
             size--;
@@ -258,14 +258,14 @@ int rt_hw_usart_init(void)
         uart->parent.type = RT_Device_Class_Char;
         uart->uart_base = LPC_USART0;
         uart->uart_irq = UART0_IRQn;
-        
+
         rt_ringbuffer_init(&(uart->rx_rb), uart->rx_buffer, sizeof(uart->rx_buffer));
 
         /* device interface */
-        uart->parent.init 	    = rt_uart_init;
-        uart->parent.open 	    = rt_uart_open;
+        uart->parent.init       = rt_uart_init;
+        uart->parent.open       = rt_uart_open;
         uart->parent.close      = rt_uart_close;
-        uart->parent.read 	    = rt_uart_read;
+        uart->parent.read       = rt_uart_read;
         uart->parent.write      = rt_uart_write;
         uart->parent.control    = RT_NULL;
         uart->parent.user_data  = RT_NULL;
@@ -273,7 +273,7 @@ int rt_hw_usart_init(void)
         rt_device_register(&uart->parent, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
     }
 #endif
-    
+
 #ifdef RT_USING_UART1
     {
         struct lpc8xx_uart* uart;
@@ -285,14 +285,14 @@ int rt_hw_usart_init(void)
         uart->parent.type = RT_Device_Class_Char;
         uart->uart_base = LPC_USART1;
         uart->uart_irq = UART1_IRQn;
-        
+
         rt_ringbuffer_init(&(uart->rx_rb), uart->rx_buffer, sizeof(uart->rx_buffer));
 
         /* device interface */
-        uart->parent.init 	    = rt_uart_init;
-        uart->parent.open 	    = rt_uart_open;
+        uart->parent.init       = rt_uart_init;
+        uart->parent.open       = rt_uart_open;
         uart->parent.close      = rt_uart_close;
-        uart->parent.read 	    = rt_uart_read;
+        uart->parent.read       = rt_uart_read;
         uart->parent.write      = rt_uart_write;
         uart->parent.control    = RT_NULL;
         uart->parent.user_data  = RT_NULL;
@@ -315,10 +315,10 @@ int rt_hw_usart_init(void)
         rt_ringbuffer_init(&(uart->rx_rb), uart->rx_buffer, sizeof(uart->rx_buffer));
 
         /* device interface */
-        uart->parent.init 	    = rt_uart_init;
-        uart->parent.open 	    = rt_uart_open;
+        uart->parent.init       = rt_uart_init;
+        uart->parent.open       = rt_uart_open;
         uart->parent.close      = rt_uart_close;
-        uart->parent.read 	    = rt_uart_read;
+        uart->parent.read       = rt_uart_read;
         uart->parent.write      = rt_uart_write;
         uart->parent.control    = RT_NULL;
         uart->parent.user_data  = RT_NULL;
diff --git a/bsp/lpc824/drivers/usart.h b/bsp/lpc824/drivers/usart.h
index 1db28e9385..7298cdab8b 100644
--- a/bsp/lpc824/drivers/usart.h
+++ b/bsp/lpc824/drivers/usart.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc824/rtconfig.h b/bsp/lpc824/rtconfig.h
index e8a551c2a3..d7c9608e28 100644
--- a/bsp/lpc824/rtconfig.h
+++ b/bsp/lpc824/rtconfig.h
@@ -6,17 +6,17 @@
 // <<< Use Configuration Wizard in Context Menu >>>
 // Basic Configuration
 // Maximal level of thread priority <8-256>
-//	Default: 32
+//  Default: 32
 #define RT_THREAD_PRIORITY_MAX  8
 // OS tick per second
 //  Default: 1000   (1ms)
-#define RT_TICK_PER_SECOND	100
+#define RT_TICK_PER_SECOND  100
 // Alignment size for CPU architecture data access
-//	Default: 4
+//  Default: 4
 #define RT_ALIGN_SIZE   4
 // the max length of object name<2-16>
-//	Default: 8
-#define RT_NAME_MAX	   8
+//  Default: 8
+#define RT_NAME_MAX    8
 // Using RT-Thread components initialization
 //  Using RT-Thread components initialization
 #define RT_USING_COMPONENTS_INIT
@@ -26,7 +26,7 @@
 //#define RT_USING_USER_MAIN
 // 
 // the size of main thread<1-4086>
-//	Default: 512
+//  Default: 512
 #define RT_MAIN_THREAD_STACK_SIZE     256
 
 // 
@@ -64,13 +64,13 @@
 #endif
 // The priority level of timer thread <0-31>
 //  Default: 4
-#define RT_TIMER_THREAD_PRIO		4
+#define RT_TIMER_THREAD_PRIO        4
 // The stack size of timer thread <0-8192>
 //  Default: 512
-#define RT_TIMER_THREAD_STACK_SIZE	512
+#define RT_TIMER_THREAD_STACK_SIZE  512
 // The soft-timer tick per second <0-1000>
 //  Default: 100
-#define RT_TIMER_TICK_PER_SECOND	100
+#define RT_TIMER_TICK_PER_SECOND    100
 // 
 
 // IPC(Inter-process communication) Configuration
@@ -164,7 +164,7 @@
 // the history lines of finsh thread <1-32>
 //  the history lines of finsh thread
 //  Default: 5
-#define FINSH_HISTORY_LINES	        1
+#define FINSH_HISTORY_LINES         1
 // Using symbol table in finsh shell
 //  Using symbol table in finsh shell
 #define FINSH_USING_SYMTAB
diff --git a/bsp/ls1bdev/Kconfig b/bsp/ls1bdev/Kconfig
index c1788b1c6b..b02aee337a 100644
--- a/bsp/ls1bdev/Kconfig
+++ b/bsp/ls1bdev/Kconfig
@@ -16,7 +16,6 @@ config PKGS_DIR
     default "packages"
 
 source "$RTT_DIR/Kconfig"
-source "$RTT_DIR/libcpu/mips/common/Kconfig"
 source "$PKGS_DIR/Kconfig"
 
 config SOC_LS1B
@@ -25,16 +24,33 @@ config SOC_LS1B
     select RT_USING_USER_MAIN
     default y
 
+config RT_MEM_SIZE
+    int "Memory Size (MByte)"
+    default 256
+
+config RT_OSC_CLK
+    int "Oscillator Clock (Hz)"
+    default 25000000
+
 if RT_USING_SERIAL
 config RT_USING_UART0
     bool "Using RT_USING_UART0"
-    default y
+    default n
 config RT_USING_UART1
     bool "Using RT_USING_UART1"
     default n
+config RT_USING_UART2
+    bool "Using RT_USING_UART2"
+    default n
 config RT_USING_UART3
     bool "Using RT_USING_UART3"
     default n
+config RT_USING_UART4
+    bool "Using RT_USING_UART4"
+    default n
+config RT_USING_UART5
+    bool "Using RT_USING_UART5"
+    default y
 
 config RT_UART_RX_BUFFER_SIZE
     int "The rx buffer size"
diff --git a/bsp/ls1bdev/drivers/board.c b/bsp/ls1bdev/drivers/board.c
index a3f907f664..0933568526 100644
--- a/bsp/ls1bdev/drivers/board.c
+++ b/bsp/ls1bdev/drivers/board.c
@@ -1,11 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2012, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -19,7 +15,7 @@
 #include 
 
 #include "board.h"
-#include "uart.h"
+#include "drv_uart.h"
 #include "ls1b.h"
 
 #ifdef RT_USING_RTGUI
@@ -33,7 +29,7 @@ extern unsigned char __bss_end;
 /**
  * @addtogroup Loongson LS1B
  */
- 
+
 /*@{*/
 
 /**
@@ -43,10 +39,10 @@ void rt_hw_board_init(void)
 {
     /* init hardware interrupt */
     rt_hw_exception_init();
-    
+
     /* init hardware interrupt */
     rt_hw_interrupt_init();
-    
+
 #ifdef RT_USING_HEAP
     rt_system_heap_init((void*)&__bss_end, (void*)RT_HW_HEAP_END);
 #endif
@@ -84,6 +80,6 @@ void rt_hw_board_init(void)
 #ifdef RT_USING_COMPONENTS_INIT
     rt_components_board_init();
 #endif
-
+    rt_kprintf("current sr: 0x%08x\n", read_c0_status());
 }
 /*@}*/
diff --git a/bsp/ls1bdev/drivers/board.h b/bsp/ls1bdev/drivers/board.h
index 9ba4f9f25c..7d7002892c 100644
--- a/bsp/ls1bdev/drivers/board.h
+++ b/bsp/ls1bdev/drivers/board.h
@@ -1,11 +1,7 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2012, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -19,7 +15,7 @@
 void rt_hw_board_init(void);
 
 /* 64M SDRAM */
-#define RT_HW_HEAP_END	(0x80000000 + 64 * 1024 * 1024)
-#define CPU_HZ			(125 * 1000000)
+#define RT_HW_HEAP_END  (0x80000000 + RT_MEM_SIZE * 1024 * 1024)
+#define CPU_HZ          (125 * 1000000)
 
 #endif
diff --git a/bsp/ls1bdev/drivers/display_controller.c b/bsp/ls1bdev/drivers/display_controller.c
index 060bd0a041..5dba114b69 100644
--- a/bsp/ls1bdev/drivers/display_controller.c
+++ b/bsp/ls1bdev/drivers/display_controller.c
@@ -1,11 +1,7 @@
 /*
- * File      : display_controller.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2012, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -17,24 +13,24 @@
 
 struct vga_struct vga_mode[] =
 {
-	{/*"640x480_70.00"*/    28560,  640,    664,    728,    816,    480,    481,    484,    500,    },
-	{/*"640x640_60.00"*/	33100,	640,	672,	736,	832,	640,	641,	644,	663,	},
-	{/*"640x768_60.00"*/	39690,	640,	672,	736,	832,	768,	769,	772,	795,	},
-	{/*"640x800_60.00"*/	42130,	640,	680,	744,	848,	800,	801,	804,	828,	},
-	{/*"800x480_70.00"*/    35840,  800,    832,    912,    1024,   480,    481,    484,    500,    },
-	{/*"800x600_60.00"*/	38220,	800,	832,	912,	1024,	600,	601,	604,	622,	},
-	{/*"800x640_60.00"*/	40730,	800,	832,	912,	1024,	640,	641,	644,	663,	},
-	{/*"832x600_60.00"*/	40010,	832,	864,	952,	1072,	600,	601,	604,	622,	},
-	{/*"832x608_60.00"*/	40520,	832,	864,	952,	1072,	608,	609,	612,	630,	},
-	{/*"1024x480_60.00"*/	38170,	1024,	1048,	1152,	1280,	480,	481,	484,	497,	},
-	{/*"1024x600_60.00"*/	48960,	1024,	1064,	1168,	1312,	600,	601,	604,	622,	},
-	{/*"1024x640_60.00"*/	52830,	1024,	1072,	1176,	1328,	640,	641,	644,	663,	},
-	{/*"1024x768_60.00"*/	64110,	1024,	1080,	1184,	1344,	768,	769,	772,	795,	},
-	{/*"1152x764_60.00"*/   71380,  1152,   1208,   1328,   1504,   764,    765,    768,    791,    },
-	{/*"1280x800_60.00"*/   83460,  1280,   1344,   1480,   1680,   800,    801,    804,    828,    },
-	{/*"1280x1024_55.00"*/  98600,  1280,   1352,   1488,   1696,   1024,   1025,   1028,   1057,   },
-	{/*"1440x800_60.00"*/   93800,  1440,   1512,   1664,   1888,   800,    801,    804,    828,    },
-	{/*"1440x900_67.00"*/   120280, 1440,   1528,   1680,   1920,   900,    901,    904,    935,    },
+    {/*"640x480_70.00"*/    28560,  640,    664,    728,    816,    480,    481,    484,    500,    },
+    {/*"640x640_60.00"*/    33100,  640,    672,    736,    832,    640,    641,    644,    663,    },
+    {/*"640x768_60.00"*/    39690,  640,    672,    736,    832,    768,    769,    772,    795,    },
+    {/*"640x800_60.00"*/    42130,  640,    680,    744,    848,    800,    801,    804,    828,    },
+    {/*"800x480_70.00"*/    35840,  800,    832,    912,    1024,   480,    481,    484,    500,    },
+    {/*"800x600_60.00"*/    38220,  800,    832,    912,    1024,   600,    601,    604,    622,    },
+    {/*"800x640_60.00"*/    40730,  800,    832,    912,    1024,   640,    641,    644,    663,    },
+    {/*"832x600_60.00"*/    40010,  832,    864,    952,    1072,   600,    601,    604,    622,    },
+    {/*"832x608_60.00"*/    40520,  832,    864,    952,    1072,   608,    609,    612,    630,    },
+    {/*"1024x480_60.00"*/   38170,  1024,   1048,   1152,   1280,   480,    481,    484,    497,    },
+    {/*"1024x600_60.00"*/   48960,  1024,   1064,   1168,   1312,   600,    601,    604,    622,    },
+    {/*"1024x640_60.00"*/   52830,  1024,   1072,   1176,   1328,   640,    641,    644,    663,    },
+    {/*"1024x768_60.00"*/   64110,  1024,   1080,   1184,   1344,   768,    769,    772,    795,    },
+    {/*"1152x764_60.00"*/   71380,  1152,   1208,   1328,   1504,   764,    765,    768,    791,    },
+    {/*"1280x800_60.00"*/   83460,  1280,   1344,   1480,   1680,   800,    801,    804,    828,    },
+    {/*"1280x1024_55.00"*/  98600,  1280,   1352,   1488,   1696,   1024,   1025,   1028,   1057,   },
+    {/*"1440x800_60.00"*/   93800,  1440,   1512,   1664,   1888,   800,    801,    804,    828,    },
+    {/*"1440x900_67.00"*/   120280, 1440,   1528,   1680,   1920,   900,    901,    904,    935,    },
 };
 
 ALIGN(16)
@@ -46,189 +42,189 @@ static struct rt_device_graphic_info _dc_info;
 
 int caclulate_freq(long long XIN, long long PCLK)
 {
-	int i;
-	long long clk, clk1;
-	int start, end;
-	int mi;
-	int pll,ctrl,div,div1,frac;
+    int i;
+    long long clk, clk1;
+    int start, end;
+    int mi;
+    int pll,ctrl,div,div1,frac;
 
-	pll = PLL_FREQ;
-	ctrl = PLL_DIV_PARAM;
-	rt_kprintf("pll=0x%x, ctrl=0x%x\n", pll, ctrl);
-//	rt_kprintf("cpu freq is %d\n", tgt_pipefreq());
-	start = -1;
-	end = 1;
+    pll = PLL_FREQ;
+    ctrl = PLL_DIV_PARAM;
+    rt_kprintf("pll=0x%x, ctrl=0x%x\n", pll, ctrl);
+//  rt_kprintf("cpu freq is %d\n", tgt_pipefreq());
+    start = -1;
+    end = 1;
 
-	for (i=start; i<=end; i++)
-	{
-		clk = (12+i+(pll&0x3f))*33333333/2;
-		div = clk/(long)PCLK/1000;
-		clk1 = (12+i+1+(pll&0x3f))*33333333/2;
-		div1 = clk1/(long)PCLK/1000;
-		if (div!=div1)
-			break;
-	}
+    for (i=start; i<=end; i++)
+    {
+        clk = (12+i+(pll&0x3f))*33333333/2;
+        div = clk/(long)PCLK/1000;
+        clk1 = (12+i+1+(pll&0x3f))*33333333/2;
+        div1 = clk1/(long)PCLK/1000;
+        if (div!=div1)
+            break;
+    }
 
-	if (div!=div1)
-	{
-		frac = ((PCLK*1000*div1)*2*1024/33333333 - (12+i+(pll&0x3f))*1024)&0x3ff;
-		pll = (pll & ~0x3ff3f)|(frac<<8)|((pll&0x3f)+i);
-		ctrl = ctrl&~(0x1f<<26)|(div1<<26)|(1<<31);
-	}
-	else
-	{
-		clk = (12+start+(pll&0x3f))*33333333/2;
-		clk1 = (12+end+(pll&0x3f))*33333333/2;
-		if (abs((long)clk/div/1000-PCLK)type = RT_Device_Class_Graphic;
-	dc->init = rt_dc_init;
-	dc->open = RT_NULL;
-	dc->close = RT_NULL;
-	dc->control = rt_dc_control;
-	dc->user_data = (void*)&_dc_info;
-	
-	/* register Display Controller device to RT-Thread */
-	rt_device_register(dc, "dc", RT_DEVICE_FLAG_RDWR);
+    /* init device structure */
+    dc->type = RT_Device_Class_Graphic;
+    dc->init = rt_dc_init;
+    dc->open = RT_NULL;
+    dc->close = RT_NULL;
+    dc->control = rt_dc_control;
+    dc->user_data = (void*)&_dc_info;
+
+    /* register Display Controller device to RT-Thread */
+    rt_device_register(dc, "dc", RT_DEVICE_FLAG_RDWR);
 }
diff --git a/bsp/ls1bdev/drivers/display_controller.h b/bsp/ls1bdev/drivers/display_controller.h
index 5554eb1c2e..1fa6243a72 100644
--- a/bsp/ls1bdev/drivers/display_controller.h
+++ b/bsp/ls1bdev/drivers/display_controller.h
@@ -1,58 +1,54 @@
 /*
- * File      : display_controller.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2012, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2011-08-08     lgnq         first version for LS1B
  */
- 
+
 #ifndef __DISPLAY_CONTROLLER_H__
 #define __DISPLAY_CONTROLLER_H__
 
 #include 
 #include "ls1b.h"
 
-#define DC_BASE					0xBC301240  //Display Controller
+#define DC_BASE                 0xBC301240  //Display Controller
 
 /* Frame Buffer registers */
-#define DC_FB_CONFIG			__REG32(DC_BASE + 0x000)
-#define DC_FB_BUFFER_ADDR0		__REG32(DC_BASE + 0x020)
-#define DC_FB_BUFFER_STRIDE		__REG32(DC_BASE + 0x040)
-#define DC_FB_BUFFER_ORIGIN		__REG32(DC_BASE + 0x060)
-#define DC_DITHER_CONFIG		__REG32(DC_BASE + 0x120)
-#define DC_DITHER_TABLE_LOW		__REG32(DC_BASE + 0x140)
-#define DC_DITHER_TABLE_HIGH	__REG32(DC_BASE + 0x160)
-#define DC_PANEL_CONFIG			__REG32(DC_BASE + 0x180)
-#define DC_PANEL_TIMING			__REG32(DC_BASE + 0x1A0)
-#define DC_HDISPLAY				__REG32(DC_BASE + 0x1C0)
-#define DC_HSYNC				__REG32(DC_BASE + 0x1E0)
-#define DC_VDISPLAY				__REG32(DC_BASE + 0x240)
-#define DC_VSYNC				__REG32(DC_BASE + 0x260)
-#define DC_FB_BUFFER_ADDR1		__REG32(DC_BASE + 0x340)
+#define DC_FB_CONFIG            __REG32(DC_BASE + 0x000)
+#define DC_FB_BUFFER_ADDR0      __REG32(DC_BASE + 0x020)
+#define DC_FB_BUFFER_STRIDE     __REG32(DC_BASE + 0x040)
+#define DC_FB_BUFFER_ORIGIN     __REG32(DC_BASE + 0x060)
+#define DC_DITHER_CONFIG        __REG32(DC_BASE + 0x120)
+#define DC_DITHER_TABLE_LOW     __REG32(DC_BASE + 0x140)
+#define DC_DITHER_TABLE_HIGH    __REG32(DC_BASE + 0x160)
+#define DC_PANEL_CONFIG         __REG32(DC_BASE + 0x180)
+#define DC_PANEL_TIMING         __REG32(DC_BASE + 0x1A0)
+#define DC_HDISPLAY             __REG32(DC_BASE + 0x1C0)
+#define DC_HSYNC                __REG32(DC_BASE + 0x1E0)
+#define DC_VDISPLAY             __REG32(DC_BASE + 0x240)
+#define DC_VSYNC                __REG32(DC_BASE + 0x260)
+#define DC_FB_BUFFER_ADDR1      __REG32(DC_BASE + 0x340)
 
 /* Display Controller driver for 1024x768 16bit */
-#define FB_XSIZE		1024
-#define FB_YSIZE		768
+#define FB_XSIZE        1024
+#define FB_YSIZE        768
 #define CONFIG_VIDEO_16BPP
 
 #define APB_CLK 33333333
 
-#define K1BASE				0xA0000000
-#define KSEG1(addr)			((void *)(K1BASE | (rt_uint32_t)(addr)))
-#define HW_FB_ADDR			KSEG1(_rt_framebuffer)
-#define HW_FB_PIXEL(x, y)	*(volatile rt_uint16_t*)((rt_uint8_t*)HW_FB_ADDR + (y * FB_XSIZE * 2) + x * 2)
+#define K1BASE              0xA0000000
+#define KSEG1(addr)         ((void *)(K1BASE | (rt_uint32_t)(addr)))
+#define HW_FB_ADDR          KSEG1(_rt_framebuffer)
+#define HW_FB_PIXEL(x, y)   *(volatile rt_uint16_t*)((rt_uint8_t*)HW_FB_ADDR + (y * FB_XSIZE * 2) + x * 2)
 
 struct vga_struct
 {
-	long pclk;
-	int hr,hss,hse,hfl;
-	int vr,vss,vse,vfl;
+    long pclk;
+    int hr,hss,hse,hfl;
+    int vr,vss,vse,vfl;
 };
 
 #endif
diff --git a/bsp/ls1bdev/drivers/drv_uart.c b/bsp/ls1bdev/drivers/drv_uart.c
new file mode 100644
index 0000000000..8f469f26ed
--- /dev/null
+++ b/bsp/ls1bdev/drivers/drv_uart.c
@@ -0,0 +1,222 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-05-08     zhuangwei    the first version
+ * 2021-02-02     michael5hzg@gmail.com    adapt to ls1b
+ */
+#include 
+#include 
+#include 
+#include "drv_uart.h"
+#include "ls1b_pin.h"
+#include "ls1b_uart.h"
+
+/* STM32 uart driver */
+struct rt_uart_ls1b
+{
+    ls1b_uart_t UARTx;
+    rt_uint32_t IRQ;
+};
+
+static rt_err_t ls1b_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct rt_uart_ls1b *uart_dev = RT_NULL;
+    ls1b_uart_info_t uart_info = {0};
+
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+
+    uart_dev = (struct rt_uart_ls1b *)serial->parent.user_data;
+
+    // 初始化串口
+    uart_info.UARTx    = uart_dev->UARTx;
+    uart_info.baudrate = cfg->baud_rate;
+    uart_info.rx_enable = TRUE;
+    uart_init(&uart_info);
+
+    return RT_EOK;
+
+}
+
+static rt_err_t ls1b_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct rt_uart_ls1b *uart_dev = RT_NULL;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart_dev = (struct rt_uart_ls1b *)serial->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT: /* disable rx irq */
+        rt_hw_interrupt_mask(uart_dev->IRQ);
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT: /* enable rx irq */
+        rt_hw_interrupt_umask(uart_dev->IRQ);
+        break;
+
+    default:
+        break;
+    }
+
+    return RT_EOK;
+
+}
+
+static int ls1b_uart_putc(struct rt_serial_device *serial, char c)
+{
+    struct rt_uart_ls1b *uart_dev = RT_NULL;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart_dev = (struct rt_uart_ls1b *)serial->parent.user_data;
+    uart_putc(uart_dev->UARTx, c);
+
+    return 1;
+}
+
+static int ls1b_uart_getc(struct rt_serial_device *serial)
+{
+    struct rt_uart_ls1b *uart_dev = RT_NULL;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart_dev = (struct rt_uart_ls1b *)serial->parent.user_data;
+    void *uart_base = uart_get_base(uart_dev->UARTx);
+
+    if (LSR_RXRDY & reg_read_8(uart_base + LS1B_UART_LSR_OFFSET))
+    {
+        return reg_read_8(uart_base + LS1B_UART_DAT_OFFSET);
+    }
+
+    return -1;
+}
+
+/* UART interrupt handler */
+static void uart_irq_handler(int vector, void *param)
+{
+    struct rt_serial_device *serial = (struct rt_serial_device *)param;
+    struct rt_uart_ls1b *uart_dev = RT_NULL;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart_dev = (struct rt_uart_ls1b *)serial->parent.user_data;
+    void *uart_base = uart_get_base(uart_dev->UARTx);
+    unsigned char iir = reg_read_8(uart_base + LS1B_UART_IIR_OFFSET);
+
+    // 判断是否为接收超时或接收到有效数据
+    if ((IIR_RXTOUT & iir) || (IIR_RXRDY & iir))
+    {
+        rt_interrupt_enter();
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+        rt_interrupt_leave();
+    }
+
+}
+
+static const struct rt_uart_ops ls1b_uart_ops =
+{
+    ls1b_uart_configure,
+    ls1b_uart_control,
+    ls1b_uart_putc,
+    ls1b_uart_getc,
+};
+
+
+#if defined(RT_USING_UART1)
+struct rt_uart_ls1b uart1 =
+{
+    LS1B_UART1,
+    LS1B_UART1_IRQ,
+};
+struct rt_serial_device serial1;
+#endif /* RT_USING_UART1 */
+
+#if defined(RT_USING_UART2)
+struct rt_uart_ls1b uart2 =
+{
+    LS1B_UART2,
+    LS1B_UART2_IRQ,
+};
+struct rt_serial_device serial2;
+#endif /* RT_USING_UART2 */
+
+
+#if defined(RT_USING_UART3)
+struct rt_uart_ls1b uart3 =
+{
+    LS1B_UART3,
+    LS1B_UART3_IRQ,
+};
+struct rt_serial_device serial3;
+#endif /* RT_USING_UART3 */
+
+#if defined(RT_USING_UART4)
+struct rt_uart_ls1b uart4 =
+{
+    LS1B_UART4,
+    LS1B_UART4_IRQ,
+};
+struct rt_serial_device serial4;
+#endif /* RT_USING_UART4 */
+
+#if defined(RT_USING_UART5)
+struct rt_uart_ls1b uart5 =
+{
+    LS1B_UART5,
+    LS1B_UART5_IRQ,
+};
+struct rt_serial_device serial5;
+#endif /* RT_USING_UART5 */
+
+
+
+void rt_hw_uart_init(void)
+{
+    struct rt_uart_ls1b *uart;
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+#ifdef RT_USING_UART5
+		uart = &uart5;
+	
+		serial5.ops    = &ls1b_uart_ops;
+		serial5.config = config;
+	
+		rt_hw_interrupt_install(uart->IRQ, uart_irq_handler, &serial5, "UART5");
+	
+		/* register UART5 device */
+		rt_hw_serial_register(&serial5,
+							  "uart5",
+							  //RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_DMA_RX,
+							  RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+							  uart);
+#endif /* RT_USING_UART5 */
+
+
+#ifdef RT_USING_UART2
+    uart = &uart2;
+
+    serial2.ops    = &ls1b_uart_ops;
+    serial2.config = config;
+
+    pin_set_purpose(36, PIN_PURPOSE_OTHER);
+    pin_set_purpose(37, PIN_PURPOSE_OTHER);
+    pin_set_remap(36, PIN_REMAP_SECOND);
+    pin_set_remap(37, PIN_REMAP_SECOND);
+
+    rt_hw_interrupt_install(uart->IRQ, uart_irq_handler, &serial2, "UART2");
+
+    /* register UART2 device */
+    rt_hw_serial_register(&serial2,
+                          "uart2",
+                          //RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_DMA_RX,
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+#endif /* RT_USING_UART2 */
+
+}
+
diff --git a/bsp/ls1bdev/drivers/drv_uart.h b/bsp/ls1bdev/drivers/drv_uart.h
new file mode 100644
index 0000000000..01dfd9aae0
--- /dev/null
+++ b/bsp/ls1bdev/drivers/drv_uart.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-05-08     zhuangwei    the first version
+ */
+
+#ifndef __DRV_UART_H__
+#define __DRV_UART_H__
+
+#include "ls1b.h"
+#include 
+
+#define DEV_CLK 252000000 // 252MHz
+#define UART_BAUDRATE 115200
+
+#define UART0_BASE          0xBFE40000
+//#define UART0_1_BASE      0xBFE41000
+#define UART1_BASE          0xBFE44000
+#define UART2_BASE          0xBFE48000
+#define UART3_BASE          0xBFE4C000
+#define UART4_BASE          0xBFE4C400
+#define UART5_BASE          0xBFE4C500
+#define UART6_BASE          0xBFE4C600
+#define UART7_BASE          0xBFE4C700
+#define UART8_BASE          0xBFE4C800
+#define UART9_BASE          0xBFE4C900
+#define UART10_BASE         0xBFE4Ca00
+#define UART11_BASE         0xBFE4Cb00
+
+/* UART registers */
+#define UART_DAT(base)      HWREG8(base + 0x00)
+#define UART_IER(base)      HWREG8(base + 0x01)
+#define UART_IIR(base)      HWREG8(base + 0x02)
+#define UART_FCR(base)      HWREG8(base + 0x02)
+#define UART_LCR(base)      HWREG8(base + 0x03)
+#define UART_MCR(base)      HWREG8(base + 0x04)
+#define UART_LSR(base)      HWREG8(base + 0x05)
+#define UART_MSR(base)      HWREG8(base + 0x06)
+
+#define UART_LSB(base)      HWREG8(base + 0x00)
+#define UART_MSB(base)      HWREG8(base + 0x01)
+
+/* UART0 registers */
+#define UART0_DAT           HWREG8(UART0_BASE + 0x00)
+#define UART0_IER           HWREG8(UART0_BASE + 0x01)
+#define UART0_IIR           HWREG8(UART0_BASE + 0x02)
+#define UART0_FCR           HWREG8(UART0_BASE + 0x02)
+#define UART0_LCR           HWREG8(UART0_BASE + 0x03)
+#define UART0_MCR           HWREG8(UART0_BASE + 0x04)
+#define UART0_LSR           HWREG8(UART0_BASE + 0x05)
+#define UART0_MSR           HWREG8(UART0_BASE + 0x06)
+
+#define UART0_LSB           HWREG8(UART0_BASE + 0x00)
+#define UART0_MSB           HWREG8(UART0_BASE + 0x01)
+
+/* UART1 registers */
+#define UART1_DAT           HWREG8(UART1_BASE + 0x00)
+#define UART1_IER           HWREG8(UART1_BASE + 0x01)
+#define UART1_IIR           HWREG8(UART1_BASE + 0x02)
+#define UART1_FCR           HWREG8(UART1_BASE + 0x02)
+#define UART1_LCR           HWREG8(UART1_BASE + 0x03)
+#define UART1_MCR           HWREG8(UART1_BASE + 0x04)
+#define UART1_LSR           HWREG8(UART1_BASE + 0x05)
+#define UART1_MSR           HWREG8(UART1_BASE + 0x06)
+
+#define UART1_LSB           HWREG8(UART1_BASE + 0x00)
+#define UART1_MSB           HWREG8(UART1_BASE + 0x01)
+
+/* UART interrupt enable register value */
+#define UARTIER_IME     (1 << 3)
+#define UARTIER_ILE     (1 << 2)
+#define UARTIER_ITXE    (1 << 1)
+#define UARTIER_IRXE    (1 << 0)
+
+/* UART line control register value */
+#define UARTLCR_DLAB    (1 << 7)
+#define UARTLCR_BCB     (1 << 6)
+#define UARTLCR_SPB     (1 << 5)
+#define UARTLCR_EPS     (1 << 4)
+#define UARTLCR_PE      (1 << 3)
+#define UARTLCR_SB      (1 << 2)
+
+/* UART line status register value */
+#define UARTLSR_ERROR   (1 << 7)
+#define UARTLSR_TE      (1 << 6)
+#define UARTLSR_TFE     (1 << 5)
+#define UARTLSR_BI      (1 << 4)
+#define UARTLSR_FE      (1 << 3)
+#define UARTLSR_PE      (1 << 2)
+#define UARTLSR_OE      (1 << 1)
+#define UARTLSR_DR      (1 << 0)
+
+void rt_hw_uart_init(void);
+
+
+#endif
diff --git a/bsp/ls1bdev/drivers/uart.c b/bsp/ls1bdev/drivers/uart.c
deleted file mode 100644
index e920d33057..0000000000
--- a/bsp/ls1bdev/drivers/uart.c
+++ /dev/null
@@ -1,280 +0,0 @@
-/*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2012, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2011-08-08     lgnq         first version
- */
-
-#include 
-#include 
-
-#include "uart.h"
-
-/**
- * @addtogroup Loongson LS1B
- */
-
-/*@{*/
-
-#if defined(RT_USING_DEVICE)
-
-struct rt_uart_ls1b
-{
-    struct rt_device parent;
-
-    rt_uint32_t hw_base;
-    rt_uint32_t irq;
-
-    /* buffer for reception */
-    rt_uint8_t read_index, save_index;
-    rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
-}uart_device;
-
-static void rt_uart_irqhandler(int irqno, void *param)
-{
-    rt_ubase_t level;
-    rt_uint8_t isr;
-    struct rt_uart_ls1b *uart = &uart_device;
-
-    /* read interrupt status and clear it */
-    isr = UART_IIR(uart->hw_base);
-    isr = (isr >> 1) & 0x3;
-
-    /* receive data available */
-    if (isr & 0x02)
-    {
-        /* Receive Data Available */
-        while (UART_LSR(uart->hw_base) & UARTLSR_DR)
-        {
-            uart->rx_buffer[uart->save_index] = UART_DAT(uart->hw_base);
-
-            level = rt_hw_interrupt_disable();
-            uart->save_index ++;
-            if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
-                uart->save_index = 0;
-            rt_hw_interrupt_enable(level);
-        }
-
-        /* invoke callback */
-        if (uart->parent.rx_indicate != RT_NULL)
-        {
-            rt_size_t length;
-            if (uart->read_index > uart->save_index)
-                length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
-            else
-                length = uart->save_index - uart->read_index;
-
-            uart->parent.rx_indicate(&uart->parent, length);
-        }
-    }
-
-    return;
-}
-
-static rt_err_t rt_uart_init(rt_device_t dev)
-{
-    rt_uint32_t baud_div;
-    struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
-
-    RT_ASSERT(uart != RT_NULL);
-
-#if 0
-    /* init UART Hardware */
-    UART_IER(uart->hw_base) = 0; /* clear interrupt */
-    UART_FCR(uart->hw_base) = 0x60; /* reset UART Rx/Tx */
-
-    /* enable UART clock */
-    /* set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
-    UART_LCR(uart->hw_base) = 0x3;
-
-    /* set baudrate */
-    baud_div = DEV_CLK / 16 / UART_BAUDRATE;
-    UART_LCR(uart->hw_base) |= UARTLCR_DLAB;
-
-    UART_MSB(uart->hw_base) = (baud_div >> 8) & 0xff;
-    UART_LSB(uart->hw_base) = baud_div & 0xff;
-
-    UART_LCR(uart->hw_base) &= ~UARTLCR_DLAB;
-
-    /* Enable UART unit, enable and clear FIFO */
-    UART_FCR(uart->hw_base) = UARTFCR_UUE | UARTFCR_FE | UARTFCR_TFLS | UARTFCR_RFLS;
-#endif
-
-    return RT_EOK;
-}
-
-static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
-{
-    struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
-
-    RT_ASSERT(uart != RT_NULL);
-    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-    {
-        /* Enable the UART Interrupt */
-        UART_IER(uart->hw_base) |= UARTIER_IRXE;
-
-        /* install interrupt */
-        rt_hw_interrupt_install(uart->irq, rt_uart_irqhandler, RT_NULL, "UART");
-        rt_hw_interrupt_umask(uart->irq);
-    }
-    return RT_EOK;
-}
-
-static rt_err_t rt_uart_close(rt_device_t dev)
-{
-    struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
-
-    RT_ASSERT(uart != RT_NULL);
-    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-    {
-        /* Disable the UART Interrupt */
-        UART_IER(uart->hw_base) &= ~(UARTIER_IRXE);
-    }
-
-    return RT_EOK;
-}
-
-static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
-{
-    rt_uint8_t *ptr;
-    struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
-
-    RT_ASSERT(uart != RT_NULL);
-
-    /* point to buffer */
-    ptr = (rt_uint8_t *)buffer;
-    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-    {
-        while (size)
-        {
-            /* interrupt receive */
-            rt_base_t level;
-
-            /* disable interrupt */
-            level = rt_hw_interrupt_disable();
-            if (uart->read_index != uart->save_index)
-            {
-                *ptr = uart->rx_buffer[uart->read_index];
-
-                uart->read_index ++;
-                if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
-                    uart->read_index = 0;
-            }
-            else
-            {
-                /* no data in rx buffer */
-
-                /* enable interrupt */
-                rt_hw_interrupt_enable(level);
-                break;
-            }
-
-            /* enable interrupt */
-            rt_hw_interrupt_enable(level);
-
-            ptr ++;
-            size --;
-        }
-
-        return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-    }
-
-    return 0;
-}
-
-static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
-{
-    char *ptr;
-    struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
-
-    RT_ASSERT(uart != RT_NULL);
-
-    ptr = (char *)buffer;
-
-    if (dev->flag & RT_DEVICE_FLAG_STREAM)
-    {
-        /* stream mode */
-        while (size)
-        {
-            if (*ptr == '\n')
-            {
-                /* FIFO status, contain valid data */
-                while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
-                /* write data */
-                UART_DAT(uart->hw_base) = '\r';
-            }
-
-            /* FIFO status, contain valid data */
-            while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
-            /* write data */
-            UART_DAT(uart->hw_base) = *ptr;
-
-            ptr ++;
-            size --;
-        }
-    }
-    else
-    {
-        while (size != 0)
-        {
-            /* FIFO status, contain valid data */
-            while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
-
-            /* write data */
-            UART_DAT(uart->hw_base) = *ptr;
-
-            ptr++;
-            size--;
-        }
-    }
-
-    return (rt_size_t)ptr - (rt_size_t)buffer;
-}
-
-void rt_hw_uart_init(void)
-{
-    struct rt_uart_ls1b *uart;
-
-    /* get uart device */
-    uart = &uart_device;
-
-    /* device initialization */
-    uart->parent.type = RT_Device_Class_Char;
-    rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
-    uart->read_index = uart->save_index = 0;
-
-#if defined(RT_USING_UART0)
-    uart->hw_base = UART0_BASE;
-    uart->irq = LS1B_UART0_IRQ;
-#elif defined(RT_USING_UART1)
-    uart->hw_base = UART1_BASE;
-    uart->irq = LS1B_UART1_IRQ;
-#elif defined(RT_USING_UART3)
-    uart->hw_base = UART3_BASE;
-    uart->irq = LS1B_UART3_IRQ;
-#endif
-
-    /* device interface */
-    uart->parent.init       = rt_uart_init;
-    uart->parent.open       = rt_uart_open;
-    uart->parent.close      = rt_uart_close;
-    uart->parent.read       = rt_uart_read;
-    uart->parent.write      = rt_uart_write;
-    uart->parent.control    = RT_NULL;
-    uart->parent.user_data  = RT_NULL;
-
-    rt_device_register(&uart->parent, "uart0",
-                        RT_DEVICE_FLAG_RDWR |
-                        RT_DEVICE_FLAG_STREAM |
-                        RT_DEVICE_FLAG_INT_RX);
-}
-#endif /* end of UART */
-
-/*@}*/
diff --git a/bsp/ls1bdev/drivers/uart.h b/bsp/ls1bdev/drivers/uart.h
deleted file mode 100644
index bec660b740..0000000000
--- a/bsp/ls1bdev/drivers/uart.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * File      : uart.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2012, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2011-08-08     lgnq         first version for LS1B
- */
-
-#ifndef __UART_H__
-#define __UART_H__
-
-#include "ls1b.h"
-#include 
-
-#define UART0_BASE		    0xBFE40000
-#define UART0_1_BASE		0xBFE41000
-#define UART0_2_BASE		0xBFE42000
-#define UART0_3_BASE		0xBFE43000
-#define UART1_BASE			0xBFE44000
-#define UART1_1_BASE		0xBFE45000
-#define UART1_2_BASE		0xBFE46000
-#define UART1_3_BASE		0xBFE47000
-#define UART2_BASE			0xBFE48000
-#define UART3_BASE			0xBFE4C000
-#define UART4_BASE			0xBFE6C000
-#define UART5_BASE			0xBFE7C000
-
-/* UART registers */
-#define UART_DAT(base)		HWREG8(base + 0x00)
-#define UART_IER(base)		HWREG8(base + 0x01)
-#define UART_IIR(base)		HWREG8(base + 0x02)
-#define UART_FCR(base)		HWREG8(base + 0x02)
-#define UART_LCR(base)		HWREG8(base + 0x03)
-#define UART_MCR(base)		HWREG8(base + 0x04)
-#define UART_LSR(base)		HWREG8(base + 0x05)
-#define UART_MSR(base)		HWREG8(base + 0x06)
-
-#define UART_LSB(base)		HWREG8(base + 0x00)
-#define UART_MSB(base)		HWREG8(base + 0x01)
-
-/* UART0 registers */
-#define UART0_DAT			HWREG8(UART0_BASE + 0x00)
-#define UART0_IER			HWREG8(UART0_BASE + 0x01)
-#define UART0_IIR			HWREG8(UART0_BASE + 0x02)
-#define UART0_FCR			HWREG8(UART0_BASE + 0x02)
-#define UART0_LCR			HWREG8(UART0_BASE + 0x03)
-#define UART0_MCR			HWREG8(UART0_BASE + 0x04)
-#define UART0_LSR			HWREG8(UART0_BASE + 0x05)
-#define UART0_MSR			HWREG8(UART0_BASE + 0x06)
-
-#define UART0_LSB			HWREG8(UART0_BASE + 0x00)
-#define UART0_MSB			HWREG8(UART0_BASE + 0x01)
-
-/* UART1 registers */
-#define UART1_DAT			HWREG8(UART1_BASE + 0x00)
-#define UART1_IER			HWREG8(UART1_BASE + 0x01)
-#define UART1_IIR			HWREG8(UART1_BASE + 0x02)
-#define UART1_FCR			HWREG8(UART1_BASE + 0x02)
-#define UART1_LCR			HWREG8(UART1_BASE + 0x03)
-#define UART1_MCR			HWREG8(UART1_BASE + 0x04)
-#define UART1_LSR			HWREG8(UART1_BASE + 0x05)
-#define UART1_MSR			HWREG8(UART1_BASE + 0x06)
-
-#define UART1_LSB			HWREG8(UART1_BASE + 0x00)
-#define UART1_MSB			HWREG8(UART1_BASE + 0x01)
-
-/* UART interrupt enable register value */
-#define UARTIER_IME		(1 << 3)
-#define UARTIER_ILE		(1 << 2) 
-#define UARTIER_ITXE	(1 << 1)
-#define UARTIER_IRXE	(1 << 0)
-
-/* UART line control register value */
-#define UARTLCR_DLAB	(1 << 7)
-#define UARTLCR_BCB		(1 << 6)
-#define UARTLCR_SPB		(1 << 5)
-#define UARTLCR_EPS		(1 << 4)
-#define UARTLCR_PE		(1 << 3)
-#define UARTLCR_SB		(1 << 2)
-
-/* UART line status register value */
-#define UARTLSR_ERROR	(1 << 7)
-#define UARTLSR_TE		(1 << 6)
-#define UARTLSR_TFE		(1 << 5)
-#define UARTLSR_BI		(1 << 4)
-#define UARTLSR_FE		(1 << 3)
-#define UARTLSR_PE		(1 << 2)
-#define UARTLSR_OE		(1 << 1)
-#define UARTLSR_DR		(1 << 0)
-
-void rt_hw_uart_init(void);
-
-#endif
diff --git a/bsp/ls1bdev/libraries/SConscript b/bsp/ls1bdev/libraries/SConscript
new file mode 100644
index 0000000000..78797ef273
--- /dev/null
+++ b/bsp/ls1bdev/libraries/SConscript
@@ -0,0 +1,10 @@
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+
+CPPPATH = [cwd]
+
+group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/ls1bdev/libraries/ls1b_clock.c b/bsp/ls1bdev/libraries/ls1b_clock.c
new file mode 100644
index 0000000000..05547a158c
--- /dev/null
+++ b/bsp/ls1bdev/libraries/ls1b_clock.c
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-06     勤为本       first version
+ * 2021-02-02     michael5hzg@gmail.com       adapt to ls1b
+ */
+
+
+#include "rtconfig.h"
+#include "ls1b_regs.h"
+#include "ls1b_public.h"
+
+
+// 晶振的频率
+#define AHB_CLK                 (RT_OSC_CLK)
+#define APB_CLK                 (AHB_CLK)
+
+#define DIV_DC_EN			(0x1 << 31)
+#define DIV_DC				(0x1f << 26)
+#define DIV_CPU_EN			(0x1 << 25)
+#define DIV_CPU				(0x1f << 20)
+#define DIV_DDR_EN			(0x1 << 19)
+#define DIV_DDR				(0x1f << 14)
+
+#define DIV_DC_SHIFT			26
+#define DIV_CPU_SHIFT			20
+#define DIV_DDR_SHIFT			14
+
+
+/*
+ * 获取PLL频率
+ * @ret PLL频率
+ */
+unsigned long clk_get_pll_rate(void)
+{
+    unsigned int ctrl;
+    unsigned long pll_rate = 0;
+
+    ctrl = reg_read_32((volatile unsigned int *)LS1B_START_FREQ);
+	pll_rate = (12 + (ctrl & 0x3f)) * APB_CLK / 2
+		+ ((ctrl >> 8) & 0x3ff) * APB_CLK / 1024 / 2;
+
+    return pll_rate;
+}
+
+
+/*
+ * 获取CPU频率
+ * @ret CPU频率
+ */
+unsigned long clk_get_cpu_rate(void)
+{
+    unsigned long pll_rate, cpu_rate;
+    unsigned int ctrl;
+
+    pll_rate = clk_get_pll_rate();
+    ctrl = reg_read_32((volatile unsigned int *)LS1B_CLK_DIV_PARAM);
+	cpu_rate = pll_rate / ((ctrl & DIV_CPU) >> DIV_CPU_SHIFT);
+
+    return cpu_rate;
+}
+
+
+/*
+ * 获取DDR频率
+ * @ret DDR频率
+ */
+unsigned long clk_get_ddr_rate(void)
+{
+    unsigned long pll_rate, ddr_rate;
+	unsigned int ctrl;
+
+	pll_rate = clk_get_pll_rate();
+	ctrl = reg_read_32((volatile unsigned int *)LS1B_CLK_DIV_PARAM);
+
+	ddr_rate = pll_rate / ((ctrl & DIV_DDR) >> DIV_DDR_SHIFT);
+
+    return ddr_rate;
+}
+
+
+/*
+ * 获取APB频率
+ * @ret APB频率
+ */
+unsigned long clk_get_apb_rate(void)
+{
+    return clk_get_ddr_rate() / 2;
+}
+
+
+/*
+ * 获取DC频率
+ * @ret DC频率
+ */
+unsigned long clk_get_dc_rate(void)
+{
+    unsigned long pll_rate, dc_rate;
+    unsigned int ctrl;
+
+    pll_rate = clk_get_pll_rate();
+    ctrl = reg_read_32((volatile unsigned int *)LS1B_CLK_DIV_PARAM);
+
+    dc_rate = pll_rate ;
+
+    return dc_rate;
+}
+
+
+
diff --git a/bsp/ls1bdev/libraries/ls1b_clock.h b/bsp/ls1bdev/libraries/ls1b_clock.h
new file mode 100644
index 0000000000..bd22986e4c
--- /dev/null
+++ b/bsp/ls1bdev/libraries/ls1b_clock.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-06     Ϊ       first version
+ */
+
+
+#ifndef __LOONGSON_CLOCK_H
+#define __LOONGSON_CLOCK_H
+
+
+
+/*
+ * ȡPLLƵ
+ * @ret PLLƵ
+ */
+unsigned long clk_get_pll_rate(void);
+
+
+/*
+ * ȡCPUƵ
+ * @ret CPUƵ
+ */
+unsigned long clk_get_cpu_rate(void);
+
+
+
+/*
+ * ȡDDRƵ
+ * @ret DDRƵ
+ */
+unsigned long clk_get_ddr_rate(void);
+
+
+/*
+ * ȡAPBƵ
+ * @ret APBƵ
+ */
+unsigned long clk_get_apb_rate(void);
+
+
+/*
+ * ȡDCƵ
+ * @ret DCƵ
+ */
+unsigned long clk_get_dc_rate(void);
+
+
+
+#endif
+
diff --git a/bsp/ls1bdev/libraries/ls1b_gpio.c b/bsp/ls1bdev/libraries/ls1b_gpio.c
new file mode 100644
index 0000000000..2e100e7122
--- /dev/null
+++ b/bsp/ls1bdev/libraries/ls1b_gpio.c
@@ -0,0 +1,238 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-06     勤为本       first version
+ * 2021-02-02     michael5hzg@gmail.com       adapt to ls1b
+ */
+
+
+#include "ls1b_public.h"
+#include "ls1b_regs.h"
+#include "ls1b_gpio.h"
+#include "ls1b_pin.h"
+
+
+/*
+ * 获取指定gpio的CFG寄存器
+ * @gpio gpio编号
+ * @ret CFG寄存器
+ */
+volatile unsigned int *gpio_get_cfg_reg(unsigned int gpio)
+{
+    volatile unsigned int *gpio_cfgx = NULL;            // GPIO_CFGx寄存器
+    unsigned int port = GPIO_GET_PORT(gpio);
+
+    switch (port)
+    {
+        case 0:
+            gpio_cfgx = (volatile unsigned int *)LS1B_GPIO_CFG0;
+            break;
+
+        case 1:
+            gpio_cfgx = (volatile unsigned int *)LS1B_GPIO_CFG1;
+            break;
+        default:
+            gpio_cfgx = NULL;
+            break;
+    }
+
+    return gpio_cfgx;
+}
+
+
+/*
+ * 获取指定gpio的EN寄存器
+ * @gpio gpio编号
+ * @ret EN寄存器
+ */
+volatile unsigned int *gpio_get_en_reg(unsigned int gpio)
+{
+    volatile unsigned int *gpio_enx = NULL;         // GPIO_ENx寄存器
+    unsigned int port = GPIO_GET_PORT(gpio);
+    
+    switch (port)
+    {
+        case 0:
+            gpio_enx = (volatile unsigned int *)LS1B_GPIO_EN0;
+            break;
+
+        case 1:
+            gpio_enx = (volatile unsigned int *)LS1B_GPIO_EN1;
+            break;
+        default:
+            gpio_enx    = NULL;
+            return gpio_enx;
+    }
+
+    return gpio_enx;
+}
+
+/*
+ * gpio初始化
+ * @gpio gpio引脚，取值范围[0, 127]
+ * @mode gpio的工作模式(输入、输出)
+ *
+ * 例: 将gpio50初始化为输出
+ * gpio_init(50, gpio_mode_output);
+ */
+void gpio_init(unsigned int gpio, gpio_mode_t mode)
+{
+    volatile unsigned int *gpio_enx = NULL;        // GPIO_ENx寄存器
+    unsigned int pin = GPIO_GET_PIN(gpio);
+
+    // 将pin设为普通GPIO
+    pin_set_purpose(gpio, PIN_PURPOSE_GPIO);
+
+    // 设置gpio工作模式(输入、输出)
+    gpio_enx  = gpio_get_en_reg(gpio);
+    if (gpio_mode_output == mode)       // 输出
+    {
+        reg_clr_one_bit(gpio_enx, pin);
+    }
+    else                                // 输入
+    {
+        reg_set_one_bit(gpio_enx, pin);
+    }
+
+    return ;
+}
+
+
+/*
+ * 在指定gpio输出高电平或低电平
+ * @gpio gpio引脚，取值范围[0, 127]
+ * @level 电平值
+ *
+ * 例: 在gpio50上输出低电平
+ * gpio_set(50, gpio_level_low);
+ */
+void gpio_set(unsigned int gpio, gpio_level_t level)
+{
+    volatile unsigned int *gpio_outx = NULL;       // GPIO_OUTx寄存器
+    unsigned int port   = GPIO_GET_PORT(gpio);
+    unsigned int pin    = GPIO_GET_PIN(gpio);
+
+    // 获取寄存器地址
+    switch (port)
+    {
+        case 0:
+            gpio_outx = (volatile unsigned int *)LS1B_GPIO_OUT0;
+            break;
+
+        case 1:
+            gpio_outx = (volatile unsigned int *)LS1B_GPIO_OUT1;
+            break;
+        default:        // 正确的程序不应该走到这里，直接返回
+            return ;
+    }
+
+    // 输出
+    if (gpio_level_low == level)
+    {
+        reg_clr_one_bit(gpio_outx, pin);
+    }
+    else
+    {
+        reg_set_one_bit(gpio_outx, pin);
+    }
+
+    return ;
+}
+
+
+/*
+ * 读取指定gpio引脚的值
+ * @gpio gpio引脚，取值范围[0,127]
+ *
+ * 例: 读取gpio50引脚上的值
+ * gpio_level_t level;
+ * level = gpio_get(50);
+ */
+unsigned int gpio_get(unsigned int gpio)
+{
+    volatile unsigned int *gpio_inx = NULL;        // GPIO_INx寄存器
+    unsigned int port   = GPIO_GET_PORT(gpio);
+    unsigned int pin    = GPIO_GET_PIN(gpio);
+
+    // 获取寄存器地址
+    switch (port)
+    {
+        case 0:
+            gpio_inx = (volatile unsigned int *)LS1B_GPIO_IN0;
+            break;
+
+        case 1:
+            gpio_inx = (volatile unsigned int *)LS1B_GPIO_IN1;
+            break;
+        default:        // 正常的流程不应该走到这里，直接返回
+            return 0;
+    }
+
+    // 读取
+    return reg_get_bit(gpio_inx, pin);
+}
+
+
+/**
+ * 设置中断类型
+ * @gpio gpio引脚
+ * @type 触发中断的条件。高电平触发、低电平触发、上升沿触发 or 下降沿触发
+ */
+void gpio_set_irq_type(unsigned int gpio, gpio_irq_type_t type)
+{
+    volatile unsigned int *int_pol = NULL;     // 中断极性选择寄存器
+    volatile unsigned int *int_edge = NULL;    // 中断边沿选择寄存器
+    unsigned int port = GPIO_GET_PORT(gpio);
+    unsigned int pin  = GPIO_GET_PIN(gpio);
+
+    // 获取寄存器地址
+    switch (port)
+    {
+        case 0:     // GPIO[31:0]
+            int_pol     = (volatile unsigned int *)LS1B_INT2_POL;
+            int_edge    = (volatile unsigned int *)LS1B_INT2_EDGE;
+            break;
+
+        case 1:     // GPIO[63:32]
+            int_pol     = (volatile unsigned int *)LS1B_INT3_POL;
+            int_edge    = (volatile unsigned int *)LS1B_INT3_EDGE;
+            break;
+
+    }
+
+    // 设置中断类型
+    switch (type)
+    {
+        case IRQ_TYPE_EDGE_RISING:
+            *int_pol    |= (1 << pin);
+            *int_edge   |= (1 << pin);
+            break;
+
+        case IRQ_TYPE_EDGE_FALLING:
+            *int_pol    &= ~(1 << pin);
+            *int_edge   |= (1 << pin);
+            break;
+
+        case IRQ_TYPE_LEVEL_HIGH:
+            *int_pol    |= (1 << pin);
+            *int_edge   &= ~(1 << pin);
+            break;
+
+        case IRQ_TYPE_LEVEL_LOW:
+            *int_pol    &= ~(1 << pin);
+            *int_edge   &= ~(1 << pin);
+            break;
+
+        default:
+            break;
+    }
+
+    return ;
+}
+
+
+    
diff --git a/bsp/ls1bdev/libraries/ls1b_gpio.h b/bsp/ls1bdev/libraries/ls1b_gpio.h
new file mode 100644
index 0000000000..cfbe148020
--- /dev/null
+++ b/bsp/ls1bdev/libraries/ls1b_gpio.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-06     勤为本       first version
+ */
+
+
+#ifndef __LOONGSON_GPIO_H
+#define __LOONGSON_GPIO_H
+
+
+
+// 龙芯1c的gpio是按照0,1,2,3,4...这样的顺序编号的，
+// 但在操作寄存器的时候，又是按照每32个一组来分的
+// 这里利用这个特性，将每组的32个gpio叫做一个"port"，每个gpio在每组中的索引叫"pin"
+// port = gpio / 32
+// pin  = gpio % 32
+// 例如GPIO50，port=1,pin=18
+#define GPIO_GET_PORT(gpio)                 ((gpio) / 32)
+#define GPIO_GET_PIN(gpio)                  ((gpio) % 32)
+
+
+// gpio的工作模式--输入、输出
+typedef enum{
+    gpio_mode_output = 0,       // 输出
+    gpio_mode_input = 1         // 输入
+}gpio_mode_t;
+
+
+//  gpio高低电平值
+typedef enum{
+    gpio_level_low = 0,         // 低电平
+    gpio_level_high = 1         // 高电平
+}gpio_level_t;
+
+
+typedef enum {
+    // 上升沿触发
+	IRQ_TYPE_EDGE_RISING	= 0x00000001,
+	// 下降沿触发
+	IRQ_TYPE_EDGE_FALLING	= 0x00000002,
+	IRQ_TYPE_EDGE_BOTH	= (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
+	// 高电平触发
+	IRQ_TYPE_LEVEL_HIGH	= 0x00000004,
+	// 低电平触发
+	IRQ_TYPE_LEVEL_LOW	= 0x00000008,
+	IRQ_TYPE_LEVEL_MASK	= (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),	
+}gpio_irq_type_t;
+
+
+
+/*
+ * 获取指定gpio的CFG寄存器
+ * @gpio gpio编号
+ * @ret CFG寄存器
+ */
+volatile unsigned int *gpio_get_cfg_reg(unsigned int gpio);
+
+/*
+ * gpio初始化
+ * @gpio gpio引脚，取值范围[0, 127]
+ * @mode gpio的工作模式(输入、输出)
+ *
+ * 例: 将gpio50初始化为输出
+ * gpio_init(50, gpio_mode_output);
+ */
+void gpio_init(unsigned int gpio, gpio_mode_t mode);
+
+
+/*
+ * 在指定gpio输出高电平或低电平
+ * @gpio gpio引脚，取值范围[0, 127]
+ * @level 电平值
+ *
+ * 例: 在gpio50上输出低电平
+ * gpio_set(50, gpio_level_low);
+ */
+void gpio_set(unsigned int gpio, gpio_level_t level);
+
+
+
+/*
+ * 读取指定gpio引脚的值
+ * @gpio gpio引脚，取值范围[0,127]
+ *
+ * 例: 读取gpio50引脚上的值
+ * gpio_level_t level;
+ * level = gpio_get(50);
+ */
+unsigned int gpio_get(unsigned int gpio);
+
+
+
+/**
+ * 设置中断类型
+ * @gpio gpio引脚
+ * @type 触发中断的条件。高电平触发、低电平触发、上升沿触发 or 下降沿触发
+ */
+void gpio_set_irq_type(unsigned int gpio, gpio_irq_type_t type);
+
+
+
+#endif
+
diff --git a/bsp/ls1bdev/libraries/ls1b_pin.c b/bsp/ls1bdev/libraries/ls1b_pin.c
new file mode 100644
index 0000000000..58d9e7e46c
--- /dev/null
+++ b/bsp/ls1bdev/libraries/ls1b_pin.c
@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-06     勤为本       first version
+ * 2021-02-02     michael5hzg@gmail.com       adapt to ls1b
+ */
+
+// 引脚功能(普通gpio，pwm，复用等)相关接口
+
+
+#include "ls1b_public.h"
+#include "ls1b_regs.h"
+#include "ls1b_gpio.h"
+#include "ls1b_pin.h"
+
+
+/*
+ * 把指定pin设置为指定用途(普通gpio，非gpio)
+ * @gpio gpio引脚编号
+ * @purpose 用途
+ */
+void pin_set_purpose(unsigned int gpio, pin_purpose_t purpose)
+{
+    volatile unsigned int *gpio_cfgx;           // GPIO_CFGx寄存器
+    unsigned int pin = GPIO_GET_PIN(gpio);
+
+    gpio_cfgx = gpio_get_cfg_reg(gpio);
+    if (PIN_PURPOSE_GPIO == purpose)            // 引脚用作普通gpio
+    {
+        reg_set_one_bit(gpio_cfgx, pin);
+    }
+    else                                        // 引脚用作其它功能(非gpio)
+    {
+        reg_clr_one_bit(gpio_cfgx, pin);
+    }
+
+    return ;
+}
+
+
+
+/*
+ * 设置指定pin为第n复用
+ * @gpio gpio编号
+ * @remap 第n复用
+ */
+void pin_set_remap(unsigned int gpio, pin_remap_t remap)
+{
+    volatile unsigned int *reg = NULL;          // 复用寄存器
+    unsigned int port = GPIO_GET_PORT(gpio);
+    unsigned int pin  = GPIO_GET_PIN(gpio);
+    int i;
+
+    /*指定全部pin复用为0*/
+    for (i = 0; i <= 4; i++)
+    {
+        reg = (volatile unsigned int *)((LS1B_CBUS_FIRST0) + ((port) * 0x04) + ((i) * 0x10));
+        // 置0
+        reg_clr_one_bit(reg, pin);
+    }
+
+    if (remap == PIN_REMAP_DEFAULT) return;
+
+    switch (port)
+    {
+    case 0:
+        switch (remap)
+        {
+        case PIN_REMAP_FIRST:
+            reg = (volatile unsigned int *)LS1B_CBUS_FIRST0;
+            break;
+        case PIN_REMAP_SECOND:
+            reg = (volatile unsigned int *)LS1B_CBUS_SECOND0;
+            break;
+        case PIN_REMAP_THIRD:
+            reg = (volatile unsigned int *)LS1B_CBUS_THIRD0;
+            break;
+        case PIN_REMAP_FOURTH:
+            reg = (volatile unsigned int *)LS1B_CBUS_FOURTH0;
+            break;
+        case PIN_REMAP_FIFTH:
+            reg = (volatile unsigned int *)LS1B_CBUS_FIFTH0;
+            break;
+        }
+        break;
+
+    case 1:
+        switch (remap)
+        {
+        case PIN_REMAP_FIRST:
+            reg = (volatile unsigned int *)LS1B_CBUS_FIRST1;
+            break;
+        case PIN_REMAP_SECOND:
+            reg = (volatile unsigned int *)LS1B_CBUS_SECOND1;
+            break;
+        case PIN_REMAP_THIRD:
+            reg = (volatile unsigned int *)LS1B_CBUS_THIRD1;
+            break;
+        case PIN_REMAP_FOURTH:
+            reg = (volatile unsigned int *)LS1B_CBUS_FOURTH1;
+            break;
+        case PIN_REMAP_FIFTH:
+            reg = (volatile unsigned int *)LS1B_CBUS_FIFTH1;
+            break;
+        }
+        break;
+
+    case 2:
+        switch (remap)
+        {
+        case PIN_REMAP_FIRST:
+            reg = (volatile unsigned int *)LS1B_CBUS_FIRST2;
+            break;
+        case PIN_REMAP_SECOND:
+            reg = (volatile unsigned int *)LS1B_CBUS_SECOND2;
+            break;
+        case PIN_REMAP_THIRD:
+            reg = (volatile unsigned int *)LS1B_CBUS_THIRD2;
+            break;
+        case PIN_REMAP_FOURTH:
+            reg = (volatile unsigned int *)LS1B_CBUS_FOURTH2;
+            break;
+        case PIN_REMAP_FIFTH:
+            reg = (volatile unsigned int *)LS1B_CBUS_FIFTH2;
+            break;
+        }
+        break;
+
+    case 3:
+        switch (remap)
+        {
+        case PIN_REMAP_FIRST:
+            reg = (volatile unsigned int *)LS1B_CBUS_FIRST3;
+            break;
+        case PIN_REMAP_SECOND:
+            reg = (volatile unsigned int *)LS1B_CBUS_SECOND3;
+            break;
+        case PIN_REMAP_THIRD:
+            reg = (volatile unsigned int *)LS1B_CBUS_THIRD3;
+            break;
+        case PIN_REMAP_FOURTH:
+            reg = (volatile unsigned int *)LS1B_CBUS_FOURTH3;
+            break;
+        case PIN_REMAP_FIFTH:
+            reg = (volatile unsigned int *)LS1B_CBUS_FIFTH3;
+            break;
+        }
+        break;
+
+    default:
+        return ;
+    }
+
+    // 置1
+    reg_set_one_bit(reg, pin);
+
+    return ;
+}
+
+
+
diff --git a/bsp/ls1bdev/libraries/ls1b_pin.h b/bsp/ls1bdev/libraries/ls1b_pin.h
new file mode 100644
index 0000000000..af63ba4187
--- /dev/null
+++ b/bsp/ls1bdev/libraries/ls1b_pin.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-06     勤为本       first version
+ */
+
+// 引脚功能(普通gpio，pwm，复用等)相关接口
+
+#ifndef __LOONGSON_PIN_H
+#define __LOONGSON_PIN_H
+
+
+// 引脚用途
+typedef enum
+{
+    PIN_PURPOSE_GPIO = 0,               // 引脚用作普通gpio
+    PIN_PURPOSE_OTHER,                  // 引脚用作其它功能(非gpio)
+}pin_purpose_t;
+
+
+// 引脚复用
+typedef enum
+{
+    PIN_REMAP_FIRST = 0,                // 第一复用
+    PIN_REMAP_SECOND,                   // 第二复用
+    PIN_REMAP_THIRD,                    // 第三复用
+    PIN_REMAP_FOURTH,                   // 第四复用
+    PIN_REMAP_FIFTH,                    // 第五复用
+    PIN_REMAP_DEFAULT,                //缺省复用
+}pin_remap_t;
+
+
+/*
+ * 把指定pin设置为指定用途(普通gpio，非gpio)
+ * @gpio gpio引脚编号
+ * @purpose 用途
+ */
+void pin_set_purpose(unsigned int gpio, pin_purpose_t purpose);
+
+
+/*
+ * 设置指定pin为第n复用
+ * @gpio gpio编号
+ * @remap 第n复用
+ */
+void pin_set_remap(unsigned int gpio, pin_remap_t remap);
+
+
+#endif
+
diff --git a/bsp/ls1bdev/libraries/ls1b_public.c b/bsp/ls1bdev/libraries/ls1b_public.c
new file mode 100644
index 0000000000..b48d59a851
--- /dev/null
+++ b/bsp/ls1bdev/libraries/ls1b_public.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-06     勤为本       first version
+ * 2021-02-02     michael5hzg@gmail.com       adapt to ls1b
+ */
+
+// 一些常用的、共用的接口
+
+/*
+ * 将指定寄存器的指定位置1
+ * @reg 寄存器地址
+ * @bit 需要置1的那一bit
+ */
+void reg_set_one_bit(volatile unsigned int *reg, unsigned int bit)
+{
+    unsigned int temp, mask;
+
+    mask = 1 << bit;
+    temp = *reg;
+    temp |= mask;
+    *reg = temp;
+
+    return ;
+}
+
+
+/*
+ * 将指定寄存器的指定位清零
+ * @reg 寄存器地址
+ * @bit 需要清零的那一bit
+ */
+void reg_clr_one_bit(volatile unsigned int *reg, unsigned int bit)
+{
+    unsigned int temp, mask;
+
+    mask = 1 << bit;
+    temp = *reg;
+    temp &= ~mask;
+    *reg = temp;
+
+    return ;
+}
+
+
+
+/*
+ * 获取指定寄存器的指定位的值
+ * @reg 寄存器地址
+ * @bit 需要读取值的那一bit
+ * @ret 指定位的值
+ */
+unsigned int reg_get_bit(volatile unsigned int *reg, unsigned int bit)
+{
+    unsigned int temp;
+
+    temp = *reg;
+    temp = (temp >> bit) & 1;
+
+    return temp;
+}
+
+
+/*
+ * 向寄存器中写入8bit(一个字节)数据
+ * @data 待写入的数据
+ * @addr 寄存器地址
+ */
+void reg_write_8(unsigned char data, volatile unsigned char *addr)
+{
+    *addr = data;
+}
+
+
+/*
+ * 从寄存器读出8bit(一个字节)数据
+ * @addr 寄存器地址
+ * @ret 读出的数据
+ */
+unsigned char reg_read_8(volatile unsigned char *addr)
+{
+    return (*addr);
+}
+
+
+/*
+ * 向寄存器中写一个32bit的数据
+ * @data 待写入的数据
+ * @addr 寄存器地址
+ */
+void reg_write_32(unsigned int data, volatile unsigned int *addr)
+{
+    *addr = data;
+}
+
+
+/*
+ * 从寄存器读出一个32bit数据
+ * @addr 寄存器地址
+ * @ret 读出的数据
+ */
+unsigned int reg_read_32(volatile unsigned int *addr)
+{
+    return (*addr);
+}
+
+
+
+/**
+ * ffs - find first bit set
+ * @x: the word to search
+ *
+ * This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+int ls1b_ffs(int x)
+{
+	int r = 1;
+
+	if (!x)
+		return 0;
+	if (!(x & 0xffff)) {
+		x >>= 16;
+		r += 16;
+	}
+	if (!(x & 0xff)) {
+		x >>= 8;
+		r += 8;
+	}
+	if (!(x & 0xf)) {
+		x >>= 4;
+		r += 4;
+	}
+	if (!(x & 3)) {
+		x >>= 2;
+		r += 2;
+	}
+	if (!(x & 1)) {
+		x >>= 1;
+		r += 1;
+	}
+	return r;
+}
+
+
+/*
+ * fls - find last (most-significant) bit set
+ * @x: the word to search
+ *
+ * This is defined the same way as ffs.
+ * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
+ */
+int ls1b_fls(int x)
+{
+    int r = 32;
+
+    if (!x)
+        return 0;
+    if (!(x & 0xffff0000u))
+    {
+        x <<= 16;
+        r -= 16;
+    }
+    if (!(x & 0xff000000u))
+    {
+        x <<= 8;
+        r -= 8;
+    }
+    if (!(x & 0xf0000000u))
+    {
+        x <<= 4;
+        r -= 4;
+    }
+    if (!(x & 0xc0000000u))
+    {
+        x <<= 2;
+        r -= 2;
+    }
+    if (!(x & 0x80000000u))
+    {
+        x <<= 1;
+        r -= 1;
+    }
+
+    return r;
+}
+
+
diff --git a/bsp/ls1bdev/libraries/ls1b_public.h b/bsp/ls1bdev/libraries/ls1b_public.h
new file mode 100644
index 0000000000..875f413062
--- /dev/null
+++ b/bsp/ls1bdev/libraries/ls1b_public.h
@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-06     勤为本       first version
+ */
+
+// 一些常用的、共用的接口
+
+#ifndef __LOONGSON_PUBLIC_H
+#define __LOONGSON_PUBLIC_H
+
+
+#include 
+
+
+// pmon提供的打印函数，见main()函数
+struct callvectors {
+	int     (*open) (char *, int, int);
+	int     (*close) (int);
+	int     (*read) (int, void *, int);
+	int     (*write) (int, void *, int);
+	long long   (*lseek) (int, long long, int);
+	int     (*printf) (const char *, ...);
+	void    (*cacheflush) (void);
+	char    *(*gets) (char *);
+};
+#define	myprintf (*callvec->printf)
+#define	mygets   (*callvec->gets)
+extern struct callvectors *callvec;
+
+
+#define MIN(a, b)           ((a) > (b) ? (b) : (a))
+#define MAX(a, b)           ((a) > (b) ? (a) : (b))
+
+#define DIV_ROUND_UP(n, d)      (((n) + (d) - 1) / (d))
+
+typedef enum
+{
+    FALSE=0, 
+    TRUE=1
+}BOOL;
+
+/*
+ * 将指定寄存器的指定位置1
+ * @reg 寄存器地址
+ * @bit 需要置1的那一bit
+ */
+void reg_set_one_bit(volatile unsigned int *reg, unsigned int bit);
+
+
+/*
+ * 将指定寄存器的指定位清零
+ * @reg 寄存器地址
+ * @bit 需要清零的那一bit
+ */
+void reg_clr_one_bit(volatile unsigned int *reg, unsigned int bit);
+
+
+/*
+ * 获取指定寄存器的指定位的值
+ * @reg 寄存器地址
+ * @bit 需要读取值的那一bit
+ * @ret 指定位的值
+ */
+unsigned int reg_get_bit(volatile unsigned int *reg, unsigned int bit);
+
+
+/*
+ * 向寄存器中写入8bit(一个字节)数据
+ * @data 待写入的数据
+ * @addr 寄存器地址
+ */
+void reg_write_8(unsigned char data, volatile unsigned char *addr);
+
+
+/*
+ * 从寄存器读出8bit(一个字节)数据
+ * @addr 寄存器地址
+ * @ret 读出的数据
+ */
+unsigned char reg_read_8(volatile unsigned char *addr);
+
+
+/*
+ * 向寄存器中写一个32bit的数据
+ * @data 待写入的数据
+ * @addr 寄存器地址
+ */
+void reg_write_32(unsigned int data, volatile unsigned int *addr);
+
+
+/*
+ * 从寄存器读出一个32bit数据
+ * @addr 寄存器地址
+ * @ret 读出的数据
+ */
+unsigned int reg_read_32(volatile unsigned int *addr);
+
+
+/**
+ * ffs - find first bit set
+ * @x: the word to search
+ */
+int ls1b_ffs(int x);
+
+/*
+ * fls - find last (most-significant) bit set
+ * @x: the word to search
+ *
+ * This is defined the same way as ffs.
+ * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
+ */
+int ls1b_fls(int x);
+
+
+#endif
+
diff --git a/bsp/ls1bdev/libraries/ls1b_regs.h b/bsp/ls1bdev/libraries/ls1b_regs.h
new file mode 100644
index 0000000000..6dad9c29bb
--- /dev/null
+++ b/bsp/ls1bdev/libraries/ls1b_regs.h
@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-06     勤为本       first version
+ * 2021-02-02     michael5hzg@gmail.com       adapt to ls1b
+ */
+
+// 龙芯1b外设寄存器
+
+
+#ifndef __LOONGSON_LS1B_REGS_H
+#define __LOONGSON_LS1B_REGS_H
+
+
+
+
+// 时钟相关寄存器地址
+#define LS1B_START_FREQ                     (0xbfe78030)
+#define LS1B_CLK_DIV_PARAM                  (0xbfe78034)
+
+
+// gpio相关寄存器地址
+#define LS1B_GPIO_CFG0                      (0xbfd010c0)
+#define LS1B_GPIO_EN0                       (0xbfd010d0)
+#define LS1B_GPIO_IN0                       (0xbfd010e0)
+#define LS1B_GPIO_OUT0                      (0xbfd010f0)
+
+#define LS1B_GPIO_CFG1                      (0xbfd010c4)
+#define LS1B_GPIO_EN1                       (0xbfd010d4)
+#define LS1B_GPIO_IN1                       (0xbfd010e4)
+#define LS1B_GPIO_OUT1                      (0xbfd010f4)
+
+
+
+// 复用相关寄存器
+#define LS1B_CBUS_FIRST0                    (0xbfd011c0)
+#define LS1B_CBUS_SECOND0                   (0xbfd011d0)
+#define LS1B_CBUS_THIRD0                    (0xbfd011e0)
+#define LS1B_CBUS_FOURTH0                   (0xbfd011f0)
+#define LS1B_CBUS_FIFTH0                    (0xbfd01200)
+
+#define LS1B_CBUS_FIRST1                    (0xbfd011c4)
+#define LS1B_CBUS_SECOND1                   (0xbfd011d4)
+#define LS1B_CBUS_THIRD1                    (0xbfd011e4)
+#define LS1B_CBUS_FOURTH1                   (0xbfd011f4)
+#define LS1B_CBUS_FIFTH1                    (0xbfd01204)
+
+#define LS1B_CBUS_FIRST2                    (0xbfd011c8)
+#define LS1B_CBUS_SECOND2                   (0xbfd011d8)
+#define LS1B_CBUS_THIRD2                    (0xbfd011e8)
+#define LS1B_CBUS_FOURTH2                   (0xbfd011f8)
+#define LS1B_CBUS_FIFTH2                    (0xbfd01208)
+
+#define LS1B_CBUS_FIRST3                    (0xbfd011cc)
+#define LS1B_CBUS_SECOND3                   (0xbfd011dc)
+#define LS1B_CBUS_THIRD3                    (0xbfd011ec)
+#define LS1B_CBUS_FOURTH3                   (0xbfd011fc)
+#define LS1B_CBUS_FIFTH3                    (0xbfd0120c)
+
+
+// PWM寄存器偏移
+#define LS1B_PWM_CNTR                       (0x0)
+#define LS1B_PWM_HRC                        (0x4)
+#define LS1B_PWM_LRC                        (0x8)
+#define LS1B_PWM_CTRL                       (0xC)
+// PWM基地址
+#define LS1B_REG_BASE_PWM0                  (0xbfe5c000)
+#define LS1B_REG_BASE_PWM1                  (0xbfe5c010)
+#define LS1B_REG_BASE_PWM2                  (0xbfe5c020)
+#define LS1B_REG_BASE_PWM3                  (0xbfe5c030)
+
+//CAN基地址
+#define  LS1B_REG_BASE_CAN0				    (0xbfe50000)
+#define  LS1B_REG_BASE_CAN1					(0xbfe54000)
+
+// 中断配置寄存器
+#define LS1B_INT0_SR                        (0xbfd01040)
+#define LS1B_INT0_EN                        (0xbfd01044)
+#define LS1B_INT0_SET                       (0xbfd01048)
+#define LS1B_INT0_CLR                       (0xbfd0104c)
+#define LS1B_INT0_POL                       (0xbfd01050)
+#define LS1B_INT0_EDGE                      (0xbfd01054)
+
+#define LS1B_INT1_SR                        (0xbfd01058)
+#define LS1B_INT1_EN                        (0xbfd0105c)
+#define LS1B_INT1_SET                       (0xbfd01060)
+#define LS1B_INT1_CLR                       (0xbfd01064)
+#define LS1B_INT1_POL                       (0xbfd01068)
+#define LS1B_INT1_EDGE                      (0xbfd0106c)
+
+#define LS1B_INT2_SR                        (0xbfd01070)
+#define LS1B_INT2_EN                        (0xbfd01074)
+#define LS1B_INT2_SET                       (0xbfd01078)
+#define LS1B_INT2_CLR                       (0xbfd0107c)
+#define LS1B_INT2_POL                       (0xbfd01080)
+#define LS1B_INT2_EDGE                      (0xbfd01084)
+
+#define LS1B_INT3_SR                        (0xbfd01088)
+#define LS1B_INT3_EN                        (0xbfd0108c)
+#define LS1B_INT3_SET                       (0xbfd01090)
+#define LS1B_INT3_CLR                       (0xbfd01094)
+#define LS1B_INT3_POL                       (0xbfd01098)
+#define LS1B_INT3_EDGE                      (0xbfd0109c)
+
+#define LS1B_INT4_SR                        (0xbfd010a0)
+#define LS1B_INT4_EN                        (0xbfd010a4)
+#define LS1B_INT4_SET                       (0xbfd010a8)
+#define LS1B_INT4_CLR                       (0xbfd010ac)
+#define LS1B_INT4_POL                       (0xbfd010b0)
+#define LS1B_INT4_EDGE                      (0xbfd010b4)
+
+
+// I2C寄存器
+#define LS1B_I2C0_BASE                      (0xbfe58000)
+#define LS1B_I2C1_BASE                      (0xbfe68000)
+#define LS1B_I2C2_BASE                      (0xbfe70000)
+
+
+// SPI寄存器
+#define LS1B_SPI0_BASE                      (0xbfe80000)
+#define LS1B_SPI1_BASE                      (0xbfec0000)
+
+
+// 串口寄存器
+#define LS1B_UART00_BASE                    (0xbfe40000)
+#define LS1B_UART01_BASE                    (0xbfe41000)
+#define LS1B_UART1_BASE                     (0xbfe44000)
+#define LS1B_UART2_BASE                     (0xbfe48000)
+#define LS1B_UART3_BASE                     (0xbfe4c000)
+#define LS1B_UART4_BASE                     (0xbfe6c000)
+#define LS1B_UART5_BASE                     (0xbfe7c000)
+#define LS1B_UART6_BASE                     (0xbfe41000)
+#define LS1B_UART7_BASE                     (0xbfe42000)
+#define LS1B_UART8_BASE                     (0xbfe43000)
+#define LS1B_UART9_BASE                     (0xbfe45000)
+#define LS1B_UART10_BASE                    (0xbfe46000)
+#define LS1B_UART11_BASE                    (0xbfe47000)
+
+//RTC寄存器
+#define LS1B_RTC_BASE                       (0xbfe64024)
+
+
+#endif
+
diff --git a/bsp/ls1bdev/libraries/ls1b_uart.c b/bsp/ls1bdev/libraries/ls1b_uart.c
new file mode 100644
index 0000000000..73d88438f5
--- /dev/null
+++ b/bsp/ls1bdev/libraries/ls1b_uart.c
@@ -0,0 +1,251 @@
+ /*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-02-02   michael5hzg@gmail.com   adapt to ls1b
+ */
+// 串口相关源码
+
+#include 
+#include 
+#include "ls1b_public.h"
+#include "ls1b_regs.h"
+#include "ls1b_pin.h"
+#include "ls1b_uart.h"
+#include "ls1b_clock.h"
+#include "ls1b.h"
+
+
+// 串口线路状态寄存器的位域
+#define LS1B_UART_LSR_TE                (1 << 6)
+#define LS1B_UART_LSR_TFE               (1 << 5)
+
+
+// 打印缓存的大小
+#define LS1B_UART_PRINT_BUF_SIZE        (256)
+
+
+// 调试串口信息
+ls1b_uart_info_t debug_uart_info = {0};
+
+
+/*
+ * 获取指定串口模块的基地址
+ * @UARTx 串口编号
+ * @ret 基地址
+ */
+void *uart_get_base(ls1b_uart_t UARTx)
+{
+    void *base = NULL;
+
+    switch (UARTx)
+    {
+        case LS1B_UART00:
+            base = (void *)LS1B_UART00_BASE;
+            break;
+        case LS1B_UART01:
+            base = (void *)LS1B_UART01_BASE;
+            break;
+
+        case LS1B_UART1:
+            base = (void *)LS1B_UART1_BASE;
+            break;
+        
+        case LS1B_UART2:
+            base = (void *)LS1B_UART2_BASE;
+            break;
+
+        case LS1B_UART3:
+            base = (void *)LS1B_UART3_BASE;
+            break;
+        
+        case LS1B_UART4:
+            base = (void *)LS1B_UART4_BASE;
+            break;
+
+        case LS1B_UART5:
+            base = (void *)LS1B_UART5_BASE;
+            break;
+
+        case LS1B_UART6:
+            base = (void *)LS1B_UART6_BASE;
+            break;
+
+        case LS1B_UART7:
+            base = (void *)LS1B_UART7_BASE;
+            break;
+
+        case LS1B_UART8:
+            base = (void *)LS1B_UART8_BASE;
+            break;
+
+        case LS1B_UART9:
+            base = (void *)LS1B_UART9_BASE;
+            break;
+
+        case LS1B_UART10:
+            base = (void *)LS1B_UART10_BASE;
+            break;
+
+        case LS1B_UART11:
+            base = (void *)LS1B_UART11_BASE;
+            break;
+
+        default:
+            break;
+    }
+
+    return base;
+}
+
+
+/*
+ * 初始化指定的串口模块
+ * @uart_info_p 串口模块信息
+ */
+void uart_init(ls1b_uart_info_t *uart_info_p)
+{
+    void *uart_base = uart_get_base(uart_info_p->UARTx);
+    unsigned long baudrate_div = 0;
+
+    // 禁止所有中断
+    reg_write_8(0,      uart_base + LS1B_UART_IER_OFFSET);
+
+    // 接收FIFO的中断申请Trigger为14字节，清空发送和接收FIFO，并复位
+    reg_write_8(0xc3,   uart_base + LS1B_UART_FCR_OFFSET);
+
+    // 设置波特率
+    reg_write_8(0x80,   uart_base + LS1B_UART_LCR_OFFSET);
+    baudrate_div = clk_get_apb_rate() / 16 / uart_info_p->baudrate;
+    reg_write_8((baudrate_div >> 8) & 0xff, uart_base + LS1B_UART_MSB_OFFSET);
+    reg_write_8(baudrate_div & 0xff,        uart_base + LS1B_UART_LSB_OFFSET);
+
+    // 8个数据位，1个停止位，无校验
+    reg_write_8(0x03,   uart_base + LS1B_UART_LCR_OFFSET);
+
+    // 使能接收中断
+    if (TRUE == uart_info_p->rx_enable)
+    {
+        reg_write_8(IER_IRxE|IER_ILE , uart_base + LS1B_UART_IER_OFFSET);
+    }
+
+    return ;
+}
+
+
+/*
+ * 判断FIFO是否为空
+ * @uartx 串口号
+ * @ret TRUE or FALSE
+ */
+BOOL uart_is_transmit_empty(ls1b_uart_t uartx)
+{
+    void *uart_base = uart_get_base(uartx);
+    unsigned char status = reg_read_8(uart_base + LS1B_UART_LSR_OFFSET);
+
+    if (status & (LS1B_UART_LSR_TE | LS1B_UART_LSR_TFE))
+    {
+        return TRUE;
+    }
+    else
+    {
+        return FALSE;
+    }
+}
+
+
+/*
+ * 发送一个字节
+ * @uartx 串口号
+ * @ch 待发送的字符串
+ */
+void uart_putc(ls1b_uart_t uartx, unsigned char ch)
+{
+    void *uart_base = uart_get_base(uartx);
+    
+    // 等待
+    while (FALSE == uart_is_transmit_empty(uartx))
+        ;
+
+    // 发送
+    reg_write_8(ch, uart_base + LS1B_UART_DAT_OFFSET);
+
+    return ;
+}
+
+
+/*
+ * 打印一个字符串到指定串口
+ * @uartx 串口号
+ * @str 待打印的字符串
+ */
+void uart_print(ls1b_uart_t uartx, const char *str)
+{
+    while ('\0' != *str)                // 判断是否为字符串结束符
+    {
+        uart_putc(uartx, *str);   // 发送一个字符
+        str++;
+    }
+
+    return ;
+}
+
+
+/*
+ * 初始化串口2
+ */
+void uart2_init(void)
+{
+    unsigned int tx_gpio = 37;
+    unsigned int rx_gpio = 36;
+
+    // 设置复用
+    pin_set_remap(tx_gpio, PIN_REMAP_SECOND);
+    pin_set_remap(rx_gpio, PIN_REMAP_SECOND);
+    
+    // 初始化相关寄存器
+    debug_uart_info.UARTx = LS1B_UART2;
+    debug_uart_info.baudrate = 115200;
+    debug_uart_info.rx_enable = FALSE;  // 调试串口只需要打印(发送)功能，不需要接收功能
+    uart_init(&debug_uart_info);
+
+    return ;
+}
+
+
+/*
+ * 在串口2上打印字符串
+ * @str 待打印的字符串
+ */
+void uart2_print(const char *str)
+{
+    uart_print(LS1B_UART2, str);
+    return ;
+}
+
+
+/*
+ * 在调试串口打印字符串
+ * @str 待打印的字符串
+ */
+void uart_debug_print(const char *str)
+{
+    uart_print(debug_uart_info.UARTx, str);
+    return ;
+}
+
+
+/*
+ * 在调试串口打印一个字符
+ * @ch 待打印的字符
+ */
+void uart_debug_putc(unsigned char ch)
+{
+    uart_putc(debug_uart_info.UARTx, ch);
+    return ;
+}
+
+
diff --git a/bsp/ls1bdev/libraries/ls1b_uart.h b/bsp/ls1bdev/libraries/ls1b_uart.h
new file mode 100644
index 0000000000..88ee2793ad
--- /dev/null
+++ b/bsp/ls1bdev/libraries/ls1b_uart.h
@@ -0,0 +1,181 @@
+ /*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-02-02   michael5hzg@gmail.com	adapt to ls1b
+ */
+// 串口相关头文件
+
+
+#ifndef __LOONGSON_UART_H
+#define __LOONGSON_UART_H
+
+
+#include "ls1b_public.h"
+
+
+// 串口各寄存器相对基地址的偏移
+#define LS1B_UART_DAT_OFFSET            (0)
+#define LS1B_UART_IER_OFFSET            (1)
+#define LS1B_UART_IIR_OFFSET            (2)
+#define LS1B_UART_FCR_OFFSET            (2)
+#define LS1B_UART_LCR_OFFSET            (3)
+#define LS1B_UART_MCR_OFFSET            (4)
+#define LS1B_UART_LSR_OFFSET            (5)
+#define LS1B_UART_MSR_OFFSET            (6)
+
+#define LS1B_UART_LSB_OFFSET            (0)     // 分频锁存器1
+#define LS1B_UART_MSB_OFFSET            (1)     // 分频锁存器2
+
+/* interrupt enable register */
+#define	IER_IRxE	0x1	/* 接收有效数据中断使能 */
+#define	IER_ITxE	0x2	/* 传输保存寄存器为空中断使能 */
+#define	IER_ILE	    0x4	/* 接收器线路状态中断使能 */
+#define	IER_IME	    0x8	/* Modem状态中断使能 */
+
+/* interrupt identification register */
+#define	IIR_IMASK	0xf	/* mask */
+#define	IIR_RXTOUT	0xc	/* receive timeout */
+#define	IIR_RLS		0x6	/* receive line status */
+#define	IIR_RXRDY	0x4	/* receive ready */
+#define	IIR_TXRDY	0x2	/* transmit ready */
+#define	IIR_NOPEND	0x1	/* nothing */
+#define	IIR_MLSC	0x0	/* modem status */
+#define	IIR_FIFO_MASK	0xc0	/* set if FIFOs are enabled */
+
+/* fifo control register */
+#define	FIFO_ENABLE		0x01	/* enable fifo */
+#define	FIFO_RCV_RST	0x02	/* reset receive fifo */
+#define	FIFO_XMT_RST	0x04	/* reset transmit fifo */
+#define	FIFO_DMA_MODE	0x08	/* enable dma mode */
+#define	FIFO_TRIGGER_1	0x00	/* trigger at 1 char */
+#define	FIFO_TRIGGER_4	0x40	/* trigger at 4 chars */
+#define	FIFO_TRIGGER_8	0x80	/* trigger at 8 chars */
+#define	FIFO_TRIGGER_14	0xc0	/* trigger at 14 chars */
+
+// 线路控制寄存器
+/* character format control register */
+#define	CFCR_DLAB	0x80	/* divisor latch */
+#define	CFCR_SBREAK	0x40	/* send break */
+#define	CFCR_PZERO	0x30	/* zero parity */
+#define	CFCR_PONE	0x20	/* one parity */
+#define	CFCR_PEVEN	0x10	/* even parity */
+#define	CFCR_PODD	0x00	/* odd parity */
+#define	CFCR_PENAB	0x08	/* parity enable */
+#define	CFCR_STOPB	0x04	/* 2 stop bits */
+#define	CFCR_8BITS	0x03	/* 8 data bits */
+#define	CFCR_7BITS	0x02	/* 7 data bits */
+#define	CFCR_6BITS	0x01	/* 6 data bits */
+#define	CFCR_5BITS	0x00	/* 5 data bits */
+
+/* modem control register */
+#define	MCR_LOOPBACK	0x10	/* loopback */
+#define	MCR_IENABLE	0x08	/* output 2 = int enable */
+#define	MCR_DRS		0x04	/* output 1 = xxx */
+#define	MCR_RTS		0x02	/* enable RTS */
+#define	MCR_DTR		0x01	/* enable DTR */
+
+/* line status register */
+#define	LSR_RCV_FIFO	0x80	/* error in receive fifo */
+#define	LSR_TSRE	0x40	/* transmitter empty */
+#define	LSR_TXRDY	0x20	/* transmitter ready */
+#define	LSR_BI		0x10	/* break detected */
+#define	LSR_FE		0x08	/* framing error */
+#define	LSR_PE		0x04	/* parity error */
+#define	LSR_OE		0x02	/* overrun error */
+#define	LSR_RXRDY	0x01	/* receiver ready */
+#define	LSR_RCV_MASK	0x1f
+
+
+// 串口模块编号
+typedef enum
+{
+    LS1B_UART00 = 0,        // 全功能串口UART0可以分为两个四线串口UART00和UART01
+    LS1B_UART01,
+    LS1B_UART1,
+    LS1B_UART2,
+    LS1B_UART3,
+    LS1B_UART4,
+    LS1B_UART5,
+    LS1B_UART6,
+    LS1B_UART7,
+    LS1B_UART8,
+    LS1B_UART9,
+    LS1B_UART10,
+    LS1B_UART11
+}ls1b_uart_t;
+
+
+// 串口信息
+typedef struct
+{
+    ls1b_uart_t UARTx;              // 串口模块编号
+    unsigned int baudrate;          // 波特率
+    BOOL rx_enable;                 // 是否需要使用串口接收数据(使能接收中断)，发送默认使能
+}ls1b_uart_info_t;
+
+
+
+/*
+ * 获取指定串口模块的基地址
+ * @UARTx 串口编号
+ * @ret 基地址
+ */
+void *uart_get_base(ls1b_uart_t UARTx);
+
+
+/*
+ * 初始化指定的串口模块
+ * @uart_info_p 串口模块信息
+ */
+void uart_init(ls1b_uart_info_t *uart_info_p);
+
+
+/*
+ * 初始化串口2
+ */
+void uart2_init(void);
+
+
+/*
+ * 在串口2上打印字符串
+ * @str 待打印的字符串
+ */
+void uart2_print(const char *str);
+
+
+/*
+ * 在调试串口打印字符串
+ * @str 待打印的字符串
+ */
+void uart_debug_print(const char *str);
+
+
+/*
+ * 在调试串口打印一个字符
+ * @ch 待打印的字符
+ */
+void uart_debug_putc(unsigned char ch);
+
+
+/*
+ * 发送一个字节
+ * @uartx 串口号
+ * @ch 待发送的字符串
+ */
+void uart_putc(ls1b_uart_t uartx, unsigned char ch);
+
+
+/*
+ * 打印一个字符串到指定串口
+ * @uartx 串口号
+ * @str 待打印的字符串
+ */
+void uart_print(ls1b_uart_t uartx, const char *str);
+
+
+#endif
+
diff --git a/bsp/ls1bdev/ls1b_ram.lds b/bsp/ls1bdev/ls1b_ram.lds
index 872df8ad76..a3419501c0 100644
--- a/bsp/ls1bdev/ls1b_ram.lds
+++ b/bsp/ls1bdev/ls1b_ram.lds
@@ -1,11 +1,7 @@
 /*
- * File      : ls1b_ram.lds
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2011, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -21,25 +17,25 @@ ENTRY(_start)
 SECTIONS
 {
     . = 0x80200000;
-    .text : 
+    .text :
     {
-	start = ABSOLUTE(.);
-	 *(.selfboot);
-	 *(.selfboot_data);
-	. = ALIGN(4);
-	__selfboot_end = .;
-	. = ALIGN(0x1000);
-	__ebase_entry = .;
-     	KEEP(*(.exc_vectors))
-     	__ebase_end = .;
-	 *(.start);
+    start = ABSOLUTE(.);
+     *(.selfboot);
+     *(.selfboot_data);
+    . = ALIGN(4);
+    __selfboot_end = .;
+    . = ALIGN(0x1000);
+    __ebase_entry = .;
+        KEEP(*(.exc_vectors))
+        __ebase_end = .;
+     *(.start);
          *(.text)
          *(.text.*)
          *(.rodata)
          *(.rodata.*)
          *(.rodata1)
          *(.rodata1.*)
-         
+
          /* section information for finsh shell */
          . = ALIGN(4);
          __fsymtab_start = .;
@@ -57,26 +53,26 @@ SECTIONS
           __rt_init_end = .;
          . = ALIGN(4);
     }
-    
-    .eh_frame_hdr : 
-    { 
-         *(.eh_frame_hdr) 
+
+    .eh_frame_hdr :
+    {
+         *(.eh_frame_hdr)
          *(.eh_frame_entry)
     }
     .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
 
     . = ALIGN(4);
-    .data : 
+    .data :
     {
          *(.data)
          *(.data.*)
-        
+
          *(.data1)
          *(.data1.*)
-         
+
          . = ALIGN(8);
          _gp = ABSOLUTE(.);     /* Base of small data */
-         
+
          *(.sdata)
          *(.sdata.*)
     }
@@ -90,7 +86,7 @@ SECTIONS
         _system_stack = .;
     }
 
-    .sbss : 
+    .sbss :
     {
         __bss_start = .;
         *(.sbss)
diff --git a/bsp/ls1bdev/rtconfig.h b/bsp/ls1bdev/rtconfig.h
index 882d74b4d7..aede85d795 100644
--- a/bsp/ls1bdev/rtconfig.h
+++ b/bsp/ls1bdev/rtconfig.h
@@ -10,15 +10,12 @@
 #define RT_ALIGN_SIZE 4
 #define RT_THREAD_PRIORITY_32
 #define RT_THREAD_PRIORITY_MAX 32
-#define RT_TICK_PER_SECOND 100
+#define RT_TICK_PER_SECOND 1000
 #define RT_USING_OVERFLOW_CHECK
 #define RT_USING_HOOK
 #define RT_USING_IDLE_HOOK
 #define RT_IDLE_HOOK_LIST_SIZE 4
-#define IDLE_THREAD_STACK_SIZE 256
-#define RT_USING_TIMER_SOFT
-#define RT_TIMER_THREAD_PRIO 4
-#define RT_TIMER_THREAD_STACK_SIZE 512
+#define IDLE_THREAD_STACK_SIZE 1024
 #define RT_DEBUG
 
 /* Inter-Thread communication */
@@ -40,8 +37,8 @@
 #define RT_USING_DEVICE
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 128
-#define RT_CONSOLE_DEVICE_NAME "uart"
-#define RT_VER_NUM 0x40002
+#define RT_CONSOLE_DEVICE_NAME "uart5"
+#define RT_VER_NUM 0x40003
 
 /* RT-Thread Components */
 
@@ -114,9 +111,6 @@
 /* Utilities */
 
 
-/* RT-Thread MIPS CPU */
-
-
 /* RT-Thread online packages */
 
 /* IoT - internet of things */
@@ -157,7 +151,9 @@
 /* samples: kernel and components samples */
 
 #define SOC_LS1B
-#define RT_USING_UART0
+#define RT_MEM_SIZE 256
+#define RT_OSC_CLK 25000000
+#define RT_USING_UART5
 #define RT_UART_RX_BUFFER_SIZE 64
 
 #endif
diff --git a/bsp/ls1bdev/rtconfig.py b/bsp/ls1bdev/rtconfig.py
index a2c78a926a..0d76e27348 100644
--- a/bsp/ls1bdev/rtconfig.py
+++ b/bsp/ls1bdev/rtconfig.py
@@ -36,7 +36,7 @@ OBJDUMP = PREFIX + 'objdump'
 OBJCPY = PREFIX + 'objcopy'
 READELF = PREFIX + 'readelf'
 
-DEVICE = ' -mips32r2'
+DEVICE = ' -mips32 -msoft-float -mfp32'
 CFLAGS = DEVICE + ' -EL -G0 -mno-abicalls -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -fomit-frame-pointer'
 AFLAGS = ' -c' + DEVICE + ' -EL -fno-pic -fno-builtin -mno-abicalls -x assembler-with-cpp'
 LFLAGS = DEVICE + ' -nostartfiles -EL -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T ls1b_ram.lds'
diff --git a/bsp/ls1cdev/.config b/bsp/ls1cdev/.config
index abde28ef80..28414b5870 100644
--- a/bsp/ls1cdev/.config
+++ b/bsp/ls1cdev/.config
@@ -7,6 +7,8 @@
 # RT-Thread Kernel
 #
 CONFIG_RT_NAME_MAX=10
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
 CONFIG_RT_ALIGN_SIZE=8
 # CONFIG_RT_THREAD_PRIORITY_8 is not set
 CONFIG_RT_THREAD_PRIORITY_32=y
@@ -15,6 +17,7 @@ CONFIG_RT_THREAD_PRIORITY_MAX=32
 CONFIG_RT_TICK_PER_SECOND=1000
 CONFIG_RT_USING_OVERFLOW_CHECK=y
 CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
 CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
 CONFIG_IDLE_THREAD_STACK_SIZE=1024
 # CONFIG_RT_USING_TIMER_SOFT is not set
@@ -50,6 +53,7 @@ CONFIG_RT_USING_MEMHEAP=y
 CONFIG_RT_USING_SMALL_MEM=y
 # CONFIG_RT_USING_SLAB is not set
 # CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
 # CONFIG_RT_USING_MEMTRACE is not set
 CONFIG_RT_USING_HEAP=y
 
@@ -62,6 +66,9 @@ CONFIG_RT_USING_INTERRUPT_INFO=y
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart2"
+CONFIG_RT_VER_NUM=0x40003
+# CONFIG_RT_USING_CPU_FFS is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
 
 #
 # RT-Thread Components
@@ -116,12 +123,17 @@ CONFIG_RT_DFS_ELM_USE_LFN_0=y
 # CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
 # CONFIG_RT_DFS_ELM_USE_LFN_3 is not set
 CONFIG_RT_DFS_ELM_USE_LFN=0
+CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
+CONFIG_RT_DFS_ELM_LFN_UNICODE=0
 CONFIG_RT_DFS_ELM_MAX_LFN=64
 CONFIG_RT_DFS_ELM_DRIVES=2
 CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
 # CONFIG_RT_DFS_ELM_USE_ERASE is not set
 CONFIG_RT_DFS_ELM_REENTRANT=y
-# CONFIG_RT_USING_DFS_DEVFS is not set
+CONFIG_RT_USING_DFS_DEVFS=y
 # CONFIG_RT_USING_DFS_ROMFS is not set
 # CONFIG_RT_USING_DFS_RAMFS is not set
 # CONFIG_RT_USING_DFS_UFFS is not set
@@ -133,35 +145,41 @@ CONFIG_RT_DFS_ELM_REENTRANT=y
 #
 CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
 CONFIG_RT_USING_SERIAL=y
 CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
 CONFIG_RT_USING_CAN=y
 # CONFIG_RT_CAN_USING_HDR is not set
 # CONFIG_RT_USING_HWTIMER is not set
 # CONFIG_RT_USING_CPUTIME is not set
 CONFIG_RT_USING_I2C=y
+# CONFIG_RT_I2C_DEBUG is not set
 CONFIG_RT_USING_I2C_BITOPS=y
+# CONFIG_RT_I2C_BITOPS_DEBUG is not set
+# CONFIG_RT_USING_PHY is not set
 CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
 # CONFIG_RT_USING_PWM is not set
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
-# CONFIG_RT_USING_MTD is not set
 # CONFIG_RT_USING_PM is not set
 # CONFIG_RT_USING_RTC is not set
 # CONFIG_RT_USING_SDIO is not set
 CONFIG_RT_USING_SPI=y
+# CONFIG_RT_USING_QSPI is not set
 CONFIG_RT_USING_SPI_MSD=y
 # CONFIG_RT_USING_SFUD is not set
-# CONFIG_RT_USING_W25QXX is not set
-# CONFIG_RT_USING_GD is not set
 # CONFIG_RT_USING_ENC28J60 is not set
 # CONFIG_RT_USING_SPI_WIFI is not set
 # CONFIG_RT_USING_WDT is not set
 # CONFIG_RT_USING_AUDIO is not set
-
-#
-# Using WiFi
-#
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
 # CONFIG_RT_USING_WIFI is not set
 
 #
@@ -175,7 +193,12 @@ CONFIG_RT_USING_SPI_MSD=y
 #
 CONFIG_RT_USING_LIBC=y
 CONFIG_RT_USING_PTHREADS=y
-# CONFIG_RT_USING_POSIX is not set
+CONFIG_PTHREAD_NUM_MAX=8
+CONFIG_RT_USING_POSIX=y
+# CONFIG_RT_USING_POSIX_MMAP is not set
+# CONFIG_RT_USING_POSIX_TERMIOS is not set
+# CONFIG_RT_USING_POSIX_GETLINE is not set
+# CONFIG_RT_USING_POSIX_AIO is not set
 # CONFIG_RT_USING_MODULE is not set
 
 #
@@ -187,13 +210,20 @@ CONFIG_RT_USING_PTHREADS=y
 #
 # CONFIG_RT_USING_SAL is not set
 
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+CONFIG_NETDEV_USING_PING=y
+
 #
 # light weight TCP/IP stack
 #
 CONFIG_RT_USING_LWIP=y
 CONFIG_RT_USING_LWIP141=y
 # CONFIG_RT_USING_LWIP202 is not set
-# CONFIG_RT_USING_LWIP210 is not set
+# CONFIG_RT_USING_LWIP212 is not set
+CONFIG_RT_LWIP_MEM_ALIGNMENT=4
 CONFIG_RT_LWIP_IGMP=y
 CONFIG_RT_LWIP_ICMP=y
 # CONFIG_RT_LWIP_SNMP is not set
@@ -210,7 +240,7 @@ CONFIG_RT_LWIP_GWADDR="192.168.1.1"
 CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
 CONFIG_RT_LWIP_UDP=y
 CONFIG_RT_LWIP_TCP=y
-# CONFIG_RT_LWIP_RAW is not set
+CONFIG_RT_LWIP_RAW=y
 # CONFIG_RT_LWIP_PPP is not set
 CONFIG_RT_MEMP_NUM_NETCONN=8
 CONFIG_RT_LWIP_PBUF_NUM=4
@@ -230,20 +260,19 @@ CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=512
 CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
 # CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
 CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
+CONFIG_LWIP_NETIF_LINK_CALLBACK=1
 CONFIG_SO_REUSE=1
 CONFIG_LWIP_SO_RCVTIMEO=1
 CONFIG_LWIP_SO_SNDTIMEO=1
 CONFIG_LWIP_SO_RCVBUF=1
+CONFIG_LWIP_SO_LINGER=0
 # CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
 CONFIG_LWIP_NETIF_LOOPBACK=0
 # CONFIG_RT_LWIP_STATS is not set
+# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set
+CONFIG_RT_LWIP_USING_PING=y
 # CONFIG_RT_LWIP_DEBUG is not set
 
-#
-# Modbus master and slave stack
-#
-# CONFIG_RT_USING_MODBUS is not set
-
 #
 # AT commands
 #
@@ -258,39 +287,39 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 #
 # Utilities
 #
-# CONFIG_RT_USING_LOGTRACE is not set
 # CONFIG_RT_USING_RYM is not set
 # CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+
+#
+# RT-Thread MIPS CPU
+#
+# CONFIG_RT_USING_FPU is not set
 
 #
 # RT-Thread online packages
 #
 
-#
-# system packages
-#
-
-#
-# RT-Thread GUI Engine
-#
-# CONFIG_PKG_USING_GUIENGINE is not set
-# CONFIG_PKG_USING_LWEXT4 is not set
-# CONFIG_PKG_USING_PARTITION is not set
-# CONFIG_PKG_USING_SQLITE is not set
-# CONFIG_PKG_USING_RTI is not set
-
 #
 # IoT - internet of things
 #
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
 # CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
 # CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
 # CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
 # CONFIG_PKG_USING_WEBTERMINAL is not set
 # CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
 # CONFIG_PKG_USING_LJSON is not set
 # CONFIG_PKG_USING_EZXML is not set
 # CONFIG_PKG_USING_NANOPB is not set
-# CONFIG_PKG_USING_GAGENT_CLOUD is not set
 
 #
 # Wi-Fi
@@ -305,9 +334,51 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 # Wiced WiFi
 #
 # CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
 # CONFIG_PKG_USING_COAP is not set
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
 
 #
 # security packages
@@ -315,10 +386,13 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 # CONFIG_PKG_USING_MBEDTLS is not set
 # CONFIG_PKG_USING_libsodium is not set
 # CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
 
 #
 # language packages
 #
+# CONFIG_PKG_USING_LUA is not set
 # CONFIG_PKG_USING_JERRYSCRIPT is not set
 # CONFIG_PKG_USING_MICROPYTHON is not set
 
@@ -326,35 +400,208 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 # multimedia packages
 #
 # CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
 
 #
 # tools packages
 #
 # CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
 # CONFIG_PKG_USING_EASYLOGGER is not set
 # CONFIG_PKG_USING_SYSTEMVIEW is not set
-# CONFIG_PKG_USING_IPERF is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RT_PRINTF is not set
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
 
 #
 # miscellaneous packages
 #
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
 # CONFIG_PKG_USING_FASTLZ is not set
 # CONFIG_PKG_USING_MINILZO is not set
 # CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
 # CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
 
 #
-# example package: hello
+# samples: kernel and components samples
 #
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
 # CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+
+#
+# games: games run on RT-Thread console
+#
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+CONFIG_SOC_LS1C300=y
+CONFIG_RT_LS1C_OPENLOONGSON=y
+# CONFIG_RT_LS1C_BAICAIBOARD is not set
 # CONFIG_RT_USING_SELF_BOOT is not set
 CONFIG_RT_USING_UART2=y
+CONFIG_RT_USING_UART1=y
+# CONFIG_RT_USING_UART3 is not set
 CONFIG_RT_UART_RX_BUFFER_SIZE=64
 CONFIG_RT_USING_GMAC_INT_MODE=y
-# CONFIG_RT_USING_FPU is not set
 # CONFIG_RT_USING_SPI0 is not set
 # CONFIG_RT_USING_SPI1 is not set
 CONFIG_RT_USING_I2C1=y
 CONFIG_RT_USING_I2C2=y
 CONFIG_USING_BXCAN0=y
 CONFIG_USING_BXCAN1=y
+CONFIG_NO_TOUCH=y
+# CONFIG_TINA_USING_TOUCH is not set
diff --git a/bsp/ls1cdev/drivers/drv_spi.c b/bsp/ls1cdev/drivers/drv_spi.c
index 3cc2212850..25b30e07ca 100644
--- a/bsp/ls1cdev/drivers/drv_spi.c
+++ b/bsp/ls1cdev/drivers/drv_spi.c
@@ -1,21 +1,7 @@
 /*
- * File      : drv_spi.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/ls1cdev/ls1c_ram.lds b/bsp/ls1cdev/ls1c_ram.lds
index 38aabfe012..aced32b90b 100644
--- a/bsp/ls1cdev/ls1c_ram.lds
+++ b/bsp/ls1cdev/ls1c_ram.lds
@@ -1,11 +1,7 @@
 /*
- * File      : ls1c_ram.lds
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2011, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -22,25 +18,25 @@ ENTRY(_start)
 SECTIONS
 {
     . = ALIGN(4);
-    .text : 
+    .text :
     {
-	start = ABSOLUTE(.);
-	 *(.selfboot);
-	 *(.selfboot_data);
-	. = ALIGN(4);
-	__selfboot_end = .;
-	. = ALIGN(0x1000);
-	__ebase_entry = .;
-     	KEEP(*(.exc_vectors))
-     	__ebase_end = .;
-	 *(.start);
+    start = ABSOLUTE(.);
+     *(.selfboot);
+     *(.selfboot_data);
+    . = ALIGN(4);
+    __selfboot_end = .;
+    . = ALIGN(0x1000);
+    __ebase_entry = .;
+        KEEP(*(.exc_vectors))
+        __ebase_end = .;
+     *(.start);
          *(.text)
          *(.text.*)
          *(.rodata)
          *(.rodata.*)
          *(.rodata1)
          *(.rodata1.*)
-         
+
          /* section information for finsh shell */
          . = ALIGN(4);
          __fsymtab_start = .;
@@ -58,26 +54,26 @@ SECTIONS
           __rt_init_end = .;
          . = ALIGN(4);
     }
-    
-    .eh_frame_hdr : 
-    { 
-         *(.eh_frame_hdr) 
+
+    .eh_frame_hdr :
+    {
+         *(.eh_frame_hdr)
          *(.eh_frame_entry)
     }
     .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
 
     . = ALIGN(4);
-    .data : 
+    .data :
     {
          *(.data)
          *(.data.*)
-        
+
          *(.data1)
          *(.data1.*)
-         
+
          . = ALIGN(8);
          _gp = ABSOLUTE(.);     /* Base of small data */
-         
+
          *(.sdata)
          *(.sdata.*)
     }
@@ -91,7 +87,7 @@ SECTIONS
         _system_stack = .;
     }
 
-    .sbss : 
+    .sbss :
     {
         __bss_start = .;
         *(.sbss)
diff --git a/bsp/ls1cdev/rtconfig.h b/bsp/ls1cdev/rtconfig.h
index 55899c04e1..34be0a928c 100644
--- a/bsp/ls1cdev/rtconfig.h
+++ b/bsp/ls1cdev/rtconfig.h
@@ -41,7 +41,7 @@
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "uart2"
-#define RT_VER_NUM 0x40002
+#define RT_VER_NUM 0x40003
 
 /* RT-Thread Components */
 
@@ -75,6 +75,21 @@
 #define DFS_FILESYSTEMS_MAX 2
 #define DFS_FILESYSTEM_TYPES_MAX 2
 #define DFS_FD_MAX 4
+#define RT_USING_DFS_ELMFAT
+
+/* elm-chan's FatFs, Generic FAT Filesystem Module */
+
+#define RT_DFS_ELM_CODE_PAGE 936
+#define RT_DFS_ELM_WORD_ACCESS
+#define RT_DFS_ELM_USE_LFN_0
+#define RT_DFS_ELM_USE_LFN 0
+#define RT_DFS_ELM_LFN_UNICODE_0
+#define RT_DFS_ELM_LFN_UNICODE 0
+#define RT_DFS_ELM_MAX_LFN 64
+#define RT_DFS_ELM_DRIVES 2
+#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
+#define RT_DFS_ELM_REENTRANT
+#define RT_USING_DFS_DEVFS
 
 /* Device Drivers */
 
@@ -98,6 +113,7 @@
 #define RT_USING_LIBC
 #define RT_USING_PTHREADS
 #define PTHREAD_NUM_MAX 8
+#define RT_USING_POSIX
 
 /* Network */
 
@@ -106,9 +122,51 @@
 
 /* Network interface device */
 
+#define NETDEV_USING_PING
 
 /* light weight TCP/IP stack */
 
+#define RT_USING_LWIP
+#define RT_USING_LWIP141
+#define RT_LWIP_MEM_ALIGNMENT 4
+#define RT_LWIP_IGMP
+#define RT_LWIP_ICMP
+#define RT_LWIP_DNS
+#define RT_LWIP_DHCP
+#define IP_SOF_BROADCAST 1
+#define IP_SOF_BROADCAST_RECV 1
+
+/* Static IPv4 Address */
+
+#define RT_LWIP_IPADDR "192.168.1.254"
+#define RT_LWIP_GWADDR "192.168.1.1"
+#define RT_LWIP_MSKADDR "255.255.255.0"
+#define RT_LWIP_UDP
+#define RT_LWIP_TCP
+#define RT_LWIP_RAW
+#define RT_MEMP_NUM_NETCONN 8
+#define RT_LWIP_PBUF_NUM 4
+#define RT_LWIP_RAW_PCB_NUM 4
+#define RT_LWIP_UDP_PCB_NUM 4
+#define RT_LWIP_TCP_PCB_NUM 3
+#define RT_LWIP_TCP_SEG_NUM 40
+#define RT_LWIP_TCP_SND_BUF 4096
+#define RT_LWIP_TCP_WND 2048
+#define RT_LWIP_TCPTHREAD_PRIORITY 12
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
+#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
+#define RT_LWIP_ETHTHREAD_PRIORITY 14
+#define RT_LWIP_ETHTHREAD_STACKSIZE 512
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
+#define LWIP_NETIF_STATUS_CALLBACK 1
+#define LWIP_NETIF_LINK_CALLBACK 1
+#define SO_REUSE 1
+#define LWIP_SO_RCVTIMEO 1
+#define LWIP_SO_SNDTIMEO 1
+#define LWIP_SO_RCVBUF 1
+#define LWIP_SO_LINGER 0
+#define LWIP_NETIF_LOOPBACK 0
+#define RT_LWIP_USING_PING
 
 /* AT commands */
 
@@ -153,6 +211,9 @@
 /* system packages */
 
 
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
 /* peripheral libraries and drivers */
 
 
@@ -161,16 +222,19 @@
 
 /* samples: kernel and components samples */
 
+
+/* games: games run on RT-Thread console */
+
 #define SOC_LS1C300
-#define RT_LS1C_BAICAIBOARD
-#define RT_USING_SELF_BOOT
-#define RT_SELF_BOOT_DEBUG
+#define RT_LS1C_OPENLOONGSON
 #define RT_USING_UART2
 #define RT_USING_UART1
 #define RT_UART_RX_BUFFER_SIZE 64
 #define RT_USING_GMAC_INT_MODE
 #define RT_USING_I2C1
 #define RT_USING_I2C2
+#define USING_BXCAN0
+#define USING_BXCAN1
 #define NO_TOUCH
 
 #endif
diff --git a/bsp/m16c62p/applications/application.c b/bsp/m16c62p/applications/application.c
index d345cfc425..35eb423193 100644
--- a/bsp/m16c62p/applications/application.c
+++ b/bsp/m16c62p/applications/application.c
@@ -1,11 +1,7 @@
 /*
- * File      : application.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -48,7 +44,7 @@ int rt_application_init(void)
                             sizeof(led_stack),
                             RT_THREAD_PRIORITY_MAX / 2,
                             32);
-    
+
     if (result == RT_EOK)
         rt_thread_startup(&led);
 
diff --git a/bsp/m16c62p/applications/startup.c b/bsp/m16c62p/applications/startup.c
index 1802ecadee..149e530892 100644
--- a/bsp/m16c62p/applications/startup.c
+++ b/bsp/m16c62p/applications/startup.c
@@ -1,11 +1,7 @@
 /*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -40,61 +36,61 @@ extern unsigned char user_ram_end;
  */
 void rtthread_startup(void)
 {
-	/* init hardware interrupt */
-	rt_hw_interrupt_init();
-        
-	/* init board */
-	rt_hw_board_init();
+    /* init hardware interrupt */
+    rt_hw_interrupt_init();
+
+    /* init board */
+    rt_hw_board_init();
+
+    /* show version */
+    rt_show_version();
+
+    /* init timer system */
+    rt_system_timer_init();
 
-	/* show version */
-	rt_show_version();
-        
-	/* init timer system */
-	rt_system_timer_init();
-    
 #ifdef RT_USING_HEAP
 #ifdef __ICCM16C__
-	rt_system_heap_init(__segment_begin("DATA16_HEAP"), __segment_end("DATA16_HEAP"));
+    rt_system_heap_init(__segment_begin("DATA16_HEAP"), __segment_end("DATA16_HEAP"));
 #elif (defined (__GNUC__))
-	rt_system_heap_init((void*)&user_ram_end, (void*)M16C62P_SRAM_END);
+    rt_system_heap_init((void*)&user_ram_end, (void*)M16C62P_SRAM_END);
 #endif
 #endif
 
-	/* init scheduler system */
-	rt_system_scheduler_init();
+    /* init scheduler system */
+    rt_system_scheduler_init();
 
-	/* init application */
-	rt_application_init();
+    /* init application */
+    rt_application_init();
 
 #ifdef RT_USING_FINSH
-	/* init finsh */
-	finsh_system_init();
-	finsh_set_device("uart0");
+    /* init finsh */
+    finsh_system_init();
+    finsh_set_device("uart0");
 #endif
 
-	/* init timer thread */
-	rt_system_timer_thread_init();
+    /* init timer thread */
+    rt_system_timer_thread_init();
 
-	/* init idle thread */
-	rt_thread_idle_init();
-    
-	/* start scheduler */
-	rt_system_scheduler_start();
-    
-	/* never reach here */
-	return ;
+    /* init idle thread */
+    rt_thread_idle_init();
+
+    /* start scheduler */
+    rt_system_scheduler_start();
+
+    /* never reach here */
+    return ;
 }
 
 int main(void)
 {
-	/* disable interrupt first */
-	rt_hw_interrupt_disable();
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
 
-	/* init system setting */
-	system_init();
-    
-	/* startup RT-Thread RTOS */
-	rtthread_startup();
+    /* init system setting */
+    system_init();
 
-	return 0;
+    /* startup RT-Thread RTOS */
+    rtthread_startup();
+
+    return 0;
 }
diff --git a/bsp/m16c62p/drivers/board.c b/bsp/m16c62p/drivers/board.c
index 69c581ffa7..9771e97fed 100644
--- a/bsp/m16c62p/drivers/board.c
+++ b/bsp/m16c62p/drivers/board.c
@@ -1,11 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -27,8 +23,8 @@
 void rt_hw_board_init(void)
 {
 #ifdef RT_USING_UART0
-	rt_hw_uart_init();
-	rt_console_set_device("uart0");
+    rt_hw_uart_init();
+    rt_console_set_device("uart0");
 #endif
 
     rt_kprintf("\r\n\r\nSystemInit......\r\n");
diff --git a/bsp/m16c62p/drivers/board.h b/bsp/m16c62p/drivers/board.h
index e3a4a604fe..05aa63832b 100644
--- a/bsp/m16c62p/drivers/board.h
+++ b/bsp/m16c62p/drivers/board.h
@@ -1,11 +1,7 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/m16c62p/drivers/bsp.c b/bsp/m16c62p/drivers/bsp.c
index e03fa499e0..29732cb636 100644
--- a/bsp/m16c62p/drivers/bsp.c
+++ b/bsp/m16c62p/drivers/bsp.c
@@ -1,11 +1,7 @@
 /*
- * File      : bsp.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -39,31 +35,31 @@ void led_off(void)
 
 static void mcu_init(void)
 {
-	volatile  rt_uint32_t  count;
-	                                                            /* Configure clock for divide by 1 mode                     */
-	PRCR.BYTE      |= 0x01;                                     /* Enable access to clock registers           PRCR.PRC0 = 1 */
-	CM1.BYTE             = 0x20;                                     /* Set CM16, CM17 divide ratio to 1:                        */
-									                            /*  ... main clock on in high drive no PLL                  */
-	CM0.BYTE            &= ~0x40;                                    /* Set divide ratio to 1                      CM0.CM06  = 0 */			
+    volatile  rt_uint32_t  count;
+                                                                /* Configure clock for divide by 1 mode                     */
+    PRCR.BYTE      |= 0x01;                                     /* Enable access to clock registers           PRCR.PRC0 = 1 */
+    CM1.BYTE             = 0x20;                                     /* Set CM16, CM17 divide ratio to 1:                        */
+                                                                /*  ... main clock on in high drive no PLL                  */
+    CM0.BYTE            &= ~0x40;                                    /* Set divide ratio to 1                      CM0.CM06  = 0 */
 
                                                                 /* Configure main PLL                                       */
-	PRCR.BYTE           |= 0x02;                                     /* Allow writing to processor mode register   PRCR.PRC0 = 1 */
-	PM2.BYTE            |= 0x01;                                     /* Set SFR access to 2 wait, which is required for          */
-   									                            /*  ... operation greater than 16 MHz         PM2.PM20  = 1 */
-	PRCR.BYTE           &= ~0x02;                                    /* Protect processor mode register            PRCR.PRC0 = 0 */
-	PLC0.BYTE            = 0x91;                                     /* Enable and turn on PLL                                   */
+    PRCR.BYTE           |= 0x02;                                     /* Allow writing to processor mode register   PRCR.PRC0 = 1 */
+    PM2.BYTE            |= 0x01;                                     /* Set SFR access to 2 wait, which is required for          */
+                                                                /*  ... operation greater than 16 MHz         PM2.PM20  = 1 */
+    PRCR.BYTE           &= ~0x02;                                    /* Protect processor mode register            PRCR.PRC0 = 0 */
+    PLC0.BYTE            = 0x91;                                     /* Enable and turn on PLL                                   */
 
     count           = 20000;                                    /* Delay while PLL stabilizes                               */
-	while (count > 0) {
+    while (count > 0) {
         count--;
     }
 
     CM1.BYTE            |= 0x02;                                     /* Switch to PLL                              CM1.CM11  = 1 */
     PRCR.BYTE           &= ~0x01;                                    /* Protect clock control register             PRCR.PRC0 = 0 */
-	
-	PRCR.BYTE           |= 0x02;                                     /* Allow writing to processor mode register   PRCR.PRC0 = 1 */
-	PM1.BYTE            |= 0x01;                                     /* Enable data flash area                     PM1.PM10  = 1 */
-	PRCR.BYTE           &= ~0x02;                                    /* Protect processor mode register            PRCR.PRC0 = 0 */
+
+    PRCR.BYTE           |= 0x02;                                     /* Allow writing to processor mode register   PRCR.PRC0 = 1 */
+    PM1.BYTE            |= 0x01;                                     /* Enable data flash area                     PM1.PM10  = 1 */
+    PRCR.BYTE           &= ~0x02;                                    /* Protect processor mode register            PRCR.PRC0 = 0 */
 }
 
 /*
@@ -89,15 +85,15 @@ static void mcu_init(void)
 
 static void timer_tick_init(void)
 {
-	                                                            /* Set timer to timer mode                                  */
+                                                                /* Set timer to timer mode                                  */
                                                                 /* Set count source as PLL clock / 8 (f8)                   */
-	TB0MR.BYTE = 0x40;
+    TB0MR.BYTE = 0x40;
                                                                 /* Assign timer value and reload value                      */
-	TB0        = (CPU_CLK_FREQ / 8) / RT_TICK_PER_SECOND;
-	                                                            /* Set timer B channel 0 interrupt level = 7                */
-	                                                            /* Clear interrupt request                                  */
+    TB0        = (CPU_CLK_FREQ / 8) / RT_TICK_PER_SECOND;
+                                                                /* Set timer B channel 0 interrupt level = 7                */
+                                                                /* Clear interrupt request                                  */
     TB0IC.BYTE = 0x07;
-	TABSR.BYTE |= 0x20;                             /* Start timer                                              */
+    TABSR.BYTE |= 0x20;                             /* Start timer                                              */
 }
 
 void system_init(void)
diff --git a/bsp/m16c62p/drivers/bsp.h b/bsp/m16c62p/drivers/bsp.h
index 9e353d6ecb..e77e0dc7fe 100644
--- a/bsp/m16c62p/drivers/bsp.h
+++ b/bsp/m16c62p/drivers/bsp.h
@@ -1,11 +1,7 @@
 /*
- * File      : bsp.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/m16c62p/drivers/interrupts_gcc.S b/bsp/m16c62p/drivers/interrupts_gcc.S
index 5c1f4cb1a8..03ff885b51 100644
--- a/bsp/m16c62p/drivers/interrupts_gcc.S
+++ b/bsp/m16c62p/drivers/interrupts_gcc.S
@@ -1,11 +1,7 @@
 /*
- * File      : interrupt.s34
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -15,23 +11,23 @@
  * Toolchain : IAR's EW for M16C v3.401
  */
 
- 	.text
+    .text
 
-	.globl	_rt_hw_context_switch_interrupt_do
-	.type	_rt_hw_context_switch_interrupt_do, #function
+    .globl  _rt_hw_context_switch_interrupt_do
+    .type   _rt_hw_context_switch_interrupt_do, #function
 _rt_hw_context_switch_interrupt_do:
     MOV.B   #0, _rt_thread_switch_interrupt_flag
     MOV.W   _rt_interrupt_from_thread, A0
     STC     ISP, [A0]
-    
+
     MOV.W   _rt_interrupt_to_thread, A0
     LDC     [A0], ISP
     POPM    R0,R1,R2,R3,A0,A1,SB,FB             ; Restore all processor registers from the new task's stack
     REIT
-    
- 	.text
-	.globl	_rt_hw_timer_handler
-	.type	_rt_hw_timer_handler, #function
+
+    .text
+    .globl  _rt_hw_timer_handler
+    .type   _rt_hw_timer_handler, #function
 _rt_hw_timer_handler:
     PUSHM   R0,R1,R2,R3,A0,A1,SB,FB             ; Save current task's registers
     jsr.a     _rt_interrupt_enter
@@ -40,22 +36,22 @@ _rt_hw_timer_handler:
 
     CMP.B   #1, _rt_thread_switch_interrupt_flag
     JEQ     _rt_hw_context_switch_interrupt_do
-    
+
     POPM    R0,R1,R2,R3,A0,A1,SB,FB             ; Restore current task's registers
     REIT                                        ; Return from interrup
 
- 	.text
-	.globl	_rt_hw_uart0_receive_handler
-	.type	_rt_hw_uart0_receive_handler, #function
+    .text
+    .globl  _rt_hw_uart0_receive_handler
+    .type   _rt_hw_uart0_receive_handler, #function
 _rt_hw_uart0_receive_handler:
     PUSHM   R0,R1,R2,R3,A0,A1,SB,FB             ; Save current task's registers
-    jsr.a     _rt_interrupt_enter 
+    jsr.a     _rt_interrupt_enter
     jsr.a     _u0rec_handler
     jsr.a     _rt_interrupt_leave
 
     CMP.B   #1, _rt_thread_switch_interrupt_flag
     JEQ     _rt_hw_context_switch_interrupt_do
-    
+
     POPM    R0,R1,R2,R3,A0,A1,SB,FB             ; Restore current task's registers
     REIT                                        ; Return from interrup
 
diff --git a/bsp/m16c62p/drivers/interrupts_iar.asm b/bsp/m16c62p/drivers/interrupts_iar.asm
index afaaae487f..5f2688e068 100644
--- a/bsp/m16c62p/drivers/interrupts_iar.asm
+++ b/bsp/m16c62p/drivers/interrupts_iar.asm
@@ -1,11 +1,7 @@
 /*
- * File      : interrupt.s34
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -17,7 +13,7 @@
 
     PUBLIC  rt_hw_timer_handler
     PUBLIC  rt_hw_uart0_receive_handler
-        
+
     EXTERN  rt_thread_switch_interrupt_flag
     EXTERN  rt_interrupt_from_thread
     EXTERN  rt_interrupt_to_thread
@@ -25,7 +21,7 @@
     EXTERN  rt_interrupt_leave
     EXTERN  rt_tick_increase
     EXTERN  u0rec_handler
-        
+
     RSEG    CSTACK
     RSEG    ISTACK
     RSEG    CODE:CODE:NOROOT(2)
@@ -34,12 +30,12 @@ rt_hw_context_switch_interrupt_do
     MOV.B   #0, rt_thread_switch_interrupt_flag
     MOV.W   rt_interrupt_from_thread, A0
     STC     ISP, [A0]
-    
+
     MOV.W   rt_interrupt_to_thread, A0
     LDC     [A0], ISP
     POPM    R0,R1,R2,R3,A0,A1,SB,FB             ; Restore all processor registers from the new task's stack
     REIT
-    
+
     .EVEN
 rt_hw_timer_handler:
     PUSHM   R0,R1,R2,R3,A0,A1,SB,FB             ; Save current task's registers
@@ -49,20 +45,20 @@ rt_hw_timer_handler:
 
     CMP.B   #1, rt_thread_switch_interrupt_flag
     JEQ     rt_hw_context_switch_interrupt_do
-    
+
     POPM    R0,R1,R2,R3,A0,A1,SB,FB             ; Restore current task's registers
     REIT                                        ; Return from interrup
 
     .EVEN
 rt_hw_uart0_receive_handler:
     PUSHM   R0,R1,R2,R3,A0,A1,SB,FB             ; Save current task's registers
-    JSR     rt_interrupt_enter 
+    JSR     rt_interrupt_enter
     JSR     u0rec_handler
     JSR     rt_interrupt_leave
 
     CMP.B   #1, rt_thread_switch_interrupt_flag
     JEQ     rt_hw_context_switch_interrupt_do
-    
+
     POPM    R0,R1,R2,R3,A0,A1,SB,FB             ; Restore current task's registers
     REIT                                        ; Return from interrup
 
diff --git a/bsp/m16c62p/drivers/uart.c b/bsp/m16c62p/drivers/uart.c
index 76cf038347..67f56b98a3 100644
--- a/bsp/m16c62p/drivers/uart.c
+++ b/bsp/m16c62p/drivers/uart.c
@@ -1,11 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -23,44 +19,44 @@
 
 struct rt_uart_m16c
 {
-	struct rt_device parent;
+    struct rt_device parent;
 
-	/* buffer for reception */
-	rt_uint8_t read_index, save_index;
-	rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
+    /* buffer for reception */
+    rt_uint8_t read_index, save_index;
+    rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
 }uart_device;
 
 void u0rec_handler(void)
 {
-	rt_ubase_t level;
-	rt_uint8_t c;
+    rt_ubase_t level;
+    rt_uint8_t c;
 
-	struct rt_uart_m16c *uart = &uart_device;
+    struct rt_uart_m16c *uart = &uart_device;
 
-	while (U0C1.BIT.RI == 0)
-		;
-	c = U0RB.BYTE.U0RBL;
+    while (U0C1.BIT.RI == 0)
+        ;
+    c = U0RB.BYTE.U0RBL;
 
-	/* Receive Data Available */
+    /* Receive Data Available */
     uart->rx_buffer[uart->save_index] = c;
 
     level = rt_hw_interrupt_disable();
-	uart->save_index ++;
+    uart->save_index ++;
     if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
         uart->save_index = 0;
     rt_hw_interrupt_enable(level);
 
-	/* invoke callback */
-	if (uart->parent.rx_indicate != RT_NULL)
-	{
-	    rt_size_t length;
-	    if (uart->read_index > uart->save_index)
+    /* invoke callback */
+    if (uart->parent.rx_indicate != RT_NULL)
+    {
+        rt_size_t length;
+        if (uart->read_index > uart->save_index)
             length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
         else
             length = uart->save_index - uart->read_index;
 
         uart->parent.rx_indicate(&uart->parent, length);
-	}
+    }
 }
 
 static rt_err_t rt_uart_init (rt_device_t dev)
@@ -69,7 +65,7 @@ static rt_err_t rt_uart_init (rt_device_t dev)
     /* set UART0 bit rate generator bit rate can be calculated by:
           bit rate = ((BRG count source / 16)/baud rate) - 1
           Baud rate is based on main crystal or PLL not CPU core clock */
-	//pclk1 = 1;   /// seleck F1SIO
+    //pclk1 = 1;   /// seleck F1SIO
     U0BRG = (unsigned char)(((CPU_CLK_FREQ/16)/BAUD_RATE)-1);   //(N+1)
 
     /* UART Transmit/Receive Control Register 2 */
@@ -143,144 +139,144 @@ static rt_err_t rt_uart_init (rt_device_t dev)
         b6      UOLCH       Data logic select bit
         b7      UOERE       Error signal output enable bit */
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
 {
-	RT_ASSERT(dev != RT_NULL);
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* Enable the UART Interrupt */
-	}
+    RT_ASSERT(dev != RT_NULL);
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* Enable the UART Interrupt */
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_uart_close(rt_device_t dev)
 {
-	RT_ASSERT(dev != RT_NULL);
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* Disable the UART Interrupt */
-	}
+    RT_ASSERT(dev != RT_NULL);
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* Disable the UART Interrupt */
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
 {
-	rt_uint8_t *ptr;
-	struct rt_uart_m16c *uart = (struct rt_uart_m16c *)dev;
-	RT_ASSERT(uart != RT_NULL);
+    rt_uint8_t *ptr;
+    struct rt_uart_m16c *uart = (struct rt_uart_m16c *)dev;
+    RT_ASSERT(uart != RT_NULL);
 
-	/* point to buffer */
-	ptr = (rt_uint8_t *)buffer;
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		while (size)
-		{
-			/* interrupt receive */
-			rt_base_t level;
+    /* point to buffer */
+    ptr = (rt_uint8_t *)buffer;
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        while (size)
+        {
+            /* interrupt receive */
+            rt_base_t level;
 
-			/* disable interrupt */
-			level = rt_hw_interrupt_disable();
-			if (uart->read_index != uart->save_index)
-			{
-				*ptr = uart->rx_buffer[uart->read_index];
+            /* disable interrupt */
+            level = rt_hw_interrupt_disable();
+            if (uart->read_index != uart->save_index)
+            {
+                *ptr = uart->rx_buffer[uart->read_index];
 
-				uart->read_index ++;
-				if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
-					uart->read_index = 0;
-			}
-			else
-			{
-				/* no data in rx buffer */
+                uart->read_index ++;
+                if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
+                    uart->read_index = 0;
+            }
+            else
+            {
+                /* no data in rx buffer */
 
-				/* enable interrupt */
-				rt_hw_interrupt_enable(level);
-				break;
-			}
+                /* enable interrupt */
+                rt_hw_interrupt_enable(level);
+                break;
+            }
 
-			/* enable interrupt */
-			rt_hw_interrupt_enable(level);
+            /* enable interrupt */
+            rt_hw_interrupt_enable(level);
 
-			ptr ++;
-			size --;
-		}
+            ptr ++;
+            size --;
+        }
 
-		return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-	}
+        return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+    }
 
-	return 0;
+    return 0;
 }
 
 static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
 {
-	char *ptr;
-	ptr = (char *)buffer;
+    char *ptr;
+    ptr = (char *)buffer;
 
-	if (dev->flag & RT_DEVICE_FLAG_STREAM)
-	{
-		/* stream mode */
-		while (size)
-		{
-			if (*ptr == '\n')
-			{
-				while (U0C1.BIT.TI == 0)
-					;
-				U0TB.BYTE.U0TBL = '\r';
-			}
+    if (dev->flag & RT_DEVICE_FLAG_STREAM)
+    {
+        /* stream mode */
+        while (size)
+        {
+            if (*ptr == '\n')
+            {
+                while (U0C1.BIT.TI == 0)
+                    ;
+                U0TB.BYTE.U0TBL = '\r';
+            }
 
-			/* THRE status, contain valid data */
-			while (U0C1.BIT.TI == 0)
-				;
-			U0TB.BYTE.U0TBL = *ptr;
-  
-			ptr ++;
-			size --;
-		}
-	}
-	else
-	{
-		while (size != 0)
-		{
-			/* THRE status, contain valid data */
-			while (U0C1.BIT.TI == 0)
-				;
-			U0TB.BYTE.U0TBL = *ptr;
-	
-			ptr ++;
-			size --;
-		}
-	}
+            /* THRE status, contain valid data */
+            while (U0C1.BIT.TI == 0)
+                ;
+            U0TB.BYTE.U0TBL = *ptr;
 
-	return (rt_size_t)ptr - (rt_size_t)buffer;
+            ptr ++;
+            size --;
+        }
+    }
+    else
+    {
+        while (size != 0)
+        {
+            /* THRE status, contain valid data */
+            while (U0C1.BIT.TI == 0)
+                ;
+            U0TB.BYTE.U0TBL = *ptr;
+
+            ptr ++;
+            size --;
+        }
+    }
+
+    return (rt_size_t)ptr - (rt_size_t)buffer;
 }
 
 void rt_hw_uart_init(void)
 {
-	struct rt_uart_m16c *uart;
+    struct rt_uart_m16c *uart;
 
-	/* get uart device */
-	uart = &uart_device;
+    /* get uart device */
+    uart = &uart_device;
 
-	/* device initialization */
-	uart->parent.type = RT_Device_Class_Char;
-	rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
-	uart->read_index = uart->save_index = 0;
+    /* device initialization */
+    uart->parent.type = RT_Device_Class_Char;
+    rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
+    uart->read_index = uart->save_index = 0;
 
-	/* device interface */
-	uart->parent.init 	    = rt_uart_init;
-	uart->parent.open 	    = rt_uart_open;
-	uart->parent.close      = rt_uart_close;
-	uart->parent.read 	    = rt_uart_read;
-	uart->parent.write      = rt_uart_write;
-	uart->parent.control    = RT_NULL;
-	uart->parent.user_data  = RT_NULL;
+    /* device interface */
+    uart->parent.init       = rt_uart_init;
+    uart->parent.open       = rt_uart_open;
+    uart->parent.close      = rt_uart_close;
+    uart->parent.read       = rt_uart_read;
+    uart->parent.write      = rt_uart_write;
+    uart->parent.control    = RT_NULL;
+    uart->parent.user_data  = RT_NULL;
 
-	rt_device_register(&uart->parent,
-		"uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
+    rt_device_register(&uart->parent,
+        "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
 }
 #endif /* end of UART */
 
diff --git a/bsp/m16c62p/drivers/vectors_iar.asm b/bsp/m16c62p/drivers/vectors_iar.asm
index a6ec8d5b7d..8a5ce3fb54 100644
--- a/bsp/m16c62p/drivers/vectors_iar.asm
+++ b/bsp/m16c62p/drivers/vectors_iar.asm
@@ -1,11 +1,7 @@
 /*
- * File      : vectors.s34
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -24,7 +20,7 @@
     EXTERN  rt_hw_timer_handler
     EXTERN  rt_hw_uart0_receive_handler
     EXTERN  os_context_switch
-    
+
     PUBLIC  RelocatableVectTbl
 
     RSEG    INTVEC:NOROOT
diff --git a/bsp/m16c62p/readme.txt b/bsp/m16c62p/readme.txt
index 70059fd48b..95939c7bd9 100644
--- a/bsp/m16c62p/readme.txt
+++ b/bsp/m16c62p/readme.txt
@@ -1,17 +1,13 @@
 /*
- * File      : readme.txt
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2011-02-17     lgnq         the first version
  */
- 
+
 Summary:
 ========
 This directory contains the source code for M16C porting to rt-thread
@@ -23,7 +19,7 @@ finsh    - a user shell, comes with rt-thread
 Where to get help:
 ==================
 In case you have questions about, problems with or contributions for
-Renesas M16C prot to rt-thread, you can send a mail to dzzxzz@gmail.com. 
+Renesas M16C prot to rt-thread, you can send a mail to dzzxzz@gmail.com.
 
 or you can post a message to the rt-thread forum
 there are two forums:
@@ -48,10 +44,10 @@ Directory Hierarchy:
                 /startup.c              - rt-thread start, include main()
             /drivers
                 /board.c                - hardware init, init uart0
-                /board.h                
+                /board.h
                 /bsp.c                  - include led_init(), mcu_init(), timer0_init()
                 /bsp.h
-                /uart.c                 - implement uart0 device 
+                /uart.c                 - implement uart0 device
                 /uart.h
                 /start_iar.asm          - assembly start of iar
                 /interrupts_iar.asm     - include time0 interrupt handler, uart0 interrupt handler
@@ -75,7 +71,7 @@ Directory Hierarchy:
                 /context_gcc.S      - rt-thread context switch, used by SCONS + gcc
                 /interrupt.c
                 /stack.c            - rt-thread stack initlization
-                
+
 Build Project:
 ==============
 there are two ways to build the renesase M16C project:
@@ -84,7 +80,7 @@ there are two ways to build the renesase M16C project:
     rebuild all
     the target file(rtt2m16c.mot) will be produced in /rt-thread/bsp/m16c62p/Debug/Exe
     you can download the rtt2m16c.mot to m16c board with E8A
-                   
+
 2,  install python, scons and IAR for m16c(recommend python2.7, scons1.3.1 and EWM16C-EV-3501.exe)
     open a windows cmd, and change directory to m16c project, like /rt-thread/bsp/m16c62p/
     #set PATH=C:\Python27\Scripts;%PATH%
diff --git a/bsp/maxim/MAX32660_EVSYS/.config b/bsp/maxim/MAX32660_EVSYS/.config
index 82e0a0d279..c2b026f742 100644
--- a/bsp/maxim/MAX32660_EVSYS/.config
+++ b/bsp/maxim/MAX32660_EVSYS/.config
@@ -14,7 +14,7 @@ CONFIG_RT_ALIGN_SIZE=4
 CONFIG_RT_THREAD_PRIORITY_32=y
 # CONFIG_RT_THREAD_PRIORITY_256 is not set
 CONFIG_RT_THREAD_PRIORITY_MAX=32
-CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_TICK_PER_SECOND=1000
 CONFIG_RT_USING_OVERFLOW_CHECK=y
 CONFIG_RT_USING_HOOK=y
 CONFIG_RT_USING_IDLE_HOOK=y
@@ -272,6 +272,7 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_PDULIB is not set
 # CONFIG_PKG_USING_BTSTACK is not set
 # CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
 
 #
 # security packages
@@ -300,6 +301,7 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_HELIX is not set
 # CONFIG_PKG_USING_AZUREGUIX is not set
 # CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_LVGL is not set
 
 #
 # tools packages
@@ -311,6 +313,8 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_RDB is not set
 # CONFIG_PKG_USING_QRCODE is not set
 # CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
+# CONFIG_PKG_USING_LOGMGR is not set
 # CONFIG_PKG_USING_ADBD is not set
 # CONFIG_PKG_USING_COREMARK is not set
 # CONFIG_PKG_USING_DHRYSTONE is not set
@@ -324,6 +328,16 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_UMCN is not set
 # CONFIG_PKG_USING_LWRB2RTT is not set
 # CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
 
 #
 # system packages
@@ -361,6 +375,13 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_UC_COMMON is not set
 # CONFIG_PKG_USING_UC_MODBUS is not set
 # CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+# CONFIG_PKG_USING_LPM is not set
 
 #
 # peripheral libraries and drivers
@@ -369,6 +390,7 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_REALTEK_AMEBA is not set
 # CONFIG_PKG_USING_SHT2X is not set
 # CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AS7341 is not set
 # CONFIG_PKG_USING_STM32_SDIO is not set
 # CONFIG_PKG_USING_ICM20608 is not set
 # CONFIG_PKG_USING_U8G2 is not set
@@ -418,7 +440,10 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_SSD1306 is not set
 # CONFIG_PKG_USING_QKEY is not set
 # CONFIG_PKG_USING_RS485 is not set
-# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
 
 #
 # miscellaneous packages
@@ -468,6 +493,9 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_TETRIS is not set
 # CONFIG_PKG_USING_LWGPS is not set
 # CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_COWSAY is not set
 
 #
 # Hardware Drivers Config
@@ -485,3 +513,4 @@ CONFIG_BSP_USING_UART1=y
 # CONFIG_BSP_UART1_RX_USING_DMA is not set
 # CONFIG_BSP_USING_SPI is not set
 # CONFIG_BSP_USING_ON_CHIP_FLASH is not set
+# CONFIG_BSP_USING_I2C is not set
diff --git a/bsp/maxim/MAX32660_EVSYS/.vscode/.cortex-debug.peripherals.state.json b/bsp/maxim/MAX32660_EVSYS/.vscode/.cortex-debug.peripherals.state.json
new file mode 100644
index 0000000000..0637a088a0
--- /dev/null
+++ b/bsp/maxim/MAX32660_EVSYS/.vscode/.cortex-debug.peripherals.state.json
@@ -0,0 +1 @@
+[]
\ No newline at end of file
diff --git a/bsp/maxim/MAX32660_EVSYS/.vscode/.cortex-debug.registers.state.json b/bsp/maxim/MAX32660_EVSYS/.vscode/.cortex-debug.registers.state.json
new file mode 100644
index 0000000000..0637a088a0
--- /dev/null
+++ b/bsp/maxim/MAX32660_EVSYS/.vscode/.cortex-debug.registers.state.json
@@ -0,0 +1 @@
+[]
\ No newline at end of file
diff --git a/bsp/maxim/MAX32660_EVSYS/.vscode/launch.json b/bsp/maxim/MAX32660_EVSYS/.vscode/launch.json
new file mode 100644
index 0000000000..138d6ae360
--- /dev/null
+++ b/bsp/maxim/MAX32660_EVSYS/.vscode/launch.json
@@ -0,0 +1,24 @@
+{
+    // 使用 IntelliSense 了解相关属性。 
+    // 悬停以查看现有属性的描述。
+    // 欲了解更多信息，请访问: https://go.microsoft.com/fwlink/?linkid=830387
+    "version": "0.2.0",
+    "configurations": [
+        {
+            "cwd": "${workspaceRoot}",
+            "executable": "rt-thread.elf",
+            "name": "Debug MAX",
+            "request": "launch",
+            "type": "cortex-debug",
+            "servertype": "openocd",
+            "interface": "swd",
+            "svdFile": "max32660.svd",
+            "configFiles": [                  
+                "interface/cmsis-dap.cfg",
+                "target/max32660.cfg"
+            ],
+            "runToMain": true,
+            //"preLaunchTask": "build"
+        },
+    ]
+}
\ No newline at end of file
diff --git a/bsp/maxim/MAX32660_EVSYS/.vscode/tasks.json b/bsp/maxim/MAX32660_EVSYS/.vscode/tasks.json
new file mode 100644
index 0000000000..278b38cf33
--- /dev/null
+++ b/bsp/maxim/MAX32660_EVSYS/.vscode/tasks.json
@@ -0,0 +1,39 @@
+{
+    // See https://go.microsoft.com/fwlink/?LinkId=733558
+    // for the documentation about the tasks.json format
+    "version": "2.0.0",
+    "tasks": [
+        {
+            "label": "build",
+            "type": "shell",
+            "command": "scons",
+            "problemMatcher": [
+                "$gcc"
+            ],
+            "presentation": {
+                "echo": true,
+                "reveal": "always",
+                "focus": true,
+                "panel": "shared",
+                "showReuseMessage": true
+            },
+            "group": {
+                "kind": "build",
+                "isDefault": true
+            }
+        },
+        {
+            "label": "clean",
+            "type": "shell",
+            "command": "scons -c",
+            "problemMatcher": [],
+            "presentation": {
+                "echo": true,
+                "reveal": "always",
+                "focus": true,
+                "panel": "shared",
+                "showReuseMessage": true
+            }
+        },
+    ]
+}
\ No newline at end of file
diff --git a/bsp/maxim/MAX32660_EVSYS/README.md b/bsp/maxim/MAX32660_EVSYS/README.md
index 90fea40042..dbe86e3902 100644
--- a/bsp/maxim/MAX32660_EVSYS/README.md
+++ b/bsp/maxim/MAX32660_EVSYS/README.md
@@ -76,9 +76,9 @@ MAX32660-EVSYS开发板常用 **板载资源** 如下：
 | UART         |     支持     | UART0, UART1(console) |
 | PWM          |              |                       |
 | SPI          |     支持     |      SPI0, SPI1       |
-| RTC          |              |                       |
+| RTC          |     支持     |      RTC              |
 | I2S          |              |                       |
-| I2C          |              |                       |
+| I2C          |     支持     |      I2C0, I2C1       |
 | TIMER        |              |                       |
 | Watchdog     |              |                       |
 
@@ -92,14 +92,42 @@ MAX32660-EVSYS开发板常用 **板载资源** 如下：
 
 2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
 
-4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。
+4. 输入`scons --target=mdk5/vsc命令重新生成工程。
 
 ## 注意事项
 
-目前仅支持keil5环境
+目前支持keil和GCC环境
+
+
+
+## FAQ
+
+###  GCC环境如何调试使用
+
+第一步，需要配置arm-none-eabi-gcc路径到系統环境变量中去或者在rtconfig.py中EXEC_PATH  修改路径
+
+第二步，添加openocd的路径，如果你安装了eclipse，添加以下路径到系统环境变量中
+
+`C:\Maxim\Toolchain\bin`
+
+完成这两部就可以用vscode打开bsp目录了。
+
+快捷键ctrl+shift+b可以执行scons编译命令
+
+快捷键F5可以进入调试命令
+
+如果需要调试之前执行build命令，在luanch.json里面打开注释
+
+```
+            //"preLaunchTask": "build"
+```
+
+
+
+
 
 ## 联系人信息
 
 维护人:
 
--  [supperthomas], 邮箱：<78900636@qq.com>
\ No newline at end of file
+-  [supperthomas], 邮箱：<78900636@qq.com>
diff --git a/bsp/maxim/MAX32660_EVSYS/board/Kconfig b/bsp/maxim/MAX32660_EVSYS/board/Kconfig
index fa4ec1d0cd..5a470ca469 100644
--- a/bsp/maxim/MAX32660_EVSYS/board/Kconfig
+++ b/bsp/maxim/MAX32660_EVSYS/board/Kconfig
@@ -66,6 +66,26 @@ menu "On-chip Peripheral Drivers"
         select PKG_USING_FAL
         bool "Enable on-chip FLASH"
         default n
+    config BSP_USING_I2C
+        bool "Enable I2C"
+        select RT_USING_I2C
+        default n
+
+        if BSP_USING_I2C
+            config BSP_USING_I2C0
+                bool "Enable I2C0 bus [SCL P0.8; SDA P0.9]"
+                default y
+            
+            config BSP_USING_I2C1
+                bool "Enable I2C1 bus [SCL P0.2; SDA P0.3]"
+                default n
+        endif
+            
+     config BSP_USING_ONCHIP_RTC
+         bool "Enable RTC"
+         select RT_USING_RTC
+         select RT_USING_LIBC
+         default n
         
 endmenu
 
diff --git a/bsp/maxim/MAX32660_EVSYS/board/board.c b/bsp/maxim/MAX32660_EVSYS/board/board.c
index fc9ff80ad2..d34b786c98 100644
--- a/bsp/maxim/MAX32660_EVSYS/board/board.c
+++ b/bsp/maxim/MAX32660_EVSYS/board/board.c
@@ -40,7 +40,7 @@ void rt_hw_systick_init(void)
 
     if (error != E_NO_ERROR)
     {
-        printf("ERROR: Ticks is not valid");
+        rt_kprintf("ERROR: Ticks is not valid");
     }
 }
 
@@ -66,3 +66,16 @@ void rt_hw_board_init(void)
 #endif
 }
 
+void rt_hw_us_delay(rt_uint32_t us)
+{
+    rt_uint32_t start, now, delta, reload, us_tick;
+    start = SysTick->VAL;
+    reload = SysTick->LOAD;
+    us_tick = SystemCoreClock / 1000000UL;
+    do
+    {
+        now = SysTick->VAL;
+        delta = start >= now ? start - now : reload + start - now;
+    }
+    while (delta < us_tick * us);
+}
diff --git a/bsp/maxim/MAX32660_EVSYS/board/linker_scripts/link.lds b/bsp/maxim/MAX32660_EVSYS/board/linker_scripts/link.lds
index 8931956648..4736a8d23f 100644
--- a/bsp/maxim/MAX32660_EVSYS/board/linker_scripts/link.lds
+++ b/bsp/maxim/MAX32660_EVSYS/board/linker_scripts/link.lds
@@ -19,6 +19,33 @@ SECTIONS {
 
         /* C++ Exception handling */
         KEEP(*(.eh_frame*))
+        
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        
+        . = ALIGN(4);
+
+        PROVIDE(__ctors_start__ = .);
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        PROVIDE(__ctors_end__ = .);
+
+        . = ALIGN(4);
+        
         _etext = .;
     } > FLASH
 
diff --git a/bsp/maxim/MAX32660_EVSYS/max32660.svd b/bsp/maxim/MAX32660_EVSYS/max32660.svd
new file mode 100644
index 0000000000..564a9c89ca
--- /dev/null
+++ b/bsp/maxim/MAX32660_EVSYS/max32660.svd
@@ -0,0 +1,10650 @@
+
+
+ Maxim Integrated
+ Maxim
+ max32660
+ ARMCM4
+ 1.0
+ MAX32660 32-bit ARM Cortex-M4 microcontroller with 96KB of system RAM and 256KB of flash memory.
+ 
+  CM4
+  r2p1
+  little
+  true
+  true
+  3
+  false
+ 
+ 8
+ 32
+ 0x20
+ read-write
+ 0x00000000
+ 0xFFFFFFFF
+ 
+  
+   BBFC
+   Battery-Backed Function Control.
+   0x40005800
+   
+    0x00
+    0x400
+    registers
+   
+   
+    
+     BBFCR0
+     Function Control Register 0.
+     0x00
+     read-write
+     
+      
+       CKPDRV
+       Hyperbus CK Pad Driver Control.
+       0
+       4
+      
+      
+       CKNPDRV
+       Hyperbus CKN Pad Driver Control.
+       4
+       4
+      
+      
+       RDSDLLEN
+       Hyperbus RDS DLL Power Up Control.
+       8
+       1
+       
+        
+         dis
+         Disabled.
+         0
+        
+        
+         en
+         Enabled.
+         1
+        
+       
+      
+     
+    
+   
+  
+
+  
+   BBSIR
+   Battery-Backed Registers.
+   0x40005400
+   
+    0x00
+    0x400
+    registers
+   
+   
+    
+     rsv0
+     RFU
+     0x00
+    
+    
+     BB_SIR2
+     System Init. Configuration Register 2.
+     0x08
+     read-only
+    
+    
+     BB_SIR3
+     System Init. Configuration Register 3.
+     0x0C
+     read-only
+    
+   
+  
+
+  
+   DMA
+   DMA Controller Fully programmable, chaining capable DMA channels.
+   0x40028000
+   32
+   
+    0x00
+    0x1000
+    registers
+   
+   
+    DMA0
+    28
+   
+   
+    DMA1
+    29
+   
+   
+    DMA2
+    30
+   
+   
+    DMA3
+    31
+   
+   
+    DMA4
+    68
+   
+   
+    DMA5
+    69
+   
+   
+    DMA6
+    70
+   
+   
+    DMA7
+    71
+   
+   
+    DMA8
+    72
+   
+   
+    DMA9
+    73
+   
+   
+    DMA10
+    74
+   
+   
+    DMA11
+    75
+   
+   
+    DMA12
+    76
+   
+   
+    DMA13
+    77
+   
+   
+    DMA14
+    78
+   
+   
+    DMA15
+    79
+   
+   
+    
+     CN
+     DMA Control Register.
+     0x000
+     
+      
+       CH0_IEN
+       Channel 0 Interrupt Enable.
+       0
+       1
+       
+        
+         dis
+         Disable.
+         0
+        
+        
+         en
+         Enable.
+         1
+        
+       
+      
+      
+       CH1_IEN
+       Channel 1 Interrupt Enable.
+       1
+       1
+      
+      
+       CH2_IEN
+       Channel 2 Interrupt Enable.
+       2
+       1
+      
+      
+       CH3_IEN
+       Channel 3 Interrupt Enable.
+       3
+       1
+      
+     
+    
+    
+     INTR
+     DMA Interrupt Register.
+     0x004
+     read-only
+     
+      
+       CH0_IPEND
+       Channel Interrupt.   To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN.
+       0
+       1
+       
+        ch_ipend_enum
+        
+         inactive
+         No interrupt is pending.
+         0
+        
+        
+         pending
+         An interrupt is pending.
+         1
+        
+       
+      
+      
+       CH1_IPEND
+       1
+       1
+      
+      
+       CH2_IPEND
+       2
+       1
+      
+      
+       CH3_IPEND
+       3
+       1
+      
+     
+    
+    
+     4
+     4
+     CH[%s]
+     DMA Channel registers.
+     dma_ch
+     0x100
+     read-write
+     
+      CFG
+      DMA Channel Configuration Register.
+      0x100
+      
+       
+        CHEN
+        Channel Enable.  This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
+        0
+        1
+        
+         
+          dis
+          Disable.
+          0
+         
+         
+          en
+          Enable.
+          1
+         
+        
+       
+       
+        RLDEN
+        Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
+        1
+        1
+        
+         
+          dis
+          Disable.
+          0
+         
+         
+          en
+          Enable.
+          1
+         
+        
+       
+       
+        PRI
+        DMA Priority.
+        2
+        2
+        
+         
+          high
+          Highest Priority.
+          0
+         
+         
+          medHigh
+          Medium High Priority.
+          1
+         
+         
+          medLow
+          Medium Low Priority.
+          2
+         
+         
+          low
+          Lowest Priority.
+          3
+         
+        
+       
+       
+        REQSEL
+        Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
+        4
+        6
+        
+         
+          MEMTOMEM
+          Memory To Memory
+          0x00
+         
+         
+          SPI0RX
+          SPI0 RX
+          0x01
+         
+         
+          SPI1RX
+          SPI1 RX
+          0x02
+         
+         
+          UART0RX
+          UART0 RX
+          0x04
+         
+         
+          UART1RX
+          UART1 RX
+          0x05
+         
+         
+          I2C0RX
+          I2C0 RX
+          0x07
+         
+         
+          I2C1RX
+          I2C1 RX
+          0x08
+         
+         
+          SPI0TX
+          SPI0 TX
+          0x21
+         
+         
+          SPI1TX
+          SPI1 TX
+          0x22
+         
+         
+          UART0TX
+          UART0 TX
+          0x24
+         
+         
+          UART1TX
+          UART1 TX
+          0x25
+         
+         
+          I2C0TX
+          I2C0 TX
+          0x27
+         
+         
+          I2C1TX
+          I2C1 TX
+          0x28
+         
+        
+       
+       
+        REQWAIT
+        Request Wait Enable.  When enabled, delay timer start until DMA request transitions from active to inactive.
+        10
+        1
+        
+         
+          dis
+          Disable.
+          0
+         
+         
+          en
+          Enable.
+          1
+         
+        
+       
+       
+        TOSEL
+        Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
+        11
+        3
+        
+         
+          to4
+          Timeout of 3 to 4 prescale clocks.
+          0
+         
+         
+          to8
+          Timeout of 7 to 8 prescale clocks.
+          1
+         
+         
+          to16
+          Timeout of 15 to 16 prescale clocks.
+          2
+         
+         
+          to32
+          Timeout of 31 to 32 prescale clocks.
+          3
+         
+         
+          to64
+          Timeout of 63 to 64 prescale clocks.
+          4
+         
+         
+          to128
+          Timeout of 127 to 128 prescale clocks.
+          5
+         
+         
+          to256
+          Timeout of 255 to 256 prescale clocks.
+          6
+         
+         
+          to512
+          Timeout of 511 to 512 prescale clocks.
+          7
+         
+        
+       
+       
+        PSSEL
+        Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
+        14
+        2
+        
+         
+          dis
+          Disable timer.
+          0
+         
+         
+          div256
+          hclk / 256.
+          1
+         
+         
+          div64k
+          hclk / 64k.
+          2
+         
+         
+          div16M
+          hclk / 16M.
+          3
+         
+        
+       
+       
+        SRCWD
+        Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
+        16
+        2
+        
+         
+          byte
+          Byte.
+          0
+         
+         
+          halfWord
+          Halfword.
+          1
+         
+         
+          word
+          Word.
+          2
+         
+        
+       
+       
+        SRCINC
+        Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
+        18
+        1
+        
+         
+          dis
+          Disable.
+          0
+         
+         
+          en
+          Enable.
+          1
+         
+        
+       
+       
+        DSTWD
+        Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
+        20
+        2
+        
+         
+          byte
+          Byte.
+          0
+         
+         
+          halfWord
+          Halfword.
+          1
+         
+         
+          word
+          Word.
+          2
+         
+        
+       
+       
+        DSTINC
+        Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
+        22
+        1
+        
+         
+          dis
+          Disable.
+          0
+         
+         
+          en
+          Enable.
+          1
+         
+        
+       
+       
+        BRST
+        Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst.  Burst size equals 1 + value stored in this field.
+        24
+        5
+       
+       
+        CHDIEN
+        Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
+        30
+        1
+        
+         
+          dis
+          Disable.
+          0
+         
+         
+          en
+          Enable.
+          1
+         
+        
+       
+       
+        CTZIEN
+        Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
+        31
+        1
+        
+         
+          dis
+          Disable.
+          0
+         
+         
+          en
+          Enable.
+          1
+         
+        
+       
+      
+     
+     
+      ST
+      DMA Channel Status Register.
+      0x104
+      
+       
+        CH_ST
+        Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware,  the DMA_CFG.CHEN bit is also cleared (if not cleared already).
+        0
+        1
+        read-only
+        
+         
+          dis
+          Disable.
+          0
+         
+         
+          en
+          Enable.
+          1
+         
+        
+       
+       
+        IPEND
+        Channel Interrupt.
+        1
+        1
+        read-only
+        
+         
+          inactive
+          No interrupt is pending.
+          0
+         
+         
+          pending
+          An interrupt is pending.
+          1
+         
+        
+       
+       
+        CTZ_ST
+        Count-to-Zero (CTZ) Status
+        2
+        1
+        oneToClear
+        
+         ctz_st_enum_rd
+         read
+         
+          noEvent
+          The event has not occurred.
+          0
+         
+         
+          occurred
+          The event has occurred.
+          1
+         
+        
+        
+         ctz_st_enum_wr
+         write
+         
+          Clear
+          Clears the interrupt flag
+          1
+         
+        
+       
+       
+        RLD_ST
+        Reload Status.
+        3
+        1
+        oneToClear
+        
+         read
+         
+          noEvent
+          The event has not occurred.
+          0
+         
+         
+          occurred
+          The event has occurred.
+          1
+         
+        
+        
+         write
+         
+          Clear
+          Clears the interrupt flag
+          1
+         
+        
+       
+       
+        BUS_ERR
+        Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
+        4
+        1
+        oneToClear
+        
+         read
+         
+          noEvent
+          The event has not occurred.
+          0
+         
+         
+          occurred
+          The event has occurred.
+          1
+         
+        
+        
+         write
+         
+          Clear
+          Clears the interrupt flag
+          1
+         
+        
+       
+       
+        TO_ST
+        Time-Out Status.
+        6
+        1
+        oneToClear
+        
+         read
+         
+          noEvent
+          The event has not occurred.
+          0
+         
+         
+          occurred
+          The event has occurred.
+          1
+         
+        
+        
+         write
+         
+          Clear
+          Clears the interrupt flag
+          1
+         
+        
+       
+      
+     
+     
+      SRC
+      Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
+      0x108
+      
+       
+        ADDR
+        0
+        32
+       
+      
+     
+     
+      DST
+      Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
+      0x10C
+      
+       
+        ADDR
+        0
+        32
+       
+      
+     
+     
+      CNT
+      DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
+      0x110
+      
+       
+        CNT
+        DMA Counter.
+        0
+        24
+       
+      
+     
+     
+      SRC_RLD
+      Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
+      0x114
+      
+       
+        SRC_RLD
+        Source Address Reload Value.
+        0
+        31
+       
+      
+     
+     
+      DST_RLD
+      Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
+      0x118
+      
+       
+        DST_RLD
+        Destination Address Reload Value.
+        0
+        31
+       
+      
+     
+     
+      CNT_RLD
+      DMA Channel Count Reload Register.
+      0x11C
+      
+       
+        CNT_RLD
+        Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
+        0
+        24
+       
+       
+        RLDEN
+        Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
+        31
+        1
+        
+         
+          dis
+          Disable.
+          0
+         
+         
+          en
+          Enable.
+          1
+         
+        
+       
+      
+     
+    
+   
+  
+
+  
+   FLC
+   Flash Memory Control.
+   FLSH_
+   0x40029000
+   
+    0x00
+    0x1000
+    registers
+   
+   
+    Flash_Controller
+    Flash Controller interrupt.
+    23
+   
+   
+    
+     ADDR
+     Flash Write Address.
+     0x00
+     
+      
+       ADDR
+       Address for next operation.
+       0
+       32
+      
+     
+    
+    
+     CLKDIV
+     Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller.
+     0x04
+     0x00000064
+     
+      
+       CLKDIV
+       Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller.
+       0
+       8
+      
+     
+    
+    
+     CN
+     Flash Control Register.
+     0x08
+     
+      
+       WR
+       Write.  This bit is automatically cleared after the operation.
+       0
+       1
+       
+        
+         complete
+         No operation/complete.
+         0
+        
+        
+         start
+         Start operation.
+         1
+        
+       
+      
+      
+       ME
+       Mass Erase.  This bit is automatically cleared after the operation.
+       1
+       1
+      
+      
+       PGE
+       Page Erase.  This bit is automatically cleared after the operation.
+       2
+       1
+      
+      
+       WDTH
+       Data Width.  This bits selects write data width.
+       4
+       1
+       
+        
+         size128
+         128-bit.
+         0
+        
+        
+         size32
+         32-bit.
+         1
+        
+       
+      
+      
+       ERASE_CODE
+       Erase Code.  The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete.
+       8
+       8
+       
+        
+         nop
+         No operation.
+         0
+        
+        
+         erasePage
+         Enable Page Erase.
+         0x55
+        
+        
+         eraseAll
+         Enable Mass Erase. The debug port must be enabled.
+         0xAA
+        
+       
+      
+      
+       PEND
+       Flash Pending.  When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored.
+       24
+       1
+       read-only
+       
+        
+         idle
+         Idle.
+         0
+        
+        
+         busy
+         Busy.
+         1
+        
+       
+      
+      
+       LVE
+       Low Voltage Read Enable 
+       25
+       1
+       read-only
+       
+        lve_read
+        read
+        
+         dis
+         Disabled
+         0
+        
+        
+         en
+         Enabled
+         1
+        
+       
+      
+      
+       BRST
+       Burst Mode Enable.
+       27
+       1
+       
+        
+         disable
+         Disable
+         0
+        
+        
+         enable
+         Enable
+         1
+        
+       
+      
+      
+       UNLOCK
+       Flash Unlock.  The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed.
+       28
+       4
+       
+        
+         unlocked
+         Flash Unlocked
+         2
+        
+        
+         locked
+         Flash Locked
+         3
+        
+       
+      
+     
+    
+    
+     INTR
+     Flash Interrupt Register.
+     0x024
+     
+      
+       DONE
+       Flash Done Interrupt.  This bit is set to 1 upon Flash write or erase completion.
+       0
+       1
+       
+        
+         inactive
+         No interrupt is pending
+         0
+        
+        
+         pending
+         An interrupt is pending
+         1
+        
+       
+      
+      
+       AF
+       Flash Access Fail.  This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware.
+       1
+       1
+       
+        
+         noError
+         No Failure.
+         0
+        
+        
+         error
+         Failure occurs.
+         1
+        
+       
+      
+      
+       DONEIE
+       Flash Done Interrupt Enable.
+       8
+       1
+       
+        
+         disable
+         Disable.
+         0
+        
+        
+         enable
+         Enable.
+         1
+        
+       
+      
+      
+       AFIE
+       9
+       1
+      
+     
+    
+    
+     4
+     4
+     DATA[%s]
+     Flash Write Data.
+     0x30
+     
+      
+       DATA
+       Data next operation.
+       0
+       32
+      
+     
+    
+    
+     ACNTL
+     Access Control Register. Writing the ACNTL register with the following values in the order shown, allows read and write access to the system and user Information block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = 0xa1e34f20; pflc-acntl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero.
+     0x40
+     write-only
+     
+      
+       ACNTL
+       Access control.
+       0
+       32
+      
+     
+    
+   
+  
+
+  
+   GCR
+   Global Control Registers.
+   0x40000000
+   
+    0
+    0x400
+    registers
+   
+   
+    
+     SCON
+     System Control.
+     0x00
+     0xFFFFFFFE
+     
+      
+       SBUSARB
+       System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset.
+       1
+       2
+       
+        
+         fix
+         Fixed Burst abritration.
+         0
+        
+        
+         round
+         Round-robin scheme.
+         1
+        
+       
+      
+      
+       FLASH_PAGE_FLIP
+       Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer.
+       4
+       1
+       
+        
+         normal
+         Physical layout matches logical layout.
+         0
+        
+        
+         swapped
+         Bottom half mapped to logical top half and vice versa.
+         1
+        
+       
+      
+      
+       FPU_DIS
+       Floating Point Unit Disable 
+       5
+       1
+       
+        
+         enable
+         enable Floating point unit
+         0
+        
+        
+         disable
+         disable floating point unit 
+         1
+        
+       
+      
+      
+       CCACHE_FLUSH
+       Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. 
+       6
+       1
+       
+        
+         normal
+         Normal Code Cache Operation
+         0
+        
+        
+         flush
+         Code Caches and CPU instruction buffer are flushed 
+         1
+        
+       
+      
+      
+       SWD_DIS
+       Serial Wire Debug Disable 
+       14
+       1
+       
+        
+         enable
+         Enable JTAG SWD
+         0
+        
+        
+         disable
+         Disable JTAG SWD 
+         1
+        
+       
+      
+     
+    
+    
+     RSTR0
+     Reset.
+     0x04
+     
+      
+       DMA
+       DMA Reset.
+       0
+       1
+       
+        dma_write
+        write
+        
+         RFU
+         Reserved. Do not use.
+         0
+        
+        
+         reset
+         Starts reset operation.
+         1
+        
+       
+       
+        dma_read
+        read
+        
+         Reset_Done
+         Reset Complete
+         0
+        
+        
+         Busy
+         Reset Busy
+         1
+        
+       
+      
+      
+       WDT
+       Watchdog Timer Reset.
+       1
+       1
+       
+        wdt_write
+        write
+        
+         RFU
+         Reserved. Do not use.
+         0
+        
+        
+         reset
+         Starts reset operation.
+         1
+        
+       
+       
+        wdt_read
+        read
+        
+         Reset_Done
+         Reset Complete
+         0
+        
+        
+         Busy
+         Reset Busy
+         1
+        
+       
+      
+      
+       GPIO0
+       GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states.
+       2
+       1
+       
+        gpio0_write
+        write
+        
+         RFU
+         Reserved. Do not use.
+         0
+        
+        
+         reset
+         Starts reset operation.
+         1
+        
+       
+       
+        gpio0_read
+        read
+        
+         Reset_Done
+         Reset Complete
+         0
+        
+        
+         Busy
+         Reset Busy
+         1
+        
+       
+      
+      
+       TIMER0
+       Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks.
+       5
+       1
+       
+        timer0_write
+        write
+        
+         RFU
+         Reserved. Do not use.
+         0
+        
+        
+         reset
+         Starts reset operation.
+         1
+        
+       
+       
+        timer0_read
+        read
+        
+         Reset_Done
+         Reset Complete
+         0
+        
+        
+         Busy
+         Reset Busy
+         1
+        
+       
+      
+      
+       TIMER1
+       Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks.
+       6
+       1
+       
+        timer1_write
+        write
+        
+         RFU
+         Reserved. Do not use.
+         0
+        
+        
+         reset
+         Starts reset operation.
+         1
+        
+       
+       
+        timer1_read
+        read
+        
+         Reset_Done
+         Reset Complete
+         0
+        
+        
+         Busy
+         Reset Busy
+         1
+        
+       
+      
+      
+       TIMER2
+       Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks.
+       7
+       1
+       
+        timer2_write
+        write
+        
+         RFU
+         Reserved. Do not use.
+         0
+        
+        
+         reset
+         Starts reset operation.
+         1
+        
+       
+       
+        timer2_read
+        read
+        
+         Reset_Done
+         Reset Complete
+         0
+        
+        
+         Busy
+         Reset Busy
+         1
+        
+       
+      
+      
+       UART0
+       UART0 Reset. Setting this bit to 1 resets all UART 0 blocks.
+       11
+       1
+       
+        uart0_write
+        write
+        
+         RFU
+         Reserved. Do not use.
+         0
+        
+        
+         reset
+         Starts reset operation.
+         1
+        
+       
+       
+        uart0_read
+        read
+        
+         Reset_Done
+         Reset Complete
+         0
+        
+        
+         Busy
+         Reset Busy
+         1
+        
+       
+      
+      
+       UART1
+       UART1 Reset. Setting this bit to 1 resets all UART 1 blocks.
+       12
+       1
+       
+        uart1_write
+        write
+        
+         RFU
+         Reserved. Do not use.
+         0
+        
+        
+         reset
+         Starts reset operation.
+         1
+        
+       
+       
+        uart1_read
+        read
+        
+         Reset_Done
+         Reset Complete
+         0
+        
+        
+         Busy
+         Reset Busy
+         1
+        
+       
+      
+      
+       SPI0
+       SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks.
+       13
+       1
+       
+        spi0_write
+        write
+        
+         RFU
+         Reserved. Do not use.
+         0
+        
+        
+         reset
+         Starts reset operation.
+         1
+        
+       
+       
+        spi0_read
+        read
+        
+         Reset_Done
+         Reset Complete
+         0
+        
+        
+         Busy
+         Reset Busy
+         1
+        
+       
+      
+      
+       SPI1
+       SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks.
+       14
+       1
+       
+        spi1_write
+        write
+        
+         RFU
+         Reserved. Do not use.
+         0
+        
+        
+         reset
+         Starts reset operation.
+         1
+        
+       
+       
+        xpi1_read
+        read
+        
+         Reset_Done
+         Reset Complete
+         0
+        
+        
+         Busy
+         Reset Busy
+         1
+        
+       
+      
+      
+       I2C0
+       I2C0 Reset.
+       16
+       1
+       
+        i2c0_write
+        write
+        
+         RFU
+         Reserved. Do not use.
+         0
+        
+        
+         reset
+         Starts reset operation.
+         1
+        
+       
+       
+        i2c0_read
+        read
+        
+         Reset_Done
+         Reset Complete
+         0
+        
+        
+         Busy
+         Reset Busy
+         1
+        
+       
+      
+      
+       RTC
+       Real Time Clock Reset.
+       17
+       1
+       
+        rtc_write
+        write
+        
+         RFU
+         Reserved. Do not use.
+         0
+        
+        
+         reset
+         Starts reset operation.
+         1
+        
+       
+       
+        rtc_read
+        read
+        
+         Reset_Done
+         Reset Complete
+         0
+        
+        
+         Busy
+         Reset Busy
+         1
+        
+       
+      
+      
+       SRST
+       Soft Reset.Write 1 to perform a Soft Reset. A soft reset performs a Peripheral Reset and also resets the GPIO peripheral but does not reset the CPU or Watchdog Timer.
+       29
+       1
+       
+        srst_write
+        write
+        
+         RFU
+         Reserved. Do not use.
+         0
+        
+        
+         reset
+         Starts reset operation.
+         1
+        
+       
+       
+        srst_read
+        read
+        
+         Reset_Done
+         Reset Complete
+         0
+        
+        
+         Busy
+         Reset Busy
+         1
+        
+       
+      
+      
+       PRST
+       Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset.
+       30
+       1
+       
+        prst_write
+        write
+        
+         RFU
+         Reserved. Do not use.
+         0
+        
+        
+         reset
+         Starts reset operation.
+         1
+        
+       
+       
+        prst_read
+        read
+        
+         Reset_Done
+         Reset Complete
+         0
+        
+        
+         Busy
+         Reset Busy
+         1
+        
+       
+      
+      
+       SYSTEM
+       System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer.
+       31
+       1
+       
+        system_write
+        write
+        
+         RFU
+         Reserved. Do not use.
+         0
+        
+        
+         reset
+         Starts reset operation.
+         1
+        
+       
+       
+        system_read
+        read
+        
+         Reset_Done
+         Reset Complete
+         0
+        
+        
+         Busy
+         Reset Busy
+         1
+        
+       
+      
+     
+    
+    
+     CLKCN
+     Clock Control.
+     0x08
+     0x00000008
+     
+      
+       PSC
+       Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0.
+       6
+       3
+       
+        
+         div1
+         Divide by 1.
+         0
+        
+        
+         div2
+         Divide by 2.
+         1
+        
+        
+         div4
+         Divide by 4.
+         2
+        
+        
+         div8
+         Divide by 8.
+         3
+        
+        
+         div16
+         Divide by 16.
+         4
+        
+        
+         div32
+         Divide by 32.
+         5
+        
+        
+         div64
+         Divide by 64.
+         6
+        
+        
+         div128
+         Divide by 128.
+         7
+        
+       
+      
+      
+       CLKSEL
+       Clock Source Select. This 3 bit field selects the source for the system clock.
+       9
+       3
+       
+        
+         HIRC
+         The internal 96 MHz oscillator is used for the system clock.
+         0
+        
+        
+         nanoRing
+         The nano-ring output is used for the system clock.
+         3
+        
+        
+         hfxIn
+         HFXIN is used for the system clock.
+         6
+        
+       
+      
+      
+       CKRDY
+       Clock Ready. This read only bit reflects whether the currently selected system clock source is running.
+       13
+       1
+       read-only
+       
+        
+         busy
+         Switchover to the new clock source (as selected by CLKSEL) has not yet occurred.
+         0
+        
+        
+         ready
+         System clock running from CLKSEL clock source.
+         1
+        
+       
+      
+      
+       X32K_EN
+       32kHz Crystal Oscillator Enable.
+       17
+       1
+       
+        
+         dis
+         Is Disabled.
+         0
+        
+        
+         en
+         Is Enabled.
+         1
+        
+       
+      
+      
+       HIRC_EN
+       60MHz High Frequency Internal Reference Clock Enable.
+       18
+       1
+       
+        
+         dis
+         Is Disabled.
+         0
+        
+        
+         en
+         Is Enabled.
+         1
+        
+       
+      
+      
+       X32K_RDY
+       32kHz Crystal Oscillator Ready
+       25
+       1
+       read-only
+       
+        
+         not
+         Not Ready
+         0
+        
+        
+         Ready
+         X32K Ready
+         1
+        
+       
+      
+      
+       HIRC_RDY
+       60MHz HIRC Ready.
+       26
+       1
+       
+        
+         not
+         Not Ready
+         0
+        
+        
+         ready
+         HIRC Ready
+         1
+        
+       
+      
+      
+       LIRC8K_RDY
+       8kHz Low Frequency Reference Clock Ready.
+       29
+       1
+       
+        
+         not
+         Not Ready
+         0
+        
+        
+         ready
+         Clock Ready
+         1
+        
+       
+      
+     
+    
+    
+     PM
+     Power Management.
+     0x0C
+     
+      
+       MODE
+       Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode.
+       0
+       3
+       
+        
+         active
+         Active Mode.
+         0
+        
+        
+         shutdown
+         Shutdown Mode.
+         3
+        
+        
+         backup
+         Backup Mode.
+         4
+        
+       
+      
+      
+       GPIOWKEN
+       GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set.
+       4
+       1
+       
+        
+         dis
+         Wake Up Disable.
+         0
+        
+        
+         en
+         Wake Up Enable.
+         1
+        
+       
+      
+      
+       RTCWKEN
+       RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers.
+       5
+       1
+       
+        
+         dis
+         Wake Up Disable.
+         0
+        
+        
+         en
+         Wake Up Enable.
+         1
+        
+       
+      
+      
+       HIRCPD
+       HIRC Power Down. This bit selects HIRC power state in DEEPSLEEP mode. 
+       15
+       1
+       
+        
+         active
+         Mode is Active.
+         0
+        
+        
+         deepsleep
+         Powered down in DEEPSLEEP.
+         1
+        
+       
+      
+     
+    
+    
+     PCKDIV
+     Peripheral Clock Divider.
+     0x18
+     0x00000001
+     
+      
+       AONCD
+       Always-ON(AON) domain CLock Divider. These bits define the AON domain clock divider.
+       0
+       2
+       
+        
+         div_4
+         PCLK divide by 4.
+         0
+        
+        
+         div_8
+         PCLK divide by 8.
+         1
+        
+        
+         div_16
+         PCLK divide by 16.
+         2
+        
+        
+         div_32
+         PCLK divide by 32.
+         3
+        
+       
+      
+     
+    
+    
+     PERCKCN0
+     Peripheral Clock Disable.
+     0x24
+     
+      
+       GPIO0D
+       GPIO0 Disable.
+       0
+       1
+       
+        GPIODisable
+        
+         en
+         enable it.
+         0
+        
+        
+         dis
+         disable it.
+         1
+        
+       
+      
+      
+       DMAD
+       DMA Disable.
+       5
+       1
+       
+        GPIODisable
+        
+         en
+         enable it.
+         0
+        
+        
+         dis
+         disable it.
+         1
+        
+       
+      
+      
+       SPI0D
+       SPI 0 Disable.
+       6
+       1
+       
+        GPIODisable
+        
+         en
+         enable it.
+         0
+        
+        
+         dis
+         disable it.
+         1
+        
+       
+      
+      
+       SPI1D
+       SPI 1 Disable.
+       7
+       1
+       
+        GPIODisable
+        
+         en
+         enable it.
+         0
+        
+        
+         dis
+         disable it.
+         1
+        
+       
+      
+      
+       UART0D
+       UART 0 Disable.
+       9
+       1
+       
+        GPIODisable
+        
+         en
+         enable it.
+         0
+        
+        
+         dis
+         disable it.
+         1
+        
+       
+      
+      
+       UART1D
+       UART 1 Disable.
+       10
+       1
+       
+        GPIODisable
+        
+         en
+         enable it.
+         0
+        
+        
+         dis
+         disable it.
+         1
+        
+       
+      
+      
+       I2C0D
+       I2C 0 Disable.
+       13
+       1
+       
+        GPIODisable
+        
+         en
+         enable it.
+         0
+        
+        
+         dis
+         disable it.
+         1
+        
+       
+      
+      
+       T0D
+       Timer 0 Disable.
+       15
+       1
+       
+        GPIODisable
+        
+         en
+         enable it.
+         0
+        
+        
+         dis
+         disable it.
+         1
+        
+       
+      
+      
+       T1D
+       Timer 1 Disable.
+       16
+       1
+       
+        GPIODisable
+        
+         en
+         enable it.
+         0
+        
+        
+         dis
+         disable it.
+         1
+        
+       
+      
+      
+       T2D
+       Timer 2 Disable.
+       17
+       1
+       
+        GPIODisable
+        
+         en
+         enable it.
+         0
+        
+        
+         dis
+         disable it.
+         1
+        
+       
+      
+      
+       I2C1D
+       I2C 1 Disable.
+       28
+       1
+       
+        GPIODisable
+        
+         en
+         enable it.
+         0
+        
+        
+         dis
+         disable it.
+         1
+        
+       
+      
+     
+    
+    
+     MEMCKCN
+     Memory Clock Control Register.
+     0x28
+     
+      
+       FWS
+       Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2.
+       0
+       3
+      
+      
+       SYSRAM0LS
+       System RAM 0 Light Sleep Mode.
+       8
+       1
+       
+        
+         active
+         Memory is active.
+         0
+        
+        
+         light_sleep
+         Memory is in Light Sleep mode.
+         1
+        
+       
+      
+      
+       SYSRAM1LS
+       System RAM 1 Light Sleep Mode.
+       9
+       1
+       
+        
+         active
+         Memory is active.
+         0
+        
+        
+         light_sleep
+         Memory is in Light Sleep mode.
+         1
+        
+       
+      
+      
+       SYSRAM2LS
+       System RAM 2 Light Sleep Mode.
+       10
+       1
+       
+        
+         active
+         Memory is active.
+         0
+        
+        
+         light_sleep
+         Memory is in Light Sleep mode.
+         1
+        
+       
+      
+      
+       SYSRAM3LS
+       System RAM 3 Light Sleep Mode.
+       11
+       1
+       
+        
+         active
+         Memory is active.
+         0
+        
+        
+         light_sleep
+         Memory is in Light Sleep mode.
+         1
+        
+       
+      
+      
+       ICACHELS
+       ICache RAM Light Sleep Mode.
+       12
+       1
+       
+        
+         active
+         Memory is active.
+         0
+        
+        
+         light_sleep
+         Memory is in Light Sleep mode.
+         1
+        
+       
+      
+     
+    
+    
+     MEMZCN
+     Memory Zeroize Control.
+     0x2C
+     
+      
+       SRAM0Z
+       System RAM Block 0.
+       0
+       1
+       
+        
+         nop
+         No operation/complete.
+         0
+        
+        
+         start
+         Start operation.
+         1
+        
+       
+      
+      
+       ICACHEZ
+       Instruction Cache.
+       1
+       1
+       
+        
+         nop
+         No operation/complete.
+         0
+        
+        
+         start
+         Start operation.
+         1
+        
+       
+      
+     
+    
+    
+     SCCK
+     Smart Card Clock Control.
+     0x34
+     0x00001414
+    
+    
+     MPRI0
+     Master Priority Control Register 0.
+     0x38
+     0x00001414
+    
+    
+     MPRI1
+     Mater Priority Control Register 1.
+     0x3C
+     0x00001414
+    
+    
+     SYSST
+     System Status Register.
+     0x40
+     
+      
+       ICECLOCK
+       ARM ICE Lock Status.
+       0
+       1
+       
+        
+         unlocked
+         ICE is unlocked.
+         0
+        
+        
+         locked
+         ICE is locked.
+         1
+        
+       
+      
+      
+       CODEINTERR
+       Code Integrity Error Flag. This bit indicates a code integrity error has occured in XiP interface. 
+       1
+       1
+       
+        
+         norm
+         Normal Operating Condition.
+         0
+        
+        
+         code
+         Code Integrity Error.
+         1
+        
+       
+      
+      
+       SCMEMF
+       System Cache Memory Fault Flag. This bit indicates a memory fault has occured in the System Cache while receiving data from the Hyperbus Interface.
+       5
+       1
+       
+        
+         norm
+         Normal Operating Condition.
+         0
+        
+        
+         memory
+         Memory Fault.
+         1
+        
+       
+      
+     
+    
+    
+     RSTR1
+     Reset 1.
+     0x44
+     
+      
+       I2C1
+       I2C1 Reset.
+       0
+       1
+       
+        reset_write
+        write
+        
+         RFU
+         Reserved. Do not use.
+         0
+        
+        
+         reset
+         Starts reset operation.
+         1
+        
+       
+       
+        reset_read
+        read
+        
+         reset_done
+         Reset complete.
+         0
+        
+        
+         busy
+         Reset in progress.
+         1
+        
+       
+      
+     
+    
+    
+     PERCKCN1
+     Peripheral Clock Disable.
+     0x48
+     
+      
+       FLCD
+       Secure Flash Controller Disable.
+       3
+       1
+       
+        
+         en
+         Enable.
+         0
+        
+        
+         dis
+         Disable.
+         1
+        
+       
+      
+      
+       ICACHED
+       ICache Clock Disable. 
+       11
+       1
+       
+        
+         en
+         Enable.
+         0
+        
+        
+         dis
+         Disable.
+         1
+        
+       
+      
+     
+    
+    
+     EVTEN
+     Event Enable Register.
+     0x4C
+     
+      
+       DMAEVENT
+       Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode.
+       0
+       1
+      
+      
+       RXEVENT
+       Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. 
+       1
+       1
+      
+     
+    
+    
+     REVISION
+     Revision Register.
+     0x50
+     read-only
+     
+      
+       REVISION
+       Manufacturer Chip Revision. 
+       0
+       16
+      
+     
+    
+    
+     SYSSIE
+     System Status Interrupt Enable Register.
+     0x54
+     
+      
+       ICEULIE
+       ARM ICE Unlock Interrupt Enable.
+       0
+       1
+       
+        
+         dis
+         disabled.
+         0
+        
+        
+         en
+         enabled.
+         1
+        
+       
+      
+      
+       CIEIE
+       Code Integrity Error Interrupt Enable.
+       1
+       1
+       
+        
+         dis
+         disabled.
+         0
+        
+        
+         en
+         enabled.
+         1
+        
+       
+      
+      
+       SCMFIE
+       System Cache Memory Fault Interrupt Enable.
+       5
+       1
+       
+        
+         dis
+         disabled.
+         0
+        
+        
+         en
+         enabled.
+         1
+        
+       
+      
+     
+    
+   
+  
+
+  
+   GPIO0
+   Individual I/O for each GPIO
+   GPIO
+   0x40008000
+   
+    0x00
+    0x1000
+    registers
+   
+   
+    GPIO0
+    GPIO0 interrupt.
+    24
+   
+   
+    
+     EN
+     GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port.
+     0x00
+     
+      
+       GPIO_EN
+       Mask of all of the pins on the port.
+       0
+       32
+       
+        
+         alternate
+         Alternate function enabled.
+         0
+        
+        
+         GPIO
+         GPIO function is enabled.
+         1
+        
+       
+      
+     
+    
+    
+     EN_SET
+     GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register.
+     0x04
+     
+      
+       ALL
+       Mask of all of the pins on the port.
+       0
+       32
+      
+     
+    
+    
+     EN_CLR
+     GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register.
+     0x08
+     
+      
+       ALL
+       Mask of all of the pins on the port.
+       0
+       32
+      
+     
+    
+    
+     OUT_EN
+     GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port.
+     0x0C
+     
+      
+       GPIO_OUT_EN
+       Mask of all of the pins on the port.
+       0
+       32
+       
+        
+         dis
+         GPIO Output Disable
+         0
+        
+        
+         en
+         GPIO Output Enable
+         1
+        
+       
+      
+     
+    
+    
+     OUT_EN_SET
+     GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register.
+     0x10
+     
+      
+       ALL
+       Mask of all of the pins on the port.
+       0
+       32
+      
+     
+    
+    
+     OUT_EN_CLR
+     GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register.
+     0x14
+     
+      
+       ALL
+       Mask of all of the pins on the port.
+       0
+       32
+      
+     
+    
+    
+     OUT
+     GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port.  This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers.
+     0x18
+     
+      
+       GPIO_OUT
+       Mask of all of the pins on the port.
+       0
+       32
+       
+        
+         low
+         Drive Logic 0 (low) on GPIO output.
+         0
+        
+        
+         high
+         Drive logic 1 (high) on GPIO output.
+         1
+        
+       
+      
+     
+    
+    
+     OUT_SET
+     GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register.
+     0x1C
+     write-only
+     
+      
+       GPIO_OUT_SET
+       Mask of all of the pins on the port.
+       0
+       32
+       
+        
+         no
+         No Effect.
+         0
+        
+        
+         set
+         Set GPIO_OUT bit in this position to '1'
+         1
+        
+       
+      
+     
+    
+    
+     OUT_CLR
+     GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register.
+     0x20
+     write-only
+     
+      
+       GPIO_OUT_CLR
+       Mask of all of the pins on the port.
+       0
+       32
+      
+     
+    
+    
+     IN
+     GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port.
+     0x24
+     read-only
+     
+      
+       GPIO_IN
+       Mask of all of the pins on the port.
+       0
+       32
+      
+     
+    
+    
+     INT_MOD
+     GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port.
+     0x28
+     
+      
+       GPIO_INT_MOD
+       Mask of all of the pins on the port.
+       0
+       32
+       
+        
+         level
+         Interrupts for this pin are level triggered.
+         0
+        
+        
+         edge
+         Interrupts for this pin are edge triggered.
+         1
+        
+       
+      
+     
+    
+    
+     INT_POL
+     GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port.
+     0x2C
+     
+      
+       GPIO_INT_POL
+       Mask of all of the pins on the port.
+       0
+       32
+       
+        
+         falling
+         Interrupts are latched on a falling edge or low level condition for this pin.
+         0
+        
+        
+         rising
+         Interrupts are latched on a rising edge or high condition for this pin.
+         1
+        
+       
+      
+     
+    
+    
+     INT_EN
+     GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port.
+     0x34
+     
+      
+       GPIO_INT_EN
+       Mask of all of the pins on the port.
+       0
+       32
+       
+        
+         dis
+         Interrupts are disabled for this GPIO pin.
+         0
+        
+        
+         en
+         Interrupts are enabled for this GPIO pin.
+         1
+        
+       
+      
+     
+    
+    
+     INT_EN_SET
+     GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register.
+     0x38
+     
+      
+       GPIO_INT_EN_SET
+       Mask of all of the pins on the port.
+       0
+       32
+       
+        
+         no
+         No effect.
+         0
+        
+        
+         set
+         Set GPIO_INT_EN bit in this position to '1'
+         1
+        
+       
+      
+     
+    
+    
+     INT_EN_CLR
+     GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register.
+     0x3C
+     
+      
+       GPIO_INT_EN_CLR
+       Mask of all of the pins on the port.
+       0
+       32
+       
+        
+         no
+         No Effect.
+         0
+        
+        
+         clear
+         Clear GPIO_INT_EN bit in this position to '0'
+         1
+        
+       
+      
+     
+    
+    
+     INT_STAT
+     GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port.
+     0x40
+     read-only
+     
+      
+       GPIO_INT_STAT
+       Mask of all of the pins on the port.
+       0
+       32
+       
+        
+         no
+         No Interrupt is pending on this GPIO pin.
+         0
+        
+        
+         pending
+         An Interrupt is pending on this GPIO pin.
+         1
+        
+       
+      
+     
+    
+    
+     INT_CLR
+     GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register.
+     0x48
+     
+      
+       ALL
+       Mask of all of the pins on the port.
+       0
+       32
+      
+     
+    
+    
+     WAKE_EN
+     GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port.
+     0x4C
+     
+      
+       GPIO_WAKE_EN
+       Mask of all of the pins on the port.
+       0
+       32
+       
+        
+         dis
+         PMU wakeup for this GPIO is disabled.
+         0
+        
+        
+         en
+         PMU wakeup for this GPIO is enabled.
+         1
+        
+       
+      
+     
+    
+    
+     WAKE_EN_SET
+     GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register.
+     0x50
+     
+      
+       ALL
+       Mask of all of the pins on the port.
+       0
+       32
+      
+     
+    
+    
+     WAKE_EN_CLR
+     GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register.
+     0x54
+     
+      
+       ALL
+       Mask of all of the pins on the port.
+       0
+       32
+      
+     
+    
+    
+     INT_DUAL_EDGE
+     GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port.
+     0x5C
+     
+      
+       GPIO_INT_DUAL_EDGE
+       Mask of all of the pins on the port.
+       0
+       32
+       
+        
+         no
+         No Effect.
+         0
+        
+        
+         en
+         Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting.
+         1
+        
+       
+      
+     
+    
+    
+     PAD_CFG1
+     GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.
+     0x60
+     
+      
+       GPIO_PAD_CFG1
+       The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.
+       0
+       32
+       
+        
+         impedance
+         High Impedance.
+         0
+        
+        
+         pu
+         Weak pull-up mode.
+         1
+        
+        
+         pd
+         weak pull-down mode.
+         2
+        
+       
+      
+     
+    
+    
+     PAD_CFG2
+     GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.
+     0x64
+     
+      
+       GPIO_PAD_CFG2
+       The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.
+       0
+       32
+       
+        
+         impedance
+         High Impedance.
+         0
+        
+        
+         pu
+         Weak pull-up mode.
+         1
+        
+        
+         pd
+         weak pull-down mode.
+         2
+        
+       
+      
+     
+    
+    
+     EN1
+     GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.
+     0x68
+     
+      
+       GPIO_EN1
+       Mask of all of the pins on the port.
+       0
+       32
+       
+        
+         primary
+         Primary function selected.
+         0
+        
+        
+         secondary
+         Secondary function selected.
+         1
+        
+       
+      
+     
+    
+    
+     EN1_SET
+     GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register.
+     0x6C
+     
+      
+       ALL
+       Mask of all of the pins on the port.
+       0
+       32
+      
+     
+    
+    
+     EN1_CLR
+     GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register.
+     0x70
+     
+      
+       ALL
+       Mask of all of the pins on the port.
+       0
+       32
+      
+     
+    
+    
+     EN2
+     GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.
+     0x74
+     
+      
+       GPIO_EN2
+       Mask of all of the pins on the port.
+       0
+       32
+       
+        
+         primary
+         Primary function selected.
+         0
+        
+        
+         secondary
+         Secondary function selected.
+         1
+        
+       
+      
+     
+    
+    
+     EN2_SET
+     GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register.
+     0x78
+     
+      
+       ALL
+       Mask of all of the pins on the port.
+       0
+       32
+      
+     
+    
+    
+     EN2_CLR
+     GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register.
+     0x7C
+     
+      
+       ALL
+       Mask of all of the pins on the port.
+       0
+       32
+      
+     
+    
+    
+     IS
+     Input Hysteresis Enable Register
+     0xA8
+    
+    
+     SR
+     Slew Rate Select Register.
+     0xAC
+    
+    
+     DS
+     GPIO Drive Strength  Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode.
+     0xB0
+     
+      
+       DS
+       Mask of all of the pins on the port.
+       0
+       32
+       
+        
+         ld
+         GPIO port pin is in low-drive mode.
+         0
+        
+        
+         hd
+         GPIO port pin is in high-drive mode.
+         1
+        
+       
+      
+     
+    
+    
+     DS1
+     GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode.
+     0xB4
+     
+      
+       ALL
+       Mask of all of the pins on the port.
+       0
+       32
+      
+     
+    
+    
+     PS
+     GPIO Pull Select Mode.
+     0xB8
+     
+      
+       ALL
+       Mask of all of the pins on the port.
+       0
+       32
+      
+     
+    
+    
+     VSSEL
+     GPIO Voltage Select.
+     0xC0
+     
+      
+       ALL
+       Mask of all of the pins on the port.
+       0
+       32
+      
+     
+    
+   
+  
+
+  
+   I2C0
+   Inter-Integrated Circuit.
+   I2C
+   0x4001D000
+   32
+   
+    0x00
+    0x1000
+    registers
+   
+   
+    I2C0
+    I2C0 IRQ
+    13
+   
+   
+    
+     CTRL
+     Control Register0.
+     0x00
+     
+      
+       I2C_EN
+       I2C Enable.
+       [0:0]
+       read-write
+       
+        
+         dis
+         Disable I2C.
+         0
+        
+        
+         en
+         enable I2C.
+         1
+        
+       
+      
+      
+       MST
+       Master Mode Enable.
+       [1:1]
+       read-write
+       
+        
+         slave_mode
+         Slave Mode.
+         0
+        
+        
+         master_mode
+         Master Mode.
+         1
+        
+       
+      
+      
+       GEN_CALL_ADDR
+       General Call Address Enable.
+       [2:2]
+       read-write
+       
+        
+         dis
+         Ignore Gneral Call Address.
+         0
+        
+        
+         en
+         Acknowledge general call address.
+         1
+        
+       
+      
+      
+       RX_MODE
+       Interactive Receive Mode.
+       [3:3]
+       read-write
+       
+        
+         dis
+         Disable Interactive Receive Mode.
+         0
+        
+        
+         en
+         Enable Interactive Receive Mode.
+         1
+        
+       
+      
+      
+       RX_MODE_ACK
+       Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0.
+       [4:4]
+       read-write
+       
+        
+         ack
+         return ACK (pulling SDA LOW).
+         0
+        
+        
+         nack
+         return NACK (leaving SDA HIGH).
+         1
+        
+       
+      
+      
+       SCL_OUT
+       SCL Output. This bits control SCL output when SWOE =1.
+       [6:6]
+       read-write
+       
+        
+         drive_scl_low
+         Drive SCL low. 
+         0
+        
+        
+         release_scl
+         Release SCL.
+         1
+        
+       
+      
+      
+       SDA_OUT
+       SDA Output. This bits control SDA output when SWOE = 1. 
+       [7:7]
+       read-write
+       
+        
+         drive_sda_low
+         Drive SDA low. 
+         0
+        
+        
+         release_sda
+         Release SDA.
+         1
+        
+       
+      
+      
+       SCL
+       SCL status. This bit reflects the logic gate of SCL signal. 
+       [8:8]
+       read-only
+      
+      
+       SDA
+       SDA status. THis bit reflects the logic gate of SDA signal.
+       [9:9]
+       read-only
+      
+      
+       SW_OUT_EN
+       Software Output Enable.
+       [10:10]
+       read-write
+       
+        
+         outputs_disable
+         I2C Outputs SCLO and SDAO disabled. 
+         0
+        
+        
+         outputs_enable
+         I2C Outputs SCLO and SDAO enabled.
+         1
+        
+       
+      
+      
+       READ
+       Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match(GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set.
+       [11:11]
+       read-only
+       
+        
+         write
+         Write.
+         0
+        
+        
+         read
+         Read.
+         1
+        
+       
+      
+      
+       SCL_CLK_STRECH_DIS
+       This bit will disable slave clock stretching when set.
+       [12:12]
+       read-write
+       
+        
+         en
+         Slave clock stretching enabled.
+         0
+        
+        
+         dis
+         Slave clock stretching disabled.
+         1
+        
+       
+      
+      
+       SCL_PP_MODE
+       SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low. 
+       [13:13]
+       read-write
+       
+        
+         dis
+         Standard open-drain operation: drive low for 0, Hi-Z for 1
+         0
+        
+        
+         en
+         Non-standard push-pull operation: drive low for 0, drive high for 1
+         1
+        
+       
+      
+      
+       HS_MODE
+       Hs-mode Enable.
+       15
+       1
+       
+        
+         dis
+         Hs-mode disabled.
+         0
+        
+        
+         en
+         Hs-mode enabled.
+         1
+        
+       
+      
+     
+    
+    
+     STATUS
+     Status Register.
+     0x04
+     
+      
+       BUS
+       Bus Status.
+       [0:0]
+       read-only
+       
+        
+         idle
+         I2C Bus Idle.
+         0
+        
+        
+         busy
+         I2C Bus Busy.
+         1
+        
+       
+      
+      
+       RX_EMPTY
+       RX empty.
+       [1:1]
+       read-only
+       
+        
+         not_empty
+         Not Empty.
+         0
+        
+        
+         empty
+         Empty.
+         1
+        
+       
+      
+      
+       RX_FULL
+       RX Full.
+       [2:2]
+       read-only
+       
+        
+         not_full
+         Not Full.
+         0
+        
+        
+         full
+         Full.
+         1
+        
+       
+      
+      
+       TX_EMPTY
+       TX Empty.
+       [3:3]
+       
+        
+         not_empty
+         Not Empty.
+         0
+        
+        
+         empty
+         Empty.
+         1
+        
+       
+      
+      
+       TX_FULL
+       TX Full.
+       [4:4]
+       
+        
+         not_empty
+         Not Empty.
+         0
+        
+        
+         empty
+         Empty.
+         1
+        
+       
+      
+      
+       CLK_MODE
+       Clock Mode.
+       [5:5]
+       read-only
+       
+        
+         not_actively_driving_scl_clock
+         Device not actively driving SCL clock cycles.
+         0
+        
+        
+         actively_driving_scl_clock
+         Device operating as master and actively driving SCL clock cycles.
+         1
+        
+       
+      
+      
+       STATUS
+       Controller Status.
+       [11:8]
+       
+        
+         idle
+         Controller Idle.
+         0
+        
+        
+         mtx_addr
+         master Transmit address.
+         1
+        
+        
+         mrx_addr_ack
+         Master Receive address ACK.
+         2
+        
+        
+         mtx_ex_addr
+         Master Transmit extended address.
+         3
+        
+        
+         mrx_ex_addr
+         Master Receive extended address ACK.
+         4
+        
+        
+         srx_addr
+         Slave Receive address.
+         5
+        
+        
+         stx_addr_ack
+         Slave Transmit address ACK.
+         6
+        
+        
+         srx_ex_addr
+         Slave Receive extended address.
+         7
+        
+        
+         stx_ex_addr_ack
+         Slave Transmit extended address ACK.
+         8
+        
+        
+         tx
+         Transmit data (master or slave).
+         9
+        
+        
+         rx_ack
+         Receive data ACK (master or slave).
+         10
+        
+        
+         rx
+         Receive data (master or slave).
+         11
+        
+        
+         tx_ack
+         Transmit data ACK (master or slave).
+         12
+        
+        
+         nack
+         NACK stage (master or slave).
+         13
+        
+        
+         by_st
+         Bystander state (ongoing transaction but not participant- another master addressing another slave).
+         15
+        
+       
+      
+     
+    
+    
+     INT_FL0
+     Interrupt Status Register.
+     0x08
+     
+      
+       DONE
+       Transfer Done Interrupt.
+       [0:0]
+       
+        INT_FL0_Done
+        
+         inactive
+         No Interrupt is Pending.
+         0
+        
+        
+         pending
+         An interrupt is pending.
+         1
+        
+       
+      
+      
+       RX_MODE
+       Interactive Receive Interrupt.
+       [1:1]
+       
+        
+         inactive
+         No Interrupt is Pending.
+         0
+        
+        
+         pending
+         An interrupt is pending.
+         1
+        
+       
+      
+      
+       GEN_CALL_ADDR
+       Slave General Call Address Match Interrupt.
+       [2:2]
+       
+        
+         inactive
+         No Interrupt is Pending.
+         0
+        
+        
+         pending
+         An interrupt is pending.
+         1
+        
+       
+      
+      
+       ADDR_MATCH
+       Slave Address Match Interrupt.
+       [3:3]
+       
+        
+         inactive
+         No Interrupt is Pending.
+         0
+        
+        
+         pending
+         An interrupt is pending.
+         1
+        
+       
+      
+      
+       RX_THRESH
+       Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level.
+       [4:4]
+       
+        
+         inactive
+         No interrupt is pending.
+         0
+        
+        
+         pending
+         An interrupt is pending. RX_FIFO equal or more bytes than the threshold.
+         1
+        
+       
+      
+      
+       TX_THRESH
+       Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level.
+       [5:5]
+       
+        
+         inactive
+         No interrupt is pending.
+         0
+        
+        
+         pending
+         An interrupt is pending. TX_FIFO has equal or less bytes than the threshold.
+         1
+        
+       
+      
+      
+       STOP
+       STOP Interrupt.
+       [6:6]
+       
+        
+         inactive
+         No interrupt is pending.
+         0
+        
+        
+         pending
+         An interrupt is pending. TX_FIFO has equal or less bytes than the threshold.
+         1
+        
+       
+      
+      
+       ADDR_ACK
+       Address Acknowledge Interrupt.
+       [7:7]
+       
+        
+         inactive
+         No Interrupt is Pending.
+         0
+        
+        
+         pending
+         An interrupt is pending.
+         1
+        
+       
+      
+      
+       ARB_ER
+       Arbritation error Interrupt.
+       [8:8]
+       
+        
+         inactive
+         No Interrupt is Pending.
+         0
+        
+        
+         pending
+         An interrupt is pending.
+         1
+        
+       
+      
+      
+       TO_ER
+       timeout Error Interrupt.
+       [9:9]
+       
+        
+         inactive
+         No Interrupt is Pending.
+         0
+        
+        
+         pending
+         An interrupt is pending.
+         1
+        
+       
+      
+      
+       ADDR_NACK_ER
+       Address NACK Error Interrupt.
+       [10:10]
+       
+        
+         inactive
+         No Interrupt is Pending.
+         0
+        
+        
+         pending
+         An interrupt is pending.
+         1
+        
+       
+      
+      
+       DATA_ER
+       Data NACK Error Interrupt.
+       [11:11]
+       
+        
+         inactive
+         No Interrupt is Pending.
+         0
+        
+        
+         pending
+         An interrupt is pending.
+         1
+        
+       
+      
+      
+       DO_NOT_RESP_ER
+       Do Not Respond Error Interrupt.
+       [12:12]
+       
+        
+         inactive
+         No Interrupt is Pending.
+         0
+        
+        
+         pending
+         An interrupt is pending.
+         1
+        
+       
+      
+      
+       START_ER
+       Start Error Interrupt.
+       [13:13]
+       
+        
+         inactive
+         No Interrupt is Pending.
+         0
+        
+        
+         pending
+         An interrupt is pending.
+         1
+        
+       
+      
+      
+       STOP_ER
+       Stop Error Interrupt.
+       [14:14]
+       
+        
+         inactive
+         No Interrupt is Pending.
+         0
+        
+        
+         pending
+         An interrupt is pending.
+         1
+        
+       
+      
+      
+       TX_LOCK_OUT
+       Transmit Lock Out Interrupt.
+       [15:15]
+      
+     
+    
+    
+     INT_EN0
+     Interrupt Enable Register.
+     0x0C
+     read-write
+     
+      
+       DONE
+       Transfer Done Interrupt Enable.
+       [0:0]
+       read-write
+       
+        
+         dis
+         Interrupt disabled.
+         0
+        
+        
+         en
+         Interrupt enabled when DONE = 1.
+         1
+        
+       
+      
+      
+       RX_MODE
+       Description not available.
+       [1:1]
+       read-write
+       
+        
+         dis
+         Interrupt disabled.
+         0
+        
+        
+         en
+         Interrupt enabled when RX_MODE = 1.
+         1
+        
+       
+      
+      
+       GEN_CTRL_ADDR
+       Slave mode general call address match received input enable.
+       [2:2]
+       read-write
+       
+        
+         dis
+         Interrupt disabled.
+         0
+        
+        
+         en
+         Interrupt enabled when GEN_CTRL_ADDR = 1.
+         1
+        
+       
+      
+      
+       ADDR_MATCH
+       Slave mode incoming address match interrupt.
+       [3:3]
+       read-write
+       
+        
+         dis
+         Interrupt disabled.
+         0
+        
+        
+         en
+         Interrupt enabled when ADDR_MATCH = 1.
+         1
+        
+       
+      
+      
+       RX_THRESH
+       RX FIFO Above Treshold Level Interrupt Enable.
+       [4:4]
+       read-write
+       
+        
+         dis
+         Interrupt disabled.
+         0
+        
+        
+         en
+         Interrupt enabled.
+         1
+        
+       
+      
+      
+       TX_THRESH
+       TX FIFO Below Treshold Level Interrupt Enable.
+       [5:5]
+       
+        
+         dis
+         Interrupt disabled.
+         0
+        
+        
+         en
+         Interrupt enabled.
+         1
+        
+       
+      
+      
+       STOP
+       Stop Interrupt Enable
+       [6:6]
+       read-write
+       
+        
+         dis
+         Interrupt disabled.
+         0
+        
+        
+         en
+         Interrupt enabled when STOP = 1.
+         1
+        
+       
+      
+      
+       ADDR_ACK
+       Received Address ACK from Slave Interrupt.
+       [7:7]
+       
+        
+         dis
+         Interrupt disabled.
+         0
+        
+        
+         en
+         Interrupt enabled.
+         1
+        
+       
+      
+      
+       ARB_ER
+       Master Mode Arbitration Lost Interrupt.
+       [8:8]
+       
+        
+         dis
+         Interrupt disabled.
+         0
+        
+        
+         en
+         Interrupt enabled.
+         1
+        
+       
+      
+      
+       TO_ER
+       Timeout Error Interrupt Enable.
+       [9:9]
+       
+        
+         dis
+         Interrupt disabled.
+         0
+        
+        
+         en
+         Interrupt enabled.
+         1
+        
+       
+      
+      
+       ADDR_ER
+       Master Mode Address NACK Received Interrupt.
+       [10:10]
+       
+        
+         dis
+         Interrupt disabled.
+         0
+        
+        
+         en
+         Interrupt enabled.
+         1
+        
+       
+      
+      
+       DATA_ER
+       Master Mode Data NACK Received Interrupt.
+       [11:11]
+       
+        
+         dis
+         Interrupt disabled.
+         0
+        
+        
+         en
+         Interrupt enabled.
+         1
+        
+       
+      
+      
+       DO_NOT_RESP_ER
+       Slave Mode Do Not Respond Interrupt.
+       [12:12]
+       
+        
+         dis
+         Interrupt disabled.
+         0
+        
+        
+         en
+         Interrupt enabled.
+         1
+        
+       
+      
+      
+       START_ER
+       Out of Sequence START condition detected interrupt.
+       [13:13]
+       
+        
+         dis
+         Interrupt disabled.
+         0
+        
+        
+         en
+         Interrupt enabled.
+         1
+        
+       
+      
+      
+       STOP_ER
+       Out of Sequence STOP condition detected interrupt.
+       [14:14]
+       
+        
+         dis
+         Interrupt disabled.
+         0
+        
+        
+         en
+         Interrupt enabled.
+         1
+        
+       
+      
+      
+       TX_LOCK_OUT
+       TX FIFO Locked Out Interrupt.
+       [15:15]
+       
+        
+         dis
+         Interrupt disabled.
+         0
+        
+        
+         en
+         Interrupt enabled when TXLOIE = 1.
+         1
+        
+       
+      
+     
+    
+    
+     INT_FL1
+     Interrupt Status Register 1.
+     0x10
+     
+      
+       RX_OVERFLOW
+       Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full.
+       [0:0]
+       
+        
+         inactive
+         No Interrupt is Pending.
+         0
+        
+        
+         pending
+         An interrupt is pending.
+         1
+        
+       
+      
+      
+       TX_UNDERFLOW
+       Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet).
+       [1:1]
+       
+        
+         inactive
+         No Interrupt is Pending.
+         0
+        
+        
+         pending
+         An interrupt is pending.
+         1
+        
+       
+      
+     
+    
+    
+     INT_EN1
+     Interrupt Staus Register 1.
+     0x14
+     read-write
+     
+      
+       RX_OVERFLOW
+       Receiver Overflow Interrupt Enable.
+       [0:0]
+       
+        
+         dis
+         No Interrupt is Pending.
+         0
+        
+        
+         en
+         An interrupt is pending.
+         1
+        
+       
+      
+      
+       TX_UNDERFLOW
+       Transmit Underflow Interrupt Enable.
+       [1:1]
+       
+        
+         dis
+         No Interrupt is Pending.
+         0
+        
+        
+         en
+         An interrupt is pending.
+         1
+        
+       
+      
+     
+    
+    
+     FIFO_LEN
+     FIFO Configuration Register.
+     0x18
+     
+      
+       RX_LEN
+       Receive FIFO Length.
+       [7:0]
+       read-only
+      
+      
+       TX_LEN
+       Transmit FIFO Length.
+       [15:8]
+       read-only
+      
+     
+    
+    
+     RX_CTRL0
+     Receive Control Register 0.
+     0x1C
+     
+      
+       DNR
+       Do Not Respond.
+       [0:0]
+       
+        
+         respond
+         Always respond to address match.
+         0
+        
+        
+         not_respond_rx_fifo_empty
+         Do not respond to address match when RX_FIFO is not empty.
+         1
+        
+       
+      
+      
+       RX_FLUSH
+       Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status.
+       [7:7]
+       
+        
+         not_flushed
+         FIFO not flushed.
+         0
+        
+        
+         flush
+         Flush RX_FIFO.
+         1
+        
+       
+      
+      
+       RX_THRESH
+       Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold.
+       [11:8]
+      
+     
+    
+    
+     RX_CTRL1
+     Receive Control Register 1.
+     0x20
+     
+      
+       RX_CNT
+       Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction.
+       [7:0]
+      
+      
+       RX_FIFO
+       Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0.
+       [11:8]
+       read-only
+      
+     
+    
+    
+     TX_CTRL0
+     Transmit Control Register 0.
+     0x24
+     
+      
+       TX_PRELOAD
+       Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match.
+       [0:0]
+      
+      
+       TX_READY_MODE
+       Transmit FIFO Ready Manual Mode.
+       [1:1]
+       
+        
+         en
+         HW control of I2CTXRDY enabled.
+         0
+        
+        
+         dis
+         HW control of I2CTXRDY disabled.
+         1
+        
+       
+      
+      
+       TX_FLUSH
+       Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation.
+       [7:7]
+       
+        
+         not_flushed
+         FIFO not flushed.
+         0
+        
+        
+         flush
+         Flush TX_FIFO.
+         1
+        
+       
+      
+      
+       TX_THRESH
+       Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold.
+       [11:8]
+      
+     
+    
+    
+     TX_CTRL1
+     Transmit Control Register 1.
+     0x28
+     
+      
+       TX_READY
+       Transmit FIFO Preload Ready.
+       [0:0]
+      
+      
+       TX_LAST
+       Transmit Last. This bit is used in slave mod only. Do not use when preloading (cleared by hardware).
+       [1:1]
+       
+        
+         hold_scl_low
+         Hold SCL low on TX_FIFO empty.
+         0
+        
+        
+         end_transaction
+         End transaction on TX_FIFO empty.
+         1
+        
+       
+      
+      
+       TX_FIFO
+       Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO.
+       [11:8]
+       read-only
+      
+     
+    
+    
+     FIFO
+     Data Register.
+     0x2C
+     
+      
+       DATA
+       Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location.
+       0
+       8
+      
+     
+    
+    
+     MASTER_CTRL
+     Master Control Register.
+     0x30
+     
+      
+       START
+       Setting this bit to 1 will start a master transfer.
+       [0:0]
+      
+      
+       RESTART
+       Setting this bit to 1 will generate a repeated START.
+       [1:1]
+      
+      
+       STOP
+       Setting this bit to 1 will generate a STOP condition.
+       [2:2]
+      
+      
+       SL_EX_ADDR
+       Slave Extend Address Select.
+       [7:7]
+       
+        
+         7_bits_address
+         7-bit address.
+         0
+        
+        
+         10_bits_address
+         10-bit address.
+         1
+        
+       
+      
+      
+       MASTER_CODE
+       Master Code. These bits set the Master Code used in Hs-mode operation.
+       [10:8]
+      
+      
+       SCL_SPEED_UP
+       Serial Clock speed Up. Setting this bit disables the master's monitoring of SCL state for other external masters or slaves.
+       [11:11]
+       
+        
+         en
+         Master monitors SCL state.
+         0
+        
+        
+         dis
+         SCL state monitoring disabled.
+         1
+        
+       
+      
+     
+    
+    
+     CLK_LO
+     Clock Low Register.
+     0x34
+     
+      
+       CLK_LO
+       Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted.
+       [8:0]
+      
+     
+    
+    
+     CLK_HI
+     Clock high Register.
+     0x38
+     
+      
+       CKH
+       Clock High. In master mode, these bits define the SCL high period.
+       [8:0]
+      
+     
+    
+    
+     HS_CLK
+     HS-Mode Clock Control Register
+     0x3C
+     
+      
+       HS_CLK_LO
+       Slave Address.
+       [7:0]
+      
+      
+       HS_CLK_HI
+       Slave Address.
+       [15:8]
+      
+     
+    
+    
+     TIMEOUT
+     Timeout Register
+     0x40
+     
+      
+       TO
+       Timeout
+       [15:0]
+      
+     
+    
+    
+     SLAVE_ADDR
+     Slave Address Register.
+     0x44
+     
+      
+       SLAVE_ADDR
+       Slave Address.
+       [9:0]
+      
+      
+       SLAVE_ADDR_DIS
+       Slave Address DIS.
+       [10:10]
+      
+      
+       SLAVE_ADDR_IDX
+       Slave Address Index.
+       [14:11]
+      
+      
+       EX_ADDR
+       Extended Address Select.
+       [15:15]
+       
+        
+         7_bits_address
+         7-bit address.
+         0
+        
+        
+         10_bits_address
+         10-bit address.
+         1
+        
+       
+      
+     
+    
+    
+     DMA
+     DMA Register.
+     0x48
+     
+      
+       TX_EN
+       TX channel enable.
+       [0:0]
+       
+        
+         dis
+         Disable.
+         0
+        
+        
+         en
+         Enable.
+         1
+        
+       
+      
+      
+       RX_EN
+       RX channel enable.
+       [1:1]
+       
+        
+         dis
+         Disable.
+         0
+        
+        
+         en
+         Enable.
+         1
+        
+       
+      
+     
+    
+   
+  
+
+  
+   I2C1
+   Inter-Integrated Circuit. 1
+   0x4001E000
+   
+    I2C1
+    I2C1 IRQ
+    36
+   
+  
+
+  
+   ICC0
+   Instruction Cache Controller Registers
+   0x4002A000
+   
+    0x00
+    0x1000
+    registers
+   
+   
+    
+     CACHE_ID
+     Cache ID Register.
+     0x0000
+     read-only
+     
+      
+       RELNUM
+       Release Number. Identifies the RTL release version.
+       0
+       6
+      
+      
+       PARTNUM
+       Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter.
+       6
+       4
+      
+      
+       CCHID
+       Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter.
+       10
+       6
+      
+     
+    
+    
+     MEMCFG
+     Memory Configuration Register.
+     0x0004
+     read-only
+     0x00080008
+     
+      
+       CCHSZ
+       Cache Size. Indicates total size in Kbytes of cache.
+       0
+       16
+      
+      
+       MEMSZ
+       Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller.
+       16
+       16
+      
+     
+    
+    
+     CACHE_CTRL
+     Cache Control and Status Register.
+     0x0100
+     
+      
+       CACHE_EN
+       Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated.
+       0
+       1
+       
+        
+         dis
+         Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array.
+         0
+        
+        
+         en
+         Cache Enabled.
+         1
+        
+       
+      
+      
+       CACHE_RDY
+       Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready.
+       16
+       1
+       read-only
+       
+        
+         notReady
+         Not Ready.
+         0
+        
+        
+         ready
+         Ready.
+         1
+        
+       
+      
+     
+    
+    
+     INVALIDATE
+     Invalidate All Registers.
+     0x0700
+     read-write
+    
+   
+  
+
+  
+   ICC1
+   Instruction Cache Controller Registers 1
+   0x4002F000
+  
+
+  
+   PWRSEQ
+   Power Sequencer / Low Power Control Register.
+   0x40006800
+   
+    0x00
+    0x800
+    registers
+   
+   
+    
+     LP_CTRL
+     Low Power Control Register.
+     0x00
+     
+      
+       RAMRET_SEL0
+       System RAM 0 Data retention in BACKUP mode. 
+       0
+       1
+       
+        
+         dis
+         Disabled.
+         0
+        
+        
+         en
+         Enabled.
+         1
+        
+       
+      
+      
+       RAMRET_SEL1
+       System RAM 1 Data retention in BACKUP mode. 
+       1
+       1
+       
+        
+         dis
+         Disabled.
+         0
+        
+        
+         en
+         Enabled.
+         1
+        
+       
+      
+      
+       RAMRET_SEL2
+       System RAM 2 Data retention in BACKUP mode. 
+       2
+       1
+       
+        
+         dis
+         Disabled.
+         0
+        
+        
+         en
+         Enabled.
+         1
+        
+       
+      
+      
+       RAMRET_SEL3
+       System RAM 3 Data retention in BACKUP mode. 
+       3
+       1
+       
+        
+         dis
+         Disabled.
+         0
+        
+        
+         en
+         Enabled.
+         1
+        
+       
+      
+      
+       OVR
+       Operating Voltage Range
+       4
+       2
+       
+        
+         0_9V
+         0.9V 24MHz
+         0
+        
+        
+         1_0V
+         1.0V 48MHz
+         1
+        
+        
+         1_1V
+         1.1V 96MHz
+         2
+        
+       
+      
+      
+       VCORE_DET_BYPASS
+       Bypass V CORE External Supply Detection
+       6
+       1
+       
+        
+         enabled
+         enable
+         0
+        
+        
+         Disable
+         disable
+         1
+        
+       
+      
+      
+       RETREG_EN
+       Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode. 
+       8
+       1
+       
+        
+         dis
+         Disabled.
+         0
+        
+        
+         en
+         Enabled.
+         1
+        
+       
+      
+      
+       FAST_WK_EN
+       Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. 
+       10
+       1
+       
+        
+         dis
+         Disabled.
+         0
+        
+        
+         en
+         Enabled.
+         1
+        
+       
+      
+      
+       BG_OFF
+       Band Gap Disable for DEEPSLEEP and BACKUP Mode
+       11
+       1
+       
+        
+         on
+         Bandgap is always ON.
+         0
+        
+        
+         off
+         Bandgap is OFF in DeepSleep mode(default).
+         1
+        
+       
+      
+      
+       VCORE_POR_DIS
+       V CORE POR Disable for DEEPSLEEP and BACKUP Mode
+       12
+       1
+       
+        
+         dis
+         Disabled.
+         0
+        
+        
+         en
+         Enabled.
+         1
+        
+       
+      
+      
+       LDO_DIS
+       LDO Disable
+       16
+       1
+       
+        
+         en
+         Enable if Bandgap is ON(default)
+         0
+        
+        
+         dis
+         Disabled.
+         1
+        
+       
+      
+      
+       VCORE_SVM_DIS
+       V CORE Supply Voltage Monitor Disable
+       20
+       1
+       
+        
+         en
+         Enable if Bandgap is ON(default)
+         0
+        
+        
+         dis
+         Disabled.
+         1
+        
+       
+      
+      
+       VDDIO_POR_DIS
+       VDDIO Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDIO supply in all operating mods.
+       25
+       1
+       
+        
+         en
+         Enabled.
+         0
+        
+        
+         dis
+         Disabled.
+         1
+        
+       
+      
+     
+    
+    
+     LP_WAKEFL
+     Low Power Mode Wakeup Flags for GPIO0
+     0x04
+     
+      
+       WAKEST
+       Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin(s) transition(s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.
+       0
+       14
+      
+     
+    
+    
+     LPWK_EN
+     Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0.
+     0x08
+     
+      
+       WAKEEN
+       Enable wakeup. These bits allow wakeup from the corresponding GPIO pin(s) on transition(s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.
+       0
+       14
+      
+     
+    
+    
+     LPMEMSD
+     Low Power Memory Shutdown Control.
+     0x40
+     
+      
+       SRAM0_OFF
+       System RAM block 0 Shut Down.
+       0
+       1
+       
+        
+         normal
+         Normal Operating Mode.
+         0
+        
+        
+         shutdown
+         Shutdown Mode.
+         1
+        
+       
+      
+      
+       SRAM1_OFF
+       System RAM block 1 Shut Down.
+       1
+       1
+       
+        
+         normal
+         Normal Operating Mode.
+         0
+        
+        
+         shutdown
+         Shutdown Mode.
+         1
+        
+       
+      
+      
+       SRAM2_OFF
+       System RAM block 2 Shut Down.
+       2
+       1
+       
+        
+         normal
+         Normal Operating Mode.
+         0
+        
+        
+         shutdown
+         Shutdown Mode.
+         1
+        
+       
+      
+      
+       SRAM3_OFF
+       System RAM block 3 Shut Down.
+       3
+       1
+       
+        
+         normal
+         Normal Operating Mode.
+         0
+        
+        
+         shutdown
+         Shutdown Mode.
+         1
+        
+       
+      
+     
+    
+   
+  
+
+  
+   RTC
+   Real Time Clock and Alarm.
+   0x40006000
+   
+    0x00
+    0x400
+    registers
+   
+   
+    RTC
+    RTC interrupt.
+    3
+   
+   
+    
+     SEC
+     RTC Second Counter. This register contains the 32-bit second counter.
+     0x00
+     0x00000000
+    
+    
+     SSEC
+     RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00.
+     0x04
+     0x00000000
+     
+      
+       RTSS
+       RTC Sub-second Counter.
+       0
+       8
+      
+     
+    
+    
+     RAS
+     Time-of-day Alarm.
+     0x08
+     0x00000000
+     
+      
+       RAS
+       Time-of-day Alarm.
+       0
+       20
+      
+     
+    
+    
+     RSSA
+     RTC sub-second alarm.  This register contains the reload value for the sub-second alarm.
+     0x0C
+     0x00000000
+     
+      
+       RSSA
+       This register contains the reload value for the sub-second alarm.
+       0
+       32
+      
+     
+    
+    
+     CTRL
+     RTC Control Register.
+     0x10
+     0x00000008
+     0xFFFFFF38
+     
+      
+       RTCE
+       Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0.
+       0
+       1
+       
+        
+         dis
+         Disable.
+         0
+        
+        
+         en
+         Enable.
+         1
+        
+       
+      
+      
+       ADE
+       Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.
+       1
+       1
+       
+        
+         dis
+         Disable.
+         0
+        
+        
+         en
+         Enable.
+         1
+        
+       
+      
+      
+       ASE
+       Alarm Sub-second Interrupt Enable.  Change to this bit is effective only after BUSY is cleared from 1 to 0.
+       2
+       1
+       
+        
+         dis
+         Disable.
+         0
+        
+        
+         en
+         Enable.
+         1
+        
+       
+      
+      
+       BUSY
+       RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place.  This bit is automatically cleared by hardware.
+       3
+       1
+       read-only
+       
+        
+         idle
+         Idle.
+         0
+        
+        
+         busy
+         Busy.
+         1
+        
+       
+      
+      
+       RDY
+       RTC Ready. This bit is set to 1 by hardware when the RTC count registers update.  It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register.
+       4
+       1
+       
+        
+         busy
+         Register has not updated.
+         0
+        
+        
+         ready
+         Ready.
+         1
+        
+       
+      
+      
+       RDYE
+       RTC Ready Interrupt Enable.
+       5
+       1
+       
+        
+         dis
+         Disable.
+         0
+        
+        
+         en
+         Enable.
+         1
+        
+       
+      
+      
+       ALDF
+       Time-of-Day Alarm Interrupt Flag.  This alarm is qualified as wake-up source to the processor.
+       6
+       1
+       read-only
+       
+        
+         inactive
+         Not active
+         0
+        
+        
+         Pending
+         Active
+         1
+        
+       
+      
+      
+       ALSF
+       Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.
+       7
+       1
+       read-only
+       
+        
+         inactive
+         Not active
+         0
+        
+        
+         Pending
+         Active
+         1
+        
+       
+      
+      
+       SQE
+       Square Wave Output Enable.
+       8
+       1
+       
+        
+         inactive
+         Not active
+         0
+        
+        
+         Pending
+         Active
+         1
+        
+       
+      
+      
+       FT
+       Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin.
+       9
+       2
+       
+        
+         freq1Hz
+         1 Hz (Compensated).
+         0
+        
+        
+         freq512Hz
+         512 Hz (Compensated).
+         1
+        
+        
+         freq4KHz
+         4 KHz.
+         2
+        
+        
+         clkDiv8
+         RTC Input Clock / 8.
+         3
+        
+       
+      
+      
+       X32KMD
+       32KHz Oscillator Mode.
+       11
+       2
+       
+        
+         noiseImmuneMode
+         Always operate in Noise Immune Mode.  Oscillator warm-up required.
+         0
+        
+        
+         quietMode
+         Always operate in Quiet Mode.  No oscillator warm-up required.
+         1
+        
+        
+         quietInStopWithWarmup
+         Operate in Noise Immune Mode normally, switch to Quiet Mode on Stop Mode entry.  Will wait for 32K oscillator warm-up before code execution on Stop Mode exit.
+         2
+        
+        
+         quietInStopNoWarmup
+         Operate in Noise Immune Mode normally, switch to Quiet Mode on Stop Mode entry.  Will not wait for 32K oscillator warm-up before code execution on Stop Mode exit.
+         3
+        
+       
+      
+      
+       WE
+       Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits.
+       15
+       1
+       
+        
+         inactive
+         Not active
+         0
+        
+        
+         Pending
+         Active
+         1
+        
+       
+      
+     
+    
+    
+     TRIM
+     RTC Trim Register.
+     0x14
+     0x00000000
+     
+      
+       TRIM
+       RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm.
+       0
+       8
+      
+      
+       VBATTMR
+       VBAT Timer Value. When RTC is running off of VBAT, this field is incremented every 32 seconds.
+       8
+       24
+      
+     
+    
+    
+     OSCCTRL
+     RTC Oscillator Control Register.
+     0x18
+     0x00000000
+     
+      
+       FLITER_EN
+       RTC Oscillator Filter Enable
+       0
+       1
+      
+      
+       IBIAS_SEL
+       RTC Oscillator 4X Bias Current Select
+       1
+       1
+       
+        
+         2X
+         Selects 2X bias current for RTC oscillator
+         0
+        
+        
+         4X
+         Selects 4X bias current for RTC oscillator
+         1
+        
+       
+      
+      
+       HYST_EN
+       RTC Oscillator Hysteresis Buffer Enable
+       2
+       1
+      
+      
+       IBIAS_EN
+       RTC Oscillator Bias Current Enable
+       3
+       1
+      
+      
+       BYPASS
+       RTC Crystal Bypass
+       4
+       1
+      
+      
+       OUT32K
+       RTC 32kHz Square Wave Output
+       5
+       1
+      
+     
+    
+   
+  
+
+  
+   SIR
+   System Initialization Registers.
+   0x40000400
+   read-only
+   
+    0x00
+    0x400
+    registers
+   
+   
+    
+     SISTAT
+     System Initialization Status Register.
+     0x00
+     read-only
+     
+      
+       MAGIC
+       Magic Word Validation.  This bit is set by the system initialization block following power-up.
+       0
+       1
+       read-only
+       
+        read
+        
+         magicNotSet
+         Magic word was not set (OTP has not been initialized properly).
+         0
+        
+        
+         magicSet
+         Magic word was set (OTP contains valid settings).
+         1
+        
+       
+      
+      
+       CRCERR
+       CRC Error Status.  This bit is set by the system initialization block following power-up.
+       1
+       1
+       read-only
+       
+        read
+        
+         noError
+         No CRC errors occurred during the read of the OTP memory block.
+         0
+        
+        
+         error
+         A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register.
+         1
+        
+       
+      
+     
+    
+    
+     ERRADDR
+     Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1).
+     0x04
+     read-only
+     
+      
+       ERRADDR
+       0
+       32
+      
+     
+    
+    
+     FSTAT
+     funcstat register.
+     0x100
+     read-only
+     
+      
+       FPU
+       FPU Function.
+       0
+       1
+       
+        
+         no
+         0
+        
+        
+         yes
+         1
+        
+       
+      
+      
+       USB
+       USB Device.
+       1
+       1
+       
+        
+         no
+         0
+        
+        
+         yes
+         1
+        
+       
+      
+      
+       ADC
+       10-bit Sigma Delta ADC.
+       2
+       1
+       
+        
+         no
+         0
+        
+        
+         yes
+         1
+        
+       
+      
+      
+       XIP
+       XiP function.
+       3
+       1
+       
+        
+         no
+         0
+        
+        
+         yes
+         1
+        
+       
+      
+      
+       PBM
+       PBM function.
+       4
+       1
+       
+        
+         no
+         0
+        
+        
+         yes
+         1
+        
+       
+      
+      
+       HBC
+       HBC function.
+       5
+       1
+       
+        
+         no
+         0
+        
+        
+         yes
+         1
+        
+       
+      
+      
+       SDHC
+       SDHC function.
+       6
+       1
+       
+        
+         no
+         0
+        
+        
+         yes
+         1
+        
+       
+      
+      
+       SMPHR
+       SMPHR function.
+       7
+       1
+       
+        
+         no
+         0
+        
+        
+         yes
+         1
+        
+       
+      
+      
+       SCACHE
+       System Cache function.
+       8
+       1
+       
+        
+         no
+         0
+        
+        
+         yes
+         1
+        
+       
+      
+     
+    
+    
+     SFSTAT
+     secfuncstat register.
+     0x104
+     read-only
+     
+      
+       TRNG
+       TRNG function.
+       2
+       1
+       
+        
+         no
+         0
+        
+        
+         yes
+         1
+        
+       
+      
+      
+       AES
+       AES function.
+       3
+       1
+       
+        
+         no
+         0
+        
+        
+         yes
+         1
+        
+       
+      
+      
+       SHA
+       SHA function.
+       4
+       1
+       
+        
+         no
+         0
+        
+        
+         yes
+         1
+        
+       
+      
+      
+       MAA
+       MAA function.
+       5
+       1
+       
+        
+         no
+         0
+        
+        
+         yes
+         1
+        
+       
+      
+     
+    
+   
+  
+
+  
+   SMON
+   The Security Monitor block used to monitor system threat conditions.
+   0x40004000
+   
+    0x00
+    0x1000
+    registers
+   
+   
+    
+     EXTSCN
+     External Sensor Control Register.
+     0x00
+     0x3800FFC0
+     
+      
+       EXTS_EN0
+       External Sensor Enable for input/output pair 0.
+       0
+       1
+       
+        
+         dis
+         Disable.
+         0
+        
+        
+         en
+         Enable.
+         1
+        
+       
+      
+      
+       EXTS_EN1
+       External Sensor Enable for input/output pair 1.
+       1
+       1
+       
+        
+         dis
+         Disable.
+         0
+        
+        
+         en
+         Enable.
+         1
+        
+       
+      
+      
+       EXTS_EN2
+       External Sensor Enable for input/output pair 2.
+       2
+       1
+       
+        
+         dis
+         Disable.
+         0
+        
+        
+         en
+         Enable.
+         1
+        
+       
+      
+      
+       EXTS_EN3
+       External Sensor Enable for input/output pair 3.
+       3
+       1
+       
+        
+         dis
+         Disable.
+         0
+        
+        
+         en
+         Enable.
+         1
+        
+       
+      
+      
+       EXTS_EN4
+       External Sensor Enable for input/output pair 4.
+       4
+       1
+       
+        
+         dis
+         Disable.
+         0
+        
+        
+         en
+         Enable.
+         1
+        
+       
+      
+      
+       EXTS_EN5
+       External Sensor Enable for input/output pair 5.
+       5
+       1
+       
+        
+         dis
+         Disable.
+         0
+        
+        
+         en
+         Enable.
+         1
+        
+       
+      
+      
+       EXTCNT
+       External Sensor Error Counter. These bits set the number of external sensor accepted mismatches that have to occur within a single bit period before an external sensor alarm is triggered.
+       16
+       5
+      
+      
+       EXTFRQ
+       External Sensor Frequency. These bits define the frequency at which the external sensors are clocked to/from the EXTS_IN and EXTS_OUT pair.
+       21
+       3
+       
+        
+         freq2000Hz
+         Div 4 (2000Hz).
+         0
+        
+        
+         freq1000Hz
+         Div 8 (1000Hz).
+         1
+        
+        
+         freq500Hz
+         Div 16 (500Hz).
+         2
+        
+        
+         freq250Hz
+         Div 32 (250Hz).
+         3
+        
+        
+         freq125Hz
+         Div 64 (125Hz).
+         4
+        
+        
+         freq63Hz
+         Div 128 (63Hz).
+         5
+        
+        
+         freq31Hz
+         Div 256 (31Hz).
+         6
+        
+        
+         RFU
+         Reserved. Do not use.
+         7
+        
+       
+      
+      
+       DIVCLK
+       Clock Divide.  These bits are used to divide the 8KHz input clock. The resulting divided clock is used for all logic within the Security Monitor Block. Note: If the input clock is divided with these bits, the error count threshold table and output frequency will be affected accordingly with the same divide factor.
+       24
+       3
+       
+        
+         div1
+         Divide by 1 (8000 Hz).
+         0
+        
+        
+         div2
+         Divide by 2 (4000 Hz).
+         1
+        
+        
+         div4
+         Divide by 4 (2000 Hz).
+         2
+        
+        
+         div8
+         Divide by 8 (1000 Hz).
+         3
+        
+        
+         div16
+         Divide by 16 (500 Hz).
+         4
+        
+        
+         div32
+         Divide by 32 (250 Hz).
+         5
+        
+        
+         div64
+         Divide by 64 (125 Hz).
+         6
+        
+       
+      
+      
+       BUSY
+       Busy. This bit is set to 1 by hardware after EXTSCN register is written to. This bit is automatically cleared to 0 after this register information has been transferred to the security monitor domain.
+       30
+       1
+       read-only
+       
+        
+         idle
+         Idle.
+         0
+        
+        
+         busy
+         Update in Progress.
+         1
+        
+       
+      
+      
+       LOCK
+       Lock Register. Once locked, the EXTSCN register can no longer be modified.  Only a battery disconnect will clear this bit. VBAT powers this register.
+       31
+       1
+       
+        
+         unlocked
+         Unlocked.
+         0
+        
+        
+         locked
+         Locked.
+         1
+        
+       
+      
+     
+    
+    
+     INTSCN
+     Internal Sensor Control Register.
+     0x04
+     0x7F00FFF7
+     
+      
+       SHIELD_EN
+       Die Shield Enable.
+       0
+       1
+       
+        
+         dis
+         Disable.
+         0
+        
+        
+         en
+         Enable.
+         1
+        
+       
+      
+      
+       TEMP_EN
+       Temperature Sensor Enable.
+       1
+       1
+       
+        
+         dis
+         Disable.
+         0
+        
+        
+         en
+         Enable.
+         1
+        
+       
+      
+      
+       VBAT_EN
+       Battery Monitor Enable.
+       2
+       1
+       
+        
+         dis
+         Disable.
+         0
+        
+        
+         en
+         Enable.
+         1
+        
+       
+      
+      
+       LOTEMP_SEL
+       Low Temperature Detection Select.
+       16
+       1
+       
+        
+         neg50C
+         -50 degrees C.
+         0
+        
+        
+         neg30C
+         -30 degrees C.
+         1
+        
+       
+      
+      
+       VCORELOEN
+       VCORE Undervoltage Detect Enable.
+       18
+       1
+       
+        
+         dis
+         Disable.
+         0
+        
+        
+         en
+         Enable.
+         1
+        
+       
+      
+      
+       VCOREHIEN
+       VCORE Overvoltage Detect Enable.
+       19
+       1
+       
+        
+         dis
+         Disable.
+         0
+        
+        
+         en
+         Enable.
+         1
+        
+       
+      
+      
+       VDDLOEN
+       VDD Undervoltage Detect Enable.
+       20
+       1
+       
+        
+         dis
+         Disable.
+         0
+        
+        
+         en
+         Enable.
+         1
+        
+       
+      
+      
+       VDDHIEN
+       VDD Overvoltage Detect Enable.
+       21
+       1
+       
+        
+         dis
+         Disable.
+         0
+        
+        
+         en
+         Enable.
+         1
+        
+       
+      
+      
+       VGLEN
+       Voltage Glitch Detection Enable.
+       22
+       1
+       
+        
+         dis
+         Disable.
+         0
+        
+        
+         en
+         Enable.
+         1
+        
+       
+      
+      
+       LOCK
+       Lock Register. Once locked, the INTSCN register can no longer be modified.  Only a battery disconnect will clear this bit. VBAT powers this register.
+       31
+       1
+       
+        
+         unlocked
+         Unlocked.
+         0
+        
+        
+         locked
+         Locked.
+         1
+        
+       
+      
+     
+    
+    
+     SECALM
+     Security Alarm Register.
+     0x08
+     0x00000000
+     0x00000000
+     
+      
+       DRS
+       Destructive Reset Trigger. Setting this bit will generate a DRS. This bit is self-cleared by hardware.
+       0
+       1
+       
+        
+         complete
+         No operation/complete.
+         0
+        
+        
+         start
+         Start operation.
+         1
+        
+       
+      
+      
+       KEYWIPE
+       Key Wipe Trigger. Set to 1 to initiate a wipe of the AES key register. It does not reset the part, or log a timestamp. AES and DES registers are not affected by this bit. This bit is automatically cleared to 0 after the keys have been wiped.
+       1
+       1
+       
+        
+         complete
+         No operation/complete.
+         0
+        
+        
+         start
+         Start operation.
+         1
+        
+       
+      
+      
+       SHIELDF
+       Die Shield Flag.
+       2
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       LOTEMP
+       Low Temperature Detect.
+       3
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       HITEMP
+       High Temperature Detect.
+       4
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       BATLO
+       Battery Undervoltage Detect.
+       5
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       BATHI
+       Battery Overvoltage Detect.
+       6
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       EXTF
+       External Sensor Flag.   This bit is set to 1 when any of the EXTSTAT bits are set.
+       7
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       VDDLO
+       VDD Undervoltage Detect Flag.
+       8
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       VCORELO
+       VCORE Undervoltage Detect Flag.
+       9
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       VCOREHI
+       VCORE Overvoltage Detect Flag.
+       10
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       VDDHI
+       VDD Overvoltage Flag.
+       11
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       VGL
+       Voltage Glitch Detection Flag.
+       12
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       EXTSTAT0
+       External Sensor 0 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.
+       16
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       EXTSTAT1
+       External Sensor 1 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.
+       17
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       EXTSTAT2
+       External Sensor 2 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.
+       18
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       EXTSTAT3
+       External Sensor 3 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.
+       19
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       EXTSTAT4
+       External Sensor 4 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.
+       20
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       EXTSTAT5
+       External Sensor 5 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.
+       21
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       EXTSWARN0
+       External Sensor 0 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.
+       24
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       EXTSWARN1
+       External Sensor 1 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.
+       25
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       EXTSWARN2
+       External Sensor 2 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.
+       26
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       EXTSWARN3
+       External Sensor 3 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.
+       27
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       EXTSWARN4
+       External Sensor 4 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.
+       28
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       EXTSWARN5
+       External Sensor 5 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.
+       29
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+     
+    
+    
+     SECDIAG
+     Security Diagnostic Register.
+     0x0C
+     read-only
+     0x00000001
+     0xFFC0FE02
+     
+      
+       BORF
+       Battery-On-Reset Flag. This bit is set once the back up battery is conneted.
+       0
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       SHIELDF
+       Die Shield Flag.
+       2
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       LOTEMP
+       Low Temperature Detect.
+       3
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       HITEMP
+       High Temperature Detect.
+       4
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       BATLO
+       Battery Undervoltage Detect.
+       5
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       BATHI
+       Battery Overvoltage Detect.
+       6
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       DYNF
+       Dynamic Sensor Flag.  This bit is set to 1 when any of the EXTSTAT bits are set.
+       7
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       AESKT
+       AES Key Transfer.  This bit is set to 1 when AES Key has been transferred from the TRNG to the battery backed AES key register. This bit can only be reset by a BOR.
+       8
+       1
+       
+        
+         incomplete
+         Key has not been transferred.
+         0
+        
+        
+         complete
+         Key has been transferred.
+         1
+        
+       
+      
+      
+       EXTSTAT0
+       External Sensor 0 Detect.
+       16
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       EXTSTAT1
+       External Sensor 1 Detect.
+       17
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       EXTSTAT2
+       External Sensor 2 Detect.
+       18
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       EXTSTAT3
+       External Sensor 3 Detect.
+       19
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       EXTSTAT4
+       External Sensor 4 Detect.
+       20
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       EXTSTAT5
+       External Sensor 5 Detect.
+       21
+       1
+       
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+     
+    
+    
+     DLRTC
+     DRS Log RTC Value. This register contains the 32 bit value in the RTC second register when the last DRS event occurred.
+     0x10
+     read-only
+     0x00000000
+     
+      
+       DLRTC
+       DRS Log RTC Value. This register contains the 32 bit value in the RTC second register when the last DRS event occured.
+       0
+       32
+      
+     
+    
+    
+     SECST
+     Security Monitor Status Register.
+     0x34
+     read-only
+     
+      
+       EXTSRS
+       External Sensor Control Register Status.
+       0
+       1
+       
+        
+         allowed
+         Access authorized.
+         0
+        
+        
+         notAllowed
+         Access not authorized.
+         1
+        
+       
+      
+      
+       INTSRS
+       Internal Sensor Control Register Status.
+       1
+       1
+       
+        
+         allowed
+         Access authorized.
+         0
+        
+        
+         notAllowed
+         Access not authorized.
+         1
+        
+       
+      
+      
+       SECALRS
+       Security Alarm Register Status.
+       2
+       1
+       
+        
+         allowed
+         Access authorized.
+         0
+        
+        
+         notAllowed
+         Access not authorized.
+         1
+        
+       
+      
+     
+    
+   
+  
+
+  
+   SPI17Y
+   SPI peripheral.
+   0x40046000
+   
+    0x00
+    0x1000
+    registers
+   
+   
+    SPI0
+    16
+   
+   
+    
+     DATA32
+     Register for reading and writing the FIFO.
+     0x00
+     32
+     read-write
+     
+      
+       DATA
+       Read to pull from RX FIFO, write to put into TX FIFO.
+       0
+       32
+      
+     
+    
+    
+     2
+     2
+     DATA16[%s]
+     Register for reading and writing the FIFO.
+     DATA32
+     0x00
+     16
+     read-write
+     
+      
+       DATA
+       Read to pull from RX FIFO, write to put into TX FIFO.
+       0
+       16
+      
+     
+    
+    
+     4
+     1
+     DATA8[%s]
+     Register for reading and writing the FIFO.
+     DATA32
+     0x00
+     8
+     read-write
+     
+      
+       DATA
+       Read to pull from RX FIFO, write to put into TX FIFO.
+       0
+       8
+      
+     
+    
+    
+     CTRL0
+     Register for controlling SPI peripheral.
+     0x04
+     read-write
+     
+      
+       EN
+       SPI Enable.
+       0
+       1
+       
+        
+         dis
+         SPI is disabled.
+         0
+        
+        
+         en
+         SPI is enabled.
+         1
+        
+       
+      
+      
+       MASTER
+       Master Mode Enable.
+       1
+       1
+       
+        
+         dis
+         SPI is Slave mode.
+         0
+        
+        
+         en
+         SPI is  Master mode.
+         1
+        
+       
+      
+      
+       SS_IO
+       Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode.
+       4
+       1
+       
+        
+         output
+         Slave select 0 is output.
+         0
+        
+        
+         input
+         Slave Select 0 is input, only valid if MMEN=1.
+         1
+        
+       
+      
+      
+       START
+       Start Transmit.
+       5
+       1
+       
+        
+         start
+         Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction.
+         1
+        
+       
+      
+      
+       SS_CTRL
+       Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction.
+       8
+       1
+       
+        
+         DEASSERT
+         SPI De-asserts Slave Select at the end of a transaction.
+         0
+        
+        
+         ASSERT
+         SPI leaves Slave Select asserted at the end of a transaction.
+         1
+        
+       
+      
+      
+       SS
+       Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected.
+       16
+       4
+       
+        
+         SS0
+         SS0 is selected.
+         0x1
+        
+        
+         SS1
+         SS1 is selected.
+         0x2
+        
+        
+         SS2
+         SS2 is selected.
+         0x4
+        
+        
+         SS3
+         SS3 is selected.
+         0x8
+        
+       
+      
+     
+    
+    
+     CTRL1
+     Register for controlling SPI peripheral.
+     0x08
+     read-write
+     
+      
+       TX_NUM_CHAR
+       Nubmer of Characters to transmit.
+       0
+       16
+      
+      
+       RX_NUM_CHAR
+       Nubmer of Characters to receive.
+       16
+       16
+      
+     
+    
+    
+     CTRL2
+     Register for controlling SPI peripheral.
+     0x0C
+     read-write
+     
+      
+       CPHA
+       Clock Phase.
+       0
+       1
+       
+        
+         Rising_Edge
+         Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 
+         0
+        
+        
+         Falling_Edge
+         Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3
+         1
+        
+       
+      
+      
+       CPOL
+       Clock Polarity.
+       1
+       1
+       
+        
+         Normal
+         Normal Clock. Use when in SPI Mode 0 and Mode 1
+         0
+        
+        
+         Inverted
+         Inverted Clock. Use when in SPI Mode 2 and Mode 3
+         1
+        
+       
+      
+      
+       SCLK_INV
+       Reserved - Must Always Be Cleared to 0.
+       4
+       1
+      
+      
+       NUMBITS
+       Number of Bits per character.
+       8
+       4
+       
+        
+         0
+         16 bits per character.
+         0
+        
+       
+      
+      
+       DATA_WIDTH
+       SPI Data width.
+       12
+       2
+       
+        
+         Mono
+         1 data pin.
+         0
+        
+        
+         Dual
+         2 data pins.
+         1
+        
+        
+         Quad
+         4 data pins.
+         2
+        
+       
+      
+      
+       THREE_WIRE
+       Three Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire.
+       15
+       1
+       
+        
+         dis
+         Use four wire mode (Mono only).
+         0
+        
+        
+         en
+         Use three wire mode.
+         1
+        
+       
+      
+      
+       SS_POL
+       Slave Select Polarity, each Slave Select can have unique polarity.
+       16
+       8
+       
+        
+         SS0_high
+         SS0 active high.
+         0x1
+        
+        
+         SS1_high
+         SS1 active high.
+         0x2
+        
+        
+         SS2_high
+         SS2 active high.
+         0x4
+        
+        
+         SS3_high
+         SS3 active high.
+         0x8
+        
+       
+      
+      
+       SRPOL
+       Slave Ready Polarity, each Slave Ready can have unique polarity.
+       24
+       8
+       
+        
+         SR0_high
+         SR0 active high.
+         0x1
+        
+        
+         SR1_high
+         SR1 active high.
+         0x2
+        
+        
+         SR2_high
+         SR2 active high.
+         0x4
+        
+        
+         SR3_high
+         SR3 active high.
+         0x8
+        
+        
+         SR4_high
+         SR4 active high.
+         0x10
+        
+        
+         SR5_high
+         SR5 active high.
+         0x20
+        
+        
+         SR6_high
+         SR6 active high.
+         0x40
+        
+        
+         SR7_high
+         SR7 active high.
+         0x80
+        
+       
+      
+     
+    
+    
+     SS_TIME
+     Register for controlling SPI peripheral/Slave Select Timing.
+     0x10
+     read-write
+     
+      
+       PRE
+       Slave Select Pre delay 1.
+       0
+       8
+       
+        
+         256
+         256 system clocks between SS active and first serial clock edge.
+         0
+        
+       
+      
+      
+       POST
+       Slave Select Post delay 2.
+       8
+       8
+       
+        
+         256
+         256 system clocks between last serial clock edge and SS inactive.
+         0
+        
+       
+      
+      
+       INACT
+       Slave Select Inactive delay.
+       16
+       8
+       
+        
+         256
+         256 system clocks between transactions.
+         0
+        
+       
+      
+     
+    
+    
+     CLK_CFG
+     Register for controlling SPI clock rate.
+     0x14
+     read-write
+     
+      
+       LO
+       Low duty cycle control. In timer mode, reload[7:0].
+       0
+       8
+       
+        
+         Dis
+         Duty cycle control of serial clock generation is disabled.
+         0
+        
+       
+      
+      
+       HI
+       High duty cycle control. In timer mode, reload[15:8].
+       8
+       8
+       
+        
+         Dis
+         Duty cycle control of serial clock generation is disabled.
+         0
+        
+       
+      
+      
+       SCALE
+       System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock.
+       16
+       4
+      
+     
+    
+    
+     DMA
+     Register for controlling DMA.
+     0x1C
+     read-write
+     
+      
+       TX_FIFO_LEVEL
+       Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered.
+       0
+       5
+      
+      
+       TX_FIFO_EN
+       Transmit FIFO enabled for SPI transactions.
+       6
+       1
+       
+        
+         dis
+         Transmit FIFO is not enabled.
+         0
+        
+        
+         en
+         Transmit FIFO is enabled.
+         1
+        
+       
+      
+      
+       TX_FIFO_CLEAR
+       Clear TX FIFO, clear is accomplished by resetting the read and write
+            pointers. This should be done when FIFO is not being accessed on the SPI side.
+          .
+       7
+       1
+       
+        
+         CLEAR
+         Clear the Transmit FIFO, clears any pending TX FIFO status.
+         1
+        
+       
+      
+      
+       TX_FIFO_CNT
+       Count of entries in TX FIFO.
+       8
+       6
+       read-only
+      
+      
+       TX_DMA_EN
+       TX DMA Enable.
+       15
+       1
+       
+        
+         DIS
+         TX DMA requests are disabled, andy pending DMA requests are cleared.
+         0
+        
+        
+         en
+         TX DMA requests are enabled.
+         1
+        
+       
+      
+      
+       RX_FIFO_LEVEL
+       Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered.
+       16
+       5
+      
+      
+       RX_FIFO_EN
+       Receive FIFO enabled for SPI transactions.
+       22
+       1
+       
+        
+         DIS
+         Receive FIFO is not enabled.
+         0
+        
+        
+         en
+         Receive FIFO is enabled.
+         1
+        
+       
+      
+      
+       RX_FIFO_CLEAR
+       Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.
+       23
+       1
+       
+        
+         CLEAR
+         Clear the Receive FIFO, clears any pending RX FIFO status.
+         1
+        
+       
+      
+      
+       RX_FIFO_CNT
+       Count of entries in RX FIFO.
+       24
+       6
+       read-only
+      
+      
+       RX_DMA_EN
+       RX DMA Enable.
+       31
+       1
+       
+        
+         dis
+         RX DMA requests are disabled, any pending DMA requests are cleared.
+         0
+        
+        
+         en
+         RX DMA requests are enabled.
+         1
+        
+       
+      
+     
+    
+    
+     INT_FL
+     Register for reading and clearing interrupt flags. All bits are write 1 to clear.
+     0x20
+     read-write
+     
+      
+       TX_THRESH
+       TX FIFO Threshold Crossed.
+       0
+       1
+       
+        
+         clear
+         Flag is set when value read is 1. Write 1 to clear this flag.
+         1
+        
+       
+      
+      
+       TX_EMPTY
+       TX FIFO Empty.
+       1
+       1
+       
+        
+         clear
+         Flag is set when value read is 1. Write 1 to clear this flag.
+         1
+        
+       
+      
+      
+       RX_THRESH
+       RX FIFO Threshold Crossed.
+       2
+       1
+       
+        
+         clear
+         Flag is set when value read is 1. Write 1 to clear this flag.
+         1
+        
+       
+      
+      
+       RX_FULL
+       RX FIFO FULL.
+       3
+       1
+       
+        
+         clear
+         Flag is set when value read is 1. Write 1 to clear this flag.
+         1
+        
+       
+      
+      
+       SSA
+       Slave Select Asserted.
+       4
+       1
+       
+        
+         clear
+         Flag is set when value read is 1. Write 1 to clear this flag.
+         1
+        
+       
+      
+      
+       SSD
+       Slave Select Deasserted.
+       5
+       1
+       
+        
+         clear
+         Flag is set when value read is 1. Write 1 to clear this flag.
+         1
+        
+       
+      
+      
+       FAULT
+       Multi-Master Mode Fault.
+       8
+       1
+       
+        
+         clear
+         Flag is set when value read is 1. Write 1 to clear this flag.
+         1
+        
+       
+      
+      
+       ABORT
+       Slave Abort Detected.
+       9
+       1
+       
+        
+         clear
+         Flag is set when value read is 1. Write 1 to clear this flag.
+         1
+        
+       
+      
+      
+       M_DONE
+       Master Done, set when SPI Master has completed any transactions.
+       11
+       1
+       
+        
+         clear
+         Flag is set when value read is 1. Write 1 to clear this flag.
+         1
+        
+       
+      
+      
+       TX_OVR
+       Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO.
+       12
+       1
+       
+        
+         clear
+         Flag is set when value read is 1. Write 1 to clear this flag.
+         1
+        
+       
+      
+      
+       TX_UND
+       Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO.
+       13
+       1
+       
+        
+         clear
+         Flag is set when value read is 1. Write 1 to clear this flag.
+         1
+        
+       
+      
+      
+       RX_OVR
+       Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.
+       14
+       1
+       
+        
+         clear
+         Flag is set when value read is 1. Write 1 to clear this flag.
+         1
+        
+       
+      
+      
+       RX_UND
+       Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.
+       15
+       1
+       
+        
+         clear
+         Flag is set when value read is 1. Write 1 to clear this flag.
+         1
+        
+       
+      
+     
+    
+    
+     INT_EN
+     Register for enabling interrupts.
+     0x24
+     read-write
+     
+      
+       TX_THRESH
+       TX FIFO Threshold interrupt enable.
+       0
+       1
+       
+        
+         dis
+         Interrupt is disabled.
+         0
+        
+        
+         en
+         Interrupt is enabled.
+         1
+        
+       
+      
+      
+       TX_EMPTY
+       TX FIFO Empty interrupt enable.
+       1
+       1
+       
+        
+         dis
+         Interrupt is disabled.
+         0
+        
+        
+         en
+         Interrupt is enabled.
+         1
+        
+       
+      
+      
+       RX_THRESH
+       RX FIFO Threshold Crossed interrupt enable.
+       2
+       1
+       
+        
+         dis
+         Interrupt is disabled.
+         0
+        
+        
+         en
+         Interrupt is enabled.
+         1
+        
+       
+      
+      
+       RX_FULL
+       RX FIFO FULL interrupt enable.
+       3
+       1
+       
+        
+         dis
+         Interrupt is disabled.
+         0
+        
+        
+         en
+         Interrupt is enabled.
+         1
+        
+       
+      
+      
+       SSA
+       Slave Select Asserted interrupt enable.
+       4
+       1
+       
+        
+         dis
+         Interrupt is disabled.
+         0
+        
+        
+         en
+         Interrupt is enabled.
+         1
+        
+       
+      
+      
+       SSD
+       Slave Select Deasserted interrupt enable.
+       5
+       1
+       
+        
+         dis
+         Interrupt is disabled.
+         0
+        
+        
+         en
+         Interrupt is enabled.
+         1
+        
+       
+      
+      
+       FAULT
+       Multi-Master Mode Fault interrupt enable.
+       8
+       1
+       
+        
+         dis
+         Interrupt is disabled.
+         0
+        
+        
+         en
+         Interrupt is enabled.
+         1
+        
+       
+      
+      
+       ABORT
+       Slave Abort Detected interrupt enable.
+       9
+       1
+       
+        
+         dis
+         Interrupt is disabled.
+         0
+        
+        
+         en
+         Interrupt is enabled.
+         1
+        
+       
+      
+      
+       M_DONE
+       Master Done interrupt enable.
+       11
+       1
+       
+        
+         dis
+         Interrupt is disabled.
+         0
+        
+        
+         en
+         Interrupt is enabled.
+         1
+        
+       
+      
+      
+       TX_OVR
+       Transmit FIFO Overrun interrupt enable.
+       12
+       1
+       
+        
+         dis
+         Interrupt is disabled.
+         0
+        
+        
+         en
+         Interrupt is enabled.
+         1
+        
+       
+      
+      
+       TX_UND
+       Transmit FIFO Underrun interrupt enable.
+       13
+       1
+       
+        
+         dis
+         Interrupt is disabled.
+         0
+        
+        
+         en
+         Interrupt is enabled.
+         1
+        
+       
+      
+      
+       RX_OVR
+       Receive FIFO Overrun interrupt enable.
+       14
+       1
+       
+        
+         dis
+         Interrupt is disabled.
+         0
+        
+        
+         en
+         Interrupt is enabled.
+         1
+        
+       
+      
+      
+       RX_UND
+       Receive FIFO Underrun interrupt enable.
+       15
+       1
+       
+        
+         dis
+         Interrupt is disabled.
+         0
+        
+        
+         en
+         Interrupt is enabled.
+         1
+        
+       
+      
+     
+    
+    
+     WAKE_FL
+     Register for wake up flags. All bits in this register are write 1 to clear.
+     0x28
+     read-write
+     
+      
+       TX_THRESH
+       Wake on TX FIFO Threshold Crossed.
+       0
+       1
+       
+        
+         clear
+         Flag is set when value read is 1. Write 1 to clear this flag.
+         1
+        
+       
+      
+      
+       TX_EMPTY
+       Wake on TX FIFO Empty.
+       1
+       1
+       
+        
+         clear
+         Flag is set when value read is 1. Write 1 to clear this flag.
+         1
+        
+       
+      
+      
+       RX_THRESH
+       Wake on RX FIFO Threshold Crossed.
+       2
+       1
+       
+        
+         clear
+         Flag is set when value read is 1. Write 1 to clear this flag.
+         1
+        
+       
+      
+      
+       RX_FULL
+       Wake on RX FIFO Full.
+       3
+       1
+       
+        
+         clear
+         Flag is set when value read is 1. Write 1 to clear this flag.
+         1
+        
+       
+      
+     
+    
+    
+     WAKE_EN
+     Register for wake up enable.
+     0x2C
+     read-write
+     
+      
+       TX_THRESH
+       Wake on TX FIFO Threshold Crossed Enable.
+       0
+       1
+       
+        
+         dis
+         Wakeup source disabled.
+         0
+        
+        
+         en
+         Wakeup source enabled.
+         1
+        
+       
+      
+      
+       TX_EMPTY
+       Wake on TX FIFO Empty Enable.
+       1
+       1
+       
+        
+         dis
+         Wakeup source disabled.
+         0
+        
+        
+         en
+         Wakeup source enabled.
+         1
+        
+       
+      
+      
+       RX_THRESH
+       Wake on RX FIFO Threshold Crossed Enable.
+       2
+       1
+       
+        
+         dis
+         Wakeup source disabled.
+         0
+        
+        
+         en
+         Wakeup source enabled.
+         1
+        
+       
+      
+      
+       RX_FULL
+       Wake on RX FIFO Full Enable.
+       3
+       1
+       
+        
+         dis
+         Wakeup source disabled.
+         0
+        
+        
+         en
+         Wakeup source enabled.
+         1
+        
+       
+      
+     
+    
+    
+     STAT
+     SPI Status register.
+     0x30
+     read-only
+     
+      
+       BUSY
+       SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. 
+       0
+       1
+       
+        
+         not
+         SPI not active.
+         0
+        
+        
+         active
+         SPI active.
+         1
+        
+       
+      
+     
+    
+   
+  
+
+  
+   SPIMSS
+   Serial Peripheral Interface.
+   SPIMSS0_
+   0x40018000
+   
+    0x00
+    0x1000
+    registers
+   
+   
+    
+     DATA16
+     SPI 16-bit Data Access
+     0x00
+     16
+     read-write
+     
+      
+       DATA
+       SPI data.
+       0
+       16
+      
+     
+    
+    
+     2
+     1
+     DATA8[%s]
+     SPI Data 8-bit access
+     DATA16
+     0x00
+     8
+     read-write
+     
+      
+       DATA
+       SPI data.
+       0
+       8
+      
+     
+    
+    
+     CTRL
+     SPI Control Register.
+     0x04
+     
+      
+       SPIEN
+       SPI Enable.
+       0
+       1
+       
+        dis_en_enum
+        
+         disable
+         0
+        
+        
+         enable
+         1
+        
+       
+      
+      
+       MMEN
+       SPI Master Mode Enable.
+       1
+       1
+       
+        slv_mst_enum
+        
+         slave
+         0
+        
+        
+         master
+         1
+        
+       
+      
+      
+       WOR
+       Wired OR (open drain) Enable.
+       2
+       1
+       
+        dis_en_enum
+        
+         disable
+         0
+        
+        
+         enable
+         1
+        
+       
+      
+      
+       CLKPOL
+       Clock Polarity.
+       3
+       1
+       
+        spi_pol_enum
+        
+         idleLo
+         SCLK idles Low (0) after character transmission/reception.
+         0
+        
+        
+         idleHi
+         SCLK idles High (1) after character transmission/reception.
+         1
+        
+       
+      
+      
+       PHASE
+       Phase Select.
+       4
+       1
+       
+        spi_phase_enum
+        
+         activeEdge
+         Transmit on active edge of SCLK.
+         0
+        
+        
+         inactiveEdge
+         Transmit on inactive edge of SCLK.
+         1
+        
+       
+      
+      
+       BIRQ
+       Baud Rate Generator Timer Interrupt Request.
+       5
+       1
+       
+        dis_en_enum
+        
+         disable
+         0
+        
+        
+         enable
+         1
+        
+       
+      
+      
+       STR
+       Start SPI Interrupt.
+       6
+       1
+       
+        start_op_enum
+        
+         complete
+         No operation/complete.
+         0
+        
+        
+         start
+         Start operation.
+         1
+        
+       
+      
+      
+       IRQE
+       Interrupt Request Enable.
+       7
+       1
+       
+        dis_en_enum
+        
+         disable
+         0
+        
+        
+         enable
+         1
+        
+       
+      
+     
+    
+    
+     STATUS
+     SPI Status Register.
+     0x08
+     0x00000001
+     
+      
+       SLAS
+       Slave Select. If the SPI is in slave mode, this bit indicates if the SPI is selected. If the SPI is in master mode this bit has no meaning.
+       0
+       1
+       read-only
+       
+        sel_enum
+        
+         selected
+         0
+        
+        
+         notSelected
+         1
+        
+       
+      
+      
+       TXST
+       Transmit Status.
+       1
+       1
+       read-only
+       
+        busy_enum
+        
+         idle
+         0
+        
+        
+         busy
+         1
+        
+       
+      
+      
+       TUND
+       Transmit Underrun.
+       2
+       1
+       oneToClear
+       
+        event_flag_enum
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       ROVR
+       Receive Overrun.
+       3
+       1
+       
+        event_flag_enum
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       ABT
+       Slave Mode Transaction Abort.
+       4
+       1
+       
+        event_flag_enum
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       COL
+       Collision.
+       5
+       1
+       
+        event_flag_enum
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       TOVR
+       Transmit Overrun.
+       6
+       1
+       
+        event_flag_enum
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+      
+       IRQ
+       SPI Interrupt Request.
+       7
+       1
+       oneToClear
+       
+        flag_enum
+        
+         inactive
+         No interrupt is pending.
+         0
+        
+        
+         pending
+         An interrupt is pending.
+         1
+        
+       
+      
+     
+    
+    
+     MOD
+     SPI Mode Register.
+     0x0C
+     
+      
+       SSV
+       Slave Select Value.
+       0
+       1
+       
+        lo_hi_enum
+        
+         lo
+         The SSEL pin will be driven low.
+         0
+        
+        
+         hi
+         The SSEL pin will be driven high.
+         1
+        
+       
+      
+      
+       SSIO
+       Slave Select I/O.
+       1
+       1
+       
+        input_output_enum
+        
+         input
+         0
+        
+        
+         output
+         1
+        
+       
+      
+      
+       NUMBITS
+       2
+       4
+       
+        spi_bits_enum
+        
+         bits16
+         0
+        
+        
+         bits1
+         1
+        
+        
+         bits2
+         2
+        
+        
+         bits3
+         3
+        
+        
+         bits4
+         4
+        
+        
+         bits5
+         5
+        
+        
+         bits6
+         6
+        
+        
+         bits7
+         7
+        
+        
+         bits8
+         8
+        
+        
+         bits9
+         9
+        
+        
+         bits10
+         10
+        
+        
+         bits11
+         11
+        
+        
+         bits12
+         12
+        
+        
+         bits13
+         13
+        
+        
+         bits14
+         14
+        
+        
+         bits15
+         15
+        
+       
+      
+      
+       TX_LJ
+       Transmit Left Justify.
+       7
+       1
+       
+        dis_en_enum
+        
+         disable
+         0
+        
+        
+         enable
+         1
+        
+       
+      
+      
+       SSL1
+       Slave Select 1.  If SPI is enabled and in master mode, the SSEL_1 is driven according to this bit.
+       8
+       1
+       
+        hi_lo_enum
+        
+         hi
+         High.
+         0
+        
+        
+         lo
+         Low.
+         1
+        
+       
+      
+      
+       SSL2
+       Slave Select 2.  If SPI is enabled and in master mode, the SSEL_2 is driven according to this bit.
+       9
+       1
+       
+        hi_lo_enum
+        
+         hi
+         High.
+         0
+        
+        
+         lo
+         Low.
+         1
+        
+       
+      
+      
+       SSL3
+       Slave Select 3.  If SPI is enabled and in master mode, the SSEL_3 is driven according to this bit.
+       10
+       1
+       
+        hi_lo_enum
+        
+         hi
+         High.
+         0
+        
+        
+         lo
+         Low.
+         1
+        
+       
+      
+     
+    
+    
+     BRG
+     Baud Rate Reload Value. The SPI Baud Rate register is a 16-bit reload value for the SPI Baud Rate Generator. The reload value must be greater than or equal to 0002H for proper SPI operation (maximum baud rate is PCLK frequency divided by 4).
+     0x14
+     0x0000FFFF
+     
+      
+       BRG
+       Baud Rate Reload Value.
+       0
+       16
+      
+     
+    
+    
+     DMA
+     SPI DMA Register.
+     0x18
+     0x00070007
+     
+      
+       TX_FIFO_LEVEL
+       Transmit FIFO Level. Set the number of free entries in the TxFIFO when a TxDMA request occurs.
+       0
+       3
+       
+        fifo_level_enum
+        
+         entry1
+         0
+        
+        
+         entries2
+         1
+        
+        
+         entries3
+         2
+        
+        
+         entries4
+         3
+        
+        
+         entries5
+         4
+        
+        
+         entries6
+         5
+        
+        
+         entries7
+         6
+        
+        
+         entries8
+         7
+        
+       
+      
+      
+       TX_FIFO_CLEAR
+       Transmit FIFO Clear.
+       4
+       1
+       write-only
+       
+        start_op_enum
+        
+         complete
+         No operation/complete.
+         0
+        
+        
+         start
+         Start operation.
+         1
+        
+       
+      
+      
+       TX_FIFO_CNT
+       Transmit FIFO Count.
+       8
+       4
+       read-only
+      
+      
+       TX_DMA_EN
+       Transmit DMA Enable.
+       15
+       1
+       
+        dis_en_enum
+        
+         disable
+         0
+        
+        
+         enable
+         1
+        
+       
+      
+      
+       RX_FIFO_LEVEL
+       Receive FIFO Level. Sets the RX FIFO DMA request threshold. This configures the number of filled RxFIFO entries before activating an RxDMA request.
+       16
+       3
+       
+        fifo_level_enum
+        
+         entry1
+         0
+        
+        
+         entries2
+         1
+        
+        
+         entries3
+         2
+        
+        
+         entries4
+         3
+        
+        
+         entries5
+         4
+        
+        
+         entries6
+         5
+        
+        
+         entries7
+         6
+        
+        
+         entries8
+         7
+        
+       
+      
+      
+       RX_FIFO_CLEAR
+       Receive FIFO Clear.
+       20
+       1
+       
+        start_op_enum
+        
+         complete
+         No operation/complete.
+         0
+        
+        
+         start
+         Start operation.
+         1
+        
+       
+      
+      
+       RX_FIFO_CNT
+       Receive FIFO Count.
+       24
+       4
+       read-only
+      
+      
+       RX_DMA_EN
+       Receive DMA Enable.
+       31
+       1
+       
+        dis_en_enum
+        
+         disable
+         0
+        
+        
+         enable
+         1
+        
+       
+      
+     
+    
+    
+     I2S_CTRL
+     I2S Control Register.
+     0x1C
+     
+      
+       I2S_EN
+       I2S Mode Enable.
+       0
+       1
+       
+        dis_en_enum
+        
+         disable
+         0
+        
+        
+         enable
+         1
+        
+       
+      
+      
+       I2S_MUTE
+       I2S Mute transmit.
+       1
+       1
+       
+        
+         normal
+         Normal Transmit.
+         0
+        
+        
+         replaced
+         Transmit data is replaced with 0.
+         1
+        
+       
+      
+      
+       I2S_PAUSE
+       I2S Pause transmit/receive.
+       2
+       1
+       
+        
+         normal
+         Normal Transmit.
+         0
+        
+        
+         halt
+         Halt transmit and receive FIFO and DMA access, transmit 0's.
+         1
+        
+       
+      
+      
+       I2S_MONO
+       I2S Monophonic Audio Mode.
+       3
+       1
+       
+        
+         stereophonic
+         Stereophonic audio.
+         0
+        
+        
+         monophonic
+         Monophonic audio format.Each transmit data word is replicated on both left/right channels. Receive data is taken from left channel, right channel receive data is ignored.
+         1
+        
+       
+      
+      
+       I2S_LJ
+       I2S Left Justify.
+       4
+       1
+       
+        
+         normal
+         Normal I2S audio protocol.
+         0
+        
+        
+         replaced
+         Audio data is synchronized with SSEL.
+         1
+        
+       
+      
+     
+    
+   
+  
+
+  
+   TMR0
+   32-bit reloadable timer that can be used for timing and event counting.
+   Timers
+   0x40010000
+   
+    0x00
+    0x1000
+    registers
+   
+   
+    TMR0
+    TMR0 IRQ
+    5
+   
+   
+    
+     CNT
+     Count.  This register stores the current timer count.
+     0x00
+     0x00000001
+    
+    
+     CMP
+     Compare.  This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001.
+     0x04
+     0x0000FFFF
+    
+    
+     PWM
+     PWM.  This register stores the value that is compared to the current timer count.
+     0x08
+    
+    
+     INTR
+     Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt.
+     0x0C
+     oneToClear
+     
+      
+       IRQ_CLR
+       Clear Interrupt.
+       0
+       1
+      
+     
+    
+    
+     CN
+     Timer Control Register.
+     0x10
+     
+      
+       TMODE
+       Timer Mode.
+       0
+       3
+       
+        
+         oneShot
+         One Shot Mode.
+         0
+        
+        
+         continuous
+         Continuous Mode.
+         1
+        
+        
+         counter
+         Counter Mode.
+         2
+        
+        
+         pwm
+         PWM Mode.
+         3
+        
+        
+         capture
+         Capture Mode.
+         4
+        
+        
+         compare
+         Compare Mode.
+         5
+        
+        
+         gated
+         Gated Mode.
+         6
+        
+        
+         captureCompare
+         Capture/Compare Mode.
+         7
+        
+       
+      
+      
+       PRES
+       Prescaler.  Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0].
+       3
+       3
+       
+        
+         div1
+         Divide by 1.
+         0
+        
+        
+         div2
+         Divide by 2.
+         1
+        
+        
+         div4
+         Divide by 4.
+         2
+        
+        
+         div8
+         Divide by 8.
+         3
+        
+        
+         div16
+         Divide by 16.
+         4
+        
+        
+         div32
+         Divide by 32.
+         5
+        
+        
+         div64
+         Divide by 64.
+         6
+        
+        
+         div128
+         Divide by 128.
+         7
+        
+       
+      
+      
+       TPOL
+       Timer input/output polarity bit.
+       6
+       1
+       
+        
+         activeHi
+         Active High.
+         0
+        
+        
+         activeLo
+         Active Low.
+         1
+        
+       
+      
+      
+       TEN
+       Timer Enable.
+       7
+       1
+       
+        
+         dis
+         Disable.
+         0
+        
+        
+         en
+         Enable.
+         1
+        
+       
+      
+      
+       PRES3
+       MSB of prescaler value.
+       8
+       1
+      
+      
+       PWMSYNC
+       Timer PWM Synchronization Mode Enable.
+       9
+       1
+       
+        
+         dis
+         Disable.
+         0
+        
+        
+         en
+         Enable.
+         1
+        
+       
+      
+      
+       NOLHPOL
+       Timer PWM output 0A polarity bit.
+       10
+       1
+       
+        
+         dis
+         Disable.
+         0
+        
+        
+         en
+         Enable.
+         1
+        
+       
+      
+      
+       NOLLPOL
+       Timer PWM output 0A' polarity bit.
+       11
+       1
+       
+        
+         dis
+         Disable.
+         0
+        
+        
+         en
+         Enable.
+         1
+        
+       
+      
+      
+       PWMCKBD
+       Timer PWM output 0A Mode Disable.
+       12
+       1
+       
+        
+         dis
+         Disable.
+         1
+        
+        
+         en
+         Enable.
+         0
+        
+       
+      
+     
+    
+    
+     NOLCMP
+     Timer Non-Overlapping Compare Register.
+     0x14
+     
+      
+       NOLLCMP
+       Non-overlapping Low Compare.  The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'.
+       0
+       8
+      
+      
+       NOLHCMP
+       Non-overlapping High Compare.  The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A.
+       8
+       8
+      
+     
+    
+   
+  
+
+  
+   TMR1
+   32-bit reloadable timer that can be used for timing and event counting. 1
+   0x40011000
+   
+    TMR1
+    TMR1 IRQ
+    6
+   
+  
+
+  
+   TMR2
+   32-bit reloadable timer that can be used for timing and event counting. 2
+   0x40012000
+   
+    TMR2
+    TMR2 IRQ
+    7
+   
+  
+
+  
+   UART0
+   UART
+   0x40042000
+   
+    0
+    0x1000
+    registers
+   
+   
+    UART0
+    UART0 IRQ
+    14
+   
+   
+    
+     CTRL
+     Control Register.
+     0x00
+     32
+     
+      
+       ENABLE
+       UART enabled, to enable UART block, it is used to drive a gated clock in order to save power consumption when UART is not used. FIFOs are flushed when UART is disabled.
+       0
+       1
+       
+        
+         dis
+         UART disabled. FIFOs are flushed. Clock is gated off for power savings. 
+         0
+        
+        
+         en
+         UART enabled. 
+         1
+        
+       
+      
+      
+       PARITY_EN
+       Enable/disable Parity bit (9th character).
+       1
+       1
+       
+        
+         dis
+         No Parity 
+         0
+        
+        
+         en
+         Parity enabled as 9th bit
+         1
+        
+       
+      
+      
+       PARITY
+       When PARITY_EN=1, selects odd, even, Mark or Space parity.
+            Mark parity = always 1; Space parity = always 0.
+       2
+       2
+       
+        
+         Even
+         Even parity selected.
+         0
+        
+        
+         ODD
+         Odd parity selected.
+         1
+        
+        
+         MARK
+         Mark parity selected.
+         2
+        
+        
+         SPACE
+         Space parity selected.
+         3
+        
+       
+      
+      
+       PARMD
+       Selects parity based on 1s or 0s count (when PARITY_EN=1).
+       4
+       1
+       
+        
+         1
+         Parity calculation is based on number of 1s in frame.
+         0
+        
+        
+         0
+         Parity calculation is based on number of 0s in frame.
+         1
+        
+       
+      
+      
+       TX_FLUSH
+       Flushes the TX FIFO buffer.
+       5
+       1
+      
+      
+       RX_FLUSH
+       Flushes the RX FIFO buffer.
+       6
+       1
+      
+      
+       BITACC
+       If set, bit accuracy is selected, in this case the bit duration is the same for all the bits with the optimal accuracy. But the frame duration can have a significant deviation from the expected baudrate.If clear, frame accuracy is selected, therefore bits can have different duration in order to guarantee the minimum frame deviation.
+       7
+       1
+       
+        
+         FRAME
+         Frame accuracy.
+         0
+        
+        
+         BIT
+         Bit accuracy.
+         1
+        
+       
+      
+      
+       CHAR_SIZE
+       Selects UART character size.
+       8
+       2
+       
+        
+         5
+         5 bits.
+         0
+        
+        
+         6
+         6 bits.
+         1
+        
+        
+         7
+         7 bits.
+         2
+        
+        
+         8
+         8 bits.
+         3
+        
+       
+      
+      
+       STOPBITS
+       Selects the number of stop bits that will be generated.
+       10
+       1
+       
+        
+         1
+         1 stop bit.
+         0
+        
+        
+         1_5
+         1.5 stop bits.
+         1
+        
+       
+      
+      
+       FLOW_CTRL
+       Enables/disables hardware flow control.
+       11
+       1
+       
+        
+         en
+         HW Flow Control with RTS/CTS enabled
+         1
+        
+        
+         dis
+         HW Flow Control disabled
+         0
+        
+       
+      
+      
+       FLOW_POL
+       RTS/CTS polarity.
+       12
+       1
+       
+        
+         0
+         RTS/CTS asserted is logic 0.
+         0
+        
+        
+         1
+         RTS/CTS asserted is logic 1.
+         1
+        
+       
+      
+      
+       NULL_MODEM
+       NULL Modem Support (RTS/CTS and TXD/RXD swap).
+       13
+       1
+       
+        
+         DIS
+         Direct convention.
+         0
+        
+        
+         EN
+         Null Modem Mode.
+         1
+        
+       
+      
+      
+       BREAK
+       Break control bit. It causes a break condition to be transmitted to receiving UART.
+       14
+       1
+       
+        
+         DIS
+         Break characters are not generated.
+         0
+        
+        
+         EN
+         Break characters are sent(all the bits are at '0' including start/parity/stop).
+         1
+        
+       
+      
+      
+       CLKSEL
+       Baud Rate Clock Source Select.  Selects the baud rate clock.
+       15
+       1
+       
+        
+         SYSTEM
+         System clock.
+         0
+        
+        
+         ALTERNATE
+         Alternate 7.3727MHz internal clock.  Useful in low power modes when the system clock is slow.
+         1
+        
+       
+      
+      
+       RX_TO
+       RX Time Out. RX time out interrupt will occur after RXTO Uart
+              characters if RX-FIFO is not empty and RX FIFO has not been read.
+       16
+       8
+      
+     
+    
+    
+     THRESH_CTRL
+     Threshold Control register.
+     0x04
+     32
+     
+      
+       RX_FIFO_THRESH
+       RX FIFO Threshold Level.When the RX FIFO reaches this many bytes or higher, UARTn_INFTL.rx_fifo_level is set.
+       0
+       6
+      
+      
+       TX_FIFO_THRESH
+       TX FIFO Threshold Level. When the TX FIFO reaches this many bytes or higher, UARTn_INTFL.tx_fifo_level is set.
+       8
+       6
+      
+      
+       RTS_FIFO_THRESH
+       RTS threshold control. When the RX FIFO reaches this many bytes or higher, the RTS output signal is deasserted, informing the transmitting UART to stop sending data to this UART.
+       16
+       6
+      
+     
+    
+    
+     STATUS
+     Status Register.
+     0x08
+     32
+     read-only
+     
+      
+       TX_BUSY
+       Read-only flag indicating the UART transmit status.
+       0
+       1
+       read-only
+      
+      
+       RX_BUSY
+       Read-only flag indicating the UARTreceiver status.
+       1
+       1
+       read-only
+      
+      
+       PARITY
+       9th Received bit state. This bit identifies the state of the 9th bit of received data. Only available for UART_CTRL.SIZE[1:0]=3.
+       2
+       1
+       read-only
+      
+      
+       BREAK
+       Received BREAK status. BREAKS is cleared when UART_STAT register is read. Received data input is held in spacing (logic 0) state for longer than a full word transmission time (that is, the total time of Start bit + data bits + Parity + Stop bits).
+       3
+       1
+       read-only
+      
+      
+       RX_EMPTY
+       Read-only flag indicating the RX FIFO state.
+       4
+       1
+       read-only
+      
+      
+       RX_FULL
+       Read-only flag indicating the RX FIFO state.
+       5
+       1
+       read-only
+      
+      
+       TX_EMPTY
+       Read-only flag indicating the TX FIFO state.
+       6
+       1
+       read-only
+      
+      
+       TX_FULL
+       Read-only flag indicating the TX FIFO state.
+       7
+       1
+       read-only
+      
+      
+       RX_FIFO_CNT
+       Indicates the number of bytes currently in the RX FIFO.
+       8
+       6
+       read-only
+      
+      
+       TX_FIFO_CNT
+       Indicates the number of bytes currently in the TX FIFO.
+       16
+       6
+       read-only
+      
+      
+       RX_TO
+       RX Timeout status.
+       24
+       1
+       read-only
+      
+     
+    
+    
+     INT_EN
+     Interrupt Enable Register.
+     0x0C
+     32
+     
+      
+       RX_FRAME_ERROR
+       Enable for RX Frame Error Interrupt.
+       0
+       1
+      
+      
+       RX_PARITY_ERROR
+       Enable for RX Parity Error interrupt.
+       1
+       1
+      
+      
+       CTS_CHANGE
+       Enable for CTS signal change interrupt.
+       2
+       1
+      
+      
+       RX_OVERRUN
+       Enable for RX FIFO OVerrun interrupt.
+       3
+       1
+      
+      
+       RX_FIFO_THRESH
+       Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.
+       4
+       1
+      
+      
+       TX_FIFO_ALMOST_EMPTY
+       Enable for interrupt when TX FIFO has only one byte remaining.
+       5
+       1
+      
+      
+       TX_FIFO_THRESH
+       Enable for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field.
+       6
+       1
+      
+      
+       BREAK
+       Enable for received BREAK character interrupt.
+       7
+       1
+      
+      
+       RX_TIMEOUT
+       Enable for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO).
+       8
+       1
+      
+      
+       LAST_BREAK
+       Enable for Last break character interrupt.
+       9
+       1
+      
+     
+    
+    
+     INT_FL
+     Interrupt Status Flags.
+     0x10
+     32
+     oneToClear
+     
+      
+       RX_FRAME_ERROR
+       FLAG for RX Frame Error Interrupt.
+       0
+       1
+      
+      
+       RX_PARITY_ERROR
+       FLAG for RX Parity Error interrupt.
+       1
+       1
+      
+      
+       CTS_CHANGE
+       FLAG for CTS signal change interrupt.
+       2
+       1
+      
+      
+       RX_OVERRUN
+       FLAG for RX FIFO Overrun interrupt.
+       3
+       1
+      
+      
+       RX_FIFO_THRESH
+       FLAG for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.
+       4
+       1
+      
+      
+       TX_FIFO_ALMOST_EMPTY
+       FLAG for interrupt when TX FIFO has only one byte remaining.
+       5
+       1
+      
+      
+       TX_FIFO_THRESH
+       FLAG for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field.
+       6
+       1
+      
+      
+       BREAK
+       FLAG for received BREAK character interrupt.
+       7
+       1
+      
+      
+       RX_TIMEOUT
+       FLAG for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO).
+       8
+       1
+      
+      
+       LAST_BREAK
+       FLAG for Last break character interrupt.
+       9
+       1
+      
+     
+    
+    
+     BAUD0
+     Baud rate register. Integer portion.
+     0x14
+     32
+     
+      
+       IBAUD
+       Integer portion of baud rate divisor value. IBAUD = InputClock / (factor * Baud Rate Frequency).
+       0
+       12
+      
+      
+       FACTOR
+       FACTOR must be chosen to have IDIV>0. factor used in calculation = 128 >> FACTOR.
+       16
+       2
+       
+        
+         128
+         Baud Factor 128
+         0
+        
+        
+         64
+         Baud Factor 64
+         1
+        
+        
+         32
+         Baud Factor 32
+         2
+        
+        
+         16
+         Baud Factor 16
+         3
+        
+       
+      
+     
+    
+    
+     BAUD1
+     Baud rate register. Decimal Setting.
+     0x18
+     32
+     
+      
+       DBAUD
+       Decimal portion of baud rate divisor value. DIV = InputClock/(factor*Baud Rate Frequency). DDIV=(DIV-IDIV)*128.
+       0
+       12
+      
+     
+    
+    
+     FIFO
+     FIFO Data buffer.
+     0x1C
+     32
+     
+      
+       FIFO
+       Load/unload location for TX and RX FIFO buffers.
+       0
+       8
+      
+     
+    
+    
+     DMA
+     DMA Configuration.
+     0x20
+     32
+     
+      
+       TDMA_EN
+       TX DMA channel enable.
+       0
+       1
+       
+        
+         dis
+         DMA is disabled 
+         0
+        
+        
+         en
+         DMA is enabled 
+         1
+        
+       
+      
+      
+       RXDMA_EN
+       RX DMA channel enable.
+       1
+       1
+       
+        
+         dis
+         DMA is disabled 
+         0
+        
+        
+         en
+         DMA is enabled 
+         1
+        
+       
+      
+      
+       TXDMA_LEVEL
+       TX threshold for DMA transmission.
+       8
+       6
+      
+      
+       RXDMA_LEVEL
+       RX threshold for DMA transmission.
+       16
+       6
+      
+     
+    
+    
+     TX_FIFO
+     Transmit FIFO Status register.
+     0x24
+     32
+     
+      
+       DATA
+       Reading from this field returns the next character available at the
+              output of the TX FIFO (if one is available, otherwise 00h is returned).
+       0
+       7
+      
+     
+    
+   
+  
+
+  
+   UART1
+   UART 1
+   0x40043000
+   
+    UART1
+    UART1 IRQ
+    15
+   
+  
+
+  
+   WDT0
+   Watchdog Timer 0
+   0x40003000
+   
+    0x00
+    0x0400
+    registers
+   
+   
+    WDT0
+    1
+   
+   
+    
+     CTRL
+     Watchdog Timer Control Register.
+     0x00
+     0x7FFFF000
+     
+      
+       INT_PERIOD
+       Watchdog Interrupt Period. The watchdog timer will assert an interrupt, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset.
+       0
+       4
+       
+        
+         wdt2pow31
+         2**31 clock cycles.
+         0
+        
+        
+         wdt2pow30
+         2**30 clock cycles.
+         1
+        
+        
+         wdt2pow29
+         2**29 clock cycles.
+         2
+        
+        
+         wdt2pow28
+         2**28 clock cycles.
+         3
+        
+        
+         wdt2pow27
+         2^27 clock cycles.
+         4
+        
+        
+         wdt2pow26
+         2**26 clock cycles.
+         5
+        
+        
+         wdt2pow25
+         2**25 clock cycles.
+         6
+        
+        
+         wdt2pow24
+         2**24 clock cycles.
+         7
+        
+        
+         wdt2pow23
+         2**23 clock cycles.
+         8
+        
+        
+         wdt2pow22
+         2**22 clock cycles.
+         9
+        
+        
+         wdt2pow21
+         2**21 clock cycles.
+         10
+        
+        
+         wdt2pow20
+         2**20 clock cycles.
+         11
+        
+        
+         wdt2pow19
+         2**19 clock cycles.
+         12
+        
+        
+         wdt2pow18
+         2**18 clock cycles.
+         13
+        
+        
+         wdt2pow17
+         2**17 clock cycles.
+         14
+        
+        
+         wdt2pow16
+         2**16 clock cycles.
+         15
+        
+       
+      
+      
+       RST_PERIOD
+       Watchdog Reset Period. The watchdog timer will assert a reset, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset.
+       4
+       4
+       
+        
+         wdt2pow31
+         2**31 clock cycles.
+         0
+        
+        
+         wdt2pow30
+         2**30 clock cycles.
+         1
+        
+        
+         wdt2pow29
+         2**29 clock cycles.
+         2
+        
+        
+         wdt2pow28
+         2**28 clock cycles.
+         3
+        
+        
+         wdt2pow27
+         2^27 clock cycles.
+         4
+        
+        
+         wdt2pow26
+         2**26 clock cycles.
+         5
+        
+        
+         wdt2pow25
+         2**25 clock cycles.
+         6
+        
+        
+         wdt2pow24
+         2**24 clock cycles.
+         7
+        
+        
+         wdt2pow23
+         2**23 clock cycles.
+         8
+        
+        
+         wdt2pow22
+         2**22 clock cycles.
+         9
+        
+        
+         wdt2pow21
+         2**21 clock cycles.
+         10
+        
+        
+         wdt2pow20
+         2**20 clock cycles.
+         11
+        
+        
+         wdt2pow19
+         2**19 clock cycles.
+         12
+        
+        
+         wdt2pow18
+         2**18 clock cycles.
+         13
+        
+        
+         wdt2pow17
+         2**17 clock cycles.
+         14
+        
+        
+         wdt2pow16
+         2**16 clock cycles.
+         15
+        
+       
+      
+      
+       WDT_EN
+       Watchdog Timer Enable.
+       8
+       1
+       
+        
+         dis
+         Disable.
+         0
+        
+        
+         en
+         Enable.
+         1
+        
+       
+      
+      
+       INT_FLAG
+       Watchdog Timer Interrupt Flag.
+       9
+       1
+       oneToClear
+       
+        
+         inactive
+         No interrupt is pending.
+         0
+        
+        
+         pending
+         An interrupt is pending.
+         1
+        
+       
+      
+      
+       INT_EN
+       Watchdog Timer Interrupt Enable.
+       10
+       1
+       
+        
+         dis
+         Disable.
+         0
+        
+        
+         en
+         Enable.
+         1
+        
+       
+      
+      
+       RST_EN
+       Watchdog Timer Reset Enable.
+       11
+       1
+       
+        
+         dis
+         Disable.
+         0
+        
+        
+         en
+         Enable.
+         1
+        
+       
+      
+      
+       RST_FLAG
+       Watchdog Timer Reset Flag.
+       31
+       1
+       
+        read-write
+        
+         noEvent
+         The event has not occurred.
+         0
+        
+        
+         occurred
+         The event has occurred.
+         1
+        
+       
+      
+     
+    
+    
+     RST
+     Watchdog Timer Reset Register.
+     0x04
+     write-only
+     
+      
+       WDT_RST
+       Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD then a watchdog reset will occur, if enabled.
+       0
+       8
+       
+        
+         seq0
+         The first value to be written to reset the WDT.
+         0x000000A5
+        
+        
+         seq1
+         The second value to be written to reset the WDT.
+         0x0000005A
+        
+       
+      
+     
+    
+   
+  
+
+ 
+
diff --git a/bsp/maxim/MAX32660_EVSYS/project.uvoptx b/bsp/maxim/MAX32660_EVSYS/project.uvoptx
index ff7f9de14e..a8359d025b 100644
--- a/bsp/maxim/MAX32660_EVSYS/project.uvoptx
+++ b/bsp/maxim/MAX32660_EVSYS/project.uvoptx
@@ -117,26 +117,6 @@
         BIN\CMSIS_AGDI.dll
       
       
-        
-          0
-          ARMRTXEVENTFLAGS
-          -L70 -Z18 -C0 -M0 -T1
-        
-        
-          0
-          DLGTARM
-          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)
-        
-        
-          0
-          ARMDBGFLAGS
-          
-        
-        
-          0
-          DLGUARM
-          
-        
         
           0
           CMSIS_AGDI
@@ -155,12 +135,12 @@
       
         0
         0
-        1
+        0
         0
         0
         0
         0
-        1
+        0
         0
         0
         0
@@ -223,7 +203,7 @@
 
   
     CPU
-    1
+    0
     0
     0
     0
@@ -291,7 +271,7 @@
 
   
     DeviceDrivers
-    1
+    0
     0
     0
     0
@@ -407,7 +387,7 @@
 
   
     Drivers
-    1
+    0
     0
     0
     0
@@ -463,7 +443,7 @@
 
   
     finsh
-    1
+    0
     0
     0
     0
@@ -507,7 +487,7 @@
 
   
     Kernel
-    1
+    0
     0
     0
     0
diff --git a/bsp/maxim/MAX32660_EVSYS/project.uvprojx b/bsp/maxim/MAX32660_EVSYS/project.uvprojx
index 7b23a65cbc..5f53b9696b 100644
--- a/bsp/maxim/MAX32660_EVSYS/project.uvprojx
+++ b/bsp/maxim/MAX32660_EVSYS/project.uvprojx
@@ -188,7 +188,7 @@
             0
             0
             8
-            1
+            0
             0
             0
             0
diff --git a/bsp/maxim/MAX32660_EVSYS/rtconfig.h b/bsp/maxim/MAX32660_EVSYS/rtconfig.h
index a15112c1b2..a2f3204096 100644
--- a/bsp/maxim/MAX32660_EVSYS/rtconfig.h
+++ b/bsp/maxim/MAX32660_EVSYS/rtconfig.h
@@ -10,7 +10,7 @@
 #define RT_ALIGN_SIZE 4
 #define RT_THREAD_PRIORITY_32
 #define RT_THREAD_PRIORITY_MAX 32
-#define RT_TICK_PER_SECOND 100
+#define RT_TICK_PER_SECOND 1000
 #define RT_USING_OVERFLOW_CHECK
 #define RT_USING_HOOK
 #define RT_USING_IDLE_HOOK
diff --git a/bsp/maxim/MAX32660_EVSYS/rtconfig.py b/bsp/maxim/MAX32660_EVSYS/rtconfig.py
index 3d7c28a68c..48273268f4 100644
--- a/bsp/maxim/MAX32660_EVSYS/rtconfig.py
+++ b/bsp/maxim/MAX32660_EVSYS/rtconfig.py
@@ -13,7 +13,7 @@ if os.getenv('RTT_CC'):
 
 if  CROSS_TOOL == 'gcc':
     PLATFORM    = 'gcc'
-    EXEC_PATH   = r'C:\Users\XXYYZZ'
+    EXEC_PATH   = r'.'
 elif CROSS_TOOL == 'keil':
     PLATFORM    = 'armcc'
     EXEC_PATH   = 'C:/Keil_v5'
@@ -34,13 +34,14 @@ if PLATFORM == 'gcc':
     CC = PREFIX + 'gcc'
     AS = PREFIX + 'gcc'
     AR = PREFIX + 'ar'
+    CXX = PREFIX + 'g++'
     LINK = PREFIX + 'gcc'
     TARGET_EXT = 'elf'
     SIZE = PREFIX + 'size'
     OBJDUMP = PREFIX + 'objdump'
     OBJCPY = PREFIX + 'objcopy'
 
-    DEVICE = ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections'
+    DEVICE = ' -mcpu=cortex-m4 -mthumb'
     CFLAGS = DEVICE
     AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
     LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
@@ -61,6 +62,7 @@ if PLATFORM == 'gcc':
 elif PLATFORM == 'armcc':
     # toolchains
     CC = 'armcc'
+    CXX = 'armcc'
     AS = 'armasm'
     AR = 'armar'
     LINK = 'armlink'
@@ -132,3 +134,11 @@ elif PLATFORM == 'iar':
     
     EXEC_PATH = EXEC_PATH + '/arm/bin/'
     POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
+
+
+def dist_handle(BSP_ROOT, dist_dir):
+    import sys
+    cwd_path = os.getcwd()
+    sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+    from sdk_dist import dist_do_building
+    dist_do_building(BSP_ROOT, dist_dir)
\ No newline at end of file
diff --git a/bsp/maxim/MAX32660_EVSYS/template.uvprojx b/bsp/maxim/MAX32660_EVSYS/template.uvprojx
index 1ea2e5a7ba..47b809b51d 100644
--- a/bsp/maxim/MAX32660_EVSYS/template.uvprojx
+++ b/bsp/maxim/MAX32660_EVSYS/template.uvprojx
@@ -188,7 +188,7 @@
             0
             0
             8
-            1
+            0
             0
             0
             0
diff --git a/bsp/maxim/libraries/HAL_Drivers/SConscript b/bsp/maxim/libraries/HAL_Drivers/SConscript
index f6262f54da..deaa1e25a1 100644
--- a/bsp/maxim/libraries/HAL_Drivers/SConscript
+++ b/bsp/maxim/libraries/HAL_Drivers/SConscript
@@ -20,9 +20,14 @@ if GetDepend(['RT_USING_PWM']):
 if GetDepend(['RT_USING_SPI']):
     src += ['drv_spi.c']
 
+if GetDepend(['RT_USING_I2C']):
+    src += ['drv_i2c.c']
+
 if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']):
     src += ['drv_soft_i2c.c']
 
+if GetDepend(['BSP_USING_ONCHIP_RTC']):
+    src += ['drv_rtc.c']
 
 if GetDepend(['BSP_USING_WDT']):
     src += ['drv_wdt.c']
diff --git a/bsp/maxim/libraries/HAL_Drivers/drv_i2c.c b/bsp/maxim/libraries/HAL_Drivers/drv_i2c.c
new file mode 100644
index 0000000000..ddacdf0a12
--- /dev/null
+++ b/bsp/maxim/libraries/HAL_Drivers/drv_i2c.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-02-26     Jackistang   first version
+ *
+ */
+
+#include "drv_i2c.h"
+#include "i2c.h"
+#include 
+#include 
+#include "board.h"
+
+#ifdef RT_USING_I2C
+
+#if !defined(BSP_USING_I2C0) && !defined(BSP_USING_I2C1)
+    #error "Please define at least one BSP_USING_I2Cx"
+    /* this driver can be disabled at menuconfig -> Hardware Drivers Config -> On-chip Peripheral Drivers -> Enable I2C */
+#endif
+
+#define DBG_LEVEL   DBG_LOG
+#include 
+#define LOG_TAG                "drv.i2c"
+
+/* mxc config class */
+struct mxc_i2c_config
+{
+    const char *name;
+    mxc_i2c_regs_t *i2c_periph;
+    i2c_speed_t speed;
+    IRQn_Type irq_type;
+};
+
+struct mxc_i2c
+{
+    struct rt_i2c_bus_device bus;
+    struct mxc_i2c_config *config;
+};
+
+static struct mxc_i2c_config i2c_config[] =
+{
+#ifdef BSP_USING_I2C0
+    {
+        .name       = "i2c0",
+        .i2c_periph = MXC_I2C_GET_I2C(0),
+        .irq_type   = MXC_I2C_GET_IRQ(0),
+        .speed      = I2C_STD_MODE,
+        /*I2C_STD_MODE: 100KHz, I2C_FAST_MODE: 400KHz, I2C_FASTPLUS_MODE: 1MHz, I2C_HS_MODE: 3.4MHz */
+    },
+#endif
+#ifdef BSP_USING_I2C1
+    {
+        .name       = "i2c1",
+        .i2c_periph = MXC_I2C_GET_I2C(1),
+        .irq_type   = MXC_I2C_GET_IRQ(1),
+        .speed      = I2C_STD_MODE,
+        /*I2C_STD_MODE: 100KHz, I2C_FAST_MODE: 400KHz, I2C_FASTPLUS_MODE: 1MHz, I2C_HS_MODE: 3.4MHz */
+    },
+#endif
+};
+
+static struct mxc_i2c i2c_obj[sizeof(i2c_config) / sizeof(i2c_config[0])] = {0};
+
+
+static rt_size_t mxc_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
+                                  struct rt_i2c_msg msgs[],
+                                  rt_uint32_t num)
+{
+    rt_uint32_t i, ret;
+    rt_uint16_t addr;
+    int error;
+    int restart = 0;
+    struct rt_i2c_msg *msg;
+    struct mxc_i2c *obj = (struct mxc_i2c *)bus;
+
+    for (i = 0; i < num; i++)
+    {
+        msg = &msgs[i];
+
+        if (msg->flags & RT_I2C_ADDR_10BIT || msg->flags & RT_I2C_NO_START || msg->flags & RT_I2C_IGNORE_NACK || msg->flags & RT_I2C_NO_READ_ACK)
+        {
+            LOG_E("Not support RT_I2C_ADDR_10BIT or RT_I2C_NO_START or RT_I2C_IGNORE_NACK or RT_I2C_NO_READ_ACK");
+            return 0;
+        }
+
+        if (msg->flags & RT_I2C_NO_STOP)
+        {
+            restart = 1;
+        }
+
+        if (msg->flags & RT_I2C_RD)
+        {
+            addr = msg->addr << 1;
+            if ((error = I2C_MasterRead(obj->config->i2c_periph, (uint8_t)addr, msg->buf, msg->len, restart)) != msg->len)
+            {
+                LOG_E("Error writing %d", error);
+                return 0;
+            }
+        }
+        else    /* RT_I2C_WR */
+        {
+            addr = msg->addr << 1;
+            if ((error = I2C_MasterWrite(obj->config->i2c_periph, (uint8_t)addr, msg->buf, msg->len, restart)) != msg->len)
+            {
+                LOG_E("Error writing %d", error);
+                return 0;
+            }
+        }
+    }
+    ret = i;
+
+    return ret;
+}
+
+static const struct rt_i2c_bus_device_ops mxc_i2c_ops =
+{
+    mxc_i2c_mst_xfer,
+    RT_NULL,
+    RT_NULL,
+};
+
+int rt_hw_i2c_init(void)
+{
+    rt_size_t obj_num;
+    int index;
+    rt_err_t result = 0;
+
+#ifdef BSP_USING_I2C0
+    NVIC_EnableIRQ(I2C0_IRQn);
+#endif
+#ifdef BSP_USING_I2C1
+    NVIC_EnableIRQ(I2C1_IRQn);
+#endif
+
+    obj_num = sizeof(i2c_obj) / sizeof(struct mxc_i2c);
+    for (index = 0; index < obj_num; index++)
+    {
+        /* init i2c object */
+        i2c_obj[index].config = &i2c_config[index];
+        i2c_obj[index].bus.ops = &mxc_i2c_ops;
+
+        /* init i2c device */
+        I2C_Shutdown(i2c_config[index].i2c_periph);
+        I2C_Init(i2c_config[index].i2c_periph, i2c_config[index].speed, RT_NULL);
+
+        /* register i2c device */
+        result = rt_i2c_bus_device_register(&i2c_obj[index].bus,
+                                            i2c_obj[index].config->name
+                                           );
+        RT_ASSERT(result == RT_EOK);
+    }
+
+    return 0;
+}
+INIT_DEVICE_EXPORT(rt_hw_i2c_init);
+
+#ifdef BSP_USING_I2C0
+void I2C0_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    I2C_Handler(MXC_I2C0);
+    rt_interrupt_leave();
+}
+#endif
+
+#ifdef BSP_USING_I2C1
+void I2C1_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    I2C_Handler(MXC_I2C1);
+    rt_interrupt_leave();
+}
+#endif
+
+#endif /* RT_USING_I2C */
diff --git a/bsp/maxim/libraries/HAL_Drivers/drv_i2c.h b/bsp/maxim/libraries/HAL_Drivers/drv_i2c.h
new file mode 100644
index 0000000000..f1be28755c
--- /dev/null
+++ b/bsp/maxim/libraries/HAL_Drivers/drv_i2c.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-02-26     Jackistang   first version
+ *
+ */
+
+#ifndef __DRV_I2C_H__
+#define __DRV_I2C_H__
+
+
+#endif /* __DRV_I2C_H__ */
diff --git a/bsp/maxim/libraries/HAL_Drivers/drv_rtc.c b/bsp/maxim/libraries/HAL_Drivers/drv_rtc.c
new file mode 100644
index 0000000000..6584f55752
--- /dev/null
+++ b/bsp/maxim/libraries/HAL_Drivers/drv_rtc.c
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date         Author        Notes
+ * 2021-03-15   picospuch     Porting for maxiam32660
+ */
+
+#include "rtc.h"
+#include "board.h"
+#include 
+
+#ifdef BSP_USING_ONCHIP_RTC
+
+#define DBG_LEVEL   DBG_INFO
+#include 
+#define LOG_TAG                "drv.rtc"
+
+static struct rt_device rtc;
+
+static sys_cfg_rtc_t sys_cfg;
+
+static time_t get_rtc_timestamp(void)
+{
+    LOG_D("get rtc time.");
+    return RTC_GetSecond();
+}
+
+static rt_err_t set_rtc_time_stamp(time_t time_stamp)
+{
+  LOG_D("set rtc time.");
+
+  if (RTC_Init(MXC_RTC, time_stamp, 0, &sys_cfg) != E_SUCCESS) {
+    return -RT_ERROR;
+  }
+
+  if (RTC_EnableRTCE(MXC_RTC) != E_SUCCESS) {
+    return -RT_ERROR;
+  }
+
+  return RT_EOK;
+}
+
+static void rt_rtc_init(void)
+{
+  sys_cfg.tmr = MXC_TMR0;
+  RTC_Init(MXC_RTC, 0, 0, &sys_cfg);
+}
+
+static rt_err_t rt_rtc_config(struct rt_device *dev)
+{
+  if (RTC_EnableRTCE(MXC_RTC) != E_SUCCESS) {
+    return -RT_ERROR;
+  }
+  return RT_EOK;
+}
+
+static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args)
+{
+    rt_err_t result = RT_EOK;
+    RT_ASSERT(dev != RT_NULL);
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_RTC_GET_TIME:
+        *(rt_uint32_t *)args = get_rtc_timestamp();
+        LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args);
+        break;
+
+    case RT_DEVICE_CTRL_RTC_SET_TIME:
+        if (set_rtc_time_stamp(*(rt_uint32_t *)args))
+        {
+            result = -RT_ERROR;
+        }
+        LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args);
+        break;
+    }
+
+    return result;
+}
+
+#ifdef RT_USING_DEVICE_OPS
+const static struct rt_device_ops rtc_ops =
+{
+    RT_NULL,
+    RT_NULL,
+    RT_NULL,
+    RT_NULL,
+    RT_NULL,
+    rt_rtc_control
+};
+#endif
+
+static rt_err_t rt_hw_rtc_register(rt_device_t device, const char *name, rt_uint32_t flag)
+{
+    RT_ASSERT(device != RT_NULL);
+
+    rt_rtc_init();
+    if (rt_rtc_config(device) != RT_EOK)
+    {
+        return -RT_ERROR;
+    }
+#ifdef RT_USING_DEVICE_OPS
+    device->ops         = &rtc_ops;
+#else
+    device->init        = RT_NULL;
+    device->open        = RT_NULL;
+    device->close       = RT_NULL;
+    device->read        = RT_NULL;
+    device->write       = RT_NULL;
+    device->control     = rt_rtc_control;
+#endif
+    device->type        = RT_Device_Class_RTC;
+    device->rx_indicate = RT_NULL;
+    device->tx_complete = RT_NULL;
+    device->user_data   = RT_NULL;
+
+    /* register a character device */
+    return rt_device_register(device, name, flag);
+}
+
+int rt_hw_rtc_init(void)
+{
+    rt_err_t result;
+    result = rt_hw_rtc_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR);
+    if (result != RT_EOK)
+    {
+        LOG_E("rtc register err code: %d", result);
+        return result;
+    }
+    LOG_D("rtc init success");
+    return RT_EOK;
+}
+INIT_DEVICE_EXPORT(rt_hw_rtc_init);
+
+#endif /* BSP_USING_ONCHIP_RTC */
diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/startup_max32660.S b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/startup_max32660.S
index c7ca195d79..9b9c71de9b 100644
--- a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/startup_max32660.S
+++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/startup_max32660.S
@@ -223,7 +223,7 @@ Reset_Handler:
     blx     r0  
 
     /* Transfer control to users main program */
-    ldr     r0, =main
+    ldr     r0, =entry
     blx     r0 
 
 .SPIN:
diff --git a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c
index 1d404cc48d..0f3b061e8a 100644
--- a/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c
+++ b/bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c
@@ -95,6 +95,9 @@ __weak void SystemCoreClockUpdate(void)
 __weak int PreInit(void)
 {
     /* Do nothing */
+#if defined ( __CC_ARM )
+    SystemInit();
+#endif
     return 0;
 }
 
@@ -145,23 +148,23 @@ __weak void SystemInit(void)
     Board_Init();
 }
 
-#if defined ( __CC_ARM )
-/* Global variable initialization does not occur until post scatterload in Keil tools.*/
+//#if defined ( __CC_ARM )
+///* Global variable initialization does not occur until post scatterload in Keil tools.*/
 
-/* External function called after our post scatterload function implementation. */
-extern void $Super$$__main_after_scatterload(void);
+///* External function called after our post scatterload function implementation. */
+//extern void $Super$$__main_after_scatterload(void);
 
-/**
- * @brief   Initialization function for SystemCoreClock and Board_Init.
- * @details $Sub$$__main_after_scatterload is called during system startup in the Keil
- *          toolset. Global variable and static variable space must be set up by the compiler
- *          prior to using these memory spaces. Setting up the SystemCoreClock and Board_Init
- *          require global memory for variable storage and are called from this function in
- *          the Keil tool chain.
- */
-void $Sub$$__main_after_scatterload(void)
-{
-    SystemInit();
-    $Super$$__main_after_scatterload();
-}
-#endif /* __CC_ARM */
+///**
+// * @brief   Initialization function for SystemCoreClock and Board_Init.
+// * @details $Sub$$__main_after_scatterload is called during system startup in the Keil
+// *          toolset. Global variable and static variable space must be set up by the compiler
+// *          prior to using these memory spaces. Setting up the SystemCoreClock and Board_Init
+// *          require global memory for variable storage and are called from this function in
+// *          the Keil tool chain.
+// */
+//void $Sub$$__main_after_scatterload(void)
+//{
+//    SystemInit();
+//    $Super$$__main_after_scatterload();
+//}
+//#endif /* __CC_ARM */
diff --git a/bsp/maxim/tools/sdk_dist.py b/bsp/maxim/tools/sdk_dist.py
new file mode 100644
index 0000000000..2bc57c6b95
--- /dev/null
+++ b/bsp/maxim/tools/sdk_dist.py
@@ -0,0 +1,21 @@
+import os
+import sys
+import shutil
+
+cwd_path = os.getcwd()
+sys.path.append(os.path.join(os.path.dirname(cwd_path), 'rt-thread', 'tools'))
+
+
+# BSP dist function
+def dist_do_building(BSP_ROOT, dist_dir):
+    from mkdist import bsp_copy_files
+    import rtconfig
+
+    print("=> copy maxim bsp library")
+    library_dir = os.path.join(dist_dir, 'libraries')
+    library_path = os.path.join(os.path.dirname(BSP_ROOT), 'libraries')
+
+    print("=> copy bsp drivers")
+    bsp_copy_files(os.path.join(library_path, 'HAL_Drivers'), os.path.join(library_dir, 'HAL_Drivers'))
+    bsp_copy_files(os.path.join(library_path, 'MAX32660PeriphDriver'), os.path.join(library_dir, 'MAX32660PeriphDriver'))
+    
\ No newline at end of file
diff --git a/bsp/mb9bf500r/CMSIS/start_gcc.S b/bsp/mb9bf500r/CMSIS/start_gcc.S
index b1a93e52be..8789adb8f6 100644
--- a/bsp/mb9bf500r/CMSIS/start_gcc.S
+++ b/bsp/mb9bf500r/CMSIS/start_gcc.S
@@ -1,17 +1,13 @@
 /*
- * File      : start_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2011, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2011-07-01     lgnq         first version
  */
- 
+
   .syntax unified
   .cpu cortex-m3
   .fpu softvfp
@@ -20,10 +16,10 @@
 .global  g_pfnVectors
 .global  Default_Handler
 
-/* start address for the initialization values of the .data section. 
+/* start address for the initialization values of the .data section.
 defined in linker script */
 .word  _sidata
-/* start address for the .data section. defined in linker script */  
+/* start address for the .data section. defined in linker script */
 .word  _sdata
 /* end address for the .data section. defined in linker script */
 .word  _edata
@@ -38,7 +34,7 @@ defined in linker script */
  * @brief  This is the code that gets called when the processor first
  *          starts execution following a reset event. Only the absolutely
  *          necessary set is performed, after which the application
- *          supplied main() routine is called. 
+ *          supplied main() routine is called.
  * @param  None
  * @retval : None
 */
@@ -46,11 +42,11 @@ defined in linker script */
   .section  .text.Reset_Handler
   .weak  Reset_Handler
   .type  Reset_Handler, %function
-Reset_Handler:  
-/* restore original stack pointer */  
+Reset_Handler:
+/* restore original stack pointer */
   ldr   sp, =_estack       /* set stack pointer */
 
-/* Copy the data segment initializers from flash to SRAM */  
+/* Copy the data segment initializers from flash to SRAM */
   movs  r1, #0
   b  LoopCopyDataInit
 
@@ -59,7 +55,7 @@ CopyDataInit:
   ldr  r3, [r3, r1]
   str  r3, [r0, r1]
   adds  r1, r1, #4
-    
+
 LoopCopyDataInit:
   ldr  r0, =_sdata
   ldr  r3, =_edata
@@ -68,27 +64,27 @@ LoopCopyDataInit:
   bcc  CopyDataInit
   ldr  r2, =_sbss
   b  LoopFillZerobss
-/* Zero fill the bss segment. */  
+/* Zero fill the bss segment. */
 FillZerobss:
   movs  r3, #0
   str  r3, [r2], #4
-    
+
 LoopFillZerobss:
   ldr  r3, = _ebss
   cmp  r2, r3
   bcc  FillZerobss
 /* Call the application's entry point.*/
   bl  main
-  bx  lr    
+  bx  lr
 .size  Reset_Handler, .-Reset_Handler
 
 /**
- * @brief  This is the code that gets called when the processor receives an 
+ * @brief  This is the code that gets called when the processor receives an
  *         unexpected interrupt.  This simply enters an infinite loop, preserving
  *         the system state for examination by a debugger.
  *
- * @param  None     
- * @retval : None       
+ * @param  None
+ * @retval : None
 */
     .section  .text.Default_Handler,"ax",%progbits
 Default_Handler:
@@ -101,7 +97,7 @@ Infinite_Loop:
 * must be placed on this to ensure that it ends up at physical address
 * 0x0000.0000.
 *
-******************************************************************************/    
+******************************************************************************/
   .section  .isr_vector,"a",%progbits
   .type  g_pfnVectors, %object
   .size  g_pfnVectors, .-g_pfnVectors
@@ -123,7 +119,7 @@ g_pfnVectors:
   .word  0
   .word  PendSV_Handler
   .word  SysTick_Handler
-  
+
   .word  CSV_IRQHandler
   .word  SWDT_IRQHandler
   .word  LVD_IRQHandler
@@ -171,25 +167,25 @@ g_pfnVectors:
   .word  DMAC6_IRQHandler
   .word  DMAC7_IRQHandler
   .word  RESERVED_3_IRQHandler
-  .word  RESERVED_4_IRQHandler   
-   
+  .word  RESERVED_4_IRQHandler
+
 /*******************************************************************************
 *
-* Provide weak aliases for each Exception handler to the Default_Handler. 
-* As they are weak aliases, any function with the same name will override 
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
 * this definition.
 *
 *******************************************************************************/
-    
+
   .weak  NMI_Handler
   .thumb_set NMI_Handler,Default_Handler
 
   .weak  HardFault_Handler
   .thumb_set HardFault_Handler,Default_Handler
-    
+
   .weak  MemManage_Handler
   .thumb_set MemManage_Handler,Default_Handler
-  
+
   .weak  BusFault_Handler
   .thumb_set BusFault_Handler,Default_Handler
 
@@ -204,10 +200,10 @@ g_pfnVectors:
 
   .weak  PendSV_Handler
   .thumb_set PendSV_Handler,Default_Handler
-  
+
   .weak  SysTick_Handler
   .thumb_set SysTick_Handler,Default_Handler
-    
+
   .weak  CSV_IRQHandler
   .thumb_set CSV_IRQHandler,Default_Handler
 
@@ -351,4 +347,4 @@ g_pfnVectors:
 
   .weak  RESERVED_4_IRQHandler
   .thumb_set RESERVED_4_IRQHandler,Default_Handler
-  
+
diff --git a/bsp/mb9bf500r/CMSIS/start_iar.S b/bsp/mb9bf500r/CMSIS/start_iar.S
index 1daaffc49a..e60f066822 100644
--- a/bsp/mb9bf500r/CMSIS/start_iar.S
+++ b/bsp/mb9bf500r/CMSIS/start_iar.S
@@ -1,11 +1,7 @@
 ;/*
-; * File      : context_iar.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
+; * Copyright (c) 2006-2021, RT-Thread Development Team
 ; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
@@ -15,349 +11,349 @@
 
 #include "rtconfig.h"
 
-	MODULE	?cstartup
+    MODULE  ?cstartup
 
 ;; ICODE is the same segment as cstartup. By placing __low_level_init
 ;; in the same segment, we make sure it can be reached with BL. */
 
-	SECTION	CSTACK:DATA:NOROOT(3)
-	SECTION	.icode:CODE:NOROOT(2)
+    SECTION CSTACK:DATA:NOROOT(3)
+    SECTION .icode:CODE:NOROOT(2)
 
-#ifdef RT_USING_UART2   
-	IMPORT	MFS2RX_IRQHandler
+#ifdef RT_USING_UART2
+    IMPORT  MFS2RX_IRQHandler
 #endif
-	PUBLIC	__low_level_init
+    PUBLIC  __low_level_init
 
-	PUBWEAK SystemInit_ExtMemCtl
-	SECTION .text:CODE:REORDER(2)
-	THUMB
+    PUBWEAK SystemInit_ExtMemCtl
+    SECTION .text:CODE:REORDER(2)
+    THUMB
 SystemInit_ExtMemCtl
-	BX LR
+    BX LR
 
 __low_level_init:
-	;;  Initialize hardware.
-	LDR	R0, = SystemInit_ExtMemCtl ; initialize external memory controller
-	MOV	R11, LR
-	BLX	R0
-	LDR	R1, =sfe(CSTACK)        ; restore original stack pointer
-	MSR	MSP, R1
-	MOV	R0,#1
-	;; Return with BX to be independent of mode of caller
-	BX	R11
+    ;;  Initialize hardware.
+    LDR R0, = SystemInit_ExtMemCtl ; initialize external memory controller
+    MOV R11, LR
+    BLX R0
+    LDR R1, =sfe(CSTACK)        ; restore original stack pointer
+    MSR MSP, R1
+    MOV R0,#1
+    ;; Return with BX to be independent of mode of caller
+    BX  R11
 
-	;; Forward declaration of sections.
-	SECTION .intvec:CODE:NOROOT(2)
+    ;; Forward declaration of sections.
+    SECTION .intvec:CODE:NOROOT(2)
 
-	EXTERN  __iar_program_start
-	PUBLIC  __vector_table
+    EXTERN  __iar_program_start
+    PUBLIC  __vector_table
 
-	DATA
+    DATA
 __vector_table
-	DCD     sfe(CSTACK)
-	DCD     __iar_program_start
-	
-	DCD     NMI_Handler               ; NMI Handler
-	DCD     HardFault_Handler         ; Hard Fault Handler
-	DCD     MemManage_Handler         ; MPU Fault Handler
-	DCD     BusFault_Handler          ; Bus Fault Handler
-	DCD     UsageFault_Handler        ; Usage Fault Handler
-	DCD     0                         ; Reserved
-	DCD     0                         ; Reserved
-	DCD     0                         ; Reserved
-	DCD     0                         ; Reserved
-	DCD     SVC_Handler               ; SVCall Handler
-	DCD     DebugMon_Handler          ; Debug Monitor Handler
-	DCD     0                         ; Reserved
-	DCD     PendSV_Handler            ; PendSV Handler
-	DCD     SysTick_Handler           ; SysTick Handler
-	
-	; External Interrupts
-	DCD     CSV_IRQHandler            ; Clock Super Visor
-	DCD     SWDT_IRQHandler           ; Software Watchdog Timer
-	DCD     LVD_IRQHandler            ; Low Voltage Detector
-	DCD     WFG_IRQHandler            ; Wave Form Generator
-	DCD     EXINT0_7_IRQHandler       ; External Interrupt Request ch.0 to ch.7
-	DCD     EXINT8_15_IRQHandler      ; External Interrupt Request ch.8 to ch.15
-	DCD     DTIM_QDU_IRQHandler       ; Dual Timer / Quad Decoder
-	DCD     MFS0RX_IRQHandler         ; MultiFunction Serial ch.0
-	DCD     MFS0TX_IRQHandler         ; MultiFunction Serial ch.0
-	DCD     MFS1RX_IRQHandler         ; MultiFunction Serial ch.1
-	DCD     MFS1TX_IRQHandler         ; MultiFunction Serial ch.1
-#ifdef RT_USING_UART2        
-	DCD     MFS2RX_IRQHandler         ; MultiFunction Serial ch.2
+    DCD     sfe(CSTACK)
+    DCD     __iar_program_start
+
+    DCD     NMI_Handler               ; NMI Handler
+    DCD     HardFault_Handler         ; Hard Fault Handler
+    DCD     MemManage_Handler         ; MPU Fault Handler
+    DCD     BusFault_Handler          ; Bus Fault Handler
+    DCD     UsageFault_Handler        ; Usage Fault Handler
+    DCD     0                         ; Reserved
+    DCD     0                         ; Reserved
+    DCD     0                         ; Reserved
+    DCD     0                         ; Reserved
+    DCD     SVC_Handler               ; SVCall Handler
+    DCD     DebugMon_Handler          ; Debug Monitor Handler
+    DCD     0                         ; Reserved
+    DCD     PendSV_Handler            ; PendSV Handler
+    DCD     SysTick_Handler           ; SysTick Handler
+
+    ; External Interrupts
+    DCD     CSV_IRQHandler            ; Clock Super Visor
+    DCD     SWDT_IRQHandler           ; Software Watchdog Timer
+    DCD     LVD_IRQHandler            ; Low Voltage Detector
+    DCD     WFG_IRQHandler            ; Wave Form Generator
+    DCD     EXINT0_7_IRQHandler       ; External Interrupt Request ch.0 to ch.7
+    DCD     EXINT8_15_IRQHandler      ; External Interrupt Request ch.8 to ch.15
+    DCD     DTIM_QDU_IRQHandler       ; Dual Timer / Quad Decoder
+    DCD     MFS0RX_IRQHandler         ; MultiFunction Serial ch.0
+    DCD     MFS0TX_IRQHandler         ; MultiFunction Serial ch.0
+    DCD     MFS1RX_IRQHandler         ; MultiFunction Serial ch.1
+    DCD     MFS1TX_IRQHandler         ; MultiFunction Serial ch.1
+#ifdef RT_USING_UART2
+    DCD     MFS2RX_IRQHandler         ; MultiFunction Serial ch.2
 #else
-	DCD     NULL_IRQHandler           ; MultiFunction Serial ch.2
+    DCD     NULL_IRQHandler           ; MultiFunction Serial ch.2
 #endif
-	DCD     MFS2TX_IRQHandler         ; MultiFunction Serial ch.2
-	DCD     MFS3RX_IRQHandler         ; MultiFunction Serial ch.3
-	DCD     MFS3TX_IRQHandler         ; MultiFunction Serial ch.3
-	DCD     MFS4RX_IRQHandler         ; MultiFunction Serial ch.4
-	DCD     MFS4TX_IRQHandler         ; MultiFunction Serial ch.4
-	DCD     MFS5RX_IRQHandler         ; MultiFunction Serial ch.5
-	DCD     MFS5TX_IRQHandler         ; MultiFunction Serial ch.5
-	DCD     MFS6RX_IRQHandler         ; MultiFunction Serial ch.6
-	DCD     MFS6TX_IRQHandler         ; MultiFunction Serial ch.6
-	DCD     MFS7RX_IRQHandler         ; MultiFunction Serial ch.7
-	DCD     MFS7TX_IRQHandler         ; MultiFunction Serial ch.7
-	DCD     PPG_IRQHandler            ; PPG
-	DCD     OSC_PLL_WC_IRQHandler     ; OSC / PLL / Watch Counter
-	DCD     ADC0_IRQHandler           ; ADC0
-	DCD     ADC1_IRQHandler           ; ADC1
-	DCD     ADC2_IRQHandler           ; ADC2
-	DCD     FRTIM_IRQHandler          ; Free-run Timer
-	DCD     INCAP_IRQHandler          ; Input Capture
-	DCD     OUTCOMP_IRQHandler        ; Output Compare
-	DCD     BTIM_IRQHandler           ; Base Timer ch.0 to ch.7
-	DCD     CAN0_IRQHandler           ; CAN ch.0
-	DCD     CAN1_IRQHandler           ; CAN ch.1
-	DCD     USBF_IRQHandler           ; USB Function
-	DCD     USBF_USBH_IRQHandler      ; USB Function / USB HOST
-	DCD     RESERVED_1_IRQHandler     ; Reserved_1
-	DCD     RESERVED_2_IRQHandler     ; Reserved_2
-	DCD     DMAC0_IRQHandler          ; DMAC ch.0
-	DCD     DMAC1_IRQHandler          ; DMAC ch.1
-	DCD     DMAC2_IRQHandler          ; DMAC ch.2
-	DCD     DMAC3_IRQHandler          ; DMAC ch.3
-	DCD     DMAC4_IRQHandler          ; DMAC ch.4
-	DCD     DMAC5_IRQHandler          ; DMAC ch.5
-	DCD     DMAC6_IRQHandler          ; DMAC ch.6
-	DCD     DMAC7_IRQHandler          ; DMAC ch.7
-	DCD     RESERVED_3_IRQHandler     ; Reserved_3
-	DCD     RESERVED_4_IRQHandler     ; Reserved_4
+    DCD     MFS2TX_IRQHandler         ; MultiFunction Serial ch.2
+    DCD     MFS3RX_IRQHandler         ; MultiFunction Serial ch.3
+    DCD     MFS3TX_IRQHandler         ; MultiFunction Serial ch.3
+    DCD     MFS4RX_IRQHandler         ; MultiFunction Serial ch.4
+    DCD     MFS4TX_IRQHandler         ; MultiFunction Serial ch.4
+    DCD     MFS5RX_IRQHandler         ; MultiFunction Serial ch.5
+    DCD     MFS5TX_IRQHandler         ; MultiFunction Serial ch.5
+    DCD     MFS6RX_IRQHandler         ; MultiFunction Serial ch.6
+    DCD     MFS6TX_IRQHandler         ; MultiFunction Serial ch.6
+    DCD     MFS7RX_IRQHandler         ; MultiFunction Serial ch.7
+    DCD     MFS7TX_IRQHandler         ; MultiFunction Serial ch.7
+    DCD     PPG_IRQHandler            ; PPG
+    DCD     OSC_PLL_WC_IRQHandler     ; OSC / PLL / Watch Counter
+    DCD     ADC0_IRQHandler           ; ADC0
+    DCD     ADC1_IRQHandler           ; ADC1
+    DCD     ADC2_IRQHandler           ; ADC2
+    DCD     FRTIM_IRQHandler          ; Free-run Timer
+    DCD     INCAP_IRQHandler          ; Input Capture
+    DCD     OUTCOMP_IRQHandler        ; Output Compare
+    DCD     BTIM_IRQHandler           ; Base Timer ch.0 to ch.7
+    DCD     CAN0_IRQHandler           ; CAN ch.0
+    DCD     CAN1_IRQHandler           ; CAN ch.1
+    DCD     USBF_IRQHandler           ; USB Function
+    DCD     USBF_USBH_IRQHandler      ; USB Function / USB HOST
+    DCD     RESERVED_1_IRQHandler     ; Reserved_1
+    DCD     RESERVED_2_IRQHandler     ; Reserved_2
+    DCD     DMAC0_IRQHandler          ; DMAC ch.0
+    DCD     DMAC1_IRQHandler          ; DMAC ch.1
+    DCD     DMAC2_IRQHandler          ; DMAC ch.2
+    DCD     DMAC3_IRQHandler          ; DMAC ch.3
+    DCD     DMAC4_IRQHandler          ; DMAC ch.4
+    DCD     DMAC5_IRQHandler          ; DMAC ch.5
+    DCD     DMAC6_IRQHandler          ; DMAC ch.6
+    DCD     DMAC7_IRQHandler          ; DMAC ch.7
+    DCD     RESERVED_3_IRQHandler     ; Reserved_3
+    DCD     RESERVED_4_IRQHandler     ; Reserved_4
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
 ;; Default interrupt handlers.
 ;;
-	THUMB
+    THUMB
 
-	PUBWEAK NMI_Handler
-	SECTION .text:CODE:REORDER(1)
+    PUBWEAK NMI_Handler
+    SECTION .text:CODE:REORDER(1)
 NMI_Handler
-	B NMI_Handler
-	PUBWEAK HardFault_Handler
-	SECTION .text:CODE:REORDER(1)
+    B NMI_Handler
+    PUBWEAK HardFault_Handler
+    SECTION .text:CODE:REORDER(1)
 HardFault_Handler
-	B HardFault_Handler
-	PUBWEAK MemManage_Handler
-	SECTION .text:CODE:REORDER(1)
+    B HardFault_Handler
+    PUBWEAK MemManage_Handler
+    SECTION .text:CODE:REORDER(1)
 MemManage_Handler
-	B MemManage_Handler
-	PUBWEAK BusFault_Handler
-	SECTION .text:CODE:REORDER(1)
+    B MemManage_Handler
+    PUBWEAK BusFault_Handler
+    SECTION .text:CODE:REORDER(1)
 BusFault_Handler
-	B BusFault_Handler
-	PUBWEAK UsageFault_Handler
-	SECTION .text:CODE:REORDER(1)
+    B BusFault_Handler
+    PUBWEAK UsageFault_Handler
+    SECTION .text:CODE:REORDER(1)
 UsageFault_Handler
-	B UsageFault_Handler
-	PUBWEAK SVC_Handler
-	SECTION .text:CODE:REORDER(1)
+    B UsageFault_Handler
+    PUBWEAK SVC_Handler
+    SECTION .text:CODE:REORDER(1)
 SVC_Handler
-	B SVC_Handler
-	PUBWEAK DebugMon_Handler
-	SECTION .text:CODE:REORDER(1)
+    B SVC_Handler
+    PUBWEAK DebugMon_Handler
+    SECTION .text:CODE:REORDER(1)
 DebugMon_Handler
-	B DebugMon_Handler
-	PUBWEAK PendSV_Handler
-	SECTION .text:CODE:REORDER(1)
+    B DebugMon_Handler
+    PUBWEAK PendSV_Handler
+    SECTION .text:CODE:REORDER(1)
 PendSV_Handler
-	B PendSV_Handler
-	PUBWEAK SysTick_Handler
-	SECTION .text:CODE:REORDER(1)
+    B PendSV_Handler
+    PUBWEAK SysTick_Handler
+    SECTION .text:CODE:REORDER(1)
 SysTick_Handler
-	B SysTick_Handler
-	PUBWEAK CSV_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B SysTick_Handler
+    PUBWEAK CSV_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 CSV_IRQHandler
-	B CSV_IRQHandler
-	PUBWEAK SWDT_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B CSV_IRQHandler
+    PUBWEAK SWDT_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 SWDT_IRQHandler
-	B SWDT_IRQHandler
-	PUBWEAK LVD_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B SWDT_IRQHandler
+    PUBWEAK LVD_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 LVD_IRQHandler
-	B LVD_IRQHandler
-	PUBWEAK WFG_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B LVD_IRQHandler
+    PUBWEAK WFG_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 WFG_IRQHandler
-	B WFG_IRQHandler
-	PUBWEAK EXINT0_7_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B WFG_IRQHandler
+    PUBWEAK EXINT0_7_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 EXINT0_7_IRQHandler
-	B EXINT0_7_IRQHandler
-	PUBWEAK EXINT8_15_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B EXINT0_7_IRQHandler
+    PUBWEAK EXINT8_15_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 EXINT8_15_IRQHandler
-	B EXINT8_15_IRQHandler
-	PUBWEAK DTIM_QDU_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B EXINT8_15_IRQHandler
+    PUBWEAK DTIM_QDU_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 DTIM_QDU_IRQHandler
-	B DTIM_QDU_IRQHandler
-	PUBWEAK MFS0RX_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B DTIM_QDU_IRQHandler
+    PUBWEAK MFS0RX_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 MFS0RX_IRQHandler
-	B MFS0RX_IRQHandler
-	PUBWEAK MFS0TX_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B MFS0RX_IRQHandler
+    PUBWEAK MFS0TX_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 MFS0TX_IRQHandler
-	B MFS0TX_IRQHandler
-	PUBWEAK MFS1RX_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B MFS0TX_IRQHandler
+    PUBWEAK MFS1RX_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 MFS1RX_IRQHandler
-	B MFS1RX_IRQHandler
-	PUBWEAK MFS1TX_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B MFS1RX_IRQHandler
+    PUBWEAK MFS1TX_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 MFS1TX_IRQHandler
-	B MFS1TX_IRQHandler
-	PUBWEAK NULL_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B MFS1TX_IRQHandler
+    PUBWEAK NULL_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 NULL_IRQHandler
-	B NULL_IRQHandler
-	PUBWEAK MFS2TX_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B NULL_IRQHandler
+    PUBWEAK MFS2TX_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 MFS2TX_IRQHandler
-	B MFS2TX_IRQHandler
-	PUBWEAK MFS3RX_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B MFS2TX_IRQHandler
+    PUBWEAK MFS3RX_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 MFS3RX_IRQHandler
-	B MFS3RX_IRQHandler
-	PUBWEAK MFS3TX_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B MFS3RX_IRQHandler
+    PUBWEAK MFS3TX_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 MFS3TX_IRQHandler
-	B MFS3TX_IRQHandler
-	PUBWEAK MFS4RX_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B MFS3TX_IRQHandler
+    PUBWEAK MFS4RX_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 MFS4RX_IRQHandler
-	B MFS4RX_IRQHandler
-	PUBWEAK MFS4TX_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B MFS4RX_IRQHandler
+    PUBWEAK MFS4TX_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 MFS4TX_IRQHandler
-	B MFS4TX_IRQHandler
-	PUBWEAK MFS5RX_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B MFS4TX_IRQHandler
+    PUBWEAK MFS5RX_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 MFS5RX_IRQHandler
-	B MFS5RX_IRQHandler
-	PUBWEAK MFS5TX_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B MFS5RX_IRQHandler
+    PUBWEAK MFS5TX_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 MFS5TX_IRQHandler
-	B MFS5TX_IRQHandler
-	PUBWEAK MFS6RX_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B MFS5TX_IRQHandler
+    PUBWEAK MFS6RX_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 MFS6RX_IRQHandler
-	B MFS6RX_IRQHandler
-	PUBWEAK MFS6TX_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B MFS6RX_IRQHandler
+    PUBWEAK MFS6TX_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 MFS6TX_IRQHandler
-	B MFS6TX_IRQHandler
-	PUBWEAK MFS7RX_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B MFS6TX_IRQHandler
+    PUBWEAK MFS7RX_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 MFS7RX_IRQHandler
-	B MFS7RX_IRQHandler
-	PUBWEAK MFS7TX_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B MFS7RX_IRQHandler
+    PUBWEAK MFS7TX_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 MFS7TX_IRQHandler
-	B MFS7TX_IRQHandler
-	PUBWEAK PPG_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B MFS7TX_IRQHandler
+    PUBWEAK PPG_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 PPG_IRQHandler
-	B PPG_IRQHandler
-	PUBWEAK OSC_PLL_WC_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B PPG_IRQHandler
+    PUBWEAK OSC_PLL_WC_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 OSC_PLL_WC_IRQHandler
-	B OSC_PLL_WC_IRQHandler
-	PUBWEAK ADC0_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B OSC_PLL_WC_IRQHandler
+    PUBWEAK ADC0_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 ADC0_IRQHandler
-	B ADC0_IRQHandler
-	PUBWEAK ADC1_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B ADC0_IRQHandler
+    PUBWEAK ADC1_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 ADC1_IRQHandler
-	B ADC1_IRQHandler
-	PUBWEAK ADC2_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B ADC1_IRQHandler
+    PUBWEAK ADC2_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 ADC2_IRQHandler
-	B ADC2_IRQHandler
-	PUBWEAK FRTIM_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B ADC2_IRQHandler
+    PUBWEAK FRTIM_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 FRTIM_IRQHandler
-	B FRTIM_IRQHandler
-	PUBWEAK INCAP_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B FRTIM_IRQHandler
+    PUBWEAK INCAP_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 INCAP_IRQHandler
-	B INCAP_IRQHandler
-	PUBWEAK OUTCOMP_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B INCAP_IRQHandler
+    PUBWEAK OUTCOMP_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 OUTCOMP_IRQHandler
-	B OUTCOMP_IRQHandler
-	PUBWEAK BTIM_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B OUTCOMP_IRQHandler
+    PUBWEAK BTIM_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 BTIM_IRQHandler
-	B BTIM_IRQHandler
-	PUBWEAK CAN0_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B BTIM_IRQHandler
+    PUBWEAK CAN0_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 CAN0_IRQHandler
-	B CAN0_IRQHandler
-	PUBWEAK CAN1_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B CAN0_IRQHandler
+    PUBWEAK CAN1_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 CAN1_IRQHandler
-	B CAN1_IRQHandler
-	PUBWEAK USBF_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B CAN1_IRQHandler
+    PUBWEAK USBF_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 USBF_IRQHandler
-	B USBF_IRQHandler
-	PUBWEAK USBF_USBH_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B USBF_IRQHandler
+    PUBWEAK USBF_USBH_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 USBF_USBH_IRQHandler
-	B USBF_USBH_IRQHandler
-	PUBWEAK RESERVED_1_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B USBF_USBH_IRQHandler
+    PUBWEAK RESERVED_1_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 RESERVED_1_IRQHandler
-	B RESERVED_1_IRQHandler
-	PUBWEAK RESERVED_2_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B RESERVED_1_IRQHandler
+    PUBWEAK RESERVED_2_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 RESERVED_2_IRQHandler
-	B RESERVED_2_IRQHandler
-	PUBWEAK DMAC0_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B RESERVED_2_IRQHandler
+    PUBWEAK DMAC0_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 DMAC0_IRQHandler
-	B DMAC0_IRQHandler
-	PUBWEAK DMAC1_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B DMAC0_IRQHandler
+    PUBWEAK DMAC1_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 DMAC1_IRQHandler
-	B DMAC1_IRQHandler
-	PUBWEAK DMAC2_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B DMAC1_IRQHandler
+    PUBWEAK DMAC2_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 DMAC2_IRQHandler
-	B DMAC2_IRQHandler
-	PUBWEAK DMAC3_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B DMAC2_IRQHandler
+    PUBWEAK DMAC3_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 DMAC3_IRQHandler
-	B DMAC3_IRQHandler
-	PUBWEAK DMAC4_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B DMAC3_IRQHandler
+    PUBWEAK DMAC4_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 DMAC4_IRQHandler
-	B DMAC4_IRQHandler
-	PUBWEAK DMAC5_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B DMAC4_IRQHandler
+    PUBWEAK DMAC5_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 DMAC5_IRQHandler
-	B DMAC5_IRQHandler
-	PUBWEAK DMAC6_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B DMAC5_IRQHandler
+    PUBWEAK DMAC6_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 DMAC6_IRQHandler
-	B DMAC6_IRQHandler
-	PUBWEAK DMAC7_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B DMAC6_IRQHandler
+    PUBWEAK DMAC7_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 DMAC7_IRQHandler
-	B DMAC7_IRQHandler
-	PUBWEAK RESERVED_3_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B DMAC7_IRQHandler
+    PUBWEAK RESERVED_3_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 RESERVED_3_IRQHandler
-	B RESERVED_3_IRQHandler
-	PUBWEAK RESERVED_4_IRQHandler
-	SECTION .text:CODE:REORDER(1)
+    B RESERVED_3_IRQHandler
+    PUBWEAK RESERVED_4_IRQHandler
+    SECTION .text:CODE:REORDER(1)
 RESERVED_4_IRQHandler
-	B RESERVED_4_IRQHandler	
+    B RESERVED_4_IRQHandler
 
-	END
+    END
diff --git a/bsp/mb9bf500r/CMSIS/start_rvds.S b/bsp/mb9bf500r/CMSIS/start_rvds.S
index f74f0473f2..451f17aa0d 100644
--- a/bsp/mb9bf500r/CMSIS/start_rvds.S
+++ b/bsp/mb9bf500r/CMSIS/start_rvds.S
@@ -1,11 +1,7 @@
 ; /*
-; * File      : start_rvds.s
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
+; * Copyright (c) 2006-2021, RT-Thread Development Team
 ; *
-; * The license and distribution terms for this file may be
-; * found in the file LICENSE in this distribution or at
-; * http://www.rt-thread.org/license/LICENSE
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes
diff --git a/bsp/mb9bf500r/adc.c b/bsp/mb9bf500r/adc.c
index 85b4dc36ea..2e431e90c9 100644
--- a/bsp/mb9bf500r/adc.c
+++ b/bsp/mb9bf500r/adc.c
@@ -1,17 +1,13 @@
 /*
- * File      : adc.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2011, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2011-03-03     lgnq
+ * 2011-03-03     lgnq         First version
  */
-     
+
 #include 
 #include 
 #include "mb9bf506r.h"
@@ -33,45 +29,45 @@ static rt_err_t rt_adc_init(rt_device_t dev)
 
     if(!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
     {
-	    /* I/O setting AN08 - P18 */
+        /* I/O setting AN08 - P18 */
         FM3_GPIO->ADE |= 0x100;
-	    FM3_GPIO->PFR1 = 0x100;
-	
-	    /* A/DC setting */
-	    FM3_ADC0->SCIS1 = 0x01;
-	    FM3_ADC0->ADSS1 = 0x00;				/* sampling timming ADST0 */
-	    FM3_ADC0->ADST1 = 0x43;
-	    FM3_ADC0->ADCT  = 0x02;
-	    FM3_ADC0->SCCR  = 0x10;				/* FIFO clear,single mode */
-	    FM3_ADC0->CMPCR = 0x00;				/* disable comparator */
-	
-	    /* starting A/DC */
-	    FM3_ADC0->SCCR |= 0x01;				/* A/DC start */
-        
+        FM3_GPIO->PFR1 = 0x100;
+
+        /* A/DC setting */
+        FM3_ADC0->SCIS1 = 0x01;
+        FM3_ADC0->ADSS1 = 0x00;             /* sampling timming ADST0 */
+        FM3_ADC0->ADST1 = 0x43;
+        FM3_ADC0->ADCT  = 0x02;
+        FM3_ADC0->SCCR  = 0x10;             /* FIFO clear,single mode */
+        FM3_ADC0->CMPCR = 0x00;             /* disable comparator */
+
+        /* starting A/DC */
+        FM3_ADC0->SCCR |= 0x01;             /* A/DC start */
+
         dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
-	}
-	return RT_EOK;
+    }
+    return RT_EOK;
 }
 
 static rt_err_t rt_adc_control(rt_device_t dev, int cmd, void *args)
 {
-	RT_ASSERT(dev != RT_NULL);
+    RT_ASSERT(dev != RT_NULL);
 
-	switch (cmd)
-	{
-	    case RT_DEVICE_CTRL_ADC_START:
+    switch (cmd)
+    {
+        case RT_DEVICE_CTRL_ADC_START:
             FM3_ADC0->SCCR |= 0x1;
-		break;
-		
-	    case RT_DEVICE_CTRL_ADC_RESULT:
+        break;
+
+        case RT_DEVICE_CTRL_ADC_RESULT:
             while(FM3_ADC0->ADSR & 0x1)
                 ;
             *((rt_uint16_t*)args) = FM3_ADC0->SCFD;
             *((rt_uint16_t*)args) = *((rt_uint16_t*)args) >> 6;
             *((rt_uint16_t*)args) = (*((rt_uint16_t*)args)*3300)/1024;
-		break;
-	}
-	return RT_EOK;
+        break;
+    }
+    return RT_EOK;
 }
 
 extern struct rt_messagequeue mq;
@@ -80,29 +76,29 @@ rt_uint16_t adc_value;
 static void adc_thread_entry(void *parameter)
 {
     rt_device_t device;
-    
+
 #ifdef RT_USING_RTGUI
     struct rtgui_event_command ecmd;
-    
+
     RTGUI_EVENT_COMMAND_INIT(&ecmd);
     ecmd.type = RTGUI_CMD_USER_INT;
     ecmd.command_id = ADC_UPDATE;
 #else
     struct lcd_msg msg;
-#endif	
+#endif
 
     device = rt_device_find("adc");
 
     while(1)
     {
-        rt_device_control(device, RT_DEVICE_CTRL_ADC_START, RT_NULL);    
+        rt_device_control(device, RT_DEVICE_CTRL_ADC_START, RT_NULL);
         rt_device_control(device, RT_DEVICE_CTRL_ADC_RESULT, &adc_value);
         pwm_update(adc_value/3);
 #ifdef RT_USING_RTGUI
         rtgui_thread_send(info_tid, &ecmd.parent, sizeof(ecmd));
 #else
         msg.type = ADC_MSG;
-		msg.adc_value = adc_value;
+        msg.adc_value = adc_value;
         rt_mq_send(&mq, &msg, sizeof(msg));
 #endif
         rt_thread_delay(20);
@@ -112,22 +108,22 @@ static void adc_thread_entry(void *parameter)
 static rt_thread_t adc_thread;
 void rt_hw_adc_init(void)
 {
-	adc.type 		= RT_Device_Class_Char;
-	adc.rx_indicate = RT_NULL;
-	adc.tx_complete = RT_NULL;
-	adc.init 		= rt_adc_init;
-	adc.open		= RT_NULL;
-	adc.close		= RT_NULL;
-	adc.read 		= RT_NULL;
-	adc.write 		= RT_NULL;
-	adc.control 	= rt_adc_control;
-	adc.user_data	= RT_NULL;
+    adc.type        = RT_Device_Class_Char;
+    adc.rx_indicate = RT_NULL;
+    adc.tx_complete = RT_NULL;
+    adc.init        = rt_adc_init;
+    adc.open        = RT_NULL;
+    adc.close       = RT_NULL;
+    adc.read        = RT_NULL;
+    adc.write       = RT_NULL;
+    adc.control     = rt_adc_control;
+    adc.user_data   = RT_NULL;
 
     adc_thread = rt_thread_create("adc", adc_thread_entry, RT_NULL, 384, 26, 5);
-    if(adc_thread != RT_NULL) 
+    if(adc_thread != RT_NULL)
         rt_thread_startup(adc_thread);
-    
-	/* register a character device */
-	rt_device_register(&adc, "adc", RT_DEVICE_FLAG_RDWR);
+
+    /* register a character device */
+    rt_device_register(&adc, "adc", RT_DEVICE_FLAG_RDWR);
 }
 
diff --git a/bsp/mb9bf500r/adc.h b/bsp/mb9bf500r/adc.h
index edbafcf831..c8846b0beb 100644
--- a/bsp/mb9bf500r/adc.h
+++ b/bsp/mb9bf500r/adc.h
@@ -1,28 +1,24 @@
 /*
- * File      : adc.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2011, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2011-03-03     lgnq
  */
- 
+
 #ifndef __ADC_H__
 #define __ADC_H__
 
 /* Exported constants ---------------------------------------------------------*/
 /* Exported macro -------------------------------------------------------------*/
-#define ADC_MODE_SINGLE 	0x00UL
-#define ADC_MODE_SCAN 		0x01UL
-#define ADC_MODE_TAILGATE	0x02UL
+#define ADC_MODE_SINGLE     0x00UL
+#define ADC_MODE_SCAN       0x01UL
+#define ADC_MODE_TAILGATE   0x02UL
 
 #define RT_DEVICE_CTRL_ADC_START        0xF1       /* start ADC conversion */
-#define RT_DEVICE_CTRL_ADC_RESULT		0xF2		/* get ADC result */
+#define RT_DEVICE_CTRL_ADC_RESULT       0xF2        /* get ADC result */
 
 #define ADC_UPDATE 0
 
diff --git a/bsp/mb9bf500r/application.c b/bsp/mb9bf500r/application.c
index ff22c008b1..1cbd0c2d83 100644
--- a/bsp/mb9bf500r/application.c
+++ b/bsp/mb9bf500r/application.c
@@ -1,11 +1,7 @@
 /*
- * File      : application.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -15,7 +11,7 @@
 /**
  * @addtogroup FM3
  */
- 
+
 /*@{*/
 
 #include 
@@ -37,96 +33,96 @@ static char msg_pool[2048];
 
 void rt_init_thread_entry(void *parameter)
 {
-    rt_device_t lcd;  
-    
+    rt_device_t lcd;
+
     rt_hw_led_init();
-	rt_hw_key_init();
-	rt_hw_adc_init();
-	rt_hw_lcd_init();      
-	rt_hw_cpu_init();
+    rt_hw_key_init();
+    rt_hw_adc_init();
+    rt_hw_lcd_init();
+    rt_hw_cpu_init();
 
 #ifdef RT_USING_RTGUI
-	extern void rtgui_system_server_init(void);
+    extern void rtgui_system_server_init(void);
 
-	/* find lcd device */
-	lcd = rt_device_find("lcd");    
-    
-	/* set lcd device as rtgui graphic driver */		
-	rtgui_graphic_set_device(lcd);
+    /* find lcd device */
+    lcd = rt_device_find("lcd");
 
-	/* init rtgui system server */
-	rtgui_system_server_init();
-   
-	/* startup rtgui */
-	rtgui_startup();
+    /* set lcd device as rtgui graphic driver */
+    rtgui_graphic_set_device(lcd);
+
+    /* init rtgui system server */
+    rtgui_system_server_init();
+
+    /* startup rtgui */
+    rtgui_startup();
 #else
-	{
-	char buf[20] = {'\0'};
+    {
+    char buf[20] = {'\0'};
     struct lcd_msg msg;
-    rt_device_t device;   
+    rt_device_t device;
     device = rt_device_find("lcd");
-	rt_device_control(device, RT_DEVICE_CTRL_LCD_CLEAR_SCR, RT_NULL);
-	x = 1;
-	y = 1;
-	rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, "ADC"); 
-	x = 1;
-	y = 20;
-	rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, "CPU");
-	x = 1;
-	y = 40;
-	rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, "KEY");
-    
+    rt_device_control(device, RT_DEVICE_CTRL_LCD_CLEAR_SCR, RT_NULL);
+    x = 1;
+    y = 1;
+    rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, "ADC");
+    x = 1;
+    y = 20;
+    rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, "CPU");
+    x = 1;
+    y = 40;
+    rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, "KEY");
+
     while(1)
     {
         if (rt_mq_recv(&mq, &msg, sizeof(msg), RT_WAITING_FOREVER) == RT_EOK)
         {
-        	switch(msg.type)
-    		{
-    			case ADC_MSG:
-					x = 40;
-					y = 1;
-					rt_memset(buf, 0, sizeof(buf));
-					rt_sprintf(buf, "%04d", msg.adc_value);
-					rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, buf); 
-					break;
-				case CPU_MSG:
-					x = 40;
-					y = 20;
-					rt_memset(buf, 0, sizeof(buf));
-					rt_sprintf(buf, "%03d %03d", msg.major, msg.minor);
-					rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, buf); 
-					break;
-				case KEY_MSG:
-					x = 40;
-					y = 40;
-					rt_memset(buf, 0, sizeof(buf));
+            switch(msg.type)
+            {
+                case ADC_MSG:
+                    x = 40;
+                    y = 1;
+                    rt_memset(buf, 0, sizeof(buf));
+                    rt_sprintf(buf, "%04d", msg.adc_value);
+                    rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, buf);
+                    break;
+                case CPU_MSG:
+                    x = 40;
+                    y = 20;
+                    rt_memset(buf, 0, sizeof(buf));
+                    rt_sprintf(buf, "%03d %03d", msg.major, msg.minor);
+                    rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, buf);
+                    break;
+                case KEY_MSG:
+                    x = 40;
+                    y = 40;
+                    rt_memset(buf, 0, sizeof(buf));
                     switch(msg.key)
-                	{
-                		case KEY_DOWN:
-							rt_sprintf(buf, "DOWN KEY ");
-							break;
-						case KEY_UP:
-							rt_sprintf(buf, "UP KEY   ");
-							break;	
-                		case KEY_RIGHT:
-							rt_sprintf(buf, "RIGHT KEY");
-							break;
-						case KEY_LEFT:
-							rt_sprintf(buf, "LEFT KEY ");
-							break;	
-                		case KEY_ENTER:
-							rt_sprintf(buf, "ENTER KEY");
-							break;
-						default:
-							rt_sprintf(buf, "NO KEY   ");
-							break;								
-                	}
-					rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, buf); 
-                    break;                    
-    		}
+                    {
+                        case KEY_DOWN:
+                            rt_sprintf(buf, "DOWN KEY ");
+                            break;
+                        case KEY_UP:
+                            rt_sprintf(buf, "UP KEY   ");
+                            break;
+                        case KEY_RIGHT:
+                            rt_sprintf(buf, "RIGHT KEY");
+                            break;
+                        case KEY_LEFT:
+                            rt_sprintf(buf, "LEFT KEY ");
+                            break;
+                        case KEY_ENTER:
+                            rt_sprintf(buf, "ENTER KEY");
+                            break;
+                        default:
+                            rt_sprintf(buf, "NO KEY   ");
+                            break;
+                    }
+                    rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, buf);
+                    break;
+            }
         }
     }
-	}
+    }
 #endif
 }
 
@@ -134,12 +130,12 @@ int rt_application_init(void)
 {
     rt_thread_t init_thread;
 
-	rt_mq_init(&mq, "mqt", &msg_pool[0], 128 - sizeof(void*), sizeof(msg_pool), RT_IPC_FLAG_FIFO);
-	
+    rt_mq_init(&mq, "mqt", &msg_pool[0], 128 - sizeof(void*), sizeof(msg_pool), RT_IPC_FLAG_FIFO);
+
     init_thread = rt_thread_create("init", rt_init_thread_entry, RT_NULL, 1024, 21, 20);
     if(init_thread != RT_NULL)
         rt_thread_startup(init_thread);
-    
+
     return 0;
 }
 
diff --git a/bsp/mb9bf500r/board.c b/bsp/mb9bf500r/board.c
index f9f83d99ed..f52a5fa3a8 100644
--- a/bsp/mb9bf500r/board.c
+++ b/bsp/mb9bf500r/board.c
@@ -1,11 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2011 RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -33,13 +29,13 @@ extern const uint32_t SystemFrequency;
  */
 void SysTick_Handler(void)
 {
-	/* enter interrupt */
-	rt_interrupt_enter();
+    /* enter interrupt */
+    rt_interrupt_enter();
 
-	rt_tick_increase();
+    rt_tick_increase();
 
-	/* leave interrupt */
-	rt_interrupt_leave();
+    /* leave interrupt */
+    rt_interrupt_leave();
 }
 
 /**
diff --git a/bsp/mb9bf500r/board.h b/bsp/mb9bf500r/board.h
index ac5823cec1..2b419c759e 100644
--- a/bsp/mb9bf500r/board.h
+++ b/bsp/mb9bf500r/board.h
@@ -1,11 +1,7 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/mb9bf500r/cpuusage.c b/bsp/mb9bf500r/cpuusage.c
index 78e65bced6..df8ba2c240 100644
--- a/bsp/mb9bf500r/cpuusage.c
+++ b/bsp/mb9bf500r/cpuusage.c
@@ -1,3 +1,12 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
 #include 
 #include 
 #include "cpuusage.h"
@@ -9,73 +18,73 @@
 #include 
 #endif
 
-#define CPU_USAGE_CALC_TICK	10
-#define CPU_USAGE_LOOP		100
+#define CPU_USAGE_CALC_TICK 10
+#define CPU_USAGE_LOOP      100
 
 static rt_uint8_t  cpu_usage_major = 0, cpu_usage_minor= 0;
 static rt_uint32_t total_count = 0;
 
 static void cpu_usage_idle_hook()
 {
-	rt_tick_t tick;
-	rt_uint32_t count;
-	volatile rt_uint32_t loop;
+    rt_tick_t tick;
+    rt_uint32_t count;
+    volatile rt_uint32_t loop;
 
-	if (total_count == 0)
-	{
-		loop = 0;
+    if (total_count == 0)
+    {
+        loop = 0;
 
-		/* get total count */
-		rt_enter_critical();
-		tick = rt_tick_get();
-		while(rt_tick_get() - tick < CPU_USAGE_CALC_TICK)
-		{
-			total_count ++;
-			while (loop < CPU_USAGE_LOOP) loop ++;
-		}
-		rt_exit_critical();
-	}
+        /* get total count */
+        rt_enter_critical();
+        tick = rt_tick_get();
+        while(rt_tick_get() - tick < CPU_USAGE_CALC_TICK)
+        {
+            total_count ++;
+            while (loop < CPU_USAGE_LOOP) loop ++;
+        }
+        rt_exit_critical();
+    }
 
-	count = 0;
-	loop  = 0;
-	/* get CPU usage */
-	tick = rt_tick_get();
-	while (rt_tick_get() - tick < CPU_USAGE_CALC_TICK)
-	{
-		count ++;
-		while (loop < CPU_USAGE_LOOP) loop ++;
-	}
+    count = 0;
+    loop  = 0;
+    /* get CPU usage */
+    tick = rt_tick_get();
+    while (rt_tick_get() - tick < CPU_USAGE_CALC_TICK)
+    {
+        count ++;
+        while (loop < CPU_USAGE_LOOP) loop ++;
+    }
 
-	/* calculate major and minor */
-	if (count < total_count)
-	{
-		count = total_count - count;
-		cpu_usage_major = (count * 100) / total_count;
-		cpu_usage_minor = ((count * 100) % total_count) * 100 / total_count;
-	}
-	else
-	{
-		total_count = count;
+    /* calculate major and minor */
+    if (count < total_count)
+    {
+        count = total_count - count;
+        cpu_usage_major = (count * 100) / total_count;
+        cpu_usage_minor = ((count * 100) % total_count) * 100 / total_count;
+    }
+    else
+    {
+        total_count = count;
 
-		/* no CPU usage */
-		cpu_usage_major = 0;
-		cpu_usage_minor = 0;
-	}
+        /* no CPU usage */
+        cpu_usage_major = 0;
+        cpu_usage_minor = 0;
+    }
 }
 
 void cpu_usage_get(rt_uint8_t *major, rt_uint8_t *minor)
 {
-	RT_ASSERT(major != RT_NULL);
-	RT_ASSERT(minor != RT_NULL);
+    RT_ASSERT(major != RT_NULL);
+    RT_ASSERT(minor != RT_NULL);
 
-	*major = cpu_usage_major;
-	*minor = cpu_usage_minor;
+    *major = cpu_usage_major;
+    *minor = cpu_usage_minor;
 }
 
 void cpu_usage_init()
 {
-	/* set idle thread hook */
-	rt_thread_idle_sethook(cpu_usage_idle_hook);
+    /* set idle thread hook */
+    rt_thread_idle_sethook(cpu_usage_idle_hook);
 }
 extern struct rt_messagequeue mq;
 extern rt_thread_t info_tid;
@@ -83,12 +92,12 @@ static void cpu_thread_entry(void *parameter)
 {
 #ifdef RT_USING_RTGUI
     struct rtgui_event_command ecmd;
-    
+
     RTGUI_EVENT_COMMAND_INIT(&ecmd);
     ecmd.type = RTGUI_CMD_USER_INT;
     ecmd.command_id = CPU_UPDATE;
 #else
-	struct lcd_msg msg;
+    struct lcd_msg msg;
 #endif
 
     while (1)
@@ -96,10 +105,10 @@ static void cpu_thread_entry(void *parameter)
 #ifdef RT_USING_RTGUI
         rtgui_thread_send(info_tid, &ecmd.parent, sizeof(ecmd));
 #else
-		msg.type = CPU_MSG;
-		msg.major = cpu_usage_major;
-		msg.minor = cpu_usage_minor;
-		rt_mq_send(&mq, &msg, sizeof(msg));
+        msg.type = CPU_MSG;
+        msg.major = cpu_usage_major;
+        msg.minor = cpu_usage_minor;
+        rt_mq_send(&mq, &msg, sizeof(msg));
 #endif
         rt_thread_delay(20);
     }
@@ -110,6 +119,6 @@ void rt_hw_cpu_init(void)
 {
     cpu_usage_init();
     cpu_thread = rt_thread_create("cpu", cpu_thread_entry, RT_NULL, 384, 27, 5);
-    if(cpu_thread != RT_NULL) 
+    if(cpu_thread != RT_NULL)
         rt_thread_startup(cpu_thread);
 }
diff --git a/bsp/mb9bf500r/cpuusage.h b/bsp/mb9bf500r/cpuusage.h
index c7dd70c944..6a53481f3f 100644
--- a/bsp/mb9bf500r/cpuusage.h
+++ b/bsp/mb9bf500r/cpuusage.h
@@ -1,17 +1,13 @@
 /*
- * File      : cpuusage.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2011, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2011-03-03     lgnq
  */
- 
+
 #ifndef __CPUUSAGE_H__
 #define __CPUUSAGE_H__
 
diff --git a/bsp/mb9bf500r/font.h b/bsp/mb9bf500r/font.h
index bc56c0bb34..92253c59c3 100644
--- a/bsp/mb9bf500r/font.h
+++ b/bsp/mb9bf500r/font.h
@@ -1,263 +1,272 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
 #ifndef __FONT_H
 #define __FONT_H
 
 /*  Font definition  */
-#define	________	0x00
-#define	_______X	0x01
-#define	______X_	0x02
-#define	______XX	0x03
-#define	_____X__	0x04
-#define	_____X_X	0x05
-#define	_____XX_	0x06
-#define	_____XXX	0x07
-#define	____X___	0x08
-#define	____X__X	0x09
-#define	____X_X_	0x0a
-#define	____X_XX	0x0b
-#define	____XX__	0x0c
-#define	____XX_X	0x0d
-#define	____XXX_	0x0e
-#define	____XXXX	0x0f
-#define	___X____	0x10
-#define	___X___X	0x11
-#define	___X__X_	0x12
-#define	___X__XX	0x13
-#define	___X_X__	0x14
-#define	___X_X_X	0x15
-#define	___X_XX_	0x16
-#define	___X_XXX	0x17
-#define	___XX___	0x18
-#define	___XX__X	0x19
-#define	___XX_X_	0x1a
-#define	___XX_XX	0x1b
-#define	___XXX__	0x1c
-#define	___XXX_X	0x1d
-#define	___XXXX_	0x1e
-#define	___XXXXX	0x1f
-#define	__X_____	0x20
-#define	__X____X	0x21
-#define	__X___X_	0x22
-#define	__X___XX	0x23
-#define	__X__X__	0x24
-#define	__X__X_X	0x25
-#define	__X__XX_	0x26
-#define	__X__XXX	0x27
-#define	__X_X___	0x28
-#define	__X_X__X	0x29
-#define	__X_X_X_	0x2a
-#define	__X_X_XX	0x2b
-#define	__X_XX__	0x2c
-#define	__X_XX_X	0x2d
-#define	__X_XXX_	0x2e
-#define	__X_XXXX	0x2f
-#define	__XX____	0x30
-#define	__XX___X	0x31
-#define	__XX__X_	0x32
-#define	__XX__XX	0x33
-#define	__XX_X__	0x34
-#define	__XX_X_X	0x35
-#define	__XX_XX_	0x36
-#define	__XX_XXX	0x37
-#define	__XXX___	0x38
-#define	__XXX__X	0x39
-#define	__XXX_X_	0x3a
-#define	__XXX_XX	0x3b
-#define	__XXXX__	0x3c
-#define	__XXXX_X	0x3d
-#define	__XXXXX_	0x3e
-#define	__XXXXXX	0x3f
-#define	_X______	0x40
-#define	_X_____X	0x41
-#define	_X____X_	0x42
-#define	_X____XX	0x43
-#define	_X___X__	0x44
-#define	_X___X_X	0x45
-#define	_X___XX_	0x46
-#define	_X___XXX	0x47
-#define	_X__X___	0x48
-#define	_X__X__X	0x49
-#define	_X__X_X_	0x4a
-#define	_X__X_XX	0x4b
-#define	_X__XX__	0x4c
-#define	_X__XX_X	0x4d
-#define	_X__XXX_	0x4e
-#define	_X__XXXX	0x4f
-#define	_X_X____	0x50
-#define	_X_X___X	0x51
-#define	_X_X__X_	0x52
-#define	_X_X__XX	0x53
-#define	_X_X_X__	0x54
-#define	_X_X_X_X	0x55
-#define	_X_X_XX_	0x56
-#define	_X_X_XXX	0x57
-#define	_X_XX___	0x58
-#define	_X_XX__X	0x59
-#define	_X_XX_X_	0x5a
-#define	_X_XX_XX	0x5b
-#define	_X_XXX__	0x5c
-#define	_X_XXX_X	0x5d
-#define	_X_XXXX_	0x5e
-#define	_X_XXXXX	0x5f
-#define	_XX_____	0x60
-#define	_XX____X	0x61
-#define	_XX___X_	0x62
-#define	_XX___XX	0x63
-#define	_XX__X__	0x64
-#define	_XX__X_X	0x65
-#define	_XX__XX_	0x66
-#define	_XX__XXX	0x67
-#define	_XX_X___	0x68
-#define	_XX_X__X	0x69
-#define	_XX_X_X_	0x6a
-#define	_XX_X_XX	0x6b
-#define	_XX_XX__	0x6c
-#define	_XX_XX_X	0x6d
-#define	_XX_XXX_	0x6e
-#define	_XX_XXXX	0x6f
-#define	_XXX____	0x70
-#define	_XXX___X	0x71
-#define	_XXX__X_	0x72
-#define	_XXX__XX	0x73
-#define	_XXX_X__	0x74
-#define	_XXX_X_X	0x75
-#define	_XXX_XX_	0x76
-#define	_XXX_XXX	0x77
-#define	_XXXX___	0x78
-#define	_XXXX__X	0x79
-#define	_XXXX_X_	0x7a
-#define	_XXXX_XX	0x7b
-#define	_XXXXX__	0x7c
-#define	_XXXXX_X	0x7d
-#define	_XXXXXX_	0x7e
-#define	_XXXXXXX	0x7f
-#define	X_______	0x80
-#define	X______X	0x81
-#define	X_____X_	0x82
-#define	X_____XX	0x83
-#define	X____X__	0x84
-#define	X____X_X	0x85
-#define	X____XX_	0x86
-#define	X____XXX	0x87
-#define	X___X___	0x88
-#define	X___X__X	0x89
-#define	X___X_X_	0x8a
-#define	X___X_XX	0x8b
-#define	X___XX__	0x8c
-#define	X___XX_X	0x8d
-#define	X___XXX_	0x8e
-#define	X___XXXX	0x8f
-#define	X__X____	0x90
-#define	X__X___X	0x91
-#define	X__X__X_	0x92
-#define	X__X__XX	0x93
-#define	X__X_X__	0x94
-#define	X__X_X_X	0x95
-#define	X__X_XX_	0x96
-#define	X__X_XXX	0x97
-#define	X__XX___	0x98
-#define	X__XX__X	0x99
-#define	X__XX_X_	0x9a
-#define X__XX_XX	0x9b
-#define X__XXX__	0x9c
-#define X__XXX_X	0x9d
-#define	X__XXXX_	0x9e
-#define	X__XXXXX	0x9f
-#define	X_X_____	0xa0
-#define	X_X____X	0xa1
-#define	X_X___X_	0xa2
-#define	X_X___XX	0xa3
-#define	X_X__X__	0xa4
-#define	X_X__X_X	0xa5
-#define	X_X__XX_	0xa6
-#define	X_X__XXX	0xa7
-#define	X_X_X___	0xa8
-#define	X_X_X__X	0xa9
-#define	X_X_X_X_	0xaa
-#define	X_X_X_XX	0xab
-#define	X_X_XX__	0xac
-#define	X_X_XX_X	0xad
-#define	X_X_XXX_	0xae
-#define	X_X_XXXX	0xaf
-#define	X_XX____	0xb0
-#define X_XX___X	0xb1
-#define	X_XX__X_	0xb2
-#define	X_XX__XX	0xb3
-#define	X_XX_X__	0xb4
-#define	X_XX_X_X	0xb5
-#define	X_XX_XX_	0xb6
-#define	X_XX_XXX	0xb7
-#define	X_XXX___	0xb8
-#define	X_XXX__X	0xb9
-#define	X_XXX_X_	0xba
-#define	X_XXX_XX	0xbb
-#define	X_XXXX__	0xbc
-#define	X_XXXX_X	0xbd
-#define	X_XXXXX_	0xbe
-#define	X_XXXXXX	0xbf
-#define	XX______	0xc0
-#define	XX_____X	0xc1
-#define	XX____X_	0xc2
-#define	XX____XX	0xc3
-#define	XX___X__	0xc4
-#define	XX___X_X	0xc5
-#define	XX___XX_	0xc6
-#define	XX___XXX	0xc7
-#define	XX__X___	0xc8
-#define	XX__X__X	0xc9
-#define	XX__X_X_	0xca
-#define	XX__X_XX	0xcb
-#define	XX__XX__	0xcc
-#define	XX__XX_X	0xcd
-#define	XX__XXX_	0xce
-#define XX__XXXX	0xcf
-#define	XX_X____	0xd0
-#define	XX_X___X	0xd1
-#define	XX_X__X_	0xd2
-#define	XX_X__XX	0xd3
-#define	XX_X_X__	0xd4
-#define	XX_X_X_X	0xd5
-#define	XX_X_XX_	0xd6
-#define	XX_X_XXX	0xd7
-#define	XX_XX___	0xd8
-#define	XX_XX__X	0xd9
-#define	XX_XX_X_	0xda
-#define	XX_XX_XX	0xdb
-#define	XX_XXX__	0xdc
-#define	XX_XXX_X	0xdd
-#define	XX_XXXX_	0xde
-#define	XX_XXXXX	0xdf
-#define	XXX_____	0xe0
-#define	XXX____X	0xe1
-#define	XXX___X_	0xe2
-#define	XXX___XX	0xe3
-#define	XXX__X__	0xe4
-#define	XXX__X_X	0xe5
-#define	XXX__XX_	0xe6
-#define	XXX__XXX	0xe7
-#define	XXX_X___	0xe8
-#define	XXX_X__X	0xe9
-#define	XXX_X_X_	0xea
-#define	XXX_X_XX	0xeb
-#define	XXX_XX__	0xec
-#define	XXX_XX_X	0xed
-#define	XXX_XXX_	0xee
-#define	XXX_XXXX	0xef
-#define	XXXX____	0xf0
-#define	XXXX___X	0xf1
-#define	XXXX__X_	0xf2
-#define	XXXX__XX	0xf3
-#define	XXXX_X__	0xf4
-#define	XXXX_X_X	0xf5
-#define	XXXX_XX_	0xf6
-#define	XXXX_XXX	0xf7
-#define	XXXXX___	0xf8
-#define	XXXXX__X	0xf9
-#define	XXXXX_X_	0xfa
-#define	XXXXX_XX	0xfb
-#define	XXXXXX__	0xfc
-#define	XXXXXX_X	0xfd
-#define	XXXXXXX_	0xfe
-#define	XXXXXXXX	0xff
+#define ________    0x00
+#define _______X    0x01
+#define ______X_    0x02
+#define ______XX    0x03
+#define _____X__    0x04
+#define _____X_X    0x05
+#define _____XX_    0x06
+#define _____XXX    0x07
+#define ____X___    0x08
+#define ____X__X    0x09
+#define ____X_X_    0x0a
+#define ____X_XX    0x0b
+#define ____XX__    0x0c
+#define ____XX_X    0x0d
+#define ____XXX_    0x0e
+#define ____XXXX    0x0f
+#define ___X____    0x10
+#define ___X___X    0x11
+#define ___X__X_    0x12
+#define ___X__XX    0x13
+#define ___X_X__    0x14
+#define ___X_X_X    0x15
+#define ___X_XX_    0x16
+#define ___X_XXX    0x17
+#define ___XX___    0x18
+#define ___XX__X    0x19
+#define ___XX_X_    0x1a
+#define ___XX_XX    0x1b
+#define ___XXX__    0x1c
+#define ___XXX_X    0x1d
+#define ___XXXX_    0x1e
+#define ___XXXXX    0x1f
+#define __X_____    0x20
+#define __X____X    0x21
+#define __X___X_    0x22
+#define __X___XX    0x23
+#define __X__X__    0x24
+#define __X__X_X    0x25
+#define __X__XX_    0x26
+#define __X__XXX    0x27
+#define __X_X___    0x28
+#define __X_X__X    0x29
+#define __X_X_X_    0x2a
+#define __X_X_XX    0x2b
+#define __X_XX__    0x2c
+#define __X_XX_X    0x2d
+#define __X_XXX_    0x2e
+#define __X_XXXX    0x2f
+#define __XX____    0x30
+#define __XX___X    0x31
+#define __XX__X_    0x32
+#define __XX__XX    0x33
+#define __XX_X__    0x34
+#define __XX_X_X    0x35
+#define __XX_XX_    0x36
+#define __XX_XXX    0x37
+#define __XXX___    0x38
+#define __XXX__X    0x39
+#define __XXX_X_    0x3a
+#define __XXX_XX    0x3b
+#define __XXXX__    0x3c
+#define __XXXX_X    0x3d
+#define __XXXXX_    0x3e
+#define __XXXXXX    0x3f
+#define _X______    0x40
+#define _X_____X    0x41
+#define _X____X_    0x42
+#define _X____XX    0x43
+#define _X___X__    0x44
+#define _X___X_X    0x45
+#define _X___XX_    0x46
+#define _X___XXX    0x47
+#define _X__X___    0x48
+#define _X__X__X    0x49
+#define _X__X_X_    0x4a
+#define _X__X_XX    0x4b
+#define _X__XX__    0x4c
+#define _X__XX_X    0x4d
+#define _X__XXX_    0x4e
+#define _X__XXXX    0x4f
+#define _X_X____    0x50
+#define _X_X___X    0x51
+#define _X_X__X_    0x52
+#define _X_X__XX    0x53
+#define _X_X_X__    0x54
+#define _X_X_X_X    0x55
+#define _X_X_XX_    0x56
+#define _X_X_XXX    0x57
+#define _X_XX___    0x58
+#define _X_XX__X    0x59
+#define _X_XX_X_    0x5a
+#define _X_XX_XX    0x5b
+#define _X_XXX__    0x5c
+#define _X_XXX_X    0x5d
+#define _X_XXXX_    0x5e
+#define _X_XXXXX    0x5f
+#define _XX_____    0x60
+#define _XX____X    0x61
+#define _XX___X_    0x62
+#define _XX___XX    0x63
+#define _XX__X__    0x64
+#define _XX__X_X    0x65
+#define _XX__XX_    0x66
+#define _XX__XXX    0x67
+#define _XX_X___    0x68
+#define _XX_X__X    0x69
+#define _XX_X_X_    0x6a
+#define _XX_X_XX    0x6b
+#define _XX_XX__    0x6c
+#define _XX_XX_X    0x6d
+#define _XX_XXX_    0x6e
+#define _XX_XXXX    0x6f
+#define _XXX____    0x70
+#define _XXX___X    0x71
+#define _XXX__X_    0x72
+#define _XXX__XX    0x73
+#define _XXX_X__    0x74
+#define _XXX_X_X    0x75
+#define _XXX_XX_    0x76
+#define _XXX_XXX    0x77
+#define _XXXX___    0x78
+#define _XXXX__X    0x79
+#define _XXXX_X_    0x7a
+#define _XXXX_XX    0x7b
+#define _XXXXX__    0x7c
+#define _XXXXX_X    0x7d
+#define _XXXXXX_    0x7e
+#define _XXXXXXX    0x7f
+#define X_______    0x80
+#define X______X    0x81
+#define X_____X_    0x82
+#define X_____XX    0x83
+#define X____X__    0x84
+#define X____X_X    0x85
+#define X____XX_    0x86
+#define X____XXX    0x87
+#define X___X___    0x88
+#define X___X__X    0x89
+#define X___X_X_    0x8a
+#define X___X_XX    0x8b
+#define X___XX__    0x8c
+#define X___XX_X    0x8d
+#define X___XXX_    0x8e
+#define X___XXXX    0x8f
+#define X__X____    0x90
+#define X__X___X    0x91
+#define X__X__X_    0x92
+#define X__X__XX    0x93
+#define X__X_X__    0x94
+#define X__X_X_X    0x95
+#define X__X_XX_    0x96
+#define X__X_XXX    0x97
+#define X__XX___    0x98
+#define X__XX__X    0x99
+#define X__XX_X_    0x9a
+#define X__XX_XX    0x9b
+#define X__XXX__    0x9c
+#define X__XXX_X    0x9d
+#define X__XXXX_    0x9e
+#define X__XXXXX    0x9f
+#define X_X_____    0xa0
+#define X_X____X    0xa1
+#define X_X___X_    0xa2
+#define X_X___XX    0xa3
+#define X_X__X__    0xa4
+#define X_X__X_X    0xa5
+#define X_X__XX_    0xa6
+#define X_X__XXX    0xa7
+#define X_X_X___    0xa8
+#define X_X_X__X    0xa9
+#define X_X_X_X_    0xaa
+#define X_X_X_XX    0xab
+#define X_X_XX__    0xac
+#define X_X_XX_X    0xad
+#define X_X_XXX_    0xae
+#define X_X_XXXX    0xaf
+#define X_XX____    0xb0
+#define X_XX___X    0xb1
+#define X_XX__X_    0xb2
+#define X_XX__XX    0xb3
+#define X_XX_X__    0xb4
+#define X_XX_X_X    0xb5
+#define X_XX_XX_    0xb6
+#define X_XX_XXX    0xb7
+#define X_XXX___    0xb8
+#define X_XXX__X    0xb9
+#define X_XXX_X_    0xba
+#define X_XXX_XX    0xbb
+#define X_XXXX__    0xbc
+#define X_XXXX_X    0xbd
+#define X_XXXXX_    0xbe
+#define X_XXXXXX    0xbf
+#define XX______    0xc0
+#define XX_____X    0xc1
+#define XX____X_    0xc2
+#define XX____XX    0xc3
+#define XX___X__    0xc4
+#define XX___X_X    0xc5
+#define XX___XX_    0xc6
+#define XX___XXX    0xc7
+#define XX__X___    0xc8
+#define XX__X__X    0xc9
+#define XX__X_X_    0xca
+#define XX__X_XX    0xcb
+#define XX__XX__    0xcc
+#define XX__XX_X    0xcd
+#define XX__XXX_    0xce
+#define XX__XXXX    0xcf
+#define XX_X____    0xd0
+#define XX_X___X    0xd1
+#define XX_X__X_    0xd2
+#define XX_X__XX    0xd3
+#define XX_X_X__    0xd4
+#define XX_X_X_X    0xd5
+#define XX_X_XX_    0xd6
+#define XX_X_XXX    0xd7
+#define XX_XX___    0xd8
+#define XX_XX__X    0xd9
+#define XX_XX_X_    0xda
+#define XX_XX_XX    0xdb
+#define XX_XXX__    0xdc
+#define XX_XXX_X    0xdd
+#define XX_XXXX_    0xde
+#define XX_XXXXX    0xdf
+#define XXX_____    0xe0
+#define XXX____X    0xe1
+#define XXX___X_    0xe2
+#define XXX___XX    0xe3
+#define XXX__X__    0xe4
+#define XXX__X_X    0xe5
+#define XXX__XX_    0xe6
+#define XXX__XXX    0xe7
+#define XXX_X___    0xe8
+#define XXX_X__X    0xe9
+#define XXX_X_X_    0xea
+#define XXX_X_XX    0xeb
+#define XXX_XX__    0xec
+#define XXX_XX_X    0xed
+#define XXX_XXX_    0xee
+#define XXX_XXXX    0xef
+#define XXXX____    0xf0
+#define XXXX___X    0xf1
+#define XXXX__X_    0xf2
+#define XXXX__XX    0xf3
+#define XXXX_X__    0xf4
+#define XXXX_X_X    0xf5
+#define XXXX_XX_    0xf6
+#define XXXX_XXX    0xf7
+#define XXXXX___    0xf8
+#define XXXXX__X    0xf9
+#define XXXXX_X_    0xfa
+#define XXXXX_XX    0xfb
+#define XXXXXX__    0xfc
+#define XXXXXX_X    0xfd
+#define XXXXXXX_    0xfe
+#define XXXXXXXX    0xff
 
 
 
@@ -272,8 +281,8 @@ const unsigned char  FONTTYPE8_8[][8] = {
    ________,
    ________,
    ________,
-   ________} 
-    
+   ________}
+
 /*  0  */
  ,{
    __XXX___,
@@ -283,7 +292,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    XX___XX_,
    _XX_XX__,
    __XXX___,
-   ________}  
+   ________}
 
 /*  1  */
  ,{
@@ -294,7 +303,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    ___XX___,
    ___XX___,
    _XXXXXX_,
-   ________}  
+   ________}
 
 /*  2  */
  ,{
@@ -305,7 +314,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    __XX____,
    _XX__XX_,
    XXXXXXX_,
-   ________}  
+   ________}
 
 /*  3  */
  ,{
@@ -316,7 +325,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    _____XX_,
    XX___XX_,
    _XXXXX__,
-   ________}  
+   ________}
 
 /*  4  */
  ,{
@@ -327,7 +336,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    XXXXXXX_,
    ____XX__,
    ___XXXX_,
-   ________}  
+   ________}
 
 /*  5  */
  ,{
@@ -338,7 +347,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    _____XX_,
    XX___XX_,
    _XXXXX__,
-   ________}  
+   ________}
 
 /*  6  */
  ,{
@@ -349,7 +358,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    XX___XX_,
    XX___XX_,
    _XXXXX__,
-   ________}  
+   ________}
 
 /*  7  */
  ,{
@@ -360,7 +369,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    __XX____,
    __XX____,
    __XX____,
-   ________}  
+   ________}
 
 /*  8  */
  ,{
@@ -371,7 +380,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    XX___XX_,
    XX___XX_,
    _XXXXX__,
-   ________}  
+   ________}
 
 /*  9  */
  ,{
@@ -382,7 +391,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    _____XX_,
    ____XX__,
    _XXXX___,
-   ________}  
+   ________}
 
 /*  A  */
  ,{
@@ -393,7 +402,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    XX___XX_,
    XX___XX_,
    XX___XX_,
-   ________}  
+   ________}
 
 /*  B  */
  ,{
@@ -404,7 +413,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    _XX__XX_,
    _XX__XX_,
    XXXXXX__,
-   ________}  
+   ________}
 
 /*  C  */
  ,{
@@ -415,7 +424,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    XX______,
    _XX__XX_,
    __XXXX__,
-   ________}  
+   ________}
 
 /*  D  */
  ,{
@@ -426,7 +435,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    _XX__XX_,
    _XX_XX__,
    XXXXX___,
-   ________}  
+   ________}
 
 /*  E  */
  ,{
@@ -437,7 +446,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    _XX_X___,
    _XX___X_,
    XXXXXXX_,
-   ________}  
+   ________}
 
 /*  F  */
  ,{
@@ -448,7 +457,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    _XX_X___,
    _XX_____,
    XXXX____,
-   ________}  
+   ________}
 
 /*  G  */
  ,{
@@ -459,7 +468,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    XX__XXX_,
    _XX__XX_,
    __XXX_X_,
-   ________}  
+   ________}
 
 /*  H  */
  ,{
@@ -470,7 +479,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    XX___XX_,
    XX___XX_,
    XX___XX_,
-   ________}  
+   ________}
 
 /*  I  */
  ,{
@@ -481,7 +490,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    ___XX___,
    ___XX___,
    __XXXX__,
-   ________}  
+   ________}
 
 /*  J  */
  ,{
@@ -492,7 +501,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    XX__XX__,
    XX__XX__,
    _XXXX___,
-   ________}  
+   ________}
 
 /*  K  */
  ,{
@@ -503,7 +512,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    _XX_XX__,
    _XX__XX_,
    XXX__XX_,
-   ________}  
+   ________}
 
 /*  L  */
  ,{
@@ -514,7 +523,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    _XX___X_,
    _XX__XX_,
    XXXXXXX_,
-   ________}  
+   ________}
 
 /*  M  */
  ,{
@@ -525,7 +534,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    XX_X_XX_,
    XX___XX_,
    XX___XX_,
-   ________}  
+   ________}
 
 /*  N  */
  ,{
@@ -536,7 +545,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    XX__XXX_,
    XX___XX_,
    XX___XX_,
-   ________}  
+   ________}
 
 /*  O  */
  ,{
@@ -547,7 +556,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    XX___XX_,
    XX___XX_,
    _XXXXX__,
-   ________}  
+   ________}
 
 /*  P  */
  ,{
@@ -558,7 +567,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    _XX_____,
    _XX_____,
    XXXX____,
-   ________}  
+   ________}
 
 /*  Q  */
  ,{
@@ -569,7 +578,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    XX___XX_,
    XX__XXX_,
    _XXXXX__,
-   ____XXX_}  
+   ____XXX_}
 
 /*  R  */
  ,{
@@ -580,7 +589,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    _XX_XX__,
    _XX__XX_,
    XXX__XX_,
-   ________}  
+   ________}
 
 /*  S  */
  ,{
@@ -591,7 +600,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    ____XX__,
    _XX__XX_,
    __XXXX__,
-   ________}  
+   ________}
 
 /*  T  */
  ,{
@@ -602,7 +611,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    ___XX___,
    ___XX___,
    __XXXX__,
-   ________}  
+   ________}
 
 /*  U  */
  ,{
@@ -613,7 +622,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    XX___XX_,
    XX___XX_,
    _XXXXX__,
-   ________}  
+   ________}
 
 /*  V  */
  ,{
@@ -624,7 +633,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    XX___XX_,
    _XX_XX__,
    __XXX___,
-   ________}  
+   ________}
 
 /*  W  */
  ,{
@@ -635,7 +644,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    XX_X_XX_,
    XXXXXXX_,
    _XX_XX__,
-   ________}  
+   ________}
 
 /*  X  */
  ,{
@@ -646,7 +655,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    _XX_XX__,
    XX___XX_,
    XX___XX_,
-   ________}  
+   ________}
 
 /*  Y  */
  ,{
@@ -657,7 +666,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    ___XX___,
    ___XX___,
    __XXXX__,
-   ________}  
+   ________}
 
 /*  Z  */
  ,{
@@ -668,7 +677,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    __XX__X_,
    _XX__XX_,
    XXXXXXX_,
-   ________}  
+   ________}
 
 /*  a  */
  ,{
@@ -679,7 +688,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    _XXXXX__,
    XX__XX__,
    _XXX_XX_,
-   ________}  
+   ________}
 
 /*  b  */
  ,{
@@ -690,7 +699,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    _XX__XX_,
    _XX__XX_,
    XX_XXX__,
-   ________}  
+   ________}
 
 /*  c  */
  ,{
@@ -701,7 +710,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    XX______,
    XX___XX_,
    _XXXXX__,
-   ________}  
+   ________}
 
 /*  d  */
  ,{
@@ -712,7 +721,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    XX__XX__,
    XX__XX__,
    _XXX_XX_,
-   ________}  
+   ________}
 
 /*  e  */
  ,{
@@ -723,7 +732,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    XXXXXXX_,
    XX______,
    _XXXXX__,
-   ________}  
+   ________}
 
 /*  f  */
  ,{
@@ -734,7 +743,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    _XX_____,
    _XX_____,
    XXXX____,
-   ________}  
+   ________}
 
 /*  g  */
  ,{
@@ -745,7 +754,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    XX__XX__,
    _XXXXX__,
    ____XX__,
-   XXXXX___}  
+   XXXXX___}
 
 /*  h  */
  ,{
@@ -756,7 +765,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    _XX__XX_,
    _XX__XX_,
    XXX__XX_,
-   ________}  
+   ________}
 
 /*  i  */
  ,{
@@ -767,7 +776,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    ___XX___,
    ___XX___,
    __XXXX__,
-   ________}  
+   ________}
 
 /*  j  */
  ,{
@@ -778,7 +787,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    _____XX_,
    _XX__XX_,
    _XX__XX_,
-   __XXXX__}  
+   __XXXX__}
 
 /*  k  */
  ,{
@@ -789,7 +798,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    _XXXX___,
    _XX_XX__,
    XXX__XX_,
-   ________}  
+   ________}
 
 /*  l  */
  ,{
@@ -800,7 +809,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    ___XX___,
    ___XX___,
    __XXXX__,
-   ________}  
+   ________}
 
 /*  m  */
  ,{
@@ -811,7 +820,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    XX_X_XX_,
    XX_X_XX_,
    XX_X_XX_,
-   ________}  
+   ________}
 
 /*  n  */
  ,{
@@ -822,7 +831,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    _XX__XX_,
    _XX__XX_,
    _XX__XX_,
-   ________}  
+   ________}
 
 /*  o  */
  ,{
@@ -833,7 +842,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    XX___XX_,
    XX___XX_,
    _XXXXX__,
-   ________}  
+   ________}
 
 /*  p  */
  ,{
@@ -844,7 +853,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    _XX__XX_,
    _XXXXX__,
    _XX_____,
-   XXXX____}  
+   XXXX____}
 
 /*  q  */
  ,{
@@ -855,7 +864,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    XX__XX__,
    _XXXXX__,
    ____XX__,
-   ___XXXX_}  
+   ___XXXX_}
 
 /*  r  */
  ,{
@@ -866,7 +875,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    _XX_____,
    _XX_____,
    XXXX____,
-   ________}  
+   ________}
 
 /*  s  */
  ,{
@@ -877,7 +886,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    _XXXXX__,
    _____XX_,
    XXXXXX__,
-   ________}  
+   ________}
 
 /*  t  */
  ,{
@@ -888,7 +897,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    __XX____,
    __XX_XX_,
    ___XXX__,
-   ________}  
+   ________}
 
 /*  u  */
  ,{
@@ -899,7 +908,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    XX__XX__,
    XX__XX__,
    _XXX_XX_,
-   ________}  
+   ________}
 
 /*  v  */
  ,{
@@ -910,7 +919,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    XX___XX_,
    _XX_XX__,
    __XXX___,
-   ________}  
+   ________}
 
 /*  w  */
  ,{
@@ -921,7 +930,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    XX_X_XX_,
    XXXXXXX_,
    _XX_XX__,
-   ________}  
+   ________}
 
 /*  x  */
  ,{
@@ -932,7 +941,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    __XXX___,
    _XX_XX__,
    XX___XX_,
-   ________}  
+   ________}
 
 /*  y  */
  ,{
@@ -943,7 +952,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    XX___XX_,
    _XXXXXX_,
    _____XX_,
-   XXXXXX__}  
+   XXXXXX__}
 
 /*  z  */
  ,{
@@ -954,7 +963,7 @@ const unsigned char  FONTTYPE8_8[][8] = {
    ___XX___,
    __XX__X_,
    _XXXXXX_,
-   ________} 
+   ________}
 
 };
 
diff --git a/bsp/mb9bf500r/info.c b/bsp/mb9bf500r/info.c
index 6e76c95e59..fcf514f1b0 100644
--- a/bsp/mb9bf500r/info.c
+++ b/bsp/mb9bf500r/info.c
@@ -1,3 +1,12 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
 #include 
 
 #ifdef RT_USING_RTGUI
@@ -15,37 +24,37 @@ extern rt_uint16_t adc_value;
 static rt_uint8_t index = 0 ;
 static rt_bool_t view_event_handler(struct rtgui_widget* widget, struct rtgui_event* event)
 {
-	if (event->type == RTGUI_EVENT_PAINT)
-	{
-		struct rtgui_dc* dc;
-		struct rtgui_rect rect;
+    if (event->type == RTGUI_EVENT_PAINT)
+    {
+        struct rtgui_dc* dc;
+        struct rtgui_rect rect;
 
-		dc = rtgui_dc_begin_drawing(widget);
-		if (dc == RT_NULL) 
+        dc = rtgui_dc_begin_drawing(widget);
+        if (dc == RT_NULL)
             return RT_FALSE;
-		rtgui_widget_get_rect(widget, &rect);
-
-		rtgui_dc_fill_rect(dc, &rect);
-		rect.x2 -= 1; rect.y2 -= 1;
-		rtgui_dc_draw_hline(dc, rect.x1, rect.x2, rect.y1);
-		rtgui_dc_draw_vline(dc, rect.x1, rect.y1, rect.y2);
-
-		rtgui_dc_draw_hline(dc, rect.x1, rect.x2, rect.y2);
-		rtgui_dc_draw_vline(dc, rect.x2, rect.y1, rect.y2 + 1);
-        
-        /* shrink border */
-		rtgui_rect_inflate(&rect, -1);
-        
-		/* draw text */
         rtgui_widget_get_rect(widget, &rect);
-        rect.y1 += 25;        
+
+        rtgui_dc_fill_rect(dc, &rect);
+        rect.x2 -= 1; rect.y2 -= 1;
+        rtgui_dc_draw_hline(dc, rect.x1, rect.x2, rect.y1);
+        rtgui_dc_draw_vline(dc, rect.x1, rect.y1, rect.y2);
+
+        rtgui_dc_draw_hline(dc, rect.x1, rect.x2, rect.y2);
+        rtgui_dc_draw_vline(dc, rect.x2, rect.y1, rect.y2 + 1);
+
+        /* shrink border */
+        rtgui_rect_inflate(&rect, -1);
+
+        /* draw text */
+        rtgui_widget_get_rect(widget, &rect);
+        rect.y1 += 25;
         rtgui_dc_draw_text(dc, "  FM3 Easy Kit Demo", &rect);
         rect.y1 += 10;
         rtgui_dc_draw_text(dc, "  rt-thread / RTGUI", &rect);
-		rtgui_dc_end_drawing(dc, RT_TRUE);
+        rtgui_dc_end_drawing(dc, RT_TRUE);
 
-		return RT_FALSE;
-	}
+        return RT_FALSE;
+    }
     else if (event->type == RTGUI_EVENT_KBD)
     {
         struct rtgui_dc* dc;
@@ -67,18 +76,18 @@ static rt_bool_t view_event_handler(struct rtgui_widget* widget, struct rtgui_ev
                 break;
                 case RTGUIK_UP:
                 rt_sprintf(key_str, "%s", "U");
-                break;                
+                break;
                 default:
                 rt_sprintf(key_str, "%s", "S");
                 break;
             }
             dc = rtgui_dc_begin_drawing(widget);
-            if (dc == RT_NULL) 
+            if (dc == RT_NULL)
                 return RT_FALSE;
             rect.x1 = 118;
-            rect.y1 = 1;  
+            rect.y1 = 1;
             rect.x2 = 127;
-            rect.y2 = 10;       
+            rect.y2 = 10;
             rtgui_dc_fill_rect(dc, &rect);
             rtgui_dc_draw_text(dc, key_str, &rect);
             rtgui_dc_end_drawing(dc, RT_TRUE);
@@ -86,12 +95,12 @@ static rt_bool_t view_event_handler(struct rtgui_widget* widget, struct rtgui_ev
         else if (ekbd->type == RTGUI_KEYUP)
         {
             dc = rtgui_dc_begin_drawing(widget);
-            if (dc == RT_NULL) 
+            if (dc == RT_NULL)
                 return RT_FALSE;
             rect.x1 = 118;
-            rect.y1 = 1;  
+            rect.y1 = 1;
             rect.x2 = 127;
-            rect.y2 = 10;       
+            rect.y2 = 10;
             rtgui_dc_fill_rect(dc, &rect);
             //rtgui_dc_draw_text(dc, key_str, &rect);
             rtgui_dc_end_drawing(dc, RT_TRUE);
@@ -105,38 +114,38 @@ static rt_bool_t view_event_handler(struct rtgui_widget* widget, struct rtgui_ev
         struct rtgui_event_command* ecmd;
         rt_uint8_t major,minor;
         dc = rtgui_dc_begin_drawing(widget);
-        if (dc == RT_NULL) 
+        if (dc == RT_NULL)
             return RT_FALSE;
-            
+
         ecmd = (struct rtgui_event_command*)event;
         switch (ecmd->command_id)
-        {   
+        {
             case ADC_UPDATE:
                 rect.x1 = 1;
-                rect.y1 = 1;  
+                rect.y1 = 1;
                 rect.x2 = 117;
-                rect.y2 = 10;       
-                rtgui_dc_fill_rect(dc, &rect);     
-			    rt_sprintf(str, "ADC = %d mv", adc_value);
-			    rtgui_dc_draw_text(dc, str, &rect);	
+                rect.y2 = 10;
+                rtgui_dc_fill_rect(dc, &rect);
+                rt_sprintf(str, "ADC = %d mv", adc_value);
+                rtgui_dc_draw_text(dc, str, &rect);
             break;
             case CPU_UPDATE:
                 cpu_usage_get(&major, &minor);
                 rect.x1 = 1;
-                rect.y1 = 12;  
+                rect.y1 = 12;
                 rect.x2 = 127;
-                rect.y2 = 22;       
-                rtgui_dc_fill_rect(dc, &rect);     
-			    rt_sprintf(str, "CPU : %d.%d%", major, minor);
-			    rtgui_dc_draw_text(dc, str, &rect);
+                rect.y2 = 22;
+                rtgui_dc_fill_rect(dc, &rect);
+                rt_sprintf(str, "CPU : %d.%d%", major, minor);
+                rtgui_dc_draw_text(dc, str, &rect);
 
-                rect.y1 = 23;  
-                rect.y2 = 63;                 
+                rect.y1 = 23;
+                rect.y2 = 63;
                 index++;
                 if (index == 127)
-                {    
+                {
                     index = 1;
-                    rtgui_dc_fill_rect(dc, &rect);     
+                    rtgui_dc_fill_rect(dc, &rect);
                 }
                 if (major>40)
                     rtgui_dc_draw_vline(dc, index, rect.y1, rect.y2);
@@ -144,42 +153,42 @@ static rt_bool_t view_event_handler(struct rtgui_widget* widget, struct rtgui_ev
                     rtgui_dc_draw_vline(dc, index, rect.y2-major, rect.y2);
                 break;
         }
-        rtgui_dc_end_drawing(dc, RT_TRUE); 
+        rtgui_dc_end_drawing(dc, RT_TRUE);
     }
 
-	return rtgui_view_event_handler(widget, event);
+    return rtgui_view_event_handler(widget, event);
 }
 
 static void info_entry(void* parameter)
 {
-	rt_mq_t mq;
-	struct rtgui_view* view;
-	struct rtgui_workbench* workbench;
+    rt_mq_t mq;
+    struct rtgui_view* view;
+    struct rtgui_workbench* workbench;
 
-	mq = rt_mq_create("qInfo", 256, 4, RT_IPC_FLAG_FIFO);
-	rtgui_thread_register(rt_thread_self(), mq);
+    mq = rt_mq_create("qInfo", 256, 4, RT_IPC_FLAG_FIFO);
+    rtgui_thread_register(rt_thread_self(), mq);
 
-	workbench = rtgui_workbench_create("info", "workbench");
-	if(workbench == RT_NULL) 
+    workbench = rtgui_workbench_create("info", "workbench");
+    if(workbench == RT_NULL)
         return;
 
-	view = rtgui_view_create("view");
-	RTGUI_WIDGET_BACKGROUND(RTGUI_WIDGET(view)) = white;
+    view = rtgui_view_create("view");
+    RTGUI_WIDGET_BACKGROUND(RTGUI_WIDGET(view)) = white;
     RTGUI_WIDGET_FOREGROUND(RTGUI_WIDGET(view)) = black;
-	rtgui_widget_set_event_handler(RTGUI_WIDGET(view), view_event_handler);
+    rtgui_widget_set_event_handler(RTGUI_WIDGET(view), view_event_handler);
 
-	rtgui_workbench_add_view(workbench, view);
+    rtgui_workbench_add_view(workbench, view);
     /* this view can be focused */
     RTGUI_WIDGET(view)->flag |= RTGUI_WIDGET_FLAG_FOCUSABLE;
     /* set widget focus */
-    rtgui_widget_focus(RTGUI_WIDGET(view));    
+    rtgui_widget_focus(RTGUI_WIDGET(view));
 
-	rtgui_view_show(view, RT_FALSE);
+    rtgui_view_show(view, RT_FALSE);
 
-	rtgui_workbench_event_loop(workbench);
+    rtgui_workbench_event_loop(workbench);
 
-	rtgui_thread_deregister(rt_thread_self());
-	rt_mq_delete(mq);
+    rtgui_thread_deregister(rt_thread_self());
+    rt_mq_delete(mq);
 }
 
 rt_thread_t info_tid;
@@ -195,10 +204,9 @@ void info_init()
 void rtgui_startup()
 {
     rtgui_rect_t rect;
-    
-	/* GUIϵͳʼ */
+
     rtgui_system_server_init();
-        
+
     /* register dock panel */
     rect.x1 = 0;
     rect.y1 = 0;
@@ -206,9 +214,9 @@ void rtgui_startup()
     rect.y2 = 64;
     rtgui_panel_register("info", &rect);
     rtgui_panel_set_default_focused("info");
-    
-	/* info workbench */
-	info_init();
+
+    /*init info workbench */
+    info_init();
 }
 
 #endif
diff --git a/bsp/mb9bf500r/key.c b/bsp/mb9bf500r/key.c
index 6a574a1251..1886e72974 100644
--- a/bsp/mb9bf500r/key.c
+++ b/bsp/mb9bf500r/key.c
@@ -1,15 +1,11 @@
 /*
- * File      : key.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2011, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date                Author       Notes
- * 2011-03-03     	   lgnq
+ * 2011-03-03          lgnq
  */
 
 #include 
@@ -25,7 +21,7 @@ static void key_io_init(void)
 {
     /*Select CPIO function*/
     KEY_PFR &= ~KEY_MASK;
-	/*Set CPIO Pull-Up function*/
+    /*Set CPIO Pull-Up function*/
     KEY_PCR |= KEY_MASK;
     /*Make button pins inputs*/
     KEY_DDR &= ~KEY_MASK;
@@ -38,7 +34,7 @@ static void key_thread_entry(void *parameter)
     rt_uint8_t i;
 
     struct rtgui_event_kbd kbd_event;
-    
+
     key_io_init();
 
     /* init keyboard event */
@@ -109,49 +105,49 @@ static void key_thread_entry(void *parameter)
         rt_thread_delay(next_delay);
     }
 #else
-	extern struct rt_messagequeue mq;
-	rt_time_t next_delay;
-	struct lcd_msg msg;
-	msg.type = KEY_MSG;
-	
-	key_io_init();
-	
-	while (1)
-	{
-		msg.key = NO_KEY;
-	
-		next_delay = RT_TICK_PER_SECOND/10;
-	
-		if (KEY_ENTER_GETVALUE() == 0 )
-		{
-			msg.key  = KEY_ENTER;
-		}
-	
-		if (KEY_DOWN_GETVALUE() == 0)
-		{
-			msg.key  = KEY_DOWN;
-		}
-	
-		if (KEY_UP_GETVALUE() == 0)
-		{
-			msg.key  = KEY_UP;
-		}
-	
-		if (KEY_RIGHT_GETVALUE() == 0)
-		{
-			msg.key  = KEY_RIGHT;
-		}
-	
-		if (KEY_LEFT_GETVALUE() == 0)
-		{
-			msg.key  = KEY_LEFT;
-		}
-	
-		rt_mq_send(&mq, &msg, sizeof(msg));
-	
-		/* wait next key press */
-		rt_thread_delay(next_delay);
-	}
+    extern struct rt_messagequeue mq;
+    rt_time_t next_delay;
+    struct lcd_msg msg;
+    msg.type = KEY_MSG;
+
+    key_io_init();
+
+    while (1)
+    {
+        msg.key = NO_KEY;
+
+        next_delay = RT_TICK_PER_SECOND/10;
+
+        if (KEY_ENTER_GETVALUE() == 0 )
+        {
+            msg.key  = KEY_ENTER;
+        }
+
+        if (KEY_DOWN_GETVALUE() == 0)
+        {
+            msg.key  = KEY_DOWN;
+        }
+
+        if (KEY_UP_GETVALUE() == 0)
+        {
+            msg.key  = KEY_UP;
+        }
+
+        if (KEY_RIGHT_GETVALUE() == 0)
+        {
+            msg.key  = KEY_RIGHT;
+        }
+
+        if (KEY_LEFT_GETVALUE() == 0)
+        {
+            msg.key  = KEY_LEFT;
+        }
+
+        rt_mq_send(&mq, &msg, sizeof(msg));
+
+        /* wait next key press */
+        rt_thread_delay(next_delay);
+    }
 #endif
 }
 
@@ -159,6 +155,6 @@ static rt_thread_t key_thread;
 void rt_hw_key_init(void)
 {
     key_thread = rt_thread_create("key", key_thread_entry, RT_NULL, 384, 28, 5);
-    if (key_thread != RT_NULL) 
+    if (key_thread != RT_NULL)
         rt_thread_startup(key_thread);
 }
diff --git a/bsp/mb9bf500r/key.h b/bsp/mb9bf500r/key.h
index edabf1dffb..45c044c7c0 100644
--- a/bsp/mb9bf500r/key.h
+++ b/bsp/mb9bf500r/key.h
@@ -1,11 +1,7 @@
 /*
- * File      : key.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2011, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/mb9bf500r/lcd.c b/bsp/mb9bf500r/lcd.c
index db2f272a8a..8b61abf2e0 100644
--- a/bsp/mb9bf500r/lcd.c
+++ b/bsp/mb9bf500r/lcd.c
@@ -1,11 +1,7 @@
 /*
- * File      : lcd.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2011, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -59,7 +55,7 @@ void lcd_write_cmd(unsigned char command)
             LCD_DATA_HIGH();
         else
             LCD_DATA_LOW();
-            
+
         LCD_CLK_LOW();
         delay();
         LCD_CLK_HIGH();
@@ -81,7 +77,7 @@ void lcd_write_data(unsigned char data)
             LCD_DATA_HIGH();
         else
             LCD_DATA_LOW();
-        
+
         LCD_CLK_LOW();
         delay();
         LCD_CLK_HIGH();
@@ -97,12 +93,12 @@ void lcd_write_data(unsigned char data)
 static void rt_hw_lcd_update(struct rt_device_rect_info *rect_info)
 {
     rt_uint8_t i,j = GUI_LCM_XMAX;
-    rt_uint8_t* p = (rt_uint8_t*)gui_disp_buf;  
-    
+    rt_uint8_t* p = (rt_uint8_t*)gui_disp_buf;
+
     for (i=0; i> 4;
-	
-  lcd_write_cmd(SET_PAGE_ADDR_0 | page);	        // page no.
-  lcd_write_cmd(SET_COLH_ADDR_0 | colh);		// fixed col first addr
+
+  lcd_write_cmd(SET_PAGE_ADDR_0 | page);            // page no.
+  lcd_write_cmd(SET_COLH_ADDR_0 | colh);        // fixed col first addr
   lcd_write_cmd(SET_COLL_ADDR_0 | coll);
   lcd_write_data(gui_disp_buf[page][x]);
 }
 
 /****************************************************************************
 * Function Name  : LCD_PutChar
-* Description    : output a char to screen 
+* Description    : output a char to screen
                   (the char only can be ' ','0'~'9','A'~'Z','a'~'z')
 * Input          : x      X-coordinate
                    y      Y-coordinate
@@ -363,13 +359,13 @@ void  LCD_UpdatePoint(unsigned int x, unsigned int y)
                    0    Fail
 ****************************************************************************/
 unsigned char  LCD_PutChar(unsigned long x, unsigned long y, unsigned char ch)
-{  
+{
    unsigned char data;
    unsigned char i, j;
 
    if( x >=(GUI_LCM_XMAX-8) ) return(0);
    if( y >=(GUI_LCM_YMAX-8) ) return(0);
-   
+
    if(ch == 0x20)
      ch -= 0x20;
      else if((ch >= 0x30)&&(ch <= 0x39))
@@ -380,30 +376,30 @@ unsigned char  LCD_PutChar(unsigned long x, unsigned long y, unsigned char ch)
           ch -= 0x3C;
           else
             return(0);
-    
+
    for(i = 0; i < 8; i++)
-   {  
+   {
       data = FONTTYPE8_8[ch][i];
-      
+
       for(j = 0; j < 8; j++)
-      {  
+      {
          if( (data&BIT_MASK[j]) == 0)
            gui_disp_buf[y / 8][x] &= (~(0x01 << ( y % 8)));
-         else  
+         else
            gui_disp_buf[y / 8][x] |= (0x01 <<( y % 8));
          LCD_UpdatePoint(x, y);
          x ++;
       }
-      x -= 8;								
-      y++;									
+      x -= 8;
+      y++;
    }
-   
+
    return(1);
 }
 
 /****************************************************************************
 * Function Name  : LCD_PutString
-* Description    : output string to screen 
+* Description    : output string to screen
 * Input          : x      X-coordinate
                    y      Y-coordinate
                   str     pointer to string
@@ -411,32 +407,32 @@ unsigned char  LCD_PutChar(unsigned long x, unsigned long y, unsigned char ch)
 * Return         : None
 ****************************************************************************/
 void  LCD_PutString(unsigned long x, unsigned long y, char *str)
-{  
+{
   while(1)
-  {  
+  {
     if( (*str)=='\0' ) break;
     if( LCD_PutChar(x, y, *str++) == 0 ) break;
-    x += 6;								
+    x += 6;
   }
 }
 
 static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args)
 {
-	switch (cmd)
-	{
-#ifdef RT_USING_RTGUI    
-	case RTGRAPHIC_CTRL_RECT_UPDATE:
-        rt_hw_lcd_update(args);      
-		break;
-	case RTGRAPHIC_CTRL_POWERON:
-		break;
-	case RTGRAPHIC_CTRL_POWEROFF:
-		break;
-	case RTGRAPHIC_CTRL_GET_INFO:		
-		rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
-		break;
-	case RTGRAPHIC_CTRL_SET_MODE:
-		break;
+    switch (cmd)
+    {
+#ifdef RT_USING_RTGUI
+    case RTGRAPHIC_CTRL_RECT_UPDATE:
+        rt_hw_lcd_update(args);
+        break;
+    case RTGRAPHIC_CTRL_POWERON:
+        break;
+    case RTGRAPHIC_CTRL_POWEROFF:
+        break;
+    case RTGRAPHIC_CTRL_GET_INFO:
+        rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
+        break;
+    case RTGRAPHIC_CTRL_SET_MODE:
+        break;
 #else
     case RT_DEVICE_CTRL_LCD_DISPLAY_ON:
         lcd_write_cmd(DISPLAY_ON);
@@ -450,32 +446,32 @@ static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args)
     case RT_DEVICE_CTRL_LCD_CLEAR_SCR:
         LCD_ClearSCR();
         break;
-#endif        
-	}
+#endif
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 void rt_hw_lcd_init(void)
 {
-	rt_device_t lcd = rt_malloc(sizeof(struct rt_device));
-	if (lcd == RT_NULL) return; /* no memory yet */
+    rt_device_t lcd = rt_malloc(sizeof(struct rt_device));
+    if (lcd == RT_NULL) return; /* no memory yet */
 
-	_lcd_info.bits_per_pixel = 16;
-	_lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565;
-	_lcd_info.framebuffer = RT_NULL;
-	_lcd_info.width = LCD_WIDTH;
-	_lcd_info.height = LCD_HEIGHT;
+    _lcd_info.bits_per_pixel = 16;
+    _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565;
+    _lcd_info.framebuffer = RT_NULL;
+    _lcd_info.width = LCD_WIDTH;
+    _lcd_info.height = LCD_HEIGHT;
 
-	/* init device structure */
-	lcd->type = RT_Device_Class_Unknown;
-	lcd->init = rt_lcd_init;
-	lcd->open = RT_NULL;
-	lcd->close = RT_NULL;
-	lcd->control = rt_lcd_control;
+    /* init device structure */
+    lcd->type = RT_Device_Class_Unknown;
+    lcd->init = rt_lcd_init;
+    lcd->open = RT_NULL;
+    lcd->close = RT_NULL;
+    lcd->control = rt_lcd_control;
 #ifdef RT_USING_RTGUI
-	lcd->user_data = (void*)&_lcd_ops;
-#endif	
-	/* register lcd device to RT-Thread */
-	rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR);
+    lcd->user_data = (void*)&_lcd_ops;
+#endif
+    /* register lcd device to RT-Thread */
+    rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR);
 }
diff --git a/bsp/mb9bf500r/lcd.h b/bsp/mb9bf500r/lcd.h
index 8c0462d6e3..e0fa9efdc3 100644
--- a/bsp/mb9bf500r/lcd.h
+++ b/bsp/mb9bf500r/lcd.h
@@ -1,11 +1,7 @@
 /*
- * File      : lcd.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -19,166 +15,166 @@
 #include "mb9bf506r.h"
 
 /********* LCD Hardward Interface *************
-LCD_CS		PORT1.7
-LCD_CD		PORT1.6
-LCD_WR		PORT1.5
-LCD_RD		PORT1.4
-LCD_SCK		PORT1.3
-LCD_MOSI	PORT1.2
-LCD_C86		PORT1.1
-LCD_PS		PORT1.0
-LCD_DATA[0..7]		PORT5.[0..7]
+LCD_CS      PORT1.7
+LCD_CD      PORT1.6
+LCD_WR      PORT1.5
+LCD_RD      PORT1.4
+LCD_SCK     PORT1.3
+LCD_MOSI    PORT1.2
+LCD_C86     PORT1.1
+LCD_PS      PORT1.0
+LCD_DATA[0..7]      PORT5.[0..7]
 ***********************************************/
-#define LCD_CS					(1UL << 7)
-#define LCD_CS_DDR				(FM3_GPIO->DDR1)
-#define LCD_CS_PFR				(FM3_GPIO->PFR1)
-#define LCD_CS_PDOR				(FM3_GPIO->PDOR1)
+#define LCD_CS                  (1UL << 7)
+#define LCD_CS_DDR              (FM3_GPIO->DDR1)
+#define LCD_CS_PFR              (FM3_GPIO->PFR1)
+#define LCD_CS_PDOR             (FM3_GPIO->PDOR1)
 
-#define LCD_CD					(1UL << 6)
-#define LCD_CD_DDR				(FM3_GPIO->DDR1)
-#define LCD_CD_PFR				(FM3_GPIO->PFR1)
-#define LCD_CD_PDOR				(FM3_GPIO->PDOR1)
+#define LCD_CD                  (1UL << 6)
+#define LCD_CD_DDR              (FM3_GPIO->DDR1)
+#define LCD_CD_PFR              (FM3_GPIO->PFR1)
+#define LCD_CD_PDOR             (FM3_GPIO->PDOR1)
 
-#define LCD_PS					(1UL << 0)
-#define LCD_PS_DDR				(FM3_GPIO->DDR1)
-#define LCD_PS_PFR				(FM3_GPIO->PFR1)
-#define LCD_PS_PDOR				(FM3_GPIO->PDOR1)
+#define LCD_PS                  (1UL << 0)
+#define LCD_PS_DDR              (FM3_GPIO->DDR1)
+#define LCD_PS_PFR              (FM3_GPIO->PFR1)
+#define LCD_PS_PDOR             (FM3_GPIO->PDOR1)
 
-#define LCD_CLK					(1UL << 6)
-#define LCD_CLK_DDR				(FM3_GPIO->DDR5)
-#define LCD_CLK_PFR				(FM3_GPIO->PFR5)
-#define LCD_CLK_PDOR			(FM3_GPIO->PDOR5)
+#define LCD_CLK                 (1UL << 6)
+#define LCD_CLK_DDR             (FM3_GPIO->DDR5)
+#define LCD_CLK_PFR             (FM3_GPIO->PFR5)
+#define LCD_CLK_PDOR            (FM3_GPIO->PDOR5)
 
-#define LCD_DATA				(1UL << 7)
-#define LCD_DATA_DDR			(FM3_GPIO->DDR5)
-#define LCD_DATA_PFR			(FM3_GPIO->PFR5)
-#define LCD_DATA_PDOR			(FM3_GPIO->PDOR5)
+#define LCD_DATA                (1UL << 7)
+#define LCD_DATA_DDR            (FM3_GPIO->DDR5)
+#define LCD_DATA_PFR            (FM3_GPIO->PFR5)
+#define LCD_DATA_PDOR           (FM3_GPIO->PDOR5)
 
 /* LCD driver for ZYMG12864C3 */
-#define LCD_WIDTH				128
-#define LCD_HEIGHT				64
+#define LCD_WIDTH               128
+#define LCD_HEIGHT              64
 
 // Driver the LCD with Parallel or serial interface and the command/data control pin is gpio
-#define LCD_CS_HIGH()			LCD_CS_PDOR  |=  LCD_CS
-#define LCD_CS_LOW()			LCD_CS_PDOR  &= ~LCD_CS
+#define LCD_CS_HIGH()           LCD_CS_PDOR  |=  LCD_CS
+#define LCD_CS_LOW()            LCD_CS_PDOR  &= ~LCD_CS
 
-#define LCD_CD_HIGH()			LCD_CD_PDOR |=  LCD_CD
-#define LCD_CD_LOW()			LCD_CD_PDOR &= ~LCD_CD
+#define LCD_CD_HIGH()           LCD_CD_PDOR |=  LCD_CD
+#define LCD_CD_LOW()            LCD_CD_PDOR &= ~LCD_CD
 
-#define LCD_PS_HIGH()			LCD_PS_PDOR |=  LCD_PS
-#define LCD_PS_LOW()			LCD_PS_PDOR &= ~LCD_PS
+#define LCD_PS_HIGH()           LCD_PS_PDOR |=  LCD_PS
+#define LCD_PS_LOW()            LCD_PS_PDOR &= ~LCD_PS
 
-#define LCD_CLK_HIGH()			LCD_CLK_PDOR |=  LCD_CLK
-#define LCD_CLK_LOW()			LCD_CLK_PDOR &= ~LCD_CLK
+#define LCD_CLK_HIGH()          LCD_CLK_PDOR |=  LCD_CLK
+#define LCD_CLK_LOW()           LCD_CLK_PDOR &= ~LCD_CLK
 
-#define LCD_DATA_HIGH()			LCD_DATA_PDOR |=  LCD_DATA
-#define LCD_DATA_LOW()			LCD_DATA_PDOR &= ~LCD_DATA
+#define LCD_DATA_HIGH()         LCD_DATA_PDOR |=  LCD_DATA
+#define LCD_DATA_LOW()          LCD_DATA_PDOR &= ~LCD_DATA
 
 // define the arrtibute of ZYMG12864(LCM)
-#define GUI_LCM_XMAX 			128		// defined the lcd's line-number is 128 
-#define GUI_LCM_YMAX 			64		// defined the lcd's column-number is 64
-#define GUI_LCM_PAGE			8		// defined the lcd's page-number is 8(GUI_LCM_YMAX/8)
+#define GUI_LCM_XMAX            128     // defined the lcd's line-number is 128
+#define GUI_LCM_YMAX            64      // defined the lcd's column-number is 64
+#define GUI_LCM_PAGE            8       // defined the lcd's page-number is 8(GUI_LCM_YMAX/8)
 
 /* set LCD command */
-#define DISPLAY_ON				0xAF	// A0,RD,WR:010
-#define DISPLAY_OFF				0xAE	// A0,RD,WR:010
+#define DISPLAY_ON              0xAF    // A0,RD,WR:010
+#define DISPLAY_OFF             0xAE    // A0,RD,WR:010
 
-#define SET_START_LINE_0		0x40	// A0,RD,WR:010; line0~line63
-#define SET_PAGE_ADDR_0			0xB0	// A0,RD,WR:010; addr0~addr8
-#define SET_COLH_ADDR_0			0x10	// A0,RD,WR:010; 
-#define SET_COLL_ADDR_0			0x00	// A0,RD,WR:010; addr0~addr131
+#define SET_START_LINE_0        0x40    // A0,RD,WR:010; line0~line63
+#define SET_PAGE_ADDR_0         0xB0    // A0,RD,WR:010; addr0~addr8
+#define SET_COLH_ADDR_0         0x10    // A0,RD,WR:010;
+#define SET_COLL_ADDR_0         0x00    // A0,RD,WR:010; addr0~addr131
 
-#define READ_STATUS				0x-0	// A0,RD,WR:001; BUSY | ADC | ON/OFF |  RESET | 0 0 0 0
-#define STATUS_BUSY				0x80
-#define STATUS_ADC_REVERSE		0x40	// column address 131-n : SEG n, else column address n : SEG n
-#define STATUS_DISPLAY_OFF		0x20
-#define STATUS_RESET			0x80
+#define READ_STATUS             0x-0    // A0,RD,WR:001; BUSY | ADC | ON/OFF |  RESET | 0 0 0 0
+#define STATUS_BUSY             0x80
+#define STATUS_ADC_REVERSE      0x40    // column address 131-n : SEG n, else column address n : SEG n
+#define STATUS_DISPLAY_OFF      0x20
+#define STATUS_RESET            0x80
 
-#define WRITE_DATA				0x--	// A0,RD,WR:110
-#define READ_DATE				0x--	// A0,RD,WR:101; spi mode is unavailable
+#define WRITE_DATA              0x--    // A0,RD,WR:110
+#define READ_DATE               0x--    // A0,RD,WR:101; spi mode is unavailable
 
-#define SET_ADC_NORMAL			0xA0	// A0,RD,WR:010
-#define SET_ADC_REVERSE			0xA1	// A0,RD,WR:010
-#define DISPLAY_NORMAL			0xA6	// A0,RD,WR:010
-#define DISPLAY_REVERSE			0xA7	// A0,RD,WR:010; reverse color
-#define DISPLAY_ALL_ON			0xA5	// A0,RD,WR:010
-#define DISPLAY_ALL_NORMAL		0xA4	// A0,RD,WR:010
+#define SET_ADC_NORMAL          0xA0    // A0,RD,WR:010
+#define SET_ADC_REVERSE         0xA1    // A0,RD,WR:010
+#define DISPLAY_NORMAL          0xA6    // A0,RD,WR:010
+#define DISPLAY_REVERSE         0xA7    // A0,RD,WR:010; reverse color
+#define DISPLAY_ALL_ON          0xA5    // A0,RD,WR:010
+#define DISPLAY_ALL_NORMAL      0xA4    // A0,RD,WR:010
 
 /*************************************************************
-*	bias:	1/65duty | 1/49duty | 1/33duty | 1/55duty | 1/53duty *
-*	---------------|----------|----------|----------|--------- *
-*	A2: 	1/9 bias | 1/8 bias | 1/6 bias | 1/8 bias | 1/8 bias *
-*	A3:		1/7 bias | 1/6 bias | 1/5 bias | 1/6 bias | 1/6 bias *
+*   bias:   1/65duty | 1/49duty | 1/33duty | 1/55duty | 1/53duty *
+*   ---------------|----------|----------|----------|--------- *
+*   A2:     1/9 bias | 1/8 bias | 1/6 bias | 1/8 bias | 1/8 bias *
+*   A3:     1/7 bias | 1/6 bias | 1/5 bias | 1/6 bias | 1/6 bias *
 **************************************************************/
 
-#define SET_LCD_BIAS_7    		0xA3	// A0,RD,WR:010
-#define SET_LCD_BIAS_9    		0xA2	// A0,RD,WR:010
+#define SET_LCD_BIAS_7          0xA3    // A0,RD,WR:010
+#define SET_LCD_BIAS_9          0xA2    // A0,RD,WR:010
 
-#define RMW_MODE_ENABLE   		0xE0	// A0,RD,WR:010; the column address locked when read command operating
-#define RMW_MODE_END		  	0xEE	// A0,RD,WR:010; returns to the column address when RMW was entered.
-#define RESET_LCD         		0xE2	// A0,RD,WR:010
+#define RMW_MODE_ENABLE         0xE0    // A0,RD,WR:010; the column address locked when read command operating
+#define RMW_MODE_END            0xEE    // A0,RD,WR:010; returns to the column address when RMW was entered.
+#define RESET_LCD               0xE2    // A0,RD,WR:010
 
 
 /**************************************************************************************
-*	Com Scan Dir:	|	1/65duty 		| 1/49duty 		| 1/33duty 		| 1/55duty 		| 1/53duty		*
-*	--------------|-------------|-------------|-------------|------------------------ 	*
-*	C0: 	Normal	|	COM0:COM63	|	COM0:COM47	|	COM0:COM31	|	COM0:COM53	|	COM0:COM51	*
-*	C8:		Reverse	|	COM63:COM0	|	COM47:COM0	|	COM31:COM0	|	COM53:COM0	|	COM51:COM0	*
+*   Com Scan Dir:   |   1/65duty        | 1/49duty      | 1/33duty      | 1/55duty      | 1/53duty      *
+*   --------------|-------------|-------------|-------------|------------------------   *
+*   C0:     Normal  |   COM0:COM63  |   COM0:COM47  |   COM0:COM31  |   COM0:COM53  |   COM0:COM51  *
+*   C8:     Reverse |   COM63:COM0  |   COM47:COM0  |   COM31:COM0  |   COM53:COM0  |   COM51:COM0  *
 ***************************************************************************************/
 
-#define COM_SCAN_DIR_NORMAL		0xC0	// A0,RD,WR:010
-#define COM_SCAN_DIR_REVERSE	0xC8	// A0,RD,WR:010
+#define COM_SCAN_DIR_NORMAL     0xC0    // A0,RD,WR:010
+#define COM_SCAN_DIR_REVERSE    0xC8    // A0,RD,WR:010
 
 // 0 0 1 0 1 | Booster On | Regulator On | Follower On
-#define POWER_BOOSTER_ON		0x2C	// A0,RD,WR:010
-#define POWER_REGULATOR_ON		0x2E	// A0,RD,WR:010
-#define POWER_FOLLOWER_ON		0x2F	// A0,RD,WR:010
+#define POWER_BOOSTER_ON        0x2C    // A0,RD,WR:010
+#define POWER_REGULATOR_ON      0x2E    // A0,RD,WR:010
+#define POWER_FOLLOWER_ON       0x2F    // A0,RD,WR:010
 
-#define SET_RESISTOR_RATIO		0x20	// A0,RD,WR:010; 20~27:small~large
+#define SET_RESISTOR_RATIO      0x20    // A0,RD,WR:010; 20~27:small~large
 
-#define SET_ELECVOL_MODE		0x81	// A0,RD,WR:010; double byte command
-#define SET_ELECVOL_REG			0x20	// A0,RD,WR:010; the electronic volume(64 voltage levels:00~3F) function is not used.
+#define SET_ELECVOL_MODE        0x81    // A0,RD,WR:010; double byte command
+#define SET_ELECVOL_REG         0x20    // A0,RD,WR:010; the electronic volume(64 voltage levels:00~3F) function is not used.
 
-#define SLEEP_MODE_ENABLE		0xAC	// A0,RD,WR:010; double byte command, preceding command
-#define SLEEP_MODE_DISABLE		0xAD	// A0,RD,WR:010; preceding command
-#define SLEEP_MODE_DELIVER		0x00	// A0,RD,WR:010; following command
+#define SLEEP_MODE_ENABLE       0xAC    // A0,RD,WR:010; double byte command, preceding command
+#define SLEEP_MODE_DISABLE      0xAD    // A0,RD,WR:010; preceding command
+#define SLEEP_MODE_DELIVER      0x00    // A0,RD,WR:010; following command
 
-#define BOOST_RATIO_SET			0xF8	// A0,RD,WR:010; double byte command, preceding command
-#define BOOST_RATIO_234			0x00	// A0,RD,WR:010; following command
-#define BOOST_RATIO_5			0x01	// A0,RD,WR:010; following command
-#define BOOST_RATIO_6			0x03	// A0,RD,WR:010; following command
+#define BOOST_RATIO_SET         0xF8    // A0,RD,WR:010; double byte command, preceding command
+#define BOOST_RATIO_234         0x00    // A0,RD,WR:010; following command
+#define BOOST_RATIO_5           0x01    // A0,RD,WR:010; following command
+#define BOOST_RATIO_6           0x03    // A0,RD,WR:010; following command
 
-#define COMMAND_NOP				0xE3	// A0,RD,WR:010
-#define COMMAND_IC_TEST			0xFC	// A0,RD,WR:010; don't use
+#define COMMAND_NOP             0xE3    // A0,RD,WR:010
+#define COMMAND_IC_TEST         0xFC    // A0,RD,WR:010; don't use
 
-#define RT_DEVICE_CTRL_LCD_GET_WIDTH			0
-#define RT_DEVICE_CTRL_LCD_GET_HEIGHT			1
-#define RT_DEVICE_CTRL_LCD_GET_BPP			 	2
-#define RT_DEVICE_CTRL_LCD_GET_FRAMEBUFFER		3
-#define RT_DEVICE_CTRL_LCD_POWER_ON     		4
-#define RT_DEVICE_CTRL_LCD_POWER_OFF     		5
-#define RT_DEVICE_CTRL_LCD_CLEAR_SCR     		6
-#define RT_DEVICE_CTRL_LCD_FILL_ALL     		7
-#define RT_DEVICE_CTRL_LCD_UPDATE_POINT    		8
-#define RT_DEVICE_CTRL_LCD_DISPLAY_ON    		9
-#define RT_DEVICE_CTRL_LCD_DISPLAY_OFF    		10
-#define RT_DEVICE_CTRL_LCD_PUT_STRING    		11
+#define RT_DEVICE_CTRL_LCD_GET_WIDTH            0
+#define RT_DEVICE_CTRL_LCD_GET_HEIGHT           1
+#define RT_DEVICE_CTRL_LCD_GET_BPP              2
+#define RT_DEVICE_CTRL_LCD_GET_FRAMEBUFFER      3
+#define RT_DEVICE_CTRL_LCD_POWER_ON             4
+#define RT_DEVICE_CTRL_LCD_POWER_OFF            5
+#define RT_DEVICE_CTRL_LCD_CLEAR_SCR            6
+#define RT_DEVICE_CTRL_LCD_FILL_ALL             7
+#define RT_DEVICE_CTRL_LCD_UPDATE_POINT         8
+#define RT_DEVICE_CTRL_LCD_DISPLAY_ON           9
+#define RT_DEVICE_CTRL_LCD_DISPLAY_OFF          10
+#define RT_DEVICE_CTRL_LCD_PUT_STRING           11
 
-enum 
+enum
 {
-	ADC_MSG,
-	KEY_MSG,
-	CPU_MSG,
-	MAX_MSG,
+    ADC_MSG,
+    KEY_MSG,
+    CPU_MSG,
+    MAX_MSG,
 };
 
 struct lcd_msg
 {
-	rt_uint8_t	type;
-	rt_uint16_t	adc_value;
-	rt_uint8_t	key;
-	rt_uint16_t	major;
-	rt_uint16_t	minor;
+    rt_uint8_t  type;
+    rt_uint16_t adc_value;
+    rt_uint8_t  key;
+    rt_uint16_t major;
+    rt_uint16_t minor;
 };
 
 extern rt_uint32_t x;
diff --git a/bsp/mb9bf500r/led.c b/bsp/mb9bf500r/led.c
index 72c01b4507..ee28af7035 100644
--- a/bsp/mb9bf500r/led.c
+++ b/bsp/mb9bf500r/led.c
@@ -1,17 +1,13 @@
 /*
- * File      : led.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2011, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2011-03-03     lgnq
  */
-     
+
 #include 
 #include 
 
@@ -20,8 +16,8 @@
 
 void rt_hw_led_on(rt_uint8_t num)
 {
-	RT_ASSERT(num < LEDS_MAX_NUMBER);
-    
+    RT_ASSERT(num < LEDS_MAX_NUMBER);
+
     switch (num)
     {
         case 1:
@@ -31,16 +27,16 @@ void rt_hw_led_on(rt_uint8_t num)
             LED_PDOR &= ~LED2;
         break;
         case 3:
-            LED_PDOR &= ~LED3;        
+            LED_PDOR &= ~LED3;
         break;
         default:
         break;
-    }	
+    }
 }
 
 void rt_hw_led_off(rt_uint8_t num)
 {
-	RT_ASSERT(num < LEDS_MAX_NUMBER);
+    RT_ASSERT(num < LEDS_MAX_NUMBER);
 
     switch (num)
     {
@@ -51,17 +47,17 @@ void rt_hw_led_off(rt_uint8_t num)
             LED_PDOR |= LED2;
         break;
         case 3:
-            LED_PDOR |= LED3;        
+            LED_PDOR |= LED3;
         break;
         default:
         break;
-    }	
+    }
 }
 
 void rt_hw_led_toggle(rt_uint8_t num)
 {
-	RT_ASSERT(num < LEDS_MAX_NUMBER);
-    
+    RT_ASSERT(num < LEDS_MAX_NUMBER);
+
     switch (num)
     {
         case 1:
@@ -80,11 +76,11 @@ void rt_hw_led_toggle(rt_uint8_t num)
             if (LED_PDOR&LED3)
                 LED_PDOR &= ~LED3;
             else
-                LED_PDOR |= LED3;    
+                LED_PDOR |= LED3;
         break;
         default:
         break;
-    }	    
+    }
 }
 
 static rt_err_t led_io_init(void)
@@ -95,23 +91,23 @@ static rt_err_t led_io_init(void)
     LED_PDOR |= LED_MASK;
     /*Make led pins outputs*/
     LED_DDR |= LED_MASK;
-    
+
     //LED3 is controled by PWM
     FM3_GPIO->PFR3 = 0x1000;
     FM3_GPIO->EPFR04 = 0x00080000;
     FM3_BT2_PWM->TMCR = 0x0018;
-    FM3_BT2_PWM->TMCR2 = 0x01;			/* cks=0b1000 count clk 1/512 */
+    FM3_BT2_PWM->TMCR2 = 0x01;          /* cks=0b1000 count clk 1/512 */
     FM3_BT2_PWM->STC = 0x00;
-    FM3_BT2_PWM->PCSR  = 0x61A;			/* Down count = 1562 */
-    FM3_BT2_PWM->PDUT  = 0x0;			/* Duty count = 16/1562=10% */
-  
-    FM3_BT2_PWM->TMCR |= 0x03;			/* start base timer(softwere TRG) */
+    FM3_BT2_PWM->PCSR  = 0x61A;         /* Down count = 1562 */
+    FM3_BT2_PWM->PDUT  = 0x0;           /* Duty count = 16/1562=10% */
+
+    FM3_BT2_PWM->TMCR |= 0x03;          /* start base timer(softwere TRG) */
     return RT_EOK;
 }
 
 void pwm_update(rt_uint16_t value)
 {
-    FM3_BT2_PWM->PDUT  = value;			
+    FM3_BT2_PWM->PDUT  = value;
 }
 
 static void led1_thread_entry(void *parameter)
@@ -139,11 +135,11 @@ void rt_hw_led_init(void)
     led_io_init();
 
     led1_thread = rt_thread_create("led1", led1_thread_entry, RT_NULL, 384, 29, 5);
-    if (led1_thread != RT_NULL) 
+    if (led1_thread != RT_NULL)
         rt_thread_startup(led1_thread);
-    
+
     led2_thread = rt_thread_create("led2", led2_thread_entry, RT_NULL, 384, 30, 5);
-    if (led2_thread != RT_NULL) 
+    if (led2_thread != RT_NULL)
         rt_thread_startup(led2_thread);
 }
 
diff --git a/bsp/mb9bf500r/led.h b/bsp/mb9bf500r/led.h
index 6dd71c0d95..c4a433cb81 100644
--- a/bsp/mb9bf500r/led.h
+++ b/bsp/mb9bf500r/led.h
@@ -1,23 +1,19 @@
 /*
- * File      : led.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2011, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2011-03-03     lgnq
  */
- 
+
 #ifndef __LED_H__
 #define __LED_H__
 
 #include "mb9bf506r.h"
 
-#define LEDS_MAX_NUMBER 		4
+#define LEDS_MAX_NUMBER         4
 
 /*LEDs*/
 #define LED1        (1UL<<10)
@@ -29,9 +25,9 @@
 #define LED_DDR     (FM3_GPIO->DDR3)
 #define LED_PDOR    (FM3_GPIO->PDOR3)
 
-#define RT_DEVICE_CTRL_LED_ON			0
-#define RT_DEVICE_CTRL_LED_OFF			1
-#define RT_DEVICE_CTRL_LED_TOGGLE	 	2
+#define RT_DEVICE_CTRL_LED_ON           0
+#define RT_DEVICE_CTRL_LED_OFF          1
+#define RT_DEVICE_CTRL_LED_TOGGLE       2
 
 void rt_hw_led_init(void);
 void rt_hw_led_on(rt_uint8_t num);
diff --git a/bsp/mb9bf500r/rtconfig.h b/bsp/mb9bf500r/rtconfig.h
index cb2c62fccd..ac37ecb464 100644
--- a/bsp/mb9bf500r/rtconfig.h
+++ b/bsp/mb9bf500r/rtconfig.h
@@ -3,16 +3,16 @@
 #define __RTTHREAD_CFG_H__
 
 /* RT_NAME_MAX*/
-#define RT_NAME_MAX		8
+#define RT_NAME_MAX     8
 
 /* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE	4
+#define RT_ALIGN_SIZE   4
 
 /* PRIORITY_MAX */
-#define RT_THREAD_PRIORITY_MAX	32
+#define RT_THREAD_PRIORITY_MAX  32
 
 /* Tick per Second */
-#define RT_TICK_PER_SECOND	100
+#define RT_TICK_PER_SECOND  100
 
 /* SECTION: RT_DEBUG */
 /* Thread Debug */
@@ -53,20 +53,20 @@
 #define RT_USING_DEVICE
 /* RT_USING_UART */
 #define RT_USING_UART0
-#define RT_UART_RX_BUFFER_SIZE	64
+#define RT_UART_RX_BUFFER_SIZE  64
 
 /* SECTION: Console options */
 #define RT_TINY_SIZE
 #define RT_USING_CONSOLE
 /* the buffer size of console */
-#define RT_CONSOLEBUF_SIZE	128
+#define RT_CONSOLEBUF_SIZE  128
 
 /* SECTION: RTGUI support */
 /* using RTGUI support */
 /* #define RT_USING_RTGUI */
 
 /* name length of RTGUI object */
-#define RTGUI_NAME_MAX		16
+#define RTGUI_NAME_MAX      16
 /* support 16 weight font */
 //#define RTGUI_USING_FONT16
 /* support 12 weight font */
diff --git a/bsp/mb9bf500r/startup.c b/bsp/mb9bf500r/startup.c
index bc96eb5dca..1e7309ae3e 100644
--- a/bsp/mb9bf500r/startup.c
+++ b/bsp/mb9bf500r/startup.c
@@ -1,11 +1,7 @@
 /*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -38,62 +34,57 @@ extern int __bss_end;
  */
 void rtthread_startup(void)
 {
-	/* init board */
-	rt_hw_board_init();
+    /* init board */
+    rt_hw_board_init();
 
-	/* show version */
-	rt_show_version();
+    /* show version */
+    rt_show_version();
 
-	/* init timer system */
-	rt_system_timer_init();
+    /* init timer system */
+    rt_system_timer_init();
 
 #ifdef RT_USING_HEAP
-	#ifdef __CC_ARM
-		rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)FM3_SRAM_END);
-	#elif __ICCARM__
-		rt_system_heap_init(__segment_end("HEAP"), (void*)FM3_SRAM_END);
-	#else
-		/* init memory system */
-		rt_system_heap_init((void*)&__bss_end, (void*)FM3_SRAM_END);
-	#endif
+    #ifdef __CC_ARM
+        rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)FM3_SRAM_END);
+    #elif __ICCARM__
+        rt_system_heap_init(__segment_end("HEAP"), (void*)FM3_SRAM_END);
+    #else
+        /* init memory system */
+        rt_system_heap_init((void*)&__bss_end, (void*)FM3_SRAM_END);
+    #endif
 #endif
 
-	/* init scheduler system */
-	rt_system_scheduler_init();
+    /* init scheduler system */
+    rt_system_scheduler_init();
 
-#ifdef RT_USING_DEVICE
-	/* init all device */
-	rt_device_init_all();
-#endif
-
-	/* init application */
-	rt_application_init();
+    /* init application */
+    rt_application_init();
 
     /* init timer thread */
     rt_system_timer_thread_init();
 
-	/* init idle thread */
-	rt_thread_idle_init();
+    /* init idle thread */
+    rt_thread_idle_init();
 
-	/* start scheduler */
-	rt_system_scheduler_start();
+    /* start scheduler */
+    rt_system_scheduler_start();
 
-	/* never reach here */
-	return ;
+    /* never reach here */
+    return ;
 }
 
 int main(void)
 {
-	/* disable interrupt first */
-	rt_hw_interrupt_disable();
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
 
-	/* init system setting */
-	SystemInit();
-    
-	/* startup RT-Thread RTOS */
-	rtthread_startup();
+    /* init system setting */
+    SystemInit();
 
-	return 0;
+    /* startup RT-Thread RTOS */
+    rtthread_startup();
+
+    return 0;
 }
 
 /*@}*/
diff --git a/bsp/mb9bf506r/applications/application.c b/bsp/mb9bf506r/applications/application.c
index ce1daa2327..fdc42a9100 100644
--- a/bsp/mb9bf506r/applications/application.c
+++ b/bsp/mb9bf506r/applications/application.c
@@ -1,11 +1,7 @@
 /*
- * File      : application.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -33,35 +29,35 @@
 
 void rt_init_thread_entry(void *parameter)
 {
-	/* LED Initialization */
-	rt_hw_led_init();
+    /* LED Initialization */
+    rt_hw_led_init();
 
 #ifdef RT_USING_COMPONENTS_INIT
-	/* initialization RT-Thread Components */
-	rt_components_init();
+    /* initialization RT-Thread Components */
+    rt_components_init();
 #endif
 
-	/* Filesystem Initialization */
+    /* Filesystem Initialization */
 #ifdef RT_USING_DFS
-	/* mount nand fat partition 1 as root directory */
-	if (dfs_mount("nand", "/", "elm", 0, 0) == 0)
-		rt_kprintf("File System initialized!\n");
-	else
-		rt_kprintf("File System init failed!\n");
+    /* mount nand fat partition 1 as root directory */
+    if (dfs_mount("nand", "/", "elm", 0, 0) == 0)
+        rt_kprintf("File System initialized!\n");
+    else
+        rt_kprintf("File System init failed!\n");
 #endif
 }
 
 int rt_application_init(void)
 {
-	rt_thread_t tid;
+    rt_thread_t tid;
 
-	tid = rt_thread_create("init",
-			rt_init_thread_entry, RT_NULL,
-			2048, RT_THREAD_PRIORITY_MAX/3, 20);
-	if (tid != RT_NULL)
-		rt_thread_startup(tid);
+    tid = rt_thread_create("init",
+            rt_init_thread_entry, RT_NULL,
+            2048, RT_THREAD_PRIORITY_MAX/3, 20);
+    if (tid != RT_NULL)
+        rt_thread_startup(tid);
 
-	return 0;
+    return 0;
 }
 
 /*@}*/
diff --git a/bsp/mb9bf506r/applications/startup.c b/bsp/mb9bf506r/applications/startup.c
index 9076d572d6..ccb31d40b4 100644
--- a/bsp/mb9bf506r/applications/startup.c
+++ b/bsp/mb9bf506r/applications/startup.c
@@ -1,11 +1,7 @@
 /*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -38,60 +34,60 @@ extern int __bss_end;
  */
 void rtthread_startup(void)
 {
-	/* initialize board */
-	rt_hw_board_init();
+    /* initialize board */
+    rt_hw_board_init();
 
-	/* show version */
-	rt_show_version();
+    /* show version */
+    rt_show_version();
 
 #ifdef RT_USING_HEAP
-	#ifdef __CC_ARM
-		rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)FM3_SRAM_END);
-	#elif __ICCARM__
-		rt_system_heap_init(__segment_end("HEAP"), (void*)FM3_SRAM_END);
-	#else
-		/* init memory system */
-		rt_system_heap_init((void*)&__bss_end, (void*)FM3_SRAM_END);
-	#endif
+    #ifdef __CC_ARM
+        rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)FM3_SRAM_END);
+    #elif __ICCARM__
+        rt_system_heap_init(__segment_end("HEAP"), (void*)FM3_SRAM_END);
+    #else
+        /* init memory system */
+        rt_system_heap_init((void*)&__bss_end, (void*)FM3_SRAM_END);
+    #endif
 #endif
 
-	/* init scheduler system */
-	rt_system_scheduler_init();
+    /* init scheduler system */
+    rt_system_scheduler_init();
 
 #ifdef RT_USING_DEVICE
 #if defined(RT_USING_DFS) && defined(RT_USING_DFS_UFFS)
-	rt_hw_nand_init();
+    rt_hw_nand_init();
 #endif
 #endif
 
-	/* initialize application */
-	rt_application_init();
+    /* initialize application */
+    rt_application_init();
 
     /* initialize timer */
     rt_system_timer_init();
 
-	/* initialize timer thread */
-	rt_system_timer_thread_init();
+    /* initialize timer thread */
+    rt_system_timer_thread_init();
 
-	/* initialize idle thread */
-	rt_thread_idle_init();
+    /* initialize idle thread */
+    rt_thread_idle_init();
 
-	/* start scheduler */
-	rt_system_scheduler_start();
+    /* start scheduler */
+    rt_system_scheduler_start();
 
-	/* never reach here */
-	return ;
+    /* never reach here */
+    return ;
 }
 
 int main(void)
 {
-	/* disable interrupt first */
-	rt_hw_interrupt_disable();
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
 
-	/* startup RT-Thread RTOS */
-	rtthread_startup();
+    /* startup RT-Thread RTOS */
+    rtthread_startup();
 
-	return 0;
+    return 0;
 }
 
 /*@}*/
diff --git a/bsp/mb9bf506r/drivers/board.c b/bsp/mb9bf506r/drivers/board.c
index 89d42c6329..d687bea929 100644
--- a/bsp/mb9bf506r/drivers/board.c
+++ b/bsp/mb9bf506r/drivers/board.c
@@ -1,11 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2012 RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -32,13 +28,13 @@
  */
 void SysTick_Handler(void)
 {
-	/* enter interrupt */
-	rt_interrupt_enter();
+    /* enter interrupt */
+    rt_interrupt_enter();
 
-	rt_tick_increase();
+    rt_tick_increase();
 
-	/* leave interrupt */
-	rt_interrupt_leave();
+    /* leave interrupt */
+    rt_interrupt_leave();
 }
 
 /**
@@ -46,16 +42,16 @@ void SysTick_Handler(void)
  */
 void rt_hw_board_init(void)
 {
-	/* init systick */
-	SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
-    
-	/* initialize UART device */
-	rt_hw_serial_init();
-	/* set console as UART device */
-	rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
-	
-	/* initialize nand flash device */
-	rt_hw_nand_init();
+    /* init systick */
+    SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+
+    /* initialize UART device */
+    rt_hw_serial_init();
+    /* set console as UART device */
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+
+    /* initialize nand flash device */
+    rt_hw_nand_init();
 }
 
 /*@}*/
diff --git a/bsp/mb9bf506r/drivers/board.h b/bsp/mb9bf506r/drivers/board.h
index 960dac022b..d2f252990c 100644
--- a/bsp/mb9bf506r/drivers/board.h
+++ b/bsp/mb9bf506r/drivers/board.h
@@ -1,11 +1,7 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/mb9bf506r/drivers/fm3_uart.c b/bsp/mb9bf506r/drivers/fm3_uart.c
index 2c82afd288..ece042cca4 100644
--- a/bsp/mb9bf506r/drivers/fm3_uart.c
+++ b/bsp/mb9bf506r/drivers/fm3_uart.c
@@ -1,12 +1,7 @@
 /*
- * File      : fm3_uart.c
- * mb9bf506r uart driver
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -22,19 +17,19 @@
 /* UART0 device driver structure */
 struct uart03_device uart0 =
 {
-	FM3_MFS0_UART,
-	MFS0RX_IRQn,
-	MFS0TX_IRQn,
+    FM3_MFS0_UART,
+    MFS0RX_IRQn,
+    MFS0TX_IRQn,
 };
 struct rt_serial_device serial0;
 
 void MFS0RX_IRQHandler(void)
 {
-	/* enter interrupt */
-	rt_interrupt_enter();
-	rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND);
-	/* leave interrupt */
-	rt_interrupt_leave();
+    /* enter interrupt */
+    rt_interrupt_enter();
+    rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND);
+    /* leave interrupt */
+    rt_interrupt_leave();
 }
 #endif
 
@@ -42,19 +37,19 @@ void MFS0RX_IRQHandler(void)
 /* UART1 device driver structure */
 struct uart03_device uart1 =
 {
-	FM3_MFS1_UART,
-	MFS1RX_IRQn,
-	MFS1TX_IRQn,
+    FM3_MFS1_UART,
+    MFS1RX_IRQn,
+    MFS1TX_IRQn,
 };
 struct rt_serial_device serial1;
 
 void MFS1RX_IRQHandler(void)
 {
-	/* enter interrupt */
-	rt_interrupt_enter();
-	rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND);
-	/* leave interrupt */
-	rt_interrupt_leave();
+    /* enter interrupt */
+    rt_interrupt_enter();
+    rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND);
+    /* leave interrupt */
+    rt_interrupt_leave();
 }
 #endif
 
@@ -62,19 +57,19 @@ void MFS1RX_IRQHandler(void)
 /* UART2 device driver structure */
 struct uart03_device uart2 =
 {
-	FM3_MFS2_UART,
-	MFS2RX_IRQn,
-	MFS2TX_IRQn,
+    FM3_MFS2_UART,
+    MFS2RX_IRQn,
+    MFS2TX_IRQn,
 };
 struct rt_serial_device serial2;
 
 void MFS2RX_IRQHandler(void)
 {
-	/* enter interrupt */
-	rt_interrupt_enter();
-	rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND);
-	/* leave interrupt */
-	rt_interrupt_leave();
+    /* enter interrupt */
+    rt_interrupt_enter();
+    rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND);
+    /* leave interrupt */
+    rt_interrupt_leave();
 }
 #endif
 
@@ -82,19 +77,19 @@ void MFS2RX_IRQHandler(void)
 /* UART3 device driver structure */
 struct uart03_device uart3 =
 {
-	FM3_MFS3_UART,
-	MFS3RX_IRQn,
-	MFS3TX_IRQn,
+    FM3_MFS3_UART,
+    MFS3RX_IRQn,
+    MFS3TX_IRQn,
 };
 struct rt_serial_device serial3;
 
 void MFS3RX_IRQHandler(void)
 {
-	/* enter interrupt */
-	rt_interrupt_enter();
-	rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND);
-	/* leave interrupt */
-	rt_interrupt_leave();
+    /* enter interrupt */
+    rt_interrupt_enter();
+    rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND);
+    /* leave interrupt */
+    rt_interrupt_leave();
 }
 #endif
 
@@ -102,20 +97,20 @@ void MFS3RX_IRQHandler(void)
 /* UART4 device driver structure */
 struct uart47_device uart4 =
 {
-	FM3_MFS4_UART,
-	MFS4RX_IRQn,
-	MFS4TX_IRQn,
-	FIFO_SIZE,
+    FM3_MFS4_UART,
+    MFS4RX_IRQn,
+    MFS4TX_IRQn,
+    FIFO_SIZE,
 };
 struct rt_serial_device serial4;
 
 void MFS4RX_IRQHandler(void)
 {
-	/* enter interrupt */
-	rt_interrupt_enter();
-	rt_hw_serial_isr(&serial4, RT_SERIAL_EVENT_RX_IND);
-	/* leave interrupt */
-	rt_interrupt_leave();
+    /* enter interrupt */
+    rt_interrupt_enter();
+    rt_hw_serial_isr(&serial4, RT_SERIAL_EVENT_RX_IND);
+    /* leave interrupt */
+    rt_interrupt_leave();
 }
 #endif
 
@@ -123,20 +118,20 @@ void MFS4RX_IRQHandler(void)
 /* UART5 device driver structure */
 struct uart47_device uart5 =
 {
-	FM3_MFS5_UART,
-	MFS5RX_IRQn,
-	MFS5TX_IRQn,
-	FIFO_SIZE,
+    FM3_MFS5_UART,
+    MFS5RX_IRQn,
+    MFS5TX_IRQn,
+    FIFO_SIZE,
 };
 struct rt_serial_device serial5;
 
 void MFS5RX_IRQHandler(void)
 {
-	/* enter interrupt */
-	rt_interrupt_enter();
-	rt_hw_serial_isr(&serial5, RT_SERIAL_EVENT_RX_IND);
-	/* leave interrupt */
-	rt_interrupt_leave();
+    /* enter interrupt */
+    rt_interrupt_enter();
+    rt_hw_serial_isr(&serial5, RT_SERIAL_EVENT_RX_IND);
+    /* leave interrupt */
+    rt_interrupt_leave();
 }
 #endif
 
@@ -144,20 +139,20 @@ void MFS5RX_IRQHandler(void)
 /* UART6 device driver structure */
 struct uart47_device uart6 =
 {
-	FM3_MFS6_UART,
-	MFS6RX_IRQn,
-	MFS6TX_IRQn,
-	FIFO_SIZE,
+    FM3_MFS6_UART,
+    MFS6RX_IRQn,
+    MFS6TX_IRQn,
+    FIFO_SIZE,
 };
 struct rt_serial_device serial6;
 
 void MFS6RX_IRQHandler(void)
 {
-	/* enter interrupt */
-	rt_interrupt_enter();
-	rt_hw_serial_isr(&serial6, RT_SERIAL_EVENT_RX_IND);
-	/* leave interrupt */
-	rt_interrupt_leave();
+    /* enter interrupt */
+    rt_interrupt_enter();
+    rt_hw_serial_isr(&serial6, RT_SERIAL_EVENT_RX_IND);
+    /* leave interrupt */
+    rt_interrupt_leave();
 }
 #endif
 
@@ -165,20 +160,20 @@ void MFS6RX_IRQHandler(void)
 /* UART7 device driver structure */
 struct uart47_device uart7 =
 {
-	FM3_MFS7_UART,
-	MFS7RX_IRQn,
-	MFS7TX_IRQn,
-	FIFO_SIZE,
+    FM3_MFS7_UART,
+    MFS7RX_IRQn,
+    MFS7TX_IRQn,
+    FIFO_SIZE,
 };
 struct rt_serial_device serial7;
 
 void MFS7RX_IRQHandler(void)
 {
-	/* enter interrupt */
-	rt_interrupt_enter();
-	rt_hw_serial_isr(&serial7, RT_SERIAL_EVENT_RX_IND);
-	/* leave interrupt */
-	rt_interrupt_leave();
+    /* enter interrupt */
+    rt_interrupt_enter();
+    rt_hw_serial_isr(&serial7, RT_SERIAL_EVENT_RX_IND);
+    /* leave interrupt */
+    rt_interrupt_leave();
 }
 
 #endif
@@ -186,749 +181,749 @@ void MFS7RX_IRQHandler(void)
 void uart_pin_setup(void)
 {
 #if defined(RT_USING_UART0_0)
-	/* Set UART Ch0 Port, SIN0_0(P21), SOT0_0(P22) */
-	FM3_GPIO->PFR2_f.P1 = 1;
-	FM3_GPIO->PFR2_f.P2 = 1;
-	FM3_GPIO->EPFR07_f.SIN0S0 = 1;
-	FM3_GPIO->EPFR07_f.SIN0S1 = 0;
-	FM3_GPIO->EPFR07_f.SOT0B0 = 1;
-	FM3_GPIO->EPFR07_f.SOT0B1 = 0;
+    /* Set UART Ch0 Port, SIN0_0(P21), SOT0_0(P22) */
+    FM3_GPIO->PFR2_f.P1 = 1;
+    FM3_GPIO->PFR2_f.P2 = 1;
+    FM3_GPIO->EPFR07_f.SIN0S0 = 1;
+    FM3_GPIO->EPFR07_f.SIN0S1 = 0;
+    FM3_GPIO->EPFR07_f.SOT0B0 = 1;
+    FM3_GPIO->EPFR07_f.SOT0B1 = 0;
 #elif defined(RT_USING_UART0_1)
-	/* Set UART Ch0 Port, SIN0_1(P14), SOT0_1(P15) */
-	FM3_GPIO->PFR1_f.P4 = 1;
-	FM3_GPIO->PFR1_f.P5 = 1;
-	FM3_GPIO->EPFR07_f.SIN0S0 = 0;
-	FM3_GPIO->EPFR07_f.SIN0S1 = 1;
-	FM3_GPIO->EPFR07_f.SOT0B0 = 0;
-	FM3_GPIO->EPFR07_f.SOT0B1 = 1;
+    /* Set UART Ch0 Port, SIN0_1(P14), SOT0_1(P15) */
+    FM3_GPIO->PFR1_f.P4 = 1;
+    FM3_GPIO->PFR1_f.P5 = 1;
+    FM3_GPIO->EPFR07_f.SIN0S0 = 0;
+    FM3_GPIO->EPFR07_f.SIN0S1 = 1;
+    FM3_GPIO->EPFR07_f.SOT0B0 = 0;
+    FM3_GPIO->EPFR07_f.SOT0B1 = 1;
 #endif
 
 #if defined(RT_USING_UART1_0)
-	/* Set UART Ch1 Port, SIN1_0(P56), SOT1_0(P57) */
-	FM3_GPIO->PFR5_f.P6 = 1;
-	FM3_GPIO->PFR5_f.P7 = 1;
-	FM3_GPIO->EPFR07_f.SIN1S0 = 1;
-	FM3_GPIO->EPFR07_f.SIN1S1 = 0;
-	FM3_GPIO->EPFR07_f.SOT1B0 = 1;
-	FM3_GPIO->EPFR07_f.SOT1B1 = 0;
+    /* Set UART Ch1 Port, SIN1_0(P56), SOT1_0(P57) */
+    FM3_GPIO->PFR5_f.P6 = 1;
+    FM3_GPIO->PFR5_f.P7 = 1;
+    FM3_GPIO->EPFR07_f.SIN1S0 = 1;
+    FM3_GPIO->EPFR07_f.SIN1S1 = 0;
+    FM3_GPIO->EPFR07_f.SOT1B0 = 1;
+    FM3_GPIO->EPFR07_f.SOT1B1 = 0;
 #elif defined(RT_USING_UART1_1)
-	/* Set UART Ch1 Port, SIN1_1(P11), SOT1_1(P12) */
-	FM3_GPIO->PFR1_f.P1 = 1;
-	FM3_GPIO->PFR1_f.P2 = 1;
-	FM3_GPIO->EPFR07_f.SIN1S0 = 0;
-	FM3_GPIO->EPFR07_f.SIN1S1 = 1;
-	FM3_GPIO->EPFR07_f.SOT1B0 = 0;
-	FM3_GPIO->EPFR07_f.SOT1B1 = 1;
+    /* Set UART Ch1 Port, SIN1_1(P11), SOT1_1(P12) */
+    FM3_GPIO->PFR1_f.P1 = 1;
+    FM3_GPIO->PFR1_f.P2 = 1;
+    FM3_GPIO->EPFR07_f.SIN1S0 = 0;
+    FM3_GPIO->EPFR07_f.SIN1S1 = 1;
+    FM3_GPIO->EPFR07_f.SOT1B0 = 0;
+    FM3_GPIO->EPFR07_f.SOT1B1 = 1;
 #endif
 
 #if defined(RT_USING_UART2_0)
-	/* Set UART Ch2 Port, SIN2_0(P72), SOT2_0(P73) */
-	FM3_GPIO->PFR7_f.P2 = 1;
-	FM3_GPIO->PFR7_f.P3 = 1;
-	FM3_GPIO->EPFR07_f.SIN2S0 = 1;
-	FM3_GPIO->EPFR07_f.SIN2S1 = 0;
-	FM3_GPIO->EPFR07_f.SOT2B0 = 1;
-	FM3_GPIO->EPFR07_f.SOT2B1 = 0;
+    /* Set UART Ch2 Port, SIN2_0(P72), SOT2_0(P73) */
+    FM3_GPIO->PFR7_f.P2 = 1;
+    FM3_GPIO->PFR7_f.P3 = 1;
+    FM3_GPIO->EPFR07_f.SIN2S0 = 1;
+    FM3_GPIO->EPFR07_f.SIN2S1 = 0;
+    FM3_GPIO->EPFR07_f.SOT2B0 = 1;
+    FM3_GPIO->EPFR07_f.SOT2B1 = 0;
 #elif defined(RT_USING_UART2_1)
-	/* Set UART Ch2 Port, SIN2_1(P24), SOT2_1(P25) */
-	FM3_GPIO->PFR2_f.P4 = 1;
-	FM3_GPIO->PFR2_f.P5 = 1;
-	FM3_GPIO->EPFR07_f.SIN2S0 = 0;
-	FM3_GPIO->EPFR07_f.SIN2S1 = 1;
-	FM3_GPIO->EPFR07_f.SOT2B0 = 0;
-	FM3_GPIO->EPFR07_f.SOT2B1 = 1;
+    /* Set UART Ch2 Port, SIN2_1(P24), SOT2_1(P25) */
+    FM3_GPIO->PFR2_f.P4 = 1;
+    FM3_GPIO->PFR2_f.P5 = 1;
+    FM3_GPIO->EPFR07_f.SIN2S0 = 0;
+    FM3_GPIO->EPFR07_f.SIN2S1 = 1;
+    FM3_GPIO->EPFR07_f.SOT2B0 = 0;
+    FM3_GPIO->EPFR07_f.SOT2B1 = 1;
 #elif defined(RT_USING_UART2_2)
-	/* Set UART Ch2 Port, SIN2_2(P17), SOT2_2(P18) */
-	FM3_GPIO->PFR1_f.P7 = 1;
-	FM3_GPIO->PFR1_f.P8 = 1;
-	FM3_GPIO->EPFR07_f.SIN2S0 = 1;
-	FM3_GPIO->EPFR07_f.SIN2S1 = 1;
-	FM3_GPIO->EPFR07_f.SOT2B0 = 1;
-	FM3_GPIO->EPFR07_f.SOT2B1 = 1;
+    /* Set UART Ch2 Port, SIN2_2(P17), SOT2_2(P18) */
+    FM3_GPIO->PFR1_f.P7 = 1;
+    FM3_GPIO->PFR1_f.P8 = 1;
+    FM3_GPIO->EPFR07_f.SIN2S0 = 1;
+    FM3_GPIO->EPFR07_f.SIN2S1 = 1;
+    FM3_GPIO->EPFR07_f.SOT2B0 = 1;
+    FM3_GPIO->EPFR07_f.SOT2B1 = 1;
 #endif
 
 #if defined(RT_USING_UART3_0)
-	/* Set UART Ch3 Port, SIN3_0(P66), SOT3_0(P67) */
-	FM3_GPIO->PFR6_f.P6 = 1;
-	FM3_GPIO->PFR6_f.P7 = 1;
-	FM3_GPIO->EPFR07_f.SIN3S0 = 1;
-	FM3_GPIO->EPFR07_f.SIN3S1 = 0;
-	FM3_GPIO->EPFR07_f.SOT3B0 = 1;
-	FM3_GPIO->EPFR07_f.SOT3B1 = 0;
+    /* Set UART Ch3 Port, SIN3_0(P66), SOT3_0(P67) */
+    FM3_GPIO->PFR6_f.P6 = 1;
+    FM3_GPIO->PFR6_f.P7 = 1;
+    FM3_GPIO->EPFR07_f.SIN3S0 = 1;
+    FM3_GPIO->EPFR07_f.SIN3S1 = 0;
+    FM3_GPIO->EPFR07_f.SOT3B0 = 1;
+    FM3_GPIO->EPFR07_f.SOT3B1 = 0;
 #elif defined(RT_USING_UART3_1)
-	/* Set UART Ch3 Port, SIN3_1(P50), SOT3_1(P51) */
-	FM3_GPIO->PFR5_f.P0 = 1;
-	FM3_GPIO->PFR5_f.P1 = 1;
-	FM3_GPIO->EPFR07_f.SIN3S0 = 0;
-	FM3_GPIO->EPFR07_f.SIN3S1 = 1;
-	FM3_GPIO->EPFR07_f.SOT3B0 = 0;
-	FM3_GPIO->EPFR07_f.SOT3B1 = 1;
+    /* Set UART Ch3 Port, SIN3_1(P50), SOT3_1(P51) */
+    FM3_GPIO->PFR5_f.P0 = 1;
+    FM3_GPIO->PFR5_f.P1 = 1;
+    FM3_GPIO->EPFR07_f.SIN3S0 = 0;
+    FM3_GPIO->EPFR07_f.SIN3S1 = 1;
+    FM3_GPIO->EPFR07_f.SOT3B0 = 0;
+    FM3_GPIO->EPFR07_f.SOT3B1 = 1;
 #elif defined(RT_USING_UART3_2)
-	/* Set UART Ch3 Port, SIN3_2(P48), SOT3_2(P49) */
-	FM3_GPIO->PFR4_f.P8 = 1;
-	FM3_GPIO->PFR4_f.P9 = 1;
-	FM3_GPIO->EPFR07_f.SIN3S0 = 1;
-	FM3_GPIO->EPFR07_f.SIN3S1 = 1;
-	FM3_GPIO->EPFR07_f.SOT3B0 = 1;
-	FM3_GPIO->EPFR07_f.SOT3B1 = 1;
+    /* Set UART Ch3 Port, SIN3_2(P48), SOT3_2(P49) */
+    FM3_GPIO->PFR4_f.P8 = 1;
+    FM3_GPIO->PFR4_f.P9 = 1;
+    FM3_GPIO->EPFR07_f.SIN3S0 = 1;
+    FM3_GPIO->EPFR07_f.SIN3S1 = 1;
+    FM3_GPIO->EPFR07_f.SOT3B0 = 1;
+    FM3_GPIO->EPFR07_f.SOT3B1 = 1;
 #endif
 
 #if defined(RT_USING_UART4_0)
-	/* Set UART Ch4 Port, SIN4_0(P0A), SOT4_0(P0B), CTS4_0(P0E), RTS4_0(P0D) */
-	FM3_GPIO->PFR0_f.PA = 1;
-	FM3_GPIO->PFR0_f.PB = 1;
-	FM3_GPIO->PFR0_f.PD = 1;
-	FM3_GPIO->PFR0_f.PE = 1;
-	FM3_GPIO->EPFR08_f.SIN4S0 = 1;
-	FM3_GPIO->EPFR08_f.SIN4S1 = 0;
-	FM3_GPIO->EPFR08_f.SOT4B0 = 1;
-	FM3_GPIO->EPFR08_f.SOT4B1 = 0;
-	FM3_GPIO->EPFR08_f.CTS4S0 = 1;
-	FM3_GPIO->EPFR08_f.CTS4S1 = 0;
-	FM3_GPIO->EPFR08_f.RTS4E0 = 1;
-	FM3_GPIO->EPFR08_f.RTS4E1 = 0;
+    /* Set UART Ch4 Port, SIN4_0(P0A), SOT4_0(P0B), CTS4_0(P0E), RTS4_0(P0D) */
+    FM3_GPIO->PFR0_f.PA = 1;
+    FM3_GPIO->PFR0_f.PB = 1;
+    FM3_GPIO->PFR0_f.PD = 1;
+    FM3_GPIO->PFR0_f.PE = 1;
+    FM3_GPIO->EPFR08_f.SIN4S0 = 1;
+    FM3_GPIO->EPFR08_f.SIN4S1 = 0;
+    FM3_GPIO->EPFR08_f.SOT4B0 = 1;
+    FM3_GPIO->EPFR08_f.SOT4B1 = 0;
+    FM3_GPIO->EPFR08_f.CTS4S0 = 1;
+    FM3_GPIO->EPFR08_f.CTS4S1 = 0;
+    FM3_GPIO->EPFR08_f.RTS4E0 = 1;
+    FM3_GPIO->EPFR08_f.RTS4E1 = 0;
 #elif defined(RT_USING_UART4_1)
-	/* Set UART Ch4 Port, SIN4_1(P1A), SOT4_1(P1B), CTS4_1(P1D), RTS4_1(P1E) */
-	FM3_GPIO->PFR1_f.PA = 1;
-	FM3_GPIO->PFR1_f.PB = 1;
-	FM3_GPIO->PFR1_f.PD = 1;
-	FM3_GPIO->PFR1_f.PE = 1;
-	FM3_GPIO->EPFR08_f.SIN4S0 = 0;
-	FM3_GPIO->EPFR08_f.SIN4S1 = 1;
-	FM3_GPIO->EPFR08_f.SOT4B0 = 0;
-	FM3_GPIO->EPFR08_f.SOT4B1 = 1;
-	FM3_GPIO->EPFR08_f.CTS4S0 = 0;
-	FM3_GPIO->EPFR08_f.CTS4S1 = 1;
-	FM3_GPIO->EPFR08_f.RTS4E0 = 0;
-	FM3_GPIO->EPFR08_f.RTS4E1 = 1;
+    /* Set UART Ch4 Port, SIN4_1(P1A), SOT4_1(P1B), CTS4_1(P1D), RTS4_1(P1E) */
+    FM3_GPIO->PFR1_f.PA = 1;
+    FM3_GPIO->PFR1_f.PB = 1;
+    FM3_GPIO->PFR1_f.PD = 1;
+    FM3_GPIO->PFR1_f.PE = 1;
+    FM3_GPIO->EPFR08_f.SIN4S0 = 0;
+    FM3_GPIO->EPFR08_f.SIN4S1 = 1;
+    FM3_GPIO->EPFR08_f.SOT4B0 = 0;
+    FM3_GPIO->EPFR08_f.SOT4B1 = 1;
+    FM3_GPIO->EPFR08_f.CTS4S0 = 0;
+    FM3_GPIO->EPFR08_f.CTS4S1 = 1;
+    FM3_GPIO->EPFR08_f.RTS4E0 = 0;
+    FM3_GPIO->EPFR08_f.RTS4E1 = 1;
 #elif defined(RT_USING_UART4_2)
-	/* Set UART Ch4 Port, SIN4_2(P05), SOT4_2(P06), CTS4_2(P08), RTS4_2(P09)*/
-	FM3_GPIO->PFR0_f.P5 = 1;
-	FM3_GPIO->PFR0_f.P6 = 1;
-	FM3_GPIO->PFR0_f.P8 = 1;
-	FM3_GPIO->PFR0_f.P9 = 1;
-	FM3_GPIO->EPFR08_f.SIN4S0 = 1;
-	FM3_GPIO->EPFR08_f.SIN4S1 = 1;
-	FM3_GPIO->EPFR08_f.SOT4B0 = 1;
-	FM3_GPIO->EPFR08_f.SOT4B1 = 1;
-	FM3_GPIO->EPFR08_f.CTS4S0 = 1;
-	FM3_GPIO->EPFR08_f.CTS4S1 = 1;
-	FM3_GPIO->EPFR08_f.RTS4E0 = 1;
-	FM3_GPIO->EPFR08_f.RTS4E1 = 1;
+    /* Set UART Ch4 Port, SIN4_2(P05), SOT4_2(P06), CTS4_2(P08), RTS4_2(P09)*/
+    FM3_GPIO->PFR0_f.P5 = 1;
+    FM3_GPIO->PFR0_f.P6 = 1;
+    FM3_GPIO->PFR0_f.P8 = 1;
+    FM3_GPIO->PFR0_f.P9 = 1;
+    FM3_GPIO->EPFR08_f.SIN4S0 = 1;
+    FM3_GPIO->EPFR08_f.SIN4S1 = 1;
+    FM3_GPIO->EPFR08_f.SOT4B0 = 1;
+    FM3_GPIO->EPFR08_f.SOT4B1 = 1;
+    FM3_GPIO->EPFR08_f.CTS4S0 = 1;
+    FM3_GPIO->EPFR08_f.CTS4S1 = 1;
+    FM3_GPIO->EPFR08_f.RTS4E0 = 1;
+    FM3_GPIO->EPFR08_f.RTS4E1 = 1;
 #endif
 
 #if defined(RT_USING_UART5_0)
-	/* Set UART Ch5 Port, SIN5_0(P60), SOT5_0(P61) */
-	FM3_GPIO->PFR6_f.P0 = 1;
-	FM3_GPIO->PFR6_f.P1 = 1;
-	FM3_GPIO->EPFR08_f.SIN5S0 = 1;
-	FM3_GPIO->EPFR08_f.SIN5S1 = 0;
-	FM3_GPIO->EPFR08_f.SOT5B0 = 1;
-	FM3_GPIO->EPFR08_f.SOT5B1 = 0;
+    /* Set UART Ch5 Port, SIN5_0(P60), SOT5_0(P61) */
+    FM3_GPIO->PFR6_f.P0 = 1;
+    FM3_GPIO->PFR6_f.P1 = 1;
+    FM3_GPIO->EPFR08_f.SIN5S0 = 1;
+    FM3_GPIO->EPFR08_f.SIN5S1 = 0;
+    FM3_GPIO->EPFR08_f.SOT5B0 = 1;
+    FM3_GPIO->EPFR08_f.SOT5B1 = 0;
 #elif defined(RT_USING_UART5_1)
-	/* Set UART Ch5 Port, SIN5_1(P63), SOT5_1(P64) */
-	FM3_GPIO->PFR6_f.P3 = 1;
-	FM3_GPIO->PFR6_f.P4 = 1;
-	FM3_GPIO->EPFR08_f.SIN5S0 = 0;
-	FM3_GPIO->EPFR08_f.SIN5S1 = 1;
-	FM3_GPIO->EPFR08_f.SOT5B0 = 0;
-	FM3_GPIO->EPFR08_f.SOT5B1 = 1;
+    /* Set UART Ch5 Port, SIN5_1(P63), SOT5_1(P64) */
+    FM3_GPIO->PFR6_f.P3 = 1;
+    FM3_GPIO->PFR6_f.P4 = 1;
+    FM3_GPIO->EPFR08_f.SIN5S0 = 0;
+    FM3_GPIO->EPFR08_f.SIN5S1 = 1;
+    FM3_GPIO->EPFR08_f.SOT5B0 = 0;
+    FM3_GPIO->EPFR08_f.SOT5B1 = 1;
 #elif defined(RT_USING_UART5_2)
-	/* Set UART Ch5 Port, SIN5_2(P36), SOT5_2(P37) */
-	FM3_GPIO->PFR3_f.P6 = 1;
-	FM3_GPIO->PFR3_f.P7 = 1;
-	FM3_GPIO->EPFR08_f.SIN5S0 = 1;
-	FM3_GPIO->EPFR08_f.SIN5S1 = 1;
-	FM3_GPIO->EPFR08_f.SOT5B0 = 1;
-	FM3_GPIO->EPFR08_f.SOT5B1 = 1;
+    /* Set UART Ch5 Port, SIN5_2(P36), SOT5_2(P37) */
+    FM3_GPIO->PFR3_f.P6 = 1;
+    FM3_GPIO->PFR3_f.P7 = 1;
+    FM3_GPIO->EPFR08_f.SIN5S0 = 1;
+    FM3_GPIO->EPFR08_f.SIN5S1 = 1;
+    FM3_GPIO->EPFR08_f.SOT5B0 = 1;
+    FM3_GPIO->EPFR08_f.SOT5B1 = 1;
 #endif
 
 #if defined(RT_USING_UART6_0)
-	/* Set UART Ch6 Port, SIN6_0(P53), SOT6_0(P54) */
-	FM3_GPIO->PFR5_f.P3 = 1;
-	FM3_GPIO->PFR5_f.P4 = 1;
-	FM3_GPIO->EPFR08_f.SIN6S0 = 1;
-	FM3_GPIO->EPFR08_f.SIN6S1 = 0;
-	FM3_GPIO->EPFR08_f.SOT6B0 = 1;
-	FM3_GPIO->EPFR08_f.SOT6B1 = 0;
+    /* Set UART Ch6 Port, SIN6_0(P53), SOT6_0(P54) */
+    FM3_GPIO->PFR5_f.P3 = 1;
+    FM3_GPIO->PFR5_f.P4 = 1;
+    FM3_GPIO->EPFR08_f.SIN6S0 = 1;
+    FM3_GPIO->EPFR08_f.SIN6S1 = 0;
+    FM3_GPIO->EPFR08_f.SOT6B0 = 1;
+    FM3_GPIO->EPFR08_f.SOT6B1 = 0;
 #elif defined(RT_USING_UART6_1)
-	/* Set UART Ch6 Port, SIN6_1(P33), SOT6_1(P32) */
-	FM3_GPIO->PFR3_f.P2 = 1;
-	FM3_GPIO->PFR3_f.P3 = 1;
-	FM3_GPIO->EPFR08_f.SIN6S0 = 0;
-	FM3_GPIO->EPFR08_f.SIN6S1 = 1;
-	FM3_GPIO->EPFR08_f.SOT6B0 = 0;
-	FM3_GPIO->EPFR08_f.SOT6B1 = 1;
+    /* Set UART Ch6 Port, SIN6_1(P33), SOT6_1(P32) */
+    FM3_GPIO->PFR3_f.P2 = 1;
+    FM3_GPIO->PFR3_f.P3 = 1;
+    FM3_GPIO->EPFR08_f.SIN6S0 = 0;
+    FM3_GPIO->EPFR08_f.SIN6S1 = 1;
+    FM3_GPIO->EPFR08_f.SOT6B0 = 0;
+    FM3_GPIO->EPFR08_f.SOT6B1 = 1;
 #endif
 
 #if defined(RT_USING_UART7_0)
-	/* Set UART Ch7 Port, SIN7_0(P59), SOT7_0(P5A) */
-	FM3_GPIO->PFR5_f.P9 = 1;
-	FM3_GPIO->PFR5_f.PA = 1;
-	FM3_GPIO->EPFR08_f.SIN7S0 = 1;
-	FM3_GPIO->EPFR08_f.SIN7S1 = 0;
-	FM3_GPIO->EPFR08_f.SOT7B0 = 1;
-	FM3_GPIO->EPFR08_f.SOT7B1 = 0;
+    /* Set UART Ch7 Port, SIN7_0(P59), SOT7_0(P5A) */
+    FM3_GPIO->PFR5_f.P9 = 1;
+    FM3_GPIO->PFR5_f.PA = 1;
+    FM3_GPIO->EPFR08_f.SIN7S0 = 1;
+    FM3_GPIO->EPFR08_f.SIN7S1 = 0;
+    FM3_GPIO->EPFR08_f.SOT7B0 = 1;
+    FM3_GPIO->EPFR08_f.SOT7B1 = 0;
 #elif defined(RT_USING_UART7_1)
-	/* Set UART Ch7 Port, SIN7_1(P4E), SOT7_1(P4D) */
-	FM3_GPIO->PFR4_f.PD = 1;
-	FM3_GPIO->PFR4_f.PE = 1;
-	FM3_GPIO->EPFR08_f.SIN7S0 = 0;
-	FM3_GPIO->EPFR08_f.SIN7S1 = 1;
-	FM3_GPIO->EPFR08_f.SOT7B0 = 0;
-	FM3_GPIO->EPFR08_f.SOT7B1 = 1;
+    /* Set UART Ch7 Port, SIN7_1(P4E), SOT7_1(P4D) */
+    FM3_GPIO->PFR4_f.PD = 1;
+    FM3_GPIO->PFR4_f.PE = 1;
+    FM3_GPIO->EPFR08_f.SIN7S0 = 0;
+    FM3_GPIO->EPFR08_f.SIN7S1 = 1;
+    FM3_GPIO->EPFR08_f.SOT7B0 = 0;
+    FM3_GPIO->EPFR08_f.SOT7B1 = 1;
 #endif
 }
 
 static rt_err_t uart03_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
 {
-	struct uart03_device *uart;
+    struct uart03_device *uart;
 
-	RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(serial != RT_NULL);
 
-	uart = (struct uart03_device *)serial->parent.user_data;
+    uart = (struct uart03_device *)serial->parent.user_data;
 
-	uart->uart_regs->SMR = SMR_MD_UART | SMR_SOE;
+    uart->uart_regs->SMR = SMR_MD_UART | SMR_SOE;
 
-	/* set baudreate */
-	uart->uart_regs->BGR = (40000000UL + (cfg->baud_rate/2))/cfg->baud_rate - 1;
+    /* set baudreate */
+    uart->uart_regs->BGR = (40000000UL + (cfg->baud_rate/2))/cfg->baud_rate - 1;
 
-	/* set stop bits */
-	switch (cfg->stop_bits)
-	{
-	case STOP_BITS_1:
-		uart->uart_regs->SMR_f.SBL = 0;
-		uart->uart_regs->ESCR_f.ESBL = 0;
-		break;
-	case STOP_BITS_2:
-		uart->uart_regs->SMR_f.SBL = 1;
-		uart->uart_regs->ESCR_f.ESBL = 0;
-		break;
-	case STOP_BITS_3:
-		uart->uart_regs->SMR_f.SBL = 0;
-		uart->uart_regs->ESCR_f.ESBL = 1;
-		break;
-	case STOP_BITS_4:
-		uart->uart_regs->SMR_f.SBL = 1;
-		uart->uart_regs->ESCR_f.ESBL = 1;
-		break;
-	default:
-		return RT_ERROR;
-	}
+    /* set stop bits */
+    switch (cfg->stop_bits)
+    {
+    case STOP_BITS_1:
+        uart->uart_regs->SMR_f.SBL = 0;
+        uart->uart_regs->ESCR_f.ESBL = 0;
+        break;
+    case STOP_BITS_2:
+        uart->uart_regs->SMR_f.SBL = 1;
+        uart->uart_regs->ESCR_f.ESBL = 0;
+        break;
+    case STOP_BITS_3:
+        uart->uart_regs->SMR_f.SBL = 0;
+        uart->uart_regs->ESCR_f.ESBL = 1;
+        break;
+    case STOP_BITS_4:
+        uart->uart_regs->SMR_f.SBL = 1;
+        uart->uart_regs->ESCR_f.ESBL = 1;
+        break;
+    default:
+        return RT_ERROR;
+    }
 
-	/* set data bits */
-	switch (cfg->data_bits)
-	{
-	case DATA_BITS_5:
-		uart->uart_regs->ESCR_f.L0 = 1;
-		uart->uart_regs->ESCR_f.L1 = 0;
-		uart->uart_regs->ESCR_f.L2 = 0;
-		break;
-	case DATA_BITS_6:
-		uart->uart_regs->ESCR_f.L0 = 0;
-		uart->uart_regs->ESCR_f.L1 = 1;
-		uart->uart_regs->ESCR_f.L2 = 0;
-		break;
-	case DATA_BITS_7:
-		uart->uart_regs->ESCR_f.L0 = 1;
-		uart->uart_regs->ESCR_f.L1 = 1;
-		uart->uart_regs->ESCR_f.L2 = 0;
-		break;
-	case DATA_BITS_8:
-		uart->uart_regs->ESCR_f.L0 = 0;
-		uart->uart_regs->ESCR_f.L1 = 0;
-		uart->uart_regs->ESCR_f.L2 = 0;
-		break;
-	case DATA_BITS_9:
-		uart->uart_regs->ESCR_f.L0 = 0;
-		uart->uart_regs->ESCR_f.L1 = 0;
-		uart->uart_regs->ESCR_f.L2 = 1;
-		break;
-	default:
-		return RT_ERROR;
-	}
+    /* set data bits */
+    switch (cfg->data_bits)
+    {
+    case DATA_BITS_5:
+        uart->uart_regs->ESCR_f.L0 = 1;
+        uart->uart_regs->ESCR_f.L1 = 0;
+        uart->uart_regs->ESCR_f.L2 = 0;
+        break;
+    case DATA_BITS_6:
+        uart->uart_regs->ESCR_f.L0 = 0;
+        uart->uart_regs->ESCR_f.L1 = 1;
+        uart->uart_regs->ESCR_f.L2 = 0;
+        break;
+    case DATA_BITS_7:
+        uart->uart_regs->ESCR_f.L0 = 1;
+        uart->uart_regs->ESCR_f.L1 = 1;
+        uart->uart_regs->ESCR_f.L2 = 0;
+        break;
+    case DATA_BITS_8:
+        uart->uart_regs->ESCR_f.L0 = 0;
+        uart->uart_regs->ESCR_f.L1 = 0;
+        uart->uart_regs->ESCR_f.L2 = 0;
+        break;
+    case DATA_BITS_9:
+        uart->uart_regs->ESCR_f.L0 = 0;
+        uart->uart_regs->ESCR_f.L1 = 0;
+        uart->uart_regs->ESCR_f.L2 = 1;
+        break;
+    default:
+        return RT_ERROR;
+    }
 
-	/* set parity */
-	switch (cfg->parity)
-	{
-	case PARITY_NONE:
-		uart->uart_regs->ESCR_f.PEN = 0;
-		break;
-	case PARITY_EVEN:
-		uart->uart_regs->ESCR_f.PEN = 1;
-		uart->uart_regs->ESCR_f.P   = 0;
-		break;
-	case PARITY_ODD:
-		uart->uart_regs->ESCR_f.PEN = 1;
-		uart->uart_regs->ESCR_f.P   = 1;
-		break;
-	default:
-		return RT_ERROR;
-	}
+    /* set parity */
+    switch (cfg->parity)
+    {
+    case PARITY_NONE:
+        uart->uart_regs->ESCR_f.PEN = 0;
+        break;
+    case PARITY_EVEN:
+        uart->uart_regs->ESCR_f.PEN = 1;
+        uart->uart_regs->ESCR_f.P   = 0;
+        break;
+    case PARITY_ODD:
+        uart->uart_regs->ESCR_f.PEN = 1;
+        uart->uart_regs->ESCR_f.P   = 1;
+        break;
+    default:
+        return RT_ERROR;
+    }
 
-	/* set bit order */
-	switch (cfg->bit_order)
-	{
-	case BIT_ORDER_LSB:
-		uart->uart_regs->SMR_f.BDS = 0;
-		break;
-	case BIT_ORDER_MSB:
-		uart->uart_regs->SMR_f.BDS = 1;
-		break;
-	default:
-		return RT_ERROR;
-	}
+    /* set bit order */
+    switch (cfg->bit_order)
+    {
+    case BIT_ORDER_LSB:
+        uart->uart_regs->SMR_f.BDS = 0;
+        break;
+    case BIT_ORDER_MSB:
+        uart->uart_regs->SMR_f.BDS = 1;
+        break;
+    default:
+        return RT_ERROR;
+    }
 
-	/* set NRZ mode */
-	switch (cfg->invert)
-	{
-	case NRZ_NORMAL:
-		uart->uart_regs->ESCR_f.INV = 0;
-		break;
-	case NRZ_INVERTED:
-		uart->uart_regs->ESCR_f.INV = 1;
-		break;
-	default:
-		return RT_ERROR;
-	}
-	
-	uart->uart_regs->SCR = SCR_RXE | SCR_TXE | SCR_RIE;
+    /* set NRZ mode */
+    switch (cfg->invert)
+    {
+    case NRZ_NORMAL:
+        uart->uart_regs->ESCR_f.INV = 0;
+        break;
+    case NRZ_INVERTED:
+        uart->uart_regs->ESCR_f.INV = 1;
+        break;
+    default:
+        return RT_ERROR;
+    }
 
-	return RT_EOK;
+    uart->uart_regs->SCR = SCR_RXE | SCR_TXE | SCR_RIE;
+
+    return RT_EOK;
 }
- 
+
 static rt_err_t uart03_control(struct rt_serial_device *serial, int cmd, void *arg)
 {
-	struct uart03_device *uart;
-        
-	RT_ASSERT(serial != RT_NULL);	
-	uart = (struct uart03_device *)serial->parent.user_data;
-	
-	switch (cmd)
-	{
-	case RT_DEVICE_CTRL_CLR_INT:
-		/* disable rx irq */
-		UART_DISABLE_IRQ(uart->rx_irq);
-		break;
-	case RT_DEVICE_CTRL_SET_INT:
-		/* enable rx irq */
-		UART_ENABLE_IRQ(uart->rx_irq);
-		break;
-	}
+    struct uart03_device *uart;
 
-	return (RT_EOK);	
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct uart03_device *)serial->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        UART_DISABLE_IRQ(uart->rx_irq);
+        break;
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        UART_ENABLE_IRQ(uart->rx_irq);
+        break;
+    }
+
+    return (RT_EOK);
 }
-    
+
 static int uart03_putc(struct rt_serial_device *serial, char c)
 {
-	struct uart03_device *uart;
+    struct uart03_device *uart;
 
-	RT_ASSERT(serial != RT_NULL);	
-	
-	uart = (struct uart03_device *)serial->parent.user_data;
-	/* while send buffer is empty */
-	while (!(uart->uart_regs->SSR & SSR_TDRE));
-	/* write to send buffer */
-	uart->uart_regs->TDR = c;
+    RT_ASSERT(serial != RT_NULL);
 
-	return (1);	
+    uart = (struct uart03_device *)serial->parent.user_data;
+    /* while send buffer is empty */
+    while (!(uart->uart_regs->SSR & SSR_TDRE));
+    /* write to send buffer */
+    uart->uart_regs->TDR = c;
+
+    return (1);
 }
 
 static int uart03_getc(struct rt_serial_device *serial)
-{	
-	struct uart03_device *uart;
-	int ch;
-	
-	RT_ASSERT(serial != RT_NULL);	
-	
-	uart = (struct uart03_device *)serial->parent.user_data;
-	/* receive buffer is full */
-	if (uart->uart_regs->SSR & SSR_RDRF)
-	{
-		ch = uart->uart_regs->RDR & 0xff;
-		return (ch);
-	}
-	else
-		return (-1);	
+{
+    struct uart03_device *uart;
+    int ch;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = (struct uart03_device *)serial->parent.user_data;
+    /* receive buffer is full */
+    if (uart->uart_regs->SSR & SSR_RDRF)
+    {
+        ch = uart->uart_regs->RDR & 0xff;
+        return (ch);
+    }
+    else
+        return (-1);
 }
 
 static struct rt_uart_ops uart03_ops =
 {
-	uart03_configure,
-	uart03_control,
-	uart03_putc,
-	uart03_getc,
+    uart03_configure,
+    uart03_control,
+    uart03_putc,
+    uart03_getc,
 };
 
 static rt_err_t uart47_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
 {
-	struct uart47_device *uart;
+    struct uart47_device *uart;
 
-	RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(serial != RT_NULL);
 
-	uart = (struct uart47_device *)serial->parent.user_data;
+    uart = (struct uart47_device *)serial->parent.user_data;
 
-	uart->uart_regs->SMR = SMR_MD_UART | SMR_SOE;
+    uart->uart_regs->SMR = SMR_MD_UART | SMR_SOE;
 
-	/* set baudreate */
-	uart->uart_regs->BGR = (40000000UL + (cfg->baud_rate/2))/cfg->baud_rate - 1;
+    /* set baudreate */
+    uart->uart_regs->BGR = (40000000UL + (cfg->baud_rate/2))/cfg->baud_rate - 1;
 
-	/* set stop bits */
-	switch (cfg->stop_bits)
-	{
-	case STOP_BITS_1:
-		uart->uart_regs->SMR_f.SBL = 0;
-		uart->uart_regs->ESCR_f.ESBL = 0;
-		break;
-	case STOP_BITS_2:
-		uart->uart_regs->SMR_f.SBL = 1;
-		uart->uart_regs->ESCR_f.ESBL = 0;
-		break;
-	case STOP_BITS_3:
-		uart->uart_regs->SMR_f.SBL = 0;
-		uart->uart_regs->ESCR_f.ESBL = 1;
-		break;
-	case STOP_BITS_4:
-		uart->uart_regs->SMR_f.SBL = 1;
-		uart->uart_regs->ESCR_f.ESBL = 1;
-		break;
-	default:
-		return RT_ERROR;
-	}
+    /* set stop bits */
+    switch (cfg->stop_bits)
+    {
+    case STOP_BITS_1:
+        uart->uart_regs->SMR_f.SBL = 0;
+        uart->uart_regs->ESCR_f.ESBL = 0;
+        break;
+    case STOP_BITS_2:
+        uart->uart_regs->SMR_f.SBL = 1;
+        uart->uart_regs->ESCR_f.ESBL = 0;
+        break;
+    case STOP_BITS_3:
+        uart->uart_regs->SMR_f.SBL = 0;
+        uart->uart_regs->ESCR_f.ESBL = 1;
+        break;
+    case STOP_BITS_4:
+        uart->uart_regs->SMR_f.SBL = 1;
+        uart->uart_regs->ESCR_f.ESBL = 1;
+        break;
+    default:
+        return RT_ERROR;
+    }
 
-	/* set data bits */
-	switch (cfg->data_bits)
-	{
-	case DATA_BITS_5:
-		uart->uart_regs->ESCR_f.L0 = 1;
-		uart->uart_regs->ESCR_f.L1 = 0;
-		uart->uart_regs->ESCR_f.L2 = 0;
-		break;
-	case DATA_BITS_6:
-		uart->uart_regs->ESCR_f.L0 = 0;
-		uart->uart_regs->ESCR_f.L1 = 1;
-		uart->uart_regs->ESCR_f.L2 = 0;
-		break;
-	case DATA_BITS_7:
-		uart->uart_regs->ESCR_f.L0 = 1;
-		uart->uart_regs->ESCR_f.L1 = 1;
-		uart->uart_regs->ESCR_f.L2 = 0;
-		break;
-	case DATA_BITS_8:
-		uart->uart_regs->ESCR_f.L0 = 0;
-		uart->uart_regs->ESCR_f.L1 = 0;
-		uart->uart_regs->ESCR_f.L2 = 0;
-		break;
-	case DATA_BITS_9:
-		uart->uart_regs->ESCR_f.L0 = 0;
-		uart->uart_regs->ESCR_f.L1 = 0;
-		uart->uart_regs->ESCR_f.L2 = 1;
-		break;
-	default:
-		return RT_ERROR;
-	}
+    /* set data bits */
+    switch (cfg->data_bits)
+    {
+    case DATA_BITS_5:
+        uart->uart_regs->ESCR_f.L0 = 1;
+        uart->uart_regs->ESCR_f.L1 = 0;
+        uart->uart_regs->ESCR_f.L2 = 0;
+        break;
+    case DATA_BITS_6:
+        uart->uart_regs->ESCR_f.L0 = 0;
+        uart->uart_regs->ESCR_f.L1 = 1;
+        uart->uart_regs->ESCR_f.L2 = 0;
+        break;
+    case DATA_BITS_7:
+        uart->uart_regs->ESCR_f.L0 = 1;
+        uart->uart_regs->ESCR_f.L1 = 1;
+        uart->uart_regs->ESCR_f.L2 = 0;
+        break;
+    case DATA_BITS_8:
+        uart->uart_regs->ESCR_f.L0 = 0;
+        uart->uart_regs->ESCR_f.L1 = 0;
+        uart->uart_regs->ESCR_f.L2 = 0;
+        break;
+    case DATA_BITS_9:
+        uart->uart_regs->ESCR_f.L0 = 0;
+        uart->uart_regs->ESCR_f.L1 = 0;
+        uart->uart_regs->ESCR_f.L2 = 1;
+        break;
+    default:
+        return RT_ERROR;
+    }
 
-	/* set parity */
-	switch (cfg->parity)
-	{
-	case PARITY_NONE:
-		uart->uart_regs->ESCR_f.PEN = 0;
-		break;
-	case PARITY_EVEN:
-		uart->uart_regs->ESCR_f.PEN = 1;
-		uart->uart_regs->ESCR_f.P   = 0;
-		break;
-	case PARITY_ODD:
-		uart->uart_regs->ESCR_f.PEN = 1;
-		uart->uart_regs->ESCR_f.P   = 1;
-		break;
-	default:
-		return RT_ERROR;
-	}
+    /* set parity */
+    switch (cfg->parity)
+    {
+    case PARITY_NONE:
+        uart->uart_regs->ESCR_f.PEN = 0;
+        break;
+    case PARITY_EVEN:
+        uart->uart_regs->ESCR_f.PEN = 1;
+        uart->uart_regs->ESCR_f.P   = 0;
+        break;
+    case PARITY_ODD:
+        uart->uart_regs->ESCR_f.PEN = 1;
+        uart->uart_regs->ESCR_f.P   = 1;
+        break;
+    default:
+        return RT_ERROR;
+    }
 
-	/* set bit order */
-	switch (cfg->bit_order)
-	{
-	case BIT_ORDER_LSB:
-		uart->uart_regs->SMR_f.BDS = 0;
-		break;
-	case BIT_ORDER_MSB:
-		uart->uart_regs->SMR_f.BDS = 1;
-		break;
-	default:
-		return RT_ERROR;
-	}
+    /* set bit order */
+    switch (cfg->bit_order)
+    {
+    case BIT_ORDER_LSB:
+        uart->uart_regs->SMR_f.BDS = 0;
+        break;
+    case BIT_ORDER_MSB:
+        uart->uart_regs->SMR_f.BDS = 1;
+        break;
+    default:
+        return RT_ERROR;
+    }
 
-	/* set NRZ mode */
-	switch (cfg->invert)
-	{
-	case NRZ_NORMAL:
-		uart->uart_regs->ESCR_f.INV = 0;
-		break;
-	case NRZ_INVERTED:
-		uart->uart_regs->ESCR_f.INV = 1;
-		break;
-	default:
-		return RT_ERROR;
-	}
-	
-	/* configure fifo */
-	/* Disable the Data Lost detection */
-	uart->uart_regs->FCR1_f.FLSTE = 0;
-	/* Enable the received FIFO idle detection */
-	uart->uart_regs->FCR1_f.FRIE  = 1;
-	/* Requests for the transmit FIFO data */
-	uart->uart_regs->FCR1_f.FDRQ  = 1;
-	/* Disable the transmit FIFO interrupt */
-	uart->uart_regs->FCR1_f.FTIE  = 0;
-	/* Transmit FIFO:FIFO1; Received FIFO:FIFO2 */
-	uart->uart_regs->FCR1_f.FSEL  = 0;
+    /* set NRZ mode */
+    switch (cfg->invert)
+    {
+    case NRZ_NORMAL:
+        uart->uart_regs->ESCR_f.INV = 0;
+        break;
+    case NRZ_INVERTED:
+        uart->uart_regs->ESCR_f.INV = 1;
+        break;
+    default:
+        return RT_ERROR;
+    }
 
-	/* Transfer data count */
-	uart->uart_regs->FBYTE1 = 0;
-	/* Set the data count to generate a received interrupt */
-	uart->uart_regs->FBYTE2 = uart->fifo_size;
+    /* configure fifo */
+    /* Disable the Data Lost detection */
+    uart->uart_regs->FCR1_f.FLSTE = 0;
+    /* Enable the received FIFO idle detection */
+    uart->uart_regs->FCR1_f.FRIE  = 1;
+    /* Requests for the transmit FIFO data */
+    uart->uart_regs->FCR1_f.FDRQ  = 1;
+    /* Disable the transmit FIFO interrupt */
+    uart->uart_regs->FCR1_f.FTIE  = 0;
+    /* Transmit FIFO:FIFO1; Received FIFO:FIFO2 */
+    uart->uart_regs->FCR1_f.FSEL  = 0;
 
-	/* FIFO pointer Not reloaded */
-	uart->uart_regs->FCR0_f.FLD  = 0;
-	/* FIFO pointer Not saved */
-	uart->uart_regs->FCR0_f.FSET = 0;
-	/* FIFO2 is reset */
-	uart->uart_regs->FCR0_f.FCL2 = 1;
-	/* FIFO1 is reset */
-	uart->uart_regs->FCR0_f.FCL1 = 1;
-	/* Enables the FIFO2 operation */
-	uart->uart_regs->FCR0_f.FE2  = 1;
-	/* Enables the FIFO1 operation */
-	uart->uart_regs->FCR0_f.FE1  = 1;
-	
-    /* enable receive and send */	
-	uart->uart_regs->SCR = SCR_RXE | SCR_TXE | SCR_RIE;
+    /* Transfer data count */
+    uart->uart_regs->FBYTE1 = 0;
+    /* Set the data count to generate a received interrupt */
+    uart->uart_regs->FBYTE2 = uart->fifo_size;
 
-	return RT_EOK;
+    /* FIFO pointer Not reloaded */
+    uart->uart_regs->FCR0_f.FLD  = 0;
+    /* FIFO pointer Not saved */
+    uart->uart_regs->FCR0_f.FSET = 0;
+    /* FIFO2 is reset */
+    uart->uart_regs->FCR0_f.FCL2 = 1;
+    /* FIFO1 is reset */
+    uart->uart_regs->FCR0_f.FCL1 = 1;
+    /* Enables the FIFO2 operation */
+    uart->uart_regs->FCR0_f.FE2  = 1;
+    /* Enables the FIFO1 operation */
+    uart->uart_regs->FCR0_f.FE1  = 1;
+
+    /* enable receive and send */
+    uart->uart_regs->SCR = SCR_RXE | SCR_TXE | SCR_RIE;
+
+    return RT_EOK;
 }
 
 static rt_err_t uart47_control(struct rt_serial_device *serial, int cmd, void *arg)
 {
-	struct uart47_device *uart;
+    struct uart47_device *uart;
 
-	RT_ASSERT(serial != RT_NULL);	
-	uart = (struct uart47_device *)serial->parent.user_data;
-	
-	switch (cmd)
-	{
-	case RT_DEVICE_CTRL_CLR_INT:
-		/* disable rx irq */
-		UART_DISABLE_IRQ(uart->rx_irq);
-		break;
-	case RT_DEVICE_CTRL_SET_INT:
-		/* enable rx irq */
-		UART_ENABLE_IRQ(uart->rx_irq);
-		break;
-	}
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct uart47_device *)serial->parent.user_data;
 
-	return (RT_EOK);	
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        UART_DISABLE_IRQ(uart->rx_irq);
+        break;
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        UART_ENABLE_IRQ(uart->rx_irq);
+        break;
+    }
+
+    return (RT_EOK);
 }
 
 static int uart47_putc(struct rt_serial_device *serial, char c)
 {
-	struct uart47_device *uart;
+    struct uart47_device *uart;
 
-	RT_ASSERT(serial != RT_NULL);
-	
-	uart = (struct uart47_device *)serial->parent.user_data;
+    RT_ASSERT(serial != RT_NULL);
 
-	/* while send fifo is empty */
-	while (!(uart->uart_regs->SSR & SSR_TDRE));
-	/* write to fifo */
-	uart->uart_regs->TDR = c;
+    uart = (struct uart47_device *)serial->parent.user_data;
 
-	return (1);	
+    /* while send fifo is empty */
+    while (!(uart->uart_regs->SSR & SSR_TDRE));
+    /* write to fifo */
+    uart->uart_regs->TDR = c;
+
+    return (1);
 }
 
 static int uart47_getc(struct rt_serial_device *serial)
-{	
-	int ch;
-	struct uart47_device *uart;
+{
+    int ch;
+    struct uart47_device *uart;
 
-	RT_ASSERT(serial != RT_NULL);
-	
-	uart = (struct uart47_device *)serial->parent.user_data;
-    
-	/* receive is disabled */
-	if (!(uart->uart_regs->SCR & SCR_RXE))
-		return (-1);
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = (struct uart47_device *)serial->parent.user_data;
+
+    /* receive is disabled */
+    if (!(uart->uart_regs->SCR & SCR_RXE))
+        return (-1);
     /* receive fifo is not full */
-	if ((uart->uart_regs->SSR & SSR_RDRF) == 0)
-		return (-1);
-	/* read char */
-	ch = uart->uart_regs->RDR & 0xff;
- 	 
-	return (ch);	
+    if ((uart->uart_regs->SSR & SSR_RDRF) == 0)
+        return (-1);
+    /* read char */
+    ch = uart->uart_regs->RDR & 0xff;
+
+    return (ch);
 }
 
 static struct rt_uart_ops uart47_ops =
 {
-	uart47_configure,
-	uart47_control,
-	uart47_putc,
-	uart47_getc,
+    uart47_configure,
+    uart47_control,
+    uart47_putc,
+    uart47_getc,
 };
 
 void rt_hw_serial_init(void)
 {
-	struct serial_configure config;
+    struct serial_configure config;
 
-	uart_pin_setup();
+    uart_pin_setup();
 
 #if (defined(RT_USING_UART0_0) || defined(RT_USING_UART0_1))
-	config.baud_rate = BAUD_RATE_115200;
-	config.bit_order = BIT_ORDER_LSB;
-	config.data_bits = DATA_BITS_8;
-	config.parity    = PARITY_NONE;
-	config.stop_bits = STOP_BITS_1;
-	config.invert    = NRZ_NORMAL;
-	config.bufsz     = RT_SERIAL_RB_BUFSZ;
+    config.baud_rate = BAUD_RATE_115200;
+    config.bit_order = BIT_ORDER_LSB;
+    config.data_bits = DATA_BITS_8;
+    config.parity    = PARITY_NONE;
+    config.stop_bits = STOP_BITS_1;
+    config.invert    = NRZ_NORMAL;
+    config.bufsz     = RT_SERIAL_RB_BUFSZ;
 
-	serial0.ops    = &uart03_ops;
-	serial0.config = config;
+    serial0.ops    = &uart03_ops;
+    serial0.config = config;
 
-	/* register UART0 device */
-	rt_hw_serial_register(&serial0, "uart0",
-		RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
-		&uart0);
+    /* register UART0 device */
+    rt_hw_serial_register(&serial0, "uart0",
+        RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+        &uart0);
 #endif
 
 #if (defined(RT_USING_UART1_0) || defined(RT_USING_UART1_1))
-	config.baud_rate = BAUD_RATE_115200;
-	config.bit_order = BIT_ORDER_LSB;
-	config.data_bits = DATA_BITS_8;
-	config.parity    = PARITY_NONE;
-	config.stop_bits = STOP_BITS_1;
-	config.invert    = NRZ_NORMAL;
-	config.bufsz     = RT_SERIAL_RB_BUFSZ;
+    config.baud_rate = BAUD_RATE_115200;
+    config.bit_order = BIT_ORDER_LSB;
+    config.data_bits = DATA_BITS_8;
+    config.parity    = PARITY_NONE;
+    config.stop_bits = STOP_BITS_1;
+    config.invert    = NRZ_NORMAL;
+    config.bufsz     = RT_SERIAL_RB_BUFSZ;
 
-	serial1.ops    = &uart03_ops;
-	serial1.config = config;
+    serial1.ops    = &uart03_ops;
+    serial1.config = config;
 
-	/* register UART1 device */
-	rt_hw_serial_register(&serial1,
-		"uart1",
-		RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
-		&uart1);
+    /* register UART1 device */
+    rt_hw_serial_register(&serial1,
+        "uart1",
+        RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+        &uart1);
 #endif
 
 #if (defined(RT_USING_UART2_0) || defined(RT_USING_UART2_1) || defined(RT_USING_UART2_2))
-	config.baud_rate = BAUD_RATE_115200;
-	config.bit_order = BIT_ORDER_LSB;
-	config.data_bits = DATA_BITS_8;
-	config.parity    = PARITY_NONE;
-	config.stop_bits = STOP_BITS_1;
-	config.invert    = NRZ_NORMAL;
-	config.bufsz     = RT_SERIAL_RB_BUFSZ;
+    config.baud_rate = BAUD_RATE_115200;
+    config.bit_order = BIT_ORDER_LSB;
+    config.data_bits = DATA_BITS_8;
+    config.parity    = PARITY_NONE;
+    config.stop_bits = STOP_BITS_1;
+    config.invert    = NRZ_NORMAL;
+    config.bufsz     = RT_SERIAL_RB_BUFSZ;
 
-	serial2.ops    = &uart03_ops;
-	serial2.config = config;
+    serial2.ops    = &uart03_ops;
+    serial2.config = config;
 
-	/* register UART2 device */
-	rt_hw_serial_register(&serial2,
-		"uart2",
-		RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
-		&uart2);
+    /* register UART2 device */
+    rt_hw_serial_register(&serial2,
+        "uart2",
+        RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+        &uart2);
 #endif
 
 #if (defined(RT_USING_UART3_0) || defined(RT_USING_UART3_1) || defined(RT_USING_UART3_2))
-	config.baud_rate = BAUD_RATE_115200;
-	config.bit_order = BIT_ORDER_LSB;
-	config.data_bits = DATA_BITS_8;
-	config.parity    = PARITY_NONE;
-	config.stop_bits = STOP_BITS_1;
-	config.invert    = NRZ_NORMAL;
-	config.bufsz     = RT_SERIAL_RB_BUFSZ;
+    config.baud_rate = BAUD_RATE_115200;
+    config.bit_order = BIT_ORDER_LSB;
+    config.data_bits = DATA_BITS_8;
+    config.parity    = PARITY_NONE;
+    config.stop_bits = STOP_BITS_1;
+    config.invert    = NRZ_NORMAL;
+    config.bufsz     = RT_SERIAL_RB_BUFSZ;
 
-	serial3.ops    = &uart03_ops;
-	serial3.config = config;
+    serial3.ops    = &uart03_ops;
+    serial3.config = config;
 
-	/* register UART3 device */
-	rt_hw_serial_register(&serial3,
-		"uart3",
-		RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
-		&uart3);
+    /* register UART3 device */
+    rt_hw_serial_register(&serial3,
+        "uart3",
+        RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+        &uart3);
 #endif
 
 #if (defined(RT_USING_UART4_0) || defined(RT_USING_UART4_1) || defined(RT_USING_UART4_2))
-	config.baud_rate = BAUD_RATE_115200;
-	config.bit_order = BIT_ORDER_LSB;
-	config.data_bits = DATA_BITS_8;
-	config.parity    = PARITY_NONE;
-	config.stop_bits = STOP_BITS_1;
-	config.invert    = NRZ_NORMAL;
-	config.bufsz     = RT_SERIAL_RB_BUFSZ;
+    config.baud_rate = BAUD_RATE_115200;
+    config.bit_order = BIT_ORDER_LSB;
+    config.data_bits = DATA_BITS_8;
+    config.parity    = PARITY_NONE;
+    config.stop_bits = STOP_BITS_1;
+    config.invert    = NRZ_NORMAL;
+    config.bufsz     = RT_SERIAL_RB_BUFSZ;
 
-	serial4.ops    = &uart47_ops;
-	serial4.config = config;
+    serial4.ops    = &uart47_ops;
+    serial4.config = config;
 
-	/* register UART4 device */
-	rt_hw_serial_register(&serial4,
-		"uart4",
-		RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
-		&uart4);
+    /* register UART4 device */
+    rt_hw_serial_register(&serial4,
+        "uart4",
+        RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+        &uart4);
 #endif
 
 #if (defined(RT_USING_UART5_0) || defined(RT_USING_UART5_1) || defined(RT_USING_UART5_2))
-	config.baud_rate = BAUD_RATE_115200;
-	config.bit_order = BIT_ORDER_LSB;
-	config.data_bits = DATA_BITS_8;
-	config.parity    = PARITY_NONE;
-	config.stop_bits = STOP_BITS_1;
-	config.invert    = NRZ_NORMAL;
-	config.bufsz     = RT_SERIAL_RB_BUFSZ;
+    config.baud_rate = BAUD_RATE_115200;
+    config.bit_order = BIT_ORDER_LSB;
+    config.data_bits = DATA_BITS_8;
+    config.parity    = PARITY_NONE;
+    config.stop_bits = STOP_BITS_1;
+    config.invert    = NRZ_NORMAL;
+    config.bufsz     = RT_SERIAL_RB_BUFSZ;
 
-	serial5.ops    = &uart47_ops;
-	serial5.config = config;
+    serial5.ops    = &uart47_ops;
+    serial5.config = config;
 
-	/* register UART5 device */
-	rt_hw_serial_register(&serial5,
-		"uart5",
-		RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
-		&uart5);
+    /* register UART5 device */
+    rt_hw_serial_register(&serial5,
+        "uart5",
+        RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+        &uart5);
 #endif
 
 #if (defined(RT_USING_UART6_0) || defined(RT_USING_UART6_1))
-	config.baud_rate = BAUD_RATE_115200;
-	config.bit_order = BIT_ORDER_LSB;
-	config.data_bits = DATA_BITS_8;
-	config.parity    = PARITY_NONE;
-	config.stop_bits = STOP_BITS_1;
-	config.invert    = NRZ_NORMAL;
-	config.bufsz     = RT_SERIAL_RB_BUFSZ;
+    config.baud_rate = BAUD_RATE_115200;
+    config.bit_order = BIT_ORDER_LSB;
+    config.data_bits = DATA_BITS_8;
+    config.parity    = PARITY_NONE;
+    config.stop_bits = STOP_BITS_1;
+    config.invert    = NRZ_NORMAL;
+    config.bufsz     = RT_SERIAL_RB_BUFSZ;
 
-	serial6.ops    = &uart47_ops;
-	serial6.config = config;
+    serial6.ops    = &uart47_ops;
+    serial6.config = config;
 
-	/* register UART6 device */
-	rt_hw_serial_register(&serial6,
-		"uart6",
-		RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
-		&uart6);
+    /* register UART6 device */
+    rt_hw_serial_register(&serial6,
+        "uart6",
+        RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+        &uart6);
 #endif
 
 #if (defined(RT_USING_UART7_0) || defined(RT_USING_UART7_1))
-	config.baud_rate = BAUD_RATE_115200;
-	config.bit_order = BIT_ORDER_LSB;
-	config.data_bits = DATA_BITS_8;
-	config.parity    = PARITY_NONE;
-	config.stop_bits = STOP_BITS_1;
-	config.invert    = NRZ_NORMAL;
-	config.bufsz     = RT_SERIAL_RB_BUFSZ;
+    config.baud_rate = BAUD_RATE_115200;
+    config.bit_order = BIT_ORDER_LSB;
+    config.data_bits = DATA_BITS_8;
+    config.parity    = PARITY_NONE;
+    config.stop_bits = STOP_BITS_1;
+    config.invert    = NRZ_NORMAL;
+    config.bufsz     = RT_SERIAL_RB_BUFSZ;
 
-	serial7.ops    = &uart47_ops;
-	serial7.config = config;
+    serial7.ops    = &uart47_ops;
+    serial7.config = config;
 
-	/* register UART7 device */
-	rt_hw_serial_register(&serial7,
-		"uart7",
-		RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
-		&uart7);
+    /* register UART7 device */
+    rt_hw_serial_register(&serial7,
+        "uart7",
+        RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+        &uart7);
 #endif
 }
diff --git a/bsp/mb9bf506r/drivers/fm3_uart.h b/bsp/mb9bf506r/drivers/fm3_uart.h
index f8698dbe17..824592c850 100644
--- a/bsp/mb9bf506r/drivers/fm3_uart.h
+++ b/bsp/mb9bf506r/drivers/fm3_uart.h
@@ -1,11 +1,7 @@
 /*
- * File      : fm3_uart.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -55,7 +51,7 @@
 #define ESCR_DATABITS_7  0x03U
 #define ESCR_DATABITS_9  0x04U
 
-#define FIFO_SIZE		16
+#define FIFO_SIZE       16
 
 /*
  *  Enable/DISABLE Interrupt Controller
@@ -66,19 +62,19 @@
 
 struct uart03_device
 {
-	FM3_MFS03_UART_TypeDef *uart_regs;
-	/* irq number */
-	IRQn_Type rx_irq;
-	IRQn_Type tx_irq;
+    FM3_MFS03_UART_TypeDef *uart_regs;
+    /* irq number */
+    IRQn_Type rx_irq;
+    IRQn_Type tx_irq;
 };
 
 struct uart47_device
 {
-	FM3_MFS47_UART_TypeDef *uart_regs;
-	/* irq number */
-	IRQn_Type rx_irq;
-	IRQn_Type tx_irq;
-	rt_uint8_t fifo_size;	
+    FM3_MFS47_UART_TypeDef *uart_regs;
+    /* irq number */
+    IRQn_Type rx_irq;
+    IRQn_Type tx_irq;
+    rt_uint8_t fifo_size;
 };
 
 void rt_hw_serial_init(void);
diff --git a/bsp/mb9bf506r/drivers/led.c b/bsp/mb9bf506r/drivers/led.c
index a1ab6a0592..3f6a11fcfe 100644
--- a/bsp/mb9bf506r/drivers/led.c
+++ b/bsp/mb9bf506r/drivers/led.c
@@ -1,17 +1,13 @@
 /*
- * File      : led.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2011, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2011-03-03     lgnq
  */
-     
+
 #include 
 #include 
 
@@ -20,8 +16,8 @@
 
 void rt_hw_led_on(rt_uint8_t num)
 {
-	RT_ASSERT(num < LEDS_MAX_NUMBER);
-    
+    RT_ASSERT(num < LEDS_MAX_NUMBER);
+
     switch (num)
     {
         case 1:
@@ -31,16 +27,16 @@ void rt_hw_led_on(rt_uint8_t num)
             USER_LED_PDOR &= ~USER_LED2;
         break;
         case 3:
-            USER_LED_PDOR &= ~USER_LED3;        
+            USER_LED_PDOR &= ~USER_LED3;
         break;
         default:
         break;
-    }	
+    }
 }
 
 void rt_hw_led_off(rt_uint8_t num)
 {
-	RT_ASSERT(num < LEDS_MAX_NUMBER);
+    RT_ASSERT(num < LEDS_MAX_NUMBER);
 
     switch (num)
     {
@@ -51,17 +47,17 @@ void rt_hw_led_off(rt_uint8_t num)
             USER_LED_PDOR |= USER_LED2;
         break;
         case 3:
-            USER_LED_PDOR |= USER_LED3;        
+            USER_LED_PDOR |= USER_LED3;
         break;
         default:
         break;
-    }	
+    }
 }
 
 void rt_hw_led_toggle(rt_uint8_t num)
 {
-	RT_ASSERT(num < LEDS_MAX_NUMBER);
-    
+    RT_ASSERT(num < LEDS_MAX_NUMBER);
+
     switch (num)
     {
         case 1:
@@ -80,11 +76,11 @@ void rt_hw_led_toggle(rt_uint8_t num)
             if (USER_LED_PDOR&USER_LED3)
                 USER_LED_PDOR &= ~USER_LED3;
             else
-                USER_LED_PDOR |= USER_LED3;    
+                USER_LED_PDOR |= USER_LED3;
         break;
         default:
         break;
-    }	    
+    }
 }
 
 void led_init(void)
@@ -102,7 +98,7 @@ void led_init(void)
 
 void pwm_update(rt_uint16_t value)
 {
-    FM3_BT2_PWM->PDUT  = value;			
+    FM3_BT2_PWM->PDUT  = value;
 }
 
 static void led1_thread_entry(void *parameter)
@@ -130,11 +126,11 @@ void rt_hw_led_init(void)
     led_init();
 
     led1_thread = rt_thread_create("led1", led1_thread_entry, RT_NULL, 384, 29, 5);
-    if (led1_thread != RT_NULL) 
+    if (led1_thread != RT_NULL)
         rt_thread_startup(led1_thread);
-    
+
     led2_thread = rt_thread_create("led2", led2_thread_entry, RT_NULL, 384, 30, 5);
-    if (led2_thread != RT_NULL) 
+    if (led2_thread != RT_NULL)
         rt_thread_startup(led2_thread);
 }
 
diff --git a/bsp/mb9bf506r/drivers/led.h b/bsp/mb9bf506r/drivers/led.h
index 5db0980520..bcbfaf9b62 100644
--- a/bsp/mb9bf506r/drivers/led.h
+++ b/bsp/mb9bf506r/drivers/led.h
@@ -1,38 +1,34 @@
 /*
- * File      : led.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2011, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2011-03-03     lgnq
  */
- 
+
 #ifndef __LED_H__
 #define __LED_H__
 
 #include "mb9bf506r.h"
 
-#define LEDS_MAX_NUMBER 		4
+#define LEDS_MAX_NUMBER         4
 
 /* LED */
 #define USER_LED1      (1UL<<0x9)
 #define USER_LED2      (1UL<<0xa)
 #define USER_LED3      (1UL<<0xb)
 
-#define USER_LED_MASK    	(USER_LED1 | USER_LED2 | USER_LED3)
-#define USER_LED_PFR    		FM3_GPIO->PFR1
-#define USER_LED_PCR    		FM3_GPIO->PCR1
-#define USER_LED_PDOR   		FM3_GPIO->PDOR1
-#define USER_LED_DDR    		FM3_GPIO->DDR1
+#define USER_LED_MASK       (USER_LED1 | USER_LED2 | USER_LED3)
+#define USER_LED_PFR            FM3_GPIO->PFR1
+#define USER_LED_PCR            FM3_GPIO->PCR1
+#define USER_LED_PDOR           FM3_GPIO->PDOR1
+#define USER_LED_DDR            FM3_GPIO->DDR1
 
-#define RT_DEVICE_CTRL_LED_ON			0
-#define RT_DEVICE_CTRL_LED_OFF			1
-#define RT_DEVICE_CTRL_LED_TOGGLE	 	2
+#define RT_DEVICE_CTRL_LED_ON           0
+#define RT_DEVICE_CTRL_LED_OFF          1
+#define RT_DEVICE_CTRL_LED_TOGGLE       2
 
 void rt_hw_led_init(void);
 void rt_hw_led_on(rt_uint8_t num);
diff --git a/bsp/mb9bf506r/drivers/nand.c b/bsp/mb9bf506r/drivers/nand.c
index 22427a3d5f..fcd8cf42d4 100644
--- a/bsp/mb9bf506r/drivers/nand.c
+++ b/bsp/mb9bf506r/drivers/nand.c
@@ -1,11 +1,7 @@
 /*
- * File      : nand.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -16,17 +12,17 @@
 #include "mb9bf506r.h"
 
 /*
- * NandFlash driver for SamSung K9F5608 
+ * NandFlash driver for SamSung K9F5608
  * 32M x 8bit
  */
-#define PAGE_SIZE		512
-#define PAGE_PER_BLOCK	32
-#define BLOCK_NUM		2048
+#define PAGE_SIZE       512
+#define PAGE_PER_BLOCK  32
+#define BLOCK_NUM       2048
 
 /* device driver debug trace */
 /* #define NAND_DEBUG */
 #ifdef NAND_DEBUG
-#define trace_log 		rt_kprintf
+#define trace_log       rt_kprintf
 #else
 #define trace_log(...)
 #endif
@@ -38,14 +34,14 @@
  */
 struct rt_device_nand
 {
-	struct rt_device parent; 	/* which is inherited from rt_device */
+    struct rt_device parent;    /* which is inherited from rt_device */
 
-	rt_uint16_t block_num;		/* total block number in device 	*/
-	rt_uint16_t page_per_block;	/* pages in one block 				*/
-	rt_uint16_t page_size;		/* page size 						*/
+    rt_uint16_t block_num;      /* total block number in device     */
+    rt_uint16_t page_per_block; /* pages in one block               */
+    rt_uint16_t page_size;      /* page size                        */
 
-	/* this buffer which used as to save data before erase block 	*/
-	rt_uint8_t  block_buffer[PAGE_SIZE * PAGE_PER_BLOCK];
+    /* this buffer which used as to save data before erase block    */
+    rt_uint8_t  block_buffer[PAGE_SIZE * PAGE_PER_BLOCK];
 };
 static struct rt_device_nand _nand;
 
@@ -60,8 +56,8 @@ static struct rt_device_nand _nand;
 #define NF_OE_H()       {IO_NF_PDOR |= NF_EN;}
 #define NF_OE_L()       {IO_NF_PDOR &= ~NF_EN;}
 
-#define NF_DATA_OUT()	{IO_NF_PDOR &= ~NF_DATA_DIR;}
-#define NF_DATA_IN()	{IO_NF_PDOR |= NF_DATA_DIR;}
+#define NF_DATA_OUT()   {IO_NF_PDOR &= ~NF_DATA_DIR;}
+#define NF_DATA_IN()    {IO_NF_PDOR |= NF_DATA_DIR;}
 
 static unsigned char NF_ReadStatus(void);
 static void Wait(unsigned int cnt);
@@ -107,11 +103,11 @@ static unsigned char NF_ReadStatus(void)
  */
 static void NF_Init(void)
 {
-    FM3_GPIO->PFR5 |= (0x7ff);		/*  D0-D5, CS7, ALE, CLE, WEX, REX */
-    FM3_GPIO->PFR3 |= (0x3);		/* D6-D7 */
-    FM3_GPIO->EPFR10 |= (1<<13		/* CS enable */
-                       |1<<6		/* ALE, CLE, WEX, REX enable */
-                       |1<<0);		/* D0-D7 enable */
+    FM3_GPIO->PFR5 |= (0x7ff);      /*  D0-D5, CS7, ALE, CLE, WEX, REX */
+    FM3_GPIO->PFR3 |= (0x3);        /* D6-D7 */
+    FM3_GPIO->EPFR10 |= (1<<13      /* CS enable */
+                       |1<<6        /* ALE, CLE, WEX, REX enable */
+                       |1<<0);      /* D0-D7 enable */
     FM3_EXBUS->AREA7 = 0x001f00e0;  /* Select CS7 area, 32Mbyte size */
     FM3_EXBUS->MODE7 |= (1<<4);     /* Nand Flash mode turn on, set 8 bit width */
 
@@ -125,9 +121,9 @@ static void NF_Init(void)
 
 static void NF_UnInit(void)
 {
-    FM3_GPIO->PFR5 &= ~(0x7ff);		/*  disable D0-D5, CS7, ALE, CLE, WEX, REX */
-    FM3_GPIO->PFR3 &= ~(0x3);		/* disable D6-D7 */
-    FM3_GPIO->EPFR10 &= ~(1<<13		/* disable CS enable */
+    FM3_GPIO->PFR5 &= ~(0x7ff);     /*  disable D0-D5, CS7, ALE, CLE, WEX, REX */
+    FM3_GPIO->PFR3 &= ~(0x3);       /* disable D6-D7 */
+    FM3_GPIO->EPFR10 &= ~(1<<13     /* disable CS enable */
                        |1<<6        /* disable ALE, CLE, WEX, REX enable */
                        |1<<0);      /* disable D0-D7 enable */
     FM3_EXBUS->MODE7 &= ~(1<<4);
@@ -144,52 +140,52 @@ static void NF_UnInit(void)
  *   Return: 0: Flash Operation OK
  *           1: Flash Operation NG
  */
-int NF_ReadPage(unsigned int block, unsigned int page, unsigned char *buffer, 
+int NF_ReadPage(unsigned int block, unsigned int page, unsigned char *buffer,
                 unsigned char *oob)
 {
     unsigned int blockPage,i;
 
     NF_Init();
-    blockPage=(block<<5)+page;					    /* 1 block=32 page */
+    blockPage=(block<<5)+page;                      /* 1 block=32 page */
     NF_OE_L();
     NF_DATA_OUT();
-	if (buffer != RT_NULL)
-	{
-		volatile unsigned char ch;
+    if (buffer != RT_NULL)
+    {
+        volatile unsigned char ch;
 
-		NF_CMD(NAND_CMD_READ0);						/* send read data */
+        NF_CMD(NAND_CMD_READ0);                     /* send read data */
 
-		NF_ADDR(0);
-		NF_ADDR(blockPage & 0xff);
-		NF_ADDR((blockPage>>8) & 0xff);             /* send 3 byte address */
-		NF_CLR_ALE();
-		NF_DATA_IN();
+        NF_ADDR(0);
+        NF_ADDR(blockPage & 0xff);
+        NF_ADDR((blockPage>>8) & 0xff);             /* send 3 byte address */
+        NF_CLR_ALE();
+        NF_DATA_IN();
 
-		Wait(500);
+        Wait(500);
 
-		for(i=0;i<512;i++)							/* read 512 bytes data */
-			buffer[i] = NF_RDDATA();
-		for(i=0;i<16;i++)							/* read 16 bytes oob */
-			if (oob != RT_NULL)
-				oob[i] = NF_RDDATA();
-			else
-				ch = NF_RDDATA();
-	}
-	else
-	{
-		NF_CMD(NAND_CMD_READOOB);					/* send read data */
+        for(i=0;i<512;i++)                          /* read 512 bytes data */
+            buffer[i] = NF_RDDATA();
+        for(i=0;i<16;i++)                           /* read 16 bytes oob */
+            if (oob != RT_NULL)
+                oob[i] = NF_RDDATA();
+            else
+                ch = NF_RDDATA();
+    }
+    else
+    {
+        NF_CMD(NAND_CMD_READOOB);                   /* send read data */
 
-		NF_ADDR(0);
-		NF_ADDR(blockPage & 0xff);
-		NF_ADDR((blockPage>>8) & 0xff);				/* send 3 byte address */
-		NF_CLR_ALE();
-		NF_DATA_IN();
+        NF_ADDR(0);
+        NF_ADDR(blockPage & 0xff);
+        NF_ADDR((blockPage>>8) & 0xff);             /* send 3 byte address */
+        NF_CLR_ALE();
+        NF_DATA_IN();
 
-		Wait(500);
+        Wait(500);
 
-		for (i=0; i<16; i++)						/* read 16 bytes oob */
-		   oob[i] = NF_RDDATA();
-	}
+        for (i=0; i<16; i++)                        /* read 16 bytes oob */
+           oob[i] = NF_RDDATA();
+    }
 
     NF_OE_H();
     NF_UnInit();
@@ -206,7 +202,7 @@ int NF_EraseBlock(unsigned int block)
 {
     rt_uint32_t blockPage;
 
-	trace_log("Erase block %d: ", block);
+    trace_log("Erase block %d: ", block);
 
     NF_Init();
     blockPage = (block << 5);
@@ -219,19 +215,19 @@ int NF_EraseBlock(unsigned int block)
 
     if(NF_ReadStatus())
     {
-		NF_Reset();
-		NF_OE_H();
-		NF_UnInit();
-		trace_log("Failed\n");
-		rt_kprintf("erase block failed\n");
+        NF_Reset();
+        NF_OE_H();
+        NF_UnInit();
+        trace_log("Failed\n");
+        rt_kprintf("erase block failed\n");
 
-		return FLASH_NG;
+        return FLASH_NG;
     }
 
     NF_OE_H();
     NF_UnInit();
 
-	trace_log("OK\n");
+    trace_log("OK\n");
 
     return FLASH_OK;
 }
@@ -261,24 +257,24 @@ int NF_WritePage(unsigned block, unsigned page, const rt_uint8_t *buffer)
     NF_ADDR((blockPage>>8) & 0xff);
     NF_CLR_ALE();
 
-    for(i=0;i<512;i++) NF_WRDATA(buffer[i]);	/* write data */
-    for(i=0;i<16;i++) NF_WRDATA(se[i]);			/* dummy write */
+    for(i=0;i<512;i++) NF_WRDATA(buffer[i]);    /* write data */
+    for(i=0;i<16;i++) NF_WRDATA(se[i]);         /* dummy write */
 
-    NF_CMD(NAND_CMD_PAGEPROG);					/* start programming */
+    NF_CMD(NAND_CMD_PAGEPROG);                  /* start programming */
 
     if(NF_ReadStatus())
     {
-		NF_Reset();
-		NF_OE_H();
-		NF_UnInit();
-		
-		trace_log("write failed\n");
-		return FLASH_NG;
+        NF_Reset();
+        NF_OE_H();
+        NF_UnInit();
+
+        trace_log("write failed\n");
+        return FLASH_NG;
     }
 
     /* verify the write data */
     NF_DATA_OUT();
-    NF_CMD(NAND_CMD_READ0);						/* send read command */
+    NF_CMD(NAND_CMD_READ0);                     /* send read command */
     NF_ADDR(0);
     NF_ADDR(blockPage & 0xff);
     NF_ADDR((blockPage>>8) & 0xff);
@@ -288,11 +284,11 @@ int NF_WritePage(unsigned block, unsigned page, const rt_uint8_t *buffer)
     Wait(500);
     for(i=0; i<512; i++)
     {
-        data=NF_RDDATA();						/* verify 1-512 byte */
+        data=NF_RDDATA();                       /* verify 1-512 byte */
         if(data != buffer[i])
         {
-			trace_log("block %d, page %d\n", block , page);
-			trace_log("write data failed[%d]: %02x %02x\n", i, data, buffer[i]);
+            trace_log("block %d, page %d\n", block , page);
+            trace_log("write data failed[%d]: %02x %02x\n", i, data, buffer[i]);
 
             NF_Reset();
             NF_OE_H();
@@ -303,11 +299,11 @@ int NF_WritePage(unsigned block, unsigned page, const rt_uint8_t *buffer)
 
     for(i=0; i<16; i++)
     {
-       data=NF_RDDATA();						/* verify 16 byte dummy data */
+       data=NF_RDDATA();                        /* verify 16 byte dummy data */
         if(data != se[i])
         {
-			trace_log("block %d, page %d\n", block , page);
-			trace_log("write oob failed[%d]: %02x %02x\n", i, data, se[i]);
+            trace_log("block %d, page %d\n", block , page);
+            trace_log("write oob failed[%d]: %02x %02x\n", i, data, se[i]);
             NF_Reset();
             NF_OE_H();
             NF_UnInit();
@@ -327,7 +323,7 @@ int NF_WritePage(unsigned block, unsigned page, const rt_uint8_t *buffer)
  */
 void NF_ReadID(unsigned char *id)
 {
-	unsigned char maker_code;
+    unsigned char maker_code;
     NF_Init();
     NF_OE_L();
     NF_DATA_OUT();
@@ -337,7 +333,7 @@ void NF_ReadID(unsigned char *id)
     Wait(10);
     NF_DATA_IN();
     maker_code = NF_RDDATA();
-	maker_code = maker_code;
+    maker_code = maker_code;
     *id = NF_RDDATA();
     NF_OE_H();
     NF_UnInit();
@@ -345,58 +341,58 @@ void NF_ReadID(unsigned char *id)
 
 static rt_err_t rt_nand_init (rt_device_t dev)
 {
-	/* empty implementation */
-	return RT_EOK;
+    /* empty implementation */
+    return RT_EOK;
 }
 
 static rt_err_t rt_nand_open(rt_device_t dev, rt_uint16_t oflag)
 {
-	/* empty implementation */
-	return RT_EOK;
+    /* empty implementation */
+    return RT_EOK;
 }
 
 static rt_err_t rt_nand_close(rt_device_t dev)
 {
-	/* empty implementation */
-	return RT_EOK;
+    /* empty implementation */
+    return RT_EOK;
 }
 
 /* nand device read */
-static rt_size_t rt_nand_read (rt_device_t dev, rt_off_t pos, void* buffer, 
+static rt_size_t rt_nand_read (rt_device_t dev, rt_off_t pos, void* buffer,
                                rt_size_t size)
 {
-	rt_ubase_t block;			/* block of position */
-	rt_ubase_t page, index;		/* page in block of position */
-	rt_uint8_t *page_ptr, oob[16];
-	struct rt_device_nand *nand;
+    rt_ubase_t block;           /* block of position */
+    rt_ubase_t page, index;     /* page in block of position */
+    rt_uint8_t *page_ptr, oob[16];
+    struct rt_device_nand *nand;
 
-	/* get nand device */
-	nand = (struct rt_device_nand*) dev;
-	RT_ASSERT(nand != RT_NULL);
+    /* get nand device */
+    nand = (struct rt_device_nand*) dev;
+    RT_ASSERT(nand != RT_NULL);
 
-	/* get block and page */
-	block = pos / nand->page_per_block;
-	page  = pos % nand->page_per_block;
+    /* get block and page */
+    block = pos / nand->page_per_block;
+    page  = pos % nand->page_per_block;
 
-	trace_log("nand read: position %d, block %d, page %d, size %d\n", 
-		pos, block, page, size);
+    trace_log("nand read: position %d, block %d, page %d, size %d\n",
+        pos, block, page, size);
 
-	/* set page buffer pointer */
-	page_ptr = (rt_uint8_t*) buffer;
-	for (index = 0; index < size; index ++)
-	{
-		NF_ReadPage(block, page + index, page_ptr, oob);
-		page_ptr += nand->page_size;
-		
-		if (page + index > nand->page_per_block)
-		{
-			block += 1;
-			page = 0;
-		}
-	}
+    /* set page buffer pointer */
+    page_ptr = (rt_uint8_t*) buffer;
+    for (index = 0; index < size; index ++)
+    {
+        NF_ReadPage(block, page + index, page_ptr, oob);
+        page_ptr += nand->page_size;
 
-	/* return read size (count of block) */
-	return size;
+        if (page + index > nand->page_per_block)
+        {
+            block += 1;
+            page = 0;
+        }
+    }
+
+    /* return read size (count of block) */
+    return size;
 }
 
 /*
@@ -407,190 +403,190 @@ static rt_size_t rt_nand_read (rt_device_t dev, rt_off_t pos, void* buffer,
  * @param buffer the data buffer to be written
  * @param pages the number of pages to be written
  */
-static int rt_nand_eraseblock_writepage(struct rt_device_nand* nand, 
-                                        rt_ubase_t block, rt_ubase_t page, 
-	const rt_uint8_t *buffer, rt_ubase_t pages)
+static int rt_nand_eraseblock_writepage(struct rt_device_nand* nand,
+                                        rt_ubase_t block, rt_ubase_t page,
+    const rt_uint8_t *buffer, rt_ubase_t pages)
 {
-	rt_ubase_t index;
-	rt_uint32_t page_status;
-	rt_uint8_t *page_ptr, oob[16];
+    rt_ubase_t index;
+    rt_uint32_t page_status;
+    rt_uint8_t *page_ptr, oob[16];
 
-	/* set page status */
-	page_status = 0;
+    /* set page status */
+    page_status = 0;
 
-	/* read each page in block */
-	page_ptr = nand->block_buffer;
-	for (index = 0; index < nand->page_per_block; index ++)
-	{
-		NF_ReadPage(block, index, page_ptr, oob);
-		if (!oob[0])
-			page_status |= (1 << index);
-		page_ptr += nand->page_size;
-	}
+    /* read each page in block */
+    page_ptr = nand->block_buffer;
+    for (index = 0; index < nand->page_per_block; index ++)
+    {
+        NF_ReadPage(block, index, page_ptr, oob);
+        if (!oob[0])
+            page_status |= (1 << index);
+        page_ptr += nand->page_size;
+    }
 
-	/* erase block */
-	NF_EraseBlock(block);
+    /* erase block */
+    NF_EraseBlock(block);
 
-	page_ptr = &(nand->block_buffer[page * nand->page_size]);
-	/* merge buffer to page buffer */
-	for (index = 0; index < pages; index ++)
-	{
-		rt_memcpy(page_ptr, buffer, nand->page_size);
+    page_ptr = &(nand->block_buffer[page * nand->page_size]);
+    /* merge buffer to page buffer */
+    for (index = 0; index < pages; index ++)
+    {
+        rt_memcpy(page_ptr, buffer, nand->page_size);
 
-		/* set page status */
-		page_status |= (1 << (page + index));
+        /* set page status */
+        page_status |= (1 << (page + index));
 
-		/* move to next page */
-		page_ptr += nand->page_size;
-		buffer += nand->page_size;
-	}
+        /* move to next page */
+        page_ptr += nand->page_size;
+        buffer += nand->page_size;
+    }
 
-	/* write to flash */
-	page_ptr = nand->block_buffer;
-	for (index = 0; index < nand->page_per_block; index ++)
-	{
-		if (page_status & (1 << index))
-			NF_WritePage(block, index, page_ptr);
+    /* write to flash */
+    page_ptr = nand->block_buffer;
+    for (index = 0; index < nand->page_per_block; index ++)
+    {
+        if (page_status & (1 << index))
+            NF_WritePage(block, index, page_ptr);
 
-		/* move to next page */
-		page_ptr += nand->page_size;
-	}
+        /* move to next page */
+        page_ptr += nand->page_size;
+    }
 
-	return 0;
+    return 0;
 }
 
 /* nand device write */
-static rt_size_t rt_nand_write (rt_device_t dev, rt_off_t pos, 
+static rt_size_t rt_nand_write (rt_device_t dev, rt_off_t pos,
                                 const void* buffer, rt_size_t size)
 {
-	rt_ubase_t block, page;
-	rt_uint8_t oob[16];
-	struct rt_device_nand *nand;
+    rt_ubase_t block, page;
+    rt_uint8_t oob[16];
+    struct rt_device_nand *nand;
 
-	nand = (struct rt_device_nand*) dev;
-	RT_ASSERT(nand != RT_NULL);
+    nand = (struct rt_device_nand*) dev;
+    RT_ASSERT(nand != RT_NULL);
 
-	/* get block and page */
-	block = pos / nand->page_per_block;
-	page  = pos % nand->page_per_block;
+    /* get block and page */
+    block = pos / nand->page_per_block;
+    page  = pos % nand->page_per_block;
 
-	trace_log("nand write: position %d, block %d, page %d, size %d\n", 
-		pos, block, page, size);
+    trace_log("nand write: position %d, block %d, page %d, size %d\n",
+        pos, block, page, size);
 
-	if (size == 1)
-	{
-		/* write one page */
+    if (size == 1)
+    {
+        /* write one page */
 
-		/* read oob to get page status */
-		NF_ReadPage(block, page, RT_NULL, oob);
-		if (oob[0])
-			NF_WritePage(block, page, buffer);
-		else
-			/* erase block and then write page */
-			rt_nand_eraseblock_writepage(nand, block, page, buffer, 1);
-	}
-	else if (size > 1)
-	{
-		rt_ubase_t index;
-		rt_ubase_t need_erase_block;
-		const rt_uint8_t *page_ptr;
-		rt_ubase_t chunk_pages, pages;
+        /* read oob to get page status */
+        NF_ReadPage(block, page, RT_NULL, oob);
+        if (oob[0])
+            NF_WritePage(block, page, buffer);
+        else
+            /* erase block and then write page */
+            rt_nand_eraseblock_writepage(nand, block, page, buffer, 1);
+    }
+    else if (size > 1)
+    {
+        rt_ubase_t index;
+        rt_ubase_t need_erase_block;
+        const rt_uint8_t *page_ptr;
+        rt_ubase_t chunk_pages, pages;
 
-		pages = size;
-		page_ptr = (const rt_uint8_t*) buffer;
-		do
-		{
-			need_erase_block = 0;
-			/* calculate pages in current chunk */
-			if (pages > nand->page_per_block - page)
-				chunk_pages = nand->page_per_block - page;
-			else 
-				chunk_pages = pages;
+        pages = size;
+        page_ptr = (const rt_uint8_t*) buffer;
+        do
+        {
+            need_erase_block = 0;
+            /* calculate pages in current chunk */
+            if (pages > nand->page_per_block - page)
+                chunk_pages = nand->page_per_block - page;
+            else
+                chunk_pages = pages;
 
-			/* get page status in current block */
-			for (index = page; index < page + chunk_pages; index ++)
-			{
-				NF_ReadPage(block, index, RT_NULL, oob);
-				if (!oob[0])
-				{
-					/* this page has data, need erase this block firstly */
-					need_erase_block = 1;
-					break;
-				}
-			}
+            /* get page status in current block */
+            for (index = page; index < page + chunk_pages; index ++)
+            {
+                NF_ReadPage(block, index, RT_NULL, oob);
+                if (!oob[0])
+                {
+                    /* this page has data, need erase this block firstly */
+                    need_erase_block = 1;
+                    break;
+                }
+            }
 
-			if (need_erase_block)
-			{
-				/* erase block and then write it */
-				rt_nand_eraseblock_writepage(nand, block, page, page_ptr, chunk_pages);
-				page_ptr += chunk_pages * nand->page_size;
-			}
-			else
-			{
-				/* write pages directly */
-				for (index = page; index < page + chunk_pages; index ++)
-				{
-					NF_WritePage(block, index, page_ptr);
-					page_ptr += nand->page_size;
-				}
-			}
+            if (need_erase_block)
+            {
+                /* erase block and then write it */
+                rt_nand_eraseblock_writepage(nand, block, page, page_ptr, chunk_pages);
+                page_ptr += chunk_pages * nand->page_size;
+            }
+            else
+            {
+                /* write pages directly */
+                for (index = page; index < page + chunk_pages; index ++)
+                {
+                    NF_WritePage(block, index, page_ptr);
+                    page_ptr += nand->page_size;
+                }
+            }
 
-			pages -= chunk_pages;
-			page = 0; block ++; /* move to next block */
-		}
-		while (pages);
-	}
+            pages -= chunk_pages;
+            page = 0; block ++; /* move to next block */
+        }
+        while (pages);
+    }
 
-	return size;
+    return size;
 }
 
 static rt_err_t rt_nand_control (rt_device_t dev, int cmd, void *args)
 {
-	struct rt_device_nand *nand;
+    struct rt_device_nand *nand;
 
-	nand = (struct rt_device_nand*) dev;
+    nand = (struct rt_device_nand*) dev;
     RT_ASSERT(dev != RT_NULL);
 
     switch (cmd)
-	{
-	case RT_DEVICE_CTRL_BLK_GETGEOME:
-		{
-			struct rt_device_blk_geometry *geometry;
+    {
+    case RT_DEVICE_CTRL_BLK_GETGEOME:
+        {
+            struct rt_device_blk_geometry *geometry;
 
-			geometry = (struct rt_device_blk_geometry *)args;
-			if (geometry == RT_NULL) return -RT_ERROR;
+            geometry = (struct rt_device_blk_geometry *)args;
+            if (geometry == RT_NULL) return -RT_ERROR;
 
-			geometry->bytes_per_sector = nand->page_size;
-			geometry->block_size = nand->page_size * nand->page_per_block;
-			geometry->sector_count = nand->block_num * nand->page_per_block;
-		}
-		break;
-	}
+            geometry->bytes_per_sector = nand->page_size;
+            geometry->block_size = nand->page_size * nand->page_per_block;
+            geometry->sector_count = nand->block_num * nand->page_per_block;
+        }
+        break;
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 void rt_hw_nand_init(void)
 {
-	/* initialize nand flash structure */
-	_nand.block_num = BLOCK_NUM;
-	_nand.page_per_block = PAGE_PER_BLOCK;
-	_nand.page_size = PAGE_SIZE;
+    /* initialize nand flash structure */
+    _nand.block_num = BLOCK_NUM;
+    _nand.page_per_block = PAGE_PER_BLOCK;
+    _nand.page_size = PAGE_SIZE;
 
-	rt_memset(_nand.block_buffer, 0, sizeof(_nand.block_buffer));
+    rt_memset(_nand.block_buffer, 0, sizeof(_nand.block_buffer));
 
-	_nand.parent.type 		= RT_Device_Class_MTD;
-	_nand.parent.rx_indicate = RT_NULL;
-	_nand.parent.tx_complete = RT_NULL;
-	_nand.parent.init 		= rt_nand_init;
-	_nand.parent.open		= rt_nand_open;
-	_nand.parent.close		= rt_nand_close;
-	_nand.parent.read 		= rt_nand_read;
-	_nand.parent.write 		= rt_nand_write;
-	_nand.parent.control 	= rt_nand_control;
+    _nand.parent.type       = RT_Device_Class_MTD;
+    _nand.parent.rx_indicate = RT_NULL;
+    _nand.parent.tx_complete = RT_NULL;
+    _nand.parent.init       = rt_nand_init;
+    _nand.parent.open       = rt_nand_open;
+    _nand.parent.close      = rt_nand_close;
+    _nand.parent.read       = rt_nand_read;
+    _nand.parent.write      = rt_nand_write;
+    _nand.parent.control    = rt_nand_control;
 
-	/* register a MTD device */
-	rt_device_register(&(_nand.parent), "nand", RT_DEVICE_FLAG_RDWR);
+    /* register a MTD device */
+    rt_device_register(&(_nand.parent), "nand", RT_DEVICE_FLAG_RDWR);
 }
 
 #ifdef NAND_DEBUG
@@ -600,68 +596,68 @@ unsigned char nand_oob[16];
 
 void dump_mem(unsigned char* buffer, int length)
 {
-	int i;
+    int i;
 
-	if (length > 64) length = 64;	
-	for (i = 0; i < length; i ++)
-	{
-		rt_kprintf("%02x ", *buffer++);
-		if (((i+1) % 16) == 0)
-		rt_kprintf("\n");
-	}
-	rt_kprintf("\n");
+    if (length > 64) length = 64;
+    for (i = 0; i < length; i ++)
+    {
+        rt_kprintf("%02x ", *buffer++);
+        if (((i+1) % 16) == 0)
+        rt_kprintf("\n");
+    }
+    rt_kprintf("\n");
 }
 
 void nand_read(int block, int page)
 {
-	rt_kprintf("read block %d, page %d\n", block, page);
+    rt_kprintf("read block %d, page %d\n", block, page);
 
-	NF_ReadPage(block, page, nand_buffer, nand_oob);
-	rt_kprintf("page data:\n");
-	dump_mem(nand_buffer, 512);
-	rt_kprintf("oob data:\n");
-	dump_mem(nand_oob, 16);
+    NF_ReadPage(block, page, nand_buffer, nand_oob);
+    rt_kprintf("page data:\n");
+    dump_mem(nand_buffer, 512);
+    rt_kprintf("oob data:\n");
+    dump_mem(nand_oob, 16);
 }
 FINSH_FUNCTION_EXPORT_ALIAS(nand_read, read_page, read page[block/page]);
 
 void nand_write(int block, int page)
 {
-	int i;
-	for (i = 0; i < 512; i ++)
-		nand_buffer[i] = i;
+    int i;
+    for (i = 0; i < 512; i ++)
+        nand_buffer[i] = i;
 
-	NF_WritePage(block, page, nand_buffer);
+    NF_WritePage(block, page, nand_buffer);
 }
 FINSH_FUNCTION_EXPORT_ALIAS(nand_write, write_page, write page[block/page]);
 
 void nand_erase(int block)
 {
-	NF_EraseBlock(block);
+    NF_EraseBlock(block);
 }
 FINSH_FUNCTION_EXPORT_ALIAS(nand_erase, erase_block, erase block[block]);
 
 void nand_readoob(int block, int page)
 {
-	rt_kprintf("read oob on block %d, page %d\n", block, page);
+    rt_kprintf("read oob on block %d, page %d\n", block, page);
 
-	NF_ReadPage(block, page, RT_NULL, (unsigned char*)nand_oob);
-	rt_kprintf("oob data:\n");
-	dump_mem(nand_oob, 16);
+    NF_ReadPage(block, page, RT_NULL, (unsigned char*)nand_oob);
+    rt_kprintf("oob data:\n");
+    dump_mem(nand_oob, 16);
 }
 FINSH_FUNCTION_EXPORT_ALIAS(nand_readoob, readoob, read oob[block/page]);
 
 void nand_erase_chip()
 {
-	int i;
-	unsigned char id;
-	
-	NF_ReadID(&id);
-	rt_kprintf("id: %02x\n", id);
+    int i;
+    unsigned char id;
 
-	for (i = 0; i < 2048; i ++)
-	{
-		NF_EraseBlock(i);
-	}
+    NF_ReadID(&id);
+    rt_kprintf("id: %02x\n", id);
+
+    for (i = 0; i < 2048; i ++)
+    {
+        NF_EraseBlock(i);
+    }
 }
 FINSH_FUNCTION_EXPORT_ALIAS(nand_erase_chip, erase_chip, erase whole chip);
 #endif
diff --git a/bsp/mb9bf506r/drivers/nand.h b/bsp/mb9bf506r/drivers/nand.h
index ffb4bae2c3..d00909ddce 100644
--- a/bsp/mb9bf506r/drivers/nand.h
+++ b/bsp/mb9bf506r/drivers/nand.h
@@ -1,11 +1,7 @@
 /*
- * File      : nand.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -33,7 +29,7 @@
 #define NF_ALE_OFFSET        0x00003000
 #define NF_ADDR_OFFSET       0x00002000
 #define NF_CMD_OFFSET        0x00001000
-#define NF_DATA_OFFSET       0x00000000   
+#define NF_DATA_OFFSET       0x00000000
 
 /* NAND command */
 #define NAND_CMD_READ0     0x00
@@ -47,7 +43,7 @@
 #define NAND_CMD_READID1   0x91
 #define NAND_CMD_ERASE2    0xd0
 #define NAND_CMD_RESET     0xff
-  
+
 #define FLASH_OK           0
 #define FLASH_NG           1
 
diff --git a/bsp/mb9bf568r/applications/application.c b/bsp/mb9bf568r/applications/application.c
index 462207672e..e5d2b55950 100644
--- a/bsp/mb9bf568r/applications/application.c
+++ b/bsp/mb9bf568r/applications/application.c
@@ -1,11 +1,7 @@
 /*
- * File      : application.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -28,7 +24,7 @@ void rt_init_thread_entry(void *parameter)
 #endif
 
 
-		//finsh_system_init();
+    //finsh_system_init();
     finsh_set_device(RT_CONSOLE_DEVICE_NAME);
 
 
@@ -36,10 +32,6 @@ void rt_init_thread_entry(void *parameter)
     {
         extern void rt_led_hw_init(void);
         rt_led_hw_init();
-    }
-		{
-        extern int demo_init(void);
-        demo_init();
     }
 
 }
diff --git a/bsp/mb9bf568r/applications/demo.c b/bsp/mb9bf568r/applications/demo.c
deleted file mode 100644
index d43ce2f5a4..0000000000
--- a/bsp/mb9bf568r/applications/demo.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
-	demoʾ̴̬߳
- */
-#include 
-#include "board.h"
-
-#ifdef RT_USING_FINSH
-#include 
-#include 
-#endif
-
-
-static	rt_thread_t tid1 = RT_NULL;
-static	rt_thread_t tid2 = RT_NULL;
-
-
-static void thread1_entry(void* parameter)
-{
-    rt_uint32_t count = 0;
-
-    rt_kprintf("thread1 dynamicly created ok\n");
-    while (1)
-    {
-        rt_kprintf("thread1 count: %d\n",count++);
-        rt_thread_delay(RT_TICK_PER_SECOND); 
-    }
-}
-						
-static void thread2_entry(void* parameter)
-{		
-		rt_uint32_t count = 0;
-    rt_kprintf("thread2 dynamicly created ok\n");
-	  
-		while(1)
-    {
-				if(count == 3)
-					break;
-        rt_kprintf("thread2 count: %d\n",count++);
-        rt_thread_delay(RT_TICK_PER_SECOND);   
-			
-    }
-    rt_thread_delay(RT_TICK_PER_SECOND * 4);  
-    
-    rt_thread_delete(tid1);							
-    rt_kprintf("thread1 deleted ok\n");
-}
-
-
-int demo_init(void)
-{
-				
-    tid1 = rt_thread_create("thread1",
-				thread1_entry,
-				RT_NULL,
-				512, 6, 10);
-	
-    if (tid1 != RT_NULL)
-        rt_thread_startup(tid1);        
-
-    tid2 = rt_thread_create("thread2",
-        thread2_entry, 
-				RT_NULL,
-        512, 6, 10);
-		
-    if (tid2 != RT_NULL)
-        rt_thread_startup(tid2);
-
-    return 0;
-}
diff --git a/bsp/mb9bf568r/applications/startup.c b/bsp/mb9bf568r/applications/startup.c
index 1ad95dbce8..263bd20a28 100644
--- a/bsp/mb9bf568r/applications/startup.c
+++ b/bsp/mb9bf568r/applications/startup.c
@@ -1,11 +1,7 @@
 /*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -43,7 +39,7 @@ void rtthread_startup(void)
 
     /* show version */
     rt_show_version();
-	
+
     /* init timer system */
     rt_system_timer_init();
 
diff --git a/bsp/mb9bf568r/drivers/board.c b/bsp/mb9bf568r/drivers/board.c
index 2dbc219f28..bd44ad80b1 100644
--- a/bsp/mb9bf568r/drivers/board.c
+++ b/bsp/mb9bf568r/drivers/board.c
@@ -1,11 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2011 RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -64,7 +60,7 @@ rt_uint32_t rt_hw_tick_get_microsecond(void)
     rt_tick_t tick;
     rt_uint32_t value;
 
-#define TICK_US	(1000000/RT_TICK_PER_SECOND)
+#define TICK_US (1000000/RT_TICK_PER_SECOND)
 
     tick = rt_tick_get();
     value = tick * TICK_US + (SysTick->LOAD - SysTick->VAL) * TICK_US / SysTick->LOAD;
diff --git a/bsp/mb9bf568r/drivers/board.h b/bsp/mb9bf568r/drivers/board.h
index 1b784810bf..ed258f82a0 100644
--- a/bsp/mb9bf568r/drivers/board.h
+++ b/bsp/mb9bf568r/drivers/board.h
@@ -1,11 +1,7 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/mb9bf568r/drivers/led.c b/bsp/mb9bf568r/drivers/led.c
index 20e015cdc9..db80b56fd0 100644
--- a/bsp/mb9bf568r/drivers/led.c
+++ b/bsp/mb9bf568r/drivers/led.c
@@ -1,3 +1,11 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
 #include 
 #include "board.h"
 
@@ -28,9 +36,9 @@ static rt_err_t rt_led_init (rt_device_t dev)
     /* led0-1-2 : P27-P38-PE0 */
     FM4_GPIO->PFR2 &= ~((1<<7) );  /* set P27 fuction is GPIO. */
     FM4_GPIO->DDR2 |=  (1<<7) ;    /* set P27 output. */
-		FM4_GPIO->PFR3 &= ~((1<<8) );  /* set P38 fuction is GPIO. */
+        FM4_GPIO->PFR3 &= ~((1<<8) );  /* set P38 fuction is GPIO. */
     FM4_GPIO->DDR3 |=  (1<<8) ;    /* set P38 output. */
-		FM4_GPIO->PFRE &= ~((1<<0) );  /* set PE0 fuction is GPIO. */
+        FM4_GPIO->PFRE &= ~((1<<0) );  /* set PE0 fuction is GPIO. */
     FM4_GPIO->DDRE |=  (1<<0) ;    /* set PE0 output. */
 
     /* LED0 */
@@ -127,16 +135,16 @@ static rt_err_t rt_led_control (rt_device_t dev, int cmd, void *args)
 
 void rt_led_hw_init(void)
 {
-    fm4_led.parent.type 		= RT_Device_Class_Char;
+    fm4_led.parent.type         = RT_Device_Class_Char;
     fm4_led.parent.rx_indicate  = RT_NULL;
     fm4_led.parent.tx_complete  = RT_NULL;
-    fm4_led.parent.init 		= rt_led_init;
-    fm4_led.parent.open		    = rt_led_open;
-    fm4_led.parent.close		= rt_led_close;
+    fm4_led.parent.init         = rt_led_init;
+    fm4_led.parent.open         = rt_led_open;
+    fm4_led.parent.close        = rt_led_close;
     fm4_led.parent.read         = rt_led_read;
-    fm4_led.parent.write 		= rt_led_write;
-    fm4_led.parent.control 	    = rt_led_control;
-    fm4_led.parent.user_data	= RT_NULL;
+    fm4_led.parent.write        = rt_led_write;
+    fm4_led.parent.control      = rt_led_control;
+    fm4_led.parent.user_data    = RT_NULL;
 
     /* register a character device */
     rt_device_register(&fm4_led.parent, "led", RT_DEVICE_FLAG_RDWR);
diff --git a/bsp/mb9bf568r/drivers/mcu.h b/bsp/mb9bf568r/drivers/mcu.h
index 6ee4e1fe7e..5717ff37cc 100644
--- a/bsp/mb9bf568r/drivers/mcu.h
+++ b/bsp/mb9bf568r/drivers/mcu.h
@@ -41,8 +41,8 @@
  **
  ******************************************************************************/
 
-#define  PDL_INT_TYPE_C		1
-#define  PDL_INT_TYPE_A		2
+#define  PDL_INT_TYPE_C     1
+#define  PDL_INT_TYPE_A     2
 
 #define PDL_MCU_INT_TYPE  PDL_INT_TYPE_A
 
@@ -50,7 +50,7 @@
  ******************************************************************************
  ** \brief MCU header file include
  **
- ******************************************************************************/ 
+ ******************************************************************************/
 #ifndef _MB9B560R_H_
   #include "mb9b560r.h"
 #endif
@@ -59,7 +59,7 @@
  ******************************************************************************
  ** \brief MCU system start-up header file include
  **
- ******************************************************************************/ 
+ ******************************************************************************/
 #ifndef _SYSTEM_MB9ABXXX_H_
   #include "system_mb9bf56xr.h"
 #endif
diff --git a/bsp/mb9bf568r/drivers/serial.c b/bsp/mb9bf568r/drivers/serial.c
index b4d42d510b..6c3a132216 100644
--- a/bsp/mb9bf568r/drivers/serial.c
+++ b/bsp/mb9bf568r/drivers/serial.c
@@ -1,11 +1,7 @@
 /*
- * File      : serial.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -258,16 +254,16 @@ rt_err_t rt_hw_serial_register(rt_device_t device, const char* name,
 {
     RT_ASSERT(device != RT_NULL);
 
-    device->type 		= RT_Device_Class_Char;
+    device->type        = RT_Device_Class_Char;
     device->rx_indicate = RT_NULL;
     device->tx_complete = RT_NULL;
-    device->init 		= rt_serial_init;
-    device->open		= rt_serial_open;
-    device->close		= rt_serial_close;
-    device->read 		= rt_serial_read;
-    device->write 		= rt_serial_write;
-    device->control 	= rt_serial_control;
-    device->user_data	= serial;
+    device->init        = rt_serial_init;
+    device->open        = rt_serial_open;
+    device->close       = rt_serial_close;
+    device->read        = rt_serial_read;
+    device->write       = rt_serial_write;
+    device->control     = rt_serial_control;
+    device->user_data   = serial;
 
     /* register a character device */
     return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
@@ -303,7 +299,7 @@ void rt_hw_serial_isr(rt_device_t device)
 
 #ifdef RT_USING_UART0
 /* UART0 device driver structure */
-#define UART0	FM4_MFS0
+#define UART0   FM4_MFS0
 struct serial_int_rx uart0_int_rx;
 struct serial_device uart0 =
 {
@@ -316,8 +312,8 @@ struct serial_device uart0 =
 struct rt_device uart0_device;
 
 void MFS0_RX_IRQHandler(void)
-{	 
-		/* enter interrupt */
+{
+        /* enter interrupt */
     rt_interrupt_enter();
     rt_hw_serial_isr(&uart0_device);
     /* leave interrupt */
@@ -330,28 +326,28 @@ void MFS0_RX_IRQHandler(void)
 
 void rt_hw_serial_init(void)
 {
-		uint32_t APB2_clock = (SystemCoreClock >> (APBC2_PSR_Val & 0x03));
-	
+        uint32_t APB2_clock = (SystemCoreClock >> (APBC2_PSR_Val & 0x03));
+
 #ifdef RT_USING_UART0
      // Initialize ports for MFS0
-		FM4_GPIO->PFR2   = 0x06u;   // P21>SIN0_0, P22>SOT0_0
-		FM4_GPIO->EPFR07 &= 0xFFFFFF0Ful;
-		FM4_GPIO->EPFR07 |= 0x00000040ul;
-		
-		// Initialize MFS to UART asynchronous mode
-		
-		uart0.uart_device->SMR = SMR_MD_UART | SMR_SOE;;
+        FM4_GPIO->PFR2   = 0x06u;   // P21>SIN0_0, P22>SOT0_0
+        FM4_GPIO->EPFR07 &= 0xFFFFFF0Ful;
+        FM4_GPIO->EPFR07 |= 0x00000040ul;
+
+        // Initialize MFS to UART asynchronous mode
+
+        uart0.uart_device->SMR = SMR_MD_UART | SMR_SOE;;
     uart0.uart_device->BGR = (APB2_clock + (BPS/2))/BPS - 1; /* round */
     uart0.uart_device->ESCR = ESCR_DATABITS_8;
     uart0.uart_device->SCR = SCR_RXE | SCR_TXE | SCR_RIE;
-		
+
     /* register UART0 device */
     rt_hw_serial_register(&uart0_device,
                           "uart0",
                           RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
                           &uart0);
-													
-		
+
+
 #endif /**< #ifdef RT_USING_UART0 */
 
 }
diff --git a/bsp/mb9bf568r/drivers/serial.h b/bsp/mb9bf568r/drivers/serial.h
index b057a811dd..776b2a3877 100644
--- a/bsp/mb9bf568r/drivers/serial.h
+++ b/bsp/mb9bf568r/drivers/serial.h
@@ -1,16 +1,12 @@
 /*
- * File      : serial.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2006-03-13     Bernard      first version
- * 2011-05-15     lgnq         modified according bernard's implementaion.      	  	
+ * 2011-05-15     lgnq         modified according bernard's implementaion.
  */
 
 #ifndef __RT_HW_SERIAL_H__
@@ -57,21 +53,21 @@
 #define ESCR_DATABITS_7  0x03U
 #define ESCR_DATABITS_9  0x04U
 
-#define BPS					115200	/* serial baudrate */
+#define BPS                 115200  /* serial baudrate */
 
-#define UART_RX_BUFFER_SIZE		128
-#define UART_TX_BUFFER_SIZE		128
+#define UART_RX_BUFFER_SIZE     128
+#define UART_TX_BUFFER_SIZE     128
 
 struct serial_int_rx
 {
-	rt_uint8_t  rx_buffer[UART_RX_BUFFER_SIZE];
-	rt_uint32_t read_index, save_index;
+    rt_uint8_t  rx_buffer[UART_RX_BUFFER_SIZE];
+    rt_uint32_t read_index, save_index;
 };
 
 struct serial_int_tx
 {
-	rt_uint8_t  tx_buffer[UART_TX_BUFFER_SIZE];
-	rt_uint32_t write_index, save_index;
+    rt_uint8_t  tx_buffer[UART_TX_BUFFER_SIZE];
+    rt_uint32_t write_index, save_index;
 };
 
 /*
@@ -83,15 +79,15 @@ struct serial_int_tx
 
 struct serial_device
 {
-	FM4_MFS_TypeDef* uart_device;
-	/* irq number */
-	IRQn_Type rx_irq;
-	IRQn_Type tx_irq;
+    FM4_MFS_TypeDef* uart_device;
+    /* irq number */
+    IRQn_Type rx_irq;
+    IRQn_Type tx_irq;
 
-	/* rx structure */
-	struct serial_int_rx* int_rx;
-	/* tx structure */
-	struct serial_int_tx* int_tx;
+    /* rx structure */
+    struct serial_int_rx* int_rx;
+    /* tx structure */
+    struct serial_int_tx* int_tx;
 };
 
 void rt_hw_serial_isr(rt_device_t device);
diff --git a/bsp/mb9bf568r/rtconfig.h b/bsp/mb9bf568r/rtconfig.h
index 1982028ce7..8191fc8e65 100644
--- a/bsp/mb9bf568r/rtconfig.h
+++ b/bsp/mb9bf568r/rtconfig.h
@@ -3,16 +3,16 @@
 #define __RTTHREAD_CFG_H__
 
 /* RT_NAME_MAX*/
-#define RT_NAME_MAX				        8
+#define RT_NAME_MAX                     8
 
 /* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE			        4
+#define RT_ALIGN_SIZE                   4
 
 /* PRIORITY_MAX */
-#define RT_THREAD_PRIORITY_MAX	        64
+#define RT_THREAD_PRIORITY_MAX          64
 
 /* Tick per Second */
-#define RT_TICK_PER_SECOND		        100
+#define RT_TICK_PER_SECOND              100
 
 /* SECTION: RT_DEBUG */
 /* Thread Debug */
@@ -60,9 +60,9 @@
 /* #define RT_TINY_SIZE */
 #define RT_USING_CONSOLE
 /* the buffer size of console */
-#define RT_CONSOLEBUF_SIZE	128
+#define RT_CONSOLEBUF_SIZE  128
 // 
-#define RT_CONSOLE_DEVICE_NAME	        "uart0"
+#define RT_CONSOLE_DEVICE_NAME          "uart0"
 
 /* SECTION: finsh, a C-Express shell */
 /* Using FinSH as Shell*/
diff --git a/bsp/mb9bf618s/applications/application.c b/bsp/mb9bf618s/applications/application.c
index 56187b68c2..5e7c265450 100644
--- a/bsp/mb9bf618s/applications/application.c
+++ b/bsp/mb9bf618s/applications/application.c
@@ -1,11 +1,7 @@
 /*
- * File      : application.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/mb9bf618s/applications/startup.c b/bsp/mb9bf618s/applications/startup.c
index ad46ce7e39..22d38bcf95 100644
--- a/bsp/mb9bf618s/applications/startup.c
+++ b/bsp/mb9bf618s/applications/startup.c
@@ -1,11 +1,7 @@
 /*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -43,7 +39,7 @@ void rtthread_startup(void)
 
     /* show version */
     rt_show_version();
-	
+
     /* init timer system */
     rt_system_timer_init();
 
diff --git a/bsp/mb9bf618s/drivers/board.c b/bsp/mb9bf618s/drivers/board.c
index 12345bbea5..8490e7a060 100644
--- a/bsp/mb9bf618s/drivers/board.c
+++ b/bsp/mb9bf618s/drivers/board.c
@@ -1,11 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2011 RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -64,7 +60,7 @@ rt_uint32_t rt_hw_tick_get_microsecond(void)
     rt_tick_t tick;
     rt_uint32_t value;
 
-#define TICK_US	(1000000/RT_TICK_PER_SECOND)
+#define TICK_US (1000000/RT_TICK_PER_SECOND)
 
     tick = rt_tick_get();
     value = tick * TICK_US + (SysTick->LOAD - SysTick->VAL) * TICK_US / SysTick->LOAD;
diff --git a/bsp/mb9bf618s/drivers/board.h b/bsp/mb9bf618s/drivers/board.h
index 3e5887b8f1..c082b0b54c 100644
--- a/bsp/mb9bf618s/drivers/board.h
+++ b/bsp/mb9bf618s/drivers/board.h
@@ -1,11 +1,7 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/mb9bf618s/drivers/led.c b/bsp/mb9bf618s/drivers/led.c
index e36e70ca46..bfad9947e7 100644
--- a/bsp/mb9bf618s/drivers/led.c
+++ b/bsp/mb9bf618s/drivers/led.c
@@ -1,3 +1,12 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
 #include 
 #include "board.h"
 
@@ -129,16 +138,16 @@ static rt_err_t rt_led_control (rt_device_t dev, int cmd, void *args)
 
 void rt_led_hw_init(void)
 {
-    fm3_led.parent.type 		= RT_Device_Class_Char;
+    fm3_led.parent.type         = RT_Device_Class_Char;
     fm3_led.parent.rx_indicate  = RT_NULL;
     fm3_led.parent.tx_complete  = RT_NULL;
-    fm3_led.parent.init 		= rt_led_init;
-    fm3_led.parent.open		    = rt_led_open;
-    fm3_led.parent.close		= rt_led_close;
+    fm3_led.parent.init         = rt_led_init;
+    fm3_led.parent.open         = rt_led_open;
+    fm3_led.parent.close        = rt_led_close;
     fm3_led.parent.read         = rt_led_read;
-    fm3_led.parent.write 		= rt_led_write;
-    fm3_led.parent.control 	    = rt_led_control;
-    fm3_led.parent.user_data	= RT_NULL;
+    fm3_led.parent.write        = rt_led_write;
+    fm3_led.parent.control      = rt_led_control;
+    fm3_led.parent.user_data    = RT_NULL;
 
     /* register a character device */
     rt_device_register(&fm3_led.parent, "led", RT_DEVICE_FLAG_RDWR);
diff --git a/bsp/mb9bf618s/drivers/serial.c b/bsp/mb9bf618s/drivers/serial.c
index 50e3d37829..79279e79e5 100644
--- a/bsp/mb9bf618s/drivers/serial.c
+++ b/bsp/mb9bf618s/drivers/serial.c
@@ -1,11 +1,7 @@
 /*
- * File      : serial.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -258,16 +254,16 @@ rt_err_t rt_hw_serial_register(rt_device_t device, const char* name,
 {
     RT_ASSERT(device != RT_NULL);
 
-    device->type 		= RT_Device_Class_Char;
+    device->type        = RT_Device_Class_Char;
     device->rx_indicate = RT_NULL;
     device->tx_complete = RT_NULL;
-    device->init 		= rt_serial_init;
-    device->open		= rt_serial_open;
-    device->close		= rt_serial_close;
-    device->read 		= rt_serial_read;
-    device->write 		= rt_serial_write;
-    device->control 	= rt_serial_control;
-    device->user_data	= serial;
+    device->init        = rt_serial_init;
+    device->open        = rt_serial_open;
+    device->close       = rt_serial_close;
+    device->read        = rt_serial_read;
+    device->write       = rt_serial_write;
+    device->control     = rt_serial_control;
+    device->user_data   = serial;
 
     /* register a character device */
     return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
@@ -303,7 +299,7 @@ void rt_hw_serial_isr(rt_device_t device)
 
 #ifdef RT_USING_UART0
 /* UART0 device driver structure */
-#define UART0	FM3_MFS0_UART
+#define UART0   FM3_MFS0_UART
 struct serial_int_rx uart0_int_rx;
 struct serial_device uart0 =
 {
@@ -327,7 +323,7 @@ void MFS0RX_IRQHandler(void)
 
 #ifdef RT_USING_UART2
 /* UART2 device driver structure */
-#define UART2	FM3_MFS2_UART
+#define UART2   FM3_MFS2_UART
 struct serial_int_rx uart2_int_rx;
 struct serial_device uart2 =
 {
@@ -351,7 +347,7 @@ void MFS2RX_IRQHandler(void)
 
 #ifdef RT_USING_UART4
 /* UART4 device driver structure */
-#define UART4	FM3_MFS4_UART
+#define UART4   FM3_MFS4_UART
 struct serial_int_rx uart4_int_rx;
 struct serial_device uart4 =
 {
diff --git a/bsp/mb9bf618s/drivers/serial.h b/bsp/mb9bf618s/drivers/serial.h
index 9a47cba38f..388f9eef86 100644
--- a/bsp/mb9bf618s/drivers/serial.h
+++ b/bsp/mb9bf618s/drivers/serial.h
@@ -1,16 +1,12 @@
 /*
- * File      : serial.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2006-03-13     Bernard      first version
- * 2011-05-15     lgnq         modified according bernard's implementaion.      	  	
+ * 2011-05-15     lgnq         modified according bernard's implementaion.
  */
 
 #ifndef __RT_HW_SERIAL_H__
@@ -57,21 +53,21 @@
 #define ESCR_DATABITS_7  0x03U
 #define ESCR_DATABITS_9  0x04U
 
-#define BPS					115200	/* serial baudrate */
+#define BPS                 115200  /* serial baudrate */
 
-#define UART_RX_BUFFER_SIZE		64
-#define UART_TX_BUFFER_SIZE		64
+#define UART_RX_BUFFER_SIZE     64
+#define UART_TX_BUFFER_SIZE     64
 
 struct serial_int_rx
 {
-	rt_uint8_t  rx_buffer[UART_RX_BUFFER_SIZE];
-	rt_uint32_t read_index, save_index;
+    rt_uint8_t  rx_buffer[UART_RX_BUFFER_SIZE];
+    rt_uint32_t read_index, save_index;
 };
 
 struct serial_int_tx
 {
-	rt_uint8_t  tx_buffer[UART_TX_BUFFER_SIZE];
-	rt_uint32_t write_index, save_index;
+    rt_uint8_t  tx_buffer[UART_TX_BUFFER_SIZE];
+    rt_uint32_t write_index, save_index;
 };
 
 /*
@@ -83,14 +79,14 @@ struct serial_int_tx
 
 struct serial_device
 {
-	FM3_MFS03_UART_TypeDef* uart_device;
-	/* irq number */
-	IRQn_Type rx_irq, tx_irq;
+    FM3_MFS03_UART_TypeDef* uart_device;
+    /* irq number */
+    IRQn_Type rx_irq, tx_irq;
 
-	/* rx structure */
-	struct serial_int_rx* int_rx;
-	/* tx structure */
-	struct serial_int_tx* int_tx;
+    /* rx structure */
+    struct serial_int_rx* int_rx;
+    /* tx structure */
+    struct serial_int_tx* int_tx;
 };
 
 void rt_hw_serial_isr(rt_device_t device);
diff --git a/bsp/mb9bf618s/rtconfig.h b/bsp/mb9bf618s/rtconfig.h
index 1b647a7a30..d887692233 100644
--- a/bsp/mb9bf618s/rtconfig.h
+++ b/bsp/mb9bf618s/rtconfig.h
@@ -3,16 +3,16 @@
 #define __RTTHREAD_CFG_H__
 
 /* RT_NAME_MAX*/
-#define RT_NAME_MAX				        8
+#define RT_NAME_MAX                     8
 
 /* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE			        4
+#define RT_ALIGN_SIZE                   4
 
 /* PRIORITY_MAX */
-#define RT_THREAD_PRIORITY_MAX	        32
+#define RT_THREAD_PRIORITY_MAX          32
 
 /* Tick per Second */
-#define RT_TICK_PER_SECOND		        100
+#define RT_TICK_PER_SECOND              100
 
 /* SECTION: RT_DEBUG */
 /* Thread Debug */
@@ -60,9 +60,9 @@
 /* #define RT_TINY_SIZE */
 #define RT_USING_CONSOLE
 /* the buffer size of console */
-#define RT_CONSOLEBUF_SIZE	128
+#define RT_CONSOLEBUF_SIZE  128
 // 
-#define RT_CONSOLE_DEVICE_NAME	        "uart0"
+#define RT_CONSOLE_DEVICE_NAME          "uart0"
 
 /* SECTION: finsh, a C-Express shell */
 /* Using FinSH as Shell*/
diff --git a/bsp/microblaze/application.c b/bsp/microblaze/application.c
index 4a09f8b951..d2ec464861 100755
--- a/bsp/microblaze/application.c
+++ b/bsp/microblaze/application.c
@@ -1,11 +1,7 @@
 /*
- * File      : app.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -20,7 +16,7 @@
 
 int rt_application_init()
 {
-	return 0;
+    return 0;
 }
 
 /*@}*/
diff --git a/bsp/microblaze/rtconfig.h b/bsp/microblaze/rtconfig.h
index d054c175b9..bdfe09a4f8 100755
--- a/bsp/microblaze/rtconfig.h
+++ b/bsp/microblaze/rtconfig.h
@@ -93,7 +93,6 @@
 /* SECTION: a runtime libc library */
 /* a runtime libc library*/
 /* #define RT_USING_NEWLIB */
-#define RT_USING_MINILIBC
 
 /* SECTION: C++ support */
 /* Using C++ support*/
diff --git a/bsp/microblaze/startup.c b/bsp/microblaze/startup.c
index c900973bb7..e1104a4cd5 100755
--- a/bsp/microblaze/startup.c
+++ b/bsp/microblaze/startup.c
@@ -1,16 +1,12 @@
 /*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2006-08-31     Bernard      first implementation
- * 2011-12-17     nl1031	   for MicroBlaze
+ * 2011-12-17     nl1031       for MicroBlaze
  */
 
 #include 
@@ -47,66 +43,66 @@ extern rt_err_t rt_hw_serial_init(void);
  */
 void rtthread_startup(void)
 {
-	/* init hardware interrupt */
-	rt_hw_interrupt_init();
+    /* init hardware interrupt */
+    rt_hw_interrupt_init();
 
-	/* init board */
-	rt_hw_board_init();
-	
-	rt_show_version();
+    /* init board */
+    rt_hw_board_init();
 
-	/* init timer system */
-	rt_system_timer_init();
+    rt_show_version();
+
+    /* init timer system */
+    rt_system_timer_init();
 
 #ifdef RT_USING_HEAP
 #ifdef __CC_ARM
-	rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x204000);
+    rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x204000);
 #elif __ICCARM__
     rt_system_heap_init(__segment_end("HEAP"), (void*)0x204000);
 #else
-	rt_system_heap_init((void*)&__bss_end, (void*)(&__bss_end+0x4000));
+    rt_system_heap_init((void*)&__bss_end, (void*)(&__bss_end+0x4000));
 
 #endif
 #endif
 
-	/* init scheduler system */
-	rt_system_scheduler_init();
+    /* init scheduler system */
+    rt_system_scheduler_init();
 
 #ifdef RT_USING_HOOK /* if the hook is used */
-	/* set idle thread hook */
-	rt_thread_idle_sethook(rt_hw_led_flash);
+    /* set idle thread hook */
+    rt_thread_idle_sethook(rt_hw_led_flash);
 #endif
 
 #ifdef RT_USING_DEVICE
-	/* init hardware serial device */
-	rt_hw_serial_init();
+    /* init hardware serial device */
+    rt_hw_serial_init();
 #endif
 
-	/* init application */
-	rt_application_init();
+    /* init application */
+    rt_application_init();
 
 #ifdef RT_USING_FINSH
-	/* init finsh */
-	finsh_system_init();
-	finsh_set_device("uart1");
+    /* init finsh */
+    finsh_system_init();
+    finsh_set_device("uart1");
 #endif
 
-	/* init idle thread */
-	rt_thread_idle_init();
+    /* init idle thread */
+    rt_thread_idle_init();
 
-	/* start scheduler */
-	rt_system_scheduler_start();
+    /* start scheduler */
+    rt_system_scheduler_start();
 
-	/* never reach here */
-	return ;
+    /* never reach here */
+    return ;
 }
 
 int main (void)
 {
-	/* invoke rtthread_startup */
-	rtthread_startup();
-	
-	return 0;
+    /* invoke rtthread_startup */
+    rtthread_startup();
+
+    return 0;
 }
 
 /*@}*/
diff --git a/bsp/mini2440/drivers/board.c b/bsp/mini2440/drivers/board.c
index afe190e1cf..4cc2dad409 100644
--- a/bsp/mini2440/drivers/board.c
+++ b/bsp/mini2440/drivers/board.c
@@ -1,18 +1,14 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2006-03-24     Bernard      first implementation
  * 2006-05-05     Bernard      add DATA_COUNT definition
  * 2006-10-05     Alsor.Z       for s3c2410x porting
- * 2007-11-20     Yi.Qiu	     add lcd,touch,console
+ * 2007-11-20     Yi.Qiu         add lcd,touch,console
  */
 
 #include 
@@ -63,7 +59,7 @@ extern void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv);
  */
 static void rt_timer_handler(int vector, void *param)
 {
-	rt_tick_increase();
+    rt_tick_increase();
 }
 
 /**
@@ -71,22 +67,22 @@ static void rt_timer_handler(int vector, void *param)
  */
 static  void rt_hw_timer_init(void)
  {
-	/* timer4, pre = 15+1 */
-	TCFG0 &= 0xffff00ff;
-	TCFG0 |= 15 << 8;
-	/* all are interrupt mode,set Timer 4 MUX 1/4 */
-	TCFG1  &= 0xfff0ffff;
-	TCFG1  |= 0x00010000;
+    /* timer4, pre = 15+1 */
+    TCFG0 &= 0xffff00ff;
+    TCFG0 |= 15 << 8;
+    /* all are interrupt mode,set Timer 4 MUX 1/4 */
+    TCFG1  &= 0xfff0ffff;
+    TCFG1  |= 0x00010000;
 
-	TCNTB4 = (rt_int32_t)(PCLK / (4 *16* RT_TICK_PER_SECOND)) - 1;
-	/* manual update */
-	TCON = TCON & (~(0x0f<<20)) | (0x02<<20);
-	/* install interrupt handler */
-	rt_hw_interrupt_install(INTTIMER4, rt_timer_handler, RT_NULL, "tick");
-	rt_hw_interrupt_umask(INTTIMER4);
+    TCNTB4 = (rt_int32_t)(PCLK / (4 *16* RT_TICK_PER_SECOND)) - 1;
+    /* manual update */
+    TCON = TCON & (~(0x0f<<20)) | (0x02<<20);
+    /* install interrupt handler */
+    rt_hw_interrupt_install(INTTIMER4, rt_timer_handler, RT_NULL, "tick");
+    rt_hw_interrupt_umask(INTTIMER4);
 
     /* start timer4, reload */
-	TCON = TCON & (~(0x0f<<20)) | (0x05<<20);
+    TCON = TCON & (~(0x0f<<20)) | (0x05<<20);
  }
 
 /**
@@ -94,35 +90,41 @@ static  void rt_hw_timer_init(void)
  */
 void rt_hw_board_init(void)
 {
-	rt_hw_cpu_icache_enable();
-	rt_hw_cpu_dcache_enable();
+    rt_hw_cpu_icache_enable();
+    rt_hw_cpu_dcache_enable();
 
-	/* init hardware interrupt */
-	rt_hw_interrupt_init();
+    /* init hardware interrupt */
+    rt_hw_interrupt_init();
 
-	/* initialize the system clock */
-	rt_hw_clock_init();
+    /* initialize the system clock */
+    rt_hw_clock_init();
 
-	/* Get the clock */
-	rt_hw_get_clock();
+    /* Get the clock */
+    rt_hw_get_clock();
 
-	/* initialize led port */
-	rt_hw_led_init();
+    /* initialize led port */
+    rt_hw_led_init();
 
-	/* initialize mmu */
-	rt_hw_mmu_init();
+    /* initialize mmu */
+    rt_hw_mmu_init();
 
-	/* initialize timer4 */
-	rt_hw_timer_init();
+    /* initialize timer4 */
+    rt_hw_timer_init();
 
-	/* initialize system heap */
-	rt_system_heap_init(HEAP_BEGIN, HEAP_END);
+    /* initialize system heap */
+    rt_system_heap_init(HEAP_BEGIN, HEAP_END);
 
-	rt_components_board_init();
+    rt_components_board_init();
 
 #ifdef RT_USING_CONSOLE
-	rt_console_set_device("uart0");
+    rt_console_set_device("uart0");
 #endif
 
 }
+
+void rt_hw_us_delay(rt_uint32_t us)
+{
+
+}
+
 /*@}*/
diff --git a/bsp/mini2440/drivers/board.h b/bsp/mini2440/drivers/board.h
index 434f725216..33be5cf558 100644
--- a/bsp/mini2440/drivers/board.h
+++ b/bsp/mini2440/drivers/board.h
@@ -1,11 +1,7 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/mini2440/drivers/key.c b/bsp/mini2440/drivers/key.c
index d75ffd6d26..459ebf2b07 100644
--- a/bsp/mini2440/drivers/key.c
+++ b/bsp/mini2440/drivers/key.c
@@ -1,79 +1,75 @@
 /*
- * File      : touch.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2010-10-01     Yi.Qiu      first version
  */
 
- /* 
-  * Warning, this keypad driver can only work on QEMU emulator 
+ /*
+  * Warning, this keypad driver can only work on QEMU emulator
   */
-     
+
 #include 
 #include 
 #include 
 
-#define KEY_RX_BUFFER_SIZE		32
+#define KEY_RX_BUFFER_SIZE      32
 
 struct rt_key_device
 {
-	struct rt_device parent;
+    struct rt_device parent;
 
-	rt_uint32_t  rx_buffer[KEY_RX_BUFFER_SIZE];
-	rt_uint32_t read_index, save_index;	
-};	
+    rt_uint32_t  rx_buffer[KEY_RX_BUFFER_SIZE];
+    rt_uint32_t read_index, save_index;
+};
 static struct rt_key_device *key_device = RT_NULL;
 
 /* save a char to serial buffer */
 static void rt_key_savechar(char ch)
 {
-	rt_base_t level;
-	
-	/* disable interrupt */
-	level = rt_hw_interrupt_disable();
+    rt_base_t level;
 
-	key_device->rx_buffer[key_device->save_index] = ch;
-	key_device->save_index ++;
-	if (key_device->save_index >= KEY_RX_BUFFER_SIZE)
-		key_device->save_index = 0;
-	
-	/* if the next position is read index, discard this 'read char' */
-	if (key_device->save_index == key_device->read_index)
-	{
-		key_device->read_index ++;
-		if (key_device->read_index >= KEY_RX_BUFFER_SIZE)
-			key_device->read_index = 0;
-	}
+    /* disable interrupt */
+    level = rt_hw_interrupt_disable();
 
-	/* enable interrupt */
-	rt_hw_interrupt_enable(level);
+    key_device->rx_buffer[key_device->save_index] = ch;
+    key_device->save_index ++;
+    if (key_device->save_index >= KEY_RX_BUFFER_SIZE)
+        key_device->save_index = 0;
+
+    /* if the next position is read index, discard this 'read char' */
+    if (key_device->save_index == key_device->read_index)
+    {
+        key_device->read_index ++;
+        if (key_device->read_index >= KEY_RX_BUFFER_SIZE)
+            key_device->read_index = 0;
+    }
+
+    /* enable interrupt */
+    rt_hw_interrupt_enable(level);
 }
 
 /* ISR for serial interrupt */
 static void rt_hw_key_isr(void)
 {
-	/* save on rx buffer */
-	rt_key_savechar(URXH1 & 0xff);
+    /* save on rx buffer */
+    rt_key_savechar(URXH1 & 0xff);
 
-	/* invoke callback */
-	if (key_device->parent.rx_indicate != RT_NULL)
-	{
-		rt_size_t rx_length;
-		
-		/* get rx length */
-		rx_length = key_device->read_index > key_device->save_index ?
-			KEY_RX_BUFFER_SIZE - key_device->read_index + key_device->save_index :
-			key_device->save_index - key_device->read_index;
+    /* invoke callback */
+    if (key_device->parent.rx_indicate != RT_NULL)
+    {
+        rt_size_t rx_length;
 
-		key_device->parent.rx_indicate(&key_device->parent, rx_length);
-	}	
+        /* get rx length */
+        rx_length = key_device->read_index > key_device->save_index ?
+            KEY_RX_BUFFER_SIZE - key_device->read_index + key_device->save_index :
+            key_device->save_index - key_device->read_index;
+
+        key_device->parent.rx_indicate(&key_device->parent, rx_length);
+    }
 }
 
 /**
@@ -81,14 +77,14 @@ static void rt_hw_key_isr(void)
  */
 static void rt_key_handler(int vector, void *param)
 {
-	INTSUBMSK |= (BIT_SUB_RXD1);
+    INTSUBMSK |= (BIT_SUB_RXD1);
 
-	rt_hw_key_isr();
-	
-	SUBSRCPND |= BIT_SUB_RXD1;
-	
-	/*Unmask sub interrupt (RXD0)*/
-	INTSUBMSK  &=~(BIT_SUB_RXD1);
+    rt_hw_key_isr();
+
+    SUBSRCPND |= BIT_SUB_RXD1;
+
+    /*Unmask sub interrupt (RXD0)*/
+    INTSUBMSK  &=~(BIT_SUB_RXD1);
 }
 
 /**
@@ -96,114 +92,114 @@ static void rt_key_handler(int vector, void *param)
  */
 static void key_init(void)
 {
-	int i = 0;
+    int i = 0;
 
-	GPHCON |= 0xa0;
-	/*PULLUP is enable */
-	GPHUP  |= 0x0c;  
-	
-	/* FIFO enable, Tx/Rx FIFO clear */
-	UFCON1 = 0x0;
-	/* disable the flow control */
-	UMCON1= 0x0;
-	/* Normal,No parity,1 stop,8 bit */
-	ULCON1 = 0x3;
-	/*
-	 * tx=level,rx=edge,disable timeout int.,enable rx error int.,
-	 * normal,interrupt or polling
-	 */
-	UCON1 = 0x245;
+    GPHCON |= 0xa0;
+    /*PULLUP is enable */
+    GPHUP  |= 0x0c;
 
-	//UBRD0 = div;
-	// UBRD0 = 0x500;	/* baudrate = 19200bps */
-	UBRD1 = 0x1a;
+    /* FIFO enable, Tx/Rx FIFO clear */
+    UFCON1 = 0x0;
+    /* disable the flow control */
+    UMCON1= 0x0;
+    /* Normal,No parity,1 stop,8 bit */
+    ULCON1 = 0x3;
+    /*
+     * tx=level,rx=edge,disable timeout int.,enable rx error int.,
+     * normal,interrupt or polling
+     */
+    UCON1 = 0x245;
 
-	UTXH1 = 0x2;
-	URXH1 = 0x1;
+    //UBRD0 = div;
+    // UBRD0 = 0x500;   /* baudrate = 19200bps */
+    UBRD1 = 0x1a;
 
-	/* output PCLK to UART0/1, PWMTIMER */
-	CLKCON |= 0x0D00;
+    UTXH1 = 0x2;
+    URXH1 = 0x1;
 
-	for (i = 0; i < 100; i++);
+    /* output PCLK to UART0/1, PWMTIMER */
+    CLKCON |= 0x0D00;
 
-	/* install key isr */
-	INTSUBMSK &= ~(BIT_SUB_RXD1);
+    for (i = 0; i < 100; i++);
 
-	rt_hw_interrupt_install(INTUART1, rt_key_handler, RT_NULL , "INTUART1");
-	rt_hw_interrupt_umask(INTUART1);
+    /* install key isr */
+    INTSUBMSK &= ~(BIT_SUB_RXD1);
+
+    rt_hw_interrupt_install(INTUART1, rt_key_handler, RT_NULL , "INTUART1");
+    rt_hw_interrupt_umask(INTUART1);
 }
 
 static rt_err_t rt_key_init(rt_device_t dev)
-{		
-	if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
-	{
+{
+    if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
+    {
 
-		if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-		{
-			rt_memset(key_device->rx_buffer, 0, 
-				sizeof(key_device->rx_buffer));
-			key_device->read_index = key_device->save_index = 0;
-		}
+        if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+        {
+            rt_memset(key_device->rx_buffer, 0,
+                sizeof(key_device->rx_buffer));
+            key_device->read_index = key_device->save_index = 0;
+        }
 
-		dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
-	}
+        dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_key_open(rt_device_t dev, rt_uint16_t oflag)
-{	
-	return RT_EOK;
+{
+    return RT_EOK;
 }
 
 static rt_err_t rt_key_close(rt_device_t dev)
-{	
-	return RT_EOK;
+{
+    return RT_EOK;
 }
 
 static rt_size_t rt_key_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
 {
-	rt_uint8_t* ptr;
-	rt_err_t err_code;
-	rt_base_t level;
-	
-	ptr = buffer;
-	err_code = RT_EOK;
+    rt_uint8_t* ptr;
+    rt_err_t err_code;
+    rt_base_t level;
 
-	/* interrupt mode Rx */
-	while (size)
-	{
-		if (key_device->read_index != key_device->save_index)
-		{
-			*ptr++ = key_device->rx_buffer[key_device->read_index];
-			size --;
+    ptr = buffer;
+    err_code = RT_EOK;
 
-			/* disable interrupt */
-			level = rt_hw_interrupt_disable();
+    /* interrupt mode Rx */
+    while (size)
+    {
+        if (key_device->read_index != key_device->save_index)
+        {
+            *ptr++ = key_device->rx_buffer[key_device->read_index];
+            size --;
 
-			key_device->read_index ++;
-			if (key_device->read_index >= KEY_RX_BUFFER_SIZE)
-				key_device->read_index = 0;
+            /* disable interrupt */
+            level = rt_hw_interrupt_disable();
 
-			/* enable interrupt */
-			rt_hw_interrupt_enable(level);
-		}
-		else
-		{
-			/* set error code */
-			err_code = -RT_EEMPTY;
-			break;
-		}
-	}
+            key_device->read_index ++;
+            if (key_device->read_index >= KEY_RX_BUFFER_SIZE)
+                key_device->read_index = 0;
 
-	/* set error code */
-	rt_set_errno(err_code);
-	return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+            /* enable interrupt */
+            rt_hw_interrupt_enable(level);
+        }
+        else
+        {
+            /* set error code */
+            err_code = -RT_EEMPTY;
+            break;
+        }
+    }
+
+    /* set error code */
+    rt_set_errno(err_code);
+    return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
 }
 
 static rt_err_t rt_key_control(rt_device_t dev, int cmd, void *args)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 #ifdef RT_USING_RTGUI
@@ -215,96 +211,96 @@ static int s_key_map[0xff] = {0};
 
 static void rt_keymap_init(void)
 {
-	s_key_map[0x1] = RTGUIK_ESCAPE;
-	s_key_map[0xc] = RTGUIK_MINUS;
-	s_key_map[0x39] = RTGUIK_SPACE;
-	s_key_map[0xd] = RTGUIK_KP_EQUALS;
-	s_key_map[0xe] = RTGUIK_BACKSPACE;
-	s_key_map[0xf] = RTGUIK_TAB;
-	s_key_map[0x1c] = RTGUIK_KP_ENTER;
-	s_key_map[0xb] = RTGUIK_0;
-	s_key_map[0x2] = RTGUIK_1; 
-	s_key_map[0x3] = RTGUIK_2;
-	s_key_map[0x4] = RTGUIK_3;
-	s_key_map[0x5] = RTGUIK_4;
-	s_key_map[0x6] = RTGUIK_5;
-	s_key_map[0x7] = RTGUIK_6;
-	s_key_map[0x8] = RTGUIK_7;
-	s_key_map[0x9] = RTGUIK_8;
-	s_key_map[0xa] = RTGUIK_9;
-	s_key_map[0x3b] = RTGUIK_F1; 
-	s_key_map[0x3c] = RTGUIK_F2;
-	s_key_map[0x3d] = RTGUIK_F3;
-	s_key_map[0x3e] = RTGUIK_F4;
-	s_key_map[0xef] = RTGUIK_F5;
-	s_key_map[0x40] = RTGUIK_F6;
-	s_key_map[0x41] = RTGUIK_F7;
-	s_key_map[0x42] = RTGUIK_F8;
-	s_key_map[0x43] = RTGUIK_F9;
-	s_key_map[0x1e] = RTGUIK_a;
-	s_key_map[0x30] = RTGUIK_b;
-	s_key_map[0x2c] = RTGUIK_c;
-	s_key_map[0x20] = RTGUIK_d;
-	s_key_map[0x12] = RTGUIK_e;
-	s_key_map[0x21] = RTGUIK_f;
-	s_key_map[0x22] = RTGUIK_g;
-	s_key_map[0x23] = RTGUIK_h;
-	s_key_map[0x17] = RTGUIK_i;
-	s_key_map[0x24] = RTGUIK_j;
-	s_key_map[0x25] = RTGUIK_k;
-	s_key_map[0x26] = RTGUIK_l;
-	s_key_map[0x32] = RTGUIK_m;
-	s_key_map[0x31] = RTGUIK_n;
-	s_key_map[0x18] = RTGUIK_o;
-	s_key_map[0x19] = RTGUIK_p;
-	s_key_map[0x10] = RTGUIK_q;
-	s_key_map[0x13] = RTGUIK_r;
-	s_key_map[0x1f] = RTGUIK_s;
-	s_key_map[0x14] = RTGUIK_t;
-	s_key_map[0x16] = RTGUIK_u;
-	s_key_map[0x2f] = RTGUIK_v;
-	s_key_map[0x11] = RTGUIK_w;
-	s_key_map[0x2d] = RTGUIK_x;
-	s_key_map[0x15] = RTGUIK_y;
-	s_key_map[0x2c] = RTGUIK_z;
-	s_key_map[0x4b] = RTGUIK_LEFT;
-	s_key_map[0x4d] = RTGUIK_RIGHT;
-	s_key_map[0x50] = RTGUIK_DOWN;
-	s_key_map[0x2e] = RTGUIK_DELETE;
-	s_key_map[0x48] = RTGUIK_UP;
-}	
+    s_key_map[0x1] = RTGUIK_ESCAPE;
+    s_key_map[0xc] = RTGUIK_MINUS;
+    s_key_map[0x39] = RTGUIK_SPACE;
+    s_key_map[0xd] = RTGUIK_KP_EQUALS;
+    s_key_map[0xe] = RTGUIK_BACKSPACE;
+    s_key_map[0xf] = RTGUIK_TAB;
+    s_key_map[0x1c] = RTGUIK_KP_ENTER;
+    s_key_map[0xb] = RTGUIK_0;
+    s_key_map[0x2] = RTGUIK_1;
+    s_key_map[0x3] = RTGUIK_2;
+    s_key_map[0x4] = RTGUIK_3;
+    s_key_map[0x5] = RTGUIK_4;
+    s_key_map[0x6] = RTGUIK_5;
+    s_key_map[0x7] = RTGUIK_6;
+    s_key_map[0x8] = RTGUIK_7;
+    s_key_map[0x9] = RTGUIK_8;
+    s_key_map[0xa] = RTGUIK_9;
+    s_key_map[0x3b] = RTGUIK_F1;
+    s_key_map[0x3c] = RTGUIK_F2;
+    s_key_map[0x3d] = RTGUIK_F3;
+    s_key_map[0x3e] = RTGUIK_F4;
+    s_key_map[0xef] = RTGUIK_F5;
+    s_key_map[0x40] = RTGUIK_F6;
+    s_key_map[0x41] = RTGUIK_F7;
+    s_key_map[0x42] = RTGUIK_F8;
+    s_key_map[0x43] = RTGUIK_F9;
+    s_key_map[0x1e] = RTGUIK_a;
+    s_key_map[0x30] = RTGUIK_b;
+    s_key_map[0x2c] = RTGUIK_c;
+    s_key_map[0x20] = RTGUIK_d;
+    s_key_map[0x12] = RTGUIK_e;
+    s_key_map[0x21] = RTGUIK_f;
+    s_key_map[0x22] = RTGUIK_g;
+    s_key_map[0x23] = RTGUIK_h;
+    s_key_map[0x17] = RTGUIK_i;
+    s_key_map[0x24] = RTGUIK_j;
+    s_key_map[0x25] = RTGUIK_k;
+    s_key_map[0x26] = RTGUIK_l;
+    s_key_map[0x32] = RTGUIK_m;
+    s_key_map[0x31] = RTGUIK_n;
+    s_key_map[0x18] = RTGUIK_o;
+    s_key_map[0x19] = RTGUIK_p;
+    s_key_map[0x10] = RTGUIK_q;
+    s_key_map[0x13] = RTGUIK_r;
+    s_key_map[0x1f] = RTGUIK_s;
+    s_key_map[0x14] = RTGUIK_t;
+    s_key_map[0x16] = RTGUIK_u;
+    s_key_map[0x2f] = RTGUIK_v;
+    s_key_map[0x11] = RTGUIK_w;
+    s_key_map[0x2d] = RTGUIK_x;
+    s_key_map[0x15] = RTGUIK_y;
+    s_key_map[0x2c] = RTGUIK_z;
+    s_key_map[0x4b] = RTGUIK_LEFT;
+    s_key_map[0x4d] = RTGUIK_RIGHT;
+    s_key_map[0x50] = RTGUIK_DOWN;
+    s_key_map[0x2e] = RTGUIK_DELETE;
+    s_key_map[0x48] = RTGUIK_UP;
+}
 
 static rt_err_t rtgui_key_rx(rt_device_t dev, rt_size_t size)
 {
-	struct rtgui_event_kbd kbd_event;
-	char key_value;
+    struct rtgui_event_kbd kbd_event;
+    char key_value;
 
-	while(rt_device_read(dev, 0, &key_value, 1) == 1)
-	{
-		/* init keyboard event */
-		RTGUI_EVENT_KBD_INIT(&kbd_event);
-		kbd_event.mod  = RTGUI_KMOD_NONE;
-		kbd_event.unicode = 0;
-		kbd_event.key = RTGUIK_UNKNOWN;
+    while(rt_device_read(dev, 0, &key_value, 1) == 1)
+    {
+        /* init keyboard event */
+        RTGUI_EVENT_KBD_INIT(&kbd_event);
+        kbd_event.mod  = RTGUI_KMOD_NONE;
+        kbd_event.unicode = 0;
+        kbd_event.key = RTGUIK_UNKNOWN;
 
-		if(key_value &  0x80)
-		{	
-			kbd_event.type = RTGUI_KEYUP;
-		}	
-		else
-		{
-			kbd_event.type = RTGUI_KEYDOWN;
-		}	
+        if(key_value &  0x80)
+        {
+            kbd_event.type = RTGUI_KEYUP;
+        }
+        else
+        {
+            kbd_event.type = RTGUI_KEYDOWN;
+        }
 
-		kbd_event.key = s_key_map[key_value & 0x7F];
-	}
-	if (kbd_event.key != RTGUIK_UNKNOWN)
-	{
-		/* post down event */
-		rtgui_server_post_event(&(kbd_event.parent), sizeof(kbd_event));
-	}
-	
-	return RT_EOK;
+        kbd_event.key = s_key_map[key_value & 0x7F];
+    }
+    if (kbd_event.key != RTGUIK_UNKNOWN)
+    {
+        /* post down event */
+        rtgui_server_post_event(&(kbd_event.parent), sizeof(kbd_event));
+    }
+
+    return RT_EOK;
 }
 
 #endif
@@ -314,33 +310,33 @@ static rt_err_t rtgui_key_rx(rt_device_t dev, rt_size_t size)
  */
 void rt_hw_key_init(void)
 {
-	/* hardware init */
-	key_init();
+    /* hardware init */
+    key_init();
 
-	key_device = (struct rt_key_device*)rt_malloc (sizeof(struct rt_key_device));
-	if (key_device == RT_NULL) return; /* no memory yet */
+    key_device = (struct rt_key_device*)rt_malloc (sizeof(struct rt_key_device));
+    if (key_device == RT_NULL) return; /* no memory yet */
 
-	/* clear device structure */
-	rt_memset(&(key_device->parent), 0, sizeof(struct rt_device));
-	
-	key_device->parent.type 		= RT_Device_Class_Char;
-	key_device->parent.tx_complete = RT_NULL;
-	key_device->parent.init 		= rt_key_init;
-	key_device->parent.open		= rt_key_open;
-	key_device->parent.close		= rt_key_close;
-	key_device->parent.read 		= rt_key_read;
-	key_device->parent.write 		= RT_NULL;
-	key_device->parent.control 	= rt_key_control;
-	key_device->parent.user_data   = RT_NULL;
+    /* clear device structure */
+    rt_memset(&(key_device->parent), 0, sizeof(struct rt_device));
+
+    key_device->parent.type         = RT_Device_Class_Char;
+    key_device->parent.tx_complete = RT_NULL;
+    key_device->parent.init         = rt_key_init;
+    key_device->parent.open     = rt_key_open;
+    key_device->parent.close        = rt_key_close;
+    key_device->parent.read         = rt_key_read;
+    key_device->parent.write        = RT_NULL;
+    key_device->parent.control  = rt_key_control;
+    key_device->parent.user_data   = RT_NULL;
 
 #ifdef RT_USING_RTGUI
-	key_device->parent.rx_indicate = rtgui_key_rx;
+    key_device->parent.rx_indicate = rtgui_key_rx;
 
-	/* init keymap */
-	rt_keymap_init();
+    /* init keymap */
+    rt_keymap_init();
 #endif
 
-	/* register key device to RT-Thread */
-	rt_device_register(&(key_device->parent), "key", RT_DEVICE_FLAG_RDONLY | RT_DEVICE_FLAG_INT_RX);
+    /* register key device to RT-Thread */
+    rt_device_register(&(key_device->parent), "key", RT_DEVICE_FLAG_RDONLY | RT_DEVICE_FLAG_INT_RX);
 }
 
diff --git a/bsp/mini2440/drivers/lcd_a70.c b/bsp/mini2440/drivers/lcd_a70.c
index 5020012b2f..9d7da3f8c6 100644
--- a/bsp/mini2440/drivers/lcd_a70.c
+++ b/bsp/mini2440/drivers/lcd_a70.c
@@ -1,11 +1,7 @@
 /*
- * File      : lcd_t35.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -141,7 +137,7 @@ static void LcdBkLtSet(rt_uint32_t HiRatio)
 #define FREQ_PWM1       1000
     if(!HiRatio)
     {
-        GPBCON  = GPBCON & (~(3<<2)) | (1<<2) ; 
+        GPBCON  = GPBCON & (~(3<<2)) | (1<<2) ;
         GPBDAT &= ~(1<<1);
         return;
     }
@@ -212,7 +208,7 @@ static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args)
         break;
     case RTGRAPHIC_CTRL_POWEROFF:
         break;
-    case RTGRAPHIC_CTRL_GET_INFO:       
+    case RTGRAPHIC_CTRL_GET_INFO:
         rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
         break;
     case RTGRAPHIC_CTRL_SET_MODE:
@@ -225,7 +221,7 @@ static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args)
 int rt_hw_lcd_init(void)
 {
     rt_device_t lcd = rt_malloc(sizeof(struct rt_device));
-    if (lcd == RT_NULL) 
+    if (lcd == RT_NULL)
             return -RT_ERROR; /* no memory yet */
 
     _lcd_info.bits_per_pixel = 16;
@@ -241,7 +237,7 @@ int rt_hw_lcd_init(void)
     lcd->close = RT_NULL;
     lcd->control = rt_lcd_control;
     lcd->user_data = (void*)&_lcd_info;
-    
+
     /* register lcd device to RT-Thread */
     rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR);
 }
diff --git a/bsp/mini2440/drivers/lcd_n35.c b/bsp/mini2440/drivers/lcd_n35.c
index 1a3af23c09..f536dd5d7d 100644
--- a/bsp/mini2440/drivers/lcd_n35.c
+++ b/bsp/mini2440/drivers/lcd_n35.c
@@ -1,11 +1,7 @@
 /*
- * File      : lcd_t35.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -142,7 +138,7 @@ static void LcdBkLtSet(rt_uint32_t HiRatio)
 #define FREQ_PWM1       1000
     if(!HiRatio)
     {
-        GPBCON  = GPBCON & (~(3<<2)) | (1<<2) ; 
+        GPBCON  = GPBCON & (~(3<<2)) | (1<<2) ;
         GPBDAT &= ~(1<<1);
         return;
     }
@@ -167,7 +163,7 @@ static void LcdBkLtSet(rt_uint32_t HiRatio)
 
 /* RT-Thread Device Interface */
 static rt_err_t rt_lcd_init (rt_device_t dev)
-{   
+{
     GPB1_TO_OUT();
     GPB1_TO_1();
 
@@ -213,7 +209,7 @@ static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args)
         break;
     case RTGRAPHIC_CTRL_POWEROFF:
         break;
-    case RTGRAPHIC_CTRL_GET_INFO:       
+    case RTGRAPHIC_CTRL_GET_INFO:
         rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
         break;
     case RTGRAPHIC_CTRL_SET_MODE:
@@ -226,7 +222,7 @@ static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args)
 int rt_hw_lcd_init(void)
 {
     rt_device_t lcd = rt_malloc(sizeof(struct rt_device));
-    if (lcd == RT_NULL) 
+    if (lcd == RT_NULL)
             return -RT_ERROR; /* no memory yet */
 
     _lcd_info.bits_per_pixel = 16;
@@ -242,7 +238,7 @@ int rt_hw_lcd_init(void)
     lcd->close = RT_NULL;
     lcd->control = rt_lcd_control;
     lcd->user_data = (void*)&_lcd_info;
-    
+
     /* register lcd device to RT-Thread */
     rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR);
 }
diff --git a/bsp/mini2440/drivers/lcd_t35.c b/bsp/mini2440/drivers/lcd_t35.c
index c13a3c030f..edf8db17f9 100644
--- a/bsp/mini2440/drivers/lcd_t35.c
+++ b/bsp/mini2440/drivers/lcd_t35.c
@@ -1,11 +1,7 @@
 /*
- * File      : lcd_t35.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -142,7 +138,7 @@ static void LcdBkLtSet(rt_uint32_t HiRatio)
 #define FREQ_PWM1       1000
     if(!HiRatio)
     {
-        GPBCON  = GPBCON & (~(3<<2)) | (1<<2) ; 
+        GPBCON  = GPBCON & (~(3<<2)) | (1<<2) ;
         GPBDAT &= ~(1<<1);
         return;
     }
@@ -167,7 +163,7 @@ static void LcdBkLtSet(rt_uint32_t HiRatio)
 
 /* RT-Thread Device Interface */
 static rt_err_t rt_lcd_init (rt_device_t dev)
-{   
+{
     GPB1_TO_OUT();
     GPB1_TO_1();
 
@@ -214,7 +210,7 @@ static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args)
         break;
     case RTGRAPHIC_CTRL_POWEROFF:
         break;
-    case RTGRAPHIC_CTRL_GET_INFO:       
+    case RTGRAPHIC_CTRL_GET_INFO:
         rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
         break;
     case RTGRAPHIC_CTRL_SET_MODE:
@@ -227,7 +223,7 @@ static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args)
 int rt_hw_lcd_init(void)
 {
     rt_device_t lcd = rt_malloc(sizeof(struct rt_device));
-    if (lcd == RT_NULL) 
+    if (lcd == RT_NULL)
         return -RT_ERROR; /* no memory yet */
 
     _lcd_info.bits_per_pixel = 16;
@@ -243,7 +239,7 @@ int rt_hw_lcd_init(void)
     lcd->close = RT_NULL;
     lcd->control = rt_lcd_control;
     lcd->user_data = (void*)&_lcd_info;
-    
+
     /* register lcd device to RT-Thread */
     rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR);
 }
diff --git a/bsp/mini2440/drivers/lcd_x35.c b/bsp/mini2440/drivers/lcd_x35.c
index b4a8fda23c..a198aac05e 100644
--- a/bsp/mini2440/drivers/lcd_x35.c
+++ b/bsp/mini2440/drivers/lcd_x35.c
@@ -1,16 +1,12 @@
 /*
- * File      : lcd_x35.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2010-01-01     bernard      first version from QiuYi's driver
- * 2011-07-13     Manoel       Modifications on lcd_n35.c to support X35 LCD  
+ * 2011-07-13     Manoel       Modifications on lcd_n35.c to support X35 LCD
  *                             ACX502BMU - 7522J16D SONY
  */
 
@@ -28,7 +24,7 @@
 #define LCD_HSYNC_LEN 5     // hsync
 
 #define LCD_UPPER_MARGIN 1  // margin_top
-#define LCD_LOWER_MARGIN 3  // margin_botton 
+#define LCD_LOWER_MARGIN 3  // margin_botton
 #define LCD_VSYNC_LEN 9     // vsync
 
 #define LCD_XSIZE  LCD_WIDTH
@@ -144,7 +140,7 @@ static void LcdBkLtSet(rt_uint32_t HiRatio)
 #define FREQ_PWM1       1000
     if(!HiRatio)
     {
-        GPBCON  = GPBCON & (~(3<<2)) | (1<<2) ; 
+        GPBCON  = GPBCON & (~(3<<2)) | (1<<2) ;
         GPBDAT &= ~(1<<1);
         return;
     }
@@ -169,7 +165,7 @@ static void LcdBkLtSet(rt_uint32_t HiRatio)
 
 /* RT-Thread Device Interface */
 static rt_err_t rt_lcd_init (rt_device_t dev)
-{   
+{
     GPB1_TO_OUT();
     GPB1_TO_1();
 
@@ -219,7 +215,7 @@ static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args)
         break;
     case RTGRAPHIC_CTRL_POWEROFF:
         break;
-    case RTGRAPHIC_CTRL_GET_INFO:       
+    case RTGRAPHIC_CTRL_GET_INFO:
         rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
         break;
     case RTGRAPHIC_CTRL_SET_MODE:
@@ -232,7 +228,7 @@ static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args)
 int rt_hw_lcd_init(void)
 {
     rt_device_t lcd = rt_malloc(sizeof(struct rt_device));
-    if (lcd == RT_NULL) 
+    if (lcd == RT_NULL)
             return -RT_ERROR; /* no memory yet */
 
     _lcd_info.bits_per_pixel = 16;
@@ -248,7 +244,7 @@ int rt_hw_lcd_init(void)
     lcd->close = RT_NULL;
     lcd->control = rt_lcd_control;
     lcd->user_data = (void*)&_lcd_info;
-    
+
     /* register lcd device to RT-Thread */
     rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR);
 }
diff --git a/bsp/mini2440/drivers/led.c b/bsp/mini2440/drivers/led.c
index 4155a6bab7..88e83d33ef 100644
--- a/bsp/mini2440/drivers/led.c
+++ b/bsp/mini2440/drivers/led.c
@@ -1,11 +1,7 @@
 /*
- * File      : led.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -22,19 +18,19 @@
 
 void rt_hw_led_init(void)
 {
-	/* GPB5,GPB6,GPB7,GPB8 for LED */
-	GPBCON = GPBCON & (~(0xff << 10)) | (0x55 << 10);
-	GPBUP  |= (0x0f << 5);
+    /* GPB5,GPB6,GPB7,GPB8 for LED */
+    GPBCON = GPBCON & (~(0xff << 10)) | (0x55 << 10);
+    GPBUP  |= (0x0f << 5);
 }
 
 void rt_hw_led_on(unsigned char value)
 {
-	GPBDAT &= ~ ((value & 0x0f) << 5);
+    GPBDAT &= ~ ((value & 0x0f) << 5);
 }
 
 void rt_hw_led_off(unsigned char value)
 {
-	GPBDAT |= (value & 0x0f) << 5;
+    GPBDAT |= (value & 0x0f) << 5;
 }
 
 /*@}*/
diff --git a/bsp/mini2440/drivers/led.h b/bsp/mini2440/drivers/led.h
index bc719f182e..67deceb230 100644
--- a/bsp/mini2440/drivers/led.h
+++ b/bsp/mini2440/drivers/led.h
@@ -1,11 +1,7 @@
 /*
- * File      : led.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/mini2440/drivers/touch.c b/bsp/mini2440/drivers/touch.c
index 404169a43f..122488daff 100644
--- a/bsp/mini2440/drivers/touch.c
+++ b/bsp/mini2440/drivers/touch.c
@@ -1,17 +1,13 @@
 /*
- * File      : touch.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010 - 2012, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2010-01-01     Yi.Qiu      first version
  */
- 
+
 #include 
 #include 
 #include 
@@ -104,7 +100,7 @@ struct rtgui_touch_device
 
     rt_uint16_t width;
     rt_uint16_t height;
-    
+
     rt_bool_t first_down_report;
 };
 static struct rtgui_touch_device *touch = RT_NULL;
@@ -120,7 +116,7 @@ static void report_touch_input(int updown)
     /* set emouse button */
     emouse.button = RTGUI_MOUSE_BUTTON_LEFT;
     emouse.parent.sender = RT_NULL;
-    
+
     if (updown)
     {
         ts.xp = ts.xp / ts.count;
@@ -166,7 +162,7 @@ static void report_touch_input(int updown)
             emouse.button |= RTGUI_MOUSE_BUTTON_DOWN;
         }
         else
-        {   
+        {
             emouse.parent.type = RTGUI_EVENT_MOUSE_MOTION;
             emouse.button = 0;
         }
@@ -174,7 +170,7 @@ static void report_touch_input(int updown)
     else
     {
         emouse.x = touch->x;
-        emouse.y = touch->y;    
+        emouse.y = touch->y;
         emouse.parent.type = RTGUI_EVENT_MOUSE_BUTTON;
         emouse.button |= RTGUI_MOUSE_BUTTON_UP;
         if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL))
@@ -185,11 +181,11 @@ static void report_touch_input(int updown)
     }
 
     /* rt_kprintf("touch %s: ts.x: %d, ts.y: %d\n", updown? "down" : "up",
-    touch->x, touch->y); */ 
-    
+    touch->x, touch->y); */
+
     /* send event to server */
     if (touch->calibrating != RT_TRUE)
-    {   
+    {
         rtgui_server_post_event((&emouse.parent), sizeof(emouse));
     }
 }
@@ -237,7 +233,7 @@ static void report_touch_input(int updown)
         {
             if (touch->calibrating != RT_TRUE && touch->eventpost_func)
             {
-                touch->eventpost_func(touch->eventpost_param, &touch_event); 
+                touch->eventpost_func(touch->eventpost_param, &touch_event);
             }
         }
     }
@@ -246,7 +242,7 @@ static void report_touch_input(int updown)
         touch_event.x = touch->x;
         touch_event.y = touch->y;
         touch_event.pressed = 0;
-        
+
         if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL))
         {
             /* callback function */
@@ -254,8 +250,8 @@ static void report_touch_input(int updown)
         }
 
         if (touch->calibrating != RT_TRUE && touch->eventpost_func)
-        {   
-            touch->eventpost_func(touch->eventpost_param, &touch_event); 
+        {
+            touch->eventpost_func(touch->eventpost_param, &touch_event);
         }
     }
 }
@@ -295,7 +291,7 @@ static void s3c2410_adc_stylus_action(void)
 
     data0 = ADCDAT0;
     data1 = ADCDAT1;
-    
+
     ts.xp += data0 & S3C2410_ADCDAT0_XPDATA_MASK;
     ts.yp += data1 & S3C2410_ADCDAT1_YPDATA_MASK;
     ts.count ++;
@@ -336,10 +332,10 @@ static void s3c2410_intc_stylus_updown(void)
 
     /* rt_kprintf("stylus: %s\n", updown? "down" : "up"); */
 
-    if (updown) 
+    if (updown)
     {
         touch_timer_fire(0);
-    }   
+    }
     else
     {
         /* stop timer */
@@ -437,7 +433,7 @@ static rt_err_t rtgui_touch_control(rt_device_t dev, int cmd, void *args)
         /*
             rt_kprintf("min_x = %d, max_x = %d, min_y = %d, max_y = %d\n",
                 touch->min_x, touch->max_x, touch->min_y, touch->max_y);
-        */      
+        */
     }
         break;
 
@@ -480,10 +476,10 @@ int rtgui_touch_hw_init(void)
     touch->parent.user_data = RT_NULL;
 
     device = rt_device_find("lcd");
-    if (device == RT_NULL) 
+    if (device == RT_NULL)
     {
         rt_kprintf("No lcd found\n");
-        return -RT_ERROR; /* no this device */  
+        return -RT_ERROR; /* no this device */
     }
 
     /* get graphic device info */
@@ -497,7 +493,7 @@ int rtgui_touch_hw_init(void)
 
     touch->width = info.width;
     touch->height = info.height;
-    
+
     /* create 1/8 second timer */
     touch->poll_timer = rt_timer_create("touch", touch_timer_fire, RT_NULL,
                                         RT_TICK_PER_SECOND/8, RT_TIMER_FLAG_PERIODIC);
diff --git a/bsp/mini4020/applications/application.c b/bsp/mini4020/applications/application.c
index 6281b8385d..f5a77d8c60 100644
--- a/bsp/mini4020/applications/application.c
+++ b/bsp/mini4020/applications/application.c
@@ -1,22 +1,18 @@
 /*
- * File      : application.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2007-11-20     Yi.Qiu		add rtgui application
- * 2008-6-28      Bernard		no rtgui init
+ * Date           Author        Notes
+ * 2007-11-20     Yi.Qiu        add rtgui application
+ * 2008-6-28      Bernard       no rtgui init
  */
 
 /**
  * @addtogroup mini4020
  */
- 
+
 /*@{*/
 
 #include 
@@ -38,54 +34,54 @@ extern void radio_rtgui_init(void);
 
 void rt_init_thread_entry(void *parameter)
 {
-	int fd;
-	rt_uint32_t sz;
-	char buffer[20];
+    int fd;
+    rt_uint32_t sz;
+    char buffer[20];
 #ifdef RT_USING_DFS
-	dfs_init();
+    dfs_init();
 #ifdef RT_USING_DFS_ELMFAT
-	elm_init();
-	/* mount sd card fat partition 1 as root directory */
-	if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
-	{
-		rt_kprintf("File System initialized!\n");
+    elm_init();
+    /* mount sd card fat partition 1 as root directory */
+    if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
+    {
+        rt_kprintf("File System initialized!\n");
 
-		/*Open a file*/
-		fd = open("/fattest.txt", O_RDWR|O_CREAT, 0);
-		if (fd < 0)
-		{
-			rt_kprintf("open file for write failed\n");
-			return;
-		}
+        /*Open a file*/
+        fd = open("/fattest.txt", O_RDWR|O_CREAT, 0);
+        if (fd < 0)
+        {
+            rt_kprintf("open file for write failed\n");
+            return;
+        }
 
-		sz = write(fd,"Hello RT-Thread!",sizeof("Hello RT-Thread!"));
+        sz = write(fd,"Hello RT-Thread!",sizeof("Hello RT-Thread!"));
 
-		if (sz != 0)
-		{
-			rt_kprintf("written %d\n",sz);
-		}
-		else
-			rt_kprintf("haven't written\n");
+        if (sz != 0)
+        {
+            rt_kprintf("written %d\n",sz);
+        }
+        else
+            rt_kprintf("haven't written\n");
 
-		lseek(fd, 0, SEEK_SET);
-		
-		sz = read(fd, buffer, sizeof(buffer));
+        lseek(fd, 0, SEEK_SET);
 
-		if (sz != 0)
-		{
-			rt_kprintf("READ %d:",sz);
-			while (sz--)
-				rt_kprintf("%c",buffer[sz]);//opposite
-			rt_kprintf("\n");
-		}
-		else
-			rt_kprintf("haven't read\n");
+        sz = read(fd, buffer, sizeof(buffer));
 
-		close(fd);
-	}
-	else
-		rt_kprintf("File System initialzation failed!\n");
-#endif	
+        if (sz != 0)
+        {
+            rt_kprintf("READ %d:",sz);
+            while (sz--)
+                rt_kprintf("%c",buffer[sz]);//opposite
+            rt_kprintf("\n");
+        }
+        else
+            rt_kprintf("haven't read\n");
+
+        close(fd);
+    }
+    else
+        rt_kprintf("File System initialzation failed!\n");
+#endif
 #endif
 }
 
@@ -108,23 +104,23 @@ void rt_led_thread_entry(void *parameter)
 
 int rt_application_init(void)
 {
-	rt_thread_t init_thread;
-	rt_thread_t led_thread;
+    rt_thread_t init_thread;
+    rt_thread_t led_thread;
 
-	init_thread = rt_thread_create("init",
-								rt_init_thread_entry, RT_NULL,
-								RT_INIT_THREAD_STACK_SIZE, 8, 20);
-	led_thread = rt_thread_create("led",
-								rt_led_thread_entry, RT_NULL,
-								512, 200, 20);
+    init_thread = rt_thread_create("init",
+                                rt_init_thread_entry, RT_NULL,
+                                RT_INIT_THREAD_STACK_SIZE, 8, 20);
+    led_thread = rt_thread_create("led",
+                                rt_led_thread_entry, RT_NULL,
+                                512, 200, 20);
 
-	if (init_thread != RT_NULL)
-		rt_thread_startup(init_thread);
+    if (init_thread != RT_NULL)
+        rt_thread_startup(init_thread);
 
-	if (led_thread != RT_NULL)
-		rt_thread_startup(led_thread);
-	
-	return 0;
+    if (led_thread != RT_NULL)
+        rt_thread_startup(led_thread);
+
+    return 0;
 }
 
 /*@}*/
diff --git a/bsp/mini4020/applications/startup.c b/bsp/mini4020/applications/startup.c
index ae84f8b461..4d07a8edd7 100644
--- a/bsp/mini4020/applications/startup.c
+++ b/bsp/mini4020/applications/startup.c
@@ -1,11 +1,7 @@
 /*
- * File      : application.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -26,12 +22,12 @@
 #include 
 #endif
 
-#define SDRAM_BASE	0x30000000
+#define SDRAM_BASE  0x30000000
 
 #ifdef __CC_ARM
 extern int Image$$RW_RAM1$$ZI$$Limit;
 #elif (defined (__GNUC__))
-	extern unsigned char __bss_end;
+    extern unsigned char __bss_end;
 #endif
 
 extern void rt_application_init(void);
@@ -40,72 +36,72 @@ extern void sd_init(void);
 
 void rtthread_startup()
 {
-	/* init hardware interrupt */
-	rt_hw_interrupt_init();
+    /* init hardware interrupt */
+    rt_hw_interrupt_init();
 
-	/* init board */
-	rt_hw_board_init();
+    /* init board */
+    rt_hw_board_init();
 
-	/* show version */
-	rt_show_version();
-		
-	/* init timer system */
-	rt_system_timer_init();
+    /* show version */
+    rt_show_version();
 
-	/* init heap memory system */
+    /* init timer system */
+    rt_system_timer_init();
+
+    /* init heap memory system */
 #ifdef __CC_ARM
-	rt_system_heap_init((void*)&Image$$RW_RAM1$$ZI$$Limit, (void*)(SDRAM_BASE + 0x200000));
+    rt_system_heap_init((void*)&Image$$RW_RAM1$$ZI$$Limit, (void*)(SDRAM_BASE + 0x200000));
 #else
-	rt_system_heap_init(&__bss_end, (void*)0x34000000);
+    rt_system_heap_init(&__bss_end, (void*)0x34000000);
 #endif
 
 
-	/* init scheduler system */
-	rt_system_scheduler_init();
+    /* init scheduler system */
+    rt_system_scheduler_init();
 
 #ifdef RT_USING_DEVICE
 
 #ifdef RT_USING_DFS
-	rt_hw_sdcard_init();
+    rt_hw_sdcard_init();
 #endif
 
 #ifdef RT_USING_LWIP
-	eth_system_device_init();
-	rt_hw_dm9161_init();
+    eth_system_device_init();
+    rt_hw_dm9161_init();
 #endif
 #endif
 
-	/* init application */
-	rt_application_init();
+    /* init application */
+    rt_application_init();
 
 #ifdef RT_USING_FINSH
-	/* init finsh */
-	finsh_system_init();
+    /* init finsh */
+    finsh_system_init();
 #ifdef RT_USING_DEVICE
-	finsh_set_device("uart0");
+    finsh_set_device("uart0");
 #endif
 #endif
 
-	/* init idle thread */
-	rt_thread_idle_init();
+    /* init idle thread */
+    rt_thread_idle_init();
 
-	/* start scheduler */
-	rt_system_scheduler_start();
+    /* start scheduler */
+    rt_system_scheduler_start();
+
+    /* never reach here */
+    return ;
 
-	/* never reach here */
-	return ;
-	
 }
 
 int main()
 {
-	/* disable interrupt first */
-	rt_hw_interrupt_disable();
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
 
-	/* startup RT-Thread RTOS */
-	rtthread_startup();
+    /* startup RT-Thread RTOS */
+    rtthread_startup();
 
-	return 0;
+    return 0;
 }
 
 
diff --git a/bsp/mini4020/drivers/board.h b/bsp/mini4020/drivers/board.h
index fd794a8a7c..baabfae361 100644
--- a/bsp/mini4020/drivers/board.h
+++ b/bsp/mini4020/drivers/board.h
@@ -1,11 +1,7 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/mini4020/drivers/dm9161.c b/bsp/mini4020/drivers/dm9161.c
index cae98435e2..a5100f501b 100644
--- a/bsp/mini4020/drivers/dm9161.c
+++ b/bsp/mini4020/drivers/dm9161.c
@@ -1,11 +1,7 @@
 /*
- * File      : dm9161.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -22,8 +18,8 @@
 #define SPEED_100   100
 #define SPEED_1000  1000
 /* Duplex, half or full. */
-#define DUPLEX_HALF		0x00
-#define DUPLEX_FULL		0x01
+#define DUPLEX_HALF     0x00
+#define DUPLEX_FULL     0x01
 
 /*
  * Davicom dm9161EP driver
@@ -32,9 +28,9 @@
  * nLAN_CS connects to nGCS4
  */
 
-/* #define dm9161_DEBUG		1 */
+/* #define dm9161_DEBUG     1 */
 #if DM9161_DEBUG
-#define DM9161_TRACE	rt_kprintf
+#define DM9161_TRACE    rt_kprintf
 #else
 #define DM9161_TRACE(...)
 #endif
@@ -65,18 +61,18 @@ struct rt_dm9161_eth
     struct eth_device parent;
 
     enum DM9161_TYPE type;
-	enum DM9161_PHY_mode mode;
+    enum DM9161_PHY_mode mode;
 
     rt_uint8_t imr_all;
-	rt_uint8_t phy_addr;
+    rt_uint8_t phy_addr;
 
-	rt_uint32_t tx_index;
+    rt_uint32_t tx_index;
 
     rt_uint8_t packet_cnt;                  /* packet I or II */
     rt_uint16_t queue_packet_len;           /* queued packet (packet II) */
 
     /* interface address info. */
-    rt_uint8_t  dev_addr[MAX_ADDR_LEN];		/* hw address	*/
+    rt_uint8_t  dev_addr[MAX_ADDR_LEN];     /* hw address   */
 };
 static struct rt_dm9161_eth dm9161_device;
 static struct rt_semaphore sem_ack, sem_lock;
@@ -85,33 +81,33 @@ void rt_dm9161_isr(int irqno, void *param);
 
 static void udelay(unsigned long ns)
 {
-	unsigned long i;
+    unsigned long i;
 
-	while (ns--)
-	{
-		i = 100;
-		while (i--);
-	}
+    while (ns--)
+    {
+        i = 100;
+        while (i--);
+    }
 }
 
 static __inline unsigned long sep_emac_read(unsigned int reg)
 {
-	void __iomem *emac_base = (void __iomem *)reg;
+    void __iomem *emac_base = (void __iomem *)reg;
 
-	return read_reg(emac_base);
+    return read_reg(emac_base);
 }
- 
+
 /*
 * Write to a EMAC register.
 */
 static __inline void sep_emac_write(unsigned int reg, unsigned long value)
 {
-	void __iomem *emac_base = (void __iomem *)reg;
- 
-	write_reg(emac_base,value);
+    void __iomem *emac_base = (void __iomem *)reg;
+
+    write_reg(emac_base,value);
 }
 
-  
+
 /* ........................... PHY INTERFACE ........................... */
 /*         CAN DO MAC CONFIGRATION
 * Enable the MDIO bit in MAC control register
@@ -120,12 +116,12 @@ static __inline void sep_emac_write(unsigned int reg, unsigned long value)
 */
 static void enable_mdi(void)           //need think more
 {
-	unsigned long ctl;
+    unsigned long ctl;
 
-	ctl = sep_emac_read(MAC_CTRL);
-	sep_emac_write(MAC_CTRL, ctl&(~0x3));    /* enable management port */
+    ctl = sep_emac_read(MAC_CTRL);
+    sep_emac_write(MAC_CTRL, ctl&(~0x3));    /* enable management port */
 
-	return;
+    return;
 }
 
 /*          CANNOT DO MAC CONFIGRATION
@@ -133,216 +129,216 @@ static void enable_mdi(void)           //need think more
 */
 static void disable_mdi(void)
 {
-	unsigned long ctl;
-  
-	ctl = sep_emac_read(MAC_CTRL);
-	sep_emac_write(MAC_CTRL, ctl|(0x3));    /* disable management port */
+    unsigned long ctl;
 
-	return;
+    ctl = sep_emac_read(MAC_CTRL);
+    sep_emac_write(MAC_CTRL, ctl|(0x3));    /* disable management port */
+
+    return;
 }
 
 /*
 * Wait until the PHY operation is complete.
 */
-static __inline void sep_phy_wait(void) 
+static __inline void sep_phy_wait(void)
 {
-	unsigned long timeout = 2;
+    unsigned long timeout = 2;
 
-	while ((sep_emac_read(MAC_MII_STATUS) & 0x2)) 
-	{
-		timeout--;
-		if (!timeout) 
-		{
-			EOUT("sep_ether: MDIO timeout\n");
-			break;
-		}		
-	}
+    while ((sep_emac_read(MAC_MII_STATUS) & 0x2))
+    {
+        timeout--;
+        if (!timeout)
+        {
+            EOUT("sep_ether: MDIO timeout\n");
+            break;
+        }
+    }
 
-	return;
+    return;
 }
- 
+
 /*
 * Write value to the a PHY register
 * Note: MDI interface is assumed to already have been enabled.
 */
 static void write_phy(unsigned char phy_addr, unsigned char address, unsigned int value)
 {
-	unsigned short mii_txdata;
-	
-	mii_txdata = value;
-	sep_emac_write(MAC_MII_ADDRESS,(unsigned long)(address<<8) | phy_addr);
-	sep_emac_write(MAC_MII_TXDATA ,mii_txdata);
-	sep_emac_write(MAC_MII_CMD ,0x4);
-	udelay(40);
+    unsigned short mii_txdata;
 
-	sep_phy_wait();
+    mii_txdata = value;
+    sep_emac_write(MAC_MII_ADDRESS,(unsigned long)(address<<8) | phy_addr);
+    sep_emac_write(MAC_MII_TXDATA ,mii_txdata);
+    sep_emac_write(MAC_MII_CMD ,0x4);
+    udelay(40);
 
-	return;	
+    sep_phy_wait();
+
+    return;
 }
- 
+
 /*
 * Read value stored in a PHY register.
 * Note: MDI interface is assumed to already have been enabled.
 */
 static void read_phy(unsigned char phy_addr, unsigned char address, unsigned int *value)
 {
-	unsigned short mii_rxdata;
-//	unsigned long mii_status;
-	
-	sep_emac_write(MAC_MII_ADDRESS,(unsigned long)(address<<8) | phy_addr);
-	sep_emac_write(MAC_MII_CMD ,0x2);
-	udelay(40);
-	sep_phy_wait();
-		
-	mii_rxdata = sep_emac_read(MAC_MII_RXDATA);
-	*value =  mii_rxdata;
+    unsigned short mii_rxdata;
+//  unsigned long mii_status;
 
-	return;
+    sep_emac_write(MAC_MII_ADDRESS,(unsigned long)(address<<8) | phy_addr);
+    sep_emac_write(MAC_MII_CMD ,0x2);
+    udelay(40);
+    sep_phy_wait();
+
+    mii_rxdata = sep_emac_read(MAC_MII_RXDATA);
+    *value =  mii_rxdata;
+
+    return;
 }
 
 /* interrupt service routine */
 void rt_dm9161_isr(int irqno, void *param)
 {
-	unsigned long intstatus;
-	rt_uint32_t address;
+    unsigned long intstatus;
+    rt_uint32_t address;
 
- 	mask_irq(INTSRC_MAC);
-	intstatus = sep_emac_read(MAC_INTSRC);
+    mask_irq(INTSRC_MAC);
+    intstatus = sep_emac_read(MAC_INTSRC);
 
-	sep_emac_write(MAC_INTSRC,intstatus);
-	
-	/*Receive complete*/
-	if(intstatus & 0x04)
-	{
-		eth_device_ready(&(dm9161_device.parent));
-	}
-	/*Receive error*/
-	else if(intstatus & 0x08)
-	{
-		rt_kprintf("Receive error\n");
-	}
-	/*Transmit complete*/
-	else if(intstatus & 0x03)
-	{
-			if(dm9161_device.tx_index == 0)
-				address = (MAC_TX_BD +(MAX_TX_DESCR-2)*8);
-			else if(dm9161_device.tx_index == 1) 
-				address = (MAC_TX_BD +(MAX_TX_DESCR-1)*8);
-			else 
-				address = (MAC_TX_BD + dm9161_device.tx_index*8-16);
-			//printk("free tx skb 0x%x in inter!!\n",lp->txBuffIndex);	
-			sep_emac_write(address,0x0);
-	}
-	else if (intstatus & 0x10)
-	{
-		rt_kprintf("ROVER ERROR\n");
-	}
+    sep_emac_write(MAC_INTSRC,intstatus);
 
-	while(intstatus)
-	{
-		sep_emac_write(MAC_INTSRC,intstatus);
-		intstatus = sep_emac_read(MAC_INTSRC);
-	}
+    /*Receive complete*/
+    if(intstatus & 0x04)
+    {
+        eth_device_ready(&(dm9161_device.parent));
+    }
+    /*Receive error*/
+    else if(intstatus & 0x08)
+    {
+        rt_kprintf("Receive error\n");
+    }
+    /*Transmit complete*/
+    else if(intstatus & 0x03)
+    {
+            if(dm9161_device.tx_index == 0)
+                address = (MAC_TX_BD +(MAX_TX_DESCR-2)*8);
+            else if(dm9161_device.tx_index == 1)
+                address = (MAC_TX_BD +(MAX_TX_DESCR-1)*8);
+            else
+                address = (MAC_TX_BD + dm9161_device.tx_index*8-16);
+            //printk("free tx skb 0x%x in inter!!\n",lp->txBuffIndex);
+            sep_emac_write(address,0x0);
+    }
+    else if (intstatus & 0x10)
+    {
+        rt_kprintf("ROVER ERROR\n");
+    }
 
-	unmask_irq(INTSRC_MAC);
+    while(intstatus)
+    {
+        sep_emac_write(MAC_INTSRC,intstatus);
+        intstatus = sep_emac_read(MAC_INTSRC);
+    }
+
+    unmask_irq(INTSRC_MAC);
 }
 
 static rt_err_t update_mac_address()
 {
-	rt_uint32_t lo,hi;
-	hi = sep_emac_read(MAC_ADDR1);
-	lo = sep_emac_read(MAC_ADDR0);
-	DBOUT("Before MAC: hi=%x lo=%x\n",hi,lo);
+    rt_uint32_t lo,hi;
+    hi = sep_emac_read(MAC_ADDR1);
+    lo = sep_emac_read(MAC_ADDR0);
+    DBOUT("Before MAC: hi=%x lo=%x\n",hi,lo);
 
-	sep_emac_write(MAC_ADDR0,(dm9161_device.dev_addr[2] << 24) | (dm9161_device.dev_addr[3] << 16) | (dm9161_device.dev_addr[4] << 8) | (dm9161_device.dev_addr[5]));
-	sep_emac_write(MAC_ADDR1,dm9161_device.dev_addr[1]|(dm9161_device.dev_addr[0]<<8));
+    sep_emac_write(MAC_ADDR0,(dm9161_device.dev_addr[2] << 24) | (dm9161_device.dev_addr[3] << 16) | (dm9161_device.dev_addr[4] << 8) | (dm9161_device.dev_addr[5]));
+    sep_emac_write(MAC_ADDR1,dm9161_device.dev_addr[1]|(dm9161_device.dev_addr[0]<<8));
 
-	hi = sep_emac_read(MAC_ADDR1);
-	lo = sep_emac_read(MAC_ADDR0);
-	DBOUT("After MAC: hi=%x lo=%x\n",hi,lo);
+    hi = sep_emac_read(MAC_ADDR1);
+    lo = sep_emac_read(MAC_ADDR0);
+    DBOUT("After MAC: hi=%x lo=%x\n",hi,lo);
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static int mii_link_ok(unsigned long phy_id)
 {
-	/* first, a dummy read, needed to latch some MII phys */
-	unsigned int value;
+    /* first, a dummy read, needed to latch some MII phys */
+    unsigned int value;
 
-	read_phy(phy_id, MII_BMSR,&value);
-	if (value & BMSR_LSTATUS)
-		return 1;
+    read_phy(phy_id, MII_BMSR,&value);
+    if (value & BMSR_LSTATUS)
+        return 1;
 
-	return 0;
+    return 0;
 }
 
 static void update_link_speed(unsigned short phy_addr)
 {
-	unsigned int bmsr, bmcr, lpa, mac_cfg;
-	unsigned int speed, duplex;
+    unsigned int bmsr, bmcr, lpa, mac_cfg;
+    unsigned int speed, duplex;
 
-	if (!mii_link_ok(phy_addr))
-	{
-		EOUT("Link Down\n");
-		//goto result;
-	}
+    if (!mii_link_ok(phy_addr))
+    {
+        EOUT("Link Down\n");
+        //goto result;
+    }
 
-	read_phy(phy_addr,MII_BMSR,&bmsr);
-	read_phy(phy_addr,MII_BMCR,&bmcr);
+    read_phy(phy_addr,MII_BMSR,&bmsr);
+    read_phy(phy_addr,MII_BMCR,&bmcr);
 
-	if (bmcr & BMCR_ANENABLE)                /* AutoNegotiation is enabled */
-	{                         
-		if (!(bmsr & BMSR_ANEGCOMPLETE))              /* Do nothing - another interrupt generated when negotiation complete */
-			goto result;              
+    if (bmcr & BMCR_ANENABLE)                /* AutoNegotiation is enabled */
+    {
+        if (!(bmsr & BMSR_ANEGCOMPLETE))              /* Do nothing - another interrupt generated when negotiation complete */
+            goto result;
+
+        read_phy(phy_addr, MII_LPA, &lpa);
+
+        if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF))
+            speed = SPEED_100;
+        else
+            speed = SPEED_10;
+
+        if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL))
+            duplex = DUPLEX_FULL;
+        else
+            duplex = DUPLEX_HALF;
+    }
+    else
+    {
+        speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
+        duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
+    }
+
+    /* Update the MAC */
+    mac_cfg = sep_emac_read(MAC_CTRL);
+    if (speed == SPEED_100)
+    {
+        mac_cfg |= 0x800;           /* set speed 100 M */
+        //bmcr &=(~0x2000);
+        //write_phy(lp->phy_address, MII_BMCR, bmcr); //将dm9161的速度设为10M
+        if (duplex == DUPLEX_FULL)              /* 100 Full Duplex */
+            mac_cfg |= 0x400;
+        else                                    /* 100 Half Duplex */
+            mac_cfg &= (~0x400);
+    }
+    else
+    {
+        mac_cfg &= (~0x800);             /* set speed 10 M */
+
+        if (duplex == DUPLEX_FULL)              /* 10 Full Duplex */
+            mac_cfg |= 0x400;
+        else                                /* 10 Half Duplex */
+            mac_cfg &= (~0x400);
+    }
+
+    sep_emac_write(MAC_CTRL, mac_cfg);
+    rt_kprintf("Link now %i M-%s\n",  speed, (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex");
 
-		read_phy(phy_addr, MII_LPA, &lpa);
-		
-		if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) 
-			speed = SPEED_100;
-		else 
-			speed = SPEED_10;
-			
-		if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL)) 
-			duplex = DUPLEX_FULL;
-		else 
-			duplex = DUPLEX_HALF;
-	} 
-	else 
-	{
-		speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
-		duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
-	}
- 
-	/* Update the MAC */
-	mac_cfg = sep_emac_read(MAC_CTRL);
-	if (speed == SPEED_100) 
-	{
-		mac_cfg |= 0x800;			/* set speed 100 M */
-		//bmcr &=(~0x2000);
-		//write_phy(lp->phy_address, MII_BMCR, bmcr); //dm9161ٶΪ10M
-		if (duplex == DUPLEX_FULL)              /* 100 Full Duplex */
-			mac_cfg |= 0x400;
-		else                                    /* 100 Half Duplex */
-			mac_cfg &= (~0x400);
-	} 
-	else 
-	{
-		mac_cfg &= (~0x800);             /* set speed 10 M */
-		
-		if (duplex == DUPLEX_FULL)              /* 10 Full Duplex */
-			mac_cfg |= 0x400;
-		else                                /* 10 Half Duplex */
-			mac_cfg &= (~0x400);
-	}
-	
-	sep_emac_write(MAC_CTRL, mac_cfg);
-	rt_kprintf("Link now %i M-%s\n",  speed, (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex");
-			
 result:
-	mac_cfg = sep_emac_read(MAC_CTRL);
-	DBOUT("After mac_cfg=%d\n",mac_cfg);
-	
-	return;
+    mac_cfg = sep_emac_read(MAC_CTRL);
+    DBOUT("After mac_cfg=%d\n",mac_cfg);
+
+    return;
 }
 
 static rt_err_t rt_dm9161_open(rt_device_t dev, rt_uint16_t oflag);
@@ -350,53 +346,53 @@ static rt_err_t rt_dm9161_open(rt_device_t dev, rt_uint16_t oflag);
 /* initialize the interface */
 static rt_err_t rt_dm9161_init(rt_device_t dev)
 {
-	unsigned int phyid1, phyid2;
-	int detected = -1;
-	unsigned long phy_id;
-	unsigned short phy_address = 0;
+    unsigned int phyid1, phyid2;
+    int detected = -1;
+    unsigned long phy_id;
+    unsigned short phy_address = 0;
 
-	while ((detected != 0) && (phy_address < 32)) 
-	{
-		/* Read the PHY ID registers */
-		enable_mdi();
-		read_phy(phy_address, MII_PHYSID1, &phyid1);
-		read_phy(phy_address, MII_PHYSID2, &phyid2);
-	
-		disable_mdi();
+    while ((detected != 0) && (phy_address < 32))
+    {
+        /* Read the PHY ID registers */
+        enable_mdi();
+        read_phy(phy_address, MII_PHYSID1, &phyid1);
+        read_phy(phy_address, MII_PHYSID2, &phyid2);
 
-		phy_id = (phyid1 << 16) | (phyid2 & 0xfff0);
-		switch (phy_id) 
-		{
-			case MII_DM9161_ID:		/* Davicom 9161: PHY_ID1 = 0x181, PHY_ID2 = B881 */
-			case MII_DM9161A_ID:		/* Davicom 9161A: PHY_ID1 = 0x181, PHY_ID2 = B8A0 */
-			case MII_RTL8201_ID:		/* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */
-			case MII_BCM5221_ID:		/* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */
-			case MII_DP83847_ID:		/* National Semiconductor DP83847:  */
-			case MII_AC101L_ID:		/* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */
-			case MII_KS8721_ID:		/* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */
-			{
-				enable_mdi();
-				#warning SHOULD SET MAC ADDR
-				//get_mac_address(dev);		/* Get ethernet address and store it in dev->dev_addr */
-				update_mac_address();	/* Program ethernet address into MAC */
-			
-				//ùϣĴȽϵǰȺַȫ˫CRCУ飬֡
-				sep_emac_write(MAC_CTRL, 0xa413);
-				#warning SHOULD DETERMIN LINK SPEED
-				update_link_speed(phy_address);
-				dm9161_device.phy_addr = phy_address;
-				disable_mdi();
-				break;
-			}
-				
-		}
+        disable_mdi();
 
-		phy_address++;
-	}
+        phy_id = (phyid1 << 16) | (phyid2 & 0xfff0);
+        switch (phy_id)
+        {
+            case MII_DM9161_ID:     /* Davicom 9161: PHY_ID1 = 0x181, PHY_ID2 = B881 */
+            case MII_DM9161A_ID:        /* Davicom 9161A: PHY_ID1 = 0x181, PHY_ID2 = B8A0 */
+            case MII_RTL8201_ID:        /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */
+            case MII_BCM5221_ID:        /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */
+            case MII_DP83847_ID:        /* National Semiconductor DP83847:  */
+            case MII_AC101L_ID:     /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */
+            case MII_KS8721_ID:     /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */
+            {
+                enable_mdi();
+                #warning SHOULD SET MAC ADDR
+                //get_mac_address(dev);     /* Get ethernet address and store it in dev->dev_addr */
+                update_mac_address();   /* Program ethernet address into MAC */
 
-	rt_dm9161_open(dev,0);
+                //用哈希寄存器比较当前群播地址，全双工，添加CRC校验，短数据帧进行填充
+                sep_emac_write(MAC_CTRL, 0xa413);
+                #warning SHOULD DETERMIN LINK SPEED
+                update_link_speed(phy_address);
+                dm9161_device.phy_addr = phy_address;
+                disable_mdi();
+                break;
+            }
 
-	return RT_EOK;
+        }
+
+        phy_address++;
+    }
+
+    rt_dm9161_open(dev,0);
+
+    return RT_EOK;
 }
 
 /* ................................ MAC ................................ */
@@ -406,300 +402,300 @@ static rt_err_t rt_dm9161_init(rt_device_t dev)
  */
 static void sepether_start(void)
 {
-	int i;
-	unsigned int tempaddr;
- 
-	sep_emac_write(MAC_TXBD_NUM,MAX_TX_DESCR);
+    int i;
+    unsigned int tempaddr;
 
-	//ʼͺͽ
-	for (i = 0; i < MAX_TX_DESCR; i++)
-	{
-		tempaddr=(MAC_TX_BD+i*8);
-		sep_emac_write(tempaddr,0);
-		tempaddr=(MAC_TX_BD+i*8+4);
-		sep_emac_write(tempaddr,0);
-	}
-	for (i = 0; i < MAX_RX_DESCR; i++)
-	{
-		tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8);
-		sep_emac_write(tempaddr,0);
-		tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8+4);
-		sep_emac_write(tempaddr,0);
-	}
+    sep_emac_write(MAC_TXBD_NUM,MAX_TX_DESCR);
 
-	for (i = 0; i < MAX_RX_DESCR; i++) 
-	{
-		tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8);
-		sep_emac_write(tempaddr,0xc000);
-		tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8+4);
-		sep_emac_write(tempaddr,ESRAM_BASE+ MAX_TX_DESCR*0x600+i*0x600);
-	}
+    //初始化发送和接收描述符
+    for (i = 0; i < MAX_TX_DESCR; i++)
+    {
+        tempaddr=(MAC_TX_BD+i*8);
+        sep_emac_write(tempaddr,0);
+        tempaddr=(MAC_TX_BD+i*8+4);
+        sep_emac_write(tempaddr,0);
+    }
+    for (i = 0; i < MAX_RX_DESCR; i++)
+    {
+        tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8);
+        sep_emac_write(tempaddr,0);
+        tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8+4);
+        sep_emac_write(tempaddr,0);
+    }
 
-	/* Set the Wrap bit on the last descriptor */
-	tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8-8);
-	sep_emac_write(tempaddr,0xe000);
+    for (i = 0; i < MAX_RX_DESCR; i++)
+    {
+        tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8);
+        sep_emac_write(tempaddr,0xc000);
+        tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8+4);
+        sep_emac_write(tempaddr,ESRAM_BASE+ MAX_TX_DESCR*0x600+i*0x600);
+    }
 
-	for (i = 0; i < MAX_TX_DESCR; i++) 
-	{
-		tempaddr=(MAC_TX_BD+i*8);
-		sep_emac_write(tempaddr,0x0);
-		tempaddr=(MAC_TX_BD+i*8+4);
-		sep_emac_write(tempaddr,ESRAM_BASE+i*0x600);
-	}
-	
-	return;
+    /* Set the Wrap bit on the last descriptor */
+    tempaddr=(MAC_TX_BD + MAX_TX_DESCR*8+i*8-8);
+    sep_emac_write(tempaddr,0xe000);
+
+    for (i = 0; i < MAX_TX_DESCR; i++)
+    {
+        tempaddr=(MAC_TX_BD+i*8);
+        sep_emac_write(tempaddr,0x0);
+        tempaddr=(MAC_TX_BD+i*8+4);
+        sep_emac_write(tempaddr,ESRAM_BASE+i*0x600);
+    }
+
+    return;
 }
 
 static rt_err_t rt_dm9161_open(rt_device_t dev, rt_uint16_t oflag)
 {
-	unsigned int dsintr;
+    unsigned int dsintr;
 
-	enable_mdi();
-	mask_irq(28);
+    enable_mdi();
+    mask_irq(28);
 
-	sep_emac_write(MAC_INTMASK,0x0);  //ж
+    sep_emac_write(MAC_INTMASK,0x0);  //首先屏蔽中断
 
-	sepether_start();
+    sepether_start();
 
-	/* Enable PHY interrupt */
-	*(volatile unsigned long*)GPIO_PORTA_DIR |= 0x0080 ;          //1 stands for in
-	*(volatile unsigned long*)GPIO_PORTA_SEL |= 0x0080 ;       //for common use
-	*(volatile unsigned long*)GPIO_PORTA_INCTL |= 0x0080;      //ж뷽ʽ
-	*(volatile unsigned long*)GPIO_PORTA_INTRCTL |= (0x3UL<<14);    //жΪ͵ƽⷢ
-	*(volatile unsigned long*)GPIO_PORTA_INTRCLR |= 0x0080;    //ж
-	*(volatile unsigned long*)GPIO_PORTA_INTRCLR = 0x0000;          //ж
+    /* Enable PHY interrupt */
+    *(volatile unsigned long*)GPIO_PORTA_DIR |= 0x0080 ;          //1 stands for in
+    *(volatile unsigned long*)GPIO_PORTA_SEL |= 0x0080 ;       //for common use
+    *(volatile unsigned long*)GPIO_PORTA_INCTL |= 0x0080;      //中断输入方式
+    *(volatile unsigned long*)GPIO_PORTA_INTRCTL |= (0x3UL<<14);    //中断类型为低电平解发
+    *(volatile unsigned long*)GPIO_PORTA_INTRCLR |= 0x0080;    //清除中断
+    *(volatile unsigned long*)GPIO_PORTA_INTRCLR = 0x0000;          //清除中断
 
-	rt_hw_interrupt_install(INTSRC_MAC, rt_dm9161_isr, RT_NULL, "EMAC");
-	enable_irq(INTSRC_EXINT7);
+    rt_hw_interrupt_install(INTSRC_MAC, rt_dm9161_isr, RT_NULL, "EMAC");
+    enable_irq(INTSRC_EXINT7);
 
 
-	read_phy(dm9161_device.phy_addr, MII_DSINTR_REG, &dsintr);
-	dsintr = dsintr & ~0xf00;		/* clear bits 8..11 */
-	write_phy(dm9161_device.phy_addr, MII_DSINTR_REG, dsintr);
+    read_phy(dm9161_device.phy_addr, MII_DSINTR_REG, &dsintr);
+    dsintr = dsintr & ~0xf00;       /* clear bits 8..11 */
+    write_phy(dm9161_device.phy_addr, MII_DSINTR_REG, dsintr);
 
-	update_link_speed(dm9161_device.phy_addr);
-	
-	
-	/************************************************************************************/
-	/* Enable MAC interrupts */
-	sep_emac_write(MAC_INTMASK,0xff);  //openж
-	sep_emac_write(MAC_INTSRC,0xff);   //clear all mac irq
-	unmask_irq(28);
-	disable_mdi();
-	
-	rt_kprintf("SEP4020 ethernet interface open!\n\r");
+    update_link_speed(dm9161_device.phy_addr);
 
-	return RT_EOK;
+
+    /************************************************************************************/
+    /* Enable MAC interrupts */
+    sep_emac_write(MAC_INTMASK,0xff);  //open中断
+    sep_emac_write(MAC_INTSRC,0xff);   //clear all mac irq
+    unmask_irq(28);
+    disable_mdi();
+
+    rt_kprintf("SEP4020 ethernet interface open!\n\r");
+
+    return RT_EOK;
 }
 
 static rt_err_t rt_dm9161_close(rt_device_t dev)
 {
-	rt_kprintf("SEP4020 ethernet interface close!\n\r");
-	
-	/* Disable Receiver and Transmitter */
-	disable_mdi();
-	#warning disable ether;
-	
-//	INT_ENABLE(28);
-	/* Disable PHY interrupt */
-//	disable_phyirq(dev);
-	
-	/* Disable MAC interrupts */
-	sep_emac_write(MAC_INTMASK,0);  //ж
+    rt_kprintf("SEP4020 ethernet interface close!\n\r");
 
-//	INT_DISABLE(28);
-	
-	return RT_EOK;
+    /* Disable Receiver and Transmitter */
+    disable_mdi();
+    #warning disable ether;
+
+//  INT_ENABLE(28);
+    /* Disable PHY interrupt */
+//  disable_phyirq(dev);
+
+    /* Disable MAC interrupts */
+    sep_emac_write(MAC_INTMASK,0);  //屏蔽中断
+
+//  INT_DISABLE(28);
+
+    return RT_EOK;
 }
 
 static rt_size_t rt_dm9161_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
 {
-	rt_set_errno(-RT_ENOSYS);
+    rt_set_errno(-RT_ENOSYS);
 
-	return 0;
+    return 0;
 }
 
 static rt_size_t rt_dm9161_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
 {
-	rt_set_errno(-RT_ENOSYS);
+    rt_set_errno(-RT_ENOSYS);
 
-	return 0;
+    return 0;
 }
 
 static rt_err_t rt_dm9161_control(rt_device_t dev, int cmd, void *args)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 /* ethernet device interface */
 /* transmit packet. */
 rt_err_t rt_dm9161_tx( rt_device_t dev, struct pbuf* p)
 {
-	rt_uint8_t i;
-	rt_uint32_t length = 0;
-	struct pbuf *q;
-	unsigned long  address;
-	unsigned long tmp_tx_bd;
+    rt_uint8_t i;
+    rt_uint32_t length = 0;
+    struct pbuf *q;
+    unsigned long  address;
+    unsigned long tmp_tx_bd;
 
-	/* lock DM9000 device */
-//	rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
+    /* lock DM9000 device */
+//  rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
 
-	/* disable dm9000a interrupt */
-	#warning SHOULD DISABLE INTEERUPT?
+    /* disable dm9000a interrupt */
+    #warning SHOULD DISABLE INTEERUPT?
 
-	/*Search for available BD*/
-	for (i = 0;ipayload,q->len);
-		length += q->len;
-		q = q->next;
-	}
+    /*Search for available BD*/
+    for (i = 0;ipayload,q->len);
+        length += q->len;
+        q = q->next;
+    }
 
-	length = length << 16;
+    #warning SHOULD NOTICE IT'S LENGTH
 
-	if (i == MAX_TX_DESCR - 1)
-		length |= 0xb800;
-	else 
-		length |= 0x9800;
+    length = length << 16;
 
-	address = (MAC_TX_BD + i*8);
-	dm9161_device.tx_index = i;
-	sep_emac_write(address,length);
+    if (i == MAX_TX_DESCR - 1)
+        length |= 0xb800;
+    else
+        length |= 0x9800;
 
-	//wait for tranfer complete
-	while(!(sep_emac_read(address)&0x8000));
+    address = (MAC_TX_BD + i*8);
+    dm9161_device.tx_index = i;
+    sep_emac_write(address,length);
 
-	/* unlock DM9000 device */
+    //wait for tranfer complete
+    while(!(sep_emac_read(address)&0x8000));
+
+    /* unlock DM9000 device */
 //    rt_sem_release(&sem_lock);
 
-	/* wait ack */
+    /* wait ack */
 //    rt_sem_take(&sem_ack, RT_WAITING_FOREVER);
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 /* reception packet. */
 struct pbuf *rt_dm9161_rx(rt_device_t dev)
 {
-	unsigned int temp_rx_bd,address;
-	rt_uint32_t i = 0;
-	rt_uint32_t length;
-	unsigned char *p_recv;
-	struct pbuf* p = RT_NULL;
+    unsigned int temp_rx_bd,address;
+    rt_uint32_t i = 0;
+    rt_uint32_t length;
+    unsigned char *p_recv;
+    struct pbuf* p = RT_NULL;
 
-	/* lock DM9000 device */
-	rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
+    /* lock DM9000 device */
+    rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
 
-	while (1)
-	{
-	
-		address = MAC_TX_BD +  (MAX_TX_DESCR + i) * 8;
-		temp_rx_bd = sep_emac_read(address);
-	
-		if (!(temp_rx_bd & 0x8000))
-		{
-			length = temp_rx_bd;
-			length = length >> 16;
+    while (1)
+    {
 
-			p_recv = (unsigned char *)(ESRAM_BASE + (MAX_TX_DESCR + i) * 0x600);
-			p = pbuf_alloc(PBUF_LINK,length,PBUF_RAM);
-			if (p != RT_NULL)
-			{
-				struct pbuf *q;
-				rt_int32_t len;
+        address = MAC_TX_BD +  (MAX_TX_DESCR + i) * 8;
+        temp_rx_bd = sep_emac_read(address);
 
-				for (q = p; q != RT_NULL; q = q->next)
-				{
-					rt_memcpy((rt_uint8_t *)(q->payload),p_recv,q->len);
-				}
-			}
-			else
-			{
-				 rt_kprintf("Droping %d packet \n",length);
-			}
+        if (!(temp_rx_bd & 0x8000))
+        {
+            length = temp_rx_bd;
+            length = length >> 16;
 
-			if(i == (MAX_RX_DESCR-1))
-			{
-				sep_emac_write(address,0xe000);
-				i = 0;
-			}
-			else
-			{
-				sep_emac_write(address,0xc000);
-				i++;
-			}
-		}
-		else
-			break;
-	}
+            p_recv = (unsigned char *)(ESRAM_BASE + (MAX_TX_DESCR + i) * 0x600);
+            p = pbuf_alloc(PBUF_LINK,length,PBUF_RAM);
+            if (p != RT_NULL)
+            {
+                struct pbuf *q;
+                rt_int32_t len;
 
-	rt_sem_release(&sem_lock);
+                for (q = p; q != RT_NULL; q = q->next)
+                {
+                    rt_memcpy((rt_uint8_t *)(q->payload),p_recv,q->len);
+                }
+            }
+            else
+            {
+                 rt_kprintf("Droping %d packet \n",length);
+            }
 
-	return p;
+            if(i == (MAX_RX_DESCR-1))
+            {
+                sep_emac_write(address,0xe000);
+                i = 0;
+            }
+            else
+            {
+                sep_emac_write(address,0xc000);
+                i++;
+            }
+        }
+        else
+            break;
+    }
+
+    rt_sem_release(&sem_lock);
+
+    return p;
 }
 
 void rt_hw_dm9161_init()
 {
-	rt_sem_init(&sem_ack, "tx_ack", 1, RT_IPC_FLAG_FIFO);
-	rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
+    rt_sem_init(&sem_ack, "tx_ack", 1, RT_IPC_FLAG_FIFO);
+    rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
 
-	dm9161_device.type  = TYPE_DM9161;
-	dm9161_device.mode	= DM9161_AUTO;
-	dm9161_device.packet_cnt = 0;
-	dm9161_device.queue_packet_len = 0;
+    dm9161_device.type  = TYPE_DM9161;
+    dm9161_device.mode  = DM9161_AUTO;
+    dm9161_device.packet_cnt = 0;
+    dm9161_device.queue_packet_len = 0;
 
-	/*
-	 * SRAM Tx/Rx pointer automatically return to start address,
-	 * Packet Transmitted, Packet Received
-	 */
-	#warning NOTICE:
-	//dm9161_device.imr_all = IMR_PAR | IMR_PTM | IMR_PRM;
+    /*
+     * SRAM Tx/Rx pointer automatically return to start address,
+     * Packet Transmitted, Packet Received
+     */
+    #warning NOTICE:
+    //dm9161_device.imr_all = IMR_PAR | IMR_PTM | IMR_PRM;
 
-	dm9161_device.dev_addr[0] = 0x01;
-	dm9161_device.dev_addr[1] = 0x60;
-	dm9161_device.dev_addr[2] = 0x6E;
-	dm9161_device.dev_addr[3] = 0x11;
-	dm9161_device.dev_addr[4] = 0x02;
-	dm9161_device.dev_addr[5] = 0x0F;
+    dm9161_device.dev_addr[0] = 0x01;
+    dm9161_device.dev_addr[1] = 0x60;
+    dm9161_device.dev_addr[2] = 0x6E;
+    dm9161_device.dev_addr[3] = 0x11;
+    dm9161_device.dev_addr[4] = 0x02;
+    dm9161_device.dev_addr[5] = 0x0F;
 
-	dm9161_device.parent.parent.init       = rt_dm9161_init;
-	dm9161_device.parent.parent.open       = rt_dm9161_open;
-	dm9161_device.parent.parent.close      = rt_dm9161_close;
-	dm9161_device.parent.parent.read       = rt_dm9161_read;
-	dm9161_device.parent.parent.write      = rt_dm9161_write;
-	dm9161_device.parent.parent.control    = rt_dm9161_control;
-	dm9161_device.parent.parent.user_data  = RT_NULL;
+    dm9161_device.parent.parent.init       = rt_dm9161_init;
+    dm9161_device.parent.parent.open       = rt_dm9161_open;
+    dm9161_device.parent.parent.close      = rt_dm9161_close;
+    dm9161_device.parent.parent.read       = rt_dm9161_read;
+    dm9161_device.parent.parent.write      = rt_dm9161_write;
+    dm9161_device.parent.parent.control    = rt_dm9161_control;
+    dm9161_device.parent.parent.user_data  = RT_NULL;
 
-	dm9161_device.parent.eth_rx     = rt_dm9161_rx;
-	dm9161_device.parent.eth_tx     = rt_dm9161_tx;
+    dm9161_device.parent.eth_rx     = rt_dm9161_rx;
+    dm9161_device.parent.eth_tx     = rt_dm9161_tx;
 
-	eth_device_init(&(dm9161_device.parent), "e0");
+    eth_device_init(&(dm9161_device.parent), "e0");
 
-	/* instal interrupt */
-	#warning TODO
-	//rt_hw_interrupt_install(INTEINT4_7, rt_dm9161_isr, RT_NULL);
-	//rt_hw_interrupt_umask(INTEINT4_7);
+    /* instal interrupt */
+    #warning TODO
+    //rt_hw_interrupt_install(INTEINT4_7, rt_dm9161_isr, RT_NULL);
+    //rt_hw_interrupt_umask(INTEINT4_7);
 }
 
 void dm9161a(void)
diff --git a/bsp/mini4020/drivers/dm9161.h b/bsp/mini4020/drivers/dm9161.h
index 620f8653bc..5b63508aaa 100644
--- a/bsp/mini4020/drivers/dm9161.h
+++ b/bsp/mini4020/drivers/dm9161.h
@@ -1,11 +1,7 @@
 /*
- * File      : dm9161.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -21,15 +17,15 @@
  /* Davicom 9161 PHY */
  #define MII_DM9161_ID   0x0181b880
  #define MII_DM9161A_ID  0x0181b8a0
-  
+
  /* Davicom specific registers */
  #define MII_DSCR_REG    16
  #define MII_DSCSR_REG   17
  #define MII_DSINTR_REG  21
-  
+
   /* Intel LXT971A PHY */
  #define MII_LXT971A_ID  0x001378E0
-  
+
   /* Intel specific registers */
  #define MII_ISINTE_REG  18
  #define MII_ISINTS_REG  19
@@ -37,41 +33,41 @@
 
  /* Realtek RTL8201 PHY */
  #define MII_RTL8201_ID  0x00008200
-  
+
  /* Broadcom BCM5221 PHY */
  #define MII_BCM5221_ID  0x004061e0
-  
+
  /* Broadcom specific registers */
  #define MII_BCMINTR_REG 26
-  
+
   /* National Semiconductor DP83847 */
  #define MII_DP83847_ID  0x20005c30
- 
+
   /* Altima AC101L PHY */
  #define MII_AC101L_ID   0x00225520
-  
+
  /* Micrel KS8721 PHY */
  #define MII_KS8721_ID   0x00221610
- 
+
  /* ........................................................................ */
-  
+
  #define MAX_RBUFF_SZ    0x600           /* 1518 rounded up */
  #define MAX_RX_DESCR    20           /* max number of receive buffers */
-  
+
  #define MAX_TBUFF_SZ    0x600           /* 1518 rounded up */
  #define MAX_TX_DESCR    20               /* max number of receive buffers */
-  
+
  #define EMAC_DESC_DONE  0x00000001      /* bit for if DMA is done */
  #define EMAC_DESC_WRAP  0x00000002      /* bit for wrap */
-  
+
  #define EMAC_BROADCAST  0x80000000      /* broadcast address */
  #define EMAC_MULTICAST  0x40000000      /* multicast address */
  #define EMAC_UNICAST    0x20000000      /* unicast address */
- 
-#define DM9161_inb(r) 		(*(volatile rt_uint8_t  *)r)
-#define DM9161_outb(r, d) 	(*(volatile rt_uint8_t  *)r = d)
-#define DM9161_inw(r) 		(*(volatile rt_uint16_t *)r)
-#define DM9161_outw(r, d) 	(*(volatile rt_uint16_t *)r = d)
+
+#define DM9161_inb(r)       (*(volatile rt_uint8_t  *)r)
+#define DM9161_outb(r, d)   (*(volatile rt_uint8_t  *)r = d)
+#define DM9161_inw(r)       (*(volatile rt_uint16_t *)r)
+#define DM9161_outw(r, d)   (*(volatile rt_uint16_t *)r = d)
 
 void rt_hw_dm9616_init(void);
 
diff --git a/bsp/mini4020/drivers/lcd.c b/bsp/mini4020/drivers/lcd.c
index f9799d9ef7..c325764953 100644
--- a/bsp/mini4020/drivers/lcd.c
+++ b/bsp/mini4020/drivers/lcd.c
@@ -1,11 +1,7 @@
 /*
- * File      : lcd.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -56,7 +52,7 @@ void radio_rtgui_init(void)
     _rtgui_lcd_driver.bits_per_pixel  = 16;
     _rtgui_lcd_driver.width           = 320;
     _rtgui_lcd_driver.height          = 240;
-        
+
     _rtgui_lcd_driver.ops = &_rtgui_graphic_driver_ops;
 
     //_rtgui_lcd_driver.screen_update   = lcd_update;
@@ -67,7 +63,7 @@ void radio_rtgui_init(void)
     rt_memset((char*)pVideoBuffer,0xff,320*240*2);
     //rt_memcpy((char*)pVideoBuffer,pic,320*240*2);  //TESTING IMAGE
 
-    //˴
+    //此处待修正
     /* add lcd driver into graphic driver */
     // rtgui_graphic_driver_add(&_rtgui_lcd_driver);
 }
diff --git a/bsp/mini4020/drivers/lcdc.c b/bsp/mini4020/drivers/lcdc.c
index d468eebd91..4be34518ba 100644
--- a/bsp/mini4020/drivers/lcdc.c
+++ b/bsp/mini4020/drivers/lcdc.c
@@ -1,11 +1,7 @@
 /*
- * File      : lcdc.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -23,20 +19,20 @@ rt_err_t sep4020_lcd_init(void)
 {
     pVideoBuffer =(unsigned long)rt_malloc(LCDWIDTH * LCDHEIGHT * 2);
 
-    *(RP)GPIO_PORTC_SEL  |= 0X0008;      //Portc8Ϊͨÿ
-    *(RP)GPIO_PORTC_DIR  &= (~0X0008);   //Portc8Ϊ
-    *(RP)GPIO_PORTC_DATA |= 0X0008;      //Portc8ߵƽ
+    *(RP)GPIO_PORTC_SEL  |= 0X0008;      //Portc8设置为通用口
+    *(RP)GPIO_PORTC_DIR  &= (~0X0008);   //Portc8设置为输出
+    *(RP)GPIO_PORTC_DATA |= 0X0008;      //Portc8输出高电平
 
-    writel(0x00000000,LCDC_LECR);     //LCDC
-    writel(pVideoBuffer,LCDC_SSA);    //lcd֡ʼַ
+    writel(0x00000000,LCDC_LECR);     //禁用LCDC
+    writel(pVideoBuffer,LCDC_SSA);    //lcd数据帧的起始地址
     writel(YMAX | XMAX,LCDC_SIZE);
     writel(TFT|COLOR|PBSIZE|BPIX|PIXPOL|FLMPOL|LPPOL|CLKPOL|OEPOL|END_SEL|ACD_SEL|ACD|PCD,LCDC_PCR);
     writel(H_WIDTH|H_WAIT_1|H_WAIT_2,LCDC_HCR);
     writel(V_WIDTH|PASS_FRAME_WAIT|V_WAIT_1|V_WAIT_2,LCDC_VCR);
     writel(SCR|CC_EN|PW,LCDC_PWMR);
     writel(BL|HM|TM,LCDC_DMACR);
-    writel(0x00000001,LCDC_LECR);         //ʹLCDC
-    writel(0x00000000,LCDC_LCDISREN);     //жڼ֡һһʱãLCD֮һʱ
+    writel(0x00000001,LCDC_LECR);         //使能LCDC
+    writel(0x00000000,LCDC_LCDISREN);     //中断在加载帧的最后一个或第一个数据时设置，到LCD之间会有一个延时
 
     return RT_EOK;
 }
diff --git a/bsp/mini4020/drivers/lcdc.h b/bsp/mini4020/drivers/lcdc.h
index 4b361e502c..39a88e82e0 100644
--- a/bsp/mini4020/drivers/lcdc.h
+++ b/bsp/mini4020/drivers/lcdc.h
@@ -1,11 +1,7 @@
 /*
- * File      : lcdc.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -29,40 +25,40 @@
 
 //Macro for PCR register setting
 #define TFT   ((U32)1 << 31)
-#define COLOR   (1 << 30)   //1Ϊɫ.
+#define COLOR   (1 << 30)   //1为色彩.
 #define PBSIZE   (0 << 28)
-#define BPIX     (4 << 25)   //洢һضӦ16bit
-#define PIXPOL   (0 << 24)   //ؼԡصļ,Ч	   //0<<24
-#define FLMPOL   (1 << 23)   //б־ԡб־ļ,Ч.
-#define LPPOL   (1 << 22)   //弫ԡźŵļ,Ч.
-#define CLKPOL   (0 << 21)   //LCD λʱӼԡLCD λʱӵЧصļ,½Ч.
-#define OEPOL   (1 << 20)   //ʹܼԡʹźŵļ,Ч.
-#define END_SEL (0 << 18)   //ӡڰʽѡ,Сӡڰ.
-#define ACD_SEL (0 << 15)   //ACDʱԴѡѡ任ʱ,ʹFLM ΪACD ʱ
-#define ACD   (0 << 8 )   //ģʽ.
+#define BPIX     (4 << 25)   //存储器中一个像素对应16bit
+#define PIXPOL   (0 << 24)   //像素极性—设置像素的极性,高有效    //0<<24
+#define FLMPOL   (1 << 23)   //首行标志极性—设置首行标志的极性,低有效.
+#define LPPOL   (1 << 22)   //行脉冲极性—设置行脉冲信号的极性,低有效.
+#define CLKPOL   (0 << 21)   //LCD 移位时钟极性—设置LCD 移位时钟的有效沿的极性,下降延有效.
+#define OEPOL   (1 << 20)   //输出使能极性—设置输出使能信号的极性,高有效.
+#define END_SEL (0 << 18)   //印第安格式选择,小印第安.
+#define ACD_SEL (0 << 15)   //ACD时钟源选择—选择晶向变换计数器的时钟,使用FLM 作为ACD 计数时钟
+#define ACD   (0 << 8 )   //被动模式.
 #define PCD   (10)
 
-//Macro for HCR regiter setting //ˮƽüĴ.
+//Macro for HCR regiter setting //水平配置寄存器.
 #define H_WIDTH ((U32)46 << 26)
 #define H_WAIT_1 (20 << 8)
 #define H_WAIT_2 (20)
 
-//Macro for VCR register setting //ֱüĴ.
+//Macro for VCR register setting //垂直配置寄存器.
 #define V_WIDTH ((U32)10 << 26)
 #define PASS_FRAME_WAIT (0 <<16)
 #define V_WAIT_1 (3 << 8)
 #define V_WAIT_2 (3)
 
 //Macro for LGPR register setting
-#define GRAY   (4)    //Ҷȵȼ.
+#define GRAY   (4)    //灰度等级.
 
 //Macro for PWMR register setting
-#define SCR   (0 << 9)   //ʱԴѡ..
-#define CC_EN (0 << 8)   //Աȶȿʹ,.
-#define PW   (64)    //Ŀ,
+#define SCR   (0 << 9)   //时钟源选择.行脉冲.
+#define CC_EN (0 << 8)   //对比度控制使能,关.
+#define PW   (64)    //输出脉冲数目,
 
 //Macro for DMACR register setting
-#define BL   ((U32)1 << 31)   //̶.
+#define BL   ((U32)1 << 31)   //固定长度.
 #define HM   (7 << 16)
 #define TM   (3)
 
diff --git a/bsp/mini4020/drivers/mii.h b/bsp/mini4020/drivers/mii.h
index 617550bfd9..b58d8bf56f 100644
--- a/bsp/mini4020/drivers/mii.h
+++ b/bsp/mini4020/drivers/mii.h
@@ -1,11 +1,7 @@
 /*
- * File      : mii.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -25,7 +21,7 @@
 #define MII_EXPANSION       0x06        /* Expansion register          */
 #define MII_CTRL1000        0x09        /* 1000BASE-T control          */
 #define MII_STAT1000        0x0a        /* 1000BASE-T status           */
-#define MII_ESTATUS	    0x0f	/* Extended Status */
+#define MII_ESTATUS     0x0f    /* Extended Status */
 #define MII_DCOUNTER        0x12        /* Disconnect counter          */
 #define MII_FCSCOUNTER      0x13        /* False carrier counter       */
 #define MII_NWAYTEST        0x14        /* N-way auto-neg test reg     */
@@ -40,7 +36,7 @@
 
 /* Basic mode control register. */
 #define BMCR_RESV               0x003f  /* Unused...                   */
-#define BMCR_SPEED1000		0x0040  /* MSB of Speed (1000)         */
+#define BMCR_SPEED1000      0x0040  /* MSB of Speed (1000)         */
 #define BMCR_CTST               0x0080  /* Collision test              */
 #define BMCR_FULLDPLX           0x0100  /* Full duplex                 */
 #define BMCR_ANRESTART          0x0200  /* Auto negotiation restart    */
@@ -59,9 +55,9 @@
 #define BMSR_RFAULT             0x0010  /* Remote fault detected       */
 #define BMSR_ANEGCOMPLETE       0x0020  /* Auto-negotiation complete   */
 #define BMSR_RESV               0x00c0  /* Unused...                   */
-#define BMSR_ESTATEN		0x0100	/* Extended Status in R15 */
-#define BMSR_100FULL2		0x0200	/* Can do 100BASE-T2 HDX */
-#define BMSR_100HALF2		0x0400	/* Can do 100BASE-T2 FDX */
+#define BMSR_ESTATEN        0x0100  /* Extended Status in R15 */
+#define BMSR_100FULL2       0x0200  /* Can do 100BASE-T2 HDX */
+#define BMSR_100HALF2       0x0400  /* Can do 100BASE-T2 FDX */
 #define BMSR_10HALF             0x0800  /* Can do 10mbps, half-duplex  */
 #define BMSR_10FULL             0x1000  /* Can do 10mbps, full-duplex  */
 #define BMSR_100HALF            0x2000  /* Can do 100mbps, half-duplex */
@@ -88,7 +84,7 @@
 #define ADVERTISE_NPAGE         0x8000  /* Next page bit               */
 
 #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
-			ADVERTISE_CSMA)
+            ADVERTISE_CSMA)
 #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
                        ADVERTISE_100HALF | ADVERTISE_100FULL)
 
@@ -110,8 +106,8 @@
 #define LPA_LPACK               0x4000  /* Link partner acked us       */
 #define LPA_NPAGE               0x8000  /* Next page bit               */
 
-#define LPA_DUPLEX		(LPA_10FULL | LPA_100FULL)
-#define LPA_100			(LPA_100FULL | LPA_100HALF | LPA_100BASE4)
+#define LPA_DUPLEX      (LPA_10FULL | LPA_100FULL)
+#define LPA_100         (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
 
 /* Expansion register for auto-negotiation. */
 #define EXPANSION_NWAY          0x0001  /* Can do N-way auto-nego      */
@@ -121,8 +117,8 @@
 #define EXPANSION_MFAULTS       0x0010  /* Multiple faults detected    */
 #define EXPANSION_RESV          0xffe0  /* Unused...                   */
 
-#define ESTATUS_1000_TFULL	0x2000	/* Can do 1000BT Full */
-#define ESTATUS_1000_THALF	0x1000	/* Can do 1000BT Half */
+#define ESTATUS_1000_TFULL  0x2000  /* Can do 1000BT Full */
+#define ESTATUS_1000_THALF  0x1000  /* Can do 1000BT Half */
 
 /* N-way test register. */
 #define NWAYTEST_RESV1          0x00ff  /* Unused...                   */
diff --git a/bsp/mini4020/drivers/sdcard.c b/bsp/mini4020/drivers/sdcard.c
index 78c1306a0d..52c3b5cd82 100644
--- a/bsp/mini4020/drivers/sdcard.c
+++ b/bsp/mini4020/drivers/sdcard.c
@@ -1,11 +1,7 @@
 /*
- * File      : sdcard.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2007 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author      Notes
@@ -62,7 +58,7 @@ static void delay(U32 j)
 
     for (i = 0; i < j; i++)
     {
-    	/* nothing */
+        /* nothing */
     }
 }
 
diff --git a/bsp/mini4020/drivers/sdcard.h b/bsp/mini4020/drivers/sdcard.h
index c8a4acf1a1..6f2db415d0 100644
--- a/bsp/mini4020/drivers/sdcard.h
+++ b/bsp/mini4020/drivers/sdcard.h
@@ -1,11 +1,7 @@
 /*
- * File      : sdcard.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/nios_ii/application.c b/bsp/nios_ii/application.c
index 22037c8f9a..a8422dcc46 100644
--- a/bsp/nios_ii/application.c
+++ b/bsp/nios_ii/application.c
@@ -1,11 +1,7 @@
 /*
- * File      : application.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2011, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/nios_ii/board.c b/bsp/nios_ii/board.c
index 2614a25095..dfe0abc38e 100644
--- a/bsp/nios_ii/board.c
+++ b/bsp/nios_ii/board.c
@@ -1,11 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2011, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/nios_ii/board.h b/bsp/nios_ii/board.h
index d7c6d3540f..4953258665 100644
--- a/bsp/nios_ii/board.h
+++ b/bsp/nios_ii/board.h
@@ -1,11 +1,7 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2011, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/nios_ii/rtconfig.h b/bsp/nios_ii/rtconfig.h
index fcd3799846..6a7d9c7d33 100644
--- a/bsp/nios_ii/rtconfig.h
+++ b/bsp/nios_ii/rtconfig.h
@@ -6,17 +6,17 @@
 #define __RTTHREAD_CFG_H__
 
 /* RT_NAME_MAX*/
-#define RT_NAME_MAX	8
+#define RT_NAME_MAX 8
 
 /* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE	4
+#define RT_ALIGN_SIZE   4
 
 /* PRIORITY_MAX */
-#define RT_THREAD_PRIORITY_MAX	32
+#define RT_THREAD_PRIORITY_MAX  32
 
 /* Tick per Second */
 /* TIMER_TICKS_PER_SEC define in system.h */
-#define RT_TICK_PER_SECOND	TIMER_TICKS_PER_SEC
+#define RT_TICK_PER_SECOND  TIMER_TICKS_PER_SEC
 
 /* SECTION: RT_DEBUG */
 /* Thread Debug */
@@ -35,9 +35,9 @@
 
 /* Using Software Timer */
 /* #define RT_USING_TIMER_SOFT */
-#define RT_TIMER_THREAD_PRIO		4
-#define RT_TIMER_THREAD_STACK_SIZE	512
-#define RT_TIMER_TICK_PER_SECOND	10
+#define RT_TIMER_THREAD_PRIO        4
+#define RT_TIMER_THREAD_STACK_SIZE  512
+#define RT_TIMER_TICK_PER_SECOND    10
 
 /* SECTION: IPC */
 /* Using Semaphore*/
@@ -73,7 +73,7 @@
 /* SECTION: Console options */
 #define RT_USING_CONSOLE
 /* the buffer size of console*/
-#define RT_CONSOLEBUF_SIZE	128
+#define RT_CONSOLEBUF_SIZE  128
 
 #define RT_USING_NEWLIB
 
@@ -92,11 +92,11 @@
 #define RT_USING_DFS_ELMFAT
 
 /* the max number of mounted filesystem */
-#define DFS_FILESYSTEMS_MAX			2
-/* the max number of opened files 		*/
-#define DFS_FD_MAX					4
-/* the max number of cached sector 		*/
-#define DFS_CACHE_MAX_NUM   		4
+#define DFS_FILESYSTEMS_MAX         2
+/* the max number of opened files       */
+#define DFS_FD_MAX                  4
+/* the max number of cached sector      */
+#define DFS_CACHE_MAX_NUM           4
 
 /* SECTION: lwip, a lighwight TCP/IP protocol stack */
 //#define RT_USING_LWIP
@@ -110,37 +110,37 @@
 #define RT_LWIP_DNS
 
 /* the number of simulatenously active TCP connections*/
-#define RT_LWIP_TCP_PCB_NUM	5
+#define RT_LWIP_TCP_PCB_NUM 5
 
 /* Using DHCP */
 //#define RT_LWIP_DHCP
 
 /* ip address of target*/
-#define RT_LWIP_IPADDR0	192
-#define RT_LWIP_IPADDR1	168
-#define RT_LWIP_IPADDR2	1
-#define RT_LWIP_IPADDR3	30
+#define RT_LWIP_IPADDR0 192
+#define RT_LWIP_IPADDR1 168
+#define RT_LWIP_IPADDR2 1
+#define RT_LWIP_IPADDR3 30
 
 /* gateway address of target*/
-#define RT_LWIP_GWADDR0	192
-#define RT_LWIP_GWADDR1	168
-#define RT_LWIP_GWADDR2	1
-#define RT_LWIP_GWADDR3	1
+#define RT_LWIP_GWADDR0 192
+#define RT_LWIP_GWADDR1 168
+#define RT_LWIP_GWADDR2 1
+#define RT_LWIP_GWADDR3 1
 
 /* mask address of target*/
-#define RT_LWIP_MSKADDR0	255
-#define RT_LWIP_MSKADDR1	255
-#define RT_LWIP_MSKADDR2	255
-#define RT_LWIP_MSKADDR3	0
+#define RT_LWIP_MSKADDR0    255
+#define RT_LWIP_MSKADDR1    255
+#define RT_LWIP_MSKADDR2    255
+#define RT_LWIP_MSKADDR3    0
 
 /* tcp thread options */
-#define RT_LWIP_TCPTHREAD_PRIORITY		12
-#define RT_LWIP_TCPTHREAD_MBOX_SIZE		4
-#define RT_LWIP_TCPTHREAD_STACKSIZE		1024
+#define RT_LWIP_TCPTHREAD_PRIORITY      12
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE     4
+#define RT_LWIP_TCPTHREAD_STACKSIZE     1024
 
 /* ethernet if thread options */
-#define RT_LWIP_ETHTHREAD_PRIORITY		15
-#define RT_LWIP_ETHTHREAD_MBOX_SIZE		4
-#define RT_LWIP_ETHTHREAD_STACKSIZE		512
+#define RT_LWIP_ETHTHREAD_PRIORITY      15
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE     4
+#define RT_LWIP_ETHTHREAD_STACKSIZE     512
 
 #endif
diff --git a/bsp/nios_ii/startup.c b/bsp/nios_ii/startup.c
index e2bbaaa996..fd2f909aa2 100644
--- a/bsp/nios_ii/startup.c
+++ b/bsp/nios_ii/startup.c
@@ -1,11 +1,7 @@
 /*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2011, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/nios_ii/uart.c b/bsp/nios_ii/uart.c
index 65a22db34c..79c2dcc586 100644
--- a/bsp/nios_ii/uart.c
+++ b/bsp/nios_ii/uart.c
@@ -32,7 +32,7 @@ static rt_err_t rt_uart_init (rt_device_t dev)
 {
     set_baudrate(115200);
 
-    IOWR_ALTERA_AVALON_UART_CONTROL(RS232_BASE, 0x80);//жʹ
+    IOWR_ALTERA_AVALON_UART_CONTROL(RS232_BASE, 0x80);//接收中断使能
     IOWR_ALTERA_AVALON_UART_STATUS(RS232_BASE, 0x0); // clean status
 
     rx_put_index = 0;
@@ -99,17 +99,17 @@ void rt_hw_uart_init(void)
 {
     // init uart
     set_baudrate(115200);
-    IOWR_ALTERA_AVALON_UART_CONTROL(RS232_BASE, 0x80);//жʹ
+    IOWR_ALTERA_AVALON_UART_CONTROL(RS232_BASE, 0x80);//接收中断使能
     IOWR_ALTERA_AVALON_UART_STATUS(RS232_BASE, 0x0); // clean status
     alt_irq_register(RS232_IRQ, NULL, uart_isr);
 
     // register device
     uart_device.type = RT_Device_Class_Char;
     /* device interface */
-    uart_device.init 	    = rt_uart_init;
-    uart_device.open 	    = rt_uart_open;
+    uart_device.init        = rt_uart_init;
+    uart_device.open        = rt_uart_open;
     uart_device.close       = rt_uart_close;
-    uart_device.read 	    = rt_uart_read;
+    uart_device.read        = rt_uart_read;
     uart_device.write       = rt_uart_write;
     uart_device.control     = rt_uart_control;
 
diff --git a/bsp/nrf51822/Libraries/nrf51822/Include/compiler_abstraction.h b/bsp/nrf51822/Libraries/nrf51822/Include/compiler_abstraction.h
new file mode 100644
index 0000000000..c239fd11cd
--- /dev/null
+++ b/bsp/nrf51822/Libraries/nrf51822/Include/compiler_abstraction.h
@@ -0,0 +1,255 @@
+/*
+
+Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+   list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions and the following disclaimer in the
+   documentation and/or other materials provided with the distribution.
+
+3. Neither the name of Nordic Semiconductor ASA nor the names of its
+   contributors may be used to endorse or promote products derived from this
+   software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef _COMPILER_ABSTRACTION_H
+#define _COMPILER_ABSTRACTION_H
+
+/*lint ++flb "Enter library region" */
+
+#ifndef NRF_STRING_CONCATENATE_IMPL
+    #define NRF_STRING_CONCATENATE_IMPL(lhs, rhs) lhs ## rhs
+#endif
+#ifndef NRF_STRING_CONCATENATE
+    #define NRF_STRING_CONCATENATE(lhs, rhs) NRF_STRING_CONCATENATE_IMPL(lhs, rhs)
+#endif
+
+#if defined ( __CC_ARM )
+
+    #ifndef __ASM
+        #define __ASM               __asm
+    #endif
+
+    #ifndef __INLINE
+        #define __INLINE            __inline
+    #endif
+
+    #ifndef __WEAK
+        #define __WEAK              __weak
+    #endif
+
+    #ifndef __ALIGN
+        #define __ALIGN(n)          __align(n)
+    #endif
+
+    #ifndef __PACKED
+        #define __PACKED            __packed
+    #endif
+
+    #ifndef __UNUSED
+        #define __UNUSED            __attribute__((unused))
+    #endif
+
+    #define GET_SP()                __current_sp()
+
+    #ifndef NRF_STATIC_ASSERT
+        #define NRF_STATIC_ASSERT(cond, msg) \
+            ;enum { NRF_STRING_CONCATENATE(static_assert_on_line_, __LINE__) = 1 / (!!(cond)) }
+    #endif
+    
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+
+    #ifndef __ASM
+        #define __ASM               __asm
+    #endif
+
+    #ifndef __INLINE
+        #define __INLINE            __inline
+    #endif
+
+    #ifndef __WEAK
+        #define __WEAK              __attribute__((weak))
+    #endif
+
+    #ifndef __ALIGN
+        #define __ALIGN(n)          __attribute__((aligned(n)))
+    #endif
+
+    #ifndef __PACKED
+        #define __PACKED            __attribute__((packed, aligned(1)))
+    #endif
+
+    #ifndef __UNUSED
+        #define __UNUSED            __attribute__((unused))
+    #endif
+
+    #define GET_SP()                __current_sp()
+
+    #ifndef NRF_STATIC_ASSERT
+        #ifdef __cplusplus
+            #ifndef _Static_assert
+                #define _Static_assert static_assert
+            #endif
+        #endif
+        #define NRF_STATIC_ASSERT(cond, msg) _Static_assert(cond, msg)
+    #endif
+
+#elif defined ( __ICCARM__ )
+
+    #ifndef __ASM
+        #define __ASM               __asm
+    #endif
+
+    #ifndef __INLINE
+        #define __INLINE            inline
+    #endif
+
+    #ifndef __WEAK
+        #define __WEAK              __weak
+    #endif
+
+    #if (__VER__ >= 8000000)
+        #ifndef __ALIGN
+            #define __ALIGN(n) __attribute__((aligned(x)))
+        #endif
+
+        #ifndef   __PACKED
+            #define __PACKED __attribute__((packed, aligned(1)))
+        #endif
+    #else
+        #ifndef __ALIGN
+            #define STRING_PRAGMA(x) _Pragma(#x)
+            #define __ALIGN(n) STRING_PRAGMA(data_alignment = n)
+        #endif
+
+        #ifndef   __PACKED
+            #define __PACKED __packed
+        #endif
+    #endif
+
+    #ifndef __UNUSED
+        #define __UNUSED
+    #endif
+    
+    #define GET_SP()                __get_SP()
+
+    #ifndef NRF_STATIC_ASSERT
+        #define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg)
+    #endif
+
+#elif defined   ( __GNUC__ ) ||  defined   ( __clang__ )
+
+    #ifndef __ASM
+        #define __ASM               __asm
+    #endif
+
+    #ifndef __INLINE
+        #define __INLINE            inline
+    #endif
+
+    #ifndef __WEAK
+        #define __WEAK              __attribute__((weak))
+    #endif
+
+    #ifndef __ALIGN
+        #define __ALIGN(n)          __attribute__((aligned(n)))
+    #endif
+
+    #ifndef __PACKED
+        #define __PACKED           __attribute__((packed)) 
+    #endif
+
+    #ifndef __UNUSED
+        #define __UNUSED            __attribute__((unused))
+    #endif
+
+    #define GET_SP()                gcc_current_sp()
+
+    static inline unsigned int gcc_current_sp(void)
+    {
+        unsigned int stack_pointer = 0;
+        __asm__ __volatile__ ("mov %0, sp" : "=r"(stack_pointer));
+        return stack_pointer;
+    }
+
+    #ifndef NRF_STATIC_ASSERT
+        #ifdef __cplusplus
+            #ifndef _Static_assert
+                #define _Static_assert static_assert
+            #endif
+        #endif
+        #define NRF_STATIC_ASSERT(cond, msg) _Static_assert(cond, msg)
+    #endif
+
+#elif defined   ( __TASKING__ )
+
+    #ifndef __ASM
+        #define __ASM               __asm
+    #endif
+
+    #ifndef __INLINE
+        #define __INLINE            inline
+    #endif
+
+    #ifndef __WEAK
+        #define __WEAK              __attribute__((weak))
+    #endif
+
+    #ifndef __ALIGN
+        #define __ALIGN(n)          __align(n)
+    #endif
+    
+    /* Not defined for TASKING. */
+    #ifndef __PACKED
+        #define __PACKED
+    #endif
+
+    #ifndef __UNUSED
+        #define __UNUSED            __attribute__((unused))
+    #endif
+
+    #define GET_SP()                __get_MSP()
+
+    #ifndef NRF_STATIC_ASSERT
+        #define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg)
+    #endif
+
+#endif
+
+#define NRF_MDK_VERSION_ASSERT_AT_LEAST(major, minor, micro) \
+    NRF_STATIC_ASSERT( \
+        ( \
+            (major < MDK_MAJOR_VERSION) || \
+            (major == MDK_MAJOR_VERSION && minor < MDK_MINOR_VERSION) || \
+            (major == MDK_MAJOR_VERSION && minor == MDK_MINOR_VERSION && micro < MDK_MICRO_VERSION) \
+        ), "MDK version mismatch.")
+
+#define NRF_MDK_VERSION_ASSERT_EXACT(major, minor, micro) \
+    NRF_STATIC_ASSERT( \
+        ( \
+            (major != MDK_MAJOR_VERSION) || \
+            (major != MDK_MAJOR_VERSION) || \
+            (major != MDK_MAJOR_VERSION) \
+        ), "MDK version mismatch.")
+
+/*lint --flb "Leave library region" */
+
+#endif
diff --git a/bsp/nrf51822/Libraries/nrf51822/Include/nrf.h b/bsp/nrf51822/Libraries/nrf51822/Include/nrf.h
new file mode 100644
index 0000000000..6f47bd4211
--- /dev/null
+++ b/bsp/nrf51822/Libraries/nrf51822/Include/nrf.h
@@ -0,0 +1,189 @@
+/*
+
+Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+   list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions and the following disclaimer in the
+   documentation and/or other materials provided with the distribution.
+
+3. Neither the name of Nordic Semiconductor ASA nor the names of its
+   contributors may be used to endorse or promote products derived from this
+   software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef NRF_H
+#define NRF_H
+
+/* MDK version */
+#define MDK_MAJOR_VERSION   8 
+#define MDK_MINOR_VERSION   38 
+#define MDK_MICRO_VERSION   0 
+
+   
+/* Define coprocessor domains */
+#if defined (NRF5340_XXAA_APPLICATION) || defined (NRF5340_XXAA_NETWORK)
+    #ifndef NRF5340_XXAA
+        #define NRF5340_XXAA
+    #endif
+#endif
+#if defined (NRF5340_XXAA_APPLICATION)
+    #ifndef NRF_APPLICATION
+        #define NRF_APPLICATION
+    #endif
+#endif
+#if defined (NRF5340_XXAA_NETWORK)
+    #ifndef NRF_NETWORK
+        #define NRF_NETWORK
+    #endif
+#endif
+
+/* Apply compatibility macros for old nRF5340 macros */
+#if defined(NRF5340_XXAA)
+    #if defined (NRF_APPLICATION)
+        #ifndef NRF5340_XXAA_APPLICATION
+            #define NRF5340_XXAA_APPLICATION
+        #endif
+    #endif
+    #if defined (NRF_NETWORK)
+        #ifndef NRF5340_XXAA_NETWORK
+            #define NRF5340_XXAA_NETWORK
+        #endif
+    #endif
+#endif
+
+/* Define NRF51_SERIES for common use in nRF51 series devices. Only if not previously defined. */
+#if defined (NRF51) ||\
+    defined (NRF51422_XXAA) ||\
+    defined (NRF51422_XXAB) ||\
+    defined (NRF51422_XXAC) ||\
+    defined (NRF51801_XXAB) ||\
+    defined (NRF51802_XXAA) ||\
+    defined (NRF51822_XXAA) ||\
+    defined (NRF51822_XXAB) ||\
+    defined (NRF51822_XXAC) ||\
+    defined (NRF51824_XXAA)
+    #ifndef NRF51_SERIES
+        #define NRF51_SERIES
+    #endif
+    #ifndef NRF51
+        #define NRF51
+    #endif
+#endif
+
+/* Redefine "old" too-generic name NRF52 to NRF52832_XXAA to keep backwards compatibility. */
+#if defined (NRF52)
+    #ifndef NRF52832_XXAA
+        #define NRF52832_XXAA
+    #endif
+#endif
+
+/* Define NRF52_SERIES for common use in nRF52 series devices. Only if not previously defined. */
+#if defined (NRF52805_XXAA) || defined (NRF52810_XXAA) || defined (NRF52811_XXAA) || defined (NRF52820_XXAA) || defined (NRF52832_XXAA) || defined (NRF52832_XXAB) || defined (NRF52833_XXAA) || defined (NRF52840_XXAA)
+    #ifndef NRF52_SERIES
+        #define NRF52_SERIES
+    #endif
+#endif
+
+/* Define NRF53_SERIES for common use in nRF53 series devices. */
+#if defined (NRF5340_XXAA)
+    #ifndef NRF53_SERIES
+        #define NRF53_SERIES
+    #endif
+#endif
+
+/* Define NRF91_SERIES for common use in nRF91 series devices. */
+#if defined (NRF9160_XXAA)
+    #ifndef NRF91_SERIES    
+        #define NRF91_SERIES
+    #endif
+#endif
+
+/* Device selection for device includes. */
+#if defined (NRF51)
+    #include "nrf51.h"
+    #include "nrf51_bitfields.h"
+    #include "nrf51_deprecated.h"
+
+#elif defined (NRF52805_XXAA)
+    #include "nrf52805.h"
+    #include "nrf52805_bitfields.h"
+    #include "nrf51_to_nrf52810.h"
+    #include "nrf52_to_nrf52810.h"
+    #include "nrf52810_to_nrf52811.h"
+#elif defined (NRF52810_XXAA)
+    #include "nrf52810.h"
+    #include "nrf52810_bitfields.h"
+    #include "nrf51_to_nrf52810.h"
+    #include "nrf52_to_nrf52810.h"
+    #include "nrf52810_name_change.h"
+#elif defined (NRF52811_XXAA)
+    #include "nrf52811.h"
+    #include "nrf52811_bitfields.h"
+    #include "nrf51_to_nrf52810.h"
+    #include "nrf52_to_nrf52810.h"
+    #include "nrf52810_to_nrf52811.h"
+#elif defined (NRF52820_XXAA)
+    #include "nrf52820.h"
+    #include "nrf52820_bitfields.h"
+    #include "nrf51_to_nrf52.h"
+    #include "nrf52_to_nrf52833.h"
+    #include "nrf52833_to_nrf52820.h"
+#elif defined (NRF52832_XXAA) || defined (NRF52832_XXAB)
+    #include "nrf52.h"
+    #include "nrf52_bitfields.h"
+    #include "nrf51_to_nrf52.h"
+    #include "nrf52_name_change.h"
+#elif defined (NRF52833_XXAA)
+    #include "nrf52833.h"
+    #include "nrf52833_bitfields.h"
+    #include "nrf52_to_nrf52833.h"
+    #include "nrf51_to_nrf52.h"
+#elif defined (NRF52840_XXAA)
+    #include "nrf52840.h"
+    #include "nrf52840_bitfields.h"
+    #include "nrf51_to_nrf52840.h"
+    #include "nrf52_to_nrf52840.h"
+
+#elif defined (NRF5340_XXAA)
+    #if defined(NRF_APPLICATION)
+        #include "nrf5340_application.h"
+        #include "nrf5340_application_bitfields.h"
+        #include "nrf5340_application_name_change.h"
+    #elif defined (NRF_NETWORK)
+        #include "nrf5340_network.h"
+        #include "nrf5340_network_bitfields.h"
+        #include "nrf5340_network_name_change.h"
+    #endif
+
+#elif defined (NRF9160_XXAA)
+    #include "nrf9160.h"
+    #include "nrf9160_bitfields.h"
+    #include "nrf9160_name_change.h"
+
+#else
+    #error "Device must be defined. See nrf.h."
+#endif /* NRF51, NRF52805_XXAA, NRF52810_XXAA, NRF52811_XXAA, NRF52820_XXAA, NRF52832_XXAA, NRF52832_XXAB, NRF52833_XXAA, NRF52840_XXAA, NRF5340_XXAA_APPLICATION, NRF5340_XXAA_NETWORK, NRF9160_XXAA */
+
+#include "compiler_abstraction.h"
+
+#endif /* NRF_H */
+
diff --git a/bsp/nrf51822/Libraries/nrf51822/Include/nrf51_deprecated.h b/bsp/nrf51822/Libraries/nrf51822/Include/nrf51_deprecated.h
new file mode 100644
index 0000000000..a59e9d479b
--- /dev/null
+++ b/bsp/nrf51822/Libraries/nrf51822/Include/nrf51_deprecated.h
@@ -0,0 +1,446 @@
+/*
+
+Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+   list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions and the following disclaimer in the
+   documentation and/or other materials provided with the distribution.
+
+3. Neither the name of Nordic Semiconductor ASA nor the names of its
+   contributors may be used to endorse or promote products derived from this
+   software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef NRF51_DEPRECATED_H
+#define NRF51_DEPRECATED_H
+
+/*lint ++flb "Enter library region */
+
+/* This file is given to prevent your SW from not compiling with the updates made to nrf51.h and 
+ * nrf51_bitfields.h. The macros defined in this file were available previously. Do not use these
+ * macros on purpose. Use the ones defined in nrf51.h and nrf51_bitfields.h instead.
+ */
+
+/* NVMC */
+/* The register ERASEPROTECTEDPAGE is called ERASEPCR0 in the documentation. */
+#define ERASEPROTECTEDPAGE   ERASEPCR0
+
+ 
+/* LPCOMP */
+/* The interrupt ISR was renamed. Adding old name to the macros. */
+#define LPCOMP_COMP_IRQHandler          LPCOMP_IRQHandler
+#define LPCOMP_COMP_IRQn                LPCOMP_IRQn
+/* Corrected typo in RESULT register. */
+#define LPCOMP_RESULT_RESULT_Bellow     LPCOMP_RESULT_RESULT_Below
+ 
+ 
+/* MPU */
+/* The field MPU.PERR0.LPCOMP_COMP was renamed. Added into deprecated in case somebody was using the macros defined for it. */
+#define MPU_PERR0_LPCOMP_COMP_Pos           MPU_PERR0_LPCOMP_Pos
+#define MPU_PERR0_LPCOMP_COMP_Msk           MPU_PERR0_LPCOMP_Msk
+#define MPU_PERR0_LPCOMP_COMP_InRegion1     MPU_PERR0_LPCOMP_InRegion1
+#define MPU_PERR0_LPCOMP_COMP_InRegion0     MPU_PERR0_LPCOMP_InRegion0
+ 
+ 
+/* POWER */
+/* The field POWER.RAMON.OFFRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
+#define POWER_RAMON_OFFRAM3_Pos         (19UL)                                  
+#define POWER_RAMON_OFFRAM3_Msk         (0x1UL << POWER_RAMON_OFFRAM3_Pos)      
+#define POWER_RAMON_OFFRAM3_RAM3Off     (0UL)                                   
+#define POWER_RAMON_OFFRAM3_RAM3On      (1UL)                                   
+/* The field POWER.RAMON.OFFRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
+#define POWER_RAMON_OFFRAM2_Pos         (18UL)                                  
+#define POWER_RAMON_OFFRAM2_Msk         (0x1UL << POWER_RAMON_OFFRAM2_Pos)      
+#define POWER_RAMON_OFFRAM2_RAM2Off     (0UL)                                   
+#define POWER_RAMON_OFFRAM2_RAM2On      (1UL)                                  
+/* The field POWER.RAMON.ONRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
+#define POWER_RAMON_ONRAM3_Pos          (3UL)                                  
+#define POWER_RAMON_ONRAM3_Msk          (0x1UL << POWER_RAMON_ONRAM3_Pos)      
+#define POWER_RAMON_ONRAM3_RAM3Off      (0UL)                                  
+#define POWER_RAMON_ONRAM3_RAM3On       (1UL)                                  
+/* The field POWER.RAMON.ONRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
+#define POWER_RAMON_ONRAM2_Pos          (2UL)                                  
+#define POWER_RAMON_ONRAM2_Msk          (0x1UL << POWER_RAMON_ONRAM2_Pos)       
+#define POWER_RAMON_ONRAM2_RAM2Off      (0UL)                                  
+#define POWER_RAMON_ONRAM2_RAM2On       (1UL)                                 
+
+ 
+/* RADIO */
+/* The enumerated value RADIO.TXPOWER.TXPOWER.Neg40dBm was renamed. Added into deprecated with the new macro name. */
+#define RADIO_TXPOWER_TXPOWER_Neg40dBm  RADIO_TXPOWER_TXPOWER_Neg30dBm      
+/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */
+#define RADIO_CRCCNF_SKIP_ADDR_Pos      RADIO_CRCCNF_SKIPADDR_Pos 
+#define RADIO_CRCCNF_SKIP_ADDR_Msk      RADIO_CRCCNF_SKIPADDR_Msk 
+#define RADIO_CRCCNF_SKIP_ADDR_Include  RADIO_CRCCNF_SKIPADDR_Include 
+#define RADIO_CRCCNF_SKIP_ADDR_Skip     RADIO_CRCCNF_SKIPADDR_Skip 
+/* The name of the field PLLLOCK was corrected. Old macros added for compatibility. */
+#define RADIO_TEST_PLL_LOCK_Pos         RADIO_TEST_PLLLOCK_Pos 
+#define RADIO_TEST_PLL_LOCK_Msk         RADIO_TEST_PLLLOCK_Msk 
+#define RADIO_TEST_PLL_LOCK_Disabled    RADIO_TEST_PLLLOCK_Disabled 
+#define RADIO_TEST_PLL_LOCK_Enabled     RADIO_TEST_PLLLOCK_Enabled 
+/* The name of the field CONSTCARRIER was corrected. Old macros added for compatibility. */
+#define RADIO_TEST_CONST_CARRIER_Pos        RADIO_TEST_CONSTCARRIER_Pos 
+#define RADIO_TEST_CONST_CARRIER_Msk        RADIO_TEST_CONSTCARRIER_Msk 
+#define RADIO_TEST_CONST_CARRIER_Disabled   RADIO_TEST_CONSTCARRIER_Disabled 
+#define RADIO_TEST_CONST_CARRIER_Enabled    RADIO_TEST_CONSTCARRIER_Enabled 
+
+
+/* FICR */
+/* The registers FICR.SIZERAMBLOCK0, FICR.SIZERAMBLOCK1, FICR.SIZERAMBLOCK2 and FICR.SIZERAMBLOCK3 were renamed into an array. */
+#define SIZERAMBLOCK0   SIZERAMBLOCKS                   
+#define SIZERAMBLOCK1   SIZERAMBLOCKS                   
+#define SIZERAMBLOCK2   SIZERAMBLOCK[2]                 /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */
+#define SIZERAMBLOCK3   SIZERAMBLOCK[3]                 /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */
+/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */
+#define DEVICEID0       DEVICEID[0]                     
+#define DEVICEID1       DEVICEID[1]                     
+/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */
+#define ER0             ER[0]                           
+#define ER1             ER[1]                          
+#define ER2             ER[2]                       
+#define ER3             ER[3]                      
+/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */
+#define IR0             IR[0]                         
+#define IR1             IR[1]                         
+#define IR2             IR[2]                         
+#define IR3             IR[3]                          
+/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */
+#define DEVICEADDR0     DEVICEADDR[0]                  
+#define DEVICEADDR1     DEVICEADDR[1]                  
+
+
+/* PPI */
+/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
+#define TASKS_CHG0EN     TASKS_CHG[0].EN                    
+#define TASKS_CHG0DIS    TASKS_CHG[0].DIS                  
+#define TASKS_CHG1EN     TASKS_CHG[1].EN                    
+#define TASKS_CHG1DIS    TASKS_CHG[1].DIS                  
+#define TASKS_CHG2EN     TASKS_CHG[2].EN                   
+#define TASKS_CHG2DIS    TASKS_CHG[2].DIS                  
+#define TASKS_CHG3EN     TASKS_CHG[3].EN                    
+#define TASKS_CHG3DIS    TASKS_CHG[3].DIS                  
+/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
+#define CH0_EEP          CH[0].EEP                          
+#define CH0_TEP          CH[0].TEP                          
+#define CH1_EEP          CH[1].EEP                         
+#define CH1_TEP          CH[1].TEP                         
+#define CH2_EEP          CH[2].EEP                          
+#define CH2_TEP          CH[2].TEP                         
+#define CH3_EEP          CH[3].EEP                          
+#define CH3_TEP          CH[3].TEP                         
+#define CH4_EEP          CH[4].EEP                         
+#define CH4_TEP          CH[4].TEP                         
+#define CH5_EEP          CH[5].EEP                          
+#define CH5_TEP          CH[5].TEP                          
+#define CH6_EEP          CH[6].EEP                          
+#define CH6_TEP          CH[6].TEP                         
+#define CH7_EEP          CH[7].EEP                          
+#define CH7_TEP          CH[7].TEP                          
+#define CH8_EEP          CH[8].EEP                         
+#define CH8_TEP          CH[8].TEP                          
+#define CH9_EEP          CH[9].EEP                          
+#define CH9_TEP          CH[9].TEP                          
+#define CH10_EEP         CH[10].EEP                         
+#define CH10_TEP         CH[10].TEP                         
+#define CH11_EEP         CH[11].EEP                         
+#define CH11_TEP         CH[11].TEP                         
+#define CH12_EEP         CH[12].EEP                         
+#define CH12_TEP         CH[12].TEP                         
+#define CH13_EEP         CH[13].EEP                         
+#define CH13_TEP         CH[13].TEP                         
+#define CH14_EEP         CH[14].EEP                         
+#define CH14_TEP         CH[14].TEP                         
+#define CH15_EEP         CH[15].EEP                         
+#define CH15_TEP         CH[15].TEP                        
+/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
+#define CHG0             CHG[0]                            
+#define CHG1             CHG[1]                            
+#define CHG2             CHG[2]                             
+#define CHG3             CHG[3]                           
+/* All bitfield macros for the CHGx registers therefore changed name. */
+#define PPI_CHG0_CH15_Pos       PPI_CHG_CH15_Pos            
+#define PPI_CHG0_CH15_Msk       PPI_CHG_CH15_Msk            
+#define PPI_CHG0_CH15_Excluded  PPI_CHG_CH15_Excluded       
+#define PPI_CHG0_CH15_Included  PPI_CHG_CH15_Included       
+#define PPI_CHG0_CH14_Pos       PPI_CHG_CH14_Pos            
+#define PPI_CHG0_CH14_Msk       PPI_CHG_CH14_Msk           
+#define PPI_CHG0_CH14_Excluded  PPI_CHG_CH14_Excluded       
+#define PPI_CHG0_CH14_Included  PPI_CHG_CH14_Included       
+#define PPI_CHG0_CH13_Pos       PPI_CHG_CH13_Pos            
+#define PPI_CHG0_CH13_Msk       PPI_CHG_CH13_Msk            
+#define PPI_CHG0_CH13_Excluded  PPI_CHG_CH13_Excluded      
+#define PPI_CHG0_CH13_Included  PPI_CHG_CH13_Included       
+#define PPI_CHG0_CH12_Pos       PPI_CHG_CH12_Pos            
+#define PPI_CHG0_CH12_Msk       PPI_CHG_CH12_Msk            
+#define PPI_CHG0_CH12_Excluded  PPI_CHG_CH12_Excluded       
+#define PPI_CHG0_CH12_Included  PPI_CHG_CH12_Included       
+#define PPI_CHG0_CH11_Pos       PPI_CHG_CH11_Pos            
+#define PPI_CHG0_CH11_Msk       PPI_CHG_CH11_Msk            
+#define PPI_CHG0_CH11_Excluded  PPI_CHG_CH11_Excluded       
+#define PPI_CHG0_CH11_Included  PPI_CHG_CH11_Included       
+#define PPI_CHG0_CH10_Pos       PPI_CHG_CH10_Pos            
+#define PPI_CHG0_CH10_Msk       PPI_CHG_CH10_Msk            
+#define PPI_CHG0_CH10_Excluded  PPI_CHG_CH10_Excluded       
+#define PPI_CHG0_CH10_Included  PPI_CHG_CH10_Included       
+#define PPI_CHG0_CH9_Pos        PPI_CHG_CH9_Pos             
+#define PPI_CHG0_CH9_Msk        PPI_CHG_CH9_Msk             
+#define PPI_CHG0_CH9_Excluded   PPI_CHG_CH9_Excluded        
+#define PPI_CHG0_CH9_Included   PPI_CHG_CH9_Included        
+#define PPI_CHG0_CH8_Pos        PPI_CHG_CH8_Pos             
+#define PPI_CHG0_CH8_Msk        PPI_CHG_CH8_Msk             
+#define PPI_CHG0_CH8_Excluded   PPI_CHG_CH8_Excluded        
+#define PPI_CHG0_CH8_Included   PPI_CHG_CH8_Included        
+#define PPI_CHG0_CH7_Pos        PPI_CHG_CH7_Pos             
+#define PPI_CHG0_CH7_Msk        PPI_CHG_CH7_Msk             
+#define PPI_CHG0_CH7_Excluded   PPI_CHG_CH7_Excluded        
+#define PPI_CHG0_CH7_Included   PPI_CHG_CH7_Included        
+#define PPI_CHG0_CH6_Pos        PPI_CHG_CH6_Pos             
+#define PPI_CHG0_CH6_Msk        PPI_CHG_CH6_Msk             
+#define PPI_CHG0_CH6_Excluded   PPI_CHG_CH6_Excluded        
+#define PPI_CHG0_CH6_Included   PPI_CHG_CH6_Included        
+#define PPI_CHG0_CH5_Pos        PPI_CHG_CH5_Pos             
+#define PPI_CHG0_CH5_Msk        PPI_CHG_CH5_Msk             
+#define PPI_CHG0_CH5_Excluded   PPI_CHG_CH5_Excluded       
+#define PPI_CHG0_CH5_Included   PPI_CHG_CH5_Included        
+#define PPI_CHG0_CH4_Pos        PPI_CHG_CH4_Pos             
+#define PPI_CHG0_CH4_Msk        PPI_CHG_CH4_Msk             
+#define PPI_CHG0_CH4_Excluded   PPI_CHG_CH4_Excluded       
+#define PPI_CHG0_CH4_Included   PPI_CHG_CH4_Included       
+#define PPI_CHG0_CH3_Pos        PPI_CHG_CH3_Pos             
+#define PPI_CHG0_CH3_Msk        PPI_CHG_CH3_Msk            
+#define PPI_CHG0_CH3_Excluded   PPI_CHG_CH3_Excluded        
+#define PPI_CHG0_CH3_Included   PPI_CHG_CH3_Included       
+#define PPI_CHG0_CH2_Pos        PPI_CHG_CH2_Pos            
+#define PPI_CHG0_CH2_Msk        PPI_CHG_CH2_Msk             
+#define PPI_CHG0_CH2_Excluded   PPI_CHG_CH2_Excluded       
+#define PPI_CHG0_CH2_Included   PPI_CHG_CH2_Included       
+#define PPI_CHG0_CH1_Pos        PPI_CHG_CH1_Pos            
+#define PPI_CHG0_CH1_Msk        PPI_CHG_CH1_Msk            
+#define PPI_CHG0_CH1_Excluded   PPI_CHG_CH1_Excluded        
+#define PPI_CHG0_CH1_Included   PPI_CHG_CH1_Included       
+#define PPI_CHG0_CH0_Pos        PPI_CHG_CH0_Pos            
+#define PPI_CHG0_CH0_Msk        PPI_CHG_CH0_Msk            
+#define PPI_CHG0_CH0_Excluded   PPI_CHG_CH0_Excluded        
+#define PPI_CHG0_CH0_Included   PPI_CHG_CH0_Included       
+#define PPI_CHG1_CH15_Pos       PPI_CHG_CH15_Pos           
+#define PPI_CHG1_CH15_Msk       PPI_CHG_CH15_Msk           
+#define PPI_CHG1_CH15_Excluded  PPI_CHG_CH15_Excluded       
+#define PPI_CHG1_CH15_Included  PPI_CHG_CH15_Included      
+#define PPI_CHG1_CH14_Pos       PPI_CHG_CH14_Pos           
+#define PPI_CHG1_CH14_Msk       PPI_CHG_CH14_Msk            
+#define PPI_CHG1_CH14_Excluded  PPI_CHG_CH14_Excluded      
+#define PPI_CHG1_CH14_Included  PPI_CHG_CH14_Included       
+#define PPI_CHG1_CH13_Pos       PPI_CHG_CH13_Pos           
+#define PPI_CHG1_CH13_Msk       PPI_CHG_CH13_Msk            
+#define PPI_CHG1_CH13_Excluded  PPI_CHG_CH13_Excluded      
+#define PPI_CHG1_CH13_Included  PPI_CHG_CH13_Included      
+#define PPI_CHG1_CH12_Pos       PPI_CHG_CH12_Pos            
+#define PPI_CHG1_CH12_Msk       PPI_CHG_CH12_Msk           
+#define PPI_CHG1_CH12_Excluded  PPI_CHG_CH12_Excluded      
+#define PPI_CHG1_CH12_Included  PPI_CHG_CH12_Included      
+#define PPI_CHG1_CH11_Pos       PPI_CHG_CH11_Pos            
+#define PPI_CHG1_CH11_Msk       PPI_CHG_CH11_Msk           
+#define PPI_CHG1_CH11_Excluded  PPI_CHG_CH11_Excluded      
+#define PPI_CHG1_CH11_Included  PPI_CHG_CH11_Included      
+#define PPI_CHG1_CH10_Pos       PPI_CHG_CH10_Pos           
+#define PPI_CHG1_CH10_Msk       PPI_CHG_CH10_Msk            
+#define PPI_CHG1_CH10_Excluded  PPI_CHG_CH10_Excluded      
+#define PPI_CHG1_CH10_Included  PPI_CHG_CH10_Included      
+#define PPI_CHG1_CH9_Pos        PPI_CHG_CH9_Pos            
+#define PPI_CHG1_CH9_Msk        PPI_CHG_CH9_Msk            
+#define PPI_CHG1_CH9_Excluded   PPI_CHG_CH9_Excluded       
+#define PPI_CHG1_CH9_Included   PPI_CHG_CH9_Included       
+#define PPI_CHG1_CH8_Pos        PPI_CHG_CH8_Pos            
+#define PPI_CHG1_CH8_Msk        PPI_CHG_CH8_Msk            
+#define PPI_CHG1_CH8_Excluded   PPI_CHG_CH8_Excluded       
+#define PPI_CHG1_CH8_Included   PPI_CHG_CH8_Included       
+#define PPI_CHG1_CH7_Pos        PPI_CHG_CH7_Pos             
+#define PPI_CHG1_CH7_Msk        PPI_CHG_CH7_Msk            
+#define PPI_CHG1_CH7_Excluded   PPI_CHG_CH7_Excluded        
+#define PPI_CHG1_CH7_Included   PPI_CHG_CH7_Included       
+#define PPI_CHG1_CH6_Pos        PPI_CHG_CH6_Pos             
+#define PPI_CHG1_CH6_Msk        PPI_CHG_CH6_Msk            
+#define PPI_CHG1_CH6_Excluded   PPI_CHG_CH6_Excluded       
+#define PPI_CHG1_CH6_Included   PPI_CHG_CH6_Included       
+#define PPI_CHG1_CH5_Pos        PPI_CHG_CH5_Pos             
+#define PPI_CHG1_CH5_Msk        PPI_CHG_CH5_Msk             
+#define PPI_CHG1_CH5_Excluded   PPI_CHG_CH5_Excluded       
+#define PPI_CHG1_CH5_Included   PPI_CHG_CH5_Included        
+#define PPI_CHG1_CH4_Pos        PPI_CHG_CH4_Pos             
+#define PPI_CHG1_CH4_Msk        PPI_CHG_CH4_Msk             
+#define PPI_CHG1_CH4_Excluded   PPI_CHG_CH4_Excluded        
+#define PPI_CHG1_CH4_Included   PPI_CHG_CH4_Included        
+#define PPI_CHG1_CH3_Pos        PPI_CHG_CH3_Pos            
+#define PPI_CHG1_CH3_Msk        PPI_CHG_CH3_Msk             
+#define PPI_CHG1_CH3_Excluded   PPI_CHG_CH3_Excluded        
+#define PPI_CHG1_CH3_Included   PPI_CHG_CH3_Included       
+#define PPI_CHG1_CH2_Pos        PPI_CHG_CH2_Pos            
+#define PPI_CHG1_CH2_Msk        PPI_CHG_CH2_Msk             
+#define PPI_CHG1_CH2_Excluded   PPI_CHG_CH2_Excluded        
+#define PPI_CHG1_CH2_Included   PPI_CHG_CH2_Included        
+#define PPI_CHG1_CH1_Pos        PPI_CHG_CH1_Pos             
+#define PPI_CHG1_CH1_Msk        PPI_CHG_CH1_Msk            
+#define PPI_CHG1_CH1_Excluded   PPI_CHG_CH1_Excluded        
+#define PPI_CHG1_CH1_Included   PPI_CHG_CH1_Included       
+#define PPI_CHG1_CH0_Pos        PPI_CHG_CH0_Pos             
+#define PPI_CHG1_CH0_Msk        PPI_CHG_CH0_Msk            
+#define PPI_CHG1_CH0_Excluded   PPI_CHG_CH0_Excluded       
+#define PPI_CHG1_CH0_Included   PPI_CHG_CH0_Included       
+#define PPI_CHG2_CH15_Pos       PPI_CHG_CH15_Pos           
+#define PPI_CHG2_CH15_Msk       PPI_CHG_CH15_Msk            
+#define PPI_CHG2_CH15_Excluded  PPI_CHG_CH15_Excluded      
+#define PPI_CHG2_CH15_Included  PPI_CHG_CH15_Included      
+#define PPI_CHG2_CH14_Pos       PPI_CHG_CH14_Pos           
+#define PPI_CHG2_CH14_Msk       PPI_CHG_CH14_Msk           
+#define PPI_CHG2_CH14_Excluded  PPI_CHG_CH14_Excluded       
+#define PPI_CHG2_CH14_Included  PPI_CHG_CH14_Included      
+#define PPI_CHG2_CH13_Pos       PPI_CHG_CH13_Pos           
+#define PPI_CHG2_CH13_Msk       PPI_CHG_CH13_Msk            
+#define PPI_CHG2_CH13_Excluded  PPI_CHG_CH13_Excluded       
+#define PPI_CHG2_CH13_Included  PPI_CHG_CH13_Included      
+#define PPI_CHG2_CH12_Pos       PPI_CHG_CH12_Pos            
+#define PPI_CHG2_CH12_Msk       PPI_CHG_CH12_Msk            
+#define PPI_CHG2_CH12_Excluded  PPI_CHG_CH12_Excluded      
+#define PPI_CHG2_CH12_Included  PPI_CHG_CH12_Included       
+#define PPI_CHG2_CH11_Pos       PPI_CHG_CH11_Pos           
+#define PPI_CHG2_CH11_Msk       PPI_CHG_CH11_Msk           
+#define PPI_CHG2_CH11_Excluded  PPI_CHG_CH11_Excluded       
+#define PPI_CHG2_CH11_Included  PPI_CHG_CH11_Included       
+#define PPI_CHG2_CH10_Pos       PPI_CHG_CH10_Pos            
+#define PPI_CHG2_CH10_Msk       PPI_CHG_CH10_Msk            
+#define PPI_CHG2_CH10_Excluded  PPI_CHG_CH10_Excluded      
+#define PPI_CHG2_CH10_Included  PPI_CHG_CH10_Included      
+#define PPI_CHG2_CH9_Pos        PPI_CHG_CH9_Pos            
+#define PPI_CHG2_CH9_Msk        PPI_CHG_CH9_Msk            
+#define PPI_CHG2_CH9_Excluded   PPI_CHG_CH9_Excluded        
+#define PPI_CHG2_CH9_Included   PPI_CHG_CH9_Included       
+#define PPI_CHG2_CH8_Pos        PPI_CHG_CH8_Pos            
+#define PPI_CHG2_CH8_Msk        PPI_CHG_CH8_Msk            
+#define PPI_CHG2_CH8_Excluded   PPI_CHG_CH8_Excluded       
+#define PPI_CHG2_CH8_Included   PPI_CHG_CH8_Included        
+#define PPI_CHG2_CH7_Pos        PPI_CHG_CH7_Pos            
+#define PPI_CHG2_CH7_Msk        PPI_CHG_CH7_Msk            
+#define PPI_CHG2_CH7_Excluded   PPI_CHG_CH7_Excluded       
+#define PPI_CHG2_CH7_Included   PPI_CHG_CH7_Included       
+#define PPI_CHG2_CH6_Pos        PPI_CHG_CH6_Pos            
+#define PPI_CHG2_CH6_Msk        PPI_CHG_CH6_Msk            
+#define PPI_CHG2_CH6_Excluded   PPI_CHG_CH6_Excluded       
+#define PPI_CHG2_CH6_Included   PPI_CHG_CH6_Included       
+#define PPI_CHG2_CH5_Pos        PPI_CHG_CH5_Pos            
+#define PPI_CHG2_CH5_Msk        PPI_CHG_CH5_Msk            
+#define PPI_CHG2_CH5_Excluded   PPI_CHG_CH5_Excluded       
+#define PPI_CHG2_CH5_Included   PPI_CHG_CH5_Included        
+#define PPI_CHG2_CH4_Pos        PPI_CHG_CH4_Pos             
+#define PPI_CHG2_CH4_Msk        PPI_CHG_CH4_Msk             
+#define PPI_CHG2_CH4_Excluded   PPI_CHG_CH4_Excluded        
+#define PPI_CHG2_CH4_Included   PPI_CHG_CH4_Included       
+#define PPI_CHG2_CH3_Pos        PPI_CHG_CH3_Pos            
+#define PPI_CHG2_CH3_Msk        PPI_CHG_CH3_Msk            
+#define PPI_CHG2_CH3_Excluded   PPI_CHG_CH3_Excluded       
+#define PPI_CHG2_CH3_Included   PPI_CHG_CH3_Included       
+#define PPI_CHG2_CH2_Pos        PPI_CHG_CH2_Pos            
+#define PPI_CHG2_CH2_Msk        PPI_CHG_CH2_Msk           
+#define PPI_CHG2_CH2_Excluded   PPI_CHG_CH2_Excluded       
+#define PPI_CHG2_CH2_Included   PPI_CHG_CH2_Included       
+#define PPI_CHG2_CH1_Pos        PPI_CHG_CH1_Pos             
+#define PPI_CHG2_CH1_Msk        PPI_CHG_CH1_Msk             
+#define PPI_CHG2_CH1_Excluded   PPI_CHG_CH1_Excluded       
+#define PPI_CHG2_CH1_Included   PPI_CHG_CH1_Included       
+#define PPI_CHG2_CH0_Pos        PPI_CHG_CH0_Pos            
+#define PPI_CHG2_CH0_Msk        PPI_CHG_CH0_Msk            
+#define PPI_CHG2_CH0_Excluded   PPI_CHG_CH0_Excluded       
+#define PPI_CHG2_CH0_Included   PPI_CHG_CH0_Included        
+#define PPI_CHG3_CH15_Pos       PPI_CHG_CH15_Pos           
+#define PPI_CHG3_CH15_Msk       PPI_CHG_CH15_Msk           
+#define PPI_CHG3_CH15_Excluded  PPI_CHG_CH15_Excluded     
+#define PPI_CHG3_CH15_Included  PPI_CHG_CH15_Included      
+#define PPI_CHG3_CH14_Pos       PPI_CHG_CH14_Pos          
+#define PPI_CHG3_CH14_Msk       PPI_CHG_CH14_Msk           
+#define PPI_CHG3_CH14_Excluded  PPI_CHG_CH14_Excluded      
+#define PPI_CHG3_CH14_Included  PPI_CHG_CH14_Included       
+#define PPI_CHG3_CH13_Pos       PPI_CHG_CH13_Pos           
+#define PPI_CHG3_CH13_Msk       PPI_CHG_CH13_Msk            
+#define PPI_CHG3_CH13_Excluded  PPI_CHG_CH13_Excluded      
+#define PPI_CHG3_CH13_Included  PPI_CHG_CH13_Included      
+#define PPI_CHG3_CH12_Pos       PPI_CHG_CH12_Pos            
+#define PPI_CHG3_CH12_Msk       PPI_CHG_CH12_Msk            
+#define PPI_CHG3_CH12_Excluded  PPI_CHG_CH12_Excluded       
+#define PPI_CHG3_CH12_Included  PPI_CHG_CH12_Included       
+#define PPI_CHG3_CH11_Pos       PPI_CHG_CH11_Pos            
+#define PPI_CHG3_CH11_Msk       PPI_CHG_CH11_Msk            
+#define PPI_CHG3_CH11_Excluded  PPI_CHG_CH11_Excluded      
+#define PPI_CHG3_CH11_Included  PPI_CHG_CH11_Included       
+#define PPI_CHG3_CH10_Pos       PPI_CHG_CH10_Pos            
+#define PPI_CHG3_CH10_Msk       PPI_CHG_CH10_Msk            
+#define PPI_CHG3_CH10_Excluded  PPI_CHG_CH10_Excluded      
+#define PPI_CHG3_CH10_Included  PPI_CHG_CH10_Included      
+#define PPI_CHG3_CH9_Pos        PPI_CHG_CH9_Pos            
+#define PPI_CHG3_CH9_Msk        PPI_CHG_CH9_Msk            
+#define PPI_CHG3_CH9_Excluded   PPI_CHG_CH9_Excluded       
+#define PPI_CHG3_CH9_Included   PPI_CHG_CH9_Included       
+#define PPI_CHG3_CH8_Pos        PPI_CHG_CH8_Pos            
+#define PPI_CHG3_CH8_Msk        PPI_CHG_CH8_Msk             
+#define PPI_CHG3_CH8_Excluded   PPI_CHG_CH8_Excluded       
+#define PPI_CHG3_CH8_Included   PPI_CHG_CH8_Included       
+#define PPI_CHG3_CH7_Pos        PPI_CHG_CH7_Pos             
+#define PPI_CHG3_CH7_Msk        PPI_CHG_CH7_Msk            
+#define PPI_CHG3_CH7_Excluded   PPI_CHG_CH7_Excluded        
+#define PPI_CHG3_CH7_Included   PPI_CHG_CH7_Included       
+#define PPI_CHG3_CH6_Pos        PPI_CHG_CH6_Pos             
+#define PPI_CHG3_CH6_Msk        PPI_CHG_CH6_Msk             
+#define PPI_CHG3_CH6_Excluded   PPI_CHG_CH6_Excluded       
+#define PPI_CHG3_CH6_Included   PPI_CHG_CH6_Included        
+#define PPI_CHG3_CH5_Pos        PPI_CHG_CH5_Pos             
+#define PPI_CHG3_CH5_Msk        PPI_CHG_CH5_Msk             
+#define PPI_CHG3_CH5_Excluded   PPI_CHG_CH5_Excluded        
+#define PPI_CHG3_CH5_Included   PPI_CHG_CH5_Included       
+#define PPI_CHG3_CH4_Pos        PPI_CHG_CH4_Pos             
+#define PPI_CHG3_CH4_Msk        PPI_CHG_CH4_Msk            
+#define PPI_CHG3_CH4_Excluded   PPI_CHG_CH4_Excluded        
+#define PPI_CHG3_CH4_Included   PPI_CHG_CH4_Included        
+#define PPI_CHG3_CH3_Pos        PPI_CHG_CH3_Pos             
+#define PPI_CHG3_CH3_Msk        PPI_CHG_CH3_Msk            
+#define PPI_CHG3_CH3_Excluded   PPI_CHG_CH3_Excluded        
+#define PPI_CHG3_CH3_Included   PPI_CHG_CH3_Included        
+#define PPI_CHG3_CH2_Pos        PPI_CHG_CH2_Pos             
+#define PPI_CHG3_CH2_Msk        PPI_CHG_CH2_Msk             
+#define PPI_CHG3_CH2_Excluded   PPI_CHG_CH2_Excluded        
+#define PPI_CHG3_CH2_Included   PPI_CHG_CH2_Included       
+#define PPI_CHG3_CH1_Pos        PPI_CHG_CH1_Pos             
+#define PPI_CHG3_CH1_Msk        PPI_CHG_CH1_Msk             
+#define PPI_CHG3_CH1_Excluded   PPI_CHG_CH1_Excluded        
+#define PPI_CHG3_CH1_Included   PPI_CHG_CH1_Included        
+#define PPI_CHG3_CH0_Pos        PPI_CHG_CH0_Pos             
+#define PPI_CHG3_CH0_Msk        PPI_CHG_CH0_Msk             
+#define PPI_CHG3_CH0_Excluded   PPI_CHG_CH0_Excluded        
+#define PPI_CHG3_CH0_Included   PPI_CHG_CH0_Included      
+
+/* SPIS */
+/* nRF51 devices do not have an SPIS0, only SPIS1. SPIS0_EASYDMA_MAXCNT_SIZE was therefore renamed. */
+#define SPIS0_EASYDMA_MAXCNT_SIZE SPIS1_EASYDMA_MAXCNT_SIZE  
+
+
+
+/*lint --flb "Leave library region" */
+
+#endif /* NRF51_DEPRECATED_H */
+
diff --git a/bsp/nrf51822/Libraries/nrf51822/Include/system_nrf51.h b/bsp/nrf51822/Libraries/nrf51822/Include/system_nrf51.h
index ae613609dd..9db78f961c 100644
--- a/bsp/nrf51822/Libraries/nrf51822/Include/system_nrf51.h
+++ b/bsp/nrf51822/Libraries/nrf51822/Include/system_nrf51.h
@@ -1,32 +1,25 @@
-/* Copyright (c) 2013, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- *   * Redistributions of source code must retain the above copyright notice, this
- *     list of conditions and the following disclaimer.
- *
- *   * Redistributions in binary form must reproduce the above copyright notice,
- *     this list of conditions and the following disclaimer in the documentation
- *     and/or other materials provided with the distribution.
- *
- *   * Neither the name of Nordic Semiconductor ASA nor the names of its
- *     contributors may be used to endorse or promote products derived from
- *     this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
+/*
+
+Copyright (c) 2009-2021 ARM Limited. All rights reserved.
+
+    SPDX-License-Identifier: Apache-2.0
+
+Licensed under the Apache License, Version 2.0 (the License); you may
+not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an AS IS BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+NOTICE: This file has been modified by Nordic Semiconductor ASA.
+
+*/
+
 #ifndef SYSTEM_NRF51_H
 #define SYSTEM_NRF51_H
 
@@ -56,7 +49,7 @@ extern void SystemInit (void);
  * @param  none
  * @return none
  *
- * @brief  Updates the SystemCoreClock with current core Clock 
+ * @brief  Updates the SystemCoreClock with current core Clock
  *         retrieved from cpu registers.
  */
 extern void SystemCoreClockUpdate (void);
diff --git a/bsp/nrf51822/Libraries/nrf51822/Source/templates/arm/arm_startup_nrf51.s b/bsp/nrf51822/Libraries/nrf51822/Source/templates/arm/arm_startup_nrf51.s
index e06b1423b2..cad23a6595 100644
--- a/bsp/nrf51822/Libraries/nrf51822/Source/templates/arm/arm_startup_nrf51.s
+++ b/bsp/nrf51822/Libraries/nrf51822/Source/templates/arm/arm_startup_nrf51.s
@@ -1,42 +1,55 @@
-; Copyright (c) 2013, Nordic Semiconductor ASA
-; All rights reserved.
+; Copyright (c) 2009-2021 ARM Limited. All rights reserved.
 ; 
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
+;     SPDX-License-Identifier: Apache-2.0
 ; 
-; * Redistributions of source code must retain the above copyright notice, this
-;   list of conditions and the following disclaimer.
+; Licensed under the Apache License, Version 2.0 (the License); you may
+; not use this file except in compliance with the License.
+; You may obtain a copy of the License at
 ; 
-; * Redistributions in binary form must reproduce the above copyright notice,
-;   this list of conditions and the following disclaimer in the documentation
-;   and/or other materials provided with the distribution.
+;     www.apache.org/licenses/LICENSE-2.0
 ; 
-; * Neither the name of Nordic Semiconductor ASA nor the names of its
-;   contributors may be used to endorse or promote products derived from
-;   this software without specific prior written permission.
+; Unless required by applicable law or agreed to in writing, software
+; distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; See the License for the specific language governing permissions and
+; limitations under the License.
 ; 
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- 
-; NOTE: Template files (including this one) are application specific and therefore 
-; expected to be copied into the application project folder prior to its use!
+; NOTICE: This file has been modified by Nordic Semiconductor ASA.
 
-; Description message
+                IF :DEF: __STARTUP_CONFIG
+#ifdef  __STARTUP_CONFIG
+#include "startup_config.h"
+#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
+#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
+#endif
+#endif
+                ENDIF
 
-Stack_Size      EQU     0x00000400
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+                IF :DEF: __STARTUP_CONFIG
+Stack_Size      EQU __STARTUP_CONFIG_STACK_SIZE
+                ELIF :DEF: __STACK_SIZE
+Stack_Size      EQU __STACK_SIZE
+                ELSE
+Stack_Size      EQU 2048
+                ENDIF
+                
+                IF :DEF: __STARTUP_CONFIG
+Stack_Align     EQU __STARTUP_CONFIG_STACK_ALIGNEMENT
+                ELSE
+Stack_Align     EQU 3
+                ENDIF
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=Stack_Align
 Stack_Mem       SPACE   Stack_Size
 __initial_sp
 
-Heap_Size       EQU     0x00000000
+                IF :DEF: __STARTUP_CONFIG
+Heap_Size       EQU __STARTUP_CONFIG_HEAP_SIZE
+                ELIF :DEF: __HEAP_SIZE
+Heap_Size       EQU __HEAP_SIZE
+                ELSE
+Heap_Size       EQU 2048
+                ENDIF
 
                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3
 __heap_base
@@ -54,9 +67,9 @@ __heap_limit
                 EXPORT  __Vectors_Size
 
 __Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     Reset_Handler
+                DCD     NMI_Handler
+                DCD     HardFault_Handler
                 DCD     0                         ; Reserved
                 DCD     0                         ; Reserved
                 DCD     0                         ; Reserved
@@ -64,46 +77,45 @@ __Vectors       DCD     __initial_sp              ; Top of Stack
                 DCD     0                         ; Reserved
                 DCD     0                         ; Reserved
                 DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
+                DCD     SVC_Handler
                 DCD     0                         ; Reserved
                 DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
+                DCD     PendSV_Handler
+                DCD     SysTick_Handler
 
                 ; External Interrupts
-                DCD      POWER_CLOCK_IRQHandler ;POWER_CLOCK
-                DCD      RADIO_IRQHandler ;RADIO
-                DCD      UART0_IRQHandler ;UART0
-                DCD      SPI0_TWI0_IRQHandler ;SPI0_TWI0
-                DCD      SPI1_TWI1_IRQHandler ;SPI1_TWI1
-                DCD      0 ;Reserved
-                DCD      GPIOTE_IRQHandler ;GPIOTE
-                DCD      ADC_IRQHandler ;ADC
-                DCD      TIMER0_IRQHandler ;TIMER0
-                DCD      TIMER1_IRQHandler ;TIMER1
-                DCD      TIMER2_IRQHandler ;TIMER2
-                DCD      RTC0_IRQHandler ;RTC0
-                DCD      TEMP_IRQHandler ;TEMP
-                DCD      RNG_IRQHandler ;RNG
-                DCD      ECB_IRQHandler ;ECB
-                DCD      CCM_AAR_IRQHandler ;CCM_AAR
-                DCD      WDT_IRQHandler ;WDT
-                DCD      RTC1_IRQHandler ;RTC1
-                DCD      QDEC_IRQHandler ;QDEC
-                DCD      LPCOMP_IRQHandler ;LPCOMP
-                DCD      SWI0_IRQHandler ;SWI0
-                DCD      SWI1_IRQHandler ;SWI1
-                DCD      SWI2_IRQHandler ;SWI2
-                DCD      SWI3_IRQHandler ;SWI3
-                DCD      SWI4_IRQHandler ;SWI4
-                DCD      SWI5_IRQHandler ;SWI5
-                DCD      0 ;Reserved
-                DCD      0 ;Reserved
-                DCD      0 ;Reserved
-                DCD      0 ;Reserved
-                DCD      0 ;Reserved
-                DCD      0 ;Reserved
-
+                DCD     POWER_CLOCK_IRQHandler
+                DCD     RADIO_IRQHandler
+                DCD     UART0_IRQHandler
+                DCD     SPI0_TWI0_IRQHandler
+                DCD     SPI1_TWI1_IRQHandler
+                DCD     0                         ; Reserved
+                DCD     GPIOTE_IRQHandler
+                DCD     ADC_IRQHandler
+                DCD     TIMER0_IRQHandler
+                DCD     TIMER1_IRQHandler
+                DCD     TIMER2_IRQHandler
+                DCD     RTC0_IRQHandler
+                DCD     TEMP_IRQHandler
+                DCD     RNG_IRQHandler
+                DCD     ECB_IRQHandler
+                DCD     CCM_AAR_IRQHandler
+                DCD     WDT_IRQHandler
+                DCD     RTC1_IRQHandler
+                DCD     QDEC_IRQHandler
+                DCD     LPCOMP_IRQHandler
+                DCD     SWI0_IRQHandler
+                DCD     SWI1_IRQHandler
+                DCD     SWI2_IRQHandler
+                DCD     SWI3_IRQHandler
+                DCD     SWI4_IRQHandler
+                DCD     SWI5_IRQHandler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
 
 __Vectors_End
 
@@ -113,16 +125,16 @@ __Vectors_Size  EQU     __Vectors_End - __Vectors
 
 ; Reset Handler
 
-NRF_POWER_RAMON_ADDRESS            EQU   0x40000524  ; NRF_POWER->RAMON address
-NRF_POWER_RAMONB_ADDRESS           EQU   0x40000554  ; NRF_POWER->RAMONB address
-NRF_POWER_RAMONx_RAMxON_ONMODE_Msk EQU   0x3         ; All RAM blocks on in onmode bit mask
+NRF_POWER_RAMON_ADDRESS              EQU   0x40000524  ; NRF_POWER->RAMON address
+NRF_POWER_RAMONB_ADDRESS             EQU   0x40000554  ; NRF_POWER->RAMONB address
+NRF_POWER_RAMONx_RAMxON_ONMODE_Msk   EQU   0x3         ; All RAM blocks on in onmode bit mask
 
 Reset_Handler   PROC
                 EXPORT  Reset_Handler             [WEAK]
                 IMPORT  SystemInit
                 IMPORT  __main
-                
-                MOVS    R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk
+
+                                MOVS    R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk
                 
                 LDR     R0, =NRF_POWER_RAMON_ADDRESS
                 LDR     R2, [R0]
@@ -133,7 +145,7 @@ Reset_Handler   PROC
                 LDR     R2, [R0]
                 ORRS    R2, R2, R1
                 STR     R2, [R0]
-                
+
                 LDR     R0, =SystemInit
                 BLX     R0
                 LDR     R0, =__main
@@ -216,7 +228,6 @@ SWI2_IRQHandler
 SWI3_IRQHandler
 SWI4_IRQHandler
 SWI5_IRQHandler
-
                 B .
                 ENDP
                 ALIGN
@@ -224,7 +235,7 @@ SWI5_IRQHandler
 ; User Initial Stack & Heap
 
                 IF      :DEF:__MICROLIB
-                
+
                 EXPORT  __initial_sp
                 EXPORT  __heap_base
                 EXPORT  __heap_limit
@@ -233,17 +244,18 @@ SWI5_IRQHandler
 
                 IMPORT  __use_two_region_memory
                 EXPORT  __user_initial_stackheap
-__user_initial_stackheap
+
+__user_initial_stackheap PROC
 
                 LDR     R0, = Heap_Mem
                 LDR     R1, = (Stack_Mem + Stack_Size)
                 LDR     R2, = (Heap_Mem + Heap_Size)
                 LDR     R3, = Stack_Mem
                 BX      LR
+                ENDP
 
                 ALIGN
 
                 ENDIF
 
                 END
-
diff --git a/bsp/nrf51822/Libraries/nrf51822/Source/templates/system_nrf51.c b/bsp/nrf51822/Libraries/nrf51822/Source/templates/system_nrf51.c
index 712114e6c1..3c036c8cbd 100644
--- a/bsp/nrf51822/Libraries/nrf51822/Source/templates/system_nrf51.c
+++ b/bsp/nrf51822/Libraries/nrf51822/Source/templates/system_nrf51.c
@@ -1,39 +1,32 @@
-/* Copyright (c) 2013, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- *   * Redistributions of source code must retain the above copyright notice, this
- *     list of conditions and the following disclaimer.
- *
- *   * Redistributions in binary form must reproduce the above copyright notice,
- *     this list of conditions and the following disclaimer in the documentation
- *     and/or other materials provided with the distribution.
- *
- *   * Neither the name of Nordic Semiconductor ASA nor the names of its
- *     contributors may be used to endorse or promote products derived from
- *     this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
+/*
 
-/* NOTE: Template files (including this one) are application specific and therefore expected to 
+Copyright (c) 2009-2021 ARM Limited. All rights reserved.
+
+    SPDX-License-Identifier: Apache-2.0
+
+Licensed under the Apache License, Version 2.0 (the License); you may
+not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an AS IS BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+NOTICE: This file has been modified by Nordic Semiconductor ASA.
+
+*/
+
+/* NOTE: Template files (including this one) are application specific and therefore expected to
    be copied into the application project folder prior to its use! */
 
 #include 
 #include 
 #include "nrf.h"
+#include "nrf_erratas.h"
 #include "system_nrf51.h"
 
 /*lint ++flb "Enter library region" */
@@ -41,12 +34,8 @@
 
 #define __SYSTEM_CLOCK      (16000000UL)     /*!< nRF51 devices use a fixed System Clock Frequency of 16MHz */
 
-static bool is_manual_peripheral_setup_needed(void);
-static bool is_disabled_in_debug_needed(void);
-
-
 #if defined ( __CC_ARM )
-    uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;  
+    uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;
 #elif defined ( __ICCARM__ )
     __root uint32_t SystemCoreClock = __SYSTEM_CLOCK;
 #elif defined   ( __GNUC__ )
@@ -65,57 +54,36 @@ void SystemInit(void)
 
     /* Prepare the peripherals for use as indicated by the PAN 26 "System: Manual setup is required
        to enable the use of peripherals" found at Product Anomaly document for your device found at
-       https://www.nordicsemi.com/. The side effect of executing these instructions in the devices 
+       https://infocenter.nordicsemi.com/index.jsp The side effect of executing these instructions in the devices
        that do not need it is that the new peripherals in the second generation devices (LPCOMP for
        example) will not be available. */
-    if (is_manual_peripheral_setup_needed())
+    if (nrf51_errata_26())
     {
         *(uint32_t volatile *)0x40000504 = 0xC007FFDF;
         *(uint32_t volatile *)0x40006C18 = 0x00008000;
     }
-    
+
     /* Disable PROTENSET registers under debug, as indicated by PAN 59 "MPU: Reset value of DISABLEINDEBUG
-       register is incorrect" found at Product Anomaly document four your device found at 
-       https://www.nordicsemi.com/. There is no side effect of using these instruction if not needed. */
-    if (is_disabled_in_debug_needed())
+       register is incorrect" found at Product Anomaly document for your device found at
+       https://infocenter.nordicsemi.com/index.jsp There is no side effect of using these instruction if not needed. */
+    if (nrf51_errata_59())
     {
         NRF_MPU->DISABLEINDEBUG = MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos;
     }
-}
 
-
-static bool is_manual_peripheral_setup_needed(void) 
-{
-    if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
-    {
-        if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x00) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
-        {
-            return true;
-        }
-        if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x10) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
-        {
-            return true;
-        }
-        if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
-        {
-            return true;
+    /* Execute the following code to eliminate excessive current in sleep mode with RAM retention in nRF51802 devices,
+       as indicated by PAN 76 "System: Excessive current in sleep mode with retention" found at Product Anomaly document
+       for your device found at https://infocenter.nordicsemi.com/index.jsp */
+    if (nrf51_errata_76()){
+        if (*(uint32_t volatile *)0x4006EC00 != 1){
+            *(uint32_t volatile *)0x4006EC00 = 0x9375;
+            while (*(uint32_t volatile *)0x4006EC00 != 1){
+            }
         }
+        *(uint32_t volatile *)0x4006EC14 = 0xC0;
     }
-    
-    return false;
-}
 
-static bool is_disabled_in_debug_needed(void) 
-{
-    if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
-    {
-        if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
-        {
-            return true;
-        }
-    }
-    
-    return false;
+    SystemCoreClockUpdate();
 }
 
 /*lint --flb "Leave library region" */
diff --git a/bsp/nrf51822/applications/application.c b/bsp/nrf51822/applications/application.c
index 355c843156..4ff4507306 100644
--- a/bsp/nrf51822/applications/application.c
+++ b/bsp/nrf51822/applications/application.c
@@ -1,11 +1,7 @@
 /*
- * File      : application.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2015, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/nrf51822/drivers/SConscript b/bsp/nrf51822/drivers/SConscript
index 638846d656..cba5bbfffc 100644
--- a/bsp/nrf51822/drivers/SConscript
+++ b/bsp/nrf51822/drivers/SConscript
@@ -3,7 +3,7 @@ Import('rtconfig')
 from building import *
 
 # get current directory
-cwd = GetCurrentDir()
+cwd = GetCurrentDir() 
 
 src	= Glob('*.c')
 CPPPATH = [cwd]
diff --git a/bsp/nrf51822/drivers/board.c b/bsp/nrf51822/drivers/board.c
index 933e2237cc..978a9aa675 100644
--- a/bsp/nrf51822/drivers/board.c
+++ b/bsp/nrf51822/drivers/board.c
@@ -1,11 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  */
 
@@ -80,7 +76,7 @@ void RTC0_IRQHandler(void)
  */
 void rt_hw_board_init()
 {
-    lfclk_config();
+    //lfclk_config();
     rtc_config();
     NRF_RTC0->TASKS_START = 1;
     /* Initial usart deriver, and set console device */
diff --git a/bsp/nrf51822/drivers/board.h b/bsp/nrf51822/drivers/board.h
index 3e793bc307..59f0c03898 100644
--- a/bsp/nrf51822/drivers/board.h
+++ b/bsp/nrf51822/drivers/board.h
@@ -1,11 +1,7 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  */
 
@@ -14,9 +10,9 @@
 
 //  Internal SRAM memory size[Kbytes] <16 or 32>
 //  Default: 16
-#define NRF_SRAM_BEGIN	(0x20000000)
-#define NRF_SRAM_SIZE	(16 * 1024)
-#define NRF_SRAM_END	(NRF_SRAM_BEGIN + NRF_SRAM_SIZE)
+#define NRF_SRAM_BEGIN  (0x20000000)
+#define NRF_SRAM_SIZE   (16 * 1024)
+#define NRF_SRAM_END    (NRF_SRAM_BEGIN + NRF_SRAM_SIZE)
 //#endif
 
 
diff --git a/bsp/nrf51822/drivers/uart.c b/bsp/nrf51822/drivers/uart.c
index 56c3b1aefd..a7b017a949 100644
--- a/bsp/nrf51822/drivers/uart.c
+++ b/bsp/nrf51822/drivers/uart.c
@@ -1,11 +1,7 @@
 /*
- * File      : uart.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2015 RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  */
 
@@ -72,7 +68,7 @@ static rt_err_t rt_uart_init (rt_device_t dev)
         NRF_UART0->CONFIG  = (UART_CONFIG_HWFC_Enabled << UART_CONFIG_HWFC_Pos);
     }
 
-    NRF_UART0->BAUDRATE      = (UART_BAUDRATE_BAUDRATE_Baud38400 << UART_BAUDRATE_BAUDRATE_Pos);
+    NRF_UART0->BAUDRATE      = (UART_BAUDRATE_BAUDRATE_Baud115200 << UART_BAUDRATE_BAUDRATE_Pos);
     NRF_UART0->ENABLE        = (UART_ENABLE_ENABLE_Enabled << UART_ENABLE_ENABLE_Pos);
     NRF_UART0->TASKS_STARTTX = 1;
     NRF_UART0->TASKS_STARTRX = 1;
@@ -189,10 +185,10 @@ void rt_hw_uart_init(void)
     rt_ringbuffer_init(&(uart->rx_rb), rx_buffer, sizeof(rx_buffer));
 
     /* device interface */
-    uart->parent.init 	    = rt_uart_init;
-    uart->parent.open 	    = rt_uart_open;
+    uart->parent.init       = rt_uart_init;
+    uart->parent.open       = rt_uart_open;
     uart->parent.close      = rt_uart_close;
-    uart->parent.read 	    = rt_uart_read;
+    uart->parent.read       = rt_uart_read;
     uart->parent.write      = rt_uart_write;
     uart->parent.control    = RT_NULL;
     uart->parent.user_data  = RT_NULL;
diff --git a/bsp/nrf51822/drivers/uart.h b/bsp/nrf51822/drivers/uart.h
index 5ad910d3aa..48d950365c 100644
--- a/bsp/nrf51822/drivers/uart.h
+++ b/bsp/nrf51822/drivers/uart.h
@@ -1,11 +1,7 @@
 /*
- * File      : uart.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2015, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  */
 
@@ -14,10 +10,10 @@
 
 
 
-#define RX_PIN_NUMBER          23
+#define RX_PIN_NUMBER          25
 #define TX_PIN_NUMBER          24
-#define CTS_PIN_NUMBER         25
-#define RTS_PIN_NUMBER         22
+#define CTS_PIN_NUMBER         26
+#define RTS_PIN_NUMBER         27
 #define HWFC                   false
 
 
diff --git a/bsp/nrf51822/project.uvoptx b/bsp/nrf51822/project.uvoptx
new file mode 100644
index 0000000000..2557e6d7b4
--- /dev/null
+++ b/bsp/nrf51822/project.uvoptx
@@ -0,0 +1,640 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    rt-thread
+    0x4
+    ARM-ADS
+    
+      12000000
+      
+        1
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+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        .\build\
+      
+      
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+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        Segger\JL2CM3.dll
+      
+      
+        
+          0
+          JL2CM3
+          -U480200710 -O78 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0nrf51xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF51822_xxAA$Flash\nrf51xxx.flm)
+        
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0nrf51xxx -FS00 -FL0200000 -FP0($$Device:nRF51822_xxAA$Flash\nrf51xxx.flm))
+        
+      
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+      ..\..\src\kservice.c
+      kservice.c
+      0
+      0
+    
+    
+      6
+      23
+      1
+      0
+      0
+      0
+      ..\..\src\device.c
+      device.c
+      0
+      0
+    
+    
+      6
+      24
+      1
+      0
+      0
+      0
+      ..\..\src\components.c
+      components.c
+      0
+      0
+    
+    
+      6
+      25
+      1
+      0
+      0
+      0
+      ..\..\src\thread.c
+      thread.c
+      0
+      0
+    
+    
+      6
+      26
+      1
+      0
+      0
+      0
+      ..\..\src\object.c
+      object.c
+      0
+      0
+    
+    
+      6
+      27
+      1
+      0
+      0
+      0
+      ..\..\src\idle.c
+      idle.c
+      0
+      0
+    
+    
+      6
+      28
+      1
+      0
+      0
+      0
+      ..\..\src\mem.c
+      mem.c
+      0
+      0
+    
+    
+      6
+      29
+      1
+      0
+      0
+      0
+      ..\..\src\ipc.c
+      ipc.c
+      0
+      0
+    
+    
+      6
+      30
+      1
+      0
+      0
+      0
+      ..\..\src\irq.c
+      irq.c
+      0
+      0
+    
+    
+      6
+      31
+      1
+      0
+      0
+      0
+      ..\..\src\timer.c
+      timer.c
+      0
+      0
+    
+    
+      6
+      32
+      1
+      0
+      0
+      0
+      ..\..\src\clock.c
+      clock.c
+      0
+      0
+    
+    
+      6
+      33
+      1
+      0
+      0
+      0
+      ..\..\src\scheduler.c
+      scheduler.c
+      0
+      0
+    
+    
+      6
+      34
+      1
+      0
+      0
+      0
+      ..\..\src\mempool.c
+      mempool.c
+      0
+      0
+    
+  
+
+
diff --git a/bsp/nrf51822/project.uvproj b/bsp/nrf51822/project.uvprojx
similarity index 78%
rename from bsp/nrf51822/project.uvproj
rename to bsp/nrf51822/project.uvprojx
index de8e9fc084..c4d044488b 100644
--- a/bsp/nrf51822/project.uvproj
+++ b/bsp/nrf51822/project.uvprojx
@@ -1,41 +1,46 @@
 
 
+
   2.1
+
   
### uVision Project, (C) Keil Software

+
   
     
       rt-thread
       0x4
       ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
       
         
           nRF51822_xxAA
           Nordic Semiconductor
-          NordicSemiconductor.nRF_DeviceFamilyPack.1.1.4
-          http://developer.nordicsemi.com/nRF51_SDK/pieces/nRF_DeviceFamilyPack/
+          NordicSemiconductor.nRF_DeviceFamilyPack.8.38.0
+          http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/
           IROM(0x00000000,0x40000) IRAM(0x20000000,0x4000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE
-          
-          
+          
+          
           UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0nrf51xxx -FS00 -FL0200000 -FP0($$Device:nRF51822_xxAA$Flash\nrf51xxx.flm))
           0
           $$Device:nRF51822_xxAA$Device\Include\nrf.h
-          
-          
-          
-          
-          
-          
-          
-          
-          
+          
+          
+          
+          
+          
+          
+          
+          
+          
           $$Device:nRF51822_xxAA$SVD\nrf51.xml
           0
           0
-          
-          
-          
-          
-          
+          
+          
+          
+          
+          
           
             0
             0
@@ -57,8 +62,8 @@
           
             0
             0
-            
-            
+            
+            
             0
             0
             0
@@ -67,8 +72,8 @@
           
             0
             0
-            
-            
+            
+            
             0
             0
             0
@@ -77,13 +82,15 @@
           
             0
             0
-            
-            
+            
+            
             0
             0
+            0
+            0
           
           0
-          
+          
         
         
           0
@@ -97,8 +104,8 @@
           0
           0
           3
-          
-          
+          
+          
           1
         
         
@@ -119,47 +126,6 @@
             0
             16
           
-          
-            0
-            1
-            1
-            1
-            1
-            1
-            1
-            1
-            0
-            1
-          
-          
-            1
-            1
-            1
-            1
-            1
-            1
-            0
-            1
-            0
-            1
-          
-          0
-          6
-          
-            
-            
-            
-            
-            
-          
-          
-            
-            
-            
-            
-            
-            Segger\JL2CM3.dll
-          
         
         
           
@@ -173,10 +139,10 @@
           1
           BIN\UL2CM3.DLL
           "" ()
-          
-          
-          
-          
+          
+          
+          
+          
           0
         
         
@@ -209,7 +175,7 @@
             0
             0
             "Cortex-M0"
-            
+            
             0
             0
             0
@@ -218,12 +184,14 @@
             0
             0
             0
+            0
             0
             0
             8
             0
             0
             0
+            0
             3
             3
             0
@@ -340,7 +308,7 @@
                 0x0
               
             
-            
+            
           
           
             1
@@ -357,12 +325,20 @@
             0
             0
             0
+            0
             0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
             
               --c99
-              NRF51, USE_STDPERIPH_DRIVER
-              
-              .;..\..\include;applications;.;drivers;Libraries\CMSIS\Include;Libraries\nrf51822\Include;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m0;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\common
+              NRF51, __RTTHREAD__, USE_STDPERIPH_DRIVER
+              
+              applications;.;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m0;..\..\components\drivers\include;drivers;Libraries\CMSIS\Include;Libraries\nrf51822\Include;..\..\components\finsh;.;..\..\include
             
           
           
@@ -375,11 +351,12 @@
             0
             0
             0
+            0
             
-              
-              
-              
-              
+              
+              
+              
+              
             
           
           
@@ -391,207 +368,55 @@
             0
             0x08000000
             0x20000000
-            
-            
-            
-            
-            
-            
-            
+            
+            
+            
+            
+            
+            
+            
           
         
       
       
-        
-          Kernel
-          
-            
-              clock.c
-              1
-              ..\..\src\clock.c
-            
-          
-          
-            
-              components.c
-              1
-              ..\..\src\components.c
-            
-          
-          
-            
-              cpu.c
-              1
-              ..\..\src\cpu.c
-            
-          
-          
-            
-              device.c
-              1
-              ..\..\src\device.c
-            
-          
-          
-            
-              idle.c
-              1
-              ..\..\src\idle.c
-            
-          
-          
-            
-              ipc.c
-              1
-              ..\..\src\ipc.c
-            
-          
-          
-            
-              irq.c
-              1
-              ..\..\src\irq.c
-            
-          
-          
-            
-              kservice.c
-              1
-              ..\..\src\kservice.c
-            
-          
-          
-            
-              mem.c
-              1
-              ..\..\src\mem.c
-            
-          
-          
-            
-              mempool.c
-              1
-              ..\..\src\mempool.c
-            
-          
-          
-            
-              object.c
-              1
-              ..\..\src\object.c
-            
-          
-          
-            
-              scheduler.c
-              1
-              ..\..\src\scheduler.c
-            
-          
-          
-            
-              signal.c
-              1
-              ..\..\src\signal.c
-            
-          
-          
-            
-              thread.c
-              1
-              ..\..\src\thread.c
-            
-          
-          
-            
-              timer.c
-              1
-              ..\..\src\timer.c
-            
-          
-        
         
           Applications
-          
-            
-              application.c
-              1
-              applications\application.c
-            
-          
           
             
               startup.c
               1
               applications\startup.c
             
-          
-        
-        
-          Drivers
-          
             
-              board.c
+              application.c
               1
-              drivers\board.c
-            
-          
-          
-            
-              uart.c
-              1
-              drivers\uart.c
+              applications\application.c
             
           
         
         
-          Startup Code
-          
-            
-              system_nrf51.c
-              1
-              Libraries\nrf51822\Source\templates\system_nrf51.c
-            
-          
-          
-            
-              arm_startup_nrf51.s
-              2
-              Libraries\nrf51822\Source\templates\arm\arm_startup_nrf51.s
-            
-          
-        
-        
-          cpu
-          
-            
-              backtrace.c
-              1
-              ..\..\libcpu\arm\common\backtrace.c
-            
-          
+          CPU
           
             
               div0.c
               1
               ..\..\libcpu\arm\common\div0.c
             
-          
-          
             
               showmem.c
               1
               ..\..\libcpu\arm\common\showmem.c
             
-          
-          
+            
+              backtrace.c
+              1
+              ..\..\libcpu\arm\common\backtrace.c
+            
             
               cpuport.c
               1
               ..\..\libcpu\arm\cortex-m0\cpuport.c
             
-          
-          
             
               context_rvds.S
               2
@@ -601,53 +426,66 @@
         
         
           DeviceDrivers
-          
-            
-              completion.c
-              1
-              ..\..\components\drivers\src\completion.c
-            
-          
           
             
               dataqueue.c
               1
               ..\..\components\drivers\src\dataqueue.c
             
-          
-          
             
-              pipe.c
+              workqueue.c
               1
-              ..\..\components\drivers\src\pipe.c
+              ..\..\components\drivers\src\workqueue.c
             
-          
-          
             
               ringblk_buf.c
               1
               ..\..\components\drivers\src\ringblk_buf.c
             
-          
-          
+            
+              completion.c
+              1
+              ..\..\components\drivers\src\completion.c
+            
+            
+              pipe.c
+              1
+              ..\..\components\drivers\src\pipe.c
+            
             
               ringbuffer.c
               1
               ..\..\components\drivers\src\ringbuffer.c
             
-          
-          
             
               waitqueue.c
               1
               ..\..\components\drivers\src\waitqueue.c
             
           
+        
+        
+          Drivers
           
             
-              workqueue.c
+              board.c
               1
-              ..\..\components\drivers\src\workqueue.c
+              drivers\board.c
+            
+            
+              uart.c
+              1
+              drivers\uart.c
+            
+            
+              system_nrf51.c
+              1
+              Libraries\nrf51822\Source\templates\system_nrf51.c
+            
+            
+              arm_startup_nrf51.s
+              2
+              Libraries\nrf51822\Source\templates\arm\arm_startup_nrf51.s
             
           
         
@@ -659,23 +497,96 @@
               1
               ..\..\components\finsh\shell.c
             
-          
-          
+            
+              msh.c
+              1
+              ..\..\components\finsh\msh.c
+            
             
               cmd.c
               1
               ..\..\components\finsh\cmd.c
             
           
+        
+        
+          Kernel
           
             
-              msh.c
+              kservice.c
               1
-              ..\..\components\finsh\msh.c
+              ..\..\src\kservice.c
+            
+            
+              device.c
+              1
+              ..\..\src\device.c
+            
+            
+              components.c
+              1
+              ..\..\src\components.c
+            
+            
+              thread.c
+              1
+              ..\..\src\thread.c
+            
+            
+              object.c
+              1
+              ..\..\src\object.c
+            
+            
+              idle.c
+              1
+              ..\..\src\idle.c
+            
+            
+              mem.c
+              1
+              ..\..\src\mem.c
+            
+            
+              ipc.c
+              1
+              ..\..\src\ipc.c
+            
+            
+              irq.c
+              1
+              ..\..\src\irq.c
+            
+            
+              timer.c
+              1
+              ..\..\src\timer.c
+            
+            
+              clock.c
+              1
+              ..\..\src\clock.c
+            
+            
+              scheduler.c
+              1
+              ..\..\src\scheduler.c
+            
+            
+              mempool.c
+              1
+              ..\..\src\mempool.c
             
           
         
       
     
   
+
+  
+    
+    
+    
+  
+
 
diff --git a/bsp/nrf51822/rtconfig.h b/bsp/nrf51822/rtconfig.h
index ee7cb6b2f4..306c8e8b2c 100644
--- a/bsp/nrf51822/rtconfig.h
+++ b/bsp/nrf51822/rtconfig.h
@@ -3,16 +3,16 @@
 #define __RTTHREAD_CFG_H__
 
 /* RT_NAME_MAX*/
-#define RT_NAME_MAX	   6
+#define RT_NAME_MAX    6
 
 /* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE	4
+#define RT_ALIGN_SIZE   4
 
 /* PRIORITY_MAX */
-#define RT_THREAD_PRIORITY_MAX	8
+#define RT_THREAD_PRIORITY_MAX  8
 
 /* Tick per Second */
-#define RT_TICK_PER_SECOND	100
+#define RT_TICK_PER_SECOND  100
 
 /* SECTION: RT_DEBUG */
 /* Thread Debug */
@@ -24,20 +24,20 @@
 /* Using Hook */
 #define RT_USING_HOOK
 
-#define IDLE_THREAD_STACK_SIZE	512
+#define IDLE_THREAD_STACK_SIZE  512
 
 /* Using Software Timer */
 /* #define RT_USING_TIMER_SOFT */
-#define RT_TIMER_THREAD_PRIO		4
-#define RT_TIMER_THREAD_STACK_SIZE	512
-#define RT_TIMER_TICK_PER_SECOND	100
+#define RT_TIMER_THREAD_PRIO        4
+#define RT_TIMER_THREAD_STACK_SIZE  512
+#define RT_TIMER_TICK_PER_SECOND    100
 
 /* SECTION: IPC */
 /* Using Semaphore*/
 #define RT_USING_SEMAPHORE
 
 /* Using Mutex */
-/* #define RT_USING_MUTEX */
+#define RT_USING_MUTEX
 
 /* Using Event */
 /* #define RT_USING_EVENT */
@@ -74,9 +74,9 @@
 /* SECTION: Console options */
 #define RT_USING_CONSOLE
 /* the buffer size of console*/
-#define RT_CONSOLEBUF_SIZE	128
+#define RT_CONSOLEBUF_SIZE  128
 // 
-#define RT_CONSOLE_DEVICE_NAME	    "uart0"
+#define RT_CONSOLE_DEVICE_NAME      "uart0"
 
 
 
@@ -84,8 +84,8 @@
 #define RT_USING_FINSH
 /* configure finsh parameters */
 #define FINSH_THREAD_PRIORITY 6
-#define FINSH_THREAD_STACK_SIZE	512
-#define FINSH_HISTORY_LINES	1
+#define FINSH_THREAD_STACK_SIZE 512
+#define FINSH_HISTORY_LINES 1
 /* Using symbol table */
 #define FINSH_USING_SYMTAB
 #define FINSH_USING_DESCRIPTION
diff --git a/bsp/nrf51822/rtconfig.py b/bsp/nrf51822/rtconfig.py
index bad289d12d..85b4f3154b 100644
--- a/bsp/nrf51822/rtconfig.py
+++ b/bsp/nrf51822/rtconfig.py
@@ -69,7 +69,7 @@ elif PLATFORM == 'armcc':
     AFLAGS = DEVICE
     LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-stm32.map --scatter nrf51822_rom.sct'
 
-    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' 
     LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
 
     EXEC_PATH += '/arm/bin40/'
diff --git a/bsp/nrf51822/template.uvoptx b/bsp/nrf51822/template.uvoptx
new file mode 100644
index 0000000000..0b46ec95af
--- /dev/null
+++ b/bsp/nrf51822/template.uvoptx
@@ -0,0 +1,177 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    rt-thread
+    0x4
+    ARM-ADS
+    
+      12000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        .\build\
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      5
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        1
+        0
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        4
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        Segger\JL2CM3.dll
+      
+      
+        
+          0
+          JL2CM3
+          -U480200710 -O78 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0nrf51xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF51822_xxAA$Flash\nrf51xxx.flm)
+        
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0nrf51xxx -FS00 -FL0200000 -FP0($$Device:nRF51822_xxAA$Flash\nrf51xxx.flm))
+        
+      
+      
+      
+        0
+      
+      
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+    
+  
+
+
diff --git a/bsp/nrf51822/template.uvproj b/bsp/nrf51822/template.uvprojx
similarity index 95%
rename from bsp/nrf51822/template.uvproj
rename to bsp/nrf51822/template.uvprojx
index 39cd92f59a..328e8f0c3f 100644
--- a/bsp/nrf51822/template.uvproj
+++ b/bsp/nrf51822/template.uvprojx
@@ -10,12 +10,13 @@
       rt-thread
       0x4
       ARM-ADS
+      0
       
         
           nRF51822_xxAA
           Nordic Semiconductor
-          NordicSemiconductor.nRF_DeviceFamilyPack.1.1.4
-          http://developer.nordicsemi.com/nRF51_SDK/pieces/nRF_DeviceFamilyPack/
+          NordicSemiconductor.nRF_DeviceFamilyPack.8.38.0
+          http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/
           IROM(0x00000000,0x40000) IRAM(0x20000000,0x4000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE
           
           
@@ -84,6 +85,8 @@
             
             0
             0
+            0
+            0
           
           0
           
@@ -147,7 +150,7 @@
             1
           
           0
-          6
+          4
           
             
             
@@ -221,12 +224,14 @@
             0
             0
             0
+            0
             0
             0
             8
             0
             0
             0
+            0
             3
             3
             0
@@ -360,7 +365,15 @@
             0
             0
             0
+            0
             0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
             
               --c99
               
@@ -378,6 +391,7 @@
             0
             0
             0
+            0
             
               
               
diff --git a/bsp/nrf5x/docs/images/image-20210403182031505.png b/bsp/nrf5x/docs/images/image-20210403182031505.png
new file mode 100644
index 0000000000..5fcba55d3b
Binary files /dev/null and b/bsp/nrf5x/docs/images/image-20210403182031505.png differ
diff --git a/bsp/nrf5x/docs/images/image-20210403182242202.png b/bsp/nrf5x/docs/images/image-20210403182242202.png
new file mode 100644
index 0000000000..1249f99adc
Binary files /dev/null and b/bsp/nrf5x/docs/images/image-20210403182242202.png differ
diff --git a/bsp/nrf5x/docs/images/microbit-overview-1-5.png b/bsp/nrf5x/docs/images/microbit-overview-1-5.png
new file mode 100644
index 0000000000..f7977b3899
Binary files /dev/null and b/bsp/nrf5x/docs/images/microbit-overview-1-5.png differ
diff --git a/bsp/nrf5x/docs/nRF5x系列BSP制作教程.md b/bsp/nrf5x/docs/nRF5x系列BSP制作教程.md
index e69de29bb2..761db1bde9 100644
--- a/bsp/nrf5x/docs/nRF5x系列BSP制作教程.md
+++ b/bsp/nrf5x/docs/nRF5x系列BSP制作教程.md
@@ -0,0 +1,92 @@
+# Nordic 系列 BSP 制作教程
+
+为了让广大开发者更好、更方便地使用 BSP 进行开发，重新整理了现有的 Nordic 系列的 BSP，推出了新的 BSP 框架。新的 BSP 框架在易用性、移植便利性、驱动完整性、代码规范性等方面都有较大提升，在新的 BSP 框架下进行开发，可以大大提高应用的开发效率。
+
+这边参考了官方stm32的相关制作流程，熟悉STM32的可以参考[STM32](https://github.com/RT-Thread/rt-thread/blob/master/bsp/stm32/docs/STM32%E7%B3%BB%E5%88%97BSP%E5%88%B6%E4%BD%9C%E6%95%99%E7%A8%8B.md)
+
+## 1. 知识准备
+
+制作一个 BSP 的过程就是构建一个新系统的过程，因此想要制作出好用的 BSP，要对 RT-Thread 系统的构建过程有一定了解，需要的知识准备如下所示：
+
+- 掌握  Nordic系列 BSP 的使用方法
+
+  了解 BSP 的使用方法，可以阅读 [Nordic 说明文档](../README.md) 中使用教程表格内的文档。
+
+- 了解 scons 工程构建方法
+
+  RT-Thread 使用 scons 作为系统的构建工具，因此了解 scons 的常用命令对制作新 BSP 是基本要求。
+
+- 了解设备驱动框架
+
+  在 RT-Thread 系统中，应用程序通过设备驱动框架来操作硬件，因此了解设备驱动框架，对添加 BSP 驱动是很重要的。
+
+- 了解 kconfig 语法
+
+  RT-Thread 系统通过 menuconfig 的方式进行配置，而 menuconfig 中的选项是由 kconfig 文件决定的，因此想要对 RT-Thread 系统进行配置，需要对 kconfig 语法有一定了解。
+
+
+##  BSP 制作方法
+
+本节以制作microbit添加 BSP。在接下来的章节中将会详细介绍具体步骤，帮助开发者快速创建所需要的 BSP。
+
+### 复制通用模板
+制作新 BSP 的第一步是复制一份同系列的 BSP 模板作为基础，通过对 BSP 模板的修改来获得新 BSP。目前提供的 BSP 模板系列如下表所示：
+
+| 工程模板 | 说明 |
+| ------- | ---- |
+| libraries/templates/nrfx | nrfx系列 BSP 模板 |
+
+### 修改芯片类型
+
+打开board/Kconfig找到SOC_NRF52840 
+
+SOC_NRF52840 要改成你对应的芯片类型，例如SOC_NRF51822 这个时候要确认[nrfx](https://github.com/xckhmf/nrfx)软件包中的SConscript中有对应的配置选项，没用的话，可以pr到对应的软件包
+
+```
+elif GetDepend('SOC_NRF51822') == True:
+	define += ['NRF51822_XXAA']
+	src += ['./mdk/system_nrf51.c']
+	
+	if rtconfig.PLATFORM == 'armcc':
+		src += ['./mdk/arm_startup_nrf51.s']
+		
+	if rtconfig.PLATFORM == 'gcc':
+		src += ['./mdk/gcc_startup_nrf51.S']
+		
+	if rtconfig.PLATFORM == 'iar':
+		D_SRC += ['./mdk/iar_startup_nrf51.s']
+```
+
+### 修改templete.uvprojx模板
+
+修改template.uvprojx中的soc和jlink等配置选项，这个可以参考官方SDK sample的keil配置
+
+这边如果要配置jlink的话，要注意flash download算法是否需要修改。
+
+### 检查rtconfig.py
+
+检查rtconfig.py中的CPU类型，nrf52是`cortex-m4` 如果是nrf51需要改成`cortex-m0`
+
+### 修改menuconfig中的相关配置
+
+menuconfig中修改RAM size大小。并且修改link.sct文件，这个可以参考官方sample
+
+![image-20210403182242202](images/image-20210403182242202.png)
+
+配置UART0相关的的引脚配置， 选中对应的UART0 TX RX引脚
+
+![image-20210403182031505](images/image-20210403182031505.png)
+
+最后调试`scons --target=mdk5`
+
+### 修改整理readme.md
+
+修改readme.md, 将你的开发板常用的链接信息整理到readme.md中
+
+
+
+## FAQ:
+
+1. 编译keil遇到 `No section matches selector - no section to be FIRST`
+
+这个因为package里面的nrfx中的Sconscript未添加好对应的芯片，没有加载arm_startup_nrf51.s等文件导致
\ No newline at end of file
diff --git a/bsp/nrf5x/libraries/cmsis/include/arm_common_tables.h b/bsp/nrf5x/libraries/cmsis/include/arm_common_tables.h
index 8742a56991..03153851b8 100644
--- a/bsp/nrf5x/libraries/cmsis/include/arm_common_tables.h
+++ b/bsp/nrf5x/libraries/cmsis/include/arm_common_tables.h
@@ -2,12 +2,12 @@
 * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
 *
 * $Date:        19. October 2015
-* $Revision: 	V.1.4.5 a
+* $Revision:    V.1.4.5 a
 *
-* Project: 	    CMSIS DSP Library
-* Title:	    arm_common_tables.h
+* Project:      CMSIS DSP Library
+* Title:        arm_common_tables.h
 *
-* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+* Description:  This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
 *
 * Target Processor: Cortex-M4/Cortex-M3
 *
diff --git a/bsp/nrf5x/libraries/cmsis/include/arm_const_structs.h b/bsp/nrf5x/libraries/cmsis/include/arm_const_structs.h
index 726d06eb69..2927e49b34 100644
--- a/bsp/nrf5x/libraries/cmsis/include/arm_const_structs.h
+++ b/bsp/nrf5x/libraries/cmsis/include/arm_const_structs.h
@@ -2,12 +2,12 @@
 * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
 *
 * $Date:        19. March 2015
-* $Revision: 	V.1.4.5
+* $Revision:    V.1.4.5
 *
-* Project: 	    CMSIS DSP Library
-* Title:	    arm_const_structs.h
+* Project:      CMSIS DSP Library
+* Title:        arm_const_structs.h
 *
-* Description:	This file has constant structs that are initialized for
+* Description:  This file has constant structs that are initialized for
 *              user convenience.  For example, some can be given as
 *              arguments to the arm_cfft_f32() function.
 *
diff --git a/bsp/nrf5x/libraries/cmsis/include/cmsis_armcc_V6.h b/bsp/nrf5x/libraries/cmsis/include/cmsis_armcc_V6.h
index cd13240ce3..04b41ed69c 100644
--- a/bsp/nrf5x/libraries/cmsis/include/cmsis_armcc_V6.h
+++ b/bsp/nrf5x/libraries/cmsis/include/cmsis_armcc_V6.h
@@ -464,7 +464,7 @@ __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t v
 /**
   \brief   Set Base Priority with condition (non_secure)
   \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled,
-	       or the new value increases the BASEPRI priority level.
+           or the new value increases the BASEPRI priority level.
   \param [in]    basePri  Base Priority value to set
  */
 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value)
diff --git a/bsp/nrf5x/libraries/drivers/drv_adc.c b/bsp/nrf5x/libraries/drivers/drv_adc.c
index 8b136a3598..03db215aba 100644
--- a/bsp/nrf5x/libraries/drivers/drv_adc.c
+++ b/bsp/nrf5x/libraries/drivers/drv_adc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -31,7 +31,7 @@ static void nrf5x_saadc_event_hdr(nrfx_saadc_evt_t const * p_event)
                 j ++;
             }
         }
-        results.done = 1;  
+        results.done = 1;
     }
 }
 
@@ -72,22 +72,22 @@ static void set_channels(drv_nrfx_saadc_channel_t * channel)
 
 /* channel: 0-7 */
 static rt_err_t nrf5x_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
-{      
-    nrfx_err_t err_code = NRFX_SUCCESS; 
+{
+    nrfx_err_t err_code = NRFX_SUCCESS;
     uint8_t i,j;
 
     if (enabled)
-    { 
+    {
         RT_ASSERT(device != RT_NULL);
         RT_ASSERT(device->parent.user_data != RT_NULL);
-        
+
         drv_nrfx_saadc_channel_t * drv_channel_config = NULL;
-        drv_channel_config = (drv_nrfx_saadc_channel_t *)device->parent.user_data;   
-    
+        drv_channel_config = (drv_nrfx_saadc_channel_t *)device->parent.user_data;
+
         set_channels(drv_channel_config);
-        
+
         nrfx_saadc_channel_t channels_cache[results.channel_count];
-        
+
         j = 0;
         for(i = 0; i < 8; i++)
         {
@@ -97,20 +97,20 @@ static rt_err_t nrf5x_adc_enabled(struct rt_adc_device *device, rt_uint32_t chan
                 j ++;
             }
         }
-        
+
         err_code = nrfx_saadc_channels_config(channels_cache,results.channel_count);
 
         err_code = nrfx_saadc_simple_mode_set(get_channels_mask(),
                                       NRF_SAADC_RESOLUTION_12BIT,
                                       NRF_SAADC_OVERSAMPLE_DISABLED,
                                       nrf5x_saadc_event_hdr);
-        
-        err_code = nrfx_saadc_buffer_set(result_buff_cache, results.channel_count);                                     
+
+        err_code = nrfx_saadc_buffer_set(result_buff_cache, results.channel_count);
     }
     else
     {
         results.channels[channel].channel_index = 0xff;
-        
+
         results.channel_count = 0;
         for(i = 0; i < 8; i++)
         {
@@ -119,7 +119,7 @@ static rt_err_t nrf5x_adc_enabled(struct rt_adc_device *device, rt_uint32_t chan
                 results.channel_count ++;
             }
         }
-        
+
         if(results.channel_count == 0)
         {
             nrfx_saadc_channel_t channels_cache[1];
@@ -129,7 +129,7 @@ static rt_err_t nrf5x_adc_enabled(struct rt_adc_device *device, rt_uint32_t chan
         else
         {
             nrfx_saadc_channel_t channels_cache[results.channel_count];
-            
+
             j = 0;
             for(i = 0; i < 8; i++)
             {
@@ -139,25 +139,25 @@ static rt_err_t nrf5x_adc_enabled(struct rt_adc_device *device, rt_uint32_t chan
                     j ++;
                 }
             }
-            
+
             err_code = nrfx_saadc_channels_config(channels_cache,results.channel_count);
 
             err_code = nrfx_saadc_simple_mode_set(get_channels_mask(),
                                           NRF_SAADC_RESOLUTION_12BIT,
                                           NRF_SAADC_OVERSAMPLE_DISABLED,
                                           nrf5x_saadc_event_hdr);
-            
+
             err_code = nrfx_saadc_buffer_set(result_buff_cache, results.channel_count);
         }
     }
 
-    return err_code;   
+    return err_code;
 }
 
 static rt_err_t nrf5x_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
 {
-    nrfx_err_t err_code = NRFX_SUCCESS; 
-    
+    nrfx_err_t err_code = NRFX_SUCCESS;
+
     if (results.channels[channel].channel_index != 0xff)
     {
         results.done = 0;
@@ -169,7 +169,7 @@ static rt_err_t nrf5x_get_adc_value(struct rt_adc_device *device, rt_uint32_t ch
         * value = results.result_buffer[channel];
         results.done = 0;
     }
-    
+
     return err_code;
 }
 
@@ -184,7 +184,7 @@ int rt_hw_adc_init(void)
     int result = RT_EOK;
     uint8_t i;
     char name_buf[6] = ADC_NAME;
-    
+
     for(i = 0; i < 8; i++)
     {
         results.channels[i].channel_index = 0xff;
@@ -192,7 +192,7 @@ int rt_hw_adc_init(void)
         results.channel_count = 0;
         results.done = 0;
     }
-        
+
     /* initializing SAADC interrupt priority */
     if (nrfx_saadc_init(NRFX_SAADC_CONFIG_IRQ_PRIORITY) != NRFX_SUCCESS)
     {
@@ -236,43 +236,43 @@ INIT_BOARD_EXPORT(rt_hw_adc_init);
 void saadc_sample(void)
 {
     drv_nrfx_saadc_channel_t channel_config;
-    rt_uint32_t result; 
-    
+    rt_uint32_t result;
+
     rt_adc_device_t adc_dev;
     adc_dev = (rt_adc_device_t)rt_device_find(ADC_NAME);
     adc_dev->parent.user_data = &channel_config;
-    
-    channel_config = (drv_nrfx_saadc_channel_t){.mode = SAMPLE_ADC_MODE_SINGLE_ENDED, 
-                                                .pin_p = SAMPLE_ADC_AIN1, 
-                                                .pin_n = SAMPLE_ADC_AIN_NC, 
+
+    channel_config = (drv_nrfx_saadc_channel_t){.mode = SAMPLE_ADC_MODE_SINGLE_ENDED,
+                                                .pin_p = SAMPLE_ADC_AIN1,
+                                                .pin_n = SAMPLE_ADC_AIN_NC,
                                                 .channel_num = SAMPLE_ADC_CHANNEL_0};
     rt_adc_enable(adc_dev, channel_config.channel_num);
-        
-    channel_config = (drv_nrfx_saadc_channel_t){.mode = SAMPLE_ADC_MODE_SINGLE_ENDED, 
-                                                .pin_p = SAMPLE_ADC_AIN2, 
-                                                .pin_n = SAMPLE_ADC_AIN_NC, 
+
+    channel_config = (drv_nrfx_saadc_channel_t){.mode = SAMPLE_ADC_MODE_SINGLE_ENDED,
+                                                .pin_p = SAMPLE_ADC_AIN2,
+                                                .pin_n = SAMPLE_ADC_AIN_NC,
                                                 .channel_num = SAMPLE_ADC_CHANNEL_1};
     rt_adc_enable(adc_dev, channel_config.channel_num);
-    
-    channel_config = (drv_nrfx_saadc_channel_t){.mode = SAMPLE_ADC_MODE_SINGLE_ENDED, 
-                                                .pin_p = SAMPLE_ADC_AIN7, 
-                                                .pin_n = SAMPLE_ADC_AIN_NC, 
+
+    channel_config = (drv_nrfx_saadc_channel_t){.mode = SAMPLE_ADC_MODE_SINGLE_ENDED,
+                                                .pin_p = SAMPLE_ADC_AIN7,
+                                                .pin_n = SAMPLE_ADC_AIN_NC,
                                                 .channel_num = SAMPLE_ADC_CHANNEL_5};
     rt_adc_enable(adc_dev, channel_config.channel_num);
-    
-    int count = 1; 
+
+    int count = 1;
     while(count++)
     {
         result = rt_adc_read(adc_dev, 0);
         rt_kprintf("saadc channel 0 value = %d, ",result);
-        
+
         result = rt_adc_read(adc_dev, 1);
         rt_kprintf("saadc channel 1 value = %d, ",result);
-        
+
         result = rt_adc_read(adc_dev, 5);
-        rt_kprintf("saadc channel 5 value = %d",result);  
-        
-        rt_kprintf("\r\n"); 
+        rt_kprintf("saadc channel 5 value = %d",result);
+
+        rt_kprintf("\r\n");
         rt_thread_mdelay(1000);
     }
 }
diff --git a/bsp/nrf5x/libraries/drivers/drv_adc.h b/bsp/nrf5x/libraries/drivers/drv_adc.h
index b65a981982..e3c9b835fc 100644
--- a/bsp/nrf5x/libraries/drivers/drv_adc.h
+++ b/bsp/nrf5x/libraries/drivers/drv_adc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2020-08-18     guohp1128    the first version
  */
- 
+
 #ifndef __DRV_ADC_H__
 #define __DRV_ADC_H__
 
@@ -18,12 +18,12 @@
 
 #define ADC_NAME "adc"
 
-/* 
+/*
     previous definition in application
-    
+
     set single-ended mode or differential mode.
     selection ADC input pin, and config the number of Channel.
-   
+
     mode: 0 single-ended mode,1 differential mode
     pin_p: 0-7
     pin_n: 0-7,if single-ended mode, pin_n invalid
@@ -40,9 +40,9 @@ typedef struct
 typedef struct
 {
     nrfx_saadc_channel_t    channels[8];
-    uint8_t                 channel_count; 
-    nrf_saadc_value_t       result_buffer[8]; 
-    uint8_t                 done;    
+    uint8_t                 channel_count;
+    nrf_saadc_value_t       result_buffer[8];
+    uint8_t                 done;
 } drv_nrfx_saadc_result_t;
 
 #endif /* __DRV_ADC_H__ */
diff --git a/bsp/nrf5x/libraries/drivers/drv_flash.c b/bsp/nrf5x/libraries/drivers/drv_flash.c
index 727bbeda78..61948fc373 100644
--- a/bsp/nrf5x/libraries/drivers/drv_flash.c
+++ b/bsp/nrf5x/libraries/drivers/drv_flash.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/nrf5x/libraries/drivers/drv_gpio.c b/bsp/nrf5x/libraries/drivers/drv_gpio.c
index d34e62e827..7138261223 100644
--- a/bsp/nrf5x/libraries/drivers/drv_gpio.c
+++ b/bsp/nrf5x/libraries/drivers/drv_gpio.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -12,7 +12,7 @@
 
 #ifdef RT_USING_PIN
 
-static const struct pin_index pins[] = 
+static const struct pin_index pins[] =
 {
     __NRF5X_PIN(0 ,  0, 0 ),
     __NRF5X_PIN(1 ,  0, 1 ),
@@ -46,7 +46,7 @@ static const struct pin_index pins[] =
     __NRF5X_PIN(29,  0, 29),
     __NRF5X_PIN(30,  0, 30),
     __NRF5X_PIN(31,  0, 31),
-#ifdef SOC_NRF52840    
+#ifdef SOC_NRF52840
     __NRF5X_PIN(32,  1, 0 ),
     __NRF5X_PIN(33,  1, 1 ),
     __NRF5X_PIN(34,  1, 2 ),
@@ -110,7 +110,7 @@ static void nrf5x_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     {
         return;
     }
-    
+
     nrf_gpio_pin_write(pin, value);
 }
 
@@ -179,7 +179,7 @@ static void pin_irq_hdr(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action)
 {
     int i;
     int irq_quantity;
-    
+
     irq_quantity = ITEM_NUM(pin_irq_hdr_tab);
     for(i = 0; i < irq_quantity; i++)
     {
@@ -202,13 +202,13 @@ static rt_err_t nrf5x_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     nrfx_err_t err_code;
     int i;
     int irq_quantity;
-    
+
     index = get_pin(pin);
     if (index == RT_NULL)
     {
         return RT_ENOSYS;
     }
-    
+
     irq_quantity = ITEM_NUM(pin_irq_hdr_tab);
     for(i = 0; i < irq_quantity; i++)
     {
@@ -227,37 +227,37 @@ static rt_err_t nrf5x_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
     {
         return RT_ENOMEM;
     }
-    
-    level = rt_hw_interrupt_disable();  
+
+    level = rt_hw_interrupt_disable();
     pin_irq_hdr_tab[irqindex].pin  = pin;
     pin_irq_hdr_tab[irqindex].hdr  = hdr;
     pin_irq_hdr_tab[irqindex].mode = mode;
     pin_irq_hdr_tab[irqindex].args = args;
-    
+
   if(mode == PIN_IRQ_MODE_RISING)
     {
         nrfx_gpiote_in_config_t inConfig = NRFX_GPIOTE_CONFIG_IN_SENSE_LOTOHI(args);
-        inConfig.pull = NRF_GPIO_PIN_PULLDOWN;  
+        inConfig.pull = NRF_GPIO_PIN_PULLDOWN;
         err_code = nrfx_gpiote_in_init(pin, &inConfig, pin_irq_hdr);
     }
-        
+
     else if(mode == PIN_IRQ_MODE_FALLING)
     {
         nrfx_gpiote_in_config_t inConfig = NRFX_GPIOTE_CONFIG_IN_SENSE_HITOLO(args);
-        inConfig.pull = NRF_GPIO_PIN_PULLUP;  
+        inConfig.pull = NRF_GPIO_PIN_PULLUP;
         err_code = nrfx_gpiote_in_init(pin, &inConfig, pin_irq_hdr);
     }
-    
+
     else if(mode == PIN_IRQ_MODE_RISING_FALLING)
     {
         nrfx_gpiote_in_config_t inConfig = NRFX_GPIOTE_CONFIG_IN_SENSE_TOGGLE(args);
         inConfig.pull = NRF_GPIO_PIN_PULLUP;
         err_code = nrfx_gpiote_in_init(pin, &inConfig, pin_irq_hdr);
     }
-    
+
     rt_hw_interrupt_enable(level);
-    
-    switch(err_code) 
+
+    switch(err_code)
     {
         case NRFX_ERROR_BUSY:
             return RT_EBUSY;
@@ -282,7 +282,7 @@ static rt_err_t nrf5x_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
     {
         return RT_ENOSYS;
     }
-        
+
     irq_quantity = ITEM_NUM(pin_irq_hdr_tab);
     for(i = 0; i < irq_quantity; i++)
     {
@@ -308,7 +308,7 @@ static rt_err_t nrf5x_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
 static rt_err_t nrf5x_pin_irq_enable(struct rt_device *device, rt_base_t pin,
                                      rt_uint32_t enabled)
 {
-    const struct pin_index *index;  
+    const struct pin_index *index;
     rt_base_t level;
     int i;
     int irq_quantity;
@@ -337,7 +337,7 @@ static rt_err_t nrf5x_pin_irq_enable(struct rt_device *device, rt_base_t pin,
             break;
         }
     }
-    
+
     if(i >= irq_quantity)
     {
         return RT_ENOSYS;
@@ -362,8 +362,8 @@ int rt_hw_pin_init(void)
 
     err_code = (nrfx_err_t)rt_device_pin_register("pin", &_nrf5x_pin_ops, RT_NULL);
     err_code = nrfx_gpiote_init(NRFX_GPIOTE_CONFIG_IRQ_PRIORITY);
-    
-    switch(err_code) 
+
+    switch(err_code)
     {
         case NRFX_ERROR_INVALID_STATE:
             return RT_EINVAL;
@@ -372,7 +372,7 @@ int rt_hw_pin_init(void)
         default:
             return RT_ERROR;;
     }
-    
+
 }
 INIT_BOARD_EXPORT(rt_hw_pin_init);
 
@@ -389,90 +389,90 @@ INIT_BOARD_EXPORT(rt_hw_pin_init);
 
 void button_1_callback(void *args)
 {
-	static int flag1 = 0;
-	if(flag1 == 0)
-	{
-		flag1 = 1;
-		rt_pin_write(DK_BOARD_LED_1, PIN_LOW);
-	}
-	else
-	{
-		flag1 = 0;
-		rt_pin_write(DK_BOARD_LED_1, PIN_HIGH);
-	}
+    static int flag1 = 0;
+    if(flag1 == 0)
+    {
+        flag1 = 1;
+        rt_pin_write(DK_BOARD_LED_1, PIN_LOW);
+    }
+    else
+    {
+        flag1 = 0;
+        rt_pin_write(DK_BOARD_LED_1, PIN_HIGH);
+    }
 }
 void button_2_callback(void *args)
 {
-	static int flag2 = 0;
-	if(flag2 == 0)
-	{
-		flag2 = 1;
-		rt_pin_write(DK_BOARD_LED_2, PIN_LOW);
-	}
-	else
-	{
-		flag2 = 0;
-		rt_pin_write(DK_BOARD_LED_2, PIN_HIGH);
-	}
+    static int flag2 = 0;
+    if(flag2 == 0)
+    {
+        flag2 = 1;
+        rt_pin_write(DK_BOARD_LED_2, PIN_LOW);
+    }
+    else
+    {
+        flag2 = 0;
+        rt_pin_write(DK_BOARD_LED_2, PIN_HIGH);
+    }
 }
 void button_3_callback(void *args)
 {
-	static int flag3 = 0;
-	if(flag3 == 0)
-	{
-		flag3 = 1;
-		rt_pin_write(DK_BOARD_LED_3, PIN_LOW);
-	}
-	else
-	{
-		flag3 = 0;
-		rt_pin_write(DK_BOARD_LED_3, PIN_HIGH);
-	}
+    static int flag3 = 0;
+    if(flag3 == 0)
+    {
+        flag3 = 1;
+        rt_pin_write(DK_BOARD_LED_3, PIN_LOW);
+    }
+    else
+    {
+        flag3 = 0;
+        rt_pin_write(DK_BOARD_LED_3, PIN_HIGH);
+    }
 }
 void button_4_callback(void *args)
 {
-	static int flag4 = 0;
-	if(flag4 == 0)
-	{
-		flag4 = 1;
-		rt_pin_write(DK_BOARD_LED_4, PIN_LOW);
-	}
-	else
-	{
-		flag4 = 0;
-		rt_pin_write(DK_BOARD_LED_4, PIN_HIGH);
-	}
+    static int flag4 = 0;
+    if(flag4 == 0)
+    {
+        flag4 = 1;
+        rt_pin_write(DK_BOARD_LED_4, PIN_LOW);
+    }
+    else
+    {
+        flag4 = 0;
+        rt_pin_write(DK_BOARD_LED_4, PIN_HIGH);
+    }
 }
 
 void gpio_sample(void)
 {
-	rt_err_t err_code;
-    
-	rt_pin_mode(DK_BOARD_LED_1, PIN_MODE_OUTPUT);
-	rt_pin_mode(DK_BOARD_LED_2, PIN_MODE_OUTPUT);
-	rt_pin_mode(DK_BOARD_LED_3, PIN_MODE_OUTPUT);
-	rt_pin_mode(DK_BOARD_LED_4, PIN_MODE_OUTPUT);
+    rt_err_t err_code;
 
-	rt_pin_write(DK_BOARD_LED_1, PIN_HIGH);
-	rt_pin_write(DK_BOARD_LED_2, PIN_HIGH);
-	rt_pin_write(DK_BOARD_LED_3, PIN_HIGH);
-	rt_pin_write(DK_BOARD_LED_4, PIN_HIGH);
-	
-	err_code =  rt_pin_attach_irq(DK_BOARD_BUTTON_1, PIN_IRQ_MODE_FALLING,
+    rt_pin_mode(DK_BOARD_LED_1, PIN_MODE_OUTPUT);
+    rt_pin_mode(DK_BOARD_LED_2, PIN_MODE_OUTPUT);
+    rt_pin_mode(DK_BOARD_LED_3, PIN_MODE_OUTPUT);
+    rt_pin_mode(DK_BOARD_LED_4, PIN_MODE_OUTPUT);
+
+    rt_pin_write(DK_BOARD_LED_1, PIN_HIGH);
+    rt_pin_write(DK_BOARD_LED_2, PIN_HIGH);
+    rt_pin_write(DK_BOARD_LED_3, PIN_HIGH);
+    rt_pin_write(DK_BOARD_LED_4, PIN_HIGH);
+
+    err_code =  rt_pin_attach_irq(DK_BOARD_BUTTON_1, PIN_IRQ_MODE_FALLING,
                                     button_1_callback, (void*) true); //true: hi_accuracy(IN_EVENT),false: lo_accuracy(PORT_EVENT)
-	rt_pin_irq_enable(DK_BOARD_BUTTON_1, PIN_IRQ_ENABLE);
-	
-	err_code =  rt_pin_attach_irq(DK_BOARD_BUTTON_2, PIN_IRQ_MODE_FALLING,
+    rt_pin_irq_enable(DK_BOARD_BUTTON_1, PIN_IRQ_ENABLE);
+
+    err_code =  rt_pin_attach_irq(DK_BOARD_BUTTON_2, PIN_IRQ_MODE_FALLING,
                                     button_2_callback, (void*) true); //true: hi_accuracy(IN_EVENT),false: lo_accuracy(PORT_EVENT)
-	rt_pin_irq_enable(DK_BOARD_BUTTON_2, PIN_IRQ_ENABLE);
-	
-	err_code =  rt_pin_attach_irq(DK_BOARD_BUTTON_3, PIN_IRQ_MODE_FALLING,
+    rt_pin_irq_enable(DK_BOARD_BUTTON_2, PIN_IRQ_ENABLE);
+
+    err_code =  rt_pin_attach_irq(DK_BOARD_BUTTON_3, PIN_IRQ_MODE_FALLING,
                                     button_3_callback, (void*) true); //true: hi_accuracy(IN_EVENT),false: lo_accuracy(PORT_EVENT)
-	rt_pin_irq_enable(DK_BOARD_BUTTON_3, PIN_IRQ_ENABLE);
-	
-	err_code =  rt_pin_attach_irq(DK_BOARD_BUTTON_4, PIN_IRQ_MODE_FALLING,
+    rt_pin_irq_enable(DK_BOARD_BUTTON_3, PIN_IRQ_ENABLE);
+
+    err_code =  rt_pin_attach_irq(DK_BOARD_BUTTON_4, PIN_IRQ_MODE_FALLING,
                                     button_4_callback, (void*) false); //true: hi_accuracy(IN_EVENT),false: lo_accuracy(PORT_EVENT)
-	rt_pin_irq_enable(DK_BOARD_BUTTON_4, PIN_IRQ_ENABLE);	
+    rt_pin_irq_enable(DK_BOARD_BUTTON_4, PIN_IRQ_ENABLE);
 }
 MSH_CMD_EXPORT(gpio_sample, gpio sample);
 
diff --git a/bsp/nrf5x/libraries/drivers/drv_gpio.h b/bsp/nrf5x/libraries/drivers/drv_gpio.h
index bb04697ab5..9db654e169 100644
--- a/bsp/nrf5x/libraries/drivers/drv_gpio.h
+++ b/bsp/nrf5x/libraries/drivers/drv_gpio.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/nrf5x/libraries/drivers/drv_i2c.c b/bsp/nrf5x/libraries/drivers/drv_i2c.c
index fedb00b2d4..46a999dc7f 100644
--- a/bsp/nrf5x/libraries/drivers/drv_i2c.c
+++ b/bsp/nrf5x/libraries/drivers/drv_i2c.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -8,7 +8,7 @@
  * 2020-11-15     xckhmf       First Verison
  *
  */
- 
+
 #include 
 #include 
 #include 
@@ -23,7 +23,7 @@ typedef struct
 }drv_i2c_cfg_t;
 
 #ifdef BSP_USING_I2C0
-static drv_i2c_cfg_t drv_i2c_0 = 
+static drv_i2c_cfg_t drv_i2c_0 =
 {
     .freq = NRF_TWIM_FREQ_400K,
     .scl_pin = BSP_I2C0_SCL_PIN,
@@ -33,7 +33,7 @@ static drv_i2c_cfg_t drv_i2c_0 =
 static struct rt_i2c_bus_device i2c0_bus;
 #endif
 #ifdef BSP_USING_I2C1
-static drv_i2c_cfg_t drv_i2c_1 = 
+static drv_i2c_cfg_t drv_i2c_1 =
 {
     .freq = NRF_TWIM_FREQ_400K,
     .scl_pin = BSP_I2C1_SCL_PIN,
@@ -42,17 +42,17 @@ static drv_i2c_cfg_t drv_i2c_1 =
 };
 static struct rt_i2c_bus_device i2c1_bus;
 #endif
-static int twi_master_init(struct rt_i2c_bus_device *bus) 
+static int twi_master_init(struct rt_i2c_bus_device *bus)
 {
     nrfx_err_t rtn;
     nrfx_twim_config_t config = NRFX_TWIM_DEFAULT_CONFIG(0,0);
     drv_i2c_cfg_t *p_cfg = bus->priv;
     nrfx_twim_t const * p_instance = &p_cfg->twi_instance;
-    
+
     config.frequency = p_cfg->freq;
     config.scl = p_cfg->scl_pin;
     config.sda = p_cfg->sda_pin;
-    
+
     nrfx_twi_twim_bus_recover(config.scl,config.sda);
 
     rtn = nrfx_twim_init(p_instance,&config,NULL,NULL);
@@ -67,8 +67,8 @@ static rt_size_t _master_xfer(struct rt_i2c_bus_device *bus,
     nrfx_twim_t const * p_instance = &((drv_i2c_cfg_t *)bus->priv)->twi_instance;
     nrfx_err_t ret = NRFX_ERROR_INTERNAL;
     uint32_t no_stop_flag = 0;
-    
-    nrfx_twim_xfer_desc_t xfer = NRFX_TWIM_XFER_DESC_TX(msgs->addr,msgs->buf, msgs->len);    
+
+    nrfx_twim_xfer_desc_t xfer = NRFX_TWIM_XFER_DESC_TX(msgs->addr,msgs->buf, msgs->len);
     if((msgs->flags & 0x01) == RT_I2C_WR)
     {
         xfer.type = NRFX_TWIM_XFER_TX;
@@ -83,7 +83,7 @@ static rt_size_t _master_xfer(struct rt_i2c_bus_device *bus,
     }
     ret = nrfx_twim_xfer(p_instance,&xfer,no_stop_flag);
     return (ret == NRFX_SUCCESS) ? msgs->len : 0;
-	
+
 }
 
 static const struct rt_i2c_bus_device_ops _i2c_ops =
@@ -94,23 +94,23 @@ static const struct rt_i2c_bus_device_ops _i2c_ops =
 };
 
 int rt_hw_i2c_init(void)
-{ 
+{
 #ifdef BSP_USING_I2C0
     i2c0_bus.ops= &_i2c_ops;
     i2c0_bus.timeout = 0;
     i2c0_bus.priv = (void *)&drv_i2c_0;
     twi_master_init(&i2c0_bus);
-    rt_i2c_bus_device_register(&i2c0_bus, "i2c0");  
+    rt_i2c_bus_device_register(&i2c0_bus, "i2c0");
 #endif
 #ifdef BSP_USING_I2C1
     i2c1_bus.ops= &_i2c_ops;
     i2c1_bus.timeout = 0;
     i2c1_bus.priv = (void *)&drv_i2c_1;
     twi_master_init(&i2c1_bus);
-    rt_i2c_bus_device_register(&i2c1_bus, "i2c1");  
+    rt_i2c_bus_device_register(&i2c1_bus, "i2c1");
 #endif
     return 0;
 }
 
-INIT_BOARD_EXPORT(rt_hw_i2c_init);  
+INIT_BOARD_EXPORT(rt_hw_i2c_init);
 #endif /* defined(BSP_USING_I2C0) || defined(BSP_USING_I2C1) */
diff --git a/bsp/nrf5x/libraries/drivers/drv_i2c.h b/bsp/nrf5x/libraries/drivers/drv_i2c.h
index e3843927c1..8efe73ba48 100644
--- a/bsp/nrf5x/libraries/drivers/drv_i2c.h
+++ b/bsp/nrf5x/libraries/drivers/drv_i2c.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/nrf5x/libraries/drivers/drv_pwm.c b/bsp/nrf5x/libraries/drivers/drv_pwm.c
index 4d7c036ce5..3f9860343e 100644
--- a/bsp/nrf5x/libraries/drivers/drv_pwm.c
+++ b/bsp/nrf5x/libraries/drivers/drv_pwm.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -21,7 +21,7 @@
 struct mcu_pwm
 {
     struct rt_device_pwm pwm_device;
-    
+
     nrfx_pwm_t *pwm_handle;
     nrf_pwm_values_individual_t m_demo1_seq_values;
     nrf_pwm_sequence_t m_demo1_seq;
@@ -429,4 +429,4 @@ static int pwm_led_sample(int argc, char *argv[])
 }
 MSH_CMD_EXPORT(pwm_led_sample, pwm sample);
 
-#endif
\ No newline at end of file
+#endif
diff --git a/bsp/nrf5x/libraries/drivers/drv_qspi_flash.c b/bsp/nrf5x/libraries/drivers/drv_qspi_flash.c
index 18e6671a96..ba4923283d 100644
--- a/bsp/nrf5x/libraries/drivers/drv_qspi_flash.c
+++ b/bsp/nrf5x/libraries/drivers/drv_qspi_flash.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/nrf5x/libraries/drivers/drv_rtc.c b/bsp/nrf5x/libraries/drivers/drv_rtc.c
index ab65192395..e05538d617 100644
--- a/bsp/nrf5x/libraries/drivers/drv_rtc.c
+++ b/bsp/nrf5x/libraries/drivers/drv_rtc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -42,7 +42,7 @@ static uint32_t tick = 0;
 static void rtc_callback(nrfx_rtc_int_type_t int_type)
 {
     static uint32_t count = 0;
-    
+
     if (int_type == NRFX_RTC_INT_TICK)
     {
        count++;
diff --git a/bsp/nrf5x/libraries/drivers/drv_spi.c b/bsp/nrf5x/libraries/drivers/drv_spi.c
index ce4bfeb575..1f58cca9a2 100644
--- a/bsp/nrf5x/libraries/drivers/drv_spi.c
+++ b/bsp/nrf5x/libraries/drivers/drv_spi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -40,7 +40,7 @@ static struct nrfx_drv_spi_config spi_config[] =
 static struct nrfx_drv_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])];
 
 //Configure SPI bus pins using the menuconfig
-static struct nrfx_drv_spi_pin_config bsp_spi_pin[] = 
+static struct nrfx_drv_spi_pin_config bsp_spi_pin[] =
 {
 #ifdef BSP_USING_SPI0
     {
@@ -102,7 +102,7 @@ nrfx_spi_evt_handler_t spi_handler[] = {spi0_handler, spi1_handler, spi2_handler
 
 /**
   * @brief  This function config spi bus
-  * @param  device    
+  * @param  device
   * @param  configuration
   * @retval RT_EOK / RT_ERROR
   */
@@ -118,7 +118,7 @@ static rt_err_t spi_configure(struct rt_spi_device *device,
     RT_ASSERT(index != 0xFF);
 
     nrfx_spi_t spi = spi_bus_obj[index].spi;
-    nrfx_spi_config_t config = NRFX_SPI_DEFAULT_CONFIG(bsp_spi_pin[index].sck_pin, 
+    nrfx_spi_config_t config = NRFX_SPI_DEFAULT_CONFIG(bsp_spi_pin[index].sck_pin,
         bsp_spi_pin[index].mosi_pin, bsp_spi_pin[index].miso_pin, NRFX_SPI_PIN_NOT_USED);
 
     /* spi config ss pin */
@@ -211,7 +211,7 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
         nrf_gpio_pin_clear((uint32_t)device->parent.user_data);
     }
     p_xfer_desc.p_rx_buffer = message->recv_buf;
-    p_xfer_desc.rx_length = message->length;  
+    p_xfer_desc.rx_length = message->length;
     p_xfer_desc.p_tx_buffer = message->send_buf;
     p_xfer_desc.tx_length = message->length ;
     if(message->send_buf == RT_NULL)
@@ -220,7 +220,7 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
     }
     if(message->recv_buf == RT_NULL)
     {
-        p_xfer_desc.rx_length = 0;          
+        p_xfer_desc.rx_length = 0;
     }
 
     nrf_ret = nrfx_spi_xfer(p_instance, &p_xfer_desc, 0);
@@ -228,14 +228,14 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
     {
         nrf_gpio_pin_set((uint32_t)device->parent.user_data);
     }
-    
+
     if( NRFX_SUCCESS != nrf_ret)
     {
         return 0;
     }
     else
     {
-        return message->length;        
+        return message->length;
     }
 }
 
diff --git a/bsp/nrf5x/libraries/drivers/drv_spi.h b/bsp/nrf5x/libraries/drivers/drv_spi.h
index abd595bda3..891818f5ec 100644
--- a/bsp/nrf5x/libraries/drivers/drv_spi.h
+++ b/bsp/nrf5x/libraries/drivers/drv_spi.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -57,7 +57,7 @@ struct nrfx_drv_spi_config
     nrfx_spi_t spi;
 };
 
-struct nrfx_drv_spi 
+struct nrfx_drv_spi
 {
     nrfx_spi_t spi;    /* nrfx spi driver instance. */
     nrfx_spi_config_t   spi_config; /* nrfx spi config Configuration */
diff --git a/bsp/nrf5x/libraries/drivers/drv_uart.c b/bsp/nrf5x/libraries/drivers/drv_uart.c
index 7f7d4ba7d6..8ee6992f02 100644
--- a/bsp/nrf5x/libraries/drivers/drv_uart.c
+++ b/bsp/nrf5x/libraries/drivers/drv_uart.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -44,16 +44,16 @@ drv_uart_cfg_t m_uart0_cfg = {
 
 #ifdef BSP_USING_UART0
 static void uart0_event_hander(nrfx_uart_event_t const *p_event,void *p_context)
-{   
+{
     if (p_event->type == NRFX_UART_EVT_RX_DONE)
     {
         if(p_event->data.rxtx.bytes == 1)
         {
             m_uart0_cfg.rx_length = p_event->data.rxtx.bytes;
-            
+
             /* rx_byte equal p_data  */
-            //m_uart0_cfg.rx_byte = *(p_event->data.rxtx.p_data); 
-            
+            //m_uart0_cfg.rx_byte = *(p_event->data.rxtx.p_data);
+
             rt_hw_serial_isr(m_uart0_cfg.serial, RT_SERIAL_EVENT_RX_IND);
         }
         nrfx_uart_rx(&(m_uart0_cfg.uart),&m_uart0_cfg.rx_byte,1);
@@ -72,7 +72,7 @@ static rt_err_t _uart_cfg(struct rt_serial_device *serial, struct serial_configu
 
     RT_ASSERT(serial != RT_NULL);
     RT_ASSERT(cfg != RT_NULL);
-  
+
     if (serial->parent.user_data == RT_NULL)
     {
         return -RT_ERROR;
@@ -107,7 +107,7 @@ static rt_err_t _uart_cfg(struct rt_serial_device *serial, struct serial_configu
     config.hal_cfg.hwfc = NRF_UART_HWFC_DISABLED;
     config.pselrxd = instance->rx_pin;
     config.pseltxd = instance->tx_pin;
-    
+
     nrfx_uart_init(&(instance->uart), &config, instance->event_handler);
     nrfx_uart_rx(&(instance->uart),&(instance->rx_byte),1);
     nrf_uart_int_disable(instance->uart.p_reg, NRF_UART_INT_MASK_TXDRDY);
@@ -187,7 +187,7 @@ static int _uart_putc(struct rt_serial_device *serial, char c)
     while (!nrf_uart_event_check(instance->uart.p_reg, NRF_UART_EVENT_TXDRDY))
     {
         //wait for TXD send
-    }    
+    }
     return rtn;
 }
 
@@ -205,7 +205,7 @@ static int _uart_getc(struct rt_serial_device *serial)
     if (serial->parent.user_data != RT_NULL)
     {
         instance = (drv_uart_cfg_t*)serial->parent.user_data;
-    }  
+    }
     if(instance->rx_length)
     {
         ch = instance->rx_byte;
diff --git a/bsp/nrf5x/libraries/drivers/drv_uarte.c b/bsp/nrf5x/libraries/drivers/drv_uarte.c
index 680ae599f3..41725b50d5 100644
--- a/bsp/nrf5x/libraries/drivers/drv_uarte.c
+++ b/bsp/nrf5x/libraries/drivers/drv_uarte.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -68,7 +68,7 @@ static void uarte_evt_handler(nrfx_uarte_event_t const * p_event,
         case NRFX_UARTE_EVT_ERROR:
             (void)nrfx_uarte_rx(&(p_cb->uarte_instance), p_cb->rx_buffer, 1);
             break;
-        
+
         case NRFX_UARTE_EVT_TX_DONE:
             if(p_cb->serial->parent.open_flag&RT_DEVICE_FLAG_INT_TX)
             {
@@ -90,7 +90,7 @@ static rt_err_t _uart_cfg(struct rt_serial_device *serial, struct serial_configu
 
     RT_ASSERT(serial != RT_NULL);
     RT_ASSERT(cfg != RT_NULL);
-  
+
     if (serial->parent.user_data == RT_NULL)
     {
         return -RT_ERROR;
@@ -145,11 +145,11 @@ static rt_err_t _uart_cfg(struct rt_serial_device *serial, struct serial_configu
                             NRF_UARTE_PARITY_EXCLUDED:NRF_UARTE_PARITY_INCLUDED;
     config.hal_cfg.hwfc = NRF_UARTE_HWFC_DISABLED;
     config.pselrxd = p_cb->rx_pin;
-    config.pseltxd = p_cb->tx_pin;   
+    config.pseltxd = p_cb->tx_pin;
     config.p_context = (void *)p_cb;
 
     nrfx_uarte_init(&(p_cb->uarte_instance),(nrfx_uarte_config_t const *)&config,uarte_evt_handler);
-    nrfx_uarte_rx(&(p_cb->uarte_instance),p_cb->rx_buffer,1);    
+    nrfx_uarte_rx(&(p_cb->uarte_instance),p_cb->rx_buffer,1);
     p_cb->isInit = true;
     return RT_EOK;
 }
@@ -227,7 +227,7 @@ static int _uart_putc(struct rt_serial_device *serial, char c)
         while(nrfx_uarte_tx_in_progress(&(p_cb->uarte_instance)))
         {
         }
-    } 
+    }
     return rtn;
 }
 
@@ -240,7 +240,7 @@ static int _uart_getc(struct rt_serial_device *serial)
     if (serial->parent.user_data != RT_NULL)
     {
         p_cb = (drv_uart_cb_t*)serial->parent.user_data;
-    }  
+    }
     if(p_cb->rx_length)
     {
         ch = p_cb->rx_buffer[0];
@@ -260,15 +260,15 @@ void rt_hw_uart_init(void)
 {
     struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
 
-#ifdef BSP_USING_UART0 
+#ifdef BSP_USING_UART0
     m_serial_0.config = config;
     m_serial_0.ops = &_uart_ops;
     m_uarte0_cb.serial = &m_serial_0;
     rt_hw_serial_register(&m_serial_0, "uart0", \
                             RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX ,  &m_uarte0_cb);
 #endif  /* BSP_USING_UART0 */
-    
-#ifdef BSP_USING_UART1 
+
+#ifdef BSP_USING_UART1
     m_serial_1.config = config;
     m_serial_1.ops = &_uart_ops;
     m_uarte1_cb.serial = &m_serial_1;
diff --git a/bsp/nrf5x/libraries/drivers/drv_uarte.h b/bsp/nrf5x/libraries/drivers/drv_uarte.h
index f07ddafd79..c8705f0cdc 100644
--- a/bsp/nrf5x/libraries/drivers/drv_uarte.h
+++ b/bsp/nrf5x/libraries/drivers/drv_uarte.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/nrf5x/libraries/drivers/drv_wdt.c b/bsp/nrf5x/libraries/drivers/drv_wdt.c
index 2fe4f6b2dc..168b1b8ac5 100644
--- a/bsp/nrf5x/libraries/drivers/drv_wdt.c
+++ b/bsp/nrf5x/libraries/drivers/drv_wdt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/nrf5x/libraries/templates/nrf52x/applications/application.c b/bsp/nrf5x/libraries/templates/nrf52x/applications/application.c
deleted file mode 100644
index 1135d82e16..0000000000
--- a/bsp/nrf5x/libraries/templates/nrf52x/applications/application.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * File      : application.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2015, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2015-03-01     Yangfs       the first version
- * 2015-03-27     Bernard      code cleanup.
- */
-
-/**
- * @addtogroup NRF52832
- */
-/*@{*/
-
-#include 
-
-#ifdef RT_USING_FINSH
-#include 
-#include 
-#endif
-
-void rt_init_thread_entry(void* parameter)
-{
-    extern rt_err_t ble_init(void);
-
-    ble_init();
-}
-
-int rt_application_init(void)
-{
-    rt_thread_t tid;
-
-    tid = rt_thread_create("init", rt_init_thread_entry, RT_NULL, 1024,
-                            RT_THREAD_PRIORITY_MAX / 3, 20);
-    if (tid != RT_NULL)
-        rt_thread_startup(tid);
-
-    return 0;
-}
-
-
-/*@}*/
diff --git a/bsp/nrf5x/libraries/templates/nrf52x/applications/ble_nus_app.c b/bsp/nrf5x/libraries/templates/nrf52x/applications/ble_nus_app.c
deleted file mode 100644
index 5739e91c7e..0000000000
--- a/bsp/nrf5x/libraries/templates/nrf52x/applications/ble_nus_app.c
+++ /dev/null
@@ -1,681 +0,0 @@
-#include "nordic_common.h"
-#include "nrf.h"
-#include "ble_hci.h"
-#include "ble_advdata.h"
-#include "ble_advertising.h"
-#include "ble_conn_params.h"
-#include "softdevice_handler.h"
-#include "nrf_ble_gatt.h"
-#include "app_timer.h"
-#include "ble_nus.h"
-#include "app_util_platform.h"
-
-#include 
-
-typedef rt_size_t (*BLE_NOTIFY_T)(rt_uint8_t *buf, rt_uint16_t size);
-
-#define STACK_EVT_MQ_NUM        10
-
-#define FAST_ADV()          \
-    do {                    \
-        uint32_t err_code;  \
-        err_code = ble_advertising_start(BLE_ADV_MODE_FAST);    \
-        APP_ERROR_CHECK(err_code);  \
-    } while(0)
-
-typedef enum
-{
-    STACK_EV_DISCON = 1,
-    STACK_EV_DISPATCH = 2,
-    STACK_EV_KEY = 4,
-} STACK_EV_E;
-
-typedef struct
-{
-    rt_list_t node;
-    void* evt;
-} evt_list_t;
-
-typedef enum
-{
-    STACK_STATE_IDLE = 0,
-    STACK_STATE_ADV = 1,
-    STACK_STATE_CON = 2,
-    STACK_STATE_DISC = 3
-} STACK_STATE_E;
-
-STACK_STATE_E stack_state = STACK_STATE_IDLE;
-
-rt_event_t stack_event;
-rt_sem_t sd_evt_sem;
-rt_mq_t stack_evt_mq;
-rt_uint8_t *evt_sample;
-
-BLE_NOTIFY_T rx_notify = RT_NULL;
-
-// Low frequency clock source to be used by the SoftDevice
-#define NRF_CLOCK_LFCLKSRC      {.source        = NRF_CLOCK_LF_SRC_XTAL,            \
-                                 .rc_ctiv       = 0,                                \
-                                 .rc_temp_ctiv  = 0,                                \
-                                 .xtal_accuracy = NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM}
-
-
-#define CONN_CFG_TAG                    1                                           /**< A tag that refers to the BLE stack configuration we set with @ref sd_ble_cfg_set. Default tag is @ref BLE_CONN_CFG_TAG_DEFAULT. */
-
-#define APP_FEATURE_NOT_SUPPORTED       BLE_GATT_STATUS_ATTERR_APP_BEGIN + 2        /**< Reply when unsupported features are requested. */
-
-#define DEVICE_NAME                     "Nordic_UART"                               /**< Name of device. Will be included in the advertising data. */
-#define NUS_SERVICE_UUID_TYPE           BLE_UUID_TYPE_VENDOR_BEGIN                  /**< UUID type for the Nordic UART Service (vendor specific). */
-
-#define APP_ADV_INTERVAL                64                                          /**< The advertising interval (in units of 0.625 ms. This value corresponds to 40 ms). */
-#define APP_ADV_TIMEOUT_IN_SECONDS      30                                         /**< The advertising timeout (in units of seconds). */
-
-#define MIN_CONN_INTERVAL               MSEC_TO_UNITS(20, UNIT_1_25_MS)             /**< Minimum acceptable connection interval (20 ms), Connection interval uses 1.25 ms units. */
-#define MAX_CONN_INTERVAL               MSEC_TO_UNITS(75, UNIT_1_25_MS)             /**< Maximum acceptable connection interval (75 ms), Connection interval uses 1.25 ms units. */
-#define SLAVE_LATENCY                   0                                           /**< Slave latency. */
-#define CONN_SUP_TIMEOUT                MSEC_TO_UNITS(4000, UNIT_10_MS)             /**< Connection supervisory timeout (4 seconds), Supervision Timeout uses 10 ms units. */
-#define FIRST_CONN_PARAMS_UPDATE_DELAY  APP_TIMER_TICKS(5000)                       /**< Time from initiating event (connect or start of notification) to first time sd_ble_gap_conn_param_update is called (5 seconds). */
-#define NEXT_CONN_PARAMS_UPDATE_DELAY   APP_TIMER_TICKS(30000)                      /**< Time between each call to sd_ble_gap_conn_param_update after the first call (30 seconds). */
-#define MAX_CONN_PARAMS_UPDATE_COUNT    3                                           /**< Number of attempts before giving up the connection parameter negotiation. */
-
-#define DEAD_BEEF                       0xDEADBEEF                                  /**< Value used as error code on stack dump, can be used to identify stack location on stack unwind. */
-
-#define UART_TX_BUF_SIZE                256                                         /**< UART TX buffer size. */
-#define UART_RX_BUF_SIZE                256                                         /**< UART RX buffer size. */
-
-static ble_nus_t                        m_nus;                                      /**< Structure to identify the Nordic UART Service. */
-static uint16_t                         m_conn_handle = BLE_CONN_HANDLE_INVALID;    /**< Handle of the current connection. */
-
-static nrf_ble_gatt_t                   m_gatt;                                     /**< GATT module instance. */
-static ble_uuid_t                       m_adv_uuids[] = {{BLE_UUID_NUS_SERVICE, NUS_SERVICE_UUID_TYPE}};  /**< Universally unique service identifier. */
-static uint16_t                         m_ble_nus_max_data_len = BLE_GATT_ATT_MTU_DEFAULT - 3;  /**< Maximum length of data (in bytes) that can be transmitted to the peer by the Nordic UART service module. */
-
-/**@brief Function for assert macro callback.
- *
- * @details This function will be called in case of an assert in the SoftDevice.
- *
- * @warning This handler is an example only and does not fit a final product. You need to analyse
- *          how your product is supposed to react in case of Assert.
- * @warning On assert from the SoftDevice, the system can only recover on reset.
- *
- * @param[in] line_num    Line number of the failing ASSERT call.
- * @param[in] p_file_name File name of the failing ASSERT call.
- */
-void assert_nrf_callback(uint16_t line_num, const uint8_t * p_file_name)
-{
-    app_error_handler(DEAD_BEEF, line_num, p_file_name);
-}
-
-
-/**@brief Function for the GAP initialization.
- *
- * @details This function will set up all the necessary GAP (Generic Access Profile) parameters of
- *          the device. It also sets the permissions and appearance.
- */
-static void gap_params_init(void)
-{
-    uint32_t                err_code;
-    ble_gap_conn_params_t   gap_conn_params;
-    ble_gap_conn_sec_mode_t sec_mode;
-
-    BLE_GAP_CONN_SEC_MODE_SET_OPEN(&sec_mode);
-
-    err_code = sd_ble_gap_device_name_set(&sec_mode,
-                                          (const uint8_t *) DEVICE_NAME,
-                                          strlen(DEVICE_NAME));
-    APP_ERROR_CHECK(err_code);
-
-    memset(&gap_conn_params, 0, sizeof(gap_conn_params));
-
-    gap_conn_params.min_conn_interval = MIN_CONN_INTERVAL;
-    gap_conn_params.max_conn_interval = MAX_CONN_INTERVAL;
-    gap_conn_params.slave_latency     = SLAVE_LATENCY;
-    gap_conn_params.conn_sup_timeout  = CONN_SUP_TIMEOUT;
-
-    err_code = sd_ble_gap_ppcp_set(&gap_conn_params);
-    APP_ERROR_CHECK(err_code);
-}
-
-
-/**@brief Function for handling the data from the Nordic UART Service.
- *
- * @details This function will process the data received from the Nordic UART BLE Service and send
- *          it to the UART module.
- *
- * @param[in] p_nus    Nordic UART Service structure.
- * @param[in] p_data   Data to be send to UART module.
- * @param[in] length   Length of the data.
- */
-/**@snippet [Handling the data received over BLE] */
-static void nus_data_handler(ble_nus_t * p_nus, uint8_t * p_data, uint16_t length)
-{
-    rt_kprintf("Received data from BLE NUS. Writing data on UART.\r\n");
-
-    for (uint32_t i = 0; i < length; i++)
-    {
-        rt_kprintf("%02x ", p_data[i]);
-    }
-
-    // ble_send(p_data, length);
-
-    if (rx_notify != RT_NULL)
-    {
-        rx_notify(p_data, length);
-    }
-}
-/**@snippet [Handling the data received over BLE] */
-
-
-/**@brief Function for initializing services that will be used by the application.
- */
-static void services_init(void)
-{
-    uint32_t       err_code;
-    ble_nus_init_t nus_init;
-
-    memset(&nus_init, 0, sizeof(nus_init));
-
-    nus_init.data_handler = nus_data_handler;
-
-    err_code = ble_nus_init(&m_nus, &nus_init);
-    APP_ERROR_CHECK(err_code);
-}
-
-
-/**@brief Function for handling an event from the Connection Parameters Module.
- *
- * @details This function will be called for all events in the Connection Parameters Module
- *          which are passed to the application.
- *
- * @note All this function does is to disconnect. This could have been done by simply setting
- *       the disconnect_on_fail config parameter, but instead we use the event handler
- *       mechanism to demonstrate its use.
- *
- * @param[in] p_evt  Event received from the Connection Parameters Module.
- */
-static void on_conn_params_evt(ble_conn_params_evt_t * p_evt)
-{
-    uint32_t err_code;
-
-    if (p_evt->evt_type == BLE_CONN_PARAMS_EVT_FAILED)
-    {
-        err_code = sd_ble_gap_disconnect(m_conn_handle, BLE_HCI_CONN_INTERVAL_UNACCEPTABLE);
-        APP_ERROR_CHECK(err_code);
-    }
-}
-
-
-/**@brief Function for handling errors from the Connection Parameters module.
- *
- * @param[in] nrf_error  Error code containing information about what went wrong.
- */
-static void conn_params_error_handler(uint32_t nrf_error)
-{
-    APP_ERROR_HANDLER(nrf_error);
-}
-
-
-/**@brief Function for initializing the Connection Parameters module.
- */
-static void conn_params_init(void)
-{
-    uint32_t               err_code;
-    ble_conn_params_init_t cp_init;
-
-    memset(&cp_init, 0, sizeof(cp_init));
-
-    cp_init.p_conn_params                  = NULL;
-    cp_init.first_conn_params_update_delay = FIRST_CONN_PARAMS_UPDATE_DELAY;
-    cp_init.next_conn_params_update_delay  = NEXT_CONN_PARAMS_UPDATE_DELAY;
-    cp_init.max_conn_params_update_count   = MAX_CONN_PARAMS_UPDATE_COUNT;
-    cp_init.start_on_notify_cccd_handle    = BLE_GATT_HANDLE_INVALID;
-    cp_init.disconnect_on_fail             = false;
-    cp_init.evt_handler                    = on_conn_params_evt;
-    cp_init.error_handler                  = conn_params_error_handler;
-
-    err_code = ble_conn_params_init(&cp_init);
-    APP_ERROR_CHECK(err_code);
-}
-
-/**@brief Function for handling advertising events.
- *
- * @details This function will be called for advertising events which are passed to the application.
- *
- * @param[in] ble_adv_evt  Advertising event.
- */
-static void on_adv_evt(ble_adv_evt_t ble_adv_evt)
-{
-    // uint32_t err_code;
-
-    switch (ble_adv_evt)
-    {
-        case BLE_ADV_EVT_FAST:
-            // err_code = bsp_indication_set(BSP_INDICATE_ADVERTISING);
-            // APP_ERROR_CHECK(err_code);
-            stack_state = STACK_STATE_ADV;
-            rt_kprintf("ble fast advert\n");
-            break;
-        case BLE_ADV_EVT_IDLE:
-            // sleep_mode_enter();
-            stack_state = STACK_STATE_IDLE;
-            rt_kprintf("advert idle\n");
-            break;
-        default:
-            break;
-    }
-}
-
-
-/**@brief Function for the application's SoftDevice event handler.
- *
- * @param[in] p_ble_evt SoftDevice event.
- */
-static void on_ble_evt(ble_evt_t * p_ble_evt)
-{
-    uint32_t err_code;
-
-    switch (p_ble_evt->header.evt_id)
-    {
-        case BLE_GAP_EVT_CONNECTED:
-            // err_code = bsp_indication_set(BSP_INDICATE_CONNECTED);
-            // APP_ERROR_CHECK(err_code);
-            m_conn_handle = p_ble_evt->evt.gap_evt.conn_handle;
-            stack_state = STACK_STATE_CON;
-            rt_kprintf("Connected\r\n");
-            break; // BLE_GAP_EVT_CONNECTED
-
-        case BLE_GAP_EVT_DISCONNECTED:
-            // err_code = bsp_indication_set(BSP_INDICATE_IDLE);
-            // APP_ERROR_CHECK(err_code);
-            m_conn_handle = BLE_CONN_HANDLE_INVALID;
-            stack_state = STACK_STATE_DISC;
-            rt_kprintf("Disconnected\r\n");
-            break; // BLE_GAP_EVT_DISCONNECTED
-
-        case BLE_GAP_EVT_SEC_PARAMS_REQUEST:
-            // Pairing not supported
-            err_code = sd_ble_gap_sec_params_reply(m_conn_handle, BLE_GAP_SEC_STATUS_PAIRING_NOT_SUPP, NULL, NULL);
-            APP_ERROR_CHECK(err_code);
-            break; // BLE_GAP_EVT_SEC_PARAMS_REQUEST
-
-        case BLE_GAP_EVT_DATA_LENGTH_UPDATE_REQUEST:
-        {
-            ble_gap_data_length_params_t dl_params;
-
-            // Clearing the struct will effectivly set members to @ref BLE_GAP_DATA_LENGTH_AUTO
-            memset(&dl_params, 0, sizeof(ble_gap_data_length_params_t));
-            err_code = sd_ble_gap_data_length_update(p_ble_evt->evt.gap_evt.conn_handle, &dl_params, NULL);
-            APP_ERROR_CHECK(err_code);
-        } break;
-
-        case BLE_GATTS_EVT_SYS_ATTR_MISSING:
-            // No system attributes have been stored.
-            err_code = sd_ble_gatts_sys_attr_set(m_conn_handle, NULL, 0, 0);
-            APP_ERROR_CHECK(err_code);
-            break; // BLE_GATTS_EVT_SYS_ATTR_MISSING
-
-        case BLE_GATTC_EVT_TIMEOUT:
-            // Disconnect on GATT Client timeout event.
-            err_code = sd_ble_gap_disconnect(p_ble_evt->evt.gattc_evt.conn_handle,
-                                             BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION);
-            APP_ERROR_CHECK(err_code);
-            break; // BLE_GATTC_EVT_TIMEOUT
-
-        case BLE_GATTS_EVT_TIMEOUT:
-            // Disconnect on GATT Server timeout event.
-            err_code = sd_ble_gap_disconnect(p_ble_evt->evt.gatts_evt.conn_handle,
-                                             BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION);
-            APP_ERROR_CHECK(err_code);
-            break; // BLE_GATTS_EVT_TIMEOUT
-
-        case BLE_EVT_USER_MEM_REQUEST:
-            err_code = sd_ble_user_mem_reply(p_ble_evt->evt.gattc_evt.conn_handle, NULL);
-            APP_ERROR_CHECK(err_code);
-            break; // BLE_EVT_USER_MEM_REQUEST
-
-        case BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST:
-        {
-            ble_gatts_evt_rw_authorize_request_t  req;
-            ble_gatts_rw_authorize_reply_params_t auth_reply;
-
-            req = p_ble_evt->evt.gatts_evt.params.authorize_request;
-
-            if (req.type != BLE_GATTS_AUTHORIZE_TYPE_INVALID)
-            {
-                if ((req.request.write.op == BLE_GATTS_OP_PREP_WRITE_REQ)     ||
-                    (req.request.write.op == BLE_GATTS_OP_EXEC_WRITE_REQ_NOW) ||
-                    (req.request.write.op == BLE_GATTS_OP_EXEC_WRITE_REQ_CANCEL))
-                {
-                    if (req.type == BLE_GATTS_AUTHORIZE_TYPE_WRITE)
-                    {
-                        auth_reply.type = BLE_GATTS_AUTHORIZE_TYPE_WRITE;
-                    }
-                    else
-                    {
-                        auth_reply.type = BLE_GATTS_AUTHORIZE_TYPE_READ;
-                    }
-                    auth_reply.params.write.gatt_status = APP_FEATURE_NOT_SUPPORTED;
-                    err_code = sd_ble_gatts_rw_authorize_reply(p_ble_evt->evt.gatts_evt.conn_handle,
-                                                               &auth_reply);
-                    APP_ERROR_CHECK(err_code);
-                }
-            }
-        } break; // BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST
-
-        default:
-            // No implementation needed.
-            break;
-    }
-}
-
-
-/**@brief Function for dispatching a SoftDevice event to all modules with a SoftDevice
- *        event handler.
- *
- * @details This function is called from the SoftDevice event interrupt handler after a
- *          SoftDevice event has been received.
- *
- * @param[in] p_ble_evt  SoftDevice event.
- */
-static void ble_evt_dispatch(ble_evt_t * p_ble_evt)
-{
-    if (rt_mq_send(stack_evt_mq, p_ble_evt, p_ble_evt->header.evt_len) != RT_EOK)
-    {
-        rt_kprintf("dispatch malloc failure\n");
-    }
-    else
-    {
-        rt_event_send(stack_event, STACK_EV_DISPATCH);
-    }
-}
-
-static rt_err_t evt_dispatch_worker(void)
-{
-    ble_evt_t * p_ble_evt = (ble_evt_t *)evt_sample;
-    rt_err_t err;
-
-    err = rt_mq_recv(stack_evt_mq, (void*)evt_sample, BLE_STACK_EVT_MSG_BUF_SIZE, RT_WAITING_NO);
-
-    if (RT_EOK == err)
-    {
-        ble_conn_params_on_ble_evt(p_ble_evt);
-        nrf_ble_gatt_on_ble_evt(&m_gatt, p_ble_evt);
-        ble_nus_on_ble_evt(&m_nus, p_ble_evt);
-        on_ble_evt(p_ble_evt);
-        ble_advertising_on_ble_evt(p_ble_evt);
-        // bsp_btn_ble_on_ble_evt(p_ble_evt);
-
-        rt_kprintf("ble evt dispatch\n");
-    }
-
-    return err;
-}
-
-static uint32_t _softdevice_evt_schedule(void)
-{
-    rt_sem_release(sd_evt_sem);
-
-    return NRF_SUCCESS;
-}
-
-/**@brief Function for the SoftDevice initialization.
- *
- * @details This function initializes the SoftDevice and the BLE event interrupt.
- */
-static void ble_stack_init(void)
-{
-    uint32_t err_code;
-
-    nrf_clock_lf_cfg_t clock_lf_cfg = NRF_CLOCK_LFCLKSRC;
-
-    // Initialize SoftDevice.
-    SOFTDEVICE_HANDLER_INIT(&clock_lf_cfg, _softdevice_evt_schedule);
-
-    // Fetch the start address of the application RAM.
-    uint32_t ram_start = 0;
-    err_code = softdevice_app_ram_start_get(&ram_start);
-    APP_ERROR_CHECK(err_code);
-
-    // Overwrite some of the default configurations for the BLE stack.
-    ble_cfg_t ble_cfg;
-
-    // Configure the maximum number of connections.
-    memset(&ble_cfg, 0, sizeof(ble_cfg));
-    ble_cfg.gap_cfg.role_count_cfg.periph_role_count  = BLE_GAP_ROLE_COUNT_PERIPH_DEFAULT;
-    ble_cfg.gap_cfg.role_count_cfg.central_role_count = 0;
-    ble_cfg.gap_cfg.role_count_cfg.central_sec_count  = 0;
-    err_code = sd_ble_cfg_set(BLE_GAP_CFG_ROLE_COUNT, &ble_cfg, ram_start);
-    APP_ERROR_CHECK(err_code);
-
-    // Configure the maximum ATT MTU.
-    memset(&ble_cfg, 0x00, sizeof(ble_cfg));
-    ble_cfg.conn_cfg.conn_cfg_tag                 = CONN_CFG_TAG;
-    ble_cfg.conn_cfg.params.gatt_conn_cfg.att_mtu = NRF_BLE_GATT_MAX_MTU_SIZE;
-    err_code = sd_ble_cfg_set(BLE_CONN_CFG_GATT, &ble_cfg, ram_start);
-    APP_ERROR_CHECK(err_code);
-
-    // Configure the maximum event length.
-    memset(&ble_cfg, 0x00, sizeof(ble_cfg));
-    ble_cfg.conn_cfg.conn_cfg_tag                     = CONN_CFG_TAG;
-    ble_cfg.conn_cfg.params.gap_conn_cfg.event_length = 320;
-    ble_cfg.conn_cfg.params.gap_conn_cfg.conn_count   = BLE_GAP_CONN_COUNT_DEFAULT;
-    err_code = sd_ble_cfg_set(BLE_CONN_CFG_GAP, &ble_cfg, ram_start);
-    APP_ERROR_CHECK(err_code);
-
-    // Enable BLE stack.
-    err_code = softdevice_enable(&ram_start);
-    APP_ERROR_CHECK(err_code);
-
-    // Subscribe for BLE events.
-    err_code = softdevice_ble_evt_handler_set(ble_evt_dispatch);
-    APP_ERROR_CHECK(err_code);
-}
-
-/**@brief Function for handling events from the GATT library. */
-static void gatt_evt_handler(nrf_ble_gatt_t * p_gatt, const nrf_ble_gatt_evt_t * p_evt)
-{
-    if ((m_conn_handle == p_evt->conn_handle) && (p_evt->evt_id == NRF_BLE_GATT_EVT_ATT_MTU_UPDATED))
-    {
-        m_ble_nus_max_data_len = p_evt->params.att_mtu_effective - OPCODE_LENGTH - HANDLE_LENGTH;
-        rt_kprintf("Data len is set to 0x%X(%d)\r\n", m_ble_nus_max_data_len, m_ble_nus_max_data_len);
-    }
-    rt_kprintf("ATT MTU exchange completed. central 0x%x peripheral 0x%x\r\n", p_gatt->att_mtu_desired_central, p_gatt->att_mtu_desired_periph);
-}
-
-/**@brief Function for initializing the GATT library. */
-static void gatt_init(void)
-{
-    ret_code_t err_code;
-
-    err_code = nrf_ble_gatt_init(&m_gatt, gatt_evt_handler);
-    APP_ERROR_CHECK(err_code);
-
-    err_code = nrf_ble_gatt_att_mtu_periph_set(&m_gatt, 64);
-    APP_ERROR_CHECK(err_code);
-}
-
-/**@brief Function for initializing the Advertising functionality.
- */
-static void advertising_init(void)
-{
-    uint32_t               err_code;
-    ble_advdata_t          advdata;
-    ble_advdata_t          scanrsp;
-    ble_adv_modes_config_t options;
-
-    // Build advertising data struct to pass into @ref ble_advertising_init.
-    memset(&advdata, 0, sizeof(advdata));
-    advdata.name_type          = BLE_ADVDATA_FULL_NAME;
-    advdata.include_appearance = false;
-    advdata.flags              = BLE_GAP_ADV_FLAGS_LE_ONLY_LIMITED_DISC_MODE;
-
-    memset(&scanrsp, 0, sizeof(scanrsp));
-    scanrsp.uuids_complete.uuid_cnt = sizeof(m_adv_uuids) / sizeof(m_adv_uuids[0]);
-    scanrsp.uuids_complete.p_uuids  = m_adv_uuids;
-
-    memset(&options, 0, sizeof(options));
-    options.ble_adv_fast_enabled  = true;
-    options.ble_adv_fast_interval = APP_ADV_INTERVAL;
-    options.ble_adv_fast_timeout  = APP_ADV_TIMEOUT_IN_SECONDS;
-
-    err_code = ble_advertising_init(&advdata, &scanrsp, &options, on_adv_evt, NULL);
-    APP_ERROR_CHECK(err_code);
-
-    ble_advertising_conn_cfg_tag_set(CONN_CFG_TAG);
-}
-
-/**@brief   Function for handling app_uart events.
- *
- * @details This function will receive a single character from the app_uart module and append it to
- *          a string. The string will be be sent over BLE when the last character received was a
- *          'new line' '\n' (hex 0x0A) or if the string has reached the maximum data length.
- */
-/**@snippet [Handling the data received over UART] */
-void uart_event_handle(rt_device_t uart)
-{
-    uint8_t data_array[BLE_NUS_MAX_DATA_LEN];
-    rt_size_t size = 0;
-    uint32_t       err_code;
-
-    size = rt_device_read(uart, 0, data_array, BLE_NUS_MAX_DATA_LEN);
-
-    if (size <= 0)
-    {
-        return;
-    }
-
-    do
-    {
-        err_code = ble_nus_string_send(&m_nus, data_array, size);
-        if ( (err_code != NRF_ERROR_INVALID_STATE) && (err_code != NRF_ERROR_BUSY) )
-        {
-            APP_ERROR_CHECK(err_code);
-        }
-    } while (err_code == NRF_ERROR_BUSY);
-}
-/**@snippet [Handling the data received over UART] */
-
-/**@brief  Function for initializing the UART module.
- */
-/**@snippet [UART Initialization] */
-static rt_bool_t _stack_init(void)
-{
-    uint32_t err_code;
-
-    stack_event = rt_event_create("stackev", RT_IPC_FLAG_FIFO);
-    sd_evt_sem = rt_sem_create("sdsem", 0, RT_IPC_FLAG_FIFO);
-    stack_evt_mq = rt_mq_create("stackmq", BLE_STACK_EVT_MSG_BUF_SIZE, STACK_EVT_MQ_NUM, RT_IPC_FLAG_FIFO);
-    evt_sample = rt_malloc(BLE_STACK_EVT_MSG_BUF_SIZE);
-
-    if (!stack_event || !sd_evt_sem || !stack_evt_mq || !evt_sample)
-    {
-        rt_kprintf("uart rx sem create failure\n");
-        return RT_FALSE;
-    }
-
-    // Initialize.
-    err_code = app_timer_init();
-    APP_ERROR_CHECK(err_code);
-
-    ble_stack_init();
-    gap_params_init();
-    gatt_init();
-    services_init();
-    advertising_init();
-    conn_params_init();
-
-    return RT_TRUE;
-}
-
-/**@brief Application main function.
- */
-static void _stack_thread(void *parameter)
-{
-    rt_tick_t next_timeout = (rt_tick_t)RT_WAITING_FOREVER;
-
-    FAST_ADV();
-    // Enter main loop.
-    for (;;)
-    {
-        rt_uint32_t event = 0;
-        rt_tick_t dispatch_timeout = RT_WAITING_NO;
-        rt_err_t result;
-
-        result = rt_event_recv(stack_event, STACK_EV_DISCON | STACK_EV_DISPATCH | STACK_EV_KEY,
-                    RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, next_timeout, &event);
-        if (result == -RT_ETIMEOUT) 
-        {
-            LOG_E("wait completed timeout");
-            continue;
-        }
-        else if (result == -RT_ERROR) 
-        {
-            LOG_E("event received error");
-            continue;
-        }
-
-        if (evt_dispatch_worker() != RT_EOK)
-        {
-            dispatch_timeout = (rt_tick_t)RT_WAITING_FOREVER;
-        }
-
-        if (event & STACK_EV_DISCON)
-        {
-            if (BLE_CONN_HANDLE_INVALID != m_conn_handle)
-            {
-                sd_ble_gap_disconnect(m_conn_handle, BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION);
-            }
-        }
-
-        if (event & STACK_EV_KEY)
-        {
-            if (stack_state != STACK_STATE_CON && stack_state != STACK_STATE_ADV)
-            {
-                FAST_ADV();
-            }
-        }
-
-        next_timeout = (rt_tick_t)RT_WAITING_FOREVER;
-
-        if (dispatch_timeout < next_timeout)
-        {
-            next_timeout = dispatch_timeout;
-        }
-    }
-}
-
-static void _softdevice_thread(void* parameter)
-{
-    for (;;)
-    {
-        rt_sem_take(sd_evt_sem, RT_WAITING_FOREVER);
-        intern_softdevice_events_execute();
-    }
-}
-
-rt_err_t ble_init(void)
-{
-    rt_thread_t thread;
-
-    _stack_init();
-
-    thread = rt_thread_create("sdth", _softdevice_thread, RT_NULL, 512, 0, 10);
-
-    if (thread != RT_NULL)
-    {
-        rt_thread_startup(thread);
-    }
-    else
-    {
-        return RT_ERROR;
-    }
-
-    thread = rt_thread_create("bleth", _stack_thread, RT_NULL, 2048, 1, 10);
-
-    if (thread != RT_NULL)
-    {
-        return rt_thread_startup(thread);
-    }
-
-    return RT_ERROR;
-}
diff --git a/bsp/nrf5x/libraries/templates/nrf52x/applications/sdk_config.h b/bsp/nrf5x/libraries/templates/nrf52x/applications/sdk_config.h
deleted file mode 100644
index 72abeeed7c..0000000000
--- a/bsp/nrf5x/libraries/templates/nrf52x/applications/sdk_config.h
+++ /dev/null
@@ -1,3991 +0,0 @@
-
-
-#ifndef SDK_CONFIG_H
-#define SDK_CONFIG_H
-// <<< Use Configuration Wizard in Context Menu >>>\n
-#ifdef USE_APP_CONFIG
-#include "app_config.h"
-#endif
-//  nRF_BLE
-
-//==========================================================
-//  BLE_ADVERTISING_ENABLED  - ble_advertising - Advertising module
-
-
-#ifndef BLE_ADVERTISING_ENABLED
-#define BLE_ADVERTISING_ENABLED 1
-#endif
-
-//  BLE_DTM_ENABLED  - ble_dtm - Module for testing RF/PHY using DTM commands
-
-
-#ifndef BLE_DTM_ENABLED
-#define BLE_DTM_ENABLED 0
-#endif
-
-//  BLE_RACP_ENABLED  - ble_racp - Record Access Control Point library
-
-
-#ifndef BLE_RACP_ENABLED
-#define BLE_RACP_ENABLED 0
-#endif
-
-//  NRF_BLE_GATT_ENABLED - nrf_ble_gatt - GATT module
-//==========================================================
-#ifndef NRF_BLE_GATT_ENABLED
-#define NRF_BLE_GATT_ENABLED 1
-#endif
-#if  NRF_BLE_GATT_ENABLED
-//  NRF_BLE_GATT_MAX_MTU_SIZE - Static maximum MTU size that is passed to the @ref sd_ble_enable function.
-#ifndef NRF_BLE_GATT_MAX_MTU_SIZE
-#define NRF_BLE_GATT_MAX_MTU_SIZE 158
-#endif
-
-#endif //NRF_BLE_GATT_ENABLED
-// 
-
-//  NRF_BLE_QWR_ENABLED  - nrf_ble_qwr - Queued writes support module (prepare/execute write)
-
-
-#ifndef NRF_BLE_QWR_ENABLED
-#define NRF_BLE_QWR_ENABLED 0
-#endif
-
-//  PEER_MANAGER_ENABLED  - peer_manager - Peer Manager
-
-
-#ifndef PEER_MANAGER_ENABLED
-#define PEER_MANAGER_ENABLED 0
-#endif
-
-// 
-//==========================================================
-
-//  nRF_BLE_Services
-
-//==========================================================
-//  BLE_ANCS_C_ENABLED  - ble_ancs_c - Apple Notification Service Client
-
-
-#ifndef BLE_ANCS_C_ENABLED
-#define BLE_ANCS_C_ENABLED 0
-#endif
-
-//  BLE_ANS_C_ENABLED  - ble_ans_c - Alert Notification Service Client
-
-
-#ifndef BLE_ANS_C_ENABLED
-#define BLE_ANS_C_ENABLED 0
-#endif
-
-//  BLE_BAS_C_ENABLED  - ble_bas_c - Battery Service Client
-
-
-#ifndef BLE_BAS_C_ENABLED
-#define BLE_BAS_C_ENABLED 0
-#endif
-
-//  BLE_BAS_ENABLED  - ble_bas - Battery Service
-
-
-#ifndef BLE_BAS_ENABLED
-#define BLE_BAS_ENABLED 0
-#endif
-
-//  BLE_CSCS_ENABLED  - ble_cscs - Cycling Speed and Cadence Service
-
-
-#ifndef BLE_CSCS_ENABLED
-#define BLE_CSCS_ENABLED 0
-#endif
-
-//  BLE_CTS_C_ENABLED  - ble_cts_c - Current Time Service Client
-
-
-#ifndef BLE_CTS_C_ENABLED
-#define BLE_CTS_C_ENABLED 0
-#endif
-
-//  BLE_DIS_ENABLED  - ble_dis - Device Information Service
-
-
-#ifndef BLE_DIS_ENABLED
-#define BLE_DIS_ENABLED 0
-#endif
-
-//  BLE_GLS_ENABLED  - ble_gls - Glucose Service
-
-
-#ifndef BLE_GLS_ENABLED
-#define BLE_GLS_ENABLED 0
-#endif
-
-//  BLE_HIDS_ENABLED  - ble_hids - Human Interface Device Service
-
-
-#ifndef BLE_HIDS_ENABLED
-#define BLE_HIDS_ENABLED 0
-#endif
-
-//  BLE_HRS_C_ENABLED - ble_hrs_c - Heart Rate Service Client
-//==========================================================
-#ifndef BLE_HRS_C_ENABLED
-#define BLE_HRS_C_ENABLED 0
-#endif
-#if  BLE_HRS_C_ENABLED
-//  BLE_HRS_C_RR_INTERVALS_MAX_CNT - Maximum number of RR_INTERVALS per notification to be decoded
-#ifndef BLE_HRS_C_RR_INTERVALS_MAX_CNT
-#define BLE_HRS_C_RR_INTERVALS_MAX_CNT 30
-#endif
-
-#endif //BLE_HRS_C_ENABLED
-// 
-
-//  BLE_HRS_ENABLED  - ble_hrs - Heart Rate Service
-
-
-#ifndef BLE_HRS_ENABLED
-#define BLE_HRS_ENABLED 0
-#endif
-
-//  BLE_HTS_ENABLED  - ble_hts - Health Thermometer Service
-
-
-#ifndef BLE_HTS_ENABLED
-#define BLE_HTS_ENABLED 0
-#endif
-
-//  BLE_IAS_C_ENABLED  - ble_ias_c - Immediate Alert Service Client
-
-
-#ifndef BLE_IAS_C_ENABLED
-#define BLE_IAS_C_ENABLED 0
-#endif
-
-//  BLE_IAS_ENABLED  - ble_ias - Immediate Alert Service
-
-
-#ifndef BLE_IAS_ENABLED
-#define BLE_IAS_ENABLED 0
-#endif
-
-//  BLE_LBS_C_ENABLED  - ble_lbs_c - Nordic LED Button Service Client
-
-
-#ifndef BLE_LBS_C_ENABLED
-#define BLE_LBS_C_ENABLED 0
-#endif
-
-//  BLE_LBS_ENABLED  - ble_lbs - LED Button Service
-
-
-#ifndef BLE_LBS_ENABLED
-#define BLE_LBS_ENABLED 0
-#endif
-
-//  BLE_LLS_ENABLED  - ble_lls - Link Loss Service
-
-
-#ifndef BLE_LLS_ENABLED
-#define BLE_LLS_ENABLED 0
-#endif
-
-//  BLE_NUS_C_ENABLED  - ble_nus_c - Nordic UART Central Service
-
-
-#ifndef BLE_NUS_C_ENABLED
-#define BLE_NUS_C_ENABLED 0
-#endif
-
-//  BLE_NUS_ENABLED  - ble_nus - Nordic UART Service
-
-
-#ifndef BLE_NUS_ENABLED
-#define BLE_NUS_ENABLED 1
-#endif
-
-//  BLE_RSCS_C_ENABLED  - ble_rscs_c - Running Speed and Cadence Client
-
-
-#ifndef BLE_RSCS_C_ENABLED
-#define BLE_RSCS_C_ENABLED 0
-#endif
-
-//  BLE_RSCS_ENABLED  - ble_rscs - Running Speed and Cadence Service
-
-
-#ifndef BLE_RSCS_ENABLED
-#define BLE_RSCS_ENABLED 0
-#endif
-
-//  BLE_TPS_ENABLED  - ble_tps - TX Power Service
-
-
-#ifndef BLE_TPS_ENABLED
-#define BLE_TPS_ENABLED 0
-#endif
-
-// 
-//==========================================================
-
-//  nRF_Drivers
-
-//==========================================================
-//  APP_USBD_ENABLED - app_usbd - USB Device library
-//==========================================================
-#ifndef APP_USBD_ENABLED
-#define APP_USBD_ENABLED 0
-#endif
-#if  APP_USBD_ENABLED
-//  APP_USBD_VID - Vendor ID  <0x0000-0xFFFF>
-
-
-//  Vendor ID ordered from USB IF: http://www.usb.org/developers/vendor/
-
-#ifndef APP_USBD_VID
-#define APP_USBD_VID 0
-#endif
-
-//  APP_USBD_PID - Product ID  <0x0000-0xFFFF>
-
-
-//  Selected Product ID
-
-#ifndef APP_USBD_PID
-#define APP_USBD_PID 0
-#endif
-
-//  APP_USBD_DEVICE_VER_MAJOR - Device version, major part  <0-99>
-
-
-//  Device version, will be converted automatically to BCD notation. Use just decimal values.
-
-#ifndef APP_USBD_DEVICE_VER_MAJOR
-#define APP_USBD_DEVICE_VER_MAJOR 1
-#endif
-
-//  APP_USBD_DEVICE_VER_MINOR - Device version, minor part  <0-99>
-
-
-//  Device version, will be converted automatically to BCD notation. Use just decimal values.
-
-#ifndef APP_USBD_DEVICE_VER_MINOR
-#define APP_USBD_DEVICE_VER_MINOR 0
-#endif
-
-#endif //APP_USBD_ENABLED
-// 
-
-//  CLOCK_ENABLED - nrf_drv_clock - CLOCK peripheral driver
-//==========================================================
-#ifndef CLOCK_ENABLED
-#define CLOCK_ENABLED 1
-#endif
-#if  CLOCK_ENABLED
-//  CLOCK_CONFIG_XTAL_FREQ  - HF XTAL Frequency
-
-// <0=> Default (64 MHz)
-
-#ifndef CLOCK_CONFIG_XTAL_FREQ
-#define CLOCK_CONFIG_XTAL_FREQ 0
-#endif
-
-//  CLOCK_CONFIG_LF_SRC  - LF Clock Source
-
-// <0=> RC
-// <1=> XTAL
-// <2=> Synth
-
-#ifndef CLOCK_CONFIG_LF_SRC
-#define CLOCK_CONFIG_LF_SRC 1
-#endif
-
-//  CLOCK_CONFIG_IRQ_PRIORITY  - Interrupt priority
-
-
-//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef CLOCK_CONFIG_IRQ_PRIORITY
-#define CLOCK_CONFIG_IRQ_PRIORITY 7
-#endif
-
-//  CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef CLOCK_CONFIG_LOG_ENABLED
-#define CLOCK_CONFIG_LOG_ENABLED 0
-#endif
-#if  CLOCK_CONFIG_LOG_ENABLED
-//  CLOCK_CONFIG_LOG_LEVEL  - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef CLOCK_CONFIG_LOG_LEVEL
-#define CLOCK_CONFIG_LOG_LEVEL 3
-#endif
-
-//  CLOCK_CONFIG_INFO_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef CLOCK_CONFIG_INFO_COLOR
-#define CLOCK_CONFIG_INFO_COLOR 0
-#endif
-
-//  CLOCK_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef CLOCK_CONFIG_DEBUG_COLOR
-#define CLOCK_CONFIG_DEBUG_COLOR 0
-#endif
-
-#endif //CLOCK_CONFIG_LOG_ENABLED
-// 
-
-#endif //CLOCK_ENABLED
-// 
-
-//  COMP_ENABLED - nrf_drv_comp - COMP peripheral driver
-//==========================================================
-#ifndef COMP_ENABLED
-#define COMP_ENABLED 0
-#endif
-#if  COMP_ENABLED
-//  COMP_CONFIG_REF  - Reference voltage
-
-// <0=> Internal 1.2V
-// <1=> Internal 1.8V
-// <2=> Internal 2.4V
-// <4=> VDD
-// <7=> ARef
-
-#ifndef COMP_CONFIG_REF
-#define COMP_CONFIG_REF 1
-#endif
-
-//  COMP_CONFIG_MAIN_MODE  - Main mode
-
-// <0=> Single ended
-// <1=> Differential
-
-#ifndef COMP_CONFIG_MAIN_MODE
-#define COMP_CONFIG_MAIN_MODE 0
-#endif
-
-//  COMP_CONFIG_SPEED_MODE  - Speed mode
-
-// <0=> Low power
-// <1=> Normal
-// <2=> High speed
-
-#ifndef COMP_CONFIG_SPEED_MODE
-#define COMP_CONFIG_SPEED_MODE 2
-#endif
-
-//  COMP_CONFIG_HYST  - Hystheresis
-
-// <0=> No
-// <1=> 50mV
-
-#ifndef COMP_CONFIG_HYST
-#define COMP_CONFIG_HYST 0
-#endif
-
-//  COMP_CONFIG_ISOURCE  - Current Source
-
-// <0=> Off
-// <1=> 2.5 uA
-// <2=> 5 uA
-// <3=> 10 uA
-
-#ifndef COMP_CONFIG_ISOURCE
-#define COMP_CONFIG_ISOURCE 0
-#endif
-
-//  COMP_CONFIG_INPUT  - Analog input
-
-// <0=> 0
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef COMP_CONFIG_INPUT
-#define COMP_CONFIG_INPUT 0
-#endif
-
-//  COMP_CONFIG_IRQ_PRIORITY  - Interrupt priority
-
-
-//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef COMP_CONFIG_IRQ_PRIORITY
-#define COMP_CONFIG_IRQ_PRIORITY 7
-#endif
-
-//  COMP_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef COMP_CONFIG_LOG_ENABLED
-#define COMP_CONFIG_LOG_ENABLED 0
-#endif
-#if  COMP_CONFIG_LOG_ENABLED
-//  COMP_CONFIG_LOG_LEVEL  - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef COMP_CONFIG_LOG_LEVEL
-#define COMP_CONFIG_LOG_LEVEL 3
-#endif
-
-//  COMP_CONFIG_INFO_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef COMP_CONFIG_INFO_COLOR
-#define COMP_CONFIG_INFO_COLOR 0
-#endif
-
-//  COMP_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef COMP_CONFIG_DEBUG_COLOR
-#define COMP_CONFIG_DEBUG_COLOR 0
-#endif
-
-#endif //COMP_CONFIG_LOG_ENABLED
-// 
-
-#endif //COMP_ENABLED
-// 
-
-//  EGU_ENABLED - nrf_drv_swi - SWI(EGU) peripheral driver
-//==========================================================
-#ifndef EGU_ENABLED
-#define EGU_ENABLED 0
-#endif
-#if  EGU_ENABLED
-//  SWI_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef SWI_CONFIG_LOG_ENABLED
-#define SWI_CONFIG_LOG_ENABLED 0
-#endif
-#if  SWI_CONFIG_LOG_ENABLED
-//  SWI_CONFIG_LOG_LEVEL  - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef SWI_CONFIG_LOG_LEVEL
-#define SWI_CONFIG_LOG_LEVEL 3
-#endif
-
-//  SWI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef SWI_CONFIG_INFO_COLOR
-#define SWI_CONFIG_INFO_COLOR 0
-#endif
-
-//  SWI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef SWI_CONFIG_DEBUG_COLOR
-#define SWI_CONFIG_DEBUG_COLOR 0
-#endif
-
-#endif //SWI_CONFIG_LOG_ENABLED
-// 
-
-#endif //EGU_ENABLED
-// 
-
-//  GPIOTE_ENABLED - nrf_drv_gpiote - GPIOTE peripheral driver
-//==========================================================
-#ifndef GPIOTE_ENABLED
-#define GPIOTE_ENABLED 1
-#endif
-#if  GPIOTE_ENABLED
-//  GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins
-#ifndef GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS
-#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 4
-#endif
-
-//  GPIOTE_CONFIG_IRQ_PRIORITY  - Interrupt priority
-
-
-//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef GPIOTE_CONFIG_IRQ_PRIORITY
-#define GPIOTE_CONFIG_IRQ_PRIORITY 7
-#endif
-
-//  GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef GPIOTE_CONFIG_LOG_ENABLED
-#define GPIOTE_CONFIG_LOG_ENABLED 0
-#endif
-#if  GPIOTE_CONFIG_LOG_ENABLED
-//  GPIOTE_CONFIG_LOG_LEVEL  - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef GPIOTE_CONFIG_LOG_LEVEL
-#define GPIOTE_CONFIG_LOG_LEVEL 3
-#endif
-
-//  GPIOTE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef GPIOTE_CONFIG_INFO_COLOR
-#define GPIOTE_CONFIG_INFO_COLOR 0
-#endif
-
-//  GPIOTE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef GPIOTE_CONFIG_DEBUG_COLOR
-#define GPIOTE_CONFIG_DEBUG_COLOR 0
-#endif
-
-#endif //GPIOTE_CONFIG_LOG_ENABLED
-// 
-
-#endif //GPIOTE_ENABLED
-// 
-
-//  I2S_ENABLED - nrf_drv_i2s - I2S peripheral driver
-//==========================================================
-#ifndef I2S_ENABLED
-#define I2S_ENABLED 0
-#endif
-#if  I2S_ENABLED
-//  I2S_CONFIG_SCK_PIN - SCK pin  <0-31>
-
-
-#ifndef I2S_CONFIG_SCK_PIN
-#define I2S_CONFIG_SCK_PIN 31
-#endif
-
-//  I2S_CONFIG_LRCK_PIN - LRCK pin  <1-31>
-
-
-#ifndef I2S_CONFIG_LRCK_PIN
-#define I2S_CONFIG_LRCK_PIN 30
-#endif
-
-//  I2S_CONFIG_MCK_PIN - MCK pin
-#ifndef I2S_CONFIG_MCK_PIN
-#define I2S_CONFIG_MCK_PIN 255
-#endif
-
-//  I2S_CONFIG_SDOUT_PIN - SDOUT pin  <0-31>
-
-
-#ifndef I2S_CONFIG_SDOUT_PIN
-#define I2S_CONFIG_SDOUT_PIN 29
-#endif
-
-//  I2S_CONFIG_SDIN_PIN - SDIN pin  <0-31>
-
-
-#ifndef I2S_CONFIG_SDIN_PIN
-#define I2S_CONFIG_SDIN_PIN 28
-#endif
-
-//  I2S_CONFIG_MASTER  - Mode
-
-// <0=> Master
-// <1=> Slave
-
-#ifndef I2S_CONFIG_MASTER
-#define I2S_CONFIG_MASTER 0
-#endif
-
-//  I2S_CONFIG_FORMAT  - Format
-
-// <0=> I2S
-// <1=> Aligned
-
-#ifndef I2S_CONFIG_FORMAT
-#define I2S_CONFIG_FORMAT 0
-#endif
-
-//  I2S_CONFIG_ALIGN  - Alignment
-
-// <0=> Left
-// <1=> Right
-
-#ifndef I2S_CONFIG_ALIGN
-#define I2S_CONFIG_ALIGN 0
-#endif
-
-//  I2S_CONFIG_SWIDTH  - Sample width (bits)
-
-// <0=> 8
-// <1=> 16
-// <2=> 24
-
-#ifndef I2S_CONFIG_SWIDTH
-#define I2S_CONFIG_SWIDTH 1
-#endif
-
-//  I2S_CONFIG_CHANNELS  - Channels
-
-// <0=> Stereo
-// <1=> Left
-// <2=> Right
-
-#ifndef I2S_CONFIG_CHANNELS
-#define I2S_CONFIG_CHANNELS 1
-#endif
-
-//  I2S_CONFIG_MCK_SETUP  - MCK behavior
-
-// <0=> Disabled
-// <2147483648=> 32MHz/2
-// <1342177280=> 32MHz/3
-// <1073741824=> 32MHz/4
-// <805306368=> 32MHz/5
-// <671088640=> 32MHz/6
-// <536870912=> 32MHz/8
-// <402653184=> 32MHz/10
-// <369098752=> 32MHz/11
-// <285212672=> 32MHz/15
-// <268435456=> 32MHz/16
-// <201326592=> 32MHz/21
-// <184549376=> 32MHz/23
-// <142606336=> 32MHz/30
-// <138412032=> 32MHz/31
-// <134217728=> 32MHz/32
-// <100663296=> 32MHz/42
-// <68157440=> 32MHz/63
-// <34340864=> 32MHz/125
-
-#ifndef I2S_CONFIG_MCK_SETUP
-#define I2S_CONFIG_MCK_SETUP 536870912
-#endif
-
-//  I2S_CONFIG_RATIO  - MCK/LRCK ratio
-
-// <0=> 32x
-// <1=> 48x
-// <2=> 64x
-// <3=> 96x
-// <4=> 128x
-// <5=> 192x
-// <6=> 256x
-// <7=> 384x
-// <8=> 512x
-
-#ifndef I2S_CONFIG_RATIO
-#define I2S_CONFIG_RATIO 2000
-#endif
-
-//  I2S_CONFIG_IRQ_PRIORITY  - Interrupt priority
-
-
-//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef I2S_CONFIG_IRQ_PRIORITY
-#define I2S_CONFIG_IRQ_PRIORITY 7
-#endif
-
-//  I2S_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef I2S_CONFIG_LOG_ENABLED
-#define I2S_CONFIG_LOG_ENABLED 0
-#endif
-#if  I2S_CONFIG_LOG_ENABLED
-//  I2S_CONFIG_LOG_LEVEL  - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef I2S_CONFIG_LOG_LEVEL
-#define I2S_CONFIG_LOG_LEVEL 3
-#endif
-
-//  I2S_CONFIG_INFO_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef I2S_CONFIG_INFO_COLOR
-#define I2S_CONFIG_INFO_COLOR 0
-#endif
-
-//  I2S_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef I2S_CONFIG_DEBUG_COLOR
-#define I2S_CONFIG_DEBUG_COLOR 0
-#endif
-
-#endif //I2S_CONFIG_LOG_ENABLED
-// 
-
-#endif //I2S_ENABLED
-// 
-
-//  LPCOMP_ENABLED - nrf_drv_lpcomp - LPCOMP peripheral driver
-//==========================================================
-#ifndef LPCOMP_ENABLED
-#define LPCOMP_ENABLED 0
-#endif
-#if  LPCOMP_ENABLED
-//  LPCOMP_CONFIG_REFERENCE  - Reference voltage
-
-// <0=> Supply 1/8
-// <1=> Supply 2/8
-// <2=> Supply 3/8
-// <3=> Supply 4/8
-// <4=> Supply 5/8
-// <5=> Supply 6/8
-// <6=> Supply 7/8
-// <8=> Supply 1/16 (nRF52)
-// <9=> Supply 3/16 (nRF52)
-// <10=> Supply 5/16 (nRF52)
-// <11=> Supply 7/16 (nRF52)
-// <12=> Supply 9/16 (nRF52)
-// <13=> Supply 11/16 (nRF52)
-// <14=> Supply 13/16 (nRF52)
-// <15=> Supply 15/16 (nRF52)
-// <7=> External Ref 0
-// <65543=> External Ref 1
-
-#ifndef LPCOMP_CONFIG_REFERENCE
-#define LPCOMP_CONFIG_REFERENCE 3
-#endif
-
-//  LPCOMP_CONFIG_DETECTION  - Detection
-
-// <0=> Crossing
-// <1=> Up
-// <2=> Down
-
-#ifndef LPCOMP_CONFIG_DETECTION
-#define LPCOMP_CONFIG_DETECTION 2
-#endif
-
-//  LPCOMP_CONFIG_INPUT  - Analog input
-
-// <0=> 0
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef LPCOMP_CONFIG_INPUT
-#define LPCOMP_CONFIG_INPUT 0
-#endif
-
-//  LPCOMP_CONFIG_HYST  - Hysteresis
-
-
-#ifndef LPCOMP_CONFIG_HYST
-#define LPCOMP_CONFIG_HYST 0
-#endif
-
-//  LPCOMP_CONFIG_IRQ_PRIORITY  - Interrupt priority
-
-
-//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef LPCOMP_CONFIG_IRQ_PRIORITY
-#define LPCOMP_CONFIG_IRQ_PRIORITY 7
-#endif
-
-//  LPCOMP_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef LPCOMP_CONFIG_LOG_ENABLED
-#define LPCOMP_CONFIG_LOG_ENABLED 0
-#endif
-#if  LPCOMP_CONFIG_LOG_ENABLED
-//  LPCOMP_CONFIG_LOG_LEVEL  - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef LPCOMP_CONFIG_LOG_LEVEL
-#define LPCOMP_CONFIG_LOG_LEVEL 3
-#endif
-
-//  LPCOMP_CONFIG_INFO_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef LPCOMP_CONFIG_INFO_COLOR
-#define LPCOMP_CONFIG_INFO_COLOR 0
-#endif
-
-//  LPCOMP_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef LPCOMP_CONFIG_DEBUG_COLOR
-#define LPCOMP_CONFIG_DEBUG_COLOR 0
-#endif
-
-#endif //LPCOMP_CONFIG_LOG_ENABLED
-// 
-
-#endif //LPCOMP_ENABLED
-// 
-
-//  PDM_ENABLED - nrf_drv_pdm - PDM peripheral driver
-//==========================================================
-#ifndef PDM_ENABLED
-#define PDM_ENABLED 0
-#endif
-#if  PDM_ENABLED
-//  PDM_CONFIG_MODE  - Mode
-
-// <0=> Stereo
-// <1=> Mono
-
-#ifndef PDM_CONFIG_MODE
-#define PDM_CONFIG_MODE 1
-#endif
-
-//  PDM_CONFIG_EDGE  - Edge
-
-// <0=> Left falling
-// <1=> Left rising
-
-#ifndef PDM_CONFIG_EDGE
-#define PDM_CONFIG_EDGE 0
-#endif
-
-//  PDM_CONFIG_CLOCK_FREQ  - Clock frequency
-
-// <134217728=> 1000k
-// <138412032=> 1032k (default)
-// <142606336=> 1067k
-
-#ifndef PDM_CONFIG_CLOCK_FREQ
-#define PDM_CONFIG_CLOCK_FREQ 138412032
-#endif
-
-//  PDM_CONFIG_IRQ_PRIORITY  - Interrupt priority
-
-
-//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef PDM_CONFIG_IRQ_PRIORITY
-#define PDM_CONFIG_IRQ_PRIORITY 7
-#endif
-
-//  PDM_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef PDM_CONFIG_LOG_ENABLED
-#define PDM_CONFIG_LOG_ENABLED 0
-#endif
-#if  PDM_CONFIG_LOG_ENABLED
-//  PDM_CONFIG_LOG_LEVEL  - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef PDM_CONFIG_LOG_LEVEL
-#define PDM_CONFIG_LOG_LEVEL 3
-#endif
-
-//  PDM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef PDM_CONFIG_INFO_COLOR
-#define PDM_CONFIG_INFO_COLOR 0
-#endif
-
-//  PDM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef PDM_CONFIG_DEBUG_COLOR
-#define PDM_CONFIG_DEBUG_COLOR 0
-#endif
-
-#endif //PDM_CONFIG_LOG_ENABLED
-// 
-
-#endif //PDM_ENABLED
-// 
-
-//  PERIPHERAL_RESOURCE_SHARING_ENABLED - nrf_drv_common - Peripheral drivers common module
-//==========================================================
-#ifndef PERIPHERAL_RESOURCE_SHARING_ENABLED
-#define PERIPHERAL_RESOURCE_SHARING_ENABLED 0
-#endif
-#if  PERIPHERAL_RESOURCE_SHARING_ENABLED
-//  COMMON_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef COMMON_CONFIG_LOG_ENABLED
-#define COMMON_CONFIG_LOG_ENABLED 0
-#endif
-#if  COMMON_CONFIG_LOG_ENABLED
-//  COMMON_CONFIG_LOG_LEVEL  - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef COMMON_CONFIG_LOG_LEVEL
-#define COMMON_CONFIG_LOG_LEVEL 3
-#endif
-
-//  COMMON_CONFIG_INFO_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef COMMON_CONFIG_INFO_COLOR
-#define COMMON_CONFIG_INFO_COLOR 0
-#endif
-
-//  COMMON_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef COMMON_CONFIG_DEBUG_COLOR
-#define COMMON_CONFIG_DEBUG_COLOR 0
-#endif
-
-#endif //COMMON_CONFIG_LOG_ENABLED
-// 
-
-#endif //PERIPHERAL_RESOURCE_SHARING_ENABLED
-// 
-
-//  POWER_ENABLED - nrf_drv_power - POWER peripheral driver
-//==========================================================
-#ifndef POWER_ENABLED
-#define POWER_ENABLED 0
-#endif
-#if  POWER_ENABLED
-//  POWER_CONFIG_IRQ_PRIORITY  - Interrupt priority
-
-
-//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef POWER_CONFIG_IRQ_PRIORITY
-#define POWER_CONFIG_IRQ_PRIORITY 7
-#endif
-
-//  POWER_CONFIG_DEFAULT_DCDCEN  - The default configuration of main DCDC regulator
-
-
-//  This settings means only that components for DCDC regulator are installed and it can be enabled.
-
-#ifndef POWER_CONFIG_DEFAULT_DCDCEN
-#define POWER_CONFIG_DEFAULT_DCDCEN 0
-#endif
-
-//  POWER_CONFIG_DEFAULT_DCDCENHV  - The default configuration of High Voltage DCDC regulator
-
-
-//  This settings means only that components for DCDC regulator are installed and it can be enabled.
-
-#ifndef POWER_CONFIG_DEFAULT_DCDCENHV
-#define POWER_CONFIG_DEFAULT_DCDCENHV 0
-#endif
-
-#endif //POWER_ENABLED
-// 
-
-//  PPI_ENABLED - nrf_drv_ppi - PPI peripheral driver
-//==========================================================
-#ifndef PPI_ENABLED
-#define PPI_ENABLED 0
-#endif
-#if  PPI_ENABLED
-//  PPI_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef PPI_CONFIG_LOG_ENABLED
-#define PPI_CONFIG_LOG_ENABLED 0
-#endif
-#if  PPI_CONFIG_LOG_ENABLED
-//  PPI_CONFIG_LOG_LEVEL  - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef PPI_CONFIG_LOG_LEVEL
-#define PPI_CONFIG_LOG_LEVEL 3
-#endif
-
-//  PPI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef PPI_CONFIG_INFO_COLOR
-#define PPI_CONFIG_INFO_COLOR 0
-#endif
-
-//  PPI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef PPI_CONFIG_DEBUG_COLOR
-#define PPI_CONFIG_DEBUG_COLOR 0
-#endif
-
-#endif //PPI_CONFIG_LOG_ENABLED
-// 
-
-#endif //PPI_ENABLED
-// 
-
-//  PWM_ENABLED - nrf_drv_pwm - PWM peripheral driver
-//==========================================================
-#ifndef PWM_ENABLED
-#define PWM_ENABLED 1
-#endif
-#if  PWM_ENABLED
-//  PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin  <0-31>
-
-
-#ifndef PWM_DEFAULT_CONFIG_OUT0_PIN
-#define PWM_DEFAULT_CONFIG_OUT0_PIN 2
-#endif
-
-//  PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin  <0-31>
-
-
-#ifndef PWM_DEFAULT_CONFIG_OUT1_PIN
-#define PWM_DEFAULT_CONFIG_OUT1_PIN 31
-#endif
-
-//  PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin  <0-31>
-
-
-#ifndef PWM_DEFAULT_CONFIG_OUT2_PIN
-#define PWM_DEFAULT_CONFIG_OUT2_PIN 31
-#endif
-
-//  PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin  <0-31>
-
-
-#ifndef PWM_DEFAULT_CONFIG_OUT3_PIN
-#define PWM_DEFAULT_CONFIG_OUT3_PIN 31
-#endif
-
-//  PWM_DEFAULT_CONFIG_BASE_CLOCK  - Base clock
-
-// <0=> 16 MHz
-// <1=> 8 MHz
-// <2=> 4 MHz
-// <3=> 2 MHz
-// <4=> 1 MHz
-// <5=> 500 kHz
-// <6=> 250 kHz
-// <7=> 125 MHz
-
-#ifndef PWM_DEFAULT_CONFIG_BASE_CLOCK
-#define PWM_DEFAULT_CONFIG_BASE_CLOCK 7
-#endif
-
-//  PWM_DEFAULT_CONFIG_COUNT_MODE  - Count mode
-
-// <0=> Up
-// <1=> Up and Down
-
-#ifndef PWM_DEFAULT_CONFIG_COUNT_MODE
-#define PWM_DEFAULT_CONFIG_COUNT_MODE 0
-#endif
-
-//  PWM_DEFAULT_CONFIG_TOP_VALUE - Top value
-#ifndef PWM_DEFAULT_CONFIG_TOP_VALUE
-#define PWM_DEFAULT_CONFIG_TOP_VALUE 46
-#endif
-
-//  PWM_DEFAULT_CONFIG_LOAD_MODE  - Load mode
-
-// <0=> Common
-// <1=> Grouped
-// <2=> Individual
-// <3=> Waveform
-
-#ifndef PWM_DEFAULT_CONFIG_LOAD_MODE
-#define PWM_DEFAULT_CONFIG_LOAD_MODE 0
-#endif
-
-//  PWM_DEFAULT_CONFIG_STEP_MODE  - Step mode
-
-// <0=> Auto
-// <1=> Triggered
-
-#ifndef PWM_DEFAULT_CONFIG_STEP_MODE
-#define PWM_DEFAULT_CONFIG_STEP_MODE 0
-#endif
-
-//  PWM_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
-
-
-//  Priorities 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef PWM_DEFAULT_CONFIG_IRQ_PRIORITY
-#define PWM_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-//  PWM0_ENABLED  - Enable PWM0 instance
-
-
-#ifndef PWM0_ENABLED
-#define PWM0_ENABLED 1
-#endif
-
-//  PWM1_ENABLED  - Enable PWM1 instance
-
-
-#ifndef PWM1_ENABLED
-#define PWM1_ENABLED 0
-#endif
-
-//  PWM2_ENABLED  - Enable PWM2 instance
-
-
-#ifndef PWM2_ENABLED
-#define PWM2_ENABLED 0
-#endif
-
-//  PWM_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef PWM_CONFIG_LOG_ENABLED
-#define PWM_CONFIG_LOG_ENABLED 0
-#endif
-#if  PWM_CONFIG_LOG_ENABLED
-//  PWM_CONFIG_LOG_LEVEL  - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef PWM_CONFIG_LOG_LEVEL
-#define PWM_CONFIG_LOG_LEVEL 3
-#endif
-
-//  PWM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef PWM_CONFIG_INFO_COLOR
-#define PWM_CONFIG_INFO_COLOR 0
-#endif
-
-//  PWM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef PWM_CONFIG_DEBUG_COLOR
-#define PWM_CONFIG_DEBUG_COLOR 0
-#endif
-
-#endif //PWM_CONFIG_LOG_ENABLED
-// 
-
-//  PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED - Enables nRF52 Anomaly 109 workaround for PWM.
-
-//  The workaround uses interrupts to wake up the CPU and ensure
-//  it is active when PWM is about to start a DMA transfer. For
-//  initial transfer, done when a playback is started via PPI,
-//  a specific EGU instance is used to generate the interrupt.
-//  During the playback, the PWM interrupt triggered on SEQEND
-//  event of a preceding sequence is used to protect the transfer
-//  done for the next sequence to be played.
-//==========================================================
-#ifndef PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED
-#define PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED 0
-#endif
-#if  PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED
-//  PWM_NRF52_ANOMALY_109_EGU_INSTANCE  - EGU instance used by the nRF52 Anomaly 109 workaround for PWM.
-
-// <0=> EGU0
-// <1=> EGU1
-// <2=> EGU2
-// <3=> EGU3
-// <4=> EGU4
-// <5=> EGU5
-
-#ifndef PWM_NRF52_ANOMALY_109_EGU_INSTANCE
-#define PWM_NRF52_ANOMALY_109_EGU_INSTANCE 5
-#endif
-
-#endif //PWM_NRF52_ANOMALY_109_WORKAROUND_ENABLED
-// 
-
-#endif //PWM_ENABLED
-// 
-
-//  QDEC_ENABLED - nrf_drv_qdec - QDEC peripheral driver
-//==========================================================
-#ifndef QDEC_ENABLED
-#define QDEC_ENABLED 0
-#endif
-#if  QDEC_ENABLED
-//  QDEC_CONFIG_REPORTPER  - Report period
-
-// <0=> 10 Samples
-// <1=> 40 Samples
-// <2=> 80 Samples
-// <3=> 120 Samples
-// <4=> 160 Samples
-// <5=> 200 Samples
-// <6=> 240 Samples
-// <7=> 280 Samples
-
-#ifndef QDEC_CONFIG_REPORTPER
-#define QDEC_CONFIG_REPORTPER 0
-#endif
-
-//  QDEC_CONFIG_SAMPLEPER  - Sample period
-
-// <0=> 128 us
-// <1=> 256 us
-// <2=> 512 us
-// <3=> 1024 us
-// <4=> 2048 us
-// <5=> 4096 us
-// <6=> 8192 us
-// <7=> 16384 us
-
-#ifndef QDEC_CONFIG_SAMPLEPER
-#define QDEC_CONFIG_SAMPLEPER 7
-#endif
-
-//  QDEC_CONFIG_PIO_A - A pin  <0-31>
-
-
-#ifndef QDEC_CONFIG_PIO_A
-#define QDEC_CONFIG_PIO_A 31
-#endif
-
-//  QDEC_CONFIG_PIO_B - B pin  <0-31>
-
-
-#ifndef QDEC_CONFIG_PIO_B
-#define QDEC_CONFIG_PIO_B 31
-#endif
-
-//  QDEC_CONFIG_PIO_LED - LED pin  <0-31>
-
-
-#ifndef QDEC_CONFIG_PIO_LED
-#define QDEC_CONFIG_PIO_LED 31
-#endif
-
-//  QDEC_CONFIG_LEDPRE - LED pre
-#ifndef QDEC_CONFIG_LEDPRE
-#define QDEC_CONFIG_LEDPRE 511
-#endif
-
-//  QDEC_CONFIG_LEDPOL  - LED polarity
-
-// <0=> Active low
-// <1=> Active high
-
-#ifndef QDEC_CONFIG_LEDPOL
-#define QDEC_CONFIG_LEDPOL 1
-#endif
-
-//  QDEC_CONFIG_DBFEN  - Debouncing enable
-
-
-#ifndef QDEC_CONFIG_DBFEN
-#define QDEC_CONFIG_DBFEN 0
-#endif
-
-//  QDEC_CONFIG_SAMPLE_INTEN  - Sample ready interrupt enable
-
-
-#ifndef QDEC_CONFIG_SAMPLE_INTEN
-#define QDEC_CONFIG_SAMPLE_INTEN 0
-#endif
-
-//  QDEC_CONFIG_IRQ_PRIORITY  - Interrupt priority
-
-
-//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef QDEC_CONFIG_IRQ_PRIORITY
-#define QDEC_CONFIG_IRQ_PRIORITY 7
-#endif
-
-//  QDEC_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef QDEC_CONFIG_LOG_ENABLED
-#define QDEC_CONFIG_LOG_ENABLED 0
-#endif
-#if  QDEC_CONFIG_LOG_ENABLED
-//  QDEC_CONFIG_LOG_LEVEL  - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef QDEC_CONFIG_LOG_LEVEL
-#define QDEC_CONFIG_LOG_LEVEL 3
-#endif
-
-//  QDEC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef QDEC_CONFIG_INFO_COLOR
-#define QDEC_CONFIG_INFO_COLOR 0
-#endif
-
-//  QDEC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef QDEC_CONFIG_DEBUG_COLOR
-#define QDEC_CONFIG_DEBUG_COLOR 0
-#endif
-
-#endif //QDEC_CONFIG_LOG_ENABLED
-// 
-
-#endif //QDEC_ENABLED
-// 
-
-//  RNG_ENABLED - nrf_drv_rng - RNG peripheral driver
-//==========================================================
-#ifndef RNG_ENABLED
-#define RNG_ENABLED 0
-#endif
-#if  RNG_ENABLED
-//  RNG_CONFIG_ERROR_CORRECTION  - Error correction
-
-
-#ifndef RNG_CONFIG_ERROR_CORRECTION
-#define RNG_CONFIG_ERROR_CORRECTION 0
-#endif
-
-//  RNG_CONFIG_POOL_SIZE - Pool size
-#ifndef RNG_CONFIG_POOL_SIZE
-#define RNG_CONFIG_POOL_SIZE 32
-#endif
-
-//  RNG_CONFIG_IRQ_PRIORITY  - Interrupt priority
-
-
-//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef RNG_CONFIG_IRQ_PRIORITY
-#define RNG_CONFIG_IRQ_PRIORITY 7
-#endif
-
-//  RNG_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef RNG_CONFIG_LOG_ENABLED
-#define RNG_CONFIG_LOG_ENABLED 0
-#endif
-#if  RNG_CONFIG_LOG_ENABLED
-//  RNG_CONFIG_LOG_LEVEL  - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef RNG_CONFIG_LOG_LEVEL
-#define RNG_CONFIG_LOG_LEVEL 3
-#endif
-
-//  RNG_CONFIG_INFO_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef RNG_CONFIG_INFO_COLOR
-#define RNG_CONFIG_INFO_COLOR 0
-#endif
-
-//  RNG_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef RNG_CONFIG_DEBUG_COLOR
-#define RNG_CONFIG_DEBUG_COLOR 0
-#endif
-
-//  RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED  - Enables logging of random numbers.
-
-
-#ifndef RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED
-#define RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED 0
-#endif
-
-#endif //RNG_CONFIG_LOG_ENABLED
-// 
-
-#endif //RNG_ENABLED
-// 
-
-//  RTC_ENABLED - nrf_drv_rtc - RTC peripheral driver
-//==========================================================
-#ifndef RTC_ENABLED
-#define RTC_ENABLED 0
-#endif
-#if  RTC_ENABLED
-//  RTC_DEFAULT_CONFIG_FREQUENCY - Frequency  <16-32768>
-
-
-#ifndef RTC_DEFAULT_CONFIG_FREQUENCY
-#define RTC_DEFAULT_CONFIG_FREQUENCY 32768
-#endif
-
-//  RTC_DEFAULT_CONFIG_RELIABLE  - Ensures safe compare event triggering
-
-
-#ifndef RTC_DEFAULT_CONFIG_RELIABLE
-#define RTC_DEFAULT_CONFIG_RELIABLE 0
-#endif
-
-//  RTC_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
-
-
-//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef RTC_DEFAULT_CONFIG_IRQ_PRIORITY
-#define RTC_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-//  RTC0_ENABLED  - Enable RTC0 instance
-
-
-#ifndef RTC0_ENABLED
-#define RTC0_ENABLED 0
-#endif
-
-//  RTC1_ENABLED  - Enable RTC1 instance
-
-
-#ifndef RTC1_ENABLED
-#define RTC1_ENABLED 0
-#endif
-
-//  RTC2_ENABLED  - Enable RTC2 instance
-
-
-#ifndef RTC2_ENABLED
-#define RTC2_ENABLED 0
-#endif
-
-//  NRF_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt
-#ifndef NRF_MAXIMUM_LATENCY_US
-#define NRF_MAXIMUM_LATENCY_US 2000
-#endif
-
-//  RTC_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef RTC_CONFIG_LOG_ENABLED
-#define RTC_CONFIG_LOG_ENABLED 0
-#endif
-#if  RTC_CONFIG_LOG_ENABLED
-//  RTC_CONFIG_LOG_LEVEL  - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef RTC_CONFIG_LOG_LEVEL
-#define RTC_CONFIG_LOG_LEVEL 3
-#endif
-
-//  RTC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef RTC_CONFIG_INFO_COLOR
-#define RTC_CONFIG_INFO_COLOR 0
-#endif
-
-//  RTC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef RTC_CONFIG_DEBUG_COLOR
-#define RTC_CONFIG_DEBUG_COLOR 0
-#endif
-
-#endif //RTC_CONFIG_LOG_ENABLED
-// 
-
-#endif //RTC_ENABLED
-// 
-
-//  SAADC_ENABLED - nrf_drv_saadc - SAADC peripheral driver
-//==========================================================
-#ifndef SAADC_ENABLED
-#define SAADC_ENABLED 1
-#endif
-#if  SAADC_ENABLED
-//  SAADC_CONFIG_RESOLUTION  - Resolution
-
-// <0=> 8 bit
-// <1=> 10 bit
-// <2=> 12 bit
-// <3=> 14 bit
-
-#ifndef SAADC_CONFIG_RESOLUTION
-#define SAADC_CONFIG_RESOLUTION 2
-#endif
-
-//  SAADC_CONFIG_OVERSAMPLE  - Sample period
-
-// <0=> Disabled
-// <1=> 2x
-// <2=> 4x
-// <3=> 8x
-// <4=> 16x
-// <5=> 32x
-// <6=> 64x
-// <7=> 128x
-// <8=> 256x
-
-#ifndef SAADC_CONFIG_OVERSAMPLE
-#define SAADC_CONFIG_OVERSAMPLE 0
-#endif
-
-//  SAADC_CONFIG_LP_MODE  - Enabling low power mode
-
-
-#ifndef SAADC_CONFIG_LP_MODE
-#define SAADC_CONFIG_LP_MODE 0
-#endif
-
-//  SAADC_CONFIG_IRQ_PRIORITY  - Interrupt priority
-
-
-//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef SAADC_CONFIG_IRQ_PRIORITY
-#define SAADC_CONFIG_IRQ_PRIORITY 7
-#endif
-
-//  SAADC_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef SAADC_CONFIG_LOG_ENABLED
-#define SAADC_CONFIG_LOG_ENABLED 0
-#endif
-#if  SAADC_CONFIG_LOG_ENABLED
-//  SAADC_CONFIG_LOG_LEVEL  - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef SAADC_CONFIG_LOG_LEVEL
-#define SAADC_CONFIG_LOG_LEVEL 3
-#endif
-
-//  SAADC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef SAADC_CONFIG_INFO_COLOR
-#define SAADC_CONFIG_INFO_COLOR 0
-#endif
-
-//  SAADC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef SAADC_CONFIG_DEBUG_COLOR
-#define SAADC_CONFIG_DEBUG_COLOR 0
-#endif
-
-#endif //SAADC_CONFIG_LOG_ENABLED
-// 
-
-#endif //SAADC_ENABLED
-// 
-
-//  SPIS_ENABLED - nrf_drv_spis - SPI Slave driver
-//==========================================================
-#ifndef SPIS_ENABLED
-#define SPIS_ENABLED 0
-#endif
-#if  SPIS_ENABLED
-//  SPIS_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
-
-
-//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
-#define SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-//  SPIS_DEFAULT_MODE  - Mode
-
-// <0=> MODE_0
-// <1=> MODE_1
-// <2=> MODE_2
-// <3=> MODE_3
-
-#ifndef SPIS_DEFAULT_MODE
-#define SPIS_DEFAULT_MODE 0
-#endif
-
-//  SPIS_DEFAULT_BIT_ORDER  - SPIS default bit order
-
-// <0=> MSB first
-// <1=> LSB first
-
-#ifndef SPIS_DEFAULT_BIT_ORDER
-#define SPIS_DEFAULT_BIT_ORDER 0
-#endif
-
-//  SPIS_DEFAULT_DEF - SPIS default DEF character  <0-255>
-
-
-#ifndef SPIS_DEFAULT_DEF
-#define SPIS_DEFAULT_DEF 255
-#endif
-
-//  SPIS_DEFAULT_ORC - SPIS default ORC character  <0-255>
-
-
-#ifndef SPIS_DEFAULT_ORC
-#define SPIS_DEFAULT_ORC 255
-#endif
-
-//  SPIS0_ENABLED  - Enable SPIS0 instance
-
-
-#ifndef SPIS0_ENABLED
-#define SPIS0_ENABLED 0
-#endif
-
-//  SPIS1_ENABLED  - Enable SPIS1 instance
-
-
-#ifndef SPIS1_ENABLED
-#define SPIS1_ENABLED 0
-#endif
-
-//  SPIS2_ENABLED  - Enable SPIS2 instance
-
-
-#ifndef SPIS2_ENABLED
-#define SPIS2_ENABLED 0
-#endif
-
-//  SPIS_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef SPIS_CONFIG_LOG_ENABLED
-#define SPIS_CONFIG_LOG_ENABLED 0
-#endif
-#if  SPIS_CONFIG_LOG_ENABLED
-//  SPIS_CONFIG_LOG_LEVEL  - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef SPIS_CONFIG_LOG_LEVEL
-#define SPIS_CONFIG_LOG_LEVEL 3
-#endif
-
-//  SPIS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef SPIS_CONFIG_INFO_COLOR
-#define SPIS_CONFIG_INFO_COLOR 0
-#endif
-
-//  SPIS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef SPIS_CONFIG_DEBUG_COLOR
-#define SPIS_CONFIG_DEBUG_COLOR 0
-#endif
-
-#endif //SPIS_CONFIG_LOG_ENABLED
-// 
-
-//  SPIS_NRF52_ANOMALY_109_WORKAROUND_ENABLED  - Enables nRF52 Anomaly 109 workaround for SPIS.
-
-
-//  The workaround uses a GPIOTE channel to generate interrupts
-//  on falling edges detected on the CSN line. This will make
-//  the CPU active for the moment when SPIS starts DMA transfers,
-//  and this way the transfers will be protected.
-//  This workaround uses GPIOTE driver, so this driver must be
-//  enabled as well.
-
-#ifndef SPIS_NRF52_ANOMALY_109_WORKAROUND_ENABLED
-#define SPIS_NRF52_ANOMALY_109_WORKAROUND_ENABLED 0
-#endif
-
-#endif //SPIS_ENABLED
-// 
-
-//  SPI_ENABLED - nrf_drv_spi - SPI/SPIM peripheral driver
-//==========================================================
-#ifndef SPI_ENABLED
-#define SPI_ENABLED 0
-#endif
-#if  SPI_ENABLED
-//  SPI_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
-
-
-//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef SPI_DEFAULT_CONFIG_IRQ_PRIORITY
-#define SPI_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-//  SPI0_ENABLED - Enable SPI0 instance
-//==========================================================
-#ifndef SPI0_ENABLED
-#define SPI0_ENABLED 0
-#endif
-#if  SPI0_ENABLED
-//  SPI0_USE_EASY_DMA  - Use EasyDMA
-
-
-#ifndef SPI0_USE_EASY_DMA
-#define SPI0_USE_EASY_DMA 1
-#endif
-
-//  SPI0_DEFAULT_FREQUENCY  - SPI frequency
-
-// <33554432=> 125 kHz
-// <67108864=> 250 kHz
-// <134217728=> 500 kHz
-// <268435456=> 1 MHz
-// <536870912=> 2 MHz
-// <1073741824=> 4 MHz
-// <2147483648=> 8 MHz
-
-#ifndef SPI0_DEFAULT_FREQUENCY
-#define SPI0_DEFAULT_FREQUENCY 1073741824
-#endif
-
-#endif //SPI0_ENABLED
-// 
-
-//  SPI1_ENABLED - Enable SPI1 instance
-//==========================================================
-#ifndef SPI1_ENABLED
-#define SPI1_ENABLED 0
-#endif
-#if  SPI1_ENABLED
-//  SPI1_USE_EASY_DMA  - Use EasyDMA
-
-
-#ifndef SPI1_USE_EASY_DMA
-#define SPI1_USE_EASY_DMA 1
-#endif
-
-//  SPI1_DEFAULT_FREQUENCY  - SPI frequency
-
-// <33554432=> 125 kHz
-// <67108864=> 250 kHz
-// <134217728=> 500 kHz
-// <268435456=> 1 MHz
-// <536870912=> 2 MHz
-// <1073741824=> 4 MHz
-// <2147483648=> 8 MHz
-
-#ifndef SPI1_DEFAULT_FREQUENCY
-#define SPI1_DEFAULT_FREQUENCY 1073741824
-#endif
-
-#endif //SPI1_ENABLED
-// 
-
-//  SPI2_ENABLED - Enable SPI2 instance
-//==========================================================
-#ifndef SPI2_ENABLED
-#define SPI2_ENABLED 0
-#endif
-#if  SPI2_ENABLED
-//  SPI2_USE_EASY_DMA  - Use EasyDMA
-
-
-#ifndef SPI2_USE_EASY_DMA
-#define SPI2_USE_EASY_DMA 1
-#endif
-
-//  SPI2_DEFAULT_FREQUENCY  - Use EasyDMA
-
-
-#ifndef SPI2_DEFAULT_FREQUENCY
-#define SPI2_DEFAULT_FREQUENCY 1
-#endif
-
-#endif //SPI2_ENABLED
-// 
-
-//  SPI_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef SPI_CONFIG_LOG_ENABLED
-#define SPI_CONFIG_LOG_ENABLED 0
-#endif
-#if  SPI_CONFIG_LOG_ENABLED
-//  SPI_CONFIG_LOG_LEVEL  - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef SPI_CONFIG_LOG_LEVEL
-#define SPI_CONFIG_LOG_LEVEL 3
-#endif
-
-//  SPI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef SPI_CONFIG_INFO_COLOR
-#define SPI_CONFIG_INFO_COLOR 0
-#endif
-
-//  SPI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef SPI_CONFIG_DEBUG_COLOR
-#define SPI_CONFIG_DEBUG_COLOR 0
-#endif
-
-#endif //SPI_CONFIG_LOG_ENABLED
-// 
-
-//  SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED  - Enables nRF52 anomaly 109 workaround for SPIM.
-
-
-//  The workaround uses interrupts to wake up the CPU by catching
-//  a start event of zero-length transmission to start the clock. This
-//  ensures that the DMA transfer will be executed without issues and
-//  that the proper transfer will be started. See more in the Errata
-//  document or Anomaly 109 Addendum located at
-//  https://infocenter.nordicsemi.com/
-
-#ifndef SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED
-#define SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED 0
-#endif
-
-#endif //SPI_ENABLED
-// 
-
-//  TIMER_ENABLED - nrf_drv_timer - TIMER periperal driver
-//==========================================================
-#ifndef TIMER_ENABLED
-#define TIMER_ENABLED 0
-#endif
-#if  TIMER_ENABLED
-//  TIMER_DEFAULT_CONFIG_FREQUENCY  - Timer frequency if in Timer mode
-
-// <0=> 16 MHz
-// <1=> 8 MHz
-// <2=> 4 MHz
-// <3=> 2 MHz
-// <4=> 1 MHz
-// <5=> 500 kHz
-// <6=> 250 kHz
-// <7=> 125 kHz
-// <8=> 62.5 kHz
-// <9=> 31.25 kHz
-
-#ifndef TIMER_DEFAULT_CONFIG_FREQUENCY
-#define TIMER_DEFAULT_CONFIG_FREQUENCY 0
-#endif
-
-//  TIMER_DEFAULT_CONFIG_MODE  - Timer mode or operation
-
-// <0=> Timer
-// <1=> Counter
-
-#ifndef TIMER_DEFAULT_CONFIG_MODE
-#define TIMER_DEFAULT_CONFIG_MODE 0
-#endif
-
-//  TIMER_DEFAULT_CONFIG_BIT_WIDTH  - Timer counter bit width
-
-// <0=> 16 bit
-// <1=> 8 bit
-// <2=> 24 bit
-// <3=> 32 bit
-
-#ifndef TIMER_DEFAULT_CONFIG_BIT_WIDTH
-#define TIMER_DEFAULT_CONFIG_BIT_WIDTH 0
-#endif
-
-//  TIMER_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
-
-
-//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
-#define TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-//  TIMER0_ENABLED  - Enable TIMER0 instance
-
-
-#ifndef TIMER0_ENABLED
-#define TIMER0_ENABLED 0
-#endif
-
-//  TIMER1_ENABLED  - Enable TIMER1 instance
-
-
-#ifndef TIMER1_ENABLED
-#define TIMER1_ENABLED 0
-#endif
-
-//  TIMER2_ENABLED  - Enable TIMER2 instance
-
-
-#ifndef TIMER2_ENABLED
-#define TIMER2_ENABLED 0
-#endif
-
-//  TIMER3_ENABLED  - Enable TIMER3 instance
-
-
-#ifndef TIMER3_ENABLED
-#define TIMER3_ENABLED 0
-#endif
-
-//  TIMER4_ENABLED  - Enable TIMER4 instance
-
-
-#ifndef TIMER4_ENABLED
-#define TIMER4_ENABLED 0
-#endif
-
-//  TIMER_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef TIMER_CONFIG_LOG_ENABLED
-#define TIMER_CONFIG_LOG_ENABLED 0
-#endif
-#if  TIMER_CONFIG_LOG_ENABLED
-//  TIMER_CONFIG_LOG_LEVEL  - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef TIMER_CONFIG_LOG_LEVEL
-#define TIMER_CONFIG_LOG_LEVEL 3
-#endif
-
-//  TIMER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef TIMER_CONFIG_INFO_COLOR
-#define TIMER_CONFIG_INFO_COLOR 0
-#endif
-
-//  TIMER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef TIMER_CONFIG_DEBUG_COLOR
-#define TIMER_CONFIG_DEBUG_COLOR 0
-#endif
-
-#endif //TIMER_CONFIG_LOG_ENABLED
-// 
-
-#endif //TIMER_ENABLED
-// 
-
-//  TWIS_ENABLED - nrf_drv_twis - TWIS peripheral driver
-//==========================================================
-#ifndef TWIS_ENABLED
-#define TWIS_ENABLED 0
-#endif
-#if  TWIS_ENABLED
-//  TWIS_DEFAULT_CONFIG_ADDR0 - Address0
-#ifndef TWIS_DEFAULT_CONFIG_ADDR0
-#define TWIS_DEFAULT_CONFIG_ADDR0 0
-#endif
-
-//  TWIS_DEFAULT_CONFIG_ADDR1 - Address1
-#ifndef TWIS_DEFAULT_CONFIG_ADDR1
-#define TWIS_DEFAULT_CONFIG_ADDR1 0
-#endif
-
-//  TWIS_DEFAULT_CONFIG_SCL_PULL  - SCL pin pull configuration
-
-// <0=> Disabled
-// <1=> Pull down
-// <3=> Pull up
-
-#ifndef TWIS_DEFAULT_CONFIG_SCL_PULL
-#define TWIS_DEFAULT_CONFIG_SCL_PULL 0
-#endif
-
-//  TWIS_DEFAULT_CONFIG_SDA_PULL  - SDA pin pull configuration
-
-// <0=> Disabled
-// <1=> Pull down
-// <3=> Pull up
-
-#ifndef TWIS_DEFAULT_CONFIG_SDA_PULL
-#define TWIS_DEFAULT_CONFIG_SDA_PULL 0
-#endif
-
-//  TWIS_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
-
-
-//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
-#define TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-//  TWIS0_ENABLED  - Enable TWIS0 instance
-
-
-#ifndef TWIS0_ENABLED
-#define TWIS0_ENABLED 0
-#endif
-
-//  TWIS1_ENABLED  - Enable TWIS1 instance
-
-
-#ifndef TWIS1_ENABLED
-#define TWIS1_ENABLED 0
-#endif
-
-//  TWIS_ASSUME_INIT_AFTER_RESET_ONLY  - Assume that any instance would be initialized only once
-
-
-//  Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code.
-
-#ifndef TWIS_ASSUME_INIT_AFTER_RESET_ONLY
-#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
-#endif
-
-//  TWIS_NO_SYNC_MODE  - Remove support for synchronous mode
-
-
-//  Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources.
-
-#ifndef TWIS_NO_SYNC_MODE
-#define TWIS_NO_SYNC_MODE 0
-#endif
-
-//  TWIS_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef TWIS_CONFIG_LOG_ENABLED
-#define TWIS_CONFIG_LOG_ENABLED 0
-#endif
-#if  TWIS_CONFIG_LOG_ENABLED
-//  TWIS_CONFIG_LOG_LEVEL  - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef TWIS_CONFIG_LOG_LEVEL
-#define TWIS_CONFIG_LOG_LEVEL 3
-#endif
-
-//  TWIS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef TWIS_CONFIG_INFO_COLOR
-#define TWIS_CONFIG_INFO_COLOR 0
-#endif
-
-//  TWIS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef TWIS_CONFIG_DEBUG_COLOR
-#define TWIS_CONFIG_DEBUG_COLOR 0
-#endif
-
-#endif //TWIS_CONFIG_LOG_ENABLED
-// 
-
-#endif //TWIS_ENABLED
-// 
-
-//  TWI_ENABLED - nrf_drv_twi - TWI/TWIM peripheral driver
-//==========================================================
-#ifndef TWI_ENABLED
-#define TWI_ENABLED 0
-#endif
-#if  TWI_ENABLED
-//  TWI_DEFAULT_CONFIG_FREQUENCY  - Frequency
-
-// <26738688=> 100k
-// <67108864=> 250k
-// <104857600=> 400k
-
-#ifndef TWI_DEFAULT_CONFIG_FREQUENCY
-#define TWI_DEFAULT_CONFIG_FREQUENCY 26738688
-#endif
-
-//  TWI_DEFAULT_CONFIG_CLR_BUS_INIT  - Enables bus clearing procedure during init
-
-
-#ifndef TWI_DEFAULT_CONFIG_CLR_BUS_INIT
-#define TWI_DEFAULT_CONFIG_CLR_BUS_INIT 0
-#endif
-
-//  TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT  - Enables bus holding after uninit
-
-
-#ifndef TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT
-#define TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0
-#endif
-
-//  TWI_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
-
-
-//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef TWI_DEFAULT_CONFIG_IRQ_PRIORITY
-#define TWI_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-//  TWI0_ENABLED - Enable TWI0 instance
-//==========================================================
-#ifndef TWI0_ENABLED
-#define TWI0_ENABLED 0
-#endif
-#if  TWI0_ENABLED
-//  TWI0_USE_EASY_DMA  - Use EasyDMA (if present)
-
-
-#ifndef TWI0_USE_EASY_DMA
-#define TWI0_USE_EASY_DMA 0
-#endif
-
-#endif //TWI0_ENABLED
-// 
-
-//  TWI1_ENABLED - Enable TWI1 instance
-//==========================================================
-#ifndef TWI1_ENABLED
-#define TWI1_ENABLED 0
-#endif
-#if  TWI1_ENABLED
-//  TWI1_USE_EASY_DMA  - Use EasyDMA (if present)
-
-
-#ifndef TWI1_USE_EASY_DMA
-#define TWI1_USE_EASY_DMA 0
-#endif
-
-#endif //TWI1_ENABLED
-// 
-
-//  TWI_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef TWI_CONFIG_LOG_ENABLED
-#define TWI_CONFIG_LOG_ENABLED 0
-#endif
-#if  TWI_CONFIG_LOG_ENABLED
-//  TWI_CONFIG_LOG_LEVEL  - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef TWI_CONFIG_LOG_LEVEL
-#define TWI_CONFIG_LOG_LEVEL 3
-#endif
-
-//  TWI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef TWI_CONFIG_INFO_COLOR
-#define TWI_CONFIG_INFO_COLOR 0
-#endif
-
-//  TWI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef TWI_CONFIG_DEBUG_COLOR
-#define TWI_CONFIG_DEBUG_COLOR 0
-#endif
-
-#endif //TWI_CONFIG_LOG_ENABLED
-// 
-
-//  TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED  - Enables nRF52 anomaly 109 workaround for TWIM.
-
-
-//  The workaround uses interrupts to wake up the CPU by catching
-//  the start event of zero-frequency transmission, clear the
-//  peripheral, set desired frequency, start the peripheral, and
-//  the proper transmission. See more in the Errata document or
-//  Anomaly 109 Addendum located at https://infocenter.nordicsemi.com/
-
-#ifndef TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED
-#define TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED 0
-#endif
-
-#endif //TWI_ENABLED
-// 
-
-//  UART_ENABLED - nrf_drv_uart - UART/UARTE peripheral driver
-//==========================================================
-#ifndef UART_ENABLED
-#define UART_ENABLED 1
-#endif
-#if  UART_ENABLED
-//  UART_DEFAULT_CONFIG_HWFC  - Hardware Flow Control
-
-// <0=> Disabled
-// <1=> Enabled
-
-#ifndef UART_DEFAULT_CONFIG_HWFC
-#define UART_DEFAULT_CONFIG_HWFC 0
-#endif
-
-//  UART_DEFAULT_CONFIG_PARITY  - Parity
-
-// <0=> Excluded
-// <14=> Included
-
-#ifndef UART_DEFAULT_CONFIG_PARITY
-#define UART_DEFAULT_CONFIG_PARITY 0
-#endif
-
-//  UART_DEFAULT_CONFIG_BAUDRATE  - Default Baudrate
-
-// <323584=> 1200 baud
-// <643072=> 2400 baud
-// <1290240=> 4800 baud
-// <2576384=> 9600 baud
-// <3862528=> 14400 baud
-// <5152768=> 19200 baud
-// <7716864=> 28800 baud
-// <10289152=> 38400 baud
-// <15400960=> 57600 baud
-// <20615168=> 76800 baud
-// <30801920=> 115200 baud
-// <61865984=> 230400 baud
-// <67108864=> 250000 baud
-// <121634816=> 460800 baud
-// <251658240=> 921600 baud
-// <268435456=> 57600 baud
-
-#ifndef UART_DEFAULT_CONFIG_BAUDRATE
-#define UART_DEFAULT_CONFIG_BAUDRATE 30801920
-#endif
-
-//  UART_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
-
-
-//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef UART_DEFAULT_CONFIG_IRQ_PRIORITY
-#define UART_DEFAULT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-//  UART_EASY_DMA_SUPPORT  - Driver supporting EasyDMA
-
-
-#ifndef UART_EASY_DMA_SUPPORT
-#define UART_EASY_DMA_SUPPORT 0
-#endif
-
-//  UART_LEGACY_SUPPORT  - Driver supporting Legacy mode
-
-
-#ifndef UART_LEGACY_SUPPORT
-#define UART_LEGACY_SUPPORT 1
-#endif
-
-//  UART0_ENABLED - Enable UART0 instance
-//==========================================================
-#ifndef UART0_ENABLED
-#define UART0_ENABLED 1
-#endif
-#if  UART0_ENABLED
-//  UART0_CONFIG_USE_EASY_DMA  - Default setting for using EasyDMA
-
-
-#ifndef UART0_CONFIG_USE_EASY_DMA
-#define UART0_CONFIG_USE_EASY_DMA 0
-#endif
-
-#endif //UART0_ENABLED
-// 
-
-//  UART_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef UART_CONFIG_LOG_ENABLED
-#define UART_CONFIG_LOG_ENABLED 0
-#endif
-#if  UART_CONFIG_LOG_ENABLED
-//  UART_CONFIG_LOG_LEVEL  - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef UART_CONFIG_LOG_LEVEL
-#define UART_CONFIG_LOG_LEVEL 3
-#endif
-
-//  UART_CONFIG_INFO_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef UART_CONFIG_INFO_COLOR
-#define UART_CONFIG_INFO_COLOR 0
-#endif
-
-//  UART_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef UART_CONFIG_DEBUG_COLOR
-#define UART_CONFIG_DEBUG_COLOR 0
-#endif
-
-#endif //UART_CONFIG_LOG_ENABLED
-// 
-
-#endif //UART_ENABLED
-// 
-
-//  USBD_ENABLED - nrf_drv_usbd - USB driver
-//==========================================================
-#ifndef USBD_ENABLED
-#define USBD_ENABLED 0
-#endif
-#if  USBD_ENABLED
-//  USBD_CONFIG_IRQ_PRIORITY  - Interrupt priority
-
-
-//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef USBD_CONFIG_IRQ_PRIORITY
-#define USBD_CONFIG_IRQ_PRIORITY 7
-#endif
-
-//  NRF_DRV_USBD_DMASCHEDULER_MODE  - USBD SMA scheduler working scheme
-
-// <0=> Prioritized access
-// <1=> Round Robin
-
-#ifndef NRF_DRV_USBD_DMASCHEDULER_MODE
-#define NRF_DRV_USBD_DMASCHEDULER_MODE 0
-#endif
-
-//  NRF_USBD_DRV_LOG_ENABLED  - Enable logging
-
-
-#ifndef NRF_USBD_DRV_LOG_ENABLED
-#define NRF_USBD_DRV_LOG_ENABLED 0
-#endif
-
-#endif //USBD_ENABLED
-// 
-
-//  WDT_ENABLED - nrf_drv_wdt - WDT peripheral driver
-//==========================================================
-#ifndef WDT_ENABLED
-#define WDT_ENABLED 0
-#endif
-#if  WDT_ENABLED
-//  WDT_CONFIG_BEHAVIOUR  - WDT behavior in CPU SLEEP or HALT mode
-
-// <1=> Run in SLEEP, Pause in HALT
-// <8=> Pause in SLEEP, Run in HALT
-// <9=> Run in SLEEP and HALT
-// <0=> Pause in SLEEP and HALT
-
-#ifndef WDT_CONFIG_BEHAVIOUR
-#define WDT_CONFIG_BEHAVIOUR 1
-#endif
-
-//  WDT_CONFIG_RELOAD_VALUE - Reload value  <15-4294967295>
-
-
-#ifndef WDT_CONFIG_RELOAD_VALUE
-#define WDT_CONFIG_RELOAD_VALUE 2000
-#endif
-
-//  WDT_CONFIG_IRQ_PRIORITY  - Interrupt priority
-
-
-//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef WDT_CONFIG_IRQ_PRIORITY
-#define WDT_CONFIG_IRQ_PRIORITY 7
-#endif
-
-//  WDT_CONFIG_LOG_ENABLED - Enables logging in the module.
-//==========================================================
-#ifndef WDT_CONFIG_LOG_ENABLED
-#define WDT_CONFIG_LOG_ENABLED 0
-#endif
-#if  WDT_CONFIG_LOG_ENABLED
-//  WDT_CONFIG_LOG_LEVEL  - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef WDT_CONFIG_LOG_LEVEL
-#define WDT_CONFIG_LOG_LEVEL 3
-#endif
-
-//  WDT_CONFIG_INFO_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef WDT_CONFIG_INFO_COLOR
-#define WDT_CONFIG_INFO_COLOR 0
-#endif
-
-//  WDT_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef WDT_CONFIG_DEBUG_COLOR
-#define WDT_CONFIG_DEBUG_COLOR 0
-#endif
-
-#endif //WDT_CONFIG_LOG_ENABLED
-// 
-
-#endif //WDT_ENABLED
-// 
-
-// 
-//==========================================================
-
-//  nRF_Libraries
-
-//==========================================================
-//  APP_FIFO_ENABLED  - app_fifo - Software FIFO implementation
-
-
-#ifndef APP_FIFO_ENABLED
-#define APP_FIFO_ENABLED 1
-#endif
-
-//  APP_GPIOTE_ENABLED  - app_gpiote - GPIOTE events dispatcher
-
-
-#ifndef APP_GPIOTE_ENABLED
-#define APP_GPIOTE_ENABLED 0
-#endif
-
-//  APP_PWM_ENABLED  - app_pwm - PWM functionality
-
-
-#ifndef APP_PWM_ENABLED
-#define APP_PWM_ENABLED 0
-#endif
-
-//  APP_SCHEDULER_ENABLED - app_scheduler - Events scheduler
-//==========================================================
-#ifndef APP_SCHEDULER_ENABLED
-#define APP_SCHEDULER_ENABLED 1
-#endif
-#if  APP_SCHEDULER_ENABLED
-//  APP_SCHEDULER_WITH_PAUSE  - Enabling pause feature
-
-
-#ifndef APP_SCHEDULER_WITH_PAUSE
-#define APP_SCHEDULER_WITH_PAUSE 0
-#endif
-
-//  APP_SCHEDULER_WITH_PROFILER  - Enabling scheduler profiling
-
-
-#ifndef APP_SCHEDULER_WITH_PROFILER
-#define APP_SCHEDULER_WITH_PROFILER 0
-#endif
-
-#endif //APP_SCHEDULER_ENABLED
-// 
-
-//  APP_TIMER_ENABLED - app_timer - Application timer functionality
-//==========================================================
-#ifndef APP_TIMER_ENABLED
-#define APP_TIMER_ENABLED 1
-#endif
-#if  APP_TIMER_ENABLED
-//  APP_TIMER_CONFIG_RTC_FREQUENCY  - Configure RTC prescaler.
-
-// <0=> 32768 Hz
-// <1=> 16384 Hz
-// <3=> 8192 Hz
-// <7=> 4096 Hz
-// <15=> 2048 Hz
-// <31=> 1024 Hz
-
-#ifndef APP_TIMER_CONFIG_RTC_FREQUENCY
-#define APP_TIMER_CONFIG_RTC_FREQUENCY 0
-#endif
-
-//  APP_TIMER_CONFIG_IRQ_PRIORITY  - Interrupt priority
-
-
-//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest)
-// <1=> 1
-// <2=> 2
-// <3=> 3
-// <4=> 4
-// <5=> 5
-// <6=> 6
-// <7=> 7
-
-#ifndef APP_TIMER_CONFIG_IRQ_PRIORITY
-#define APP_TIMER_CONFIG_IRQ_PRIORITY 7
-#endif
-
-//  APP_TIMER_CONFIG_OP_QUEUE_SIZE - Capacity of timer requests queue.
-//  Size of the queue depends on how many timers are used
-//  in the system, how often timers are started and overall
-//  system latency. If queue size is too small app_timer calls
-//  will fail.
-
-#ifndef APP_TIMER_CONFIG_OP_QUEUE_SIZE
-#define APP_TIMER_CONFIG_OP_QUEUE_SIZE 10
-#endif
-
-//  APP_TIMER_CONFIG_USE_SCHEDULER  - Enable scheduling app_timer events to app_scheduler
-
-
-#ifndef APP_TIMER_CONFIG_USE_SCHEDULER
-#define APP_TIMER_CONFIG_USE_SCHEDULER 0
-#endif
-
-//  APP_TIMER_WITH_PROFILER  - Enable app_timer profiling
-
-
-#ifndef APP_TIMER_WITH_PROFILER
-#define APP_TIMER_WITH_PROFILER 0
-#endif
-
-//  APP_TIMER_KEEPS_RTC_ACTIVE  - Enable RTC always on
-
-
-//  If option is enabled RTC is kept running even if there is no active timers.
-//  This option can be used when app_timer is used for timestamping.
-
-#ifndef APP_TIMER_KEEPS_RTC_ACTIVE
-#define APP_TIMER_KEEPS_RTC_ACTIVE 0
-#endif
-
-//  APP_TIMER_CONFIG_SWI_NUMBER  - Configure SWI instance used.
-
-// <0=> 0
-// <1=> 1
-
-#ifndef APP_TIMER_CONFIG_SWI_NUMBER
-#define APP_TIMER_CONFIG_SWI_NUMBER 0
-#endif
-
-#endif //APP_TIMER_ENABLED
-// 
-
-//  APP_TWI_ENABLED  - app_twi - TWI transaction manager
-
-
-#ifndef APP_TWI_ENABLED
-#define APP_TWI_ENABLED 0
-#endif
-
-//  APP_UART_ENABLED - app_uart - UART driver
-//==========================================================
-#ifndef APP_UART_ENABLED
-#define APP_UART_ENABLED 1
-#endif
-#if  APP_UART_ENABLED
-//  APP_UART_DRIVER_INSTANCE  - UART instance used
-
-// <0=> 0
-
-#ifndef APP_UART_DRIVER_INSTANCE
-#define APP_UART_DRIVER_INSTANCE 0
-#endif
-
-#endif //APP_UART_ENABLED
-// 
-
-//  APP_USBD_CLASS_AUDIO_ENABLED  - app_usbd_audio - USB AUDIO class
-
-
-#ifndef APP_USBD_CLASS_AUDIO_ENABLED
-#define APP_USBD_CLASS_AUDIO_ENABLED 0
-#endif
-
-//  APP_USBD_CLASS_HID_ENABLED  - app_usbd_hid - USB HID class
-
-
-#ifndef APP_USBD_CLASS_HID_ENABLED
-#define APP_USBD_CLASS_HID_ENABLED 0
-#endif
-
-//  APP_USBD_HID_GENERIC_ENABLED  - app_usbd_hid_generic - USB HID generic
-
-
-#ifndef APP_USBD_HID_GENERIC_ENABLED
-#define APP_USBD_HID_GENERIC_ENABLED 0
-#endif
-
-//  APP_USBD_HID_KBD_ENABLED  - app_usbd_hid_kbd - USB HID keyboard
-
-
-#ifndef APP_USBD_HID_KBD_ENABLED
-#define APP_USBD_HID_KBD_ENABLED 0
-#endif
-
-//  APP_USBD_HID_MOUSE_ENABLED  - app_usbd_hid_mouse - USB HID mouse
-
-
-#ifndef APP_USBD_HID_MOUSE_ENABLED
-#define APP_USBD_HID_MOUSE_ENABLED 0
-#endif
-
-//  BUTTON_ENABLED  - app_button - buttons handling module
-
-
-#ifndef BUTTON_ENABLED
-#define BUTTON_ENABLED 1
-#endif
-
-//  CRC16_ENABLED  - crc16 - CRC16 calculation routines
-
-
-#ifndef CRC16_ENABLED
-#define CRC16_ENABLED 0
-#endif
-
-//  CRC32_ENABLED  - crc32 - CRC32 calculation routines
-
-
-#ifndef CRC32_ENABLED
-#define CRC32_ENABLED 0
-#endif
-
-//  ECC_ENABLED  - ecc - Elliptic Curve Cryptography Library
-
-
-#ifndef ECC_ENABLED
-#define ECC_ENABLED 0
-#endif
-
-//  FDS_ENABLED - fds - Flash data storage module
-//==========================================================
-#ifndef FDS_ENABLED
-#define FDS_ENABLED 0
-#endif
-#if  FDS_ENABLED
-//  FDS_OP_QUEUE_SIZE - Size of the internal queue.
-#ifndef FDS_OP_QUEUE_SIZE
-#define FDS_OP_QUEUE_SIZE 4
-#endif
-
-//  FDS_CHUNK_QUEUE_SIZE - Determines how many @ref fds_record_chunk_t structures can be buffered at any time.
-#ifndef FDS_CHUNK_QUEUE_SIZE
-#define FDS_CHUNK_QUEUE_SIZE 8
-#endif
-
-//  FDS_MAX_USERS - Maximum number of callbacks that can be registered.
-#ifndef FDS_MAX_USERS
-#define FDS_MAX_USERS 8
-#endif
-
-//  FDS_VIRTUAL_PAGES - Number of virtual flash pages to use.
-//  One of the virtual pages is reserved by the system for garbage collection.
-//  Therefore, the minimum is two virtual pages: one page to store data and
-//  one page to be used by the system for garbage collection. The total amount
-//  of flash memory that is used by FDS amounts to @ref FDS_VIRTUAL_PAGES
-//  @ref FDS_VIRTUAL_PAGE_SIZE * 4 bytes.
-
-#ifndef FDS_VIRTUAL_PAGES
-#define FDS_VIRTUAL_PAGES 3
-#endif
-
-//  FDS_VIRTUAL_PAGE_SIZE  - The size of a virtual page of flash memory, expressed in number of 4-byte words.
-
-
-//  By default, a virtual page is the same size as a physical page.
-//  The size of a virtual page must be a multiple of the size of a physical page.
-// <1024=> 1024
-// <2048=> 2048
-
-#ifndef FDS_VIRTUAL_PAGE_SIZE
-#define FDS_VIRTUAL_PAGE_SIZE 1024
-#endif
-
-#endif //FDS_ENABLED
-// 
-
-//  FSTORAGE_ENABLED - fstorage - Flash storage module
-//==========================================================
-#ifndef FSTORAGE_ENABLED
-#define FSTORAGE_ENABLED 1
-#endif
-#if  FSTORAGE_ENABLED
-//  FS_QUEUE_SIZE - Configures the size of the internal queue.
-//  Increase this if there are many users, or if it is likely that many
-//  operation will be queued at once without waiting for the previous operations
-//  to complete. In general, increase the queue size if you frequently receive
-//  @ref FS_ERR_QUEUE_FULL errors when calling @ref fs_store or @ref fs_erase.
-
-#ifndef FS_QUEUE_SIZE
-#define FS_QUEUE_SIZE 4
-#endif
-
-//  FS_OP_MAX_RETRIES - Number attempts to execute an operation if the SoftDevice fails.
-//  Increase this value if events return the @ref FS_ERR_OPERATION_TIMEOUT
-//  error often. The SoftDevice may fail to schedule flash access due to high BLE activity.
-
-#ifndef FS_OP_MAX_RETRIES
-#define FS_OP_MAX_RETRIES 3
-#endif
-
-//  FS_MAX_WRITE_SIZE_WORDS - Maximum number of words to be written to flash in a single operation.
-//  Tweaking this value can increase the chances of the SoftDevice being
-//  able to fit flash operations in between radio activity. This value is bound by the
-//  maximum number of words which the SoftDevice can write to flash in a single call to
-//  @ref sd_flash_write, which is 256 words for nRF51 ICs and 1024 words for nRF52 ICs.
-
-#ifndef FS_MAX_WRITE_SIZE_WORDS
-#define FS_MAX_WRITE_SIZE_WORDS 1024
-#endif
-
-#endif //FSTORAGE_ENABLED
-// 
-
-//  HARDFAULT_HANDLER_ENABLED  - hardfault_default - HardFault default handler for debugging and release
-
-
-#ifndef HARDFAULT_HANDLER_ENABLED
-#define HARDFAULT_HANDLER_ENABLED 0
-#endif
-
-//  HCI_MEM_POOL_ENABLED - hci_mem_pool - memory pool implementation used by HCI
-//==========================================================
-#ifndef HCI_MEM_POOL_ENABLED
-#define HCI_MEM_POOL_ENABLED 0
-#endif
-#if  HCI_MEM_POOL_ENABLED
-//  HCI_TX_BUF_SIZE - TX buffer size in bytes.
-#ifndef HCI_TX_BUF_SIZE
-#define HCI_TX_BUF_SIZE 600
-#endif
-
-//  HCI_RX_BUF_SIZE - RX buffer size in bytes.
-#ifndef HCI_RX_BUF_SIZE
-#define HCI_RX_BUF_SIZE 600
-#endif
-
-//  HCI_RX_BUF_QUEUE_SIZE - RX buffer queue size.
-#ifndef HCI_RX_BUF_QUEUE_SIZE
-#define HCI_RX_BUF_QUEUE_SIZE 4
-#endif
-
-#endif //HCI_MEM_POOL_ENABLED
-// 
-
-//  HCI_SLIP_ENABLED - hci_slip - SLIP protocol implementation used by HCI
-//==========================================================
-#ifndef HCI_SLIP_ENABLED
-#define HCI_SLIP_ENABLED 0
-#endif
-#if  HCI_SLIP_ENABLED
-//  HCI_UART_BAUDRATE  - Default Baudrate
-
-// <323584=> 1200 baud
-// <643072=> 2400 baud
-// <1290240=> 4800 baud
-// <2576384=> 9600 baud
-// <3862528=> 14400 baud
-// <5152768=> 19200 baud
-// <7716864=> 28800 baud
-// <10289152=> 38400 baud
-// <15400960=> 57600 baud
-// <20615168=> 76800 baud
-// <30801920=> 115200 baud
-// <61865984=> 230400 baud
-// <67108864=> 250000 baud
-// <121634816=> 460800 baud
-// <251658240=> 921600 baud
-// <268435456=> 57600 baud
-
-#ifndef HCI_UART_BAUDRATE
-#define HCI_UART_BAUDRATE 30801920
-#endif
-
-//  HCI_UART_FLOW_CONTROL  - Hardware Flow Control
-
-// <0=> Disabled
-// <1=> Enabled
-
-#ifndef HCI_UART_FLOW_CONTROL
-#define HCI_UART_FLOW_CONTROL 0
-#endif
-
-//  HCI_UART_RX_PIN - UART RX pin
-#ifndef HCI_UART_RX_PIN
-#define HCI_UART_RX_PIN 8
-#endif
-
-//  HCI_UART_TX_PIN - UART TX pin
-#ifndef HCI_UART_TX_PIN
-#define HCI_UART_TX_PIN 6
-#endif
-
-//  HCI_UART_RTS_PIN - UART RTS pin
-#ifndef HCI_UART_RTS_PIN
-#define HCI_UART_RTS_PIN 5
-#endif
-
-//  HCI_UART_CTS_PIN - UART CTS pin
-#ifndef HCI_UART_CTS_PIN
-#define HCI_UART_CTS_PIN 7
-#endif
-
-#endif //HCI_SLIP_ENABLED
-// 
-
-//  HCI_TRANSPORT_ENABLED - hci_transport - HCI transport
-//==========================================================
-#ifndef HCI_TRANSPORT_ENABLED
-#define HCI_TRANSPORT_ENABLED 0
-#endif
-#if  HCI_TRANSPORT_ENABLED
-//  HCI_MAX_PACKET_SIZE_IN_BITS - Maximum size of a single application packet in bits.
-#ifndef HCI_MAX_PACKET_SIZE_IN_BITS
-#define HCI_MAX_PACKET_SIZE_IN_BITS 8000
-#endif
-
-#endif //HCI_TRANSPORT_ENABLED
-// 
-
-//  LED_SOFTBLINK_ENABLED  - led_softblink - led_softblink module
-
-
-#ifndef LED_SOFTBLINK_ENABLED
-#define LED_SOFTBLINK_ENABLED 0
-#endif
-
-//  LOW_POWER_PWM_ENABLED  - low_power_pwm - low_power_pwm module
-
-
-#ifndef LOW_POWER_PWM_ENABLED
-#define LOW_POWER_PWM_ENABLED 0
-#endif
-
-//  MEM_MANAGER_ENABLED - mem_manager - Dynamic memory allocator
-//==========================================================
-#ifndef MEM_MANAGER_ENABLED
-#define MEM_MANAGER_ENABLED 0
-#endif
-#if  MEM_MANAGER_ENABLED
-//  MEMORY_MANAGER_SMALL_BLOCK_COUNT - Size of each memory blocks identified as 'small' block.  <0-255>
-
-
-#ifndef MEMORY_MANAGER_SMALL_BLOCK_COUNT
-#define MEMORY_MANAGER_SMALL_BLOCK_COUNT 1
-#endif
-
-//  MEMORY_MANAGER_SMALL_BLOCK_SIZE -  Size of each memory blocks identified as 'small' block.
-//   Size of each memory blocks identified as 'small' block. Memory block are recommended to be word-sized.
-
-#ifndef MEMORY_MANAGER_SMALL_BLOCK_SIZE
-#define MEMORY_MANAGER_SMALL_BLOCK_SIZE 32
-#endif
-
-//  MEMORY_MANAGER_MEDIUM_BLOCK_COUNT - Size of each memory blocks identified as 'medium' block.  <0-255>
-
-
-#ifndef MEMORY_MANAGER_MEDIUM_BLOCK_COUNT
-#define MEMORY_MANAGER_MEDIUM_BLOCK_COUNT 0
-#endif
-
-//  MEMORY_MANAGER_MEDIUM_BLOCK_SIZE -  Size of each memory blocks identified as 'medium' block.
-//   Size of each memory blocks identified as 'medium' block. Memory block are recommended to be word-sized.
-
-#ifndef MEMORY_MANAGER_MEDIUM_BLOCK_SIZE
-#define MEMORY_MANAGER_MEDIUM_BLOCK_SIZE 256
-#endif
-
-//  MEMORY_MANAGER_LARGE_BLOCK_COUNT - Size of each memory blocks identified as 'large' block.  <0-255>
-
-
-#ifndef MEMORY_MANAGER_LARGE_BLOCK_COUNT
-#define MEMORY_MANAGER_LARGE_BLOCK_COUNT 0
-#endif
-
-//  MEMORY_MANAGER_LARGE_BLOCK_SIZE -  Size of each memory blocks identified as 'large' block.
-//   Size of each memory blocks identified as 'large' block. Memory block are recommended to be word-sized.
-
-#ifndef MEMORY_MANAGER_LARGE_BLOCK_SIZE
-#define MEMORY_MANAGER_LARGE_BLOCK_SIZE 256
-#endif
-
-//  MEMORY_MANAGER_XLARGE_BLOCK_COUNT - Size of each memory blocks identified as 'extra large' block.  <0-255>
-
-
-#ifndef MEMORY_MANAGER_XLARGE_BLOCK_COUNT
-#define MEMORY_MANAGER_XLARGE_BLOCK_COUNT 0
-#endif
-
-//  MEMORY_MANAGER_XLARGE_BLOCK_SIZE -  Size of each memory blocks identified as 'extra large' block.
-//   Size of each memory blocks identified as 'extra large' block. Memory block are recommended to be word-sized.
-
-#ifndef MEMORY_MANAGER_XLARGE_BLOCK_SIZE
-#define MEMORY_MANAGER_XLARGE_BLOCK_SIZE 1320
-#endif
-
-//  MEMORY_MANAGER_XXLARGE_BLOCK_COUNT - Size of each memory blocks identified as 'extra extra large' block.  <0-255>
-
-
-#ifndef MEMORY_MANAGER_XXLARGE_BLOCK_COUNT
-#define MEMORY_MANAGER_XXLARGE_BLOCK_COUNT 0
-#endif
-
-//  MEMORY_MANAGER_XXLARGE_BLOCK_SIZE -  Size of each memory blocks identified as 'extra extra large' block.
-//   Size of each memory blocks identified as 'extra extra large' block. Memory block are recommended to be word-sized.
-
-#ifndef MEMORY_MANAGER_XXLARGE_BLOCK_SIZE
-#define MEMORY_MANAGER_XXLARGE_BLOCK_SIZE 3444
-#endif
-
-//  MEMORY_MANAGER_XSMALL_BLOCK_COUNT - Size of each memory blocks identified as 'extra small' block.  <0-255>
-
-
-#ifndef MEMORY_MANAGER_XSMALL_BLOCK_COUNT
-#define MEMORY_MANAGER_XSMALL_BLOCK_COUNT 0
-#endif
-
-//  MEMORY_MANAGER_XSMALL_BLOCK_SIZE -  Size of each memory blocks identified as 'extra small' block.
-//   Size of each memory blocks identified as 'extra large' block. Memory block are recommended to be word-sized.
-
-#ifndef MEMORY_MANAGER_XSMALL_BLOCK_SIZE
-#define MEMORY_MANAGER_XSMALL_BLOCK_SIZE 64
-#endif
-
-//  MEMORY_MANAGER_XXSMALL_BLOCK_COUNT - Size of each memory blocks identified as 'extra extra small' block.  <0-255>
-
-
-#ifndef MEMORY_MANAGER_XXSMALL_BLOCK_COUNT
-#define MEMORY_MANAGER_XXSMALL_BLOCK_COUNT 0
-#endif
-
-//  MEMORY_MANAGER_XXSMALL_BLOCK_SIZE -  Size of each memory blocks identified as 'extra extra small' block.
-//   Size of each memory blocks identified as 'extra extra small' block. Memory block are recommended to be word-sized.
-
-#ifndef MEMORY_MANAGER_XXSMALL_BLOCK_SIZE
-#define MEMORY_MANAGER_XXSMALL_BLOCK_SIZE 32
-#endif
-
-//  MEM_MANAGER_ENABLE_LOGS  - Enable debug trace in the module.
-
-
-#ifndef MEM_MANAGER_ENABLE_LOGS
-#define MEM_MANAGER_ENABLE_LOGS 0
-#endif
-
-//  MEM_MANAGER_DISABLE_API_PARAM_CHECK  - Disable API parameter checks in the module.
-
-
-#ifndef MEM_MANAGER_DISABLE_API_PARAM_CHECK
-#define MEM_MANAGER_DISABLE_API_PARAM_CHECK 0
-#endif
-
-#endif //MEM_MANAGER_ENABLED
-// 
-
-//  NRF_CSENSE_ENABLED - nrf_csense - Capacitive sensor module
-//==========================================================
-#ifndef NRF_CSENSE_ENABLED
-#define NRF_CSENSE_ENABLED 0
-#endif
-#if  NRF_CSENSE_ENABLED
-//  NRF_CSENSE_PAD_HYSTERESIS - Minimum value of change required to determine that a pad was touched.
-#ifndef NRF_CSENSE_PAD_HYSTERESIS
-#define NRF_CSENSE_PAD_HYSTERESIS 15
-#endif
-
-//  NRF_CSENSE_PAD_DEVIATION - Minimum value measured on a pad required to take it into account while calculating the step.
-#ifndef NRF_CSENSE_PAD_DEVIATION
-#define NRF_CSENSE_PAD_DEVIATION 70
-#endif
-
-//  NRF_CSENSE_MIN_PAD_VALUE - Minimum normalized value on a pad required to take its value into account.
-#ifndef NRF_CSENSE_MIN_PAD_VALUE
-#define NRF_CSENSE_MIN_PAD_VALUE 20
-#endif
-
-//  NRF_CSENSE_MAX_PADS_NUMBER - Maximum number of pads used for one instance.
-#ifndef NRF_CSENSE_MAX_PADS_NUMBER
-#define NRF_CSENSE_MAX_PADS_NUMBER 20
-#endif
-
-//  NRF_CSENSE_MAX_VALUE - Maximum normalized value obtained from measurement.
-#ifndef NRF_CSENSE_MAX_VALUE
-#define NRF_CSENSE_MAX_VALUE 1000
-#endif
-
-//  NRF_CSENSE_OUTPUT_PIN - Output pin used by the low-level module.
-//  This is used when capacitive sensor does not use COMP.
-
-#ifndef NRF_CSENSE_OUTPUT_PIN
-#define NRF_CSENSE_OUTPUT_PIN 26
-#endif
-
-#endif //NRF_CSENSE_ENABLED
-// 
-
-//  NRF_DRV_CSENSE_ENABLED - nrf_drv_csense - Capacitive sensor low-level module
-//==========================================================
-#ifndef NRF_DRV_CSENSE_ENABLED
-#define NRF_DRV_CSENSE_ENABLED 0
-#endif
-#if  NRF_DRV_CSENSE_ENABLED
-//  USE_COMP - Use the comparator to implement the capacitive sensor driver.
-
-//  Due to Anomaly 84, COMP I_SOURCE is not functional. It has too high a varation.
-//==========================================================
-#ifndef USE_COMP
-#define USE_COMP 0
-#endif
-#if  USE_COMP
-//  TIMER0_FOR_CSENSE - First TIMER instance used by the driver (not used on nRF51).
-#ifndef TIMER0_FOR_CSENSE
-#define TIMER0_FOR_CSENSE 1
-#endif
-
-//  TIMER1_FOR_CSENSE - Second TIMER instance used by the driver (not used on nRF51).
-#ifndef TIMER1_FOR_CSENSE
-#define TIMER1_FOR_CSENSE 2
-#endif
-
-//  MEASUREMENT_PERIOD - Single measurement period.
-//  Time of a single measurement can be calculated as
-//  T = (1/2)*MEASUREMENT_PERIOD*(1/f_OSC) where f_OSC = I_SOURCE / (2C*(VUP-VDOWN) ).
-//  I_SOURCE, VUP, and VDOWN are values used to initialize COMP and C is the capacitance of the used pad.
-
-#ifndef MEASUREMENT_PERIOD
-#define MEASUREMENT_PERIOD 20
-#endif
-
-#endif //USE_COMP
-// 
-
-#endif //NRF_DRV_CSENSE_ENABLED
-// 
-
-//  NRF_QUEUE_ENABLED  - nrf_queue - Queue module
-
-
-#ifndef NRF_QUEUE_ENABLED
-#define NRF_QUEUE_ENABLED 0
-#endif
-
-//  NRF_STRERROR_ENABLED  - nrf_strerror - Library for converting error code to string.
-
-
-#ifndef NRF_STRERROR_ENABLED
-#define NRF_STRERROR_ENABLED 1
-#endif
-
-//  RETARGET_ENABLED  - retarget - Retargeting stdio functions
-
-
-#ifndef RETARGET_ENABLED
-#define RETARGET_ENABLED 1
-#endif
-
-//  SLIP_ENABLED  - slip - SLIP encoding and decoding
-
-
-#ifndef SLIP_ENABLED
-#define SLIP_ENABLED 0
-#endif
-
-//  app_usbd_cdc_acm - USB CDC ACM class
-
-//==========================================================
-//  APP_USBD_CLASS_CDC_ACM_ENABLED  - Enabling USBD CDC ACM Class library
-
-
-#ifndef APP_USBD_CLASS_CDC_ACM_ENABLED
-#define APP_USBD_CLASS_CDC_ACM_ENABLED 0
-#endif
-
-//  APP_USBD_CDC_ACM_LOG_ENABLED  - Enables logging in the module.
-
-
-#ifndef APP_USBD_CDC_ACM_LOG_ENABLED
-#define APP_USBD_CDC_ACM_LOG_ENABLED 0
-#endif
-
-// 
-//==========================================================
-
-//  app_usbd_msc - USB MSC class
-
-//==========================================================
-//  APP_USBD_CLASS_MSC_ENABLED  - Enabling USBD MSC Class library
-
-
-#ifndef APP_USBD_CLASS_MSC_ENABLED
-#define APP_USBD_CLASS_MSC_ENABLED 0
-#endif
-
-//  APP_USBD_MSC_CLASS_LOG_ENABLED  - Enables logging in the module.
-
-
-#ifndef APP_USBD_MSC_CLASS_LOG_ENABLED
-#define APP_USBD_MSC_CLASS_LOG_ENABLED 0
-#endif
-
-// 
-//==========================================================
-
-// 
-//==========================================================
-
-//  nRF_Log
-
-//==========================================================
-//  NRF_LOG_ENABLED - nrf_log - Logging
-//==========================================================
-#ifndef NRF_LOG_ENABLED
-#define NRF_LOG_ENABLED 0
-#endif
-#if  NRF_LOG_ENABLED
-//  NRF_LOG_USES_COLORS - If enabled then ANSI escape code for colors is prefixed to every string
-//==========================================================
-#ifndef NRF_LOG_USES_COLORS
-#define NRF_LOG_USES_COLORS 0
-#endif
-#if  NRF_LOG_USES_COLORS
-//  NRF_LOG_COLOR_DEFAULT  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRF_LOG_COLOR_DEFAULT
-#define NRF_LOG_COLOR_DEFAULT 0
-#endif
-
-//  NRF_LOG_ERROR_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRF_LOG_ERROR_COLOR
-#define NRF_LOG_ERROR_COLOR 0
-#endif
-
-//  NRF_LOG_WARNING_COLOR  - ANSI escape code prefix.
-
-// <0=> Default
-// <1=> Black
-// <2=> Red
-// <3=> Green
-// <4=> Yellow
-// <5=> Blue
-// <6=> Magenta
-// <7=> Cyan
-// <8=> White
-
-#ifndef NRF_LOG_WARNING_COLOR
-#define NRF_LOG_WARNING_COLOR 0
-#endif
-
-#endif //NRF_LOG_USES_COLORS
-// 
-
-//  NRF_LOG_DEFAULT_LEVEL  - Default Severity level
-
-// <0=> Off
-// <1=> Error
-// <2=> Warning
-// <3=> Info
-// <4=> Debug
-
-#ifndef NRF_LOG_DEFAULT_LEVEL
-#define NRF_LOG_DEFAULT_LEVEL 3
-#endif
-
-//  NRF_LOG_DEFERRED - Enable deffered logger.
-
-//  Log data is buffered and can be processed in idle.
-//==========================================================
-#ifndef NRF_LOG_DEFERRED
-#define NRF_LOG_DEFERRED 0
-#endif
-#if  NRF_LOG_DEFERRED
-//  NRF_LOG_DEFERRED_BUFSIZE - Size of the buffer for logs in words.
-//  Must be power of 2
-
-#ifndef NRF_LOG_DEFERRED_BUFSIZE
-#define NRF_LOG_DEFERRED_BUFSIZE 256
-#endif
-
-#endif //NRF_LOG_DEFERRED
-// 
-
-//  NRF_LOG_USES_TIMESTAMP  - Enable timestamping
-
-
-//  Function for getting the timestamp is provided by the user
-
-#ifndef NRF_LOG_USES_TIMESTAMP
-#define NRF_LOG_USES_TIMESTAMP 0
-#endif
-
-#endif //NRF_LOG_ENABLED
-// 
-
-//  nrf_log_backend - Logging sink
-
-//==========================================================
-//  NRF_LOG_BACKEND_MAX_STRING_LENGTH - Buffer for storing single output string
-//  Logger backend RAM usage is determined by this value.
-
-#ifndef NRF_LOG_BACKEND_MAX_STRING_LENGTH
-#define NRF_LOG_BACKEND_MAX_STRING_LENGTH 256
-#endif
-
-//  NRF_LOG_TIMESTAMP_DIGITS - Number of digits for timestamp
-//  If higher resolution timestamp source is used it might be needed to increase that
-
-#ifndef NRF_LOG_TIMESTAMP_DIGITS
-#define NRF_LOG_TIMESTAMP_DIGITS 8
-#endif
-
-//  NRF_LOG_BACKEND_SERIAL_USES_UART - If enabled data is printed over UART
-//==========================================================
-#ifndef NRF_LOG_BACKEND_SERIAL_USES_UART
-#define NRF_LOG_BACKEND_SERIAL_USES_UART 0
-#endif
-#if  NRF_LOG_BACKEND_SERIAL_USES_UART
-//  NRF_LOG_BACKEND_SERIAL_UART_BAUDRATE  - Default Baudrate
-
-// <323584=> 1200 baud
-// <643072=> 2400 baud
-// <1290240=> 4800 baud
-// <2576384=> 9600 baud
-// <3862528=> 14400 baud
-// <5152768=> 19200 baud
-// <7716864=> 28800 baud
-// <10289152=> 38400 baud
-// <15400960=> 57600 baud
-// <20615168=> 76800 baud
-// <30801920=> 115200 baud
-// <61865984=> 230400 baud
-// <67108864=> 250000 baud
-// <121634816=> 460800 baud
-// <251658240=> 921600 baud
-// <268435456=> 57600 baud
-
-#ifndef NRF_LOG_BACKEND_SERIAL_UART_BAUDRATE
-#define NRF_LOG_BACKEND_SERIAL_UART_BAUDRATE 30801920
-#endif
-
-//  NRF_LOG_BACKEND_SERIAL_UART_TX_PIN - UART TX pin
-#ifndef NRF_LOG_BACKEND_SERIAL_UART_TX_PIN
-#define NRF_LOG_BACKEND_SERIAL_UART_TX_PIN 4
-#endif
-
-//  NRF_LOG_BACKEND_SERIAL_UART_RX_PIN - UART RX pin
-#ifndef NRF_LOG_BACKEND_SERIAL_UART_RX_PIN
-#define NRF_LOG_BACKEND_SERIAL_UART_RX_PIN 3
-#endif
-
-//  NRF_LOG_BACKEND_SERIAL_UART_RTS_PIN - UART RTS pin
-#ifndef NRF_LOG_BACKEND_SERIAL_UART_RTS_PIN
-#define NRF_LOG_BACKEND_SERIAL_UART_RTS_PIN 5
-#endif
-
-//  NRF_LOG_BACKEND_SERIAL_UART_CTS_PIN - UART CTS pin
-#ifndef NRF_LOG_BACKEND_SERIAL_UART_CTS_PIN
-#define NRF_LOG_BACKEND_SERIAL_UART_CTS_PIN 7
-#endif
-
-//  NRF_LOG_BACKEND_SERIAL_UART_FLOW_CONTROL  - Hardware Flow Control
-
-// <0=> Disabled
-// <1=> Enabled
-
-#ifndef NRF_LOG_BACKEND_SERIAL_UART_FLOW_CONTROL
-#define NRF_LOG_BACKEND_SERIAL_UART_FLOW_CONTROL 0
-#endif
-
-//  NRF_LOG_BACKEND_UART_INSTANCE  - UART instance used
-
-// <0=> 0
-
-#ifndef NRF_LOG_BACKEND_UART_INSTANCE
-#define NRF_LOG_BACKEND_UART_INSTANCE 0
-#endif
-
-#endif //NRF_LOG_BACKEND_SERIAL_USES_UART
-// 
-
-//  NRF_LOG_BACKEND_SERIAL_USES_RTT - If enabled data is printed using RTT
-//==========================================================
-#ifndef NRF_LOG_BACKEND_SERIAL_USES_RTT
-#define NRF_LOG_BACKEND_SERIAL_USES_RTT 0
-#endif
-#if  NRF_LOG_BACKEND_SERIAL_USES_RTT
-//  NRF_LOG_BACKEND_RTT_OUTPUT_BUFFER_SIZE - RTT output buffer size.
-//  Should be equal or bigger than \ref NRF_LOG_BACKEND_MAX_STRING_LENGTH.
-//  This value is used in Segger RTT configuration to set the buffer size
-//  if it is bigger than default RTT buffer size.
-
-#ifndef NRF_LOG_BACKEND_RTT_OUTPUT_BUFFER_SIZE
-#define NRF_LOG_BACKEND_RTT_OUTPUT_BUFFER_SIZE 512
-#endif
-
-#endif //NRF_LOG_BACKEND_SERIAL_USES_RTT
-// 
-
-// 
-//==========================================================
-
-// 
-//==========================================================
-
-//  nRF_Segger_RTT
-
-//==========================================================
-//  segger_rtt - SEGGER RTT
-
-//==========================================================
-//  SEGGER_RTT_CONFIG_BUFFER_SIZE_UP - Size of upstream buffer.
-//  Note that either @ref NRF_LOG_BACKEND_RTT_OUTPUT_BUFFER_SIZE
-//  or this value is actually used. It depends on which one is bigger.
-
-#ifndef SEGGER_RTT_CONFIG_BUFFER_SIZE_UP
-#define SEGGER_RTT_CONFIG_BUFFER_SIZE_UP 64
-#endif
-
-//  SEGGER_RTT_CONFIG_MAX_NUM_UP_BUFFERS - Size of upstream buffer.
-#ifndef SEGGER_RTT_CONFIG_MAX_NUM_UP_BUFFERS
-#define SEGGER_RTT_CONFIG_MAX_NUM_UP_BUFFERS 2
-#endif
-
-//  SEGGER_RTT_CONFIG_BUFFER_SIZE_DOWN - Size of upstream buffer.
-#ifndef SEGGER_RTT_CONFIG_BUFFER_SIZE_DOWN
-#define SEGGER_RTT_CONFIG_BUFFER_SIZE_DOWN 16
-#endif
-
-//  SEGGER_RTT_CONFIG_MAX_NUM_DOWN_BUFFERS - Size of upstream buffer.
-#ifndef SEGGER_RTT_CONFIG_MAX_NUM_DOWN_BUFFERS
-#define SEGGER_RTT_CONFIG_MAX_NUM_DOWN_BUFFERS 2
-#endif
-
-//  SEGGER_RTT_CONFIG_DEFAULT_MODE  - RTT behavior if the buffer is full.
-
-
-//  The following modes are supported:
-//  - SKIP  - Do not block, output nothing.
-//  - TRIM  - Do not block, output as much as fits.
-//  - BLOCK - Wait until there is space in the buffer.
-// <0=> SKIP
-// <1=> TRIM
-// <2=> BLOCK_IF_FIFO_FULL
-
-#ifndef SEGGER_RTT_CONFIG_DEFAULT_MODE
-#define SEGGER_RTT_CONFIG_DEFAULT_MODE 0
-#endif
-
-// 
-//==========================================================
-
-// 
-//==========================================================
-
-// <<< end of configuration section >>>
-#endif //SDK_CONFIG_H
-
diff --git a/bsp/nrf5x/libraries/templates/nrf52x/applications/startup.c b/bsp/nrf5x/libraries/templates/nrf52x/applications/startup.c
deleted file mode 100644
index 78a5ef7f65..0000000000
--- a/bsp/nrf5x/libraries/templates/nrf52x/applications/startup.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2015, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2015-03-01     Yangfs       the first version
- * 2015-03-27     Bernard      code cleanup.
- */
-
-#include 
-#include 
-
-#include "board.h"
-
-/**
- * @addtogroup NRF52832
- */
-
-/*@{*/
-
-extern int  rt_application_init(void);
-
-#ifdef __CC_ARM
-extern int Image$$RW_IRAM1$$ZI$$Limit;
-#define NRF_SRAM_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
-#elif __ICCARM__
-#pragma section="HEAP"
-#define NRF_SRAM_BEGIN    (__segment_end("HEAP"))
-#else
-extern int __bss_end;
-#define NRF_SRAM_BEGIN    (&__bss_end)
-#endif
-
-/**
- * This function will startup RT-Thread RTOS.
- */
-void rtthread_startup(void)
-{
-    /* init board */
-    rt_hw_board_init();
-
-    /* show version */
-    rt_show_version();
-
-    /* init timer system */
-    rt_system_timer_init();
-
-#ifdef RT_USING_HEAP
-    rt_system_heap_init((void*)NRF_SRAM_BEGIN, (void*)CHIP_SRAM_END);
-#endif
-
-    /* init scheduler system */
-    rt_system_scheduler_init();
-
-#ifdef RT_USING_COMPONENTS_INIT
-    rt_components_init();
-#endif
-
-    /* init application */
-    rt_application_init();
-
-    /* init timer thread */
-    rt_system_timer_thread_init();
-
-    /* init idle thread */
-    rt_thread_idle_init();
-
-    /* start scheduler */
-    rt_system_scheduler_start();
-
-    /* never reach here */
-    return ;
-}
-
-int main(void)
-{
-    /* disable interrupt first */
-    // rt_hw_interrupt_disable();
-
-    /* startup RT-Thread RTOS */
-    rtthread_startup();
-
-    return 0;
-}
-
-/*@}*/
diff --git a/bsp/nrf5x/libraries/templates/nrf52x/board/Kconfig b/bsp/nrf5x/libraries/templates/nrf52x/board/Kconfig
deleted file mode 100644
index 40823ab976..0000000000
--- a/bsp/nrf5x/libraries/templates/nrf52x/board/Kconfig
+++ /dev/null
@@ -1,22 +0,0 @@
-menu "Hardware Drivers Config"
-
-config SOC_NRF52832
-    bool
-    select RT_USING_COMPONENTS_INIT
-    # select RT_USING_USER_MAIN
-    default y
-
-menu "Onboard Peripheral Drivers"
-
-endmenu
-
-menu "On-chip Peripheral Drivers"
-
-    menuconfig BSP_USING_UART
-        bool "Enable UART"
-        default y
-        select RT_USING_SERIAL
-
-endmenu
-
-endmenu
diff --git a/bsp/nrf5x/libraries/templates/nrf52x/board/board.c b/bsp/nrf5x/libraries/templates/nrf52x/board/board.c
deleted file mode 100644
index 7ff8bfd9c4..0000000000
--- a/bsp/nrf5x/libraries/templates/nrf52x/board/board.c
+++ /dev/null
@@ -1,227 +0,0 @@
-#include "board.h"
-#include "drv_uart.h"
-#include "app_util_platform.h"
-#include "nrf_drv_common.h"
-#include "nrf_systick.h"
-#include "nrf_rtc.h"
-#include "nrf_drv_clock.h"
-#include "softdevice_handler.h"
-#include "nrf_drv_uart.h"
-#include "nrf_gpio.h"
-
-#include 
-#include 
-
-#define TICK_RATE_HZ  RT_TICK_PER_SECOND
-#define SYSTICK_CLOCK_HZ  ( 32768UL )
-
-#define NRF_RTC_REG        NRF_RTC1
-    /* IRQn used by the selected RTC */
-#define NRF_RTC_IRQn       RTC1_IRQn
-    /* Constants required to manipulate the NVIC. */
-#define NRF_RTC_PRESCALER  ( (uint32_t) (ROUNDED_DIV(SYSTICK_CLOCK_HZ, TICK_RATE_HZ) - 1) )
-    /* Maximum RTC ticks */
-#define NRF_RTC_MAXTICKS   ((1U<<24)-1U)
-
-static volatile uint32_t m_tick_overflow_count = 0;
-#define NRF_RTC_BITWIDTH 24
-#define OSTick_Handler     RTC1_IRQHandler
-#define EXPECTED_IDLE_TIME_BEFORE_SLEEP   2
-
-void SysTick_Configuration(void)
-{
-    nrf_drv_clock_lfclk_request(NULL);
-
-    /* Configure SysTick to interrupt at the requested rate. */
-    nrf_rtc_prescaler_set(NRF_RTC_REG, NRF_RTC_PRESCALER);
-    nrf_rtc_int_enable   (NRF_RTC_REG, RTC_INTENSET_TICK_Msk);
-    nrf_rtc_task_trigger (NRF_RTC_REG, NRF_RTC_TASK_CLEAR);
-    nrf_rtc_task_trigger (NRF_RTC_REG, NRF_RTC_TASK_START);
-    nrf_rtc_event_enable(NRF_RTC_REG, RTC_EVTEN_OVRFLW_Msk);
-
-    NVIC_SetPriority(NRF_RTC_IRQn, 0xF);
-    NVIC_EnableIRQ(NRF_RTC_IRQn);
-}
-
-static rt_tick_t _tick_distance(void)
-{
-    nrf_rtc_event_clear(NRF_RTC_REG, NRF_RTC_EVENT_COMPARE_0);
-
-    uint32_t systick_counter = nrf_rtc_counter_get(NRF_RTC_REG);
-    nrf_rtc_event_clear(NRF_RTC_REG, NRF_RTC_EVENT_TICK);
-
-    /* check for overflow in TICK counter */
-    if(nrf_rtc_event_pending(NRF_RTC_REG, NRF_RTC_EVENT_OVERFLOW))
-    {
-        nrf_rtc_event_clear(NRF_RTC_REG, NRF_RTC_EVENT_OVERFLOW);
-        m_tick_overflow_count++;
-    }
-
-    return ((m_tick_overflow_count << NRF_RTC_BITWIDTH) + systick_counter) - rt_tick_get();
-}
-
-void OSTick_Handler( void )
-{
-    uint32_t diff;
-
-	/* enter interrupt */
-    rt_interrupt_enter();
-    diff = _tick_distance();
-
-    while((diff--) > 0)
-    {
-        if (rt_thread_self() != RT_NULL)
-        {
-          rt_tick_increase();
-        }
-    }
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-
-static void _wakeup_tick_adjust(void)
-{
-    uint32_t diff;
-    uint32_t level;
-
-    level = rt_hw_interrupt_disable();
-
-    diff = _tick_distance();
-
-    rt_tick_set(rt_tick_get() + diff);
-
-    if (rt_thread_self() != RT_NULL)
-    {
-    	struct rt_thread *thread;
-
-        /* check time slice */
-        thread = rt_thread_self();
-
-        if (thread->remaining_tick <= diff)
-        {
-            /* change to initialized tick */
-            thread->remaining_tick = thread->init_tick;
-
-            /* yield */
-            rt_thread_yield();
-        }
-        else
-        {
-            thread->remaining_tick -= diff;
-        }
-
-        /* check timer */
-        rt_timer_check();
-    }
-
-    rt_hw_interrupt_enable(level);
-}
-
-static void _sleep_ongo( uint32_t sleep_tick )
-{
-    uint32_t enterTime;
-    uint32_t entry_tick;
-
-    /* Make sure the SysTick reload value does not overflow the counter. */
-    if ( sleep_tick > NRF_RTC_MAXTICKS - EXPECTED_IDLE_TIME_BEFORE_SLEEP )
-    {
-        sleep_tick = NRF_RTC_MAXTICKS - EXPECTED_IDLE_TIME_BEFORE_SLEEP;
-    }
-
-    rt_enter_critical();
-
-    enterTime = nrf_rtc_counter_get(NRF_RTC_REG);
-
-    {
-        uint32_t wakeupTime = (enterTime + sleep_tick) & NRF_RTC_MAXTICKS;
-
-        /* Stop tick events */
-        nrf_rtc_int_disable(NRF_RTC_REG, NRF_RTC_INT_TICK_MASK);
-
-        /* Configure CTC interrupt */
-        nrf_rtc_cc_set(NRF_RTC_REG, 0, wakeupTime);
-        nrf_rtc_event_clear(NRF_RTC_REG, NRF_RTC_EVENT_COMPARE_0);
-        nrf_rtc_int_enable(NRF_RTC_REG, NRF_RTC_INT_COMPARE0_MASK);
-
-        entry_tick = rt_tick_get();
-
-        __DSB();
-
-        if ( sleep_tick > 0 )
-        {
-#ifdef SOFTDEVICE_PRESENT
-            if (softdevice_handler_is_enabled())
-            {
-                uint32_t err_code = sd_app_evt_wait();
-                APP_ERROR_CHECK(err_code);
-            }
-            else
-#endif
-            {
-                /* No SD -  we would just block interrupts globally.
-                * BASEPRI cannot be used for that because it would prevent WFE from wake up.
-                */
-                do{
-                    __WFE();
-                } while (0 == (NVIC->ISPR[0] | NVIC->ISPR[1]));
-            }
-        }
-
-        nrf_rtc_int_disable(NRF_RTC_REG, NRF_RTC_INT_COMPARE0_MASK);
-        nrf_rtc_event_clear(NRF_RTC_REG, NRF_RTC_EVENT_COMPARE_0);
-
-        _wakeup_tick_adjust();
-
-        /* Correct the system ticks */
-        {
-
-            nrf_rtc_event_clear(NRF_RTC_REG, NRF_RTC_EVENT_TICK);
-            nrf_rtc_int_enable (NRF_RTC_REG, NRF_RTC_INT_TICK_MASK);
-            /* It is important that we clear pending here so that our corrections are latest and in sync with tick_interrupt handler */
-            NVIC_ClearPendingIRQ(NRF_RTC_IRQn);
-        }
-
-        // rt_kprintf("entry tick:%u, expected:%u, current tick:%u\n", entry_tick, sleep_tick, rt_tick_get());
-    }
-
-    rt_exit_critical();
-}
-
-
-void rt_hw_system_powersave(void)
-{
-    uint32_t sleep_tick;
-
-    sleep_tick = rt_timer_next_timeout_tick() - rt_tick_get();
-
-    if ( sleep_tick >= EXPECTED_IDLE_TIME_BEFORE_SLEEP)
-    {
-        // rt_kprintf("sleep entry:%u\n", rt_tick_get());
-        _sleep_ongo( sleep_tick );
-    }
-}
-
-void rt_hw_board_init(void)
-{
-    // sd_power_dcdc_mode_set(NRF_POWER_DCDC_ENABLE);
-    /* Activate deep sleep mode */
-    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
-    nrf_drv_clock_init();
-    // nrf_drv_clock_hfclk_request(0);
-
-    SysTick_Configuration();
-
-    rt_thread_idle_sethook(rt_hw_system_powersave);
-
-    rt_hw_uart_init();
-
-#ifdef RT_USING_CONSOLE
-    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
-#endif
-
-#ifdef RT_USING_COMPONENTS_INIT
-    rt_components_board_init();
-#endif
-}
-
diff --git a/bsp/nrf5x/libraries/templates/nrf52x/board/board.h b/bsp/nrf5x/libraries/templates/nrf52x/board/board.h
deleted file mode 100644
index f9d291792a..0000000000
--- a/bsp/nrf5x/libraries/templates/nrf52x/board/board.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-#include 
-
-#include "nrf.h"
-
-#define CHIP_SRAM_END       (0x20000000 + 64*1024)
-
-void rt_hw_board_init(void);
-
-#endif
-
diff --git a/bsp/nrf5x/libraries/templates/nrf5x_board_kconfig b/bsp/nrf5x/libraries/templates/nrf5x_board_kconfig
deleted file mode 100644
index e69de29bb2..0000000000
diff --git a/bsp/nrf5x/libraries/templates/nrfx/.config b/bsp/nrf5x/libraries/templates/nrfx/.config
new file mode 100644
index 0000000000..33a4d2c017
--- /dev/null
+++ b/bsp/nrf5x/libraries/templates/nrfx/.config
@@ -0,0 +1,540 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+# CONFIG_RT_KSERVICE_USING_STDLIB is not set
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+CONFIG_RT_VER_NUM=0x40003
+# CONFIG_RT_USING_CPU_FFS is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+CONFIG_FINSH_USING_MSH_ONLY=y
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+# CONFIG_RT_SERIAL_USING_DMA is not set
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+# CONFIG_RT_USING_LIBC is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_LIBC_USING_TIME is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+# CONFIG_PKG_USING_LPM is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+CONFIG_PKG_USING_NRFX=y
+CONFIG_PKG_NRFX_PATH="/packages/peripherals/nrfx"
+# CONFIG_PKG_USING_NRFX_V210 is not set
+CONFIG_PKG_USING_NRFX_LATEST_VERSION=y
+CONFIG_PKG_NRFX_VER="latest"
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+
+#
+# games: games run on RT-Thread console
+#
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_COWSAY is not set
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_NRF52840=y
+CONFIG_NRFX_CLOCK_ENABLED=1
+CONFIG_NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY=7
+CONFIG_NRFX_CLOCK_CONFIG_LF_SRC=1
+CONFIG_SOC_NORDIC=y
+
+#
+# On-chip Peripheral Drivers
+#
+# CONFIG_BSP_USING_GPIO is not set
+CONFIG_BSP_USING_UART=y
+CONFIG_NRFX_USING_UART=y
+# CONFIG_NRFX_USING_UARTE is not set
+CONFIG_NRFX_UART_ENABLED=1
+CONFIG_BSP_USING_UART0=y
+CONFIG_NRFX_UART0_ENABLED=1
+CONFIG_BSP_UART0_RX_PIN=8
+CONFIG_BSP_UART0_TX_PIN=6
+
+#
+# On-chip flash config
+#
+CONFIG_MCU_FLASH_START_ADDRESS=0x00000000
+CONFIG_MCU_FLASH_SIZE_KB=1024
+CONFIG_MCU_SRAM_START_ADDRESS=0x20000000
+CONFIG_MCU_SRAM_SIZE_KB=256
+CONFIG_MCU_FLASH_PAGE_SIZE=0x1000
diff --git a/bsp/nrf5x/libraries/templates/nrf52x/Kconfig b/bsp/nrf5x/libraries/templates/nrfx/Kconfig
similarity index 100%
rename from bsp/nrf5x/libraries/templates/nrf52x/Kconfig
rename to bsp/nrf5x/libraries/templates/nrfx/Kconfig
diff --git a/bsp/nrf5x/libraries/templates/nrfx/README.md b/bsp/nrf5x/libraries/templates/nrfx/README.md
new file mode 100644
index 0000000000..c3a4a95f9f
--- /dev/null
+++ b/bsp/nrf5x/libraries/templates/nrfx/README.md
@@ -0,0 +1,77 @@
+# nRF52840-PCA10056 BSP说明
+
+## 简介
+
+该文件夹主要存放所有主芯片为nRF52840的板级支持包。目前默认支持的开发板是官方[PCA10056](https://www.nordicsemi.com/Software-and-tools/Development-Kits/nRF52840-DK)
+本文主要内容如下：
+
+- 开发板资源介绍
+- 进阶使用方法
+
+## 开发板介绍
+
+PCA10056-nRF52840是Nordic 官方的开发板，搭载nRF52840 芯片，基于ARM Cortex-M4内核，最高主频64 MHz，具有丰富的外设资源。
+
+开发板外观如下图所示
+
+![image-20201017202046725](../docs/images/nrf52840.png)
+
+PCA10056-nrf52840 开发板常用 **板载资源** 如下：
+
+- MCU：NRF52840，主频 64MHz，1MB FLASH ，256kB RAM
+- MCU 外设: GPIO, UART, SPI, I2C(TWI), RTC,TIMER,NFC,QSPI,PWM,ADC,USB,I2S
+- 板载设
+  - LED：4个，USB communication (LD1), user LED (LD2), power LED (LD3) 。
+  - 按键：5个，4个USER and 1个RESET 。
+  - USB:   1个
+- 常用接口：USB device、Arduino Uno 接口
+- 调试接口：板载 J-LINK 调试器。
+
+开发板更多详细信息请参考NORDIC官方[PCA10056](https://www.nordicsemi.com/Software-and-tools/Development-Kits/nRF52840-DK)
+
+
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **片上外设** | **支持情况** |        **备注**        |
+| :----------- | :----------: | :--------------------: |
+| GPIO         |     支持     |         GPION          |
+| UART         |     支持     |         UART0          |
+| PWM          |     支持     |          支持          |
+| SPI          |     支持     |          支持          |
+| QSPI         |     支持     | 支持开发板上QSPI FLASH |
+| RTC          |     支持     |                        |
+| ADC          |     支持     |                        |
+|              |              |                        |
+|              |              |                        |
+|              |              |                        |
+
+
+
+### 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 串口 0 的功能，更多高级功能需要利用 env 工具对 BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。
+
+
+
+## 支持其他开发板
+
+客户可以将自己的开发板的.config文件和board/Kconfig文件到board/$(board_name)下面添加README.md即可，使用的时候替换.config文件
+
+## 注意事项
+
+## 联系人信息
+
+维护人:
+
+-  [supperthomas], 邮箱：<78900636@qq.com>
\ No newline at end of file
diff --git a/bsp/nrf5x/libraries/templates/nrf52x/SConscript b/bsp/nrf5x/libraries/templates/nrfx/SConscript
similarity index 100%
rename from bsp/nrf5x/libraries/templates/nrf52x/SConscript
rename to bsp/nrf5x/libraries/templates/nrfx/SConscript
diff --git a/bsp/nrf5x/libraries/templates/nrf52x/SConstruct b/bsp/nrf5x/libraries/templates/nrfx/SConstruct
similarity index 93%
rename from bsp/nrf5x/libraries/templates/nrf52x/SConstruct
rename to bsp/nrf5x/libraries/templates/nrfx/SConstruct
index 20d41c40ae..2ac1ce6674 100644
--- a/bsp/nrf5x/libraries/templates/nrf52x/SConstruct
+++ b/bsp/nrf5x/libraries/templates/nrfx/SConstruct
@@ -50,5 +50,8 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
 # include drivers
 objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript')))
 
+# include cmsis
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'cmsis', 'SConscript')))
+
 # make a building
 DoBuilding(TARGET, objs)
diff --git a/bsp/nrf5x/libraries/templates/nrf52x/applications/SConscript b/bsp/nrf5x/libraries/templates/nrfx/applications/SConscript
similarity index 100%
rename from bsp/nrf5x/libraries/templates/nrf52x/applications/SConscript
rename to bsp/nrf5x/libraries/templates/nrfx/applications/SConscript
diff --git a/bsp/nrf5x/libraries/templates/nrfx/applications/application.c b/bsp/nrf5x/libraries/templates/nrfx/applications/application.c
new file mode 100644
index 0000000000..87d0f04b86
--- /dev/null
+++ b/bsp/nrf5x/libraries/templates/nrfx/applications/application.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-29     supperthomas first version
+ *
+ */
+
+#include 
+#include 
+
+int main(void)
+{
+    while (1)
+    {
+        rt_thread_mdelay(500);
+    }
+    return RT_EOK;
+}
+
diff --git a/bsp/nrf5x/libraries/templates/nrfx/board/Kconfig b/bsp/nrf5x/libraries/templates/nrfx/board/Kconfig
new file mode 100644
index 0000000000..81fa49369d
--- /dev/null
+++ b/bsp/nrf5x/libraries/templates/nrfx/board/Kconfig
@@ -0,0 +1,97 @@
+menu "Hardware Drivers Config"
+
+config SOC_NRF52840
+    bool
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+    
+config SOC_NORDIC
+    bool 
+    default y
+
+choice
+    prompt "Select BSP board "
+    default BSP_BOARD_PCA_10056
+
+    config BSP_BOARD_PCA_10056
+        bool "NRF52840 pca10056 "
+        
+endchoice
+
+menu "On-chip Peripheral Drivers"    
+    config BSP_USING_UART
+		bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+            config BSP_USING_UART0
+                bool "Enable UART0"
+                default y 
+                depends on BSP_USING_UART
+                
+                config BSP_UART0_RX_PIN
+                    depends on BSP_USING_UART0
+                    int "uart0 rx pin number"
+                    default 8 if BSP_BOARD_PCA_10056
+                    
+                config BSP_UART0_TX_PIN
+                    depends on BSP_USING_UART0
+                    int "uart0 tx pin number"
+                    default 6 if BSP_BOARD_PCA_10056
+
+    menu "On-chip flash config"
+
+        config MCU_FLASH_START_ADDRESS  
+            hex "MCU FLASH START ADDRESS"
+            default 0x00000000
+
+        config MCU_FLASH_SIZE_KB  
+            int "MCU FLASH SIZE, MAX size 1024 KB"
+            default 1024
+
+        config MCU_SRAM_START_ADDRESS 
+            hex "MCU RAM START ADDRESS"
+            default 0x20000000
+
+        config MCU_SRAM_SIZE_KB  
+            int "MCU RAM SIZE"
+            default 256
+
+        config MCU_FLASH_PAGE_SIZE 
+            hex "MCU FLASH PAGE SIZE, please not change,nrfx default is 0x1000"
+            default 0x1000
+	endmenu
+
+endmenu
+
+if SOC_NORDIC
+    config NRFX_CLOCK_ENABLED
+    int 
+    default 1
+    config    NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY
+    int 
+    default 7
+    config NRFX_CLOCK_CONFIG_LF_SRC
+    int 
+    default 1    
+endif
+
+if BSP_USING_UART
+    config NRFX_USING_UART
+    bool
+    default y
+    
+    config NRFX_UART_ENABLED
+    int 
+    default 1
+    
+    config NRFX_UART0_ENABLED
+    int 
+    default 1
+    depends on BSP_USING_UART0
+endif
+
+
+endmenu
+
+
diff --git a/bsp/nrf5x/libraries/templates/nrf52x/board/SConscript b/bsp/nrf5x/libraries/templates/nrfx/board/SConscript
similarity index 78%
rename from bsp/nrf5x/libraries/templates/nrf52x/board/SConscript
rename to bsp/nrf5x/libraries/templates/nrfx/board/SConscript
index abe43c5729..27bcddd310 100644
--- a/bsp/nrf5x/libraries/templates/nrf52x/board/SConscript
+++ b/bsp/nrf5x/libraries/templates/nrfx/board/SConscript
@@ -5,6 +5,7 @@ from building import *
 cwd = GetCurrentDir()
 src = Glob('*.c')
 CPPPATH = [cwd]
+define = ['USE_APP_CONFIG']
 
-group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH,)
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH,CPPDEFINES = define)
 Return('group')
diff --git a/bsp/nrf5x/libraries/templates/nrfx/board/board.c b/bsp/nrf5x/libraries/templates/nrfx/board/board.c
new file mode 100644
index 0000000000..2cb94fb6fa
--- /dev/null
+++ b/bsp/nrf5x/libraries/templates/nrfx/board/board.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-29     supperthomas first version
+ *
+ */
+#include 
+#include 
+#include 
+
+#include "board.h"
+#include "drv_uart.h"
+#include 
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+static void clk_event_handler(nrfx_clock_evt_type_t event){}
+
+void SysTick_Configuration(void)
+{
+    nrfx_clock_init(clk_event_handler);
+    nrfx_clock_enable();
+    nrfx_clock_lfclk_start();
+    /* Set interrupt priority */
+    NVIC_SetPriority(SysTick_IRQn, 0xf);
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    nrf_systick_load_set(SystemCoreClock / RT_TICK_PER_SECOND);
+    nrf_systick_val_clear();
+    nrf_systick_csr_set(NRF_SYSTICK_CSR_CLKSOURCE_CPU | NRF_SYSTICK_CSR_TICKINT_ENABLE
+                        | NRF_SYSTICK_CSR_ENABLE);
+
+}
+
+
+void rt_hw_board_init(void)
+{
+    rt_hw_interrupt_enable(0);
+
+    SysTick_Configuration();
+
+#if defined(RT_USING_HEAP)
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+
+#ifdef RT_USING_SERIAL
+    rt_hw_uart_init();
+#endif
+
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+
+#ifdef BSP_USING_SOFTDEVICE
+    extern uint32_t  Image$$RW_IRAM1$$Base;
+    uint32_t const *const m_ram_start  = &Image$$RW_IRAM1$$Base;
+    if ((uint32_t)m_ram_start == 0x20000000)
+    {
+        rt_kprintf("\r\n using softdevice the RAM couldn't be %p,please use the templete from package\r\n", m_ram_start);
+        while (1);
+    }
+    else
+    {
+        rt_kprintf("\r\n using softdevice the RAM at %p\r\n", m_ram_start);
+    }
+#endif
+
+}
+
diff --git a/bsp/nrf5x/libraries/templates/nrfx/board/board.h b/bsp/nrf5x/libraries/templates/nrfx/board/board.h
new file mode 100644
index 0000000000..52e812fac6
--- /dev/null
+++ b/bsp/nrf5x/libraries/templates/nrfx/board/board.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-29     supperthomas first version
+ *
+ */
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include 
+#include 
+#include "nrf.h"
+
+#define MCU_FLASH_SIZE MCU_FLASH_SIZE_KB*1024
+#define MCU_FLASH_END_ADDRESS        ((uint32_t)(MCU_FLASH_START_ADDRESS + MCU_FLASH_SIZE))
+#define MCU_SRAM_SIZE MCU_SRAM_SIZE_KB*1024
+#define MCU_SRAM_END_ADDRESS        (MCU_SRAM_START_ADDRESS + MCU_SRAM_SIZE)
+
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN      ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="CSTACK"
+#define HEAP_BEGIN      (__segment_end("CSTACK"))
+#else
+extern int __bss_end__;
+#define HEAP_BEGIN      ((void *)&__bss_end__)
+#endif
+
+
+#define HEAP_END       (MCU_SRAM_END_ADDRESS)
+
+void rt_hw_board_init(void);
+
+#endif
+
diff --git a/bsp/nrf5x/libraries/templates/nrfx/board/linker_scripts/link.lds b/bsp/nrf5x/libraries/templates/nrfx/board/linker_scripts/link.lds
new file mode 100644
index 0000000000..f91b8466ca
--- /dev/null
+++ b/bsp/nrf5x/libraries/templates/nrfx/board/linker_scripts/link.lds
@@ -0,0 +1,15 @@
+/* Linker script to configure memory regions. */
+
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x100000
+  RAM (rwx) :  ORIGIN = 0x20000000, LENGTH = 0x40000
+}
+
+INCLUDE "packages/nrfx-v2.1.0/mdk/nrf_common.ld"
+
+
+
diff --git a/bsp/stm32/stm32f103-mini-system/board/linker_scripts/link.sct b/bsp/nrf5x/libraries/templates/nrfx/board/linker_scripts/link.sct
similarity index 58%
rename from bsp/stm32/stm32f103-mini-system/board/linker_scripts/link.sct
rename to bsp/nrf5x/libraries/templates/nrfx/board/linker_scripts/link.sct
index 6930ff4b50..a2f8ebd922 100644
--- a/bsp/stm32/stm32f103-mini-system/board/linker_scripts/link.sct
+++ b/bsp/nrf5x/libraries/templates/nrfx/board/linker_scripts/link.sct
@@ -2,13 +2,13 @@
 ; *** Scatter-Loading Description File generated by uVision ***
 ; *************************************************************
 
-LR_IROM1 0x08000000 0x00010000  {    ; load region size_region
-  ER_IROM1 0x08000000 0x00010000  {  ; load address = execution address
+LR_IROM1 0x00000000 0x100000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x100000  {  ; load address = execution address
    *.o (RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)
   }
-  RW_IRAM1 0x20000000 0x00005000  {  ; RW data
+  RW_IRAM1 0x20000000 0x40000  {  ; RW data
    .ANY (+RW +ZI)
   }
 }
diff --git a/bsp/nrf5x/libraries/templates/nrfx/board/nrfx_config.h b/bsp/nrf5x/libraries/templates/nrfx/board/nrfx_config.h
new file mode 100644
index 0000000000..b006b6bcd5
--- /dev/null
+++ b/bsp/nrf5x/libraries/templates/nrfx/board/nrfx_config.h
@@ -0,0 +1,47 @@
+/**
+ * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form, except as embedded into a Nordic
+ *    Semiconductor ASA integrated circuit in a product or a software update for
+ *    such product, must reproduce the above copyright notice, this list of
+ *    conditions and the following disclaimer in the documentation and/or other
+ *    materials provided with the distribution.
+ *
+ * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ *    contributors may be used to endorse or promote products derived from this
+ *    software without specific prior written permission.
+ *
+ * 4. This software, with or without modification, must only be used with a
+ *    Nordic Semiconductor ASA integrated circuit.
+ *
+ * 5. Any software provided in binary form under this license must not be reverse
+ *    engineered, decompiled, modified and/or disassembled.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef NRFX_CONFIG_H__
+#define NRFX_CONFIG_H__
+
+// TODO - temporary redirection
+#include 
+
+#endif // NRFX_CONFIG_H__
diff --git a/bsp/nrf5x/libraries/templates/nrfx/board/nrfx_glue.h b/bsp/nrf5x/libraries/templates/nrfx/board/nrfx_glue.h
new file mode 100644
index 0000000000..28025dafae
--- /dev/null
+++ b/bsp/nrf5x/libraries/templates/nrfx/board/nrfx_glue.h
@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from this
+ *    software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRFX_GLUE_H__
+#define NRFX_GLUE_H__
+
+// THIS IS A TEMPLATE FILE.
+// It should be copied to a suitable location within the host environment into
+// which nrfx is integrated, and the following macros should be provided with
+// appropriate implementations.
+// And this comment should be removed from the customized file.
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include 
+#include "nrf.h"
+/**
+ * @defgroup nrfx_glue nrfx_glue.h
+ * @{
+ * @ingroup nrfx
+ *
+ * @brief This file contains macros that should be implemented according to
+ *        the needs of the host environment into which @em nrfx is integrated.
+ */
+
+// Uncomment this line to use the standard MDK way of binding IRQ handlers
+// at linking time.
+#include 
+
+//------------------------------------------------------------------------------
+
+/**
+ * @brief Macro for placing a runtime assertion.
+ *
+ * @param expression Expression to be evaluated.
+ */
+#define NRFX_ASSERT(expression)
+
+/**
+ * @brief Macro for placing a compile time assertion.
+ *
+ * @param expression Expression to be evaluated.
+ */
+#define NRFX_STATIC_ASSERT(expression)
+
+//------------------------------------------------------------------------------
+
+/**
+ * @brief Macro for setting the priority of a specific IRQ.
+ *
+ * @param irq_number IRQ number.
+ * @param priority   Priority to be set.
+ */
+#define NRFX_IRQ_PRIORITY_SET(irq_number, priority)     NVIC_SetPriority(irq_number, priority)
+
+/**
+ * @brief Macro for enabling a specific IRQ.
+ *
+ * @param irq_number IRQ number.
+ */
+#define NRFX_IRQ_ENABLE(irq_number)     NVIC_EnableIRQ(irq_number)
+
+/**
+ * @brief Macro for checking if a specific IRQ is enabled.
+ *
+ * @param irq_number IRQ number.
+ *
+ * @retval true  If the IRQ is enabled.
+ * @retval false Otherwise.
+ */
+#define NRFX_IRQ_IS_ENABLED(irq_number)  _NRFX_IRQ_IS_ENABLED(irq_number)
+static inline bool _NRFX_IRQ_IS_ENABLED(IRQn_Type irq_number)
+{
+    return 0 != (NVIC->ISER[irq_number / 32] & (1UL << (irq_number % 32)));
+}
+
+
+/**
+ * @brief Macro for disabling a specific IRQ.
+ *
+ * @param irq_number IRQ number.
+ */
+#define NRFX_IRQ_DISABLE(irq_number)  _NRFX_IRQ_DISABLE(irq_number)
+static inline void _NRFX_IRQ_DISABLE(IRQn_Type irq_number)
+{
+    NVIC_DisableIRQ(irq_number);
+}
+
+
+/**
+ * @brief Macro for setting a specific IRQ as pending.
+ *
+ * @param irq_number IRQ number.
+ */
+#define NRFX_IRQ_PENDING_SET(irq_number)
+
+/**
+ * @brief Macro for clearing the pending status of a specific IRQ.
+ *
+ * @param irq_number IRQ number.
+ */
+#define NRFX_IRQ_PENDING_CLEAR(irq_number)
+
+/**
+ * @brief Macro for checking the pending status of a specific IRQ.
+ *
+ * @retval true  If the IRQ is pending.
+ * @retval false Otherwise.
+ */
+#define NRFX_IRQ_IS_PENDING(irq_number)
+
+/** @brief Macro for entering into a critical section. */
+#define NRFX_CRITICAL_SECTION_ENTER()
+
+/** @brief Macro for exiting from a critical section. */
+#define NRFX_CRITICAL_SECTION_EXIT()
+
+//------------------------------------------------------------------------------
+
+/**
+ * @brief When set to a non-zero value, this macro specifies that
+ *        @ref nrfx_coredep_delay_us uses a precise DWT-based solution.
+ *        A compilation error is generated if the DWT unit is not present
+ *        in the SoC used.
+ */
+#define NRFX_DELAY_DWT_BASED    0
+
+/**
+ * @brief Macro for delaying the code execution for at least the specified time.
+ *
+ * @param us_time Number of microseconds to wait.
+ */
+#define NRFX_DELAY_US(us_time)
+
+//------------------------------------------------------------------------------
+
+/** @brief Atomic 32-bit unsigned type. */
+#define nrfx_atomic_t
+
+/**
+ * @brief Macro for storing a value to an atomic object and returning its previous value.
+ *
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value  Value to store.
+ *
+ * @return Previous value of the atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_STORE(p_data, value)
+
+/**
+ * @brief Macro for running a bitwise OR operation on an atomic object and returning its previous value.
+ *
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value  Value of the second operand in the OR operation.
+ *
+ * @return Previous value of the atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_OR(p_data, value)
+
+/**
+ * @brief Macro for running a bitwise AND operation on an atomic object
+ *        and returning its previous value.
+ *
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value  Value of the second operand in the AND operation.
+ *
+ * @return Previous value of the atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_AND(p_data, value)
+
+/**
+ * @brief Macro for running a bitwise XOR operation on an atomic object
+ *        and returning its previous value.
+ *
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value  Value of the second operand in the XOR operation.
+ *
+ * @return Previous value of the atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_XOR(p_data, value)
+
+/**
+ * @brief Macro for running an addition operation on an atomic object
+ *        and returning its previous value.
+ *
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value  Value of the second operand in the ADD operation.
+ *
+ * @return Previous value of the atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_ADD(p_data, value)
+
+/**
+ * @brief Macro for running a subtraction operation on an atomic object
+ *        and returning its previous value.
+ *
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value  Value of the second operand in the SUB operation.
+ *
+ * @return Previous value of the atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_SUB(p_data, value)
+
+//------------------------------------------------------------------------------
+
+/**
+ * @brief When set to a non-zero value, this macro specifies that the
+ *        @ref nrfx_error_codes and the @ref nrfx_err_t type itself are defined
+ *        in a customized way and the default definitions from @c 
+ *        should not be used.
+ */
+#define NRFX_CUSTOM_ERROR_CODES 0
+
+//------------------------------------------------------------------------------
+
+/** @brief Bitmask that defines DPPI channels that are reserved for use outside of the nrfx library. */
+#define NRFX_DPPI_CHANNELS_USED  0
+
+/** @brief Bitmask that defines DPPI groups that are reserved for use outside of the nrfx library. */
+#define NRFX_DPPI_GROUPS_USED    0
+
+/** @brief Bitmask that defines PPI channels that are reserved for use outside of the nrfx library. */
+#define NRFX_PPI_CHANNELS_USED  0
+
+/** @brief Bitmask that defines PPI groups that are reserved for use outside of the nrfx library. */
+#define NRFX_PPI_GROUPS_USED    0
+
+/** @brief Bitmask that defines EGU instances that are reserved for use outside of the nrfx library. */
+#define NRFX_EGUS_USED          0
+
+/** @brief Bitmask that defines TIMER instances that are reserved for use outside of the nrfx library. */
+#define NRFX_TIMERS_USED        0
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRFX_GLUE_H__
diff --git a/bsp/nrf5x/libraries/templates/nrfx/board/nrfx_log.h b/bsp/nrf5x/libraries/templates/nrfx/board/nrfx_log.h
new file mode 100644
index 0000000000..80d8efbdf1
--- /dev/null
+++ b/bsp/nrf5x/libraries/templates/nrfx/board/nrfx_log.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from this
+ *    software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRFX_LOG_H__
+#define NRFX_LOG_H__
+
+// THIS IS A TEMPLATE FILE.
+// It should be copied to a suitable location within the host environment into
+// which nrfx is integrated, and the following macros should be provided with
+// appropriate implementations.
+// And this comment should be removed from the customized file.
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup nrfx_log nrfx_log.h
+ * @{
+ * @ingroup nrfx
+ *
+ * @brief This file contains macros that should be implemented according to
+ *        the needs of the host environment into which @em nrfx is integrated.
+ */
+
+/**
+ * @brief Macro for logging a message with the severity level ERROR.
+ *
+ * @param format printf-style format string, optionally followed by arguments
+ *               to be formatted and inserted in the resulting string.
+ */
+#define NRFX_LOG_ERROR(format, ...)
+
+/**
+ * @brief Macro for logging a message with the severity level WARNING.
+ *
+ * @param format printf-style format string, optionally followed by arguments
+ *               to be formatted and inserted in the resulting string.
+ */
+#define NRFX_LOG_WARNING(format, ...)
+
+/**
+ * @brief Macro for logging a message with the severity level INFO.
+ *
+ * @param format printf-style format string, optionally followed by arguments
+ *               to be formatted and inserted in the resulting string.
+ */
+#define NRFX_LOG_INFO(format, ...)
+
+/**
+ * @brief Macro for logging a message with the severity level DEBUG.
+ *
+ * @param format printf-style format string, optionally followed by arguments
+ *               to be formatted and inserted in the resulting string.
+ */
+#define NRFX_LOG_DEBUG(format, ...)
+
+
+/**
+ * @brief Macro for logging a memory dump with the severity level ERROR.
+ *
+ * @param[in] p_memory Pointer to the memory region to be dumped.
+ * @param[in] length   Length of the memory region in bytes.
+ */
+#define NRFX_LOG_HEXDUMP_ERROR(p_memory, length)
+
+/**
+ * @brief Macro for logging a memory dump with the severity level WARNING.
+ *
+ * @param[in] p_memory Pointer to the memory region to be dumped.
+ * @param[in] length   Length of the memory region in bytes.
+ */
+#define NRFX_LOG_HEXDUMP_WARNING(p_memory, length)
+
+/**
+ * @brief Macro for logging a memory dump with the severity level INFO.
+ *
+ * @param[in] p_memory Pointer to the memory region to be dumped.
+ * @param[in] length   Length of the memory region in bytes.
+ */
+#define NRFX_LOG_HEXDUMP_INFO(p_memory, length)
+
+/**
+ * @brief Macro for logging a memory dump with the severity level DEBUG.
+ *
+ * @param[in] p_memory Pointer to the memory region to be dumped.
+ * @param[in] length   Length of the memory region in bytes.
+ */
+#define NRFX_LOG_HEXDUMP_DEBUG(p_memory, length)
+
+
+/**
+ * @brief Macro for getting the textual representation of a given error code.
+ *
+ * @param[in] error_code Error code.
+ *
+ * @return String containing the textual representation of the error code.
+ */
+#define NRFX_LOG_ERROR_STRING_GET(error_code)
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRFX_LOG_H__
diff --git a/bsp/nrf5x/libraries/templates/nrfx/board/sdk_config.h b/bsp/nrf5x/libraries/templates/nrfx/board/sdk_config.h
new file mode 100644
index 0000000000..25fa4938fa
--- /dev/null
+++ b/bsp/nrf5x/libraries/templates/nrfx/board/sdk_config.h
@@ -0,0 +1,11701 @@
+/**
+ * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form, except as embedded into a Nordic
+ *    Semiconductor ASA integrated circuit in a product or a software update for
+ *    such product, must reproduce the above copyright notice, this list of
+ *    conditions and the following disclaimer in the documentation and/or other
+ *    materials provided with the distribution.
+ *
+ * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ *    contributors may be used to endorse or promote products derived from this
+ *    software without specific prior written permission.
+ *
+ * 4. This software, with or without modification, must only be used with a
+ *    Nordic Semiconductor ASA integrated circuit.
+ *
+ * 5. Any software provided in binary form under this license must not be reverse
+ *    engineered, decompiled, modified and/or disassembled.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+
+
+#ifndef SDK_CONFIG_H
+#define SDK_CONFIG_H
+// <<< Use Configuration Wizard in Context Menu >>>\n
+//  nRF_BLE
+
+#include 
+//==========================================================
+//  BLE_ADVERTISING_ENABLED  - ble_advertising - Advertising module
+
+
+#ifndef BLE_ADVERTISING_ENABLED
+#define BLE_ADVERTISING_ENABLED 0
+#endif
+
+//  BLE_DTM_ENABLED  - ble_dtm - Module for testing RF/PHY using DTM commands
+
+
+#ifndef BLE_DTM_ENABLED
+#define BLE_DTM_ENABLED 0
+#endif
+
+//  BLE_RACP_ENABLED  - ble_racp - Record Access Control Point library
+
+
+#ifndef BLE_RACP_ENABLED
+#define BLE_RACP_ENABLED 0
+#endif
+
+//  NRF_BLE_QWR_ENABLED - nrf_ble_qwr - Queued writes support module (prepare/execute write)
+//==========================================================
+#ifndef NRF_BLE_QWR_ENABLED
+#define NRF_BLE_QWR_ENABLED 0
+#endif
+//  NRF_BLE_QWR_MAX_ATTR - Maximum number of attribute handles that can be registered. This number must be adjusted according to the number of attributes for which Queued Writes will be enabled. If it is zero, the module will reject all Queued Write requests.
+#ifndef NRF_BLE_QWR_MAX_ATTR
+#define NRF_BLE_QWR_MAX_ATTR 0
+#endif
+
+// 
+
+//  PEER_MANAGER_ENABLED - peer_manager - Peer Manager
+//==========================================================
+#ifndef PEER_MANAGER_ENABLED
+#define PEER_MANAGER_ENABLED 0
+#endif
+//  PM_MAX_REGISTRANTS - Number of event handlers that can be registered.
+#ifndef PM_MAX_REGISTRANTS
+#define PM_MAX_REGISTRANTS 3
+#endif
+
+//  PM_FLASH_BUFFERS - Number of internal buffers for flash operations.
+//  Decrease this value to lower RAM usage.
+
+#ifndef PM_FLASH_BUFFERS
+#define PM_FLASH_BUFFERS 4
+#endif
+
+//  PM_CENTRAL_ENABLED  - Enable/disable central-specific Peer Manager functionality.
+
+
+//  Enable/disable central-specific Peer Manager functionality.
+
+#ifndef PM_CENTRAL_ENABLED
+#define PM_CENTRAL_ENABLED 1
+#endif
+
+//  PM_SERVICE_CHANGED_ENABLED  - Enable/disable the service changed management for GATT server in Peer Manager.
+
+
+//  If not using a GATT server, or using a server wihout a service changed characteristic,
+//  disable this to save code space.
+
+#ifndef PM_SERVICE_CHANGED_ENABLED
+#define PM_SERVICE_CHANGED_ENABLED 1
+#endif
+
+//  PM_PEER_RANKS_ENABLED  - Enable/disable the peer rank management in Peer Manager.
+
+
+//  Set this to false to save code space if not using the peer rank API.
+
+#ifndef PM_PEER_RANKS_ENABLED
+#define PM_PEER_RANKS_ENABLED 1
+#endif
+
+//  PM_LESC_ENABLED  - Enable/disable LESC support in Peer Manager.
+
+
+//  If set to true, you need to call nrf_ble_lesc_request_handler() in the main loop to respond to LESC-related BLE events. If LESC support is not required, set this to false to save code space.
+
+#ifndef PM_LESC_ENABLED
+#define PM_LESC_ENABLED 0
+#endif
+
+//  PM_RA_PROTECTION_ENABLED - Enable/disable protection against repeated pairing attempts in Peer Manager.
+//==========================================================
+#ifndef PM_RA_PROTECTION_ENABLED
+#define PM_RA_PROTECTION_ENABLED 0
+#endif
+//  PM_RA_PROTECTION_TRACKED_PEERS_NUM - Maximum number of peers whose authorization status can be tracked.
+#ifndef PM_RA_PROTECTION_TRACKED_PEERS_NUM
+#define PM_RA_PROTECTION_TRACKED_PEERS_NUM 8
+#endif
+
+//  PM_RA_PROTECTION_MIN_WAIT_INTERVAL - Minimum waiting interval (in ms) before a new pairing attempt can be initiated.
+#ifndef PM_RA_PROTECTION_MIN_WAIT_INTERVAL
+#define PM_RA_PROTECTION_MIN_WAIT_INTERVAL 4000
+#endif
+
+//  PM_RA_PROTECTION_MAX_WAIT_INTERVAL - Maximum waiting interval (in ms) before a new pairing attempt can be initiated.
+#ifndef PM_RA_PROTECTION_MAX_WAIT_INTERVAL
+#define PM_RA_PROTECTION_MAX_WAIT_INTERVAL 64000
+#endif
+
+//  PM_RA_PROTECTION_REWARD_PERIOD - Reward period (in ms).
+//  The waiting interval is gradually decreased when no new failed pairing attempts are made during reward period.
+
+#ifndef PM_RA_PROTECTION_REWARD_PERIOD
+#define PM_RA_PROTECTION_REWARD_PERIOD 10000
+#endif
+
+// 
+
+//  PM_HANDLER_SEC_DELAY_MS - Delay before starting security.
+//   This might be necessary for interoperability reasons, especially as peripheral.
+
+#ifndef PM_HANDLER_SEC_DELAY_MS
+#define PM_HANDLER_SEC_DELAY_MS 0
+#endif
+
+// 
+
+// 
+//==========================================================
+
+//  nRF_BLE_Services
+
+//==========================================================
+//  BLE_ANCS_C_ENABLED  - ble_ancs_c - Apple Notification Service Client
+
+
+#ifndef BLE_ANCS_C_ENABLED
+#define BLE_ANCS_C_ENABLED 0
+#endif
+
+//  BLE_ANS_C_ENABLED  - ble_ans_c - Alert Notification Service Client
+
+
+#ifndef BLE_ANS_C_ENABLED
+#define BLE_ANS_C_ENABLED 0
+#endif
+
+//  BLE_BAS_C_ENABLED  - ble_bas_c - Battery Service Client
+
+
+#ifndef BLE_BAS_C_ENABLED
+#define BLE_BAS_C_ENABLED 0
+#endif
+
+//  BLE_BAS_ENABLED - ble_bas - Battery Service
+//==========================================================
+#ifndef BLE_BAS_ENABLED
+#define BLE_BAS_ENABLED 0
+#endif
+//  BLE_BAS_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef BLE_BAS_CONFIG_LOG_ENABLED
+#define BLE_BAS_CONFIG_LOG_ENABLED 0
+#endif
+//  BLE_BAS_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef BLE_BAS_CONFIG_LOG_LEVEL
+#define BLE_BAS_CONFIG_LOG_LEVEL 3
+#endif
+
+//  BLE_BAS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef BLE_BAS_CONFIG_INFO_COLOR
+#define BLE_BAS_CONFIG_INFO_COLOR 0
+#endif
+
+//  BLE_BAS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef BLE_BAS_CONFIG_DEBUG_COLOR
+#define BLE_BAS_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  BLE_CSCS_ENABLED  - ble_cscs - Cycling Speed and Cadence Service
+
+
+#ifndef BLE_CSCS_ENABLED
+#define BLE_CSCS_ENABLED 0
+#endif
+
+//  BLE_CTS_C_ENABLED  - ble_cts_c - Current Time Service Client
+
+
+#ifndef BLE_CTS_C_ENABLED
+#define BLE_CTS_C_ENABLED 0
+#endif
+
+//  BLE_DIS_ENABLED  - ble_dis - Device Information Service
+
+
+#ifndef BLE_DIS_ENABLED
+#define BLE_DIS_ENABLED 0
+#endif
+
+//  BLE_GLS_ENABLED  - ble_gls - Glucose Service
+
+
+#ifndef BLE_GLS_ENABLED
+#define BLE_GLS_ENABLED 0
+#endif
+
+//  BLE_HIDS_ENABLED  - ble_hids - Human Interface Device Service
+
+
+#ifndef BLE_HIDS_ENABLED
+#define BLE_HIDS_ENABLED 0
+#endif
+
+//  BLE_HRS_C_ENABLED  - ble_hrs_c - Heart Rate Service Client
+
+
+#ifndef BLE_HRS_C_ENABLED
+#define BLE_HRS_C_ENABLED 0
+#endif
+
+//  BLE_HRS_ENABLED  - ble_hrs - Heart Rate Service
+
+
+#ifndef BLE_HRS_ENABLED
+#define BLE_HRS_ENABLED 0
+#endif
+
+//  BLE_HTS_ENABLED  - ble_hts - Health Thermometer Service
+
+
+#ifndef BLE_HTS_ENABLED
+#define BLE_HTS_ENABLED 0
+#endif
+
+//  BLE_IAS_C_ENABLED  - ble_ias_c - Immediate Alert Service Client
+
+
+#ifndef BLE_IAS_C_ENABLED
+#define BLE_IAS_C_ENABLED 0
+#endif
+
+//  BLE_IAS_ENABLED - ble_ias - Immediate Alert Service
+//==========================================================
+#ifndef BLE_IAS_ENABLED
+#define BLE_IAS_ENABLED 0
+#endif
+//  BLE_IAS_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef BLE_IAS_CONFIG_LOG_ENABLED
+#define BLE_IAS_CONFIG_LOG_ENABLED 0
+#endif
+//  BLE_IAS_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef BLE_IAS_CONFIG_LOG_LEVEL
+#define BLE_IAS_CONFIG_LOG_LEVEL 3
+#endif
+
+//  BLE_IAS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef BLE_IAS_CONFIG_INFO_COLOR
+#define BLE_IAS_CONFIG_INFO_COLOR 0
+#endif
+
+//  BLE_IAS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef BLE_IAS_CONFIG_DEBUG_COLOR
+#define BLE_IAS_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  BLE_LBS_C_ENABLED  - ble_lbs_c - Nordic LED Button Service Client
+
+
+#ifndef BLE_LBS_C_ENABLED
+#define BLE_LBS_C_ENABLED 0
+#endif
+
+//  BLE_LBS_ENABLED  - ble_lbs - LED Button Service
+
+
+#ifndef BLE_LBS_ENABLED
+#define BLE_LBS_ENABLED 0
+#endif
+
+//  BLE_LLS_ENABLED  - ble_lls - Link Loss Service
+
+
+#ifndef BLE_LLS_ENABLED
+#define BLE_LLS_ENABLED 0
+#endif
+
+//  BLE_NUS_C_ENABLED  - ble_nus_c - Nordic UART Central Service
+
+
+#ifndef BLE_NUS_C_ENABLED
+#define BLE_NUS_C_ENABLED 0
+#endif
+
+//  BLE_NUS_ENABLED - ble_nus - Nordic UART Service
+//==========================================================
+#ifndef BLE_NUS_ENABLED
+#define BLE_NUS_ENABLED 0
+#endif
+//  BLE_NUS_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef BLE_NUS_CONFIG_LOG_ENABLED
+#define BLE_NUS_CONFIG_LOG_ENABLED 0
+#endif
+//  BLE_NUS_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef BLE_NUS_CONFIG_LOG_LEVEL
+#define BLE_NUS_CONFIG_LOG_LEVEL 3
+#endif
+
+//  BLE_NUS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef BLE_NUS_CONFIG_INFO_COLOR
+#define BLE_NUS_CONFIG_INFO_COLOR 0
+#endif
+
+//  BLE_NUS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef BLE_NUS_CONFIG_DEBUG_COLOR
+#define BLE_NUS_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  BLE_RSCS_C_ENABLED  - ble_rscs_c - Running Speed and Cadence Client
+
+
+#ifndef BLE_RSCS_C_ENABLED
+#define BLE_RSCS_C_ENABLED 0
+#endif
+
+//  BLE_RSCS_ENABLED  - ble_rscs - Running Speed and Cadence Service
+
+
+#ifndef BLE_RSCS_ENABLED
+#define BLE_RSCS_ENABLED 0
+#endif
+
+//  BLE_TPS_ENABLED  - ble_tps - TX Power Service
+
+
+#ifndef BLE_TPS_ENABLED
+#define BLE_TPS_ENABLED 0
+#endif
+
+// 
+//==========================================================
+
+//  nRF_Core
+
+//==========================================================
+//  NRF_MPU_LIB_ENABLED - nrf_mpu_lib - Module for MPU
+//==========================================================
+#ifndef NRF_MPU_LIB_ENABLED
+#define NRF_MPU_LIB_ENABLED 0
+#endif
+//  NRF_MPU_LIB_CLI_CMDS  - Enable CLI commands specific to the module.
+
+
+#ifndef NRF_MPU_LIB_CLI_CMDS
+#define NRF_MPU_LIB_CLI_CMDS 0
+#endif
+
+// 
+
+//  NRF_STACK_GUARD_ENABLED - nrf_stack_guard - Stack guard
+//==========================================================
+#ifndef NRF_STACK_GUARD_ENABLED
+#define NRF_STACK_GUARD_ENABLED 0
+#endif
+//  NRF_STACK_GUARD_CONFIG_SIZE  - Size of the stack guard.
+
+// <5=> 32 bytes
+// <6=> 64 bytes
+// <7=> 128 bytes
+// <8=> 256 bytes
+// <9=> 512 bytes
+// <10=> 1024 bytes
+// <11=> 2048 bytes
+// <12=> 4096 bytes
+
+#ifndef NRF_STACK_GUARD_CONFIG_SIZE
+#define NRF_STACK_GUARD_CONFIG_SIZE 7
+#endif
+
+// 
+
+// 
+//==========================================================
+
+//  nRF_Crypto
+
+//==========================================================
+//  NRF_CRYPTO_ENABLED - nrf_crypto - Cryptography library.
+//==========================================================
+#ifndef NRF_CRYPTO_ENABLED
+#define NRF_CRYPTO_ENABLED 1
+#endif
+//  NRF_CRYPTO_ALLOCATOR  - Memory allocator
+
+
+//  Choose memory allocator used by nrf_crypto. Default is alloca if possible or nrf_malloc otherwise. If 'User macros' are selected, the user has to create 'nrf_crypto_allocator.h' file that contains NRF_CRYPTO_ALLOC, NRF_CRYPTO_FREE, and NRF_CRYPTO_ALLOC_ON_STACK.
+// <0=> Default
+// <1=> User macros
+// <2=> On stack (alloca)
+// <3=> C dynamic memory (malloc)
+// <4=> SDK Memory Manager (nrf_malloc)
+
+#ifndef NRF_CRYPTO_ALLOCATOR
+#define NRF_CRYPTO_ALLOCATOR 0
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_BL_ENABLED - Enable the ARM Cryptocell CC310 reduced backend.
+
+//  The CC310 hardware-accelerated cryptography backend with reduced functionality and footprint (only available on nRF52840).
+//==========================================================
+#ifndef NRF_CRYPTO_BACKEND_CC310_BL_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_BL_ENABLED 0
+#endif
+//  NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP224R1_ENABLED  - Enable the secp224r1 elliptic curve support using CC310_BL.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP224R1_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP224R1_ENABLED 0
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP256R1_ENABLED  - Enable the secp256r1 elliptic curve support using CC310_BL.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP256R1_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP256R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_BL_HASH_SHA256_ENABLED  - CC310_BL SHA-256 hash functionality.
+
+
+//  CC310_BL backend implementation for hardware-accelerated SHA-256.
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_BL_HASH_SHA256_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_BL_HASH_SHA256_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_ENABLED  - nrf_cc310_bl buffers to RAM before running hash operation
+
+
+//  Enabling this makes hashing of addresses in FLASH range possible. Size of buffer allocated for hashing is set by NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_ENABLED 0
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE - nrf_cc310_bl hash outputs digests in little endian
+//  Makes the nrf_cc310_bl hash functions output digests in little endian format. Only for use in nRF SDK DFU!
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE
+#define NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE 4096
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_BL_INTERRUPTS_ENABLED  - Enable Interrupts while support using CC310 bl.
+
+
+//  Select a library version compatible with the configuration. When interrupts are disable, a version named _noint must be used
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_BL_INTERRUPTS_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_BL_INTERRUPTS_ENABLED 1
+#endif
+
+// 
+
+//  NRF_CRYPTO_BACKEND_CC310_ENABLED - Enable the ARM Cryptocell CC310 backend.
+
+//  The CC310 hardware-accelerated cryptography backend (only available on nRF52840).
+//==========================================================
+#ifndef NRF_CRYPTO_BACKEND_CC310_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_ENABLED 0
+#endif
+//  NRF_CRYPTO_BACKEND_CC310_AES_CBC_ENABLED  - Enable the AES CBC mode using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CBC_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_AES_CBC_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_AES_CTR_ENABLED  - Enable the AES CTR mode using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CTR_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_AES_CTR_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_AES_ECB_ENABLED  - Enable the AES ECB mode using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_AES_ECB_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_AES_ECB_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_AES_CBC_MAC_ENABLED  - Enable the AES CBC_MAC mode using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CBC_MAC_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_AES_CBC_MAC_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_AES_CMAC_ENABLED  - Enable the AES CMAC mode using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CMAC_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_AES_CMAC_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_AES_CCM_ENABLED  - Enable the AES CCM mode using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CCM_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_AES_CCM_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_AES_CCM_STAR_ENABLED  - Enable the AES CCM* mode using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CCM_STAR_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_AES_CCM_STAR_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_CHACHA_POLY_ENABLED  - Enable the CHACHA-POLY mode using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_CHACHA_POLY_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_CHACHA_POLY_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R1_ENABLED  - Enable the secp160r1 elliptic curve support using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R1_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R2_ENABLED  - Enable the secp160r2 elliptic curve support using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R2_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R2_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_ECC_SECP192R1_ENABLED  - Enable the secp192r1 elliptic curve support using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP192R1_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP192R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_ECC_SECP224R1_ENABLED  - Enable the secp224r1 elliptic curve support using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP224R1_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP224R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_ECC_SECP256R1_ENABLED  - Enable the secp256r1 elliptic curve support using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP256R1_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP256R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_ECC_SECP384R1_ENABLED  - Enable the secp384r1 elliptic curve support using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP384R1_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP384R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_ECC_SECP521R1_ENABLED  - Enable the secp521r1 elliptic curve support using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP521R1_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP521R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_ECC_SECP160K1_ENABLED  - Enable the secp160k1 elliptic curve support using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP160K1_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160K1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_ECC_SECP192K1_ENABLED  - Enable the secp192k1 elliptic curve support using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP192K1_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP192K1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_ECC_SECP224K1_ENABLED  - Enable the secp224k1 elliptic curve support using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP224K1_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP224K1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_ECC_SECP256K1_ENABLED  - Enable the secp256k1 elliptic curve support using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP256K1_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP256K1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_ECC_CURVE25519_ENABLED  - Enable the Curve25519 curve support using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_CURVE25519_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_ECC_CURVE25519_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_ECC_ED25519_ENABLED  - Enable the Ed25519 curve support using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_ED25519_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_ECC_ED25519_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_HASH_SHA256_ENABLED  - CC310 SHA-256 hash functionality.
+
+
+//  CC310 backend implementation for hardware-accelerated SHA-256.
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_HASH_SHA256_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_HASH_SHA256_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_HASH_SHA512_ENABLED  - CC310 SHA-512 hash functionality
+
+
+//  CC310 backend implementation for SHA-512 (in software).
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_HASH_SHA512_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_HASH_SHA512_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_HMAC_SHA256_ENABLED  - CC310 HMAC using SHA-256
+
+
+//  CC310 backend implementation for HMAC using hardware-accelerated SHA-256.
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_HMAC_SHA256_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_HMAC_SHA256_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_HMAC_SHA512_ENABLED  - CC310 HMAC using SHA-512
+
+
+//  CC310 backend implementation for HMAC using SHA-512 (in software).
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_HMAC_SHA512_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_HMAC_SHA512_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_RNG_ENABLED  - Enable RNG support using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_RNG_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_RNG_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_INTERRUPTS_ENABLED  - Enable Interrupts while support using CC310.
+
+
+//  Select a library version compatible with the configuration. When interrupts are disable, a version named _noint must be used
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_INTERRUPTS_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_INTERRUPTS_ENABLED 1
+#endif
+
+// 
+
+//  NRF_CRYPTO_BACKEND_CIFRA_ENABLED - Enable the Cifra backend.
+//==========================================================
+#ifndef NRF_CRYPTO_BACKEND_CIFRA_ENABLED
+#define NRF_CRYPTO_BACKEND_CIFRA_ENABLED 0
+#endif
+//  NRF_CRYPTO_BACKEND_CIFRA_AES_EAX_ENABLED  - Enable the AES EAX mode using Cifra.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CIFRA_AES_EAX_ENABLED
+#define NRF_CRYPTO_BACKEND_CIFRA_AES_EAX_ENABLED 1
+#endif
+
+// 
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_ENABLED - Enable the mbed TLS backend.
+//==========================================================
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_ENABLED 0
+#endif
+//  NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_ENABLED  - Enable the AES CBC mode mbed TLS.
+
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_AES_CTR_ENABLED  - Enable the AES CTR mode using mbed TLS.
+
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CTR_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CTR_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_AES_CFB_ENABLED  - Enable the AES CFB mode using mbed TLS.
+
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CFB_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CFB_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_AES_ECB_ENABLED  - Enable the AES ECB mode using mbed TLS.
+
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_ECB_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_ECB_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_MAC_ENABLED  - Enable the AES CBC MAC mode using mbed TLS.
+
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_MAC_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_MAC_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_AES_CMAC_ENABLED  - Enable the AES CMAC mode using mbed TLS.
+
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CMAC_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CMAC_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_AES_CCM_ENABLED  - Enable the AES CCM mode using mbed TLS.
+
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CCM_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CCM_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_AES_GCM_ENABLED  - Enable the AES GCM mode using mbed TLS.
+
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_GCM_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_GCM_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192R1_ENABLED  - Enable secp192r1 (NIST 192-bit) curve
+
+
+//  Enable this setting if you need secp192r1 (NIST 192-bit) support using MBEDTLS
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192R1_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224R1_ENABLED  - Enable secp224r1 (NIST 224-bit) curve
+
+
+//  Enable this setting if you need secp224r1 (NIST 224-bit) support using MBEDTLS
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224R1_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256R1_ENABLED  - Enable secp256r1 (NIST 256-bit) curve
+
+
+//  Enable this setting if you need secp256r1 (NIST 256-bit) support using MBEDTLS
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256R1_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP384R1_ENABLED  - Enable secp384r1 (NIST 384-bit) curve
+
+
+//  Enable this setting if you need secp384r1 (NIST 384-bit) support using MBEDTLS
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP384R1_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP384R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP521R1_ENABLED  - Enable secp521r1 (NIST 521-bit) curve
+
+
+//  Enable this setting if you need secp521r1 (NIST 521-bit) support using MBEDTLS
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP521R1_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP521R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192K1_ENABLED  - Enable secp192k1 (Koblitz 192-bit) curve
+
+
+//  Enable this setting if you need secp192k1 (Koblitz 192-bit) support using MBEDTLS
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192K1_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192K1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224K1_ENABLED  - Enable secp224k1 (Koblitz 224-bit) curve
+
+
+//  Enable this setting if you need secp224k1 (Koblitz 224-bit) support using MBEDTLS
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224K1_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224K1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256K1_ENABLED  - Enable secp256k1 (Koblitz 256-bit) curve
+
+
+//  Enable this setting if you need secp256k1 (Koblitz 256-bit) support using MBEDTLS
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256K1_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256K1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP256R1_ENABLED  - Enable bp256r1 (Brainpool 256-bit) curve
+
+
+//  Enable this setting if you need bp256r1 (Brainpool 256-bit) support using MBEDTLS
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP256R1_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP256R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP384R1_ENABLED  - Enable bp384r1 (Brainpool 384-bit) curve
+
+
+//  Enable this setting if you need bp384r1 (Brainpool 384-bit) support using MBEDTLS
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP384R1_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP384R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP512R1_ENABLED  - Enable bp512r1 (Brainpool 512-bit) curve
+
+
+//  Enable this setting if you need bp512r1 (Brainpool 512-bit) support using MBEDTLS
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP512R1_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP512R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_CURVE25519_ENABLED  - Enable Curve25519 curve
+
+
+//  Enable this setting if you need Curve25519 support using MBEDTLS
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_CURVE25519_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_CURVE25519_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA256_ENABLED  - Enable mbed TLS SHA-256 hash functionality.
+
+
+//  mbed TLS backend implementation for SHA-256.
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA256_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA256_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA512_ENABLED  - Enable mbed TLS SHA-512 hash functionality.
+
+
+//  mbed TLS backend implementation for SHA-512.
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA512_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA512_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA256_ENABLED  - Enable mbed TLS HMAC using SHA-256.
+
+
+//  mbed TLS backend implementation for HMAC using SHA-256.
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA256_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA256_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA512_ENABLED  - Enable mbed TLS HMAC using SHA-512.
+
+
+//  mbed TLS backend implementation for HMAC using SHA-512.
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA512_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA512_ENABLED 1
+#endif
+
+// 
+
+//  NRF_CRYPTO_BACKEND_MICRO_ECC_ENABLED - Enable the micro-ecc backend.
+//==========================================================
+#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ENABLED
+#define NRF_CRYPTO_BACKEND_MICRO_ECC_ENABLED 0
+#endif
+//  NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP192R1_ENABLED  - Enable secp192r1 (NIST 192-bit) curve
+
+
+//  Enable this setting if you need secp192r1 (NIST 192-bit) support using micro-ecc
+
+#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP192R1_ENABLED
+#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP192R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP224R1_ENABLED  - Enable secp224r1 (NIST 224-bit) curve
+
+
+//  Enable this setting if you need secp224r1 (NIST 224-bit) support using micro-ecc
+
+#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP224R1_ENABLED
+#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP224R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256R1_ENABLED  - Enable secp256r1 (NIST 256-bit) curve
+
+
+//  Enable this setting if you need secp256r1 (NIST 256-bit) support using micro-ecc
+
+#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256R1_ENABLED
+#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256K1_ENABLED  - Enable secp256k1 (Koblitz 256-bit) curve
+
+
+//  Enable this setting if you need secp256k1 (Koblitz 256-bit) support using micro-ecc
+
+#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256K1_ENABLED
+#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256K1_ENABLED 1
+#endif
+
+// 
+
+//  NRF_CRYPTO_BACKEND_NRF_HW_RNG_ENABLED - Enable the nRF HW RNG backend.
+
+//  The nRF HW backend provide access to RNG peripheral in nRF5x devices.
+//==========================================================
+#ifndef NRF_CRYPTO_BACKEND_NRF_HW_RNG_ENABLED
+#define NRF_CRYPTO_BACKEND_NRF_HW_RNG_ENABLED 0
+#endif
+//  NRF_CRYPTO_BACKEND_NRF_HW_RNG_MBEDTLS_CTR_DRBG_ENABLED  - Enable mbed TLS CTR-DRBG algorithm.
+
+
+//  Enable mbed TLS CTR-DRBG standardized by NIST (NIST SP 800-90A Rev. 1). The nRF HW RNG is used as an entropy source for seeding.
+
+#ifndef NRF_CRYPTO_BACKEND_NRF_HW_RNG_MBEDTLS_CTR_DRBG_ENABLED
+#define NRF_CRYPTO_BACKEND_NRF_HW_RNG_MBEDTLS_CTR_DRBG_ENABLED 1
+#endif
+
+// 
+
+//  NRF_CRYPTO_BACKEND_NRF_SW_ENABLED - Enable the legacy nRFx sw for crypto.
+
+//  The nRF SW cryptography backend (only used in bootloader context).
+//==========================================================
+#ifndef NRF_CRYPTO_BACKEND_NRF_SW_ENABLED
+#define NRF_CRYPTO_BACKEND_NRF_SW_ENABLED 0
+#endif
+//  NRF_CRYPTO_BACKEND_NRF_SW_HASH_SHA256_ENABLED  - nRF SW hash backend support for SHA-256
+
+
+//  The nRF SW backend provide access to nRF SDK legacy hash implementation of SHA-256.
+
+#ifndef NRF_CRYPTO_BACKEND_NRF_SW_HASH_SHA256_ENABLED
+#define NRF_CRYPTO_BACKEND_NRF_SW_HASH_SHA256_ENABLED 1
+#endif
+
+// 
+
+//  NRF_CRYPTO_BACKEND_OBERON_ENABLED - Enable the Oberon backend
+
+//  The Oberon backend
+//==========================================================
+#ifndef NRF_CRYPTO_BACKEND_OBERON_ENABLED
+#define NRF_CRYPTO_BACKEND_OBERON_ENABLED 0
+#endif
+//  NRF_CRYPTO_BACKEND_OBERON_CHACHA_POLY_ENABLED  - Enable the CHACHA-POLY mode using Oberon.
+
+
+#ifndef NRF_CRYPTO_BACKEND_OBERON_CHACHA_POLY_ENABLED
+#define NRF_CRYPTO_BACKEND_OBERON_CHACHA_POLY_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_OBERON_ECC_SECP256R1_ENABLED  - Enable secp256r1 curve
+
+
+//  Enable this setting if you need secp256r1 curve support using Oberon library
+
+#ifndef NRF_CRYPTO_BACKEND_OBERON_ECC_SECP256R1_ENABLED
+#define NRF_CRYPTO_BACKEND_OBERON_ECC_SECP256R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_OBERON_ECC_CURVE25519_ENABLED  - Enable Curve25519 ECDH
+
+
+//  Enable this setting if you need Curve25519 ECDH support using Oberon library
+
+#ifndef NRF_CRYPTO_BACKEND_OBERON_ECC_CURVE25519_ENABLED
+#define NRF_CRYPTO_BACKEND_OBERON_ECC_CURVE25519_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_OBERON_ECC_ED25519_ENABLED  - Enable Ed25519 signature scheme
+
+
+//  Enable this setting if you need Ed25519 support using Oberon library
+
+#ifndef NRF_CRYPTO_BACKEND_OBERON_ECC_ED25519_ENABLED
+#define NRF_CRYPTO_BACKEND_OBERON_ECC_ED25519_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_OBERON_HASH_SHA256_ENABLED  - Oberon SHA-256 hash functionality
+
+
+//  Oberon backend implementation for SHA-256.
+
+#ifndef NRF_CRYPTO_BACKEND_OBERON_HASH_SHA256_ENABLED
+#define NRF_CRYPTO_BACKEND_OBERON_HASH_SHA256_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_OBERON_HASH_SHA512_ENABLED  - Oberon SHA-512 hash functionality
+
+
+//  Oberon backend implementation for SHA-512.
+
+#ifndef NRF_CRYPTO_BACKEND_OBERON_HASH_SHA512_ENABLED
+#define NRF_CRYPTO_BACKEND_OBERON_HASH_SHA512_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA256_ENABLED  - Oberon HMAC using SHA-256
+
+
+//  Oberon backend implementation for HMAC using SHA-256.
+
+#ifndef NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA256_ENABLED
+#define NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA256_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA512_ENABLED  - Oberon HMAC using SHA-512
+
+
+//  Oberon backend implementation for HMAC using SHA-512.
+
+#ifndef NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA512_ENABLED
+#define NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA512_ENABLED 1
+#endif
+
+// 
+
+//  NRF_CRYPTO_BACKEND_OPTIGA_ENABLED - Enable the nrf_crypto Optiga Trust X backend.
+
+//  Enables the nrf_crypto backend for Optiga Trust X devices.
+//==========================================================
+#ifndef NRF_CRYPTO_BACKEND_OPTIGA_ENABLED
+#define NRF_CRYPTO_BACKEND_OPTIGA_ENABLED 0
+#endif
+//  NRF_CRYPTO_BACKEND_OPTIGA_RNG_ENABLED  - Optiga backend support for RNG
+
+
+//  The Optiga backend provide external chip RNG.
+
+#ifndef NRF_CRYPTO_BACKEND_OPTIGA_RNG_ENABLED
+#define NRF_CRYPTO_BACKEND_OPTIGA_RNG_ENABLED 0
+#endif
+
+//  NRF_CRYPTO_BACKEND_OPTIGA_ECC_SECP256R1_ENABLED  - Optiga backend support for ECC secp256r1
+
+
+//  The Optiga backend provide external chip ECC using secp256r1.
+
+#ifndef NRF_CRYPTO_BACKEND_OPTIGA_ECC_SECP256R1_ENABLED
+#define NRF_CRYPTO_BACKEND_OPTIGA_ECC_SECP256R1_ENABLED 1
+#endif
+
+// 
+
+//  NRF_CRYPTO_CURVE25519_BIG_ENDIAN_ENABLED  - Big-endian byte order in raw Curve25519 data
+
+
+//  Enable big-endian byte order in Curve25519 API, if set to 1. Use little-endian, if set to 0.
+
+#ifndef NRF_CRYPTO_CURVE25519_BIG_ENDIAN_ENABLED
+#define NRF_CRYPTO_CURVE25519_BIG_ENDIAN_ENABLED 0
+#endif
+
+// 
+
+// 
+//==========================================================
+
+//  nRF_DFU
+
+//==========================================================
+//  ble_dfu - Device Firmware Update
+
+//==========================================================
+//  BLE_DFU_ENABLED  - Enable DFU Service.
+
+
+#ifndef BLE_DFU_ENABLED
+#define BLE_DFU_ENABLED 0
+#endif
+
+//  NRF_DFU_BLE_BUTTONLESS_SUPPORTS_BONDS  - Buttonless DFU supports bonds.
+
+
+#ifndef NRF_DFU_BLE_BUTTONLESS_SUPPORTS_BONDS
+#define NRF_DFU_BLE_BUTTONLESS_SUPPORTS_BONDS 0
+#endif
+
+// 
+//==========================================================
+
+// 
+//==========================================================
+
+//  nRF_Drivers
+
+//==========================================================
+//  COMP_ENABLED - nrf_drv_comp - COMP peripheral driver - legacy layer
+//==========================================================
+#ifndef COMP_ENABLED
+#define COMP_ENABLED 0
+#endif
+//  COMP_CONFIG_REF  - Reference voltage
+
+// <0=> Internal 1.2V
+// <1=> Internal 1.8V
+// <2=> Internal 2.4V
+// <4=> VDD
+// <7=> ARef
+
+#ifndef COMP_CONFIG_REF
+#define COMP_CONFIG_REF 1
+#endif
+
+//  COMP_CONFIG_MAIN_MODE  - Main mode
+
+// <0=> Single ended
+// <1=> Differential
+
+#ifndef COMP_CONFIG_MAIN_MODE
+#define COMP_CONFIG_MAIN_MODE 0
+#endif
+
+//  COMP_CONFIG_SPEED_MODE  - Speed mode
+
+// <0=> Low power
+// <1=> Normal
+// <2=> High speed
+
+#ifndef COMP_CONFIG_SPEED_MODE
+#define COMP_CONFIG_SPEED_MODE 2
+#endif
+
+//  COMP_CONFIG_HYST  - Hystheresis
+
+// <0=> No
+// <1=> 50mV
+
+#ifndef COMP_CONFIG_HYST
+#define COMP_CONFIG_HYST 0
+#endif
+
+//  COMP_CONFIG_ISOURCE  - Current Source
+
+// <0=> Off
+// <1=> 2.5 uA
+// <2=> 5 uA
+// <3=> 10 uA
+
+#ifndef COMP_CONFIG_ISOURCE
+#define COMP_CONFIG_ISOURCE 0
+#endif
+
+//  COMP_CONFIG_INPUT  - Analog input
+
+// <0=> 0
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef COMP_CONFIG_INPUT
+#define COMP_CONFIG_INPUT 0
+#endif
+
+//  COMP_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef COMP_CONFIG_IRQ_PRIORITY
+#define COMP_CONFIG_IRQ_PRIORITY 6
+#endif
+
+// 
+
+//  EGU_ENABLED  - nrf_drv_swi - SWI(EGU) peripheral driver - legacy layer
+
+
+#ifndef EGU_ENABLED
+#define EGU_ENABLED 0
+#endif
+
+//  GPIOTE_ENABLED - nrf_drv_gpiote - GPIOTE peripheral driver - legacy layer
+//==========================================================
+#ifndef GPIOTE_ENABLED
+#define GPIOTE_ENABLED 0
+#endif
+//  GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins
+#ifndef GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS
+#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1
+#endif
+
+//  GPIOTE_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef GPIOTE_CONFIG_IRQ_PRIORITY
+#define GPIOTE_CONFIG_IRQ_PRIORITY 6
+#endif
+
+// 
+
+//  I2S_ENABLED - nrf_drv_i2s - I2S peripheral driver - legacy layer
+//==========================================================
+#ifndef I2S_ENABLED
+#define I2S_ENABLED 0
+#endif
+//  I2S_CONFIG_SCK_PIN - SCK pin  <0-31>
+
+
+#ifndef I2S_CONFIG_SCK_PIN
+#define I2S_CONFIG_SCK_PIN 31
+#endif
+
+//  I2S_CONFIG_LRCK_PIN - LRCK pin  <1-31>
+
+
+#ifndef I2S_CONFIG_LRCK_PIN
+#define I2S_CONFIG_LRCK_PIN 30
+#endif
+
+//  I2S_CONFIG_MCK_PIN - MCK pin
+#ifndef I2S_CONFIG_MCK_PIN
+#define I2S_CONFIG_MCK_PIN 255
+#endif
+
+//  I2S_CONFIG_SDOUT_PIN - SDOUT pin  <0-31>
+
+
+#ifndef I2S_CONFIG_SDOUT_PIN
+#define I2S_CONFIG_SDOUT_PIN 29
+#endif
+
+//  I2S_CONFIG_SDIN_PIN - SDIN pin  <0-31>
+
+
+#ifndef I2S_CONFIG_SDIN_PIN
+#define I2S_CONFIG_SDIN_PIN 28
+#endif
+
+//  I2S_CONFIG_MASTER  - Mode
+
+// <0=> Master
+// <1=> Slave
+
+#ifndef I2S_CONFIG_MASTER
+#define I2S_CONFIG_MASTER 0
+#endif
+
+//  I2S_CONFIG_FORMAT  - Format
+
+// <0=> I2S
+// <1=> Aligned
+
+#ifndef I2S_CONFIG_FORMAT
+#define I2S_CONFIG_FORMAT 0
+#endif
+
+//  I2S_CONFIG_ALIGN  - Alignment
+
+// <0=> Left
+// <1=> Right
+
+#ifndef I2S_CONFIG_ALIGN
+#define I2S_CONFIG_ALIGN 0
+#endif
+
+//  I2S_CONFIG_SWIDTH  - Sample width (bits)
+
+// <0=> 8
+// <1=> 16
+// <2=> 24
+
+#ifndef I2S_CONFIG_SWIDTH
+#define I2S_CONFIG_SWIDTH 1
+#endif
+
+//  I2S_CONFIG_CHANNELS  - Channels
+
+// <0=> Stereo
+// <1=> Left
+// <2=> Right
+
+#ifndef I2S_CONFIG_CHANNELS
+#define I2S_CONFIG_CHANNELS 1
+#endif
+
+//  I2S_CONFIG_MCK_SETUP  - MCK behavior
+
+// <0=> Disabled
+// <2147483648=> 32MHz/2
+// <1342177280=> 32MHz/3
+// <1073741824=> 32MHz/4
+// <805306368=> 32MHz/5
+// <671088640=> 32MHz/6
+// <536870912=> 32MHz/8
+// <402653184=> 32MHz/10
+// <369098752=> 32MHz/11
+// <285212672=> 32MHz/15
+// <268435456=> 32MHz/16
+// <201326592=> 32MHz/21
+// <184549376=> 32MHz/23
+// <142606336=> 32MHz/30
+// <138412032=> 32MHz/31
+// <134217728=> 32MHz/32
+// <100663296=> 32MHz/42
+// <68157440=> 32MHz/63
+// <34340864=> 32MHz/125
+
+#ifndef I2S_CONFIG_MCK_SETUP
+#define I2S_CONFIG_MCK_SETUP 536870912
+#endif
+
+//  I2S_CONFIG_RATIO  - MCK/LRCK ratio
+
+// <0=> 32x
+// <1=> 48x
+// <2=> 64x
+// <3=> 96x
+// <4=> 128x
+// <5=> 192x
+// <6=> 256x
+// <7=> 384x
+// <8=> 512x
+
+#ifndef I2S_CONFIG_RATIO
+#define I2S_CONFIG_RATIO 2000
+#endif
+
+//  I2S_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef I2S_CONFIG_IRQ_PRIORITY
+#define I2S_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  I2S_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef I2S_CONFIG_LOG_ENABLED
+#define I2S_CONFIG_LOG_ENABLED 0
+#endif
+//  I2S_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef I2S_CONFIG_LOG_LEVEL
+#define I2S_CONFIG_LOG_LEVEL 3
+#endif
+
+//  I2S_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef I2S_CONFIG_INFO_COLOR
+#define I2S_CONFIG_INFO_COLOR 0
+#endif
+
+//  I2S_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef I2S_CONFIG_DEBUG_COLOR
+#define I2S_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  LPCOMP_ENABLED - nrf_drv_lpcomp - LPCOMP peripheral driver - legacy layer
+//==========================================================
+#ifndef LPCOMP_ENABLED
+#define LPCOMP_ENABLED 0
+#endif
+//  LPCOMP_CONFIG_REFERENCE  - Reference voltage
+
+// <0=> Supply 1/8
+// <1=> Supply 2/8
+// <2=> Supply 3/8
+// <3=> Supply 4/8
+// <4=> Supply 5/8
+// <5=> Supply 6/8
+// <6=> Supply 7/8
+// <8=> Supply 1/16 (nRF52)
+// <9=> Supply 3/16 (nRF52)
+// <10=> Supply 5/16 (nRF52)
+// <11=> Supply 7/16 (nRF52)
+// <12=> Supply 9/16 (nRF52)
+// <13=> Supply 11/16 (nRF52)
+// <14=> Supply 13/16 (nRF52)
+// <15=> Supply 15/16 (nRF52)
+// <7=> External Ref 0
+// <65543=> External Ref 1
+
+#ifndef LPCOMP_CONFIG_REFERENCE
+#define LPCOMP_CONFIG_REFERENCE 3
+#endif
+
+//  LPCOMP_CONFIG_DETECTION  - Detection
+
+// <0=> Crossing
+// <1=> Up
+// <2=> Down
+
+#ifndef LPCOMP_CONFIG_DETECTION
+#define LPCOMP_CONFIG_DETECTION 2
+#endif
+
+//  LPCOMP_CONFIG_INPUT  - Analog input
+
+// <0=> 0
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef LPCOMP_CONFIG_INPUT
+#define LPCOMP_CONFIG_INPUT 0
+#endif
+
+//  LPCOMP_CONFIG_HYST  - Hysteresis
+
+
+#ifndef LPCOMP_CONFIG_HYST
+#define LPCOMP_CONFIG_HYST 0
+#endif
+
+//  LPCOMP_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef LPCOMP_CONFIG_IRQ_PRIORITY
+#define LPCOMP_CONFIG_IRQ_PRIORITY 6
+#endif
+
+// 
+
+//  NRFX_CLOCK_ENABLED - nrfx_clock - CLOCK peripheral driver
+//==========================================================
+#ifndef NRFX_CLOCK_ENABLED
+#define NRFX_CLOCK_ENABLED 0
+#endif
+//  NRFX_CLOCK_CONFIG_LF_SRC  - LF Clock Source
+
+// <0=> RC
+// <1=> XTAL
+// <2=> Synth
+// <131073=> External Low Swing
+// <196609=> External Full Swing
+
+#ifndef NRFX_CLOCK_CONFIG_LF_SRC
+#define NRFX_CLOCK_CONFIG_LF_SRC 1
+#endif
+
+//  NRFX_CLOCK_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_CLOCK_CONFIG_IRQ_PRIORITY
+#define NRFX_CLOCK_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_CLOCK_CONFIG_LOG_ENABLED
+#define NRFX_CLOCK_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_CLOCK_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_CLOCK_CONFIG_LOG_LEVEL
+#define NRFX_CLOCK_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_CLOCK_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_CLOCK_CONFIG_INFO_COLOR
+#define NRFX_CLOCK_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_CLOCK_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_CLOCK_CONFIG_DEBUG_COLOR
+#define NRFX_CLOCK_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_COMP_ENABLED - nrfx_comp - COMP peripheral driver
+//==========================================================
+#ifndef NRFX_COMP_ENABLED
+#define NRFX_COMP_ENABLED 0
+#endif
+//  NRFX_COMP_CONFIG_REF  - Reference voltage
+
+// <0=> Internal 1.2V
+// <1=> Internal 1.8V
+// <2=> Internal 2.4V
+// <4=> VDD
+// <7=> ARef
+
+#ifndef NRFX_COMP_CONFIG_REF
+#define NRFX_COMP_CONFIG_REF 1
+#endif
+
+//  NRFX_COMP_CONFIG_MAIN_MODE  - Main mode
+
+// <0=> Single ended
+// <1=> Differential
+
+#ifndef NRFX_COMP_CONFIG_MAIN_MODE
+#define NRFX_COMP_CONFIG_MAIN_MODE 0
+#endif
+
+//  NRFX_COMP_CONFIG_SPEED_MODE  - Speed mode
+
+// <0=> Low power
+// <1=> Normal
+// <2=> High speed
+
+#ifndef NRFX_COMP_CONFIG_SPEED_MODE
+#define NRFX_COMP_CONFIG_SPEED_MODE 2
+#endif
+
+//  NRFX_COMP_CONFIG_HYST  - Hystheresis
+
+// <0=> No
+// <1=> 50mV
+
+#ifndef NRFX_COMP_CONFIG_HYST
+#define NRFX_COMP_CONFIG_HYST 0
+#endif
+
+//  NRFX_COMP_CONFIG_ISOURCE  - Current Source
+
+// <0=> Off
+// <1=> 2.5 uA
+// <2=> 5 uA
+// <3=> 10 uA
+
+#ifndef NRFX_COMP_CONFIG_ISOURCE
+#define NRFX_COMP_CONFIG_ISOURCE 0
+#endif
+
+//  NRFX_COMP_CONFIG_INPUT  - Analog input
+
+// <0=> 0
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_COMP_CONFIG_INPUT
+#define NRFX_COMP_CONFIG_INPUT 0
+#endif
+
+//  NRFX_COMP_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_COMP_CONFIG_IRQ_PRIORITY
+#define NRFX_COMP_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_COMP_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_COMP_CONFIG_LOG_ENABLED
+#define NRFX_COMP_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_COMP_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_COMP_CONFIG_LOG_LEVEL
+#define NRFX_COMP_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_COMP_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_COMP_CONFIG_INFO_COLOR
+#define NRFX_COMP_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_COMP_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_COMP_CONFIG_DEBUG_COLOR
+#define NRFX_COMP_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_GPIOTE_ENABLED - nrfx_gpiote - GPIOTE peripheral driver
+//==========================================================
+#ifndef NRFX_GPIOTE_ENABLED
+#define NRFX_GPIOTE_ENABLED 0
+#endif
+//  NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins
+#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS
+#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1
+#endif
+
+//  NRFX_GPIOTE_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_GPIOTE_CONFIG_IRQ_PRIORITY
+#define NRFX_GPIOTE_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED
+#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_GPIOTE_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL
+#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_GPIOTE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_GPIOTE_CONFIG_INFO_COLOR
+#define NRFX_GPIOTE_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_GPIOTE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_GPIOTE_CONFIG_DEBUG_COLOR
+#define NRFX_GPIOTE_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_I2S_ENABLED - nrfx_i2s - I2S peripheral driver
+//==========================================================
+#ifndef NRFX_I2S_ENABLED
+#define NRFX_I2S_ENABLED 0
+#endif
+//  NRFX_I2S_CONFIG_SCK_PIN - SCK pin  <0-31>
+
+
+#ifndef NRFX_I2S_CONFIG_SCK_PIN
+#define NRFX_I2S_CONFIG_SCK_PIN 31
+#endif
+
+//  NRFX_I2S_CONFIG_LRCK_PIN - LRCK pin  <1-31>
+
+
+#ifndef NRFX_I2S_CONFIG_LRCK_PIN
+#define NRFX_I2S_CONFIG_LRCK_PIN 30
+#endif
+
+//  NRFX_I2S_CONFIG_MCK_PIN - MCK pin
+#ifndef NRFX_I2S_CONFIG_MCK_PIN
+#define NRFX_I2S_CONFIG_MCK_PIN 255
+#endif
+
+//  NRFX_I2S_CONFIG_SDOUT_PIN - SDOUT pin  <0-31>
+
+
+#ifndef NRFX_I2S_CONFIG_SDOUT_PIN
+#define NRFX_I2S_CONFIG_SDOUT_PIN 29
+#endif
+
+//  NRFX_I2S_CONFIG_SDIN_PIN - SDIN pin  <0-31>
+
+
+#ifndef NRFX_I2S_CONFIG_SDIN_PIN
+#define NRFX_I2S_CONFIG_SDIN_PIN 28
+#endif
+
+//  NRFX_I2S_CONFIG_MASTER  - Mode
+
+// <0=> Master
+// <1=> Slave
+
+#ifndef NRFX_I2S_CONFIG_MASTER
+#define NRFX_I2S_CONFIG_MASTER 0
+#endif
+
+//  NRFX_I2S_CONFIG_FORMAT  - Format
+
+// <0=> I2S
+// <1=> Aligned
+
+#ifndef NRFX_I2S_CONFIG_FORMAT
+#define NRFX_I2S_CONFIG_FORMAT 0
+#endif
+
+//  NRFX_I2S_CONFIG_ALIGN  - Alignment
+
+// <0=> Left
+// <1=> Right
+
+#ifndef NRFX_I2S_CONFIG_ALIGN
+#define NRFX_I2S_CONFIG_ALIGN 0
+#endif
+
+//  NRFX_I2S_CONFIG_SWIDTH  - Sample width (bits)
+
+// <0=> 8
+// <1=> 16
+// <2=> 24
+
+#ifndef NRFX_I2S_CONFIG_SWIDTH
+#define NRFX_I2S_CONFIG_SWIDTH 1
+#endif
+
+//  NRFX_I2S_CONFIG_CHANNELS  - Channels
+
+// <0=> Stereo
+// <1=> Left
+// <2=> Right
+
+#ifndef NRFX_I2S_CONFIG_CHANNELS
+#define NRFX_I2S_CONFIG_CHANNELS 1
+#endif
+
+//  NRFX_I2S_CONFIG_MCK_SETUP  - MCK behavior
+
+// <0=> Disabled
+// <2147483648=> 32MHz/2
+// <1342177280=> 32MHz/3
+// <1073741824=> 32MHz/4
+// <805306368=> 32MHz/5
+// <671088640=> 32MHz/6
+// <536870912=> 32MHz/8
+// <402653184=> 32MHz/10
+// <369098752=> 32MHz/11
+// <285212672=> 32MHz/15
+// <268435456=> 32MHz/16
+// <201326592=> 32MHz/21
+// <184549376=> 32MHz/23
+// <142606336=> 32MHz/30
+// <138412032=> 32MHz/31
+// <134217728=> 32MHz/32
+// <100663296=> 32MHz/42
+// <68157440=> 32MHz/63
+// <34340864=> 32MHz/125
+
+#ifndef NRFX_I2S_CONFIG_MCK_SETUP
+#define NRFX_I2S_CONFIG_MCK_SETUP 536870912
+#endif
+
+//  NRFX_I2S_CONFIG_RATIO  - MCK/LRCK ratio
+
+// <0=> 32x
+// <1=> 48x
+// <2=> 64x
+// <3=> 96x
+// <4=> 128x
+// <5=> 192x
+// <6=> 256x
+// <7=> 384x
+// <8=> 512x
+
+#ifndef NRFX_I2S_CONFIG_RATIO
+#define NRFX_I2S_CONFIG_RATIO 2000
+#endif
+
+//  NRFX_I2S_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_I2S_CONFIG_IRQ_PRIORITY
+#define NRFX_I2S_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_I2S_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_I2S_CONFIG_LOG_ENABLED
+#define NRFX_I2S_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_I2S_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_I2S_CONFIG_LOG_LEVEL
+#define NRFX_I2S_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_I2S_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_I2S_CONFIG_INFO_COLOR
+#define NRFX_I2S_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_I2S_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_I2S_CONFIG_DEBUG_COLOR
+#define NRFX_I2S_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_LPCOMP_ENABLED - nrfx_lpcomp - LPCOMP peripheral driver
+//==========================================================
+#ifndef NRFX_LPCOMP_ENABLED
+#define NRFX_LPCOMP_ENABLED 0
+#endif
+//  NRFX_LPCOMP_CONFIG_REFERENCE  - Reference voltage
+
+// <0=> Supply 1/8
+// <1=> Supply 2/8
+// <2=> Supply 3/8
+// <3=> Supply 4/8
+// <4=> Supply 5/8
+// <5=> Supply 6/8
+// <6=> Supply 7/8
+// <8=> Supply 1/16 (nRF52)
+// <9=> Supply 3/16 (nRF52)
+// <10=> Supply 5/16 (nRF52)
+// <11=> Supply 7/16 (nRF52)
+// <12=> Supply 9/16 (nRF52)
+// <13=> Supply 11/16 (nRF52)
+// <14=> Supply 13/16 (nRF52)
+// <15=> Supply 15/16 (nRF52)
+// <7=> External Ref 0
+// <65543=> External Ref 1
+
+#ifndef NRFX_LPCOMP_CONFIG_REFERENCE
+#define NRFX_LPCOMP_CONFIG_REFERENCE 3
+#endif
+
+//  NRFX_LPCOMP_CONFIG_DETECTION  - Detection
+
+// <0=> Crossing
+// <1=> Up
+// <2=> Down
+
+#ifndef NRFX_LPCOMP_CONFIG_DETECTION
+#define NRFX_LPCOMP_CONFIG_DETECTION 2
+#endif
+
+//  NRFX_LPCOMP_CONFIG_INPUT  - Analog input
+
+// <0=> 0
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_LPCOMP_CONFIG_INPUT
+#define NRFX_LPCOMP_CONFIG_INPUT 0
+#endif
+
+//  NRFX_LPCOMP_CONFIG_HYST  - Hysteresis
+
+
+#ifndef NRFX_LPCOMP_CONFIG_HYST
+#define NRFX_LPCOMP_CONFIG_HYST 0
+#endif
+
+//  NRFX_LPCOMP_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_LPCOMP_CONFIG_IRQ_PRIORITY
+#define NRFX_LPCOMP_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_LPCOMP_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED
+#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_LPCOMP_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL
+#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_LPCOMP_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_LPCOMP_CONFIG_INFO_COLOR
+#define NRFX_LPCOMP_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_LPCOMP_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_LPCOMP_CONFIG_DEBUG_COLOR
+#define NRFX_LPCOMP_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_NFCT_ENABLED - nrfx_nfct - NFCT peripheral driver
+//==========================================================
+#ifndef NRFX_NFCT_ENABLED
+#define NRFX_NFCT_ENABLED 0
+#endif
+//  NRFX_NFCT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_NFCT_CONFIG_IRQ_PRIORITY
+#define NRFX_NFCT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_NFCT_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_NFCT_CONFIG_LOG_ENABLED
+#define NRFX_NFCT_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_NFCT_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_NFCT_CONFIG_LOG_LEVEL
+#define NRFX_NFCT_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_NFCT_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_NFCT_CONFIG_INFO_COLOR
+#define NRFX_NFCT_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_NFCT_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_NFCT_CONFIG_DEBUG_COLOR
+#define NRFX_NFCT_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_PDM_ENABLED - nrfx_pdm - PDM peripheral driver
+//==========================================================
+#ifndef NRFX_PDM_ENABLED
+#define NRFX_PDM_ENABLED 0
+#endif
+//  NRFX_PDM_CONFIG_MODE  - Mode
+
+// <0=> Stereo
+// <1=> Mono
+
+#ifndef NRFX_PDM_CONFIG_MODE
+#define NRFX_PDM_CONFIG_MODE 1
+#endif
+
+//  NRFX_PDM_CONFIG_EDGE  - Edge
+
+// <0=> Left falling
+// <1=> Left rising
+
+#ifndef NRFX_PDM_CONFIG_EDGE
+#define NRFX_PDM_CONFIG_EDGE 0
+#endif
+
+//  NRFX_PDM_CONFIG_CLOCK_FREQ  - Clock frequency
+
+// <134217728=> 1000k
+// <138412032=> 1032k (default)
+// <142606336=> 1067k
+
+#ifndef NRFX_PDM_CONFIG_CLOCK_FREQ
+#define NRFX_PDM_CONFIG_CLOCK_FREQ 138412032
+#endif
+
+//  NRFX_PDM_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_PDM_CONFIG_IRQ_PRIORITY
+#define NRFX_PDM_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_PDM_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_PDM_CONFIG_LOG_ENABLED
+#define NRFX_PDM_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_PDM_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_PDM_CONFIG_LOG_LEVEL
+#define NRFX_PDM_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_PDM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_PDM_CONFIG_INFO_COLOR
+#define NRFX_PDM_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_PDM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_PDM_CONFIG_DEBUG_COLOR
+#define NRFX_PDM_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_POWER_ENABLED - nrfx_power - POWER peripheral driver
+//==========================================================
+#ifndef NRFX_POWER_ENABLED
+#define NRFX_POWER_ENABLED 0
+#endif
+//  NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#endif
+
+//  NRFX_POWER_CONFIG_DEFAULT_DCDCEN  - The default configuration of main DCDC regulator
+
+
+//  This settings means only that components for DCDC regulator are installed and it can be enabled.
+
+#ifndef NRFX_POWER_CONFIG_DEFAULT_DCDCEN
+#define NRFX_POWER_CONFIG_DEFAULT_DCDCEN 0
+#endif
+
+//  NRFX_POWER_CONFIG_DEFAULT_DCDCENHV  - The default configuration of High Voltage DCDC regulator
+
+
+//  This settings means only that components for DCDC regulator are installed and it can be enabled.
+
+#ifndef NRFX_POWER_CONFIG_DEFAULT_DCDCENHV
+#define NRFX_POWER_CONFIG_DEFAULT_DCDCENHV 0
+#endif
+
+// 
+
+//  NRFX_PPI_ENABLED - nrfx_ppi - PPI peripheral allocator
+//==========================================================
+#ifndef NRFX_PPI_ENABLED
+#define NRFX_PPI_ENABLED 0
+#endif
+//  NRFX_PPI_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_PPI_CONFIG_LOG_ENABLED
+#define NRFX_PPI_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_PPI_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_PPI_CONFIG_LOG_LEVEL
+#define NRFX_PPI_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_PPI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_PPI_CONFIG_INFO_COLOR
+#define NRFX_PPI_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_PPI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_PPI_CONFIG_DEBUG_COLOR
+#define NRFX_PPI_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_PWM_ENABLED - nrfx_pwm - PWM peripheral driver
+//==========================================================
+#ifndef NRFX_PWM_ENABLED
+#define NRFX_PWM_ENABLED 0
+#endif
+//  NRFX_PWM0_ENABLED  - Enable PWM0 instance
+
+
+#ifndef NRFX_PWM0_ENABLED
+#define NRFX_PWM0_ENABLED 0
+#endif
+
+//  NRFX_PWM1_ENABLED  - Enable PWM1 instance
+
+
+#ifndef NRFX_PWM1_ENABLED
+#define NRFX_PWM1_ENABLED 0
+#endif
+
+//  NRFX_PWM2_ENABLED  - Enable PWM2 instance
+
+
+#ifndef NRFX_PWM2_ENABLED
+#define NRFX_PWM2_ENABLED 0
+#endif
+
+//  NRFX_PWM3_ENABLED  - Enable PWM3 instance
+
+
+#ifndef NRFX_PWM3_ENABLED
+#define NRFX_PWM3_ENABLED 0
+#endif
+
+//  NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin  <0-31>
+
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN
+#define NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN 31
+#endif
+
+//  NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin  <0-31>
+
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN
+#define NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN 31
+#endif
+
+//  NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin  <0-31>
+
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN
+#define NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN 31
+#endif
+
+//  NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin  <0-31>
+
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN
+#define NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN 31
+#endif
+
+//  NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK  - Base clock
+
+// <0=> 16 MHz
+// <1=> 8 MHz
+// <2=> 4 MHz
+// <3=> 2 MHz
+// <4=> 1 MHz
+// <5=> 500 kHz
+// <6=> 250 kHz
+// <7=> 125 kHz
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK
+#define NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK 4
+#endif
+
+//  NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE  - Count mode
+
+// <0=> Up
+// <1=> Up and Down
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE
+#define NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE 0
+#endif
+
+//  NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE - Top value
+#ifndef NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE
+#define NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE 1000
+#endif
+
+//  NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE  - Load mode
+
+// <0=> Common
+// <1=> Grouped
+// <2=> Individual
+// <3=> Waveform
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE
+#define NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE 0
+#endif
+
+//  NRFX_PWM_DEFAULT_CONFIG_STEP_MODE  - Step mode
+
+// <0=> Auto
+// <1=> Triggered
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_STEP_MODE
+#define NRFX_PWM_DEFAULT_CONFIG_STEP_MODE 0
+#endif
+
+//  NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_PWM_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_PWM_CONFIG_LOG_ENABLED
+#define NRFX_PWM_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_PWM_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_PWM_CONFIG_LOG_LEVEL
+#define NRFX_PWM_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_PWM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_PWM_CONFIG_INFO_COLOR
+#define NRFX_PWM_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_PWM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_PWM_CONFIG_DEBUG_COLOR
+#define NRFX_PWM_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_QDEC_ENABLED - nrfx_qdec - QDEC peripheral driver
+//==========================================================
+#ifndef NRFX_QDEC_ENABLED
+#define NRFX_QDEC_ENABLED 0
+#endif
+//  NRFX_QDEC_CONFIG_REPORTPER  - Report period
+
+// <0=> 10 Samples
+// <1=> 40 Samples
+// <2=> 80 Samples
+// <3=> 120 Samples
+// <4=> 160 Samples
+// <5=> 200 Samples
+// <6=> 240 Samples
+// <7=> 280 Samples
+
+#ifndef NRFX_QDEC_CONFIG_REPORTPER
+#define NRFX_QDEC_CONFIG_REPORTPER 0
+#endif
+
+//  NRFX_QDEC_CONFIG_SAMPLEPER  - Sample period
+
+// <0=> 128 us
+// <1=> 256 us
+// <2=> 512 us
+// <3=> 1024 us
+// <4=> 2048 us
+// <5=> 4096 us
+// <6=> 8192 us
+// <7=> 16384 us
+
+#ifndef NRFX_QDEC_CONFIG_SAMPLEPER
+#define NRFX_QDEC_CONFIG_SAMPLEPER 7
+#endif
+
+//  NRFX_QDEC_CONFIG_PIO_A - A pin  <0-31>
+
+
+#ifndef NRFX_QDEC_CONFIG_PIO_A
+#define NRFX_QDEC_CONFIG_PIO_A 31
+#endif
+
+//  NRFX_QDEC_CONFIG_PIO_B - B pin  <0-31>
+
+
+#ifndef NRFX_QDEC_CONFIG_PIO_B
+#define NRFX_QDEC_CONFIG_PIO_B 31
+#endif
+
+//  NRFX_QDEC_CONFIG_PIO_LED - LED pin  <0-31>
+
+
+#ifndef NRFX_QDEC_CONFIG_PIO_LED
+#define NRFX_QDEC_CONFIG_PIO_LED 31
+#endif
+
+//  NRFX_QDEC_CONFIG_LEDPRE - LED pre
+#ifndef NRFX_QDEC_CONFIG_LEDPRE
+#define NRFX_QDEC_CONFIG_LEDPRE 511
+#endif
+
+//  NRFX_QDEC_CONFIG_LEDPOL  - LED polarity
+
+// <0=> Active low
+// <1=> Active high
+
+#ifndef NRFX_QDEC_CONFIG_LEDPOL
+#define NRFX_QDEC_CONFIG_LEDPOL 1
+#endif
+
+//  NRFX_QDEC_CONFIG_DBFEN  - Debouncing enable
+
+
+#ifndef NRFX_QDEC_CONFIG_DBFEN
+#define NRFX_QDEC_CONFIG_DBFEN 0
+#endif
+
+//  NRFX_QDEC_CONFIG_SAMPLE_INTEN  - Sample ready interrupt enable
+
+
+#ifndef NRFX_QDEC_CONFIG_SAMPLE_INTEN
+#define NRFX_QDEC_CONFIG_SAMPLE_INTEN 0
+#endif
+
+//  NRFX_QDEC_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_QDEC_CONFIG_IRQ_PRIORITY
+#define NRFX_QDEC_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_QDEC_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED
+#define NRFX_QDEC_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_QDEC_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL
+#define NRFX_QDEC_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_QDEC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_QDEC_CONFIG_INFO_COLOR
+#define NRFX_QDEC_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_QDEC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_QDEC_CONFIG_DEBUG_COLOR
+#define NRFX_QDEC_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_QSPI_ENABLED - nrfx_qspi - QSPI peripheral driver
+//==========================================================
+#ifndef NRFX_QSPI_ENABLED
+#define NRFX_QSPI_ENABLED 0
+#endif
+//  NRFX_QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns).  <0-255>
+
+
+#ifndef NRFX_QSPI_CONFIG_SCK_DELAY
+#define NRFX_QSPI_CONFIG_SCK_DELAY 1
+#endif
+
+//  NRFX_QSPI_CONFIG_XIP_OFFSET - Address offset in the external memory for Execute in Place operation.
+#ifndef NRFX_QSPI_CONFIG_XIP_OFFSET
+#define NRFX_QSPI_CONFIG_XIP_OFFSET 0
+#endif
+
+//  NRFX_QSPI_CONFIG_READOC  - Number of data lines and opcode used for reading.
+
+// <0=> FastRead
+// <1=> Read2O
+// <2=> Read2IO
+// <3=> Read4O
+// <4=> Read4IO
+
+#ifndef NRFX_QSPI_CONFIG_READOC
+#define NRFX_QSPI_CONFIG_READOC 0
+#endif
+
+//  NRFX_QSPI_CONFIG_WRITEOC  - Number of data lines and opcode used for writing.
+
+// <0=> PP
+// <1=> PP2O
+// <2=> PP4O
+// <3=> PP4IO
+
+#ifndef NRFX_QSPI_CONFIG_WRITEOC
+#define NRFX_QSPI_CONFIG_WRITEOC 0
+#endif
+
+//  NRFX_QSPI_CONFIG_ADDRMODE  - Addressing mode.
+
+// <0=> 24bit
+// <1=> 32bit
+
+#ifndef NRFX_QSPI_CONFIG_ADDRMODE
+#define NRFX_QSPI_CONFIG_ADDRMODE 0
+#endif
+
+//  NRFX_QSPI_CONFIG_MODE  - SPI mode.
+
+// <0=> Mode 0
+// <1=> Mode 1
+
+#ifndef NRFX_QSPI_CONFIG_MODE
+#define NRFX_QSPI_CONFIG_MODE 0
+#endif
+
+//  NRFX_QSPI_CONFIG_FREQUENCY  - Frequency divider.
+
+// <0=> 32MHz/1
+// <1=> 32MHz/2
+// <2=> 32MHz/3
+// <3=> 32MHz/4
+// <4=> 32MHz/5
+// <5=> 32MHz/6
+// <6=> 32MHz/7
+// <7=> 32MHz/8
+// <8=> 32MHz/9
+// <9=> 32MHz/10
+// <10=> 32MHz/11
+// <11=> 32MHz/12
+// <12=> 32MHz/13
+// <13=> 32MHz/14
+// <14=> 32MHz/15
+// <15=> 32MHz/16
+
+#ifndef NRFX_QSPI_CONFIG_FREQUENCY
+#define NRFX_QSPI_CONFIG_FREQUENCY 15
+#endif
+
+//  NRFX_QSPI_PIN_SCK - SCK pin value.
+#ifndef NRFX_QSPI_PIN_SCK
+#define NRFX_QSPI_PIN_SCK NRF_QSPI_PIN_NOT_CONNECTED
+#endif
+
+//  NRFX_QSPI_PIN_CSN - CSN pin value.
+#ifndef NRFX_QSPI_PIN_CSN
+#define NRFX_QSPI_PIN_CSN NRF_QSPI_PIN_NOT_CONNECTED
+#endif
+
+//  NRFX_QSPI_PIN_IO0 - IO0 pin value.
+#ifndef NRFX_QSPI_PIN_IO0
+#define NRFX_QSPI_PIN_IO0 NRF_QSPI_PIN_NOT_CONNECTED
+#endif
+
+//  NRFX_QSPI_PIN_IO1 - IO1 pin value.
+#ifndef NRFX_QSPI_PIN_IO1
+#define NRFX_QSPI_PIN_IO1 NRF_QSPI_PIN_NOT_CONNECTED
+#endif
+
+//  NRFX_QSPI_PIN_IO2 - IO2 pin value.
+#ifndef NRFX_QSPI_PIN_IO2
+#define NRFX_QSPI_PIN_IO2 NRF_QSPI_PIN_NOT_CONNECTED
+#endif
+
+//  NRFX_QSPI_PIN_IO3 - IO3 pin value.
+#ifndef NRFX_QSPI_PIN_IO3
+#define NRFX_QSPI_PIN_IO3 NRF_QSPI_PIN_NOT_CONNECTED
+#endif
+
+//  NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+// 
+
+//  NRFX_RNG_ENABLED - nrfx_rng - RNG peripheral driver
+//==========================================================
+#ifndef NRFX_RNG_ENABLED
+#define NRFX_RNG_ENABLED 0
+#endif
+//  NRFX_RNG_CONFIG_ERROR_CORRECTION  - Error correction
+
+
+#ifndef NRFX_RNG_CONFIG_ERROR_CORRECTION
+#define NRFX_RNG_CONFIG_ERROR_CORRECTION 1
+#endif
+
+//  NRFX_RNG_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_RNG_CONFIG_IRQ_PRIORITY
+#define NRFX_RNG_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_RNG_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_RNG_CONFIG_LOG_ENABLED
+#define NRFX_RNG_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_RNG_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_RNG_CONFIG_LOG_LEVEL
+#define NRFX_RNG_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_RNG_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_RNG_CONFIG_INFO_COLOR
+#define NRFX_RNG_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_RNG_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_RNG_CONFIG_DEBUG_COLOR
+#define NRFX_RNG_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_RTC_ENABLED - nrfx_rtc - RTC peripheral driver
+//==========================================================
+#ifndef NRFX_RTC_ENABLED
+#define NRFX_RTC_ENABLED 0
+#endif
+//  NRFX_RTC0_ENABLED  - Enable RTC0 instance
+
+
+#ifndef NRFX_RTC0_ENABLED
+#define NRFX_RTC0_ENABLED 0
+#endif
+
+//  NRFX_RTC1_ENABLED  - Enable RTC1 instance
+
+
+#ifndef NRFX_RTC1_ENABLED
+#define NRFX_RTC1_ENABLED 0
+#endif
+
+//  NRFX_RTC2_ENABLED  - Enable RTC2 instance
+
+
+#ifndef NRFX_RTC2_ENABLED
+#define NRFX_RTC2_ENABLED 0
+#endif
+
+//  NRFX_RTC_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt
+#ifndef NRFX_RTC_MAXIMUM_LATENCY_US
+#define NRFX_RTC_MAXIMUM_LATENCY_US 2000
+#endif
+
+//  NRFX_RTC_DEFAULT_CONFIG_FREQUENCY - Frequency  <16-32768>
+
+
+#ifndef NRFX_RTC_DEFAULT_CONFIG_FREQUENCY
+#define NRFX_RTC_DEFAULT_CONFIG_FREQUENCY 32768
+#endif
+
+//  NRFX_RTC_DEFAULT_CONFIG_RELIABLE  - Ensures safe compare event triggering
+
+
+#ifndef NRFX_RTC_DEFAULT_CONFIG_RELIABLE
+#define NRFX_RTC_DEFAULT_CONFIG_RELIABLE 0
+#endif
+
+//  NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_RTC_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_RTC_CONFIG_LOG_ENABLED
+#define NRFX_RTC_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_RTC_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_RTC_CONFIG_LOG_LEVEL
+#define NRFX_RTC_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_RTC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_RTC_CONFIG_INFO_COLOR
+#define NRFX_RTC_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_RTC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_RTC_CONFIG_DEBUG_COLOR
+#define NRFX_RTC_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_SAADC_ENABLED - nrfx_saadc - SAADC peripheral driver
+//==========================================================
+#ifndef NRFX_SAADC_ENABLED
+#define NRFX_SAADC_ENABLED 0
+#endif
+//  NRFX_SAADC_CONFIG_RESOLUTION  - Resolution
+
+// <0=> 8 bit
+// <1=> 10 bit
+// <2=> 12 bit
+// <3=> 14 bit
+
+#ifndef NRFX_SAADC_CONFIG_RESOLUTION
+#define NRFX_SAADC_CONFIG_RESOLUTION 1
+#endif
+
+//  NRFX_SAADC_CONFIG_OVERSAMPLE  - Sample period
+
+// <0=> Disabled
+// <1=> 2x
+// <2=> 4x
+// <3=> 8x
+// <4=> 16x
+// <5=> 32x
+// <6=> 64x
+// <7=> 128x
+// <8=> 256x
+
+#ifndef NRFX_SAADC_CONFIG_OVERSAMPLE
+#define NRFX_SAADC_CONFIG_OVERSAMPLE 0
+#endif
+
+//  NRFX_SAADC_CONFIG_LP_MODE  - Enabling low power mode
+
+
+#ifndef NRFX_SAADC_CONFIG_LP_MODE
+#define NRFX_SAADC_CONFIG_LP_MODE 0
+#endif
+
+//  NRFX_SAADC_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_SAADC_CONFIG_IRQ_PRIORITY
+#define NRFX_SAADC_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_SAADC_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED
+#define NRFX_SAADC_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_SAADC_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL
+#define NRFX_SAADC_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_SAADC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_SAADC_CONFIG_INFO_COLOR
+#define NRFX_SAADC_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_SAADC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_SAADC_CONFIG_DEBUG_COLOR
+#define NRFX_SAADC_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_SPIM_ENABLED - nrfx_spim - SPIM peripheral driver
+//==========================================================
+#ifndef NRFX_SPIM_ENABLED
+#define NRFX_SPIM_ENABLED 0
+#endif
+//  NRFX_SPIM0_ENABLED  - Enable SPIM0 instance
+
+
+#ifndef NRFX_SPIM0_ENABLED
+#define NRFX_SPIM0_ENABLED 0
+#endif
+
+//  NRFX_SPIM1_ENABLED  - Enable SPIM1 instance
+
+
+#ifndef NRFX_SPIM1_ENABLED
+#define NRFX_SPIM1_ENABLED 0
+#endif
+
+//  NRFX_SPIM2_ENABLED  - Enable SPIM2 instance
+
+
+#ifndef NRFX_SPIM2_ENABLED
+#define NRFX_SPIM2_ENABLED 0
+#endif
+
+//  NRFX_SPIM3_ENABLED  - Enable SPIM3 instance
+
+
+#ifndef NRFX_SPIM3_ENABLED
+#define NRFX_SPIM3_ENABLED 0
+#endif
+
+//  NRFX_SPIM_EXTENDED_ENABLED  - Enable extended SPIM features
+
+
+#ifndef NRFX_SPIM_EXTENDED_ENABLED
+#define NRFX_SPIM_EXTENDED_ENABLED 0
+#endif
+
+//  NRFX_SPIM_MISO_PULL_CFG  - MISO pin pull configuration.
+
+// <0=> NRF_GPIO_PIN_NOPULL
+// <1=> NRF_GPIO_PIN_PULLDOWN
+// <3=> NRF_GPIO_PIN_PULLUP
+
+#ifndef NRFX_SPIM_MISO_PULL_CFG
+#define NRFX_SPIM_MISO_PULL_CFG 1
+#endif
+
+//  NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_SPIM_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED
+#define NRFX_SPIM_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_SPIM_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL
+#define NRFX_SPIM_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_SPIM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_SPIM_CONFIG_INFO_COLOR
+#define NRFX_SPIM_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_SPIM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_SPIM_CONFIG_DEBUG_COLOR
+#define NRFX_SPIM_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_SPIS_ENABLED - nrfx_spis - SPIS peripheral driver
+//==========================================================
+#ifndef NRFX_SPIS_ENABLED
+#define NRFX_SPIS_ENABLED 0
+#endif
+//  NRFX_SPIS0_ENABLED  - Enable SPIS0 instance
+
+
+#ifndef NRFX_SPIS0_ENABLED
+#define NRFX_SPIS0_ENABLED 0
+#endif
+
+//  NRFX_SPIS1_ENABLED  - Enable SPIS1 instance
+
+
+#ifndef NRFX_SPIS1_ENABLED
+#define NRFX_SPIS1_ENABLED 0
+#endif
+
+//  NRFX_SPIS2_ENABLED  - Enable SPIS2 instance
+
+
+#ifndef NRFX_SPIS2_ENABLED
+#define NRFX_SPIS2_ENABLED 0
+#endif
+
+//  NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_SPIS_DEFAULT_DEF - SPIS default DEF character  <0-255>
+
+
+#ifndef NRFX_SPIS_DEFAULT_DEF
+#define NRFX_SPIS_DEFAULT_DEF 255
+#endif
+
+//  NRFX_SPIS_DEFAULT_ORC - SPIS default ORC character  <0-255>
+
+
+#ifndef NRFX_SPIS_DEFAULT_ORC
+#define NRFX_SPIS_DEFAULT_ORC 255
+#endif
+
+//  NRFX_SPIS_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED
+#define NRFX_SPIS_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_SPIS_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL
+#define NRFX_SPIS_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_SPIS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_SPIS_CONFIG_INFO_COLOR
+#define NRFX_SPIS_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_SPIS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_SPIS_CONFIG_DEBUG_COLOR
+#define NRFX_SPIS_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_SPI_ENABLED - nrfx_spi - SPI peripheral driver
+//==========================================================
+#ifndef NRFX_SPI_ENABLED
+#define NRFX_SPI_ENABLED 0
+#endif
+//  NRFX_SPI0_ENABLED  - Enable SPI0 instance
+
+
+#ifndef NRFX_SPI0_ENABLED
+#define NRFX_SPI0_ENABLED 0
+#endif
+
+//  NRFX_SPI1_ENABLED  - Enable SPI1 instance
+
+
+#ifndef NRFX_SPI1_ENABLED
+#define NRFX_SPI1_ENABLED 0
+#endif
+
+//  NRFX_SPI2_ENABLED  - Enable SPI2 instance
+
+
+#ifndef NRFX_SPI2_ENABLED
+#define NRFX_SPI2_ENABLED 0
+#endif
+
+//  NRFX_SPI_MISO_PULL_CFG  - MISO pin pull configuration.
+
+// <0=> NRF_GPIO_PIN_NOPULL
+// <1=> NRF_GPIO_PIN_PULLDOWN
+// <3=> NRF_GPIO_PIN_PULLUP
+
+#ifndef NRFX_SPI_MISO_PULL_CFG
+#define NRFX_SPI_MISO_PULL_CFG 1
+#endif
+
+//  NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_SPI_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_SPI_CONFIG_LOG_ENABLED
+#define NRFX_SPI_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_SPI_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_SPI_CONFIG_LOG_LEVEL
+#define NRFX_SPI_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_SPI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_SPI_CONFIG_INFO_COLOR
+#define NRFX_SPI_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_SPI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_SPI_CONFIG_DEBUG_COLOR
+#define NRFX_SPI_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_SWI_ENABLED - nrfx_swi - SWI/EGU peripheral allocator
+//==========================================================
+#ifndef NRFX_SWI_ENABLED
+#define NRFX_SWI_ENABLED 0
+#endif
+//  NRFX_EGU_ENABLED  - Enable EGU support
+
+
+#ifndef NRFX_EGU_ENABLED
+#define NRFX_EGU_ENABLED 0
+#endif
+
+//  NRFX_SWI0_DISABLED  - Exclude SWI0 from being utilized by the driver
+
+
+#ifndef NRFX_SWI0_DISABLED
+#define NRFX_SWI0_DISABLED 0
+#endif
+
+//  NRFX_SWI1_DISABLED  - Exclude SWI1 from being utilized by the driver
+
+
+#ifndef NRFX_SWI1_DISABLED
+#define NRFX_SWI1_DISABLED 0
+#endif
+
+//  NRFX_SWI2_DISABLED  - Exclude SWI2 from being utilized by the driver
+
+
+#ifndef NRFX_SWI2_DISABLED
+#define NRFX_SWI2_DISABLED 0
+#endif
+
+//  NRFX_SWI3_DISABLED  - Exclude SWI3 from being utilized by the driver
+
+
+#ifndef NRFX_SWI3_DISABLED
+#define NRFX_SWI3_DISABLED 0
+#endif
+
+//  NRFX_SWI4_DISABLED  - Exclude SWI4 from being utilized by the driver
+
+
+#ifndef NRFX_SWI4_DISABLED
+#define NRFX_SWI4_DISABLED 0
+#endif
+
+//  NRFX_SWI5_DISABLED  - Exclude SWI5 from being utilized by the driver
+
+
+#ifndef NRFX_SWI5_DISABLED
+#define NRFX_SWI5_DISABLED 0
+#endif
+
+//  NRFX_SWI_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_SWI_CONFIG_LOG_ENABLED
+#define NRFX_SWI_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_SWI_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_SWI_CONFIG_LOG_LEVEL
+#define NRFX_SWI_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_SWI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_SWI_CONFIG_INFO_COLOR
+#define NRFX_SWI_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_SWI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_SWI_CONFIG_DEBUG_COLOR
+#define NRFX_SWI_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_TIMER_ENABLED - nrfx_timer - TIMER periperal driver
+//==========================================================
+#ifndef NRFX_TIMER_ENABLED
+#define NRFX_TIMER_ENABLED 0
+#endif
+//  NRFX_TIMER0_ENABLED  - Enable TIMER0 instance
+
+
+#ifndef NRFX_TIMER0_ENABLED
+#define NRFX_TIMER0_ENABLED 0
+#endif
+
+//  NRFX_TIMER1_ENABLED  - Enable TIMER1 instance
+
+
+#ifndef NRFX_TIMER1_ENABLED
+#define NRFX_TIMER1_ENABLED 0
+#endif
+
+//  NRFX_TIMER2_ENABLED  - Enable TIMER2 instance
+
+
+#ifndef NRFX_TIMER2_ENABLED
+#define NRFX_TIMER2_ENABLED 0
+#endif
+
+//  NRFX_TIMER3_ENABLED  - Enable TIMER3 instance
+
+
+#ifndef NRFX_TIMER3_ENABLED
+#define NRFX_TIMER3_ENABLED 0
+#endif
+
+//  NRFX_TIMER4_ENABLED  - Enable TIMER4 instance
+
+
+#ifndef NRFX_TIMER4_ENABLED
+#define NRFX_TIMER4_ENABLED 0
+#endif
+
+//  NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY  - Timer frequency if in Timer mode
+
+// <0=> 16 MHz
+// <1=> 8 MHz
+// <2=> 4 MHz
+// <3=> 2 MHz
+// <4=> 1 MHz
+// <5=> 500 kHz
+// <6=> 250 kHz
+// <7=> 125 kHz
+// <8=> 62.5 kHz
+// <9=> 31.25 kHz
+
+#ifndef NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY
+#define NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY 0
+#endif
+
+//  NRFX_TIMER_DEFAULT_CONFIG_MODE  - Timer mode or operation
+
+// <0=> Timer
+// <1=> Counter
+
+#ifndef NRFX_TIMER_DEFAULT_CONFIG_MODE
+#define NRFX_TIMER_DEFAULT_CONFIG_MODE 0
+#endif
+
+//  NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH  - Timer counter bit width
+
+// <0=> 16 bit
+// <1=> 8 bit
+// <2=> 24 bit
+// <3=> 32 bit
+
+#ifndef NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH
+#define NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH 0
+#endif
+
+//  NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_TIMER_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED
+#define NRFX_TIMER_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_TIMER_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL
+#define NRFX_TIMER_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_TIMER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_TIMER_CONFIG_INFO_COLOR
+#define NRFX_TIMER_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_TIMER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_TIMER_CONFIG_DEBUG_COLOR
+#define NRFX_TIMER_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_TWIM_ENABLED - nrfx_twim - TWIM peripheral driver
+//==========================================================
+#ifndef NRFX_TWIM_ENABLED
+#define NRFX_TWIM_ENABLED 0
+#endif
+//  NRFX_TWIM0_ENABLED  - Enable TWIM0 instance
+
+
+#ifndef NRFX_TWIM0_ENABLED
+#define NRFX_TWIM0_ENABLED 0
+#endif
+
+//  NRFX_TWIM1_ENABLED  - Enable TWIM1 instance
+
+
+#ifndef NRFX_TWIM1_ENABLED
+#define NRFX_TWIM1_ENABLED 0
+#endif
+
+//  NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY  - Frequency
+
+// <26738688=> 100k
+// <67108864=> 250k
+// <104857600=> 400k
+
+#ifndef NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY
+#define NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY 26738688
+#endif
+
+//  NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT  - Enables bus holding after uninit
+
+
+#ifndef NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT
+#define NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0
+#endif
+
+//  NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_TWIM_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED
+#define NRFX_TWIM_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_TWIM_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL
+#define NRFX_TWIM_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_TWIM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_TWIM_CONFIG_INFO_COLOR
+#define NRFX_TWIM_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_TWIM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_TWIM_CONFIG_DEBUG_COLOR
+#define NRFX_TWIM_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_TWIS_ENABLED - nrfx_twis - TWIS peripheral driver
+//==========================================================
+#ifndef NRFX_TWIS_ENABLED
+#define NRFX_TWIS_ENABLED 0
+#endif
+//  NRFX_TWIS0_ENABLED  - Enable TWIS0 instance
+
+
+#ifndef NRFX_TWIS0_ENABLED
+#define NRFX_TWIS0_ENABLED 0
+#endif
+
+//  NRFX_TWIS1_ENABLED  - Enable TWIS1 instance
+
+
+#ifndef NRFX_TWIS1_ENABLED
+#define NRFX_TWIS1_ENABLED 0
+#endif
+
+//  NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY  - Assume that any instance would be initialized only once
+
+
+//  Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code.
+
+#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY
+#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
+#endif
+
+//  NRFX_TWIS_NO_SYNC_MODE  - Remove support for synchronous mode
+
+
+//  Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources.
+
+#ifndef NRFX_TWIS_NO_SYNC_MODE
+#define NRFX_TWIS_NO_SYNC_MODE 0
+#endif
+
+//  NRFX_TWIS_DEFAULT_CONFIG_ADDR0 - Address0
+#ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR0
+#define NRFX_TWIS_DEFAULT_CONFIG_ADDR0 0
+#endif
+
+//  NRFX_TWIS_DEFAULT_CONFIG_ADDR1 - Address1
+#ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR1
+#define NRFX_TWIS_DEFAULT_CONFIG_ADDR1 0
+#endif
+
+//  NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL  - SCL pin pull configuration
+
+// <0=> Disabled
+// <1=> Pull down
+// <3=> Pull up
+
+#ifndef NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL
+#define NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL 0
+#endif
+
+//  NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL  - SDA pin pull configuration
+
+// <0=> Disabled
+// <1=> Pull down
+// <3=> Pull up
+
+#ifndef NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL
+#define NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL 0
+#endif
+
+//  NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_TWIS_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED
+#define NRFX_TWIS_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_TWIS_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL
+#define NRFX_TWIS_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_TWIS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_TWIS_CONFIG_INFO_COLOR
+#define NRFX_TWIS_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_TWIS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_TWIS_CONFIG_DEBUG_COLOR
+#define NRFX_TWIS_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_TWI_ENABLED - nrfx_twi - TWI peripheral driver
+//==========================================================
+#ifndef NRFX_TWI_ENABLED
+#define NRFX_TWI_ENABLED 0
+#endif
+//  NRFX_TWI0_ENABLED  - Enable TWI0 instance
+
+
+#ifndef NRFX_TWI0_ENABLED
+#define NRFX_TWI0_ENABLED 0
+#endif
+
+//  NRFX_TWI1_ENABLED  - Enable TWI1 instance
+
+
+#ifndef NRFX_TWI1_ENABLED
+#define NRFX_TWI1_ENABLED 0
+#endif
+
+//  NRFX_TWI_DEFAULT_CONFIG_FREQUENCY  - Frequency
+
+// <26738688=> 100k
+// <67108864=> 250k
+// <104857600=> 400k
+
+#ifndef NRFX_TWI_DEFAULT_CONFIG_FREQUENCY
+#define NRFX_TWI_DEFAULT_CONFIG_FREQUENCY 26738688
+#endif
+
+//  NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT  - Enables bus holding after uninit
+
+
+#ifndef NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT
+#define NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0
+#endif
+
+//  NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_TWI_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_TWI_CONFIG_LOG_ENABLED
+#define NRFX_TWI_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_TWI_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_TWI_CONFIG_LOG_LEVEL
+#define NRFX_TWI_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_TWI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_TWI_CONFIG_INFO_COLOR
+#define NRFX_TWI_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_TWI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_TWI_CONFIG_DEBUG_COLOR
+#define NRFX_TWI_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_UARTE_ENABLED - nrfx_uarte - UARTE peripheral driver
+//==========================================================
+#ifndef NRFX_UARTE_ENABLED
+#define NRFX_UARTE_ENABLED 0
+#endif
+//  NRFX_UARTE0_ENABLED - Enable UARTE0 instance
+#ifndef NRFX_UARTE0_ENABLED
+#define NRFX_UARTE0_ENABLED 0
+#endif
+
+//  NRFX_UARTE1_ENABLED - Enable UARTE1 instance
+#ifndef NRFX_UARTE1_ENABLED
+#define NRFX_UARTE1_ENABLED 0
+#endif
+
+//  NRFX_UARTE_DEFAULT_CONFIG_HWFC  - Hardware Flow Control
+
+// <0=> Disabled
+// <1=> Enabled
+
+#ifndef NRFX_UARTE_DEFAULT_CONFIG_HWFC
+#define NRFX_UARTE_DEFAULT_CONFIG_HWFC 0
+#endif
+
+//  NRFX_UARTE_DEFAULT_CONFIG_PARITY  - Parity
+
+// <0=> Excluded
+// <14=> Included
+
+#ifndef NRFX_UARTE_DEFAULT_CONFIG_PARITY
+#define NRFX_UARTE_DEFAULT_CONFIG_PARITY 0
+#endif
+
+//  NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE  - Default Baudrate
+
+// <323584=> 1200 baud
+// <643072=> 2400 baud
+// <1290240=> 4800 baud
+// <2576384=> 9600 baud
+// <3862528=> 14400 baud
+// <5152768=> 19200 baud
+// <7716864=> 28800 baud
+// <8388608=> 31250 baud
+// <10289152=> 38400 baud
+// <15007744=> 56000 baud
+// <15400960=> 57600 baud
+// <20615168=> 76800 baud
+// <30801920=> 115200 baud
+// <61865984=> 230400 baud
+// <67108864=> 250000 baud
+// <121634816=> 460800 baud
+// <251658240=> 921600 baud
+// <268435456=> 1000000 baud
+
+#ifndef NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE
+#define NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE 30801920
+#endif
+
+//  NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_UARTE_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED
+#define NRFX_UARTE_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_UARTE_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL
+#define NRFX_UARTE_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_UARTE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_UARTE_CONFIG_INFO_COLOR
+#define NRFX_UARTE_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_UARTE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_UARTE_CONFIG_DEBUG_COLOR
+#define NRFX_UARTE_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_UART_ENABLED - nrfx_uart - UART peripheral driver
+//==========================================================
+#ifndef NRFX_UART_ENABLED
+#define NRFX_UART_ENABLED 0
+#endif
+//  NRFX_UART0_ENABLED - Enable UART0 instance
+#ifndef NRFX_UART0_ENABLED
+#define NRFX_UART0_ENABLED 0
+#endif
+
+//  NRFX_UART_DEFAULT_CONFIG_HWFC  - Hardware Flow Control
+
+// <0=> Disabled
+// <1=> Enabled
+
+#ifndef NRFX_UART_DEFAULT_CONFIG_HWFC
+#define NRFX_UART_DEFAULT_CONFIG_HWFC 0
+#endif
+
+//  NRFX_UART_DEFAULT_CONFIG_PARITY  - Parity
+
+// <0=> Excluded
+// <14=> Included
+
+#ifndef NRFX_UART_DEFAULT_CONFIG_PARITY
+#define NRFX_UART_DEFAULT_CONFIG_PARITY 0
+#endif
+
+//  NRFX_UART_DEFAULT_CONFIG_BAUDRATE  - Default Baudrate
+
+// <323584=> 1200 baud
+// <643072=> 2400 baud
+// <1290240=> 4800 baud
+// <2576384=> 9600 baud
+// <3866624=> 14400 baud
+// <5152768=> 19200 baud
+// <7729152=> 28800 baud
+// <8388608=> 31250 baud
+// <10309632=> 38400 baud
+// <15007744=> 56000 baud
+// <15462400=> 57600 baud
+// <20615168=> 76800 baud
+// <30924800=> 115200 baud
+// <61845504=> 230400 baud
+// <67108864=> 250000 baud
+// <123695104=> 460800 baud
+// <247386112=> 921600 baud
+// <268435456=> 1000000 baud
+
+#ifndef NRFX_UART_DEFAULT_CONFIG_BAUDRATE
+#define NRFX_UART_DEFAULT_CONFIG_BAUDRATE 30924800
+#endif
+
+//  NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY 4
+#endif
+
+//  NRFX_UART_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_UART_CONFIG_LOG_ENABLED
+#define NRFX_UART_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_UART_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_UART_CONFIG_LOG_LEVEL
+#define NRFX_UART_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_UART_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_UART_CONFIG_INFO_COLOR
+#define NRFX_UART_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_UART_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_UART_CONFIG_DEBUG_COLOR
+#define NRFX_UART_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_USBD_ENABLED - nrfx_usbd - USBD peripheral driver
+//==========================================================
+#ifndef NRFX_USBD_ENABLED
+#define NRFX_USBD_ENABLED 0
+#endif
+//  NRFX_USBD_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_USBD_CONFIG_IRQ_PRIORITY
+#define NRFX_USBD_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_USBD_CONFIG_DMASCHEDULER_MODE  - USBD DMA scheduler working scheme
+
+// <0=> Prioritized access
+// <1=> Round Robin
+
+#ifndef NRFX_USBD_CONFIG_DMASCHEDULER_MODE
+#define NRFX_USBD_CONFIG_DMASCHEDULER_MODE 0
+#endif
+
+//  NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST  - Give priority to isochronous transfers
+
+
+//  This option gives priority to isochronous transfers.
+//  Enabling it assures that isochronous transfers are always processed,
+//  even if multiple other transfers are pending.
+//  Isochronous endpoints are prioritized before the usbd_dma_scheduler_algorithm
+//  function is called, so the option is independent of the algorithm chosen.
+
+#ifndef NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST
+#define NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST 1
+#endif
+
+//  NRFX_USBD_CONFIG_ISO_IN_ZLP  - Respond to an IN token on ISO IN endpoint with ZLP when no data is ready
+
+
+//  If set, ISO IN endpoint will respond to an IN token with ZLP when no data is ready to be sent.
+//  Else, there will be no response.
+
+#ifndef NRFX_USBD_CONFIG_ISO_IN_ZLP
+#define NRFX_USBD_CONFIG_ISO_IN_ZLP 0
+#endif
+
+// 
+
+//  NRFX_WDT_ENABLED - nrfx_wdt - WDT peripheral driver
+//==========================================================
+#ifndef NRFX_WDT_ENABLED
+#define NRFX_WDT_ENABLED 0
+#endif
+//  NRFX_WDT_CONFIG_BEHAVIOUR  - WDT behavior in CPU SLEEP or HALT mode
+
+// <1=> Run in SLEEP, Pause in HALT
+// <8=> Pause in SLEEP, Run in HALT
+// <9=> Run in SLEEP and HALT
+// <0=> Pause in SLEEP and HALT
+
+#ifndef NRFX_WDT_CONFIG_BEHAVIOUR
+#define NRFX_WDT_CONFIG_BEHAVIOUR 1
+#endif
+
+//  NRFX_WDT_CONFIG_RELOAD_VALUE - Reload value  <15-4294967295>
+
+
+#ifndef NRFX_WDT_CONFIG_RELOAD_VALUE
+#define NRFX_WDT_CONFIG_RELOAD_VALUE 2000
+#endif
+
+//  NRFX_WDT_CONFIG_NO_IRQ  - Remove WDT IRQ handling from WDT driver
+
+// <0=> Include WDT IRQ handling
+// <1=> Remove WDT IRQ handling
+
+#ifndef NRFX_WDT_CONFIG_NO_IRQ
+#define NRFX_WDT_CONFIG_NO_IRQ 0
+#endif
+
+//  NRFX_WDT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_WDT_CONFIG_IRQ_PRIORITY
+#define NRFX_WDT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_WDT_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_WDT_CONFIG_LOG_ENABLED
+#define NRFX_WDT_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_WDT_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_WDT_CONFIG_LOG_LEVEL
+#define NRFX_WDT_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_WDT_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_WDT_CONFIG_INFO_COLOR
+#define NRFX_WDT_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_WDT_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_WDT_CONFIG_DEBUG_COLOR
+#define NRFX_WDT_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRF_CLOCK_ENABLED - nrf_drv_clock - CLOCK peripheral driver - legacy layer
+//==========================================================
+#ifndef NRF_CLOCK_ENABLED
+#define NRF_CLOCK_ENABLED 0
+#endif
+//  CLOCK_CONFIG_LF_SRC  - LF Clock Source
+
+// <0=> RC
+// <1=> XTAL
+// <2=> Synth
+// <131073=> External Low Swing
+// <196609=> External Full Swing
+
+#ifndef CLOCK_CONFIG_LF_SRC
+#define CLOCK_CONFIG_LF_SRC 1
+#endif
+
+//  CLOCK_CONFIG_LF_CAL_ENABLED  - Calibration enable for LF Clock Source
+
+
+#ifndef CLOCK_CONFIG_LF_CAL_ENABLED
+#define CLOCK_CONFIG_LF_CAL_ENABLED 0
+#endif
+
+//  CLOCK_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef CLOCK_CONFIG_IRQ_PRIORITY
+#define CLOCK_CONFIG_IRQ_PRIORITY 6
+#endif
+
+// 
+
+//  PDM_ENABLED - nrf_drv_pdm - PDM peripheral driver - legacy layer
+//==========================================================
+#ifndef PDM_ENABLED
+#define PDM_ENABLED 0
+#endif
+//  PDM_CONFIG_MODE  - Mode
+
+// <0=> Stereo
+// <1=> Mono
+
+#ifndef PDM_CONFIG_MODE
+#define PDM_CONFIG_MODE 1
+#endif
+
+//  PDM_CONFIG_EDGE  - Edge
+
+// <0=> Left falling
+// <1=> Left rising
+
+#ifndef PDM_CONFIG_EDGE
+#define PDM_CONFIG_EDGE 0
+#endif
+
+//  PDM_CONFIG_CLOCK_FREQ  - Clock frequency
+
+// <134217728=> 1000k
+// <138412032=> 1032k (default)
+// <142606336=> 1067k
+
+#ifndef PDM_CONFIG_CLOCK_FREQ
+#define PDM_CONFIG_CLOCK_FREQ 138412032
+#endif
+
+//  PDM_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef PDM_CONFIG_IRQ_PRIORITY
+#define PDM_CONFIG_IRQ_PRIORITY 6
+#endif
+
+// 
+
+//  POWER_ENABLED - nrf_drv_power - POWER peripheral driver - legacy layer
+//==========================================================
+#ifndef POWER_ENABLED
+#define POWER_ENABLED 0
+#endif
+//  POWER_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef POWER_CONFIG_IRQ_PRIORITY
+#define POWER_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  POWER_CONFIG_DEFAULT_DCDCEN  - The default configuration of main DCDC regulator
+
+
+//  This settings means only that components for DCDC regulator are installed and it can be enabled.
+
+#ifndef POWER_CONFIG_DEFAULT_DCDCEN
+#define POWER_CONFIG_DEFAULT_DCDCEN 0
+#endif
+
+//  POWER_CONFIG_DEFAULT_DCDCENHV  - The default configuration of High Voltage DCDC regulator
+
+
+//  This settings means only that components for DCDC regulator are installed and it can be enabled.
+
+#ifndef POWER_CONFIG_DEFAULT_DCDCENHV
+#define POWER_CONFIG_DEFAULT_DCDCENHV 0
+#endif
+
+// 
+
+//  PPI_ENABLED  - nrf_drv_ppi - PPI peripheral driver - legacy layer
+
+
+#ifndef PPI_ENABLED
+#define PPI_ENABLED 0
+#endif
+
+//  PWM_ENABLED - nrf_drv_pwm - PWM peripheral driver - legacy layer
+//==========================================================
+#ifndef PWM_ENABLED
+#define PWM_ENABLED 0
+#endif
+//  PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin  <0-31>
+
+
+#ifndef PWM_DEFAULT_CONFIG_OUT0_PIN
+#define PWM_DEFAULT_CONFIG_OUT0_PIN 31
+#endif
+
+//  PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin  <0-31>
+
+
+#ifndef PWM_DEFAULT_CONFIG_OUT1_PIN
+#define PWM_DEFAULT_CONFIG_OUT1_PIN 31
+#endif
+
+//  PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin  <0-31>
+
+
+#ifndef PWM_DEFAULT_CONFIG_OUT2_PIN
+#define PWM_DEFAULT_CONFIG_OUT2_PIN 31
+#endif
+
+//  PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin  <0-31>
+
+
+#ifndef PWM_DEFAULT_CONFIG_OUT3_PIN
+#define PWM_DEFAULT_CONFIG_OUT3_PIN 31
+#endif
+
+//  PWM_DEFAULT_CONFIG_BASE_CLOCK  - Base clock
+
+// <0=> 16 MHz
+// <1=> 8 MHz
+// <2=> 4 MHz
+// <3=> 2 MHz
+// <4=> 1 MHz
+// <5=> 500 kHz
+// <6=> 250 kHz
+// <7=> 125 kHz
+
+#ifndef PWM_DEFAULT_CONFIG_BASE_CLOCK
+#define PWM_DEFAULT_CONFIG_BASE_CLOCK 4
+#endif
+
+//  PWM_DEFAULT_CONFIG_COUNT_MODE  - Count mode
+
+// <0=> Up
+// <1=> Up and Down
+
+#ifndef PWM_DEFAULT_CONFIG_COUNT_MODE
+#define PWM_DEFAULT_CONFIG_COUNT_MODE 0
+#endif
+
+//  PWM_DEFAULT_CONFIG_TOP_VALUE - Top value
+#ifndef PWM_DEFAULT_CONFIG_TOP_VALUE
+#define PWM_DEFAULT_CONFIG_TOP_VALUE 1000
+#endif
+
+//  PWM_DEFAULT_CONFIG_LOAD_MODE  - Load mode
+
+// <0=> Common
+// <1=> Grouped
+// <2=> Individual
+// <3=> Waveform
+
+#ifndef PWM_DEFAULT_CONFIG_LOAD_MODE
+#define PWM_DEFAULT_CONFIG_LOAD_MODE 0
+#endif
+
+//  PWM_DEFAULT_CONFIG_STEP_MODE  - Step mode
+
+// <0=> Auto
+// <1=> Triggered
+
+#ifndef PWM_DEFAULT_CONFIG_STEP_MODE
+#define PWM_DEFAULT_CONFIG_STEP_MODE 0
+#endif
+
+//  PWM_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef PWM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define PWM_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  PWM0_ENABLED  - Enable PWM0 instance
+
+
+#ifndef PWM0_ENABLED
+#define PWM0_ENABLED 0
+#endif
+
+//  PWM1_ENABLED  - Enable PWM1 instance
+
+
+#ifndef PWM1_ENABLED
+#define PWM1_ENABLED 0
+#endif
+
+//  PWM2_ENABLED  - Enable PWM2 instance
+
+
+#ifndef PWM2_ENABLED
+#define PWM2_ENABLED 0
+#endif
+
+//  PWM3_ENABLED  - Enable PWM3 instance
+
+
+#ifndef PWM3_ENABLED
+#define PWM3_ENABLED 0
+#endif
+
+// 
+
+//  QDEC_ENABLED - nrf_drv_qdec - QDEC peripheral driver - legacy layer
+//==========================================================
+#ifndef QDEC_ENABLED
+#define QDEC_ENABLED 0
+#endif
+//  QDEC_CONFIG_REPORTPER  - Report period
+
+// <0=> 10 Samples
+// <1=> 40 Samples
+// <2=> 80 Samples
+// <3=> 120 Samples
+// <4=> 160 Samples
+// <5=> 200 Samples
+// <6=> 240 Samples
+// <7=> 280 Samples
+
+#ifndef QDEC_CONFIG_REPORTPER
+#define QDEC_CONFIG_REPORTPER 0
+#endif
+
+//  QDEC_CONFIG_SAMPLEPER  - Sample period
+
+// <0=> 128 us
+// <1=> 256 us
+// <2=> 512 us
+// <3=> 1024 us
+// <4=> 2048 us
+// <5=> 4096 us
+// <6=> 8192 us
+// <7=> 16384 us
+
+#ifndef QDEC_CONFIG_SAMPLEPER
+#define QDEC_CONFIG_SAMPLEPER 7
+#endif
+
+//  QDEC_CONFIG_PIO_A - A pin  <0-31>
+
+
+#ifndef QDEC_CONFIG_PIO_A
+#define QDEC_CONFIG_PIO_A 31
+#endif
+
+//  QDEC_CONFIG_PIO_B - B pin  <0-31>
+
+
+#ifndef QDEC_CONFIG_PIO_B
+#define QDEC_CONFIG_PIO_B 31
+#endif
+
+//  QDEC_CONFIG_PIO_LED - LED pin  <0-31>
+
+
+#ifndef QDEC_CONFIG_PIO_LED
+#define QDEC_CONFIG_PIO_LED 31
+#endif
+
+//  QDEC_CONFIG_LEDPRE - LED pre
+#ifndef QDEC_CONFIG_LEDPRE
+#define QDEC_CONFIG_LEDPRE 511
+#endif
+
+//  QDEC_CONFIG_LEDPOL  - LED polarity
+
+// <0=> Active low
+// <1=> Active high
+
+#ifndef QDEC_CONFIG_LEDPOL
+#define QDEC_CONFIG_LEDPOL 1
+#endif
+
+//  QDEC_CONFIG_DBFEN  - Debouncing enable
+
+
+#ifndef QDEC_CONFIG_DBFEN
+#define QDEC_CONFIG_DBFEN 0
+#endif
+
+//  QDEC_CONFIG_SAMPLE_INTEN  - Sample ready interrupt enable
+
+
+#ifndef QDEC_CONFIG_SAMPLE_INTEN
+#define QDEC_CONFIG_SAMPLE_INTEN 0
+#endif
+
+//  QDEC_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef QDEC_CONFIG_IRQ_PRIORITY
+#define QDEC_CONFIG_IRQ_PRIORITY 6
+#endif
+
+// 
+
+//  QSPI_ENABLED - nrf_drv_qspi - QSPI peripheral driver - legacy layer
+//==========================================================
+#ifndef QSPI_ENABLED
+#define QSPI_ENABLED 0
+#endif
+//  QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns).  <0-255>
+
+
+#ifndef QSPI_CONFIG_SCK_DELAY
+#define QSPI_CONFIG_SCK_DELAY 1
+#endif
+
+//  QSPI_CONFIG_XIP_OFFSET - Address offset in the external memory for Execute in Place operation.
+#ifndef QSPI_CONFIG_XIP_OFFSET
+#define QSPI_CONFIG_XIP_OFFSET 0
+#endif
+
+//  QSPI_CONFIG_READOC  - Number of data lines and opcode used for reading.
+
+// <0=> FastRead
+// <1=> Read2O
+// <2=> Read2IO
+// <3=> Read4O
+// <4=> Read4IO
+
+#ifndef QSPI_CONFIG_READOC
+#define QSPI_CONFIG_READOC 0
+#endif
+
+//  QSPI_CONFIG_WRITEOC  - Number of data lines and opcode used for writing.
+
+// <0=> PP
+// <1=> PP2O
+// <2=> PP4O
+// <3=> PP4IO
+
+#ifndef QSPI_CONFIG_WRITEOC
+#define QSPI_CONFIG_WRITEOC 0
+#endif
+
+//  QSPI_CONFIG_ADDRMODE  - Addressing mode.
+
+// <0=> 24bit
+// <1=> 32bit
+
+#ifndef QSPI_CONFIG_ADDRMODE
+#define QSPI_CONFIG_ADDRMODE 0
+#endif
+
+//  QSPI_CONFIG_MODE  - SPI mode.
+
+// <0=> Mode 0
+// <1=> Mode 1
+
+#ifndef QSPI_CONFIG_MODE
+#define QSPI_CONFIG_MODE 0
+#endif
+
+//  QSPI_CONFIG_FREQUENCY  - Frequency divider.
+
+// <0=> 32MHz/1
+// <1=> 32MHz/2
+// <2=> 32MHz/3
+// <3=> 32MHz/4
+// <4=> 32MHz/5
+// <5=> 32MHz/6
+// <6=> 32MHz/7
+// <7=> 32MHz/8
+// <8=> 32MHz/9
+// <9=> 32MHz/10
+// <10=> 32MHz/11
+// <11=> 32MHz/12
+// <12=> 32MHz/13
+// <13=> 32MHz/14
+// <14=> 32MHz/15
+// <15=> 32MHz/16
+
+#ifndef QSPI_CONFIG_FREQUENCY
+#define QSPI_CONFIG_FREQUENCY 15
+#endif
+
+//  QSPI_PIN_SCK - SCK pin value.
+#ifndef QSPI_PIN_SCK
+#define QSPI_PIN_SCK NRF_QSPI_PIN_NOT_CONNECTED
+#endif
+
+//  QSPI_PIN_CSN - CSN pin value.
+#ifndef QSPI_PIN_CSN
+#define QSPI_PIN_CSN NRF_QSPI_PIN_NOT_CONNECTED
+#endif
+
+//  QSPI_PIN_IO0 - IO0 pin value.
+#ifndef QSPI_PIN_IO0
+#define QSPI_PIN_IO0 NRF_QSPI_PIN_NOT_CONNECTED
+#endif
+
+//  QSPI_PIN_IO1 - IO1 pin value.
+#ifndef QSPI_PIN_IO1
+#define QSPI_PIN_IO1 NRF_QSPI_PIN_NOT_CONNECTED
+#endif
+
+//  QSPI_PIN_IO2 - IO2 pin value.
+#ifndef QSPI_PIN_IO2
+#define QSPI_PIN_IO2 NRF_QSPI_PIN_NOT_CONNECTED
+#endif
+
+//  QSPI_PIN_IO3 - IO3 pin value.
+#ifndef QSPI_PIN_IO3
+#define QSPI_PIN_IO3 NRF_QSPI_PIN_NOT_CONNECTED
+#endif
+
+//  QSPI_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef QSPI_CONFIG_IRQ_PRIORITY
+#define QSPI_CONFIG_IRQ_PRIORITY 6
+#endif
+
+// 
+
+//  RNG_ENABLED - nrf_drv_rng - RNG peripheral driver - legacy layer
+//==========================================================
+#ifndef RNG_ENABLED
+#define RNG_ENABLED 0
+#endif
+//  RNG_CONFIG_ERROR_CORRECTION  - Error correction
+
+
+#ifndef RNG_CONFIG_ERROR_CORRECTION
+#define RNG_CONFIG_ERROR_CORRECTION 1
+#endif
+
+//  RNG_CONFIG_POOL_SIZE - Pool size
+#ifndef RNG_CONFIG_POOL_SIZE
+#define RNG_CONFIG_POOL_SIZE 64
+#endif
+
+//  RNG_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef RNG_CONFIG_IRQ_PRIORITY
+#define RNG_CONFIG_IRQ_PRIORITY 6
+#endif
+
+// 
+
+//  RTC_ENABLED - nrf_drv_rtc - RTC peripheral driver - legacy layer
+//==========================================================
+#ifndef RTC_ENABLED
+#define RTC_ENABLED 0
+#endif
+//  RTC_DEFAULT_CONFIG_FREQUENCY - Frequency  <16-32768>
+
+
+#ifndef RTC_DEFAULT_CONFIG_FREQUENCY
+#define RTC_DEFAULT_CONFIG_FREQUENCY 32768
+#endif
+
+//  RTC_DEFAULT_CONFIG_RELIABLE  - Ensures safe compare event triggering
+
+
+#ifndef RTC_DEFAULT_CONFIG_RELIABLE
+#define RTC_DEFAULT_CONFIG_RELIABLE 0
+#endif
+
+//  RTC_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef RTC_DEFAULT_CONFIG_IRQ_PRIORITY
+#define RTC_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  RTC0_ENABLED  - Enable RTC0 instance
+
+
+#ifndef RTC0_ENABLED
+#define RTC0_ENABLED 0
+#endif
+
+//  RTC1_ENABLED  - Enable RTC1 instance
+
+
+#ifndef RTC1_ENABLED
+#define RTC1_ENABLED 0
+#endif
+
+//  RTC2_ENABLED  - Enable RTC2 instance
+
+
+#ifndef RTC2_ENABLED
+#define RTC2_ENABLED 0
+#endif
+
+//  NRF_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt
+#ifndef NRF_MAXIMUM_LATENCY_US
+#define NRF_MAXIMUM_LATENCY_US 2000
+#endif
+
+// 
+
+//  SAADC_ENABLED - nrf_drv_saadc - SAADC peripheral driver - legacy layer
+//==========================================================
+#ifndef SAADC_ENABLED
+#define SAADC_ENABLED 0
+#endif
+//  SAADC_CONFIG_RESOLUTION  - Resolution
+
+// <0=> 8 bit
+// <1=> 10 bit
+// <2=> 12 bit
+// <3=> 14 bit
+
+#ifndef SAADC_CONFIG_RESOLUTION
+#define SAADC_CONFIG_RESOLUTION 1
+#endif
+
+//  SAADC_CONFIG_OVERSAMPLE  - Sample period
+
+// <0=> Disabled
+// <1=> 2x
+// <2=> 4x
+// <3=> 8x
+// <4=> 16x
+// <5=> 32x
+// <6=> 64x
+// <7=> 128x
+// <8=> 256x
+
+#ifndef SAADC_CONFIG_OVERSAMPLE
+#define SAADC_CONFIG_OVERSAMPLE 0
+#endif
+
+//  SAADC_CONFIG_LP_MODE  - Enabling low power mode
+
+
+#ifndef SAADC_CONFIG_LP_MODE
+#define SAADC_CONFIG_LP_MODE 0
+#endif
+
+//  SAADC_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef SAADC_CONFIG_IRQ_PRIORITY
+#define SAADC_CONFIG_IRQ_PRIORITY 6
+#endif
+
+// 
+
+//  SPIS_ENABLED - nrf_drv_spis - SPIS peripheral driver - legacy layer
+//==========================================================
+#ifndef SPIS_ENABLED
+#define SPIS_ENABLED 0
+#endif
+//  SPIS_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
+#define SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  SPIS_DEFAULT_MODE  - Mode
+
+// <0=> MODE_0
+// <1=> MODE_1
+// <2=> MODE_2
+// <3=> MODE_3
+
+#ifndef SPIS_DEFAULT_MODE
+#define SPIS_DEFAULT_MODE 0
+#endif
+
+//  SPIS_DEFAULT_BIT_ORDER  - SPIS default bit order
+
+// <0=> MSB first
+// <1=> LSB first
+
+#ifndef SPIS_DEFAULT_BIT_ORDER
+#define SPIS_DEFAULT_BIT_ORDER 0
+#endif
+
+//  SPIS_DEFAULT_DEF - SPIS default DEF character  <0-255>
+
+
+#ifndef SPIS_DEFAULT_DEF
+#define SPIS_DEFAULT_DEF 255
+#endif
+
+//  SPIS_DEFAULT_ORC - SPIS default ORC character  <0-255>
+
+
+#ifndef SPIS_DEFAULT_ORC
+#define SPIS_DEFAULT_ORC 255
+#endif
+
+//  SPIS0_ENABLED  - Enable SPIS0 instance
+
+
+#ifndef SPIS0_ENABLED
+#define SPIS0_ENABLED 0
+#endif
+
+//  SPIS1_ENABLED  - Enable SPIS1 instance
+
+
+#ifndef SPIS1_ENABLED
+#define SPIS1_ENABLED 0
+#endif
+
+//  SPIS2_ENABLED  - Enable SPIS2 instance
+
+
+#ifndef SPIS2_ENABLED
+#define SPIS2_ENABLED 0
+#endif
+
+// 
+
+//  SPI_ENABLED - nrf_drv_spi - SPI/SPIM peripheral driver - legacy layer
+//==========================================================
+#ifndef SPI_ENABLED
+#define SPI_ENABLED 0
+#endif
+//  SPI_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef SPI_DEFAULT_CONFIG_IRQ_PRIORITY
+#define SPI_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRF_SPI_DRV_MISO_PULLUP_CFG  - MISO PIN pull-up configuration.
+
+// <0=> NRF_GPIO_PIN_NOPULL
+// <1=> NRF_GPIO_PIN_PULLDOWN
+// <3=> NRF_GPIO_PIN_PULLUP
+
+#ifndef NRF_SPI_DRV_MISO_PULLUP_CFG
+#define NRF_SPI_DRV_MISO_PULLUP_CFG 1
+#endif
+
+//  SPI0_ENABLED - Enable SPI0 instance
+//==========================================================
+#ifndef SPI0_ENABLED
+#define SPI0_ENABLED 0
+#endif
+//  SPI0_USE_EASY_DMA  - Use EasyDMA
+
+
+#ifndef SPI0_USE_EASY_DMA
+#define SPI0_USE_EASY_DMA 1
+#endif
+
+// 
+
+//  SPI1_ENABLED - Enable SPI1 instance
+//==========================================================
+#ifndef SPI1_ENABLED
+#define SPI1_ENABLED 0
+#endif
+//  SPI1_USE_EASY_DMA  - Use EasyDMA
+
+
+#ifndef SPI1_USE_EASY_DMA
+#define SPI1_USE_EASY_DMA 1
+#endif
+
+// 
+
+//  SPI2_ENABLED - Enable SPI2 instance
+//==========================================================
+#ifndef SPI2_ENABLED
+#define SPI2_ENABLED 0
+#endif
+//  SPI2_USE_EASY_DMA  - Use EasyDMA
+
+
+#ifndef SPI2_USE_EASY_DMA
+#define SPI2_USE_EASY_DMA 1
+#endif
+
+// 
+
+// 
+
+//  TIMER_ENABLED - nrf_drv_timer - TIMER periperal driver - legacy layer
+//==========================================================
+#ifndef TIMER_ENABLED
+#define TIMER_ENABLED 0
+#endif
+//  TIMER_DEFAULT_CONFIG_FREQUENCY  - Timer frequency if in Timer mode
+
+// <0=> 16 MHz
+// <1=> 8 MHz
+// <2=> 4 MHz
+// <3=> 2 MHz
+// <4=> 1 MHz
+// <5=> 500 kHz
+// <6=> 250 kHz
+// <7=> 125 kHz
+// <8=> 62.5 kHz
+// <9=> 31.25 kHz
+
+#ifndef TIMER_DEFAULT_CONFIG_FREQUENCY
+#define TIMER_DEFAULT_CONFIG_FREQUENCY 0
+#endif
+
+//  TIMER_DEFAULT_CONFIG_MODE  - Timer mode or operation
+
+// <0=> Timer
+// <1=> Counter
+
+#ifndef TIMER_DEFAULT_CONFIG_MODE
+#define TIMER_DEFAULT_CONFIG_MODE 0
+#endif
+
+//  TIMER_DEFAULT_CONFIG_BIT_WIDTH  - Timer counter bit width
+
+// <0=> 16 bit
+// <1=> 8 bit
+// <2=> 24 bit
+// <3=> 32 bit
+
+#ifndef TIMER_DEFAULT_CONFIG_BIT_WIDTH
+#define TIMER_DEFAULT_CONFIG_BIT_WIDTH 0
+#endif
+
+//  TIMER_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
+#define TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  TIMER0_ENABLED  - Enable TIMER0 instance
+
+
+#ifndef TIMER0_ENABLED
+#define TIMER0_ENABLED 0
+#endif
+
+//  TIMER1_ENABLED  - Enable TIMER1 instance
+
+
+#ifndef TIMER1_ENABLED
+#define TIMER1_ENABLED 0
+#endif
+
+//  TIMER2_ENABLED  - Enable TIMER2 instance
+
+
+#ifndef TIMER2_ENABLED
+#define TIMER2_ENABLED 0
+#endif
+
+//  TIMER3_ENABLED  - Enable TIMER3 instance
+
+
+#ifndef TIMER3_ENABLED
+#define TIMER3_ENABLED 0
+#endif
+
+//  TIMER4_ENABLED  - Enable TIMER4 instance
+
+
+#ifndef TIMER4_ENABLED
+#define TIMER4_ENABLED 0
+#endif
+
+// 
+
+//  TWIS_ENABLED - nrf_drv_twis - TWIS peripheral driver - legacy layer
+//==========================================================
+#ifndef TWIS_ENABLED
+#define TWIS_ENABLED 0
+#endif
+//  TWIS0_ENABLED  - Enable TWIS0 instance
+
+
+#ifndef TWIS0_ENABLED
+#define TWIS0_ENABLED 0
+#endif
+
+//  TWIS1_ENABLED  - Enable TWIS1 instance
+
+
+#ifndef TWIS1_ENABLED
+#define TWIS1_ENABLED 0
+#endif
+
+//  TWIS_ASSUME_INIT_AFTER_RESET_ONLY  - Assume that any instance would be initialized only once
+
+
+//  Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code.
+
+#ifndef TWIS_ASSUME_INIT_AFTER_RESET_ONLY
+#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
+#endif
+
+//  TWIS_NO_SYNC_MODE  - Remove support for synchronous mode
+
+
+//  Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources.
+
+#ifndef TWIS_NO_SYNC_MODE
+#define TWIS_NO_SYNC_MODE 0
+#endif
+
+//  TWIS_DEFAULT_CONFIG_ADDR0 - Address0
+#ifndef TWIS_DEFAULT_CONFIG_ADDR0
+#define TWIS_DEFAULT_CONFIG_ADDR0 0
+#endif
+
+//  TWIS_DEFAULT_CONFIG_ADDR1 - Address1
+#ifndef TWIS_DEFAULT_CONFIG_ADDR1
+#define TWIS_DEFAULT_CONFIG_ADDR1 0
+#endif
+
+//  TWIS_DEFAULT_CONFIG_SCL_PULL  - SCL pin pull configuration
+
+// <0=> Disabled
+// <1=> Pull down
+// <3=> Pull up
+
+#ifndef TWIS_DEFAULT_CONFIG_SCL_PULL
+#define TWIS_DEFAULT_CONFIG_SCL_PULL 0
+#endif
+
+//  TWIS_DEFAULT_CONFIG_SDA_PULL  - SDA pin pull configuration
+
+// <0=> Disabled
+// <1=> Pull down
+// <3=> Pull up
+
+#ifndef TWIS_DEFAULT_CONFIG_SDA_PULL
+#define TWIS_DEFAULT_CONFIG_SDA_PULL 0
+#endif
+
+//  TWIS_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
+#define TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+// 
+
+//  TWI_ENABLED - nrf_drv_twi - TWI/TWIM peripheral driver - legacy layer
+//==========================================================
+#ifndef TWI_ENABLED
+#define TWI_ENABLED 0
+#endif
+//  TWI_DEFAULT_CONFIG_FREQUENCY  - Frequency
+
+// <26738688=> 100k
+// <67108864=> 250k
+// <104857600=> 400k
+
+#ifndef TWI_DEFAULT_CONFIG_FREQUENCY
+#define TWI_DEFAULT_CONFIG_FREQUENCY 26738688
+#endif
+
+//  TWI_DEFAULT_CONFIG_CLR_BUS_INIT  - Enables bus clearing procedure during init
+
+
+#ifndef TWI_DEFAULT_CONFIG_CLR_BUS_INIT
+#define TWI_DEFAULT_CONFIG_CLR_BUS_INIT 0
+#endif
+
+//  TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT  - Enables bus holding after uninit
+
+
+#ifndef TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT
+#define TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0
+#endif
+
+//  TWI_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef TWI_DEFAULT_CONFIG_IRQ_PRIORITY
+#define TWI_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  TWI0_ENABLED - Enable TWI0 instance
+//==========================================================
+#ifndef TWI0_ENABLED
+#define TWI0_ENABLED 0
+#endif
+//  TWI0_USE_EASY_DMA  - Use EasyDMA (if present)
+
+
+#ifndef TWI0_USE_EASY_DMA
+#define TWI0_USE_EASY_DMA 0
+#endif
+
+// 
+
+//  TWI1_ENABLED - Enable TWI1 instance
+//==========================================================
+#ifndef TWI1_ENABLED
+#define TWI1_ENABLED 0
+#endif
+//  TWI1_USE_EASY_DMA  - Use EasyDMA (if present)
+
+
+#ifndef TWI1_USE_EASY_DMA
+#define TWI1_USE_EASY_DMA 0
+#endif
+
+// 
+
+// 
+
+//  UART_ENABLED - nrf_drv_uart - UART/UARTE peripheral driver - legacy layer
+//==========================================================
+#ifndef UART_ENABLED
+#define UART_ENABLED 0
+#endif
+//  UART_DEFAULT_CONFIG_HWFC  - Hardware Flow Control
+
+// <0=> Disabled
+// <1=> Enabled
+
+#ifndef UART_DEFAULT_CONFIG_HWFC
+#define UART_DEFAULT_CONFIG_HWFC 0
+#endif
+
+//  UART_DEFAULT_CONFIG_PARITY  - Parity
+
+// <0=> Excluded
+// <14=> Included
+
+#ifndef UART_DEFAULT_CONFIG_PARITY
+#define UART_DEFAULT_CONFIG_PARITY 0
+#endif
+
+//  UART_DEFAULT_CONFIG_BAUDRATE  - Default Baudrate
+
+// <323584=> 1200 baud
+// <643072=> 2400 baud
+// <1290240=> 4800 baud
+// <2576384=> 9600 baud
+// <3862528=> 14400 baud
+// <5152768=> 19200 baud
+// <7716864=> 28800 baud
+// <10289152=> 38400 baud
+// <15400960=> 57600 baud
+// <20615168=> 76800 baud
+// <30801920=> 115200 baud
+// <61865984=> 230400 baud
+// <67108864=> 250000 baud
+// <121634816=> 460800 baud
+// <251658240=> 921600 baud
+// <268435456=> 1000000 baud
+
+#ifndef UART_DEFAULT_CONFIG_BAUDRATE
+#define UART_DEFAULT_CONFIG_BAUDRATE 30801920
+#endif
+
+//  UART_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef UART_DEFAULT_CONFIG_IRQ_PRIORITY
+#define UART_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  UART_EASY_DMA_SUPPORT  - Driver supporting EasyDMA
+
+
+#ifndef UART_EASY_DMA_SUPPORT
+#define UART_EASY_DMA_SUPPORT 1
+#endif
+
+//  UART_LEGACY_SUPPORT  - Driver supporting Legacy mode
+
+
+#ifndef UART_LEGACY_SUPPORT
+#define UART_LEGACY_SUPPORT 1
+#endif
+
+//  UART0_ENABLED - Enable UART0 instance
+//==========================================================
+#ifndef UART0_ENABLED
+#define UART0_ENABLED 0
+#endif
+//  UART0_CONFIG_USE_EASY_DMA  - Default setting for using EasyDMA
+
+
+#ifndef UART0_CONFIG_USE_EASY_DMA
+#define UART0_CONFIG_USE_EASY_DMA 1
+#endif
+
+// 
+
+//  UART1_ENABLED - Enable UART1 instance
+//==========================================================
+#ifndef UART1_ENABLED
+#define UART1_ENABLED 0
+#endif
+// 
+
+// 
+
+//  USBD_ENABLED - nrf_drv_usbd - Software Component
+//==========================================================
+#ifndef USBD_ENABLED
+#define USBD_ENABLED 0
+#endif
+//  USBD_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef USBD_CONFIG_IRQ_PRIORITY
+#define USBD_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  USBD_CONFIG_DMASCHEDULER_MODE  - USBD SMA scheduler working scheme
+
+// <0=> Prioritized access
+// <1=> Round Robin
+
+#ifndef USBD_CONFIG_DMASCHEDULER_MODE
+#define USBD_CONFIG_DMASCHEDULER_MODE 0
+#endif
+
+//  USBD_CONFIG_DMASCHEDULER_ISO_BOOST  - Give priority to isochronous transfers
+
+
+//  This option gives priority to isochronous transfers.
+//  Enabling it assures that isochronous transfers are always processed,
+//  even if multiple other transfers are pending.
+//  Isochronous endpoints are prioritized before the usbd_dma_scheduler_algorithm
+//  function is called, so the option is independent of the algorithm chosen.
+
+#ifndef USBD_CONFIG_DMASCHEDULER_ISO_BOOST
+#define USBD_CONFIG_DMASCHEDULER_ISO_BOOST 1
+#endif
+
+//  USBD_CONFIG_ISO_IN_ZLP  - Respond to an IN token on ISO IN endpoint with ZLP when no data is ready
+
+
+//  If set, ISO IN endpoint will respond to an IN token with ZLP when no data is ready to be sent.
+//  Else, there will be no response.
+//  NOTE: This option does not work on Engineering A chip.
+
+#ifndef USBD_CONFIG_ISO_IN_ZLP
+#define USBD_CONFIG_ISO_IN_ZLP 0
+#endif
+
+// 
+
+//  WDT_ENABLED - nrf_drv_wdt - WDT peripheral driver - legacy layer
+//==========================================================
+#ifndef WDT_ENABLED
+#define WDT_ENABLED 0
+#endif
+//  WDT_CONFIG_BEHAVIOUR  - WDT behavior in CPU SLEEP or HALT mode
+
+// <1=> Run in SLEEP, Pause in HALT
+// <8=> Pause in SLEEP, Run in HALT
+// <9=> Run in SLEEP and HALT
+// <0=> Pause in SLEEP and HALT
+
+#ifndef WDT_CONFIG_BEHAVIOUR
+#define WDT_CONFIG_BEHAVIOUR 1
+#endif
+
+//  WDT_CONFIG_RELOAD_VALUE - Reload value  <15-4294967295>
+
+
+#ifndef WDT_CONFIG_RELOAD_VALUE
+#define WDT_CONFIG_RELOAD_VALUE 2000
+#endif
+
+//  WDT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef WDT_CONFIG_IRQ_PRIORITY
+#define WDT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+// 
+
+// 
+//==========================================================
+
+//  nRF_Drivers_External
+
+//==========================================================
+//  NRF_TWI_SENSOR_ENABLED  - nrf_twi_sensor - nRF TWI Sensor module
+
+
+#ifndef NRF_TWI_SENSOR_ENABLED
+#define NRF_TWI_SENSOR_ENABLED 0
+#endif
+
+// 
+//==========================================================
+
+//  nRF_Libraries
+
+//==========================================================
+//  APP_GPIOTE_ENABLED  - app_gpiote - GPIOTE events dispatcher
+
+
+#ifndef APP_GPIOTE_ENABLED
+#define APP_GPIOTE_ENABLED 0
+#endif
+
+//  APP_PWM_ENABLED  - app_pwm - PWM functionality
+
+
+#ifndef APP_PWM_ENABLED
+#define APP_PWM_ENABLED 0
+#endif
+
+//  APP_SCHEDULER_ENABLED - app_scheduler - Events scheduler
+//==========================================================
+#ifndef APP_SCHEDULER_ENABLED
+#define APP_SCHEDULER_ENABLED 0
+#endif
+//  APP_SCHEDULER_WITH_PAUSE  - Enabling pause feature
+
+
+#ifndef APP_SCHEDULER_WITH_PAUSE
+#define APP_SCHEDULER_WITH_PAUSE 0
+#endif
+
+//  APP_SCHEDULER_WITH_PROFILER  - Enabling scheduler profiling
+
+
+#ifndef APP_SCHEDULER_WITH_PROFILER
+#define APP_SCHEDULER_WITH_PROFILER 0
+#endif
+
+// 
+
+//  APP_SDCARD_ENABLED - app_sdcard - SD/MMC card support using SPI
+//==========================================================
+#ifndef APP_SDCARD_ENABLED
+#define APP_SDCARD_ENABLED 0
+#endif
+//  APP_SDCARD_SPI_INSTANCE  - SPI instance used
+
+// <0=> 0
+// <1=> 1
+// <2=> 2
+
+#ifndef APP_SDCARD_SPI_INSTANCE
+#define APP_SDCARD_SPI_INSTANCE 0
+#endif
+
+//  APP_SDCARD_FREQ_INIT  - SPI frequency
+
+// <33554432=> 125 kHz
+// <67108864=> 250 kHz
+// <134217728=> 500 kHz
+// <268435456=> 1 MHz
+// <536870912=> 2 MHz
+// <1073741824=> 4 MHz
+// <2147483648=> 8 MHz
+
+#ifndef APP_SDCARD_FREQ_INIT
+#define APP_SDCARD_FREQ_INIT 67108864
+#endif
+
+//  APP_SDCARD_FREQ_DATA  - SPI frequency
+
+// <33554432=> 125 kHz
+// <67108864=> 250 kHz
+// <134217728=> 500 kHz
+// <268435456=> 1 MHz
+// <536870912=> 2 MHz
+// <1073741824=> 4 MHz
+// <2147483648=> 8 MHz
+
+#ifndef APP_SDCARD_FREQ_DATA
+#define APP_SDCARD_FREQ_DATA 1073741824
+#endif
+
+// 
+
+//  APP_TIMER_ENABLED - app_timer - Application timer functionality
+//==========================================================
+#ifndef APP_TIMER_ENABLED
+#define APP_TIMER_ENABLED 0
+#endif
+//  APP_TIMER_CONFIG_RTC_FREQUENCY  - Configure RTC prescaler.
+
+// <0=> 32768 Hz
+// <1=> 16384 Hz
+// <3=> 8192 Hz
+// <7=> 4096 Hz
+// <15=> 2048 Hz
+// <31=> 1024 Hz
+
+#ifndef APP_TIMER_CONFIG_RTC_FREQUENCY
+#define APP_TIMER_CONFIG_RTC_FREQUENCY 1
+#endif
+
+//  APP_TIMER_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef APP_TIMER_CONFIG_IRQ_PRIORITY
+#define APP_TIMER_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  APP_TIMER_CONFIG_OP_QUEUE_SIZE - Capacity of timer requests queue.
+//  Size of the queue depends on how many timers are used
+//  in the system, how often timers are started and overall
+//  system latency. If queue size is too small app_timer calls
+//  will fail.
+
+#ifndef APP_TIMER_CONFIG_OP_QUEUE_SIZE
+#define APP_TIMER_CONFIG_OP_QUEUE_SIZE 10
+#endif
+
+//  APP_TIMER_CONFIG_USE_SCHEDULER  - Enable scheduling app_timer events to app_scheduler
+
+
+#ifndef APP_TIMER_CONFIG_USE_SCHEDULER
+#define APP_TIMER_CONFIG_USE_SCHEDULER 0
+#endif
+
+//  APP_TIMER_KEEPS_RTC_ACTIVE  - Enable RTC always on
+
+
+//  If option is enabled RTC is kept running even if there is no active timers.
+//  This option can be used when app_timer is used for timestamping.
+
+#ifndef APP_TIMER_KEEPS_RTC_ACTIVE
+#define APP_TIMER_KEEPS_RTC_ACTIVE 0
+#endif
+
+//  APP_TIMER_SAFE_WINDOW_MS - Maximum possible latency (in milliseconds) of handling app_timer event.
+//  Maximum possible timeout that can be set is reduced by safe window.
+//  Example: RTC frequency 16384 Hz, maximum possible timeout 1024 seconds - APP_TIMER_SAFE_WINDOW_MS.
+//  Since RTC is not stopped when processor is halted in debugging session, this value
+//  must cover it if debugging is needed. It is possible to halt processor for APP_TIMER_SAFE_WINDOW_MS
+//  without corrupting app_timer behavior.
+
+#ifndef APP_TIMER_SAFE_WINDOW_MS
+#define APP_TIMER_SAFE_WINDOW_MS 300000
+#endif
+
+//  App Timer Legacy configuration - Legacy configuration.
+
+//==========================================================
+//  APP_TIMER_WITH_PROFILER  - Enable app_timer profiling
+
+
+#ifndef APP_TIMER_WITH_PROFILER
+#define APP_TIMER_WITH_PROFILER 0
+#endif
+
+//  APP_TIMER_CONFIG_SWI_NUMBER  - Configure SWI instance used.
+
+
+#ifndef APP_TIMER_CONFIG_SWI_NUMBER
+#define APP_TIMER_CONFIG_SWI_NUMBER 0
+#endif
+
+// 
+//==========================================================
+
+// 
+
+//  APP_USBD_AUDIO_ENABLED  - app_usbd_audio - USB AUDIO class
+
+
+#ifndef APP_USBD_AUDIO_ENABLED
+#define APP_USBD_AUDIO_ENABLED 0
+#endif
+
+//  APP_USBD_ENABLED - app_usbd - USB Device library
+//==========================================================
+#ifndef APP_USBD_ENABLED
+#define APP_USBD_ENABLED 0
+#endif
+//  APP_USBD_VID - Vendor ID.  <0x0000-0xFFFF>
+
+
+//  Note: This value is not editable in Configuration Wizard.
+//  Vendor ID ordered from USB IF: http://www.usb.org/developers/vendor/
+
+#ifndef APP_USBD_VID
+#define APP_USBD_VID 0
+#endif
+
+//  APP_USBD_PID - Product ID.  <0x0000-0xFFFF>
+
+
+//  Note: This value is not editable in Configuration Wizard.
+//  Selected Product ID
+
+#ifndef APP_USBD_PID
+#define APP_USBD_PID 0
+#endif
+
+//  APP_USBD_DEVICE_VER_MAJOR - Major device version  <0-99>
+
+
+//  Major device version, will be converted automatically to BCD notation. Use just decimal values.
+
+#ifndef APP_USBD_DEVICE_VER_MAJOR
+#define APP_USBD_DEVICE_VER_MAJOR 1
+#endif
+
+//  APP_USBD_DEVICE_VER_MINOR - Minor device version  <0-9>
+
+
+//  Minor device version, will be converted automatically to BCD notation. Use just decimal values.
+
+#ifndef APP_USBD_DEVICE_VER_MINOR
+#define APP_USBD_DEVICE_VER_MINOR 0
+#endif
+
+//  APP_USBD_DEVICE_VER_SUB - Sub-minor device version  <0-9>
+
+
+//  Sub-minor device version, will be converted automatically to BCD notation. Use just decimal values.
+
+#ifndef APP_USBD_DEVICE_VER_SUB
+#define APP_USBD_DEVICE_VER_SUB 0
+#endif
+
+//  APP_USBD_CONFIG_SELF_POWERED  - Self-powered device, as opposed to bus-powered.
+
+
+#ifndef APP_USBD_CONFIG_SELF_POWERED
+#define APP_USBD_CONFIG_SELF_POWERED 1
+#endif
+
+//  APP_USBD_CONFIG_MAX_POWER - MaxPower field in configuration descriptor in milliamps.  <0-500>
+
+
+#ifndef APP_USBD_CONFIG_MAX_POWER
+#define APP_USBD_CONFIG_MAX_POWER 100
+#endif
+
+//  APP_USBD_CONFIG_POWER_EVENTS_PROCESS  - Process power events.
+
+
+//  Enable processing power events in USB event handler.
+
+#ifndef APP_USBD_CONFIG_POWER_EVENTS_PROCESS
+#define APP_USBD_CONFIG_POWER_EVENTS_PROCESS 1
+#endif
+
+//  APP_USBD_CONFIG_EVENT_QUEUE_ENABLE - Enable event queue.
+
+//  This is the default configuration when all the events are placed into internal queue.
+//  Disable it when an external queue is used like app_scheduler or if you wish to process all events inside interrupts.
+//  Processing all events from the interrupt level adds requirement not to call any functions that modifies the USBD library state from the context higher than USB interrupt context.
+//  Functions that modify USBD state are functions for sleep, wakeup, start, stop, enable, and disable.
+//==========================================================
+#ifndef APP_USBD_CONFIG_EVENT_QUEUE_ENABLE
+#define APP_USBD_CONFIG_EVENT_QUEUE_ENABLE 1
+#endif
+//  APP_USBD_CONFIG_EVENT_QUEUE_SIZE - The size of the event queue.  <16-64>
+
+
+//  The size of the queue for the events that would be processed in the main loop.
+
+#ifndef APP_USBD_CONFIG_EVENT_QUEUE_SIZE
+#define APP_USBD_CONFIG_EVENT_QUEUE_SIZE 32
+#endif
+
+//  APP_USBD_CONFIG_SOF_HANDLING_MODE  - Change SOF events handling mode.
+
+
+//  Normal queue   - SOF events are pushed normally into the event queue.
+//  Compress queue - SOF events are counted and binded with other events or executed when the queue is empty.
+//                   This prevents the queue from filling up with SOF events.
+//  Interrupt      - SOF events are processed in interrupt.
+// <0=> Normal queue
+// <1=> Compress queue
+// <2=> Interrupt
+
+#ifndef APP_USBD_CONFIG_SOF_HANDLING_MODE
+#define APP_USBD_CONFIG_SOF_HANDLING_MODE 1
+#endif
+
+// 
+
+//  APP_USBD_CONFIG_SOF_TIMESTAMP_PROVIDE  - Provide a function that generates timestamps for logs based on the current SOF.
+
+
+//  The function app_usbd_sof_timestamp_get is implemented if the logger is enabled.
+//  Use it when initializing the logger.
+//  SOF processing is always enabled when this configuration parameter is active.
+//  Note: This option is configured outside of APP_USBD_CONFIG_LOG_ENABLED.
+//  This means that it works even if the logging in this very module is disabled.
+
+#ifndef APP_USBD_CONFIG_SOF_TIMESTAMP_PROVIDE
+#define APP_USBD_CONFIG_SOF_TIMESTAMP_PROVIDE 0
+#endif
+
+//  APP_USBD_CONFIG_DESC_STRING_SIZE - Maximum size of the NULL-terminated string of the string descriptor.  <31-254>
+
+
+//  31 characters can be stored in the internal USB buffer used for transfers.
+//  Any value higher than 31 creates an additional buffer just for descriptor strings.
+
+#ifndef APP_USBD_CONFIG_DESC_STRING_SIZE
+#define APP_USBD_CONFIG_DESC_STRING_SIZE 31
+#endif
+
+//  APP_USBD_CONFIG_DESC_STRING_UTF_ENABLED  - Enable UTF8 conversion.
+
+
+//  Enable UTF8-encoded characters. In normal processing, only ASCII characters are available.
+
+#ifndef APP_USBD_CONFIG_DESC_STRING_UTF_ENABLED
+#define APP_USBD_CONFIG_DESC_STRING_UTF_ENABLED 0
+#endif
+
+//  APP_USBD_STRINGS_LANGIDS - Supported languages identifiers.
+
+//  Note: This value is not editable in Configuration Wizard.
+//  Comma-separated list of supported languages.
+#ifndef APP_USBD_STRINGS_LANGIDS
+#define APP_USBD_STRINGS_LANGIDS APP_USBD_LANG_AND_SUBLANG(APP_USBD_LANG_ENGLISH, APP_USBD_SUBLANG_ENGLISH_US)
+#endif
+
+//  APP_USBD_STRING_ID_MANUFACTURER - Define manufacturer string ID.
+
+//  Setting ID to 0 disables the string.
+//==========================================================
+#ifndef APP_USBD_STRING_ID_MANUFACTURER
+#define APP_USBD_STRING_ID_MANUFACTURER 1
+#endif
+//  APP_USBD_STRINGS_MANUFACTURER_EXTERN  - Define whether @ref APP_USBD_STRINGS_MANUFACTURER is created by macro or declared as a global variable.
+
+
+#ifndef APP_USBD_STRINGS_MANUFACTURER_EXTERN
+#define APP_USBD_STRINGS_MANUFACTURER_EXTERN 0
+#endif
+
+//  APP_USBD_STRINGS_MANUFACTURER - String descriptor for the manufacturer name.
+
+//  Note: This value is not editable in Configuration Wizard.
+//  Comma-separated list of manufacturer names for each defined language.
+//  Use @ref APP_USBD_STRING_DESC macro to create string descriptor from a NULL-terminated string.
+//  Use @ref APP_USBD_STRING_RAW8_DESC macro to create string descriptor from comma-separated uint8_t values.
+//  Use @ref APP_USBD_STRING_RAW16_DESC macro to create string descriptor from comma-separated uint16_t values.
+//  Alternatively, configure the macro to point to any internal variable pointer that already contains the descriptor.
+//  Setting string to NULL disables that string.
+//  The order of manufacturer names must be the same like in @ref APP_USBD_STRINGS_LANGIDS.
+#ifndef APP_USBD_STRINGS_MANUFACTURER
+#define APP_USBD_STRINGS_MANUFACTURER APP_USBD_STRING_DESC("Nordic Semiconductor")
+#endif
+
+// 
+
+//  APP_USBD_STRING_ID_PRODUCT - Define product string ID.
+
+//  Setting ID to 0 disables the string.
+//==========================================================
+#ifndef APP_USBD_STRING_ID_PRODUCT
+#define APP_USBD_STRING_ID_PRODUCT 2
+#endif
+//  APP_USBD_STRINGS_PRODUCT_EXTERN  - Define whether @ref APP_USBD_STRINGS_PRODUCT is created by macro or declared as a global variable.
+
+
+#ifndef APP_USBD_STRINGS_PRODUCT_EXTERN
+#define APP_USBD_STRINGS_PRODUCT_EXTERN 0
+#endif
+
+//  APP_USBD_STRINGS_PRODUCT - String descriptor for the product name.
+
+//  Note: This value is not editable in Configuration Wizard.
+//  List of product names that is defined the same way like in @ref APP_USBD_STRINGS_MANUFACTURER.
+#ifndef APP_USBD_STRINGS_PRODUCT
+#define APP_USBD_STRINGS_PRODUCT APP_USBD_STRING_DESC("nRF52 USB Product")
+#endif
+
+// 
+
+//  APP_USBD_STRING_ID_SERIAL - Define serial number string ID.
+
+//  Setting ID to 0 disables the string.
+//==========================================================
+#ifndef APP_USBD_STRING_ID_SERIAL
+#define APP_USBD_STRING_ID_SERIAL 3
+#endif
+//  APP_USBD_STRING_SERIAL_EXTERN  - Define whether @ref APP_USBD_STRING_SERIAL is created by macro or declared as a global variable.
+
+
+#ifndef APP_USBD_STRING_SERIAL_EXTERN
+#define APP_USBD_STRING_SERIAL_EXTERN 0
+#endif
+
+//  APP_USBD_STRING_SERIAL - String descriptor for the serial number.
+
+//  Note: This value is not editable in Configuration Wizard.
+//  Serial number that is defined the same way like in @ref APP_USBD_STRINGS_MANUFACTURER.
+#ifndef APP_USBD_STRING_SERIAL
+#define APP_USBD_STRING_SERIAL APP_USBD_STRING_DESC("000000000000")
+#endif
+
+// 
+
+//  APP_USBD_STRING_ID_CONFIGURATION - Define configuration string ID.
+
+//  Setting ID to 0 disables the string.
+//==========================================================
+#ifndef APP_USBD_STRING_ID_CONFIGURATION
+#define APP_USBD_STRING_ID_CONFIGURATION 4
+#endif
+//  APP_USBD_STRING_CONFIGURATION_EXTERN  - Define whether @ref APP_USBD_STRINGS_CONFIGURATION is created by macro or declared as global variable.
+
+
+#ifndef APP_USBD_STRING_CONFIGURATION_EXTERN
+#define APP_USBD_STRING_CONFIGURATION_EXTERN 0
+#endif
+
+//  APP_USBD_STRINGS_CONFIGURATION - String descriptor for the device configuration.
+
+//  Note: This value is not editable in Configuration Wizard.
+//  Configuration string that is defined the same way like in @ref APP_USBD_STRINGS_MANUFACTURER.
+#ifndef APP_USBD_STRINGS_CONFIGURATION
+#define APP_USBD_STRINGS_CONFIGURATION APP_USBD_STRING_DESC("Default configuration")
+#endif
+
+// 
+
+//  APP_USBD_STRINGS_USER - Default values for user strings.
+
+//  Note: This value is not editable in Configuration Wizard.
+//  This value stores all application specific user strings with the default initialization.
+//  The setup is done by X-macros.
+//  Expected macro parameters:
+//  @code
+//  X(mnemonic, [=str_idx], ...)
+//  @endcode
+//  - @c mnemonic: Mnemonic of the string descriptor that would be added to
+//                 @ref app_usbd_string_desc_idx_t enumerator.
+//  - @c str_idx : String index value, can be set or left empty.
+//                 For example, WinUSB driver requires descriptor to be present on 0xEE index.
+//                 Then use X(USBD_STRING_WINUSB, =0xEE, (APP_USBD_STRING_DESC(...)))
+//  - @c ...     : List of string descriptors for each defined language.
+#ifndef APP_USBD_STRINGS_USER
+#define APP_USBD_STRINGS_USER X(APP_USER_1, , APP_USBD_STRING_DESC("User 1"))
+#endif
+
+// 
+
+//  APP_USBD_HID_ENABLED - app_usbd_hid - USB HID class
+//==========================================================
+#ifndef APP_USBD_HID_ENABLED
+#define APP_USBD_HID_ENABLED 0
+#endif
+//  APP_USBD_HID_DEFAULT_IDLE_RATE - Default idle rate for HID class.   <0-255>
+
+
+//  0 means indefinite duration, any other value is multiplied by 4 milliseconds. Refer to Chapter 7.2.4 of HID 1.11 Specification.
+
+#ifndef APP_USBD_HID_DEFAULT_IDLE_RATE
+#define APP_USBD_HID_DEFAULT_IDLE_RATE 0
+#endif
+
+//  APP_USBD_HID_REPORT_IDLE_TABLE_SIZE - Size of idle rate table.   <1-255>
+
+
+//  Must be higher than the highest report ID used.
+
+#ifndef APP_USBD_HID_REPORT_IDLE_TABLE_SIZE
+#define APP_USBD_HID_REPORT_IDLE_TABLE_SIZE 4
+#endif
+
+// 
+
+//  APP_USBD_HID_GENERIC_ENABLED  - app_usbd_hid_generic - USB HID generic
+
+
+#ifndef APP_USBD_HID_GENERIC_ENABLED
+#define APP_USBD_HID_GENERIC_ENABLED 0
+#endif
+
+//  APP_USBD_HID_KBD_ENABLED  - app_usbd_hid_kbd - USB HID keyboard
+
+
+#ifndef APP_USBD_HID_KBD_ENABLED
+#define APP_USBD_HID_KBD_ENABLED 0
+#endif
+
+//  APP_USBD_HID_MOUSE_ENABLED  - app_usbd_hid_mouse - USB HID mouse
+
+
+#ifndef APP_USBD_HID_MOUSE_ENABLED
+#define APP_USBD_HID_MOUSE_ENABLED 0
+#endif
+
+//  APP_USBD_MSC_ENABLED  - app_usbd_msc - USB MSC class
+
+
+#ifndef APP_USBD_MSC_ENABLED
+#define APP_USBD_MSC_ENABLED 0
+#endif
+
+//  CRC16_ENABLED  - crc16 - CRC16 calculation routines
+
+
+#ifndef CRC16_ENABLED
+#define CRC16_ENABLED 0
+#endif
+
+//  CRC32_ENABLED  - crc32 - CRC32 calculation routines
+
+
+#ifndef CRC32_ENABLED
+#define CRC32_ENABLED 0
+#endif
+
+//  ECC_ENABLED  - ecc - Elliptic Curve Cryptography Library
+
+
+#ifndef ECC_ENABLED
+#define ECC_ENABLED 0
+#endif
+
+//  FDS_ENABLED - fds - Flash data storage module
+//==========================================================
+#ifndef FDS_ENABLED
+#define FDS_ENABLED 0
+#endif
+//  Pages - Virtual page settings
+
+//  Configure the number of virtual pages to use and their size.
+//==========================================================
+//  FDS_VIRTUAL_PAGES - Number of virtual flash pages to use.
+//  One of the virtual pages is reserved by the system for garbage collection.
+//  Therefore, the minimum is two virtual pages: one page to store data and one page to be used by the system for garbage collection.
+//  The total amount of flash memory that is used by FDS amounts to @ref FDS_VIRTUAL_PAGES * @ref FDS_VIRTUAL_PAGE_SIZE * 4 bytes.
+
+#ifndef FDS_VIRTUAL_PAGES
+#define FDS_VIRTUAL_PAGES 3
+#endif
+
+//  FDS_VIRTUAL_PAGE_SIZE  - The size of a virtual flash page.
+
+
+//  Expressed in number of 4-byte words.
+//  By default, a virtual page is the same size as a physical page.
+//  The size of a virtual page must be a multiple of the size of a physical page.
+// <1024=> 1024
+// <2048=> 2048
+
+#ifndef FDS_VIRTUAL_PAGE_SIZE
+#define FDS_VIRTUAL_PAGE_SIZE 1024
+#endif
+
+//  FDS_VIRTUAL_PAGES_RESERVED - The number of virtual flash pages that are used by other modules.
+//  FDS module stores its data in the last pages of the flash memory.
+//  By setting this value, you can move flash end address used by the FDS.
+//  As a result the reserved space can be used by other modules.
+
+#ifndef FDS_VIRTUAL_PAGES_RESERVED
+#define FDS_VIRTUAL_PAGES_RESERVED 0
+#endif
+
+// 
+//==========================================================
+
+//  Backend - Backend configuration
+
+//  Configure which nrf_fstorage backend is used by FDS to write to flash.
+//==========================================================
+//  FDS_BACKEND  - FDS flash backend.
+
+
+//  NRF_FSTORAGE_SD uses the nrf_fstorage_sd backend implementation using the SoftDevice API. Use this if you have a SoftDevice present.
+//  NRF_FSTORAGE_NVMC uses the nrf_fstorage_nvmc implementation. Use this setting if you don't use the SoftDevice.
+// <1=> NRF_FSTORAGE_NVMC
+// <2=> NRF_FSTORAGE_SD
+
+#ifndef FDS_BACKEND
+#define FDS_BACKEND 2
+#endif
+
+// 
+//==========================================================
+
+//  Queue - Queue settings
+
+//==========================================================
+//  FDS_OP_QUEUE_SIZE - Size of the internal queue.
+//  Increase this value if you frequently get synchronous FDS_ERR_NO_SPACE_IN_QUEUES errors.
+
+#ifndef FDS_OP_QUEUE_SIZE
+#define FDS_OP_QUEUE_SIZE 4
+#endif
+
+// 
+//==========================================================
+
+//  CRC - CRC functionality
+
+//==========================================================
+//  FDS_CRC_CHECK_ON_READ - Enable CRC checks.
+
+//  Save a record's CRC when it is written to flash and check it when the record is opened.
+//  Records with an incorrect CRC can still be 'seen' by the user using FDS functions, but they cannot be opened.
+//  Additionally, they will not be garbage collected until they are deleted.
+//==========================================================
+#ifndef FDS_CRC_CHECK_ON_READ
+#define FDS_CRC_CHECK_ON_READ 0
+#endif
+//  FDS_CRC_CHECK_ON_WRITE  - Perform a CRC check on newly written records.
+
+
+//  Perform a CRC check on newly written records.
+//  This setting can be used to make sure that the record data was not altered while being written to flash.
+// <1=> Enabled
+// <0=> Disabled
+
+#ifndef FDS_CRC_CHECK_ON_WRITE
+#define FDS_CRC_CHECK_ON_WRITE 0
+#endif
+
+// 
+
+// 
+//==========================================================
+
+//  Users - Number of users
+
+//==========================================================
+//  FDS_MAX_USERS - Maximum number of callbacks that can be registered.
+#ifndef FDS_MAX_USERS
+#define FDS_MAX_USERS 4
+#endif
+
+// 
+//==========================================================
+
+// 
+
+//  HARDFAULT_HANDLER_ENABLED  - hardfault_default - HardFault default handler for debugging and release
+
+
+#ifndef HARDFAULT_HANDLER_ENABLED
+#define HARDFAULT_HANDLER_ENABLED 0
+#endif
+
+//  HCI_MEM_POOL_ENABLED - hci_mem_pool - memory pool implementation used by HCI
+//==========================================================
+#ifndef HCI_MEM_POOL_ENABLED
+#define HCI_MEM_POOL_ENABLED 0
+#endif
+//  HCI_TX_BUF_SIZE - TX buffer size in bytes.
+#ifndef HCI_TX_BUF_SIZE
+#define HCI_TX_BUF_SIZE 600
+#endif
+
+//  HCI_RX_BUF_SIZE - RX buffer size in bytes.
+#ifndef HCI_RX_BUF_SIZE
+#define HCI_RX_BUF_SIZE 600
+#endif
+
+//  HCI_RX_BUF_QUEUE_SIZE - RX buffer queue size.
+#ifndef HCI_RX_BUF_QUEUE_SIZE
+#define HCI_RX_BUF_QUEUE_SIZE 4
+#endif
+
+// 
+
+//  HCI_SLIP_ENABLED - hci_slip - SLIP protocol implementation used by HCI
+//==========================================================
+#ifndef HCI_SLIP_ENABLED
+#define HCI_SLIP_ENABLED 0
+#endif
+//  HCI_UART_BAUDRATE  - Default Baudrate
+
+// <323584=> 1200 baud
+// <643072=> 2400 baud
+// <1290240=> 4800 baud
+// <2576384=> 9600 baud
+// <3862528=> 14400 baud
+// <5152768=> 19200 baud
+// <7716864=> 28800 baud
+// <10289152=> 38400 baud
+// <15400960=> 57600 baud
+// <20615168=> 76800 baud
+// <30801920=> 115200 baud
+// <61865984=> 230400 baud
+// <67108864=> 250000 baud
+// <121634816=> 460800 baud
+// <251658240=> 921600 baud
+// <268435456=> 1000000 baud
+
+#ifndef HCI_UART_BAUDRATE
+#define HCI_UART_BAUDRATE 30801920
+#endif
+
+//  HCI_UART_FLOW_CONTROL  - Hardware Flow Control
+
+// <0=> Disabled
+// <1=> Enabled
+
+#ifndef HCI_UART_FLOW_CONTROL
+#define HCI_UART_FLOW_CONTROL 0
+#endif
+
+//  HCI_UART_RX_PIN - UART RX pin
+#ifndef HCI_UART_RX_PIN
+#define HCI_UART_RX_PIN 31
+#endif
+
+//  HCI_UART_TX_PIN - UART TX pin
+#ifndef HCI_UART_TX_PIN
+#define HCI_UART_TX_PIN 31
+#endif
+
+//  HCI_UART_RTS_PIN - UART RTS pin
+#ifndef HCI_UART_RTS_PIN
+#define HCI_UART_RTS_PIN 31
+#endif
+
+//  HCI_UART_CTS_PIN - UART CTS pin
+#ifndef HCI_UART_CTS_PIN
+#define HCI_UART_CTS_PIN 31
+#endif
+
+// 
+
+//  HCI_TRANSPORT_ENABLED - hci_transport - HCI transport
+//==========================================================
+#ifndef HCI_TRANSPORT_ENABLED
+#define HCI_TRANSPORT_ENABLED 0
+#endif
+//  HCI_MAX_PACKET_SIZE_IN_BITS - Maximum size of a single application packet in bits.
+#ifndef HCI_MAX_PACKET_SIZE_IN_BITS
+#define HCI_MAX_PACKET_SIZE_IN_BITS 8000
+#endif
+
+// 
+
+//  LED_SOFTBLINK_ENABLED  - led_softblink - led_softblink module
+
+
+#ifndef LED_SOFTBLINK_ENABLED
+#define LED_SOFTBLINK_ENABLED 0
+#endif
+
+//  LOW_POWER_PWM_ENABLED  - low_power_pwm - low_power_pwm module
+
+
+#ifndef LOW_POWER_PWM_ENABLED
+#define LOW_POWER_PWM_ENABLED 0
+#endif
+
+//  MEM_MANAGER_ENABLED - mem_manager - Dynamic memory allocator
+//==========================================================
+#ifndef MEM_MANAGER_ENABLED
+#define MEM_MANAGER_ENABLED 0
+#endif
+//  MEMORY_MANAGER_SMALL_BLOCK_COUNT - Size of each memory blocks identified as 'small' block.  <0-255>
+
+
+#ifndef MEMORY_MANAGER_SMALL_BLOCK_COUNT
+#define MEMORY_MANAGER_SMALL_BLOCK_COUNT 1
+#endif
+
+//  MEMORY_MANAGER_SMALL_BLOCK_SIZE -  Size of each memory blocks identified as 'small' block.
+//   Size of each memory blocks identified as 'small' block. Memory block are recommended to be word-sized.
+
+#ifndef MEMORY_MANAGER_SMALL_BLOCK_SIZE
+#define MEMORY_MANAGER_SMALL_BLOCK_SIZE 32
+#endif
+
+//  MEMORY_MANAGER_MEDIUM_BLOCK_COUNT - Size of each memory blocks identified as 'medium' block.  <0-255>
+
+
+#ifndef MEMORY_MANAGER_MEDIUM_BLOCK_COUNT
+#define MEMORY_MANAGER_MEDIUM_BLOCK_COUNT 0
+#endif
+
+//  MEMORY_MANAGER_MEDIUM_BLOCK_SIZE -  Size of each memory blocks identified as 'medium' block.
+//   Size of each memory blocks identified as 'medium' block. Memory block are recommended to be word-sized.
+
+#ifndef MEMORY_MANAGER_MEDIUM_BLOCK_SIZE
+#define MEMORY_MANAGER_MEDIUM_BLOCK_SIZE 256
+#endif
+
+//  MEMORY_MANAGER_LARGE_BLOCK_COUNT - Size of each memory blocks identified as 'large' block.  <0-255>
+
+
+#ifndef MEMORY_MANAGER_LARGE_BLOCK_COUNT
+#define MEMORY_MANAGER_LARGE_BLOCK_COUNT 0
+#endif
+
+//  MEMORY_MANAGER_LARGE_BLOCK_SIZE -  Size of each memory blocks identified as 'large' block.
+//   Size of each memory blocks identified as 'large' block. Memory block are recommended to be word-sized.
+
+#ifndef MEMORY_MANAGER_LARGE_BLOCK_SIZE
+#define MEMORY_MANAGER_LARGE_BLOCK_SIZE 256
+#endif
+
+//  MEMORY_MANAGER_XLARGE_BLOCK_COUNT - Size of each memory blocks identified as 'extra large' block.  <0-255>
+
+
+#ifndef MEMORY_MANAGER_XLARGE_BLOCK_COUNT
+#define MEMORY_MANAGER_XLARGE_BLOCK_COUNT 0
+#endif
+
+//  MEMORY_MANAGER_XLARGE_BLOCK_SIZE -  Size of each memory blocks identified as 'extra large' block.
+//   Size of each memory blocks identified as 'extra large' block. Memory block are recommended to be word-sized.
+
+#ifndef MEMORY_MANAGER_XLARGE_BLOCK_SIZE
+#define MEMORY_MANAGER_XLARGE_BLOCK_SIZE 1320
+#endif
+
+//  MEMORY_MANAGER_XXLARGE_BLOCK_COUNT - Size of each memory blocks identified as 'extra extra large' block.  <0-255>
+
+
+#ifndef MEMORY_MANAGER_XXLARGE_BLOCK_COUNT
+#define MEMORY_MANAGER_XXLARGE_BLOCK_COUNT 0
+#endif
+
+//  MEMORY_MANAGER_XXLARGE_BLOCK_SIZE -  Size of each memory blocks identified as 'extra extra large' block.
+//   Size of each memory blocks identified as 'extra extra large' block. Memory block are recommended to be word-sized.
+
+#ifndef MEMORY_MANAGER_XXLARGE_BLOCK_SIZE
+#define MEMORY_MANAGER_XXLARGE_BLOCK_SIZE 3444
+#endif
+
+//  MEMORY_MANAGER_XSMALL_BLOCK_COUNT - Size of each memory blocks identified as 'extra small' block.  <0-255>
+
+
+#ifndef MEMORY_MANAGER_XSMALL_BLOCK_COUNT
+#define MEMORY_MANAGER_XSMALL_BLOCK_COUNT 0
+#endif
+
+//  MEMORY_MANAGER_XSMALL_BLOCK_SIZE -  Size of each memory blocks identified as 'extra small' block.
+//   Size of each memory blocks identified as 'extra large' block. Memory block are recommended to be word-sized.
+
+#ifndef MEMORY_MANAGER_XSMALL_BLOCK_SIZE
+#define MEMORY_MANAGER_XSMALL_BLOCK_SIZE 64
+#endif
+
+//  MEMORY_MANAGER_XXSMALL_BLOCK_COUNT - Size of each memory blocks identified as 'extra extra small' block.  <0-255>
+
+
+#ifndef MEMORY_MANAGER_XXSMALL_BLOCK_COUNT
+#define MEMORY_MANAGER_XXSMALL_BLOCK_COUNT 0
+#endif
+
+//  MEMORY_MANAGER_XXSMALL_BLOCK_SIZE -  Size of each memory blocks identified as 'extra extra small' block.
+//   Size of each memory blocks identified as 'extra extra small' block. Memory block are recommended to be word-sized.
+
+#ifndef MEMORY_MANAGER_XXSMALL_BLOCK_SIZE
+#define MEMORY_MANAGER_XXSMALL_BLOCK_SIZE 32
+#endif
+
+//  MEM_MANAGER_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef MEM_MANAGER_CONFIG_LOG_ENABLED
+#define MEM_MANAGER_CONFIG_LOG_ENABLED 0
+#endif
+//  MEM_MANAGER_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef MEM_MANAGER_CONFIG_LOG_LEVEL
+#define MEM_MANAGER_CONFIG_LOG_LEVEL 3
+#endif
+
+//  MEM_MANAGER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef MEM_MANAGER_CONFIG_INFO_COLOR
+#define MEM_MANAGER_CONFIG_INFO_COLOR 0
+#endif
+
+//  MEM_MANAGER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef MEM_MANAGER_CONFIG_DEBUG_COLOR
+#define MEM_MANAGER_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  MEM_MANAGER_DISABLE_API_PARAM_CHECK  - Disable API parameter checks in the module.
+
+
+#ifndef MEM_MANAGER_DISABLE_API_PARAM_CHECK
+#define MEM_MANAGER_DISABLE_API_PARAM_CHECK 0
+#endif
+
+// 
+
+//  NRF_BALLOC_ENABLED - nrf_balloc - Block allocator module
+//==========================================================
+#ifndef NRF_BALLOC_ENABLED
+#define NRF_BALLOC_ENABLED 1
+#endif
+//  NRF_BALLOC_CONFIG_DEBUG_ENABLED - Enables debug mode in the module.
+//==========================================================
+#ifndef NRF_BALLOC_CONFIG_DEBUG_ENABLED
+#define NRF_BALLOC_CONFIG_DEBUG_ENABLED 0
+#endif
+//  NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS - Number of words used as head guard.  <0-255>
+
+
+#ifndef NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS
+#define NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS 1
+#endif
+
+//  NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS - Number of words used as tail guard.  <0-255>
+
+
+#ifndef NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS
+#define NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS 1
+#endif
+
+//  NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED  - Enables basic checks in this module.
+
+
+#ifndef NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED
+#define NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED 0
+#endif
+
+//  NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED  - Enables double memory free check in this module.
+
+
+#ifndef NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED
+#define NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED 0
+#endif
+
+//  NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED  - Enables free memory corruption check in this module.
+
+
+#ifndef NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED
+#define NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED 0
+#endif
+
+//  NRF_BALLOC_CLI_CMDS  - Enable CLI commands specific to the module
+
+
+#ifndef NRF_BALLOC_CLI_CMDS
+#define NRF_BALLOC_CLI_CMDS 0
+#endif
+
+// 
+
+// 
+
+//  NRF_CSENSE_ENABLED - nrf_csense - Capacitive sensor module
+//==========================================================
+#ifndef NRF_CSENSE_ENABLED
+#define NRF_CSENSE_ENABLED 0
+#endif
+//  NRF_CSENSE_PAD_HYSTERESIS - Minimum value of change required to determine that a pad was touched.
+#ifndef NRF_CSENSE_PAD_HYSTERESIS
+#define NRF_CSENSE_PAD_HYSTERESIS 15
+#endif
+
+//  NRF_CSENSE_PAD_DEVIATION - Minimum value measured on a pad required to take it into account while calculating the step.
+#ifndef NRF_CSENSE_PAD_DEVIATION
+#define NRF_CSENSE_PAD_DEVIATION 70
+#endif
+
+//  NRF_CSENSE_MIN_PAD_VALUE - Minimum normalized value on a pad required to take its value into account.
+#ifndef NRF_CSENSE_MIN_PAD_VALUE
+#define NRF_CSENSE_MIN_PAD_VALUE 20
+#endif
+
+//  NRF_CSENSE_MAX_PADS_NUMBER - Maximum number of pads used for one instance.
+#ifndef NRF_CSENSE_MAX_PADS_NUMBER
+#define NRF_CSENSE_MAX_PADS_NUMBER 20
+#endif
+
+//  NRF_CSENSE_MAX_VALUE - Maximum normalized value obtained from measurement.
+#ifndef NRF_CSENSE_MAX_VALUE
+#define NRF_CSENSE_MAX_VALUE 1000
+#endif
+
+//  NRF_CSENSE_OUTPUT_PIN - Output pin used by the low-level module.
+//  This is used when capacitive sensor does not use COMP.
+
+#ifndef NRF_CSENSE_OUTPUT_PIN
+#define NRF_CSENSE_OUTPUT_PIN 26
+#endif
+
+// 
+
+//  NRF_DRV_CSENSE_ENABLED - nrf_drv_csense - Capacitive sensor low-level module
+//==========================================================
+#ifndef NRF_DRV_CSENSE_ENABLED
+#define NRF_DRV_CSENSE_ENABLED 0
+#endif
+//  USE_COMP - Use the comparator to implement the capacitive sensor driver.
+
+//  Due to Anomaly 84, COMP I_SOURCE is not functional. It has too high a varation.
+//==========================================================
+#ifndef USE_COMP
+#define USE_COMP 0
+#endif
+//  TIMER0_FOR_CSENSE - First TIMER instance used by the driver (not used on nRF51).
+#ifndef TIMER0_FOR_CSENSE
+#define TIMER0_FOR_CSENSE 1
+#endif
+
+//  TIMER1_FOR_CSENSE - Second TIMER instance used by the driver (not used on nRF51).
+#ifndef TIMER1_FOR_CSENSE
+#define TIMER1_FOR_CSENSE 2
+#endif
+
+//  MEASUREMENT_PERIOD - Single measurement period.
+//  Time of a single measurement can be calculated as
+//  T = (1/2)*MEASUREMENT_PERIOD*(1/f_OSC) where f_OSC = I_SOURCE / (2C*(VUP-VDOWN) ).
+//  I_SOURCE, VUP, and VDOWN are values used to initialize COMP and C is the capacitance of the used pad.
+
+#ifndef MEASUREMENT_PERIOD
+#define MEASUREMENT_PERIOD 20
+#endif
+
+// 
+
+// 
+
+//  NRF_FSTORAGE_ENABLED - nrf_fstorage - Flash abstraction library
+//==========================================================
+#ifndef NRF_FSTORAGE_ENABLED
+#define NRF_FSTORAGE_ENABLED 0
+#endif
+//  nrf_fstorage - Common settings
+
+//  Common settings to all fstorage implementations
+//==========================================================
+//  NRF_FSTORAGE_PARAM_CHECK_DISABLED  - Disable user input validation
+
+
+//  If selected, use ASSERT to validate user input.
+//  This effectively removes user input validation in production code.
+//  Recommended setting: OFF, only enable this setting if size is a major concern.
+
+#ifndef NRF_FSTORAGE_PARAM_CHECK_DISABLED
+#define NRF_FSTORAGE_PARAM_CHECK_DISABLED 0
+#endif
+
+// 
+//==========================================================
+
+//  nrf_fstorage_sd - Implementation using the SoftDevice
+
+//  Configuration options for the fstorage implementation using the SoftDevice
+//==========================================================
+//  NRF_FSTORAGE_SD_QUEUE_SIZE - Size of the internal queue of operations
+//  Increase this value if API calls frequently return the error @ref NRF_ERROR_NO_MEM.
+
+#ifndef NRF_FSTORAGE_SD_QUEUE_SIZE
+#define NRF_FSTORAGE_SD_QUEUE_SIZE 4
+#endif
+
+//  NRF_FSTORAGE_SD_MAX_RETRIES - Maximum number of attempts at executing an operation when the SoftDevice is busy
+//  Increase this value if events frequently return the @ref NRF_ERROR_TIMEOUT error.
+//  The SoftDevice might fail to schedule flash access due to high BLE activity.
+
+#ifndef NRF_FSTORAGE_SD_MAX_RETRIES
+#define NRF_FSTORAGE_SD_MAX_RETRIES 8
+#endif
+
+//  NRF_FSTORAGE_SD_MAX_WRITE_SIZE - Maximum number of bytes to be written to flash in a single operation
+//  This value must be a multiple of four.
+//  Lowering this value can increase the chances of the SoftDevice being able to execute flash operations in between radio activity.
+//  This value is bound by the maximum number of bytes that can be written to flash in a single call to @ref sd_flash_write.
+//  That is 1024 bytes for nRF51 ICs and 4096 bytes for nRF52 ICs.
+
+#ifndef NRF_FSTORAGE_SD_MAX_WRITE_SIZE
+#define NRF_FSTORAGE_SD_MAX_WRITE_SIZE 4096
+#endif
+
+// 
+//==========================================================
+
+// 
+
+//  NRF_GFX_ENABLED  - nrf_gfx - GFX module
+
+
+#ifndef NRF_GFX_ENABLED
+#define NRF_GFX_ENABLED 0
+#endif
+
+//  NRF_MEMOBJ_ENABLED  - nrf_memobj - Linked memory allocator module
+
+
+#ifndef NRF_MEMOBJ_ENABLED
+#define NRF_MEMOBJ_ENABLED 1
+#endif
+
+//  NRF_PWR_MGMT_ENABLED - nrf_pwr_mgmt - Power management module
+//==========================================================
+#ifndef NRF_PWR_MGMT_ENABLED
+#define NRF_PWR_MGMT_ENABLED 0
+#endif
+//  NRF_PWR_MGMT_CONFIG_DEBUG_PIN_ENABLED - Enables pin debug in the module.
+
+//  Selected pin will be set when CPU is in sleep mode.
+//==========================================================
+#ifndef NRF_PWR_MGMT_CONFIG_DEBUG_PIN_ENABLED
+#define NRF_PWR_MGMT_CONFIG_DEBUG_PIN_ENABLED 0
+#endif
+//  NRF_PWR_MGMT_SLEEP_DEBUG_PIN  - Pin number
+
+// <0=> 0 (P0.0)
+// <1=> 1 (P0.1)
+// <2=> 2 (P0.2)
+// <3=> 3 (P0.3)
+// <4=> 4 (P0.4)
+// <5=> 5 (P0.5)
+// <6=> 6 (P0.6)
+// <7=> 7 (P0.7)
+// <8=> 8 (P0.8)
+// <9=> 9 (P0.9)
+// <10=> 10 (P0.10)
+// <11=> 11 (P0.11)
+// <12=> 12 (P0.12)
+// <13=> 13 (P0.13)
+// <14=> 14 (P0.14)
+// <15=> 15 (P0.15)
+// <16=> 16 (P0.16)
+// <17=> 17 (P0.17)
+// <18=> 18 (P0.18)
+// <19=> 19 (P0.19)
+// <20=> 20 (P0.20)
+// <21=> 21 (P0.21)
+// <22=> 22 (P0.22)
+// <23=> 23 (P0.23)
+// <24=> 24 (P0.24)
+// <25=> 25 (P0.25)
+// <26=> 26 (P0.26)
+// <27=> 27 (P0.27)
+// <28=> 28 (P0.28)
+// <29=> 29 (P0.29)
+// <30=> 30 (P0.30)
+// <31=> 31 (P0.31)
+// <32=> 32 (P1.0)
+// <33=> 33 (P1.1)
+// <34=> 34 (P1.2)
+// <35=> 35 (P1.3)
+// <36=> 36 (P1.4)
+// <37=> 37 (P1.5)
+// <38=> 38 (P1.6)
+// <39=> 39 (P1.7)
+// <40=> 40 (P1.8)
+// <41=> 41 (P1.9)
+// <42=> 42 (P1.10)
+// <43=> 43 (P1.11)
+// <44=> 44 (P1.12)
+// <45=> 45 (P1.13)
+// <46=> 46 (P1.14)
+// <47=> 47 (P1.15)
+// <4294967295=> Not connected
+
+#ifndef NRF_PWR_MGMT_SLEEP_DEBUG_PIN
+#define NRF_PWR_MGMT_SLEEP_DEBUG_PIN 31
+#endif
+
+// 
+
+//  NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED  - Enables CPU usage monitor.
+
+
+//  Module will trace percentage of CPU usage in one second intervals.
+
+#ifndef NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED
+#define NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED 0
+#endif
+
+//  NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_ENABLED - Enable standby timeout.
+//==========================================================
+#ifndef NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_ENABLED
+#define NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_ENABLED 0
+#endif
+//  NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S - Standby timeout (in seconds).
+//  Shutdown procedure will begin no earlier than after this number of seconds.
+
+#ifndef NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S
+#define NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S 3
+#endif
+
+// 
+
+//  NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED  - Enables FPU event cleaning.
+
+
+#ifndef NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED
+#define NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED 0
+#endif
+
+//  NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY  - Blocked shutdown procedure will be retried every second.
+
+
+#ifndef NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY
+#define NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY 0
+#endif
+
+//  NRF_PWR_MGMT_CONFIG_USE_SCHEDULER  - Module will use @ref app_scheduler.
+
+
+#ifndef NRF_PWR_MGMT_CONFIG_USE_SCHEDULER
+#define NRF_PWR_MGMT_CONFIG_USE_SCHEDULER 0
+#endif
+
+//  NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT - The number of priorities for module handlers.
+//  The number of stages of the shutdown process.
+
+#ifndef NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT
+#define NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT 3
+#endif
+
+// 
+
+//  NRF_QUEUE_ENABLED - nrf_queue - Queue module
+//==========================================================
+#ifndef NRF_QUEUE_ENABLED
+#define NRF_QUEUE_ENABLED 0
+#endif
+//  NRF_QUEUE_CLI_CMDS  - Enable CLI commands specific to the module
+
+
+#ifndef NRF_QUEUE_CLI_CMDS
+#define NRF_QUEUE_CLI_CMDS 0
+#endif
+
+// 
+
+//  NRF_SECTION_ITER_ENABLED  - nrf_section_iter - Section iterator
+
+
+#ifndef NRF_SECTION_ITER_ENABLED
+#define NRF_SECTION_ITER_ENABLED 1
+#endif
+
+//  NRF_SORTLIST_ENABLED  - nrf_sortlist - Sorted list
+
+
+#ifndef NRF_SORTLIST_ENABLED
+#define NRF_SORTLIST_ENABLED 1
+#endif
+
+//  NRF_SPI_MNGR_ENABLED  - nrf_spi_mngr - SPI transaction manager
+
+
+#ifndef NRF_SPI_MNGR_ENABLED
+#define NRF_SPI_MNGR_ENABLED 0
+#endif
+
+//  NRF_STRERROR_ENABLED  - nrf_strerror - Library for converting error code to string.
+
+
+#ifndef NRF_STRERROR_ENABLED
+#define NRF_STRERROR_ENABLED 1
+#endif
+
+//  NRF_TWI_MNGR_ENABLED  - nrf_twi_mngr - TWI transaction manager
+
+
+#ifndef NRF_TWI_MNGR_ENABLED
+#define NRF_TWI_MNGR_ENABLED 0
+#endif
+
+//  SLIP_ENABLED  - slip - SLIP encoding and decoding
+
+
+#ifndef SLIP_ENABLED
+#define SLIP_ENABLED 0
+#endif
+
+//  TASK_MANAGER_ENABLED - task_manager - Task manager.
+//==========================================================
+#ifndef TASK_MANAGER_ENABLED
+#define TASK_MANAGER_ENABLED 0
+#endif
+//  TASK_MANAGER_CLI_CMDS  - Enable CLI commands specific to the module
+
+
+#ifndef TASK_MANAGER_CLI_CMDS
+#define TASK_MANAGER_CLI_CMDS 0
+#endif
+
+//  TASK_MANAGER_CONFIG_MAX_TASKS - Maximum number of tasks which can be created
+#ifndef TASK_MANAGER_CONFIG_MAX_TASKS
+#define TASK_MANAGER_CONFIG_MAX_TASKS 2
+#endif
+
+//  TASK_MANAGER_CONFIG_STACK_SIZE - Stack size for every task (power of 2)
+#ifndef TASK_MANAGER_CONFIG_STACK_SIZE
+#define TASK_MANAGER_CONFIG_STACK_SIZE 1024
+#endif
+
+//  TASK_MANAGER_CONFIG_STACK_PROFILER_ENABLED  - Enable stack profiling.
+
+
+#ifndef TASK_MANAGER_CONFIG_STACK_PROFILER_ENABLED
+#define TASK_MANAGER_CONFIG_STACK_PROFILER_ENABLED 1
+#endif
+
+//  TASK_MANAGER_CONFIG_STACK_GUARD  - Configures stack guard.
+
+// <0=> Disabled
+// <4=> 32 bytes
+// <5=> 64 bytes
+// <6=> 128 bytes
+// <7=> 256 bytes
+// <8=> 512 bytes
+
+#ifndef TASK_MANAGER_CONFIG_STACK_GUARD
+#define TASK_MANAGER_CONFIG_STACK_GUARD 7
+#endif
+
+// 
+
+//  app_button - buttons handling module
+
+//==========================================================
+//  BUTTON_ENABLED  - Enables Button module
+
+
+#ifndef BUTTON_ENABLED
+#define BUTTON_ENABLED 0
+#endif
+
+//  BUTTON_HIGH_ACCURACY_ENABLED  - Enables GPIOTE high accuracy for buttons
+
+
+#ifndef BUTTON_HIGH_ACCURACY_ENABLED
+#define BUTTON_HIGH_ACCURACY_ENABLED 0
+#endif
+
+// 
+//==========================================================
+
+//  app_usbd_cdc_acm - USB CDC ACM class
+
+//==========================================================
+//  APP_USBD_CDC_ACM_ENABLED  - Enabling USBD CDC ACM Class library
+
+
+#ifndef APP_USBD_CDC_ACM_ENABLED
+#define APP_USBD_CDC_ACM_ENABLED 0
+#endif
+
+//  APP_USBD_CDC_ACM_ZLP_ON_EPSIZE_WRITE  - Send ZLP on write with same size as endpoint
+
+
+//  If enabled, CDC ACM class will automatically send a zero length packet after transfer which has the same size as endpoint.
+//  This may limit throughput if a lot of binary data is sent, but in terminal mode operation it makes sure that the data is always displayed right after it is sent.
+
+#ifndef APP_USBD_CDC_ACM_ZLP_ON_EPSIZE_WRITE
+#define APP_USBD_CDC_ACM_ZLP_ON_EPSIZE_WRITE 1
+#endif
+
+// 
+//==========================================================
+
+//  nrf_cli - Command line interface
+
+//==========================================================
+//  NRF_CLI_ENABLED  - Enable/disable the CLI module.
+
+
+#ifndef NRF_CLI_ENABLED
+#define NRF_CLI_ENABLED 0
+#endif
+
+//  NRF_CLI_ARGC_MAX - Maximum number of parameters passed to the command handler.
+#ifndef NRF_CLI_ARGC_MAX
+#define NRF_CLI_ARGC_MAX 12
+#endif
+
+//  NRF_CLI_BUILD_IN_CMDS_ENABLED  - CLI built-in commands.
+
+
+#ifndef NRF_CLI_BUILD_IN_CMDS_ENABLED
+#define NRF_CLI_BUILD_IN_CMDS_ENABLED 1
+#endif
+
+//  NRF_CLI_CMD_BUFF_SIZE - Maximum buffer size for a single command.
+#ifndef NRF_CLI_CMD_BUFF_SIZE
+#define NRF_CLI_CMD_BUFF_SIZE 128
+#endif
+
+//  NRF_CLI_ECHO_STATUS  - CLI echo status. If set, echo is ON.
+
+
+#ifndef NRF_CLI_ECHO_STATUS
+#define NRF_CLI_ECHO_STATUS 1
+#endif
+
+//  NRF_CLI_WILDCARD_ENABLED  - Enable wildcard functionality for CLI commands.
+
+
+#ifndef NRF_CLI_WILDCARD_ENABLED
+#define NRF_CLI_WILDCARD_ENABLED 0
+#endif
+
+//  NRF_CLI_METAKEYS_ENABLED  - Enable additional control keys for CLI commands like ctrl+a, ctrl+e, ctrl+w, ctrl+u
+
+
+#ifndef NRF_CLI_METAKEYS_ENABLED
+#define NRF_CLI_METAKEYS_ENABLED 0
+#endif
+
+//  NRF_CLI_PRINTF_BUFF_SIZE - Maximum print buffer size.
+#ifndef NRF_CLI_PRINTF_BUFF_SIZE
+#define NRF_CLI_PRINTF_BUFF_SIZE 23
+#endif
+
+//  NRF_CLI_HISTORY_ENABLED - Enable CLI history mode.
+//==========================================================
+#ifndef NRF_CLI_HISTORY_ENABLED
+#define NRF_CLI_HISTORY_ENABLED 1
+#endif
+//  NRF_CLI_HISTORY_ELEMENT_SIZE - Size of one memory object reserved for CLI history.
+#ifndef NRF_CLI_HISTORY_ELEMENT_SIZE
+#define NRF_CLI_HISTORY_ELEMENT_SIZE 32
+#endif
+
+//  NRF_CLI_HISTORY_ELEMENT_COUNT - Number of history memory objects.
+#ifndef NRF_CLI_HISTORY_ELEMENT_COUNT
+#define NRF_CLI_HISTORY_ELEMENT_COUNT 8
+#endif
+
+// 
+
+//  NRF_CLI_VT100_COLORS_ENABLED  - CLI VT100 colors.
+
+
+#ifndef NRF_CLI_VT100_COLORS_ENABLED
+#define NRF_CLI_VT100_COLORS_ENABLED 1
+#endif
+
+//  NRF_CLI_STATISTICS_ENABLED  - Enable CLI statistics.
+
+
+#ifndef NRF_CLI_STATISTICS_ENABLED
+#define NRF_CLI_STATISTICS_ENABLED 1
+#endif
+
+//  NRF_CLI_LOG_BACKEND  - Enable logger backend interface.
+
+
+#ifndef NRF_CLI_LOG_BACKEND
+#define NRF_CLI_LOG_BACKEND 1
+#endif
+
+//  NRF_CLI_USES_TASK_MANAGER_ENABLED  - Enable CLI to use task_manager
+
+
+#ifndef NRF_CLI_USES_TASK_MANAGER_ENABLED
+#define NRF_CLI_USES_TASK_MANAGER_ENABLED 0
+#endif
+
+// 
+//==========================================================
+
+//  nrf_fprintf - fprintf function.
+
+//==========================================================
+//  NRF_FPRINTF_ENABLED  - Enable/disable fprintf module.
+
+
+#ifndef NRF_FPRINTF_ENABLED
+#define NRF_FPRINTF_ENABLED 1
+#endif
+
+//  NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF_ENABLED  - For each printed LF, function will add CR.
+
+
+#ifndef NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF_ENABLED
+#define NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF_ENABLED 1
+#endif
+
+//  NRF_FPRINTF_DOUBLE_ENABLED  - Enable IEEE-754 double precision formatting.
+
+
+#ifndef NRF_FPRINTF_DOUBLE_ENABLED
+#define NRF_FPRINTF_DOUBLE_ENABLED 0
+#endif
+
+// 
+//==========================================================
+
+// 
+//==========================================================
+
+//  nRF_Log
+
+//==========================================================
+//  NRF_LOG_ENABLED - nrf_log - Logger
+//==========================================================
+#ifndef NRF_LOG_ENABLED
+#define NRF_LOG_ENABLED 0
+#endif
+//  Log message pool - Configuration of log message pool
+
+//==========================================================
+//  NRF_LOG_MSGPOOL_ELEMENT_SIZE - Size of a single element in the pool of memory objects.
+//  If a small value is set, then performance of logs processing
+//  is degraded because data is fragmented. Bigger value impacts
+//  RAM memory utilization. The size is set to fit a message with
+//  a timestamp and up to 2 arguments in a single memory object.
+
+#ifndef NRF_LOG_MSGPOOL_ELEMENT_SIZE
+#define NRF_LOG_MSGPOOL_ELEMENT_SIZE 20
+#endif
+
+//  NRF_LOG_MSGPOOL_ELEMENT_COUNT - Number of elements in the pool of memory objects
+//  If a small value is set, then it may lead to a deadlock
+//  in certain cases if backend has high latency and holds
+//  multiple messages for long time. Bigger value impacts
+//  RAM memory usage.
+
+#ifndef NRF_LOG_MSGPOOL_ELEMENT_COUNT
+#define NRF_LOG_MSGPOOL_ELEMENT_COUNT 8
+#endif
+
+// 
+//==========================================================
+
+//  NRF_LOG_ALLOW_OVERFLOW  - Configures behavior when circular buffer is full.
+
+
+//  If set then oldest logs are overwritten. Otherwise a
+//  marker is injected informing about overflow.
+
+#ifndef NRF_LOG_ALLOW_OVERFLOW
+#define NRF_LOG_ALLOW_OVERFLOW 1
+#endif
+
+//  NRF_LOG_BUFSIZE  - Size of the buffer for storing logs (in bytes).
+
+
+//  Must be power of 2 and multiple of 4.
+//  If NRF_LOG_DEFERRED = 0 then buffer size can be reduced to minimum.
+// <128=> 128
+// <256=> 256
+// <512=> 512
+// <1024=> 1024
+// <2048=> 2048
+// <4096=> 4096
+// <8192=> 8192
+// <16384=> 16384
+
+#ifndef NRF_LOG_BUFSIZE
+#define NRF_LOG_BUFSIZE 1024
+#endif
+
+//  NRF_LOG_CLI_CMDS  - Enable CLI commands for the module.
+
+
+#ifndef NRF_LOG_CLI_CMDS
+#define NRF_LOG_CLI_CMDS 0
+#endif
+
+//  NRF_LOG_DEFAULT_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_LOG_DEFAULT_LEVEL
+#define NRF_LOG_DEFAULT_LEVEL 3
+#endif
+
+//  NRF_LOG_DEFERRED  - Enable deffered logger.
+
+
+//  Log data is buffered and can be processed in idle.
+
+#ifndef NRF_LOG_DEFERRED
+#define NRF_LOG_DEFERRED 1
+#endif
+
+//  NRF_LOG_FILTERS_ENABLED  - Enable dynamic filtering of logs.
+
+
+#ifndef NRF_LOG_FILTERS_ENABLED
+#define NRF_LOG_FILTERS_ENABLED 0
+#endif
+
+//  NRF_LOG_NON_DEFFERED_CRITICAL_REGION_ENABLED  - Enable use of critical region for non deffered mode when flushing logs.
+
+
+//  When enabled NRF_LOG_FLUSH is called from critical section when non deffered mode is used.
+//  Log output will never be corrupted as access to the log backend is exclusive
+//  but system will spend significant amount of time in critical section
+
+#ifndef NRF_LOG_NON_DEFFERED_CRITICAL_REGION_ENABLED
+#define NRF_LOG_NON_DEFFERED_CRITICAL_REGION_ENABLED 0
+#endif
+
+//  NRF_LOG_STR_PUSH_BUFFER_SIZE  - Size of the buffer dedicated for strings stored using @ref NRF_LOG_PUSH.
+
+// <16=> 16
+// <32=> 32
+// <64=> 64
+// <128=> 128
+// <256=> 256
+// <512=> 512
+// <1024=> 1024
+
+#ifndef NRF_LOG_STR_PUSH_BUFFER_SIZE
+#define NRF_LOG_STR_PUSH_BUFFER_SIZE 128
+#endif
+
+//  NRF_LOG_STR_PUSH_BUFFER_SIZE  - Size of the buffer dedicated for strings stored using @ref NRF_LOG_PUSH.
+
+// <16=> 16
+// <32=> 32
+// <64=> 64
+// <128=> 128
+// <256=> 256
+// <512=> 512
+// <1024=> 1024
+
+#ifndef NRF_LOG_STR_PUSH_BUFFER_SIZE
+#define NRF_LOG_STR_PUSH_BUFFER_SIZE 128
+#endif
+
+//  NRF_LOG_USES_COLORS - If enabled then ANSI escape code for colors is prefixed to every string
+//==========================================================
+#ifndef NRF_LOG_USES_COLORS
+#define NRF_LOG_USES_COLORS 0
+#endif
+//  NRF_LOG_COLOR_DEFAULT  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_LOG_COLOR_DEFAULT
+#define NRF_LOG_COLOR_DEFAULT 0
+#endif
+
+//  NRF_LOG_ERROR_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_LOG_ERROR_COLOR
+#define NRF_LOG_ERROR_COLOR 2
+#endif
+
+//  NRF_LOG_WARNING_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_LOG_WARNING_COLOR
+#define NRF_LOG_WARNING_COLOR 4
+#endif
+
+// 
+
+//  NRF_LOG_USES_TIMESTAMP - Enable timestamping
+
+//  Function for getting the timestamp is provided by the user
+//==========================================================
+#ifndef NRF_LOG_USES_TIMESTAMP
+#define NRF_LOG_USES_TIMESTAMP 0
+#endif
+//  NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY - Default frequency of the timestamp (in Hz) or 0 to use app_timer frequency.
+#ifndef NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY
+#define NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY 0
+#endif
+
+// 
+
+//  nrf_log module configuration
+
+//==========================================================
+//  nrf_log in nRF_Core
+
+//==========================================================
+//  NRF_MPU_LIB_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_MPU_LIB_CONFIG_LOG_ENABLED
+#define NRF_MPU_LIB_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_MPU_LIB_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_MPU_LIB_CONFIG_LOG_LEVEL
+#define NRF_MPU_LIB_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_MPU_LIB_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_MPU_LIB_CONFIG_INFO_COLOR
+#define NRF_MPU_LIB_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_MPU_LIB_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_MPU_LIB_CONFIG_DEBUG_COLOR
+#define NRF_MPU_LIB_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_STACK_GUARD_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_STACK_GUARD_CONFIG_LOG_ENABLED
+#define NRF_STACK_GUARD_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_STACK_GUARD_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_STACK_GUARD_CONFIG_LOG_LEVEL
+#define NRF_STACK_GUARD_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_STACK_GUARD_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_STACK_GUARD_CONFIG_INFO_COLOR
+#define NRF_STACK_GUARD_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_STACK_GUARD_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_STACK_GUARD_CONFIG_DEBUG_COLOR
+#define NRF_STACK_GUARD_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  TASK_MANAGER_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef TASK_MANAGER_CONFIG_LOG_ENABLED
+#define TASK_MANAGER_CONFIG_LOG_ENABLED 0
+#endif
+//  TASK_MANAGER_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef TASK_MANAGER_CONFIG_LOG_LEVEL
+#define TASK_MANAGER_CONFIG_LOG_LEVEL 3
+#endif
+
+//  TASK_MANAGER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef TASK_MANAGER_CONFIG_INFO_COLOR
+#define TASK_MANAGER_CONFIG_INFO_COLOR 0
+#endif
+
+//  TASK_MANAGER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef TASK_MANAGER_CONFIG_DEBUG_COLOR
+#define TASK_MANAGER_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+//==========================================================
+
+//  nrf_log in nRF_Drivers
+
+//==========================================================
+//  CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef CLOCK_CONFIG_LOG_ENABLED
+#define CLOCK_CONFIG_LOG_ENABLED 0
+#endif
+//  CLOCK_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef CLOCK_CONFIG_LOG_LEVEL
+#define CLOCK_CONFIG_LOG_LEVEL 3
+#endif
+
+//  CLOCK_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef CLOCK_CONFIG_INFO_COLOR
+#define CLOCK_CONFIG_INFO_COLOR 0
+#endif
+
+//  CLOCK_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef CLOCK_CONFIG_DEBUG_COLOR
+#define CLOCK_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  COMP_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef COMP_CONFIG_LOG_ENABLED
+#define COMP_CONFIG_LOG_ENABLED 0
+#endif
+//  COMP_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef COMP_CONFIG_LOG_LEVEL
+#define COMP_CONFIG_LOG_LEVEL 3
+#endif
+
+//  COMP_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef COMP_CONFIG_INFO_COLOR
+#define COMP_CONFIG_INFO_COLOR 0
+#endif
+
+//  COMP_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef COMP_CONFIG_DEBUG_COLOR
+#define COMP_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef GPIOTE_CONFIG_LOG_ENABLED
+#define GPIOTE_CONFIG_LOG_ENABLED 0
+#endif
+//  GPIOTE_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef GPIOTE_CONFIG_LOG_LEVEL
+#define GPIOTE_CONFIG_LOG_LEVEL 3
+#endif
+
+//  GPIOTE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef GPIOTE_CONFIG_INFO_COLOR
+#define GPIOTE_CONFIG_INFO_COLOR 0
+#endif
+
+//  GPIOTE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef GPIOTE_CONFIG_DEBUG_COLOR
+#define GPIOTE_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  LPCOMP_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef LPCOMP_CONFIG_LOG_ENABLED
+#define LPCOMP_CONFIG_LOG_ENABLED 0
+#endif
+//  LPCOMP_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef LPCOMP_CONFIG_LOG_LEVEL
+#define LPCOMP_CONFIG_LOG_LEVEL 3
+#endif
+
+//  LPCOMP_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef LPCOMP_CONFIG_INFO_COLOR
+#define LPCOMP_CONFIG_INFO_COLOR 0
+#endif
+
+//  LPCOMP_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef LPCOMP_CONFIG_DEBUG_COLOR
+#define LPCOMP_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  MAX3421E_HOST_CONFIG_LOG_ENABLED - Enable logging in the module
+//==========================================================
+#ifndef MAX3421E_HOST_CONFIG_LOG_ENABLED
+#define MAX3421E_HOST_CONFIG_LOG_ENABLED 0
+#endif
+//  MAX3421E_HOST_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef MAX3421E_HOST_CONFIG_LOG_LEVEL
+#define MAX3421E_HOST_CONFIG_LOG_LEVEL 3
+#endif
+
+//  MAX3421E_HOST_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef MAX3421E_HOST_CONFIG_INFO_COLOR
+#define MAX3421E_HOST_CONFIG_INFO_COLOR 0
+#endif
+
+//  MAX3421E_HOST_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef MAX3421E_HOST_CONFIG_DEBUG_COLOR
+#define MAX3421E_HOST_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRFX_USBD_CONFIG_LOG_ENABLED - Enable logging in the module
+//==========================================================
+#ifndef NRFX_USBD_CONFIG_LOG_ENABLED
+#define NRFX_USBD_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_USBD_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_USBD_CONFIG_LOG_LEVEL
+#define NRFX_USBD_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_USBD_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_USBD_CONFIG_INFO_COLOR
+#define NRFX_USBD_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_USBD_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_USBD_CONFIG_DEBUG_COLOR
+#define NRFX_USBD_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  PDM_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef PDM_CONFIG_LOG_ENABLED
+#define PDM_CONFIG_LOG_ENABLED 0
+#endif
+//  PDM_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef PDM_CONFIG_LOG_LEVEL
+#define PDM_CONFIG_LOG_LEVEL 3
+#endif
+
+//  PDM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef PDM_CONFIG_INFO_COLOR
+#define PDM_CONFIG_INFO_COLOR 0
+#endif
+
+//  PDM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef PDM_CONFIG_DEBUG_COLOR
+#define PDM_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  PPI_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef PPI_CONFIG_LOG_ENABLED
+#define PPI_CONFIG_LOG_ENABLED 0
+#endif
+//  PPI_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef PPI_CONFIG_LOG_LEVEL
+#define PPI_CONFIG_LOG_LEVEL 3
+#endif
+
+//  PPI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef PPI_CONFIG_INFO_COLOR
+#define PPI_CONFIG_INFO_COLOR 0
+#endif
+
+//  PPI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef PPI_CONFIG_DEBUG_COLOR
+#define PPI_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  PWM_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef PWM_CONFIG_LOG_ENABLED
+#define PWM_CONFIG_LOG_ENABLED 0
+#endif
+//  PWM_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef PWM_CONFIG_LOG_LEVEL
+#define PWM_CONFIG_LOG_LEVEL 3
+#endif
+
+//  PWM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef PWM_CONFIG_INFO_COLOR
+#define PWM_CONFIG_INFO_COLOR 0
+#endif
+
+//  PWM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef PWM_CONFIG_DEBUG_COLOR
+#define PWM_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  QDEC_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef QDEC_CONFIG_LOG_ENABLED
+#define QDEC_CONFIG_LOG_ENABLED 0
+#endif
+//  QDEC_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef QDEC_CONFIG_LOG_LEVEL
+#define QDEC_CONFIG_LOG_LEVEL 3
+#endif
+
+//  QDEC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef QDEC_CONFIG_INFO_COLOR
+#define QDEC_CONFIG_INFO_COLOR 0
+#endif
+
+//  QDEC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef QDEC_CONFIG_DEBUG_COLOR
+#define QDEC_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  RNG_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef RNG_CONFIG_LOG_ENABLED
+#define RNG_CONFIG_LOG_ENABLED 0
+#endif
+//  RNG_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef RNG_CONFIG_LOG_LEVEL
+#define RNG_CONFIG_LOG_LEVEL 3
+#endif
+
+//  RNG_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef RNG_CONFIG_INFO_COLOR
+#define RNG_CONFIG_INFO_COLOR 0
+#endif
+
+//  RNG_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef RNG_CONFIG_DEBUG_COLOR
+#define RNG_CONFIG_DEBUG_COLOR 0
+#endif
+
+//  RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED  - Enables logging of random numbers.
+
+
+#ifndef RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED
+#define RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED 0
+#endif
+
+// 
+
+//  RTC_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef RTC_CONFIG_LOG_ENABLED
+#define RTC_CONFIG_LOG_ENABLED 0
+#endif
+//  RTC_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef RTC_CONFIG_LOG_LEVEL
+#define RTC_CONFIG_LOG_LEVEL 3
+#endif
+
+//  RTC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef RTC_CONFIG_INFO_COLOR
+#define RTC_CONFIG_INFO_COLOR 0
+#endif
+
+//  RTC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef RTC_CONFIG_DEBUG_COLOR
+#define RTC_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  SAADC_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef SAADC_CONFIG_LOG_ENABLED
+#define SAADC_CONFIG_LOG_ENABLED 0
+#endif
+//  SAADC_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef SAADC_CONFIG_LOG_LEVEL
+#define SAADC_CONFIG_LOG_LEVEL 3
+#endif
+
+//  SAADC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef SAADC_CONFIG_INFO_COLOR
+#define SAADC_CONFIG_INFO_COLOR 0
+#endif
+
+//  SAADC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef SAADC_CONFIG_DEBUG_COLOR
+#define SAADC_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  SPIS_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef SPIS_CONFIG_LOG_ENABLED
+#define SPIS_CONFIG_LOG_ENABLED 0
+#endif
+//  SPIS_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef SPIS_CONFIG_LOG_LEVEL
+#define SPIS_CONFIG_LOG_LEVEL 3
+#endif
+
+//  SPIS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef SPIS_CONFIG_INFO_COLOR
+#define SPIS_CONFIG_INFO_COLOR 0
+#endif
+
+//  SPIS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef SPIS_CONFIG_DEBUG_COLOR
+#define SPIS_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  SPI_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef SPI_CONFIG_LOG_ENABLED
+#define SPI_CONFIG_LOG_ENABLED 0
+#endif
+//  SPI_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef SPI_CONFIG_LOG_LEVEL
+#define SPI_CONFIG_LOG_LEVEL 3
+#endif
+
+//  SPI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef SPI_CONFIG_INFO_COLOR
+#define SPI_CONFIG_INFO_COLOR 0
+#endif
+
+//  SPI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef SPI_CONFIG_DEBUG_COLOR
+#define SPI_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  TIMER_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef TIMER_CONFIG_LOG_ENABLED
+#define TIMER_CONFIG_LOG_ENABLED 0
+#endif
+//  TIMER_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef TIMER_CONFIG_LOG_LEVEL
+#define TIMER_CONFIG_LOG_LEVEL 3
+#endif
+
+//  TIMER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef TIMER_CONFIG_INFO_COLOR
+#define TIMER_CONFIG_INFO_COLOR 0
+#endif
+
+//  TIMER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef TIMER_CONFIG_DEBUG_COLOR
+#define TIMER_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  TWIS_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef TWIS_CONFIG_LOG_ENABLED
+#define TWIS_CONFIG_LOG_ENABLED 0
+#endif
+//  TWIS_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef TWIS_CONFIG_LOG_LEVEL
+#define TWIS_CONFIG_LOG_LEVEL 3
+#endif
+
+//  TWIS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef TWIS_CONFIG_INFO_COLOR
+#define TWIS_CONFIG_INFO_COLOR 0
+#endif
+
+//  TWIS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef TWIS_CONFIG_DEBUG_COLOR
+#define TWIS_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  TWI_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef TWI_CONFIG_LOG_ENABLED
+#define TWI_CONFIG_LOG_ENABLED 0
+#endif
+//  TWI_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef TWI_CONFIG_LOG_LEVEL
+#define TWI_CONFIG_LOG_LEVEL 3
+#endif
+
+//  TWI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef TWI_CONFIG_INFO_COLOR
+#define TWI_CONFIG_INFO_COLOR 0
+#endif
+
+//  TWI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef TWI_CONFIG_DEBUG_COLOR
+#define TWI_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  UART_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef UART_CONFIG_LOG_ENABLED
+#define UART_CONFIG_LOG_ENABLED 0
+#endif
+//  UART_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef UART_CONFIG_LOG_LEVEL
+#define UART_CONFIG_LOG_LEVEL 3
+#endif
+
+//  UART_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef UART_CONFIG_INFO_COLOR
+#define UART_CONFIG_INFO_COLOR 0
+#endif
+
+//  UART_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef UART_CONFIG_DEBUG_COLOR
+#define UART_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  USBD_CONFIG_LOG_ENABLED - Enable logging in the module
+//==========================================================
+#ifndef USBD_CONFIG_LOG_ENABLED
+#define USBD_CONFIG_LOG_ENABLED 0
+#endif
+//  USBD_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef USBD_CONFIG_LOG_LEVEL
+#define USBD_CONFIG_LOG_LEVEL 3
+#endif
+
+//  USBD_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef USBD_CONFIG_INFO_COLOR
+#define USBD_CONFIG_INFO_COLOR 0
+#endif
+
+//  USBD_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef USBD_CONFIG_DEBUG_COLOR
+#define USBD_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  WDT_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef WDT_CONFIG_LOG_ENABLED
+#define WDT_CONFIG_LOG_ENABLED 0
+#endif
+//  WDT_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef WDT_CONFIG_LOG_LEVEL
+#define WDT_CONFIG_LOG_LEVEL 3
+#endif
+
+//  WDT_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef WDT_CONFIG_INFO_COLOR
+#define WDT_CONFIG_INFO_COLOR 0
+#endif
+
+//  WDT_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef WDT_CONFIG_DEBUG_COLOR
+#define WDT_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+//==========================================================
+
+//  nrf_log in nRF_Libraries
+
+//==========================================================
+//  APP_BUTTON_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef APP_BUTTON_CONFIG_LOG_ENABLED
+#define APP_BUTTON_CONFIG_LOG_ENABLED 0
+#endif
+//  APP_BUTTON_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef APP_BUTTON_CONFIG_LOG_LEVEL
+#define APP_BUTTON_CONFIG_LOG_LEVEL 3
+#endif
+
+//  APP_BUTTON_CONFIG_INITIAL_LOG_LEVEL  - Initial severity level if dynamic filtering is enabled.
+
+
+//  If module generates a lot of logs, initial log level can
+//  be decreased to prevent flooding. Severity level can be
+//  increased on instance basis.
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef APP_BUTTON_CONFIG_INITIAL_LOG_LEVEL
+#define APP_BUTTON_CONFIG_INITIAL_LOG_LEVEL 3
+#endif
+
+//  APP_BUTTON_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef APP_BUTTON_CONFIG_INFO_COLOR
+#define APP_BUTTON_CONFIG_INFO_COLOR 0
+#endif
+
+//  APP_BUTTON_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef APP_BUTTON_CONFIG_DEBUG_COLOR
+#define APP_BUTTON_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  APP_TIMER_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef APP_TIMER_CONFIG_LOG_ENABLED
+#define APP_TIMER_CONFIG_LOG_ENABLED 0
+#endif
+//  APP_TIMER_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef APP_TIMER_CONFIG_LOG_LEVEL
+#define APP_TIMER_CONFIG_LOG_LEVEL 3
+#endif
+
+//  APP_TIMER_CONFIG_INITIAL_LOG_LEVEL  - Initial severity level if dynamic filtering is enabled.
+
+
+//  If module generates a lot of logs, initial log level can
+//  be decreased to prevent flooding. Severity level can be
+//  increased on instance basis.
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef APP_TIMER_CONFIG_INITIAL_LOG_LEVEL
+#define APP_TIMER_CONFIG_INITIAL_LOG_LEVEL 3
+#endif
+
+//  APP_TIMER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef APP_TIMER_CONFIG_INFO_COLOR
+#define APP_TIMER_CONFIG_INFO_COLOR 0
+#endif
+
+//  APP_TIMER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef APP_TIMER_CONFIG_DEBUG_COLOR
+#define APP_TIMER_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  APP_USBD_CDC_ACM_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef APP_USBD_CDC_ACM_CONFIG_LOG_ENABLED
+#define APP_USBD_CDC_ACM_CONFIG_LOG_ENABLED 0
+#endif
+//  APP_USBD_CDC_ACM_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef APP_USBD_CDC_ACM_CONFIG_LOG_LEVEL
+#define APP_USBD_CDC_ACM_CONFIG_LOG_LEVEL 3
+#endif
+
+//  APP_USBD_CDC_ACM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef APP_USBD_CDC_ACM_CONFIG_INFO_COLOR
+#define APP_USBD_CDC_ACM_CONFIG_INFO_COLOR 0
+#endif
+
+//  APP_USBD_CDC_ACM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef APP_USBD_CDC_ACM_CONFIG_DEBUG_COLOR
+#define APP_USBD_CDC_ACM_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  APP_USBD_CONFIG_LOG_ENABLED - Enable logging in the module.
+//==========================================================
+#ifndef APP_USBD_CONFIG_LOG_ENABLED
+#define APP_USBD_CONFIG_LOG_ENABLED 0
+#endif
+//  APP_USBD_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef APP_USBD_CONFIG_LOG_LEVEL
+#define APP_USBD_CONFIG_LOG_LEVEL 3
+#endif
+
+//  APP_USBD_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef APP_USBD_CONFIG_INFO_COLOR
+#define APP_USBD_CONFIG_INFO_COLOR 0
+#endif
+
+//  APP_USBD_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef APP_USBD_CONFIG_DEBUG_COLOR
+#define APP_USBD_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  APP_USBD_DUMMY_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef APP_USBD_DUMMY_CONFIG_LOG_ENABLED
+#define APP_USBD_DUMMY_CONFIG_LOG_ENABLED 0
+#endif
+//  APP_USBD_DUMMY_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef APP_USBD_DUMMY_CONFIG_LOG_LEVEL
+#define APP_USBD_DUMMY_CONFIG_LOG_LEVEL 3
+#endif
+
+//  APP_USBD_DUMMY_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef APP_USBD_DUMMY_CONFIG_INFO_COLOR
+#define APP_USBD_DUMMY_CONFIG_INFO_COLOR 0
+#endif
+
+//  APP_USBD_DUMMY_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef APP_USBD_DUMMY_CONFIG_DEBUG_COLOR
+#define APP_USBD_DUMMY_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  APP_USBD_MSC_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef APP_USBD_MSC_CONFIG_LOG_ENABLED
+#define APP_USBD_MSC_CONFIG_LOG_ENABLED 0
+#endif
+//  APP_USBD_MSC_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef APP_USBD_MSC_CONFIG_LOG_LEVEL
+#define APP_USBD_MSC_CONFIG_LOG_LEVEL 3
+#endif
+
+//  APP_USBD_MSC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef APP_USBD_MSC_CONFIG_INFO_COLOR
+#define APP_USBD_MSC_CONFIG_INFO_COLOR 0
+#endif
+
+//  APP_USBD_MSC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef APP_USBD_MSC_CONFIG_DEBUG_COLOR
+#define APP_USBD_MSC_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_ENABLED
+#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_ENABLED 0
+#endif
+//  APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_LEVEL
+#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_LEVEL 3
+#endif
+
+//  APP_USBD_NRF_DFU_TRIGGER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_INFO_COLOR
+#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_INFO_COLOR 0
+#endif
+
+//  APP_USBD_NRF_DFU_TRIGGER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_DEBUG_COLOR
+#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_ATFIFO_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_ATFIFO_CONFIG_LOG_ENABLED
+#define NRF_ATFIFO_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_ATFIFO_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_ATFIFO_CONFIG_LOG_LEVEL
+#define NRF_ATFIFO_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_ATFIFO_CONFIG_LOG_INIT_FILTER_LEVEL  - Initial severity level if dynamic filtering is enabled
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_ATFIFO_CONFIG_LOG_INIT_FILTER_LEVEL
+#define NRF_ATFIFO_CONFIG_LOG_INIT_FILTER_LEVEL 3
+#endif
+
+//  NRF_ATFIFO_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_ATFIFO_CONFIG_INFO_COLOR
+#define NRF_ATFIFO_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_ATFIFO_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_ATFIFO_CONFIG_DEBUG_COLOR
+#define NRF_ATFIFO_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_BALLOC_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_BALLOC_CONFIG_LOG_ENABLED
+#define NRF_BALLOC_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_BALLOC_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_BALLOC_CONFIG_LOG_LEVEL
+#define NRF_BALLOC_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL  - Initial severity level if dynamic filtering is enabled.
+
+
+//  If module generates a lot of logs, initial log level can
+//  be decreased to prevent flooding. Severity level can be
+//  increased on instance basis.
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL
+#define NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL 3
+#endif
+
+//  NRF_BALLOC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_BALLOC_CONFIG_INFO_COLOR
+#define NRF_BALLOC_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_BALLOC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_BALLOC_CONFIG_DEBUG_COLOR
+#define NRF_BALLOC_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_ENABLED
+#define NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_LEVEL
+#define NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_INIT_FILTER_LEVEL  - Initial severity level if dynamic filtering is enabled
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_INIT_FILTER_LEVEL
+#define NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_INIT_FILTER_LEVEL 3
+#endif
+
+//  NRF_BLOCK_DEV_EMPTY_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_INFO_COLOR
+#define NRF_BLOCK_DEV_EMPTY_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_BLOCK_DEV_EMPTY_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_DEBUG_COLOR
+#define NRF_BLOCK_DEV_EMPTY_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_BLOCK_DEV_QSPI_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_BLOCK_DEV_QSPI_CONFIG_LOG_ENABLED
+#define NRF_BLOCK_DEV_QSPI_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_BLOCK_DEV_QSPI_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_BLOCK_DEV_QSPI_CONFIG_LOG_LEVEL
+#define NRF_BLOCK_DEV_QSPI_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_BLOCK_DEV_QSPI_CONFIG_LOG_INIT_FILTER_LEVEL  - Initial severity level if dynamic filtering is enabled
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_BLOCK_DEV_QSPI_CONFIG_LOG_INIT_FILTER_LEVEL
+#define NRF_BLOCK_DEV_QSPI_CONFIG_LOG_INIT_FILTER_LEVEL 3
+#endif
+
+//  NRF_BLOCK_DEV_QSPI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_BLOCK_DEV_QSPI_CONFIG_INFO_COLOR
+#define NRF_BLOCK_DEV_QSPI_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_BLOCK_DEV_QSPI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_BLOCK_DEV_QSPI_CONFIG_DEBUG_COLOR
+#define NRF_BLOCK_DEV_QSPI_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_BLOCK_DEV_RAM_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_BLOCK_DEV_RAM_CONFIG_LOG_ENABLED
+#define NRF_BLOCK_DEV_RAM_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_BLOCK_DEV_RAM_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_BLOCK_DEV_RAM_CONFIG_LOG_LEVEL
+#define NRF_BLOCK_DEV_RAM_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_BLOCK_DEV_RAM_CONFIG_LOG_INIT_FILTER_LEVEL  - Initial severity level if dynamic filtering is enabled
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_BLOCK_DEV_RAM_CONFIG_LOG_INIT_FILTER_LEVEL
+#define NRF_BLOCK_DEV_RAM_CONFIG_LOG_INIT_FILTER_LEVEL 3
+#endif
+
+//  NRF_BLOCK_DEV_RAM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_BLOCK_DEV_RAM_CONFIG_INFO_COLOR
+#define NRF_BLOCK_DEV_RAM_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_BLOCK_DEV_RAM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_BLOCK_DEV_RAM_CONFIG_DEBUG_COLOR
+#define NRF_BLOCK_DEV_RAM_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_CLI_BLE_UART_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_CLI_BLE_UART_CONFIG_LOG_ENABLED
+#define NRF_CLI_BLE_UART_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_CLI_BLE_UART_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_CLI_BLE_UART_CONFIG_LOG_LEVEL
+#define NRF_CLI_BLE_UART_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_CLI_BLE_UART_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_CLI_BLE_UART_CONFIG_INFO_COLOR
+#define NRF_CLI_BLE_UART_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_CLI_BLE_UART_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_CLI_BLE_UART_CONFIG_DEBUG_COLOR
+#define NRF_CLI_BLE_UART_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_CLI_LIBUARTE_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_CLI_LIBUARTE_CONFIG_LOG_ENABLED
+#define NRF_CLI_LIBUARTE_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_CLI_LIBUARTE_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_CLI_LIBUARTE_CONFIG_LOG_LEVEL
+#define NRF_CLI_LIBUARTE_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_CLI_LIBUARTE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_CLI_LIBUARTE_CONFIG_INFO_COLOR
+#define NRF_CLI_LIBUARTE_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_CLI_LIBUARTE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_CLI_LIBUARTE_CONFIG_DEBUG_COLOR
+#define NRF_CLI_LIBUARTE_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_CLI_UART_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_CLI_UART_CONFIG_LOG_ENABLED
+#define NRF_CLI_UART_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_CLI_UART_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_CLI_UART_CONFIG_LOG_LEVEL
+#define NRF_CLI_UART_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_CLI_UART_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_CLI_UART_CONFIG_INFO_COLOR
+#define NRF_CLI_UART_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_CLI_UART_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_CLI_UART_CONFIG_DEBUG_COLOR
+#define NRF_CLI_UART_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_LIBUARTE_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_LIBUARTE_CONFIG_LOG_ENABLED
+#define NRF_LIBUARTE_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_LIBUARTE_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_LIBUARTE_CONFIG_LOG_LEVEL
+#define NRF_LIBUARTE_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_LIBUARTE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_LIBUARTE_CONFIG_INFO_COLOR
+#define NRF_LIBUARTE_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_LIBUARTE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_LIBUARTE_CONFIG_DEBUG_COLOR
+#define NRF_LIBUARTE_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_MEMOBJ_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_MEMOBJ_CONFIG_LOG_ENABLED
+#define NRF_MEMOBJ_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_MEMOBJ_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_MEMOBJ_CONFIG_LOG_LEVEL
+#define NRF_MEMOBJ_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_MEMOBJ_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_MEMOBJ_CONFIG_INFO_COLOR
+#define NRF_MEMOBJ_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_MEMOBJ_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_MEMOBJ_CONFIG_DEBUG_COLOR
+#define NRF_MEMOBJ_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_PWR_MGMT_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_PWR_MGMT_CONFIG_LOG_ENABLED
+#define NRF_PWR_MGMT_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_PWR_MGMT_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_PWR_MGMT_CONFIG_LOG_LEVEL
+#define NRF_PWR_MGMT_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_PWR_MGMT_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_PWR_MGMT_CONFIG_INFO_COLOR
+#define NRF_PWR_MGMT_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_PWR_MGMT_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_PWR_MGMT_CONFIG_DEBUG_COLOR
+#define NRF_PWR_MGMT_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_QUEUE_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_QUEUE_CONFIG_LOG_ENABLED
+#define NRF_QUEUE_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_QUEUE_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_QUEUE_CONFIG_LOG_LEVEL
+#define NRF_QUEUE_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_QUEUE_CONFIG_LOG_INIT_FILTER_LEVEL  - Initial severity level if dynamic filtering is enabled
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_QUEUE_CONFIG_LOG_INIT_FILTER_LEVEL
+#define NRF_QUEUE_CONFIG_LOG_INIT_FILTER_LEVEL 3
+#endif
+
+//  NRF_QUEUE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_QUEUE_CONFIG_INFO_COLOR
+#define NRF_QUEUE_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_QUEUE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_QUEUE_CONFIG_DEBUG_COLOR
+#define NRF_QUEUE_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_SDH_ANT_LOG_ENABLED - Enable logging in SoftDevice handler (ANT) module.
+//==========================================================
+#ifndef NRF_SDH_ANT_LOG_ENABLED
+#define NRF_SDH_ANT_LOG_ENABLED 0
+#endif
+//  NRF_SDH_ANT_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_SDH_ANT_LOG_LEVEL
+#define NRF_SDH_ANT_LOG_LEVEL 3
+#endif
+
+//  NRF_SDH_ANT_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_SDH_ANT_INFO_COLOR
+#define NRF_SDH_ANT_INFO_COLOR 0
+#endif
+
+//  NRF_SDH_ANT_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_SDH_ANT_DEBUG_COLOR
+#define NRF_SDH_ANT_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_SDH_BLE_LOG_ENABLED - Enable logging in SoftDevice handler (BLE) module.
+//==========================================================
+#ifndef NRF_SDH_BLE_LOG_ENABLED
+#define NRF_SDH_BLE_LOG_ENABLED 1
+#endif
+//  NRF_SDH_BLE_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_SDH_BLE_LOG_LEVEL
+#define NRF_SDH_BLE_LOG_LEVEL 3
+#endif
+
+//  NRF_SDH_BLE_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_SDH_BLE_INFO_COLOR
+#define NRF_SDH_BLE_INFO_COLOR 0
+#endif
+
+//  NRF_SDH_BLE_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_SDH_BLE_DEBUG_COLOR
+#define NRF_SDH_BLE_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_SDH_LOG_ENABLED - Enable logging in SoftDevice handler module.
+//==========================================================
+#ifndef NRF_SDH_LOG_ENABLED
+#define NRF_SDH_LOG_ENABLED 1
+#endif
+//  NRF_SDH_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_SDH_LOG_LEVEL
+#define NRF_SDH_LOG_LEVEL 3
+#endif
+
+//  NRF_SDH_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_SDH_INFO_COLOR
+#define NRF_SDH_INFO_COLOR 0
+#endif
+
+//  NRF_SDH_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_SDH_DEBUG_COLOR
+#define NRF_SDH_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_SDH_SOC_LOG_ENABLED - Enable logging in SoftDevice handler (SoC) module.
+//==========================================================
+#ifndef NRF_SDH_SOC_LOG_ENABLED
+#define NRF_SDH_SOC_LOG_ENABLED 1
+#endif
+//  NRF_SDH_SOC_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_SDH_SOC_LOG_LEVEL
+#define NRF_SDH_SOC_LOG_LEVEL 3
+#endif
+
+//  NRF_SDH_SOC_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_SDH_SOC_INFO_COLOR
+#define NRF_SDH_SOC_INFO_COLOR 0
+#endif
+
+//  NRF_SDH_SOC_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_SDH_SOC_DEBUG_COLOR
+#define NRF_SDH_SOC_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_SORTLIST_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_SORTLIST_CONFIG_LOG_ENABLED
+#define NRF_SORTLIST_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_SORTLIST_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_SORTLIST_CONFIG_LOG_LEVEL
+#define NRF_SORTLIST_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_SORTLIST_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_SORTLIST_CONFIG_INFO_COLOR
+#define NRF_SORTLIST_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_SORTLIST_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_SORTLIST_CONFIG_DEBUG_COLOR
+#define NRF_SORTLIST_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_TWI_SENSOR_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_TWI_SENSOR_CONFIG_LOG_ENABLED
+#define NRF_TWI_SENSOR_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_TWI_SENSOR_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_TWI_SENSOR_CONFIG_LOG_LEVEL
+#define NRF_TWI_SENSOR_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_TWI_SENSOR_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_TWI_SENSOR_CONFIG_INFO_COLOR
+#define NRF_TWI_SENSOR_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_TWI_SENSOR_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_TWI_SENSOR_CONFIG_DEBUG_COLOR
+#define NRF_TWI_SENSOR_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  PM_LOG_ENABLED - Enable logging in Peer Manager and its submodules.
+//==========================================================
+#ifndef PM_LOG_ENABLED
+#define PM_LOG_ENABLED 1
+#endif
+//  PM_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef PM_LOG_LEVEL
+#define PM_LOG_LEVEL 3
+#endif
+
+//  PM_LOG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef PM_LOG_INFO_COLOR
+#define PM_LOG_INFO_COLOR 0
+#endif
+
+//  PM_LOG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef PM_LOG_DEBUG_COLOR
+#define PM_LOG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+//==========================================================
+
+//  nrf_log in nRF_Serialization
+
+//==========================================================
+//  SER_HAL_TRANSPORT_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef SER_HAL_TRANSPORT_CONFIG_LOG_ENABLED
+#define SER_HAL_TRANSPORT_CONFIG_LOG_ENABLED 0
+#endif
+//  SER_HAL_TRANSPORT_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef SER_HAL_TRANSPORT_CONFIG_LOG_LEVEL
+#define SER_HAL_TRANSPORT_CONFIG_LOG_LEVEL 3
+#endif
+
+//  SER_HAL_TRANSPORT_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef SER_HAL_TRANSPORT_CONFIG_INFO_COLOR
+#define SER_HAL_TRANSPORT_CONFIG_INFO_COLOR 0
+#endif
+
+//  SER_HAL_TRANSPORT_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef SER_HAL_TRANSPORT_CONFIG_DEBUG_COLOR
+#define SER_HAL_TRANSPORT_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+//==========================================================
+
+// 
+//==========================================================
+
+// 
+
+//  NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED  - nrf_log_str_formatter - Log string formatter
+
+
+#ifndef NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED
+#define NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED 1
+#endif
+
+// 
+//==========================================================
+
+//  nRF_NFC
+
+//==========================================================
+//  NFC_AC_REC_ENABLED  - nfc_ac_rec - NFC NDEF Alternative Carrier record encoder
+
+
+#ifndef NFC_AC_REC_ENABLED
+#define NFC_AC_REC_ENABLED 0
+#endif
+
+//  NFC_AC_REC_PARSER_ENABLED  - nfc_ac_rec_parser - Alternative Carrier record parser
+
+
+#ifndef NFC_AC_REC_PARSER_ENABLED
+#define NFC_AC_REC_PARSER_ENABLED 0
+#endif
+
+//  NFC_BLE_OOB_ADVDATA_ENABLED - nfc_ble_oob_advdata - AD data for OOB pairing encoder
+//==========================================================
+#ifndef NFC_BLE_OOB_ADVDATA_ENABLED
+#define NFC_BLE_OOB_ADVDATA_ENABLED 0
+#endif
+//  ADVANCED_ADVDATA_SUPPORT  - Non-mandatory AD types for BLE OOB pairing are encoded inside the NDEF message (e.g. service UUIDs)
+
+// <1=> Enabled
+// <0=> Disabled
+
+#ifndef ADVANCED_ADVDATA_SUPPORT
+#define ADVANCED_ADVDATA_SUPPORT 0
+#endif
+
+// 
+
+//  NFC_BLE_OOB_ADVDATA_PARSER_ENABLED  - nfc_ble_oob_advdata_parser - BLE OOB pairing AD data parser
+
+
+#ifndef NFC_BLE_OOB_ADVDATA_PARSER_ENABLED
+#define NFC_BLE_OOB_ADVDATA_PARSER_ENABLED 0
+#endif
+
+//  NFC_BLE_PAIR_LIB_ENABLED - nfc_ble_pair_lib - Library parameters
+//==========================================================
+#ifndef NFC_BLE_PAIR_LIB_ENABLED
+#define NFC_BLE_PAIR_LIB_ENABLED 0
+#endif
+//  NFC_BLE_PAIR_LIB_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NFC_BLE_PAIR_LIB_LOG_ENABLED
+#define NFC_BLE_PAIR_LIB_LOG_ENABLED 0
+#endif
+//  NFC_BLE_PAIR_LIB_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NFC_BLE_PAIR_LIB_LOG_LEVEL
+#define NFC_BLE_PAIR_LIB_LOG_LEVEL 3
+#endif
+
+//  NFC_BLE_PAIR_LIB_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NFC_BLE_PAIR_LIB_INFO_COLOR
+#define NFC_BLE_PAIR_LIB_INFO_COLOR 0
+#endif
+
+//  NFC_BLE_PAIR_LIB_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NFC_BLE_PAIR_LIB_DEBUG_COLOR
+#define NFC_BLE_PAIR_LIB_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NFC_BLE_PAIR_LIB_SECURITY_PARAMETERS - Common Peer Manager security parameters.
+
+//==========================================================
+//  BLE_NFC_SEC_PARAM_BOND - Enables device bonding.
+
+//  If bonding is enabled at least one of the BLE_NFC_SEC_PARAM_KDIST options must be enabled.
+//==========================================================
+#ifndef BLE_NFC_SEC_PARAM_BOND
+#define BLE_NFC_SEC_PARAM_BOND 1
+#endif
+//  BLE_NFC_SEC_PARAM_KDIST_OWN_ENC  - Enables Long Term Key and Master Identification distribution by device.
+
+
+#ifndef BLE_NFC_SEC_PARAM_KDIST_OWN_ENC
+#define BLE_NFC_SEC_PARAM_KDIST_OWN_ENC 1
+#endif
+
+//  BLE_NFC_SEC_PARAM_KDIST_OWN_ID  - Enables Identity Resolving Key and Identity Address Information distribution by device.
+
+
+#ifndef BLE_NFC_SEC_PARAM_KDIST_OWN_ID
+#define BLE_NFC_SEC_PARAM_KDIST_OWN_ID 1
+#endif
+
+//  BLE_NFC_SEC_PARAM_KDIST_PEER_ENC  - Enables Long Term Key and Master Identification distribution by peer.
+
+
+#ifndef BLE_NFC_SEC_PARAM_KDIST_PEER_ENC
+#define BLE_NFC_SEC_PARAM_KDIST_PEER_ENC 1
+#endif
+
+//  BLE_NFC_SEC_PARAM_KDIST_PEER_ID  - Enables Identity Resolving Key and Identity Address Information distribution by peer.
+
+
+#ifndef BLE_NFC_SEC_PARAM_KDIST_PEER_ID
+#define BLE_NFC_SEC_PARAM_KDIST_PEER_ID 1
+#endif
+
+// 
+
+//  BLE_NFC_SEC_PARAM_MIN_KEY_SIZE  - Minimal size of a security key.
+
+// <7=> 7
+// <8=> 8
+// <9=> 9
+// <10=> 10
+// <11=> 11
+// <12=> 12
+// <13=> 13
+// <14=> 14
+// <15=> 15
+// <16=> 16
+
+#ifndef BLE_NFC_SEC_PARAM_MIN_KEY_SIZE
+#define BLE_NFC_SEC_PARAM_MIN_KEY_SIZE 7
+#endif
+
+//  BLE_NFC_SEC_PARAM_MAX_KEY_SIZE  - Maximal size of a security key.
+
+// <7=> 7
+// <8=> 8
+// <9=> 9
+// <10=> 10
+// <11=> 11
+// <12=> 12
+// <13=> 13
+// <14=> 14
+// <15=> 15
+// <16=> 16
+
+#ifndef BLE_NFC_SEC_PARAM_MAX_KEY_SIZE
+#define BLE_NFC_SEC_PARAM_MAX_KEY_SIZE 16
+#endif
+
+// 
+//==========================================================
+
+// 
+
+//  NFC_BLE_PAIR_MSG_ENABLED  - nfc_ble_pair_msg - NDEF message for OOB pairing encoder
+
+
+#ifndef NFC_BLE_PAIR_MSG_ENABLED
+#define NFC_BLE_PAIR_MSG_ENABLED 0
+#endif
+
+//  NFC_CH_COMMON_ENABLED  - nfc_ble_pair_common - OOB pairing common data
+
+
+#ifndef NFC_CH_COMMON_ENABLED
+#define NFC_CH_COMMON_ENABLED 0
+#endif
+
+//  NFC_EP_OOB_REC_ENABLED  - nfc_ep_oob_rec - EP record for BLE pairing encoder
+
+
+#ifndef NFC_EP_OOB_REC_ENABLED
+#define NFC_EP_OOB_REC_ENABLED 0
+#endif
+
+//  NFC_HS_REC_ENABLED  - nfc_hs_rec - Handover Select NDEF record encoder
+
+
+#ifndef NFC_HS_REC_ENABLED
+#define NFC_HS_REC_ENABLED 0
+#endif
+
+//  NFC_LE_OOB_REC_ENABLED  - nfc_le_oob_rec - LE record for BLE pairing encoder
+
+
+#ifndef NFC_LE_OOB_REC_ENABLED
+#define NFC_LE_OOB_REC_ENABLED 0
+#endif
+
+//  NFC_LE_OOB_REC_PARSER_ENABLED  - nfc_le_oob_rec_parser - LE record parser
+
+
+#ifndef NFC_LE_OOB_REC_PARSER_ENABLED
+#define NFC_LE_OOB_REC_PARSER_ENABLED 0
+#endif
+
+//  NFC_NDEF_LAUNCHAPP_MSG_ENABLED  - nfc_launchapp_msg - Encoding data for NDEF Application Launching message for NFC Tag
+
+
+#ifndef NFC_NDEF_LAUNCHAPP_MSG_ENABLED
+#define NFC_NDEF_LAUNCHAPP_MSG_ENABLED 0
+#endif
+
+//  NFC_NDEF_LAUNCHAPP_REC_ENABLED  - nfc_launchapp_rec - Encoding data for NDEF Application Launching record for NFC Tag
+
+
+#ifndef NFC_NDEF_LAUNCHAPP_REC_ENABLED
+#define NFC_NDEF_LAUNCHAPP_REC_ENABLED 0
+#endif
+
+//  NFC_NDEF_MSG_ENABLED - nfc_ndef_msg - NFC NDEF Message generator module
+//==========================================================
+#ifndef NFC_NDEF_MSG_ENABLED
+#define NFC_NDEF_MSG_ENABLED 0
+#endif
+//  NFC_NDEF_MSG_TAG_TYPE  - NFC Tag Type
+
+// <2=> Type 2 Tag
+// <4=> Type 4 Tag
+
+#ifndef NFC_NDEF_MSG_TAG_TYPE
+#define NFC_NDEF_MSG_TAG_TYPE 2
+#endif
+
+// 
+
+//  NFC_NDEF_MSG_PARSER_ENABLED - nfc_ndef_msg_parser - NFC NDEF message parser module
+//==========================================================
+#ifndef NFC_NDEF_MSG_PARSER_ENABLED
+#define NFC_NDEF_MSG_PARSER_ENABLED 0
+#endif
+//  NFC_NDEF_MSG_PARSER_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NFC_NDEF_MSG_PARSER_LOG_ENABLED
+#define NFC_NDEF_MSG_PARSER_LOG_ENABLED 0
+#endif
+//  NFC_NDEF_MSG_PARSER_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NFC_NDEF_MSG_PARSER_LOG_LEVEL
+#define NFC_NDEF_MSG_PARSER_LOG_LEVEL 3
+#endif
+
+//  NFC_NDEF_MSG_PARSER_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NFC_NDEF_MSG_PARSER_INFO_COLOR
+#define NFC_NDEF_MSG_PARSER_INFO_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NFC_NDEF_RECORD_ENABLED  - nfc_ndef_record - NFC NDEF Record generator module
+
+
+#ifndef NFC_NDEF_RECORD_ENABLED
+#define NFC_NDEF_RECORD_ENABLED 0
+#endif
+
+//  NFC_NDEF_RECORD_PARSER_ENABLED - nfc_ndef_record_parser - NFC NDEF Record parser module
+//==========================================================
+#ifndef NFC_NDEF_RECORD_PARSER_ENABLED
+#define NFC_NDEF_RECORD_PARSER_ENABLED 0
+#endif
+//  NFC_NDEF_RECORD_PARSER_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NFC_NDEF_RECORD_PARSER_LOG_ENABLED
+#define NFC_NDEF_RECORD_PARSER_LOG_ENABLED 0
+#endif
+//  NFC_NDEF_RECORD_PARSER_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NFC_NDEF_RECORD_PARSER_LOG_LEVEL
+#define NFC_NDEF_RECORD_PARSER_LOG_LEVEL 3
+#endif
+
+//  NFC_NDEF_RECORD_PARSER_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NFC_NDEF_RECORD_PARSER_INFO_COLOR
+#define NFC_NDEF_RECORD_PARSER_INFO_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NFC_NDEF_TEXT_RECORD_ENABLED  - nfc_text_rec - Encoding data for a text record for NFC Tag
+
+
+#ifndef NFC_NDEF_TEXT_RECORD_ENABLED
+#define NFC_NDEF_TEXT_RECORD_ENABLED 0
+#endif
+
+//  NFC_NDEF_URI_MSG_ENABLED  - nfc_uri_msg - Encoding data for NDEF message with URI record for NFC Tag
+
+
+#ifndef NFC_NDEF_URI_MSG_ENABLED
+#define NFC_NDEF_URI_MSG_ENABLED 0
+#endif
+
+//  NFC_NDEF_URI_REC_ENABLED  - nfc_uri_rec - Encoding data for a URI record for NFC Tag
+
+
+#ifndef NFC_NDEF_URI_REC_ENABLED
+#define NFC_NDEF_URI_REC_ENABLED 0
+#endif
+
+//  NFC_PLATFORM_ENABLED - nfc_platform - NFC platform module for Clock control.
+//==========================================================
+#ifndef NFC_PLATFORM_ENABLED
+#define NFC_PLATFORM_ENABLED 0
+#endif
+//  NFC_PLATFORM_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NFC_PLATFORM_LOG_ENABLED
+#define NFC_PLATFORM_LOG_ENABLED 0
+#endif
+//  NFC_PLATFORM_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NFC_PLATFORM_LOG_LEVEL
+#define NFC_PLATFORM_LOG_LEVEL 3
+#endif
+
+//  NFC_PLATFORM_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NFC_PLATFORM_INFO_COLOR
+#define NFC_PLATFORM_INFO_COLOR 0
+#endif
+
+//  NFC_PLATFORM_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NFC_PLATFORM_DEBUG_COLOR
+#define NFC_PLATFORM_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NFC_T2T_PARSER_ENABLED - nfc_type_2_tag_parser - Parser for decoding Type 2 Tag data
+//==========================================================
+#ifndef NFC_T2T_PARSER_ENABLED
+#define NFC_T2T_PARSER_ENABLED 0
+#endif
+//  NFC_T2T_PARSER_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NFC_T2T_PARSER_LOG_ENABLED
+#define NFC_T2T_PARSER_LOG_ENABLED 0
+#endif
+//  NFC_T2T_PARSER_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NFC_T2T_PARSER_LOG_LEVEL
+#define NFC_T2T_PARSER_LOG_LEVEL 3
+#endif
+
+//  NFC_T2T_PARSER_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NFC_T2T_PARSER_INFO_COLOR
+#define NFC_T2T_PARSER_INFO_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NFC_T4T_APDU_ENABLED - nfc_t4t_apdu - APDU encoder/decoder for Type 4 Tag
+//==========================================================
+#ifndef NFC_T4T_APDU_ENABLED
+#define NFC_T4T_APDU_ENABLED 0
+#endif
+//  NFC_T4T_APDU_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NFC_T4T_APDU_LOG_ENABLED
+#define NFC_T4T_APDU_LOG_ENABLED 0
+#endif
+//  NFC_T4T_APDU_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NFC_T4T_APDU_LOG_LEVEL
+#define NFC_T4T_APDU_LOG_LEVEL 3
+#endif
+
+//  NFC_T4T_APDU_LOG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NFC_T4T_APDU_LOG_COLOR
+#define NFC_T4T_APDU_LOG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NFC_T4T_CC_FILE_PARSER_ENABLED - nfc_t4t_cc_file - Capability Container file for Type 4 Tag
+//==========================================================
+#ifndef NFC_T4T_CC_FILE_PARSER_ENABLED
+#define NFC_T4T_CC_FILE_PARSER_ENABLED 0
+#endif
+//  NFC_T4T_CC_FILE_PARSER_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NFC_T4T_CC_FILE_PARSER_LOG_ENABLED
+#define NFC_T4T_CC_FILE_PARSER_LOG_ENABLED 0
+#endif
+//  NFC_T4T_CC_FILE_PARSER_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NFC_T4T_CC_FILE_PARSER_LOG_LEVEL
+#define NFC_T4T_CC_FILE_PARSER_LOG_LEVEL 3
+#endif
+
+//  NFC_T4T_CC_FILE_PARSER_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NFC_T4T_CC_FILE_PARSER_INFO_COLOR
+#define NFC_T4T_CC_FILE_PARSER_INFO_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NFC_T4T_HL_DETECTION_PROCEDURES_ENABLED - nfc_t4t_hl_detection_procedures - NDEF Detection Procedure for Type 4 Tag
+//==========================================================
+#ifndef NFC_T4T_HL_DETECTION_PROCEDURES_ENABLED
+#define NFC_T4T_HL_DETECTION_PROCEDURES_ENABLED 0
+#endif
+//  NFC_T4T_HL_DETECTION_PROCEDURES_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NFC_T4T_HL_DETECTION_PROCEDURES_LOG_ENABLED
+#define NFC_T4T_HL_DETECTION_PROCEDURES_LOG_ENABLED 0
+#endif
+//  NFC_T4T_HL_DETECTION_PROCEDURES_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NFC_T4T_HL_DETECTION_PROCEDURES_LOG_LEVEL
+#define NFC_T4T_HL_DETECTION_PROCEDURES_LOG_LEVEL 3
+#endif
+
+//  NFC_T4T_HL_DETECTION_PROCEDURES_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NFC_T4T_HL_DETECTION_PROCEDURES_INFO_COLOR
+#define NFC_T4T_HL_DETECTION_PROCEDURES_INFO_COLOR 0
+#endif
+
+// 
+
+//  APDU_BUFF_SIZE - Size (in bytes) of the buffer for APDU storage
+#ifndef APDU_BUFF_SIZE
+#define APDU_BUFF_SIZE 250
+#endif
+
+//  CC_STORAGE_BUFF_SIZE - Size (in bytes) of the buffer for CC file storage
+#ifndef CC_STORAGE_BUFF_SIZE
+#define CC_STORAGE_BUFF_SIZE 64
+#endif
+
+// 
+
+//  NFC_T4T_TLV_BLOCK_PARSER_ENABLED - nfc_t4t_tlv_block - TLV block for Type 4 Tag
+//==========================================================
+#ifndef NFC_T4T_TLV_BLOCK_PARSER_ENABLED
+#define NFC_T4T_TLV_BLOCK_PARSER_ENABLED 0
+#endif
+//  NFC_T4T_TLV_BLOCK_PARSER_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NFC_T4T_TLV_BLOCK_PARSER_LOG_ENABLED
+#define NFC_T4T_TLV_BLOCK_PARSER_LOG_ENABLED 0
+#endif
+//  NFC_T4T_TLV_BLOCK_PARSER_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NFC_T4T_TLV_BLOCK_PARSER_LOG_LEVEL
+#define NFC_T4T_TLV_BLOCK_PARSER_LOG_LEVEL 3
+#endif
+
+//  NFC_T4T_TLV_BLOCK_PARSER_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NFC_T4T_TLV_BLOCK_PARSER_INFO_COLOR
+#define NFC_T4T_TLV_BLOCK_PARSER_INFO_COLOR 0
+#endif
+
+// 
+
+// 
+
+// 
+//==========================================================
+
+//  nRF_SoftDevice
+
+//==========================================================
+//  NRF_SDH_BLE_ENABLED - nrf_sdh_ble - SoftDevice BLE event handler
+//==========================================================
+#ifndef NRF_SDH_BLE_ENABLED
+#define NRF_SDH_BLE_ENABLED 0
+#endif
+//  BLE Stack configuration - Stack configuration parameters
+
+//  The SoftDevice handler will configure the stack with these parameters when calling @ref nrf_sdh_ble_default_cfg_set.
+//  Other libraries might depend on these values; keep them up-to-date even if you are not explicitely calling @ref nrf_sdh_ble_default_cfg_set.
+//==========================================================
+//  NRF_SDH_BLE_GAP_DATA_LENGTH   <27-251>
+
+
+//  Requested BLE GAP data length to be negotiated.
+
+#ifndef NRF_SDH_BLE_GAP_DATA_LENGTH
+#define NRF_SDH_BLE_GAP_DATA_LENGTH 27
+#endif
+
+//  NRF_SDH_BLE_PERIPHERAL_LINK_COUNT - Maximum number of peripheral links.
+#ifndef NRF_SDH_BLE_PERIPHERAL_LINK_COUNT
+#define NRF_SDH_BLE_PERIPHERAL_LINK_COUNT 0
+#endif
+
+//  NRF_SDH_BLE_CENTRAL_LINK_COUNT - Maximum number of central links.
+#ifndef NRF_SDH_BLE_CENTRAL_LINK_COUNT
+#define NRF_SDH_BLE_CENTRAL_LINK_COUNT 0
+#endif
+
+//  NRF_SDH_BLE_TOTAL_LINK_COUNT - Total link count.
+//  Maximum number of total concurrent connections using the default configuration.
+
+#ifndef NRF_SDH_BLE_TOTAL_LINK_COUNT
+#define NRF_SDH_BLE_TOTAL_LINK_COUNT 1
+#endif
+
+//  NRF_SDH_BLE_GAP_EVENT_LENGTH - GAP event length.
+//  The time set aside for this connection on every connection interval in 1.25 ms units.
+
+#ifndef NRF_SDH_BLE_GAP_EVENT_LENGTH
+#define NRF_SDH_BLE_GAP_EVENT_LENGTH 6
+#endif
+
+//  NRF_SDH_BLE_GATT_MAX_MTU_SIZE - Static maximum MTU size.
+#ifndef NRF_SDH_BLE_GATT_MAX_MTU_SIZE
+#define NRF_SDH_BLE_GATT_MAX_MTU_SIZE 23
+#endif
+
+//  NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE - Attribute Table size in bytes. The size must be a multiple of 4.
+#ifndef NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE
+#define NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE 1408
+#endif
+
+//  NRF_SDH_BLE_VS_UUID_COUNT - The number of vendor-specific UUIDs.
+#ifndef NRF_SDH_BLE_VS_UUID_COUNT
+#define NRF_SDH_BLE_VS_UUID_COUNT 0
+#endif
+
+//  NRF_SDH_BLE_SERVICE_CHANGED  - Include the Service Changed characteristic in the Attribute Table.
+
+
+#ifndef NRF_SDH_BLE_SERVICE_CHANGED
+#define NRF_SDH_BLE_SERVICE_CHANGED 0
+#endif
+
+// 
+//==========================================================
+
+//  BLE Observers - Observers and priority levels
+
+//==========================================================
+//  NRF_SDH_BLE_OBSERVER_PRIO_LEVELS - Total number of priority levels for BLE observers.
+//  This setting configures the number of priority levels available for BLE event handlers.
+//  The priority level of a handler determines the order in which it receives events, with respect to other handlers.
+
+#ifndef NRF_SDH_BLE_OBSERVER_PRIO_LEVELS
+#define NRF_SDH_BLE_OBSERVER_PRIO_LEVELS 4
+#endif
+
+//  BLE Observers priorities - Invididual priorities
+
+//==========================================================
+//  BLE_ADV_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Advertising module.
+
+#ifndef BLE_ADV_BLE_OBSERVER_PRIO
+#define BLE_ADV_BLE_OBSERVER_PRIO 1
+#endif
+
+//  BLE_ANCS_C_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Apple Notification Service Client.
+
+#ifndef BLE_ANCS_C_BLE_OBSERVER_PRIO
+#define BLE_ANCS_C_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_ANS_C_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Alert Notification Service Client.
+
+#ifndef BLE_ANS_C_BLE_OBSERVER_PRIO
+#define BLE_ANS_C_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_BAS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Battery Service.
+
+#ifndef BLE_BAS_BLE_OBSERVER_PRIO
+#define BLE_BAS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_BAS_C_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Battery Service Client.
+
+#ifndef BLE_BAS_C_BLE_OBSERVER_PRIO
+#define BLE_BAS_C_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_BPS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Blood Pressure Service.
+
+#ifndef BLE_BPS_BLE_OBSERVER_PRIO
+#define BLE_BPS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_CONN_PARAMS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Connection parameters module.
+
+#ifndef BLE_CONN_PARAMS_BLE_OBSERVER_PRIO
+#define BLE_CONN_PARAMS_BLE_OBSERVER_PRIO 1
+#endif
+
+//  BLE_CONN_STATE_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Connection State module.
+
+#ifndef BLE_CONN_STATE_BLE_OBSERVER_PRIO
+#define BLE_CONN_STATE_BLE_OBSERVER_PRIO 0
+#endif
+
+//  BLE_CSCS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Cycling Speed and Cadence Service.
+
+#ifndef BLE_CSCS_BLE_OBSERVER_PRIO
+#define BLE_CSCS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_CTS_C_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Current Time Service Client.
+
+#ifndef BLE_CTS_C_BLE_OBSERVER_PRIO
+#define BLE_CTS_C_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_DB_DISC_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Database Discovery module.
+
+#ifndef BLE_DB_DISC_BLE_OBSERVER_PRIO
+#define BLE_DB_DISC_BLE_OBSERVER_PRIO 1
+#endif
+
+//  BLE_DFU_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the DFU Service.
+
+#ifndef BLE_DFU_BLE_OBSERVER_PRIO
+#define BLE_DFU_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_DIS_C_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Device Information Client.
+
+#ifndef BLE_DIS_C_BLE_OBSERVER_PRIO
+#define BLE_DIS_C_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_GLS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Glucose Service.
+
+#ifndef BLE_GLS_BLE_OBSERVER_PRIO
+#define BLE_GLS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_HIDS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Human Interface Device Service.
+
+#ifndef BLE_HIDS_BLE_OBSERVER_PRIO
+#define BLE_HIDS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_HRS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Heart Rate Service.
+
+#ifndef BLE_HRS_BLE_OBSERVER_PRIO
+#define BLE_HRS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_HRS_C_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Heart Rate Service Client.
+
+#ifndef BLE_HRS_C_BLE_OBSERVER_PRIO
+#define BLE_HRS_C_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_HTS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Health Thermometer Service.
+
+#ifndef BLE_HTS_BLE_OBSERVER_PRIO
+#define BLE_HTS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_IAS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Immediate Alert Service.
+
+#ifndef BLE_IAS_BLE_OBSERVER_PRIO
+#define BLE_IAS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_IAS_C_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Immediate Alert Service Client.
+
+#ifndef BLE_IAS_C_BLE_OBSERVER_PRIO
+#define BLE_IAS_C_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_LBS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the LED Button Service.
+
+#ifndef BLE_LBS_BLE_OBSERVER_PRIO
+#define BLE_LBS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_LBS_C_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the LED Button Service Client.
+
+#ifndef BLE_LBS_C_BLE_OBSERVER_PRIO
+#define BLE_LBS_C_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_LLS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Link Loss Service.
+
+#ifndef BLE_LLS_BLE_OBSERVER_PRIO
+#define BLE_LLS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_LNS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Location Navigation Service.
+
+#ifndef BLE_LNS_BLE_OBSERVER_PRIO
+#define BLE_LNS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_NUS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the UART Service.
+
+#ifndef BLE_NUS_BLE_OBSERVER_PRIO
+#define BLE_NUS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_NUS_C_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the UART Central Service.
+
+#ifndef BLE_NUS_C_BLE_OBSERVER_PRIO
+#define BLE_NUS_C_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_OTS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Object transfer service.
+
+#ifndef BLE_OTS_BLE_OBSERVER_PRIO
+#define BLE_OTS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_OTS_C_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Object transfer service client.
+
+#ifndef BLE_OTS_C_BLE_OBSERVER_PRIO
+#define BLE_OTS_C_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_RSCS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Running Speed and Cadence Service.
+
+#ifndef BLE_RSCS_BLE_OBSERVER_PRIO
+#define BLE_RSCS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_RSCS_C_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Running Speed and Cadence Client.
+
+#ifndef BLE_RSCS_C_BLE_OBSERVER_PRIO
+#define BLE_RSCS_C_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_TPS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the TX Power Service.
+
+#ifndef BLE_TPS_BLE_OBSERVER_PRIO
+#define BLE_TPS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BSP_BTN_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Button Control module.
+
+#ifndef BSP_BTN_BLE_OBSERVER_PRIO
+#define BSP_BTN_BLE_OBSERVER_PRIO 1
+#endif
+
+//  NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the NFC pairing library.
+
+#ifndef NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO
+#define NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO 1
+#endif
+
+//  NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the NFC pairing library.
+
+#ifndef NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO
+#define NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO 1
+#endif
+
+//  NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the NFC pairing library.
+
+#ifndef NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO
+#define NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO 1
+#endif
+
+//  NRF_BLE_BMS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Bond Management Service.
+
+#ifndef NRF_BLE_BMS_BLE_OBSERVER_PRIO
+#define NRF_BLE_BMS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  NRF_BLE_CGMS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Contiuon Glucose Monitoring Service.
+
+#ifndef NRF_BLE_CGMS_BLE_OBSERVER_PRIO
+#define NRF_BLE_CGMS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  NRF_BLE_ES_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Eddystone module.
+
+#ifndef NRF_BLE_ES_BLE_OBSERVER_PRIO
+#define NRF_BLE_ES_BLE_OBSERVER_PRIO 2
+#endif
+
+//  NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the GATT Service Client.
+
+#ifndef NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO
+#define NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO 2
+#endif
+
+//  NRF_BLE_GATT_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the GATT module.
+
+#ifndef NRF_BLE_GATT_BLE_OBSERVER_PRIO
+#define NRF_BLE_GATT_BLE_OBSERVER_PRIO 1
+#endif
+
+//  NRF_BLE_GQ_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the GATT Queue module.
+
+#ifndef NRF_BLE_GQ_BLE_OBSERVER_PRIO
+#define NRF_BLE_GQ_BLE_OBSERVER_PRIO 1
+#endif
+
+//  NRF_BLE_QWR_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Queued writes module.
+
+#ifndef NRF_BLE_QWR_BLE_OBSERVER_PRIO
+#define NRF_BLE_QWR_BLE_OBSERVER_PRIO 2
+#endif
+
+//  NRF_BLE_SCAN_OBSERVER_PRIO
+//  Priority for dispatching the BLE events to the Scanning Module.
+
+#ifndef NRF_BLE_SCAN_OBSERVER_PRIO
+#define NRF_BLE_SCAN_OBSERVER_PRIO 1
+#endif
+
+//  PM_BLE_OBSERVER_PRIO - Priority with which BLE events are dispatched to the Peer Manager module.
+#ifndef PM_BLE_OBSERVER_PRIO
+#define PM_BLE_OBSERVER_PRIO 1
+#endif
+
+// 
+//==========================================================
+
+// 
+//==========================================================
+
+
+// 
+
+//  NRF_SDH_ENABLED - nrf_sdh - SoftDevice handler
+//==========================================================
+#ifndef NRF_SDH_ENABLED
+#define NRF_SDH_ENABLED 0
+#endif
+//  Dispatch model
+
+//  This setting configures how Stack events are dispatched to the application.
+//==========================================================
+//  NRF_SDH_DISPATCH_MODEL
+
+
+//  NRF_SDH_DISPATCH_MODEL_INTERRUPT: SoftDevice events are passed to the application from the interrupt context.
+//  NRF_SDH_DISPATCH_MODEL_APPSH: SoftDevice events are scheduled using @ref app_scheduler.
+//  NRF_SDH_DISPATCH_MODEL_POLLING: SoftDevice events are to be fetched manually.
+// <0=> NRF_SDH_DISPATCH_MODEL_INTERRUPT
+// <1=> NRF_SDH_DISPATCH_MODEL_APPSH
+// <2=> NRF_SDH_DISPATCH_MODEL_POLLING
+
+#ifndef NRF_SDH_DISPATCH_MODEL
+#define NRF_SDH_DISPATCH_MODEL 0
+#endif
+
+// 
+//==========================================================
+
+//  Clock - SoftDevice clock configuration
+
+//==========================================================
+//  NRF_SDH_CLOCK_LF_SRC  - SoftDevice clock source.
+
+// <0=> NRF_CLOCK_LF_SRC_RC
+// <1=> NRF_CLOCK_LF_SRC_XTAL
+// <2=> NRF_CLOCK_LF_SRC_SYNTH
+
+#ifndef NRF_SDH_CLOCK_LF_SRC
+#define NRF_SDH_CLOCK_LF_SRC 1
+#endif
+
+//  NRF_SDH_CLOCK_LF_RC_CTIV - SoftDevice calibration timer interval.
+#ifndef NRF_SDH_CLOCK_LF_RC_CTIV
+#define NRF_SDH_CLOCK_LF_RC_CTIV 0
+#endif
+
+//  NRF_SDH_CLOCK_LF_RC_TEMP_CTIV - SoftDevice calibration timer interval under constant temperature.
+//  How often (in number of calibration intervals) the RC oscillator shall be calibrated
+//   if the temperature has not changed.
+
+#ifndef NRF_SDH_CLOCK_LF_RC_TEMP_CTIV
+#define NRF_SDH_CLOCK_LF_RC_TEMP_CTIV 0
+#endif
+
+//  NRF_SDH_CLOCK_LF_ACCURACY  - External clock accuracy used in the LL to compute timing.
+
+// <0=> NRF_CLOCK_LF_ACCURACY_250_PPM
+// <1=> NRF_CLOCK_LF_ACCURACY_500_PPM
+// <2=> NRF_CLOCK_LF_ACCURACY_150_PPM
+// <3=> NRF_CLOCK_LF_ACCURACY_100_PPM
+// <4=> NRF_CLOCK_LF_ACCURACY_75_PPM
+// <5=> NRF_CLOCK_LF_ACCURACY_50_PPM
+// <6=> NRF_CLOCK_LF_ACCURACY_30_PPM
+// <7=> NRF_CLOCK_LF_ACCURACY_20_PPM
+// <8=> NRF_CLOCK_LF_ACCURACY_10_PPM
+// <9=> NRF_CLOCK_LF_ACCURACY_5_PPM
+// <10=> NRF_CLOCK_LF_ACCURACY_2_PPM
+// <11=> NRF_CLOCK_LF_ACCURACY_1_PPM
+
+#ifndef NRF_SDH_CLOCK_LF_ACCURACY
+#define NRF_SDH_CLOCK_LF_ACCURACY 7
+#endif
+
+// 
+//==========================================================
+
+//  SDH Observers - Observers and priority levels
+
+//==========================================================
+//  NRF_SDH_REQ_OBSERVER_PRIO_LEVELS - Total number of priority levels for request observers.
+//  This setting configures the number of priority levels available for the SoftDevice request event handlers.
+//  The priority level of a handler determines the order in which it receives events, with respect to other handlers.
+
+#ifndef NRF_SDH_REQ_OBSERVER_PRIO_LEVELS
+#define NRF_SDH_REQ_OBSERVER_PRIO_LEVELS 2
+#endif
+
+//  NRF_SDH_STATE_OBSERVER_PRIO_LEVELS - Total number of priority levels for state observers.
+//  This setting configures the number of priority levels available for the SoftDevice state event handlers.
+//  The priority level of a handler determines the order in which it receives events, with respect to other handlers.
+
+#ifndef NRF_SDH_STATE_OBSERVER_PRIO_LEVELS
+#define NRF_SDH_STATE_OBSERVER_PRIO_LEVELS 2
+#endif
+
+//  NRF_SDH_STACK_OBSERVER_PRIO_LEVELS - Total number of priority levels for stack event observers.
+//  This setting configures the number of priority levels available for the SoftDevice stack event handlers (ANT, BLE, SoC).
+//  The priority level of a handler determines the order in which it receives events, with respect to other handlers.
+
+#ifndef NRF_SDH_STACK_OBSERVER_PRIO_LEVELS
+#define NRF_SDH_STACK_OBSERVER_PRIO_LEVELS 2
+#endif
+
+
+//  State Observers priorities - Invididual priorities
+
+//==========================================================
+//  CLOCK_CONFIG_STATE_OBSERVER_PRIO
+//  Priority with which state events are dispatched to the Clock driver.
+
+#ifndef CLOCK_CONFIG_STATE_OBSERVER_PRIO
+#define CLOCK_CONFIG_STATE_OBSERVER_PRIO 0
+#endif
+
+//  POWER_CONFIG_STATE_OBSERVER_PRIO
+//  Priority with which state events are dispatched to the Power driver.
+
+#ifndef POWER_CONFIG_STATE_OBSERVER_PRIO
+#define POWER_CONFIG_STATE_OBSERVER_PRIO 0
+#endif
+
+//  RNG_CONFIG_STATE_OBSERVER_PRIO
+//  Priority with which state events are dispatched to this module.
+
+#ifndef RNG_CONFIG_STATE_OBSERVER_PRIO
+#define RNG_CONFIG_STATE_OBSERVER_PRIO 0
+#endif
+
+// 
+//==========================================================
+
+//  Stack Event Observers priorities - Invididual priorities
+
+//==========================================================
+//  NRF_SDH_ANT_STACK_OBSERVER_PRIO
+//  This setting configures the priority with which ANT events are processed with respect to other events coming from the stack.
+//  Modify this setting if you need to have ANT events dispatched before or after other stack events, such as BLE or SoC.
+//  Zero is the highest priority.
+
+#ifndef NRF_SDH_ANT_STACK_OBSERVER_PRIO
+#define NRF_SDH_ANT_STACK_OBSERVER_PRIO 0
+#endif
+
+//  NRF_SDH_BLE_STACK_OBSERVER_PRIO
+//  This setting configures the priority with which BLE events are processed with respect to other events coming from the stack.
+//  Modify this setting if you need to have BLE events dispatched before or after other stack events, such as ANT or SoC.
+//  Zero is the highest priority.
+
+#ifndef NRF_SDH_BLE_STACK_OBSERVER_PRIO
+#define NRF_SDH_BLE_STACK_OBSERVER_PRIO 0
+#endif
+
+//  NRF_SDH_SOC_STACK_OBSERVER_PRIO
+//  This setting configures the priority with which SoC events are processed with respect to other events coming from the stack.
+//  Modify this setting if you need to have SoC events dispatched before or after other stack events, such as ANT or BLE.
+//  Zero is the highest priority.
+
+#ifndef NRF_SDH_SOC_STACK_OBSERVER_PRIO
+#define NRF_SDH_SOC_STACK_OBSERVER_PRIO 0
+#endif
+
+// 
+//==========================================================
+
+// 
+//==========================================================
+
+
+// 
+
+//  NRF_SDH_SOC_ENABLED - nrf_sdh_soc - SoftDevice SoC event handler
+//==========================================================
+#ifndef NRF_SDH_SOC_ENABLED
+#define NRF_SDH_SOC_ENABLED 0
+#endif
+//  SoC Observers - Observers and priority levels
+
+//==========================================================
+//  NRF_SDH_SOC_OBSERVER_PRIO_LEVELS - Total number of priority levels for SoC observers.
+//  This setting configures the number of priority levels available for the SoC event handlers.
+//  The priority level of a handler determines the order in which it receives events, with respect to other handlers.
+
+#ifndef NRF_SDH_SOC_OBSERVER_PRIO_LEVELS
+#define NRF_SDH_SOC_OBSERVER_PRIO_LEVELS 2
+#endif
+
+//  SoC Observers priorities - Invididual priorities
+
+//==========================================================
+//  BLE_DFU_SOC_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the DFU Service.
+
+#ifndef BLE_DFU_SOC_OBSERVER_PRIO
+#define BLE_DFU_SOC_OBSERVER_PRIO 1
+#endif
+
+//  CLOCK_CONFIG_SOC_OBSERVER_PRIO
+//  Priority with which SoC events are dispatched to the Clock driver.
+
+#ifndef CLOCK_CONFIG_SOC_OBSERVER_PRIO
+#define CLOCK_CONFIG_SOC_OBSERVER_PRIO 0
+#endif
+
+//  POWER_CONFIG_SOC_OBSERVER_PRIO
+//  Priority with which SoC events are dispatched to the Power driver.
+
+#ifndef POWER_CONFIG_SOC_OBSERVER_PRIO
+#define POWER_CONFIG_SOC_OBSERVER_PRIO 0
+#endif
+
+// 
+//==========================================================
+
+// 
+//==========================================================
+
+//  NRFX_NVMC_ENABLED - nrfx_nvmc - NVMC peripheral driver
+//==========================================================
+#ifndef NRFX_NVMC_ENABLED
+#define NRFX_NVMC_ENABLED 1
+#endif
+// 
+
+//==========================================================
+#ifndef NRFX_SYSTICK_ENABLED
+#define NRFX_SYSTICK_ENABLED 1
+#endif
+// <<< end of configuration section >>>
+#endif //SDK_CONFIG_H
+
diff --git a/bsp/nrf5x/libraries/templates/nrf52x/project.uvoptx b/bsp/nrf5x/libraries/templates/nrfx/project.uvoptx
similarity index 74%
rename from bsp/nrf5x/libraries/templates/nrf52x/project.uvoptx
rename to bsp/nrf5x/libraries/templates/nrfx/project.uvoptx
index 4ce3d63283..b65395593c 100644
--- a/bsp/nrf5x/libraries/templates/nrf52x/project.uvoptx
+++ b/bsp/nrf5x/libraries/templates/nrfx/project.uvoptx
@@ -120,12 +120,12 @@
         
           0
           JL2CM3
-          -U59401765 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF52832_xxAA$Flash\nrf52xxx.flm) -FF1nrf52xxx_uicr.flm -FS110001000 -FL11000 -FP1($$Device:nRF52832_xxAA$Flash\nrf52xxx_uicr.flm)
+          -U683349164 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FF1nrf52xxx_uicr.flm -FS110001000 -FL11000 -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm)
         
         
           0
           UL2CM3
-          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx -FS00 -FL0200000 -FF1nrf52xxx_uicr -FS110001000 -FL11000 -FP0($$Device:nRF52832_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52832_xxAA$Flash\nrf52xxx_uicr.flm))
+          UL2CM3(-S0 -C0 -P0 )  -FN2 -FC4000 -FD20000000 -FF0nrf52xxx -FF1nrf52xxx_uicr -FL0200000 -FL11000 -FS00 -FS110001000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm)
         
       
       
@@ -171,12 +171,19 @@
       
       
       
+      
+        1
+        1
+        0
+        2
+        10000000
+      
     
   
 
   
-    Kernel
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diff --git a/bsp/nrf5x/libraries/templates/nrf52x/project.uvprojx b/bsp/nrf5x/libraries/templates/nrfx/project.uvprojx
similarity index 72%
rename from bsp/nrf5x/libraries/templates/nrf52x/project.uvprojx
rename to bsp/nrf5x/libraries/templates/nrfx/project.uvprojx
index 5289463556..991a9de5f4 100644
--- a/bsp/nrf5x/libraries/templates/nrf52x/project.uvprojx
+++ b/bsp/nrf5x/libraries/templates/nrfx/project.uvprojx
@@ -14,16 +14,16 @@
       0
       
         
-          nRF52832_xxAA
+          nRF52840_xxAA
           Nordic Semiconductor
-          NordicSemiconductor.nRF_DeviceFamilyPack.8.31.0
+          NordicSemiconductor.nRF_DeviceFamilyPack.8.38.0
           http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/
-          IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE
+          IRAM(0x20000000,0x40000) IROM(0x00000000,0x100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE
           
           
-          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx -FS00 -FL0200000 -FF1nrf52xxx_uicr -FS110001000 -FL11000 -FP0($$Device:nRF52832_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52832_xxAA$Flash\nrf52xxx_uicr.flm))
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx -FS00 -FL0200000 -FF1nrf52xxx_uicr -FS110001000 -FL11000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm))
           0
-          $$Device:nRF52832_xxAA$Device\Include\nrf.h
+          $$Device:nRF52840_xxAA$Device\Include\nrf.h
           
           
           
@@ -33,7 +33,7 @@
           
           
           
-          $$Device:nRF52832_xxAA$SVD\nrf52.svd
+          $$Device:nRF52840_xxAA$SVD\nrf52840.svd
           0
           0
           
@@ -245,12 +245,12 @@
               
                 0
                 0x20000000
-                0x10000
+                0x40000
               
               
                 1
                 0x0
-                0x80000
+                0x100000
               
               
                 0
@@ -274,8 +274,8 @@
               
               
                 1
-                0x1f000
-                0x61000
+                0x0
+                0x100000
               
               
                 1
@@ -299,8 +299,8 @@
               
               
                 0
-                0x200025f8
-                0xda08
+                0x20000000
+                0x40000
               
               
                 0
@@ -336,9 +336,9 @@
             0
             
               --reduce_paths
-              NRF52_PAN_55, NRF52_PAN_12, NRF52_PAN_15, NRF52_PAN_58, SWI_DISABLE0, SOFTDEVICE_PRESENT, NRF52_PAN_54, NRF52, BLE_STACK_SUPPORT_REQD, NRF52_PAN_51, NRF52_PAN_36, RTTHREAD, CONFIG_GPIO_AS_PINRESET, NRF52_PAN_64, NRF52_PAN_20, NRF52_PAN_74, NRF52832_XXAA, S132, NRF_SD_BLE_API_VERSION=4, NRF52_PAN_31, RT_USING_ARM_LIBC
+              NRF52840_XXAA, USE_APP_CONFIG, __RTTHREAD__
               
-              .;..\..\..\include;applications;.;board;..\libraries\drivers;packages\nRF5_SDK_13.0.0_04a0bfd\components;packages\nRF5_SDK_13.0.0_04a0bfd\components\softdevice\common\softdevice_handler;packages\nRF5_SDK_13.0.0_04a0bfd\components\softdevice\s132\headers;packages\nRF5_SDK_13.0.0_04a0bfd\components\softdevice\s132\headers\nrf52;packages\nRF5_SDK_13.0.0_04a0bfd\components\ble\common;packages\nRF5_SDK_13.0.0_04a0bfd\components\ble\nrf_ble_gatt;packages\nRF5_SDK_13.0.0_04a0bfd\components\ble\ble_advertising;packages\nRF5_SDK_13.0.0_04a0bfd\components\ble\ble_services\ble_nus;packages\nRF5_SDK_13.0.0_04a0bfd\components;packages\nRF5_SDK_13.0.0_04a0bfd\components\device;packages\nRF5_SDK_13.0.0_04a0bfd\components\drivers_nrf\delay;packages\nRF5_SDK_13.0.0_04a0bfd\components\drivers_nrf\uart;packages\nRF5_SDK_13.0.0_04a0bfd\components\drivers_nrf\clock;packages\nRF5_SDK_13.0.0_04a0bfd\components\drivers_nrf\gpiote;packages\nRF5_SDK_13.0.0_04a0bfd\components\drivers_nrf\common;packages\nRF5_SDK_13.0.0_04a0bfd\components\drivers_nrf\hal;packages\nRF5_SDK_13.0.0_04a0bfd\components\drivers_nrf\pwm;packages\nRF5_SDK_13.0.0_04a0bfd\components\drivers_nrf\saadc;packages\nRF5_SDK_13.0.0_04a0bfd\components\libraries\util;packages\nRF5_SDK_13.0.0_04a0bfd\components\libraries\timer;packages\nRF5_SDK_13.0.0_04a0bfd\components\libraries\fstorage;packages\nRF5_SDK_13.0.0_04a0bfd\components\libraries\experimental_section_vars;packages\nRF5_SDK_13.0.0_04a0bfd\components\libraries\log;packages\nRF5_SDK_13.0.0_04a0bfd\components\libraries\log\src;packages\nRF5_SDK_13.0.0_04a0bfd\components\libraries\strerror;packages\nRF5_SDK_13.0.0_04a0bfd\components\toolchain\cmsis\include;packages\nRF5_SDK_13.0.0_04a0bfd\components\toolchain;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\compilers\common
+              applications;.;..\libraries\cmsis\include;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\drivers;..\..\..\components\finsh;.;..\..\..\include;packages\nrfx-v2.1.0;packages\nrfx-v2.1.0\drivers;packages\nrfx-v2.1.0\drivers\include;packages\nrfx-v2.1.0\mdk;packages\nrfx-v2.1.0\hal
             
           
           
@@ -354,7 +354,7 @@
             0
             
               --cpreproc_opts=-DBLE_STACK_SUPPORT_REQD,-DNRF_SD_BLE_API_VERSION=4,-DS132,-DSOFTDEVICE_PRESENT,-DSWI_DISABLE0,-DCONFIG_GPIO_AS_PINRESET,-DNRF52,-DNRF52832_XXAA,-DNRF52_PAN_12,-DNRF52_PAN_15,-DNRF52_PAN_20,-DNRF52_PAN_31,-DNRF52_PAN_36,-DNRF52_PAN_51,-DNRF52_PAN_54,-DNRF52_PAN_55,-DNRF52_PAN_58,-DNRF52_PAN_64,-DNRF52_PAN_74
-              BLE_STACK_SUPPORT_REQD NRF_SD_BLE_API_VERSION=4 S132 SOFTDEVICE_PRESENT SWI_DISABLE0 CONFIG_GPIO_AS_PINRESET NRF52 NRF52832_XXAA NRF52_PAN_12 NRF52_PAN_15 NRF52_PAN_20 NRF52_PAN_31 NRF52_PAN_36 NRF52_PAN_51 NRF52_PAN_54 NRF52_PAN_55 NRF52_PAN_58 NRF52_PAN_64 NRF52_PAN_74
+              
               
               
             
@@ -379,81 +379,6 @@
         
       
       
-        
-          Kernel
-          
-            
-              clock.c
-              1
-              ..\..\..\src\clock.c
-            
-            
-              components.c
-              1
-              ..\..\..\src\components.c
-            
-            
-              device.c
-              1
-              ..\..\..\src\device.c
-            
-            
-              idle.c
-              1
-              ..\..\..\src\idle.c
-            
-            
-              ipc.c
-              1
-              ..\..\..\src\ipc.c
-            
-            
-              irq.c
-              1
-              ..\..\..\src\irq.c
-            
-            
-              kservice.c
-              1
-              ..\..\..\src\kservice.c
-            
-            
-              mem.c
-              1
-              ..\..\..\src\mem.c
-            
-            
-              mempool.c
-              1
-              ..\..\..\src\mempool.c
-            
-            
-              object.c
-              1
-              ..\..\..\src\object.c
-            
-            
-              scheduler.c
-              1
-              ..\..\..\src\scheduler.c
-            
-            
-              signal.c
-              1
-              ..\..\..\src\signal.c
-            
-            
-              thread.c
-              1
-              ..\..\..\src\thread.c
-            
-            
-              timer.c
-              1
-              ..\..\..\src\timer.c
-            
-          
-        
         
           Applications
           
@@ -462,15 +387,85 @@
               1
               applications\application.c
             
+          
+        
+        
+          CPU
+          
             
-              ble_nus_app.c
+              div0.c
               1
-              applications\ble_nus_app.c
+              ..\..\..\libcpu\arm\common\div0.c
             
             
-              startup.c
+              backtrace.c
               1
-              applications\startup.c
+              ..\..\..\libcpu\arm\common\backtrace.c
+            
+            
+              showmem.c
+              1
+              ..\..\..\libcpu\arm\common\showmem.c
+            
+            
+              context_rvds.S
+              2
+              ..\..\..\libcpu\arm\cortex-m4\context_rvds.S
+            
+            
+              cpuport.c
+              1
+              ..\..\..\libcpu\arm\cortex-m4\cpuport.c
+            
+          
+        
+        
+          DeviceDrivers
+          
+            
+              pin.c
+              1
+              ..\..\..\components\drivers\misc\pin.c
+            
+            
+              serial.c
+              1
+              ..\..\..\components\drivers\serial\serial.c
+            
+            
+              ringblk_buf.c
+              1
+              ..\..\..\components\drivers\src\ringblk_buf.c
+            
+            
+              ringbuffer.c
+              1
+              ..\..\..\components\drivers\src\ringbuffer.c
+            
+            
+              workqueue.c
+              1
+              ..\..\..\components\drivers\src\workqueue.c
+            
+            
+              waitqueue.c
+              1
+              ..\..\..\components\drivers\src\waitqueue.c
+            
+            
+              completion.c
+              1
+              ..\..\..\components\drivers\src\completion.c
+            
+            
+              pipe.c
+              1
+              ..\..\..\components\drivers\src\pipe.c
+            
+            
+              dataqueue.c
+              1
+              ..\..\..\components\drivers\src\dataqueue.c
             
           
         
@@ -489,226 +484,6 @@
             
           
         
-        
-          BLE_STACK
-          
-            
-              ble_advdata.c
-              1
-              packages\nRF5_SDK_13.0.0_04a0bfd\components\ble\common\ble_advdata.c
-            
-            
-              ble_conn_params.c
-              1
-              packages\nRF5_SDK_13.0.0_04a0bfd\components\ble\common\ble_conn_params.c
-            
-            
-              ble_conn_state.c
-              1
-              packages\nRF5_SDK_13.0.0_04a0bfd\components\ble\common\ble_conn_state.c
-            
-            
-              ble_srv_common.c
-              1
-              packages\nRF5_SDK_13.0.0_04a0bfd\components\ble\common\ble_srv_common.c
-            
-            
-              nrf_ble_gatt.c
-              1
-              packages\nRF5_SDK_13.0.0_04a0bfd\components\ble\nrf_ble_gatt\nrf_ble_gatt.c
-            
-            
-              ble_nus.c
-              1
-              packages\nRF5_SDK_13.0.0_04a0bfd\components\ble\ble_services\ble_nus\ble_nus.c
-            
-            
-              ble_advertising.c
-              1
-              packages\nRF5_SDK_13.0.0_04a0bfd\components\ble\ble_advertising\ble_advertising.c
-            
-            
-              softdevice_handler.c
-              1
-              packages\nRF5_SDK_13.0.0_04a0bfd\components\softdevice\common\softdevice_handler\softdevice_handler.c
-            
-          
-        
-        
-          NRF_DRIVERS
-          
-            
-              nrf_saadc.c
-              1
-              packages\nRF5_SDK_13.0.0_04a0bfd\components\drivers_nrf\hal\nrf_saadc.c
-            
-            
-              nrf_drv_common.c
-              1
-              packages\nRF5_SDK_13.0.0_04a0bfd\components\drivers_nrf\common\nrf_drv_common.c
-            
-            
-              nrf_drv_clock.c
-              1
-              packages\nRF5_SDK_13.0.0_04a0bfd\components\drivers_nrf\clock\nrf_drv_clock.c
-            
-            
-              nrf_drv_gpiote.c
-              1
-              packages\nRF5_SDK_13.0.0_04a0bfd\components\drivers_nrf\gpiote\nrf_drv_gpiote.c
-            
-            
-              nrf_drv_pwm.c
-              1
-              packages\nRF5_SDK_13.0.0_04a0bfd\components\drivers_nrf\pwm\nrf_drv_pwm.c
-            
-            
-              nrf_drv_saadc.c
-              1
-              packages\nRF5_SDK_13.0.0_04a0bfd\components\drivers_nrf\saadc\nrf_drv_saadc.c
-            
-            
-              nrf_log_backend_serial.c
-              1
-              packages\nRF5_SDK_13.0.0_04a0bfd\components\libraries\log\src\nrf_log_backend_serial.c
-            
-            
-              nrf_log_frontend.c
-              1
-              packages\nRF5_SDK_13.0.0_04a0bfd\components\libraries\log\src\nrf_log_frontend.c
-            
-            
-              app_timer_rtthread.c
-              1
-              packages\nRF5_SDK_13.0.0_04a0bfd\components\libraries\timer\app_timer_rtthread.c
-            
-            
-              app_error.c
-              1
-              packages\nRF5_SDK_13.0.0_04a0bfd\components\libraries\util\app_error.c
-            
-            
-              app_error_weak.c
-              1
-              packages\nRF5_SDK_13.0.0_04a0bfd\components\libraries\util\app_error_weak.c
-            
-            
-              app_util_platform.c
-              1
-              packages\nRF5_SDK_13.0.0_04a0bfd\components\libraries\util\app_util_platform.c
-            
-            
-              nrf_assert.c
-              1
-              packages\nRF5_SDK_13.0.0_04a0bfd\components\libraries\util\nrf_assert.c
-            
-            
-              sdk_mapped_flags.c
-              1
-              packages\nRF5_SDK_13.0.0_04a0bfd\components\libraries\util\sdk_mapped_flags.c
-            
-            
-              fstorage.c
-              1
-              packages\nRF5_SDK_13.0.0_04a0bfd\components\libraries\fstorage\fstorage.c
-            
-            
-              nrf_strerror.c
-              1
-              packages\nRF5_SDK_13.0.0_04a0bfd\components\libraries\strerror\nrf_strerror.c
-            
-            
-              system_nrf52.c
-              1
-              packages\nRF5_SDK_13.0.0_04a0bfd\components\toolchain\system_nrf52.c
-            
-            
-              arm_startup_nrf52.s
-              2
-              packages\nRF5_SDK_13.0.0_04a0bfd\components\toolchain\arm\arm_startup_nrf52.s
-            
-          
-        
-        
-          cpu
-          
-            
-              backtrace.c
-              1
-              ..\..\..\libcpu\arm\common\backtrace.c
-            
-            
-              div0.c
-              1
-              ..\..\..\libcpu\arm\common\div0.c
-            
-            
-              showmem.c
-              1
-              ..\..\..\libcpu\arm\common\showmem.c
-            
-            
-              cpuport.c
-              1
-              ..\..\..\libcpu\arm\cortex-m4\cpuport.c
-            
-            
-              context_rvds.S
-              2
-              ..\..\..\libcpu\arm\cortex-m4\context_rvds.S
-            
-          
-        
-        
-          DeviceDrivers
-          
-            
-              pin.c
-              1
-              ..\..\..\components\drivers\misc\pin.c
-            
-            
-              serial.c
-              1
-              ..\..\..\components\drivers\serial\serial.c
-            
-            
-              completion.c
-              1
-              ..\..\..\components\drivers\src\completion.c
-            
-            
-              dataqueue.c
-              1
-              ..\..\..\components\drivers\src\dataqueue.c
-            
-            
-              pipe.c
-              1
-              ..\..\..\components\drivers\src\pipe.c
-            
-            
-              ringblk_buf.c
-              1
-              ..\..\..\components\drivers\src\ringblk_buf.c
-            
-            
-              ringbuffer.c
-              1
-              ..\..\..\components\drivers\src\ringbuffer.c
-            
-            
-              waitqueue.c
-              1
-              ..\..\..\components\drivers\src\waitqueue.c
-            
-            
-              workqueue.c
-              1
-              ..\..\..\components\drivers\src\workqueue.c
-            
-          
-        
         
           finsh
           
@@ -717,40 +492,275 @@
               1
               ..\..\..\components\finsh\shell.c
             
-            
-              cmd.c
-              1
-              ..\..\..\components\finsh\cmd.c
-            
             
               msh.c
               1
               ..\..\..\components\finsh\msh.c
             
+            
+              cmd.c
+              1
+              ..\..\..\components\finsh\cmd.c
+            
           
         
         
-          libc
+          Kernel
           
             
-              libc.c
+              irq.c
               1
-              ..\..\..\components\libc\compilers\armlibc\libc.c
+              ..\..\..\src\irq.c
             
             
-              mem_std.c
+              clock.c
               1
-              ..\..\..\components\libc\compilers\armlibc\mem_std.c
+              ..\..\..\src\clock.c
             
             
-              stubs.c
+              kservice.c
               1
-              ..\..\..\components\libc\compilers\armlibc\stubs.c
+              ..\..\..\src\kservice.c
             
             
-              time.c
+              timer.c
               1
-              ..\..\..\components\libc\compilers\common\time.c
+              ..\..\..\src\timer.c
+            
+            
+              object.c
+              1
+              ..\..\..\src\object.c
+            
+            
+              components.c
+              1
+              ..\..\..\src\components.c
+            
+            
+              scheduler.c
+              1
+              ..\..\..\src\scheduler.c
+            
+            
+              idle.c
+              1
+              ..\..\..\src\idle.c
+            
+            
+              ipc.c
+              1
+              ..\..\..\src\ipc.c
+            
+            
+              mem.c
+              1
+              ..\..\..\src\mem.c
+            
+            
+              thread.c
+              1
+              ..\..\..\src\thread.c
+            
+            
+              mempool.c
+              1
+              ..\..\..\src\mempool.c
+            
+            
+              device.c
+              1
+              ..\..\..\src\device.c
+            
+          
+        
+        
+          nrfx
+          
+            
+              nrfx_spim.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_spim.c
+            
+            
+              nrfx_pwm.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_pwm.c
+            
+            
+              nrfx_spi.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_spi.c
+            
+            
+              nrfx_saadc.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_saadc.c
+            
+            
+              nrfx_usbd.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_usbd.c
+            
+            
+              nrfx_nvmc.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_nvmc.c
+            
+            
+              nrfx_comp.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_comp.c
+            
+            
+              nrfx_clock.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_clock.c
+            
+            
+              nrfx_twi_twim.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_twi_twim.c
+            
+            
+              nrfx_uart.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_uart.c
+            
+            
+              nrfx_temp.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_temp.c
+            
+            
+              nrfx_twis.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_twis.c
+            
+            
+              nrfx_ipc.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_ipc.c
+            
+            
+              nrfx_adc.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_adc.c
+            
+            
+              nrfx_dppi.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_dppi.c
+            
+            
+              nrfx_usbreg.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_usbreg.c
+            
+            
+              arm_startup_nrf52840.s
+              2
+              packages\nrfx-v2.1.0\mdk\arm_startup_nrf52840.s
+            
+            
+              nrfx_systick.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_systick.c
+            
+            
+              nrfx_spis.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_spis.c
+            
+            
+              nrfx_uarte.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_uarte.c
+            
+            
+              nrfx_gpiote.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_gpiote.c
+            
+            
+              nrfx_timer.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_timer.c
+            
+            
+              nrfx_qspi.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_qspi.c
+            
+            
+              nrfx_pdm.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_pdm.c
+            
+            
+              nrfx_rng.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_rng.c
+            
+            
+              nrfx_lpcomp.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_lpcomp.c
+            
+            
+              nrfx_i2s.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_i2s.c
+            
+            
+              nrfx_power.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_power.c
+            
+            
+              nrfx_ppi.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_ppi.c
+            
+            
+              system_nrf52840.c
+              1
+              packages\nrfx-v2.1.0\mdk\system_nrf52840.c
+            
+            
+              nrfx_egu.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_egu.c
+            
+            
+              nrfx_rtc.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_rtc.c
+            
+            
+              nrfx_twi.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_twi.c
+            
+            
+              nrfx_wdt.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_wdt.c
+            
+            
+              nrfx_nfct.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_nfct.c
+            
+            
+              nrfx_qdec.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_qdec.c
+            
+            
+              nrfx_twim.c
+              1
+              packages\nrfx-v2.1.0\drivers\src\nrfx_twim.c
             
           
         
diff --git a/bsp/nrf5x/libraries/templates/nrfx/rtconfig.h b/bsp/nrf5x/libraries/templates/nrfx/rtconfig.h
new file mode 100644
index 0000000000..8b32e12a55
--- /dev/null
+++ b/bsp/nrf5x/libraries/templates/nrfx/rtconfig.h
@@ -0,0 +1,186 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart0"
+#define RT_VER_NUM 0x40003
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_USING_MSH_ONLY
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SERIAL
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* Network interface device */
+
+
+/* light weight TCP/IP stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+#define PKG_USING_NRFX
+#define PKG_USING_NRFX_LATEST_VERSION
+
+/* AI packages */
+
+
+/* miscellaneous packages */
+
+
+/* samples: kernel and components samples */
+
+
+/* games: games run on RT-Thread console */
+
+
+/* Hardware Drivers Config */
+
+#define SOC_NRF52840
+#define NRFX_CLOCK_ENABLED 1
+#define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_CLOCK_CONFIG_LF_SRC 1
+#define SOC_NORDIC
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_UART
+#define NRFX_USING_UART
+#define NRFX_UART_ENABLED 1
+#define BSP_USING_UART0
+#define NRFX_UART0_ENABLED 1
+#define BSP_UART0_RX_PIN 8
+#define BSP_UART0_TX_PIN 6
+
+/* On-chip flash config */
+
+#define MCU_FLASH_START_ADDRESS 0x00000000
+#define MCU_FLASH_SIZE_KB 1024
+#define MCU_SRAM_START_ADDRESS 0x20000000
+#define MCU_SRAM_SIZE_KB 256
+#define MCU_FLASH_PAGE_SIZE 0x1000
+
+#endif
diff --git a/bsp/nrf5x/libraries/templates/nrf52x/rtconfig.py b/bsp/nrf5x/libraries/templates/nrfx/rtconfig.py
similarity index 83%
rename from bsp/nrf5x/libraries/templates/nrf52x/rtconfig.py
rename to bsp/nrf5x/libraries/templates/nrfx/rtconfig.py
index c1c6022558..c809814516 100644
--- a/bsp/nrf5x/libraries/templates/nrf52x/rtconfig.py
+++ b/bsp/nrf5x/libraries/templates/nrfx/rtconfig.py
@@ -40,10 +40,10 @@ if PLATFORM == 'gcc':
     OBJDUMP = PREFIX + 'objdump'
     OBJCPY = PREFIX + 'objcopy'
 
-    DEVICE = ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections'
+    DEVICE = ' -mcpu='+CPU + ' -mthumb -ffunction-sections -fdata-sections'
     CFLAGS = DEVICE
     AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
-    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-nrf52832.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
 
     CPATH = ''
     LPATH = ''
@@ -82,3 +82,11 @@ elif PLATFORM == 'armcc':
         CFLAGS += ' -O2'
 
     POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+
+def dist_handle(BSP_ROOT, dist_dir):
+    import sys
+    cwd_path = os.getcwd()
+    sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+    from sdk_dist import dist_do_building
+    dist_do_building(BSP_ROOT, dist_dir)
diff --git a/bsp/nrf5x/libraries/templates/nrfx/template.uvoptx b/bsp/nrf5x/libraries/templates/nrfx/template.uvoptx
new file mode 100644
index 0000000000..f567bf47e8
--- /dev/null
+++ b/bsp/nrf5x/libraries/templates/nrfx/template.uvoptx
@@ -0,0 +1,184 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    rtthread
+    0x4
+    ARM-ADS
+    
+      12000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        .\build\
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        0
+        0
+        1
+      
+      5
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        1
+        1
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        4
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        Segger\JL2CM3.dll
+      
+      
+        
+          0
+          JL2CM3
+          -U683349164 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FF1nrf52xxx_uicr.flm -FS110001000 -FL11000 -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm)
+        
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 )  -FN2 -FC4000 -FD20000000 -FF0nrf52xxx -FF1nrf52xxx_uicr -FL0200000 -FL11000 -FS00 -FS110001000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm)
+        
+      
+      
+      
+        0
+      
+      
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+      
+      
+      
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
+      
+        1
+        1
+        0
+        2
+        10000000
+      
+    
+  
+
+
diff --git a/bsp/nrf5x/libraries/templates/nrf52x/template.uvprojx b/bsp/nrf5x/libraries/templates/nrfx/template.uvprojx
similarity index 90%
rename from bsp/nrf5x/libraries/templates/nrf52x/template.uvprojx
rename to bsp/nrf5x/libraries/templates/nrfx/template.uvprojx
index 0bf64c89f2..47cfe00539 100644
--- a/bsp/nrf5x/libraries/templates/nrf52x/template.uvprojx
+++ b/bsp/nrf5x/libraries/templates/nrfx/template.uvprojx
@@ -14,16 +14,16 @@
       0
       
         
-          nRF52832_xxAA
+          nRF52840_xxAA
           Nordic Semiconductor
-          NordicSemiconductor.nRF_DeviceFamilyPack.8.24.1
+          NordicSemiconductor.nRF_DeviceFamilyPack.8.38.0
           http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/
-          IRAM(0x20000000,0x10000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE
+          IRAM(0x20000000,0x40000) IROM(0x00000000,0x100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE
           
           
-          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx -FS00 -FL0200000 -FF1nrf52xxx_uicr -FS110001000 -FL11000 -FP0($$Device:nRF52832_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52832_xxAA$Flash\nrf52xxx_uicr.flm))
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx -FS00 -FL0200000 -FF1nrf52xxx_uicr -FS110001000 -FL11000 -FP0($$Device:nRF52840_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52840_xxAA$Flash\nrf52xxx_uicr.flm))
           0
-          $$Device:nRF52832_xxAA$Device\Include\nrf.h
+          $$Device:nRF52840_xxAA$Device\Include\nrf.h
           
           
           
@@ -33,7 +33,7 @@
           
           
           
-          $$Device:nRF52832_xxAA$SVD\nrf52.svd
+          $$Device:nRF52840_xxAA$SVD\nrf52840.svd
           0
           0
           
@@ -245,12 +245,12 @@
               
                 0
                 0x20000000
-                0x10000
+                0x40000
               
               
                 1
                 0x0
-                0x80000
+                0x100000
               
               
                 0
@@ -274,8 +274,8 @@
               
               
                 1
-                0x1f000
-                0x61000
+                0x0
+                0x100000
               
               
                 1
@@ -299,8 +299,8 @@
               
               
                 0
-                0x200025f8
-                0xda08
+                0x20000000
+                0x40000
               
               
                 0
@@ -336,7 +336,7 @@
             0
             
               --reduce_paths
-              BLE_STACK_SUPPORT_REQD NRF_SD_BLE_API_VERSION=4 S132 SOFTDEVICE_PRESENT SWI_DISABLE0 CONFIG_GPIO_AS_PINRESET NRF52 NRF52832_XXAA NRF52_PAN_12 NRF52_PAN_15 NRF52_PAN_20 NRF52_PAN_31 NRF52_PAN_36 NRF52_PAN_51 NRF52_PAN_54 NRF52_PAN_55 NRF52_PAN_58 NRF52_PAN_64 NRF52_PAN_74
+              
               
               
             
@@ -354,13 +354,13 @@
             0
             
               --cpreproc_opts=-DBLE_STACK_SUPPORT_REQD,-DNRF_SD_BLE_API_VERSION=4,-DS132,-DSOFTDEVICE_PRESENT,-DSWI_DISABLE0,-DCONFIG_GPIO_AS_PINRESET,-DNRF52,-DNRF52832_XXAA,-DNRF52_PAN_12,-DNRF52_PAN_15,-DNRF52_PAN_20,-DNRF52_PAN_31,-DNRF52_PAN_36,-DNRF52_PAN_51,-DNRF52_PAN_54,-DNRF52_PAN_55,-DNRF52_PAN_58,-DNRF52_PAN_64,-DNRF52_PAN_74
-              BLE_STACK_SUPPORT_REQD NRF_SD_BLE_API_VERSION=4 S132 SOFTDEVICE_PRESENT SWI_DISABLE0 CONFIG_GPIO_AS_PINRESET NRF52 NRF52832_XXAA NRF52_PAN_12 NRF52_PAN_15 NRF52_PAN_20 NRF52_PAN_31 NRF52_PAN_36 NRF52_PAN_51 NRF52_PAN_54 NRF52_PAN_55 NRF52_PAN_58 NRF52_PAN_64 NRF52_PAN_74
+              
               
               
             
           
           
-            1
+            0
             0
             0
             0
@@ -369,7 +369,7 @@
             0x00000000
             0x20000000
             
-            
+            .\board\linker_scripts\link.sct
             
             
             --diag_suppress 6330
diff --git a/bsp/nrf5x/nrf51822/.config b/bsp/nrf5x/nrf51822/.config
new file mode 100644
index 0000000000..73a95686b2
--- /dev/null
+++ b/bsp/nrf5x/nrf51822/.config
@@ -0,0 +1,561 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+
+#
+# kservice optimization
+#
+# CONFIG_RT_KSERVICE_USING_STDLIB is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+CONFIG_RT_VER_NUM=0x40003
+# CONFIG_RT_USING_CPU_FFS is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+CONFIG_FINSH_USING_MSH_ONLY=y
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+# CONFIG_RT_SERIAL_USING_DMA is not set
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+# CONFIG_RT_USING_LIBC is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_LIBC_USING_TIME is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+CONFIG_PKG_USING_NRFX=y
+CONFIG_PKG_NRFX_PATH="/packages/peripherals/nrfx"
+# CONFIG_PKG_USING_NRFX_V210 is not set
+CONFIG_PKG_USING_NRFX_LATEST_VERSION=y
+CONFIG_PKG_NRFX_VER="latest"
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_COWSAY is not set
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_NRF51822=y
+CONFIG_SOC_NORDIC=y
+CONFIG_BSP_BOARD_MICROBIT_1_5=y
+# CONFIG_BSP_BOARD_MICROBIT_1_0 is not set
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_UART=y
+CONFIG_BSP_USING_UART0=y
+CONFIG_BSP_UART0_RX_PIN=25
+CONFIG_BSP_UART0_TX_PIN=24
+
+#
+# On-chip flash config
+#
+CONFIG_MCU_FLASH_START_ADDRESS=0x00000000
+CONFIG_MCU_FLASH_SIZE_KB=256
+CONFIG_MCU_SRAM_START_ADDRESS=0x20000000
+CONFIG_MCU_SRAM_SIZE_KB=16
+CONFIG_MCU_FLASH_PAGE_SIZE=0x1000
+CONFIG_NRFX_CLOCK_ENABLED=1
+CONFIG_NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY=7
+CONFIG_NRFX_CLOCK_CONFIG_LF_SRC=1
+CONFIG_NRFX_USING_UART=y
+CONFIG_NRFX_UART_ENABLED=1
+CONFIG_NRFX_UART0_ENABLED=1
diff --git a/bsp/nrf5x/nrf51822/Kconfig b/bsp/nrf5x/nrf51822/Kconfig
new file mode 100644
index 0000000000..3640eaa0ed
--- /dev/null
+++ b/bsp/nrf5x/nrf51822/Kconfig
@@ -0,0 +1,21 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "board/Kconfig"
+
diff --git a/bsp/nrf5x/nrf51822/README.md b/bsp/nrf5x/nrf51822/README.md
new file mode 100644
index 0000000000..9f917eb0b6
--- /dev/null
+++ b/bsp/nrf5x/nrf51822/README.md
@@ -0,0 +1,76 @@
+# nRF51822 BSP说明
+
+## 简介
+
+该文件夹主要存放所有主芯片为nRF51822的板级支持包。目前默认支持的开发板是[Micro:bitV1.5](https://tech.microbit.org/hardware/1-5-revision/)
+本文主要内容如下：
+
+- 开发板资源介绍
+- 进阶使用方法
+
+## 开发板介绍
+
+Microbit是BCC基于nordic的mcu nrf51822的开发板，基于ARM Cortex-M0内核，最高主频64 MHz，具有丰富的外设资源。
+
+
+
+开发板外观如下图所示
+
+![](../docs/images/microbit-overview-1-5.png)
+
+nrf51822 开发板常用 **板载资源** 如下：
+
+- MCU：NRF51822，主频 16MHz，256kB FLASH ，16kB RAM
+- MCU 外设: GPIO, UART, SPI, I2C(TWI), RTC,TIMER,PWM,ADC
+- 板载外设
+  - LED墙：25个，矩阵控制。
+  - 按键：3个，2个USER and 1个RESET 。
+  - 三轴加速度传感器:   LSM303AGR 
+  - CMSIS-DAP: KL26Z调试器
+- 调试接口：板载CMSIS-DAP 调试器。
+
+更详细的整理的资料见[nrf51822](https://github.com/supperthomas/BSP_BOARD_Nrf51822_microbit)
+
+官方主页[nrf51822](https://infocenter.nordicsemi.com/index.jsp?topic=%2Fstruct_nrf51%2Fstruct%2Fnrf51822.html)
+
+
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **片上外设** | **支持情况** | **备注** |
+| :----------- | :----------: | :------: |
+| GPIO         |    待支持    |          |
+| UART         |     支持     |  UART0   |
+|              |              |          |
+|              |              |          |
+|              |              |          |
+
+
+
+### 进阶使用
+
+此 BSP 默认只开启了串口 0 的功能，更多高级功能需要利用 env 工具对 BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=mdk5命令重新生成工程。
+
+
+
+## 支持其他开发板
+
+可以在board/Kconfig里面的`bsp choice`里面添加对应的其他开发板
+
+
+
+## 联系人信息
+
+维护人:
+
+-  [supperthomas], 邮箱：<78900636@qq.com>
\ No newline at end of file
diff --git a/bsp/stm32/stm32f103-mini-system/SConscript b/bsp/nrf5x/nrf51822/SConscript
similarity index 100%
rename from bsp/stm32/stm32f103-mini-system/SConscript
rename to bsp/nrf5x/nrf51822/SConscript
diff --git a/bsp/nrf5x/nrf51822/SConstruct b/bsp/nrf5x/nrf51822/SConstruct
new file mode 100644
index 0000000000..2ac1ce6674
--- /dev/null
+++ b/bsp/nrf5x/nrf51822/SConstruct
@@ -0,0 +1,57 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+print(SDK_LIB)
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript')))
+
+# include cmsis
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'cmsis', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/zynq7000/applications/SConscript b/bsp/nrf5x/nrf51822/applications/SConscript
similarity index 72%
rename from bsp/zynq7000/applications/SConscript
rename to bsp/nrf5x/nrf51822/applications/SConscript
index 01eb940dfb..fc2501998c 100644
--- a/bsp/zynq7000/applications/SConscript
+++ b/bsp/nrf5x/nrf51822/applications/SConscript
@@ -2,8 +2,8 @@ Import('RTT_ROOT')
 Import('rtconfig')
 from building import *
 
-cwd     = os.path.join(str(Dir('#')), 'applications')
-src	= Glob('*.c')
+cwd = os.path.join(str(Dir('#')), 'applications')
+src = Glob('*.c')
 CPPPATH = [cwd, str(Dir('#'))]
 
 group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
diff --git a/bsp/nrf5x/nrf51822/applications/application.c b/bsp/nrf5x/nrf51822/applications/application.c
new file mode 100644
index 0000000000..87d0f04b86
--- /dev/null
+++ b/bsp/nrf5x/nrf51822/applications/application.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-29     supperthomas first version
+ *
+ */
+
+#include 
+#include 
+
+int main(void)
+{
+    while (1)
+    {
+        rt_thread_mdelay(500);
+    }
+    return RT_EOK;
+}
+
diff --git a/bsp/nrf5x/nrf51822/board/Kconfig b/bsp/nrf5x/nrf51822/board/Kconfig
new file mode 100644
index 0000000000..64ee8325ed
--- /dev/null
+++ b/bsp/nrf5x/nrf51822/board/Kconfig
@@ -0,0 +1,101 @@
+menu "Hardware Drivers Config"
+
+config SOC_NRF51822
+    bool
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+    
+config SOC_NORDIC
+    bool 
+    default y
+
+choice
+    prompt "Select BSP board "
+    default BSP_BOARD_MICROBIT_1_5
+
+    config BSP_BOARD_MICROBIT_1_5
+        bool "microbit nrf51822 v1.5"
+        
+    config BSP_BOARD_MICROBIT_1_0
+        bool "microbit nrf51822 v1.0"
+        
+endchoice
+
+menu "On-chip Peripheral Drivers"    
+    config BSP_USING_UART
+		bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+            config BSP_USING_UART0
+                bool "Enable UART0"
+                default y 
+                depends on BSP_USING_UART
+                
+                config BSP_UART0_RX_PIN
+                    depends on BSP_USING_UART0
+                    int "uart0 rx pin number"
+                    default 25 if BSP_BOARD_MICROBIT_1_5
+                    default 8 if BSP_BOARD_MICROBIT_1_0
+                config BSP_UART0_TX_PIN
+                    depends on BSP_USING_UART0
+                    int "uart0 tx pin number"
+                    default 24  if BSP_BOARD_MICROBIT_1_5
+                    default 9   if BSP_BOARD_MICROBIT_1_0
+
+    menu "On-chip flash config"
+
+        config MCU_FLASH_START_ADDRESS  
+            hex "MCU FLASH START ADDRESS"
+            default 0x00000000
+
+        config MCU_FLASH_SIZE_KB  
+            int "MCU FLASH SIZE, MAX size 1024 KB"
+            default 1024
+
+        config MCU_SRAM_START_ADDRESS 
+            hex "MCU RAM START ADDRESS"
+            default 0x20000000
+
+        config MCU_SRAM_SIZE_KB  
+            int "MCU RAM SIZE"
+            default 16
+
+        config MCU_FLASH_PAGE_SIZE 
+            hex "MCU FLASH PAGE SIZE, please not change,nrfx default is 0x1000"
+            default 0x1000
+	endmenu
+
+endmenu
+
+if SOC_NORDIC
+    config NRFX_CLOCK_ENABLED
+    int 
+    default 1
+    config    NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY
+    int 
+    default 7
+    config NRFX_CLOCK_CONFIG_LF_SRC
+    int 
+    default 1    
+endif
+
+if BSP_USING_UART
+    config NRFX_USING_UART
+    bool
+    default y
+    
+    config NRFX_UART_ENABLED
+    int 
+    default 1
+    
+    config NRFX_UART0_ENABLED
+    int 
+    default 1
+    depends on BSP_USING_UART0
+endif
+
+
+endmenu
+
+
diff --git a/bsp/nrf5x/nrf51822/board/SConscript b/bsp/nrf5x/nrf51822/board/SConscript
new file mode 100644
index 0000000000..27bcddd310
--- /dev/null
+++ b/bsp/nrf5x/nrf51822/board/SConscript
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+define = ['USE_APP_CONFIG']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH,CPPDEFINES = define)
+Return('group')
diff --git a/bsp/nrf5x/nrf51822/board/board.c b/bsp/nrf5x/nrf51822/board/board.c
new file mode 100644
index 0000000000..2cb94fb6fa
--- /dev/null
+++ b/bsp/nrf5x/nrf51822/board/board.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-29     supperthomas first version
+ *
+ */
+#include 
+#include 
+#include 
+
+#include "board.h"
+#include "drv_uart.h"
+#include 
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+static void clk_event_handler(nrfx_clock_evt_type_t event){}
+
+void SysTick_Configuration(void)
+{
+    nrfx_clock_init(clk_event_handler);
+    nrfx_clock_enable();
+    nrfx_clock_lfclk_start();
+    /* Set interrupt priority */
+    NVIC_SetPriority(SysTick_IRQn, 0xf);
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    nrf_systick_load_set(SystemCoreClock / RT_TICK_PER_SECOND);
+    nrf_systick_val_clear();
+    nrf_systick_csr_set(NRF_SYSTICK_CSR_CLKSOURCE_CPU | NRF_SYSTICK_CSR_TICKINT_ENABLE
+                        | NRF_SYSTICK_CSR_ENABLE);
+
+}
+
+
+void rt_hw_board_init(void)
+{
+    rt_hw_interrupt_enable(0);
+
+    SysTick_Configuration();
+
+#if defined(RT_USING_HEAP)
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+
+#ifdef RT_USING_SERIAL
+    rt_hw_uart_init();
+#endif
+
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+
+#ifdef BSP_USING_SOFTDEVICE
+    extern uint32_t  Image$$RW_IRAM1$$Base;
+    uint32_t const *const m_ram_start  = &Image$$RW_IRAM1$$Base;
+    if ((uint32_t)m_ram_start == 0x20000000)
+    {
+        rt_kprintf("\r\n using softdevice the RAM couldn't be %p,please use the templete from package\r\n", m_ram_start);
+        while (1);
+    }
+    else
+    {
+        rt_kprintf("\r\n using softdevice the RAM at %p\r\n", m_ram_start);
+    }
+#endif
+
+}
+
diff --git a/bsp/nrf5x/nrf51822/board/board.h b/bsp/nrf5x/nrf51822/board/board.h
new file mode 100644
index 0000000000..a3ccadfa36
--- /dev/null
+++ b/bsp/nrf5x/nrf51822/board/board.h
@@ -0,0 +1,30 @@
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include 
+#include 
+#include "nrf.h"
+
+#define MCU_FLASH_SIZE MCU_FLASH_SIZE_KB*1024
+#define MCU_FLASH_END_ADDRESS        ((uint32_t)(MCU_FLASH_START_ADDRESS + MCU_FLASH_SIZE))
+#define MCU_SRAM_SIZE MCU_SRAM_SIZE_KB*1024
+#define MCU_SRAM_END_ADDRESS        (MCU_SRAM_START_ADDRESS + MCU_SRAM_SIZE)
+
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN      ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="CSTACK"
+#define HEAP_BEGIN      (__segment_end("CSTACK"))
+#else
+extern int __bss_end__;
+#define HEAP_BEGIN      ((void *)&__bss_end__)
+#endif
+
+
+#define HEAP_END       (MCU_SRAM_END_ADDRESS)
+
+void rt_hw_board_init(void);
+
+#endif
+
diff --git a/bsp/nrf5x/nrf51822/board/linker_scripts/link.lds b/bsp/nrf5x/nrf51822/board/linker_scripts/link.lds
new file mode 100644
index 0000000000..47f823186e
--- /dev/null
+++ b/bsp/nrf5x/nrf51822/board/linker_scripts/link.lds
@@ -0,0 +1,15 @@
+/* Linker script to configure memory regions. */
+
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x40000
+  RAM (rwx) :  ORIGIN = 0x20000000, LENGTH = 0x4000
+}
+
+INCLUDE "packages/nrfx-v2.1.0/mdk/nrf_common.ld"
+
+
+
diff --git a/bsp/nrf5x/nrf51822/board/linker_scripts/link.sct b/bsp/nrf5x/nrf51822/board/linker_scripts/link.sct
new file mode 100644
index 0000000000..e4a89512f2
--- /dev/null
+++ b/bsp/nrf5x/nrf51822/board/linker_scripts/link.sct
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x40000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x40000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20000000 0x4000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+
diff --git a/bsp/nrf5x/nrf51822/board/nrfx_config.h b/bsp/nrf5x/nrf51822/board/nrfx_config.h
new file mode 100644
index 0000000000..b006b6bcd5
--- /dev/null
+++ b/bsp/nrf5x/nrf51822/board/nrfx_config.h
@@ -0,0 +1,47 @@
+/**
+ * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form, except as embedded into a Nordic
+ *    Semiconductor ASA integrated circuit in a product or a software update for
+ *    such product, must reproduce the above copyright notice, this list of
+ *    conditions and the following disclaimer in the documentation and/or other
+ *    materials provided with the distribution.
+ *
+ * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ *    contributors may be used to endorse or promote products derived from this
+ *    software without specific prior written permission.
+ *
+ * 4. This software, with or without modification, must only be used with a
+ *    Nordic Semiconductor ASA integrated circuit.
+ *
+ * 5. Any software provided in binary form under this license must not be reverse
+ *    engineered, decompiled, modified and/or disassembled.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef NRFX_CONFIG_H__
+#define NRFX_CONFIG_H__
+
+// TODO - temporary redirection
+#include 
+
+#endif // NRFX_CONFIG_H__
diff --git a/bsp/nrf5x/nrf51822/board/nrfx_glue.h b/bsp/nrf5x/nrf51822/board/nrfx_glue.h
new file mode 100644
index 0000000000..28025dafae
--- /dev/null
+++ b/bsp/nrf5x/nrf51822/board/nrfx_glue.h
@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from this
+ *    software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRFX_GLUE_H__
+#define NRFX_GLUE_H__
+
+// THIS IS A TEMPLATE FILE.
+// It should be copied to a suitable location within the host environment into
+// which nrfx is integrated, and the following macros should be provided with
+// appropriate implementations.
+// And this comment should be removed from the customized file.
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include 
+#include "nrf.h"
+/**
+ * @defgroup nrfx_glue nrfx_glue.h
+ * @{
+ * @ingroup nrfx
+ *
+ * @brief This file contains macros that should be implemented according to
+ *        the needs of the host environment into which @em nrfx is integrated.
+ */
+
+// Uncomment this line to use the standard MDK way of binding IRQ handlers
+// at linking time.
+#include 
+
+//------------------------------------------------------------------------------
+
+/**
+ * @brief Macro for placing a runtime assertion.
+ *
+ * @param expression Expression to be evaluated.
+ */
+#define NRFX_ASSERT(expression)
+
+/**
+ * @brief Macro for placing a compile time assertion.
+ *
+ * @param expression Expression to be evaluated.
+ */
+#define NRFX_STATIC_ASSERT(expression)
+
+//------------------------------------------------------------------------------
+
+/**
+ * @brief Macro for setting the priority of a specific IRQ.
+ *
+ * @param irq_number IRQ number.
+ * @param priority   Priority to be set.
+ */
+#define NRFX_IRQ_PRIORITY_SET(irq_number, priority)     NVIC_SetPriority(irq_number, priority)
+
+/**
+ * @brief Macro for enabling a specific IRQ.
+ *
+ * @param irq_number IRQ number.
+ */
+#define NRFX_IRQ_ENABLE(irq_number)     NVIC_EnableIRQ(irq_number)
+
+/**
+ * @brief Macro for checking if a specific IRQ is enabled.
+ *
+ * @param irq_number IRQ number.
+ *
+ * @retval true  If the IRQ is enabled.
+ * @retval false Otherwise.
+ */
+#define NRFX_IRQ_IS_ENABLED(irq_number)  _NRFX_IRQ_IS_ENABLED(irq_number)
+static inline bool _NRFX_IRQ_IS_ENABLED(IRQn_Type irq_number)
+{
+    return 0 != (NVIC->ISER[irq_number / 32] & (1UL << (irq_number % 32)));
+}
+
+
+/**
+ * @brief Macro for disabling a specific IRQ.
+ *
+ * @param irq_number IRQ number.
+ */
+#define NRFX_IRQ_DISABLE(irq_number)  _NRFX_IRQ_DISABLE(irq_number)
+static inline void _NRFX_IRQ_DISABLE(IRQn_Type irq_number)
+{
+    NVIC_DisableIRQ(irq_number);
+}
+
+
+/**
+ * @brief Macro for setting a specific IRQ as pending.
+ *
+ * @param irq_number IRQ number.
+ */
+#define NRFX_IRQ_PENDING_SET(irq_number)
+
+/**
+ * @brief Macro for clearing the pending status of a specific IRQ.
+ *
+ * @param irq_number IRQ number.
+ */
+#define NRFX_IRQ_PENDING_CLEAR(irq_number)
+
+/**
+ * @brief Macro for checking the pending status of a specific IRQ.
+ *
+ * @retval true  If the IRQ is pending.
+ * @retval false Otherwise.
+ */
+#define NRFX_IRQ_IS_PENDING(irq_number)
+
+/** @brief Macro for entering into a critical section. */
+#define NRFX_CRITICAL_SECTION_ENTER()
+
+/** @brief Macro for exiting from a critical section. */
+#define NRFX_CRITICAL_SECTION_EXIT()
+
+//------------------------------------------------------------------------------
+
+/**
+ * @brief When set to a non-zero value, this macro specifies that
+ *        @ref nrfx_coredep_delay_us uses a precise DWT-based solution.
+ *        A compilation error is generated if the DWT unit is not present
+ *        in the SoC used.
+ */
+#define NRFX_DELAY_DWT_BASED    0
+
+/**
+ * @brief Macro for delaying the code execution for at least the specified time.
+ *
+ * @param us_time Number of microseconds to wait.
+ */
+#define NRFX_DELAY_US(us_time)
+
+//------------------------------------------------------------------------------
+
+/** @brief Atomic 32-bit unsigned type. */
+#define nrfx_atomic_t
+
+/**
+ * @brief Macro for storing a value to an atomic object and returning its previous value.
+ *
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value  Value to store.
+ *
+ * @return Previous value of the atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_STORE(p_data, value)
+
+/**
+ * @brief Macro for running a bitwise OR operation on an atomic object and returning its previous value.
+ *
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value  Value of the second operand in the OR operation.
+ *
+ * @return Previous value of the atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_OR(p_data, value)
+
+/**
+ * @brief Macro for running a bitwise AND operation on an atomic object
+ *        and returning its previous value.
+ *
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value  Value of the second operand in the AND operation.
+ *
+ * @return Previous value of the atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_AND(p_data, value)
+
+/**
+ * @brief Macro for running a bitwise XOR operation on an atomic object
+ *        and returning its previous value.
+ *
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value  Value of the second operand in the XOR operation.
+ *
+ * @return Previous value of the atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_XOR(p_data, value)
+
+/**
+ * @brief Macro for running an addition operation on an atomic object
+ *        and returning its previous value.
+ *
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value  Value of the second operand in the ADD operation.
+ *
+ * @return Previous value of the atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_ADD(p_data, value)
+
+/**
+ * @brief Macro for running a subtraction operation on an atomic object
+ *        and returning its previous value.
+ *
+ * @param[in] p_data Atomic memory pointer.
+ * @param[in] value  Value of the second operand in the SUB operation.
+ *
+ * @return Previous value of the atomic object.
+ */
+#define NRFX_ATOMIC_FETCH_SUB(p_data, value)
+
+//------------------------------------------------------------------------------
+
+/**
+ * @brief When set to a non-zero value, this macro specifies that the
+ *        @ref nrfx_error_codes and the @ref nrfx_err_t type itself are defined
+ *        in a customized way and the default definitions from @c 
+ *        should not be used.
+ */
+#define NRFX_CUSTOM_ERROR_CODES 0
+
+//------------------------------------------------------------------------------
+
+/** @brief Bitmask that defines DPPI channels that are reserved for use outside of the nrfx library. */
+#define NRFX_DPPI_CHANNELS_USED  0
+
+/** @brief Bitmask that defines DPPI groups that are reserved for use outside of the nrfx library. */
+#define NRFX_DPPI_GROUPS_USED    0
+
+/** @brief Bitmask that defines PPI channels that are reserved for use outside of the nrfx library. */
+#define NRFX_PPI_CHANNELS_USED  0
+
+/** @brief Bitmask that defines PPI groups that are reserved for use outside of the nrfx library. */
+#define NRFX_PPI_GROUPS_USED    0
+
+/** @brief Bitmask that defines EGU instances that are reserved for use outside of the nrfx library. */
+#define NRFX_EGUS_USED          0
+
+/** @brief Bitmask that defines TIMER instances that are reserved for use outside of the nrfx library. */
+#define NRFX_TIMERS_USED        0
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRFX_GLUE_H__
diff --git a/bsp/nrf5x/nrf51822/board/nrfx_log.h b/bsp/nrf5x/nrf51822/board/nrfx_log.h
new file mode 100644
index 0000000000..80d8efbdf1
--- /dev/null
+++ b/bsp/nrf5x/nrf51822/board/nrfx_log.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from this
+ *    software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef NRFX_LOG_H__
+#define NRFX_LOG_H__
+
+// THIS IS A TEMPLATE FILE.
+// It should be copied to a suitable location within the host environment into
+// which nrfx is integrated, and the following macros should be provided with
+// appropriate implementations.
+// And this comment should be removed from the customized file.
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup nrfx_log nrfx_log.h
+ * @{
+ * @ingroup nrfx
+ *
+ * @brief This file contains macros that should be implemented according to
+ *        the needs of the host environment into which @em nrfx is integrated.
+ */
+
+/**
+ * @brief Macro for logging a message with the severity level ERROR.
+ *
+ * @param format printf-style format string, optionally followed by arguments
+ *               to be formatted and inserted in the resulting string.
+ */
+#define NRFX_LOG_ERROR(format, ...)
+
+/**
+ * @brief Macro for logging a message with the severity level WARNING.
+ *
+ * @param format printf-style format string, optionally followed by arguments
+ *               to be formatted and inserted in the resulting string.
+ */
+#define NRFX_LOG_WARNING(format, ...)
+
+/**
+ * @brief Macro for logging a message with the severity level INFO.
+ *
+ * @param format printf-style format string, optionally followed by arguments
+ *               to be formatted and inserted in the resulting string.
+ */
+#define NRFX_LOG_INFO(format, ...)
+
+/**
+ * @brief Macro for logging a message with the severity level DEBUG.
+ *
+ * @param format printf-style format string, optionally followed by arguments
+ *               to be formatted and inserted in the resulting string.
+ */
+#define NRFX_LOG_DEBUG(format, ...)
+
+
+/**
+ * @brief Macro for logging a memory dump with the severity level ERROR.
+ *
+ * @param[in] p_memory Pointer to the memory region to be dumped.
+ * @param[in] length   Length of the memory region in bytes.
+ */
+#define NRFX_LOG_HEXDUMP_ERROR(p_memory, length)
+
+/**
+ * @brief Macro for logging a memory dump with the severity level WARNING.
+ *
+ * @param[in] p_memory Pointer to the memory region to be dumped.
+ * @param[in] length   Length of the memory region in bytes.
+ */
+#define NRFX_LOG_HEXDUMP_WARNING(p_memory, length)
+
+/**
+ * @brief Macro for logging a memory dump with the severity level INFO.
+ *
+ * @param[in] p_memory Pointer to the memory region to be dumped.
+ * @param[in] length   Length of the memory region in bytes.
+ */
+#define NRFX_LOG_HEXDUMP_INFO(p_memory, length)
+
+/**
+ * @brief Macro for logging a memory dump with the severity level DEBUG.
+ *
+ * @param[in] p_memory Pointer to the memory region to be dumped.
+ * @param[in] length   Length of the memory region in bytes.
+ */
+#define NRFX_LOG_HEXDUMP_DEBUG(p_memory, length)
+
+
+/**
+ * @brief Macro for getting the textual representation of a given error code.
+ *
+ * @param[in] error_code Error code.
+ *
+ * @return String containing the textual representation of the error code.
+ */
+#define NRFX_LOG_ERROR_STRING_GET(error_code)
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRFX_LOG_H__
diff --git a/bsp/nrf5x/nrf51822/board/sdk_config.h b/bsp/nrf5x/nrf51822/board/sdk_config.h
new file mode 100644
index 0000000000..25fa4938fa
--- /dev/null
+++ b/bsp/nrf5x/nrf51822/board/sdk_config.h
@@ -0,0 +1,11701 @@
+/**
+ * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form, except as embedded into a Nordic
+ *    Semiconductor ASA integrated circuit in a product or a software update for
+ *    such product, must reproduce the above copyright notice, this list of
+ *    conditions and the following disclaimer in the documentation and/or other
+ *    materials provided with the distribution.
+ *
+ * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+ *    contributors may be used to endorse or promote products derived from this
+ *    software without specific prior written permission.
+ *
+ * 4. This software, with or without modification, must only be used with a
+ *    Nordic Semiconductor ASA integrated circuit.
+ *
+ * 5. Any software provided in binary form under this license must not be reverse
+ *    engineered, decompiled, modified and/or disassembled.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+
+
+#ifndef SDK_CONFIG_H
+#define SDK_CONFIG_H
+// <<< Use Configuration Wizard in Context Menu >>>\n
+//  nRF_BLE
+
+#include 
+//==========================================================
+//  BLE_ADVERTISING_ENABLED  - ble_advertising - Advertising module
+
+
+#ifndef BLE_ADVERTISING_ENABLED
+#define BLE_ADVERTISING_ENABLED 0
+#endif
+
+//  BLE_DTM_ENABLED  - ble_dtm - Module for testing RF/PHY using DTM commands
+
+
+#ifndef BLE_DTM_ENABLED
+#define BLE_DTM_ENABLED 0
+#endif
+
+//  BLE_RACP_ENABLED  - ble_racp - Record Access Control Point library
+
+
+#ifndef BLE_RACP_ENABLED
+#define BLE_RACP_ENABLED 0
+#endif
+
+//  NRF_BLE_QWR_ENABLED - nrf_ble_qwr - Queued writes support module (prepare/execute write)
+//==========================================================
+#ifndef NRF_BLE_QWR_ENABLED
+#define NRF_BLE_QWR_ENABLED 0
+#endif
+//  NRF_BLE_QWR_MAX_ATTR - Maximum number of attribute handles that can be registered. This number must be adjusted according to the number of attributes for which Queued Writes will be enabled. If it is zero, the module will reject all Queued Write requests.
+#ifndef NRF_BLE_QWR_MAX_ATTR
+#define NRF_BLE_QWR_MAX_ATTR 0
+#endif
+
+// 
+
+//  PEER_MANAGER_ENABLED - peer_manager - Peer Manager
+//==========================================================
+#ifndef PEER_MANAGER_ENABLED
+#define PEER_MANAGER_ENABLED 0
+#endif
+//  PM_MAX_REGISTRANTS - Number of event handlers that can be registered.
+#ifndef PM_MAX_REGISTRANTS
+#define PM_MAX_REGISTRANTS 3
+#endif
+
+//  PM_FLASH_BUFFERS - Number of internal buffers for flash operations.
+//  Decrease this value to lower RAM usage.
+
+#ifndef PM_FLASH_BUFFERS
+#define PM_FLASH_BUFFERS 4
+#endif
+
+//  PM_CENTRAL_ENABLED  - Enable/disable central-specific Peer Manager functionality.
+
+
+//  Enable/disable central-specific Peer Manager functionality.
+
+#ifndef PM_CENTRAL_ENABLED
+#define PM_CENTRAL_ENABLED 1
+#endif
+
+//  PM_SERVICE_CHANGED_ENABLED  - Enable/disable the service changed management for GATT server in Peer Manager.
+
+
+//  If not using a GATT server, or using a server wihout a service changed characteristic,
+//  disable this to save code space.
+
+#ifndef PM_SERVICE_CHANGED_ENABLED
+#define PM_SERVICE_CHANGED_ENABLED 1
+#endif
+
+//  PM_PEER_RANKS_ENABLED  - Enable/disable the peer rank management in Peer Manager.
+
+
+//  Set this to false to save code space if not using the peer rank API.
+
+#ifndef PM_PEER_RANKS_ENABLED
+#define PM_PEER_RANKS_ENABLED 1
+#endif
+
+//  PM_LESC_ENABLED  - Enable/disable LESC support in Peer Manager.
+
+
+//  If set to true, you need to call nrf_ble_lesc_request_handler() in the main loop to respond to LESC-related BLE events. If LESC support is not required, set this to false to save code space.
+
+#ifndef PM_LESC_ENABLED
+#define PM_LESC_ENABLED 0
+#endif
+
+//  PM_RA_PROTECTION_ENABLED - Enable/disable protection against repeated pairing attempts in Peer Manager.
+//==========================================================
+#ifndef PM_RA_PROTECTION_ENABLED
+#define PM_RA_PROTECTION_ENABLED 0
+#endif
+//  PM_RA_PROTECTION_TRACKED_PEERS_NUM - Maximum number of peers whose authorization status can be tracked.
+#ifndef PM_RA_PROTECTION_TRACKED_PEERS_NUM
+#define PM_RA_PROTECTION_TRACKED_PEERS_NUM 8
+#endif
+
+//  PM_RA_PROTECTION_MIN_WAIT_INTERVAL - Minimum waiting interval (in ms) before a new pairing attempt can be initiated.
+#ifndef PM_RA_PROTECTION_MIN_WAIT_INTERVAL
+#define PM_RA_PROTECTION_MIN_WAIT_INTERVAL 4000
+#endif
+
+//  PM_RA_PROTECTION_MAX_WAIT_INTERVAL - Maximum waiting interval (in ms) before a new pairing attempt can be initiated.
+#ifndef PM_RA_PROTECTION_MAX_WAIT_INTERVAL
+#define PM_RA_PROTECTION_MAX_WAIT_INTERVAL 64000
+#endif
+
+//  PM_RA_PROTECTION_REWARD_PERIOD - Reward period (in ms).
+//  The waiting interval is gradually decreased when no new failed pairing attempts are made during reward period.
+
+#ifndef PM_RA_PROTECTION_REWARD_PERIOD
+#define PM_RA_PROTECTION_REWARD_PERIOD 10000
+#endif
+
+// 
+
+//  PM_HANDLER_SEC_DELAY_MS - Delay before starting security.
+//   This might be necessary for interoperability reasons, especially as peripheral.
+
+#ifndef PM_HANDLER_SEC_DELAY_MS
+#define PM_HANDLER_SEC_DELAY_MS 0
+#endif
+
+// 
+
+// 
+//==========================================================
+
+//  nRF_BLE_Services
+
+//==========================================================
+//  BLE_ANCS_C_ENABLED  - ble_ancs_c - Apple Notification Service Client
+
+
+#ifndef BLE_ANCS_C_ENABLED
+#define BLE_ANCS_C_ENABLED 0
+#endif
+
+//  BLE_ANS_C_ENABLED  - ble_ans_c - Alert Notification Service Client
+
+
+#ifndef BLE_ANS_C_ENABLED
+#define BLE_ANS_C_ENABLED 0
+#endif
+
+//  BLE_BAS_C_ENABLED  - ble_bas_c - Battery Service Client
+
+
+#ifndef BLE_BAS_C_ENABLED
+#define BLE_BAS_C_ENABLED 0
+#endif
+
+//  BLE_BAS_ENABLED - ble_bas - Battery Service
+//==========================================================
+#ifndef BLE_BAS_ENABLED
+#define BLE_BAS_ENABLED 0
+#endif
+//  BLE_BAS_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef BLE_BAS_CONFIG_LOG_ENABLED
+#define BLE_BAS_CONFIG_LOG_ENABLED 0
+#endif
+//  BLE_BAS_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef BLE_BAS_CONFIG_LOG_LEVEL
+#define BLE_BAS_CONFIG_LOG_LEVEL 3
+#endif
+
+//  BLE_BAS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef BLE_BAS_CONFIG_INFO_COLOR
+#define BLE_BAS_CONFIG_INFO_COLOR 0
+#endif
+
+//  BLE_BAS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef BLE_BAS_CONFIG_DEBUG_COLOR
+#define BLE_BAS_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  BLE_CSCS_ENABLED  - ble_cscs - Cycling Speed and Cadence Service
+
+
+#ifndef BLE_CSCS_ENABLED
+#define BLE_CSCS_ENABLED 0
+#endif
+
+//  BLE_CTS_C_ENABLED  - ble_cts_c - Current Time Service Client
+
+
+#ifndef BLE_CTS_C_ENABLED
+#define BLE_CTS_C_ENABLED 0
+#endif
+
+//  BLE_DIS_ENABLED  - ble_dis - Device Information Service
+
+
+#ifndef BLE_DIS_ENABLED
+#define BLE_DIS_ENABLED 0
+#endif
+
+//  BLE_GLS_ENABLED  - ble_gls - Glucose Service
+
+
+#ifndef BLE_GLS_ENABLED
+#define BLE_GLS_ENABLED 0
+#endif
+
+//  BLE_HIDS_ENABLED  - ble_hids - Human Interface Device Service
+
+
+#ifndef BLE_HIDS_ENABLED
+#define BLE_HIDS_ENABLED 0
+#endif
+
+//  BLE_HRS_C_ENABLED  - ble_hrs_c - Heart Rate Service Client
+
+
+#ifndef BLE_HRS_C_ENABLED
+#define BLE_HRS_C_ENABLED 0
+#endif
+
+//  BLE_HRS_ENABLED  - ble_hrs - Heart Rate Service
+
+
+#ifndef BLE_HRS_ENABLED
+#define BLE_HRS_ENABLED 0
+#endif
+
+//  BLE_HTS_ENABLED  - ble_hts - Health Thermometer Service
+
+
+#ifndef BLE_HTS_ENABLED
+#define BLE_HTS_ENABLED 0
+#endif
+
+//  BLE_IAS_C_ENABLED  - ble_ias_c - Immediate Alert Service Client
+
+
+#ifndef BLE_IAS_C_ENABLED
+#define BLE_IAS_C_ENABLED 0
+#endif
+
+//  BLE_IAS_ENABLED - ble_ias - Immediate Alert Service
+//==========================================================
+#ifndef BLE_IAS_ENABLED
+#define BLE_IAS_ENABLED 0
+#endif
+//  BLE_IAS_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef BLE_IAS_CONFIG_LOG_ENABLED
+#define BLE_IAS_CONFIG_LOG_ENABLED 0
+#endif
+//  BLE_IAS_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef BLE_IAS_CONFIG_LOG_LEVEL
+#define BLE_IAS_CONFIG_LOG_LEVEL 3
+#endif
+
+//  BLE_IAS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef BLE_IAS_CONFIG_INFO_COLOR
+#define BLE_IAS_CONFIG_INFO_COLOR 0
+#endif
+
+//  BLE_IAS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef BLE_IAS_CONFIG_DEBUG_COLOR
+#define BLE_IAS_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  BLE_LBS_C_ENABLED  - ble_lbs_c - Nordic LED Button Service Client
+
+
+#ifndef BLE_LBS_C_ENABLED
+#define BLE_LBS_C_ENABLED 0
+#endif
+
+//  BLE_LBS_ENABLED  - ble_lbs - LED Button Service
+
+
+#ifndef BLE_LBS_ENABLED
+#define BLE_LBS_ENABLED 0
+#endif
+
+//  BLE_LLS_ENABLED  - ble_lls - Link Loss Service
+
+
+#ifndef BLE_LLS_ENABLED
+#define BLE_LLS_ENABLED 0
+#endif
+
+//  BLE_NUS_C_ENABLED  - ble_nus_c - Nordic UART Central Service
+
+
+#ifndef BLE_NUS_C_ENABLED
+#define BLE_NUS_C_ENABLED 0
+#endif
+
+//  BLE_NUS_ENABLED - ble_nus - Nordic UART Service
+//==========================================================
+#ifndef BLE_NUS_ENABLED
+#define BLE_NUS_ENABLED 0
+#endif
+//  BLE_NUS_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef BLE_NUS_CONFIG_LOG_ENABLED
+#define BLE_NUS_CONFIG_LOG_ENABLED 0
+#endif
+//  BLE_NUS_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef BLE_NUS_CONFIG_LOG_LEVEL
+#define BLE_NUS_CONFIG_LOG_LEVEL 3
+#endif
+
+//  BLE_NUS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef BLE_NUS_CONFIG_INFO_COLOR
+#define BLE_NUS_CONFIG_INFO_COLOR 0
+#endif
+
+//  BLE_NUS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef BLE_NUS_CONFIG_DEBUG_COLOR
+#define BLE_NUS_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  BLE_RSCS_C_ENABLED  - ble_rscs_c - Running Speed and Cadence Client
+
+
+#ifndef BLE_RSCS_C_ENABLED
+#define BLE_RSCS_C_ENABLED 0
+#endif
+
+//  BLE_RSCS_ENABLED  - ble_rscs - Running Speed and Cadence Service
+
+
+#ifndef BLE_RSCS_ENABLED
+#define BLE_RSCS_ENABLED 0
+#endif
+
+//  BLE_TPS_ENABLED  - ble_tps - TX Power Service
+
+
+#ifndef BLE_TPS_ENABLED
+#define BLE_TPS_ENABLED 0
+#endif
+
+// 
+//==========================================================
+
+//  nRF_Core
+
+//==========================================================
+//  NRF_MPU_LIB_ENABLED - nrf_mpu_lib - Module for MPU
+//==========================================================
+#ifndef NRF_MPU_LIB_ENABLED
+#define NRF_MPU_LIB_ENABLED 0
+#endif
+//  NRF_MPU_LIB_CLI_CMDS  - Enable CLI commands specific to the module.
+
+
+#ifndef NRF_MPU_LIB_CLI_CMDS
+#define NRF_MPU_LIB_CLI_CMDS 0
+#endif
+
+// 
+
+//  NRF_STACK_GUARD_ENABLED - nrf_stack_guard - Stack guard
+//==========================================================
+#ifndef NRF_STACK_GUARD_ENABLED
+#define NRF_STACK_GUARD_ENABLED 0
+#endif
+//  NRF_STACK_GUARD_CONFIG_SIZE  - Size of the stack guard.
+
+// <5=> 32 bytes
+// <6=> 64 bytes
+// <7=> 128 bytes
+// <8=> 256 bytes
+// <9=> 512 bytes
+// <10=> 1024 bytes
+// <11=> 2048 bytes
+// <12=> 4096 bytes
+
+#ifndef NRF_STACK_GUARD_CONFIG_SIZE
+#define NRF_STACK_GUARD_CONFIG_SIZE 7
+#endif
+
+// 
+
+// 
+//==========================================================
+
+//  nRF_Crypto
+
+//==========================================================
+//  NRF_CRYPTO_ENABLED - nrf_crypto - Cryptography library.
+//==========================================================
+#ifndef NRF_CRYPTO_ENABLED
+#define NRF_CRYPTO_ENABLED 1
+#endif
+//  NRF_CRYPTO_ALLOCATOR  - Memory allocator
+
+
+//  Choose memory allocator used by nrf_crypto. Default is alloca if possible or nrf_malloc otherwise. If 'User macros' are selected, the user has to create 'nrf_crypto_allocator.h' file that contains NRF_CRYPTO_ALLOC, NRF_CRYPTO_FREE, and NRF_CRYPTO_ALLOC_ON_STACK.
+// <0=> Default
+// <1=> User macros
+// <2=> On stack (alloca)
+// <3=> C dynamic memory (malloc)
+// <4=> SDK Memory Manager (nrf_malloc)
+
+#ifndef NRF_CRYPTO_ALLOCATOR
+#define NRF_CRYPTO_ALLOCATOR 0
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_BL_ENABLED - Enable the ARM Cryptocell CC310 reduced backend.
+
+//  The CC310 hardware-accelerated cryptography backend with reduced functionality and footprint (only available on nRF52840).
+//==========================================================
+#ifndef NRF_CRYPTO_BACKEND_CC310_BL_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_BL_ENABLED 0
+#endif
+//  NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP224R1_ENABLED  - Enable the secp224r1 elliptic curve support using CC310_BL.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP224R1_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP224R1_ENABLED 0
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP256R1_ENABLED  - Enable the secp256r1 elliptic curve support using CC310_BL.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP256R1_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP256R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_BL_HASH_SHA256_ENABLED  - CC310_BL SHA-256 hash functionality.
+
+
+//  CC310_BL backend implementation for hardware-accelerated SHA-256.
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_BL_HASH_SHA256_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_BL_HASH_SHA256_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_ENABLED  - nrf_cc310_bl buffers to RAM before running hash operation
+
+
+//  Enabling this makes hashing of addresses in FLASH range possible. Size of buffer allocated for hashing is set by NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_ENABLED 0
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE - nrf_cc310_bl hash outputs digests in little endian
+//  Makes the nrf_cc310_bl hash functions output digests in little endian format. Only for use in nRF SDK DFU!
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE
+#define NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE 4096
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_BL_INTERRUPTS_ENABLED  - Enable Interrupts while support using CC310 bl.
+
+
+//  Select a library version compatible with the configuration. When interrupts are disable, a version named _noint must be used
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_BL_INTERRUPTS_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_BL_INTERRUPTS_ENABLED 1
+#endif
+
+// 
+
+//  NRF_CRYPTO_BACKEND_CC310_ENABLED - Enable the ARM Cryptocell CC310 backend.
+
+//  The CC310 hardware-accelerated cryptography backend (only available on nRF52840).
+//==========================================================
+#ifndef NRF_CRYPTO_BACKEND_CC310_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_ENABLED 0
+#endif
+//  NRF_CRYPTO_BACKEND_CC310_AES_CBC_ENABLED  - Enable the AES CBC mode using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CBC_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_AES_CBC_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_AES_CTR_ENABLED  - Enable the AES CTR mode using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CTR_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_AES_CTR_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_AES_ECB_ENABLED  - Enable the AES ECB mode using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_AES_ECB_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_AES_ECB_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_AES_CBC_MAC_ENABLED  - Enable the AES CBC_MAC mode using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CBC_MAC_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_AES_CBC_MAC_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_AES_CMAC_ENABLED  - Enable the AES CMAC mode using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CMAC_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_AES_CMAC_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_AES_CCM_ENABLED  - Enable the AES CCM mode using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CCM_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_AES_CCM_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_AES_CCM_STAR_ENABLED  - Enable the AES CCM* mode using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CCM_STAR_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_AES_CCM_STAR_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_CHACHA_POLY_ENABLED  - Enable the CHACHA-POLY mode using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_CHACHA_POLY_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_CHACHA_POLY_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R1_ENABLED  - Enable the secp160r1 elliptic curve support using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R1_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R2_ENABLED  - Enable the secp160r2 elliptic curve support using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R2_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R2_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_ECC_SECP192R1_ENABLED  - Enable the secp192r1 elliptic curve support using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP192R1_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP192R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_ECC_SECP224R1_ENABLED  - Enable the secp224r1 elliptic curve support using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP224R1_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP224R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_ECC_SECP256R1_ENABLED  - Enable the secp256r1 elliptic curve support using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP256R1_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP256R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_ECC_SECP384R1_ENABLED  - Enable the secp384r1 elliptic curve support using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP384R1_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP384R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_ECC_SECP521R1_ENABLED  - Enable the secp521r1 elliptic curve support using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP521R1_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP521R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_ECC_SECP160K1_ENABLED  - Enable the secp160k1 elliptic curve support using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP160K1_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160K1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_ECC_SECP192K1_ENABLED  - Enable the secp192k1 elliptic curve support using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP192K1_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP192K1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_ECC_SECP224K1_ENABLED  - Enable the secp224k1 elliptic curve support using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP224K1_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP224K1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_ECC_SECP256K1_ENABLED  - Enable the secp256k1 elliptic curve support using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP256K1_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP256K1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_ECC_CURVE25519_ENABLED  - Enable the Curve25519 curve support using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_CURVE25519_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_ECC_CURVE25519_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_ECC_ED25519_ENABLED  - Enable the Ed25519 curve support using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_ED25519_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_ECC_ED25519_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_HASH_SHA256_ENABLED  - CC310 SHA-256 hash functionality.
+
+
+//  CC310 backend implementation for hardware-accelerated SHA-256.
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_HASH_SHA256_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_HASH_SHA256_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_HASH_SHA512_ENABLED  - CC310 SHA-512 hash functionality
+
+
+//  CC310 backend implementation for SHA-512 (in software).
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_HASH_SHA512_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_HASH_SHA512_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_HMAC_SHA256_ENABLED  - CC310 HMAC using SHA-256
+
+
+//  CC310 backend implementation for HMAC using hardware-accelerated SHA-256.
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_HMAC_SHA256_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_HMAC_SHA256_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_HMAC_SHA512_ENABLED  - CC310 HMAC using SHA-512
+
+
+//  CC310 backend implementation for HMAC using SHA-512 (in software).
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_HMAC_SHA512_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_HMAC_SHA512_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_RNG_ENABLED  - Enable RNG support using CC310.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_RNG_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_RNG_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_CC310_INTERRUPTS_ENABLED  - Enable Interrupts while support using CC310.
+
+
+//  Select a library version compatible with the configuration. When interrupts are disable, a version named _noint must be used
+
+#ifndef NRF_CRYPTO_BACKEND_CC310_INTERRUPTS_ENABLED
+#define NRF_CRYPTO_BACKEND_CC310_INTERRUPTS_ENABLED 1
+#endif
+
+// 
+
+//  NRF_CRYPTO_BACKEND_CIFRA_ENABLED - Enable the Cifra backend.
+//==========================================================
+#ifndef NRF_CRYPTO_BACKEND_CIFRA_ENABLED
+#define NRF_CRYPTO_BACKEND_CIFRA_ENABLED 0
+#endif
+//  NRF_CRYPTO_BACKEND_CIFRA_AES_EAX_ENABLED  - Enable the AES EAX mode using Cifra.
+
+
+#ifndef NRF_CRYPTO_BACKEND_CIFRA_AES_EAX_ENABLED
+#define NRF_CRYPTO_BACKEND_CIFRA_AES_EAX_ENABLED 1
+#endif
+
+// 
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_ENABLED - Enable the mbed TLS backend.
+//==========================================================
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_ENABLED 0
+#endif
+//  NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_ENABLED  - Enable the AES CBC mode mbed TLS.
+
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_AES_CTR_ENABLED  - Enable the AES CTR mode using mbed TLS.
+
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CTR_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CTR_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_AES_CFB_ENABLED  - Enable the AES CFB mode using mbed TLS.
+
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CFB_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CFB_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_AES_ECB_ENABLED  - Enable the AES ECB mode using mbed TLS.
+
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_ECB_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_ECB_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_MAC_ENABLED  - Enable the AES CBC MAC mode using mbed TLS.
+
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_MAC_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_MAC_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_AES_CMAC_ENABLED  - Enable the AES CMAC mode using mbed TLS.
+
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CMAC_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CMAC_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_AES_CCM_ENABLED  - Enable the AES CCM mode using mbed TLS.
+
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CCM_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CCM_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_AES_GCM_ENABLED  - Enable the AES GCM mode using mbed TLS.
+
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_GCM_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_GCM_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192R1_ENABLED  - Enable secp192r1 (NIST 192-bit) curve
+
+
+//  Enable this setting if you need secp192r1 (NIST 192-bit) support using MBEDTLS
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192R1_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224R1_ENABLED  - Enable secp224r1 (NIST 224-bit) curve
+
+
+//  Enable this setting if you need secp224r1 (NIST 224-bit) support using MBEDTLS
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224R1_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256R1_ENABLED  - Enable secp256r1 (NIST 256-bit) curve
+
+
+//  Enable this setting if you need secp256r1 (NIST 256-bit) support using MBEDTLS
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256R1_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP384R1_ENABLED  - Enable secp384r1 (NIST 384-bit) curve
+
+
+//  Enable this setting if you need secp384r1 (NIST 384-bit) support using MBEDTLS
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP384R1_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP384R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP521R1_ENABLED  - Enable secp521r1 (NIST 521-bit) curve
+
+
+//  Enable this setting if you need secp521r1 (NIST 521-bit) support using MBEDTLS
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP521R1_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP521R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192K1_ENABLED  - Enable secp192k1 (Koblitz 192-bit) curve
+
+
+//  Enable this setting if you need secp192k1 (Koblitz 192-bit) support using MBEDTLS
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192K1_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192K1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224K1_ENABLED  - Enable secp224k1 (Koblitz 224-bit) curve
+
+
+//  Enable this setting if you need secp224k1 (Koblitz 224-bit) support using MBEDTLS
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224K1_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224K1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256K1_ENABLED  - Enable secp256k1 (Koblitz 256-bit) curve
+
+
+//  Enable this setting if you need secp256k1 (Koblitz 256-bit) support using MBEDTLS
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256K1_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256K1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP256R1_ENABLED  - Enable bp256r1 (Brainpool 256-bit) curve
+
+
+//  Enable this setting if you need bp256r1 (Brainpool 256-bit) support using MBEDTLS
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP256R1_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP256R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP384R1_ENABLED  - Enable bp384r1 (Brainpool 384-bit) curve
+
+
+//  Enable this setting if you need bp384r1 (Brainpool 384-bit) support using MBEDTLS
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP384R1_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP384R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP512R1_ENABLED  - Enable bp512r1 (Brainpool 512-bit) curve
+
+
+//  Enable this setting if you need bp512r1 (Brainpool 512-bit) support using MBEDTLS
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP512R1_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP512R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_CURVE25519_ENABLED  - Enable Curve25519 curve
+
+
+//  Enable this setting if you need Curve25519 support using MBEDTLS
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_CURVE25519_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_CURVE25519_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA256_ENABLED  - Enable mbed TLS SHA-256 hash functionality.
+
+
+//  mbed TLS backend implementation for SHA-256.
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA256_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA256_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA512_ENABLED  - Enable mbed TLS SHA-512 hash functionality.
+
+
+//  mbed TLS backend implementation for SHA-512.
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA512_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA512_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA256_ENABLED  - Enable mbed TLS HMAC using SHA-256.
+
+
+//  mbed TLS backend implementation for HMAC using SHA-256.
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA256_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA256_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA512_ENABLED  - Enable mbed TLS HMAC using SHA-512.
+
+
+//  mbed TLS backend implementation for HMAC using SHA-512.
+
+#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA512_ENABLED
+#define NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA512_ENABLED 1
+#endif
+
+// 
+
+//  NRF_CRYPTO_BACKEND_MICRO_ECC_ENABLED - Enable the micro-ecc backend.
+//==========================================================
+#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ENABLED
+#define NRF_CRYPTO_BACKEND_MICRO_ECC_ENABLED 0
+#endif
+//  NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP192R1_ENABLED  - Enable secp192r1 (NIST 192-bit) curve
+
+
+//  Enable this setting if you need secp192r1 (NIST 192-bit) support using micro-ecc
+
+#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP192R1_ENABLED
+#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP192R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP224R1_ENABLED  - Enable secp224r1 (NIST 224-bit) curve
+
+
+//  Enable this setting if you need secp224r1 (NIST 224-bit) support using micro-ecc
+
+#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP224R1_ENABLED
+#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP224R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256R1_ENABLED  - Enable secp256r1 (NIST 256-bit) curve
+
+
+//  Enable this setting if you need secp256r1 (NIST 256-bit) support using micro-ecc
+
+#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256R1_ENABLED
+#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256K1_ENABLED  - Enable secp256k1 (Koblitz 256-bit) curve
+
+
+//  Enable this setting if you need secp256k1 (Koblitz 256-bit) support using micro-ecc
+
+#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256K1_ENABLED
+#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256K1_ENABLED 1
+#endif
+
+// 
+
+//  NRF_CRYPTO_BACKEND_NRF_HW_RNG_ENABLED - Enable the nRF HW RNG backend.
+
+//  The nRF HW backend provide access to RNG peripheral in nRF5x devices.
+//==========================================================
+#ifndef NRF_CRYPTO_BACKEND_NRF_HW_RNG_ENABLED
+#define NRF_CRYPTO_BACKEND_NRF_HW_RNG_ENABLED 0
+#endif
+//  NRF_CRYPTO_BACKEND_NRF_HW_RNG_MBEDTLS_CTR_DRBG_ENABLED  - Enable mbed TLS CTR-DRBG algorithm.
+
+
+//  Enable mbed TLS CTR-DRBG standardized by NIST (NIST SP 800-90A Rev. 1). The nRF HW RNG is used as an entropy source for seeding.
+
+#ifndef NRF_CRYPTO_BACKEND_NRF_HW_RNG_MBEDTLS_CTR_DRBG_ENABLED
+#define NRF_CRYPTO_BACKEND_NRF_HW_RNG_MBEDTLS_CTR_DRBG_ENABLED 1
+#endif
+
+// 
+
+//  NRF_CRYPTO_BACKEND_NRF_SW_ENABLED - Enable the legacy nRFx sw for crypto.
+
+//  The nRF SW cryptography backend (only used in bootloader context).
+//==========================================================
+#ifndef NRF_CRYPTO_BACKEND_NRF_SW_ENABLED
+#define NRF_CRYPTO_BACKEND_NRF_SW_ENABLED 0
+#endif
+//  NRF_CRYPTO_BACKEND_NRF_SW_HASH_SHA256_ENABLED  - nRF SW hash backend support for SHA-256
+
+
+//  The nRF SW backend provide access to nRF SDK legacy hash implementation of SHA-256.
+
+#ifndef NRF_CRYPTO_BACKEND_NRF_SW_HASH_SHA256_ENABLED
+#define NRF_CRYPTO_BACKEND_NRF_SW_HASH_SHA256_ENABLED 1
+#endif
+
+// 
+
+//  NRF_CRYPTO_BACKEND_OBERON_ENABLED - Enable the Oberon backend
+
+//  The Oberon backend
+//==========================================================
+#ifndef NRF_CRYPTO_BACKEND_OBERON_ENABLED
+#define NRF_CRYPTO_BACKEND_OBERON_ENABLED 0
+#endif
+//  NRF_CRYPTO_BACKEND_OBERON_CHACHA_POLY_ENABLED  - Enable the CHACHA-POLY mode using Oberon.
+
+
+#ifndef NRF_CRYPTO_BACKEND_OBERON_CHACHA_POLY_ENABLED
+#define NRF_CRYPTO_BACKEND_OBERON_CHACHA_POLY_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_OBERON_ECC_SECP256R1_ENABLED  - Enable secp256r1 curve
+
+
+//  Enable this setting if you need secp256r1 curve support using Oberon library
+
+#ifndef NRF_CRYPTO_BACKEND_OBERON_ECC_SECP256R1_ENABLED
+#define NRF_CRYPTO_BACKEND_OBERON_ECC_SECP256R1_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_OBERON_ECC_CURVE25519_ENABLED  - Enable Curve25519 ECDH
+
+
+//  Enable this setting if you need Curve25519 ECDH support using Oberon library
+
+#ifndef NRF_CRYPTO_BACKEND_OBERON_ECC_CURVE25519_ENABLED
+#define NRF_CRYPTO_BACKEND_OBERON_ECC_CURVE25519_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_OBERON_ECC_ED25519_ENABLED  - Enable Ed25519 signature scheme
+
+
+//  Enable this setting if you need Ed25519 support using Oberon library
+
+#ifndef NRF_CRYPTO_BACKEND_OBERON_ECC_ED25519_ENABLED
+#define NRF_CRYPTO_BACKEND_OBERON_ECC_ED25519_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_OBERON_HASH_SHA256_ENABLED  - Oberon SHA-256 hash functionality
+
+
+//  Oberon backend implementation for SHA-256.
+
+#ifndef NRF_CRYPTO_BACKEND_OBERON_HASH_SHA256_ENABLED
+#define NRF_CRYPTO_BACKEND_OBERON_HASH_SHA256_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_OBERON_HASH_SHA512_ENABLED  - Oberon SHA-512 hash functionality
+
+
+//  Oberon backend implementation for SHA-512.
+
+#ifndef NRF_CRYPTO_BACKEND_OBERON_HASH_SHA512_ENABLED
+#define NRF_CRYPTO_BACKEND_OBERON_HASH_SHA512_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA256_ENABLED  - Oberon HMAC using SHA-256
+
+
+//  Oberon backend implementation for HMAC using SHA-256.
+
+#ifndef NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA256_ENABLED
+#define NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA256_ENABLED 1
+#endif
+
+//  NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA512_ENABLED  - Oberon HMAC using SHA-512
+
+
+//  Oberon backend implementation for HMAC using SHA-512.
+
+#ifndef NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA512_ENABLED
+#define NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA512_ENABLED 1
+#endif
+
+// 
+
+//  NRF_CRYPTO_BACKEND_OPTIGA_ENABLED - Enable the nrf_crypto Optiga Trust X backend.
+
+//  Enables the nrf_crypto backend for Optiga Trust X devices.
+//==========================================================
+#ifndef NRF_CRYPTO_BACKEND_OPTIGA_ENABLED
+#define NRF_CRYPTO_BACKEND_OPTIGA_ENABLED 0
+#endif
+//  NRF_CRYPTO_BACKEND_OPTIGA_RNG_ENABLED  - Optiga backend support for RNG
+
+
+//  The Optiga backend provide external chip RNG.
+
+#ifndef NRF_CRYPTO_BACKEND_OPTIGA_RNG_ENABLED
+#define NRF_CRYPTO_BACKEND_OPTIGA_RNG_ENABLED 0
+#endif
+
+//  NRF_CRYPTO_BACKEND_OPTIGA_ECC_SECP256R1_ENABLED  - Optiga backend support for ECC secp256r1
+
+
+//  The Optiga backend provide external chip ECC using secp256r1.
+
+#ifndef NRF_CRYPTO_BACKEND_OPTIGA_ECC_SECP256R1_ENABLED
+#define NRF_CRYPTO_BACKEND_OPTIGA_ECC_SECP256R1_ENABLED 1
+#endif
+
+// 
+
+//  NRF_CRYPTO_CURVE25519_BIG_ENDIAN_ENABLED  - Big-endian byte order in raw Curve25519 data
+
+
+//  Enable big-endian byte order in Curve25519 API, if set to 1. Use little-endian, if set to 0.
+
+#ifndef NRF_CRYPTO_CURVE25519_BIG_ENDIAN_ENABLED
+#define NRF_CRYPTO_CURVE25519_BIG_ENDIAN_ENABLED 0
+#endif
+
+// 
+
+// 
+//==========================================================
+
+//  nRF_DFU
+
+//==========================================================
+//  ble_dfu - Device Firmware Update
+
+//==========================================================
+//  BLE_DFU_ENABLED  - Enable DFU Service.
+
+
+#ifndef BLE_DFU_ENABLED
+#define BLE_DFU_ENABLED 0
+#endif
+
+//  NRF_DFU_BLE_BUTTONLESS_SUPPORTS_BONDS  - Buttonless DFU supports bonds.
+
+
+#ifndef NRF_DFU_BLE_BUTTONLESS_SUPPORTS_BONDS
+#define NRF_DFU_BLE_BUTTONLESS_SUPPORTS_BONDS 0
+#endif
+
+// 
+//==========================================================
+
+// 
+//==========================================================
+
+//  nRF_Drivers
+
+//==========================================================
+//  COMP_ENABLED - nrf_drv_comp - COMP peripheral driver - legacy layer
+//==========================================================
+#ifndef COMP_ENABLED
+#define COMP_ENABLED 0
+#endif
+//  COMP_CONFIG_REF  - Reference voltage
+
+// <0=> Internal 1.2V
+// <1=> Internal 1.8V
+// <2=> Internal 2.4V
+// <4=> VDD
+// <7=> ARef
+
+#ifndef COMP_CONFIG_REF
+#define COMP_CONFIG_REF 1
+#endif
+
+//  COMP_CONFIG_MAIN_MODE  - Main mode
+
+// <0=> Single ended
+// <1=> Differential
+
+#ifndef COMP_CONFIG_MAIN_MODE
+#define COMP_CONFIG_MAIN_MODE 0
+#endif
+
+//  COMP_CONFIG_SPEED_MODE  - Speed mode
+
+// <0=> Low power
+// <1=> Normal
+// <2=> High speed
+
+#ifndef COMP_CONFIG_SPEED_MODE
+#define COMP_CONFIG_SPEED_MODE 2
+#endif
+
+//  COMP_CONFIG_HYST  - Hystheresis
+
+// <0=> No
+// <1=> 50mV
+
+#ifndef COMP_CONFIG_HYST
+#define COMP_CONFIG_HYST 0
+#endif
+
+//  COMP_CONFIG_ISOURCE  - Current Source
+
+// <0=> Off
+// <1=> 2.5 uA
+// <2=> 5 uA
+// <3=> 10 uA
+
+#ifndef COMP_CONFIG_ISOURCE
+#define COMP_CONFIG_ISOURCE 0
+#endif
+
+//  COMP_CONFIG_INPUT  - Analog input
+
+// <0=> 0
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef COMP_CONFIG_INPUT
+#define COMP_CONFIG_INPUT 0
+#endif
+
+//  COMP_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef COMP_CONFIG_IRQ_PRIORITY
+#define COMP_CONFIG_IRQ_PRIORITY 6
+#endif
+
+// 
+
+//  EGU_ENABLED  - nrf_drv_swi - SWI(EGU) peripheral driver - legacy layer
+
+
+#ifndef EGU_ENABLED
+#define EGU_ENABLED 0
+#endif
+
+//  GPIOTE_ENABLED - nrf_drv_gpiote - GPIOTE peripheral driver - legacy layer
+//==========================================================
+#ifndef GPIOTE_ENABLED
+#define GPIOTE_ENABLED 0
+#endif
+//  GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins
+#ifndef GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS
+#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1
+#endif
+
+//  GPIOTE_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef GPIOTE_CONFIG_IRQ_PRIORITY
+#define GPIOTE_CONFIG_IRQ_PRIORITY 6
+#endif
+
+// 
+
+//  I2S_ENABLED - nrf_drv_i2s - I2S peripheral driver - legacy layer
+//==========================================================
+#ifndef I2S_ENABLED
+#define I2S_ENABLED 0
+#endif
+//  I2S_CONFIG_SCK_PIN - SCK pin  <0-31>
+
+
+#ifndef I2S_CONFIG_SCK_PIN
+#define I2S_CONFIG_SCK_PIN 31
+#endif
+
+//  I2S_CONFIG_LRCK_PIN - LRCK pin  <1-31>
+
+
+#ifndef I2S_CONFIG_LRCK_PIN
+#define I2S_CONFIG_LRCK_PIN 30
+#endif
+
+//  I2S_CONFIG_MCK_PIN - MCK pin
+#ifndef I2S_CONFIG_MCK_PIN
+#define I2S_CONFIG_MCK_PIN 255
+#endif
+
+//  I2S_CONFIG_SDOUT_PIN - SDOUT pin  <0-31>
+
+
+#ifndef I2S_CONFIG_SDOUT_PIN
+#define I2S_CONFIG_SDOUT_PIN 29
+#endif
+
+//  I2S_CONFIG_SDIN_PIN - SDIN pin  <0-31>
+
+
+#ifndef I2S_CONFIG_SDIN_PIN
+#define I2S_CONFIG_SDIN_PIN 28
+#endif
+
+//  I2S_CONFIG_MASTER  - Mode
+
+// <0=> Master
+// <1=> Slave
+
+#ifndef I2S_CONFIG_MASTER
+#define I2S_CONFIG_MASTER 0
+#endif
+
+//  I2S_CONFIG_FORMAT  - Format
+
+// <0=> I2S
+// <1=> Aligned
+
+#ifndef I2S_CONFIG_FORMAT
+#define I2S_CONFIG_FORMAT 0
+#endif
+
+//  I2S_CONFIG_ALIGN  - Alignment
+
+// <0=> Left
+// <1=> Right
+
+#ifndef I2S_CONFIG_ALIGN
+#define I2S_CONFIG_ALIGN 0
+#endif
+
+//  I2S_CONFIG_SWIDTH  - Sample width (bits)
+
+// <0=> 8
+// <1=> 16
+// <2=> 24
+
+#ifndef I2S_CONFIG_SWIDTH
+#define I2S_CONFIG_SWIDTH 1
+#endif
+
+//  I2S_CONFIG_CHANNELS  - Channels
+
+// <0=> Stereo
+// <1=> Left
+// <2=> Right
+
+#ifndef I2S_CONFIG_CHANNELS
+#define I2S_CONFIG_CHANNELS 1
+#endif
+
+//  I2S_CONFIG_MCK_SETUP  - MCK behavior
+
+// <0=> Disabled
+// <2147483648=> 32MHz/2
+// <1342177280=> 32MHz/3
+// <1073741824=> 32MHz/4
+// <805306368=> 32MHz/5
+// <671088640=> 32MHz/6
+// <536870912=> 32MHz/8
+// <402653184=> 32MHz/10
+// <369098752=> 32MHz/11
+// <285212672=> 32MHz/15
+// <268435456=> 32MHz/16
+// <201326592=> 32MHz/21
+// <184549376=> 32MHz/23
+// <142606336=> 32MHz/30
+// <138412032=> 32MHz/31
+// <134217728=> 32MHz/32
+// <100663296=> 32MHz/42
+// <68157440=> 32MHz/63
+// <34340864=> 32MHz/125
+
+#ifndef I2S_CONFIG_MCK_SETUP
+#define I2S_CONFIG_MCK_SETUP 536870912
+#endif
+
+//  I2S_CONFIG_RATIO  - MCK/LRCK ratio
+
+// <0=> 32x
+// <1=> 48x
+// <2=> 64x
+// <3=> 96x
+// <4=> 128x
+// <5=> 192x
+// <6=> 256x
+// <7=> 384x
+// <8=> 512x
+
+#ifndef I2S_CONFIG_RATIO
+#define I2S_CONFIG_RATIO 2000
+#endif
+
+//  I2S_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef I2S_CONFIG_IRQ_PRIORITY
+#define I2S_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  I2S_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef I2S_CONFIG_LOG_ENABLED
+#define I2S_CONFIG_LOG_ENABLED 0
+#endif
+//  I2S_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef I2S_CONFIG_LOG_LEVEL
+#define I2S_CONFIG_LOG_LEVEL 3
+#endif
+
+//  I2S_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef I2S_CONFIG_INFO_COLOR
+#define I2S_CONFIG_INFO_COLOR 0
+#endif
+
+//  I2S_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef I2S_CONFIG_DEBUG_COLOR
+#define I2S_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  LPCOMP_ENABLED - nrf_drv_lpcomp - LPCOMP peripheral driver - legacy layer
+//==========================================================
+#ifndef LPCOMP_ENABLED
+#define LPCOMP_ENABLED 0
+#endif
+//  LPCOMP_CONFIG_REFERENCE  - Reference voltage
+
+// <0=> Supply 1/8
+// <1=> Supply 2/8
+// <2=> Supply 3/8
+// <3=> Supply 4/8
+// <4=> Supply 5/8
+// <5=> Supply 6/8
+// <6=> Supply 7/8
+// <8=> Supply 1/16 (nRF52)
+// <9=> Supply 3/16 (nRF52)
+// <10=> Supply 5/16 (nRF52)
+// <11=> Supply 7/16 (nRF52)
+// <12=> Supply 9/16 (nRF52)
+// <13=> Supply 11/16 (nRF52)
+// <14=> Supply 13/16 (nRF52)
+// <15=> Supply 15/16 (nRF52)
+// <7=> External Ref 0
+// <65543=> External Ref 1
+
+#ifndef LPCOMP_CONFIG_REFERENCE
+#define LPCOMP_CONFIG_REFERENCE 3
+#endif
+
+//  LPCOMP_CONFIG_DETECTION  - Detection
+
+// <0=> Crossing
+// <1=> Up
+// <2=> Down
+
+#ifndef LPCOMP_CONFIG_DETECTION
+#define LPCOMP_CONFIG_DETECTION 2
+#endif
+
+//  LPCOMP_CONFIG_INPUT  - Analog input
+
+// <0=> 0
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef LPCOMP_CONFIG_INPUT
+#define LPCOMP_CONFIG_INPUT 0
+#endif
+
+//  LPCOMP_CONFIG_HYST  - Hysteresis
+
+
+#ifndef LPCOMP_CONFIG_HYST
+#define LPCOMP_CONFIG_HYST 0
+#endif
+
+//  LPCOMP_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef LPCOMP_CONFIG_IRQ_PRIORITY
+#define LPCOMP_CONFIG_IRQ_PRIORITY 6
+#endif
+
+// 
+
+//  NRFX_CLOCK_ENABLED - nrfx_clock - CLOCK peripheral driver
+//==========================================================
+#ifndef NRFX_CLOCK_ENABLED
+#define NRFX_CLOCK_ENABLED 0
+#endif
+//  NRFX_CLOCK_CONFIG_LF_SRC  - LF Clock Source
+
+// <0=> RC
+// <1=> XTAL
+// <2=> Synth
+// <131073=> External Low Swing
+// <196609=> External Full Swing
+
+#ifndef NRFX_CLOCK_CONFIG_LF_SRC
+#define NRFX_CLOCK_CONFIG_LF_SRC 1
+#endif
+
+//  NRFX_CLOCK_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_CLOCK_CONFIG_IRQ_PRIORITY
+#define NRFX_CLOCK_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_CLOCK_CONFIG_LOG_ENABLED
+#define NRFX_CLOCK_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_CLOCK_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_CLOCK_CONFIG_LOG_LEVEL
+#define NRFX_CLOCK_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_CLOCK_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_CLOCK_CONFIG_INFO_COLOR
+#define NRFX_CLOCK_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_CLOCK_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_CLOCK_CONFIG_DEBUG_COLOR
+#define NRFX_CLOCK_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_COMP_ENABLED - nrfx_comp - COMP peripheral driver
+//==========================================================
+#ifndef NRFX_COMP_ENABLED
+#define NRFX_COMP_ENABLED 0
+#endif
+//  NRFX_COMP_CONFIG_REF  - Reference voltage
+
+// <0=> Internal 1.2V
+// <1=> Internal 1.8V
+// <2=> Internal 2.4V
+// <4=> VDD
+// <7=> ARef
+
+#ifndef NRFX_COMP_CONFIG_REF
+#define NRFX_COMP_CONFIG_REF 1
+#endif
+
+//  NRFX_COMP_CONFIG_MAIN_MODE  - Main mode
+
+// <0=> Single ended
+// <1=> Differential
+
+#ifndef NRFX_COMP_CONFIG_MAIN_MODE
+#define NRFX_COMP_CONFIG_MAIN_MODE 0
+#endif
+
+//  NRFX_COMP_CONFIG_SPEED_MODE  - Speed mode
+
+// <0=> Low power
+// <1=> Normal
+// <2=> High speed
+
+#ifndef NRFX_COMP_CONFIG_SPEED_MODE
+#define NRFX_COMP_CONFIG_SPEED_MODE 2
+#endif
+
+//  NRFX_COMP_CONFIG_HYST  - Hystheresis
+
+// <0=> No
+// <1=> 50mV
+
+#ifndef NRFX_COMP_CONFIG_HYST
+#define NRFX_COMP_CONFIG_HYST 0
+#endif
+
+//  NRFX_COMP_CONFIG_ISOURCE  - Current Source
+
+// <0=> Off
+// <1=> 2.5 uA
+// <2=> 5 uA
+// <3=> 10 uA
+
+#ifndef NRFX_COMP_CONFIG_ISOURCE
+#define NRFX_COMP_CONFIG_ISOURCE 0
+#endif
+
+//  NRFX_COMP_CONFIG_INPUT  - Analog input
+
+// <0=> 0
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_COMP_CONFIG_INPUT
+#define NRFX_COMP_CONFIG_INPUT 0
+#endif
+
+//  NRFX_COMP_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_COMP_CONFIG_IRQ_PRIORITY
+#define NRFX_COMP_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_COMP_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_COMP_CONFIG_LOG_ENABLED
+#define NRFX_COMP_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_COMP_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_COMP_CONFIG_LOG_LEVEL
+#define NRFX_COMP_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_COMP_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_COMP_CONFIG_INFO_COLOR
+#define NRFX_COMP_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_COMP_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_COMP_CONFIG_DEBUG_COLOR
+#define NRFX_COMP_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_GPIOTE_ENABLED - nrfx_gpiote - GPIOTE peripheral driver
+//==========================================================
+#ifndef NRFX_GPIOTE_ENABLED
+#define NRFX_GPIOTE_ENABLED 0
+#endif
+//  NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins
+#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS
+#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1
+#endif
+
+//  NRFX_GPIOTE_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_GPIOTE_CONFIG_IRQ_PRIORITY
+#define NRFX_GPIOTE_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED
+#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_GPIOTE_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL
+#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_GPIOTE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_GPIOTE_CONFIG_INFO_COLOR
+#define NRFX_GPIOTE_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_GPIOTE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_GPIOTE_CONFIG_DEBUG_COLOR
+#define NRFX_GPIOTE_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_I2S_ENABLED - nrfx_i2s - I2S peripheral driver
+//==========================================================
+#ifndef NRFX_I2S_ENABLED
+#define NRFX_I2S_ENABLED 0
+#endif
+//  NRFX_I2S_CONFIG_SCK_PIN - SCK pin  <0-31>
+
+
+#ifndef NRFX_I2S_CONFIG_SCK_PIN
+#define NRFX_I2S_CONFIG_SCK_PIN 31
+#endif
+
+//  NRFX_I2S_CONFIG_LRCK_PIN - LRCK pin  <1-31>
+
+
+#ifndef NRFX_I2S_CONFIG_LRCK_PIN
+#define NRFX_I2S_CONFIG_LRCK_PIN 30
+#endif
+
+//  NRFX_I2S_CONFIG_MCK_PIN - MCK pin
+#ifndef NRFX_I2S_CONFIG_MCK_PIN
+#define NRFX_I2S_CONFIG_MCK_PIN 255
+#endif
+
+//  NRFX_I2S_CONFIG_SDOUT_PIN - SDOUT pin  <0-31>
+
+
+#ifndef NRFX_I2S_CONFIG_SDOUT_PIN
+#define NRFX_I2S_CONFIG_SDOUT_PIN 29
+#endif
+
+//  NRFX_I2S_CONFIG_SDIN_PIN - SDIN pin  <0-31>
+
+
+#ifndef NRFX_I2S_CONFIG_SDIN_PIN
+#define NRFX_I2S_CONFIG_SDIN_PIN 28
+#endif
+
+//  NRFX_I2S_CONFIG_MASTER  - Mode
+
+// <0=> Master
+// <1=> Slave
+
+#ifndef NRFX_I2S_CONFIG_MASTER
+#define NRFX_I2S_CONFIG_MASTER 0
+#endif
+
+//  NRFX_I2S_CONFIG_FORMAT  - Format
+
+// <0=> I2S
+// <1=> Aligned
+
+#ifndef NRFX_I2S_CONFIG_FORMAT
+#define NRFX_I2S_CONFIG_FORMAT 0
+#endif
+
+//  NRFX_I2S_CONFIG_ALIGN  - Alignment
+
+// <0=> Left
+// <1=> Right
+
+#ifndef NRFX_I2S_CONFIG_ALIGN
+#define NRFX_I2S_CONFIG_ALIGN 0
+#endif
+
+//  NRFX_I2S_CONFIG_SWIDTH  - Sample width (bits)
+
+// <0=> 8
+// <1=> 16
+// <2=> 24
+
+#ifndef NRFX_I2S_CONFIG_SWIDTH
+#define NRFX_I2S_CONFIG_SWIDTH 1
+#endif
+
+//  NRFX_I2S_CONFIG_CHANNELS  - Channels
+
+// <0=> Stereo
+// <1=> Left
+// <2=> Right
+
+#ifndef NRFX_I2S_CONFIG_CHANNELS
+#define NRFX_I2S_CONFIG_CHANNELS 1
+#endif
+
+//  NRFX_I2S_CONFIG_MCK_SETUP  - MCK behavior
+
+// <0=> Disabled
+// <2147483648=> 32MHz/2
+// <1342177280=> 32MHz/3
+// <1073741824=> 32MHz/4
+// <805306368=> 32MHz/5
+// <671088640=> 32MHz/6
+// <536870912=> 32MHz/8
+// <402653184=> 32MHz/10
+// <369098752=> 32MHz/11
+// <285212672=> 32MHz/15
+// <268435456=> 32MHz/16
+// <201326592=> 32MHz/21
+// <184549376=> 32MHz/23
+// <142606336=> 32MHz/30
+// <138412032=> 32MHz/31
+// <134217728=> 32MHz/32
+// <100663296=> 32MHz/42
+// <68157440=> 32MHz/63
+// <34340864=> 32MHz/125
+
+#ifndef NRFX_I2S_CONFIG_MCK_SETUP
+#define NRFX_I2S_CONFIG_MCK_SETUP 536870912
+#endif
+
+//  NRFX_I2S_CONFIG_RATIO  - MCK/LRCK ratio
+
+// <0=> 32x
+// <1=> 48x
+// <2=> 64x
+// <3=> 96x
+// <4=> 128x
+// <5=> 192x
+// <6=> 256x
+// <7=> 384x
+// <8=> 512x
+
+#ifndef NRFX_I2S_CONFIG_RATIO
+#define NRFX_I2S_CONFIG_RATIO 2000
+#endif
+
+//  NRFX_I2S_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_I2S_CONFIG_IRQ_PRIORITY
+#define NRFX_I2S_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_I2S_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_I2S_CONFIG_LOG_ENABLED
+#define NRFX_I2S_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_I2S_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_I2S_CONFIG_LOG_LEVEL
+#define NRFX_I2S_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_I2S_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_I2S_CONFIG_INFO_COLOR
+#define NRFX_I2S_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_I2S_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_I2S_CONFIG_DEBUG_COLOR
+#define NRFX_I2S_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_LPCOMP_ENABLED - nrfx_lpcomp - LPCOMP peripheral driver
+//==========================================================
+#ifndef NRFX_LPCOMP_ENABLED
+#define NRFX_LPCOMP_ENABLED 0
+#endif
+//  NRFX_LPCOMP_CONFIG_REFERENCE  - Reference voltage
+
+// <0=> Supply 1/8
+// <1=> Supply 2/8
+// <2=> Supply 3/8
+// <3=> Supply 4/8
+// <4=> Supply 5/8
+// <5=> Supply 6/8
+// <6=> Supply 7/8
+// <8=> Supply 1/16 (nRF52)
+// <9=> Supply 3/16 (nRF52)
+// <10=> Supply 5/16 (nRF52)
+// <11=> Supply 7/16 (nRF52)
+// <12=> Supply 9/16 (nRF52)
+// <13=> Supply 11/16 (nRF52)
+// <14=> Supply 13/16 (nRF52)
+// <15=> Supply 15/16 (nRF52)
+// <7=> External Ref 0
+// <65543=> External Ref 1
+
+#ifndef NRFX_LPCOMP_CONFIG_REFERENCE
+#define NRFX_LPCOMP_CONFIG_REFERENCE 3
+#endif
+
+//  NRFX_LPCOMP_CONFIG_DETECTION  - Detection
+
+// <0=> Crossing
+// <1=> Up
+// <2=> Down
+
+#ifndef NRFX_LPCOMP_CONFIG_DETECTION
+#define NRFX_LPCOMP_CONFIG_DETECTION 2
+#endif
+
+//  NRFX_LPCOMP_CONFIG_INPUT  - Analog input
+
+// <0=> 0
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_LPCOMP_CONFIG_INPUT
+#define NRFX_LPCOMP_CONFIG_INPUT 0
+#endif
+
+//  NRFX_LPCOMP_CONFIG_HYST  - Hysteresis
+
+
+#ifndef NRFX_LPCOMP_CONFIG_HYST
+#define NRFX_LPCOMP_CONFIG_HYST 0
+#endif
+
+//  NRFX_LPCOMP_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_LPCOMP_CONFIG_IRQ_PRIORITY
+#define NRFX_LPCOMP_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_LPCOMP_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_LPCOMP_CONFIG_LOG_ENABLED
+#define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_LPCOMP_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL
+#define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_LPCOMP_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_LPCOMP_CONFIG_INFO_COLOR
+#define NRFX_LPCOMP_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_LPCOMP_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_LPCOMP_CONFIG_DEBUG_COLOR
+#define NRFX_LPCOMP_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_NFCT_ENABLED - nrfx_nfct - NFCT peripheral driver
+//==========================================================
+#ifndef NRFX_NFCT_ENABLED
+#define NRFX_NFCT_ENABLED 0
+#endif
+//  NRFX_NFCT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_NFCT_CONFIG_IRQ_PRIORITY
+#define NRFX_NFCT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_NFCT_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_NFCT_CONFIG_LOG_ENABLED
+#define NRFX_NFCT_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_NFCT_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_NFCT_CONFIG_LOG_LEVEL
+#define NRFX_NFCT_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_NFCT_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_NFCT_CONFIG_INFO_COLOR
+#define NRFX_NFCT_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_NFCT_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_NFCT_CONFIG_DEBUG_COLOR
+#define NRFX_NFCT_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_PDM_ENABLED - nrfx_pdm - PDM peripheral driver
+//==========================================================
+#ifndef NRFX_PDM_ENABLED
+#define NRFX_PDM_ENABLED 0
+#endif
+//  NRFX_PDM_CONFIG_MODE  - Mode
+
+// <0=> Stereo
+// <1=> Mono
+
+#ifndef NRFX_PDM_CONFIG_MODE
+#define NRFX_PDM_CONFIG_MODE 1
+#endif
+
+//  NRFX_PDM_CONFIG_EDGE  - Edge
+
+// <0=> Left falling
+// <1=> Left rising
+
+#ifndef NRFX_PDM_CONFIG_EDGE
+#define NRFX_PDM_CONFIG_EDGE 0
+#endif
+
+//  NRFX_PDM_CONFIG_CLOCK_FREQ  - Clock frequency
+
+// <134217728=> 1000k
+// <138412032=> 1032k (default)
+// <142606336=> 1067k
+
+#ifndef NRFX_PDM_CONFIG_CLOCK_FREQ
+#define NRFX_PDM_CONFIG_CLOCK_FREQ 138412032
+#endif
+
+//  NRFX_PDM_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_PDM_CONFIG_IRQ_PRIORITY
+#define NRFX_PDM_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_PDM_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_PDM_CONFIG_LOG_ENABLED
+#define NRFX_PDM_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_PDM_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_PDM_CONFIG_LOG_LEVEL
+#define NRFX_PDM_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_PDM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_PDM_CONFIG_INFO_COLOR
+#define NRFX_PDM_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_PDM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_PDM_CONFIG_DEBUG_COLOR
+#define NRFX_PDM_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_POWER_ENABLED - nrfx_power - POWER peripheral driver
+//==========================================================
+#ifndef NRFX_POWER_ENABLED
+#define NRFX_POWER_ENABLED 0
+#endif
+//  NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#endif
+
+//  NRFX_POWER_CONFIG_DEFAULT_DCDCEN  - The default configuration of main DCDC regulator
+
+
+//  This settings means only that components for DCDC regulator are installed and it can be enabled.
+
+#ifndef NRFX_POWER_CONFIG_DEFAULT_DCDCEN
+#define NRFX_POWER_CONFIG_DEFAULT_DCDCEN 0
+#endif
+
+//  NRFX_POWER_CONFIG_DEFAULT_DCDCENHV  - The default configuration of High Voltage DCDC regulator
+
+
+//  This settings means only that components for DCDC regulator are installed and it can be enabled.
+
+#ifndef NRFX_POWER_CONFIG_DEFAULT_DCDCENHV
+#define NRFX_POWER_CONFIG_DEFAULT_DCDCENHV 0
+#endif
+
+// 
+
+//  NRFX_PPI_ENABLED - nrfx_ppi - PPI peripheral allocator
+//==========================================================
+#ifndef NRFX_PPI_ENABLED
+#define NRFX_PPI_ENABLED 0
+#endif
+//  NRFX_PPI_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_PPI_CONFIG_LOG_ENABLED
+#define NRFX_PPI_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_PPI_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_PPI_CONFIG_LOG_LEVEL
+#define NRFX_PPI_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_PPI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_PPI_CONFIG_INFO_COLOR
+#define NRFX_PPI_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_PPI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_PPI_CONFIG_DEBUG_COLOR
+#define NRFX_PPI_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_PWM_ENABLED - nrfx_pwm - PWM peripheral driver
+//==========================================================
+#ifndef NRFX_PWM_ENABLED
+#define NRFX_PWM_ENABLED 0
+#endif
+//  NRFX_PWM0_ENABLED  - Enable PWM0 instance
+
+
+#ifndef NRFX_PWM0_ENABLED
+#define NRFX_PWM0_ENABLED 0
+#endif
+
+//  NRFX_PWM1_ENABLED  - Enable PWM1 instance
+
+
+#ifndef NRFX_PWM1_ENABLED
+#define NRFX_PWM1_ENABLED 0
+#endif
+
+//  NRFX_PWM2_ENABLED  - Enable PWM2 instance
+
+
+#ifndef NRFX_PWM2_ENABLED
+#define NRFX_PWM2_ENABLED 0
+#endif
+
+//  NRFX_PWM3_ENABLED  - Enable PWM3 instance
+
+
+#ifndef NRFX_PWM3_ENABLED
+#define NRFX_PWM3_ENABLED 0
+#endif
+
+//  NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin  <0-31>
+
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN
+#define NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN 31
+#endif
+
+//  NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin  <0-31>
+
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN
+#define NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN 31
+#endif
+
+//  NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin  <0-31>
+
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN
+#define NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN 31
+#endif
+
+//  NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin  <0-31>
+
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN
+#define NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN 31
+#endif
+
+//  NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK  - Base clock
+
+// <0=> 16 MHz
+// <1=> 8 MHz
+// <2=> 4 MHz
+// <3=> 2 MHz
+// <4=> 1 MHz
+// <5=> 500 kHz
+// <6=> 250 kHz
+// <7=> 125 kHz
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK
+#define NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK 4
+#endif
+
+//  NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE  - Count mode
+
+// <0=> Up
+// <1=> Up and Down
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE
+#define NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE 0
+#endif
+
+//  NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE - Top value
+#ifndef NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE
+#define NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE 1000
+#endif
+
+//  NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE  - Load mode
+
+// <0=> Common
+// <1=> Grouped
+// <2=> Individual
+// <3=> Waveform
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE
+#define NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE 0
+#endif
+
+//  NRFX_PWM_DEFAULT_CONFIG_STEP_MODE  - Step mode
+
+// <0=> Auto
+// <1=> Triggered
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_STEP_MODE
+#define NRFX_PWM_DEFAULT_CONFIG_STEP_MODE 0
+#endif
+
+//  NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_PWM_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_PWM_CONFIG_LOG_ENABLED
+#define NRFX_PWM_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_PWM_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_PWM_CONFIG_LOG_LEVEL
+#define NRFX_PWM_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_PWM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_PWM_CONFIG_INFO_COLOR
+#define NRFX_PWM_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_PWM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_PWM_CONFIG_DEBUG_COLOR
+#define NRFX_PWM_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_QDEC_ENABLED - nrfx_qdec - QDEC peripheral driver
+//==========================================================
+#ifndef NRFX_QDEC_ENABLED
+#define NRFX_QDEC_ENABLED 0
+#endif
+//  NRFX_QDEC_CONFIG_REPORTPER  - Report period
+
+// <0=> 10 Samples
+// <1=> 40 Samples
+// <2=> 80 Samples
+// <3=> 120 Samples
+// <4=> 160 Samples
+// <5=> 200 Samples
+// <6=> 240 Samples
+// <7=> 280 Samples
+
+#ifndef NRFX_QDEC_CONFIG_REPORTPER
+#define NRFX_QDEC_CONFIG_REPORTPER 0
+#endif
+
+//  NRFX_QDEC_CONFIG_SAMPLEPER  - Sample period
+
+// <0=> 128 us
+// <1=> 256 us
+// <2=> 512 us
+// <3=> 1024 us
+// <4=> 2048 us
+// <5=> 4096 us
+// <6=> 8192 us
+// <7=> 16384 us
+
+#ifndef NRFX_QDEC_CONFIG_SAMPLEPER
+#define NRFX_QDEC_CONFIG_SAMPLEPER 7
+#endif
+
+//  NRFX_QDEC_CONFIG_PIO_A - A pin  <0-31>
+
+
+#ifndef NRFX_QDEC_CONFIG_PIO_A
+#define NRFX_QDEC_CONFIG_PIO_A 31
+#endif
+
+//  NRFX_QDEC_CONFIG_PIO_B - B pin  <0-31>
+
+
+#ifndef NRFX_QDEC_CONFIG_PIO_B
+#define NRFX_QDEC_CONFIG_PIO_B 31
+#endif
+
+//  NRFX_QDEC_CONFIG_PIO_LED - LED pin  <0-31>
+
+
+#ifndef NRFX_QDEC_CONFIG_PIO_LED
+#define NRFX_QDEC_CONFIG_PIO_LED 31
+#endif
+
+//  NRFX_QDEC_CONFIG_LEDPRE - LED pre
+#ifndef NRFX_QDEC_CONFIG_LEDPRE
+#define NRFX_QDEC_CONFIG_LEDPRE 511
+#endif
+
+//  NRFX_QDEC_CONFIG_LEDPOL  - LED polarity
+
+// <0=> Active low
+// <1=> Active high
+
+#ifndef NRFX_QDEC_CONFIG_LEDPOL
+#define NRFX_QDEC_CONFIG_LEDPOL 1
+#endif
+
+//  NRFX_QDEC_CONFIG_DBFEN  - Debouncing enable
+
+
+#ifndef NRFX_QDEC_CONFIG_DBFEN
+#define NRFX_QDEC_CONFIG_DBFEN 0
+#endif
+
+//  NRFX_QDEC_CONFIG_SAMPLE_INTEN  - Sample ready interrupt enable
+
+
+#ifndef NRFX_QDEC_CONFIG_SAMPLE_INTEN
+#define NRFX_QDEC_CONFIG_SAMPLE_INTEN 0
+#endif
+
+//  NRFX_QDEC_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_QDEC_CONFIG_IRQ_PRIORITY
+#define NRFX_QDEC_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_QDEC_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED
+#define NRFX_QDEC_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_QDEC_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL
+#define NRFX_QDEC_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_QDEC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_QDEC_CONFIG_INFO_COLOR
+#define NRFX_QDEC_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_QDEC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_QDEC_CONFIG_DEBUG_COLOR
+#define NRFX_QDEC_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_QSPI_ENABLED - nrfx_qspi - QSPI peripheral driver
+//==========================================================
+#ifndef NRFX_QSPI_ENABLED
+#define NRFX_QSPI_ENABLED 0
+#endif
+//  NRFX_QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns).  <0-255>
+
+
+#ifndef NRFX_QSPI_CONFIG_SCK_DELAY
+#define NRFX_QSPI_CONFIG_SCK_DELAY 1
+#endif
+
+//  NRFX_QSPI_CONFIG_XIP_OFFSET - Address offset in the external memory for Execute in Place operation.
+#ifndef NRFX_QSPI_CONFIG_XIP_OFFSET
+#define NRFX_QSPI_CONFIG_XIP_OFFSET 0
+#endif
+
+//  NRFX_QSPI_CONFIG_READOC  - Number of data lines and opcode used for reading.
+
+// <0=> FastRead
+// <1=> Read2O
+// <2=> Read2IO
+// <3=> Read4O
+// <4=> Read4IO
+
+#ifndef NRFX_QSPI_CONFIG_READOC
+#define NRFX_QSPI_CONFIG_READOC 0
+#endif
+
+//  NRFX_QSPI_CONFIG_WRITEOC  - Number of data lines and opcode used for writing.
+
+// <0=> PP
+// <1=> PP2O
+// <2=> PP4O
+// <3=> PP4IO
+
+#ifndef NRFX_QSPI_CONFIG_WRITEOC
+#define NRFX_QSPI_CONFIG_WRITEOC 0
+#endif
+
+//  NRFX_QSPI_CONFIG_ADDRMODE  - Addressing mode.
+
+// <0=> 24bit
+// <1=> 32bit
+
+#ifndef NRFX_QSPI_CONFIG_ADDRMODE
+#define NRFX_QSPI_CONFIG_ADDRMODE 0
+#endif
+
+//  NRFX_QSPI_CONFIG_MODE  - SPI mode.
+
+// <0=> Mode 0
+// <1=> Mode 1
+
+#ifndef NRFX_QSPI_CONFIG_MODE
+#define NRFX_QSPI_CONFIG_MODE 0
+#endif
+
+//  NRFX_QSPI_CONFIG_FREQUENCY  - Frequency divider.
+
+// <0=> 32MHz/1
+// <1=> 32MHz/2
+// <2=> 32MHz/3
+// <3=> 32MHz/4
+// <4=> 32MHz/5
+// <5=> 32MHz/6
+// <6=> 32MHz/7
+// <7=> 32MHz/8
+// <8=> 32MHz/9
+// <9=> 32MHz/10
+// <10=> 32MHz/11
+// <11=> 32MHz/12
+// <12=> 32MHz/13
+// <13=> 32MHz/14
+// <14=> 32MHz/15
+// <15=> 32MHz/16
+
+#ifndef NRFX_QSPI_CONFIG_FREQUENCY
+#define NRFX_QSPI_CONFIG_FREQUENCY 15
+#endif
+
+//  NRFX_QSPI_PIN_SCK - SCK pin value.
+#ifndef NRFX_QSPI_PIN_SCK
+#define NRFX_QSPI_PIN_SCK NRF_QSPI_PIN_NOT_CONNECTED
+#endif
+
+//  NRFX_QSPI_PIN_CSN - CSN pin value.
+#ifndef NRFX_QSPI_PIN_CSN
+#define NRFX_QSPI_PIN_CSN NRF_QSPI_PIN_NOT_CONNECTED
+#endif
+
+//  NRFX_QSPI_PIN_IO0 - IO0 pin value.
+#ifndef NRFX_QSPI_PIN_IO0
+#define NRFX_QSPI_PIN_IO0 NRF_QSPI_PIN_NOT_CONNECTED
+#endif
+
+//  NRFX_QSPI_PIN_IO1 - IO1 pin value.
+#ifndef NRFX_QSPI_PIN_IO1
+#define NRFX_QSPI_PIN_IO1 NRF_QSPI_PIN_NOT_CONNECTED
+#endif
+
+//  NRFX_QSPI_PIN_IO2 - IO2 pin value.
+#ifndef NRFX_QSPI_PIN_IO2
+#define NRFX_QSPI_PIN_IO2 NRF_QSPI_PIN_NOT_CONNECTED
+#endif
+
+//  NRFX_QSPI_PIN_IO3 - IO3 pin value.
+#ifndef NRFX_QSPI_PIN_IO3
+#define NRFX_QSPI_PIN_IO3 NRF_QSPI_PIN_NOT_CONNECTED
+#endif
+
+//  NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+// 
+
+//  NRFX_RNG_ENABLED - nrfx_rng - RNG peripheral driver
+//==========================================================
+#ifndef NRFX_RNG_ENABLED
+#define NRFX_RNG_ENABLED 0
+#endif
+//  NRFX_RNG_CONFIG_ERROR_CORRECTION  - Error correction
+
+
+#ifndef NRFX_RNG_CONFIG_ERROR_CORRECTION
+#define NRFX_RNG_CONFIG_ERROR_CORRECTION 1
+#endif
+
+//  NRFX_RNG_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_RNG_CONFIG_IRQ_PRIORITY
+#define NRFX_RNG_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_RNG_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_RNG_CONFIG_LOG_ENABLED
+#define NRFX_RNG_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_RNG_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_RNG_CONFIG_LOG_LEVEL
+#define NRFX_RNG_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_RNG_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_RNG_CONFIG_INFO_COLOR
+#define NRFX_RNG_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_RNG_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_RNG_CONFIG_DEBUG_COLOR
+#define NRFX_RNG_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_RTC_ENABLED - nrfx_rtc - RTC peripheral driver
+//==========================================================
+#ifndef NRFX_RTC_ENABLED
+#define NRFX_RTC_ENABLED 0
+#endif
+//  NRFX_RTC0_ENABLED  - Enable RTC0 instance
+
+
+#ifndef NRFX_RTC0_ENABLED
+#define NRFX_RTC0_ENABLED 0
+#endif
+
+//  NRFX_RTC1_ENABLED  - Enable RTC1 instance
+
+
+#ifndef NRFX_RTC1_ENABLED
+#define NRFX_RTC1_ENABLED 0
+#endif
+
+//  NRFX_RTC2_ENABLED  - Enable RTC2 instance
+
+
+#ifndef NRFX_RTC2_ENABLED
+#define NRFX_RTC2_ENABLED 0
+#endif
+
+//  NRFX_RTC_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt
+#ifndef NRFX_RTC_MAXIMUM_LATENCY_US
+#define NRFX_RTC_MAXIMUM_LATENCY_US 2000
+#endif
+
+//  NRFX_RTC_DEFAULT_CONFIG_FREQUENCY - Frequency  <16-32768>
+
+
+#ifndef NRFX_RTC_DEFAULT_CONFIG_FREQUENCY
+#define NRFX_RTC_DEFAULT_CONFIG_FREQUENCY 32768
+#endif
+
+//  NRFX_RTC_DEFAULT_CONFIG_RELIABLE  - Ensures safe compare event triggering
+
+
+#ifndef NRFX_RTC_DEFAULT_CONFIG_RELIABLE
+#define NRFX_RTC_DEFAULT_CONFIG_RELIABLE 0
+#endif
+
+//  NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_RTC_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_RTC_CONFIG_LOG_ENABLED
+#define NRFX_RTC_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_RTC_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_RTC_CONFIG_LOG_LEVEL
+#define NRFX_RTC_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_RTC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_RTC_CONFIG_INFO_COLOR
+#define NRFX_RTC_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_RTC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_RTC_CONFIG_DEBUG_COLOR
+#define NRFX_RTC_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_SAADC_ENABLED - nrfx_saadc - SAADC peripheral driver
+//==========================================================
+#ifndef NRFX_SAADC_ENABLED
+#define NRFX_SAADC_ENABLED 0
+#endif
+//  NRFX_SAADC_CONFIG_RESOLUTION  - Resolution
+
+// <0=> 8 bit
+// <1=> 10 bit
+// <2=> 12 bit
+// <3=> 14 bit
+
+#ifndef NRFX_SAADC_CONFIG_RESOLUTION
+#define NRFX_SAADC_CONFIG_RESOLUTION 1
+#endif
+
+//  NRFX_SAADC_CONFIG_OVERSAMPLE  - Sample period
+
+// <0=> Disabled
+// <1=> 2x
+// <2=> 4x
+// <3=> 8x
+// <4=> 16x
+// <5=> 32x
+// <6=> 64x
+// <7=> 128x
+// <8=> 256x
+
+#ifndef NRFX_SAADC_CONFIG_OVERSAMPLE
+#define NRFX_SAADC_CONFIG_OVERSAMPLE 0
+#endif
+
+//  NRFX_SAADC_CONFIG_LP_MODE  - Enabling low power mode
+
+
+#ifndef NRFX_SAADC_CONFIG_LP_MODE
+#define NRFX_SAADC_CONFIG_LP_MODE 0
+#endif
+
+//  NRFX_SAADC_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_SAADC_CONFIG_IRQ_PRIORITY
+#define NRFX_SAADC_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_SAADC_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED
+#define NRFX_SAADC_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_SAADC_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL
+#define NRFX_SAADC_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_SAADC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_SAADC_CONFIG_INFO_COLOR
+#define NRFX_SAADC_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_SAADC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_SAADC_CONFIG_DEBUG_COLOR
+#define NRFX_SAADC_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_SPIM_ENABLED - nrfx_spim - SPIM peripheral driver
+//==========================================================
+#ifndef NRFX_SPIM_ENABLED
+#define NRFX_SPIM_ENABLED 0
+#endif
+//  NRFX_SPIM0_ENABLED  - Enable SPIM0 instance
+
+
+#ifndef NRFX_SPIM0_ENABLED
+#define NRFX_SPIM0_ENABLED 0
+#endif
+
+//  NRFX_SPIM1_ENABLED  - Enable SPIM1 instance
+
+
+#ifndef NRFX_SPIM1_ENABLED
+#define NRFX_SPIM1_ENABLED 0
+#endif
+
+//  NRFX_SPIM2_ENABLED  - Enable SPIM2 instance
+
+
+#ifndef NRFX_SPIM2_ENABLED
+#define NRFX_SPIM2_ENABLED 0
+#endif
+
+//  NRFX_SPIM3_ENABLED  - Enable SPIM3 instance
+
+
+#ifndef NRFX_SPIM3_ENABLED
+#define NRFX_SPIM3_ENABLED 0
+#endif
+
+//  NRFX_SPIM_EXTENDED_ENABLED  - Enable extended SPIM features
+
+
+#ifndef NRFX_SPIM_EXTENDED_ENABLED
+#define NRFX_SPIM_EXTENDED_ENABLED 0
+#endif
+
+//  NRFX_SPIM_MISO_PULL_CFG  - MISO pin pull configuration.
+
+// <0=> NRF_GPIO_PIN_NOPULL
+// <1=> NRF_GPIO_PIN_PULLDOWN
+// <3=> NRF_GPIO_PIN_PULLUP
+
+#ifndef NRFX_SPIM_MISO_PULL_CFG
+#define NRFX_SPIM_MISO_PULL_CFG 1
+#endif
+
+//  NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_SPIM_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED
+#define NRFX_SPIM_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_SPIM_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL
+#define NRFX_SPIM_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_SPIM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_SPIM_CONFIG_INFO_COLOR
+#define NRFX_SPIM_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_SPIM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_SPIM_CONFIG_DEBUG_COLOR
+#define NRFX_SPIM_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_SPIS_ENABLED - nrfx_spis - SPIS peripheral driver
+//==========================================================
+#ifndef NRFX_SPIS_ENABLED
+#define NRFX_SPIS_ENABLED 0
+#endif
+//  NRFX_SPIS0_ENABLED  - Enable SPIS0 instance
+
+
+#ifndef NRFX_SPIS0_ENABLED
+#define NRFX_SPIS0_ENABLED 0
+#endif
+
+//  NRFX_SPIS1_ENABLED  - Enable SPIS1 instance
+
+
+#ifndef NRFX_SPIS1_ENABLED
+#define NRFX_SPIS1_ENABLED 0
+#endif
+
+//  NRFX_SPIS2_ENABLED  - Enable SPIS2 instance
+
+
+#ifndef NRFX_SPIS2_ENABLED
+#define NRFX_SPIS2_ENABLED 0
+#endif
+
+//  NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_SPIS_DEFAULT_DEF - SPIS default DEF character  <0-255>
+
+
+#ifndef NRFX_SPIS_DEFAULT_DEF
+#define NRFX_SPIS_DEFAULT_DEF 255
+#endif
+
+//  NRFX_SPIS_DEFAULT_ORC - SPIS default ORC character  <0-255>
+
+
+#ifndef NRFX_SPIS_DEFAULT_ORC
+#define NRFX_SPIS_DEFAULT_ORC 255
+#endif
+
+//  NRFX_SPIS_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED
+#define NRFX_SPIS_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_SPIS_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL
+#define NRFX_SPIS_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_SPIS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_SPIS_CONFIG_INFO_COLOR
+#define NRFX_SPIS_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_SPIS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_SPIS_CONFIG_DEBUG_COLOR
+#define NRFX_SPIS_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_SPI_ENABLED - nrfx_spi - SPI peripheral driver
+//==========================================================
+#ifndef NRFX_SPI_ENABLED
+#define NRFX_SPI_ENABLED 0
+#endif
+//  NRFX_SPI0_ENABLED  - Enable SPI0 instance
+
+
+#ifndef NRFX_SPI0_ENABLED
+#define NRFX_SPI0_ENABLED 0
+#endif
+
+//  NRFX_SPI1_ENABLED  - Enable SPI1 instance
+
+
+#ifndef NRFX_SPI1_ENABLED
+#define NRFX_SPI1_ENABLED 0
+#endif
+
+//  NRFX_SPI2_ENABLED  - Enable SPI2 instance
+
+
+#ifndef NRFX_SPI2_ENABLED
+#define NRFX_SPI2_ENABLED 0
+#endif
+
+//  NRFX_SPI_MISO_PULL_CFG  - MISO pin pull configuration.
+
+// <0=> NRF_GPIO_PIN_NOPULL
+// <1=> NRF_GPIO_PIN_PULLDOWN
+// <3=> NRF_GPIO_PIN_PULLUP
+
+#ifndef NRFX_SPI_MISO_PULL_CFG
+#define NRFX_SPI_MISO_PULL_CFG 1
+#endif
+
+//  NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_SPI_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_SPI_CONFIG_LOG_ENABLED
+#define NRFX_SPI_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_SPI_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_SPI_CONFIG_LOG_LEVEL
+#define NRFX_SPI_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_SPI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_SPI_CONFIG_INFO_COLOR
+#define NRFX_SPI_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_SPI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_SPI_CONFIG_DEBUG_COLOR
+#define NRFX_SPI_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_SWI_ENABLED - nrfx_swi - SWI/EGU peripheral allocator
+//==========================================================
+#ifndef NRFX_SWI_ENABLED
+#define NRFX_SWI_ENABLED 0
+#endif
+//  NRFX_EGU_ENABLED  - Enable EGU support
+
+
+#ifndef NRFX_EGU_ENABLED
+#define NRFX_EGU_ENABLED 0
+#endif
+
+//  NRFX_SWI0_DISABLED  - Exclude SWI0 from being utilized by the driver
+
+
+#ifndef NRFX_SWI0_DISABLED
+#define NRFX_SWI0_DISABLED 0
+#endif
+
+//  NRFX_SWI1_DISABLED  - Exclude SWI1 from being utilized by the driver
+
+
+#ifndef NRFX_SWI1_DISABLED
+#define NRFX_SWI1_DISABLED 0
+#endif
+
+//  NRFX_SWI2_DISABLED  - Exclude SWI2 from being utilized by the driver
+
+
+#ifndef NRFX_SWI2_DISABLED
+#define NRFX_SWI2_DISABLED 0
+#endif
+
+//  NRFX_SWI3_DISABLED  - Exclude SWI3 from being utilized by the driver
+
+
+#ifndef NRFX_SWI3_DISABLED
+#define NRFX_SWI3_DISABLED 0
+#endif
+
+//  NRFX_SWI4_DISABLED  - Exclude SWI4 from being utilized by the driver
+
+
+#ifndef NRFX_SWI4_DISABLED
+#define NRFX_SWI4_DISABLED 0
+#endif
+
+//  NRFX_SWI5_DISABLED  - Exclude SWI5 from being utilized by the driver
+
+
+#ifndef NRFX_SWI5_DISABLED
+#define NRFX_SWI5_DISABLED 0
+#endif
+
+//  NRFX_SWI_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_SWI_CONFIG_LOG_ENABLED
+#define NRFX_SWI_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_SWI_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_SWI_CONFIG_LOG_LEVEL
+#define NRFX_SWI_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_SWI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_SWI_CONFIG_INFO_COLOR
+#define NRFX_SWI_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_SWI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_SWI_CONFIG_DEBUG_COLOR
+#define NRFX_SWI_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_TIMER_ENABLED - nrfx_timer - TIMER periperal driver
+//==========================================================
+#ifndef NRFX_TIMER_ENABLED
+#define NRFX_TIMER_ENABLED 0
+#endif
+//  NRFX_TIMER0_ENABLED  - Enable TIMER0 instance
+
+
+#ifndef NRFX_TIMER0_ENABLED
+#define NRFX_TIMER0_ENABLED 0
+#endif
+
+//  NRFX_TIMER1_ENABLED  - Enable TIMER1 instance
+
+
+#ifndef NRFX_TIMER1_ENABLED
+#define NRFX_TIMER1_ENABLED 0
+#endif
+
+//  NRFX_TIMER2_ENABLED  - Enable TIMER2 instance
+
+
+#ifndef NRFX_TIMER2_ENABLED
+#define NRFX_TIMER2_ENABLED 0
+#endif
+
+//  NRFX_TIMER3_ENABLED  - Enable TIMER3 instance
+
+
+#ifndef NRFX_TIMER3_ENABLED
+#define NRFX_TIMER3_ENABLED 0
+#endif
+
+//  NRFX_TIMER4_ENABLED  - Enable TIMER4 instance
+
+
+#ifndef NRFX_TIMER4_ENABLED
+#define NRFX_TIMER4_ENABLED 0
+#endif
+
+//  NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY  - Timer frequency if in Timer mode
+
+// <0=> 16 MHz
+// <1=> 8 MHz
+// <2=> 4 MHz
+// <3=> 2 MHz
+// <4=> 1 MHz
+// <5=> 500 kHz
+// <6=> 250 kHz
+// <7=> 125 kHz
+// <8=> 62.5 kHz
+// <9=> 31.25 kHz
+
+#ifndef NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY
+#define NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY 0
+#endif
+
+//  NRFX_TIMER_DEFAULT_CONFIG_MODE  - Timer mode or operation
+
+// <0=> Timer
+// <1=> Counter
+
+#ifndef NRFX_TIMER_DEFAULT_CONFIG_MODE
+#define NRFX_TIMER_DEFAULT_CONFIG_MODE 0
+#endif
+
+//  NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH  - Timer counter bit width
+
+// <0=> 16 bit
+// <1=> 8 bit
+// <2=> 24 bit
+// <3=> 32 bit
+
+#ifndef NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH
+#define NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH 0
+#endif
+
+//  NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_TIMER_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED
+#define NRFX_TIMER_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_TIMER_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL
+#define NRFX_TIMER_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_TIMER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_TIMER_CONFIG_INFO_COLOR
+#define NRFX_TIMER_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_TIMER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_TIMER_CONFIG_DEBUG_COLOR
+#define NRFX_TIMER_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_TWIM_ENABLED - nrfx_twim - TWIM peripheral driver
+//==========================================================
+#ifndef NRFX_TWIM_ENABLED
+#define NRFX_TWIM_ENABLED 0
+#endif
+//  NRFX_TWIM0_ENABLED  - Enable TWIM0 instance
+
+
+#ifndef NRFX_TWIM0_ENABLED
+#define NRFX_TWIM0_ENABLED 0
+#endif
+
+//  NRFX_TWIM1_ENABLED  - Enable TWIM1 instance
+
+
+#ifndef NRFX_TWIM1_ENABLED
+#define NRFX_TWIM1_ENABLED 0
+#endif
+
+//  NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY  - Frequency
+
+// <26738688=> 100k
+// <67108864=> 250k
+// <104857600=> 400k
+
+#ifndef NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY
+#define NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY 26738688
+#endif
+
+//  NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT  - Enables bus holding after uninit
+
+
+#ifndef NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT
+#define NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0
+#endif
+
+//  NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_TWIM_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED
+#define NRFX_TWIM_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_TWIM_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL
+#define NRFX_TWIM_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_TWIM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_TWIM_CONFIG_INFO_COLOR
+#define NRFX_TWIM_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_TWIM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_TWIM_CONFIG_DEBUG_COLOR
+#define NRFX_TWIM_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_TWIS_ENABLED - nrfx_twis - TWIS peripheral driver
+//==========================================================
+#ifndef NRFX_TWIS_ENABLED
+#define NRFX_TWIS_ENABLED 0
+#endif
+//  NRFX_TWIS0_ENABLED  - Enable TWIS0 instance
+
+
+#ifndef NRFX_TWIS0_ENABLED
+#define NRFX_TWIS0_ENABLED 0
+#endif
+
+//  NRFX_TWIS1_ENABLED  - Enable TWIS1 instance
+
+
+#ifndef NRFX_TWIS1_ENABLED
+#define NRFX_TWIS1_ENABLED 0
+#endif
+
+//  NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY  - Assume that any instance would be initialized only once
+
+
+//  Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code.
+
+#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY
+#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
+#endif
+
+//  NRFX_TWIS_NO_SYNC_MODE  - Remove support for synchronous mode
+
+
+//  Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources.
+
+#ifndef NRFX_TWIS_NO_SYNC_MODE
+#define NRFX_TWIS_NO_SYNC_MODE 0
+#endif
+
+//  NRFX_TWIS_DEFAULT_CONFIG_ADDR0 - Address0
+#ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR0
+#define NRFX_TWIS_DEFAULT_CONFIG_ADDR0 0
+#endif
+
+//  NRFX_TWIS_DEFAULT_CONFIG_ADDR1 - Address1
+#ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR1
+#define NRFX_TWIS_DEFAULT_CONFIG_ADDR1 0
+#endif
+
+//  NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL  - SCL pin pull configuration
+
+// <0=> Disabled
+// <1=> Pull down
+// <3=> Pull up
+
+#ifndef NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL
+#define NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL 0
+#endif
+
+//  NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL  - SDA pin pull configuration
+
+// <0=> Disabled
+// <1=> Pull down
+// <3=> Pull up
+
+#ifndef NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL
+#define NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL 0
+#endif
+
+//  NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_TWIS_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED
+#define NRFX_TWIS_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_TWIS_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL
+#define NRFX_TWIS_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_TWIS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_TWIS_CONFIG_INFO_COLOR
+#define NRFX_TWIS_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_TWIS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_TWIS_CONFIG_DEBUG_COLOR
+#define NRFX_TWIS_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_TWI_ENABLED - nrfx_twi - TWI peripheral driver
+//==========================================================
+#ifndef NRFX_TWI_ENABLED
+#define NRFX_TWI_ENABLED 0
+#endif
+//  NRFX_TWI0_ENABLED  - Enable TWI0 instance
+
+
+#ifndef NRFX_TWI0_ENABLED
+#define NRFX_TWI0_ENABLED 0
+#endif
+
+//  NRFX_TWI1_ENABLED  - Enable TWI1 instance
+
+
+#ifndef NRFX_TWI1_ENABLED
+#define NRFX_TWI1_ENABLED 0
+#endif
+
+//  NRFX_TWI_DEFAULT_CONFIG_FREQUENCY  - Frequency
+
+// <26738688=> 100k
+// <67108864=> 250k
+// <104857600=> 400k
+
+#ifndef NRFX_TWI_DEFAULT_CONFIG_FREQUENCY
+#define NRFX_TWI_DEFAULT_CONFIG_FREQUENCY 26738688
+#endif
+
+//  NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT  - Enables bus holding after uninit
+
+
+#ifndef NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT
+#define NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0
+#endif
+
+//  NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_TWI_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_TWI_CONFIG_LOG_ENABLED
+#define NRFX_TWI_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_TWI_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_TWI_CONFIG_LOG_LEVEL
+#define NRFX_TWI_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_TWI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_TWI_CONFIG_INFO_COLOR
+#define NRFX_TWI_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_TWI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_TWI_CONFIG_DEBUG_COLOR
+#define NRFX_TWI_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_UARTE_ENABLED - nrfx_uarte - UARTE peripheral driver
+//==========================================================
+#ifndef NRFX_UARTE_ENABLED
+#define NRFX_UARTE_ENABLED 0
+#endif
+//  NRFX_UARTE0_ENABLED - Enable UARTE0 instance
+#ifndef NRFX_UARTE0_ENABLED
+#define NRFX_UARTE0_ENABLED 0
+#endif
+
+//  NRFX_UARTE1_ENABLED - Enable UARTE1 instance
+#ifndef NRFX_UARTE1_ENABLED
+#define NRFX_UARTE1_ENABLED 0
+#endif
+
+//  NRFX_UARTE_DEFAULT_CONFIG_HWFC  - Hardware Flow Control
+
+// <0=> Disabled
+// <1=> Enabled
+
+#ifndef NRFX_UARTE_DEFAULT_CONFIG_HWFC
+#define NRFX_UARTE_DEFAULT_CONFIG_HWFC 0
+#endif
+
+//  NRFX_UARTE_DEFAULT_CONFIG_PARITY  - Parity
+
+// <0=> Excluded
+// <14=> Included
+
+#ifndef NRFX_UARTE_DEFAULT_CONFIG_PARITY
+#define NRFX_UARTE_DEFAULT_CONFIG_PARITY 0
+#endif
+
+//  NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE  - Default Baudrate
+
+// <323584=> 1200 baud
+// <643072=> 2400 baud
+// <1290240=> 4800 baud
+// <2576384=> 9600 baud
+// <3862528=> 14400 baud
+// <5152768=> 19200 baud
+// <7716864=> 28800 baud
+// <8388608=> 31250 baud
+// <10289152=> 38400 baud
+// <15007744=> 56000 baud
+// <15400960=> 57600 baud
+// <20615168=> 76800 baud
+// <30801920=> 115200 baud
+// <61865984=> 230400 baud
+// <67108864=> 250000 baud
+// <121634816=> 460800 baud
+// <251658240=> 921600 baud
+// <268435456=> 1000000 baud
+
+#ifndef NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE
+#define NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE 30801920
+#endif
+
+//  NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_UARTE_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED
+#define NRFX_UARTE_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_UARTE_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL
+#define NRFX_UARTE_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_UARTE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_UARTE_CONFIG_INFO_COLOR
+#define NRFX_UARTE_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_UARTE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_UARTE_CONFIG_DEBUG_COLOR
+#define NRFX_UARTE_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_UART_ENABLED - nrfx_uart - UART peripheral driver
+//==========================================================
+#ifndef NRFX_UART_ENABLED
+#define NRFX_UART_ENABLED 0
+#endif
+//  NRFX_UART0_ENABLED - Enable UART0 instance
+#ifndef NRFX_UART0_ENABLED
+#define NRFX_UART0_ENABLED 0
+#endif
+
+//  NRFX_UART_DEFAULT_CONFIG_HWFC  - Hardware Flow Control
+
+// <0=> Disabled
+// <1=> Enabled
+
+#ifndef NRFX_UART_DEFAULT_CONFIG_HWFC
+#define NRFX_UART_DEFAULT_CONFIG_HWFC 0
+#endif
+
+//  NRFX_UART_DEFAULT_CONFIG_PARITY  - Parity
+
+// <0=> Excluded
+// <14=> Included
+
+#ifndef NRFX_UART_DEFAULT_CONFIG_PARITY
+#define NRFX_UART_DEFAULT_CONFIG_PARITY 0
+#endif
+
+//  NRFX_UART_DEFAULT_CONFIG_BAUDRATE  - Default Baudrate
+
+// <323584=> 1200 baud
+// <643072=> 2400 baud
+// <1290240=> 4800 baud
+// <2576384=> 9600 baud
+// <3866624=> 14400 baud
+// <5152768=> 19200 baud
+// <7729152=> 28800 baud
+// <8388608=> 31250 baud
+// <10309632=> 38400 baud
+// <15007744=> 56000 baud
+// <15462400=> 57600 baud
+// <20615168=> 76800 baud
+// <30924800=> 115200 baud
+// <61845504=> 230400 baud
+// <67108864=> 250000 baud
+// <123695104=> 460800 baud
+// <247386112=> 921600 baud
+// <268435456=> 1000000 baud
+
+#ifndef NRFX_UART_DEFAULT_CONFIG_BAUDRATE
+#define NRFX_UART_DEFAULT_CONFIG_BAUDRATE 30924800
+#endif
+
+//  NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY
+#define NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY 4
+#endif
+
+//  NRFX_UART_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_UART_CONFIG_LOG_ENABLED
+#define NRFX_UART_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_UART_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_UART_CONFIG_LOG_LEVEL
+#define NRFX_UART_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_UART_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_UART_CONFIG_INFO_COLOR
+#define NRFX_UART_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_UART_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_UART_CONFIG_DEBUG_COLOR
+#define NRFX_UART_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRFX_USBD_ENABLED - nrfx_usbd - USBD peripheral driver
+//==========================================================
+#ifndef NRFX_USBD_ENABLED
+#define NRFX_USBD_ENABLED 0
+#endif
+//  NRFX_USBD_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_USBD_CONFIG_IRQ_PRIORITY
+#define NRFX_USBD_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_USBD_CONFIG_DMASCHEDULER_MODE  - USBD DMA scheduler working scheme
+
+// <0=> Prioritized access
+// <1=> Round Robin
+
+#ifndef NRFX_USBD_CONFIG_DMASCHEDULER_MODE
+#define NRFX_USBD_CONFIG_DMASCHEDULER_MODE 0
+#endif
+
+//  NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST  - Give priority to isochronous transfers
+
+
+//  This option gives priority to isochronous transfers.
+//  Enabling it assures that isochronous transfers are always processed,
+//  even if multiple other transfers are pending.
+//  Isochronous endpoints are prioritized before the usbd_dma_scheduler_algorithm
+//  function is called, so the option is independent of the algorithm chosen.
+
+#ifndef NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST
+#define NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST 1
+#endif
+
+//  NRFX_USBD_CONFIG_ISO_IN_ZLP  - Respond to an IN token on ISO IN endpoint with ZLP when no data is ready
+
+
+//  If set, ISO IN endpoint will respond to an IN token with ZLP when no data is ready to be sent.
+//  Else, there will be no response.
+
+#ifndef NRFX_USBD_CONFIG_ISO_IN_ZLP
+#define NRFX_USBD_CONFIG_ISO_IN_ZLP 0
+#endif
+
+// 
+
+//  NRFX_WDT_ENABLED - nrfx_wdt - WDT peripheral driver
+//==========================================================
+#ifndef NRFX_WDT_ENABLED
+#define NRFX_WDT_ENABLED 0
+#endif
+//  NRFX_WDT_CONFIG_BEHAVIOUR  - WDT behavior in CPU SLEEP or HALT mode
+
+// <1=> Run in SLEEP, Pause in HALT
+// <8=> Pause in SLEEP, Run in HALT
+// <9=> Run in SLEEP and HALT
+// <0=> Pause in SLEEP and HALT
+
+#ifndef NRFX_WDT_CONFIG_BEHAVIOUR
+#define NRFX_WDT_CONFIG_BEHAVIOUR 1
+#endif
+
+//  NRFX_WDT_CONFIG_RELOAD_VALUE - Reload value  <15-4294967295>
+
+
+#ifndef NRFX_WDT_CONFIG_RELOAD_VALUE
+#define NRFX_WDT_CONFIG_RELOAD_VALUE 2000
+#endif
+
+//  NRFX_WDT_CONFIG_NO_IRQ  - Remove WDT IRQ handling from WDT driver
+
+// <0=> Include WDT IRQ handling
+// <1=> Remove WDT IRQ handling
+
+#ifndef NRFX_WDT_CONFIG_NO_IRQ
+#define NRFX_WDT_CONFIG_NO_IRQ 0
+#endif
+
+//  NRFX_WDT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef NRFX_WDT_CONFIG_IRQ_PRIORITY
+#define NRFX_WDT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRFX_WDT_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRFX_WDT_CONFIG_LOG_ENABLED
+#define NRFX_WDT_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_WDT_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_WDT_CONFIG_LOG_LEVEL
+#define NRFX_WDT_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_WDT_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_WDT_CONFIG_INFO_COLOR
+#define NRFX_WDT_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_WDT_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_WDT_CONFIG_DEBUG_COLOR
+#define NRFX_WDT_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NRF_CLOCK_ENABLED - nrf_drv_clock - CLOCK peripheral driver - legacy layer
+//==========================================================
+#ifndef NRF_CLOCK_ENABLED
+#define NRF_CLOCK_ENABLED 0
+#endif
+//  CLOCK_CONFIG_LF_SRC  - LF Clock Source
+
+// <0=> RC
+// <1=> XTAL
+// <2=> Synth
+// <131073=> External Low Swing
+// <196609=> External Full Swing
+
+#ifndef CLOCK_CONFIG_LF_SRC
+#define CLOCK_CONFIG_LF_SRC 1
+#endif
+
+//  CLOCK_CONFIG_LF_CAL_ENABLED  - Calibration enable for LF Clock Source
+
+
+#ifndef CLOCK_CONFIG_LF_CAL_ENABLED
+#define CLOCK_CONFIG_LF_CAL_ENABLED 0
+#endif
+
+//  CLOCK_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef CLOCK_CONFIG_IRQ_PRIORITY
+#define CLOCK_CONFIG_IRQ_PRIORITY 6
+#endif
+
+// 
+
+//  PDM_ENABLED - nrf_drv_pdm - PDM peripheral driver - legacy layer
+//==========================================================
+#ifndef PDM_ENABLED
+#define PDM_ENABLED 0
+#endif
+//  PDM_CONFIG_MODE  - Mode
+
+// <0=> Stereo
+// <1=> Mono
+
+#ifndef PDM_CONFIG_MODE
+#define PDM_CONFIG_MODE 1
+#endif
+
+//  PDM_CONFIG_EDGE  - Edge
+
+// <0=> Left falling
+// <1=> Left rising
+
+#ifndef PDM_CONFIG_EDGE
+#define PDM_CONFIG_EDGE 0
+#endif
+
+//  PDM_CONFIG_CLOCK_FREQ  - Clock frequency
+
+// <134217728=> 1000k
+// <138412032=> 1032k (default)
+// <142606336=> 1067k
+
+#ifndef PDM_CONFIG_CLOCK_FREQ
+#define PDM_CONFIG_CLOCK_FREQ 138412032
+#endif
+
+//  PDM_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef PDM_CONFIG_IRQ_PRIORITY
+#define PDM_CONFIG_IRQ_PRIORITY 6
+#endif
+
+// 
+
+//  POWER_ENABLED - nrf_drv_power - POWER peripheral driver - legacy layer
+//==========================================================
+#ifndef POWER_ENABLED
+#define POWER_ENABLED 0
+#endif
+//  POWER_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef POWER_CONFIG_IRQ_PRIORITY
+#define POWER_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  POWER_CONFIG_DEFAULT_DCDCEN  - The default configuration of main DCDC regulator
+
+
+//  This settings means only that components for DCDC regulator are installed and it can be enabled.
+
+#ifndef POWER_CONFIG_DEFAULT_DCDCEN
+#define POWER_CONFIG_DEFAULT_DCDCEN 0
+#endif
+
+//  POWER_CONFIG_DEFAULT_DCDCENHV  - The default configuration of High Voltage DCDC regulator
+
+
+//  This settings means only that components for DCDC regulator are installed and it can be enabled.
+
+#ifndef POWER_CONFIG_DEFAULT_DCDCENHV
+#define POWER_CONFIG_DEFAULT_DCDCENHV 0
+#endif
+
+// 
+
+//  PPI_ENABLED  - nrf_drv_ppi - PPI peripheral driver - legacy layer
+
+
+#ifndef PPI_ENABLED
+#define PPI_ENABLED 0
+#endif
+
+//  PWM_ENABLED - nrf_drv_pwm - PWM peripheral driver - legacy layer
+//==========================================================
+#ifndef PWM_ENABLED
+#define PWM_ENABLED 0
+#endif
+//  PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin  <0-31>
+
+
+#ifndef PWM_DEFAULT_CONFIG_OUT0_PIN
+#define PWM_DEFAULT_CONFIG_OUT0_PIN 31
+#endif
+
+//  PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin  <0-31>
+
+
+#ifndef PWM_DEFAULT_CONFIG_OUT1_PIN
+#define PWM_DEFAULT_CONFIG_OUT1_PIN 31
+#endif
+
+//  PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin  <0-31>
+
+
+#ifndef PWM_DEFAULT_CONFIG_OUT2_PIN
+#define PWM_DEFAULT_CONFIG_OUT2_PIN 31
+#endif
+
+//  PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin  <0-31>
+
+
+#ifndef PWM_DEFAULT_CONFIG_OUT3_PIN
+#define PWM_DEFAULT_CONFIG_OUT3_PIN 31
+#endif
+
+//  PWM_DEFAULT_CONFIG_BASE_CLOCK  - Base clock
+
+// <0=> 16 MHz
+// <1=> 8 MHz
+// <2=> 4 MHz
+// <3=> 2 MHz
+// <4=> 1 MHz
+// <5=> 500 kHz
+// <6=> 250 kHz
+// <7=> 125 kHz
+
+#ifndef PWM_DEFAULT_CONFIG_BASE_CLOCK
+#define PWM_DEFAULT_CONFIG_BASE_CLOCK 4
+#endif
+
+//  PWM_DEFAULT_CONFIG_COUNT_MODE  - Count mode
+
+// <0=> Up
+// <1=> Up and Down
+
+#ifndef PWM_DEFAULT_CONFIG_COUNT_MODE
+#define PWM_DEFAULT_CONFIG_COUNT_MODE 0
+#endif
+
+//  PWM_DEFAULT_CONFIG_TOP_VALUE - Top value
+#ifndef PWM_DEFAULT_CONFIG_TOP_VALUE
+#define PWM_DEFAULT_CONFIG_TOP_VALUE 1000
+#endif
+
+//  PWM_DEFAULT_CONFIG_LOAD_MODE  - Load mode
+
+// <0=> Common
+// <1=> Grouped
+// <2=> Individual
+// <3=> Waveform
+
+#ifndef PWM_DEFAULT_CONFIG_LOAD_MODE
+#define PWM_DEFAULT_CONFIG_LOAD_MODE 0
+#endif
+
+//  PWM_DEFAULT_CONFIG_STEP_MODE  - Step mode
+
+// <0=> Auto
+// <1=> Triggered
+
+#ifndef PWM_DEFAULT_CONFIG_STEP_MODE
+#define PWM_DEFAULT_CONFIG_STEP_MODE 0
+#endif
+
+//  PWM_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef PWM_DEFAULT_CONFIG_IRQ_PRIORITY
+#define PWM_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  PWM0_ENABLED  - Enable PWM0 instance
+
+
+#ifndef PWM0_ENABLED
+#define PWM0_ENABLED 0
+#endif
+
+//  PWM1_ENABLED  - Enable PWM1 instance
+
+
+#ifndef PWM1_ENABLED
+#define PWM1_ENABLED 0
+#endif
+
+//  PWM2_ENABLED  - Enable PWM2 instance
+
+
+#ifndef PWM2_ENABLED
+#define PWM2_ENABLED 0
+#endif
+
+//  PWM3_ENABLED  - Enable PWM3 instance
+
+
+#ifndef PWM3_ENABLED
+#define PWM3_ENABLED 0
+#endif
+
+// 
+
+//  QDEC_ENABLED - nrf_drv_qdec - QDEC peripheral driver - legacy layer
+//==========================================================
+#ifndef QDEC_ENABLED
+#define QDEC_ENABLED 0
+#endif
+//  QDEC_CONFIG_REPORTPER  - Report period
+
+// <0=> 10 Samples
+// <1=> 40 Samples
+// <2=> 80 Samples
+// <3=> 120 Samples
+// <4=> 160 Samples
+// <5=> 200 Samples
+// <6=> 240 Samples
+// <7=> 280 Samples
+
+#ifndef QDEC_CONFIG_REPORTPER
+#define QDEC_CONFIG_REPORTPER 0
+#endif
+
+//  QDEC_CONFIG_SAMPLEPER  - Sample period
+
+// <0=> 128 us
+// <1=> 256 us
+// <2=> 512 us
+// <3=> 1024 us
+// <4=> 2048 us
+// <5=> 4096 us
+// <6=> 8192 us
+// <7=> 16384 us
+
+#ifndef QDEC_CONFIG_SAMPLEPER
+#define QDEC_CONFIG_SAMPLEPER 7
+#endif
+
+//  QDEC_CONFIG_PIO_A - A pin  <0-31>
+
+
+#ifndef QDEC_CONFIG_PIO_A
+#define QDEC_CONFIG_PIO_A 31
+#endif
+
+//  QDEC_CONFIG_PIO_B - B pin  <0-31>
+
+
+#ifndef QDEC_CONFIG_PIO_B
+#define QDEC_CONFIG_PIO_B 31
+#endif
+
+//  QDEC_CONFIG_PIO_LED - LED pin  <0-31>
+
+
+#ifndef QDEC_CONFIG_PIO_LED
+#define QDEC_CONFIG_PIO_LED 31
+#endif
+
+//  QDEC_CONFIG_LEDPRE - LED pre
+#ifndef QDEC_CONFIG_LEDPRE
+#define QDEC_CONFIG_LEDPRE 511
+#endif
+
+//  QDEC_CONFIG_LEDPOL  - LED polarity
+
+// <0=> Active low
+// <1=> Active high
+
+#ifndef QDEC_CONFIG_LEDPOL
+#define QDEC_CONFIG_LEDPOL 1
+#endif
+
+//  QDEC_CONFIG_DBFEN  - Debouncing enable
+
+
+#ifndef QDEC_CONFIG_DBFEN
+#define QDEC_CONFIG_DBFEN 0
+#endif
+
+//  QDEC_CONFIG_SAMPLE_INTEN  - Sample ready interrupt enable
+
+
+#ifndef QDEC_CONFIG_SAMPLE_INTEN
+#define QDEC_CONFIG_SAMPLE_INTEN 0
+#endif
+
+//  QDEC_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef QDEC_CONFIG_IRQ_PRIORITY
+#define QDEC_CONFIG_IRQ_PRIORITY 6
+#endif
+
+// 
+
+//  QSPI_ENABLED - nrf_drv_qspi - QSPI peripheral driver - legacy layer
+//==========================================================
+#ifndef QSPI_ENABLED
+#define QSPI_ENABLED 0
+#endif
+//  QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns).  <0-255>
+
+
+#ifndef QSPI_CONFIG_SCK_DELAY
+#define QSPI_CONFIG_SCK_DELAY 1
+#endif
+
+//  QSPI_CONFIG_XIP_OFFSET - Address offset in the external memory for Execute in Place operation.
+#ifndef QSPI_CONFIG_XIP_OFFSET
+#define QSPI_CONFIG_XIP_OFFSET 0
+#endif
+
+//  QSPI_CONFIG_READOC  - Number of data lines and opcode used for reading.
+
+// <0=> FastRead
+// <1=> Read2O
+// <2=> Read2IO
+// <3=> Read4O
+// <4=> Read4IO
+
+#ifndef QSPI_CONFIG_READOC
+#define QSPI_CONFIG_READOC 0
+#endif
+
+//  QSPI_CONFIG_WRITEOC  - Number of data lines and opcode used for writing.
+
+// <0=> PP
+// <1=> PP2O
+// <2=> PP4O
+// <3=> PP4IO
+
+#ifndef QSPI_CONFIG_WRITEOC
+#define QSPI_CONFIG_WRITEOC 0
+#endif
+
+//  QSPI_CONFIG_ADDRMODE  - Addressing mode.
+
+// <0=> 24bit
+// <1=> 32bit
+
+#ifndef QSPI_CONFIG_ADDRMODE
+#define QSPI_CONFIG_ADDRMODE 0
+#endif
+
+//  QSPI_CONFIG_MODE  - SPI mode.
+
+// <0=> Mode 0
+// <1=> Mode 1
+
+#ifndef QSPI_CONFIG_MODE
+#define QSPI_CONFIG_MODE 0
+#endif
+
+//  QSPI_CONFIG_FREQUENCY  - Frequency divider.
+
+// <0=> 32MHz/1
+// <1=> 32MHz/2
+// <2=> 32MHz/3
+// <3=> 32MHz/4
+// <4=> 32MHz/5
+// <5=> 32MHz/6
+// <6=> 32MHz/7
+// <7=> 32MHz/8
+// <8=> 32MHz/9
+// <9=> 32MHz/10
+// <10=> 32MHz/11
+// <11=> 32MHz/12
+// <12=> 32MHz/13
+// <13=> 32MHz/14
+// <14=> 32MHz/15
+// <15=> 32MHz/16
+
+#ifndef QSPI_CONFIG_FREQUENCY
+#define QSPI_CONFIG_FREQUENCY 15
+#endif
+
+//  QSPI_PIN_SCK - SCK pin value.
+#ifndef QSPI_PIN_SCK
+#define QSPI_PIN_SCK NRF_QSPI_PIN_NOT_CONNECTED
+#endif
+
+//  QSPI_PIN_CSN - CSN pin value.
+#ifndef QSPI_PIN_CSN
+#define QSPI_PIN_CSN NRF_QSPI_PIN_NOT_CONNECTED
+#endif
+
+//  QSPI_PIN_IO0 - IO0 pin value.
+#ifndef QSPI_PIN_IO0
+#define QSPI_PIN_IO0 NRF_QSPI_PIN_NOT_CONNECTED
+#endif
+
+//  QSPI_PIN_IO1 - IO1 pin value.
+#ifndef QSPI_PIN_IO1
+#define QSPI_PIN_IO1 NRF_QSPI_PIN_NOT_CONNECTED
+#endif
+
+//  QSPI_PIN_IO2 - IO2 pin value.
+#ifndef QSPI_PIN_IO2
+#define QSPI_PIN_IO2 NRF_QSPI_PIN_NOT_CONNECTED
+#endif
+
+//  QSPI_PIN_IO3 - IO3 pin value.
+#ifndef QSPI_PIN_IO3
+#define QSPI_PIN_IO3 NRF_QSPI_PIN_NOT_CONNECTED
+#endif
+
+//  QSPI_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef QSPI_CONFIG_IRQ_PRIORITY
+#define QSPI_CONFIG_IRQ_PRIORITY 6
+#endif
+
+// 
+
+//  RNG_ENABLED - nrf_drv_rng - RNG peripheral driver - legacy layer
+//==========================================================
+#ifndef RNG_ENABLED
+#define RNG_ENABLED 0
+#endif
+//  RNG_CONFIG_ERROR_CORRECTION  - Error correction
+
+
+#ifndef RNG_CONFIG_ERROR_CORRECTION
+#define RNG_CONFIG_ERROR_CORRECTION 1
+#endif
+
+//  RNG_CONFIG_POOL_SIZE - Pool size
+#ifndef RNG_CONFIG_POOL_SIZE
+#define RNG_CONFIG_POOL_SIZE 64
+#endif
+
+//  RNG_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef RNG_CONFIG_IRQ_PRIORITY
+#define RNG_CONFIG_IRQ_PRIORITY 6
+#endif
+
+// 
+
+//  RTC_ENABLED - nrf_drv_rtc - RTC peripheral driver - legacy layer
+//==========================================================
+#ifndef RTC_ENABLED
+#define RTC_ENABLED 0
+#endif
+//  RTC_DEFAULT_CONFIG_FREQUENCY - Frequency  <16-32768>
+
+
+#ifndef RTC_DEFAULT_CONFIG_FREQUENCY
+#define RTC_DEFAULT_CONFIG_FREQUENCY 32768
+#endif
+
+//  RTC_DEFAULT_CONFIG_RELIABLE  - Ensures safe compare event triggering
+
+
+#ifndef RTC_DEFAULT_CONFIG_RELIABLE
+#define RTC_DEFAULT_CONFIG_RELIABLE 0
+#endif
+
+//  RTC_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef RTC_DEFAULT_CONFIG_IRQ_PRIORITY
+#define RTC_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  RTC0_ENABLED  - Enable RTC0 instance
+
+
+#ifndef RTC0_ENABLED
+#define RTC0_ENABLED 0
+#endif
+
+//  RTC1_ENABLED  - Enable RTC1 instance
+
+
+#ifndef RTC1_ENABLED
+#define RTC1_ENABLED 0
+#endif
+
+//  RTC2_ENABLED  - Enable RTC2 instance
+
+
+#ifndef RTC2_ENABLED
+#define RTC2_ENABLED 0
+#endif
+
+//  NRF_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt
+#ifndef NRF_MAXIMUM_LATENCY_US
+#define NRF_MAXIMUM_LATENCY_US 2000
+#endif
+
+// 
+
+//  SAADC_ENABLED - nrf_drv_saadc - SAADC peripheral driver - legacy layer
+//==========================================================
+#ifndef SAADC_ENABLED
+#define SAADC_ENABLED 0
+#endif
+//  SAADC_CONFIG_RESOLUTION  - Resolution
+
+// <0=> 8 bit
+// <1=> 10 bit
+// <2=> 12 bit
+// <3=> 14 bit
+
+#ifndef SAADC_CONFIG_RESOLUTION
+#define SAADC_CONFIG_RESOLUTION 1
+#endif
+
+//  SAADC_CONFIG_OVERSAMPLE  - Sample period
+
+// <0=> Disabled
+// <1=> 2x
+// <2=> 4x
+// <3=> 8x
+// <4=> 16x
+// <5=> 32x
+// <6=> 64x
+// <7=> 128x
+// <8=> 256x
+
+#ifndef SAADC_CONFIG_OVERSAMPLE
+#define SAADC_CONFIG_OVERSAMPLE 0
+#endif
+
+//  SAADC_CONFIG_LP_MODE  - Enabling low power mode
+
+
+#ifndef SAADC_CONFIG_LP_MODE
+#define SAADC_CONFIG_LP_MODE 0
+#endif
+
+//  SAADC_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef SAADC_CONFIG_IRQ_PRIORITY
+#define SAADC_CONFIG_IRQ_PRIORITY 6
+#endif
+
+// 
+
+//  SPIS_ENABLED - nrf_drv_spis - SPIS peripheral driver - legacy layer
+//==========================================================
+#ifndef SPIS_ENABLED
+#define SPIS_ENABLED 0
+#endif
+//  SPIS_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
+#define SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  SPIS_DEFAULT_MODE  - Mode
+
+// <0=> MODE_0
+// <1=> MODE_1
+// <2=> MODE_2
+// <3=> MODE_3
+
+#ifndef SPIS_DEFAULT_MODE
+#define SPIS_DEFAULT_MODE 0
+#endif
+
+//  SPIS_DEFAULT_BIT_ORDER  - SPIS default bit order
+
+// <0=> MSB first
+// <1=> LSB first
+
+#ifndef SPIS_DEFAULT_BIT_ORDER
+#define SPIS_DEFAULT_BIT_ORDER 0
+#endif
+
+//  SPIS_DEFAULT_DEF - SPIS default DEF character  <0-255>
+
+
+#ifndef SPIS_DEFAULT_DEF
+#define SPIS_DEFAULT_DEF 255
+#endif
+
+//  SPIS_DEFAULT_ORC - SPIS default ORC character  <0-255>
+
+
+#ifndef SPIS_DEFAULT_ORC
+#define SPIS_DEFAULT_ORC 255
+#endif
+
+//  SPIS0_ENABLED  - Enable SPIS0 instance
+
+
+#ifndef SPIS0_ENABLED
+#define SPIS0_ENABLED 0
+#endif
+
+//  SPIS1_ENABLED  - Enable SPIS1 instance
+
+
+#ifndef SPIS1_ENABLED
+#define SPIS1_ENABLED 0
+#endif
+
+//  SPIS2_ENABLED  - Enable SPIS2 instance
+
+
+#ifndef SPIS2_ENABLED
+#define SPIS2_ENABLED 0
+#endif
+
+// 
+
+//  SPI_ENABLED - nrf_drv_spi - SPI/SPIM peripheral driver - legacy layer
+//==========================================================
+#ifndef SPI_ENABLED
+#define SPI_ENABLED 0
+#endif
+//  SPI_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef SPI_DEFAULT_CONFIG_IRQ_PRIORITY
+#define SPI_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  NRF_SPI_DRV_MISO_PULLUP_CFG  - MISO PIN pull-up configuration.
+
+// <0=> NRF_GPIO_PIN_NOPULL
+// <1=> NRF_GPIO_PIN_PULLDOWN
+// <3=> NRF_GPIO_PIN_PULLUP
+
+#ifndef NRF_SPI_DRV_MISO_PULLUP_CFG
+#define NRF_SPI_DRV_MISO_PULLUP_CFG 1
+#endif
+
+//  SPI0_ENABLED - Enable SPI0 instance
+//==========================================================
+#ifndef SPI0_ENABLED
+#define SPI0_ENABLED 0
+#endif
+//  SPI0_USE_EASY_DMA  - Use EasyDMA
+
+
+#ifndef SPI0_USE_EASY_DMA
+#define SPI0_USE_EASY_DMA 1
+#endif
+
+// 
+
+//  SPI1_ENABLED - Enable SPI1 instance
+//==========================================================
+#ifndef SPI1_ENABLED
+#define SPI1_ENABLED 0
+#endif
+//  SPI1_USE_EASY_DMA  - Use EasyDMA
+
+
+#ifndef SPI1_USE_EASY_DMA
+#define SPI1_USE_EASY_DMA 1
+#endif
+
+// 
+
+//  SPI2_ENABLED - Enable SPI2 instance
+//==========================================================
+#ifndef SPI2_ENABLED
+#define SPI2_ENABLED 0
+#endif
+//  SPI2_USE_EASY_DMA  - Use EasyDMA
+
+
+#ifndef SPI2_USE_EASY_DMA
+#define SPI2_USE_EASY_DMA 1
+#endif
+
+// 
+
+// 
+
+//  TIMER_ENABLED - nrf_drv_timer - TIMER periperal driver - legacy layer
+//==========================================================
+#ifndef TIMER_ENABLED
+#define TIMER_ENABLED 0
+#endif
+//  TIMER_DEFAULT_CONFIG_FREQUENCY  - Timer frequency if in Timer mode
+
+// <0=> 16 MHz
+// <1=> 8 MHz
+// <2=> 4 MHz
+// <3=> 2 MHz
+// <4=> 1 MHz
+// <5=> 500 kHz
+// <6=> 250 kHz
+// <7=> 125 kHz
+// <8=> 62.5 kHz
+// <9=> 31.25 kHz
+
+#ifndef TIMER_DEFAULT_CONFIG_FREQUENCY
+#define TIMER_DEFAULT_CONFIG_FREQUENCY 0
+#endif
+
+//  TIMER_DEFAULT_CONFIG_MODE  - Timer mode or operation
+
+// <0=> Timer
+// <1=> Counter
+
+#ifndef TIMER_DEFAULT_CONFIG_MODE
+#define TIMER_DEFAULT_CONFIG_MODE 0
+#endif
+
+//  TIMER_DEFAULT_CONFIG_BIT_WIDTH  - Timer counter bit width
+
+// <0=> 16 bit
+// <1=> 8 bit
+// <2=> 24 bit
+// <3=> 32 bit
+
+#ifndef TIMER_DEFAULT_CONFIG_BIT_WIDTH
+#define TIMER_DEFAULT_CONFIG_BIT_WIDTH 0
+#endif
+
+//  TIMER_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
+#define TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  TIMER0_ENABLED  - Enable TIMER0 instance
+
+
+#ifndef TIMER0_ENABLED
+#define TIMER0_ENABLED 0
+#endif
+
+//  TIMER1_ENABLED  - Enable TIMER1 instance
+
+
+#ifndef TIMER1_ENABLED
+#define TIMER1_ENABLED 0
+#endif
+
+//  TIMER2_ENABLED  - Enable TIMER2 instance
+
+
+#ifndef TIMER2_ENABLED
+#define TIMER2_ENABLED 0
+#endif
+
+//  TIMER3_ENABLED  - Enable TIMER3 instance
+
+
+#ifndef TIMER3_ENABLED
+#define TIMER3_ENABLED 0
+#endif
+
+//  TIMER4_ENABLED  - Enable TIMER4 instance
+
+
+#ifndef TIMER4_ENABLED
+#define TIMER4_ENABLED 0
+#endif
+
+// 
+
+//  TWIS_ENABLED - nrf_drv_twis - TWIS peripheral driver - legacy layer
+//==========================================================
+#ifndef TWIS_ENABLED
+#define TWIS_ENABLED 0
+#endif
+//  TWIS0_ENABLED  - Enable TWIS0 instance
+
+
+#ifndef TWIS0_ENABLED
+#define TWIS0_ENABLED 0
+#endif
+
+//  TWIS1_ENABLED  - Enable TWIS1 instance
+
+
+#ifndef TWIS1_ENABLED
+#define TWIS1_ENABLED 0
+#endif
+
+//  TWIS_ASSUME_INIT_AFTER_RESET_ONLY  - Assume that any instance would be initialized only once
+
+
+//  Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code.
+
+#ifndef TWIS_ASSUME_INIT_AFTER_RESET_ONLY
+#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
+#endif
+
+//  TWIS_NO_SYNC_MODE  - Remove support for synchronous mode
+
+
+//  Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources.
+
+#ifndef TWIS_NO_SYNC_MODE
+#define TWIS_NO_SYNC_MODE 0
+#endif
+
+//  TWIS_DEFAULT_CONFIG_ADDR0 - Address0
+#ifndef TWIS_DEFAULT_CONFIG_ADDR0
+#define TWIS_DEFAULT_CONFIG_ADDR0 0
+#endif
+
+//  TWIS_DEFAULT_CONFIG_ADDR1 - Address1
+#ifndef TWIS_DEFAULT_CONFIG_ADDR1
+#define TWIS_DEFAULT_CONFIG_ADDR1 0
+#endif
+
+//  TWIS_DEFAULT_CONFIG_SCL_PULL  - SCL pin pull configuration
+
+// <0=> Disabled
+// <1=> Pull down
+// <3=> Pull up
+
+#ifndef TWIS_DEFAULT_CONFIG_SCL_PULL
+#define TWIS_DEFAULT_CONFIG_SCL_PULL 0
+#endif
+
+//  TWIS_DEFAULT_CONFIG_SDA_PULL  - SDA pin pull configuration
+
+// <0=> Disabled
+// <1=> Pull down
+// <3=> Pull up
+
+#ifndef TWIS_DEFAULT_CONFIG_SDA_PULL
+#define TWIS_DEFAULT_CONFIG_SDA_PULL 0
+#endif
+
+//  TWIS_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
+#define TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+// 
+
+//  TWI_ENABLED - nrf_drv_twi - TWI/TWIM peripheral driver - legacy layer
+//==========================================================
+#ifndef TWI_ENABLED
+#define TWI_ENABLED 0
+#endif
+//  TWI_DEFAULT_CONFIG_FREQUENCY  - Frequency
+
+// <26738688=> 100k
+// <67108864=> 250k
+// <104857600=> 400k
+
+#ifndef TWI_DEFAULT_CONFIG_FREQUENCY
+#define TWI_DEFAULT_CONFIG_FREQUENCY 26738688
+#endif
+
+//  TWI_DEFAULT_CONFIG_CLR_BUS_INIT  - Enables bus clearing procedure during init
+
+
+#ifndef TWI_DEFAULT_CONFIG_CLR_BUS_INIT
+#define TWI_DEFAULT_CONFIG_CLR_BUS_INIT 0
+#endif
+
+//  TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT  - Enables bus holding after uninit
+
+
+#ifndef TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT
+#define TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0
+#endif
+
+//  TWI_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef TWI_DEFAULT_CONFIG_IRQ_PRIORITY
+#define TWI_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  TWI0_ENABLED - Enable TWI0 instance
+//==========================================================
+#ifndef TWI0_ENABLED
+#define TWI0_ENABLED 0
+#endif
+//  TWI0_USE_EASY_DMA  - Use EasyDMA (if present)
+
+
+#ifndef TWI0_USE_EASY_DMA
+#define TWI0_USE_EASY_DMA 0
+#endif
+
+// 
+
+//  TWI1_ENABLED - Enable TWI1 instance
+//==========================================================
+#ifndef TWI1_ENABLED
+#define TWI1_ENABLED 0
+#endif
+//  TWI1_USE_EASY_DMA  - Use EasyDMA (if present)
+
+
+#ifndef TWI1_USE_EASY_DMA
+#define TWI1_USE_EASY_DMA 0
+#endif
+
+// 
+
+// 
+
+//  UART_ENABLED - nrf_drv_uart - UART/UARTE peripheral driver - legacy layer
+//==========================================================
+#ifndef UART_ENABLED
+#define UART_ENABLED 0
+#endif
+//  UART_DEFAULT_CONFIG_HWFC  - Hardware Flow Control
+
+// <0=> Disabled
+// <1=> Enabled
+
+#ifndef UART_DEFAULT_CONFIG_HWFC
+#define UART_DEFAULT_CONFIG_HWFC 0
+#endif
+
+//  UART_DEFAULT_CONFIG_PARITY  - Parity
+
+// <0=> Excluded
+// <14=> Included
+
+#ifndef UART_DEFAULT_CONFIG_PARITY
+#define UART_DEFAULT_CONFIG_PARITY 0
+#endif
+
+//  UART_DEFAULT_CONFIG_BAUDRATE  - Default Baudrate
+
+// <323584=> 1200 baud
+// <643072=> 2400 baud
+// <1290240=> 4800 baud
+// <2576384=> 9600 baud
+// <3862528=> 14400 baud
+// <5152768=> 19200 baud
+// <7716864=> 28800 baud
+// <10289152=> 38400 baud
+// <15400960=> 57600 baud
+// <20615168=> 76800 baud
+// <30801920=> 115200 baud
+// <61865984=> 230400 baud
+// <67108864=> 250000 baud
+// <121634816=> 460800 baud
+// <251658240=> 921600 baud
+// <268435456=> 1000000 baud
+
+#ifndef UART_DEFAULT_CONFIG_BAUDRATE
+#define UART_DEFAULT_CONFIG_BAUDRATE 30801920
+#endif
+
+//  UART_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef UART_DEFAULT_CONFIG_IRQ_PRIORITY
+#define UART_DEFAULT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  UART_EASY_DMA_SUPPORT  - Driver supporting EasyDMA
+
+
+#ifndef UART_EASY_DMA_SUPPORT
+#define UART_EASY_DMA_SUPPORT 1
+#endif
+
+//  UART_LEGACY_SUPPORT  - Driver supporting Legacy mode
+
+
+#ifndef UART_LEGACY_SUPPORT
+#define UART_LEGACY_SUPPORT 1
+#endif
+
+//  UART0_ENABLED - Enable UART0 instance
+//==========================================================
+#ifndef UART0_ENABLED
+#define UART0_ENABLED 0
+#endif
+//  UART0_CONFIG_USE_EASY_DMA  - Default setting for using EasyDMA
+
+
+#ifndef UART0_CONFIG_USE_EASY_DMA
+#define UART0_CONFIG_USE_EASY_DMA 1
+#endif
+
+// 
+
+//  UART1_ENABLED - Enable UART1 instance
+//==========================================================
+#ifndef UART1_ENABLED
+#define UART1_ENABLED 0
+#endif
+// 
+
+// 
+
+//  USBD_ENABLED - nrf_drv_usbd - Software Component
+//==========================================================
+#ifndef USBD_ENABLED
+#define USBD_ENABLED 0
+#endif
+//  USBD_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef USBD_CONFIG_IRQ_PRIORITY
+#define USBD_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  USBD_CONFIG_DMASCHEDULER_MODE  - USBD SMA scheduler working scheme
+
+// <0=> Prioritized access
+// <1=> Round Robin
+
+#ifndef USBD_CONFIG_DMASCHEDULER_MODE
+#define USBD_CONFIG_DMASCHEDULER_MODE 0
+#endif
+
+//  USBD_CONFIG_DMASCHEDULER_ISO_BOOST  - Give priority to isochronous transfers
+
+
+//  This option gives priority to isochronous transfers.
+//  Enabling it assures that isochronous transfers are always processed,
+//  even if multiple other transfers are pending.
+//  Isochronous endpoints are prioritized before the usbd_dma_scheduler_algorithm
+//  function is called, so the option is independent of the algorithm chosen.
+
+#ifndef USBD_CONFIG_DMASCHEDULER_ISO_BOOST
+#define USBD_CONFIG_DMASCHEDULER_ISO_BOOST 1
+#endif
+
+//  USBD_CONFIG_ISO_IN_ZLP  - Respond to an IN token on ISO IN endpoint with ZLP when no data is ready
+
+
+//  If set, ISO IN endpoint will respond to an IN token with ZLP when no data is ready to be sent.
+//  Else, there will be no response.
+//  NOTE: This option does not work on Engineering A chip.
+
+#ifndef USBD_CONFIG_ISO_IN_ZLP
+#define USBD_CONFIG_ISO_IN_ZLP 0
+#endif
+
+// 
+
+//  WDT_ENABLED - nrf_drv_wdt - WDT peripheral driver - legacy layer
+//==========================================================
+#ifndef WDT_ENABLED
+#define WDT_ENABLED 0
+#endif
+//  WDT_CONFIG_BEHAVIOUR  - WDT behavior in CPU SLEEP or HALT mode
+
+// <1=> Run in SLEEP, Pause in HALT
+// <8=> Pause in SLEEP, Run in HALT
+// <9=> Run in SLEEP and HALT
+// <0=> Pause in SLEEP and HALT
+
+#ifndef WDT_CONFIG_BEHAVIOUR
+#define WDT_CONFIG_BEHAVIOUR 1
+#endif
+
+//  WDT_CONFIG_RELOAD_VALUE - Reload value  <15-4294967295>
+
+
+#ifndef WDT_CONFIG_RELOAD_VALUE
+#define WDT_CONFIG_RELOAD_VALUE 2000
+#endif
+
+//  WDT_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef WDT_CONFIG_IRQ_PRIORITY
+#define WDT_CONFIG_IRQ_PRIORITY 6
+#endif
+
+// 
+
+// 
+//==========================================================
+
+//  nRF_Drivers_External
+
+//==========================================================
+//  NRF_TWI_SENSOR_ENABLED  - nrf_twi_sensor - nRF TWI Sensor module
+
+
+#ifndef NRF_TWI_SENSOR_ENABLED
+#define NRF_TWI_SENSOR_ENABLED 0
+#endif
+
+// 
+//==========================================================
+
+//  nRF_Libraries
+
+//==========================================================
+//  APP_GPIOTE_ENABLED  - app_gpiote - GPIOTE events dispatcher
+
+
+#ifndef APP_GPIOTE_ENABLED
+#define APP_GPIOTE_ENABLED 0
+#endif
+
+//  APP_PWM_ENABLED  - app_pwm - PWM functionality
+
+
+#ifndef APP_PWM_ENABLED
+#define APP_PWM_ENABLED 0
+#endif
+
+//  APP_SCHEDULER_ENABLED - app_scheduler - Events scheduler
+//==========================================================
+#ifndef APP_SCHEDULER_ENABLED
+#define APP_SCHEDULER_ENABLED 0
+#endif
+//  APP_SCHEDULER_WITH_PAUSE  - Enabling pause feature
+
+
+#ifndef APP_SCHEDULER_WITH_PAUSE
+#define APP_SCHEDULER_WITH_PAUSE 0
+#endif
+
+//  APP_SCHEDULER_WITH_PROFILER  - Enabling scheduler profiling
+
+
+#ifndef APP_SCHEDULER_WITH_PROFILER
+#define APP_SCHEDULER_WITH_PROFILER 0
+#endif
+
+// 
+
+//  APP_SDCARD_ENABLED - app_sdcard - SD/MMC card support using SPI
+//==========================================================
+#ifndef APP_SDCARD_ENABLED
+#define APP_SDCARD_ENABLED 0
+#endif
+//  APP_SDCARD_SPI_INSTANCE  - SPI instance used
+
+// <0=> 0
+// <1=> 1
+// <2=> 2
+
+#ifndef APP_SDCARD_SPI_INSTANCE
+#define APP_SDCARD_SPI_INSTANCE 0
+#endif
+
+//  APP_SDCARD_FREQ_INIT  - SPI frequency
+
+// <33554432=> 125 kHz
+// <67108864=> 250 kHz
+// <134217728=> 500 kHz
+// <268435456=> 1 MHz
+// <536870912=> 2 MHz
+// <1073741824=> 4 MHz
+// <2147483648=> 8 MHz
+
+#ifndef APP_SDCARD_FREQ_INIT
+#define APP_SDCARD_FREQ_INIT 67108864
+#endif
+
+//  APP_SDCARD_FREQ_DATA  - SPI frequency
+
+// <33554432=> 125 kHz
+// <67108864=> 250 kHz
+// <134217728=> 500 kHz
+// <268435456=> 1 MHz
+// <536870912=> 2 MHz
+// <1073741824=> 4 MHz
+// <2147483648=> 8 MHz
+
+#ifndef APP_SDCARD_FREQ_DATA
+#define APP_SDCARD_FREQ_DATA 1073741824
+#endif
+
+// 
+
+//  APP_TIMER_ENABLED - app_timer - Application timer functionality
+//==========================================================
+#ifndef APP_TIMER_ENABLED
+#define APP_TIMER_ENABLED 0
+#endif
+//  APP_TIMER_CONFIG_RTC_FREQUENCY  - Configure RTC prescaler.
+
+// <0=> 32768 Hz
+// <1=> 16384 Hz
+// <3=> 8192 Hz
+// <7=> 4096 Hz
+// <15=> 2048 Hz
+// <31=> 1024 Hz
+
+#ifndef APP_TIMER_CONFIG_RTC_FREQUENCY
+#define APP_TIMER_CONFIG_RTC_FREQUENCY 1
+#endif
+
+//  APP_TIMER_CONFIG_IRQ_PRIORITY  - Interrupt priority
+
+
+//  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
+
+#ifndef APP_TIMER_CONFIG_IRQ_PRIORITY
+#define APP_TIMER_CONFIG_IRQ_PRIORITY 6
+#endif
+
+//  APP_TIMER_CONFIG_OP_QUEUE_SIZE - Capacity of timer requests queue.
+//  Size of the queue depends on how many timers are used
+//  in the system, how often timers are started and overall
+//  system latency. If queue size is too small app_timer calls
+//  will fail.
+
+#ifndef APP_TIMER_CONFIG_OP_QUEUE_SIZE
+#define APP_TIMER_CONFIG_OP_QUEUE_SIZE 10
+#endif
+
+//  APP_TIMER_CONFIG_USE_SCHEDULER  - Enable scheduling app_timer events to app_scheduler
+
+
+#ifndef APP_TIMER_CONFIG_USE_SCHEDULER
+#define APP_TIMER_CONFIG_USE_SCHEDULER 0
+#endif
+
+//  APP_TIMER_KEEPS_RTC_ACTIVE  - Enable RTC always on
+
+
+//  If option is enabled RTC is kept running even if there is no active timers.
+//  This option can be used when app_timer is used for timestamping.
+
+#ifndef APP_TIMER_KEEPS_RTC_ACTIVE
+#define APP_TIMER_KEEPS_RTC_ACTIVE 0
+#endif
+
+//  APP_TIMER_SAFE_WINDOW_MS - Maximum possible latency (in milliseconds) of handling app_timer event.
+//  Maximum possible timeout that can be set is reduced by safe window.
+//  Example: RTC frequency 16384 Hz, maximum possible timeout 1024 seconds - APP_TIMER_SAFE_WINDOW_MS.
+//  Since RTC is not stopped when processor is halted in debugging session, this value
+//  must cover it if debugging is needed. It is possible to halt processor for APP_TIMER_SAFE_WINDOW_MS
+//  without corrupting app_timer behavior.
+
+#ifndef APP_TIMER_SAFE_WINDOW_MS
+#define APP_TIMER_SAFE_WINDOW_MS 300000
+#endif
+
+//  App Timer Legacy configuration - Legacy configuration.
+
+//==========================================================
+//  APP_TIMER_WITH_PROFILER  - Enable app_timer profiling
+
+
+#ifndef APP_TIMER_WITH_PROFILER
+#define APP_TIMER_WITH_PROFILER 0
+#endif
+
+//  APP_TIMER_CONFIG_SWI_NUMBER  - Configure SWI instance used.
+
+
+#ifndef APP_TIMER_CONFIG_SWI_NUMBER
+#define APP_TIMER_CONFIG_SWI_NUMBER 0
+#endif
+
+// 
+//==========================================================
+
+// 
+
+//  APP_USBD_AUDIO_ENABLED  - app_usbd_audio - USB AUDIO class
+
+
+#ifndef APP_USBD_AUDIO_ENABLED
+#define APP_USBD_AUDIO_ENABLED 0
+#endif
+
+//  APP_USBD_ENABLED - app_usbd - USB Device library
+//==========================================================
+#ifndef APP_USBD_ENABLED
+#define APP_USBD_ENABLED 0
+#endif
+//  APP_USBD_VID - Vendor ID.  <0x0000-0xFFFF>
+
+
+//  Note: This value is not editable in Configuration Wizard.
+//  Vendor ID ordered from USB IF: http://www.usb.org/developers/vendor/
+
+#ifndef APP_USBD_VID
+#define APP_USBD_VID 0
+#endif
+
+//  APP_USBD_PID - Product ID.  <0x0000-0xFFFF>
+
+
+//  Note: This value is not editable in Configuration Wizard.
+//  Selected Product ID
+
+#ifndef APP_USBD_PID
+#define APP_USBD_PID 0
+#endif
+
+//  APP_USBD_DEVICE_VER_MAJOR - Major device version  <0-99>
+
+
+//  Major device version, will be converted automatically to BCD notation. Use just decimal values.
+
+#ifndef APP_USBD_DEVICE_VER_MAJOR
+#define APP_USBD_DEVICE_VER_MAJOR 1
+#endif
+
+//  APP_USBD_DEVICE_VER_MINOR - Minor device version  <0-9>
+
+
+//  Minor device version, will be converted automatically to BCD notation. Use just decimal values.
+
+#ifndef APP_USBD_DEVICE_VER_MINOR
+#define APP_USBD_DEVICE_VER_MINOR 0
+#endif
+
+//  APP_USBD_DEVICE_VER_SUB - Sub-minor device version  <0-9>
+
+
+//  Sub-minor device version, will be converted automatically to BCD notation. Use just decimal values.
+
+#ifndef APP_USBD_DEVICE_VER_SUB
+#define APP_USBD_DEVICE_VER_SUB 0
+#endif
+
+//  APP_USBD_CONFIG_SELF_POWERED  - Self-powered device, as opposed to bus-powered.
+
+
+#ifndef APP_USBD_CONFIG_SELF_POWERED
+#define APP_USBD_CONFIG_SELF_POWERED 1
+#endif
+
+//  APP_USBD_CONFIG_MAX_POWER - MaxPower field in configuration descriptor in milliamps.  <0-500>
+
+
+#ifndef APP_USBD_CONFIG_MAX_POWER
+#define APP_USBD_CONFIG_MAX_POWER 100
+#endif
+
+//  APP_USBD_CONFIG_POWER_EVENTS_PROCESS  - Process power events.
+
+
+//  Enable processing power events in USB event handler.
+
+#ifndef APP_USBD_CONFIG_POWER_EVENTS_PROCESS
+#define APP_USBD_CONFIG_POWER_EVENTS_PROCESS 1
+#endif
+
+//  APP_USBD_CONFIG_EVENT_QUEUE_ENABLE - Enable event queue.
+
+//  This is the default configuration when all the events are placed into internal queue.
+//  Disable it when an external queue is used like app_scheduler or if you wish to process all events inside interrupts.
+//  Processing all events from the interrupt level adds requirement not to call any functions that modifies the USBD library state from the context higher than USB interrupt context.
+//  Functions that modify USBD state are functions for sleep, wakeup, start, stop, enable, and disable.
+//==========================================================
+#ifndef APP_USBD_CONFIG_EVENT_QUEUE_ENABLE
+#define APP_USBD_CONFIG_EVENT_QUEUE_ENABLE 1
+#endif
+//  APP_USBD_CONFIG_EVENT_QUEUE_SIZE - The size of the event queue.  <16-64>
+
+
+//  The size of the queue for the events that would be processed in the main loop.
+
+#ifndef APP_USBD_CONFIG_EVENT_QUEUE_SIZE
+#define APP_USBD_CONFIG_EVENT_QUEUE_SIZE 32
+#endif
+
+//  APP_USBD_CONFIG_SOF_HANDLING_MODE  - Change SOF events handling mode.
+
+
+//  Normal queue   - SOF events are pushed normally into the event queue.
+//  Compress queue - SOF events are counted and binded with other events or executed when the queue is empty.
+//                   This prevents the queue from filling up with SOF events.
+//  Interrupt      - SOF events are processed in interrupt.
+// <0=> Normal queue
+// <1=> Compress queue
+// <2=> Interrupt
+
+#ifndef APP_USBD_CONFIG_SOF_HANDLING_MODE
+#define APP_USBD_CONFIG_SOF_HANDLING_MODE 1
+#endif
+
+// 
+
+//  APP_USBD_CONFIG_SOF_TIMESTAMP_PROVIDE  - Provide a function that generates timestamps for logs based on the current SOF.
+
+
+//  The function app_usbd_sof_timestamp_get is implemented if the logger is enabled.
+//  Use it when initializing the logger.
+//  SOF processing is always enabled when this configuration parameter is active.
+//  Note: This option is configured outside of APP_USBD_CONFIG_LOG_ENABLED.
+//  This means that it works even if the logging in this very module is disabled.
+
+#ifndef APP_USBD_CONFIG_SOF_TIMESTAMP_PROVIDE
+#define APP_USBD_CONFIG_SOF_TIMESTAMP_PROVIDE 0
+#endif
+
+//  APP_USBD_CONFIG_DESC_STRING_SIZE - Maximum size of the NULL-terminated string of the string descriptor.  <31-254>
+
+
+//  31 characters can be stored in the internal USB buffer used for transfers.
+//  Any value higher than 31 creates an additional buffer just for descriptor strings.
+
+#ifndef APP_USBD_CONFIG_DESC_STRING_SIZE
+#define APP_USBD_CONFIG_DESC_STRING_SIZE 31
+#endif
+
+//  APP_USBD_CONFIG_DESC_STRING_UTF_ENABLED  - Enable UTF8 conversion.
+
+
+//  Enable UTF8-encoded characters. In normal processing, only ASCII characters are available.
+
+#ifndef APP_USBD_CONFIG_DESC_STRING_UTF_ENABLED
+#define APP_USBD_CONFIG_DESC_STRING_UTF_ENABLED 0
+#endif
+
+//  APP_USBD_STRINGS_LANGIDS - Supported languages identifiers.
+
+//  Note: This value is not editable in Configuration Wizard.
+//  Comma-separated list of supported languages.
+#ifndef APP_USBD_STRINGS_LANGIDS
+#define APP_USBD_STRINGS_LANGIDS APP_USBD_LANG_AND_SUBLANG(APP_USBD_LANG_ENGLISH, APP_USBD_SUBLANG_ENGLISH_US)
+#endif
+
+//  APP_USBD_STRING_ID_MANUFACTURER - Define manufacturer string ID.
+
+//  Setting ID to 0 disables the string.
+//==========================================================
+#ifndef APP_USBD_STRING_ID_MANUFACTURER
+#define APP_USBD_STRING_ID_MANUFACTURER 1
+#endif
+//  APP_USBD_STRINGS_MANUFACTURER_EXTERN  - Define whether @ref APP_USBD_STRINGS_MANUFACTURER is created by macro or declared as a global variable.
+
+
+#ifndef APP_USBD_STRINGS_MANUFACTURER_EXTERN
+#define APP_USBD_STRINGS_MANUFACTURER_EXTERN 0
+#endif
+
+//  APP_USBD_STRINGS_MANUFACTURER - String descriptor for the manufacturer name.
+
+//  Note: This value is not editable in Configuration Wizard.
+//  Comma-separated list of manufacturer names for each defined language.
+//  Use @ref APP_USBD_STRING_DESC macro to create string descriptor from a NULL-terminated string.
+//  Use @ref APP_USBD_STRING_RAW8_DESC macro to create string descriptor from comma-separated uint8_t values.
+//  Use @ref APP_USBD_STRING_RAW16_DESC macro to create string descriptor from comma-separated uint16_t values.
+//  Alternatively, configure the macro to point to any internal variable pointer that already contains the descriptor.
+//  Setting string to NULL disables that string.
+//  The order of manufacturer names must be the same like in @ref APP_USBD_STRINGS_LANGIDS.
+#ifndef APP_USBD_STRINGS_MANUFACTURER
+#define APP_USBD_STRINGS_MANUFACTURER APP_USBD_STRING_DESC("Nordic Semiconductor")
+#endif
+
+// 
+
+//  APP_USBD_STRING_ID_PRODUCT - Define product string ID.
+
+//  Setting ID to 0 disables the string.
+//==========================================================
+#ifndef APP_USBD_STRING_ID_PRODUCT
+#define APP_USBD_STRING_ID_PRODUCT 2
+#endif
+//  APP_USBD_STRINGS_PRODUCT_EXTERN  - Define whether @ref APP_USBD_STRINGS_PRODUCT is created by macro or declared as a global variable.
+
+
+#ifndef APP_USBD_STRINGS_PRODUCT_EXTERN
+#define APP_USBD_STRINGS_PRODUCT_EXTERN 0
+#endif
+
+//  APP_USBD_STRINGS_PRODUCT - String descriptor for the product name.
+
+//  Note: This value is not editable in Configuration Wizard.
+//  List of product names that is defined the same way like in @ref APP_USBD_STRINGS_MANUFACTURER.
+#ifndef APP_USBD_STRINGS_PRODUCT
+#define APP_USBD_STRINGS_PRODUCT APP_USBD_STRING_DESC("nRF52 USB Product")
+#endif
+
+// 
+
+//  APP_USBD_STRING_ID_SERIAL - Define serial number string ID.
+
+//  Setting ID to 0 disables the string.
+//==========================================================
+#ifndef APP_USBD_STRING_ID_SERIAL
+#define APP_USBD_STRING_ID_SERIAL 3
+#endif
+//  APP_USBD_STRING_SERIAL_EXTERN  - Define whether @ref APP_USBD_STRING_SERIAL is created by macro or declared as a global variable.
+
+
+#ifndef APP_USBD_STRING_SERIAL_EXTERN
+#define APP_USBD_STRING_SERIAL_EXTERN 0
+#endif
+
+//  APP_USBD_STRING_SERIAL - String descriptor for the serial number.
+
+//  Note: This value is not editable in Configuration Wizard.
+//  Serial number that is defined the same way like in @ref APP_USBD_STRINGS_MANUFACTURER.
+#ifndef APP_USBD_STRING_SERIAL
+#define APP_USBD_STRING_SERIAL APP_USBD_STRING_DESC("000000000000")
+#endif
+
+// 
+
+//  APP_USBD_STRING_ID_CONFIGURATION - Define configuration string ID.
+
+//  Setting ID to 0 disables the string.
+//==========================================================
+#ifndef APP_USBD_STRING_ID_CONFIGURATION
+#define APP_USBD_STRING_ID_CONFIGURATION 4
+#endif
+//  APP_USBD_STRING_CONFIGURATION_EXTERN  - Define whether @ref APP_USBD_STRINGS_CONFIGURATION is created by macro or declared as global variable.
+
+
+#ifndef APP_USBD_STRING_CONFIGURATION_EXTERN
+#define APP_USBD_STRING_CONFIGURATION_EXTERN 0
+#endif
+
+//  APP_USBD_STRINGS_CONFIGURATION - String descriptor for the device configuration.
+
+//  Note: This value is not editable in Configuration Wizard.
+//  Configuration string that is defined the same way like in @ref APP_USBD_STRINGS_MANUFACTURER.
+#ifndef APP_USBD_STRINGS_CONFIGURATION
+#define APP_USBD_STRINGS_CONFIGURATION APP_USBD_STRING_DESC("Default configuration")
+#endif
+
+// 
+
+//  APP_USBD_STRINGS_USER - Default values for user strings.
+
+//  Note: This value is not editable in Configuration Wizard.
+//  This value stores all application specific user strings with the default initialization.
+//  The setup is done by X-macros.
+//  Expected macro parameters:
+//  @code
+//  X(mnemonic, [=str_idx], ...)
+//  @endcode
+//  - @c mnemonic: Mnemonic of the string descriptor that would be added to
+//                 @ref app_usbd_string_desc_idx_t enumerator.
+//  - @c str_idx : String index value, can be set or left empty.
+//                 For example, WinUSB driver requires descriptor to be present on 0xEE index.
+//                 Then use X(USBD_STRING_WINUSB, =0xEE, (APP_USBD_STRING_DESC(...)))
+//  - @c ...     : List of string descriptors for each defined language.
+#ifndef APP_USBD_STRINGS_USER
+#define APP_USBD_STRINGS_USER X(APP_USER_1, , APP_USBD_STRING_DESC("User 1"))
+#endif
+
+// 
+
+//  APP_USBD_HID_ENABLED - app_usbd_hid - USB HID class
+//==========================================================
+#ifndef APP_USBD_HID_ENABLED
+#define APP_USBD_HID_ENABLED 0
+#endif
+//  APP_USBD_HID_DEFAULT_IDLE_RATE - Default idle rate for HID class.   <0-255>
+
+
+//  0 means indefinite duration, any other value is multiplied by 4 milliseconds. Refer to Chapter 7.2.4 of HID 1.11 Specification.
+
+#ifndef APP_USBD_HID_DEFAULT_IDLE_RATE
+#define APP_USBD_HID_DEFAULT_IDLE_RATE 0
+#endif
+
+//  APP_USBD_HID_REPORT_IDLE_TABLE_SIZE - Size of idle rate table.   <1-255>
+
+
+//  Must be higher than the highest report ID used.
+
+#ifndef APP_USBD_HID_REPORT_IDLE_TABLE_SIZE
+#define APP_USBD_HID_REPORT_IDLE_TABLE_SIZE 4
+#endif
+
+// 
+
+//  APP_USBD_HID_GENERIC_ENABLED  - app_usbd_hid_generic - USB HID generic
+
+
+#ifndef APP_USBD_HID_GENERIC_ENABLED
+#define APP_USBD_HID_GENERIC_ENABLED 0
+#endif
+
+//  APP_USBD_HID_KBD_ENABLED  - app_usbd_hid_kbd - USB HID keyboard
+
+
+#ifndef APP_USBD_HID_KBD_ENABLED
+#define APP_USBD_HID_KBD_ENABLED 0
+#endif
+
+//  APP_USBD_HID_MOUSE_ENABLED  - app_usbd_hid_mouse - USB HID mouse
+
+
+#ifndef APP_USBD_HID_MOUSE_ENABLED
+#define APP_USBD_HID_MOUSE_ENABLED 0
+#endif
+
+//  APP_USBD_MSC_ENABLED  - app_usbd_msc - USB MSC class
+
+
+#ifndef APP_USBD_MSC_ENABLED
+#define APP_USBD_MSC_ENABLED 0
+#endif
+
+//  CRC16_ENABLED  - crc16 - CRC16 calculation routines
+
+
+#ifndef CRC16_ENABLED
+#define CRC16_ENABLED 0
+#endif
+
+//  CRC32_ENABLED  - crc32 - CRC32 calculation routines
+
+
+#ifndef CRC32_ENABLED
+#define CRC32_ENABLED 0
+#endif
+
+//  ECC_ENABLED  - ecc - Elliptic Curve Cryptography Library
+
+
+#ifndef ECC_ENABLED
+#define ECC_ENABLED 0
+#endif
+
+//  FDS_ENABLED - fds - Flash data storage module
+//==========================================================
+#ifndef FDS_ENABLED
+#define FDS_ENABLED 0
+#endif
+//  Pages - Virtual page settings
+
+//  Configure the number of virtual pages to use and their size.
+//==========================================================
+//  FDS_VIRTUAL_PAGES - Number of virtual flash pages to use.
+//  One of the virtual pages is reserved by the system for garbage collection.
+//  Therefore, the minimum is two virtual pages: one page to store data and one page to be used by the system for garbage collection.
+//  The total amount of flash memory that is used by FDS amounts to @ref FDS_VIRTUAL_PAGES * @ref FDS_VIRTUAL_PAGE_SIZE * 4 bytes.
+
+#ifndef FDS_VIRTUAL_PAGES
+#define FDS_VIRTUAL_PAGES 3
+#endif
+
+//  FDS_VIRTUAL_PAGE_SIZE  - The size of a virtual flash page.
+
+
+//  Expressed in number of 4-byte words.
+//  By default, a virtual page is the same size as a physical page.
+//  The size of a virtual page must be a multiple of the size of a physical page.
+// <1024=> 1024
+// <2048=> 2048
+
+#ifndef FDS_VIRTUAL_PAGE_SIZE
+#define FDS_VIRTUAL_PAGE_SIZE 1024
+#endif
+
+//  FDS_VIRTUAL_PAGES_RESERVED - The number of virtual flash pages that are used by other modules.
+//  FDS module stores its data in the last pages of the flash memory.
+//  By setting this value, you can move flash end address used by the FDS.
+//  As a result the reserved space can be used by other modules.
+
+#ifndef FDS_VIRTUAL_PAGES_RESERVED
+#define FDS_VIRTUAL_PAGES_RESERVED 0
+#endif
+
+// 
+//==========================================================
+
+//  Backend - Backend configuration
+
+//  Configure which nrf_fstorage backend is used by FDS to write to flash.
+//==========================================================
+//  FDS_BACKEND  - FDS flash backend.
+
+
+//  NRF_FSTORAGE_SD uses the nrf_fstorage_sd backend implementation using the SoftDevice API. Use this if you have a SoftDevice present.
+//  NRF_FSTORAGE_NVMC uses the nrf_fstorage_nvmc implementation. Use this setting if you don't use the SoftDevice.
+// <1=> NRF_FSTORAGE_NVMC
+// <2=> NRF_FSTORAGE_SD
+
+#ifndef FDS_BACKEND
+#define FDS_BACKEND 2
+#endif
+
+// 
+//==========================================================
+
+//  Queue - Queue settings
+
+//==========================================================
+//  FDS_OP_QUEUE_SIZE - Size of the internal queue.
+//  Increase this value if you frequently get synchronous FDS_ERR_NO_SPACE_IN_QUEUES errors.
+
+#ifndef FDS_OP_QUEUE_SIZE
+#define FDS_OP_QUEUE_SIZE 4
+#endif
+
+// 
+//==========================================================
+
+//  CRC - CRC functionality
+
+//==========================================================
+//  FDS_CRC_CHECK_ON_READ - Enable CRC checks.
+
+//  Save a record's CRC when it is written to flash and check it when the record is opened.
+//  Records with an incorrect CRC can still be 'seen' by the user using FDS functions, but they cannot be opened.
+//  Additionally, they will not be garbage collected until they are deleted.
+//==========================================================
+#ifndef FDS_CRC_CHECK_ON_READ
+#define FDS_CRC_CHECK_ON_READ 0
+#endif
+//  FDS_CRC_CHECK_ON_WRITE  - Perform a CRC check on newly written records.
+
+
+//  Perform a CRC check on newly written records.
+//  This setting can be used to make sure that the record data was not altered while being written to flash.
+// <1=> Enabled
+// <0=> Disabled
+
+#ifndef FDS_CRC_CHECK_ON_WRITE
+#define FDS_CRC_CHECK_ON_WRITE 0
+#endif
+
+// 
+
+// 
+//==========================================================
+
+//  Users - Number of users
+
+//==========================================================
+//  FDS_MAX_USERS - Maximum number of callbacks that can be registered.
+#ifndef FDS_MAX_USERS
+#define FDS_MAX_USERS 4
+#endif
+
+// 
+//==========================================================
+
+// 
+
+//  HARDFAULT_HANDLER_ENABLED  - hardfault_default - HardFault default handler for debugging and release
+
+
+#ifndef HARDFAULT_HANDLER_ENABLED
+#define HARDFAULT_HANDLER_ENABLED 0
+#endif
+
+//  HCI_MEM_POOL_ENABLED - hci_mem_pool - memory pool implementation used by HCI
+//==========================================================
+#ifndef HCI_MEM_POOL_ENABLED
+#define HCI_MEM_POOL_ENABLED 0
+#endif
+//  HCI_TX_BUF_SIZE - TX buffer size in bytes.
+#ifndef HCI_TX_BUF_SIZE
+#define HCI_TX_BUF_SIZE 600
+#endif
+
+//  HCI_RX_BUF_SIZE - RX buffer size in bytes.
+#ifndef HCI_RX_BUF_SIZE
+#define HCI_RX_BUF_SIZE 600
+#endif
+
+//  HCI_RX_BUF_QUEUE_SIZE - RX buffer queue size.
+#ifndef HCI_RX_BUF_QUEUE_SIZE
+#define HCI_RX_BUF_QUEUE_SIZE 4
+#endif
+
+// 
+
+//  HCI_SLIP_ENABLED - hci_slip - SLIP protocol implementation used by HCI
+//==========================================================
+#ifndef HCI_SLIP_ENABLED
+#define HCI_SLIP_ENABLED 0
+#endif
+//  HCI_UART_BAUDRATE  - Default Baudrate
+
+// <323584=> 1200 baud
+// <643072=> 2400 baud
+// <1290240=> 4800 baud
+// <2576384=> 9600 baud
+// <3862528=> 14400 baud
+// <5152768=> 19200 baud
+// <7716864=> 28800 baud
+// <10289152=> 38400 baud
+// <15400960=> 57600 baud
+// <20615168=> 76800 baud
+// <30801920=> 115200 baud
+// <61865984=> 230400 baud
+// <67108864=> 250000 baud
+// <121634816=> 460800 baud
+// <251658240=> 921600 baud
+// <268435456=> 1000000 baud
+
+#ifndef HCI_UART_BAUDRATE
+#define HCI_UART_BAUDRATE 30801920
+#endif
+
+//  HCI_UART_FLOW_CONTROL  - Hardware Flow Control
+
+// <0=> Disabled
+// <1=> Enabled
+
+#ifndef HCI_UART_FLOW_CONTROL
+#define HCI_UART_FLOW_CONTROL 0
+#endif
+
+//  HCI_UART_RX_PIN - UART RX pin
+#ifndef HCI_UART_RX_PIN
+#define HCI_UART_RX_PIN 31
+#endif
+
+//  HCI_UART_TX_PIN - UART TX pin
+#ifndef HCI_UART_TX_PIN
+#define HCI_UART_TX_PIN 31
+#endif
+
+//  HCI_UART_RTS_PIN - UART RTS pin
+#ifndef HCI_UART_RTS_PIN
+#define HCI_UART_RTS_PIN 31
+#endif
+
+//  HCI_UART_CTS_PIN - UART CTS pin
+#ifndef HCI_UART_CTS_PIN
+#define HCI_UART_CTS_PIN 31
+#endif
+
+// 
+
+//  HCI_TRANSPORT_ENABLED - hci_transport - HCI transport
+//==========================================================
+#ifndef HCI_TRANSPORT_ENABLED
+#define HCI_TRANSPORT_ENABLED 0
+#endif
+//  HCI_MAX_PACKET_SIZE_IN_BITS - Maximum size of a single application packet in bits.
+#ifndef HCI_MAX_PACKET_SIZE_IN_BITS
+#define HCI_MAX_PACKET_SIZE_IN_BITS 8000
+#endif
+
+// 
+
+//  LED_SOFTBLINK_ENABLED  - led_softblink - led_softblink module
+
+
+#ifndef LED_SOFTBLINK_ENABLED
+#define LED_SOFTBLINK_ENABLED 0
+#endif
+
+//  LOW_POWER_PWM_ENABLED  - low_power_pwm - low_power_pwm module
+
+
+#ifndef LOW_POWER_PWM_ENABLED
+#define LOW_POWER_PWM_ENABLED 0
+#endif
+
+//  MEM_MANAGER_ENABLED - mem_manager - Dynamic memory allocator
+//==========================================================
+#ifndef MEM_MANAGER_ENABLED
+#define MEM_MANAGER_ENABLED 0
+#endif
+//  MEMORY_MANAGER_SMALL_BLOCK_COUNT - Size of each memory blocks identified as 'small' block.  <0-255>
+
+
+#ifndef MEMORY_MANAGER_SMALL_BLOCK_COUNT
+#define MEMORY_MANAGER_SMALL_BLOCK_COUNT 1
+#endif
+
+//  MEMORY_MANAGER_SMALL_BLOCK_SIZE -  Size of each memory blocks identified as 'small' block.
+//   Size of each memory blocks identified as 'small' block. Memory block are recommended to be word-sized.
+
+#ifndef MEMORY_MANAGER_SMALL_BLOCK_SIZE
+#define MEMORY_MANAGER_SMALL_BLOCK_SIZE 32
+#endif
+
+//  MEMORY_MANAGER_MEDIUM_BLOCK_COUNT - Size of each memory blocks identified as 'medium' block.  <0-255>
+
+
+#ifndef MEMORY_MANAGER_MEDIUM_BLOCK_COUNT
+#define MEMORY_MANAGER_MEDIUM_BLOCK_COUNT 0
+#endif
+
+//  MEMORY_MANAGER_MEDIUM_BLOCK_SIZE -  Size of each memory blocks identified as 'medium' block.
+//   Size of each memory blocks identified as 'medium' block. Memory block are recommended to be word-sized.
+
+#ifndef MEMORY_MANAGER_MEDIUM_BLOCK_SIZE
+#define MEMORY_MANAGER_MEDIUM_BLOCK_SIZE 256
+#endif
+
+//  MEMORY_MANAGER_LARGE_BLOCK_COUNT - Size of each memory blocks identified as 'large' block.  <0-255>
+
+
+#ifndef MEMORY_MANAGER_LARGE_BLOCK_COUNT
+#define MEMORY_MANAGER_LARGE_BLOCK_COUNT 0
+#endif
+
+//  MEMORY_MANAGER_LARGE_BLOCK_SIZE -  Size of each memory blocks identified as 'large' block.
+//   Size of each memory blocks identified as 'large' block. Memory block are recommended to be word-sized.
+
+#ifndef MEMORY_MANAGER_LARGE_BLOCK_SIZE
+#define MEMORY_MANAGER_LARGE_BLOCK_SIZE 256
+#endif
+
+//  MEMORY_MANAGER_XLARGE_BLOCK_COUNT - Size of each memory blocks identified as 'extra large' block.  <0-255>
+
+
+#ifndef MEMORY_MANAGER_XLARGE_BLOCK_COUNT
+#define MEMORY_MANAGER_XLARGE_BLOCK_COUNT 0
+#endif
+
+//  MEMORY_MANAGER_XLARGE_BLOCK_SIZE -  Size of each memory blocks identified as 'extra large' block.
+//   Size of each memory blocks identified as 'extra large' block. Memory block are recommended to be word-sized.
+
+#ifndef MEMORY_MANAGER_XLARGE_BLOCK_SIZE
+#define MEMORY_MANAGER_XLARGE_BLOCK_SIZE 1320
+#endif
+
+//  MEMORY_MANAGER_XXLARGE_BLOCK_COUNT - Size of each memory blocks identified as 'extra extra large' block.  <0-255>
+
+
+#ifndef MEMORY_MANAGER_XXLARGE_BLOCK_COUNT
+#define MEMORY_MANAGER_XXLARGE_BLOCK_COUNT 0
+#endif
+
+//  MEMORY_MANAGER_XXLARGE_BLOCK_SIZE -  Size of each memory blocks identified as 'extra extra large' block.
+//   Size of each memory blocks identified as 'extra extra large' block. Memory block are recommended to be word-sized.
+
+#ifndef MEMORY_MANAGER_XXLARGE_BLOCK_SIZE
+#define MEMORY_MANAGER_XXLARGE_BLOCK_SIZE 3444
+#endif
+
+//  MEMORY_MANAGER_XSMALL_BLOCK_COUNT - Size of each memory blocks identified as 'extra small' block.  <0-255>
+
+
+#ifndef MEMORY_MANAGER_XSMALL_BLOCK_COUNT
+#define MEMORY_MANAGER_XSMALL_BLOCK_COUNT 0
+#endif
+
+//  MEMORY_MANAGER_XSMALL_BLOCK_SIZE -  Size of each memory blocks identified as 'extra small' block.
+//   Size of each memory blocks identified as 'extra large' block. Memory block are recommended to be word-sized.
+
+#ifndef MEMORY_MANAGER_XSMALL_BLOCK_SIZE
+#define MEMORY_MANAGER_XSMALL_BLOCK_SIZE 64
+#endif
+
+//  MEMORY_MANAGER_XXSMALL_BLOCK_COUNT - Size of each memory blocks identified as 'extra extra small' block.  <0-255>
+
+
+#ifndef MEMORY_MANAGER_XXSMALL_BLOCK_COUNT
+#define MEMORY_MANAGER_XXSMALL_BLOCK_COUNT 0
+#endif
+
+//  MEMORY_MANAGER_XXSMALL_BLOCK_SIZE -  Size of each memory blocks identified as 'extra extra small' block.
+//   Size of each memory blocks identified as 'extra extra small' block. Memory block are recommended to be word-sized.
+
+#ifndef MEMORY_MANAGER_XXSMALL_BLOCK_SIZE
+#define MEMORY_MANAGER_XXSMALL_BLOCK_SIZE 32
+#endif
+
+//  MEM_MANAGER_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef MEM_MANAGER_CONFIG_LOG_ENABLED
+#define MEM_MANAGER_CONFIG_LOG_ENABLED 0
+#endif
+//  MEM_MANAGER_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef MEM_MANAGER_CONFIG_LOG_LEVEL
+#define MEM_MANAGER_CONFIG_LOG_LEVEL 3
+#endif
+
+//  MEM_MANAGER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef MEM_MANAGER_CONFIG_INFO_COLOR
+#define MEM_MANAGER_CONFIG_INFO_COLOR 0
+#endif
+
+//  MEM_MANAGER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef MEM_MANAGER_CONFIG_DEBUG_COLOR
+#define MEM_MANAGER_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  MEM_MANAGER_DISABLE_API_PARAM_CHECK  - Disable API parameter checks in the module.
+
+
+#ifndef MEM_MANAGER_DISABLE_API_PARAM_CHECK
+#define MEM_MANAGER_DISABLE_API_PARAM_CHECK 0
+#endif
+
+// 
+
+//  NRF_BALLOC_ENABLED - nrf_balloc - Block allocator module
+//==========================================================
+#ifndef NRF_BALLOC_ENABLED
+#define NRF_BALLOC_ENABLED 1
+#endif
+//  NRF_BALLOC_CONFIG_DEBUG_ENABLED - Enables debug mode in the module.
+//==========================================================
+#ifndef NRF_BALLOC_CONFIG_DEBUG_ENABLED
+#define NRF_BALLOC_CONFIG_DEBUG_ENABLED 0
+#endif
+//  NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS - Number of words used as head guard.  <0-255>
+
+
+#ifndef NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS
+#define NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS 1
+#endif
+
+//  NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS - Number of words used as tail guard.  <0-255>
+
+
+#ifndef NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS
+#define NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS 1
+#endif
+
+//  NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED  - Enables basic checks in this module.
+
+
+#ifndef NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED
+#define NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED 0
+#endif
+
+//  NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED  - Enables double memory free check in this module.
+
+
+#ifndef NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED
+#define NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED 0
+#endif
+
+//  NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED  - Enables free memory corruption check in this module.
+
+
+#ifndef NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED
+#define NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED 0
+#endif
+
+//  NRF_BALLOC_CLI_CMDS  - Enable CLI commands specific to the module
+
+
+#ifndef NRF_BALLOC_CLI_CMDS
+#define NRF_BALLOC_CLI_CMDS 0
+#endif
+
+// 
+
+// 
+
+//  NRF_CSENSE_ENABLED - nrf_csense - Capacitive sensor module
+//==========================================================
+#ifndef NRF_CSENSE_ENABLED
+#define NRF_CSENSE_ENABLED 0
+#endif
+//  NRF_CSENSE_PAD_HYSTERESIS - Minimum value of change required to determine that a pad was touched.
+#ifndef NRF_CSENSE_PAD_HYSTERESIS
+#define NRF_CSENSE_PAD_HYSTERESIS 15
+#endif
+
+//  NRF_CSENSE_PAD_DEVIATION - Minimum value measured on a pad required to take it into account while calculating the step.
+#ifndef NRF_CSENSE_PAD_DEVIATION
+#define NRF_CSENSE_PAD_DEVIATION 70
+#endif
+
+//  NRF_CSENSE_MIN_PAD_VALUE - Minimum normalized value on a pad required to take its value into account.
+#ifndef NRF_CSENSE_MIN_PAD_VALUE
+#define NRF_CSENSE_MIN_PAD_VALUE 20
+#endif
+
+//  NRF_CSENSE_MAX_PADS_NUMBER - Maximum number of pads used for one instance.
+#ifndef NRF_CSENSE_MAX_PADS_NUMBER
+#define NRF_CSENSE_MAX_PADS_NUMBER 20
+#endif
+
+//  NRF_CSENSE_MAX_VALUE - Maximum normalized value obtained from measurement.
+#ifndef NRF_CSENSE_MAX_VALUE
+#define NRF_CSENSE_MAX_VALUE 1000
+#endif
+
+//  NRF_CSENSE_OUTPUT_PIN - Output pin used by the low-level module.
+//  This is used when capacitive sensor does not use COMP.
+
+#ifndef NRF_CSENSE_OUTPUT_PIN
+#define NRF_CSENSE_OUTPUT_PIN 26
+#endif
+
+// 
+
+//  NRF_DRV_CSENSE_ENABLED - nrf_drv_csense - Capacitive sensor low-level module
+//==========================================================
+#ifndef NRF_DRV_CSENSE_ENABLED
+#define NRF_DRV_CSENSE_ENABLED 0
+#endif
+//  USE_COMP - Use the comparator to implement the capacitive sensor driver.
+
+//  Due to Anomaly 84, COMP I_SOURCE is not functional. It has too high a varation.
+//==========================================================
+#ifndef USE_COMP
+#define USE_COMP 0
+#endif
+//  TIMER0_FOR_CSENSE - First TIMER instance used by the driver (not used on nRF51).
+#ifndef TIMER0_FOR_CSENSE
+#define TIMER0_FOR_CSENSE 1
+#endif
+
+//  TIMER1_FOR_CSENSE - Second TIMER instance used by the driver (not used on nRF51).
+#ifndef TIMER1_FOR_CSENSE
+#define TIMER1_FOR_CSENSE 2
+#endif
+
+//  MEASUREMENT_PERIOD - Single measurement period.
+//  Time of a single measurement can be calculated as
+//  T = (1/2)*MEASUREMENT_PERIOD*(1/f_OSC) where f_OSC = I_SOURCE / (2C*(VUP-VDOWN) ).
+//  I_SOURCE, VUP, and VDOWN are values used to initialize COMP and C is the capacitance of the used pad.
+
+#ifndef MEASUREMENT_PERIOD
+#define MEASUREMENT_PERIOD 20
+#endif
+
+// 
+
+// 
+
+//  NRF_FSTORAGE_ENABLED - nrf_fstorage - Flash abstraction library
+//==========================================================
+#ifndef NRF_FSTORAGE_ENABLED
+#define NRF_FSTORAGE_ENABLED 0
+#endif
+//  nrf_fstorage - Common settings
+
+//  Common settings to all fstorage implementations
+//==========================================================
+//  NRF_FSTORAGE_PARAM_CHECK_DISABLED  - Disable user input validation
+
+
+//  If selected, use ASSERT to validate user input.
+//  This effectively removes user input validation in production code.
+//  Recommended setting: OFF, only enable this setting if size is a major concern.
+
+#ifndef NRF_FSTORAGE_PARAM_CHECK_DISABLED
+#define NRF_FSTORAGE_PARAM_CHECK_DISABLED 0
+#endif
+
+// 
+//==========================================================
+
+//  nrf_fstorage_sd - Implementation using the SoftDevice
+
+//  Configuration options for the fstorage implementation using the SoftDevice
+//==========================================================
+//  NRF_FSTORAGE_SD_QUEUE_SIZE - Size of the internal queue of operations
+//  Increase this value if API calls frequently return the error @ref NRF_ERROR_NO_MEM.
+
+#ifndef NRF_FSTORAGE_SD_QUEUE_SIZE
+#define NRF_FSTORAGE_SD_QUEUE_SIZE 4
+#endif
+
+//  NRF_FSTORAGE_SD_MAX_RETRIES - Maximum number of attempts at executing an operation when the SoftDevice is busy
+//  Increase this value if events frequently return the @ref NRF_ERROR_TIMEOUT error.
+//  The SoftDevice might fail to schedule flash access due to high BLE activity.
+
+#ifndef NRF_FSTORAGE_SD_MAX_RETRIES
+#define NRF_FSTORAGE_SD_MAX_RETRIES 8
+#endif
+
+//  NRF_FSTORAGE_SD_MAX_WRITE_SIZE - Maximum number of bytes to be written to flash in a single operation
+//  This value must be a multiple of four.
+//  Lowering this value can increase the chances of the SoftDevice being able to execute flash operations in between radio activity.
+//  This value is bound by the maximum number of bytes that can be written to flash in a single call to @ref sd_flash_write.
+//  That is 1024 bytes for nRF51 ICs and 4096 bytes for nRF52 ICs.
+
+#ifndef NRF_FSTORAGE_SD_MAX_WRITE_SIZE
+#define NRF_FSTORAGE_SD_MAX_WRITE_SIZE 4096
+#endif
+
+// 
+//==========================================================
+
+// 
+
+//  NRF_GFX_ENABLED  - nrf_gfx - GFX module
+
+
+#ifndef NRF_GFX_ENABLED
+#define NRF_GFX_ENABLED 0
+#endif
+
+//  NRF_MEMOBJ_ENABLED  - nrf_memobj - Linked memory allocator module
+
+
+#ifndef NRF_MEMOBJ_ENABLED
+#define NRF_MEMOBJ_ENABLED 1
+#endif
+
+//  NRF_PWR_MGMT_ENABLED - nrf_pwr_mgmt - Power management module
+//==========================================================
+#ifndef NRF_PWR_MGMT_ENABLED
+#define NRF_PWR_MGMT_ENABLED 0
+#endif
+//  NRF_PWR_MGMT_CONFIG_DEBUG_PIN_ENABLED - Enables pin debug in the module.
+
+//  Selected pin will be set when CPU is in sleep mode.
+//==========================================================
+#ifndef NRF_PWR_MGMT_CONFIG_DEBUG_PIN_ENABLED
+#define NRF_PWR_MGMT_CONFIG_DEBUG_PIN_ENABLED 0
+#endif
+//  NRF_PWR_MGMT_SLEEP_DEBUG_PIN  - Pin number
+
+// <0=> 0 (P0.0)
+// <1=> 1 (P0.1)
+// <2=> 2 (P0.2)
+// <3=> 3 (P0.3)
+// <4=> 4 (P0.4)
+// <5=> 5 (P0.5)
+// <6=> 6 (P0.6)
+// <7=> 7 (P0.7)
+// <8=> 8 (P0.8)
+// <9=> 9 (P0.9)
+// <10=> 10 (P0.10)
+// <11=> 11 (P0.11)
+// <12=> 12 (P0.12)
+// <13=> 13 (P0.13)
+// <14=> 14 (P0.14)
+// <15=> 15 (P0.15)
+// <16=> 16 (P0.16)
+// <17=> 17 (P0.17)
+// <18=> 18 (P0.18)
+// <19=> 19 (P0.19)
+// <20=> 20 (P0.20)
+// <21=> 21 (P0.21)
+// <22=> 22 (P0.22)
+// <23=> 23 (P0.23)
+// <24=> 24 (P0.24)
+// <25=> 25 (P0.25)
+// <26=> 26 (P0.26)
+// <27=> 27 (P0.27)
+// <28=> 28 (P0.28)
+// <29=> 29 (P0.29)
+// <30=> 30 (P0.30)
+// <31=> 31 (P0.31)
+// <32=> 32 (P1.0)
+// <33=> 33 (P1.1)
+// <34=> 34 (P1.2)
+// <35=> 35 (P1.3)
+// <36=> 36 (P1.4)
+// <37=> 37 (P1.5)
+// <38=> 38 (P1.6)
+// <39=> 39 (P1.7)
+// <40=> 40 (P1.8)
+// <41=> 41 (P1.9)
+// <42=> 42 (P1.10)
+// <43=> 43 (P1.11)
+// <44=> 44 (P1.12)
+// <45=> 45 (P1.13)
+// <46=> 46 (P1.14)
+// <47=> 47 (P1.15)
+// <4294967295=> Not connected
+
+#ifndef NRF_PWR_MGMT_SLEEP_DEBUG_PIN
+#define NRF_PWR_MGMT_SLEEP_DEBUG_PIN 31
+#endif
+
+// 
+
+//  NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED  - Enables CPU usage monitor.
+
+
+//  Module will trace percentage of CPU usage in one second intervals.
+
+#ifndef NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED
+#define NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED 0
+#endif
+
+//  NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_ENABLED - Enable standby timeout.
+//==========================================================
+#ifndef NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_ENABLED
+#define NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_ENABLED 0
+#endif
+//  NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S - Standby timeout (in seconds).
+//  Shutdown procedure will begin no earlier than after this number of seconds.
+
+#ifndef NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S
+#define NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S 3
+#endif
+
+// 
+
+//  NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED  - Enables FPU event cleaning.
+
+
+#ifndef NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED
+#define NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED 0
+#endif
+
+//  NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY  - Blocked shutdown procedure will be retried every second.
+
+
+#ifndef NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY
+#define NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY 0
+#endif
+
+//  NRF_PWR_MGMT_CONFIG_USE_SCHEDULER  - Module will use @ref app_scheduler.
+
+
+#ifndef NRF_PWR_MGMT_CONFIG_USE_SCHEDULER
+#define NRF_PWR_MGMT_CONFIG_USE_SCHEDULER 0
+#endif
+
+//  NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT - The number of priorities for module handlers.
+//  The number of stages of the shutdown process.
+
+#ifndef NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT
+#define NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT 3
+#endif
+
+// 
+
+//  NRF_QUEUE_ENABLED - nrf_queue - Queue module
+//==========================================================
+#ifndef NRF_QUEUE_ENABLED
+#define NRF_QUEUE_ENABLED 0
+#endif
+//  NRF_QUEUE_CLI_CMDS  - Enable CLI commands specific to the module
+
+
+#ifndef NRF_QUEUE_CLI_CMDS
+#define NRF_QUEUE_CLI_CMDS 0
+#endif
+
+// 
+
+//  NRF_SECTION_ITER_ENABLED  - nrf_section_iter - Section iterator
+
+
+#ifndef NRF_SECTION_ITER_ENABLED
+#define NRF_SECTION_ITER_ENABLED 1
+#endif
+
+//  NRF_SORTLIST_ENABLED  - nrf_sortlist - Sorted list
+
+
+#ifndef NRF_SORTLIST_ENABLED
+#define NRF_SORTLIST_ENABLED 1
+#endif
+
+//  NRF_SPI_MNGR_ENABLED  - nrf_spi_mngr - SPI transaction manager
+
+
+#ifndef NRF_SPI_MNGR_ENABLED
+#define NRF_SPI_MNGR_ENABLED 0
+#endif
+
+//  NRF_STRERROR_ENABLED  - nrf_strerror - Library for converting error code to string.
+
+
+#ifndef NRF_STRERROR_ENABLED
+#define NRF_STRERROR_ENABLED 1
+#endif
+
+//  NRF_TWI_MNGR_ENABLED  - nrf_twi_mngr - TWI transaction manager
+
+
+#ifndef NRF_TWI_MNGR_ENABLED
+#define NRF_TWI_MNGR_ENABLED 0
+#endif
+
+//  SLIP_ENABLED  - slip - SLIP encoding and decoding
+
+
+#ifndef SLIP_ENABLED
+#define SLIP_ENABLED 0
+#endif
+
+//  TASK_MANAGER_ENABLED - task_manager - Task manager.
+//==========================================================
+#ifndef TASK_MANAGER_ENABLED
+#define TASK_MANAGER_ENABLED 0
+#endif
+//  TASK_MANAGER_CLI_CMDS  - Enable CLI commands specific to the module
+
+
+#ifndef TASK_MANAGER_CLI_CMDS
+#define TASK_MANAGER_CLI_CMDS 0
+#endif
+
+//  TASK_MANAGER_CONFIG_MAX_TASKS - Maximum number of tasks which can be created
+#ifndef TASK_MANAGER_CONFIG_MAX_TASKS
+#define TASK_MANAGER_CONFIG_MAX_TASKS 2
+#endif
+
+//  TASK_MANAGER_CONFIG_STACK_SIZE - Stack size for every task (power of 2)
+#ifndef TASK_MANAGER_CONFIG_STACK_SIZE
+#define TASK_MANAGER_CONFIG_STACK_SIZE 1024
+#endif
+
+//  TASK_MANAGER_CONFIG_STACK_PROFILER_ENABLED  - Enable stack profiling.
+
+
+#ifndef TASK_MANAGER_CONFIG_STACK_PROFILER_ENABLED
+#define TASK_MANAGER_CONFIG_STACK_PROFILER_ENABLED 1
+#endif
+
+//  TASK_MANAGER_CONFIG_STACK_GUARD  - Configures stack guard.
+
+// <0=> Disabled
+// <4=> 32 bytes
+// <5=> 64 bytes
+// <6=> 128 bytes
+// <7=> 256 bytes
+// <8=> 512 bytes
+
+#ifndef TASK_MANAGER_CONFIG_STACK_GUARD
+#define TASK_MANAGER_CONFIG_STACK_GUARD 7
+#endif
+
+// 
+
+//  app_button - buttons handling module
+
+//==========================================================
+//  BUTTON_ENABLED  - Enables Button module
+
+
+#ifndef BUTTON_ENABLED
+#define BUTTON_ENABLED 0
+#endif
+
+//  BUTTON_HIGH_ACCURACY_ENABLED  - Enables GPIOTE high accuracy for buttons
+
+
+#ifndef BUTTON_HIGH_ACCURACY_ENABLED
+#define BUTTON_HIGH_ACCURACY_ENABLED 0
+#endif
+
+// 
+//==========================================================
+
+//  app_usbd_cdc_acm - USB CDC ACM class
+
+//==========================================================
+//  APP_USBD_CDC_ACM_ENABLED  - Enabling USBD CDC ACM Class library
+
+
+#ifndef APP_USBD_CDC_ACM_ENABLED
+#define APP_USBD_CDC_ACM_ENABLED 0
+#endif
+
+//  APP_USBD_CDC_ACM_ZLP_ON_EPSIZE_WRITE  - Send ZLP on write with same size as endpoint
+
+
+//  If enabled, CDC ACM class will automatically send a zero length packet after transfer which has the same size as endpoint.
+//  This may limit throughput if a lot of binary data is sent, but in terminal mode operation it makes sure that the data is always displayed right after it is sent.
+
+#ifndef APP_USBD_CDC_ACM_ZLP_ON_EPSIZE_WRITE
+#define APP_USBD_CDC_ACM_ZLP_ON_EPSIZE_WRITE 1
+#endif
+
+// 
+//==========================================================
+
+//  nrf_cli - Command line interface
+
+//==========================================================
+//  NRF_CLI_ENABLED  - Enable/disable the CLI module.
+
+
+#ifndef NRF_CLI_ENABLED
+#define NRF_CLI_ENABLED 0
+#endif
+
+//  NRF_CLI_ARGC_MAX - Maximum number of parameters passed to the command handler.
+#ifndef NRF_CLI_ARGC_MAX
+#define NRF_CLI_ARGC_MAX 12
+#endif
+
+//  NRF_CLI_BUILD_IN_CMDS_ENABLED  - CLI built-in commands.
+
+
+#ifndef NRF_CLI_BUILD_IN_CMDS_ENABLED
+#define NRF_CLI_BUILD_IN_CMDS_ENABLED 1
+#endif
+
+//  NRF_CLI_CMD_BUFF_SIZE - Maximum buffer size for a single command.
+#ifndef NRF_CLI_CMD_BUFF_SIZE
+#define NRF_CLI_CMD_BUFF_SIZE 128
+#endif
+
+//  NRF_CLI_ECHO_STATUS  - CLI echo status. If set, echo is ON.
+
+
+#ifndef NRF_CLI_ECHO_STATUS
+#define NRF_CLI_ECHO_STATUS 1
+#endif
+
+//  NRF_CLI_WILDCARD_ENABLED  - Enable wildcard functionality for CLI commands.
+
+
+#ifndef NRF_CLI_WILDCARD_ENABLED
+#define NRF_CLI_WILDCARD_ENABLED 0
+#endif
+
+//  NRF_CLI_METAKEYS_ENABLED  - Enable additional control keys for CLI commands like ctrl+a, ctrl+e, ctrl+w, ctrl+u
+
+
+#ifndef NRF_CLI_METAKEYS_ENABLED
+#define NRF_CLI_METAKEYS_ENABLED 0
+#endif
+
+//  NRF_CLI_PRINTF_BUFF_SIZE - Maximum print buffer size.
+#ifndef NRF_CLI_PRINTF_BUFF_SIZE
+#define NRF_CLI_PRINTF_BUFF_SIZE 23
+#endif
+
+//  NRF_CLI_HISTORY_ENABLED - Enable CLI history mode.
+//==========================================================
+#ifndef NRF_CLI_HISTORY_ENABLED
+#define NRF_CLI_HISTORY_ENABLED 1
+#endif
+//  NRF_CLI_HISTORY_ELEMENT_SIZE - Size of one memory object reserved for CLI history.
+#ifndef NRF_CLI_HISTORY_ELEMENT_SIZE
+#define NRF_CLI_HISTORY_ELEMENT_SIZE 32
+#endif
+
+//  NRF_CLI_HISTORY_ELEMENT_COUNT - Number of history memory objects.
+#ifndef NRF_CLI_HISTORY_ELEMENT_COUNT
+#define NRF_CLI_HISTORY_ELEMENT_COUNT 8
+#endif
+
+// 
+
+//  NRF_CLI_VT100_COLORS_ENABLED  - CLI VT100 colors.
+
+
+#ifndef NRF_CLI_VT100_COLORS_ENABLED
+#define NRF_CLI_VT100_COLORS_ENABLED 1
+#endif
+
+//  NRF_CLI_STATISTICS_ENABLED  - Enable CLI statistics.
+
+
+#ifndef NRF_CLI_STATISTICS_ENABLED
+#define NRF_CLI_STATISTICS_ENABLED 1
+#endif
+
+//  NRF_CLI_LOG_BACKEND  - Enable logger backend interface.
+
+
+#ifndef NRF_CLI_LOG_BACKEND
+#define NRF_CLI_LOG_BACKEND 1
+#endif
+
+//  NRF_CLI_USES_TASK_MANAGER_ENABLED  - Enable CLI to use task_manager
+
+
+#ifndef NRF_CLI_USES_TASK_MANAGER_ENABLED
+#define NRF_CLI_USES_TASK_MANAGER_ENABLED 0
+#endif
+
+// 
+//==========================================================
+
+//  nrf_fprintf - fprintf function.
+
+//==========================================================
+//  NRF_FPRINTF_ENABLED  - Enable/disable fprintf module.
+
+
+#ifndef NRF_FPRINTF_ENABLED
+#define NRF_FPRINTF_ENABLED 1
+#endif
+
+//  NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF_ENABLED  - For each printed LF, function will add CR.
+
+
+#ifndef NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF_ENABLED
+#define NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF_ENABLED 1
+#endif
+
+//  NRF_FPRINTF_DOUBLE_ENABLED  - Enable IEEE-754 double precision formatting.
+
+
+#ifndef NRF_FPRINTF_DOUBLE_ENABLED
+#define NRF_FPRINTF_DOUBLE_ENABLED 0
+#endif
+
+// 
+//==========================================================
+
+// 
+//==========================================================
+
+//  nRF_Log
+
+//==========================================================
+//  NRF_LOG_ENABLED - nrf_log - Logger
+//==========================================================
+#ifndef NRF_LOG_ENABLED
+#define NRF_LOG_ENABLED 0
+#endif
+//  Log message pool - Configuration of log message pool
+
+//==========================================================
+//  NRF_LOG_MSGPOOL_ELEMENT_SIZE - Size of a single element in the pool of memory objects.
+//  If a small value is set, then performance of logs processing
+//  is degraded because data is fragmented. Bigger value impacts
+//  RAM memory utilization. The size is set to fit a message with
+//  a timestamp and up to 2 arguments in a single memory object.
+
+#ifndef NRF_LOG_MSGPOOL_ELEMENT_SIZE
+#define NRF_LOG_MSGPOOL_ELEMENT_SIZE 20
+#endif
+
+//  NRF_LOG_MSGPOOL_ELEMENT_COUNT - Number of elements in the pool of memory objects
+//  If a small value is set, then it may lead to a deadlock
+//  in certain cases if backend has high latency and holds
+//  multiple messages for long time. Bigger value impacts
+//  RAM memory usage.
+
+#ifndef NRF_LOG_MSGPOOL_ELEMENT_COUNT
+#define NRF_LOG_MSGPOOL_ELEMENT_COUNT 8
+#endif
+
+// 
+//==========================================================
+
+//  NRF_LOG_ALLOW_OVERFLOW  - Configures behavior when circular buffer is full.
+
+
+//  If set then oldest logs are overwritten. Otherwise a
+//  marker is injected informing about overflow.
+
+#ifndef NRF_LOG_ALLOW_OVERFLOW
+#define NRF_LOG_ALLOW_OVERFLOW 1
+#endif
+
+//  NRF_LOG_BUFSIZE  - Size of the buffer for storing logs (in bytes).
+
+
+//  Must be power of 2 and multiple of 4.
+//  If NRF_LOG_DEFERRED = 0 then buffer size can be reduced to minimum.
+// <128=> 128
+// <256=> 256
+// <512=> 512
+// <1024=> 1024
+// <2048=> 2048
+// <4096=> 4096
+// <8192=> 8192
+// <16384=> 16384
+
+#ifndef NRF_LOG_BUFSIZE
+#define NRF_LOG_BUFSIZE 1024
+#endif
+
+//  NRF_LOG_CLI_CMDS  - Enable CLI commands for the module.
+
+
+#ifndef NRF_LOG_CLI_CMDS
+#define NRF_LOG_CLI_CMDS 0
+#endif
+
+//  NRF_LOG_DEFAULT_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_LOG_DEFAULT_LEVEL
+#define NRF_LOG_DEFAULT_LEVEL 3
+#endif
+
+//  NRF_LOG_DEFERRED  - Enable deffered logger.
+
+
+//  Log data is buffered and can be processed in idle.
+
+#ifndef NRF_LOG_DEFERRED
+#define NRF_LOG_DEFERRED 1
+#endif
+
+//  NRF_LOG_FILTERS_ENABLED  - Enable dynamic filtering of logs.
+
+
+#ifndef NRF_LOG_FILTERS_ENABLED
+#define NRF_LOG_FILTERS_ENABLED 0
+#endif
+
+//  NRF_LOG_NON_DEFFERED_CRITICAL_REGION_ENABLED  - Enable use of critical region for non deffered mode when flushing logs.
+
+
+//  When enabled NRF_LOG_FLUSH is called from critical section when non deffered mode is used.
+//  Log output will never be corrupted as access to the log backend is exclusive
+//  but system will spend significant amount of time in critical section
+
+#ifndef NRF_LOG_NON_DEFFERED_CRITICAL_REGION_ENABLED
+#define NRF_LOG_NON_DEFFERED_CRITICAL_REGION_ENABLED 0
+#endif
+
+//  NRF_LOG_STR_PUSH_BUFFER_SIZE  - Size of the buffer dedicated for strings stored using @ref NRF_LOG_PUSH.
+
+// <16=> 16
+// <32=> 32
+// <64=> 64
+// <128=> 128
+// <256=> 256
+// <512=> 512
+// <1024=> 1024
+
+#ifndef NRF_LOG_STR_PUSH_BUFFER_SIZE
+#define NRF_LOG_STR_PUSH_BUFFER_SIZE 128
+#endif
+
+//  NRF_LOG_STR_PUSH_BUFFER_SIZE  - Size of the buffer dedicated for strings stored using @ref NRF_LOG_PUSH.
+
+// <16=> 16
+// <32=> 32
+// <64=> 64
+// <128=> 128
+// <256=> 256
+// <512=> 512
+// <1024=> 1024
+
+#ifndef NRF_LOG_STR_PUSH_BUFFER_SIZE
+#define NRF_LOG_STR_PUSH_BUFFER_SIZE 128
+#endif
+
+//  NRF_LOG_USES_COLORS - If enabled then ANSI escape code for colors is prefixed to every string
+//==========================================================
+#ifndef NRF_LOG_USES_COLORS
+#define NRF_LOG_USES_COLORS 0
+#endif
+//  NRF_LOG_COLOR_DEFAULT  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_LOG_COLOR_DEFAULT
+#define NRF_LOG_COLOR_DEFAULT 0
+#endif
+
+//  NRF_LOG_ERROR_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_LOG_ERROR_COLOR
+#define NRF_LOG_ERROR_COLOR 2
+#endif
+
+//  NRF_LOG_WARNING_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_LOG_WARNING_COLOR
+#define NRF_LOG_WARNING_COLOR 4
+#endif
+
+// 
+
+//  NRF_LOG_USES_TIMESTAMP - Enable timestamping
+
+//  Function for getting the timestamp is provided by the user
+//==========================================================
+#ifndef NRF_LOG_USES_TIMESTAMP
+#define NRF_LOG_USES_TIMESTAMP 0
+#endif
+//  NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY - Default frequency of the timestamp (in Hz) or 0 to use app_timer frequency.
+#ifndef NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY
+#define NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY 0
+#endif
+
+// 
+
+//  nrf_log module configuration
+
+//==========================================================
+//  nrf_log in nRF_Core
+
+//==========================================================
+//  NRF_MPU_LIB_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_MPU_LIB_CONFIG_LOG_ENABLED
+#define NRF_MPU_LIB_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_MPU_LIB_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_MPU_LIB_CONFIG_LOG_LEVEL
+#define NRF_MPU_LIB_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_MPU_LIB_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_MPU_LIB_CONFIG_INFO_COLOR
+#define NRF_MPU_LIB_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_MPU_LIB_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_MPU_LIB_CONFIG_DEBUG_COLOR
+#define NRF_MPU_LIB_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_STACK_GUARD_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_STACK_GUARD_CONFIG_LOG_ENABLED
+#define NRF_STACK_GUARD_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_STACK_GUARD_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_STACK_GUARD_CONFIG_LOG_LEVEL
+#define NRF_STACK_GUARD_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_STACK_GUARD_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_STACK_GUARD_CONFIG_INFO_COLOR
+#define NRF_STACK_GUARD_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_STACK_GUARD_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_STACK_GUARD_CONFIG_DEBUG_COLOR
+#define NRF_STACK_GUARD_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  TASK_MANAGER_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef TASK_MANAGER_CONFIG_LOG_ENABLED
+#define TASK_MANAGER_CONFIG_LOG_ENABLED 0
+#endif
+//  TASK_MANAGER_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef TASK_MANAGER_CONFIG_LOG_LEVEL
+#define TASK_MANAGER_CONFIG_LOG_LEVEL 3
+#endif
+
+//  TASK_MANAGER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef TASK_MANAGER_CONFIG_INFO_COLOR
+#define TASK_MANAGER_CONFIG_INFO_COLOR 0
+#endif
+
+//  TASK_MANAGER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef TASK_MANAGER_CONFIG_DEBUG_COLOR
+#define TASK_MANAGER_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+//==========================================================
+
+//  nrf_log in nRF_Drivers
+
+//==========================================================
+//  CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef CLOCK_CONFIG_LOG_ENABLED
+#define CLOCK_CONFIG_LOG_ENABLED 0
+#endif
+//  CLOCK_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef CLOCK_CONFIG_LOG_LEVEL
+#define CLOCK_CONFIG_LOG_LEVEL 3
+#endif
+
+//  CLOCK_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef CLOCK_CONFIG_INFO_COLOR
+#define CLOCK_CONFIG_INFO_COLOR 0
+#endif
+
+//  CLOCK_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef CLOCK_CONFIG_DEBUG_COLOR
+#define CLOCK_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  COMP_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef COMP_CONFIG_LOG_ENABLED
+#define COMP_CONFIG_LOG_ENABLED 0
+#endif
+//  COMP_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef COMP_CONFIG_LOG_LEVEL
+#define COMP_CONFIG_LOG_LEVEL 3
+#endif
+
+//  COMP_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef COMP_CONFIG_INFO_COLOR
+#define COMP_CONFIG_INFO_COLOR 0
+#endif
+
+//  COMP_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef COMP_CONFIG_DEBUG_COLOR
+#define COMP_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef GPIOTE_CONFIG_LOG_ENABLED
+#define GPIOTE_CONFIG_LOG_ENABLED 0
+#endif
+//  GPIOTE_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef GPIOTE_CONFIG_LOG_LEVEL
+#define GPIOTE_CONFIG_LOG_LEVEL 3
+#endif
+
+//  GPIOTE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef GPIOTE_CONFIG_INFO_COLOR
+#define GPIOTE_CONFIG_INFO_COLOR 0
+#endif
+
+//  GPIOTE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef GPIOTE_CONFIG_DEBUG_COLOR
+#define GPIOTE_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  LPCOMP_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef LPCOMP_CONFIG_LOG_ENABLED
+#define LPCOMP_CONFIG_LOG_ENABLED 0
+#endif
+//  LPCOMP_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef LPCOMP_CONFIG_LOG_LEVEL
+#define LPCOMP_CONFIG_LOG_LEVEL 3
+#endif
+
+//  LPCOMP_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef LPCOMP_CONFIG_INFO_COLOR
+#define LPCOMP_CONFIG_INFO_COLOR 0
+#endif
+
+//  LPCOMP_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef LPCOMP_CONFIG_DEBUG_COLOR
+#define LPCOMP_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  MAX3421E_HOST_CONFIG_LOG_ENABLED - Enable logging in the module
+//==========================================================
+#ifndef MAX3421E_HOST_CONFIG_LOG_ENABLED
+#define MAX3421E_HOST_CONFIG_LOG_ENABLED 0
+#endif
+//  MAX3421E_HOST_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef MAX3421E_HOST_CONFIG_LOG_LEVEL
+#define MAX3421E_HOST_CONFIG_LOG_LEVEL 3
+#endif
+
+//  MAX3421E_HOST_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef MAX3421E_HOST_CONFIG_INFO_COLOR
+#define MAX3421E_HOST_CONFIG_INFO_COLOR 0
+#endif
+
+//  MAX3421E_HOST_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef MAX3421E_HOST_CONFIG_DEBUG_COLOR
+#define MAX3421E_HOST_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRFX_USBD_CONFIG_LOG_ENABLED - Enable logging in the module
+//==========================================================
+#ifndef NRFX_USBD_CONFIG_LOG_ENABLED
+#define NRFX_USBD_CONFIG_LOG_ENABLED 0
+#endif
+//  NRFX_USBD_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRFX_USBD_CONFIG_LOG_LEVEL
+#define NRFX_USBD_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRFX_USBD_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_USBD_CONFIG_INFO_COLOR
+#define NRFX_USBD_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRFX_USBD_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRFX_USBD_CONFIG_DEBUG_COLOR
+#define NRFX_USBD_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  PDM_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef PDM_CONFIG_LOG_ENABLED
+#define PDM_CONFIG_LOG_ENABLED 0
+#endif
+//  PDM_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef PDM_CONFIG_LOG_LEVEL
+#define PDM_CONFIG_LOG_LEVEL 3
+#endif
+
+//  PDM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef PDM_CONFIG_INFO_COLOR
+#define PDM_CONFIG_INFO_COLOR 0
+#endif
+
+//  PDM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef PDM_CONFIG_DEBUG_COLOR
+#define PDM_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  PPI_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef PPI_CONFIG_LOG_ENABLED
+#define PPI_CONFIG_LOG_ENABLED 0
+#endif
+//  PPI_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef PPI_CONFIG_LOG_LEVEL
+#define PPI_CONFIG_LOG_LEVEL 3
+#endif
+
+//  PPI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef PPI_CONFIG_INFO_COLOR
+#define PPI_CONFIG_INFO_COLOR 0
+#endif
+
+//  PPI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef PPI_CONFIG_DEBUG_COLOR
+#define PPI_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  PWM_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef PWM_CONFIG_LOG_ENABLED
+#define PWM_CONFIG_LOG_ENABLED 0
+#endif
+//  PWM_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef PWM_CONFIG_LOG_LEVEL
+#define PWM_CONFIG_LOG_LEVEL 3
+#endif
+
+//  PWM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef PWM_CONFIG_INFO_COLOR
+#define PWM_CONFIG_INFO_COLOR 0
+#endif
+
+//  PWM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef PWM_CONFIG_DEBUG_COLOR
+#define PWM_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  QDEC_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef QDEC_CONFIG_LOG_ENABLED
+#define QDEC_CONFIG_LOG_ENABLED 0
+#endif
+//  QDEC_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef QDEC_CONFIG_LOG_LEVEL
+#define QDEC_CONFIG_LOG_LEVEL 3
+#endif
+
+//  QDEC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef QDEC_CONFIG_INFO_COLOR
+#define QDEC_CONFIG_INFO_COLOR 0
+#endif
+
+//  QDEC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef QDEC_CONFIG_DEBUG_COLOR
+#define QDEC_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  RNG_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef RNG_CONFIG_LOG_ENABLED
+#define RNG_CONFIG_LOG_ENABLED 0
+#endif
+//  RNG_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef RNG_CONFIG_LOG_LEVEL
+#define RNG_CONFIG_LOG_LEVEL 3
+#endif
+
+//  RNG_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef RNG_CONFIG_INFO_COLOR
+#define RNG_CONFIG_INFO_COLOR 0
+#endif
+
+//  RNG_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef RNG_CONFIG_DEBUG_COLOR
+#define RNG_CONFIG_DEBUG_COLOR 0
+#endif
+
+//  RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED  - Enables logging of random numbers.
+
+
+#ifndef RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED
+#define RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED 0
+#endif
+
+// 
+
+//  RTC_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef RTC_CONFIG_LOG_ENABLED
+#define RTC_CONFIG_LOG_ENABLED 0
+#endif
+//  RTC_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef RTC_CONFIG_LOG_LEVEL
+#define RTC_CONFIG_LOG_LEVEL 3
+#endif
+
+//  RTC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef RTC_CONFIG_INFO_COLOR
+#define RTC_CONFIG_INFO_COLOR 0
+#endif
+
+//  RTC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef RTC_CONFIG_DEBUG_COLOR
+#define RTC_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  SAADC_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef SAADC_CONFIG_LOG_ENABLED
+#define SAADC_CONFIG_LOG_ENABLED 0
+#endif
+//  SAADC_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef SAADC_CONFIG_LOG_LEVEL
+#define SAADC_CONFIG_LOG_LEVEL 3
+#endif
+
+//  SAADC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef SAADC_CONFIG_INFO_COLOR
+#define SAADC_CONFIG_INFO_COLOR 0
+#endif
+
+//  SAADC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef SAADC_CONFIG_DEBUG_COLOR
+#define SAADC_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  SPIS_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef SPIS_CONFIG_LOG_ENABLED
+#define SPIS_CONFIG_LOG_ENABLED 0
+#endif
+//  SPIS_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef SPIS_CONFIG_LOG_LEVEL
+#define SPIS_CONFIG_LOG_LEVEL 3
+#endif
+
+//  SPIS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef SPIS_CONFIG_INFO_COLOR
+#define SPIS_CONFIG_INFO_COLOR 0
+#endif
+
+//  SPIS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef SPIS_CONFIG_DEBUG_COLOR
+#define SPIS_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  SPI_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef SPI_CONFIG_LOG_ENABLED
+#define SPI_CONFIG_LOG_ENABLED 0
+#endif
+//  SPI_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef SPI_CONFIG_LOG_LEVEL
+#define SPI_CONFIG_LOG_LEVEL 3
+#endif
+
+//  SPI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef SPI_CONFIG_INFO_COLOR
+#define SPI_CONFIG_INFO_COLOR 0
+#endif
+
+//  SPI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef SPI_CONFIG_DEBUG_COLOR
+#define SPI_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  TIMER_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef TIMER_CONFIG_LOG_ENABLED
+#define TIMER_CONFIG_LOG_ENABLED 0
+#endif
+//  TIMER_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef TIMER_CONFIG_LOG_LEVEL
+#define TIMER_CONFIG_LOG_LEVEL 3
+#endif
+
+//  TIMER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef TIMER_CONFIG_INFO_COLOR
+#define TIMER_CONFIG_INFO_COLOR 0
+#endif
+
+//  TIMER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef TIMER_CONFIG_DEBUG_COLOR
+#define TIMER_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  TWIS_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef TWIS_CONFIG_LOG_ENABLED
+#define TWIS_CONFIG_LOG_ENABLED 0
+#endif
+//  TWIS_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef TWIS_CONFIG_LOG_LEVEL
+#define TWIS_CONFIG_LOG_LEVEL 3
+#endif
+
+//  TWIS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef TWIS_CONFIG_INFO_COLOR
+#define TWIS_CONFIG_INFO_COLOR 0
+#endif
+
+//  TWIS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef TWIS_CONFIG_DEBUG_COLOR
+#define TWIS_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  TWI_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef TWI_CONFIG_LOG_ENABLED
+#define TWI_CONFIG_LOG_ENABLED 0
+#endif
+//  TWI_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef TWI_CONFIG_LOG_LEVEL
+#define TWI_CONFIG_LOG_LEVEL 3
+#endif
+
+//  TWI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef TWI_CONFIG_INFO_COLOR
+#define TWI_CONFIG_INFO_COLOR 0
+#endif
+
+//  TWI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef TWI_CONFIG_DEBUG_COLOR
+#define TWI_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  UART_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef UART_CONFIG_LOG_ENABLED
+#define UART_CONFIG_LOG_ENABLED 0
+#endif
+//  UART_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef UART_CONFIG_LOG_LEVEL
+#define UART_CONFIG_LOG_LEVEL 3
+#endif
+
+//  UART_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef UART_CONFIG_INFO_COLOR
+#define UART_CONFIG_INFO_COLOR 0
+#endif
+
+//  UART_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef UART_CONFIG_DEBUG_COLOR
+#define UART_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  USBD_CONFIG_LOG_ENABLED - Enable logging in the module
+//==========================================================
+#ifndef USBD_CONFIG_LOG_ENABLED
+#define USBD_CONFIG_LOG_ENABLED 0
+#endif
+//  USBD_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef USBD_CONFIG_LOG_LEVEL
+#define USBD_CONFIG_LOG_LEVEL 3
+#endif
+
+//  USBD_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef USBD_CONFIG_INFO_COLOR
+#define USBD_CONFIG_INFO_COLOR 0
+#endif
+
+//  USBD_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef USBD_CONFIG_DEBUG_COLOR
+#define USBD_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  WDT_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef WDT_CONFIG_LOG_ENABLED
+#define WDT_CONFIG_LOG_ENABLED 0
+#endif
+//  WDT_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef WDT_CONFIG_LOG_LEVEL
+#define WDT_CONFIG_LOG_LEVEL 3
+#endif
+
+//  WDT_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef WDT_CONFIG_INFO_COLOR
+#define WDT_CONFIG_INFO_COLOR 0
+#endif
+
+//  WDT_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef WDT_CONFIG_DEBUG_COLOR
+#define WDT_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+//==========================================================
+
+//  nrf_log in nRF_Libraries
+
+//==========================================================
+//  APP_BUTTON_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef APP_BUTTON_CONFIG_LOG_ENABLED
+#define APP_BUTTON_CONFIG_LOG_ENABLED 0
+#endif
+//  APP_BUTTON_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef APP_BUTTON_CONFIG_LOG_LEVEL
+#define APP_BUTTON_CONFIG_LOG_LEVEL 3
+#endif
+
+//  APP_BUTTON_CONFIG_INITIAL_LOG_LEVEL  - Initial severity level if dynamic filtering is enabled.
+
+
+//  If module generates a lot of logs, initial log level can
+//  be decreased to prevent flooding. Severity level can be
+//  increased on instance basis.
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef APP_BUTTON_CONFIG_INITIAL_LOG_LEVEL
+#define APP_BUTTON_CONFIG_INITIAL_LOG_LEVEL 3
+#endif
+
+//  APP_BUTTON_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef APP_BUTTON_CONFIG_INFO_COLOR
+#define APP_BUTTON_CONFIG_INFO_COLOR 0
+#endif
+
+//  APP_BUTTON_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef APP_BUTTON_CONFIG_DEBUG_COLOR
+#define APP_BUTTON_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  APP_TIMER_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef APP_TIMER_CONFIG_LOG_ENABLED
+#define APP_TIMER_CONFIG_LOG_ENABLED 0
+#endif
+//  APP_TIMER_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef APP_TIMER_CONFIG_LOG_LEVEL
+#define APP_TIMER_CONFIG_LOG_LEVEL 3
+#endif
+
+//  APP_TIMER_CONFIG_INITIAL_LOG_LEVEL  - Initial severity level if dynamic filtering is enabled.
+
+
+//  If module generates a lot of logs, initial log level can
+//  be decreased to prevent flooding. Severity level can be
+//  increased on instance basis.
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef APP_TIMER_CONFIG_INITIAL_LOG_LEVEL
+#define APP_TIMER_CONFIG_INITIAL_LOG_LEVEL 3
+#endif
+
+//  APP_TIMER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef APP_TIMER_CONFIG_INFO_COLOR
+#define APP_TIMER_CONFIG_INFO_COLOR 0
+#endif
+
+//  APP_TIMER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef APP_TIMER_CONFIG_DEBUG_COLOR
+#define APP_TIMER_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  APP_USBD_CDC_ACM_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef APP_USBD_CDC_ACM_CONFIG_LOG_ENABLED
+#define APP_USBD_CDC_ACM_CONFIG_LOG_ENABLED 0
+#endif
+//  APP_USBD_CDC_ACM_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef APP_USBD_CDC_ACM_CONFIG_LOG_LEVEL
+#define APP_USBD_CDC_ACM_CONFIG_LOG_LEVEL 3
+#endif
+
+//  APP_USBD_CDC_ACM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef APP_USBD_CDC_ACM_CONFIG_INFO_COLOR
+#define APP_USBD_CDC_ACM_CONFIG_INFO_COLOR 0
+#endif
+
+//  APP_USBD_CDC_ACM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef APP_USBD_CDC_ACM_CONFIG_DEBUG_COLOR
+#define APP_USBD_CDC_ACM_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  APP_USBD_CONFIG_LOG_ENABLED - Enable logging in the module.
+//==========================================================
+#ifndef APP_USBD_CONFIG_LOG_ENABLED
+#define APP_USBD_CONFIG_LOG_ENABLED 0
+#endif
+//  APP_USBD_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef APP_USBD_CONFIG_LOG_LEVEL
+#define APP_USBD_CONFIG_LOG_LEVEL 3
+#endif
+
+//  APP_USBD_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef APP_USBD_CONFIG_INFO_COLOR
+#define APP_USBD_CONFIG_INFO_COLOR 0
+#endif
+
+//  APP_USBD_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef APP_USBD_CONFIG_DEBUG_COLOR
+#define APP_USBD_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  APP_USBD_DUMMY_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef APP_USBD_DUMMY_CONFIG_LOG_ENABLED
+#define APP_USBD_DUMMY_CONFIG_LOG_ENABLED 0
+#endif
+//  APP_USBD_DUMMY_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef APP_USBD_DUMMY_CONFIG_LOG_LEVEL
+#define APP_USBD_DUMMY_CONFIG_LOG_LEVEL 3
+#endif
+
+//  APP_USBD_DUMMY_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef APP_USBD_DUMMY_CONFIG_INFO_COLOR
+#define APP_USBD_DUMMY_CONFIG_INFO_COLOR 0
+#endif
+
+//  APP_USBD_DUMMY_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef APP_USBD_DUMMY_CONFIG_DEBUG_COLOR
+#define APP_USBD_DUMMY_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  APP_USBD_MSC_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef APP_USBD_MSC_CONFIG_LOG_ENABLED
+#define APP_USBD_MSC_CONFIG_LOG_ENABLED 0
+#endif
+//  APP_USBD_MSC_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef APP_USBD_MSC_CONFIG_LOG_LEVEL
+#define APP_USBD_MSC_CONFIG_LOG_LEVEL 3
+#endif
+
+//  APP_USBD_MSC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef APP_USBD_MSC_CONFIG_INFO_COLOR
+#define APP_USBD_MSC_CONFIG_INFO_COLOR 0
+#endif
+
+//  APP_USBD_MSC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef APP_USBD_MSC_CONFIG_DEBUG_COLOR
+#define APP_USBD_MSC_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_ENABLED
+#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_ENABLED 0
+#endif
+//  APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_LEVEL
+#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_LEVEL 3
+#endif
+
+//  APP_USBD_NRF_DFU_TRIGGER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_INFO_COLOR
+#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_INFO_COLOR 0
+#endif
+
+//  APP_USBD_NRF_DFU_TRIGGER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_DEBUG_COLOR
+#define APP_USBD_NRF_DFU_TRIGGER_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_ATFIFO_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_ATFIFO_CONFIG_LOG_ENABLED
+#define NRF_ATFIFO_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_ATFIFO_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_ATFIFO_CONFIG_LOG_LEVEL
+#define NRF_ATFIFO_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_ATFIFO_CONFIG_LOG_INIT_FILTER_LEVEL  - Initial severity level if dynamic filtering is enabled
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_ATFIFO_CONFIG_LOG_INIT_FILTER_LEVEL
+#define NRF_ATFIFO_CONFIG_LOG_INIT_FILTER_LEVEL 3
+#endif
+
+//  NRF_ATFIFO_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_ATFIFO_CONFIG_INFO_COLOR
+#define NRF_ATFIFO_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_ATFIFO_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_ATFIFO_CONFIG_DEBUG_COLOR
+#define NRF_ATFIFO_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_BALLOC_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_BALLOC_CONFIG_LOG_ENABLED
+#define NRF_BALLOC_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_BALLOC_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_BALLOC_CONFIG_LOG_LEVEL
+#define NRF_BALLOC_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL  - Initial severity level if dynamic filtering is enabled.
+
+
+//  If module generates a lot of logs, initial log level can
+//  be decreased to prevent flooding. Severity level can be
+//  increased on instance basis.
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL
+#define NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL 3
+#endif
+
+//  NRF_BALLOC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_BALLOC_CONFIG_INFO_COLOR
+#define NRF_BALLOC_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_BALLOC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_BALLOC_CONFIG_DEBUG_COLOR
+#define NRF_BALLOC_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_ENABLED
+#define NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_LEVEL
+#define NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_INIT_FILTER_LEVEL  - Initial severity level if dynamic filtering is enabled
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_INIT_FILTER_LEVEL
+#define NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_INIT_FILTER_LEVEL 3
+#endif
+
+//  NRF_BLOCK_DEV_EMPTY_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_INFO_COLOR
+#define NRF_BLOCK_DEV_EMPTY_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_BLOCK_DEV_EMPTY_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_DEBUG_COLOR
+#define NRF_BLOCK_DEV_EMPTY_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_BLOCK_DEV_QSPI_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_BLOCK_DEV_QSPI_CONFIG_LOG_ENABLED
+#define NRF_BLOCK_DEV_QSPI_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_BLOCK_DEV_QSPI_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_BLOCK_DEV_QSPI_CONFIG_LOG_LEVEL
+#define NRF_BLOCK_DEV_QSPI_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_BLOCK_DEV_QSPI_CONFIG_LOG_INIT_FILTER_LEVEL  - Initial severity level if dynamic filtering is enabled
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_BLOCK_DEV_QSPI_CONFIG_LOG_INIT_FILTER_LEVEL
+#define NRF_BLOCK_DEV_QSPI_CONFIG_LOG_INIT_FILTER_LEVEL 3
+#endif
+
+//  NRF_BLOCK_DEV_QSPI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_BLOCK_DEV_QSPI_CONFIG_INFO_COLOR
+#define NRF_BLOCK_DEV_QSPI_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_BLOCK_DEV_QSPI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_BLOCK_DEV_QSPI_CONFIG_DEBUG_COLOR
+#define NRF_BLOCK_DEV_QSPI_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_BLOCK_DEV_RAM_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_BLOCK_DEV_RAM_CONFIG_LOG_ENABLED
+#define NRF_BLOCK_DEV_RAM_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_BLOCK_DEV_RAM_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_BLOCK_DEV_RAM_CONFIG_LOG_LEVEL
+#define NRF_BLOCK_DEV_RAM_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_BLOCK_DEV_RAM_CONFIG_LOG_INIT_FILTER_LEVEL  - Initial severity level if dynamic filtering is enabled
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_BLOCK_DEV_RAM_CONFIG_LOG_INIT_FILTER_LEVEL
+#define NRF_BLOCK_DEV_RAM_CONFIG_LOG_INIT_FILTER_LEVEL 3
+#endif
+
+//  NRF_BLOCK_DEV_RAM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_BLOCK_DEV_RAM_CONFIG_INFO_COLOR
+#define NRF_BLOCK_DEV_RAM_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_BLOCK_DEV_RAM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_BLOCK_DEV_RAM_CONFIG_DEBUG_COLOR
+#define NRF_BLOCK_DEV_RAM_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_CLI_BLE_UART_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_CLI_BLE_UART_CONFIG_LOG_ENABLED
+#define NRF_CLI_BLE_UART_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_CLI_BLE_UART_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_CLI_BLE_UART_CONFIG_LOG_LEVEL
+#define NRF_CLI_BLE_UART_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_CLI_BLE_UART_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_CLI_BLE_UART_CONFIG_INFO_COLOR
+#define NRF_CLI_BLE_UART_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_CLI_BLE_UART_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_CLI_BLE_UART_CONFIG_DEBUG_COLOR
+#define NRF_CLI_BLE_UART_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_CLI_LIBUARTE_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_CLI_LIBUARTE_CONFIG_LOG_ENABLED
+#define NRF_CLI_LIBUARTE_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_CLI_LIBUARTE_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_CLI_LIBUARTE_CONFIG_LOG_LEVEL
+#define NRF_CLI_LIBUARTE_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_CLI_LIBUARTE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_CLI_LIBUARTE_CONFIG_INFO_COLOR
+#define NRF_CLI_LIBUARTE_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_CLI_LIBUARTE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_CLI_LIBUARTE_CONFIG_DEBUG_COLOR
+#define NRF_CLI_LIBUARTE_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_CLI_UART_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_CLI_UART_CONFIG_LOG_ENABLED
+#define NRF_CLI_UART_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_CLI_UART_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_CLI_UART_CONFIG_LOG_LEVEL
+#define NRF_CLI_UART_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_CLI_UART_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_CLI_UART_CONFIG_INFO_COLOR
+#define NRF_CLI_UART_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_CLI_UART_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_CLI_UART_CONFIG_DEBUG_COLOR
+#define NRF_CLI_UART_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_LIBUARTE_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_LIBUARTE_CONFIG_LOG_ENABLED
+#define NRF_LIBUARTE_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_LIBUARTE_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_LIBUARTE_CONFIG_LOG_LEVEL
+#define NRF_LIBUARTE_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_LIBUARTE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_LIBUARTE_CONFIG_INFO_COLOR
+#define NRF_LIBUARTE_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_LIBUARTE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_LIBUARTE_CONFIG_DEBUG_COLOR
+#define NRF_LIBUARTE_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_MEMOBJ_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_MEMOBJ_CONFIG_LOG_ENABLED
+#define NRF_MEMOBJ_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_MEMOBJ_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_MEMOBJ_CONFIG_LOG_LEVEL
+#define NRF_MEMOBJ_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_MEMOBJ_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_MEMOBJ_CONFIG_INFO_COLOR
+#define NRF_MEMOBJ_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_MEMOBJ_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_MEMOBJ_CONFIG_DEBUG_COLOR
+#define NRF_MEMOBJ_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_PWR_MGMT_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_PWR_MGMT_CONFIG_LOG_ENABLED
+#define NRF_PWR_MGMT_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_PWR_MGMT_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_PWR_MGMT_CONFIG_LOG_LEVEL
+#define NRF_PWR_MGMT_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_PWR_MGMT_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_PWR_MGMT_CONFIG_INFO_COLOR
+#define NRF_PWR_MGMT_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_PWR_MGMT_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_PWR_MGMT_CONFIG_DEBUG_COLOR
+#define NRF_PWR_MGMT_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_QUEUE_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_QUEUE_CONFIG_LOG_ENABLED
+#define NRF_QUEUE_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_QUEUE_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_QUEUE_CONFIG_LOG_LEVEL
+#define NRF_QUEUE_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_QUEUE_CONFIG_LOG_INIT_FILTER_LEVEL  - Initial severity level if dynamic filtering is enabled
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_QUEUE_CONFIG_LOG_INIT_FILTER_LEVEL
+#define NRF_QUEUE_CONFIG_LOG_INIT_FILTER_LEVEL 3
+#endif
+
+//  NRF_QUEUE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_QUEUE_CONFIG_INFO_COLOR
+#define NRF_QUEUE_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_QUEUE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_QUEUE_CONFIG_DEBUG_COLOR
+#define NRF_QUEUE_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_SDH_ANT_LOG_ENABLED - Enable logging in SoftDevice handler (ANT) module.
+//==========================================================
+#ifndef NRF_SDH_ANT_LOG_ENABLED
+#define NRF_SDH_ANT_LOG_ENABLED 0
+#endif
+//  NRF_SDH_ANT_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_SDH_ANT_LOG_LEVEL
+#define NRF_SDH_ANT_LOG_LEVEL 3
+#endif
+
+//  NRF_SDH_ANT_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_SDH_ANT_INFO_COLOR
+#define NRF_SDH_ANT_INFO_COLOR 0
+#endif
+
+//  NRF_SDH_ANT_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_SDH_ANT_DEBUG_COLOR
+#define NRF_SDH_ANT_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_SDH_BLE_LOG_ENABLED - Enable logging in SoftDevice handler (BLE) module.
+//==========================================================
+#ifndef NRF_SDH_BLE_LOG_ENABLED
+#define NRF_SDH_BLE_LOG_ENABLED 1
+#endif
+//  NRF_SDH_BLE_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_SDH_BLE_LOG_LEVEL
+#define NRF_SDH_BLE_LOG_LEVEL 3
+#endif
+
+//  NRF_SDH_BLE_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_SDH_BLE_INFO_COLOR
+#define NRF_SDH_BLE_INFO_COLOR 0
+#endif
+
+//  NRF_SDH_BLE_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_SDH_BLE_DEBUG_COLOR
+#define NRF_SDH_BLE_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_SDH_LOG_ENABLED - Enable logging in SoftDevice handler module.
+//==========================================================
+#ifndef NRF_SDH_LOG_ENABLED
+#define NRF_SDH_LOG_ENABLED 1
+#endif
+//  NRF_SDH_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_SDH_LOG_LEVEL
+#define NRF_SDH_LOG_LEVEL 3
+#endif
+
+//  NRF_SDH_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_SDH_INFO_COLOR
+#define NRF_SDH_INFO_COLOR 0
+#endif
+
+//  NRF_SDH_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_SDH_DEBUG_COLOR
+#define NRF_SDH_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_SDH_SOC_LOG_ENABLED - Enable logging in SoftDevice handler (SoC) module.
+//==========================================================
+#ifndef NRF_SDH_SOC_LOG_ENABLED
+#define NRF_SDH_SOC_LOG_ENABLED 1
+#endif
+//  NRF_SDH_SOC_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_SDH_SOC_LOG_LEVEL
+#define NRF_SDH_SOC_LOG_LEVEL 3
+#endif
+
+//  NRF_SDH_SOC_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_SDH_SOC_INFO_COLOR
+#define NRF_SDH_SOC_INFO_COLOR 0
+#endif
+
+//  NRF_SDH_SOC_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_SDH_SOC_DEBUG_COLOR
+#define NRF_SDH_SOC_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_SORTLIST_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_SORTLIST_CONFIG_LOG_ENABLED
+#define NRF_SORTLIST_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_SORTLIST_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_SORTLIST_CONFIG_LOG_LEVEL
+#define NRF_SORTLIST_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_SORTLIST_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_SORTLIST_CONFIG_INFO_COLOR
+#define NRF_SORTLIST_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_SORTLIST_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_SORTLIST_CONFIG_DEBUG_COLOR
+#define NRF_SORTLIST_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NRF_TWI_SENSOR_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NRF_TWI_SENSOR_CONFIG_LOG_ENABLED
+#define NRF_TWI_SENSOR_CONFIG_LOG_ENABLED 0
+#endif
+//  NRF_TWI_SENSOR_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NRF_TWI_SENSOR_CONFIG_LOG_LEVEL
+#define NRF_TWI_SENSOR_CONFIG_LOG_LEVEL 3
+#endif
+
+//  NRF_TWI_SENSOR_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_TWI_SENSOR_CONFIG_INFO_COLOR
+#define NRF_TWI_SENSOR_CONFIG_INFO_COLOR 0
+#endif
+
+//  NRF_TWI_SENSOR_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NRF_TWI_SENSOR_CONFIG_DEBUG_COLOR
+#define NRF_TWI_SENSOR_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  PM_LOG_ENABLED - Enable logging in Peer Manager and its submodules.
+//==========================================================
+#ifndef PM_LOG_ENABLED
+#define PM_LOG_ENABLED 1
+#endif
+//  PM_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef PM_LOG_LEVEL
+#define PM_LOG_LEVEL 3
+#endif
+
+//  PM_LOG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef PM_LOG_INFO_COLOR
+#define PM_LOG_INFO_COLOR 0
+#endif
+
+//  PM_LOG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef PM_LOG_DEBUG_COLOR
+#define PM_LOG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+//==========================================================
+
+//  nrf_log in nRF_Serialization
+
+//==========================================================
+//  SER_HAL_TRANSPORT_CONFIG_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef SER_HAL_TRANSPORT_CONFIG_LOG_ENABLED
+#define SER_HAL_TRANSPORT_CONFIG_LOG_ENABLED 0
+#endif
+//  SER_HAL_TRANSPORT_CONFIG_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef SER_HAL_TRANSPORT_CONFIG_LOG_LEVEL
+#define SER_HAL_TRANSPORT_CONFIG_LOG_LEVEL 3
+#endif
+
+//  SER_HAL_TRANSPORT_CONFIG_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef SER_HAL_TRANSPORT_CONFIG_INFO_COLOR
+#define SER_HAL_TRANSPORT_CONFIG_INFO_COLOR 0
+#endif
+
+//  SER_HAL_TRANSPORT_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef SER_HAL_TRANSPORT_CONFIG_DEBUG_COLOR
+#define SER_HAL_TRANSPORT_CONFIG_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+//==========================================================
+
+// 
+//==========================================================
+
+// 
+
+//  NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED  - nrf_log_str_formatter - Log string formatter
+
+
+#ifndef NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED
+#define NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED 1
+#endif
+
+// 
+//==========================================================
+
+//  nRF_NFC
+
+//==========================================================
+//  NFC_AC_REC_ENABLED  - nfc_ac_rec - NFC NDEF Alternative Carrier record encoder
+
+
+#ifndef NFC_AC_REC_ENABLED
+#define NFC_AC_REC_ENABLED 0
+#endif
+
+//  NFC_AC_REC_PARSER_ENABLED  - nfc_ac_rec_parser - Alternative Carrier record parser
+
+
+#ifndef NFC_AC_REC_PARSER_ENABLED
+#define NFC_AC_REC_PARSER_ENABLED 0
+#endif
+
+//  NFC_BLE_OOB_ADVDATA_ENABLED - nfc_ble_oob_advdata - AD data for OOB pairing encoder
+//==========================================================
+#ifndef NFC_BLE_OOB_ADVDATA_ENABLED
+#define NFC_BLE_OOB_ADVDATA_ENABLED 0
+#endif
+//  ADVANCED_ADVDATA_SUPPORT  - Non-mandatory AD types for BLE OOB pairing are encoded inside the NDEF message (e.g. service UUIDs)
+
+// <1=> Enabled
+// <0=> Disabled
+
+#ifndef ADVANCED_ADVDATA_SUPPORT
+#define ADVANCED_ADVDATA_SUPPORT 0
+#endif
+
+// 
+
+//  NFC_BLE_OOB_ADVDATA_PARSER_ENABLED  - nfc_ble_oob_advdata_parser - BLE OOB pairing AD data parser
+
+
+#ifndef NFC_BLE_OOB_ADVDATA_PARSER_ENABLED
+#define NFC_BLE_OOB_ADVDATA_PARSER_ENABLED 0
+#endif
+
+//  NFC_BLE_PAIR_LIB_ENABLED - nfc_ble_pair_lib - Library parameters
+//==========================================================
+#ifndef NFC_BLE_PAIR_LIB_ENABLED
+#define NFC_BLE_PAIR_LIB_ENABLED 0
+#endif
+//  NFC_BLE_PAIR_LIB_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NFC_BLE_PAIR_LIB_LOG_ENABLED
+#define NFC_BLE_PAIR_LIB_LOG_ENABLED 0
+#endif
+//  NFC_BLE_PAIR_LIB_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NFC_BLE_PAIR_LIB_LOG_LEVEL
+#define NFC_BLE_PAIR_LIB_LOG_LEVEL 3
+#endif
+
+//  NFC_BLE_PAIR_LIB_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NFC_BLE_PAIR_LIB_INFO_COLOR
+#define NFC_BLE_PAIR_LIB_INFO_COLOR 0
+#endif
+
+//  NFC_BLE_PAIR_LIB_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NFC_BLE_PAIR_LIB_DEBUG_COLOR
+#define NFC_BLE_PAIR_LIB_DEBUG_COLOR 0
+#endif
+
+// 
+
+//  NFC_BLE_PAIR_LIB_SECURITY_PARAMETERS - Common Peer Manager security parameters.
+
+//==========================================================
+//  BLE_NFC_SEC_PARAM_BOND - Enables device bonding.
+
+//  If bonding is enabled at least one of the BLE_NFC_SEC_PARAM_KDIST options must be enabled.
+//==========================================================
+#ifndef BLE_NFC_SEC_PARAM_BOND
+#define BLE_NFC_SEC_PARAM_BOND 1
+#endif
+//  BLE_NFC_SEC_PARAM_KDIST_OWN_ENC  - Enables Long Term Key and Master Identification distribution by device.
+
+
+#ifndef BLE_NFC_SEC_PARAM_KDIST_OWN_ENC
+#define BLE_NFC_SEC_PARAM_KDIST_OWN_ENC 1
+#endif
+
+//  BLE_NFC_SEC_PARAM_KDIST_OWN_ID  - Enables Identity Resolving Key and Identity Address Information distribution by device.
+
+
+#ifndef BLE_NFC_SEC_PARAM_KDIST_OWN_ID
+#define BLE_NFC_SEC_PARAM_KDIST_OWN_ID 1
+#endif
+
+//  BLE_NFC_SEC_PARAM_KDIST_PEER_ENC  - Enables Long Term Key and Master Identification distribution by peer.
+
+
+#ifndef BLE_NFC_SEC_PARAM_KDIST_PEER_ENC
+#define BLE_NFC_SEC_PARAM_KDIST_PEER_ENC 1
+#endif
+
+//  BLE_NFC_SEC_PARAM_KDIST_PEER_ID  - Enables Identity Resolving Key and Identity Address Information distribution by peer.
+
+
+#ifndef BLE_NFC_SEC_PARAM_KDIST_PEER_ID
+#define BLE_NFC_SEC_PARAM_KDIST_PEER_ID 1
+#endif
+
+// 
+
+//  BLE_NFC_SEC_PARAM_MIN_KEY_SIZE  - Minimal size of a security key.
+
+// <7=> 7
+// <8=> 8
+// <9=> 9
+// <10=> 10
+// <11=> 11
+// <12=> 12
+// <13=> 13
+// <14=> 14
+// <15=> 15
+// <16=> 16
+
+#ifndef BLE_NFC_SEC_PARAM_MIN_KEY_SIZE
+#define BLE_NFC_SEC_PARAM_MIN_KEY_SIZE 7
+#endif
+
+//  BLE_NFC_SEC_PARAM_MAX_KEY_SIZE  - Maximal size of a security key.
+
+// <7=> 7
+// <8=> 8
+// <9=> 9
+// <10=> 10
+// <11=> 11
+// <12=> 12
+// <13=> 13
+// <14=> 14
+// <15=> 15
+// <16=> 16
+
+#ifndef BLE_NFC_SEC_PARAM_MAX_KEY_SIZE
+#define BLE_NFC_SEC_PARAM_MAX_KEY_SIZE 16
+#endif
+
+// 
+//==========================================================
+
+// 
+
+//  NFC_BLE_PAIR_MSG_ENABLED  - nfc_ble_pair_msg - NDEF message for OOB pairing encoder
+
+
+#ifndef NFC_BLE_PAIR_MSG_ENABLED
+#define NFC_BLE_PAIR_MSG_ENABLED 0
+#endif
+
+//  NFC_CH_COMMON_ENABLED  - nfc_ble_pair_common - OOB pairing common data
+
+
+#ifndef NFC_CH_COMMON_ENABLED
+#define NFC_CH_COMMON_ENABLED 0
+#endif
+
+//  NFC_EP_OOB_REC_ENABLED  - nfc_ep_oob_rec - EP record for BLE pairing encoder
+
+
+#ifndef NFC_EP_OOB_REC_ENABLED
+#define NFC_EP_OOB_REC_ENABLED 0
+#endif
+
+//  NFC_HS_REC_ENABLED  - nfc_hs_rec - Handover Select NDEF record encoder
+
+
+#ifndef NFC_HS_REC_ENABLED
+#define NFC_HS_REC_ENABLED 0
+#endif
+
+//  NFC_LE_OOB_REC_ENABLED  - nfc_le_oob_rec - LE record for BLE pairing encoder
+
+
+#ifndef NFC_LE_OOB_REC_ENABLED
+#define NFC_LE_OOB_REC_ENABLED 0
+#endif
+
+//  NFC_LE_OOB_REC_PARSER_ENABLED  - nfc_le_oob_rec_parser - LE record parser
+
+
+#ifndef NFC_LE_OOB_REC_PARSER_ENABLED
+#define NFC_LE_OOB_REC_PARSER_ENABLED 0
+#endif
+
+//  NFC_NDEF_LAUNCHAPP_MSG_ENABLED  - nfc_launchapp_msg - Encoding data for NDEF Application Launching message for NFC Tag
+
+
+#ifndef NFC_NDEF_LAUNCHAPP_MSG_ENABLED
+#define NFC_NDEF_LAUNCHAPP_MSG_ENABLED 0
+#endif
+
+//  NFC_NDEF_LAUNCHAPP_REC_ENABLED  - nfc_launchapp_rec - Encoding data for NDEF Application Launching record for NFC Tag
+
+
+#ifndef NFC_NDEF_LAUNCHAPP_REC_ENABLED
+#define NFC_NDEF_LAUNCHAPP_REC_ENABLED 0
+#endif
+
+//  NFC_NDEF_MSG_ENABLED - nfc_ndef_msg - NFC NDEF Message generator module
+//==========================================================
+#ifndef NFC_NDEF_MSG_ENABLED
+#define NFC_NDEF_MSG_ENABLED 0
+#endif
+//  NFC_NDEF_MSG_TAG_TYPE  - NFC Tag Type
+
+// <2=> Type 2 Tag
+// <4=> Type 4 Tag
+
+#ifndef NFC_NDEF_MSG_TAG_TYPE
+#define NFC_NDEF_MSG_TAG_TYPE 2
+#endif
+
+// 
+
+//  NFC_NDEF_MSG_PARSER_ENABLED - nfc_ndef_msg_parser - NFC NDEF message parser module
+//==========================================================
+#ifndef NFC_NDEF_MSG_PARSER_ENABLED
+#define NFC_NDEF_MSG_PARSER_ENABLED 0
+#endif
+//  NFC_NDEF_MSG_PARSER_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NFC_NDEF_MSG_PARSER_LOG_ENABLED
+#define NFC_NDEF_MSG_PARSER_LOG_ENABLED 0
+#endif
+//  NFC_NDEF_MSG_PARSER_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NFC_NDEF_MSG_PARSER_LOG_LEVEL
+#define NFC_NDEF_MSG_PARSER_LOG_LEVEL 3
+#endif
+
+//  NFC_NDEF_MSG_PARSER_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NFC_NDEF_MSG_PARSER_INFO_COLOR
+#define NFC_NDEF_MSG_PARSER_INFO_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NFC_NDEF_RECORD_ENABLED  - nfc_ndef_record - NFC NDEF Record generator module
+
+
+#ifndef NFC_NDEF_RECORD_ENABLED
+#define NFC_NDEF_RECORD_ENABLED 0
+#endif
+
+//  NFC_NDEF_RECORD_PARSER_ENABLED - nfc_ndef_record_parser - NFC NDEF Record parser module
+//==========================================================
+#ifndef NFC_NDEF_RECORD_PARSER_ENABLED
+#define NFC_NDEF_RECORD_PARSER_ENABLED 0
+#endif
+//  NFC_NDEF_RECORD_PARSER_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NFC_NDEF_RECORD_PARSER_LOG_ENABLED
+#define NFC_NDEF_RECORD_PARSER_LOG_ENABLED 0
+#endif
+//  NFC_NDEF_RECORD_PARSER_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NFC_NDEF_RECORD_PARSER_LOG_LEVEL
+#define NFC_NDEF_RECORD_PARSER_LOG_LEVEL 3
+#endif
+
+//  NFC_NDEF_RECORD_PARSER_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NFC_NDEF_RECORD_PARSER_INFO_COLOR
+#define NFC_NDEF_RECORD_PARSER_INFO_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NFC_NDEF_TEXT_RECORD_ENABLED  - nfc_text_rec - Encoding data for a text record for NFC Tag
+
+
+#ifndef NFC_NDEF_TEXT_RECORD_ENABLED
+#define NFC_NDEF_TEXT_RECORD_ENABLED 0
+#endif
+
+//  NFC_NDEF_URI_MSG_ENABLED  - nfc_uri_msg - Encoding data for NDEF message with URI record for NFC Tag
+
+
+#ifndef NFC_NDEF_URI_MSG_ENABLED
+#define NFC_NDEF_URI_MSG_ENABLED 0
+#endif
+
+//  NFC_NDEF_URI_REC_ENABLED  - nfc_uri_rec - Encoding data for a URI record for NFC Tag
+
+
+#ifndef NFC_NDEF_URI_REC_ENABLED
+#define NFC_NDEF_URI_REC_ENABLED 0
+#endif
+
+//  NFC_PLATFORM_ENABLED - nfc_platform - NFC platform module for Clock control.
+//==========================================================
+#ifndef NFC_PLATFORM_ENABLED
+#define NFC_PLATFORM_ENABLED 0
+#endif
+//  NFC_PLATFORM_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NFC_PLATFORM_LOG_ENABLED
+#define NFC_PLATFORM_LOG_ENABLED 0
+#endif
+//  NFC_PLATFORM_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NFC_PLATFORM_LOG_LEVEL
+#define NFC_PLATFORM_LOG_LEVEL 3
+#endif
+
+//  NFC_PLATFORM_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NFC_PLATFORM_INFO_COLOR
+#define NFC_PLATFORM_INFO_COLOR 0
+#endif
+
+//  NFC_PLATFORM_DEBUG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NFC_PLATFORM_DEBUG_COLOR
+#define NFC_PLATFORM_DEBUG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NFC_T2T_PARSER_ENABLED - nfc_type_2_tag_parser - Parser for decoding Type 2 Tag data
+//==========================================================
+#ifndef NFC_T2T_PARSER_ENABLED
+#define NFC_T2T_PARSER_ENABLED 0
+#endif
+//  NFC_T2T_PARSER_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NFC_T2T_PARSER_LOG_ENABLED
+#define NFC_T2T_PARSER_LOG_ENABLED 0
+#endif
+//  NFC_T2T_PARSER_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NFC_T2T_PARSER_LOG_LEVEL
+#define NFC_T2T_PARSER_LOG_LEVEL 3
+#endif
+
+//  NFC_T2T_PARSER_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NFC_T2T_PARSER_INFO_COLOR
+#define NFC_T2T_PARSER_INFO_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NFC_T4T_APDU_ENABLED - nfc_t4t_apdu - APDU encoder/decoder for Type 4 Tag
+//==========================================================
+#ifndef NFC_T4T_APDU_ENABLED
+#define NFC_T4T_APDU_ENABLED 0
+#endif
+//  NFC_T4T_APDU_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NFC_T4T_APDU_LOG_ENABLED
+#define NFC_T4T_APDU_LOG_ENABLED 0
+#endif
+//  NFC_T4T_APDU_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NFC_T4T_APDU_LOG_LEVEL
+#define NFC_T4T_APDU_LOG_LEVEL 3
+#endif
+
+//  NFC_T4T_APDU_LOG_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NFC_T4T_APDU_LOG_COLOR
+#define NFC_T4T_APDU_LOG_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NFC_T4T_CC_FILE_PARSER_ENABLED - nfc_t4t_cc_file - Capability Container file for Type 4 Tag
+//==========================================================
+#ifndef NFC_T4T_CC_FILE_PARSER_ENABLED
+#define NFC_T4T_CC_FILE_PARSER_ENABLED 0
+#endif
+//  NFC_T4T_CC_FILE_PARSER_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NFC_T4T_CC_FILE_PARSER_LOG_ENABLED
+#define NFC_T4T_CC_FILE_PARSER_LOG_ENABLED 0
+#endif
+//  NFC_T4T_CC_FILE_PARSER_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NFC_T4T_CC_FILE_PARSER_LOG_LEVEL
+#define NFC_T4T_CC_FILE_PARSER_LOG_LEVEL 3
+#endif
+
+//  NFC_T4T_CC_FILE_PARSER_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NFC_T4T_CC_FILE_PARSER_INFO_COLOR
+#define NFC_T4T_CC_FILE_PARSER_INFO_COLOR 0
+#endif
+
+// 
+
+// 
+
+//  NFC_T4T_HL_DETECTION_PROCEDURES_ENABLED - nfc_t4t_hl_detection_procedures - NDEF Detection Procedure for Type 4 Tag
+//==========================================================
+#ifndef NFC_T4T_HL_DETECTION_PROCEDURES_ENABLED
+#define NFC_T4T_HL_DETECTION_PROCEDURES_ENABLED 0
+#endif
+//  NFC_T4T_HL_DETECTION_PROCEDURES_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NFC_T4T_HL_DETECTION_PROCEDURES_LOG_ENABLED
+#define NFC_T4T_HL_DETECTION_PROCEDURES_LOG_ENABLED 0
+#endif
+//  NFC_T4T_HL_DETECTION_PROCEDURES_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NFC_T4T_HL_DETECTION_PROCEDURES_LOG_LEVEL
+#define NFC_T4T_HL_DETECTION_PROCEDURES_LOG_LEVEL 3
+#endif
+
+//  NFC_T4T_HL_DETECTION_PROCEDURES_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NFC_T4T_HL_DETECTION_PROCEDURES_INFO_COLOR
+#define NFC_T4T_HL_DETECTION_PROCEDURES_INFO_COLOR 0
+#endif
+
+// 
+
+//  APDU_BUFF_SIZE - Size (in bytes) of the buffer for APDU storage
+#ifndef APDU_BUFF_SIZE
+#define APDU_BUFF_SIZE 250
+#endif
+
+//  CC_STORAGE_BUFF_SIZE - Size (in bytes) of the buffer for CC file storage
+#ifndef CC_STORAGE_BUFF_SIZE
+#define CC_STORAGE_BUFF_SIZE 64
+#endif
+
+// 
+
+//  NFC_T4T_TLV_BLOCK_PARSER_ENABLED - nfc_t4t_tlv_block - TLV block for Type 4 Tag
+//==========================================================
+#ifndef NFC_T4T_TLV_BLOCK_PARSER_ENABLED
+#define NFC_T4T_TLV_BLOCK_PARSER_ENABLED 0
+#endif
+//  NFC_T4T_TLV_BLOCK_PARSER_LOG_ENABLED - Enables logging in the module.
+//==========================================================
+#ifndef NFC_T4T_TLV_BLOCK_PARSER_LOG_ENABLED
+#define NFC_T4T_TLV_BLOCK_PARSER_LOG_ENABLED 0
+#endif
+//  NFC_T4T_TLV_BLOCK_PARSER_LOG_LEVEL  - Default Severity level
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
+
+#ifndef NFC_T4T_TLV_BLOCK_PARSER_LOG_LEVEL
+#define NFC_T4T_TLV_BLOCK_PARSER_LOG_LEVEL 3
+#endif
+
+//  NFC_T4T_TLV_BLOCK_PARSER_INFO_COLOR  - ANSI escape code prefix.
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
+
+#ifndef NFC_T4T_TLV_BLOCK_PARSER_INFO_COLOR
+#define NFC_T4T_TLV_BLOCK_PARSER_INFO_COLOR 0
+#endif
+
+// 
+
+// 
+
+// 
+//==========================================================
+
+//  nRF_SoftDevice
+
+//==========================================================
+//  NRF_SDH_BLE_ENABLED - nrf_sdh_ble - SoftDevice BLE event handler
+//==========================================================
+#ifndef NRF_SDH_BLE_ENABLED
+#define NRF_SDH_BLE_ENABLED 0
+#endif
+//  BLE Stack configuration - Stack configuration parameters
+
+//  The SoftDevice handler will configure the stack with these parameters when calling @ref nrf_sdh_ble_default_cfg_set.
+//  Other libraries might depend on these values; keep them up-to-date even if you are not explicitely calling @ref nrf_sdh_ble_default_cfg_set.
+//==========================================================
+//  NRF_SDH_BLE_GAP_DATA_LENGTH   <27-251>
+
+
+//  Requested BLE GAP data length to be negotiated.
+
+#ifndef NRF_SDH_BLE_GAP_DATA_LENGTH
+#define NRF_SDH_BLE_GAP_DATA_LENGTH 27
+#endif
+
+//  NRF_SDH_BLE_PERIPHERAL_LINK_COUNT - Maximum number of peripheral links.
+#ifndef NRF_SDH_BLE_PERIPHERAL_LINK_COUNT
+#define NRF_SDH_BLE_PERIPHERAL_LINK_COUNT 0
+#endif
+
+//  NRF_SDH_BLE_CENTRAL_LINK_COUNT - Maximum number of central links.
+#ifndef NRF_SDH_BLE_CENTRAL_LINK_COUNT
+#define NRF_SDH_BLE_CENTRAL_LINK_COUNT 0
+#endif
+
+//  NRF_SDH_BLE_TOTAL_LINK_COUNT - Total link count.
+//  Maximum number of total concurrent connections using the default configuration.
+
+#ifndef NRF_SDH_BLE_TOTAL_LINK_COUNT
+#define NRF_SDH_BLE_TOTAL_LINK_COUNT 1
+#endif
+
+//  NRF_SDH_BLE_GAP_EVENT_LENGTH - GAP event length.
+//  The time set aside for this connection on every connection interval in 1.25 ms units.
+
+#ifndef NRF_SDH_BLE_GAP_EVENT_LENGTH
+#define NRF_SDH_BLE_GAP_EVENT_LENGTH 6
+#endif
+
+//  NRF_SDH_BLE_GATT_MAX_MTU_SIZE - Static maximum MTU size.
+#ifndef NRF_SDH_BLE_GATT_MAX_MTU_SIZE
+#define NRF_SDH_BLE_GATT_MAX_MTU_SIZE 23
+#endif
+
+//  NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE - Attribute Table size in bytes. The size must be a multiple of 4.
+#ifndef NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE
+#define NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE 1408
+#endif
+
+//  NRF_SDH_BLE_VS_UUID_COUNT - The number of vendor-specific UUIDs.
+#ifndef NRF_SDH_BLE_VS_UUID_COUNT
+#define NRF_SDH_BLE_VS_UUID_COUNT 0
+#endif
+
+//  NRF_SDH_BLE_SERVICE_CHANGED  - Include the Service Changed characteristic in the Attribute Table.
+
+
+#ifndef NRF_SDH_BLE_SERVICE_CHANGED
+#define NRF_SDH_BLE_SERVICE_CHANGED 0
+#endif
+
+// 
+//==========================================================
+
+//  BLE Observers - Observers and priority levels
+
+//==========================================================
+//  NRF_SDH_BLE_OBSERVER_PRIO_LEVELS - Total number of priority levels for BLE observers.
+//  This setting configures the number of priority levels available for BLE event handlers.
+//  The priority level of a handler determines the order in which it receives events, with respect to other handlers.
+
+#ifndef NRF_SDH_BLE_OBSERVER_PRIO_LEVELS
+#define NRF_SDH_BLE_OBSERVER_PRIO_LEVELS 4
+#endif
+
+//  BLE Observers priorities - Invididual priorities
+
+//==========================================================
+//  BLE_ADV_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Advertising module.
+
+#ifndef BLE_ADV_BLE_OBSERVER_PRIO
+#define BLE_ADV_BLE_OBSERVER_PRIO 1
+#endif
+
+//  BLE_ANCS_C_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Apple Notification Service Client.
+
+#ifndef BLE_ANCS_C_BLE_OBSERVER_PRIO
+#define BLE_ANCS_C_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_ANS_C_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Alert Notification Service Client.
+
+#ifndef BLE_ANS_C_BLE_OBSERVER_PRIO
+#define BLE_ANS_C_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_BAS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Battery Service.
+
+#ifndef BLE_BAS_BLE_OBSERVER_PRIO
+#define BLE_BAS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_BAS_C_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Battery Service Client.
+
+#ifndef BLE_BAS_C_BLE_OBSERVER_PRIO
+#define BLE_BAS_C_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_BPS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Blood Pressure Service.
+
+#ifndef BLE_BPS_BLE_OBSERVER_PRIO
+#define BLE_BPS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_CONN_PARAMS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Connection parameters module.
+
+#ifndef BLE_CONN_PARAMS_BLE_OBSERVER_PRIO
+#define BLE_CONN_PARAMS_BLE_OBSERVER_PRIO 1
+#endif
+
+//  BLE_CONN_STATE_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Connection State module.
+
+#ifndef BLE_CONN_STATE_BLE_OBSERVER_PRIO
+#define BLE_CONN_STATE_BLE_OBSERVER_PRIO 0
+#endif
+
+//  BLE_CSCS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Cycling Speed and Cadence Service.
+
+#ifndef BLE_CSCS_BLE_OBSERVER_PRIO
+#define BLE_CSCS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_CTS_C_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Current Time Service Client.
+
+#ifndef BLE_CTS_C_BLE_OBSERVER_PRIO
+#define BLE_CTS_C_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_DB_DISC_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Database Discovery module.
+
+#ifndef BLE_DB_DISC_BLE_OBSERVER_PRIO
+#define BLE_DB_DISC_BLE_OBSERVER_PRIO 1
+#endif
+
+//  BLE_DFU_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the DFU Service.
+
+#ifndef BLE_DFU_BLE_OBSERVER_PRIO
+#define BLE_DFU_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_DIS_C_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Device Information Client.
+
+#ifndef BLE_DIS_C_BLE_OBSERVER_PRIO
+#define BLE_DIS_C_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_GLS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Glucose Service.
+
+#ifndef BLE_GLS_BLE_OBSERVER_PRIO
+#define BLE_GLS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_HIDS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Human Interface Device Service.
+
+#ifndef BLE_HIDS_BLE_OBSERVER_PRIO
+#define BLE_HIDS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_HRS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Heart Rate Service.
+
+#ifndef BLE_HRS_BLE_OBSERVER_PRIO
+#define BLE_HRS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_HRS_C_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Heart Rate Service Client.
+
+#ifndef BLE_HRS_C_BLE_OBSERVER_PRIO
+#define BLE_HRS_C_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_HTS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Health Thermometer Service.
+
+#ifndef BLE_HTS_BLE_OBSERVER_PRIO
+#define BLE_HTS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_IAS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Immediate Alert Service.
+
+#ifndef BLE_IAS_BLE_OBSERVER_PRIO
+#define BLE_IAS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_IAS_C_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Immediate Alert Service Client.
+
+#ifndef BLE_IAS_C_BLE_OBSERVER_PRIO
+#define BLE_IAS_C_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_LBS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the LED Button Service.
+
+#ifndef BLE_LBS_BLE_OBSERVER_PRIO
+#define BLE_LBS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_LBS_C_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the LED Button Service Client.
+
+#ifndef BLE_LBS_C_BLE_OBSERVER_PRIO
+#define BLE_LBS_C_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_LLS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Link Loss Service.
+
+#ifndef BLE_LLS_BLE_OBSERVER_PRIO
+#define BLE_LLS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_LNS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Location Navigation Service.
+
+#ifndef BLE_LNS_BLE_OBSERVER_PRIO
+#define BLE_LNS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_NUS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the UART Service.
+
+#ifndef BLE_NUS_BLE_OBSERVER_PRIO
+#define BLE_NUS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_NUS_C_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the UART Central Service.
+
+#ifndef BLE_NUS_C_BLE_OBSERVER_PRIO
+#define BLE_NUS_C_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_OTS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Object transfer service.
+
+#ifndef BLE_OTS_BLE_OBSERVER_PRIO
+#define BLE_OTS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_OTS_C_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Object transfer service client.
+
+#ifndef BLE_OTS_C_BLE_OBSERVER_PRIO
+#define BLE_OTS_C_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_RSCS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Running Speed and Cadence Service.
+
+#ifndef BLE_RSCS_BLE_OBSERVER_PRIO
+#define BLE_RSCS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_RSCS_C_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Running Speed and Cadence Client.
+
+#ifndef BLE_RSCS_C_BLE_OBSERVER_PRIO
+#define BLE_RSCS_C_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BLE_TPS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the TX Power Service.
+
+#ifndef BLE_TPS_BLE_OBSERVER_PRIO
+#define BLE_TPS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  BSP_BTN_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Button Control module.
+
+#ifndef BSP_BTN_BLE_OBSERVER_PRIO
+#define BSP_BTN_BLE_OBSERVER_PRIO 1
+#endif
+
+//  NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the NFC pairing library.
+
+#ifndef NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO
+#define NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO 1
+#endif
+
+//  NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the NFC pairing library.
+
+#ifndef NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO
+#define NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO 1
+#endif
+
+//  NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the NFC pairing library.
+
+#ifndef NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO
+#define NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO 1
+#endif
+
+//  NRF_BLE_BMS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Bond Management Service.
+
+#ifndef NRF_BLE_BMS_BLE_OBSERVER_PRIO
+#define NRF_BLE_BMS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  NRF_BLE_CGMS_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Contiuon Glucose Monitoring Service.
+
+#ifndef NRF_BLE_CGMS_BLE_OBSERVER_PRIO
+#define NRF_BLE_CGMS_BLE_OBSERVER_PRIO 2
+#endif
+
+//  NRF_BLE_ES_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Eddystone module.
+
+#ifndef NRF_BLE_ES_BLE_OBSERVER_PRIO
+#define NRF_BLE_ES_BLE_OBSERVER_PRIO 2
+#endif
+
+//  NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the GATT Service Client.
+
+#ifndef NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO
+#define NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO 2
+#endif
+
+//  NRF_BLE_GATT_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the GATT module.
+
+#ifndef NRF_BLE_GATT_BLE_OBSERVER_PRIO
+#define NRF_BLE_GATT_BLE_OBSERVER_PRIO 1
+#endif
+
+//  NRF_BLE_GQ_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the GATT Queue module.
+
+#ifndef NRF_BLE_GQ_BLE_OBSERVER_PRIO
+#define NRF_BLE_GQ_BLE_OBSERVER_PRIO 1
+#endif
+
+//  NRF_BLE_QWR_BLE_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the Queued writes module.
+
+#ifndef NRF_BLE_QWR_BLE_OBSERVER_PRIO
+#define NRF_BLE_QWR_BLE_OBSERVER_PRIO 2
+#endif
+
+//  NRF_BLE_SCAN_OBSERVER_PRIO
+//  Priority for dispatching the BLE events to the Scanning Module.
+
+#ifndef NRF_BLE_SCAN_OBSERVER_PRIO
+#define NRF_BLE_SCAN_OBSERVER_PRIO 1
+#endif
+
+//  PM_BLE_OBSERVER_PRIO - Priority with which BLE events are dispatched to the Peer Manager module.
+#ifndef PM_BLE_OBSERVER_PRIO
+#define PM_BLE_OBSERVER_PRIO 1
+#endif
+
+// 
+//==========================================================
+
+// 
+//==========================================================
+
+
+// 
+
+//  NRF_SDH_ENABLED - nrf_sdh - SoftDevice handler
+//==========================================================
+#ifndef NRF_SDH_ENABLED
+#define NRF_SDH_ENABLED 0
+#endif
+//  Dispatch model
+
+//  This setting configures how Stack events are dispatched to the application.
+//==========================================================
+//  NRF_SDH_DISPATCH_MODEL
+
+
+//  NRF_SDH_DISPATCH_MODEL_INTERRUPT: SoftDevice events are passed to the application from the interrupt context.
+//  NRF_SDH_DISPATCH_MODEL_APPSH: SoftDevice events are scheduled using @ref app_scheduler.
+//  NRF_SDH_DISPATCH_MODEL_POLLING: SoftDevice events are to be fetched manually.
+// <0=> NRF_SDH_DISPATCH_MODEL_INTERRUPT
+// <1=> NRF_SDH_DISPATCH_MODEL_APPSH
+// <2=> NRF_SDH_DISPATCH_MODEL_POLLING
+
+#ifndef NRF_SDH_DISPATCH_MODEL
+#define NRF_SDH_DISPATCH_MODEL 0
+#endif
+
+// 
+//==========================================================
+
+//  Clock - SoftDevice clock configuration
+
+//==========================================================
+//  NRF_SDH_CLOCK_LF_SRC  - SoftDevice clock source.
+
+// <0=> NRF_CLOCK_LF_SRC_RC
+// <1=> NRF_CLOCK_LF_SRC_XTAL
+// <2=> NRF_CLOCK_LF_SRC_SYNTH
+
+#ifndef NRF_SDH_CLOCK_LF_SRC
+#define NRF_SDH_CLOCK_LF_SRC 1
+#endif
+
+//  NRF_SDH_CLOCK_LF_RC_CTIV - SoftDevice calibration timer interval.
+#ifndef NRF_SDH_CLOCK_LF_RC_CTIV
+#define NRF_SDH_CLOCK_LF_RC_CTIV 0
+#endif
+
+//  NRF_SDH_CLOCK_LF_RC_TEMP_CTIV - SoftDevice calibration timer interval under constant temperature.
+//  How often (in number of calibration intervals) the RC oscillator shall be calibrated
+//   if the temperature has not changed.
+
+#ifndef NRF_SDH_CLOCK_LF_RC_TEMP_CTIV
+#define NRF_SDH_CLOCK_LF_RC_TEMP_CTIV 0
+#endif
+
+//  NRF_SDH_CLOCK_LF_ACCURACY  - External clock accuracy used in the LL to compute timing.
+
+// <0=> NRF_CLOCK_LF_ACCURACY_250_PPM
+// <1=> NRF_CLOCK_LF_ACCURACY_500_PPM
+// <2=> NRF_CLOCK_LF_ACCURACY_150_PPM
+// <3=> NRF_CLOCK_LF_ACCURACY_100_PPM
+// <4=> NRF_CLOCK_LF_ACCURACY_75_PPM
+// <5=> NRF_CLOCK_LF_ACCURACY_50_PPM
+// <6=> NRF_CLOCK_LF_ACCURACY_30_PPM
+// <7=> NRF_CLOCK_LF_ACCURACY_20_PPM
+// <8=> NRF_CLOCK_LF_ACCURACY_10_PPM
+// <9=> NRF_CLOCK_LF_ACCURACY_5_PPM
+// <10=> NRF_CLOCK_LF_ACCURACY_2_PPM
+// <11=> NRF_CLOCK_LF_ACCURACY_1_PPM
+
+#ifndef NRF_SDH_CLOCK_LF_ACCURACY
+#define NRF_SDH_CLOCK_LF_ACCURACY 7
+#endif
+
+// 
+//==========================================================
+
+//  SDH Observers - Observers and priority levels
+
+//==========================================================
+//  NRF_SDH_REQ_OBSERVER_PRIO_LEVELS - Total number of priority levels for request observers.
+//  This setting configures the number of priority levels available for the SoftDevice request event handlers.
+//  The priority level of a handler determines the order in which it receives events, with respect to other handlers.
+
+#ifndef NRF_SDH_REQ_OBSERVER_PRIO_LEVELS
+#define NRF_SDH_REQ_OBSERVER_PRIO_LEVELS 2
+#endif
+
+//  NRF_SDH_STATE_OBSERVER_PRIO_LEVELS - Total number of priority levels for state observers.
+//  This setting configures the number of priority levels available for the SoftDevice state event handlers.
+//  The priority level of a handler determines the order in which it receives events, with respect to other handlers.
+
+#ifndef NRF_SDH_STATE_OBSERVER_PRIO_LEVELS
+#define NRF_SDH_STATE_OBSERVER_PRIO_LEVELS 2
+#endif
+
+//  NRF_SDH_STACK_OBSERVER_PRIO_LEVELS - Total number of priority levels for stack event observers.
+//  This setting configures the number of priority levels available for the SoftDevice stack event handlers (ANT, BLE, SoC).
+//  The priority level of a handler determines the order in which it receives events, with respect to other handlers.
+
+#ifndef NRF_SDH_STACK_OBSERVER_PRIO_LEVELS
+#define NRF_SDH_STACK_OBSERVER_PRIO_LEVELS 2
+#endif
+
+
+//  State Observers priorities - Invididual priorities
+
+//==========================================================
+//  CLOCK_CONFIG_STATE_OBSERVER_PRIO
+//  Priority with which state events are dispatched to the Clock driver.
+
+#ifndef CLOCK_CONFIG_STATE_OBSERVER_PRIO
+#define CLOCK_CONFIG_STATE_OBSERVER_PRIO 0
+#endif
+
+//  POWER_CONFIG_STATE_OBSERVER_PRIO
+//  Priority with which state events are dispatched to the Power driver.
+
+#ifndef POWER_CONFIG_STATE_OBSERVER_PRIO
+#define POWER_CONFIG_STATE_OBSERVER_PRIO 0
+#endif
+
+//  RNG_CONFIG_STATE_OBSERVER_PRIO
+//  Priority with which state events are dispatched to this module.
+
+#ifndef RNG_CONFIG_STATE_OBSERVER_PRIO
+#define RNG_CONFIG_STATE_OBSERVER_PRIO 0
+#endif
+
+// 
+//==========================================================
+
+//  Stack Event Observers priorities - Invididual priorities
+
+//==========================================================
+//  NRF_SDH_ANT_STACK_OBSERVER_PRIO
+//  This setting configures the priority with which ANT events are processed with respect to other events coming from the stack.
+//  Modify this setting if you need to have ANT events dispatched before or after other stack events, such as BLE or SoC.
+//  Zero is the highest priority.
+
+#ifndef NRF_SDH_ANT_STACK_OBSERVER_PRIO
+#define NRF_SDH_ANT_STACK_OBSERVER_PRIO 0
+#endif
+
+//  NRF_SDH_BLE_STACK_OBSERVER_PRIO
+//  This setting configures the priority with which BLE events are processed with respect to other events coming from the stack.
+//  Modify this setting if you need to have BLE events dispatched before or after other stack events, such as ANT or SoC.
+//  Zero is the highest priority.
+
+#ifndef NRF_SDH_BLE_STACK_OBSERVER_PRIO
+#define NRF_SDH_BLE_STACK_OBSERVER_PRIO 0
+#endif
+
+//  NRF_SDH_SOC_STACK_OBSERVER_PRIO
+//  This setting configures the priority with which SoC events are processed with respect to other events coming from the stack.
+//  Modify this setting if you need to have SoC events dispatched before or after other stack events, such as ANT or BLE.
+//  Zero is the highest priority.
+
+#ifndef NRF_SDH_SOC_STACK_OBSERVER_PRIO
+#define NRF_SDH_SOC_STACK_OBSERVER_PRIO 0
+#endif
+
+// 
+//==========================================================
+
+// 
+//==========================================================
+
+
+// 
+
+//  NRF_SDH_SOC_ENABLED - nrf_sdh_soc - SoftDevice SoC event handler
+//==========================================================
+#ifndef NRF_SDH_SOC_ENABLED
+#define NRF_SDH_SOC_ENABLED 0
+#endif
+//  SoC Observers - Observers and priority levels
+
+//==========================================================
+//  NRF_SDH_SOC_OBSERVER_PRIO_LEVELS - Total number of priority levels for SoC observers.
+//  This setting configures the number of priority levels available for the SoC event handlers.
+//  The priority level of a handler determines the order in which it receives events, with respect to other handlers.
+
+#ifndef NRF_SDH_SOC_OBSERVER_PRIO_LEVELS
+#define NRF_SDH_SOC_OBSERVER_PRIO_LEVELS 2
+#endif
+
+//  SoC Observers priorities - Invididual priorities
+
+//==========================================================
+//  BLE_DFU_SOC_OBSERVER_PRIO
+//  Priority with which BLE events are dispatched to the DFU Service.
+
+#ifndef BLE_DFU_SOC_OBSERVER_PRIO
+#define BLE_DFU_SOC_OBSERVER_PRIO 1
+#endif
+
+//  CLOCK_CONFIG_SOC_OBSERVER_PRIO
+//  Priority with which SoC events are dispatched to the Clock driver.
+
+#ifndef CLOCK_CONFIG_SOC_OBSERVER_PRIO
+#define CLOCK_CONFIG_SOC_OBSERVER_PRIO 0
+#endif
+
+//  POWER_CONFIG_SOC_OBSERVER_PRIO
+//  Priority with which SoC events are dispatched to the Power driver.
+
+#ifndef POWER_CONFIG_SOC_OBSERVER_PRIO
+#define POWER_CONFIG_SOC_OBSERVER_PRIO 0
+#endif
+
+// 
+//==========================================================
+
+// 
+//==========================================================
+
+//  NRFX_NVMC_ENABLED - nrfx_nvmc - NVMC peripheral driver
+//==========================================================
+#ifndef NRFX_NVMC_ENABLED
+#define NRFX_NVMC_ENABLED 1
+#endif
+// 
+
+//==========================================================
+#ifndef NRFX_SYSTICK_ENABLED
+#define NRFX_SYSTICK_ENABLED 1
+#endif
+// <<< end of configuration section >>>
+#endif //SDK_CONFIG_H
+
diff --git a/bsp/nrf5x/nrf51822/project.uvoptx b/bsp/nrf5x/nrf51822/project.uvoptx
new file mode 100644
index 0000000000..0b8ce213d7
--- /dev/null
+++ b/bsp/nrf5x/nrf51822/project.uvoptx
@@ -0,0 +1,1080 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
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+      
+      
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 )  -FN1 -FC4000 -FD20000000 -FF0nrf51xxx -FL0200000 -FS00 -FP0($$Device:nRF51822_xxAA$Flash\nrf51xxx.flm)
+        
+        
+          0
+          JL2CM3
+          -U17935099 -O78 -S8 -ZTIFSpeedSel50000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN1 -FF0nrf51xxx -FS00 -FL0200000 -FP0($$Device:nRF51822_xxAA$Flash\nrf51xxx.flm)
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+      0
+      packages\nrfx-latest\drivers\src\nrfx_systick.c
+      nrfx_systick.c
+      0
+      0
+    
+    
+      7
+      37
+      1
+      0
+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_wdt.c
+      nrfx_wdt.c
+      0
+      0
+    
+    
+      7
+      38
+      1
+      0
+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_gpiote.c
+      nrfx_gpiote.c
+      0
+      0
+    
+    
+      7
+      39
+      1
+      0
+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_spis.c
+      nrfx_spis.c
+      0
+      0
+    
+    
+      7
+      40
+      1
+      0
+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_ipc.c
+      nrfx_ipc.c
+      0
+      0
+    
+    
+      7
+      41
+      1
+      0
+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_rng.c
+      nrfx_rng.c
+      0
+      0
+    
+    
+      7
+      42
+      1
+      0
+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_qspi.c
+      nrfx_qspi.c
+      0
+      0
+    
+    
+      7
+      43
+      1
+      0
+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_spi.c
+      nrfx_spi.c
+      0
+      0
+    
+    
+      7
+      44
+      1
+      0
+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_rtc.c
+      nrfx_rtc.c
+      0
+      0
+    
+    
+      7
+      45
+      1
+      0
+      0
+      0
+      packages\nrfx-latest\mdk\system_nrf51.c
+      system_nrf51.c
+      0
+      0
+    
+    
+      7
+      46
+      1
+      0
+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_qdec.c
+      nrfx_qdec.c
+      0
+      0
+    
+    
+      7
+      47
+      1
+      0
+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_twim.c
+      nrfx_twim.c
+      0
+      0
+    
+    
+      7
+      48
+      1
+      0
+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_clock.c
+      nrfx_clock.c
+      0
+      0
+    
+    
+      7
+      49
+      1
+      0
+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_pdm.c
+      nrfx_pdm.c
+      0
+      0
+    
+    
+      7
+      50
+      1
+      0
+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_uarte.c
+      nrfx_uarte.c
+      0
+      0
+    
+    
+      7
+      51
+      1
+      0
+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_adc.c
+      nrfx_adc.c
+      0
+      0
+    
+    
+      7
+      52
+      1
+      0
+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_ppi.c
+      nrfx_ppi.c
+      0
+      0
+    
+    
+      7
+      53
+      1
+      0
+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_uart.c
+      nrfx_uart.c
+      0
+      0
+    
+    
+      7
+      54
+      1
+      0
+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_saadc.c
+      nrfx_saadc.c
+      0
+      0
+    
+    
+      7
+      55
+      1
+      0
+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_usbd.c
+      nrfx_usbd.c
+      0
+      0
+    
+    
+      7
+      56
+      1
+      0
+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_i2s.c
+      nrfx_i2s.c
+      0
+      0
+    
+    
+      7
+      57
+      2
+      0
+      0
+      0
+      packages\nrfx-latest\mdk\arm_startup_nrf51.s
+      arm_startup_nrf51.s
+      0
+      0
+    
+    
+      7
+      58
+      1
+      0
+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_twis.c
+      nrfx_twis.c
+      0
+      0
+    
+    
+      7
+      59
+      1
+      0
+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_egu.c
+      nrfx_egu.c
+      0
+      0
+    
+    
+      7
+      60
+      1
+      0
+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_lpcomp.c
+      nrfx_lpcomp.c
+      0
+      0
+    
+    
+      7
+      61
+      1
+      0
+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_power.c
+      nrfx_power.c
+      0
+      0
+    
+    
+      7
+      62
+      1
+      0
+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_usbreg.c
+      nrfx_usbreg.c
+      0
+      0
+    
+    
+      7
+      63
+      1
+      0
+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_nvmc.c
+      nrfx_nvmc.c
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+      0
+    
+    
+      7
+      64
+      1
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+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_spim.c
+      nrfx_spim.c
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+      0
+    
+    
+      7
+      65
+      1
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+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_twi_twim.c
+      nrfx_twi_twim.c
+      0
+      0
+    
+    
+      7
+      66
+      1
+      0
+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_pwm.c
+      nrfx_pwm.c
+      0
+      0
+    
+    
+      7
+      67
+      1
+      0
+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_twi.c
+      nrfx_twi.c
+      0
+      0
+    
+    
+      7
+      68
+      1
+      0
+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_dppi.c
+      nrfx_dppi.c
+      0
+      0
+    
+    
+      7
+      69
+      1
+      0
+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_comp.c
+      nrfx_comp.c
+      0
+      0
+    
+    
+      7
+      70
+      1
+      0
+      0
+      0
+      packages\nrfx-latest\drivers\src\nrfx_temp.c
+      nrfx_temp.c
+      0
+      0
+    
+  
+
+
diff --git a/bsp/nrf5x/nrf51822/project.uvprojx b/bsp/nrf5x/nrf51822/project.uvprojx
new file mode 100644
index 0000000000..ae49ad3fe5
--- /dev/null
+++ b/bsp/nrf5x/nrf51822/project.uvprojx
@@ -0,0 +1,777 @@
+
+
+
+  2.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      rtthread
+      0x4
+      ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
+      
+        
+          nRF51822_xxAA
+          Nordic Semiconductor
+          NordicSemiconductor.nRF_DeviceFamilyPack.8.38.0
+          http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/
+          IRAM(0x20000000,0x00004000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE
+          
+          
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC4000 -FN1 -FF0nrf51xxx -FS00 -FL0200000 -FP0($$Device:nRF51822_xxAA$Flash\nrf51xxx.flm))
+          0
+          $$Device:nRF51822_xxAA$Device\Include\nrf.h
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:nRF51822_xxAA$SVD\nrf51.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          .\build\
+          rtthread
+          1
+          0
+          0
+          1
+          1
+          .\build\
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            1
+            0
+            fromelf --bin !L --output rtthread.bin
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          1
+        
+        
+          SARMCM3.DLL
+            
+          DARMCM1.DLL
+          -pCM0
+          SARMCM3.DLL
+           
+          TARMCM1.DLL
+          -pCM0
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4096
+          
+          1
+          BIN\UL2CM3.DLL
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M0"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            8
+            0
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x4000
+              
+              
+                1
+                0x0
+                0x40000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x40000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x4000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            1
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              --reduce_paths
+              NRF51822_XXAA, USE_APP_CONFIG, __RTTHREAD__
+              
+              applications;.;..\libraries\cmsis\include;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\drivers;..\..\..\components\finsh;.;..\..\..\include;packages\nrfx-latest;packages\nrfx-latest\drivers;packages\nrfx-latest\drivers\include;packages\nrfx-latest\mdk;packages\nrfx-latest\hal
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              --cpreproc_opts=-DBLE_STACK_SUPPORT_REQD,-DNRF_SD_BLE_API_VERSION=4,-DS132,-DSOFTDEVICE_PRESENT,-DSWI_DISABLE0,-DCONFIG_GPIO_AS_PINRESET,-DNRF52,-DNRF52832_XXAA,-DNRF52_PAN_12,-DNRF52_PAN_15,-DNRF52_PAN_20,-DNRF52_PAN_31,-DNRF52_PAN_36,-DNRF52_PAN_51,-DNRF52_PAN_54,-DNRF52_PAN_55,-DNRF52_PAN_58,-DNRF52_PAN_64,-DNRF52_PAN_74
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x00000000
+            0x20000000
+            
+            .\board\linker_scripts\link.sct
+            
+            
+            
+            
+            
+          
+        
+      
+      
+        
+          Applications
+          
+            
+              application.c
+              1
+              applications\application.c
+            
+          
+        
+        
+          CPU
+          
+            
+              backtrace.c
+              1
+              ..\..\..\libcpu\arm\common\backtrace.c
+            
+            
+              showmem.c
+              1
+              ..\..\..\libcpu\arm\common\showmem.c
+            
+            
+              div0.c
+              1
+              ..\..\..\libcpu\arm\common\div0.c
+            
+            
+              context_rvds.S
+              2
+              ..\..\..\libcpu\arm\cortex-m0\context_rvds.S
+            
+            
+              cpuport.c
+              1
+              ..\..\..\libcpu\arm\cortex-m0\cpuport.c
+            
+          
+        
+        
+          DeviceDrivers
+          
+            
+              pin.c
+              1
+              ..\..\..\components\drivers\misc\pin.c
+            
+            
+              serial.c
+              1
+              ..\..\..\components\drivers\serial\serial.c
+            
+            
+              waitqueue.c
+              1
+              ..\..\..\components\drivers\src\waitqueue.c
+            
+            
+              workqueue.c
+              1
+              ..\..\..\components\drivers\src\workqueue.c
+            
+            
+              ringbuffer.c
+              1
+              ..\..\..\components\drivers\src\ringbuffer.c
+            
+            
+              dataqueue.c
+              1
+              ..\..\..\components\drivers\src\dataqueue.c
+            
+            
+              pipe.c
+              1
+              ..\..\..\components\drivers\src\pipe.c
+            
+            
+              ringblk_buf.c
+              1
+              ..\..\..\components\drivers\src\ringblk_buf.c
+            
+            
+              completion.c
+              1
+              ..\..\..\components\drivers\src\completion.c
+            
+          
+        
+        
+          Drivers
+          
+            
+              board.c
+              1
+              board\board.c
+            
+            
+              drv_uart.c
+              1
+              ..\libraries\drivers\drv_uart.c
+            
+          
+        
+        
+          finsh
+          
+            
+              shell.c
+              1
+              ..\..\..\components\finsh\shell.c
+            
+            
+              msh.c
+              1
+              ..\..\..\components\finsh\msh.c
+            
+            
+              cmd.c
+              1
+              ..\..\..\components\finsh\cmd.c
+            
+          
+        
+        
+          Kernel
+          
+            
+              thread.c
+              1
+              ..\..\..\src\thread.c
+            
+            
+              scheduler.c
+              1
+              ..\..\..\src\scheduler.c
+            
+            
+              mem.c
+              1
+              ..\..\..\src\mem.c
+            
+            
+              mempool.c
+              1
+              ..\..\..\src\mempool.c
+            
+            
+              clock.c
+              1
+              ..\..\..\src\clock.c
+            
+            
+              timer.c
+              1
+              ..\..\..\src\timer.c
+            
+            
+              idle.c
+              1
+              ..\..\..\src\idle.c
+            
+            
+              kservice.c
+              1
+              ..\..\..\src\kservice.c
+            
+            
+              components.c
+              1
+              ..\..\..\src\components.c
+            
+            
+              irq.c
+              1
+              ..\..\..\src\irq.c
+            
+            
+              device.c
+              1
+              ..\..\..\src\device.c
+            
+            
+              object.c
+              1
+              ..\..\..\src\object.c
+            
+            
+              ipc.c
+              1
+              ..\..\..\src\ipc.c
+            
+          
+        
+        
+          nrfx
+          
+            
+              nrfx_timer.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_timer.c
+            
+            
+              nrfx_nfct.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_nfct.c
+            
+            
+              nrfx_systick.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_systick.c
+            
+            
+              nrfx_wdt.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_wdt.c
+            
+            
+              nrfx_gpiote.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_gpiote.c
+            
+            
+              nrfx_spis.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_spis.c
+            
+            
+              nrfx_ipc.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_ipc.c
+            
+            
+              nrfx_rng.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_rng.c
+            
+            
+              nrfx_qspi.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_qspi.c
+            
+            
+              nrfx_spi.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_spi.c
+            
+            
+              nrfx_rtc.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_rtc.c
+            
+            
+              system_nrf51.c
+              1
+              packages\nrfx-latest\mdk\system_nrf51.c
+            
+            
+              nrfx_qdec.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_qdec.c
+            
+            
+              nrfx_twim.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_twim.c
+            
+            
+              nrfx_clock.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_clock.c
+            
+            
+              nrfx_pdm.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_pdm.c
+            
+            
+              nrfx_uarte.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_uarte.c
+            
+            
+              nrfx_adc.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_adc.c
+            
+            
+              nrfx_ppi.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_ppi.c
+            
+            
+              nrfx_uart.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_uart.c
+            
+            
+              nrfx_saadc.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_saadc.c
+            
+            
+              nrfx_usbd.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_usbd.c
+            
+            
+              nrfx_i2s.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_i2s.c
+            
+            
+              arm_startup_nrf51.s
+              2
+              packages\nrfx-latest\mdk\arm_startup_nrf51.s
+            
+            
+              nrfx_twis.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_twis.c
+            
+            
+              nrfx_egu.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_egu.c
+            
+            
+              nrfx_lpcomp.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_lpcomp.c
+            
+            
+              nrfx_power.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_power.c
+            
+            
+              nrfx_usbreg.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_usbreg.c
+            
+            
+              nrfx_nvmc.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_nvmc.c
+            
+            
+              nrfx_spim.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_spim.c
+            
+            
+              nrfx_twi_twim.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_twi_twim.c
+            
+            
+              nrfx_pwm.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_pwm.c
+            
+            
+              nrfx_twi.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_twi.c
+            
+            
+              nrfx_dppi.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_dppi.c
+            
+            
+              nrfx_comp.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_comp.c
+            
+            
+              nrfx_temp.c
+              1
+              packages\nrfx-latest\drivers\src\nrfx_temp.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+    
+  
+
+
diff --git a/bsp/nrf5x/nrf51822/rtconfig.h b/bsp/nrf5x/nrf51822/rtconfig.h
new file mode 100644
index 0000000000..a4e1a98a9e
--- /dev/null
+++ b/bsp/nrf5x/nrf51822/rtconfig.h
@@ -0,0 +1,190 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+
+/* kservice optimization */
+
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart0"
+#define RT_VER_NUM 0x40003
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_USING_MSH_ONLY
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SERIAL
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* Network interface device */
+
+
+/* light weight TCP/IP stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+#define PKG_USING_NRFX
+#define PKG_USING_NRFX_LATEST_VERSION
+
+/* AI packages */
+
+
+/* miscellaneous packages */
+
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Hardware Drivers Config */
+
+#define SOC_NRF51822
+#define SOC_NORDIC
+#define BSP_BOARD_MICROBIT_1_5
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_UART
+#define BSP_USING_UART0
+#define BSP_UART0_RX_PIN 25
+#define BSP_UART0_TX_PIN 24
+
+/* On-chip flash config */
+
+#define MCU_FLASH_START_ADDRESS 0x00000000
+#define MCU_FLASH_SIZE_KB 256
+#define MCU_SRAM_START_ADDRESS 0x20000000
+#define MCU_SRAM_SIZE_KB 16
+#define MCU_FLASH_PAGE_SIZE 0x1000
+#define NRFX_CLOCK_ENABLED 1
+#define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY 7
+#define NRFX_CLOCK_CONFIG_LF_SRC 1
+#define NRFX_USING_UART
+#define NRFX_UART_ENABLED 1
+#define NRFX_UART0_ENABLED 1
+
+#endif
diff --git a/bsp/nrf5x/nrf51822/rtconfig.py b/bsp/nrf5x/nrf51822/rtconfig.py
new file mode 100644
index 0000000000..bfa1a160f1
--- /dev/null
+++ b/bsp/nrf5x/nrf51822/rtconfig.py
@@ -0,0 +1,92 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m0'
+CROSS_TOOL='keil'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = 'D:/SourceryGCC/bin'
+elif CROSS_TOOL == 'keil':
+    PLATFORM    = 'armcc'
+    EXEC_PATH   = 'C:/Keil_v5'
+elif CROSS_TOOL == 'iar':
+    print('================ERROR============================')
+    print('Not support iar yet!')
+    print('=================================================')
+    exit(0)
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu='+CPU + ' -mthumb -ffunction-sections -fdata-sections'
+    CFLAGS = DEVICE
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --device DARMSTM'
+    CFLAGS = DEVICE + ' --apcs=interwork'
+    AFLAGS = DEVICE
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "board\linker_scripts\link.sct"'
+
+    CFLAGS += ' --c99'
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
+    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
+
+    EXEC_PATH += '/arm/bin40/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+
+def dist_handle(BSP_ROOT, dist_dir):
+    import sys
+    cwd_path = os.getcwd()
+    sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+    from sdk_dist import dist_do_building
+    dist_do_building(BSP_ROOT, dist_dir)
diff --git a/bsp/nrf5x/libraries/templates/nrf52x/template.uvoptx b/bsp/nrf5x/nrf51822/template.uvoptx
similarity index 87%
rename from bsp/nrf5x/libraries/templates/nrf52x/template.uvoptx
rename to bsp/nrf5x/nrf51822/template.uvoptx
index 7bd9338b2b..96e6c68740 100644
--- a/bsp/nrf5x/libraries/templates/nrf52x/template.uvoptx
+++ b/bsp/nrf5x/nrf51822/template.uvoptx
@@ -119,13 +119,13 @@
       
         
           0
-          JL2CM3
-          -U59401765 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF52832_xxAA$Flash\nrf52xxx.flm) -FF1nrf52xxx_uicr.flm -FS110001000 -FL11000 -FP1($$Device:nRF52832_xxAA$Flash\nrf52xxx_uicr.flm)
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 )  -FN1 -FC4000 -FD20000000 -FF0nrf51xxx -FL0200000 -FS00 -FP0($$Device:nRF51822_xxAA$Flash\nrf51xxx.flm)
         
         
           0
-          UL2CM3
-          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC4000 -FN2 -FF0nrf52xxx -FS00 -FL0200000 -FF1nrf52xxx_uicr -FS110001000 -FL11000 -FP0($$Device:nRF52832_xxAA$Flash\nrf52xxx.flm) -FP1($$Device:nRF52832_xxAA$Flash\nrf52xxx_uicr.flm))
+          JL2CM3
+          -U17935099 -O78 -S8 -ZTIFSpeedSel50000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC4000 -FN1 -FF0nrf51xxx -FS00 -FL0200000 -FP0($$Device:nRF51822_xxAA$Flash\nrf51xxx.flm)
         
       
       
@@ -171,6 +171,13 @@
       
       
       
+      
+        1
+        1
+        0
+        2
+        10000000
+      
     
   
 
diff --git a/bsp/nrf5x/nrf51822/template.uvprojx b/bsp/nrf5x/nrf51822/template.uvprojx
new file mode 100644
index 0000000000..e08678d3c2
--- /dev/null
+++ b/bsp/nrf5x/nrf51822/template.uvprojx
@@ -0,0 +1,390 @@
+
+
+
+  2.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      rtthread
+      0x4
+      ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
+      
+        
+          nRF51822_xxAA
+          Nordic Semiconductor
+          NordicSemiconductor.nRF_DeviceFamilyPack.8.38.0
+          http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/
+          IRAM(0x20000000,0x00004000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE
+          
+          
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC4000 -FN1 -FF0nrf51xxx -FS00 -FL0200000 -FP0($$Device:nRF51822_xxAA$Flash\nrf51xxx.flm))
+          0
+          $$Device:nRF51822_xxAA$Device\Include\nrf.h
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:nRF51822_xxAA$SVD\nrf51.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          .\build\
+          rtthread
+          1
+          0
+          0
+          1
+          1
+          .\build\
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            1
+            0
+            fromelf --bin !L --output rtthread.bin
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          1
+        
+        
+          SARMCM3.DLL
+            
+          DARMCM1.DLL
+          -pCM0
+          SARMCM3.DLL
+           
+          TARMCM1.DLL
+          -pCM0
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4096
+          
+          1
+          BIN\UL2CM3.DLL
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M0"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            8
+            0
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x4000
+              
+              
+                1
+                0x0
+                0x40000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x40000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x4000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            1
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              --reduce_paths
+              
+              
+              
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              --cpreproc_opts=-DBLE_STACK_SUPPORT_REQD,-DNRF_SD_BLE_API_VERSION=4,-DS132,-DSOFTDEVICE_PRESENT,-DSWI_DISABLE0,-DCONFIG_GPIO_AS_PINRESET,-DNRF52,-DNRF52832_XXAA,-DNRF52_PAN_12,-DNRF52_PAN_15,-DNRF52_PAN_20,-DNRF52_PAN_31,-DNRF52_PAN_36,-DNRF52_PAN_51,-DNRF52_PAN_54,-DNRF52_PAN_55,-DNRF52_PAN_58,-DNRF52_PAN_64,-DNRF52_PAN_74
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x00000000
+            0x20000000
+            
+            .\board\linker_scripts\link.sct
+            
+            
+            --diag_suppress 6330
+            
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+    
+  
+
+
diff --git a/bsp/nrf5x/nrf52832/.gitignore b/bsp/nrf5x/nrf52832/.gitignore
new file mode 100644
index 0000000000..2541e31630
--- /dev/null
+++ b/bsp/nrf5x/nrf52832/.gitignore
@@ -0,0 +1,7 @@
+# vscode common config
+.vscode/*
+!.vscode/launch.json
+!.vscode/tasks.json
+
+# OS X icon info
+.DS_Store
\ No newline at end of file
diff --git a/bsp/nrf5x/nrf52832/.vscode/launch.json b/bsp/nrf5x/nrf52832/.vscode/launch.json
new file mode 100644
index 0000000000..c3a54b371b
--- /dev/null
+++ b/bsp/nrf5x/nrf52832/.vscode/launch.json
@@ -0,0 +1,15 @@
+{
+    "version": "0.2.0",
+    "configurations": [
+        {
+            "type": "cortex-debug",
+            "request": "launch",
+            "servertype": "jlink",
+            "cwd": "${workspaceRoot}",
+            "executable": "rt-thread.elf",
+            "name": "Cortex Debug",
+            "device": "nrf52",
+            "interface": "swd"
+        }
+    ]
+}
\ No newline at end of file
diff --git a/bsp/nrf5x/nrf52832/.vscode/tasks.json b/bsp/nrf5x/nrf52832/.vscode/tasks.json
new file mode 100644
index 0000000000..68331caaad
--- /dev/null
+++ b/bsp/nrf5x/nrf52832/.vscode/tasks.json
@@ -0,0 +1,54 @@
+{
+    // See https://go.microsoft.com/fwlink/?LinkId=733558
+    // for the documentation about the tasks.json format
+    "version": "2.0.0",
+    "tasks": [
+        {
+            "label": "config",
+            "type": "shell",
+            "command": "RTT_ROOT=../../.. scons --pyconfig",
+            "problemMatcher": []
+        },
+        {
+            "label": "build",
+            "type": "shell",
+            "command": "scons",
+            "problemMatcher": [],
+            "group": {
+                "kind": "build",
+                "isDefault": true
+            }
+        },
+        {
+            "label": "clean",
+            "type": "shell",
+            "command": "scons -c",
+            "problemMatcher": []
+        },
+        {
+            "label": "flash",
+            "type": "shell",
+            "command": "nrfjprog -f nrf52 --program rt-thread.hex --sectorerase",
+            "group": "build",
+            "problemMatcher": []
+        },
+        {
+            "label": "flash_softdevice",
+            "type": "shell",
+            "command": "nrfjprog -f nrf52 --program packages/nrf5x_sdk-latest/components/softdevice/s132/hex/s132_nrf52_7.0.1_softdevice.hex --sectorerase",
+            "problemMatcher": []
+        },
+        {
+            "label": "erase",
+            "type": "shell",
+            "command": "nrfjprog -f nrf52 --eraseall",
+            "problemMatcher": []
+        },
+        {
+            "label": "reset",
+            "type": "shell",
+            "command": "nrfjprog -f nrf52 --reset",
+            "problemMatcher": []
+        }
+    ]
+}
\ No newline at end of file
diff --git a/bsp/nrf5x/nrf52832/README.md b/bsp/nrf5x/nrf52832/README.md
index 8892190001..e5f46d456f 100644
--- a/bsp/nrf5x/nrf52832/README.md
+++ b/bsp/nrf5x/nrf52832/README.md
@@ -2,7 +2,7 @@
 
 ## 简介
 
-该文件夹主要存放所有主芯片为nRF52840的板级支持包。目前默认支持的开发板是官方[PCA10040](https://www.nordicsemi.com/Software-and-tools/Development-Kits/nRF52-DK)
+该文件夹主要存放所有主芯片为nRF52832的板级支持包。目前默认支持的开发板是官方[PCA10040](https://www.nordicsemi.com/Software-and-tools/Development-Kits/nRF52-DK)
 主要内容如下：
 
 - 开发板资源介绍
@@ -61,6 +61,30 @@ PCA10040-nrf52832开发板常用 **板载资源** 如下：
 4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。
 
 
+### VS Code开发支持
+
+配置步骤：
+
+1. 在命令行设置以下两个环境变量：
+
+    ```bash
+    export RTT_CC=gcc
+    export RTT_EXEC_PATH=<工具链路径/bin>
+    ```
+
+2. 搜索插件`Cortex-debug`并安装。
+3. 安装[nRF Command Line Tools](https://www.nordicsemi.com/Software-and-tools/Development-Tools/nRF-Command-Line-Tools)以支持`nrfjprog`命令。
+4. 在.vscode/settings.json内配置工具链和`JlinkGDBServer`，sample：
+
+    ```json
+    {
+        "cortex-debug.armToolchainPath": "/usr/local/gcc-arm-none-eabi-9-2019-q4-major/bin/",
+        "cortex-debug.armToolchainPrefix": "arm-none-eabi",
+        "cortex-debug.JLinkGDBServerPath": "/Applications/SEGGER/JLink/JLinkGDBServer"
+    }
+    ```
+
+5. 点击`终端`->`运行任务`->`build`编译，点击`终端`->`运行任务`->`flash`烧录，点击左侧`debug`->`run`使用VS Code进行debug。
 
 ## 支持其他开发板
 
diff --git a/bsp/nrf5x/nrf52832/applications/application.c b/bsp/nrf5x/nrf52832/applications/application.c
index 3e29eeeac3..5027866e19 100644
--- a/bsp/nrf5x/nrf52832/applications/application.c
+++ b/bsp/nrf5x/nrf52832/applications/application.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,16 +16,16 @@
 
 int main(void)
 {
-    int count = 1; 
+    int count = 1;
     rt_pin_mode(DK_BOARD_LED_1, PIN_MODE_OUTPUT);
-    
+
     while (count++)
-    {    
+    {
         rt_pin_write(DK_BOARD_LED_1, PIN_HIGH);
         rt_thread_mdelay(500);
-        
+
         rt_pin_write(DK_BOARD_LED_1, PIN_LOW);
-        rt_thread_mdelay(500);                    
+        rt_thread_mdelay(500);
     }
     return RT_EOK;
 }
diff --git a/bsp/nrf5x/nrf52832/board/app_config.h b/bsp/nrf5x/nrf52832/board/app_config.h
index 7909dd55b4..67db2eb886 100644
--- a/bsp/nrf5x/nrf52832/board/app_config.h
+++ b/bsp/nrf5x/nrf52832/board/app_config.h
@@ -1,4 +1,4 @@
 #ifndef APP_CONFIG_H
 #define APP_CONFIG_H
 
-#endif	//APP_CONFIG_H
+#endif  //APP_CONFIG_H
diff --git a/bsp/nrf5x/nrf52832/board/board.c b/bsp/nrf5x/nrf52832/board/board.c
index 2ba3214bfa..0b3a436530 100644
--- a/bsp/nrf5x/nrf52832/board/board.c
+++ b/bsp/nrf5x/nrf52832/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/nrf5x/nrf52832/board/sdk_config.h b/bsp/nrf5x/nrf52832/board/sdk_config.h
index 4055c9ddde..c3948ba354 100644
--- a/bsp/nrf5x/nrf52832/board/sdk_config.h
+++ b/bsp/nrf5x/nrf52832/board/sdk_config.h
@@ -46,26 +46,26 @@
 #ifdef USE_APP_CONFIG
 #include "app_config.h"
 #endif
-//  nRF_BLE 
+//  nRF_BLE
 
 #include 
 //==========================================================
 //  BLE_ADVERTISING_ENABLED  - ble_advertising - Advertising module
- 
+
 
 #ifndef BLE_ADVERTISING_ENABLED
 #define BLE_ADVERTISING_ENABLED 0
 #endif
 
 //  BLE_DTM_ENABLED  - ble_dtm - Module for testing RF/PHY using DTM commands
- 
+
 
 #ifndef BLE_DTM_ENABLED
 #define BLE_DTM_ENABLED 0
 #endif
 
 //  BLE_RACP_ENABLED  - ble_racp - Record Access Control Point library
- 
+
 
 #ifndef BLE_RACP_ENABLED
 #define BLE_RACP_ENABLED 0
@@ -76,7 +76,7 @@
 #ifndef NRF_BLE_QWR_ENABLED
 #define NRF_BLE_QWR_ENABLED 0
 #endif
-//  NRF_BLE_QWR_MAX_ATTR - Maximum number of attribute handles that can be registered. This number must be adjusted according to the number of attributes for which Queued Writes will be enabled. If it is zero, the module will reject all Queued Write requests. 
+//  NRF_BLE_QWR_MAX_ATTR - Maximum number of attribute handles that can be registered. This number must be adjusted according to the number of attributes for which Queued Writes will be enabled. If it is zero, the module will reject all Queued Write requests.
 #ifndef NRF_BLE_QWR_MAX_ATTR
 #define NRF_BLE_QWR_MAX_ATTR 0
 #endif
@@ -88,12 +88,12 @@
 #ifndef PEER_MANAGER_ENABLED
 #define PEER_MANAGER_ENABLED 0
 #endif
-//  PM_MAX_REGISTRANTS - Number of event handlers that can be registered. 
+//  PM_MAX_REGISTRANTS - Number of event handlers that can be registered.
 #ifndef PM_MAX_REGISTRANTS
 #define PM_MAX_REGISTRANTS 3
 #endif
 
-//  PM_FLASH_BUFFERS - Number of internal buffers for flash operations. 
+//  PM_FLASH_BUFFERS - Number of internal buffers for flash operations.
 //  Decrease this value to lower RAM usage.
 
 #ifndef PM_FLASH_BUFFERS
@@ -101,7 +101,7 @@
 #endif
 
 //  PM_CENTRAL_ENABLED  - Enable/disable central-specific Peer Manager functionality.
- 
+
 
 //  Enable/disable central-specific Peer Manager functionality.
 
@@ -110,7 +110,7 @@
 #endif
 
 //  PM_SERVICE_CHANGED_ENABLED  - Enable/disable the service changed management for GATT server in Peer Manager.
- 
+
 
 //  If not using a GATT server, or using a server wihout a service changed characteristic,
 //  disable this to save code space.
@@ -120,7 +120,7 @@
 #endif
 
 //  PM_PEER_RANKS_ENABLED  - Enable/disable the peer rank management in Peer Manager.
- 
+
 
 //  Set this to false to save code space if not using the peer rank API.
 
@@ -129,7 +129,7 @@
 #endif
 
 //  PM_LESC_ENABLED  - Enable/disable LESC support in Peer Manager.
- 
+
 
 //  If set to true, you need to call nrf_ble_lesc_request_handler() in the main loop to respond to LESC-related BLE events. If LESC support is not required, set this to false to save code space.
 
@@ -142,22 +142,22 @@
 #ifndef PM_RA_PROTECTION_ENABLED
 #define PM_RA_PROTECTION_ENABLED 0
 #endif
-//  PM_RA_PROTECTION_TRACKED_PEERS_NUM - Maximum number of peers whose authorization status can be tracked. 
+//  PM_RA_PROTECTION_TRACKED_PEERS_NUM - Maximum number of peers whose authorization status can be tracked.
 #ifndef PM_RA_PROTECTION_TRACKED_PEERS_NUM
 #define PM_RA_PROTECTION_TRACKED_PEERS_NUM 8
 #endif
 
-//  PM_RA_PROTECTION_MIN_WAIT_INTERVAL - Minimum waiting interval (in ms) before a new pairing attempt can be initiated. 
+//  PM_RA_PROTECTION_MIN_WAIT_INTERVAL - Minimum waiting interval (in ms) before a new pairing attempt can be initiated.
 #ifndef PM_RA_PROTECTION_MIN_WAIT_INTERVAL
 #define PM_RA_PROTECTION_MIN_WAIT_INTERVAL 4000
 #endif
 
-//  PM_RA_PROTECTION_MAX_WAIT_INTERVAL - Maximum waiting interval (in ms) before a new pairing attempt can be initiated. 
+//  PM_RA_PROTECTION_MAX_WAIT_INTERVAL - Maximum waiting interval (in ms) before a new pairing attempt can be initiated.
 #ifndef PM_RA_PROTECTION_MAX_WAIT_INTERVAL
 #define PM_RA_PROTECTION_MAX_WAIT_INTERVAL 64000
 #endif
 
-//  PM_RA_PROTECTION_REWARD_PERIOD - Reward period (in ms). 
+//  PM_RA_PROTECTION_REWARD_PERIOD - Reward period (in ms).
 //  The waiting interval is gradually decreased when no new failed pairing attempts are made during reward period.
 
 #ifndef PM_RA_PROTECTION_REWARD_PERIOD
@@ -166,7 +166,7 @@
 
 // 
 
-//  PM_HANDLER_SEC_DELAY_MS - Delay before starting security. 
+//  PM_HANDLER_SEC_DELAY_MS - Delay before starting security.
 //   This might be necessary for interoperability reasons, especially as peripheral.
 
 #ifndef PM_HANDLER_SEC_DELAY_MS
@@ -175,28 +175,28 @@
 
 // 
 
-//  
+// 
 //==========================================================
 
-//  nRF_BLE_Services 
+//  nRF_BLE_Services
 
 //==========================================================
 //  BLE_ANCS_C_ENABLED  - ble_ancs_c - Apple Notification Service Client
- 
+
 
 #ifndef BLE_ANCS_C_ENABLED
 #define BLE_ANCS_C_ENABLED 0
 #endif
 
 //  BLE_ANS_C_ENABLED  - ble_ans_c - Alert Notification Service Client
- 
+
 
 #ifndef BLE_ANS_C_ENABLED
 #define BLE_ANS_C_ENABLED 0
 #endif
 
 //  BLE_BAS_C_ENABLED  - ble_bas_c - Battery Service Client
- 
+
 
 #ifndef BLE_BAS_C_ENABLED
 #define BLE_BAS_C_ENABLED 0
@@ -213,44 +213,44 @@
 #define BLE_BAS_CONFIG_LOG_ENABLED 0
 #endif
 //  BLE_BAS_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef BLE_BAS_CONFIG_LOG_LEVEL
 #define BLE_BAS_CONFIG_LOG_LEVEL 3
 #endif
 
 //  BLE_BAS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef BLE_BAS_CONFIG_INFO_COLOR
 #define BLE_BAS_CONFIG_INFO_COLOR 0
 #endif
 
 //  BLE_BAS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef BLE_BAS_CONFIG_DEBUG_COLOR
 #define BLE_BAS_CONFIG_DEBUG_COLOR 0
@@ -261,63 +261,63 @@
 // 
 
 //  BLE_CSCS_ENABLED  - ble_cscs - Cycling Speed and Cadence Service
- 
+
 
 #ifndef BLE_CSCS_ENABLED
 #define BLE_CSCS_ENABLED 0
 #endif
 
 //  BLE_CTS_C_ENABLED  - ble_cts_c - Current Time Service Client
- 
+
 
 #ifndef BLE_CTS_C_ENABLED
 #define BLE_CTS_C_ENABLED 0
 #endif
 
 //  BLE_DIS_ENABLED  - ble_dis - Device Information Service
- 
+
 
 #ifndef BLE_DIS_ENABLED
 #define BLE_DIS_ENABLED 0
 #endif
 
 //  BLE_GLS_ENABLED  - ble_gls - Glucose Service
- 
+
 
 #ifndef BLE_GLS_ENABLED
 #define BLE_GLS_ENABLED 0
 #endif
 
 //  BLE_HIDS_ENABLED  - ble_hids - Human Interface Device Service
- 
+
 
 #ifndef BLE_HIDS_ENABLED
 #define BLE_HIDS_ENABLED 0
 #endif
 
 //  BLE_HRS_C_ENABLED  - ble_hrs_c - Heart Rate Service Client
- 
+
 
 #ifndef BLE_HRS_C_ENABLED
 #define BLE_HRS_C_ENABLED 0
 #endif
 
 //  BLE_HRS_ENABLED  - ble_hrs - Heart Rate Service
- 
+
 
 #ifndef BLE_HRS_ENABLED
 #define BLE_HRS_ENABLED 0
 #endif
 
 //  BLE_HTS_ENABLED  - ble_hts - Health Thermometer Service
- 
+
 
 #ifndef BLE_HTS_ENABLED
 #define BLE_HTS_ENABLED 0
 #endif
 
 //  BLE_IAS_C_ENABLED  - ble_ias_c - Immediate Alert Service Client
- 
+
 
 #ifndef BLE_IAS_C_ENABLED
 #define BLE_IAS_C_ENABLED 0
@@ -334,44 +334,44 @@
 #define BLE_IAS_CONFIG_LOG_ENABLED 0
 #endif
 //  BLE_IAS_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef BLE_IAS_CONFIG_LOG_LEVEL
 #define BLE_IAS_CONFIG_LOG_LEVEL 3
 #endif
 
 //  BLE_IAS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef BLE_IAS_CONFIG_INFO_COLOR
 #define BLE_IAS_CONFIG_INFO_COLOR 0
 #endif
 
 //  BLE_IAS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef BLE_IAS_CONFIG_DEBUG_COLOR
 #define BLE_IAS_CONFIG_DEBUG_COLOR 0
@@ -382,28 +382,28 @@
 // 
 
 //  BLE_LBS_C_ENABLED  - ble_lbs_c - Nordic LED Button Service Client
- 
+
 
 #ifndef BLE_LBS_C_ENABLED
 #define BLE_LBS_C_ENABLED 0
 #endif
 
 //  BLE_LBS_ENABLED  - ble_lbs - LED Button Service
- 
+
 
 #ifndef BLE_LBS_ENABLED
 #define BLE_LBS_ENABLED 0
 #endif
 
 //  BLE_LLS_ENABLED  - ble_lls - Link Loss Service
- 
+
 
 #ifndef BLE_LLS_ENABLED
 #define BLE_LLS_ENABLED 0
 #endif
 
 //  BLE_NUS_C_ENABLED  - ble_nus_c - Nordic UART Central Service
- 
+
 
 #ifndef BLE_NUS_C_ENABLED
 #define BLE_NUS_C_ENABLED 0
@@ -420,44 +420,44 @@
 #define BLE_NUS_CONFIG_LOG_ENABLED 0
 #endif
 //  BLE_NUS_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef BLE_NUS_CONFIG_LOG_LEVEL
 #define BLE_NUS_CONFIG_LOG_LEVEL 3
 #endif
 
 //  BLE_NUS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef BLE_NUS_CONFIG_INFO_COLOR
 #define BLE_NUS_CONFIG_INFO_COLOR 0
 #endif
 
 //  BLE_NUS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef BLE_NUS_CONFIG_DEBUG_COLOR
 #define BLE_NUS_CONFIG_DEBUG_COLOR 0
@@ -468,30 +468,30 @@
 // 
 
 //  BLE_RSCS_C_ENABLED  - ble_rscs_c - Running Speed and Cadence Client
- 
+
 
 #ifndef BLE_RSCS_C_ENABLED
 #define BLE_RSCS_C_ENABLED 0
 #endif
 
 //  BLE_RSCS_ENABLED  - ble_rscs - Running Speed and Cadence Service
- 
+
 
 #ifndef BLE_RSCS_ENABLED
 #define BLE_RSCS_ENABLED 0
 #endif
 
 //  BLE_TPS_ENABLED  - ble_tps - TX Power Service
- 
+
 
 #ifndef BLE_TPS_ENABLED
 #define BLE_TPS_ENABLED 0
 #endif
 
-//  
+// 
 //==========================================================
 
-//  nRF_Core 
+//  nRF_Core
 
 //==========================================================
 //  NRF_MPU_LIB_ENABLED - nrf_mpu_lib - Module for MPU
@@ -500,7 +500,7 @@
 #define NRF_MPU_LIB_ENABLED 0
 #endif
 //  NRF_MPU_LIB_CLI_CMDS  - Enable CLI commands specific to the module.
- 
+
 
 #ifndef NRF_MPU_LIB_CLI_CMDS
 #define NRF_MPU_LIB_CLI_CMDS 0
@@ -514,15 +514,15 @@
 #define NRF_STACK_GUARD_ENABLED 0
 #endif
 //  NRF_STACK_GUARD_CONFIG_SIZE  - Size of the stack guard.
- 
-// <5=> 32 bytes 
-// <6=> 64 bytes 
-// <7=> 128 bytes 
-// <8=> 256 bytes 
-// <9=> 512 bytes 
-// <10=> 1024 bytes 
-// <11=> 2048 bytes 
-// <12=> 4096 bytes 
+
+// <5=> 32 bytes
+// <6=> 64 bytes
+// <7=> 128 bytes
+// <8=> 256 bytes
+// <9=> 512 bytes
+// <10=> 1024 bytes
+// <11=> 2048 bytes
+// <12=> 4096 bytes
 
 #ifndef NRF_STACK_GUARD_CONFIG_SIZE
 #define NRF_STACK_GUARD_CONFIG_SIZE 7
@@ -530,10 +530,10 @@
 
 // 
 
-//  
+// 
 //==========================================================
 
-//  nRF_Crypto 
+//  nRF_Crypto
 
 //==========================================================
 //  NRF_CRYPTO_ENABLED - nrf_crypto - Cryptography library.
@@ -542,14 +542,14 @@
 #define NRF_CRYPTO_ENABLED 1
 #endif
 //  NRF_CRYPTO_ALLOCATOR  - Memory allocator
- 
+
 
 //  Choose memory allocator used by nrf_crypto. Default is alloca if possible or nrf_malloc otherwise. If 'User macros' are selected, the user has to create 'nrf_crypto_allocator.h' file that contains NRF_CRYPTO_ALLOC, NRF_CRYPTO_FREE, and NRF_CRYPTO_ALLOC_ON_STACK.
-// <0=> Default 
-// <1=> User macros 
-// <2=> On stack (alloca) 
-// <3=> C dynamic memory (malloc) 
-// <4=> SDK Memory Manager (nrf_malloc) 
+// <0=> Default
+// <1=> User macros
+// <2=> On stack (alloca)
+// <3=> C dynamic memory (malloc)
+// <4=> SDK Memory Manager (nrf_malloc)
 
 #ifndef NRF_CRYPTO_ALLOCATOR
 #define NRF_CRYPTO_ALLOCATOR 0
@@ -563,21 +563,21 @@
 #define NRF_CRYPTO_BACKEND_CC310_BL_ENABLED 0
 #endif
 //  NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP224R1_ENABLED  - Enable the secp224r1 elliptic curve support using CC310_BL.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP224R1_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP224R1_ENABLED 0
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP256R1_ENABLED  - Enable the secp256r1 elliptic curve support using CC310_BL.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP256R1_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP256R1_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_BL_HASH_SHA256_ENABLED  - CC310_BL SHA-256 hash functionality.
- 
+
 
 //  CC310_BL backend implementation for hardware-accelerated SHA-256.
 
@@ -586,7 +586,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_ENABLED  - nrf_cc310_bl buffers to RAM before running hash operation
- 
+
 
 //  Enabling this makes hashing of addresses in FLASH range possible. Size of buffer allocated for hashing is set by NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE
 
@@ -594,7 +594,7 @@
 #define NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_ENABLED 0
 #endif
 
-//  NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE - nrf_cc310_bl hash outputs digests in little endian 
+//  NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE - nrf_cc310_bl hash outputs digests in little endian
 //  Makes the nrf_cc310_bl hash functions output digests in little endian format. Only for use in nRF SDK DFU!
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE
@@ -602,7 +602,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_BL_INTERRUPTS_ENABLED  - Enable Interrupts while support using CC310 bl.
- 
+
 
 //  Select a library version compatible with the configuration. When interrupts are disable, a version named _noint must be used
 
@@ -620,154 +620,154 @@
 #define NRF_CRYPTO_BACKEND_CC310_ENABLED 0
 #endif
 //  NRF_CRYPTO_BACKEND_CC310_AES_CBC_ENABLED  - Enable the AES CBC mode using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_AES_CBC_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_AES_CBC_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_AES_CTR_ENABLED  - Enable the AES CTR mode using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_AES_CTR_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_AES_CTR_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_AES_ECB_ENABLED  - Enable the AES ECB mode using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_AES_ECB_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_AES_ECB_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_AES_CBC_MAC_ENABLED  - Enable the AES CBC_MAC mode using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_AES_CBC_MAC_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_AES_CBC_MAC_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_AES_CMAC_ENABLED  - Enable the AES CMAC mode using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_AES_CMAC_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_AES_CMAC_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_AES_CCM_ENABLED  - Enable the AES CCM mode using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_AES_CCM_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_AES_CCM_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_AES_CCM_STAR_ENABLED  - Enable the AES CCM* mode using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_AES_CCM_STAR_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_AES_CCM_STAR_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_CHACHA_POLY_ENABLED  - Enable the CHACHA-POLY mode using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_CHACHA_POLY_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_CHACHA_POLY_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R1_ENABLED  - Enable the secp160r1 elliptic curve support using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R1_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R1_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R2_ENABLED  - Enable the secp160r2 elliptic curve support using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R2_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R2_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_ECC_SECP192R1_ENABLED  - Enable the secp192r1 elliptic curve support using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP192R1_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_ECC_SECP192R1_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_ECC_SECP224R1_ENABLED  - Enable the secp224r1 elliptic curve support using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP224R1_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_ECC_SECP224R1_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_ECC_SECP256R1_ENABLED  - Enable the secp256r1 elliptic curve support using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP256R1_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_ECC_SECP256R1_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_ECC_SECP384R1_ENABLED  - Enable the secp384r1 elliptic curve support using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP384R1_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_ECC_SECP384R1_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_ECC_SECP521R1_ENABLED  - Enable the secp521r1 elliptic curve support using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP521R1_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_ECC_SECP521R1_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_ECC_SECP160K1_ENABLED  - Enable the secp160k1 elliptic curve support using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP160K1_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160K1_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_ECC_SECP192K1_ENABLED  - Enable the secp192k1 elliptic curve support using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP192K1_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_ECC_SECP192K1_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_ECC_SECP224K1_ENABLED  - Enable the secp224k1 elliptic curve support using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP224K1_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_ECC_SECP224K1_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_ECC_SECP256K1_ENABLED  - Enable the secp256k1 elliptic curve support using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP256K1_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_ECC_SECP256K1_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_ECC_CURVE25519_ENABLED  - Enable the Curve25519 curve support using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_ECC_CURVE25519_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_ECC_CURVE25519_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_ECC_ED25519_ENABLED  - Enable the Ed25519 curve support using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_ECC_ED25519_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_ECC_ED25519_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_HASH_SHA256_ENABLED  - CC310 SHA-256 hash functionality.
- 
+
 
 //  CC310 backend implementation for hardware-accelerated SHA-256.
 
@@ -776,7 +776,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_HASH_SHA512_ENABLED  - CC310 SHA-512 hash functionality
- 
+
 
 //  CC310 backend implementation for SHA-512 (in software).
 
@@ -785,7 +785,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_HMAC_SHA256_ENABLED  - CC310 HMAC using SHA-256
- 
+
 
 //  CC310 backend implementation for HMAC using hardware-accelerated SHA-256.
 
@@ -794,7 +794,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_HMAC_SHA512_ENABLED  - CC310 HMAC using SHA-512
- 
+
 
 //  CC310 backend implementation for HMAC using SHA-512 (in software).
 
@@ -803,14 +803,14 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_RNG_ENABLED  - Enable RNG support using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_RNG_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_RNG_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_INTERRUPTS_ENABLED  - Enable Interrupts while support using CC310.
- 
+
 
 //  Select a library version compatible with the configuration. When interrupts are disable, a version named _noint must be used
 
@@ -826,7 +826,7 @@
 #define NRF_CRYPTO_BACKEND_CIFRA_ENABLED 0
 #endif
 //  NRF_CRYPTO_BACKEND_CIFRA_AES_EAX_ENABLED  - Enable the AES EAX mode using Cifra.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CIFRA_AES_EAX_ENABLED
 #define NRF_CRYPTO_BACKEND_CIFRA_AES_EAX_ENABLED 1
@@ -840,63 +840,63 @@
 #define NRF_CRYPTO_BACKEND_MBEDTLS_ENABLED 0
 #endif
 //  NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_ENABLED  - Enable the AES CBC mode mbed TLS.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_ENABLED
 #define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_AES_CTR_ENABLED  - Enable the AES CTR mode using mbed TLS.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CTR_ENABLED
 #define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CTR_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_AES_CFB_ENABLED  - Enable the AES CFB mode using mbed TLS.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CFB_ENABLED
 #define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CFB_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_AES_ECB_ENABLED  - Enable the AES ECB mode using mbed TLS.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_ECB_ENABLED
 #define NRF_CRYPTO_BACKEND_MBEDTLS_AES_ECB_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_MAC_ENABLED  - Enable the AES CBC MAC mode using mbed TLS.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_MAC_ENABLED
 #define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_MAC_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_AES_CMAC_ENABLED  - Enable the AES CMAC mode using mbed TLS.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CMAC_ENABLED
 #define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CMAC_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_AES_CCM_ENABLED  - Enable the AES CCM mode using mbed TLS.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CCM_ENABLED
 #define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CCM_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_AES_GCM_ENABLED  - Enable the AES GCM mode using mbed TLS.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_GCM_ENABLED
 #define NRF_CRYPTO_BACKEND_MBEDTLS_AES_GCM_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192R1_ENABLED  - Enable secp192r1 (NIST 192-bit) curve
- 
+
 
 //  Enable this setting if you need secp192r1 (NIST 192-bit) support using MBEDTLS
 
@@ -905,7 +905,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224R1_ENABLED  - Enable secp224r1 (NIST 224-bit) curve
- 
+
 
 //  Enable this setting if you need secp224r1 (NIST 224-bit) support using MBEDTLS
 
@@ -914,7 +914,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256R1_ENABLED  - Enable secp256r1 (NIST 256-bit) curve
- 
+
 
 //  Enable this setting if you need secp256r1 (NIST 256-bit) support using MBEDTLS
 
@@ -923,7 +923,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP384R1_ENABLED  - Enable secp384r1 (NIST 384-bit) curve
- 
+
 
 //  Enable this setting if you need secp384r1 (NIST 384-bit) support using MBEDTLS
 
@@ -932,7 +932,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP521R1_ENABLED  - Enable secp521r1 (NIST 521-bit) curve
- 
+
 
 //  Enable this setting if you need secp521r1 (NIST 521-bit) support using MBEDTLS
 
@@ -941,7 +941,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192K1_ENABLED  - Enable secp192k1 (Koblitz 192-bit) curve
- 
+
 
 //  Enable this setting if you need secp192k1 (Koblitz 192-bit) support using MBEDTLS
 
@@ -950,7 +950,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224K1_ENABLED  - Enable secp224k1 (Koblitz 224-bit) curve
- 
+
 
 //  Enable this setting if you need secp224k1 (Koblitz 224-bit) support using MBEDTLS
 
@@ -959,7 +959,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256K1_ENABLED  - Enable secp256k1 (Koblitz 256-bit) curve
- 
+
 
 //  Enable this setting if you need secp256k1 (Koblitz 256-bit) support using MBEDTLS
 
@@ -968,7 +968,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP256R1_ENABLED  - Enable bp256r1 (Brainpool 256-bit) curve
- 
+
 
 //  Enable this setting if you need bp256r1 (Brainpool 256-bit) support using MBEDTLS
 
@@ -977,7 +977,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP384R1_ENABLED  - Enable bp384r1 (Brainpool 384-bit) curve
- 
+
 
 //  Enable this setting if you need bp384r1 (Brainpool 384-bit) support using MBEDTLS
 
@@ -986,7 +986,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP512R1_ENABLED  - Enable bp512r1 (Brainpool 512-bit) curve
- 
+
 
 //  Enable this setting if you need bp512r1 (Brainpool 512-bit) support using MBEDTLS
 
@@ -995,7 +995,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_CURVE25519_ENABLED  - Enable Curve25519 curve
- 
+
 
 //  Enable this setting if you need Curve25519 support using MBEDTLS
 
@@ -1004,7 +1004,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA256_ENABLED  - Enable mbed TLS SHA-256 hash functionality.
- 
+
 
 //  mbed TLS backend implementation for SHA-256.
 
@@ -1013,7 +1013,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA512_ENABLED  - Enable mbed TLS SHA-512 hash functionality.
- 
+
 
 //  mbed TLS backend implementation for SHA-512.
 
@@ -1022,7 +1022,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA256_ENABLED  - Enable mbed TLS HMAC using SHA-256.
- 
+
 
 //  mbed TLS backend implementation for HMAC using SHA-256.
 
@@ -1031,7 +1031,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA512_ENABLED  - Enable mbed TLS HMAC using SHA-512.
- 
+
 
 //  mbed TLS backend implementation for HMAC using SHA-512.
 
@@ -1047,7 +1047,7 @@
 #define NRF_CRYPTO_BACKEND_MICRO_ECC_ENABLED 0
 #endif
 //  NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP192R1_ENABLED  - Enable secp192r1 (NIST 192-bit) curve
- 
+
 
 //  Enable this setting if you need secp192r1 (NIST 192-bit) support using micro-ecc
 
@@ -1056,7 +1056,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP224R1_ENABLED  - Enable secp224r1 (NIST 224-bit) curve
- 
+
 
 //  Enable this setting if you need secp224r1 (NIST 224-bit) support using micro-ecc
 
@@ -1065,7 +1065,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256R1_ENABLED  - Enable secp256r1 (NIST 256-bit) curve
- 
+
 
 //  Enable this setting if you need secp256r1 (NIST 256-bit) support using micro-ecc
 
@@ -1074,7 +1074,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256K1_ENABLED  - Enable secp256k1 (Koblitz 256-bit) curve
- 
+
 
 //  Enable this setting if you need secp256k1 (Koblitz 256-bit) support using micro-ecc
 
@@ -1092,7 +1092,7 @@
 #define NRF_CRYPTO_BACKEND_NRF_HW_RNG_ENABLED 0
 #endif
 //  NRF_CRYPTO_BACKEND_NRF_HW_RNG_MBEDTLS_CTR_DRBG_ENABLED  - Enable mbed TLS CTR-DRBG algorithm.
- 
+
 
 //  Enable mbed TLS CTR-DRBG standardized by NIST (NIST SP 800-90A Rev. 1). The nRF HW RNG is used as an entropy source for seeding.
 
@@ -1110,7 +1110,7 @@
 #define NRF_CRYPTO_BACKEND_NRF_SW_ENABLED 0
 #endif
 //  NRF_CRYPTO_BACKEND_NRF_SW_HASH_SHA256_ENABLED  - nRF SW hash backend support for SHA-256
- 
+
 
 //  The nRF SW backend provide access to nRF SDK legacy hash implementation of SHA-256.
 
@@ -1128,14 +1128,14 @@
 #define NRF_CRYPTO_BACKEND_OBERON_ENABLED 0
 #endif
 //  NRF_CRYPTO_BACKEND_OBERON_CHACHA_POLY_ENABLED  - Enable the CHACHA-POLY mode using Oberon.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_OBERON_CHACHA_POLY_ENABLED
 #define NRF_CRYPTO_BACKEND_OBERON_CHACHA_POLY_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_OBERON_ECC_SECP256R1_ENABLED  - Enable secp256r1 curve
- 
+
 
 //  Enable this setting if you need secp256r1 curve support using Oberon library
 
@@ -1144,7 +1144,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_OBERON_ECC_CURVE25519_ENABLED  - Enable Curve25519 ECDH
- 
+
 
 //  Enable this setting if you need Curve25519 ECDH support using Oberon library
 
@@ -1153,7 +1153,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_OBERON_ECC_ED25519_ENABLED  - Enable Ed25519 signature scheme
- 
+
 
 //  Enable this setting if you need Ed25519 support using Oberon library
 
@@ -1162,7 +1162,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_OBERON_HASH_SHA256_ENABLED  - Oberon SHA-256 hash functionality
- 
+
 
 //  Oberon backend implementation for SHA-256.
 
@@ -1171,7 +1171,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_OBERON_HASH_SHA512_ENABLED  - Oberon SHA-512 hash functionality
- 
+
 
 //  Oberon backend implementation for SHA-512.
 
@@ -1180,7 +1180,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA256_ENABLED  - Oberon HMAC using SHA-256
- 
+
 
 //  Oberon backend implementation for HMAC using SHA-256.
 
@@ -1189,7 +1189,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA512_ENABLED  - Oberon HMAC using SHA-512
- 
+
 
 //  Oberon backend implementation for HMAC using SHA-512.
 
@@ -1207,7 +1207,7 @@
 #define NRF_CRYPTO_BACKEND_OPTIGA_ENABLED 0
 #endif
 //  NRF_CRYPTO_BACKEND_OPTIGA_RNG_ENABLED  - Optiga backend support for RNG
- 
+
 
 //  The Optiga backend provide external chip RNG.
 
@@ -1216,7 +1216,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_OPTIGA_ECC_SECP256R1_ENABLED  - Optiga backend support for ECC secp256r1
- 
+
 
 //  The Optiga backend provide external chip ECC using secp256r1.
 
@@ -1227,7 +1227,7 @@
 // 
 
 //  NRF_CRYPTO_CURVE25519_BIG_ENDIAN_ENABLED  - Big-endian byte order in raw Curve25519 data
- 
+
 
 //  Enable big-endian byte order in Curve25519 API, if set to 1. Use little-endian, if set to 0.
 
@@ -1237,36 +1237,36 @@
 
 // 
 
-//  
+// 
 //==========================================================
 
-//  nRF_DFU 
+//  nRF_DFU
 
 //==========================================================
 //  ble_dfu - Device Firmware Update
 
 //==========================================================
 //  BLE_DFU_ENABLED  - Enable DFU Service.
- 
+
 
 #ifndef BLE_DFU_ENABLED
 #define BLE_DFU_ENABLED 0
 #endif
 
 //  NRF_DFU_BLE_BUTTONLESS_SUPPORTS_BONDS  - Buttonless DFU supports bonds.
- 
+
 
 #ifndef NRF_DFU_BLE_BUTTONLESS_SUPPORTS_BONDS
 #define NRF_DFU_BLE_BUTTONLESS_SUPPORTS_BONDS 0
 #endif
 
-//  
+// 
 //==========================================================
 
-//  
+// 
 //==========================================================
 
-//  nRF_Drivers 
+//  nRF_Drivers
 
 //==========================================================
 //  COMP_ENABLED - nrf_drv_comp - COMP peripheral driver - legacy layer
@@ -1275,83 +1275,83 @@
 #define COMP_ENABLED 0
 #endif
 //  COMP_CONFIG_REF  - Reference voltage
- 
-// <0=> Internal 1.2V 
-// <1=> Internal 1.8V 
-// <2=> Internal 2.4V 
-// <4=> VDD 
-// <7=> ARef 
+
+// <0=> Internal 1.2V
+// <1=> Internal 1.8V
+// <2=> Internal 2.4V
+// <4=> VDD
+// <7=> ARef
 
 #ifndef COMP_CONFIG_REF
 #define COMP_CONFIG_REF 1
 #endif
 
 //  COMP_CONFIG_MAIN_MODE  - Main mode
- 
-// <0=> Single ended 
-// <1=> Differential 
+
+// <0=> Single ended
+// <1=> Differential
 
 #ifndef COMP_CONFIG_MAIN_MODE
 #define COMP_CONFIG_MAIN_MODE 0
 #endif
 
 //  COMP_CONFIG_SPEED_MODE  - Speed mode
- 
-// <0=> Low power 
-// <1=> Normal 
-// <2=> High speed 
+
+// <0=> Low power
+// <1=> Normal
+// <2=> High speed
 
 #ifndef COMP_CONFIG_SPEED_MODE
 #define COMP_CONFIG_SPEED_MODE 2
 #endif
 
 //  COMP_CONFIG_HYST  - Hystheresis
- 
-// <0=> No 
-// <1=> 50mV 
+
+// <0=> No
+// <1=> 50mV
 
 #ifndef COMP_CONFIG_HYST
 #define COMP_CONFIG_HYST 0
 #endif
 
 //  COMP_CONFIG_ISOURCE  - Current Source
- 
-// <0=> Off 
-// <1=> 2.5 uA 
-// <2=> 5 uA 
-// <3=> 10 uA 
+
+// <0=> Off
+// <1=> 2.5 uA
+// <2=> 5 uA
+// <3=> 10 uA
 
 #ifndef COMP_CONFIG_ISOURCE
 #define COMP_CONFIG_ISOURCE 0
 #endif
 
 //  COMP_CONFIG_INPUT  - Analog input
- 
-// <0=> 0 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef COMP_CONFIG_INPUT
 #define COMP_CONFIG_INPUT 0
 #endif
 
 //  COMP_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef COMP_CONFIG_IRQ_PRIORITY
 #define COMP_CONFIG_IRQ_PRIORITY 6
@@ -1360,7 +1360,7 @@
 // 
 
 //  EGU_ENABLED  - nrf_drv_swi - SWI(EGU) peripheral driver - legacy layer
- 
+
 
 #ifndef EGU_ENABLED
 #define EGU_ENABLED 0
@@ -1371,23 +1371,23 @@
 #ifndef GPIOTE_ENABLED
 #define GPIOTE_ENABLED 0
 #endif
-//  GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins 
+//  GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins
 #ifndef GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS
 #define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1
 #endif
 
 //  GPIOTE_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef GPIOTE_CONFIG_IRQ_PRIORITY
 #define GPIOTE_CONFIG_IRQ_PRIORITY 6
@@ -1400,33 +1400,33 @@
 #ifndef I2S_ENABLED
 #define I2S_ENABLED 0
 #endif
-//  I2S_CONFIG_SCK_PIN - SCK pin  <0-31> 
+//  I2S_CONFIG_SCK_PIN - SCK pin  <0-31>
 
 
 #ifndef I2S_CONFIG_SCK_PIN
 #define I2S_CONFIG_SCK_PIN 31
 #endif
 
-//  I2S_CONFIG_LRCK_PIN - LRCK pin  <1-31> 
+//  I2S_CONFIG_LRCK_PIN - LRCK pin  <1-31>
 
 
 #ifndef I2S_CONFIG_LRCK_PIN
 #define I2S_CONFIG_LRCK_PIN 30
 #endif
 
-//  I2S_CONFIG_MCK_PIN - MCK pin 
+//  I2S_CONFIG_MCK_PIN - MCK pin
 #ifndef I2S_CONFIG_MCK_PIN
 #define I2S_CONFIG_MCK_PIN 255
 #endif
 
-//  I2S_CONFIG_SDOUT_PIN - SDOUT pin  <0-31> 
+//  I2S_CONFIG_SDOUT_PIN - SDOUT pin  <0-31>
 
 
 #ifndef I2S_CONFIG_SDOUT_PIN
 #define I2S_CONFIG_SDOUT_PIN 29
 #endif
 
-//  I2S_CONFIG_SDIN_PIN - SDIN pin  <0-31> 
+//  I2S_CONFIG_SDIN_PIN - SDIN pin  <0-31>
 
 
 #ifndef I2S_CONFIG_SDIN_PIN
@@ -1434,106 +1434,106 @@
 #endif
 
 //  I2S_CONFIG_MASTER  - Mode
- 
-// <0=> Master 
-// <1=> Slave 
+
+// <0=> Master
+// <1=> Slave
 
 #ifndef I2S_CONFIG_MASTER
 #define I2S_CONFIG_MASTER 0
 #endif
 
 //  I2S_CONFIG_FORMAT  - Format
- 
-// <0=> I2S 
-// <1=> Aligned 
+
+// <0=> I2S
+// <1=> Aligned
 
 #ifndef I2S_CONFIG_FORMAT
 #define I2S_CONFIG_FORMAT 0
 #endif
 
 //  I2S_CONFIG_ALIGN  - Alignment
- 
-// <0=> Left 
-// <1=> Right 
+
+// <0=> Left
+// <1=> Right
 
 #ifndef I2S_CONFIG_ALIGN
 #define I2S_CONFIG_ALIGN 0
 #endif
 
 //  I2S_CONFIG_SWIDTH  - Sample width (bits)
- 
-// <0=> 8 
-// <1=> 16 
-// <2=> 24 
+
+// <0=> 8
+// <1=> 16
+// <2=> 24
 
 #ifndef I2S_CONFIG_SWIDTH
 #define I2S_CONFIG_SWIDTH 1
 #endif
 
 //  I2S_CONFIG_CHANNELS  - Channels
- 
-// <0=> Stereo 
-// <1=> Left 
-// <2=> Right 
+
+// <0=> Stereo
+// <1=> Left
+// <2=> Right
 
 #ifndef I2S_CONFIG_CHANNELS
 #define I2S_CONFIG_CHANNELS 1
 #endif
 
 //  I2S_CONFIG_MCK_SETUP  - MCK behavior
- 
-// <0=> Disabled 
-// <2147483648=> 32MHz/2 
-// <1342177280=> 32MHz/3 
-// <1073741824=> 32MHz/4 
-// <805306368=> 32MHz/5 
-// <671088640=> 32MHz/6 
-// <536870912=> 32MHz/8 
-// <402653184=> 32MHz/10 
-// <369098752=> 32MHz/11 
-// <285212672=> 32MHz/15 
-// <268435456=> 32MHz/16 
-// <201326592=> 32MHz/21 
-// <184549376=> 32MHz/23 
-// <142606336=> 32MHz/30 
-// <138412032=> 32MHz/31 
-// <134217728=> 32MHz/32 
-// <100663296=> 32MHz/42 
-// <68157440=> 32MHz/63 
-// <34340864=> 32MHz/125 
+
+// <0=> Disabled
+// <2147483648=> 32MHz/2
+// <1342177280=> 32MHz/3
+// <1073741824=> 32MHz/4
+// <805306368=> 32MHz/5
+// <671088640=> 32MHz/6
+// <536870912=> 32MHz/8
+// <402653184=> 32MHz/10
+// <369098752=> 32MHz/11
+// <285212672=> 32MHz/15
+// <268435456=> 32MHz/16
+// <201326592=> 32MHz/21
+// <184549376=> 32MHz/23
+// <142606336=> 32MHz/30
+// <138412032=> 32MHz/31
+// <134217728=> 32MHz/32
+// <100663296=> 32MHz/42
+// <68157440=> 32MHz/63
+// <34340864=> 32MHz/125
 
 #ifndef I2S_CONFIG_MCK_SETUP
 #define I2S_CONFIG_MCK_SETUP 536870912
 #endif
 
 //  I2S_CONFIG_RATIO  - MCK/LRCK ratio
- 
-// <0=> 32x 
-// <1=> 48x 
-// <2=> 64x 
-// <3=> 96x 
-// <4=> 128x 
-// <5=> 192x 
-// <6=> 256x 
-// <7=> 384x 
-// <8=> 512x 
+
+// <0=> 32x
+// <1=> 48x
+// <2=> 64x
+// <3=> 96x
+// <4=> 128x
+// <5=> 192x
+// <6=> 256x
+// <7=> 384x
+// <8=> 512x
 
 #ifndef I2S_CONFIG_RATIO
 #define I2S_CONFIG_RATIO 2000
 #endif
 
 //  I2S_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef I2S_CONFIG_IRQ_PRIORITY
 #define I2S_CONFIG_IRQ_PRIORITY 6
@@ -1545,44 +1545,44 @@
 #define I2S_CONFIG_LOG_ENABLED 0
 #endif
 //  I2S_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef I2S_CONFIG_LOG_LEVEL
 #define I2S_CONFIG_LOG_LEVEL 3
 #endif
 
 //  I2S_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef I2S_CONFIG_INFO_COLOR
 #define I2S_CONFIG_INFO_COLOR 0
 #endif
 
 //  I2S_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef I2S_CONFIG_DEBUG_COLOR
 #define I2S_CONFIG_DEBUG_COLOR 0
@@ -1598,73 +1598,73 @@
 #define LPCOMP_ENABLED 0
 #endif
 //  LPCOMP_CONFIG_REFERENCE  - Reference voltage
- 
-// <0=> Supply 1/8 
-// <1=> Supply 2/8 
-// <2=> Supply 3/8 
-// <3=> Supply 4/8 
-// <4=> Supply 5/8 
-// <5=> Supply 6/8 
-// <6=> Supply 7/8 
-// <8=> Supply 1/16 (nRF52) 
-// <9=> Supply 3/16 (nRF52) 
-// <10=> Supply 5/16 (nRF52) 
-// <11=> Supply 7/16 (nRF52) 
-// <12=> Supply 9/16 (nRF52) 
-// <13=> Supply 11/16 (nRF52) 
-// <14=> Supply 13/16 (nRF52) 
-// <15=> Supply 15/16 (nRF52) 
-// <7=> External Ref 0 
-// <65543=> External Ref 1 
+
+// <0=> Supply 1/8
+// <1=> Supply 2/8
+// <2=> Supply 3/8
+// <3=> Supply 4/8
+// <4=> Supply 5/8
+// <5=> Supply 6/8
+// <6=> Supply 7/8
+// <8=> Supply 1/16 (nRF52)
+// <9=> Supply 3/16 (nRF52)
+// <10=> Supply 5/16 (nRF52)
+// <11=> Supply 7/16 (nRF52)
+// <12=> Supply 9/16 (nRF52)
+// <13=> Supply 11/16 (nRF52)
+// <14=> Supply 13/16 (nRF52)
+// <15=> Supply 15/16 (nRF52)
+// <7=> External Ref 0
+// <65543=> External Ref 1
 
 #ifndef LPCOMP_CONFIG_REFERENCE
 #define LPCOMP_CONFIG_REFERENCE 3
 #endif
 
 //  LPCOMP_CONFIG_DETECTION  - Detection
- 
-// <0=> Crossing 
-// <1=> Up 
-// <2=> Down 
+
+// <0=> Crossing
+// <1=> Up
+// <2=> Down
 
 #ifndef LPCOMP_CONFIG_DETECTION
 #define LPCOMP_CONFIG_DETECTION 2
 #endif
 
 //  LPCOMP_CONFIG_INPUT  - Analog input
- 
-// <0=> 0 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef LPCOMP_CONFIG_INPUT
 #define LPCOMP_CONFIG_INPUT 0
 #endif
 
 //  LPCOMP_CONFIG_HYST  - Hysteresis
- 
+
 
 #ifndef LPCOMP_CONFIG_HYST
 #define LPCOMP_CONFIG_HYST 0
 #endif
 
 //  LPCOMP_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef LPCOMP_CONFIG_IRQ_PRIORITY
 #define LPCOMP_CONFIG_IRQ_PRIORITY 6
@@ -1678,27 +1678,27 @@
 #define NRFX_CLOCK_ENABLED 0
 #endif
 //  NRFX_CLOCK_CONFIG_LF_SRC  - LF Clock Source
- 
-// <0=> RC 
-// <1=> XTAL 
-// <2=> Synth 
-// <131073=> External Low Swing 
-// <196609=> External Full Swing 
+
+// <0=> RC
+// <1=> XTAL
+// <2=> Synth
+// <131073=> External Low Swing
+// <196609=> External Full Swing
 
 #ifndef NRFX_CLOCK_CONFIG_LF_SRC
 #define NRFX_CLOCK_CONFIG_LF_SRC 1
 #endif
 
 //  NRFX_CLOCK_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_CLOCK_CONFIG_IRQ_PRIORITY
 #define NRFX_CLOCK_CONFIG_IRQ_PRIORITY 6
@@ -1710,44 +1710,44 @@
 #define NRFX_CLOCK_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_CLOCK_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_CLOCK_CONFIG_LOG_LEVEL
 #define NRFX_CLOCK_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_CLOCK_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_CLOCK_CONFIG_INFO_COLOR
 #define NRFX_CLOCK_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_CLOCK_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_CLOCK_CONFIG_DEBUG_COLOR
 #define NRFX_CLOCK_CONFIG_DEBUG_COLOR 0
@@ -1763,81 +1763,81 @@
 #define NRFX_COMP_ENABLED 0
 #endif
 //  NRFX_COMP_CONFIG_REF  - Reference voltage
- 
-// <0=> Internal 1.2V 
-// <1=> Internal 1.8V 
-// <2=> Internal 2.4V 
-// <4=> VDD 
-// <7=> ARef 
+
+// <0=> Internal 1.2V
+// <1=> Internal 1.8V
+// <2=> Internal 2.4V
+// <4=> VDD
+// <7=> ARef
 
 #ifndef NRFX_COMP_CONFIG_REF
 #define NRFX_COMP_CONFIG_REF 1
 #endif
 
 //  NRFX_COMP_CONFIG_MAIN_MODE  - Main mode
- 
-// <0=> Single ended 
-// <1=> Differential 
+
+// <0=> Single ended
+// <1=> Differential
 
 #ifndef NRFX_COMP_CONFIG_MAIN_MODE
 #define NRFX_COMP_CONFIG_MAIN_MODE 0
 #endif
 
 //  NRFX_COMP_CONFIG_SPEED_MODE  - Speed mode
- 
-// <0=> Low power 
-// <1=> Normal 
-// <2=> High speed 
+
+// <0=> Low power
+// <1=> Normal
+// <2=> High speed
 
 #ifndef NRFX_COMP_CONFIG_SPEED_MODE
 #define NRFX_COMP_CONFIG_SPEED_MODE 2
 #endif
 
 //  NRFX_COMP_CONFIG_HYST  - Hystheresis
- 
-// <0=> No 
-// <1=> 50mV 
+
+// <0=> No
+// <1=> 50mV
 
 #ifndef NRFX_COMP_CONFIG_HYST
 #define NRFX_COMP_CONFIG_HYST 0
 #endif
 
 //  NRFX_COMP_CONFIG_ISOURCE  - Current Source
- 
-// <0=> Off 
-// <1=> 2.5 uA 
-// <2=> 5 uA 
-// <3=> 10 uA 
+
+// <0=> Off
+// <1=> 2.5 uA
+// <2=> 5 uA
+// <3=> 10 uA
 
 #ifndef NRFX_COMP_CONFIG_ISOURCE
 #define NRFX_COMP_CONFIG_ISOURCE 0
 #endif
 
 //  NRFX_COMP_CONFIG_INPUT  - Analog input
- 
-// <0=> 0 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_COMP_CONFIG_INPUT
 #define NRFX_COMP_CONFIG_INPUT 0
 #endif
 
 //  NRFX_COMP_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_COMP_CONFIG_IRQ_PRIORITY
 #define NRFX_COMP_CONFIG_IRQ_PRIORITY 6
@@ -1849,44 +1849,44 @@
 #define NRFX_COMP_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_COMP_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_COMP_CONFIG_LOG_LEVEL
 #define NRFX_COMP_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_COMP_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_COMP_CONFIG_INFO_COLOR
 #define NRFX_COMP_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_COMP_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_COMP_CONFIG_DEBUG_COLOR
 #define NRFX_COMP_CONFIG_DEBUG_COLOR 0
@@ -1901,21 +1901,21 @@
 #ifndef NRFX_GPIOTE_ENABLED
 #define NRFX_GPIOTE_ENABLED 0
 #endif
-//  NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins 
+//  NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins
 #ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS
 #define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1
 #endif
 
 //  NRFX_GPIOTE_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_GPIOTE_CONFIG_IRQ_PRIORITY
 #define NRFX_GPIOTE_CONFIG_IRQ_PRIORITY 6
@@ -1927,44 +1927,44 @@
 #define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_GPIOTE_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL
 #define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_GPIOTE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_GPIOTE_CONFIG_INFO_COLOR
 #define NRFX_GPIOTE_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_GPIOTE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_GPIOTE_CONFIG_DEBUG_COLOR
 #define NRFX_GPIOTE_CONFIG_DEBUG_COLOR 0
@@ -1979,33 +1979,33 @@
 #ifndef NRFX_I2S_ENABLED
 #define NRFX_I2S_ENABLED 0
 #endif
-//  NRFX_I2S_CONFIG_SCK_PIN - SCK pin  <0-31> 
+//  NRFX_I2S_CONFIG_SCK_PIN - SCK pin  <0-31>
 
 
 #ifndef NRFX_I2S_CONFIG_SCK_PIN
 #define NRFX_I2S_CONFIG_SCK_PIN 31
 #endif
 
-//  NRFX_I2S_CONFIG_LRCK_PIN - LRCK pin  <1-31> 
+//  NRFX_I2S_CONFIG_LRCK_PIN - LRCK pin  <1-31>
 
 
 #ifndef NRFX_I2S_CONFIG_LRCK_PIN
 #define NRFX_I2S_CONFIG_LRCK_PIN 30
 #endif
 
-//  NRFX_I2S_CONFIG_MCK_PIN - MCK pin 
+//  NRFX_I2S_CONFIG_MCK_PIN - MCK pin
 #ifndef NRFX_I2S_CONFIG_MCK_PIN
 #define NRFX_I2S_CONFIG_MCK_PIN 255
 #endif
 
-//  NRFX_I2S_CONFIG_SDOUT_PIN - SDOUT pin  <0-31> 
+//  NRFX_I2S_CONFIG_SDOUT_PIN - SDOUT pin  <0-31>
 
 
 #ifndef NRFX_I2S_CONFIG_SDOUT_PIN
 #define NRFX_I2S_CONFIG_SDOUT_PIN 29
 #endif
 
-//  NRFX_I2S_CONFIG_SDIN_PIN - SDIN pin  <0-31> 
+//  NRFX_I2S_CONFIG_SDIN_PIN - SDIN pin  <0-31>
 
 
 #ifndef NRFX_I2S_CONFIG_SDIN_PIN
@@ -2013,104 +2013,104 @@
 #endif
 
 //  NRFX_I2S_CONFIG_MASTER  - Mode
- 
-// <0=> Master 
-// <1=> Slave 
+
+// <0=> Master
+// <1=> Slave
 
 #ifndef NRFX_I2S_CONFIG_MASTER
 #define NRFX_I2S_CONFIG_MASTER 0
 #endif
 
 //  NRFX_I2S_CONFIG_FORMAT  - Format
- 
-// <0=> I2S 
-// <1=> Aligned 
+
+// <0=> I2S
+// <1=> Aligned
 
 #ifndef NRFX_I2S_CONFIG_FORMAT
 #define NRFX_I2S_CONFIG_FORMAT 0
 #endif
 
 //  NRFX_I2S_CONFIG_ALIGN  - Alignment
- 
-// <0=> Left 
-// <1=> Right 
+
+// <0=> Left
+// <1=> Right
 
 #ifndef NRFX_I2S_CONFIG_ALIGN
 #define NRFX_I2S_CONFIG_ALIGN 0
 #endif
 
 //  NRFX_I2S_CONFIG_SWIDTH  - Sample width (bits)
- 
-// <0=> 8 
-// <1=> 16 
-// <2=> 24 
+
+// <0=> 8
+// <1=> 16
+// <2=> 24
 
 #ifndef NRFX_I2S_CONFIG_SWIDTH
 #define NRFX_I2S_CONFIG_SWIDTH 1
 #endif
 
 //  NRFX_I2S_CONFIG_CHANNELS  - Channels
- 
-// <0=> Stereo 
-// <1=> Left 
-// <2=> Right 
+
+// <0=> Stereo
+// <1=> Left
+// <2=> Right
 
 #ifndef NRFX_I2S_CONFIG_CHANNELS
 #define NRFX_I2S_CONFIG_CHANNELS 1
 #endif
 
 //  NRFX_I2S_CONFIG_MCK_SETUP  - MCK behavior
- 
-// <0=> Disabled 
-// <2147483648=> 32MHz/2 
-// <1342177280=> 32MHz/3 
-// <1073741824=> 32MHz/4 
-// <805306368=> 32MHz/5 
-// <671088640=> 32MHz/6 
-// <536870912=> 32MHz/8 
-// <402653184=> 32MHz/10 
-// <369098752=> 32MHz/11 
-// <285212672=> 32MHz/15 
-// <268435456=> 32MHz/16 
-// <201326592=> 32MHz/21 
-// <184549376=> 32MHz/23 
-// <142606336=> 32MHz/30 
-// <138412032=> 32MHz/31 
-// <134217728=> 32MHz/32 
-// <100663296=> 32MHz/42 
-// <68157440=> 32MHz/63 
-// <34340864=> 32MHz/125 
+
+// <0=> Disabled
+// <2147483648=> 32MHz/2
+// <1342177280=> 32MHz/3
+// <1073741824=> 32MHz/4
+// <805306368=> 32MHz/5
+// <671088640=> 32MHz/6
+// <536870912=> 32MHz/8
+// <402653184=> 32MHz/10
+// <369098752=> 32MHz/11
+// <285212672=> 32MHz/15
+// <268435456=> 32MHz/16
+// <201326592=> 32MHz/21
+// <184549376=> 32MHz/23
+// <142606336=> 32MHz/30
+// <138412032=> 32MHz/31
+// <134217728=> 32MHz/32
+// <100663296=> 32MHz/42
+// <68157440=> 32MHz/63
+// <34340864=> 32MHz/125
 
 #ifndef NRFX_I2S_CONFIG_MCK_SETUP
 #define NRFX_I2S_CONFIG_MCK_SETUP 536870912
 #endif
 
 //  NRFX_I2S_CONFIG_RATIO  - MCK/LRCK ratio
- 
-// <0=> 32x 
-// <1=> 48x 
-// <2=> 64x 
-// <3=> 96x 
-// <4=> 128x 
-// <5=> 192x 
-// <6=> 256x 
-// <7=> 384x 
-// <8=> 512x 
+
+// <0=> 32x
+// <1=> 48x
+// <2=> 64x
+// <3=> 96x
+// <4=> 128x
+// <5=> 192x
+// <6=> 256x
+// <7=> 384x
+// <8=> 512x
 
 #ifndef NRFX_I2S_CONFIG_RATIO
 #define NRFX_I2S_CONFIG_RATIO 2000
 #endif
 
 //  NRFX_I2S_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_I2S_CONFIG_IRQ_PRIORITY
 #define NRFX_I2S_CONFIG_IRQ_PRIORITY 6
@@ -2122,44 +2122,44 @@
 #define NRFX_I2S_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_I2S_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_I2S_CONFIG_LOG_LEVEL
 #define NRFX_I2S_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_I2S_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_I2S_CONFIG_INFO_COLOR
 #define NRFX_I2S_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_I2S_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_I2S_CONFIG_DEBUG_COLOR
 #define NRFX_I2S_CONFIG_DEBUG_COLOR 0
@@ -2175,71 +2175,71 @@
 #define NRFX_LPCOMP_ENABLED 0
 #endif
 //  NRFX_LPCOMP_CONFIG_REFERENCE  - Reference voltage
- 
-// <0=> Supply 1/8 
-// <1=> Supply 2/8 
-// <2=> Supply 3/8 
-// <3=> Supply 4/8 
-// <4=> Supply 5/8 
-// <5=> Supply 6/8 
-// <6=> Supply 7/8 
-// <8=> Supply 1/16 (nRF52) 
-// <9=> Supply 3/16 (nRF52) 
-// <10=> Supply 5/16 (nRF52) 
-// <11=> Supply 7/16 (nRF52) 
-// <12=> Supply 9/16 (nRF52) 
-// <13=> Supply 11/16 (nRF52) 
-// <14=> Supply 13/16 (nRF52) 
-// <15=> Supply 15/16 (nRF52) 
-// <7=> External Ref 0 
-// <65543=> External Ref 1 
+
+// <0=> Supply 1/8
+// <1=> Supply 2/8
+// <2=> Supply 3/8
+// <3=> Supply 4/8
+// <4=> Supply 5/8
+// <5=> Supply 6/8
+// <6=> Supply 7/8
+// <8=> Supply 1/16 (nRF52)
+// <9=> Supply 3/16 (nRF52)
+// <10=> Supply 5/16 (nRF52)
+// <11=> Supply 7/16 (nRF52)
+// <12=> Supply 9/16 (nRF52)
+// <13=> Supply 11/16 (nRF52)
+// <14=> Supply 13/16 (nRF52)
+// <15=> Supply 15/16 (nRF52)
+// <7=> External Ref 0
+// <65543=> External Ref 1
 
 #ifndef NRFX_LPCOMP_CONFIG_REFERENCE
 #define NRFX_LPCOMP_CONFIG_REFERENCE 3
 #endif
 
 //  NRFX_LPCOMP_CONFIG_DETECTION  - Detection
- 
-// <0=> Crossing 
-// <1=> Up 
-// <2=> Down 
+
+// <0=> Crossing
+// <1=> Up
+// <2=> Down
 
 #ifndef NRFX_LPCOMP_CONFIG_DETECTION
 #define NRFX_LPCOMP_CONFIG_DETECTION 2
 #endif
 
 //  NRFX_LPCOMP_CONFIG_INPUT  - Analog input
- 
-// <0=> 0 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_LPCOMP_CONFIG_INPUT
 #define NRFX_LPCOMP_CONFIG_INPUT 0
 #endif
 
 //  NRFX_LPCOMP_CONFIG_HYST  - Hysteresis
- 
+
 
 #ifndef NRFX_LPCOMP_CONFIG_HYST
 #define NRFX_LPCOMP_CONFIG_HYST 0
 #endif
 
 //  NRFX_LPCOMP_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_LPCOMP_CONFIG_IRQ_PRIORITY
 #define NRFX_LPCOMP_CONFIG_IRQ_PRIORITY 6
@@ -2251,44 +2251,44 @@
 #define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_LPCOMP_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL
 #define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_LPCOMP_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_LPCOMP_CONFIG_INFO_COLOR
 #define NRFX_LPCOMP_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_LPCOMP_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_LPCOMP_CONFIG_DEBUG_COLOR
 #define NRFX_LPCOMP_CONFIG_DEBUG_COLOR 0
@@ -2304,15 +2304,15 @@
 #define NRFX_NFCT_ENABLED 0
 #endif
 //  NRFX_NFCT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_NFCT_CONFIG_IRQ_PRIORITY
 #define NRFX_NFCT_CONFIG_IRQ_PRIORITY 6
@@ -2324,44 +2324,44 @@
 #define NRFX_NFCT_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_NFCT_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_NFCT_CONFIG_LOG_LEVEL
 #define NRFX_NFCT_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_NFCT_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_NFCT_CONFIG_INFO_COLOR
 #define NRFX_NFCT_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_NFCT_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_NFCT_CONFIG_DEBUG_COLOR
 #define NRFX_NFCT_CONFIG_DEBUG_COLOR 0
@@ -2377,43 +2377,43 @@
 #define NRFX_PDM_ENABLED 0
 #endif
 //  NRFX_PDM_CONFIG_MODE  - Mode
- 
-// <0=> Stereo 
-// <1=> Mono 
+
+// <0=> Stereo
+// <1=> Mono
 
 #ifndef NRFX_PDM_CONFIG_MODE
 #define NRFX_PDM_CONFIG_MODE 1
 #endif
 
 //  NRFX_PDM_CONFIG_EDGE  - Edge
- 
-// <0=> Left falling 
-// <1=> Left rising 
+
+// <0=> Left falling
+// <1=> Left rising
 
 #ifndef NRFX_PDM_CONFIG_EDGE
 #define NRFX_PDM_CONFIG_EDGE 0
 #endif
 
 //  NRFX_PDM_CONFIG_CLOCK_FREQ  - Clock frequency
- 
-// <134217728=> 1000k 
-// <138412032=> 1032k (default) 
-// <142606336=> 1067k 
+
+// <134217728=> 1000k
+// <138412032=> 1032k (default)
+// <142606336=> 1067k
 
 #ifndef NRFX_PDM_CONFIG_CLOCK_FREQ
 #define NRFX_PDM_CONFIG_CLOCK_FREQ 138412032
 #endif
 
 //  NRFX_PDM_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_PDM_CONFIG_IRQ_PRIORITY
 #define NRFX_PDM_CONFIG_IRQ_PRIORITY 6
@@ -2425,44 +2425,44 @@
 #define NRFX_PDM_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_PDM_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_PDM_CONFIG_LOG_LEVEL
 #define NRFX_PDM_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_PDM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_PDM_CONFIG_INFO_COLOR
 #define NRFX_PDM_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_PDM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_PDM_CONFIG_DEBUG_COLOR
 #define NRFX_PDM_CONFIG_DEBUG_COLOR 0
@@ -2493,7 +2493,7 @@
 #endif
 
 //  NRFX_POWER_CONFIG_DEFAULT_DCDCEN  - The default configuration of main DCDC regulator
- 
+
 
 //  This settings means only that components for DCDC regulator are installed and it can be enabled.
 
@@ -2502,7 +2502,7 @@
 #endif
 
 //  NRFX_POWER_CONFIG_DEFAULT_DCDCENHV  - The default configuration of High Voltage DCDC regulator
- 
+
 
 //  This settings means only that components for DCDC regulator are installed and it can be enabled.
 
@@ -2523,44 +2523,44 @@
 #define NRFX_PPI_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_PPI_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_PPI_CONFIG_LOG_LEVEL
 #define NRFX_PPI_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_PPI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_PPI_CONFIG_INFO_COLOR
 #define NRFX_PPI_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_PPI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_PPI_CONFIG_DEBUG_COLOR
 #define NRFX_PPI_CONFIG_DEBUG_COLOR 0
@@ -2576,55 +2576,55 @@
 #define NRFX_PWM_ENABLED 0
 #endif
 //  NRFX_PWM0_ENABLED  - Enable PWM0 instance
- 
+
 
 #ifndef NRFX_PWM0_ENABLED
 #define NRFX_PWM0_ENABLED 0
 #endif
 
 //  NRFX_PWM1_ENABLED  - Enable PWM1 instance
- 
+
 
 #ifndef NRFX_PWM1_ENABLED
 #define NRFX_PWM1_ENABLED 0
 #endif
 
 //  NRFX_PWM2_ENABLED  - Enable PWM2 instance
- 
+
 
 #ifndef NRFX_PWM2_ENABLED
 #define NRFX_PWM2_ENABLED 0
 #endif
 
 //  NRFX_PWM3_ENABLED  - Enable PWM3 instance
- 
+
 
 #ifndef NRFX_PWM3_ENABLED
 #define NRFX_PWM3_ENABLED 0
 #endif
 
-//  NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin  <0-31> 
+//  NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin  <0-31>
 
 
 #ifndef NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN
 #define NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN 31
 #endif
 
-//  NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin  <0-31> 
+//  NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin  <0-31>
 
 
 #ifndef NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN
 #define NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN 31
 #endif
 
-//  NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin  <0-31> 
+//  NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin  <0-31>
 
 
 #ifndef NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN
 #define NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN 31
 #endif
 
-//  NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin  <0-31> 
+//  NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin  <0-31>
 
 
 #ifndef NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN
@@ -2632,64 +2632,64 @@
 #endif
 
 //  NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK  - Base clock
- 
-// <0=> 16 MHz 
-// <1=> 8 MHz 
-// <2=> 4 MHz 
-// <3=> 2 MHz 
-// <4=> 1 MHz 
-// <5=> 500 kHz 
-// <6=> 250 kHz 
-// <7=> 125 kHz 
+
+// <0=> 16 MHz
+// <1=> 8 MHz
+// <2=> 4 MHz
+// <3=> 2 MHz
+// <4=> 1 MHz
+// <5=> 500 kHz
+// <6=> 250 kHz
+// <7=> 125 kHz
 
 #ifndef NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK
 #define NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK 4
 #endif
 
 //  NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE  - Count mode
- 
-// <0=> Up 
-// <1=> Up and Down 
+
+// <0=> Up
+// <1=> Up and Down
 
 #ifndef NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE
 #define NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE 0
 #endif
 
-//  NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE - Top value 
+//  NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE - Top value
 #ifndef NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE
 #define NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE 1000
 #endif
 
 //  NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE  - Load mode
- 
-// <0=> Common 
-// <1=> Grouped 
-// <2=> Individual 
-// <3=> Waveform 
+
+// <0=> Common
+// <1=> Grouped
+// <2=> Individual
+// <3=> Waveform
 
 #ifndef NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE
 #define NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE 0
 #endif
 
 //  NRFX_PWM_DEFAULT_CONFIG_STEP_MODE  - Step mode
- 
-// <0=> Auto 
-// <1=> Triggered 
+
+// <0=> Auto
+// <1=> Triggered
 
 #ifndef NRFX_PWM_DEFAULT_CONFIG_STEP_MODE
 #define NRFX_PWM_DEFAULT_CONFIG_STEP_MODE 0
 #endif
 
 //  NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY
 #define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY 6
@@ -2701,44 +2701,44 @@
 #define NRFX_PWM_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_PWM_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_PWM_CONFIG_LOG_LEVEL
 #define NRFX_PWM_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_PWM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_PWM_CONFIG_INFO_COLOR
 #define NRFX_PWM_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_PWM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_PWM_CONFIG_DEBUG_COLOR
 #define NRFX_PWM_CONFIG_DEBUG_COLOR 0
@@ -2754,94 +2754,94 @@
 #define NRFX_QDEC_ENABLED 0
 #endif
 //  NRFX_QDEC_CONFIG_REPORTPER  - Report period
- 
-// <0=> 10 Samples 
-// <1=> 40 Samples 
-// <2=> 80 Samples 
-// <3=> 120 Samples 
-// <4=> 160 Samples 
-// <5=> 200 Samples 
-// <6=> 240 Samples 
-// <7=> 280 Samples 
+
+// <0=> 10 Samples
+// <1=> 40 Samples
+// <2=> 80 Samples
+// <3=> 120 Samples
+// <4=> 160 Samples
+// <5=> 200 Samples
+// <6=> 240 Samples
+// <7=> 280 Samples
 
 #ifndef NRFX_QDEC_CONFIG_REPORTPER
 #define NRFX_QDEC_CONFIG_REPORTPER 0
 #endif
 
 //  NRFX_QDEC_CONFIG_SAMPLEPER  - Sample period
- 
-// <0=> 128 us 
-// <1=> 256 us 
-// <2=> 512 us 
-// <3=> 1024 us 
-// <4=> 2048 us 
-// <5=> 4096 us 
-// <6=> 8192 us 
-// <7=> 16384 us 
+
+// <0=> 128 us
+// <1=> 256 us
+// <2=> 512 us
+// <3=> 1024 us
+// <4=> 2048 us
+// <5=> 4096 us
+// <6=> 8192 us
+// <7=> 16384 us
 
 #ifndef NRFX_QDEC_CONFIG_SAMPLEPER
 #define NRFX_QDEC_CONFIG_SAMPLEPER 7
 #endif
 
-//  NRFX_QDEC_CONFIG_PIO_A - A pin  <0-31> 
+//  NRFX_QDEC_CONFIG_PIO_A - A pin  <0-31>
 
 
 #ifndef NRFX_QDEC_CONFIG_PIO_A
 #define NRFX_QDEC_CONFIG_PIO_A 31
 #endif
 
-//  NRFX_QDEC_CONFIG_PIO_B - B pin  <0-31> 
+//  NRFX_QDEC_CONFIG_PIO_B - B pin  <0-31>
 
 
 #ifndef NRFX_QDEC_CONFIG_PIO_B
 #define NRFX_QDEC_CONFIG_PIO_B 31
 #endif
 
-//  NRFX_QDEC_CONFIG_PIO_LED - LED pin  <0-31> 
+//  NRFX_QDEC_CONFIG_PIO_LED - LED pin  <0-31>
 
 
 #ifndef NRFX_QDEC_CONFIG_PIO_LED
 #define NRFX_QDEC_CONFIG_PIO_LED 31
 #endif
 
-//  NRFX_QDEC_CONFIG_LEDPRE - LED pre 
+//  NRFX_QDEC_CONFIG_LEDPRE - LED pre
 #ifndef NRFX_QDEC_CONFIG_LEDPRE
 #define NRFX_QDEC_CONFIG_LEDPRE 511
 #endif
 
 //  NRFX_QDEC_CONFIG_LEDPOL  - LED polarity
- 
-// <0=> Active low 
-// <1=> Active high 
+
+// <0=> Active low
+// <1=> Active high
 
 #ifndef NRFX_QDEC_CONFIG_LEDPOL
 #define NRFX_QDEC_CONFIG_LEDPOL 1
 #endif
 
 //  NRFX_QDEC_CONFIG_DBFEN  - Debouncing enable
- 
+
 
 #ifndef NRFX_QDEC_CONFIG_DBFEN
 #define NRFX_QDEC_CONFIG_DBFEN 0
 #endif
 
 //  NRFX_QDEC_CONFIG_SAMPLE_INTEN  - Sample ready interrupt enable
- 
+
 
 #ifndef NRFX_QDEC_CONFIG_SAMPLE_INTEN
 #define NRFX_QDEC_CONFIG_SAMPLE_INTEN 0
 #endif
 
 //  NRFX_QDEC_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_QDEC_CONFIG_IRQ_PRIORITY
 #define NRFX_QDEC_CONFIG_IRQ_PRIORITY 6
@@ -2853,44 +2853,44 @@
 #define NRFX_QDEC_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_QDEC_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_QDEC_CONFIG_LOG_LEVEL
 #define NRFX_QDEC_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_QDEC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_QDEC_CONFIG_INFO_COLOR
 #define NRFX_QDEC_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_QDEC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_QDEC_CONFIG_DEBUG_COLOR
 #define NRFX_QDEC_CONFIG_DEBUG_COLOR 0
@@ -2905,77 +2905,77 @@
 #ifndef NRFX_QSPI_ENABLED
 #define NRFX_QSPI_ENABLED 0
 #endif
-//  NRFX_QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns).  <0-255> 
+//  NRFX_QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns).  <0-255>
 
 
 #ifndef NRFX_QSPI_CONFIG_SCK_DELAY
 #define NRFX_QSPI_CONFIG_SCK_DELAY 1
 #endif
 
-//  NRFX_QSPI_CONFIG_XIP_OFFSET - Address offset in the external memory for Execute in Place operation. 
+//  NRFX_QSPI_CONFIG_XIP_OFFSET - Address offset in the external memory for Execute in Place operation.
 #ifndef NRFX_QSPI_CONFIG_XIP_OFFSET
 #define NRFX_QSPI_CONFIG_XIP_OFFSET 0
 #endif
 
 //  NRFX_QSPI_CONFIG_READOC  - Number of data lines and opcode used for reading.
- 
-// <0=> FastRead 
-// <1=> Read2O 
-// <2=> Read2IO 
-// <3=> Read4O 
-// <4=> Read4IO 
+
+// <0=> FastRead
+// <1=> Read2O
+// <2=> Read2IO
+// <3=> Read4O
+// <4=> Read4IO
 
 #ifndef NRFX_QSPI_CONFIG_READOC
 #define NRFX_QSPI_CONFIG_READOC 0
 #endif
 
 //  NRFX_QSPI_CONFIG_WRITEOC  - Number of data lines and opcode used for writing.
- 
-// <0=> PP 
-// <1=> PP2O 
-// <2=> PP4O 
-// <3=> PP4IO 
+
+// <0=> PP
+// <1=> PP2O
+// <2=> PP4O
+// <3=> PP4IO
 
 #ifndef NRFX_QSPI_CONFIG_WRITEOC
 #define NRFX_QSPI_CONFIG_WRITEOC 0
 #endif
 
 //  NRFX_QSPI_CONFIG_ADDRMODE  - Addressing mode.
- 
-// <0=> 24bit 
-// <1=> 32bit 
+
+// <0=> 24bit
+// <1=> 32bit
 
 #ifndef NRFX_QSPI_CONFIG_ADDRMODE
 #define NRFX_QSPI_CONFIG_ADDRMODE 0
 #endif
 
 //  NRFX_QSPI_CONFIG_MODE  - SPI mode.
- 
-// <0=> Mode 0 
-// <1=> Mode 1 
+
+// <0=> Mode 0
+// <1=> Mode 1
 
 #ifndef NRFX_QSPI_CONFIG_MODE
 #define NRFX_QSPI_CONFIG_MODE 0
 #endif
 
 //  NRFX_QSPI_CONFIG_FREQUENCY  - Frequency divider.
- 
-// <0=> 32MHz/1 
-// <1=> 32MHz/2 
-// <2=> 32MHz/3 
-// <3=> 32MHz/4 
-// <4=> 32MHz/5 
-// <5=> 32MHz/6 
-// <6=> 32MHz/7 
-// <7=> 32MHz/8 
-// <8=> 32MHz/9 
-// <9=> 32MHz/10 
-// <10=> 32MHz/11 
-// <11=> 32MHz/12 
-// <12=> 32MHz/13 
-// <13=> 32MHz/14 
-// <14=> 32MHz/15 
-// <15=> 32MHz/16 
+
+// <0=> 32MHz/1
+// <1=> 32MHz/2
+// <2=> 32MHz/3
+// <3=> 32MHz/4
+// <4=> 32MHz/5
+// <5=> 32MHz/6
+// <6=> 32MHz/7
+// <7=> 32MHz/8
+// <8=> 32MHz/9
+// <9=> 32MHz/10
+// <10=> 32MHz/11
+// <11=> 32MHz/12
+// <12=> 32MHz/13
+// <13=> 32MHz/14
+// <14=> 32MHz/15
+// <15=> 32MHz/16
 
 #ifndef NRFX_QSPI_CONFIG_FREQUENCY
 #define NRFX_QSPI_CONFIG_FREQUENCY 15
@@ -3012,15 +3012,15 @@
 #endif
 
 //  NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY
 #define NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY 6
@@ -3034,22 +3034,22 @@
 #define NRFX_RNG_ENABLED 0
 #endif
 //  NRFX_RNG_CONFIG_ERROR_CORRECTION  - Error correction
- 
+
 
 #ifndef NRFX_RNG_CONFIG_ERROR_CORRECTION
 #define NRFX_RNG_CONFIG_ERROR_CORRECTION 1
 #endif
 
 //  NRFX_RNG_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_RNG_CONFIG_IRQ_PRIORITY
 #define NRFX_RNG_CONFIG_IRQ_PRIORITY 6
@@ -3061,44 +3061,44 @@
 #define NRFX_RNG_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_RNG_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_RNG_CONFIG_LOG_LEVEL
 #define NRFX_RNG_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_RNG_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_RNG_CONFIG_INFO_COLOR
 #define NRFX_RNG_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_RNG_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_RNG_CONFIG_DEBUG_COLOR
 #define NRFX_RNG_CONFIG_DEBUG_COLOR 0
@@ -3114,32 +3114,32 @@
 #define NRFX_RTC_ENABLED 0
 #endif
 //  NRFX_RTC0_ENABLED  - Enable RTC0 instance
- 
+
 
 #ifndef NRFX_RTC0_ENABLED
 #define NRFX_RTC0_ENABLED 0
 #endif
 
 //  NRFX_RTC1_ENABLED  - Enable RTC1 instance
- 
+
 
 #ifndef NRFX_RTC1_ENABLED
 #define NRFX_RTC1_ENABLED 0
 #endif
 
 //  NRFX_RTC2_ENABLED  - Enable RTC2 instance
- 
+
 
 #ifndef NRFX_RTC2_ENABLED
 #define NRFX_RTC2_ENABLED 0
 #endif
 
-//  NRFX_RTC_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt 
+//  NRFX_RTC_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt
 #ifndef NRFX_RTC_MAXIMUM_LATENCY_US
 #define NRFX_RTC_MAXIMUM_LATENCY_US 2000
 #endif
 
-//  NRFX_RTC_DEFAULT_CONFIG_FREQUENCY - Frequency  <16-32768> 
+//  NRFX_RTC_DEFAULT_CONFIG_FREQUENCY - Frequency  <16-32768>
 
 
 #ifndef NRFX_RTC_DEFAULT_CONFIG_FREQUENCY
@@ -3147,22 +3147,22 @@
 #endif
 
 //  NRFX_RTC_DEFAULT_CONFIG_RELIABLE  - Ensures safe compare event triggering
- 
+
 
 #ifndef NRFX_RTC_DEFAULT_CONFIG_RELIABLE
 #define NRFX_RTC_DEFAULT_CONFIG_RELIABLE 0
 #endif
 
 //  NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY
 #define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY 6
@@ -3174,44 +3174,44 @@
 #define NRFX_RTC_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_RTC_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_RTC_CONFIG_LOG_LEVEL
 #define NRFX_RTC_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_RTC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_RTC_CONFIG_INFO_COLOR
 #define NRFX_RTC_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_RTC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_RTC_CONFIG_DEBUG_COLOR
 #define NRFX_RTC_CONFIG_DEBUG_COLOR 0
@@ -3227,49 +3227,49 @@
 #define NRFX_SAADC_ENABLED 0
 #endif
 //  NRFX_SAADC_CONFIG_RESOLUTION  - Resolution
- 
-// <0=> 8 bit 
-// <1=> 10 bit 
-// <2=> 12 bit 
-// <3=> 14 bit 
+
+// <0=> 8 bit
+// <1=> 10 bit
+// <2=> 12 bit
+// <3=> 14 bit
 
 #ifndef NRFX_SAADC_CONFIG_RESOLUTION
 #define NRFX_SAADC_CONFIG_RESOLUTION 1
 #endif
 
 //  NRFX_SAADC_CONFIG_OVERSAMPLE  - Sample period
- 
-// <0=> Disabled 
-// <1=> 2x 
-// <2=> 4x 
-// <3=> 8x 
-// <4=> 16x 
-// <5=> 32x 
-// <6=> 64x 
-// <7=> 128x 
-// <8=> 256x 
+
+// <0=> Disabled
+// <1=> 2x
+// <2=> 4x
+// <3=> 8x
+// <4=> 16x
+// <5=> 32x
+// <6=> 64x
+// <7=> 128x
+// <8=> 256x
 
 #ifndef NRFX_SAADC_CONFIG_OVERSAMPLE
 #define NRFX_SAADC_CONFIG_OVERSAMPLE 0
 #endif
 
 //  NRFX_SAADC_CONFIG_LP_MODE  - Enabling low power mode
- 
+
 
 #ifndef NRFX_SAADC_CONFIG_LP_MODE
 #define NRFX_SAADC_CONFIG_LP_MODE 0
 #endif
 
 //  NRFX_SAADC_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_SAADC_CONFIG_IRQ_PRIORITY
 #define NRFX_SAADC_CONFIG_IRQ_PRIORITY 6
@@ -3281,44 +3281,44 @@
 #define NRFX_SAADC_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_SAADC_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_SAADC_CONFIG_LOG_LEVEL
 #define NRFX_SAADC_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_SAADC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_SAADC_CONFIG_INFO_COLOR
 #define NRFX_SAADC_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_SAADC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_SAADC_CONFIG_DEBUG_COLOR
 #define NRFX_SAADC_CONFIG_DEBUG_COLOR 0
@@ -3334,60 +3334,60 @@
 #define NRFX_SPIM_ENABLED 0
 #endif
 //  NRFX_SPIM0_ENABLED  - Enable SPIM0 instance
- 
+
 
 #ifndef NRFX_SPIM0_ENABLED
 #define NRFX_SPIM0_ENABLED 0
 #endif
 
 //  NRFX_SPIM1_ENABLED  - Enable SPIM1 instance
- 
+
 
 #ifndef NRFX_SPIM1_ENABLED
 #define NRFX_SPIM1_ENABLED 0
 #endif
 
 //  NRFX_SPIM2_ENABLED  - Enable SPIM2 instance
- 
+
 
 #ifndef NRFX_SPIM2_ENABLED
 #define NRFX_SPIM2_ENABLED 0
 #endif
 
 //  NRFX_SPIM3_ENABLED  - Enable SPIM3 instance
- 
+
 
 #ifndef NRFX_SPIM3_ENABLED
 #define NRFX_SPIM3_ENABLED 0
 #endif
 
 //  NRFX_SPIM_EXTENDED_ENABLED  - Enable extended SPIM features
- 
+
 
 #ifndef NRFX_SPIM_EXTENDED_ENABLED
 #define NRFX_SPIM_EXTENDED_ENABLED 0
 #endif
 
 //  NRFX_SPIM_MISO_PULL_CFG  - MISO pin pull configuration.
- 
-// <0=> NRF_GPIO_PIN_NOPULL 
-// <1=> NRF_GPIO_PIN_PULLDOWN 
-// <3=> NRF_GPIO_PIN_PULLUP 
+
+// <0=> NRF_GPIO_PIN_NOPULL
+// <1=> NRF_GPIO_PIN_PULLDOWN
+// <3=> NRF_GPIO_PIN_PULLUP
 
 #ifndef NRFX_SPIM_MISO_PULL_CFG
 #define NRFX_SPIM_MISO_PULL_CFG 1
 #endif
 
 //  NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY
 #define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY 6
@@ -3399,44 +3399,44 @@
 #define NRFX_SPIM_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_SPIM_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_SPIM_CONFIG_LOG_LEVEL
 #define NRFX_SPIM_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_SPIM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_SPIM_CONFIG_INFO_COLOR
 #define NRFX_SPIM_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_SPIM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_SPIM_CONFIG_DEBUG_COLOR
 #define NRFX_SPIM_CONFIG_DEBUG_COLOR 0
@@ -3452,49 +3452,49 @@
 #define NRFX_SPIS_ENABLED 0
 #endif
 //  NRFX_SPIS0_ENABLED  - Enable SPIS0 instance
- 
+
 
 #ifndef NRFX_SPIS0_ENABLED
 #define NRFX_SPIS0_ENABLED 0
 #endif
 
 //  NRFX_SPIS1_ENABLED  - Enable SPIS1 instance
- 
+
 
 #ifndef NRFX_SPIS1_ENABLED
 #define NRFX_SPIS1_ENABLED 0
 #endif
 
 //  NRFX_SPIS2_ENABLED  - Enable SPIS2 instance
- 
+
 
 #ifndef NRFX_SPIS2_ENABLED
 #define NRFX_SPIS2_ENABLED 0
 #endif
 
 //  NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
 #define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 6
 #endif
 
-//  NRFX_SPIS_DEFAULT_DEF - SPIS default DEF character  <0-255> 
+//  NRFX_SPIS_DEFAULT_DEF - SPIS default DEF character  <0-255>
 
 
 #ifndef NRFX_SPIS_DEFAULT_DEF
 #define NRFX_SPIS_DEFAULT_DEF 255
 #endif
 
-//  NRFX_SPIS_DEFAULT_ORC - SPIS default ORC character  <0-255> 
+//  NRFX_SPIS_DEFAULT_ORC - SPIS default ORC character  <0-255>
 
 
 #ifndef NRFX_SPIS_DEFAULT_ORC
@@ -3507,44 +3507,44 @@
 #define NRFX_SPIS_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_SPIS_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_SPIS_CONFIG_LOG_LEVEL
 #define NRFX_SPIS_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_SPIS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_SPIS_CONFIG_INFO_COLOR
 #define NRFX_SPIS_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_SPIS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_SPIS_CONFIG_DEBUG_COLOR
 #define NRFX_SPIS_CONFIG_DEBUG_COLOR 0
@@ -3560,46 +3560,46 @@
 #define NRFX_SPI_ENABLED 0
 #endif
 //  NRFX_SPI0_ENABLED  - Enable SPI0 instance
- 
+
 
 #ifndef NRFX_SPI0_ENABLED
 #define NRFX_SPI0_ENABLED 1
 #endif
 
 //  NRFX_SPI1_ENABLED  - Enable SPI1 instance
- 
+
 
 #ifndef NRFX_SPI1_ENABLED
 #define NRFX_SPI1_ENABLED 1
 #endif
 
 //  NRFX_SPI2_ENABLED  - Enable SPI2 instance
- 
+
 
 #ifndef NRFX_SPI2_ENABLED
 #define NRFX_SPI2_ENABLED 1
 #endif
 
 //  NRFX_SPI_MISO_PULL_CFG  - MISO pin pull configuration.
- 
-// <0=> NRF_GPIO_PIN_NOPULL 
-// <1=> NRF_GPIO_PIN_PULLDOWN 
-// <3=> NRF_GPIO_PIN_PULLUP 
+
+// <0=> NRF_GPIO_PIN_NOPULL
+// <1=> NRF_GPIO_PIN_PULLDOWN
+// <3=> NRF_GPIO_PIN_PULLUP
 
 #ifndef NRFX_SPI_MISO_PULL_CFG
 #define NRFX_SPI_MISO_PULL_CFG 1
 #endif
 
 //  NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY
 #define NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY 6
@@ -3611,44 +3611,44 @@
 #define NRFX_SPI_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_SPI_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_SPI_CONFIG_LOG_LEVEL
 #define NRFX_SPI_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_SPI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_SPI_CONFIG_INFO_COLOR
 #define NRFX_SPI_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_SPI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_SPI_CONFIG_DEBUG_COLOR
 #define NRFX_SPI_CONFIG_DEBUG_COLOR 0
@@ -3664,49 +3664,49 @@
 #define NRFX_SWI_ENABLED 0
 #endif
 //  NRFX_EGU_ENABLED  - Enable EGU support
- 
+
 
 #ifndef NRFX_EGU_ENABLED
 #define NRFX_EGU_ENABLED 0
 #endif
 
 //  NRFX_SWI0_DISABLED  - Exclude SWI0 from being utilized by the driver
- 
+
 
 #ifndef NRFX_SWI0_DISABLED
 #define NRFX_SWI0_DISABLED 0
 #endif
 
 //  NRFX_SWI1_DISABLED  - Exclude SWI1 from being utilized by the driver
- 
+
 
 #ifndef NRFX_SWI1_DISABLED
 #define NRFX_SWI1_DISABLED 0
 #endif
 
 //  NRFX_SWI2_DISABLED  - Exclude SWI2 from being utilized by the driver
- 
+
 
 #ifndef NRFX_SWI2_DISABLED
 #define NRFX_SWI2_DISABLED 0
 #endif
 
 //  NRFX_SWI3_DISABLED  - Exclude SWI3 from being utilized by the driver
- 
+
 
 #ifndef NRFX_SWI3_DISABLED
 #define NRFX_SWI3_DISABLED 0
 #endif
 
 //  NRFX_SWI4_DISABLED  - Exclude SWI4 from being utilized by the driver
- 
+
 
 #ifndef NRFX_SWI4_DISABLED
 #define NRFX_SWI4_DISABLED 0
 #endif
 
 //  NRFX_SWI5_DISABLED  - Exclude SWI5 from being utilized by the driver
- 
+
 
 #ifndef NRFX_SWI5_DISABLED
 #define NRFX_SWI5_DISABLED 0
@@ -3718,44 +3718,44 @@
 #define NRFX_SWI_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_SWI_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_SWI_CONFIG_LOG_LEVEL
 #define NRFX_SWI_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_SWI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_SWI_CONFIG_INFO_COLOR
 #define NRFX_SWI_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_SWI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_SWI_CONFIG_DEBUG_COLOR
 #define NRFX_SWI_CONFIG_DEBUG_COLOR 0
@@ -3771,87 +3771,87 @@
 #define NRFX_TIMER_ENABLED 0
 #endif
 //  NRFX_TIMER0_ENABLED  - Enable TIMER0 instance
- 
+
 
 #ifndef NRFX_TIMER0_ENABLED
 #define NRFX_TIMER0_ENABLED 0
 #endif
 
 //  NRFX_TIMER1_ENABLED  - Enable TIMER1 instance
- 
+
 
 #ifndef NRFX_TIMER1_ENABLED
 #define NRFX_TIMER1_ENABLED 0
 #endif
 
 //  NRFX_TIMER2_ENABLED  - Enable TIMER2 instance
- 
+
 
 #ifndef NRFX_TIMER2_ENABLED
 #define NRFX_TIMER2_ENABLED 0
 #endif
 
 //  NRFX_TIMER3_ENABLED  - Enable TIMER3 instance
- 
+
 
 #ifndef NRFX_TIMER3_ENABLED
 #define NRFX_TIMER3_ENABLED 0
 #endif
 
 //  NRFX_TIMER4_ENABLED  - Enable TIMER4 instance
- 
+
 
 #ifndef NRFX_TIMER4_ENABLED
 #define NRFX_TIMER4_ENABLED 0
 #endif
 
 //  NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY  - Timer frequency if in Timer mode
- 
-// <0=> 16 MHz 
-// <1=> 8 MHz 
-// <2=> 4 MHz 
-// <3=> 2 MHz 
-// <4=> 1 MHz 
-// <5=> 500 kHz 
-// <6=> 250 kHz 
-// <7=> 125 kHz 
-// <8=> 62.5 kHz 
-// <9=> 31.25 kHz 
+
+// <0=> 16 MHz
+// <1=> 8 MHz
+// <2=> 4 MHz
+// <3=> 2 MHz
+// <4=> 1 MHz
+// <5=> 500 kHz
+// <6=> 250 kHz
+// <7=> 125 kHz
+// <8=> 62.5 kHz
+// <9=> 31.25 kHz
 
 #ifndef NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY
 #define NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY 0
 #endif
 
 //  NRFX_TIMER_DEFAULT_CONFIG_MODE  - Timer mode or operation
- 
-// <0=> Timer 
-// <1=> Counter 
+
+// <0=> Timer
+// <1=> Counter
 
 #ifndef NRFX_TIMER_DEFAULT_CONFIG_MODE
 #define NRFX_TIMER_DEFAULT_CONFIG_MODE 0
 #endif
 
 //  NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH  - Timer counter bit width
- 
-// <0=> 16 bit 
-// <1=> 8 bit 
-// <2=> 24 bit 
-// <3=> 32 bit 
+
+// <0=> 16 bit
+// <1=> 8 bit
+// <2=> 24 bit
+// <3=> 32 bit
 
 #ifndef NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH
 #define NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH 0
 #endif
 
 //  NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
 #define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 6
@@ -3863,44 +3863,44 @@
 #define NRFX_TIMER_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_TIMER_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_TIMER_CONFIG_LOG_LEVEL
 #define NRFX_TIMER_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_TIMER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_TIMER_CONFIG_INFO_COLOR
 #define NRFX_TIMER_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_TIMER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_TIMER_CONFIG_DEBUG_COLOR
 #define NRFX_TIMER_CONFIG_DEBUG_COLOR 0
@@ -3916,46 +3916,46 @@
 #define NRFX_TWIM_ENABLED 0
 #endif
 //  NRFX_TWIM0_ENABLED  - Enable TWIM0 instance
- 
+
 
 #ifndef NRFX_TWIM0_ENABLED
 #define NRFX_TWIM0_ENABLED 0
 #endif
 
 //  NRFX_TWIM1_ENABLED  - Enable TWIM1 instance
- 
+
 
 #ifndef NRFX_TWIM1_ENABLED
 #define NRFX_TWIM1_ENABLED 0
 #endif
 
 //  NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY  - Frequency
- 
-// <26738688=> 100k 
-// <67108864=> 250k 
-// <104857600=> 400k 
+
+// <26738688=> 100k
+// <67108864=> 250k
+// <104857600=> 400k
 
 #ifndef NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY
 #define NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY 26738688
 #endif
 
 //  NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT  - Enables bus holding after uninit
- 
+
 
 #ifndef NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT
 #define NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0
 #endif
 
 //  NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY
 #define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY 6
@@ -3967,44 +3967,44 @@
 #define NRFX_TWIM_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_TWIM_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_TWIM_CONFIG_LOG_LEVEL
 #define NRFX_TWIM_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_TWIM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_TWIM_CONFIG_INFO_COLOR
 #define NRFX_TWIM_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_TWIM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_TWIM_CONFIG_DEBUG_COLOR
 #define NRFX_TWIM_CONFIG_DEBUG_COLOR 0
@@ -4020,21 +4020,21 @@
 #define NRFX_TWIS_ENABLED 0
 #endif
 //  NRFX_TWIS0_ENABLED  - Enable TWIS0 instance
- 
+
 
 #ifndef NRFX_TWIS0_ENABLED
 #define NRFX_TWIS0_ENABLED 0
 #endif
 
 //  NRFX_TWIS1_ENABLED  - Enable TWIS1 instance
- 
+
 
 #ifndef NRFX_TWIS1_ENABLED
 #define NRFX_TWIS1_ENABLED 0
 #endif
 
 //  NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY  - Assume that any instance would be initialized only once
- 
+
 
 //  Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code.
 
@@ -4043,7 +4043,7 @@
 #endif
 
 //  NRFX_TWIS_NO_SYNC_MODE  - Remove support for synchronous mode
- 
+
 
 //  Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources.
 
@@ -4051,46 +4051,46 @@
 #define NRFX_TWIS_NO_SYNC_MODE 0
 #endif
 
-//  NRFX_TWIS_DEFAULT_CONFIG_ADDR0 - Address0 
+//  NRFX_TWIS_DEFAULT_CONFIG_ADDR0 - Address0
 #ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR0
 #define NRFX_TWIS_DEFAULT_CONFIG_ADDR0 0
 #endif
 
-//  NRFX_TWIS_DEFAULT_CONFIG_ADDR1 - Address1 
+//  NRFX_TWIS_DEFAULT_CONFIG_ADDR1 - Address1
 #ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR1
 #define NRFX_TWIS_DEFAULT_CONFIG_ADDR1 0
 #endif
 
 //  NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL  - SCL pin pull configuration
- 
-// <0=> Disabled 
-// <1=> Pull down 
-// <3=> Pull up 
+
+// <0=> Disabled
+// <1=> Pull down
+// <3=> Pull up
 
 #ifndef NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL
 #define NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL 0
 #endif
 
 //  NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL  - SDA pin pull configuration
- 
-// <0=> Disabled 
-// <1=> Pull down 
-// <3=> Pull up 
+
+// <0=> Disabled
+// <1=> Pull down
+// <3=> Pull up
 
 #ifndef NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL
 #define NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL 0
 #endif
 
 //  NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
 #define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 6
@@ -4102,44 +4102,44 @@
 #define NRFX_TWIS_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_TWIS_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_TWIS_CONFIG_LOG_LEVEL
 #define NRFX_TWIS_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_TWIS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_TWIS_CONFIG_INFO_COLOR
 #define NRFX_TWIS_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_TWIS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_TWIS_CONFIG_DEBUG_COLOR
 #define NRFX_TWIS_CONFIG_DEBUG_COLOR 0
@@ -4155,46 +4155,46 @@
 #define NRFX_TWI_ENABLED 0
 #endif
 //  NRFX_TWI0_ENABLED  - Enable TWI0 instance
- 
+
 
 #ifndef NRFX_TWI0_ENABLED
 #define NRFX_TWI0_ENABLED 0
 #endif
 
 //  NRFX_TWI1_ENABLED  - Enable TWI1 instance
- 
+
 
 #ifndef NRFX_TWI1_ENABLED
 #define NRFX_TWI1_ENABLED 0
 #endif
 
 //  NRFX_TWI_DEFAULT_CONFIG_FREQUENCY  - Frequency
- 
-// <26738688=> 100k 
-// <67108864=> 250k 
-// <104857600=> 400k 
+
+// <26738688=> 100k
+// <67108864=> 250k
+// <104857600=> 400k
 
 #ifndef NRFX_TWI_DEFAULT_CONFIG_FREQUENCY
 #define NRFX_TWI_DEFAULT_CONFIG_FREQUENCY 26738688
 #endif
 
 //  NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT  - Enables bus holding after uninit
- 
+
 
 #ifndef NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT
 #define NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0
 #endif
 
 //  NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY
 #define NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY 6
@@ -4206,44 +4206,44 @@
 #define NRFX_TWI_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_TWI_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_TWI_CONFIG_LOG_LEVEL
 #define NRFX_TWI_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_TWI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_TWI_CONFIG_INFO_COLOR
 #define NRFX_TWI_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_TWI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_TWI_CONFIG_DEBUG_COLOR
 #define NRFX_TWI_CONFIG_DEBUG_COLOR 0
@@ -4258,69 +4258,69 @@
 #ifndef NRFX_UARTE_ENABLED
 #define NRFX_UARTE_ENABLED 0
 #endif
-//  NRFX_UARTE0_ENABLED - Enable UARTE0 instance 
+//  NRFX_UARTE0_ENABLED - Enable UARTE0 instance
 #ifndef NRFX_UARTE0_ENABLED
 #define NRFX_UARTE0_ENABLED 0
 #endif
 
-//  NRFX_UARTE1_ENABLED - Enable UARTE1 instance 
+//  NRFX_UARTE1_ENABLED - Enable UARTE1 instance
 #ifndef NRFX_UARTE1_ENABLED
 #define NRFX_UARTE1_ENABLED 0
 #endif
 
 //  NRFX_UARTE_DEFAULT_CONFIG_HWFC  - Hardware Flow Control
- 
-// <0=> Disabled 
-// <1=> Enabled 
+
+// <0=> Disabled
+// <1=> Enabled
 
 #ifndef NRFX_UARTE_DEFAULT_CONFIG_HWFC
 #define NRFX_UARTE_DEFAULT_CONFIG_HWFC 0
 #endif
 
 //  NRFX_UARTE_DEFAULT_CONFIG_PARITY  - Parity
- 
-// <0=> Excluded 
-// <14=> Included 
+
+// <0=> Excluded
+// <14=> Included
 
 #ifndef NRFX_UARTE_DEFAULT_CONFIG_PARITY
 #define NRFX_UARTE_DEFAULT_CONFIG_PARITY 0
 #endif
 
 //  NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE  - Default Baudrate
- 
-// <323584=> 1200 baud 
-// <643072=> 2400 baud 
-// <1290240=> 4800 baud 
-// <2576384=> 9600 baud 
-// <3862528=> 14400 baud 
-// <5152768=> 19200 baud 
-// <7716864=> 28800 baud 
-// <8388608=> 31250 baud 
-// <10289152=> 38400 baud 
-// <15007744=> 56000 baud 
-// <15400960=> 57600 baud 
-// <20615168=> 76800 baud 
-// <30801920=> 115200 baud 
-// <61865984=> 230400 baud 
-// <67108864=> 250000 baud 
-// <121634816=> 460800 baud 
-// <251658240=> 921600 baud 
-// <268435456=> 1000000 baud 
+
+// <323584=> 1200 baud
+// <643072=> 2400 baud
+// <1290240=> 4800 baud
+// <2576384=> 9600 baud
+// <3862528=> 14400 baud
+// <5152768=> 19200 baud
+// <7716864=> 28800 baud
+// <8388608=> 31250 baud
+// <10289152=> 38400 baud
+// <15007744=> 56000 baud
+// <15400960=> 57600 baud
+// <20615168=> 76800 baud
+// <30801920=> 115200 baud
+// <61865984=> 230400 baud
+// <67108864=> 250000 baud
+// <121634816=> 460800 baud
+// <251658240=> 921600 baud
+// <268435456=> 1000000 baud
 
 #ifndef NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE
 #define NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE 30801920
 #endif
 
 //  NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY
 #define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY 6
@@ -4332,44 +4332,44 @@
 #define NRFX_UARTE_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_UARTE_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_UARTE_CONFIG_LOG_LEVEL
 #define NRFX_UARTE_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_UARTE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_UARTE_CONFIG_INFO_COLOR
 #define NRFX_UARTE_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_UARTE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_UARTE_CONFIG_DEBUG_COLOR
 #define NRFX_UARTE_CONFIG_DEBUG_COLOR 0
@@ -4384,64 +4384,64 @@
 #ifndef NRFX_UART_ENABLED
 #define NRFX_UART_ENABLED 0
 #endif
-//  NRFX_UART0_ENABLED - Enable UART0 instance 
+//  NRFX_UART0_ENABLED - Enable UART0 instance
 #ifndef NRFX_UART0_ENABLED
 #define NRFX_UART0_ENABLED 0
 #endif
 
 //  NRFX_UART_DEFAULT_CONFIG_HWFC  - Hardware Flow Control
- 
-// <0=> Disabled 
-// <1=> Enabled 
+
+// <0=> Disabled
+// <1=> Enabled
 
 #ifndef NRFX_UART_DEFAULT_CONFIG_HWFC
 #define NRFX_UART_DEFAULT_CONFIG_HWFC 0
 #endif
 
 //  NRFX_UART_DEFAULT_CONFIG_PARITY  - Parity
- 
-// <0=> Excluded 
-// <14=> Included 
+
+// <0=> Excluded
+// <14=> Included
 
 #ifndef NRFX_UART_DEFAULT_CONFIG_PARITY
 #define NRFX_UART_DEFAULT_CONFIG_PARITY 0
 #endif
 
 //  NRFX_UART_DEFAULT_CONFIG_BAUDRATE  - Default Baudrate
- 
-// <323584=> 1200 baud 
-// <643072=> 2400 baud 
-// <1290240=> 4800 baud 
-// <2576384=> 9600 baud 
-// <3866624=> 14400 baud 
-// <5152768=> 19200 baud 
-// <7729152=> 28800 baud 
-// <8388608=> 31250 baud 
-// <10309632=> 38400 baud 
-// <15007744=> 56000 baud 
-// <15462400=> 57600 baud 
-// <20615168=> 76800 baud 
-// <30924800=> 115200 baud 
-// <61845504=> 230400 baud 
-// <67108864=> 250000 baud 
-// <123695104=> 460800 baud 
-// <247386112=> 921600 baud 
-// <268435456=> 1000000 baud 
+
+// <323584=> 1200 baud
+// <643072=> 2400 baud
+// <1290240=> 4800 baud
+// <2576384=> 9600 baud
+// <3866624=> 14400 baud
+// <5152768=> 19200 baud
+// <7729152=> 28800 baud
+// <8388608=> 31250 baud
+// <10309632=> 38400 baud
+// <15007744=> 56000 baud
+// <15462400=> 57600 baud
+// <20615168=> 76800 baud
+// <30924800=> 115200 baud
+// <61845504=> 230400 baud
+// <67108864=> 250000 baud
+// <123695104=> 460800 baud
+// <247386112=> 921600 baud
+// <268435456=> 1000000 baud
 
 #ifndef NRFX_UART_DEFAULT_CONFIG_BAUDRATE
 #define NRFX_UART_DEFAULT_CONFIG_BAUDRATE 30924800
 #endif
 
 //  NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY
 #define NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY 4
@@ -4453,44 +4453,44 @@
 #define NRFX_UART_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_UART_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_UART_CONFIG_LOG_LEVEL
 #define NRFX_UART_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_UART_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_UART_CONFIG_INFO_COLOR
 #define NRFX_UART_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_UART_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_UART_CONFIG_DEBUG_COLOR
 #define NRFX_UART_CONFIG_DEBUG_COLOR 0
@@ -4506,31 +4506,31 @@
 #define NRFX_USBD_ENABLED 0
 #endif
 //  NRFX_USBD_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_USBD_CONFIG_IRQ_PRIORITY
 #define NRFX_USBD_CONFIG_IRQ_PRIORITY 6
 #endif
 
 //  NRFX_USBD_CONFIG_DMASCHEDULER_MODE  - USBD DMA scheduler working scheme
- 
-// <0=> Prioritized access 
-// <1=> Round Robin 
+
+// <0=> Prioritized access
+// <1=> Round Robin
 
 #ifndef NRFX_USBD_CONFIG_DMASCHEDULER_MODE
 #define NRFX_USBD_CONFIG_DMASCHEDULER_MODE 0
 #endif
 
 //  NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST  - Give priority to isochronous transfers
- 
+
 
 //  This option gives priority to isochronous transfers.
 //  Enabling it assures that isochronous transfers are always processed,
@@ -4543,7 +4543,7 @@
 #endif
 
 //  NRFX_USBD_CONFIG_ISO_IN_ZLP  - Respond to an IN token on ISO IN endpoint with ZLP when no data is ready
- 
+
 
 //  If set, ISO IN endpoint will respond to an IN token with ZLP when no data is ready to be sent.
 //  Else, there will be no response.
@@ -4560,17 +4560,17 @@
 #define NRFX_WDT_ENABLED 0
 #endif
 //  NRFX_WDT_CONFIG_BEHAVIOUR  - WDT behavior in CPU SLEEP or HALT mode
- 
-// <1=> Run in SLEEP, Pause in HALT 
-// <8=> Pause in SLEEP, Run in HALT 
-// <9=> Run in SLEEP and HALT 
-// <0=> Pause in SLEEP and HALT 
+
+// <1=> Run in SLEEP, Pause in HALT
+// <8=> Pause in SLEEP, Run in HALT
+// <9=> Run in SLEEP and HALT
+// <0=> Pause in SLEEP and HALT
 
 #ifndef NRFX_WDT_CONFIG_BEHAVIOUR
 #define NRFX_WDT_CONFIG_BEHAVIOUR 1
 #endif
 
-//  NRFX_WDT_CONFIG_RELOAD_VALUE - Reload value  <15-4294967295> 
+//  NRFX_WDT_CONFIG_RELOAD_VALUE - Reload value  <15-4294967295>
 
 
 #ifndef NRFX_WDT_CONFIG_RELOAD_VALUE
@@ -4578,24 +4578,24 @@
 #endif
 
 //  NRFX_WDT_CONFIG_NO_IRQ  - Remove WDT IRQ handling from WDT driver
- 
-// <0=> Include WDT IRQ handling 
-// <1=> Remove WDT IRQ handling 
+
+// <0=> Include WDT IRQ handling
+// <1=> Remove WDT IRQ handling
 
 #ifndef NRFX_WDT_CONFIG_NO_IRQ
 #define NRFX_WDT_CONFIG_NO_IRQ 0
 #endif
 
 //  NRFX_WDT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_WDT_CONFIG_IRQ_PRIORITY
 #define NRFX_WDT_CONFIG_IRQ_PRIORITY 6
@@ -4607,44 +4607,44 @@
 #define NRFX_WDT_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_WDT_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_WDT_CONFIG_LOG_LEVEL
 #define NRFX_WDT_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_WDT_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_WDT_CONFIG_INFO_COLOR
 #define NRFX_WDT_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_WDT_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_WDT_CONFIG_DEBUG_COLOR
 #define NRFX_WDT_CONFIG_DEBUG_COLOR 0
@@ -4660,36 +4660,36 @@
 #define NRF_CLOCK_ENABLED 0
 #endif
 //  CLOCK_CONFIG_LF_SRC  - LF Clock Source
- 
-// <0=> RC 
-// <1=> XTAL 
-// <2=> Synth 
-// <131073=> External Low Swing 
-// <196609=> External Full Swing 
+
+// <0=> RC
+// <1=> XTAL
+// <2=> Synth
+// <131073=> External Low Swing
+// <196609=> External Full Swing
 
 #ifndef CLOCK_CONFIG_LF_SRC
 #define CLOCK_CONFIG_LF_SRC 1
 #endif
 
 //  CLOCK_CONFIG_LF_CAL_ENABLED  - Calibration enable for LF Clock Source
- 
+
 
 #ifndef CLOCK_CONFIG_LF_CAL_ENABLED
 #define CLOCK_CONFIG_LF_CAL_ENABLED 0
 #endif
 
 //  CLOCK_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef CLOCK_CONFIG_IRQ_PRIORITY
 #define CLOCK_CONFIG_IRQ_PRIORITY 6
@@ -4703,45 +4703,45 @@
 #define PDM_ENABLED 0
 #endif
 //  PDM_CONFIG_MODE  - Mode
- 
-// <0=> Stereo 
-// <1=> Mono 
+
+// <0=> Stereo
+// <1=> Mono
 
 #ifndef PDM_CONFIG_MODE
 #define PDM_CONFIG_MODE 1
 #endif
 
 //  PDM_CONFIG_EDGE  - Edge
- 
-// <0=> Left falling 
-// <1=> Left rising 
+
+// <0=> Left falling
+// <1=> Left rising
 
 #ifndef PDM_CONFIG_EDGE
 #define PDM_CONFIG_EDGE 0
 #endif
 
 //  PDM_CONFIG_CLOCK_FREQ  - Clock frequency
- 
-// <134217728=> 1000k 
-// <138412032=> 1032k (default) 
-// <142606336=> 1067k 
+
+// <134217728=> 1000k
+// <138412032=> 1032k (default)
+// <142606336=> 1067k
 
 #ifndef PDM_CONFIG_CLOCK_FREQ
 #define PDM_CONFIG_CLOCK_FREQ 138412032
 #endif
 
 //  PDM_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef PDM_CONFIG_IRQ_PRIORITY
 #define PDM_CONFIG_IRQ_PRIORITY 6
@@ -4755,24 +4755,24 @@
 #define POWER_ENABLED 0
 #endif
 //  POWER_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef POWER_CONFIG_IRQ_PRIORITY
 #define POWER_CONFIG_IRQ_PRIORITY 6
 #endif
 
 //  POWER_CONFIG_DEFAULT_DCDCEN  - The default configuration of main DCDC regulator
- 
+
 
 //  This settings means only that components for DCDC regulator are installed and it can be enabled.
 
@@ -4781,7 +4781,7 @@
 #endif
 
 //  POWER_CONFIG_DEFAULT_DCDCENHV  - The default configuration of High Voltage DCDC regulator
- 
+
 
 //  This settings means only that components for DCDC regulator are installed and it can be enabled.
 
@@ -4792,7 +4792,7 @@
 // 
 
 //  PPI_ENABLED  - nrf_drv_ppi - PPI peripheral driver - legacy layer
- 
+
 
 #ifndef PPI_ENABLED
 #define PPI_ENABLED 0
@@ -4803,28 +4803,28 @@
 #ifndef PWM_ENABLED
 #define PWM_ENABLED 0
 #endif
-//  PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin  <0-31> 
+//  PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin  <0-31>
 
 
 #ifndef PWM_DEFAULT_CONFIG_OUT0_PIN
 #define PWM_DEFAULT_CONFIG_OUT0_PIN 31
 #endif
 
-//  PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin  <0-31> 
+//  PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin  <0-31>
 
 
 #ifndef PWM_DEFAULT_CONFIG_OUT1_PIN
 #define PWM_DEFAULT_CONFIG_OUT1_PIN 31
 #endif
 
-//  PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin  <0-31> 
+//  PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin  <0-31>
 
 
 #ifndef PWM_DEFAULT_CONFIG_OUT2_PIN
 #define PWM_DEFAULT_CONFIG_OUT2_PIN 31
 #endif
 
-//  PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin  <0-31> 
+//  PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin  <0-31>
 
 
 #ifndef PWM_DEFAULT_CONFIG_OUT3_PIN
@@ -4832,94 +4832,94 @@
 #endif
 
 //  PWM_DEFAULT_CONFIG_BASE_CLOCK  - Base clock
- 
-// <0=> 16 MHz 
-// <1=> 8 MHz 
-// <2=> 4 MHz 
-// <3=> 2 MHz 
-// <4=> 1 MHz 
-// <5=> 500 kHz 
-// <6=> 250 kHz 
-// <7=> 125 kHz 
+
+// <0=> 16 MHz
+// <1=> 8 MHz
+// <2=> 4 MHz
+// <3=> 2 MHz
+// <4=> 1 MHz
+// <5=> 500 kHz
+// <6=> 250 kHz
+// <7=> 125 kHz
 
 #ifndef PWM_DEFAULT_CONFIG_BASE_CLOCK
 #define PWM_DEFAULT_CONFIG_BASE_CLOCK 4
 #endif
 
 //  PWM_DEFAULT_CONFIG_COUNT_MODE  - Count mode
- 
-// <0=> Up 
-// <1=> Up and Down 
+
+// <0=> Up
+// <1=> Up and Down
 
 #ifndef PWM_DEFAULT_CONFIG_COUNT_MODE
 #define PWM_DEFAULT_CONFIG_COUNT_MODE 0
 #endif
 
-//  PWM_DEFAULT_CONFIG_TOP_VALUE - Top value 
+//  PWM_DEFAULT_CONFIG_TOP_VALUE - Top value
 #ifndef PWM_DEFAULT_CONFIG_TOP_VALUE
 #define PWM_DEFAULT_CONFIG_TOP_VALUE 1000
 #endif
 
 //  PWM_DEFAULT_CONFIG_LOAD_MODE  - Load mode
- 
-// <0=> Common 
-// <1=> Grouped 
-// <2=> Individual 
-// <3=> Waveform 
+
+// <0=> Common
+// <1=> Grouped
+// <2=> Individual
+// <3=> Waveform
 
 #ifndef PWM_DEFAULT_CONFIG_LOAD_MODE
 #define PWM_DEFAULT_CONFIG_LOAD_MODE 0
 #endif
 
 //  PWM_DEFAULT_CONFIG_STEP_MODE  - Step mode
- 
-// <0=> Auto 
-// <1=> Triggered 
+
+// <0=> Auto
+// <1=> Triggered
 
 #ifndef PWM_DEFAULT_CONFIG_STEP_MODE
 #define PWM_DEFAULT_CONFIG_STEP_MODE 0
 #endif
 
 //  PWM_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef PWM_DEFAULT_CONFIG_IRQ_PRIORITY
 #define PWM_DEFAULT_CONFIG_IRQ_PRIORITY 6
 #endif
 
 //  PWM0_ENABLED  - Enable PWM0 instance
- 
+
 
 #ifndef PWM0_ENABLED
 #define PWM0_ENABLED 0
 #endif
 
 //  PWM1_ENABLED  - Enable PWM1 instance
- 
+
 
 #ifndef PWM1_ENABLED
 #define PWM1_ENABLED 0
 #endif
 
 //  PWM2_ENABLED  - Enable PWM2 instance
- 
+
 
 #ifndef PWM2_ENABLED
 #define PWM2_ENABLED 0
 #endif
 
 //  PWM3_ENABLED  - Enable PWM3 instance
- 
+
 
 #ifndef PWM3_ENABLED
 #define PWM3_ENABLED 0
@@ -4933,96 +4933,96 @@
 #define QDEC_ENABLED 0
 #endif
 //  QDEC_CONFIG_REPORTPER  - Report period
- 
-// <0=> 10 Samples 
-// <1=> 40 Samples 
-// <2=> 80 Samples 
-// <3=> 120 Samples 
-// <4=> 160 Samples 
-// <5=> 200 Samples 
-// <6=> 240 Samples 
-// <7=> 280 Samples 
+
+// <0=> 10 Samples
+// <1=> 40 Samples
+// <2=> 80 Samples
+// <3=> 120 Samples
+// <4=> 160 Samples
+// <5=> 200 Samples
+// <6=> 240 Samples
+// <7=> 280 Samples
 
 #ifndef QDEC_CONFIG_REPORTPER
 #define QDEC_CONFIG_REPORTPER 0
 #endif
 
 //  QDEC_CONFIG_SAMPLEPER  - Sample period
- 
-// <0=> 128 us 
-// <1=> 256 us 
-// <2=> 512 us 
-// <3=> 1024 us 
-// <4=> 2048 us 
-// <5=> 4096 us 
-// <6=> 8192 us 
-// <7=> 16384 us 
+
+// <0=> 128 us
+// <1=> 256 us
+// <2=> 512 us
+// <3=> 1024 us
+// <4=> 2048 us
+// <5=> 4096 us
+// <6=> 8192 us
+// <7=> 16384 us
 
 #ifndef QDEC_CONFIG_SAMPLEPER
 #define QDEC_CONFIG_SAMPLEPER 7
 #endif
 
-//  QDEC_CONFIG_PIO_A - A pin  <0-31> 
+//  QDEC_CONFIG_PIO_A - A pin  <0-31>
 
 
 #ifndef QDEC_CONFIG_PIO_A
 #define QDEC_CONFIG_PIO_A 31
 #endif
 
-//  QDEC_CONFIG_PIO_B - B pin  <0-31> 
+//  QDEC_CONFIG_PIO_B - B pin  <0-31>
 
 
 #ifndef QDEC_CONFIG_PIO_B
 #define QDEC_CONFIG_PIO_B 31
 #endif
 
-//  QDEC_CONFIG_PIO_LED - LED pin  <0-31> 
+//  QDEC_CONFIG_PIO_LED - LED pin  <0-31>
 
 
 #ifndef QDEC_CONFIG_PIO_LED
 #define QDEC_CONFIG_PIO_LED 31
 #endif
 
-//  QDEC_CONFIG_LEDPRE - LED pre 
+//  QDEC_CONFIG_LEDPRE - LED pre
 #ifndef QDEC_CONFIG_LEDPRE
 #define QDEC_CONFIG_LEDPRE 511
 #endif
 
 //  QDEC_CONFIG_LEDPOL  - LED polarity
- 
-// <0=> Active low 
-// <1=> Active high 
+
+// <0=> Active low
+// <1=> Active high
 
 #ifndef QDEC_CONFIG_LEDPOL
 #define QDEC_CONFIG_LEDPOL 1
 #endif
 
 //  QDEC_CONFIG_DBFEN  - Debouncing enable
- 
+
 
 #ifndef QDEC_CONFIG_DBFEN
 #define QDEC_CONFIG_DBFEN 0
 #endif
 
 //  QDEC_CONFIG_SAMPLE_INTEN  - Sample ready interrupt enable
- 
+
 
 #ifndef QDEC_CONFIG_SAMPLE_INTEN
 #define QDEC_CONFIG_SAMPLE_INTEN 0
 #endif
 
 //  QDEC_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef QDEC_CONFIG_IRQ_PRIORITY
 #define QDEC_CONFIG_IRQ_PRIORITY 6
@@ -5035,77 +5035,77 @@
 #ifndef QSPI_ENABLED
 #define QSPI_ENABLED 0
 #endif
-//  QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns).  <0-255> 
+//  QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns).  <0-255>
 
 
 #ifndef QSPI_CONFIG_SCK_DELAY
 #define QSPI_CONFIG_SCK_DELAY 1
 #endif
 
-//  QSPI_CONFIG_XIP_OFFSET - Address offset in the external memory for Execute in Place operation. 
+//  QSPI_CONFIG_XIP_OFFSET - Address offset in the external memory for Execute in Place operation.
 #ifndef QSPI_CONFIG_XIP_OFFSET
 #define QSPI_CONFIG_XIP_OFFSET 0
 #endif
 
 //  QSPI_CONFIG_READOC  - Number of data lines and opcode used for reading.
- 
-// <0=> FastRead 
-// <1=> Read2O 
-// <2=> Read2IO 
-// <3=> Read4O 
-// <4=> Read4IO 
+
+// <0=> FastRead
+// <1=> Read2O
+// <2=> Read2IO
+// <3=> Read4O
+// <4=> Read4IO
 
 #ifndef QSPI_CONFIG_READOC
 #define QSPI_CONFIG_READOC 0
 #endif
 
 //  QSPI_CONFIG_WRITEOC  - Number of data lines and opcode used for writing.
- 
-// <0=> PP 
-// <1=> PP2O 
-// <2=> PP4O 
-// <3=> PP4IO 
+
+// <0=> PP
+// <1=> PP2O
+// <2=> PP4O
+// <3=> PP4IO
 
 #ifndef QSPI_CONFIG_WRITEOC
 #define QSPI_CONFIG_WRITEOC 0
 #endif
 
 //  QSPI_CONFIG_ADDRMODE  - Addressing mode.
- 
-// <0=> 24bit 
-// <1=> 32bit 
+
+// <0=> 24bit
+// <1=> 32bit
 
 #ifndef QSPI_CONFIG_ADDRMODE
 #define QSPI_CONFIG_ADDRMODE 0
 #endif
 
 //  QSPI_CONFIG_MODE  - SPI mode.
- 
-// <0=> Mode 0 
-// <1=> Mode 1 
+
+// <0=> Mode 0
+// <1=> Mode 1
 
 #ifndef QSPI_CONFIG_MODE
 #define QSPI_CONFIG_MODE 0
 #endif
 
 //  QSPI_CONFIG_FREQUENCY  - Frequency divider.
- 
-// <0=> 32MHz/1 
-// <1=> 32MHz/2 
-// <2=> 32MHz/3 
-// <3=> 32MHz/4 
-// <4=> 32MHz/5 
-// <5=> 32MHz/6 
-// <6=> 32MHz/7 
-// <7=> 32MHz/8 
-// <8=> 32MHz/9 
-// <9=> 32MHz/10 
-// <10=> 32MHz/11 
-// <11=> 32MHz/12 
-// <12=> 32MHz/13 
-// <13=> 32MHz/14 
-// <14=> 32MHz/15 
-// <15=> 32MHz/16 
+
+// <0=> 32MHz/1
+// <1=> 32MHz/2
+// <2=> 32MHz/3
+// <3=> 32MHz/4
+// <4=> 32MHz/5
+// <5=> 32MHz/6
+// <6=> 32MHz/7
+// <7=> 32MHz/8
+// <8=> 32MHz/9
+// <9=> 32MHz/10
+// <10=> 32MHz/11
+// <11=> 32MHz/12
+// <12=> 32MHz/13
+// <13=> 32MHz/14
+// <14=> 32MHz/15
+// <15=> 32MHz/16
 
 #ifndef QSPI_CONFIG_FREQUENCY
 #define QSPI_CONFIG_FREQUENCY 15
@@ -5142,17 +5142,17 @@
 #endif
 
 //  QSPI_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef QSPI_CONFIG_IRQ_PRIORITY
 #define QSPI_CONFIG_IRQ_PRIORITY 6
@@ -5166,29 +5166,29 @@
 #define RNG_ENABLED 0
 #endif
 //  RNG_CONFIG_ERROR_CORRECTION  - Error correction
- 
+
 
 #ifndef RNG_CONFIG_ERROR_CORRECTION
 #define RNG_CONFIG_ERROR_CORRECTION 1
 #endif
 
-//  RNG_CONFIG_POOL_SIZE - Pool size 
+//  RNG_CONFIG_POOL_SIZE - Pool size
 #ifndef RNG_CONFIG_POOL_SIZE
 #define RNG_CONFIG_POOL_SIZE 64
 #endif
 
 //  RNG_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef RNG_CONFIG_IRQ_PRIORITY
 #define RNG_CONFIG_IRQ_PRIORITY 6
@@ -5201,7 +5201,7 @@
 #ifndef RTC_ENABLED
 #define RTC_ENABLED 0
 #endif
-//  RTC_DEFAULT_CONFIG_FREQUENCY - Frequency  <16-32768> 
+//  RTC_DEFAULT_CONFIG_FREQUENCY - Frequency  <16-32768>
 
 
 #ifndef RTC_DEFAULT_CONFIG_FREQUENCY
@@ -5209,51 +5209,51 @@
 #endif
 
 //  RTC_DEFAULT_CONFIG_RELIABLE  - Ensures safe compare event triggering
- 
+
 
 #ifndef RTC_DEFAULT_CONFIG_RELIABLE
 #define RTC_DEFAULT_CONFIG_RELIABLE 0
 #endif
 
 //  RTC_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef RTC_DEFAULT_CONFIG_IRQ_PRIORITY
 #define RTC_DEFAULT_CONFIG_IRQ_PRIORITY 6
 #endif
 
 //  RTC0_ENABLED  - Enable RTC0 instance
- 
+
 
 #ifndef RTC0_ENABLED
 #define RTC0_ENABLED 0
 #endif
 
 //  RTC1_ENABLED  - Enable RTC1 instance
- 
+
 
 #ifndef RTC1_ENABLED
 #define RTC1_ENABLED 0
 #endif
 
 //  RTC2_ENABLED  - Enable RTC2 instance
- 
+
 
 #ifndef RTC2_ENABLED
 #define RTC2_ENABLED 0
 #endif
 
-//  NRF_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt 
+//  NRF_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt
 #ifndef NRF_MAXIMUM_LATENCY_US
 #define NRF_MAXIMUM_LATENCY_US 2000
 #endif
@@ -5266,51 +5266,51 @@
 #define SAADC_ENABLED 0
 #endif
 //  SAADC_CONFIG_RESOLUTION  - Resolution
- 
-// <0=> 8 bit 
-// <1=> 10 bit 
-// <2=> 12 bit 
-// <3=> 14 bit 
+
+// <0=> 8 bit
+// <1=> 10 bit
+// <2=> 12 bit
+// <3=> 14 bit
 
 #ifndef SAADC_CONFIG_RESOLUTION
 #define SAADC_CONFIG_RESOLUTION 1
 #endif
 
 //  SAADC_CONFIG_OVERSAMPLE  - Sample period
- 
-// <0=> Disabled 
-// <1=> 2x 
-// <2=> 4x 
-// <3=> 8x 
-// <4=> 16x 
-// <5=> 32x 
-// <6=> 64x 
-// <7=> 128x 
-// <8=> 256x 
+
+// <0=> Disabled
+// <1=> 2x
+// <2=> 4x
+// <3=> 8x
+// <4=> 16x
+// <5=> 32x
+// <6=> 64x
+// <7=> 128x
+// <8=> 256x
 
 #ifndef SAADC_CONFIG_OVERSAMPLE
 #define SAADC_CONFIG_OVERSAMPLE 0
 #endif
 
 //  SAADC_CONFIG_LP_MODE  - Enabling low power mode
- 
+
 
 #ifndef SAADC_CONFIG_LP_MODE
 #define SAADC_CONFIG_LP_MODE 0
 #endif
 
 //  SAADC_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef SAADC_CONFIG_IRQ_PRIORITY
 #define SAADC_CONFIG_IRQ_PRIORITY 6
@@ -5324,50 +5324,50 @@
 #define SPIS_ENABLED 0
 #endif
 //  SPIS_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
 #define SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 6
 #endif
 
 //  SPIS_DEFAULT_MODE  - Mode
- 
-// <0=> MODE_0 
-// <1=> MODE_1 
-// <2=> MODE_2 
-// <3=> MODE_3 
+
+// <0=> MODE_0
+// <1=> MODE_1
+// <2=> MODE_2
+// <3=> MODE_3
 
 #ifndef SPIS_DEFAULT_MODE
 #define SPIS_DEFAULT_MODE 0
 #endif
 
 //  SPIS_DEFAULT_BIT_ORDER  - SPIS default bit order
- 
-// <0=> MSB first 
-// <1=> LSB first 
+
+// <0=> MSB first
+// <1=> LSB first
 
 #ifndef SPIS_DEFAULT_BIT_ORDER
 #define SPIS_DEFAULT_BIT_ORDER 0
 #endif
 
-//  SPIS_DEFAULT_DEF - SPIS default DEF character  <0-255> 
+//  SPIS_DEFAULT_DEF - SPIS default DEF character  <0-255>
 
 
 #ifndef SPIS_DEFAULT_DEF
 #define SPIS_DEFAULT_DEF 255
 #endif
 
-//  SPIS_DEFAULT_ORC - SPIS default ORC character  <0-255> 
+//  SPIS_DEFAULT_ORC - SPIS default ORC character  <0-255>
 
 
 #ifndef SPIS_DEFAULT_ORC
@@ -5375,21 +5375,21 @@
 #endif
 
 //  SPIS0_ENABLED  - Enable SPIS0 instance
- 
+
 
 #ifndef SPIS0_ENABLED
 #define SPIS0_ENABLED 0
 #endif
 
 //  SPIS1_ENABLED  - Enable SPIS1 instance
- 
+
 
 #ifndef SPIS1_ENABLED
 #define SPIS1_ENABLED 0
 #endif
 
 //  SPIS2_ENABLED  - Enable SPIS2 instance
- 
+
 
 #ifndef SPIS2_ENABLED
 #define SPIS2_ENABLED 0
@@ -5403,27 +5403,27 @@
 #define SPI_ENABLED 0
 #endif
 //  SPI_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef SPI_DEFAULT_CONFIG_IRQ_PRIORITY
 #define SPI_DEFAULT_CONFIG_IRQ_PRIORITY 6
 #endif
 
 //  NRF_SPI_DRV_MISO_PULLUP_CFG  - MISO PIN pull-up configuration.
- 
-// <0=> NRF_GPIO_PIN_NOPULL 
-// <1=> NRF_GPIO_PIN_PULLDOWN 
-// <3=> NRF_GPIO_PIN_PULLUP 
+
+// <0=> NRF_GPIO_PIN_NOPULL
+// <1=> NRF_GPIO_PIN_PULLDOWN
+// <3=> NRF_GPIO_PIN_PULLUP
 
 #ifndef NRF_SPI_DRV_MISO_PULLUP_CFG
 #define NRF_SPI_DRV_MISO_PULLUP_CFG 1
@@ -5435,7 +5435,7 @@
 #define SPI0_ENABLED 0
 #endif
 //  SPI0_USE_EASY_DMA  - Use EasyDMA
- 
+
 
 #ifndef SPI0_USE_EASY_DMA
 #define SPI0_USE_EASY_DMA 1
@@ -5449,7 +5449,7 @@
 #define SPI1_ENABLED 0
 #endif
 //  SPI1_USE_EASY_DMA  - Use EasyDMA
- 
+
 
 #ifndef SPI1_USE_EASY_DMA
 #define SPI1_USE_EASY_DMA 1
@@ -5463,7 +5463,7 @@
 #define SPI2_ENABLED 0
 #endif
 //  SPI2_USE_EASY_DMA  - Use EasyDMA
- 
+
 
 #ifndef SPI2_USE_EASY_DMA
 #define SPI2_USE_EASY_DMA 1
@@ -5479,89 +5479,89 @@
 #define TIMER_ENABLED 0
 #endif
 //  TIMER_DEFAULT_CONFIG_FREQUENCY  - Timer frequency if in Timer mode
- 
-// <0=> 16 MHz 
-// <1=> 8 MHz 
-// <2=> 4 MHz 
-// <3=> 2 MHz 
-// <4=> 1 MHz 
-// <5=> 500 kHz 
-// <6=> 250 kHz 
-// <7=> 125 kHz 
-// <8=> 62.5 kHz 
-// <9=> 31.25 kHz 
+
+// <0=> 16 MHz
+// <1=> 8 MHz
+// <2=> 4 MHz
+// <3=> 2 MHz
+// <4=> 1 MHz
+// <5=> 500 kHz
+// <6=> 250 kHz
+// <7=> 125 kHz
+// <8=> 62.5 kHz
+// <9=> 31.25 kHz
 
 #ifndef TIMER_DEFAULT_CONFIG_FREQUENCY
 #define TIMER_DEFAULT_CONFIG_FREQUENCY 0
 #endif
 
 //  TIMER_DEFAULT_CONFIG_MODE  - Timer mode or operation
- 
-// <0=> Timer 
-// <1=> Counter 
+
+// <0=> Timer
+// <1=> Counter
 
 #ifndef TIMER_DEFAULT_CONFIG_MODE
 #define TIMER_DEFAULT_CONFIG_MODE 0
 #endif
 
 //  TIMER_DEFAULT_CONFIG_BIT_WIDTH  - Timer counter bit width
- 
-// <0=> 16 bit 
-// <1=> 8 bit 
-// <2=> 24 bit 
-// <3=> 32 bit 
+
+// <0=> 16 bit
+// <1=> 8 bit
+// <2=> 24 bit
+// <3=> 32 bit
 
 #ifndef TIMER_DEFAULT_CONFIG_BIT_WIDTH
 #define TIMER_DEFAULT_CONFIG_BIT_WIDTH 0
 #endif
 
 //  TIMER_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
 #define TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 6
 #endif
 
 //  TIMER0_ENABLED  - Enable TIMER0 instance
- 
+
 
 #ifndef TIMER0_ENABLED
 #define TIMER0_ENABLED 0
 #endif
 
 //  TIMER1_ENABLED  - Enable TIMER1 instance
- 
+
 
 #ifndef TIMER1_ENABLED
 #define TIMER1_ENABLED 0
 #endif
 
 //  TIMER2_ENABLED  - Enable TIMER2 instance
- 
+
 
 #ifndef TIMER2_ENABLED
 #define TIMER2_ENABLED 0
 #endif
 
 //  TIMER3_ENABLED  - Enable TIMER3 instance
- 
+
 
 #ifndef TIMER3_ENABLED
 #define TIMER3_ENABLED 0
 #endif
 
 //  TIMER4_ENABLED  - Enable TIMER4 instance
- 
+
 
 #ifndef TIMER4_ENABLED
 #define TIMER4_ENABLED 0
@@ -5575,21 +5575,21 @@
 #define TWIS_ENABLED 0
 #endif
 //  TWIS0_ENABLED  - Enable TWIS0 instance
- 
+
 
 #ifndef TWIS0_ENABLED
 #define TWIS0_ENABLED 0
 #endif
 
 //  TWIS1_ENABLED  - Enable TWIS1 instance
- 
+
 
 #ifndef TWIS1_ENABLED
 #define TWIS1_ENABLED 0
 #endif
 
 //  TWIS_ASSUME_INIT_AFTER_RESET_ONLY  - Assume that any instance would be initialized only once
- 
+
 
 //  Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code.
 
@@ -5598,7 +5598,7 @@
 #endif
 
 //  TWIS_NO_SYNC_MODE  - Remove support for synchronous mode
- 
+
 
 //  Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources.
 
@@ -5606,48 +5606,48 @@
 #define TWIS_NO_SYNC_MODE 0
 #endif
 
-//  TWIS_DEFAULT_CONFIG_ADDR0 - Address0 
+//  TWIS_DEFAULT_CONFIG_ADDR0 - Address0
 #ifndef TWIS_DEFAULT_CONFIG_ADDR0
 #define TWIS_DEFAULT_CONFIG_ADDR0 0
 #endif
 
-//  TWIS_DEFAULT_CONFIG_ADDR1 - Address1 
+//  TWIS_DEFAULT_CONFIG_ADDR1 - Address1
 #ifndef TWIS_DEFAULT_CONFIG_ADDR1
 #define TWIS_DEFAULT_CONFIG_ADDR1 0
 #endif
 
 //  TWIS_DEFAULT_CONFIG_SCL_PULL  - SCL pin pull configuration
- 
-// <0=> Disabled 
-// <1=> Pull down 
-// <3=> Pull up 
+
+// <0=> Disabled
+// <1=> Pull down
+// <3=> Pull up
 
 #ifndef TWIS_DEFAULT_CONFIG_SCL_PULL
 #define TWIS_DEFAULT_CONFIG_SCL_PULL 0
 #endif
 
 //  TWIS_DEFAULT_CONFIG_SDA_PULL  - SDA pin pull configuration
- 
-// <0=> Disabled 
-// <1=> Pull down 
-// <3=> Pull up 
+
+// <0=> Disabled
+// <1=> Pull down
+// <3=> Pull up
 
 #ifndef TWIS_DEFAULT_CONFIG_SDA_PULL
 #define TWIS_DEFAULT_CONFIG_SDA_PULL 0
 #endif
 
 //  TWIS_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
 #define TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 6
@@ -5661,41 +5661,41 @@
 #define TWI_ENABLED 0
 #endif
 //  TWI_DEFAULT_CONFIG_FREQUENCY  - Frequency
- 
-// <26738688=> 100k 
-// <67108864=> 250k 
-// <104857600=> 400k 
+
+// <26738688=> 100k
+// <67108864=> 250k
+// <104857600=> 400k
 
 #ifndef TWI_DEFAULT_CONFIG_FREQUENCY
 #define TWI_DEFAULT_CONFIG_FREQUENCY 26738688
 #endif
 
 //  TWI_DEFAULT_CONFIG_CLR_BUS_INIT  - Enables bus clearing procedure during init
- 
+
 
 #ifndef TWI_DEFAULT_CONFIG_CLR_BUS_INIT
 #define TWI_DEFAULT_CONFIG_CLR_BUS_INIT 0
 #endif
 
 //  TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT  - Enables bus holding after uninit
- 
+
 
 #ifndef TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT
 #define TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0
 #endif
 
 //  TWI_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef TWI_DEFAULT_CONFIG_IRQ_PRIORITY
 #define TWI_DEFAULT_CONFIG_IRQ_PRIORITY 6
@@ -5707,7 +5707,7 @@
 #define TWI0_ENABLED 0
 #endif
 //  TWI0_USE_EASY_DMA  - Use EasyDMA (if present)
- 
+
 
 #ifndef TWI0_USE_EASY_DMA
 #define TWI0_USE_EASY_DMA 0
@@ -5721,7 +5721,7 @@
 #define TWI1_ENABLED 0
 #endif
 //  TWI1_USE_EASY_DMA  - Use EasyDMA (if present)
- 
+
 
 #ifndef TWI1_USE_EASY_DMA
 #define TWI1_USE_EASY_DMA 0
@@ -5737,72 +5737,72 @@
 #define UART_ENABLED 0
 #endif
 //  UART_DEFAULT_CONFIG_HWFC  - Hardware Flow Control
- 
-// <0=> Disabled 
-// <1=> Enabled 
+
+// <0=> Disabled
+// <1=> Enabled
 
 #ifndef UART_DEFAULT_CONFIG_HWFC
 #define UART_DEFAULT_CONFIG_HWFC 0
 #endif
 
 //  UART_DEFAULT_CONFIG_PARITY  - Parity
- 
-// <0=> Excluded 
-// <14=> Included 
+
+// <0=> Excluded
+// <14=> Included
 
 #ifndef UART_DEFAULT_CONFIG_PARITY
 #define UART_DEFAULT_CONFIG_PARITY 0
 #endif
 
 //  UART_DEFAULT_CONFIG_BAUDRATE  - Default Baudrate
- 
-// <323584=> 1200 baud 
-// <643072=> 2400 baud 
-// <1290240=> 4800 baud 
-// <2576384=> 9600 baud 
-// <3862528=> 14400 baud 
-// <5152768=> 19200 baud 
-// <7716864=> 28800 baud 
-// <10289152=> 38400 baud 
-// <15400960=> 57600 baud 
-// <20615168=> 76800 baud 
-// <30801920=> 115200 baud 
-// <61865984=> 230400 baud 
-// <67108864=> 250000 baud 
-// <121634816=> 460800 baud 
-// <251658240=> 921600 baud 
-// <268435456=> 1000000 baud 
+
+// <323584=> 1200 baud
+// <643072=> 2400 baud
+// <1290240=> 4800 baud
+// <2576384=> 9600 baud
+// <3862528=> 14400 baud
+// <5152768=> 19200 baud
+// <7716864=> 28800 baud
+// <10289152=> 38400 baud
+// <15400960=> 57600 baud
+// <20615168=> 76800 baud
+// <30801920=> 115200 baud
+// <61865984=> 230400 baud
+// <67108864=> 250000 baud
+// <121634816=> 460800 baud
+// <251658240=> 921600 baud
+// <268435456=> 1000000 baud
 
 #ifndef UART_DEFAULT_CONFIG_BAUDRATE
 #define UART_DEFAULT_CONFIG_BAUDRATE 30801920
 #endif
 
 //  UART_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef UART_DEFAULT_CONFIG_IRQ_PRIORITY
 #define UART_DEFAULT_CONFIG_IRQ_PRIORITY 6
 #endif
 
 //  UART_EASY_DMA_SUPPORT  - Driver supporting EasyDMA
- 
+
 
 #ifndef UART_EASY_DMA_SUPPORT
 #define UART_EASY_DMA_SUPPORT 1
 #endif
 
 //  UART_LEGACY_SUPPORT  - Driver supporting Legacy mode
- 
+
 
 #ifndef UART_LEGACY_SUPPORT
 #define UART_LEGACY_SUPPORT 1
@@ -5814,7 +5814,7 @@
 #define UART0_ENABLED 0
 #endif
 //  UART0_CONFIG_USE_EASY_DMA  - Default setting for using EasyDMA
- 
+
 
 #ifndef UART0_CONFIG_USE_EASY_DMA
 #define UART0_CONFIG_USE_EASY_DMA 1
@@ -5837,33 +5837,33 @@
 #define USBD_ENABLED 0
 #endif
 //  USBD_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef USBD_CONFIG_IRQ_PRIORITY
 #define USBD_CONFIG_IRQ_PRIORITY 6
 #endif
 
 //  USBD_CONFIG_DMASCHEDULER_MODE  - USBD SMA scheduler working scheme
- 
-// <0=> Prioritized access 
-// <1=> Round Robin 
+
+// <0=> Prioritized access
+// <1=> Round Robin
 
 #ifndef USBD_CONFIG_DMASCHEDULER_MODE
 #define USBD_CONFIG_DMASCHEDULER_MODE 0
 #endif
 
 //  USBD_CONFIG_DMASCHEDULER_ISO_BOOST  - Give priority to isochronous transfers
- 
+
 
 //  This option gives priority to isochronous transfers.
 //  Enabling it assures that isochronous transfers are always processed,
@@ -5876,7 +5876,7 @@
 #endif
 
 //  USBD_CONFIG_ISO_IN_ZLP  - Respond to an IN token on ISO IN endpoint with ZLP when no data is ready
- 
+
 
 //  If set, ISO IN endpoint will respond to an IN token with ZLP when no data is ready to be sent.
 //  Else, there will be no response.
@@ -5894,17 +5894,17 @@
 #define WDT_ENABLED 0
 #endif
 //  WDT_CONFIG_BEHAVIOUR  - WDT behavior in CPU SLEEP or HALT mode
- 
-// <1=> Run in SLEEP, Pause in HALT 
-// <8=> Pause in SLEEP, Run in HALT 
-// <9=> Run in SLEEP and HALT 
-// <0=> Pause in SLEEP and HALT 
+
+// <1=> Run in SLEEP, Pause in HALT
+// <8=> Pause in SLEEP, Run in HALT
+// <9=> Run in SLEEP and HALT
+// <0=> Pause in SLEEP and HALT
 
 #ifndef WDT_CONFIG_BEHAVIOUR
 #define WDT_CONFIG_BEHAVIOUR 1
 #endif
 
-//  WDT_CONFIG_RELOAD_VALUE - Reload value  <15-4294967295> 
+//  WDT_CONFIG_RELOAD_VALUE - Reload value  <15-4294967295>
 
 
 #ifndef WDT_CONFIG_RELOAD_VALUE
@@ -5912,17 +5912,17 @@
 #endif
 
 //  WDT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef WDT_CONFIG_IRQ_PRIORITY
 #define WDT_CONFIG_IRQ_PRIORITY 6
@@ -5930,34 +5930,34 @@
 
 // 
 
-//  
+// 
 //==========================================================
 
-//  nRF_Drivers_External 
+//  nRF_Drivers_External
 
 //==========================================================
 //  NRF_TWI_SENSOR_ENABLED  - nrf_twi_sensor - nRF TWI Sensor module
- 
+
 
 #ifndef NRF_TWI_SENSOR_ENABLED
 #define NRF_TWI_SENSOR_ENABLED 0
 #endif
 
-//  
+// 
 //==========================================================
 
-//  nRF_Libraries 
+//  nRF_Libraries
 
 //==========================================================
 //  APP_GPIOTE_ENABLED  - app_gpiote - GPIOTE events dispatcher
- 
+
 
 #ifndef APP_GPIOTE_ENABLED
 #define APP_GPIOTE_ENABLED 0
 #endif
 
 //  APP_PWM_ENABLED  - app_pwm - PWM functionality
- 
+
 
 #ifndef APP_PWM_ENABLED
 #define APP_PWM_ENABLED 0
@@ -5969,14 +5969,14 @@
 #define APP_SCHEDULER_ENABLED 0
 #endif
 //  APP_SCHEDULER_WITH_PAUSE  - Enabling pause feature
- 
+
 
 #ifndef APP_SCHEDULER_WITH_PAUSE
 #define APP_SCHEDULER_WITH_PAUSE 0
 #endif
 
 //  APP_SCHEDULER_WITH_PROFILER  - Enabling scheduler profiling
- 
+
 
 #ifndef APP_SCHEDULER_WITH_PROFILER
 #define APP_SCHEDULER_WITH_PROFILER 0
@@ -5990,38 +5990,38 @@
 #define APP_SDCARD_ENABLED 0
 #endif
 //  APP_SDCARD_SPI_INSTANCE  - SPI instance used
- 
-// <0=> 0 
-// <1=> 1 
-// <2=> 2 
+
+// <0=> 0
+// <1=> 1
+// <2=> 2
 
 #ifndef APP_SDCARD_SPI_INSTANCE
 #define APP_SDCARD_SPI_INSTANCE 0
 #endif
 
 //  APP_SDCARD_FREQ_INIT  - SPI frequency
- 
-// <33554432=> 125 kHz 
-// <67108864=> 250 kHz 
-// <134217728=> 500 kHz 
-// <268435456=> 1 MHz 
-// <536870912=> 2 MHz 
-// <1073741824=> 4 MHz 
-// <2147483648=> 8 MHz 
+
+// <33554432=> 125 kHz
+// <67108864=> 250 kHz
+// <134217728=> 500 kHz
+// <268435456=> 1 MHz
+// <536870912=> 2 MHz
+// <1073741824=> 4 MHz
+// <2147483648=> 8 MHz
 
 #ifndef APP_SDCARD_FREQ_INIT
 #define APP_SDCARD_FREQ_INIT 67108864
 #endif
 
 //  APP_SDCARD_FREQ_DATA  - SPI frequency
- 
-// <33554432=> 125 kHz 
-// <67108864=> 250 kHz 
-// <134217728=> 500 kHz 
-// <268435456=> 1 MHz 
-// <536870912=> 2 MHz 
-// <1073741824=> 4 MHz 
-// <2147483648=> 8 MHz 
+
+// <33554432=> 125 kHz
+// <67108864=> 250 kHz
+// <134217728=> 500 kHz
+// <268435456=> 1 MHz
+// <536870912=> 2 MHz
+// <1073741824=> 4 MHz
+// <2147483648=> 8 MHz
 
 #ifndef APP_SDCARD_FREQ_DATA
 #define APP_SDCARD_FREQ_DATA 1073741824
@@ -6035,36 +6035,36 @@
 #define APP_TIMER_ENABLED 0
 #endif
 //  APP_TIMER_CONFIG_RTC_FREQUENCY  - Configure RTC prescaler.
- 
-// <0=> 32768 Hz 
-// <1=> 16384 Hz 
-// <3=> 8192 Hz 
-// <7=> 4096 Hz 
-// <15=> 2048 Hz 
-// <31=> 1024 Hz 
+
+// <0=> 32768 Hz
+// <1=> 16384 Hz
+// <3=> 8192 Hz
+// <7=> 4096 Hz
+// <15=> 2048 Hz
+// <31=> 1024 Hz
 
 #ifndef APP_TIMER_CONFIG_RTC_FREQUENCY
 #define APP_TIMER_CONFIG_RTC_FREQUENCY 1
 #endif
 
 //  APP_TIMER_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef APP_TIMER_CONFIG_IRQ_PRIORITY
 #define APP_TIMER_CONFIG_IRQ_PRIORITY 6
 #endif
 
-//  APP_TIMER_CONFIG_OP_QUEUE_SIZE - Capacity of timer requests queue. 
+//  APP_TIMER_CONFIG_OP_QUEUE_SIZE - Capacity of timer requests queue.
 //  Size of the queue depends on how many timers are used
 //  in the system, how often timers are started and overall
 //  system latency. If queue size is too small app_timer calls
@@ -6075,14 +6075,14 @@
 #endif
 
 //  APP_TIMER_CONFIG_USE_SCHEDULER  - Enable scheduling app_timer events to app_scheduler
- 
+
 
 #ifndef APP_TIMER_CONFIG_USE_SCHEDULER
 #define APP_TIMER_CONFIG_USE_SCHEDULER 0
 #endif
 
 //  APP_TIMER_KEEPS_RTC_ACTIVE  - Enable RTC always on
- 
+
 
 //  If option is enabled RTC is kept running even if there is no active timers.
 //  This option can be used when app_timer is used for timestamping.
@@ -6091,7 +6091,7 @@
 #define APP_TIMER_KEEPS_RTC_ACTIVE 0
 #endif
 
-//  APP_TIMER_SAFE_WINDOW_MS - Maximum possible latency (in milliseconds) of handling app_timer event. 
+//  APP_TIMER_SAFE_WINDOW_MS - Maximum possible latency (in milliseconds) of handling app_timer event.
 //  Maximum possible timeout that can be set is reduced by safe window.
 //  Example: RTC frequency 16384 Hz, maximum possible timeout 1024 seconds - APP_TIMER_SAFE_WINDOW_MS.
 //  Since RTC is not stopped when processor is halted in debugging session, this value
@@ -6106,26 +6106,26 @@
 
 //==========================================================
 //  APP_TIMER_WITH_PROFILER  - Enable app_timer profiling
- 
+
 
 #ifndef APP_TIMER_WITH_PROFILER
 #define APP_TIMER_WITH_PROFILER 0
 #endif
 
 //  APP_TIMER_CONFIG_SWI_NUMBER  - Configure SWI instance used.
- 
+
 
 #ifndef APP_TIMER_CONFIG_SWI_NUMBER
 #define APP_TIMER_CONFIG_SWI_NUMBER 0
 #endif
 
-//  
+// 
 //==========================================================
 
 // 
 
 //  APP_USBD_AUDIO_ENABLED  - app_usbd_audio - USB AUDIO class
- 
+
 
 #ifndef APP_USBD_AUDIO_ENABLED
 #define APP_USBD_AUDIO_ENABLED 0
@@ -6136,7 +6136,7 @@
 #ifndef APP_USBD_ENABLED
 #define APP_USBD_ENABLED 0
 #endif
-//  APP_USBD_VID - Vendor ID.  <0x0000-0xFFFF> 
+//  APP_USBD_VID - Vendor ID.  <0x0000-0xFFFF>
 
 
 //  Note: This value is not editable in Configuration Wizard.
@@ -6146,7 +6146,7 @@
 #define APP_USBD_VID 0
 #endif
 
-//  APP_USBD_PID - Product ID.  <0x0000-0xFFFF> 
+//  APP_USBD_PID - Product ID.  <0x0000-0xFFFF>
 
 
 //  Note: This value is not editable in Configuration Wizard.
@@ -6156,7 +6156,7 @@
 #define APP_USBD_PID 0
 #endif
 
-//  APP_USBD_DEVICE_VER_MAJOR - Major device version  <0-99> 
+//  APP_USBD_DEVICE_VER_MAJOR - Major device version  <0-99>
 
 
 //  Major device version, will be converted automatically to BCD notation. Use just decimal values.
@@ -6165,7 +6165,7 @@
 #define APP_USBD_DEVICE_VER_MAJOR 1
 #endif
 
-//  APP_USBD_DEVICE_VER_MINOR - Minor device version  <0-9> 
+//  APP_USBD_DEVICE_VER_MINOR - Minor device version  <0-9>
 
 
 //  Minor device version, will be converted automatically to BCD notation. Use just decimal values.
@@ -6174,7 +6174,7 @@
 #define APP_USBD_DEVICE_VER_MINOR 0
 #endif
 
-//  APP_USBD_DEVICE_VER_SUB - Sub-minor device version  <0-9> 
+//  APP_USBD_DEVICE_VER_SUB - Sub-minor device version  <0-9>
 
 
 //  Sub-minor device version, will be converted automatically to BCD notation. Use just decimal values.
@@ -6184,13 +6184,13 @@
 #endif
 
 //  APP_USBD_CONFIG_SELF_POWERED  - Self-powered device, as opposed to bus-powered.
- 
+
 
 #ifndef APP_USBD_CONFIG_SELF_POWERED
 #define APP_USBD_CONFIG_SELF_POWERED 1
 #endif
 
-//  APP_USBD_CONFIG_MAX_POWER - MaxPower field in configuration descriptor in milliamps.  <0-500> 
+//  APP_USBD_CONFIG_MAX_POWER - MaxPower field in configuration descriptor in milliamps.  <0-500>
 
 
 #ifndef APP_USBD_CONFIG_MAX_POWER
@@ -6198,7 +6198,7 @@
 #endif
 
 //  APP_USBD_CONFIG_POWER_EVENTS_PROCESS  - Process power events.
- 
+
 
 //  Enable processing power events in USB event handler.
 
@@ -6216,7 +6216,7 @@
 #ifndef APP_USBD_CONFIG_EVENT_QUEUE_ENABLE
 #define APP_USBD_CONFIG_EVENT_QUEUE_ENABLE 1
 #endif
-//  APP_USBD_CONFIG_EVENT_QUEUE_SIZE - The size of the event queue.  <16-64> 
+//  APP_USBD_CONFIG_EVENT_QUEUE_SIZE - The size of the event queue.  <16-64>
 
 
 //  The size of the queue for the events that would be processed in the main loop.
@@ -6226,15 +6226,15 @@
 #endif
 
 //  APP_USBD_CONFIG_SOF_HANDLING_MODE  - Change SOF events handling mode.
- 
+
 
 //  Normal queue   - SOF events are pushed normally into the event queue.
 //  Compress queue - SOF events are counted and binded with other events or executed when the queue is empty.
 //                   This prevents the queue from filling up with SOF events.
 //  Interrupt      - SOF events are processed in interrupt.
-// <0=> Normal queue 
-// <1=> Compress queue 
-// <2=> Interrupt 
+// <0=> Normal queue
+// <1=> Compress queue
+// <2=> Interrupt
 
 #ifndef APP_USBD_CONFIG_SOF_HANDLING_MODE
 #define APP_USBD_CONFIG_SOF_HANDLING_MODE 1
@@ -6243,19 +6243,19 @@
 // 
 
 //  APP_USBD_CONFIG_SOF_TIMESTAMP_PROVIDE  - Provide a function that generates timestamps for logs based on the current SOF.
- 
 
-//  The function app_usbd_sof_timestamp_get is implemented if the logger is enabled. 
-//  Use it when initializing the logger. 
-//  SOF processing is always enabled when this configuration parameter is active. 
-//  Note: This option is configured outside of APP_USBD_CONFIG_LOG_ENABLED. 
-//  This means that it works even if the logging in this very module is disabled. 
+
+//  The function app_usbd_sof_timestamp_get is implemented if the logger is enabled.
+//  Use it when initializing the logger.
+//  SOF processing is always enabled when this configuration parameter is active.
+//  Note: This option is configured outside of APP_USBD_CONFIG_LOG_ENABLED.
+//  This means that it works even if the logging in this very module is disabled.
 
 #ifndef APP_USBD_CONFIG_SOF_TIMESTAMP_PROVIDE
 #define APP_USBD_CONFIG_SOF_TIMESTAMP_PROVIDE 0
 #endif
 
-//  APP_USBD_CONFIG_DESC_STRING_SIZE - Maximum size of the NULL-terminated string of the string descriptor.  <31-254> 
+//  APP_USBD_CONFIG_DESC_STRING_SIZE - Maximum size of the NULL-terminated string of the string descriptor.  <31-254>
 
 
 //  31 characters can be stored in the internal USB buffer used for transfers.
@@ -6266,7 +6266,7 @@
 #endif
 
 //  APP_USBD_CONFIG_DESC_STRING_UTF_ENABLED  - Enable UTF8 conversion.
- 
+
 
 //  Enable UTF8-encoded characters. In normal processing, only ASCII characters are available.
 
@@ -6290,7 +6290,7 @@
 #define APP_USBD_STRING_ID_MANUFACTURER 1
 #endif
 //  APP_USBD_STRINGS_MANUFACTURER_EXTERN  - Define whether @ref APP_USBD_STRINGS_MANUFACTURER is created by macro or declared as a global variable.
- 
+
 
 #ifndef APP_USBD_STRINGS_MANUFACTURER_EXTERN
 #define APP_USBD_STRINGS_MANUFACTURER_EXTERN 0
@@ -6320,7 +6320,7 @@
 #define APP_USBD_STRING_ID_PRODUCT 2
 #endif
 //  APP_USBD_STRINGS_PRODUCT_EXTERN  - Define whether @ref APP_USBD_STRINGS_PRODUCT is created by macro or declared as a global variable.
- 
+
 
 #ifndef APP_USBD_STRINGS_PRODUCT_EXTERN
 #define APP_USBD_STRINGS_PRODUCT_EXTERN 0
@@ -6344,7 +6344,7 @@
 #define APP_USBD_STRING_ID_SERIAL 3
 #endif
 //  APP_USBD_STRING_SERIAL_EXTERN  - Define whether @ref APP_USBD_STRING_SERIAL is created by macro or declared as a global variable.
- 
+
 
 #ifndef APP_USBD_STRING_SERIAL_EXTERN
 #define APP_USBD_STRING_SERIAL_EXTERN 0
@@ -6368,7 +6368,7 @@
 #define APP_USBD_STRING_ID_CONFIGURATION 4
 #endif
 //  APP_USBD_STRING_CONFIGURATION_EXTERN  - Define whether @ref APP_USBD_STRINGS_CONFIGURATION is created by macro or declared as global variable.
- 
+
 
 #ifndef APP_USBD_STRING_CONFIGURATION_EXTERN
 #define APP_USBD_STRING_CONFIGURATION_EXTERN 0
@@ -6410,7 +6410,7 @@
 #ifndef APP_USBD_HID_ENABLED
 #define APP_USBD_HID_ENABLED 0
 #endif
-//  APP_USBD_HID_DEFAULT_IDLE_RATE - Default idle rate for HID class.   <0-255> 
+//  APP_USBD_HID_DEFAULT_IDLE_RATE - Default idle rate for HID class.   <0-255>
 
 
 //  0 means indefinite duration, any other value is multiplied by 4 milliseconds. Refer to Chapter 7.2.4 of HID 1.11 Specification.
@@ -6419,7 +6419,7 @@
 #define APP_USBD_HID_DEFAULT_IDLE_RATE 0
 #endif
 
-//  APP_USBD_HID_REPORT_IDLE_TABLE_SIZE - Size of idle rate table.   <1-255> 
+//  APP_USBD_HID_REPORT_IDLE_TABLE_SIZE - Size of idle rate table.   <1-255>
 
 
 //  Must be higher than the highest report ID used.
@@ -6431,49 +6431,49 @@
 // 
 
 //  APP_USBD_HID_GENERIC_ENABLED  - app_usbd_hid_generic - USB HID generic
- 
+
 
 #ifndef APP_USBD_HID_GENERIC_ENABLED
 #define APP_USBD_HID_GENERIC_ENABLED 0
 #endif
 
 //  APP_USBD_HID_KBD_ENABLED  - app_usbd_hid_kbd - USB HID keyboard
- 
+
 
 #ifndef APP_USBD_HID_KBD_ENABLED
 #define APP_USBD_HID_KBD_ENABLED 0
 #endif
 
 //  APP_USBD_HID_MOUSE_ENABLED  - app_usbd_hid_mouse - USB HID mouse
- 
+
 
 #ifndef APP_USBD_HID_MOUSE_ENABLED
 #define APP_USBD_HID_MOUSE_ENABLED 0
 #endif
 
 //  APP_USBD_MSC_ENABLED  - app_usbd_msc - USB MSC class
- 
+
 
 #ifndef APP_USBD_MSC_ENABLED
 #define APP_USBD_MSC_ENABLED 0
 #endif
 
 //  CRC16_ENABLED  - crc16 - CRC16 calculation routines
- 
+
 
 #ifndef CRC16_ENABLED
 #define CRC16_ENABLED 0
 #endif
 
 //  CRC32_ENABLED  - crc32 - CRC32 calculation routines
- 
+
 
 #ifndef CRC32_ENABLED
 #define CRC32_ENABLED 0
 #endif
 
 //  ECC_ENABLED  - ecc - Elliptic Curve Cryptography Library
- 
+
 
 #ifndef ECC_ENABLED
 #define ECC_ENABLED 0
@@ -6488,7 +6488,7 @@
 
 //  Configure the number of virtual pages to use and their size.
 //==========================================================
-//  FDS_VIRTUAL_PAGES - Number of virtual flash pages to use. 
+//  FDS_VIRTUAL_PAGES - Number of virtual flash pages to use.
 //  One of the virtual pages is reserved by the system for garbage collection.
 //  Therefore, the minimum is two virtual pages: one page to store data and one page to be used by the system for garbage collection.
 //  The total amount of flash memory that is used by FDS amounts to @ref FDS_VIRTUAL_PAGES * @ref FDS_VIRTUAL_PAGE_SIZE * 4 bytes.
@@ -6498,19 +6498,19 @@
 #endif
 
 //  FDS_VIRTUAL_PAGE_SIZE  - The size of a virtual flash page.
- 
+
 
 //  Expressed in number of 4-byte words.
 //  By default, a virtual page is the same size as a physical page.
 //  The size of a virtual page must be a multiple of the size of a physical page.
-// <1024=> 1024 
-// <2048=> 2048 
+// <1024=> 1024
+// <2048=> 2048
 
 #ifndef FDS_VIRTUAL_PAGE_SIZE
 #define FDS_VIRTUAL_PAGE_SIZE 1024
 #endif
 
-//  FDS_VIRTUAL_PAGES_RESERVED - The number of virtual flash pages that are used by other modules. 
+//  FDS_VIRTUAL_PAGES_RESERVED - The number of virtual flash pages that are used by other modules.
 //  FDS module stores its data in the last pages of the flash memory.
 //  By setting this value, you can move flash end address used by the FDS.
 //  As a result the reserved space can be used by other modules.
@@ -6519,7 +6519,7 @@
 #define FDS_VIRTUAL_PAGES_RESERVED 0
 #endif
 
-//  
+// 
 //==========================================================
 
 //  Backend - Backend configuration
@@ -6527,31 +6527,31 @@
 //  Configure which nrf_fstorage backend is used by FDS to write to flash.
 //==========================================================
 //  FDS_BACKEND  - FDS flash backend.
- 
+
 
 //  NRF_FSTORAGE_SD uses the nrf_fstorage_sd backend implementation using the SoftDevice API. Use this if you have a SoftDevice present.
 //  NRF_FSTORAGE_NVMC uses the nrf_fstorage_nvmc implementation. Use this setting if you don't use the SoftDevice.
-// <1=> NRF_FSTORAGE_NVMC 
-// <2=> NRF_FSTORAGE_SD 
+// <1=> NRF_FSTORAGE_NVMC
+// <2=> NRF_FSTORAGE_SD
 
 #ifndef FDS_BACKEND
 #define FDS_BACKEND 2
 #endif
 
-//  
+// 
 //==========================================================
 
 //  Queue - Queue settings
 
 //==========================================================
-//  FDS_OP_QUEUE_SIZE - Size of the internal queue. 
+//  FDS_OP_QUEUE_SIZE - Size of the internal queue.
 //  Increase this value if you frequently get synchronous FDS_ERR_NO_SPACE_IN_QUEUES errors.
 
 #ifndef FDS_OP_QUEUE_SIZE
 #define FDS_OP_QUEUE_SIZE 4
 #endif
 
-//  
+// 
 //==========================================================
 
 //  CRC - CRC functionality
@@ -6567,12 +6567,12 @@
 #define FDS_CRC_CHECK_ON_READ 0
 #endif
 //  FDS_CRC_CHECK_ON_WRITE  - Perform a CRC check on newly written records.
- 
+
 
 //  Perform a CRC check on newly written records.
 //  This setting can be used to make sure that the record data was not altered while being written to flash.
-// <1=> Enabled 
-// <0=> Disabled 
+// <1=> Enabled
+// <0=> Disabled
 
 #ifndef FDS_CRC_CHECK_ON_WRITE
 #define FDS_CRC_CHECK_ON_WRITE 0
@@ -6580,24 +6580,24 @@
 
 // 
 
-//  
+// 
 //==========================================================
 
 //  Users - Number of users
 
 //==========================================================
-//  FDS_MAX_USERS - Maximum number of callbacks that can be registered. 
+//  FDS_MAX_USERS - Maximum number of callbacks that can be registered.
 #ifndef FDS_MAX_USERS
 #define FDS_MAX_USERS 4
 #endif
 
-//  
+// 
 //==========================================================
 
 // 
 
 //  HARDFAULT_HANDLER_ENABLED  - hardfault_default - HardFault default handler for debugging and release
- 
+
 
 #ifndef HARDFAULT_HANDLER_ENABLED
 #define HARDFAULT_HANDLER_ENABLED 0
@@ -6608,17 +6608,17 @@
 #ifndef HCI_MEM_POOL_ENABLED
 #define HCI_MEM_POOL_ENABLED 0
 #endif
-//  HCI_TX_BUF_SIZE - TX buffer size in bytes. 
+//  HCI_TX_BUF_SIZE - TX buffer size in bytes.
 #ifndef HCI_TX_BUF_SIZE
 #define HCI_TX_BUF_SIZE 600
 #endif
 
-//  HCI_RX_BUF_SIZE - RX buffer size in bytes. 
+//  HCI_RX_BUF_SIZE - RX buffer size in bytes.
 #ifndef HCI_RX_BUF_SIZE
 #define HCI_RX_BUF_SIZE 600
 #endif
 
-//  HCI_RX_BUF_QUEUE_SIZE - RX buffer queue size. 
+//  HCI_RX_BUF_QUEUE_SIZE - RX buffer queue size.
 #ifndef HCI_RX_BUF_QUEUE_SIZE
 #define HCI_RX_BUF_QUEUE_SIZE 4
 #endif
@@ -6631,53 +6631,53 @@
 #define HCI_SLIP_ENABLED 0
 #endif
 //  HCI_UART_BAUDRATE  - Default Baudrate
- 
-// <323584=> 1200 baud 
-// <643072=> 2400 baud 
-// <1290240=> 4800 baud 
-// <2576384=> 9600 baud 
-// <3862528=> 14400 baud 
-// <5152768=> 19200 baud 
-// <7716864=> 28800 baud 
-// <10289152=> 38400 baud 
-// <15400960=> 57600 baud 
-// <20615168=> 76800 baud 
-// <30801920=> 115200 baud 
-// <61865984=> 230400 baud 
-// <67108864=> 250000 baud 
-// <121634816=> 460800 baud 
-// <251658240=> 921600 baud 
-// <268435456=> 1000000 baud 
+
+// <323584=> 1200 baud
+// <643072=> 2400 baud
+// <1290240=> 4800 baud
+// <2576384=> 9600 baud
+// <3862528=> 14400 baud
+// <5152768=> 19200 baud
+// <7716864=> 28800 baud
+// <10289152=> 38400 baud
+// <15400960=> 57600 baud
+// <20615168=> 76800 baud
+// <30801920=> 115200 baud
+// <61865984=> 230400 baud
+// <67108864=> 250000 baud
+// <121634816=> 460800 baud
+// <251658240=> 921600 baud
+// <268435456=> 1000000 baud
 
 #ifndef HCI_UART_BAUDRATE
 #define HCI_UART_BAUDRATE 30801920
 #endif
 
 //  HCI_UART_FLOW_CONTROL  - Hardware Flow Control
- 
-// <0=> Disabled 
-// <1=> Enabled 
+
+// <0=> Disabled
+// <1=> Enabled
 
 #ifndef HCI_UART_FLOW_CONTROL
 #define HCI_UART_FLOW_CONTROL 0
 #endif
 
-//  HCI_UART_RX_PIN - UART RX pin 
+//  HCI_UART_RX_PIN - UART RX pin
 #ifndef HCI_UART_RX_PIN
 #define HCI_UART_RX_PIN 31
 #endif
 
-//  HCI_UART_TX_PIN - UART TX pin 
+//  HCI_UART_TX_PIN - UART TX pin
 #ifndef HCI_UART_TX_PIN
 #define HCI_UART_TX_PIN 31
 #endif
 
-//  HCI_UART_RTS_PIN - UART RTS pin 
+//  HCI_UART_RTS_PIN - UART RTS pin
 #ifndef HCI_UART_RTS_PIN
 #define HCI_UART_RTS_PIN 31
 #endif
 
-//  HCI_UART_CTS_PIN - UART CTS pin 
+//  HCI_UART_CTS_PIN - UART CTS pin
 #ifndef HCI_UART_CTS_PIN
 #define HCI_UART_CTS_PIN 31
 #endif
@@ -6689,7 +6689,7 @@
 #ifndef HCI_TRANSPORT_ENABLED
 #define HCI_TRANSPORT_ENABLED 0
 #endif
-//  HCI_MAX_PACKET_SIZE_IN_BITS - Maximum size of a single application packet in bits. 
+//  HCI_MAX_PACKET_SIZE_IN_BITS - Maximum size of a single application packet in bits.
 #ifndef HCI_MAX_PACKET_SIZE_IN_BITS
 #define HCI_MAX_PACKET_SIZE_IN_BITS 8000
 #endif
@@ -6697,14 +6697,14 @@
 // 
 
 //  LED_SOFTBLINK_ENABLED  - led_softblink - led_softblink module
- 
+
 
 #ifndef LED_SOFTBLINK_ENABLED
 #define LED_SOFTBLINK_ENABLED 0
 #endif
 
 //  LOW_POWER_PWM_ENABLED  - low_power_pwm - low_power_pwm module
- 
+
 
 #ifndef LOW_POWER_PWM_ENABLED
 #define LOW_POWER_PWM_ENABLED 0
@@ -6715,98 +6715,98 @@
 #ifndef MEM_MANAGER_ENABLED
 #define MEM_MANAGER_ENABLED 0
 #endif
-//  MEMORY_MANAGER_SMALL_BLOCK_COUNT - Size of each memory blocks identified as 'small' block.  <0-255> 
+//  MEMORY_MANAGER_SMALL_BLOCK_COUNT - Size of each memory blocks identified as 'small' block.  <0-255>
 
 
 #ifndef MEMORY_MANAGER_SMALL_BLOCK_COUNT
 #define MEMORY_MANAGER_SMALL_BLOCK_COUNT 1
 #endif
 
-//  MEMORY_MANAGER_SMALL_BLOCK_SIZE -  Size of each memory blocks identified as 'small' block. 
+//  MEMORY_MANAGER_SMALL_BLOCK_SIZE -  Size of each memory blocks identified as 'small' block.
 //   Size of each memory blocks identified as 'small' block. Memory block are recommended to be word-sized.
 
 #ifndef MEMORY_MANAGER_SMALL_BLOCK_SIZE
 #define MEMORY_MANAGER_SMALL_BLOCK_SIZE 32
 #endif
 
-//  MEMORY_MANAGER_MEDIUM_BLOCK_COUNT - Size of each memory blocks identified as 'medium' block.  <0-255> 
+//  MEMORY_MANAGER_MEDIUM_BLOCK_COUNT - Size of each memory blocks identified as 'medium' block.  <0-255>
 
 
 #ifndef MEMORY_MANAGER_MEDIUM_BLOCK_COUNT
 #define MEMORY_MANAGER_MEDIUM_BLOCK_COUNT 0
 #endif
 
-//  MEMORY_MANAGER_MEDIUM_BLOCK_SIZE -  Size of each memory blocks identified as 'medium' block. 
+//  MEMORY_MANAGER_MEDIUM_BLOCK_SIZE -  Size of each memory blocks identified as 'medium' block.
 //   Size of each memory blocks identified as 'medium' block. Memory block are recommended to be word-sized.
 
 #ifndef MEMORY_MANAGER_MEDIUM_BLOCK_SIZE
 #define MEMORY_MANAGER_MEDIUM_BLOCK_SIZE 256
 #endif
 
-//  MEMORY_MANAGER_LARGE_BLOCK_COUNT - Size of each memory blocks identified as 'large' block.  <0-255> 
+//  MEMORY_MANAGER_LARGE_BLOCK_COUNT - Size of each memory blocks identified as 'large' block.  <0-255>
 
 
 #ifndef MEMORY_MANAGER_LARGE_BLOCK_COUNT
 #define MEMORY_MANAGER_LARGE_BLOCK_COUNT 0
 #endif
 
-//  MEMORY_MANAGER_LARGE_BLOCK_SIZE -  Size of each memory blocks identified as 'large' block. 
+//  MEMORY_MANAGER_LARGE_BLOCK_SIZE -  Size of each memory blocks identified as 'large' block.
 //   Size of each memory blocks identified as 'large' block. Memory block are recommended to be word-sized.
 
 #ifndef MEMORY_MANAGER_LARGE_BLOCK_SIZE
 #define MEMORY_MANAGER_LARGE_BLOCK_SIZE 256
 #endif
 
-//  MEMORY_MANAGER_XLARGE_BLOCK_COUNT - Size of each memory blocks identified as 'extra large' block.  <0-255> 
+//  MEMORY_MANAGER_XLARGE_BLOCK_COUNT - Size of each memory blocks identified as 'extra large' block.  <0-255>
 
 
 #ifndef MEMORY_MANAGER_XLARGE_BLOCK_COUNT
 #define MEMORY_MANAGER_XLARGE_BLOCK_COUNT 0
 #endif
 
-//  MEMORY_MANAGER_XLARGE_BLOCK_SIZE -  Size of each memory blocks identified as 'extra large' block. 
+//  MEMORY_MANAGER_XLARGE_BLOCK_SIZE -  Size of each memory blocks identified as 'extra large' block.
 //   Size of each memory blocks identified as 'extra large' block. Memory block are recommended to be word-sized.
 
 #ifndef MEMORY_MANAGER_XLARGE_BLOCK_SIZE
 #define MEMORY_MANAGER_XLARGE_BLOCK_SIZE 1320
 #endif
 
-//  MEMORY_MANAGER_XXLARGE_BLOCK_COUNT - Size of each memory blocks identified as 'extra extra large' block.  <0-255> 
+//  MEMORY_MANAGER_XXLARGE_BLOCK_COUNT - Size of each memory blocks identified as 'extra extra large' block.  <0-255>
 
 
 #ifndef MEMORY_MANAGER_XXLARGE_BLOCK_COUNT
 #define MEMORY_MANAGER_XXLARGE_BLOCK_COUNT 0
 #endif
 
-//  MEMORY_MANAGER_XXLARGE_BLOCK_SIZE -  Size of each memory blocks identified as 'extra extra large' block. 
+//  MEMORY_MANAGER_XXLARGE_BLOCK_SIZE -  Size of each memory blocks identified as 'extra extra large' block.
 //   Size of each memory blocks identified as 'extra extra large' block. Memory block are recommended to be word-sized.
 
 #ifndef MEMORY_MANAGER_XXLARGE_BLOCK_SIZE
 #define MEMORY_MANAGER_XXLARGE_BLOCK_SIZE 3444
 #endif
 
-//  MEMORY_MANAGER_XSMALL_BLOCK_COUNT - Size of each memory blocks identified as 'extra small' block.  <0-255> 
+//  MEMORY_MANAGER_XSMALL_BLOCK_COUNT - Size of each memory blocks identified as 'extra small' block.  <0-255>
 
 
 #ifndef MEMORY_MANAGER_XSMALL_BLOCK_COUNT
 #define MEMORY_MANAGER_XSMALL_BLOCK_COUNT 0
 #endif
 
-//  MEMORY_MANAGER_XSMALL_BLOCK_SIZE -  Size of each memory blocks identified as 'extra small' block. 
+//  MEMORY_MANAGER_XSMALL_BLOCK_SIZE -  Size of each memory blocks identified as 'extra small' block.
 //   Size of each memory blocks identified as 'extra large' block. Memory block are recommended to be word-sized.
 
 #ifndef MEMORY_MANAGER_XSMALL_BLOCK_SIZE
 #define MEMORY_MANAGER_XSMALL_BLOCK_SIZE 64
 #endif
 
-//  MEMORY_MANAGER_XXSMALL_BLOCK_COUNT - Size of each memory blocks identified as 'extra extra small' block.  <0-255> 
+//  MEMORY_MANAGER_XXSMALL_BLOCK_COUNT - Size of each memory blocks identified as 'extra extra small' block.  <0-255>
 
 
 #ifndef MEMORY_MANAGER_XXSMALL_BLOCK_COUNT
 #define MEMORY_MANAGER_XXSMALL_BLOCK_COUNT 0
 #endif
 
-//  MEMORY_MANAGER_XXSMALL_BLOCK_SIZE -  Size of each memory blocks identified as 'extra extra small' block. 
+//  MEMORY_MANAGER_XXSMALL_BLOCK_SIZE -  Size of each memory blocks identified as 'extra extra small' block.
 //   Size of each memory blocks identified as 'extra extra small' block. Memory block are recommended to be word-sized.
 
 #ifndef MEMORY_MANAGER_XXSMALL_BLOCK_SIZE
@@ -6819,44 +6819,44 @@
 #define MEM_MANAGER_CONFIG_LOG_ENABLED 0
 #endif
 //  MEM_MANAGER_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef MEM_MANAGER_CONFIG_LOG_LEVEL
 #define MEM_MANAGER_CONFIG_LOG_LEVEL 3
 #endif
 
 //  MEM_MANAGER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef MEM_MANAGER_CONFIG_INFO_COLOR
 #define MEM_MANAGER_CONFIG_INFO_COLOR 0
 #endif
 
 //  MEM_MANAGER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef MEM_MANAGER_CONFIG_DEBUG_COLOR
 #define MEM_MANAGER_CONFIG_DEBUG_COLOR 0
@@ -6865,7 +6865,7 @@
 // 
 
 //  MEM_MANAGER_DISABLE_API_PARAM_CHECK  - Disable API parameter checks in the module.
- 
+
 
 #ifndef MEM_MANAGER_DISABLE_API_PARAM_CHECK
 #define MEM_MANAGER_DISABLE_API_PARAM_CHECK 0
@@ -6883,14 +6883,14 @@
 #ifndef NRF_BALLOC_CONFIG_DEBUG_ENABLED
 #define NRF_BALLOC_CONFIG_DEBUG_ENABLED 0
 #endif
-//  NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS - Number of words used as head guard.  <0-255> 
+//  NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS - Number of words used as head guard.  <0-255>
 
 
 #ifndef NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS
 #define NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS 1
 #endif
 
-//  NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS - Number of words used as tail guard.  <0-255> 
+//  NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS - Number of words used as tail guard.  <0-255>
 
 
 #ifndef NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS
@@ -6898,28 +6898,28 @@
 #endif
 
 //  NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED  - Enables basic checks in this module.
- 
+
 
 #ifndef NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED
 #define NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED 0
 #endif
 
 //  NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED  - Enables double memory free check in this module.
- 
+
 
 #ifndef NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED
 #define NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED 0
 #endif
 
 //  NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED  - Enables free memory corruption check in this module.
- 
+
 
 #ifndef NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED
 #define NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED 0
 #endif
 
 //  NRF_BALLOC_CLI_CMDS  - Enable CLI commands specific to the module
- 
+
 
 #ifndef NRF_BALLOC_CLI_CMDS
 #define NRF_BALLOC_CLI_CMDS 0
@@ -6934,32 +6934,32 @@
 #ifndef NRF_CSENSE_ENABLED
 #define NRF_CSENSE_ENABLED 0
 #endif
-//  NRF_CSENSE_PAD_HYSTERESIS - Minimum value of change required to determine that a pad was touched. 
+//  NRF_CSENSE_PAD_HYSTERESIS - Minimum value of change required to determine that a pad was touched.
 #ifndef NRF_CSENSE_PAD_HYSTERESIS
 #define NRF_CSENSE_PAD_HYSTERESIS 15
 #endif
 
-//  NRF_CSENSE_PAD_DEVIATION - Minimum value measured on a pad required to take it into account while calculating the step. 
+//  NRF_CSENSE_PAD_DEVIATION - Minimum value measured on a pad required to take it into account while calculating the step.
 #ifndef NRF_CSENSE_PAD_DEVIATION
 #define NRF_CSENSE_PAD_DEVIATION 70
 #endif
 
-//  NRF_CSENSE_MIN_PAD_VALUE - Minimum normalized value on a pad required to take its value into account. 
+//  NRF_CSENSE_MIN_PAD_VALUE - Minimum normalized value on a pad required to take its value into account.
 #ifndef NRF_CSENSE_MIN_PAD_VALUE
 #define NRF_CSENSE_MIN_PAD_VALUE 20
 #endif
 
-//  NRF_CSENSE_MAX_PADS_NUMBER - Maximum number of pads used for one instance. 
+//  NRF_CSENSE_MAX_PADS_NUMBER - Maximum number of pads used for one instance.
 #ifndef NRF_CSENSE_MAX_PADS_NUMBER
 #define NRF_CSENSE_MAX_PADS_NUMBER 20
 #endif
 
-//  NRF_CSENSE_MAX_VALUE - Maximum normalized value obtained from measurement. 
+//  NRF_CSENSE_MAX_VALUE - Maximum normalized value obtained from measurement.
 #ifndef NRF_CSENSE_MAX_VALUE
 #define NRF_CSENSE_MAX_VALUE 1000
 #endif
 
-//  NRF_CSENSE_OUTPUT_PIN - Output pin used by the low-level module. 
+//  NRF_CSENSE_OUTPUT_PIN - Output pin used by the low-level module.
 //  This is used when capacitive sensor does not use COMP.
 
 #ifndef NRF_CSENSE_OUTPUT_PIN
@@ -6980,17 +6980,17 @@
 #ifndef USE_COMP
 #define USE_COMP 0
 #endif
-//  TIMER0_FOR_CSENSE - First TIMER instance used by the driver (not used on nRF51). 
+//  TIMER0_FOR_CSENSE - First TIMER instance used by the driver (not used on nRF51).
 #ifndef TIMER0_FOR_CSENSE
 #define TIMER0_FOR_CSENSE 1
 #endif
 
-//  TIMER1_FOR_CSENSE - Second TIMER instance used by the driver (not used on nRF51). 
+//  TIMER1_FOR_CSENSE - Second TIMER instance used by the driver (not used on nRF51).
 #ifndef TIMER1_FOR_CSENSE
 #define TIMER1_FOR_CSENSE 2
 #endif
 
-//  MEASUREMENT_PERIOD - Single measurement period. 
+//  MEASUREMENT_PERIOD - Single measurement period.
 //  Time of a single measurement can be calculated as
 //  T = (1/2)*MEASUREMENT_PERIOD*(1/f_OSC) where f_OSC = I_SOURCE / (2C*(VUP-VDOWN) ).
 //  I_SOURCE, VUP, and VDOWN are values used to initialize COMP and C is the capacitance of the used pad.
@@ -7013,7 +7013,7 @@
 //  Common settings to all fstorage implementations
 //==========================================================
 //  NRF_FSTORAGE_PARAM_CHECK_DISABLED  - Disable user input validation
- 
+
 
 //  If selected, use ASSERT to validate user input.
 //  This effectively removes user input validation in production code.
@@ -7023,21 +7023,21 @@
 #define NRF_FSTORAGE_PARAM_CHECK_DISABLED 0
 #endif
 
-//  
+// 
 //==========================================================
 
 //  nrf_fstorage_sd - Implementation using the SoftDevice
 
 //  Configuration options for the fstorage implementation using the SoftDevice
 //==========================================================
-//  NRF_FSTORAGE_SD_QUEUE_SIZE - Size of the internal queue of operations 
+//  NRF_FSTORAGE_SD_QUEUE_SIZE - Size of the internal queue of operations
 //  Increase this value if API calls frequently return the error @ref NRF_ERROR_NO_MEM.
 
 #ifndef NRF_FSTORAGE_SD_QUEUE_SIZE
 #define NRF_FSTORAGE_SD_QUEUE_SIZE 4
 #endif
 
-//  NRF_FSTORAGE_SD_MAX_RETRIES - Maximum number of attempts at executing an operation when the SoftDevice is busy 
+//  NRF_FSTORAGE_SD_MAX_RETRIES - Maximum number of attempts at executing an operation when the SoftDevice is busy
 //  Increase this value if events frequently return the @ref NRF_ERROR_TIMEOUT error.
 //  The SoftDevice might fail to schedule flash access due to high BLE activity.
 
@@ -7045,7 +7045,7 @@
 #define NRF_FSTORAGE_SD_MAX_RETRIES 8
 #endif
 
-//  NRF_FSTORAGE_SD_MAX_WRITE_SIZE - Maximum number of bytes to be written to flash in a single operation 
+//  NRF_FSTORAGE_SD_MAX_WRITE_SIZE - Maximum number of bytes to be written to flash in a single operation
 //  This value must be a multiple of four.
 //  Lowering this value can increase the chances of the SoftDevice being able to execute flash operations in between radio activity.
 //  This value is bound by the maximum number of bytes that can be written to flash in a single call to @ref sd_flash_write.
@@ -7055,20 +7055,20 @@
 #define NRF_FSTORAGE_SD_MAX_WRITE_SIZE 4096
 #endif
 
-//  
+// 
 //==========================================================
 
 // 
 
 //  NRF_GFX_ENABLED  - nrf_gfx - GFX module
- 
+
 
 #ifndef NRF_GFX_ENABLED
 #define NRF_GFX_ENABLED 0
 #endif
 
 //  NRF_MEMOBJ_ENABLED  - nrf_memobj - Linked memory allocator module
- 
+
 
 #ifndef NRF_MEMOBJ_ENABLED
 #define NRF_MEMOBJ_ENABLED 1
@@ -7087,56 +7087,56 @@
 #define NRF_PWR_MGMT_CONFIG_DEBUG_PIN_ENABLED 0
 #endif
 //  NRF_PWR_MGMT_SLEEP_DEBUG_PIN  - Pin number
- 
-// <0=> 0 (P0.0) 
-// <1=> 1 (P0.1) 
-// <2=> 2 (P0.2) 
-// <3=> 3 (P0.3) 
-// <4=> 4 (P0.4) 
-// <5=> 5 (P0.5) 
-// <6=> 6 (P0.6) 
-// <7=> 7 (P0.7) 
-// <8=> 8 (P0.8) 
-// <9=> 9 (P0.9) 
-// <10=> 10 (P0.10) 
-// <11=> 11 (P0.11) 
-// <12=> 12 (P0.12) 
-// <13=> 13 (P0.13) 
-// <14=> 14 (P0.14) 
-// <15=> 15 (P0.15) 
-// <16=> 16 (P0.16) 
-// <17=> 17 (P0.17) 
-// <18=> 18 (P0.18) 
-// <19=> 19 (P0.19) 
-// <20=> 20 (P0.20) 
-// <21=> 21 (P0.21) 
-// <22=> 22 (P0.22) 
-// <23=> 23 (P0.23) 
-// <24=> 24 (P0.24) 
-// <25=> 25 (P0.25) 
-// <26=> 26 (P0.26) 
-// <27=> 27 (P0.27) 
-// <28=> 28 (P0.28) 
-// <29=> 29 (P0.29) 
-// <30=> 30 (P0.30) 
-// <31=> 31 (P0.31) 
-// <32=> 32 (P1.0) 
-// <33=> 33 (P1.1) 
-// <34=> 34 (P1.2) 
-// <35=> 35 (P1.3) 
-// <36=> 36 (P1.4) 
-// <37=> 37 (P1.5) 
-// <38=> 38 (P1.6) 
-// <39=> 39 (P1.7) 
-// <40=> 40 (P1.8) 
-// <41=> 41 (P1.9) 
-// <42=> 42 (P1.10) 
-// <43=> 43 (P1.11) 
-// <44=> 44 (P1.12) 
-// <45=> 45 (P1.13) 
-// <46=> 46 (P1.14) 
-// <47=> 47 (P1.15) 
-// <4294967295=> Not connected 
+
+// <0=> 0 (P0.0)
+// <1=> 1 (P0.1)
+// <2=> 2 (P0.2)
+// <3=> 3 (P0.3)
+// <4=> 4 (P0.4)
+// <5=> 5 (P0.5)
+// <6=> 6 (P0.6)
+// <7=> 7 (P0.7)
+// <8=> 8 (P0.8)
+// <9=> 9 (P0.9)
+// <10=> 10 (P0.10)
+// <11=> 11 (P0.11)
+// <12=> 12 (P0.12)
+// <13=> 13 (P0.13)
+// <14=> 14 (P0.14)
+// <15=> 15 (P0.15)
+// <16=> 16 (P0.16)
+// <17=> 17 (P0.17)
+// <18=> 18 (P0.18)
+// <19=> 19 (P0.19)
+// <20=> 20 (P0.20)
+// <21=> 21 (P0.21)
+// <22=> 22 (P0.22)
+// <23=> 23 (P0.23)
+// <24=> 24 (P0.24)
+// <25=> 25 (P0.25)
+// <26=> 26 (P0.26)
+// <27=> 27 (P0.27)
+// <28=> 28 (P0.28)
+// <29=> 29 (P0.29)
+// <30=> 30 (P0.30)
+// <31=> 31 (P0.31)
+// <32=> 32 (P1.0)
+// <33=> 33 (P1.1)
+// <34=> 34 (P1.2)
+// <35=> 35 (P1.3)
+// <36=> 36 (P1.4)
+// <37=> 37 (P1.5)
+// <38=> 38 (P1.6)
+// <39=> 39 (P1.7)
+// <40=> 40 (P1.8)
+// <41=> 41 (P1.9)
+// <42=> 42 (P1.10)
+// <43=> 43 (P1.11)
+// <44=> 44 (P1.12)
+// <45=> 45 (P1.13)
+// <46=> 46 (P1.14)
+// <47=> 47 (P1.15)
+// <4294967295=> Not connected
 
 #ifndef NRF_PWR_MGMT_SLEEP_DEBUG_PIN
 #define NRF_PWR_MGMT_SLEEP_DEBUG_PIN 31
@@ -7145,7 +7145,7 @@
 // 
 
 //  NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED  - Enables CPU usage monitor.
- 
+
 
 //  Module will trace percentage of CPU usage in one second intervals.
 
@@ -7158,7 +7158,7 @@
 #ifndef NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_ENABLED
 #define NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_ENABLED 0
 #endif
-//  NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S - Standby timeout (in seconds). 
+//  NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S - Standby timeout (in seconds).
 //  Shutdown procedure will begin no earlier than after this number of seconds.
 
 #ifndef NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S
@@ -7168,27 +7168,27 @@
 // 
 
 //  NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED  - Enables FPU event cleaning.
- 
+
 
 #ifndef NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED
 #define NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED 0
 #endif
 
 //  NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY  - Blocked shutdown procedure will be retried every second.
- 
+
 
 #ifndef NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY
 #define NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY 0
 #endif
 
 //  NRF_PWR_MGMT_CONFIG_USE_SCHEDULER  - Module will use @ref app_scheduler.
- 
+
 
 #ifndef NRF_PWR_MGMT_CONFIG_USE_SCHEDULER
 #define NRF_PWR_MGMT_CONFIG_USE_SCHEDULER 0
 #endif
 
-//  NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT - The number of priorities for module handlers. 
+//  NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT - The number of priorities for module handlers.
 //  The number of stages of the shutdown process.
 
 #ifndef NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT
@@ -7203,7 +7203,7 @@
 #define NRF_QUEUE_ENABLED 0
 #endif
 //  NRF_QUEUE_CLI_CMDS  - Enable CLI commands specific to the module
- 
+
 
 #ifndef NRF_QUEUE_CLI_CMDS
 #define NRF_QUEUE_CLI_CMDS 0
@@ -7212,42 +7212,42 @@
 // 
 
 //  NRF_SECTION_ITER_ENABLED  - nrf_section_iter - Section iterator
- 
+
 
 #ifndef NRF_SECTION_ITER_ENABLED
 #define NRF_SECTION_ITER_ENABLED 1
 #endif
 
 //  NRF_SORTLIST_ENABLED  - nrf_sortlist - Sorted list
- 
+
 
 #ifndef NRF_SORTLIST_ENABLED
 #define NRF_SORTLIST_ENABLED 1
 #endif
 
 //  NRF_SPI_MNGR_ENABLED  - nrf_spi_mngr - SPI transaction manager
- 
+
 
 #ifndef NRF_SPI_MNGR_ENABLED
 #define NRF_SPI_MNGR_ENABLED 0
 #endif
 
 //  NRF_STRERROR_ENABLED  - nrf_strerror - Library for converting error code to string.
- 
+
 
 #ifndef NRF_STRERROR_ENABLED
 #define NRF_STRERROR_ENABLED 1
 #endif
 
 //  NRF_TWI_MNGR_ENABLED  - nrf_twi_mngr - TWI transaction manager
- 
+
 
 #ifndef NRF_TWI_MNGR_ENABLED
 #define NRF_TWI_MNGR_ENABLED 0
 #endif
 
 //  SLIP_ENABLED  - slip - SLIP encoding and decoding
- 
+
 
 #ifndef SLIP_ENABLED
 #define SLIP_ENABLED 0
@@ -7259,37 +7259,37 @@
 #define TASK_MANAGER_ENABLED 0
 #endif
 //  TASK_MANAGER_CLI_CMDS  - Enable CLI commands specific to the module
- 
+
 
 #ifndef TASK_MANAGER_CLI_CMDS
 #define TASK_MANAGER_CLI_CMDS 0
 #endif
 
-//  TASK_MANAGER_CONFIG_MAX_TASKS - Maximum number of tasks which can be created 
+//  TASK_MANAGER_CONFIG_MAX_TASKS - Maximum number of tasks which can be created
 #ifndef TASK_MANAGER_CONFIG_MAX_TASKS
 #define TASK_MANAGER_CONFIG_MAX_TASKS 2
 #endif
 
-//  TASK_MANAGER_CONFIG_STACK_SIZE - Stack size for every task (power of 2) 
+//  TASK_MANAGER_CONFIG_STACK_SIZE - Stack size for every task (power of 2)
 #ifndef TASK_MANAGER_CONFIG_STACK_SIZE
 #define TASK_MANAGER_CONFIG_STACK_SIZE 1024
 #endif
 
 //  TASK_MANAGER_CONFIG_STACK_PROFILER_ENABLED  - Enable stack profiling.
- 
+
 
 #ifndef TASK_MANAGER_CONFIG_STACK_PROFILER_ENABLED
 #define TASK_MANAGER_CONFIG_STACK_PROFILER_ENABLED 1
 #endif
 
 //  TASK_MANAGER_CONFIG_STACK_GUARD  - Configures stack guard.
- 
-// <0=> Disabled 
-// <4=> 32 bytes 
-// <5=> 64 bytes 
-// <6=> 128 bytes 
-// <7=> 256 bytes 
-// <8=> 512 bytes 
+
+// <0=> Disabled
+// <4=> 32 bytes
+// <5=> 64 bytes
+// <6=> 128 bytes
+// <7=> 256 bytes
+// <8=> 512 bytes
 
 #ifndef TASK_MANAGER_CONFIG_STACK_GUARD
 #define TASK_MANAGER_CONFIG_STACK_GUARD 7
@@ -7301,34 +7301,34 @@
 
 //==========================================================
 //  BUTTON_ENABLED  - Enables Button module
- 
+
 
 #ifndef BUTTON_ENABLED
 #define BUTTON_ENABLED 0
 #endif
 
 //  BUTTON_HIGH_ACCURACY_ENABLED  - Enables GPIOTE high accuracy for buttons
- 
+
 
 #ifndef BUTTON_HIGH_ACCURACY_ENABLED
 #define BUTTON_HIGH_ACCURACY_ENABLED 0
 #endif
 
-//  
+// 
 //==========================================================
 
 //  app_usbd_cdc_acm - USB CDC ACM class
 
 //==========================================================
 //  APP_USBD_CDC_ACM_ENABLED  - Enabling USBD CDC ACM Class library
- 
+
 
 #ifndef APP_USBD_CDC_ACM_ENABLED
 #define APP_USBD_CDC_ACM_ENABLED 0
 #endif
 
 //  APP_USBD_CDC_ACM_ZLP_ON_EPSIZE_WRITE  - Send ZLP on write with same size as endpoint
- 
+
 
 //  If enabled, CDC ACM class will automatically send a zero length packet after transfer which has the same size as endpoint.
 //  This may limit throughput if a lot of binary data is sent, but in terminal mode operation it makes sure that the data is always displayed right after it is sent.
@@ -7337,58 +7337,58 @@
 #define APP_USBD_CDC_ACM_ZLP_ON_EPSIZE_WRITE 1
 #endif
 
-//  
+// 
 //==========================================================
 
 //  nrf_cli - Command line interface
 
 //==========================================================
 //  NRF_CLI_ENABLED  - Enable/disable the CLI module.
- 
+
 
 #ifndef NRF_CLI_ENABLED
 #define NRF_CLI_ENABLED 0
 #endif
 
-//  NRF_CLI_ARGC_MAX - Maximum number of parameters passed to the command handler. 
+//  NRF_CLI_ARGC_MAX - Maximum number of parameters passed to the command handler.
 #ifndef NRF_CLI_ARGC_MAX
 #define NRF_CLI_ARGC_MAX 12
 #endif
 
 //  NRF_CLI_BUILD_IN_CMDS_ENABLED  - CLI built-in commands.
- 
+
 
 #ifndef NRF_CLI_BUILD_IN_CMDS_ENABLED
 #define NRF_CLI_BUILD_IN_CMDS_ENABLED 1
 #endif
 
-//  NRF_CLI_CMD_BUFF_SIZE - Maximum buffer size for a single command. 
+//  NRF_CLI_CMD_BUFF_SIZE - Maximum buffer size for a single command.
 #ifndef NRF_CLI_CMD_BUFF_SIZE
 #define NRF_CLI_CMD_BUFF_SIZE 128
 #endif
 
 //  NRF_CLI_ECHO_STATUS  - CLI echo status. If set, echo is ON.
- 
+
 
 #ifndef NRF_CLI_ECHO_STATUS
 #define NRF_CLI_ECHO_STATUS 1
 #endif
 
 //  NRF_CLI_WILDCARD_ENABLED  - Enable wildcard functionality for CLI commands.
- 
+
 
 #ifndef NRF_CLI_WILDCARD_ENABLED
 #define NRF_CLI_WILDCARD_ENABLED 0
 #endif
 
 //  NRF_CLI_METAKEYS_ENABLED  - Enable additional control keys for CLI commands like ctrl+a, ctrl+e, ctrl+w, ctrl+u
- 
+
 
 #ifndef NRF_CLI_METAKEYS_ENABLED
 #define NRF_CLI_METAKEYS_ENABLED 0
 #endif
 
-//  NRF_CLI_PRINTF_BUFF_SIZE - Maximum print buffer size. 
+//  NRF_CLI_PRINTF_BUFF_SIZE - Maximum print buffer size.
 #ifndef NRF_CLI_PRINTF_BUFF_SIZE
 #define NRF_CLI_PRINTF_BUFF_SIZE 23
 #endif
@@ -7398,12 +7398,12 @@
 #ifndef NRF_CLI_HISTORY_ENABLED
 #define NRF_CLI_HISTORY_ENABLED 1
 #endif
-//  NRF_CLI_HISTORY_ELEMENT_SIZE - Size of one memory object reserved for CLI history. 
+//  NRF_CLI_HISTORY_ELEMENT_SIZE - Size of one memory object reserved for CLI history.
 #ifndef NRF_CLI_HISTORY_ELEMENT_SIZE
 #define NRF_CLI_HISTORY_ELEMENT_SIZE 32
 #endif
 
-//  NRF_CLI_HISTORY_ELEMENT_COUNT - Number of history memory objects. 
+//  NRF_CLI_HISTORY_ELEMENT_COUNT - Number of history memory objects.
 #ifndef NRF_CLI_HISTORY_ELEMENT_COUNT
 #define NRF_CLI_HISTORY_ELEMENT_COUNT 8
 #endif
@@ -7411,67 +7411,67 @@
 // 
 
 //  NRF_CLI_VT100_COLORS_ENABLED  - CLI VT100 colors.
- 
+
 
 #ifndef NRF_CLI_VT100_COLORS_ENABLED
 #define NRF_CLI_VT100_COLORS_ENABLED 1
 #endif
 
 //  NRF_CLI_STATISTICS_ENABLED  - Enable CLI statistics.
- 
+
 
 #ifndef NRF_CLI_STATISTICS_ENABLED
 #define NRF_CLI_STATISTICS_ENABLED 1
 #endif
 
 //  NRF_CLI_LOG_BACKEND  - Enable logger backend interface.
- 
+
 
 #ifndef NRF_CLI_LOG_BACKEND
 #define NRF_CLI_LOG_BACKEND 1
 #endif
 
 //  NRF_CLI_USES_TASK_MANAGER_ENABLED  - Enable CLI to use task_manager
- 
+
 
 #ifndef NRF_CLI_USES_TASK_MANAGER_ENABLED
 #define NRF_CLI_USES_TASK_MANAGER_ENABLED 0
 #endif
 
-//  
+// 
 //==========================================================
 
 //  nrf_fprintf - fprintf function.
 
 //==========================================================
 //  NRF_FPRINTF_ENABLED  - Enable/disable fprintf module.
- 
+
 
 #ifndef NRF_FPRINTF_ENABLED
 #define NRF_FPRINTF_ENABLED 1
 #endif
 
 //  NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF_ENABLED  - For each printed LF, function will add CR.
- 
+
 
 #ifndef NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF_ENABLED
 #define NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF_ENABLED 1
 #endif
 
 //  NRF_FPRINTF_DOUBLE_ENABLED  - Enable IEEE-754 double precision formatting.
- 
+
 
 #ifndef NRF_FPRINTF_DOUBLE_ENABLED
 #define NRF_FPRINTF_DOUBLE_ENABLED 0
 #endif
 
-//  
+// 
 //==========================================================
 
-//  
+// 
 //==========================================================
 
-//  nRF_Log 
+//  nRF_Log
 
 //==========================================================
 //  NRF_LOG_ENABLED - nrf_log - Logger
@@ -7482,7 +7482,7 @@
 //  Log message pool - Configuration of log message pool
 
 //==========================================================
-//  NRF_LOG_MSGPOOL_ELEMENT_SIZE - Size of a single element in the pool of memory objects. 
+//  NRF_LOG_MSGPOOL_ELEMENT_SIZE - Size of a single element in the pool of memory objects.
 //  If a small value is set, then performance of logs processing
 //  is degraded because data is fragmented. Bigger value impacts
 //  RAM memory utilization. The size is set to fit a message with
@@ -7492,7 +7492,7 @@
 #define NRF_LOG_MSGPOOL_ELEMENT_SIZE 20
 #endif
 
-//  NRF_LOG_MSGPOOL_ELEMENT_COUNT - Number of elements in the pool of memory objects 
+//  NRF_LOG_MSGPOOL_ELEMENT_COUNT - Number of elements in the pool of memory objects
 //  If a small value is set, then it may lead to a deadlock
 //  in certain cases if backend has high latency and holds
 //  multiple messages for long time. Bigger value impacts
@@ -7502,13 +7502,13 @@
 #define NRF_LOG_MSGPOOL_ELEMENT_COUNT 8
 #endif
 
-//  
+// 
 //==========================================================
 
 //  NRF_LOG_ALLOW_OVERFLOW  - Configures behavior when circular buffer is full.
- 
 
-//  If set then oldest logs are overwritten. Otherwise a 
+
+//  If set then oldest logs are overwritten. Otherwise a
 //  marker is injected informing about overflow.
 
 #ifndef NRF_LOG_ALLOW_OVERFLOW
@@ -7516,44 +7516,44 @@
 #endif
 
 //  NRF_LOG_BUFSIZE  - Size of the buffer for storing logs (in bytes).
- 
+
 
 //  Must be power of 2 and multiple of 4.
 //  If NRF_LOG_DEFERRED = 0 then buffer size can be reduced to minimum.
-// <128=> 128 
-// <256=> 256 
-// <512=> 512 
-// <1024=> 1024 
-// <2048=> 2048 
-// <4096=> 4096 
-// <8192=> 8192 
-// <16384=> 16384 
+// <128=> 128
+// <256=> 256
+// <512=> 512
+// <1024=> 1024
+// <2048=> 2048
+// <4096=> 4096
+// <8192=> 8192
+// <16384=> 16384
 
 #ifndef NRF_LOG_BUFSIZE
 #define NRF_LOG_BUFSIZE 1024
 #endif
 
 //  NRF_LOG_CLI_CMDS  - Enable CLI commands for the module.
- 
+
 
 #ifndef NRF_LOG_CLI_CMDS
 #define NRF_LOG_CLI_CMDS 0
 #endif
 
 //  NRF_LOG_DEFAULT_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_LOG_DEFAULT_LEVEL
 #define NRF_LOG_DEFAULT_LEVEL 3
 #endif
 
 //  NRF_LOG_DEFERRED  - Enable deffered logger.
- 
+
 
 //  Log data is buffered and can be processed in idle.
 
@@ -7562,14 +7562,14 @@
 #endif
 
 //  NRF_LOG_FILTERS_ENABLED  - Enable dynamic filtering of logs.
- 
+
 
 #ifndef NRF_LOG_FILTERS_ENABLED
 #define NRF_LOG_FILTERS_ENABLED 0
 #endif
 
 //  NRF_LOG_NON_DEFFERED_CRITICAL_REGION_ENABLED  - Enable use of critical region for non deffered mode when flushing logs.
- 
+
 
 //  When enabled NRF_LOG_FLUSH is called from critical section when non deffered mode is used.
 //  Log output will never be corrupted as access to the log backend is exclusive
@@ -7580,28 +7580,28 @@
 #endif
 
 //  NRF_LOG_STR_PUSH_BUFFER_SIZE  - Size of the buffer dedicated for strings stored using @ref NRF_LOG_PUSH.
- 
-// <16=> 16 
-// <32=> 32 
-// <64=> 64 
-// <128=> 128 
-// <256=> 256 
-// <512=> 512 
-// <1024=> 1024 
+
+// <16=> 16
+// <32=> 32
+// <64=> 64
+// <128=> 128
+// <256=> 256
+// <512=> 512
+// <1024=> 1024
 
 #ifndef NRF_LOG_STR_PUSH_BUFFER_SIZE
 #define NRF_LOG_STR_PUSH_BUFFER_SIZE 128
 #endif
 
 //  NRF_LOG_STR_PUSH_BUFFER_SIZE  - Size of the buffer dedicated for strings stored using @ref NRF_LOG_PUSH.
- 
-// <16=> 16 
-// <32=> 32 
-// <64=> 64 
-// <128=> 128 
-// <256=> 256 
-// <512=> 512 
-// <1024=> 1024 
+
+// <16=> 16
+// <32=> 32
+// <64=> 64
+// <128=> 128
+// <256=> 256
+// <512=> 512
+// <1024=> 1024
 
 #ifndef NRF_LOG_STR_PUSH_BUFFER_SIZE
 #define NRF_LOG_STR_PUSH_BUFFER_SIZE 128
@@ -7613,48 +7613,48 @@
 #define NRF_LOG_USES_COLORS 0
 #endif
 //  NRF_LOG_COLOR_DEFAULT  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_LOG_COLOR_DEFAULT
 #define NRF_LOG_COLOR_DEFAULT 0
 #endif
 
 //  NRF_LOG_ERROR_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_LOG_ERROR_COLOR
 #define NRF_LOG_ERROR_COLOR 2
 #endif
 
 //  NRF_LOG_WARNING_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_LOG_WARNING_COLOR
 #define NRF_LOG_WARNING_COLOR 4
@@ -7669,17 +7669,17 @@
 #ifndef NRF_LOG_USES_TIMESTAMP
 #define NRF_LOG_USES_TIMESTAMP 0
 #endif
-//  NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY - Default frequency of the timestamp (in Hz) or 0 to use app_timer frequency. 
+//  NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY - Default frequency of the timestamp (in Hz) or 0 to use app_timer frequency.
 #ifndef NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY
 #define NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY 0
 #endif
 
 // 
 
-//  nrf_log module configuration 
+//  nrf_log module configuration
 
 //==========================================================
-//  nrf_log in nRF_Core 
+//  nrf_log in nRF_Core
 
 //==========================================================
 //  NRF_MPU_LIB_CONFIG_LOG_ENABLED - Enables logging in the module.
@@ -7688,44 +7688,44 @@
 #define NRF_MPU_LIB_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_MPU_LIB_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_MPU_LIB_CONFIG_LOG_LEVEL
 #define NRF_MPU_LIB_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_MPU_LIB_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_MPU_LIB_CONFIG_INFO_COLOR
 #define NRF_MPU_LIB_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_MPU_LIB_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_MPU_LIB_CONFIG_DEBUG_COLOR
 #define NRF_MPU_LIB_CONFIG_DEBUG_COLOR 0
@@ -7739,44 +7739,44 @@
 #define NRF_STACK_GUARD_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_STACK_GUARD_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_STACK_GUARD_CONFIG_LOG_LEVEL
 #define NRF_STACK_GUARD_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_STACK_GUARD_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_STACK_GUARD_CONFIG_INFO_COLOR
 #define NRF_STACK_GUARD_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_STACK_GUARD_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_STACK_GUARD_CONFIG_DEBUG_COLOR
 #define NRF_STACK_GUARD_CONFIG_DEBUG_COLOR 0
@@ -7790,44 +7790,44 @@
 #define TASK_MANAGER_CONFIG_LOG_ENABLED 0
 #endif
 //  TASK_MANAGER_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef TASK_MANAGER_CONFIG_LOG_LEVEL
 #define TASK_MANAGER_CONFIG_LOG_LEVEL 3
 #endif
 
 //  TASK_MANAGER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef TASK_MANAGER_CONFIG_INFO_COLOR
 #define TASK_MANAGER_CONFIG_INFO_COLOR 0
 #endif
 
 //  TASK_MANAGER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef TASK_MANAGER_CONFIG_DEBUG_COLOR
 #define TASK_MANAGER_CONFIG_DEBUG_COLOR 0
@@ -7835,10 +7835,10 @@
 
 // 
 
-//  
+// 
 //==========================================================
 
-//  nrf_log in nRF_Drivers 
+//  nrf_log in nRF_Drivers
 
 //==========================================================
 //  CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module.
@@ -7847,44 +7847,44 @@
 #define CLOCK_CONFIG_LOG_ENABLED 0
 #endif
 //  CLOCK_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef CLOCK_CONFIG_LOG_LEVEL
 #define CLOCK_CONFIG_LOG_LEVEL 3
 #endif
 
 //  CLOCK_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef CLOCK_CONFIG_INFO_COLOR
 #define CLOCK_CONFIG_INFO_COLOR 0
 #endif
 
 //  CLOCK_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef CLOCK_CONFIG_DEBUG_COLOR
 #define CLOCK_CONFIG_DEBUG_COLOR 0
@@ -7898,44 +7898,44 @@
 #define COMP_CONFIG_LOG_ENABLED 0
 #endif
 //  COMP_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef COMP_CONFIG_LOG_LEVEL
 #define COMP_CONFIG_LOG_LEVEL 3
 #endif
 
 //  COMP_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef COMP_CONFIG_INFO_COLOR
 #define COMP_CONFIG_INFO_COLOR 0
 #endif
 
 //  COMP_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef COMP_CONFIG_DEBUG_COLOR
 #define COMP_CONFIG_DEBUG_COLOR 0
@@ -7949,44 +7949,44 @@
 #define GPIOTE_CONFIG_LOG_ENABLED 0
 #endif
 //  GPIOTE_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef GPIOTE_CONFIG_LOG_LEVEL
 #define GPIOTE_CONFIG_LOG_LEVEL 3
 #endif
 
 //  GPIOTE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef GPIOTE_CONFIG_INFO_COLOR
 #define GPIOTE_CONFIG_INFO_COLOR 0
 #endif
 
 //  GPIOTE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef GPIOTE_CONFIG_DEBUG_COLOR
 #define GPIOTE_CONFIG_DEBUG_COLOR 0
@@ -8000,44 +8000,44 @@
 #define LPCOMP_CONFIG_LOG_ENABLED 0
 #endif
 //  LPCOMP_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef LPCOMP_CONFIG_LOG_LEVEL
 #define LPCOMP_CONFIG_LOG_LEVEL 3
 #endif
 
 //  LPCOMP_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef LPCOMP_CONFIG_INFO_COLOR
 #define LPCOMP_CONFIG_INFO_COLOR 0
 #endif
 
 //  LPCOMP_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef LPCOMP_CONFIG_DEBUG_COLOR
 #define LPCOMP_CONFIG_DEBUG_COLOR 0
@@ -8051,44 +8051,44 @@
 #define MAX3421E_HOST_CONFIG_LOG_ENABLED 0
 #endif
 //  MAX3421E_HOST_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef MAX3421E_HOST_CONFIG_LOG_LEVEL
 #define MAX3421E_HOST_CONFIG_LOG_LEVEL 3
 #endif
 
 //  MAX3421E_HOST_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef MAX3421E_HOST_CONFIG_INFO_COLOR
 #define MAX3421E_HOST_CONFIG_INFO_COLOR 0
 #endif
 
 //  MAX3421E_HOST_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef MAX3421E_HOST_CONFIG_DEBUG_COLOR
 #define MAX3421E_HOST_CONFIG_DEBUG_COLOR 0
@@ -8102,44 +8102,44 @@
 #define NRFX_USBD_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_USBD_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_USBD_CONFIG_LOG_LEVEL
 #define NRFX_USBD_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_USBD_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_USBD_CONFIG_INFO_COLOR
 #define NRFX_USBD_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_USBD_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_USBD_CONFIG_DEBUG_COLOR
 #define NRFX_USBD_CONFIG_DEBUG_COLOR 0
@@ -8153,44 +8153,44 @@
 #define PDM_CONFIG_LOG_ENABLED 0
 #endif
 //  PDM_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef PDM_CONFIG_LOG_LEVEL
 #define PDM_CONFIG_LOG_LEVEL 3
 #endif
 
 //  PDM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef PDM_CONFIG_INFO_COLOR
 #define PDM_CONFIG_INFO_COLOR 0
 #endif
 
 //  PDM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef PDM_CONFIG_DEBUG_COLOR
 #define PDM_CONFIG_DEBUG_COLOR 0
@@ -8204,44 +8204,44 @@
 #define PPI_CONFIG_LOG_ENABLED 0
 #endif
 //  PPI_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef PPI_CONFIG_LOG_LEVEL
 #define PPI_CONFIG_LOG_LEVEL 3
 #endif
 
 //  PPI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef PPI_CONFIG_INFO_COLOR
 #define PPI_CONFIG_INFO_COLOR 0
 #endif
 
 //  PPI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef PPI_CONFIG_DEBUG_COLOR
 #define PPI_CONFIG_DEBUG_COLOR 0
@@ -8255,44 +8255,44 @@
 #define PWM_CONFIG_LOG_ENABLED 0
 #endif
 //  PWM_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef PWM_CONFIG_LOG_LEVEL
 #define PWM_CONFIG_LOG_LEVEL 3
 #endif
 
 //  PWM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef PWM_CONFIG_INFO_COLOR
 #define PWM_CONFIG_INFO_COLOR 0
 #endif
 
 //  PWM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef PWM_CONFIG_DEBUG_COLOR
 #define PWM_CONFIG_DEBUG_COLOR 0
@@ -8306,44 +8306,44 @@
 #define QDEC_CONFIG_LOG_ENABLED 0
 #endif
 //  QDEC_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef QDEC_CONFIG_LOG_LEVEL
 #define QDEC_CONFIG_LOG_LEVEL 3
 #endif
 
 //  QDEC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef QDEC_CONFIG_INFO_COLOR
 #define QDEC_CONFIG_INFO_COLOR 0
 #endif
 
 //  QDEC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef QDEC_CONFIG_DEBUG_COLOR
 #define QDEC_CONFIG_DEBUG_COLOR 0
@@ -8357,51 +8357,51 @@
 #define RNG_CONFIG_LOG_ENABLED 0
 #endif
 //  RNG_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef RNG_CONFIG_LOG_LEVEL
 #define RNG_CONFIG_LOG_LEVEL 3
 #endif
 
 //  RNG_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef RNG_CONFIG_INFO_COLOR
 #define RNG_CONFIG_INFO_COLOR 0
 #endif
 
 //  RNG_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef RNG_CONFIG_DEBUG_COLOR
 #define RNG_CONFIG_DEBUG_COLOR 0
 #endif
 
 //  RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED  - Enables logging of random numbers.
- 
+
 
 #ifndef RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED
 #define RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED 0
@@ -8415,44 +8415,44 @@
 #define RTC_CONFIG_LOG_ENABLED 0
 #endif
 //  RTC_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef RTC_CONFIG_LOG_LEVEL
 #define RTC_CONFIG_LOG_LEVEL 3
 #endif
 
 //  RTC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef RTC_CONFIG_INFO_COLOR
 #define RTC_CONFIG_INFO_COLOR 0
 #endif
 
 //  RTC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef RTC_CONFIG_DEBUG_COLOR
 #define RTC_CONFIG_DEBUG_COLOR 0
@@ -8466,44 +8466,44 @@
 #define SAADC_CONFIG_LOG_ENABLED 0
 #endif
 //  SAADC_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef SAADC_CONFIG_LOG_LEVEL
 #define SAADC_CONFIG_LOG_LEVEL 3
 #endif
 
 //  SAADC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef SAADC_CONFIG_INFO_COLOR
 #define SAADC_CONFIG_INFO_COLOR 0
 #endif
 
 //  SAADC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef SAADC_CONFIG_DEBUG_COLOR
 #define SAADC_CONFIG_DEBUG_COLOR 0
@@ -8517,44 +8517,44 @@
 #define SPIS_CONFIG_LOG_ENABLED 0
 #endif
 //  SPIS_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef SPIS_CONFIG_LOG_LEVEL
 #define SPIS_CONFIG_LOG_LEVEL 3
 #endif
 
 //  SPIS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef SPIS_CONFIG_INFO_COLOR
 #define SPIS_CONFIG_INFO_COLOR 0
 #endif
 
 //  SPIS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef SPIS_CONFIG_DEBUG_COLOR
 #define SPIS_CONFIG_DEBUG_COLOR 0
@@ -8568,44 +8568,44 @@
 #define SPI_CONFIG_LOG_ENABLED 0
 #endif
 //  SPI_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef SPI_CONFIG_LOG_LEVEL
 #define SPI_CONFIG_LOG_LEVEL 3
 #endif
 
 //  SPI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef SPI_CONFIG_INFO_COLOR
 #define SPI_CONFIG_INFO_COLOR 0
 #endif
 
 //  SPI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef SPI_CONFIG_DEBUG_COLOR
 #define SPI_CONFIG_DEBUG_COLOR 0
@@ -8619,44 +8619,44 @@
 #define TIMER_CONFIG_LOG_ENABLED 0
 #endif
 //  TIMER_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef TIMER_CONFIG_LOG_LEVEL
 #define TIMER_CONFIG_LOG_LEVEL 3
 #endif
 
 //  TIMER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef TIMER_CONFIG_INFO_COLOR
 #define TIMER_CONFIG_INFO_COLOR 0
 #endif
 
 //  TIMER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef TIMER_CONFIG_DEBUG_COLOR
 #define TIMER_CONFIG_DEBUG_COLOR 0
@@ -8670,44 +8670,44 @@
 #define TWIS_CONFIG_LOG_ENABLED 0
 #endif
 //  TWIS_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef TWIS_CONFIG_LOG_LEVEL
 #define TWIS_CONFIG_LOG_LEVEL 3
 #endif
 
 //  TWIS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef TWIS_CONFIG_INFO_COLOR
 #define TWIS_CONFIG_INFO_COLOR 0
 #endif
 
 //  TWIS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef TWIS_CONFIG_DEBUG_COLOR
 #define TWIS_CONFIG_DEBUG_COLOR 0
@@ -8721,44 +8721,44 @@
 #define TWI_CONFIG_LOG_ENABLED 0
 #endif
 //  TWI_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef TWI_CONFIG_LOG_LEVEL
 #define TWI_CONFIG_LOG_LEVEL 3
 #endif
 
 //  TWI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef TWI_CONFIG_INFO_COLOR
 #define TWI_CONFIG_INFO_COLOR 0
 #endif
 
 //  TWI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef TWI_CONFIG_DEBUG_COLOR
 #define TWI_CONFIG_DEBUG_COLOR 0
@@ -8772,44 +8772,44 @@
 #define UART_CONFIG_LOG_ENABLED 0
 #endif
 //  UART_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef UART_CONFIG_LOG_LEVEL
 #define UART_CONFIG_LOG_LEVEL 3
 #endif
 
 //  UART_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef UART_CONFIG_INFO_COLOR
 #define UART_CONFIG_INFO_COLOR 0
 #endif
 
 //  UART_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef UART_CONFIG_DEBUG_COLOR
 #define UART_CONFIG_DEBUG_COLOR 0
@@ -8823,44 +8823,44 @@
 #define USBD_CONFIG_LOG_ENABLED 0
 #endif
 //  USBD_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef USBD_CONFIG_LOG_LEVEL
 #define USBD_CONFIG_LOG_LEVEL 3
 #endif
 
 //  USBD_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef USBD_CONFIG_INFO_COLOR
 #define USBD_CONFIG_INFO_COLOR 0
 #endif
 
 //  USBD_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef USBD_CONFIG_DEBUG_COLOR
 #define USBD_CONFIG_DEBUG_COLOR 0
@@ -8874,44 +8874,44 @@
 #define WDT_CONFIG_LOG_ENABLED 0
 #endif
 //  WDT_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef WDT_CONFIG_LOG_LEVEL
 #define WDT_CONFIG_LOG_LEVEL 3
 #endif
 
 //  WDT_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef WDT_CONFIG_INFO_COLOR
 #define WDT_CONFIG_INFO_COLOR 0
 #endif
 
 //  WDT_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef WDT_CONFIG_DEBUG_COLOR
 #define WDT_CONFIG_DEBUG_COLOR 0
@@ -8919,10 +8919,10 @@
 
 // 
 
-//  
+// 
 //==========================================================
 
-//  nrf_log in nRF_Libraries 
+//  nrf_log in nRF_Libraries
 
 //==========================================================
 //  APP_BUTTON_CONFIG_LOG_ENABLED - Enables logging in the module.
@@ -8931,60 +8931,60 @@
 #define APP_BUTTON_CONFIG_LOG_ENABLED 0
 #endif
 //  APP_BUTTON_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef APP_BUTTON_CONFIG_LOG_LEVEL
 #define APP_BUTTON_CONFIG_LOG_LEVEL 3
 #endif
 
 //  APP_BUTTON_CONFIG_INITIAL_LOG_LEVEL  - Initial severity level if dynamic filtering is enabled.
- 
+
 
 //  If module generates a lot of logs, initial log level can
 //  be decreased to prevent flooding. Severity level can be
 //  increased on instance basis.
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef APP_BUTTON_CONFIG_INITIAL_LOG_LEVEL
 #define APP_BUTTON_CONFIG_INITIAL_LOG_LEVEL 3
 #endif
 
 //  APP_BUTTON_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef APP_BUTTON_CONFIG_INFO_COLOR
 #define APP_BUTTON_CONFIG_INFO_COLOR 0
 #endif
 
 //  APP_BUTTON_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef APP_BUTTON_CONFIG_DEBUG_COLOR
 #define APP_BUTTON_CONFIG_DEBUG_COLOR 0
@@ -8998,60 +8998,60 @@
 #define APP_TIMER_CONFIG_LOG_ENABLED 0
 #endif
 //  APP_TIMER_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef APP_TIMER_CONFIG_LOG_LEVEL
 #define APP_TIMER_CONFIG_LOG_LEVEL 3
 #endif
 
 //  APP_TIMER_CONFIG_INITIAL_LOG_LEVEL  - Initial severity level if dynamic filtering is enabled.
- 
+
 
 //  If module generates a lot of logs, initial log level can
 //  be decreased to prevent flooding. Severity level can be
 //  increased on instance basis.
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef APP_TIMER_CONFIG_INITIAL_LOG_LEVEL
 #define APP_TIMER_CONFIG_INITIAL_LOG_LEVEL 3
 #endif
 
 //  APP_TIMER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef APP_TIMER_CONFIG_INFO_COLOR
 #define APP_TIMER_CONFIG_INFO_COLOR 0
 #endif
 
 //  APP_TIMER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef APP_TIMER_CONFIG_DEBUG_COLOR
 #define APP_TIMER_CONFIG_DEBUG_COLOR 0
@@ -9065,44 +9065,44 @@
 #define APP_USBD_CDC_ACM_CONFIG_LOG_ENABLED 0
 #endif
 //  APP_USBD_CDC_ACM_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef APP_USBD_CDC_ACM_CONFIG_LOG_LEVEL
 #define APP_USBD_CDC_ACM_CONFIG_LOG_LEVEL 3
 #endif
 
 //  APP_USBD_CDC_ACM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef APP_USBD_CDC_ACM_CONFIG_INFO_COLOR
 #define APP_USBD_CDC_ACM_CONFIG_INFO_COLOR 0
 #endif
 
 //  APP_USBD_CDC_ACM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef APP_USBD_CDC_ACM_CONFIG_DEBUG_COLOR
 #define APP_USBD_CDC_ACM_CONFIG_DEBUG_COLOR 0
@@ -9116,44 +9116,44 @@
 #define APP_USBD_CONFIG_LOG_ENABLED 0
 #endif
 //  APP_USBD_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef APP_USBD_CONFIG_LOG_LEVEL
 #define APP_USBD_CONFIG_LOG_LEVEL 3
 #endif
 
 //  APP_USBD_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef APP_USBD_CONFIG_INFO_COLOR
 #define APP_USBD_CONFIG_INFO_COLOR 0
 #endif
 
 //  APP_USBD_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef APP_USBD_CONFIG_DEBUG_COLOR
 #define APP_USBD_CONFIG_DEBUG_COLOR 0
@@ -9167,44 +9167,44 @@
 #define APP_USBD_DUMMY_CONFIG_LOG_ENABLED 0
 #endif
 //  APP_USBD_DUMMY_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef APP_USBD_DUMMY_CONFIG_LOG_LEVEL
 #define APP_USBD_DUMMY_CONFIG_LOG_LEVEL 3
 #endif
 
 //  APP_USBD_DUMMY_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef APP_USBD_DUMMY_CONFIG_INFO_COLOR
 #define APP_USBD_DUMMY_CONFIG_INFO_COLOR 0
 #endif
 
 //  APP_USBD_DUMMY_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef APP_USBD_DUMMY_CONFIG_DEBUG_COLOR
 #define APP_USBD_DUMMY_CONFIG_DEBUG_COLOR 0
@@ -9218,44 +9218,44 @@
 #define APP_USBD_MSC_CONFIG_LOG_ENABLED 0
 #endif
 //  APP_USBD_MSC_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef APP_USBD_MSC_CONFIG_LOG_LEVEL
 #define APP_USBD_MSC_CONFIG_LOG_LEVEL 3
 #endif
 
 //  APP_USBD_MSC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef APP_USBD_MSC_CONFIG_INFO_COLOR
 #define APP_USBD_MSC_CONFIG_INFO_COLOR 0
 #endif
 
 //  APP_USBD_MSC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef APP_USBD_MSC_CONFIG_DEBUG_COLOR
 #define APP_USBD_MSC_CONFIG_DEBUG_COLOR 0
@@ -9269,44 +9269,44 @@
 #define APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_ENABLED 0
 #endif
 //  APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_LEVEL
 #define APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_LEVEL 3
 #endif
 
 //  APP_USBD_NRF_DFU_TRIGGER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_INFO_COLOR
 #define APP_USBD_NRF_DFU_TRIGGER_CONFIG_INFO_COLOR 0
 #endif
 
 //  APP_USBD_NRF_DFU_TRIGGER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_DEBUG_COLOR
 #define APP_USBD_NRF_DFU_TRIGGER_CONFIG_DEBUG_COLOR 0
@@ -9320,56 +9320,56 @@
 #define NRF_ATFIFO_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_ATFIFO_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_ATFIFO_CONFIG_LOG_LEVEL
 #define NRF_ATFIFO_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_ATFIFO_CONFIG_LOG_INIT_FILTER_LEVEL  - Initial severity level if dynamic filtering is enabled
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_ATFIFO_CONFIG_LOG_INIT_FILTER_LEVEL
 #define NRF_ATFIFO_CONFIG_LOG_INIT_FILTER_LEVEL 3
 #endif
 
 //  NRF_ATFIFO_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_ATFIFO_CONFIG_INFO_COLOR
 #define NRF_ATFIFO_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_ATFIFO_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_ATFIFO_CONFIG_DEBUG_COLOR
 #define NRF_ATFIFO_CONFIG_DEBUG_COLOR 0
@@ -9383,60 +9383,60 @@
 #define NRF_BALLOC_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_BALLOC_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_BALLOC_CONFIG_LOG_LEVEL
 #define NRF_BALLOC_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL  - Initial severity level if dynamic filtering is enabled.
- 
+
 
 //  If module generates a lot of logs, initial log level can
 //  be decreased to prevent flooding. Severity level can be
 //  increased on instance basis.
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL
 #define NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL 3
 #endif
 
 //  NRF_BALLOC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_BALLOC_CONFIG_INFO_COLOR
 #define NRF_BALLOC_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_BALLOC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_BALLOC_CONFIG_DEBUG_COLOR
 #define NRF_BALLOC_CONFIG_DEBUG_COLOR 0
@@ -9450,56 +9450,56 @@
 #define NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_LEVEL
 #define NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_INIT_FILTER_LEVEL  - Initial severity level if dynamic filtering is enabled
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_INIT_FILTER_LEVEL
 #define NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_INIT_FILTER_LEVEL 3
 #endif
 
 //  NRF_BLOCK_DEV_EMPTY_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_INFO_COLOR
 #define NRF_BLOCK_DEV_EMPTY_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_BLOCK_DEV_EMPTY_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_DEBUG_COLOR
 #define NRF_BLOCK_DEV_EMPTY_CONFIG_DEBUG_COLOR 0
@@ -9513,56 +9513,56 @@
 #define NRF_BLOCK_DEV_QSPI_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_BLOCK_DEV_QSPI_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_BLOCK_DEV_QSPI_CONFIG_LOG_LEVEL
 #define NRF_BLOCK_DEV_QSPI_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_BLOCK_DEV_QSPI_CONFIG_LOG_INIT_FILTER_LEVEL  - Initial severity level if dynamic filtering is enabled
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_BLOCK_DEV_QSPI_CONFIG_LOG_INIT_FILTER_LEVEL
 #define NRF_BLOCK_DEV_QSPI_CONFIG_LOG_INIT_FILTER_LEVEL 3
 #endif
 
 //  NRF_BLOCK_DEV_QSPI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_BLOCK_DEV_QSPI_CONFIG_INFO_COLOR
 #define NRF_BLOCK_DEV_QSPI_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_BLOCK_DEV_QSPI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_BLOCK_DEV_QSPI_CONFIG_DEBUG_COLOR
 #define NRF_BLOCK_DEV_QSPI_CONFIG_DEBUG_COLOR 0
@@ -9576,56 +9576,56 @@
 #define NRF_BLOCK_DEV_RAM_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_BLOCK_DEV_RAM_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_BLOCK_DEV_RAM_CONFIG_LOG_LEVEL
 #define NRF_BLOCK_DEV_RAM_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_BLOCK_DEV_RAM_CONFIG_LOG_INIT_FILTER_LEVEL  - Initial severity level if dynamic filtering is enabled
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_BLOCK_DEV_RAM_CONFIG_LOG_INIT_FILTER_LEVEL
 #define NRF_BLOCK_DEV_RAM_CONFIG_LOG_INIT_FILTER_LEVEL 3
 #endif
 
 //  NRF_BLOCK_DEV_RAM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_BLOCK_DEV_RAM_CONFIG_INFO_COLOR
 #define NRF_BLOCK_DEV_RAM_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_BLOCK_DEV_RAM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_BLOCK_DEV_RAM_CONFIG_DEBUG_COLOR
 #define NRF_BLOCK_DEV_RAM_CONFIG_DEBUG_COLOR 0
@@ -9639,44 +9639,44 @@
 #define NRF_CLI_BLE_UART_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_CLI_BLE_UART_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_CLI_BLE_UART_CONFIG_LOG_LEVEL
 #define NRF_CLI_BLE_UART_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_CLI_BLE_UART_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_CLI_BLE_UART_CONFIG_INFO_COLOR
 #define NRF_CLI_BLE_UART_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_CLI_BLE_UART_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_CLI_BLE_UART_CONFIG_DEBUG_COLOR
 #define NRF_CLI_BLE_UART_CONFIG_DEBUG_COLOR 0
@@ -9690,44 +9690,44 @@
 #define NRF_CLI_LIBUARTE_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_CLI_LIBUARTE_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_CLI_LIBUARTE_CONFIG_LOG_LEVEL
 #define NRF_CLI_LIBUARTE_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_CLI_LIBUARTE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_CLI_LIBUARTE_CONFIG_INFO_COLOR
 #define NRF_CLI_LIBUARTE_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_CLI_LIBUARTE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_CLI_LIBUARTE_CONFIG_DEBUG_COLOR
 #define NRF_CLI_LIBUARTE_CONFIG_DEBUG_COLOR 0
@@ -9741,44 +9741,44 @@
 #define NRF_CLI_UART_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_CLI_UART_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_CLI_UART_CONFIG_LOG_LEVEL
 #define NRF_CLI_UART_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_CLI_UART_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_CLI_UART_CONFIG_INFO_COLOR
 #define NRF_CLI_UART_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_CLI_UART_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_CLI_UART_CONFIG_DEBUG_COLOR
 #define NRF_CLI_UART_CONFIG_DEBUG_COLOR 0
@@ -9792,44 +9792,44 @@
 #define NRF_LIBUARTE_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_LIBUARTE_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_LIBUARTE_CONFIG_LOG_LEVEL
 #define NRF_LIBUARTE_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_LIBUARTE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_LIBUARTE_CONFIG_INFO_COLOR
 #define NRF_LIBUARTE_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_LIBUARTE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_LIBUARTE_CONFIG_DEBUG_COLOR
 #define NRF_LIBUARTE_CONFIG_DEBUG_COLOR 0
@@ -9843,44 +9843,44 @@
 #define NRF_MEMOBJ_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_MEMOBJ_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_MEMOBJ_CONFIG_LOG_LEVEL
 #define NRF_MEMOBJ_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_MEMOBJ_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_MEMOBJ_CONFIG_INFO_COLOR
 #define NRF_MEMOBJ_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_MEMOBJ_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_MEMOBJ_CONFIG_DEBUG_COLOR
 #define NRF_MEMOBJ_CONFIG_DEBUG_COLOR 0
@@ -9894,44 +9894,44 @@
 #define NRF_PWR_MGMT_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_PWR_MGMT_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_PWR_MGMT_CONFIG_LOG_LEVEL
 #define NRF_PWR_MGMT_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_PWR_MGMT_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_PWR_MGMT_CONFIG_INFO_COLOR
 #define NRF_PWR_MGMT_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_PWR_MGMT_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_PWR_MGMT_CONFIG_DEBUG_COLOR
 #define NRF_PWR_MGMT_CONFIG_DEBUG_COLOR 0
@@ -9945,56 +9945,56 @@
 #define NRF_QUEUE_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_QUEUE_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_QUEUE_CONFIG_LOG_LEVEL
 #define NRF_QUEUE_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_QUEUE_CONFIG_LOG_INIT_FILTER_LEVEL  - Initial severity level if dynamic filtering is enabled
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_QUEUE_CONFIG_LOG_INIT_FILTER_LEVEL
 #define NRF_QUEUE_CONFIG_LOG_INIT_FILTER_LEVEL 3
 #endif
 
 //  NRF_QUEUE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_QUEUE_CONFIG_INFO_COLOR
 #define NRF_QUEUE_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_QUEUE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_QUEUE_CONFIG_DEBUG_COLOR
 #define NRF_QUEUE_CONFIG_DEBUG_COLOR 0
@@ -10008,44 +10008,44 @@
 #define NRF_SDH_ANT_LOG_ENABLED 0
 #endif
 //  NRF_SDH_ANT_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_SDH_ANT_LOG_LEVEL
 #define NRF_SDH_ANT_LOG_LEVEL 3
 #endif
 
 //  NRF_SDH_ANT_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_SDH_ANT_INFO_COLOR
 #define NRF_SDH_ANT_INFO_COLOR 0
 #endif
 
 //  NRF_SDH_ANT_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_SDH_ANT_DEBUG_COLOR
 #define NRF_SDH_ANT_DEBUG_COLOR 0
@@ -10059,44 +10059,44 @@
 #define NRF_SDH_BLE_LOG_ENABLED 1
 #endif
 //  NRF_SDH_BLE_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_SDH_BLE_LOG_LEVEL
 #define NRF_SDH_BLE_LOG_LEVEL 3
 #endif
 
 //  NRF_SDH_BLE_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_SDH_BLE_INFO_COLOR
 #define NRF_SDH_BLE_INFO_COLOR 0
 #endif
 
 //  NRF_SDH_BLE_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_SDH_BLE_DEBUG_COLOR
 #define NRF_SDH_BLE_DEBUG_COLOR 0
@@ -10110,44 +10110,44 @@
 #define NRF_SDH_LOG_ENABLED 1
 #endif
 //  NRF_SDH_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_SDH_LOG_LEVEL
 #define NRF_SDH_LOG_LEVEL 3
 #endif
 
 //  NRF_SDH_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_SDH_INFO_COLOR
 #define NRF_SDH_INFO_COLOR 0
 #endif
 
 //  NRF_SDH_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_SDH_DEBUG_COLOR
 #define NRF_SDH_DEBUG_COLOR 0
@@ -10161,44 +10161,44 @@
 #define NRF_SDH_SOC_LOG_ENABLED 1
 #endif
 //  NRF_SDH_SOC_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_SDH_SOC_LOG_LEVEL
 #define NRF_SDH_SOC_LOG_LEVEL 3
 #endif
 
 //  NRF_SDH_SOC_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_SDH_SOC_INFO_COLOR
 #define NRF_SDH_SOC_INFO_COLOR 0
 #endif
 
 //  NRF_SDH_SOC_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_SDH_SOC_DEBUG_COLOR
 #define NRF_SDH_SOC_DEBUG_COLOR 0
@@ -10212,44 +10212,44 @@
 #define NRF_SORTLIST_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_SORTLIST_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_SORTLIST_CONFIG_LOG_LEVEL
 #define NRF_SORTLIST_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_SORTLIST_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_SORTLIST_CONFIG_INFO_COLOR
 #define NRF_SORTLIST_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_SORTLIST_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_SORTLIST_CONFIG_DEBUG_COLOR
 #define NRF_SORTLIST_CONFIG_DEBUG_COLOR 0
@@ -10263,44 +10263,44 @@
 #define NRF_TWI_SENSOR_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_TWI_SENSOR_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_TWI_SENSOR_CONFIG_LOG_LEVEL
 #define NRF_TWI_SENSOR_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_TWI_SENSOR_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_TWI_SENSOR_CONFIG_INFO_COLOR
 #define NRF_TWI_SENSOR_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_TWI_SENSOR_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_TWI_SENSOR_CONFIG_DEBUG_COLOR
 #define NRF_TWI_SENSOR_CONFIG_DEBUG_COLOR 0
@@ -10314,44 +10314,44 @@
 #define PM_LOG_ENABLED 1
 #endif
 //  PM_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef PM_LOG_LEVEL
 #define PM_LOG_LEVEL 3
 #endif
 
 //  PM_LOG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef PM_LOG_INFO_COLOR
 #define PM_LOG_INFO_COLOR 0
 #endif
 
 //  PM_LOG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef PM_LOG_DEBUG_COLOR
 #define PM_LOG_DEBUG_COLOR 0
@@ -10359,10 +10359,10 @@
 
 // 
 
-//  
+// 
 //==========================================================
 
-//  nrf_log in nRF_Serialization 
+//  nrf_log in nRF_Serialization
 
 //==========================================================
 //  SER_HAL_TRANSPORT_CONFIG_LOG_ENABLED - Enables logging in the module.
@@ -10371,44 +10371,44 @@
 #define SER_HAL_TRANSPORT_CONFIG_LOG_ENABLED 0
 #endif
 //  SER_HAL_TRANSPORT_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef SER_HAL_TRANSPORT_CONFIG_LOG_LEVEL
 #define SER_HAL_TRANSPORT_CONFIG_LOG_LEVEL 3
 #endif
 
 //  SER_HAL_TRANSPORT_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef SER_HAL_TRANSPORT_CONFIG_INFO_COLOR
 #define SER_HAL_TRANSPORT_CONFIG_INFO_COLOR 0
 #endif
 
 //  SER_HAL_TRANSPORT_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef SER_HAL_TRANSPORT_CONFIG_DEBUG_COLOR
 #define SER_HAL_TRANSPORT_CONFIG_DEBUG_COLOR 0
@@ -10416,36 +10416,36 @@
 
 // 
 
-//  
+// 
 //==========================================================
 
-//  
+// 
 //==========================================================
 
 // 
 
 //  NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED  - nrf_log_str_formatter - Log string formatter
- 
+
 
 #ifndef NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED
 #define NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED 1
 #endif
 
-//  
+// 
 //==========================================================
 
-//  nRF_NFC 
+//  nRF_NFC
 
 //==========================================================
 //  NFC_AC_REC_ENABLED  - nfc_ac_rec - NFC NDEF Alternative Carrier record encoder
- 
+
 
 #ifndef NFC_AC_REC_ENABLED
 #define NFC_AC_REC_ENABLED 0
 #endif
 
 //  NFC_AC_REC_PARSER_ENABLED  - nfc_ac_rec_parser - Alternative Carrier record parser
- 
+
 
 #ifndef NFC_AC_REC_PARSER_ENABLED
 #define NFC_AC_REC_PARSER_ENABLED 0
@@ -10457,9 +10457,9 @@
 #define NFC_BLE_OOB_ADVDATA_ENABLED 0
 #endif
 //  ADVANCED_ADVDATA_SUPPORT  - Non-mandatory AD types for BLE OOB pairing are encoded inside the NDEF message (e.g. service UUIDs)
- 
-// <1=> Enabled 
-// <0=> Disabled 
+
+// <1=> Enabled
+// <0=> Disabled
 
 #ifndef ADVANCED_ADVDATA_SUPPORT
 #define ADVANCED_ADVDATA_SUPPORT 0
@@ -10468,7 +10468,7 @@
 // 
 
 //  NFC_BLE_OOB_ADVDATA_PARSER_ENABLED  - nfc_ble_oob_advdata_parser - BLE OOB pairing AD data parser
- 
+
 
 #ifndef NFC_BLE_OOB_ADVDATA_PARSER_ENABLED
 #define NFC_BLE_OOB_ADVDATA_PARSER_ENABLED 0
@@ -10485,44 +10485,44 @@
 #define NFC_BLE_PAIR_LIB_LOG_ENABLED 0
 #endif
 //  NFC_BLE_PAIR_LIB_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NFC_BLE_PAIR_LIB_LOG_LEVEL
 #define NFC_BLE_PAIR_LIB_LOG_LEVEL 3
 #endif
 
 //  NFC_BLE_PAIR_LIB_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NFC_BLE_PAIR_LIB_INFO_COLOR
 #define NFC_BLE_PAIR_LIB_INFO_COLOR 0
 #endif
 
 //  NFC_BLE_PAIR_LIB_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NFC_BLE_PAIR_LIB_DEBUG_COLOR
 #define NFC_BLE_PAIR_LIB_DEBUG_COLOR 0
@@ -10541,28 +10541,28 @@
 #define BLE_NFC_SEC_PARAM_BOND 1
 #endif
 //  BLE_NFC_SEC_PARAM_KDIST_OWN_ENC  - Enables Long Term Key and Master Identification distribution by device.
- 
+
 
 #ifndef BLE_NFC_SEC_PARAM_KDIST_OWN_ENC
 #define BLE_NFC_SEC_PARAM_KDIST_OWN_ENC 1
 #endif
 
 //  BLE_NFC_SEC_PARAM_KDIST_OWN_ID  - Enables Identity Resolving Key and Identity Address Information distribution by device.
- 
+
 
 #ifndef BLE_NFC_SEC_PARAM_KDIST_OWN_ID
 #define BLE_NFC_SEC_PARAM_KDIST_OWN_ID 1
 #endif
 
 //  BLE_NFC_SEC_PARAM_KDIST_PEER_ENC  - Enables Long Term Key and Master Identification distribution by peer.
- 
+
 
 #ifndef BLE_NFC_SEC_PARAM_KDIST_PEER_ENC
 #define BLE_NFC_SEC_PARAM_KDIST_PEER_ENC 1
 #endif
 
 //  BLE_NFC_SEC_PARAM_KDIST_PEER_ID  - Enables Identity Resolving Key and Identity Address Information distribution by peer.
- 
+
 
 #ifndef BLE_NFC_SEC_PARAM_KDIST_PEER_ID
 #define BLE_NFC_SEC_PARAM_KDIST_PEER_ID 1
@@ -10571,95 +10571,95 @@
 // 
 
 //  BLE_NFC_SEC_PARAM_MIN_KEY_SIZE  - Minimal size of a security key.
- 
-// <7=> 7 
-// <8=> 8 
-// <9=> 9 
-// <10=> 10 
-// <11=> 11 
-// <12=> 12 
-// <13=> 13 
-// <14=> 14 
-// <15=> 15 
-// <16=> 16 
+
+// <7=> 7
+// <8=> 8
+// <9=> 9
+// <10=> 10
+// <11=> 11
+// <12=> 12
+// <13=> 13
+// <14=> 14
+// <15=> 15
+// <16=> 16
 
 #ifndef BLE_NFC_SEC_PARAM_MIN_KEY_SIZE
 #define BLE_NFC_SEC_PARAM_MIN_KEY_SIZE 7
 #endif
 
 //  BLE_NFC_SEC_PARAM_MAX_KEY_SIZE  - Maximal size of a security key.
- 
-// <7=> 7 
-// <8=> 8 
-// <9=> 9 
-// <10=> 10 
-// <11=> 11 
-// <12=> 12 
-// <13=> 13 
-// <14=> 14 
-// <15=> 15 
-// <16=> 16 
+
+// <7=> 7
+// <8=> 8
+// <9=> 9
+// <10=> 10
+// <11=> 11
+// <12=> 12
+// <13=> 13
+// <14=> 14
+// <15=> 15
+// <16=> 16
 
 #ifndef BLE_NFC_SEC_PARAM_MAX_KEY_SIZE
 #define BLE_NFC_SEC_PARAM_MAX_KEY_SIZE 16
 #endif
 
-//  
+// 
 //==========================================================
 
 // 
 
 //  NFC_BLE_PAIR_MSG_ENABLED  - nfc_ble_pair_msg - NDEF message for OOB pairing encoder
- 
+
 
 #ifndef NFC_BLE_PAIR_MSG_ENABLED
 #define NFC_BLE_PAIR_MSG_ENABLED 0
 #endif
 
 //  NFC_CH_COMMON_ENABLED  - nfc_ble_pair_common - OOB pairing common data
- 
+
 
 #ifndef NFC_CH_COMMON_ENABLED
 #define NFC_CH_COMMON_ENABLED 0
 #endif
 
 //  NFC_EP_OOB_REC_ENABLED  - nfc_ep_oob_rec - EP record for BLE pairing encoder
- 
+
 
 #ifndef NFC_EP_OOB_REC_ENABLED
 #define NFC_EP_OOB_REC_ENABLED 0
 #endif
 
 //  NFC_HS_REC_ENABLED  - nfc_hs_rec - Handover Select NDEF record encoder
- 
+
 
 #ifndef NFC_HS_REC_ENABLED
 #define NFC_HS_REC_ENABLED 0
 #endif
 
 //  NFC_LE_OOB_REC_ENABLED  - nfc_le_oob_rec - LE record for BLE pairing encoder
- 
+
 
 #ifndef NFC_LE_OOB_REC_ENABLED
 #define NFC_LE_OOB_REC_ENABLED 0
 #endif
 
 //  NFC_LE_OOB_REC_PARSER_ENABLED  - nfc_le_oob_rec_parser - LE record parser
- 
+
 
 #ifndef NFC_LE_OOB_REC_PARSER_ENABLED
 #define NFC_LE_OOB_REC_PARSER_ENABLED 0
 #endif
 
 //  NFC_NDEF_LAUNCHAPP_MSG_ENABLED  - nfc_launchapp_msg - Encoding data for NDEF Application Launching message for NFC Tag
- 
+
 
 #ifndef NFC_NDEF_LAUNCHAPP_MSG_ENABLED
 #define NFC_NDEF_LAUNCHAPP_MSG_ENABLED 0
 #endif
 
 //  NFC_NDEF_LAUNCHAPP_REC_ENABLED  - nfc_launchapp_rec - Encoding data for NDEF Application Launching record for NFC Tag
- 
+
 
 #ifndef NFC_NDEF_LAUNCHAPP_REC_ENABLED
 #define NFC_NDEF_LAUNCHAPP_REC_ENABLED 0
@@ -10671,9 +10671,9 @@
 #define NFC_NDEF_MSG_ENABLED 0
 #endif
 //  NFC_NDEF_MSG_TAG_TYPE  - NFC Tag Type
- 
-// <2=> Type 2 Tag 
-// <4=> Type 4 Tag 
+
+// <2=> Type 2 Tag
+// <4=> Type 4 Tag
 
 #ifndef NFC_NDEF_MSG_TAG_TYPE
 #define NFC_NDEF_MSG_TAG_TYPE 2
@@ -10692,28 +10692,28 @@
 #define NFC_NDEF_MSG_PARSER_LOG_ENABLED 0
 #endif
 //  NFC_NDEF_MSG_PARSER_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NFC_NDEF_MSG_PARSER_LOG_LEVEL
 #define NFC_NDEF_MSG_PARSER_LOG_LEVEL 3
 #endif
 
 //  NFC_NDEF_MSG_PARSER_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NFC_NDEF_MSG_PARSER_INFO_COLOR
 #define NFC_NDEF_MSG_PARSER_INFO_COLOR 0
@@ -10724,7 +10724,7 @@
 // 
 
 //  NFC_NDEF_RECORD_ENABLED  - nfc_ndef_record - NFC NDEF Record generator module
- 
+
 
 #ifndef NFC_NDEF_RECORD_ENABLED
 #define NFC_NDEF_RECORD_ENABLED 0
@@ -10741,28 +10741,28 @@
 #define NFC_NDEF_RECORD_PARSER_LOG_ENABLED 0
 #endif
 //  NFC_NDEF_RECORD_PARSER_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NFC_NDEF_RECORD_PARSER_LOG_LEVEL
 #define NFC_NDEF_RECORD_PARSER_LOG_LEVEL 3
 #endif
 
 //  NFC_NDEF_RECORD_PARSER_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NFC_NDEF_RECORD_PARSER_INFO_COLOR
 #define NFC_NDEF_RECORD_PARSER_INFO_COLOR 0
@@ -10773,21 +10773,21 @@
 // 
 
 //  NFC_NDEF_TEXT_RECORD_ENABLED  - nfc_text_rec - Encoding data for a text record for NFC Tag
- 
+
 
 #ifndef NFC_NDEF_TEXT_RECORD_ENABLED
 #define NFC_NDEF_TEXT_RECORD_ENABLED 0
 #endif
 
 //  NFC_NDEF_URI_MSG_ENABLED  - nfc_uri_msg - Encoding data for NDEF message with URI record for NFC Tag
- 
+
 
 #ifndef NFC_NDEF_URI_MSG_ENABLED
 #define NFC_NDEF_URI_MSG_ENABLED 0
 #endif
 
 //  NFC_NDEF_URI_REC_ENABLED  - nfc_uri_rec - Encoding data for a URI record for NFC Tag
- 
+
 
 #ifndef NFC_NDEF_URI_REC_ENABLED
 #define NFC_NDEF_URI_REC_ENABLED 0
@@ -10804,44 +10804,44 @@
 #define NFC_PLATFORM_LOG_ENABLED 0
 #endif
 //  NFC_PLATFORM_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NFC_PLATFORM_LOG_LEVEL
 #define NFC_PLATFORM_LOG_LEVEL 3
 #endif
 
 //  NFC_PLATFORM_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NFC_PLATFORM_INFO_COLOR
 #define NFC_PLATFORM_INFO_COLOR 0
 #endif
 
 //  NFC_PLATFORM_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NFC_PLATFORM_DEBUG_COLOR
 #define NFC_PLATFORM_DEBUG_COLOR 0
@@ -10862,28 +10862,28 @@
 #define NFC_T2T_PARSER_LOG_ENABLED 0
 #endif
 //  NFC_T2T_PARSER_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NFC_T2T_PARSER_LOG_LEVEL
 #define NFC_T2T_PARSER_LOG_LEVEL 3
 #endif
 
 //  NFC_T2T_PARSER_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NFC_T2T_PARSER_INFO_COLOR
 #define NFC_T2T_PARSER_INFO_COLOR 0
@@ -10904,28 +10904,28 @@
 #define NFC_T4T_APDU_LOG_ENABLED 0
 #endif
 //  NFC_T4T_APDU_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NFC_T4T_APDU_LOG_LEVEL
 #define NFC_T4T_APDU_LOG_LEVEL 3
 #endif
 
 //  NFC_T4T_APDU_LOG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NFC_T4T_APDU_LOG_COLOR
 #define NFC_T4T_APDU_LOG_COLOR 0
@@ -10946,28 +10946,28 @@
 #define NFC_T4T_CC_FILE_PARSER_LOG_ENABLED 0
 #endif
 //  NFC_T4T_CC_FILE_PARSER_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NFC_T4T_CC_FILE_PARSER_LOG_LEVEL
 #define NFC_T4T_CC_FILE_PARSER_LOG_LEVEL 3
 #endif
 
 //  NFC_T4T_CC_FILE_PARSER_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NFC_T4T_CC_FILE_PARSER_INFO_COLOR
 #define NFC_T4T_CC_FILE_PARSER_INFO_COLOR 0
@@ -10988,28 +10988,28 @@
 #define NFC_T4T_HL_DETECTION_PROCEDURES_LOG_ENABLED 0
 #endif
 //  NFC_T4T_HL_DETECTION_PROCEDURES_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NFC_T4T_HL_DETECTION_PROCEDURES_LOG_LEVEL
 #define NFC_T4T_HL_DETECTION_PROCEDURES_LOG_LEVEL 3
 #endif
 
 //  NFC_T4T_HL_DETECTION_PROCEDURES_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NFC_T4T_HL_DETECTION_PROCEDURES_INFO_COLOR
 #define NFC_T4T_HL_DETECTION_PROCEDURES_INFO_COLOR 0
@@ -11017,12 +11017,12 @@
 
 // 
 
-//  APDU_BUFF_SIZE - Size (in bytes) of the buffer for APDU storage 
+//  APDU_BUFF_SIZE - Size (in bytes) of the buffer for APDU storage
 #ifndef APDU_BUFF_SIZE
 #define APDU_BUFF_SIZE 250
 #endif
 
-//  CC_STORAGE_BUFF_SIZE - Size (in bytes) of the buffer for CC file storage 
+//  CC_STORAGE_BUFF_SIZE - Size (in bytes) of the buffer for CC file storage
 #ifndef CC_STORAGE_BUFF_SIZE
 #define CC_STORAGE_BUFF_SIZE 64
 #endif
@@ -11040,28 +11040,28 @@
 #define NFC_T4T_TLV_BLOCK_PARSER_LOG_ENABLED 0
 #endif
 //  NFC_T4T_TLV_BLOCK_PARSER_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NFC_T4T_TLV_BLOCK_PARSER_LOG_LEVEL
 #define NFC_T4T_TLV_BLOCK_PARSER_LOG_LEVEL 3
 #endif
 
 //  NFC_T4T_TLV_BLOCK_PARSER_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NFC_T4T_TLV_BLOCK_PARSER_INFO_COLOR
 #define NFC_T4T_TLV_BLOCK_PARSER_INFO_COLOR 0
@@ -11071,10 +11071,10 @@
 
 // 
 
-//  
+// 
 //==========================================================
 
-//  nRF_SoftDevice 
+//  nRF_SoftDevice
 
 //==========================================================
 //  NRF_SDH_BLE_ENABLED - nrf_sdh_ble - SoftDevice BLE event handler
@@ -11087,7 +11087,7 @@
 //  The SoftDevice handler will configure the stack with these parameters when calling @ref nrf_sdh_ble_default_cfg_set.
 //  Other libraries might depend on these values; keep them up-to-date even if you are not explicitely calling @ref nrf_sdh_ble_default_cfg_set.
 //==========================================================
-//  NRF_SDH_BLE_GAP_DATA_LENGTH   <27-251> 
+//  NRF_SDH_BLE_GAP_DATA_LENGTH   <27-251>
 
 
 //  Requested BLE GAP data length to be negotiated.
@@ -11096,59 +11096,59 @@
 #define NRF_SDH_BLE_GAP_DATA_LENGTH 27
 #endif
 
-//  NRF_SDH_BLE_PERIPHERAL_LINK_COUNT - Maximum number of peripheral links. 
+//  NRF_SDH_BLE_PERIPHERAL_LINK_COUNT - Maximum number of peripheral links.
 #ifndef NRF_SDH_BLE_PERIPHERAL_LINK_COUNT
 #define NRF_SDH_BLE_PERIPHERAL_LINK_COUNT 0
 #endif
 
-//  NRF_SDH_BLE_CENTRAL_LINK_COUNT - Maximum number of central links. 
+//  NRF_SDH_BLE_CENTRAL_LINK_COUNT - Maximum number of central links.
 #ifndef NRF_SDH_BLE_CENTRAL_LINK_COUNT
 #define NRF_SDH_BLE_CENTRAL_LINK_COUNT 0
 #endif
 
-//  NRF_SDH_BLE_TOTAL_LINK_COUNT - Total link count. 
+//  NRF_SDH_BLE_TOTAL_LINK_COUNT - Total link count.
 //  Maximum number of total concurrent connections using the default configuration.
 
 #ifndef NRF_SDH_BLE_TOTAL_LINK_COUNT
 #define NRF_SDH_BLE_TOTAL_LINK_COUNT 1
 #endif
 
-//  NRF_SDH_BLE_GAP_EVENT_LENGTH - GAP event length. 
+//  NRF_SDH_BLE_GAP_EVENT_LENGTH - GAP event length.
 //  The time set aside for this connection on every connection interval in 1.25 ms units.
 
 #ifndef NRF_SDH_BLE_GAP_EVENT_LENGTH
 #define NRF_SDH_BLE_GAP_EVENT_LENGTH 6
 #endif
 
-//  NRF_SDH_BLE_GATT_MAX_MTU_SIZE - Static maximum MTU size. 
+//  NRF_SDH_BLE_GATT_MAX_MTU_SIZE - Static maximum MTU size.
 #ifndef NRF_SDH_BLE_GATT_MAX_MTU_SIZE
 #define NRF_SDH_BLE_GATT_MAX_MTU_SIZE 23
 #endif
 
-//  NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE - Attribute Table size in bytes. The size must be a multiple of 4. 
+//  NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE - Attribute Table size in bytes. The size must be a multiple of 4.
 #ifndef NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE
 #define NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE 1408
 #endif
 
-//  NRF_SDH_BLE_VS_UUID_COUNT - The number of vendor-specific UUIDs. 
+//  NRF_SDH_BLE_VS_UUID_COUNT - The number of vendor-specific UUIDs.
 #ifndef NRF_SDH_BLE_VS_UUID_COUNT
 #define NRF_SDH_BLE_VS_UUID_COUNT 0
 #endif
 
 //  NRF_SDH_BLE_SERVICE_CHANGED  - Include the Service Changed characteristic in the Attribute Table.
- 
+
 
 #ifndef NRF_SDH_BLE_SERVICE_CHANGED
 #define NRF_SDH_BLE_SERVICE_CHANGED 0
 #endif
 
-//  
+// 
 //==========================================================
 
 //  BLE Observers - Observers and priority levels
 
 //==========================================================
-//  NRF_SDH_BLE_OBSERVER_PRIO_LEVELS - Total number of priority levels for BLE observers. 
+//  NRF_SDH_BLE_OBSERVER_PRIO_LEVELS - Total number of priority levels for BLE observers.
 //  This setting configures the number of priority levels available for BLE event handlers.
 //  The priority level of a handler determines the order in which it receives events, with respect to other handlers.
 
@@ -11159,316 +11159,316 @@
 //  BLE Observers priorities - Invididual priorities
 
 //==========================================================
-//  BLE_ADV_BLE_OBSERVER_PRIO  
+//  BLE_ADV_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Advertising module.
 
 #ifndef BLE_ADV_BLE_OBSERVER_PRIO
 #define BLE_ADV_BLE_OBSERVER_PRIO 1
 #endif
 
-//  BLE_ANCS_C_BLE_OBSERVER_PRIO  
+//  BLE_ANCS_C_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Apple Notification Service Client.
 
 #ifndef BLE_ANCS_C_BLE_OBSERVER_PRIO
 #define BLE_ANCS_C_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_ANS_C_BLE_OBSERVER_PRIO  
+//  BLE_ANS_C_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Alert Notification Service Client.
 
 #ifndef BLE_ANS_C_BLE_OBSERVER_PRIO
 #define BLE_ANS_C_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_BAS_BLE_OBSERVER_PRIO  
+//  BLE_BAS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Battery Service.
 
 #ifndef BLE_BAS_BLE_OBSERVER_PRIO
 #define BLE_BAS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_BAS_C_BLE_OBSERVER_PRIO  
+//  BLE_BAS_C_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Battery Service Client.
 
 #ifndef BLE_BAS_C_BLE_OBSERVER_PRIO
 #define BLE_BAS_C_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_BPS_BLE_OBSERVER_PRIO  
+//  BLE_BPS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Blood Pressure Service.
 
 #ifndef BLE_BPS_BLE_OBSERVER_PRIO
 #define BLE_BPS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_CONN_PARAMS_BLE_OBSERVER_PRIO  
+//  BLE_CONN_PARAMS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Connection parameters module.
 
 #ifndef BLE_CONN_PARAMS_BLE_OBSERVER_PRIO
 #define BLE_CONN_PARAMS_BLE_OBSERVER_PRIO 1
 #endif
 
-//  BLE_CONN_STATE_BLE_OBSERVER_PRIO  
+//  BLE_CONN_STATE_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Connection State module.
 
 #ifndef BLE_CONN_STATE_BLE_OBSERVER_PRIO
 #define BLE_CONN_STATE_BLE_OBSERVER_PRIO 0
 #endif
 
-//  BLE_CSCS_BLE_OBSERVER_PRIO  
+//  BLE_CSCS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Cycling Speed and Cadence Service.
 
 #ifndef BLE_CSCS_BLE_OBSERVER_PRIO
 #define BLE_CSCS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_CTS_C_BLE_OBSERVER_PRIO  
+//  BLE_CTS_C_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Current Time Service Client.
 
 #ifndef BLE_CTS_C_BLE_OBSERVER_PRIO
 #define BLE_CTS_C_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_DB_DISC_BLE_OBSERVER_PRIO  
+//  BLE_DB_DISC_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Database Discovery module.
 
 #ifndef BLE_DB_DISC_BLE_OBSERVER_PRIO
 #define BLE_DB_DISC_BLE_OBSERVER_PRIO 1
 #endif
 
-//  BLE_DFU_BLE_OBSERVER_PRIO  
+//  BLE_DFU_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the DFU Service.
 
 #ifndef BLE_DFU_BLE_OBSERVER_PRIO
 #define BLE_DFU_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_DIS_C_BLE_OBSERVER_PRIO  
+//  BLE_DIS_C_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Device Information Client.
 
 #ifndef BLE_DIS_C_BLE_OBSERVER_PRIO
 #define BLE_DIS_C_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_GLS_BLE_OBSERVER_PRIO  
+//  BLE_GLS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Glucose Service.
 
 #ifndef BLE_GLS_BLE_OBSERVER_PRIO
 #define BLE_GLS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_HIDS_BLE_OBSERVER_PRIO  
+//  BLE_HIDS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Human Interface Device Service.
 
 #ifndef BLE_HIDS_BLE_OBSERVER_PRIO
 #define BLE_HIDS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_HRS_BLE_OBSERVER_PRIO  
+//  BLE_HRS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Heart Rate Service.
 
 #ifndef BLE_HRS_BLE_OBSERVER_PRIO
 #define BLE_HRS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_HRS_C_BLE_OBSERVER_PRIO  
+//  BLE_HRS_C_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Heart Rate Service Client.
 
 #ifndef BLE_HRS_C_BLE_OBSERVER_PRIO
 #define BLE_HRS_C_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_HTS_BLE_OBSERVER_PRIO  
+//  BLE_HTS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Health Thermometer Service.
 
 #ifndef BLE_HTS_BLE_OBSERVER_PRIO
 #define BLE_HTS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_IAS_BLE_OBSERVER_PRIO  
+//  BLE_IAS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Immediate Alert Service.
 
 #ifndef BLE_IAS_BLE_OBSERVER_PRIO
 #define BLE_IAS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_IAS_C_BLE_OBSERVER_PRIO  
+//  BLE_IAS_C_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Immediate Alert Service Client.
 
 #ifndef BLE_IAS_C_BLE_OBSERVER_PRIO
 #define BLE_IAS_C_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_LBS_BLE_OBSERVER_PRIO  
+//  BLE_LBS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the LED Button Service.
 
 #ifndef BLE_LBS_BLE_OBSERVER_PRIO
 #define BLE_LBS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_LBS_C_BLE_OBSERVER_PRIO  
+//  BLE_LBS_C_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the LED Button Service Client.
 
 #ifndef BLE_LBS_C_BLE_OBSERVER_PRIO
 #define BLE_LBS_C_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_LLS_BLE_OBSERVER_PRIO  
+//  BLE_LLS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Link Loss Service.
 
 #ifndef BLE_LLS_BLE_OBSERVER_PRIO
 #define BLE_LLS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_LNS_BLE_OBSERVER_PRIO  
+//  BLE_LNS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Location Navigation Service.
 
 #ifndef BLE_LNS_BLE_OBSERVER_PRIO
 #define BLE_LNS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_NUS_BLE_OBSERVER_PRIO  
+//  BLE_NUS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the UART Service.
 
 #ifndef BLE_NUS_BLE_OBSERVER_PRIO
 #define BLE_NUS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_NUS_C_BLE_OBSERVER_PRIO  
+//  BLE_NUS_C_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the UART Central Service.
 
 #ifndef BLE_NUS_C_BLE_OBSERVER_PRIO
 #define BLE_NUS_C_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_OTS_BLE_OBSERVER_PRIO  
+//  BLE_OTS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Object transfer service.
 
 #ifndef BLE_OTS_BLE_OBSERVER_PRIO
 #define BLE_OTS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_OTS_C_BLE_OBSERVER_PRIO  
+//  BLE_OTS_C_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Object transfer service client.
 
 #ifndef BLE_OTS_C_BLE_OBSERVER_PRIO
 #define BLE_OTS_C_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_RSCS_BLE_OBSERVER_PRIO  
+//  BLE_RSCS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Running Speed and Cadence Service.
 
 #ifndef BLE_RSCS_BLE_OBSERVER_PRIO
 #define BLE_RSCS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_RSCS_C_BLE_OBSERVER_PRIO  
+//  BLE_RSCS_C_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Running Speed and Cadence Client.
 
 #ifndef BLE_RSCS_C_BLE_OBSERVER_PRIO
 #define BLE_RSCS_C_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_TPS_BLE_OBSERVER_PRIO  
+//  BLE_TPS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the TX Power Service.
 
 #ifndef BLE_TPS_BLE_OBSERVER_PRIO
 #define BLE_TPS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BSP_BTN_BLE_OBSERVER_PRIO  
+//  BSP_BTN_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Button Control module.
 
 #ifndef BSP_BTN_BLE_OBSERVER_PRIO
 #define BSP_BTN_BLE_OBSERVER_PRIO 1
 #endif
 
-//  NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO  
+//  NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the NFC pairing library.
 
 #ifndef NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO
 #define NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO 1
 #endif
 
-//  NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO  
+//  NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the NFC pairing library.
 
 #ifndef NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO
 #define NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO 1
 #endif
 
-//  NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO  
+//  NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the NFC pairing library.
 
 #ifndef NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO
 #define NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO 1
 #endif
 
-//  NRF_BLE_BMS_BLE_OBSERVER_PRIO  
+//  NRF_BLE_BMS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Bond Management Service.
 
 #ifndef NRF_BLE_BMS_BLE_OBSERVER_PRIO
 #define NRF_BLE_BMS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  NRF_BLE_CGMS_BLE_OBSERVER_PRIO  
+//  NRF_BLE_CGMS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Contiuon Glucose Monitoring Service.
 
 #ifndef NRF_BLE_CGMS_BLE_OBSERVER_PRIO
 #define NRF_BLE_CGMS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  NRF_BLE_ES_BLE_OBSERVER_PRIO  
+//  NRF_BLE_ES_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Eddystone module.
 
 #ifndef NRF_BLE_ES_BLE_OBSERVER_PRIO
 #define NRF_BLE_ES_BLE_OBSERVER_PRIO 2
 #endif
 
-//  NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO  
+//  NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the GATT Service Client.
 
 #ifndef NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO
 #define NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO 2
 #endif
 
-//  NRF_BLE_GATT_BLE_OBSERVER_PRIO  
+//  NRF_BLE_GATT_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the GATT module.
 
 #ifndef NRF_BLE_GATT_BLE_OBSERVER_PRIO
 #define NRF_BLE_GATT_BLE_OBSERVER_PRIO 1
 #endif
 
-//  NRF_BLE_GQ_BLE_OBSERVER_PRIO  
+//  NRF_BLE_GQ_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the GATT Queue module.
 
 #ifndef NRF_BLE_GQ_BLE_OBSERVER_PRIO
 #define NRF_BLE_GQ_BLE_OBSERVER_PRIO 1
 #endif
 
-//  NRF_BLE_QWR_BLE_OBSERVER_PRIO  
+//  NRF_BLE_QWR_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Queued writes module.
 
 #ifndef NRF_BLE_QWR_BLE_OBSERVER_PRIO
 #define NRF_BLE_QWR_BLE_OBSERVER_PRIO 2
 #endif
 
-//  NRF_BLE_SCAN_OBSERVER_PRIO  
+//  NRF_BLE_SCAN_OBSERVER_PRIO
 //  Priority for dispatching the BLE events to the Scanning Module.
 
 #ifndef NRF_BLE_SCAN_OBSERVER_PRIO
 #define NRF_BLE_SCAN_OBSERVER_PRIO 1
 #endif
 
-//  PM_BLE_OBSERVER_PRIO - Priority with which BLE events are dispatched to the Peer Manager module. 
+//  PM_BLE_OBSERVER_PRIO - Priority with which BLE events are dispatched to the Peer Manager module.
 #ifndef PM_BLE_OBSERVER_PRIO
 #define PM_BLE_OBSERVER_PRIO 1
 #endif
 
-//  
+// 
 //==========================================================
 
-//  
+// 
 //==========================================================
 
 
@@ -11479,46 +11479,46 @@
 #ifndef NRF_SDH_ENABLED
 #define NRF_SDH_ENABLED 0
 #endif
-//  Dispatch model 
+//  Dispatch model
 
 //  This setting configures how Stack events are dispatched to the application.
 //==========================================================
 //  NRF_SDH_DISPATCH_MODEL
- 
+
 
 //  NRF_SDH_DISPATCH_MODEL_INTERRUPT: SoftDevice events are passed to the application from the interrupt context.
 //  NRF_SDH_DISPATCH_MODEL_APPSH: SoftDevice events are scheduled using @ref app_scheduler.
 //  NRF_SDH_DISPATCH_MODEL_POLLING: SoftDevice events are to be fetched manually.
-// <0=> NRF_SDH_DISPATCH_MODEL_INTERRUPT 
-// <1=> NRF_SDH_DISPATCH_MODEL_APPSH 
-// <2=> NRF_SDH_DISPATCH_MODEL_POLLING 
+// <0=> NRF_SDH_DISPATCH_MODEL_INTERRUPT
+// <1=> NRF_SDH_DISPATCH_MODEL_APPSH
+// <2=> NRF_SDH_DISPATCH_MODEL_POLLING
 
 #ifndef NRF_SDH_DISPATCH_MODEL
 #define NRF_SDH_DISPATCH_MODEL 0
 #endif
 
-//  
+// 
 //==========================================================
 
 //  Clock - SoftDevice clock configuration
 
 //==========================================================
 //  NRF_SDH_CLOCK_LF_SRC  - SoftDevice clock source.
- 
-// <0=> NRF_CLOCK_LF_SRC_RC 
-// <1=> NRF_CLOCK_LF_SRC_XTAL 
-// <2=> NRF_CLOCK_LF_SRC_SYNTH 
+
+// <0=> NRF_CLOCK_LF_SRC_RC
+// <1=> NRF_CLOCK_LF_SRC_XTAL
+// <2=> NRF_CLOCK_LF_SRC_SYNTH
 
 #ifndef NRF_SDH_CLOCK_LF_SRC
 #define NRF_SDH_CLOCK_LF_SRC 1
 #endif
 
-//  NRF_SDH_CLOCK_LF_RC_CTIV - SoftDevice calibration timer interval. 
+//  NRF_SDH_CLOCK_LF_RC_CTIV - SoftDevice calibration timer interval.
 #ifndef NRF_SDH_CLOCK_LF_RC_CTIV
 #define NRF_SDH_CLOCK_LF_RC_CTIV 0
 #endif
 
-//  NRF_SDH_CLOCK_LF_RC_TEMP_CTIV - SoftDevice calibration timer interval under constant temperature. 
+//  NRF_SDH_CLOCK_LF_RC_TEMP_CTIV - SoftDevice calibration timer interval under constant temperature.
 //  How often (in number of calibration intervals) the RC oscillator shall be calibrated
 //   if the temperature has not changed.
 
@@ -11527,31 +11527,31 @@
 #endif
 
 //  NRF_SDH_CLOCK_LF_ACCURACY  - External clock accuracy used in the LL to compute timing.
- 
-// <0=> NRF_CLOCK_LF_ACCURACY_250_PPM 
-// <1=> NRF_CLOCK_LF_ACCURACY_500_PPM 
-// <2=> NRF_CLOCK_LF_ACCURACY_150_PPM 
-// <3=> NRF_CLOCK_LF_ACCURACY_100_PPM 
-// <4=> NRF_CLOCK_LF_ACCURACY_75_PPM 
-// <5=> NRF_CLOCK_LF_ACCURACY_50_PPM 
-// <6=> NRF_CLOCK_LF_ACCURACY_30_PPM 
-// <7=> NRF_CLOCK_LF_ACCURACY_20_PPM 
-// <8=> NRF_CLOCK_LF_ACCURACY_10_PPM 
-// <9=> NRF_CLOCK_LF_ACCURACY_5_PPM 
-// <10=> NRF_CLOCK_LF_ACCURACY_2_PPM 
-// <11=> NRF_CLOCK_LF_ACCURACY_1_PPM 
+
+// <0=> NRF_CLOCK_LF_ACCURACY_250_PPM
+// <1=> NRF_CLOCK_LF_ACCURACY_500_PPM
+// <2=> NRF_CLOCK_LF_ACCURACY_150_PPM
+// <3=> NRF_CLOCK_LF_ACCURACY_100_PPM
+// <4=> NRF_CLOCK_LF_ACCURACY_75_PPM
+// <5=> NRF_CLOCK_LF_ACCURACY_50_PPM
+// <6=> NRF_CLOCK_LF_ACCURACY_30_PPM
+// <7=> NRF_CLOCK_LF_ACCURACY_20_PPM
+// <8=> NRF_CLOCK_LF_ACCURACY_10_PPM
+// <9=> NRF_CLOCK_LF_ACCURACY_5_PPM
+// <10=> NRF_CLOCK_LF_ACCURACY_2_PPM
+// <11=> NRF_CLOCK_LF_ACCURACY_1_PPM
 
 #ifndef NRF_SDH_CLOCK_LF_ACCURACY
 #define NRF_SDH_CLOCK_LF_ACCURACY 7
 #endif
 
-//  
+// 
 //==========================================================
 
 //  SDH Observers - Observers and priority levels
 
 //==========================================================
-//  NRF_SDH_REQ_OBSERVER_PRIO_LEVELS - Total number of priority levels for request observers. 
+//  NRF_SDH_REQ_OBSERVER_PRIO_LEVELS - Total number of priority levels for request observers.
 //  This setting configures the number of priority levels available for the SoftDevice request event handlers.
 //  The priority level of a handler determines the order in which it receives events, with respect to other handlers.
 
@@ -11559,7 +11559,7 @@
 #define NRF_SDH_REQ_OBSERVER_PRIO_LEVELS 2
 #endif
 
-//  NRF_SDH_STATE_OBSERVER_PRIO_LEVELS - Total number of priority levels for state observers. 
+//  NRF_SDH_STATE_OBSERVER_PRIO_LEVELS - Total number of priority levels for state observers.
 //  This setting configures the number of priority levels available for the SoftDevice state event handlers.
 //  The priority level of a handler determines the order in which it receives events, with respect to other handlers.
 
@@ -11567,7 +11567,7 @@
 #define NRF_SDH_STATE_OBSERVER_PRIO_LEVELS 2
 #endif
 
-//  NRF_SDH_STACK_OBSERVER_PRIO_LEVELS - Total number of priority levels for stack event observers. 
+//  NRF_SDH_STACK_OBSERVER_PRIO_LEVELS - Total number of priority levels for stack event observers.
 //  This setting configures the number of priority levels available for the SoftDevice stack event handlers (ANT, BLE, SoC).
 //  The priority level of a handler determines the order in which it receives events, with respect to other handlers.
 
@@ -11579,34 +11579,34 @@
 //  State Observers priorities - Invididual priorities
 
 //==========================================================
-//  CLOCK_CONFIG_STATE_OBSERVER_PRIO  
+//  CLOCK_CONFIG_STATE_OBSERVER_PRIO
 //  Priority with which state events are dispatched to the Clock driver.
 
 #ifndef CLOCK_CONFIG_STATE_OBSERVER_PRIO
 #define CLOCK_CONFIG_STATE_OBSERVER_PRIO 0
 #endif
 
-//  POWER_CONFIG_STATE_OBSERVER_PRIO  
+//  POWER_CONFIG_STATE_OBSERVER_PRIO
 //  Priority with which state events are dispatched to the Power driver.
 
 #ifndef POWER_CONFIG_STATE_OBSERVER_PRIO
 #define POWER_CONFIG_STATE_OBSERVER_PRIO 0
 #endif
 
-//  RNG_CONFIG_STATE_OBSERVER_PRIO  
+//  RNG_CONFIG_STATE_OBSERVER_PRIO
 //  Priority with which state events are dispatched to this module.
 
 #ifndef RNG_CONFIG_STATE_OBSERVER_PRIO
 #define RNG_CONFIG_STATE_OBSERVER_PRIO 0
 #endif
 
-//  
+// 
 //==========================================================
 
 //  Stack Event Observers priorities - Invididual priorities
 
 //==========================================================
-//  NRF_SDH_ANT_STACK_OBSERVER_PRIO  
+//  NRF_SDH_ANT_STACK_OBSERVER_PRIO
 //  This setting configures the priority with which ANT events are processed with respect to other events coming from the stack.
 //  Modify this setting if you need to have ANT events dispatched before or after other stack events, such as BLE or SoC.
 //  Zero is the highest priority.
@@ -11615,7 +11615,7 @@
 #define NRF_SDH_ANT_STACK_OBSERVER_PRIO 0
 #endif
 
-//  NRF_SDH_BLE_STACK_OBSERVER_PRIO  
+//  NRF_SDH_BLE_STACK_OBSERVER_PRIO
 //  This setting configures the priority with which BLE events are processed with respect to other events coming from the stack.
 //  Modify this setting if you need to have BLE events dispatched before or after other stack events, such as ANT or SoC.
 //  Zero is the highest priority.
@@ -11624,7 +11624,7 @@
 #define NRF_SDH_BLE_STACK_OBSERVER_PRIO 0
 #endif
 
-//  NRF_SDH_SOC_STACK_OBSERVER_PRIO  
+//  NRF_SDH_SOC_STACK_OBSERVER_PRIO
 //  This setting configures the priority with which SoC events are processed with respect to other events coming from the stack.
 //  Modify this setting if you need to have SoC events dispatched before or after other stack events, such as ANT or BLE.
 //  Zero is the highest priority.
@@ -11633,10 +11633,10 @@
 #define NRF_SDH_SOC_STACK_OBSERVER_PRIO 0
 #endif
 
-//  
+// 
 //==========================================================
 
-//  
+// 
 //==========================================================
 
 
@@ -11650,7 +11650,7 @@
 //  SoC Observers - Observers and priority levels
 
 //==========================================================
-//  NRF_SDH_SOC_OBSERVER_PRIO_LEVELS - Total number of priority levels for SoC observers. 
+//  NRF_SDH_SOC_OBSERVER_PRIO_LEVELS - Total number of priority levels for SoC observers.
 //  This setting configures the number of priority levels available for the SoC event handlers.
 //  The priority level of a handler determines the order in which it receives events, with respect to other handlers.
 
@@ -11661,31 +11661,31 @@
 //  SoC Observers priorities - Invididual priorities
 
 //==========================================================
-//  BLE_DFU_SOC_OBSERVER_PRIO  
+//  BLE_DFU_SOC_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the DFU Service.
 
 #ifndef BLE_DFU_SOC_OBSERVER_PRIO
 #define BLE_DFU_SOC_OBSERVER_PRIO 1
 #endif
 
-//  CLOCK_CONFIG_SOC_OBSERVER_PRIO  
+//  CLOCK_CONFIG_SOC_OBSERVER_PRIO
 //  Priority with which SoC events are dispatched to the Clock driver.
 
 #ifndef CLOCK_CONFIG_SOC_OBSERVER_PRIO
 #define CLOCK_CONFIG_SOC_OBSERVER_PRIO 0
 #endif
 
-//  POWER_CONFIG_SOC_OBSERVER_PRIO  
+//  POWER_CONFIG_SOC_OBSERVER_PRIO
 //  Priority with which SoC events are dispatched to the Power driver.
 
 #ifndef POWER_CONFIG_SOC_OBSERVER_PRIO
 #define POWER_CONFIG_SOC_OBSERVER_PRIO 0
 #endif
 
-//  
+// 
 //==========================================================
 
-//  
+// 
 //==========================================================
 
 //  NRFX_NVMC_ENABLED - nrfx_nvmc - NVMC peripheral driver
diff --git a/bsp/nrf5x/nrf52832/rtconfig.py b/bsp/nrf5x/nrf52832/rtconfig.py
index 219d20d303..e8a959bc85 100644
--- a/bsp/nrf5x/nrf52832/rtconfig.py
+++ b/bsp/nrf5x/nrf52832/rtconfig.py
@@ -54,7 +54,9 @@ if PLATFORM == 'gcc':
     else:
         CFLAGS += ' -O2'
 
-    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rt-thread.bin\n'
+    POST_ACTION += OBJCPY + ' -O ihex $TARGET rt-thread.hex\n'
+    POST_ACTION += SIZE + ' $TARGET \n'
 
 elif PLATFORM == 'armcc':
     # toolchains
@@ -82,3 +84,11 @@ elif PLATFORM == 'armcc':
         CFLAGS += ' -O2'
 
     POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+
+def dist_handle(BSP_ROOT, dist_dir):
+    import sys
+    cwd_path = os.getcwd()
+    sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+    from sdk_dist import dist_do_building
+    dist_do_building(BSP_ROOT, dist_dir)
diff --git a/bsp/nrf5x/nrf52840/applications/application.c b/bsp/nrf5x/nrf52840/applications/application.c
index 69def315c7..f2cae69ed1 100644
--- a/bsp/nrf5x/nrf52840/applications/application.c
+++ b/bsp/nrf5x/nrf52840/applications/application.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,16 +16,16 @@
 
 int main(void)
 {
-    int count = 1; 
+    int count = 1;
     rt_pin_mode(DK_BOARD_LED_1, PIN_MODE_OUTPUT);
-    
+
     while (count++)
-    {    
+    {
         rt_pin_write(DK_BOARD_LED_1, PIN_HIGH);
         rt_thread_mdelay(500);
-        
+
         rt_pin_write(DK_BOARD_LED_1, PIN_LOW);
-        rt_thread_mdelay(500);                    
+        rt_thread_mdelay(500);
     }
     return RT_EOK;
 }
diff --git a/bsp/nrf5x/nrf52840/board/app_config.h b/bsp/nrf5x/nrf52840/board/app_config.h
index 7909dd55b4..67db2eb886 100644
--- a/bsp/nrf5x/nrf52840/board/app_config.h
+++ b/bsp/nrf5x/nrf52840/board/app_config.h
@@ -1,4 +1,4 @@
 #ifndef APP_CONFIG_H
 #define APP_CONFIG_H
 
-#endif	//APP_CONFIG_H
+#endif  //APP_CONFIG_H
diff --git a/bsp/nrf5x/nrf52840/board/board.c b/bsp/nrf5x/nrf52840/board/board.c
index 5bd27ac8fc..2cb94fb6fa 100644
--- a/bsp/nrf5x/nrf52840/board/board.c
+++ b/bsp/nrf5x/nrf52840/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/nrf5x/nrf52840/board/fal_cfg.h b/bsp/nrf5x/nrf52840/board/fal_cfg.h
index 42611e0c13..27a1e8ecf4 100644
--- a/bsp/nrf5x/nrf52840/board/fal_cfg.h
+++ b/bsp/nrf5x/nrf52840/board/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/nrf5x/nrf52840/board/sdk_config.h b/bsp/nrf5x/nrf52840/board/sdk_config.h
index 8f6f5dc0d9..d62c024da3 100644
--- a/bsp/nrf5x/nrf52840/board/sdk_config.h
+++ b/bsp/nrf5x/nrf52840/board/sdk_config.h
@@ -46,26 +46,26 @@
 #ifdef USE_APP_CONFIG
 #include "app_config.h"
 #endif
-//  nRF_BLE 
+//  nRF_BLE
 
 #include 
 //==========================================================
 //  BLE_ADVERTISING_ENABLED  - ble_advertising - Advertising module
- 
+
 
 #ifndef BLE_ADVERTISING_ENABLED
 #define BLE_ADVERTISING_ENABLED 0
 #endif
 
 //  BLE_DTM_ENABLED  - ble_dtm - Module for testing RF/PHY using DTM commands
- 
+
 
 #ifndef BLE_DTM_ENABLED
 #define BLE_DTM_ENABLED 0
 #endif
 
 //  BLE_RACP_ENABLED  - ble_racp - Record Access Control Point library
- 
+
 
 #ifndef BLE_RACP_ENABLED
 #define BLE_RACP_ENABLED 0
@@ -76,7 +76,7 @@
 #ifndef NRF_BLE_QWR_ENABLED
 #define NRF_BLE_QWR_ENABLED 0
 #endif
-//  NRF_BLE_QWR_MAX_ATTR - Maximum number of attribute handles that can be registered. This number must be adjusted according to the number of attributes for which Queued Writes will be enabled. If it is zero, the module will reject all Queued Write requests. 
+//  NRF_BLE_QWR_MAX_ATTR - Maximum number of attribute handles that can be registered. This number must be adjusted according to the number of attributes for which Queued Writes will be enabled. If it is zero, the module will reject all Queued Write requests.
 #ifndef NRF_BLE_QWR_MAX_ATTR
 #define NRF_BLE_QWR_MAX_ATTR 0
 #endif
@@ -88,12 +88,12 @@
 #ifndef PEER_MANAGER_ENABLED
 #define PEER_MANAGER_ENABLED 0
 #endif
-//  PM_MAX_REGISTRANTS - Number of event handlers that can be registered. 
+//  PM_MAX_REGISTRANTS - Number of event handlers that can be registered.
 #ifndef PM_MAX_REGISTRANTS
 #define PM_MAX_REGISTRANTS 3
 #endif
 
-//  PM_FLASH_BUFFERS - Number of internal buffers for flash operations. 
+//  PM_FLASH_BUFFERS - Number of internal buffers for flash operations.
 //  Decrease this value to lower RAM usage.
 
 #ifndef PM_FLASH_BUFFERS
@@ -101,7 +101,7 @@
 #endif
 
 //  PM_CENTRAL_ENABLED  - Enable/disable central-specific Peer Manager functionality.
- 
+
 
 //  Enable/disable central-specific Peer Manager functionality.
 
@@ -110,7 +110,7 @@
 #endif
 
 //  PM_SERVICE_CHANGED_ENABLED  - Enable/disable the service changed management for GATT server in Peer Manager.
- 
+
 
 //  If not using a GATT server, or using a server wihout a service changed characteristic,
 //  disable this to save code space.
@@ -120,7 +120,7 @@
 #endif
 
 //  PM_PEER_RANKS_ENABLED  - Enable/disable the peer rank management in Peer Manager.
- 
+
 
 //  Set this to false to save code space if not using the peer rank API.
 
@@ -129,7 +129,7 @@
 #endif
 
 //  PM_LESC_ENABLED  - Enable/disable LESC support in Peer Manager.
- 
+
 
 //  If set to true, you need to call nrf_ble_lesc_request_handler() in the main loop to respond to LESC-related BLE events. If LESC support is not required, set this to false to save code space.
 
@@ -142,22 +142,22 @@
 #ifndef PM_RA_PROTECTION_ENABLED
 #define PM_RA_PROTECTION_ENABLED 0
 #endif
-//  PM_RA_PROTECTION_TRACKED_PEERS_NUM - Maximum number of peers whose authorization status can be tracked. 
+//  PM_RA_PROTECTION_TRACKED_PEERS_NUM - Maximum number of peers whose authorization status can be tracked.
 #ifndef PM_RA_PROTECTION_TRACKED_PEERS_NUM
 #define PM_RA_PROTECTION_TRACKED_PEERS_NUM 8
 #endif
 
-//  PM_RA_PROTECTION_MIN_WAIT_INTERVAL - Minimum waiting interval (in ms) before a new pairing attempt can be initiated. 
+//  PM_RA_PROTECTION_MIN_WAIT_INTERVAL - Minimum waiting interval (in ms) before a new pairing attempt can be initiated.
 #ifndef PM_RA_PROTECTION_MIN_WAIT_INTERVAL
 #define PM_RA_PROTECTION_MIN_WAIT_INTERVAL 4000
 #endif
 
-//  PM_RA_PROTECTION_MAX_WAIT_INTERVAL - Maximum waiting interval (in ms) before a new pairing attempt can be initiated. 
+//  PM_RA_PROTECTION_MAX_WAIT_INTERVAL - Maximum waiting interval (in ms) before a new pairing attempt can be initiated.
 #ifndef PM_RA_PROTECTION_MAX_WAIT_INTERVAL
 #define PM_RA_PROTECTION_MAX_WAIT_INTERVAL 64000
 #endif
 
-//  PM_RA_PROTECTION_REWARD_PERIOD - Reward period (in ms). 
+//  PM_RA_PROTECTION_REWARD_PERIOD - Reward period (in ms).
 //  The waiting interval is gradually decreased when no new failed pairing attempts are made during reward period.
 
 #ifndef PM_RA_PROTECTION_REWARD_PERIOD
@@ -166,7 +166,7 @@
 
 // 
 
-//  PM_HANDLER_SEC_DELAY_MS - Delay before starting security. 
+//  PM_HANDLER_SEC_DELAY_MS - Delay before starting security.
 //   This might be necessary for interoperability reasons, especially as peripheral.
 
 #ifndef PM_HANDLER_SEC_DELAY_MS
@@ -175,28 +175,28 @@
 
 // 
 
-//  
+// 
 //==========================================================
 
-//  nRF_BLE_Services 
+//  nRF_BLE_Services
 
 //==========================================================
 //  BLE_ANCS_C_ENABLED  - ble_ancs_c - Apple Notification Service Client
- 
+
 
 #ifndef BLE_ANCS_C_ENABLED
 #define BLE_ANCS_C_ENABLED 0
 #endif
 
 //  BLE_ANS_C_ENABLED  - ble_ans_c - Alert Notification Service Client
- 
+
 
 #ifndef BLE_ANS_C_ENABLED
 #define BLE_ANS_C_ENABLED 0
 #endif
 
 //  BLE_BAS_C_ENABLED  - ble_bas_c - Battery Service Client
- 
+
 
 #ifndef BLE_BAS_C_ENABLED
 #define BLE_BAS_C_ENABLED 0
@@ -213,44 +213,44 @@
 #define BLE_BAS_CONFIG_LOG_ENABLED 0
 #endif
 //  BLE_BAS_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef BLE_BAS_CONFIG_LOG_LEVEL
 #define BLE_BAS_CONFIG_LOG_LEVEL 3
 #endif
 
 //  BLE_BAS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef BLE_BAS_CONFIG_INFO_COLOR
 #define BLE_BAS_CONFIG_INFO_COLOR 0
 #endif
 
 //  BLE_BAS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef BLE_BAS_CONFIG_DEBUG_COLOR
 #define BLE_BAS_CONFIG_DEBUG_COLOR 0
@@ -261,63 +261,63 @@
 // 
 
 //  BLE_CSCS_ENABLED  - ble_cscs - Cycling Speed and Cadence Service
- 
+
 
 #ifndef BLE_CSCS_ENABLED
 #define BLE_CSCS_ENABLED 0
 #endif
 
 //  BLE_CTS_C_ENABLED  - ble_cts_c - Current Time Service Client
- 
+
 
 #ifndef BLE_CTS_C_ENABLED
 #define BLE_CTS_C_ENABLED 0
 #endif
 
 //  BLE_DIS_ENABLED  - ble_dis - Device Information Service
- 
+
 
 #ifndef BLE_DIS_ENABLED
 #define BLE_DIS_ENABLED 0
 #endif
 
 //  BLE_GLS_ENABLED  - ble_gls - Glucose Service
- 
+
 
 #ifndef BLE_GLS_ENABLED
 #define BLE_GLS_ENABLED 0
 #endif
 
 //  BLE_HIDS_ENABLED  - ble_hids - Human Interface Device Service
- 
+
 
 #ifndef BLE_HIDS_ENABLED
 #define BLE_HIDS_ENABLED 0
 #endif
 
 //  BLE_HRS_C_ENABLED  - ble_hrs_c - Heart Rate Service Client
- 
+
 
 #ifndef BLE_HRS_C_ENABLED
 #define BLE_HRS_C_ENABLED 0
 #endif
 
 //  BLE_HRS_ENABLED  - ble_hrs - Heart Rate Service
- 
+
 
 #ifndef BLE_HRS_ENABLED
 #define BLE_HRS_ENABLED 0
 #endif
 
 //  BLE_HTS_ENABLED  - ble_hts - Health Thermometer Service
- 
+
 
 #ifndef BLE_HTS_ENABLED
 #define BLE_HTS_ENABLED 0
 #endif
 
 //  BLE_IAS_C_ENABLED  - ble_ias_c - Immediate Alert Service Client
- 
+
 
 #ifndef BLE_IAS_C_ENABLED
 #define BLE_IAS_C_ENABLED 0
@@ -334,44 +334,44 @@
 #define BLE_IAS_CONFIG_LOG_ENABLED 0
 #endif
 //  BLE_IAS_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef BLE_IAS_CONFIG_LOG_LEVEL
 #define BLE_IAS_CONFIG_LOG_LEVEL 3
 #endif
 
 //  BLE_IAS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef BLE_IAS_CONFIG_INFO_COLOR
 #define BLE_IAS_CONFIG_INFO_COLOR 0
 #endif
 
 //  BLE_IAS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef BLE_IAS_CONFIG_DEBUG_COLOR
 #define BLE_IAS_CONFIG_DEBUG_COLOR 0
@@ -382,28 +382,28 @@
 // 
 
 //  BLE_LBS_C_ENABLED  - ble_lbs_c - Nordic LED Button Service Client
- 
+
 
 #ifndef BLE_LBS_C_ENABLED
 #define BLE_LBS_C_ENABLED 0
 #endif
 
 //  BLE_LBS_ENABLED  - ble_lbs - LED Button Service
- 
+
 
 #ifndef BLE_LBS_ENABLED
 #define BLE_LBS_ENABLED 0
 #endif
 
 //  BLE_LLS_ENABLED  - ble_lls - Link Loss Service
- 
+
 
 #ifndef BLE_LLS_ENABLED
 #define BLE_LLS_ENABLED 0
 #endif
 
 //  BLE_NUS_C_ENABLED  - ble_nus_c - Nordic UART Central Service
- 
+
 
 #ifndef BLE_NUS_C_ENABLED
 #define BLE_NUS_C_ENABLED 0
@@ -420,44 +420,44 @@
 #define BLE_NUS_CONFIG_LOG_ENABLED 0
 #endif
 //  BLE_NUS_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef BLE_NUS_CONFIG_LOG_LEVEL
 #define BLE_NUS_CONFIG_LOG_LEVEL 3
 #endif
 
 //  BLE_NUS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef BLE_NUS_CONFIG_INFO_COLOR
 #define BLE_NUS_CONFIG_INFO_COLOR 0
 #endif
 
 //  BLE_NUS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef BLE_NUS_CONFIG_DEBUG_COLOR
 #define BLE_NUS_CONFIG_DEBUG_COLOR 0
@@ -468,30 +468,30 @@
 // 
 
 //  BLE_RSCS_C_ENABLED  - ble_rscs_c - Running Speed and Cadence Client
- 
+
 
 #ifndef BLE_RSCS_C_ENABLED
 #define BLE_RSCS_C_ENABLED 0
 #endif
 
 //  BLE_RSCS_ENABLED  - ble_rscs - Running Speed and Cadence Service
- 
+
 
 #ifndef BLE_RSCS_ENABLED
 #define BLE_RSCS_ENABLED 0
 #endif
 
 //  BLE_TPS_ENABLED  - ble_tps - TX Power Service
- 
+
 
 #ifndef BLE_TPS_ENABLED
 #define BLE_TPS_ENABLED 0
 #endif
 
-//  
+// 
 //==========================================================
 
-//  nRF_Core 
+//  nRF_Core
 
 //==========================================================
 //  NRF_MPU_LIB_ENABLED - nrf_mpu_lib - Module for MPU
@@ -500,7 +500,7 @@
 #define NRF_MPU_LIB_ENABLED 0
 #endif
 //  NRF_MPU_LIB_CLI_CMDS  - Enable CLI commands specific to the module.
- 
+
 
 #ifndef NRF_MPU_LIB_CLI_CMDS
 #define NRF_MPU_LIB_CLI_CMDS 0
@@ -514,15 +514,15 @@
 #define NRF_STACK_GUARD_ENABLED 0
 #endif
 //  NRF_STACK_GUARD_CONFIG_SIZE  - Size of the stack guard.
- 
-// <5=> 32 bytes 
-// <6=> 64 bytes 
-// <7=> 128 bytes 
-// <8=> 256 bytes 
-// <9=> 512 bytes 
-// <10=> 1024 bytes 
-// <11=> 2048 bytes 
-// <12=> 4096 bytes 
+
+// <5=> 32 bytes
+// <6=> 64 bytes
+// <7=> 128 bytes
+// <8=> 256 bytes
+// <9=> 512 bytes
+// <10=> 1024 bytes
+// <11=> 2048 bytes
+// <12=> 4096 bytes
 
 #ifndef NRF_STACK_GUARD_CONFIG_SIZE
 #define NRF_STACK_GUARD_CONFIG_SIZE 7
@@ -530,10 +530,10 @@
 
 // 
 
-//  
+// 
 //==========================================================
 
-//  nRF_Crypto 
+//  nRF_Crypto
 
 //==========================================================
 //  NRF_CRYPTO_ENABLED - nrf_crypto - Cryptography library.
@@ -542,14 +542,14 @@
 #define NRF_CRYPTO_ENABLED 1
 #endif
 //  NRF_CRYPTO_ALLOCATOR  - Memory allocator
- 
+
 
 //  Choose memory allocator used by nrf_crypto. Default is alloca if possible or nrf_malloc otherwise. If 'User macros' are selected, the user has to create 'nrf_crypto_allocator.h' file that contains NRF_CRYPTO_ALLOC, NRF_CRYPTO_FREE, and NRF_CRYPTO_ALLOC_ON_STACK.
-// <0=> Default 
-// <1=> User macros 
-// <2=> On stack (alloca) 
-// <3=> C dynamic memory (malloc) 
-// <4=> SDK Memory Manager (nrf_malloc) 
+// <0=> Default
+// <1=> User macros
+// <2=> On stack (alloca)
+// <3=> C dynamic memory (malloc)
+// <4=> SDK Memory Manager (nrf_malloc)
 
 #ifndef NRF_CRYPTO_ALLOCATOR
 #define NRF_CRYPTO_ALLOCATOR 0
@@ -563,21 +563,21 @@
 #define NRF_CRYPTO_BACKEND_CC310_BL_ENABLED 0
 #endif
 //  NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP224R1_ENABLED  - Enable the secp224r1 elliptic curve support using CC310_BL.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP224R1_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP224R1_ENABLED 0
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP256R1_ENABLED  - Enable the secp256r1 elliptic curve support using CC310_BL.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP256R1_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP256R1_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_BL_HASH_SHA256_ENABLED  - CC310_BL SHA-256 hash functionality.
- 
+
 
 //  CC310_BL backend implementation for hardware-accelerated SHA-256.
 
@@ -586,7 +586,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_ENABLED  - nrf_cc310_bl buffers to RAM before running hash operation
- 
+
 
 //  Enabling this makes hashing of addresses in FLASH range possible. Size of buffer allocated for hashing is set by NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE
 
@@ -594,7 +594,7 @@
 #define NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_ENABLED 0
 #endif
 
-//  NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE - nrf_cc310_bl hash outputs digests in little endian 
+//  NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE - nrf_cc310_bl hash outputs digests in little endian
 //  Makes the nrf_cc310_bl hash functions output digests in little endian format. Only for use in nRF SDK DFU!
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE
@@ -602,7 +602,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_BL_INTERRUPTS_ENABLED  - Enable Interrupts while support using CC310 bl.
- 
+
 
 //  Select a library version compatible with the configuration. When interrupts are disable, a version named _noint must be used
 
@@ -620,154 +620,154 @@
 #define NRF_CRYPTO_BACKEND_CC310_ENABLED 0
 #endif
 //  NRF_CRYPTO_BACKEND_CC310_AES_CBC_ENABLED  - Enable the AES CBC mode using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_AES_CBC_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_AES_CBC_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_AES_CTR_ENABLED  - Enable the AES CTR mode using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_AES_CTR_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_AES_CTR_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_AES_ECB_ENABLED  - Enable the AES ECB mode using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_AES_ECB_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_AES_ECB_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_AES_CBC_MAC_ENABLED  - Enable the AES CBC_MAC mode using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_AES_CBC_MAC_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_AES_CBC_MAC_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_AES_CMAC_ENABLED  - Enable the AES CMAC mode using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_AES_CMAC_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_AES_CMAC_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_AES_CCM_ENABLED  - Enable the AES CCM mode using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_AES_CCM_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_AES_CCM_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_AES_CCM_STAR_ENABLED  - Enable the AES CCM* mode using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_AES_CCM_STAR_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_AES_CCM_STAR_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_CHACHA_POLY_ENABLED  - Enable the CHACHA-POLY mode using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_CHACHA_POLY_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_CHACHA_POLY_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R1_ENABLED  - Enable the secp160r1 elliptic curve support using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R1_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R1_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R2_ENABLED  - Enable the secp160r2 elliptic curve support using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R2_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R2_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_ECC_SECP192R1_ENABLED  - Enable the secp192r1 elliptic curve support using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP192R1_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_ECC_SECP192R1_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_ECC_SECP224R1_ENABLED  - Enable the secp224r1 elliptic curve support using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP224R1_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_ECC_SECP224R1_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_ECC_SECP256R1_ENABLED  - Enable the secp256r1 elliptic curve support using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP256R1_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_ECC_SECP256R1_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_ECC_SECP384R1_ENABLED  - Enable the secp384r1 elliptic curve support using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP384R1_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_ECC_SECP384R1_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_ECC_SECP521R1_ENABLED  - Enable the secp521r1 elliptic curve support using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP521R1_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_ECC_SECP521R1_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_ECC_SECP160K1_ENABLED  - Enable the secp160k1 elliptic curve support using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP160K1_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160K1_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_ECC_SECP192K1_ENABLED  - Enable the secp192k1 elliptic curve support using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP192K1_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_ECC_SECP192K1_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_ECC_SECP224K1_ENABLED  - Enable the secp224k1 elliptic curve support using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP224K1_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_ECC_SECP224K1_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_ECC_SECP256K1_ENABLED  - Enable the secp256k1 elliptic curve support using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP256K1_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_ECC_SECP256K1_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_ECC_CURVE25519_ENABLED  - Enable the Curve25519 curve support using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_ECC_CURVE25519_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_ECC_CURVE25519_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_ECC_ED25519_ENABLED  - Enable the Ed25519 curve support using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_ECC_ED25519_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_ECC_ED25519_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_HASH_SHA256_ENABLED  - CC310 SHA-256 hash functionality.
- 
+
 
 //  CC310 backend implementation for hardware-accelerated SHA-256.
 
@@ -776,7 +776,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_HASH_SHA512_ENABLED  - CC310 SHA-512 hash functionality
- 
+
 
 //  CC310 backend implementation for SHA-512 (in software).
 
@@ -785,7 +785,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_HMAC_SHA256_ENABLED  - CC310 HMAC using SHA-256
- 
+
 
 //  CC310 backend implementation for HMAC using hardware-accelerated SHA-256.
 
@@ -794,7 +794,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_HMAC_SHA512_ENABLED  - CC310 HMAC using SHA-512
- 
+
 
 //  CC310 backend implementation for HMAC using SHA-512 (in software).
 
@@ -803,14 +803,14 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_RNG_ENABLED  - Enable RNG support using CC310.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CC310_RNG_ENABLED
 #define NRF_CRYPTO_BACKEND_CC310_RNG_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_CC310_INTERRUPTS_ENABLED  - Enable Interrupts while support using CC310.
- 
+
 
 //  Select a library version compatible with the configuration. When interrupts are disable, a version named _noint must be used
 
@@ -826,7 +826,7 @@
 #define NRF_CRYPTO_BACKEND_CIFRA_ENABLED 0
 #endif
 //  NRF_CRYPTO_BACKEND_CIFRA_AES_EAX_ENABLED  - Enable the AES EAX mode using Cifra.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_CIFRA_AES_EAX_ENABLED
 #define NRF_CRYPTO_BACKEND_CIFRA_AES_EAX_ENABLED 1
@@ -840,63 +840,63 @@
 #define NRF_CRYPTO_BACKEND_MBEDTLS_ENABLED 0
 #endif
 //  NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_ENABLED  - Enable the AES CBC mode mbed TLS.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_ENABLED
 #define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_AES_CTR_ENABLED  - Enable the AES CTR mode using mbed TLS.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CTR_ENABLED
 #define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CTR_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_AES_CFB_ENABLED  - Enable the AES CFB mode using mbed TLS.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CFB_ENABLED
 #define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CFB_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_AES_ECB_ENABLED  - Enable the AES ECB mode using mbed TLS.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_ECB_ENABLED
 #define NRF_CRYPTO_BACKEND_MBEDTLS_AES_ECB_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_MAC_ENABLED  - Enable the AES CBC MAC mode using mbed TLS.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_MAC_ENABLED
 #define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_MAC_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_AES_CMAC_ENABLED  - Enable the AES CMAC mode using mbed TLS.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CMAC_ENABLED
 #define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CMAC_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_AES_CCM_ENABLED  - Enable the AES CCM mode using mbed TLS.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CCM_ENABLED
 #define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CCM_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_AES_GCM_ENABLED  - Enable the AES GCM mode using mbed TLS.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_GCM_ENABLED
 #define NRF_CRYPTO_BACKEND_MBEDTLS_AES_GCM_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192R1_ENABLED  - Enable secp192r1 (NIST 192-bit) curve
- 
+
 
 //  Enable this setting if you need secp192r1 (NIST 192-bit) support using MBEDTLS
 
@@ -905,7 +905,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224R1_ENABLED  - Enable secp224r1 (NIST 224-bit) curve
- 
+
 
 //  Enable this setting if you need secp224r1 (NIST 224-bit) support using MBEDTLS
 
@@ -914,7 +914,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256R1_ENABLED  - Enable secp256r1 (NIST 256-bit) curve
- 
+
 
 //  Enable this setting if you need secp256r1 (NIST 256-bit) support using MBEDTLS
 
@@ -923,7 +923,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP384R1_ENABLED  - Enable secp384r1 (NIST 384-bit) curve
- 
+
 
 //  Enable this setting if you need secp384r1 (NIST 384-bit) support using MBEDTLS
 
@@ -932,7 +932,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP521R1_ENABLED  - Enable secp521r1 (NIST 521-bit) curve
- 
+
 
 //  Enable this setting if you need secp521r1 (NIST 521-bit) support using MBEDTLS
 
@@ -941,7 +941,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192K1_ENABLED  - Enable secp192k1 (Koblitz 192-bit) curve
- 
+
 
 //  Enable this setting if you need secp192k1 (Koblitz 192-bit) support using MBEDTLS
 
@@ -950,7 +950,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224K1_ENABLED  - Enable secp224k1 (Koblitz 224-bit) curve
- 
+
 
 //  Enable this setting if you need secp224k1 (Koblitz 224-bit) support using MBEDTLS
 
@@ -959,7 +959,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256K1_ENABLED  - Enable secp256k1 (Koblitz 256-bit) curve
- 
+
 
 //  Enable this setting if you need secp256k1 (Koblitz 256-bit) support using MBEDTLS
 
@@ -968,7 +968,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP256R1_ENABLED  - Enable bp256r1 (Brainpool 256-bit) curve
- 
+
 
 //  Enable this setting if you need bp256r1 (Brainpool 256-bit) support using MBEDTLS
 
@@ -977,7 +977,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP384R1_ENABLED  - Enable bp384r1 (Brainpool 384-bit) curve
- 
+
 
 //  Enable this setting if you need bp384r1 (Brainpool 384-bit) support using MBEDTLS
 
@@ -986,7 +986,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP512R1_ENABLED  - Enable bp512r1 (Brainpool 512-bit) curve
- 
+
 
 //  Enable this setting if you need bp512r1 (Brainpool 512-bit) support using MBEDTLS
 
@@ -995,7 +995,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_ECC_CURVE25519_ENABLED  - Enable Curve25519 curve
- 
+
 
 //  Enable this setting if you need Curve25519 support using MBEDTLS
 
@@ -1004,7 +1004,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA256_ENABLED  - Enable mbed TLS SHA-256 hash functionality.
- 
+
 
 //  mbed TLS backend implementation for SHA-256.
 
@@ -1013,7 +1013,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA512_ENABLED  - Enable mbed TLS SHA-512 hash functionality.
- 
+
 
 //  mbed TLS backend implementation for SHA-512.
 
@@ -1022,7 +1022,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA256_ENABLED  - Enable mbed TLS HMAC using SHA-256.
- 
+
 
 //  mbed TLS backend implementation for HMAC using SHA-256.
 
@@ -1031,7 +1031,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA512_ENABLED  - Enable mbed TLS HMAC using SHA-512.
- 
+
 
 //  mbed TLS backend implementation for HMAC using SHA-512.
 
@@ -1047,7 +1047,7 @@
 #define NRF_CRYPTO_BACKEND_MICRO_ECC_ENABLED 0
 #endif
 //  NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP192R1_ENABLED  - Enable secp192r1 (NIST 192-bit) curve
- 
+
 
 //  Enable this setting if you need secp192r1 (NIST 192-bit) support using micro-ecc
 
@@ -1056,7 +1056,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP224R1_ENABLED  - Enable secp224r1 (NIST 224-bit) curve
- 
+
 
 //  Enable this setting if you need secp224r1 (NIST 224-bit) support using micro-ecc
 
@@ -1065,7 +1065,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256R1_ENABLED  - Enable secp256r1 (NIST 256-bit) curve
- 
+
 
 //  Enable this setting if you need secp256r1 (NIST 256-bit) support using micro-ecc
 
@@ -1074,7 +1074,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256K1_ENABLED  - Enable secp256k1 (Koblitz 256-bit) curve
- 
+
 
 //  Enable this setting if you need secp256k1 (Koblitz 256-bit) support using micro-ecc
 
@@ -1092,7 +1092,7 @@
 #define NRF_CRYPTO_BACKEND_NRF_HW_RNG_ENABLED 0
 #endif
 //  NRF_CRYPTO_BACKEND_NRF_HW_RNG_MBEDTLS_CTR_DRBG_ENABLED  - Enable mbed TLS CTR-DRBG algorithm.
- 
+
 
 //  Enable mbed TLS CTR-DRBG standardized by NIST (NIST SP 800-90A Rev. 1). The nRF HW RNG is used as an entropy source for seeding.
 
@@ -1110,7 +1110,7 @@
 #define NRF_CRYPTO_BACKEND_NRF_SW_ENABLED 0
 #endif
 //  NRF_CRYPTO_BACKEND_NRF_SW_HASH_SHA256_ENABLED  - nRF SW hash backend support for SHA-256
- 
+
 
 //  The nRF SW backend provide access to nRF SDK legacy hash implementation of SHA-256.
 
@@ -1128,14 +1128,14 @@
 #define NRF_CRYPTO_BACKEND_OBERON_ENABLED 0
 #endif
 //  NRF_CRYPTO_BACKEND_OBERON_CHACHA_POLY_ENABLED  - Enable the CHACHA-POLY mode using Oberon.
- 
+
 
 #ifndef NRF_CRYPTO_BACKEND_OBERON_CHACHA_POLY_ENABLED
 #define NRF_CRYPTO_BACKEND_OBERON_CHACHA_POLY_ENABLED 1
 #endif
 
 //  NRF_CRYPTO_BACKEND_OBERON_ECC_SECP256R1_ENABLED  - Enable secp256r1 curve
- 
+
 
 //  Enable this setting if you need secp256r1 curve support using Oberon library
 
@@ -1144,7 +1144,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_OBERON_ECC_CURVE25519_ENABLED  - Enable Curve25519 ECDH
- 
+
 
 //  Enable this setting if you need Curve25519 ECDH support using Oberon library
 
@@ -1153,7 +1153,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_OBERON_ECC_ED25519_ENABLED  - Enable Ed25519 signature scheme
- 
+
 
 //  Enable this setting if you need Ed25519 support using Oberon library
 
@@ -1162,7 +1162,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_OBERON_HASH_SHA256_ENABLED  - Oberon SHA-256 hash functionality
- 
+
 
 //  Oberon backend implementation for SHA-256.
 
@@ -1171,7 +1171,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_OBERON_HASH_SHA512_ENABLED  - Oberon SHA-512 hash functionality
- 
+
 
 //  Oberon backend implementation for SHA-512.
 
@@ -1180,7 +1180,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA256_ENABLED  - Oberon HMAC using SHA-256
- 
+
 
 //  Oberon backend implementation for HMAC using SHA-256.
 
@@ -1189,7 +1189,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA512_ENABLED  - Oberon HMAC using SHA-512
- 
+
 
 //  Oberon backend implementation for HMAC using SHA-512.
 
@@ -1207,7 +1207,7 @@
 #define NRF_CRYPTO_BACKEND_OPTIGA_ENABLED 0
 #endif
 //  NRF_CRYPTO_BACKEND_OPTIGA_RNG_ENABLED  - Optiga backend support for RNG
- 
+
 
 //  The Optiga backend provide external chip RNG.
 
@@ -1216,7 +1216,7 @@
 #endif
 
 //  NRF_CRYPTO_BACKEND_OPTIGA_ECC_SECP256R1_ENABLED  - Optiga backend support for ECC secp256r1
- 
+
 
 //  The Optiga backend provide external chip ECC using secp256r1.
 
@@ -1227,7 +1227,7 @@
 // 
 
 //  NRF_CRYPTO_CURVE25519_BIG_ENDIAN_ENABLED  - Big-endian byte order in raw Curve25519 data
- 
+
 
 //  Enable big-endian byte order in Curve25519 API, if set to 1. Use little-endian, if set to 0.
 
@@ -1237,36 +1237,36 @@
 
 // 
 
-//  
+// 
 //==========================================================
 
-//  nRF_DFU 
+//  nRF_DFU
 
 //==========================================================
 //  ble_dfu - Device Firmware Update
 
 //==========================================================
 //  BLE_DFU_ENABLED  - Enable DFU Service.
- 
+
 
 #ifndef BLE_DFU_ENABLED
 #define BLE_DFU_ENABLED 0
 #endif
 
 //  NRF_DFU_BLE_BUTTONLESS_SUPPORTS_BONDS  - Buttonless DFU supports bonds.
- 
+
 
 #ifndef NRF_DFU_BLE_BUTTONLESS_SUPPORTS_BONDS
 #define NRF_DFU_BLE_BUTTONLESS_SUPPORTS_BONDS 0
 #endif
 
-//  
+// 
 //==========================================================
 
-//  
+// 
 //==========================================================
 
-//  nRF_Drivers 
+//  nRF_Drivers
 
 //==========================================================
 //  COMP_ENABLED - nrf_drv_comp - COMP peripheral driver - legacy layer
@@ -1275,83 +1275,83 @@
 #define COMP_ENABLED 0
 #endif
 //  COMP_CONFIG_REF  - Reference voltage
- 
-// <0=> Internal 1.2V 
-// <1=> Internal 1.8V 
-// <2=> Internal 2.4V 
-// <4=> VDD 
-// <7=> ARef 
+
+// <0=> Internal 1.2V
+// <1=> Internal 1.8V
+// <2=> Internal 2.4V
+// <4=> VDD
+// <7=> ARef
 
 #ifndef COMP_CONFIG_REF
 #define COMP_CONFIG_REF 1
 #endif
 
 //  COMP_CONFIG_MAIN_MODE  - Main mode
- 
-// <0=> Single ended 
-// <1=> Differential 
+
+// <0=> Single ended
+// <1=> Differential
 
 #ifndef COMP_CONFIG_MAIN_MODE
 #define COMP_CONFIG_MAIN_MODE 0
 #endif
 
 //  COMP_CONFIG_SPEED_MODE  - Speed mode
- 
-// <0=> Low power 
-// <1=> Normal 
-// <2=> High speed 
+
+// <0=> Low power
+// <1=> Normal
+// <2=> High speed
 
 #ifndef COMP_CONFIG_SPEED_MODE
 #define COMP_CONFIG_SPEED_MODE 2
 #endif
 
 //  COMP_CONFIG_HYST  - Hystheresis
- 
-// <0=> No 
-// <1=> 50mV 
+
+// <0=> No
+// <1=> 50mV
 
 #ifndef COMP_CONFIG_HYST
 #define COMP_CONFIG_HYST 0
 #endif
 
 //  COMP_CONFIG_ISOURCE  - Current Source
- 
-// <0=> Off 
-// <1=> 2.5 uA 
-// <2=> 5 uA 
-// <3=> 10 uA 
+
+// <0=> Off
+// <1=> 2.5 uA
+// <2=> 5 uA
+// <3=> 10 uA
 
 #ifndef COMP_CONFIG_ISOURCE
 #define COMP_CONFIG_ISOURCE 0
 #endif
 
 //  COMP_CONFIG_INPUT  - Analog input
- 
-// <0=> 0 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef COMP_CONFIG_INPUT
 #define COMP_CONFIG_INPUT 0
 #endif
 
 //  COMP_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef COMP_CONFIG_IRQ_PRIORITY
 #define COMP_CONFIG_IRQ_PRIORITY 6
@@ -1360,7 +1360,7 @@
 // 
 
 //  EGU_ENABLED  - nrf_drv_swi - SWI(EGU) peripheral driver - legacy layer
- 
+
 
 #ifndef EGU_ENABLED
 #define EGU_ENABLED 0
@@ -1371,23 +1371,23 @@
 #ifndef GPIOTE_ENABLED
 #define GPIOTE_ENABLED 0
 #endif
-//  GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins 
+//  GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins
 #ifndef GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS
 #define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1
 #endif
 
 //  GPIOTE_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef GPIOTE_CONFIG_IRQ_PRIORITY
 #define GPIOTE_CONFIG_IRQ_PRIORITY 6
@@ -1400,33 +1400,33 @@
 #ifndef I2S_ENABLED
 #define I2S_ENABLED 0
 #endif
-//  I2S_CONFIG_SCK_PIN - SCK pin  <0-31> 
+//  I2S_CONFIG_SCK_PIN - SCK pin  <0-31>
 
 
 #ifndef I2S_CONFIG_SCK_PIN
 #define I2S_CONFIG_SCK_PIN 31
 #endif
 
-//  I2S_CONFIG_LRCK_PIN - LRCK pin  <1-31> 
+//  I2S_CONFIG_LRCK_PIN - LRCK pin  <1-31>
 
 
 #ifndef I2S_CONFIG_LRCK_PIN
 #define I2S_CONFIG_LRCK_PIN 30
 #endif
 
-//  I2S_CONFIG_MCK_PIN - MCK pin 
+//  I2S_CONFIG_MCK_PIN - MCK pin
 #ifndef I2S_CONFIG_MCK_PIN
 #define I2S_CONFIG_MCK_PIN 255
 #endif
 
-//  I2S_CONFIG_SDOUT_PIN - SDOUT pin  <0-31> 
+//  I2S_CONFIG_SDOUT_PIN - SDOUT pin  <0-31>
 
 
 #ifndef I2S_CONFIG_SDOUT_PIN
 #define I2S_CONFIG_SDOUT_PIN 29
 #endif
 
-//  I2S_CONFIG_SDIN_PIN - SDIN pin  <0-31> 
+//  I2S_CONFIG_SDIN_PIN - SDIN pin  <0-31>
 
 
 #ifndef I2S_CONFIG_SDIN_PIN
@@ -1434,106 +1434,106 @@
 #endif
 
 //  I2S_CONFIG_MASTER  - Mode
- 
-// <0=> Master 
-// <1=> Slave 
+
+// <0=> Master
+// <1=> Slave
 
 #ifndef I2S_CONFIG_MASTER
 #define I2S_CONFIG_MASTER 0
 #endif
 
 //  I2S_CONFIG_FORMAT  - Format
- 
-// <0=> I2S 
-// <1=> Aligned 
+
+// <0=> I2S
+// <1=> Aligned
 
 #ifndef I2S_CONFIG_FORMAT
 #define I2S_CONFIG_FORMAT 0
 #endif
 
 //  I2S_CONFIG_ALIGN  - Alignment
- 
-// <0=> Left 
-// <1=> Right 
+
+// <0=> Left
+// <1=> Right
 
 #ifndef I2S_CONFIG_ALIGN
 #define I2S_CONFIG_ALIGN 0
 #endif
 
 //  I2S_CONFIG_SWIDTH  - Sample width (bits)
- 
-// <0=> 8 
-// <1=> 16 
-// <2=> 24 
+
+// <0=> 8
+// <1=> 16
+// <2=> 24
 
 #ifndef I2S_CONFIG_SWIDTH
 #define I2S_CONFIG_SWIDTH 1
 #endif
 
 //  I2S_CONFIG_CHANNELS  - Channels
- 
-// <0=> Stereo 
-// <1=> Left 
-// <2=> Right 
+
+// <0=> Stereo
+// <1=> Left
+// <2=> Right
 
 #ifndef I2S_CONFIG_CHANNELS
 #define I2S_CONFIG_CHANNELS 1
 #endif
 
 //  I2S_CONFIG_MCK_SETUP  - MCK behavior
- 
-// <0=> Disabled 
-// <2147483648=> 32MHz/2 
-// <1342177280=> 32MHz/3 
-// <1073741824=> 32MHz/4 
-// <805306368=> 32MHz/5 
-// <671088640=> 32MHz/6 
-// <536870912=> 32MHz/8 
-// <402653184=> 32MHz/10 
-// <369098752=> 32MHz/11 
-// <285212672=> 32MHz/15 
-// <268435456=> 32MHz/16 
-// <201326592=> 32MHz/21 
-// <184549376=> 32MHz/23 
-// <142606336=> 32MHz/30 
-// <138412032=> 32MHz/31 
-// <134217728=> 32MHz/32 
-// <100663296=> 32MHz/42 
-// <68157440=> 32MHz/63 
-// <34340864=> 32MHz/125 
+
+// <0=> Disabled
+// <2147483648=> 32MHz/2
+// <1342177280=> 32MHz/3
+// <1073741824=> 32MHz/4
+// <805306368=> 32MHz/5
+// <671088640=> 32MHz/6
+// <536870912=> 32MHz/8
+// <402653184=> 32MHz/10
+// <369098752=> 32MHz/11
+// <285212672=> 32MHz/15
+// <268435456=> 32MHz/16
+// <201326592=> 32MHz/21
+// <184549376=> 32MHz/23
+// <142606336=> 32MHz/30
+// <138412032=> 32MHz/31
+// <134217728=> 32MHz/32
+// <100663296=> 32MHz/42
+// <68157440=> 32MHz/63
+// <34340864=> 32MHz/125
 
 #ifndef I2S_CONFIG_MCK_SETUP
 #define I2S_CONFIG_MCK_SETUP 536870912
 #endif
 
 //  I2S_CONFIG_RATIO  - MCK/LRCK ratio
- 
-// <0=> 32x 
-// <1=> 48x 
-// <2=> 64x 
-// <3=> 96x 
-// <4=> 128x 
-// <5=> 192x 
-// <6=> 256x 
-// <7=> 384x 
-// <8=> 512x 
+
+// <0=> 32x
+// <1=> 48x
+// <2=> 64x
+// <3=> 96x
+// <4=> 128x
+// <5=> 192x
+// <6=> 256x
+// <7=> 384x
+// <8=> 512x
 
 #ifndef I2S_CONFIG_RATIO
 #define I2S_CONFIG_RATIO 2000
 #endif
 
 //  I2S_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef I2S_CONFIG_IRQ_PRIORITY
 #define I2S_CONFIG_IRQ_PRIORITY 6
@@ -1545,44 +1545,44 @@
 #define I2S_CONFIG_LOG_ENABLED 0
 #endif
 //  I2S_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef I2S_CONFIG_LOG_LEVEL
 #define I2S_CONFIG_LOG_LEVEL 3
 #endif
 
 //  I2S_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef I2S_CONFIG_INFO_COLOR
 #define I2S_CONFIG_INFO_COLOR 0
 #endif
 
 //  I2S_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef I2S_CONFIG_DEBUG_COLOR
 #define I2S_CONFIG_DEBUG_COLOR 0
@@ -1598,73 +1598,73 @@
 #define LPCOMP_ENABLED 0
 #endif
 //  LPCOMP_CONFIG_REFERENCE  - Reference voltage
- 
-// <0=> Supply 1/8 
-// <1=> Supply 2/8 
-// <2=> Supply 3/8 
-// <3=> Supply 4/8 
-// <4=> Supply 5/8 
-// <5=> Supply 6/8 
-// <6=> Supply 7/8 
-// <8=> Supply 1/16 (nRF52) 
-// <9=> Supply 3/16 (nRF52) 
-// <10=> Supply 5/16 (nRF52) 
-// <11=> Supply 7/16 (nRF52) 
-// <12=> Supply 9/16 (nRF52) 
-// <13=> Supply 11/16 (nRF52) 
-// <14=> Supply 13/16 (nRF52) 
-// <15=> Supply 15/16 (nRF52) 
-// <7=> External Ref 0 
-// <65543=> External Ref 1 
+
+// <0=> Supply 1/8
+// <1=> Supply 2/8
+// <2=> Supply 3/8
+// <3=> Supply 4/8
+// <4=> Supply 5/8
+// <5=> Supply 6/8
+// <6=> Supply 7/8
+// <8=> Supply 1/16 (nRF52)
+// <9=> Supply 3/16 (nRF52)
+// <10=> Supply 5/16 (nRF52)
+// <11=> Supply 7/16 (nRF52)
+// <12=> Supply 9/16 (nRF52)
+// <13=> Supply 11/16 (nRF52)
+// <14=> Supply 13/16 (nRF52)
+// <15=> Supply 15/16 (nRF52)
+// <7=> External Ref 0
+// <65543=> External Ref 1
 
 #ifndef LPCOMP_CONFIG_REFERENCE
 #define LPCOMP_CONFIG_REFERENCE 3
 #endif
 
 //  LPCOMP_CONFIG_DETECTION  - Detection
- 
-// <0=> Crossing 
-// <1=> Up 
-// <2=> Down 
+
+// <0=> Crossing
+// <1=> Up
+// <2=> Down
 
 #ifndef LPCOMP_CONFIG_DETECTION
 #define LPCOMP_CONFIG_DETECTION 2
 #endif
 
 //  LPCOMP_CONFIG_INPUT  - Analog input
- 
-// <0=> 0 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef LPCOMP_CONFIG_INPUT
 #define LPCOMP_CONFIG_INPUT 0
 #endif
 
 //  LPCOMP_CONFIG_HYST  - Hysteresis
- 
+
 
 #ifndef LPCOMP_CONFIG_HYST
 #define LPCOMP_CONFIG_HYST 0
 #endif
 
 //  LPCOMP_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef LPCOMP_CONFIG_IRQ_PRIORITY
 #define LPCOMP_CONFIG_IRQ_PRIORITY 6
@@ -1678,27 +1678,27 @@
 #define NRFX_CLOCK_ENABLED 0
 #endif
 //  NRFX_CLOCK_CONFIG_LF_SRC  - LF Clock Source
- 
-// <0=> RC 
-// <1=> XTAL 
-// <2=> Synth 
-// <131073=> External Low Swing 
-// <196609=> External Full Swing 
+
+// <0=> RC
+// <1=> XTAL
+// <2=> Synth
+// <131073=> External Low Swing
+// <196609=> External Full Swing
 
 #ifndef NRFX_CLOCK_CONFIG_LF_SRC
 #define NRFX_CLOCK_CONFIG_LF_SRC 1
 #endif
 
 //  NRFX_CLOCK_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_CLOCK_CONFIG_IRQ_PRIORITY
 #define NRFX_CLOCK_CONFIG_IRQ_PRIORITY 6
@@ -1710,44 +1710,44 @@
 #define NRFX_CLOCK_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_CLOCK_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_CLOCK_CONFIG_LOG_LEVEL
 #define NRFX_CLOCK_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_CLOCK_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_CLOCK_CONFIG_INFO_COLOR
 #define NRFX_CLOCK_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_CLOCK_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_CLOCK_CONFIG_DEBUG_COLOR
 #define NRFX_CLOCK_CONFIG_DEBUG_COLOR 0
@@ -1763,81 +1763,81 @@
 #define NRFX_COMP_ENABLED 0
 #endif
 //  NRFX_COMP_CONFIG_REF  - Reference voltage
- 
-// <0=> Internal 1.2V 
-// <1=> Internal 1.8V 
-// <2=> Internal 2.4V 
-// <4=> VDD 
-// <7=> ARef 
+
+// <0=> Internal 1.2V
+// <1=> Internal 1.8V
+// <2=> Internal 2.4V
+// <4=> VDD
+// <7=> ARef
 
 #ifndef NRFX_COMP_CONFIG_REF
 #define NRFX_COMP_CONFIG_REF 1
 #endif
 
 //  NRFX_COMP_CONFIG_MAIN_MODE  - Main mode
- 
-// <0=> Single ended 
-// <1=> Differential 
+
+// <0=> Single ended
+// <1=> Differential
 
 #ifndef NRFX_COMP_CONFIG_MAIN_MODE
 #define NRFX_COMP_CONFIG_MAIN_MODE 0
 #endif
 
 //  NRFX_COMP_CONFIG_SPEED_MODE  - Speed mode
- 
-// <0=> Low power 
-// <1=> Normal 
-// <2=> High speed 
+
+// <0=> Low power
+// <1=> Normal
+// <2=> High speed
 
 #ifndef NRFX_COMP_CONFIG_SPEED_MODE
 #define NRFX_COMP_CONFIG_SPEED_MODE 2
 #endif
 
 //  NRFX_COMP_CONFIG_HYST  - Hystheresis
- 
-// <0=> No 
-// <1=> 50mV 
+
+// <0=> No
+// <1=> 50mV
 
 #ifndef NRFX_COMP_CONFIG_HYST
 #define NRFX_COMP_CONFIG_HYST 0
 #endif
 
 //  NRFX_COMP_CONFIG_ISOURCE  - Current Source
- 
-// <0=> Off 
-// <1=> 2.5 uA 
-// <2=> 5 uA 
-// <3=> 10 uA 
+
+// <0=> Off
+// <1=> 2.5 uA
+// <2=> 5 uA
+// <3=> 10 uA
 
 #ifndef NRFX_COMP_CONFIG_ISOURCE
 #define NRFX_COMP_CONFIG_ISOURCE 0
 #endif
 
 //  NRFX_COMP_CONFIG_INPUT  - Analog input
- 
-// <0=> 0 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_COMP_CONFIG_INPUT
 #define NRFX_COMP_CONFIG_INPUT 0
 #endif
 
 //  NRFX_COMP_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_COMP_CONFIG_IRQ_PRIORITY
 #define NRFX_COMP_CONFIG_IRQ_PRIORITY 6
@@ -1849,44 +1849,44 @@
 #define NRFX_COMP_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_COMP_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_COMP_CONFIG_LOG_LEVEL
 #define NRFX_COMP_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_COMP_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_COMP_CONFIG_INFO_COLOR
 #define NRFX_COMP_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_COMP_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_COMP_CONFIG_DEBUG_COLOR
 #define NRFX_COMP_CONFIG_DEBUG_COLOR 0
@@ -1901,21 +1901,21 @@
 #ifndef NRFX_GPIOTE_ENABLED
 #define NRFX_GPIOTE_ENABLED 0
 #endif
-//  NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins 
+//  NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins
 #ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS
 #define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1
 #endif
 
 //  NRFX_GPIOTE_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_GPIOTE_CONFIG_IRQ_PRIORITY
 #define NRFX_GPIOTE_CONFIG_IRQ_PRIORITY 6
@@ -1927,44 +1927,44 @@
 #define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_GPIOTE_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL
 #define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_GPIOTE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_GPIOTE_CONFIG_INFO_COLOR
 #define NRFX_GPIOTE_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_GPIOTE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_GPIOTE_CONFIG_DEBUG_COLOR
 #define NRFX_GPIOTE_CONFIG_DEBUG_COLOR 0
@@ -1979,33 +1979,33 @@
 #ifndef NRFX_I2S_ENABLED
 #define NRFX_I2S_ENABLED 0
 #endif
-//  NRFX_I2S_CONFIG_SCK_PIN - SCK pin  <0-31> 
+//  NRFX_I2S_CONFIG_SCK_PIN - SCK pin  <0-31>
 
 
 #ifndef NRFX_I2S_CONFIG_SCK_PIN
 #define NRFX_I2S_CONFIG_SCK_PIN 31
 #endif
 
-//  NRFX_I2S_CONFIG_LRCK_PIN - LRCK pin  <1-31> 
+//  NRFX_I2S_CONFIG_LRCK_PIN - LRCK pin  <1-31>
 
 
 #ifndef NRFX_I2S_CONFIG_LRCK_PIN
 #define NRFX_I2S_CONFIG_LRCK_PIN 30
 #endif
 
-//  NRFX_I2S_CONFIG_MCK_PIN - MCK pin 
+//  NRFX_I2S_CONFIG_MCK_PIN - MCK pin
 #ifndef NRFX_I2S_CONFIG_MCK_PIN
 #define NRFX_I2S_CONFIG_MCK_PIN 255
 #endif
 
-//  NRFX_I2S_CONFIG_SDOUT_PIN - SDOUT pin  <0-31> 
+//  NRFX_I2S_CONFIG_SDOUT_PIN - SDOUT pin  <0-31>
 
 
 #ifndef NRFX_I2S_CONFIG_SDOUT_PIN
 #define NRFX_I2S_CONFIG_SDOUT_PIN 29
 #endif
 
-//  NRFX_I2S_CONFIG_SDIN_PIN - SDIN pin  <0-31> 
+//  NRFX_I2S_CONFIG_SDIN_PIN - SDIN pin  <0-31>
 
 
 #ifndef NRFX_I2S_CONFIG_SDIN_PIN
@@ -2013,104 +2013,104 @@
 #endif
 
 //  NRFX_I2S_CONFIG_MASTER  - Mode
- 
-// <0=> Master 
-// <1=> Slave 
+
+// <0=> Master
+// <1=> Slave
 
 #ifndef NRFX_I2S_CONFIG_MASTER
 #define NRFX_I2S_CONFIG_MASTER 0
 #endif
 
 //  NRFX_I2S_CONFIG_FORMAT  - Format
- 
-// <0=> I2S 
-// <1=> Aligned 
+
+// <0=> I2S
+// <1=> Aligned
 
 #ifndef NRFX_I2S_CONFIG_FORMAT
 #define NRFX_I2S_CONFIG_FORMAT 0
 #endif
 
 //  NRFX_I2S_CONFIG_ALIGN  - Alignment
- 
-// <0=> Left 
-// <1=> Right 
+
+// <0=> Left
+// <1=> Right
 
 #ifndef NRFX_I2S_CONFIG_ALIGN
 #define NRFX_I2S_CONFIG_ALIGN 0
 #endif
 
 //  NRFX_I2S_CONFIG_SWIDTH  - Sample width (bits)
- 
-// <0=> 8 
-// <1=> 16 
-// <2=> 24 
+
+// <0=> 8
+// <1=> 16
+// <2=> 24
 
 #ifndef NRFX_I2S_CONFIG_SWIDTH
 #define NRFX_I2S_CONFIG_SWIDTH 1
 #endif
 
 //  NRFX_I2S_CONFIG_CHANNELS  - Channels
- 
-// <0=> Stereo 
-// <1=> Left 
-// <2=> Right 
+
+// <0=> Stereo
+// <1=> Left
+// <2=> Right
 
 #ifndef NRFX_I2S_CONFIG_CHANNELS
 #define NRFX_I2S_CONFIG_CHANNELS 1
 #endif
 
 //  NRFX_I2S_CONFIG_MCK_SETUP  - MCK behavior
- 
-// <0=> Disabled 
-// <2147483648=> 32MHz/2 
-// <1342177280=> 32MHz/3 
-// <1073741824=> 32MHz/4 
-// <805306368=> 32MHz/5 
-// <671088640=> 32MHz/6 
-// <536870912=> 32MHz/8 
-// <402653184=> 32MHz/10 
-// <369098752=> 32MHz/11 
-// <285212672=> 32MHz/15 
-// <268435456=> 32MHz/16 
-// <201326592=> 32MHz/21 
-// <184549376=> 32MHz/23 
-// <142606336=> 32MHz/30 
-// <138412032=> 32MHz/31 
-// <134217728=> 32MHz/32 
-// <100663296=> 32MHz/42 
-// <68157440=> 32MHz/63 
-// <34340864=> 32MHz/125 
+
+// <0=> Disabled
+// <2147483648=> 32MHz/2
+// <1342177280=> 32MHz/3
+// <1073741824=> 32MHz/4
+// <805306368=> 32MHz/5
+// <671088640=> 32MHz/6
+// <536870912=> 32MHz/8
+// <402653184=> 32MHz/10
+// <369098752=> 32MHz/11
+// <285212672=> 32MHz/15
+// <268435456=> 32MHz/16
+// <201326592=> 32MHz/21
+// <184549376=> 32MHz/23
+// <142606336=> 32MHz/30
+// <138412032=> 32MHz/31
+// <134217728=> 32MHz/32
+// <100663296=> 32MHz/42
+// <68157440=> 32MHz/63
+// <34340864=> 32MHz/125
 
 #ifndef NRFX_I2S_CONFIG_MCK_SETUP
 #define NRFX_I2S_CONFIG_MCK_SETUP 536870912
 #endif
 
 //  NRFX_I2S_CONFIG_RATIO  - MCK/LRCK ratio
- 
-// <0=> 32x 
-// <1=> 48x 
-// <2=> 64x 
-// <3=> 96x 
-// <4=> 128x 
-// <5=> 192x 
-// <6=> 256x 
-// <7=> 384x 
-// <8=> 512x 
+
+// <0=> 32x
+// <1=> 48x
+// <2=> 64x
+// <3=> 96x
+// <4=> 128x
+// <5=> 192x
+// <6=> 256x
+// <7=> 384x
+// <8=> 512x
 
 #ifndef NRFX_I2S_CONFIG_RATIO
 #define NRFX_I2S_CONFIG_RATIO 2000
 #endif
 
 //  NRFX_I2S_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_I2S_CONFIG_IRQ_PRIORITY
 #define NRFX_I2S_CONFIG_IRQ_PRIORITY 6
@@ -2122,44 +2122,44 @@
 #define NRFX_I2S_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_I2S_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_I2S_CONFIG_LOG_LEVEL
 #define NRFX_I2S_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_I2S_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_I2S_CONFIG_INFO_COLOR
 #define NRFX_I2S_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_I2S_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_I2S_CONFIG_DEBUG_COLOR
 #define NRFX_I2S_CONFIG_DEBUG_COLOR 0
@@ -2175,71 +2175,71 @@
 #define NRFX_LPCOMP_ENABLED 0
 #endif
 //  NRFX_LPCOMP_CONFIG_REFERENCE  - Reference voltage
- 
-// <0=> Supply 1/8 
-// <1=> Supply 2/8 
-// <2=> Supply 3/8 
-// <3=> Supply 4/8 
-// <4=> Supply 5/8 
-// <5=> Supply 6/8 
-// <6=> Supply 7/8 
-// <8=> Supply 1/16 (nRF52) 
-// <9=> Supply 3/16 (nRF52) 
-// <10=> Supply 5/16 (nRF52) 
-// <11=> Supply 7/16 (nRF52) 
-// <12=> Supply 9/16 (nRF52) 
-// <13=> Supply 11/16 (nRF52) 
-// <14=> Supply 13/16 (nRF52) 
-// <15=> Supply 15/16 (nRF52) 
-// <7=> External Ref 0 
-// <65543=> External Ref 1 
+
+// <0=> Supply 1/8
+// <1=> Supply 2/8
+// <2=> Supply 3/8
+// <3=> Supply 4/8
+// <4=> Supply 5/8
+// <5=> Supply 6/8
+// <6=> Supply 7/8
+// <8=> Supply 1/16 (nRF52)
+// <9=> Supply 3/16 (nRF52)
+// <10=> Supply 5/16 (nRF52)
+// <11=> Supply 7/16 (nRF52)
+// <12=> Supply 9/16 (nRF52)
+// <13=> Supply 11/16 (nRF52)
+// <14=> Supply 13/16 (nRF52)
+// <15=> Supply 15/16 (nRF52)
+// <7=> External Ref 0
+// <65543=> External Ref 1
 
 #ifndef NRFX_LPCOMP_CONFIG_REFERENCE
 #define NRFX_LPCOMP_CONFIG_REFERENCE 3
 #endif
 
 //  NRFX_LPCOMP_CONFIG_DETECTION  - Detection
- 
-// <0=> Crossing 
-// <1=> Up 
-// <2=> Down 
+
+// <0=> Crossing
+// <1=> Up
+// <2=> Down
 
 #ifndef NRFX_LPCOMP_CONFIG_DETECTION
 #define NRFX_LPCOMP_CONFIG_DETECTION 2
 #endif
 
 //  NRFX_LPCOMP_CONFIG_INPUT  - Analog input
- 
-// <0=> 0 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_LPCOMP_CONFIG_INPUT
 #define NRFX_LPCOMP_CONFIG_INPUT 0
 #endif
 
 //  NRFX_LPCOMP_CONFIG_HYST  - Hysteresis
- 
+
 
 #ifndef NRFX_LPCOMP_CONFIG_HYST
 #define NRFX_LPCOMP_CONFIG_HYST 0
 #endif
 
 //  NRFX_LPCOMP_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_LPCOMP_CONFIG_IRQ_PRIORITY
 #define NRFX_LPCOMP_CONFIG_IRQ_PRIORITY 6
@@ -2251,44 +2251,44 @@
 #define NRFX_LPCOMP_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_LPCOMP_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_LPCOMP_CONFIG_LOG_LEVEL
 #define NRFX_LPCOMP_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_LPCOMP_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_LPCOMP_CONFIG_INFO_COLOR
 #define NRFX_LPCOMP_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_LPCOMP_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_LPCOMP_CONFIG_DEBUG_COLOR
 #define NRFX_LPCOMP_CONFIG_DEBUG_COLOR 0
@@ -2304,15 +2304,15 @@
 #define NRFX_NFCT_ENABLED 0
 #endif
 //  NRFX_NFCT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_NFCT_CONFIG_IRQ_PRIORITY
 #define NRFX_NFCT_CONFIG_IRQ_PRIORITY 6
@@ -2324,44 +2324,44 @@
 #define NRFX_NFCT_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_NFCT_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_NFCT_CONFIG_LOG_LEVEL
 #define NRFX_NFCT_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_NFCT_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_NFCT_CONFIG_INFO_COLOR
 #define NRFX_NFCT_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_NFCT_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_NFCT_CONFIG_DEBUG_COLOR
 #define NRFX_NFCT_CONFIG_DEBUG_COLOR 0
@@ -2377,43 +2377,43 @@
 #define NRFX_PDM_ENABLED 0
 #endif
 //  NRFX_PDM_CONFIG_MODE  - Mode
- 
-// <0=> Stereo 
-// <1=> Mono 
+
+// <0=> Stereo
+// <1=> Mono
 
 #ifndef NRFX_PDM_CONFIG_MODE
 #define NRFX_PDM_CONFIG_MODE 1
 #endif
 
 //  NRFX_PDM_CONFIG_EDGE  - Edge
- 
-// <0=> Left falling 
-// <1=> Left rising 
+
+// <0=> Left falling
+// <1=> Left rising
 
 #ifndef NRFX_PDM_CONFIG_EDGE
 #define NRFX_PDM_CONFIG_EDGE 0
 #endif
 
 //  NRFX_PDM_CONFIG_CLOCK_FREQ  - Clock frequency
- 
-// <134217728=> 1000k 
-// <138412032=> 1032k (default) 
-// <142606336=> 1067k 
+
+// <134217728=> 1000k
+// <138412032=> 1032k (default)
+// <142606336=> 1067k
 
 #ifndef NRFX_PDM_CONFIG_CLOCK_FREQ
 #define NRFX_PDM_CONFIG_CLOCK_FREQ 138412032
 #endif
 
 //  NRFX_PDM_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_PDM_CONFIG_IRQ_PRIORITY
 #define NRFX_PDM_CONFIG_IRQ_PRIORITY 6
@@ -2425,44 +2425,44 @@
 #define NRFX_PDM_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_PDM_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_PDM_CONFIG_LOG_LEVEL
 #define NRFX_PDM_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_PDM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_PDM_CONFIG_INFO_COLOR
 #define NRFX_PDM_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_PDM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_PDM_CONFIG_DEBUG_COLOR
 #define NRFX_PDM_CONFIG_DEBUG_COLOR 0
@@ -2493,7 +2493,7 @@
 #endif
 
 //  NRFX_POWER_CONFIG_DEFAULT_DCDCEN  - The default configuration of main DCDC regulator
- 
+
 
 //  This settings means only that components for DCDC regulator are installed and it can be enabled.
 
@@ -2502,7 +2502,7 @@
 #endif
 
 //  NRFX_POWER_CONFIG_DEFAULT_DCDCENHV  - The default configuration of High Voltage DCDC regulator
- 
+
 
 //  This settings means only that components for DCDC regulator are installed and it can be enabled.
 
@@ -2523,44 +2523,44 @@
 #define NRFX_PPI_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_PPI_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_PPI_CONFIG_LOG_LEVEL
 #define NRFX_PPI_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_PPI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_PPI_CONFIG_INFO_COLOR
 #define NRFX_PPI_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_PPI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_PPI_CONFIG_DEBUG_COLOR
 #define NRFX_PPI_CONFIG_DEBUG_COLOR 0
@@ -2576,55 +2576,55 @@
 #define NRFX_PWM_ENABLED 0
 #endif
 //  NRFX_PWM0_ENABLED  - Enable PWM0 instance
- 
+
 
 #ifndef NRFX_PWM0_ENABLED
 #define NRFX_PWM0_ENABLED 0
 #endif
 
 //  NRFX_PWM1_ENABLED  - Enable PWM1 instance
- 
+
 
 #ifndef NRFX_PWM1_ENABLED
 #define NRFX_PWM1_ENABLED 0
 #endif
 
 //  NRFX_PWM2_ENABLED  - Enable PWM2 instance
- 
+
 
 #ifndef NRFX_PWM2_ENABLED
 #define NRFX_PWM2_ENABLED 0
 #endif
 
 //  NRFX_PWM3_ENABLED  - Enable PWM3 instance
- 
+
 
 #ifndef NRFX_PWM3_ENABLED
 #define NRFX_PWM3_ENABLED 0
 #endif
 
-//  NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin  <0-31> 
+//  NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin  <0-31>
 
 
 #ifndef NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN
 #define NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN 31
 #endif
 
-//  NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin  <0-31> 
+//  NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin  <0-31>
 
 
 #ifndef NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN
 #define NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN 31
 #endif
 
-//  NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin  <0-31> 
+//  NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin  <0-31>
 
 
 #ifndef NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN
 #define NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN 31
 #endif
 
-//  NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin  <0-31> 
+//  NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin  <0-31>
 
 
 #ifndef NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN
@@ -2632,64 +2632,64 @@
 #endif
 
 //  NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK  - Base clock
- 
-// <0=> 16 MHz 
-// <1=> 8 MHz 
-// <2=> 4 MHz 
-// <3=> 2 MHz 
-// <4=> 1 MHz 
-// <5=> 500 kHz 
-// <6=> 250 kHz 
-// <7=> 125 kHz 
+
+// <0=> 16 MHz
+// <1=> 8 MHz
+// <2=> 4 MHz
+// <3=> 2 MHz
+// <4=> 1 MHz
+// <5=> 500 kHz
+// <6=> 250 kHz
+// <7=> 125 kHz
 
 #ifndef NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK
 #define NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK 4
 #endif
 
 //  NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE  - Count mode
- 
-// <0=> Up 
-// <1=> Up and Down 
+
+// <0=> Up
+// <1=> Up and Down
 
 #ifndef NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE
 #define NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE 0
 #endif
 
-//  NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE - Top value 
+//  NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE - Top value
 #ifndef NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE
 #define NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE 1000
 #endif
 
 //  NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE  - Load mode
- 
-// <0=> Common 
-// <1=> Grouped 
-// <2=> Individual 
-// <3=> Waveform 
+
+// <0=> Common
+// <1=> Grouped
+// <2=> Individual
+// <3=> Waveform
 
 #ifndef NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE
 #define NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE 0
 #endif
 
 //  NRFX_PWM_DEFAULT_CONFIG_STEP_MODE  - Step mode
- 
-// <0=> Auto 
-// <1=> Triggered 
+
+// <0=> Auto
+// <1=> Triggered
 
 #ifndef NRFX_PWM_DEFAULT_CONFIG_STEP_MODE
 #define NRFX_PWM_DEFAULT_CONFIG_STEP_MODE 0
 #endif
 
 //  NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY
 #define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY 6
@@ -2701,44 +2701,44 @@
 #define NRFX_PWM_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_PWM_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_PWM_CONFIG_LOG_LEVEL
 #define NRFX_PWM_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_PWM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_PWM_CONFIG_INFO_COLOR
 #define NRFX_PWM_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_PWM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_PWM_CONFIG_DEBUG_COLOR
 #define NRFX_PWM_CONFIG_DEBUG_COLOR 0
@@ -2754,94 +2754,94 @@
 #define NRFX_QDEC_ENABLED 0
 #endif
 //  NRFX_QDEC_CONFIG_REPORTPER  - Report period
- 
-// <0=> 10 Samples 
-// <1=> 40 Samples 
-// <2=> 80 Samples 
-// <3=> 120 Samples 
-// <4=> 160 Samples 
-// <5=> 200 Samples 
-// <6=> 240 Samples 
-// <7=> 280 Samples 
+
+// <0=> 10 Samples
+// <1=> 40 Samples
+// <2=> 80 Samples
+// <3=> 120 Samples
+// <4=> 160 Samples
+// <5=> 200 Samples
+// <6=> 240 Samples
+// <7=> 280 Samples
 
 #ifndef NRFX_QDEC_CONFIG_REPORTPER
 #define NRFX_QDEC_CONFIG_REPORTPER 0
 #endif
 
 //  NRFX_QDEC_CONFIG_SAMPLEPER  - Sample period
- 
-// <0=> 128 us 
-// <1=> 256 us 
-// <2=> 512 us 
-// <3=> 1024 us 
-// <4=> 2048 us 
-// <5=> 4096 us 
-// <6=> 8192 us 
-// <7=> 16384 us 
+
+// <0=> 128 us
+// <1=> 256 us
+// <2=> 512 us
+// <3=> 1024 us
+// <4=> 2048 us
+// <5=> 4096 us
+// <6=> 8192 us
+// <7=> 16384 us
 
 #ifndef NRFX_QDEC_CONFIG_SAMPLEPER
 #define NRFX_QDEC_CONFIG_SAMPLEPER 7
 #endif
 
-//  NRFX_QDEC_CONFIG_PIO_A - A pin  <0-31> 
+//  NRFX_QDEC_CONFIG_PIO_A - A pin  <0-31>
 
 
 #ifndef NRFX_QDEC_CONFIG_PIO_A
 #define NRFX_QDEC_CONFIG_PIO_A 31
 #endif
 
-//  NRFX_QDEC_CONFIG_PIO_B - B pin  <0-31> 
+//  NRFX_QDEC_CONFIG_PIO_B - B pin  <0-31>
 
 
 #ifndef NRFX_QDEC_CONFIG_PIO_B
 #define NRFX_QDEC_CONFIG_PIO_B 31
 #endif
 
-//  NRFX_QDEC_CONFIG_PIO_LED - LED pin  <0-31> 
+//  NRFX_QDEC_CONFIG_PIO_LED - LED pin  <0-31>
 
 
 #ifndef NRFX_QDEC_CONFIG_PIO_LED
 #define NRFX_QDEC_CONFIG_PIO_LED 31
 #endif
 
-//  NRFX_QDEC_CONFIG_LEDPRE - LED pre 
+//  NRFX_QDEC_CONFIG_LEDPRE - LED pre
 #ifndef NRFX_QDEC_CONFIG_LEDPRE
 #define NRFX_QDEC_CONFIG_LEDPRE 511
 #endif
 
 //  NRFX_QDEC_CONFIG_LEDPOL  - LED polarity
- 
-// <0=> Active low 
-// <1=> Active high 
+
+// <0=> Active low
+// <1=> Active high
 
 #ifndef NRFX_QDEC_CONFIG_LEDPOL
 #define NRFX_QDEC_CONFIG_LEDPOL 1
 #endif
 
 //  NRFX_QDEC_CONFIG_DBFEN  - Debouncing enable
- 
+
 
 #ifndef NRFX_QDEC_CONFIG_DBFEN
 #define NRFX_QDEC_CONFIG_DBFEN 0
 #endif
 
 //  NRFX_QDEC_CONFIG_SAMPLE_INTEN  - Sample ready interrupt enable
- 
+
 
 #ifndef NRFX_QDEC_CONFIG_SAMPLE_INTEN
 #define NRFX_QDEC_CONFIG_SAMPLE_INTEN 0
 #endif
 
 //  NRFX_QDEC_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_QDEC_CONFIG_IRQ_PRIORITY
 #define NRFX_QDEC_CONFIG_IRQ_PRIORITY 6
@@ -2853,44 +2853,44 @@
 #define NRFX_QDEC_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_QDEC_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_QDEC_CONFIG_LOG_LEVEL
 #define NRFX_QDEC_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_QDEC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_QDEC_CONFIG_INFO_COLOR
 #define NRFX_QDEC_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_QDEC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_QDEC_CONFIG_DEBUG_COLOR
 #define NRFX_QDEC_CONFIG_DEBUG_COLOR 0
@@ -2905,77 +2905,77 @@
 #ifndef NRFX_QSPI_ENABLED
 #define NRFX_QSPI_ENABLED 0
 #endif
-//  NRFX_QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns).  <0-255> 
+//  NRFX_QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns).  <0-255>
 
 
 #ifndef NRFX_QSPI_CONFIG_SCK_DELAY
 #define NRFX_QSPI_CONFIG_SCK_DELAY 1
 #endif
 
-//  NRFX_QSPI_CONFIG_XIP_OFFSET - Address offset in the external memory for Execute in Place operation. 
+//  NRFX_QSPI_CONFIG_XIP_OFFSET - Address offset in the external memory for Execute in Place operation.
 #ifndef NRFX_QSPI_CONFIG_XIP_OFFSET
 #define NRFX_QSPI_CONFIG_XIP_OFFSET 0
 #endif
 
 //  NRFX_QSPI_CONFIG_READOC  - Number of data lines and opcode used for reading.
- 
-// <0=> FastRead 
-// <1=> Read2O 
-// <2=> Read2IO 
-// <3=> Read4O 
-// <4=> Read4IO 
+
+// <0=> FastRead
+// <1=> Read2O
+// <2=> Read2IO
+// <3=> Read4O
+// <4=> Read4IO
 
 #ifndef NRFX_QSPI_CONFIG_READOC
 #define NRFX_QSPI_CONFIG_READOC 0
 #endif
 
 //  NRFX_QSPI_CONFIG_WRITEOC  - Number of data lines and opcode used for writing.
- 
-// <0=> PP 
-// <1=> PP2O 
-// <2=> PP4O 
-// <3=> PP4IO 
+
+// <0=> PP
+// <1=> PP2O
+// <2=> PP4O
+// <3=> PP4IO
 
 #ifndef NRFX_QSPI_CONFIG_WRITEOC
 #define NRFX_QSPI_CONFIG_WRITEOC 0
 #endif
 
 //  NRFX_QSPI_CONFIG_ADDRMODE  - Addressing mode.
- 
-// <0=> 24bit 
-// <1=> 32bit 
+
+// <0=> 24bit
+// <1=> 32bit
 
 #ifndef NRFX_QSPI_CONFIG_ADDRMODE
 #define NRFX_QSPI_CONFIG_ADDRMODE 0
 #endif
 
 //  NRFX_QSPI_CONFIG_MODE  - SPI mode.
- 
-// <0=> Mode 0 
-// <1=> Mode 1 
+
+// <0=> Mode 0
+// <1=> Mode 1
 
 #ifndef NRFX_QSPI_CONFIG_MODE
 #define NRFX_QSPI_CONFIG_MODE 0
 #endif
 
 //  NRFX_QSPI_CONFIG_FREQUENCY  - Frequency divider.
- 
-// <0=> 32MHz/1 
-// <1=> 32MHz/2 
-// <2=> 32MHz/3 
-// <3=> 32MHz/4 
-// <4=> 32MHz/5 
-// <5=> 32MHz/6 
-// <6=> 32MHz/7 
-// <7=> 32MHz/8 
-// <8=> 32MHz/9 
-// <9=> 32MHz/10 
-// <10=> 32MHz/11 
-// <11=> 32MHz/12 
-// <12=> 32MHz/13 
-// <13=> 32MHz/14 
-// <14=> 32MHz/15 
-// <15=> 32MHz/16 
+
+// <0=> 32MHz/1
+// <1=> 32MHz/2
+// <2=> 32MHz/3
+// <3=> 32MHz/4
+// <4=> 32MHz/5
+// <5=> 32MHz/6
+// <6=> 32MHz/7
+// <7=> 32MHz/8
+// <8=> 32MHz/9
+// <9=> 32MHz/10
+// <10=> 32MHz/11
+// <11=> 32MHz/12
+// <12=> 32MHz/13
+// <13=> 32MHz/14
+// <14=> 32MHz/15
+// <15=> 32MHz/16
 
 #ifndef NRFX_QSPI_CONFIG_FREQUENCY
 #define NRFX_QSPI_CONFIG_FREQUENCY 15
@@ -3012,15 +3012,15 @@
 #endif
 
 //  NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY
 #define NRFX_QSPI_DEFAULT_CONFIG_IRQ_PRIORITY 6
@@ -3034,22 +3034,22 @@
 #define NRFX_RNG_ENABLED 0
 #endif
 //  NRFX_RNG_CONFIG_ERROR_CORRECTION  - Error correction
- 
+
 
 #ifndef NRFX_RNG_CONFIG_ERROR_CORRECTION
 #define NRFX_RNG_CONFIG_ERROR_CORRECTION 1
 #endif
 
 //  NRFX_RNG_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_RNG_CONFIG_IRQ_PRIORITY
 #define NRFX_RNG_CONFIG_IRQ_PRIORITY 6
@@ -3061,44 +3061,44 @@
 #define NRFX_RNG_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_RNG_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_RNG_CONFIG_LOG_LEVEL
 #define NRFX_RNG_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_RNG_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_RNG_CONFIG_INFO_COLOR
 #define NRFX_RNG_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_RNG_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_RNG_CONFIG_DEBUG_COLOR
 #define NRFX_RNG_CONFIG_DEBUG_COLOR 0
@@ -3114,32 +3114,32 @@
 #define NRFX_RTC_ENABLED 0
 #endif
 //  NRFX_RTC0_ENABLED  - Enable RTC0 instance
- 
+
 
 #ifndef NRFX_RTC0_ENABLED
 #define NRFX_RTC0_ENABLED 0
 #endif
 
 //  NRFX_RTC1_ENABLED  - Enable RTC1 instance
- 
+
 
 #ifndef NRFX_RTC1_ENABLED
 #define NRFX_RTC1_ENABLED 0
 #endif
 
 //  NRFX_RTC2_ENABLED  - Enable RTC2 instance
- 
+
 
 #ifndef NRFX_RTC2_ENABLED
 #define NRFX_RTC2_ENABLED 0
 #endif
 
-//  NRFX_RTC_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt 
+//  NRFX_RTC_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt
 #ifndef NRFX_RTC_MAXIMUM_LATENCY_US
 #define NRFX_RTC_MAXIMUM_LATENCY_US 2000
 #endif
 
-//  NRFX_RTC_DEFAULT_CONFIG_FREQUENCY - Frequency  <16-32768> 
+//  NRFX_RTC_DEFAULT_CONFIG_FREQUENCY - Frequency  <16-32768>
 
 
 #ifndef NRFX_RTC_DEFAULT_CONFIG_FREQUENCY
@@ -3147,22 +3147,22 @@
 #endif
 
 //  NRFX_RTC_DEFAULT_CONFIG_RELIABLE  - Ensures safe compare event triggering
- 
+
 
 #ifndef NRFX_RTC_DEFAULT_CONFIG_RELIABLE
 #define NRFX_RTC_DEFAULT_CONFIG_RELIABLE 0
 #endif
 
 //  NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY
 #define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY 6
@@ -3174,44 +3174,44 @@
 #define NRFX_RTC_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_RTC_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_RTC_CONFIG_LOG_LEVEL
 #define NRFX_RTC_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_RTC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_RTC_CONFIG_INFO_COLOR
 #define NRFX_RTC_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_RTC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_RTC_CONFIG_DEBUG_COLOR
 #define NRFX_RTC_CONFIG_DEBUG_COLOR 0
@@ -3227,49 +3227,49 @@
 #define NRFX_SAADC_ENABLED 0
 #endif
 //  NRFX_SAADC_CONFIG_RESOLUTION  - Resolution
- 
-// <0=> 8 bit 
-// <1=> 10 bit 
-// <2=> 12 bit 
-// <3=> 14 bit 
+
+// <0=> 8 bit
+// <1=> 10 bit
+// <2=> 12 bit
+// <3=> 14 bit
 
 #ifndef NRFX_SAADC_CONFIG_RESOLUTION
 #define NRFX_SAADC_CONFIG_RESOLUTION 1
 #endif
 
 //  NRFX_SAADC_CONFIG_OVERSAMPLE  - Sample period
- 
-// <0=> Disabled 
-// <1=> 2x 
-// <2=> 4x 
-// <3=> 8x 
-// <4=> 16x 
-// <5=> 32x 
-// <6=> 64x 
-// <7=> 128x 
-// <8=> 256x 
+
+// <0=> Disabled
+// <1=> 2x
+// <2=> 4x
+// <3=> 8x
+// <4=> 16x
+// <5=> 32x
+// <6=> 64x
+// <7=> 128x
+// <8=> 256x
 
 #ifndef NRFX_SAADC_CONFIG_OVERSAMPLE
 #define NRFX_SAADC_CONFIG_OVERSAMPLE 0
 #endif
 
 //  NRFX_SAADC_CONFIG_LP_MODE  - Enabling low power mode
- 
+
 
 #ifndef NRFX_SAADC_CONFIG_LP_MODE
 #define NRFX_SAADC_CONFIG_LP_MODE 0
 #endif
 
 //  NRFX_SAADC_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_SAADC_CONFIG_IRQ_PRIORITY
 #define NRFX_SAADC_CONFIG_IRQ_PRIORITY 6
@@ -3281,44 +3281,44 @@
 #define NRFX_SAADC_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_SAADC_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_SAADC_CONFIG_LOG_LEVEL
 #define NRFX_SAADC_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_SAADC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_SAADC_CONFIG_INFO_COLOR
 #define NRFX_SAADC_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_SAADC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_SAADC_CONFIG_DEBUG_COLOR
 #define NRFX_SAADC_CONFIG_DEBUG_COLOR 0
@@ -3334,60 +3334,60 @@
 #define NRFX_SPIM_ENABLED 0
 #endif
 //  NRFX_SPIM0_ENABLED  - Enable SPIM0 instance
- 
+
 
 #ifndef NRFX_SPIM0_ENABLED
 #define NRFX_SPIM0_ENABLED 0
 #endif
 
 //  NRFX_SPIM1_ENABLED  - Enable SPIM1 instance
- 
+
 
 #ifndef NRFX_SPIM1_ENABLED
 #define NRFX_SPIM1_ENABLED 0
 #endif
 
 //  NRFX_SPIM2_ENABLED  - Enable SPIM2 instance
- 
+
 
 #ifndef NRFX_SPIM2_ENABLED
 #define NRFX_SPIM2_ENABLED 0
 #endif
 
 //  NRFX_SPIM3_ENABLED  - Enable SPIM3 instance
- 
+
 
 #ifndef NRFX_SPIM3_ENABLED
 #define NRFX_SPIM3_ENABLED 0
 #endif
 
 //  NRFX_SPIM_EXTENDED_ENABLED  - Enable extended SPIM features
- 
+
 
 #ifndef NRFX_SPIM_EXTENDED_ENABLED
 #define NRFX_SPIM_EXTENDED_ENABLED 0
 #endif
 
 //  NRFX_SPIM_MISO_PULL_CFG  - MISO pin pull configuration.
- 
-// <0=> NRF_GPIO_PIN_NOPULL 
-// <1=> NRF_GPIO_PIN_PULLDOWN 
-// <3=> NRF_GPIO_PIN_PULLUP 
+
+// <0=> NRF_GPIO_PIN_NOPULL
+// <1=> NRF_GPIO_PIN_PULLDOWN
+// <3=> NRF_GPIO_PIN_PULLUP
 
 #ifndef NRFX_SPIM_MISO_PULL_CFG
 #define NRFX_SPIM_MISO_PULL_CFG 1
 #endif
 
 //  NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY
 #define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY 6
@@ -3399,44 +3399,44 @@
 #define NRFX_SPIM_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_SPIM_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_SPIM_CONFIG_LOG_LEVEL
 #define NRFX_SPIM_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_SPIM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_SPIM_CONFIG_INFO_COLOR
 #define NRFX_SPIM_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_SPIM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_SPIM_CONFIG_DEBUG_COLOR
 #define NRFX_SPIM_CONFIG_DEBUG_COLOR 0
@@ -3452,49 +3452,49 @@
 #define NRFX_SPIS_ENABLED 0
 #endif
 //  NRFX_SPIS0_ENABLED  - Enable SPIS0 instance
- 
+
 
 #ifndef NRFX_SPIS0_ENABLED
 #define NRFX_SPIS0_ENABLED 0
 #endif
 
 //  NRFX_SPIS1_ENABLED  - Enable SPIS1 instance
- 
+
 
 #ifndef NRFX_SPIS1_ENABLED
 #define NRFX_SPIS1_ENABLED 0
 #endif
 
 //  NRFX_SPIS2_ENABLED  - Enable SPIS2 instance
- 
+
 
 #ifndef NRFX_SPIS2_ENABLED
 #define NRFX_SPIS2_ENABLED 0
 #endif
 
 //  NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
 #define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 6
 #endif
 
-//  NRFX_SPIS_DEFAULT_DEF - SPIS default DEF character  <0-255> 
+//  NRFX_SPIS_DEFAULT_DEF - SPIS default DEF character  <0-255>
 
 
 #ifndef NRFX_SPIS_DEFAULT_DEF
 #define NRFX_SPIS_DEFAULT_DEF 255
 #endif
 
-//  NRFX_SPIS_DEFAULT_ORC - SPIS default ORC character  <0-255> 
+//  NRFX_SPIS_DEFAULT_ORC - SPIS default ORC character  <0-255>
 
 
 #ifndef NRFX_SPIS_DEFAULT_ORC
@@ -3507,44 +3507,44 @@
 #define NRFX_SPIS_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_SPIS_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_SPIS_CONFIG_LOG_LEVEL
 #define NRFX_SPIS_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_SPIS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_SPIS_CONFIG_INFO_COLOR
 #define NRFX_SPIS_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_SPIS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_SPIS_CONFIG_DEBUG_COLOR
 #define NRFX_SPIS_CONFIG_DEBUG_COLOR 0
@@ -3560,46 +3560,46 @@
 #define NRFX_SPI_ENABLED 0
 #endif
 //  NRFX_SPI0_ENABLED  - Enable SPI0 instance
- 
+
 
 #ifndef NRFX_SPI0_ENABLED
 #define NRFX_SPI0_ENABLED 0
 #endif
 
 //  NRFX_SPI1_ENABLED  - Enable SPI1 instance
- 
+
 
 #ifndef NRFX_SPI1_ENABLED
 #define NRFX_SPI1_ENABLED 0
 #endif
 
 //  NRFX_SPI2_ENABLED  - Enable SPI2 instance
- 
+
 
 #ifndef NRFX_SPI2_ENABLED
 #define NRFX_SPI2_ENABLED 0
 #endif
 
 //  NRFX_SPI_MISO_PULL_CFG  - MISO pin pull configuration.
- 
-// <0=> NRF_GPIO_PIN_NOPULL 
-// <1=> NRF_GPIO_PIN_PULLDOWN 
-// <3=> NRF_GPIO_PIN_PULLUP 
+
+// <0=> NRF_GPIO_PIN_NOPULL
+// <1=> NRF_GPIO_PIN_PULLDOWN
+// <3=> NRF_GPIO_PIN_PULLUP
 
 #ifndef NRFX_SPI_MISO_PULL_CFG
 #define NRFX_SPI_MISO_PULL_CFG 1
 #endif
 
 //  NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY
 #define NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY 6
@@ -3611,44 +3611,44 @@
 #define NRFX_SPI_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_SPI_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_SPI_CONFIG_LOG_LEVEL
 #define NRFX_SPI_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_SPI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_SPI_CONFIG_INFO_COLOR
 #define NRFX_SPI_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_SPI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_SPI_CONFIG_DEBUG_COLOR
 #define NRFX_SPI_CONFIG_DEBUG_COLOR 0
@@ -3664,49 +3664,49 @@
 #define NRFX_SWI_ENABLED 0
 #endif
 //  NRFX_EGU_ENABLED  - Enable EGU support
- 
+
 
 #ifndef NRFX_EGU_ENABLED
 #define NRFX_EGU_ENABLED 0
 #endif
 
 //  NRFX_SWI0_DISABLED  - Exclude SWI0 from being utilized by the driver
- 
+
 
 #ifndef NRFX_SWI0_DISABLED
 #define NRFX_SWI0_DISABLED 0
 #endif
 
 //  NRFX_SWI1_DISABLED  - Exclude SWI1 from being utilized by the driver
- 
+
 
 #ifndef NRFX_SWI1_DISABLED
 #define NRFX_SWI1_DISABLED 0
 #endif
 
 //  NRFX_SWI2_DISABLED  - Exclude SWI2 from being utilized by the driver
- 
+
 
 #ifndef NRFX_SWI2_DISABLED
 #define NRFX_SWI2_DISABLED 0
 #endif
 
 //  NRFX_SWI3_DISABLED  - Exclude SWI3 from being utilized by the driver
- 
+
 
 #ifndef NRFX_SWI3_DISABLED
 #define NRFX_SWI3_DISABLED 0
 #endif
 
 //  NRFX_SWI4_DISABLED  - Exclude SWI4 from being utilized by the driver
- 
+
 
 #ifndef NRFX_SWI4_DISABLED
 #define NRFX_SWI4_DISABLED 0
 #endif
 
 //  NRFX_SWI5_DISABLED  - Exclude SWI5 from being utilized by the driver
- 
+
 
 #ifndef NRFX_SWI5_DISABLED
 #define NRFX_SWI5_DISABLED 0
@@ -3718,44 +3718,44 @@
 #define NRFX_SWI_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_SWI_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_SWI_CONFIG_LOG_LEVEL
 #define NRFX_SWI_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_SWI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_SWI_CONFIG_INFO_COLOR
 #define NRFX_SWI_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_SWI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_SWI_CONFIG_DEBUG_COLOR
 #define NRFX_SWI_CONFIG_DEBUG_COLOR 0
@@ -3771,87 +3771,87 @@
 #define NRFX_TIMER_ENABLED 0
 #endif
 //  NRFX_TIMER0_ENABLED  - Enable TIMER0 instance
- 
+
 
 #ifndef NRFX_TIMER0_ENABLED
 #define NRFX_TIMER0_ENABLED 0
 #endif
 
 //  NRFX_TIMER1_ENABLED  - Enable TIMER1 instance
- 
+
 
 #ifndef NRFX_TIMER1_ENABLED
 #define NRFX_TIMER1_ENABLED 0
 #endif
 
 //  NRFX_TIMER2_ENABLED  - Enable TIMER2 instance
- 
+
 
 #ifndef NRFX_TIMER2_ENABLED
 #define NRFX_TIMER2_ENABLED 0
 #endif
 
 //  NRFX_TIMER3_ENABLED  - Enable TIMER3 instance
- 
+
 
 #ifndef NRFX_TIMER3_ENABLED
 #define NRFX_TIMER3_ENABLED 0
 #endif
 
 //  NRFX_TIMER4_ENABLED  - Enable TIMER4 instance
- 
+
 
 #ifndef NRFX_TIMER4_ENABLED
 #define NRFX_TIMER4_ENABLED 0
 #endif
 
 //  NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY  - Timer frequency if in Timer mode
- 
-// <0=> 16 MHz 
-// <1=> 8 MHz 
-// <2=> 4 MHz 
-// <3=> 2 MHz 
-// <4=> 1 MHz 
-// <5=> 500 kHz 
-// <6=> 250 kHz 
-// <7=> 125 kHz 
-// <8=> 62.5 kHz 
-// <9=> 31.25 kHz 
+
+// <0=> 16 MHz
+// <1=> 8 MHz
+// <2=> 4 MHz
+// <3=> 2 MHz
+// <4=> 1 MHz
+// <5=> 500 kHz
+// <6=> 250 kHz
+// <7=> 125 kHz
+// <8=> 62.5 kHz
+// <9=> 31.25 kHz
 
 #ifndef NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY
 #define NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY 0
 #endif
 
 //  NRFX_TIMER_DEFAULT_CONFIG_MODE  - Timer mode or operation
- 
-// <0=> Timer 
-// <1=> Counter 
+
+// <0=> Timer
+// <1=> Counter
 
 #ifndef NRFX_TIMER_DEFAULT_CONFIG_MODE
 #define NRFX_TIMER_DEFAULT_CONFIG_MODE 0
 #endif
 
 //  NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH  - Timer counter bit width
- 
-// <0=> 16 bit 
-// <1=> 8 bit 
-// <2=> 24 bit 
-// <3=> 32 bit 
+
+// <0=> 16 bit
+// <1=> 8 bit
+// <2=> 24 bit
+// <3=> 32 bit
 
 #ifndef NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH
 #define NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH 0
 #endif
 
 //  NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
 #define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 6
@@ -3863,44 +3863,44 @@
 #define NRFX_TIMER_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_TIMER_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_TIMER_CONFIG_LOG_LEVEL
 #define NRFX_TIMER_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_TIMER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_TIMER_CONFIG_INFO_COLOR
 #define NRFX_TIMER_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_TIMER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_TIMER_CONFIG_DEBUG_COLOR
 #define NRFX_TIMER_CONFIG_DEBUG_COLOR 0
@@ -3916,46 +3916,46 @@
 #define NRFX_TWIM_ENABLED 0
 #endif
 //  NRFX_TWIM0_ENABLED  - Enable TWIM0 instance
- 
+
 
 #ifndef NRFX_TWIM0_ENABLED
 #define NRFX_TWIM0_ENABLED 0
 #endif
 
 //  NRFX_TWIM1_ENABLED  - Enable TWIM1 instance
- 
+
 
 #ifndef NRFX_TWIM1_ENABLED
 #define NRFX_TWIM1_ENABLED 0
 #endif
 
 //  NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY  - Frequency
- 
-// <26738688=> 100k 
-// <67108864=> 250k 
-// <104857600=> 400k 
+
+// <26738688=> 100k
+// <67108864=> 250k
+// <104857600=> 400k
 
 #ifndef NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY
 #define NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY 26738688
 #endif
 
 //  NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT  - Enables bus holding after uninit
- 
+
 
 #ifndef NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT
 #define NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0
 #endif
 
 //  NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY
 #define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY 6
@@ -3967,44 +3967,44 @@
 #define NRFX_TWIM_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_TWIM_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_TWIM_CONFIG_LOG_LEVEL
 #define NRFX_TWIM_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_TWIM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_TWIM_CONFIG_INFO_COLOR
 #define NRFX_TWIM_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_TWIM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_TWIM_CONFIG_DEBUG_COLOR
 #define NRFX_TWIM_CONFIG_DEBUG_COLOR 0
@@ -4020,21 +4020,21 @@
 #define NRFX_TWIS_ENABLED 0
 #endif
 //  NRFX_TWIS0_ENABLED  - Enable TWIS0 instance
- 
+
 
 #ifndef NRFX_TWIS0_ENABLED
 #define NRFX_TWIS0_ENABLED 0
 #endif
 
 //  NRFX_TWIS1_ENABLED  - Enable TWIS1 instance
- 
+
 
 #ifndef NRFX_TWIS1_ENABLED
 #define NRFX_TWIS1_ENABLED 0
 #endif
 
 //  NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY  - Assume that any instance would be initialized only once
- 
+
 
 //  Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code.
 
@@ -4043,7 +4043,7 @@
 #endif
 
 //  NRFX_TWIS_NO_SYNC_MODE  - Remove support for synchronous mode
- 
+
 
 //  Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources.
 
@@ -4051,46 +4051,46 @@
 #define NRFX_TWIS_NO_SYNC_MODE 0
 #endif
 
-//  NRFX_TWIS_DEFAULT_CONFIG_ADDR0 - Address0 
+//  NRFX_TWIS_DEFAULT_CONFIG_ADDR0 - Address0
 #ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR0
 #define NRFX_TWIS_DEFAULT_CONFIG_ADDR0 0
 #endif
 
-//  NRFX_TWIS_DEFAULT_CONFIG_ADDR1 - Address1 
+//  NRFX_TWIS_DEFAULT_CONFIG_ADDR1 - Address1
 #ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR1
 #define NRFX_TWIS_DEFAULT_CONFIG_ADDR1 0
 #endif
 
 //  NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL  - SCL pin pull configuration
- 
-// <0=> Disabled 
-// <1=> Pull down 
-// <3=> Pull up 
+
+// <0=> Disabled
+// <1=> Pull down
+// <3=> Pull up
 
 #ifndef NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL
 #define NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL 0
 #endif
 
 //  NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL  - SDA pin pull configuration
- 
-// <0=> Disabled 
-// <1=> Pull down 
-// <3=> Pull up 
+
+// <0=> Disabled
+// <1=> Pull down
+// <3=> Pull up
 
 #ifndef NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL
 #define NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL 0
 #endif
 
 //  NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
 #define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 6
@@ -4102,44 +4102,44 @@
 #define NRFX_TWIS_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_TWIS_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_TWIS_CONFIG_LOG_LEVEL
 #define NRFX_TWIS_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_TWIS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_TWIS_CONFIG_INFO_COLOR
 #define NRFX_TWIS_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_TWIS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_TWIS_CONFIG_DEBUG_COLOR
 #define NRFX_TWIS_CONFIG_DEBUG_COLOR 0
@@ -4155,46 +4155,46 @@
 #define NRFX_TWI_ENABLED 0
 #endif
 //  NRFX_TWI0_ENABLED  - Enable TWI0 instance
- 
+
 
 #ifndef NRFX_TWI0_ENABLED
 #define NRFX_TWI0_ENABLED 0
 #endif
 
 //  NRFX_TWI1_ENABLED  - Enable TWI1 instance
- 
+
 
 #ifndef NRFX_TWI1_ENABLED
 #define NRFX_TWI1_ENABLED 0
 #endif
 
 //  NRFX_TWI_DEFAULT_CONFIG_FREQUENCY  - Frequency
- 
-// <26738688=> 100k 
-// <67108864=> 250k 
-// <104857600=> 400k 
+
+// <26738688=> 100k
+// <67108864=> 250k
+// <104857600=> 400k
 
 #ifndef NRFX_TWI_DEFAULT_CONFIG_FREQUENCY
 #define NRFX_TWI_DEFAULT_CONFIG_FREQUENCY 26738688
 #endif
 
 //  NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT  - Enables bus holding after uninit
- 
+
 
 #ifndef NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT
 #define NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0
 #endif
 
 //  NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY
 #define NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY 6
@@ -4206,44 +4206,44 @@
 #define NRFX_TWI_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_TWI_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_TWI_CONFIG_LOG_LEVEL
 #define NRFX_TWI_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_TWI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_TWI_CONFIG_INFO_COLOR
 #define NRFX_TWI_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_TWI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_TWI_CONFIG_DEBUG_COLOR
 #define NRFX_TWI_CONFIG_DEBUG_COLOR 0
@@ -4258,69 +4258,69 @@
 #ifndef NRFX_UARTE_ENABLED
 #define NRFX_UARTE_ENABLED 0
 #endif
-//  NRFX_UARTE0_ENABLED - Enable UARTE0 instance 
+//  NRFX_UARTE0_ENABLED - Enable UARTE0 instance
 #ifndef NRFX_UARTE0_ENABLED
 #define NRFX_UARTE0_ENABLED 0
 #endif
 
-//  NRFX_UARTE1_ENABLED - Enable UARTE1 instance 
+//  NRFX_UARTE1_ENABLED - Enable UARTE1 instance
 #ifndef NRFX_UARTE1_ENABLED
 #define NRFX_UARTE1_ENABLED 0
 #endif
 
 //  NRFX_UARTE_DEFAULT_CONFIG_HWFC  - Hardware Flow Control
- 
-// <0=> Disabled 
-// <1=> Enabled 
+
+// <0=> Disabled
+// <1=> Enabled
 
 #ifndef NRFX_UARTE_DEFAULT_CONFIG_HWFC
 #define NRFX_UARTE_DEFAULT_CONFIG_HWFC 0
 #endif
 
 //  NRFX_UARTE_DEFAULT_CONFIG_PARITY  - Parity
- 
-// <0=> Excluded 
-// <14=> Included 
+
+// <0=> Excluded
+// <14=> Included
 
 #ifndef NRFX_UARTE_DEFAULT_CONFIG_PARITY
 #define NRFX_UARTE_DEFAULT_CONFIG_PARITY 0
 #endif
 
 //  NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE  - Default Baudrate
- 
-// <323584=> 1200 baud 
-// <643072=> 2400 baud 
-// <1290240=> 4800 baud 
-// <2576384=> 9600 baud 
-// <3862528=> 14400 baud 
-// <5152768=> 19200 baud 
-// <7716864=> 28800 baud 
-// <8388608=> 31250 baud 
-// <10289152=> 38400 baud 
-// <15007744=> 56000 baud 
-// <15400960=> 57600 baud 
-// <20615168=> 76800 baud 
-// <30801920=> 115200 baud 
-// <61865984=> 230400 baud 
-// <67108864=> 250000 baud 
-// <121634816=> 460800 baud 
-// <251658240=> 921600 baud 
-// <268435456=> 1000000 baud 
+
+// <323584=> 1200 baud
+// <643072=> 2400 baud
+// <1290240=> 4800 baud
+// <2576384=> 9600 baud
+// <3862528=> 14400 baud
+// <5152768=> 19200 baud
+// <7716864=> 28800 baud
+// <8388608=> 31250 baud
+// <10289152=> 38400 baud
+// <15007744=> 56000 baud
+// <15400960=> 57600 baud
+// <20615168=> 76800 baud
+// <30801920=> 115200 baud
+// <61865984=> 230400 baud
+// <67108864=> 250000 baud
+// <121634816=> 460800 baud
+// <251658240=> 921600 baud
+// <268435456=> 1000000 baud
 
 #ifndef NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE
 #define NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE 30801920
 #endif
 
 //  NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY
 #define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY 6
@@ -4332,44 +4332,44 @@
 #define NRFX_UARTE_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_UARTE_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_UARTE_CONFIG_LOG_LEVEL
 #define NRFX_UARTE_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_UARTE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_UARTE_CONFIG_INFO_COLOR
 #define NRFX_UARTE_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_UARTE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_UARTE_CONFIG_DEBUG_COLOR
 #define NRFX_UARTE_CONFIG_DEBUG_COLOR 0
@@ -4384,64 +4384,64 @@
 #ifndef NRFX_UART_ENABLED
 #define NRFX_UART_ENABLED 0
 #endif
-//  NRFX_UART0_ENABLED - Enable UART0 instance 
+//  NRFX_UART0_ENABLED - Enable UART0 instance
 #ifndef NRFX_UART0_ENABLED
 #define NRFX_UART0_ENABLED 0
 #endif
 
 //  NRFX_UART_DEFAULT_CONFIG_HWFC  - Hardware Flow Control
- 
-// <0=> Disabled 
-// <1=> Enabled 
+
+// <0=> Disabled
+// <1=> Enabled
 
 #ifndef NRFX_UART_DEFAULT_CONFIG_HWFC
 #define NRFX_UART_DEFAULT_CONFIG_HWFC 0
 #endif
 
 //  NRFX_UART_DEFAULT_CONFIG_PARITY  - Parity
- 
-// <0=> Excluded 
-// <14=> Included 
+
+// <0=> Excluded
+// <14=> Included
 
 #ifndef NRFX_UART_DEFAULT_CONFIG_PARITY
 #define NRFX_UART_DEFAULT_CONFIG_PARITY 0
 #endif
 
 //  NRFX_UART_DEFAULT_CONFIG_BAUDRATE  - Default Baudrate
- 
-// <323584=> 1200 baud 
-// <643072=> 2400 baud 
-// <1290240=> 4800 baud 
-// <2576384=> 9600 baud 
-// <3866624=> 14400 baud 
-// <5152768=> 19200 baud 
-// <7729152=> 28800 baud 
-// <8388608=> 31250 baud 
-// <10309632=> 38400 baud 
-// <15007744=> 56000 baud 
-// <15462400=> 57600 baud 
-// <20615168=> 76800 baud 
-// <30924800=> 115200 baud 
-// <61845504=> 230400 baud 
-// <67108864=> 250000 baud 
-// <123695104=> 460800 baud 
-// <247386112=> 921600 baud 
-// <268435456=> 1000000 baud 
+
+// <323584=> 1200 baud
+// <643072=> 2400 baud
+// <1290240=> 4800 baud
+// <2576384=> 9600 baud
+// <3866624=> 14400 baud
+// <5152768=> 19200 baud
+// <7729152=> 28800 baud
+// <8388608=> 31250 baud
+// <10309632=> 38400 baud
+// <15007744=> 56000 baud
+// <15462400=> 57600 baud
+// <20615168=> 76800 baud
+// <30924800=> 115200 baud
+// <61845504=> 230400 baud
+// <67108864=> 250000 baud
+// <123695104=> 460800 baud
+// <247386112=> 921600 baud
+// <268435456=> 1000000 baud
 
 #ifndef NRFX_UART_DEFAULT_CONFIG_BAUDRATE
 #define NRFX_UART_DEFAULT_CONFIG_BAUDRATE 30924800
 #endif
 
 //  NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY
 #define NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY 4
@@ -4453,44 +4453,44 @@
 #define NRFX_UART_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_UART_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_UART_CONFIG_LOG_LEVEL
 #define NRFX_UART_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_UART_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_UART_CONFIG_INFO_COLOR
 #define NRFX_UART_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_UART_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_UART_CONFIG_DEBUG_COLOR
 #define NRFX_UART_CONFIG_DEBUG_COLOR 0
@@ -4506,31 +4506,31 @@
 #define NRFX_USBD_ENABLED 0
 #endif
 //  NRFX_USBD_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_USBD_CONFIG_IRQ_PRIORITY
 #define NRFX_USBD_CONFIG_IRQ_PRIORITY 6
 #endif
 
 //  NRFX_USBD_CONFIG_DMASCHEDULER_MODE  - USBD DMA scheduler working scheme
- 
-// <0=> Prioritized access 
-// <1=> Round Robin 
+
+// <0=> Prioritized access
+// <1=> Round Robin
 
 #ifndef NRFX_USBD_CONFIG_DMASCHEDULER_MODE
 #define NRFX_USBD_CONFIG_DMASCHEDULER_MODE 0
 #endif
 
 //  NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST  - Give priority to isochronous transfers
- 
+
 
 //  This option gives priority to isochronous transfers.
 //  Enabling it assures that isochronous transfers are always processed,
@@ -4543,7 +4543,7 @@
 #endif
 
 //  NRFX_USBD_CONFIG_ISO_IN_ZLP  - Respond to an IN token on ISO IN endpoint with ZLP when no data is ready
- 
+
 
 //  If set, ISO IN endpoint will respond to an IN token with ZLP when no data is ready to be sent.
 //  Else, there will be no response.
@@ -4560,17 +4560,17 @@
 #define NRFX_WDT_ENABLED 0
 #endif
 //  NRFX_WDT_CONFIG_BEHAVIOUR  - WDT behavior in CPU SLEEP or HALT mode
- 
-// <1=> Run in SLEEP, Pause in HALT 
-// <8=> Pause in SLEEP, Run in HALT 
-// <9=> Run in SLEEP and HALT 
-// <0=> Pause in SLEEP and HALT 
+
+// <1=> Run in SLEEP, Pause in HALT
+// <8=> Pause in SLEEP, Run in HALT
+// <9=> Run in SLEEP and HALT
+// <0=> Pause in SLEEP and HALT
 
 #ifndef NRFX_WDT_CONFIG_BEHAVIOUR
 #define NRFX_WDT_CONFIG_BEHAVIOUR 1
 #endif
 
-//  NRFX_WDT_CONFIG_RELOAD_VALUE - Reload value  <15-4294967295> 
+//  NRFX_WDT_CONFIG_RELOAD_VALUE - Reload value  <15-4294967295>
 
 
 #ifndef NRFX_WDT_CONFIG_RELOAD_VALUE
@@ -4578,24 +4578,24 @@
 #endif
 
 //  NRFX_WDT_CONFIG_NO_IRQ  - Remove WDT IRQ handling from WDT driver
- 
-// <0=> Include WDT IRQ handling 
-// <1=> Remove WDT IRQ handling 
+
+// <0=> Include WDT IRQ handling
+// <1=> Remove WDT IRQ handling
 
 #ifndef NRFX_WDT_CONFIG_NO_IRQ
 #define NRFX_WDT_CONFIG_NO_IRQ 0
 #endif
 
 //  NRFX_WDT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef NRFX_WDT_CONFIG_IRQ_PRIORITY
 #define NRFX_WDT_CONFIG_IRQ_PRIORITY 6
@@ -4607,44 +4607,44 @@
 #define NRFX_WDT_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_WDT_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_WDT_CONFIG_LOG_LEVEL
 #define NRFX_WDT_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_WDT_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_WDT_CONFIG_INFO_COLOR
 #define NRFX_WDT_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_WDT_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_WDT_CONFIG_DEBUG_COLOR
 #define NRFX_WDT_CONFIG_DEBUG_COLOR 0
@@ -4660,36 +4660,36 @@
 #define NRF_CLOCK_ENABLED 0
 #endif
 //  CLOCK_CONFIG_LF_SRC  - LF Clock Source
- 
-// <0=> RC 
-// <1=> XTAL 
-// <2=> Synth 
-// <131073=> External Low Swing 
-// <196609=> External Full Swing 
+
+// <0=> RC
+// <1=> XTAL
+// <2=> Synth
+// <131073=> External Low Swing
+// <196609=> External Full Swing
 
 #ifndef CLOCK_CONFIG_LF_SRC
 #define CLOCK_CONFIG_LF_SRC 1
 #endif
 
 //  CLOCK_CONFIG_LF_CAL_ENABLED  - Calibration enable for LF Clock Source
- 
+
 
 #ifndef CLOCK_CONFIG_LF_CAL_ENABLED
 #define CLOCK_CONFIG_LF_CAL_ENABLED 0
 #endif
 
 //  CLOCK_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef CLOCK_CONFIG_IRQ_PRIORITY
 #define CLOCK_CONFIG_IRQ_PRIORITY 6
@@ -4703,45 +4703,45 @@
 #define PDM_ENABLED 0
 #endif
 //  PDM_CONFIG_MODE  - Mode
- 
-// <0=> Stereo 
-// <1=> Mono 
+
+// <0=> Stereo
+// <1=> Mono
 
 #ifndef PDM_CONFIG_MODE
 #define PDM_CONFIG_MODE 1
 #endif
 
 //  PDM_CONFIG_EDGE  - Edge
- 
-// <0=> Left falling 
-// <1=> Left rising 
+
+// <0=> Left falling
+// <1=> Left rising
 
 #ifndef PDM_CONFIG_EDGE
 #define PDM_CONFIG_EDGE 0
 #endif
 
 //  PDM_CONFIG_CLOCK_FREQ  - Clock frequency
- 
-// <134217728=> 1000k 
-// <138412032=> 1032k (default) 
-// <142606336=> 1067k 
+
+// <134217728=> 1000k
+// <138412032=> 1032k (default)
+// <142606336=> 1067k
 
 #ifndef PDM_CONFIG_CLOCK_FREQ
 #define PDM_CONFIG_CLOCK_FREQ 138412032
 #endif
 
 //  PDM_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef PDM_CONFIG_IRQ_PRIORITY
 #define PDM_CONFIG_IRQ_PRIORITY 6
@@ -4755,24 +4755,24 @@
 #define POWER_ENABLED 0
 #endif
 //  POWER_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef POWER_CONFIG_IRQ_PRIORITY
 #define POWER_CONFIG_IRQ_PRIORITY 6
 #endif
 
 //  POWER_CONFIG_DEFAULT_DCDCEN  - The default configuration of main DCDC regulator
- 
+
 
 //  This settings means only that components for DCDC regulator are installed and it can be enabled.
 
@@ -4781,7 +4781,7 @@
 #endif
 
 //  POWER_CONFIG_DEFAULT_DCDCENHV  - The default configuration of High Voltage DCDC regulator
- 
+
 
 //  This settings means only that components for DCDC regulator are installed and it can be enabled.
 
@@ -4792,7 +4792,7 @@
 // 
 
 //  PPI_ENABLED  - nrf_drv_ppi - PPI peripheral driver - legacy layer
- 
+
 
 #ifndef PPI_ENABLED
 #define PPI_ENABLED 0
@@ -4803,28 +4803,28 @@
 #ifndef PWM_ENABLED
 #define PWM_ENABLED 0
 #endif
-//  PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin  <0-31> 
+//  PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin  <0-31>
 
 
 #ifndef PWM_DEFAULT_CONFIG_OUT0_PIN
 #define PWM_DEFAULT_CONFIG_OUT0_PIN 31
 #endif
 
-//  PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin  <0-31> 
+//  PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin  <0-31>
 
 
 #ifndef PWM_DEFAULT_CONFIG_OUT1_PIN
 #define PWM_DEFAULT_CONFIG_OUT1_PIN 31
 #endif
 
-//  PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin  <0-31> 
+//  PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin  <0-31>
 
 
 #ifndef PWM_DEFAULT_CONFIG_OUT2_PIN
 #define PWM_DEFAULT_CONFIG_OUT2_PIN 31
 #endif
 
-//  PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin  <0-31> 
+//  PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin  <0-31>
 
 
 #ifndef PWM_DEFAULT_CONFIG_OUT3_PIN
@@ -4832,94 +4832,94 @@
 #endif
 
 //  PWM_DEFAULT_CONFIG_BASE_CLOCK  - Base clock
- 
-// <0=> 16 MHz 
-// <1=> 8 MHz 
-// <2=> 4 MHz 
-// <3=> 2 MHz 
-// <4=> 1 MHz 
-// <5=> 500 kHz 
-// <6=> 250 kHz 
-// <7=> 125 kHz 
+
+// <0=> 16 MHz
+// <1=> 8 MHz
+// <2=> 4 MHz
+// <3=> 2 MHz
+// <4=> 1 MHz
+// <5=> 500 kHz
+// <6=> 250 kHz
+// <7=> 125 kHz
 
 #ifndef PWM_DEFAULT_CONFIG_BASE_CLOCK
 #define PWM_DEFAULT_CONFIG_BASE_CLOCK 4
 #endif
 
 //  PWM_DEFAULT_CONFIG_COUNT_MODE  - Count mode
- 
-// <0=> Up 
-// <1=> Up and Down 
+
+// <0=> Up
+// <1=> Up and Down
 
 #ifndef PWM_DEFAULT_CONFIG_COUNT_MODE
 #define PWM_DEFAULT_CONFIG_COUNT_MODE 0
 #endif
 
-//  PWM_DEFAULT_CONFIG_TOP_VALUE - Top value 
+//  PWM_DEFAULT_CONFIG_TOP_VALUE - Top value
 #ifndef PWM_DEFAULT_CONFIG_TOP_VALUE
 #define PWM_DEFAULT_CONFIG_TOP_VALUE 1000
 #endif
 
 //  PWM_DEFAULT_CONFIG_LOAD_MODE  - Load mode
- 
-// <0=> Common 
-// <1=> Grouped 
-// <2=> Individual 
-// <3=> Waveform 
+
+// <0=> Common
+// <1=> Grouped
+// <2=> Individual
+// <3=> Waveform
 
 #ifndef PWM_DEFAULT_CONFIG_LOAD_MODE
 #define PWM_DEFAULT_CONFIG_LOAD_MODE 0
 #endif
 
 //  PWM_DEFAULT_CONFIG_STEP_MODE  - Step mode
- 
-// <0=> Auto 
-// <1=> Triggered 
+
+// <0=> Auto
+// <1=> Triggered
 
 #ifndef PWM_DEFAULT_CONFIG_STEP_MODE
 #define PWM_DEFAULT_CONFIG_STEP_MODE 0
 #endif
 
 //  PWM_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef PWM_DEFAULT_CONFIG_IRQ_PRIORITY
 #define PWM_DEFAULT_CONFIG_IRQ_PRIORITY 6
 #endif
 
 //  PWM0_ENABLED  - Enable PWM0 instance
- 
+
 
 #ifndef PWM0_ENABLED
 #define PWM0_ENABLED 0
 #endif
 
 //  PWM1_ENABLED  - Enable PWM1 instance
- 
+
 
 #ifndef PWM1_ENABLED
 #define PWM1_ENABLED 0
 #endif
 
 //  PWM2_ENABLED  - Enable PWM2 instance
- 
+
 
 #ifndef PWM2_ENABLED
 #define PWM2_ENABLED 0
 #endif
 
 //  PWM3_ENABLED  - Enable PWM3 instance
- 
+
 
 #ifndef PWM3_ENABLED
 #define PWM3_ENABLED 0
@@ -4933,96 +4933,96 @@
 #define QDEC_ENABLED 0
 #endif
 //  QDEC_CONFIG_REPORTPER  - Report period
- 
-// <0=> 10 Samples 
-// <1=> 40 Samples 
-// <2=> 80 Samples 
-// <3=> 120 Samples 
-// <4=> 160 Samples 
-// <5=> 200 Samples 
-// <6=> 240 Samples 
-// <7=> 280 Samples 
+
+// <0=> 10 Samples
+// <1=> 40 Samples
+// <2=> 80 Samples
+// <3=> 120 Samples
+// <4=> 160 Samples
+// <5=> 200 Samples
+// <6=> 240 Samples
+// <7=> 280 Samples
 
 #ifndef QDEC_CONFIG_REPORTPER
 #define QDEC_CONFIG_REPORTPER 0
 #endif
 
 //  QDEC_CONFIG_SAMPLEPER  - Sample period
- 
-// <0=> 128 us 
-// <1=> 256 us 
-// <2=> 512 us 
-// <3=> 1024 us 
-// <4=> 2048 us 
-// <5=> 4096 us 
-// <6=> 8192 us 
-// <7=> 16384 us 
+
+// <0=> 128 us
+// <1=> 256 us
+// <2=> 512 us
+// <3=> 1024 us
+// <4=> 2048 us
+// <5=> 4096 us
+// <6=> 8192 us
+// <7=> 16384 us
 
 #ifndef QDEC_CONFIG_SAMPLEPER
 #define QDEC_CONFIG_SAMPLEPER 7
 #endif
 
-//  QDEC_CONFIG_PIO_A - A pin  <0-31> 
+//  QDEC_CONFIG_PIO_A - A pin  <0-31>
 
 
 #ifndef QDEC_CONFIG_PIO_A
 #define QDEC_CONFIG_PIO_A 31
 #endif
 
-//  QDEC_CONFIG_PIO_B - B pin  <0-31> 
+//  QDEC_CONFIG_PIO_B - B pin  <0-31>
 
 
 #ifndef QDEC_CONFIG_PIO_B
 #define QDEC_CONFIG_PIO_B 31
 #endif
 
-//  QDEC_CONFIG_PIO_LED - LED pin  <0-31> 
+//  QDEC_CONFIG_PIO_LED - LED pin  <0-31>
 
 
 #ifndef QDEC_CONFIG_PIO_LED
 #define QDEC_CONFIG_PIO_LED 31
 #endif
 
-//  QDEC_CONFIG_LEDPRE - LED pre 
+//  QDEC_CONFIG_LEDPRE - LED pre
 #ifndef QDEC_CONFIG_LEDPRE
 #define QDEC_CONFIG_LEDPRE 511
 #endif
 
 //  QDEC_CONFIG_LEDPOL  - LED polarity
- 
-// <0=> Active low 
-// <1=> Active high 
+
+// <0=> Active low
+// <1=> Active high
 
 #ifndef QDEC_CONFIG_LEDPOL
 #define QDEC_CONFIG_LEDPOL 1
 #endif
 
 //  QDEC_CONFIG_DBFEN  - Debouncing enable
- 
+
 
 #ifndef QDEC_CONFIG_DBFEN
 #define QDEC_CONFIG_DBFEN 0
 #endif
 
 //  QDEC_CONFIG_SAMPLE_INTEN  - Sample ready interrupt enable
- 
+
 
 #ifndef QDEC_CONFIG_SAMPLE_INTEN
 #define QDEC_CONFIG_SAMPLE_INTEN 0
 #endif
 
 //  QDEC_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef QDEC_CONFIG_IRQ_PRIORITY
 #define QDEC_CONFIG_IRQ_PRIORITY 6
@@ -5035,77 +5035,77 @@
 #ifndef QSPI_ENABLED
 #define QSPI_ENABLED 0
 #endif
-//  QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns).  <0-255> 
+//  QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns).  <0-255>
 
 
 #ifndef QSPI_CONFIG_SCK_DELAY
 #define QSPI_CONFIG_SCK_DELAY 1
 #endif
 
-//  QSPI_CONFIG_XIP_OFFSET - Address offset in the external memory for Execute in Place operation. 
+//  QSPI_CONFIG_XIP_OFFSET - Address offset in the external memory for Execute in Place operation.
 #ifndef QSPI_CONFIG_XIP_OFFSET
 #define QSPI_CONFIG_XIP_OFFSET 0
 #endif
 
 //  QSPI_CONFIG_READOC  - Number of data lines and opcode used for reading.
- 
-// <0=> FastRead 
-// <1=> Read2O 
-// <2=> Read2IO 
-// <3=> Read4O 
-// <4=> Read4IO 
+
+// <0=> FastRead
+// <1=> Read2O
+// <2=> Read2IO
+// <3=> Read4O
+// <4=> Read4IO
 
 #ifndef QSPI_CONFIG_READOC
 #define QSPI_CONFIG_READOC 0
 #endif
 
 //  QSPI_CONFIG_WRITEOC  - Number of data lines and opcode used for writing.
- 
-// <0=> PP 
-// <1=> PP2O 
-// <2=> PP4O 
-// <3=> PP4IO 
+
+// <0=> PP
+// <1=> PP2O
+// <2=> PP4O
+// <3=> PP4IO
 
 #ifndef QSPI_CONFIG_WRITEOC
 #define QSPI_CONFIG_WRITEOC 0
 #endif
 
 //  QSPI_CONFIG_ADDRMODE  - Addressing mode.
- 
-// <0=> 24bit 
-// <1=> 32bit 
+
+// <0=> 24bit
+// <1=> 32bit
 
 #ifndef QSPI_CONFIG_ADDRMODE
 #define QSPI_CONFIG_ADDRMODE 0
 #endif
 
 //  QSPI_CONFIG_MODE  - SPI mode.
- 
-// <0=> Mode 0 
-// <1=> Mode 1 
+
+// <0=> Mode 0
+// <1=> Mode 1
 
 #ifndef QSPI_CONFIG_MODE
 #define QSPI_CONFIG_MODE 0
 #endif
 
 //  QSPI_CONFIG_FREQUENCY  - Frequency divider.
- 
-// <0=> 32MHz/1 
-// <1=> 32MHz/2 
-// <2=> 32MHz/3 
-// <3=> 32MHz/4 
-// <4=> 32MHz/5 
-// <5=> 32MHz/6 
-// <6=> 32MHz/7 
-// <7=> 32MHz/8 
-// <8=> 32MHz/9 
-// <9=> 32MHz/10 
-// <10=> 32MHz/11 
-// <11=> 32MHz/12 
-// <12=> 32MHz/13 
-// <13=> 32MHz/14 
-// <14=> 32MHz/15 
-// <15=> 32MHz/16 
+
+// <0=> 32MHz/1
+// <1=> 32MHz/2
+// <2=> 32MHz/3
+// <3=> 32MHz/4
+// <4=> 32MHz/5
+// <5=> 32MHz/6
+// <6=> 32MHz/7
+// <7=> 32MHz/8
+// <8=> 32MHz/9
+// <9=> 32MHz/10
+// <10=> 32MHz/11
+// <11=> 32MHz/12
+// <12=> 32MHz/13
+// <13=> 32MHz/14
+// <14=> 32MHz/15
+// <15=> 32MHz/16
 
 #ifndef QSPI_CONFIG_FREQUENCY
 #define QSPI_CONFIG_FREQUENCY 15
@@ -5142,17 +5142,17 @@
 #endif
 
 //  QSPI_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef QSPI_CONFIG_IRQ_PRIORITY
 #define QSPI_CONFIG_IRQ_PRIORITY 6
@@ -5166,29 +5166,29 @@
 #define RNG_ENABLED 0
 #endif
 //  RNG_CONFIG_ERROR_CORRECTION  - Error correction
- 
+
 
 #ifndef RNG_CONFIG_ERROR_CORRECTION
 #define RNG_CONFIG_ERROR_CORRECTION 1
 #endif
 
-//  RNG_CONFIG_POOL_SIZE - Pool size 
+//  RNG_CONFIG_POOL_SIZE - Pool size
 #ifndef RNG_CONFIG_POOL_SIZE
 #define RNG_CONFIG_POOL_SIZE 64
 #endif
 
 //  RNG_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef RNG_CONFIG_IRQ_PRIORITY
 #define RNG_CONFIG_IRQ_PRIORITY 6
@@ -5201,7 +5201,7 @@
 #ifndef RTC_ENABLED
 #define RTC_ENABLED 0
 #endif
-//  RTC_DEFAULT_CONFIG_FREQUENCY - Frequency  <16-32768> 
+//  RTC_DEFAULT_CONFIG_FREQUENCY - Frequency  <16-32768>
 
 
 #ifndef RTC_DEFAULT_CONFIG_FREQUENCY
@@ -5209,51 +5209,51 @@
 #endif
 
 //  RTC_DEFAULT_CONFIG_RELIABLE  - Ensures safe compare event triggering
- 
+
 
 #ifndef RTC_DEFAULT_CONFIG_RELIABLE
 #define RTC_DEFAULT_CONFIG_RELIABLE 0
 #endif
 
 //  RTC_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef RTC_DEFAULT_CONFIG_IRQ_PRIORITY
 #define RTC_DEFAULT_CONFIG_IRQ_PRIORITY 6
 #endif
 
 //  RTC0_ENABLED  - Enable RTC0 instance
- 
+
 
 #ifndef RTC0_ENABLED
 #define RTC0_ENABLED 0
 #endif
 
 //  RTC1_ENABLED  - Enable RTC1 instance
- 
+
 
 #ifndef RTC1_ENABLED
 #define RTC1_ENABLED 0
 #endif
 
 //  RTC2_ENABLED  - Enable RTC2 instance
- 
+
 
 #ifndef RTC2_ENABLED
 #define RTC2_ENABLED 0
 #endif
 
-//  NRF_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt 
+//  NRF_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt
 #ifndef NRF_MAXIMUM_LATENCY_US
 #define NRF_MAXIMUM_LATENCY_US 2000
 #endif
@@ -5266,51 +5266,51 @@
 #define SAADC_ENABLED 0
 #endif
 //  SAADC_CONFIG_RESOLUTION  - Resolution
- 
-// <0=> 8 bit 
-// <1=> 10 bit 
-// <2=> 12 bit 
-// <3=> 14 bit 
+
+// <0=> 8 bit
+// <1=> 10 bit
+// <2=> 12 bit
+// <3=> 14 bit
 
 #ifndef SAADC_CONFIG_RESOLUTION
 #define SAADC_CONFIG_RESOLUTION 1
 #endif
 
 //  SAADC_CONFIG_OVERSAMPLE  - Sample period
- 
-// <0=> Disabled 
-// <1=> 2x 
-// <2=> 4x 
-// <3=> 8x 
-// <4=> 16x 
-// <5=> 32x 
-// <6=> 64x 
-// <7=> 128x 
-// <8=> 256x 
+
+// <0=> Disabled
+// <1=> 2x
+// <2=> 4x
+// <3=> 8x
+// <4=> 16x
+// <5=> 32x
+// <6=> 64x
+// <7=> 128x
+// <8=> 256x
 
 #ifndef SAADC_CONFIG_OVERSAMPLE
 #define SAADC_CONFIG_OVERSAMPLE 0
 #endif
 
 //  SAADC_CONFIG_LP_MODE  - Enabling low power mode
- 
+
 
 #ifndef SAADC_CONFIG_LP_MODE
 #define SAADC_CONFIG_LP_MODE 0
 #endif
 
 //  SAADC_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef SAADC_CONFIG_IRQ_PRIORITY
 #define SAADC_CONFIG_IRQ_PRIORITY 6
@@ -5324,50 +5324,50 @@
 #define SPIS_ENABLED 0
 #endif
 //  SPIS_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef SPIS_DEFAULT_CONFIG_IRQ_PRIORITY
 #define SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 6
 #endif
 
 //  SPIS_DEFAULT_MODE  - Mode
- 
-// <0=> MODE_0 
-// <1=> MODE_1 
-// <2=> MODE_2 
-// <3=> MODE_3 
+
+// <0=> MODE_0
+// <1=> MODE_1
+// <2=> MODE_2
+// <3=> MODE_3
 
 #ifndef SPIS_DEFAULT_MODE
 #define SPIS_DEFAULT_MODE 0
 #endif
 
 //  SPIS_DEFAULT_BIT_ORDER  - SPIS default bit order
- 
-// <0=> MSB first 
-// <1=> LSB first 
+
+// <0=> MSB first
+// <1=> LSB first
 
 #ifndef SPIS_DEFAULT_BIT_ORDER
 #define SPIS_DEFAULT_BIT_ORDER 0
 #endif
 
-//  SPIS_DEFAULT_DEF - SPIS default DEF character  <0-255> 
+//  SPIS_DEFAULT_DEF - SPIS default DEF character  <0-255>
 
 
 #ifndef SPIS_DEFAULT_DEF
 #define SPIS_DEFAULT_DEF 255
 #endif
 
-//  SPIS_DEFAULT_ORC - SPIS default ORC character  <0-255> 
+//  SPIS_DEFAULT_ORC - SPIS default ORC character  <0-255>
 
 
 #ifndef SPIS_DEFAULT_ORC
@@ -5375,21 +5375,21 @@
 #endif
 
 //  SPIS0_ENABLED  - Enable SPIS0 instance
- 
+
 
 #ifndef SPIS0_ENABLED
 #define SPIS0_ENABLED 0
 #endif
 
 //  SPIS1_ENABLED  - Enable SPIS1 instance
- 
+
 
 #ifndef SPIS1_ENABLED
 #define SPIS1_ENABLED 0
 #endif
 
 //  SPIS2_ENABLED  - Enable SPIS2 instance
- 
+
 
 #ifndef SPIS2_ENABLED
 #define SPIS2_ENABLED 0
@@ -5403,27 +5403,27 @@
 #define SPI_ENABLED 0
 #endif
 //  SPI_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef SPI_DEFAULT_CONFIG_IRQ_PRIORITY
 #define SPI_DEFAULT_CONFIG_IRQ_PRIORITY 6
 #endif
 
 //  NRF_SPI_DRV_MISO_PULLUP_CFG  - MISO PIN pull-up configuration.
- 
-// <0=> NRF_GPIO_PIN_NOPULL 
-// <1=> NRF_GPIO_PIN_PULLDOWN 
-// <3=> NRF_GPIO_PIN_PULLUP 
+
+// <0=> NRF_GPIO_PIN_NOPULL
+// <1=> NRF_GPIO_PIN_PULLDOWN
+// <3=> NRF_GPIO_PIN_PULLUP
 
 #ifndef NRF_SPI_DRV_MISO_PULLUP_CFG
 #define NRF_SPI_DRV_MISO_PULLUP_CFG 1
@@ -5435,7 +5435,7 @@
 #define SPI0_ENABLED 0
 #endif
 //  SPI0_USE_EASY_DMA  - Use EasyDMA
- 
+
 
 #ifndef SPI0_USE_EASY_DMA
 #define SPI0_USE_EASY_DMA 1
@@ -5449,7 +5449,7 @@
 #define SPI1_ENABLED 0
 #endif
 //  SPI1_USE_EASY_DMA  - Use EasyDMA
- 
+
 
 #ifndef SPI1_USE_EASY_DMA
 #define SPI1_USE_EASY_DMA 1
@@ -5463,7 +5463,7 @@
 #define SPI2_ENABLED 0
 #endif
 //  SPI2_USE_EASY_DMA  - Use EasyDMA
- 
+
 
 #ifndef SPI2_USE_EASY_DMA
 #define SPI2_USE_EASY_DMA 1
@@ -5479,89 +5479,89 @@
 #define TIMER_ENABLED 0
 #endif
 //  TIMER_DEFAULT_CONFIG_FREQUENCY  - Timer frequency if in Timer mode
- 
-// <0=> 16 MHz 
-// <1=> 8 MHz 
-// <2=> 4 MHz 
-// <3=> 2 MHz 
-// <4=> 1 MHz 
-// <5=> 500 kHz 
-// <6=> 250 kHz 
-// <7=> 125 kHz 
-// <8=> 62.5 kHz 
-// <9=> 31.25 kHz 
+
+// <0=> 16 MHz
+// <1=> 8 MHz
+// <2=> 4 MHz
+// <3=> 2 MHz
+// <4=> 1 MHz
+// <5=> 500 kHz
+// <6=> 250 kHz
+// <7=> 125 kHz
+// <8=> 62.5 kHz
+// <9=> 31.25 kHz
 
 #ifndef TIMER_DEFAULT_CONFIG_FREQUENCY
 #define TIMER_DEFAULT_CONFIG_FREQUENCY 0
 #endif
 
 //  TIMER_DEFAULT_CONFIG_MODE  - Timer mode or operation
- 
-// <0=> Timer 
-// <1=> Counter 
+
+// <0=> Timer
+// <1=> Counter
 
 #ifndef TIMER_DEFAULT_CONFIG_MODE
 #define TIMER_DEFAULT_CONFIG_MODE 0
 #endif
 
 //  TIMER_DEFAULT_CONFIG_BIT_WIDTH  - Timer counter bit width
- 
-// <0=> 16 bit 
-// <1=> 8 bit 
-// <2=> 24 bit 
-// <3=> 32 bit 
+
+// <0=> 16 bit
+// <1=> 8 bit
+// <2=> 24 bit
+// <3=> 32 bit
 
 #ifndef TIMER_DEFAULT_CONFIG_BIT_WIDTH
 #define TIMER_DEFAULT_CONFIG_BIT_WIDTH 0
 #endif
 
 //  TIMER_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef TIMER_DEFAULT_CONFIG_IRQ_PRIORITY
 #define TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 6
 #endif
 
 //  TIMER0_ENABLED  - Enable TIMER0 instance
- 
+
 
 #ifndef TIMER0_ENABLED
 #define TIMER0_ENABLED 0
 #endif
 
 //  TIMER1_ENABLED  - Enable TIMER1 instance
- 
+
 
 #ifndef TIMER1_ENABLED
 #define TIMER1_ENABLED 0
 #endif
 
 //  TIMER2_ENABLED  - Enable TIMER2 instance
- 
+
 
 #ifndef TIMER2_ENABLED
 #define TIMER2_ENABLED 0
 #endif
 
 //  TIMER3_ENABLED  - Enable TIMER3 instance
- 
+
 
 #ifndef TIMER3_ENABLED
 #define TIMER3_ENABLED 0
 #endif
 
 //  TIMER4_ENABLED  - Enable TIMER4 instance
- 
+
 
 #ifndef TIMER4_ENABLED
 #define TIMER4_ENABLED 0
@@ -5575,21 +5575,21 @@
 #define TWIS_ENABLED 0
 #endif
 //  TWIS0_ENABLED  - Enable TWIS0 instance
- 
+
 
 #ifndef TWIS0_ENABLED
 #define TWIS0_ENABLED 0
 #endif
 
 //  TWIS1_ENABLED  - Enable TWIS1 instance
- 
+
 
 #ifndef TWIS1_ENABLED
 #define TWIS1_ENABLED 0
 #endif
 
 //  TWIS_ASSUME_INIT_AFTER_RESET_ONLY  - Assume that any instance would be initialized only once
- 
+
 
 //  Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code.
 
@@ -5598,7 +5598,7 @@
 #endif
 
 //  TWIS_NO_SYNC_MODE  - Remove support for synchronous mode
- 
+
 
 //  Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources.
 
@@ -5606,48 +5606,48 @@
 #define TWIS_NO_SYNC_MODE 0
 #endif
 
-//  TWIS_DEFAULT_CONFIG_ADDR0 - Address0 
+//  TWIS_DEFAULT_CONFIG_ADDR0 - Address0
 #ifndef TWIS_DEFAULT_CONFIG_ADDR0
 #define TWIS_DEFAULT_CONFIG_ADDR0 0
 #endif
 
-//  TWIS_DEFAULT_CONFIG_ADDR1 - Address1 
+//  TWIS_DEFAULT_CONFIG_ADDR1 - Address1
 #ifndef TWIS_DEFAULT_CONFIG_ADDR1
 #define TWIS_DEFAULT_CONFIG_ADDR1 0
 #endif
 
 //  TWIS_DEFAULT_CONFIG_SCL_PULL  - SCL pin pull configuration
- 
-// <0=> Disabled 
-// <1=> Pull down 
-// <3=> Pull up 
+
+// <0=> Disabled
+// <1=> Pull down
+// <3=> Pull up
 
 #ifndef TWIS_DEFAULT_CONFIG_SCL_PULL
 #define TWIS_DEFAULT_CONFIG_SCL_PULL 0
 #endif
 
 //  TWIS_DEFAULT_CONFIG_SDA_PULL  - SDA pin pull configuration
- 
-// <0=> Disabled 
-// <1=> Pull down 
-// <3=> Pull up 
+
+// <0=> Disabled
+// <1=> Pull down
+// <3=> Pull up
 
 #ifndef TWIS_DEFAULT_CONFIG_SDA_PULL
 #define TWIS_DEFAULT_CONFIG_SDA_PULL 0
 #endif
 
 //  TWIS_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef TWIS_DEFAULT_CONFIG_IRQ_PRIORITY
 #define TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 6
@@ -5661,41 +5661,41 @@
 #define TWI_ENABLED 0
 #endif
 //  TWI_DEFAULT_CONFIG_FREQUENCY  - Frequency
- 
-// <26738688=> 100k 
-// <67108864=> 250k 
-// <104857600=> 400k 
+
+// <26738688=> 100k
+// <67108864=> 250k
+// <104857600=> 400k
 
 #ifndef TWI_DEFAULT_CONFIG_FREQUENCY
 #define TWI_DEFAULT_CONFIG_FREQUENCY 26738688
 #endif
 
 //  TWI_DEFAULT_CONFIG_CLR_BUS_INIT  - Enables bus clearing procedure during init
- 
+
 
 #ifndef TWI_DEFAULT_CONFIG_CLR_BUS_INIT
 #define TWI_DEFAULT_CONFIG_CLR_BUS_INIT 0
 #endif
 
 //  TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT  - Enables bus holding after uninit
- 
+
 
 #ifndef TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT
 #define TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0
 #endif
 
 //  TWI_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef TWI_DEFAULT_CONFIG_IRQ_PRIORITY
 #define TWI_DEFAULT_CONFIG_IRQ_PRIORITY 6
@@ -5707,7 +5707,7 @@
 #define TWI0_ENABLED 0
 #endif
 //  TWI0_USE_EASY_DMA  - Use EasyDMA (if present)
- 
+
 
 #ifndef TWI0_USE_EASY_DMA
 #define TWI0_USE_EASY_DMA 0
@@ -5721,7 +5721,7 @@
 #define TWI1_ENABLED 0
 #endif
 //  TWI1_USE_EASY_DMA  - Use EasyDMA (if present)
- 
+
 
 #ifndef TWI1_USE_EASY_DMA
 #define TWI1_USE_EASY_DMA 0
@@ -5737,72 +5737,72 @@
 #define UART_ENABLED 0
 #endif
 //  UART_DEFAULT_CONFIG_HWFC  - Hardware Flow Control
- 
-// <0=> Disabled 
-// <1=> Enabled 
+
+// <0=> Disabled
+// <1=> Enabled
 
 #ifndef UART_DEFAULT_CONFIG_HWFC
 #define UART_DEFAULT_CONFIG_HWFC 0
 #endif
 
 //  UART_DEFAULT_CONFIG_PARITY  - Parity
- 
-// <0=> Excluded 
-// <14=> Included 
+
+// <0=> Excluded
+// <14=> Included
 
 #ifndef UART_DEFAULT_CONFIG_PARITY
 #define UART_DEFAULT_CONFIG_PARITY 0
 #endif
 
 //  UART_DEFAULT_CONFIG_BAUDRATE  - Default Baudrate
- 
-// <323584=> 1200 baud 
-// <643072=> 2400 baud 
-// <1290240=> 4800 baud 
-// <2576384=> 9600 baud 
-// <3862528=> 14400 baud 
-// <5152768=> 19200 baud 
-// <7716864=> 28800 baud 
-// <10289152=> 38400 baud 
-// <15400960=> 57600 baud 
-// <20615168=> 76800 baud 
-// <30801920=> 115200 baud 
-// <61865984=> 230400 baud 
-// <67108864=> 250000 baud 
-// <121634816=> 460800 baud 
-// <251658240=> 921600 baud 
-// <268435456=> 1000000 baud 
+
+// <323584=> 1200 baud
+// <643072=> 2400 baud
+// <1290240=> 4800 baud
+// <2576384=> 9600 baud
+// <3862528=> 14400 baud
+// <5152768=> 19200 baud
+// <7716864=> 28800 baud
+// <10289152=> 38400 baud
+// <15400960=> 57600 baud
+// <20615168=> 76800 baud
+// <30801920=> 115200 baud
+// <61865984=> 230400 baud
+// <67108864=> 250000 baud
+// <121634816=> 460800 baud
+// <251658240=> 921600 baud
+// <268435456=> 1000000 baud
 
 #ifndef UART_DEFAULT_CONFIG_BAUDRATE
 #define UART_DEFAULT_CONFIG_BAUDRATE 30801920
 #endif
 
 //  UART_DEFAULT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef UART_DEFAULT_CONFIG_IRQ_PRIORITY
 #define UART_DEFAULT_CONFIG_IRQ_PRIORITY 6
 #endif
 
 //  UART_EASY_DMA_SUPPORT  - Driver supporting EasyDMA
- 
+
 
 #ifndef UART_EASY_DMA_SUPPORT
 #define UART_EASY_DMA_SUPPORT 1
 #endif
 
 //  UART_LEGACY_SUPPORT  - Driver supporting Legacy mode
- 
+
 
 #ifndef UART_LEGACY_SUPPORT
 #define UART_LEGACY_SUPPORT 1
@@ -5814,7 +5814,7 @@
 #define UART0_ENABLED 0
 #endif
 //  UART0_CONFIG_USE_EASY_DMA  - Default setting for using EasyDMA
- 
+
 
 #ifndef UART0_CONFIG_USE_EASY_DMA
 #define UART0_CONFIG_USE_EASY_DMA 1
@@ -5837,33 +5837,33 @@
 #define USBD_ENABLED 0
 #endif
 //  USBD_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef USBD_CONFIG_IRQ_PRIORITY
 #define USBD_CONFIG_IRQ_PRIORITY 6
 #endif
 
 //  USBD_CONFIG_DMASCHEDULER_MODE  - USBD SMA scheduler working scheme
- 
-// <0=> Prioritized access 
-// <1=> Round Robin 
+
+// <0=> Prioritized access
+// <1=> Round Robin
 
 #ifndef USBD_CONFIG_DMASCHEDULER_MODE
 #define USBD_CONFIG_DMASCHEDULER_MODE 0
 #endif
 
 //  USBD_CONFIG_DMASCHEDULER_ISO_BOOST  - Give priority to isochronous transfers
- 
+
 
 //  This option gives priority to isochronous transfers.
 //  Enabling it assures that isochronous transfers are always processed,
@@ -5876,7 +5876,7 @@
 #endif
 
 //  USBD_CONFIG_ISO_IN_ZLP  - Respond to an IN token on ISO IN endpoint with ZLP when no data is ready
- 
+
 
 //  If set, ISO IN endpoint will respond to an IN token with ZLP when no data is ready to be sent.
 //  Else, there will be no response.
@@ -5894,17 +5894,17 @@
 #define WDT_ENABLED 0
 #endif
 //  WDT_CONFIG_BEHAVIOUR  - WDT behavior in CPU SLEEP or HALT mode
- 
-// <1=> Run in SLEEP, Pause in HALT 
-// <8=> Pause in SLEEP, Run in HALT 
-// <9=> Run in SLEEP and HALT 
-// <0=> Pause in SLEEP and HALT 
+
+// <1=> Run in SLEEP, Pause in HALT
+// <8=> Pause in SLEEP, Run in HALT
+// <9=> Run in SLEEP and HALT
+// <0=> Pause in SLEEP and HALT
 
 #ifndef WDT_CONFIG_BEHAVIOUR
 #define WDT_CONFIG_BEHAVIOUR 1
 #endif
 
-//  WDT_CONFIG_RELOAD_VALUE - Reload value  <15-4294967295> 
+//  WDT_CONFIG_RELOAD_VALUE - Reload value  <15-4294967295>
 
 
 #ifndef WDT_CONFIG_RELOAD_VALUE
@@ -5912,17 +5912,17 @@
 #endif
 
 //  WDT_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef WDT_CONFIG_IRQ_PRIORITY
 #define WDT_CONFIG_IRQ_PRIORITY 6
@@ -5930,34 +5930,34 @@
 
 // 
 
-//  
+// 
 //==========================================================
 
-//  nRF_Drivers_External 
+//  nRF_Drivers_External
 
 //==========================================================
 //  NRF_TWI_SENSOR_ENABLED  - nrf_twi_sensor - nRF TWI Sensor module
- 
+
 
 #ifndef NRF_TWI_SENSOR_ENABLED
 #define NRF_TWI_SENSOR_ENABLED 0
 #endif
 
-//  
+// 
 //==========================================================
 
-//  nRF_Libraries 
+//  nRF_Libraries
 
 //==========================================================
 //  APP_GPIOTE_ENABLED  - app_gpiote - GPIOTE events dispatcher
- 
+
 
 #ifndef APP_GPIOTE_ENABLED
 #define APP_GPIOTE_ENABLED 0
 #endif
 
 //  APP_PWM_ENABLED  - app_pwm - PWM functionality
- 
+
 
 #ifndef APP_PWM_ENABLED
 #define APP_PWM_ENABLED 0
@@ -5969,14 +5969,14 @@
 #define APP_SCHEDULER_ENABLED 0
 #endif
 //  APP_SCHEDULER_WITH_PAUSE  - Enabling pause feature
- 
+
 
 #ifndef APP_SCHEDULER_WITH_PAUSE
 #define APP_SCHEDULER_WITH_PAUSE 0
 #endif
 
 //  APP_SCHEDULER_WITH_PROFILER  - Enabling scheduler profiling
- 
+
 
 #ifndef APP_SCHEDULER_WITH_PROFILER
 #define APP_SCHEDULER_WITH_PROFILER 0
@@ -5990,38 +5990,38 @@
 #define APP_SDCARD_ENABLED 0
 #endif
 //  APP_SDCARD_SPI_INSTANCE  - SPI instance used
- 
-// <0=> 0 
-// <1=> 1 
-// <2=> 2 
+
+// <0=> 0
+// <1=> 1
+// <2=> 2
 
 #ifndef APP_SDCARD_SPI_INSTANCE
 #define APP_SDCARD_SPI_INSTANCE 0
 #endif
 
 //  APP_SDCARD_FREQ_INIT  - SPI frequency
- 
-// <33554432=> 125 kHz 
-// <67108864=> 250 kHz 
-// <134217728=> 500 kHz 
-// <268435456=> 1 MHz 
-// <536870912=> 2 MHz 
-// <1073741824=> 4 MHz 
-// <2147483648=> 8 MHz 
+
+// <33554432=> 125 kHz
+// <67108864=> 250 kHz
+// <134217728=> 500 kHz
+// <268435456=> 1 MHz
+// <536870912=> 2 MHz
+// <1073741824=> 4 MHz
+// <2147483648=> 8 MHz
 
 #ifndef APP_SDCARD_FREQ_INIT
 #define APP_SDCARD_FREQ_INIT 67108864
 #endif
 
 //  APP_SDCARD_FREQ_DATA  - SPI frequency
- 
-// <33554432=> 125 kHz 
-// <67108864=> 250 kHz 
-// <134217728=> 500 kHz 
-// <268435456=> 1 MHz 
-// <536870912=> 2 MHz 
-// <1073741824=> 4 MHz 
-// <2147483648=> 8 MHz 
+
+// <33554432=> 125 kHz
+// <67108864=> 250 kHz
+// <134217728=> 500 kHz
+// <268435456=> 1 MHz
+// <536870912=> 2 MHz
+// <1073741824=> 4 MHz
+// <2147483648=> 8 MHz
 
 #ifndef APP_SDCARD_FREQ_DATA
 #define APP_SDCARD_FREQ_DATA 1073741824
@@ -6035,36 +6035,36 @@
 #define APP_TIMER_ENABLED 0
 #endif
 //  APP_TIMER_CONFIG_RTC_FREQUENCY  - Configure RTC prescaler.
- 
-// <0=> 32768 Hz 
-// <1=> 16384 Hz 
-// <3=> 8192 Hz 
-// <7=> 4096 Hz 
-// <15=> 2048 Hz 
-// <31=> 1024 Hz 
+
+// <0=> 32768 Hz
+// <1=> 16384 Hz
+// <3=> 8192 Hz
+// <7=> 4096 Hz
+// <15=> 2048 Hz
+// <31=> 1024 Hz
 
 #ifndef APP_TIMER_CONFIG_RTC_FREQUENCY
 #define APP_TIMER_CONFIG_RTC_FREQUENCY 1
 #endif
 
 //  APP_TIMER_CONFIG_IRQ_PRIORITY  - Interrupt priority
- 
+
 
 //  Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
-// <0=> 0 (highest) 
-// <1=> 1 
-// <2=> 2 
-// <3=> 3 
-// <4=> 4 
-// <5=> 5 
-// <6=> 6 
-// <7=> 7 
+// <0=> 0 (highest)
+// <1=> 1
+// <2=> 2
+// <3=> 3
+// <4=> 4
+// <5=> 5
+// <6=> 6
+// <7=> 7
 
 #ifndef APP_TIMER_CONFIG_IRQ_PRIORITY
 #define APP_TIMER_CONFIG_IRQ_PRIORITY 6
 #endif
 
-//  APP_TIMER_CONFIG_OP_QUEUE_SIZE - Capacity of timer requests queue. 
+//  APP_TIMER_CONFIG_OP_QUEUE_SIZE - Capacity of timer requests queue.
 //  Size of the queue depends on how many timers are used
 //  in the system, how often timers are started and overall
 //  system latency. If queue size is too small app_timer calls
@@ -6075,14 +6075,14 @@
 #endif
 
 //  APP_TIMER_CONFIG_USE_SCHEDULER  - Enable scheduling app_timer events to app_scheduler
- 
+
 
 #ifndef APP_TIMER_CONFIG_USE_SCHEDULER
 #define APP_TIMER_CONFIG_USE_SCHEDULER 0
 #endif
 
 //  APP_TIMER_KEEPS_RTC_ACTIVE  - Enable RTC always on
- 
+
 
 //  If option is enabled RTC is kept running even if there is no active timers.
 //  This option can be used when app_timer is used for timestamping.
@@ -6091,7 +6091,7 @@
 #define APP_TIMER_KEEPS_RTC_ACTIVE 0
 #endif
 
-//  APP_TIMER_SAFE_WINDOW_MS - Maximum possible latency (in milliseconds) of handling app_timer event. 
+//  APP_TIMER_SAFE_WINDOW_MS - Maximum possible latency (in milliseconds) of handling app_timer event.
 //  Maximum possible timeout that can be set is reduced by safe window.
 //  Example: RTC frequency 16384 Hz, maximum possible timeout 1024 seconds - APP_TIMER_SAFE_WINDOW_MS.
 //  Since RTC is not stopped when processor is halted in debugging session, this value
@@ -6106,26 +6106,26 @@
 
 //==========================================================
 //  APP_TIMER_WITH_PROFILER  - Enable app_timer profiling
- 
+
 
 #ifndef APP_TIMER_WITH_PROFILER
 #define APP_TIMER_WITH_PROFILER 0
 #endif
 
 //  APP_TIMER_CONFIG_SWI_NUMBER  - Configure SWI instance used.
- 
+
 
 #ifndef APP_TIMER_CONFIG_SWI_NUMBER
 #define APP_TIMER_CONFIG_SWI_NUMBER 0
 #endif
 
-//  
+// 
 //==========================================================
 
 // 
 
 //  APP_USBD_AUDIO_ENABLED  - app_usbd_audio - USB AUDIO class
- 
+
 
 #ifndef APP_USBD_AUDIO_ENABLED
 #define APP_USBD_AUDIO_ENABLED 0
@@ -6136,7 +6136,7 @@
 #ifndef APP_USBD_ENABLED
 #define APP_USBD_ENABLED 0
 #endif
-//  APP_USBD_VID - Vendor ID.  <0x0000-0xFFFF> 
+//  APP_USBD_VID - Vendor ID.  <0x0000-0xFFFF>
 
 
 //  Note: This value is not editable in Configuration Wizard.
@@ -6146,7 +6146,7 @@
 #define APP_USBD_VID 0
 #endif
 
-//  APP_USBD_PID - Product ID.  <0x0000-0xFFFF> 
+//  APP_USBD_PID - Product ID.  <0x0000-0xFFFF>
 
 
 //  Note: This value is not editable in Configuration Wizard.
@@ -6156,7 +6156,7 @@
 #define APP_USBD_PID 0
 #endif
 
-//  APP_USBD_DEVICE_VER_MAJOR - Major device version  <0-99> 
+//  APP_USBD_DEVICE_VER_MAJOR - Major device version  <0-99>
 
 
 //  Major device version, will be converted automatically to BCD notation. Use just decimal values.
@@ -6165,7 +6165,7 @@
 #define APP_USBD_DEVICE_VER_MAJOR 1
 #endif
 
-//  APP_USBD_DEVICE_VER_MINOR - Minor device version  <0-9> 
+//  APP_USBD_DEVICE_VER_MINOR - Minor device version  <0-9>
 
 
 //  Minor device version, will be converted automatically to BCD notation. Use just decimal values.
@@ -6174,7 +6174,7 @@
 #define APP_USBD_DEVICE_VER_MINOR 0
 #endif
 
-//  APP_USBD_DEVICE_VER_SUB - Sub-minor device version  <0-9> 
+//  APP_USBD_DEVICE_VER_SUB - Sub-minor device version  <0-9>
 
 
 //  Sub-minor device version, will be converted automatically to BCD notation. Use just decimal values.
@@ -6184,13 +6184,13 @@
 #endif
 
 //  APP_USBD_CONFIG_SELF_POWERED  - Self-powered device, as opposed to bus-powered.
- 
+
 
 #ifndef APP_USBD_CONFIG_SELF_POWERED
 #define APP_USBD_CONFIG_SELF_POWERED 1
 #endif
 
-//  APP_USBD_CONFIG_MAX_POWER - MaxPower field in configuration descriptor in milliamps.  <0-500> 
+//  APP_USBD_CONFIG_MAX_POWER - MaxPower field in configuration descriptor in milliamps.  <0-500>
 
 
 #ifndef APP_USBD_CONFIG_MAX_POWER
@@ -6198,7 +6198,7 @@
 #endif
 
 //  APP_USBD_CONFIG_POWER_EVENTS_PROCESS  - Process power events.
- 
+
 
 //  Enable processing power events in USB event handler.
 
@@ -6216,7 +6216,7 @@
 #ifndef APP_USBD_CONFIG_EVENT_QUEUE_ENABLE
 #define APP_USBD_CONFIG_EVENT_QUEUE_ENABLE 1
 #endif
-//  APP_USBD_CONFIG_EVENT_QUEUE_SIZE - The size of the event queue.  <16-64> 
+//  APP_USBD_CONFIG_EVENT_QUEUE_SIZE - The size of the event queue.  <16-64>
 
 
 //  The size of the queue for the events that would be processed in the main loop.
@@ -6226,15 +6226,15 @@
 #endif
 
 //  APP_USBD_CONFIG_SOF_HANDLING_MODE  - Change SOF events handling mode.
- 
+
 
 //  Normal queue   - SOF events are pushed normally into the event queue.
 //  Compress queue - SOF events are counted and binded with other events or executed when the queue is empty.
 //                   This prevents the queue from filling up with SOF events.
 //  Interrupt      - SOF events are processed in interrupt.
-// <0=> Normal queue 
-// <1=> Compress queue 
-// <2=> Interrupt 
+// <0=> Normal queue
+// <1=> Compress queue
+// <2=> Interrupt
 
 #ifndef APP_USBD_CONFIG_SOF_HANDLING_MODE
 #define APP_USBD_CONFIG_SOF_HANDLING_MODE 1
@@ -6243,19 +6243,19 @@
 // 
 
 //  APP_USBD_CONFIG_SOF_TIMESTAMP_PROVIDE  - Provide a function that generates timestamps for logs based on the current SOF.
- 
 
-//  The function app_usbd_sof_timestamp_get is implemented if the logger is enabled. 
-//  Use it when initializing the logger. 
-//  SOF processing is always enabled when this configuration parameter is active. 
-//  Note: This option is configured outside of APP_USBD_CONFIG_LOG_ENABLED. 
-//  This means that it works even if the logging in this very module is disabled. 
+
+//  The function app_usbd_sof_timestamp_get is implemented if the logger is enabled.
+//  Use it when initializing the logger.
+//  SOF processing is always enabled when this configuration parameter is active.
+//  Note: This option is configured outside of APP_USBD_CONFIG_LOG_ENABLED.
+//  This means that it works even if the logging in this very module is disabled.
 
 #ifndef APP_USBD_CONFIG_SOF_TIMESTAMP_PROVIDE
 #define APP_USBD_CONFIG_SOF_TIMESTAMP_PROVIDE 0
 #endif
 
-//  APP_USBD_CONFIG_DESC_STRING_SIZE - Maximum size of the NULL-terminated string of the string descriptor.  <31-254> 
+//  APP_USBD_CONFIG_DESC_STRING_SIZE - Maximum size of the NULL-terminated string of the string descriptor.  <31-254>
 
 
 //  31 characters can be stored in the internal USB buffer used for transfers.
@@ -6266,7 +6266,7 @@
 #endif
 
 //  APP_USBD_CONFIG_DESC_STRING_UTF_ENABLED  - Enable UTF8 conversion.
- 
+
 
 //  Enable UTF8-encoded characters. In normal processing, only ASCII characters are available.
 
@@ -6290,7 +6290,7 @@
 #define APP_USBD_STRING_ID_MANUFACTURER 1
 #endif
 //  APP_USBD_STRINGS_MANUFACTURER_EXTERN  - Define whether @ref APP_USBD_STRINGS_MANUFACTURER is created by macro or declared as a global variable.
- 
+
 
 #ifndef APP_USBD_STRINGS_MANUFACTURER_EXTERN
 #define APP_USBD_STRINGS_MANUFACTURER_EXTERN 0
@@ -6320,7 +6320,7 @@
 #define APP_USBD_STRING_ID_PRODUCT 2
 #endif
 //  APP_USBD_STRINGS_PRODUCT_EXTERN  - Define whether @ref APP_USBD_STRINGS_PRODUCT is created by macro or declared as a global variable.
- 
+
 
 #ifndef APP_USBD_STRINGS_PRODUCT_EXTERN
 #define APP_USBD_STRINGS_PRODUCT_EXTERN 0
@@ -6344,7 +6344,7 @@
 #define APP_USBD_STRING_ID_SERIAL 3
 #endif
 //  APP_USBD_STRING_SERIAL_EXTERN  - Define whether @ref APP_USBD_STRING_SERIAL is created by macro or declared as a global variable.
- 
+
 
 #ifndef APP_USBD_STRING_SERIAL_EXTERN
 #define APP_USBD_STRING_SERIAL_EXTERN 0
@@ -6368,7 +6368,7 @@
 #define APP_USBD_STRING_ID_CONFIGURATION 4
 #endif
 //  APP_USBD_STRING_CONFIGURATION_EXTERN  - Define whether @ref APP_USBD_STRINGS_CONFIGURATION is created by macro or declared as global variable.
- 
+
 
 #ifndef APP_USBD_STRING_CONFIGURATION_EXTERN
 #define APP_USBD_STRING_CONFIGURATION_EXTERN 0
@@ -6410,7 +6410,7 @@
 #ifndef APP_USBD_HID_ENABLED
 #define APP_USBD_HID_ENABLED 0
 #endif
-//  APP_USBD_HID_DEFAULT_IDLE_RATE - Default idle rate for HID class.   <0-255> 
+//  APP_USBD_HID_DEFAULT_IDLE_RATE - Default idle rate for HID class.   <0-255>
 
 
 //  0 means indefinite duration, any other value is multiplied by 4 milliseconds. Refer to Chapter 7.2.4 of HID 1.11 Specification.
@@ -6419,7 +6419,7 @@
 #define APP_USBD_HID_DEFAULT_IDLE_RATE 0
 #endif
 
-//  APP_USBD_HID_REPORT_IDLE_TABLE_SIZE - Size of idle rate table.   <1-255> 
+//  APP_USBD_HID_REPORT_IDLE_TABLE_SIZE - Size of idle rate table.   <1-255>
 
 
 //  Must be higher than the highest report ID used.
@@ -6431,49 +6431,49 @@
 // 
 
 //  APP_USBD_HID_GENERIC_ENABLED  - app_usbd_hid_generic - USB HID generic
- 
+
 
 #ifndef APP_USBD_HID_GENERIC_ENABLED
 #define APP_USBD_HID_GENERIC_ENABLED 0
 #endif
 
 //  APP_USBD_HID_KBD_ENABLED  - app_usbd_hid_kbd - USB HID keyboard
- 
+
 
 #ifndef APP_USBD_HID_KBD_ENABLED
 #define APP_USBD_HID_KBD_ENABLED 0
 #endif
 
 //  APP_USBD_HID_MOUSE_ENABLED  - app_usbd_hid_mouse - USB HID mouse
- 
+
 
 #ifndef APP_USBD_HID_MOUSE_ENABLED
 #define APP_USBD_HID_MOUSE_ENABLED 0
 #endif
 
 //  APP_USBD_MSC_ENABLED  - app_usbd_msc - USB MSC class
- 
+
 
 #ifndef APP_USBD_MSC_ENABLED
 #define APP_USBD_MSC_ENABLED 0
 #endif
 
 //  CRC16_ENABLED  - crc16 - CRC16 calculation routines
- 
+
 
 #ifndef CRC16_ENABLED
 #define CRC16_ENABLED 0
 #endif
 
 //  CRC32_ENABLED  - crc32 - CRC32 calculation routines
- 
+
 
 #ifndef CRC32_ENABLED
 #define CRC32_ENABLED 0
 #endif
 
 //  ECC_ENABLED  - ecc - Elliptic Curve Cryptography Library
- 
+
 
 #ifndef ECC_ENABLED
 #define ECC_ENABLED 0
@@ -6488,7 +6488,7 @@
 
 //  Configure the number of virtual pages to use and their size.
 //==========================================================
-//  FDS_VIRTUAL_PAGES - Number of virtual flash pages to use. 
+//  FDS_VIRTUAL_PAGES - Number of virtual flash pages to use.
 //  One of the virtual pages is reserved by the system for garbage collection.
 //  Therefore, the minimum is two virtual pages: one page to store data and one page to be used by the system for garbage collection.
 //  The total amount of flash memory that is used by FDS amounts to @ref FDS_VIRTUAL_PAGES * @ref FDS_VIRTUAL_PAGE_SIZE * 4 bytes.
@@ -6498,19 +6498,19 @@
 #endif
 
 //  FDS_VIRTUAL_PAGE_SIZE  - The size of a virtual flash page.
- 
+
 
 //  Expressed in number of 4-byte words.
 //  By default, a virtual page is the same size as a physical page.
 //  The size of a virtual page must be a multiple of the size of a physical page.
-// <1024=> 1024 
-// <2048=> 2048 
+// <1024=> 1024
+// <2048=> 2048
 
 #ifndef FDS_VIRTUAL_PAGE_SIZE
 #define FDS_VIRTUAL_PAGE_SIZE 1024
 #endif
 
-//  FDS_VIRTUAL_PAGES_RESERVED - The number of virtual flash pages that are used by other modules. 
+//  FDS_VIRTUAL_PAGES_RESERVED - The number of virtual flash pages that are used by other modules.
 //  FDS module stores its data in the last pages of the flash memory.
 //  By setting this value, you can move flash end address used by the FDS.
 //  As a result the reserved space can be used by other modules.
@@ -6519,7 +6519,7 @@
 #define FDS_VIRTUAL_PAGES_RESERVED 0
 #endif
 
-//  
+// 
 //==========================================================
 
 //  Backend - Backend configuration
@@ -6527,31 +6527,31 @@
 //  Configure which nrf_fstorage backend is used by FDS to write to flash.
 //==========================================================
 //  FDS_BACKEND  - FDS flash backend.
- 
+
 
 //  NRF_FSTORAGE_SD uses the nrf_fstorage_sd backend implementation using the SoftDevice API. Use this if you have a SoftDevice present.
 //  NRF_FSTORAGE_NVMC uses the nrf_fstorage_nvmc implementation. Use this setting if you don't use the SoftDevice.
-// <1=> NRF_FSTORAGE_NVMC 
-// <2=> NRF_FSTORAGE_SD 
+// <1=> NRF_FSTORAGE_NVMC
+// <2=> NRF_FSTORAGE_SD
 
 #ifndef FDS_BACKEND
 #define FDS_BACKEND 2
 #endif
 
-//  
+// 
 //==========================================================
 
 //  Queue - Queue settings
 
 //==========================================================
-//  FDS_OP_QUEUE_SIZE - Size of the internal queue. 
+//  FDS_OP_QUEUE_SIZE - Size of the internal queue.
 //  Increase this value if you frequently get synchronous FDS_ERR_NO_SPACE_IN_QUEUES errors.
 
 #ifndef FDS_OP_QUEUE_SIZE
 #define FDS_OP_QUEUE_SIZE 4
 #endif
 
-//  
+// 
 //==========================================================
 
 //  CRC - CRC functionality
@@ -6567,12 +6567,12 @@
 #define FDS_CRC_CHECK_ON_READ 0
 #endif
 //  FDS_CRC_CHECK_ON_WRITE  - Perform a CRC check on newly written records.
- 
+
 
 //  Perform a CRC check on newly written records.
 //  This setting can be used to make sure that the record data was not altered while being written to flash.
-// <1=> Enabled 
-// <0=> Disabled 
+// <1=> Enabled
+// <0=> Disabled
 
 #ifndef FDS_CRC_CHECK_ON_WRITE
 #define FDS_CRC_CHECK_ON_WRITE 0
@@ -6580,24 +6580,24 @@
 
 // 
 
-//  
+// 
 //==========================================================
 
 //  Users - Number of users
 
 //==========================================================
-//  FDS_MAX_USERS - Maximum number of callbacks that can be registered. 
+//  FDS_MAX_USERS - Maximum number of callbacks that can be registered.
 #ifndef FDS_MAX_USERS
 #define FDS_MAX_USERS 4
 #endif
 
-//  
+// 
 //==========================================================
 
 // 
 
 //  HARDFAULT_HANDLER_ENABLED  - hardfault_default - HardFault default handler for debugging and release
- 
+
 
 #ifndef HARDFAULT_HANDLER_ENABLED
 #define HARDFAULT_HANDLER_ENABLED 0
@@ -6608,17 +6608,17 @@
 #ifndef HCI_MEM_POOL_ENABLED
 #define HCI_MEM_POOL_ENABLED 0
 #endif
-//  HCI_TX_BUF_SIZE - TX buffer size in bytes. 
+//  HCI_TX_BUF_SIZE - TX buffer size in bytes.
 #ifndef HCI_TX_BUF_SIZE
 #define HCI_TX_BUF_SIZE 600
 #endif
 
-//  HCI_RX_BUF_SIZE - RX buffer size in bytes. 
+//  HCI_RX_BUF_SIZE - RX buffer size in bytes.
 #ifndef HCI_RX_BUF_SIZE
 #define HCI_RX_BUF_SIZE 600
 #endif
 
-//  HCI_RX_BUF_QUEUE_SIZE - RX buffer queue size. 
+//  HCI_RX_BUF_QUEUE_SIZE - RX buffer queue size.
 #ifndef HCI_RX_BUF_QUEUE_SIZE
 #define HCI_RX_BUF_QUEUE_SIZE 4
 #endif
@@ -6631,53 +6631,53 @@
 #define HCI_SLIP_ENABLED 0
 #endif
 //  HCI_UART_BAUDRATE  - Default Baudrate
- 
-// <323584=> 1200 baud 
-// <643072=> 2400 baud 
-// <1290240=> 4800 baud 
-// <2576384=> 9600 baud 
-// <3862528=> 14400 baud 
-// <5152768=> 19200 baud 
-// <7716864=> 28800 baud 
-// <10289152=> 38400 baud 
-// <15400960=> 57600 baud 
-// <20615168=> 76800 baud 
-// <30801920=> 115200 baud 
-// <61865984=> 230400 baud 
-// <67108864=> 250000 baud 
-// <121634816=> 460800 baud 
-// <251658240=> 921600 baud 
-// <268435456=> 1000000 baud 
+
+// <323584=> 1200 baud
+// <643072=> 2400 baud
+// <1290240=> 4800 baud
+// <2576384=> 9600 baud
+// <3862528=> 14400 baud
+// <5152768=> 19200 baud
+// <7716864=> 28800 baud
+// <10289152=> 38400 baud
+// <15400960=> 57600 baud
+// <20615168=> 76800 baud
+// <30801920=> 115200 baud
+// <61865984=> 230400 baud
+// <67108864=> 250000 baud
+// <121634816=> 460800 baud
+// <251658240=> 921600 baud
+// <268435456=> 1000000 baud
 
 #ifndef HCI_UART_BAUDRATE
 #define HCI_UART_BAUDRATE 30801920
 #endif
 
 //  HCI_UART_FLOW_CONTROL  - Hardware Flow Control
- 
-// <0=> Disabled 
-// <1=> Enabled 
+
+// <0=> Disabled
+// <1=> Enabled
 
 #ifndef HCI_UART_FLOW_CONTROL
 #define HCI_UART_FLOW_CONTROL 0
 #endif
 
-//  HCI_UART_RX_PIN - UART RX pin 
+//  HCI_UART_RX_PIN - UART RX pin
 #ifndef HCI_UART_RX_PIN
 #define HCI_UART_RX_PIN 31
 #endif
 
-//  HCI_UART_TX_PIN - UART TX pin 
+//  HCI_UART_TX_PIN - UART TX pin
 #ifndef HCI_UART_TX_PIN
 #define HCI_UART_TX_PIN 31
 #endif
 
-//  HCI_UART_RTS_PIN - UART RTS pin 
+//  HCI_UART_RTS_PIN - UART RTS pin
 #ifndef HCI_UART_RTS_PIN
 #define HCI_UART_RTS_PIN 31
 #endif
 
-//  HCI_UART_CTS_PIN - UART CTS pin 
+//  HCI_UART_CTS_PIN - UART CTS pin
 #ifndef HCI_UART_CTS_PIN
 #define HCI_UART_CTS_PIN 31
 #endif
@@ -6689,7 +6689,7 @@
 #ifndef HCI_TRANSPORT_ENABLED
 #define HCI_TRANSPORT_ENABLED 0
 #endif
-//  HCI_MAX_PACKET_SIZE_IN_BITS - Maximum size of a single application packet in bits. 
+//  HCI_MAX_PACKET_SIZE_IN_BITS - Maximum size of a single application packet in bits.
 #ifndef HCI_MAX_PACKET_SIZE_IN_BITS
 #define HCI_MAX_PACKET_SIZE_IN_BITS 8000
 #endif
@@ -6697,14 +6697,14 @@
 // 
 
 //  LED_SOFTBLINK_ENABLED  - led_softblink - led_softblink module
- 
+
 
 #ifndef LED_SOFTBLINK_ENABLED
 #define LED_SOFTBLINK_ENABLED 0
 #endif
 
 //  LOW_POWER_PWM_ENABLED  - low_power_pwm - low_power_pwm module
- 
+
 
 #ifndef LOW_POWER_PWM_ENABLED
 #define LOW_POWER_PWM_ENABLED 0
@@ -6715,98 +6715,98 @@
 #ifndef MEM_MANAGER_ENABLED
 #define MEM_MANAGER_ENABLED 0
 #endif
-//  MEMORY_MANAGER_SMALL_BLOCK_COUNT - Size of each memory blocks identified as 'small' block.  <0-255> 
+//  MEMORY_MANAGER_SMALL_BLOCK_COUNT - Size of each memory blocks identified as 'small' block.  <0-255>
 
 
 #ifndef MEMORY_MANAGER_SMALL_BLOCK_COUNT
 #define MEMORY_MANAGER_SMALL_BLOCK_COUNT 1
 #endif
 
-//  MEMORY_MANAGER_SMALL_BLOCK_SIZE -  Size of each memory blocks identified as 'small' block. 
+//  MEMORY_MANAGER_SMALL_BLOCK_SIZE -  Size of each memory blocks identified as 'small' block.
 //   Size of each memory blocks identified as 'small' block. Memory block are recommended to be word-sized.
 
 #ifndef MEMORY_MANAGER_SMALL_BLOCK_SIZE
 #define MEMORY_MANAGER_SMALL_BLOCK_SIZE 32
 #endif
 
-//  MEMORY_MANAGER_MEDIUM_BLOCK_COUNT - Size of each memory blocks identified as 'medium' block.  <0-255> 
+//  MEMORY_MANAGER_MEDIUM_BLOCK_COUNT - Size of each memory blocks identified as 'medium' block.  <0-255>
 
 
 #ifndef MEMORY_MANAGER_MEDIUM_BLOCK_COUNT
 #define MEMORY_MANAGER_MEDIUM_BLOCK_COUNT 0
 #endif
 
-//  MEMORY_MANAGER_MEDIUM_BLOCK_SIZE -  Size of each memory blocks identified as 'medium' block. 
+//  MEMORY_MANAGER_MEDIUM_BLOCK_SIZE -  Size of each memory blocks identified as 'medium' block.
 //   Size of each memory blocks identified as 'medium' block. Memory block are recommended to be word-sized.
 
 #ifndef MEMORY_MANAGER_MEDIUM_BLOCK_SIZE
 #define MEMORY_MANAGER_MEDIUM_BLOCK_SIZE 256
 #endif
 
-//  MEMORY_MANAGER_LARGE_BLOCK_COUNT - Size of each memory blocks identified as 'large' block.  <0-255> 
+//  MEMORY_MANAGER_LARGE_BLOCK_COUNT - Size of each memory blocks identified as 'large' block.  <0-255>
 
 
 #ifndef MEMORY_MANAGER_LARGE_BLOCK_COUNT
 #define MEMORY_MANAGER_LARGE_BLOCK_COUNT 0
 #endif
 
-//  MEMORY_MANAGER_LARGE_BLOCK_SIZE -  Size of each memory blocks identified as 'large' block. 
+//  MEMORY_MANAGER_LARGE_BLOCK_SIZE -  Size of each memory blocks identified as 'large' block.
 //   Size of each memory blocks identified as 'large' block. Memory block are recommended to be word-sized.
 
 #ifndef MEMORY_MANAGER_LARGE_BLOCK_SIZE
 #define MEMORY_MANAGER_LARGE_BLOCK_SIZE 256
 #endif
 
-//  MEMORY_MANAGER_XLARGE_BLOCK_COUNT - Size of each memory blocks identified as 'extra large' block.  <0-255> 
+//  MEMORY_MANAGER_XLARGE_BLOCK_COUNT - Size of each memory blocks identified as 'extra large' block.  <0-255>
 
 
 #ifndef MEMORY_MANAGER_XLARGE_BLOCK_COUNT
 #define MEMORY_MANAGER_XLARGE_BLOCK_COUNT 0
 #endif
 
-//  MEMORY_MANAGER_XLARGE_BLOCK_SIZE -  Size of each memory blocks identified as 'extra large' block. 
+//  MEMORY_MANAGER_XLARGE_BLOCK_SIZE -  Size of each memory blocks identified as 'extra large' block.
 //   Size of each memory blocks identified as 'extra large' block. Memory block are recommended to be word-sized.
 
 #ifndef MEMORY_MANAGER_XLARGE_BLOCK_SIZE
 #define MEMORY_MANAGER_XLARGE_BLOCK_SIZE 1320
 #endif
 
-//  MEMORY_MANAGER_XXLARGE_BLOCK_COUNT - Size of each memory blocks identified as 'extra extra large' block.  <0-255> 
+//  MEMORY_MANAGER_XXLARGE_BLOCK_COUNT - Size of each memory blocks identified as 'extra extra large' block.  <0-255>
 
 
 #ifndef MEMORY_MANAGER_XXLARGE_BLOCK_COUNT
 #define MEMORY_MANAGER_XXLARGE_BLOCK_COUNT 0
 #endif
 
-//  MEMORY_MANAGER_XXLARGE_BLOCK_SIZE -  Size of each memory blocks identified as 'extra extra large' block. 
+//  MEMORY_MANAGER_XXLARGE_BLOCK_SIZE -  Size of each memory blocks identified as 'extra extra large' block.
 //   Size of each memory blocks identified as 'extra extra large' block. Memory block are recommended to be word-sized.
 
 #ifndef MEMORY_MANAGER_XXLARGE_BLOCK_SIZE
 #define MEMORY_MANAGER_XXLARGE_BLOCK_SIZE 3444
 #endif
 
-//  MEMORY_MANAGER_XSMALL_BLOCK_COUNT - Size of each memory blocks identified as 'extra small' block.  <0-255> 
+//  MEMORY_MANAGER_XSMALL_BLOCK_COUNT - Size of each memory blocks identified as 'extra small' block.  <0-255>
 
 
 #ifndef MEMORY_MANAGER_XSMALL_BLOCK_COUNT
 #define MEMORY_MANAGER_XSMALL_BLOCK_COUNT 0
 #endif
 
-//  MEMORY_MANAGER_XSMALL_BLOCK_SIZE -  Size of each memory blocks identified as 'extra small' block. 
+//  MEMORY_MANAGER_XSMALL_BLOCK_SIZE -  Size of each memory blocks identified as 'extra small' block.
 //   Size of each memory blocks identified as 'extra large' block. Memory block are recommended to be word-sized.
 
 #ifndef MEMORY_MANAGER_XSMALL_BLOCK_SIZE
 #define MEMORY_MANAGER_XSMALL_BLOCK_SIZE 64
 #endif
 
-//  MEMORY_MANAGER_XXSMALL_BLOCK_COUNT - Size of each memory blocks identified as 'extra extra small' block.  <0-255> 
+//  MEMORY_MANAGER_XXSMALL_BLOCK_COUNT - Size of each memory blocks identified as 'extra extra small' block.  <0-255>
 
 
 #ifndef MEMORY_MANAGER_XXSMALL_BLOCK_COUNT
 #define MEMORY_MANAGER_XXSMALL_BLOCK_COUNT 0
 #endif
 
-//  MEMORY_MANAGER_XXSMALL_BLOCK_SIZE -  Size of each memory blocks identified as 'extra extra small' block. 
+//  MEMORY_MANAGER_XXSMALL_BLOCK_SIZE -  Size of each memory blocks identified as 'extra extra small' block.
 //   Size of each memory blocks identified as 'extra extra small' block. Memory block are recommended to be word-sized.
 
 #ifndef MEMORY_MANAGER_XXSMALL_BLOCK_SIZE
@@ -6819,44 +6819,44 @@
 #define MEM_MANAGER_CONFIG_LOG_ENABLED 0
 #endif
 //  MEM_MANAGER_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef MEM_MANAGER_CONFIG_LOG_LEVEL
 #define MEM_MANAGER_CONFIG_LOG_LEVEL 3
 #endif
 
 //  MEM_MANAGER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef MEM_MANAGER_CONFIG_INFO_COLOR
 #define MEM_MANAGER_CONFIG_INFO_COLOR 0
 #endif
 
 //  MEM_MANAGER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef MEM_MANAGER_CONFIG_DEBUG_COLOR
 #define MEM_MANAGER_CONFIG_DEBUG_COLOR 0
@@ -6865,7 +6865,7 @@
 // 
 
 //  MEM_MANAGER_DISABLE_API_PARAM_CHECK  - Disable API parameter checks in the module.
- 
+
 
 #ifndef MEM_MANAGER_DISABLE_API_PARAM_CHECK
 #define MEM_MANAGER_DISABLE_API_PARAM_CHECK 0
@@ -6883,14 +6883,14 @@
 #ifndef NRF_BALLOC_CONFIG_DEBUG_ENABLED
 #define NRF_BALLOC_CONFIG_DEBUG_ENABLED 0
 #endif
-//  NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS - Number of words used as head guard.  <0-255> 
+//  NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS - Number of words used as head guard.  <0-255>
 
 
 #ifndef NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS
 #define NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS 1
 #endif
 
-//  NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS - Number of words used as tail guard.  <0-255> 
+//  NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS - Number of words used as tail guard.  <0-255>
 
 
 #ifndef NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS
@@ -6898,28 +6898,28 @@
 #endif
 
 //  NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED  - Enables basic checks in this module.
- 
+
 
 #ifndef NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED
 #define NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED 0
 #endif
 
 //  NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED  - Enables double memory free check in this module.
- 
+
 
 #ifndef NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED
 #define NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED 0
 #endif
 
 //  NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED  - Enables free memory corruption check in this module.
- 
+
 
 #ifndef NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED
 #define NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED 0
 #endif
 
 //  NRF_BALLOC_CLI_CMDS  - Enable CLI commands specific to the module
- 
+
 
 #ifndef NRF_BALLOC_CLI_CMDS
 #define NRF_BALLOC_CLI_CMDS 0
@@ -6934,32 +6934,32 @@
 #ifndef NRF_CSENSE_ENABLED
 #define NRF_CSENSE_ENABLED 0
 #endif
-//  NRF_CSENSE_PAD_HYSTERESIS - Minimum value of change required to determine that a pad was touched. 
+//  NRF_CSENSE_PAD_HYSTERESIS - Minimum value of change required to determine that a pad was touched.
 #ifndef NRF_CSENSE_PAD_HYSTERESIS
 #define NRF_CSENSE_PAD_HYSTERESIS 15
 #endif
 
-//  NRF_CSENSE_PAD_DEVIATION - Minimum value measured on a pad required to take it into account while calculating the step. 
+//  NRF_CSENSE_PAD_DEVIATION - Minimum value measured on a pad required to take it into account while calculating the step.
 #ifndef NRF_CSENSE_PAD_DEVIATION
 #define NRF_CSENSE_PAD_DEVIATION 70
 #endif
 
-//  NRF_CSENSE_MIN_PAD_VALUE - Minimum normalized value on a pad required to take its value into account. 
+//  NRF_CSENSE_MIN_PAD_VALUE - Minimum normalized value on a pad required to take its value into account.
 #ifndef NRF_CSENSE_MIN_PAD_VALUE
 #define NRF_CSENSE_MIN_PAD_VALUE 20
 #endif
 
-//  NRF_CSENSE_MAX_PADS_NUMBER - Maximum number of pads used for one instance. 
+//  NRF_CSENSE_MAX_PADS_NUMBER - Maximum number of pads used for one instance.
 #ifndef NRF_CSENSE_MAX_PADS_NUMBER
 #define NRF_CSENSE_MAX_PADS_NUMBER 20
 #endif
 
-//  NRF_CSENSE_MAX_VALUE - Maximum normalized value obtained from measurement. 
+//  NRF_CSENSE_MAX_VALUE - Maximum normalized value obtained from measurement.
 #ifndef NRF_CSENSE_MAX_VALUE
 #define NRF_CSENSE_MAX_VALUE 1000
 #endif
 
-//  NRF_CSENSE_OUTPUT_PIN - Output pin used by the low-level module. 
+//  NRF_CSENSE_OUTPUT_PIN - Output pin used by the low-level module.
 //  This is used when capacitive sensor does not use COMP.
 
 #ifndef NRF_CSENSE_OUTPUT_PIN
@@ -6980,17 +6980,17 @@
 #ifndef USE_COMP
 #define USE_COMP 0
 #endif
-//  TIMER0_FOR_CSENSE - First TIMER instance used by the driver (not used on nRF51). 
+//  TIMER0_FOR_CSENSE - First TIMER instance used by the driver (not used on nRF51).
 #ifndef TIMER0_FOR_CSENSE
 #define TIMER0_FOR_CSENSE 1
 #endif
 
-//  TIMER1_FOR_CSENSE - Second TIMER instance used by the driver (not used on nRF51). 
+//  TIMER1_FOR_CSENSE - Second TIMER instance used by the driver (not used on nRF51).
 #ifndef TIMER1_FOR_CSENSE
 #define TIMER1_FOR_CSENSE 2
 #endif
 
-//  MEASUREMENT_PERIOD - Single measurement period. 
+//  MEASUREMENT_PERIOD - Single measurement period.
 //  Time of a single measurement can be calculated as
 //  T = (1/2)*MEASUREMENT_PERIOD*(1/f_OSC) where f_OSC = I_SOURCE / (2C*(VUP-VDOWN) ).
 //  I_SOURCE, VUP, and VDOWN are values used to initialize COMP and C is the capacitance of the used pad.
@@ -7013,7 +7013,7 @@
 //  Common settings to all fstorage implementations
 //==========================================================
 //  NRF_FSTORAGE_PARAM_CHECK_DISABLED  - Disable user input validation
- 
+
 
 //  If selected, use ASSERT to validate user input.
 //  This effectively removes user input validation in production code.
@@ -7023,21 +7023,21 @@
 #define NRF_FSTORAGE_PARAM_CHECK_DISABLED 0
 #endif
 
-//  
+// 
 //==========================================================
 
 //  nrf_fstorage_sd - Implementation using the SoftDevice
 
 //  Configuration options for the fstorage implementation using the SoftDevice
 //==========================================================
-//  NRF_FSTORAGE_SD_QUEUE_SIZE - Size of the internal queue of operations 
+//  NRF_FSTORAGE_SD_QUEUE_SIZE - Size of the internal queue of operations
 //  Increase this value if API calls frequently return the error @ref NRF_ERROR_NO_MEM.
 
 #ifndef NRF_FSTORAGE_SD_QUEUE_SIZE
 #define NRF_FSTORAGE_SD_QUEUE_SIZE 4
 #endif
 
-//  NRF_FSTORAGE_SD_MAX_RETRIES - Maximum number of attempts at executing an operation when the SoftDevice is busy 
+//  NRF_FSTORAGE_SD_MAX_RETRIES - Maximum number of attempts at executing an operation when the SoftDevice is busy
 //  Increase this value if events frequently return the @ref NRF_ERROR_TIMEOUT error.
 //  The SoftDevice might fail to schedule flash access due to high BLE activity.
 
@@ -7045,7 +7045,7 @@
 #define NRF_FSTORAGE_SD_MAX_RETRIES 8
 #endif
 
-//  NRF_FSTORAGE_SD_MAX_WRITE_SIZE - Maximum number of bytes to be written to flash in a single operation 
+//  NRF_FSTORAGE_SD_MAX_WRITE_SIZE - Maximum number of bytes to be written to flash in a single operation
 //  This value must be a multiple of four.
 //  Lowering this value can increase the chances of the SoftDevice being able to execute flash operations in between radio activity.
 //  This value is bound by the maximum number of bytes that can be written to flash in a single call to @ref sd_flash_write.
@@ -7055,20 +7055,20 @@
 #define NRF_FSTORAGE_SD_MAX_WRITE_SIZE 4096
 #endif
 
-//  
+// 
 //==========================================================
 
 // 
 
 //  NRF_GFX_ENABLED  - nrf_gfx - GFX module
- 
+
 
 #ifndef NRF_GFX_ENABLED
 #define NRF_GFX_ENABLED 0
 #endif
 
 //  NRF_MEMOBJ_ENABLED  - nrf_memobj - Linked memory allocator module
- 
+
 
 #ifndef NRF_MEMOBJ_ENABLED
 #define NRF_MEMOBJ_ENABLED 1
@@ -7087,56 +7087,56 @@
 #define NRF_PWR_MGMT_CONFIG_DEBUG_PIN_ENABLED 0
 #endif
 //  NRF_PWR_MGMT_SLEEP_DEBUG_PIN  - Pin number
- 
-// <0=> 0 (P0.0) 
-// <1=> 1 (P0.1) 
-// <2=> 2 (P0.2) 
-// <3=> 3 (P0.3) 
-// <4=> 4 (P0.4) 
-// <5=> 5 (P0.5) 
-// <6=> 6 (P0.6) 
-// <7=> 7 (P0.7) 
-// <8=> 8 (P0.8) 
-// <9=> 9 (P0.9) 
-// <10=> 10 (P0.10) 
-// <11=> 11 (P0.11) 
-// <12=> 12 (P0.12) 
-// <13=> 13 (P0.13) 
-// <14=> 14 (P0.14) 
-// <15=> 15 (P0.15) 
-// <16=> 16 (P0.16) 
-// <17=> 17 (P0.17) 
-// <18=> 18 (P0.18) 
-// <19=> 19 (P0.19) 
-// <20=> 20 (P0.20) 
-// <21=> 21 (P0.21) 
-// <22=> 22 (P0.22) 
-// <23=> 23 (P0.23) 
-// <24=> 24 (P0.24) 
-// <25=> 25 (P0.25) 
-// <26=> 26 (P0.26) 
-// <27=> 27 (P0.27) 
-// <28=> 28 (P0.28) 
-// <29=> 29 (P0.29) 
-// <30=> 30 (P0.30) 
-// <31=> 31 (P0.31) 
-// <32=> 32 (P1.0) 
-// <33=> 33 (P1.1) 
-// <34=> 34 (P1.2) 
-// <35=> 35 (P1.3) 
-// <36=> 36 (P1.4) 
-// <37=> 37 (P1.5) 
-// <38=> 38 (P1.6) 
-// <39=> 39 (P1.7) 
-// <40=> 40 (P1.8) 
-// <41=> 41 (P1.9) 
-// <42=> 42 (P1.10) 
-// <43=> 43 (P1.11) 
-// <44=> 44 (P1.12) 
-// <45=> 45 (P1.13) 
-// <46=> 46 (P1.14) 
-// <47=> 47 (P1.15) 
-// <4294967295=> Not connected 
+
+// <0=> 0 (P0.0)
+// <1=> 1 (P0.1)
+// <2=> 2 (P0.2)
+// <3=> 3 (P0.3)
+// <4=> 4 (P0.4)
+// <5=> 5 (P0.5)
+// <6=> 6 (P0.6)
+// <7=> 7 (P0.7)
+// <8=> 8 (P0.8)
+// <9=> 9 (P0.9)
+// <10=> 10 (P0.10)
+// <11=> 11 (P0.11)
+// <12=> 12 (P0.12)
+// <13=> 13 (P0.13)
+// <14=> 14 (P0.14)
+// <15=> 15 (P0.15)
+// <16=> 16 (P0.16)
+// <17=> 17 (P0.17)
+// <18=> 18 (P0.18)
+// <19=> 19 (P0.19)
+// <20=> 20 (P0.20)
+// <21=> 21 (P0.21)
+// <22=> 22 (P0.22)
+// <23=> 23 (P0.23)
+// <24=> 24 (P0.24)
+// <25=> 25 (P0.25)
+// <26=> 26 (P0.26)
+// <27=> 27 (P0.27)
+// <28=> 28 (P0.28)
+// <29=> 29 (P0.29)
+// <30=> 30 (P0.30)
+// <31=> 31 (P0.31)
+// <32=> 32 (P1.0)
+// <33=> 33 (P1.1)
+// <34=> 34 (P1.2)
+// <35=> 35 (P1.3)
+// <36=> 36 (P1.4)
+// <37=> 37 (P1.5)
+// <38=> 38 (P1.6)
+// <39=> 39 (P1.7)
+// <40=> 40 (P1.8)
+// <41=> 41 (P1.9)
+// <42=> 42 (P1.10)
+// <43=> 43 (P1.11)
+// <44=> 44 (P1.12)
+// <45=> 45 (P1.13)
+// <46=> 46 (P1.14)
+// <47=> 47 (P1.15)
+// <4294967295=> Not connected
 
 #ifndef NRF_PWR_MGMT_SLEEP_DEBUG_PIN
 #define NRF_PWR_MGMT_SLEEP_DEBUG_PIN 31
@@ -7145,7 +7145,7 @@
 // 
 
 //  NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED  - Enables CPU usage monitor.
- 
+
 
 //  Module will trace percentage of CPU usage in one second intervals.
 
@@ -7158,7 +7158,7 @@
 #ifndef NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_ENABLED
 #define NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_ENABLED 0
 #endif
-//  NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S - Standby timeout (in seconds). 
+//  NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S - Standby timeout (in seconds).
 //  Shutdown procedure will begin no earlier than after this number of seconds.
 
 #ifndef NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S
@@ -7168,27 +7168,27 @@
 // 
 
 //  NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED  - Enables FPU event cleaning.
- 
+
 
 #ifndef NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED
 #define NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED 0
 #endif
 
 //  NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY  - Blocked shutdown procedure will be retried every second.
- 
+
 
 #ifndef NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY
 #define NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY 0
 #endif
 
 //  NRF_PWR_MGMT_CONFIG_USE_SCHEDULER  - Module will use @ref app_scheduler.
- 
+
 
 #ifndef NRF_PWR_MGMT_CONFIG_USE_SCHEDULER
 #define NRF_PWR_MGMT_CONFIG_USE_SCHEDULER 0
 #endif
 
-//  NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT - The number of priorities for module handlers. 
+//  NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT - The number of priorities for module handlers.
 //  The number of stages of the shutdown process.
 
 #ifndef NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT
@@ -7203,7 +7203,7 @@
 #define NRF_QUEUE_ENABLED 0
 #endif
 //  NRF_QUEUE_CLI_CMDS  - Enable CLI commands specific to the module
- 
+
 
 #ifndef NRF_QUEUE_CLI_CMDS
 #define NRF_QUEUE_CLI_CMDS 0
@@ -7212,42 +7212,42 @@
 // 
 
 //  NRF_SECTION_ITER_ENABLED  - nrf_section_iter - Section iterator
- 
+
 
 #ifndef NRF_SECTION_ITER_ENABLED
 #define NRF_SECTION_ITER_ENABLED 1
 #endif
 
 //  NRF_SORTLIST_ENABLED  - nrf_sortlist - Sorted list
- 
+
 
 #ifndef NRF_SORTLIST_ENABLED
 #define NRF_SORTLIST_ENABLED 1
 #endif
 
 //  NRF_SPI_MNGR_ENABLED  - nrf_spi_mngr - SPI transaction manager
- 
+
 
 #ifndef NRF_SPI_MNGR_ENABLED
 #define NRF_SPI_MNGR_ENABLED 0
 #endif
 
 //  NRF_STRERROR_ENABLED  - nrf_strerror - Library for converting error code to string.
- 
+
 
 #ifndef NRF_STRERROR_ENABLED
 #define NRF_STRERROR_ENABLED 1
 #endif
 
 //  NRF_TWI_MNGR_ENABLED  - nrf_twi_mngr - TWI transaction manager
- 
+
 
 #ifndef NRF_TWI_MNGR_ENABLED
 #define NRF_TWI_MNGR_ENABLED 0
 #endif
 
 //  SLIP_ENABLED  - slip - SLIP encoding and decoding
- 
+
 
 #ifndef SLIP_ENABLED
 #define SLIP_ENABLED 0
@@ -7259,37 +7259,37 @@
 #define TASK_MANAGER_ENABLED 0
 #endif
 //  TASK_MANAGER_CLI_CMDS  - Enable CLI commands specific to the module
- 
+
 
 #ifndef TASK_MANAGER_CLI_CMDS
 #define TASK_MANAGER_CLI_CMDS 0
 #endif
 
-//  TASK_MANAGER_CONFIG_MAX_TASKS - Maximum number of tasks which can be created 
+//  TASK_MANAGER_CONFIG_MAX_TASKS - Maximum number of tasks which can be created
 #ifndef TASK_MANAGER_CONFIG_MAX_TASKS
 #define TASK_MANAGER_CONFIG_MAX_TASKS 2
 #endif
 
-//  TASK_MANAGER_CONFIG_STACK_SIZE - Stack size for every task (power of 2) 
+//  TASK_MANAGER_CONFIG_STACK_SIZE - Stack size for every task (power of 2)
 #ifndef TASK_MANAGER_CONFIG_STACK_SIZE
 #define TASK_MANAGER_CONFIG_STACK_SIZE 1024
 #endif
 
 //  TASK_MANAGER_CONFIG_STACK_PROFILER_ENABLED  - Enable stack profiling.
- 
+
 
 #ifndef TASK_MANAGER_CONFIG_STACK_PROFILER_ENABLED
 #define TASK_MANAGER_CONFIG_STACK_PROFILER_ENABLED 1
 #endif
 
 //  TASK_MANAGER_CONFIG_STACK_GUARD  - Configures stack guard.
- 
-// <0=> Disabled 
-// <4=> 32 bytes 
-// <5=> 64 bytes 
-// <6=> 128 bytes 
-// <7=> 256 bytes 
-// <8=> 512 bytes 
+
+// <0=> Disabled
+// <4=> 32 bytes
+// <5=> 64 bytes
+// <6=> 128 bytes
+// <7=> 256 bytes
+// <8=> 512 bytes
 
 #ifndef TASK_MANAGER_CONFIG_STACK_GUARD
 #define TASK_MANAGER_CONFIG_STACK_GUARD 7
@@ -7301,34 +7301,34 @@
 
 //==========================================================
 //  BUTTON_ENABLED  - Enables Button module
- 
+
 
 #ifndef BUTTON_ENABLED
 #define BUTTON_ENABLED 0
 #endif
 
 //  BUTTON_HIGH_ACCURACY_ENABLED  - Enables GPIOTE high accuracy for buttons
- 
+
 
 #ifndef BUTTON_HIGH_ACCURACY_ENABLED
 #define BUTTON_HIGH_ACCURACY_ENABLED 0
 #endif
 
-//  
+// 
 //==========================================================
 
 //  app_usbd_cdc_acm - USB CDC ACM class
 
 //==========================================================
 //  APP_USBD_CDC_ACM_ENABLED  - Enabling USBD CDC ACM Class library
- 
+
 
 #ifndef APP_USBD_CDC_ACM_ENABLED
 #define APP_USBD_CDC_ACM_ENABLED 0
 #endif
 
 //  APP_USBD_CDC_ACM_ZLP_ON_EPSIZE_WRITE  - Send ZLP on write with same size as endpoint
- 
+
 
 //  If enabled, CDC ACM class will automatically send a zero length packet after transfer which has the same size as endpoint.
 //  This may limit throughput if a lot of binary data is sent, but in terminal mode operation it makes sure that the data is always displayed right after it is sent.
@@ -7337,58 +7337,58 @@
 #define APP_USBD_CDC_ACM_ZLP_ON_EPSIZE_WRITE 1
 #endif
 
-//  
+// 
 //==========================================================
 
 //  nrf_cli - Command line interface
 
 //==========================================================
 //  NRF_CLI_ENABLED  - Enable/disable the CLI module.
- 
+
 
 #ifndef NRF_CLI_ENABLED
 #define NRF_CLI_ENABLED 0
 #endif
 
-//  NRF_CLI_ARGC_MAX - Maximum number of parameters passed to the command handler. 
+//  NRF_CLI_ARGC_MAX - Maximum number of parameters passed to the command handler.
 #ifndef NRF_CLI_ARGC_MAX
 #define NRF_CLI_ARGC_MAX 12
 #endif
 
 //  NRF_CLI_BUILD_IN_CMDS_ENABLED  - CLI built-in commands.
- 
+
 
 #ifndef NRF_CLI_BUILD_IN_CMDS_ENABLED
 #define NRF_CLI_BUILD_IN_CMDS_ENABLED 1
 #endif
 
-//  NRF_CLI_CMD_BUFF_SIZE - Maximum buffer size for a single command. 
+//  NRF_CLI_CMD_BUFF_SIZE - Maximum buffer size for a single command.
 #ifndef NRF_CLI_CMD_BUFF_SIZE
 #define NRF_CLI_CMD_BUFF_SIZE 128
 #endif
 
 //  NRF_CLI_ECHO_STATUS  - CLI echo status. If set, echo is ON.
- 
+
 
 #ifndef NRF_CLI_ECHO_STATUS
 #define NRF_CLI_ECHO_STATUS 1
 #endif
 
 //  NRF_CLI_WILDCARD_ENABLED  - Enable wildcard functionality for CLI commands.
- 
+
 
 #ifndef NRF_CLI_WILDCARD_ENABLED
 #define NRF_CLI_WILDCARD_ENABLED 0
 #endif
 
 //  NRF_CLI_METAKEYS_ENABLED  - Enable additional control keys for CLI commands like ctrl+a, ctrl+e, ctrl+w, ctrl+u
- 
+
 
 #ifndef NRF_CLI_METAKEYS_ENABLED
 #define NRF_CLI_METAKEYS_ENABLED 0
 #endif
 
-//  NRF_CLI_PRINTF_BUFF_SIZE - Maximum print buffer size. 
+//  NRF_CLI_PRINTF_BUFF_SIZE - Maximum print buffer size.
 #ifndef NRF_CLI_PRINTF_BUFF_SIZE
 #define NRF_CLI_PRINTF_BUFF_SIZE 23
 #endif
@@ -7398,12 +7398,12 @@
 #ifndef NRF_CLI_HISTORY_ENABLED
 #define NRF_CLI_HISTORY_ENABLED 1
 #endif
-//  NRF_CLI_HISTORY_ELEMENT_SIZE - Size of one memory object reserved for CLI history. 
+//  NRF_CLI_HISTORY_ELEMENT_SIZE - Size of one memory object reserved for CLI history.
 #ifndef NRF_CLI_HISTORY_ELEMENT_SIZE
 #define NRF_CLI_HISTORY_ELEMENT_SIZE 32
 #endif
 
-//  NRF_CLI_HISTORY_ELEMENT_COUNT - Number of history memory objects. 
+//  NRF_CLI_HISTORY_ELEMENT_COUNT - Number of history memory objects.
 #ifndef NRF_CLI_HISTORY_ELEMENT_COUNT
 #define NRF_CLI_HISTORY_ELEMENT_COUNT 8
 #endif
@@ -7411,67 +7411,67 @@
 // 
 
 //  NRF_CLI_VT100_COLORS_ENABLED  - CLI VT100 colors.
- 
+
 
 #ifndef NRF_CLI_VT100_COLORS_ENABLED
 #define NRF_CLI_VT100_COLORS_ENABLED 1
 #endif
 
 //  NRF_CLI_STATISTICS_ENABLED  - Enable CLI statistics.
- 
+
 
 #ifndef NRF_CLI_STATISTICS_ENABLED
 #define NRF_CLI_STATISTICS_ENABLED 1
 #endif
 
 //  NRF_CLI_LOG_BACKEND  - Enable logger backend interface.
- 
+
 
 #ifndef NRF_CLI_LOG_BACKEND
 #define NRF_CLI_LOG_BACKEND 1
 #endif
 
 //  NRF_CLI_USES_TASK_MANAGER_ENABLED  - Enable CLI to use task_manager
- 
+
 
 #ifndef NRF_CLI_USES_TASK_MANAGER_ENABLED
 #define NRF_CLI_USES_TASK_MANAGER_ENABLED 0
 #endif
 
-//  
+// 
 //==========================================================
 
 //  nrf_fprintf - fprintf function.
 
 //==========================================================
 //  NRF_FPRINTF_ENABLED  - Enable/disable fprintf module.
- 
+
 
 #ifndef NRF_FPRINTF_ENABLED
 #define NRF_FPRINTF_ENABLED 1
 #endif
 
 //  NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF_ENABLED  - For each printed LF, function will add CR.
- 
+
 
 #ifndef NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF_ENABLED
 #define NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF_ENABLED 1
 #endif
 
 //  NRF_FPRINTF_DOUBLE_ENABLED  - Enable IEEE-754 double precision formatting.
- 
+
 
 #ifndef NRF_FPRINTF_DOUBLE_ENABLED
 #define NRF_FPRINTF_DOUBLE_ENABLED 0
 #endif
 
-//  
+// 
 //==========================================================
 
-//  
+// 
 //==========================================================
 
-//  nRF_Log 
+//  nRF_Log
 
 //==========================================================
 //  NRF_LOG_ENABLED - nrf_log - Logger
@@ -7482,7 +7482,7 @@
 //  Log message pool - Configuration of log message pool
 
 //==========================================================
-//  NRF_LOG_MSGPOOL_ELEMENT_SIZE - Size of a single element in the pool of memory objects. 
+//  NRF_LOG_MSGPOOL_ELEMENT_SIZE - Size of a single element in the pool of memory objects.
 //  If a small value is set, then performance of logs processing
 //  is degraded because data is fragmented. Bigger value impacts
 //  RAM memory utilization. The size is set to fit a message with
@@ -7492,7 +7492,7 @@
 #define NRF_LOG_MSGPOOL_ELEMENT_SIZE 20
 #endif
 
-//  NRF_LOG_MSGPOOL_ELEMENT_COUNT - Number of elements in the pool of memory objects 
+//  NRF_LOG_MSGPOOL_ELEMENT_COUNT - Number of elements in the pool of memory objects
 //  If a small value is set, then it may lead to a deadlock
 //  in certain cases if backend has high latency and holds
 //  multiple messages for long time. Bigger value impacts
@@ -7502,13 +7502,13 @@
 #define NRF_LOG_MSGPOOL_ELEMENT_COUNT 8
 #endif
 
-//  
+// 
 //==========================================================
 
 //  NRF_LOG_ALLOW_OVERFLOW  - Configures behavior when circular buffer is full.
- 
 
-//  If set then oldest logs are overwritten. Otherwise a 
+
+//  If set then oldest logs are overwritten. Otherwise a
 //  marker is injected informing about overflow.
 
 #ifndef NRF_LOG_ALLOW_OVERFLOW
@@ -7516,44 +7516,44 @@
 #endif
 
 //  NRF_LOG_BUFSIZE  - Size of the buffer for storing logs (in bytes).
- 
+
 
 //  Must be power of 2 and multiple of 4.
 //  If NRF_LOG_DEFERRED = 0 then buffer size can be reduced to minimum.
-// <128=> 128 
-// <256=> 256 
-// <512=> 512 
-// <1024=> 1024 
-// <2048=> 2048 
-// <4096=> 4096 
-// <8192=> 8192 
-// <16384=> 16384 
+// <128=> 128
+// <256=> 256
+// <512=> 512
+// <1024=> 1024
+// <2048=> 2048
+// <4096=> 4096
+// <8192=> 8192
+// <16384=> 16384
 
 #ifndef NRF_LOG_BUFSIZE
 #define NRF_LOG_BUFSIZE 1024
 #endif
 
 //  NRF_LOG_CLI_CMDS  - Enable CLI commands for the module.
- 
+
 
 #ifndef NRF_LOG_CLI_CMDS
 #define NRF_LOG_CLI_CMDS 0
 #endif
 
 //  NRF_LOG_DEFAULT_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_LOG_DEFAULT_LEVEL
 #define NRF_LOG_DEFAULT_LEVEL 3
 #endif
 
 //  NRF_LOG_DEFERRED  - Enable deffered logger.
- 
+
 
 //  Log data is buffered and can be processed in idle.
 
@@ -7562,14 +7562,14 @@
 #endif
 
 //  NRF_LOG_FILTERS_ENABLED  - Enable dynamic filtering of logs.
- 
+
 
 #ifndef NRF_LOG_FILTERS_ENABLED
 #define NRF_LOG_FILTERS_ENABLED 0
 #endif
 
 //  NRF_LOG_NON_DEFFERED_CRITICAL_REGION_ENABLED  - Enable use of critical region for non deffered mode when flushing logs.
- 
+
 
 //  When enabled NRF_LOG_FLUSH is called from critical section when non deffered mode is used.
 //  Log output will never be corrupted as access to the log backend is exclusive
@@ -7580,28 +7580,28 @@
 #endif
 
 //  NRF_LOG_STR_PUSH_BUFFER_SIZE  - Size of the buffer dedicated for strings stored using @ref NRF_LOG_PUSH.
- 
-// <16=> 16 
-// <32=> 32 
-// <64=> 64 
-// <128=> 128 
-// <256=> 256 
-// <512=> 512 
-// <1024=> 1024 
+
+// <16=> 16
+// <32=> 32
+// <64=> 64
+// <128=> 128
+// <256=> 256
+// <512=> 512
+// <1024=> 1024
 
 #ifndef NRF_LOG_STR_PUSH_BUFFER_SIZE
 #define NRF_LOG_STR_PUSH_BUFFER_SIZE 128
 #endif
 
 //  NRF_LOG_STR_PUSH_BUFFER_SIZE  - Size of the buffer dedicated for strings stored using @ref NRF_LOG_PUSH.
- 
-// <16=> 16 
-// <32=> 32 
-// <64=> 64 
-// <128=> 128 
-// <256=> 256 
-// <512=> 512 
-// <1024=> 1024 
+
+// <16=> 16
+// <32=> 32
+// <64=> 64
+// <128=> 128
+// <256=> 256
+// <512=> 512
+// <1024=> 1024
 
 #ifndef NRF_LOG_STR_PUSH_BUFFER_SIZE
 #define NRF_LOG_STR_PUSH_BUFFER_SIZE 128
@@ -7613,48 +7613,48 @@
 #define NRF_LOG_USES_COLORS 0
 #endif
 //  NRF_LOG_COLOR_DEFAULT  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_LOG_COLOR_DEFAULT
 #define NRF_LOG_COLOR_DEFAULT 0
 #endif
 
 //  NRF_LOG_ERROR_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_LOG_ERROR_COLOR
 #define NRF_LOG_ERROR_COLOR 2
 #endif
 
 //  NRF_LOG_WARNING_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_LOG_WARNING_COLOR
 #define NRF_LOG_WARNING_COLOR 4
@@ -7669,17 +7669,17 @@
 #ifndef NRF_LOG_USES_TIMESTAMP
 #define NRF_LOG_USES_TIMESTAMP 0
 #endif
-//  NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY - Default frequency of the timestamp (in Hz) or 0 to use app_timer frequency. 
+//  NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY - Default frequency of the timestamp (in Hz) or 0 to use app_timer frequency.
 #ifndef NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY
 #define NRF_LOG_TIMESTAMP_DEFAULT_FREQUENCY 0
 #endif
 
 // 
 
-//  nrf_log module configuration 
+//  nrf_log module configuration
 
 //==========================================================
-//  nrf_log in nRF_Core 
+//  nrf_log in nRF_Core
 
 //==========================================================
 //  NRF_MPU_LIB_CONFIG_LOG_ENABLED - Enables logging in the module.
@@ -7688,44 +7688,44 @@
 #define NRF_MPU_LIB_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_MPU_LIB_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_MPU_LIB_CONFIG_LOG_LEVEL
 #define NRF_MPU_LIB_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_MPU_LIB_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_MPU_LIB_CONFIG_INFO_COLOR
 #define NRF_MPU_LIB_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_MPU_LIB_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_MPU_LIB_CONFIG_DEBUG_COLOR
 #define NRF_MPU_LIB_CONFIG_DEBUG_COLOR 0
@@ -7739,44 +7739,44 @@
 #define NRF_STACK_GUARD_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_STACK_GUARD_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_STACK_GUARD_CONFIG_LOG_LEVEL
 #define NRF_STACK_GUARD_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_STACK_GUARD_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_STACK_GUARD_CONFIG_INFO_COLOR
 #define NRF_STACK_GUARD_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_STACK_GUARD_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_STACK_GUARD_CONFIG_DEBUG_COLOR
 #define NRF_STACK_GUARD_CONFIG_DEBUG_COLOR 0
@@ -7790,44 +7790,44 @@
 #define TASK_MANAGER_CONFIG_LOG_ENABLED 0
 #endif
 //  TASK_MANAGER_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef TASK_MANAGER_CONFIG_LOG_LEVEL
 #define TASK_MANAGER_CONFIG_LOG_LEVEL 3
 #endif
 
 //  TASK_MANAGER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef TASK_MANAGER_CONFIG_INFO_COLOR
 #define TASK_MANAGER_CONFIG_INFO_COLOR 0
 #endif
 
 //  TASK_MANAGER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef TASK_MANAGER_CONFIG_DEBUG_COLOR
 #define TASK_MANAGER_CONFIG_DEBUG_COLOR 0
@@ -7835,10 +7835,10 @@
 
 // 
 
-//  
+// 
 //==========================================================
 
-//  nrf_log in nRF_Drivers 
+//  nrf_log in nRF_Drivers
 
 //==========================================================
 //  CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module.
@@ -7847,44 +7847,44 @@
 #define CLOCK_CONFIG_LOG_ENABLED 0
 #endif
 //  CLOCK_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef CLOCK_CONFIG_LOG_LEVEL
 #define CLOCK_CONFIG_LOG_LEVEL 3
 #endif
 
 //  CLOCK_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef CLOCK_CONFIG_INFO_COLOR
 #define CLOCK_CONFIG_INFO_COLOR 0
 #endif
 
 //  CLOCK_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef CLOCK_CONFIG_DEBUG_COLOR
 #define CLOCK_CONFIG_DEBUG_COLOR 0
@@ -7898,44 +7898,44 @@
 #define COMP_CONFIG_LOG_ENABLED 0
 #endif
 //  COMP_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef COMP_CONFIG_LOG_LEVEL
 #define COMP_CONFIG_LOG_LEVEL 3
 #endif
 
 //  COMP_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef COMP_CONFIG_INFO_COLOR
 #define COMP_CONFIG_INFO_COLOR 0
 #endif
 
 //  COMP_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef COMP_CONFIG_DEBUG_COLOR
 #define COMP_CONFIG_DEBUG_COLOR 0
@@ -7949,44 +7949,44 @@
 #define GPIOTE_CONFIG_LOG_ENABLED 0
 #endif
 //  GPIOTE_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef GPIOTE_CONFIG_LOG_LEVEL
 #define GPIOTE_CONFIG_LOG_LEVEL 3
 #endif
 
 //  GPIOTE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef GPIOTE_CONFIG_INFO_COLOR
 #define GPIOTE_CONFIG_INFO_COLOR 0
 #endif
 
 //  GPIOTE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef GPIOTE_CONFIG_DEBUG_COLOR
 #define GPIOTE_CONFIG_DEBUG_COLOR 0
@@ -8000,44 +8000,44 @@
 #define LPCOMP_CONFIG_LOG_ENABLED 0
 #endif
 //  LPCOMP_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef LPCOMP_CONFIG_LOG_LEVEL
 #define LPCOMP_CONFIG_LOG_LEVEL 3
 #endif
 
 //  LPCOMP_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef LPCOMP_CONFIG_INFO_COLOR
 #define LPCOMP_CONFIG_INFO_COLOR 0
 #endif
 
 //  LPCOMP_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef LPCOMP_CONFIG_DEBUG_COLOR
 #define LPCOMP_CONFIG_DEBUG_COLOR 0
@@ -8051,44 +8051,44 @@
 #define MAX3421E_HOST_CONFIG_LOG_ENABLED 0
 #endif
 //  MAX3421E_HOST_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef MAX3421E_HOST_CONFIG_LOG_LEVEL
 #define MAX3421E_HOST_CONFIG_LOG_LEVEL 3
 #endif
 
 //  MAX3421E_HOST_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef MAX3421E_HOST_CONFIG_INFO_COLOR
 #define MAX3421E_HOST_CONFIG_INFO_COLOR 0
 #endif
 
 //  MAX3421E_HOST_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef MAX3421E_HOST_CONFIG_DEBUG_COLOR
 #define MAX3421E_HOST_CONFIG_DEBUG_COLOR 0
@@ -8102,44 +8102,44 @@
 #define NRFX_USBD_CONFIG_LOG_ENABLED 0
 #endif
 //  NRFX_USBD_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRFX_USBD_CONFIG_LOG_LEVEL
 #define NRFX_USBD_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRFX_USBD_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_USBD_CONFIG_INFO_COLOR
 #define NRFX_USBD_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRFX_USBD_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRFX_USBD_CONFIG_DEBUG_COLOR
 #define NRFX_USBD_CONFIG_DEBUG_COLOR 0
@@ -8153,44 +8153,44 @@
 #define PDM_CONFIG_LOG_ENABLED 0
 #endif
 //  PDM_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef PDM_CONFIG_LOG_LEVEL
 #define PDM_CONFIG_LOG_LEVEL 3
 #endif
 
 //  PDM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef PDM_CONFIG_INFO_COLOR
 #define PDM_CONFIG_INFO_COLOR 0
 #endif
 
 //  PDM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef PDM_CONFIG_DEBUG_COLOR
 #define PDM_CONFIG_DEBUG_COLOR 0
@@ -8204,44 +8204,44 @@
 #define PPI_CONFIG_LOG_ENABLED 0
 #endif
 //  PPI_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef PPI_CONFIG_LOG_LEVEL
 #define PPI_CONFIG_LOG_LEVEL 3
 #endif
 
 //  PPI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef PPI_CONFIG_INFO_COLOR
 #define PPI_CONFIG_INFO_COLOR 0
 #endif
 
 //  PPI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef PPI_CONFIG_DEBUG_COLOR
 #define PPI_CONFIG_DEBUG_COLOR 0
@@ -8255,44 +8255,44 @@
 #define PWM_CONFIG_LOG_ENABLED 0
 #endif
 //  PWM_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef PWM_CONFIG_LOG_LEVEL
 #define PWM_CONFIG_LOG_LEVEL 3
 #endif
 
 //  PWM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef PWM_CONFIG_INFO_COLOR
 #define PWM_CONFIG_INFO_COLOR 0
 #endif
 
 //  PWM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef PWM_CONFIG_DEBUG_COLOR
 #define PWM_CONFIG_DEBUG_COLOR 0
@@ -8306,44 +8306,44 @@
 #define QDEC_CONFIG_LOG_ENABLED 0
 #endif
 //  QDEC_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef QDEC_CONFIG_LOG_LEVEL
 #define QDEC_CONFIG_LOG_LEVEL 3
 #endif
 
 //  QDEC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef QDEC_CONFIG_INFO_COLOR
 #define QDEC_CONFIG_INFO_COLOR 0
 #endif
 
 //  QDEC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef QDEC_CONFIG_DEBUG_COLOR
 #define QDEC_CONFIG_DEBUG_COLOR 0
@@ -8357,51 +8357,51 @@
 #define RNG_CONFIG_LOG_ENABLED 0
 #endif
 //  RNG_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef RNG_CONFIG_LOG_LEVEL
 #define RNG_CONFIG_LOG_LEVEL 3
 #endif
 
 //  RNG_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef RNG_CONFIG_INFO_COLOR
 #define RNG_CONFIG_INFO_COLOR 0
 #endif
 
 //  RNG_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef RNG_CONFIG_DEBUG_COLOR
 #define RNG_CONFIG_DEBUG_COLOR 0
 #endif
 
 //  RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED  - Enables logging of random numbers.
- 
+
 
 #ifndef RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED
 #define RNG_CONFIG_RANDOM_NUMBER_LOG_ENABLED 0
@@ -8415,44 +8415,44 @@
 #define RTC_CONFIG_LOG_ENABLED 0
 #endif
 //  RTC_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef RTC_CONFIG_LOG_LEVEL
 #define RTC_CONFIG_LOG_LEVEL 3
 #endif
 
 //  RTC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef RTC_CONFIG_INFO_COLOR
 #define RTC_CONFIG_INFO_COLOR 0
 #endif
 
 //  RTC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef RTC_CONFIG_DEBUG_COLOR
 #define RTC_CONFIG_DEBUG_COLOR 0
@@ -8466,44 +8466,44 @@
 #define SAADC_CONFIG_LOG_ENABLED 0
 #endif
 //  SAADC_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef SAADC_CONFIG_LOG_LEVEL
 #define SAADC_CONFIG_LOG_LEVEL 3
 #endif
 
 //  SAADC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef SAADC_CONFIG_INFO_COLOR
 #define SAADC_CONFIG_INFO_COLOR 0
 #endif
 
 //  SAADC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef SAADC_CONFIG_DEBUG_COLOR
 #define SAADC_CONFIG_DEBUG_COLOR 0
@@ -8517,44 +8517,44 @@
 #define SPIS_CONFIG_LOG_ENABLED 0
 #endif
 //  SPIS_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef SPIS_CONFIG_LOG_LEVEL
 #define SPIS_CONFIG_LOG_LEVEL 3
 #endif
 
 //  SPIS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef SPIS_CONFIG_INFO_COLOR
 #define SPIS_CONFIG_INFO_COLOR 0
 #endif
 
 //  SPIS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef SPIS_CONFIG_DEBUG_COLOR
 #define SPIS_CONFIG_DEBUG_COLOR 0
@@ -8568,44 +8568,44 @@
 #define SPI_CONFIG_LOG_ENABLED 0
 #endif
 //  SPI_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef SPI_CONFIG_LOG_LEVEL
 #define SPI_CONFIG_LOG_LEVEL 3
 #endif
 
 //  SPI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef SPI_CONFIG_INFO_COLOR
 #define SPI_CONFIG_INFO_COLOR 0
 #endif
 
 //  SPI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef SPI_CONFIG_DEBUG_COLOR
 #define SPI_CONFIG_DEBUG_COLOR 0
@@ -8619,44 +8619,44 @@
 #define TIMER_CONFIG_LOG_ENABLED 0
 #endif
 //  TIMER_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef TIMER_CONFIG_LOG_LEVEL
 #define TIMER_CONFIG_LOG_LEVEL 3
 #endif
 
 //  TIMER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef TIMER_CONFIG_INFO_COLOR
 #define TIMER_CONFIG_INFO_COLOR 0
 #endif
 
 //  TIMER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef TIMER_CONFIG_DEBUG_COLOR
 #define TIMER_CONFIG_DEBUG_COLOR 0
@@ -8670,44 +8670,44 @@
 #define TWIS_CONFIG_LOG_ENABLED 0
 #endif
 //  TWIS_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef TWIS_CONFIG_LOG_LEVEL
 #define TWIS_CONFIG_LOG_LEVEL 3
 #endif
 
 //  TWIS_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef TWIS_CONFIG_INFO_COLOR
 #define TWIS_CONFIG_INFO_COLOR 0
 #endif
 
 //  TWIS_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef TWIS_CONFIG_DEBUG_COLOR
 #define TWIS_CONFIG_DEBUG_COLOR 0
@@ -8721,44 +8721,44 @@
 #define TWI_CONFIG_LOG_ENABLED 0
 #endif
 //  TWI_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef TWI_CONFIG_LOG_LEVEL
 #define TWI_CONFIG_LOG_LEVEL 3
 #endif
 
 //  TWI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef TWI_CONFIG_INFO_COLOR
 #define TWI_CONFIG_INFO_COLOR 0
 #endif
 
 //  TWI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef TWI_CONFIG_DEBUG_COLOR
 #define TWI_CONFIG_DEBUG_COLOR 0
@@ -8772,44 +8772,44 @@
 #define UART_CONFIG_LOG_ENABLED 0
 #endif
 //  UART_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef UART_CONFIG_LOG_LEVEL
 #define UART_CONFIG_LOG_LEVEL 3
 #endif
 
 //  UART_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef UART_CONFIG_INFO_COLOR
 #define UART_CONFIG_INFO_COLOR 0
 #endif
 
 //  UART_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef UART_CONFIG_DEBUG_COLOR
 #define UART_CONFIG_DEBUG_COLOR 0
@@ -8823,44 +8823,44 @@
 #define USBD_CONFIG_LOG_ENABLED 0
 #endif
 //  USBD_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef USBD_CONFIG_LOG_LEVEL
 #define USBD_CONFIG_LOG_LEVEL 3
 #endif
 
 //  USBD_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef USBD_CONFIG_INFO_COLOR
 #define USBD_CONFIG_INFO_COLOR 0
 #endif
 
 //  USBD_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef USBD_CONFIG_DEBUG_COLOR
 #define USBD_CONFIG_DEBUG_COLOR 0
@@ -8874,44 +8874,44 @@
 #define WDT_CONFIG_LOG_ENABLED 0
 #endif
 //  WDT_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef WDT_CONFIG_LOG_LEVEL
 #define WDT_CONFIG_LOG_LEVEL 3
 #endif
 
 //  WDT_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef WDT_CONFIG_INFO_COLOR
 #define WDT_CONFIG_INFO_COLOR 0
 #endif
 
 //  WDT_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef WDT_CONFIG_DEBUG_COLOR
 #define WDT_CONFIG_DEBUG_COLOR 0
@@ -8919,10 +8919,10 @@
 
 // 
 
-//  
+// 
 //==========================================================
 
-//  nrf_log in nRF_Libraries 
+//  nrf_log in nRF_Libraries
 
 //==========================================================
 //  APP_BUTTON_CONFIG_LOG_ENABLED - Enables logging in the module.
@@ -8931,60 +8931,60 @@
 #define APP_BUTTON_CONFIG_LOG_ENABLED 0
 #endif
 //  APP_BUTTON_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef APP_BUTTON_CONFIG_LOG_LEVEL
 #define APP_BUTTON_CONFIG_LOG_LEVEL 3
 #endif
 
 //  APP_BUTTON_CONFIG_INITIAL_LOG_LEVEL  - Initial severity level if dynamic filtering is enabled.
- 
+
 
 //  If module generates a lot of logs, initial log level can
 //  be decreased to prevent flooding. Severity level can be
 //  increased on instance basis.
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef APP_BUTTON_CONFIG_INITIAL_LOG_LEVEL
 #define APP_BUTTON_CONFIG_INITIAL_LOG_LEVEL 3
 #endif
 
 //  APP_BUTTON_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef APP_BUTTON_CONFIG_INFO_COLOR
 #define APP_BUTTON_CONFIG_INFO_COLOR 0
 #endif
 
 //  APP_BUTTON_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef APP_BUTTON_CONFIG_DEBUG_COLOR
 #define APP_BUTTON_CONFIG_DEBUG_COLOR 0
@@ -8998,60 +8998,60 @@
 #define APP_TIMER_CONFIG_LOG_ENABLED 0
 #endif
 //  APP_TIMER_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef APP_TIMER_CONFIG_LOG_LEVEL
 #define APP_TIMER_CONFIG_LOG_LEVEL 3
 #endif
 
 //  APP_TIMER_CONFIG_INITIAL_LOG_LEVEL  - Initial severity level if dynamic filtering is enabled.
- 
+
 
 //  If module generates a lot of logs, initial log level can
 //  be decreased to prevent flooding. Severity level can be
 //  increased on instance basis.
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef APP_TIMER_CONFIG_INITIAL_LOG_LEVEL
 #define APP_TIMER_CONFIG_INITIAL_LOG_LEVEL 3
 #endif
 
 //  APP_TIMER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef APP_TIMER_CONFIG_INFO_COLOR
 #define APP_TIMER_CONFIG_INFO_COLOR 0
 #endif
 
 //  APP_TIMER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef APP_TIMER_CONFIG_DEBUG_COLOR
 #define APP_TIMER_CONFIG_DEBUG_COLOR 0
@@ -9065,44 +9065,44 @@
 #define APP_USBD_CDC_ACM_CONFIG_LOG_ENABLED 0
 #endif
 //  APP_USBD_CDC_ACM_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef APP_USBD_CDC_ACM_CONFIG_LOG_LEVEL
 #define APP_USBD_CDC_ACM_CONFIG_LOG_LEVEL 3
 #endif
 
 //  APP_USBD_CDC_ACM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef APP_USBD_CDC_ACM_CONFIG_INFO_COLOR
 #define APP_USBD_CDC_ACM_CONFIG_INFO_COLOR 0
 #endif
 
 //  APP_USBD_CDC_ACM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef APP_USBD_CDC_ACM_CONFIG_DEBUG_COLOR
 #define APP_USBD_CDC_ACM_CONFIG_DEBUG_COLOR 0
@@ -9116,44 +9116,44 @@
 #define APP_USBD_CONFIG_LOG_ENABLED 0
 #endif
 //  APP_USBD_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef APP_USBD_CONFIG_LOG_LEVEL
 #define APP_USBD_CONFIG_LOG_LEVEL 3
 #endif
 
 //  APP_USBD_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef APP_USBD_CONFIG_INFO_COLOR
 #define APP_USBD_CONFIG_INFO_COLOR 0
 #endif
 
 //  APP_USBD_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef APP_USBD_CONFIG_DEBUG_COLOR
 #define APP_USBD_CONFIG_DEBUG_COLOR 0
@@ -9167,44 +9167,44 @@
 #define APP_USBD_DUMMY_CONFIG_LOG_ENABLED 0
 #endif
 //  APP_USBD_DUMMY_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef APP_USBD_DUMMY_CONFIG_LOG_LEVEL
 #define APP_USBD_DUMMY_CONFIG_LOG_LEVEL 3
 #endif
 
 //  APP_USBD_DUMMY_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef APP_USBD_DUMMY_CONFIG_INFO_COLOR
 #define APP_USBD_DUMMY_CONFIG_INFO_COLOR 0
 #endif
 
 //  APP_USBD_DUMMY_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef APP_USBD_DUMMY_CONFIG_DEBUG_COLOR
 #define APP_USBD_DUMMY_CONFIG_DEBUG_COLOR 0
@@ -9218,44 +9218,44 @@
 #define APP_USBD_MSC_CONFIG_LOG_ENABLED 0
 #endif
 //  APP_USBD_MSC_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef APP_USBD_MSC_CONFIG_LOG_LEVEL
 #define APP_USBD_MSC_CONFIG_LOG_LEVEL 3
 #endif
 
 //  APP_USBD_MSC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef APP_USBD_MSC_CONFIG_INFO_COLOR
 #define APP_USBD_MSC_CONFIG_INFO_COLOR 0
 #endif
 
 //  APP_USBD_MSC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef APP_USBD_MSC_CONFIG_DEBUG_COLOR
 #define APP_USBD_MSC_CONFIG_DEBUG_COLOR 0
@@ -9269,44 +9269,44 @@
 #define APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_ENABLED 0
 #endif
 //  APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_LEVEL
 #define APP_USBD_NRF_DFU_TRIGGER_CONFIG_LOG_LEVEL 3
 #endif
 
 //  APP_USBD_NRF_DFU_TRIGGER_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_INFO_COLOR
 #define APP_USBD_NRF_DFU_TRIGGER_CONFIG_INFO_COLOR 0
 #endif
 
 //  APP_USBD_NRF_DFU_TRIGGER_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef APP_USBD_NRF_DFU_TRIGGER_CONFIG_DEBUG_COLOR
 #define APP_USBD_NRF_DFU_TRIGGER_CONFIG_DEBUG_COLOR 0
@@ -9320,56 +9320,56 @@
 #define NRF_ATFIFO_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_ATFIFO_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_ATFIFO_CONFIG_LOG_LEVEL
 #define NRF_ATFIFO_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_ATFIFO_CONFIG_LOG_INIT_FILTER_LEVEL  - Initial severity level if dynamic filtering is enabled
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_ATFIFO_CONFIG_LOG_INIT_FILTER_LEVEL
 #define NRF_ATFIFO_CONFIG_LOG_INIT_FILTER_LEVEL 3
 #endif
 
 //  NRF_ATFIFO_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_ATFIFO_CONFIG_INFO_COLOR
 #define NRF_ATFIFO_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_ATFIFO_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_ATFIFO_CONFIG_DEBUG_COLOR
 #define NRF_ATFIFO_CONFIG_DEBUG_COLOR 0
@@ -9383,60 +9383,60 @@
 #define NRF_BALLOC_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_BALLOC_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_BALLOC_CONFIG_LOG_LEVEL
 #define NRF_BALLOC_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL  - Initial severity level if dynamic filtering is enabled.
- 
+
 
 //  If module generates a lot of logs, initial log level can
 //  be decreased to prevent flooding. Severity level can be
 //  increased on instance basis.
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL
 #define NRF_BALLOC_CONFIG_INITIAL_LOG_LEVEL 3
 #endif
 
 //  NRF_BALLOC_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_BALLOC_CONFIG_INFO_COLOR
 #define NRF_BALLOC_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_BALLOC_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_BALLOC_CONFIG_DEBUG_COLOR
 #define NRF_BALLOC_CONFIG_DEBUG_COLOR 0
@@ -9450,56 +9450,56 @@
 #define NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_LEVEL
 #define NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_INIT_FILTER_LEVEL  - Initial severity level if dynamic filtering is enabled
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_INIT_FILTER_LEVEL
 #define NRF_BLOCK_DEV_EMPTY_CONFIG_LOG_INIT_FILTER_LEVEL 3
 #endif
 
 //  NRF_BLOCK_DEV_EMPTY_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_INFO_COLOR
 #define NRF_BLOCK_DEV_EMPTY_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_BLOCK_DEV_EMPTY_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_BLOCK_DEV_EMPTY_CONFIG_DEBUG_COLOR
 #define NRF_BLOCK_DEV_EMPTY_CONFIG_DEBUG_COLOR 0
@@ -9513,56 +9513,56 @@
 #define NRF_BLOCK_DEV_QSPI_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_BLOCK_DEV_QSPI_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_BLOCK_DEV_QSPI_CONFIG_LOG_LEVEL
 #define NRF_BLOCK_DEV_QSPI_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_BLOCK_DEV_QSPI_CONFIG_LOG_INIT_FILTER_LEVEL  - Initial severity level if dynamic filtering is enabled
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_BLOCK_DEV_QSPI_CONFIG_LOG_INIT_FILTER_LEVEL
 #define NRF_BLOCK_DEV_QSPI_CONFIG_LOG_INIT_FILTER_LEVEL 3
 #endif
 
 //  NRF_BLOCK_DEV_QSPI_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_BLOCK_DEV_QSPI_CONFIG_INFO_COLOR
 #define NRF_BLOCK_DEV_QSPI_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_BLOCK_DEV_QSPI_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_BLOCK_DEV_QSPI_CONFIG_DEBUG_COLOR
 #define NRF_BLOCK_DEV_QSPI_CONFIG_DEBUG_COLOR 0
@@ -9576,56 +9576,56 @@
 #define NRF_BLOCK_DEV_RAM_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_BLOCK_DEV_RAM_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_BLOCK_DEV_RAM_CONFIG_LOG_LEVEL
 #define NRF_BLOCK_DEV_RAM_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_BLOCK_DEV_RAM_CONFIG_LOG_INIT_FILTER_LEVEL  - Initial severity level if dynamic filtering is enabled
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_BLOCK_DEV_RAM_CONFIG_LOG_INIT_FILTER_LEVEL
 #define NRF_BLOCK_DEV_RAM_CONFIG_LOG_INIT_FILTER_LEVEL 3
 #endif
 
 //  NRF_BLOCK_DEV_RAM_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_BLOCK_DEV_RAM_CONFIG_INFO_COLOR
 #define NRF_BLOCK_DEV_RAM_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_BLOCK_DEV_RAM_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_BLOCK_DEV_RAM_CONFIG_DEBUG_COLOR
 #define NRF_BLOCK_DEV_RAM_CONFIG_DEBUG_COLOR 0
@@ -9639,44 +9639,44 @@
 #define NRF_CLI_BLE_UART_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_CLI_BLE_UART_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_CLI_BLE_UART_CONFIG_LOG_LEVEL
 #define NRF_CLI_BLE_UART_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_CLI_BLE_UART_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_CLI_BLE_UART_CONFIG_INFO_COLOR
 #define NRF_CLI_BLE_UART_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_CLI_BLE_UART_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_CLI_BLE_UART_CONFIG_DEBUG_COLOR
 #define NRF_CLI_BLE_UART_CONFIG_DEBUG_COLOR 0
@@ -9690,44 +9690,44 @@
 #define NRF_CLI_LIBUARTE_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_CLI_LIBUARTE_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_CLI_LIBUARTE_CONFIG_LOG_LEVEL
 #define NRF_CLI_LIBUARTE_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_CLI_LIBUARTE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_CLI_LIBUARTE_CONFIG_INFO_COLOR
 #define NRF_CLI_LIBUARTE_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_CLI_LIBUARTE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_CLI_LIBUARTE_CONFIG_DEBUG_COLOR
 #define NRF_CLI_LIBUARTE_CONFIG_DEBUG_COLOR 0
@@ -9741,44 +9741,44 @@
 #define NRF_CLI_UART_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_CLI_UART_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_CLI_UART_CONFIG_LOG_LEVEL
 #define NRF_CLI_UART_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_CLI_UART_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_CLI_UART_CONFIG_INFO_COLOR
 #define NRF_CLI_UART_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_CLI_UART_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_CLI_UART_CONFIG_DEBUG_COLOR
 #define NRF_CLI_UART_CONFIG_DEBUG_COLOR 0
@@ -9792,44 +9792,44 @@
 #define NRF_LIBUARTE_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_LIBUARTE_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_LIBUARTE_CONFIG_LOG_LEVEL
 #define NRF_LIBUARTE_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_LIBUARTE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_LIBUARTE_CONFIG_INFO_COLOR
 #define NRF_LIBUARTE_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_LIBUARTE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_LIBUARTE_CONFIG_DEBUG_COLOR
 #define NRF_LIBUARTE_CONFIG_DEBUG_COLOR 0
@@ -9843,44 +9843,44 @@
 #define NRF_MEMOBJ_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_MEMOBJ_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_MEMOBJ_CONFIG_LOG_LEVEL
 #define NRF_MEMOBJ_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_MEMOBJ_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_MEMOBJ_CONFIG_INFO_COLOR
 #define NRF_MEMOBJ_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_MEMOBJ_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_MEMOBJ_CONFIG_DEBUG_COLOR
 #define NRF_MEMOBJ_CONFIG_DEBUG_COLOR 0
@@ -9894,44 +9894,44 @@
 #define NRF_PWR_MGMT_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_PWR_MGMT_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_PWR_MGMT_CONFIG_LOG_LEVEL
 #define NRF_PWR_MGMT_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_PWR_MGMT_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_PWR_MGMT_CONFIG_INFO_COLOR
 #define NRF_PWR_MGMT_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_PWR_MGMT_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_PWR_MGMT_CONFIG_DEBUG_COLOR
 #define NRF_PWR_MGMT_CONFIG_DEBUG_COLOR 0
@@ -9945,56 +9945,56 @@
 #define NRF_QUEUE_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_QUEUE_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_QUEUE_CONFIG_LOG_LEVEL
 #define NRF_QUEUE_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_QUEUE_CONFIG_LOG_INIT_FILTER_LEVEL  - Initial severity level if dynamic filtering is enabled
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_QUEUE_CONFIG_LOG_INIT_FILTER_LEVEL
 #define NRF_QUEUE_CONFIG_LOG_INIT_FILTER_LEVEL 3
 #endif
 
 //  NRF_QUEUE_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_QUEUE_CONFIG_INFO_COLOR
 #define NRF_QUEUE_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_QUEUE_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_QUEUE_CONFIG_DEBUG_COLOR
 #define NRF_QUEUE_CONFIG_DEBUG_COLOR 0
@@ -10008,44 +10008,44 @@
 #define NRF_SDH_ANT_LOG_ENABLED 0
 #endif
 //  NRF_SDH_ANT_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_SDH_ANT_LOG_LEVEL
 #define NRF_SDH_ANT_LOG_LEVEL 3
 #endif
 
 //  NRF_SDH_ANT_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_SDH_ANT_INFO_COLOR
 #define NRF_SDH_ANT_INFO_COLOR 0
 #endif
 
 //  NRF_SDH_ANT_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_SDH_ANT_DEBUG_COLOR
 #define NRF_SDH_ANT_DEBUG_COLOR 0
@@ -10059,44 +10059,44 @@
 #define NRF_SDH_BLE_LOG_ENABLED 1
 #endif
 //  NRF_SDH_BLE_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_SDH_BLE_LOG_LEVEL
 #define NRF_SDH_BLE_LOG_LEVEL 3
 #endif
 
 //  NRF_SDH_BLE_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_SDH_BLE_INFO_COLOR
 #define NRF_SDH_BLE_INFO_COLOR 0
 #endif
 
 //  NRF_SDH_BLE_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_SDH_BLE_DEBUG_COLOR
 #define NRF_SDH_BLE_DEBUG_COLOR 0
@@ -10110,44 +10110,44 @@
 #define NRF_SDH_LOG_ENABLED 1
 #endif
 //  NRF_SDH_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_SDH_LOG_LEVEL
 #define NRF_SDH_LOG_LEVEL 3
 #endif
 
 //  NRF_SDH_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_SDH_INFO_COLOR
 #define NRF_SDH_INFO_COLOR 0
 #endif
 
 //  NRF_SDH_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_SDH_DEBUG_COLOR
 #define NRF_SDH_DEBUG_COLOR 0
@@ -10161,44 +10161,44 @@
 #define NRF_SDH_SOC_LOG_ENABLED 1
 #endif
 //  NRF_SDH_SOC_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_SDH_SOC_LOG_LEVEL
 #define NRF_SDH_SOC_LOG_LEVEL 3
 #endif
 
 //  NRF_SDH_SOC_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_SDH_SOC_INFO_COLOR
 #define NRF_SDH_SOC_INFO_COLOR 0
 #endif
 
 //  NRF_SDH_SOC_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_SDH_SOC_DEBUG_COLOR
 #define NRF_SDH_SOC_DEBUG_COLOR 0
@@ -10212,44 +10212,44 @@
 #define NRF_SORTLIST_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_SORTLIST_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_SORTLIST_CONFIG_LOG_LEVEL
 #define NRF_SORTLIST_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_SORTLIST_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_SORTLIST_CONFIG_INFO_COLOR
 #define NRF_SORTLIST_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_SORTLIST_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_SORTLIST_CONFIG_DEBUG_COLOR
 #define NRF_SORTLIST_CONFIG_DEBUG_COLOR 0
@@ -10263,44 +10263,44 @@
 #define NRF_TWI_SENSOR_CONFIG_LOG_ENABLED 0
 #endif
 //  NRF_TWI_SENSOR_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NRF_TWI_SENSOR_CONFIG_LOG_LEVEL
 #define NRF_TWI_SENSOR_CONFIG_LOG_LEVEL 3
 #endif
 
 //  NRF_TWI_SENSOR_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_TWI_SENSOR_CONFIG_INFO_COLOR
 #define NRF_TWI_SENSOR_CONFIG_INFO_COLOR 0
 #endif
 
 //  NRF_TWI_SENSOR_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NRF_TWI_SENSOR_CONFIG_DEBUG_COLOR
 #define NRF_TWI_SENSOR_CONFIG_DEBUG_COLOR 0
@@ -10314,44 +10314,44 @@
 #define PM_LOG_ENABLED 1
 #endif
 //  PM_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef PM_LOG_LEVEL
 #define PM_LOG_LEVEL 3
 #endif
 
 //  PM_LOG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef PM_LOG_INFO_COLOR
 #define PM_LOG_INFO_COLOR 0
 #endif
 
 //  PM_LOG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef PM_LOG_DEBUG_COLOR
 #define PM_LOG_DEBUG_COLOR 0
@@ -10359,10 +10359,10 @@
 
 // 
 
-//  
+// 
 //==========================================================
 
-//  nrf_log in nRF_Serialization 
+//  nrf_log in nRF_Serialization
 
 //==========================================================
 //  SER_HAL_TRANSPORT_CONFIG_LOG_ENABLED - Enables logging in the module.
@@ -10371,44 +10371,44 @@
 #define SER_HAL_TRANSPORT_CONFIG_LOG_ENABLED 0
 #endif
 //  SER_HAL_TRANSPORT_CONFIG_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef SER_HAL_TRANSPORT_CONFIG_LOG_LEVEL
 #define SER_HAL_TRANSPORT_CONFIG_LOG_LEVEL 3
 #endif
 
 //  SER_HAL_TRANSPORT_CONFIG_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef SER_HAL_TRANSPORT_CONFIG_INFO_COLOR
 #define SER_HAL_TRANSPORT_CONFIG_INFO_COLOR 0
 #endif
 
 //  SER_HAL_TRANSPORT_CONFIG_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef SER_HAL_TRANSPORT_CONFIG_DEBUG_COLOR
 #define SER_HAL_TRANSPORT_CONFIG_DEBUG_COLOR 0
@@ -10416,36 +10416,36 @@
 
 // 
 
-//  
+// 
 //==========================================================
 
-//  
+// 
 //==========================================================
 
 // 
 
 //  NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED  - nrf_log_str_formatter - Log string formatter
- 
+
 
 #ifndef NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED
 #define NRF_LOG_STR_FORMATTER_TIMESTAMP_FORMAT_ENABLED 1
 #endif
 
-//  
+// 
 //==========================================================
 
-//  nRF_NFC 
+//  nRF_NFC
 
 //==========================================================
 //  NFC_AC_REC_ENABLED  - nfc_ac_rec - NFC NDEF Alternative Carrier record encoder
- 
+
 
 #ifndef NFC_AC_REC_ENABLED
 #define NFC_AC_REC_ENABLED 0
 #endif
 
 //  NFC_AC_REC_PARSER_ENABLED  - nfc_ac_rec_parser - Alternative Carrier record parser
- 
+
 
 #ifndef NFC_AC_REC_PARSER_ENABLED
 #define NFC_AC_REC_PARSER_ENABLED 0
@@ -10457,9 +10457,9 @@
 #define NFC_BLE_OOB_ADVDATA_ENABLED 0
 #endif
 //  ADVANCED_ADVDATA_SUPPORT  - Non-mandatory AD types for BLE OOB pairing are encoded inside the NDEF message (e.g. service UUIDs)
- 
-// <1=> Enabled 
-// <0=> Disabled 
+
+// <1=> Enabled
+// <0=> Disabled
 
 #ifndef ADVANCED_ADVDATA_SUPPORT
 #define ADVANCED_ADVDATA_SUPPORT 0
@@ -10468,7 +10468,7 @@
 // 
 
 //  NFC_BLE_OOB_ADVDATA_PARSER_ENABLED  - nfc_ble_oob_advdata_parser - BLE OOB pairing AD data parser
- 
+
 
 #ifndef NFC_BLE_OOB_ADVDATA_PARSER_ENABLED
 #define NFC_BLE_OOB_ADVDATA_PARSER_ENABLED 0
@@ -10485,44 +10485,44 @@
 #define NFC_BLE_PAIR_LIB_LOG_ENABLED 0
 #endif
 //  NFC_BLE_PAIR_LIB_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NFC_BLE_PAIR_LIB_LOG_LEVEL
 #define NFC_BLE_PAIR_LIB_LOG_LEVEL 3
 #endif
 
 //  NFC_BLE_PAIR_LIB_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NFC_BLE_PAIR_LIB_INFO_COLOR
 #define NFC_BLE_PAIR_LIB_INFO_COLOR 0
 #endif
 
 //  NFC_BLE_PAIR_LIB_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NFC_BLE_PAIR_LIB_DEBUG_COLOR
 #define NFC_BLE_PAIR_LIB_DEBUG_COLOR 0
@@ -10541,28 +10541,28 @@
 #define BLE_NFC_SEC_PARAM_BOND 1
 #endif
 //  BLE_NFC_SEC_PARAM_KDIST_OWN_ENC  - Enables Long Term Key and Master Identification distribution by device.
- 
+
 
 #ifndef BLE_NFC_SEC_PARAM_KDIST_OWN_ENC
 #define BLE_NFC_SEC_PARAM_KDIST_OWN_ENC 1
 #endif
 
 //  BLE_NFC_SEC_PARAM_KDIST_OWN_ID  - Enables Identity Resolving Key and Identity Address Information distribution by device.
- 
+
 
 #ifndef BLE_NFC_SEC_PARAM_KDIST_OWN_ID
 #define BLE_NFC_SEC_PARAM_KDIST_OWN_ID 1
 #endif
 
 //  BLE_NFC_SEC_PARAM_KDIST_PEER_ENC  - Enables Long Term Key and Master Identification distribution by peer.
- 
+
 
 #ifndef BLE_NFC_SEC_PARAM_KDIST_PEER_ENC
 #define BLE_NFC_SEC_PARAM_KDIST_PEER_ENC 1
 #endif
 
 //  BLE_NFC_SEC_PARAM_KDIST_PEER_ID  - Enables Identity Resolving Key and Identity Address Information distribution by peer.
- 
+
 
 #ifndef BLE_NFC_SEC_PARAM_KDIST_PEER_ID
 #define BLE_NFC_SEC_PARAM_KDIST_PEER_ID 1
@@ -10571,95 +10571,95 @@
 // 
 
 //  BLE_NFC_SEC_PARAM_MIN_KEY_SIZE  - Minimal size of a security key.
- 
-// <7=> 7 
-// <8=> 8 
-// <9=> 9 
-// <10=> 10 
-// <11=> 11 
-// <12=> 12 
-// <13=> 13 
-// <14=> 14 
-// <15=> 15 
-// <16=> 16 
+
+// <7=> 7
+// <8=> 8
+// <9=> 9
+// <10=> 10
+// <11=> 11
+// <12=> 12
+// <13=> 13
+// <14=> 14
+// <15=> 15
+// <16=> 16
 
 #ifndef BLE_NFC_SEC_PARAM_MIN_KEY_SIZE
 #define BLE_NFC_SEC_PARAM_MIN_KEY_SIZE 7
 #endif
 
 //  BLE_NFC_SEC_PARAM_MAX_KEY_SIZE  - Maximal size of a security key.
- 
-// <7=> 7 
-// <8=> 8 
-// <9=> 9 
-// <10=> 10 
-// <11=> 11 
-// <12=> 12 
-// <13=> 13 
-// <14=> 14 
-// <15=> 15 
-// <16=> 16 
+
+// <7=> 7
+// <8=> 8
+// <9=> 9
+// <10=> 10
+// <11=> 11
+// <12=> 12
+// <13=> 13
+// <14=> 14
+// <15=> 15
+// <16=> 16
 
 #ifndef BLE_NFC_SEC_PARAM_MAX_KEY_SIZE
 #define BLE_NFC_SEC_PARAM_MAX_KEY_SIZE 16
 #endif
 
-//  
+// 
 //==========================================================
 
 // 
 
 //  NFC_BLE_PAIR_MSG_ENABLED  - nfc_ble_pair_msg - NDEF message for OOB pairing encoder
- 
+
 
 #ifndef NFC_BLE_PAIR_MSG_ENABLED
 #define NFC_BLE_PAIR_MSG_ENABLED 0
 #endif
 
 //  NFC_CH_COMMON_ENABLED  - nfc_ble_pair_common - OOB pairing common data
- 
+
 
 #ifndef NFC_CH_COMMON_ENABLED
 #define NFC_CH_COMMON_ENABLED 0
 #endif
 
 //  NFC_EP_OOB_REC_ENABLED  - nfc_ep_oob_rec - EP record for BLE pairing encoder
- 
+
 
 #ifndef NFC_EP_OOB_REC_ENABLED
 #define NFC_EP_OOB_REC_ENABLED 0
 #endif
 
 //  NFC_HS_REC_ENABLED  - nfc_hs_rec - Handover Select NDEF record encoder
- 
+
 
 #ifndef NFC_HS_REC_ENABLED
 #define NFC_HS_REC_ENABLED 0
 #endif
 
 //  NFC_LE_OOB_REC_ENABLED  - nfc_le_oob_rec - LE record for BLE pairing encoder
- 
+
 
 #ifndef NFC_LE_OOB_REC_ENABLED
 #define NFC_LE_OOB_REC_ENABLED 0
 #endif
 
 //  NFC_LE_OOB_REC_PARSER_ENABLED  - nfc_le_oob_rec_parser - LE record parser
- 
+
 
 #ifndef NFC_LE_OOB_REC_PARSER_ENABLED
 #define NFC_LE_OOB_REC_PARSER_ENABLED 0
 #endif
 
 //  NFC_NDEF_LAUNCHAPP_MSG_ENABLED  - nfc_launchapp_msg - Encoding data for NDEF Application Launching message for NFC Tag
- 
+
 
 #ifndef NFC_NDEF_LAUNCHAPP_MSG_ENABLED
 #define NFC_NDEF_LAUNCHAPP_MSG_ENABLED 0
 #endif
 
 //  NFC_NDEF_LAUNCHAPP_REC_ENABLED  - nfc_launchapp_rec - Encoding data for NDEF Application Launching record for NFC Tag
- 
+
 
 #ifndef NFC_NDEF_LAUNCHAPP_REC_ENABLED
 #define NFC_NDEF_LAUNCHAPP_REC_ENABLED 0
@@ -10671,9 +10671,9 @@
 #define NFC_NDEF_MSG_ENABLED 0
 #endif
 //  NFC_NDEF_MSG_TAG_TYPE  - NFC Tag Type
- 
-// <2=> Type 2 Tag 
-// <4=> Type 4 Tag 
+
+// <2=> Type 2 Tag
+// <4=> Type 4 Tag
 
 #ifndef NFC_NDEF_MSG_TAG_TYPE
 #define NFC_NDEF_MSG_TAG_TYPE 2
@@ -10692,28 +10692,28 @@
 #define NFC_NDEF_MSG_PARSER_LOG_ENABLED 0
 #endif
 //  NFC_NDEF_MSG_PARSER_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NFC_NDEF_MSG_PARSER_LOG_LEVEL
 #define NFC_NDEF_MSG_PARSER_LOG_LEVEL 3
 #endif
 
 //  NFC_NDEF_MSG_PARSER_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NFC_NDEF_MSG_PARSER_INFO_COLOR
 #define NFC_NDEF_MSG_PARSER_INFO_COLOR 0
@@ -10724,7 +10724,7 @@
 // 
 
 //  NFC_NDEF_RECORD_ENABLED  - nfc_ndef_record - NFC NDEF Record generator module
- 
+
 
 #ifndef NFC_NDEF_RECORD_ENABLED
 #define NFC_NDEF_RECORD_ENABLED 0
@@ -10741,28 +10741,28 @@
 #define NFC_NDEF_RECORD_PARSER_LOG_ENABLED 0
 #endif
 //  NFC_NDEF_RECORD_PARSER_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NFC_NDEF_RECORD_PARSER_LOG_LEVEL
 #define NFC_NDEF_RECORD_PARSER_LOG_LEVEL 3
 #endif
 
 //  NFC_NDEF_RECORD_PARSER_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NFC_NDEF_RECORD_PARSER_INFO_COLOR
 #define NFC_NDEF_RECORD_PARSER_INFO_COLOR 0
@@ -10773,21 +10773,21 @@
 // 
 
 //  NFC_NDEF_TEXT_RECORD_ENABLED  - nfc_text_rec - Encoding data for a text record for NFC Tag
- 
+
 
 #ifndef NFC_NDEF_TEXT_RECORD_ENABLED
 #define NFC_NDEF_TEXT_RECORD_ENABLED 0
 #endif
 
 //  NFC_NDEF_URI_MSG_ENABLED  - nfc_uri_msg - Encoding data for NDEF message with URI record for NFC Tag
- 
+
 
 #ifndef NFC_NDEF_URI_MSG_ENABLED
 #define NFC_NDEF_URI_MSG_ENABLED 0
 #endif
 
 //  NFC_NDEF_URI_REC_ENABLED  - nfc_uri_rec - Encoding data for a URI record for NFC Tag
- 
+
 
 #ifndef NFC_NDEF_URI_REC_ENABLED
 #define NFC_NDEF_URI_REC_ENABLED 0
@@ -10804,44 +10804,44 @@
 #define NFC_PLATFORM_LOG_ENABLED 0
 #endif
 //  NFC_PLATFORM_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NFC_PLATFORM_LOG_LEVEL
 #define NFC_PLATFORM_LOG_LEVEL 3
 #endif
 
 //  NFC_PLATFORM_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NFC_PLATFORM_INFO_COLOR
 #define NFC_PLATFORM_INFO_COLOR 0
 #endif
 
 //  NFC_PLATFORM_DEBUG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NFC_PLATFORM_DEBUG_COLOR
 #define NFC_PLATFORM_DEBUG_COLOR 0
@@ -10862,28 +10862,28 @@
 #define NFC_T2T_PARSER_LOG_ENABLED 0
 #endif
 //  NFC_T2T_PARSER_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NFC_T2T_PARSER_LOG_LEVEL
 #define NFC_T2T_PARSER_LOG_LEVEL 3
 #endif
 
 //  NFC_T2T_PARSER_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NFC_T2T_PARSER_INFO_COLOR
 #define NFC_T2T_PARSER_INFO_COLOR 0
@@ -10904,28 +10904,28 @@
 #define NFC_T4T_APDU_LOG_ENABLED 0
 #endif
 //  NFC_T4T_APDU_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NFC_T4T_APDU_LOG_LEVEL
 #define NFC_T4T_APDU_LOG_LEVEL 3
 #endif
 
 //  NFC_T4T_APDU_LOG_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NFC_T4T_APDU_LOG_COLOR
 #define NFC_T4T_APDU_LOG_COLOR 0
@@ -10946,28 +10946,28 @@
 #define NFC_T4T_CC_FILE_PARSER_LOG_ENABLED 0
 #endif
 //  NFC_T4T_CC_FILE_PARSER_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NFC_T4T_CC_FILE_PARSER_LOG_LEVEL
 #define NFC_T4T_CC_FILE_PARSER_LOG_LEVEL 3
 #endif
 
 //  NFC_T4T_CC_FILE_PARSER_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NFC_T4T_CC_FILE_PARSER_INFO_COLOR
 #define NFC_T4T_CC_FILE_PARSER_INFO_COLOR 0
@@ -10988,28 +10988,28 @@
 #define NFC_T4T_HL_DETECTION_PROCEDURES_LOG_ENABLED 0
 #endif
 //  NFC_T4T_HL_DETECTION_PROCEDURES_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NFC_T4T_HL_DETECTION_PROCEDURES_LOG_LEVEL
 #define NFC_T4T_HL_DETECTION_PROCEDURES_LOG_LEVEL 3
 #endif
 
 //  NFC_T4T_HL_DETECTION_PROCEDURES_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NFC_T4T_HL_DETECTION_PROCEDURES_INFO_COLOR
 #define NFC_T4T_HL_DETECTION_PROCEDURES_INFO_COLOR 0
@@ -11017,12 +11017,12 @@
 
 // 
 
-//  APDU_BUFF_SIZE - Size (in bytes) of the buffer for APDU storage 
+//  APDU_BUFF_SIZE - Size (in bytes) of the buffer for APDU storage
 #ifndef APDU_BUFF_SIZE
 #define APDU_BUFF_SIZE 250
 #endif
 
-//  CC_STORAGE_BUFF_SIZE - Size (in bytes) of the buffer for CC file storage 
+//  CC_STORAGE_BUFF_SIZE - Size (in bytes) of the buffer for CC file storage
 #ifndef CC_STORAGE_BUFF_SIZE
 #define CC_STORAGE_BUFF_SIZE 64
 #endif
@@ -11040,28 +11040,28 @@
 #define NFC_T4T_TLV_BLOCK_PARSER_LOG_ENABLED 0
 #endif
 //  NFC_T4T_TLV_BLOCK_PARSER_LOG_LEVEL  - Default Severity level
- 
-// <0=> Off 
-// <1=> Error 
-// <2=> Warning 
-// <3=> Info 
-// <4=> Debug 
+
+// <0=> Off
+// <1=> Error
+// <2=> Warning
+// <3=> Info
+// <4=> Debug
 
 #ifndef NFC_T4T_TLV_BLOCK_PARSER_LOG_LEVEL
 #define NFC_T4T_TLV_BLOCK_PARSER_LOG_LEVEL 3
 #endif
 
 //  NFC_T4T_TLV_BLOCK_PARSER_INFO_COLOR  - ANSI escape code prefix.
- 
-// <0=> Default 
-// <1=> Black 
-// <2=> Red 
-// <3=> Green 
-// <4=> Yellow 
-// <5=> Blue 
-// <6=> Magenta 
-// <7=> Cyan 
-// <8=> White 
+
+// <0=> Default
+// <1=> Black
+// <2=> Red
+// <3=> Green
+// <4=> Yellow
+// <5=> Blue
+// <6=> Magenta
+// <7=> Cyan
+// <8=> White
 
 #ifndef NFC_T4T_TLV_BLOCK_PARSER_INFO_COLOR
 #define NFC_T4T_TLV_BLOCK_PARSER_INFO_COLOR 0
@@ -11071,10 +11071,10 @@
 
 // 
 
-//  
+// 
 //==========================================================
 
-//  nRF_SoftDevice 
+//  nRF_SoftDevice
 
 //==========================================================
 //  NRF_SDH_BLE_ENABLED - nrf_sdh_ble - SoftDevice BLE event handler
@@ -11087,7 +11087,7 @@
 //  The SoftDevice handler will configure the stack with these parameters when calling @ref nrf_sdh_ble_default_cfg_set.
 //  Other libraries might depend on these values; keep them up-to-date even if you are not explicitely calling @ref nrf_sdh_ble_default_cfg_set.
 //==========================================================
-//  NRF_SDH_BLE_GAP_DATA_LENGTH   <27-251> 
+//  NRF_SDH_BLE_GAP_DATA_LENGTH   <27-251>
 
 
 //  Requested BLE GAP data length to be negotiated.
@@ -11096,59 +11096,59 @@
 #define NRF_SDH_BLE_GAP_DATA_LENGTH 27
 #endif
 
-//  NRF_SDH_BLE_PERIPHERAL_LINK_COUNT - Maximum number of peripheral links. 
+//  NRF_SDH_BLE_PERIPHERAL_LINK_COUNT - Maximum number of peripheral links.
 #ifndef NRF_SDH_BLE_PERIPHERAL_LINK_COUNT
 #define NRF_SDH_BLE_PERIPHERAL_LINK_COUNT 0
 #endif
 
-//  NRF_SDH_BLE_CENTRAL_LINK_COUNT - Maximum number of central links. 
+//  NRF_SDH_BLE_CENTRAL_LINK_COUNT - Maximum number of central links.
 #ifndef NRF_SDH_BLE_CENTRAL_LINK_COUNT
 #define NRF_SDH_BLE_CENTRAL_LINK_COUNT 0
 #endif
 
-//  NRF_SDH_BLE_TOTAL_LINK_COUNT - Total link count. 
+//  NRF_SDH_BLE_TOTAL_LINK_COUNT - Total link count.
 //  Maximum number of total concurrent connections using the default configuration.
 
 #ifndef NRF_SDH_BLE_TOTAL_LINK_COUNT
 #define NRF_SDH_BLE_TOTAL_LINK_COUNT 1
 #endif
 
-//  NRF_SDH_BLE_GAP_EVENT_LENGTH - GAP event length. 
+//  NRF_SDH_BLE_GAP_EVENT_LENGTH - GAP event length.
 //  The time set aside for this connection on every connection interval in 1.25 ms units.
 
 #ifndef NRF_SDH_BLE_GAP_EVENT_LENGTH
 #define NRF_SDH_BLE_GAP_EVENT_LENGTH 6
 #endif
 
-//  NRF_SDH_BLE_GATT_MAX_MTU_SIZE - Static maximum MTU size. 
+//  NRF_SDH_BLE_GATT_MAX_MTU_SIZE - Static maximum MTU size.
 #ifndef NRF_SDH_BLE_GATT_MAX_MTU_SIZE
 #define NRF_SDH_BLE_GATT_MAX_MTU_SIZE 23
 #endif
 
-//  NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE - Attribute Table size in bytes. The size must be a multiple of 4. 
+//  NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE - Attribute Table size in bytes. The size must be a multiple of 4.
 #ifndef NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE
 #define NRF_SDH_BLE_GATTS_ATTR_TAB_SIZE 1408
 #endif
 
-//  NRF_SDH_BLE_VS_UUID_COUNT - The number of vendor-specific UUIDs. 
+//  NRF_SDH_BLE_VS_UUID_COUNT - The number of vendor-specific UUIDs.
 #ifndef NRF_SDH_BLE_VS_UUID_COUNT
 #define NRF_SDH_BLE_VS_UUID_COUNT 0
 #endif
 
 //  NRF_SDH_BLE_SERVICE_CHANGED  - Include the Service Changed characteristic in the Attribute Table.
- 
+
 
 #ifndef NRF_SDH_BLE_SERVICE_CHANGED
 #define NRF_SDH_BLE_SERVICE_CHANGED 0
 #endif
 
-//  
+// 
 //==========================================================
 
 //  BLE Observers - Observers and priority levels
 
 //==========================================================
-//  NRF_SDH_BLE_OBSERVER_PRIO_LEVELS - Total number of priority levels for BLE observers. 
+//  NRF_SDH_BLE_OBSERVER_PRIO_LEVELS - Total number of priority levels for BLE observers.
 //  This setting configures the number of priority levels available for BLE event handlers.
 //  The priority level of a handler determines the order in which it receives events, with respect to other handlers.
 
@@ -11159,316 +11159,316 @@
 //  BLE Observers priorities - Invididual priorities
 
 //==========================================================
-//  BLE_ADV_BLE_OBSERVER_PRIO  
+//  BLE_ADV_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Advertising module.
 
 #ifndef BLE_ADV_BLE_OBSERVER_PRIO
 #define BLE_ADV_BLE_OBSERVER_PRIO 1
 #endif
 
-//  BLE_ANCS_C_BLE_OBSERVER_PRIO  
+//  BLE_ANCS_C_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Apple Notification Service Client.
 
 #ifndef BLE_ANCS_C_BLE_OBSERVER_PRIO
 #define BLE_ANCS_C_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_ANS_C_BLE_OBSERVER_PRIO  
+//  BLE_ANS_C_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Alert Notification Service Client.
 
 #ifndef BLE_ANS_C_BLE_OBSERVER_PRIO
 #define BLE_ANS_C_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_BAS_BLE_OBSERVER_PRIO  
+//  BLE_BAS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Battery Service.
 
 #ifndef BLE_BAS_BLE_OBSERVER_PRIO
 #define BLE_BAS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_BAS_C_BLE_OBSERVER_PRIO  
+//  BLE_BAS_C_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Battery Service Client.
 
 #ifndef BLE_BAS_C_BLE_OBSERVER_PRIO
 #define BLE_BAS_C_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_BPS_BLE_OBSERVER_PRIO  
+//  BLE_BPS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Blood Pressure Service.
 
 #ifndef BLE_BPS_BLE_OBSERVER_PRIO
 #define BLE_BPS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_CONN_PARAMS_BLE_OBSERVER_PRIO  
+//  BLE_CONN_PARAMS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Connection parameters module.
 
 #ifndef BLE_CONN_PARAMS_BLE_OBSERVER_PRIO
 #define BLE_CONN_PARAMS_BLE_OBSERVER_PRIO 1
 #endif
 
-//  BLE_CONN_STATE_BLE_OBSERVER_PRIO  
+//  BLE_CONN_STATE_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Connection State module.
 
 #ifndef BLE_CONN_STATE_BLE_OBSERVER_PRIO
 #define BLE_CONN_STATE_BLE_OBSERVER_PRIO 0
 #endif
 
-//  BLE_CSCS_BLE_OBSERVER_PRIO  
+//  BLE_CSCS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Cycling Speed and Cadence Service.
 
 #ifndef BLE_CSCS_BLE_OBSERVER_PRIO
 #define BLE_CSCS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_CTS_C_BLE_OBSERVER_PRIO  
+//  BLE_CTS_C_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Current Time Service Client.
 
 #ifndef BLE_CTS_C_BLE_OBSERVER_PRIO
 #define BLE_CTS_C_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_DB_DISC_BLE_OBSERVER_PRIO  
+//  BLE_DB_DISC_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Database Discovery module.
 
 #ifndef BLE_DB_DISC_BLE_OBSERVER_PRIO
 #define BLE_DB_DISC_BLE_OBSERVER_PRIO 1
 #endif
 
-//  BLE_DFU_BLE_OBSERVER_PRIO  
+//  BLE_DFU_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the DFU Service.
 
 #ifndef BLE_DFU_BLE_OBSERVER_PRIO
 #define BLE_DFU_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_DIS_C_BLE_OBSERVER_PRIO  
+//  BLE_DIS_C_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Device Information Client.
 
 #ifndef BLE_DIS_C_BLE_OBSERVER_PRIO
 #define BLE_DIS_C_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_GLS_BLE_OBSERVER_PRIO  
+//  BLE_GLS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Glucose Service.
 
 #ifndef BLE_GLS_BLE_OBSERVER_PRIO
 #define BLE_GLS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_HIDS_BLE_OBSERVER_PRIO  
+//  BLE_HIDS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Human Interface Device Service.
 
 #ifndef BLE_HIDS_BLE_OBSERVER_PRIO
 #define BLE_HIDS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_HRS_BLE_OBSERVER_PRIO  
+//  BLE_HRS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Heart Rate Service.
 
 #ifndef BLE_HRS_BLE_OBSERVER_PRIO
 #define BLE_HRS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_HRS_C_BLE_OBSERVER_PRIO  
+//  BLE_HRS_C_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Heart Rate Service Client.
 
 #ifndef BLE_HRS_C_BLE_OBSERVER_PRIO
 #define BLE_HRS_C_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_HTS_BLE_OBSERVER_PRIO  
+//  BLE_HTS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Health Thermometer Service.
 
 #ifndef BLE_HTS_BLE_OBSERVER_PRIO
 #define BLE_HTS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_IAS_BLE_OBSERVER_PRIO  
+//  BLE_IAS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Immediate Alert Service.
 
 #ifndef BLE_IAS_BLE_OBSERVER_PRIO
 #define BLE_IAS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_IAS_C_BLE_OBSERVER_PRIO  
+//  BLE_IAS_C_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Immediate Alert Service Client.
 
 #ifndef BLE_IAS_C_BLE_OBSERVER_PRIO
 #define BLE_IAS_C_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_LBS_BLE_OBSERVER_PRIO  
+//  BLE_LBS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the LED Button Service.
 
 #ifndef BLE_LBS_BLE_OBSERVER_PRIO
 #define BLE_LBS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_LBS_C_BLE_OBSERVER_PRIO  
+//  BLE_LBS_C_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the LED Button Service Client.
 
 #ifndef BLE_LBS_C_BLE_OBSERVER_PRIO
 #define BLE_LBS_C_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_LLS_BLE_OBSERVER_PRIO  
+//  BLE_LLS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Link Loss Service.
 
 #ifndef BLE_LLS_BLE_OBSERVER_PRIO
 #define BLE_LLS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_LNS_BLE_OBSERVER_PRIO  
+//  BLE_LNS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Location Navigation Service.
 
 #ifndef BLE_LNS_BLE_OBSERVER_PRIO
 #define BLE_LNS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_NUS_BLE_OBSERVER_PRIO  
+//  BLE_NUS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the UART Service.
 
 #ifndef BLE_NUS_BLE_OBSERVER_PRIO
 #define BLE_NUS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_NUS_C_BLE_OBSERVER_PRIO  
+//  BLE_NUS_C_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the UART Central Service.
 
 #ifndef BLE_NUS_C_BLE_OBSERVER_PRIO
 #define BLE_NUS_C_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_OTS_BLE_OBSERVER_PRIO  
+//  BLE_OTS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Object transfer service.
 
 #ifndef BLE_OTS_BLE_OBSERVER_PRIO
 #define BLE_OTS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_OTS_C_BLE_OBSERVER_PRIO  
+//  BLE_OTS_C_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Object transfer service client.
 
 #ifndef BLE_OTS_C_BLE_OBSERVER_PRIO
 #define BLE_OTS_C_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_RSCS_BLE_OBSERVER_PRIO  
+//  BLE_RSCS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Running Speed and Cadence Service.
 
 #ifndef BLE_RSCS_BLE_OBSERVER_PRIO
 #define BLE_RSCS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_RSCS_C_BLE_OBSERVER_PRIO  
+//  BLE_RSCS_C_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Running Speed and Cadence Client.
 
 #ifndef BLE_RSCS_C_BLE_OBSERVER_PRIO
 #define BLE_RSCS_C_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BLE_TPS_BLE_OBSERVER_PRIO  
+//  BLE_TPS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the TX Power Service.
 
 #ifndef BLE_TPS_BLE_OBSERVER_PRIO
 #define BLE_TPS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  BSP_BTN_BLE_OBSERVER_PRIO  
+//  BSP_BTN_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Button Control module.
 
 #ifndef BSP_BTN_BLE_OBSERVER_PRIO
 #define BSP_BTN_BLE_OBSERVER_PRIO 1
 #endif
 
-//  NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO  
+//  NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the NFC pairing library.
 
 #ifndef NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO
 #define NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO 1
 #endif
 
-//  NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO  
+//  NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the NFC pairing library.
 
 #ifndef NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO
 #define NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO 1
 #endif
 
-//  NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO  
+//  NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the NFC pairing library.
 
 #ifndef NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO
 #define NFC_BLE_PAIR_LIB_BLE_OBSERVER_PRIO 1
 #endif
 
-//  NRF_BLE_BMS_BLE_OBSERVER_PRIO  
+//  NRF_BLE_BMS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Bond Management Service.
 
 #ifndef NRF_BLE_BMS_BLE_OBSERVER_PRIO
 #define NRF_BLE_BMS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  NRF_BLE_CGMS_BLE_OBSERVER_PRIO  
+//  NRF_BLE_CGMS_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Contiuon Glucose Monitoring Service.
 
 #ifndef NRF_BLE_CGMS_BLE_OBSERVER_PRIO
 #define NRF_BLE_CGMS_BLE_OBSERVER_PRIO 2
 #endif
 
-//  NRF_BLE_ES_BLE_OBSERVER_PRIO  
+//  NRF_BLE_ES_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Eddystone module.
 
 #ifndef NRF_BLE_ES_BLE_OBSERVER_PRIO
 #define NRF_BLE_ES_BLE_OBSERVER_PRIO 2
 #endif
 
-//  NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO  
+//  NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the GATT Service Client.
 
 #ifndef NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO
 #define NRF_BLE_GATTS_C_BLE_OBSERVER_PRIO 2
 #endif
 
-//  NRF_BLE_GATT_BLE_OBSERVER_PRIO  
+//  NRF_BLE_GATT_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the GATT module.
 
 #ifndef NRF_BLE_GATT_BLE_OBSERVER_PRIO
 #define NRF_BLE_GATT_BLE_OBSERVER_PRIO 1
 #endif
 
-//  NRF_BLE_GQ_BLE_OBSERVER_PRIO  
+//  NRF_BLE_GQ_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the GATT Queue module.
 
 #ifndef NRF_BLE_GQ_BLE_OBSERVER_PRIO
 #define NRF_BLE_GQ_BLE_OBSERVER_PRIO 1
 #endif
 
-//  NRF_BLE_QWR_BLE_OBSERVER_PRIO  
+//  NRF_BLE_QWR_BLE_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the Queued writes module.
 
 #ifndef NRF_BLE_QWR_BLE_OBSERVER_PRIO
 #define NRF_BLE_QWR_BLE_OBSERVER_PRIO 2
 #endif
 
-//  NRF_BLE_SCAN_OBSERVER_PRIO  
+//  NRF_BLE_SCAN_OBSERVER_PRIO
 //  Priority for dispatching the BLE events to the Scanning Module.
 
 #ifndef NRF_BLE_SCAN_OBSERVER_PRIO
 #define NRF_BLE_SCAN_OBSERVER_PRIO 1
 #endif
 
-//  PM_BLE_OBSERVER_PRIO - Priority with which BLE events are dispatched to the Peer Manager module. 
+//  PM_BLE_OBSERVER_PRIO - Priority with which BLE events are dispatched to the Peer Manager module.
 #ifndef PM_BLE_OBSERVER_PRIO
 #define PM_BLE_OBSERVER_PRIO 1
 #endif
 
-//  
+// 
 //==========================================================
 
-//  
+// 
 //==========================================================
 
 
@@ -11479,46 +11479,46 @@
 #ifndef NRF_SDH_ENABLED
 #define NRF_SDH_ENABLED 0
 #endif
-//  Dispatch model 
+//  Dispatch model
 
 //  This setting configures how Stack events are dispatched to the application.
 //==========================================================
 //  NRF_SDH_DISPATCH_MODEL
- 
+
 
 //  NRF_SDH_DISPATCH_MODEL_INTERRUPT: SoftDevice events are passed to the application from the interrupt context.
 //  NRF_SDH_DISPATCH_MODEL_APPSH: SoftDevice events are scheduled using @ref app_scheduler.
 //  NRF_SDH_DISPATCH_MODEL_POLLING: SoftDevice events are to be fetched manually.
-// <0=> NRF_SDH_DISPATCH_MODEL_INTERRUPT 
-// <1=> NRF_SDH_DISPATCH_MODEL_APPSH 
-// <2=> NRF_SDH_DISPATCH_MODEL_POLLING 
+// <0=> NRF_SDH_DISPATCH_MODEL_INTERRUPT
+// <1=> NRF_SDH_DISPATCH_MODEL_APPSH
+// <2=> NRF_SDH_DISPATCH_MODEL_POLLING
 
 #ifndef NRF_SDH_DISPATCH_MODEL
 #define NRF_SDH_DISPATCH_MODEL 0
 #endif
 
-//  
+// 
 //==========================================================
 
 //  Clock - SoftDevice clock configuration
 
 //==========================================================
 //  NRF_SDH_CLOCK_LF_SRC  - SoftDevice clock source.
- 
-// <0=> NRF_CLOCK_LF_SRC_RC 
-// <1=> NRF_CLOCK_LF_SRC_XTAL 
-// <2=> NRF_CLOCK_LF_SRC_SYNTH 
+
+// <0=> NRF_CLOCK_LF_SRC_RC
+// <1=> NRF_CLOCK_LF_SRC_XTAL
+// <2=> NRF_CLOCK_LF_SRC_SYNTH
 
 #ifndef NRF_SDH_CLOCK_LF_SRC
 #define NRF_SDH_CLOCK_LF_SRC 1
 #endif
 
-//  NRF_SDH_CLOCK_LF_RC_CTIV - SoftDevice calibration timer interval. 
+//  NRF_SDH_CLOCK_LF_RC_CTIV - SoftDevice calibration timer interval.
 #ifndef NRF_SDH_CLOCK_LF_RC_CTIV
 #define NRF_SDH_CLOCK_LF_RC_CTIV 0
 #endif
 
-//  NRF_SDH_CLOCK_LF_RC_TEMP_CTIV - SoftDevice calibration timer interval under constant temperature. 
+//  NRF_SDH_CLOCK_LF_RC_TEMP_CTIV - SoftDevice calibration timer interval under constant temperature.
 //  How often (in number of calibration intervals) the RC oscillator shall be calibrated
 //   if the temperature has not changed.
 
@@ -11527,31 +11527,31 @@
 #endif
 
 //  NRF_SDH_CLOCK_LF_ACCURACY  - External clock accuracy used in the LL to compute timing.
- 
-// <0=> NRF_CLOCK_LF_ACCURACY_250_PPM 
-// <1=> NRF_CLOCK_LF_ACCURACY_500_PPM 
-// <2=> NRF_CLOCK_LF_ACCURACY_150_PPM 
-// <3=> NRF_CLOCK_LF_ACCURACY_100_PPM 
-// <4=> NRF_CLOCK_LF_ACCURACY_75_PPM 
-// <5=> NRF_CLOCK_LF_ACCURACY_50_PPM 
-// <6=> NRF_CLOCK_LF_ACCURACY_30_PPM 
-// <7=> NRF_CLOCK_LF_ACCURACY_20_PPM 
-// <8=> NRF_CLOCK_LF_ACCURACY_10_PPM 
-// <9=> NRF_CLOCK_LF_ACCURACY_5_PPM 
-// <10=> NRF_CLOCK_LF_ACCURACY_2_PPM 
-// <11=> NRF_CLOCK_LF_ACCURACY_1_PPM 
+
+// <0=> NRF_CLOCK_LF_ACCURACY_250_PPM
+// <1=> NRF_CLOCK_LF_ACCURACY_500_PPM
+// <2=> NRF_CLOCK_LF_ACCURACY_150_PPM
+// <3=> NRF_CLOCK_LF_ACCURACY_100_PPM
+// <4=> NRF_CLOCK_LF_ACCURACY_75_PPM
+// <5=> NRF_CLOCK_LF_ACCURACY_50_PPM
+// <6=> NRF_CLOCK_LF_ACCURACY_30_PPM
+// <7=> NRF_CLOCK_LF_ACCURACY_20_PPM
+// <8=> NRF_CLOCK_LF_ACCURACY_10_PPM
+// <9=> NRF_CLOCK_LF_ACCURACY_5_PPM
+// <10=> NRF_CLOCK_LF_ACCURACY_2_PPM
+// <11=> NRF_CLOCK_LF_ACCURACY_1_PPM
 
 #ifndef NRF_SDH_CLOCK_LF_ACCURACY
 #define NRF_SDH_CLOCK_LF_ACCURACY 7
 #endif
 
-//  
+// 
 //==========================================================
 
 //  SDH Observers - Observers and priority levels
 
 //==========================================================
-//  NRF_SDH_REQ_OBSERVER_PRIO_LEVELS - Total number of priority levels for request observers. 
+//  NRF_SDH_REQ_OBSERVER_PRIO_LEVELS - Total number of priority levels for request observers.
 //  This setting configures the number of priority levels available for the SoftDevice request event handlers.
 //  The priority level of a handler determines the order in which it receives events, with respect to other handlers.
 
@@ -11559,7 +11559,7 @@
 #define NRF_SDH_REQ_OBSERVER_PRIO_LEVELS 2
 #endif
 
-//  NRF_SDH_STATE_OBSERVER_PRIO_LEVELS - Total number of priority levels for state observers. 
+//  NRF_SDH_STATE_OBSERVER_PRIO_LEVELS - Total number of priority levels for state observers.
 //  This setting configures the number of priority levels available for the SoftDevice state event handlers.
 //  The priority level of a handler determines the order in which it receives events, with respect to other handlers.
 
@@ -11567,7 +11567,7 @@
 #define NRF_SDH_STATE_OBSERVER_PRIO_LEVELS 2
 #endif
 
-//  NRF_SDH_STACK_OBSERVER_PRIO_LEVELS - Total number of priority levels for stack event observers. 
+//  NRF_SDH_STACK_OBSERVER_PRIO_LEVELS - Total number of priority levels for stack event observers.
 //  This setting configures the number of priority levels available for the SoftDevice stack event handlers (ANT, BLE, SoC).
 //  The priority level of a handler determines the order in which it receives events, with respect to other handlers.
 
@@ -11579,34 +11579,34 @@
 //  State Observers priorities - Invididual priorities
 
 //==========================================================
-//  CLOCK_CONFIG_STATE_OBSERVER_PRIO  
+//  CLOCK_CONFIG_STATE_OBSERVER_PRIO
 //  Priority with which state events are dispatched to the Clock driver.
 
 #ifndef CLOCK_CONFIG_STATE_OBSERVER_PRIO
 #define CLOCK_CONFIG_STATE_OBSERVER_PRIO 0
 #endif
 
-//  POWER_CONFIG_STATE_OBSERVER_PRIO  
+//  POWER_CONFIG_STATE_OBSERVER_PRIO
 //  Priority with which state events are dispatched to the Power driver.
 
 #ifndef POWER_CONFIG_STATE_OBSERVER_PRIO
 #define POWER_CONFIG_STATE_OBSERVER_PRIO 0
 #endif
 
-//  RNG_CONFIG_STATE_OBSERVER_PRIO  
+//  RNG_CONFIG_STATE_OBSERVER_PRIO
 //  Priority with which state events are dispatched to this module.
 
 #ifndef RNG_CONFIG_STATE_OBSERVER_PRIO
 #define RNG_CONFIG_STATE_OBSERVER_PRIO 0
 #endif
 
-//  
+// 
 //==========================================================
 
 //  Stack Event Observers priorities - Invididual priorities
 
 //==========================================================
-//  NRF_SDH_ANT_STACK_OBSERVER_PRIO  
+//  NRF_SDH_ANT_STACK_OBSERVER_PRIO
 //  This setting configures the priority with which ANT events are processed with respect to other events coming from the stack.
 //  Modify this setting if you need to have ANT events dispatched before or after other stack events, such as BLE or SoC.
 //  Zero is the highest priority.
@@ -11615,7 +11615,7 @@
 #define NRF_SDH_ANT_STACK_OBSERVER_PRIO 0
 #endif
 
-//  NRF_SDH_BLE_STACK_OBSERVER_PRIO  
+//  NRF_SDH_BLE_STACK_OBSERVER_PRIO
 //  This setting configures the priority with which BLE events are processed with respect to other events coming from the stack.
 //  Modify this setting if you need to have BLE events dispatched before or after other stack events, such as ANT or SoC.
 //  Zero is the highest priority.
@@ -11624,7 +11624,7 @@
 #define NRF_SDH_BLE_STACK_OBSERVER_PRIO 0
 #endif
 
-//  NRF_SDH_SOC_STACK_OBSERVER_PRIO  
+//  NRF_SDH_SOC_STACK_OBSERVER_PRIO
 //  This setting configures the priority with which SoC events are processed with respect to other events coming from the stack.
 //  Modify this setting if you need to have SoC events dispatched before or after other stack events, such as ANT or BLE.
 //  Zero is the highest priority.
@@ -11633,10 +11633,10 @@
 #define NRF_SDH_SOC_STACK_OBSERVER_PRIO 0
 #endif
 
-//  
+// 
 //==========================================================
 
-//  
+// 
 //==========================================================
 
 
@@ -11650,7 +11650,7 @@
 //  SoC Observers - Observers and priority levels
 
 //==========================================================
-//  NRF_SDH_SOC_OBSERVER_PRIO_LEVELS - Total number of priority levels for SoC observers. 
+//  NRF_SDH_SOC_OBSERVER_PRIO_LEVELS - Total number of priority levels for SoC observers.
 //  This setting configures the number of priority levels available for the SoC event handlers.
 //  The priority level of a handler determines the order in which it receives events, with respect to other handlers.
 
@@ -11661,31 +11661,31 @@
 //  SoC Observers priorities - Invididual priorities
 
 //==========================================================
-//  BLE_DFU_SOC_OBSERVER_PRIO  
+//  BLE_DFU_SOC_OBSERVER_PRIO
 //  Priority with which BLE events are dispatched to the DFU Service.
 
 #ifndef BLE_DFU_SOC_OBSERVER_PRIO
 #define BLE_DFU_SOC_OBSERVER_PRIO 1
 #endif
 
-//  CLOCK_CONFIG_SOC_OBSERVER_PRIO  
+//  CLOCK_CONFIG_SOC_OBSERVER_PRIO
 //  Priority with which SoC events are dispatched to the Clock driver.
 
 #ifndef CLOCK_CONFIG_SOC_OBSERVER_PRIO
 #define CLOCK_CONFIG_SOC_OBSERVER_PRIO 0
 #endif
 
-//  POWER_CONFIG_SOC_OBSERVER_PRIO  
+//  POWER_CONFIG_SOC_OBSERVER_PRIO
 //  Priority with which SoC events are dispatched to the Power driver.
 
 #ifndef POWER_CONFIG_SOC_OBSERVER_PRIO
 #define POWER_CONFIG_SOC_OBSERVER_PRIO 0
 #endif
 
-//  
+// 
 //==========================================================
 
-//  
+// 
 //==========================================================
 
 //  NRFX_NVMC_ENABLED - nrfx_nvmc - NVMC peripheral driver
diff --git a/bsp/nrf5x/nrf52840/rtconfig.py b/bsp/nrf5x/nrf52840/rtconfig.py
index 219d20d303..4ef29e332f 100644
--- a/bsp/nrf5x/nrf52840/rtconfig.py
+++ b/bsp/nrf5x/nrf52840/rtconfig.py
@@ -82,3 +82,11 @@ elif PLATFORM == 'armcc':
         CFLAGS += ' -O2'
 
     POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+
+def dist_handle(BSP_ROOT, dist_dir):
+    import sys
+    cwd_path = os.getcwd()
+    sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+    from sdk_dist import dist_do_building
+    dist_do_building(BSP_ROOT, dist_dir)
diff --git a/bsp/nrf5x/tools/sdk_dist.py b/bsp/nrf5x/tools/sdk_dist.py
new file mode 100644
index 0000000000..d9fe5aa1f8
--- /dev/null
+++ b/bsp/nrf5x/tools/sdk_dist.py
@@ -0,0 +1,17 @@
+import os
+import sys
+import shutil
+cwd_path = os.getcwd()
+sys.path.append(os.path.join(os.path.dirname(cwd_path), 'rt-thread', 'tools'))
+
+# BSP dist function
+def dist_do_building(BSP_ROOT, dist_dir):
+    from mkdist import bsp_copy_files
+    import rtconfig
+
+    library_dir  = os.path.join(dist_dir, 'libraries')
+
+    print("=> copy nrf52 bsp libraries")
+    library_path = os.path.join(os.path.dirname(BSP_ROOT), 'libraries')
+
+    bsp_copy_files(library_path, library_dir)
diff --git a/bsp/nuvoton/README.md b/bsp/nuvoton/README.md
index 1a5b3c578e..9d0c433984 100644
--- a/bsp/nuvoton/README.md
+++ b/bsp/nuvoton/README.md
@@ -1,4 +1,4 @@
-# Nuvoton BSP descriptions
+? Nuvoton BSP descriptions
 Current supported BSP shown in below table:
 
 | **BSP folder** | **Board name** |
@@ -6,3 +6,5 @@ Current supported BSP shown in below table:
 | [numaker-iot-m487](numaker-iot-m487) | Nuvoton NuMaker-IoT-M487 |
 | [numaker-pfm-m487](numaker-pfm-m487) | Nuvoton NuMaker-PFM-M487 |
 | [nk-980iot](nk-980iot) | Nuvoton NK-980IOT |
+| [numaker-m2354](numaker-m2354) | Nuvoton NuMaker-M2354 |
+| [nk-rtu980](nk-rtu980) | Nuvoton NK-RTU980 |
\ No newline at end of file
diff --git a/bsp/nuvoton/libraries/m2354/CMSIS/Include/arm_common_tables.h b/bsp/nuvoton/libraries/m2354/CMSIS/Include/arm_common_tables.h
new file mode 100644
index 0000000000..dfea7460e9
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/CMSIS/Include/arm_common_tables.h
@@ -0,0 +1,121 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_common_tables.h
+ * Description:  Extern declaration for common tables
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
+#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
+#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
+#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
+#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
+#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
+#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
+#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */
diff --git a/bsp/nuvoton/libraries/m2354/CMSIS/Include/arm_const_structs.h b/bsp/nuvoton/libraries/m2354/CMSIS/Include/arm_const_structs.h
new file mode 100644
index 0000000000..80a3e8bbe7
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/CMSIS/Include/arm_const_structs.h
@@ -0,0 +1,66 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_const_structs.h
+ * Description:  Constant structs that are initialized for user convenience.
+ *               For example, some can be given as arguments to the arm_cfft_f32() function.
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
diff --git a/bsp/nuvoton/libraries/m2354/CMSIS/Include/arm_math.h b/bsp/nuvoton/libraries/m2354/CMSIS/Include/arm_math.h
new file mode 100644
index 0000000000..6d75401896
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/CMSIS/Include/arm_math.h
@@ -0,0 +1,7257 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_math.h
+ * Description:  Public header file for CMSIS DSP Library
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * Introduction
+   * ------------
+   *
+   * This user manual describes the CMSIS DSP software library,
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values.
+   *
+   * Using the Library
+   * ------------
+   *
+   * The library installer contains prebuilt versions of the libraries in the Lib folder.
+   * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)
+   * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)
+   * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)
+   * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)
+   * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)
+   * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)
+   * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)
+   * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)
+   * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)
+   * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)
+   * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)
+   * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)
+   * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)
+   * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)
+   * - arm_ARMv8MBLl_math.lib (ARMv8M Baseline, Little endian)
+   * - arm_ARMv8MMLl_math.lib (ARMv8M Mainline, Little endian)
+   * - arm_ARMv8MMLlfsp_math.lib (ARMv8M Mainline, Little endian, Single Precision Floating Point Unit)
+   * - arm_ARMv8MMLld_math.lib (ARMv8M Mainline, Little endian, DSP instructions)
+   * - arm_ARMv8MMLldfsp_math.lib (ARMv8M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
+   *
+   * The library functions are declared in the public file arm_math.h which is placed in the Include folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+   * public header file  arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+   * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or  ARM_MATH_CM3 or
+   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+   * For ARMv8M cores define pre processor MACRO ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
+   * Set Pre processor MACRO __DSP_PRESENT if ARMv8M Mainline core supports DSP instructions.
+   * 
+   *
+   * Examples
+   * --------
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * Toolchain Support
+   * ------------
+   *
+   * The library has been developed and tested with MDK-ARM version 5.14.0.0
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * Building the Library
+   * ------------
+   *
+   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder.
+   * - arm_cortexM_math.uvprojx
+   *
+   *
+   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+   *
+   * Pre-processor Macros
+   * ------------
+   *
+   * Each library project have differant pre-processor macros.
+   *
+   * - UNALIGNED_SUPPORT_DISABLE:
+   *
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_MATH_MATRIX_CHECK:
+   *
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
+   * - ARM_MATH_ROUNDING:
+   *
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+   * ARM_MATH_CM7 for building the library on cortex-M7.
+   *
+   * - ARM_MATH_ARMV8MxL:
+   *
+   * Define macro ARM_MATH_ARMV8MBL for building the library on ARMv8M Baseline target, ARM_MATH_ARMV8MBL for building library
+   * on ARMv8M Mainline target.
+   *
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries.
+   *
+   * - __DSP_PRESENT:
+   *
+   * Initialize macro __DSP_PRESENT = 1 when ARMv8M Mainline core supports DSP instructions.
+   *
+   * 

+   * CMSIS-DSP in ARM::CMSIS Pack
+   * -----------------------------
+   *
+   * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories:
+   * |File/Folder                   |Content                                                                 |
+   * |------------------------------|------------------------------------------------------------------------|
+   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
+   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
+   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
+   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
+   *
+   * 

+   * Revision History of CMSIS-DSP
+   * ------------
+   * Please refer to \ref ChangeLog_pg.
+   *
+   * Copyright Notice
+   * ------------
+   *
+   * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * 

+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size numRows X numCols
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * 
+ *     pData[i*numCols + j]
+ * 

+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function arm_mat_init_f32(), arm_mat_init_q31()
+ * and arm_mat_init_q15() for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ * 

+ * where nRows specifies the number of rows, nColumns
+ * specifies the number of columns, and pData points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices.  For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns.  If the size check fails the functions return:
+ * 
+ *     ARM_MATH_SIZE_MISMATCH
+ * 

+ * Otherwise the functions return
+ * 
+ *     ARM_MATH_SUCCESS
+ * 

+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * 
+ *     ARM_MATH_MATRIX_CHECK
+ * 

+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled.  By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster.  With size checking disabled the functions always
+ * return ARM_MATH_SUCCESS.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+/* Compiler specific diagnostic adjustment */
+#if   defined ( __CC_ARM )
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+#elif defined ( __ICCARM__ )
+
+#elif defined ( __TI_ARM__ )
+
+#elif defined ( __CSMC__ )
+
+#elif defined ( __TASKING__ )
+
+#else
+  #error Unknown compiler
+#endif
+
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+  #include "core_cm7.h"
+  #define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM4)
+  #include "core_cm4.h"
+  #define ARM_MATH_DSP
+#elif defined (ARM_MATH_CM3)
+  #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+  #include "core_cm0.h"
+  #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+  #include "core_cm0plus.h"
+  #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MBL)
+  #include "core_armv8mbl.h"
+  #define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_ARMV8MML)
+  #include "core_armv8mml.h"
+  #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1))
+    #define ARM_MATH_DSP
+  #endif
+#else
+  #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML"
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef   __cplusplus
+extern "C"
+{
+#endif
+
+
+  /**
+   * @brief Macros required for reciprocal calculation in Normalized LMS
+   */
+
+#define DELTA_Q31          (0x100)
+#define DELTA_Q15          0x5
+#define INDEX_MASK         0x0000003F
+#ifndef PI
+  #define PI               3.14159265358979f
+#endif
+
+  /**
+   * @brief Macros required for SINE and COSINE Fast math approximations
+   */
+
+#define FAST_MATH_TABLE_SIZE  512
+#define FAST_MATH_Q31_SHIFT   (32 - 10)
+#define FAST_MATH_Q15_SHIFT   (16 - 10)
+#define CONTROLLER_Q31_SHIFT  (32 - 9)
+#define TABLE_SPACING_Q31     0x400000
+#define TABLE_SPACING_Q15     0x80
+
+  /**
+   * @brief Macros required for SINE and COSINE Controller functions
+   */
+  /* 1.31(q31) Fixed value of 2/360 */
+  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING         0xB60B61
+
+  /**
+   * @brief Macro for Unaligned Support
+   */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+    #define ALIGN4
+#else
+  #if defined  (__GNUC__)
+    #define ALIGN4 __attribute__((aligned(4)))
+  #else
+    #define ALIGN4 __align(4)
+  #endif
+#endif   /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+  /**
+   * @brief Error status returned by some functions in the library.
+   */
+
+  typedef enum
+  {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+  } arm_status;
+
+  /**
+   * @brief 8-bit fractional data type in 1.7 format.
+   */
+  typedef int8_t q7_t;
+
+  /**
+   * @brief 16-bit fractional data type in 1.15 format.
+   */
+  typedef int16_t q15_t;
+
+  /**
+   * @brief 32-bit fractional data type in 1.31 format.
+   */
+  typedef int32_t q31_t;
+
+  /**
+   * @brief 64-bit fractional data type in 1.63 format.
+   */
+  typedef int64_t q63_t;
+
+  /**
+   * @brief 32-bit floating-point type definition.
+   */
+  typedef float float32_t;
+
+  /**
+   * @brief 64-bit floating-point type definition.
+   */
+  typedef double float64_t;
+
+  /**
+   * @brief definition to read/write two 16 bit values.
+   */
+#if   defined ( __CC_ARM )
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED __attribute__((unused))
+  #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED __attribute__((unused))
+  #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __GNUC__ )
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED __attribute__((unused))
+  #define CMSIS_INLINE __attribute__((always_inline))
+
+#elif defined ( __ICCARM__ )
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED
+  #define CMSIS_INLINE
+
+#elif defined ( __TI_ARM__ )
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED __attribute__((unused))
+  #define CMSIS_INLINE
+
+#elif defined ( __CSMC__ )
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED
+  #define CMSIS_INLINE
+
+#elif defined ( __TASKING__ )
+  #define __SIMD32_TYPE __unaligned int32_t
+  #define CMSIS_UNUSED
+  #define CMSIS_INLINE
+
+#else
+  #error Unknown compiler
+#endif
+
+#define __SIMD32(addr)        (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
+#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
+#define __SIMD64(addr)        (*(int64_t **) & (addr))
+
+/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#if !defined (ARM_MATH_DSP)
+  /**
+   * @brief definition to pack two 16 bit values.
+   */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0x0000FFFF) | \
+                                    (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0xFFFF0000) | \
+                                    (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#endif /* !defined (ARM_MATH_DSP) */
+
+   /**
+   * @brief definition to pack four 8 bit values.
+   */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) | \
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) | \
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+  /**
+   * @brief Clips Q63 to Q31 values.
+   */
+  CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
+
+  /**
+   * @brief Clips Q63 to Q15 values.
+   */
+  CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
+
+  /**
+   * @brief Clips Q31 to Q7 values.
+   */
+  CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
+
+  /**
+   * @brief Clips Q31 to Q15 values.
+   */
+  CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
+
+  /**
+   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+   */
+
+  CMSIS_INLINE __STATIC_INLINE q63_t mult32x64(
+  q63_t x,
+  q31_t y)
+  {
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+  }
+
+/*
+  #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
+  #define __CLZ __clz
+  #endif
+ */
+/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__))  )
+  CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ(
+  q31_t data);
+
+  CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ(
+  q31_t data)
+  {
+    uint32_t count = 0;
+    uint32_t mask = 0x80000000;
+
+    while ((data & mask) == 0)
+    {
+      count += 1u;
+      mask = mask >> 1u;
+    }
+
+    return (count);
+  }
+#endif
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+   */
+
+  CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31(
+  q31_t in,
+  q31_t * dst,
+  q31_t * pRecipTable)
+  {
+    q31_t out;
+    uint32_t tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if (in > 0)
+    {
+      signBits = ((uint32_t) (__CLZ( in) - 1));
+    }
+    else
+    {
+      signBits = ((uint32_t) (__CLZ(-in) - 1));
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = (in << signBits);
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t)(in >> 24);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++)
+    {
+      tempVal = (uint32_t) (((q63_t) in * out) >> 31);
+      tempVal = 0x7FFFFFFFu - tempVal;
+      /*      1.31 with exp 1 */
+      /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
+      out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1u);
+  }
+
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15(
+  q15_t in,
+  q15_t * dst,
+  q15_t * pRecipTable)
+  {
+    q15_t out = 0;
+    uint32_t tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if (in > 0)
+    {
+      signBits = ((uint32_t)(__CLZ( in) - 17));
+    }
+    else
+    {
+      signBits = ((uint32_t)(__CLZ(-in) - 17));
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = (in << signBits);
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t)(in >>  8);
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++)
+    {
+      tempVal = (uint32_t) (((q31_t) in * out) >> 15);
+      tempVal = 0x7FFFu - tempVal;
+      /*      1.15 with exp 1 */
+      out = (q15_t) (((q31_t) out * tempVal) >> 14);
+      /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+  }
+
+
+  /*
+   * @brief C custom defined intrinisic function for only M0 processors
+   */
+#if defined(ARM_MATH_CM0_FAMILY)
+  CMSIS_INLINE __STATIC_INLINE q31_t __SSAT(
+  q31_t x,
+  uint32_t y)
+  {
+    int32_t posMax, negMin;
+    uint32_t i;
+
+    posMax = 1;
+    for (i = 0; i < (y - 1); i++)
+    {
+      posMax = posMax * 2;
+    }
+
+    if (x > 0)
+    {
+      posMax = (posMax - 1);
+
+      if (x > posMax)
+      {
+        x = posMax;
+      }
+    }
+    else
+    {
+      negMin = -posMax;
+
+      if (x < negMin)
+      {
+        x = negMin;
+      }
+    }
+    return (x);
+  }
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+  /*
+   * @brief C custom defined intrinsic function for M3 and M0 processors
+   */
+/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#if !defined (ARM_MATH_DSP)
+
+  /*
+   * @brief C custom defined QADD8 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s, t, u;
+
+    r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+    s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+    t = __SSAT(((((q31_t)x <<  8) >> 24) + (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
+    u = __SSAT(((((q31_t)x      ) >> 24) + (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
+
+    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QSUB8 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s, t, u;
+
+    r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+    s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+    t = __SSAT(((((q31_t)x <<  8) >> 24) - (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;
+    u = __SSAT(((((q31_t)x      ) >> 24) - (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;
+
+    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16(
+  uint32_t x,
+  uint32_t y)
+  {
+/*  q31_t r,     s;  without initialisation 'arm_offset_q15 test' fails  but 'intrinsic' tests pass! for armCC */
+    q31_t r = 0, s = 0;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHADD16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QSUB16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHSUB16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QASX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QASX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHASX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined QSAX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;
+    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SHSAX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX(
+  uint32_t x,
+  uint32_t y)
+  {
+    q31_t r, s;
+
+    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+    s = (((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+    return ((uint32_t)((s << 16) | (r      )));
+  }
+
+
+  /*
+   * @brief C custom defined SMUSDX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
+  }
+
+  /*
+   * @brief C custom defined SMUADX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));
+  }
+
+
+  /*
+   * @brief C custom defined QADD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE int32_t __QADD(
+  int32_t x,
+  int32_t y)
+  {
+    return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
+  }
+
+
+  /*
+   * @brief C custom defined QSUB for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE int32_t __QSUB(
+  int32_t x,
+  int32_t y)
+  {
+    return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
+  }
+
+
+  /*
+   * @brief C custom defined SMLAD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD(
+  uint32_t x,
+  uint32_t y,
+  uint32_t sum)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ( ((q31_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLADX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX(
+  uint32_t x,
+  uint32_t y,
+  uint32_t sum)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ( ((q31_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLSDX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX(
+  uint32_t x,
+  uint32_t y,
+  uint32_t sum)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ( ((q31_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLALD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD(
+  uint32_t x,
+  uint32_t y,
+  uint64_t sum)
+  {
+/*  return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
+    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ( ((q63_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMLALDX for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX(
+  uint32_t x,
+  uint32_t y,
+  uint64_t sum)
+  {
+/*  return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
+    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ( ((q63_t)sum    )                                  )   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMUAD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
+  }
+
+
+  /*
+   * @brief C custom defined SMUSD for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD(
+  uint32_t x,
+  uint32_t y)
+  {
+    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
+                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));
+  }
+
+
+  /*
+   * @brief C custom defined SXTB16 for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16(
+  uint32_t x)
+  {
+    return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
+                       ((((q31_t)x <<  8) >>  8) & (q31_t)0xFFFF0000)  ));
+  }
+
+  /*
+   * @brief C custom defined SMMLA for M3 and M0 processors
+   */
+  CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA(
+  int32_t x,
+  int32_t y,
+  int32_t sum)
+  {
+    return (sum + (int32_t) (((int64_t) x * y) >> 32));
+  }
+
+#if 0
+  /*
+   * @brief C custom defined PKHBT for unavailable DSP extension
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __PKHBT(
+  uint32_t x,
+  uint32_t y,
+  uint32_t leftshift)
+  {
+    return ( ((x             ) & 0x0000FFFFUL) |
+             ((y << leftshift) & 0xFFFF0000UL)  );
+  }
+
+  /*
+   * @brief C custom defined PKHTB for unavailable DSP extension
+   */
+  CMSIS_INLINE __STATIC_INLINE uint32_t __PKHTB(
+  uint32_t x,
+  uint32_t y,
+  uint32_t rightshift)
+  {
+    return ( ((x              ) & 0xFFFF0000UL) |
+             ((y >> rightshift) & 0x0000FFFFUL)  );
+  }
+#endif
+
+/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+#endif /* !defined (ARM_MATH_DSP) */
+
+
+  /**
+   * @brief Instance structure for the Q7 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q7;
+
+  /**
+   * @brief Instance structure for the Q15 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q7 FIR filter.
+   * @param[in]  S          points to an instance of the Q7 FIR filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 FIR filter.
+   * @param[in,out] S          points to an instance of the Q7 FIR structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed.
+   */
+  void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR filter.
+   * @param[in]  S          points to an instance of the Q15 FIR structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q15 FIR filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR filter.
+   * @param[in,out] S          points to an instance of the Q15 FIR filter structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed at a time.
+   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+   * numTaps is not a supported value.
+   */
+  arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR filter.
+   * @param[in]  S          points to an instance of the Q31 FIR filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q31 FIR structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR filter.
+   * @param[in,out] S          points to an instance of the Q31 FIR structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed at a time.
+   */
+  void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR filter.
+   * @param[in]  S          points to an instance of the floating-point FIR structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR filter.
+   * @param[in,out] S          points to an instance of the floating-point FIR filter structure.
+   * @param[in]     numTaps    Number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of samples that are processed at a time.
+   */
+  void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    int8_t numStages;        /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;        /**< Additional shift, in bits, applied to each output sample. */
+  } arm_biquad_casd_df1_inst_q15;
+
+  /**
+   * @brief Instance structure for the Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+  } arm_biquad_casd_df1_inst_q31;
+
+  /**
+   * @brief Instance structure for the floating-point Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;       /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;      /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_casd_df1_inst_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 Biquad cascade filter.
+   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
+   */
+  void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 Biquad cascade filter
+   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format
+   */
+  void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Processing function for the floating-point Biquad cascade filter.
+   * @param[in]  S          points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f32;
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float64_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f64;
+
+  /**
+   * @brief Instance structure for the Q15 matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t *pData;         /**< points to the data of the matrix. */
+  } arm_matrix_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 matrix structure.
+   */
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t *pData;         /**< points to the data of the matrix. */
+  } arm_matrix_instance_q31;
+
+
+  /**
+   * @brief Floating-point matrix addition.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+  arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix addition.
+   * @param[in]   pSrcA  points to the first input matrix structure
+   * @param[in]   pSrcB  points to the second input matrix structure
+   * @param[out]  pDst   points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+  arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix addition.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+  arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point, complex, matrix multiplication.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+  arm_status arm_mat_cmplx_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15, complex,  matrix multiplication.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+  arm_status arm_mat_cmplx_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Q31, complex, matrix multiplication.
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+  arm_status arm_mat_cmplx_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix transpose.
+   * @param[in]  pSrc  points to the input matrix
+   * @param[out] pDst  points to the output matrix
+   * @return    The function returns either  ARM_MATH_SIZE_MISMATCH
+   * or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+  arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix transpose.
+   * @param[in]  pSrc  points to the input matrix
+   * @param[out] pDst  points to the output matrix
+   * @return    The function returns either  ARM_MATH_SIZE_MISMATCH
+   * or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+  arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix transpose.
+   * @param[in]  pSrc  points to the input matrix
+   * @param[out] pDst  points to the output matrix
+   * @return    The function returns either  ARM_MATH_SIZE_MISMATCH
+   * or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+  arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix multiplication
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix multiplication
+   * @param[in]  pSrcA   points to the first input matrix structure
+   * @param[in]  pSrcB   points to the second input matrix structure
+   * @param[out] pDst    points to output matrix structure
+   * @param[in]  pState  points to the array for storing intermediate results
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+
+  /**
+   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA   points to the first input matrix structure
+   * @param[in]  pSrcB   points to the second input matrix structure
+   * @param[out] pDst    points to output matrix structure
+   * @param[in]  pState  points to the array for storing intermediate results
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+
+  /**
+   * @brief Q31 matrix multiplication
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+  arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix subtraction
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+  arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix subtraction
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+  arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix subtraction
+   * @param[in]  pSrcA  points to the first input matrix structure
+   * @param[in]  pSrcB  points to the second input matrix structure
+   * @param[out] pDst   points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+  arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix scaling.
+   * @param[in]  pSrc   points to the input matrix
+   * @param[in]  scale  scale factor
+   * @param[out] pDst   points to the output matrix
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+  arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix scaling.
+   * @param[in]  pSrc        points to input matrix
+   * @param[in]  scaleFract  fractional portion of the scale factor
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to output matrix
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+  arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst);
+
+
+  /**
+   * @brief Q31 matrix scaling.
+   * @param[in]  pSrc        points to input matrix
+   * @param[in]  scaleFract  fractional portion of the scale factor
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+  arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] S         points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows     number of rows in the matrix.
+   * @param[in]     nColumns  number of columns in the matrix.
+   * @param[in]     pData     points to the matrix data array.
+   */
+  void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData);
+
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] S         points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows     number of rows in the matrix.
+   * @param[in]     nColumns  number of columns in the matrix.
+   * @param[in]     pData     points to the matrix data array.
+   */
+  void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData);
+
+
+  /**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] S         points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows     number of rows in the matrix.
+   * @param[in]     nColumns  number of columns in the matrix.
+   * @param[in]     pData     points to the matrix data array.
+   */
+  void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 PID Control.
+   */
+  typedef struct
+  {
+    q15_t A0;           /**< The derived gain, A0 = Kp + Ki + Kd . */
+#if !defined (ARM_MATH_DSP)
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];     /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+  } arm_pid_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 PID Control.
+   */
+  typedef struct
+  {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+  } arm_pid_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point PID Control.
+   */
+  typedef struct
+  {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;          /**< The proportional gain. */
+    float32_t Ki;          /**< The integral gain. */
+    float32_t Kd;          /**< The derivative gain. */
+  } arm_pid_instance_f32;
+
+
+
+  /**
+   * @brief  Initialization function for the floating-point PID Control.
+   * @param[in,out] S               points to an instance of the PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   */
+  void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the floating-point PID Control.
+   * @param[in,out] S  is an instance of the floating-point PID Control structure
+   */
+  void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q31 PID Control.
+   * @param[in,out] S               points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   */
+  void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q31 PID Control.
+   * @param[in,out] S   points to an instance of the Q31 PID Control structure
+   */
+
+  void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q15 PID Control.
+   * @param[in,out] S               points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   */
+  void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q15 PID Control.
+   * @param[in,out] S  points to an instance of the q15 PID Control structure
+   */
+  void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S);
+
+
+  /**
+   * @brief Instance structure for the floating-point Linear Interpolate function.
+   */
+  typedef struct
+  {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t *pYData;          /**< pointer to the table of Y values */
+  } arm_linear_interp_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t *pData;   /**< points to the data table. */
+  } arm_bilinear_interp_instance_f32;
+
+   /**
+   * @brief Instance structure for the Q31 bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q31;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q15;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t *pData;        /**< points to the data table. */
+  } arm_bilinear_interp_instance_q7;
+
+
+  /**
+   * @brief Q7 vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Floating-point vector multiplication.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_mult_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the Sin twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q15(
+  arm_cfft_radix2_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q15(
+  const arm_cfft_radix2_instance_q15 * S,
+  q15_t * pSrc);
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q31(
+  arm_cfft_radix2_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q31(
+  const arm_cfft_radix2_instance_q31 * S,
+  q31_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Q31 CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+  void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc);
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;             /**< value of 1/fftLen. */
+  } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_f32(
+  arm_cfft_radix2_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_f32(
+  const arm_cfft_radix2_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;             /**< value of 1/fftLen. */
+  } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q15;
+
+void arm_cfft_q15(
+    const arm_cfft_instance_q15 * S,
+    q15_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q31;
+
+void arm_cfft_q31(
+    const arm_cfft_instance_q31 * S,
+    q31_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_f32;
+
+  void arm_cfft_f32(
+  const arm_cfft_instance_f32 * S,
+  float32_t * p1,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the Q15 RFFT/RIFFT function.
+   */
+  typedef struct
+  {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q15;
+
+  arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst);
+
+  /**
+   * @brief Instance structure for the Q31 RFFT/RIFFT function.
+   */
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q31;
+
+  arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_f32;
+
+  arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+typedef struct
+  {
+    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
+    uint16_t fftLenRFFT;             /**< length of the real sequence */
+    float32_t * pTwiddleRFFT;        /**< Twiddle factors real stage  */
+  } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+   arm_rfft_fast_instance_f32 * S,
+   uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+  arm_rfft_fast_instance_f32 * S,
+  float32_t * p, float32_t * pOut,
+  uint8_t ifftFlag);
+
+  /**
+   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+   */
+  typedef struct
+  {
+    uint16_t N;                          /**< length of the DCT4. */
+    uint16_t Nby2;                       /**< half of the length of the DCT4. */
+    float32_t normalize;                 /**< normalizing factor. */
+    float32_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    float32_t *pCosFactor;               /**< points to the cosFactor table. */
+    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_f32;
+
+
+  /**
+   * @brief  Initialization function for the floating-point DCT4/IDCT4.
+   * @param[in,out] S          points to an instance of floating-point DCT4/IDCT4 structure.
+   * @param[in]     S_RFFT     points to an instance of floating-point RFFT/RIFFT structure.
+   * @param[in]     S_CFFT     points to an instance of floating-point CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.
+   */
+  arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize);
+
+
+  /**
+   * @brief Processing function for the floating-point DCT4/IDCT4.
+   * @param[in]     S              points to an instance of the floating-point DCT4/IDCT4 structure.
+   * @param[in]     pState         points to state buffer.
+   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
+   */
+  void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer);
+
+
+  /**
+   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+   */
+  typedef struct
+  {
+    uint16_t N;                          /**< length of the DCT4. */
+    uint16_t Nby2;                       /**< half of the length of the DCT4. */
+    q31_t normalize;                     /**< normalizing factor. */
+    q31_t *pTwiddle;                     /**< points to the twiddle factor table. */
+    q31_t *pCosFactor;                   /**< points to the cosFactor table. */
+    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q31;
+
+
+  /**
+   * @brief  Initialization function for the Q31 DCT4/IDCT4.
+   * @param[in,out] S          points to an instance of Q31 DCT4/IDCT4 structure.
+   * @param[in]     S_RFFT     points to an instance of Q31 RFFT/RIFFT structure
+   * @param[in]     S_CFFT     points to an instance of Q31 CFFT/CIFFT structure
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+   */
+  arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize);
+
+
+  /**
+   * @brief Processing function for the Q31 DCT4/IDCT4.
+   * @param[in]     S              points to an instance of the Q31 DCT4 structure.
+   * @param[in]     pState         points to state buffer.
+   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
+   */
+  void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer);
+
+
+  /**
+   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+   */
+  typedef struct
+  {
+    uint16_t N;                          /**< length of the DCT4. */
+    uint16_t Nby2;                       /**< half of the length of the DCT4. */
+    q15_t normalize;                     /**< normalizing factor. */
+    q15_t *pTwiddle;                     /**< points to the twiddle factor table. */
+    q15_t *pCosFactor;                   /**< points to the cosFactor table. */
+    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q15;
+
+
+  /**
+   * @brief  Initialization function for the Q15 DCT4/IDCT4.
+   * @param[in,out] S          points to an instance of Q15 DCT4/IDCT4 structure.
+   * @param[in]     S_RFFT     points to an instance of Q15 RFFT/RIFFT structure.
+   * @param[in]     S_CFFT     points to an instance of Q15 CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+   */
+  arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize);
+
+
+  /**
+   * @brief Processing function for the Q15 DCT4/IDCT4.
+   * @param[in]     S              points to an instance of the Q15 DCT4 structure.
+   * @param[in]     pState         points to state buffer.
+   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.
+   */
+  void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer);
+
+
+  /**
+   * @brief Floating-point vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q7 vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector addition.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_add_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Floating-point vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q7 vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector subtraction.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_sub_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a floating-point vector by a scalar.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  scale      scale factor to be applied
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_scale_f32(
+  float32_t * pSrc,
+  float32_t scale,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a Q7 vector by a scalar.
+   * @param[in]  pSrc        points to the input vector
+   * @param[in]  scaleFract  fractional portion of the scale value
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to the output vector
+   * @param[in]  blockSize   number of samples in the vector
+   */
+  void arm_scale_q7(
+  q7_t * pSrc,
+  q7_t scaleFract,
+  int8_t shift,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a Q15 vector by a scalar.
+   * @param[in]  pSrc        points to the input vector
+   * @param[in]  scaleFract  fractional portion of the scale value
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to the output vector
+   * @param[in]  blockSize   number of samples in the vector
+   */
+  void arm_scale_q15(
+  q15_t * pSrc,
+  q15_t scaleFract,
+  int8_t shift,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Multiplies a Q31 vector by a scalar.
+   * @param[in]  pSrc        points to the input vector
+   * @param[in]  scaleFract  fractional portion of the scale value
+   * @param[in]  shift       number of bits to shift the result by
+   * @param[out] pDst        points to the output vector
+   * @param[in]  blockSize   number of samples in the vector
+   */
+  void arm_scale_q31(
+  q31_t * pSrc,
+  q31_t scaleFract,
+  int8_t shift,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q7 vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Floating-point vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q15 vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Q31 vector absolute value.
+   * @param[in]  pSrc       points to the input buffer
+   * @param[out] pDst       points to the output buffer
+   * @param[in]  blockSize  number of samples in each vector
+   */
+  void arm_abs_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Dot product of floating-point vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t blockSize,
+  float32_t * result);
+
+
+  /**
+   * @brief Dot product of Q7 vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  uint32_t blockSize,
+  q31_t * result);
+
+
+  /**
+   * @brief Dot product of Q15 vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+
+  /**
+   * @brief Dot product of Q31 vectors.
+   * @param[in]  pSrcA      points to the first input vector
+   * @param[in]  pSrcB      points to the second input vector
+   * @param[in]  blockSize  number of samples in each vector
+   * @param[out] result     output result returned here
+   */
+  void arm_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+
+  /**
+   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_shift_q7(
+  q7_t * pSrc,
+  int8_t shiftBits,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_shift_q15(
+  q15_t * pSrc,
+  int8_t shiftBits,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_shift_q31(
+  q31_t * pSrc,
+  int8_t shiftBits,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a floating-point vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_f32(
+  float32_t * pSrc,
+  float32_t offset,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a Q7 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_q7(
+  q7_t * pSrc,
+  q7_t offset,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a Q15 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_q15(
+  q15_t * pSrc,
+  q15_t offset,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Adds a constant offset to a Q31 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[in]  offset     is the offset to be added
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_offset_q31(
+  q31_t * pSrc,
+  q31_t offset,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a floating-point vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a Q7 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a Q15 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Negates the elements of a Q31 vector.
+   * @param[in]  pSrc       points to the input vector
+   * @param[out] pDst       points to the output vector
+   * @param[in]  blockSize  number of samples in the vector
+   */
+  void arm_negate_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a floating-point vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a Q7 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a Q15 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Copies the elements of a Q31 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a floating-point vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a Q7 vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a Q15 vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Fills a constant value into a Q31 vector.
+   * @param[in]  value      input value to be filled
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ */
+  void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences.
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
+   */
+  void arm_conv_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in]  pSrcA    points to the first input sequence.
+ * @param[in]  srcALen  length of the first input sequence.
+ * @param[in]  pSrcB    points to the second input sequence.
+ * @param[in]  srcBLen  length of the second input sequence.
+ * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ */
+  void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_fast_q15(
+          q15_t * pSrcA,
+          uint32_t srcALen,
+          q15_t * pSrcB,
+          uint32_t srcBLen,
+          q15_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).
+   */
+  void arm_conv_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Convolution of Q31 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+    /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   */
+  void arm_conv_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.
+   */
+  void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Partial convolution of floating-point sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q7 sequences
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @param[in]  pScratch1   points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2   points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]  pSrcA       points to the first input sequence.
+   * @param[in]  srcALen     length of the first input sequence.
+   * @param[in]  pSrcB       points to the second input sequence.
+   * @param[in]  srcBLen     length of the second input sequence.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  firstIndex  is the first output sample to start with.
+   * @param[in]  numPoints   is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+  arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR decimator.
+   */
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q15_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR decimator.
+   */
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR decimator.
+   */
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    float32_t *pCoeffs;         /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t *pState;          /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in]  S          points to an instance of the floating-point FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR decimator.
+   * @param[in,out] S          points to an instance of the floating-point FIR decimator structure.
+   * @param[in]     numTaps    number of coefficients in the filter.
+   * @param[in]     M          decimation factor.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * blockSize is not a multiple of M.
+   */
+  arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator.
+   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR decimator.
+   * @param[in,out] S          points to an instance of the Q15 FIR decimator structure.
+   * @param[in]     numTaps    number of coefficients in the filter.
+   * @param[in]     M          decimation factor.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * blockSize is not a multiple of M.
+   */
+  arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator.
+   * @param[in]  S     points to an instance of the Q31 FIR decimator structure.
+   * @param[in]  pSrc  points to the block of input data.
+   * @param[out] pDst  points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   */
+  void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in]  S          points to an instance of the Q31 FIR decimator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR decimator.
+   * @param[in,out] S          points to an instance of the Q31 FIR decimator structure.
+   * @param[in]     numTaps    number of coefficients in the filter.
+   * @param[in]     M          decimation factor.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * blockSize is not a multiple of M.
+   */
+  arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR interpolator.
+   */
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR interpolator.
+   */
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR interpolator.
+   */
+  typedef struct
+  {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t *pCoeffs;            /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t *pState;             /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+  } arm_fir_interpolate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 FIR interpolator.
+   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR interpolator.
+   * @param[in,out] S          points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]     L          upsample factor.
+   * @param[in]     numTaps    number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficient buffer.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length numTaps is not a multiple of the interpolation factor L.
+   */
+  arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR interpolator.
+   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR interpolator.
+   * @param[in,out] S          points to an instance of the Q31 FIR interpolator structure.
+   * @param[in]     L          upsample factor.
+   * @param[in]     numTaps    number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficient buffer.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length numTaps is not a multiple of the interpolation factor L.
+   */
+  arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR interpolator.
+   * @param[in]  S          points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of input samples to process per call.
+   */
+  void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR interpolator.
+   * @param[in,out] S          points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]     L          upsample factor.
+   * @param[in]     numTaps    number of filter coefficients in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficient buffer.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     blockSize  number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length numTaps is not a multiple of the interpolation factor L.
+   */
+  arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+  } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+  /**
+   * @param[in]  S          points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @param[in,out] S          points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     postShift  shift to be applied to the output. Varies according to the coefficients format
+   */
+  void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift);
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f64;
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  S          points to an instance of the filter data structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+   * @param[in]  S          points to an instance of the filter data structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_stereo_df2T_f32(
+  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  S          points to an instance of the filter data structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_biquad_cascade_df2T_f64(
+  const arm_biquad_cascade_df2T_instance_f64 * S,
+  float64_t * pSrc,
+  float64_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the filter data structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the filter data structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_stereo_df2T_init_f32(
+  arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] S          points to an instance of the filter data structure.
+   * @param[in]     numStages  number of 2nd order stages in the filter.
+   * @param[in]     pCoeffs    points to the filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   */
+  void arm_biquad_cascade_df2T_init_f64(
+  arm_biquad_cascade_df2T_instance_f64 * S,
+  uint8_t numStages,
+  float64_t * pCoeffs,
+  float64_t * pState);
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages. */
+    q15_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages. */
+    q31_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_f32;
+
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] S          points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] pState     points to the state buffer.  The array is of length numStages.
+   */
+  void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR lattice filter.
+   * @param[in]  S          points to an instance of the Q15 FIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] S          points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] pState     points to the state buffer.   The array is of length numStages.
+   */
+  void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR lattice filter.
+   * @param[in]  S          points to an instance of the Q31 FIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] S          points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] pState     points to the state buffer.  The array is of length numStages.
+ */
+  void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  S          points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of stages in the filter. */
+    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of stages in the filter. */
+    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of stages in the filter. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t *pkCoeffs;                 /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t *pvCoeffs;                 /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_f32;
+
+
+  /**
+   * @brief Processing function for the floating-point IIR lattice filter.
+   * @param[in]  S          points to an instance of the floating-point IIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the floating-point IIR lattice filter.
+   * @param[in] S          points to an instance of the floating-point IIR lattice structure.
+   * @param[in] numStages  number of stages in the filter.
+   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize-1.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 IIR lattice filter.
+   * @param[in]  S          points to an instance of the Q31 IIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] S          points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages  number of stages in the filter.
+   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 IIR lattice filter.
+   * @param[in]  S          points to an instance of the Q15 IIR lattice structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[out] pDst       points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] S          points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] pkCoeffs   points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] pvCoeffs   points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] pState     points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize  number of samples to process per call.
+ */
+  void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the floating-point LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+  } arm_lms_instance_f32;
+
+
+  /**
+   * @brief Processing function for floating-point LMS filter.
+   * @param[in]  S          points to an instance of the floating-point LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] S          points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to the coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q15;
+
+
+  /**
+   * @brief Initialization function for the Q15 LMS filter.
+   * @param[in] S          points to an instance of the Q15 LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to the coefficient buffer.
+   * @param[in] pState     points to the state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+
+  /**
+   * @brief Processing function for Q15 LMS filter.
+   * @param[in]  S          points to an instance of the Q15 LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q31;
+
+
+  /**
+   * @brief Processing function for Q31 LMS filter.
+   * @param[in]  S          points to an instance of the Q15 LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] S          points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+
+  /**
+   * @brief Instance structure for the floating-point normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;         /**< step size that control filter coefficient updates. */
+    float32_t energy;     /**< saves previous frame energy. */
+    float32_t x0;         /**< saves previous input sample. */
+  } arm_lms_norm_instance_f32;
+
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in]  S          points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] S          points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   */
+  void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q31;
+
+
+  /**
+   * @brief Processing function for Q31 normalized LMS filter.
+   * @param[in]  S          points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] S          points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+
+  /**
+   * @brief Instance structure for the Q15 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< Number of coefficients in the filter. */
+    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q15_t *recipTable;    /**< Points to the reciprocal initial value table. */
+    q15_t energy;         /**< saves previous frame energy. */
+    q15_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q15;
+
+
+  /**
+   * @brief Processing function for Q15 normalized LMS filter.
+   * @param[in]  S          points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in]  pSrc       points to the block of input data.
+   * @param[in]  pRef       points to the block of reference data.
+   * @param[out] pOut       points to the block of output data.
+   * @param[out] pErr       points to the block of error data.
+   * @param[in]  blockSize  number of samples to process.
+   */
+  void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] S          points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps    number of filter coefficients.
+   * @param[in] pCoeffs    points to coefficient buffer.
+   * @param[in] pState     points to state buffer.
+   * @param[in] mu         step size that controls filter coefficient updates.
+   * @param[in] blockSize  number of samples to process.
+   * @param[in] postShift  bit shift applied to coefficients.
+   */
+  void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+
+  /**
+   * @brief Correlation of floating-point sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+   /**
+   * @brief Correlation of Q15 sequences
+   * @param[in]  pSrcA     points to the first input sequence.
+   * @param[in]  srcALen   length of the first input sequence.
+   * @param[in]  pSrcB     points to the second input sequence.
+   * @param[in]  srcBLen   length of the second input sequence.
+   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   */
+  void arm_correlate_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q15 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+
+  void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+
+  void arm_correlate_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in]  pSrcA     points to the first input sequence.
+   * @param[in]  srcALen   length of the first input sequence.
+   * @param[in]  pSrcB     points to the second input sequence.
+   * @param[in]  srcBLen   length of the second input sequence.
+   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   */
+  void arm_correlate_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q31 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+  /**
+   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+ /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in]  pSrcA      points to the first input sequence.
+   * @param[in]  srcALen    length of the first input sequence.
+   * @param[in]  pSrcB      points to the second input sequence.
+   * @param[in]  srcBLen    length of the second input sequence.
+   * @param[out] pDst       points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   */
+  void arm_correlate_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in]  pSrcA    points to the first input sequence.
+   * @param[in]  srcALen  length of the first input sequence.
+   * @param[in]  pSrcB    points to the second input sequence.
+   * @param[in]  srcBLen  length of the second input sequence.
+   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   */
+  void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Instance structure for the floating-point sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q31 sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q31;
+
+  /**
+   * @brief Instance structure for the Q15 sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q7 sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q7;
+
+
+  /**
+   * @brief Processing function for the floating-point sparse FIR filter.
+   * @param[in]  S           points to an instance of the floating-point sparse FIR structure.
+   * @param[in]  pSrc        points to the block of input data.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   */
+  void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point sparse FIR filter.
+   * @param[in,out] S          points to an instance of the floating-point sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 sparse FIR filter.
+   * @param[in]  S           points to an instance of the Q31 sparse FIR structure.
+   * @param[in]  pSrc        points to the block of input data.
+   * @param[out] pDst        points to the block of output data
+   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   */
+  void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 sparse FIR filter.
+   * @param[in,out] S          points to an instance of the Q31 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 sparse FIR filter.
+   * @param[in]  S            points to an instance of the Q15 sparse FIR structure.
+   * @param[in]  pSrc         points to the block of input data.
+   * @param[out] pDst         points to the block of output data
+   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
+   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   */
+  void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 sparse FIR filter.
+   * @param[in,out] S          points to an instance of the Q15 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q7 sparse FIR filter.
+   * @param[in]  S            points to an instance of the Q7 sparse FIR structure.
+   * @param[in]  pSrc         points to the block of input data.
+   * @param[out] pDst         points to the block of output data
+   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.
+   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   */
+  void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 sparse FIR filter.
+   * @param[in,out] S          points to an instance of the Q7 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     pCoeffs    points to the array of filter coefficients.
+   * @param[in]     pState     points to the state buffer.
+   * @param[in]     pTapDelay  points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   */
+  void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Floating-point sin_cos function.
+   * @param[in]  theta   input value in degrees
+   * @param[out] pSinVal  points to the processed sine output.
+   * @param[out] pCosVal  points to the processed cos output.
+   */
+  void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCosVal);
+
+
+  /**
+   * @brief  Q31 sin_cos function.
+   * @param[in]  theta    scaled input value in degrees
+   * @param[out] pSinVal  points to the processed sine output.
+   * @param[out] pCosVal  points to the processed cosine output.
+   */
+  void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal);
+
+
+  /**
+   * @brief  Floating-point complex conjugate.
+   * @param[in]  pSrc        points to the input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex conjugate.
+   * @param[in]  pSrc        points to the input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex conjugate.
+   * @param[in]  pSrc        points to the input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Floating-point complex magnitude squared
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex magnitude squared
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex magnitude squared
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+ /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup PID PID Motor Control
+   *
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control
+   * loop mechanism widely used in industrial control systems.
+   * A PID controller is the most commonly used type of feedback controller.
+   *
+   * This set of functions implements (PID) controllers
+   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+   * of data and each call to the function returns a single processed value.
+   * S points to an instance of the PID control data structure.  in
+   * is the input sample value. The functions return the output value.
+   *
+   * \par Algorithm:
+   * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  

+   *
+   * \par
+   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   *
+   * \par
+   * \image html PID.gif "Proportional Integral Derivative Controller"
+   *
+   * \par
+   * The PID controller calculates an "error" value as the difference between
+   * the measured output and the reference input.
+   * The controller attempts to minimize the error by adjusting the process control inputs.
+   * The proportional value determines the reaction to the current error,
+   * the integral value determines the reaction based on the sum of recent errors,
+   * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
+   * \par Instance Structure
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+   * A separate instance structure must be defined for each PID Controller.
+   * There are separate instance structure declarations for each of the 3 supported data types.
+   *
+   * \par Reset Functions
+   * There is also an associated reset function for each data type which clears the state array.
+   *
+   * \par Initialization Functions
+   * There is also an associated initialization function for each data type.
+   * The initialization function performs the following operations:
+   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+   * - Zeros out the values in the state buffer.
+   *
+   * \par
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+   *
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the fixed-point versions of the PID Controller functions.
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup PID
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point PID Control.
+   * @param[in,out] S   is an instance of the floating-point PID Control structure
+   * @param[in]     in  input sample to process
+   * @return out processed output sample.
+   */
+  CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32(
+  arm_pid_instance_f32 * S,
+  float32_t in)
+  {
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q31 PID Control.
+   * @param[in,out] S  points to an instance of the Q31 PID Control structure
+   * @param[in]     in  input sample to process
+   * @return out processed output sample.
+   *
+   * Scaling and Overflow Behavior:
+   * \par
+   * The function is implemented using an internal 64-bit accumulator.
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+   * Thus, if the accumulator result overflows it wraps around rather than clip.
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+   */
+  CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31(
+  arm_pid_instance_q31 * S,
+  q31_t in)
+  {
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31u);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+  }
+
+
+  /**
+   * @brief  Process function for the Q15 PID Control.
+   * @param[in,out] S   points to an instance of the Q15 PID Control structure
+   * @param[in]     in  input sample to process
+   * @return out processed output sample.
+   *
+   * Scaling and Overflow Behavior:
+   * \par
+   * The function is implemented using a 64-bit internal accumulator.
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+   */
+  CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15(
+  arm_pid_instance_q15 * S,
+  q15_t in)
+  {
+    q63_t acc;
+    q15_t out;
+
+#if defined (ARM_MATH_DSP)
+    __SIMD32_TYPE *vstate;
+
+    /* Implementation of PID controller */
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    vstate = __SIMD32_CONST(S->state);
+    acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);
+#else
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+  }
+
+  /**
+   * @} end of PID group
+   */
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  src   points to the instance of the input floating-point matrix structure.
+   * @param[out] dst   points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+  arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * src,
+  arm_matrix_instance_f32 * dst);
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  src   points to the instance of the input floating-point matrix structure.
+   * @param[out] dst   points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+  arm_status arm_mat_inverse_f64(
+  const arm_matrix_instance_f64 * src,
+  arm_matrix_instance_f64 * dst);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup clarke Vector Clarke Transform
+   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+   * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents
+   * in the two-phase orthogonal stator axis Ialpha and Ibeta.
+   * When Ialpha is superposed with Ia as shown in the figure below
+   * \image html clarke.gif Stator current space vector and its components in (a,b).
+   * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta
+   * can be calculated using only Ia and Ib.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeFormula.gif
+   * where Ia and Ib are the instantaneous stator phases and
+   * pIalpha and pIbeta are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup clarke
+   * @{
+   */
+
+  /**
+   *
+   * @brief  Floating-point Clarke transform
+   * @param[in]  Ia       input three-phase coordinate a
+   * @param[in]  Ib       input three-phase coordinate b
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32(
+  float32_t Ia,
+  float32_t Ib,
+  float32_t * pIalpha,
+  float32_t * pIbeta)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+  }
+
+
+  /**
+   * @brief  Clarke transform for Q31 version
+   * @param[in]  Ia       input three-phase coordinate a
+   * @param[in]  Ib       input three-phase coordinate b
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   *
+   * Scaling and Overflow Behavior:
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31(
+  q31_t Ia,
+  q31_t Ib,
+  q31_t * pIalpha,
+  q31_t * pIbeta)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+  }
+
+  /**
+   * @} end of clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q31 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_clarke Vector Inverse Clarke Transform
+   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeInvFormula.gif
+   * where pIa and pIb are the instantaneous stator phases and
+   * Ialpha and Ibeta are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_clarke
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Clarke transform
+   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out] pIa     points to output three-phase coordinate a
+   * @param[out] pIb     points to output three-phase coordinate b
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pIa,
+  float32_t * pIb)
+  {
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
+  }
+
+
+  /**
+   * @brief  Inverse Clarke transform for Q31 version
+   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out] pIa     points to output three-phase coordinate a
+   * @param[out] pIb     points to output three-phase coordinate b
+   *
+   * Scaling and Overflow Behavior:
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the subtraction, hence there is no risk of overflow.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pIa,
+  q31_t * pIb)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+  }
+
+  /**
+   * @} end of inv_clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q15 vector.
+   * @param[in]  pSrc       input pointer
+   * @param[out] pDst       output pointer
+   * @param[in]  blockSize  number of samples to process
+   */
+  void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup park Vector Park Transform
+   *
+   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+   * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents
+   * from the stationary to the moving reference frame and control the spatial relationship between
+   * the stator vector current and rotor flux vector.
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+   * current vector and the relationship from the two reference frames:
+   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkFormula.gif
+   * where Ialpha and Ibeta are the stator vector components,
+   * pId and pIq are rotor vector components and cosVal and sinVal are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup park
+   * @{
+   */
+
+  /**
+   * @brief Floating-point Park transform
+   * @param[in]  Ialpha  input two-phase vector coordinate alpha
+   * @param[in]  Ibeta   input two-phase vector coordinate beta
+   * @param[out] pId     points to output   rotor reference frame d
+   * @param[out] pIq     points to output   rotor reference frame q
+   * @param[in]  sinVal  sine value of rotation angle theta
+   * @param[in]  cosVal  cosine value of rotation angle theta
+   *
+   * The function implements the forward Park transform.
+   *
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_park_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pId,
+  float32_t * pIq,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+  }
+
+
+  /**
+   * @brief  Park transform for Q31 version
+   * @param[in]  Ialpha  input two-phase vector coordinate alpha
+   * @param[in]  Ibeta   input two-phase vector coordinate beta
+   * @param[out] pId     points to output rotor reference frame d
+   * @param[out] pIq     points to output rotor reference frame q
+   * @param[in]  sinVal  sine value of rotation angle theta
+   * @param[in]  cosVal  cosine value of rotation angle theta
+   *
+   * Scaling and Overflow Behavior:
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_park_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pId,
+  q31_t * pIq,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+  }
+
+  /**
+   * @} end of park group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_park Vector Inverse Park transform
+   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkInvFormula.gif
+   * where pIalpha and pIbeta are the stator vector components,
+   * Id and Iq are rotor vector components and cosVal and sinVal are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_park
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Park transform
+   * @param[in]  Id       input coordinate of rotor reference frame d
+   * @param[in]  Iq       input coordinate of rotor reference frame q
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]  sinVal   sine value of rotation angle theta
+   * @param[in]  cosVal   cosine value of rotation angle theta
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32(
+  float32_t Id,
+  float32_t Iq,
+  float32_t * pIalpha,
+  float32_t * pIbeta,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+  }
+
+
+  /**
+   * @brief  Inverse Park transform for   Q31 version
+   * @param[in]  Id       input coordinate of rotor reference frame d
+   * @param[in]  Iq       input coordinate of rotor reference frame q
+   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]  sinVal   sine value of rotation angle theta
+   * @param[in]  cosVal   cosine value of rotation angle theta
+   *
+   * Scaling and Overflow Behavior:
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31(
+  q31_t Id,
+  q31_t Iq,
+  q31_t * pIalpha,
+  q31_t * pIbeta,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+  }
+
+  /**
+   * @} end of Inverse park group
+   */
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup LinearInterpolate Linear Interpolation
+   *
+   * Linear interpolation is a method of curve fitting using linear polynomials.
+   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
+   * \par
+   * \image html LinearInterp.gif "Linear interpolation"
+   *
+   * \par
+   * A  Linear Interpolate function calculates an output value(y), for the input(x)
+   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
+   * \par Algorithm:
+   * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * 

+   *
+   * \par
+   * This set of functions implements Linear interpolation process
+   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+   * sample of data and each call to the function returns a single processed value.
+   * S points to an instance of the Linear Interpolate function data structure.
+   * x is the input sample value. The functions returns the output value.
+   *
+   * \par
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table
+   * if x is below input range and returns last value of table if x is above range.
+   */
+
+  /**
+   * @addtogroup LinearInterpolate
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point Linear Interpolation Function.
+   * @param[in,out] S  is an instance of the floating-point Linear Interpolation structure
+   * @param[in]     x  input sample to process
+   * @return y processed output sample.
+   *
+   */
+  CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32(
+  arm_linear_interp_instance_f32 * S,
+  float32_t x)
+  {
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t *pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (int32_t) ((x - S->x1) / xSpacing);
+
+    if (i < 0)
+    {
+      /* Iniatilize output for below specified range as least output value of table */
+      y = pYData[0];
+    }
+    else if ((uint32_t)i >= S->nValues)
+    {
+      /* Iniatilize output for above specified range as last output value of table */
+      y = pYData[S->nValues - 1];
+    }
+    else
+    {
+      /* Calculation of nearest input values */
+      x0 = S->x1 +  i      * xSpacing;
+      x1 = S->x1 + (i + 1) * xSpacing;
+
+      /* Read of nearest output values */
+      y0 = pYData[i];
+      y1 = pYData[i + 1];
+
+      /* Calculation of output */
+      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+  }
+
+
+   /**
+   *
+   * @brief  Process function for the Q31 Linear Interpolation Function.
+   * @param[in] pYData   pointer to Q31 Linear Interpolation table
+   * @param[in] x        input sample to process
+   * @param[in] nValues  number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+  CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31(
+  q31_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & (q31_t)0xFFF00000) >> 20);
+
+    if (index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if (index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* shift left by 11 to keep fract in 1.31 format */
+      fract = (x & 0x000FFFFF) << 11;
+
+      /* Read two nearest output values from the index in 1.31(q31) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1];
+
+      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+      /* Convert y to 1.31 format */
+      return (y << 1u);
+    }
+  }
+
+
+  /**
+   *
+   * @brief  Process function for the Q15 Linear Interpolation Function.
+   * @param[in] pYData   pointer to Q15 Linear Interpolation table
+   * @param[in] x        input sample to process
+   * @param[in] nValues  number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+  CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15(
+  q15_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & (int32_t)0xFFF00000) >> 20);
+
+    if (index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if (index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index */
+      y0 = pYData[index];
+      y1 = pYData[index + 1];
+
+      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+      y = ((q63_t) y0 * (0xFFFFF - fract));
+
+      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+      y += ((q63_t) y1 * (fract));
+
+      /* convert y to 1.15 format */
+      return (q15_t) (y >> 20);
+    }
+  }
+
+
+  /**
+   *
+   * @brief  Process function for the Q7 Linear Interpolation Function.
+   * @param[in] pYData   pointer to Q7 Linear Interpolation table
+   * @param[in] x        input sample to process
+   * @param[in] nValues  number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   */
+  CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7(
+  q7_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    uint32_t index;                              /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    if (x < 0)
+    {
+      return (pYData[0]);
+    }
+    index = (x >> 20) & 0xfff;
+
+    if (index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index and are in 1.7(q7) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1];
+
+      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+      y = ((y0 * (0xFFFFF - fract)));
+
+      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+      y += (y1 * fract);
+
+      /* convert y to 1.7(q7) format */
+      return (q7_t) (y >> 20);
+     }
+  }
+
+  /**
+   * @} end of LinearInterpolate group
+   */
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+   * @param[in] x  input value in radians.
+   * @return  sin(x).
+   */
+  float32_t arm_sin_f32(
+  float32_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  sin(x).
+   */
+  q31_t arm_sin_q31(
+  q31_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  sin(x).
+   */
+  q15_t arm_sin_q15(
+  q15_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+   * @param[in] x  input value in radians.
+   * @return  cos(x).
+   */
+  float32_t arm_cos_f32(
+  float32_t x);
+
+
+  /**
+   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  cos(x).
+   */
+  q31_t arm_cos_q31(
+  q31_t x);
+
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+   * @param[in] x  Scaled input value in radians.
+   * @return  cos(x).
+   */
+  q15_t arm_cos_q15(
+  q15_t x);
+
+
+  /**
+   * @ingroup groupFastMath
+   */
+
+
+  /**
+   * @defgroup SQRT Square Root
+   *
+   * Computes the square root of a number.
+   * There are separate functions for Q15, Q31, and floating-point data types.
+   * The square root function is computed using the Newton-Raphson algorithm.
+   * This is an iterative algorithm of the form:
+   * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   * 

+   * where x1 is the current estimate,
+   * x0 is the previous estimate, and
+   * f'(x0) is the derivative of f() evaluated at x0.
+   * For the square root function, the algorithm reduces to:
+   * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * 

+   */
+
+
+  /**
+   * @addtogroup SQRT
+   * @{
+   */
+
+  /**
+   * @brief  Floating-point square root function.
+   * @param[in]  in    input value.
+   * @param[out] pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * in is negative value and returns zero output for negative values.
+   */
+  CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32(
+  float32_t in,
+  float32_t * pOut)
+  {
+    if (in >= 0.0f)
+    {
+
+#if   (__FPU_USED == 1) && defined ( __CC_ARM   )
+      *pOut = __sqrtf(in);
+#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+      *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined(__GNUC__)
+      *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
+      __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
+#else
+      *pOut = sqrtf(in);
+#endif
+
+      return (ARM_MATH_SUCCESS);
+    }
+    else
+    {
+      *pOut = 0.0f;
+      return (ARM_MATH_ARGUMENT_ERROR);
+    }
+  }
+
+
+  /**
+   * @brief Q31 square root function.
+   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+   * @param[out] pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * in is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut);
+
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out] pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * in is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut);
+
+  /**
+   * @} end of SQRT group
+   */
+
+
+  /**
+   * @brief floating-point Circular write function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const int32_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if (wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = (uint16_t)wOffset;
+  }
+
+
+
+  /**
+   * @brief floating-point Circular Read function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  int32_t * dst,
+  int32_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if (dst == (int32_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value  */
+      rOffset += bufferInc;
+
+      if (rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q15 Circular write function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q15_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if (wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = (uint16_t)wOffset;
+  }
+
+
+  /**
+   * @brief Q15 Circular Read function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q15_t * dst,
+  q15_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if (dst == (q15_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if (rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular write function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q7_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if (wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = (uint16_t)wOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular Read function.
+   */
+  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q7_t * dst,
+  q7_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while (i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if (dst == (q7_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if (rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Mean value of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Variance of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Variance of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Variance of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Root Mean Square of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Standard deviation of the elements of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+
+  /**
+   * @brief  Standard deviation of the elements of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+
+  /**
+   * @brief  Standard deviation of the elements of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output value.
+   */
+  void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+
+  /**
+   * @brief  Floating-point complex magnitude
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex magnitude
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex magnitude
+   * @param[in]  pSrc        points to the complex input vector
+   * @param[out] pDst        points to the real output vector
+   * @param[in]  numSamples  number of complex samples in the input vector
+   */
+  void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q15 complex dot product
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   * @param[out] realResult  real part of the result returned here
+   * @param[out] imagResult  imaginary part of the result returned here
+   */
+  void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult);
+
+
+  /**
+   * @brief  Q31 complex dot product
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   * @param[out] realResult  real part of the result returned here
+   * @param[out] imagResult  imaginary part of the result returned here
+   */
+  void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult);
+
+
+  /**
+   * @brief  Floating-point complex dot product
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   * @param[out] realResult  real part of the result returned here
+   * @param[out] imagResult  imaginary part of the result returned here
+   */
+  void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult);
+
+
+  /**
+   * @brief  Q15 complex-by-real multiplication
+   * @param[in]  pSrcCmplx   points to the complex input vector
+   * @param[in]  pSrcReal    points to the real input vector
+   * @param[out] pCmplxDst   points to the complex output vector
+   * @param[in]  numSamples  number of samples in each vector
+   */
+  void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex-by-real multiplication
+   * @param[in]  pSrcCmplx   points to the complex input vector
+   * @param[in]  pSrcReal    points to the real input vector
+   * @param[out] pCmplxDst   points to the complex output vector
+   * @param[in]  numSamples  number of samples in each vector
+   */
+  void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Floating-point complex-by-real multiplication
+   * @param[in]  pSrcCmplx   points to the complex input vector
+   * @param[in]  pSrcReal    points to the real input vector
+   * @param[out] pCmplxDst   points to the complex output vector
+   * @param[in]  numSamples  number of samples in each vector
+   */
+  void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Minimum value of a Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] result     is output pointer
+   * @param[in]  index      is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * result,
+  uint32_t * index);
+
+
+  /**
+   * @brief  Minimum value of a Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output pointer
+   * @param[in]  pIndex     is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+
+  /**
+   * @brief  Minimum value of a Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output pointer
+   * @param[out] pIndex     is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+
+  /**
+   * @brief  Minimum value of a floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[in]  blockSize  is the number of samples to process
+   * @param[out] pResult    is output pointer
+   * @param[out] pIndex     is the array index of the minimum value in the input buffer.
+   */
+  void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]  pSrc       points to the input buffer
+ * @param[in]  blockSize  length of the input vector
+ * @param[out] pResult    maximum value returned here
+ * @param[out] pIndex     index of maximum value returned here
+ */
+  void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+
+  /**
+   * @brief  Q15 complex-by-complex multiplication
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Q31 complex-by-complex multiplication
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief  Floating-point complex-by-complex multiplication
+   * @param[in]  pSrcA       points to the first input vector
+   * @param[in]  pSrcB       points to the second input vector
+   * @param[out] pDst        points to the output vector
+   * @param[in]  numSamples  number of complex samples in each vector
+   */
+  void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q31 vector.
+   * @param[in]  pSrc       points to the floating-point input vector
+   * @param[out] pDst       points to the Q31 output vector
+   * @param[in]  blockSize  length of the input vector
+   */
+  void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q15 vector.
+   * @param[in]  pSrc       points to the floating-point input vector
+   * @param[out] pDst       points to the Q15 output vector
+   * @param[in]  blockSize  length of the input vector
+   */
+  void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q7 vector.
+   * @param[in]  pSrc       points to the floating-point input vector
+   * @param[out] pDst       points to the Q7 output vector
+   * @param[in]  blockSize  length of the input vector
+   */
+  void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q15 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to floating-point vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q31 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q7 vector.
+   * @param[in]  pSrc       is input pointer
+   * @param[out] pDst       is output pointer
+   * @param[in]  blockSize  is the number of samples to process
+   */
+  void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
+   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+   * The underlying function f(x, y) is sampled on a regular grid and the interpolation process
+   * determines values between the grid points.
+   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+   * Bilinear interpolation is often used in image processing to rescale images.
+   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
+   * Algorithm
+   * \par
+   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+   * For floating-point, the instance structure is defined as:
+   * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * 

+   *
+   * \par
+   * where numRows specifies the number of rows in the table;
+   * numCols specifies the number of columns in the table;
+   * and pData points to an array of size numRows*numCols values.
+   * The data table pTable is organized in row order and the supplied data values fall on integer indexes.
+   * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers.
+   *
+   * \par
+   * Let (x, y) specify the desired interpolation point.  Then define:
+   * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * 

+   * \par
+   * The interpolated output point is computed as:
+   * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * 

+   * Note that the coordinates (x, y) contain integer and fractional components.
+   * The integer components specify which portion of the table to use while the
+   * fractional components control the interpolation processor.
+   *
+   * \par
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+   */
+
+  /**
+   * @addtogroup BilinearInterpolate
+   * @{
+   */
+
+
+  /**
+  *
+  * @brief  Floating-point bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate.
+  * @param[in]     Y  interpolation coordinate.
+  * @return out interpolated value.
+  */
+  CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32(
+  const arm_bilinear_interp_instance_f32 * S,
+  float32_t X,
+  float32_t Y)
+  {
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t *pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+  }
+
+
+  /**
+  *
+  * @brief  Q31 bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate in 12.20 format.
+  * @param[in]     Y  interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+  CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31(
+  arm_bilinear_interp_instance_q31 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + (int32_t)nCols * (cI)    ];
+    x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + (int32_t)nCols * (cI + 1)    ];
+    y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1  * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return ((q31_t)(acc << 2));
+  }
+
+
+  /**
+  * @brief  Q15 bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate in 12.20 format.
+  * @param[in]     Y  interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+  CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15(
+  arm_bilinear_interp_instance_q15 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
+    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
+    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return ((q15_t)(acc >> 36));
+  }
+
+
+  /**
+  * @brief  Q7 bilinear interpolation.
+  * @param[in,out] S  points to an instance of the interpolation structure.
+  * @param[in]     X  interpolation coordinate in 12.20 format.
+  * @param[in]     Y  interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+  CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7(
+  arm_bilinear_interp_instance_q7 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t *pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & (q31_t)0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];
+    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & (q31_t)0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];
+    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return ((q7_t)(acc >> 40));
+  }
+
+  /**
+   * @} end of BilinearInterpolate group
+   */
+
+
+/* SMMLAR */
+#define multAcc_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMLSR */
+#define multSub_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMULR */
+#define mult_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+/* SMMLA */
+#define multAcc_32x32_keep32(a, x, y) \
+    a += (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMLS */
+#define multSub_32x32_keep32(a, x, y) \
+    a -= (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMUL */
+#define mult_32x32_keep32(a, x, y) \
+    a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if   defined ( __CC_ARM )
+  /* Enter low optimization region - place directly above function definition */
+  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+    #define LOW_OPTIMIZATION_ENTER \
+       _Pragma ("push")         \
+       _Pragma ("O1")
+  #else
+    #define LOW_OPTIMIZATION_ENTER
+  #endif
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+    #define LOW_OPTIMIZATION_EXIT \
+       _Pragma ("pop")
+  #else
+    #define LOW_OPTIMIZATION_EXIT
+  #endif
+
+  /* Enter low optimization region - place directly above function definition */
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+  #define LOW_OPTIMIZATION_ENTER
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __GNUC__ )
+  #define LOW_OPTIMIZATION_ENTER \
+       __attribute__(( optimize("-O1") ))
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __ICCARM__ )
+  /* Enter low optimization region - place directly above function definition */
+  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+    #define LOW_OPTIMIZATION_ENTER \
+       _Pragma ("optimize=low")
+  #else
+    #define LOW_OPTIMIZATION_ENTER
+  #endif
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #define LOW_OPTIMIZATION_EXIT
+
+  /* Enter low optimization region - place directly above function definition */
+  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
+    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+       _Pragma ("optimize=low")
+  #else
+    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #endif
+
+  /* Exit low optimization region - place directly after end of function definition */
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TI_ARM__ )
+  #define LOW_OPTIMIZATION_ENTER
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __CSMC__ )
+  #define LOW_OPTIMIZATION_ENTER
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined ( __TASKING__ )
+  #define LOW_OPTIMIZATION_ENTER
+  #define LOW_OPTIMIZATION_EXIT
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef   __cplusplus
+}
+#endif
+
+/* Compiler specific diagnostic adjustment */
+#if   defined ( __CC_ARM )
+
+#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+
+#elif defined ( __ICCARM__ )
+
+#elif defined ( __TI_ARM__ )
+
+#elif defined ( __CSMC__ )
+
+#elif defined ( __TASKING__ )
+
+#else
+  #error Unknown compiler
+#endif
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
diff --git a/bsp/nuvoton/libraries/m2354/CMSIS/Include/cmsis_armcc.h b/bsp/nuvoton/libraries/m2354/CMSIS/Include/cmsis_armcc.h
new file mode 100644
index 0000000000..1d6a5fbd5c
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/CMSIS/Include/cmsis_armcc.h
@@ -0,0 +1,814 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler ARMCC (ARM compiler V5) header file
+ * @version  V5.0.2
+ * @date     13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
+     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
+  #define __ARM_ARCH_6M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
+  #define __ARM_ARCH_7M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+  #define __ARM_ARCH_7EM__          1
+#endif
+
+  /* __ARM_ARCH_8M_BASE__  not applicable */
+  /* __ARM_ARCH_8M_MAIN__  not applicable */
+
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         __packed union
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();     */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in integer value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in two unsigned short values.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order in signed short value
+  \details Reverses the byte order in a signed short value with sign extension to integer.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/bsp/nuvoton/libraries/m2354/CMSIS/Include/cmsis_armclang.h b/bsp/nuvoton/libraries/m2354/CMSIS/Include/cmsis_armclang.h
new file mode 100644
index 0000000000..2148297082
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/CMSIS/Include/cmsis_armclang.h
@@ -0,0 +1,1802 @@
+/**************************************************************************//**
+ * @file     cmsis_armclang.h
+ * @brief    CMSIS compiler ARMCLANG (ARM compiler V6) header file
+ * @version  V5.0.3
+ * @date     27. March 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#ifndef __ARM_COMPAT_H
+#include     /* Compatibility header for ARM Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((noreturn))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+
+  return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+/* #define __get_FPSCR      __builtin_arm_get_fpscr */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#else
+  return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+/* #define __set_FPSCR      __builtin_arm_set_fpscr */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "memory");
+#else
+  (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP          __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI          __builtin_arm_wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE          __builtin_arm_wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV          __builtin_arm_sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()        __builtin_arm_isb(0xF);
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()        __builtin_arm_dsb(0xF);
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()        __builtin_arm_dmb(0xF);
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in integer value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV          __builtin_bswap32
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in two unsigned short values.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16          __builtin_bswap16                /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
+#if 0
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order in signed short value
+  \details Reverses the byte order in a signed short value with sign extension to integer.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+                                                          /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+  int32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+                                                          /* ToDo ARMCLANG: check if __builtin_arm_rbit is supported */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return(result);
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             __builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT             __builtin_arm_ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEX                  (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+  int32_t result;
+
+  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/bsp/nuvoton/libraries/m2354/CMSIS/Include/cmsis_compiler.h b/bsp/nuvoton/libraries/m2354/CMSIS/Include/cmsis_compiler.h
new file mode 100644
index 0000000000..147c8089df
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/CMSIS/Include/cmsis_compiler.h
@@ -0,0 +1,353 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.0.2
+ * @date     13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include 
+
+/*
+ * ARM Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * ARM Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+
+  #include 
+
+  /* CMSIS compiler control architecture macros */
+  #if (__CORE__ == __ARM6M__) || (__CORE__ == __ARM6SM__)
+    #ifndef __ARM_ARCH_6M__
+      #define __ARM_ARCH_6M__                      1
+    #endif
+  #elif (__CORE__ == __ARM7M__)
+    #ifndef __ARM_ARCH_7M__
+      #define __ARM_ARCH_7M__                      1
+    #endif
+  #elif (__CORE__ == __ARM7EM__)
+    #ifndef __ARM_ARCH_7EM__
+      #define __ARM_ARCH_7EM__                     1
+    #endif
+  #endif
+
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __noreturn
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __root
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        __packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         __packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    __packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    //#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    //#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+  // Workaround for missing __CLZ intrinsic in
+  // various versions of the IAR compilers.
+  // __IAR_FEATURE_CLZ__ should be defined by
+  // the compiler that supports __CLZ internally.
+  #if (defined (__ARM_ARCH_6M__)) && (__ARM_ARCH_6M__ == 1) && (!defined (__IAR_FEATURE_CLZ__))
+    __STATIC_INLINE uint32_t __CLZ(uint32_t data)
+    {
+      if (data == 0u) { return 32u; }
+      
+      uint32_t count = 0;
+      uint32_t mask = 0x80000000;
+      
+      while ((data & mask) == 0)
+      {
+        count += 1u;
+        mask = mask >> 1u;
+      }
+      
+      return (count);
+    }
+  #endif
+
+
+/*
+ * TI ARM Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include 
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include 
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/bsp/nuvoton/libraries/m2354/CMSIS/Include/cmsis_gcc.h b/bsp/nuvoton/libraries/m2354/CMSIS/Include/cmsis_gcc.h
new file mode 100644
index 0000000000..05f7570394
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/CMSIS/Include/cmsis_gcc.h
@@ -0,0 +1,1979 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler GCC header file
+ * @version  V5.0.2
+ * @date     13. February 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+  #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((noreturn))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+
+  return(result);
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+}
+
+
+#if ((defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3)) && \
+     (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  return __builtin_arm_get_fpscr();
+#else
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#endif
+#else
+  return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  __builtin_arm_set_fpscr(fpscr);
+#else
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+  (void)fpscr;
+#endif
+}
+
+#endif /* ((defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+//{
+//  __ASM volatile ("nop");
+//}
+#define __NOP()                             __ASM volatile ("nop")       /* This implementation generates debug information */
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+//{
+//  __ASM volatile ("wfi");
+//}
+#define __WFI()                             __ASM volatile ("wfi")       /* This implementation generates debug information */
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+//{
+//  __ASM volatile ("wfe");
+//}
+#define __WFE()                             __ASM volatile ("wfe")       /* This implementation generates debug information */
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+//{
+//  __ASM volatile ("sev");
+//}
+#define __SEV()                             __ASM volatile ("sev")       /* This implementation generates debug information */
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in integer value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in two unsigned short values.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   Reverse byte order in signed short value
+  \details Reverses the byte order in a signed short value with sign extension to integer.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  int32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return(result);
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             __builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (__ARM_FEATURE_DSP == 1)                             /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/bsp/nuvoton/libraries/m2354/CMSIS/Include/cmsis_version.h b/bsp/nuvoton/libraries/m2354/CMSIS/Include/cmsis_version.h
new file mode 100644
index 0000000000..d458a6c859
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/CMSIS/Include/cmsis_version.h
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 0U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif
diff --git a/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_armv8mbl.h b/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_armv8mbl.h
new file mode 100644
index 0000000000..13003e1cd6
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_armv8mbl.h
@@ -0,0 +1,1878 @@
+/**************************************************************************//**
+ * @file     core_armv8mbl.h
+ * @brief    CMSIS ARMv8MBL Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MBL_H_GENERIC
+#define __CORE_ARMV8MBL_H_GENERIC
+
+#include 
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMv8MBL
+  @{
+ */
+ 
+#include "cmsis_version.h"
+
+/*  CMSIS definitions */
+#define __ARMv8MBL_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MBL_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __ARMv8MBL_CMSIS_VERSION       ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
+                                         __ARMv8MBL_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                     ( 2U)                                            /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MBL_H_DEPENDANT
+#define __CORE_ARMV8MBL_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __ARMv8MBL_REV
+    #define __ARMv8MBL_REV               0x0000U
+    #warning "__ARMv8MBL_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ETM_PRESENT
+    #define __ETM_PRESENT             0U
+    #warning "__ETM_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MTB_PRESENT
+    #define __MTB_PRESENT             0U
+    #warning "__MTB_PRESENT not defined in device header file; using default!"
+  #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MBL */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+        uint32_t RESERVED0[6U];
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+        uint32_t RESERVED0[7U];
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for ARMv8-M Baseline */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for ARMv8-M Baseline */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_armv8mml.h b/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_armv8mml.h
new file mode 100644
index 0000000000..5c4d6f6ee1
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_armv8mml.h
@@ -0,0 +1,2902 @@
+/**************************************************************************//**
+ * @file     core_armv8mml.h
+ * @brief    CMSIS ARMv8MML Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MML_H_GENERIC
+#define __CORE_ARMV8MML_H_GENERIC
+
+#include 
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMv8MML
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS ARMv8MML definitions */
+#define __ARMv8MML_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MML_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __ARMv8MML_CMSIS_VERSION       ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
+                                         __ARMv8MML_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                     (81U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MML_H_DEPENDANT
+#define __CORE_ARMV8MML_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __ARMv8MML_REV
+    #define __ARMv8MML_REV               0x0000U
+    #warning "__ARMv8MML_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MML */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED3[92U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_cm0.h b/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_cm0.h
new file mode 100644
index 0000000000..2f63b68610
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_cm0.h
@@ -0,0 +1,888 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include 
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M0
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000U
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M0 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M0 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_cm0plus.h b/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_cm0plus.h
new file mode 100644
index 0000000000..5c6135802b
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_cm0plus.h
@@ -0,0 +1,1021 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include 
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex-M0+
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                   /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000U
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0+ header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M0+ */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M0+ */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+    uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_cm23.h b/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_cm23.h
new file mode 100644
index 0000000000..b97fa9dd3f
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_cm23.h
@@ -0,0 +1,1878 @@
+/**************************************************************************//**
+ * @file     core_cm23.h
+ * @brief    CMSIS Cortex-M23 Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM23_H_GENERIC
+#define __CORE_CM23_H_GENERIC
+
+#include 
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M23
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS definitions */
+#define __CM23_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM23_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM23_CMSIS_VERSION       ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
+                                     __CM23_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                     (23U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM23_H_DEPENDANT
+#define __CORE_CM23_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM23_REV
+    #define __CM23_REV                0x0000U
+    #warning "__CM23_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ETM_PRESENT
+    #define __ETM_PRESENT             0U
+    #warning "__ETM_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MTB_PRESENT
+    #define __MTB_PRESENT             0U
+    #warning "__MTB_PRESENT not defined in device header file; using default!"
+  #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M23 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+        uint32_t RESERVED0[6U];
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+        uint32_t RESERVED0[7U];
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M23 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M23 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_cm3.h b/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_cm3.h
new file mode 100644
index 0000000000..3c1f01f497
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_cm3.h
@@ -0,0 +1,1928 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#include 
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M3
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM3_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (3U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200U
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+#else
+        uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_cm33.h b/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_cm33.h
new file mode 100644
index 0000000000..fab2f9a118
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_cm33.h
@@ -0,0 +1,2898 @@
+/**************************************************************************//**
+ * @file     core_cm33.h
+ * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM33_H_GENERIC
+#define __CORE_CM33_H_GENERIC
+
+#include 
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M33
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM33 definitions */
+#define __CM33_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                   /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
+                                     __CM33_CMSIS_VERSION_SUB           )     /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                 (33U)                                      /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM33_H_DEPENDANT
+#define __CORE_CM33_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM33_REV
+    #define __CM33_REV                0x0000U
+    #warning "__CM33_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED3[92U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function TZ_SysTick_Config_NS is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_cm4.h b/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_cm4.h
new file mode 100644
index 0000000000..ad3bc27d58
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_cm4.h
@@ -0,0 +1,2113 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include 
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M4
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM4_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000U
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_cm7.h b/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_cm7.h
new file mode 100644
index 0000000000..bf701fe8ef
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_cm7.h
@@ -0,0 +1,2655 @@
+/**************************************************************************//**
+ * @file     core_cm7.h
+ * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#include 
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M7
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB   ( __CM_CMSIS_VERSION_SUB)                  /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM7_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (7U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM7_REV
+    #define __CM7_REV               0x0000U
+    #warning "__CM7_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ICACHE_PRESENT
+    #define __ICACHE_PRESENT          0U
+    #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DCACHE_PRESENT
+    #define __DCACHE_PRESENT          0U
+    #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DTCM_PRESENT
+    #define __DTCM_PRESENT            0U
+    #warning "__DTCM_PRESENT        not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+        uint32_t RESERVED3[93U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED3[981U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = SCB->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################  Cache functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
+
+
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
+  */
+__STATIC_INLINE void SCB_EnableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
+  */
+__STATIC_INLINE void SCB_DisableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
+  */
+__STATIC_INLINE void SCB_EnableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+    __DSB();
+
+    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
+  */
+__STATIC_INLINE void SCB_DisableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    register uint32_t ccsidr;
+    register uint32_t sets;
+    register uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
+  */
+__STATIC_INLINE void SCB_CleanDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+     SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+   __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t)addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCIMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCIMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_sc000.h b/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_sc000.h
new file mode 100644
index 0000000000..bd26eaa0db
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_sc000.h
@@ -0,0 +1,1016 @@
+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include 
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC000
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC000_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC                 (000U)                                   /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC000_REV
+    #define __SC000_REV             0x0000U
+    #warning "__SC000_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+        uint32_t RESERVED1[154U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the SC000 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for SC000 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for SC000 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for SC000 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_sc300.h b/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_sc300.h
new file mode 100644
index 0000000000..780372a350
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/CMSIS/Include/core_sc300.h
@@ -0,0 +1,1903 @@
+/**************************************************************************//**
+ * @file     core_sc300.h
+ * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#include 
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.

+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.

+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.

+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC3000
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC300_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC                 (300U)                                   /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC300_REV
+    #define __SC300_REV               0x0000U
+    #warning "__SC300_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    IO Type Qualifiers are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+        uint32_t RESERVED1[129U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+        uint32_t RESERVED1[1U];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable __Vendor_SysTickConfig is set to 1, then the
+           function SysTick_Config is not included. In this case, the file device.h
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/nuvoton/libraries/m2354/CMSIS/Include/mpu_armv7.h b/bsp/nuvoton/libraries/m2354/CMSIS/Include/mpu_armv7.h
new file mode 100644
index 0000000000..fb1a339bec
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/CMSIS/Include/mpu_armv7.h
@@ -0,0 +1,182 @@
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for ARMv7 MPU
+ * @version  V5.0.2
+ * @date     09. June 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U)
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U)
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U)
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U)
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U)
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U)
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU)
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU)
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU)
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU)
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU)
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU)
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U)
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U)
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U)
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U)
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U)
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U)
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U)
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U)
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U)
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U)
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU)
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU)
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU)
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU)
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU)
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU)
+
+#define ARM_MPU_AP_NONE 0u 
+#define ARM_MPU_AP_PRIV 1u
+#define ARM_MPU_AP_URO  2u
+#define ARM_MPU_AP_FULL 3u
+#define ARM_MPU_AP_PRO  5u
+#define ARM_MPU_AP_RO   6u
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) ((BaseAddress & MPU_RBAR_ADDR_Msk) | (Region & MPU_RBAR_REGION_Msk) | (1UL << MPU_RBAR_VALID_Pos))
+
+/**
+* MPU Region Attribut and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/                         
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ((DisableExec      << MPU_RASR_XN_Pos)     & MPU_RASR_XN_Msk)     | \
+  ((AccessPermission << MPU_RASR_AP_Pos)     & MPU_RASR_AP_Msk)     | \
+  ((TypeExtField     << MPU_RASR_TEX_Pos)    & MPU_RASR_TEX_Msk)    | \
+  ((IsShareable      << MPU_RASR_S_Pos)      & MPU_RASR_S_Msk)      | \
+  ((IsCacheable      << MPU_RASR_C_Pos)      & MPU_RASR_C_Msk)      | \
+  ((IsBufferable     << MPU_RASR_B_Pos)      & MPU_RASR_B_Msk)      | \
+  ((SubRegionDisable << MPU_RASR_SRD_Pos)    & MPU_RASR_SRD_Msk)    | \
+  ((Size             << MPU_RASR_SIZE_Pos)   & MPU_RASR_SIZE_Msk)   | \
+  ((1UL              << MPU_RASR_ENABLE_Pos) & MPU_RASR_ENABLE_Msk)
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct _ARM_MPU_Region_t {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable()
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0u;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0u; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*sizeof(ARM_MPU_Region_t)/4u);
+}
+
+#endif
diff --git a/bsp/nuvoton/libraries/m2354/CMSIS/Include/tz_context.h b/bsp/nuvoton/libraries/m2354/CMSIS/Include/tz_context.h
new file mode 100644
index 0000000000..0784d26cac
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/CMSIS/Include/tz_context.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2015-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * ----------------------------------------------------------------------------
+ *
+ * $Date:        21. September 2016
+ * $Revision:    V1.0
+ *
+ * Project:      TrustZone for ARMv8-M
+ * Title:        Context Management for ARMv8-M TrustZone
+ *
+ * Version 1.0
+ *    Initial Release
+ *---------------------------------------------------------------------------*/
+  
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+ 
+#include 
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+  
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+ 
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+ 
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+ 
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+ 
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+ 
+#endif  // TZ_CONTEXT_H
diff --git a/bsp/nuvoton/libraries/m2354/CMSIS/SConscript b/bsp/nuvoton/libraries/m2354/CMSIS/SConscript
new file mode 100644
index 0000000000..904fca4146
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/CMSIS/SConscript
@@ -0,0 +1,16 @@
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+src = Split("""
+""")
+
+path = [cwd + '/Include',]
+
+group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = path)
+
+Return('group')
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/M2354.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/M2354.h
new file mode 100644
index 0000000000..5b546a056e
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/M2354.h
@@ -0,0 +1,1100 @@
+/**************************************************************************//**
+ * @file     M2354.h
+ * @version  V3.0
+ * @brief    Peripheral Access Layer Header File
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+
+/**
+  \mainpage Introduction
+  *
+  *
+  * This user manual describes the usage of M2354 device driver
+  *
+  * Disclaimer
+  *
+  * The Software is furnished "AS IS", without warranty as to performance or results, and
+  * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all
+  * warranties, express, implied or otherwise, with regard to the Software, its use, or
+  * operation, including without limitation any and all warranties of merchantability, fitness
+  * for a particular purpose, and non-infringement of intellectual property rights.
+  *
+  */
+
+
+#ifndef __M2354_H__
+#define __M2354_H__
+
+/*=============================================================================*/
+typedef volatile unsigned char  vu8;
+typedef volatile unsigned int   vu32;
+typedef volatile unsigned short vu16;
+#define M8(adr)  (*((vu8  *) (adr)))
+#define M16(adr) (*((vu16 *) (adr)))
+#define M32(adr) (*((vu32 *) (adr)))
+
+#define outpw(port,value)   (*((volatile unsigned int *)(port))=(value))
+#define inpw(port)          ((*((volatile unsigned int *)(port))))
+#define outpb(port,value)   (*((volatile unsigned char *)(port))=(value))
+#define inpb(port)          ((*((volatile unsigned char *)(port))))
+#define outps(port,value)   (*((volatile unsigned short *)(port))=(value))
+#define inps(port)          ((*((volatile unsigned short *)(port))))
+
+#define outp32(port,value)  (*((volatile unsigned int *)(port))=(value))
+#define inp32(port)         ((*((volatile unsigned int *)(port))))
+#define outp8(port,value)   (*((volatile unsigned char *)(port))=(value))
+#define inp8(port)          ((*((volatile unsigned char *)(port))))
+#define outp16(port,value)  (*((volatile unsigned short *)(port))=(value))
+#define inp16(port)         ((*((volatile unsigned short *)(port))))
+
+
+#define E_SUCCESS   0
+
+#define TRUE        (1L)
+#define FALSE       (0L)
+
+#define ENABLE      1
+#define DISABLE     0
+
+/* Bit Mask Definitions */
+#define BIT0    0x00000001UL
+#define BIT1    0x00000002UL
+#define BIT2    0x00000004UL
+#define BIT3    0x00000008UL
+#define BIT4    0x00000010UL
+#define BIT5    0x00000020UL
+#define BIT6    0x00000040UL
+#define BIT7    0x00000080UL
+#define BIT8    0x00000100UL
+#define BIT9    0x00000200UL
+#define BIT10   0x00000400UL
+#define BIT11   0x00000800UL
+#define BIT12   0x00001000UL
+#define BIT13   0x00002000UL
+#define BIT14   0x00004000UL
+#define BIT15   0x00008000UL
+#define BIT16   0x00010000UL
+#define BIT17   0x00020000UL
+#define BIT18   0x00040000UL
+#define BIT19   0x00080000UL
+#define BIT20   0x00100000UL
+#define BIT21   0x00200000UL
+#define BIT22   0x00400000UL
+#define BIT23   0x00800000UL
+#define BIT24   0x01000000UL
+#define BIT25   0x02000000UL
+#define BIT26   0x04000000UL
+#define BIT27   0x08000000UL
+#define BIT28   0x10000000UL
+#define BIT29   0x20000000UL
+#define BIT30   0x40000000UL
+#define BIT31   0x80000000UL
+
+
+/* Byte Mask Definitions */
+#define BYTE0_Msk               (0x000000FFUL)
+#define BYTE1_Msk               (0x0000FF00UL)
+#define BYTE2_Msk               (0x00FF0000UL)
+#define BYTE3_Msk               (0xFF000000UL)
+
+#define _GET_BYTE0(u32Param)    (((u32Param) & BYTE0_Msk)        )  /*!< Extract Byte 0 (Bit  0~ 7) from parameter u32Param */
+#define _GET_BYTE1(u32Param)    (((u32Param) & BYTE1_Msk) >>  8UL)  /*!< Extract Byte 1 (Bit  8~15) from parameter u32Param */
+#define _GET_BYTE2(u32Param)    (((u32Param) & BYTE2_Msk) >> 16UL)  /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */
+#define _GET_BYTE3(u32Param)    (((u32Param) & BYTE3_Msk) >> 24UL)  /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/******************************************************************************/
+/*                Processor and Core Peripherals                              */
+/******************************************************************************/
+/** @addtogroup CMSIS_Device CMSIS Definitions
+  Configuration of the Cortex-M23 Processor and Core Peripherals
+  @{
+*/
+
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+/**
+ * @details  Interrupt Number Definition. The maximum of 32 Specific Interrupts are possible.
+ */
+typedef enum IRQn
+{
+    /******  Cortex-M0 Processor Exceptions Numbers ***************************************************/
+    NonMaskableInt_IRQn       = -14,      /*!< 2 Non Maskable Interrupt                             */
+    HardFault_IRQn            = -13,      /*!< 3 Cortex-M23 Hard Fault Interrupt                    */
+    SVCall_IRQn               = -5,       /*!< 11 Cortex-M23 SV Call Interrupt                      */
+    PendSV_IRQn               = -2,       /*!< 14 Cortex-M23 Pend SV Interrupt                      */
+    SysTick_IRQn              = -1,       /*!< 15 Cortex-M23 System Tick Interrupt                  */
+
+    /******  ARMIKMCU Swift specific Interrupt Numbers ************************************************/
+
+    BOD_IRQn                      = 0,        /*!< Brown Out detection Interrupt                    */
+    IRC_IRQn                      = 1,        /*!< Internal RC Interrupt                            */
+    PWRWU_IRQn                    = 2,        /*!< Power Down Wake Up Interrupt                     */
+    RAMPE_IRQn                    = 3,        /*!< SRAM parity check failed Interrupt               */
+    CKFAIL_IRQn                   = 4,        /*!< Clock failed Interrupt                           */
+    ISP_IRQn                      = 5,        /*!< FMC ISP Interrupt                                */
+    RTC_IRQn                      = 6,        /*!< Real Time Clock Interrupt                        */
+    RTC_TAMPER_IRQn               = 7,        /*!< RTC Tamper detection Interrupt                   */
+    WDT_IRQn                      = 8,        /*!< Watchdog Timer Interrupt                         */
+    WWDT_IRQn                     = 9,        /*!< Window Watchdog Timer Interrupt                  */
+    EINT0_IRQn                    = 10,       /*!< External Input 0 Interrupt                       */
+    EINT1_IRQn                    = 11,       /*!< External Input 1 Interrupt                       */
+    EINT2_IRQn                    = 12,       /*!< External Input 2 Interrupt                       */
+    EINT3_IRQn                    = 13,       /*!< External Input 3 Interrupt                       */
+    EINT4_IRQn                    = 14,       /*!< External Input 4 Interrupt                       */
+    EINT5_IRQn                    = 15,       /*!< External Input 5 Interrupt                       */
+    GPA_IRQn                      = 16,       /*!< GPIO Port A Interrupt                            */
+    GPB_IRQn                      = 17,       /*!< GPIO Port B Interrupt                            */
+    GPC_IRQn                      = 18,       /*!< GPIO Port C Interrupt                            */
+    GPD_IRQn                      = 19,       /*!< GPIO Port D Interrupt                            */
+    GPE_IRQn                      = 20,       /*!< GPIO Port E Interrupt                            */
+    GPF_IRQn                      = 21,       /*!< GPIO Port F Interrupt                            */
+    QSPI0_IRQn                    = 22,       /*!< QSPI0 Interrupt                                  */
+    SPI0_IRQn                     = 23,       /*!< SPI0 Interrupt                                   */
+    BRAKE0_IRQn                   = 24,       /*!< BRAKE0 Interrupt                                 */
+    EPWM0_P0_IRQn                 = 25,       /*!< EPWM0P0 Interrupt                                */
+    EPWM0_P1_IRQn                 = 26,       /*!< EPWM0P1 Interrupt                                */
+    EPWM0_P2_IRQn                 = 27,       /*!< EPWM0P2 Interrupt                                */
+    BRAKE1_IRQn                   = 28,       /*!< BRAKE1 Interrupt                                 */
+    EPWM1_P0_IRQn                 = 29,       /*!< EPWM1P0 Interrupt                                */
+    EPWM1_P1_IRQn                 = 30,       /*!< EPWM1P1 Interrupt                                */
+    EPWM1_P2_IRQn                 = 31,       /*!< EPWM1P2 Interrupt                                */
+    TMR0_IRQn                     = 32,       /*!< Timer 0 Interrupt                                */
+    TMR1_IRQn                     = 33,       /*!< Timer 1 Interrupt                                */
+    TMR2_IRQn                     = 34,       /*!< Timer 2 Interrupt                                */
+    TMR3_IRQn                     = 35,       /*!< Timer 3 Interrupt                                */
+    UART0_IRQn                    = 36,       /*!< UART 0 Interrupt                                 */
+    UART1_IRQn                    = 37,       /*!< UART 1 Interrupt                                 */
+    I2C0_IRQn                     = 38,       /*!< I2C 0 Interrupt                                  */
+    I2C1_IRQn                     = 39,       /*!< I2C 1 Interrupt                                  */
+    PDMA0_IRQn                    = 40,       /*!< Peripheral DMA 0 Interrupt                       */
+    DAC_IRQn                      = 41,       /*!< DAC Interrupt                                    */
+    EADC0_IRQn                    = 42,       /*!< EADC Source 0 Interrupt                          */
+    EADC1_IRQn                    = 43,       /*!< EADC Source 1 Interrupt                          */
+    ACMP01_IRQn                   = 44,       /*!< Analog Comparator 0 and 1 Interrupt              */
+    EADC2_IRQn                    = 46,       /*!< EADC Source 2 Interrupt                          */
+    EADC3_IRQn                    = 47,       /*!< EADC Source 3 Interrupt                          */
+    UART2_IRQn                    = 48,       /*!< UART2 Interrupt                                  */
+    UART3_IRQn                    = 49,       /*!< UART3 Interrupt                                  */
+    SPI1_IRQn                     = 51,       /*!< SPI1 Interrupt                                   */
+    SPI2_IRQn                     = 52,       /*!< SPI2 Interrupt                                   */
+    USBD_IRQn                     = 53,       /*!< USB device Interrupt                             */
+    USBH_IRQn                     = 54,       /*!< USB host Interrupt                               */
+    USBOTG_IRQn                   = 55,       /*!< USB OTG Interrupt                                */
+    CAN0_IRQn                     = 56,       /*!< CAN0 Interrupt                                   */
+    SC0_IRQn                      = 58,       /*!< Smart Card 0 Interrupt                           */
+    SC1_IRQn                      = 59,       /*!< Smart Card 1 Interrupt                           */
+    SC2_IRQn                      = 60,       /*!< Smart Card 2 Interrupt                           */
+    SPI3_IRQn                     = 62,       /*!< SPI3 Interrupt                                   */
+    SDH0_IRQn                     = 64,       /*!< SDH0 Interrupt                                   */
+    I2S0_IRQn                     = 68,       /*!< I2S0 Interrupt                                   */
+    CRPT_IRQn                     = 71,       /*!< CRPT Interrupt                                   */
+    GPG_IRQn                      = 72,       /*!< GPIO Port G Interrupt                            */
+    EINT6_IRQn                    = 73,       /*!< External Input 6 Interrupt                       */
+    UART4_IRQn                    = 74,       /*!< UART4 Interrupt                                  */
+    UART5_IRQn                    = 75,       /*!< UART5 Interrupt                                  */
+    USCI0_IRQn                    = 76,       /*!< USCI0 Interrupt                                  */
+    USCI1_IRQn                    = 77,       /*!< USCI1 Interrupt                                  */
+    BPWM0_IRQn                    = 78,       /*!< BPWM0 Interrupt                                  */
+    BPWM1_IRQn                    = 79,       /*!< BPWM1 Interrupt                                  */
+    I2C2_IRQn                     = 82,       /*!< I2C2 Interrupt                                   */
+    QEI0_IRQn                     = 84,       /*!< QEI0 Interrupt                                   */
+    QEI1_IRQn                     = 85,       /*!< QEI1 Interrupt                                   */
+    ECAP0_IRQn                    = 86,       /*!< ECAP0 Interrupt                                  */
+    ECAP1_IRQn                    = 87,       /*!< ECAP1 Interrupt                                  */
+    GPH_IRQn                      = 88,       /*!< GPIO Port H Interrupt                            */
+    EINT7_IRQn                    = 89,       /*!< External Input 7 Interrupt                       */
+    PDMA1_IRQn                    = 98,       /*!< Peripheral DMA 1 Interrupt                       */
+    SCU_IRQn                      = 99,       /*!< SCU Interrupt                                    */
+    LCD_IRQn                      = 100,      /*!< LCD interrupt                                    */
+    TRNG_IRQn                     = 101,      /*!< TRNG interrupt                                   */
+    KS_IRQn                       = 109,      /*!< Key Store interrupt                              */
+    TAMPER_IRQn                   = 110,      /*!< TAMPER interrupt                                 */
+    EWDT_IRQn                     = 111,      /*!< Extra Watchdog Timer interrupt                   */
+    EWWDT_IRQn                    = 112,      /*!< Extra Window Watchdog Timer interrupt            */
+    NS_ISP_IRQn                   = 113,      /*!< Non-secure FMC ISP interrupt                     */
+    TMR4_IRQn                     = 114,      /*!< Timer 4 Interrupt                                */
+    TMR5_IRQn                     = 115,      /*!< Timer 5 Interrupt                                */
+
+
+} IRQn_Type;
+
+
+/* ================================================================================ */
+/* ================      Processor and Core Peripheral Section     ================ */
+/* ================================================================================ */
+
+/* -------  Start of section using anonymous unions and disabling warnings  ------- */
+#if   defined (__CC_ARM)
+#pragma push
+#pragma anon_unions
+#elif defined (__ICCARM__)
+#pragma language=extended
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang diagnostic push
+#pragma clang diagnostic ignored "-Wc11-extensions"
+#pragma clang diagnostic ignored "-Wreserved-id-macro"
+#elif defined (__GNUC__)
+/* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+/* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+#pragma warning 586
+#elif defined (__CSMC__)
+/* anonymous unions are enabled by default */
+#else
+#warning Not supported compiler type
+#endif
+
+
+/* --------  Configuration of the Cortex-ARMv8MBL Processor and Core Peripherals  ------- */
+#define __ARMv8MBL_REV            0x0000U   /* Core revision r0p0 */
+#define __SAU_PRESENT             1U        /* SAU present */
+#define __SAUREGION_PRESENT       1U        /* SAU present */
+#define __MPU_PRESENT             1U        /* MPU present */
+#define __VTOR_PRESENT            1U        /* VTOR present */
+#define __NVIC_PRIO_BITS          2U        /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig    0U        /* Set to 1 if different SysTick Config is used */
+#define USE_ASSERT                0U        /* Define to use Assert function or not */
+
+/**@}*/ /* end of group CMSIS */
+
+#include "core_armv8mbl.h"                  /* Processor and core peripherals */
+#include "system_M2354.h"                   /* System Header */
+#include "nu_partition_M2354.h"
+
+/**
+ * Initialize the system clock
+ *
+ * @brief  Setup the micro controller system
+ *         Initialize the PLL and update the SystemFrequency variable
+ */
+extern void SystemInit(void);
+
+
+/******************************************************************************/
+/*                Device Specific Peripheral registers structures             */
+/******************************************************************************/
+
+
+#include "acmp_reg.h"
+#include "bpwm_reg.h"
+#include "can_reg.h"
+#include "clk_reg.h"
+#include "crc_reg.h"
+#include "dac_reg.h"
+#include "eadc_reg.h"
+#include "ebi_reg.h"
+#include "ecap_reg.h"
+#include "fmc_reg.h"
+#include "gpio_reg.h"
+#include "hdiv_reg.h"
+#include "i2c_reg.h"
+#include "i2s_reg.h"
+#include "pdma_reg.h"
+#include "epwm_reg.h"
+#include "qei_reg.h"
+#include "rtc_reg.h"
+#include "sc_reg.h"
+#include "scu_reg.h"
+#include "sdh_reg.h"
+#include "qspi_reg.h"
+#include "spi_reg.h"
+#include "sys_reg.h"
+#include "timer_reg.h"
+#include "trng_reg.h"
+#include "uart_reg.h"
+#include "ui2c_reg.h"
+#include "usbh_reg.h"
+#include "usbd_reg.h"
+#include "otg_reg.h"
+#include "crpt_reg.h"
+#include "uspi_reg.h"
+#include "uuart_reg.h"
+#include "wdt_reg.h"
+#include "wwdt_reg.h"
+#include "keystore_reg.h"
+#include "tamper_reg.h"
+#include "lcd_reg.h"
+#include "ewdt_reg.h"
+#include "ewwdt_reg.h"
+
+
+
+/******************************************************************************/
+/*                         Peripheral memory map                              */
+/******************************************************************************/
+/** @addtogroup PERIPHERAL_BASE Peripheral Memory Base
+  Memory Mapped Structure for Series Peripheral
+  @{
+ */
+
+
+/* Peripheral and SRAM base address */
+#define SRAM_BASE            (0x20000000UL)                              /*!< (SRAM      ) Base Address */
+#define PERIPH_BASE          (0x40000000UL)                              /*!< (Peripheral) Base Address */
+#define NS_OFFSET            (0x10000000UL)
+
+/* Peripheral memory map */
+#define AHBPERIPH_BASE       PERIPH_BASE
+#define APBPERIPH_BASE       (PERIPH_BASE + 0x00040000UL)
+
+/*!< AHB peripherals */
+#define SYS_BASE             (AHBPERIPH_BASE + 0x00000UL)
+#define CLK_BASE             (AHBPERIPH_BASE + 0x00200UL)
+#define INT_BASE             (AHBPERIPH_BASE + 0x00300UL)
+#define GPIO_BASE            (AHBPERIPH_BASE + 0x04000UL)
+#define GPIOA_BASE           (AHBPERIPH_BASE + 0x04000UL)
+#define GPIOB_BASE           (AHBPERIPH_BASE + 0x04040UL)
+#define GPIOC_BASE           (AHBPERIPH_BASE + 0x04080UL)
+#define GPIOD_BASE           (AHBPERIPH_BASE + 0x040C0UL)
+#define GPIOE_BASE           (AHBPERIPH_BASE + 0x04100UL)
+#define GPIOF_BASE           (AHBPERIPH_BASE + 0x04140UL)
+#define GPIOG_BASE           (AHBPERIPH_BASE + 0x04180UL)
+#define GPIOH_BASE           (AHBPERIPH_BASE + 0x041C0UL)
+#define GPIO_DBCTL_BASE      (AHBPERIPH_BASE + 0x04440UL)
+#define GPIO_PIN_DATA_BASE   (AHBPERIPH_BASE + 0x04800UL)
+#define PDMA0_BASE           (AHBPERIPH_BASE + 0x08000UL)
+#define PDMA1_BASE           (AHBPERIPH_BASE + 0x18000UL)
+#define USBH_BASE            (AHBPERIPH_BASE + 0x09000UL)
+#define FMC_BASE             (AHBPERIPH_BASE + 0x0C000UL)
+#define SDH0_BASE            (AHBPERIPH_BASE + 0x0D000UL)
+#define SDH1_BASE            (AHBPERIPH_BASE + 0x0E000UL)
+#define EBI_BASE             (AHBPERIPH_BASE + 0x10000UL)
+#define CRC_BASE             (AHBPERIPH_BASE + 0x31000UL)
+#define CRPT_BASE            (AHBPERIPH_BASE + 0x32000UL)
+#define SCU_BASE             (AHBPERIPH_BASE + 0x2F000UL)
+#define FVC_BASE             (AHBPERIPH_BASE + 0x2F500UL)
+#define DPM_BASE             (AHBPERIPH_BASE + 0x2F600UL)
+#define PLM_BASE             (AHBPERIPH_BASE + 0x2F700UL)
+
+#define BTF_BASE             (AHBPERIPH_BASE + 0x2F800UL)
+
+/*!< APB peripherals */
+#define WDT_BASE             (APBPERIPH_BASE + 0x00000UL)
+#define WWDT_BASE            (APBPERIPH_BASE + 0x00100UL)
+#define RTC_BASE             (APBPERIPH_BASE + 0x01000UL)
+#define EADC_BASE            (APBPERIPH_BASE + 0x03000UL)
+#define ACMP01_BASE          (APBPERIPH_BASE + 0x05000UL)
+#define DAC0_BASE            (APBPERIPH_BASE + 0x07000UL)
+#define DAC1_BASE            (APBPERIPH_BASE + 0x07040UL)
+#define I2S0_BASE            (APBPERIPH_BASE + 0x08000UL)
+#define OTG_BASE             (APBPERIPH_BASE + 0x0D000UL)
+#define TMR01_BASE           (APBPERIPH_BASE + 0x10000UL)
+#define TMR23_BASE           (APBPERIPH_BASE + 0x11000UL)
+#define TMR45_BASE           (APBPERIPH_BASE + 0x12000UL)
+#define EPWM0_BASE           (APBPERIPH_BASE + 0x18000UL)
+#define EPWM1_BASE           (APBPERIPH_BASE + 0x19000UL)
+#define BPWM0_BASE           (APBPERIPH_BASE + 0x1A000UL)
+#define BPWM1_BASE           (APBPERIPH_BASE + 0x1B000UL)
+#define QSPI0_BASE           (APBPERIPH_BASE + 0x20000UL)
+#define SPI0_BASE            (APBPERIPH_BASE + 0x21000UL)
+#define SPI1_BASE            (APBPERIPH_BASE + 0x22000UL)
+#define SPI2_BASE            (APBPERIPH_BASE + 0x23000UL)
+#define SPI3_BASE            (APBPERIPH_BASE + 0x24000UL)
+#define UART0_BASE           (APBPERIPH_BASE + 0x30000UL)
+#define UART0_BASE           (APBPERIPH_BASE + 0x30000UL)
+#define UART1_BASE           (APBPERIPH_BASE + 0x31000UL)
+#define UART2_BASE           (APBPERIPH_BASE + 0x32000UL)
+#define UART3_BASE           (APBPERIPH_BASE + 0x33000UL)
+#define UART4_BASE           (APBPERIPH_BASE + 0x34000UL)
+#define UART5_BASE           (APBPERIPH_BASE + 0x35000UL)
+#define I2C0_BASE            (APBPERIPH_BASE + 0x40000UL)
+#define I2C1_BASE            (APBPERIPH_BASE + 0x41000UL)
+#define I2C2_BASE            (APBPERIPH_BASE + 0x42000UL)
+#define SC0_BASE             (APBPERIPH_BASE + 0x50000UL)
+#define SC1_BASE             (APBPERIPH_BASE + 0x51000UL)
+#define SC2_BASE             (APBPERIPH_BASE + 0x52000UL)
+#define CAN0_BASE            (APBPERIPH_BASE + 0x60000UL)
+#define QEI0_BASE            (APBPERIPH_BASE + 0x70000UL)
+#define QEI1_BASE            (APBPERIPH_BASE + 0x71000UL)
+#define ECAP0_BASE           (APBPERIPH_BASE + 0x74000UL)
+#define ECAP1_BASE           (APBPERIPH_BASE + 0x75000UL)
+#define TRNG_BASE            (APBPERIPH_BASE + 0x79000UL)
+#define USBD_BASE            (APBPERIPH_BASE + 0x80000UL)
+#define USCI0_BASE           (APBPERIPH_BASE + 0x90000UL)
+#define USCI1_BASE           (APBPERIPH_BASE + 0x91000UL)
+
+#define EWDT_BASE            (APBPERIPH_BASE + 0x02000UL)
+#define EWWDT_BASE           (APBPERIPH_BASE + 0x02100UL)
+
+
+#define KS_BASE              (AHBPERIPH_BASE + 0x35000UL)
+#define TAMPER_BASE          (AHBPERIPH_BASE + 0xBD000UL)
+#define LCD_BASE             (AHBPERIPH_BASE + 0xBB000UL)
+
+
+
+/**@}*/ /* PERIPHERAL */
+
+/******************************************************************************/
+/*                         Peripheral declaration                             */
+/******************************************************************************/
+
+/** @addtogroup PMODULE Peripheral Pointer
+  The Declaration of Peripheral Pointer
+  @{
+ */
+
+/** @addtogroup PMODULE_S Secure Peripheral Pointer
+ The Declaration of Secure Peripheral Pointer
+ @{
+*/
+
+#define PA_S                  ((GPIO_T *) GPIOA_BASE)                     /*!< GPIO PORTA Pointer                 */
+#define PB_S                  ((GPIO_T *) GPIOB_BASE)                     /*!< GPIO PORTB Pointer                 */
+#define PC_S                  ((GPIO_T *) GPIOC_BASE)                     /*!< GPIO PORTC Pointer                 */
+#define PD_S                  ((GPIO_T *) GPIOD_BASE)                     /*!< GPIO PORTD Pointer                 */
+#define PE_S                  ((GPIO_T *) GPIOE_BASE)                     /*!< GPIO PORTE Pointer                 */
+#define PF_S                  ((GPIO_T *) GPIOF_BASE)                     /*!< GPIO PORTF Pointer                 */
+#define PG_S                  ((GPIO_T *) GPIOG_BASE)                     /*!< GPIO PORTG Pointer                 */
+#define PH_S                  ((GPIO_T *) GPIOH_BASE)                     /*!< GPIO PORTH Pointer                 */
+
+#define UART0_S               ((UART_T *) UART0_BASE)                     /*!< UART0 Pointer                      */
+#define UART1_S               ((UART_T *) UART1_BASE)                     /*!< UART1 Pointer                      */
+#define UART2_S               ((UART_T *) UART2_BASE)                     /*!< UART2 Pointer                      */
+#define UART3_S               ((UART_T *) UART3_BASE)                     /*!< UART3 Pointer                      */
+#define UART4_S               ((UART_T *) UART4_BASE)                     /*!< UART4 Pointer                      */
+#define UART5_S               ((UART_T *) UART5_BASE)                     /*!< UART5 Pointer                      */
+
+
+#define TIMER0_S              ((TIMER_T *) TMR01_BASE)                    /*!< TIMER0 Pointer                      */
+#define TIMER1_S              ((TIMER_T *) (TMR01_BASE + 0x100UL))        /*!< TIMER1 Pointer                      */
+#define TIMER2_S              ((TIMER_T *) TMR23_BASE)                    /*!< TIMER2 Pointer                      */
+#define TIMER3_S              ((TIMER_T *) (TMR23_BASE + 0x100UL))        /*!< TIMER3 Pointer                      */
+#define TIMER4_S              ((TIMER_T *) TMR45_BASE)                    /*!< TIMER4 Pointer                      */
+#define TIMER5_S              ((TIMER_T *) (TMR45_BASE + 0x100UL))        /*!< TIMER5 Pointer                      */
+
+#define WDT_S                 ((WDT_T *) WDT_BASE)                        /*!< Watch Dog Timer Pointer             */
+
+#define WWDT_S                ((WWDT_T *) WWDT_BASE)                      /*!< Window Watch Dog Timer Pointer      */
+
+#define QSPI0_S               ((QSPI_T *) QSPI0_BASE)                     /*!< QSPI0 Pointer                       */
+#define SPI0_S                ((SPI_T *) SPI0_BASE)                       /*!< SPI0 Pointer                        */
+#define SPI1_S                ((SPI_T *) SPI1_BASE)                       /*!< SPI1 Pointer                        */
+#define SPI2_S                ((SPI_T *) SPI2_BASE)                       /*!< SPI2 Pointer                        */
+#define SPI3_S                ((SPI_T *) SPI3_BASE)                       /*!< SPI3 Pointer                        */
+
+#define I2S0_S                ((I2S_T *) I2S0_BASE)                       /*!< I2S0 Pointer                        */
+
+#define I2C0_S                ((I2C_T *) I2C0_BASE)                       /*!< I2C0 Pointer                        */
+#define I2C1_S                ((I2C_T *) I2C1_BASE)                       /*!< I2C1 Pointer                        */
+#define I2C2_S                ((I2C_T *) I2C2_BASE)                       /*!< I2C1 Pointer                        */
+
+#define QEI0_S                ((QEI_T *) QEI0_BASE)                       /*!< QEI0 Pointer                        */
+#define QEI1_S                ((QEI_T *) QEI1_BASE)                       /*!< QEI1 Pointer                        */
+
+#define RTC_S                 ((RTC_T *) RTC_BASE)                        /*!< RTC Pointer                         */
+
+#define ACMP01_S              ((ACMP_T *) ACMP01_BASE)                    /*!< ACMP01 Pointer                      */
+
+#define CLK_S                 ((CLK_T *) CLK_BASE)                        /*!< System Clock Controller Pointer     */
+
+#define DAC0_S                ((DAC_T *) DAC0_BASE)                       /*!< DAC0 Pointer                        */
+#define DAC1_S                ((DAC_T *) DAC1_BASE)                       /*!< DAC1 Pointer                        */
+
+#define EADC_S                ((EADC_T *) EADC_BASE)                      /*!< EADC Pointer                        */
+
+#define SYS_S                 ((SYS_T *) SYS_BASE)                        /*!< System Global Controller Pointer    */
+
+#define SYSINT_S              ((SYS_INT_T *) INT_BASE)                    /*!< Interrupt Source Controller Pointer */
+
+#define FMC_S                 ((FMC_T *) FMC_BASE)                        /*!< Flash Memory Controller */
+
+#define SDH0_S                ((SDH_T *)   SDH0_BASE)
+
+#define CRPT_S                ((CRPT_T *) CRPT_BASE)                      /*!< Crypto Accelerator Pointer          */
+#define TRNG_S                ((TRNG_T *)TRNG_BASE)                       /*!< True Random Number Pointer          */
+
+#define BPWM0_S               ((BPWM_T *) BPWM0_BASE)                     /*!< BPWM0 Pointer                       */
+#define BPWM1_S               ((BPWM_T *) BPWM1_BASE)                     /*!< BPWM1 Pointer                       */
+
+#define EPWM0_S               ((EPWM_T *) EPWM0_BASE)                     /*!< EPWM0 Pointer                       */
+#define EPWM1_S               ((EPWM_T *) EPWM1_BASE)                     /*!< EPWM1 Pointer                       */
+
+#define SC0_S                 ((SC_T *) SC0_BASE)                         /*!< SC0 Pointer                         */
+#define SC1_S                 ((SC_T *) SC1_BASE)                         /*!< SC1 Pointer                         */
+#define SC2_S                 ((SC_T *) SC2_BASE)                         /*!< SC2 Pointer                         */
+
+#define EBI_S                 ((EBI_T *) EBI_BASE)                        /*!< EBI Pointer                         */
+
+#define CRC_S                 ((CRC_T *) CRC_BASE)                        /*!< CRC Pointer                         */
+
+#define USBD_S                ((USBD_T *) USBD_BASE)                      /*!< USB Device Pointer                  */
+#define USBH_S                ((USBH_T *) USBH_BASE)                      /*!< USBH Pointer                        */
+#define OTG_S                 ((OTG_T *) OTG_BASE)                        /*!< OTG Pointer                         */
+
+#define PDMA0_S               ((PDMA_T *) PDMA0_BASE)                     /*!< PDMA0 Pointer                        */
+#define PDMA1_S               ((PDMA_T *) PDMA1_BASE)                     /*!< PDMA1 Pointer                        */
+
+#define UI2C0_S               ((UI2C_T *) USCI0_BASE)                     /*!< UI2C0 Pointer                       */
+#define UI2C1_S               ((UI2C_T *) USCI1_BASE)                     /*!< UI2C1 Pointer                       */
+
+#define USPI0_S               ((USPI_T *) USCI0_BASE)                     /*!< USPI0 Pointer                       */
+#define USPI1_S               ((USPI_T *) USCI1_BASE)                     /*!< USPI1 Pointer                       */
+
+#define UUART0_S              ((UUART_T *) USCI0_BASE)                    /*!< UUART0 Pointer                      */
+#define UUART1_S              ((UUART_T *) USCI1_BASE)                    /*!< UUART1 Pointer                      */
+
+#define SCU_S                 ((SCU_T *) SCU_BASE)                        /*!< SCU Pointer                         */
+#define ECAP0_S               ((ECAP_T *) ECAP0_BASE)                     /*!< ECAP0 Pointer                       */
+#define ECAP1_S               ((ECAP_T *) ECAP1_BASE)                     /*!< ECAP1 Pointer                       */
+
+#define CAN0_S                ((CAN_T *)CAN0_BASE)                        /*!< CAN0 Pointer                        */
+
+#define KS_S                  ((KS_T *)KS_BASE)                           /*!< Key Store Pointer                   */
+#define TAMPER_S              ((TAMPER_T *)TAMPER_BASE)                   /*!< TAMPER Pointer                      */
+#define LCD_S                 ((LCD_T *)LCD_BASE)                         /*!< LCD Pointer                         */
+
+#define EWDT_S                ((EWDT_T *) EWDT_BASE)                      /*!< Extra Watch Dog Timer Pointer       */
+
+#define EWWDT_S               ((EWWDT_T *) EWWDT_BASE)                    /*!< Extra Window Watch Dog Timer Pointer*/
+
+#define FVC_S                 ((FVC_T *) FVC_BASE)
+#define DPM_S                 ((DPM_T *) DPM_BASE)
+#define PLM_S                 ((PLM_T *) PLM_BASE)
+
+
+
+/**@}*/ /* end of group PMODULE_S */
+
+/** @addtogroup PMODULE_NS Non-secure Peripheral Pointer
+ The Declaration of Non-secure Peripheral Pointer
+ @{
+*/
+
+
+#define PA_NS                  ((GPIO_T *)  (GPIOA_BASE+NS_OFFSET))                     /*!< GPIO PORTA Pointer                        */
+#define PB_NS                  ((GPIO_T *)  (GPIOB_BASE+NS_OFFSET))                     /*!< GPIO PORTB Pointer                        */
+#define PC_NS                  ((GPIO_T *)  (GPIOC_BASE+NS_OFFSET))                     /*!< GPIO PORTC Pointer                        */
+#define PD_NS                  ((GPIO_T *)  (GPIOD_BASE+NS_OFFSET))                     /*!< GPIO PORTD Pointer                        */
+#define PE_NS                  ((GPIO_T *)  (GPIOE_BASE+NS_OFFSET))                     /*!< GPIO PORTE Pointer                        */
+#define PF_NS                  ((GPIO_T *)  (GPIOF_BASE+NS_OFFSET))                     /*!< GPIO PORTF Pointer                        */
+#define PG_NS                  ((GPIO_T *)  (GPIOG_BASE+NS_OFFSET))                     /*!< GPIO PORTG Pointer                        */
+#define PH_NS                  ((GPIO_T *)  (GPIOH_BASE+NS_OFFSET))                     /*!< GPIO PORTH Pointer                        */
+#define UART0_NS               ((UART_T *)  (UART0_BASE+NS_OFFSET))                     /*!< UART0 Pointer                       */
+#define UART1_NS               ((UART_T *)  (UART1_BASE+NS_OFFSET))                     /*!< UART1 Pointer                       */
+#define UART2_NS               ((UART_T *)  (UART2_BASE+NS_OFFSET))                     /*!< UART2 Pointer                       */
+#define UART3_NS               ((UART_T *)  (UART3_BASE+NS_OFFSET))                     /*!< UART3 Pointer                       */
+#define UART4_NS               ((UART_T *)  (UART4_BASE+NS_OFFSET))                     /*!< UART4 Pointer                       */
+#define UART5_NS               ((UART_T *)  (UART5_BASE+NS_OFFSET))                     /*!< UART5 Pointer                       */
+#define TIMER2_NS              ((TIMER_T *) (TMR23_BASE+NS_OFFSET))                     /*!< TIMER2 Pointer                      */
+#define TIMER3_NS              ((TIMER_T *) (TMR23_BASE+NS_OFFSET+0x100UL))             /*!< TIMER3 Pointer                      */
+#define TIMER4_NS              ((TIMER_T *) (TMR45_BASE+NS_OFFSET))                     /*!< TIMER4 Pointer                      */
+#define TIMER5_NS              ((TIMER_T *) (TMR45_BASE+NS_OFFSET+0x100UL))             /*!< TIMER5 Pointer                      */
+#define QSPI0_NS               ((QSPI_T *)  (QSPI0_BASE+NS_OFFSET))                      /*!< QSPI0 Pointer                       */
+#define SPI0_NS                ((SPI_T *)   (SPI0_BASE+NS_OFFSET))                       /*!< SPI0 Pointer                        */
+#define SPI1_NS                ((SPI_T *)   (SPI1_BASE+NS_OFFSET))                       /*!< SPI1 Pointer                        */
+#define SPI2_NS                ((SPI_T *)   (SPI2_BASE+NS_OFFSET))                       /*!< SPI2 Pointer                        */
+#define SPI3_NS                ((SPI_T *)   (SPI3_BASE+NS_OFFSET))                       /*!< SPI3 Pointer                        */
+#define I2S0_NS                ((I2S_T *)   (I2S0_BASE+NS_OFFSET))                       /*!< I2S0 Pointer                        */
+#define I2C0_NS                ((I2C_T *)   (I2C0_BASE+NS_OFFSET))                       /*!< I2C0 Pointer                        */
+#define I2C1_NS                ((I2C_T *)   (I2C1_BASE+NS_OFFSET))                       /*!< I2C1 Pointer                        */
+#define I2C2_NS                ((I2C_T *)   (I2C2_BASE+NS_OFFSET))                       /*!< I2C1 Pointer                        */
+#define QEI0_NS                ((QEI_T *)   (QEI0_BASE+NS_OFFSET))                       /*!< QEI0 Pointer                        */
+#define QEI1_NS                ((QEI_T *)   (QEI1_BASE+NS_OFFSET))                       /*!< QEI1 Pointer                        */
+#define ACMP01_NS              ((ACMP_T *)  (ACMP01_BASE+NS_OFFSET))                    /*!< ACMP01 Pointer                      */
+#define DAC0_NS                ((DAC_T *)   (DAC0_BASE+NS_OFFSET))                       /*!< DAC0 Pointer                        */
+#define DAC1_NS                ((DAC_T *)   (DAC1_BASE+NS_OFFSET))                       /*!< DAC1 Pointer                        */
+#define EADC_NS                ((EADC_T *)  (EADC_BASE+NS_OFFSET))                      /*!< EADC Pointer                        */
+#define SDH0_NS                ((SDH_T *)  (SDH0_BASE +NS_OFFSET))
+#define CRPT_NS                ((CRPT_T *) (CRPT_BASE +NS_OFFSET))
+#define TRNG_NS                ((TRNG_T *) (TRNG_BASE +NS_OFFSET))                     /*!< Random Number Generator Pointer    */
+#define BPWM0_NS               ((BPWM_T *) (BPWM0_BASE+NS_OFFSET))                     /*!< BPWM0 Pointer                       */
+#define BPWM1_NS               ((BPWM_T *) (BPWM1_BASE+NS_OFFSET))                     /*!< BPWM1 Pointer                       */
+#define EPWM0_NS               ((EPWM_T *) (EPWM0_BASE+NS_OFFSET))                     /*!< EPWM0 Pointer                       */
+#define EPWM1_NS               ((EPWM_T *) (EPWM1_BASE+NS_OFFSET))                     /*!< EPWM1 Pointer                       */
+#define SC0_NS                 ((SC_T *)   (SC0_BASE  +NS_OFFSET))                     /*!< SC0 Pointer                         */
+#define SC1_NS                 ((SC_T *)   (SC1_BASE  +NS_OFFSET))                     /*!< SC1 Pointer                         */
+#define SC2_NS                 ((SC_T *)   (SC2_BASE  +NS_OFFSET))                     /*!< SC2 Pointer                         */
+#define EBI_NS                 ((EBI_T *)  (EBI_BASE  +NS_OFFSET))                     /*!< EBI Pointer                         */
+#define CRC_NS                 ((CRC_T *)  (CRC_BASE  +NS_OFFSET))                     /*!< CRC Pointer                         */
+#define USBD_NS                ((USBD_T *) (USBD_BASE +NS_OFFSET))                     /*!< USB Device Pointer                  */
+#define USBH_NS                ((USBH_T *) (USBH_BASE +NS_OFFSET))                     /*!< USBH Pointer                        */
+#define OTG_NS                 ((OTG_T *)  (OTG_BASE  +NS_OFFSET))                     /*!< OTG Pointer                         */
+#define PDMA1_NS               ((PDMA_T *)   (PDMA1_BASE +NS_OFFSET))                     /*!< PDMA1 Pointer                        */
+#define UI2C0_NS                ((UI2C_T *)  (USCI0_BASE +NS_OFFSET))                     /*!< UI2C0 Pointer                       */
+#define UI2C1_NS                ((UI2C_T *)  (USCI1_BASE +NS_OFFSET))                     /*!< UI2C1 Pointer                       */
+#define USPI0_NS                ((USPI_T *)  (USCI0_BASE +NS_OFFSET))                     /*!< USPI0 Pointer                       */
+#define USPI1_NS                ((USPI_T *)  (USCI1_BASE +NS_OFFSET))                     /*!< USPI1 Pointer                       */
+#define UUART0_NS               ((UUART_T *) (USCI0_BASE+NS_OFFSET))                    /*!< UUART0 Pointer                      */
+#define UUART1_NS               ((UUART_T *) (USCI1_BASE+NS_OFFSET))                    /*!< UUART1 Pointer                      */
+#define SCU_NS                 ((SCU_T *)    (SCU_BASE  +NS_OFFSET))                        /*!< SCU Pointer                         */
+#define ECAP0_NS               ((ECAP_T *)   (ECAP0_BASE+NS_OFFSET))                     /*!< ECAP0 Pointer                       */
+#define ECAP1_NS               ((ECAP_T *)   (ECAP1_BASE+NS_OFFSET))                     /*!< ECAP1 Pointer                       */
+#define CAN0_NS                ((CAN_T *)    (CAN0_BASE +NS_OFFSET))                        /*!< CAN0 Pointer                        */
+
+#define EWDT_NS                ((EWDT_T *) (EWDT_BASE+NS_OFFSET))                     /*!< Extra Watch Dog Timer Pointer       */
+
+#define EWWDT_NS               ((EWWDT_T *) (EWWDT_BASE+NS_OFFSET))                   /*!< Extra Window Watch Dog Timer Pointer*/
+
+
+#define LCD_NS                 ((LCD_T *)(LCD_BASE+NS_OFFSET))                        /*!< LCD Pointer                         */
+#define DPM_NS                 ((DPM_T *)(DPM_BASE+NS_OFFSET))
+#define FMC_NS                 ((FMC_T *)(FMC_BASE+NS_OFFSET))                        /*!< Flash Memory Controller */
+#define SYS_NS                 ((SYS_T *)(SYS_BASE+NS_OFFSET))
+#define CLK_NS                 ((CLK_T *)(CLK_BASE+NS_OFFSET))
+
+
+/**@}*/ /* end of group PMODULE_NS */
+
+/** @addtogroup PMODULE_SNS Peripheral Pointer
+ The Declaration of Peripheral Pointer
+ @{
+*/
+
+/* Always Secure Modules */
+#define SYS SYS_S
+#define SYSINT SYSINT_S
+#define CLK CLK_S
+#define FMC FMC_S
+#define SCU SCU_S
+#define FVC FVC_S
+#define PLM PLM_S
+#define DPM DPM_S
+#define PDMA0 PDMA0_S
+#define WDT WDT_S
+#define WWDT WWDT_S
+#define TIMER0  TIMER0_S
+#define TIMER1  TIMER1_S
+#define RTC RTC_S
+#define KS KS_S
+#define TAMPER TAMPER_S
+
+#if defined (SCU_INIT_PNSSET0_VAL) && (SCU_INIT_PNSSET0_VAL & BIT9 )
+# define USBH USBH_NS
+#else
+# define USBH USBH_S
+#endif
+
+#if defined (SCU_INIT_PNSSET0_VAL) && (SCU_INIT_PNSSET0_VAL & BIT13)
+# define SDH0 SDH0_NS
+#else
+# define SDH0 SDH0_S
+#endif
+
+#if defined (SCU_INIT_PNSSET0_VAL) && (SCU_INIT_PNSSET0_VAL & BIT16)
+# define EBI EBI_NS
+#else
+# define EBI EBI_S
+#endif
+
+
+#if defined (SCU_INIT_PNSSET0_VAL) && (SCU_INIT_PNSSET0_VAL & BIT24)
+# define PDMA1 PDMA1_NS
+#else
+# define PDMA1 PDMA1_S
+#endif
+
+#if defined (SCU_INIT_PNSSET1_VAL) && (SCU_INIT_PNSSET1_VAL & BIT17)
+# define CRC CRC_NS
+#else
+# define CRC CRC_S
+#endif
+
+#if defined (SCU_INIT_PNSSET1_VAL) && (SCU_INIT_PNSSET1_VAL & BIT18)
+# define CRPT CRPT_NS
+#else
+# define CRPT CRPT_S
+#endif
+
+#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT2 )
+# define EWDT EWDT_NS
+# define EWWDT EWWDT_NS
+#else
+# define EWDT EWDT_S
+# define EWWDT EWWDT_S
+#endif
+
+#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT3 )
+# define EADC EADC_NS
+#else
+# define EADC EADC_S
+#endif
+
+#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT3 )
+# define EADC EADC_NS
+#else
+# define EADC EADC_S
+#endif
+
+#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT3 )
+# define EADC EADC_NS
+#else
+# define EADC EADC_S
+#endif
+
+#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT3 )
+# define EADC EADC_NS
+#else
+# define EADC EADC_S
+#endif
+
+#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT5 )
+# define ACMP01 ACMP01_NS
+#else
+# define ACMP01 ACMP01_S
+#endif
+
+#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT7 )
+# define DAC0 DAC0_NS
+# define DAC1 DAC1_NS
+#else
+# define DAC0 DAC0_S
+# define DAC1 DAC1_S
+#endif
+
+#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT8 )
+# define I2S0 I2S0_NS
+#else
+# define I2S0 I2S0_S
+#endif
+
+#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT13)
+# define OTG OTG_NS
+#else
+# define OTG OTG_S
+#endif
+
+#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT17)
+# define TIMER2 TIMER2_NS
+# define TIMER3 TIMER3_NS
+#else
+# define TIMER2 TIMER2_S
+# define TIMER3 TIMER3_S
+#endif
+
+#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT18)
+# define TIMER4 TIMER4_NS
+# define TIMER5 TIMER5_NS
+#else
+# define TIMER4 TIMER4_S
+# define TIMER5 TIMER5_S
+#endif
+
+#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT24)
+# define EPWM0 EPWM0_NS
+#else
+# define EPWM0 EPWM0_S
+#endif
+
+#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT24)
+# define EPWM0 EPWM0_NS
+#else
+# define EPWM0 EPWM0_S
+#endif
+
+#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT24)
+# define EPWM0 EPWM0_NS
+#else
+# define EPWM0 EPWM0_S
+#endif
+
+#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT25)
+# define EPWM1 EPWM1_NS
+#else
+# define EPWM1 EPWM1_S
+#endif
+
+#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT25)
+# define EPWM1 EPWM1_NS
+#else
+# define EPWM1 EPWM1_S
+#endif
+
+#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT25)
+# define EPWM1 EPWM1_NS
+#else
+# define EPWM1 EPWM1_S
+#endif
+
+#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT26)
+# define BPWM0 BPWM0_NS
+#else
+# define BPWM0 BPWM0_S
+#endif
+
+#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT27)
+# define BPWM1 BPWM1_NS
+#else
+# define BPWM1 BPWM1_S
+#endif
+
+#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT0 )
+# define QSPI0 QSPI0_NS
+#else
+# define QSPI0 QSPI0_S
+#endif
+
+#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT1 )
+# define SPI0 SPI0_NS
+#else
+# define SPI0 SPI0_S
+#endif
+
+#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT2 )
+# define SPI1 SPI1_NS
+#else
+# define SPI1 SPI1_S
+#endif
+
+#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT3 )
+# define SPI2 SPI2_NS
+#else
+# define SPI2 SPI2_S
+#endif
+
+#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT4 )
+# define SPI3 SPI3_NS
+#else
+# define SPI3 SPI3_S
+#endif
+
+#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT16)
+# define UART0 UART0_NS
+#else
+# define UART0 UART0_S
+#endif
+
+#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT17)
+# define UART1 UART1_NS
+#else
+# define UART1 UART1_S
+#endif
+
+#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT18)
+# define UART2 UART2_NS
+#else
+# define UART2 UART2_S
+#endif
+
+#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT19)
+# define UART3 UART3_NS
+#else
+# define UART3 UART3_S
+#endif
+
+#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT20)
+# define UART4 UART4_NS
+#else
+# define UART4 UART4_S
+#endif
+
+#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT21)
+# define UART5 UART5_NS
+#else
+# define UART5 UART5_S
+#endif
+
+#if defined (SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & BIT0 )
+# define I2C0 I2C0_NS
+#else
+# define I2C0 I2C0_S
+#endif
+
+#if defined (SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & BIT1 )
+# define I2C1 I2C1_NS
+#else
+# define I2C1 I2C1_S
+#endif
+
+#if defined (SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & BIT2 )
+# define I2C2 I2C2_NS
+#else
+# define I2C2 I2C2_S
+#endif
+
+#if defined (SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & BIT16)
+# define SC0 SC0_NS
+#else
+# define SC0 SC0_S
+#endif
+
+#if defined (SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & BIT17)
+# define SC1 SC1_NS
+#else
+# define SC1 SC1_S
+#endif
+
+#if defined (SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & BIT18)
+# define SC2 SC2_NS
+#else
+# define SC2 SC2_S
+#endif
+
+#if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT0 )
+# define CAN0 CAN0_NS
+#else
+# define CAN0 CAN0_S
+#endif
+
+#if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT16)
+# define QEI0 QEI0_NS
+#else
+# define QEI0 QEI0_S
+#endif
+
+#if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT17)
+# define QEI1 QEI1_NS
+#else
+# define QEI1 QEI1_S
+#endif
+
+#if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT20)
+# define ECAP0 ECAP0_NS
+#else
+# define ECAP0 ECAP0_S
+#endif
+
+#if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT21)
+# define ECAP1 ECAP1_NS
+#else
+# define ECAP1 ECAP1_S
+#endif
+
+#if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT25)
+# define TRNG TRNG_NS
+#else
+# define TRNG TRNG_S
+#endif
+
+#if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT27)
+# define LCD LCD_NS
+#else
+# define LCD LCD_S
+#endif
+
+#if defined (SCU_INIT_PNSSET6_VAL) && (SCU_INIT_PNSSET6_VAL & BIT0 )
+# define USBD USBD_NS
+#else
+# define USBD USBD_S
+#endif
+
+#if defined (SCU_INIT_PNSSET6_VAL) && (SCU_INIT_PNSSET6_VAL & BIT16)
+# define USCI0 USCI0_NS
+# define UI2C0 UI2C0_NS
+# define USPI0 USPI0_NS
+# define UUART0 UUART0_NS
+
+#else
+# define USCI0 USCI0_S
+# define UI2C0 UI2C0_S
+# define USPI0 USPI0_S
+# define UUART0 UUART0_S
+
+#endif
+
+#if defined (SCU_INIT_PNSSET6_VAL) && (SCU_INIT_PNSSET6_VAL & BIT17)
+# define USCI1 USCI1_NS
+# define USPI1 USPI1_NS
+# define UI2C1 UI2C1_NS
+# define UUART1 UUART1_NS
+
+#else
+# define USCI1 USCI1_S
+# define USPI1 USPI1_S
+# define UI2C1 UI2C1_S
+# define UUART1 UUART1_S
+#endif
+
+#define PA  ( (__PC() & NS_OFFSET) ? PA_NS : PA_S)
+#define PB  ( (__PC() & NS_OFFSET) ? PB_NS : PB_S)
+#define PC  ( (__PC() & NS_OFFSET) ? PC_NS : PC_S)
+#define PD  ( (__PC() & NS_OFFSET) ? PD_NS : PD_S)
+#define PE  ( (__PC() & NS_OFFSET) ? PE_NS : PE_S)
+#define PF  ( (__PC() & NS_OFFSET) ? PF_NS : PF_S)
+#define PG  ( (__PC() & NS_OFFSET) ? PG_NS : PG_S)
+#define PH  ( (__PC() & NS_OFFSET) ? PH_NS : PH_S)
+
+/**@}*/ /* end of group PMODULE_SNS */
+
+/**@}*/ /* end of group PMODULE */
+
+/* --------------------  End of section using anonymous unions  ------------------- */
+#if   defined (__CC_ARM)
+#pragma pop
+#elif defined (__ICCARM__)
+/* leave anonymous unions enabled */
+#elif (__ARMCC_VERSION >= 6010050)
+#pragma clang diagnostic pop
+#elif defined (__GNUC__)
+/* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+/* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+#pragma warning restore
+#elif defined (__CSMC__)
+/* anonymous unions are enabled by default */
+#else
+#warning Not supported compiler type
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+/******************************************************************************/
+/*                         Peripheral header files                            */
+/******************************************************************************/
+#include "nu_sys.h"
+#include "nu_clk.h"
+#include "nu_dac.h"
+#include "nu_eadc.h"
+#include "nu_ebi.h"
+#include "nu_ecap.h"
+#include "nu_fmc.h"
+#include "nu_gpio.h"
+#include "nu_i2c.h"
+#include "nu_i2s.h"
+#include "nu_bpwm.h"
+#include "nu_epwm.h"
+#include "nu_qspi.h"
+#include "nu_spi.h"
+#include "nu_timer.h"
+#include "nu_timer_pwm.h"
+#include "nu_wdt.h"
+#include "nu_wwdt.h"
+#include "nu_rtc.h"
+#include "nu_uart.h"
+#include "nu_acmp.h"
+#include "nu_crc.h"
+#include "nu_usbd.h"
+#include "nu_otg.h"
+#include "nu_pdma.h"
+#include "nu_ebi.h"
+#include "nu_keystore.h"
+#include "nu_crypto.h"
+#include "nu_sc.h"
+#include "nu_scuart.h"
+#include "nu_usci_spi.h"
+#include "nu_usci_uart.h"
+#include "nu_usci_i2c.h"
+#include "nu_sdh.h"
+#include "nu_qei.h"
+#include "nu_can.h"
+#include "nu_scu.h"
+#include "nu_tamper.h"
+#include "nu_rng.h"
+#include "nu_dpm.h"
+#include "nu_fvc.h"
+#include "nu_ewwdt.h"
+#include "nu_ewdt.h"
+#include "nu_plm.h"
+#include "nu_lcd.h"
+
+#endif  /* __M2354_H__ */
+
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/NuMicro.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/NuMicro.h
new file mode 100644
index 0000000000..cccccd4e7a
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/NuMicro.h
@@ -0,0 +1,17 @@
+/**************************************************************************//**
+ * @file     NuMicro.h
+ * @version  V1.00
+ * @brief    NuMicro peripheral access layer header file.
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NUMICRO_H__
+#define __NUMICRO_H__
+
+#include "nutool_clkcfg.h"
+#include "M2354.h"
+
+#endif  /* __NUMICRO_H__ */
+
+
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/acmp_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/acmp_reg.h
new file mode 100644
index 0000000000..5d110acfa1
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/acmp_reg.h
@@ -0,0 +1,244 @@
+/**************************************************************************//**
+ * @file     acmp_reg.h
+ * @version  V1.00
+ * @brief    ACMP register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __ACMP_REG_H__
+#define __ACMP_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+
+/*---------------------- Analog Comparator Controller -------------------------*/
+/**
+    @addtogroup ACMP Analog Comparator Controller(ACMP)
+    Memory Mapped Structure for ACMP Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var ACMP_T::CTL
+     * Offset: 0x00  Analog Comparator 0 Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ACMPEN    |Comparator Enable Bit
+     * |        |          |0 = Comparator 0 Disabled.
+     * |        |          |1 = Comparator 0 Enabled.
+     * |[1]     |ACMPIE    |Comparator Interrupt Enable Bit
+     * |        |          |0 = Comparator 0 interrupt Disabled.
+     * |        |          |1 = Comparator 0 interrupt Enabled.
+     * |        |          |If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well.
+     * |[2]     |HYSEN     |Comparator Hysteresis Enable Bit
+     * |        |          |0 = Comparator 0 hysteresis Disabled.
+     * |        |          |1 = Comparator 0 hysteresis Enabled.
+     * |        |          |Note: If HYSEN = 0, user can adjust HYS by HYSSEL.
+     * |        |          |Note: If HYSEN = 1, HYSSEL is invalid. The Hysteresis is fixed to 30mV.
+     * |[3]     |ACMPOINV  |Comparator Output Inverse
+     * |        |          |0 = Comparator 0 output inverse Disabled.
+     * |        |          |1 = Comparator 0 output inverse Enabled.
+     * |[5:4]   |NEGSEL    |Comparator Negative Input Selection
+     * |        |          |00 = ACMP0_N pin.
+     * |        |          |01 = Internal comparator reference voltage (CRV).
+     * |        |          |10 = Band-gap voltage.
+     * |        |          |11 = DAC output.
+     * |[7:6]   |POSSEL    |Comparator Positive Input Selection
+     * |        |          |00 = Input from ACMP0_P0.
+     * |        |          |01 = Input from ACMP0_P1.
+     * |        |          |10 = Input from ACMP0_P2.
+     * |        |          |11 = Input from ACMP0_P3.
+     * |[9:8]   |INTPOL    |Interrupt Condition Polarity Selection
+     * |        |          |ACMPIF0 will be set to 1 when comparator output edge condition is detected.
+     * |        |          |00 = Rising edge or falling edge.
+     * |        |          |01 = Rising edge.
+     * |        |          |10 = Falling edge.
+     * |        |          |11 = Reserved.
+     * |[12]    |OUTSEL    |Comparator Output Select
+     * |        |          |0 = Comparator 0 output to ACMP0_O pin is unfiltered comparator output.
+     * |        |          |1 = Comparator 0 output to ACMP0_O pin is from filter output.
+     * |[15:13] |FILTSEL   |Comparator Output Filter Count Selection
+     * |        |          |000 = Filter function is Disabled.
+     * |        |          |001 = ACMP0 output is sampled 1 consecutive PCLK.
+     * |        |          |010 = ACMP0 output is sampled 2 consecutive PCLKs.
+     * |        |          |011 = ACMP0 output is sampled 4 consecutive PCLKs.
+     * |        |          |100 = ACMP0 output is sampled 8 consecutive PCLKs.
+     * |        |          |101 = ACMP0 output is sampled 16 consecutive PCLKs.
+     * |        |          |110 = ACMP0 output is sampled 32 consecutive PCLKs.
+     * |        |          |111 = ACMP0 output is sampled 64 consecutive PCLKs.
+     * |[16]    |WKEN      |Power-down Wake-up Enable Bit
+     * |        |          |0 = Wake-up function Disabled.
+     * |        |          |1 = Wake-up function Enabled.
+     * |[17]    |WLATEN    |Window Latch Mode Enable Bit
+     * |        |          |0 = Window Latch Mode Disabled.
+     * |        |          |1 = Window Latch Mode Enabled.
+     * |[18]    |WCMPSEL   |Window Compare Mode Selection
+     * |        |          |0 = Window Compare Mode Disabled.
+     * |        |          |1 = Window Compare Mode is Selected.
+     * |[25:24] |HYSSEL    |Hysteresis Mode Selection
+     * |        |          |00 = Hysteresis is 0mV.
+     * |        |          |01 = Hysteresis is 10mV.
+     * |        |          |10 = Hysteresis is 20mV.
+     * |        |          |11 = Hysteresis is 30mV.
+     * |[29:28] |MODESEL   |Propagation Delay Mode Selection
+     * |        |          |00 = Max propagation delay is 4.5uS, operation current is 1.2uA.
+     * |        |          |01 = Max propagation delay is 2uS, operation current is 3uA.
+     * |        |          |10 = Max propagation delay is 600nS, operation current is 10uA.
+     * |        |          |11 = Max propagation delay is 200nS, operation current is 75uA.
+     * @var ACMP_T::STATUS
+     * Offset: 0x08  Analog Comparator Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ACMPIF0   |Comparator 0 Interrupt Flag
+     * |        |          |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output
+     * |        |          |This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[1]     |ACMPIF1   |Comparator 1 Interrupt Flag
+     * |        |          |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output
+     * |        |          |This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[4]     |ACMPO0    |Comparator 0 Output
+     * |        |          |Synchronized to the PCLK to allow reading by software
+     * |        |          |Cleared when the comparator 0 is disabled, i.e
+     * |        |          |ACMPEN (ACMP_CTL0[0]) is cleared to 0.
+     * |[5]     |ACMPO1    |Comparator 1 Output
+     * |        |          |Synchronized to the PCLK to allow reading by software
+     * |        |          |Cleared when the comparator 1 is disabled, i.e
+     * |        |          |ACMPEN (ACMP_CTL1[0]) is cleared to 0.
+     * |[8]     |WKIF0     |Comparator 0 Power-down Wake-up Interrupt Flag
+     * |        |          |This bit will be set to 1 when ACMP0 wake-up interrupt event occurs.
+     * |        |          |0 = No power-down wake-up occurred.
+     * |        |          |1 = Power-down wake-up occurred.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[9]     |WKIF1     |Comparator 1 Power-down Wake-up Interrupt Flag
+     * |        |          |This bit will be set to 1 when ACMP1 wake-up interrupt event occurs.
+     * |        |          |0 = No power-down wake-up occurred.
+     * |        |          |1 = Power-down wake-up occurred.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[12]    |ACMPS0    |Comparator 0 Status
+     * |        |          |Synchronized to the PCLK to allow reading by software
+     * |        |          |Cleared when the comparator 0 is disabled, i.e
+     * |        |          |ACMPEN (ACMP_CTL0[0]) is cleared to 0.
+     * |[13]    |ACMPS1    |Comparator 1 Status
+     * |        |          |Synchronized to the PCLK to allow reading by software
+     * |        |          |Cleared when the comparator 1 is disabled, i.e
+     * |        |          |ACMPEN (ACMP_CTL1[0]) is cleared to 0.
+     * |[16]    |ACMPWO    |Comparator Window Output
+     * |        |          |This bit shows the output status of window compare mode
+     * |        |          |0 = The positive input voltage is outside the window.
+     * |        |          |1 = The positive input voltage is in the window.
+     * @var ACMP_T::VREF
+     * Offset: 0x0C  Analog Comparator Reference Voltage Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |CRVCTL    |Comparator Reference Voltage Setting
+     * |        |          |CRV = CRV source voltage * (1/6+CRVCTL/24).
+     * |[6]     |CRVSSEL   |CRV Source Voltage Selection
+     * |        |          |0 = VDDA is selected as CRV source voltage.
+     * |        |          |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage.
+     */
+
+    __IO uint32_t CTL[2];                /*!< [0x0000~0x0004] Analog Comparator 0~1 Control Register                    */
+    __IO uint32_t STATUS;                /*!< [0x0008] Analog Comparator Status Register                                */
+    __IO uint32_t VREF;                  /*!< [0x000c] Analog Comparator Reference Voltage Control Register             */
+
+} ACMP_T;
+
+/**
+    @addtogroup ACMP_CONST ACMP Bit Field Definition
+    Constant Definitions for ACMP Controller
+  @{
+*/
+
+#define ACMP_CTL_ACMPEN_Pos             (0)                                               /*!< ACMP_T::CTL: ACMPEN Position          */
+#define ACMP_CTL_ACMPEN_Msk             (0x1ul << ACMP_CTL_ACMPEN_Pos)                    /*!< ACMP_T::CTL: ACMPEN Mask              */
+
+#define ACMP_CTL_ACMPIE_Pos             (1)                                               /*!< ACMP_T::CTL: ACMPIE Position          */
+#define ACMP_CTL_ACMPIE_Msk             (0x1ul << ACMP_CTL_ACMPIE_Pos)                    /*!< ACMP_T::CTL: ACMPIE Mask              */
+
+#define ACMP_CTL_HYSEN_Pos              (2)                                               /*!< ACMP_T::CTL: HYSEN Position           */
+#define ACMP_CTL_HYSEN_Msk              (0x1ul << ACMP_CTL_HYSEN_Pos)                     /*!< ACMP_T::CTL: HYSEN Mask               */
+
+#define ACMP_CTL_ACMPOINV_Pos           (3)                                               /*!< ACMP_T::CTL: ACMPOINV Position        */
+#define ACMP_CTL_ACMPOINV_Msk           (0x1ul << ACMP_CTL_ACMPOINV_Pos)                  /*!< ACMP_T::CTL: ACMPOINV Mask            */
+
+#define ACMP_CTL_NEGSEL_Pos             (4)                                               /*!< ACMP_T::CTL: NEGSEL Position          */
+#define ACMP_CTL_NEGSEL_Msk             (0x3ul << ACMP_CTL_NEGSEL_Pos)                    /*!< ACMP_T::CTL: NEGSEL Mask              */
+
+#define ACMP_CTL_POSSEL_Pos             (6)                                               /*!< ACMP_T::CTL: POSSEL Position          */
+#define ACMP_CTL_POSSEL_Msk             (0x3ul << ACMP_CTL_POSSEL_Pos)                    /*!< ACMP_T::CTL: POSSEL Mask              */
+
+#define ACMP_CTL_INTPOL_Pos             (8)                                               /*!< ACMP_T::CTL: INTPOL Position          */
+#define ACMP_CTL_INTPOL_Msk             (0x3ul << ACMP_CTL_INTPOL_Pos)                    /*!< ACMP_T::CTL: INTPOL Mask              */
+
+#define ACMP_CTL_OUTSEL_Pos             (12)                                              /*!< ACMP_T::CTL: OUTSEL Position          */
+#define ACMP_CTL_OUTSEL_Msk             (0x1ul << ACMP_CTL_OUTSEL_Pos)                    /*!< ACMP_T::CTL: OUTSEL Mask              */
+
+#define ACMP_CTL_FILTSEL_Pos            (13)                                              /*!< ACMP_T::CTL: FILTSEL Position         */
+#define ACMP_CTL_FILTSEL_Msk            (0x7ul << ACMP_CTL_FILTSEL_Pos)                   /*!< ACMP_T::CTL: FILTSEL Mask             */
+
+#define ACMP_CTL_WKEN_Pos               (16)                                              /*!< ACMP_T::CTL: WKEN Position            */
+#define ACMP_CTL_WKEN_Msk               (0x1ul << ACMP_CTL_WKEN_Pos)                      /*!< ACMP_T::CTL: WKEN Mask                */
+
+#define ACMP_CTL_WLATEN_Pos             (17)                                              /*!< ACMP_T::CTL: WLATEN Position          */
+#define ACMP_CTL_WLATEN_Msk             (0x1ul << ACMP_CTL_WLATEN_Pos)                    /*!< ACMP_T::CTL: WLATEN Mask              */
+
+#define ACMP_CTL_WCMPSEL_Pos            (18)                                              /*!< ACMP_T::CTL: WCMPSEL Position         */
+#define ACMP_CTL_WCMPSEL_Msk            (0x1ul << ACMP_CTL_WCMPSEL_Pos)                   /*!< ACMP_T::CTL: WCMPSEL Mask             */
+
+#define ACMP_CTL_HYSSEL_Pos             (24)                                              /*!< ACMP_T::CTL: HYSSEL Position          */
+#define ACMP_CTL_HYSSEL_Msk             (0x3ul << ACMP_CTL_HYSSEL_Pos)                    /*!< ACMP_T::CTL: HYSSEL Mask              */
+
+#define ACMP_CTL_MODESEL_Pos            (28)                                              /*!< ACMP_T::CTL: MODESEL Position         */
+#define ACMP_CTL_MODESEL_Msk            (0x3ul << ACMP_CTL_MODESEL_Pos)                   /*!< ACMP_T::CTL: MODESEL Mask             */
+
+#define ACMP_STATUS_ACMPIF0_Pos          (0)                                               /*!< ACMP_T::STATUS: ACMPIF0 Position       */
+#define ACMP_STATUS_ACMPIF0_Msk          (0x1ul << ACMP_STATUS_ACMPIF0_Pos)                /*!< ACMP_T::STATUS: ACMPIF0 Mask           */
+
+#define ACMP_STATUS_ACMPIF1_Pos          (1)                                               /*!< ACMP_T::STATUS: ACMPIF1 Position       */
+#define ACMP_STATUS_ACMPIF1_Msk          (0x1ul << ACMP_STATUS_ACMPIF1_Pos)                /*!< ACMP_T::STATUS: ACMPIF1 Mask           */
+
+#define ACMP_STATUS_ACMPO0_Pos           (4)                                               /*!< ACMP_T::STATUS: ACMPO0 Position        */
+#define ACMP_STATUS_ACMPO0_Msk           (0x1ul << ACMP_STATUS_ACMPO0_Pos)                 /*!< ACMP_T::STATUS: ACMPO0 Mask            */
+
+#define ACMP_STATUS_ACMPO1_Pos           (5)                                               /*!< ACMP_T::STATUS: ACMPO1 Position        */
+#define ACMP_STATUS_ACMPO1_Msk           (0x1ul << ACMP_STATUS_ACMPO1_Pos)                 /*!< ACMP_T::STATUS: ACMPO1 Mask            */
+
+#define ACMP_STATUS_WKIF0_Pos            (8)                                               /*!< ACMP_T::STATUS: WKIF0 Position         */
+#define ACMP_STATUS_WKIF0_Msk            (0x1ul << ACMP_STATUS_WKIF0_Pos)                  /*!< ACMP_T::STATUS: WKIF0 Mask             */
+
+#define ACMP_STATUS_WKIF1_Pos            (9)                                               /*!< ACMP_T::STATUS: WKIF1 Position         */
+#define ACMP_STATUS_WKIF1_Msk            (0x1ul << ACMP_STATUS_WKIF1_Pos)                  /*!< ACMP_T::STATUS: WKIF1 Mask             */
+
+#define ACMP_STATUS_ACMPS0_Pos           (12)                                              /*!< ACMP_T::STATUS: ACMPS0 Position        */
+#define ACMP_STATUS_ACMPS0_Msk           (0x1ul << ACMP_STATUS_ACMPS0_Pos)                 /*!< ACMP_T::STATUS: ACMPS0 Mask            */
+
+#define ACMP_STATUS_ACMPS1_Pos           (13)                                              /*!< ACMP_T::STATUS: ACMPS1 Position        */
+#define ACMP_STATUS_ACMPS1_Msk           (0x1ul << ACMP_STATUS_ACMPS1_Pos)                 /*!< ACMP_T::STATUS: ACMPS1 Mask            */
+
+#define ACMP_STATUS_ACMPWO_Pos           (16)                                              /*!< ACMP_T::STATUS: ACMPWO Position        */
+#define ACMP_STATUS_ACMPWO_Msk           (0x1ul << ACMP_STATUS_ACMPWO_Pos)                 /*!< ACMP_T::STATUS: ACMPWO Mask            */
+
+#define ACMP_VREF_CRVCTL_Pos             (0)                                               /*!< ACMP_T::VREF: CRVCTL Position          */
+#define ACMP_VREF_CRVCTL_Msk             (0xful << ACMP_VREF_CRVCTL_Pos)                   /*!< ACMP_T::VREF: CRVCTL Mask              */
+
+#define ACMP_VREF_CRVSSEL_Pos            (6)                                               /*!< ACMP_T::VREF: CRVSSEL Position         */
+#define ACMP_VREF_CRVSSEL_Msk            (0x1ul << ACMP_VREF_CRVSSEL_Pos)                  /*!< ACMP_T::VREF: CRVSSEL Mask             */
+
+/**@}*/ /* ACMP_CONST */
+/**@}*/ /* end of ACMP register group */
+/**@}*/ /* end of REGISTER group */
+
+#endif /* __ACMP_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/bpwm_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/bpwm_reg.h
new file mode 100644
index 0000000000..14455bf7f1
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/bpwm_reg.h
@@ -0,0 +1,1800 @@
+/**************************************************************************//**
+ * @file     bpwm_reg.h
+ * @version  V1.00
+ * @brief    BPWM register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __BPWM_REG_H__
+#define __BPWM_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+
+/*---------------------- Basic Pulse Width Modulation Controller -------------------------*/
+/**
+    @addtogroup BPWM Basic Pulse Width Modulation Controller(BPWM)
+    Memory Mapped Structure for BPWM Controller
+  @{
+*/
+
+typedef struct
+{
+    /**
+     * @var BCAPDAT_T::RCAPDAT
+     * Offset: 0x20C  BPWM Rising Capture Data Register 0~5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |RCAPDAT   |BPWM Rising Capture Data (Read Only)
+     * |        |          |When rising capture condition happened, the BPWM counter value will be saved in this register.
+     * @var BCAPDAT_T::FCAPDAT
+     * Offset: 0x210  BPWM Falling Capture Data Register 0~5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |FCAPDAT   |BPWM Falling Capture Data (Read Only)
+     * |        |          |When falling capture condition happened, the BPWM counter value will be saved in this register.
+     */
+    __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] BPWM Rising Capture Data Register 0~5 */
+    __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] BPWM Falling Capture Data Register 0~5 */
+} BCAPDAT_T;
+
+
+typedef struct
+{
+    /**
+     * @var BPWM_T::CTL0
+     * Offset: 0x00  BPWM Control Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CTRLD0    |Center Re-load
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the center point of a period
+     * |[1]     |CTRLD1    |Center Re-load
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the center point of a period
+     * |[2]     |CTRLD2    |Center Re-load
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the center point of a period
+     * |[3]     |CTRLD3    |Center Re-load
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the center point of a period
+     * |[4]     |CTRLD4    |Center Re-load
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the center point of a period
+     * |[5]     |CTRLD5    |Center Re-load
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |In up-down counter type, PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the center point of a period
+     * |[16]    |IMMLDEN0  |Immediately Load Enable Bit(S)
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+     * |        |          |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+     * |        |          |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
+     * |[17]    |IMMLDEN1  |Immediately Load Enable Bit(S)
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+     * |        |          |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+     * |        |          |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
+     * |[18]    |IMMLDEN2  |Immediately Load Enable Bit(S)
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+     * |        |          |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+     * |        |          |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
+     * |[19]    |IMMLDEN3  |Immediately Load Enable Bit(S)
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+     * |        |          |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+     * |        |          |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
+     * |[20]    |IMMLDEN4  |Immediately Load Enable Bit(S)
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+     * |        |          |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+     * |        |          |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
+     * |[21]    |IMMLDEN5  |Immediately Load Enable Bit(S)
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = PERIOD will load to PBUF at the end point of each period
+     * |        |          |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
+     * |        |          |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
+     * |        |          |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
+     * |[30]    |DBGHALT   |ICE Debug Mode Counter Halt (Write Protect)
+     * |        |          |If counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode.
+     * |        |          |0 = ICE debug mode counter halt Disable.
+     * |        |          |1 = ICE debug mode counter halt Enable.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[31]    |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect)
+     * |        |          |0 = ICE debug mode acknowledgement effects BPWM output.
+     * |        |          |BPWM pin will be forced as tri-state while ICE debug mode acknowledged.
+     * |        |          |1 = ICE debug mode acknowledgement Disabled.
+     * |        |          |BPWM pin will keep output no matter ICE debug mode acknowledged or not.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * @var BPWM_T::CTL1
+     * Offset: 0x04  BPWM Control Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |CNTTYPE0  |BPWM Counter Behavior Type 0
+     * |        |          |Each bit n controls corresponding BPWM channel n.
+     * |        |          |00 = Up counter type (supports in capture mode).
+     * |        |          |01 = Down count type (supports in capture mode).
+     * |        |          |10 = Up-down counter type.
+     * |        |          |11 = Reserved.
+     * @var BPWM_T::CLKSRC
+     * Offset: 0x10  BPWM Clock Source Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |ECLKSRC0  |BPWM_CH01 External Clock Source Select
+     * |        |          |000 = BPWMx_CLK, x denotes 0 or 1.
+     * |        |          |001 = TIMER0 overflow.
+     * |        |          |010 = TIMER1 overflow.
+     * |        |          |011 = TIMER2 overflow.
+     * |        |          |100 = TIMER3 overflow.
+     * |        |          |Others = Reserved.
+     * @var BPWM_T::CLKPSC
+     * Offset: 0x14  BPWM Clock Prescale Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[11:0]  |CLKPSC    |BPWM Counter Clock Prescale
+     * |        |          |The clock of BPWM counter is decided by clock prescaler
+     * |        |          |Each BPWM pair share one BPWM counter clock prescaler
+     * |        |          |The clock of BPWM counter is divided by (CLKPSC+ 1)
+     * @var BPWM_T::CNTEN
+     * Offset: 0x20  BPWM Counter Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CNTEN0    |BPWM Counter 0 Enable Bit
+     * |        |          |0 = BPWM Counter and clock prescaler stop running.
+     * |        |          |1 = BPWM Counter and clock prescaler start running.
+     * @var BPWM_T::CNTCLR
+     * Offset: 0x24  BPWM Clear Counter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CNTCLR0   |Clear BPWM Counter Control Bit 0
+     * |        |          |It is automatically cleared by hardware.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear 16-bit BPWM counter to 0000H.
+     * @var BPWM_T::PERIOD
+     * Offset: 0x30  BPWM Period Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |PERIOD    |BPWM Period Register
+     * |        |          |Up-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0.
+     * |        |          |Down-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD.
+     * |        |          |BPWM period time = (PERIOD+1) * BPWM_CLK period.
+     * |        |          |Up-Down-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.
+     * |        |          |BPWM period time = 2 * PERIOD * BPWM_CLK period.
+     * @var BPWM_T::CMPDAT[6]
+     * Offset: 0x50  BPWM Comparator Register 0~5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |CMPDAT    |BPWM Comparator Register
+     * |        |          |CMPDAT use to compare with CNTR to generate BPWM waveform, interrupt and trigger EADC.
+     * |        |          |In independent mode, CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point.
+     * @var BPWM_T::CNT
+     * Offset: 0x90  BPWM Counter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |CNT       |BPWM Data Register (Read Only)
+     * |        |          |User can monitor CNTR to know the current value in 16-bit period counter.
+     * |[16]    |DIRF      |BPWM Direction Indicator Flag (Read Only)
+     * |        |          |0 = Counter is Down count.
+     * |        |          |1 = Counter is UP count.
+     * @var BPWM_T::WGCTL0
+     * Offset: 0xB0  BPWM Generation Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |ZPCTL0    |BPWM Zero Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM zero point output Low.
+     * |        |          |10 = BPWM zero point output High.
+     * |        |          |11 = BPWM zero point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to zero.
+     * |[3:2]   |ZPCTL1    |BPWM Zero Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM zero point output Low.
+     * |        |          |10 = BPWM zero point output High.
+     * |        |          |11 = BPWM zero point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to zero.
+     * |[5:4]   |ZPCTL2    |BPWM Zero Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM zero point output Low.
+     * |        |          |10 = BPWM zero point output High.
+     * |        |          |11 = BPWM zero point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to zero.
+     * |[7:6]   |ZPCTL3    |BPWM Zero Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM zero point output Low.
+     * |        |          |10 = BPWM zero point output High.
+     * |        |          |11 = BPWM zero point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to zero.
+     * |[9:8]   |ZPCTL4    |BPWM Zero Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM zero point output Low.
+     * |        |          |10 = BPWM zero point output High.
+     * |        |          |11 = BPWM zero point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to zero.
+     * |[11:10] |ZPCTL5    |BPWM Zero Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM zero point output Low.
+     * |        |          |10 = BPWM zero point output High.
+     * |        |          |11 = BPWM zero point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to zero.
+     * |[17:16] |PRDPCTL0  |BPWM Period (Center) Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM period (center) point output Low.
+     * |        |          |10 = BPWM period (center) point output High.
+     * |        |          |11 = BPWM period (center) point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to (PERIOD+1).
+     * |        |          |Note: This bit is center point control when BPWM counter operating in up-down counter type.
+     * |[19:18] |PRDPCTL1  |BPWM Period (Center) Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM period (center) point output Low.
+     * |        |          |10 = BPWM period (center) point output High.
+     * |        |          |11 = BPWM period (center) point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to (PERIOD+1).
+     * |        |          |Note: This bit is center point control when BPWM counter operating in up-down counter type.
+     * |[21:20] |PRDPCTL2  |BPWM Period (Center) Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM period (center) point output Low.
+     * |        |          |10 = BPWM period (center) point output High.
+     * |        |          |11 = BPWM period (center) point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to (PERIOD+1).
+     * |        |          |Note: This bit is center point control when BPWM counter operating in up-down counter type.
+     * |[23:22] |PRDPCTL3  |BPWM Period (Center) Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM period (center) point output Low.
+     * |        |          |10 = BPWM period (center) point output High.
+     * |        |          |11 = BPWM period (center) point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to (PERIOD+1).
+     * |        |          |Note: This bit is center point control when BPWM counter operating in up-down counter type.
+     * |[25:24] |PRDPCTL4  |BPWM Period (Center) Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM period (center) point output Low.
+     * |        |          |10 = BPWM period (center) point output High.
+     * |        |          |11 = BPWM period (center) point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to (PERIOD+1).
+     * |        |          |Note: This bit is center point control when BPWM counter operating in up-down counter type.
+     * |[27:26] |PRDPCTL5  |BPWM Period (Center) Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM period (center) point output Low.
+     * |        |          |10 = BPWM period (center) point output High.
+     * |        |          |11 = BPWM period (center) point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter count to (PERIOD+1).
+     * |        |          |Note: This bit is center point control when BPWM counter operating in up-down counter type.
+     * @var BPWM_T::WGCTL1
+     * Offset: 0xB4  BPWM Generation Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |CMPUCTL0  |BPWM Compare Up Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare up point output Low.
+     * |        |          |10 = BPWM compare up point output High.
+     * |        |          |11 = BPWM compare up point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter up count to CMPDAT.
+     * |[3:2]   |CMPUCTL1  |BPWM Compare Up Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare up point output Low.
+     * |        |          |10 = BPWM compare up point output High.
+     * |        |          |11 = BPWM compare up point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter up count to CMPDAT.
+     * |[5:4]   |CMPUCTL2  |BPWM Compare Up Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare up point output Low.
+     * |        |          |10 = BPWM compare up point output High.
+     * |        |          |11 = BPWM compare up point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter up count to CMPDAT.
+     * |[7:6]   |CMPUCTL3  |BPWM Compare Up Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare up point output Low.
+     * |        |          |10 = BPWM compare up point output High.
+     * |        |          |11 = BPWM compare up point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter up count to CMPDAT.
+     * |[9:8]   |CMPUCTL4  |BPWM Compare Up Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare up point output Low.
+     * |        |          |10 = BPWM compare up point output High.
+     * |        |          |11 = BPWM compare up point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter up count to CMPDAT.
+     * |[11:10] |CMPUCTL5  |BPWM Compare Up Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare up point output Low.
+     * |        |          |10 = BPWM compare up point output High.
+     * |        |          |11 = BPWM compare up point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter up count to CMPDAT.
+     * |[17:16] |CMPDCTL0  |BPWM Compare Down Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare down point output Low.
+     * |        |          |10 = BPWM compare down point output High.
+     * |        |          |11 = BPWM compare down point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter down count to CMPDAT.
+     * |[19:18] |CMPDCTL1  |BPWM Compare Down Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare down point output Low.
+     * |        |          |10 = BPWM compare down point output High.
+     * |        |          |11 = BPWM compare down point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter down count to CMPDAT.
+     * |[21:20] |CMPDCTL2  |BPWM Compare Down Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare down point output Low.
+     * |        |          |10 = BPWM compare down point output High.
+     * |        |          |11 = BPWM compare down point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter down count to CMPDAT.
+     * |[23:22] |CMPDCTL3  |BPWM Compare Down Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare down point output Low.
+     * |        |          |10 = BPWM compare down point output High.
+     * |        |          |11 = BPWM compare down point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter down count to CMPDAT.
+     * |[25:24] |CMPDCTL4  |BPWM Compare Down Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare down point output Low.
+     * |        |          |10 = BPWM compare down point output High.
+     * |        |          |11 = BPWM compare down point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter down count to CMPDAT.
+     * |[27:26] |CMPDCTL5  |BPWM Compare Down Point Control
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = BPWM compare down point output Low.
+     * |        |          |10 = BPWM compare down point output High.
+     * |        |          |11 = BPWM compare down point output Toggle.
+     * |        |          |BPWM can control output level when BPWM counter down count to CMPDAT.
+     * @var BPWM_T::MSKEN
+     * Offset: 0xB8  BPWM Mask Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |MSKEN0    |BPWM Mask Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |The BPWM output signal will be masked when this bit is enabled
+     * |        |          |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
+     * |        |          |0 = BPWM output signal is non-masked.
+     * |        |          |1 = BPWM output signal is masked and output MSKDATn data.
+     * |[1]     |MSKEN1    |BPWM Mask Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |The BPWM output signal will be masked when this bit is enabled
+     * |        |          |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
+     * |        |          |0 = BPWM output signal is non-masked.
+     * |        |          |1 = BPWM output signal is masked and output MSKDATn data.
+     * |[2]     |MSKEN2    |BPWM Mask Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |The BPWM output signal will be masked when this bit is enabled
+     * |        |          |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
+     * |        |          |0 = BPWM output signal is non-masked.
+     * |        |          |1 = BPWM output signal is masked and output MSKDATn data.
+     * |[3]     |MSKEN3    |BPWM Mask Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |The BPWM output signal will be masked when this bit is enabled
+     * |        |          |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
+     * |        |          |0 = BPWM output signal is non-masked.
+     * |        |          |1 = BPWM output signal is masked and output MSKDATn data.
+     * |[4]     |MSKEN4    |BPWM Mask Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |The BPWM output signal will be masked when this bit is enabled
+     * |        |          |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
+     * |        |          |0 = BPWM output signal is non-masked.
+     * |        |          |1 = BPWM output signal is masked and output MSKDATn data.
+     * |[5]     |MSKEN5    |BPWM Mask Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |The BPWM output signal will be masked when this bit is enabled
+     * |        |          |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
+     * |        |          |0 = BPWM output signal is non-masked.
+     * |        |          |1 = BPWM output signal is masked and output MSKDATn data.
+     * @var BPWM_T::MSK
+     * Offset: 0xBC  BPWM Mask Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |MSKDAT0   |BPWM Mask Data Bit
+     * |        |          |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Output logic low to BPWMn.
+     * |        |          |1 = Output logic high to BPWMn.
+     * |[1]     |MSKDAT1   |BPWM Mask Data Bit
+     * |        |          |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Output logic low to BPWMn.
+     * |        |          |1 = Output logic high to BPWMn.
+     * |[2]     |MSKDAT2   |BPWM Mask Data Bit
+     * |        |          |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Output logic low to BPWMn.
+     * |        |          |1 = Output logic high to BPWMn.
+     * |[3]     |MSKDAT3   |BPWM Mask Data Bit
+     * |        |          |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Output logic low to BPWMn.
+     * |        |          |1 = Output logic high to BPWMn.
+     * |[4]     |MSKDAT4   |BPWM Mask Data Bit
+     * |        |          |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Output logic low to BPWMn.
+     * |        |          |1 = Output logic high to BPWMn.
+     * |[5]     |MSKDAT5   |BPWM Mask Data Bit
+     * |        |          |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Output logic low to BPWMn.
+     * |        |          |1 = Output logic high to BPWMn.
+     * @var BPWM_T::POLCTL
+     * Offset: 0xD4  BPWM Pin Polar Inverse Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PINV0     |BPWM PIN Polar Inverse Control
+     * |        |          |The register controls polarity state of BPWM output
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM output polar inverse Disabled.
+     * |        |          |1 = BPWM output polar inverse Enabled.
+     * |[1]     |PINV1     |BPWM PIN Polar Inverse Control
+     * |        |          |The register controls polarity state of BPWM output
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM output polar inverse Disabled.
+     * |        |          |1 = BPWM output polar inverse Enabled.
+     * |[2]     |PINV2     |BPWM PIN Polar Inverse Control
+     * |        |          |The register controls polarity state of BPWM output
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM output polar inverse Disabled.
+     * |        |          |1 = BPWM output polar inverse Enabled.
+     * |[3]     |PINV3     |BPWM PIN Polar Inverse Control
+     * |        |          |The register controls polarity state of BPWM output
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM output polar inverse Disabled.
+     * |        |          |1 = BPWM output polar inverse Enabled.
+     * |[4]     |PINV4     |BPWM PIN Polar Inverse Control
+     * |        |          |The register controls polarity state of BPWM output
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM output polar inverse Disabled.
+     * |        |          |1 = BPWM output polar inverse Enabled.
+     * |[5]     |PINV5     |BPWM PIN Polar Inverse Control
+     * |        |          |The register controls polarity state of BPWM output
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM output polar inverse Disabled.
+     * |        |          |1 = BPWM output polar inverse Enabled.
+     * @var BPWM_T::POEN
+     * Offset: 0xD8  BPWM Output Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |POEN0     |BPWM Pin Output Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM pin at tri-state.
+     * |        |          |1 = BPWM pin in output mode.
+     * |[1]     |POEN1     |BPWM Pin Output Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM pin at tri-state.
+     * |        |          |1 = BPWM pin in output mode.
+     * |[2]     |POEN2     |BPWM Pin Output Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM pin at tri-state.
+     * |        |          |1 = BPWM pin in output mode.
+     * |[3]     |POEN3     |BPWM Pin Output Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM pin at tri-state.
+     * |        |          |1 = BPWM pin in output mode.
+     * |[4]     |POEN4     |BPWM Pin Output Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM pin at tri-state.
+     * |        |          |1 = BPWM pin in output mode.
+     * |[5]     |POEN5     |BPWM Pin Output Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM pin at tri-state.
+     * |        |          |1 = BPWM pin in output mode.
+     * @var BPWM_T::INTEN
+     * Offset: 0xE0  BPWM Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ZIEN0     |BPWM Zero Point Interrupt 0 Enable Bit
+     * |        |          |0 = Zero point interrupt Disabled.
+     * |        |          |1 = Zero point interrupt Enabled.
+     * |[8]     |PIEN0     |BPWM Period Point Interrupt 0 Enable Bit
+     * |        |          |0 = Period point interrupt Disabled.
+     * |        |          |1 = Period point interrupt Enabled.
+     * |        |          |Note: When up-down counter type period point means center point.
+     * |[16]    |CMPUIEN0  |BPWM Compare Up Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |[17]    |CMPUIEN1  |BPWM Compare Up Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |[18]    |CMPUIEN2  |BPWM Compare Up Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |[19]    |CMPUIEN3  |BPWM Compare Up Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |[20]    |CMPUIEN4  |BPWM Compare Up Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |[21]    |CMPUIEN5  |BPWM Compare Up Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |[24]    |CMPDIEN0  |BPWM Compare Down Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * |[25]    |CMPDIEN1  |BPWM Compare Down Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * |[26]    |CMPDIEN2  |BPWM Compare Down Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * |[27]    |CMPDIEN3  |BPWM Compare Down Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * |[28]    |CMPDIEN4  |BPWM Compare Down Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * |[29]    |CMPDIEN5  |BPWM Compare Down Count Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * @var BPWM_T::INTSTS
+     * Offset: 0xE8  BPWM Interrupt Flag Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ZIF0      |BPWM Zero Point Interrupt Flag 0
+     * |        |          |This bit is set by hardware when BPWM_CH0 counter reaches zero, software can write 1 to clear this bit to zero.
+     * |[8]     |PIF0      |BPWM Period Point Interrupt Flag 0
+     * |        |          |This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to zero.
+     * |[16]    |CMPUIF0   |BPWM Compare Up Count Interrupt Flag
+     * |        |          |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+     * |[17]    |CMPUIF1   |BPWM Compare Up Count Interrupt Flag
+     * |        |          |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+     * |[18]    |CMPUIF2   |BPWM Compare Up Count Interrupt Flag
+     * |        |          |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+     * |[19]    |CMPUIF3   |BPWM Compare Up Count Interrupt Flag
+     * |        |          |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+     * |[20]    |CMPUIF4   |BPWM Compare Up Count Interrupt Flag
+     * |        |          |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+     * |[21]    |CMPUIF5   |BPWM Compare Up Count Interrupt Flag
+     * |        |          |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+     * |[24]    |CMPDIF0   |BPWM Compare Down Count Interrupt Flag
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+     * |[25]    |CMPDIF1   |BPWM Compare Down Count Interrupt Flag
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+     * |[26]    |CMPDIF2   |BPWM Compare Down Count Interrupt Flag
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+     * |[27]    |CMPDIF3   |BPWM Compare Down Count Interrupt Flag
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+     * |[28]    |CMPDIF4   |BPWM Compare Down Count Interrupt Flag
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+     * |[29]    |CMPDIF5   |BPWM Compare Down Count Interrupt Flag
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
+     * |        |          |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+     * @var BPWM_T::EADCTS0
+     * Offset: 0xF8  BPWM Trigger EADC Source Select Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |TRGSEL0   |BPWM_CH0 Trigger EADC Source Select
+     * |        |          |0000 = BPWM_CH0 zero point.
+     * |        |          |0001 = BPWM_CH0 period point.
+     * |        |          |0010 = BPWM_CH0 zero or period point.
+     * |        |          |0011 = BPWM_CH0 up-count CMPDAT point.
+     * |        |          |0100 = BPWM_CH0 down-count CMPDAT point.
+     * |        |          |0101 = Reserved.
+     * |        |          |0110 = Reserved.
+     * |        |          |0111 = Reserved.
+     * |        |          |1000 = BPWM_CH1 up-count CMPDAT point.
+     * |        |          |1001 = BPWM_CH1 down-count CMPDAT point.
+     * |        |          |Others reserved
+     * |[7]     |TRGEN0    |BPWM_CH0 Trigger EADC Enable Bit
+     * |[11:8]  |TRGSEL1   |BPWM_CH1 Trigger EADC Source Select
+     * |        |          |0000 = BPWM_CH0 zero point.
+     * |        |          |0001 = BPWM_CH0 period point.
+     * |        |          |0010 = BPWM_CH0 zero or period point.
+     * |        |          |0011 = BPWM_CH0 up-count CMPDAT point.
+     * |        |          |0100 = BPWM_CH0 down-count CMPDAT point.
+     * |        |          |0101 = Reserved.
+     * |        |          |0110 = Reserved.
+     * |        |          |0111 = Reserved.
+     * |        |          |1000 = BPWM_CH1 up-count CMPDAT point.
+     * |        |          |1001 = BPWM_CH1 down-count CMPDAT point.
+     * |        |          |Others reserved
+     * |[15]    |TRGEN1    |BPWM_CH1 Trigger EADC Enable Bit
+     * |[19:16] |TRGSEL2   |BPWM_CH2 Trigger EADC Source Select
+     * |        |          |0000 = BPWM_CH2 zero point.
+     * |        |          |0001 = BPWM_CH2 period point.
+     * |        |          |0010 = BPWM_CH2 zero or period point.
+     * |        |          |0011 = BPWM_CH2 up-count CMPDAT point.
+     * |        |          |0100 = BPWM_CH2 down-count CMPDAT point.
+     * |        |          |0101 = Reserved.
+     * |        |          |0110 = Reserved.
+     * |        |          |0111 = Reserved.
+     * |        |          |1000 = BPWM_CH3 up-count CMPDAT point.
+     * |        |          |1001 = BPWM_CH3 down-count CMPDAT point.
+     * |        |          |Others reserved
+     * |[23]    |TRGEN2    |BPWM_CH2 Trigger EADC Enable Bit
+     * |[27:24] |TRGSEL3   |BPWM_CH3 Trigger EADC Source Select
+     * |        |          |0000 = BPWM_CH2 zero point.
+     * |        |          |0001 = BPWM_CH2 period point.
+     * |        |          |0010 = BPWM_CH2 zero or period point.
+     * |        |          |0011 = BPWM_CH2 up-count CMPDAT point.
+     * |        |          |0100 = BPWM_CH2 down-count CMPDAT point.
+     * |        |          |0101 = Reserved.
+     * |        |          |0110 = Reserved.
+     * |        |          |0111 = Reserved.
+     * |        |          |1000 = BPWM_CH3 up-count CMPDAT point.
+     * |        |          |1001 = BPWM_CH3 down-count CMPDAT point.
+     * |        |          |Others reserved.
+     * |[31]    |TRGEN3    |BPWM_CH3 Trigger EADC Enable Bit
+     * @var BPWM_T::EADCTS1
+     * Offset: 0xFC  BPWM Trigger EADC Source Select Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |TRGSEL4   |BPWM_CH4 Trigger EADC Source Select
+     * |        |          |0000 = BPWM_CH4 zero point.
+     * |        |          |0001 = BPWM_CH4 period point.
+     * |        |          |0010 = BPWM_CH4 zero or period point.
+     * |        |          |0011 = BPWM_CH4 up-count CMPDAT point.
+     * |        |          |0100 = BPWM_CH4 down-count CMPDAT point.
+     * |        |          |0101 = Reserved.
+     * |        |          |0110 = Reserved.
+     * |        |          |0111 = Reserved.
+     * |        |          |1000 = BPWM_CH5 up-count CMPDAT point.
+     * |        |          |1001 = BPWM_CH5 down-count CMPDAT point.
+     * |        |          |Others reserved
+     * |[7]     |TRGEN4    |BPWM_CH4 Trigger EADC Enable Bit
+     * |[11:8]  |TRGSEL5   |BPWM_CH5 Trigger EADC Source Select
+     * |        |          |0000 = BPWM_CH4 zero point.
+     * |        |          |0001 = BPWM_CH4 period point.
+     * |        |          |0010 = BPWM_CH4 zero or period point.
+     * |        |          |0011 = BPWM_CH4 up-count CMPDAT point.
+     * |        |          |0100 = BPWM_CH4 down-count CMPDAT point.
+     * |        |          |0101 = Reserved.
+     * |        |          |0110 = Reserved.
+     * |        |          |0111 = Reserved.
+     * |        |          |1000 = BPWM_CH5 up-count CMPDAT point.
+     * |        |          |1001 = BPWM_CH5 down-count CMPDAT point.
+     * |        |          |Others reserved
+     * |[15]    |TRGEN5    |BPWM_CH5 Trigger EADC Enable Bit
+     * @var BPWM_T::SSCTL
+     * Offset: 0x110  BPWM Synchronous Start Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SSEN0     |BPWM Synchronous Start Function 0 Enable Bit
+     * |        |          |When synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN).
+     * |        |          |0 = BPWM synchronous start function Disabled.
+     * |        |          |1 = BPWM synchronous start function Enabled.
+     * |[9:8]   |SSRC      |BPWM Synchronous Start Source Select
+     * |        |          |00 = Synchronous start source come from PWM0.
+     * |        |          |01 = Synchronous start source come from PWM1.
+     * |        |          |10 = Synchronous start source come from BPWM0.
+     * |        |          |11 = Synchronous start source come from BPWM1.
+     * @var BPWM_T::SSTRG
+     * Offset: 0x114  BPWM Synchronous Start Trigger Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CNTSEN    |BPWM Counter Synchronous Start Enable Bit(Write Only)
+     * |        |          |BPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time.
+     * |        |          |Writing this bit to 1 will also set the counter enable bit if correlated BPWM channel counter synchronous start function is enabled.
+     * @var BPWM_T::STATUS
+     * Offset: 0x120  BPWM Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CNTMAX0   |Time-base Counter 0 Equal to 0xFFFF Latched Status
+     * |        |          |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
+     * |        |          |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
+     * |[16]    |EADCTRG0  |EADC Start of Conversion Status
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Indicates no EADC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+     * |[17]    |EADCTRG1  |EADC Start of Conversion Status
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Indicates no EADC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+     * |[18]    |EADCTRG2  |EADC Start of Conversion Status
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Indicates no EADC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+     * |[19]    |EADCTRG3  |EADC Start of Conversion Status
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Indicates no EADC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+     * |[20]    |EADCTRG4  |EADC Start of Conversion Status
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Indicates no EADC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+     * |[21]    |EADCTRG5  |EADC Start of Conversion Status
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Indicates no EADC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+     * @var BPWM_T::CAPINEN
+     * Offset: 0x200  BPWM Capture Input Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CAPINEN0  |Capture Input Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM Channel capture input path Disabled
+     * |        |          |The input of BPWM channel capture function is always regarded as 0.
+     * |        |          |1 = BPWM Channel capture input path Enabled
+     * |        |          |The input of BPWM channel capture function comes from correlative multifunction pin.
+     * |[1]     |CAPINEN1  |Capture Input Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM Channel capture input path Disabled
+     * |        |          |The input of BPWM channel capture function is always regarded as 0.
+     * |        |          |1 = BPWM Channel capture input path Enabled
+     * |        |          |The input of BPWM channel capture function comes from correlative multifunction pin.
+     * |[2]     |CAPINEN2  |Capture Input Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM Channel capture input path Disabled
+     * |        |          |The input of BPWM channel capture function is always regarded as 0.
+     * |        |          |1 = BPWM Channel capture input path Enabled
+     * |        |          |The input of BPWM channel capture function comes from correlative multifunction pin.
+     * |[3]     |CAPINEN3  |Capture Input Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM Channel capture input path Disabled
+     * |        |          |The input of BPWM channel capture function is always regarded as 0.
+     * |        |          |1 = BPWM Channel capture input path Enabled
+     * |        |          |The input of BPWM channel capture function comes from correlative multifunction pin.
+     * |[4]     |CAPINEN4  |Capture Input Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM Channel capture input path Disabled
+     * |        |          |The input of BPWM channel capture function is always regarded as 0.
+     * |        |          |1 = BPWM Channel capture input path Enabled
+     * |        |          |The input of BPWM channel capture function comes from correlative multifunction pin.
+     * |[5]     |CAPINEN5  |Capture Input Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = BPWM Channel capture input path Disabled
+     * |        |          |The input of BPWM channel capture function is always regarded as 0.
+     * |        |          |1 = BPWM Channel capture input path Enabled
+     * |        |          |The input of BPWM channel capture function comes from correlative multifunction pin.
+     * @var BPWM_T::CAPCTL
+     * Offset: 0x204  BPWM Capture Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CAPEN0    |Capture Function Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+     * |        |          |1 = Capture function Enabled
+     * |        |          |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+     * |[1]     |CAPEN1    |Capture Function Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+     * |        |          |1 = Capture function Enabled
+     * |        |          |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+     * |[2]     |CAPEN2    |Capture Function Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+     * |        |          |1 = Capture function Enabled
+     * |        |          |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+     * |[3]     |CAPEN3    |Capture Function Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+     * |        |          |1 = Capture function Enabled
+     * |        |          |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+     * |[4]     |CAPEN4    |Capture Function Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+     * |        |          |1 = Capture function Enabled
+     * |        |          |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+     * |[5]     |CAPEN5    |Capture Function Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+     * |        |          |1 = Capture function Enabled
+     * |        |          |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+     * |[8]     |CAPINV0   |Capture Inverter Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture source inverter Disabled.
+     * |        |          |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+     * |[9]     |CAPINV1   |Capture Inverter Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture source inverter Disabled.
+     * |        |          |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+     * |[10]    |CAPINV2   |Capture Inverter Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture source inverter Disabled.
+     * |        |          |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+     * |[11]    |CAPINV3   |Capture Inverter Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture source inverter Disabled.
+     * |        |          |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+     * |[12]    |CAPINV4   |Capture Inverter Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture source inverter Disabled.
+     * |        |          |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+     * |[13]    |CAPINV5   |Capture Inverter Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture source inverter Disabled.
+     * |        |          |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+     * |[16]    |RCRLDEN0  |Rising Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Rising capture reload counter Disabled.
+     * |        |          |1 = Rising capture reload counter Enabled.
+     * |[17]    |RCRLDEN1  |Rising Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Rising capture reload counter Disabled.
+     * |        |          |1 = Rising capture reload counter Enabled.
+     * |[18]    |RCRLDEN2  |Rising Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Rising capture reload counter Disabled.
+     * |        |          |1 = Rising capture reload counter Enabled.
+     * |[19]    |RCRLDEN3  |Rising Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Rising capture reload counter Disabled.
+     * |        |          |1 = Rising capture reload counter Enabled.
+     * |[20]    |RCRLDEN4  |Rising Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Rising capture reload counter Disabled.
+     * |        |          |1 = Rising capture reload counter Enabled.
+     * |[21]    |RCRLDEN5  |Rising Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Rising capture reload counter Disabled.
+     * |        |          |1 = Rising capture reload counter Enabled.
+     * |[24]    |FCRLDEN0  |Falling Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Falling capture reload counter Disabled.
+     * |        |          |1 = Falling capture reload counter Enabled.
+     * |[25]    |FCRLDEN1  |Falling Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Falling capture reload counter Disabled.
+     * |        |          |1 = Falling capture reload counter Enabled.
+     * |[26]    |FCRLDEN2  |Falling Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Falling capture reload counter Disabled.
+     * |        |          |1 = Falling capture reload counter Enabled.
+     * |[27]    |FCRLDEN3  |Falling Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Falling capture reload counter Disabled.
+     * |        |          |1 = Falling capture reload counter Enabled.
+     * |[28]    |FCRLDEN4  |Falling Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Falling capture reload counter Disabled.
+     * |        |          |1 = Falling capture reload counter Enabled.
+     * |[29]    |FCRLDEN5  |Falling Capture Reload Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Falling capture reload counter Disabled.
+     * |        |          |1 = Falling capture reload counter Enabled.
+     * @var BPWM_T::CAPSTS
+     * Offset: 0x208  BPWM Capture Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CRIFOV0   |Capture Rising Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
+     * |[1]     |CRIFOV1   |Capture Rising Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
+     * |[2]     |CRIFOV2   |Capture Rising Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
+     * |[3]     |CRIFOV3   |Capture Rising Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
+     * |[4]     |CRIFOV4   |Capture Rising Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
+     * |[5]     |CRIFOV5   |Capture Rising Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
+     * |[8]     |CFIFOV0   |Capture Falling Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
+     * |[9]     |CFIFOV1   |Capture Falling Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
+     * |[10]    |CFIFOV2   |Capture Falling Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
+     * |[11]    |CFIFOV3   |Capture Falling Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
+     * |[12]    |CFIFOV4   |Capture Falling Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
+     * |[13]    |CFIFOV5   |Capture Falling Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
+     * @var BPWM_T::CAPIEN
+     * Offset: 0x250  BPWM Capture Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[5:0]   |CAPRIENn  |BPWM Capture Rising Latch Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture rising edge latch interrupt Disabled.
+     * |        |          |1 = Capture rising edge latch interrupt Enabled.
+     * |[13:8]  |CAPFIENn  |BPWM Capture Falling Latch Interrupt Enable Bits
+     * |        |          |Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = Capture falling edge latch interrupt Disabled.
+     * |        |          |1 = Capture falling edge latch interrupt Enabled.
+     * @var BPWM_T::CAPIF
+     * Offset: 0x254  BPWM Capture Interrupt Flag Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CAPRIF0   |BPWM Capture Rising Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture rising latch condition happened.
+     * |        |          |1 = Capture rising latch condition happened, this flag will be set to high.
+     * |[1]     |CAPRIF1   |BPWM Capture Rising Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture rising latch condition happened.
+     * |        |          |1 = Capture rising latch condition happened, this flag will be set to high.
+     * |[2]     |CAPRIF2   |BPWM Capture Rising Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture rising latch condition happened.
+     * |        |          |1 = Capture rising latch condition happened, this flag will be set to high.
+     * |[3]     |CAPRIF3   |BPWM Capture Rising Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture rising latch condition happened.
+     * |        |          |1 = Capture rising latch condition happened, this flag will be set to high.
+     * |[4]     |CAPRIF4   |BPWM Capture Rising Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture rising latch condition happened.
+     * |        |          |1 = Capture rising latch condition happened, this flag will be set to high.
+     * |[5]     |CAPRIF5   |BPWM Capture Rising Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture rising latch condition happened.
+     * |        |          |1 = Capture rising latch condition happened, this flag will be set to high.
+     * |[8]     |CAPFIF0   |BPWM Capture Falling Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture falling latch condition happened.
+     * |        |          |1 = Capture falling latch condition happened, this flag will be set to high.
+     * |[9]     |CAPFIF1   |BPWM Capture Falling Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture falling latch condition happened.
+     * |        |          |1 = Capture falling latch condition happened, this flag will be set to high.
+     * |[10]    |CAPFIF2   |BPWM Capture Falling Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture falling latch condition happened.
+     * |        |          |1 = Capture falling latch condition happened, this flag will be set to high.
+     * |[11]    |CAPFIF3   |BPWM Capture Falling Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture falling latch condition happened.
+     * |        |          |1 = Capture falling latch condition happened, this flag will be set to high.
+     * |[12]    |CAPFIF4   |BPWM Capture Falling Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture falling latch condition happened.
+     * |        |          |1 = Capture falling latch condition happened, this flag will be set to high.
+     * |[13]    |CAPFIF5   |BPWM Capture Falling Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
+     * |        |          |0 = No capture falling latch condition happened.
+     * |        |          |1 = Capture falling latch condition happened, this flag will be set to high.
+     * @var BPWM_T::PBUF
+     * Offset: 0x304  BPWM PERIOD Buffer
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |PBUF      |BPWM Period Buffer (Read Only)
+     * |        |          |Used as PERIOD active register.
+     * @var BPWM_T::CMPBUF[6]
+     * Offset: 0x31C  BPWM CMPDAT 0~5 Buffer
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |CMPBUF    |BPWM Comparator Buffer (Read Only)
+     * |        |          |Used as CMP active register.
+     */
+    __IO uint32_t CTL0;                  /*!< [0x0000] BPWM Control Register 0                                          */
+    __IO uint32_t CTL1;                  /*!< [0x0004] BPWM Control Register 1                                          */
+    __I  uint32_t RESERVED0[2];
+    __IO uint32_t CLKSRC;                /*!< [0x0010] BPWM Clock Source Register                                       */
+    __IO uint32_t CLKPSC;                /*!< [0x0014] BPWM Clock Prescale Register                                     */
+    __I  uint32_t RESERVED1[2];
+    __IO uint32_t CNTEN;                 /*!< [0x0020] BPWM Counter Enable Register                                     */
+    __IO uint32_t CNTCLR;                /*!< [0x0024] BPWM Clear Counter Register                                      */
+    __I  uint32_t RESERVED2[2];
+    __IO uint32_t PERIOD;                /*!< [0x0030] BPWM Period Register                                             */
+    __I  uint32_t RESERVED3[7];
+    __IO uint32_t CMPDAT[6];             /*!< [0x0050~0x0064] BPWM Comparator Register 0~5                              */
+    __I  uint32_t RESERVED4[10];
+    __I  uint32_t CNT;                   /*!< [0x0090] BPWM Counter Register                                            */
+    __I  uint32_t RESERVED5[7];
+    __IO uint32_t WGCTL0;                /*!< [0x00b0] BPWM Generation Register 0                                       */
+    __IO uint32_t WGCTL1;                /*!< [0x00b4] BPWM Generation Register 1                                       */
+    __IO uint32_t MSKEN;                 /*!< [0x00b8] BPWM Mask Enable Register                                        */
+    __IO uint32_t MSK;                   /*!< [0x00bc] BPWM Mask Data Register                                          */
+    __I  uint32_t RESERVED6[5];
+    __IO uint32_t POLCTL;                /*!< [0x00d4] BPWM Pin Polar Inverse Register                                  */
+    __IO uint32_t POEN;                  /*!< [0x00d8] BPWM Output Enable Register                                      */
+    __I  uint32_t RESERVED7[1];
+    __IO uint32_t INTEN;                 /*!< [0x00e0] BPWM Interrupt Enable Register                                   */
+    __I  uint32_t RESERVED8[1];
+    __IO uint32_t INTSTS;                /*!< [0x00e8] BPWM Interrupt Flag Register                                     */
+    __I  uint32_t RESERVED9[3];
+    __IO uint32_t EADCTS0;               /*!< [0x00f8] BPWM Trigger EADC Source Select Register 0                       */
+    __IO uint32_t EADCTS1;               /*!< [0x00fc] BPWM Trigger EADC Source Select Register 1                       */
+    __I  uint32_t RESERVED10[4];
+    __IO uint32_t SSCTL;                 /*!< [0x0110] BPWM Synchronous Start Control Register                          */
+    __O  uint32_t SSTRG;                 /*!< [0x0114] BPWM Synchronous Start Trigger Register                          */
+    __I  uint32_t RESERVED11[2];
+    __IO uint32_t STATUS;                /*!< [0x0120] BPWM Status Register                                             */
+    __I  uint32_t RESERVED12[55];
+    __IO uint32_t CAPINEN;               /*!< [0x0200] BPWM Capture Input Enable Register                               */
+    __IO uint32_t CAPCTL;                /*!< [0x0204] BPWM Capture Control Register                                    */
+    __I  uint32_t CAPSTS;                /*!< [0x0208] BPWM Capture Status Register                                     */
+    BCAPDAT_T CAPDAT[6];                  /*!< [0x020c~0x0238] BPWM Rising and Falling Capture Data Register 0~5         */
+    __I  uint32_t RESERVED13[5];
+    __IO uint32_t CAPIEN;                /*!< [0x0250] BPWM Capture Interrupt Enable Register                           */
+    __IO uint32_t CAPIF;                 /*!< [0x0254] BPWM Capture Interrupt Flag Register                             */
+    __I  uint32_t RESERVED14[43];
+    __I  uint32_t PBUF;                  /*!< [0x0304] BPWM PERIOD Buffer                                               */
+    __I  uint32_t RESERVED15[5];
+    __I  uint32_t CMPBUF[6];               /*!< [0x031c~0x0330] BPWM CMPDAT 0~5 Buffer                                  */
+
+} BPWM_T;
+
+/**
+    @addtogroup BPWM_CONST BPWM Bit Field Definition
+    Constant Definitions for BPWM Controller
+  @{
+*/
+
+#define BPWM_CTL0_CTRLD0_Pos             (0)                                               /*!< BPWM_T::CTL0: CTRLD0 Position          */
+#define BPWM_CTL0_CTRLD0_Msk             (0x1ul << BPWM_CTL0_CTRLD0_Pos)                   /*!< BPWM_T::CTL0: CTRLD0 Mask              */
+
+#define BPWM_CTL0_CTRLD1_Pos             (1)                                               /*!< BPWM_T::CTL0: CTRLD1 Position          */
+#define BPWM_CTL0_CTRLD1_Msk             (0x1ul << BPWM_CTL0_CTRLD1_Pos)                   /*!< BPWM_T::CTL0: CTRLD1 Mask              */
+
+#define BPWM_CTL0_CTRLD2_Pos             (2)                                               /*!< BPWM_T::CTL0: CTRLD2 Position          */
+#define BPWM_CTL0_CTRLD2_Msk             (0x1ul << BPWM_CTL0_CTRLD2_Pos)                   /*!< BPWM_T::CTL0: CTRLD2 Mask              */
+
+#define BPWM_CTL0_CTRLD3_Pos             (3)                                               /*!< BPWM_T::CTL0: CTRLD3 Position          */
+#define BPWM_CTL0_CTRLD3_Msk             (0x1ul << BPWM_CTL0_CTRLD3_Pos)                   /*!< BPWM_T::CTL0: CTRLD3 Mask              */
+
+#define BPWM_CTL0_CTRLD4_Pos             (4)                                               /*!< BPWM_T::CTL0: CTRLD4 Position          */
+#define BPWM_CTL0_CTRLD4_Msk             (0x1ul << BPWM_CTL0_CTRLD4_Pos)                   /*!< BPWM_T::CTL0: CTRLD4 Mask              */
+
+#define BPWM_CTL0_CTRLD5_Pos             (5)                                               /*!< BPWM_T::CTL0: CTRLD5 Position          */
+#define BPWM_CTL0_CTRLD5_Msk             (0x1ul << BPWM_CTL0_CTRLD5_Pos)                   /*!< BPWM_T::CTL0: CTRLD5 Mask              */
+
+#define BPWM_CTL0_IMMLDEN0_Pos           (16)                                              /*!< BPWM_T::CTL0: IMMLDEN0 Position        */
+#define BPWM_CTL0_IMMLDEN0_Msk           (0x1ul << BPWM_CTL0_IMMLDEN0_Pos)                 /*!< BPWM_T::CTL0: IMMLDEN0 Mask            */
+
+#define BPWM_CTL0_IMMLDEN1_Pos           (17)                                              /*!< BPWM_T::CTL0: IMMLDEN1 Position        */
+#define BPWM_CTL0_IMMLDEN1_Msk           (0x1ul << BPWM_CTL0_IMMLDEN1_Pos)                 /*!< BPWM_T::CTL0: IMMLDEN1 Mask            */
+
+#define BPWM_CTL0_IMMLDEN2_Pos           (18)                                              /*!< BPWM_T::CTL0: IMMLDEN2 Position        */
+#define BPWM_CTL0_IMMLDEN2_Msk           (0x1ul << BPWM_CTL0_IMMLDEN2_Pos)                 /*!< BPWM_T::CTL0: IMMLDEN2 Mask            */
+
+#define BPWM_CTL0_IMMLDEN3_Pos           (19)                                              /*!< BPWM_T::CTL0: IMMLDEN3 Position        */
+#define BPWM_CTL0_IMMLDEN3_Msk           (0x1ul << BPWM_CTL0_IMMLDEN3_Pos)                 /*!< BPWM_T::CTL0: IMMLDEN3 Mask            */
+
+#define BPWM_CTL0_IMMLDEN4_Pos           (20)                                              /*!< BPWM_T::CTL0: IMMLDEN4 Position        */
+#define BPWM_CTL0_IMMLDEN4_Msk           (0x1ul << BPWM_CTL0_IMMLDEN4_Pos)                 /*!< BPWM_T::CTL0: IMMLDEN4 Mask            */
+
+#define BPWM_CTL0_IMMLDEN5_Pos           (21)                                              /*!< BPWM_T::CTL0: IMMLDEN5 Position        */
+#define BPWM_CTL0_IMMLDEN5_Msk           (0x1ul << BPWM_CTL0_IMMLDEN5_Pos)                 /*!< BPWM_T::CTL0: IMMLDEN5 Mask            */
+
+#define BPWM_CTL0_DBGHALT_Pos            (30)                                              /*!< BPWM_T::CTL0: DBGHALT Position         */
+#define BPWM_CTL0_DBGHALT_Msk            (0x1ul << BPWM_CTL0_DBGHALT_Pos)                  /*!< BPWM_T::CTL0: DBGHALT Mask             */
+
+#define BPWM_CTL0_DBGTRIOFF_Pos          (31)                                              /*!< BPWM_T::CTL0: DBGTRIOFF Position       */
+#define BPWM_CTL0_DBGTRIOFF_Msk          (0x1ul << BPWM_CTL0_DBGTRIOFF_Pos)                /*!< BPWM_T::CTL0: DBGTRIOFF Mask           */
+
+#define BPWM_CTL1_CNTTYPE0_Pos           (0)                                               /*!< BPWM_T::CTL1: CNTTYPE0 Position        */
+#define BPWM_CTL1_CNTTYPE0_Msk           (0x3ul << BPWM_CTL1_CNTTYPE0_Pos)                 /*!< BPWM_T::CTL1: CNTTYPE0 Mask            */
+
+#define BPWM_CLKSRC_ECLKSRC0_Pos         (0)                                               /*!< BPWM_T::CLKSRC: ECLKSRC0 Position      */
+#define BPWM_CLKSRC_ECLKSRC0_Msk         (0x7ul << BPWM_CLKSRC_ECLKSRC0_Pos)               /*!< BPWM_T::CLKSRC: ECLKSRC0 Mask          */
+
+#define BPWM_CLKPSC_CLKPSC_Pos           (0)                                               /*!< BPWM_T::CLKPSC: CLKPSC Position        */
+#define BPWM_CLKPSC_CLKPSC_Msk           (0xffful << BPWM_CLKPSC_CLKPSC_Pos)               /*!< BPWM_T::CLKPSC: CLKPSC Mask            */
+
+#define BPWM_CNTEN_CNTEN0_Pos            (0)                                               /*!< BPWM_T::CNTEN: CNTEN0 Position         */
+#define BPWM_CNTEN_CNTEN0_Msk            (0x1ul << BPWM_CNTEN_CNTEN0_Pos)                  /*!< BPWM_T::CNTEN: CNTEN0 Mask             */
+
+#define BPWM_CNTCLR_CNTCLR0_Pos          (0)                                               /*!< BPWM_T::CNTCLR: CNTCLR0 Position       */
+#define BPWM_CNTCLR_CNTCLR0_Msk          (0x1ul << BPWM_CNTCLR_CNTCLR0_Pos)                /*!< BPWM_T::CNTCLR: CNTCLR0 Mask           */
+
+#define BPWM_PERIOD_PERIOD_Pos           (0)                                               /*!< BPWM_T::PERIOD: PERIOD Position        */
+#define BPWM_PERIOD_PERIOD_Msk           (0xfffful << BPWM_PERIOD_PERIOD_Pos)              /*!< BPWM_T::PERIOD: PERIOD Mask            */
+
+#define BPWM_CMPDAT0_CMPDAT_Pos          (0)                                               /*!< BPWM_T::CMPDAT0: CMPDAT Position       */
+#define BPWM_CMPDAT0_CMPDAT_Msk          (0xfffful << BPWM_CMPDAT0_CMPDAT_Pos)             /*!< BPWM_T::CMPDAT0: CMPDAT Mask           */
+
+#define BPWM_CMPDAT1_CMPDAT_Pos          (0)                                               /*!< BPWM_T::CMPDAT1: CMPDAT Position       */
+#define BPWM_CMPDAT1_CMPDAT_Msk          (0xfffful << BPWM_CMPDAT1_CMPDAT_Pos)             /*!< BPWM_T::CMPDAT1: CMPDAT Mask           */
+
+#define BPWM_CMPDAT2_CMPDAT_Pos          (0)                                               /*!< BPWM_T::CMPDAT2: CMPDAT Position       */
+#define BPWM_CMPDAT2_CMPDAT_Msk          (0xfffful << BPWM_CMPDAT2_CMPDAT_Pos)             /*!< BPWM_T::CMPDAT2: CMPDAT Mask           */
+
+#define BPWM_CMPDAT3_CMPDAT_Pos          (0)                                               /*!< BPWM_T::CMPDAT3: CMPDAT Position       */
+#define BPWM_CMPDAT3_CMPDAT_Msk          (0xfffful << BPWM_CMPDAT3_CMPDAT_Pos)             /*!< BPWM_T::CMPDAT3: CMPDAT Mask           */
+
+#define BPWM_CMPDAT4_CMPDAT_Pos          (0)                                               /*!< BPWM_T::CMPDAT4: CMPDAT Position       */
+#define BPWM_CMPDAT4_CMPDAT_Msk          (0xfffful << BPWM_CMPDAT4_CMPDAT_Pos)             /*!< BPWM_T::CMPDAT4: CMPDAT Mask           */
+
+#define BPWM_CMPDAT5_CMPDAT_Pos          (0)                                               /*!< BPWM_T::CMPDAT5: CMPDAT Position       */
+#define BPWM_CMPDAT5_CMPDAT_Msk          (0xfffful << BPWM_CMPDAT5_CMPDAT_Pos)             /*!< BPWM_T::CMPDAT5: CMPDAT Mask           */
+
+#define BPWM_CNT_CNT_Pos                 (0)                                               /*!< BPWM_T::CNT: CNT Position              */
+#define BPWM_CNT_CNT_Msk                 (0xfffful << BPWM_CNT_CNT_Pos)                    /*!< BPWM_T::CNT: CNT Mask                  */
+
+#define BPWM_CNT_DIRF_Pos                (16)                                              /*!< BPWM_T::CNT: DIRF Position             */
+#define BPWM_CNT_DIRF_Msk                (0x1ul << BPWM_CNT_DIRF_Pos)                      /*!< BPWM_T::CNT: DIRF Mask                 */
+
+#define BPWM_WGCTL0_ZPCTL0_Pos           (0)                                               /*!< BPWM_T::WGCTL0: ZPCTL0 Position        */
+#define BPWM_WGCTL0_ZPCTL0_Msk           (0x3ul << BPWM_WGCTL0_ZPCTL0_Pos)                 /*!< BPWM_T::WGCTL0: ZPCTL0 Mask            */
+
+#define BPWM_WGCTL0_ZPCTL1_Pos           (2)                                               /*!< BPWM_T::WGCTL0: ZPCTL1 Position        */
+#define BPWM_WGCTL0_ZPCTL1_Msk           (0x3ul << BPWM_WGCTL0_ZPCTL1_Pos)                 /*!< BPWM_T::WGCTL0: ZPCTL1 Mask            */
+
+#define BPWM_WGCTL0_ZPCTL2_Pos           (4)                                               /*!< BPWM_T::WGCTL0: ZPCTL2 Position        */
+#define BPWM_WGCTL0_ZPCTL2_Msk           (0x3ul << BPWM_WGCTL0_ZPCTL2_Pos)                 /*!< BPWM_T::WGCTL0: ZPCTL2 Mask            */
+
+#define BPWM_WGCTL0_ZPCTL3_Pos           (6)                                               /*!< BPWM_T::WGCTL0: ZPCTL3 Position        */
+#define BPWM_WGCTL0_ZPCTL3_Msk           (0x3ul << BPWM_WGCTL0_ZPCTL3_Pos)                 /*!< BPWM_T::WGCTL0: ZPCTL3 Mask            */
+
+#define BPWM_WGCTL0_ZPCTL4_Pos           (8)                                               /*!< BPWM_T::WGCTL0: ZPCTL4 Position        */
+#define BPWM_WGCTL0_ZPCTL4_Msk           (0x3ul << BPWM_WGCTL0_ZPCTL4_Pos)                 /*!< BPWM_T::WGCTL0: ZPCTL4 Mask            */
+
+#define BPWM_WGCTL0_ZPCTL5_Pos           (10)                                              /*!< BPWM_T::WGCTL0: ZPCTL5 Position        */
+#define BPWM_WGCTL0_ZPCTL5_Msk           (0x3ul << BPWM_WGCTL0_ZPCTL5_Pos)                 /*!< BPWM_T::WGCTL0: ZPCTL5 Mask            */
+
+#define BPWM_WGCTL0_ZPCTLn_Pos           (0)                                               /*!< BPWM_T::WGCTL0: ZPCTLn Position        */
+#define BPWM_WGCTL0_ZPCTLn_Msk           (0xffful << BPWM_WGCTL0_ZPCTLn_Pos)               /*!< BPWM_T::WGCTL0: ZPCTLn Mask            */
+
+#define BPWM_WGCTL0_PRDPCTL0_Pos         (16)                                              /*!< BPWM_T::WGCTL0: PRDPCTL0 Position      */
+#define BPWM_WGCTL0_PRDPCTL0_Msk         (0x3ul << BPWM_WGCTL0_PRDPCTL0_Pos)               /*!< BPWM_T::WGCTL0: PRDPCTL0 Mask          */
+
+#define BPWM_WGCTL0_PRDPCTL1_Pos         (18)                                              /*!< BPWM_T::WGCTL0: PRDPCTL1 Position      */
+#define BPWM_WGCTL0_PRDPCTL1_Msk         (0x3ul << BPWM_WGCTL0_PRDPCTL1_Pos)               /*!< BPWM_T::WGCTL0: PRDPCTL1 Mask          */
+
+#define BPWM_WGCTL0_PRDPCTL2_Pos         (20)                                              /*!< BPWM_T::WGCTL0: PRDPCTL2 Position      */
+#define BPWM_WGCTL0_PRDPCTL2_Msk         (0x3ul << BPWM_WGCTL0_PRDPCTL2_Pos)               /*!< BPWM_T::WGCTL0: PRDPCTL2 Mask          */
+
+#define BPWM_WGCTL0_PRDPCTL3_Pos         (22)                                              /*!< BPWM_T::WGCTL0: PRDPCTL3 Position      */
+#define BPWM_WGCTL0_PRDPCTL3_Msk         (0x3ul << BPWM_WGCTL0_PRDPCTL3_Pos)               /*!< BPWM_T::WGCTL0: PRDPCTL3 Mask          */
+
+#define BPWM_WGCTL0_PRDPCTL4_Pos         (24)                                              /*!< BPWM_T::WGCTL0: PRDPCTL4 Position      */
+#define BPWM_WGCTL0_PRDPCTL4_Msk         (0x3ul << BPWM_WGCTL0_PRDPCTL4_Pos)               /*!< BPWM_T::WGCTL0: PRDPCTL4 Mask          */
+
+#define BPWM_WGCTL0_PRDPCTL5_Pos         (26)                                              /*!< BPWM_T::WGCTL0: PRDPCTL5 Position      */
+#define BPWM_WGCTL0_PRDPCTL5_Msk         (0x3ul << BPWM_WGCTL0_PRDPCTL5_Pos)               /*!< BPWM_T::WGCTL0: PRDPCTL5 Mask          */
+
+#define BPWM_WGCTL0_PRDPCTLn_Pos         (16)                                              /*!< BPWM_T::WGCTL0: PRDPCTLn Position      */
+#define BPWM_WGCTL0_PRDPCTLn_Msk         (0xffful << BPWM_WGCTL0_PRDPCTLn_Pos)             /*!< BPWM_T::WGCTL0: PRDPCTLn Mask          */
+
+#define BPWM_WGCTL1_CMPUCTL0_Pos         (0)                                               /*!< BPWM_T::WGCTL1: CMPUCTL0 Position      */
+#define BPWM_WGCTL1_CMPUCTL0_Msk         (0x3ul << BPWM_WGCTL1_CMPUCTL0_Pos)               /*!< BPWM_T::WGCTL1: CMPUCTL0 Mask          */
+
+#define BPWM_WGCTL1_CMPUCTL1_Pos         (2)                                               /*!< BPWM_T::WGCTL1: CMPUCTL1 Position      */
+#define BPWM_WGCTL1_CMPUCTL1_Msk         (0x3ul << BPWM_WGCTL1_CMPUCTL1_Pos)               /*!< BPWM_T::WGCTL1: CMPUCTL1 Mask          */
+
+#define BPWM_WGCTL1_CMPUCTL2_Pos         (4)                                               /*!< BPWM_T::WGCTL1: CMPUCTL2 Position      */
+#define BPWM_WGCTL1_CMPUCTL2_Msk         (0x3ul << BPWM_WGCTL1_CMPUCTL2_Pos)               /*!< BPWM_T::WGCTL1: CMPUCTL2 Mask          */
+
+#define BPWM_WGCTL1_CMPUCTL3_Pos         (6)                                               /*!< BPWM_T::WGCTL1: CMPUCTL3 Position      */
+#define BPWM_WGCTL1_CMPUCTL3_Msk         (0x3ul << BPWM_WGCTL1_CMPUCTL3_Pos)               /*!< BPWM_T::WGCTL1: CMPUCTL3 Mask          */
+
+#define BPWM_WGCTL1_CMPUCTL4_Pos         (8)                                               /*!< BPWM_T::WGCTL1: CMPUCTL4 Position      */
+#define BPWM_WGCTL1_CMPUCTL4_Msk         (0x3ul << BPWM_WGCTL1_CMPUCTL4_Pos)               /*!< BPWM_T::WGCTL1: CMPUCTL4 Mask          */
+
+#define BPWM_WGCTL1_CMPUCTL5_Pos         (10)                                              /*!< BPWM_T::WGCTL1: CMPUCTL5 Position      */
+#define BPWM_WGCTL1_CMPUCTL5_Msk         (0x3ul << BPWM_WGCTL1_CMPUCTL5_Pos)               /*!< BPWM_T::WGCTL1: CMPUCTL5 Mask          */
+
+#define BPWM_WGCTL1_CMPUCTLn_Pos         (0)                                               /*!< BPWM_T::WGCTL1: CMPUCTLn Position      */
+#define BPWM_WGCTL1_CMPUCTLn_Msk         (0xffful << BPWM_WGCTL1_CMPUCTLn_Pos)             /*!< BPWM_T::WGCTL1: CMPUCTLn Mask          */
+
+#define BPWM_WGCTL1_CMPDCTL0_Pos         (16)                                              /*!< BPWM_T::WGCTL1: CMPDCTL0 Position      */
+#define BPWM_WGCTL1_CMPDCTL0_Msk         (0x3ul << BPWM_WGCTL1_CMPDCTL0_Pos)               /*!< BPWM_T::WGCTL1: CMPDCTL0 Mask          */
+
+#define BPWM_WGCTL1_CMPDCTL1_Pos         (18)                                              /*!< BPWM_T::WGCTL1: CMPDCTL1 Position      */
+#define BPWM_WGCTL1_CMPDCTL1_Msk         (0x3ul << BPWM_WGCTL1_CMPDCTL1_Pos)               /*!< BPWM_T::WGCTL1: CMPDCTL1 Mask          */
+
+#define BPWM_WGCTL1_CMPDCTL2_Pos         (20)                                              /*!< BPWM_T::WGCTL1: CMPDCTL2 Position      */
+#define BPWM_WGCTL1_CMPDCTL2_Msk         (0x3ul << BPWM_WGCTL1_CMPDCTL2_Pos)               /*!< BPWM_T::WGCTL1: CMPDCTL2 Mask          */
+
+#define BPWM_WGCTL1_CMPDCTL3_Pos         (22)                                              /*!< BPWM_T::WGCTL1: CMPDCTL3 Position      */
+#define BPWM_WGCTL1_CMPDCTL3_Msk         (0x3ul << BPWM_WGCTL1_CMPDCTL3_Pos)               /*!< BPWM_T::WGCTL1: CMPDCTL3 Mask          */
+
+#define BPWM_WGCTL1_CMPDCTL4_Pos         (24)                                              /*!< BPWM_T::WGCTL1: CMPDCTL4 Position      */
+#define BPWM_WGCTL1_CMPDCTL4_Msk         (0x3ul << BPWM_WGCTL1_CMPDCTL4_Pos)               /*!< BPWM_T::WGCTL1: CMPDCTL4 Mask          */
+
+#define BPWM_WGCTL1_CMPDCTL5_Pos         (26)                                              /*!< BPWM_T::WGCTL1: CMPDCTL5 Position      */
+#define BPWM_WGCTL1_CMPDCTL5_Msk         (0x3ul << BPWM_WGCTL1_CMPDCTL5_Pos)               /*!< BPWM_T::WGCTL1: CMPDCTL5 Mask          */
+
+#define BPWM_WGCTL1_CMPDCTLn_Pos         (16)                                              /*!< BPWM_T::WGCTL1: CMPDCTLn Position      */
+#define BPWM_WGCTL1_CMPDCTLn_Msk         (0xffful << BPWM_WGCTL1_CMPDCTLn_Pos)             /*!< BPWM_T::WGCTL1: CMPDCTLn Mask          */
+
+#define BPWM_MSKEN_MSKEN0_Pos            (0)                                               /*!< BPWM_T::MSKEN: MSKEN0 Position         */
+#define BPWM_MSKEN_MSKEN0_Msk            (0x1ul << BPWM_MSKEN_MSKEN0_Pos)                  /*!< BPWM_T::MSKEN: MSKEN0 Mask             */
+
+#define BPWM_MSKEN_MSKEN1_Pos            (1)                                               /*!< BPWM_T::MSKEN: MSKEN1 Position         */
+#define BPWM_MSKEN_MSKEN1_Msk            (0x1ul << BPWM_MSKEN_MSKEN1_Pos)                  /*!< BPWM_T::MSKEN: MSKEN1 Mask             */
+
+#define BPWM_MSKEN_MSKEN2_Pos            (2)                                               /*!< BPWM_T::MSKEN: MSKEN2 Position         */
+#define BPWM_MSKEN_MSKEN2_Msk            (0x1ul << BPWM_MSKEN_MSKEN2_Pos)                  /*!< BPWM_T::MSKEN: MSKEN2 Mask             */
+
+#define BPWM_MSKEN_MSKEN3_Pos            (3)                                               /*!< BPWM_T::MSKEN: MSKEN3 Position         */
+#define BPWM_MSKEN_MSKEN3_Msk            (0x1ul << BPWM_MSKEN_MSKEN3_Pos)                  /*!< BPWM_T::MSKEN: MSKEN3 Mask             */
+
+#define BPWM_MSKEN_MSKEN4_Pos            (4)                                               /*!< BPWM_T::MSKEN: MSKEN4 Position         */
+#define BPWM_MSKEN_MSKEN4_Msk            (0x1ul << BPWM_MSKEN_MSKEN4_Pos)                  /*!< BPWM_T::MSKEN: MSKEN4 Mask             */
+
+#define BPWM_MSKEN_MSKEN5_Pos            (5)                                               /*!< BPWM_T::MSKEN: MSKEN5 Position         */
+#define BPWM_MSKEN_MSKEN5_Msk            (0x1ul << BPWM_MSKEN_MSKEN5_Pos)                  /*!< BPWM_T::MSKEN: MSKEN5 Mask             */
+
+#define BPWM_MSKEN_MSKENn_Pos            (0)                                               /*!< BPWM_T::MSKEN: MSKENn Position         */
+#define BPWM_MSKEN_MSKENn_Msk            (0x3ful << BPWM_MSKEN_MSKENn_Pos)                 /*!< BPWM_T::MSKEN: MSKENn Mask             */
+
+#define BPWM_MSK_MSKDAT0_Pos             (0)                                               /*!< BPWM_T::MSK: MSKDAT0 Position          */
+#define BPWM_MSK_MSKDAT0_Msk             (0x1ul << BPWM_MSK_MSKDAT0_Pos)                   /*!< BPWM_T::MSK: MSKDAT0 Mask              */
+
+#define BPWM_MSK_MSKDAT1_Pos             (1)                                               /*!< BPWM_T::MSK: MSKDAT1 Position          */
+#define BPWM_MSK_MSKDAT1_Msk             (0x1ul << BPWM_MSK_MSKDAT1_Pos)                   /*!< BPWM_T::MSK: MSKDAT1 Mask              */
+
+#define BPWM_MSK_MSKDAT2_Pos             (2)                                               /*!< BPWM_T::MSK: MSKDAT2 Position          */
+#define BPWM_MSK_MSKDAT2_Msk             (0x1ul << BPWM_MSK_MSKDAT2_Pos)                   /*!< BPWM_T::MSK: MSKDAT2 Mask              */
+
+#define BPWM_MSK_MSKDAT3_Pos             (3)                                               /*!< BPWM_T::MSK: MSKDAT3 Position          */
+#define BPWM_MSK_MSKDAT3_Msk             (0x1ul << BPWM_MSK_MSKDAT3_Pos)                   /*!< BPWM_T::MSK: MSKDAT3 Mask              */
+
+#define BPWM_MSK_MSKDAT4_Pos             (4)                                               /*!< BPWM_T::MSK: MSKDAT4 Position          */
+#define BPWM_MSK_MSKDAT4_Msk             (0x1ul << BPWM_MSK_MSKDAT4_Pos)                   /*!< BPWM_T::MSK: MSKDAT4 Mask              */
+
+#define BPWM_MSK_MSKDAT5_Pos             (5)                                               /*!< BPWM_T::MSK: MSKDAT5 Position          */
+#define BPWM_MSK_MSKDAT5_Msk             (0x1ul << BPWM_MSK_MSKDAT5_Pos)                   /*!< BPWM_T::MSK: MSKDAT5 Mask              */
+
+#define BPWM_MSK_MSKDATn_Pos             (0)                                               /*!< BPWM_T::MSK: MSKDATn Position          */
+#define BPWM_MSK_MSKDATn_Msk             (0x3ful << BPWM_MSK_MSKDATn_Pos)                  /*!< BPWM_T::MSK: MSKDATn Mask              */
+
+#define BPWM_POLCTL_PINV0_Pos            (0)                                               /*!< BPWM_T::POLCTL: PINV0 Position         */
+#define BPWM_POLCTL_PINV0_Msk            (0x1ul << BPWM_POLCTL_PINV0_Pos)                  /*!< BPWM_T::POLCTL: PINV0 Mask             */
+
+#define BPWM_POLCTL_PINV1_Pos            (1)                                               /*!< BPWM_T::POLCTL: PINV1 Position         */
+#define BPWM_POLCTL_PINV1_Msk            (0x1ul << BPWM_POLCTL_PINV1_Pos)                  /*!< BPWM_T::POLCTL: PINV1 Mask             */
+
+#define BPWM_POLCTL_PINV2_Pos            (2)                                               /*!< BPWM_T::POLCTL: PINV2 Position         */
+#define BPWM_POLCTL_PINV2_Msk            (0x1ul << BPWM_POLCTL_PINV2_Pos)                  /*!< BPWM_T::POLCTL: PINV2 Mask             */
+
+#define BPWM_POLCTL_PINV3_Pos            (3)                                               /*!< BPWM_T::POLCTL: PINV3 Position         */
+#define BPWM_POLCTL_PINV3_Msk            (0x1ul << BPWM_POLCTL_PINV3_Pos)                  /*!< BPWM_T::POLCTL: PINV3 Mask             */
+
+#define BPWM_POLCTL_PINV4_Pos            (4)                                               /*!< BPWM_T::POLCTL: PINV4 Position         */
+#define BPWM_POLCTL_PINV4_Msk            (0x1ul << BPWM_POLCTL_PINV4_Pos)                  /*!< BPWM_T::POLCTL: PINV4 Mask             */
+
+#define BPWM_POLCTL_PINV5_Pos            (5)                                               /*!< BPWM_T::POLCTL: PINV5 Position         */
+#define BPWM_POLCTL_PINV5_Msk            (0x1ul << BPWM_POLCTL_PINV5_Pos)                  /*!< BPWM_T::POLCTL: PINV5 Mask             */
+
+#define BPWM_POLCTL_PINVn_Pos            (0)                                               /*!< BPWM_T::POLCTL: PINVn Position         */
+#define BPWM_POLCTL_PINVn_Msk            (0x3ful << BPWM_POLCTL_PINVn_Pos)                 /*!< BPWM_T::POLCTL: PINVn Mask             */
+
+#define BPWM_POEN_POEN0_Pos              (0)                                               /*!< BPWM_T::POEN: POEN0 Position           */
+#define BPWM_POEN_POEN0_Msk              (0x1ul << BPWM_POEN_POEN0_Pos)                    /*!< BPWM_T::POEN: POEN0 Mask               */
+
+#define BPWM_POEN_POEN1_Pos              (1)                                               /*!< BPWM_T::POEN: POEN1 Position           */
+#define BPWM_POEN_POEN1_Msk              (0x1ul << BPWM_POEN_POEN1_Pos)                    /*!< BPWM_T::POEN: POEN1 Mask               */
+
+#define BPWM_POEN_POEN2_Pos              (2)                                               /*!< BPWM_T::POEN: POEN2 Position           */
+#define BPWM_POEN_POEN2_Msk              (0x1ul << BPWM_POEN_POEN2_Pos)                    /*!< BPWM_T::POEN: POEN2 Mask               */
+
+#define BPWM_POEN_POEN3_Pos              (3)                                               /*!< BPWM_T::POEN: POEN3 Position           */
+#define BPWM_POEN_POEN3_Msk              (0x1ul << BPWM_POEN_POEN3_Pos)                    /*!< BPWM_T::POEN: POEN3 Mask               */
+
+#define BPWM_POEN_POEN4_Pos              (4)                                               /*!< BPWM_T::POEN: POEN4 Position           */
+#define BPWM_POEN_POEN4_Msk              (0x1ul << BPWM_POEN_POEN4_Pos)                    /*!< BPWM_T::POEN: POEN4 Mask               */
+
+#define BPWM_POEN_POEN5_Pos              (5)                                               /*!< BPWM_T::POEN: POEN5 Position           */
+#define BPWM_POEN_POEN5_Msk              (0x1ul << BPWM_POEN_POEN5_Pos)                    /*!< BPWM_T::POEN: POEN5 Mask               */
+
+#define BPWM_POEN_POENn_Pos              (0)                                               /*!< BPWM_T::POEN: POENn Position           */
+#define BPWM_POEN_POENn_Msk              (0x3ful << BPWM_POEN_POENn_Pos)                   /*!< BPWM_T::POEN: POENn Mask               */
+
+#define BPWM_INTEN_ZIEN0_Pos             (0)                                               /*!< BPWM_T::INTEN: ZIEN0 Position          */
+#define BPWM_INTEN_ZIEN0_Msk             (0x1ul << BPWM_INTEN_ZIEN0_Pos)                   /*!< BPWM_T::INTEN: ZIEN0 Mask              */
+
+#define BPWM_INTEN_PIEN0_Pos             (8)                                               /*!< BPWM_T::INTEN: PIEN0 Position          */
+#define BPWM_INTEN_PIEN0_Msk             (0x1ul << BPWM_INTEN_PIEN0_Pos)                   /*!< BPWM_T::INTEN: PIEN0 Mask              */
+
+#define BPWM_INTEN_CMPUIEN0_Pos          (16)                                              /*!< BPWM_T::INTEN: CMPUIEN0 Position       */
+#define BPWM_INTEN_CMPUIEN0_Msk          (0x1ul << BPWM_INTEN_CMPUIEN0_Pos)                /*!< BPWM_T::INTEN: CMPUIEN0 Mask           */
+
+#define BPWM_INTEN_CMPUIEN1_Pos          (17)                                              /*!< BPWM_T::INTEN: CMPUIEN1 Position       */
+#define BPWM_INTEN_CMPUIEN1_Msk          (0x1ul << BPWM_INTEN_CMPUIEN1_Pos)                /*!< BPWM_T::INTEN: CMPUIEN1 Mask           */
+
+#define BPWM_INTEN_CMPUIEN2_Pos          (18)                                              /*!< BPWM_T::INTEN: CMPUIEN2 Position       */
+#define BPWM_INTEN_CMPUIEN2_Msk          (0x1ul << BPWM_INTEN_CMPUIEN2_Pos)                /*!< BPWM_T::INTEN: CMPUIEN2 Mask           */
+
+#define BPWM_INTEN_CMPUIEN3_Pos          (19)                                              /*!< BPWM_T::INTEN: CMPUIEN3 Position       */
+#define BPWM_INTEN_CMPUIEN3_Msk          (0x1ul << BPWM_INTEN_CMPUIEN3_Pos)                /*!< BPWM_T::INTEN: CMPUIEN3 Mask           */
+
+#define BPWM_INTEN_CMPUIEN4_Pos          (20)                                              /*!< BPWM_T::INTEN: CMPUIEN4 Position       */
+#define BPWM_INTEN_CMPUIEN4_Msk          (0x1ul << BPWM_INTEN_CMPUIEN4_Pos)                /*!< BPWM_T::INTEN: CMPUIEN4 Mask           */
+
+#define BPWM_INTEN_CMPUIEN5_Pos          (21)                                              /*!< BPWM_T::INTEN: CMPUIEN5 Position       */
+#define BPWM_INTEN_CMPUIEN5_Msk          (0x1ul << BPWM_INTEN_CMPUIEN5_Pos)                /*!< BPWM_T::INTEN: CMPUIEN5 Mask           */
+
+#define BPWM_INTEN_CMPUIENn_Pos          (16)                                              /*!< BPWM_T::INTEN: CMPUIENn Position       */
+#define BPWM_INTEN_CMPUIENn_Msk          (0x3ful << BPWM_INTEN_CMPUIENn_Pos)               /*!< BPWM_T::INTEN: CMPUIENn Mask           */
+
+#define BPWM_INTEN_CMPDIEN0_Pos          (24)                                              /*!< BPWM_T::INTEN: CMPDIEN0 Position       */
+#define BPWM_INTEN_CMPDIEN0_Msk          (0x1ul << BPWM_INTEN_CMPDIEN0_Pos)                /*!< BPWM_T::INTEN: CMPDIEN0 Mask           */
+
+#define BPWM_INTEN_CMPDIEN1_Pos          (25)                                              /*!< BPWM_T::INTEN: CMPDIEN1 Position       */
+#define BPWM_INTEN_CMPDIEN1_Msk          (0x1ul << BPWM_INTEN_CMPDIEN1_Pos)                /*!< BPWM_T::INTEN: CMPDIEN1 Mask           */
+
+#define BPWM_INTEN_CMPDIEN2_Pos          (26)                                              /*!< BPWM_T::INTEN: CMPDIEN2 Position       */
+#define BPWM_INTEN_CMPDIEN2_Msk          (0x1ul << BPWM_INTEN_CMPDIEN2_Pos)                /*!< BPWM_T::INTEN: CMPDIEN2 Mask           */
+
+#define BPWM_INTEN_CMPDIEN3_Pos          (27)                                              /*!< BPWM_T::INTEN: CMPDIEN3 Position       */
+#define BPWM_INTEN_CMPDIEN3_Msk          (0x1ul << BPWM_INTEN_CMPDIEN3_Pos)                /*!< BPWM_T::INTEN: CMPDIEN3 Mask           */
+
+#define BPWM_INTEN_CMPDIEN4_Pos          (28)                                              /*!< BPWM_T::INTEN: CMPDIEN4 Position       */
+#define BPWM_INTEN_CMPDIEN4_Msk          (0x1ul << BPWM_INTEN_CMPDIEN4_Pos)                /*!< BPWM_T::INTEN: CMPDIEN4 Mask           */
+
+#define BPWM_INTEN_CMPDIEN5_Pos          (29)                                              /*!< BPWM_T::INTEN: CMPDIEN5 Position       */
+#define BPWM_INTEN_CMPDIEN5_Msk          (0x1ul << BPWM_INTEN_CMPDIEN5_Pos)                /*!< BPWM_T::INTEN: CMPDIEN5 Mask           */
+
+#define BPWM_INTEN_CMPDIENn_Pos          (24)                                              /*!< BPWM_T::INTEN: CMPDIENn Position       */
+#define BPWM_INTEN_CMPDIENn_Msk          (0x3ful << BPWM_INTEN_CMPDIENn_Pos)               /*!< BPWM_T::INTEN: CMPDIENn Mask           */
+
+#define BPWM_INTSTS_ZIF0_Pos             (0)                                               /*!< BPWM_T::INTSTS: ZIF0 Position          */
+#define BPWM_INTSTS_ZIF0_Msk             (0x1ul << BPWM_INTSTS_ZIF0_Pos)                   /*!< BPWM_T::INTSTS: ZIF0 Mask              */
+
+#define BPWM_INTSTS_PIF0_Pos             (8)                                               /*!< BPWM_T::INTSTS: PIF0 Position          */
+#define BPWM_INTSTS_PIF0_Msk             (0x1ul << BPWM_INTSTS_PIF0_Pos)                   /*!< BPWM_T::INTSTS: PIF0 Mask              */
+
+#define BPWM_INTSTS_CMPUIF0_Pos          (16)                                              /*!< BPWM_T::INTSTS: CMPUIF0 Position       */
+#define BPWM_INTSTS_CMPUIF0_Msk          (0x1ul << BPWM_INTSTS_CMPUIF0_Pos)                /*!< BPWM_T::INTSTS: CMPUIF0 Mask           */
+
+#define BPWM_INTSTS_CMPUIF1_Pos          (17)                                              /*!< BPWM_T::INTSTS: CMPUIF1 Position       */
+#define BPWM_INTSTS_CMPUIF1_Msk          (0x1ul << BPWM_INTSTS_CMPUIF1_Pos)                /*!< BPWM_T::INTSTS: CMPUIF1 Mask           */
+
+#define BPWM_INTSTS_CMPUIF2_Pos          (18)                                              /*!< BPWM_T::INTSTS: CMPUIF2 Position       */
+#define BPWM_INTSTS_CMPUIF2_Msk          (0x1ul << BPWM_INTSTS_CMPUIF2_Pos)                /*!< BPWM_T::INTSTS: CMPUIF2 Mask           */
+
+#define BPWM_INTSTS_CMPUIF3_Pos          (19)                                              /*!< BPWM_T::INTSTS: CMPUIF3 Position       */
+#define BPWM_INTSTS_CMPUIF3_Msk          (0x1ul << BPWM_INTSTS_CMPUIF3_Pos)                /*!< BPWM_T::INTSTS: CMPUIF3 Mask           */
+
+#define BPWM_INTSTS_CMPUIF4_Pos          (20)                                              /*!< BPWM_T::INTSTS: CMPUIF4 Position       */
+#define BPWM_INTSTS_CMPUIF4_Msk          (0x1ul << BPWM_INTSTS_CMPUIF4_Pos)                /*!< BPWM_T::INTSTS: CMPUIF4 Mask           */
+
+#define BPWM_INTSTS_CMPUIF5_Pos          (21)                                              /*!< BPWM_T::INTSTS: CMPUIF5 Position       */
+#define BPWM_INTSTS_CMPUIF5_Msk          (0x1ul << BPWM_INTSTS_CMPUIF5_Pos)                /*!< BPWM_T::INTSTS: CMPUIF5 Mask           */
+
+#define BPWM_INTSTS_CMPUIFn_Pos          (16)                                              /*!< BPWM_T::INTSTS: CMPUIFn Position       */
+#define BPWM_INTSTS_CMPUIFn_Msk          (0x3ful << BPWM_INTSTS_CMPUIFn_Pos)               /*!< BPWM_T::INTSTS: CMPUIFn Mask           */
+
+#define BPWM_INTSTS_CMPDIF0_Pos          (24)                                              /*!< BPWM_T::INTSTS: CMPDIF0 Position       */
+#define BPWM_INTSTS_CMPDIF0_Msk          (0x1ul << BPWM_INTSTS_CMPDIF0_Pos)                /*!< BPWM_T::INTSTS: CMPDIF0 Mask           */
+
+#define BPWM_INTSTS_CMPDIF1_Pos          (25)                                              /*!< BPWM_T::INTSTS: CMPDIF1 Position       */
+#define BPWM_INTSTS_CMPDIF1_Msk          (0x1ul << BPWM_INTSTS_CMPDIF1_Pos)                /*!< BPWM_T::INTSTS: CMPDIF1 Mask           */
+
+#define BPWM_INTSTS_CMPDIF2_Pos          (26)                                              /*!< BPWM_T::INTSTS: CMPDIF2 Position       */
+#define BPWM_INTSTS_CMPDIF2_Msk          (0x1ul << BPWM_INTSTS_CMPDIF2_Pos)                /*!< BPWM_T::INTSTS: CMPDIF2 Mask           */
+
+#define BPWM_INTSTS_CMPDIF3_Pos          (27)                                              /*!< BPWM_T::INTSTS: CMPDIF3 Position       */
+#define BPWM_INTSTS_CMPDIF3_Msk          (0x1ul << BPWM_INTSTS_CMPDIF3_Pos)                /*!< BPWM_T::INTSTS: CMPDIF3 Mask           */
+
+#define BPWM_INTSTS_CMPDIF4_Pos          (28)                                              /*!< BPWM_T::INTSTS: CMPDIF4 Position       */
+#define BPWM_INTSTS_CMPDIF4_Msk          (0x1ul << BPWM_INTSTS_CMPDIF4_Pos)                /*!< BPWM_T::INTSTS: CMPDIF4 Mask           */
+
+#define BPWM_INTSTS_CMPDIF5_Pos          (29)                                              /*!< BPWM_T::INTSTS: CMPDIF5 Position       */
+#define BPWM_INTSTS_CMPDIF5_Msk          (0x1ul << BPWM_INTSTS_CMPDIF5_Pos)                /*!< BPWM_T::INTSTS: CMPDIF5 Mask           */
+
+#define BPWM_INTSTS_CMPDIFn_Pos          (24)                                              /*!< BPWM_T::INTSTS: CMPDIFn Position       */
+#define BPWM_INTSTS_CMPDIFn_Msk          (0x3ful << BPWM_INTSTS_CMPDIFn_Pos)               /*!< BPWM_T::INTSTS: CMPDIFn Mask           */
+
+#define BPWM_EADCTS0_TRGSEL0_Pos         (0)                                               /*!< BPWM_T::EADCTS0: TRGSEL0 Position      */
+#define BPWM_EADCTS0_TRGSEL0_Msk         (0xful << BPWM_EADCTS0_TRGSEL0_Pos)               /*!< BPWM_T::EADCTS0: TRGSEL0 Mask          */
+
+#define BPWM_EADCTS0_TRGEN0_Pos          (7)                                               /*!< BPWM_T::EADCTS0: TRGEN0 Position       */
+#define BPWM_EADCTS0_TRGEN0_Msk          (0x1ul << BPWM_EADCTS0_TRGEN0_Pos)                /*!< BPWM_T::EADCTS0: TRGEN0 Mask           */
+
+#define BPWM_EADCTS0_TRGSEL1_Pos         (8)                                               /*!< BPWM_T::EADCTS0: TRGSEL1 Position      */
+#define BPWM_EADCTS0_TRGSEL1_Msk         (0xful << BPWM_EADCTS0_TRGSEL1_Pos)               /*!< BPWM_T::EADCTS0: TRGSEL1 Mask          */
+
+#define BPWM_EADCTS0_TRGEN1_Pos          (15)                                              /*!< BPWM_T::EADCTS0: TRGEN1 Position       */
+#define BPWM_EADCTS0_TRGEN1_Msk          (0x1ul << BPWM_EADCTS0_TRGEN1_Pos)                /*!< BPWM_T::EADCTS0: TRGEN1 Mask           */
+
+#define BPWM_EADCTS0_TRGSEL2_Pos         (16)                                              /*!< BPWM_T::EADCTS0: TRGSEL2 Position      */
+#define BPWM_EADCTS0_TRGSEL2_Msk         (0xful << BPWM_EADCTS0_TRGSEL2_Pos)               /*!< BPWM_T::EADCTS0: TRGSEL2 Mask          */
+
+#define BPWM_EADCTS0_TRGEN2_Pos          (23)                                              /*!< BPWM_T::EADCTS0: TRGEN2 Position       */
+#define BPWM_EADCTS0_TRGEN2_Msk          (0x1ul << BPWM_EADCTS0_TRGEN2_Pos)                /*!< BPWM_T::EADCTS0: TRGEN2 Mask           */
+
+#define BPWM_EADCTS0_TRGSEL3_Pos         (24)                                              /*!< BPWM_T::EADCTS0: TRGSEL3 Position      */
+#define BPWM_EADCTS0_TRGSEL3_Msk         (0xful << BPWM_EADCTS0_TRGSEL3_Pos)               /*!< BPWM_T::EADCTS0: TRGSEL3 Mask          */
+
+#define BPWM_EADCTS0_TRGEN3_Pos          (31)                                              /*!< BPWM_T::EADCTS0: TRGEN3 Position       */
+#define BPWM_EADCTS0_TRGEN3_Msk          (0x1ul << BPWM_EADCTS0_TRGEN3_Pos)                /*!< BPWM_T::EADCTS0: TRGEN3 Mask           */
+
+#define BPWM_EADCTS1_TRGSEL4_Pos         (0)                                               /*!< BPWM_T::EADCTS1: TRGSEL4 Position      */
+#define BPWM_EADCTS1_TRGSEL4_Msk         (0xful << BPWM_EADCTS1_TRGSEL4_Pos)               /*!< BPWM_T::EADCTS1: TRGSEL4 Mask          */
+
+#define BPWM_EADCTS1_TRGEN4_Pos          (7)                                               /*!< BPWM_T::EADCTS1: TRGEN4 Position       */
+#define BPWM_EADCTS1_TRGEN4_Msk          (0x1ul << BPWM_EADCTS1_TRGEN4_Pos)                /*!< BPWM_T::EADCTS1: TRGEN4 Mask           */
+
+#define BPWM_EADCTS1_TRGSEL5_Pos         (8)                                               /*!< BPWM_T::EADCTS1: TRGSEL5 Position      */
+#define BPWM_EADCTS1_TRGSEL5_Msk         (0xful << BPWM_EADCTS1_TRGSEL5_Pos)               /*!< BPWM_T::EADCTS1: TRGSEL5 Mask          */
+
+#define BPWM_EADCTS1_TRGEN5_Pos          (15)                                              /*!< BPWM_T::EADCTS1: TRGEN5 Position       */
+#define BPWM_EADCTS1_TRGEN5_Msk          (0x1ul << BPWM_EADCTS1_TRGEN5_Pos)                /*!< BPWM_T::EADCTS1: TRGEN5 Mask           */
+
+#define BPWM_SSCTL_SSEN0_Pos             (0)                                               /*!< BPWM_T::SSCTL: SSEN0 Position          */
+#define BPWM_SSCTL_SSEN0_Msk             (0x1ul << BPWM_SSCTL_SSEN0_Pos)                   /*!< BPWM_T::SSCTL: SSEN0 Mask              */
+
+#define BPWM_SSCTL_SSRC_Pos              (8)                                               /*!< BPWM_T::SSCTL: SSRC Position           */
+#define BPWM_SSCTL_SSRC_Msk              (0x3ul << BPWM_SSCTL_SSRC_Pos)                    /*!< BPWM_T::SSCTL: SSRC Mask               */
+
+#define BPWM_SSTRG_CNTSEN_Pos            (0)                                               /*!< BPWM_T::SSTRG: CNTSEN Position         */
+#define BPWM_SSTRG_CNTSEN_Msk            (0x1ul << BPWM_SSTRG_CNTSEN_Pos)                  /*!< BPWM_T::SSTRG: CNTSEN Mask             */
+
+#define BPWM_STATUS_CNTMAX0_Pos          (0)                                               /*!< BPWM_T::STATUS: CNTMAX0 Position       */
+#define BPWM_STATUS_CNTMAX0_Msk          (0x1ul << BPWM_STATUS_CNTMAX0_Pos)                /*!< BPWM_T::STATUS: CNTMAX0 Mask           */
+
+#define BPWM_STATUS_EADCTRG0_Pos         (16)                                              /*!< BPWM_T::STATUS: EADCTRG0 Position      */
+#define BPWM_STATUS_EADCTRG0_Msk         (0x1ul << BPWM_STATUS_EADCTRG0_Pos)               /*!< BPWM_T::STATUS: EADCTRG0 Mask          */
+
+#define BPWM_STATUS_EADCTRG1_Pos         (17)                                              /*!< BPWM_T::STATUS: EADCTRG1 Position      */
+#define BPWM_STATUS_EADCTRG1_Msk         (0x1ul << BPWM_STATUS_EADCTRG1_Pos)               /*!< BPWM_T::STATUS: EADCTRG1 Mask          */
+
+#define BPWM_STATUS_EADCTRG2_Pos         (18)                                              /*!< BPWM_T::STATUS: EADCTRG2 Position      */
+#define BPWM_STATUS_EADCTRG2_Msk         (0x1ul << BPWM_STATUS_EADCTRG2_Pos)               /*!< BPWM_T::STATUS: EADCTRG2 Mask          */
+
+#define BPWM_STATUS_EADCTRG3_Pos         (19)                                              /*!< BPWM_T::STATUS: EADCTRG3 Position      */
+#define BPWM_STATUS_EADCTRG3_Msk         (0x1ul << BPWM_STATUS_EADCTRG3_Pos)               /*!< BPWM_T::STATUS: EADCTRG3 Mask          */
+
+#define BPWM_STATUS_EADCTRG4_Pos         (20)                                              /*!< BPWM_T::STATUS: EADCTRG4 Position      */
+#define BPWM_STATUS_EADCTRG4_Msk         (0x1ul << BPWM_STATUS_EADCTRG4_Pos)               /*!< BPWM_T::STATUS: EADCTRG4 Mask          */
+
+#define BPWM_STATUS_EADCTRG5_Pos         (21)                                              /*!< BPWM_T::STATUS: EADCTRG5 Position      */
+#define BPWM_STATUS_EADCTRG5_Msk         (0x1ul << BPWM_STATUS_EADCTRG5_Pos)               /*!< BPWM_T::STATUS: EADCTRG5 Mask          */
+
+#define BPWM_STATUS_EADCTRGn_Pos         (16)                                              /*!< BPWM_T::STATUS: EADCTRGn Position       */
+#define BPWM_STATUS_EADCTRGn_Msk         (0x3ful << BPWM_STATUS_EADCTRGn_Pos)               /*!< BPWM_T::STATUS: EADCTRGn Mask           */
+
+#define BPWM_CAPINEN_CAPINEN0_Pos        (0)                                               /*!< BPWM_T::CAPINEN: CAPINEN0 Position     */
+#define BPWM_CAPINEN_CAPINEN0_Msk        (0x1ul << BPWM_CAPINEN_CAPINEN0_Pos)              /*!< BPWM_T::CAPINEN: CAPINEN0 Mask         */
+
+#define BPWM_CAPINEN_CAPINEN1_Pos        (1)                                               /*!< BPWM_T::CAPINEN: CAPINEN1 Position     */
+#define BPWM_CAPINEN_CAPINEN1_Msk        (0x1ul << BPWM_CAPINEN_CAPINEN1_Pos)              /*!< BPWM_T::CAPINEN: CAPINEN1 Mask         */
+
+#define BPWM_CAPINEN_CAPINEN2_Pos        (2)                                               /*!< BPWM_T::CAPINEN: CAPINEN2 Position     */
+#define BPWM_CAPINEN_CAPINEN2_Msk        (0x1ul << BPWM_CAPINEN_CAPINEN2_Pos)              /*!< BPWM_T::CAPINEN: CAPINEN2 Mask         */
+
+#define BPWM_CAPINEN_CAPINEN3_Pos        (3)                                               /*!< BPWM_T::CAPINEN: CAPINEN3 Position     */
+#define BPWM_CAPINEN_CAPINEN3_Msk        (0x1ul << BPWM_CAPINEN_CAPINEN3_Pos)              /*!< BPWM_T::CAPINEN: CAPINEN3 Mask         */
+
+#define BPWM_CAPINEN_CAPINEN4_Pos        (4)                                               /*!< BPWM_T::CAPINEN: CAPINEN4 Position     */
+#define BPWM_CAPINEN_CAPINEN4_Msk        (0x1ul << BPWM_CAPINEN_CAPINEN4_Pos)              /*!< BPWM_T::CAPINEN: CAPINEN4 Mask         */
+
+#define BPWM_CAPINEN_CAPINEN5_Pos        (5)                                               /*!< BPWM_T::CAPINEN: CAPINEN5 Position     */
+#define BPWM_CAPINEN_CAPINEN5_Msk        (0x1ul << BPWM_CAPINEN_CAPINEN5_Pos)              /*!< BPWM_T::CAPINEN: CAPINEN5 Mask         */
+
+#define BPWM_CAPINEN_CAPINENn_Pos        (0)                                               /*!< BPWM_T::CAPINEN: CAPINENn Position     */
+#define BPWM_CAPINEN_CAPINENn_Msk        (0x3ful << BPWM_CAPINEN_CAPINENn_Pos)             /*!< BPWM_T::CAPINEN: CAPINENn Mask         */
+
+#define BPWM_CAPCTL_CAPEN0_Pos           (0)                                               /*!< BPWM_T::CAPCTL: CAPEN0 Position        */
+#define BPWM_CAPCTL_CAPEN0_Msk           (0x1ul << BPWM_CAPCTL_CAPEN0_Pos)                 /*!< BPWM_T::CAPCTL: CAPEN0 Mask            */
+
+#define BPWM_CAPCTL_CAPEN1_Pos           (1)                                               /*!< BPWM_T::CAPCTL: CAPEN1 Position        */
+#define BPWM_CAPCTL_CAPEN1_Msk           (0x1ul << BPWM_CAPCTL_CAPEN1_Pos)                 /*!< BPWM_T::CAPCTL: CAPEN1 Mask            */
+
+#define BPWM_CAPCTL_CAPEN2_Pos           (2)                                               /*!< BPWM_T::CAPCTL: CAPEN2 Position        */
+#define BPWM_CAPCTL_CAPEN2_Msk           (0x1ul << BPWM_CAPCTL_CAPEN2_Pos)                 /*!< BPWM_T::CAPCTL: CAPEN2 Mask            */
+
+#define BPWM_CAPCTL_CAPEN3_Pos           (3)                                               /*!< BPWM_T::CAPCTL: CAPEN3 Position        */
+#define BPWM_CAPCTL_CAPEN3_Msk           (0x1ul << BPWM_CAPCTL_CAPEN3_Pos)                 /*!< BPWM_T::CAPCTL: CAPEN3 Mask            */
+
+#define BPWM_CAPCTL_CAPEN4_Pos           (4)                                               /*!< BPWM_T::CAPCTL: CAPEN4 Position        */
+#define BPWM_CAPCTL_CAPEN4_Msk           (0x1ul << BPWM_CAPCTL_CAPEN4_Pos)                 /*!< BPWM_T::CAPCTL: CAPEN4 Mask            */
+
+#define BPWM_CAPCTL_CAPEN5_Pos           (5)                                               /*!< BPWM_T::CAPCTL: CAPEN5 Position        */
+#define BPWM_CAPCTL_CAPEN5_Msk           (0x1ul << BPWM_CAPCTL_CAPEN5_Pos)                 /*!< BPWM_T::CAPCTL: CAPEN5 Mask            */
+
+#define BPWM_CAPCTL_CAPENn_Pos           (0)                                               /*!< BPWM_T::CAPCTL: CAPENn Position        */
+#define BPWM_CAPCTL_CAPENn_Msk           (0x3ful << BPWM_CAPCTL_CAPENn_Pos)                /*!< BPWM_T::CAPCTL: CAPENn Mask            */
+
+#define BPWM_CAPCTL_CAPINV0_Pos          (8)                                               /*!< BPWM_T::CAPCTL: CAPINV0 Position       */
+#define BPWM_CAPCTL_CAPINV0_Msk          (0x1ul << BPWM_CAPCTL_CAPINV0_Pos)                /*!< BPWM_T::CAPCTL: CAPINV0 Mask           */
+
+#define BPWM_CAPCTL_CAPINV1_Pos          (9)                                               /*!< BPWM_T::CAPCTL: CAPINV1 Position       */
+#define BPWM_CAPCTL_CAPINV1_Msk          (0x1ul << BPWM_CAPCTL_CAPINV1_Pos)                /*!< BPWM_T::CAPCTL: CAPINV1 Mask           */
+
+#define BPWM_CAPCTL_CAPINV2_Pos          (10)                                              /*!< BPWM_T::CAPCTL: CAPINV2 Position       */
+#define BPWM_CAPCTL_CAPINV2_Msk          (0x1ul << BPWM_CAPCTL_CAPINV2_Pos)                /*!< BPWM_T::CAPCTL: CAPINV2 Mask           */
+
+#define BPWM_CAPCTL_CAPINV3_Pos          (11)                                              /*!< BPWM_T::CAPCTL: CAPINV3 Position       */
+#define BPWM_CAPCTL_CAPINV3_Msk          (0x1ul << BPWM_CAPCTL_CAPINV3_Pos)                /*!< BPWM_T::CAPCTL: CAPINV3 Mask           */
+
+#define BPWM_CAPCTL_CAPINV4_Pos          (12)                                              /*!< BPWM_T::CAPCTL: CAPINV4 Position       */
+#define BPWM_CAPCTL_CAPINV4_Msk          (0x1ul << BPWM_CAPCTL_CAPINV4_Pos)                /*!< BPWM_T::CAPCTL: CAPINV4 Mask           */
+
+#define BPWM_CAPCTL_CAPINV5_Pos          (13)                                              /*!< BPWM_T::CAPCTL: CAPINV5 Position       */
+#define BPWM_CAPCTL_CAPINV5_Msk          (0x1ul << BPWM_CAPCTL_CAPINV5_Pos)                /*!< BPWM_T::CAPCTL: CAPINV5 Mask           */
+
+#define BPWM_CAPCTL_CAPINVn_Pos          (8)                                               /*!< BPWM_T::CAPCTL: CAPINVn Position       */
+#define BPWM_CAPCTL_CAPINVn_Msk          (0x3ful << BPWM_CAPCTL_CAPINVn_Pos)               /*!< BPWM_T::CAPCTL: CAPINVn Mask           */
+
+#define BPWM_CAPCTL_RCRLDEN0_Pos         (16)                                              /*!< BPWM_T::CAPCTL: RCRLDEN0 Position      */
+#define BPWM_CAPCTL_RCRLDEN0_Msk         (0x1ul << BPWM_CAPCTL_RCRLDEN0_Pos)               /*!< BPWM_T::CAPCTL: RCRLDEN0 Mask          */
+
+#define BPWM_CAPCTL_RCRLDEN1_Pos         (17)                                              /*!< BPWM_T::CAPCTL: RCRLDEN1 Position      */
+#define BPWM_CAPCTL_RCRLDEN1_Msk         (0x1ul << BPWM_CAPCTL_RCRLDEN1_Pos)               /*!< BPWM_T::CAPCTL: RCRLDEN1 Mask          */
+
+#define BPWM_CAPCTL_RCRLDEN2_Pos         (18)                                              /*!< BPWM_T::CAPCTL: RCRLDEN2 Position      */
+#define BPWM_CAPCTL_RCRLDEN2_Msk         (0x1ul << BPWM_CAPCTL_RCRLDEN2_Pos)               /*!< BPWM_T::CAPCTL: RCRLDEN2 Mask          */
+
+#define BPWM_CAPCTL_RCRLDEN3_Pos         (19)                                              /*!< BPWM_T::CAPCTL: RCRLDEN3 Position      */
+#define BPWM_CAPCTL_RCRLDEN3_Msk         (0x1ul << BPWM_CAPCTL_RCRLDEN3_Pos)               /*!< BPWM_T::CAPCTL: RCRLDEN3 Mask          */
+
+#define BPWM_CAPCTL_RCRLDEN4_Pos         (20)                                              /*!< BPWM_T::CAPCTL: RCRLDEN4 Position      */
+#define BPWM_CAPCTL_RCRLDEN4_Msk         (0x1ul << BPWM_CAPCTL_RCRLDEN4_Pos)               /*!< BPWM_T::CAPCTL: RCRLDEN4 Mask          */
+
+#define BPWM_CAPCTL_RCRLDEN5_Pos         (21)                                              /*!< BPWM_T::CAPCTL: RCRLDEN5 Position      */
+#define BPWM_CAPCTL_RCRLDEN5_Msk         (0x1ul << BPWM_CAPCTL_RCRLDEN5_Pos)               /*!< BPWM_T::CAPCTL: RCRLDEN5 Mask          */
+
+#define BPWM_CAPCTL_RCRLDENn_Pos         (16)                                              /*!< BPWM_T::CAPCTL: RCRLDENn Position      */
+#define BPWM_CAPCTL_RCRLDENn_Msk         (0x3ful << BPWM_CAPCTL_RCRLDENn_Pos)              /*!< BPWM_T::CAPCTL: RCRLDENn Mask          */
+
+#define BPWM_CAPCTL_FCRLDEN0_Pos         (24)                                              /*!< BPWM_T::CAPCTL: FCRLDEN0 Position      */
+#define BPWM_CAPCTL_FCRLDEN0_Msk         (0x1ul << BPWM_CAPCTL_FCRLDEN0_Pos)               /*!< BPWM_T::CAPCTL: FCRLDEN0 Mask          */
+
+#define BPWM_CAPCTL_FCRLDEN1_Pos         (25)                                              /*!< BPWM_T::CAPCTL: FCRLDEN1 Position      */
+#define BPWM_CAPCTL_FCRLDEN1_Msk         (0x1ul << BPWM_CAPCTL_FCRLDEN1_Pos)               /*!< BPWM_T::CAPCTL: FCRLDEN1 Mask          */
+
+#define BPWM_CAPCTL_FCRLDEN2_Pos         (26)                                              /*!< BPWM_T::CAPCTL: FCRLDEN2 Position      */
+#define BPWM_CAPCTL_FCRLDEN2_Msk         (0x1ul << BPWM_CAPCTL_FCRLDEN2_Pos)               /*!< BPWM_T::CAPCTL: FCRLDEN2 Mask          */
+
+#define BPWM_CAPCTL_FCRLDEN3_Pos         (27)                                              /*!< BPWM_T::CAPCTL: FCRLDEN3 Position      */
+#define BPWM_CAPCTL_FCRLDEN3_Msk         (0x1ul << BPWM_CAPCTL_FCRLDEN3_Pos)               /*!< BPWM_T::CAPCTL: FCRLDEN3 Mask          */
+
+#define BPWM_CAPCTL_FCRLDEN4_Pos         (28)                                              /*!< BPWM_T::CAPCTL: FCRLDEN4 Position      */
+#define BPWM_CAPCTL_FCRLDEN4_Msk         (0x1ul << BPWM_CAPCTL_FCRLDEN4_Pos)               /*!< BPWM_T::CAPCTL: FCRLDEN4 Mask          */
+
+#define BPWM_CAPCTL_FCRLDEN5_Pos         (29)                                              /*!< BPWM_T::CAPCTL: FCRLDEN5 Position      */
+#define BPWM_CAPCTL_FCRLDEN5_Msk         (0x1ul << BPWM_CAPCTL_FCRLDEN5_Pos)               /*!< BPWM_T::CAPCTL: FCRLDEN5 Mask          */
+
+#define BPWM_CAPCTL_FCRLDENn_Pos         (24)                                              /*!< BPWM_T::CAPCTL: FCRLDENn Position      */
+#define BPWM_CAPCTL_FCRLDENn_Msk         (0x3ful << BPWM_CAPCTL_FCRLDENn_Pos)              /*!< BPWM_T::CAPCTL: FCRLDENn Mask          */
+
+#define BPWM_CAPSTS_CRIFOV0_Pos          (0)                                               /*!< BPWM_T::CAPSTS: CRIFOV0 Position       */
+#define BPWM_CAPSTS_CRIFOV0_Msk          (0x1ul << BPWM_CAPSTS_CRIFOV0_Pos)                /*!< BPWM_T::CAPSTS: CRIFOV0 Mask           */
+
+#define BPWM_CAPSTS_CRIFOV1_Pos          (1)                                               /*!< BPWM_T::CAPSTS: CRIFOV1 Position       */
+#define BPWM_CAPSTS_CRIFOV1_Msk          (0x1ul << BPWM_CAPSTS_CRIFOV1_Pos)                /*!< BPWM_T::CAPSTS: CRIFOV1 Mask           */
+
+#define BPWM_CAPSTS_CRIFOV2_Pos          (2)                                               /*!< BPWM_T::CAPSTS: CRIFOV2 Position       */
+#define BPWM_CAPSTS_CRIFOV2_Msk          (0x1ul << BPWM_CAPSTS_CRIFOV2_Pos)                /*!< BPWM_T::CAPSTS: CRIFOV2 Mask           */
+
+#define BPWM_CAPSTS_CRIFOV3_Pos          (3)                                               /*!< BPWM_T::CAPSTS: CRIFOV3 Position       */
+#define BPWM_CAPSTS_CRIFOV3_Msk          (0x1ul << BPWM_CAPSTS_CRIFOV3_Pos)                /*!< BPWM_T::CAPSTS: CRIFOV3 Mask           */
+
+#define BPWM_CAPSTS_CRIFOV4_Pos          (4)                                               /*!< BPWM_T::CAPSTS: CRIFOV4 Position       */
+#define BPWM_CAPSTS_CRIFOV4_Msk          (0x1ul << BPWM_CAPSTS_CRIFOV4_Pos)                /*!< BPWM_T::CAPSTS: CRIFOV4 Mask           */
+
+#define BPWM_CAPSTS_CRIFOV5_Pos          (5)                                               /*!< BPWM_T::CAPSTS: CRIFOV5 Position       */
+#define BPWM_CAPSTS_CRIFOV5_Msk          (0x1ul << BPWM_CAPSTS_CRIFOV5_Pos)                /*!< BPWM_T::CAPSTS: CRIFOV5 Mask           */
+
+#define BPWM_CAPSTS_CRIFOVn_Pos          (0)                                               /*!< BPWM_T::CAPSTS: CRIFOVn Position       */
+#define BPWM_CAPSTS_CRIFOVn_Msk          (0x3ful << BPWM_CAPSTS_CRIFOVn_Pos)               /*!< BPWM_T::CAPSTS: CRIFOVn Mask           */
+
+#define BPWM_CAPSTS_CFIFOV0_Pos          (8)                                               /*!< BPWM_T::CAPSTS: CFIFOV0 Position       */
+#define BPWM_CAPSTS_CFIFOV0_Msk          (0x1ul << BPWM_CAPSTS_CFIFOV0_Pos)                /*!< BPWM_T::CAPSTS: CFIFOV0 Mask           */
+
+#define BPWM_CAPSTS_CFIFOV1_Pos          (9)                                               /*!< BPWM_T::CAPSTS: CFIFOV1 Position       */
+#define BPWM_CAPSTS_CFIFOV1_Msk          (0x1ul << BPWM_CAPSTS_CFIFOV1_Pos)                /*!< BPWM_T::CAPSTS: CFIFOV1 Mask           */
+
+#define BPWM_CAPSTS_CFIFOV2_Pos          (10)                                              /*!< BPWM_T::CAPSTS: CFIFOV2 Position       */
+#define BPWM_CAPSTS_CFIFOV2_Msk          (0x1ul << BPWM_CAPSTS_CFIFOV2_Pos)                /*!< BPWM_T::CAPSTS: CFIFOV2 Mask           */
+
+#define BPWM_CAPSTS_CFIFOV3_Pos          (11)                                              /*!< BPWM_T::CAPSTS: CFIFOV3 Position       */
+#define BPWM_CAPSTS_CFIFOV3_Msk          (0x1ul << BPWM_CAPSTS_CFIFOV3_Pos)                /*!< BPWM_T::CAPSTS: CFIFOV3 Mask           */
+
+#define BPWM_CAPSTS_CFIFOV4_Pos          (12)                                              /*!< BPWM_T::CAPSTS: CFIFOV4 Position       */
+#define BPWM_CAPSTS_CFIFOV4_Msk          (0x1ul << BPWM_CAPSTS_CFIFOV4_Pos)                /*!< BPWM_T::CAPSTS: CFIFOV4 Mask           */
+
+#define BPWM_CAPSTS_CFIFOV5_Pos          (13)                                              /*!< BPWM_T::CAPSTS: CFIFOV5 Position       */
+#define BPWM_CAPSTS_CFIFOV5_Msk          (0x1ul << BPWM_CAPSTS_CFIFOV5_Pos)                /*!< BPWM_T::CAPSTS: CFIFOV5 Mask           */
+
+#define BPWM_CAPSTS_CFIFOVn_Pos          (8)                                               /*!< BPWM_T::CAPSTS: CFIFOVn Position       */
+#define BPWM_CAPSTS_CFIFOVn_Msk          (0x3ful << BPWM_CAPSTS_CFIFOVn_Pos)               /*!< BPWM_T::CAPSTS: CFIFOVn Mask           */
+
+#define BPWM_RCAPDAT0_RCAPDAT_Pos        (0)                                               /*!< BPWM_T::RCAPDAT0: RCAPDAT Position     */
+#define BPWM_RCAPDAT0_RCAPDAT_Msk        (0xfffful << BPWM_RCAPDAT0_RCAPDAT_Pos)           /*!< BPWM_T::RCAPDAT0: RCAPDAT Mask         */
+
+#define BPWM_FCAPDAT0_FCAPDAT_Pos        (0)                                               /*!< BPWM_T::FCAPDAT0: FCAPDAT Position     */
+#define BPWM_FCAPDAT0_FCAPDAT_Msk        (0xfffful << BPWM_FCAPDAT0_FCAPDAT_Pos)           /*!< BPWM_T::FCAPDAT0: FCAPDAT Mask         */
+
+#define BPWM_RCAPDAT1_RCAPDAT_Pos        (0)                                               /*!< BPWM_T::RCAPDAT1: RCAPDAT Position     */
+#define BPWM_RCAPDAT1_RCAPDAT_Msk        (0xfffful << BPWM_RCAPDAT1_RCAPDAT_Pos)           /*!< BPWM_T::RCAPDAT1: RCAPDAT Mask         */
+
+#define BPWM_FCAPDAT1_FCAPDAT_Pos        (0)                                               /*!< BPWM_T::FCAPDAT1: FCAPDAT Position     */
+#define BPWM_FCAPDAT1_FCAPDAT_Msk        (0xfffful << BPWM_FCAPDAT1_FCAPDAT_Pos)           /*!< BPWM_T::FCAPDAT1: FCAPDAT Mask         */
+
+#define BPWM_RCAPDAT2_RCAPDAT_Pos        (0)                                               /*!< BPWM_T::RCAPDAT2: RCAPDAT Position     */
+#define BPWM_RCAPDAT2_RCAPDAT_Msk        (0xfffful << BPWM_RCAPDAT2_RCAPDAT_Pos)           /*!< BPWM_T::RCAPDAT2: RCAPDAT Mask         */
+
+#define BPWM_FCAPDAT2_FCAPDAT_Pos        (0)                                               /*!< BPWM_T::FCAPDAT2: FCAPDAT Position     */
+#define BPWM_FCAPDAT2_FCAPDAT_Msk        (0xfffful << BPWM_FCAPDAT2_FCAPDAT_Pos)           /*!< BPWM_T::FCAPDAT2: FCAPDAT Mask         */
+
+#define BPWM_RCAPDAT3_RCAPDAT_Pos        (0)                                               /*!< BPWM_T::RCAPDAT3: RCAPDAT Position     */
+#define BPWM_RCAPDAT3_RCAPDAT_Msk        (0xfffful << BPWM_RCAPDAT3_RCAPDAT_Pos)           /*!< BPWM_T::RCAPDAT3: RCAPDAT Mask         */
+
+#define BPWM_FCAPDAT3_FCAPDAT_Pos        (0)                                               /*!< BPWM_T::FCAPDAT3: FCAPDAT Position     */
+#define BPWM_FCAPDAT3_FCAPDAT_Msk        (0xfffful << BPWM_FCAPDAT3_FCAPDAT_Pos)           /*!< BPWM_T::FCAPDAT3: FCAPDAT Mask         */
+
+#define BPWM_RCAPDAT4_RCAPDAT_Pos        (0)                                               /*!< BPWM_T::RCAPDAT4: RCAPDAT Position     */
+#define BPWM_RCAPDAT4_RCAPDAT_Msk        (0xfffful << BPWM_RCAPDAT4_RCAPDAT_Pos)           /*!< BPWM_T::RCAPDAT4: RCAPDAT Mask         */
+
+#define BPWM_FCAPDAT4_FCAPDAT_Pos        (0)                                               /*!< BPWM_T::FCAPDAT4: FCAPDAT Position     */
+#define BPWM_FCAPDAT4_FCAPDAT_Msk        (0xfffful << BPWM_FCAPDAT4_FCAPDAT_Pos)           /*!< BPWM_T::FCAPDAT4: FCAPDAT Mask         */
+
+#define BPWM_RCAPDAT5_RCAPDAT_Pos        (0)                                               /*!< BPWM_T::RCAPDAT5: RCAPDAT Position     */
+#define BPWM_RCAPDAT5_RCAPDAT_Msk        (0xfffful << BPWM_RCAPDAT5_RCAPDAT_Pos)           /*!< BPWM_T::RCAPDAT5: RCAPDAT Mask         */
+
+#define BPWM_FCAPDAT5_FCAPDAT_Pos        (0)                                               /*!< BPWM_T::FCAPDAT5: FCAPDAT Position     */
+#define BPWM_FCAPDAT5_FCAPDAT_Msk        (0xfffful << BPWM_FCAPDAT5_FCAPDAT_Pos)           /*!< BPWM_T::FCAPDAT5: FCAPDAT Mask         */
+
+#define BPWM_CAPIEN_CAPRIENn_Pos         (0)                                               /*!< BPWM_T::CAPIEN: CAPRIENn Position      */
+#define BPWM_CAPIEN_CAPRIENn_Msk         (0x3ful << BPWM_CAPIEN_CAPRIENn_Pos)              /*!< BPWM_T::CAPIEN: CAPRIENn Mask          */
+
+#define BPWM_CAPIEN_CAPFIENn_Pos         (8)                                               /*!< BPWM_T::CAPIEN: CAPFIENn Position      */
+#define BPWM_CAPIEN_CAPFIENn_Msk         (0x3ful << BPWM_CAPIEN_CAPFIENn_Pos)              /*!< BPWM_T::CAPIEN: CAPFIENn Mask          */
+
+#define BPWM_CAPIF_CAPRIF0_Pos           (0)                                               /*!< BPWM_T::CAPIF: CAPRIF0 Position        */
+#define BPWM_CAPIF_CAPRIF0_Msk           (0x1ul << BPWM_CAPIF_CAPRIF0_Pos)                 /*!< BPWM_T::CAPIF: CAPRIF0 Mask            */
+
+#define BPWM_CAPIF_CAPRIF1_Pos           (1)                                               /*!< BPWM_T::CAPIF: CAPRIF1 Position        */
+#define BPWM_CAPIF_CAPRIF1_Msk           (0x1ul << BPWM_CAPIF_CAPRIF1_Pos)                 /*!< BPWM_T::CAPIF: CAPRIF1 Mask            */
+
+#define BPWM_CAPIF_CAPRIF2_Pos           (2)                                               /*!< BPWM_T::CAPIF: CAPRIF2 Position        */
+#define BPWM_CAPIF_CAPRIF2_Msk           (0x1ul << BPWM_CAPIF_CAPRIF2_Pos)                 /*!< BPWM_T::CAPIF: CAPRIF2 Mask            */
+
+#define BPWM_CAPIF_CAPRIF3_Pos           (3)                                               /*!< BPWM_T::CAPIF: CAPRIF3 Position        */
+#define BPWM_CAPIF_CAPRIF3_Msk           (0x1ul << BPWM_CAPIF_CAPRIF3_Pos)                 /*!< BPWM_T::CAPIF: CAPRIF3 Mask            */
+
+#define BPWM_CAPIF_CAPRIF4_Pos           (4)                                               /*!< BPWM_T::CAPIF: CAPRIF4 Position        */
+#define BPWM_CAPIF_CAPRIF4_Msk           (0x1ul << BPWM_CAPIF_CAPRIF4_Pos)                 /*!< BPWM_T::CAPIF: CAPRIF4 Mask            */
+
+#define BPWM_CAPIF_CAPRIF5_Pos           (5)                                               /*!< BPWM_T::CAPIF: CAPRIF5 Position        */
+#define BPWM_CAPIF_CAPRIF5_Msk           (0x1ul << BPWM_CAPIF_CAPRIF5_Pos)                 /*!< BPWM_T::CAPIF: CAPRIF5 Mask            */
+
+#define BPWM_CAPIF_CAPRIFn_Pos           (0)                                               /*!< BPWM_T::CAPIF: CAPRIFn Position        */
+#define BPWM_CAPIF_CAPRIFn_Msk           (0x3ful << BPWM_CAPIF_CAPRIFn_Pos)                /*!< BPWM_T::CAPIF: CAPRIFn Mask            */
+
+#define BPWM_CAPIF_CAPFIF0_Pos           (8)                                               /*!< BPWM_T::CAPIF: CAPFIF0 Position        */
+#define BPWM_CAPIF_CAPFIF0_Msk           (0x1ul << BPWM_CAPIF_CAPFIF0_Pos)                 /*!< BPWM_T::CAPIF: CAPFIF0 Mask            */
+
+#define BPWM_CAPIF_CAPFIF1_Pos           (9)                                               /*!< BPWM_T::CAPIF: CAPFIF1 Position        */
+#define BPWM_CAPIF_CAPFIF1_Msk           (0x1ul << BPWM_CAPIF_CAPFIF1_Pos)                 /*!< BPWM_T::CAPIF: CAPFIF1 Mask            */
+
+#define BPWM_CAPIF_CAPFIF2_Pos           (10)                                              /*!< BPWM_T::CAPIF: CAPFIF2 Position        */
+#define BPWM_CAPIF_CAPFIF2_Msk           (0x1ul << BPWM_CAPIF_CAPFIF2_Pos)                 /*!< BPWM_T::CAPIF: CAPFIF2 Mask            */
+
+#define BPWM_CAPIF_CAPFIF3_Pos           (11)                                              /*!< BPWM_T::CAPIF: CAPFIF3 Position        */
+#define BPWM_CAPIF_CAPFIF3_Msk           (0x1ul << BPWM_CAPIF_CAPFIF3_Pos)                 /*!< BPWM_T::CAPIF: CAPFIF3 Mask            */
+
+#define BPWM_CAPIF_CAPFIF4_Pos           (12)                                              /*!< BPWM_T::CAPIF: CAPFIF4 Position        */
+#define BPWM_CAPIF_CAPFIF4_Msk           (0x1ul << BPWM_CAPIF_CAPFIF4_Pos)                 /*!< BPWM_T::CAPIF: CAPFIF4 Mask            */
+
+#define BPWM_CAPIF_CAPFIF5_Pos           (13)                                              /*!< BPWM_T::CAPIF: CAPFIF5 Position        */
+#define BPWM_CAPIF_CAPFIF5_Msk           (0x1ul << BPWM_CAPIF_CAPFIF5_Pos)                 /*!< BPWM_T::CAPIF: CAPFIF5 Mask            */
+
+#define BPWM_CAPIF_CAPFIFn_Pos           (8)                                               /*!< BPWM_T::CAPIF: CAPFIFn Position        */
+#define BPWM_CAPIF_CAPFIFn_Msk           (0x3ful << BPWM_CAPIF_CAPFIFn_Pos)                /*!< BPWM_T::CAPIF: CAPFIFn Mask            */
+
+#define BPWM_PBUF_PBUF_Pos               (0)                                               /*!< BPWM_T::PBUF: PBUF Position            */
+#define BPWM_PBUF_PBUF_Msk               (0xfffful << BPWM_PBUF_PBUF_Pos)                  /*!< BPWM_T::PBUF: PBUF Mask                */
+
+#define BPWM_CMPBUF0_CMPBUF_Pos          (0)                                               /*!< BPWM_T::CMPBUF0: CMPBUF Position       */
+#define BPWM_CMPBUF0_CMPBUF_Msk          (0xfffful << BPWM_CMPBUF0_CMPBUF_Pos)             /*!< BPWM_T::CMPBUF0: CMPBUF Mask           */
+
+#define BPWM_CMPBUF1_CMPBUF_Pos          (0)                                               /*!< BPWM_T::CMPBUF1: CMPBUF Position       */
+#define BPWM_CMPBUF1_CMPBUF_Msk          (0xfffful << BPWM_CMPBUF1_CMPBUF_Pos)             /*!< BPWM_T::CMPBUF1: CMPBUF Mask           */
+
+#define BPWM_CMPBUF2_CMPBUF_Pos          (0)                                               /*!< BPWM_T::CMPBUF2: CMPBUF Position       */
+#define BPWM_CMPBUF2_CMPBUF_Msk          (0xfffful << BPWM_CMPBUF2_CMPBUF_Pos)             /*!< BPWM_T::CMPBUF2: CMPBUF Mask           */
+
+#define BPWM_CMPBUF3_CMPBUF_Pos          (0)                                               /*!< BPWM_T::CMPBUF3: CMPBUF Position       */
+#define BPWM_CMPBUF3_CMPBUF_Msk          (0xfffful << BPWM_CMPBUF3_CMPBUF_Pos)             /*!< BPWM_T::CMPBUF3: CMPBUF Mask           */
+
+#define BPWM_CMPBUF4_CMPBUF_Pos          (0)                                               /*!< BPWM_T::CMPBUF4: CMPBUF Position       */
+#define BPWM_CMPBUF4_CMPBUF_Msk          (0xfffful << BPWM_CMPBUF4_CMPBUF_Pos)             /*!< BPWM_T::CMPBUF4: CMPBUF Mask           */
+
+#define BPWM_CMPBUF5_CMPBUF_Pos          (0)                                               /*!< BPWM_T::CMPBUF5: CMPBUF Position       */
+#define BPWM_CMPBUF5_CMPBUF_Msk          (0xfffful << BPWM_CMPBUF5_CMPBUF_Pos)             /*!< BPWM_T::CMPBUF5: CMPBUF Mask           */
+
+/**@}*/ /* BPWM_CONST */
+/**@}*/ /* end of BPWM register group */
+/**@}*/ /* end of REGISTER group */
+
+
+#endif /* __BPWM_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/can_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/can_reg.h
new file mode 100644
index 0000000000..76f5d2816c
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/can_reg.h
@@ -0,0 +1,790 @@
+/**************************************************************************//**
+ * @file     can_reg.h
+ * @version  V1.00
+ * @brief    CAN register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __CAN_REG_H__
+#define __CAN_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+
+/*---------------------- Controller Area Network Controller -------------------------*/
+/**
+    @addtogroup CAN Controller Area Network Controller(CAN)
+    Memory Mapped Structure for CAN Controller
+  @{
+*/
+
+
+typedef struct
+{
+
+
+
+    /**
+     * @var CAN_IF_T::CREQ
+     * Offset: 0x20, 0x80  IFn (Register Map Note 2) Command Request Registers
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[5:0]   |MessageNumber|Message Number
+     * |        |          |0x01-0x20: Valid Message Number, the Message Object in the Message
+     * |        |          |RAM is selected for data transfer.
+     * |        |          |0x00: Not a valid Message Number, interpreted as 0x20.
+     * |        |          |0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F.
+     * |[15]    |Busy      |Busy Flag
+     * |        |          |0 = Read/write action has finished.
+     * |        |          |1 = Writing to the IFn Command Request Register is in progress.
+     * |        |          |This bit can only be read by the software.
+     * @var CAN_IF_T::CMASK
+     * Offset: 0x24, 0x84  IFn Command Mask Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |DAT_B     |Access Data Bytes [7:4]
+     * |        |          |Write Operation:
+     * |        |          |0 = Data Bytes [7:4] unchanged.
+     * |        |          |1 = Transfer Data Bytes [7:4] to Message Object.
+     * |        |          |Read Operation:
+     * |        |          |0 = Data Bytes [7:4] unchanged.
+     * |        |          |1 = Transfer Data Bytes [7:4] to IFn Message Buffer Register.
+     * |[1]     |DAT_A     |Access Data Bytes [3:0]
+     * |        |          |Write Operation:
+     * |        |          |0 = Data Bytes [3:0] unchanged.
+     * |        |          |1 = Transfer Data Bytes [3:0] to Message Object.
+     * |        |          |Read Operation:
+     * |        |          |0 = Data Bytes [3:0] unchanged.
+     * |        |          |1 = Transfer Data Bytes [3:0] to IFn Message Buffer Register.
+     * |[2]     |TxRqst_NewDat|Access Transmission Request Bit When Write Operation
+     * |        |          |0 = TxRqst bit unchanged.
+     * |        |          |1 = Set TxRqst bit.
+     * |        |          |Note: If a transmission is requested by programming bit TxRqst/NewDat in the IFn Command Mask Register, bit TxRqst in the IFn Message Control Register will be ignored.
+     * |        |          |Access New Data Bit when Read Operation.
+     * |        |          |0 = NewDat bit remains unchanged.
+     * |        |          |1 = Clear NewDat bit in the Message Object.
+     * |        |          |Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat.
+     * |        |          |The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits.
+     * |[3]     |ClrIntPnd |Clear Interrupt Pending Bit
+     * |        |          |Write Operation:
+     * |        |          |When writing to a Message Object, this bit is ignored.
+     * |        |          |Read Operation:
+     * |        |          |0 = IntPnd bit (CAN_IFn_MCON[13]) remains unchanged.
+     * |        |          |1 = Clear IntPnd bit in the Message Object.
+     * |[4]     |Control   |Control Access Control Bits
+     * |        |          |Write Operation:
+     * |        |          |0 = Control Bits unchanged.
+     * |        |          |1 = Transfer Control Bits to Message Object.
+     * |        |          |Read Operation:
+     * |        |          |0 = Control Bits unchanged.
+     * |        |          |1 = Transfer Control Bits to IFn Message Buffer Register.
+     * |[5]     |Arb       |Access Arbitration Bits
+     * |        |          |Write Operation:
+     * |        |          |0 = Arbitration bits unchanged.
+     * |        |          |1 = Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_APB2[15]) to Message Object.
+     * |        |          |Read Operation:
+     * |        |          |0 = Arbitration bits unchanged.
+     * |        |          |1 = Transfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register.
+     * |[6]     |Mask      |Access Mask Bits
+     * |        |          |Write Operation:
+     * |        |          |0 = Mask bits unchanged.
+     * |        |          |1 = Transfer Identifier Mask + MDir + MXtd to Message Object.
+     * |        |          |Read Operation:
+     * |        |          |0 = Mask bits unchanged.
+     * |        |          |1 = Transfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register.
+     * |[7]     |WR_RD     |Write / Read Mode
+     * |        |          |0 = Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers.
+     * |        |          |1 = Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register.
+     * @var CAN_IF_T::MASK1
+     * Offset: 0x28, 0x88  IFn Mask 1 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |Msk[15:0] |Identifier Mask 15-0
+     * |        |          |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
+     * |        |          |1 = The corresponding identifier bit is used for acceptance filtering.
+     * @var CAN_IF_T::MASK2
+     * Offset: 0x2C, 0x8C  IFn Mask 2 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[12:0]  |Msk[28:16]|Identifier Mask 28-16
+     * |        |          |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
+     * |        |          |1 = The corresponding identifier bit is used for acceptance filtering.
+     * |[14]    |MDir      |Mask Message Direction
+     * |        |          |0 = The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering.
+     * |        |          |1 = The message direction bit (Dir) is used for acceptance filtering.
+     * |[15]    |MXtd      |Mask Extended Identifier
+     * |        |          |0 = The extended identifier bit (IDE) has no effect on the acceptance filtering.
+     * |        |          |1 = The extended identifier bit (IDE) is used for acceptance filtering.
+     * |        |          |Note: When 11-bit ("standard") Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2]).
+     * |        |          |For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered.
+     * @var CAN_IF_T::ARB1
+     * Offset: 0x30, 0x90  IFn Arbitration 1 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |ID[15:0]  |Message Identifier 15-0
+     * |        |          |ID28 - ID0, 29-bit Identifier ("Extended Frame").
+     * |        |          |ID28 - ID18, 11-bit Identifier ("Standard Frame")
+     * @var CAN_IF_T::ARB2
+     * Offset: 0x34, 0x94  IFn Arbitration 2 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[12:0]  |ID[28:16] |Message Identifier 28-16
+     * |        |          |ID28 - ID0, 29-bit Identifier ("Extended Frame").
+     * |        |          |ID28 - ID18, 11-bit Identifier ("Standard Frame")
+     * |[13]    |Dir       |Message Direction
+     * |        |          |0 = Direction is receive.
+     * |        |          |On TxRqst, a Remote Frame with the identifier of this Message Object is transmitted.
+     * |        |          |On reception of a Data Frame with matching identifier, that message is stored in this Message Object.
+     * |        |          |1 = Direction is transmit.
+     * |        |          |On TxRqst, the respective Message Object is transmitted as a Data Frame.
+     * |        |          |On reception of a Remote Frame with matching identifier, the TxRqst bit (CAN_IFn_CMASK[2]) of this Message Object is set (if RmtEn (CAN_IFn_MCON[9]) = one).
+     * |[14]    |Xtd       |Extended Identifier
+     * |        |          |0 = The 11-bit ("standard") Identifier will be used for this Message Object.
+     * |        |          |1 = The 29-bit ("extended") Identifier will be used for this Message Object.
+     * |[15]    |MsgVal    |Message Valid
+     * |        |          |0 = The Message Object is ignored by the Message Handler.
+     * |        |          |1 = The Message Object is configured and should be considered by the Message Handler.
+     * |        |          |Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]).
+     * |        |          |This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_APB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required.
+     * @var CAN_IF_T::MCON
+     * Offset: 0x38, 0x98  IFn Message Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |DLC       |Data Length Code
+     * |        |          |0-8: Data Frame has 0-8 data bytes.
+     * |        |          |9-15: Data Frame has 8 data bytes
+     * |        |          |Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes.
+     * |        |          |When the Message Handler stores a data frame, it will write the DLC to the value given by the received message.
+     * |        |          |Data 0: 1st data byte of a CAN Data Frame
+     * |        |          |Data 1: 2nd data byte of a CAN Data Frame
+     * |        |          |Data 2: 3rd data byte of a CAN Data Frame
+     * |        |          |Data 3: 4th data byte of a CAN Data Frame
+     * |        |          |Data 4: 5th data byte of a CAN Data Frame
+     * |        |          |Data 5: 6th data byte of a CAN Data Frame
+     * |        |          |Data 6: 7th data byte of a CAN Data Frame
+     * |        |          |Data 7 : 8th data byte of a CAN Data Frame
+     * |        |          |Note: The Data 0 Byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data 7 byte is the last.
+     * |        |          |When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object.
+     * |        |          |If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values.
+     * |[7]     |EoB       |End Of Buffer
+     * |        |          |0 = Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer.
+     * |        |          |1 = Single Message Object or last Message Object of a FIFO Buffer.
+     * |        |          |Note: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer.
+     * |        |          |For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one.
+     * |[8]     |TxRqst    |Transmit Request
+     * |        |          |0 = This Message Object is not waiting for transmission.
+     * |        |          |1 = The transmission of this Message Object is requested and is not yet done.
+     * |[9]     |RmtEn     |Remote Enable Control
+     * |        |          |0 = At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged.
+     * |        |          |1 = At the reception of a Remote Frame, TxRqst is set.
+     * |[10]    |RxIE      |Receive Interrupt Enable Control
+     * |        |          |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame.
+     * |        |          |1 = IntPnd will be set after a successful reception of a frame.
+     * |[11]    |TxIE      |Transmit Interrupt Enable Control
+     * |        |          |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame.
+     * |        |          |1 = IntPnd will be set after a successful transmission of a frame.
+     * |[12]    |UMask     |Use Acceptance Mask
+     * |        |          |0 = Mask ignored.
+     * |        |          |1 = Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering.
+     * |        |          |Note: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_APB2[15]) is set to one.
+     * |[13]    |IntPnd    |Interrupt Pending
+     * |        |          |0 = This message object is not the source of an interrupt.
+     * |        |          |1 = This message object is the source of an interrupt.
+     * |        |          |The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority.
+     * |[14]    |MsgLst    |Message Lost (only valid for Message Objects with direction = receive).
+     * |        |          |0 = No message lost since last time this bit was reset by the CPU.
+     * |        |          |1 = The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message.
+     * |[15]    |NewDat    |New Data
+     * |        |          |0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software.
+     * |        |          |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
+     * @var CAN_IF_T::DAT_A1
+     * Offset: 0x3C, 0x9C  IFn Data A1 Register (Register Map Note 3)
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |Data0     |Data Byte 0
+     * |        |          |1st data byte of a CAN Data Frame
+     * |[15:8]  |Data1     |Data Byte 1
+     * |        |          |2nd data byte of a CAN Data Frame
+     * @var CAN_IF_T::DAT_A2
+     * Offset: 0x40, 0xA0  IFn Data A2 Register (Register Map Note 3)
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |Data2     |Data Byte 2
+     * |        |          |3rd data byte of CAN Data Frame
+     * |[15:8]  |Data3     |Data Byte 3
+     * |        |          |4th data byte of CAN Data Frame
+     * @var CAN_IF_T::DAT_B1
+     * Offset: 0x44, 0xA4  IFn Data B1 Register (Register Map Note 3)
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |Data4     |Data Byte 4
+     * |        |          |5th data byte of CAN Data Frame
+     * |[15:8]  |Data5     |Data Byte 5
+     * |        |          |6th data byte of CAN Data Frame
+     * @var CAN_IF_T::DAT_B2
+     * Offset: 0x48, 0xA8  IFn Data B2 Register (Register Map Note 3)
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |Data6     |Data Byte 6
+     * |        |          |7th data byte of CAN Data Frame.
+     * |[15:8]  |Data7     |Data Byte 7
+     * |        |          |8th data byte of CAN Data Frame.
+     */
+
+    __IO uint32_t CREQ;          /* Offset: 0x20, 0x80  IFn (Register Map Note 2) Command Request Registers          */
+    __IO uint32_t CMASK;         /* Offset: 0x24, 0x84  IFn Command Mask Register                                    */
+    __IO uint32_t MASK1;         /* Offset: 0x28, 0x88  IFn Mask 1 Register                                          */
+    __IO uint32_t MASK2;         /* Offset: 0x2C, 0x8C  IFn Mask 2 Register                                          */
+    __IO uint32_t ARB1;          /* Offset: 0x30, 0x90  IFn Arbitration 1 Register                                   */
+    __IO uint32_t ARB2;          /* Offset: 0x34, 0x94  IFn Arbitration 2 Register                                   */
+    __IO uint32_t MCON;          /* Offset: 0x38, 0x98  IFn Message Control Register                                 */
+    __IO uint32_t DAT_A1;        /* Offset: 0x3C, 0x9C  IFn Data A1 Register (Register Map Note 3)                   */
+    __IO uint32_t DAT_A2;        /* Offset: 0x40, 0xA0  IFn Data A2 Register (Register Map Note 3)                   */
+    __IO uint32_t DAT_B1;        /* Offset: 0x44, 0xA4  IFn Data B1 Register (Register Map Note 3)                   */
+    __IO uint32_t DAT_B2;        /* Offset: 0x48, 0xA8  IFn Data B2 Register (Register Map Note 3)                   */
+    __I  uint32_t RESERVE0[13];
+
+} CAN_IF_T;
+
+
+
+
+typedef struct
+{
+
+
+
+    /**
+     * @var CAN_T::CON
+     * Offset: 0x00  Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |Init      |Init Initialization
+     * |        |          |0 = Normal Operation.
+     * |        |          |1 = Initialization is started.
+     * |[1]     |IE        |Module Interrupt Enable Control
+     * |        |          |0 = Disabled.
+     * |        |          |1 = Enabled.
+     * |[2]     |SIE       |Status Change Interrupt Enable Control
+     * |        |          |0 = Disabled - No Status Change Interrupt will be generated.
+     * |        |          |1 = Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected.
+     * |[3]     |EIE       |Error Interrupt Enable Control
+     * |        |          |0 = Disabled - No Error Status Interrupt will be generated.
+     * |        |          |1 = Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt.
+     * |[5]     |DAR       |Automatic Re-Transmission Disable Control
+     * |        |          |0 = Automatic Retransmission of disturbed messages enabled.
+     * |        |          |1 = Automatic Retransmission disabled.
+     * |[6]     |CCE       |Configuration Change Enable Control
+     * |        |          |0 = No write access to the Bit Timing Register.
+     * |        |          |1 = Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1).
+     * |[7]     |Test      |Test Mode Enable Control
+     * |        |          |0 = Normal Operation.
+     * |        |          |1 = Test Mode.
+     * @var CAN_T::STATUS
+     * Offset: 0x04  Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |LEC       |Last Error Code (Type Of The Last Error To Occur On The CAN Bus)
+     * |        |          |The LEC field holds a code, which indicates the type of the last error to occur on the CAN bus.
+     * |        |          |This field will be cleared to '0' when a message has been transferred (reception or transmission) without error.
+     * |        |          |The unused code '7' may be written by the CPU to check for updates.
+     * |        |          |The following table describes the error code.
+     * |[3]     |TxOK      |Transmitted A Message Successfully
+     * |        |          |0 = Since this bit was reset by the CPU, no message has been successfully transmitted.
+     * |        |          |This bit is never reset by the CAN Core.
+     * |        |          |1 = Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted.
+     * |[4]     |RxOK      |Received A Message Successfully
+     * |        |          |0 = No message has been successfully received since this bit was last reset by the CPU.
+     * |        |          |This bit is never reset by the CAN Core.
+     * |        |          |1 = A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering).
+     * |[5]     |EPass     |Error Passive (Read Only)
+     * |        |          |0 = The CAN Core is error active.
+     * |        |          |1 = The CAN Core is in the error passive state as defined in the CAN Specification.
+     * |[6]     |EWarn     |Error Warning Status (Read Only)
+     * |        |          |0 = Both error counters are below the error warning limit of 96.
+     * |        |          |1 = At least one of the error counters in the EML has reached the error warning limit of 96.
+     * |[7]     |BOff      |Bus-Off Status (Read Only)
+     * |        |          |0 = The CAN module is not in bus-off state.
+     * |        |          |1 = The CAN module is in bus-off state.
+     * @var CAN_T::ERR
+     * Offset: 0x08  Error Counter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |TEC       |Transmit Error Counter
+     * |        |          |Actual state of the Transmit Error Counter. Values between 0 and 255.
+     * |[14:8]  |REC       |Receive Error Counter
+     * |        |          |Actual state of the Receive Error Counter. Values between 0 and 127.
+     * |[15]    |RP        |Receive Error Passive
+     * |        |          |0 = The Receive Error Counter is below the error passive level.
+     * |        |          |1 = The Receive Error Counter has reached the error passive level as defined in the CAN Specification.
+     * @var CAN_T::BTIME
+     * Offset: 0x0C  Bit Timing Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[5:0]   |BRP       |Baud Rate Prescaler
+     * |        |          |0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta.
+     * |        |          |The bit time is built up from a multiple of this quanta.
+     * |        |          |Valid values for the Baud Rate Prescaler are [ 0 ... 63 ].
+     * |        |          |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
+     * |[7:6]   |SJW       |(Re)Synchronization Jump Width
+     * |        |          |0x0-0x3: Valid programmed values are [0 ... 3].
+     * |        |          |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
+     * |[11:8]  |TSeg1     |Time Segment Before The Sample Point Minus Sync_Seg
+     * |        |          |0x01-0x0F: valid values for TSeg1 are [1 ... 15].
+     * |        |          |The actual interpretation by the hardware of this value is such that one more than the value programmed is used.
+     * |[14:12] |TSeg2     |Time Segment After Sample Point
+     * |        |          |0x0-0x7: Valid values for TSeg2 are [0 ... 7].
+     * |        |          |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
+     * @var CAN_T::IIDR
+     * Offset: 0x10  Interrupt Identifier Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |IntId     |Interrupt Identifier (Indicates The Source Of The Interrupt)
+     * |        |          |If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order.
+     * |        |          |An interrupt remains pending until the application software has cleared it.
+     * |        |          |If IntId is different from 0x0000 and IE (CAN_IFn_MCON[1]) is set, the IRQ interrupt signal to the EIC is active.
+     * |        |          |The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.
+     * |        |          |The Status Interrupt has the highest priority.
+     * |        |          |Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number.
+     * |        |          |A message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13]).
+     * |        |          |The Status Interrupt is cleared by reading the Status Register.
+     * @var CAN_T::TEST
+     * Offset: 0x14  Test Register (Register Map Note 1)
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |Res       |Reserved
+     * |        |          |There are reserved bits.
+     * |        |          |These bits are always read as '0' and must always be written with '0'.
+     * |[2]     |Basic     |Basic Mode
+     * |        |          |0 = Basic Mode disabled.
+     * |        |          |1= IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer.
+     * |[3]     |Silent    |Silent Mode
+     * |        |          |0 = Normal operation.
+     * |        |          |1 = The module is in Silent Mode.
+     * |[4]     |LBack     |Loop Back Mode Enable Control
+     * |        |          |0 = Loop Back Mode is disabled.
+     * |        |          |1 = Loop Back Mode is enabled.
+     * |[6:5]   |Tx10      |Tx[1:0]: Control Of CAN_TX Pin
+     * |        |          |00 = Reset value, CAN_TX pin is controlled by the CAN Core.
+     * |        |          |01 = Sample Point can be monitored at CAN_TX pin.
+     * |        |          |10 = CAN_TX pin drives a dominant ('0') value.
+     * |        |          |11 = CAN_TX pin drives a recessive ('1') value.
+     * |[7]     |Rx        |Monitors The Actual Value Of CAN_RX Pin (Read Only)
+     * |        |          |0 = The CAN bus is dominant (CAN_RX = '0').
+     * |        |          |1 = The CAN bus is recessive (CAN_RX = '1').
+     * @var CAN_T::BRPE
+     * Offset: 0x18  Baud Rate Prescaler Extension Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |BRPE      |BRPE: Baud Rate Prescaler Extension
+     * |        |          |0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023.
+     * |        |          |The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used.
+     * @var CAN_T::IF
+     * Offset: 0x20~0xFC  CAN Interface Registers
+     * ---------------------------------------------------------------------------------------------------
+     * CAN interface structure. Refer to \ref CAN_IF_T for detail information.
+         *
+     * @var CAN_T::TXREQ1
+     * Offset: 0x100  Transmission Request Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |TxRqst[16:1]|Transmission Request Bits 16-1 (Of All Message Objects)
+     * |        |          |0 = This Message Object is not waiting for transmission.
+     * |        |          |1 = The transmission of this Message Object is requested and is not yet done.
+     * |        |          |These bits are read only.
+     * @var CAN_T::TXREQ2
+     * Offset: 0x104  Transmission Request Register 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |TxRqst[32:17]|Transmission Request Bits 32-17 (Of All Message Objects)
+     * |        |          |0 = This Message Object is not waiting for transmission.
+     * |        |          |1 = The transmission of this Message Object is requested and is not yet done.
+     * |        |          |These bits are read only.
+     * @var CAN_T::NDAT1
+     * Offset: 0x120  New Data Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |NewData[16:1]|New Data Bits 16-1 (Of All Message Objects)
+     * |        |          |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
+     * |        |          |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
+     * @var CAN_T::NDAT2
+     * Offset: 0x124  New Data Register 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |NewData[32:17]|New Data Bits 32-17 (Of All Message Objects)
+     * |        |          |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
+     * |        |          |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
+     * @var CAN_T::IPND1
+     * Offset: 0x140  Interrupt Pending Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |IntPnd[16:1]|Interrupt Pending Bits 16-1 (Of All Message Objects)
+     * |        |          |0 = This message object is not the source of an interrupt.
+     * |        |          |1 = This message object is the source of an interrupt.
+     * @var CAN_T::IPND2
+     * Offset: 0x144  Interrupt Pending Register 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |IntPnd[32:17]|Interrupt Pending Bits 32-17(Of All Message Objects)
+     * |        |          |0 = This message object is not the source of an interrupt.
+     * |        |          |1 = This message object is the source of an interrupt.
+     * @var CAN_T::MVLD1
+     * Offset: 0x160  Message Valid Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |MsgVal[16:1]|Message Valid Bits 16-1 (Of All Message Objects) (Read Only)
+     * |        |          |0 = This Message Object is ignored by the Message Handler.
+     * |        |          |1 = This Message Object is configured and should be considered by the Message Handler.
+     * |        |          |Ex.
+     * |        |          |CAN_MVLD1[0] means Message object No.1 is valid or not.
+     * |        |          |If CAN_MVLD1[0] is set, message object No.1 is configured.
+     * @var CAN_T::MVLD2
+     * Offset: 0x164  Message Valid Register 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |MsgVal[32:17]|Message Valid Bits 32-17 (Of All Message Objects) (Read Only)
+     * |        |          |0 = This Message Object is ignored by the Message Handler.
+     * |        |          |1 = This Message Object is configured and should be considered by the Message Handler.
+     * |        |          |Ex.CAN_MVLD2[15] means Message object No.32 is valid or not.
+     * |        |          |If CAN_MVLD2[15] is set, message object No.32 is configured.
+     * @var CAN_T::WU_EN
+     * Offset: 0x168  Wake-up Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WAKUP_EN  |Wake-Up Enable Control
+     * |        |          |0 = The wake-up function Disabled.
+     * |        |          |1 = The wake-up function Enabled.
+     * |        |          |Note: User can wake-up system when there is a falling edge in the CAN_Rx pin.
+     * @var CAN_T::WU_STATUS
+     * Offset: 0x16C  Wake-up Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WAKUP_STS |Wake-Up Status
+     * |        |          |0 = No wake-up event occurred.
+     * |        |          |1 = Wake-up event occurred.
+     * |        |          |Note: This bit can be cleared by writing '0'.
+     */
+
+    __IO uint32_t CON;           /* Offset: 0x00  Control Register                                                   */
+    __IO uint32_t STATUS;        /* Offset: 0x04  Status Register                                                    */
+    __I  uint32_t ERR;           /* Offset: 0x08  Error Counter Register                                             */
+    __IO uint32_t BTIME;         /* Offset: 0x0C  Bit Timing Register                                                */
+    __I  uint32_t IIDR;          /* Offset: 0x10  Interrupt Identifier Register                                      */
+    __IO uint32_t TEST;          /* Offset: 0x14  Test Register (Register Map Note 1)                                */
+    __IO uint32_t BRPE;          /* Offset: 0x18  Baud Rate Prescaler Extension Register                             */
+    __I  uint32_t RESERVE0[1];
+    __IO CAN_IF_T IF[2];         /* Offset: 0x20~0xFC  CAN Interface Registers                                       */
+    __I  uint32_t RESERVE1[8];
+    __I  uint32_t TXREQ1;        /* Offset: 0x100  Transmission Request Register 1                                   */
+    __I  uint32_t TXREQ2;        /* Offset: 0x104  Transmission Request Register 2                                   */
+    __I  uint32_t RESERVE3[6];
+    __I  uint32_t NDAT1;         /* Offset: 0x120  New Data Register 1                                               */
+    __I  uint32_t NDAT2;         /* Offset: 0x124  New Data Register 2                                               */
+    __I  uint32_t RESERVE4[6];
+    __I  uint32_t IPND1;         /* Offset: 0x140  Interrupt Pending Register 1                                      */
+    __I  uint32_t IPND2;         /* Offset: 0x144  Interrupt Pending Register 2                                      */
+    __I  uint32_t RESERVE5[6];
+    __I  uint32_t MVLD1;         /* Offset: 0x160  Message Valid Register 1                                          */
+    __I  uint32_t MVLD2;         /* Offset: 0x164  Message Valid Register 2                                          */
+    __IO uint32_t WU_EN;         /* Offset: 0x168  Wake-up Enable Register                                           */
+    __IO uint32_t WU_STATUS;     /* Offset: 0x16C  Wake-up Status Register                                           */
+
+} CAN_T;
+
+
+
+/**
+    @addtogroup CAN_CONST CAN Bit Field Definition
+    Constant Definitions for CAN Controller
+  @{
+*/
+/* CAN CON Bit Field Definitions */
+#define CAN_CON_TEST_Pos           7                                    /*!< CAN_T::CON: TEST Position */
+#define CAN_CON_TEST_Msk           (0x1ul << CAN_CON_TEST_Pos)          /*!< CAN_T::CON: TEST Mask     */
+
+#define CAN_CON_CCE_Pos            6                                    /*!< CAN_T::CON: CCE Position  */
+#define CAN_CON_CCE_Msk            (0x1ul << CAN_CON_CCE_Pos)           /*!< CAN_T::CON: CCE Mask      */
+
+#define CAN_CON_DAR_Pos            5                                    /*!< CAN_T::CON: DAR Position  */
+#define CAN_CON_DAR_Msk            (0x1ul << CAN_CON_DAR_Pos)           /*!< CAN_T::CON: DAR Mask      */
+
+#define CAN_CON_EIE_Pos            3                                    /*!< CAN_T::CON: EIE Position  */
+#define CAN_CON_EIE_Msk            (0x1ul << CAN_CON_EIE_Pos)           /*!< CAN_T::CON: EIE Mask      */
+
+#define CAN_CON_SIE_Pos            2                                    /*!< CAN_T::CON: SIE Position  */
+#define CAN_CON_SIE_Msk            (0x1ul << CAN_CON_SIE_Pos)           /*!< CAN_T::CON: SIE Mask      */
+
+#define CAN_CON_IE_Pos             1                                    /*!< CAN_T::CON: IE Position   */
+#define CAN_CON_IE_Msk             (0x1ul << CAN_CON_IE_Pos)            /*!< CAN_T::CON: IE Mask       */
+
+#define CAN_CON_INIT_Pos           0                                    /*!< CAN_T::CON: INIT Position */
+#define CAN_CON_INIT_Msk           (0x1ul << CAN_CON_INIT_Pos)          /*!< CAN_T::CON: INIT Mask     */
+
+/* CAN STATUS Bit Field Definitions */
+#define CAN_STATUS_BOFF_Pos        7                                    /*!< CAN_T::STATUS: BOFF Position  */
+#define CAN_STATUS_BOFF_Msk        (0x1ul << CAN_STATUS_BOFF_Pos)       /*!< CAN_T::STATUS: BOFF Mask      */
+
+#define CAN_STATUS_EWARN_Pos       6                                    /*!< CAN_T::STATUS: EWARN Position */
+#define CAN_STATUS_EWARN_Msk       (0x1ul << CAN_STATUS_EWARN_Pos)      /*!< CAN_T::STATUS: EWARN Mask     */
+
+#define CAN_STATUS_EPASS_Pos       5                                    /*!< CAN_T::STATUS: EPASS Position */
+#define CAN_STATUS_EPASS_Msk       (0x1ul << CAN_STATUS_EPASS_Pos)      /*!< CAN_T::STATUS: EPASS Mask     */
+
+#define CAN_STATUS_RXOK_Pos        4                                    /*!< CAN_T::STATUS: RXOK Position  */
+#define CAN_STATUS_RXOK_Msk        (0x1ul << CAN_STATUS_RXOK_Pos)       /*!< CAN_T::STATUS: RXOK Mask      */
+
+#define CAN_STATUS_TXOK_Pos        3                                    /*!< CAN_T::STATUS: TXOK Position  */
+#define CAN_STATUS_TXOK_Msk        (0x1ul << CAN_STATUS_TXOK_Pos)       /*!< CAN_T::STATUS: TXOK Mask      */
+
+#define CAN_STATUS_LEC_Pos         0                                    /*!< CAN_T::STATUS: LEC Position   */
+#define CAN_STATUS_LEC_Msk         (0x7ul << CAN_STATUS_LEC_Pos)        /*!< CAN_T::STATUS: LEC Mask       */
+
+/* CAN ERR Bit Field Definitions */
+#define CAN_ERR_RP_Pos             15                                   /*!< CAN_T::ERR: RP Position       */
+#define CAN_ERR_RP_Msk             (0x1ul << CAN_ERR_RP_Pos)            /*!< CAN_T::ERR: RP Mask           */
+
+#define CAN_ERR_REC_Pos            8                                    /*!< CAN_T::ERR: REC Position      */
+#define CAN_ERR_REC_Msk            (0x7Ful << CAN_ERR_REC_Pos)          /*!< CAN_T::ERR: REC Mask          */
+
+#define CAN_ERR_TEC_Pos            0                                    /*!< CAN_T::ERR: TEC Position      */
+#define CAN_ERR_TEC_Msk            (0xFFul << CAN_ERR_TEC_Pos)          /*!< CAN_T::ERR: TEC Mask          */
+
+/* CAN BTIME Bit Field Definitions */
+#define CAN_BTIME_TSEG2_Pos        12                                   /*!< CAN_T::BTIME: TSEG2 Position  */
+#define CAN_BTIME_TSEG2_Msk        (0x7ul << CAN_BTIME_TSEG2_Pos)       /*!< CAN_T::BTIME: TSEG2 Mask      */
+
+#define CAN_BTIME_TSEG1_Pos        8                                    /*!< CAN_T::BTIME: TSEG1 Position  */
+#define CAN_BTIME_TSEG1_Msk        (0xFul << CAN_BTIME_TSEG1_Pos)       /*!< CAN_T::BTIME: TSEG1 Mask      */
+
+#define CAN_BTIME_SJW_Pos          6                                    /*!< CAN_T::BTIME: SJW Position    */
+#define CAN_BTIME_SJW_Msk          (0x3ul << CAN_BTIME_SJW_Pos)         /*!< CAN_T::BTIME: SJW Mask        */
+
+#define CAN_BTIME_BRP_Pos          0                                    /*!< CAN_T::BTIME: BRP Position    */
+#define CAN_BTIME_BRP_Msk          (0x3Ful << CAN_BTIME_BRP_Pos)        /*!< CAN_T::BTIME: BRP Mask        */
+
+/* CAN IIDR Bit Field Definitions */
+#define CAN_IIDR_INTID_Pos         0                                    /*!< CAN_T::IIDR: INTID Position   */
+#define CAN_IIDR_INTID_Msk         (0xFFFFul << CAN_IIDR_INTID_Pos)     /*!< CAN_T::IIDR: INTID Mask       */
+
+/* CAN TEST Bit Field Definitions */
+#define CAN_TEST_RX_Pos            7                                    /*!< CAN_T::TEST: RX Position      */
+#define CAN_TEST_RX_Msk            (0x1ul << CAN_TEST_RX_Pos)           /*!< CAN_T::TEST: RX Mask          */
+
+#define CAN_TEST_TX_Pos            5                                    /*!< CAN_T::TEST: TX Position      */
+#define CAN_TEST_TX_Msk            (0x3ul << CAN_TEST_TX_Pos)           /*!< CAN_T::TEST: TX Mask          */
+
+#define CAN_TEST_LBACK_Pos         4                                    /*!< CAN_T::TEST: LBACK Position   */
+#define CAN_TEST_LBACK_Msk         (0x1ul << CAN_TEST_LBACK_Pos)        /*!< CAN_T::TEST: LBACK Mask       */
+
+#define CAN_TEST_SILENT_Pos        3                                    /*!< CAN_T::TEST: Silent Position  */
+#define CAN_TEST_SILENT_Msk        (0x1ul << CAN_TEST_SILENT_Pos)       /*!< CAN_T::TEST: Silent Mask      */
+
+#define CAN_TEST_BASIC_Pos         2                                    /*!< CAN_T::TEST: Basic Position   */
+#define CAN_TEST_BASIC_Msk         (0x1ul << CAN_TEST_BASIC_Pos)        /*!< CAN_T::TEST: Basic Mask       */
+
+/* CAN BPRE Bit Field Definitions */
+#define CAN_BRPE_BRPE_Pos          0                                    /*!< CAN_T::BRPE: BRPE Position    */
+#define CAN_BRPE_BRPE_Msk          (0xFul << CAN_BRPE_BRPE_Pos)         /*!< CAN_T::BRPE: BRPE Mask        */
+
+/* CAN IFn_CREQ Bit Field Definitions */
+#define CAN_IF_CREQ_BUSY_Pos       15                                     /*!< CAN_IF_T::CREQ: BUSY Position */
+#define CAN_IF_CREQ_BUSY_Msk       (0x1ul << CAN_IF_CREQ_BUSY_Pos)        /*!< CAN_IF_T::CREQ: BUSY Mask     */
+
+#define CAN_IF_CREQ_MSGNUM_Pos     0                                      /*!< CAN_IF_T::CREQ: MSGNUM Position */
+#define CAN_IF_CREQ_MSGNUM_Msk     (0x3Ful << CAN_IF_CREQ_MSGNUM_Pos)     /*!< CAN_IF_T::CREQ: MSGNUM Mask     */
+
+/* CAN IFn_CMASK Bit Field Definitions */
+#define CAN_IF_CMASK_WRRD_Pos      7                                      /*!< CAN_IF_T::CMASK: WRRD Position */
+#define CAN_IF_CMASK_WRRD_Msk      (0x1ul << CAN_IF_CMASK_WRRD_Pos)       /*!< CAN_IF_T::CMASK: WRRD Mask     */
+
+#define CAN_IF_CMASK_MASK_Pos      6                                      /*!< CAN_IF_T::CMASK: MASK Position */
+#define CAN_IF_CMASK_MASK_Msk      (0x1ul << CAN_IF_CMASK_MASK_Pos)       /*!< CAN_IF_T::CMASK: MASK Mask     */
+
+#define CAN_IF_CMASK_ARB_Pos       5                                      /*!< CAN_IF_T::CMASK: ARB Position  */
+#define CAN_IF_CMASK_ARB_Msk       (0x1ul << CAN_IF_CMASK_ARB_Pos)        /*!< CAN_IF_T::CMASK: ARB Mask      */
+
+#define CAN_IF_CMASK_CONTROL_Pos   4                                     /*!< CAN_IF_T::CMASK: CONTROL Position */
+#define CAN_IF_CMASK_CONTROL_Msk   (0x1ul << CAN_IF_CMASK_CONTROL_Pos)   /*!< CAN_IF_T::CMASK: CONTROL Mask */
+
+#define CAN_IF_CMASK_CLRINTPND_Pos 3                                       /*!< CAN_IF_T::CMASK: CLRINTPND Position */
+#define CAN_IF_CMASK_CLRINTPND_Msk (0x1ul << CAN_IF_CMASK_CLRINTPND_Pos)   /*!< CAN_IF_T::CMASK: CLRINTPND Mask */
+
+#define CAN_IF_CMASK_TXRQSTNEWDAT_Pos 2                                         /*!< CAN_IF_T::CMASK: TXRQSTNEWDAT Position */
+#define CAN_IF_CMASK_TXRQSTNEWDAT_Msk (0x1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos)  /*!< CAN_IF_T::CMASK: TXRQSTNEWDAT Mask     */
+
+#define CAN_IF_CMASK_DATAA_Pos     1                                    /*!< CAN_IF_T::CMASK: DATAA Position */
+#define CAN_IF_CMASK_DATAA_Msk     (0x1ul << CAN_IF_CMASK_DATAA_Pos)    /*!< CAN_IF_T::CMASK: DATAA Mask     */
+
+#define CAN_IF_CMASK_DATAB_Pos     0                                    /*!< CAN_IF_T::CMASK: DATAB Position */
+#define CAN_IF_CMASK_DATAB_Msk     (0x1ul << CAN_IF_CMASK_DATAB_Pos)    /*!< CAN_IF_T::CMASK: DATAB Mask     */
+
+/* CAN IFn_MASK1 Bit Field Definitions */
+#define CAN_IF_MASK1_MSK_Pos       0                                    /*!< CAN_IF_T::MASK1: MSK Position   */
+#define CAN_IF_MASK1_MSK_Msk       (0xFFul << CAN_IF_MASK1_MSK_Pos)     /*!< CAN_IF_T::MASK1: MSK Mask       */
+
+/* CAN IFn_MASK2 Bit Field Definitions */
+#define CAN_IF_MASK2_MXTD_Pos      15                                   /*!< CAN_IF_T::MASK2: MXTD Position */
+#define CAN_IF_MASK2_MXTD_Msk      (0x1ul << CAN_IF_MASK2_MXTD_Pos)     /*!< CAN_IF_T::MASK2: MXTD Mask     */
+
+#define CAN_IF_MASK2_MDIR_Pos      14                                   /*!< CAN_IF_T::MASK2: MDIR Position */
+#define CAN_IF_MASK2_MDIR_Msk      (0x1ul << CAN_IF_MASK2_MDIR_Pos)     /*!< CAN_IF_T::MASK2: MDIR Mask     */
+
+#define CAN_IF_MASK2_MSK_Pos       0                                    /*!< CAN_IF_T::MASK2: MSK Position */
+#define CAN_IF_MASK2_MSK_Msk       (0x1FFul << CAN_IF_MASK2_MSK_Pos)    /*!< CAN_IF_T::MASK2: MSK Mask     */
+
+/* CAN IFn_ARB1 Bit Field Definitions */
+#define CAN_IF_ARB1_ID_Pos         0                                    /*!< CAN_IF_T::ARB1: ID Position   */
+#define CAN_IF_ARB1_ID_Msk         (0xFFFFul << CAN_IF_ARB1_ID_Pos)     /*!< CAN_IF_T::ARB1: ID Mask       */
+
+/* CAN IFn_ARB2 Bit Field Definitions */
+#define CAN_IF_ARB2_MSGVAL_Pos     15                                   /*!< CAN_IF_T::ARB2: MSGVAL Position */
+#define CAN_IF_ARB2_MSGVAL_Msk     (0x1ul << CAN_IF_ARB2_MSGVAL_Pos)    /*!< CAN_IF_T::ARB2: MSGVAL Mask     */
+
+#define CAN_IF_ARB2_XTD_Pos        14                                   /*!< CAN_IF_T::ARB2: XTD Position    */
+#define CAN_IF_ARB2_XTD_Msk        (0x1ul << CAN_IF_ARB2_XTD_Pos)       /*!< CAN_IF_T::ARB2: XTD Mask        */
+
+#define CAN_IF_ARB2_DIR_Pos        13                                   /*!< CAN_IF_T::ARB2: DIR Position    */
+#define CAN_IF_ARB2_DIR_Msk        (0x1ul << CAN_IF_ARB2_DIR_Pos)       /*!< CAN_IF_T::ARB2: DIR Mask        */
+
+#define CAN_IF_ARB2_ID_Pos         0                                    /*!< CAN_IF_T::ARB2: ID Position     */
+#define CAN_IF_ARB2_ID_Msk         (0x1FFFul << CAN_IF_ARB2_ID_Pos)     /*!< CAN_IF_T::ARB2: ID Mask         */
+
+/* CAN IFn_MCON Bit Field Definitions */
+#define CAN_IF_MCON_NEWDAT_Pos     15                                   /*!< CAN_IF_T::MCON: NEWDAT Position */
+#define CAN_IF_MCON_NEWDAT_Msk     (0x1ul << CAN_IF_MCON_NEWDAT_Pos)    /*!< CAN_IF_T::MCON: NEWDAT Mask     */
+
+#define CAN_IF_MCON_MSGLST_Pos     14                                   /*!< CAN_IF_T::MCON: MSGLST Position */
+#define CAN_IF_MCON_MSGLST_Msk     (0x1ul << CAN_IF_MCON_MSGLST_Pos)    /*!< CAN_IF_T::MCON: MSGLST Mask     */
+
+#define CAN_IF_MCON_INTPND_Pos     13                                   /*!< CAN_IF_T::MCON: INTPND Position */
+#define CAN_IF_MCON_INTPND_Msk     (0x1ul << CAN_IF_MCON_INTPND_Pos)    /*!< CAN_IF_T::MCON: INTPND Mask     */
+
+#define CAN_IF_MCON_UMASK_Pos      12                                   /*!< CAN_IF_T::MCON: UMASK Position  */
+#define CAN_IF_MCON_UMASK_Msk      (0x1ul << CAN_IF_MCON_UMASK_Pos)     /*!< CAN_IF_T::MCON: UMASK Mask      */
+
+#define CAN_IF_MCON_TXIE_Pos       11                                   /*!< CAN_IF_T::MCON: TXIE Position   */
+#define CAN_IF_MCON_TXIE_Msk       (0x1ul << CAN_IF_MCON_TXIE_Pos)      /*!< CAN_IF_T::MCON: TXIE Mask       */
+
+#define CAN_IF_MCON_RXIE_Pos       10                                   /*!< CAN_IF_T::MCON: RXIE Position   */
+#define CAN_IF_MCON_RXIE_Msk       (0x1ul << CAN_IF_MCON_RXIE_Pos)      /*!< CAN_IF_T::MCON: RXIE Mask       */
+
+#define CAN_IF_MCON_RMTEN_Pos      9                                    /*!< CAN_IF_T::MCON: RMTEN Position  */
+#define CAN_IF_MCON_RMTEN_Msk      (0x1ul << CAN_IF_MCON_RMTEN_Pos)     /*!< CAN_IF_T::MCON: RMTEN Mask      */
+
+#define CAN_IF_MCON_TXRQST_Pos     8                                    /*!< CAN_IF_T::MCON: TXRQST Position */
+#define CAN_IF_MCON_TXRQST_Msk     (0x1ul << CAN_IF_MCON_TXRQST_Pos)    /*!< CAN_IF_T::MCON: TXRQST Mask     */
+
+#define CAN_IF_MCON_EOB_Pos        7                                    /*!< CAN_IF_T::MCON: EOB Position    */
+#define CAN_IF_MCON_EOB_Msk        (0x1ul << CAN_IF_MCON_EOB_Pos)       /*!< CAN_IF_T::MCON: EOB Mask        */
+
+#define CAN_IF_MCON_DLC_Pos        0                                    /*!< CAN_IF_T::MCON: DLC Position    */
+#define CAN_IF_MCON_DLC_Msk        (0xFul << CAN_IF_MCON_DLC_Pos)       /*!< CAN_IF_T::MCON: DLC Mask        */
+
+/* CAN IFn_DATA_A1 Bit Field Definitions */
+#define CAN_IF_DAT_A1_DATA1_Pos    8                                    /*!< CAN_IF_T::DATAA1: DATA1 Position */
+#define CAN_IF_DAT_A1_DATA1_Msk    (0xFFul << CAN_IF_DAT_A1_DATA1_Pos)  /*!< CAN_IF_T::DATAA1: DATA1 Mask     */
+
+#define CAN_IF_DAT_A1_DATA0_Pos    0                                    /*!< CAN_IF_T::DATAA1: DATA0 Position */
+#define CAN_IF_DAT_A1_DATA0_Msk    (0xFFul << CAN_IF_DAT_A1_DATA0_Pos)  /*!< CAN_IF_T::DATAA1: DATA0 Mask     */
+
+/* CAN IFn_DATA_A2 Bit Field Definitions */
+#define CAN_IF_DAT_A2_DATA3_Pos    8                                    /*!< CAN_IF_T::DATAA1: DATA3 Position */
+#define CAN_IF_DAT_A2_DATA3_Msk    (0xFFul << CAN_IF_DAT_A2_DATA3_Pos)  /*!< CAN_IF_T::DATAA1: DATA3 Mask     */
+
+#define CAN_IF_DAT_A2_DATA2_Pos    0                                    /*!< CAN_IF_T::DATAA1: DATA2 Position */
+#define CAN_IF_DAT_A2_DATA2_Msk    (0xFFul << CAN_IF_DAT_A2_DATA2_Pos)  /*!< CAN_IF_T::DATAA1: DATA2 Mask     */
+
+/* CAN IFn_DATA_B1 Bit Field Definitions */
+#define CAN_IF_DAT_B1_DATA5_Pos    8                                    /*!< CAN_IF_T::DATAB1: DATA5 Position */
+#define CAN_IF_DAT_B1_DATA5_Msk    (0xFFul << CAN_IF_DAT_B1_DATA5_Pos)  /*!< CAN_IF_T::DATAB1: DATA5 Mask */
+
+#define CAN_IF_DAT_B1_DATA4_Pos    0                                    /*!< CAN_IF_T::DATAB1: DATA4 Position */
+#define CAN_IF_DAT_B1_DATA4_Msk    (0xFFul << CAN_IF_DAT_B1_DATA4_Pos)  /*!< CAN_IF_T::DATAB1: DATA4 Mask */
+
+/* CAN IFn_DATA_B2 Bit Field Definitions */
+#define CAN_IF_DAT_B2_DATA7_Pos    8                                    /*!< CAN_IF_T::DATAB2: DATA7 Position */
+#define CAN_IF_DAT_B2_DATA7_Msk    (0xFFul << CAN_IF_DAT_B2_DATA7_Pos)  /*!< CAN_IF_T::DATAB2: DATA7 Mask     */
+
+#define CAN_IF_DAT_B2_DATA6_Pos    0                                    /*!< CAN_IF_T::DATAB2: DATA6 Position */
+#define CAN_IF_DAT_B2_DATA6_Msk    (0xFFul << CAN_IF_DAT_B2_DATA6_Pos)  /*!< CAN_IF_T::DATAB2: DATA6 Mask     */
+
+/* CAN IFn_TXRQST1 Bit Field Definitions */
+#define CAN_TXRQST1_TXRQST_Pos  0                                        /*!< CAN_T::TXRQST1: TXRQST Position */
+#define CAN_TXRQST1_TXRQST_Msk  (0xFFFFul << CAN_TXRQST1_TXRQST_Pos)  /*!< CAN_T::TXRQST1: TXRQST Mask     */
+
+/* CAN IFn_TXRQST2 Bit Field Definitions */
+#define CAN_TXRQST2_TXRQST_Pos  0                                        /*!< CAN_T::TXRQST2: TXRQST Position  */
+#define CAN_TXRQST2_TXRQST_Msk  (0xFFFFul << CAN_TXRQST2_TXRQST_Pos)  /*!< CAN_T::TXRQST2: TXRQST Mask      */
+
+/* CAN IFn_NDAT1 Bit Field Definitions */
+#define CAN_NDAT1_NEWDATA_Pos   0                                        /*!< CAN_T::NDAT1: NEWDATA Position */
+#define CAN_NDAT1_NEWDATA_Msk   (0xFFFFul << CAN_NDAT1_NEWDATA_Pos)   /*!< CAN_T::NDAT1: NEWDATA Mask     */
+
+/* CAN IFn_NDAT2 Bit Field Definitions */
+#define CAN_NDAT2_NEWDATA_Pos   0                                        /*!< CAN_T::NDAT2: NEWDATA Position */
+#define CAN_NDAT2_NEWDATA_Msk   (0xFFFFul << CAN_NDAT2_NEWDATA_Pos)   /*!< CAN_T::NDAT2: NEWDATA Mask     */
+
+/* CAN IFn_IPND1 Bit Field Definitions */
+#define CAN_IPND1_INTPND_Pos   0                                         /*!< CAN_T::IPND1: INTPND Position */
+#define CAN_IPND1_INTPND_Msk   (0xFFFFul << CAN_IPND1_INTPND_Pos)     /*!< CAN_T::IPND1: INTPND Mask     */
+
+/* CAN IFn_IPND2 Bit Field Definitions */
+#define CAN_IPND2_INTPND_Pos   0                                         /*!< CAN_T::IPND2: INTPND Position */
+#define CAN_IPND2_INTPND_Msk   (0xFFFFul << CAN_IPND2_INTPND_Pos)     /*!< CAN_T::IPND2: INTPND Mask     */
+
+/* CAN IFn_MVLD1 Bit Field Definitions */
+#define CAN_MVLD1_MSGVAL_Pos   0                                         /*!< CAN_T::MVLD1: MSGVAL Position */
+#define CAN_MVLD1_MSGVAL_Msk   (0xFFFFul << CAN_MVLD1_MSGVAL_Pos)     /*!< CAN_T::MVLD1: MSGVAL Mask     */
+
+/* CAN IFn_MVLD2 Bit Field Definitions */
+#define CAN_MVLD2_MSGVAL_Pos   0                                         /*!< CAN_T::MVLD2: MSGVAL Position */
+#define CAN_MVLD2_MSGVAL_Msk   (0xFFFFul << CAN_MVLD2_MSGVAL_Pos)     /*!< CAN_T::MVLD2: MSGVAL Mask     */
+
+/* CAN WUEN Bit Field Definitions */
+#define CAN_WU_EN_WAKUP_EN_Pos     0                                         /*!< CAN_T::WU_EN: WAKUP_EN Position */
+#define CAN_WU_EN_WAKUP_EN_Msk    (0x1ul << CAN_WU_EN_WAKUP_EN_Pos)           /*!< CAN_T::WU_EN: WAKUP_EN Mask     */
+
+/* CAN WUSTATUS Bit Field Definitions */
+#define CAN_WU_STATUS_WAKUP_STS_Pos     0                                      /*!< CAN_T::WU_STATUS: WAKUP_STS Position */
+#define CAN_WU_STATUS_WAKUP_STS_Msk    (0x1ul << CAN_WU_STATUS_WAKUP_STS_Pos)   /*!< CAN_T::WU_STATUS: WAKUP_STS Mask     */
+
+
+/**@}*/ /* CAN_CONST */
+/**@}*/ /* end of CAN register group */
+/**@}*/ /* end of REGISTER group */
+
+
+#endif /* __CAN_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/clk_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/clk_reg.h
new file mode 100644
index 0000000000..34a3eb82e6
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/clk_reg.h
@@ -0,0 +1,1815 @@
+/**************************************************************************//**
+ * @file     clk_reg.h
+ * @version  V1.00
+ * @brief    CLK register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __CLK_REG_H__
+#define __CLK_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+
+/*---------------------- System Clock Controller -------------------------*/
+/**
+    @addtogroup CLK System Clock Controller(CLK)
+    Memory Mapped Structure for CLK Controller
+  @{
+*/
+
+typedef struct
+{
+
+    /**
+     * @var CLK_T::PWRCTL
+     * Offset: 0x00  System Power-down Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |HXTEN     |HXT Enable Bit (Write Protect)
+     * |        |          |0 = 4~24 MHz external high speed crystal (HXT) Disabled.
+     * |        |          |1 = 4~24 MHz external high speed crystal (HXT) Enabled.
+     * |        |          |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note2: HXT cannot be disabled and HXTEN will always read as 1 if HCLK clock source is selected from HXT or PLL (clock source from HXT).
+     * |[1]     |LXTEN     |LXT Enable Bit (Write Protect)
+     * |        |          |0 = 32.768 kHz external low speed crystal (extLXT) Disabled.
+     * |        |          |1 = 32.768 kHz external low speed crystal (extLXT) Enabled.
+     * |        |          |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note2: LXT cannot be disabled and LXTEN will always read as 1 if HCLK clock source is selected from LXT when the LXT clock source is selected as extLXT by setting C32KS(RTC_LXTCTL[7]) to 1.
+     * |[2]     |HIRCEN    |HIRC Enable Bit (Write Protect)
+     * |        |          |The HCLK default clock source is from HIRC and this bit default value is 1.
+     * |        |          |0 = 12 MHz internal high speed RC oscillator (HIRC) Disabled.
+     * |        |          |1 = 12 MHz internal high speed RC oscillator (HIRC) Enabled.
+     * |        |          |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note2: HIRC cannot be disabled and HIRCEN will always read as 1 if HCLK clock source is selected from HIRC or PLL (clock source from HIRC).
+     * |[3]     |LIRCEN    |LIRC Enable Bit (Write Protect)
+     * |        |          |0 = 32 kHz internal low speed RC oscillator (LIRC) Disabled.
+     * |        |          |1 = 32 kHz internal low speed RC oscillator (LIRC) Enabled.
+     * |        |          |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note2: LIRC cannot be disabled and LIRCEN will always read as 1 if HCLK clock source is selected from LIRC.
+     * |        |          |Note3: If CWDTEN(CONFIG[31,4:3]) is set to 111, LIRC clock can be enabled or disabled by setting LIRCEN(CLK_PWRCTL[3]).
+     * |        |          |If CWDTEN(CONFIG0[31,4:3]) is not set to 111, LIRC cannot be disabled in normal mode and LIRCEN will always read as 1
+     * |        |          |In Power-down mode, LIRC clock is controlled by LIRCEN(CLK_PWRCTL[3]) and CWDTPDEN (CONFIG0[30]) setting.
+     * |[5]     |PDWKIEN   |Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)
+     * |        |          |0 = Power-down mode wake-up interrupt Disabled.
+     * |        |          |1 = Power-down mode wake-up interrupt Enabled.
+     * |        |          |Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high, after resume from Power-down mode.
+     * |        |          |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[6]     |PDWKIF    |Power-down Mode Wake-up Interrupt Status
+     * |        |          |Set by Power-down wake-up event, it indicates that resume from Power-down mode.
+     * |        |          |The flag is set if the EINT7~0, GPIO, UART0~5, USBH, USBD, OTG, CAN0, BOD, ACMP, WDT, EWDT, SDH0, TIMER, I2C0~2, USCI0~1, RTC, TAMPER and CLKD wake-up occurred.
+     * |        |          |Note1: Write 1 to clear the bit to 0.
+     * |        |          |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
+     * |[7]     |PDEN      |System Power-down Enable (Write Protect)
+     * |        |          |When this bit is set to 1, Power-down mode is enabled and the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.
+     * |        |          |When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down.
+     * |        |          |In Power-down mode, HXT, HIRC, HIRC48, PLL and system clock will be disabled and ignored the clock source selection.
+     * |        |          |The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT, LIRC or MIRC.
+     * |        |          |0 = Chip operating normally or chip in idle mode because of WFI command.
+     * |        |          |1 = Chip waits CPU sleep command WFI and then enters Power-down mode.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[11:10] |HXTGAIN   |HXT Gain Control Bit (Write Protect)
+     * |        |          |Gain control is used to enlarge the gain of crystal to make sure crystal work normally.
+     * |        |          |If gain control is enabled, crystal will consume more power than gain control off.
+     * |        |          |00 = HXT frequency is lower than from 8 MHz.
+     * |        |          |01 = HXT frequency is from 8 MHz to 12 MHz.
+     * |        |          |10 = HXT frequency is from 12 MHz to 16 MHz.
+     * |        |          |11 = HXT frequency is higher than 16 MHz.
+     * |        |          |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |[12]    |HXTSELTYP |HXT Crystal Type Select Bit (Write Protect)
+     * |        |          |0 = Select INV type.
+     * |        |          |1 = Select GM type.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[13]    |HXTTBEN   |HXT Crystal TURBO Mode (Write Protect)
+     * |        |          |0 = HXT Crystal TURBO mode disabled.
+     * |        |          |1 = HXT Crystal TURBO mode enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[18]    |HIRC48EN  |HIRC48 Enable Bit (Write Protect)
+     * |        |          |0 = 48 MHz internal high speed RC oscillator (HIRC48) Disabled.
+     * |        |          |1 = 48 MHz internal high speed RC oscillator (HIRC48) Enabled.
+     * |        |          |Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note 2: HIRC48 cannot be disabled and HIRC48EN will always read as 1 if HCLK clock source is selected from HIRC48.
+     * |[20]    |MIRC1P2MEN|MIRC1P2M Enable Bit (Write Protect)
+     * |        |          |0 = 1.2 MHz internal medium speed RC oscillator (MIRC1P2M) Disabled.
+     * |        |          |1 = 1.2 MHz internal medium speed RC oscillator (MIRC1P2M) Enabled.
+     * |        |          |Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note 2: This clock source only for LCD use.
+     * |[21]    |MIRCEN    |MIRC Enable Bit (Write Protect)
+     * |        |          |0 = 4 MHz internal medium speed RC oscillator (MIRC) Disabled.
+     * |        |          |1 = 4 MHz internal medium speed RC oscillator (MIRC) Enabled.
+     * |        |          |Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note 2: MIRC cannot be disabled and MIRC will always read as 1 if HCLK clock source is selected from MIRC.
+     * @var CLK_T::AHBCLK
+     * Offset: 0x04  AHB Devices Clock Enable Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PDMA0CKEN |PDMA0 Controller Clock Enable Bit (Secure)
+     * |        |          |0 = PDMA0 peripheral clock Disabled.
+     * |        |          |1 = PDMA0 peripheral clock Enabled.
+     * |[1]     |PDMA1CKEN |PDMA1 Controller Clock Enable Bit
+     * |        |          |0 = PDMA1 peripheral clock Disabled.
+     * |        |          |1 = PDMA1 peripheral clock Enabled.
+     * |[2]     |ISPCKEN   |Flash ISP Controller Clock Enable Bit
+     * |        |          |0 = Flash ISP peripheral clock Disabled.
+     * |        |          |1 = Flash ISP peripheral clock Enabled.
+     * |[3]     |EBICKEN   |EBI Controller Clock Enable Bit
+     * |        |          |0 = EBI peripheral clock Disabled.
+     * |        |          |1 = EBI peripheral clock Enabled.
+     * |[4]     |EXSTCKEN  |External System Tick Clock Enable Bit
+     * |        |          |0 = External System tick clock Disabled.
+     * |        |          |1 = External System tick clock Enabled.
+     * |[6]     |SDH0CKEN  |SDHOST0 Controller Clock Enable Bit
+     * |        |          |0 = SDHOST0 peripheral clock Disabled.
+     * |        |          |1 = SDHOST0 peripheral clock Enabled.
+     * |[7]     |CRCCKEN   |CRC Generator Controller Clock Enable Bit
+     * |        |          |0 = CRC peripheral clock Disabled.
+     * |        |          |1 = CRC peripheral clock Enabled.
+     * |[12]    |CRPTCKEN  |Cryptographic Accelerator Clock Enable Bit
+     * |        |          |0 = Cryptographic Accelerator clock Disabled.
+     * |        |          |1 = Cryptographic Accelerator clock Enabled.
+     * |[13]    |KSCKEN    |Key Store Clock Enable Bit
+     * |        |          |0 = Key store clock Disabled.
+     * |        |          |1 = Key store clock Enabled.
+     * |[14]    |TRACECKEN |Trace Clock Enable Bit
+     * |        |          |0 = Trace clock Disabled.
+     * |        |          |1 = Trace clock Enabled.
+     * |[15]    |FMCIDLE   |Flash Memory Controller Clock Enable Bit in IDLE Mode
+     * |        |          |0 = FMC clock Disabled when chip is under IDLE mode.
+     * |        |          |1 = FMC clock Enabled when chip is under IDLE mode.
+     * |[16]    |USBHCKEN  |USB HOST 1.1 Controller Clock Enable Bit
+     * |        |          |0 = USB HOST 1.1 peripheral clock Disabled.
+     * |        |          |1 = USB HOST 1.1 peripheral clock Enabled.
+     * |[20]    |SRAM0CKEN |SRAM Bank0 Controller Clock Enable Bit
+     * |        |          |0 = SRAM bank0 clock Disabled.
+     * |        |          |1 = SRAM bank0 clock Enabled.
+     * |[21]    |SRAM1CKEN |SRAM Bank1 Controller Clock Enable Bit
+     * |        |          |0 = SRAM bank1 clock Disabled.
+     * |        |          |1 = SRAM bank1 clock Enabled.
+     * |[22]    |SRAM2CKEN |SRAM Bank2 Controller Clock Enable Bit
+     * |        |          |0 = SRAM bank2 clock Disabled.
+     * |        |          |1 = SRAM bank2 clock Enabled.
+     * |[24]    |GPACKEN   |GPIOA Clock Enable Bit
+     * |        |          |0 = GPIOA port clock Disabled.
+     * |        |          |1 = GPIOA port clock Enabled.
+     * |[25]    |GPBCKEN   |GPIOB Clock Enable Bit
+     * |        |          |0 = GPIOB port clock Disabled.
+     * |        |          |1 = GPIOB port clock Enabled.
+     * |[26]    |GPCCKEN   |GPIOC Clock Enable Bit
+     * |        |          |0 = GPIOC port clock Disabled.
+     * |        |          |1 = GPIOC port clock Enabled.
+     * |[27]    |GPDCKEN   |GPIOD Clock Enable Bit
+     * |        |          |0 = GPIOD port clock Disabled.
+     * |        |          |1 = GPIOD port clock Enabled.
+     * |[28]    |GPECKEN   |GPIOE Clock Enable Bit
+     * |        |          |0 = GPIOE port clock Disabled.
+     * |        |          |1 = GPIOE port clock Enabled.
+     * |[29]    |GPFCKEN   |GPIOF Clock Enable Bit
+     * |        |          |0 = GPIOF port clock Disabled.
+     * |        |          |1 = GPIOF port clock Enabled.
+     * |[30]    |GPGCKEN   |GPIOG Clock Enable Bit
+     * |        |          |0 = GPIOG port clock Disabled.
+     * |        |          |1 = GPIOG port clock Enabled.
+     * |[31]    |GPHCKEN   |GPIOH Clock Enable Bit
+     * |        |          |0 = GPIOH port clock Disabled.
+     * |        |          |1 = GPIOH port clock Enabled.
+     * @var CLK_T::APBCLK0
+     * Offset: 0x08  APB Devices Clock Enable Control Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WDTCKEN   |Watchdog Timer Clock Enable Bit (Write Protect)
+     * |        |          |0 = Watchdog timer and Windows watchdog timer clock Disabled.
+     * |        |          |1 = Watchdog timer and Windows watchdog timer clock Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[1]     |RTCCKEN   |Real-time-clock APB Interface Clock Enable Bit
+     * |        |          |This bit is used to control the RTC APB clock only.
+     * |        |          |The RTC peripheral clock source is selected from RTCCKSEL(RTC_LXTCTL[7]).
+     * |        |          |It can be selected to 32.768 kHz external low speed crystal (LXT) or 32 kHz internal low speed RC oscillator (LIRC).
+     * |        |          |0 = RTC clock Disabled.
+     * |        |          |1 = RTC clock Enabled.
+     * |[2]     |TMR0CKEN  |Timer0 Clock Enable Bit
+     * |        |          |0 = Timer0 clock Disabled.
+     * |        |          |1 = Timer0 clock Enabled.
+     * |[3]     |TMR1CKEN  |Timer1 Clock Enable Bit
+     * |        |          |0 = Timer1 clock Disabled.
+     * |        |          |1 = Timer1 clock Enabled.
+     * |[4]     |TMR2CKEN  |Timer2 Clock Enable Bit
+     * |        |          |0 = Timer2 clock Disabled.
+     * |        |          |1 = Timer2 clock Enabled.
+     * |[5]     |TMR3CKEN  |Timer3 Clock Enable Bit
+     * |        |          |0 = Timer3 clock Disabled.
+     * |        |          |1 = Timer3 clock Enabled.
+     * |[6]     |CLKOCKEN  |CLKO Clock Enable Bit
+     * |        |          |0 = CLKO clock Disabled.
+     * |        |          |1 = CLKO clock Enabled.
+     * |[7]     |ACMP01CKEN|Analog Comparator 0/1 Clock Enable Bit
+     * |        |          |0 = Analog comparator 0/1 clock Disabled.
+     * |        |          |1 = Analog comparator 0/1 clock Enabled.
+     * |[8]     |I2C0CKEN  |I2C0 Clock Enable Bit
+     * |        |          |0 = I2C0 clock Disabled.
+     * |        |          |1 = I2C0 clock Enabled.
+     * |[9]     |I2C1CKEN  |I2C1 Clock Enable Bit
+     * |        |          |0 = I2C1 clock Disabled.
+     * |        |          |1 = I2C1 clock Enabled.
+     * |[10]    |I2C2CKEN  |I2C2 Clock Enable Bit
+     * |        |          |0 = I2C2 clock Disabled.
+     * |        |          |1 = I2C2 clock Enabled.
+     * |[12]    |QSPI0CKEN |QSPI0 Clock Enable Bit
+     * |        |          |0 = QSPI0 clock Disabled.
+     * |        |          |1 = QSPI0 clock Enabled.
+     * |[13]    |SPI0CKEN  |SPI0 Clock Enable Bit
+     * |        |          |0 = SPI0 clock Disabled.
+     * |        |          |1 = SPI0 clock Enabled.
+     * |[14]    |SPI1CKEN  |SPI1 Clock Enable Bit
+     * |        |          |0 = SPI1 clock Disabled.
+     * |        |          |1 = SPI1 clock Enabled.
+     * |[15]    |SPI2CKEN  |SPI2 Clock Enable Bit
+     * |        |          |0 = SPI2 clock Disabled.
+     * |        |          |1 = SPI2 clock Enabled.
+     * |[16]    |UART0CKEN |UART0 Clock Enable Bit
+     * |        |          |0 = UART0 clock Disabled.
+     * |        |          |1 = UART0 clock Enabled.
+     * |[17]    |UART1CKEN |UART1 Clock Enable Bit
+     * |        |          |0 = UART1 clock Disabled.
+     * |        |          |1 = UART1 clock Enabled.
+     * |[18]    |UART2CKEN |UART2 Clock Enable Bit
+     * |        |          |0 = UART2 clock Disabled.
+     * |        |          |1 = UART2 clock Enabled.
+     * |[19]    |UART3CKEN |UART3 Clock Enable Bit
+     * |        |          |0 = UART3 clock Disabled.
+     * |        |          |1 = UART3 clock Enabled.
+     * |[20]    |UART4CKEN |UART4 Clock Enable Bit
+     * |        |          |0 = UART4 clock Disabled.
+     * |        |          |1 = UART4 clock Enabled.
+     * |[21]    |UART5CKEN |UART5 Clock Enable Bit
+     * |        |          |0 = UART5 clock Disabled.
+     * |        |          |1 = UART5 clock Enabled.
+     * |[24]    |CAN0CKEN  |CAN0 Clock Enable Bit
+     * |        |          |0 = CAN0 clock Disabled.
+     * |        |          |1 = CAN0 clock Enabled.
+     * |[26]    |OTGCKEN   |USB OTG Clock Enable Bit
+     * |        |          |0 = USB OTG clock Disabled.
+     * |        |          |1 = USB OTG clock Enabled.
+     * |[27]    |USBDCKEN  |USB Device Clock Enable Bit
+     * |        |          |0 = USB Device clock Disabled.
+     * |        |          |1 = USB Device clock Enabled.
+     * |[28]    |EADCCKEN  |Enhanced Analog-digital-converter (EADC) Clock Enable Bit
+     * |        |          |0 = EADC clock Disabled.
+     * |        |          |1 = EADC clock Enabled.
+     * |[29]    |I2S0CKEN  |I2S0 Clock Enable Bit
+     * |        |          |0 = I2S0 Clock Disabled.
+     * |        |          |1 = I2S0 Clock Enabled.
+     * |[31]    |EWDTCKEN |Extra Watchdog Timer Clock Enable Bit (Write Protect)
+     * |        |          |0 = Extra Watchdog timer and Extra Windows watchdog timer clock Disabled.
+     * |        |          |1 = Extra Watchdog timer and Extra Windows watchdog timer clock Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * @var CLK_T::APBCLK1
+     * Offset: 0x0C  APB Devices Clock Enable Control Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SC0CKEN   |Smart Card 0 (SC0) Clock Enable Bit
+     * |        |          |0 = SC0 clock Disabled.
+     * |        |          |1 = SC0 clock Enabled.
+     * |[1]     |SC1CKEN   |Smart Card 1 (SC1) Clock Enable Bit
+     * |        |          |0 = SC1 clock Disabled.
+     * |        |          |1 = SC1 clock Enabled.
+     * |[2]     |SC2CKEN   |Smart Card 2 (SC2) Clock Enable Bit
+     * |        |          |0 = SC2 clock Disabled.
+     * |        |          |1 = SC2 clock Enabled.
+     * |[4]     |TMR4CKEN  |Timer4 Clock Enable Bit
+     * |        |          |0 = Timer4 clock Disabled.
+     * |        |          |1 = Timer4 clock Enabled.
+     * |[5]     |TMR5CKEN  |Timer5 Clock Enable Bit
+     * |        |          |0 = Timer5 clock Disabled.
+     * |        |          |1 = Timer5 clock Enabled.
+     * |[6]     |SPI3CKEN  |SPI3 Clock Enable Bit
+     * |        |          |0 = SPI3 clock Disabled.
+     * |        |          |1 = SPI3 clock Enabled.
+     * |[8]     |USCI0CKEN |USCI0 Clock Enable Bit
+     * |        |          |0 = USCI0 clock Disabled.
+     * |        |          |1 = USCI0 clock Enabled.
+     * |[9]     |USCI1CKEN |USCI1 Clock Enable Bit
+     * |        |          |0 = USCI1 clock Disabled.
+     * |        |          |1 = USCI1 clock Enabled.
+     * |[12]    |DACCKEN   |DAC Clock Enable Bit
+     * |        |          |0 = DAC clock Disabled.
+     * |        |          |1 = DAC clock Enabled.
+     * |[16]    |EPWM0CKEN |EPWM0 Clock Enable Bit
+     * |        |          |0 = EPWM0 clock Disabled.
+     * |        |          |1 = EPWM0 clock Enabled.
+     * |[17]    |EPWM1CKEN |EPWM1 Clock Enable Bit
+     * |        |          |0 = EPWM1 clock Disabled.
+     * |        |          |1 = EPWM1 clock Enabled.
+     * |[18]    |BPWM0CKEN |BPWM0 Clock Enable Bit
+     * |        |          |0 = BPWM0 clock Disabled.
+     * |        |          |1 = BPWM0 clock Enabled.
+     * |[19]    |BPWM1CKEN |BPWM1 Clock Enable Bit
+     * |        |          |0 = BPWM1 clock Disabled.
+     * |        |          |1 = BPWM1 clock Enabled.
+     * |[22]    |QEI0CKEN  |QEI0 Clock Enable Bit
+     * |        |          |0 = QEI0 clock Disabled.
+     * |        |          |1 = QEI0 clock Enabled.
+     * |[23]    |QEI1CKEN  |QEI1 Clock Enable Bit
+     * |        |          |0 = QEI1 clock Disabled.
+     * |        |          |1 = QEI1 clock Enabled.
+     * |[25]    |TRNGCKEN  |TRNG Clock Enable Bit
+     * |        |          |0 = TRNG clock Disabled.
+     * |        |          |1 = TRNG clock Enabled.
+     * |[26]    |ECAP0CKEN |ECAP0 Clock Enable Bit
+     * |        |          |0 = ECAP0 clock Disabled.
+     * |        |          |1 = ECAP0 clock Enabled.
+     * |[27]    |ECAP1CKEN |ECAP1 Clock Enable Bit
+     * |        |          |0 = ECAP1 clock Disabled.
+     * |        |          |1 = ECAP1 clock Enabled.
+     * |[28]    |LCDCPCKEN |LCD Charge Pump Clock Enable Bit
+     * |        |          |0 = LCD charge pump clock Disabled.
+     * |        |          |1 = LCD charge pump clock Enabled.
+     * @var CLK_T::CLKSEL0
+     * Offset: 0x10  Clock Source Select Control Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |HCLKSEL   |HCLK Clock Source Selection (Write Protect)
+     * |        |          |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on.
+     * |        |          |000 = Clock source from HXT.
+     * |        |          |001 = Clock source from LXT.
+     * |        |          |010 = Clock source from PLL.
+     * |        |          |011 = Clock source from LIRC.
+     * |        |          |100 = Reserved.
+     * |        |          |101 = Clock source from HIRC48.
+     * |        |          |110 = Clock source from MIRC.
+     * |        |          |111 = Clock source from HIRC.
+     * |        |          |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |[5:3]   |STCLKSEL  |SysTick Clock Source Selection (Write Protect)
+     * |        |          |If SYST_CTRL[2]=0, SysTick uses listed clock source below.
+     * |        |          |000 = Clock source from HXT.
+     * |        |          |001 = Clock source from LXT.
+     * |        |          |010 = Clock source from HXT/2.
+     * |        |          |011 = Clock source from HCLK/2.
+     * |        |          |111 = Clock source from HIRC/2.
+     * |        |          |Others = Reserved.
+     * |        |          |Note1: if SysTick clock source is not from HCLK (i.e SYST_CTRL[2] = 0),
+     * |        |          |SysTick need to enable EXSTCKEN(CLK_AHBCLK[4]) and clock frequency must less than or equal to HCLK/2.
+     * |        |          |Note2: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |[8]     |USBSEL    |USB Clock Source Selection (Write Protect)
+     * |        |          |0 = Clock source from HIRC48.
+     * |        |          |1 = Clock source from PLL.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[21:20] |SDH0SEL   |SDHOST0 Peripheral Clock Source Selection (Write Protect)
+     * |        |          |00 = Clock source from HXT clock.
+     * |        |          |01 = Clock source from PLL clock.
+     * |        |          |10 = Clock source from HCLK.
+     * |        |          |11 = Clock source from HIRC clock.
+     * |        |          |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * @var CLK_T::CLKSEL1
+     * Offset: 0x14  Clock Source Select Control Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |WDTSEL    |Watchdog Timer Clock Source Selection (Write Protect)
+     * |        |          |00 = Reserved.
+     * |        |          |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |10 = Clock source from HCLK/2048.
+     * |        |          |11 = Clock source from 32 kHz internal low speed RC oscillator (LIRC).
+     * |        |          |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |[2]     |LCDSEL    |LCD Clock Source Selection
+     * |        |          |0 = Clock source from 32 kHz internal low speed RC oscillator (LIRC).
+     * |        |          |1 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |[3]     |LCDCPSEL  |LCD Charge Pump Clock Source Selection
+     * |        |          |0 = Clock source from 1.2 MHz internal medium speed RC oscillator (MIRC1P2M).
+     * |        |          |1 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC).
+     * |[5:4]   |EWDTSEL   |Extra Watchdog Timer Clock Source Selection (Write Protect)
+     * |        |          |00 = Reserved.
+     * |        |          |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |10 = Clock source from HCLK/2048.
+     * |        |          |11 = Clock source from 32 kHz internal low speed RC oscillator (LIRC).
+     * |        |          |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |[7:6]   |EWWDTSEL  |Extra Window Watchdog Timer Clock Source Selection (Write Protect)
+     * |        |          |10 = Clock source from HCLK/2048.
+     * |        |          |11 = Clock source from 32 kHz internal low speed RC oscillator (LIRC).
+     * |        |          |Others = Reserved.
+     * |        |          |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |[10:8]  |TMR0SEL   |TIMER0 Clock Source Selection
+     * |        |          |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |010 = Clock source from PCLK0.
+     * |        |          |011 = Clock source from external clock TM0 pin.
+     * |        |          |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC).
+     * |        |          |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |        |          |Others = Reserved.
+     * |[14:12] |TMR1SEL   |TIMER1 Clock Source Selection
+     * |        |          |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |010 = Clock source from PCLK0.
+     * |        |          |011 = Clock source from external clock TM1 pin.
+     * |        |          |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC).
+     * |        |          |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |        |          |Others = Reserved.
+     * |[18:16] |TMR2SEL   |TIMER2 Clock Source Selection
+     * |        |          |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |010 = Clock source from PCLK1.
+     * |        |          |011 = Clock source from external clock TM2 pin.
+     * |        |          |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC).
+     * |        |          |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |        |          |Others = Reserved.
+     * |[22:20] |TMR3SEL   |TIMER3 Clock Source Selection
+     * |        |          |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |010 = Clock source from PCLK1.
+     * |        |          |011 = Clock source from external clock TM3 pin.
+     * |        |          |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC).
+     * |        |          |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |        |          |Others = Reserved.
+     * |[29:28] |CLKOSEL   |Clock Output Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |10 = Clock source from HCLK.
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[31:30] |WWDTSEL   |Window Watchdog Timer Clock Source Selection (Write Protect)
+     * |        |          |10 = Clock source from HCLK/2048.
+     * |        |          |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
+     * |        |          |Others = Reserved.
+     * |        |          |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * @var CLK_T::CLKSEL2
+     * Offset: 0x18  Clock Source Select Control Register 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |EPWM0SEL  |EPWM0 Clock Source Selection (Read Only)
+     * |        |          |The peripheral clock source of EPWM0 is defined by EPWM0SEL.
+     * |        |          |1 = Clock source from PCLK0.
+     * |[1]     |EPWM1SEL  |EPWM1 Clock Source Selection (Read Only)
+     * |        |          |The peripheral clock source of EPWM1 is defined by EPWM1SEL.
+     * |        |          |1 = Clock source from PCLK1.
+     * |[3:2]   |QSPI0SEL  |QSPI0 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from PCLK0.
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[5:4]   |SPI0SEL   |SPI0 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from PCLK1.
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[7:6]   |SPI1SEL   |SPI1 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from PCLK0.
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[8]     |BPWM0SEL  |BPWM0 Clock Source Selection (Read Only)
+     * |        |          |The peripheral clock source of BPWM0 is defined by BPWM0SEL.
+     * |        |          |1 = Clock source from PCLK0.
+     * |[9]     |BPWM1SEL  |BPWM1 Clock Source Selection (Read Only)
+     * |        |          |The peripheral clock source of BPWM1 is defined by BPWM1SEL.
+     * |        |          |1 = Clock source from PCLK1.
+     * |[11:10] |SPI2SEL   |SPI2 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from PCLK1.
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[13:12] |SPI3SEL   |SPI3 Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from PCLK0.
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[18:16] |UART0SEL  |UART0 Clock Source Selection
+     * |        |          |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |001 = Clock source from PLL.
+     * |        |          |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |        |          |100 = Clock source from PCLK0.
+     * |        |          |Others = Reserved.
+     * |[22:20] |UART1SEL  |UART1 Clock Source Selection
+     * |        |          |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |001 = Clock source from PLL.
+     * |        |          |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |        |          |100 = Clock source from PCLK1.
+     * |        |          |Others = Reserved.
+     * |[26:24] |UART2SEL  |UART2 Clock Source Selection
+     * |        |          |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |001 = Clock source from PLL.
+     * |        |          |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |        |          |100 = Clock source from PCLK0.
+     * |        |          |Others = Reserved.
+     * |[32:28] |UART3SEL  |UART3 Clock Source Selection
+     * |        |          |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |001 = Clock source from PLL.
+     * |        |          |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |        |          |100 = Clock source from PCLK1.
+     * |        |          |Others = Reserved.
+     * @var CLK_T::CLKSEL3
+     * Offset: 0x1C  Clock Source Select Control Register 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |SC0SEL    |Smart Card 0 (SC0) Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from PCLK0.
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[3:2]   |SC1SEL    |Smart Card 1 (SC1) Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from PCLK1.
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[5:4]   |SC2SEL    |Smart Card 2 (SC2) Clock Source Selection
+     * |        |          |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |01 = Clock source from PLL.
+     * |        |          |10 = Clock source from PCLK0.
+     * |        |          |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[10:8]  |TMR4SEL   |TIMER4 Clock Source Selection
+     * |        |          |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |010 = Clock source from PCLK0.
+     * |        |          |011 = Clock source from external clock TM4 pin.
+     * |        |          |100 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC).
+     * |        |          |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC).
+     * |        |          |110 = Reserved.
+     * |        |          |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[14:12] |TMR5SEL   |TIMER5 Clock Source Selection
+     * |        |          |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |010 = Clock source from PCLK0.
+     * |        |          |011 = Clock source from external clock TM5 pin.
+     * |        |          |100 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC).
+     * |        |          |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC).
+     * |        |          |110 = Reserved.
+     * |        |          |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |[17:16] |I2S0SEL   |I2S0 Clock Source Selection
+     * |        |          |00 = Clock source from HXT clock.
+     * |        |          |01 = Clock source from PLL clock.
+     * |        |          |10 = Clock source from PCLK0.
+     * |        |          |11 = Clock source from HIRC clock.
+     * |[27:24] |UART4SEL  |UART4 Clock Source Selection
+     * |        |          |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |001 = Clock source from PLL.
+     * |        |          |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |        |          |100 = Clock source from PCLK0.
+     * |        |          |Others = Reserved.
+     * |[28:30] |UART5SEL  |UART5 Clock Source Selection
+     * |        |          |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
+     * |        |          |001 = Clock source from PLL.
+     * |        |          |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
+     * |        |          |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
+     * |        |          |100 = Clock source from PCLK1.
+     * |        |          |Others = Reserved.
+     * @var CLK_T::CLKDIV0
+     * Offset: 0x20  Clock Divider Number Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |HCLKDIV   |HCLK Clock Divide Number from HCLK Clock Source
+     * |        |          |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1).
+     * |[7:4]   |USBDIV    |USB Clock Divide Number from USB Clock Source
+     * |        |          |USB clock frequency = (USB clock source frequency) / (USBDIV + 1).
+     * |[11:8]  |UART0DIV  |UART0 Clock Divide Number from UART0 Clock Source
+     * |        |          |UART0 clock frequency = (UART0 clock source frequency) / (UART0DIV + 1).
+     * |[15:12] |UART1DIV  |UART1 Clock Divide Number from UART1 Clock Source
+     * |        |          |UART1 clock frequency = (UART1 clock source frequency) / (UART1DIV + 1).
+     * |[23:16] |EADCDIV   |EADC Clock Divide Number from EADC Clock Source
+     * |        |          |EADC clock frequency = (EADC clock source frequency) / (EADCDIV + 1).
+     * |[31:24] |SDH0DIV   |SDHOST0 Clock Divide Number from SDHOST0 Clock Source
+     * |        |          |SDHOST0 clock frequency = (SDHOST0 clock source frequency) / (SDH0DIV + 1).
+     * @var CLK_T::CLKDIV1
+     * Offset: 0x24  Clock Divider Number Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |SC0DIV    |Smart Card 0 (SC0) Clock Divide Number from SC0 Clock Source
+     * |        |          |SC0 clock frequency = (SC0 clock source frequency) / (SC0DIV + 1).
+     * |[15:8]  |SC1DIV    |Smart Card 1 (SC1) Clock Divide Number from SC1 Clock Source
+     * |        |          |SC1 clock frequency = (SC1 clock source frequency) / (SC1DIV + 1).
+     * |[23:16] |SC2DIV    |Smart Card 2 (SC2) Clock Divide Number from SC2 Clock Source
+     * |        |          |SC2 clock frequency = (SC2 clock source frequency) / (SC2DIV + 1).
+     * @var CLK_T::CLKDIV4
+     * Offset: 0x30  Clock Divider Number Register 4
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |UART2DIV  |UART2 Clock Divide Number from UART2 Clock Source
+     * |        |          |UART2 clock frequency = (UART2 clock source frequency) / (UART2DIV + 1).
+     * |[7:4]   |UART3DIV  |UART3 Clock Divide Number from UART3 Clock Source
+     * |        |          |UART3 clock frequency = (UART3 clock source frequency) / (UART3DIV + 1).
+     * |[11:8]  |UART4DIV  |UART4 Clock Divide Number from UART4 Clock Source
+     * |        |          |UART4 clock frequency = (UART4 clock source frequency) / (UART4DIV + 1).
+     * |[15:12] |UART5DIV  |UART5 Clock Divide Number from UART5 Clock Source
+     * |        |          |UART5 clock frequency = (UART5 clock source frequency) / (UART5DIV + 1).
+    * @var CLK_T::PLLCTL
+     * Offset: 0x40  PLL Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[8:0]   |FBDIV     |PLL Feedback Divider Control (Write Protect)
+     * |        |          |Refer to the PLL formulas.
+     * |        |          |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |[13:9]  |INDIV     |PLL Input Divider Control (Write Protect)
+     * |        |          |Refer to the PLL formulas.
+     * |        |          |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |[15:14] |OUTDIV    |PLL Output Divider Control (Write Protect)
+     * |        |          |Refer to the PLL formulas.
+     * |        |          |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |[16]    |PD        |Power-down Mode (Write Protect)
+     * |        |          |0 = PLL is enable (in normal mode).
+     * |        |          |1 = PLL is disable (in Power-down mode) (default).
+     * |        |          |Note1: If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.
+     * |        |          |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[17]    |BP        |PLL Bypass Control (Write Protect)
+     * |        |          |0 = PLL is in normal mode (default).
+     * |        |          |1 = PLL clock output is same as PLL input clock FIN.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[19]    |PLLSRC    |PLL Source Clock Selection (Write Protect)
+     * |        |          |0 = PLL source clock from 4~24 MHz external high-speed crystal oscillator (HXT).
+     * |        |          |1 = PLL source clock from 12 MHz internal high-speed oscillator (HIRC).
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[23]    |STBSEL    |PLL Stable Counter Selection (Write Protect)
+     * |        |          |0 = PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12 MHz).
+     * |        |          |1 = PLL stable time is 12288 PLL source clock (suitable for source clock is larger than 12 MHz).
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * @var CLK_T::STATUS
+     * Offset: 0x50  Clock Status Monitor Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |HXTSTB    |HXT Clock Source Stable Flag (Read Only)
+     * |        |          |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled.
+     * |        |          |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled.
+     * |[1]     |LXTSTB    |LXT Clock Source Stable Flag (Read Only)
+     * |        |          |LXT clock source can be selected as extLXT or LIRC32 by setting C32KS(RTC_LXTCTL[7]).
+     * |        |          |If C32KS is set to 0 the LXT stable flag is set when extLXT clock source is stable.
+     * |        |          |If C32KS is set to 1 the LXT stable flag is set when LIRC32 clock source is stable.
+     * |        |          |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled.
+     * |        |          |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled.
+     * |[2]     |PLLSTB    |Internal PLL Clock Source Stable Flag (Read Only)
+     * |        |          |0 = Internal PLL clock is not stable or disabled.
+     * |        |          |1 = Internal PLL clock is stable and enabled.
+     * |[3]     |LIRCSTB   |LIRC Clock Source Stable Flag (Read Only)
+     * |        |          |0 = 32 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled.
+     * |        |          |1 = 32 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled.
+     * |[4]     |HIRCSTB   |HIRC Clock Source Stable Flag (Read Only)
+     * |        |          |0 = 12 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled.
+     * |        |          |1 = 12 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled.
+     * |[5]     |MIRCSTB   |MIRC Clock Source Stable Flag (Read Only)
+     * |        |          |0 = 4 MHz internal medium speed RC oscillator (MIRC) clock is not stable or disabled.
+     * |        |          |1 = 4 MHz internal medium speed RC oscillator (MIRC) clock is stable and enabled.
+     * |[6]     |HIRC48STB |HIRC48 Clock Source Stable Flag (Read Only)
+     * |        |          |0 = 48 MHz internal high speed RC oscillator (HIRC48) clock is not stable or disabled.
+     * |        |          |1 = 48 MHz internal high speed RC oscillator (HIRC48) clock is stable and enabled.
+     * |[7]     |CLKSFAIL  |Clock Switching Fail Flag (Read Only)
+     * |        |          |This bit is updated when software switches system clock source.
+     * |        |          |If switch target clock is stable, this bit will be set to 0.
+     * |        |          |If switch target clock is not stable, this bit will be set to 1.
+     * |        |          |0 = Clock switching success.
+     * |        |          |1 = Clock switching failure.
+     * |        |          |Note: This bit is read only.
+     * |        |          |After selected clock source is stable, hardware will switch system clock to selected clock automatically, and CLKSFAIL will be cleared automatically by hardware.
+     * |[8]     |EXTLXTSTB |EXTLXT Clock Source Stable Flag (Read Only)
+     * |        |          |0 = 32.768 kHz external low speed crystal oscillator (extLXT) clock is not stable or disabled.
+     * |        |          |1 = 32.768 kHz external low speed crystal oscillator (extLXT) clock is stable and enabled.
+     * |[9]     |LIRC32STB |LIRC32 Clock Source Stable Flag (Read Only)
+     * |        |          |0 = 32 kHz internal low speed RC oscillator (LIRC32) clock is not stable or disabled.
+     * |        |          |1 = 32 kHz internal low speed RC oscillator (LIRC32) clock is stable and enabled.
+     * @var CLK_T::CLKOCTL
+     * Offset: 0x60  Clock Output Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |FREQSEL   |Clock Output Frequency Selection
+     * |        |          |The formula of output frequency is Fout = Fin/2^(N+1).
+     * |        |          |Fin is the input clock frequency.
+     * |        |          |Fout is the frequency of divider output clock.
+     * |        |          |N is the 4-bit value of FREQSEL[3:0].
+     * |[4]     |CLKOEN    |Clock Output Enable Bit
+     * |        |          |0 = Clock Output function Disabled.
+     * |        |          |1 = Clock Output function Enabled.
+     * |[5]     |DIV1EN    |Clock Output Divide One Enable Bit
+     * |        |          |0 = Clock Output will output clock with source frequency divided by FREQSEL.
+     * |        |          |1 = Clock Output will output clock with source frequency.
+     * |[6]     |CLK1HZEN  |Clock Output 1Hz Enable Bit
+     * |        |          |0 = 1 Hz clock output for 32.768 kHz frequency compensation Disabled.
+     * |        |          |1 = 1 Hz clock output for 32.768 kHz frequency compensation Enabled.
+     * @var CLK_T::CLKDCTL
+     * Offset: 0x70  Clock Fail Detector Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[4]     |HXTFDEN   |HXT Clock Fail Detector Enable Bit
+     * |        |          |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled.
+     * |        |          |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled.
+     * |[5]     |HXTFIEN   |HXT Clock Fail Interrupt Enable Bit
+     * |        |          |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled.
+     * |        |          |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled.
+     * |[6]     |HXTFDSEL  |HXT Clock Fail Detector Selection
+     * |        |          |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector after HXT stable.
+     * |        |          |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector bypass HXT stable.
+     * |        |          |Note: When HXT Clock Fail Detector Selection is set, detector will keep detect whether HXT is stable or not, prevent HXT fail before stable.
+     * |[12]    |LXTFDEN   |LXT Clock Fail Detector Enable Bit
+     * |        |          |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled.
+     * |        |          |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled.
+     * |[13]    |LXTFIEN   |LXT Clock Fail Interrupt Enable Bit
+     * |        |          |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled.
+     * |        |          |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled.
+     * |[16]    |HXTFQDEN  |HXT Clock Frequency Monitor Enable Bit
+     * |        |          |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor Disabled.
+     * |        |          |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor Enabled.
+     * |[17]    |HXTFQIEN  |HXT Clock Frequency Monitor Interrupt Enable Bit
+     * |        |          |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Disabled.
+     * |        |          |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Enabled.
+     * @var CLK_T::CLKDSTS
+     * Offset: 0x74  Clock Fail Detector Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |HXTFIF    |HXT Clock Fail Interrupt Flag (Write Protect)
+     * |        |          |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is normal.
+     * |        |          |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock stops.
+     * |        |          |Note1: Write 1 to clear the bit to 0.
+     * |        |          |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[1]     |LXTFIF    |LXT Clock Fail Interrupt Flag (Write Protect)
+     * |        |          |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is normal.
+     * |        |          |1 = 32.768 kHz external low speed crystal oscillator (LXT) stops.
+     * |        |          |Note1: Write 1 to clear the bit to 0.
+     * |        |          |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[8]     |HXTFQIF   |HXT Clock Frequency Monitor Interrupt Flag (Write Protect)
+     * |        |          |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is normal.
+     * |        |          |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal.
+     * |        |          |Note1: Write 1 to clear the bit to 0.
+     * |        |          |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * @var CLK_T::CDUPB
+     * Offset: 0x78  Clock Frequency Detector Upper Boundary Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[9:0]   |UPERBD    |HXT Clock Frequency Detector Upper Boundary
+     * |        |          |The bits define the high value of frequency monitor window.
+     * |        |          |When HXT frequency monitor value higher than this register, the HXT frequency detect fail interrupt flag will set to 1.
+     * @var CLK_T::CDLOWB
+     * Offset: 0x7C  Clock Frequency Detector Lower Boundary Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[9:0]   |LOWERBD   |HXT Clock Frequency Detector Lower Boundary
+     * |        |          |The bits define the low value of frequency monitor window.
+     * |        |          |When HXT frequency monitor value lower than this register, the HXT frequency detect fail interrupt flag will set to 1.
+     * @var CLK_T::PMUCTL
+     * Offset: 0x90  Power Manager Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |PDMSEL    |Power-down Mode Selection (Write Protect)
+     * |        |          |These bits control chip Power-down mode grade selection when CPU execute WFI/WFE instruction.
+     * |        |          |000 = Power-down mode is selected (PD).
+     * |        |          |001 = Low leakage Power-down mode is selected (LLPD).
+     * |        |          |010 = Fast wake-up Power-down (FWPD).
+     * |        |          |011 = Ultra low leakage Power-down mode is selected (ULLPD).
+     * |        |          |100 = Standby Power-down mode is selected (SPD).
+     * |        |          |101 = Reserved.
+     * |        |          |110 = Deep Power-down mode is selected (DPD).
+     * |        |          |111 = Reserved.
+     * |        |          |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |[4]     |VDROPEN   |Standby Power Down Mode Regulator Output Voltage Drop Enable Bit (Write Protect)
+     * |        |          |If this bit be asserted, regulator output voltage drop to 0.9V when SPD mode.
+     * |        |          |0 = Regulator voltage auto drop function Disabled.
+     * |        |          |1 = Regulator voltage auto drop function Enabled. (default)
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[7]     |WRBUSY    |Write Busy Flag (Read Only)
+     * |        |          |If CLK_PMUCTL be written, this bit be asserted automatic by hardware, and be de-asserted when write procedure finish.
+     * |        |          |0 = CLK_PMUCTL write ready.
+     * |        |          |1 = CLK_PMUCTL write ignore.
+     * |[8]     |WKTMREN   |Wake-up Timer Enable Bit (Write Protect)
+     * |        |          |0 = Wake-up timer Disable in Deep Power-down mode or Standby Power-down mode.
+     * |        |          |1 = Wake-up timer Enabled in Deep Power-down mode or Standby Power-down mode.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[11:9]  |WKTMRIS   |Wake-up Timer Time-out Interval Select (Write Protect)
+     * |        |          |These bits control wake-up timer time-out interval when chip under Deep Power-down mode or Standby Power-down mode.
+     * |        |          |000 = Time-out interval is 410 LIRC clocks (12.8ms).
+     * |        |          |001 = Time-out interval is 819 LIRC clocks (25.6ms).
+     * |        |          |010 = Time-out interval is 1638 LIRC clocks (51.2ms).
+     * |        |          |011 = Time-out interval is 3277 LIRC clocks (102.4ms).
+     * |        |          |100 = Time-out interval is 13107 LIRC clocks (409.6ms).
+     * |        |          |101 = Time-out interval is 26214 LIRC clocks (819.2ms).
+     * |        |          |110 = Time-out interval is 52429 LIRC clocks (1638.4ms).
+     * |        |          |111 = Time-out interval is 209715 LIRC clocks (6553.6ms).
+     * |[17:16] |WKPINEN0  |Wake-up Pin 0 Enable (Write Protect)
+     * |        |          |This is control register for GPC.0 to wake-up pin.
+     * |        |          |00 = Wake-up pin Disable in Deep Power-down mode.
+     * |        |          |01 = Wake-up pin rising edge Enabled in Deep Power-down mode.
+     * |        |          |10 = Wake-up pin falling edge Enabled in Deep Power-down mode.
+     * |        |          |11 = Wake-up pin both edge Enabled in Deep Power-down mode.
+     * |        |          |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |[18]    |ACMPSPWK  |ACMP Standby Power-down Mode Wake-up Enable (Write Protect)
+     * |        |          |0 = ACMP wake-up disable in Standby Power-down mode.
+     * |        |          |1 = ACMP wake-up enabled in Standby Power-down mode.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[19]    |TAMPERWK  |Tamper Standby Power-down Mode Wake-up Enable Bit (Write Protect)
+     * |        |          |0 = Tamper wake-up disable at Standby Power-down mode.
+     * |        |          |1 = Tamper wake-up enabled at Standby Power-down mode.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[23]    |RTCWKEN   |RTC Wake-up Enable (Write Protect)
+     * |        |          |This is a protected register. Please refer to open lock sequence to program it.
+     * |        |          |0 = RTC wake-up Disable in Deep Power-down mode or Standby Power-down mode.
+     * |        |          |1 = RTC wake-up Enabled in Deep Power-down mode or Standby Power-down mode.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[25:24] |WKPINEN1  |Wake-up Pin 1 Enable (Write Protect)
+     * |        |          |This is control register for GPB.0 to wake-up pin.
+     * |        |          |00 = Wake-up pin Disable in Deep Power-down mode.
+     * |        |          |01 = Wake-up pin rising edge Enabled in Deep Power-down mode.
+     * |        |          |10 = Wake-up pin falling edge Enabled in Deep Power-down mode.
+     * |        |          |11 = Wake-up pin both edge Enabled in Deep Power-down mode.
+     * |        |          |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |[27:26] |WKPINEN2  |Wake-up Pin 2 Enable (Write Protect)
+     * |        |          |This is control register for GPB.2 to wake-up pin.
+     * |        |          |00 = Wake-up pin Disable in Deep Power-down mode.
+     * |        |          |01 = Wake-up pin rising edge Enabled in Deep Power-down mode.
+     * |        |          |10 = Wake-up pin falling edge Enabled in Deep Power-down mode.
+     * |        |          |11 = Wake-up pin both edge Enabled in Deep Power-down mode.
+     * |        |          |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |[29:28] |WKPINEN3  |Wake-up Pin 3 Enable (Write Protect)
+     * |        |          |This is control register for GPB.12 to wake-up pin.
+     * |        |          |00 = Wake-up pin Disable in Deep Power-down mode.
+     * |        |          |01 = Wake-up pin rising edge Enabled in Deep Power-down mode.
+     * |        |          |10 = Wake-up pin falling edge Enabled in Deep Power-down mode.
+     * |        |          |11 = Wake-up pin both edge Enabled in Deep Power-down mode.
+     * |        |          |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |[31:30] |WKPINEN4  |Wake-up Pin 4 Enable (Write Protect)
+     * |        |          |This is control register for GPF.6 to wake-up pin.
+     * |        |          |00 = Wake-up pin Disable in Deep Power-down mode.
+     * |        |          |01 = Wake-up pin rising edge Enabled in Deep Power-down mode.
+     * |        |          |10 = Wake-up pin falling edge Enabled in Deep Power-down mode.
+     * |        |          |11 = Wake-up pin both edge Enabled in Deep Power-down mode.
+     * |        |          |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * @var CLK_T::PMUSTS
+     * Offset: 0x94  Power Manager Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PINWK0    |Pin 0 Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by a transition of the Wake-up pin (GPC.0).
+     * |        |          |This flag is cleared when DPD mode is entered.
+     * |[1]     |TMRWK     |Timer Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested by wakeup timer time-out.
+     * |        |          |This flag is cleared when DPD or SPD mode is entered.
+     * |[2]     |RTCWK     |RTC Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wakeup of device from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested with a RTC alarm, tick time or tamper happened.
+     * |        |          |This flag is cleared when DPD or SPD mode is entered.
+     * |[3]     |PINWK1    |Pin 1 Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by a transition of the Wake-up pin (GPB.0).
+     * |        |          |This flag is cleared when DPD mode is entered.
+     * |[4]     |PINWK2    |Pin 2 Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by a transition of the Wake-up pin (GPB.2).
+     * |        |          |This flag is cleared when DPD mode is entered.
+     * |[5]     |PINWK3    |Pin 3 Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by a transition of the Wake-up pin (GPB.12).
+     * |        |          |This flag is cleared when DPD mode is entered.
+     * |[6]     |PINWK4    |Pin 4 Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by a transition of the Wake-up pin (GPF.6).
+     * |        |          |This flag is cleared when DPD mode is entered.
+     * |[8]     |GPAWK     |GPA Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPA group pins.
+     * |        |          |This flag is cleared when SPD mode is entered.
+     * |[9]     |GPBWK     |GPB Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPB group pins.
+     * |        |          |This flag is cleared when SPD mode is entered.
+     * |[10]    |GPCWK     |GPC Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPC group pins.
+     * |        |          |This flag is cleared when SPD mode is entered.
+     * |[11]    |GPDWK     |GPD Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPD group pins.
+     * |        |          |This flag is cleared when SPD mode is entered.
+     * |[12]    |LVRWK     |LVR Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wake-up of device from Standby Power-down mode (SPD) was requested with a LVR happened.
+     * |        |          |This flag is cleared when SPD mode is entered.
+     * |[13]    |BODWK     |BOD Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wake-up of device from Standby Power-down mode (SPD) was requested with a BOD happened.
+     * |        |          |This flag is cleared when SPD mode is entered.
+     * |[14]    |ACMPWK    |ACMP Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wake-up of device from Standby Power-down mode (SPD) was requested with a ACMP transition.
+     * |        |          |This flag is cleared when SPD mode is entered.
+     * |[15]    |TAMPERWK  |Tamper Wake-up Flag (Read Only)
+     * |        |          |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a Tamper event occurred.
+     * |        |          |This flag is cleared when SPD mode is entered.
+     * |[31]    |CLRWK     |Clear Wake-up Flag
+     * |        |          |0 = No clear.
+     * |        |          |1 = Clear all wake-up flag.
+     * |        |          |Note: This bit is auto cleared by hardware.
+     * @var CLK_T::SWKDBCTL
+     * Offset: 0x9C  Standby Power-down Wake-up De-bounce Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |SWKDBCLKSEL|Standby Power-down Wake-up De-bounce Sampling Cycle Selection
+     * |        |          |0000 = Sample wake-up input once per 1 clocks.
+     * |        |          |0001 = Sample wake-up input once per 2 clocks.
+     * |        |          |0010 = Sample wake-up input once per 4 clocks.
+     * |        |          |0011 = Sample wake-up input once per 8 clocks.
+     * |        |          |0100 = Sample wake-up input once per 16 clocks.
+     * |        |          |0101 = Sample wake-up input once per 32 clocks.
+     * |        |          |0110 = Sample wake-up input once per 64 clocks.
+     * |        |          |0111 = Sample wake-up input once per 128 clocks.
+     * |        |          |1000 = Sample wake-up input once per 256 clocks.
+     * |        |          |1001 = Sample wake-up input once per 2*256 clocks.
+     * |        |          |1010 = Sample wake-up input once per 4*256 clocks.
+     * |        |          |1011 = Sample wake-up input once per 8*256 clocks.
+     * |        |          |1100 = Sample wake-up input once per 16*256 clocks.
+     * |        |          |1101 = Sample wake-up input once per 32*256 clocks.
+     * |        |          |1110 = Sample wake-up input once per 64*256 clocks.
+     * |        |          |1111 = Sample wake-up input once per 128*256 clocks.
+     * |        |          |Note: De-bounce counter clock source is the 32 kHz internal low speed RC oscillator (LIRC).
+     * @var CLK_T::PASWKCTL
+     * Offset: 0xA0  GPA Standby Power-down Wake-up Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WKEN      |Standby Power-down Pin Wake-up Enable Bit
+     * |        |          |0 = GPA group pin wake-up function disabled.
+     * |        |          |1 = GPA group pin wake-up function Enabled.
+     * |[1]     |PRWKEN    |Pin Rising Edge Wake-up Enable Bit
+     * |        |          |0 = GPA group pin rising edge wake-up function Disabled.
+     * |        |          |1 = GPA group pin rising edge wake-up function Enabled.
+     * |[2]     |PFWKEN    |Pin Falling Edge Wake-up Enable Bit
+     * |        |          |0 = GPA group pin falling edge wake-up function Disabled.
+     * |        |          |1 = GPA group pin falling edge wake-up function Enabled.
+     * |[7:4]   |WKPSEL    |GPA Standby Power-down Wake-up Pin Select
+     * |        |          |0000 = GPA.0 wake-up function enabled.
+     * |        |          |0001 = GPA.1 wake-up function enabled.
+     * |        |          |0010 = GPA.2 wake-up function enabled.
+     * |        |          |0011 = GPA.3 wake-up function enabled.
+     * |        |          |0100 = GPA.4 wake-up function enabled.
+     * |        |          |0101 = GPA.5 wake-up function enabled.
+     * |        |          |0110 = GPA.6 wake-up function enabled.
+     * |        |          |0111 = GPA.7 wake-up function enabled.
+     * |        |          |1000 = GPA.8 wake-up function enabled.
+     * |        |          |1001 = GPA.9 wake-up function enabled.
+     * |        |          |1010 = GPA.10 wake-up function enabled.
+     * |        |          |1011 = GPA.11 wake-up function enabled.
+     * |        |          |1100 = GPA.12 wake-up function enabled.
+     * |        |          |1101 = GPA.13 wake-up function enabled.
+     * |        |          |1110 = GPA.14 wake-up function enabled.
+     * |        |          |1111 = GPA.15 wake-up function enabled.
+     * |[8]     |DBEN      |GPA Input Signal De-bounce Enable Bit
+     * |        |          |The DBEN bit is used to enable the de-bounce function for each corresponding IO.
+     * |        |          |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup.
+     * |        |          |The de-bounce clock source is the 32 kHz internal low speed RC oscillator (LIRC).
+     * |        |          |0 = Standby power-down wake-up pin De-bounce function Disable.
+     * |        |          |1 = Standby power-down wake-up pin De-bounce function Enable.
+     * |        |          |The de-bounce function is valid only for edge triggered.
+     * @var CLK_T::PBSWKCTL
+     * Offset: 0xA4  GPB Standby Power-down Wake-up Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WKEN      |Standby Power-down Pin Wake-up Enable Bit
+     * |        |          |0 = GPB group pin wake-up function Disabled.
+     * |        |          |1 = GPB group pin wake-up function Enabled.
+     * |[1]     |PRWKEN    |Pin Rising Edge Wake-up Enable Bit
+     * |        |          |0 = GPB group pin rising edge wake-up function Disabled.
+     * |        |          |1 = GPB group pin rising edge wake-up function Enabled.
+     * |[2]     |PFWKEN    |Pin Falling Edge Wake-up Enable Bit
+     * |        |          |0 = GPB group pin falling edge wake-up function Disabled.
+     * |        |          |1 = GPB group pin falling edge wake-up function Enabled.
+     * |[7:4]   |WKPSEL    |GPB Standby Power-down Wake-up Pin Select
+     * |        |          |0000 = GPB.0 wake-up function enabled.
+     * |        |          |0001 = GPB.1 wake-up function enabled.
+     * |        |          |0010 = GPB.2 wake-up function enabled.
+     * |        |          |0011 = GPB.3 wake-up function enabled.
+     * |        |          |0100 = GPB.4 wake-up function enabled.
+     * |        |          |0101 = GPB.5 wake-up function enabled.
+     * |        |          |0110 = GPB.6 wake-up function enabled.
+     * |        |          |0111 = GPB.7 wake-up function enabled.
+     * |        |          |1000 = GPB.8 wake-up function enabled.
+     * |        |          |1001 = GPB.9 wake-up function enabled.
+     * |        |          |1010 = GPB.10 wake-up function enabled.
+     * |        |          |1011 = GPB.11 wake-up function enabled.
+     * |        |          |1100 = GPB.12 wake-up function enabled.
+     * |        |          |1101 = GPB.13 wake-up function enabled.
+     * |        |          |1110 = GPB.14 wake-up function enabled.
+     * |        |          |1111 = GPB.15 wake-up function enabled.
+     * |[8]     |DBEN      |GPB Input Signal De-bounce Enable Bit
+     * |        |          |The DBEN bit is used to enable the de-bounce function for each corresponding IO.
+     * |        |          |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup.
+     * |        |          |The de-bounce clock source is the 32 kHz internal low speed RC oscillator (LIRC).
+     * |        |          |0 = Standby power-down wake-up pin De-bounce function Disable.
+     * |        |          |1 = Standby power-down wake-up pin De-bounce function Enable.
+     * |        |          |The de-bounce function is valid only for edge triggered.
+     * @var CLK_T::PCSWKCTL
+     * Offset: 0xA8  GPC Standby Power-down Wake-up Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WKEN      |Standby Power-down Pin Wake-up Enable Bit
+     * |        |          |0 = GPC group pin wake-up function Disabled.
+     * |        |          |1 = GPC group pin wake-up function Enabled.
+     * |[1]     |PRWKEN    |Pin Rising Edge Wake-up Enable Bit
+     * |        |          |0 = GPC group pin rising edge wake-up function Disabled.
+     * |        |          |1 = GPC group pin rising edge wake-up function Enabled.
+     * |[2]     |PFWKEN    |Pin Falling Edge Wake-up Enable Bit
+     * |        |          |0 = GPC group pin falling edge wake-up function Disabled.
+     * |        |          |1 = GPC group pin falling edge wake-up function Enabled.
+     * |[7:4]   |WKPSEL    |GPC Standby Power-down Wake-up Pin Select
+     * |        |          |0000 = GPC.0 wake-up function enabled.
+     * |        |          |0001 = GPC.1 wake-up function enabled.
+     * |        |          |0010 = GPC.2 wake-up function enabled.
+     * |        |          |0011 = GPC.3 wake-up function enabled.
+     * |        |          |0100 = GPC.4 wake-up function enabled.
+     * |        |          |0101 = GPC.5 wake-up function enabled.
+     * |        |          |0110 = GPC.6 wake-up function enabled.
+     * |        |          |0111 = GPC.7 wake-up function enabled.
+     * |        |          |1000 = GPC.8 wake-up function enabled.
+     * |        |          |1001 = GPC.9 wake-up function enabled.
+     * |        |          |1010 = GPC.10 wake-up function enabled.
+     * |        |          |1011 = GPC.11 wake-up function enabled.
+     * |        |          |1100 = GPC.12 wake-up function enabled.
+     * |        |          |1101 = GPC.13 wake-up function enabled.
+     * |        |          |1110 = Reserved.
+     * |        |          |1111 = Reserved.
+     * |[8]     |DBEN      |GPC Input Signal De-bounce Enable Bit
+     * |        |          |The DBEN bit is used to enable the de-bounce function for each corresponding IO.
+     * |        |          |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup.
+     * |        |          |The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC).
+     * |        |          |0 = Standby power-down wake-up pin De-bounce function Disable.
+     * |        |          |1 = Standby power-down wake-up pin De-bounce function Enable.
+     * |        |          |The de-bounce function is valid only for edge triggered.
+     * @var CLK_T::PDSWKCTL
+     * Offset: 0xAC  GPD Standby Power-down Wake-up Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WKEN      |Standby Power-down Pin Wake-up Enable Bit
+     * |        |          |0 = GPD group pin wake-up function Disabled.
+     * |        |          |1 = GPD group pin wake-up function Enabled.
+     * |[1]     |PRWKEN    |Pin Rising Edge Wake-up Enable Bit
+     * |        |          |0 = GPD group pin rising edge wake-up function Disabled.
+     * |        |          |1 = GPD group pin rising edge wake-up function Enabled.
+     * |[2]     |PFWKEN    |Pin Falling Edge Wake-up Enable Bit
+     * |        |          |0 = GPD group pin falling edge wake-up function Disabled.
+     * |        |          |1 = GPD group pin falling edge wake-up function Enabled.
+     * |[7:4]   |WKPSEL    |GPD Standby Power-down Wake-up Pin Select
+     * |        |          |0000 = GPD.0 wake-up function enabled.
+     * |        |          |0001 = GPD.1 wake-up function enabled.
+     * |        |          |0010 = GPD.2 wake-up function enabled.
+     * |        |          |0011 = GPD.3 wake-up function enabled.
+     * |        |          |0100 = GPD.4 wake-up function enabled.
+     * |        |          |0101 = GPD.5 wake-up function enabled.
+     * |        |          |0110 = GPD.6 wake-up function enabled.
+     * |        |          |0111 = GPD.7 wake-up function enabled.
+     * |        |          |1000 = GPD.8 wake-up function enabled.
+     * |        |          |1001 = GPD.9 wake-up function enabled.
+     * |        |          |1010 = GPD.10 wake-up function enabled.
+     * |        |          |1011 = GPD.11 wake-up function enabled.
+     * |        |          |1100 = GPD.12 wake-up function enabled.
+     * |        |          |1101 = Reserved.
+     * |        |          |1110 = GPD.14 wake-up function enabled.
+     * |        |          |1111 = Reserved.
+     * |[8]     |DBEN      |GPD Input Signal De-bounce Enable Bit
+     * |        |          |The DBEN bit is used to enable the de-bounce function for each corresponding IO.
+     * |        |          |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup.
+     * |        |          |The de-bounce clock source is the 32 kHz internal low speed RC oscillator (LIRC).
+     * |        |          |0 = Standby power-down wake-up pin De-bounce function Disable.
+     * |        |          |1 = Standby power-down wake-up pin De-bounce function Enable.
+     * |        |          |The de-bounce function is valid only for edge triggered.
+     * @var CLK_T::IOPDCTL
+     * Offset: 0xB0  GPIO Standby Power-down Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |IOHR      |GPIO Hold Release
+     * |        |          |When GPIO enter standby power-down mode, all I/O status are hold to keep normal operating status.
+     * |        |          |After chip was waked up from standby Power-down mode, the I/O still keeps hold status until user sets this bit to release I/O hold status.
+     * |        |          |Note: This bit is auto cleared by hardware.
+     * @var CLK_T::HXTFSEL
+     * Offset: 0xB4  HXT Filter Select Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |HXTFSEL   |HXT Filter Select
+     * |        |          |0 = HXT frequency is > 12MHz.
+     * |        |          |1 = HXT frequency is <= 12MHz.
+     * |        |          |Note: This bit is auto cleared by hardware.
+     */
+
+
+    __IO uint32_t PWRCTL;                /*!< [0x0000] System Power-down Control Register                               */
+    __IO uint32_t AHBCLK;                /*!< [0x0004] AHB Devices Clock Enable Control Register                        */
+    __IO uint32_t APBCLK0;               /*!< [0x0008] APB Devices Clock Enable Control Register 0                      */
+    __IO uint32_t APBCLK1;               /*!< [0x000C] APB Devices Clock Enable Control Register 1                      */
+    __IO uint32_t CLKSEL0;               /*!< [0x0010] Clock Source Select Control Register 0                           */
+    __IO uint32_t CLKSEL1;               /*!< [0x0014] Clock Source Select Control Register 1                           */
+    __IO uint32_t CLKSEL2;               /*!< [0x0018] Clock Source Select Control Register 2                           */
+    __IO uint32_t CLKSEL3;               /*!< [0x001C] Clock Source Select Control Register 3                           */
+    __IO uint32_t CLKDIV0;               /*!< [0x0020] Clock Divider Number Register 0                                  */
+    __IO uint32_t CLKDIV1;               /*!< [0x0024] Clock Divider Number Register 1                                  */
+    __I  uint32_t RESERVE0[2];
+    __IO uint32_t CLKDIV4;               /*!< [0x0030] Clock Divider Number Register 4                                  */
+    __I  uint32_t RESERVE7[1];
+    __I  uint32_t RESERVE1[2];
+    __IO uint32_t PLLCTL;                /*!< [0x0040] PLL Control Register                                             */
+    __I  uint32_t RESERVE2[3];
+    __I  uint32_t STATUS;                /*!< [0x0050] Clock Status Monitor Register                                    */
+    __I  uint32_t RESERVE3[3];
+    __IO uint32_t CLKOCTL;               /*!< [0x0060] Clock Output Control Register                                    */
+    __I  uint32_t RESERVE4[3];
+    __IO uint32_t CLKDCTL;               /*!< [0x0070] Clock Fail Detector Control Register                             */
+    __IO uint32_t CLKDSTS;               /*!< [0x0074] Clock Fail Detector Status Register                              */
+    __IO uint32_t CDUPB;                 /*!< [0x0078] Clock Frequency Detector Upper Boundary Register                 */
+    __IO uint32_t CDLOWB;                /*!< [0x007C] Clock Frequency Detector Low Boundary Register                   */
+    __I  uint32_t RESERVE5[4];
+    __IO uint32_t PMUCTL;                /*!< [0x0090] Power Manager Control Register                                   */
+    __IO uint32_t PMUSTS;                /*!< [0x0094] Power Manager Status Register                                    */
+    __I  uint32_t RESERVE6[1];
+    __IO uint32_t SWKDBCTL;              /*!< [0x009C] Standby Power-down Wake-up De-bounce Control Register            */
+    __IO uint32_t PASWKCTL;              /*!< [0x00A0] GPA Standby Power-down Wake-up Control Register                  */
+    __IO uint32_t PBSWKCTL;              /*!< [0x00A4] GPB Standby Power-down Wake-up Control Register                  */
+    __IO uint32_t PCSWKCTL;              /*!< [0x00A8] GPC Standby Power-down Wake-up Control Register                  */
+    __IO uint32_t PDSWKCTL;              /*!< [0x00AC] GPD Standby Power-down Wake-up Control Register                  */
+    __IO uint32_t IOPDCTL;               /*!< [0x00B0] GPIO Standby Power-down Control Register                         */
+    __IO uint32_t HXTFSEL;               /*!< [0x00B4] HXT Filter Select Control Register                               */
+
+} CLK_T;
+
+/**
+    @addtogroup CLK_CONST CLK Bit Field Definition
+    Constant Definitions for CLK Controller
+  @{
+*/
+
+#define CLK_PWRCTL_HXTEN_Pos             (0)                                               /*!< CLK_T::PWRCTL: HXTEN Position          */
+#define CLK_PWRCTL_HXTEN_Msk             (0x1ul << CLK_PWRCTL_HXTEN_Pos)                   /*!< CLK_T::PWRCTL: HXTEN Mask              */
+
+#define CLK_PWRCTL_LXTEN_Pos             (1)                                               /*!< CLK_T::PWRCTL: LXTEN Position          */
+#define CLK_PWRCTL_LXTEN_Msk             (0x1ul << CLK_PWRCTL_LXTEN_Pos)                   /*!< CLK_T::PWRCTL: LXTEN Mask              */
+
+#define CLK_PWRCTL_HIRCEN_Pos            (2)                                               /*!< CLK_T::PWRCTL: HIRCEN Position         */
+#define CLK_PWRCTL_HIRCEN_Msk            (0x1ul << CLK_PWRCTL_HIRCEN_Pos)                  /*!< CLK_T::PWRCTL: HIRCEN Mask             */
+
+#define CLK_PWRCTL_LIRCEN_Pos            (3)                                               /*!< CLK_T::PWRCTL: LIRCEN Position         */
+#define CLK_PWRCTL_LIRCEN_Msk            (0x1ul << CLK_PWRCTL_LIRCEN_Pos)                  /*!< CLK_T::PWRCTL: LIRCEN Mask             */
+
+#define CLK_PWRCTL_PDWKIEN_Pos           (5)                                               /*!< CLK_T::PWRCTL: PDWKIEN Position        */
+#define CLK_PWRCTL_PDWKIEN_Msk           (0x1ul << CLK_PWRCTL_PDWKIEN_Pos)                 /*!< CLK_T::PWRCTL: PDWKIEN Mask            */
+
+#define CLK_PWRCTL_PDWKIF_Pos            (6)                                               /*!< CLK_T::PWRCTL: PDWKIF Position         */
+#define CLK_PWRCTL_PDWKIF_Msk            (0x1ul << CLK_PWRCTL_PDWKIF_Pos)                  /*!< CLK_T::PWRCTL: PDWKIF Mask             */
+
+#define CLK_PWRCTL_PDEN_Pos              (7)                                               /*!< CLK_T::PWRCTL: PDEN Position           */
+#define CLK_PWRCTL_PDEN_Msk              (0x1ul << CLK_PWRCTL_PDEN_Pos)                    /*!< CLK_T::PWRCTL: PDEN Mask               */
+
+#define CLK_PWRCTL_HXTGAIN_Pos           (10)                                              /*!< CLK_T::PWRCTL: HXTGAIN Position        */
+#define CLK_PWRCTL_HXTGAIN_Msk           (0x3ul << CLK_PWRCTL_HXTGAIN_Pos)                 /*!< CLK_T::PWRCTL: HXTGAIN Mask            */
+
+#define CLK_PWRCTL_HXTSELTYP_Pos         (12)                                              /*!< CLK_T::PWRCTL: HXTSELTYP Position      */
+#define CLK_PWRCTL_HXTSELTYP_Msk         (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos)               /*!< CLK_T::PWRCTL: HXTSELTYP Mask          */
+
+#define CLK_PWRCTL_HXTTBEN_Pos           (13)                                              /*!< CLK_T::PWRCTL: HXTTBEN Position        */
+#define CLK_PWRCTL_HXTTBEN_Msk           (0x1ul << CLK_PWRCTL_HXTTBEN_Pos)                 /*!< CLK_T::PWRCTL: HXTTBEN Mask            */
+
+#define CLK_PWRCTL_HIRC48EN_Pos          (18)                                              /*!< CLK_T::PWRCTL: HIRC48EN Position       */
+#define CLK_PWRCTL_HIRC48EN_Msk          (0x1ul << CLK_PWRCTL_HIRC48EN_Pos)                /*!< CLK_T::PWRCTL: HIRC48EN Mask           */
+
+#define CLK_PWRCTL_MIRC1P2MEN_Pos        (20)                                              /*!< CLK_T::PWRCTL: MIRC1P2MEN Position     */
+#define CLK_PWRCTL_MIRC1P2MEN_Msk        (0x1ul << CLK_PWRCTL_MIRC1P2MEN_Pos)              /*!< CLK_T::PWRCTL: MIRC1P2MEN Mask         */
+
+#define CLK_PWRCTL_MIRCEN_Pos            (21)                                              /*!< CLK_T::PWRCTL: MIRCEN Position         */
+#define CLK_PWRCTL_MIRCEN_Msk            (0x1ul << CLK_PWRCTL_MIRCEN_Pos)                  /*!< CLK_T::PWRCTL: MIRCEN Mask             */
+
+#define CLK_AHBCLK_PDMA0CKEN_Pos         (0)                                               /*!< CLK_T::AHBCLK: PDMA0CKEN Position      */
+#define CLK_AHBCLK_PDMA0CKEN_Msk         (0x1ul << CLK_AHBCLK_PDMA0CKEN_Pos)               /*!< CLK_T::AHBCLK: PDMA0CKEN Mask          */
+
+#define CLK_AHBCLK_PDMA1CKEN_Pos         (1)                                               /*!< CLK_T::AHBCLK: PDMA1CKEN Position      */
+#define CLK_AHBCLK_PDMA1CKEN_Msk         (0x1ul << CLK_AHBCLK_PDMA1CKEN_Pos)               /*!< CLK_T::AHBCLK: PDMA1CKEN Mask          */
+
+#define CLK_AHBCLK_ISPCKEN_Pos           (2)                                               /*!< CLK_T::AHBCLK: ISPCKEN Position        */
+#define CLK_AHBCLK_ISPCKEN_Msk           (0x1ul << CLK_AHBCLK_ISPCKEN_Pos)                 /*!< CLK_T::AHBCLK: ISPCKEN Mask            */
+
+#define CLK_AHBCLK_EBICKEN_Pos           (3)                                               /*!< CLK_T::AHBCLK: EBICKEN Position        */
+#define CLK_AHBCLK_EBICKEN_Msk           (0x1ul << CLK_AHBCLK_EBICKEN_Pos)                 /*!< CLK_T::AHBCLK: EBICKEN Mask            */
+
+#define CLK_AHBCLK_EXSTCKEN_Pos          (4)                                               /*!< CLK_T::AHBCLK: EXSTCKEN Position       */
+#define CLK_AHBCLK_EXSTCKEN_Msk          (0x1ul << CLK_AHBCLK_EXSTCKEN_Pos)                /*!< CLK_T::AHBCLK: EXSTCKEN Mask           */
+
+#define CLK_AHBCLK_SDH0CKEN_Pos          (6)                                               /*!< CLK_T::AHBCLK: SDH0CKEN Position       */
+#define CLK_AHBCLK_SDH0CKEN_Msk          (0x1ul << CLK_AHBCLK_SDH0CKEN_Pos)                /*!< CLK_T::AHBCLK: SDH0CKEN Mask           */
+
+#define CLK_AHBCLK_CRCCKEN_Pos           (7)                                               /*!< CLK_T::AHBCLK: CRCCKEN Position        */
+#define CLK_AHBCLK_CRCCKEN_Msk           (0x1ul << CLK_AHBCLK_CRCCKEN_Pos)                 /*!< CLK_T::AHBCLK: CRCCKEN Mask            */
+
+#define CLK_AHBCLK_CRPTCKEN_Pos          (12)                                              /*!< CLK_T::AHBCLK: CRPTCKEN Position       */
+#define CLK_AHBCLK_CRPTCKEN_Msk          (0x1ul << CLK_AHBCLK_CRPTCKEN_Pos)                /*!< CLK_T::AHBCLK: CRPTCKEN Mask           */
+
+#define CLK_AHBCLK_KSCKEN_Pos            (13)                                              /*!< CLK_T::AHBCLK: KSCKEN Position         */
+#define CLK_AHBCLK_KSCKEN_Msk            (0x1ul << CLK_AHBCLK_KSCKEN_Pos)                  /*!< CLK_T::AHBCLK: KSCKEN Mask             */
+
+#define CLK_AHBCLK_TRACECKEN_Pos         (14)                                              /*!< CLK_T::AHBCLK: TRACECKEN Position      */
+#define CLK_AHBCLK_TRACECKEN_Msk         (0x1ul << CLK_AHBCLK_TRACECKEN_Pos)               /*!< CLK_T::AHBCLK: TRACECKEN Mask          */
+
+#define CLK_AHBCLK_FMCIDLE_Pos           (15)                                              /*!< CLK_T::AHBCLK: FMCIDLE Position        */
+#define CLK_AHBCLK_FMCIDLE_Msk           (0x1ul << CLK_AHBCLK_FMCIDLE_Pos)                 /*!< CLK_T::AHBCLK: FMCIDLE Mask            */
+
+#define CLK_AHBCLK_USBHCKEN_Pos          (16)                                              /*!< CLK_T::AHBCLK: USBHCKEN Position       */
+#define CLK_AHBCLK_USBHCKEN_Msk          (0x1ul << CLK_AHBCLK_USBHCKEN_Pos)                /*!< CLK_T::AHBCLK: USBHCKEN Mask           */
+
+#define CLK_AHBCLK_SRAM0CKEN_Pos         (20)                                              /*!< CLK_T::AHBCLK: SRAM0CKEN Position      */
+#define CLK_AHBCLK_SRAM0CKEN_Msk         (0x1ul << CLK_AHBCLK_SRAM0CKEN_Pos)               /*!< CLK_T::AHBCLK: SRAM0CKEN Mask          */
+
+#define CLK_AHBCLK_SRAM1CKEN_Pos         (21)                                              /*!< CLK_T::AHBCLK: SRAM1CKEN Position      */
+#define CLK_AHBCLK_SRAM1CKEN_Msk         (0x1ul << CLK_AHBCLK_SRAM1CKEN_Pos)               /*!< CLK_T::AHBCLK: SRAM1CKEN Mask          */
+
+#define CLK_AHBCLK_SRAM2CKEN_Pos         (22)                                              /*!< CLK_T::AHBCLK: SRAM2CKEN Position      */
+#define CLK_AHBCLK_SRAM2CKEN_Msk         (0x1ul << CLK_AHBCLK_SRAM2CKEN_Pos)               /*!< CLK_T::AHBCLK: SRAM2CKEN Mask          */
+
+#define CLK_AHBCLK_GPACKEN_Pos           (24)                                              /*!< CLK_T::AHBCLK: GPACKEN Position        */
+#define CLK_AHBCLK_GPACKEN_Msk           (0x1ul << CLK_AHBCLK_GPACKEN_Pos)                 /*!< CLK_T::AHBCLK: GPACKEN Mask            */
+
+#define CLK_AHBCLK_GPBCKEN_Pos           (25)                                              /*!< CLK_T::AHBCLK: GPBCKEN Position        */
+#define CLK_AHBCLK_GPBCKEN_Msk           (0x1ul << CLK_AHBCLK_GPBCKEN_Pos)                 /*!< CLK_T::AHBCLK: GPBCKEN Mask            */
+
+#define CLK_AHBCLK_GPCCKEN_Pos           (26)                                              /*!< CLK_T::AHBCLK: GPCCKEN Position        */
+#define CLK_AHBCLK_GPCCKEN_Msk           (0x1ul << CLK_AHBCLK_GPCCKEN_Pos)                 /*!< CLK_T::AHBCLK: GPCCKEN Mask            */
+
+#define CLK_AHBCLK_GPDCKEN_Pos           (27)                                              /*!< CLK_T::AHBCLK: GPDCKEN Position        */
+#define CLK_AHBCLK_GPDCKEN_Msk           (0x1ul << CLK_AHBCLK_GPDCKEN_Pos)                 /*!< CLK_T::AHBCLK: GPDCKEN Mask            */
+
+#define CLK_AHBCLK_GPECKEN_Pos           (28)                                              /*!< CLK_T::AHBCLK: GPECKEN Position        */
+#define CLK_AHBCLK_GPECKEN_Msk           (0x1ul << CLK_AHBCLK_GPECKEN_Pos)                 /*!< CLK_T::AHBCLK: GPECKEN Mask            */
+
+#define CLK_AHBCLK_GPFCKEN_Pos           (29)                                              /*!< CLK_T::AHBCLK: GPFCKEN Position        */
+#define CLK_AHBCLK_GPFCKEN_Msk           (0x1ul << CLK_AHBCLK_GPFCKEN_Pos)                 /*!< CLK_T::AHBCLK: GPFCKEN Mask            */
+
+#define CLK_AHBCLK_GPGCKEN_Pos           (30)                                              /*!< CLK_T::AHBCLK: GPGCKEN Position        */
+#define CLK_AHBCLK_GPGCKEN_Msk           (0x1ul << CLK_AHBCLK_GPGCKEN_Pos)                 /*!< CLK_T::AHBCLK: GPGCKEN Mask            */
+
+#define CLK_AHBCLK_GPHCKEN_Pos           (31)                                              /*!< CLK_T::AHBCLK: GPHCKEN Position        */
+#define CLK_AHBCLK_GPHCKEN_Msk           (0x1ul << CLK_AHBCLK_GPHCKEN_Pos)                 /*!< CLK_T::AHBCLK: GPHCKEN Mask            */
+
+#define CLK_APBCLK0_WDTCKEN_Pos          (0)                                               /*!< CLK_T::APBCLK0: WDTCKEN Position       */
+#define CLK_APBCLK0_WDTCKEN_Msk          (0x1ul << CLK_APBCLK0_WDTCKEN_Pos)                /*!< CLK_T::APBCLK0: WDTCKEN Mask           */
+
+#define CLK_APBCLK0_RTCCKEN_Pos          (1)                                               /*!< CLK_T::APBCLK0: RTCCKEN Position       */
+#define CLK_APBCLK0_RTCCKEN_Msk          (0x1ul << CLK_APBCLK0_RTCCKEN_Pos)                /*!< CLK_T::APBCLK0: RTCCKEN Mask           */
+
+#define CLK_APBCLK0_TMR0CKEN_Pos         (2)                                               /*!< CLK_T::APBCLK0: TMR0CKEN Position      */
+#define CLK_APBCLK0_TMR0CKEN_Msk         (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos)               /*!< CLK_T::APBCLK0: TMR0CKEN Mask          */
+
+#define CLK_APBCLK0_TMR1CKEN_Pos         (3)                                               /*!< CLK_T::APBCLK0: TMR1CKEN Position      */
+#define CLK_APBCLK0_TMR1CKEN_Msk         (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos)               /*!< CLK_T::APBCLK0: TMR1CKEN Mask          */
+
+#define CLK_APBCLK0_TMR2CKEN_Pos         (4)                                               /*!< CLK_T::APBCLK0: TMR2CKEN Position      */
+#define CLK_APBCLK0_TMR2CKEN_Msk         (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos)               /*!< CLK_T::APBCLK0: TMR2CKEN Mask          */
+
+#define CLK_APBCLK0_TMR3CKEN_Pos         (5)                                               /*!< CLK_T::APBCLK0: TMR3CKEN Position      */
+#define CLK_APBCLK0_TMR3CKEN_Msk         (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos)               /*!< CLK_T::APBCLK0: TMR3CKEN Mask          */
+
+#define CLK_APBCLK0_CLKOCKEN_Pos         (6)                                               /*!< CLK_T::APBCLK0: CLKOCKEN Position      */
+#define CLK_APBCLK0_CLKOCKEN_Msk         (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos)               /*!< CLK_T::APBCLK0: CLKOCKEN Mask          */
+
+#define CLK_APBCLK0_ACMP01CKEN_Pos       (7)                                               /*!< CLK_T::APBCLK0: ACMP01CKEN Position    */
+#define CLK_APBCLK0_ACMP01CKEN_Msk       (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos)             /*!< CLK_T::APBCLK0: ACMP01CKEN Mask        */
+
+#define CLK_APBCLK0_I2C0CKEN_Pos         (8)                                               /*!< CLK_T::APBCLK0: I2C0CKEN Position      */
+#define CLK_APBCLK0_I2C0CKEN_Msk         (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos)               /*!< CLK_T::APBCLK0: I2C0CKEN Mask          */
+
+#define CLK_APBCLK0_I2C1CKEN_Pos         (9)                                               /*!< CLK_T::APBCLK0: I2C1CKEN Position      */
+#define CLK_APBCLK0_I2C1CKEN_Msk         (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos)               /*!< CLK_T::APBCLK0: I2C1CKEN Mask          */
+
+#define CLK_APBCLK0_I2C2CKEN_Pos         (10)                                              /*!< CLK_T::APBCLK0: I2C2CKEN Position      */
+#define CLK_APBCLK0_I2C2CKEN_Msk         (0x1ul << CLK_APBCLK0_I2C2CKEN_Pos)               /*!< CLK_T::APBCLK0: I2C2CKEN Mask          */
+
+#define CLK_APBCLK0_QSPI0CKEN_Pos        (12)                                              /*!< CLK_T::APBCLK0: QSPI0CKEN Position     */
+#define CLK_APBCLK0_QSPI0CKEN_Msk        (0x1ul << CLK_APBCLK0_QSPI0CKEN_Pos)              /*!< CLK_T::APBCLK0: QSPI0CKEN Mask         */
+
+#define CLK_APBCLK0_SPI0CKEN_Pos         (13)                                              /*!< CLK_T::APBCLK0: SPI0CKEN Position      */
+#define CLK_APBCLK0_SPI0CKEN_Msk         (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos)               /*!< CLK_T::APBCLK0: SPI0CKEN Mask          */
+
+#define CLK_APBCLK0_SPI1CKEN_Pos         (14)                                              /*!< CLK_T::APBCLK0: SPI1CKEN Position      */
+#define CLK_APBCLK0_SPI1CKEN_Msk         (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos)               /*!< CLK_T::APBCLK0: SPI1CKEN Mask          */
+
+#define CLK_APBCLK0_SPI2CKEN_Pos         (15)                                              /*!< CLK_T::APBCLK0: SPI2CKEN Position      */
+#define CLK_APBCLK0_SPI2CKEN_Msk         (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos)               /*!< CLK_T::APBCLK0: SPI2CKEN Mask          */
+
+#define CLK_APBCLK0_UART0CKEN_Pos        (16)                                              /*!< CLK_T::APBCLK0: UART0CKEN Position     */
+#define CLK_APBCLK0_UART0CKEN_Msk        (0x1ul << CLK_APBCLK0_UART0CKEN_Pos)              /*!< CLK_T::APBCLK0: UART0CKEN Mask         */
+
+#define CLK_APBCLK0_UART1CKEN_Pos        (17)                                              /*!< CLK_T::APBCLK0: UART1CKEN Position     */
+#define CLK_APBCLK0_UART1CKEN_Msk        (0x1ul << CLK_APBCLK0_UART1CKEN_Pos)              /*!< CLK_T::APBCLK0: UART1CKEN Mask         */
+
+#define CLK_APBCLK0_UART2CKEN_Pos        (18)                                              /*!< CLK_T::APBCLK0: UART2CKEN Position     */
+#define CLK_APBCLK0_UART2CKEN_Msk        (0x1ul << CLK_APBCLK0_UART2CKEN_Pos)              /*!< CLK_T::APBCLK0: UART2CKEN Mask         */
+
+#define CLK_APBCLK0_UART3CKEN_Pos        (19)                                              /*!< CLK_T::APBCLK0: UART3CKEN Position     */
+#define CLK_APBCLK0_UART3CKEN_Msk        (0x1ul << CLK_APBCLK0_UART3CKEN_Pos)              /*!< CLK_T::APBCLK0: UART3CKEN Mask         */
+
+#define CLK_APBCLK0_UART4CKEN_Pos        (20)                                              /*!< CLK_T::APBCLK0: UART4CKEN Position     */
+#define CLK_APBCLK0_UART4CKEN_Msk        (0x1ul << CLK_APBCLK0_UART4CKEN_Pos)              /*!< CLK_T::APBCLK0: UART4CKEN Mask         */
+
+#define CLK_APBCLK0_UART5CKEN_Pos        (21)                                              /*!< CLK_T::APBCLK0: UART5CKEN Position     */
+#define CLK_APBCLK0_UART5CKEN_Msk        (0x1ul << CLK_APBCLK0_UART5CKEN_Pos)              /*!< CLK_T::APBCLK0: UART5CKEN Mask         */
+
+#define CLK_APBCLK0_TAMPERCKEN_Pos       (22)                                              /*!< CLK_T::APBCLK0: TAMPERCKEN Position    */
+#define CLK_APBCLK0_TAMPERCKEN_Msk       (0x1ul << CLK_APBCLK0_TAMPERCKEN_Pos)             /*!< CLK_T::APBCLK0: TAMPERCKEN Mask        */
+
+#define CLK_APBCLK0_CAN0CKEN_Pos         (24)                                              /*!< CLK_T::APBCLK0: CAN0CKEN Position      */
+#define CLK_APBCLK0_CAN0CKEN_Msk         (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos)               /*!< CLK_T::APBCLK0: CAN0CKEN Mask          */
+
+#define CLK_APBCLK0_OTGCKEN_Pos          (26)                                              /*!< CLK_T::APBCLK0: OTGCKEN Position       */
+#define CLK_APBCLK0_OTGCKEN_Msk          (0x1ul << CLK_APBCLK0_OTGCKEN_Pos)                /*!< CLK_T::APBCLK0: OTGCKEN Mask           */
+
+#define CLK_APBCLK0_USBDCKEN_Pos         (27)                                              /*!< CLK_T::APBCLK0: USBDCKEN Position      */
+#define CLK_APBCLK0_USBDCKEN_Msk         (0x1ul << CLK_APBCLK0_USBDCKEN_Pos)               /*!< CLK_T::APBCLK0: USBDCKEN Mask          */
+
+#define CLK_APBCLK0_USBDCKEN_Pos         (27)                                              /*!< CLK_T::APBCLK0: USBDCKEN Position      */
+#define CLK_APBCLK0_USBDCKEN_Msk         (0x1ul << CLK_APBCLK0_USBDCKEN_Pos)               /*!< CLK_T::APBCLK0: USBDCKEN Mask          */
+
+#define CLK_APBCLK0_EADCCKEN_Pos         (28)                                              /*!< CLK_T::APBCLK0: EADCCKEN Position      */
+#define CLK_APBCLK0_EADCCKEN_Msk         (0x1ul << CLK_APBCLK0_EADCCKEN_Pos)               /*!< CLK_T::APBCLK0: EADCCKEN Mask          */
+
+#define CLK_APBCLK0_I2S0CKEN_Pos         (29)                                              /*!< CLK_T::APBCLK0: I2S0CKEN Position      */
+#define CLK_APBCLK0_I2S0CKEN_Msk         (0x1ul << CLK_APBCLK0_I2S0CKEN_Pos)               /*!< CLK_T::APBCLK0: I2S0CKEN Mask          */
+
+#define CLK_APBCLK0_EWDTCKEN_Pos         (31)                                              /*!< CLK_T::APBCLK0: EWDTCKEN Position      */
+#define CLK_APBCLK0_EWDTCKEN_Msk         (0x1ul << CLK_APBCLK0_EWDTCKEN_Pos)               /*!< CLK_T::APBCLK0: EWDTCKEN Mask          */
+
+#define CLK_APBCLK1_SC0CKEN_Pos          (0)                                               /*!< CLK_T::APBCLK1: SC0CKEN Position       */
+#define CLK_APBCLK1_SC0CKEN_Msk          (0x1ul << CLK_APBCLK1_SC0CKEN_Pos)                /*!< CLK_T::APBCLK1: SC0CKEN Mask           */
+
+#define CLK_APBCLK1_SC1CKEN_Pos          (1)                                               /*!< CLK_T::APBCLK1: SC1CKEN Position       */
+#define CLK_APBCLK1_SC1CKEN_Msk          (0x1ul << CLK_APBCLK1_SC1CKEN_Pos)                /*!< CLK_T::APBCLK1: SC1CKEN Mask           */
+
+#define CLK_APBCLK1_SC2CKEN_Pos          (2)                                               /*!< CLK_T::APBCLK1: SC2CKEN Position       */
+#define CLK_APBCLK1_SC2CKEN_Msk          (0x1ul << CLK_APBCLK1_SC2CKEN_Pos)                /*!< CLK_T::APBCLK1: SC2CKEN Mask           */
+
+#define CLK_APBCLK1_TMR4CKEN_Pos         (4)                                               /*!< CLK_T::APBCLK1: TMR4CKEN Position      */
+#define CLK_APBCLK1_TMR4CKEN_Msk         (0x1ul << CLK_APBCLK1_TMR4CKEN_Pos)               /*!< CLK_T::APBCLK1: TMR4CKEN Mask          */
+
+#define CLK_APBCLK1_TMR5CKEN_Pos         (5)                                               /*!< CLK_T::APBCLK1: TMR5CKEN Position      */
+#define CLK_APBCLK1_TMR5CKEN_Msk         (0x1ul << CLK_APBCLK1_TMR5CKEN_Pos)               /*!< CLK_T::APBCLK1: TMR5CKEN Mask          */
+
+#define CLK_APBCLK1_SPI3CKEN_Pos         (6)                                               /*!< CLK_T::APBCLK1: SPI3CKEN Position      */
+#define CLK_APBCLK1_SPI3CKEN_Msk         (0x1ul << CLK_APBCLK1_SPI3CKEN_Pos)               /*!< CLK_T::APBCLK1: SPI3CKEN Mask          */
+
+#define CLK_APBCLK1_USCI0CKEN_Pos        (8)                                               /*!< CLK_T::APBCLK1: USCI0CKEN Position     */
+#define CLK_APBCLK1_USCI0CKEN_Msk        (0x1ul << CLK_APBCLK1_USCI0CKEN_Pos)              /*!< CLK_T::APBCLK1: USCI0CKEN Mask         */
+
+#define CLK_APBCLK1_USCI1CKEN_Pos        (9)                                               /*!< CLK_T::APBCLK1: USCI1CKEN Position     */
+#define CLK_APBCLK1_USCI1CKEN_Msk        (0x1ul << CLK_APBCLK1_USCI1CKEN_Pos)              /*!< CLK_T::APBCLK1: USCI1CKEN Mask         */
+
+#define CLK_APBCLK1_DACCKEN_Pos          (12)                                              /*!< CLK_T::APBCLK1: DACCKEN Position       */
+#define CLK_APBCLK1_DACCKEN_Msk          (0x1ul << CLK_APBCLK1_DACCKEN_Pos)                /*!< CLK_T::APBCLK1: DACCKEN Mask           */
+
+#define CLK_APBCLK1_EPWM0CKEN_Pos        (16)                                              /*!< CLK_T::APBCLK1: EPWM0CKEN Position     */
+#define CLK_APBCLK1_EPWM0CKEN_Msk        (0x1ul << CLK_APBCLK1_EPWM0CKEN_Pos)              /*!< CLK_T::APBCLK1: EPWM0CKEN Mask         */
+
+#define CLK_APBCLK1_EPWM1CKEN_Pos        (17)                                              /*!< CLK_T::APBCLK1: EPWM1CKEN Position     */
+#define CLK_APBCLK1_EPWM1CKEN_Msk        (0x1ul << CLK_APBCLK1_EPWM1CKEN_Pos)              /*!< CLK_T::APBCLK1: EPWM1CKEN Mask         */
+
+#define CLK_APBCLK1_BPWM0CKEN_Pos        (18)                                              /*!< CLK_T::APBCLK1: BPWM0CKEN Position     */
+#define CLK_APBCLK1_BPWM0CKEN_Msk        (0x1ul << CLK_APBCLK1_BPWM0CKEN_Pos)              /*!< CLK_T::APBCLK1: BPWM0CKEN Mask         */
+
+#define CLK_APBCLK1_BPWM1CKEN_Pos        (19)                                              /*!< CLK_T::APBCLK1: BPWM1CKEN Position     */
+#define CLK_APBCLK1_BPWM1CKEN_Msk        (0x1ul << CLK_APBCLK1_BPWM1CKEN_Pos)              /*!< CLK_T::APBCLK1: BPWM1CKEN Mask         */
+
+#define CLK_APBCLK1_QEI0CKEN_Pos         (22)                                              /*!< CLK_T::APBCLK1: QEI0CKEN Position      */
+#define CLK_APBCLK1_QEI0CKEN_Msk         (0x1ul << CLK_APBCLK1_QEI0CKEN_Pos)               /*!< CLK_T::APBCLK1: QEI0CKEN Mask          */
+
+#define CLK_APBCLK1_QEI1CKEN_Pos         (23)                                              /*!< CLK_T::APBCLK1: QEI1CKEN Position      */
+#define CLK_APBCLK1_QEI1CKEN_Msk         (0x1ul << CLK_APBCLK1_QEI1CKEN_Pos)               /*!< CLK_T::APBCLK1: QEI1CKEN Mask          */
+
+#define CLK_APBCLK1_LCDCKEN_Pos          (24)                                              /*!< CLK_T::APBCLK1: LCDCKEN Position       */
+#define CLK_APBCLK1_LCDCKEN_Msk          (0x1ul << CLK_APBCLK1_LCDCKEN_Pos)                /*!< CLK_T::APBCLK1: LCKCKEN Mask           */
+
+#define CLK_APBCLK1_TRNGCKEN_Pos         (25)                                              /*!< CLK_T::APBCLK1: TRNGCKEN Position      */
+#define CLK_APBCLK1_TRNGCKEN_Msk         (0x1ul << CLK_APBCLK1_TRNGCKEN_Pos)               /*!< CLK_T::APBCLK1: TRNGCKEN Mask          */
+
+#define CLK_APBCLK1_ECAP0CKEN_Pos        (26)                                              /*!< CLK_T::APBCLK1: ECAP0CKEN Position     */
+#define CLK_APBCLK1_ECAP0CKEN_Msk        (0x1ul << CLK_APBCLK1_ECAP0CKEN_Pos)              /*!< CLK_T::APBCLK1: ECAP0CKEN Mask         */
+
+#define CLK_APBCLK1_ECAP1CKEN_Pos        (27)                                              /*!< CLK_T::APBCLK1: ECAP1CKEN Position     */
+#define CLK_APBCLK1_ECAP1CKEN_Msk        (0x1ul << CLK_APBCLK1_ECAP1CKEN_Pos)              /*!< CLK_T::APBCLK1: ECAP1CKEN Mask         */
+
+#define CLK_APBCLK1_LCDCPCKEN_Pos        (28)                                              /*!< CLK_T::APBCLK1: LCDCPCKEN Position     */
+#define CLK_APBCLK1_LCDCPCKEN_Msk        (0x1ul << CLK_APBCLK1_LCDCPCKEN_Pos)              /*!< CLK_T::APBCLK1: LCDCPCKEN Mask         */
+
+#define CLK_CLKSEL0_HCLKSEL_Pos          (0)                                               /*!< CLK_T::CLKSEL0: HCLKSEL Position       */
+#define CLK_CLKSEL0_HCLKSEL_Msk          (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos)                /*!< CLK_T::CLKSEL0: HCLKSEL Mask           */
+
+#define CLK_CLKSEL0_STCLKSEL_Pos         (3)                                               /*!< CLK_T::CLKSEL0: STCLKSEL Position      */
+#define CLK_CLKSEL0_STCLKSEL_Msk         (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos)               /*!< CLK_T::CLKSEL0: STCLKSEL Mask          */
+
+#define CLK_CLKSEL0_USBSEL_Pos           (8)                                               /*!< CLK_T::CLKSEL0: USBSEL Position        */
+#define CLK_CLKSEL0_USBSEL_Msk           (0x1ul << CLK_CLKSEL0_USBSEL_Pos)                 /*!< CLK_T::CLKSEL0: USBSEL Mask            */
+
+#define CLK_CLKSEL0_SDH0SEL_Pos          (20)                                              /*!< CLK_T::CLKSEL0: SDH0SEL Position       */
+#define CLK_CLKSEL0_SDH0SEL_Msk          (0x3ul << CLK_CLKSEL0_SDH0SEL_Pos)                /*!< CLK_T::CLKSEL0: SDH0SEL Mask           */
+
+#define CLK_CLKSEL1_WDTSEL_Pos           (0)                                               /*!< CLK_T::CLKSEL1: WDTSEL Position        */
+#define CLK_CLKSEL1_WDTSEL_Msk           (0x3ul << CLK_CLKSEL1_WDTSEL_Pos)                 /*!< CLK_T::CLKSEL1: WDTSEL Mask            */
+
+#define CLK_CLKSEL1_LCDSEL_Pos           (2)                                               /*!< CLK_T::CLKSEL1: LCDSEL Position        */
+#define CLK_CLKSEL1_LCDSEL_Msk           (0x1ul << CLK_CLKSEL1_LCDSEL_Pos)                 /*!< CLK_T::CLKSEL1: LCDSEL Mask            */
+
+#define CLK_CLKSEL1_LCDCPSEL_Pos         (3)                                               /*!< CLK_T::CLKSEL1: LCDCPSEL Position      */
+#define CLK_CLKSEL1_LCDCPSEL_Msk         (0x1ul << CLK_CLKSEL1_LCDCPSEL_Pos)               /*!< CLK_T::CLKSEL1: LCDCPSEL Mask          */
+
+#define CLK_CLKSEL1_EWDTSEL_Pos          (4)                                               /*!< CLK_T::CLKSEL1: EWDTSEL Position       */
+#define CLK_CLKSEL1_EWDTSEL_Msk          (0x3ul << CLK_CLKSEL1_EWDTSEL_Pos)                /*!< CLK_T::CLKSEL1: EWDTSEL Mask           */
+
+#define CLK_CLKSEL1_EWWDTSEL_Pos         (6)                                               /*!< CLK_T::CLKSEL1: EWWDTSEL Position      */
+#define CLK_CLKSEL1_EWWDTSEL_Msk         (0x3ul << CLK_CLKSEL1_EWWDTSEL_Pos)               /*!< CLK_T::CLKSEL1: EWWDTSEL Mask          */
+
+#define CLK_CLKSEL1_TMR0SEL_Pos          (8)                                               /*!< CLK_T::CLKSEL1: TMR0SEL Position       */
+#define CLK_CLKSEL1_TMR0SEL_Msk          (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos)                /*!< CLK_T::CLKSEL1: TMR0SEL Mask           */
+
+#define CLK_CLKSEL1_TMR1SEL_Pos          (12)                                              /*!< CLK_T::CLKSEL1: TMR1SEL Position       */
+#define CLK_CLKSEL1_TMR1SEL_Msk          (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos)                /*!< CLK_T::CLKSEL1: TMR1SEL Mask           */
+
+#define CLK_CLKSEL1_TMR2SEL_Pos          (16)                                              /*!< CLK_T::CLKSEL1: TMR2SEL Position       */
+#define CLK_CLKSEL1_TMR2SEL_Msk          (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos)                /*!< CLK_T::CLKSEL1: TMR2SEL Mask           */
+
+#define CLK_CLKSEL1_TMR3SEL_Pos          (20)                                              /*!< CLK_T::CLKSEL1: TMR3SEL Position       */
+#define CLK_CLKSEL1_TMR3SEL_Msk          (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos)                /*!< CLK_T::CLKSEL1: TMR3SEL Mask           */
+
+#define CLK_CLKSEL1_CLKOSEL_Pos          (28)                                              /*!< CLK_T::CLKSEL1: CLKOSEL Position       */
+#define CLK_CLKSEL1_CLKOSEL_Msk          (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos)                /*!< CLK_T::CLKSEL1: CLKOSEL Mask           */
+
+#define CLK_CLKSEL1_WWDTSEL_Pos          (30)                                              /*!< CLK_T::CLKSEL1: WWDTSEL Position       */
+#define CLK_CLKSEL1_WWDTSEL_Msk          (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos)                /*!< CLK_T::CLKSEL1: WWDTSEL Mask           */
+
+#define CLK_CLKSEL2_EPWM0SEL_Pos         (0)                                               /*!< CLK_T::CLKSEL2: EPWM0SEL Position      */
+#define CLK_CLKSEL2_EPWM0SEL_Msk         (0x1ul << CLK_CLKSEL2_EPWM0SEL_Pos)               /*!< CLK_T::CLKSEL2: EPWM0SEL Mask          */
+
+#define CLK_CLKSEL2_EPWM1SEL_Pos         (1)                                               /*!< CLK_T::CLKSEL2: EPWM1SEL Position      */
+#define CLK_CLKSEL2_EPWM1SEL_Msk         (0x1ul << CLK_CLKSEL2_EPWM1SEL_Pos)               /*!< CLK_T::CLKSEL2: EPWM1SEL Mask          */
+
+#define CLK_CLKSEL2_QSPI0SEL_Pos         (2)                                               /*!< CLK_T::CLKSEL2: QSPI0SEL Position      */
+#define CLK_CLKSEL2_QSPI0SEL_Msk         (0x3ul << CLK_CLKSEL2_QSPI0SEL_Pos)               /*!< CLK_T::CLKSEL2: QSPI0SEL Mask          */
+
+#define CLK_CLKSEL2_SPI0SEL_Pos          (4)                                               /*!< CLK_T::CLKSEL2: SPI0SEL Position       */
+#define CLK_CLKSEL2_SPI0SEL_Msk          (0x3ul << CLK_CLKSEL2_SPI0SEL_Pos)                /*!< CLK_T::CLKSEL2: SPI0SEL Mask           */
+
+#define CLK_CLKSEL2_SPI1SEL_Pos          (6)                                               /*!< CLK_T::CLKSEL2: SPI1SEL Position       */
+#define CLK_CLKSEL2_SPI1SEL_Msk          (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos)                /*!< CLK_T::CLKSEL2: SPI1SEL Mask           */
+
+#define CLK_CLKSEL2_SPI2SEL_Pos          (10)                                              /*!< CLK_T::CLKSEL2: SPI2SEL Position       */
+#define CLK_CLKSEL2_SPI2SEL_Msk          (0x3ul << CLK_CLKSEL2_SPI2SEL_Pos)                /*!< CLK_T::CLKSEL2: SPI2SEL Mask           */
+
+#define CLK_CLKSEL2_BPWM0SEL_Pos         (8)                                               /*!< CLK_T::CLKSEL2: BPWM0SEL Position      */
+#define CLK_CLKSEL2_BPWM0SEL_Msk         (0x1ul << CLK_CLKSEL2_BPWM0SEL_Pos)               /*!< CLK_T::CLKSEL2: BPWM0SEL Mask          */
+
+#define CLK_CLKSEL2_BPWM1SEL_Pos         (9)                                               /*!< CLK_T::CLKSEL2: BPWM1SEL Position      */
+#define CLK_CLKSEL2_BPWM1SEL_Msk         (0x1ul << CLK_CLKSEL2_BPWM1SEL_Pos)               /*!< CLK_T::CLKSEL2: BPWM1SEL Mask          */
+
+#define CLK_CLKSEL2_SPI3SEL_Pos          (12)                                              /*!< CLK_T::CLKSEL2: SPI3SEL Position       */
+#define CLK_CLKSEL2_SPI3SEL_Msk          (0x3ul << CLK_CLKSEL2_SPI3SEL_Pos)                /*!< CLK_T::CLKSEL2: SPI3SEL Mask           */
+
+#define CLK_CLKSEL2_UART0SEL_Pos         (16)                                              /*!< CLK_T::CLKSEL2: UART0SEL Position      */
+#define CLK_CLKSEL2_UART0SEL_Msk         (0x7ul << CLK_CLKSEL2_UART0SEL_Pos)               /*!< CLK_T::CLKSEL2: UART0SEL Mask          */
+
+#define CLK_CLKSEL2_UART1SEL_Pos         (20)                                              /*!< CLK_T::CLKSEL2: UART1SEL Position      */
+#define CLK_CLKSEL2_UART1SEL_Msk         (0x7ul << CLK_CLKSEL2_UART1SEL_Pos)               /*!< CLK_T::CLKSEL2: UART1SEL Mask          */
+
+#define CLK_CLKSEL2_UART2SEL_Pos         (24)                                              /*!< CLK_T::CLKSEL2: UART2SEL Position      */
+#define CLK_CLKSEL2_UART2SEL_Msk         (0x7ul << CLK_CLKSEL2_UART2SEL_Pos)               /*!< CLK_T::CLKSEL2: UART2SEL Mask          */
+
+#define CLK_CLKSEL2_UART3SEL_Pos         (28)                                              /*!< CLK_T::CLKSEL2: UART3SEL Position      */
+#define CLK_CLKSEL2_UART3SEL_Msk         (0x7ul << CLK_CLKSEL2_UART3SEL_Pos)               /*!< CLK_T::CLKSEL2: UART3SEL Mask          */
+
+#define CLK_CLKSEL3_SC0SEL_Pos           (0)                                               /*!< CLK_T::CLKSEL3: SC0SEL Position        */
+#define CLK_CLKSEL3_SC0SEL_Msk           (0x3ul << CLK_CLKSEL3_SC0SEL_Pos)                 /*!< CLK_T::CLKSEL3: SC0SEL Mask            */
+
+#define CLK_CLKSEL3_SC1SEL_Pos           (2)                                               /*!< CLK_T::CLKSEL3: SC1SEL Position        */
+#define CLK_CLKSEL3_SC1SEL_Msk           (0x3ul << CLK_CLKSEL3_SC1SEL_Pos)                 /*!< CLK_T::CLKSEL3: SC1SEL Mask            */
+
+#define CLK_CLKSEL3_SC2SEL_Pos           (4)                                               /*!< CLK_T::CLKSEL3: SC2SEL Position        */
+#define CLK_CLKSEL3_SC2SEL_Msk           (0x3ul << CLK_CLKSEL3_SC2SEL_Pos)                 /*!< CLK_T::CLKSEL3: SC2SEL Mask            */
+
+#define CLK_CLKSEL3_TMR4SEL_Pos          (8)                                               /*!< CLK_T::CLKSEL3: TMR4SEL Position       */
+#define CLK_CLKSEL3_TMR4SEL_Msk          (0x7ul << CLK_CLKSEL3_TMR4SEL_Pos)                /*!< CLK_T::CLKSEL3: TMR4SEL Mask           */
+
+#define CLK_CLKSEL3_TMR5SEL_Pos          (12)                                              /*!< CLK_T::CLKSEL3: TMR5SEL Position       */
+#define CLK_CLKSEL3_TMR5SEL_Msk          (0x7ul << CLK_CLKSEL3_TMR5SEL_Pos)                /*!< CLK_T::CLKSEL3: TMR5SEL Mask           */
+
+#define CLK_CLKSEL3_I2S0SEL_Pos          (16)                                              /*!< CLK_T::CLKSEL3: I2S0SEL Position       */
+#define CLK_CLKSEL3_I2S0SEL_Msk          (0x3ul << CLK_CLKSEL3_I2S0SEL_Pos)                /*!< CLK_T::CLKSEL3: I2S0SEL Mask           */
+
+#define CLK_CLKSEL3_UART4SEL_Pos         (24)                                              /*!< CLK_T::CLKSEL3: UART4SEL Position      */
+#define CLK_CLKSEL3_UART4SEL_Msk         (0x7ul << CLK_CLKSEL3_UART4SEL_Pos)               /*!< CLK_T::CLKSEL3: UART4SEL Mask          */
+
+#define CLK_CLKSEL3_UART5SEL_Pos         (28)                                              /*!< CLK_T::CLKSEL3: UART5SEL Position      */
+#define CLK_CLKSEL3_UART5SEL_Msk         (0x7ul << CLK_CLKSEL3_UART5SEL_Pos)               /*!< CLK_T::CLKSEL3: UART5SEL Mask          */
+
+#define CLK_CLKDIV0_HCLKDIV_Pos          (0)                                               /*!< CLK_T::CLKDIV0: HCLKDIV Position       */
+#define CLK_CLKDIV0_HCLKDIV_Msk          (0xful << CLK_CLKDIV0_HCLKDIV_Pos)                /*!< CLK_T::CLKDIV0: HCLKDIV Mask           */
+
+#define CLK_CLKDIV0_USBDIV_Pos           (4)                                               /*!< CLK_T::CLKDIV0: USBDIV Position        */
+#define CLK_CLKDIV0_USBDIV_Msk           (0xful << CLK_CLKDIV0_USBDIV_Pos)                 /*!< CLK_T::CLKDIV0: USBDIV Mask            */
+
+#define CLK_CLKDIV0_UART0DIV_Pos         (8)                                               /*!< CLK_T::CLKDIV0: UART0DIV Position      */
+#define CLK_CLKDIV0_UART0DIV_Msk         (0xful << CLK_CLKDIV0_UART0DIV_Pos)               /*!< CLK_T::CLKDIV0: UART0DIV Mask          */
+
+#define CLK_CLKDIV0_UART1DIV_Pos         (12)                                              /*!< CLK_T::CLKDIV0: UART1DIV Position      */
+#define CLK_CLKDIV0_UART1DIV_Msk         (0xful << CLK_CLKDIV0_UART1DIV_Pos)               /*!< CLK_T::CLKDIV0: UART1DIV Mask          */
+
+#define CLK_CLKDIV0_EADCDIV_Pos          (16)                                              /*!< CLK_T::CLKDIV0: EADCDIV Position       */
+#define CLK_CLKDIV0_EADCDIV_Msk          (0xfful << CLK_CLKDIV0_EADCDIV_Pos)               /*!< CLK_T::CLKDIV0: EADCDIV Mask           */
+
+#define CLK_CLKDIV0_SDH0DIV_Pos          (24)                                              /*!< CLK_T::CLKDIV0: SDH0DIV Position       */
+#define CLK_CLKDIV0_SDH0DIV_Msk          (0xfful << CLK_CLKDIV0_SDH0DIV_Pos)               /*!< CLK_T::CLKDIV0: SDH0DIV Mask           */
+
+#define CLK_CLKDIV1_SC0DIV_Pos           (0)                                               /*!< CLK_T::CLKDIV1: SC0DIV Position        */
+#define CLK_CLKDIV1_SC0DIV_Msk           (0xfful << CLK_CLKDIV1_SC0DIV_Pos)                /*!< CLK_T::CLKDIV1: SC0DIV Mask            */
+
+#define CLK_CLKDIV1_SC1DIV_Pos           (8)                                               /*!< CLK_T::CLKDIV1: SC1DIV Position        */
+#define CLK_CLKDIV1_SC1DIV_Msk           (0xfful << CLK_CLKDIV1_SC1DIV_Pos)                /*!< CLK_T::CLKDIV1: SC1DIV Mask            */
+
+#define CLK_CLKDIV1_SC2DIV_Pos           (16)                                              /*!< CLK_T::CLKDIV1: SC2DIV Position        */
+#define CLK_CLKDIV1_SC2DIV_Msk           (0xfful << CLK_CLKDIV1_SC2DIV_Pos)                /*!< CLK_T::CLKDIV1: SC2DIV Mask            */
+
+#define CLK_CLKDIV4_UART2DIV_Pos         (0)                                               /*!< CLK_T::CLKDIV4: UART2DIV Position      */
+#define CLK_CLKDIV4_UART2DIV_Msk         (0xful << CLK_CLKDIV4_UART2DIV_Pos)               /*!< CLK_T::CLKDIV4: UART2DIV Mask          */
+
+#define CLK_CLKDIV4_UART3DIV_Pos         (4)                                               /*!< CLK_T::CLKDIV4: UART3DIV Position      */
+#define CLK_CLKDIV4_UART3DIV_Msk         (0xful << CLK_CLKDIV4_UART3DIV_Pos)               /*!< CLK_T::CLKDIV4: UART3DIV Mask          */
+
+#define CLK_CLKDIV4_UART4DIV_Pos         (8)                                               /*!< CLK_T::CLKDIV4: UART4DIV Position      */
+#define CLK_CLKDIV4_UART4DIV_Msk         (0xful << CLK_CLKDIV4_UART4DIV_Pos)               /*!< CLK_T::CLKDIV4: UART4DIV Mask          */
+
+#define CLK_CLKDIV4_UART5DIV_Pos         (12)                                              /*!< CLK_T::CLKDIV4: UART5DIV Position      */
+#define CLK_CLKDIV4_UART5DIV_Msk         (0xful << CLK_CLKDIV4_UART5DIV_Pos)               /*!< CLK_T::CLKDIV4: UART5DIV Mask          */
+
+#define CLK_PLLCTL_FBDIV_Pos             (0)                                               /*!< CLK_T::PLLCTL: FBDIV Position          */
+#define CLK_PLLCTL_FBDIV_Msk             (0x1fful << CLK_PLLCTL_FBDIV_Pos)                 /*!< CLK_T::PLLCTL: FBDIV Mask              */
+
+#define CLK_PLLCTL_INDIV_Pos             (9)                                               /*!< CLK_T::PLLCTL: INDIV Position          */
+#define CLK_PLLCTL_INDIV_Msk             (0x1ful << CLK_PLLCTL_INDIV_Pos)                  /*!< CLK_T::PLLCTL: INDIV Mask              */
+
+#define CLK_PLLCTL_OUTDIV_Pos            (14)                                              /*!< CLK_T::PLLCTL: OUTDIV Position         */
+#define CLK_PLLCTL_OUTDIV_Msk            (0x3ul << CLK_PLLCTL_OUTDIV_Pos)                  /*!< CLK_T::PLLCTL: OUTDIV Mask             */
+
+#define CLK_PLLCTL_PD_Pos                (16)                                              /*!< CLK_T::PLLCTL: PD Position             */
+#define CLK_PLLCTL_PD_Msk                (0x1ul << CLK_PLLCTL_PD_Pos)                      /*!< CLK_T::PLLCTL: PD Mask                 */
+
+#define CLK_PLLCTL_BP_Pos                (17)                                              /*!< CLK_T::PLLCTL: BP Position             */
+#define CLK_PLLCTL_BP_Msk                (0x1ul << CLK_PLLCTL_BP_Pos)                      /*!< CLK_T::PLLCTL: BP Mask                 */
+
+#define CLK_PLLCTL_PLLSRC_Pos            (19)                                              /*!< CLK_T::PLLCTL: PLLSRC Position         */
+#define CLK_PLLCTL_PLLSRC_Msk            (0x1ul << CLK_PLLCTL_PLLSRC_Pos)                  /*!< CLK_T::PLLCTL: PLLSRC Mask             */
+
+#define CLK_PLLCTL_STBSEL_Pos            (23)                                              /*!< CLK_T::PLLCTL: STBSEL Position         */
+#define CLK_PLLCTL_STBSEL_Msk            (0x1ul << CLK_PLLCTL_STBSEL_Pos)                  /*!< CLK_T::PLLCTL: STBSEL Mask             */
+
+#define CLK_STATUS_HXTSTB_Pos            (0)                                               /*!< CLK_T::STATUS: HXTSTB Position         */
+#define CLK_STATUS_HXTSTB_Msk            (0x1ul << CLK_STATUS_HXTSTB_Pos)                  /*!< CLK_T::STATUS: HXTSTB Mask             */
+
+#define CLK_STATUS_LXTSTB_Pos            (1)                                               /*!< CLK_T::STATUS: LXTSTB Position         */
+#define CLK_STATUS_LXTSTB_Msk            (0x1ul << CLK_STATUS_LXTSTB_Pos)                  /*!< CLK_T::STATUS: LXTSTB Mask             */
+
+#define CLK_STATUS_PLLSTB_Pos            (2)                                               /*!< CLK_T::STATUS: PLLSTB Position         */
+#define CLK_STATUS_PLLSTB_Msk            (0x1ul << CLK_STATUS_PLLSTB_Pos)                  /*!< CLK_T::STATUS: PLLSTB Mask             */
+
+#define CLK_STATUS_LIRCSTB_Pos           (3)                                               /*!< CLK_T::STATUS: LIRCSTB Position        */
+#define CLK_STATUS_LIRCSTB_Msk           (0x1ul << CLK_STATUS_LIRCSTB_Pos)                 /*!< CLK_T::STATUS: LIRCSTB Mask            */
+
+#define CLK_STATUS_HIRCSTB_Pos           (4)                                               /*!< CLK_T::STATUS: HIRCSTB Position        */
+#define CLK_STATUS_HIRCSTB_Msk           (0x1ul << CLK_STATUS_HIRCSTB_Pos)                 /*!< CLK_T::STATUS: HIRCSTB Mask            */
+
+#define CLK_STATUS_MIRCSTB_Pos           (5)                                               /*!< CLK_T::STATUS: MIRCSTB Position        */
+#define CLK_STATUS_MIRCSTB_Msk           (0x1ul << CLK_STATUS_MIRCSTB_Pos)                 /*!< CLK_T::STATUS: MIRCSTB Mask            */
+
+#define CLK_STATUS_HIRC48STB_Pos         (6)                                               /*!< CLK_T::STATUS: HIRC48STB Position      */
+#define CLK_STATUS_HIRC48STB_Msk         (0x1ul << CLK_STATUS_HIRC48STB_Pos)               /*!< CLK_T::STATUS: HIRC48STB Mask          */
+
+#define CLK_STATUS_CLKSFAIL_Pos          (7)                                               /*!< CLK_T::STATUS: CLKSFAIL Position       */
+#define CLK_STATUS_CLKSFAIL_Msk          (0x1ul << CLK_STATUS_CLKSFAIL_Pos)                /*!< CLK_T::STATUS: CLKSFAIL Mask           */
+
+#define CLK_STATUS_EXTLXTSTB_Pos         (8)                                               /*!< CLK_T::STATUS: EXTLXTSTB Position      */
+#define CLK_STATUS_EXTLXTSTB_Msk         (0x1ul << CLK_STATUS_EXTLXTSTB_Pos)               /*!< CLK_T::STATUS: EXTLXTSTB Mask          */
+
+#define CLK_STATUS_LIRC32STB_Pos         (9)                                               /*!< CLK_T::STATUS: LIRC32STB Position      */
+#define CLK_STATUS_LIRC32STB_Msk         (0x1ul << CLK_STATUS_LIRC32STB_Pos)               /*!< CLK_T::STATUS: LIRC32STB Mask          */
+
+#define CLK_CLKOCTL_FREQSEL_Pos          (0)                                               /*!< CLK_T::CLKOCTL: FREQSEL Position       */
+#define CLK_CLKOCTL_FREQSEL_Msk          (0xful << CLK_CLKOCTL_FREQSEL_Pos)                /*!< CLK_T::CLKOCTL: FREQSEL Mask           */
+
+#define CLK_CLKOCTL_CLKOEN_Pos           (4)                                               /*!< CLK_T::CLKOCTL: CLKOEN Position        */
+#define CLK_CLKOCTL_CLKOEN_Msk           (0x1ul << CLK_CLKOCTL_CLKOEN_Pos)                 /*!< CLK_T::CLKOCTL: CLKOEN Mask            */
+
+#define CLK_CLKOCTL_DIV1EN_Pos           (5)                                               /*!< CLK_T::CLKOCTL: DIV1EN Position        */
+#define CLK_CLKOCTL_DIV1EN_Msk           (0x1ul << CLK_CLKOCTL_DIV1EN_Pos)                 /*!< CLK_T::CLKOCTL: DIV1EN Mask            */
+
+#define CLK_CLKOCTL_CLK1HZEN_Pos         (6)                                               /*!< CLK_T::CLKOCTL: CLK1HZEN Position      */
+#define CLK_CLKOCTL_CLK1HZEN_Msk         (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos)               /*!< CLK_T::CLKOCTL: CLK1HZEN Mask          */
+
+#define CLK_CLKDCTL_HXTFDEN_Pos          (4)                                               /*!< CLK_T::CLKDCTL: HXTFDEN Position       */
+#define CLK_CLKDCTL_HXTFDEN_Msk          (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos)                /*!< CLK_T::CLKDCTL: HXTFDEN Mask           */
+
+#define CLK_CLKDCTL_HXTFIEN_Pos          (5)                                               /*!< CLK_T::CLKDCTL: HXTFIEN Position       */
+#define CLK_CLKDCTL_HXTFIEN_Msk          (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos)                /*!< CLK_T::CLKDCTL: HXTFIEN Mask           */
+
+#define CLK_CLKDCTL_HXTFDSEL_Pos         (6)                                               /*!< CLK_T::CLKDCTL: HXTFDSEL Position      */
+#define CLK_CLKDCTL_HXTFDSEL_Msk         (0x1ul << CLK_CLKDCTL_HXTFDSEL_Pos)               /*!< CLK_T::CLKDCTL: HXTFDSEL Mask          */
+
+#define CLK_CLKDCTL_LXTFDEN_Pos          (12)                                              /*!< CLK_T::CLKDCTL: LXTFDEN Position       */
+#define CLK_CLKDCTL_LXTFDEN_Msk          (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos)                /*!< CLK_T::CLKDCTL: LXTFDEN Mask           */
+
+#define CLK_CLKDCTL_LXTFIEN_Pos          (13)                                              /*!< CLK_T::CLKDCTL: LXTFIEN Position       */
+#define CLK_CLKDCTL_LXTFIEN_Msk          (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos)                /*!< CLK_T::CLKDCTL: LXTFIEN Mask           */
+
+#define CLK_CLKDCTL_HXTFQDEN_Pos         (16)                                              /*!< CLK_T::CLKDCTL: HXTFQDEN Position      */
+#define CLK_CLKDCTL_HXTFQDEN_Msk         (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos)               /*!< CLK_T::CLKDCTL: HXTFQDEN Mask          */
+
+#define CLK_CLKDCTL_HXTFQIEN_Pos         (17)                                              /*!< CLK_T::CLKDCTL: HXTFQIEN Position      */
+#define CLK_CLKDCTL_HXTFQIEN_Msk         (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos)               /*!< CLK_T::CLKDCTL: HXTFQIEN Mask          */
+
+#define CLK_CLKDSTS_HXTFIF_Pos           (0)                                               /*!< CLK_T::CLKDSTS: HXTFIF Position        */
+#define CLK_CLKDSTS_HXTFIF_Msk           (0x1ul << CLK_CLKDSTS_HXTFIF_Pos)                 /*!< CLK_T::CLKDSTS: HXTFIF Mask            */
+
+#define CLK_CLKDSTS_LXTFIF_Pos           (1)                                               /*!< CLK_T::CLKDSTS: LXTFIF Position        */
+#define CLK_CLKDSTS_LXTFIF_Msk           (0x1ul << CLK_CLKDSTS_LXTFIF_Pos)                 /*!< CLK_T::CLKDSTS: LXTFIF Mask            */
+
+#define CLK_CLKDSTS_HXTFQIF_Pos          (8)                                               /*!< CLK_T::CLKDSTS: HXTFQIF Position       */
+#define CLK_CLKDSTS_HXTFQIF_Msk          (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos)                /*!< CLK_T::CLKDSTS: HXTFQIF Mask           */
+
+#define CLK_CDUPB_UPERBD_Pos             (0)                                               /*!< CLK_T::CDUPB: UPERBD Position          */
+#define CLK_CDUPB_UPERBD_Msk             (0x3fful << CLK_CDUPB_UPERBD_Pos)                 /*!< CLK_T::CDUPB: UPERBD Mask              */
+
+#define CLK_CDLOWB_LOWERBD_Pos           (0)                                               /*!< CLK_T::CDLOWB: LOWERBD Position        */
+#define CLK_CDLOWB_LOWERBD_Msk           (0x3fful << CLK_CDLOWB_LOWERBD_Pos)               /*!< CLK_T::CDLOWB: LOWERBD Mask            */
+
+#define CLK_PMUCTL_PDMSEL_Pos            (0)                                               /*!< CLK_T::PMUCTL: PDMSEL Position         */
+#define CLK_PMUCTL_PDMSEL_Msk            (0x7ul<< CLK_PMUCTL_PDMSEL_Pos)                   /*!< CLK_T::PMUCTL: PDMSEL Mask             */
+
+#define CLK_PMUCTL_VDROPEN_Pos           (4)                                               /*!< CLK_T::PMUCTL: VDROPEN Position        */
+#define CLK_PMUCTL_VDROPEN_Msk           (0x1ul<< CLK_PMUCTL_VDROPEN_Pos)                  /*!< CLK_T::PMUCTL: VDROPEN Mask            */
+
+#define CLK_PMUCTL_WRBUSY_Pos            (7)                                               /*!< CLK_T::PMUCTL: WRBUSY Position         */
+#define CLK_PMUCTL_WRBUSY_Msk            (0x1ul<< CLK_PMUCTL_WRBUSY_Pos)                   /*!< CLK_T::PMUCTL: WRBUSY Mask             */
+
+#define CLK_PMUCTL_WKTMREN_Pos           (8)                                               /*!< CLK_T::PMUCTL: WKTMREN Position        */
+#define CLK_PMUCTL_WKTMREN_Msk           (0x1ul<< CLK_PMUCTL_WKTMREN_Pos)                  /*!< CLK_T::PMUCTL: WKTMREN Mask            */
+
+#define CLK_PMUCTL_WKTMRIS_Pos           (9)                                               /*!< CLK_T::PMUCTL: WKTMRIS Position        */
+#define CLK_PMUCTL_WKTMRIS_Msk           (0x7ul<< CLK_PMUCTL_WKTMRIS_Pos)                  /*!< CLK_T::PMUCTL: WKTMRIS Mask            */
+
+#define CLK_PMUCTL_WKPINEN_Pos           (16)                                              /*!< CLK_T::PMUCTL: WKPINEN Position        */
+#define CLK_PMUCTL_WKPINEN_Msk           (0x3ul<< CLK_PMUCTL_WKPINEN_Pos)                  /*!< CLK_T::PMUCTL: WKPINEN Mask            */
+
+#define CLK_PMUCTL_WKPINEN0_Pos          (16)                                              /*!< CLK_T::PMUCTL: WKPINEN0 Position       */
+#define CLK_PMUCTL_WKPINEN0_Msk          (0x3ul<< CLK_PMUCTL_WKPINEN0_Pos)                 /*!< CLK_T::PMUCTL: WKPINEN0 Mask           */
+
+#define CLK_PMUCTL_ACMPSPWK_Pos          (18)                                              /*!< CLK_T::PMUCTL: ACMPSPWK Position       */
+#define CLK_PMUCTL_ACMPSPWK_Msk          (0x1ul<< CLK_PMUCTL_ACMPSPWK_Pos)                 /*!< CLK_T::PMUCTL: ACMPSPWK Mask           */
+
+#define CLK_PMUCTL_TAMPERWK_Pos          (19)                                              /*!< CLK_T::PMUCTL: TAMPERWK Position       */
+#define CLK_PMUCTL_TAMPERWK_Msk          (0x1ul<< CLK_PMUCTL_TAMPERWK_Pos)                 /*!< CLK_T::PMUCTL: TAMPERWK Mask           */
+
+#define CLK_PMUCTL_RTCWKEN_Pos           (23)                                              /*!< CLK_T::PMUCTL: RTCWKEN Position        */
+#define CLK_PMUCTL_RTCWKEN_Msk           (0x1ul<< CLK_PMUCTL_RTCWKEN_Pos)                  /*!< CLK_T::PMUCTL: RTCWKEN Mask            */
+
+#define CLK_PMUCTL_WKPINEN1_Pos          (24)                                              /*!< CLK_T::PMUCTL: WKPINEN1 Position       */
+#define CLK_PMUCTL_WKPINEN1_Msk          (0x3ul << CLK_PMUCTL_WKPINEN1_Pos)                /*!< CLK_T::PMUCTL: WKPINEN1 Mask           */
+
+#define CLK_PMUCTL_WKPINEN2_Pos          (26)                                              /*!< CLK_T::PMUCTL: WKPINEN2 Position       */
+#define CLK_PMUCTL_WKPINEN2_Msk          (0x3ul << CLK_PMUCTL_WKPINEN2_Pos)                /*!< CLK_T::PMUCTL: WKPINEN2 Mask           */
+
+#define CLK_PMUCTL_WKPINEN3_Pos          (28)                                              /*!< CLK_T::PMUCTL: WKPINEN3 Position       */
+#define CLK_PMUCTL_WKPINEN3_Msk          (0x3ul << CLK_PMUCTL_WKPINEN3_Pos)                /*!< CLK_T::PMUCTL: WKPINEN3 Mask           */
+
+#define CLK_PMUCTL_WKPINEN4_Pos          (30)                                              /*!< CLK_T::PMUCTL: WKPINEN4 Position       */
+#define CLK_PMUCTL_WKPINEN4_Msk          (0x3ul << CLK_PMUCTL_WKPINEN4_Pos)                /*!< CLK_T::PMUCTL: WKPINEN4 Mask           */
+
+#define CLK_PMUSTS_PINWK0_Pos            (0)                                               /*!< CLK_T::PMUSTS: PINWK0 Position         */
+#define CLK_PMUSTS_PINWK0_Msk            (0x1ul << CLK_PMUSTS_PINWK0_Pos)                  /*!< CLK_T::PMUSTS: PINWK0 Mask             */
+
+#define CLK_PMUSTS_PINWK_Pos             (0)                                               /*!< CLK_T::PMUSTS: PINWK Position          */
+#define CLK_PMUSTS_PINWK_Msk             (0x1ul << CLK_PMUSTS_PINWK_Pos)                   /*!< CLK_T::PMUSTS: PINWK Mask              */
+
+#define CLK_PMUSTS_TMRWK_Pos             (1)                                               /*!< CLK_T::PMUSTS: TMRWK Position          */
+#define CLK_PMUSTS_TMRWK_Msk             (0x1ul << CLK_PMUSTS_TMRWK_Pos)                   /*!< CLK_T::PMUSTS: TMRWK Mask              */
+
+#define CLK_PMUSTS_RTCWK_Pos             (2)                                               /*!< CLK_T::PMUSTS: RTCWK Position          */
+#define CLK_PMUSTS_RTCWK_Msk             (0x1ul << CLK_PMUSTS_RTCWK_Pos)                   /*!< CLK_T::PMUSTS: RTCWK Mask              */
+
+#define CLK_PMUSTS_PINWK1_Pos            (3)                                               /*!< CLK_T::PMUSTS: PINWK1 Position         */
+#define CLK_PMUSTS_PINWK1_Msk            (0x1ul << CLK_PMUSTS_PINWK1_Pos)                  /*!< CLK_T::PMUSTS: PINWK1 Mask             */
+
+#define CLK_PMUSTS_PINWK2_Pos            (4)                                               /*!< CLK_T::PMUSTS: PINWK2 Position         */
+#define CLK_PMUSTS_PINWK2_Msk            (0x1ul << CLK_PMUSTS_PINWK2_Pos)                  /*!< CLK_T::PMUSTS: PINWK2 Mask             */
+
+#define CLK_PMUSTS_PINWK3_Pos            (5)                                               /*!< CLK_T::PMUSTS: PINWK3 Position         */
+#define CLK_PMUSTS_PINWK3_Msk            (0x1ul << CLK_PMUSTS_PINWK3_Pos)                  /*!< CLK_T::PMUSTS: PINWK3 Mask             */
+
+#define CLK_PMUSTS_PINWK4_Pos            (6)                                               /*!< CLK_T::PMUSTS: PINWK4 Position         */
+#define CLK_PMUSTS_PINWK4_Msk            (0x1ul << CLK_PMUSTS_PINWK4_Pos)                  /*!< CLK_T::PMUSTS: PINWK4 Mask             */
+
+#define CLK_PMUSTS_GPAWK_Pos             (8)                                               /*!< CLK_T::PMUSTS: GPAWK Position          */
+#define CLK_PMUSTS_GPAWK_Msk             (0x1ul << CLK_PMUSTS_GPAWK_Pos)                   /*!< CLK_T::PMUSTS: GPAWK Mask              */
+
+#define CLK_PMUSTS_GPBWK_Pos             (9)                                               /*!< CLK_T::PMUSTS: GPBWK Position          */
+#define CLK_PMUSTS_GPBWK_Msk             (0x1ul << CLK_PMUSTS_GPBWK_Pos)                   /*!< CLK_T::PMUSTS: GPBWK Mask              */
+
+#define CLK_PMUSTS_GPCWK_Pos             (10)                                              /*!< CLK_T::PMUSTS: GPCWK Position          */
+#define CLK_PMUSTS_GPCWK_Msk             (0x1ul << CLK_PMUSTS_GPCWK_Pos)                   /*!< CLK_T::PMUSTS: GPCWK Mask              */
+
+#define CLK_PMUSTS_GPDWK_Pos             (11)                                              /*!< CLK_T::PMUSTS: GPDWK Position          */
+#define CLK_PMUSTS_GPDWK_Msk             (0x1ul << CLK_PMUSTS_GPDWK_Pos)                   /*!< CLK_T::PMUSTS: GPDWK Mask              */
+
+#define CLK_PMUSTS_LVRWK_Pos             (12)                                              /*!< CLK_T::PMUSTS: LVRWK Position          */
+#define CLK_PMUSTS_LVRWK_Msk             (0x1ul << CLK_PMUSTS_LVRWK_Pos)                   /*!< CLK_T::PMUSTS: LVRWK Mask              */
+
+#define CLK_PMUSTS_BODWK_Pos             (13)                                              /*!< CLK_T::PMUSTS: BODWK Position          */
+#define CLK_PMUSTS_BODWK_Msk             (0x1ul << CLK_PMUSTS_BODWK_Pos)                   /*!< CLK_T::PMUSTS: BODWK Mask              */
+
+#define CLK_PMUSTS_ACMPWK_Pos            (14)                                              /*!< CLK_T::PMUSTS: ACMPWK Position         */
+#define CLK_PMUSTS_ACMPWK_Msk            (0x1ul << CLK_PMUSTS_ACMPWK_Pos)                  /*!< CLK_T::PMUSTS: ACMPWK Mask             */
+
+#define CLK_PMUSTS_TAMPERWK_Pos          (15)                                              /*!< CLK_T::PMUSTS: TAMPERWK Position       */
+#define CLK_PMUSTS_TAMPERWK_Msk          (0x1ul << CLK_PMUSTS_TAMPERWK_Pos)                /*!< CLK_T::PMUSTS: TAMPERWK Mask           */
+
+#define CLK_PMUSTS_CLRWK_Pos             (31)                                              /*!< CLK_T::PMUSTS: CLRWK Position          */
+#define CLK_PMUSTS_CLRWK_Msk             (0x1ul << CLK_PMUSTS_CLRWK_Pos)                   /*!< CLK_T::PMUSTS: CLRWK Mask              */
+
+#define CLK_SWKDBCTL_SWKDBCLKSEL_Pos     (0)                                               /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Position  */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_Msk     (0xFul<< CLK_SWKDBCTL_SWKDBCLKSEL_Pos)            /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Mask      */
+
+#define CLK_PASWKCTL_WKEN_Pos            (0)                                               /*!< CLK_T::PASWKCTL: WKEN Position         */
+#define CLK_PASWKCTL_WKEN_Msk            (0x1ul << CLK_PASWKCTL_WKEN_Pos)                  /*!< CLK_T::PASWKCTL: WKEN Mask             */
+
+#define CLK_PASWKCTL_PRWKEN_Pos          (1)                                               /*!< CLK_T::PASWKCTL: PRWKEN Position       */
+#define CLK_PASWKCTL_PRWKEN_Msk          (0x1ul << CLK_PASWKCTL_PRWKEN_Pos)                /*!< CLK_T::PASWKCTL: PRWKEN Mask           */
+
+#define CLK_PASWKCTL_PFWKEN_Pos          (2)                                               /*!< CLK_T::PASWKCTL: PFWKEN Position       */
+#define CLK_PASWKCTL_PFWKEN_Msk          (0x1ul << CLK_PASWKCTL_PFWKEN_Pos)                /*!< CLK_T::PASWKCTL: PFWKEN Mask           */
+
+#define CLK_PASWKCTL_WKPSEL_Pos          (4)                                               /*!< CLK_T::PASWKCTL: WKPSEL Position       */
+#define CLK_PASWKCTL_WKPSEL_Msk          (0xful << CLK_PASWKCTL_WKPSEL_Pos)                /*!< CLK_T::PASWKCTL: WKPSEL Mask           */
+
+#define CLK_PASWKCTL_DBEN_Pos            (8)                                               /*!< CLK_T::PASWKCTL: DBEN Position         */
+#define CLK_PASWKCTL_DBEN_Msk            (0x1ul << CLK_PASWKCTL_DBEN_Pos)                  /*!< CLK_T::PASWKCTL: DBEN Mask             */
+
+#define CLK_PBSWKCTL_WKEN_Pos            (0)                                               /*!< CLK_T::PBSWKCTL: WKEN Position         */
+#define CLK_PBSWKCTL_WKEN_Msk            (0x1ul << CLK_PBSWKCTL_WKEN_Pos)                  /*!< CLK_T::PBSWKCTL: WKEN Mask             */
+
+#define CLK_PBSWKCTL_PRWKEN_Pos          (1)                                               /*!< CLK_T::PBSWKCTL: PRWKEN Position       */
+#define CLK_PBSWKCTL_PRWKEN_Msk          (0x1ul << CLK_PBSWKCTL_PRWKEN_Pos)                /*!< CLK_T::PBSWKCTL: PRWKEN Mask           */
+
+#define CLK_PBSWKCTL_PFWKEN_Pos          (2)                                               /*!< CLK_T::PBSWKCTL: PFWKEN Position       */
+#define CLK_PBSWKCTL_PFWKEN_Msk          (0x1ul << CLK_PBSWKCTL_PFWKEN_Pos)                /*!< CLK_T::PBSWKCTL: PFWKEN Mask           */
+
+#define CLK_PBSWKCTL_WKPSEL_Pos          (4)                                               /*!< CLK_T::PBSWKCTL: WKPSEL Position       */
+#define CLK_PBSWKCTL_WKPSEL_Msk          (0xful << CLK_PBSWKCTL_WKPSEL_Pos)                /*!< CLK_T::PBSWKCTL: WKPSEL Mask           */
+
+#define CLK_PBSWKCTL_DBEN_Pos            (8)                                               /*!< CLK_T::PBSWKCTL: DBEN Position         */
+#define CLK_PBSWKCTL_DBEN_Msk            (0x1ul << CLK_PBSWKCTL_DBEN_Pos)                  /*!< CLK_T::PBSWKCTL: DBEN Mask             */
+
+#define CLK_PCSWKCTL_WKEN_Pos            (0)                                               /*!< CLK_T::PCSWKCTL: WKEN Position         */
+#define CLK_PCSWKCTL_WKEN_Msk            (0x1ul << CLK_PCSWKCTL_WKEN_Pos)                  /*!< CLK_T::PCSWKCTL: WKEN Mask             */
+
+#define CLK_PCSWKCTL_PRWKEN_Pos          (1)                                               /*!< CLK_T::PCSWKCTL: PRWKEN Position       */
+#define CLK_PCSWKCTL_PRWKEN_Msk          (0x1ul << CLK_PCSWKCTL_PRWKEN_Pos)                /*!< CLK_T::PCSWKCTL: PRWKEN Mask           */
+
+#define CLK_PCSWKCTL_PFWKEN_Pos          (2)                                               /*!< CLK_T::PCSWKCTL: PFWKEN Position       */
+#define CLK_PCSWKCTL_PFWKEN_Msk          (0x1ul << CLK_PCSWKCTL_PFWKEN_Pos)                /*!< CLK_T::PCSWKCTL: PFWKEN Mask           */
+
+#define CLK_PCSWKCTL_WKPSEL_Pos          (4)                                               /*!< CLK_T::PCSWKCTL: WKPSEL Position       */
+#define CLK_PCSWKCTL_WKPSEL_Msk          (0xful << CLK_PCSWKCTL_WKPSEL_Pos)                /*!< CLK_T::PCSWKCTL: WKPSEL Mask           */
+
+#define CLK_PCSWKCTL_DBEN_Pos            (8)                                               /*!< CLK_T::PCSWKCTL: DBEN Position         */
+#define CLK_PCSWKCTL_DBEN_Msk            (0x1ul << CLK_PCSWKCTL_DBEN_Pos)                  /*!< CLK_T::PCSWKCTL: DBEN Mask             */
+
+#define CLK_PDSWKCTL_WKEN_Pos            (0)                                               /*!< CLK_T::PDSWKCTL: WKEN Position         */
+#define CLK_PDSWKCTL_WKEN_Msk            (0x1ul << CLK_PDSWKCTL_WKEN_Pos)                  /*!< CLK_T::PDSWKCTL: WKEN Mask             */
+
+#define CLK_PDSWKCTL_PRWKEN_Pos          (1)                                               /*!< CLK_T::PDSWKCTL: PRWKEN Position       */
+#define CLK_PDSWKCTL_PRWKEN_Msk          (0x1ul << CLK_PDSWKCTL_PRWKEN_Pos)                /*!< CLK_T::PDSWKCTL: PRWKEN Mask           */
+
+#define CLK_PDSWKCTL_PFWKEN_Pos          (2)                                               /*!< CLK_T::PDSWKCTL: PFWKEN Position       */
+#define CLK_PDSWKCTL_PFWKEN_Msk          (0x1ul << CLK_PDSWKCTL_PFWKEN_Pos)                /*!< CLK_T::PDSWKCTL: PFWKEN Mask           */
+
+#define CLK_PDSWKCTL_WKPSEL_Pos          (4)                                               /*!< CLK_T::PDSWKCTL: WKPSEL Position       */
+#define CLK_PDSWKCTL_WKPSEL_Msk          (0xful << CLK_PDSWKCTL_WKPSEL_Pos)                /*!< CLK_T::PDSWKCTL: WKPSEL Mask           */
+
+#define CLK_PDSWKCTL_DBEN_Pos            (8)                                               /*!< CLK_T::PDSWKCTL: DBEN Position         */
+#define CLK_PDSWKCTL_DBEN_Msk            (0x1ul << CLK_PDSWKCTL_DBEN_Pos)                  /*!< CLK_T::PDSWKCTL: DBEN Mask             */
+
+#define CLK_IOPDCTL_IOHR_Pos             (0)                                               /*!< CLK_T::IOPDCTL: IOHR Position          */
+#define CLK_IOPDCTL_IOHR_Msk             (0x1ul << CLK_IOPDCTL_IOHR_Pos)                   /*!< CLK_T::IOPDCTL: IOHR Mask              */
+
+#define CLK_HXTFSEL_HXTFSEL_Pos          (0)                                               /*!< CLK_T::HXTFSEL: HXTFSEL Position       */
+#define CLK_HXTFSEL_HXTFSEL_Msk          (0x1ul << CLK_HXTFSEL_HXTFSEL_Pos)                /*!< CLK_T::HXTFSEL: HXTFSEL Mask           */
+
+
+/**@}*/ /* CLK_CONST */
+/**@}*/ /* end of CLK register group */
+/**@}*/ /* end of REGISTER group */
+
+#endif /* __CLK_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/crc_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/crc_reg.h
new file mode 100644
index 0000000000..4fe1913823
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/crc_reg.h
@@ -0,0 +1,153 @@
+/**************************************************************************//**
+ * @file     crc_reg.h
+ * @version  V1.00
+ * @brief    CRC register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __CRC_REG_H__
+#define __CRC_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+
+/*---------------------- Cyclic Redundancy Check Controller -------------------------*/
+/**
+    @addtogroup CRC Cyclic Redundancy Check Controller(CRC)
+    Memory Mapped Structure for CRC Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var CRC_T::CTL
+     * Offset: 0x00  CRC Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CRCEN     |CRC Channel Generator Enable Bit
+     * |        |          |Set this bit 1 to enable CRC generator for CRC operation.
+     * |        |          |0 = No effect.
+     * |        |          |1 = CRC operation generator is active.
+     * |[1]     |CHKSINIT  |Checksum Initialization
+     * |        |          |Set this bit will auto reload SEED (CRC_SEED [31:0]) to CHECKSUM (CRC_CHECKSUM[31:0]) as CRC operation initial value.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reload SEED value to CHECKSUM register as CRC operation initial checksum value.
+     * |        |          |The others contents of CRC_CTL register will not be cleared.
+     * |        |          |Note1: This bit will be cleared automatically
+     * |        |          |Note2: Setting this bit will reload the seed value from CRC_SEED register as checksum initial value.
+     * |[24]    |DATREV    |Write Data Bit Order Reverse Enable Bit
+     * |        |          |This bit is used to enable the bit order reverse function per byte for write data value DATA (CRC_DATA[31:0]) in CRC_DAT register.
+     * |        |          |0 = Bit order reversed for CRC_DATA write data in Disabled.
+     * |        |          |1 = Bit order reversed for CRC_DATA write data in Enabled (per byte).
+     * |        |          |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
+     * |[25]    |CHKSREV   |Checksum Bit Order Reverse Enable Bit
+     * |        |          |This bit is used to enable the bit order reverse function for checksum result CHECKSUM (CRC_CHECKSUM[31:0]).
+     * |        |          |0 = Bit order reverse for CRC CHECKSUMCRC checksum Disabled.
+     * |        |          |1 = Bit order reverse for CRC CHECKSUMCRC checksum Enabled.
+     * |        |          |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse result for CRC checksum is 0x74F0DEBB.
+     * |[26]    |DATFMT    |Write Data 1's Complement Enable Bit
+     * |        |          |This bit is used to enable the 1's complement function for write data value DATA (CRC_DATA[31:0]).
+     * |        |          |0 = 1's complement for CRC_DATA writes data in Disabled.
+     * |        |          |1 = 1's complement for CRC_DATA writes data in Enabled.
+     * |[27]    |CHKSFMT   |Checksum 1's Complement Enable Bit
+     * |        |          |This bit is used to enable the 1's complement function for checksum result in CHECKSUM (CRC_CHECKSUM[31:0]) register.
+     * |        |          |0 = 1's complement for CRC CHECKSUM Disabled.
+     * |        |          |1 = 1's complement for CRC CHECKSUMCRC Enabled.
+     * |[29:28] |DATLEN    |CPU Write Data Length
+     * |        |          |This field indicates the valid write data length of DATA (CRC_DAT[31:0]).
+     * |        |          |00 = Data length is 8-bit mode.
+     * |        |          |01 = Data length is 16-bit mode.
+     * |        |          |1x = Data length is 32-bit mode.
+     * |        |          |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]
+     * |[31:30] |CRCMODE   |CRC Polynomial Mode
+     * |        |          |This field indicates the CRC operation polynomial mode.
+     * |        |          |00 = CRC-CCITT Polynomial mode.
+     * |        |          |01 = CRC-8 Polynomial mode.
+     * |        |          |10 = CRC-16 Polynomial mode.
+     * |        |          |11 = CRC-32 Polynomial mode.
+     * @var CRC_T::DAT
+     * Offset: 0x04  CRC Write Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DATA      |CRC Write Data Bits
+     * |        |          |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
+     * |        |          |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
+     * @var CRC_T::SEED
+     * Offset: 0x08  CRC Seed Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SEED      |CRC Seed Value
+     * |        |          |This field indicates the CRC seed value.
+     * |        |          |Note1: This field SEED value will be reloaded to as checksum initial value CHECKSUM (CRC_CHECKSUM[31:0]) register) after perform CRC engine reset, CHKSINIT (CRC_CTL[1]) to 1.
+     * |        |          |Note2: The valid bits of CRC_SEED[31:0] is correlated to CRCMODE (CRC_CTL[31:30]).
+     * @var CRC_T::CHECKSUM
+     * Offset: 0x0C  CRC Checksum Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CHECKSUM  |CRC Checksum Results
+     * |        |          |This field indicates the CRC checksum result.
+     * |        |          |Note: The valid bits of CRC_CHECKSUM[31:0] is correlated to CRCMODE (CRC_CTL[31:30]).
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] CRC Control Register                                             */
+    __IO uint32_t DAT;                   /*!< [0x0004] CRC Write Data Register                                          */
+    __IO uint32_t SEED;                  /*!< [0x0008] CRC Seed Register                                                */
+    __I  uint32_t CHECKSUM;              /*!< [0x000c] CRC Checksum Register                                            */
+
+} CRC_T;
+
+/**
+    @addtogroup CRC_CONST CRC Bit Field Definition
+    Constant Definitions for CRC Controller
+  @{
+*/
+
+#define CRC_CTL_CRCEN_Pos                (0)                                               /*!< CRC_T::CTL: CRCEN Position             */
+#define CRC_CTL_CRCEN_Msk                (0x1ul << CRC_CTL_CRCEN_Pos)                      /*!< CRC_T::CTL: CRCEN Mask                 */
+
+#define CRC_CTL_CHKSINIT_Pos             (1)                                               /*!< CRC_T::CTL: CHKSINIT Position          */
+#define CRC_CTL_CHKSINIT_Msk             (0x1ul << CRC_CTL_CHKSINIT_Pos)                   /*!< CRC_T::CTL: CHKSINIT Mask              */
+
+#define CRC_CTL_DATREV_Pos               (24)                                              /*!< CRC_T::CTL: DATREV Position            */
+#define CRC_CTL_DATREV_Msk               (0x1ul << CRC_CTL_DATREV_Pos)                     /*!< CRC_T::CTL: DATREV Mask                */
+
+#define CRC_CTL_CHKSREV_Pos              (25)                                              /*!< CRC_T::CTL: CHKSREV Position           */
+#define CRC_CTL_CHKSREV_Msk              (0x1ul << CRC_CTL_CHKSREV_Pos)                    /*!< CRC_T::CTL: CHKSREV Mask               */
+
+#define CRC_CTL_DATFMT_Pos               (26)                                              /*!< CRC_T::CTL: DATFMT Position            */
+#define CRC_CTL_DATFMT_Msk               (0x1ul << CRC_CTL_DATFMT_Pos)                     /*!< CRC_T::CTL: DATFMT Mask                */
+
+#define CRC_CTL_CHKSFMT_Pos              (27)                                              /*!< CRC_T::CTL: CHKSFMT Position           */
+#define CRC_CTL_CHKSFMT_Msk              (0x1ul << CRC_CTL_CHKSFMT_Pos)                    /*!< CRC_T::CTL: CHKSFMT Mask               */
+
+#define CRC_CTL_DATLEN_Pos               (28)                                              /*!< CRC_T::CTL: DATLEN Position            */
+#define CRC_CTL_DATLEN_Msk               (0x3ul << CRC_CTL_DATLEN_Pos)                     /*!< CRC_T::CTL: DATLEN Mask                */
+
+#define CRC_CTL_CRCMODE_Pos              (30)                                              /*!< CRC_T::CTL: CRCMODE Position           */
+#define CRC_CTL_CRCMODE_Msk              (0x3ul << CRC_CTL_CRCMODE_Pos)                    /*!< CRC_T::CTL: CRCMODE Mask               */
+
+#define CRC_DAT_DATA_Pos                 (0)                                               /*!< CRC_T::DAT: DATA Position              */
+#define CRC_DAT_DATA_Msk                 (0xfffffffful << CRC_DAT_DATA_Pos)                /*!< CRC_T::DAT: DATA Mask                  */
+
+#define CRC_SEED_SEED_Pos                (0)                                               /*!< CRC_T::SEED: SEED Position             */
+#define CRC_SEED_SEED_Msk                (0xfffffffful << CRC_SEED_SEED_Pos)               /*!< CRC_T::SEED: SEED Mask                 */
+
+#define CRC_CHECKSUM_CHECKSUM_Pos        (0)                                               /*!< CRC_T::CHECKSUM: CHECKSUM Position     */
+#define CRC_CHECKSUM_CHECKSUM_Msk        (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos)       /*!< CRC_T::CHECKSUM: CHECKSUM Mask         */
+
+/**@}*/ /* CRC_CONST */
+/**@}*/ /* end of CRC register group */
+/**@}*/ /* end of REGISTER group */
+
+#endif /* __CLK_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/crpt_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/crpt_reg.h
new file mode 100644
index 0000000000..ddffb2ba95
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/crpt_reg.h
@@ -0,0 +1,2083 @@
+/**************************************************************************//**
+* @file     crpt_reg.h
+* @version  V1.00
+* @brief    CRPT register definition header file
+*
+* @copyright SPDX-License-Identifier: Apache-2.0
+* @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __CRPT_REG_H__
+#define __CRPT_REG_H__
+
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+
+/*---------------------- Cryptographic Accelerator -------------------------*/
+/**
+    @addtogroup CRPT Cryptographic Accelerator(CRPT)
+    Memory Mapped Structure for CRPT Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var CRPT_T::INTEN
+     * Offset: 0x00  Crypto Interrupt Enable Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |AESIEN    |AES Interrupt Enable Bit
+     * |        |          |0 = AES interrupt Disabled.
+     * |        |          |1 = AES interrupt Enabled.
+     * |        |          |Note: In DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine.
+     * |        |          |In Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation.
+     * |[1]     |AESEIEN   |AES Error Flag Enable Bit
+     * |        |          |0 = AES error interrupt flag Disabled.
+     * |        |          |1 = AES error interrupt flag Enabled.
+     * |[16]    |PRNGIEN   |PRNG Interrupt Enable Bit
+     * |        |          |0 = PRNG interrupt Disabled.
+     * |        |          |1 = PRNG interrupt Enabled.
+     * |[17]    |PRNGEIEN  |PRNG Error Flag Enable Bit
+     * |        |          |0 = PRNG error interrupt flag Disabled.
+     * |        |          |1 = PRNG error interrupt flag Enabled.
+     * |[22]    |ECCIEN    |ECC Interrupt Enable Bit
+     * |        |          |0 = ECC interrupt Disabled.
+     * |        |          |1 = ECC interrupt Enabled.
+     * |        |          |Note: In DMA mode, an interrupt will be triggered when amount of data set in ECC_DMA_CNT is fed into the ECC engine
+     * |        |          |In Non-DMA mode, an interrupt will be triggered when the ECC engine finishes the operation.
+     * |[23]    |ECCEIEN   |ECC Error Interrupt Enable Bit
+     * |        |          |0 = ECC error interrupt flag Disabled.
+     * |        |          |1 = ECC error interrupt flag Enabled.
+     * |[24]    |HMACIEN   |SHA/HMAC Interrupt Enable Bit
+     * |        |          |0 = SHA/HMAC interrupt Disabled.
+     * |        |          |1 = SHA/HMAC interrupt Enabled.
+     * |        |          |Note: In DMA mode, an interrupt will be triggered when amount of data set in HMAC_DMA_CNT is fed into the SHA/HMAC engine
+     * |        |          |In Non-DMA mode, an interrupt will be triggered when the SHA/HMAC engine finishes the operation.
+     * |[25]    |HMACEIEN  |SHA/HMAC Error Interrupt Enable Bit
+     * |        |          |0 = SHA/HMAC error interrupt flag Disabled.
+     * |        |          |1 = HMAC error interrupt flag Enabled.
+     * |[30]    |RSAIEN    |RSA Interrupt Enable Bit
+     * |        |          |0 = RSA interrupt Disabled.
+     * |        |          |1 = RSA interrupt Enabled.
+     * |        |          |Note: In DMA mode, an interrupt will be triggered when amount of data set in RSA_DMA_CNT is fed into the RSA engine.
+     * |[31]    |RSAEIEN   |RSA Error Interrupt Enable Bit
+     * |        |          |0 = RSA error interrupt flag Disabled.
+     * |        |          |1 = RSA error interrupt flag Enabled.
+     * @var CRPT_T::INTSTS
+     * Offset: 0x04  Crypto Interrupt Flag
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |AESIF     |AES Finish Interrupt Flag
+     * |        |          |0 = No AES interrupt.
+     * |        |          |1 = AES encryption/decryption done interrupt.
+     * |        |          |Note:This bit is cleared by writing 1, and it has no effect by writing 0.
+     * |[1]     |AESEIF    |AES Error Flag
+     * |        |          |0 = No AES error.
+     * |        |          |1 = AES encryption/decryption error interrupt.
+     * |        |          |Note:This bit is cleared by writing 1, and it has no effect by writing 0.
+     * |[16]    |PRNGIF    |PRNG Finish Interrupt Flag
+     * |        |          |0 = No PRNG interrupt.
+     * |        |          |1 = PRNG key generation done interrupt.
+     * |        |          |Note:This bit is cleared by writing 1, and it has no effect by writing 0.
+     * |[17]    |PRNGEIF   |PRNGError Flag
+     * |        |          |0 = No PRNG error.
+     * |        |          |1 = PRNG key generation error interrupt.
+     * |        |          |Note:This bit is cleared by writing 1, and it has no effect by writing 0.
+     * |[22]    |ECCIF     |ECC Finish Interrupt Flag
+     * |        |          |0 = No ECC interrupt.
+     * |        |          |1 = ECC operation done interrupt.
+     * |        |          |Note:This bit is cleared by writing 1, and it has no effect by writing 0.
+     * |[23]    |ECCEIF    |ECC Error Flag
+     * |        |          |This register includes operating and setting error
+     * |        |          |The detail flag is shown in CRPT_ECC_STS register.
+     * |        |          |0 = No ECC error.
+     * |        |          |1 = ECC error interrupt.
+     * |        |          |Note:This bit is cleared by writing 1, and it has no effect by writing 0.
+     * |[24]    |HMACIF    |SHA/HMAC Finish Interrupt Flag
+     * |        |          |0 = No SHA/HMAC interrupt.
+     * |        |          |1 = SHA/HMAC operation done interrupt.
+     * |        |          |Note:This bit is cleared by writing 1, and it has no effect by writing 0.
+     * |[25]    |HMACEIF   |SHA/HMAC Error Flag
+     * |        |          |This register includes operating and setting error
+     * |        |          |The detail flag is shown in CRPT_HMAC_STS register.
+     * |        |          |0 = No SHA/HMAC error.
+     * |        |          |1 = SHA/HMAC error interrupt.
+     * |        |          |Note:This bit is cleared by writing 1, and it has no effect by writing 0.
+     * |[30]    |RSAIF     |RSA Finish Interrupt Flag
+     * |        |          |This bit is cleared by writing 1, and it has no effect by writing 0.
+     * |        |          |0 = No RSA interrupt.
+     * |        |          |1 = RSA operation done interrupt.
+     * |[31]    |RSAEIF    |RSA Error Interrupt Flag
+     * |        |          |This register includes operating and setting error
+     * |        |          |The detail flag is shown in CRPT_RSA_STS register.
+     * |        |          |This bit is cleared by writing 1, and it has no effect by writing 0.
+     * |        |          |0 = No RSA error.
+     * |        |          |1 = RSA error interrupt.
+     * @var CRPT_T::PRNG_CTL
+     * Offset: 0x08  PRNG Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |START     |Start PRNG Engine
+     * |        |          |0 = Stop PRNG engine.
+     * |        |          |1 = Generate new key and store the new key to register CRPT_PRNG_KEYx, which will be cleared when the new key is generated.
+     * |[1]     |SEEDRLD   |Reload New Seed for PRNG Engine
+     * |        |          |0 = Generating key based on the current seed.
+     * |        |          |1 = Reload new seed.
+     * |[5:2]   |KEYSZ     |PRNG Generate Key Size
+     * |        |          |0000 = 128 bits.
+     * |        |          |0001 = 163 bits.
+     * |        |          |0010 = 192 bits.
+     * |        |          |0011 = 224 bits.
+     * |        |          |0100 = 233 bits.
+     * |        |          |0101 = 255 bits.
+     * |        |          |0110 = 256 bits.
+     * |        |          |0111 = 283 bits (only for KS).
+     * |        |          |1000 = 384 bits (only for KS).
+     * |        |          |1001 = 409 bits (only for KS).
+     * |        |          |1010 = 512 bits (only for KS).
+     * |        |          |1011 = 521 bits (only for KS).
+     * |        |          |1100 = 571 bits (only for KS).
+     * |        |          |1101 = Reserved.
+     * |        |          |1110 = Reserved.
+     * |        |          |1111 = Reserved.
+     * |        |          |Note: 283~571 bits only generate for Key Store.
+     * |[6]     |SEEDSEL   |Seed Select
+     * |        |          |This bit can be set to 1 only after SEEDRDY (TRNG_CTL[9]) bit become to 1.
+     * |        |          |0 = Select the seed which is from PRNG.
+     * |        |          |1 = Select the seed which is from TRNG. (not from CRPT_PRNG_SEED)
+     * |[7]     |SEEDSRC   |Seed Source (Read Only)
+     * |        |          |0 = Seed is from PRNG.
+     * |        |          |1 = Seed is from TRNG. (not from CRPT_PRNG_SEED)
+     * |        |          |Note: This bit is cleared to u20180u2019 when SEEDSEL is 0.
+     * |[8]     |BUSY      |PRNG Busy (Read Only)
+     * |        |          |0 = PRNG engine is idle.
+     * |        |          |1 = Indicate that the PRNG engine is generating CRPT_PRNG_KEYx.
+     * @var CRPT_T::PRNG_SEED
+     * Offset: 0x0C  Seed for PRNG
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SEED      |Seed for PRNG (Write Only)
+     * |        |          |The bits store the seed for PRNG engine.
+     * |        |          |Note: In TRNG+PRNG mode, the seed is from TRNGengine, and it will not store in this register.
+     * @var CRPT_T::PRNG_KEY
+     * Offset: 0x10-0x2C  PRNG Generated Key
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |Store PRNG Generated Key (Read Only)
+     * |        |          |The bits store the key that is generated by PRNG.
+     * @var CRPT_T::PRNG_STS
+     * Offset: 0x30  PRNG Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BUSY      |PRNG Busy Flag
+     * |        |          |0 = PRNG engine is idle.
+     * |        |          |1 = Indicate that the PRNG engine is generating CRPT_PRNG_KEYx.
+     * |[16]    |KCTLERR   |PRNG Key Control Register Error Flag
+     * |        |          |0 = No error.
+     * |        |          |1 = PRNG key control error
+     * |        |          |When PRNG execute ECDSA or ECDH, but PRNG seed not from TRNG or key is not written to the SRAM of key store (WSDST,CRPT_PRNG_KSCTL[23:22] is not equal to u201900u2019).
+     * |[17]    |KSERR     |PRNG Access Key Store Error Flag
+     * |        |          |0 = No error.
+     * |        |          |1 = Access key store fail.
+     * @var CRPT_T::AES_FDBCK
+     * Offset: 0x50-0x5C  AES Engine Output Feedback Data After Cryptographic Operation
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |FDBCK     |AES Feedback Information
+     * |        |          |The feedback value is 128 bits in size.
+     * |        |          |The AES engine uses the data from CRPT_AES_FDBCKx as the data inputted to CRPT_AES_IVx for the next block in DMA cascade mode.
+     * |        |          |The AES engine outputs feedback information for IV in the next block operation
+     * |        |          |Software can use this feedback information to implement more than four DMA channels
+     * |        |          |Software can store that feedback value temporarily
+     * |        |          |After switching back, fill the stored feedback value to CRPT_AES_IVx in the same channel operation, and then continue the operation with the original setting.
+     * @var CRPT_T::AES_GCM_IVCNT
+     * Offset: 0x80-0x84  AES GCM IV Byte Count Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CNT       |AES GCM IV   Byte Count
+     * |        |          |The bit   length of IV is 64 bits for AES GCM mode
+     * |        |          |The CRPT_AES_GCM_IVCNT keeps the low weightbyte count of initial vector (i.e., len(IV)[34:3])of AES GCM mode and can be read and written.
+     * @var CRPT_T::AES_GCM_ACNT
+     * Offset: 0x88-0x8C  AES GCM A Byte Count Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CNT       |AES GCM aByte   Count
+     * |        |          |The bit   length of A is 64 bits for AES GCM mode
+     * |        |          |The CRPT_AES_GCM_ACNT keeps the low   weightbyte count of theadditional authenticated data (i.e., len(A)[34:3])of AES GCM mode and can be read and written.
+     * @var CRPT_T::AES_GCM_PCNT
+     * Offset: 0x90-0x94  AES GCM P Byte Count Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CNT       |AES GCM PByte   Count
+     * |        |          |The bit   length of Por Cis 39 bits for AES GCM mode
+     * |        |          |The CRPT_AES_GCM_PCNT0 keeps   the low weightbyte count of theplaintextor ciphertext (i.e., len(P)[34:3]   or len(C)[34:3])of AES GCM mode and can be read and written.
+     * |[60:32] |CNT       |AES GCM P Byte   Count
+     * |        |          |The bit   length of Por C is 39 bits for AES GCM mode
+     * |        |          |The CRPT_AES_GCM_PCNT1 keeps   the high weightbyte count of theplaintext or ciphertext (i.e., len(P)[38:35]   or len(C)[38:35])of AES GCM mode and can be read and written.
+     * |        |          |The bit   length of Por C is 64 bits for AES CCM mode
+     * |        |          |The CRPT_AES_GCM_PCNT1 keeps   the high weightbyte count of theplaintext or ciphertext (i.e., len(P)[63:35]   or len(C)[63:35])of AES CCM mode and can be read and written.
+     * @var CRPT_T::AES_FBADDR
+     * Offset: 0xA0  AES DMA Feedback Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |FBADDR    |AES DMA Feedback Address
+     * |        |          |In DMA cascade mode, software can update DMA feedbackaddress register for automatically reading and writing feedback vaules via DMA.The FBADDR keeps the feedback address of the feedback data for the next cascade operation
+     * |        |          |Based on the feedback address, the AES accelerator can read thefeedback dataof the last cascade opeation from SRAM memory space and write thefeedback dataof the current cascade opeation to SRAM memory space
+     * |        |          |The start of feedback address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of FBADDR are ignored.
+     * |        |          |FBADDR can be read and written.
+     * |        |          |In DMA mode, software can update the next CRPT_AES_FBADDR before triggering START.
+     * @var CRPT_T::AES_CTL
+     * Offset: 0x100  AES Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |START     |AES Engine Start
+     * |        |          |0 = No effect.
+     * |        |          |1 = Start AES engine. BUSY flag will be set.
+     * |        |          |Note: This bit is always 0 when it read back.
+     * |[1]     |STOP      |AES Engine Stop
+     * |        |          |0 = No effect.
+     * |        |          |1 = Stop AES engine.
+     * |        |          |Note: This bit is always 0 when it read back.
+     * |[3:2]   |KEYSZ     |AES Key Size
+     * |        |          |This bit defines three different key size for AES operation.
+     * |        |          |2u2019b00 = 128 bits key.
+     * |        |          |2u2019b01 = 192 bits key.
+     * |        |          |2u2019b10 = 256 bits key.
+     * |        |          |2u2019b11 = Reserved.
+     * |        |          |If the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect.
+     * |        |          |Note:When SM4EN=1, the key size of AESmust be 128.
+     * |[5]     |DMALAST   |AES Last Block
+     * |        |          |In DMA mode, this bit must be set as beginning the last DMA cascade round.
+     * |        |          |In Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode.
+     * |        |          |This bit is always 0 when it read back. Must be written again once START is triggered.
+     * |[6]     |DMACSCAD  |AES Engine DMA with Cascade Mode
+     * |        |          |0 = DMA cascade function Disabled.
+     * |        |          |1 = In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation.
+     * |[7]     |DMAEN     |AES Engine DMA Enable Bit
+     * |        |          |0 = AES DMA engine Disabled.
+     * |        |          |The AES engine operates in Non-DMA mode. The data need to be written in CRPT_AES_DATIN.
+     * |        |          |1 = AES_DMA engine Enabled.
+     * |        |          |The AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
+     * |[15:8]  |OPMODE    |AES Engine Operation Modes
+     * |        |          |0x00 = ECB (Electronic Codebook Mode)  0x01 = CBC (Cipher Block Chaining Mode).
+     * |        |          |0x02 = CFB (Cipher Feedback Mode).
+     * |        |          |0x03 = OFB (Output Feedback Mode).
+     * |        |          |0x04 = CTR (Counter Mode).
+     * |        |          |0x10 = CBC-CS1 (CBC Ciphertext-Stealing 1 Mode).
+     * |        |          |0x11 = CBC-CS2 (CBC Ciphertext-Stealing 2 Mode).
+     * |        |          |0x12 = CBC-CS3 (CBC Ciphertext-Stealing 3 Mode).
+     * |        |          |0x20 = GCM (Galois/Counter Mode).
+     * |        |          |0x21 = GHASH (Galois Hash Function).
+     * |        |          |0x22 = CCM (Counter with CBC-MAC Mode).
+     * |[16]    |ENCRYPTO  |AES Encryption/Decryption
+     * |        |          |0 = AES engine executes decryption operation.
+     * |        |          |1 = AES engine executes encryption operation.
+     * |[17]    |SM4EN     |SM4 Engine Enable
+     * |        |          |0 = Enable AES engine.
+     * |        |          |1 =Enable SM4 engine.
+     * |[20]    |FBIN      |Feedback Input to AES Via DMA Automatically
+     * |        |          |0 = Disable DMA automatical feedback input fucntion.
+     * |        |          |1 =Enable DMA automatical feedback input fucntion.when DMAEN = 1.
+     * |[21]    |FBOUT     |Feedback Output From AES Via DMA Automatically
+     * |        |          |0 = Disable DMA automatical feedback output fucntion.
+     * |        |          |1 =Enable DMA automatical feedback output fucntion when DMAEN = 1.
+     * |[22]    |OUTSWAP   |AES Engine Output Data Swap
+     * |        |          |0 = Keep the original order.
+     * |        |          |1 =The order that CPU reads data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
+     * |[23]    |INSWAP    |AES Engine Input Data Swap
+     * |        |          |0 = Keep the original order.
+     * |        |          |1 =The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
+     * |[24]    |KOUTSWAP  |AES Engine Output Key, Initial Vector and Feedback Swap
+     * |        |          |0 = Keep the original order.
+     * |        |          |1 =The order that CPU readskey, initial vector and feeback from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
+     * |[25]    |KINSWAP   |AES Engine Input Key and Initial Vector Swap
+     * |        |          |0 = Keep the original order.
+     * |        |          |1 =The order that CPU feeds key and initial vector to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
+     * |[30:26] |KEYUNPRT  |Unprotect Key
+     * |        |          |Writing 0 to CRPT_AES_CTL[31] and u201C10110u201D to CRPT_AES_CTL[30:26] is to unprotect theAES key.
+     * |        |          |The KEYUNPRT can be read and written
+     * |        |          |When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.
+     * |[31]    |KEYPRT    |Protect Key
+     * |        |          |Read as a flag to reflect KEYPRT.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Protect the content of the AES key from reading
+     * |        |          |The return value for reading CRPT_AES_KEYx is not the content of the registers CRPT_AES_KEYx
+     * |        |          |Once it is set, it can be cleared by asserting KEYUNPRT
+     * |        |          |And the key content would be cleared as well.
+     * @var CRPT_T::AES_STS
+     * Offset: 0x104  AES Engine Flag
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BUSY      |AES Engine Busy
+     * |        |          |0 = The AES engine is idle or finished.
+     * |        |          |1 = The AES engine is under processing.
+     * |[8]     |INBUFEMPTY|AES Input Buffer Empty
+     * |        |          |0 = There are some data in input buffer waiting for the AES engine to process.
+     * |        |          |1 = AES input buffer is empty
+     * |        |          |Software needs to feed data to the AES engine
+     * |        |          |Otherwise, the AES engine will be pending to wait for input data.
+     * |[9]     |INBUFFULL |AES Input Buffer Full Flag
+     * |        |          |0 = AES input buffer is not full. Software can feed the data into the AES engine.
+     * |        |          |1 = AES input buffer is full
+     * |        |          |Software cannot feed data to the AES engine
+     * |        |          |Otherwise, the flag INBUFERR will be set to 1.
+     * |[10]    |INBUFERR  |AES Input Buffer Error Flag
+     * |        |          |0 = No error.
+     * |        |          |1 = Error happens during feeding data to the AES engine.
+     * |[12]    |CNTERR    |CRPT_AES_CNT Setting Error
+     * |        |          |0 = No error in CRPT_AES_CNT setting.
+     * |        |          |1 = CRPT_AES_CNT is 0 or not a multiply of 16 in ECB, CBC, CFB, OFB, and CTR mode if DMAEN (CRPT_AES_CTL[7]) is enabled.
+     * |[16]    |OUTBUFEMPTY|AES Out Buffer Empty
+     * |        |          |0 = AES output buffer is not empty. There are some valid data kept in output buffer.
+     * |        |          |1 = AES output buffer is empty
+     * |        |          |Software cannot get data from CRPT_AES_DATOUT
+     * |        |          |Otherwise, the flag OUTBUFERR will be set to 1 since the output buffer is empty.
+     * |[17]    |OUTBUFFULL|AES Out Buffer Full Flag
+     * |        |          |0 = AES output buffer is not full.
+     * |        |          |1 = AES output buffer is full, and software needs to get data from CRPT_AES_DATOUT
+     * |        |          |Otherwise, the AES engine will be pending since the output buffer is full.
+     * |[18]    |OUTBUFERR |AES Out Buffer Error Flag
+     * |        |          |0 = No error.
+     * |        |          |1 = Error happens during getting the result from AES engine.
+     * |[20]    |BUSERR    |AES DMA Access Bus Error Flag
+     * |        |          |0 = No error.
+     * |        |          |1 = Bus error will stop DMA operation and AES engine.
+     * |[21]    |KSERR     |AES Engine Access Key Store Error Flag
+     * |        |          |0 = No error.
+     * |        |          |1 = Access error will stop AES engine.
+     * @var CRPT_T::AES_DATIN
+     * Offset: 0x108  AES Engine Data Input Port Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DATIN     |AES Engine Input Port
+     * |        |          |CPU feeds data to AES engine through this port by checking CRPT_AES_STS. Feed data as INBUFFULL is 0.
+     * @var CRPT_T::AES_DATOUT
+     * Offset: 0x10C  AES Engine Data Output Port Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DATOUT    |AES Engine Output Port
+     * |        |          |CPU gets results from the AES engine through this port by checking CRPT_AES_STS
+     * |        |          |Get data as OUTBUFEMPTY is 0.
+     * @var CRPT_T::AES_KEY
+     * Offset: 0x110-0x12C  AES Key Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |CRPT_AES_KEYx
+     * |        |          |The KEY keeps the security key for AES operation.
+     * |        |          |x = 0, 1..7.
+     * |        |          |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
+     * |        |          |{CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 128-bit security key for AES operation.
+     * |        |          |{CRPT_AES_KEY5, CRPT_AES_KEY4, CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 192-bit security key for AES operation.
+     * |        |          |{CRPT_AES_KEY7, CRPT_AES_KEY6, CRPT_AES_KEY5, CRPT_AES_KEY4, CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 256-bit security key for AES operation.
+     * @var CRPT_T::AES_IV
+     * Offset: 0x130-0x13C  AES Initial Vector Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |IV        |AES Initial Vectors
+     * |        |          |x = 0, 1..3.
+     * |        |          |Four initial vectors (CRPT_AES_IV0, CRPT_AES_IV1, CRPT_AES_IV2, and CRPT_AES_IV3) are for AES operating in CBC, CFB, and OFB mode
+     * |        |          |Four registers (CRPT_AES_IV0, CRPT_AES_IV1, CRPT_AES_IV2, and CRPT_AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
+     * @var CRPT_T::AES_SADDR
+     * Offset: 0x140  AES DMA Source Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SADDR     |AES DMA Source Address
+     * |        |          |The AES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO
+     * |        |          |The SADDR keeps the source address of the data buffer where the source text is stored
+     * |        |          |Based on the source address, the AES accelerator can read the plain text (encryption) / cipher text (descryption) from SRAM memory space and do AES operation
+     * |        |          |The start of source address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of SADDR are ignored.
+     * |        |          |SADDR can be read and written
+     * |        |          |Writing to SADDR while the AES accelerator is operating doesnu2019t affect the current AES operation
+     * |        |          |But the value of SADDR will be updated later on
+     * |        |          |Consequently, software can prepare the DMA source address for the next AES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_AES_SADDR before triggering START.
+     * |        |          |The value of CRPT_AES_SADDR and CRPT_AES_DADDR can be the same.
+     * @var CRPT_T::AES_DADDR
+     * Offset: 0x144  AES DMA Destination Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DADDR     |AES DMA Destination Address
+     * |        |          |The AES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO
+     * |        |          |The DADDR keeps the destination address of the data buffer where the engine output text will be stored
+     * |        |          |Based on the destination address, the AES accelerator can write the cipher text (encryption) / plain text (decryption) back to SRAM memory space after the AES operation is finished
+     * |        |          |The start of destination address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of DADDR are ignored.
+     * |        |          |DADDR can be read and written
+     * |        |          |Writing to DADDR while the AES accelerator is operating doesnu2019t affect the current AES operation
+     * |        |          |But the value of DADDR will be updated later on
+     * |        |          |Consequently, software can prepare the destination address for the next AES operation.
+     * |        |          |In DMA mode, software can update the next CRPT_AES_DADDR before triggering START.
+     * |        |          |The value of CRPT_AES_SADDR and CRPT_AES_DADDR can be the same.
+     * @var CRPT_T::AES_CNT
+     * Offset: 0x148  AES Byte Count Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CNT       |AES Byte   Count
+     * |        |          |The CRPT_AES_CNT   keeps the byte count of source text that is for the AES engine operating in   DMA mode
+     * |        |          |The CRPT_AES_CNT is 32-bit and the maximum of byte count is 4G   bytes.
+     * |        |          |CRPT_AES_CNT   can be read and written
+     * |        |          |Writing to CRPT_AES_CNT while the AES accelerator   is operating doesnu2019t affect the current AES operation
+     * |        |          |But the value of CRPT_AES_CNT   will be updated later on
+     * |        |          |Consequently, software can prepare the byte count   of data for the next AES operation.
+     * |        |          |According to   CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be more   than 16 bytes
+     * |        |          |Operations that are qual or less than one block will output   unexpected result.
+     * |        |          |In Non-DMA   ECB, CBC, CFB, OFB, CTR, CCM and GCM mode, CRPT_AES_CNT must be set as byte   count for the last block of data before feeding in the last block of data
+     * |        |          |In   Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AES_CNT must be set as   byte count for the last two blocks of data before feeding in the last two   blocks of data.
+     * |        |          |In AES GCM   mode without DMA cascade fucntion, the value of CRPT_AES_CNT is equal to   the total value of{CRPT_AES_GCM_IVCNT1, CRPT_AES_GCM_IVCNT0}, {CRPT_AES_GCM_ACNT1,   CRPT_AES_GCM_ACNT0} and {CRPT_AES_GCM_PCNT1, CRPT_AES_GCM_PCNT0}.
+     * |        |          |In AES GCM   mode with DMA cascade fucntion,the value of CRPT_AES_CNT represents the byte   count of source text in this cascade function
+     * |        |          |Thus, the value of   CRPT_AES_CNT is less than or equal to the total value of {CRPT_AES_GCM_IVCNT1,   CRPT_AES_GCM_IVCNT0}, {CRPT_AES_GCM_ACNT1, CRPT_AES_GCM_ACNT0} and {CRPT_AES_GCM_PCNT1,   CRPT_AES_GCM_PCNT0} and must be block alignment.
+     * |        |          |In AES CCM   mode without DMA cascade fucntion, the value of CRPT_AES_CNT is equal to   the total value of {CRPT_AES_GCM_ACNT1, CRPT_AES_GCM_ACNT0} and {CRPT_AES_GCM_PCNT1,   CRPT_AES_GCM_PCNT0}.
+     * |        |          |In AES CCM   mode with DMA cascade fucntion,the value of CRPT_AES_CNT represents the byte   count of source text in this cascade function
+     * |        |          |Thus, the value of   CRPT_AES_CNT is less than or equal to the total value of {CRPT_AES_GCM_ACNT1,   CRPT_AES_GCM_ACNT0} and {CRPT_AES_GCM_PCNT1, CRPT_AES_GCM_PCNT0} and   must be block alignment, except for the last block of plaintext or ciphertext.
+     * @var CRPT_T::HMAC_CTL
+     * Offset: 0x300  SHA/HMAC Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |START     |SHA/HMAC Engine Start
+     * |        |          |0 = No effect.
+     * |        |          |1 = Start SHA/HMAC engine. BUSY flag will be set.
+     * |        |          |Note: This bit is always 0 when it read back.
+     * |[1]     |STOP      |SHA/HMAC Engine Stop
+     * |        |          |0 = No effect.
+     * |        |          |1 = Stop SHA/HMAC engine.
+     * |        |          |Note: This bit is always 0 when it read back.
+     * |[4]     |DMAFIRST  |SHA/HMAC First Blockin Cascadefunction
+     * |        |          |This bit must be set as feeding in first byte of data.
+     * |[5]     |DMALAST   |SHA/HMAC Last Block
+     * |        |          |This bit must be set as feeding in last byte of data.
+     * |[6]     |DMACSCAD  |SHA/HMAC Engine DMA with Cascade Mode
+     * |        |          |0 = DMA cascade function Disabled.
+     * |        |          |1 = In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation.
+     * |[7]     |DMAEN     |SHA/HMAC Engine DMA Enable Bit
+     * |        |          |0 = SHA/HMAC DMA engine Disabled.
+     * |        |          |SHA/HMAC engine operates in Non-DMA mode. The data need to be written in CRPT_HMAC_DATIN.
+     * |        |          |1 = SHA/HMAC DMA engine Enabled.
+     * |        |          |SHA/HMAC engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
+     * |[10:8]  |OPMODE    |SHA/HMAC Engine Operation Modes
+     * |        |          |0x0xx: SHA1-160
+     * |        |          |0x100: SHA2-256
+     * |        |          |0x101: SHA2-224
+     * |        |          |0x110: SHA2-512
+     * |        |          |0x111: SHA2-384
+     * |        |          |Note: These bits can be read and written. But writing tothem wouldnu2019t take effect as BUSY is 1..
+     * |        |          |Note:When SM3EN=1, SHA/HMAC only execute SM3-256.
+     * |[11]    |HMACEN    |HMAC_SHA Engine Operating Mode
+     * |        |          |0 = Execute SHA function.
+     * |        |          |1 = Execute HMAC function.
+     * |[13]    |SM3EN     |SM3 Engine Enable Bit
+     * |        |          |0 = Execute other function.
+     * |        |          |1 = Execute SM3 function.
+     * |[20]    |FBIN      |Feedback Input to SHA/HMAC Via DMA Automatically
+     * |        |          |0 = Disable DMA automatical feedback input fucntion..
+     * |        |          |1 = Enable DMA automatical feedback input fucntion when DMAEN = 1.
+     * |[21]    |FBOUT     |Feedback Output From SHA/HMAC Via DMA Automatically
+     * |        |          |0 = Disable DMA automatical feedback output fucntion..
+     * |        |          |1 = Enable DMA automatical feedback output fucntion when DMAEN = 1.
+     * |[22]    |OUTSWAP   |SHA/HMAC Engine Output Data Swap
+     * |        |          |0 = Keep the original order.
+     * |        |          |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
+     * |[23]    |INSWAP    |SHA/HMAC Engine Input Data Swap
+     * |        |          |0 = Keep the original order.
+     * |        |          |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
+     * @var CRPT_T::HMAC_STS
+     * Offset: 0x304  SHA/HMAC Status Flag
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BUSY      |SHA/HMAC Engine Busy
+     * |        |          |0 = SHA/HMAC engine is idle or finished.
+     * |        |          |1 = SHA/HMAC engine is busy.
+     * |[1]     |DMABUSY   |SHA/HMAC Engine DMA Busy Flag
+     * |        |          |0 = SHA/HMAC DMA engine is idle or finished.
+     * |        |          |1 = SHA/HMAC DMA engine is busy.
+     * |[8]     |DMAERR    |SHA/HMAC Engine DMA Error Flag
+     * |        |          |0 = Show the SHA/HMAC engine access normal.
+     * |        |          |1 = Show the SHA/HMAC engine access error.
+     * |[9]     |KSERR     |HMAC Engine Access Key Store Error Flag
+     * |        |          |0 = No error.
+     * |        |          |1 = Access error will stop HMAC engine.
+     * |[16]    |DATINREQ  |SHA/HMAC Non-dMA Mode Data Input Request
+     * |        |          |0 = No effect.
+     * |        |          |1 = Request SHA/HMAC Non-DMA mode data input.
+     * @var CRPT_T::HMAC_DGST
+     * Offset: 0x308-0x344  SHA/HMAC Output Feedback Data
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DGST      |SHA/HMACOutput Feedback Data Output Register
+     * |        |          |For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4.
+     * |        |          |For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6.
+     * |        |          |For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7.
+     * |        |          |For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11.
+     * |        |          |For SHA-512, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15.
+     * @var CRPT_T::HMAC_KEYCNT
+     * Offset: 0x348  SHA/HMAC Key Byte Count Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEYCNT    |SHA/HMAC Key Byte Count
+     * |        |          |The CRPT_HMAC_KEYCNT keeps the byte count of key that SHA/HMAC engine operates
+     * |        |          |The register is 32-bit and the maximum byte count is 4G bytes
+     * |        |          |It can be read and written.
+     * |        |          |Writing to the register CRPT_HMAC_KEYCNT as the SHA/HMAC accelerator operating doesnu2019t affect the current SHA/HMAC operation
+     * |        |          |But the value of CRPT_HMAC_KEYCNT will be updated later on
+     * |        |          |Consequently, software can prepare the key count for the next SHA/HMAC operation.
+     * @var CRPT_T::HMAC_SADDR
+     * Offset: 0x34C  SHA/HMAC DMA Source Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SADDR     |SHA/HMAC DMA Source Address
+     * |        |          |The SHA/HMAC accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO
+     * |        |          |The CRPT_HMAC_SADDR keeps the source address of the data buffer where the source text is stored
+     * |        |          |Based on the source address, the SHA/HMAC accelerator can read the plain text from SRAM memory space and do SHA/HMAC operation
+     * |        |          |The start of source address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of CRPT_HMAC_SADDR are ignored.
+     * |        |          |CRPT_HMAC_SADDR can be read and written
+     * |        |          |Writing to CRPT_HMAC_SADDR while the SHA/HMAC accelerator is operating doesnu2019t affect the current SHA/HMAC operation
+     * |        |          |But the value of CRPT_HMAC_SADDR will be updated later on
+     * |        |          |Consequently, software can prepare the DMA source address for the next SHA/HMAC operation.
+     * |        |          |In DMA mode, software can update the next CRPT_HMAC_SADDR before triggering START.
+     * |        |          |CRPT_HMAC_SADDR and CRPT_HMAC_DADDR can be the same in the value.
+     * @var CRPT_T::HMAC_DMACNT
+     * Offset: 0x350  SHA/HMAC Byte Count Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DMACNT    |SHA/HMAC Operation Byte Count
+     * |        |          |The CRPT_HMAC_DMACNT keeps the byte count of source text that is for the SHA/HMAC engine operating in DMA mode
+     * |        |          |The CRPT_HMAC_DMACNT is 32-bit and the maximum of byte count is 4G bytes.
+     * |        |          |CRPT_HMAC_DMACNT can be read and written
+     * |        |          |Writing to CRPT_HMAC_DMACNT while the SHA/HMAC accelerator is operating doesnu2019t affect the current SHA/HMAC operation
+     * |        |          |But the value of CRPT_HMAC_DMACNT will be updated later on
+     * |        |          |Consequently, software can prepare the byte count of data for the next SHA/HMAC operation.
+     * |        |          |In Non-DMA mode, CRPT_HMAC_DMACNT must be set as the byte count of the last block before feeding in the last block of data.
+     * @var CRPT_T::HMAC_DATIN
+     * Offset: 0x354  SHA/HMAC Engine Non-dMA Mode Data Input Port Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DATIN     |SHA/HMAC Engine Input Port
+     * |        |          |CPU feeds data to SHA/HMAC engine through this port by checking CRPT_HMAC_STS
+     * |        |          |Feed data as DATINREQ is 1.
+     * @var CRPT_T::HMAC_FDBCK
+     * Offset: 0x358-0x42C  SHA/HMAC Output Feedback Data After SHA/HMAC Operation
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |FDBCK     |SHA/HMAC Feedback Information
+     * |        |          |The feedback value is 1728 bits in size for SHA1/2.
+     * |        |          |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode.
+     * |        |          |The SHA/HMAC engine outputs feedback information for initial setting in the next block operation
+     * |        |          |Software can store that feedback value temporarily
+     * |        |          |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting.
+     * @var CRPT_T::HMAC_FBADDR
+     * Offset: 0x4FC  SHA/HMAC DMA Feedback Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |FBADDR    |SHA/HMAC DMA Feedback Address
+     * |        |          |In DMA cascade mode, software can update DMA feedbackaddress register for automatically reading and writing feedback vaules via DMA.The FBADDR keeps the feedback address of the feedback data for the next cascade operation
+     * |        |          |Based on the feedback address, the SHA/HMAC accelerator can read thefeedback dataof the last cascade opeation from SRAM memory space and write thefeedback dataof the current cascade opeation to SRAM memory space
+     * |        |          |The start of feedback address should be located at word boundary
+     * |        |          |In other words, bit 1 and 0 of FBADDR are ignored.
+     * |        |          |FBADDR can be read and written.
+     * |        |          |In DMA mode, software can update the next CRPT_HMAC_FBADDR before triggering START.
+     * @var CRPT_T::ECC_CTL
+     * Offset: 0x800  ECC Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |START     |ECC Accelerator Start
+     * |        |          |0 = No effect.
+     * |        |          |1 = Start ECC accelerator. BUSY flag will be set.
+     * |        |          |This bit is always 0 when it read back.
+     * |        |          |ECC accelerator will ignore this START signal when BUSY flag is 1.
+     * |[1]     |STOP      |ECC Accelerator Stop
+     * |        |          |0 = No effect.
+     * |        |          |1 = Abort ECC accelerator and make it into idle state.
+     * |        |          |This bit is always 0 when it read back.
+     * |        |          |Remember to clear ECC interrupt flag after stopping ECC accelerator.
+     * |[3]     |PFA2C     |Primg Field Adder with 2Cycles
+     * |        |          |0 = cost1 cycle .
+     * |        |          |1 = cost 2 cycles.
+     * |[4]     |ECDSAS    |Generate S in ECDSA Signature Generation
+     * |        |          |0 = No effect.
+     * |        |          |1 = Formula for generating S.
+     * |        |          |POINTX1 = ((POINTX2 * POINTY1 + POINTY2 ) / POINTX1) % CURVEN.
+     * |[5]     |ECDSAR    |Generate R in ECDSA Signature Generation
+     * |        |          |0 = No effect.
+     * |        |          |1 = Formula for generating R.
+     * |        |          |(POINTX1, POINTY1) = SCALARK * (POINTX1, POINTY1).
+     * |[7]     |DMAEN     |ECC Accelerator DMA Enable Bit
+     * |        |          |0 = ECC DMA engine Disabled.
+     * |        |          |1 = ECC DMA engine Enabled.
+     * |        |          |Only when START and DMAEN are 1, ECC DMA engine will be active
+     * |[8]     |FSEL      |Field Selection
+     * |        |          |0 = Binary Field (GF(2m )).
+     * |        |          |1 = Prime Field (GF(p)).
+     * |[10:9]  |ECCOP     |Point Operation for BF and PF
+     * |        |          |00 = Point multiplication :.
+     * |        |          |(POINTX1, POINTY1) = SCALARK * (POINTX1, POINTY1).
+     * |        |          |01 = Modulus operation : choose by MODOP (CRPT_ECC_CTL[12:11]).
+     * |        |          |10 = Point addition :.
+     * |        |          |(POINTX1, POINTY1) = (POINTX1, POINTY1) +.
+     * |        |          |(POINTX2, POINTY2)
+     * |        |          |11 = Point doubling :.
+     * |        |          |(POINTX1, POINTY1) = 2 * (POINTX1, POINTY1).
+     * |        |          |Besides above three input data, point operations still need the parameters of elliptic curve (CURVEA, CURVEB, CURVEN and CURVEM) as shown in Figure 6.27-11
+     * |[12:11] |MODOP     |Modulus Operation for PF
+     * |        |          |00 = Division :.
+     * |        |          |POINTX1 = (POINTY1 / POINTX1) % CURVEN.
+     * |        |          |01 = Multiplication :.
+     * |        |          |POINTX1 = (POINTX1 * POINTY1) % CURVEN.
+     * |        |          |10 = Addition :.
+     * |        |          |POINTX1 = (POINTX1 + POINTY1) % CURVEN.
+     * |        |          |11 = Subtraction :.
+     * |        |          |POINTX1 = (POINTX1 - POINTY1) % CURVEN.
+     * |        |          |MODOP is active only when ECCOP = 01.
+     * |[13]    |CSEL      |Curve Selection
+     * |        |          |0 = NISTsuggested curve.
+     * |        |          |1 = Montgomery curve.
+     * |[14]    |SCAP      |Side-channel Attack Protection
+     * |        |          |0 = Full speed without side-channel protection.
+     * |        |          |1 = Less speed with side-channel protection.
+     * |[15]    |SBM       |Secure-boot Mode
+     * |        |          |0 = (POINTX1,POINTY1)from user data.
+     * |        |          |1 = (POINTX1,POINTY1)from secure boot key.
+     * |[16]    |LDP1      |The Control Signal of RegisterPOINTX1and POINTY1for the xand Y Coordinate of the First Point
+     * |        |          |0 = The register for POINTX1 and POINTY1 is not modified by DMA or user.
+     * |        |          |1 = The register for POINTX1 and POINTY1 is modified by DMA or user.
+     * |[17]    |LDP2      |The Control Signal of Register POINTX2and POINTY2for the xand Y Coordinate of the Second Point
+     * |        |          |0 = The register for POINTX2 and POINTY2 is not modified by DMA or user.
+     * |        |          |1 = The register for POINTX2 and POINTY2 is modified by DMA or user.
+     * |[18]    |LDA       |The Control Signal of Register for the Parameter CURVEA of Elliptic Curve
+     * |        |          |0 = The register for CURVEA is not modified by DMA or user.
+     * |        |          |1 = The register for CURVEA is modified by DMA or user.
+     * |[19]    |LDB       |The Control Signal of Register for the Parameter CURVEB of Elliptic Curve
+     * |        |          |0 = The register for CURVEB is not modified by DMA or user.
+     * |        |          |1 = The register for CURVEB is modified by DMA or user.
+     * |[20]    |LDN       |The Control Signal of Register for the Parameter CURVEN of Elliptic Curve
+     * |        |          |0 = The register for CURVEN is not modified by DMA or user.
+     * |        |          |1 = The register for CURVEN is modified by DMA or user.
+     * |[21]    |LDK       |The Control Signal of Register for SCALARK
+     * |        |          |0 = The register for SCALARK is not modified by DMA or user.
+     * |        |          |1 = The register for SCALARK is modified by DMA or user.
+     * |[31:22] |CURVEM    |The key length of elliptic curve.
+     * @var CRPT_T::ECC_STS
+     * Offset: 0x804  ECC Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BUSY      |ECC Accelerator Busy Flag
+     * |        |          |0 = The ECC accelerator is idle or finished.
+     * |        |          |1 = The ECC accelerator is under processing and protects all registers.
+     * |        |          |Remember to clear ECC interrupt flag after ECC accelerator finished
+     * |[1]     |DMABUSY   |ECC DMA Busy Flag
+     * |        |          |0 = ECC DMA is idle or finished.
+     * |        |          |1 = ECC DMA is busy.
+     * |[16]    |BUSERR    |ECC DMA Access Bus Error Flag
+     * |        |          |0 = No error.
+     * |        |          |1 = Bus error will stop DMA operation and ECC accelerator..
+     * |[17]    |KSERR     |ECC Engine Access Key Store Error Flag
+     * |        |          |0 = No error.
+     * |        |          |1 = Access error will stop ECC engine.
+     * @var CRPT_T::ECC_X1
+     * Offset: 0x808-0x84C  ECC the X-coordinate Word of the First Point
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |POINTX1   |ECC the X-coordinate Value of the First Point
+     * |        |          |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05
+     * |        |          |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07
+     * |        |          |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08
+     * |        |          |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12
+     * |        |          |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17
+     * |        |          |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05
+     * |        |          |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06
+     * |        |          |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07
+     * |        |          |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11
+     * |        |          |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16
+     * @var CRPT_T::ECC_Y1
+     * Offset: 0x850-0x894  ECC the Y-coordinate Word of the First Point
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |POINTY1   |ECC the Y-coordinate Value of the First Point
+     * |        |          |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05
+     * |        |          |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07
+     * |        |          |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08
+     * |        |          |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12
+     * |        |          |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17
+     * |        |          |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05
+     * |        |          |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06
+     * |        |          |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07
+     * |        |          |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11
+     * |        |          |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16
+     * @var CRPT_T::ECC_X2
+     * Offset: 0x898-0x8DC  ECC the X-coordinate Word of the Second Point
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |POINTX2   |ECC the X-coordinate Value of the Second Point
+     * |        |          |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05
+     * |        |          |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07
+     * |        |          |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08
+     * |        |          |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12
+     * |        |          |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17
+     * |        |          |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05
+     * |        |          |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06
+     * |        |          |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07
+     * |        |          |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11
+     * |        |          |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16
+     * @var CRPT_T::ECC_Y2
+     * Offset: 0x8E0-0x924  ECC the Y-coordinate Word of the Second Point
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |POINTY2   |ECC the Y-coordinate Value of the Second Point
+     * |        |          |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05
+     * |        |          |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07
+     * |        |          |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08
+     * |        |          |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12
+     * |        |          |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17
+     * |        |          |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05
+     * |        |          |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06
+     * |        |          |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07
+     * |        |          |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11
+     * |        |          |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16
+     * @var CRPT_T::ECC_A
+     * Offset: 0x928-0x96C  ECC the Parameter CURVEA Word of Elliptic Curve
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CURVEA    |ECC the Parameter CURVEA Value of Elliptic Curve
+     * |        |          |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m).
+     * |        |          |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05
+     * |        |          |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07
+     * |        |          |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08
+     * |        |          |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12
+     * |        |          |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17
+     * |        |          |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05
+     * |        |          |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06
+     * |        |          |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07
+     * |        |          |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11
+     * |        |          |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16
+     * @var CRPT_T::ECC_B
+     * Offset: 0x970-0x9B4  ECC the Parameter CURVEB Word of Elliptic Curve
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CURVEB    |ECC the Parameter CURVEB Value of Elliptic Curve
+     * |        |          |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m).
+     * |        |          |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05
+     * |        |          |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07
+     * |        |          |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08
+     * |        |          |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12
+     * |        |          |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17
+     * |        |          |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05
+     * |        |          |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06
+     * |        |          |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07
+     * |        |          |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11
+     * |        |          |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16
+     * @var CRPT_T::ECC_N
+     * Offset: 0x9B8-0x9FC  ECC the Parameter CURVEN Word of Elliptic Curve
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CURVEN    |ECC the Parameter CURVEN Value of Elliptic Curve
+     * |        |          |In GF(p), CURVEN is the prime p.
+     * |        |          |In GF(2m), CURVEN is  the irreducible polynomial.
+     * |        |          |For B-163 or K-163, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05
+     * |        |          |For B-233 or K-233, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07
+     * |        |          |For B-283 or K-283, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_08
+     * |        |          |For B-409 or K-409, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_12
+     * |        |          |For B-571 or K-571, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_17
+     * |        |          |For P-192, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05
+     * |        |          |For P-224, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_06
+     * |        |          |For P-256, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07
+     * |        |          |For P-384, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_11
+     * |        |          |For P-521, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_16
+     * @var CRPT_T::ECC_K
+     * Offset: 0xA00-0xA44  ECC the Scalar SCALARK Word of Point Multiplication
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SCALARK   |ECC the Scalar SCALARK Value of Point Multiplication
+     * |        |          |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK.
+     * |        |          |For B-163 or K-163, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05
+     * |        |          |For B-233 or K-233, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07
+     * |        |          |For B-283 or K-283, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_08
+     * |        |          |For B-409 or K-409, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_12
+     * |        |          |For B-571 or K-571, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_17
+     * |        |          |For P-192, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05
+     * |        |          |For P-224, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_06
+     * |        |          |For P-256, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07
+     * |        |          |For P-384, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_11
+     * |        |          |For P-521, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_16
+     * @var CRPT_T::ECC_SADDR
+     * Offset: 0xA48  ECC DMA Source Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SADDR     |ECC DMA Source Address
+     * |        |          |The ECC accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and ECC accelerator.
+     * |        |          |The SADDR keeps the source address of the data buffer where the source text is stored. Based on the source address,
+     * |        |          |the ECC accelerator can read the DATA and PARAMETER from SRAM memory space and do ECC operation.
+     * |        |          |The start of source address should be located at word boundary. That is, bit 1 and 0 of SADDR are ignored.
+     * |        |          |SADDR can be read and written. In DMA mode, software must update the CRYPTO_ECC_SADDR before triggering START.
+     * @var CRPT_T::ECC_DADDR
+     * Offset: 0xA4C  ECC DMA Destination Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DADDR     |ECC DMA Destination Address
+     * |        |          |The ECC accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory and ECC accelerator
+     * |        |          |The DADDR keeps the destination address of the data buffer where output data of ECC engine will be stored
+     * |        |          |Based on the destination address, the ECC accelerator can write the result data back to SRAM memory space after the ECC operation is finished
+     * |        |          |The start of destination address should be located at word boundary
+     * |        |          |That is, bit 1 and 0 of DADDR are ignored
+     * |        |          |DADDR can be read and written
+     * |        |          |In DMA mode, software must update the CRPT_ECC_DADDR before triggering START
+     * @var CRPT_T::ECC_STARTREG
+     * Offset: 0xA50  ECC Starting Address of Updated Registers
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |STARTREG  |ECC Starting Address of Updated Registers
+     * |        |          |The address of the updated registers that DMA feeds the first data or parameter to ECC engine
+     * |        |          |When ECC engine is active, ECC accelerator does not allow users to modify STARTREG, for example, to update input data from register CRPT_ECC POINTX1
+     * |        |          |Thus, the value of STARTREG is 0x808.
+     * @var CRPT_T::ECC_WORDCNT
+     * Offset: 0xA54  ECC DMA Word Count
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |WORDCNT   |ECC DMA Word Count
+     * |        |          |The CRPT_ECC_WORDCNT keeps the word count of source data that is for the required input data of ECC accelerator with various operations in DMA mode
+     * |        |          |Although CRPT_ECC_WORDCNT is 32-bit, the maximum of word count in ECC accelerator is 144words
+     * |        |          |CRPT_ECC_WORDCNT can be read and written
+     * @var CRPT_T::RSA_CTL
+     * Offset: 0xB00  RSA Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |START     |RSA Accelerator Start
+     * |        |          |0 = No effect.
+     * |        |          |1 = Start RSAaccelerator. BUSY flag will be set.
+     * |        |          |This bit is always 0 when it read back.
+     * |        |          |RSAaccelerator will ignore this START signal when BUSY flag is 1.
+     * |[1]     |STOP      |RSA Accelerator Stop
+     * |        |          |0 = No effect.
+     * |        |          |1 = Abort RSA accelerator and make it into initialstate.
+     * |        |          |This bit is always 0 when it read back.
+     * |        |          |Remember to clear RSA interrupt flag after stopping RSA accelerator.
+     * |[2]     |CRT       |CRT Enable Control
+     * |        |          |0 = CRT Disabled.
+     * |        |          |1 = CRT Enabled.
+     * |        |          |CRT is only used in decryption with key length 2048, 3072,4096 bits.
+     * |[3]     |CRTBYP    |CRT BypassEnable Control
+     * |        |          |0 = CRT Bypass Disabled.
+     * |        |          |1 = CRT Bypass Enabled.
+     * |        |          |CRT bypass is only used in CRT decryption with the same key.
+     * |        |          |Note: If users want to decrypt repeatedly with the same key, they can execute CRT bypass mode after the first time CRT decryption(means the second time to the latest time), but they canu2019t set CRTBYP to 1 in non-CRT mode.
+     * |[5:4]   |KEYLENG   |The Key Length of RSA Operation
+     * |        |          |00 = 1024bits.
+     * |        |          |01 = 2048bits.
+     * |        |          |10 = 3072bits.
+     * |        |          |11 = 4096bits.
+     * |[8]     |SCAP      |Side Channel Attack Protection Enable Control
+     * |        |          |0 = Side Channel Attack Protection Disabled.
+     * |        |          |1 = Side Channel Attack Protection Enabled.
+     * @var CRPT_T::RSA_STS
+     * Offset: 0xB04  RSA Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BUSY      |RSA Accelerator Busy Flag
+     * |        |          |0 = The RSA accelerator is idle or finished.
+     * |        |          |1 = The RSA accelerator is under processing and protects all registers.
+     * |        |          |Remember to clear RSA interrupt flag after RSA accelerator finished
+     * |[1]     |DMABUSY   |RSA DMA Busy Flag
+     * |        |          |0 = RSA DMA is idle or finished.
+     * |        |          |1 = RSA DMA is busy.
+     * |[16]    |BUSERR    |RSA DMA Access Bus Error Flag
+     * |        |          |0 = No error.
+     * |        |          |1 = Bus error will stop DMA operation and RSA accelerator.
+     * |[17]    |CTLERR    |RSA Control Register Error Flag
+     * |        |          |0 = No error.
+     * |        |          |1 = RSA control error. RSA will not start in the unsupported situation.
+     * |        |          |Note: If user use the control error condition, but donu2019t set START(CRPT_RSA_CTL[0]) to 1, CTLERR still be set to 1.
+     * |[18]    |KSERR     |RSA Engine Access Key Store Error Flag
+     * |        |          |0 = No error.
+     * |        |          |1 = Access error will stop RSA engine.
+     * @var CRPT_T::RSA_SADDR
+     * Offset: 0xB08-0xB18  RSA DMA Source Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SADDR0    |RSA DMA Source Address Register0
+     * |        |          |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelarator.
+     * |        |          |This register is stored the address of RSA the Base of Exponentiation (M,N,E,p,q).
+     * @var CRPT_T::RSA_DADDR
+     * Offset: 0xB1C  RSA DMA Destination Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DADDR     |RSA DMA Destination Address Register
+     * |        |          |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelarator.
+     * |        |          |This register is stored the address of RSA DMA Destination Address Register (Ans).
+     * @var CRPT_T::RSA_MADDR
+     * Offset: 0xB20-0xB38  RSA DMA Middle Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |MADDR     |RSA DMA Middle Address Register
+     * |        |          |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelarator.
+     * |        |          |This register is stored the address of RSA CRT the Temporary Value (Cp -> Mp -> Sp, Cq -> Mq -> Sq, Dp, Dq, Rp, Rq, E').
+     * @var CRPT_T::PRNG_KSCTL
+     * Offset: 0xF00  PRNG Key Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[4:0]   |NUM       |Write Key Number
+     * |        |          |The key number is sent to key store
+     * |        |          |Note: Only for destination Is OTP of Key Store.
+     * |[16]    |TRUST     |Write Key Trust Selection Bit
+     * |        |          |0 = Set written key as the non-secure key.
+     * |        |          |1 = Set written key as the secure key.
+     * |[18]    |PRIV      |Privilege Key Selection Bit
+     * |        |          |0 = Set key as the non-privilege key.
+     * |        |          |1 = Set key as the privilege key.
+     * |[19]    |ECDH      |ECDH Control Bit
+     * |        |          |0 =reserved.
+     * |        |          |1 = key is written to key store and used in ECDH.
+     * |        |          |Note:When ECDH was set to u20181u2019, 1
+     * |        |          |PRNG seed must from TRNG and key is must written to the SRAM of key store (WSDST, CRPT_PRNG_KSCTL[23:22] must set to u201800u2019)
+     * |        |          |Otherwise, KCTLERRwill become u20181u2019(CRPT_PRNG_KSSTS[16])
+     * |        |          |2
+     * |        |          |Key must in the interval [1, n-1] (the parameter n is from ECC)
+     * |        |          |The value of n canu2019t be 0 or 1, otherwise, PRNG will always keep busy.
+     * |[20]    |ECDSA     |ECDSA Control Bit
+     * |        |          |0 =reserved.
+     * |        |          |1 = key is written to key store and used in ECDSA.
+     * |        |          |Note:When ECDSA was set to u20181u2019, 1
+     * |        |          |PRNG seed must from TRNGand key is must written to the SRAM of key store (WSDST, CRPT_PRNG_KSCTL[23:22] must set to u201800u2019)
+     * |        |          |Otherwise, KCTLERRwill become u20181u2019(CRPT_PRNG_KSSTS[16])
+     * |        |          |2.Key must in the interval [1, n-1] (the parameter n is from ECC)
+     * |        |          |The value of n canu2019t be 0 or 1, otherwise, PRNG will always keep busy.
+     * |[21]    |WDST      |Write Key Destination
+     * |        |          |0 = key is written to registers CRPT_PRNG_KEYx.
+     * |        |          |1 = key is written to key store.
+     * |[23:22] |WSDST     |Write Key Store Destination
+     * |        |          |00 = key is written to the SRAM of key store.
+     * |        |          |10 = key is written to the OTP of key store.
+     * |        |          |Others = reserved.
+     * |[26:24] |OWNER     |Write Key Owner Selection Bits
+     * |        |          |000 = Only for AES used.
+     * |        |          |001 = Only for HMAC engine used.
+     * |        |          |100 = Only for ECC engine used.
+     * |        |          |101 = Only for CPU engine use.
+     * |        |          |Others = reserved.
+     * @var CRPT_T::PRNG_KSSTS
+     * Offset: 0xF04  PRNG Key Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[4:0]   |NUM       |Key Number
+     * |        |          |The key number is generated by key store
+     * |[16]    |KCTLERR   |PRNG Key Control Register Error Flag
+     * |        |          |0 = No error.
+     * |        |          |1 = PRNG key control error
+     * |        |          |When PRNG execute ECDSA or ECDH, but PRNG seed not from TRNG or key is not written to the SRAM of key store (WSDST,CRPT_PRNG_KSCTL[23:22] is not equal to u201900u2019).
+     * @var CRPT_T::AES_KSCTL
+     * Offset: 0xF10  AES Key Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[4:0]   |NUM       |Read Key Number
+     * |        |          |The key number is sent to key store
+     * |[5]     |RSRC      |Read Key Destination
+     * |        |          |0 = key is read from registers CRPT_AESx_KEYx.
+     * |        |          |1 = key is read from key store.
+     * |[7:6]   |RSSRC     |Read Key Store Destination
+     * |        |          |00 = key is read from the SRAM of key store.
+     * |        |          |10 = key is read from the OTP of key store.
+     * |        |          |Others = reserved.
+     * @var CRPT_T::HMAC_KSCTL
+     * Offset: 0xF30  HMAC Key Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[4:0]   |NUM       |Read Key Number
+     * |        |          |The key number is sent to key store
+     * |[5]     |RSRC      |Read Key Destination
+     * |        |          |0 = key is read from HMAC registers.
+     * |        |          |1 = key is read from key store.
+     * |[7:6]   |RSSRC     |Read Key Store Destination
+     * |        |          |00 = key is read from the SRAM of key store.
+     * |        |          |10 = key is read from the OTP of key store.
+     * |        |          |Others = reserved.
+     * @var CRPT_T::ECC_KSCTL
+     * Offset: 0xF40  ECC Key Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[4:0]   |NUMK      |Read Key Number K
+     * |        |          |The key number of CRPT_ECC_K is sent to key store when RSRCK =1.
+     * |[5]     |RSRCK     |Read Key Destinationfor Key Number K
+     * |        |          |0 = key is read from ECC registers.
+     * |        |          |1 = key is read from key store.
+     * |[7:6]   |RSSRCK    |Read Key Store Destinationfor Key Number K
+     * |        |          |00 = key is read from the SRAM of key store.
+     * |        |          |10 = key is read from the OTP of key store.
+     * |        |          |Others = reserved.
+     * |[14]    |ECDH      |ECDH Control Bit
+     * |        |          |0 =reserved.
+     * |        |          |1 = Set ECC opereration is in ECDH
+     * |        |          |When this bit and RSRCK are equal to 0x1, ECC will read ECDH private key to CRPT_ECC_K from key store.
+     * |[16]    |TRUST     |Write Key Trust Selection Bit
+     * |        |          |0 = Set ECDH written key as the non-secure key.
+     * |        |          |1 = Set ECDH written key as the secure key.
+     * |[18]    |PRIV      |Write Key Privilege Selection Bit
+     * |        |          |0 = Set ECDH written key as the non-privilege key.
+     * |        |          |1 = Set ECDHwritten key as the privilege key.
+     * |[20]    |XY        |ECDH Output Select Bit
+     * |        |          |0 =The ECDH written key is from X-coordinate Value.
+     * |        |          |1 = The ECDH written key is from Y-coordinate Value.
+     * |[21]    |WDST      |Write Key Destination
+     * |        |          |0 = The ECDH writtenkey is in registers CRPT_ECC_X1 and CRPT_ECC_Y.
+     * |        |          |1 = The ECDH writtenkey is written to key store.
+     * |[23:22] |WSDST     |Write Key Store Destination
+     * |        |          |00 = The ECDH writtenkey is written to the SRAM of key store.
+     * |        |          |10 = The ECDH writtenkey is written to the OTP of key store.
+     * |        |          |Others = reserved.
+     * |[26:24] |OWNER     |Write Key Owner Selection Bits
+     * |        |          |000 = The ECDH written key is only for AES used.
+     * |        |          |001 = The ECDH written key is only for HMAC engine used.
+     * |        |          |100 = The ECDH written key is only for ECC engine used.
+     * |        |          |101 = The ECDH written key is only for CPU engine use.
+     * |        |          |Others = reserved.
+     * @var CRPT_T::ECC_KSSTS
+     * Offset: 0xF44  ECC Key Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[4:0]   |NUM       |Key Number
+     * |        |          |The key number is generated by key store after ECDH.
+     * @var CRPT_T::ECC_KSXY
+     * Offset: 0xF48  ECC XY Number Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[4:0]   |NUMX      |Read Key Number X
+     * |        |          |The key number of CRPT_ECC_X1 is sent to key store when RSRCXY =1.
+     * |[5]     |RSRCXY    |Read Key Source for Key Number xand Y
+     * |        |          |0 = key is read from ECC registers.
+     * |        |          |1 = key is read from key store.
+     * |[7:6]   |RSSRCX    |Read Key Store Source for Key Number X
+     * |        |          |00 = key is read from the SRAM of key store.
+     * |        |          |10 = key is read from the OTP of key store.
+     * |        |          |Others = reserved.
+     * |[12:8]  |NUMY      |Read Key Number Y
+     * |        |          |The key number of CRPT_ECC_Y1 is sent to key store when RSRCXY =1.
+     * |[15:14] |RSSRCY    |Read Key Store Source for Key Number Y
+     * |        |          |00 = key is read from the SRAM of key store.
+     * |        |          |10 = key is read from the OTP of key store.
+     * |        |          |Others = reserved.
+     * @var CRPT_T::RSA_KSCTL
+     * Offset: 0xF50  RSA Key Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[4:0]   |NUM       |Read Key Number
+     * |        |          |The key number is sent to key store
+     * |[5]     |RSRC      |Read Key Destination
+     * |        |          |0 = key is read from RSA engine.
+     * |        |          |1 = key is read from key store.
+     * |[7:6]   |RSSRC     |Read Key Store Destination
+     * |        |          |00 = key is read from the SRAM of key store.
+     * |        |          |10 = key is read from the OTP of key store.
+     * |        |          |Others = reserved.
+     * |[12:8]  |BKNUM     |Read Exponent Blind Key Number
+     * |        |          |The key number is sent to key store, and its destination always be the SRAM of key store
+     * |        |          |CPU canu2019t read the exponent blind key.
+     * |        |          |Note:Use this key number, only when executing SCA protection but no-CRT mode.
+     * @var CRPT_T::RSA_KSSTS
+     * Offset: 0xF54-0xF58  RSA Key Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[4:0]   |NUM0      |Key Number0
+     * |        |          |The key number is generated by key store, RSA can get complete p by key number in Key Store while operating.
+     * |[12:8]  |NUM1      |Key Number1
+     * |        |          |The key number is generated by key store, RSA can get complete q by key number in Key Store while operating.
+     * |[20:16] |NUM2      |Key Number2
+     * |        |          |The key number is generated by key store, RSA can get or store Cp by key number in Key Store while operating.
+     * |[28:24] |NUM3      |Key Number3
+     * |        |          |The key number is generated by key store, RSA can get or store Cq by key number in Key Store while operating.
+     * |[36:32]  |NUM4      |Key Number4
+     * |        |          |The key number is generated by key store, RSA can get or store Dp by key number in Key Store while operating.
+     * |[44:40] |NUM5      |Key Number5
+     * |        |          |The key number is generated by key store, RSA can get or store Dq by key number in Key Store while operating.
+     * |[52:48] |NUM6      |Key Number6
+     * |        |          |The key number is generated by key store, RSA can get or store Rp by key number in Key Store while operating.
+     * |[60:56] |NUM7      |Key Number7
+     * |        |          |The key number is generated by key store, RSA can get or store Rq by key number in Key Store while operating.
+     */
+    __IO uint32_t INTEN;                 /*!< [0x0000] Crypto Interrupt Enable Control Register                         */
+    __IO uint32_t INTSTS;                /*!< [0x0004] Crypto Interrupt Flag                                            */
+    __IO uint32_t PRNG_CTL;              /*!< [0x0008] PRNG Control Register                                            */
+    __O  uint32_t PRNG_SEED;             /*!< [0x000c] Seed for PRNG                                                    */
+    __I  uint32_t PRNG_KEY[8];           /*!< [0x0010] ~ [0x002c] PRNG Generated Key0 ~ Key7                            */
+    __I  uint32_t PRNG_STS;              /*!< [0x0030] PRNG Status Register                                             */
+    __I  uint32_t RESERVE0[7];
+    __I  uint32_t AES_FDBCK[4];          /*!< [0x0050] ~ [0x005c] AES Engine Output Feedback Data after Cryptographic Operation    */
+    __I  uint32_t RESERVE1[8];
+    __IO uint32_t AES_GCM_IVCNT[2];        /*!< [0x0080] ~ [0x0084] AES GCM IV Byte Count Register 0                                 */
+    __IO uint32_t AES_GCM_ACNT[2];         /*!< [0x0088] ~ [0x008c] AES GCM A Byte Count Register 0                                  */
+    __IO uint32_t AES_GCM_PCNT[2];         /*!< [0x0090] ~ [0x0094] AES GCM P Byte Count Register 0                                  */
+    __I  uint32_t RESERVE2[2];
+    __IO uint32_t AES_FBADDR;            /*!< [0x00a0] AES DMA Feedback Address Register                                */
+    __I  uint32_t RESERVE3[23];
+    __IO uint32_t AES_CTL;               /*!< [0x0100] AES Control Register                                             */
+    __I  uint32_t AES_STS;               /*!< [0x0104] AES Engine Flag                                                  */
+    __IO uint32_t AES_DATIN;             /*!< [0x0108] AES Engine Data Input Port Register                              */
+    __I  uint32_t AES_DATOUT;            /*!< [0x010c] AES Engine Data Output Port Register                             */
+    __IO uint32_t AES_KEY[8];           /*!< [0x0110] ~ [0x012c] AES Key Word 0~7 Register for Channel 0                */
+    __IO uint32_t AES_IV[4];            /*!< [0x0130] ~ [0x013c] AES Initial Vector Word 0 ~ 3 Register for Channel 0   */
+    __IO uint32_t AES_SADDR;             /*!< [0x0140] AES DMA Source Address Register                                  */
+    __IO uint32_t AES_DADDR;             /*!< [0x0144] AES DMA Destination Address Register                             */
+    __IO uint32_t AES_CNT;               /*!< [0x0148] AES Byte Count Register                                          */
+    __I  uint32_t RESERVE4[109];
+    __IO uint32_t HMAC_CTL;              /*!< [0x0300] SHA/HMAC Control Register                                        */
+    __I  uint32_t HMAC_STS;              /*!< [0x0304] SHA/HMAC Status Flag                                             */
+    __I  uint32_t HMAC_DGST[16];         /*!< [0x0308] ~ [0x0344] SHA/HMAC Digest Message 0~15                          */
+    __IO uint32_t HMAC_KEYCNT;           /*!< [0x0348] SHA/HMAC Key Byte Count Register                                 */
+    __IO uint32_t HMAC_SADDR;            /*!< [0x034c] SHA/HMAC DMA Source Address Register                             */
+    __IO uint32_t HMAC_DMACNT;           /*!< [0x0350] SHA/HMAC Byte Count Register                                     */
+    __IO uint32_t HMAC_DATIN;            /*!< [0x0354] SHA/HMAC Engine Non-dMA Mode Data Input Port Register            */
+    __IO uint32_t HMAC_FDBCK[54];           /*!< [0x0358] ~ [0x042c] SHA/HMAC Output Feedback Data 0After SHA/HMAC Operation          */
+    __I  uint32_t RESERVE5[51];
+    __IO uint32_t HMAC_FBADDR;           /*!< [0x04fc] SHA/HMAC DMA Feedback Address Register                           */
+    __I  uint32_t RESERVE6[192];
+    __IO uint32_t ECC_CTL;               /*!< [0x0800] ECC Control Register                                             */
+    __I  uint32_t ECC_STS;               /*!< [0x0804] ECC Status Register                                              */
+    __IO uint32_t ECC_X1[18];             /*!< [0x0808] ~ [0x084c] ECC the X-coordinate Word0 of the First Point        */
+    __IO uint32_t ECC_Y1[18];            /*!< [0x0850] ~ [0x0894] ECC The Y-coordinate word 0~17 of the first point     */
+    __IO uint32_t ECC_X2[18];            /*!< [0x0898] ~ [0x08dc] ECC The X-coordinate word 0~17 of the second point    */
+    __IO uint32_t ECC_Y2[18];            /*!< [0x08e0] ~ [0x0924] ECC The Y-coordinate word 0~17 of the second point    */
+    __IO uint32_t ECC_A[18];             /*!< [0x0928] ~ [0x096c] ECC The parameter CURVEA word 0~17 of elliptic curve  */
+    __IO uint32_t ECC_B[18];             /*!< [0x0970] ~ [0x09b4] ECC The parameter CURVEB word 0~17 of elliptic curve  */
+    __IO uint32_t ECC_N[18];             /*!< [0x09b8] ~ [0x09fc] ECC The parameter CURVEN word 0~17 of elliptic curve  */
+    __O  uint32_t ECC_K[18];             /*!< [0x0a00] ~ [0x0a44] ECC The scalar SCALARK word 0~17 of point multiplication */
+    __IO uint32_t ECC_SADDR;             /*!< [0x0a48] ECC DMA Source Address Register                                  */
+    __IO uint32_t ECC_DADDR;             /*!< [0x0a4c] ECC DMA Destination Address Register                             */
+    __IO uint32_t ECC_STARTREG;          /*!< [0x0a50] ECC Starting Address of Updated Registers                        */
+    __IO uint32_t ECC_WORDCNT;           /*!< [0x0a54] ECC DMA Word Count                                               */
+    __I  uint32_t RESERVE7[42];
+    __IO uint32_t RSA_CTL;               /*!< [0x0b00] RSA Control Register                                             */
+    __I  uint32_t RSA_STS;               /*!< [0x0b04] RSA Status Register                                              */
+    __IO uint32_t RSA_SADDR[5];          /*!< [0x0b08] ~ [0x0b18] RSA DMA Source Address Register0                      */
+    __IO uint32_t RSA_DADDR;             /*!< [0x0b1c] RSA DMA Destination Address Register                             */
+    __IO uint32_t RSA_MADDR[7];          /*!< [0x0b20] ~ [0x0b38] RSA DMA Middle Address Register0                      */
+    __I  uint32_t RESERVE8[241];
+    __O  uint32_t PRNG_KSCTL;            /*!< [0x0f00] PRNG Key Control Register                                        */
+    __I  uint32_t PRNG_KSSTS;            /*!< [0x0f04] PRNG Key Status Register                                         */
+    __I  uint32_t RESERVE9[2];
+    __O  uint32_t AES_KSCTL;             /*!< [0x0f10] AES Key Control Register                                         */
+    __I  uint32_t RESERVE10[7];
+    __O  uint32_t HMAC_KSCTL;            /*!< [0x0f30] HMAC Key Control Register                                        */
+    __I  uint32_t RESERVE11[3];
+    __O  uint32_t ECC_KSCTL;             /*!< [0x0f40] ECC Key Control Register                                         */
+    __I  uint32_t ECC_KSSTS;             /*!< [0x0f44] ECC Key Status Register                                          */
+    __O  uint32_t ECC_KSXY;              /*!< [0x0f48] ECC XY Number Register                                           */
+    __I  uint32_t RESERVE12[1];
+    __O  uint32_t RSA_KSCTL;             /*!< [0x0f50] RSA Key Control Register                                         */
+    __IO uint32_t RSA_KSSTS[2];          /*!< [0x0f54] ~ [0x0f58] RSA Key Status Register 0                             */
+    __I  uint32_t RESERVE13[40];
+
+} CRPT_T;
+
+/**
+    @addtogroup CRPT_CONST CRYPTO Bit Field Definition
+    Constant Definitions for CRYPTO Controller
+  @{
+*/
+
+#define CRPT_INTEN_AESIEN_Pos          (0)                                               /*!< CRPT_T::INTEN: AESIEN Position       */
+#define CRPT_INTEN_AESIEN_Msk          (0x1ul << CRPT_INTEN_AESIEN_Pos)                /*!< CRPT_T::INTEN: AESIEN Mask           */
+
+#define CRPT_INTEN_AESEIEN_Pos         (1)                                               /*!< CRPT_T::INTEN: AESEIEN Position      */
+#define CRPT_INTEN_AESEIEN_Msk         (0x1ul << CRPT_INTEN_AESEIEN_Pos)               /*!< CRPT_T::INTEN: AESEIEN Mask          */
+
+#define CRPT_INTEN_PRNGIEN_Pos         (16)                                              /*!< CRPT_T::INTEN: PRNGIEN Position      */
+#define CRPT_INTEN_PRNGIEN_Msk         (0x1ul << CRPT_INTEN_PRNGIEN_Pos)               /*!< CRPT_T::INTEN: PRNGIEN Mask          */
+
+#define CRPT_INTEN_PRNGEIEN_Pos        (17)                                              /*!< CRPT_T::INTEN: PRNGEIEN Position     */
+#define CRPT_INTEN_PRNGEIEN_Msk        (0x1ul << CRPT_INTEN_PRNGEIEN_Pos)              /*!< CRPT_T::INTEN: PRNGEIEN Mask         */
+
+#define CRPT_INTEN_ECCIEN_Pos          (22)                                              /*!< CRPT_T::INTEN: ECCIEN Position       */
+#define CRPT_INTEN_ECCIEN_Msk          (0x1ul << CRPT_INTEN_ECCIEN_Pos)                /*!< CRPT_T::INTEN: ECCIEN Mask           */
+
+#define CRPT_INTEN_ECCEIEN_Pos         (23)                                              /*!< CRPT_T::INTEN: ECCEIEN Position      */
+#define CRPT_INTEN_ECCEIEN_Msk         (0x1ul << CRPT_INTEN_ECCEIEN_Pos)               /*!< CRPT_T::INTEN: ECCEIEN Mask          */
+
+#define CRPT_INTEN_HMACIEN_Pos         (24)                                              /*!< CRPT_T::INTEN: HMACIEN Position      */
+#define CRPT_INTEN_HMACIEN_Msk         (0x1ul << CRPT_INTEN_HMACIEN_Pos)               /*!< CRPT_T::INTEN: HMACIEN Mask          */
+
+#define CRPT_INTEN_HMACEIEN_Pos        (25)                                              /*!< CRPT_T::INTEN: HMACEIEN Position     */
+#define CRPT_INTEN_HMACEIEN_Msk        (0x1ul << CRPT_INTEN_HMACEIEN_Pos)              /*!< CRPT_T::INTEN: HMACEIEN Mask         */
+
+#define CRPT_INTEN_RSAIEN_Pos          (30)                                              /*!< CRPT_T::INTEN: RSAIEN Position       */
+#define CRPT_INTEN_RSAIEN_Msk          (0x1ul << CRPT_INTEN_RSAIEN_Pos)                /*!< CRPT_T::INTEN: RSAIEN Mask           */
+
+#define CRPT_INTEN_RSAEIEN_Pos         (31)                                              /*!< CRPT_T::INTEN: RSAEIEN Position      */
+#define CRPT_INTEN_RSAEIEN_Msk         (0x1ul << CRPT_INTEN_RSAEIEN_Pos)               /*!< CRPT_T::INTEN: RSAEIEN Mask          */
+
+#define CRPT_INTSTS_AESIF_Pos          (0)                                               /*!< CRPT_T::INTSTS: AESIF Position       */
+#define CRPT_INTSTS_AESIF_Msk          (0x1ul << CRPT_INTSTS_AESIF_Pos)                /*!< CRPT_T::INTSTS: AESIF Mask           */
+
+#define CRPT_INTSTS_AESEIF_Pos         (1)                                               /*!< CRPT_T::INTSTS: AESEIF Position      */
+#define CRPT_INTSTS_AESEIF_Msk         (0x1ul << CRPT_INTSTS_AESEIF_Pos)               /*!< CRPT_T::INTSTS: AESEIF Mask          */
+
+#define CRPT_INTSTS_PRNGIF_Pos         (16)                                              /*!< CRPT_T::INTSTS: PRNGIF Position      */
+#define CRPT_INTSTS_PRNGIF_Msk         (0x1ul << CRPT_INTSTS_PRNGIF_Pos)               /*!< CRPT_T::INTSTS: PRNGIF Mask          */
+
+#define CRPT_INTSTS_PRNGEIF_Pos        (17)                                              /*!< CRPT_T::INTSTS: PRNGEIF Position     */
+#define CRPT_INTSTS_PRNGEIF_Msk        (0x1ul << CRPT_INTSTS_PRNGEIF_Pos)              /*!< CRPT_T::INTSTS: PRNGEIF Mask         */
+
+#define CRPT_INTSTS_ECCIF_Pos          (22)                                              /*!< CRPT_T::INTSTS: ECCIF Position       */
+#define CRPT_INTSTS_ECCIF_Msk          (0x1ul << CRPT_INTSTS_ECCIF_Pos)                /*!< CRPT_T::INTSTS: ECCIF Mask           */
+
+#define CRPT_INTSTS_ECCEIF_Pos         (23)                                              /*!< CRPT_T::INTSTS: ECCEIF Position      */
+#define CRPT_INTSTS_ECCEIF_Msk         (0x1ul << CRPT_INTSTS_ECCEIF_Pos)               /*!< CRPT_T::INTSTS: ECCEIF Mask          */
+
+#define CRPT_INTSTS_HMACIF_Pos         (24)                                              /*!< CRPT_T::INTSTS: HMACIF Position      */
+#define CRPT_INTSTS_HMACIF_Msk         (0x1ul << CRPT_INTSTS_HMACIF_Pos)               /*!< CRPT_T::INTSTS: HMACIF Mask          */
+
+#define CRPT_INTSTS_HMACEIF_Pos        (25)                                              /*!< CRPT_T::INTSTS: HMACEIF Position     */
+#define CRPT_INTSTS_HMACEIF_Msk        (0x1ul << CRPT_INTSTS_HMACEIF_Pos)              /*!< CRPT_T::INTSTS: HMACEIF Mask         */
+
+#define CRPT_INTSTS_RSAIF_Pos          (30)                                              /*!< CRPT_T::INTSTS: RSAIF Position       */
+#define CRPT_INTSTS_RSAIF_Msk          (0x1ul << CRPT_INTSTS_RSAIF_Pos)                /*!< CRPT_T::INTSTS: RSAIF Mask           */
+
+#define CRPT_INTSTS_RSAEIF_Pos         (31)                                              /*!< CRPT_T::INTSTS: RSAEIF Position      */
+#define CRPT_INTSTS_RSAEIF_Msk         (0x1ul << CRPT_INTSTS_RSAEIF_Pos)               /*!< CRPT_T::INTSTS: RSAEIF Mask          */
+
+#define CRPT_PRNG_CTL_START_Pos        (0)                                               /*!< CRPT_T::PRNG_CTL: START Position     */
+#define CRPT_PRNG_CTL_START_Msk        (0x1ul << CRPT_PRNG_CTL_START_Pos)              /*!< CRPT_T::PRNG_CTL: START Mask         */
+
+#define CRPT_PRNG_CTL_SEEDRLD_Pos      (1)                                               /*!< CRPT_T::PRNG_CTL: SEEDRLD Position   */
+#define CRPT_PRNG_CTL_SEEDRLD_Msk      (0x1ul << CRPT_PRNG_CTL_SEEDRLD_Pos)            /*!< CRPT_T::PRNG_CTL: SEEDRLD Mask       */
+
+#define CRPT_PRNG_CTL_KEYSZ_Pos        (2)                                               /*!< CRPT_T::PRNG_CTL: KEYSZ Position     */
+#define CRPT_PRNG_CTL_KEYSZ_Msk        (0xful << CRPT_PRNG_CTL_KEYSZ_Pos)              /*!< CRPT_T::PRNG_CTL: KEYSZ Mask         */
+
+#define CRPT_PRNG_CTL_SEEDSEL_Pos      (6)                                               /*!< CRPT_T::PRNG_CTL: SEEDSEL Position   */
+#define CRPT_PRNG_CTL_SEEDSEL_Msk      (0x1ul << CRPT_PRNG_CTL_SEEDSEL_Pos)            /*!< CRPT_T::PRNG_CTL: SEEDSEL Mask       */
+
+#define CRPT_PRNG_CTL_SEEDSRC_Pos      (7)                                               /*!< CRPT_T::PRNG_CTL: SEEDSRC Position   */
+#define CRPT_PRNG_CTL_SEEDSRC_Msk      (0x1ul << CRPT_PRNG_CTL_SEEDSRC_Pos)            /*!< CRPT_T::PRNG_CTL: SEEDSRC Mask       */
+
+#define CRPT_PRNG_CTL_BUSY_Pos         (8)                                               /*!< CRPT_T::PRNG_CTL: BUSY Position      */
+#define CRPT_PRNG_CTL_BUSY_Msk         (0x1ul << CRPT_PRNG_CTL_BUSY_Pos)               /*!< CRPT_T::PRNG_CTL: BUSY Mask          */
+
+#define CRPT_PRNG_SEED_SEED_Pos        (0)                                               /*!< CRPT_T::PRNG_SEED: SEED Position     */
+#define CRPT_PRNG_SEED_SEED_Msk        (0xfffffffful << CRPT_PRNG_SEED_SEED_Pos)       /*!< CRPT_T::PRNG_SEED: SEED Mask         */
+
+#define CRPT_PRNG_KEY0_KEY_Pos         (0)                                               /*!< CRPT_T::PRNG_KEY0: KEY Position      */
+#define CRPT_PRNG_KEY0_KEY_Msk         (0xfffffffful << CRPT_PRNG_KEY0_KEY_Pos)        /*!< CRPT_T::PRNG_KEY0: KEY Mask          */
+
+#define CRPT_PRNG_KEY1_KEY_Pos         (0)                                               /*!< CRPT_T::PRNG_KEY1: KEY Position      */
+#define CRPT_PRNG_KEY1_KEY_Msk         (0xfffffffful << CRPT_PRNG_KEY1_KEY_Pos)        /*!< CRPT_T::PRNG_KEY1: KEY Mask          */
+
+#define CRPT_PRNG_KEY2_KEY_Pos         (0)                                               /*!< CRPT_T::PRNG_KEY2: KEY Position      */
+#define CRPT_PRNG_KEY2_KEY_Msk         (0xfffffffful << CRPT_PRNG_KEY2_KEY_Pos)        /*!< CRPT_T::PRNG_KEY2: KEY Mask          */
+
+#define CRPT_PRNG_KEY3_KEY_Pos         (0)                                               /*!< CRPT_T::PRNG_KEY3: KEY Position      */
+#define CRPT_PRNG_KEY3_KEY_Msk         (0xfffffffful << CRPT_PRNG_KEY3_KEY_Pos)        /*!< CRPT_T::PRNG_KEY3: KEY Mask          */
+
+#define CRPT_PRNG_KEY4_KEY_Pos         (0)                                               /*!< CRPT_T::PRNG_KEY4: KEY Position      */
+#define CRPT_PRNG_KEY4_KEY_Msk         (0xfffffffful << CRPT_PRNG_KEY4_KEY_Pos)        /*!< CRPT_T::PRNG_KEY4: KEY Mask          */
+
+#define CRPT_PRNG_KEY5_KEY_Pos         (0)                                               /*!< CRPT_T::PRNG_KEY5: KEY Position      */
+#define CRPT_PRNG_KEY5_KEY_Msk         (0xfffffffful << CRPT_PRNG_KEY5_KEY_Pos)        /*!< CRPT_T::PRNG_KEY5: KEY Mask          */
+
+#define CRPT_PRNG_KEY6_KEY_Pos         (0)                                               /*!< CRPT_T::PRNG_KEY6: KEY Position      */
+#define CRPT_PRNG_KEY6_KEY_Msk         (0xfffffffful << CRPT_PRNG_KEY6_KEY_Pos)        /*!< CRPT_T::PRNG_KEY6: KEY Mask          */
+
+#define CRPT_PRNG_KEY7_KEY_Pos         (0)                                               /*!< CRPT_T::PRNG_KEY7: KEY Position      */
+#define CRPT_PRNG_KEY7_KEY_Msk         (0xfffffffful << CRPT_PRNG_KEY7_KEY_Pos)        /*!< CRPT_T::PRNG_KEY7: KEY Mask          */
+
+#define CRPT_PRNG_STS_BUSY_Pos         (0)                                               /*!< CRPT_T::PRNG_STS: BUSY Position      */
+#define CRPT_PRNG_STS_BUSY_Msk         (0x1ul << CRPT_PRNG_STS_BUSY_Pos)               /*!< CRPT_T::PRNG_STS: BUSY Mask          */
+
+#define CRPT_PRNG_STS_KCTLERR_Pos      (16)                                              /*!< CRPT_T::PRNG_STS: KCTLERR Position   */
+#define CRPT_PRNG_STS_KCTLERR_Msk      (0x1ul << CRPT_PRNG_STS_KCTLERR_Pos)            /*!< CRPT_T::PRNG_STS: KCTLERR Mask       */
+
+#define CRPT_PRNG_STS_KSERR_Pos        (17)                                              /*!< CRPT_T::PRNG_STS: KSERR Position     */
+#define CRPT_PRNG_STS_KSERR_Msk        (0x1ul << CRPT_PRNG_STS_KSERR_Pos)              /*!< CRPT_T::PRNG_STS: KSERR Mask         */
+
+#define CRPT_AES_FDBCK0_FDBCK_Pos      (0)                                               /*!< CRPT_T::AES_FDBCK0: FDBCK Position   */
+#define CRPT_AES_FDBCK0_FDBCK_Msk      (0xfffffffful << CRPT_AES_FDBCK0_FDBCK_Pos)     /*!< CRPT_T::AES_FDBCK0: FDBCK Mask       */
+
+#define CRPT_AES_FDBCK1_FDBCK_Pos      (0)                                               /*!< CRPT_T::AES_FDBCK1: FDBCK Position   */
+#define CRPT_AES_FDBCK1_FDBCK_Msk      (0xfffffffful << CRPT_AES_FDBCK1_FDBCK_Pos)     /*!< CRPT_T::AES_FDBCK1: FDBCK Mask       */
+
+#define CRPT_AES_FDBCK2_FDBCK_Pos      (0)                                               /*!< CRPT_T::AES_FDBCK2: FDBCK Position   */
+#define CRPT_AES_FDBCK2_FDBCK_Msk      (0xfffffffful << CRPT_AES_FDBCK2_FDBCK_Pos)     /*!< CRPT_T::AES_FDBCK2: FDBCK Mask       */
+
+#define CRPT_AES_FDBCK3_FDBCK_Pos      (0)                                               /*!< CRPT_T::AES_FDBCK3: FDBCK Position   */
+#define CRPT_AES_FDBCK3_FDBCK_Msk      (0xfffffffful << CRPT_AES_FDBCK3_FDBCK_Pos)     /*!< CRPT_T::AES_FDBCK3: FDBCK Mask       */
+
+#define CRPT_AES_GCM_IVCNT0_CNT_Pos    (0)                                               /*!< CRPT_T::AES_GCM_IVCNT0: CNT Position */
+#define CRPT_AES_GCM_IVCNT0_CNT_Msk    (0xfffffffful << CRPT_AES_GCM_IVCNT0_CNT_Pos)   /*!< CRPT_T::AES_GCM_IVCNT0: CNT Mask     */
+
+#define CRPT_AES_GCM_IVCNT1_CNT_Pos    (0)                                               /*!< CRPT_T::AES_GCM_IVCNT1: CNT Position */
+#define CRPT_AES_GCM_IVCNT1_CNT_Msk    (0x1ffffffful << CRPT_AES_GCM_IVCNT1_CNT_Pos)   /*!< CRPT_T::AES_GCM_IVCNT1: CNT Mask     */
+
+#define CRPT_AES_GCM_ACNT0_CNT_Pos     (0)                                               /*!< CRPT_T::AES_GCM_ACNT0: CNT Position  */
+#define CRPT_AES_GCM_ACNT0_CNT_Msk     (0xfffffffful << CRPT_AES_GCM_ACNT0_CNT_Pos)    /*!< CRPT_T::AES_GCM_ACNT0: CNT Mask      */
+
+#define CRPT_AES_GCM_ACNT1_CNT_Pos     (0)                                               /*!< CRPT_T::AES_GCM_ACNT1: CNT Position  */
+#define CRPT_AES_GCM_ACNT1_CNT_Msk     (0x1ffffffful << CRPT_AES_GCM_ACNT1_CNT_Pos)    /*!< CRPT_T::AES_GCM_ACNT1: CNT Mask      */
+
+#define CRPT_AES_GCM_PCNT0_CNT_Pos     (0)                                               /*!< CRPT_T::AES_GCM_PCNT0: CNT Position  */
+#define CRPT_AES_GCM_PCNT0_CNT_Msk     (0xfffffffful << CRPT_AES_GCM_PCNT0_CNT_Pos)    /*!< CRPT_T::AES_GCM_PCNT0: CNT Mask      */
+
+#define CRPT_AES_GCM_PCNT1_CNT_Pos     (0)                                               /*!< CRPT_T::AES_GCM_PCNT1: CNT Position  */
+#define CRPT_AES_GCM_PCNT1_CNT_Msk     (0x1ffffffful << CRPT_AES_GCM_PCNT1_CNT_Pos)    /*!< CRPT_T::AES_GCM_PCNT1: CNT Mask      */
+
+#define CRPT_AES_FBADDR_FBADDR_Pos     (0)                                               /*!< CRPT_T::AES_FBADDR: FBADDR Position  */
+#define CRPT_AES_FBADDR_FBADDR_Msk     (0xfffffffful << CRPT_AES_FBADDR_FBADDR_Pos)    /*!< CRPT_T::AES_FBADDR: FBADDR Mask      */
+
+#define CRPT_AES_CTL_START_Pos         (0)                                               /*!< CRPT_T::AES_CTL: START Position      */
+#define CRPT_AES_CTL_START_Msk         (0x1ul << CRPT_AES_CTL_START_Pos)               /*!< CRPT_T::AES_CTL: START Mask          */
+
+#define CRPT_AES_CTL_STOP_Pos          (1)                                               /*!< CRPT_T::AES_CTL: STOP Position       */
+#define CRPT_AES_CTL_STOP_Msk          (0x1ul << CRPT_AES_CTL_STOP_Pos)                /*!< CRPT_T::AES_CTL: STOP Mask           */
+
+#define CRPT_AES_CTL_KEYSZ_Pos         (2)                                               /*!< CRPT_T::AES_CTL: KEYSZ Position      */
+#define CRPT_AES_CTL_KEYSZ_Msk         (0x3ul << CRPT_AES_CTL_KEYSZ_Pos)               /*!< CRPT_T::AES_CTL: KEYSZ Mask          */
+
+#define CRPT_AES_CTL_DMALAST_Pos       (5)                                               /*!< CRPT_T::AES_CTL: DMALAST Position    */
+#define CRPT_AES_CTL_DMALAST_Msk       (0x1ul << CRPT_AES_CTL_DMALAST_Pos)             /*!< CRPT_T::AES_CTL: DMALAST Mask        */
+
+#define CRPT_AES_CTL_DMACSCAD_Pos      (6)                                               /*!< CRPT_T::AES_CTL: DMACSCAD Position   */
+#define CRPT_AES_CTL_DMACSCAD_Msk      (0x1ul << CRPT_AES_CTL_DMACSCAD_Pos)            /*!< CRPT_T::AES_CTL: DMACSCAD Mask       */
+
+#define CRPT_AES_CTL_DMAEN_Pos         (7)                                               /*!< CRPT_T::AES_CTL: DMAEN Position      */
+#define CRPT_AES_CTL_DMAEN_Msk         (0x1ul << CRPT_AES_CTL_DMAEN_Pos)               /*!< CRPT_T::AES_CTL: DMAEN Mask          */
+
+#define CRPT_AES_CTL_OPMODE_Pos        (8)                                               /*!< CRPT_T::AES_CTL: OPMODE Position     */
+#define CRPT_AES_CTL_OPMODE_Msk        (0xfful << CRPT_AES_CTL_OPMODE_Pos)             /*!< CRPT_T::AES_CTL: OPMODE Mask         */
+
+#define CRPT_AES_CTL_ENCRPT_Pos      (16)                                              /*!< CRPT_T::AES_CTL: ENCRYPTO Position   */
+#define CRPT_AES_CTL_ENCRPT_Msk      (0x1ul << CRPT_AES_CTL_ENCRPT_Pos)            /*!< CRPT_T::AES_CTL: ENCRYPTO Mask       */
+
+#define CRPT_AES_CTL_SM4EN_Pos         (17)                                              /*!< CRPT_T::AES_CTL: SM4EN Position      */
+#define CRPT_AES_CTL_SM4EN_Msk         (0x1ul << CRPT_AES_CTL_SM4EN_Pos)               /*!< CRPT_T::AES_CTL: SM4EN Mask          */
+
+#define CRPT_AES_CTL_FBIN_Pos          (20)                                              /*!< CRPT_T::AES_CTL: FBIN Position       */
+#define CRPT_AES_CTL_FBIN_Msk          (0x1ul << CRPT_AES_CTL_FBIN_Pos)                /*!< CRPT_T::AES_CTL: FBIN Mask           */
+
+#define CRPT_AES_CTL_FBOUT_Pos         (21)                                              /*!< CRPT_T::AES_CTL: FBOUT Position      */
+#define CRPT_AES_CTL_FBOUT_Msk         (0x1ul << CRPT_AES_CTL_FBOUT_Pos)               /*!< CRPT_T::AES_CTL: FBOUT Mask          */
+
+#define CRPT_AES_CTL_OUTSWAP_Pos       (22)                                              /*!< CRPT_T::AES_CTL: OUTSWAP Position    */
+#define CRPT_AES_CTL_OUTSWAP_Msk       (0x1ul << CRPT_AES_CTL_OUTSWAP_Pos)             /*!< CRPT_T::AES_CTL: OUTSWAP Mask        */
+
+#define CRPT_AES_CTL_INSWAP_Pos        (23)                                              /*!< CRPT_T::AES_CTL: INSWAP Position     */
+#define CRPT_AES_CTL_INSWAP_Msk        (0x1ul << CRPT_AES_CTL_INSWAP_Pos)              /*!< CRPT_T::AES_CTL: INSWAP Mask         */
+
+#define CRPT_AES_CTL_KOUTSWAP_Pos      (24)                                              /*!< CRPT_T::AES_CTL: KOUTSWAP Position   */
+#define CRPT_AES_CTL_KOUTSWAP_Msk      (0x1ul << CRPT_AES_CTL_KOUTSWAP_Pos)            /*!< CRPT_T::AES_CTL: KOUTSWAP Mask       */
+
+#define CRPT_AES_CTL_KINSWAP_Pos       (25)                                              /*!< CRPT_T::AES_CTL: KINSWAP Position    */
+#define CRPT_AES_CTL_KINSWAP_Msk       (0x1ul << CRPT_AES_CTL_KINSWAP_Pos)             /*!< CRPT_T::AES_CTL: KINSWAP Mask        */
+
+#define CRPT_AES_CTL_KEYUNPRT_Pos      (26)                                              /*!< CRPT_T::AES_CTL: KEYUNPRT Position   */
+#define CRPT_AES_CTL_KEYUNPRT_Msk      (0x1ful << CRPT_AES_CTL_KEYUNPRT_Pos)           /*!< CRPT_T::AES_CTL: KEYUNPRT Mask       */
+
+#define CRPT_AES_CTL_KEYPRT_Pos        (31)                                              /*!< CRPT_T::AES_CTL: KEYPRT Position     */
+#define CRPT_AES_CTL_KEYPRT_Msk        (0x1ul << CRPT_AES_CTL_KEYPRT_Pos)              /*!< CRPT_T::AES_CTL: KEYPRT Mask         */
+
+#define CRPT_AES_STS_BUSY_Pos          (0)                                               /*!< CRPT_T::AES_STS: BUSY Position       */
+#define CRPT_AES_STS_BUSY_Msk          (0x1ul << CRPT_AES_STS_BUSY_Pos)                /*!< CRPT_T::AES_STS: BUSY Mask           */
+
+#define CRPT_AES_STS_INBUFEMPTY_Pos    (8)                                               /*!< CRPT_T::AES_STS: INBUFEMPTY Position */
+#define CRPT_AES_STS_INBUFEMPTY_Msk    (0x1ul << CRPT_AES_STS_INBUFEMPTY_Pos)          /*!< CRPT_T::AES_STS: INBUFEMPTY Mask     */
+
+#define CRPT_AES_STS_INBUFFULL_Pos     (9)                                               /*!< CRPT_T::AES_STS: INBUFFULL Position  */
+#define CRPT_AES_STS_INBUFFULL_Msk     (0x1ul << CRPT_AES_STS_INBUFFULL_Pos)           /*!< CRPT_T::AES_STS: INBUFFULL Mask      */
+
+#define CRPT_AES_STS_INBUFERR_Pos      (10)                                              /*!< CRPT_T::AES_STS: INBUFERR Position   */
+#define CRPT_AES_STS_INBUFERR_Msk      (0x1ul << CRPT_AES_STS_INBUFERR_Pos)            /*!< CRPT_T::AES_STS: INBUFERR Mask       */
+
+#define CRPT_AES_STS_CNTERR_Pos        (12)                                              /*!< CRPT_T::AES_STS: CNTERR Position     */
+#define CRPT_AES_STS_CNTERR_Msk        (0x1ul << CRPT_AES_STS_CNTERR_Pos)              /*!< CRPT_T::AES_STS: CNTERR Mask         */
+
+#define CRPT_AES_STS_OUTBUFEMPTY_Pos   (16)                                              /*!< CRPT_T::AES_STS: OUTBUFEMPTY Position*/
+#define CRPT_AES_STS_OUTBUFEMPTY_Msk   (0x1ul << CRPT_AES_STS_OUTBUFEMPTY_Pos)         /*!< CRPT_T::AES_STS: OUTBUFEMPTY Mask    */
+
+#define CRPT_AES_STS_OUTBUFFULL_Pos    (17)                                              /*!< CRPT_T::AES_STS: OUTBUFFULL Position */
+#define CRPT_AES_STS_OUTBUFFULL_Msk    (0x1ul << CRPT_AES_STS_OUTBUFFULL_Pos)          /*!< CRPT_T::AES_STS: OUTBUFFULL Mask     */
+
+#define CRPT_AES_STS_OUTBUFERR_Pos     (18)                                              /*!< CRPT_T::AES_STS: OUTBUFERR Position  */
+#define CRPT_AES_STS_OUTBUFERR_Msk     (0x1ul << CRPT_AES_STS_OUTBUFERR_Pos)           /*!< CRPT_T::AES_STS: OUTBUFERR Mask      */
+
+#define CRPT_AES_STS_BUSERR_Pos        (20)                                              /*!< CRPT_T::AES_STS: BUSERR Position     */
+#define CRPT_AES_STS_BUSERR_Msk        (0x1ul << CRPT_AES_STS_BUSERR_Pos)              /*!< CRPT_T::AES_STS: BUSERR Mask         */
+
+#define CRPT_AES_STS_KSERR_Pos         (21)                                              /*!< CRPT_T::AES_STS: KSERR Position      */
+#define CRPT_AES_STS_KSERR_Msk         (0x1ul << CRPT_AES_STS_KSERR_Pos)               /*!< CRPT_T::AES_STS: KSERR Mask          */
+
+#define CRPT_AES_DATIN_DATIN_Pos       (0)                                               /*!< CRPT_T::AES_DATIN: DATIN Position    */
+#define CRPT_AES_DATIN_DATIN_Msk       (0xfffffffful << CRPT_AES_DATIN_DATIN_Pos)      /*!< CRPT_T::AES_DATIN: DATIN Mask        */
+
+#define CRPT_AES_DATOUT_DATOUT_Pos     (0)                                               /*!< CRPT_T::AES_DATOUT: DATOUT Position  */
+#define CRPT_AES_DATOUT_DATOUT_Msk     (0xfffffffful << CRPT_AES_DATOUT_DATOUT_Pos)    /*!< CRPT_T::AES_DATOUT: DATOUT Mask      */
+
+#define CRPT_AES_KEY0_KEY_Pos          (0)                                               /*!< CRPT_T::AES_KEY0: KEY Position       */
+#define CRPT_AES_KEY0_KEY_Msk          (0xfffffffful << CRPT_AES_KEY0_KEY_Pos)         /*!< CRPT_T::AES_KEY0: KEY Mask           */
+
+#define CRPT_AES_KEY1_KEY_Pos          (0)                                               /*!< CRPT_T::AES_KEY1: KEY Position       */
+#define CRPT_AES_KEY1_KEY_Msk          (0xfffffffful << CRPT_AES_KEY1_KEY_Pos)         /*!< CRPT_T::AES_KEY1: KEY Mask           */
+
+#define CRPT_AES_KEY2_KEY_Pos          (0)                                               /*!< CRPT_T::AES_KEY2: KEY Position       */
+#define CRPT_AES_KEY2_KEY_Msk          (0xfffffffful << CRPT_AES_KEY2_KEY_Pos)         /*!< CRPT_T::AES_KEY2: KEY Mask           */
+
+#define CRPT_AES_KEY3_KEY_Pos          (0)                                               /*!< CRPT_T::AES_KEY3: KEY Position       */
+#define CRPT_AES_KEY3_KEY_Msk          (0xfffffffful << CRPT_AES_KEY3_KEY_Pos)         /*!< CRPT_T::AES_KEY3: KEY Mask           */
+
+#define CRPT_AES_KEY4_KEY_Pos          (0)                                               /*!< CRPT_T::AES_KEY4: KEY Position       */
+#define CRPT_AES_KEY4_KEY_Msk          (0xfffffffful << CRPT_AES_KEY4_KEY_Pos)         /*!< CRPT_T::AES_KEY4: KEY Mask           */
+
+#define CRPT_AES_KEY5_KEY_Pos          (0)                                               /*!< CRPT_T::AES_KEY5: KEY Position       */
+#define CRPT_AES_KEY5_KEY_Msk          (0xfffffffful << CRPT_AES_KEY5_KEY_Pos)         /*!< CRPT_T::AES_KEY5: KEY Mask           */
+
+#define CRPT_AES_KEY6_KEY_Pos          (0)                                               /*!< CRPT_T::AES_KEY6: KEY Position       */
+#define CRPT_AES_KEY6_KEY_Msk          (0xfffffffful << CRPT_AES_KEY6_KEY_Pos)         /*!< CRPT_T::AES_KEY6: KEY Mask           */
+
+#define CRPT_AES_KEY7_KEY_Pos          (0)                                               /*!< CRPT_T::AES_KEY7: KEY Position       */
+#define CRPT_AES_KEY7_KEY_Msk          (0xfffffffful << CRPT_AES_KEY7_KEY_Pos)         /*!< CRPT_T::AES_KEY7: KEY Mask           */
+
+#define CRPT_AES_IV0_IV_Pos            (0)                                               /*!< CRPT_T::AES_IV0: IV Position         */
+#define CRPT_AES_IV0_IV_Msk            (0xfffffffful << CRPT_AES_IV0_IV_Pos)           /*!< CRPT_T::AES_IV0: IV Mask             */
+
+#define CRPT_AES_IV1_IV_Pos            (0)                                               /*!< CRPT_T::AES_IV1: IV Position         */
+#define CRPT_AES_IV1_IV_Msk            (0xfffffffful << CRPT_AES_IV1_IV_Pos)           /*!< CRPT_T::AES_IV1: IV Mask             */
+
+#define CRPT_AES_IV2_IV_Pos            (0)                                               /*!< CRPT_T::AES_IV2: IV Position         */
+#define CRPT_AES_IV2_IV_Msk            (0xfffffffful << CRPT_AES_IV2_IV_Pos)           /*!< CRPT_T::AES_IV2: IV Mask             */
+
+#define CRPT_AES_IV3_IV_Pos            (0)                                               /*!< CRPT_T::AES_IV3: IV Position         */
+#define CRPT_AES_IV3_IV_Msk            (0xfffffffful << CRPT_AES_IV3_IV_Pos)           /*!< CRPT_T::AES_IV3: IV Mask             */
+
+#define CRPT_AES_SADDR_SADDR_Pos       (0)                                               /*!< CRPT_T::AES_SADDR: SADDR Position    */
+#define CRPT_AES_SADDR_SADDR_Msk       (0xfffffffful << CRPT_AES_SADDR_SADDR_Pos)      /*!< CRPT_T::AES_SADDR: SADDR Mask        */
+
+#define CRPT_AES_DADDR_DADDR_Pos       (0)                                               /*!< CRPT_T::AES_DADDR: DADDR Position    */
+#define CRPT_AES_DADDR_DADDR_Msk       (0xfffffffful << CRPT_AES_DADDR_DADDR_Pos)      /*!< CRPT_T::AES_DADDR: DADDR Mask        */
+
+#define CRPT_AES_CNT_CNT_Pos           (0)                                               /*!< CRPT_T::AES_CNT: CNT Position        */
+#define CRPT_AES_CNT_CNT_Msk           (0xfffffffful << CRPT_AES_CNT_CNT_Pos)          /*!< CRPT_T::AES_CNT: CNT Mask            */
+
+#define CRPT_HMAC_CTL_START_Pos        (0)                                               /*!< CRPT_T::HMAC_CTL: START Position     */
+#define CRPT_HMAC_CTL_START_Msk        (0x1ul << CRPT_HMAC_CTL_START_Pos)              /*!< CRPT_T::HMAC_CTL: START Mask         */
+
+#define CRPT_HMAC_CTL_STOP_Pos         (1)                                               /*!< CRPT_T::HMAC_CTL: STOP Position      */
+#define CRPT_HMAC_CTL_STOP_Msk         (0x1ul << CRPT_HMAC_CTL_STOP_Pos)               /*!< CRPT_T::HMAC_CTL: STOP Mask          */
+
+#define CRPT_HMAC_CTL_DMAFIRST_Pos     (4)                                               /*!< CRPT_T::HMAC_CTL: DMAFIRST Position  */
+#define CRPT_HMAC_CTL_DMAFIRST_Msk     (0x1ul << CRPT_HMAC_CTL_DMAFIRST_Pos)           /*!< CRPT_T::HMAC_CTL: DMAFIRST Mask      */
+
+#define CRPT_HMAC_CTL_DMALAST_Pos      (5)                                               /*!< CRPT_T::HMAC_CTL: DMALAST Position   */
+#define CRPT_HMAC_CTL_DMALAST_Msk      (0x1ul << CRPT_HMAC_CTL_DMALAST_Pos)            /*!< CRPT_T::HMAC_CTL: DMALAST Mask       */
+
+#define CRPT_HMAC_CTL_DMACSCAD_Pos     (6)                                               /*!< CRPT_T::HMAC_CTL: DMACSCAD Position  */
+#define CRPT_HMAC_CTL_DMACSCAD_Msk     (0x1ul << CRPT_HMAC_CTL_DMACSCAD_Pos)           /*!< CRPT_T::HMAC_CTL: DMACSCAD Mask      */
+
+#define CRPT_HMAC_CTL_DMAEN_Pos        (7)                                               /*!< CRPT_T::HMAC_CTL: DMAEN Position     */
+#define CRPT_HMAC_CTL_DMAEN_Msk        (0x1ul << CRPT_HMAC_CTL_DMAEN_Pos)              /*!< CRPT_T::HMAC_CTL: DMAEN Mask         */
+
+#define CRPT_HMAC_CTL_OPMODE_Pos       (8)                                               /*!< CRPT_T::HMAC_CTL: OPMODE Position    */
+#define CRPT_HMAC_CTL_OPMODE_Msk       (0x7ul << CRPT_HMAC_CTL_OPMODE_Pos)             /*!< CRPT_T::HMAC_CTL: OPMODE Mask        */
+
+#define CRPT_HMAC_CTL_HMACEN_Pos       (11)                                              /*!< CRPT_T::HMAC_CTL: HMACEN Position    */
+#define CRPT_HMAC_CTL_HMACEN_Msk       (0x1ul << CRPT_HMAC_CTL_HMACEN_Pos)             /*!< CRPT_T::HMAC_CTL: HMACEN Mask        */
+
+#define CRPT_HMAC_CTL_SM3EN_Pos        (13)                                              /*!< CRPT_T::HMAC_CTL: SM3EN Position     */
+#define CRPT_HMAC_CTL_SM3EN_Msk        (0x1ul << CRPT_HMAC_CTL_SM3EN_Pos)              /*!< CRPT_T::HMAC_CTL: SM3EN Mask         */
+
+#define CRPT_HMAC_CTL_FBIN_Pos         (20)                                              /*!< CRPT_T::HMAC_CTL: FBIN Position      */
+#define CRPT_HMAC_CTL_FBIN_Msk         (0x1ul << CRPT_HMAC_CTL_FBIN_Pos)               /*!< CRPT_T::HMAC_CTL: FBIN Mask          */
+
+#define CRPT_HMAC_CTL_FBOUT_Pos        (21)                                              /*!< CRPT_T::HMAC_CTL: FBOUT Position     */
+#define CRPT_HMAC_CTL_FBOUT_Msk        (0x1ul << CRPT_HMAC_CTL_FBOUT_Pos)              /*!< CRPT_T::HMAC_CTL: FBOUT Mask         */
+
+#define CRPT_HMAC_CTL_OUTSWAP_Pos      (22)                                              /*!< CRPT_T::HMAC_CTL: OUTSWAP Position   */
+#define CRPT_HMAC_CTL_OUTSWAP_Msk      (0x1ul << CRPT_HMAC_CTL_OUTSWAP_Pos)            /*!< CRPT_T::HMAC_CTL: OUTSWAP Mask       */
+
+#define CRPT_HMAC_CTL_INSWAP_Pos       (23)                                              /*!< CRPT_T::HMAC_CTL: INSWAP Position    */
+#define CRPT_HMAC_CTL_INSWAP_Msk       (0x1ul << CRPT_HMAC_CTL_INSWAP_Pos)             /*!< CRPT_T::HMAC_CTL: INSWAP Mask        */
+
+#define CRPT_HMAC_STS_BUSY_Pos         (0)                                               /*!< CRPT_T::HMAC_STS: BUSY Position      */
+#define CRPT_HMAC_STS_BUSY_Msk         (0x1ul << CRPT_HMAC_STS_BUSY_Pos)               /*!< CRPT_T::HMAC_STS: BUSY Mask          */
+
+#define CRPT_HMAC_STS_DMABUSY_Pos      (1)                                               /*!< CRPT_T::HMAC_STS: DMABUSY Position   */
+#define CRPT_HMAC_STS_DMABUSY_Msk      (0x1ul << CRPT_HMAC_STS_DMABUSY_Pos)            /*!< CRPT_T::HMAC_STS: DMABUSY Mask       */
+
+#define CRPT_HMAC_STS_DMAERR_Pos       (8)                                               /*!< CRPT_T::HMAC_STS: DMAERR Position    */
+#define CRPT_HMAC_STS_DMAERR_Msk       (0x1ul << CRPT_HMAC_STS_DMAERR_Pos)             /*!< CRPT_T::HMAC_STS: DMAERR Mask        */
+
+#define CRPT_HMAC_STS_KSERR_Pos        (9)                                               /*!< CRPT_T::HMAC_STS: KSERR Position     */
+#define CRPT_HMAC_STS_KSERR_Msk        (0x1ul << CRPT_HMAC_STS_KSERR_Pos)              /*!< CRPT_T::HMAC_STS: KSERR Mask         */
+
+#define CRPT_HMAC_STS_DATINREQ_Pos     (16)                                              /*!< CRPT_T::HMAC_STS: DATINREQ Position  */
+#define CRPT_HMAC_STS_DATINREQ_Msk     (0x1ul << CRPT_HMAC_STS_DATINREQ_Pos)           /*!< CRPT_T::HMAC_STS: DATINREQ Mask      */
+
+#define CRPT_HMAC_DGST0_DGST_Pos       (0)                                               /*!< CRPT_T::HMAC_DGST0: DGST Position    */
+#define CRPT_HMAC_DGST0_DGST_Msk       (0xfffffffful << CRPT_HMAC_DGST0_DGST_Pos)      /*!< CRPT_T::HMAC_DGST0: DGST Mask        */
+
+#define CRPT_HMAC_DGST1_DGST_Pos       (0)                                               /*!< CRPT_T::HMAC_DGST1: DGST Position    */
+#define CRPT_HMAC_DGST1_DGST_Msk       (0xfffffffful << CRPT_HMAC_DGST1_DGST_Pos)      /*!< CRPT_T::HMAC_DGST1: DGST Mask        */
+
+#define CRPT_HMAC_DGST2_DGST_Pos       (0)                                               /*!< CRPT_T::HMAC_DGST2: DGST Position    */
+#define CRPT_HMAC_DGST2_DGST_Msk       (0xfffffffful << CRPT_HMAC_DGST2_DGST_Pos)      /*!< CRPT_T::HMAC_DGST2: DGST Mask        */
+
+#define CRPT_HMAC_DGST3_DGST_Pos       (0)                                               /*!< CRPT_T::HMAC_DGST3: DGST Position    */
+#define CRPT_HMAC_DGST3_DGST_Msk       (0xfffffffful << CRPT_HMAC_DGST3_DGST_Pos)      /*!< CRPT_T::HMAC_DGST3: DGST Mask        */
+
+#define CRPT_HMAC_DGST4_DGST_Pos       (0)                                               /*!< CRPT_T::HMAC_DGST4: DGST Position    */
+#define CRPT_HMAC_DGST4_DGST_Msk       (0xfffffffful << CRPT_HMAC_DGST4_DGST_Pos)      /*!< CRPT_T::HMAC_DGST4: DGST Mask        */
+
+#define CRPT_HMAC_DGST5_DGST_Pos       (0)                                               /*!< CRPT_T::HMAC_DGST5: DGST Position    */
+#define CRPT_HMAC_DGST5_DGST_Msk       (0xfffffffful << CRPT_HMAC_DGST5_DGST_Pos)      /*!< CRPT_T::HMAC_DGST5: DGST Mask        */
+
+#define CRPT_HMAC_DGST6_DGST_Pos       (0)                                               /*!< CRPT_T::HMAC_DGST6: DGST Position    */
+#define CRPT_HMAC_DGST6_DGST_Msk       (0xfffffffful << CRPT_HMAC_DGST6_DGST_Pos)      /*!< CRPT_T::HMAC_DGST6: DGST Mask        */
+
+#define CRPT_HMAC_DGST7_DGST_Pos       (0)                                               /*!< CRPT_T::HMAC_DGST7: DGST Position    */
+#define CRPT_HMAC_DGST7_DGST_Msk       (0xfffffffful << CRPT_HMAC_DGST7_DGST_Pos)      /*!< CRPT_T::HMAC_DGST7: DGST Mask        */
+
+#define CRPT_HMAC_DGST8_DGST_Pos       (0)                                               /*!< CRPT_T::HMAC_DGST8: DGST Position    */
+#define CRPT_HMAC_DGST8_DGST_Msk       (0xfffffffful << CRPT_HMAC_DGST8_DGST_Pos)      /*!< CRPT_T::HMAC_DGST8: DGST Mask        */
+
+#define CRPT_HMAC_DGST9_DGST_Pos       (0)                                               /*!< CRPT_T::HMAC_DGST9: DGST Position    */
+#define CRPT_HMAC_DGST9_DGST_Msk       (0xfffffffful << CRPT_HMAC_DGST9_DGST_Pos)      /*!< CRPT_T::HMAC_DGST9: DGST Mask        */
+
+#define CRPT_HMAC_DGST10_DGST_Pos      (0)                                               /*!< CRPT_T::HMAC_DGST10: DGST Position   */
+#define CRPT_HMAC_DGST10_DGST_Msk      (0xfffffffful << CRPT_HMAC_DGST10_DGST_Pos)     /*!< CRPT_T::HMAC_DGST10: DGST Mask       */
+
+#define CRPT_HMAC_DGST11_DGST_Pos      (0)                                               /*!< CRPT_T::HMAC_DGST11: DGST Position   */
+#define CRPT_HMAC_DGST11_DGST_Msk      (0xfffffffful << CRPT_HMAC_DGST11_DGST_Pos)     /*!< CRPT_T::HMAC_DGST11: DGST Mask       */
+
+#define CRPT_HMAC_DGST12_DGST_Pos      (0)                                               /*!< CRPT_T::HMAC_DGST12: DGST Position   */
+#define CRPT_HMAC_DGST12_DGST_Msk      (0xfffffffful << CRPT_HMAC_DGST12_DGST_Pos)     /*!< CRPT_T::HMAC_DGST12: DGST Mask       */
+
+#define CRPT_HMAC_DGST13_DGST_Pos      (0)                                               /*!< CRPT_T::HMAC_DGST13: DGST Position   */
+#define CRPT_HMAC_DGST13_DGST_Msk      (0xfffffffful << CRPT_HMAC_DGST13_DGST_Pos)     /*!< CRPT_T::HMAC_DGST13: DGST Mask       */
+
+#define CRPT_HMAC_DGST14_DGST_Pos      (0)                                               /*!< CRPT_T::HMAC_DGST14: DGST Position   */
+#define CRPT_HMAC_DGST14_DGST_Msk      (0xfffffffful << CRPT_HMAC_DGST14_DGST_Pos)     /*!< CRPT_T::HMAC_DGST14: DGST Mask       */
+
+#define CRPT_HMAC_DGST15_DGST_Pos      (0)                                               /*!< CRPT_T::HMAC_DGST15: DGST Position   */
+#define CRPT_HMAC_DGST15_DGST_Msk      (0xfffffffful << CRPT_HMAC_DGST15_DGST_Pos)     /*!< CRPT_T::HMAC_DGST15: DGST Mask       */
+
+#define CRPT_HMAC_KEYCNT_KEYCNT_Pos    (0)                                               /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Position */
+#define CRPT_HMAC_KEYCNT_KEYCNT_Msk    (0xfffffffful << CRPT_HMAC_KEYCNT_KEYCNT_Pos)   /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Mask     */
+
+#define CRPT_HMAC_SADDR_SADDR_Pos      (0)                                               /*!< CRPT_T::HMAC_SADDR: SADDR Position   */
+#define CRPT_HMAC_SADDR_SADDR_Msk      (0xfffffffful << CRPT_HMAC_SADDR_SADDR_Pos)     /*!< CRPT_T::HMAC_SADDR: SADDR Mask       */
+
+#define CRPT_HMAC_DMACNT_DMACNT_Pos    (0)                                               /*!< CRPT_T::HMAC_DMACNT: DMACNT Position */
+#define CRPT_HMAC_DMACNT_DMACNT_Msk    (0xfffffffful << CRPT_HMAC_DMACNT_DMACNT_Pos)   /*!< CRPT_T::HMAC_DMACNT: DMACNT Mask     */
+
+#define CRPT_HMAC_DATIN_DATIN_Pos      (0)                                               /*!< CRPT_T::HMAC_DATIN: DATIN Position   */
+#define CRPT_HMAC_DATIN_DATIN_Msk      (0xfffffffful << CRPT_HMAC_DATIN_DATIN_Pos)     /*!< CRPT_T::HMAC_DATIN: DATIN Mask       */
+
+#define CRPT_HMAC_FDBCK0_FDBCK_Pos     (0)                                               /*!< CRPT_T::HMAC_FDBCK0: FDBCK Position  */
+#define CRPT_HMAC_FDBCK0_FDBCK_Msk     (0xfffffffful << CRPT_HMAC_FDBCK0_FDBCK_Pos)    /*!< CRPT_T::HMAC_FDBCK0: FDBCK Mask      */
+
+#define CRPT_HMAC_FDBCK1_FDBCK_Pos     (0)                                               /*!< CRPT_T::HMAC_FDBCK1: FDBCK Position  */
+#define CRPT_HMAC_FDBCK1_FDBCK_Msk     (0xfffffffful << CRPT_HMAC_FDBCK1_FDBCK_Pos)    /*!< CRPT_T::HMAC_FDBCK1: FDBCK Mask      */
+
+#define CRPT_HMAC_FDBCK2_FDBCK_Pos     (0)                                               /*!< CRPT_T::HMAC_FDBCK2: FDBCK Position  */
+#define CRPT_HMAC_FDBCK2_FDBCK_Msk     (0xfffffffful << CRPT_HMAC_FDBCK2_FDBCK_Pos)    /*!< CRPT_T::HMAC_FDBCK2: FDBCK Mask      */
+
+#define CRPT_HMAC_FDBCK3_FDBCK_Pos     (0)                                               /*!< CRPT_T::HMAC_FDBCK3: FDBCK Position  */
+#define CRPT_HMAC_FDBCK3_FDBCK_Msk     (0xfffffffful << CRPT_HMAC_FDBCK3_FDBCK_Pos)    /*!< CRPT_T::HMAC_FDBCK3: FDBCK Mask      */
+
+#define CRPT_HMAC_FDBCK4_FDBCK_Pos     (0)                                               /*!< CRPT_T::HMAC_FDBCK4: FDBCK Position  */
+#define CRPT_HMAC_FDBCK4_FDBCK_Msk     (0xfffffffful << CRPT_HMAC_FDBCK4_FDBCK_Pos)    /*!< CRPT_T::HMAC_FDBCK4: FDBCK Mask      */
+
+#define CRPT_HMAC_FDBCK5_FDBCK_Pos     (0)                                               /*!< CRPT_T::HMAC_FDBCK5: FDBCK Position  */
+#define CRPT_HMAC_FDBCK5_FDBCK_Msk     (0xfffffffful << CRPT_HMAC_FDBCK5_FDBCK_Pos)    /*!< CRPT_T::HMAC_FDBCK5: FDBCK Mask      */
+
+#define CRPT_HMAC_FDBCK6_FDBCK_Pos     (0)                                               /*!< CRPT_T::HMAC_FDBCK6: FDBCK Position  */
+#define CRPT_HMAC_FDBCK6_FDBCK_Msk     (0xfffffffful << CRPT_HMAC_FDBCK6_FDBCK_Pos)    /*!< CRPT_T::HMAC_FDBCK6: FDBCK Mask      */
+
+#define CRPT_HMAC_FDBCK7_FDBCK_Pos     (0)                                               /*!< CRPT_T::HMAC_FDBCK7: FDBCK Position  */
+#define CRPT_HMAC_FDBCK7_FDBCK_Msk     (0xfffffffful << CRPT_HMAC_FDBCK7_FDBCK_Pos)    /*!< CRPT_T::HMAC_FDBCK7: FDBCK Mask      */
+
+#define CRPT_HMAC_FDBCK8_FDBCK_Pos     (0)                                               /*!< CRPT_T::HMAC_FDBCK8: FDBCK Position  */
+#define CRPT_HMAC_FDBCK8_FDBCK_Msk     (0xfffffffful << CRPT_HMAC_FDBCK8_FDBCK_Pos)    /*!< CRPT_T::HMAC_FDBCK8: FDBCK Mask      */
+
+#define CRPT_HMAC_FDBCK9_FDBCK_Pos     (0)                                               /*!< CRPT_T::HMAC_FDBCK9: FDBCK Position  */
+#define CRPT_HMAC_FDBCK9_FDBCK_Msk     (0xfffffffful << CRPT_HMAC_FDBCK9_FDBCK_Pos)    /*!< CRPT_T::HMAC_FDBCK9: FDBCK Mask      */
+
+#define CRPT_HMAC_FDBCK10_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK10: FDBCK Position */
+#define CRPT_HMAC_FDBCK10_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK10_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK10: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK11_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK11: FDBCK Position */
+#define CRPT_HMAC_FDBCK11_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK11_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK11: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK12_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK12: FDBCK Position */
+#define CRPT_HMAC_FDBCK12_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK12_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK12: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK13_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK13: FDBCK Position */
+#define CRPT_HMAC_FDBCK13_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK13_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK13: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK14_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK14: FDBCK Position */
+#define CRPT_HMAC_FDBCK14_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK14_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK14: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK15_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK15: FDBCK Position */
+#define CRPT_HMAC_FDBCK15_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK15_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK15: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK16_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK16: FDBCK Position */
+#define CRPT_HMAC_FDBCK16_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK16_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK16: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK17_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK17: FDBCK Position */
+#define CRPT_HMAC_FDBCK17_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK17_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK17: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK18_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK18: FDBCK Position */
+#define CRPT_HMAC_FDBCK18_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK18_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK18: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK19_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK19: FDBCK Position */
+#define CRPT_HMAC_FDBCK19_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK19_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK19: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK20_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK20: FDBCK Position */
+#define CRPT_HMAC_FDBCK20_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK20_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK20: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK21_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK21: FDBCK Position */
+#define CRPT_HMAC_FDBCK21_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK21_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK21: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK22_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK22: FDBCK Position */
+#define CRPT_HMAC_FDBCK22_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK22_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK22: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK23_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK23: FDBCK Position */
+#define CRPT_HMAC_FDBCK23_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK23_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK23: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK24_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK24: FDBCK Position */
+#define CRPT_HMAC_FDBCK24_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK24_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK24: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK25_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK25: FDBCK Position */
+#define CRPT_HMAC_FDBCK25_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK25_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK25: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK26_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK26: FDBCK Position */
+#define CRPT_HMAC_FDBCK26_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK26_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK26: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK27_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK27: FDBCK Position */
+#define CRPT_HMAC_FDBCK27_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK27_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK27: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK28_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK28: FDBCK Position */
+#define CRPT_HMAC_FDBCK28_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK28_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK28: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK29_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK29: FDBCK Position */
+#define CRPT_HMAC_FDBCK29_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK29_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK29: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK30_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK30: FDBCK Position */
+#define CRPT_HMAC_FDBCK30_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK30_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK30: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK31_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK31: FDBCK Position */
+#define CRPT_HMAC_FDBCK31_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK31_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK31: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK32_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK32: FDBCK Position */
+#define CRPT_HMAC_FDBCK32_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK32_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK32: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK33_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK33: FDBCK Position */
+#define CRPT_HMAC_FDBCK33_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK33_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK33: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK34_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK34: FDBCK Position */
+#define CRPT_HMAC_FDBCK34_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK34_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK34: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK35_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK35: FDBCK Position */
+#define CRPT_HMAC_FDBCK35_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK35_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK35: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK36_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK36: FDBCK Position */
+#define CRPT_HMAC_FDBCK36_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK36_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK36: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK37_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK37: FDBCK Position */
+#define CRPT_HMAC_FDBCK37_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK37_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK37: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK38_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK38: FDBCK Position */
+#define CRPT_HMAC_FDBCK38_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK38_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK38: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK39_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK39: FDBCK Position */
+#define CRPT_HMAC_FDBCK39_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK39_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK39: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK40_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK40: FDBCK Position */
+#define CRPT_HMAC_FDBCK40_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK40_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK40: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK41_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK41: FDBCK Position */
+#define CRPT_HMAC_FDBCK41_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK41_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK41: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK42_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK42: FDBCK Position */
+#define CRPT_HMAC_FDBCK42_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK42_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK42: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK43_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK43: FDBCK Position */
+#define CRPT_HMAC_FDBCK43_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK43_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK43: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK44_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK44: FDBCK Position */
+#define CRPT_HMAC_FDBCK44_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK44_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK44: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK45_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK45: FDBCK Position */
+#define CRPT_HMAC_FDBCK45_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK45_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK45: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK46_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK46: FDBCK Position */
+#define CRPT_HMAC_FDBCK46_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK46_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK46: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK47_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK47: FDBCK Position */
+#define CRPT_HMAC_FDBCK47_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK47_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK47: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK48_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK48: FDBCK Position */
+#define CRPT_HMAC_FDBCK48_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK48_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK48: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK49_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK49: FDBCK Position */
+#define CRPT_HMAC_FDBCK49_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK49_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK49: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK50_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK50: FDBCK Position */
+#define CRPT_HMAC_FDBCK50_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK50_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK50: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK51_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK51: FDBCK Position */
+#define CRPT_HMAC_FDBCK51_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK51_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK51: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK52_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK52: FDBCK Position */
+#define CRPT_HMAC_FDBCK52_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK52_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK52: FDBCK Mask     */
+
+#define CRPT_HMAC_FDBCK53_FDBCK_Pos    (0)                                               /*!< CRPT_T::HMAC_FDBCK53: FDBCK Position */
+#define CRPT_HMAC_FDBCK53_FDBCK_Msk    (0xfffffffful << CRPT_HMAC_FDBCK53_FDBCK_Pos)   /*!< CRPT_T::HMAC_FDBCK53: FDBCK Mask     */
+
+#define CRPT_HMAC_FBADDR_FBADDR_Pos    (0)                                               /*!< CRPT_T::HMAC_FBADDR: FBADDR Position */
+#define CRPT_HMAC_FBADDR_FBADDR_Msk    (0xfffffffful << CRPT_HMAC_FBADDR_FBADDR_Pos)   /*!< CRPT_T::HMAC_FBADDR: FBADDR Mask     */
+
+#define CRPT_ECC_CTL_START_Pos         (0)                                               /*!< CRPT_T::ECC_CTL: START Position      */
+#define CRPT_ECC_CTL_START_Msk         (0x1ul << CRPT_ECC_CTL_START_Pos)               /*!< CRPT_T::ECC_CTL: START Mask          */
+
+#define CRPT_ECC_CTL_STOP_Pos          (1)                                               /*!< CRPT_T::ECC_CTL: STOP Position       */
+#define CRPT_ECC_CTL_STOP_Msk          (0x1ul << CRPT_ECC_CTL_STOP_Pos)                /*!< CRPT_T::ECC_CTL: STOP Mask           */
+
+#define CRPT_ECC_CTL_PFA2C_Pos         (3)                                               /*!< CRPT_T::ECC_CTL: PFA2C Position      */
+#define CRPT_ECC_CTL_PFA2C_Msk         (0x1ul << CRPT_ECC_CTL_PFA2C_Pos)               /*!< CRPT_T::ECC_CTL: PFA2C Mask          */
+
+#define CRPT_ECC_CTL_ECDSAS_Pos        (4)                                               /*!< CRPT_T::ECC_CTL: ECDSAS Position     */
+#define CRPT_ECC_CTL_ECDSAS_Msk        (0x1ul << CRPT_ECC_CTL_ECDSAS_Pos)              /*!< CRPT_T::ECC_CTL: ECDSAS Mask         */
+
+#define CRPT_ECC_CTL_ECDSAR_Pos        (5)                                               /*!< CRPT_T::ECC_CTL: ECDSAR Position     */
+#define CRPT_ECC_CTL_ECDSAR_Msk        (0x1ul << CRPT_ECC_CTL_ECDSAR_Pos)              /*!< CRPT_T::ECC_CTL: ECDSAR Mask         */
+
+#define CRPT_ECC_CTL_DMAEN_Pos         (7)                                               /*!< CRPT_T::ECC_CTL: DMAEN Position      */
+#define CRPT_ECC_CTL_DMAEN_Msk         (0x1ul << CRPT_ECC_CTL_DMAEN_Pos)               /*!< CRPT_T::ECC_CTL: DMAEN Mask          */
+
+#define CRPT_ECC_CTL_FSEL_Pos          (8)                                               /*!< CRPT_T::ECC_CTL: FSEL Position       */
+#define CRPT_ECC_CTL_FSEL_Msk          (0x1ul << CRPT_ECC_CTL_FSEL_Pos)                /*!< CRPT_T::ECC_CTL: FSEL Mask           */
+
+#define CRPT_ECC_CTL_ECCOP_Pos         (9)                                               /*!< CRPT_T::ECC_CTL: ECCOP Position      */
+#define CRPT_ECC_CTL_ECCOP_Msk         (0x3ul << CRPT_ECC_CTL_ECCOP_Pos)               /*!< CRPT_T::ECC_CTL: ECCOP Mask          */
+
+#define CRPT_ECC_CTL_MODOP_Pos         (11)                                              /*!< CRPT_T::ECC_CTL: MODOP Position      */
+#define CRPT_ECC_CTL_MODOP_Msk         (0x3ul << CRPT_ECC_CTL_MODOP_Pos)               /*!< CRPT_T::ECC_CTL: MODOP Mask          */
+
+#define CRPT_ECC_CTL_CSEL_Pos          (13)                                              /*!< CRPT_T::ECC_CTL: CSEL Position       */
+#define CRPT_ECC_CTL_CSEL_Msk          (0x1ul << CRPT_ECC_CTL_CSEL_Pos)                /*!< CRPT_T::ECC_CTL: CSEL Mask           */
+
+#define CRPT_ECC_CTL_SCAP_Pos          (14)                                              /*!< CRPT_T::ECC_CTL: SCAP Position       */
+#define CRPT_ECC_CTL_SCAP_Msk          (0x1ul << CRPT_ECC_CTL_SCAP_Pos)                /*!< CRPT_T::ECC_CTL: SCAP Mask           */
+
+#define CRPT_ECC_CTL_SBM_Pos           (15)                                              /*!< CRPT_T::ECC_CTL: SBM Position        */
+#define CRPT_ECC_CTL_SBM_Msk           (0x1ul << CRPT_ECC_CTL_SBM_Pos)                 /*!< CRPT_T::ECC_CTL: SBM Mask            */
+
+#define CRPT_ECC_CTL_LDP1_Pos          (16)                                              /*!< CRPT_T::ECC_CTL: LDP1 Position       */
+#define CRPT_ECC_CTL_LDP1_Msk          (0x1ul << CRPT_ECC_CTL_LDP1_Pos)                /*!< CRPT_T::ECC_CTL: LDP1 Mask           */
+
+#define CRPT_ECC_CTL_LDP2_Pos          (17)                                              /*!< CRPT_T::ECC_CTL: LDP2 Position       */
+#define CRPT_ECC_CTL_LDP2_Msk          (0x1ul << CRPT_ECC_CTL_LDP2_Pos)                /*!< CRPT_T::ECC_CTL: LDP2 Mask           */
+
+#define CRPT_ECC_CTL_LDA_Pos           (18)                                              /*!< CRPT_T::ECC_CTL: LDA Position        */
+#define CRPT_ECC_CTL_LDA_Msk           (0x1ul << CRPT_ECC_CTL_LDA_Pos)                 /*!< CRPT_T::ECC_CTL: LDA Mask            */
+
+#define CRPT_ECC_CTL_LDB_Pos           (19)                                              /*!< CRPT_T::ECC_CTL: LDB Position        */
+#define CRPT_ECC_CTL_LDB_Msk           (0x1ul << CRPT_ECC_CTL_LDB_Pos)                 /*!< CRPT_T::ECC_CTL: LDB Mask            */
+
+#define CRPT_ECC_CTL_LDN_Pos           (20)                                              /*!< CRPT_T::ECC_CTL: LDN Position        */
+#define CRPT_ECC_CTL_LDN_Msk           (0x1ul << CRPT_ECC_CTL_LDN_Pos)                 /*!< CRPT_T::ECC_CTL: LDN Mask            */
+
+#define CRPT_ECC_CTL_LDK_Pos           (21)                                              /*!< CRPT_T::ECC_CTL: LDK Position        */
+#define CRPT_ECC_CTL_LDK_Msk           (0x1ul << CRPT_ECC_CTL_LDK_Pos)                 /*!< CRPT_T::ECC_CTL: LDK Mask            */
+
+#define CRPT_ECC_CTL_CURVEM_Pos        (22)                                              /*!< CRPT_T::ECC_CTL: CURVEM Position     */
+#define CRPT_ECC_CTL_CURVEM_Msk        (0x3fful << CRPT_ECC_CTL_CURVEM_Pos)            /*!< CRPT_T::ECC_CTL: CURVEM Mask         */
+
+#define CRPT_ECC_STS_BUSY_Pos          (0)                                               /*!< CRPT_T::ECC_STS: BUSY Position       */
+#define CRPT_ECC_STS_BUSY_Msk          (0x1ul << CRPT_ECC_STS_BUSY_Pos)                /*!< CRPT_T::ECC_STS: BUSY Mask           */
+
+#define CRPT_ECC_STS_DMABUSY_Pos       (1)                                               /*!< CRPT_T::ECC_STS: DMABUSY Position    */
+#define CRPT_ECC_STS_DMABUSY_Msk       (0x1ul << CRPT_ECC_STS_DMABUSY_Pos)             /*!< CRPT_T::ECC_STS: DMABUSY Mask        */
+
+#define CRPT_ECC_STS_BUSERR_Pos        (16)                                              /*!< CRPT_T::ECC_STS: BUSERR Position     */
+#define CRPT_ECC_STS_BUSERR_Msk        (0x1ul << CRPT_ECC_STS_BUSERR_Pos)              /*!< CRPT_T::ECC_STS: BUSERR Mask         */
+
+#define CRPT_ECC_STS_KSERR_Pos         (17)                                              /*!< CRPT_T::ECC_STS: KSERR Position      */
+#define CRPT_ECC_STS_KSERR_Msk         (0x1ul << CRPT_ECC_STS_KSERR_Pos)               /*!< CRPT_T::ECC_STS: KSERR Mask          */
+
+#define CRPT_ECC_X1_Pos     (0)                                               /*!< CRPT_T::ECC_X1: POINTX Position  */
+#define CRPT_ECC_X1_Msk     (0xfffffffful << CRPT_ECC_X1_Pos)    /*!< CRPT_T::ECC_X1: POINTX Mask      */
+
+
+#define CRPT_ECC_X2_Pos     (0)                                               /*!< CRPT_T::ECC_X2: POINTX2 Position  */
+#define CRPT_ECC_X2TX_Msk     (0xfffffffful << CRPT_ECC_X2_Pos)    /*!< CRPT_T::ECC_X2: POINTX2 Mask      */
+
+
+#define CRPT_ECC_Y2_Pos     (0)                                               /*!< CRPT_T::ECC_Y2: POINTY2 Position  */
+#define CRPT_ECC_Y2_Msk     (0xfffffffful << CRPT_ECC_Y2_Pos)    /*!< CRPT_T::ECC_Y2: POINTY2 Mask      */
+
+#define CRPT_ECC_A_Pos       (0)                                               /*!< CRPT_T::ECC_A: CURVEA Position    */
+#define CRPT_ECC_A_Msk       (0xfffffffful << CRPT_ECC_A_Pos)      /*!< CRPT_T::ECC_A: CURVEA Mask        */
+
+#define CRPT_ECC_B_Pos       (0)                                               /*!< CRPT_T::ECC_B: CURVEB Position    */
+#define CRPT_ECC_B_Msk       (0xfffffffful << CRPT_ECC_B_Pos)      /*!< CRPT_T::ECC_B: CURVEB Mask        */
+
+#define CRPT_ECC_N_Pos      (0)                                               /*!< CRPT_T::ECC_N: SCALARK Position   */
+#define CRPT_ECC_N_Msk      (0xfffffffful << CRPT_ECC_N_Pos)     /*!< CRPT_T::ECC_N: SCALARK Mask       */
+
+#define CRPT_ECC_DADDR_DADDR_Pos       (0)                                               /*!< CRPT_T::ECC_DADDR: DADDR Position    */
+#define CRPT_ECC_DADDR_DADDR_Msk       (0xfffffffful << CRPT_ECC_DADDR_DADDR_Pos)      /*!< CRPT_T::ECC_DADDR: DADDR Mask        */
+
+#define CRPT_ECC_STARTREG_STARTREG_Pos (0)                                               /*!< CRPT_T::ECC_STARTREG: STARTREG Position*/
+#define CRPT_ECC_STARTREG_STARTREG_Msk (0xfffffffful << CRPT_ECC_STARTREG_STARTREG_Pos) /*!< CRPT_T::ECC_STARTREG: STARTREG Mask  */
+
+#define CRPT_ECC_WORDCNT_WORDCNT_Pos   (0)                                               /*!< CRPT_T::ECC_WORDCNT: WORDCNT Position*/
+#define CRPT_ECC_WORDCNT_WORDCNT_Msk   (0xfffffffful << CRPT_ECC_WORDCNT_WORDCNT_Pos)  /*!< CRPT_T::ECC_WORDCNT: WORDCNT Mask    */
+
+#define CRPT_RSA_CTL_START_Pos         (0)                                               /*!< CRPT_T::RSA_CTL: START Position      */
+#define CRPT_RSA_CTL_START_Msk         (0x1ul << CRPT_RSA_CTL_START_Pos)               /*!< CRPT_T::RSA_CTL: START Mask          */
+
+#define CRPT_RSA_CTL_STOP_Pos          (1)                                               /*!< CRPT_T::RSA_CTL: STOP Position       */
+#define CRPT_RSA_CTL_STOP_Msk          (0x1ul << CRPT_RSA_CTL_STOP_Pos)                /*!< CRPT_T::RSA_CTL: STOP Mask           */
+
+#define CRPT_RSA_CTL_CRT_Pos           (2)                                               /*!< CRPT_T::RSA_CTL: CRT Position        */
+#define CRPT_RSA_CTL_CRT_Msk           (0x1ul << CRPT_RSA_CTL_CRT_Pos)                 /*!< CRPT_T::RSA_CTL: CRT Mask            */
+
+#define CRPT_RSA_CTL_CRTBYP_Pos        (3)                                               /*!< CRPT_T::RSA_CTL: CRTBYP Position     */
+#define CRPT_RSA_CTL_CRTBYP_Msk        (0x1ul << CRPT_RSA_CTL_CRTBYP_Pos)              /*!< CRPT_T::RSA_CTL: CRTBYP Mask         */
+
+#define CRPT_RSA_CTL_KEYLENG_Pos       (4)                                               /*!< CRPT_T::RSA_CTL: KEYLENG Position    */
+#define CRPT_RSA_CTL_KEYLENG_Msk       (0x3ul << CRPT_RSA_CTL_KEYLENG_Pos)             /*!< CRPT_T::RSA_CTL: KEYLENG Mask        */
+
+#define CRPT_RSA_CTL_SCAP_Pos          (8)                                               /*!< CRPT_T::RSA_CTL: SCAP Position       */
+#define CRPT_RSA_CTL_SCAP_Msk          (0x1ul << CRPT_RSA_CTL_SCAP_Pos)                /*!< CRPT_T::RSA_CTL: SCAP Mask           */
+
+#define CRPT_RSA_STS_BUSY_Pos          (0)                                               /*!< CRPT_T::RSA_STS: BUSY Position       */
+#define CRPT_RSA_STS_BUSY_Msk          (0x1ul << CRPT_RSA_STS_BUSY_Pos)                /*!< CRPT_T::RSA_STS: BUSY Mask           */
+
+#define CRPT_RSA_STS_DMABUSY_Pos       (1)                                               /*!< CRPT_T::RSA_STS: DMABUSY Position    */
+#define CRPT_RSA_STS_DMABUSY_Msk       (0x1ul << CRPT_RSA_STS_DMABUSY_Pos)             /*!< CRPT_T::RSA_STS: DMABUSY Mask        */
+
+#define CRPT_RSA_STS_BUSERR_Pos        (16)                                              /*!< CRPT_T::RSA_STS: BUSERR Position     */
+#define CRPT_RSA_STS_BUSERR_Msk        (0x1ul << CRPT_RSA_STS_BUSERR_Pos)              /*!< CRPT_T::RSA_STS: BUSERR Mask         */
+
+#define CRPT_RSA_STS_CTLERR_Pos        (17)                                              /*!< CRPT_T::RSA_STS: CTLERR Position     */
+#define CRPT_RSA_STS_CTLERR_Msk        (0x1ul << CRPT_RSA_STS_CTLERR_Pos)              /*!< CRPT_T::RSA_STS: CTLERR Mask         */
+
+#define CRPT_RSA_STS_KSERR_Pos         (18)                                              /*!< CRPT_T::RSA_STS: KSERR Position      */
+#define CRPT_RSA_STS_KSERR_Msk         (0x1ul << CRPT_RSA_STS_KSERR_Pos)               /*!< CRPT_T::RSA_STS: KSERR Mask          */
+
+#define CRPT_RSA_SADDR_Pos     (0)                                               /*!< CRPT_T::RSA_SADDR: SADDR Position  */
+#define CRPT_RSA_SADDR_Msk     (0xfffffffful << CRPT_RSA_SADDR_Pos)    /*!< CRPT_T::RSA_SADDR: SADDR Mask      */
+
+#define CRPT_RSA_DADDR_Pos       (0)                                               /*!< CRPT_T::RSA_DADDR: DADDR Position    */
+#define CRPT_RSA_DADDR_Msk       (0xfffffffful << CRPT_RSA_DADDR_Pos)      /*!< CRPT_T::RSA_DADDR: DADDR Mask        */
+
+#define CRPT_RSA_MADDR_Pos     (0)                                               /*!< CRPT_T::RSA_MADDR: MADDR Position  */
+#define CRPT_RSA_MADDR_Msk     (0xfffffffful << CRPT_RSA_MADDR_Pos)    /*!< CRPT_T::RSA_MADDR: MADDR Mask      */
+
+#define CRPT_PRNG_KSCTL_NUM_Pos        (0)                                               /*!< CRPT_T::PRNG_KSCTL: NUM Position     */
+#define CRPT_PRNG_KSCTL_NUM_Msk        (0x1ful << CRPT_PRNG_KSCTL_NUM_Pos)             /*!< CRPT_T::PRNG_KSCTL: NUM Mask         */
+
+#define CRPT_PRNG_KSCTL_TRUST_Pos      (16)                                              /*!< CRPT_T::PRNG_KSCTL: TRUST Position   */
+#define CRPT_PRNG_KSCTL_TRUST_Msk      (0x1ul << CRPT_PRNG_KSCTL_TRUST_Pos)            /*!< CRPT_T::PRNG_KSCTL: TRUST Mask       */
+
+#define CRPT_PRNG_KSCTL_PRIV_Pos       (18)                                              /*!< CRPT_T::PRNG_KSCTL: PRIV Position    */
+#define CRPT_PRNG_KSCTL_PRIV_Msk       (0x1ul << CRPT_PRNG_KSCTL_PRIV_Pos)             /*!< CRPT_T::PRNG_KSCTL: PRIV Mask        */
+
+#define CRPT_PRNG_KSCTL_ECDH_Pos       (19)                                              /*!< CRPT_T::PRNG_KSCTL: ECDH Position    */
+#define CRPT_PRNG_KSCTL_ECDH_Msk       (0x1ul << CRPT_PRNG_KSCTL_ECDH_Pos)             /*!< CRPT_T::PRNG_KSCTL: ECDH Mask        */
+
+#define CRPT_PRNG_KSCTL_ECDSA_Pos      (20)                                              /*!< CRPT_T::PRNG_KSCTL: ECDSA Position   */
+#define CRPT_PRNG_KSCTL_ECDSA_Msk      (0x1ul << CRPT_PRNG_KSCTL_ECDSA_Pos)            /*!< CRPT_T::PRNG_KSCTL: ECDSA Mask       */
+
+#define CRPT_PRNG_KSCTL_WDST_Pos       (21)                                              /*!< CRPT_T::PRNG_KSCTL: WDST Position    */
+#define CRPT_PRNG_KSCTL_WDST_Msk       (0x1ul << CRPT_PRNG_KSCTL_WDST_Pos)             /*!< CRPT_T::PRNG_KSCTL: WDST Mask        */
+
+#define CRPT_PRNG_KSCTL_WSDST_Pos      (22)                                              /*!< CRPT_T::PRNG_KSCTL: WSDST Position   */
+#define CRPT_PRNG_KSCTL_WSDST_Msk      (0x3ul << CRPT_PRNG_KSCTL_WSDST_Pos)            /*!< CRPT_T::PRNG_KSCTL: WSDST Mask       */
+
+#define CRPT_PRNG_KSCTL_OWNER_Pos      (24)                                              /*!< CRPT_T::PRNG_KSCTL: OWNER Position   */
+#define CRPT_PRNG_KSCTL_OWNER_Msk      (0x7ul << CRPT_PRNG_KSCTL_OWNER_Pos)            /*!< CRPT_T::PRNG_KSCTL: OWNER Mask       */
+
+#define CRPT_PRNG_KSSTS_NUM_Pos        (0)                                               /*!< CRPT_T::PRNG_KSSTS: NUM Position     */
+#define CRPT_PRNG_KSSTS_NUM_Msk        (0x1ful << CRPT_PRNG_KSSTS_NUM_Pos)             /*!< CRPT_T::PRNG_KSSTS: NUM Mask         */
+
+#define CRPT_PRNG_KSSTS_KCTLERR_Pos    (16)                                              /*!< CRPT_T::PRNG_KSSTS: KCTLERR Position */
+#define CRPT_PRNG_KSSTS_KCTLERR_Msk    (0x1ul << CRPT_PRNG_KSSTS_KCTLERR_Pos)          /*!< CRPT_T::PRNG_KSSTS: KCTLERR Mask     */
+
+#define CRPT_AES_KSCTL_NUM_Pos         (0)                                               /*!< CRPT_T::AES_KSCTL: NUM Position      */
+#define CRPT_AES_KSCTL_NUM_Msk         (0x1ful << CRPT_AES_KSCTL_NUM_Pos)              /*!< CRPT_T::AES_KSCTL: NUM Mask          */
+
+#define CRPT_AES_KSCTL_RSRC_Pos        (5)                                               /*!< CRPT_T::AES_KSCTL: RSRC Position     */
+#define CRPT_AES_KSCTL_RSRC_Msk        (0x1ul << CRPT_AES_KSCTL_RSRC_Pos)              /*!< CRPT_T::AES_KSCTL: RSRC Mask         */
+
+#define CRPT_AES_KSCTL_RSSRC_Pos       (6)                                               /*!< CRPT_T::AES_KSCTL: RSSRC Position    */
+#define CRPT_AES_KSCTL_RSSRC_Msk       (0x3ul << CRPT_AES_KSCTL_RSSRC_Pos)             /*!< CRPT_T::AES_KSCTL: RSSRC Mask        */
+
+#define CRPT_HMAC_KSCTL_NUM_Pos        (0)                                               /*!< CRPT_T::HMAC_KSCTL: NUM Position     */
+#define CRPT_HMAC_KSCTL_NUM_Msk        (0x1ful << CRPT_HMAC_KSCTL_NUM_Pos)             /*!< CRPT_T::HMAC_KSCTL: NUM Mask         */
+
+#define CRPT_HMAC_KSCTL_RSRC_Pos       (5)                                               /*!< CRPT_T::HMAC_KSCTL: RSRC Position    */
+#define CRPT_HMAC_KSCTL_RSRC_Msk       (0x1ul << CRPT_HMAC_KSCTL_RSRC_Pos)             /*!< CRPT_T::HMAC_KSCTL: RSRC Mask        */
+
+#define CRPT_HMAC_KSCTL_RSSRC_Pos      (6)                                               /*!< CRPT_T::HMAC_KSCTL: RSSRC Position   */
+#define CRPT_HMAC_KSCTL_RSSRC_Msk      (0x3ul << CRPT_HMAC_KSCTL_RSSRC_Pos)            /*!< CRPT_T::HMAC_KSCTL: RSSRC Mask       */
+
+#define CRPT_ECC_KSCTL_NUMK_Pos        (0)                                               /*!< CRPT_T::ECC_KSCTL: NUMK Position     */
+#define CRPT_ECC_KSCTL_NUMK_Msk        (0x1ful << CRPT_ECC_KSCTL_NUMK_Pos)             /*!< CRPT_T::ECC_KSCTL: NUMK Mask         */
+
+#define CRPT_ECC_KSCTL_RSRCK_Pos       (5)                                               /*!< CRPT_T::ECC_KSCTL: RSRCK Position    */
+#define CRPT_ECC_KSCTL_RSRCK_Msk       (0x1ul << CRPT_ECC_KSCTL_RSRCK_Pos)             /*!< CRPT_T::ECC_KSCTL: RSRCK Mask        */
+
+#define CRPT_ECC_KSCTL_RSSRCK_Pos      (6)                                               /*!< CRPT_T::ECC_KSCTL: RSSRCK Position   */
+#define CRPT_ECC_KSCTL_RSSRCK_Msk      (0x3ul << CRPT_ECC_KSCTL_RSSRCK_Pos)            /*!< CRPT_T::ECC_KSCTL: RSSRCK Mask       */
+
+#define CRPT_ECC_KSCTL_ECDH_Pos        (14)                                              /*!< CRPT_T::ECC_KSCTL: ECDH Position     */
+#define CRPT_ECC_KSCTL_ECDH_Msk        (0x1ul << CRPT_ECC_KSCTL_ECDH_Pos)              /*!< CRPT_T::ECC_KSCTL: ECDH Mask         */
+
+#define CRPT_ECC_KSCTL_TRUST_Pos       (16)                                              /*!< CRPT_T::ECC_KSCTL: TRUST Position    */
+#define CRPT_ECC_KSCTL_TRUST_Msk       (0x1ul << CRPT_ECC_KSCTL_TRUST_Pos)             /*!< CRPT_T::ECC_KSCTL: TRUST Mask        */
+
+#define CRPT_ECC_KSCTL_PRIV_Pos        (18)                                              /*!< CRPT_T::ECC_KSCTL: PRIV Position     */
+#define CRPT_ECC_KSCTL_PRIV_Msk        (0x1ul << CRPT_ECC_KSCTL_PRIV_Pos)              /*!< CRPT_T::ECC_KSCTL: PRIV Mask         */
+
+#define CRPT_ECC_KSCTL_XY_Pos          (20)                                              /*!< CRPT_T::ECC_KSCTL: XY Position       */
+#define CRPT_ECC_KSCTL_XY_Msk          (0x1ul << CRPT_ECC_KSCTL_XY_Pos)                /*!< CRPT_T::ECC_KSCTL: XY Mask           */
+
+#define CRPT_ECC_KSCTL_WDST_Pos        (21)                                              /*!< CRPT_T::ECC_KSCTL: WDST Position     */
+#define CRPT_ECC_KSCTL_WDST_Msk        (0x1ul << CRPT_ECC_KSCTL_WDST_Pos)              /*!< CRPT_T::ECC_KSCTL: WDST Mask         */
+
+#define CRPT_ECC_KSCTL_WSDST_Pos       (22)                                              /*!< CRPT_T::ECC_KSCTL: WSDST Position    */
+#define CRPT_ECC_KSCTL_WSDST_Msk       (0x3ul << CRPT_ECC_KSCTL_WSDST_Pos)             /*!< CRPT_T::ECC_KSCTL: WSDST Mask        */
+
+#define CRPT_ECC_KSCTL_OWNER_Pos       (24)                                              /*!< CRPT_T::ECC_KSCTL: OWNER Position    */
+#define CRPT_ECC_KSCTL_OWNER_Msk       (0x7ul << CRPT_ECC_KSCTL_OWNER_Pos)             /*!< CRPT_T::ECC_KSCTL: OWNER Mask        */
+
+#define CRPT_ECC_KSSTS_NUM_Pos         (0)                                               /*!< CRPT_T::ECC_KSSTS: NUM Position      */
+#define CRPT_ECC_KSSTS_NUM_Msk         (0x1ful << CRPT_ECC_KSSTS_NUM_Pos)              /*!< CRPT_T::ECC_KSSTS: NUM Mask          */
+
+#define CRPT_ECC_KSXY_NUMX_Pos         (0)                                               /*!< CRPT_T::ECC_KSXY: NUMX Position      */
+#define CRPT_ECC_KSXY_NUMX_Msk         (0x1ful << CRPT_ECC_KSXY_NUMX_Pos)              /*!< CRPT_T::ECC_KSXY: NUMX Mask          */
+
+#define CRPT_ECC_KSXY_RSRCXY_Pos       (5)                                               /*!< CRPT_T::ECC_KSXY: RSRCXY Position    */
+#define CRPT_ECC_KSXY_RSRCXY_Msk       (0x1ul << CRPT_ECC_KSXY_RSRCXY_Pos)             /*!< CRPT_T::ECC_KSXY: RSRCXY Mask        */
+
+#define CRPT_ECC_KSXY_RSSRCX_Pos       (6)                                               /*!< CRPT_T::ECC_KSXY: RSSRCX Position    */
+#define CRPT_ECC_KSXY_RSSRCX_Msk       (0x3ul << CRPT_ECC_KSXY_RSSRCX_Pos)             /*!< CRPT_T::ECC_KSXY: RSSRCX Mask        */
+
+#define CRPT_ECC_KSXY_NUMY_Pos         (8)                                               /*!< CRPT_T::ECC_KSXY: NUMY Position      */
+#define CRPT_ECC_KSXY_NUMY_Msk         (0x1ful << CRPT_ECC_KSXY_NUMY_Pos)              /*!< CRPT_T::ECC_KSXY: NUMY Mask          */
+
+#define CRPT_ECC_KSXY_RSSRCY_Pos       (14)                                              /*!< CRPT_T::ECC_KSXY: RSSRCY Position    */
+#define CRPT_ECC_KSXY_RSSRCY_Msk       (0x3ul << CRPT_ECC_KSXY_RSSRCY_Pos)             /*!< CRPT_T::ECC_KSXY: RSSRCY Mask        */
+
+#define CRPT_RSA_KSCTL_NUM_Pos         (0)                                               /*!< CRPT_T::RSA_KSCTL: NUM Position      */
+#define CRPT_RSA_KSCTL_NUM_Msk         (0x1ful << CRPT_RSA_KSCTL_NUM_Pos)              /*!< CRPT_T::RSA_KSCTL: NUM Mask          */
+
+#define CRPT_RSA_KSCTL_RSRC_Pos        (5)                                               /*!< CRPT_T::RSA_KSCTL: RSRC Position     */
+#define CRPT_RSA_KSCTL_RSRC_Msk        (0x1ul << CRPT_RSA_KSCTL_RSRC_Pos)              /*!< CRPT_T::RSA_KSCTL: RSRC Mask         */
+
+#define CRPT_RSA_KSCTL_RSSRC_Pos       (6)                                               /*!< CRPT_T::RSA_KSCTL: RSSRC Position    */
+#define CRPT_RSA_KSCTL_RSSRC_Msk       (0x3ul << CRPT_RSA_KSCTL_RSSRC_Pos)             /*!< CRPT_T::RSA_KSCTL: RSSRC Mask        */
+
+#define CRPT_RSA_KSCTL_BKNUM_Pos       (8)                                               /*!< CRPT_T::RSA_KSCTL: BKNUM Position    */
+#define CRPT_RSA_KSCTL_BKNUM_Msk       (0x1ful << CRPT_RSA_KSCTL_BKNUM_Pos)            /*!< CRPT_T::RSA_KSCTL: BKNUM Mask        */
+
+#define CRPT_RSA_KSSTS0_NUM0_Pos       (0)                                               /*!< CRPT_T::RSA_KSSTS0: NUM0 Position    */
+#define CRPT_RSA_KSSTS0_NUM0_Msk       (0x1ful << CRPT_RSA_KSSTS0_NUM0_Pos)            /*!< CRPT_T::RSA_KSSTS0: NUM0 Mask        */
+
+#define CRPT_RSA_KSSTS0_NUM1_Pos       (8)                                               /*!< CRPT_T::RSA_KSSTS0: NUM1 Position    */
+#define CRPT_RSA_KSSTS0_NUM1_Msk       (0x1ful << CRPT_RSA_KSSTS0_NUM1_Pos)            /*!< CRPT_T::RSA_KSSTS0: NUM1 Mask        */
+
+#define CRPT_RSA_KSSTS0_NUM2_Pos       (16)                                              /*!< CRPT_T::RSA_KSSTS0: NUM2 Position    */
+#define CRPT_RSA_KSSTS0_NUM2_Msk       (0x1ful << CRPT_RSA_KSSTS0_NUM2_Pos)            /*!< CRPT_T::RSA_KSSTS0: NUM2 Mask        */
+
+#define CRPT_RSA_KSSTS0_NUM3_Pos       (24)                                              /*!< CRPT_T::RSA_KSSTS0: NUM3 Position    */
+#define CRPT_RSA_KSSTS0_NUM3_Msk       (0x1ful << CRPT_RSA_KSSTS0_NUM3_Pos)            /*!< CRPT_T::RSA_KSSTS0: NUM3 Mask        */
+
+#define CRPT_RSA_KSSTS1_NUM4_Pos       (0)                                               /*!< CRPT_T::RSA_KSSTS1: NUM4 Position    */
+#define CRPT_RSA_KSSTS1_NUM4_Msk       (0x1ful << CRPT_RSA_KSSTS1_NUM4_Pos)            /*!< CRPT_T::RSA_KSSTS1: NUM4 Mask        */
+
+#define CRPT_RSA_KSSTS1_NUM5_Pos       (8)                                               /*!< CRPT_T::RSA_KSSTS1: NUM5 Position    */
+#define CRPT_RSA_KSSTS1_NUM5_Msk       (0x1ful << CRPT_RSA_KSSTS1_NUM5_Pos)            /*!< CRPT_T::RSA_KSSTS1: NUM5 Mask        */
+
+#define CRPT_RSA_KSSTS1_NUM6_Pos       (16)                                              /*!< CRPT_T::RSA_KSSTS1: NUM6 Position    */
+#define CRPT_RSA_KSSTS1_NUM6_Msk       (0x1ful << CRPT_RSA_KSSTS1_NUM6_Pos)            /*!< CRPT_T::RSA_KSSTS1: NUM6 Mask        */
+
+#define CRPT_RSA_KSSTS1_NUM7_Pos       (24)                                              /*!< CRPT_T::RSA_KSSTS1: NUM7 Position    */
+#define CRPT_RSA_KSSTS1_NUM7_Msk       (0x1ful << CRPT_RSA_KSSTS1_NUM7_Pos)            /*!< CRPT_T::RSA_KSSTS1: NUM7 Mask        */
+
+#define CRPT_VERSION_MINOR_Pos         (0)                                               /*!< CRPT_T::VERSION: MINOR Position      */
+#define CRPT_VERSION_MINOR_Msk         (0xfffful << CRPT_VERSION_MINOR_Pos)            /*!< CRPT_T::VERSION: MINOR Mask          */
+
+#define CRPT_VERSION_SUB_Pos           (16)                                              /*!< CRPT_T::VERSION: SUB Position        */
+#define CRPT_VERSION_SUB_Msk           (0xfful << CRPT_VERSION_SUB_Pos)                /*!< CRPT_T::VERSION: SUB Mask            */
+
+#define CRPT_VERSION_MAJOR_Pos         (24)                                              /*!< CRPT_T::VERSION: MAJOR Position      */
+#define CRPT_VERSION_MAJOR_Msk         (0xfful << CRPT_VERSION_MAJOR_Pos)              /*!< CRPT_T::VERSION: MAJOR Mask          */
+
+/**@}*/ /* CRPT_CONST */
+/**@}*/ /* end of CRYPTO register group */
+
+
+/**@}*/ /* end of REGISTER group */
+
+#endif /* __CRPT_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/dac_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/dac_reg.h
new file mode 100644
index 0000000000..564203dbf3
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/dac_reg.h
@@ -0,0 +1,208 @@
+/**************************************************************************//**
+ * @file     dac_reg.h
+ * @version  V1.00
+ * @brief    DAC register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __DAC_REG_H__
+#define __DAC_REG_H__
+
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+/*---------------------- Digital to Analog Converter -------------------------*/
+/**
+    @addtogroup DAC Digital to Analog Converter(DAC)
+    Memory Mapped Structure for DAC Controller
+  @{
+*/
+
+
+typedef struct
+{
+
+
+
+    /**
+     * @var DAC_T::CTL
+     * Offset: 0x00  DAC Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |DACEN     |DAC Enable Bit
+     * |        |          |0 = DAC is Disabled.
+     * |        |          |1 = DAC is Enabled.
+     * |[1]     |DACIEN    |DAC Interrupt Enable Bit
+     * |        |          |0 = Interrupt is Disabled.
+     * |        |          |1 = Interrupt is Enabled.
+     * |[2]     |DMAEN     |DMA Mode Enable Bit
+     * |        |          |0 = DMA mode Disabled.
+     * |        |          |1 = DMA mode Enabled.
+     * |[3]     |DMAURIEN  |DMA Under-run Interrupt Enable Bit
+     * |        |          |0 = DMA under-run interrupt Disabled.
+     * |        |          |1 = DMA under-run interrupt Enabled.
+     * |[4]     |TRGEN     |Trigger Mode Enable Bit
+     * |        |          |0 = DAC event trigger mode Disabled.
+     * |        |          |1 = DAC event trigger mode Enabled.
+     * |[7:5]   |TRGSEL    |Trigger Source Selection
+     * |        |          |000 = Software trigger.
+     * |        |          |001 = External pin DAC0_ST trigger.
+     * |        |          |010 = Timer 0 trigger.
+     * |        |          |011 = Timer 1 trigger.
+     * |        |          |100 = Timer 2 trigger.
+     * |        |          |101 = Timer 3 trigger.
+     * |        |          |110 = EPWM0 trigger.
+     * |        |          |111 = EPWM1 trigger.
+     * |[8]     |BYPASS    |Bypass Buffer Mode
+     * |        |          |0 = Output voltage buffer Enabled.
+     * |        |          |1 = Output voltage buffer Disabled.
+     * |[10]    |LALIGN    |DAC Data Left-aligned Enabled Control
+     * |        |          |0 = Right alignment.
+     * |        |          |1 = Left alignment.
+     * |[13:12] |ETRGSEL   |External Pin Trigger Selection
+     * |        |          |00 = Low level trigger.
+     * |        |          |01 = High level trigger.
+     * |        |          |10 = Falling edge trigger.
+     * |        |          |11 = Rising edge trigger.
+     * |[15:14] |BWSEL     |DAC Data Bit-width Selection
+     * |        |          |00 = data is 12 bits.
+     * |        |          |01 = data is 8 bits.
+     * |        |          |Others = reserved.
+     * |[16]    |GRPEN     |DAC Group Mode Enable Bit
+     * |        |          |0 = DAC0 and DAC1 are not grouped.
+     * |        |          |1 = DAC0 and DAC1 are grouped.
+     * @var DAC_T::SWTRG
+     * Offset: 0x04  DAC Software Trigger Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SWTRG     |Software Trigger
+     * |        |          |0 = Software trigger Disabled.
+     * |        |          |1 = Software trigger Enabled.
+     * |        |          |User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0.
+     * @var DAC_T::DAT
+     * Offset: 0x08  DAC Data Holding Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |DACDAT    |DAC 12-bit Holding Data
+     * |        |          |These bits are written by user software which specifies 12-bit conversion data for DAC output.
+     * |        |          |The unused bits (DACDAT[3:0] in left-alignment mode and DACDAT[15:12] in right alignment mode) are ignored by DAC controller hardware.
+     * |        |          |12 bit left alignment: user has to load data into DACDAT[15:4] bits.
+     * |        |          |12 bit right alignment: user has to load data into DACDAT[11:0] bits.
+     * @var DAC_T::DATOUT
+     * Offset: 0x0C  DAC Data Output Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[11:0]  |DATOUT    |DAC 12-bit Output Data
+     * |        |          |These bits are current digital data for DAC output conversion.
+     * |        |          |It is loaded from DAC_DAT register and user cannot write it directly.
+     * @var DAC_T::STATUS
+     * Offset: 0x10  DAC Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |FINISH    |DAC Conversion Complete Finish Flag
+     * |        |          |0 = DAC is in conversion state.
+     * |        |          |1 = DAC conversion finish.
+     * |        |          |This bit set to 1 when conversion time counter counts to SETTLET.
+     * |        |          |It is cleared to 0 when DAC starts a new conversion.
+     * |        |          |User writes 1 to clear this bit to 0.
+     * |[1]     |DMAUDR    |DMA Under-run Interrupt Flag
+     * |        |          |0 = No DMA under-run error condition occurred.
+     * |        |          |1 = DMA under-run error condition occurred.
+     * |        |          |User writes 1 to clear this bit.
+     * |[8]     |BUSY      |DAC Busy Flag (Read Only)
+     * |        |          |0 = DAC is ready for next conversion.
+     * |        |          |1 = DAC is busy in conversion.
+     * |        |          |This is read only bit.
+     * @var DAC_T::TCTL
+     * Offset: 0x14  DAC Timing Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[9:0]   |SETTLET   |DAC Output Settling Time
+     * |        |          |User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.
+     * |        |          |For example, DAC controller clock speed is 64MHz and DAC conversion setting time is 1 us, SETTLET value must be greater than 0x40.
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] DAC Control Register                                             */
+    __IO uint32_t SWTRG;                 /*!< [0x0004] DAC Software Trigger Control Register                            */
+    __IO uint32_t DAT;                   /*!< [0x0008] DAC Data Holding Register                                        */
+    __I  uint32_t DATOUT;                /*!< [0x000c] DAC Data Output Register                                         */
+    __IO uint32_t STATUS;                /*!< [0x0010] DAC Status Register                                              */
+    __IO uint32_t TCTL;                  /*!< [0x0014] DAC Timing Control Register                                      */
+
+} DAC_T;
+
+/**
+    @addtogroup DAC_CONST DAC Bit Field Definition
+    Constant Definitions for DAC Controller
+  @{
+*/
+
+#define DAC_CTL_DACEN_Pos                (0)                                               /*!< DAC_T::CTL: DACEN Position             */
+#define DAC_CTL_DACEN_Msk                (0x1ul << DAC_CTL_DACEN_Pos)                      /*!< DAC_T::CTL: DACEN Mask                 */
+
+#define DAC_CTL_DACIEN_Pos               (1)                                               /*!< DAC_T::CTL: DACIEN Position            */
+#define DAC_CTL_DACIEN_Msk               (0x1ul << DAC_CTL_DACIEN_Pos)                     /*!< DAC_T::CTL: DACIEN Mask                */
+
+#define DAC_CTL_DMAEN_Pos                (2)                                               /*!< DAC_T::CTL: DMAEN Position             */
+#define DAC_CTL_DMAEN_Msk                (0x1ul << DAC_CTL_DMAEN_Pos)                      /*!< DAC_T::CTL: DMAEN Mask                 */
+
+#define DAC_CTL_DMAURIEN_Pos             (3)                                               /*!< DAC_T::CTL: DMAURIEN Position          */
+#define DAC_CTL_DMAURIEN_Msk             (0x1ul << DAC_CTL_DMAURIEN_Pos)                   /*!< DAC_T::CTL: DMAURIEN Mask              */
+
+#define DAC_CTL_TRGEN_Pos                (4)                                               /*!< DAC_T::CTL: TRGEN Position             */
+#define DAC_CTL_TRGEN_Msk                (0x1ul << DAC_CTL_TRGEN_Pos)                      /*!< DAC_T::CTL: TRGEN Mask                 */
+
+#define DAC_CTL_TRGSEL_Pos               (5)                                               /*!< DAC_T::CTL: TRGSEL Position            */
+#define DAC_CTL_TRGSEL_Msk               (0x7ul << DAC_CTL_TRGSEL_Pos)                     /*!< DAC_T::CTL: TRGSEL Mask                */
+
+#define DAC_CTL_BYPASS_Pos               (8)                                               /*!< DAC_T::CTL: BYPASS Position            */
+#define DAC_CTL_BYPASS_Msk               (0x1ul << DAC_CTL_BYPASS_Pos)                     /*!< DAC_T::CTL: BYPASS Mask                */
+
+#define DAC_CTL_LALIGN_Pos               (10)                                              /*!< DAC_T::CTL: LALIGN Position            */
+#define DAC_CTL_LALIGN_Msk               (0x1ul << DAC_CTL_LALIGN_Pos)                     /*!< DAC_T::CTL: LALIGN Mask                */
+
+#define DAC_CTL_ETRGSEL_Pos              (12)                                              /*!< DAC_T::CTL: ETRGSEL Position           */
+#define DAC_CTL_ETRGSEL_Msk              (0x3ul << DAC_CTL_ETRGSEL_Pos)                    /*!< DAC_T::CTL: ETRGSEL Mask               */
+
+#define DAC_CTL_BWSEL_Pos                (14)                                              /*!< DAC_T::CTL: BWSEL Position             */
+#define DAC_CTL_BWSEL_Msk                (0x3ul << DAC_CTL_BWSEL_Pos)                      /*!< DAC_T::CTL: BWSEL Mask                 */
+
+#define DAC_CTL_GRPEN_Pos                (16)                                              /*!< DAC_T::CTL: GRPEN Position             */
+#define DAC_CTL_GRPEN_Msk                (0x1ul << DAC_CTL_GRPEN_Pos)                      /*!< DAC_T::CTL: GRPEN Mask                 */
+
+#define DAC_SWTRG_SWTRG_Pos              (0)                                               /*!< DAC_T::SWTRG: SWTRG Position           */
+#define DAC_SWTRG_SWTRG_Msk              (0x1ul << DAC_SWTRG_SWTRG_Pos)                    /*!< DAC_T::SWTRG: SWTRG Mask               */
+
+#define DAC_DAT_DACDAT_Pos               (0)                                               /*!< DAC_T::DAT: DACDAT Position            */
+#define DAC_DAT_DACDAT_Msk               (0xfffful << DAC_DAT_DACDAT_Pos)                  /*!< DAC_T::DAT: DACDAT Mask                */
+
+#define DAC_DATOUT_DATOUT_Pos            (0)                                               /*!< DAC_T::DATOUT: DATOUT Position         */
+#define DAC_DATOUT_DATOUT_Msk            (0xffful << DAC_DATOUT_DATOUT_Pos)                /*!< DAC_T::DATOUT: DATOUT Mask             */
+
+#define DAC_STATUS_FINISH_Pos            (0)                                               /*!< DAC_T::STATUS: FINISH Position         */
+#define DAC_STATUS_FINISH_Msk            (0x1ul << DAC_STATUS_FINISH_Pos)                  /*!< DAC_T::STATUS: FINISH Mask             */
+
+#define DAC_STATUS_DMAUDR_Pos            (1)                                               /*!< DAC_T::STATUS: DMAUDR Position         */
+#define DAC_STATUS_DMAUDR_Msk            (0x1ul << DAC_STATUS_DMAUDR_Pos)                  /*!< DAC_T::STATUS: DMAUDR Mask             */
+
+#define DAC_STATUS_BUSY_Pos              (8)                                               /*!< DAC_T::STATUS: BUSY Position           */
+#define DAC_STATUS_BUSY_Msk              (0x1ul << DAC_STATUS_BUSY_Pos)                    /*!< DAC_T::STATUS: BUSY Mask               */
+
+#define DAC_TCTL_SETTLET_Pos             (0)                                               /*!< DAC_T::TCTL: SETTLET Position          */
+#define DAC_TCTL_SETTLET_Msk             (0x3fful << DAC_TCTL_SETTLET_Pos)                 /*!< DAC_T::TCTL: SETTLET Mask              */
+
+/**@}*/ /* DAC_CONST */
+/**@}*/ /* end of DAC register group */
+/**@}*/ /* end of REGISTER group */
+
+#endif /* __DAC_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/eadc_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/eadc_reg.h
new file mode 100644
index 0000000000..bedb6a60c0
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/eadc_reg.h
@@ -0,0 +1,1707 @@
+/**************************************************************************//**
+ * @file     eadc_reg.h
+ * @version  V1.00
+ * @brief    EADC register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __EADC_REG_H__
+#define __EADC_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+/*---------------------- Enhanced Analog to Digital Converter -------------------------*/
+/**
+    @addtogroup EADC Enhanced Analog to Digital Converter(EADC)
+    Memory Mapped Structure for EADC Controller
+  @{
+*/
+
+
+typedef struct
+{
+
+
+    /**
+     * @var EADC_T::DAT[19]
+     * Offset: 0x00  ADC Data Register 0~18 for Sample Module 0~18
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |RESULT    |ADC Conversion Result
+     * |        |          |This field contains 12 bits conversion result.
+     * |        |          |When DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].
+     * |        |          |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12].
+     * |[16]    |OV        |Overrun Flag
+     * |        |          |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1.
+     * |        |          |0 = Data in RESULT[11:0] is recent conversion result.
+     * |        |          |1 = Data in RESULT[11:0] is overwrite.
+     * |        |          |Note: It is cleared by hardware after EADC_DAT register is read.
+     * |[17]    |VALID     |Valid Flag
+     * |        |          |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read.
+     * |        |          |0 = Data in RESULT[11:0] bits is not valid.
+     * |        |          |1 = Data in RESULT[11:0] bits is valid.
+     * @var EADC_T::CURDAT
+     * Offset: 0x4C  ADC PDMA Current Transfer Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[17:0]  |CURDAT    |ADC PDMA Current Transfer Data Register
+     * |        |          |This register is a shadow register of EADC_DATn (n=0~18) for PDMA support.
+     * |        |          |This is a read only register.
+     * @var EADC_T::CTL
+     * Offset: 0x50  ADC Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ADCEN     |ADC Converter Enable Bit
+     * |        |          |0 = Disabled EADC.
+     * |        |          |1 = Enabled EADC.
+     * |        |          |Note: Before starting ADC conversion function, this bit should be set to 1
+     * |        |          |Clear it to 0 to disable ADC converter analog circuit power consumption.
+     * |[1]     |ADCRST    |ADC Converter Control Circuits Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Cause ADC control circuits reset to initial state, but not change the ADC registers value.
+     * |        |          |Note: ADCRST bit remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0.
+     * |[2]     |ADCIEN0   |Specific Sample Module ADC ADINT0 Interrupt Enable Bit
+     * |        |          |The ADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module ADC conversion
+     * |        |          |If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated.
+     * |        |          |0 = Specific sample module ADC ADINT0 interrupt function Disabled.
+     * |        |          |1 = Specific sample module ADC ADINT0 interrupt function Enabled.
+     * |[3]     |ADCIEN1   |Specific Sample Module ADC ADINT1 Interrupt Enable Bit
+     * |        |          |The ADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module ADC conversion
+     * |        |          |If ADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated.
+     * |        |          |0 = Specific sample module ADC ADINT1 interrupt function Disabled.
+     * |        |          |1 = Specific sample module ADC ADINT1 interrupt function Enabled.
+     * |[4]     |ADCIEN2   |Specific Sample Module ADC ADINT2 Interrupt Enable Bit
+     * |        |          |The ADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module ADC conversion
+     * |        |          |If ADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated.
+     * |        |          |0 = Specific sample module ADC ADINT2 interrupt function Disabled.
+     * |        |          |1 = Specific sample module ADC ADINT2 interrupt function Enabled.
+     * |[5]     |ADCIEN3   |Specific Sample Module ADC ADINT3 Interrupt Enable Bit
+     * |        |          |The ADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module ADC conversion
+     * |        |          |If ADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated.
+     * |        |          |0 = Specific sample module ADC ADINT3 interrupt function Disabled.
+     * |        |          |1 = Specific sample module ADC ADINT3 interrupt function Enabled.
+     * |[7:6]   |RESSEL    |Resolution Selection
+     * |        |          |00 = 6-bit ADC result will be put at RESULT (EADC_DATn[5:0]).
+     * |        |          |01 = 8-bit ADC result will be put at RESULT (EADC_DATn[7:0]).
+     * |        |          |10 = 10-bit ADC result will be put at RESULT (EADC_DATn[9:0]).
+     * |        |          |11 = 12-bit ADC result will be put at RESULT (EADC_DATn[11:0]).
+     * |[8]     |DIFFEN    |Differential Analog Input Mode Enable Bit
+     * |        |          |0 = Single-end analog input mode.
+     * |        |          |1 = Differential analog input mode.
+     * |[9]     |DMOF      |ADC Differential Input Mode Output Format
+     * |        |          |0 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with unsigned format.
+     * |        |          |1 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with 2'complement format.
+     * @var EADC_T::SWTRG
+     * Offset: 0x54  ADC Sample Module Software Start Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[18:0]  |SWTRG     |ADC Sample Module 0~18 Software Force to Start ADC Conversion
+     * |        |          |0 = No effect.
+     * |        |          |1 = Cause an ADC conversion when the priority is given to sample module.
+     * |        |          |Note: After write this register to start ADC conversion, the EADC_PENDSTS register will show which sample module will conversion
+     * |        |          |If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.
+     * @var EADC_T::PENDSTS
+     * Offset: 0x58  ADC Start of Conversion Pending Flag Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[18:0]  |STPF      |ADC Sample Module 0~18 Start of Conversion Pending Flag
+     * |        |          |Read:
+     * |        |          |0 = There is no pending conversion for sample module.
+     * |        |          |1 = Sample module ADC start of conversion is pending.
+     * |        |          |Write:
+     * |        |          |1 = clear pending flag and cancel the conversion for sample module.
+     * |        |          |Note: This bit remains 1 during pending state, when the respective ADC conversion is end, the STPFn (n=0~18) bit is automatically cleared to 0
+     * @var EADC_T::OVSTS
+     * Offset: 0x5C  ADC Sample Module Start of Conversion Overrun Flag Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[18:0]  |SPOVF     |ADC SAMPLE0~18 Overrun Flag
+     * |        |          |0 = No sample module event overrun.
+     * |        |          |1 = Indicates a new sample module event is generated while an old one event is pending.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * @var EADC_T::SCTL[19]
+     * Offset: 0x80  ADC Sample Module 0~18 Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |CHSEL     |ADC Sample Module Channel Selection
+     * |        |          |00H = EADC_CH0 (slow channel).
+     * |        |          |01H = EADC_CH1 (slow channel).
+     * |        |          |02H = EADC_CH2 (slow channel).
+     * |        |          |03H = EADC_CH3 (slow channel).
+     * |        |          |04H = EADC_CH4 (slow channel).
+     * |        |          |05H = EADC_CH5 (slow channel).
+     * |        |          |06H = EADC_CH6 (slow channel).
+     * |        |          |07H = EADC_CH7 (slow channel).
+     * |        |          |08H = EADC_CH8 (slow channel).
+     * |        |          |09H = EADC_CH9 (slow channel).
+     * |        |          |0AH = EADC_CH10 (fast channel).
+     * |        |          |0BH = EADC_CH11 (fast channel).
+     * |        |          |0CH = EADC_CH12 (fast channel).
+     * |        |          |0DH = EADC_CH13 (fast channel).
+     * |        |          |0EH = EADC_CH14 (fast channel).
+     * |        |          |0FH = EADC_CH15 (fast channel).
+     * |[4]     |EXTREN    |ADC External Trigger Rising Edge Enable Bit
+     * |        |          |0 = Rising edge Disabled when ADC selects EADC0_ST as trigger source.
+     * |        |          |1 = Rising edge Enabled when ADC selects EADC0_ST as trigger source.
+     * |[5]     |EXTFEN    |ADC External Trigger Falling Edge Enable Bit
+     * |        |          |0 = Falling edge Disabled when ADC selects EADC0_ST as trigger source.
+     * |        |          |1 = Falling edge Enabled when ADC selects EADC0_ST as trigger source.
+     * |[7:6]   |TRGDLYDIV |ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection
+     * |        |          |Trigger delay clock frequency:
+     * |        |          |00 = ADC_CLK/1.
+     * |        |          |01 = ADC_CLK/2.
+     * |        |          |10 = ADC_CLK/4.
+     * |        |          |11 = ADC_CLK/16.
+     * |[15:8]  |TRGDLYCNT |ADC Sample Module Start of Conversion Trigger Delay Time
+     * |        |          |Trigger delay time = TRGDLYCNT x ADC_CLK x n (n=1,2,4,16 from TRGDLYDIV setting).
+     * |[20:16] |TRGSEL    |ADC Sample Module Start of Conversion Trigger Source Selection
+     * |        |          |0H = Disable trigger.
+     * |        |          |1H = External trigger from EADC0_ST pin input.
+     * |        |          |2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger.
+     * |        |          |3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger.
+     * |        |          |4H = Timer0 overflow pulse trigger.
+     * |        |          |5H = Timer1 overflow pulse trigger.
+     * |        |          |6H = Timer2 overflow pulse trigger.
+     * |        |          |7H = Timer3 overflow pulse trigger.
+     * |        |          |8H = Timer4 overflow pulse trigger.
+     * |        |          |9H = Timer5 overflow pulse trigger.
+     * |        |          |AH = EPWM0TG0.
+     * |        |          |BH = EPWM0TG1.
+     * |        |          |CH = EPWM0TG2.
+     * |        |          |DH = EPWM0TG3.
+     * |        |          |EH = EPWM0TG4.
+     * |        |          |FH = EPWM0TG5.
+     * |        |          |10H = EPWM1TG0.
+     * |        |          |11H = EPWM1TG1.
+     * |        |          |12H = EPWM1TG2.
+     * |        |          |13H = EPWM1TG3.
+     * |        |          |14H = EPWM1TG4.
+     * |        |          |15H = EPWM1TG5.
+     * |        |          |16H = BPWM0TG.
+     * |        |          |17H = BPWM1TG.
+     * |        |          |other = Reserved.
+     * |[22]    |INTPOS    |Interrupt Flag Position Select
+     * |        |          |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC end of conversion.
+     * |        |          |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC start of conversion.
+     * |[23]    |DBMEN     |Double Buffer Mode Enable Bit
+     * |        |          |0 = Sample has one sample result register. (default).
+     * |        |          |1 = Sample has two sample result registers.
+     * |[31:24] |EXTSMPT   |ADC Sampling Time Extend
+     * |        |          |When ADC converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend ADC sampling time after trigger source is coming to get enough sampling time.
+     * |        |          |The range of start delay time is from 0~255 ADC clock.
+     * @var EADC_T::INTSRC[4]
+     * Offset: 0xD0  ADC interrupt 0~3 Source Enable Control Register.
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SPLIE0    |Sample Module 0 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 0 interrupt Disabled.
+     * |        |          |1 = Sample Module 0 interrupt Enabled.
+     * |[1]     |SPLIE1    |Sample Module 1 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 1 interrupt Disabled.
+     * |        |          |1 = Sample Module 1 interrupt Enabled.
+     * |[2]     |SPLIE2    |Sample Module 2 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 2 interrupt Disabled.
+     * |        |          |1 = Sample Module 2 interrupt Enabled.
+     * |[3]     |SPLIE3    |Sample Module 3 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 3 interrupt Disabled.
+     * |        |          |1 = Sample Module 3 interrupt Enabled.
+     * |[4]     |SPLIE4    |Sample Module 4 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 4 interrupt Disabled.
+     * |        |          |1 = Sample Module 4 interrupt Enabled.
+     * |[5]     |SPLIE5    |Sample Module 5 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 5 interrupt Disabled.
+     * |        |          |1 = Sample Module 5 interrupt Enabled.
+     * |[6]     |SPLIE6    |Sample Module 6 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 6 interrupt Disabled.
+     * |        |          |1 = Sample Module 6 interrupt Enabled.
+     * |[7]     |SPLIE7    |Sample Module 7 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 7 interrupt Disabled.
+     * |        |          |1 = Sample Module 7 interrupt Enabled.
+     * |[8]     |SPLIE8    |Sample Module 8 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 8 interrupt Disabled.
+     * |        |          |1 = Sample Module 8 interrupt Enabled.
+     * |[9]     |SPLIE9    |Sample Module 9 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 9 interrupt Disabled.
+     * |        |          |1 = Sample Module 9 interrupt Enabled.
+     * |[10]    |SPLIE10   |Sample Module 10 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 10 interrupt Disabled.
+     * |        |          |1 = Sample Module 10 interrupt Enabled.
+     * |[11]    |SPLIE11   |Sample Module 11 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 11 interrupt Disabled.
+     * |        |          |1 = Sample Module 11 interrupt Enabled.
+     * |[12]    |SPLIE12   |Sample Module 12 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 12 interrupt Disabled.
+     * |        |          |1 = Sample Module 12 interrupt Enabled.
+     * |[13]    |SPLIE13   |Sample Module 13 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 13 interrupt Disabled.
+     * |        |          |1 = Sample Module 13 interrupt Enabled.
+     * |[14]    |SPLIE14   |Sample Module 14 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 14 interrupt Disabled.
+     * |        |          |1 = Sample Module 14 interrupt Enabled.
+     * |[15]    |SPLIE15   |Sample Module 15 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 15 interrupt Disabled.
+     * |        |          |1 = Sample Module 15 interrupt Enabled.
+     * |[16]    |SPLIE16   |Sample Module 16 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 16 interrupt Disabled.
+     * |        |          |1 = Sample Module 16 interrupt Enabled.
+     * |[17]    |SPLIE17   |Sample Module 17 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 17 interrupt Disabled.
+     * |        |          |1 = Sample Module 17 interrupt Enabled.
+     * |[18]    |SPLIE18   |Sample Module 18 Interrupt Enable Bit
+     * |        |          |0 = Sample Module 18 interrupt Disabled.
+     * |        |          |1 = Sample Module 18 interrupt Enabled.
+     * @var EADC_T::CMP[4]
+     * Offset: 0xE0  ADC Result Compare Register 0~3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ADCMPEN   |ADC Result Compare Enable Bit
+     * |        |          |0 = Compare Disabled.
+     * |        |          |1 = Compare Enabled.
+     * |        |          |Set this bit to 1 to enable compare CMPDAT (EADC_CMPn[27:16], n=0~3) with specified sample module conversion result when converted data is loaded into EADC_DAT register.
+     * |[1]     |ADCMPIE   |ADC Result Compare Interrupt Enable Bit
+     * |        |          |0 = Compare function interrupt Disabled.
+     * |        |          |1 = Compare function interrupt Enabled.
+     * |        |          |If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated.
+     * |[2]     |CMPCOND   |Compare Condition
+     * |        |          |0= Set the compare condition as that when a 12-bit ADC conversion result is less than the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one.
+     * |        |          |1= Set the compare condition as that when a 12-bit ADC conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one.
+     * |        |          |Note: When the internal counter reaches the value to (CMPMCNT (EADC_CMPn[11:8], n=0~3) +1), the CMPF bit will be set.
+     * |[7:3]   |CMPSPL    |Compare Sample Module Selection
+     * |        |          |00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared.
+     * |        |          |00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared.
+     * |        |          |00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared.
+     * |        |          |00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared.
+     * |        |          |00100 = Sample Module 4 conversion result EADC_DAT4 is selected to be compared.
+     * |        |          |00101 = Sample Module 5 conversion result EADC_DAT5 is selected to be compared.
+     * |        |          |00110 = Sample Module 6 conversion result EADC_DAT6 is selected to be compared.
+     * |        |          |00111 = Sample Module 7 conversion result EADC_DAT7 is selected to be compared.
+     * |        |          |01000 = Sample Module 8 conversion result EADC_DAT8 is selected to be compared.
+     * |        |          |01001 = Sample Module 9 conversion result EADC_DAT9 is selected to be compared.
+     * |        |          |01010 = Sample Module 10 conversion result EADC_DAT10 is selected to be compared.
+     * |        |          |01011 = Sample Module 11 conversion result EADC_DAT11 is selected to be compared.
+     * |        |          |01100 = Sample Module 12 conversion result EADC_DAT12 is selected to be compared.
+     * |        |          |01101 = Sample Module 13 conversion result EADC_DAT13 is selected to be compared.
+     * |        |          |01110 = Sample Module 14 conversion result EADC_DAT14 is selected to be compared.
+     * |        |          |01111 = Sample Module 15 conversion result EADC_DAT15 is selected to be compared.
+     * |        |          |10000 = Sample Module 16 conversion result EADC_DAT16 is selected to be compared.
+     * |        |          |10001 = Sample Module 17 conversion result EADC_DAT17 is selected to be compared.
+     * |        |          |10010 = Sample Module 18 conversion result EADC_DAT18 is selected to be compared.
+     * |[11:8]  |CMPMCNT   |Compare Match Count
+     * |        |          |When the specified ADC sample module analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPn[2], n=0~3), the internal match counter will increase 1
+     * |        |          |If the compare result does not meet the compare condition, the internal compare match counter will reset to 0
+     * |        |          |When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be set.
+     * |[15]    |CMPWEN    |Compare Window Mode Enable Bit
+     * |        |          |0 = ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched
+     * |        |          |ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched
+     * |        |          |1 = ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched
+     * |        |          |ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched.
+     * |        |          |Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register.
+     * |[27:16] |CMPDAT    |Comparison Data
+     * |        |          |The 12 bits data is used to compare with conversion result of specified sample module
+     * |        |          |User can use it to monitor the external analog input pin voltage transition without imposing a load on software.
+     * @var EADC_T::STATUS0
+     * Offset: 0xF0  ADC Status Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |VALID     |EADC_DAT0~15 Data Valid Flag
+     * |        |          |It is a mirror of VALID bit in sample module ADC result data register EADC_DATn. (n=0~18).
+     * |[31:16] |OV        |EADC_DAT0~15 Overrun Flag
+     * |        |          |It is a mirror to OV bit in sample module ADC result data register EADC_DATn. (n=0~18).
+     * @var EADC_T::STATUS1
+     * Offset: 0xF4  ADC Status Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |VALID     |EADC_DAT16~18 Data Valid Flag
+     * |        |          |It is a mirror of VALID bit in sample module ADC result data register EADC_DATn. (n=0~18).
+     * |[18:16] |OV        |EADC_DAT16~18 Overrun Flag
+     * |        |          |It is a mirror to OV bit in sample module ADC result data register EADC_DATn. (n=0~18).
+     * @var EADC_T::STATUS2
+     * Offset: 0xF8  ADC Status Register 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ADIF0     |ADC ADINT0 Interrupt Flag
+     * |        |          |0 = No ADINT0 interrupt pulse received.
+     * |        |          |1 = ADINT0 interrupt pulse has been received.
+     * |        |          |Note1: This bit is cleared by writing 1 to it.
+     * |        |          |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed
+     * |[1]     |ADIF1     |ADC ADINT1 Interrupt Flag
+     * |        |          |0 = No ADINT1 interrupt pulse received.
+     * |        |          |1 = ADINT1 interrupt pulse has been received.
+     * |        |          |Note1: This bit is cleared by writing 1 to it.
+     * |        |          |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed
+     * |[2]     |ADIF2     |ADC ADINT2 Interrupt Flag
+     * |        |          |0 = No ADINT2 interrupt pulse received.
+     * |        |          |1 = ADINT2 interrupt pulse has been received.
+     * |        |          |Note1: This bit is cleared by writing 1 to it.
+     * |        |          |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed
+     * |[3]     |ADIF3     |ADC ADINT3 Interrupt Flag
+     * |        |          |0 = No ADINT3 interrupt pulse received.
+     * |        |          |1 = ADINT3 interrupt pulse has been received.
+     * |        |          |Note1: This bit is cleared by writing 1 to it.
+     * |        |          |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed
+     * |[4]     |ADCMPF0   |ADC Compare 0 Flag
+     * |        |          |When the specific sample module ADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.
+     * |        |          |0 = Conversion result in EADC_DAT does not meet EADC_CMP0 register setting.
+     * |        |          |1 = Conversion result in EADC_DAT meets EADC_CMP0 register setting.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[5]     |ADCMPF1   |ADC Compare 1 Flag
+     * |        |          |When the specific sample module ADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.
+     * |        |          |0 = Conversion result in EADC_DAT does not meet EADC_CMP1 register setting.
+     * |        |          |1 = Conversion result in EADC_DAT meets EADC_CMP1 register setting.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[6]     |ADCMPF2   |ADC Compare 2 Flag
+     * |        |          |When the specific sample module ADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1.
+     * |        |          |0 = Conversion result in EADC_DAT does not meet EADC_CMP2 register setting.
+     * |        |          |1 = Conversion result in EADC_DAT meets EADC_CMP2 register setting.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[7]     |ADCMPF3   |ADC Compare 3 Flag
+     * |        |          |When the specific sample module ADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1.
+     * |        |          |0 = Conversion result in EADC_DAT does not meet EADC_CMP3 register setting.
+     * |        |          |1 = Conversion result in EADC_DAT meets EADC_CMP3 register setting.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[8]     |ADOVIF0   |ADC ADINT0 Interrupt Flag Overrun
+     * |        |          |0 = ADINT0 interrupt flag is not overwritten to 1.
+     * |        |          |1 = ADINT0 interrupt flag is overwritten to 1.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[9]     |ADOVIF1   |ADC ADINT1 Interrupt Flag Overrun
+     * |        |          |0 = ADINT1 interrupt flag is not overwritten to 1.
+     * |        |          |1 = ADINT1 interrupt flag is overwritten to 1.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[10]    |ADOVIF2   |ADC ADINT2 Interrupt Flag Overrun
+     * |        |          |0 = ADINT2 interrupt flag is not overwritten to 1.
+     * |        |          |1 = ADINT2 interrupt flag is s overwritten to 1.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[11]    |ADOVIF3   |ADC ADINT3 Interrupt Flag Overrun
+     * |        |          |0 = ADINT3 interrupt flag is not overwritten to 1.
+     * |        |          |1 = ADINT3 interrupt flag is overwritten to 1.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[12]    |ADCMPO0   |ADC Compare 0 Output Status (Read Only)
+     * |        |          |The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module.
+     * |        |          |User can use it to monitor the external analog input pin voltage status.
+     * |        |          |0 = Conversion result in EADC_DAT less than CMPDAT0 setting.
+     * |        |          |1 = Conversion result in EADC_DAT great than or equal CMPDAT0 setting.
+     * |[13]    |ADCMPO1   |ADC Compare 1 Output Status (Read Only)
+     * |        |          |The 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module.
+     * |        |          |User can use it to monitor the external analog input pin voltage status.
+     * |        |          |0 = Conversion result in EADC_DAT less than CMPDAT1 setting.
+     * |        |          |1 = Conversion result in EADC_DAT great than or equal CMPDAT1 setting.
+     * |[14]    |ADCMPO2   |ADC Compare 2 Output Status (Read Only)
+     * |        |          |The 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module.
+     * |        |          |User can use it to monitor the external analog input pin voltage status.
+     * |        |          |0 = Conversion result in EADC_DAT less than CMPDAT2 setting.
+     * |        |          |1 = Conversion result in EADC_DAT great than or equal CMPDAT2 setting.
+     * |[15]    |ADCMPO3   |ADC Compare 3 Output Status (Read Only)
+     * |        |          |The 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module.
+     * |        |          |User can use it to monitor the external analog input pin voltage status.
+     * |        |          |0 = Conversion result in EADC_DAT less than CMPDAT3 setting.
+     * |        |          |1 = Conversion result in EADC_DAT great than or equal CMPDAT3 setting.
+     * |[20:16] |CHANNEL   |Current Conversion Channel (Read Only)
+     * |        |          |This filed reflects ADC current conversion channel when BUSY=1.
+     * |        |          |It is read only.
+     * |        |          |00H = EADC_CH0.
+     * |        |          |01H = EADC_CH1.
+     * |        |          |02H = EADC_CH2.
+     * |        |          |03H = EADC_CH3.
+     * |        |          |04H = EADC_CH4.
+     * |        |          |05H = EADC_CH5.
+     * |        |          |06H = EADC_CH6.
+     * |        |          |07H = EADC_CH7.
+     * |        |          |08H = EADC_CH8.
+     * |        |          |09H = EADC_CH9.
+     * |        |          |0AH = EADC_CH10.
+     * |        |          |0BH = EADC_CH11.
+     * |        |          |0CH = EADC_CH12.
+     * |        |          |0DH = EADC_CH13.
+     * |        |          |0EH = EADC_CH14.
+     * |        |          |0FH = EADC_CH15.
+     * |        |          |10H = VBG.
+     * |        |          |11H = VTEMP.
+     * |        |          |12H = VBAT/4.
+     * |[23]    |BUSY      |Busy/Idle (Read Only)
+     * |        |          |0 = EADC is in idle state.
+     * |        |          |1 = EADC is busy at conversion.
+     * |[24]    |ADOVIF    |All ADC Interrupt Flag Overrun Bits Check (Read Only)
+     * |        |          |n=0~3.
+     * |        |          |0 = None of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
+     * |        |          |1 = Any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
+     * |        |          |Note: This bit will keep 1 when any ADOVIFn Flag is equal to 1.
+     * |[25]    |STOVF     |for All ADC Sample Module Start of Conversion Overrun Flags Check (Read Only)
+     * |        |          |n=0~18.
+     * |        |          |0 = None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
+     * |        |          |1 = Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
+     * |        |          |Note: This bit will keep 1 when any SPOVFn Flag is equal to 1.
+     * |[26]    |AVALID    |for All Sample Module ADC Result Data Register EADC_DAT Data Valid Flag Check (Read Only)
+     * |        |          |n=0~18.
+     * |        |          |0 = None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
+     * |        |          |1 = Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
+     * |        |          |Note: This bit will keep 1 when any VALIDn Flag is equal to 1.
+     * |[27]    |AOV       |for All Sample Module ADC Result Data Register Overrun Flags Check (Read Only)
+     * |        |          |n=0~18.
+     * |        |          |0 = None of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
+     * |        |          |1 = Any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
+     * |        |          |Note: This bit will keep 1 when any OVn Flag is equal to 1.
+     * @var EADC_T::STATUS3
+     * Offset: 0xFC  ADC Status Register 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[4:0]   |CURSPL    |ADC Current Sample Module
+     * |        |          |This register show the current ADC is controlled by which sample module control logic modules.
+     * |        |          |If the ADC is Idle, this bit filed will set to 0x1F.
+     * |        |          |This is a read only register.
+     * @var EADC_T::DDAT
+     * Offset: 0x100-0x10C  ADC Double Data Register n for Sample Module n, n=0~3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |RESULT    |ADC Conversion Results
+     * |        |          |This field contains 12 bits conversion results.
+     * |        |          |When the DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12].
+     * |        |          |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT [11:0] and signed bits to will be filled in RESULT [15:12].
+     * |[16]    |OV        |Overrun Flag
+     * |        |          |0 = Data in RESULT (EADC_DATn[15:0], n=0~3) is recent conversion result.
+     * |        |          |1 = Data in RESULT (EADC_DATn[15:0], n=0~3) is overwrite.
+     * |        |          |If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1.
+     * |        |          |It is cleared by hardware after EADC_DDAT register is read.
+     * |[17]    |VALID     |Valid Flag
+     * |        |          |0 = Double data in RESULT (EADC_DDATn[15:0]) is not valid.
+     * |        |          |1 = Double data in RESULT (EADC_DDATn[15:0]) is valid.
+     * |        |          |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DDATn register is read.
+     * |        |          |(n=0~3).
+     * @var EADC_T::PWRM
+     * Offset: 0x110  ADC Power Management Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PWUPRDY   |ADC Power-up Sequence Completed and Ready for Conversion (Read Only)
+     * |        |          |0 = ADC is not ready for conversion may be in power down state or in the progress of power up.
+     * |        |          |1 = ADC is ready for conversion.
+     * |[1]     |PWUCALEN  |Power Up Calibration Function Enable Control
+     * |        |          |0 = Disable the function of calibration at power up.
+     * |        |          |1 = Enable the function of calibration at power up.
+     * |        |          |Note: This bit work together with CALSEL (EADC_CALCTL [3]), see the following
+     * |        |          |{PWUCALEN, CALSEL } Description:
+     * |        |          |PWUCALEN is 0 and CALSEL is 0: No need to calibrate.
+     * |        |          |PWUCALEN is 0 and CALSEL is 1: No need to calibrate.
+     * |        |          |PWUCALEN is 1 and CALSEL is 0: Load calibration word when power up.
+     * |        |          |PWUCALEN is 1 and CALSEL is 1: Calibrate when power up.
+     * |[3:2]   |PWDMOD    |ADC Power-down Mode
+     * |        |          |Set this bit fields to select ADC power down mode when system power-down.
+     * |        |          |00 = ADC Deep power down mode.
+     * |        |          |01 = ADC Power down.
+     * |        |          |10 = ADC Standby mode.
+     * |        |          |11 = ADC Deep power down mode.
+     * |        |          |Note: Different PWDMOD has different power down/up sequence, in order to avoid ADC powering up with wrong sequence; user must keep PWMOD consistent each time in power down and start up
+     * |[19:8]  |LDOSUT    |ADC Internal LDO Start-up Time
+     * |        |          |Set this bit fields to control LDO start-up time
+     * |        |          |The minimum required LDO start-up time is 20us
+     * |        |          |LDO start-up time = (1/ADC_CLK) x LDOSUT.
+     * @var EADC_T::CALCTL
+     * Offset: 0x114  ADC Calibration Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1]     |CALSTART  |Calibration Functional Block Start
+     * |        |          |0 = Stops calibration functional block.
+     * |        |          |1 = Starts calibration functional block.
+     * |        |          |Note: This bit is set by SW and clear by HW after re-calibration finish
+     * |[2]     |CALDONE   |Calibration Functional Block Complete (Read Only)
+     * |        |          |0 = During a calibration.
+     * |        |          |1 = Calibration is completed.
+     * |[3]     |CALSEL    |Select Calibration Functional Block
+     * |        |          |0 = Load calibration word when calibration functional block is active.
+     * |        |          |1 = Execute calibration when calibration functional block is active.
+     * @var EADC_T::CALDWRD
+     * Offset: 0x118  ADC Calibration Load Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[6:0]   |CALWORD   |Calibration Word Bits
+     * |        |          |Write to this register with the previous calibration word before load calibration action.
+     * |        |          |Read this register after calibration done.
+     * |        |          |Note: The calibration block contains two parts CALIBRATION and LOAD CALIBRATION; if the calibration block configure as CALIBRATION; then this register represent the result of calibration when calibration is completed; if configure as LOAD CALIBRATION ; configure this register before loading calibration action, after loading calibration complete, the laoded calibration word will apply to the ADC; while in loading calibration function the loaded value will not be equal to the original CALWORD until calibration is done.
+     */
+
+    __I  uint32_t DAT[19];               /*!< [0x0000~0x0048] ADC Data Register n for Sample Module n, n=0~18           */
+    __I  uint32_t CURDAT;                /*!< [0x004c] ADC PDMA Current Transfer Data Register                          */
+    __IO uint32_t CTL;                   /*!< [0x0050] ADC Control Register                                             */
+    __O  uint32_t SWTRG;                 /*!< [0x0054] ADC Sample Module Software Start Register                        */
+    __IO uint32_t PENDSTS;               /*!< [0x0058] ADC Start of Conversion Pending Flag Register                    */
+    __IO uint32_t OVSTS;                 /*!< [0x005c] ADC Sample Module Start of Conversion Overrun Flag Register      */
+    __I  uint32_t RESERVE0[8];
+    __IO uint32_t SCTL[19];              /*!< [0x0080~0x00c8]  ADC Sample Module n Control Register, n=0~18             */
+    __I  uint32_t RESERVE1[1];
+    __IO uint32_t INTSRC[4];             /*!< [0x00d0~0x00dc]  ADC interrupt n Source Enable Control Register, n=0~3    */
+    __IO uint32_t CMP[4];                /*!< [0x00e0~0x00ec]  ADC Result Compare Register n, n=0~3                     */
+    __I  uint32_t STATUS0;               /*!< [0x00f0] ADC Status Register 0                                            */
+    __I  uint32_t STATUS1;               /*!< [0x00f4] ADC Status Register 1                                            */
+    __IO uint32_t STATUS2;               /*!< [0x00f8] ADC Status Register 2                                            */
+    __I  uint32_t STATUS3;               /*!< [0x00fc] ADC Status Register 3                                            */
+    __I  uint32_t DDAT[4];               /*!< [0x0100~0x010c]  ADC Double Data Register n for Sample Module n, n=0~3    */
+    __IO uint32_t PWRM;                  /*!< [0x0110] ADC Power Management Register                                    */
+    __IO uint32_t CALCTL;                /*!< [0x0114] ADC Calibration Control Register                                 */
+    __IO uint32_t CALDWRD;               /*!< [0x0118] ADC Calibration Load Word Register                               */
+    __I  uint32_t RESERVE2[5];
+    __IO uint32_t PDMACTL;               /*!< [0x0130] ADC PDMA Control Register                                        */
+
+} EADC_T;
+
+/**
+    @addtogroup EADC_CONST EADC Bit Field Definition
+    Constant Definitions for EADC Controller
+  @{
+*/
+
+#define EADC_DAT_RESULT_Pos              (0)                                                /*!< EADC_T::DAT: RESULT Position          */
+#define EADC_DAT_RESULT_Msk              (0xfffful << EADC_DAT_RESULT_Pos)                  /*!< EADC_T::DAT: RESULT Mask              */
+
+#define EADC_DAT_OV_Pos                  (16)                                               /*!< EADC_T::DAT: OV Position              */
+#define EADC_DAT_OV_Msk                  (0x1ul << EADC_DAT_OV_Pos)                         /*!< EADC_T::DAT: OV Mask                  */
+
+#define EADC_DAT_VALID_Pos               (17)                                               /*!< EADC_T::DAT: VALID Position           */
+#define EADC_DAT_VALID_Msk               (0x1ul << EADC_DAT_VALID_Pos)                      /*!< EADC_T::DAT: VALID Mask               */
+
+#define EADC_DAT0_RESULT_Pos             (0)                                               /*!< EADC_T::DAT0: RESULT Position          */
+#define EADC_DAT0_RESULT_Msk             (0xfffful << EADC_DAT0_RESULT_Pos)                /*!< EADC_T::DAT0: RESULT Mask              */
+
+#define EADC_DAT0_OV_Pos                 (16)                                              /*!< EADC_T::DAT0: OV Position              */
+#define EADC_DAT0_OV_Msk                 (0x1ul << EADC_DAT0_OV_Pos)                       /*!< EADC_T::DAT0: OV Mask                  */
+
+#define EADC_DAT0_VALID_Pos              (17)                                              /*!< EADC_T::DAT0: VALID Position           */
+#define EADC_DAT0_VALID_Msk              (0x1ul << EADC_DAT0_VALID_Pos)                    /*!< EADC_T::DAT0: VALID Mask               */
+
+#define EADC_DAT1_RESULT_Pos             (0)                                               /*!< EADC_T::DAT1: RESULT Position          */
+#define EADC_DAT1_RESULT_Msk             (0xfffful << EADC_DAT1_RESULT_Pos)                /*!< EADC_T::DAT1: RESULT Mask              */
+
+#define EADC_DAT1_OV_Pos                 (16)                                              /*!< EADC_T::DAT1: OV Position              */
+#define EADC_DAT1_OV_Msk                 (0x1ul << EADC_DAT1_OV_Pos)                       /*!< EADC_T::DAT1: OV Mask                  */
+
+#define EADC_DAT1_VALID_Pos              (17)                                              /*!< EADC_T::DAT1: VALID Position           */
+#define EADC_DAT1_VALID_Msk              (0x1ul << EADC_DAT1_VALID_Pos)                    /*!< EADC_T::DAT1: VALID Mask               */
+
+#define EADC_DAT2_RESULT_Pos             (0)                                               /*!< EADC_T::DAT2: RESULT Position          */
+#define EADC_DAT2_RESULT_Msk             (0xfffful << EADC_DAT2_RESULT_Pos)                /*!< EADC_T::DAT2: RESULT Mask              */
+
+#define EADC_DAT2_OV_Pos                 (16)                                              /*!< EADC_T::DAT2: OV Position              */
+#define EADC_DAT2_OV_Msk                 (0x1ul << EADC_DAT2_OV_Pos)                       /*!< EADC_T::DAT2: OV Mask                  */
+
+#define EADC_DAT2_VALID_Pos              (17)                                              /*!< EADC_T::DAT2: VALID Position           */
+#define EADC_DAT2_VALID_Msk              (0x1ul << EADC_DAT2_VALID_Pos)                    /*!< EADC_T::DAT2: VALID Mask               */
+
+#define EADC_DAT3_RESULT_Pos             (0)                                               /*!< EADC_T::DAT3: RESULT Position          */
+#define EADC_DAT3_RESULT_Msk             (0xfffful << EADC_DAT3_RESULT_Pos)                /*!< EADC_T::DAT3: RESULT Mask              */
+
+#define EADC_DAT3_OV_Pos                 (16)                                              /*!< EADC_T::DAT3: OV Position              */
+#define EADC_DAT3_OV_Msk                 (0x1ul << EADC_DAT3_OV_Pos)                       /*!< EADC_T::DAT3: OV Mask                  */
+
+#define EADC_DAT3_VALID_Pos              (17)                                              /*!< EADC_T::DAT3: VALID Position           */
+#define EADC_DAT3_VALID_Msk              (0x1ul << EADC_DAT3_VALID_Pos)                    /*!< EADC_T::DAT3: VALID Mask               */
+
+#define EADC_DAT4_RESULT_Pos             (0)                                               /*!< EADC_T::DAT4: RESULT Position          */
+#define EADC_DAT4_RESULT_Msk             (0xfffful << EADC_DAT4_RESULT_Pos)                /*!< EADC_T::DAT4: RESULT Mask              */
+
+#define EADC_DAT4_OV_Pos                 (16)                                              /*!< EADC_T::DAT4: OV Position              */
+#define EADC_DAT4_OV_Msk                 (0x1ul << EADC_DAT4_OV_Pos)                       /*!< EADC_T::DAT4: OV Mask                  */
+
+#define EADC_DAT4_VALID_Pos              (17)                                              /*!< EADC_T::DAT4: VALID Position           */
+#define EADC_DAT4_VALID_Msk              (0x1ul << EADC_DAT4_VALID_Pos)                    /*!< EADC_T::DAT4: VALID Mask               */
+
+#define EADC_DAT5_RESULT_Pos             (0)                                               /*!< EADC_T::DAT5: RESULT Position          */
+#define EADC_DAT5_RESULT_Msk             (0xfffful << EADC_DAT5_RESULT_Pos)                /*!< EADC_T::DAT5: RESULT Mask              */
+
+#define EADC_DAT5_OV_Pos                 (16)                                              /*!< EADC_T::DAT5: OV Position              */
+#define EADC_DAT5_OV_Msk                 (0x1ul << EADC_DAT5_OV_Pos)                       /*!< EADC_T::DAT5: OV Mask                  */
+
+#define EADC_DAT5_VALID_Pos              (17)                                              /*!< EADC_T::DAT5: VALID Position           */
+#define EADC_DAT5_VALID_Msk              (0x1ul << EADC_DAT5_VALID_Pos)                    /*!< EADC_T::DAT5: VALID Mask               */
+
+#define EADC_DAT6_RESULT_Pos             (0)                                               /*!< EADC_T::DAT6: RESULT Position          */
+#define EADC_DAT6_RESULT_Msk             (0xfffful << EADC_DAT6_RESULT_Pos)                /*!< EADC_T::DAT6: RESULT Mask              */
+
+#define EADC_DAT6_OV_Pos                 (16)                                              /*!< EADC_T::DAT6: OV Position              */
+#define EADC_DAT6_OV_Msk                 (0x1ul << EADC_DAT6_OV_Pos)                       /*!< EADC_T::DAT6: OV Mask                  */
+
+#define EADC_DAT6_VALID_Pos              (17)                                              /*!< EADC_T::DAT6: VALID Position           */
+#define EADC_DAT6_VALID_Msk              (0x1ul << EADC_DAT6_VALID_Pos)                    /*!< EADC_T::DAT6: VALID Mask               */
+
+#define EADC_DAT7_RESULT_Pos             (0)                                               /*!< EADC_T::DAT7: RESULT Position          */
+#define EADC_DAT7_RESULT_Msk             (0xfffful << EADC_DAT7_RESULT_Pos)                /*!< EADC_T::DAT7: RESULT Mask              */
+
+#define EADC_DAT7_OV_Pos                 (16)                                              /*!< EADC_T::DAT7: OV Position              */
+#define EADC_DAT7_OV_Msk                 (0x1ul << EADC_DAT7_OV_Pos)                       /*!< EADC_T::DAT7: OV Mask                  */
+
+#define EADC_DAT7_VALID_Pos              (17)                                              /*!< EADC_T::DAT7: VALID Position           */
+#define EADC_DAT7_VALID_Msk              (0x1ul << EADC_DAT7_VALID_Pos)                    /*!< EADC_T::DAT7: VALID Mask               */
+
+#define EADC_DAT8_RESULT_Pos             (0)                                               /*!< EADC_T::DAT8: RESULT Position          */
+#define EADC_DAT8_RESULT_Msk             (0xfffful << EADC_DAT8_RESULT_Pos)                /*!< EADC_T::DAT8: RESULT Mask              */
+
+#define EADC_DAT8_OV_Pos                 (16)                                              /*!< EADC_T::DAT8: OV Position              */
+#define EADC_DAT8_OV_Msk                 (0x1ul << EADC_DAT8_OV_Pos)                       /*!< EADC_T::DAT8: OV Mask                  */
+
+#define EADC_DAT8_VALID_Pos              (17)                                              /*!< EADC_T::DAT8: VALID Position           */
+#define EADC_DAT8_VALID_Msk              (0x1ul << EADC_DAT8_VALID_Pos)                    /*!< EADC_T::DAT8: VALID Mask               */
+
+#define EADC_DAT9_RESULT_Pos             (0)                                               /*!< EADC_T::DAT9: RESULT Position          */
+#define EADC_DAT9_RESULT_Msk             (0xfffful << EADC_DAT9_RESULT_Pos)                /*!< EADC_T::DAT9: RESULT Mask              */
+
+#define EADC_DAT9_OV_Pos                 (16)                                              /*!< EADC_T::DAT9: OV Position              */
+#define EADC_DAT9_OV_Msk                 (0x1ul << EADC_DAT9_OV_Pos)                       /*!< EADC_T::DAT9: OV Mask                  */
+
+#define EADC_DAT9_VALID_Pos              (17)                                              /*!< EADC_T::DAT9: VALID Position           */
+#define EADC_DAT9_VALID_Msk              (0x1ul << EADC_DAT9_VALID_Pos)                    /*!< EADC_T::DAT9: VALID Mask               */
+
+#define EADC_DAT10_RESULT_Pos            (0)                                               /*!< EADC_T::DAT10: RESULT Position         */
+#define EADC_DAT10_RESULT_Msk            (0xfffful << EADC_DAT10_RESULT_Pos)               /*!< EADC_T::DAT10: RESULT Mask             */
+
+#define EADC_DAT10_OV_Pos                (16)                                              /*!< EADC_T::DAT10: OV Position             */
+#define EADC_DAT10_OV_Msk                (0x1ul << EADC_DAT10_OV_Pos)                      /*!< EADC_T::DAT10: OV Mask                 */
+
+#define EADC_DAT10_VALID_Pos             (17)                                              /*!< EADC_T::DAT10: VALID Position          */
+#define EADC_DAT10_VALID_Msk             (0x1ul << EADC_DAT10_VALID_Pos)                   /*!< EADC_T::DAT10: VALID Mask              */
+
+#define EADC_DAT11_RESULT_Pos            (0)                                               /*!< EADC_T::DAT11: RESULT Position         */
+#define EADC_DAT11_RESULT_Msk            (0xfffful << EADC_DAT11_RESULT_Pos)               /*!< EADC_T::DAT11: RESULT Mask             */
+
+#define EADC_DAT11_OV_Pos                (16)                                              /*!< EADC_T::DAT11: OV Position             */
+#define EADC_DAT11_OV_Msk                (0x1ul << EADC_DAT11_OV_Pos)                      /*!< EADC_T::DAT11: OV Mask                 */
+
+#define EADC_DAT11_VALID_Pos             (17)                                              /*!< EADC_T::DAT11: VALID Position          */
+#define EADC_DAT11_VALID_Msk             (0x1ul << EADC_DAT11_VALID_Pos)                   /*!< EADC_T::DAT11: VALID Mask              */
+
+#define EADC_DAT12_RESULT_Pos            (0)                                               /*!< EADC_T::DAT12: RESULT Position         */
+#define EADC_DAT12_RESULT_Msk            (0xfffful << EADC_DAT12_RESULT_Pos)               /*!< EADC_T::DAT12: RESULT Mask             */
+
+#define EADC_DAT12_OV_Pos                (16)                                              /*!< EADC_T::DAT12: OV Position             */
+#define EADC_DAT12_OV_Msk                (0x1ul << EADC_DAT12_OV_Pos)                      /*!< EADC_T::DAT12: OV Mask                 */
+
+#define EADC_DAT12_VALID_Pos             (17)                                              /*!< EADC_T::DAT12: VALID Position          */
+#define EADC_DAT12_VALID_Msk             (0x1ul << EADC_DAT12_VALID_Pos)                   /*!< EADC_T::DAT12: VALID Mask              */
+
+#define EADC_DAT13_RESULT_Pos            (0)                                               /*!< EADC_T::DAT13: RESULT Position         */
+#define EADC_DAT13_RESULT_Msk            (0xfffful << EADC_DAT13_RESULT_Pos)               /*!< EADC_T::DAT13: RESULT Mask             */
+
+#define EADC_DAT13_OV_Pos                (16)                                              /*!< EADC_T::DAT13: OV Position             */
+#define EADC_DAT13_OV_Msk                (0x1ul << EADC_DAT13_OV_Pos)                      /*!< EADC_T::DAT13: OV Mask                 */
+
+#define EADC_DAT13_VALID_Pos             (17)                                              /*!< EADC_T::DAT13: VALID Position          */
+#define EADC_DAT13_VALID_Msk             (0x1ul << EADC_DAT13_VALID_Pos)                   /*!< EADC_T::DAT13: VALID Mask              */
+
+#define EADC_DAT14_RESULT_Pos            (0)                                               /*!< EADC_T::DAT14: RESULT Position         */
+#define EADC_DAT14_RESULT_Msk            (0xfffful << EADC_DAT14_RESULT_Pos)               /*!< EADC_T::DAT14: RESULT Mask             */
+
+#define EADC_DAT14_OV_Pos                (16)                                              /*!< EADC_T::DAT14: OV Position             */
+#define EADC_DAT14_OV_Msk                (0x1ul << EADC_DAT14_OV_Pos)                      /*!< EADC_T::DAT14: OV Mask                 */
+
+#define EADC_DAT14_VALID_Pos             (17)                                              /*!< EADC_T::DAT14: VALID Position          */
+#define EADC_DAT14_VALID_Msk             (0x1ul << EADC_DAT14_VALID_Pos)                   /*!< EADC_T::DAT14: VALID Mask              */
+
+#define EADC_DAT15_RESULT_Pos            (0)                                               /*!< EADC_T::DAT15: RESULT Position         */
+#define EADC_DAT15_RESULT_Msk            (0xfffful << EADC_DAT15_RESULT_Pos)               /*!< EADC_T::DAT15: RESULT Mask             */
+
+#define EADC_DAT15_OV_Pos                (16)                                              /*!< EADC_T::DAT15: OV Position             */
+#define EADC_DAT15_OV_Msk                (0x1ul << EADC_DAT15_OV_Pos)                      /*!< EADC_T::DAT15: OV Mask                 */
+
+#define EADC_DAT15_VALID_Pos             (17)                                              /*!< EADC_T::DAT15: VALID Position          */
+#define EADC_DAT15_VALID_Msk             (0x1ul << EADC_DAT15_VALID_Pos)                   /*!< EADC_T::DAT15: VALID Mask              */
+
+#define EADC_DAT16_RESULT_Pos            (0)                                               /*!< EADC_T::DAT16: RESULT Position         */
+#define EADC_DAT16_RESULT_Msk            (0xfffful << EADC_DAT16_RESULT_Pos)               /*!< EADC_T::DAT16: RESULT Mask             */
+
+#define EADC_DAT16_OV_Pos                (16)                                              /*!< EADC_T::DAT16: OV Position             */
+#define EADC_DAT16_OV_Msk                (0x1ul << EADC_DAT16_OV_Pos)                      /*!< EADC_T::DAT16: OV Mask                 */
+
+#define EADC_DAT16_VALID_Pos             (17)                                              /*!< EADC_T::DAT16: VALID Position          */
+#define EADC_DAT16_VALID_Msk             (0x1ul << EADC_DAT16_VALID_Pos)                   /*!< EADC_T::DAT16: VALID Mask              */
+
+#define EADC_DAT17_RESULT_Pos            (0)                                               /*!< EADC_T::DAT17: RESULT Position         */
+#define EADC_DAT17_RESULT_Msk            (0xfffful << EADC_DAT17_RESULT_Pos)               /*!< EADC_T::DAT17: RESULT Mask             */
+
+#define EADC_DAT17_OV_Pos                (16)                                              /*!< EADC_T::DAT17: OV Position             */
+#define EADC_DAT17_OV_Msk                (0x1ul << EADC_DAT17_OV_Pos)                      /*!< EADC_T::DAT17: OV Mask                 */
+
+#define EADC_DAT17_VALID_Pos             (17)                                              /*!< EADC_T::DAT17: VALID Position          */
+#define EADC_DAT17_VALID_Msk             (0x1ul << EADC_DAT17_VALID_Pos)                   /*!< EADC_T::DAT17: VALID Mask              */
+
+#define EADC_DAT18_RESULT_Pos            (0)                                               /*!< EADC_T::DAT18: RESULT Position         */
+#define EADC_DAT18_RESULT_Msk            (0xfffful << EADC_DAT18_RESULT_Pos)               /*!< EADC_T::DAT18: RESULT Mask             */
+
+#define EADC_DAT18_OV_Pos                (16)                                              /*!< EADC_T::DAT18: OV Position             */
+#define EADC_DAT18_OV_Msk                (0x1ul << EADC_DAT18_OV_Pos)                      /*!< EADC_T::DAT18: OV Mask                 */
+
+#define EADC_DAT18_VALID_Pos             (17)                                              /*!< EADC_T::DAT18: VALID Position          */
+#define EADC_DAT18_VALID_Msk             (0x1ul << EADC_DAT18_VALID_Pos)                   /*!< EADC_T::DAT18: VALID Mask              */
+
+#define EADC_CURDAT_CURDAT_Pos           (0)                                               /*!< EADC_T::CURDAT: CURDAT Position        */
+#define EADC_CURDAT_CURDAT_Msk           (0x3fffful << EADC_CURDAT_CURDAT_Pos)             /*!< EADC_T::CURDAT: CURDAT Mask            */
+
+#define EADC_CTL_ADCEN_Pos               (0)                                               /*!< EADC_T::CTL: ADCEN Position            */
+#define EADC_CTL_ADCEN_Msk               (0x1ul << EADC_CTL_ADCEN_Pos)                     /*!< EADC_T::CTL: ADCEN Mask                */
+
+#define EADC_CTL_ADCRST_Pos              (1)                                               /*!< EADC_T::CTL: ADCRST Position           */
+#define EADC_CTL_ADCRST_Msk              (0x1ul << EADC_CTL_ADCRST_Pos)                    /*!< EADC_T::CTL: ADCRST Mask               */
+
+#define EADC_CTL_ADCIEN0_Pos             (2)                                               /*!< EADC_T::CTL: ADCIEN0 Position          */
+#define EADC_CTL_ADCIEN0_Msk             (0x1ul << EADC_CTL_ADCIEN0_Pos)                   /*!< EADC_T::CTL: ADCIEN0 Mask              */
+
+#define EADC_CTL_ADCIEN1_Pos             (3)                                               /*!< EADC_T::CTL: ADCIEN1 Position          */
+#define EADC_CTL_ADCIEN1_Msk             (0x1ul << EADC_CTL_ADCIEN1_Pos)                   /*!< EADC_T::CTL: ADCIEN1 Mask              */
+
+#define EADC_CTL_ADCIEN2_Pos             (4)                                               /*!< EADC_T::CTL: ADCIEN2 Position          */
+#define EADC_CTL_ADCIEN2_Msk             (0x1ul << EADC_CTL_ADCIEN2_Pos)                   /*!< EADC_T::CTL: ADCIEN2 Mask              */
+
+#define EADC_CTL_ADCIEN3_Pos             (5)                                               /*!< EADC_T::CTL: ADCIEN3 Position          */
+#define EADC_CTL_ADCIEN3_Msk             (0x1ul << EADC_CTL_ADCIEN3_Pos)                   /*!< EADC_T::CTL: ADCIEN3 Mask              */
+
+#define EADC_CTL_RESSEL_Pos              (6)                                               /*!< EADC_T::CTL: RESSEL Position           */
+#define EADC_CTL_RESSEL_Msk              (0x3ul << EADC_CTL_RESSEL_Pos)                    /*!< EADC_T::CTL: RESSEL Mask               */
+
+#define EADC_CTL_DIFFEN_Pos              (8)                                               /*!< EADC_T::CTL: DIFFEN Position           */
+#define EADC_CTL_DIFFEN_Msk              (0x1ul << EADC_CTL_DIFFEN_Pos)                    /*!< EADC_T::CTL: DIFFEN Mask               */
+
+#define EADC_CTL_DMOF_Pos                (9)                                               /*!< EADC_T::CTL: DMOF Position             */
+#define EADC_CTL_DMOF_Msk                (0x1ul << EADC_CTL_DMOF_Pos)                      /*!< EADC_T::CTL: DMOF Mask                 */
+
+#define EADC_SWTRG_SWTRG_Pos             (0)                                               /*!< EADC_T::SWTRG: SWTRG Position          */
+#define EADC_SWTRG_SWTRG_Msk             (0x7fffful << EADC_SWTRG_SWTRG_Pos)               /*!< EADC_T::SWTRG: SWTRG Mask              */
+
+#define EADC_PENDSTS_STPF_Pos            (0)                                               /*!< EADC_T::PENDSTS: STPF Position         */
+#define EADC_PENDSTS_STPF_Msk            (0x7fffful << EADC_PENDSTS_STPF_Pos)              /*!< EADC_T::PENDSTS: STPF Mask             */
+
+#define EADC_OVSTS_SPOVF_Pos             (0)                                               /*!< EADC_T::OVSTS: SPOVF Position          */
+#define EADC_OVSTS_SPOVF_Msk             (0x7fffful << EADC_OVSTS_SPOVF_Pos)               /*!< EADC_T::OVSTS: SPOVF Mask              */
+
+#define EADC_SCTL_CHSEL_Pos              (0)                                               /*!< EADC_T::SCTL: CHSEL Position           */
+#define EADC_SCTL_CHSEL_Msk              (0xful << EADC_SCTL_CHSEL_Pos)                    /*!< EADC_T::SCTL: CHSEL Mask               */
+
+#define EADC_SCTL_EXTREN_Pos             (4)                                               /*!< EADC_T::SCTL: EXTREN Position          */
+#define EADC_SCTL_EXTREN_Msk             (0x1ul << EADC_SCTL_EXTREN_Pos)                   /*!< EADC_T::SCTL: EXTREN Mask              */
+
+#define EADC_SCTL_EXTFEN_Pos             (5)                                               /*!< EADC_T::SCTL: EXTFEN Position          */
+#define EADC_SCTL_EXTFEN_Msk             (0x1ul << EADC_SCTL_EXTFEN_Pos)                   /*!< EADC_T::SCTL: EXTFEN Mask              */
+
+#define EADC_SCTL_TRGDLYDIV_Pos          (6)                                               /*!< EADC_T::SCTL: TRGDLYDIV Position       */
+#define EADC_SCTL_TRGDLYDIV_Msk          (0x3ul << EADC_SCTL_TRGDLYDIV_Pos)                /*!< EADC_T::SCTL: TRGDLYDIV Mask           */
+
+#define EADC_SCTL_TRGDLYCNT_Pos          (8)                                               /*!< EADC_T::SCTL: TRGDLYCNT Position       */
+#define EADC_SCTL_TRGDLYCNT_Msk          (0xfful << EADC_SCTL_TRGDLYCNT_Pos)               /*!< EADC_T::SCTL: TRGDLYCNT Mask           */
+
+#define EADC_SCTL_TRGSEL_Pos             (16)                                              /*!< EADC_T::SCTL: TRGSEL Position          */
+#define EADC_SCTL_TRGSEL_Msk             (0x1ful << EADC_SCTL_TRGSEL_Pos)                  /*!< EADC_T::SCTL: TRGSEL Mask              */
+
+#define EADC_SCTL_INTPOS_Pos             (22)                                              /*!< EADC_T::SCTL: INTPOS Position          */
+#define EADC_SCTL_INTPOS_Msk             (0x1ul << EADC_SCTL_INTPOS_Pos)                   /*!< EADC_T::SCTL: INTPOS Mask              */
+
+#define EADC_SCTL_DBMEN_Pos              (23)                                              /*!< EADC_T::SCTL: DBMEN Position           */
+#define EADC_SCTL_DBMEN_Msk              (0x1ul << EADC_SCTL_DBMEN_Pos)                    /*!< EADC_T::SCTL: DBMEN Mask               */
+
+#define EADC_SCTL_EXTSMPT_Pos            (24)                                              /*!< EADC_T::SCTL: EXTSMPT Position         */
+#define EADC_SCTL_EXTSMPT_Msk            (0xfful << EADC_SCTL_EXTSMPT_Pos)                 /*!< EADC_T::SCTL: EXTSMPT Mask             */
+
+#define EADC_SCTL0_CHSEL_Pos             (0)                                               /*!< EADC_T::SCTL0: CHSEL Position          */
+#define EADC_SCTL0_CHSEL_Msk             (0xful << EADC_SCTL0_CHSEL_Pos)                   /*!< EADC_T::SCTL0: CHSEL Mask              */
+
+#define EADC_SCTL0_EXTREN_Pos            (4)                                               /*!< EADC_T::SCTL0: EXTREN Position         */
+#define EADC_SCTL0_EXTREN_Msk            (0x1ul << EADC_SCTL0_EXTREN_Pos)                  /*!< EADC_T::SCTL0: EXTREN Mask             */
+
+#define EADC_SCTL0_EXTFEN_Pos            (5)                                               /*!< EADC_T::SCTL0: EXTFEN Position         */
+#define EADC_SCTL0_EXTFEN_Msk            (0x1ul << EADC_SCTL0_EXTFEN_Pos)                  /*!< EADC_T::SCTL0: EXTFEN Mask             */
+
+#define EADC_SCTL0_TRGDLYDIV_Pos         (6)                                               /*!< EADC_T::SCTL0: TRGDLYDIV Position      */
+#define EADC_SCTL0_TRGDLYDIV_Msk         (0x3ul << EADC_SCTL0_TRGDLYDIV_Pos)               /*!< EADC_T::SCTL0: TRGDLYDIV Mask          */
+
+#define EADC_SCTL0_TRGDLYCNT_Pos         (8)                                               /*!< EADC_T::SCTL0: TRGDLYCNT Position      */
+#define EADC_SCTL0_TRGDLYCNT_Msk         (0xfful << EADC_SCTL0_TRGDLYCNT_Pos)              /*!< EADC_T::SCTL0: TRGDLYCNT Mask          */
+
+#define EADC_SCTL0_TRGSEL_Pos            (16)                                              /*!< EADC_T::SCTL0: TRGSEL Position         */
+#define EADC_SCTL0_TRGSEL_Msk            (0x1ful << EADC_SCTL0_TRGSEL_Pos)                 /*!< EADC_T::SCTL0: TRGSEL Mask             */
+
+#define EADC_SCTL0_INTPOS_Pos            (22)                                              /*!< EADC_T::SCTL0: INTPOS Position         */
+#define EADC_SCTL0_INTPOS_Msk            (0x1ul << EADC_SCTL0_INTPOS_Pos)                  /*!< EADC_T::SCTL0: INTPOS Mask             */
+
+#define EADC_SCTL0_DBMEN_Pos             (23)                                              /*!< EADC_T::SCTL0: DBMEN Position          */
+#define EADC_SCTL0_DBMEN_Msk             (0x1ul << EADC_SCTL0_DBMEN_Pos)                   /*!< EADC_T::SCTL0: DBMEN Mask              */
+
+#define EADC_SCTL0_EXTSMPT_Pos           (24)                                              /*!< EADC_T::SCTL0: EXTSMPT Position        */
+#define EADC_SCTL0_EXTSMPT_Msk           (0xfful << EADC_SCTL0_EXTSMPT_Pos)                /*!< EADC_T::SCTL0: EXTSMPT Mask            */
+
+#define EADC_SCTL1_CHSEL_Pos             (0)                                               /*!< EADC_T::SCTL1: CHSEL Position          */
+#define EADC_SCTL1_CHSEL_Msk             (0xful << EADC_SCTL1_CHSEL_Pos)                   /*!< EADC_T::SCTL1: CHSEL Mask              */
+
+#define EADC_SCTL1_EXTREN_Pos            (4)                                               /*!< EADC_T::SCTL1: EXTREN Position         */
+#define EADC_SCTL1_EXTREN_Msk            (0x1ul << EADC_SCTL1_EXTREN_Pos)                  /*!< EADC_T::SCTL1: EXTREN Mask             */
+
+#define EADC_SCTL1_EXTFEN_Pos            (5)                                               /*!< EADC_T::SCTL1: EXTFEN Position         */
+#define EADC_SCTL1_EXTFEN_Msk            (0x1ul << EADC_SCTL1_EXTFEN_Pos)                  /*!< EADC_T::SCTL1: EXTFEN Mask             */
+
+#define EADC_SCTL1_TRGDLYDIV_Pos         (6)                                               /*!< EADC_T::SCTL1: TRGDLYDIV Position      */
+#define EADC_SCTL1_TRGDLYDIV_Msk         (0x3ul << EADC_SCTL1_TRGDLYDIV_Pos)               /*!< EADC_T::SCTL1: TRGDLYDIV Mask          */
+
+#define EADC_SCTL1_TRGDLYCNT_Pos         (8)                                               /*!< EADC_T::SCTL1: TRGDLYCNT Position      */
+#define EADC_SCTL1_TRGDLYCNT_Msk         (0xfful << EADC_SCTL1_TRGDLYCNT_Pos)              /*!< EADC_T::SCTL1: TRGDLYCNT Mask          */
+
+#define EADC_SCTL1_TRGSEL_Pos            (16)                                              /*!< EADC_T::SCTL1: TRGSEL Position         */
+#define EADC_SCTL1_TRGSEL_Msk            (0x1ful << EADC_SCTL1_TRGSEL_Pos)                 /*!< EADC_T::SCTL1: TRGSEL Mask             */
+
+#define EADC_SCTL1_INTPOS_Pos            (22)                                              /*!< EADC_T::SCTL1: INTPOS Position         */
+#define EADC_SCTL1_INTPOS_Msk            (0x1ul << EADC_SCTL1_INTPOS_Pos)                  /*!< EADC_T::SCTL1: INTPOS Mask             */
+
+#define EADC_SCTL1_DBMEN_Pos             (23)                                              /*!< EADC_T::SCTL1: DBMEN Position          */
+#define EADC_SCTL1_DBMEN_Msk             (0x1ul << EADC_SCTL1_DBMEN_Pos)                   /*!< EADC_T::SCTL1: DBMEN Mask              */
+
+#define EADC_SCTL1_EXTSMPT_Pos           (24)                                              /*!< EADC_T::SCTL1: EXTSMPT Position        */
+#define EADC_SCTL1_EXTSMPT_Msk           (0xfful << EADC_SCTL1_EXTSMPT_Pos)                /*!< EADC_T::SCTL1: EXTSMPT Mask            */
+
+#define EADC_SCTL2_CHSEL_Pos             (0)                                               /*!< EADC_T::SCTL2: CHSEL Position          */
+#define EADC_SCTL2_CHSEL_Msk             (0xful << EADC_SCTL2_CHSEL_Pos)                   /*!< EADC_T::SCTL2: CHSEL Mask              */
+
+#define EADC_SCTL2_EXTREN_Pos            (4)                                               /*!< EADC_T::SCTL2: EXTREN Position         */
+#define EADC_SCTL2_EXTREN_Msk            (0x1ul << EADC_SCTL2_EXTREN_Pos)                  /*!< EADC_T::SCTL2: EXTREN Mask             */
+
+#define EADC_SCTL2_EXTFEN_Pos            (5)                                               /*!< EADC_T::SCTL2: EXTFEN Position         */
+#define EADC_SCTL2_EXTFEN_Msk            (0x1ul << EADC_SCTL2_EXTFEN_Pos)                  /*!< EADC_T::SCTL2: EXTFEN Mask             */
+
+#define EADC_SCTL2_TRGDLYDIV_Pos         (6)                                               /*!< EADC_T::SCTL2: TRGDLYDIV Position      */
+#define EADC_SCTL2_TRGDLYDIV_Msk         (0x3ul << EADC_SCTL2_TRGDLYDIV_Pos)               /*!< EADC_T::SCTL2: TRGDLYDIV Mask          */
+
+#define EADC_SCTL2_TRGDLYCNT_Pos         (8)                                               /*!< EADC_T::SCTL2: TRGDLYCNT Position      */
+#define EADC_SCTL2_TRGDLYCNT_Msk         (0xfful << EADC_SCTL2_TRGDLYCNT_Pos)              /*!< EADC_T::SCTL2: TRGDLYCNT Mask          */
+
+#define EADC_SCTL2_TRGSEL_Pos            (16)                                              /*!< EADC_T::SCTL2: TRGSEL Position         */
+#define EADC_SCTL2_TRGSEL_Msk            (0x1ful << EADC_SCTL2_TRGSEL_Pos)                 /*!< EADC_T::SCTL2: TRGSEL Mask             */
+
+#define EADC_SCTL2_INTPOS_Pos            (22)                                              /*!< EADC_T::SCTL2: INTPOS Position         */
+#define EADC_SCTL2_INTPOS_Msk            (0x1ul << EADC_SCTL2_INTPOS_Pos)                  /*!< EADC_T::SCTL2: INTPOS Mask             */
+
+#define EADC_SCTL2_DBMEN_Pos             (23)                                              /*!< EADC_T::SCTL2: DBMEN Position          */
+#define EADC_SCTL2_DBMEN_Msk             (0x1ul << EADC_SCTL2_DBMEN_Pos)                   /*!< EADC_T::SCTL2: DBMEN Mask              */
+
+#define EADC_SCTL2_EXTSMPT_Pos           (24)                                              /*!< EADC_T::SCTL2: EXTSMPT Position        */
+#define EADC_SCTL2_EXTSMPT_Msk           (0xfful << EADC_SCTL2_EXTSMPT_Pos)                /*!< EADC_T::SCTL2: EXTSMPT Mask            */
+
+#define EADC_SCTL3_CHSEL_Pos             (0)                                               /*!< EADC_T::SCTL3: CHSEL Position          */
+#define EADC_SCTL3_CHSEL_Msk             (0xful << EADC_SCTL3_CHSEL_Pos)                   /*!< EADC_T::SCTL3: CHSEL Mask              */
+
+#define EADC_SCTL3_EXTREN_Pos            (4)                                               /*!< EADC_T::SCTL3: EXTREN Position         */
+#define EADC_SCTL3_EXTREN_Msk            (0x1ul << EADC_SCTL3_EXTREN_Pos)                  /*!< EADC_T::SCTL3: EXTREN Mask             */
+
+#define EADC_SCTL3_EXTFEN_Pos            (5)                                               /*!< EADC_T::SCTL3: EXTFEN Position         */
+#define EADC_SCTL3_EXTFEN_Msk            (0x1ul << EADC_SCTL3_EXTFEN_Pos)                  /*!< EADC_T::SCTL3: EXTFEN Mask             */
+
+#define EADC_SCTL3_TRGDLYDIV_Pos         (6)                                               /*!< EADC_T::SCTL3: TRGDLYDIV Position      */
+#define EADC_SCTL3_TRGDLYDIV_Msk         (0x3ul << EADC_SCTL3_TRGDLYDIV_Pos)               /*!< EADC_T::SCTL3: TRGDLYDIV Mask          */
+
+#define EADC_SCTL3_TRGDLYCNT_Pos         (8)                                               /*!< EADC_T::SCTL3: TRGDLYCNT Position      */
+#define EADC_SCTL3_TRGDLYCNT_Msk         (0xfful << EADC_SCTL3_TRGDLYCNT_Pos)              /*!< EADC_T::SCTL3: TRGDLYCNT Mask          */
+
+#define EADC_SCTL3_TRGSEL_Pos            (16)                                              /*!< EADC_T::SCTL3: TRGSEL Position         */
+#define EADC_SCTL3_TRGSEL_Msk            (0x1ful << EADC_SCTL3_TRGSEL_Pos)                 /*!< EADC_T::SCTL3: TRGSEL Mask             */
+
+#define EADC_SCTL3_INTPOS_Pos            (22)                                              /*!< EADC_T::SCTL3: INTPOS Position         */
+#define EADC_SCTL3_INTPOS_Msk            (0x1ul << EADC_SCTL3_INTPOS_Pos)                  /*!< EADC_T::SCTL3: INTPOS Mask             */
+
+#define EADC_SCTL3_DBMEN_Pos             (23)                                              /*!< EADC_T::SCTL3: DBMEN Position          */
+#define EADC_SCTL3_DBMEN_Msk             (0x1ul << EADC_SCTL3_DBMEN_Pos)                   /*!< EADC_T::SCTL3: DBMEN Mask              */
+
+#define EADC_SCTL3_EXTSMPT_Pos           (24)                                              /*!< EADC_T::SCTL3: EXTSMPT Position        */
+#define EADC_SCTL3_EXTSMPT_Msk           (0xfful << EADC_SCTL3_EXTSMPT_Pos)                /*!< EADC_T::SCTL3: EXTSMPT Mask            */
+
+#define EADC_SCTL4_CHSEL_Pos             (0)                                               /*!< EADC_T::SCTL4: CHSEL Position          */
+#define EADC_SCTL4_CHSEL_Msk             (0xful << EADC_SCTL4_CHSEL_Pos)                   /*!< EADC_T::SCTL4: CHSEL Mask              */
+
+#define EADC_SCTL4_EXTREN_Pos            (4)                                               /*!< EADC_T::SCTL4: EXTREN Position         */
+#define EADC_SCTL4_EXTREN_Msk            (0x1ul << EADC_SCTL4_EXTREN_Pos)                  /*!< EADC_T::SCTL4: EXTREN Mask             */
+
+#define EADC_SCTL4_EXTFEN_Pos            (5)                                               /*!< EADC_T::SCTL4: EXTFEN Position         */
+#define EADC_SCTL4_EXTFEN_Msk            (0x1ul << EADC_SCTL4_EXTFEN_Pos)                  /*!< EADC_T::SCTL4: EXTFEN Mask             */
+
+#define EADC_SCTL4_TRGDLYDIV_Pos         (6)                                               /*!< EADC_T::SCTL4: TRGDLYDIV Position      */
+#define EADC_SCTL4_TRGDLYDIV_Msk         (0x3ul << EADC_SCTL4_TRGDLYDIV_Pos)               /*!< EADC_T::SCTL4: TRGDLYDIV Mask          */
+
+#define EADC_SCTL4_TRGDLYCNT_Pos         (8)                                               /*!< EADC_T::SCTL4: TRGDLYCNT Position      */
+#define EADC_SCTL4_TRGDLYCNT_Msk         (0xfful << EADC_SCTL4_TRGDLYCNT_Pos)              /*!< EADC_T::SCTL4: TRGDLYCNT Mask          */
+
+#define EADC_SCTL4_TRGSEL_Pos            (16)                                              /*!< EADC_T::SCTL4: TRGSEL Position         */
+#define EADC_SCTL4_TRGSEL_Msk            (0x1ful << EADC_SCTL4_TRGSEL_Pos)                 /*!< EADC_T::SCTL4: TRGSEL Mask             */
+
+#define EADC_SCTL4_INTPOS_Pos            (22)                                              /*!< EADC_T::SCTL4: INTPOS Position         */
+#define EADC_SCTL4_INTPOS_Msk            (0x1ul << EADC_SCTL4_INTPOS_Pos)                  /*!< EADC_T::SCTL4: INTPOS Mask             */
+
+#define EADC_SCTL4_EXTSMPT_Pos           (24)                                              /*!< EADC_T::SCTL4: EXTSMPT Position        */
+#define EADC_SCTL4_EXTSMPT_Msk           (0xfful << EADC_SCTL4_EXTSMPT_Pos)                /*!< EADC_T::SCTL4: EXTSMPT Mask            */
+
+#define EADC_SCTL5_CHSEL_Pos             (0)                                               /*!< EADC_T::SCTL5: CHSEL Position          */
+#define EADC_SCTL5_CHSEL_Msk             (0xful << EADC_SCTL5_CHSEL_Pos)                   /*!< EADC_T::SCTL5: CHSEL Mask              */
+
+#define EADC_SCTL5_EXTREN_Pos            (4)                                               /*!< EADC_T::SCTL5: EXTREN Position         */
+#define EADC_SCTL5_EXTREN_Msk            (0x1ul << EADC_SCTL5_EXTREN_Pos)                  /*!< EADC_T::SCTL5: EXTREN Mask             */
+
+#define EADC_SCTL5_EXTFEN_Pos            (5)                                               /*!< EADC_T::SCTL5: EXTFEN Position         */
+#define EADC_SCTL5_EXTFEN_Msk            (0x1ul << EADC_SCTL5_EXTFEN_Pos)                  /*!< EADC_T::SCTL5: EXTFEN Mask             */
+
+#define EADC_SCTL5_TRGDLYDIV_Pos         (6)                                               /*!< EADC_T::SCTL5: TRGDLYDIV Position      */
+#define EADC_SCTL5_TRGDLYDIV_Msk         (0x3ul << EADC_SCTL5_TRGDLYDIV_Pos)               /*!< EADC_T::SCTL5: TRGDLYDIV Mask          */
+
+#define EADC_SCTL5_TRGDLYCNT_Pos         (8)                                               /*!< EADC_T::SCTL5: TRGDLYCNT Position      */
+#define EADC_SCTL5_TRGDLYCNT_Msk         (0xfful << EADC_SCTL5_TRGDLYCNT_Pos)              /*!< EADC_T::SCTL5: TRGDLYCNT Mask          */
+
+#define EADC_SCTL5_TRGSEL_Pos            (16)                                              /*!< EADC_T::SCTL5: TRGSEL Position         */
+#define EADC_SCTL5_TRGSEL_Msk            (0x1ful << EADC_SCTL5_TRGSEL_Pos)                 /*!< EADC_T::SCTL5: TRGSEL Mask             */
+
+#define EADC_SCTL5_INTPOS_Pos            (22)                                              /*!< EADC_T::SCTL5: INTPOS Position         */
+#define EADC_SCTL5_INTPOS_Msk            (0x1ul << EADC_SCTL5_INTPOS_Pos)                  /*!< EADC_T::SCTL5: INTPOS Mask             */
+
+#define EADC_SCTL5_EXTSMPT_Pos           (24)                                              /*!< EADC_T::SCTL5: EXTSMPT Position        */
+#define EADC_SCTL5_EXTSMPT_Msk           (0xfful << EADC_SCTL5_EXTSMPT_Pos)                /*!< EADC_T::SCTL5: EXTSMPT Mask            */
+
+#define EADC_SCTL6_CHSEL_Pos             (0)                                               /*!< EADC_T::SCTL6: CHSEL Position          */
+#define EADC_SCTL6_CHSEL_Msk             (0xful << EADC_SCTL6_CHSEL_Pos)                   /*!< EADC_T::SCTL6: CHSEL Mask              */
+
+#define EADC_SCTL6_EXTREN_Pos            (4)                                               /*!< EADC_T::SCTL6: EXTREN Position         */
+#define EADC_SCTL6_EXTREN_Msk            (0x1ul << EADC_SCTL6_EXTREN_Pos)                  /*!< EADC_T::SCTL6: EXTREN Mask             */
+
+#define EADC_SCTL6_EXTFEN_Pos            (5)                                               /*!< EADC_T::SCTL6: EXTFEN Position         */
+#define EADC_SCTL6_EXTFEN_Msk            (0x1ul << EADC_SCTL6_EXTFEN_Pos)                  /*!< EADC_T::SCTL6: EXTFEN Mask             */
+
+#define EADC_SCTL6_TRGDLYDIV_Pos         (6)                                               /*!< EADC_T::SCTL6: TRGDLYDIV Position      */
+#define EADC_SCTL6_TRGDLYDIV_Msk         (0x3ul << EADC_SCTL6_TRGDLYDIV_Pos)               /*!< EADC_T::SCTL6: TRGDLYDIV Mask          */
+
+#define EADC_SCTL6_TRGDLYCNT_Pos         (8)                                               /*!< EADC_T::SCTL6: TRGDLYCNT Position      */
+#define EADC_SCTL6_TRGDLYCNT_Msk         (0xfful << EADC_SCTL6_TRGDLYCNT_Pos)              /*!< EADC_T::SCTL6: TRGDLYCNT Mask          */
+
+#define EADC_SCTL6_TRGSEL_Pos            (16)                                              /*!< EADC_T::SCTL6: TRGSEL Position         */
+#define EADC_SCTL6_TRGSEL_Msk            (0x1ful << EADC_SCTL6_TRGSEL_Pos)                 /*!< EADC_T::SCTL6: TRGSEL Mask             */
+
+#define EADC_SCTL6_INTPOS_Pos            (22)                                              /*!< EADC_T::SCTL6: INTPOS Position         */
+#define EADC_SCTL6_INTPOS_Msk            (0x1ul << EADC_SCTL6_INTPOS_Pos)                  /*!< EADC_T::SCTL6: INTPOS Mask             */
+
+#define EADC_SCTL6_EXTSMPT_Pos           (24)                                              /*!< EADC_T::SCTL6: EXTSMPT Position        */
+#define EADC_SCTL6_EXTSMPT_Msk           (0xfful << EADC_SCTL6_EXTSMPT_Pos)                /*!< EADC_T::SCTL6: EXTSMPT Mask            */
+
+#define EADC_SCTL7_CHSEL_Pos             (0)                                               /*!< EADC_T::SCTL7: CHSEL Position          */
+#define EADC_SCTL7_CHSEL_Msk             (0xful << EADC_SCTL7_CHSEL_Pos)                   /*!< EADC_T::SCTL7: CHSEL Mask              */
+
+#define EADC_SCTL7_EXTREN_Pos            (4)                                               /*!< EADC_T::SCTL7: EXTREN Position         */
+#define EADC_SCTL7_EXTREN_Msk            (0x1ul << EADC_SCTL7_EXTREN_Pos)                  /*!< EADC_T::SCTL7: EXTREN Mask             */
+
+#define EADC_SCTL7_EXTFEN_Pos            (5)                                               /*!< EADC_T::SCTL7: EXTFEN Position         */
+#define EADC_SCTL7_EXTFEN_Msk            (0x1ul << EADC_SCTL7_EXTFEN_Pos)                  /*!< EADC_T::SCTL7: EXTFEN Mask             */
+
+#define EADC_SCTL7_TRGDLYDIV_Pos         (6)                                               /*!< EADC_T::SCTL7: TRGDLYDIV Position      */
+#define EADC_SCTL7_TRGDLYDIV_Msk         (0x3ul << EADC_SCTL7_TRGDLYDIV_Pos)               /*!< EADC_T::SCTL7: TRGDLYDIV Mask          */
+
+#define EADC_SCTL7_TRGDLYCNT_Pos         (8)                                               /*!< EADC_T::SCTL7: TRGDLYCNT Position      */
+#define EADC_SCTL7_TRGDLYCNT_Msk         (0xfful << EADC_SCTL7_TRGDLYCNT_Pos)              /*!< EADC_T::SCTL7: TRGDLYCNT Mask          */
+
+#define EADC_SCTL7_TRGSEL_Pos            (16)                                              /*!< EADC_T::SCTL7: TRGSEL Position         */
+#define EADC_SCTL7_TRGSEL_Msk            (0x1ful << EADC_SCTL7_TRGSEL_Pos)                 /*!< EADC_T::SCTL7: TRGSEL Mask             */
+
+#define EADC_SCTL7_INTPOS_Pos            (22)                                              /*!< EADC_T::SCTL7: INTPOS Position         */
+#define EADC_SCTL7_INTPOS_Msk            (0x1ul << EADC_SCTL7_INTPOS_Pos)                  /*!< EADC_T::SCTL7: INTPOS Mask             */
+
+#define EADC_SCTL7_EXTSMPT_Pos           (24)                                              /*!< EADC_T::SCTL7: EXTSMPT Position        */
+#define EADC_SCTL7_EXTSMPT_Msk           (0xfful << EADC_SCTL7_EXTSMPT_Pos)                /*!< EADC_T::SCTL7: EXTSMPT Mask            */
+
+#define EADC_SCTL8_CHSEL_Pos             (0)                                               /*!< EADC_T::SCTL8: CHSEL Position          */
+#define EADC_SCTL8_CHSEL_Msk             (0xful << EADC_SCTL8_CHSEL_Pos)                   /*!< EADC_T::SCTL8: CHSEL Mask              */
+
+#define EADC_SCTL8_EXTREN_Pos            (4)                                               /*!< EADC_T::SCTL8: EXTREN Position         */
+#define EADC_SCTL8_EXTREN_Msk            (0x1ul << EADC_SCTL8_EXTREN_Pos)                  /*!< EADC_T::SCTL8: EXTREN Mask             */
+
+#define EADC_SCTL8_EXTFEN_Pos            (5)                                               /*!< EADC_T::SCTL8: EXTFEN Position         */
+#define EADC_SCTL8_EXTFEN_Msk            (0x1ul << EADC_SCTL8_EXTFEN_Pos)                  /*!< EADC_T::SCTL8: EXTFEN Mask             */
+
+#define EADC_SCTL8_TRGDLYDIV_Pos         (6)                                               /*!< EADC_T::SCTL8: TRGDLYDIV Position      */
+#define EADC_SCTL8_TRGDLYDIV_Msk         (0x3ul << EADC_SCTL8_TRGDLYDIV_Pos)               /*!< EADC_T::SCTL8: TRGDLYDIV Mask          */
+
+#define EADC_SCTL8_TRGDLYCNT_Pos         (8)                                               /*!< EADC_T::SCTL8: TRGDLYCNT Position      */
+#define EADC_SCTL8_TRGDLYCNT_Msk         (0xfful << EADC_SCTL8_TRGDLYCNT_Pos)              /*!< EADC_T::SCTL8: TRGDLYCNT Mask          */
+
+#define EADC_SCTL8_TRGSEL_Pos            (16)                                              /*!< EADC_T::SCTL8: TRGSEL Position         */
+#define EADC_SCTL8_TRGSEL_Msk            (0x1ful << EADC_SCTL8_TRGSEL_Pos)                 /*!< EADC_T::SCTL8: TRGSEL Mask             */
+
+#define EADC_SCTL8_INTPOS_Pos            (22)                                              /*!< EADC_T::SCTL8: INTPOS Position         */
+#define EADC_SCTL8_INTPOS_Msk            (0x1ul << EADC_SCTL8_INTPOS_Pos)                  /*!< EADC_T::SCTL8: INTPOS Mask             */
+
+#define EADC_SCTL8_EXTSMPT_Pos           (24)                                              /*!< EADC_T::SCTL8: EXTSMPT Position        */
+#define EADC_SCTL8_EXTSMPT_Msk           (0xfful << EADC_SCTL8_EXTSMPT_Pos)                /*!< EADC_T::SCTL8: EXTSMPT Mask            */
+
+#define EADC_SCTL9_CHSEL_Pos             (0)                                               /*!< EADC_T::SCTL9: CHSEL Position          */
+#define EADC_SCTL9_CHSEL_Msk             (0xful << EADC_SCTL9_CHSEL_Pos)                   /*!< EADC_T::SCTL9: CHSEL Mask              */
+
+#define EADC_SCTL9_EXTREN_Pos            (4)                                               /*!< EADC_T::SCTL9: EXTREN Position         */
+#define EADC_SCTL9_EXTREN_Msk            (0x1ul << EADC_SCTL9_EXTREN_Pos)                  /*!< EADC_T::SCTL9: EXTREN Mask             */
+
+#define EADC_SCTL9_EXTFEN_Pos            (5)                                               /*!< EADC_T::SCTL9: EXTFEN Position         */
+#define EADC_SCTL9_EXTFEN_Msk            (0x1ul << EADC_SCTL9_EXTFEN_Pos)                  /*!< EADC_T::SCTL9: EXTFEN Mask             */
+
+#define EADC_SCTL9_TRGDLYDIV_Pos         (6)                                               /*!< EADC_T::SCTL9: TRGDLYDIV Position      */
+#define EADC_SCTL9_TRGDLYDIV_Msk         (0x3ul << EADC_SCTL9_TRGDLYDIV_Pos)               /*!< EADC_T::SCTL9: TRGDLYDIV Mask          */
+
+#define EADC_SCTL9_TRGDLYCNT_Pos         (8)                                               /*!< EADC_T::SCTL9: TRGDLYCNT Position      */
+#define EADC_SCTL9_TRGDLYCNT_Msk         (0xfful << EADC_SCTL9_TRGDLYCNT_Pos)              /*!< EADC_T::SCTL9: TRGDLYCNT Mask          */
+
+#define EADC_SCTL9_TRGSEL_Pos            (16)                                              /*!< EADC_T::SCTL9: TRGSEL Position         */
+#define EADC_SCTL9_TRGSEL_Msk            (0x1ful << EADC_SCTL9_TRGSEL_Pos)                 /*!< EADC_T::SCTL9: TRGSEL Mask             */
+
+#define EADC_SCTL9_INTPOS_Pos            (22)                                              /*!< EADC_T::SCTL9: INTPOS Position         */
+#define EADC_SCTL9_INTPOS_Msk            (0x1ul << EADC_SCTL9_INTPOS_Pos)                  /*!< EADC_T::SCTL9: INTPOS Mask             */
+
+#define EADC_SCTL9_EXTSMPT_Pos           (24)                                              /*!< EADC_T::SCTL9: EXTSMPT Position        */
+#define EADC_SCTL9_EXTSMPT_Msk           (0xfful << EADC_SCTL9_EXTSMPT_Pos)                /*!< EADC_T::SCTL9: EXTSMPT Mask            */
+
+#define EADC_SCTL10_CHSEL_Pos            (0)                                               /*!< EADC_T::SCTL10: CHSEL Position         */
+#define EADC_SCTL10_CHSEL_Msk            (0xful << EADC_SCTL10_CHSEL_Pos)                  /*!< EADC_T::SCTL10: CHSEL Mask             */
+
+#define EADC_SCTL10_EXTREN_Pos           (4)                                               /*!< EADC_T::SCTL10: EXTREN Position        */
+#define EADC_SCTL10_EXTREN_Msk           (0x1ul << EADC_SCTL10_EXTREN_Pos)                 /*!< EADC_T::SCTL10: EXTREN Mask            */
+
+#define EADC_SCTL10_EXTFEN_Pos           (5)                                               /*!< EADC_T::SCTL10: EXTFEN Position        */
+#define EADC_SCTL10_EXTFEN_Msk           (0x1ul << EADC_SCTL10_EXTFEN_Pos)                 /*!< EADC_T::SCTL10: EXTFEN Mask            */
+
+#define EADC_SCTL10_TRGDLYDIV_Pos        (6)                                               /*!< EADC_T::SCTL10: TRGDLYDIV Position     */
+#define EADC_SCTL10_TRGDLYDIV_Msk        (0x3ul << EADC_SCTL10_TRGDLYDIV_Pos)              /*!< EADC_T::SCTL10: TRGDLYDIV Mask         */
+
+#define EADC_SCTL10_TRGDLYCNT_Pos        (8)                                               /*!< EADC_T::SCTL10: TRGDLYCNT Position     */
+#define EADC_SCTL10_TRGDLYCNT_Msk        (0xfful << EADC_SCTL10_TRGDLYCNT_Pos)             /*!< EADC_T::SCTL10: TRGDLYCNT Mask         */
+
+#define EADC_SCTL10_TRGSEL_Pos           (16)                                              /*!< EADC_T::SCTL10: TRGSEL Position        */
+#define EADC_SCTL10_TRGSEL_Msk           (0x1ful << EADC_SCTL10_TRGSEL_Pos)                /*!< EADC_T::SCTL10: TRGSEL Mask            */
+
+#define EADC_SCTL10_INTPOS_Pos           (22)                                              /*!< EADC_T::SCTL10: INTPOS Position        */
+#define EADC_SCTL10_INTPOS_Msk           (0x1ul << EADC_SCTL10_INTPOS_Pos)                 /*!< EADC_T::SCTL10: INTPOS Mask            */
+
+#define EADC_SCTL10_EXTSMPT_Pos          (24)                                              /*!< EADC_T::SCTL10: EXTSMPT Position       */
+#define EADC_SCTL10_EXTSMPT_Msk          (0xfful << EADC_SCTL10_EXTSMPT_Pos)               /*!< EADC_T::SCTL10: EXTSMPT Mask           */
+
+#define EADC_SCTL11_CHSEL_Pos            (0)                                               /*!< EADC_T::SCTL11: CHSEL Position         */
+#define EADC_SCTL11_CHSEL_Msk            (0xful << EADC_SCTL11_CHSEL_Pos)                  /*!< EADC_T::SCTL11: CHSEL Mask             */
+
+#define EADC_SCTL11_EXTREN_Pos           (4)                                               /*!< EADC_T::SCTL11: EXTREN Position        */
+#define EADC_SCTL11_EXTREN_Msk           (0x1ul << EADC_SCTL11_EXTREN_Pos)                 /*!< EADC_T::SCTL11: EXTREN Mask            */
+
+#define EADC_SCTL11_EXTFEN_Pos           (5)                                               /*!< EADC_T::SCTL11: EXTFEN Position        */
+#define EADC_SCTL11_EXTFEN_Msk           (0x1ul << EADC_SCTL11_EXTFEN_Pos)                 /*!< EADC_T::SCTL11: EXTFEN Mask            */
+
+#define EADC_SCTL11_TRGDLYDIV_Pos        (6)                                               /*!< EADC_T::SCTL11: TRGDLYDIV Position     */
+#define EADC_SCTL11_TRGDLYDIV_Msk        (0x3ul << EADC_SCTL11_TRGDLYDIV_Pos)              /*!< EADC_T::SCTL11: TRGDLYDIV Mask         */
+
+#define EADC_SCTL11_TRGDLYCNT_Pos        (8)                                               /*!< EADC_T::SCTL11: TRGDLYCNT Position     */
+#define EADC_SCTL11_TRGDLYCNT_Msk        (0xfful << EADC_SCTL11_TRGDLYCNT_Pos)             /*!< EADC_T::SCTL11: TRGDLYCNT Mask         */
+
+#define EADC_SCTL11_TRGSEL_Pos           (16)                                              /*!< EADC_T::SCTL11: TRGSEL Position        */
+#define EADC_SCTL11_TRGSEL_Msk           (0x1ful << EADC_SCTL11_TRGSEL_Pos)                /*!< EADC_T::SCTL11: TRGSEL Mask            */
+
+#define EADC_SCTL11_INTPOS_Pos           (22)                                              /*!< EADC_T::SCTL11: INTPOS Position        */
+#define EADC_SCTL11_INTPOS_Msk           (0x1ul << EADC_SCTL11_INTPOS_Pos)                 /*!< EADC_T::SCTL11: INTPOS Mask            */
+
+#define EADC_SCTL11_EXTSMPT_Pos          (24)                                              /*!< EADC_T::SCTL11: EXTSMPT Position       */
+#define EADC_SCTL11_EXTSMPT_Msk          (0xfful << EADC_SCTL11_EXTSMPT_Pos)               /*!< EADC_T::SCTL11: EXTSMPT Mask           */
+
+#define EADC_SCTL12_CHSEL_Pos            (0)                                               /*!< EADC_T::SCTL12: CHSEL Position         */
+#define EADC_SCTL12_CHSEL_Msk            (0xful << EADC_SCTL12_CHSEL_Pos)                  /*!< EADC_T::SCTL12: CHSEL Mask             */
+
+#define EADC_SCTL12_EXTREN_Pos           (4)                                               /*!< EADC_T::SCTL12: EXTREN Position        */
+#define EADC_SCTL12_EXTREN_Msk           (0x1ul << EADC_SCTL12_EXTREN_Pos)                 /*!< EADC_T::SCTL12: EXTREN Mask            */
+
+#define EADC_SCTL12_EXTFEN_Pos           (5)                                               /*!< EADC_T::SCTL12: EXTFEN Position        */
+#define EADC_SCTL12_EXTFEN_Msk           (0x1ul << EADC_SCTL12_EXTFEN_Pos)                 /*!< EADC_T::SCTL12: EXTFEN Mask            */
+
+#define EADC_SCTL12_TRGDLYDIV_Pos        (6)                                               /*!< EADC_T::SCTL12: TRGDLYDIV Position     */
+#define EADC_SCTL12_TRGDLYDIV_Msk        (0x3ul << EADC_SCTL12_TRGDLYDIV_Pos)              /*!< EADC_T::SCTL12: TRGDLYDIV Mask         */
+
+#define EADC_SCTL12_TRGDLYCNT_Pos        (8)                                               /*!< EADC_T::SCTL12: TRGDLYCNT Position     */
+#define EADC_SCTL12_TRGDLYCNT_Msk        (0xfful << EADC_SCTL12_TRGDLYCNT_Pos)             /*!< EADC_T::SCTL12: TRGDLYCNT Mask         */
+
+#define EADC_SCTL12_TRGSEL_Pos           (16)                                              /*!< EADC_T::SCTL12: TRGSEL Position        */
+#define EADC_SCTL12_TRGSEL_Msk           (0x1ful << EADC_SCTL12_TRGSEL_Pos)                /*!< EADC_T::SCTL12: TRGSEL Mask            */
+
+#define EADC_SCTL12_INTPOS_Pos           (22)                                              /*!< EADC_T::SCTL12: INTPOS Position        */
+#define EADC_SCTL12_INTPOS_Msk           (0x1ul << EADC_SCTL12_INTPOS_Pos)                 /*!< EADC_T::SCTL12: INTPOS Mask            */
+
+#define EADC_SCTL12_EXTSMPT_Pos          (24)                                              /*!< EADC_T::SCTL12: EXTSMPT Position       */
+#define EADC_SCTL12_EXTSMPT_Msk          (0xfful << EADC_SCTL12_EXTSMPT_Pos)               /*!< EADC_T::SCTL12: EXTSMPT Mask           */
+
+#define EADC_SCTL13_CHSEL_Pos            (0)                                               /*!< EADC_T::SCTL13: CHSEL Position         */
+#define EADC_SCTL13_CHSEL_Msk            (0xful << EADC_SCTL13_CHSEL_Pos)                  /*!< EADC_T::SCTL13: CHSEL Mask             */
+
+#define EADC_SCTL13_EXTREN_Pos           (4)                                               /*!< EADC_T::SCTL13: EXTREN Position        */
+#define EADC_SCTL13_EXTREN_Msk           (0x1ul << EADC_SCTL13_EXTREN_Pos)                 /*!< EADC_T::SCTL13: EXTREN Mask            */
+
+#define EADC_SCTL13_EXTFEN_Pos           (5)                                               /*!< EADC_T::SCTL13: EXTFEN Position        */
+#define EADC_SCTL13_EXTFEN_Msk           (0x1ul << EADC_SCTL13_EXTFEN_Pos)                 /*!< EADC_T::SCTL13: EXTFEN Mask            */
+
+#define EADC_SCTL13_TRGDLYDIV_Pos        (6)                                               /*!< EADC_T::SCTL13: TRGDLYDIV Position     */
+#define EADC_SCTL13_TRGDLYDIV_Msk        (0x3ul << EADC_SCTL13_TRGDLYDIV_Pos)              /*!< EADC_T::SCTL13: TRGDLYDIV Mask         */
+
+#define EADC_SCTL13_TRGDLYCNT_Pos        (8)                                               /*!< EADC_T::SCTL13: TRGDLYCNT Position     */
+#define EADC_SCTL13_TRGDLYCNT_Msk        (0xfful << EADC_SCTL13_TRGDLYCNT_Pos)             /*!< EADC_T::SCTL13: TRGDLYCNT Mask         */
+
+#define EADC_SCTL13_TRGSEL_Pos           (16)                                              /*!< EADC_T::SCTL13: TRGSEL Position        */
+#define EADC_SCTL13_TRGSEL_Msk           (0x1ful << EADC_SCTL13_TRGSEL_Pos)                /*!< EADC_T::SCTL13: TRGSEL Mask            */
+
+#define EADC_SCTL13_INTPOS_Pos           (22)                                              /*!< EADC_T::SCTL13: INTPOS Position        */
+#define EADC_SCTL13_INTPOS_Msk           (0x1ul << EADC_SCTL13_INTPOS_Pos)                 /*!< EADC_T::SCTL13: INTPOS Mask            */
+
+#define EADC_SCTL13_EXTSMPT_Pos          (24)                                              /*!< EADC_T::SCTL13: EXTSMPT Position       */
+#define EADC_SCTL13_EXTSMPT_Msk          (0xfful << EADC_SCTL13_EXTSMPT_Pos)               /*!< EADC_T::SCTL13: EXTSMPT Mask           */
+
+#define EADC_SCTL14_CHSEL_Pos            (0)                                               /*!< EADC_T::SCTL14: CHSEL Position         */
+#define EADC_SCTL14_CHSEL_Msk            (0xful << EADC_SCTL14_CHSEL_Pos)                  /*!< EADC_T::SCTL14: CHSEL Mask             */
+
+#define EADC_SCTL14_EXTREN_Pos           (4)                                               /*!< EADC_T::SCTL14: EXTREN Position        */
+#define EADC_SCTL14_EXTREN_Msk           (0x1ul << EADC_SCTL14_EXTREN_Pos)                 /*!< EADC_T::SCTL14: EXTREN Mask            */
+
+#define EADC_SCTL14_EXTFEN_Pos           (5)                                               /*!< EADC_T::SCTL14: EXTFEN Position        */
+#define EADC_SCTL14_EXTFEN_Msk           (0x1ul << EADC_SCTL14_EXTFEN_Pos)                 /*!< EADC_T::SCTL14: EXTFEN Mask            */
+
+#define EADC_SCTL14_TRGDLYDIV_Pos        (6)                                               /*!< EADC_T::SCTL14: TRGDLYDIV Position     */
+#define EADC_SCTL14_TRGDLYDIV_Msk        (0x3ul << EADC_SCTL14_TRGDLYDIV_Pos)              /*!< EADC_T::SCTL14: TRGDLYDIV Mask         */
+
+#define EADC_SCTL14_TRGDLYCNT_Pos        (8)                                               /*!< EADC_T::SCTL14: TRGDLYCNT Position     */
+#define EADC_SCTL14_TRGDLYCNT_Msk        (0xfful << EADC_SCTL14_TRGDLYCNT_Pos)             /*!< EADC_T::SCTL14: TRGDLYCNT Mask         */
+
+#define EADC_SCTL14_TRGSEL_Pos           (16)                                              /*!< EADC_T::SCTL14: TRGSEL Position        */
+#define EADC_SCTL14_TRGSEL_Msk           (0x1ful << EADC_SCTL14_TRGSEL_Pos)                /*!< EADC_T::SCTL14: TRGSEL Mask            */
+
+#define EADC_SCTL14_INTPOS_Pos           (22)                                              /*!< EADC_T::SCTL14: INTPOS Position        */
+#define EADC_SCTL14_INTPOS_Msk           (0x1ul << EADC_SCTL14_INTPOS_Pos)                 /*!< EADC_T::SCTL14: INTPOS Mask            */
+
+#define EADC_SCTL14_EXTSMPT_Pos          (24)                                              /*!< EADC_T::SCTL14: EXTSMPT Position       */
+#define EADC_SCTL14_EXTSMPT_Msk          (0xfful << EADC_SCTL14_EXTSMPT_Pos)               /*!< EADC_T::SCTL14: EXTSMPT Mask           */
+
+#define EADC_SCTL15_CHSEL_Pos            (0)                                               /*!< EADC_T::SCTL15: CHSEL Position         */
+#define EADC_SCTL15_CHSEL_Msk            (0xful << EADC_SCTL15_CHSEL_Pos)                  /*!< EADC_T::SCTL15: CHSEL Mask             */
+
+#define EADC_SCTL15_EXTREN_Pos           (4)                                               /*!< EADC_T::SCTL15: EXTREN Position        */
+#define EADC_SCTL15_EXTREN_Msk           (0x1ul << EADC_SCTL15_EXTREN_Pos)                 /*!< EADC_T::SCTL15: EXTREN Mask            */
+
+#define EADC_SCTL15_EXTFEN_Pos           (5)                                               /*!< EADC_T::SCTL15: EXTFEN Position        */
+#define EADC_SCTL15_EXTFEN_Msk           (0x1ul << EADC_SCTL15_EXTFEN_Pos)                 /*!< EADC_T::SCTL15: EXTFEN Mask            */
+
+#define EADC_SCTL15_TRGDLYDIV_Pos        (6)                                               /*!< EADC_T::SCTL15: TRGDLYDIV Position     */
+#define EADC_SCTL15_TRGDLYDIV_Msk        (0x3ul << EADC_SCTL15_TRGDLYDIV_Pos)              /*!< EADC_T::SCTL15: TRGDLYDIV Mask         */
+
+#define EADC_SCTL15_TRGDLYCNT_Pos        (8)                                               /*!< EADC_T::SCTL15: TRGDLYCNT Position     */
+#define EADC_SCTL15_TRGDLYCNT_Msk        (0xfful << EADC_SCTL15_TRGDLYCNT_Pos)             /*!< EADC_T::SCTL15: TRGDLYCNT Mask         */
+
+#define EADC_SCTL15_TRGSEL_Pos           (16)                                              /*!< EADC_T::SCTL15: TRGSEL Position        */
+#define EADC_SCTL15_TRGSEL_Msk           (0x1ful << EADC_SCTL15_TRGSEL_Pos)                /*!< EADC_T::SCTL15: TRGSEL Mask            */
+
+#define EADC_SCTL15_INTPOS_Pos           (22)                                              /*!< EADC_T::SCTL15: INTPOS Position        */
+#define EADC_SCTL15_INTPOS_Msk           (0x1ul << EADC_SCTL15_INTPOS_Pos)                 /*!< EADC_T::SCTL15: INTPOS Mask            */
+
+#define EADC_SCTL15_EXTSMPT_Pos          (24)                                              /*!< EADC_T::SCTL15: EXTSMPT Position       */
+#define EADC_SCTL15_EXTSMPT_Msk          (0xfful << EADC_SCTL15_EXTSMPT_Pos)               /*!< EADC_T::SCTL15: EXTSMPT Mask           */
+
+#define EADC_SCTL16_EXTSMPT_Pos          (24)                                              /*!< EADC_T::SCTL16: EXTSMPT Position       */
+#define EADC_SCTL16_EXTSMPT_Msk          (0xfful << EADC_SCTL16_EXTSMPT_Pos)               /*!< EADC_T::SCTL16: EXTSMPT Mask           */
+
+#define EADC_SCTL17_EXTSMPT_Pos          (24)                                              /*!< EADC_T::SCTL17: EXTSMPT Position       */
+#define EADC_SCTL17_EXTSMPT_Msk          (0xfful << EADC_SCTL17_EXTSMPT_Pos)               /*!< EADC_T::SCTL17: EXTSMPT Mask           */
+
+#define EADC_SCTL18_EXTSMPT_Pos          (24)                                              /*!< EADC_T::SCTL18: EXTSMPT Position       */
+#define EADC_SCTL18_EXTSMPT_Msk          (0xfful << EADC_SCTL18_EXTSMPT_Pos)               /*!< EADC_T::SCTL18: EXTSMPT Mask           */
+
+#define EADC_INTSRC0_SPLIE0_Pos          (0)                                               /*!< EADC_T::INTSRC0: SPLIE0 Position       */
+#define EADC_INTSRC0_SPLIE0_Msk          (0x1ul << EADC_INTSRC0_SPLIE0_Pos)                /*!< EADC_T::INTSRC0: SPLIE0 Mask           */
+
+#define EADC_INTSRC0_SPLIE1_Pos          (1)                                               /*!< EADC_T::INTSRC0: SPLIE1 Position       */
+#define EADC_INTSRC0_SPLIE1_Msk          (0x1ul << EADC_INTSRC0_SPLIE1_Pos)                /*!< EADC_T::INTSRC0: SPLIE1 Mask           */
+
+#define EADC_INTSRC0_SPLIE2_Pos          (2)                                               /*!< EADC_T::INTSRC0: SPLIE2 Position       */
+#define EADC_INTSRC0_SPLIE2_Msk          (0x1ul << EADC_INTSRC0_SPLIE2_Pos)                /*!< EADC_T::INTSRC0: SPLIE2 Mask           */
+
+#define EADC_INTSRC0_SPLIE3_Pos          (3)                                               /*!< EADC_T::INTSRC0: SPLIE3 Position       */
+#define EADC_INTSRC0_SPLIE3_Msk          (0x1ul << EADC_INTSRC0_SPLIE3_Pos)                /*!< EADC_T::INTSRC0: SPLIE3 Mask           */
+
+#define EADC_INTSRC0_SPLIE4_Pos          (4)                                               /*!< EADC_T::INTSRC0: SPLIE4 Position       */
+#define EADC_INTSRC0_SPLIE4_Msk          (0x1ul << EADC_INTSRC0_SPLIE4_Pos)                /*!< EADC_T::INTSRC0: SPLIE4 Mask           */
+
+#define EADC_INTSRC0_SPLIE5_Pos          (5)                                               /*!< EADC_T::INTSRC0: SPLIE5 Position       */
+#define EADC_INTSRC0_SPLIE5_Msk          (0x1ul << EADC_INTSRC0_SPLIE5_Pos)                /*!< EADC_T::INTSRC0: SPLIE5 Mask           */
+
+#define EADC_INTSRC0_SPLIE6_Pos          (6)                                               /*!< EADC_T::INTSRC0: SPLIE6 Position       */
+#define EADC_INTSRC0_SPLIE6_Msk          (0x1ul << EADC_INTSRC0_SPLIE6_Pos)                /*!< EADC_T::INTSRC0: SPLIE6 Mask           */
+
+#define EADC_INTSRC0_SPLIE7_Pos          (7)                                               /*!< EADC_T::INTSRC0: SPLIE7 Position       */
+#define EADC_INTSRC0_SPLIE7_Msk          (0x1ul << EADC_INTSRC0_SPLIE7_Pos)                /*!< EADC_T::INTSRC0: SPLIE7 Mask           */
+
+#define EADC_INTSRC0_SPLIE8_Pos          (8)                                               /*!< EADC_T::INTSRC0: SPLIE8 Position       */
+#define EADC_INTSRC0_SPLIE8_Msk          (0x1ul << EADC_INTSRC0_SPLIE8_Pos)                /*!< EADC_T::INTSRC0: SPLIE8 Mask           */
+
+#define EADC_INTSRC0_SPLIE9_Pos          (9)                                               /*!< EADC_T::INTSRC0: SPLIE9 Position       */
+#define EADC_INTSRC0_SPLIE9_Msk          (0x1ul << EADC_INTSRC0_SPLIE9_Pos)                /*!< EADC_T::INTSRC0: SPLIE9 Mask           */
+
+#define EADC_INTSRC0_SPLIE10_Pos         (10)                                              /*!< EADC_T::INTSRC0: SPLIE10 Position      */
+#define EADC_INTSRC0_SPLIE10_Msk         (0x1ul << EADC_INTSRC0_SPLIE10_Pos)               /*!< EADC_T::INTSRC0: SPLIE10 Mask          */
+
+#define EADC_INTSRC0_SPLIE11_Pos         (11)                                              /*!< EADC_T::INTSRC0: SPLIE11 Position      */
+#define EADC_INTSRC0_SPLIE11_Msk         (0x1ul << EADC_INTSRC0_SPLIE11_Pos)               /*!< EADC_T::INTSRC0: SPLIE11 Mask          */
+
+#define EADC_INTSRC0_SPLIE12_Pos         (12)                                              /*!< EADC_T::INTSRC0: SPLIE12 Position      */
+#define EADC_INTSRC0_SPLIE12_Msk         (0x1ul << EADC_INTSRC0_SPLIE12_Pos)               /*!< EADC_T::INTSRC0: SPLIE12 Mask          */
+
+#define EADC_INTSRC0_SPLIE13_Pos         (13)                                              /*!< EADC_T::INTSRC0: SPLIE13 Position      */
+#define EADC_INTSRC0_SPLIE13_Msk         (0x1ul << EADC_INTSRC0_SPLIE13_Pos)               /*!< EADC_T::INTSRC0: SPLIE13 Mask          */
+
+#define EADC_INTSRC0_SPLIE14_Pos         (14)                                              /*!< EADC_T::INTSRC0: SPLIE14 Position      */
+#define EADC_INTSRC0_SPLIE14_Msk         (0x1ul << EADC_INTSRC0_SPLIE14_Pos)               /*!< EADC_T::INTSRC0: SPLIE14 Mask          */
+
+#define EADC_INTSRC0_SPLIE15_Pos         (15)                                              /*!< EADC_T::INTSRC0: SPLIE15 Position      */
+#define EADC_INTSRC0_SPLIE15_Msk         (0x1ul << EADC_INTSRC0_SPLIE15_Pos)               /*!< EADC_T::INTSRC0: SPLIE15 Mask          */
+
+#define EADC_INTSRC0_SPLIE16_Pos         (16)                                              /*!< EADC_T::INTSRC0: SPLIE16 Position      */
+#define EADC_INTSRC0_SPLIE16_Msk         (0x1ul << EADC_INTSRC0_SPLIE16_Pos)               /*!< EADC_T::INTSRC0: SPLIE16 Mask          */
+
+#define EADC_INTSRC0_SPLIE17_Pos         (17)                                              /*!< EADC_T::INTSRC0: SPLIE17 Position      */
+#define EADC_INTSRC0_SPLIE17_Msk         (0x1ul << EADC_INTSRC0_SPLIE17_Pos)               /*!< EADC_T::INTSRC0: SPLIE17 Mask          */
+
+#define EADC_INTSRC0_SPLIE18_Pos         (18)                                              /*!< EADC_T::INTSRC0: SPLIE18 Position      */
+#define EADC_INTSRC0_SPLIE18_Msk         (0x1ul << EADC_INTSRC0_SPLIE18_Pos)               /*!< EADC_T::INTSRC0: SPLIE18 Mask          */
+
+#define EADC_INTSRC1_SPLIE0_Pos          (0)                                               /*!< EADC_T::INTSRC1: SPLIE0 Position       */
+#define EADC_INTSRC1_SPLIE0_Msk          (0x1ul << EADC_INTSRC1_SPLIE0_Pos)                /*!< EADC_T::INTSRC1: SPLIE0 Mask           */
+
+#define EADC_INTSRC1_SPLIE1_Pos          (1)                                               /*!< EADC_T::INTSRC1: SPLIE1 Position       */
+#define EADC_INTSRC1_SPLIE1_Msk          (0x1ul << EADC_INTSRC1_SPLIE1_Pos)                /*!< EADC_T::INTSRC1: SPLIE1 Mask           */
+
+#define EADC_INTSRC1_SPLIE2_Pos          (2)                                               /*!< EADC_T::INTSRC1: SPLIE2 Position       */
+#define EADC_INTSRC1_SPLIE2_Msk          (0x1ul << EADC_INTSRC1_SPLIE2_Pos)                /*!< EADC_T::INTSRC1: SPLIE2 Mask           */
+
+#define EADC_INTSRC1_SPLIE3_Pos          (3)                                               /*!< EADC_T::INTSRC1: SPLIE3 Position       */
+#define EADC_INTSRC1_SPLIE3_Msk          (0x1ul << EADC_INTSRC1_SPLIE3_Pos)                /*!< EADC_T::INTSRC1: SPLIE3 Mask           */
+
+#define EADC_INTSRC1_SPLIE4_Pos          (4)                                               /*!< EADC_T::INTSRC1: SPLIE4 Position       */
+#define EADC_INTSRC1_SPLIE4_Msk          (0x1ul << EADC_INTSRC1_SPLIE4_Pos)                /*!< EADC_T::INTSRC1: SPLIE4 Mask           */
+
+#define EADC_INTSRC1_SPLIE5_Pos          (5)                                               /*!< EADC_T::INTSRC1: SPLIE5 Position       */
+#define EADC_INTSRC1_SPLIE5_Msk          (0x1ul << EADC_INTSRC1_SPLIE5_Pos)                /*!< EADC_T::INTSRC1: SPLIE5 Mask           */
+
+#define EADC_INTSRC1_SPLIE6_Pos          (6)                                               /*!< EADC_T::INTSRC1: SPLIE6 Position       */
+#define EADC_INTSRC1_SPLIE6_Msk          (0x1ul << EADC_INTSRC1_SPLIE6_Pos)                /*!< EADC_T::INTSRC1: SPLIE6 Mask           */
+
+#define EADC_INTSRC1_SPLIE7_Pos          (7)                                               /*!< EADC_T::INTSRC1: SPLIE7 Position       */
+#define EADC_INTSRC1_SPLIE7_Msk          (0x1ul << EADC_INTSRC1_SPLIE7_Pos)                /*!< EADC_T::INTSRC1: SPLIE7 Mask           */
+
+#define EADC_INTSRC1_SPLIE8_Pos          (8)                                               /*!< EADC_T::INTSRC1: SPLIE8 Position       */
+#define EADC_INTSRC1_SPLIE8_Msk          (0x1ul << EADC_INTSRC1_SPLIE8_Pos)                /*!< EADC_T::INTSRC1: SPLIE8 Mask           */
+
+#define EADC_INTSRC1_SPLIE9_Pos          (9)                                               /*!< EADC_T::INTSRC1: SPLIE9 Position       */
+#define EADC_INTSRC1_SPLIE9_Msk          (0x1ul << EADC_INTSRC1_SPLIE9_Pos)                /*!< EADC_T::INTSRC1: SPLIE9 Mask           */
+
+#define EADC_INTSRC1_SPLIE10_Pos         (10)                                              /*!< EADC_T::INTSRC1: SPLIE10 Position      */
+#define EADC_INTSRC1_SPLIE10_Msk         (0x1ul << EADC_INTSRC1_SPLIE10_Pos)               /*!< EADC_T::INTSRC1: SPLIE10 Mask          */
+
+#define EADC_INTSRC1_SPLIE11_Pos         (11)                                              /*!< EADC_T::INTSRC1: SPLIE11 Position      */
+#define EADC_INTSRC1_SPLIE11_Msk         (0x1ul << EADC_INTSRC1_SPLIE11_Pos)               /*!< EADC_T::INTSRC1: SPLIE11 Mask          */
+
+#define EADC_INTSRC1_SPLIE12_Pos         (12)                                              /*!< EADC_T::INTSRC1: SPLIE12 Position      */
+#define EADC_INTSRC1_SPLIE12_Msk         (0x1ul << EADC_INTSRC1_SPLIE12_Pos)               /*!< EADC_T::INTSRC1: SPLIE12 Mask          */
+
+#define EADC_INTSRC1_SPLIE13_Pos         (13)                                              /*!< EADC_T::INTSRC1: SPLIE13 Position      */
+#define EADC_INTSRC1_SPLIE13_Msk         (0x1ul << EADC_INTSRC1_SPLIE13_Pos)               /*!< EADC_T::INTSRC1: SPLIE13 Mask          */
+
+#define EADC_INTSRC1_SPLIE14_Pos         (14)                                              /*!< EADC_T::INTSRC1: SPLIE14 Position      */
+#define EADC_INTSRC1_SPLIE14_Msk         (0x1ul << EADC_INTSRC1_SPLIE14_Pos)               /*!< EADC_T::INTSRC1: SPLIE14 Mask          */
+
+#define EADC_INTSRC1_SPLIE15_Pos         (15)                                              /*!< EADC_T::INTSRC1: SPLIE15 Position      */
+#define EADC_INTSRC1_SPLIE15_Msk         (0x1ul << EADC_INTSRC1_SPLIE15_Pos)               /*!< EADC_T::INTSRC1: SPLIE15 Mask          */
+
+#define EADC_INTSRC1_SPLIE16_Pos         (16)                                              /*!< EADC_T::INTSRC1: SPLIE16 Position      */
+#define EADC_INTSRC1_SPLIE16_Msk         (0x1ul << EADC_INTSRC1_SPLIE16_Pos)               /*!< EADC_T::INTSRC1: SPLIE16 Mask          */
+
+#define EADC_INTSRC1_SPLIE17_Pos         (17)                                              /*!< EADC_T::INTSRC1: SPLIE17 Position      */
+#define EADC_INTSRC1_SPLIE17_Msk         (0x1ul << EADC_INTSRC1_SPLIE17_Pos)               /*!< EADC_T::INTSRC1: SPLIE17 Mask          */
+
+#define EADC_INTSRC1_SPLIE18_Pos         (18)                                              /*!< EADC_T::INTSRC1: SPLIE18 Position      */
+#define EADC_INTSRC1_SPLIE18_Msk         (0x1ul << EADC_INTSRC1_SPLIE18_Pos)               /*!< EADC_T::INTSRC1: SPLIE18 Mask          */
+
+#define EADC_INTSRC2_SPLIE0_Pos          (0)                                               /*!< EADC_T::INTSRC2: SPLIE0 Position       */
+#define EADC_INTSRC2_SPLIE0_Msk          (0x1ul << EADC_INTSRC2_SPLIE0_Pos)                /*!< EADC_T::INTSRC2: SPLIE0 Mask           */
+
+#define EADC_INTSRC2_SPLIE1_Pos          (1)                                               /*!< EADC_T::INTSRC2: SPLIE1 Position       */
+#define EADC_INTSRC2_SPLIE1_Msk          (0x1ul << EADC_INTSRC2_SPLIE1_Pos)                /*!< EADC_T::INTSRC2: SPLIE1 Mask           */
+
+#define EADC_INTSRC2_SPLIE2_Pos          (2)                                               /*!< EADC_T::INTSRC2: SPLIE2 Position       */
+#define EADC_INTSRC2_SPLIE2_Msk          (0x1ul << EADC_INTSRC2_SPLIE2_Pos)                /*!< EADC_T::INTSRC2: SPLIE2 Mask           */
+
+#define EADC_INTSRC2_SPLIE3_Pos          (3)                                               /*!< EADC_T::INTSRC2: SPLIE3 Position       */
+#define EADC_INTSRC2_SPLIE3_Msk          (0x1ul << EADC_INTSRC2_SPLIE3_Pos)                /*!< EADC_T::INTSRC2: SPLIE3 Mask           */
+
+#define EADC_INTSRC2_SPLIE4_Pos          (4)                                               /*!< EADC_T::INTSRC2: SPLIE4 Position       */
+#define EADC_INTSRC2_SPLIE4_Msk          (0x1ul << EADC_INTSRC2_SPLIE4_Pos)                /*!< EADC_T::INTSRC2: SPLIE4 Mask           */
+
+#define EADC_INTSRC2_SPLIE5_Pos          (5)                                               /*!< EADC_T::INTSRC2: SPLIE5 Position       */
+#define EADC_INTSRC2_SPLIE5_Msk          (0x1ul << EADC_INTSRC2_SPLIE5_Pos)                /*!< EADC_T::INTSRC2: SPLIE5 Mask           */
+
+#define EADC_INTSRC2_SPLIE6_Pos          (6)                                               /*!< EADC_T::INTSRC2: SPLIE6 Position       */
+#define EADC_INTSRC2_SPLIE6_Msk          (0x1ul << EADC_INTSRC2_SPLIE6_Pos)                /*!< EADC_T::INTSRC2: SPLIE6 Mask           */
+
+#define EADC_INTSRC2_SPLIE7_Pos          (7)                                               /*!< EADC_T::INTSRC2: SPLIE7 Position       */
+#define EADC_INTSRC2_SPLIE7_Msk          (0x1ul << EADC_INTSRC2_SPLIE7_Pos)                /*!< EADC_T::INTSRC2: SPLIE7 Mask           */
+
+#define EADC_INTSRC2_SPLIE8_Pos          (8)                                               /*!< EADC_T::INTSRC2: SPLIE8 Position       */
+#define EADC_INTSRC2_SPLIE8_Msk          (0x1ul << EADC_INTSRC2_SPLIE8_Pos)                /*!< EADC_T::INTSRC2: SPLIE8 Mask           */
+
+#define EADC_INTSRC2_SPLIE9_Pos          (9)                                               /*!< EADC_T::INTSRC2: SPLIE9 Position       */
+#define EADC_INTSRC2_SPLIE9_Msk          (0x1ul << EADC_INTSRC2_SPLIE9_Pos)                /*!< EADC_T::INTSRC2: SPLIE9 Mask           */
+
+#define EADC_INTSRC2_SPLIE10_Pos         (10)                                              /*!< EADC_T::INTSRC2: SPLIE10 Position      */
+#define EADC_INTSRC2_SPLIE10_Msk         (0x1ul << EADC_INTSRC2_SPLIE10_Pos)               /*!< EADC_T::INTSRC2: SPLIE10 Mask          */
+
+#define EADC_INTSRC2_SPLIE11_Pos         (11)                                              /*!< EADC_T::INTSRC2: SPLIE11 Position      */
+#define EADC_INTSRC2_SPLIE11_Msk         (0x1ul << EADC_INTSRC2_SPLIE11_Pos)               /*!< EADC_T::INTSRC2: SPLIE11 Mask          */
+
+#define EADC_INTSRC2_SPLIE12_Pos         (12)                                              /*!< EADC_T::INTSRC2: SPLIE12 Position      */
+#define EADC_INTSRC2_SPLIE12_Msk         (0x1ul << EADC_INTSRC2_SPLIE12_Pos)               /*!< EADC_T::INTSRC2: SPLIE12 Mask          */
+
+#define EADC_INTSRC2_SPLIE13_Pos         (13)                                              /*!< EADC_T::INTSRC2: SPLIE13 Position      */
+#define EADC_INTSRC2_SPLIE13_Msk         (0x1ul << EADC_INTSRC2_SPLIE13_Pos)               /*!< EADC_T::INTSRC2: SPLIE13 Mask          */
+
+#define EADC_INTSRC2_SPLIE14_Pos         (14)                                              /*!< EADC_T::INTSRC2: SPLIE14 Position      */
+#define EADC_INTSRC2_SPLIE14_Msk         (0x1ul << EADC_INTSRC2_SPLIE14_Pos)               /*!< EADC_T::INTSRC2: SPLIE14 Mask          */
+
+#define EADC_INTSRC2_SPLIE15_Pos         (15)                                              /*!< EADC_T::INTSRC2: SPLIE15 Position      */
+#define EADC_INTSRC2_SPLIE15_Msk         (0x1ul << EADC_INTSRC2_SPLIE15_Pos)               /*!< EADC_T::INTSRC2: SPLIE15 Mask          */
+
+#define EADC_INTSRC2_SPLIE16_Pos         (16)                                              /*!< EADC_T::INTSRC2: SPLIE16 Position      */
+#define EADC_INTSRC2_SPLIE16_Msk         (0x1ul << EADC_INTSRC2_SPLIE16_Pos)               /*!< EADC_T::INTSRC2: SPLIE16 Mask          */
+
+#define EADC_INTSRC2_SPLIE17_Pos         (17)                                              /*!< EADC_T::INTSRC2: SPLIE17 Position      */
+#define EADC_INTSRC2_SPLIE17_Msk         (0x1ul << EADC_INTSRC2_SPLIE17_Pos)               /*!< EADC_T::INTSRC2: SPLIE17 Mask          */
+
+#define EADC_INTSRC2_SPLIE18_Pos         (18)                                              /*!< EADC_T::INTSRC2: SPLIE18 Position      */
+#define EADC_INTSRC2_SPLIE18_Msk         (0x1ul << EADC_INTSRC2_SPLIE18_Pos)               /*!< EADC_T::INTSRC2: SPLIE18 Mask          */
+
+#define EADC_INTSRC3_SPLIE0_Pos          (0)                                               /*!< EADC_T::INTSRC3: SPLIE0 Position       */
+#define EADC_INTSRC3_SPLIE0_Msk          (0x1ul << EADC_INTSRC3_SPLIE0_Pos)                /*!< EADC_T::INTSRC3: SPLIE0 Mask           */
+
+#define EADC_INTSRC3_SPLIE1_Pos          (1)                                               /*!< EADC_T::INTSRC3: SPLIE1 Position       */
+#define EADC_INTSRC3_SPLIE1_Msk          (0x1ul << EADC_INTSRC3_SPLIE1_Pos)                /*!< EADC_T::INTSRC3: SPLIE1 Mask           */
+
+#define EADC_INTSRC3_SPLIE2_Pos          (2)                                               /*!< EADC_T::INTSRC3: SPLIE2 Position       */
+#define EADC_INTSRC3_SPLIE2_Msk          (0x1ul << EADC_INTSRC3_SPLIE2_Pos)                /*!< EADC_T::INTSRC3: SPLIE2 Mask           */
+
+#define EADC_INTSRC3_SPLIE3_Pos          (3)                                               /*!< EADC_T::INTSRC3: SPLIE3 Position       */
+#define EADC_INTSRC3_SPLIE3_Msk          (0x1ul << EADC_INTSRC3_SPLIE3_Pos)                /*!< EADC_T::INTSRC3: SPLIE3 Mask           */
+
+#define EADC_INTSRC3_SPLIE4_Pos          (4)                                               /*!< EADC_T::INTSRC3: SPLIE4 Position       */
+#define EADC_INTSRC3_SPLIE4_Msk          (0x1ul << EADC_INTSRC3_SPLIE4_Pos)                /*!< EADC_T::INTSRC3: SPLIE4 Mask           */
+
+#define EADC_INTSRC3_SPLIE5_Pos          (5)                                               /*!< EADC_T::INTSRC3: SPLIE5 Position       */
+#define EADC_INTSRC3_SPLIE5_Msk          (0x1ul << EADC_INTSRC3_SPLIE5_Pos)                /*!< EADC_T::INTSRC3: SPLIE5 Mask           */
+
+#define EADC_INTSRC3_SPLIE6_Pos          (6)                                               /*!< EADC_T::INTSRC3: SPLIE6 Position       */
+#define EADC_INTSRC3_SPLIE6_Msk          (0x1ul << EADC_INTSRC3_SPLIE6_Pos)                /*!< EADC_T::INTSRC3: SPLIE6 Mask           */
+
+#define EADC_INTSRC3_SPLIE7_Pos          (7)                                               /*!< EADC_T::INTSRC3: SPLIE7 Position       */
+#define EADC_INTSRC3_SPLIE7_Msk          (0x1ul << EADC_INTSRC3_SPLIE7_Pos)                /*!< EADC_T::INTSRC3: SPLIE7 Mask           */
+
+#define EADC_INTSRC3_SPLIE8_Pos          (8)                                               /*!< EADC_T::INTSRC3: SPLIE8 Position       */
+#define EADC_INTSRC3_SPLIE8_Msk          (0x1ul << EADC_INTSRC3_SPLIE8_Pos)                /*!< EADC_T::INTSRC3: SPLIE8 Mask           */
+
+#define EADC_INTSRC3_SPLIE9_Pos          (9)                                               /*!< EADC_T::INTSRC3: SPLIE9 Position       */
+#define EADC_INTSRC3_SPLIE9_Msk          (0x1ul << EADC_INTSRC3_SPLIE9_Pos)                /*!< EADC_T::INTSRC3: SPLIE9 Mask           */
+
+#define EADC_INTSRC3_SPLIE10_Pos         (10)                                              /*!< EADC_T::INTSRC3: SPLIE10 Position      */
+#define EADC_INTSRC3_SPLIE10_Msk         (0x1ul << EADC_INTSRC3_SPLIE10_Pos)               /*!< EADC_T::INTSRC3: SPLIE10 Mask          */
+
+#define EADC_INTSRC3_SPLIE11_Pos         (11)                                              /*!< EADC_T::INTSRC3: SPLIE11 Position      */
+#define EADC_INTSRC3_SPLIE11_Msk         (0x1ul << EADC_INTSRC3_SPLIE11_Pos)               /*!< EADC_T::INTSRC3: SPLIE11 Mask          */
+
+#define EADC_INTSRC3_SPLIE12_Pos         (12)                                              /*!< EADC_T::INTSRC3: SPLIE12 Position      */
+#define EADC_INTSRC3_SPLIE12_Msk         (0x1ul << EADC_INTSRC3_SPLIE12_Pos)               /*!< EADC_T::INTSRC3: SPLIE12 Mask          */
+
+#define EADC_INTSRC3_SPLIE13_Pos         (13)                                              /*!< EADC_T::INTSRC3: SPLIE13 Position      */
+#define EADC_INTSRC3_SPLIE13_Msk         (0x1ul << EADC_INTSRC3_SPLIE13_Pos)               /*!< EADC_T::INTSRC3: SPLIE13 Mask          */
+
+#define EADC_INTSRC3_SPLIE14_Pos         (14)                                              /*!< EADC_T::INTSRC3: SPLIE14 Position      */
+#define EADC_INTSRC3_SPLIE14_Msk         (0x1ul << EADC_INTSRC3_SPLIE14_Pos)               /*!< EADC_T::INTSRC3: SPLIE14 Mask          */
+
+#define EADC_INTSRC3_SPLIE15_Pos         (15)                                              /*!< EADC_T::INTSRC3: SPLIE15 Position      */
+#define EADC_INTSRC3_SPLIE15_Msk         (0x1ul << EADC_INTSRC3_SPLIE15_Pos)               /*!< EADC_T::INTSRC3: SPLIE15 Mask          */
+
+#define EADC_INTSRC3_SPLIE16_Pos         (16)                                              /*!< EADC_T::INTSRC3: SPLIE16 Position      */
+#define EADC_INTSRC3_SPLIE16_Msk         (0x1ul << EADC_INTSRC3_SPLIE16_Pos)               /*!< EADC_T::INTSRC3: SPLIE16 Mask          */
+
+#define EADC_INTSRC3_SPLIE17_Pos         (17)                                              /*!< EADC_T::INTSRC3: SPLIE17 Position      */
+#define EADC_INTSRC3_SPLIE17_Msk         (0x1ul << EADC_INTSRC3_SPLIE17_Pos)               /*!< EADC_T::INTSRC3: SPLIE17 Mask          */
+
+#define EADC_INTSRC3_SPLIE18_Pos         (18)                                              /*!< EADC_T::INTSRC3: SPLIE18 Position      */
+#define EADC_INTSRC3_SPLIE18_Msk         (0x1ul << EADC_INTSRC3_SPLIE18_Pos)               /*!< EADC_T::INTSRC3: SPLIE18 Mask          */
+
+#define EADC_CMP_ADCMPEN_Pos             (0)                                               /*!< EADC_T::CMP: ADCMPEN Position          */
+#define EADC_CMP_ADCMPEN_Msk             (0x1ul << EADC_CMP_ADCMPEN_Pos)                   /*!< EADC_T::CMP: ADCMPEN Mask              */
+
+#define EADC_CMP_ADCMPIE_Pos             (1)                                               /*!< EADC_T::CMP: ADCMPIE Position          */
+#define EADC_CMP_ADCMPIE_Msk             (0x1ul << EADC_CMP_ADCMPIE_Pos)                   /*!< EADC_T::CMP: ADCMPIE Mask              */
+
+#define EADC_CMP_CMPCOND_Pos             (2)                                               /*!< EADC_T::CMP: CMPCOND Position          */
+#define EADC_CMP_CMPCOND_Msk             (0x1ul << EADC_CMP_CMPCOND_Pos)                   /*!< EADC_T::CMP: CMPCOND Mask              */
+
+#define EADC_CMP_CMPSPL_Pos              (3)                                               /*!< EADC_T::CMP: CMPSPL Position           */
+#define EADC_CMP_CMPSPL_Msk              (0x1ful << EADC_CMP_CMPSPL_Pos)                   /*!< EADC_T::CMP: CMPSPL Mask               */
+
+#define EADC_CMP_CMPMCNT_Pos             (8)                                               /*!< EADC_T::CMP: CMPMCNT Position          */
+#define EADC_CMP_CMPMCNT_Msk             (0xful << EADC_CMP_CMPMCNT_Pos)                   /*!< EADC_T::CMP: CMPMCNT Mask              */
+
+#define EADC_CMP_CMPWEN_Pos              (15)                                              /*!< EADC_T::CMP: CMPWEN Position           */
+#define EADC_CMP_CMPWEN_Msk              (0x1ul << EADC_CMP_CMPWEN_Pos)                    /*!< EADC_T::CMP: CMPWEN Mask               */
+
+#define EADC_CMP_CMPDAT_Pos              (16)                                              /*!< EADC_T::CMP: CMPDAT Position           */
+#define EADC_CMP_CMPDAT_Msk              (0xffful << EADC_CMP_CMPDAT_Pos)                  /*!< EADC_T::CMP: CMPDAT Mask               */
+
+#define EADC_CMP0_ADCMPEN_Pos            (0)                                               /*!< EADC_T::CMP0: ADCMPEN Position         */
+#define EADC_CMP0_ADCMPEN_Msk            (0x1ul << EADC_CMP0_ADCMPEN_Pos)                  /*!< EADC_T::CMP0: ADCMPEN Mask             */
+
+#define EADC_CMP0_ADCMPIE_Pos            (1)                                               /*!< EADC_T::CMP0: ADCMPIE Position         */
+#define EADC_CMP0_ADCMPIE_Msk            (0x1ul << EADC_CMP0_ADCMPIE_Pos)                  /*!< EADC_T::CMP0: ADCMPIE Mask             */
+
+#define EADC_CMP0_CMPCOND_Pos            (2)                                               /*!< EADC_T::CMP0: CMPCOND Position         */
+#define EADC_CMP0_CMPCOND_Msk            (0x1ul << EADC_CMP0_CMPCOND_Pos)                  /*!< EADC_T::CMP0: CMPCOND Mask             */
+
+#define EADC_CMP0_CMPSPL_Pos             (3)                                               /*!< EADC_T::CMP0: CMPSPL Position          */
+#define EADC_CMP0_CMPSPL_Msk             (0x1ful << EADC_CMP0_CMPSPL_Pos)                  /*!< EADC_T::CMP0: CMPSPL Mask              */
+
+#define EADC_CMP0_CMPMCNT_Pos            (8)                                               /*!< EADC_T::CMP0: CMPMCNT Position         */
+#define EADC_CMP0_CMPMCNT_Msk            (0xful << EADC_CMP0_CMPMCNT_Pos)                  /*!< EADC_T::CMP0: CMPMCNT Mask             */
+
+#define EADC_CMP0_CMPWEN_Pos             (15)                                              /*!< EADC_T::CMP0: CMPWEN Position          */
+#define EADC_CMP0_CMPWEN_Msk             (0x1ul << EADC_CMP0_CMPWEN_Pos)                   /*!< EADC_T::CMP0: CMPWEN Mask              */
+
+#define EADC_CMP0_CMPDAT_Pos             (16)                                              /*!< EADC_T::CMP0: CMPDAT Position          */
+#define EADC_CMP0_CMPDAT_Msk             (0xffful << EADC_CMP0_CMPDAT_Pos)                 /*!< EADC_T::CMP0: CMPDAT Mask              */
+
+#define EADC_CMP1_ADCMPEN_Pos            (0)                                               /*!< EADC_T::CMP1: ADCMPEN Position         */
+#define EADC_CMP1_ADCMPEN_Msk            (0x1ul << EADC_CMP1_ADCMPEN_Pos)                  /*!< EADC_T::CMP1: ADCMPEN Mask             */
+
+#define EADC_CMP1_ADCMPIE_Pos            (1)                                               /*!< EADC_T::CMP1: ADCMPIE Position         */
+#define EADC_CMP1_ADCMPIE_Msk            (0x1ul << EADC_CMP1_ADCMPIE_Pos)                  /*!< EADC_T::CMP1: ADCMPIE Mask             */
+
+#define EADC_CMP1_CMPCOND_Pos            (2)                                               /*!< EADC_T::CMP1: CMPCOND Position         */
+#define EADC_CMP1_CMPCOND_Msk            (0x1ul << EADC_CMP1_CMPCOND_Pos)                  /*!< EADC_T::CMP1: CMPCOND Mask             */
+
+#define EADC_CMP1_CMPSPL_Pos             (3)                                               /*!< EADC_T::CMP1: CMPSPL Position          */
+#define EADC_CMP1_CMPSPL_Msk             (0x1ful << EADC_CMP1_CMPSPL_Pos)                  /*!< EADC_T::CMP1: CMPSPL Mask              */
+
+#define EADC_CMP1_CMPMCNT_Pos            (8)                                               /*!< EADC_T::CMP1: CMPMCNT Position         */
+#define EADC_CMP1_CMPMCNT_Msk            (0xful << EADC_CMP1_CMPMCNT_Pos)                  /*!< EADC_T::CMP1: CMPMCNT Mask             */
+
+#define EADC_CMP1_CMPWEN_Pos             (15)                                              /*!< EADC_T::CMP1: CMPWEN Position          */
+#define EADC_CMP1_CMPWEN_Msk             (0x1ul << EADC_CMP1_CMPWEN_Pos)                   /*!< EADC_T::CMP1: CMPWEN Mask              */
+
+#define EADC_CMP1_CMPDAT_Pos             (16)                                              /*!< EADC_T::CMP1: CMPDAT Position          */
+#define EADC_CMP1_CMPDAT_Msk             (0xffful << EADC_CMP1_CMPDAT_Pos)                 /*!< EADC_T::CMP1: CMPDAT Mask              */
+
+#define EADC_CMP2_ADCMPEN_Pos            (0)                                               /*!< EADC_T::CMP2: ADCMPEN Position         */
+#define EADC_CMP2_ADCMPEN_Msk            (0x1ul << EADC_CMP2_ADCMPEN_Pos)                  /*!< EADC_T::CMP2: ADCMPEN Mask             */
+
+#define EADC_CMP2_ADCMPIE_Pos            (1)                                               /*!< EADC_T::CMP2: ADCMPIE Position         */
+#define EADC_CMP2_ADCMPIE_Msk            (0x1ul << EADC_CMP2_ADCMPIE_Pos)                  /*!< EADC_T::CMP2: ADCMPIE Mask             */
+
+#define EADC_CMP2_CMPCOND_Pos            (2)                                               /*!< EADC_T::CMP2: CMPCOND Position         */
+#define EADC_CMP2_CMPCOND_Msk            (0x1ul << EADC_CMP2_CMPCOND_Pos)                  /*!< EADC_T::CMP2: CMPCOND Mask             */
+
+#define EADC_CMP2_CMPSPL_Pos             (3)                                               /*!< EADC_T::CMP2: CMPSPL Position          */
+#define EADC_CMP2_CMPSPL_Msk             (0x1ful << EADC_CMP2_CMPSPL_Pos)                  /*!< EADC_T::CMP2: CMPSPL Mask              */
+
+#define EADC_CMP2_CMPMCNT_Pos            (8)                                               /*!< EADC_T::CMP2: CMPMCNT Position         */
+#define EADC_CMP2_CMPMCNT_Msk            (0xful << EADC_CMP2_CMPMCNT_Pos)                  /*!< EADC_T::CMP2: CMPMCNT Mask             */
+
+#define EADC_CMP2_CMPWEN_Pos             (15)                                              /*!< EADC_T::CMP2: CMPWEN Position          */
+#define EADC_CMP2_CMPWEN_Msk             (0x1ul << EADC_CMP2_CMPWEN_Pos)                   /*!< EADC_T::CMP2: CMPWEN Mask              */
+
+#define EADC_CMP2_CMPDAT_Pos             (16)                                              /*!< EADC_T::CMP2: CMPDAT Position          */
+#define EADC_CMP2_CMPDAT_Msk             (0xffful << EADC_CMP2_CMPDAT_Pos)                 /*!< EADC_T::CMP2: CMPDAT Mask              */
+
+#define EADC_CMP3_ADCMPEN_Pos            (0)                                               /*!< EADC_T::CMP3: ADCMPEN Position         */
+#define EADC_CMP3_ADCMPEN_Msk            (0x1ul << EADC_CMP3_ADCMPEN_Pos)                  /*!< EADC_T::CMP3: ADCMPEN Mask             */
+
+#define EADC_CMP3_ADCMPIE_Pos            (1)                                               /*!< EADC_T::CMP3: ADCMPIE Position         */
+#define EADC_CMP3_ADCMPIE_Msk            (0x1ul << EADC_CMP3_ADCMPIE_Pos)                  /*!< EADC_T::CMP3: ADCMPIE Mask             */
+
+#define EADC_CMP3_CMPCOND_Pos            (2)                                               /*!< EADC_T::CMP3: CMPCOND Position         */
+#define EADC_CMP3_CMPCOND_Msk            (0x1ul << EADC_CMP3_CMPCOND_Pos)                  /*!< EADC_T::CMP3: CMPCOND Mask             */
+
+#define EADC_CMP3_CMPSPL_Pos             (3)                                               /*!< EADC_T::CMP3: CMPSPL Position          */
+#define EADC_CMP3_CMPSPL_Msk             (0x1ful << EADC_CMP3_CMPSPL_Pos)                  /*!< EADC_T::CMP3: CMPSPL Mask              */
+
+#define EADC_CMP3_CMPMCNT_Pos            (8)                                               /*!< EADC_T::CMP3: CMPMCNT Position         */
+#define EADC_CMP3_CMPMCNT_Msk            (0xful << EADC_CMP3_CMPMCNT_Pos)                  /*!< EADC_T::CMP3: CMPMCNT Mask             */
+
+#define EADC_CMP3_CMPWEN_Pos             (15)                                              /*!< EADC_T::CMP3: CMPWEN Position          */
+#define EADC_CMP3_CMPWEN_Msk             (0x1ul << EADC_CMP3_CMPWEN_Pos)                   /*!< EADC_T::CMP3: CMPWEN Mask              */
+
+#define EADC_CMP3_CMPDAT_Pos             (16)                                              /*!< EADC_T::CMP3: CMPDAT Position          */
+#define EADC_CMP3_CMPDAT_Msk             (0xffful << EADC_CMP3_CMPDAT_Pos)                 /*!< EADC_T::CMP3: CMPDAT Mask              */
+
+#define EADC_STATUS0_VALID_Pos           (0)                                               /*!< EADC_T::STATUS0: VALID Position        */
+#define EADC_STATUS0_VALID_Msk           (0xfffful << EADC_STATUS0_VALID_Pos)              /*!< EADC_T::STATUS0: VALID Mask            */
+
+#define EADC_STATUS0_OV_Pos              (16)                                              /*!< EADC_T::STATUS0: OV Position           */
+#define EADC_STATUS0_OV_Msk              (0xfffful << EADC_STATUS0_OV_Pos)                 /*!< EADC_T::STATUS0: OV Mask               */
+
+#define EADC_STATUS1_VALID_Pos           (0)                                               /*!< EADC_T::STATUS1: VALID Position        */
+#define EADC_STATUS1_VALID_Msk           (0x7ul << EADC_STATUS1_VALID_Pos)                 /*!< EADC_T::STATUS1: VALID Mask            */
+
+#define EADC_STATUS1_OV_Pos              (16)                                              /*!< EADC_T::STATUS1: OV Position           */
+#define EADC_STATUS1_OV_Msk              (0x7ul << EADC_STATUS1_OV_Pos)                    /*!< EADC_T::STATUS1: OV Mask               */
+
+#define EADC_STATUS2_ADIF0_Pos           (0)                                               /*!< EADC_T::STATUS2: ADIF0 Position        */
+#define EADC_STATUS2_ADIF0_Msk           (0x1ul << EADC_STATUS2_ADIF0_Pos)                 /*!< EADC_T::STATUS2: ADIF0 Mask            */
+
+#define EADC_STATUS2_ADIF1_Pos           (1)                                               /*!< EADC_T::STATUS2: ADIF1 Position        */
+#define EADC_STATUS2_ADIF1_Msk           (0x1ul << EADC_STATUS2_ADIF1_Pos)                 /*!< EADC_T::STATUS2: ADIF1 Mask            */
+
+#define EADC_STATUS2_ADIF2_Pos           (2)                                               /*!< EADC_T::STATUS2: ADIF2 Position        */
+#define EADC_STATUS2_ADIF2_Msk           (0x1ul << EADC_STATUS2_ADIF2_Pos)                 /*!< EADC_T::STATUS2: ADIF2 Mask            */
+
+#define EADC_STATUS2_ADIF3_Pos           (3)                                               /*!< EADC_T::STATUS2: ADIF3 Position        */
+#define EADC_STATUS2_ADIF3_Msk           (0x1ul << EADC_STATUS2_ADIF3_Pos)                 /*!< EADC_T::STATUS2: ADIF3 Mask            */
+
+#define EADC_STATUS2_ADCMPF0_Pos         (4)                                               /*!< EADC_T::STATUS2: ADCMPF0 Position      */
+#define EADC_STATUS2_ADCMPF0_Msk         (0x1ul << EADC_STATUS2_ADCMPF0_Pos)               /*!< EADC_T::STATUS2: ADCMPF0 Mask          */
+
+#define EADC_STATUS2_ADCMPF1_Pos         (5)                                               /*!< EADC_T::STATUS2: ADCMPF1 Position      */
+#define EADC_STATUS2_ADCMPF1_Msk         (0x1ul << EADC_STATUS2_ADCMPF1_Pos)               /*!< EADC_T::STATUS2: ADCMPF1 Mask          */
+
+#define EADC_STATUS2_ADCMPF2_Pos         (6)                                               /*!< EADC_T::STATUS2: ADCMPF2 Position      */
+#define EADC_STATUS2_ADCMPF2_Msk         (0x1ul << EADC_STATUS2_ADCMPF2_Pos)               /*!< EADC_T::STATUS2: ADCMPF2 Mask          */
+
+#define EADC_STATUS2_ADCMPF3_Pos         (7)                                               /*!< EADC_T::STATUS2: ADCMPF3 Position      */
+#define EADC_STATUS2_ADCMPF3_Msk         (0x1ul << EADC_STATUS2_ADCMPF3_Pos)               /*!< EADC_T::STATUS2: ADCMPF3 Mask          */
+
+#define EADC_STATUS2_ADOVIF0_Pos         (8)                                               /*!< EADC_T::STATUS2: ADOVIF0 Position      */
+#define EADC_STATUS2_ADOVIF0_Msk         (0x1ul << EADC_STATUS2_ADOVIF0_Pos)               /*!< EADC_T::STATUS2: ADOVIF0 Mask          */
+
+#define EADC_STATUS2_ADOVIF1_Pos         (9)                                               /*!< EADC_T::STATUS2: ADOVIF1 Position      */
+#define EADC_STATUS2_ADOVIF1_Msk         (0x1ul << EADC_STATUS2_ADOVIF1_Pos)               /*!< EADC_T::STATUS2: ADOVIF1 Mask          */
+
+#define EADC_STATUS2_ADOVIF2_Pos         (10)                                              /*!< EADC_T::STATUS2: ADOVIF2 Position      */
+#define EADC_STATUS2_ADOVIF2_Msk         (0x1ul << EADC_STATUS2_ADOVIF2_Pos)               /*!< EADC_T::STATUS2: ADOVIF2 Mask          */
+
+#define EADC_STATUS2_ADOVIF3_Pos         (11)                                              /*!< EADC_T::STATUS2: ADOVIF3 Position      */
+#define EADC_STATUS2_ADOVIF3_Msk         (0x1ul << EADC_STATUS2_ADOVIF3_Pos)               /*!< EADC_T::STATUS2: ADOVIF3 Mask          */
+
+#define EADC_STATUS2_ADCMPO0_Pos         (12)                                              /*!< EADC_T::STATUS2: ADCMPO0 Position      */
+#define EADC_STATUS2_ADCMPO0_Msk         (0x1ul << EADC_STATUS2_ADCMPO0_Pos)               /*!< EADC_T::STATUS2: ADCMPO0 Mask          */
+
+#define EADC_STATUS2_ADCMPO1_Pos         (13)                                              /*!< EADC_T::STATUS2: ADCMPO1 Position      */
+#define EADC_STATUS2_ADCMPO1_Msk         (0x1ul << EADC_STATUS2_ADCMPO1_Pos)               /*!< EADC_T::STATUS2: ADCMPO1 Mask          */
+
+#define EADC_STATUS2_ADCMPO2_Pos         (14)                                              /*!< EADC_T::STATUS2: ADCMPO2 Position      */
+#define EADC_STATUS2_ADCMPO2_Msk         (0x1ul << EADC_STATUS2_ADCMPO2_Pos)               /*!< EADC_T::STATUS2: ADCMPO2 Mask          */
+
+#define EADC_STATUS2_ADCMPO3_Pos         (15)                                              /*!< EADC_T::STATUS2: ADCMPO3 Position      */
+#define EADC_STATUS2_ADCMPO3_Msk         (0x1ul << EADC_STATUS2_ADCMPO3_Pos)               /*!< EADC_T::STATUS2: ADCMPO3 Mask          */
+
+#define EADC_STATUS2_CHANNEL_Pos         (16)                                              /*!< EADC_T::STATUS2: CHANNEL Position      */
+#define EADC_STATUS2_CHANNEL_Msk         (0x1ful << EADC_STATUS2_CHANNEL_Pos)              /*!< EADC_T::STATUS2: CHANNEL Mask          */
+
+#define EADC_STATUS2_BUSY_Pos            (23)                                              /*!< EADC_T::STATUS2: BUSY Position         */
+#define EADC_STATUS2_BUSY_Msk            (0x1ul << EADC_STATUS2_BUSY_Pos)                  /*!< EADC_T::STATUS2: BUSY Mask             */
+
+#define EADC_STATUS2_ADOVIF_Pos          (24)                                              /*!< EADC_T::STATUS2: ADOVIF Position       */
+#define EADC_STATUS2_ADOVIF_Msk          (0x1ul << EADC_STATUS2_ADOVIF_Pos)                /*!< EADC_T::STATUS2: ADOVIF Mask           */
+
+#define EADC_STATUS2_STOVF_Pos           (25)                                              /*!< EADC_T::STATUS2: STOVF Position        */
+#define EADC_STATUS2_STOVF_Msk           (0x1ul << EADC_STATUS2_STOVF_Pos)                 /*!< EADC_T::STATUS2: STOVF Mask            */
+
+#define EADC_STATUS2_AVALID_Pos          (26)                                              /*!< EADC_T::STATUS2: AVALID Position       */
+#define EADC_STATUS2_AVALID_Msk          (0x1ul << EADC_STATUS2_AVALID_Pos)                /*!< EADC_T::STATUS2: AVALID Mask           */
+
+#define EADC_STATUS2_AOV_Pos             (27)                                              /*!< EADC_T::STATUS2: AOV Position          */
+#define EADC_STATUS2_AOV_Msk             (0x1ul << EADC_STATUS2_AOV_Pos)                   /*!< EADC_T::STATUS2: AOV Mask              */
+
+#define EADC_STATUS3_CURSPL_Pos          (0)                                               /*!< EADC_T::STATUS3: CURSPL Position       */
+#define EADC_STATUS3_CURSPL_Msk          (0x1ful << EADC_STATUS3_CURSPL_Pos)               /*!< EADC_T::STATUS3: CURSPL Mask           */
+
+#define EADC_DDAT0_RESULT_Pos            (0)                                               /*!< EADC_T::DDAT0: RESULT Position         */
+#define EADC_DDAT0_RESULT_Msk            (0xfffful << EADC_DDAT0_RESULT_Pos)               /*!< EADC_T::DDAT0: RESULT Mask             */
+
+#define EADC_DDAT0_OV_Pos                (16)                                              /*!< EADC_T::DDAT0: OV Position             */
+#define EADC_DDAT0_OV_Msk                (0x1ul << EADC_DDAT0_OV_Pos)                      /*!< EADC_T::DDAT0: OV Mask                 */
+
+#define EADC_DDAT0_VALID_Pos             (17)                                              /*!< EADC_T::DDAT0: VALID Position          */
+#define EADC_DDAT0_VALID_Msk             (0x1ul << EADC_DDAT0_VALID_Pos)                   /*!< EADC_T::DDAT0: VALID Mask              */
+
+#define EADC_DDAT1_RESULT_Pos            (0)                                               /*!< EADC_T::DDAT1: RESULT Position         */
+#define EADC_DDAT1_RESULT_Msk            (0xfffful << EADC_DDAT1_RESULT_Pos)               /*!< EADC_T::DDAT1: RESULT Mask             */
+
+#define EADC_DDAT1_OV_Pos                (16)                                              /*!< EADC_T::DDAT1: OV Position             */
+#define EADC_DDAT1_OV_Msk                (0x1ul << EADC_DDAT1_OV_Pos)                      /*!< EADC_T::DDAT1: OV Mask                 */
+
+#define EADC_DDAT1_VALID_Pos             (17)                                              /*!< EADC_T::DDAT1: VALID Position          */
+#define EADC_DDAT1_VALID_Msk             (0x1ul << EADC_DDAT1_VALID_Pos)                   /*!< EADC_T::DDAT1: VALID Mask              */
+
+#define EADC_DDAT2_RESULT_Pos            (0)                                               /*!< EADC_T::DDAT2: RESULT Position         */
+#define EADC_DDAT2_RESULT_Msk            (0xfffful << EADC_DDAT2_RESULT_Pos)               /*!< EADC_T::DDAT2: RESULT Mask             */
+
+#define EADC_DDAT2_OV_Pos                (16)                                              /*!< EADC_T::DDAT2: OV Position             */
+#define EADC_DDAT2_OV_Msk                (0x1ul << EADC_DDAT2_OV_Pos)                      /*!< EADC_T::DDAT2: OV Mask                 */
+
+#define EADC_DDAT2_VALID_Pos             (17)                                              /*!< EADC_T::DDAT2: VALID Position          */
+#define EADC_DDAT2_VALID_Msk             (0x1ul << EADC_DDAT2_VALID_Pos)                   /*!< EADC_T::DDAT2: VALID Mask              */
+
+#define EADC_DDAT3_RESULT_Pos            (0)                                               /*!< EADC_T::DDAT3: RESULT Position         */
+#define EADC_DDAT3_RESULT_Msk            (0xfffful << EADC_DDAT3_RESULT_Pos)               /*!< EADC_T::DDAT3: RESULT Mask             */
+
+#define EADC_DDAT3_OV_Pos                (16)                                              /*!< EADC_T::DDAT3: OV Position             */
+#define EADC_DDAT3_OV_Msk                (0x1ul << EADC_DDAT3_OV_Pos)                      /*!< EADC_T::DDAT3: OV Mask                 */
+
+#define EADC_DDAT3_VALID_Pos             (17)                                              /*!< EADC_T::DDAT3: VALID Position          */
+#define EADC_DDAT3_VALID_Msk             (0x1ul << EADC_DDAT3_VALID_Pos)                   /*!< EADC_T::DDAT3: VALID Mask              */
+
+#define EADC_PWRM_PWUPRDY_Pos            (0)                                               /*!< EADC_T::PWRM: PWUPRDY Position         */
+#define EADC_PWRM_PWUPRDY_Msk            (0x1ul << EADC_PWRM_PWUPRDY_Pos)                  /*!< EADC_T::PWRM: PWUPRDY Mask             */
+
+#define EADC_PWRM_PWUCALEN_Pos           (1)                                               /*!< EADC_T::PWRM: PWUCALEN Position        */
+#define EADC_PWRM_PWUCALEN_Msk           (0x1ul << EADC_PWRM_PWUCALEN_Pos)                 /*!< EADC_T::PWRM: PWUCALEN Mask            */
+
+#define EADC_PWRM_PWDMOD_Pos             (2)                                               /*!< EADC_T::PWRM: PWDMOD Position          */
+#define EADC_PWRM_PWDMOD_Msk             (0x3ul << EADC_PWRM_PWDMOD_Pos)                   /*!< EADC_T::PWRM: PWDMOD Mask              */
+
+#define EADC_PWRM_LDOSUT_Pos             (8)                                               /*!< EADC_T::PWRM: LDOSUT Position          */
+#define EADC_PWRM_LDOSUT_Msk             (0xffful << EADC_PWRM_LDOSUT_Pos)                 /*!< EADC_T::PWRM: LDOSUT Mask              */
+
+#define EADC_CALCTL_CALSTART_Pos         (1)                                               /*!< EADC_T::CALCTL: CALSTART Position      */
+#define EADC_CALCTL_CALSTART_Msk         (0x1ul << EADC_CALCTL_CALSTART_Pos)               /*!< EADC_T::CALCTL: CALSTART Mask          */
+
+#define EADC_CALCTL_CALDONE_Pos          (2)                                               /*!< EADC_T::CALCTL: CALDONE Position       */
+#define EADC_CALCTL_CALDONE_Msk          (0x1ul << EADC_CALCTL_CALDONE_Pos)                /*!< EADC_T::CALCTL: CALDONE Mask           */
+
+#define EADC_CALCTL_CALSEL_Pos           (3)                                               /*!< EADC_T::CALCTL: CALSEL Position        */
+#define EADC_CALCTL_CALSEL_Msk           (0x1ul << EADC_CALCTL_CALSEL_Pos)                 /*!< EADC_T::CALCTL: CALSEL Mask            */
+
+#define EADC_CALDWRD_CALWORD_Pos         (0)                                               /*!< EADC_T::CALDWRD: CALWORD Position      */
+#define EADC_CALDWRD_CALWORD_Msk         (0x7ful << EADC_CALDWRD_CALWORD_Pos)              /*!< EADC_T::CALDWRD: CALWORD Mask          */
+
+#define EADC_PDMACTL_PDMATEN_Pos         (0)                                               /*!< EADC_T::PDMACTL: PDMATEN Position      */
+#define EADC_PDMACTL_PDMATEN_Msk         (0x7fffful << EADC_PDMACTL_PDMATEN_Pos)           /*!< EADC_T::PDMACTL: PDMATEN Mask          */
+
+
+/**@}*/ /* EADC_CONST */
+/**@}*/ /* end of EADC register group */
+/**@}*/ /* end of REGISTER group */
+
+
+
+#endif /* __EADC_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/ebi_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/ebi_reg.h
new file mode 100644
index 0000000000..f884d34c07
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/ebi_reg.h
@@ -0,0 +1,163 @@
+/**************************************************************************//**
+ * @file     ebi_reg.h
+ * @version  V1.00
+ * @brief    EBI register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __EBI_REG_H__
+#define __EBI_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+
+/*---------------------- External Bus Interface Controller -------------------------*/
+/**
+    @addtogroup EBI External Bus Interface Controller(EBI)
+    Memory Mapped Structure for EBI Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var EBI_T::CTL0
+     * Offset: 0x00  External Bus Interface Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |EN        |EBI Enable Bit
+     * |        |          |This bit is the functional enable bit for EBI.
+     * |        |          |0 = EBI function Disabled.
+     * |        |          |1 = EBI function Enabled.
+     * |[1]     |DW16      |EBI Data Width 16-bit Select
+     * |        |          |This bit defines if the EBI data width is 8-bit or 16-bit.
+     * |        |          |0 = EBI data width is 8-bit.
+     * |        |          |1 = EBI data width is 16-bit.
+     * |[2]     |CSPOLINV  |Chip Select Pin Polar Inverse
+     * |        |          |This bit defines the active level of EBI chip select pin (EBI_nCS).
+     * |        |          |0 = Chip select pin (EBI_nCS) is active low.
+     * |        |          |1 = Chip select pin (EBI_nCS) is active high.
+     * |[3]     |ADSEPEN   |EBI Address/Data Bus Separating Mode Enable Bit
+     * |        |          |0 = Address/Data Bus Separating Mode Disabled.
+     * |        |          |1 = Address/Data Bus Separating Mode Enabled.
+     * |[4]     |CACCESS   |Continuous Data Access Mode
+     * |        |          |When continuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
+     * |        |          |0 = Continuous data access mode Disabled.
+     * |        |          |1 = Continuous data access mode Enabled.
+     * |[10:8]  |MCLKDIV   |External Output Clock Divider
+     * |        |          |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
+     * |        |          |000 = HCLK/1.
+     * |        |          |001 = HCLK/2.
+     * |        |          |010 = HCLK/4.
+     * |        |          |011 = HCLK/8.
+     * |        |          |100 = HCLK/16.
+     * |        |          |101 = HCLK/32.
+     * |        |          |110 = HCLK/64.
+     * |        |          |111 = HCLK/128.
+     * |[18:16] |TALE      |Extend Time of ALE
+     * |        |          |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
+     * |        |          |tALE = (TALE+1)*EBI_MCLK.
+     * |        |          |Note: This field only available in EBI_CTL0 register
+     * |[24]    |WBUFEN    |EBI Write Buffer Enable Bit
+     * |        |          |0 = EBI write buffer Disabled.
+     * |        |          |1 = EBI write buffer Enabled.
+     * |        |          |Note: This bit only available in EBI_CTL0 register
+     * @var EBI_T::TCTL0
+     * Offset: 0x04  External Bus Interface Timing Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:3]   |TACC      |EBI Data Access Time
+     * |        |          |TACC define data access time (tACC).
+     * |        |          |tACC = (TACC+1) * EBI_MCLK.
+     * |[10:8]  |TAHD      |EBI Data Access Hold Time
+     * |        |          |TAHD define data access hold time (tAHD).
+     * |        |          |tAHD = (TAHD+1) * EBI_MCLK.
+     * |[15:12] |W2X       |Idle Cycle After Write
+     * |        |          |This field defines the number of W2X idle cycle.
+     * |        |          |W2X idle cycle = (W2X * EBI_MCLK).
+     * |        |          |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
+     * |[22]    |RAHDOFF   |Access Hold Time Disable Control When Read
+     * |        |          |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
+     * |        |          |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
+     * |[23]    |WAHDOFF   |Access Hold Time Disable Control When Write
+     * |        |          |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
+     * |        |          |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
+     * |[27:24] |R2R       |Idle Cycle Between Read-to-read
+     * |        |          |This field defines the number of R2R idle cycle.
+     * |        |          |R2R idle cycle = (R2R * EBI_MCLK).
+     * |        |          |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.
+     */
+    __IO uint32_t CTL0;                  /*!< [0x0000] External Bus Interface Bank0 Control Register                    */
+    __IO uint32_t TCTL0;                 /*!< [0x0004] External Bus Interface Bank0 Timing Control Register             */
+    __I  uint32_t RESERVE0[2];
+    __IO uint32_t CTL1;                  /*!< [0x0010] External Bus Interface Bank1 Control Register                    */
+    __IO uint32_t TCTL1;                 /*!< [0x0014] External Bus Interface Bank1 Timing Control Register             */
+    __I  uint32_t RESERVE1[2];
+    __IO uint32_t CTL2;                  /*!< [0x0020] External Bus Interface Bank2 Control Register                    */
+    __IO uint32_t TCTL2;                 /*!< [0x0024] External Bus Interface Bank2 Timing Control Register             */
+
+} EBI_T;
+
+/**
+    @addtogroup EBI_CONST EBI Bit Field Definition
+    Constant Definitions for EBI Controller
+  @{
+*/
+
+#define EBI_CTL_EN_Pos                   (0)                                               /*!< EBI_T::CTL0: EN Position                  */
+#define EBI_CTL_EN_Msk                   (0x1ul << EBI_CTL_EN_Pos)                         /*!< EBI_T::CTL0: EN Mask                      */
+
+#define EBI_CTL_DW16_Pos                 (1)                                               /*!< EBI_T::CTL0: DW16 Position                */
+#define EBI_CTL_DW16_Msk                 (0x1ul << EBI_CTL_DW16_Pos)                       /*!< EBI_T::CTL0: DW16 Mask                    */
+
+#define EBI_CTL_CSPOLINV_Pos             (2)                                               /*!< EBI_T::CTL0: CSPOLINV Position            */
+#define EBI_CTL_CSPOLINV_Msk             (0x1ul << EBI_CTL_CSPOLINV_Pos)                   /*!< EBI_T::CTL0: CSPOLINV Mask                */
+
+#define EBI_CTL_ADSEPEN_Pos              (3)                                               /*!< EBI_T::CTL0: ADSEPEN Position            */
+#define EBI_CTL_ADSEPEN_Msk              (0x1ul << EBI_CTL_ADSEPEN_Pos)                    /*!< EBI_T::CTL0: ADSEPEN Mask                */
+
+#define EBI_CTL_CACCESS_Pos              (4)                                               /*!< EBI_T::CTL0: CACCESS Position             */
+#define EBI_CTL_CACCESS_Msk              (0x1ul << EBI_CTL_CACCESS_Pos)                    /*!< EBI_T::CTL0: CACCESS Mask                 */
+
+#define EBI_CTL_MCLKDIV_Pos              (8)                                               /*!< EBI_T::CTL0: MCLKDIV Position             */
+#define EBI_CTL_MCLKDIV_Msk              (0x7ul << EBI_CTL_MCLKDIV_Pos)                    /*!< EBI_T::CTL0: MCLKDIV Mask                 */
+
+#define EBI_CTL_TALE_Pos                 (16)                                              /*!< EBI_T::CTL0: TALE Position                */
+#define EBI_CTL_TALE_Msk                 (0x7ul << EBI_CTL_TALE_Pos)                       /*!< EBI_T::CTL0: TALE Mask                    */
+
+#define EBI_CTL_WBUFEN_Pos               (24)                                              /*!< EBI_T::CTL0: WBUFEN Position              */
+#define EBI_CTL_WBUFEN_Msk               (0x1ul << EBI_CTL_WBUFEN_Pos)                     /*!< EBI_T::CTL0: WBUFEN Mask                  */
+
+#define EBI_TCTL_TACC_Pos                (3)                                               /*!< EBI_T::TCTL0: TACC Position               */
+#define EBI_TCTL_TACC_Msk                (0x1ful << EBI_TCTL_TACC_Pos)                     /*!< EBI_T::TCTL0: TACC Mask                   */
+
+#define EBI_TCTL_TAHD_Pos                (8)                                               /*!< EBI_T::TCTL0: TAHD Position               */
+#define EBI_TCTL_TAHD_Msk                (0x7ul << EBI_TCTL_TAHD_Pos)                      /*!< EBI_T::TCTL0: TAHD Mask                   */
+
+#define EBI_TCTL_W2X_Pos                 (12)                                              /*!< EBI_T::TCTL0: W2X Position                */
+#define EBI_TCTL_W2X_Msk                 (0xful << EBI_TCTL_W2X_Pos)                       /*!< EBI_T::TCTL0: W2X Mask                    */
+
+#define EBI_TCTL_RAHDOFF_Pos             (22)                                              /*!< EBI_T::TCTL0: RAHDOFF Position            */
+#define EBI_TCTL_RAHDOFF_Msk             (0x1ul << EBI_TCTL_RAHDOFF_Pos)                   /*!< EBI_T::TCTL0: RAHDOFF Mask                */
+
+#define EBI_TCTL_WAHDOFF_Pos             (23)                                              /*!< EBI_T::TCTL0: WAHDOFF Position            */
+#define EBI_TCTL_WAHDOFF_Msk             (0x1ul << EBI_TCTL_WAHDOFF_Pos)                   /*!< EBI_T::TCTL0: WAHDOFF Mask                */
+
+#define EBI_TCTL_R2R_Pos                 (24)                                              /*!< EBI_T::TCTL0: R2R Position                */
+#define EBI_TCTL_R2R_Msk                 (0xful << EBI_TCTL_R2R_Pos)                       /*!< EBI_T::TCTL0: R2R Mask                    */
+
+/**@}*/ /* EBI_CONST */
+/**@}*/ /* end of EBI register group */
+/**@}*/ /* end of REGISTER group */
+
+
+#endif /* __EBI_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/ecap_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/ecap_reg.h
new file mode 100644
index 0000000000..8710ce59f0
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/ecap_reg.h
@@ -0,0 +1,388 @@
+/**************************************************************************//**
+ * @file     ecap_reg.h
+ * @version  V1.00
+ * @brief    ECAP register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __ECAP_REG_H__
+#define __ECAP_REG_H__
+
+/**
+  @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+/*---------------------- Enhanced Input Capture Timer -------------------------*/
+/**
+  @addtogroup ECAP Enhanced Input Capture Timer(ECAP)
+  Memory Mapped Structure for ECAP Controller
+  @{
+*/
+
+typedef struct
+{
+
+    /**
+     * @var ECAP_T::CNT
+     * Offset: 0x00  Input Capture Counter (24-bit up counter)
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:0]  |CNT       |Input Capture Timer/Counter
+     * |        |          |The input Capture Timer/Counter is a 24-bit up-counting counter
+     * |        |          |The clock source for the counter is from the clock divider
+     * @var ECAP_T::HLD0
+     * Offset: 0x04  Input Capture Hold Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:0]  |HOLD      |Input Capture Counter Hold Register
+     * |        |          |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
+     * |        |          |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
+     * @var ECAP_T::HLD1
+     * Offset: 0x08  Input Capture Hold Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:0]  |HOLD      |Input Capture Counter Hold Register
+     * |        |          |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
+     * |        |          |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
+     * @var ECAP_T::HLD2
+     * Offset: 0x0C  Input Capture Hold Register 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:0]  |HOLD      |Input Capture Counter Hold Register
+     * |        |          |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register
+     * |        |          |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
+     * @var ECAP_T::CNTCMP
+     * Offset: 0x10  Input Capture Compare Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:0]  |CNTCMP    |Input Capture Counter Compare Register
+     * |        |          |If the compare function is enabled (CMPEN = 1), this register (ECAP_CNTCMP) is used to compare with the capture counter (ECAP_CNT).
+     * |        |          |If the reload control is enabled (RLDEN[n] = 1, n=0~3), an overflow event or capture events will trigger the hardware to load the value of this register (ECAP_CNTCMP) into ECAP_CNT.
+     * @var ECAP_T::CTL0
+     * Offset: 0x14  Input Capture Control Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |NFCLKSEL  |Noise Filter Clock Pre-divide Selection
+     * |        |          |To determine the sampling frequency of the Noise Filter clock
+     * |        |          |000 = CAP_CLK.
+     * |        |          |001 = CAP_CLK/2.
+     * |        |          |010 = CAP_CLK/4.
+     * |        |          |011 = CAP_CLK/16.
+     * |        |          |100 = CAP_CLK/32.
+     * |        |          |101 = CAP_CLK/64.
+     * |[3]     |CAPNFDIS  |Input Capture Noise Filter Disable Control
+     * |        |          |0 = Noise filter of Input Capture Enabled.
+     * |        |          |1 = Noise filter of Input Capture Disabled (Bypass).
+     * |[4]     |IC0EN     |Port Pin IC0 Input to Input Capture Unit Enable Control
+     * |        |          |0 = IC0 input to Input Capture Unit Disabled.
+     * |        |          |1 = IC0 input to Input Capture Unit Enabled.
+     * |[5]     |IC1EN     |Port Pin IC1 Input to Input Capture Unit Enable Control
+     * |        |          |0 = IC1 input to Input Capture Unit Disabled.
+     * |        |          |1 = IC1 input to Input Capture Unit Enabled.
+     * |[6]     |IC2EN     |Port Pin IC2 Input to Input Capture Unit Enable Control
+     * |        |          |0 = IC2 input to Input Capture Unit Disabled.
+     * |        |          |1 = IC2 input to Input Capture Unit Enabled.
+     * |[9:8]   |CAPSEL0   |CAP0 Input Source Selection
+     * |        |          |00 = CAP0 input is from port pin ICAP0.
+     * |        |          |01 = Reserved.
+     * |        |          |10 = CAP0 input is from signal CHA of QEI controller unit n.
+     * |        |          |11 = Reserved.
+     * |        |          |Note: Input capture unit n matches QEIn, where n = 0~1.
+     * |[11:10] |CAPSEL1   |CAP1 Input Source Selection
+     * |        |          |00 = CAP1 input is from port pin ICAP1.
+     * |        |          |01 = Reserved.
+     * |        |          |10 = CAP1 input is from signal CHB of QEI controller unit n.
+     * |        |          |11 = Reserved.
+     * |        |          |Note: Input capture unit n matches QEIn, where n = 0~1.
+     * |[13:12] |CAPSEL2   |CAP2 Input Source Selection
+     * |        |          |00 = CAP2 input is from port pin ICAP2.
+     * |        |          |01 = Reserved.
+     * |        |          |10 = CAP2 input is from signal CHX of QEI controller unit n.
+     * |        |          |11 = Reserved.
+     * |        |          |Note: Input capture unit n matches QEIn, where n = 0~1.
+     * |[16]    |CAPIEN0   |Input Capture Channel 0 Interrupt Enable Control
+     * |        |          |0 = The flag CAPTF0 can trigger Input Capture interrupt Disabled.
+     * |        |          |1 = The flag CAPTF0 can trigger Input Capture interrupt Enabled.
+     * |[17]    |CAPIEN1   |Input Capture Channel 1 Interrupt Enable Control
+     * |        |          |0 = The flag CAPTF1 can trigger Input Capture interrupt Disabled.
+     * |        |          |1 = The flag CAPTF1 can trigger Input Capture interrupt Enabled.
+     * |[18]    |CAPIEN2   |Input Capture Channel 2 Interrupt Enable Control
+     * |        |          |0 = The flag CAPTF2 can trigger Input Capture interrupt Disabled.
+     * |        |          |1 = The flag CAPTF2 can trigger Input Capture interrupt Enabled.
+     * |[20]    |OVIEN     |CAPOVF Trigger Input Capture Interrupt Enable Control
+     * |        |          |0 = The flag CAPOVF can trigger Input Capture interrupt Disabled.
+     * |        |          |1 = The flag CAPOVF can trigger Input Capture interrupt Enabled.
+     * |[21]    |CMPIEN    |CAPCMPF Trigger Input Capture Interrupt Enable Control
+     * |        |          |0 = The flag CAPCMPF can trigger Input Capture interrupt Disabled.
+     * |        |          |1 = The flag CAPCMPF can trigger Input Capture interrupt Enabled.
+     * |[24]    |CNTEN     |Input Capture Counter Start Counting Control
+     * |        |          |Setting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the .
+     * |        |          |0 = ECAP_CNT stop counting.
+     * |        |          |1 = ECAP_CNT starts up-counting.
+     * |[25]    |CMPCLREN  |Input Capture Counter Cleared by Compare-match Control
+     * |        |          |If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to 0 when the compare-match event (CAPCMPF = 1) occurs.
+     * |        |          |0 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Disabled.
+     * |        |          |1 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Enabled.
+     * |[28]    |CMPEN     |Compare Function Enable Control
+     * |        |          |The compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CAPCMPF will be set.
+     * |        |          |0 = The compare function Disabled.
+     * |        |          |1 = The compare function Enabled.
+     * |[29]    |CAPEN     |Input Capture Timer/Counter Enable Control
+     * |        |          |0 = Input Capture function Disabled.
+     * |        |          |1 = Input Capture function Enabled.
+     * @var ECAP_T::CTL1
+     * Offset: 0x18  Input Capture Control Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |EDGESEL0  |Channel 0 Captured Edge Selection
+     * |        |          |Input capture0 can detect falling edge change only, rising edge change only or both edge change
+     * |        |          |00 = Detect rising edge only.
+     * |        |          |01 = Detect falling edge only.
+     * |        |          |1x = Detect both rising and falling edge.
+     * |[3:2]   |EDGESEL1  |Channel 1 Captured Edge Selection
+     * |        |          |Input capture1 can detect falling edge change only, rising edge change only or both edge change
+     * |        |          |00 = Detect rising edge only.
+     * |        |          |01 = Detect falling edge only.
+     * |        |          |1x = Detect both rising and falling edge.
+     * |[5:4]   |EDGESEL2  |Channel 2 Captured Edge Selection
+     * |        |          |Input capture2 can detect falling edge change only, rising edge change only or both edge changes
+     * |        |          |00 = Detect rising edge only.
+     * |        |          |01 = Detect falling edge only.
+     * |        |          |1x = Detect both rising and falling edge.
+     * |[8]     |CAP0RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE0 Enable Bit
+     * |        |          |0 = The reload triggered by Event CAPTE0 Disabled.
+     * |        |          |1 = The reload triggered by Event CAPTE0 Enabled.
+     * |[9]     |CAP1RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE1 Enable Bit
+     * |        |          |0 = The reload triggered by Event CAPTE1 Disabled.
+     * |        |          |1 = The reload triggered by Event CAPTE1 Enabled.
+     * |[10]    |CAP2RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE2 Enable Bit
+     * |        |          |0 = The reload triggered by Event CAPTE2 Disabled.
+     * |        |          |1 = The reload triggered by Event CAPTE2 Enabled.
+     * |[11]    |OVRLDEN   |Capture Counteru2019s Reload Function Triggered by Overflow Enable Bit
+     * |        |          |0 = The reload triggered by CAPOV Disabled.
+     * |        |          |1 = The reload triggered by CAPOV Enabled.
+     * |[14:12] |CLKSEL    |Capture Timer Clock Divide Selection
+     * |        |          |The capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0].
+     * |        |          |000 = CAP_CLK/1.
+     * |        |          |001 = CAP_CLK/4.
+     * |        |          |010 = CAP_CLK/16.
+     * |        |          |011 = CAP_CLK/32.
+     * |        |          |100 = CAP_CLK/64.
+     * |        |          |101 = CAP_CLK/96.
+     * |        |          |110 = CAP_CLK/112.
+     * |        |          |111 = CAP_CLK/128.
+     * |[17:16] |CNTSRCSEL |Capture Timer/Counter Clock Source Selection
+     * |        |          |Select the capture timer/counter clock source.
+     * |        |          |00 = CAP_CLK (default).
+     * |        |          |01 = CAP0.
+     * |        |          |10 = CAP1.
+     * |        |          |11 = CAP2.
+     * |[20]    |CAP0CLREN |Capture Counter Cleared by Capture Event0 Control
+     * |        |          |0 = Event CAPTE0 can clear capture counter (ECAP_CNT) Disabled.
+     * |        |          |1 = Event CAPTE0 can clear capture counter (ECAP_CNT) Enabled.
+     * |[21]    |CAP1CLREN |Capture Counter Cleared by Capture Event1 Control
+     * |        |          |0 = Event CAPTE1 can clear capture counter (ECAP_CNT) Disabled.
+     * |        |          |1 = Event CAPTE1 can clear capture counter (ECAP_CNT) Enabled.
+     * |[22]    |CAP2CLREN |Capture Counter Cleared by Capture Event2 Control
+     * |        |          |0 = Event CAPTE2 can clear capture counter (ECAP_CNT) Disabled.
+     * |        |          |1 = Event CAPTE2 can clear capture counter (ECAP_CNT) Enabled.
+     * @var ECAP_T::STATUS
+     * Offset: 0x1C  Input Capture Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CAPTF0    |Input Capture Channel 0 Triggered Flag
+     * |        |          |When the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high.
+     * |        |          |0 = No valid edge change has been detected at CAP0 input since last clear.
+     * |        |          |1 = At least a valid edge change has been detected at CAP0 input since last clear.
+     * |        |          |Note: This bit is only cleared by writing 1 to it.
+     * |[1]     |CAPTF1    |Input Capture Channel 1 Triggered Flag
+     * |        |          |When the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high.
+     * |        |          |0 = No valid edge change has been detected at CAP1 input since last clear.
+     * |        |          |1 = At least a valid edge change has been detected at CAP1 input since last clear.
+     * |        |          |Note: This bit is only cleared by writing 1 to it.
+     * |[2]     |CAPTF2    |Input Capture Channel 2 Triggered Flag
+     * |        |          |When the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high.
+     * |        |          |0 = No valid edge change has been detected at CAP2 input since last clear.
+     * |        |          |1 = At least a valid edge change has been detected at CAP2 input since last clear.
+     * |        |          |Note: This bit is only cleared by writing 1 to it.
+     * |[4]     |CAPCMPF   |Input Capture Compare-match Flag
+     * |        |          |If the input capture compare function is enabled, the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value.
+     * |        |          |0 = ECAP_CNT has not matched ECAP_CNTCMP value since last clear.
+     * |        |          |1 = ECAP_CNT has matched ECAP_CNTCMP value at least once since last clear.
+     * |        |          |Note: This bit is only cleared by writing 1 to it.
+     * |[5]     |CAPOVF    |Input Capture Counter Overflow Flag
+     * |        |          |Flag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.
+     * |        |          |0 = No overflow event has occurred since last clear.
+     * |        |          |1 = Overflow event(s) has/have occurred since last clear.
+     * |        |          |Note: This bit is only cleared by writing 1 to it.
+     * |[6]     |CAP0      |Value of Input Channel 0, CAP0 (Read Only)
+     * |        |          |Reflecting the value of input channel 0, CAP0
+     * |        |          |(The bit is read only and write is ignored)
+     * |[7]     |CAP1      |Value of Input Channel 1, CAP1 (Read Only)
+     * |        |          |Reflecting the value of input channel 1, CAP1
+     * |        |          |(The bit is read only and write is ignored)
+     * |[8]     |CAP2      |Value of Input Channel 2, CAP2 (Read Only)
+     * |        |          |Reflecting the value of input channel 2, CAP2.
+     * |        |          |(The bit is read only and write is ignored)
+     */
+    __IO uint32_t CNT;                   /*!< [0x0000] Input Capture Counter                                            */
+    __IO uint32_t HLD0;                  /*!< [0x0004] Input Capture Hold Register 0                                    */
+    __IO uint32_t HLD1;                  /*!< [0x0008] Input Capture Hold Register 1                                    */
+    __IO uint32_t HLD2;                  /*!< [0x000c] Input Capture Hold Register 2                                    */
+    __IO uint32_t CNTCMP;                /*!< [0x0010] Input Capture Compare Register                                   */
+    __IO uint32_t CTL0;                  /*!< [0x0014] Input Capture Control Register 0                                 */
+    __IO uint32_t CTL1;                  /*!< [0x0018] Input Capture Control Register 1                                 */
+    __IO uint32_t STATUS;                /*!< [0x001c] Input Capture Status Register                                    */
+
+} ECAP_T;
+
+/**
+  @addtogroup ECAP_CONST ECAP Bit Field Definition
+  Constant Definitions for ECAP Controller
+  @{
+*/
+
+#define ECAP_CNT_CNT_Pos                 (0)                                               /*!< ECAP_T::CNT: CNT Position              */
+#define ECAP_CNT_CNT_Msk                 (0xfffffful << ECAP_CNT_CNT_Pos)                  /*!< ECAP_T::CNT: CNT Mask                  */
+
+#define ECAP_HLD0_HOLD_Pos               (0)                                               /*!< ECAP_T::HLD0: HOLD Position            */
+#define ECAP_HLD0_HOLD_Msk               (0xfffffful << ECAP_HLD0_HOLD_Pos)                /*!< ECAP_T::HLD0: HOLD Mask                */
+
+#define ECAP_HLD1_HOLD_Pos               (0)                                               /*!< ECAP_T::HLD1: HOLD Position            */
+#define ECAP_HLD1_HOLD_Msk               (0xfffffful << ECAP_HLD1_HOLD_Pos)                /*!< ECAP_T::HLD1: HOLD Mask                */
+
+#define ECAP_HLD2_HOLD_Pos               (0)                                               /*!< ECAP_T::HLD2: HOLD Position            */
+#define ECAP_HLD2_HOLD_Msk               (0xfffffful << ECAP_HLD2_HOLD_Pos)                /*!< ECAP_T::HLD2: HOLD Mask                */
+
+#define ECAP_CNTCMP_CNTCMP_Pos           (0)                                               /*!< ECAP_T::CNTCMP: CNTCMP Position        */
+#define ECAP_CNTCMP_CNTCMP_Msk           (0xfffffful << ECAP_CNTCMP_CNTCMP_Pos)            /*!< ECAP_T::CNTCMP: CNTCMP Mask            */
+
+#define ECAP_CTL0_NFCLKSEL_Pos           (0)                                               /*!< ECAP_T::CTL0: NFCLKSEL Position        */
+#define ECAP_CTL0_NFCLKSEL_Msk           (0x7ul << ECAP_CTL0_NFCLKSEL_Pos)                 /*!< ECAP_T::CTL0: NFCLKSEL Mask            */
+
+#define ECAP_CTL0_CAPNFDIS_Pos           (3)                                               /*!< ECAP_T::CTL0: CAPNFDIS Position        */
+#define ECAP_CTL0_CAPNFDIS_Msk           (0x1ul << ECAP_CTL0_CAPNFDIS_Pos)                 /*!< ECAP_T::CTL0: CAPNFDIS Mask            */
+
+#define ECAP_CTL0_IC0EN_Pos              (4)                                               /*!< ECAP_T::CTL0: IC0EN Position           */
+#define ECAP_CTL0_IC0EN_Msk              (0x1ul << ECAP_CTL0_IC0EN_Pos)                    /*!< ECAP_T::CTL0: IC0EN Mask               */
+
+#define ECAP_CTL0_IC1EN_Pos              (5)                                               /*!< ECAP_T::CTL0: IC1EN Position           */
+#define ECAP_CTL0_IC1EN_Msk              (0x1ul << ECAP_CTL0_IC1EN_Pos)                    /*!< ECAP_T::CTL0: IC1EN Mask               */
+
+#define ECAP_CTL0_IC2EN_Pos              (6)                                               /*!< ECAP_T::CTL0: IC2EN Position           */
+#define ECAP_CTL0_IC2EN_Msk              (0x1ul << ECAP_CTL0_IC2EN_Pos)                    /*!< ECAP_T::CTL0: IC2EN Mask               */
+
+#define ECAP_CTL0_CAPSEL0_Pos            (8)                                               /*!< ECAP_T::CTL0: CAPSEL0 Position         */
+#define ECAP_CTL0_CAPSEL0_Msk            (0x3ul << ECAP_CTL0_CAPSEL0_Pos)                  /*!< ECAP_T::CTL0: CAPSEL0 Mask             */
+
+#define ECAP_CTL0_CAPSEL1_Pos            (10)                                              /*!< ECAP_T::CTL0: CAPSEL1 Position         */
+#define ECAP_CTL0_CAPSEL1_Msk            (0x3ul << ECAP_CTL0_CAPSEL1_Pos)                  /*!< ECAP_T::CTL0: CAPSEL1 Mask             */
+
+#define ECAP_CTL0_CAPSEL2_Pos            (12)                                              /*!< ECAP_T::CTL0: CAPSEL2 Position         */
+#define ECAP_CTL0_CAPSEL2_Msk            (0x3ul << ECAP_CTL0_CAPSEL2_Pos)                  /*!< ECAP_T::CTL0: CAPSEL2 Mask             */
+
+#define ECAP_CTL0_CAPIEN0_Pos            (16)                                              /*!< ECAP_T::CTL0: CAPIEN0 Position         */
+#define ECAP_CTL0_CAPIEN0_Msk            (0x1ul << ECAP_CTL0_CAPIEN0_Pos)                  /*!< ECAP_T::CTL0: CAPIEN0 Mask             */
+
+#define ECAP_CTL0_CAPIEN1_Pos            (17)                                              /*!< ECAP_T::CTL0: CAPIEN1 Position         */
+#define ECAP_CTL0_CAPIEN1_Msk            (0x1ul << ECAP_CTL0_CAPIEN1_Pos)                  /*!< ECAP_T::CTL0: CAPIEN1 Mask             */
+
+#define ECAP_CTL0_CAPIEN2_Pos            (18)                                              /*!< ECAP_T::CTL0: CAPIEN2 Position         */
+#define ECAP_CTL0_CAPIEN2_Msk            (0x1ul << ECAP_CTL0_CAPIEN2_Pos)                  /*!< ECAP_T::CTL0: CAPIEN2 Mask             */
+
+#define ECAP_CTL0_OVIEN_Pos              (20)                                              /*!< ECAP_T::CTL0: OVIEN Position           */
+#define ECAP_CTL0_OVIEN_Msk              (0x1ul << ECAP_CTL0_OVIEN_Pos)                    /*!< ECAP_T::CTL0: OVIEN Mask               */
+
+#define ECAP_CTL0_CMPIEN_Pos             (21)                                              /*!< ECAP_T::CTL0: CMPIEN Position          */
+#define ECAP_CTL0_CMPIEN_Msk             (0x1ul << ECAP_CTL0_CMPIEN_Pos)                   /*!< ECAP_T::CTL0: CMPIEN Mask              */
+
+#define ECAP_CTL0_CNTEN_Pos              (24)                                              /*!< ECAP_T::CTL0: CNTEN Position           */
+#define ECAP_CTL0_CNTEN_Msk              (0x1ul << ECAP_CTL0_CNTEN_Pos)                    /*!< ECAP_T::CTL0: CNTEN Mask               */
+
+#define ECAP_CTL0_CMPCLREN_Pos           (25)                                              /*!< ECAP_T::CTL0: CMPCLREN Position        */
+#define ECAP_CTL0_CMPCLREN_Msk           (0x1ul << ECAP_CTL0_CMPCLREN_Pos)                 /*!< ECAP_T::CTL0: CMPCLREN Mask            */
+
+#define ECAP_CTL0_CMPEN_Pos              (28)                                              /*!< ECAP_T::CTL0: CMPEN Position           */
+#define ECAP_CTL0_CMPEN_Msk              (0x1ul << ECAP_CTL0_CMPEN_Pos)                    /*!< ECAP_T::CTL0: CMPEN Mask               */
+
+#define ECAP_CTL0_CAPEN_Pos              (29)                                              /*!< ECAP_T::CTL0: CAPEN Position           */
+#define ECAP_CTL0_CAPEN_Msk              (0x1ul << ECAP_CTL0_CAPEN_Pos)                    /*!< ECAP_T::CTL0: CAPEN Mask               */
+
+#define ECAP_CTL1_EDGESEL0_Pos           (0)                                               /*!< ECAP_T::CTL1: EDGESEL0 Position        */
+#define ECAP_CTL1_EDGESEL0_Msk           (0x3ul << ECAP_CTL1_EDGESEL0_Pos)                 /*!< ECAP_T::CTL1: EDGESEL0 Mask            */
+
+#define ECAP_CTL1_EDGESEL1_Pos           (2)                                               /*!< ECAP_T::CTL1: EDGESEL1 Position        */
+#define ECAP_CTL1_EDGESEL1_Msk           (0x3ul << ECAP_CTL1_EDGESEL1_Pos)                 /*!< ECAP_T::CTL1: EDGESEL1 Mask            */
+
+#define ECAP_CTL1_EDGESEL2_Pos           (4)                                               /*!< ECAP_T::CTL1: EDGESEL2 Position        */
+#define ECAP_CTL1_EDGESEL2_Msk           (0x3ul << ECAP_CTL1_EDGESEL2_Pos)                 /*!< ECAP_T::CTL1: EDGESEL2 Mask            */
+
+#define ECAP_CTL1_CAP0RLDEN_Pos          (8)                                               /*!< ECAP_T::CTL1: CAP0RLDEN Position       */
+#define ECAP_CTL1_CAP0RLDEN_Msk          (0x1ul << ECAP_CTL1_CAP0RLDEN_Pos)                /*!< ECAP_T::CTL1: CAP0RLDEN Mask           */
+
+#define ECAP_CTL1_CAP1RLDEN_Pos          (9)                                               /*!< ECAP_T::CTL1: CAP1RLDEN Position       */
+#define ECAP_CTL1_CAP1RLDEN_Msk          (0x1ul << ECAP_CTL1_CAP1RLDEN_Pos)                /*!< ECAP_T::CTL1: CAP1RLDEN Mask           */
+
+#define ECAP_CTL1_CAP2RLDEN_Pos          (10)                                              /*!< ECAP_T::CTL1: CAP2RLDEN Position       */
+#define ECAP_CTL1_CAP2RLDEN_Msk          (0x1ul << ECAP_CTL1_CAP2RLDEN_Pos)                /*!< ECAP_T::CTL1: CAP2RLDEN Mask           */
+
+#define ECAP_CTL1_OVRLDEN_Pos            (11)                                              /*!< ECAP_T::CTL1: OVRLDEN Position         */
+#define ECAP_CTL1_OVRLDEN_Msk            (0x1ul << ECAP_CTL1_OVRLDEN_Pos)                  /*!< ECAP_T::CTL1: OVRLDEN Mask             */
+
+#define ECAP_CTL1_CLKSEL_Pos             (12)                                              /*!< ECAP_T::CTL1: CLKSEL Position          */
+#define ECAP_CTL1_CLKSEL_Msk             (0x7ul << ECAP_CTL1_CLKSEL_Pos)                   /*!< ECAP_T::CTL1: CLKSEL Mask              */
+
+#define ECAP_CTL1_CNTSRCSEL_Pos          (16)                                              /*!< ECAP_T::CTL1: CNTSRCSEL Position       */
+#define ECAP_CTL1_CNTSRCSEL_Msk          (0x3ul << ECAP_CTL1_CNTSRCSEL_Pos)                /*!< ECAP_T::CTL1: CNTSRCSEL Mask           */
+
+#define ECAP_CTL1_CAP0CLREN_Pos          (20)                                              /*!< ECAP_T::CTL1: CAP0CLREN Position       */
+#define ECAP_CTL1_CAP0CLREN_Msk          (0x1ul << ECAP_CTL1_CAP0CLREN_Pos)                /*!< ECAP_T::CTL1: CAP0CLREN Mask           */
+
+#define ECAP_CTL1_CAP1CLREN_Pos          (21)                                              /*!< ECAP_T::CTL1: CAP1CLREN Position       */
+#define ECAP_CTL1_CAP1CLREN_Msk          (0x1ul << ECAP_CTL1_CAP1CLREN_Pos)                /*!< ECAP_T::CTL1: CAP1CLREN Mask           */
+
+#define ECAP_CTL1_CAP2CLREN_Pos          (22)                                              /*!< ECAP_T::CTL1: CAP2CLREN Position       */
+#define ECAP_CTL1_CAP2CLREN_Msk          (0x1ul << ECAP_CTL1_CAP2CLREN_Pos)                /*!< ECAP_T::CTL1: CAP2CLREN Mask           */
+
+#define ECAP_STATUS_CAPTF0_Pos           (0)                                               /*!< ECAP_T::STATUS: CAPTF0 Position        */
+#define ECAP_STATUS_CAPTF0_Msk           (0x1ul << ECAP_STATUS_CAPTF0_Pos)                 /*!< ECAP_T::STATUS: CAPTF0 Mask            */
+
+#define ECAP_STATUS_CAPTF1_Pos           (1)                                               /*!< ECAP_T::STATUS: CAPTF1 Position        */
+#define ECAP_STATUS_CAPTF1_Msk           (0x1ul << ECAP_STATUS_CAPTF1_Pos)                 /*!< ECAP_T::STATUS: CAPTF1 Mask            */
+
+#define ECAP_STATUS_CAPTF2_Pos           (2)                                               /*!< ECAP_T::STATUS: CAPTF2 Position        */
+#define ECAP_STATUS_CAPTF2_Msk           (0x1ul << ECAP_STATUS_CAPTF2_Pos)                 /*!< ECAP_T::STATUS: CAPTF2 Mask            */
+
+#define ECAP_STATUS_CAPCMPF_Pos          (4)                                               /*!< ECAP_T::STATUS: CAPCMPF Position       */
+#define ECAP_STATUS_CAPCMPF_Msk          (0x1ul << ECAP_STATUS_CAPCMPF_Pos)                /*!< ECAP_T::STATUS: CAPCMPF Mask           */
+
+#define ECAP_STATUS_CAPOVF_Pos           (5)                                               /*!< ECAP_T::STATUS: CAPOVF Position        */
+#define ECAP_STATUS_CAPOVF_Msk           (0x1ul << ECAP_STATUS_CAPOVF_Pos)                 /*!< ECAP_T::STATUS: CAPOVF Mask            */
+
+#define ECAP_STATUS_CAP0_Pos             (8)                                               /*!< ECAP_T::STATUS: CAP0 Position          */
+#define ECAP_STATUS_CAP0_Msk             (0x1ul << ECAP_STATUS_CAP0_Pos)                   /*!< ECAP_T::STATUS: CAP0 Mask              */
+
+#define ECAP_STATUS_CAP1_Pos             (9)                                               /*!< ECAP_T::STATUS: CAP1 Position          */
+#define ECAP_STATUS_CAP1_Msk             (0x1ul << ECAP_STATUS_CAP1_Pos)                   /*!< ECAP_T::STATUS: CAP1 Mask              */
+
+#define ECAP_STATUS_CAP2_Pos             (10)                                              /*!< ECAP_T::STATUS: CAP2 Position          */
+#define ECAP_STATUS_CAP2_Msk             (0x1ul << ECAP_STATUS_CAP2_Pos)                   /*!< ECAP_T::STATUS: CAP2 Mask              */
+
+/**@}*/ /* ECAP_CONST */
+/**@}*/ /* end of ECAP register group */
+/**@}*/ /* end of REGISTER group */
+
+
+#endif /* __ECAP_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/epwm_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/epwm_reg.h
new file mode 100644
index 0000000000..813f8b1ae0
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/epwm_reg.h
@@ -0,0 +1,4001 @@
+/**************************************************************************//**
+ * @file     epwm_reg.h
+ * @version  V1.00
+ * @brief    EPWM register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __EPWM_REG_H__
+#define __EPWM_REG_H__
+
+/**
+  @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+
+/*---------------------- Enhanced Pulse Width Modulation Controller -------------------------*/
+/**
+  @addtogroup EPWM Enhanced Pulse Width Modulation Controller(EPWM)
+  Memory Mapped Structure for EPWM Controller
+  @{
+*/
+
+typedef struct
+{
+    /**
+     * @var ECAPDAT_T::RCAPDAT
+     * Offset: 0x20C  EPWM Rising Capture Data Register 0~5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |RCAPDAT   |EPWM Rising Capture Data (Read Only)
+     * |        |          |When rising capture condition happened, the EPWM counter value will be saved in this register.
+     * @var ECAPDAT_T::FCAPDAT
+     * Offset: 0x210  EPWM Falling Capture Data Register 0~5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |FCAPDAT   |EPWM Falling Capture Data (Read Only)
+     * |        |          |When falling capture condition happened, the EPWM counter value will be saved in this register.
+     */
+    __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] EPWM Rising Capture Data Register 0~5 */
+    __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] EPWM Falling Capture Data Register 0~5 */
+} ECAPDAT_T;
+
+typedef struct
+{
+
+
+    /**
+     * @var EPWM_T::CTL0
+     * Offset: 0x00  EPWM Control Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CTRLD0    |Center Re-load
+     * |        |          |In up-down counter type, PERIOD0 register will load to PBUF0 register at the end point of each period.
+     * |        |          |CMPDAT0 register will load to CMPBUF0 register at the center point of a period.
+     * |[1]     |CTRLD1    |Center Re-load
+     * |        |          |In up-down counter type, PERIOD1 register will load to PBUF1 register at the end point of each period.
+     * |        |          |CMPDAT1 register will load to CMPBUF1 register at the center point of a period.
+     * |[2]     |CTRLD2    |Center Re-load
+     * |        |          |In up-down counter type, PERIOD2 register will load to PBUF2 register at the end point of each period.
+     * |        |          |CMPDAT2 register will load to CMPBUF2 register at the center point of a period.
+     * |[3]     |CTRLD3    |Center Re-load
+     * |        |          |In up-down counter type, PERIOD3 register will load to PBUF3 register at the end point of each period.
+     * |        |          |CMPDAT3 register will load to CMPBUF3 register at the center point of a period.
+     * |[4]     |CTRLD4    |Center Re-load
+     * |        |          |In up-down counter type, PERIOD4 register will load to PBUF4 register at the end point of each period.
+     * |        |          |CMPDAT4 register will load to CMPBUF4 register at the center point of a period.
+     * |[5]     |CTRLD5    |Center Re-load
+     * |        |          |In up-down counter type, PERIOD5 register will load to PBUF5 register at the end point of each period.
+     * |        |          |CMPDAT5 register will load to CMPBUF5 register at the center point of a period.
+     * |[8]     |WINLDEN0  |Window Load Enable Bits
+     * |        |          |0 = PERIOD0 register will load to PBUF0 register at the end point of each period.
+     * |        |          |CMPDAT0 register will load to CMPBUF0 register at the end point or center point of each period by setting CTRLD0 bit.
+     * |        |          |1 = PERIOD0 register will load to PBUF0 and CMPDAT0 registers will load to CMPBUF0 register at the end point of each period when valid reload window is set.
+     * |        |          |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success.
+     * |[9]     |WINLDEN1  |Window Load Enable Bits
+     * |        |          |0 = PERIOD1 register will load to PBUF1 register at the end point of each period.
+     * |        |          |CMPDAT1 register will load to CMPBUF1 register at the end point or center point of each period by setting CTRLD1 bit.
+     * |        |          |1 = PERIOD1 register will load to PBUF1 and CMPDAT1 registers will load to CMPBUF1 register at the end point of each period when valid reload window is set.
+     * |        |          |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success.
+     * |[10]    |WINLDEN2  |Window Load Enable Bits
+     * |        |          |0 = PERIOD2 register will load to PBUF2 register at the end point of each period.
+     * |        |          |CMPDAT2 register will load to CMPBUF2 register at the end point or center point of each period by setting CTRLD2 bit.
+     * |        |          |1 = PERIOD2 register will load to PBUF2 and CMPDAT2 registers will load to CMPBUF2 register at the end point of each period when valid reload window is set.
+     * |        |          |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success.
+     * |[11]    |WINLDEN3  |Window Load Enable Bits
+     * |        |          |0 = PERIOD3 register will load to PBUF3 register at the end point of each period.
+     * |        |          |CMPDAT3 register will load to CMPBUF3 register at the end point or center point of each period by setting CTRLD3 bit.
+     * |        |          |1 = PERIOD3 register will load to PBUF3 and CMPDAT3 registers will load to CMPBUF3 register at the end point of each period when valid reload window is set.
+     * |        |          |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success.
+     * |[12]    |WINLDEN4  |Window Load Enable Bits
+     * |        |          |0 = PERIOD4 register will load to PBUF4 register at the end point of each period.
+     * |        |          |CMPDAT4 register will load to CMPBUF4 register at the end point or center point of each period by setting CTRLD4 bit.
+     * |        |          |1 = PERIOD4 register will load to PBUF4 and CMPDAT4 registers will load to CMPBUF4 register at the end point of each period when valid reload window is set.
+     * |        |          |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success.
+     * |[13]    |WINLDEN5  |Window Load Enable Bits
+     * |        |          |0 = PERIOD5 register will load to PBUF5 register at the end point of each period.
+     * |        |          |CMPDAT5 register will load to CMPBUF5 register at the end point or center point of each period by setting CTRLD5 bit.
+     * |        |          |1 = PERIOD5 register will load to PBUF5 and CMPDAT5 registers will load to CMPBUF5 register at the end point of each period when valid reload window is set.
+     * |        |          |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success.
+     * |[16]    |IMMLDEN0  |Immediately Load Enable Bits
+     * |        |          |0 = PERIOD0 register will load to PBUF0 register at the end point of each period.
+     * |        |          |CMPDAT0 register will load to CMPBUF0 register at the end point or center point of each period by setting CTRLD0 bit.
+     * |        |          |1 = PERIOD0/CMPDAT0 registers will load to PBUF0 and CMPBUF0 register immediately when software update PERIOD0/CMPDAT0 register.
+     * |        |          |Note: If IMMLDEN0 bit is enabled, WINLDEN0 bit and CTRLD0 bits will be invalid.
+     * |[17]    |IMMLDEN1  |Immediately Load Enable Bits
+     * |        |          |0 = PERIOD1 register will load to PBUF1 register at the end point of each period.
+     * |        |          |CMPDAT1 register will load to CMPBUF1 register at the end point or center point of each period by setting CTRLD1 bit.
+     * |        |          |1 = PERIOD1/CMPDAT1 registers will load to PBUF1 and CMPBUF1 register immediately when software update PERIOD1/CMPDAT1 register.
+     * |        |          |Note: If IMMLDEN1 bit is enabled, WINLDEN1 bit and CTRLD1 bits will be invalid.
+     * |[18]    |IMMLDEN2  |Immediately Load Enable Bits
+     * |        |          |0 = PERIOD2 register will load to PBUF2 register at the end point of each period.
+     * |        |          |CMPDAT2 register will load to CMPBUF2 register at the end point or center point of each period by setting CTRLD2 bit.
+     * |        |          |1 = PERIOD2/CMPDAT2 registers will load to PBUF2 and CMPBUF2 register immediately when software update PERIOD2/CMPDAT2 register.
+     * |        |          |Note: If IMMLDEN2 bit is enabled, WINLDEN2 bit and CTRLD2 bits will be invalid.
+     * |[19]    |IMMLDEN3  |Immediately Load Enable Bits
+     * |        |          |0 = PERIOD3 register will load to PBUF3 register at the end point of each period.
+     * |        |          |CMPDAT3 register will load to CMPBUF3 register at the end point or center point of each period by setting CTRLD3 bit.
+     * |        |          |1 = PERIOD3/CMPDAT3 registers will load to PBUF3 and CMPBUF3 register immediately when software update PERIOD3/CMPDAT3 register.
+     * |        |          |Note: If IMMLDEN3 bit is enabled, WINLDEN3 bit and CTRLD3 bits will be invalid.
+     * |[20]    |IMMLDEN4  |Immediately Load Enable Bits
+     * |        |          |0 = PERIOD4 register will load to PBUF4 register at the end point of each period.
+     * |        |          |CMPDAT4 register will load to CMPBUF4 register at the end point or center point of each period by setting CTRLD4 bit.
+     * |        |          |1 = PERIOD4/CMPDAT4 registers will load to PBUF4 and CMPBUF4 register immediately when software update PERIOD4/CMPDAT4 register.
+     * |        |          |Note: If IMMLDEN4 bit is enabled, WINLDEN4 bit and CTRLD4 bits will be invalid.
+     * |[21]    |IMMLDEN5  |Immediately Load Enable Bits
+     * |        |          |0 = PERIOD5 register will load to PBUF5 register at the end point of each period.
+     * |        |          |CMPDAT5 register will load to CMPBUF5 register at the end point or center point of each period by setting CTRLD5 bit.
+     * |        |          |1 = PERIOD5/CMPDAT5 registers will load to PBUF5 and CMPBUF5 register immediately when software update PERIOD5/CMPDAT5 register.
+     * |        |          |Note: If IMMLDEN5 bit is enabled, WINLDEN5 bit and CTRLD5 bits will be invalid.
+     * |[24]    |GROUPEN   |Group Function Enable Bit
+     * |        |          |0 = The output waveform of each EPWM channel are independent.
+     * |        |          |1 = Unify the EPWMx_CH2 and EPWMx_CH4 to output the same waveform as EPWMx_CH0 and unify the EPWMx_CH3 and EPWMx_CH5 to output the same waveform as EPWMx_CH1.
+     * |[30]    |DBGHALT   |ICE Debug Mode Counter Halt (Write Protect)
+     * |        |          |If counter halt is enabled, EPWM all counters will keep current value until exit ICE debug mode.
+     * |        |          |0 = ICE debug mode counter halt disable.
+     * |        |          |1 = ICE debug mode counter halt enable.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[31]    |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect)
+     * |        |          |0 = ICE debug mode acknowledgement effects EPWM output.
+     * |        |          |EPWM pin will be forced as tri-state while ICE debug mode acknowledged.
+     * |        |          |1 = ICE debug mode acknowledgement disabled.
+     * |        |          |EPWM pin will keep output no matter ICE debug mode acknowledged or not.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * @var EPWM_T::CTL1
+     * Offset: 0x04  EPWM Control Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |CNTTYPE0  |EPWM Counter Behavior Type
+     * |        |          |00 = Up counter type (supports in capture mode).
+     * |        |          |01 = Down count type (supports in capture mode).
+     * |        |          |10 = Up-down counter type.
+     * |        |          |11 = Reserved.
+     * |[3:2]   |CNTTYPE1  |EPWM Counter Behavior Type
+     * |        |          |00 = Up counter type (supports in capture mode).
+     * |        |          |01 = Down count type (supports in capture mode).
+     * |        |          |10 = Up-down counter type.
+     * |        |          |11 = Reserved.
+     * |[5:4]   |CNTTYPE2  |EPWM Counter Behavior Type
+     * |        |          |00 = Up counter type (supports in capture mode).
+     * |        |          |01 = Down count type (supports in capture mode).
+     * |        |          |10 = Up-down counter type.
+     * |        |          |11 = Reserved.
+     * |[7:6]   |CNTTYPE3  |EPWM Counter Behavior Type
+     * |        |          |00 = Up counter type (supports in capture mode).
+     * |        |          |01 = Down count type (supports in capture mode).
+     * |        |          |10 = Up-down counter type.
+     * |        |          |11 = Reserved.
+     * |[9:8]   |CNTTYPE4  |EPWM Counter Behavior Type
+     * |        |          |00 = Up counter type (supports in capture mode).
+     * |        |          |01 = Down count type (supports in capture mode).
+     * |        |          |10 = Up-down counter type.
+     * |        |          |11 = Reserved.
+     * |[11:10] |CNTTYPE5  |EPWM Counter Behavior Type
+     * |        |          |00 = Up counter type (supports in capture mode).
+     * |        |          |01 = Down count type (supports in capture mode).
+     * |        |          |10 = Up-down counter type.
+     * |        |          |11 = Reserved.
+     * |[16]    |CNTMODE0  |EPWM Counter Mode
+     * |        |          |0 = Auto-reload mode.
+     * |        |          |1 = One-shot mode.
+     * |[17]    |CNTMODE1  |EPWM Counter Mode
+     * |        |          |0 = Auto-reload mode.
+     * |        |          |1 = One-shot mode.
+     * |[18]    |CNTMODE2  |EPWM Counter Mode
+     * |        |          |0 = Auto-reload mode.
+     * |        |          |1 = One-shot mode.
+     * |[19]    |CNTMODE3  |EPWM Counter Mode
+     * |        |          |0 = Auto-reload mode.
+     * |        |          |1 = One-shot mode.
+     * |[20]    |CNTMODE4  |EPWM Counter Mode
+     * |        |          |0 = Auto-reload mode.
+     * |        |          |1 = One-shot mode.
+     * |[21]    |CNTMODE5  |EPWM Counter Mode
+     * |        |          |0 = Auto-reload mode.
+     * |        |          |1 = One-shot mode.
+     * |[24]    |OUTMODE0  |EPWM Output Mode
+     * |        |          |Each bit n controls the output mode of corresponding EPWM channel n.
+     * |        |          |0 = EPWM independent mode.
+     * |        |          |1 = EPWM complementary mode.
+     * |        |          |Note: When operating in group function, these bits must all set to the same mode.
+     * |[25]    |OUTMODE2  |EPWM Output Mode
+     * |        |          |Each bit n controls the output mode of corresponding EPWM channel n.
+     * |        |          |0 = EPWM independent mode.
+     * |        |          |1 = EPWM complementary mode.
+     * |        |          |Note: When operating in group function, these bits must all set to the same mode.
+     * |[26]    |OUTMODE4  |EPWM Output Mode
+     * |        |          |Each bit n controls the output mode of corresponding EPWM channel n.
+     * |        |          |0 = EPWM independent mode.
+     * |        |          |1 = EPWM complementary mode.
+     * |        |          |Note: When operating in group function, these bits must all set to the same mode.
+     * @var EPWM_T::SYNC
+     * Offset: 0x08  EPWM Synchronization Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PHSEN0    |SYNC Phase Enable Bits
+     * |        |          |0 = EPWM counter disable to load PHS value.
+     * |        |          |1 = EPWM counter enable to load PHS value.
+     * |[1]     |PHSEN2    |SYNC Phase Enable Bits
+     * |        |          |0 = EPWM counter disable to load PHS value.
+     * |        |          |1 = EPWM counter enable to load PHS value.
+     * |[2]     |PHSEN4    |SYNC Phase Enable Bits
+     * |        |          |0 = EPWM counter disable to load PHS value.
+     * |        |          |1 = EPWM counter enable to load PHS value.
+     * |[9:8]   |SINSRC0   |EPWM0_SYNC_IN Source Selection
+     * |        |          |00 = Synchronize source from SYNC_IN or SWSYNC.
+     * |        |          |01 = Counter equal to 0.
+     * |        |          |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5.
+     * |        |          |11 = SYNC_OUT will not be generated.
+     * |[11:10] |SINSRC2   |EPWM0_SYNC_IN Source Selection
+     * |        |          |00 = Synchronize source from SYNC_IN or SWSYNC.
+     * |        |          |01 = Counter equal to 0.
+     * |        |          |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5.
+     * |        |          |11 = SYNC_OUT will not be generated.
+     * |[13:12] |SINSRC4   |EPWM0_SYNC_IN Source Selection
+     * |        |          |00 = Synchronize source from SYNC_IN or SWSYNC.
+     * |        |          |01 = Counter equal to 0.
+     * |        |          |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5.
+     * |        |          |11 = SYNC_OUT will not be generated.
+     * |[16]    |SNFLTEN   |EPWM0_SYNC_IN Noise Filter Enable Bits
+     * |        |          |0 = Noise filter of input pin EPWM0_SYNC_IN is Disabled.
+     * |        |          |1 = Noise filter of input pin EPWM0_SYNC_IN is Enabled.
+     * |[19:17] |SFLTCSEL  |SYNC Edge Detector Filter Clock Selection
+     * |        |          |000 = Filter clock = HCLK.
+     * |        |          |001 = Filter clock = HCLK/2.
+     * |        |          |010 = Filter clock = HCLK/4.
+     * |        |          |011 = Filter clock = HCLK/8.
+     * |        |          |100 = Filter clock = HCLK/16.
+     * |        |          |101 = Filter clock = HCLK/32.
+     * |        |          |110 = Filter clock = HCLK/64.
+     * |        |          |111 = Filter clock = HCLK/128.
+     * |[22:20] |SFLTCNT   |SYNC Edge Detector Filter Count
+     * |        |          |The register bits control the counter number of edge detector.
+     * |[23]    |SINPINV   |SYNC Input Pin Inverse
+     * |        |          |0 = The state of pin EPWM0_SYNC_IN is passed to the negative edge detector.
+     * |        |          |1 = The inverse state of pin EPWM0_SYNC_IN is passed to the negative edge detector.
+     * |[24]    |PHSDIR0   |EPWM Phase Direction Control
+     * |        |          |0 = Control EPWM counter count decrement after synchronizing.
+     * |        |          |1 = Control EPWM counter count increment after synchronizing.
+     * |[25]    |PHSDIR2   |EPWM Phase Direction Control
+     * |        |          |0 = Control EPWM counter count decrement after synchronizing.
+     * |        |          |1 = Control EPWM counter count increment after synchronizing.
+     * |[26]    |PHSDIR4   |EPWM Phase Direction Control
+     * |        |          |0 = Control EPWM counter count decrement after synchronizing.
+     * |        |          |1 = Control EPWM counter count increment after synchronizing.
+     * @var EPWM_T::SWSYNC
+     * Offset: 0x0C  EPWM Software Control Synchronization Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SWSYNC0   |Software SYNC Function
+     * |        |          |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
+     * |[1]     |SWSYNC2   |Software SYNC Function
+     * |        |          |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
+     * |[2]     |SWSYNC4   |Software SYNC Function
+     * |        |          |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
+     * @var EPWM_T::CLKSRC
+     * Offset: 0x10  EPWM Clock Source Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |ECLKSRC0  |EPWM_CH01 External Clock Source Select
+     * |        |          |000 = EPWMx_CLK, x denotes 0 or 1.
+     * |        |          |001 = TIMER0 overflow.
+     * |        |          |010 = TIMER1 overflow.
+     * |        |          |011 = TIMER2 overflow.
+     * |        |          |100 = TIMER3 overflow.
+     * |        |          |Others = Reserved.
+     * |[10:8]  |ECLKSRC2  |EPWM_CH23 External Clock Source Select
+     * |        |          |000 = EPWMx_CLK, x denotes 0 or 1.
+     * |        |          |001 = TIMER0 overflow.
+     * |        |          |010 = TIMER1 overflow.
+     * |        |          |011 = TIMER2 overflow.
+     * |        |          |100 = TIMER3 overflow.
+     * |        |          |Others = Reserved.
+     * |[18:16] |ECLKSRC4  |EPWM_CH45 External Clock Source Select
+     * |        |          |000 = EPWMx_CLK, x denotes 0 or 1.
+     * |        |          |001 = TIMER0 overflow.
+     * |        |          |010 = TIMER1 overflow.
+     * |        |          |011 = TIMER2 overflow.
+     * |        |          |100 = TIMER3 overflow.
+     * |        |          |Others = Reserved.
+     * @var EPWM_T::CLKPSC[3]
+     * Offset: 0x14  EPWM Clock Prescale Register 0/1, 2/3, 4/5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[11:0]  |CLKPSC    |EPWM Counter Clock Prescale
+     * |        |          |The clock of EPWM counter is decided by clock prescaler
+     * |        |          |Each EPWM pair share one EPWM counter clock prescaler
+     * |        |          |The clock of EPWM counter is divided by (CLKPSC+ 1)
+     * @var EPWM_T::CNTEN
+     * Offset: 0x20  EPWM Counter Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CNTEN0    |EPWM Counter Enable Bits
+     * |        |          |0 = EPWM Counter and clock prescaler Stop Running.
+     * |        |          |1 = EPWM Counter and clock prescaler Start Running.
+     * |[1]     |CNTEN1    |EPWM Counter Enable Bits
+     * |        |          |0 = EPWM Counter and clock prescaler Stop Running.
+     * |        |          |1 = EPWM Counter and clock prescaler Start Running.
+     * |[2]     |CNTEN2    |EPWM Counter Enable Bits
+     * |        |          |0 = EPWM Counter and clock prescaler Stop Running.
+     * |        |          |1 = EPWM Counter and clock prescaler Start Running.
+     * |[3]     |CNTEN3    |EPWM Counter Enable Bits
+     * |        |          |0 = EPWM Counter and clock prescaler Stop Running.
+     * |        |          |1 = EPWM Counter and clock prescaler Start Running.
+     * |[4]     |CNTEN4    |EPWM Counter Enable Bits
+     * |        |          |0 = EPWM Counter and clock prescaler Stop Running.
+     * |        |          |1 = EPWM Counter and clock prescaler Start Running.
+     * |[5]     |CNTEN5    |EPWM Counter Enable Bits
+     * |        |          |0 = EPWM Counter and clock prescaler Stop Running.
+     * |        |          |1 = EPWM Counter and clock prescaler Start Running.
+     * @var EPWM_T::CNTCLR
+     * Offset: 0x24  EPWM Clear Counter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CNTCLR0   |Clear EPWM Counter Control Bit
+     * |        |          |It is automatically cleared by hardware.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear 16-bit EPWM counter to 0000H.
+     * |[1]     |CNTCLR1   |Clear EPWM Counter Control Bit
+     * |        |          |It is automatically cleared by hardware.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear 16-bit EPWM counter to 0000H.
+     * |[2]     |CNTCLR2   |Clear EPWM Counter Control Bit
+     * |        |          |It is automatically cleared by hardware.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear 16-bit EPWM counter to 0000H.
+     * |[3]     |CNTCLR3   |Clear EPWM Counter Control Bit
+     * |        |          |It is automatically cleared by hardware.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear 16-bit EPWM counter to 0000H.
+     * |[4]     |CNTCLR4   |Clear EPWM Counter Control Bit
+     * |        |          |It is automatically cleared by hardware.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear 16-bit EPWM counter to 0000H.
+     * |[5]     |CNTCLR5   |Clear EPWM Counter Control Bit
+     * |        |          |It is automatically cleared by hardware.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear 16-bit EPWM counter to 0000H.
+     * @var EPWM_T::LOAD
+     * Offset: 0x28  EPWM Load Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |LOAD0     |Re-load EPWM Comparator Register (CMPDAT) Control Bit
+     * |        |          |This bit is software write, hardware clear when current EPWM period end.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Set load window of window loading mode.
+     * |        |          |Read Operation:
+     * |        |          |0 = No load window is set.
+     * |        |          |1 = Load window is set.
+     * |        |          |Note: This bit only use in window loading mode, WINLDEN0(EPWM_CTL0[13:8]) = 1.
+     * |[1]     |LOAD1     |Re-load EPWM Comparator Register (CMPDAT) Control Bit
+     * |        |          |This bit is software write, hardware clear when current EPWM period end.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Set load window of window loading mode.
+     * |        |          |Read Operation:
+     * |        |          |0 = No load window is set.
+     * |        |          |1 = Load window is set.
+     * |        |          |Note: This bit only use in window loading mode, WINLDEN1(EPWM_CTL0[13:8]) = 1.
+     * |[2]     |LOAD2     |Re-load EPWM Comparator Register (CMPDAT) Control Bit
+     * |        |          |This bit is software write, hardware clear when current EPWM period end.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Set load window of window loading mode.
+     * |        |          |Read Operation:
+     * |        |          |0 = No load window is set.
+     * |        |          |1 = Load window is set.
+     * |        |          |Note: This bit only use in window loading mode, WINLDEN2(EPWM_CTL0[13:8]) = 1.
+     * |[3]     |LOAD3     |Re-load EPWM Comparator Register (CMPDAT) Control Bit
+     * |        |          |This bit is software write, hardware clear when current EPWM period end.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Set load window of window loading mode.
+     * |        |          |Read Operation:
+     * |        |          |0 = No load window is set.
+     * |        |          |1 = Load window is set.
+     * |        |          |Note: This bit only use in window loading mode, WINLDEN3(EPWM_CTL0[13:8]) = 1.
+     * |[4]     |LOAD4     |Re-load EPWM Comparator Register (CMPDAT) Control Bit
+     * |        |          |This bit is software write, hardware clear when current EPWM period end.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Set load window of window loading mode.
+     * |        |          |Read Operation:
+     * |        |          |0 = No load window is set.
+     * |        |          |1 = Load window is set.
+     * |        |          |Note: This bit only use in window loading mode, WINLDEN4(EPWM_CTL0[13:8]) = 1.
+     * |[5]     |LOAD5     |Re-load EPWM Comparator Register (CMPDAT) Control Bit
+     * |        |          |This bit is software write, hardware clear when current EPWM period end.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Set load window of window loading mode.
+     * |        |          |Read Operation:
+     * |        |          |0 = No load window is set.
+     * |        |          |1 = Load window is set.
+     * |        |          |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1.
+     * @var EPWM_T::PERIOD[6]
+     * Offset: 0x30  EPWM Period Register 0~5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |PERIOD    |EPWM Period Register
+     * |        |          |Up-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, and restarts from 0.
+     * |        |          |Down-Count mode: In this mode, EPWM counter counts from PERIOD to 0, and restarts from PERIOD.
+     * |        |          |EPWM period time = (PERIOD+1) * EPWM_CLK period.
+     * |        |          |Up-Down-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.
+     * |        |          |EPWM period time = 2 * PERIOD * EPWM_CLK period.
+     * @var EPWM_T::CMPDAT[6]
+     * Offset: 0x50  EPWM Comparator Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |CMP       |EPWM Comparator Register
+     * |        |          |CMP use to compare with CNTR to generate EPWM waveform, interrupt and trigger EADC/DAC.
+     * |        |          |In independent mode, CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.
+     * |        |          |In complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5.
+     * @var EPWM_T::DTCTL[3]
+     * Offset: 0x70  EPWM Dead-Time Control Register 0/1,2/3,4/5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[11:0]  |DTCNT     |Dead-time Counter (Write Protect)
+     * |        |          |The dead-time can be calculated from the following formula:
+     * |        |          |Dead-time = (DTCNT[11:0]+1) * EPWM_CLK period.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[16]    |DTEN      |Enable Dead-time Insertion for EPWM Pair (EPWM_CH0, EPWM_CH1) (EPWM_CH2, EPWM_CH3) (EPWM_CH4, EPWM_CH5) (Write Protect)
+     * |        |          |Dead-time insertion is only active when this pair of complementary EPWM is enabled
+     * |        |          |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.
+     * |        |          |0 = Dead-time insertion Disabled on the pin pair.
+     * |        |          |1 = Dead-time insertion Enabled on the pin pair.
+     * |        |          |Note: This register is write protected. Refer toSYS_REGLCTL register.
+     * |[24]    |DTCKSEL   |Dead-time Clock Select (Write Protect)
+     * |        |          |0 = Dead-time clock source from EPWM_CLK.
+     * |        |          |1 = Dead-time clock source from prescaler output.
+     * |        |          |Note: This register is write protected. Refer toREGWRPROT register.
+     * @var EPWM_T::PHS[3]
+     * Offset: 0x80  EPWM Counter Phase Register 0/1,2/3,4/5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |PHS       |EPWM Synchronous Start Phase Bits
+     * |        |          |PHS determines the EPWM synchronous start phase value. These bits only use in synchronous function.
+     * @var EPWM_T::CNT[6]
+     * Offset: 0x90  EPWM Counter Register 0~5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |CNT       |EPWM Data Register (Read Only)
+     * |        |          |User can monitor CNTR to know the current value in 16-bit period counter.
+     * |[16]    |DIRF      |EPWM Direction Indicator Flag (Read Only)
+     * |        |          |0 = Counter is Down count.
+     * |        |          |1 = Counter is UP count.
+     * @var EPWM_T::WGCTL0
+     * Offset: 0xB0  EPWM Generation Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |ZPCTL0    |EPWM Zero Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM zero point output Low.
+     * |        |          |10 = EPWM zero point output High.
+     * |        |          |11 = EPWM zero point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter count to zero.
+     * |[3:2]   |ZPCTL1    |EPWM Zero Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM zero point output Low.
+     * |        |          |10 = EPWM zero point output High.
+     * |        |          |11 = EPWM zero point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter count to zero.
+     * |[5:4]   |ZPCTL2    |EPWM Zero Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM zero point output Low.
+     * |        |          |10 = EPWM zero point output High.
+     * |        |          |11 = EPWM zero point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter count to zero.
+     * |[7:6]   |ZPCTL3    |EPWM Zero Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM zero point output Low.
+     * |        |          |10 = EPWM zero point output High.
+     * |        |          |11 = EPWM zero point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter count to zero.
+     * |[9:8]   |ZPCTL4    |EPWM Zero Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM zero point output Low.
+     * |        |          |10 = EPWM zero point output High.
+     * |        |          |11 = EPWM zero point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter count to zero.
+     * |[11:10] |ZPCTL5    |EPWM Zero Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM zero point output Low.
+     * |        |          |10 = EPWM zero point output High.
+     * |        |          |11 = EPWM zero point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter count to zero.
+     * |[17:16] |PRDPCTL0  |EPWM Period (Center) Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM period (center) point output Low.
+     * |        |          |10 = EPWM period (center) point output High.
+     * |        |          |11 = EPWM period (center) point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter count to (PERIOD0+1).
+     * |        |          |Note: This bit is center point control when EPWM counter operating in up-down counter type.
+     * |[19:18] |PRDPCTL1  |EPWM Period (Center) Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM period (center) point output Low.
+     * |        |          |10 = EPWM period (center) point output High.
+     * |        |          |11 = EPWM period (center) point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter count to (PERIOD1+1).
+     * |        |          |Note: This bit is center point control when EPWM counter operating in up-down counter type.
+     * |[21:20] |PRDPCTL2  |EPWM Period (Center) Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM period (center) point output Low.
+     * |        |          |10 = EPWM period (center) point output High.
+     * |        |          |11 = EPWM period (center) point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter count to (PERIOD2+1).
+     * |        |          |Note: This bit is center point control when EPWM counter operating in up-down counter type.
+     * |[23:22] |PRDPCTL3  |EPWM Period (Center) Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM period (center) point output Low.
+     * |        |          |10 = EPWM period (center) point output High.
+     * |        |          |11 = EPWM period (center) point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter count to (PERIOD3+1).
+     * |        |          |Note: This bit is center point control when EPWM counter operating in up-down counter type.
+     * |[25:24] |PRDPCTL4  |EPWM Period (Center) Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM period (center) point output Low.
+     * |        |          |10 = EPWM period (center) point output High.
+     * |        |          |11 = EPWM period (center) point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter count to (PERIOD4+1).
+     * |        |          |Note: This bit is center point control when EPWM counter operating in up-down counter type.
+     * |[27:26] |PRDPCTL5  |EPWM Period (Center) Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM period (center) point output Low.
+     * |        |          |10 = EPWM period (center) point output High.
+     * |        |          |11 = EPWM period (center) point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter count to (PERIOD5+1).
+     * |        |          |Note: This bit is center point control when EPWM counter operating in up-down counter type.
+     * @var EPWM_T::WGCTL1
+     * Offset: 0xB4  EPWM Generation Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |CMPUCTL0  |EPWM Compare Up Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM compare up point output Low.
+     * |        |          |10 = EPWM compare up point output High.
+     * |        |          |11 = EPWM compare up point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter up count to CMPDAT.
+     * |        |          |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
+     * |[3:2]   |CMPUCTL1  |EPWM Compare Up Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM compare up point output Low.
+     * |        |          |10 = EPWM compare up point output High.
+     * |        |          |11 = EPWM compare up point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter up count to CMPDAT.
+     * |        |          |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
+     * |[5:4]   |CMPUCTL2  |EPWM Compare Up Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM compare up point output Low.
+     * |        |          |10 = EPWM compare up point output High.
+     * |        |          |11 = EPWM compare up point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter up count to CMPDAT.
+     * |        |          |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
+     * |[7:6]   |CMPUCTL3  |EPWM Compare Up Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM compare up point output Low.
+     * |        |          |10 = EPWM compare up point output High.
+     * |        |          |11 = EPWM compare up point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter up count to CMPDAT.
+     * |        |          |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
+     * |[9:8]   |CMPUCTL4  |EPWM Compare Up Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM compare up point output Low.
+     * |        |          |10 = EPWM compare up point output High.
+     * |        |          |11 = EPWM compare up point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter up count to CMPDAT.
+     * |        |          |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
+     * |[11:10] |CMPUCTL5  |EPWM Compare Up Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM compare up point output Low.
+     * |        |          |10 = EPWM compare up point output High.
+     * |        |          |11 = EPWM compare up point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter up count to CMPDAT.
+     * |        |          |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
+     * |[17:16] |CMPDCTL0  |EPWM Compare Down Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM compare down point output Low.
+     * |        |          |10 = EPWM compare down point output High.
+     * |        |          |11 = EPWM compare down point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter down count to CMPDAT.
+     * |        |          |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
+     * |[19:18] |CMPDCTL1  |EPWM Compare Down Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM compare down point output Low.
+     * |        |          |10 = EPWM compare down point output High.
+     * |        |          |11 = EPWM compare down point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter down count to CMPDAT.
+     * |        |          |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
+     * |[21:20] |CMPDCTL2  |EPWM Compare Down Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM compare down point output Low.
+     * |        |          |10 = EPWM compare down point output High.
+     * |        |          |11 = EPWM compare down point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter down count to CMPDAT.
+     * |        |          |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
+     * |[23:22] |CMPDCTL3  |EPWM Compare Down Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM compare down point output Low.
+     * |        |          |10 = EPWM compare down point output High.
+     * |        |          |11 = EPWM compare down point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter down count to CMPDAT.
+     * |        |          |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
+     * |[25:24] |CMPDCTL4  |EPWM Compare Down Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM compare down point output Low.
+     * |        |          |10 = EPWM compare down point output High.
+     * |        |          |11 = EPWM compare down point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter down count to CMPDAT.
+     * |        |          |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
+     * |[27:26] |CMPDCTL5  |EPWM Compare Down Point Control
+     * |        |          |00 = Do nothing.
+     * |        |          |01 = EPWM compare down point output Low.
+     * |        |          |10 = EPWM compare down point output High.
+     * |        |          |11 = EPWM compare down point output Toggle.
+     * |        |          |EPWM can control output level when EPWM counter down count to CMPDAT.
+     * |        |          |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
+     * @var EPWM_T::MSKEN
+     * Offset: 0xB8  EPWM Mask Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |MSKEN0    |EPWM Mask Enable Bits
+     * |        |          |The EPWM output signal will be masked when this bit is enabled.
+     * |        |          |The corresponding EPWM channel 0 will output MSKDAT0 (EPWM_MSK[5:0]) data.
+     * |        |          |0 = EPWM output signal is non-masked.
+     * |        |          |1 = EPWM output signal is masked and output MSKDAT0 data.
+     * |[1]     |MSKEN1    |EPWM Mask Enable Bits
+     * |        |          |The EPWM output signal will be masked when this bit is enabled.
+     * |        |          |The corresponding EPWM channel 1 will output MSKDAT1 (EPWM_MSK[5:0]) data.
+     * |        |          |0 = EPWM output signal is non-masked.
+     * |        |          |1 = EPWM output signal is masked and output MSKDAT1 data.
+     * |[2]     |MSKEN2    |EPWM Mask Enable Bits
+     * |        |          |The EPWM output signal will be masked when this bit is enabled.
+     * |        |          |The corresponding EPWM channel 2 will output MSKDAT2 (EPWM_MSK[5:0]) data.
+     * |        |          |0 = EPWM output signal is non-masked.
+     * |        |          |1 = EPWM output signal is masked and output MSKDAT2 data.
+     * |[3]     |MSKEN3    |EPWM Mask Enable Bits
+     * |        |          |The EPWM output signal will be masked when this bit is enabled.
+     * |        |          |The corresponding EPWM channel 3 will output MSKDAT3 (EPWM_MSK[5:0]) data.
+     * |        |          |0 = EPWM output signal is non-masked.
+     * |        |          |1 = EPWM output signal is masked and output MSKDAT3 data.
+     * |[4]     |MSKEN4    |EPWM Mask Enable Bits
+     * |        |          |The EPWM output signal will be masked when this bit is enabled.
+     * |        |          |The corresponding EPWM channel 4 will output MSKDAT4 (EPWM_MSK[5:0]) data.
+     * |        |          |0 = EPWM output signal is non-masked.
+     * |        |          |1 = EPWM output signal is masked and output MSKDAT4 data.
+     * |[5]     |MSKEN5    |EPWM Mask Enable Bits
+     * |        |          |The EPWM output signal will be masked when this bit is enabled.
+     * |        |          |The corresponding EPWM channel 5 will output MSKDAT5 (EPWM_MSK[5:0]) data.
+     * |        |          |0 = EPWM output signal is non-masked.
+     * |        |          |1 = EPWM output signal is masked and output MSKDAT5 data.
+     * @var EPWM_T::MSK
+     * Offset: 0xBC  EPWM Mask Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |MSKDAT0   |EPWM Mask Data Bit
+     * |        |          |This data bit control the state of EPWM_CH0 output pin, if corresponding mask function is enabled.
+     * |        |          |0 = Output logic low to EPWM_CH0.
+     * |        |          |1 = Output logic high to EPWM_CH0.
+     * |[1]     |MSKDAT1   |EPWM Mask Data Bit
+     * |        |          |This data bit control the state of EPWM_CH1 output pin, if corresponding mask function is enabled.
+     * |        |          |0 = Output logic low to EPWM_CH1.
+     * |        |          |1 = Output logic high to EPWM_CH1.
+     * |[2]     |MSKDAT2   |EPWM Mask Data Bit
+     * |        |          |This data bit control the state of EPWM_CH2 output pin, if corresponding mask function is enabled.
+     * |        |          |0 = Output logic low to EPWM_CH2.
+     * |        |          |1 = Output logic high to EPWM_CH2.
+     * |[3]     |MSKDAT3   |EPWM Mask Data Bit
+     * |        |          |This data bit control the state of EPWM_CH3 output pin, if corresponding mask function is enabled.
+     * |        |          |0 = Output logic low to EPWM_CH3.
+     * |        |          |1 = Output logic high to EPWM_CH3.
+     * |[4]     |MSKDAT4   |EPWM Mask Data Bit
+     * |        |          |This data bit control the state of EPWM_CH4 output pin, if corresponding mask function is enabled.
+     * |        |          |0 = Output logic low to EPWM_CH4.
+     * |        |          |1 = Output logic high to EPWM_CH4.
+     * |[5]     |MSKDAT5   |EPWM Mask Data Bit
+     * |        |          |This data bit control the state of EPWM_CH5 output pin, if corresponding mask function is enabled.
+     * |        |          |0 = Output logic low to EPWM_CH5.
+     * |        |          |1 = Output logic high to EPWM_CH5.
+     * @var EPWM_T::BNF
+     * Offset: 0xC0  EPWM Brake Noise Filter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BRK0NFEN  |EPWM Brake 0 Noise Filter Enable Bit
+     * |        |          |0 = Noise filter of EPWM Brake 0 Disabled.
+     * |        |          |1 = Noise filter of EPWM Brake 0 Enabled.
+     * |[3:1]   |BRK0NFSEL |Brake 0 Edge Detector Filter Clock Selection
+     * |        |          |000 = Filter clock = HCLK.
+     * |        |          |001 = Filter clock = HCLK/2.
+     * |        |          |010 = Filter clock = HCLK/4.
+     * |        |          |011 = Filter clock = HCLK/8.
+     * |        |          |100 = Filter clock = HCLK/16.
+     * |        |          |101 = Filter clock = HCLK/32.
+     * |        |          |110 = Filter clock = HCLK/64.
+     * |        |          |111 = Filter clock = HCLK/128.
+     * |[6:4]   |BRK0FCNT  |Brake 0 Edge Detector Filter Count
+     * |        |          |The register bits control the Brake0 filter counter to count from 0 to BRK0FCNT.
+     * |[7]     |BRK0PINV  |Brake 0 Pin Inverse
+     * |        |          |0 = The state of pin EPWMx_BRAKE0 is passed to the negative edge detector.
+     * |        |          |1 = The inversed state of pin EPWMx_BRAKE0 is passed to the negative edge detector.
+     * |[8]     |BRK1NFEN  |EPWM Brake 1 Noise Filter Enable Bit
+     * |        |          |0 = Noise filter of EPWM Brake 1 Disabled.
+     * |        |          |1 = Noise filter of EPWM Brake 1 Enabled.
+     * |[11:9]  |BRK1NFSEL |Brake 1 Edge Detector Filter Clock Selection
+     * |        |          |000 = Filter clock = HCLK.
+     * |        |          |001 = Filter clock = HCLK/2.
+     * |        |          |010 = Filter clock = HCLK/4.
+     * |        |          |011 = Filter clock = HCLK/8.
+     * |        |          |100 = Filter clock = HCLK/16.
+     * |        |          |101 = Filter clock = HCLK/32.
+     * |        |          |110 = Filter clock = HCLK/64.
+     * |        |          |111 = Filter clock = HCLK/128.
+     * |[14:12] |BRK1FCNT  |Brake 1 Edge Detector Filter Count
+     * |        |          |The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT.
+     * |[15]    |BRK1PINV  |Brake 1 Pin Inverse
+     * |        |          |0 = The state of pin EPWMx_BRAKE1 is passed to the negative edge detector.
+     * |        |          |1 = The inversed state of pin EPWMx_BRAKE1 is passed to the negative edge detector.
+     * |[16]    |BK0SRC    |Brake 0 Pin Source Select
+     * |        |          |For EPWM0 setting:
+     * |        |          |0 = Brake 0 pin source come from EPWM0_BRAKE0.
+     * |        |          |1 = Brake 0 pin source come from EPWM1_BRAKE0.
+     * |        |          |For EPWM1 setting:
+     * |        |          |0 = Brake 0 pin source come from EPWM1_BRAKE0.
+     * |        |          |1 = Brake 0 pin source come from EPWM0_BRAKE0.
+     * |[24]    |BK1SRC    |Brake 1 Pin Source Select
+     * |        |          |For EPWM0 setting:
+     * |        |          |0 = Brake 1 pin source come from EPWM0_BRAKE1.
+     * |        |          |1 = Brake 1 pin source come from EPWM1_BRAKE1.
+     * |        |          |For EPWM1 setting:
+     * |        |          |0 = Brake 1 pin source come from EPWM1_BRAKE1.
+     * |        |          |1 = Brake 1 pin source come from EPWM0_BRAKE1.
+     * @var EPWM_T::FAILBRK
+     * Offset: 0xC4  EPWM System Fail Brake Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CSSBRKEN  |Clock Security System Detection Trigger EPWM Brake Function 0 Enable Bit
+     * |        |          |0 = Brake Function triggered by CSS detection Disabled.
+     * |        |          |1 = Brake Function triggered by CSS detection Enabled.
+     * |[1]     |BODBRKEN  |Brown-out Detection Trigger EPWM Brake Function 0 Enable Bit
+     * |        |          |0 = Brake Function triggered by BOD Disabled.
+     * |        |          |1 = Brake Function triggered by BOD Enabled.
+     * |[2]     |RAMBRKEN  |SRAM Parity Error Detection Trigger EPWM Brake Function 0 Enable Bit
+     * |        |          |0 = Brake Function triggered by SRAM parity error detection Disabled.
+     * |        |          |1 = Brake Function triggered by SRAM parity error detection Enabled.
+     * |[3]     |CORBRKEN  |Core Lockup Detection Trigger EPWM Brake Function 0 Enable Bit
+     * |        |          |0 = Brake Function triggered by Core lockup detection Disabled.
+     * |        |          |1 = Brake Function triggered by Core lockup detection Enabled.
+     * @var EPWM_T::BRKCTL[3]
+     * Offset: 0xC8  EPWM Brake Edge Detect Control Register 0/1,2/3,4/5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CPO0EBEN  |Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)
+     * |        |          |0 = ACMP0_O as edge-detect brake source Disabled.
+     * |        |          |1 = ACMP0_O as edge-detect brake source Enabled.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[1]     |CPO1EBEN  |Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)
+     * |        |          |0 = ACMP1_O as edge-detect brake source Disabled.
+     * |        |          |1 = ACMP1_O as edge-detect brake source Enabled.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[4]     |BRKP0EEN  |Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)
+     * |        |          |0 = EPWMx_BRAKE0 pin as edge-detect brake source Disabled.
+     * |        |          |1 = EPWMx_BRAKE0 pin as edge-detect brake source Enabled.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[5]     |BRKP1EEN  |Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)
+     * |        |          |0 = EPWMx_BRAKE1 pin as edge-detect brake source Disabled.
+     * |        |          |1 = EPWMx_BRAKE1 pin as edge-detect brake source Enabled.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[7]     |SYSEBEN   |Enable System Fail As Edge-detect Brake Source (Write Protect)
+     * |        |          |0 = System Fail condition as edge-detect brake source Disabled.
+     * |        |          |1 = System Fail condition as edge-detect brake source Enabled.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[8]     |CPO0LBEN  |Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)
+     * |        |          |0 = ACMP0_O as level-detect brake source Disabled.
+     * |        |          |1 = ACMP0_O as level-detect brake source Enabled.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[9]     |CPO1LBEN  |Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)
+     * |        |          |0 = ACMP1_O as level-detect brake source Disabled.
+     * |        |          |1 = ACMP1_O as level-detect brake source Enabled.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[12]    |BRKP0LEN  |Enable BKP0 Pin As Level-detect Brake Source (Write Protect)
+     * |        |          |0 = EPWMx_BRAKE0 pin as level-detect brake source Disabled.
+     * |        |          |1 = EPWMx_BRAKE0 pin as level-detect brake source Enabled.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[13]    |BRKP1LEN  |Enable BKP1 Pin As Level-detect Brake Source (Write Protect)
+     * |        |          |0 = EPWMx_BRAKE1 pin as level-detect brake source Disabled.
+     * |        |          |1 = EPWMx_BRAKE1 pin as level-detect brake source Enabled.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[15]    |SYSLBEN   |Enable System Fail As Level-detect Brake Source (Write Protect)
+     * |        |          |0 = System Fail condition as level-detect brake source Disabled.
+     * |        |          |1 = System Fail condition as level-detect brake source Enabled.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[17:16] |BRKAEVEN  |EPWM Brake Action Select for Even Channel (Write Protect)
+     * |        |          |00 = EPWMx brake event will not affect even channels output.
+     * |        |          |01 = EPWM even channel output tri-state when EPWMx brake event happened.
+     * |        |          |10 = EPWM even channel output low level when EPWMx brake event happened.
+     * |        |          |11 = EPWM even channel output high level when EPWMx brake event happened.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[19:18] |BRKAODD   |EPWM Brake Action Select for Odd Channel (Write Protect)
+     * |        |          |00 = EPWMx brake event will not affect odd channels output.
+     * |        |          |01 = EPWM odd channel output tri-state when EPWMx brake event happened.
+     * |        |          |10 = EPWM odd channel output low level when EPWMx brake event happened.
+     * |        |          |11 = EPWM odd channel output high level when EPWMx brake event happened.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[20]    |EADCEBEN  |Enable EADC Result Monitor (EADCRM) As Edge-detect Brake Source (Write Protect)
+     * |        |          |0 = EADCRM as edge-detect brake source Disabled.
+     * |        |          |1 = EADCRM as edge-detect brake source Enabled.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[28]    |EADCLBEN  |Enable EADC Result Monitor (EADCRM) As Level-detect Brake Source (Write Protect)
+     * |        |          |0 = EADCRM as level-detect brake source Disabled.
+     * |        |          |1 = EADCRM as level-detect brake source Enabled.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * @var EPWM_T::POLCTL
+     * Offset: 0xD4  EPWM Pin Polar Inverse Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PINV0     |EPWM_CH0 PIN Polar Inverse Control
+     * |        |          |The register controls polarity state of EPWM_CH0 output.
+     * |        |          |0 = EPWM_CH0 output polar inverse Disabled.
+     * |        |          |1 = EPWM_CH0 output polar inverse Enabled.
+     * |[1]     |PINV1     |EPWM_CH1 PIN Polar Inverse Control
+     * |        |          |The register controls polarity state of EPWM_CH1 output.
+     * |        |          |0 = EPWM_CH1 output polar inverse Disabled.
+     * |        |          |1 = EPWM_CH1 output polar inverse Enabled.
+     * |[2]     |PINV2     |EPWM_CH2 PIN Polar Inverse Control
+     * |        |          |The register controls polarity state of EPWM_CH2 output.
+     * |        |          |0 = EPWM_CH2 output polar inverse Disabled.
+     * |        |          |1 = EPWM_CH2 output polar inverse Enabled.
+     * |[3]     |PINV3     |EPWM_CH3 PIN Polar Inverse Control
+     * |        |          |The register controls polarity state of EPWM_CH3 output.
+     * |        |          |0 = EPWM_CH3 output polar inverse Disabled.
+     * |        |          |1 = EPWM_CH3 output polar inverse Enabled.
+     * |[4]     |PINV4     |EPWM_CH4 PIN Polar Inverse Control
+     * |        |          |The register controls polarity state of EPWM_CH4 output.
+     * |        |          |0 = EPWM_CH4 output polar inverse Disabled.
+     * |        |          |1 = EPWM_CH4 output polar inverse Enabled.
+     * |[5]     |PINV5     |EPWM_CH5 PIN Polar Inverse Control
+     * |        |          |The register controls polarity state of EPWM_CH5 output.
+     * |        |          |0 = EPWM_CH5 output polar inverse Disabled.
+     * |        |          |1 = EPWM_CH5 output polar inverse Enabled.
+     * @var EPWM_T::POEN
+     * Offset: 0xD8  EPWM Output Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |POEN0     |EPWM_CH0 Pin Output Enable Bits
+     * |        |          |0 = EPWM_CH0 pin at tri-state.
+     * |        |          |1 = EPWM_CH0 pin in output mode.
+     * |[1]     |POEN1     |EPWM_CH1 Pin Output Enable Bits
+     * |        |          |0 = EPWM_CH1 pin at tri-state.
+     * |        |          |1 = EPWM_CH1 pin in output mode.
+     * |[2]     |POEN2     |EPWM_CH2 Pin Output Enable Bits
+     * |        |          |0 = EPWM_CH2 pin at tri-state.
+     * |        |          |1 = EPWM_CH2 pin in output mode.
+     * |[3]     |POEN3     |EPWM_CH3 Pin Output Enable Bits
+     * |        |          |0 = EPWM_CH3 pin at tri-state.
+     * |        |          |1 = EPWM_CH3 pin in output mode.
+     * |[4]     |POEN4     |EPWM_CH4 Pin Output Enable Bits
+     * |        |          |0 = EPWM_CH4 pin at tri-state.
+     * |        |          |1 = EPWM_CH4 pin in output mode.
+     * |[5]     |POEN5     |EPWM_CH5 Pin Output Enable Bits
+     * |        |          |0 = EPWM_CH5 pin at tri-state.
+     * |        |          |1 = EPWM_CH5 pin in output mode.
+     * @var EPWM_T::SWBRK
+     * Offset: 0xDC  EPWM Software Brake Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BRKETRG0  |EPWM Edge Brake Software Trigger (Write Only) (Write Protect)
+     * |        |          |Write 1 to this bit will trigger edge brake, and set BRKEIF0 to 1 in EPWM_INTSTS1 register.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[1]     |BRKETRG2  |EPWM Edge Brake Software Trigger (Write Only) (Write Protect)
+     * |        |          |Write 1 to this bit will trigger edge brake, and set BRKEIF2 to 1 in EPWM_INTSTS1 register.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[2]     |BRKETRG4  |EPWM Edge Brake Software Trigger (Write Only) (Write Protect)
+     * |        |          |Write 1 to this bit will trigger edge brake, and set BRKEIF4 to 1 in EPWM_INTSTS1 register.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[8]     |BRKLTRG0  |EPWM Level Brake Software Trigger (Write Only) (Write Protect)
+     * |        |          |Write 1 to this bit will trigger level brake, and set BRKLIF0 to 1 in EPWM_INTSTS1 register.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[9]     |BRKLTRG2  |EPWM Level Brake Software Trigger (Write Only) (Write Protect)
+     * |        |          |Write 1 to this bit will trigger level brake, and set BRKLIF2 to 1 in EPWM_INTSTS1 register.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[10]    |BRKLTRG4  |EPWM Level Brake Software Trigger (Write Only) (Write Protect)
+     * |        |          |Write 1 to this bit will trigger level brake, and set BRKLIF4 to 1 in EPWM_INTSTS1 register.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * @var EPWM_T::INTEN0
+     * Offset: 0xE0  EPWM Interrupt Enable Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ZIEN0     |EPWM Zero Point Interrupt Enable Bits
+     * |        |          |0 = Zero point interrupt Disabled.
+     * |        |          |1 = Zero point interrupt Enabled.
+     * |        |          |Note: Odd channels will read always 0 at complementary mode.
+     * |[1]     |ZIEN1     |EPWM Zero Point Interrupt Enable Bits
+     * |        |          |0 = Zero point interrupt Disabled.
+     * |        |          |1 = Zero point interrupt Enabled.
+     * |        |          |Note: Odd channels will read always 0 at complementary mode.
+     * |[2]     |ZIEN2     |EPWM Zero Point Interrupt Enable Bits
+     * |        |          |0 = Zero point interrupt Disabled.
+     * |        |          |1 = Zero point interrupt Enabled.
+     * |        |          |Note: Odd channels will read always 0 at complementary mode.
+     * |[3]     |ZIEN3     |EPWM Zero Point Interrupt Enable Bits
+     * |        |          |0 = Zero point interrupt Disabled.
+     * |        |          |1 = Zero point interrupt Enabled.
+     * |        |          |Note: Odd channels will read always 0 at complementary mode.
+     * |[4]     |ZIEN4     |EPWM Zero Point Interrupt Enable Bits
+     * |        |          |0 = Zero point interrupt Disabled.
+     * |        |          |1 = Zero point interrupt Enabled.
+     * |        |          |Note: Odd channels will read always 0 at complementary mode.
+     * |[5]     |ZIEN5     |EPWM Zero Point Interrupt Enable Bits
+     * |        |          |0 = Zero point interrupt Disabled.
+     * |        |          |1 = Zero point interrupt Enabled.
+     * |        |          |Note: Odd channels will read always 0 at complementary mode.
+     * |[8]     |PIEN0     |EPWM Period Point Interrupt Enable Bits
+     * |        |          |0 = Period point interrupt Disabled.
+     * |        |          |1 = Period point interrupt Enabled.
+     * |        |          |Note1: When up-down counter type period point means center point.
+     * |        |          |Note2: Odd channels will read always 0 at complementary mode.
+     * |[9]     |PIEN1     |EPWM Period Point Interrupt Enable Bits
+     * |        |          |0 = Period point interrupt Disabled.
+     * |        |          |1 = Period point interrupt Enabled.
+     * |        |          |Note1: When up-down counter type period point means center point.
+     * |        |          |Note2: Odd channels will read always 0 at complementary mode.
+     * |[10]    |PIEN2     |EPWM Period Point Interrupt Enable Bits
+     * |        |          |0 = Period point interrupt Disabled.
+     * |        |          |1 = Period point interrupt Enabled.
+     * |        |          |Note1: When up-down counter type period point means center point.
+     * |        |          |Note2: Odd channels will read always 0 at complementary mode.
+     * |[11]    |PIEN3     |EPWM Period Point Interrupt Enable Bits
+     * |        |          |0 = Period point interrupt Disabled.
+     * |        |          |1 = Period point interrupt Enabled.
+     * |        |          |Note1: When up-down counter type period point means center point.
+     * |        |          |Note2: Odd channels will read always 0 at complementary mode.
+     * |[12]    |PIEN4     |EPWM Period Point Interrupt Enable Bits
+     * |        |          |0 = Period point interrupt Disabled.
+     * |        |          |1 = Period point interrupt Enabled.
+     * |        |          |Note1: When up-down counter type period point means center point.
+     * |        |          |Note2: Odd channels will read always 0 at complementary mode.
+     * |[13]    |PIEN5     |EPWM Period Point Interrupt Enable Bits
+     * |        |          |0 = Period point interrupt Disabled.
+     * |        |          |1 = Period point interrupt Enabled.
+     * |        |          |Note1: When up-down counter type period point means center point.
+     * |        |          |Note2: Odd channels will read always 0 at complementary mode.
+     * |[16]    |CMPUIEN0  |EPWM Compare Up Count Interrupt Enable Bits
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |        |          |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
+     * |[17]    |CMPUIEN1  |EPWM Compare Up Count Interrupt Enable Bits
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |        |          |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
+     * |[18]    |CMPUIEN2  |EPWM Compare Up Count Interrupt Enable Bits
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |        |          |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
+     * |[19]    |CMPUIEN3  |EPWM Compare Up Count Interrupt Enable Bits
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |        |          |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
+     * |[20]    |CMPUIEN4  |EPWM Compare Up Count Interrupt Enable Bits
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |        |          |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
+     * |[21]    |CMPUIEN5  |EPWM Compare Up Count Interrupt Enable Bits
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |        |          |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
+     * |[24]    |CMPDIEN0  |EPWM Compare Down Count Interrupt Enable Bits
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * |        |          |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
+     * |[25]    |CMPDIEN1  |EPWM Compare Down Count Interrupt Enable Bits
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * |        |          |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
+     * |[26]    |CMPDIEN2  |EPWM Compare Down Count Interrupt Enable Bits
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * |        |          |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
+     * |[27]    |CMPDIEN3  |EPWM Compare Down Count Interrupt Enable Bits
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * |        |          |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
+     * |[28]    |CMPDIEN4  |EPWM Compare Down Count Interrupt Enable Bits
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * |        |          |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
+     * |[29]    |CMPDIEN5  |EPWM Compare Down Count Interrupt Enable Bits
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * |        |          |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
+     * @var EPWM_T::INTEN1
+     * Offset: 0xE4  EPWM Interrupt Enable Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BRKEIEN0_1|EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)
+     * |        |          |0 = Edge-detect Brake interrupt for channel0/1 Disabled.
+     * |        |          |1 = Edge-detect Brake interrupt for channel0/1 Enabled.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[1]     |BRKEIEN2_3|EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)
+     * |        |          |0 = Edge-detect Brake interrupt for channel2/3 Disabled.
+     * |        |          |1 = Edge-detect Brake interrupt for channel2/3 Enabled.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[2]     |BRKEIEN4_5|EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)
+     * |        |          |0 = Edge-detect Brake interrupt for channel4/5 Disabled.
+     * |        |          |1 = Edge-detect Brake interrupt for channel4/5 Enabled.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[8]     |BRKLIEN0_1|EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)
+     * |        |          |0 = Level-detect Brake interrupt for channel0/1 Disabled.
+     * |        |          |1 = Level-detect Brake interrupt for channel0/1 Enabled.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[9]     |BRKLIEN2_3|EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)
+     * |        |          |0 = Level-detect Brake interrupt for channel2/3 Disabled.
+     * |        |          |1 = Level-detect Brake interrupt for channel2/3 Enabled.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[10]    |BRKLIEN4_5|EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)
+     * |        |          |0 = Level-detect Brake interrupt for channel4/5 Disabled.
+     * |        |          |1 = Level-detect Brake interrupt for channel4/5 Enabled.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * @var EPWM_T::INTSTS0
+     * Offset: 0xE8  EPWM Interrupt Flag Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ZIF0      |EPWM Zero Point Interrupt Flag
+     * |        |          |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
+     * |[1]     |ZIF1      |EPWM Zero Point Interrupt Flag
+     * |        |          |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
+     * |[2]     |ZIF2      |EPWM Zero Point Interrupt Flag
+     * |        |          |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
+     * |[3]     |ZIF3      |EPWM Zero Point Interrupt Flag
+     * |        |          |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
+     * |[4]     |ZIF4      |EPWM Zero Point Interrupt Flag
+     * |        |          |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
+     * |[5]     |ZIF5      |EPWM Zero Point Interrupt Flag
+     * |        |          |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero.
+     * |[8]     |PIF0      |EPWM Period Point Interrupt Flag
+     * |        |          |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD0, software can write 1 to clear this bit to zero
+     * |[9]     |PIF1      |EPWM Period Point Interrupt Flag
+     * |        |          |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD1, software can write 1 to clear this bit to zero
+     * |[10]    |PIF2      |EPWM Period Point Interrupt Flag
+     * |        |          |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD2, software can write 1 to clear this bit to zero
+     * |[11]    |PIF3      |EPWM Period Point Interrupt Flag
+     * |        |          |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD4, software can write 1 to clear this bit to zero
+     * |[12]    |PIF4      |EPWM Period Point Interrupt Flag
+     * |        |          |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD5, software can write 1 to clear this bit to zero
+     * |[13]    |PIF5      |EPWM Period Point Interrupt Flag
+     * |        |          |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero.
+     * |[16]    |CMPUIF0   |EPWM Compare Up Count Interrupt Flag
+     * |        |          |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT0, software can clear this bit by writing 1 to it.
+     * |        |          |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+     * |        |          |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
+     * |[17]    |CMPUIF1   |EPWM Compare Up Count Interrupt Flag
+     * |        |          |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT1, software can clear this bit by writing 1 to it.
+     * |        |          |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+     * |        |          |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
+     * |[18]    |CMPUIF2   |EPWM Compare Up Count Interrupt Flag
+     * |        |          |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT2, software can clear this bit by writing 1 to it.
+     * |        |          |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+     * |        |          |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
+     * |[19]    |CMPUIF3   |EPWM Compare Up Count Interrupt Flag
+     * |        |          |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT3, software can clear this bit by writing 1 to it.
+     * |        |          |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+     * |        |          |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
+     * |[20]    |CMPUIF4   |EPWM Compare Up Count Interrupt Flag
+     * |        |          |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT4, software can clear this bit by writing 1 to it.
+     * |        |          |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+     * |        |          |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
+     * |[21]    |CMPUIF5   |EPWM Compare Up Count Interrupt Flag
+     * |        |          |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT5, software can clear this bit by writing 1 to it.
+     * |        |          |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
+     * |        |          |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
+     * |[24]    |CMPDIF0   |EPWM Compare Down Count Interrupt Flag
+     * |        |          |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT0, software can clear this bit by writing 1 to it.
+     * |        |          |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+     * |        |          |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
+     * |[25]    |CMPDIF1   |EPWM Compare Down Count Interrupt Flag
+     * |        |          |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT1, software can clear this bit by writing 1 to it.
+     * |        |          |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+     * |        |          |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
+     * |[26]    |CMPDIF2   |EPWM Compare Down Count Interrupt Flag
+     * |        |          |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT2, software can clear this bit by writing 1 to it.
+     * |        |          |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+     * |        |          |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
+     * |[27]    |CMPDIF3   |EPWM Compare Down Count Interrupt Flag
+     * |        |          |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT3, software can clear this bit by writing 1 to it.
+     * |        |          |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+     * |        |          |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
+     * |[28]    |CMPDIF4   |EPWM Compare Down Count Interrupt Flag
+     * |        |          |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT4, software can clear this bit by writing 1 to it.
+     * |        |          |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+     * |        |          |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
+     * |[29]    |CMPDIF5   |EPWM Compare Down Count Interrupt Flag
+     * |        |          |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT5, software can clear this bit by writing 1 to it.
+     * |        |          |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
+     * |        |          |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
+     * @var EPWM_T::INTSTS1
+     * Offset: 0xEC  EPWM Interrupt Flag Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BRKEIF0   |EPWM Channel0 Edge-detect Brake Interrupt Flag (Write Protect)
+     * |        |          |0 = EPWM channel0 edge-detect brake event do not happened.
+     * |        |          |1 = When EPWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[1]     |BRKEIF1   |EPWM Channel1 Edge-detect Brake Interrupt Flag (Write Protect)
+     * |        |          |0 = EPWM channel1 edge-detect brake event do not happened.
+     * |        |          |1 = When EPWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[2]     |BRKEIF2   |EPWM Channel2 Edge-detect Brake Interrupt Flag (Write Protect)
+     * |        |          |0 = EPWM channel2 edge-detect brake event do not happened.
+     * |        |          |1 = When EPWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[3]     |BRKEIF3   |EPWM Channel3 Edge-detect Brake Interrupt Flag (Write Protect)
+     * |        |          |0 = EPWM channel3 edge-detect brake event do not happened.
+     * |        |          |1 = When EPWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[4]     |BRKEIF4   |EPWM Channel4 Edge-detect Brake Interrupt Flag (Write Protect)
+     * |        |          |0 = EPWM channel4 edge-detect brake event do not happened.
+     * |        |          |1 = When EPWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[5]     |BRKEIF5   |EPWM Channel5 Edge-detect Brake Interrupt Flag (Write Protect)
+     * |        |          |0 = EPWM channel5 edge-detect brake event do not happened.
+     * |        |          |1 = When EPWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[8]     |BRKLIF0   |EPWM Channel0 Level-detect Brake Interrupt Flag (Write Protect)
+     * |        |          |0 = EPWM channel0 level-detect brake event do not happened.
+     * |        |          |1 = When EPWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[9]     |BRKLIF1   |EPWM Channel1 Level-detect Brake Interrupt Flag (Write Protect)
+     * |        |          |0 = EPWM channel1 level-detect brake event do not happened.
+     * |        |          |1 = When EPWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[10]    |BRKLIF2   |EPWM Channel2 Level-detect Brake Interrupt Flag (Write Protect)
+     * |        |          |0 = EPWM channel2 level-detect brake event do not happened.
+     * |        |          |1 = When EPWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[11]    |BRKLIF3   |EPWM Channel3 Level-detect Brake Interrupt Flag (Write Protect)
+     * |        |          |0 = EPWM channel3 level-detect brake event do not happened.
+     * |        |          |1 = When EPWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[12]    |BRKLIF4   |EPWM Channel4 Level-detect Brake Interrupt Flag (Write Protect)
+     * |        |          |0 = EPWM channel4 level-detect brake event do not happened.
+     * |        |          |1 = When EPWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[13]    |BRKLIF5   |EPWM Channel5 Level-detect Brake Interrupt Flag (Write Protect)
+     * |        |          |0 = EPWM channel5 level-detect brake event do not happened.
+     * |        |          |1 = When EPWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
+     * |        |          |Note: This register is write protected. Refer to SYS_REGLCTL register.
+     * |[16]    |BRKESTS0  |EPWM Channel0 Edge-detect Brake Status (Read Only)
+     * |        |          |0 = EPWM channel0 edge-detect brake state is released.
+     * |        |          |1 = When EPWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state, writing 1 to clear.
+     * |[17]    |BRKESTS1  |EPWM Channel1 Edge-detect Brake Status (Read Only)
+     * |        |          |0 = EPWM channel1 edge-detect brake state is released.
+     * |        |          |1 = When EPWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state, writing 1 to clear.
+     * |[18]    |BRKESTS2  |EPWM Channel2 Edge-detect Brake Status (Read Only)
+     * |        |          |0 = EPWM channel2 edge-detect brake state is released.
+     * |        |          |1 = When EPWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state, writing 1 to clear.
+     * |[19]    |BRKESTS3  |EPWM Channel3 Edge-detect Brake Status (Read Only)
+     * |        |          |0 = EPWM channel3 edge-detect brake state is released.
+     * |        |          |1 = When EPWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state, writing 1 to clear.
+     * |[20]    |BRKESTS4  |EPWM Channel4 Edge-detect Brake Status (Read Only)
+     * |        |          |0 = EPWM channel4 edge-detect brake state is released.
+     * |        |          |1 = When EPWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state, writing 1 to clear.
+     * |[21]    |BRKESTS5  |EPWM Channel5 Edge-detect Brake Status (Read Only)
+     * |        |          |0 = EPWM channel5 edge-detect brake state is released.
+     * |        |          |1 = When EPWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state, writing 1 to clear.
+     * |[24]    |BRKLSTS0  |EPWM Channel0 Level-detect Brake Status (Read Only)
+     * |        |          |0 = EPWM channel0 level-detect brake state is released.
+     * |        |          |1 = When EPWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state.
+     * |        |          |Note: This bit is read only and auto cleared by hardware
+     * |        |          |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
+     * |        |          |The EPWM waveform will start output from next full EPWM period.
+     * |[25]    |BRKLSTS1  |EPWM Channel1 Level-detect Brake Status (Read Only)
+     * |        |          |0 = EPWM channel1 level-detect brake state is released.
+     * |        |          |1 = When EPWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state.
+     * |        |          |Note: This bit is read only and auto cleared by hardware
+     * |        |          |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
+     * |        |          |The EPWM waveform will start output from next full EPWM period.
+     * |[26]    |BRKLSTS2  |EPWM Channel2 Level-detect Brake Status (Read Only)
+     * |        |          |0 = EPWM channel2 level-detect brake state is released.
+     * |        |          |1 = When EPWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state.
+     * |        |          |Note: This bit is read only and auto cleared by hardware
+     * |        |          |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
+     * |        |          |The EPWM waveform will start output from next full EPWM period.
+     * |[27]    |BRKLSTS3  |EPWM Channel3 Level-detect Brake Status (Read Only)
+     * |        |          |0 = EPWM channel3 level-detect brake state is released.
+     * |        |          |1 = When EPWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state.
+     * |        |          |Note: This bit is read only and auto cleared by hardware
+     * |        |          |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
+     * |        |          |The EPWM waveform will start output from next full EPWM period.
+     * |[28]    |BRKLSTS4  |EPWM Channel4 Level-detect Brake Status (Read Only)
+     * |        |          |0 = EPWM channel4 level-detect brake state is released.
+     * |        |          |1 = When EPWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state.
+     * |        |          |Note: This bit is read only and auto cleared by hardware
+     * |        |          |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
+     * |        |          |The EPWM waveform will start output from next full EPWM period.
+     * |[29]    |BRKLSTS5  |EPWM Channel5 Level-detect Brake Status (Read Only)
+     * |        |          |0 = EPWM channel5 level-detect brake state is released.
+     * |        |          |1 = When EPWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state.
+     * |        |          |Note: This bit is read only and auto cleared by hardware
+     * |        |          |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished
+     * |        |          |The EPWM waveform will start output from next full EPWM period.
+     * @var EPWM_T::DACTRGEN
+     * Offset: 0xF4  EPWM Trigger DAC Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ZTE0      |EPWM Zero Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
+     * |        |          |0 = EPWM period point trigger DAC function Disabled.
+     * |        |          |1 = EPWM period point trigger DAC function Enabled.
+     * |[1]     |ZTE1      |EPWM Zero Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
+     * |        |          |0 = EPWM period point trigger DAC function Disabled.
+     * |        |          |1 = EPWM period point trigger DAC function Enabled.
+     * |[2]     |ZTE2      |EPWM Zero Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
+     * |        |          |0 = EPWM period point trigger DAC function Disabled.
+     * |        |          |1 = EPWM period point trigger DAC function Enabled.
+     * |[3]     |ZTE3      |EPWM Zero Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
+     * |        |          |0 = EPWM period point trigger DAC function Disabled.
+     * |        |          |1 = EPWM period point trigger DAC function Enabled.
+     * |[4]     |ZTE4      |EPWM Zero Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
+     * |        |          |0 = EPWM period point trigger DAC function Disabled.
+     * |        |          |1 = EPWM period point trigger DAC function Enabled.
+     * |[5]     |ZTE5      |EPWM Zero Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
+     * |        |          |0 = EPWM period point trigger DAC function Disabled.
+     * |        |          |1 = EPWM period point trigger DAC function Enabled.
+     * |[8]     |PTE0      |EPWM Period Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
+     * |        |          |0 = EPWM period point trigger DAC function Disabled.
+     * |        |          |1 = EPWM period point trigger DAC function Enabled.
+     * |[9]     |PTE1      |EPWM Period Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
+     * |        |          |0 = EPWM period point trigger DAC function Disabled.
+     * |        |          |1 = EPWM period point trigger DAC function Enabled.
+     * |[10]    |PTE2      |EPWM Period Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
+     * |        |          |0 = EPWM period point trigger DAC function Disabled.
+     * |        |          |1 = EPWM period point trigger DAC function Enabled.
+     * |[11]    |PTE3      |EPWM Period Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
+     * |        |          |0 = EPWM period point trigger DAC function Disabled.
+     * |        |          |1 = EPWM period point trigger DAC function Enabled.
+     * |[12]    |PTE4      |EPWM Period Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
+     * |        |          |0 = EPWM period point trigger DAC function Disabled.
+     * |        |          |1 = EPWM period point trigger DAC function Enabled.
+     * |[13]    |PTE5      |EPWM Period Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1.
+     * |        |          |0 = EPWM period point trigger DAC function Disabled.
+     * |        |          |1 = EPWM period point trigger DAC function Enabled.
+     * |[16]    |CUTRGE0   |EPWM Compare Up Count Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
+     * |        |          |0 = EPWM Compare Up point trigger DAC function Disabled.
+     * |        |          |1 = EPWM Compare Up point trigger DAC function Enabled.
+     * |        |          |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
+     * |        |          |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
+     * |[17]    |CUTRGE1   |EPWM Compare Up Count Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
+     * |        |          |0 = EPWM Compare Up point trigger DAC function Disabled.
+     * |        |          |1 = EPWM Compare Up point trigger DAC function Enabled.
+     * |        |          |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
+     * |        |          |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
+     * |[18]    |CUTRGE2   |EPWM Compare Up Count Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
+     * |        |          |0 = EPWM Compare Up point trigger DAC function Disabled.
+     * |        |          |1 = EPWM Compare Up point trigger DAC function Enabled.
+     * |        |          |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
+     * |        |          |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
+     * |[19]    |CUTRGE3   |EPWM Compare Up Count Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
+     * |        |          |0 = EPWM Compare Up point trigger DAC function Disabled.
+     * |        |          |1 = EPWM Compare Up point trigger DAC function Enabled.
+     * |        |          |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
+     * |        |          |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
+     * |[20]    |CUTRGE4   |EPWM Compare Up Count Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
+     * |        |          |0 = EPWM Compare Up point trigger DAC function Disabled.
+     * |        |          |1 = EPWM Compare Up point trigger DAC function Enabled.
+     * |        |          |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
+     * |        |          |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
+     * |[21]    |CUTRGE5   |EPWM Compare Up Count Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1.
+     * |        |          |0 = EPWM Compare Up point trigger DAC function Disabled.
+     * |        |          |1 = EPWM Compare Up point trigger DAC function Enabled.
+     * |        |          |Note1: This bit should keep at 0 when EPWM counter operating in down counter type.
+     * |        |          |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4.
+     * |[24]    |CDTRGE0   |EPWM Compare Down Count Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
+     * |        |          |0 = EPWM Compare Down count point trigger DAC function Disabled.
+     * |        |          |1 = EPWM Compare Down count point trigger DAC function Enabled.
+     * |        |          |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
+     * |        |          |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
+     * |[25]    |CDTRGE1   |EPWM Compare Down Count Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
+     * |        |          |0 = EPWM Compare Down count point trigger DAC function Disabled.
+     * |        |          |1 = EPWM Compare Down count point trigger DAC function Enabled.
+     * |        |          |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
+     * |        |          |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
+     * |[26]    |CDTRGE2   |EPWM Compare Down Count Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
+     * |        |          |0 = EPWM Compare Down count point trigger DAC function Disabled.
+     * |        |          |1 = EPWM Compare Down count point trigger DAC function Enabled.
+     * |        |          |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
+     * |        |          |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
+     * |[27]    |CDTRGE3   |EPWM Compare Down Count Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
+     * |        |          |0 = EPWM Compare Down count point trigger DAC function Disabled.
+     * |        |          |1 = EPWM Compare Down count point trigger DAC function Enabled.
+     * |        |          |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
+     * |        |          |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
+     * |[28]    |CDTRGE4   |EPWM Compare Down Count Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
+     * |        |          |0 = EPWM Compare Down count point trigger DAC function Disabled.
+     * |        |          |1 = EPWM Compare Down count point trigger DAC function Enabled.
+     * |        |          |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
+     * |        |          |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
+     * |[29]    |CDTRGE5   |EPWM Compare Down Count Point Trigger DAC Enable Bits
+     * |        |          |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.
+     * |        |          |0 = EPWM Compare Down count point trigger DAC function Disabled.
+     * |        |          |1 = EPWM Compare Down count point trigger DAC function Enabled.
+     * |        |          |Note1: This bit should keep at 0 when EPWM counter operating in up counter type.
+     * |        |          |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4.
+     * @var EPWM_T::EADCTS0
+     * Offset: 0xF8  EPWM Trigger EADC Source Select Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |TRGSEL0   |EPWM_CH0 Trigger EADC Source Select
+     * |        |          |0000 = EPWM_CH0 zero point.
+     * |        |          |0001 = EPWM_CH0 period point.
+     * |        |          |0010 = EPWM_CH0 zero or period point.
+     * |        |          |0011 = EPWM_CH0 up-count CMPDAT point.
+     * |        |          |0100 = EPWM_CH0 down-count CMPDAT point.
+     * |        |          |0101 = EPWM_CH1 zero point.
+     * |        |          |0110 = EPWM_CH1 period point.
+     * |        |          |0111 = EPWM_CH1 zero or period point.
+     * |        |          |1000 = EPWM_CH1 up-count CMPDAT point.
+     * |        |          |1001 = EPWM_CH1 down-count CMPDAT point.
+     * |        |          |1010 = EPWM_CH0 up-count free CMPDAT point.
+     * |        |          |1011 = EPWM_CH0 down-count free CMPDAT point.
+     * |        |          |1100 = EPWM_CH2 up-count free CMPDAT point.
+     * |        |          |1101 = EPWM_CH2 down-count free CMPDAT point.
+     * |        |          |1110 = EPWM_CH4 up-count free CMPDAT point.
+     * |        |          |1111 = EPWM_CH4 down-count free CMPDAT point.
+     * |[7]     |TRGEN0    |EPWM_CH0 Trigger EADC enable bit
+     * |[11:8]  |TRGSEL1   |EPWM_CH1 Trigger EADC Source Select
+     * |        |          |0000 = EPWM_CH0 zero point.
+     * |        |          |0001 = EPWM_CH0 period point.
+     * |        |          |0010 = EPWM_CH0 zero or period point.
+     * |        |          |0011 = EPWM_CH0 up-count CMPDAT point.
+     * |        |          |0100 = EPWM_CH0 down-count CMPDAT point.
+     * |        |          |0101 = EPWM_CH1 zero point.
+     * |        |          |0110 = EPWM_CH1 period point.
+     * |        |          |0111 = EPWM_CH1 zero or period point.
+     * |        |          |1000 = EPWM_CH1 up-count CMPDAT point.
+     * |        |          |1001 = EPWM_CH1 down-count CMPDAT point.
+     * |        |          |1010 = EPWM_CH0 up-count free CMPDAT point.
+     * |        |          |1011 = EPWM_CH0 down-count free CMPDAT point.
+     * |        |          |1100 = EPWM_CH2 up-count free CMPDAT point.
+     * |        |          |1101 = EPWM_CH2 down-count free CMPDAT point.
+     * |        |          |1110 = EPWM_CH4 up-count free CMPDAT point.
+     * |        |          |1111 = EPWM_CH4 down-count free CMPDAT point.
+     * |[15]    |TRGEN1    |EPWM_CH1 Trigger EADC enable bit
+     * |[19:16] |TRGSEL2   |EPWM_CH2 Trigger EADC Source Select
+     * |        |          |0000 = EPWM_CH2 zero point.
+     * |        |          |0001 = EPWM_CH2 period point.
+     * |        |          |0010 = EPWM_CH2 zero or period point.
+     * |        |          |0011 = EPWM_CH2 up-count CMPDAT point.
+     * |        |          |0100 = EPWM_CH2 down-count CMPDAT point.
+     * |        |          |0101 = EPWM_CH3 zero point.
+     * |        |          |0110 = EPWM_CH3 period point.
+     * |        |          |0111 = EPWM_CH3 zero or period point.
+     * |        |          |1000 = EPWM_CH3 up-count CMPDAT point.
+     * |        |          |1001 = EPWM_CH3 down-count CMPDAT point.
+     * |        |          |1010 = EPWM_CH0 up-count free CMPDAT point.
+     * |        |          |1011 = EPWM_CH0 down-count free CMPDAT point.
+     * |        |          |1100 = EPWM_CH2 up-count free CMPDAT point.
+     * |        |          |1101 = EPWM_CH2 down-count free CMPDAT point.
+     * |        |          |1110 = EPWM_CH4 up-count free CMPDAT point.
+     * |        |          |1111 = EPWM_CH4 down-count free CMPDAT point.
+     * |[23]    |TRGEN2    |EPWM_CH2 Trigger EADC enable bit
+     * |[27:24] |TRGSEL3   |EPWM_CH3 Trigger EADC Source Select
+     * |        |          |0000 = EPWM_CH2 zero point.
+     * |        |          |0001 = EPWM_CH2 period point.
+     * |        |          |0010 = EPWM_CH2 zero or period point.
+     * |        |          |0011 = EPWM_CH2 up-count CMPDAT point.
+     * |        |          |0100 = EPWM_CH2 down-count CMPDAT point.
+     * |        |          |0101 = EPWM_CH3 zero point.
+     * |        |          |0110 = EPWM_CH3 period point.
+     * |        |          |0111 = EPWM_CH3 zero or period point.
+     * |        |          |1000 = EPWM_CH3 up-count CMPDAT point.
+     * |        |          |1001 = EPWM_CH3 down-count CMPDAT point.
+     * |        |          |1010 = EPWM_CH0 up-count free CMPDAT point.
+     * |        |          |1011 = EPWM_CH0 down-count free CMPDAT point.
+     * |        |          |1100 = EPWM_CH2 up-count free CMPDAT point.
+     * |        |          |1101 = EPWM_CH2 down-count free CMPDAT point.
+     * |        |          |1110 = EPWM_CH4 up-count free CMPDAT point.
+     * |        |          |1111 = EPWM_CH4 down-count free CMPDAT point.
+     * |[31]    |TRGEN3    |EPWM_CH3 Trigger EADC enable bit
+     * @var EPWM_T::EADCTS1
+     * Offset: 0xFC  EPWM Trigger EADC Source Select Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |TRGSEL4   |EPWM_CH4 Trigger EADC Source Select
+     * |        |          |0000 = EPWM_CH4 zero point.
+     * |        |          |0001 = EPWM_CH4 period point.
+     * |        |          |0010 = EPWM_CH4 zero or period point.
+     * |        |          |0011 = EPWM_CH4 up-count CMPDAT point.
+     * |        |          |0100 = EPWM_CH4 down-count CMPDAT point.
+     * |        |          |0101 = EPWM_CH5 zero point.
+     * |        |          |0110 = EPWM_CH5 period point.
+     * |        |          |0111 = EPWM_CH5 zero or period point.
+     * |        |          |1000 = EPWM_CH5 up-count CMPDAT point.
+     * |        |          |1001 = EPWM_CH5 down-count CMPDAT point.
+     * |        |          |1010 = EPWM_CH0 up-count free CMPDAT point.
+     * |        |          |1011 = EPWM_CH0 down-count free CMPDAT point.
+     * |        |          |1100 = EPWM_CH2 up-count free CMPDAT point.
+     * |        |          |1101 = EPWM_CH2 down-count free CMPDAT point.
+     * |        |          |1110 = EPWM_CH4 up-count free CMPDAT point.
+     * |        |          |1111 = EPWM_CH4 down-count free CMPDAT point.
+     * |[7]     |TRGEN4    |EPWM_CH4 Trigger EADC enable bit
+     * |[11:8]  |TRGSEL5   |EPWM_CH5 Trigger EADC Source Select
+     * |        |          |0000 = EPWM_CH4 zero point.
+     * |        |          |0001 = EPWM_CH4 period point.
+     * |        |          |0010 = EPWM_CH4 zero or period point.
+     * |        |          |0011 = EPWM_CH4 up-count CMPDAT point.
+     * |        |          |0100 = EPWM_CH4 down-count CMPDAT point.
+     * |        |          |0101 = EPWM_CH5 zero point.
+     * |        |          |0110 = EPWM_CH5 period point.
+     * |        |          |0111 = EPWM_CH5 zero or period point.
+     * |        |          |1000 = EPWM_CH5 up-count CMPDAT point.
+     * |        |          |1001 = EPWM_CH5 down-count CMPDAT point.
+     * |        |          |1010 = EPWM_CH0 up-count free CMPDAT point.
+     * |        |          |1011 = EPWM_CH0 down-count free CMPDAT point.
+     * |        |          |1100 = EPWM_CH2 up-count free CMPDAT point.
+     * |        |          |1101 = EPWM_CH2 down-count free CMPDAT point.
+     * |        |          |1110 = EPWM_CH4 up-count free CMPDAT point.
+     * |        |          |1111 = EPWM_CH4 down-count free CMPDAT point.
+     * |[15]    |TRGEN5    |EPWM_CH5 Trigger EADC enable bit
+     * @var EPWM_T::FTCMPDAT[3]
+     * Offset: 0x100  EPWM Free Trigger Compare Register 0/1,2/3,4/5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |FTCMP     |EPWM Free Trigger Compare Register
+     * |        |          |FTCMP use to compare with even CNTR to trigger EADC
+     * |        |          |FTCMPDAT0, 2, 4 corresponding complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5.
+     * @var EPWM_T::SSCTL
+     * Offset: 0x110  EPWM Synchronous Start Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SSEN0     |EPWM Synchronous Start Function Enable Bits
+     * |        |          |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
+     * |        |          |0 = EPWM synchronous start function Disabled.
+     * |        |          |1 = EPWM synchronous start function Enabled.
+     * |[1]     |SSEN1     |EPWM Synchronous Start Function Enable Bits
+     * |        |          |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
+     * |        |          |0 = EPWM synchronous start function Disabled.
+     * |        |          |1 = EPWM synchronous start function Enabled.
+     * |[2]     |SSEN2     |EPWM Synchronous Start Function Enable Bits
+     * |        |          |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
+     * |        |          |0 = EPWM synchronous start function Disabled.
+     * |        |          |1 = EPWM synchronous start function Enabled.
+     * |[3]     |SSEN3     |EPWM Synchronous Start Function Enable Bits
+     * |        |          |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
+     * |        |          |0 = EPWM synchronous start function Disabled.
+     * |        |          |1 = EPWM synchronous start function Enabled.
+     * |[4]     |SSEN4     |EPWM Synchronous Start Function Enable Bits
+     * |        |          |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
+     * |        |          |0 = EPWM synchronous start function Disabled.
+     * |        |          |1 = EPWM synchronous start function Enabled.
+     * |[5]     |SSEN5     |EPWM Synchronous Start Function Enable Bits
+     * |        |          |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
+     * |        |          |0 = EPWM synchronous start function Disabled.
+     * |        |          |1 = EPWM synchronous start function Enabled.
+     * |[9:8]   |SSRC      |EPWM Synchronous Start Source Select Bits
+     * |        |          |00 = Synchronous start source come from EPWM0.
+     * |        |          |01 = Synchronous start source come from EPWM1.
+     * |        |          |10 = Synchronous start source come from BPWM0.
+     * |        |          |11 = Synchronous start source come from BPWM1.
+     * @var EPWM_T::SSTRG
+     * Offset: 0x114  EPWM Synchronous Start Trigger Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CNTSEN    |EPWM Counter Synchronous Start Enable (Write Only)
+     * |        |          |PMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time.
+     * |        |          |Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated EPWM channel counter synchronous start function is enabled.
+     * @var EPWM_T::LEBCTL
+     * Offset: 0x118  EPWM Leading Edge Blanking Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |LEBEN     |EPWM Leading Edge Blanking Enable Bit
+     * |        |          |0 = EPWM Leading Edge Blanking Disabled.
+     * |        |          |1 = EPWM Leading Edge Blanking Enabled.
+     * |[8]     |SRCEN0    |EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit
+     * |        |          |0 = EPWM Leading Edge Blanking Source from EPWM_CH0 Disabled.
+     * |        |          |1 = EPWM Leading Edge Blanking Source from EPWM_CH0 Enabled.
+     * |[9]     |SRCEN2    |EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit
+     * |        |          |0 = EPWM Leading Edge Blanking Source from EPWM_CH2 Disabled.
+     * |        |          |1 = EPWM Leading Edge Blanking Source from EPWM_CH2 Enabled.
+     * |[10]    |SRCEN4    |EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit
+     * |        |          |0 = EPWM Leading Edge Blanking Source from EPWM_CH4 Disabled.
+     * |        |          |1 = EPWM Leading Edge Blanking Source from EPWM_CH4 Enabled.
+     * |[17:16] |TRGTYPE   |EPWM Leading Edge Blanking Trigger Type
+     * |        |          |0 = When detect leading edge blanking source rising edge, blanking counter start counting.
+     * |        |          |1 = When detect leading edge blanking source falling edge, blanking counter start counting.
+     * |        |          |2 = When detect leading edge blanking source rising or falling edge, blanking counter start counting.
+     * |        |          |3 = Reserved.
+     * @var EPWM_T::LEBCNT
+     * Offset: 0x11C  EPWM Leading Edge Blanking Counter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[8:0]   |LEBCNT    |EPWM Leading Edge Blanking Counter
+     * |        |          |This counter value decides leading edge blanking window size.
+     * |        |          |Blanking window size = LEBCNT+1, and LEB counter clock base is ECLK.
+     * @var EPWM_T::STATUS
+     * Offset: 0x120  EPWM Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CNTMAXF0  |Time-base Counter Equal to 0xFFFF Latched Flag
+     * |        |          |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
+     * |        |          |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
+     * |[1]     |CNTMAXF1  |Time-base Counter Equal to 0xFFFF Latched Flag
+     * |        |          |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
+     * |        |          |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
+     * |[2]     |CNTMAXF2  |Time-base Counter Equal to 0xFFFF Latched Flag
+     * |        |          |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
+     * |        |          |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
+     * |[3]     |CNTMAXF3  |Time-base Counter Equal to 0xFFFF Latched Flag
+     * |        |          |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
+     * |        |          |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
+     * |[4]     |CNTMAXF4  |Time-base Counter Equal to 0xFFFF Latched Flag
+     * |        |          |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
+     * |        |          |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
+     * |[5]     |CNTMAXF5  |Time-base Counter Equal to 0xFFFF Latched Flag
+     * |        |          |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
+     * |        |          |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
+     * |[8]     |SYNCINF0  |Input Synchronization Latched Flag
+     * |        |          |0 = Indicates no SYNC_IN event has occurred.
+     * |        |          |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit.
+     * |[9]     |SYNCINF2  |Input Synchronization Latched Flag
+     * |        |          |0 = Indicates no SYNC_IN event has occurred.
+     * |        |          |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit.
+     * |[10]    |SYNCINF4  |Input Synchronization Latched Flag
+     * |        |          |0 = Indicates no SYNC_IN event has occurred.
+     * |        |          |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit.
+     * |[16]    |EADCTRGF0 |EADC Start of Conversion Flag
+     * |        |          |0 = Indicates no EADC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+     * |[17]    |EADCTRGF1 |EADC Start of Conversion Flag
+     * |        |          |0 = Indicates no EADC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+     * |[18]    |EADCTRGF2 |EADC Start of Conversion Flag
+     * |        |          |0 = Indicates no EADC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+     * |[19]    |EADCTRGF3 |EADC Start of Conversion Flag
+     * |        |          |0 = Indicates no EADC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+     * |[20]    |EADCTRGF4 |EADC Start of Conversion Flag
+     * |        |          |0 = Indicates no EADC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+     * |[21]    |EADCTRGF5 |EADC Start of Conversion Flag
+     * |        |          |0 = Indicates no EADC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
+     * |[24]    |DACTRGF   |DAC Start of Conversion Flag
+     * |        |          |0 = Indicates no DAC start of conversion trigger event has occurred.
+     * |        |          |1 = Indicates an DAC start of conversion trigger event has occurred, software can write 1 to clear this bit
+     * @var EPWM_T::IFA[6]
+     * Offset: 0x130  EPWM Interrupt Flag Accumulator Register 0~5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |IFACNT    |EPWM_CHn Interrupt Flag Counter
+     * |        |          |The register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.
+     * |        |          |EPWM flag will be set in every IFACNT[15:0] times of EPWM period.
+     * |[24]    |STPMOD    |EPWM_CHn Interrupt Flag Accumulator Stop Mode Enable Bits
+     * |        |          |0 = EPWM_CHn interrupt flag accumulator stop mode disable.
+     * |        |          |1 = EPWM_CHn interrupt flag accumulator stop mode enable.
+     * |[29:28] |IFASEL    |EPWM_CHn Interrupt Flag Accumulator Source Select
+     * |        |          |00 = CNT equal to Zero in channel n.
+     * |        |          |01 = CNT equal to PERIOD in channel n.
+     * |        |          |10 = CNT equal to CMPU in channel n.
+     * |        |          |11 = CNT equal to CMPD in channel n.
+     * |[31]    |IFAEN     |EPWM_CHn Interrupt Flag Accumulator Enable Bits
+     * |        |          |0 = EPWM_CHn interrupt flag accumulator disable.
+     * |        |          |1 = EPWM_CHn interrupt flag accumulator enable.
+     * @var EPWM_T::AINTSTS
+     * Offset: 0x150  EPWM Accumulator Interrupt Flag Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |IFAIF0    |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
+     * |        |          |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
+     * |[1]     |IFAIF1    |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
+     * |        |          |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
+     * |[2]     |IFAIF2    |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
+     * |        |          |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
+     * |[3]     |IFAIF3    |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
+     * |        |          |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
+     * |[4]     |IFAIF4    |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
+     * |        |          |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
+     * |[5]     |IFAIF5    |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag
+     * |        |          |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
+     * @var EPWM_T::AINTEN
+     * Offset: 0x154  EPWM Accumulator Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |IFAIEN0   |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
+     * |        |          |0 = Interrupt Flag accumulator interrupt Disabled.
+     * |        |          |1 = Interrupt Flag accumulator interrupt Enabled.
+     * |[1]     |IFAIEN1   |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
+     * |        |          |0 = Interrupt Flag accumulator interrupt Disabled.
+     * |        |          |1 = Interrupt Flag accumulator interrupt Enabled.
+     * |[2]     |IFAIEN2   |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
+     * |        |          |0 = Interrupt Flag accumulator interrupt Disabled.
+     * |        |          |1 = Interrupt Flag accumulator interrupt Enabled.
+     * |[3]     |IFAIEN3   |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
+     * |        |          |0 = Interrupt Flag accumulator interrupt Disabled.
+     * |        |          |1 = Interrupt Flag accumulator interrupt Enabled.
+     * |[4]     |IFAIEN4   |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
+     * |        |          |0 = Interrupt Flag accumulator interrupt Disabled.
+     * |        |          |1 = Interrupt Flag accumulator interrupt Enabled.
+     * |[5]     |IFAIEN5   |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
+     * |        |          |0 = Interrupt Flag accumulator interrupt Disabled.
+     * |        |          |1 = Interrupt Flag accumulator interrupt Enabled.
+     * @var EPWM_T::APDMACTL
+     * Offset: 0x158  EPWM Accumulator PDMA Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |APDMAEN0  |Channel N Accumulator PDMA Enable Bits
+     * |        |          |0 = Channel n PDMA function Disabled.
+     * |        |          |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
+     * |[1]     |APDMAEN1  |Channel N Accumulator PDMA Enable Bits
+     * |        |          |0 = Channel n PDMA function Disabled.
+     * |        |          |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
+     * |[2]     |APDMAEN2  |Channel N Accumulator PDMA Enable Bits
+     * |        |          |0 = Channel n PDMA function Disabled.
+     * |        |          |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
+     * |[3]     |APDMAEN3  |Channel N Accumulator PDMA Enable Bits
+     * |        |          |0 = Channel n PDMA function Disabled.
+     * |        |          |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
+     * |[4]     |APDMAEN4  |Channel N Accumulator PDMA Enable Bits
+     * |        |          |0 = Channel n PDMA function Disabled.
+     * |        |          |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
+     * |[5]     |APDMAEN5  |Channel N Accumulator PDMA Enable Bits
+     * |        |          |0 = Channel n PDMA function Disabled.
+     * |        |          |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register.
+     * @var EPWM_T::CAPINEN
+     * Offset: 0x200  EPWM Capture Input Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CAPINEN0  |Capture Input Enable Bits
+     * |        |          |0 = EPWM Channel capture input path Disabled
+     * |        |          |The input of EPWM channel capture function is always regarded as 0.
+     * |        |          |1 = EPWM Channel capture input path Enabled
+     * |        |          |The input of EPWM channel capture function comes from correlative multifunction pin.
+     * |[1]     |CAPINEN1  |Capture Input Enable Bits
+     * |        |          |0 = EPWM Channel capture input path Disabled
+     * |        |          |The input of EPWM channel capture function is always regarded as 0.
+     * |        |          |1 = EPWM Channel capture input path Enabled
+     * |        |          |The input of EPWM channel capture function comes from correlative multifunction pin.
+     * |[2]     |CAPINEN2  |Capture Input Enable Bits
+     * |        |          |0 = EPWM Channel capture input path Disabled
+     * |        |          |The input of EPWM channel capture function is always regarded as 0.
+     * |        |          |1 = EPWM Channel capture input path Enabled
+     * |        |          |The input of EPWM channel capture function comes from correlative multifunction pin.
+     * |[3]     |CAPINEN3  |Capture Input Enable Bits
+     * |        |          |0 = EPWM Channel capture input path Disabled
+     * |        |          |The input of EPWM channel capture function is always regarded as 0.
+     * |        |          |1 = EPWM Channel capture input path Enabled
+     * |        |          |The input of EPWM channel capture function comes from correlative multifunction pin.
+     * |[4]     |CAPINEN4  |Capture Input Enable Bits
+     * |        |          |0 = EPWM Channel capture input path Disabled
+     * |        |          |The input of EPWM channel capture function is always regarded as 0.
+     * |        |          |1 = EPWM Channel capture input path Enabled
+     * |        |          |The input of EPWM channel capture function comes from correlative multifunction pin.
+     * |[5]     |CAPINEN5  |Capture Input Enable Bits
+     * |        |          |0 = EPWM Channel capture input path Disabled
+     * |        |          |The input of EPWM channel capture function is always regarded as 0.
+     * |        |          |1 = EPWM Channel capture input path Enabled
+     * |        |          |The input of EPWM channel capture function comes from correlative multifunction pin.
+     * @var EPWM_T::CAPCTL
+     * Offset: 0x204  EPWM Capture Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CAPEN0    |Capture Function Enable Bits
+     * |        |          |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+     * |        |          |1 = Capture function Enabled
+     * |        |          |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+     * |[1]     |CAPEN1    |Capture Function Enable Bits
+     * |        |          |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+     * |        |          |1 = Capture function Enabled
+     * |        |          |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+     * |[2]     |CAPEN2    |Capture Function Enable Bits
+     * |        |          |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+     * |        |          |1 = Capture function Enabled
+     * |        |          |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+     * |[3]     |CAPEN3    |Capture Function Enable Bits
+     * |        |          |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+     * |        |          |1 = Capture function Enabled
+     * |        |          |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+     * |[4]     |CAPEN4    |Capture Function Enable Bits
+     * |        |          |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+     * |        |          |1 = Capture function Enabled
+     * |        |          |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+     * |[5]     |CAPEN5    |Capture Function Enable Bits
+     * |        |          |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
+     * |        |          |1 = Capture function Enabled
+     * |        |          |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
+     * |[8]     |CAPINV0   |Capture Inverter Enable Bits
+     * |        |          |0 = Capture source inverter Disabled.
+     * |        |          |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+     * |[9]     |CAPINV1   |Capture Inverter Enable Bits
+     * |        |          |0 = Capture source inverter Disabled.
+     * |        |          |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+     * |[10]    |CAPINV2   |Capture Inverter Enable Bits
+     * |        |          |0 = Capture source inverter Disabled.
+     * |        |          |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+     * |[11]    |CAPINV3   |Capture Inverter Enable Bits
+     * |        |          |0 = Capture source inverter Disabled.
+     * |        |          |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+     * |[12]    |CAPINV4   |Capture Inverter Enable Bits
+     * |        |          |0 = Capture source inverter Disabled.
+     * |        |          |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+     * |[13]    |CAPINV5   |Capture Inverter Enable Bits
+     * |        |          |0 = Capture source inverter Disabled.
+     * |        |          |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
+     * |[16]    |RCRLDEN0  |Rising Capture Reload Enable Bits
+     * |        |          |0 = Rising capture reload counter Disabled.
+     * |        |          |1 = Rising capture reload counter Enabled.
+     * |[17]    |RCRLDEN1  |Rising Capture Reload Enable Bits
+     * |        |          |0 = Rising capture reload counter Disabled.
+     * |        |          |1 = Rising capture reload counter Enabled.
+     * |[18]    |RCRLDEN2  |Rising Capture Reload Enable Bits
+     * |        |          |0 = Rising capture reload counter Disabled.
+     * |        |          |1 = Rising capture reload counter Enabled.
+     * |[19]    |RCRLDEN3  |Rising Capture Reload Enable Bits
+     * |        |          |0 = Rising capture reload counter Disabled.
+     * |        |          |1 = Rising capture reload counter Enabled.
+     * |[20]    |RCRLDEN4  |Rising Capture Reload Enable Bits
+     * |        |          |0 = Rising capture reload counter Disabled.
+     * |        |          |1 = Rising capture reload counter Enabled.
+     * |[21]    |RCRLDEN5  |Rising Capture Reload Enable Bits
+     * |        |          |0 = Rising capture reload counter Disabled.
+     * |        |          |1 = Rising capture reload counter Enabled.
+     * |[24]    |FCRLDEN0  |Falling Capture Reload Enable Bits
+     * |        |          |0 = Falling capture reload counter Disabled.
+     * |        |          |1 = Falling capture reload counter Enabled.
+     * |[25]    |FCRLDEN1  |Falling Capture Reload Enable Bits
+     * |        |          |0 = Falling capture reload counter Disabled.
+     * |        |          |1 = Falling capture reload counter Enabled.
+     * |[26]    |FCRLDEN2  |Falling Capture Reload Enable Bits
+     * |        |          |0 = Falling capture reload counter Disabled.
+     * |        |          |1 = Falling capture reload counter Enabled.
+     * |[27]    |FCRLDEN3  |Falling Capture Reload Enable Bits
+     * |        |          |0 = Falling capture reload counter Disabled.
+     * |        |          |1 = Falling capture reload counter Enabled.
+     * |[28]    |FCRLDEN4  |Falling Capture Reload Enable Bits
+     * |        |          |0 = Falling capture reload counter Disabled.
+     * |        |          |1 = Falling capture reload counter Enabled.
+     * |[29]    |FCRLDEN5  |Falling Capture Reload Enable Bits
+     * |        |          |0 = Falling capture reload counter Disabled.
+     * |        |          |1 = Falling capture reload counter Enabled.
+     * @var EPWM_T::CAPSTS
+     * Offset: 0x208  EPWM Capture Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CRLIFOV0  |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
+     * |[1]     |CRLIFOV1  |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
+     * |[2]     |CRLIFOV2  |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
+     * |[3]     |CRLIFOV3  |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
+     * |[4]     |CRLIFOV4  |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
+     * |[5]     |CRLIFOV5  |Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if rising latch happened when the corresponding CRLIF is 1.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
+     * |[8]     |CFLIFOV0  |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
+     * |[9]     |CFLIFOV1  |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
+     * |[10]    |CFLIFOV2  |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
+     * |[11]    |CFLIFOV3  |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
+     * |[12]    |CFLIFOV4  |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
+     * |[13]    |CFLIFOV5  |Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
+     * |        |          |This flag indicates if falling latch happened when the corresponding CFLIF is 1.
+     * |        |          |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
+     * @var EPWM_T::PDMACTL
+     * Offset: 0x23C  EPWM PDMA Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CHEN0_1   |Channel 0/1 PDMA Enable
+     * |        |          |0 = Channel 0/1 PDMA function Disabled.
+     * |        |          |1 = Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory.
+     * |[2:1]   |CAPMOD0_1 |Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer
+     * |        |          |00 = Reserved.
+     * |        |          |01 = EPWM_RCAPDAT0/1 register.
+     * |        |          |10 = EPWM_FCAPDAT0/1 register.
+     * |        |          |11 = Both EPWM_RCAPDAT0/1 and EPWM_FCAPDAT0/1 registers.
+     * |[3]     |CAPORD0_1 |Capture Channel 0/1 Rising/Falling Order
+     * |        |          |Set this bit to determine whether the EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 register is the first captured data transferred to memory through PDMA when CAPMOD0_1 bits are set to = 0x3.
+     * |        |          |0 = EPWM_FCAPDAT0/1 register is the first captured data to memory.
+     * |        |          |1 = EPWM_RCAPDAT0/1 register is the first captured data to memory.
+     * |[4]     |CHSEL0_1  |Select Channel 0/1 to Do PDMA Transfer
+     * |        |          |0 = Channel0.
+     * |        |          |1 = Channel1.
+     * |[8]     |CHEN2_3   |Channel 2/3 PDMA Enable
+     * |        |          |0 = Channel 2/3 PDMA function Disabled.
+     * |        |          |1 = Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory.
+     * |[10:9]  |CAPMOD2_3 |Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer
+     * |        |          |00 = Reserved.
+     * |        |          |01 = EPWM_RCAPDAT2/3 register.
+     * |        |          |10 = EPWM_FCAPDAT2/3 register.
+     * |        |          |11 = Both EPWM_RCAPDAT2/3 and EPWM_FCAPDAT2/3 registers.
+     * |[11]    |CAPORD2_3 |Capture Channel 2/3 Rising/Falling Order
+     * |        |          |Set this bit to determine whether the EPWM_RCAPDAT2/3 or EPWM_FCAPDAT2/3 register is the first captured data transferred to memory through PDMA when CAPMOD2_3 bits are set to =0x3.
+     * |        |          |0 = EPWM_FCAPDAT2/3 register is the first captured data to memory.
+     * |        |          |1 = EPWM_RCAPDAT2/3 register is the first captured data to memory.
+     * |[12]    |CHSEL2_3  |Select Channel 2/3 to Do PDMA Transfer
+     * |        |          |0 = Channel2.
+     * |        |          |1 = Channel3.
+     * |[16]    |CHEN4_5   |Channel 4/5 PDMA Enable
+     * |        |          |0 = Channel 4/5 PDMA function Disabled.
+     * |        |          |1 = Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory.
+     * |[18:17] |CAPMOD4_5 |Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer
+     * |        |          |00 = Reserved.
+     * |        |          |01 = EPWM_RCAPDAT4/5 register.
+     * |        |          |10 = EPWM_FCAPDAT4/5 register.
+     * |        |          |11 = Both EPWM_RCAPDAT4/5 and EPWM_FCAPDAT4/5 registers.
+     * |[19]    |CAPORD4_5 |Capture Channel 4/5 Rising/Falling Order
+     * |        |          |Set this bit to determine whether the EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 register is the first captured data transferred to memory through PDMA when CAPMOD4_5 bits =are set to 0x3.
+     * |        |          |0 = EPWM_FCAPDAT4/5 register is the first captured data to memory.
+     * |        |          |1 = EPWM_RCAPDAT4/5 register is the first captured data to memory.
+     * |[20]    |CHSEL4_5  |Select Channel 4/5 to Do PDMA Transfer
+     * |        |          |0 = Channel4.
+     * |        |          |1 = Channel5.
+     * @var EPWM_T::PDMACAP[3]
+     * Offset: 0x240  EPWM Capture Channel 01 PDMA Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |CAPBUF    |EPWM Capture PDMA Register (Read Only)
+     * |        |          |This register is use as a buffer to transfer EPWM capture rising or falling data to memory by PDMA.
+     * @var EPWM_T::CAPIEN
+     * Offset: 0x250  EPWM Capture Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CAPRIEN0  |EPWM Capture Rising Latch Interrupt Enable Bits
+     * |        |          |0 = Capture rising edge latch interrupt Disabled.
+     * |        |          |1 = Capture rising edge latch interrupt Enabled.
+     * |        |          |Note: When Capture with PDMA operating, corresponding channel CAPRIEN0 bit must be disabled.
+     * |[1]     |CAPRIEN1  |EPWM Capture Rising Latch Interrupt Enable Bits
+     * |        |          |0 = Capture rising edge latch interrupt Disabled.
+     * |        |          |1 = Capture rising edge latch interrupt Enabled.
+     * |        |          |Note: When Capture with PDMA operating, corresponding channel CAPRIEN1 bit must be disabled.
+     * |[2]     |CAPRIEN2  |EPWM Capture Rising Latch Interrupt Enable Bits
+     * |        |          |0 = Capture rising edge latch interrupt Disabled.
+     * |        |          |1 = Capture rising edge latch interrupt Enabled.
+     * |        |          |Note: When Capture with PDMA operating, corresponding channel CAPRIEN2 bit must be disabled.
+     * |[3]     |CAPRIEN3  |EPWM Capture Rising Latch Interrupt Enable Bits
+     * |        |          |0 = Capture rising edge latch interrupt Disabled.
+     * |        |          |1 = Capture rising edge latch interrupt Enabled.
+     * |        |          |Note: When Capture with PDMA operating, corresponding channel CAPRIEN3 bit must be disabled.
+     * |[4]     |CAPRIEN4  |EPWM Capture Rising Latch Interrupt Enable Bits
+     * |        |          |0 = Capture rising edge latch interrupt Disabled.
+     * |        |          |1 = Capture rising edge latch interrupt Enabled.
+     * |        |          |Note: When Capture with PDMA operating, corresponding channel CAPRIEN4 bit must be disabled.
+     * |[5]     |CAPRIEN5  |EPWM Capture Rising Latch Interrupt Enable Bits
+     * |        |          |0 = Capture rising edge latch interrupt Disabled.
+     * |        |          |1 = Capture rising edge latch interrupt Enabled.
+     * |        |          |Note: When Capture with PDMA operating, corresponding channel CAPRIEN5 bit must be disabled.
+     * |[8]     |CAPFIEN0  |EPWM Capture Falling Latch Interrupt Enable Bits
+     * |        |          |0 = Capture falling edge latch interrupt Disabled.
+     * |        |          |1 = Capture falling edge latch interrupt Enabled.
+     * |        |          |Note: When Capture with PDMA operating, corresponding channel CAPFIEN0 bit must be disabled.
+     * |[9]     |CAPFIEN1  |EPWM Capture Falling Latch Interrupt Enable Bits
+     * |        |          |0 = Capture falling edge latch interrupt Disabled.
+     * |        |          |1 = Capture falling edge latch interrupt Enabled.
+     * |        |          |Note: When Capture with PDMA operating, corresponding channel CAPFIEN1 bit must be disabled.
+     * |[10]    |CAPFIEN2  |EPWM Capture Falling Latch Interrupt Enable Bits
+     * |        |          |0 = Capture falling edge latch interrupt Disabled.
+     * |        |          |1 = Capture falling edge latch interrupt Enabled.
+     * |        |          |Note: When Capture with PDMA operating, corresponding channel CAPFIEN2 bit must be disabled.
+     * |[11]    |CAPFIEN3  |EPWM Capture Falling Latch Interrupt Enable Bits
+     * |        |          |0 = Capture falling edge latch interrupt Disabled.
+     * |        |          |1 = Capture falling edge latch interrupt Enabled.
+     * |        |          |Note: When Capture with PDMA operating, corresponding channel CAPFIEN3 bit must be disabled.
+     * |[12]    |CAPFIEN4  |EPWM Capture Falling Latch Interrupt Enable Bits
+     * |        |          |0 = Capture falling edge latch interrupt Disabled.
+     * |        |          |1 = Capture falling edge latch interrupt Enabled.
+     * |        |          |Note: When Capture with PDMA operating, corresponding channel CAPFIEN4 bit must be disabled.
+     * |[13]    |CAPFIEN5  |EPWM Capture Falling Latch Interrupt Enable Bits
+     * |        |          |0 = Capture falling edge latch interrupt Disabled.
+     * |        |          |1 = Capture falling edge latch interrupt Enabled.
+     * |        |          |Note: When Capture with PDMA operating, corresponding channel CAPFIEN5 bit must be disabled.
+     * @var EPWM_T::CAPIF
+     * Offset: 0x254  EPWM Capture Interrupt Flag Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CRLIF0    |EPWM Capture Rising Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear.
+     * |        |          |0 = No capture rising latch condition happened.
+     * |        |          |1 = Capture rising latch condition happened, this flag will be set to high.
+     * |        |          |Note: When Capture with PDMA operating, corresponding channel CRLIF0 bit will cleared by hardware after PDMA transfer data.
+     * |[1]     |CRLIF1    |EPWM Capture Rising Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear.
+     * |        |          |0 = No capture rising latch condition happened.
+     * |        |          |1 = Capture rising latch condition happened, this flag will be set to high.
+     * |        |          |Note: When Capture with PDMA operating, corresponding channel CRLIF1 bit will cleared by hardware after PDMA transfer data.
+     * |[2]     |CRLIF2    |EPWM Capture Rising Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear.
+     * |        |          |0 = No capture rising latch condition happened.
+     * |        |          |1 = Capture rising latch condition happened, this flag will be set to high.
+     * |        |          |Note: When Capture with PDMA operating, corresponding channel CRLIF2 bit will cleared by hardware after PDMA transfer data.
+     * |[3]     |CRLIF3    |EPWM Capture Rising Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear.
+     * |        |          |0 = No capture rising latch condition happened.
+     * |        |          |1 = Capture rising latch condition happened, this flag will be set to high.
+     * |        |          |Note: When Capture with PDMA operating, corresponding channel CRLIF3 bit will cleared by hardware after PDMA transfer data.
+     * |[4]     |CRLIF4    |EPWM Capture Rising Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear.
+     * |        |          |0 = No capture rising latch condition happened.
+     * |        |          |1 = Capture rising latch condition happened, this flag will be set to high.
+     * |        |          |Note: When Capture with PDMA operating, corresponding channel CRLIF4 bit will cleared by hardware after PDMA transfer data.
+     * |[5]     |CRLIF5    |EPWM Capture Rising Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear.
+     * |        |          |0 = No capture rising latch condition happened.
+     * |        |          |1 = Capture rising latch condition happened, this flag will be set to high.
+     * |        |          |Note: When Capture with PDMA operating, corresponding channel CRLIF5 bit will cleared by hardware after PDMA transfer data.
+     * |[8]     |CFLIF0    |EPWM Capture Falling Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear.
+     * |        |          |0 = No capture falling latch condition happened.
+     * |        |          |1 = Capture falling latch condition happened, this flag will be set to high.
+     * |        |          |Note: When Capture with PDMA operating, corresponding channel CFLIF0 bit will cleared by hardware after PDMA transfer data.
+     * |[9]     |CFLIF1    |EPWM Capture Falling Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear.
+     * |        |          |0 = No capture falling latch condition happened.
+     * |        |          |1 = Capture falling latch condition happened, this flag will be set to high.
+     * |        |          |Note: When Capture with PDMA operating, corresponding channel CFLIF1 bit will cleared by hardware after PDMA transfer data.
+     * |[10]    |CFLIF2    |EPWM Capture Falling Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear.
+     * |        |          |0 = No capture falling latch condition happened.
+     * |        |          |1 = Capture falling latch condition happened, this flag will be set to high.
+     * |        |          |Note: When Capture with PDMA operating, corresponding channel CFLIF2 bit will cleared by hardware after PDMA transfer data.
+     * |[11]    |CFLIF3    |EPWM Capture Falling Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear.
+     * |        |          |0 = No capture falling latch condition happened.
+     * |        |          |1 = Capture falling latch condition happened, this flag will be set to high.
+     * |        |          |Note: When Capture with PDMA operating, corresponding channel CFLIF3 bit will cleared by hardware after PDMA transfer data.
+     * |[12]    |CFLIF4    |EPWM Capture Falling Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear.
+     * |        |          |0 = No capture falling latch condition happened.
+     * |        |          |1 = Capture falling latch condition happened, this flag will be set to high.
+     * |        |          |Note: When Capture with PDMA operating, corresponding channel CFLIF4 bit will cleared by hardware after PDMA transfer data.
+     * |[13]    |CFLIF5    |EPWM Capture Falling Latch Interrupt Flag
+     * |        |          |This bit is writing 1 to clear.
+     * |        |          |0 = No capture falling latch condition happened.
+     * |        |          |1 = Capture falling latch condition happened, this flag will be set to high.
+     * |        |          |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
+     * @var EPWM_T::PBUF[6]
+     * Offset: 0x304  EPWM PERIOD0~5 Buffer
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |PBUF      |EPWM Period Register Buffer (Read Only)
+     * |        |          |Used as PERIOD active register.
+     * @var EPWM_T::CMPBUF[6]
+     * Offset: 0x31C  EPWM CMPDAT0~5 Buffer
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |CMPBUF    |EPWM Comparator Register Buffer (Read Only)
+     * |        |          |Used as CMP active register.
+     * @var EPWM_T::CPSCBUF[3]
+     * Offset: 0x334  EPWM CLKPSC0_1/2_3/4_5 Buffer
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[11:0]  |CPSCBUF   |EPWM Counter Clock Prescale Buffer
+     * |        |          |Use as EPWM counter clock prescale active register.
+     * @var EPWM_T::FTCBUF[3]
+     * Offset: 0x340  EPWM FTCMPDAT0_1/2_3/4_5 Buffer
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |FTCMPBUF  |EPWM FTCMPDAT Buffer (Read Only)
+     * |        |          |Used as FTCMPDAT active register.
+     * @var EPWM_T::FTCI
+     * Offset: 0x34C  EPWM FTCMPDAT Indicator Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |FTCMU0    |EPWM FTCMPDAT Up Indicator
+     * |        |          |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit.
+     * |[1]     |FTCMU2    |EPWM FTCMPDAT Up Indicator
+     * |        |          |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit.
+     * |[2]     |FTCMU4    |EPWM FTCMPDAT Up Indicator
+     * |        |          |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit.
+     * |[8]     |FTCMD0    |EPWM FTCMPDAT Down Indicator
+     * |        |          |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit.
+     * |[9]     |FTCMD2    |EPWM FTCMPDAT Down Indicator
+     * |        |          |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit.
+     * |[10]    |FTCMD4    |EPWM FTCMPDAT Down Indicator
+     * |        |          |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit.
+     */
+    __IO uint32_t CTL0;                  /*!< [0x0000] EPWM Control Register 0                                           */
+    __IO uint32_t CTL1;                  /*!< [0x0004] EPWM Control Register 1                                           */
+    __IO uint32_t SYNC;                  /*!< [0x0008] EPWM Synchronization Register                                     */
+    __IO uint32_t SWSYNC;                /*!< [0x000c] EPWM Software Control Synchronization Register                    */
+    __IO uint32_t CLKSRC;                /*!< [0x0010] EPWM Clock Source Register                                        */
+    __IO uint32_t CLKPSC[3];             /*!< [0x0014~0x001c] EPWM Clock Prescale Register 0_1,2_3,4_5                   */
+    __IO uint32_t CNTEN;                 /*!< [0x0020] EPWM Counter Enable Register                                      */
+    __IO uint32_t CNTCLR;                /*!< [0x0024] EPWM Clear Counter Register                                       */
+    __IO uint32_t LOAD;                  /*!< [0x0028] EPWM Load Register                                                */
+    __I  uint32_t RESERVE0[1];
+    __IO uint32_t PERIOD[6];             /*!< [0x0030~0x0044]  EPWM Period Register 0~5                                  */
+    __I  uint32_t RESERVE1[2];
+    __IO uint32_t CMPDAT[6];             /*!< [0x0050~0x0064]  EPWM Comparator Register 0~5                              */
+    __I  uint32_t RESERVE2[2];
+    __IO uint32_t DTCTL[3];              /*!< [0x0070~0x0078] EPWM Dead-Time Control Register 0_1,2_3,4_5                */
+    __I  uint32_t RESERVE3[1];
+    __IO uint32_t PHS[3];                /*!< [0x0080~0x0088] EPWM Counter Phase Register 0_1,2_3,4_5                    */
+    __I  uint32_t RESERVE4[1];
+    __I  uint32_t CNT[6];                /*!< [0x0090~0x00A4  EPWM Counter Register 0~5                                  */
+    __I  uint32_t RESERVE5[2];
+    __IO uint32_t WGCTL0;                /*!< [0x00b0] EPWM Generation Register 0                                        */
+    __IO uint32_t WGCTL1;                /*!< [0x00b4] EPWM Generation Register 1                                        */
+    __IO uint32_t MSKEN;                 /*!< [0x00b8] EPWM Mask Enable Register                                         */
+    __IO uint32_t MSK;                   /*!< [0x00bc] EPWM Mask Data Register                                           */
+    __IO uint32_t BNF;                   /*!< [0x00c0] EPWM Brake Noise Filter Register                                  */
+    __IO uint32_t FAILBRK;               /*!< [0x00c4] EPWM System Fail Brake Control Register                           */
+    __IO uint32_t BRKCTL[3];             /*!< [0x00c8~0x00d0] EPWM Brake Edge Detect Control Register 0_1,2_3,4_5        */
+    __IO uint32_t POLCTL;                /*!< [0x00d4] EPWM Pin Polar Inverse Register                                   */
+    __IO uint32_t POEN;                  /*!< [0x00d8] EPWM Output Enable Register                                       */
+    __O  uint32_t SWBRK;                 /*!< [0x00dc] EPWM Software Brake Control Register                              */
+    __IO uint32_t INTEN0;                /*!< [0x00e0] EPWM Interrupt Enable Register 0                                  */
+    __IO uint32_t INTEN1;                /*!< [0x00e4] EPWM Interrupt Enable Register 1                                  */
+    __IO uint32_t INTSTS0;               /*!< [0x00e8] EPWM Interrupt Flag Register 0                                    */
+    __IO uint32_t INTSTS1;               /*!< [0x00ec] EPWM Interrupt Flag Register 1                                    */
+    __I  uint32_t RESERVE6[1];
+    __IO uint32_t DACTRGEN;              /*!< [0x00f4] EPWM Trigger DAC Enable Register                                  */
+    __IO uint32_t EADCTS0;               /*!< [0x00f8] EPWM Trigger EADC Source Select Register 0                        */
+    __IO uint32_t EADCTS1;               /*!< [0x00fc] EPWM Trigger EADC Source Select Register 1                        */
+    __IO uint32_t FTCMPDAT[3];           /*!< [0x0100~0x108] EPWM Free Trigger Compare Register 0_1,2_3,4_5              */
+    __I  uint32_t RESERVE7[1];
+    __IO uint32_t SSCTL;                 /*!< [0x0110] EPWM Synchronous Start Control Register                           */
+    __O  uint32_t SSTRG;                 /*!< [0x0114] EPWM Synchronous Start Trigger Register                           */
+    __IO uint32_t LEBCTL;                /*!< [0x0118] EPWM Leading Edge Blanking Control Register                       */
+    __IO uint32_t LEBCNT;                /*!< [0x011c] EPWM Leading Edge Blanking Counter Register                       */
+    __IO uint32_t STATUS;                /*!< [0x0120] EPWM Status Register                                              */
+    __I  uint32_t RESERVE8[3];
+    __IO uint32_t IFA[6];                /*!< [0x0130~0x144] EPWM Interrupt Flag Accumulator Register 0~5                */
+    __I  uint32_t RESERVE9[2];
+    __IO uint32_t AINTSTS;               /*!< [0x0150] EPWM Accumulator Interrupt Flag Register                          */
+    __IO uint32_t AINTEN;                /*!< [0x0154] EPWM Accumulator Interrupt Enable Register                        */
+    __IO uint32_t APDMACTL;              /*!< [0x0158] EPWM Accumulator PDMA Control Register                            */
+    __I  uint32_t RESERVE10[1];
+    __IO uint32_t FDEN;                  /*!< [0x0160] EPWM Fault Detect Enable Register                                 */
+    __IO uint32_t FDCTL[6];              /*!< [0x0164~0x178] EPWM Fault Detect Control Register 0~5                      */
+    __IO uint32_t FDIEN;                 /*!< [0x017C] EPWM Fault Detect Interrupt Enable Register                       */
+    __IO uint32_t FDSTS;                 /*!< [0x0180] EPWM Fault Detect Interrupt Flag Register                         */
+    __IO uint32_t EADCPSCCTL;            /*!< [0x0184] EPWM Trigger EADC Prescale Control Register                       */
+    __IO uint32_t EADCPSC0;              /*!< [0x0188] EPWM Trigger EADC Prescale Register 0                             */
+    __IO uint32_t EADCPSC1;              /*!< [0x018C] EPWM Trigger EADC Prescale Register 1                             */
+    __IO uint32_t EADCPSCNT0;            /*!< [0x0190] EPWM Trigger EADC Prescale Counter Register 0                     */
+    __IO uint32_t EADCPSCNT1;            /*!< [0x0194] EPWM Trigger EADC Prescale Counter Register 1                     */
+    __I  uint32_t RESERVE11[26];
+    __IO uint32_t CAPINEN;               /*!< [0x0200] EPWM Capture Input Enable Register                                */
+    __IO uint32_t CAPCTL;                /*!< [0x0204] EPWM Capture Control Register                                     */
+    __I  uint32_t CAPSTS;                /*!< [0x0208] EPWM Capture Status Register                                      */
+    ECAPDAT_T CAPDAT[6];                  /*!< [0x020c~0x0238] EPWM Rising and Falling Capture Data Register 0~5         */
+    __IO uint32_t PDMACTL;               /*!< [0x023c] EPWM PDMA Control Register                                        */
+    __I  uint32_t PDMACAP[3];            /*!< [0x0240~0x248] EPWM Capture Channel 0_1,2_3,4_5 PDMA Register              */
+    __I  uint32_t RESERVE12[1];
+    __IO uint32_t CAPIEN;                /*!< [0x0250] EPWM Capture Interrupt Enable Register                            */
+    __IO uint32_t CAPIF;                 /*!< [0x0254] EPWM Capture Interrupt Flag Register                              */
+    __I  uint32_t RESERVE13[43];
+    __I  uint32_t PBUF[6];               /*!< [0x0304~0x0318  EPWM PERIOD0~5 Buffer                                      */
+    __I  uint32_t CMPBUF[6];             /*!< [0x031C~0x0330  EPWM CMPDAT0~5 Buffer                                      */
+    __I  uint32_t CPSCBUF[3];            /*!< [0x0334~0x33c] EPWM CLKPSC0_1,2_3,4_5 Buffer                               */
+    __I  uint32_t FTCBUF[3];             /*!< [0x0340~0x348] EPWM FTCMPDAT0_1,2_3,4_5 Buffer                             */
+    __IO uint32_t FTCI;                  /*!< [0x034c] EPWM FTCMPDAT Indicator Register                                  */
+
+} EPWM_T;
+
+/**
+  @addtogroup EPWM_CONST EPWM Bit Field Definition
+  Constant Definitions for EPWM Controller
+  @{
+*/
+
+#define EPWM_CTL0_CTRLD0_Pos              (0)                                               /*!< EPWM_T::CTL0: CTRLD0 Position           */
+#define EPWM_CTL0_CTRLD0_Msk              (0x1ul << EPWM_CTL0_CTRLD0_Pos)                   /*!< EPWM_T::CTL0: CTRLD0 Mask               */
+
+#define EPWM_CTL0_CTRLD1_Pos              (1)                                               /*!< EPWM_T::CTL0: CTRLD1 Position           */
+#define EPWM_CTL0_CTRLD1_Msk              (0x1ul << EPWM_CTL0_CTRLD1_Pos)                   /*!< EPWM_T::CTL0: CTRLD1 Mask               */
+
+#define EPWM_CTL0_CTRLD2_Pos              (2)                                               /*!< EPWM_T::CTL0: CTRLD2 Position           */
+#define EPWM_CTL0_CTRLD2_Msk              (0x1ul << EPWM_CTL0_CTRLD2_Pos)                    /*!< EPWM_T::CTL0: CTRLD2 Mask               */
+
+#define EPWM_CTL0_CTRLD3_Pos              (3)                                               /*!< EPWM_T::CTL0: CTRLD3 Position           */
+#define EPWM_CTL0_CTRLD3_Msk              (0x1ul << EPWM_CTL0_CTRLD3_Pos)                    /*!< EPWM_T::CTL0: CTRLD3 Mask               */
+
+#define EPWM_CTL0_CTRLD4_Pos              (4)                                               /*!< EPWM_T::CTL0: CTRLD4 Position           */
+#define EPWM_CTL0_CTRLD4_Msk              (0x1ul << EPWM_CTL0_CTRLD4_Pos)                    /*!< EPWM_T::CTL0: CTRLD4 Mask               */
+
+#define EPWM_CTL0_CTRLD5_Pos              (5)                                               /*!< EPWM_T::CTL0: CTRLD5 Position           */
+#define EPWM_CTL0_CTRLD5_Msk              (0x1ul << EPWM_CTL0_CTRLD5_Pos)                    /*!< EPWM_T::CTL0: CTRLD5 Mask               */
+
+#define EPWM_CTL0_WINLDEN0_Pos            (8)                                               /*!< EPWM_T::CTL0: WINLDEN0 Position         */
+#define EPWM_CTL0_WINLDEN0_Msk            (0x1ul << EPWM_CTL0_WINLDEN0_Pos)                  /*!< EPWM_T::CTL0: WINLDEN0 Mask             */
+
+#define EPWM_CTL0_WINLDEN1_Pos            (9)                                               /*!< EPWM_T::CTL0: WINLDEN1 Position         */
+#define EPWM_CTL0_WINLDEN1_Msk            (0x1ul << EPWM_CTL0_WINLDEN1_Pos)                  /*!< EPWM_T::CTL0: WINLDEN1 Mask             */
+
+#define EPWM_CTL0_WINLDEN2_Pos            (10)                                              /*!< EPWM_T::CTL0: WINLDEN2 Position         */
+#define EPWM_CTL0_WINLDEN2_Msk            (0x1ul << EPWM_CTL0_WINLDEN2_Pos)                  /*!< EPWM_T::CTL0: WINLDEN2 Mask             */
+
+#define EPWM_CTL0_WINLDEN3_Pos            (11)                                              /*!< EPWM_T::CTL0: WINLDEN3 Position         */
+#define EPWM_CTL0_WINLDEN3_Msk            (0x1ul << EPWM_CTL0_WINLDEN3_Pos)                  /*!< EPWM_T::CTL0: WINLDEN3 Mask             */
+
+#define EPWM_CTL0_WINLDEN4_Pos            (12)                                              /*!< EPWM_T::CTL0: WINLDEN4 Position         */
+#define EPWM_CTL0_WINLDEN4_Msk            (0x1ul << EPWM_CTL0_WINLDEN4_Pos)                  /*!< EPWM_T::CTL0: WINLDEN4 Mask             */
+
+#define EPWM_CTL0_WINLDEN5_Pos            (13)                                              /*!< EPWM_T::CTL0: WINLDEN5 Position         */
+#define EPWM_CTL0_WINLDEN5_Msk            (0x1ul << EPWM_CTL0_WINLDEN5_Pos)                  /*!< EPWM_T::CTL0: WINLDEN5 Mask             */
+
+#define EPWM_CTL0_IMMLDEN0_Pos            (16)                                              /*!< EPWM_T::CTL0: IMMLDEN0 Position         */
+#define EPWM_CTL0_IMMLDEN0_Msk            (0x1ul << EPWM_CTL0_IMMLDEN0_Pos)                  /*!< EPWM_T::CTL0: IMMLDEN0 Mask             */
+
+#define EPWM_CTL0_IMMLDEN1_Pos            (17)                                              /*!< EPWM_T::CTL0: IMMLDEN1 Position         */
+#define EPWM_CTL0_IMMLDEN1_Msk            (0x1ul << EPWM_CTL0_IMMLDEN1_Pos)                  /*!< EPWM_T::CTL0: IMMLDEN1 Mask             */
+
+#define EPWM_CTL0_IMMLDEN2_Pos            (18)                                              /*!< EPWM_T::CTL0: IMMLDEN2 Position         */
+#define EPWM_CTL0_IMMLDEN2_Msk            (0x1ul << EPWM_CTL0_IMMLDEN2_Pos)                  /*!< EPWM_T::CTL0: IMMLDEN2 Mask             */
+
+#define EPWM_CTL0_IMMLDEN3_Pos            (19)                                              /*!< EPWM_T::CTL0: IMMLDEN3 Position         */
+#define EPWM_CTL0_IMMLDEN3_Msk            (0x1ul << EPWM_CTL0_IMMLDEN3_Pos)                  /*!< EPWM_T::CTL0: IMMLDEN3 Mask             */
+
+#define EPWM_CTL0_IMMLDEN4_Pos            (20)                                              /*!< EPWM_T::CTL0: IMMLDEN4 Position         */
+#define EPWM_CTL0_IMMLDEN4_Msk            (0x1ul << EPWM_CTL0_IMMLDEN4_Pos)                  /*!< EPWM_T::CTL0: IMMLDEN4 Mask             */
+
+#define EPWM_CTL0_IMMLDEN5_Pos            (21)                                              /*!< EPWM_T::CTL0: IMMLDEN5 Position         */
+#define EPWM_CTL0_IMMLDEN5_Msk            (0x1ul << EPWM_CTL0_IMMLDEN5_Pos)                  /*!< EPWM_T::CTL0: IMMLDEN5 Mask             */
+
+#define EPWM_CTL0_GROUPEN_Pos             (24)                                              /*!< EPWM_T::CTL0: GROUPEN Position          */
+#define EPWM_CTL0_GROUPEN_Msk             (0x1ul << EPWM_CTL0_GROUPEN_Pos)                   /*!< EPWM_T::CTL0: GROUPEN Mask              */
+
+#define EPWM_CTL0_DBGHALT_Pos             (30)                                              /*!< EPWM_T::CTL0: DBGHALT Position          */
+#define EPWM_CTL0_DBGHALT_Msk             (0x1ul << EPWM_CTL0_DBGHALT_Pos)                   /*!< EPWM_T::CTL0: DBGHALT Mask              */
+
+#define EPWM_CTL0_DBGTRIOFF_Pos           (31)                                              /*!< EPWM_T::CTL0: DBGTRIOFF Position        */
+#define EPWM_CTL0_DBGTRIOFF_Msk           (0x1ul << EPWM_CTL0_DBGTRIOFF_Pos)                 /*!< EPWM_T::CTL0: DBGTRIOFF Mask            */
+
+#define EPWM_CTL1_CNTTYPE0_Pos            (0)                                               /*!< EPWM_T::CTL1: CNTTYPE0 Position         */
+#define EPWM_CTL1_CNTTYPE0_Msk            (0x3ul << EPWM_CTL1_CNTTYPE0_Pos)                  /*!< EPWM_T::CTL1: CNTTYPE0 Mask             */
+
+#define EPWM_CTL1_CNTTYPE1_Pos            (2)                                               /*!< EPWM_T::CTL1: CNTTYPE1 Position         */
+#define EPWM_CTL1_CNTTYPE1_Msk            (0x3ul << EPWM_CTL1_CNTTYPE1_Pos)                  /*!< EPWM_T::CTL1: CNTTYPE1 Mask             */
+
+#define EPWM_CTL1_CNTTYPE2_Pos            (4)                                               /*!< EPWM_T::CTL1: CNTTYPE2 Position         */
+#define EPWM_CTL1_CNTTYPE2_Msk            (0x3ul << EPWM_CTL1_CNTTYPE2_Pos)                  /*!< EPWM_T::CTL1: CNTTYPE2 Mask             */
+
+#define EPWM_CTL1_CNTTYPE3_Pos            (6)                                               /*!< EPWM_T::CTL1: CNTTYPE3 Position         */
+#define EPWM_CTL1_CNTTYPE3_Msk            (0x3ul << EPWM_CTL1_CNTTYPE3_Pos)                  /*!< EPWM_T::CTL1: CNTTYPE3 Mask             */
+
+#define EPWM_CTL1_CNTTYPE4_Pos            (8)                                               /*!< EPWM_T::CTL1: CNTTYPE4 Position         */
+#define EPWM_CTL1_CNTTYPE4_Msk            (0x3ul << EPWM_CTL1_CNTTYPE4_Pos)                  /*!< EPWM_T::CTL1: CNTTYPE4 Mask             */
+
+#define EPWM_CTL1_CNTTYPE5_Pos            (10)                                              /*!< EPWM_T::CTL1: CNTTYPE5 Position         */
+#define EPWM_CTL1_CNTTYPE5_Msk            (0x3ul << EPWM_CTL1_CNTTYPE5_Pos)                  /*!< EPWM_T::CTL1: CNTTYPE5 Mask             */
+
+#define EPWM_CTL1_CNTMODE0_Pos            (16)                                              /*!< EPWM_T::CTL1: CNTMODE0 Position         */
+#define EPWM_CTL1_CNTMODE0_Msk            (0x1ul << EPWM_CTL1_CNTMODE0_Pos)                  /*!< EPWM_T::CTL1: CNTMODE0 Mask             */
+
+#define EPWM_CTL1_CNTMODE1_Pos            (17)                                              /*!< EPWM_T::CTL1: CNTMODE1 Position         */
+#define EPWM_CTL1_CNTMODE1_Msk            (0x1ul << EPWM_CTL1_CNTMODE1_Pos)                  /*!< EPWM_T::CTL1: CNTMODE1 Mask             */
+
+#define EPWM_CTL1_CNTMODE2_Pos            (18)                                              /*!< EPWM_T::CTL1: CNTMODE2 Position         */
+#define EPWM_CTL1_CNTMODE2_Msk            (0x1ul << EPWM_CTL1_CNTMODE2_Pos)                  /*!< EPWM_T::CTL1: CNTMODE2 Mask             */
+
+#define EPWM_CTL1_CNTMODE3_Pos            (19)                                              /*!< EPWM_T::CTL1: CNTMODE3 Position         */
+#define EPWM_CTL1_CNTMODE3_Msk            (0x1ul << EPWM_CTL1_CNTMODE3_Pos)                  /*!< EPWM_T::CTL1: CNTMODE3 Mask             */
+
+#define EPWM_CTL1_CNTMODE4_Pos            (20)                                              /*!< EPWM_T::CTL1: CNTMODE4 Position         */
+#define EPWM_CTL1_CNTMODE4_Msk            (0x1ul << EPWM_CTL1_CNTMODE4_Pos)                  /*!< EPWM_T::CTL1: CNTMODE4 Mask             */
+
+#define EPWM_CTL1_CNTMODE5_Pos            (21)                                              /*!< EPWM_T::CTL1: CNTMODE5 Position         */
+#define EPWM_CTL1_CNTMODE5_Msk            (0x1ul << EPWM_CTL1_CNTMODE5_Pos)                  /*!< EPWM_T::CTL1: CNTMODE5 Mask             */
+
+#define EPWM_CTL1_OUTMODE0_Pos            (24)                                              /*!< EPWM_T::CTL1: OUTMODE0 Position         */
+#define EPWM_CTL1_OUTMODE0_Msk            (0x1ul << EPWM_CTL1_OUTMODE0_Pos)                  /*!< EPWM_T::CTL1: OUTMODE0 Mask             */
+
+#define EPWM_CTL1_OUTMODE2_Pos            (25)                                              /*!< EPWM_T::CTL1: OUTMODE2 Position         */
+#define EPWM_CTL1_OUTMODE2_Msk            (0x1ul << EPWM_CTL1_OUTMODE2_Pos)                  /*!< EPWM_T::CTL1: OUTMODE2 Mask             */
+
+#define EPWM_CTL1_OUTMODE4_Pos            (26)                                              /*!< EPWM_T::CTL1: OUTMODE4 Position         */
+#define EPWM_CTL1_OUTMODE4_Msk            (0x1ul << EPWM_CTL1_OUTMODE4_Pos)                  /*!< EPWM_T::CTL1: OUTMODE4 Mask             */
+
+#define EPWM_SYNC_PHSEN0_Pos              (0)                                               /*!< EPWM_T::SYNC: PHSEN0 Position           */
+#define EPWM_SYNC_PHSEN0_Msk              (0x1ul << EPWM_SYNC_PHSEN0_Pos)                    /*!< EPWM_T::SYNC: PHSEN0 Mask               */
+
+#define EPWM_SYNC_PHSEN2_Pos              (1)                                               /*!< EPWM_T::SYNC: PHSEN2 Position           */
+#define EPWM_SYNC_PHSEN2_Msk              (0x1ul << EPWM_SYNC_PHSEN2_Pos)                    /*!< EPWM_T::SYNC: PHSEN2 Mask               */
+
+#define EPWM_SYNC_PHSEN4_Pos              (2)                                               /*!< EPWM_T::SYNC: PHSEN4 Position           */
+#define EPWM_SYNC_PHSEN4_Msk              (0x1ul << EPWM_SYNC_PHSEN4_Pos)                    /*!< EPWM_T::SYNC: PHSEN4 Mask               */
+
+#define EPWM_SYNC_SINSRC0_Pos             (8)                                               /*!< EPWM_T::SYNC: SINSRC0 Position          */
+#define EPWM_SYNC_SINSRC0_Msk             (0x3ul << EPWM_SYNC_SINSRC0_Pos)                   /*!< EPWM_T::SYNC: SINSRC0 Mask              */
+
+#define EPWM_SYNC_SINSRC2_Pos             (10)                                              /*!< EPWM_T::SYNC: SINSRC2 Position          */
+#define EPWM_SYNC_SINSRC2_Msk             (0x3ul << EPWM_SYNC_SINSRC2_Pos)                   /*!< EPWM_T::SYNC: SINSRC2 Mask              */
+
+#define EPWM_SYNC_SINSRC4_Pos             (12)                                              /*!< EPWM_T::SYNC: SINSRC4 Position          */
+#define EPWM_SYNC_SINSRC4_Msk             (0x3ul << EPWM_SYNC_SINSRC4_Pos)                   /*!< EPWM_T::SYNC: SINSRC4 Mask              */
+
+#define EPWM_SYNC_SNFLTEN_Pos             (16)                                              /*!< EPWM_T::SYNC: SNFLTEN Position          */
+#define EPWM_SYNC_SNFLTEN_Msk             (0x1ul << EPWM_SYNC_SNFLTEN_Pos)                   /*!< EPWM_T::SYNC: SNFLTEN Mask              */
+
+#define EPWM_SYNC_SFLTCSEL_Pos            (17)                                              /*!< EPWM_T::SYNC: SFLTCSEL Position         */
+#define EPWM_SYNC_SFLTCSEL_Msk            (0x7ul << EPWM_SYNC_SFLTCSEL_Pos)                  /*!< EPWM_T::SYNC: SFLTCSEL Mask             */
+
+#define EPWM_SYNC_SFLTCNT_Pos             (20)                                              /*!< EPWM_T::SYNC: SFLTCNT Position          */
+#define EPWM_SYNC_SFLTCNT_Msk             (0x7ul << EPWM_SYNC_SFLTCNT_Pos)                   /*!< EPWM_T::SYNC: SFLTCNT Mask              */
+
+#define EPWM_SYNC_SINPINV_Pos             (23)                                              /*!< EPWM_T::SYNC: SINPINV Position          */
+#define EPWM_SYNC_SINPINV_Msk             (0x1ul << EPWM_SYNC_SINPINV_Pos)                   /*!< EPWM_T::SYNC: SINPINV Mask              */
+
+#define EPWM_SYNC_PHSDIR0_Pos             (24)                                              /*!< EPWM_T::SYNC: PHSDIR0 Position          */
+#define EPWM_SYNC_PHSDIR0_Msk             (0x1ul << EPWM_SYNC_PHSDIR0_Pos)                   /*!< EPWM_T::SYNC: PHSDIR0 Mask              */
+
+#define EPWM_SYNC_PHSDIR2_Pos             (25)                                              /*!< EPWM_T::SYNC: PHSDIR2 Position          */
+#define EPWM_SYNC_PHSDIR2_Msk             (0x1ul << EPWM_SYNC_PHSDIR2_Pos)                   /*!< EPWM_T::SYNC: PHSDIR2 Mask              */
+
+#define EPWM_SYNC_PHSDIR4_Pos             (26)                                              /*!< EPWM_T::SYNC: PHSDIR4 Position          */
+#define EPWM_SYNC_PHSDIR4_Msk             (0x1ul << EPWM_SYNC_PHSDIR4_Pos)                   /*!< EPWM_T::SYNC: PHSDIR4 Mask              */
+
+#define EPWM_SWSYNC_SWSYNC0_Pos           (0)                                               /*!< EPWM_T::SWSYNC: SWSYNC0 Position        */
+#define EPWM_SWSYNC_SWSYNC0_Msk           (0x1ul << EPWM_SWSYNC_SWSYNC0_Pos)                 /*!< EPWM_T::SWSYNC: SWSYNC0 Mask            */
+
+#define EPWM_SWSYNC_SWSYNC2_Pos           (1)                                               /*!< EPWM_T::SWSYNC: SWSYNC2 Position        */
+#define EPWM_SWSYNC_SWSYNC2_Msk           (0x1ul << EPWM_SWSYNC_SWSYNC2_Pos)                 /*!< EPWM_T::SWSYNC: SWSYNC2 Mask            */
+
+#define EPWM_SWSYNC_SWSYNC4_Pos           (2)                                               /*!< EPWM_T::SWSYNC: SWSYNC4 Position        */
+#define EPWM_SWSYNC_SWSYNC4_Msk           (0x1ul << EPWM_SWSYNC_SWSYNC4_Pos)                 /*!< EPWM_T::SWSYNC: SWSYNC4 Mask            */
+
+#define EPWM_CLKSRC_ECLKSRC0_Pos          (0)                                               /*!< EPWM_T::CLKSRC: ECLKSRC0 Position       */
+#define EPWM_CLKSRC_ECLKSRC0_Msk          (0x7ul << EPWM_CLKSRC_ECLKSRC0_Pos)                /*!< EPWM_T::CLKSRC: ECLKSRC0 Mask           */
+
+#define EPWM_CLKSRC_ECLKSRC2_Pos          (8)                                               /*!< EPWM_T::CLKSRC: ECLKSRC2 Position       */
+#define EPWM_CLKSRC_ECLKSRC2_Msk          (0x7ul << EPWM_CLKSRC_ECLKSRC2_Pos)                /*!< EPWM_T::CLKSRC: ECLKSRC2 Mask           */
+
+#define EPWM_CLKSRC_ECLKSRC4_Pos          (16)                                              /*!< EPWM_T::CLKSRC: ECLKSRC4 Position       */
+#define EPWM_CLKSRC_ECLKSRC4_Msk          (0x7ul << EPWM_CLKSRC_ECLKSRC4_Pos)                /*!< EPWM_T::CLKSRC: ECLKSRC4 Mask           */
+
+#define EPWM_CLKPSC0_1_CLKPSC_Pos         (0)                                               /*!< EPWM_T::CLKPSC0_1: CLKPSC Position      */
+#define EPWM_CLKPSC0_1_CLKPSC_Msk         (0xffful << EPWM_CLKPSC0_1_CLKPSC_Pos)             /*!< EPWM_T::CLKPSC0_1: CLKPSC Mask          */
+
+#define EPWM_CLKPSC2_3_CLKPSC_Pos         (0)                                               /*!< EPWM_T::CLKPSC2_3: CLKPSC Position      */
+#define EPWM_CLKPSC2_3_CLKPSC_Msk         (0xffful << EPWM_CLKPSC2_3_CLKPSC_Pos)             /*!< EPWM_T::CLKPSC2_3: CLKPSC Mask          */
+
+#define EPWM_CLKPSC4_5_CLKPSC_Pos         (0)                                               /*!< EPWM_T::CLKPSC4_5: CLKPSC Position      */
+#define EPWM_CLKPSC4_5_CLKPSC_Msk         (0xffful << EPWM_CLKPSC4_5_CLKPSC_Pos)             /*!< EPWM_T::CLKPSC4_5: CLKPSC Mask          */
+
+#define EPWM_CNTEN_CNTEN0_Pos             (0)                                               /*!< EPWM_T::CNTEN: CNTEN0 Position          */
+#define EPWM_CNTEN_CNTEN0_Msk             (0x1ul << EPWM_CNTEN_CNTEN0_Pos)                   /*!< EPWM_T::CNTEN: CNTEN0 Mask              */
+
+#define EPWM_CNTEN_CNTEN1_Pos             (1)                                               /*!< EPWM_T::CNTEN: CNTEN1 Position          */
+#define EPWM_CNTEN_CNTEN1_Msk             (0x1ul << EPWM_CNTEN_CNTEN1_Pos)                   /*!< EPWM_T::CNTEN: CNTEN1 Mask              */
+
+#define EPWM_CNTEN_CNTEN2_Pos             (2)                                               /*!< EPWM_T::CNTEN: CNTEN2 Position          */
+#define EPWM_CNTEN_CNTEN2_Msk             (0x1ul << EPWM_CNTEN_CNTEN2_Pos)                   /*!< EPWM_T::CNTEN: CNTEN2 Mask              */
+
+#define EPWM_CNTEN_CNTEN3_Pos             (3)                                               /*!< EPWM_T::CNTEN: CNTEN3 Position          */
+#define EPWM_CNTEN_CNTEN3_Msk             (0x1ul << EPWM_CNTEN_CNTEN3_Pos)                   /*!< EPWM_T::CNTEN: CNTEN3 Mask              */
+
+#define EPWM_CNTEN_CNTEN4_Pos             (4)                                               /*!< EPWM_T::CNTEN: CNTEN4 Position          */
+#define EPWM_CNTEN_CNTEN4_Msk             (0x1ul << EPWM_CNTEN_CNTEN4_Pos)                   /*!< EPWM_T::CNTEN: CNTEN4 Mask              */
+
+#define EPWM_CNTEN_CNTEN5_Pos             (5)                                               /*!< EPWM_T::CNTEN: CNTEN5 Position          */
+#define EPWM_CNTEN_CNTEN5_Msk             (0x1ul << EPWM_CNTEN_CNTEN5_Pos)                   /*!< EPWM_T::CNTEN: CNTEN5 Mask              */
+
+#define EPWM_CNTCLR_CNTCLR0_Pos           (0)                                               /*!< EPWM_T::CNTCLR: CNTCLR0 Position        */
+#define EPWM_CNTCLR_CNTCLR0_Msk           (0x1ul << EPWM_CNTCLR_CNTCLR0_Pos)                 /*!< EPWM_T::CNTCLR: CNTCLR0 Mask            */
+
+#define EPWM_CNTCLR_CNTCLR1_Pos           (1)                                               /*!< EPWM_T::CNTCLR: CNTCLR1 Position        */
+#define EPWM_CNTCLR_CNTCLR1_Msk           (0x1ul << EPWM_CNTCLR_CNTCLR1_Pos)                 /*!< EPWM_T::CNTCLR: CNTCLR1 Mask            */
+
+#define EPWM_CNTCLR_CNTCLR2_Pos           (2)                                               /*!< EPWM_T::CNTCLR: CNTCLR2 Position        */
+#define EPWM_CNTCLR_CNTCLR2_Msk           (0x1ul << EPWM_CNTCLR_CNTCLR2_Pos)                 /*!< EPWM_T::CNTCLR: CNTCLR2 Mask            */
+
+#define EPWM_CNTCLR_CNTCLR3_Pos           (3)                                               /*!< EPWM_T::CNTCLR: CNTCLR3 Position        */
+#define EPWM_CNTCLR_CNTCLR3_Msk           (0x1ul << EPWM_CNTCLR_CNTCLR3_Pos)                 /*!< EPWM_T::CNTCLR: CNTCLR3 Mask            */
+
+#define EPWM_CNTCLR_CNTCLR4_Pos           (4)                                               /*!< EPWM_T::CNTCLR: CNTCLR4 Position        */
+#define EPWM_CNTCLR_CNTCLR4_Msk           (0x1ul << EPWM_CNTCLR_CNTCLR4_Pos)                 /*!< EPWM_T::CNTCLR: CNTCLR4 Mask            */
+
+#define EPWM_CNTCLR_CNTCLR5_Pos           (5)                                               /*!< EPWM_T::CNTCLR: CNTCLR5 Position        */
+#define EPWM_CNTCLR_CNTCLR5_Msk           (0x1ul << EPWM_CNTCLR_CNTCLR5_Pos)                 /*!< EPWM_T::CNTCLR: CNTCLR5 Mask            */
+
+#define EPWM_LOAD_LOAD0_Pos               (0)                                               /*!< EPWM_T::LOAD: LOAD0 Position            */
+#define EPWM_LOAD_LOAD0_Msk               (0x1ul << EPWM_LOAD_LOAD0_Pos)                     /*!< EPWM_T::LOAD: LOAD0 Mask                */
+
+#define EPWM_LOAD_LOAD1_Pos               (1)                                               /*!< EPWM_T::LOAD: LOAD1 Position            */
+#define EPWM_LOAD_LOAD1_Msk               (0x1ul << EPWM_LOAD_LOAD1_Pos)                     /*!< EPWM_T::LOAD: LOAD1 Mask                */
+
+#define EPWM_LOAD_LOAD2_Pos               (2)                                               /*!< EPWM_T::LOAD: LOAD2 Position            */
+#define EPWM_LOAD_LOAD2_Msk               (0x1ul << EPWM_LOAD_LOAD2_Pos)                     /*!< EPWM_T::LOAD: LOAD2 Mask                */
+
+#define EPWM_LOAD_LOAD3_Pos               (3)                                               /*!< EPWM_T::LOAD: LOAD3 Position            */
+#define EPWM_LOAD_LOAD3_Msk               (0x1ul << EPWM_LOAD_LOAD3_Pos)                     /*!< EPWM_T::LOAD: LOAD3 Mask                */
+
+#define EPWM_LOAD_LOAD4_Pos               (4)                                               /*!< EPWM_T::LOAD: LOAD4 Position            */
+#define EPWM_LOAD_LOAD4_Msk               (0x1ul << EPWM_LOAD_LOAD4_Pos)                     /*!< EPWM_T::LOAD: LOAD4 Mask                */
+
+#define EPWM_LOAD_LOAD5_Pos               (5)                                               /*!< EPWM_T::LOAD: LOAD5 Position            */
+#define EPWM_LOAD_LOAD5_Msk               (0x1ul << EPWM_LOAD_LOAD5_Pos)                     /*!< EPWM_T::LOAD: LOAD5 Mask                */
+
+#define EPWM_PERIOD0_PERIOD_Pos           (0)                                               /*!< EPWM_T::PERIOD0: PERIOD Position        */
+#define EPWM_PERIOD0_PERIOD_Msk           (0xfffful << EPWM_PERIOD0_PERIOD_Pos)              /*!< EPWM_T::PERIOD0: PERIOD Mask            */
+
+#define EPWM_PERIOD1_PERIOD_Pos           (0)                                               /*!< EPWM_T::PERIOD1: PERIOD Position        */
+#define EPWM_PERIOD1_PERIOD_Msk           (0xfffful << EPWM_PERIOD1_PERIOD_Pos)              /*!< EPWM_T::PERIOD1: PERIOD Mask            */
+
+#define EPWM_PERIOD2_PERIOD_Pos           (0)                                               /*!< EPWM_T::PERIOD2: PERIOD Position        */
+#define EPWM_PERIOD2_PERIOD_Msk           (0xfffful << EPWM_PERIOD2_PERIOD_Pos)              /*!< EPWM_T::PERIOD2: PERIOD Mask            */
+
+#define EPWM_PERIOD3_PERIOD_Pos           (0)                                               /*!< EPWM_T::PERIOD3: PERIOD Position        */
+#define EPWM_PERIOD3_PERIOD_Msk           (0xfffful << EPWM_PERIOD3_PERIOD_Pos)              /*!< EPWM_T::PERIOD3: PERIOD Mask            */
+
+#define EPWM_PERIOD4_PERIOD_Pos           (0)                                               /*!< EPWM_T::PERIOD4: PERIOD Position        */
+#define EPWM_PERIOD4_PERIOD_Msk           (0xfffful << EPWM_PERIOD4_PERIOD_Pos)              /*!< EPWM_T::PERIOD4: PERIOD Mask            */
+
+#define EPWM_PERIOD5_PERIOD_Pos           (0)                                               /*!< EPWM_T::PERIOD5: PERIOD Position        */
+#define EPWM_PERIOD5_PERIOD_Msk           (0xfffful << EPWM_PERIOD5_PERIOD_Pos)              /*!< EPWM_T::PERIOD5: PERIOD Mask            */
+
+#define EPWM_CMPDAT0_CMP_Pos              (0)                                               /*!< EPWM_T::CMPDAT0: CMP Position           */
+#define EPWM_CMPDAT0_CMP_Msk              (0xfffful << EPWM_CMPDAT0_CMP_Pos)                 /*!< EPWM_T::CMPDAT0: CMP Mask               */
+
+#define EPWM_CMPDAT1_CMP_Pos              (0)                                               /*!< EPWM_T::CMPDAT1: CMP Position           */
+#define EPWM_CMPDAT1_CMP_Msk              (0xfffful << EPWM_CMPDAT1_CMP_Pos)                 /*!< EPWM_T::CMPDAT1: CMP Mask               */
+
+#define EPWM_CMPDAT2_CMP_Pos              (0)                                               /*!< EPWM_T::CMPDAT2: CMP Position           */
+#define EPWM_CMPDAT2_CMP_Msk              (0xfffful << EPWM_CMPDAT2_CMP_Pos)                 /*!< EPWM_T::CMPDAT2: CMP Mask               */
+
+#define EPWM_CMPDAT3_CMP_Pos              (0)                                               /*!< EPWM_T::CMPDAT3: CMP Position           */
+#define EPWM_CMPDAT3_CMP_Msk              (0xfffful << EPWM_CMPDAT3_CMP_Pos)                 /*!< EPWM_T::CMPDAT3: CMP Mask               */
+
+#define EPWM_CMPDAT4_CMP_Pos              (0)                                               /*!< EPWM_T::CMPDAT4: CMP Position           */
+#define EPWM_CMPDAT4_CMP_Msk              (0xfffful << EPWM_CMPDAT4_CMP_Pos)                 /*!< EPWM_T::CMPDAT4: CMP Mask               */
+
+#define EPWM_CMPDAT5_CMP_Pos              (0)                                               /*!< EPWM_T::CMPDAT5: CMP Position           */
+#define EPWM_CMPDAT5_CMP_Msk              (0xfffful << EPWM_CMPDAT5_CMP_Pos)                 /*!< EPWM_T::CMPDAT5: CMP Mask               */
+
+#define EPWM_DTCTL0_1_DTCNT_Pos           (0)                                               /*!< EPWM_T::DTCTL0_1: DTCNT Position        */
+#define EPWM_DTCTL0_1_DTCNT_Msk           (0xffful << EPWM_DTCTL0_1_DTCNT_Pos)               /*!< EPWM_T::DTCTL0_1: DTCNT Mask            */
+
+#define EPWM_DTCTL0_1_DTEN_Pos            (16)                                              /*!< EPWM_T::DTCTL0_1: DTEN Position         */
+#define EPWM_DTCTL0_1_DTEN_Msk            (0x1ul << EPWM_DTCTL0_1_DTEN_Pos)                  /*!< EPWM_T::DTCTL0_1: DTEN Mask             */
+
+#define EPWM_DTCTL0_1_DTCKSEL_Pos         (24)                                              /*!< EPWM_T::DTCTL0_1: DTCKSEL Position      */
+#define EPWM_DTCTL0_1_DTCKSEL_Msk         (0x1ul << EPWM_DTCTL0_1_DTCKSEL_Pos)               /*!< EPWM_T::DTCTL0_1: DTCKSEL Mask          */
+
+#define EPWM_DTCTL2_3_DTCNT_Pos           (0)                                               /*!< EPWM_T::DTCTL2_3: DTCNT Position        */
+#define EPWM_DTCTL2_3_DTCNT_Msk           (0xffful << EPWM_DTCTL2_3_DTCNT_Pos)               /*!< EPWM_T::DTCTL2_3: DTCNT Mask            */
+
+#define EPWM_DTCTL2_3_DTEN_Pos            (16)                                              /*!< EPWM_T::DTCTL2_3: DTEN Position         */
+#define EPWM_DTCTL2_3_DTEN_Msk            (0x1ul << EPWM_DTCTL2_3_DTEN_Pos)                  /*!< EPWM_T::DTCTL2_3: DTEN Mask             */
+
+#define EPWM_DTCTL2_3_DTCKSEL_Pos         (24)                                              /*!< EPWM_T::DTCTL2_3: DTCKSEL Position      */
+#define EPWM_DTCTL2_3_DTCKSEL_Msk         (0x1ul << EPWM_DTCTL2_3_DTCKSEL_Pos)               /*!< EPWM_T::DTCTL2_3: DTCKSEL Mask          */
+
+#define EPWM_DTCTL4_5_DTCNT_Pos           (0)                                               /*!< EPWM_T::DTCTL4_5: DTCNT Position        */
+#define EPWM_DTCTL4_5_DTCNT_Msk           (0xffful << EPWM_DTCTL4_5_DTCNT_Pos)               /*!< EPWM_T::DTCTL4_5: DTCNT Mask            */
+
+#define EPWM_DTCTL4_5_DTEN_Pos            (16)                                              /*!< EPWM_T::DTCTL4_5: DTEN Position         */
+#define EPWM_DTCTL4_5_DTEN_Msk            (0x1ul << EPWM_DTCTL4_5_DTEN_Pos)                  /*!< EPWM_T::DTCTL4_5: DTEN Mask             */
+
+#define EPWM_DTCTL4_5_DTCKSEL_Pos         (24)                                              /*!< EPWM_T::DTCTL4_5: DTCKSEL Position      */
+#define EPWM_DTCTL4_5_DTCKSEL_Msk         (0x1ul << EPWM_DTCTL4_5_DTCKSEL_Pos)               /*!< EPWM_T::DTCTL4_5: DTCKSEL Mask          */
+
+#define EPWM_PHS0_1_PHS_Pos               (0)                                               /*!< EPWM_T::PHS0_1: PHS Position            */
+#define EPWM_PHS0_1_PHS_Msk               (0xfffful << EPWM_PHS0_1_PHS_Pos)                  /*!< EPWM_T::PHS0_1: PHS Mask                */
+
+#define EPWM_PHS2_3_PHS_Pos               (0)                                               /*!< EPWM_T::PHS2_3: PHS Position            */
+#define EPWM_PHS2_3_PHS_Msk               (0xfffful << EPWM_PHS2_3_PHS_Pos)                  /*!< EPWM_T::PHS2_3: PHS Mask                */
+
+#define EPWM_PHS4_5_PHS_Pos               (0)                                               /*!< EPWM_T::PHS4_5: PHS Position            */
+#define EPWM_PHS4_5_PHS_Msk               (0xfffful << EPWM_PHS4_5_PHS_Pos)                  /*!< EPWM_T::PHS4_5: PHS Mask                */
+
+#define EPWM_CNT0_CNT_Pos                 (0)                                               /*!< EPWM_T::CNT0: CNT Position              */
+#define EPWM_CNT0_CNT_Msk                 (0xfffful << EPWM_CNT0_CNT_Pos)                    /*!< EPWM_T::CNT0: CNT Mask                  */
+
+#define EPWM_CNT0_DIRF_Pos                (16)                                              /*!< EPWM_T::CNT0: DIRF Position             */
+#define EPWM_CNT0_DIRF_Msk                (0x1ul << EPWM_CNT0_DIRF_Pos)                      /*!< EPWM_T::CNT0: DIRF Mask                 */
+
+#define EPWM_CNT1_CNT_Pos                 (0)                                               /*!< EPWM_T::CNT1: CNT Position              */
+#define EPWM_CNT1_CNT_Msk                 (0xfffful << EPWM_CNT1_CNT_Pos)                    /*!< EPWM_T::CNT1: CNT Mask                  */
+
+#define EPWM_CNT1_DIRF_Pos                (16)                                              /*!< EPWM_T::CNT1: DIRF Position             */
+#define EPWM_CNT1_DIRF_Msk                (0x1ul << EPWM_CNT1_DIRF_Pos)                      /*!< EPWM_T::CNT1: DIRF Mask                 */
+
+#define EPWM_CNT2_CNT_Pos                 (0)                                               /*!< EPWM_T::CNT2: CNT Position              */
+#define EPWM_CNT2_CNT_Msk                 (0xfffful << EPWM_CNT2_CNT_Pos)                    /*!< EPWM_T::CNT2: CNT Mask                  */
+
+#define EPWM_CNT2_DIRF_Pos                (16)                                              /*!< EPWM_T::CNT2: DIRF Position             */
+#define EPWM_CNT2_DIRF_Msk                (0x1ul << EPWM_CNT2_DIRF_Pos)                      /*!< EPWM_T::CNT2: DIRF Mask                 */
+
+#define EPWM_CNT3_CNT_Pos                 (0)                                               /*!< EPWM_T::CNT3: CNT Position              */
+#define EPWM_CNT3_CNT_Msk                 (0xfffful << EPWM_CNT3_CNT_Pos)                    /*!< EPWM_T::CNT3: CNT Mask                  */
+
+#define EPWM_CNT3_DIRF_Pos                (16)                                              /*!< EPWM_T::CNT3: DIRF Position             */
+#define EPWM_CNT3_DIRF_Msk                (0x1ul << EPWM_CNT3_DIRF_Pos)                      /*!< EPWM_T::CNT3: DIRF Mask                 */
+
+#define EPWM_CNT4_CNT_Pos                 (0)                                               /*!< EPWM_T::CNT4: CNT Position              */
+#define EPWM_CNT4_CNT_Msk                 (0xfffful << EPWM_CNT4_CNT_Pos)                    /*!< EPWM_T::CNT4: CNT Mask                  */
+
+#define EPWM_CNT4_DIRF_Pos                (16)                                              /*!< EPWM_T::CNT4: DIRF Position             */
+#define EPWM_CNT4_DIRF_Msk                (0x1ul << EPWM_CNT4_DIRF_Pos)                      /*!< EPWM_T::CNT4: DIRF Mask                 */
+
+#define EPWM_CNT5_CNT_Pos                 (0)                                               /*!< EPWM_T::CNT5: CNT Position              */
+#define EPWM_CNT5_CNT_Msk                 (0xfffful << EPWM_CNT5_CNT_Pos)                    /*!< EPWM_T::CNT5: CNT Mask                  */
+
+#define EPWM_CNT5_DIRF_Pos                (16)                                              /*!< EPWM_T::CNT5: DIRF Position             */
+#define EPWM_CNT5_DIRF_Msk                (0x1ul << EPWM_CNT5_DIRF_Pos)                      /*!< EPWM_T::CNT5: DIRF Mask                 */
+
+#define EPWM_WGCTL0_ZPCTL0_Pos            (0)                                               /*!< EPWM_T::WGCTL0: ZPCTL0 Position         */
+#define EPWM_WGCTL0_ZPCTL0_Msk            (0x3ul << EPWM_WGCTL0_ZPCTL0_Pos)                  /*!< EPWM_T::WGCTL0: ZPCTL0 Mask             */
+
+#define EPWM_WGCTL0_ZPCTL1_Pos            (2)                                               /*!< EPWM_T::WGCTL0: ZPCTL1 Position         */
+#define EPWM_WGCTL0_ZPCTL1_Msk            (0x3ul << EPWM_WGCTL0_ZPCTL1_Pos)                  /*!< EPWM_T::WGCTL0: ZPCTL1 Mask             */
+
+#define EPWM_WGCTL0_ZPCTL2_Pos            (4)                                               /*!< EPWM_T::WGCTL0: ZPCTL2 Position         */
+#define EPWM_WGCTL0_ZPCTL2_Msk            (0x3ul << EPWM_WGCTL0_ZPCTL2_Pos)                  /*!< EPWM_T::WGCTL0: ZPCTL2 Mask             */
+
+#define EPWM_WGCTL0_ZPCTL3_Pos            (6)                                               /*!< EPWM_T::WGCTL0: ZPCTL3 Position         */
+#define EPWM_WGCTL0_ZPCTL3_Msk            (0x3ul << EPWM_WGCTL0_ZPCTL3_Pos)                  /*!< EPWM_T::WGCTL0: ZPCTL3 Mask             */
+
+#define EPWM_WGCTL0_ZPCTL4_Pos            (8)                                               /*!< EPWM_T::WGCTL0: ZPCTL4 Position         */
+#define EPWM_WGCTL0_ZPCTL4_Msk            (0x3ul << EPWM_WGCTL0_ZPCTL4_Pos)                  /*!< EPWM_T::WGCTL0: ZPCTL4 Mask             */
+
+#define EPWM_WGCTL0_ZPCTL5_Pos            (10)                                              /*!< EPWM_T::WGCTL0: ZPCTL5 Position         */
+#define EPWM_WGCTL0_ZPCTL5_Msk            (0x3ul << EPWM_WGCTL0_ZPCTL5_Pos)                  /*!< EPWM_T::WGCTL0: ZPCTL5 Mask             */
+
+#define EPWM_WGCTL0_PRDPCTL0_Pos          (16)                                              /*!< EPWM_T::WGCTL0: PRDPCTL0 Position       */
+#define EPWM_WGCTL0_PRDPCTL0_Msk          (0x3ul << EPWM_WGCTL0_PRDPCTL0_Pos)                /*!< EPWM_T::WGCTL0: PRDPCTL0 Mask           */
+
+#define EPWM_WGCTL0_PRDPCTL1_Pos          (18)                                              /*!< EPWM_T::WGCTL0: PRDPCTL1 Position       */
+#define EPWM_WGCTL0_PRDPCTL1_Msk          (0x3ul << EPWM_WGCTL0_PRDPCTL1_Pos)                /*!< EPWM_T::WGCTL0: PRDPCTL1 Mask           */
+
+#define EPWM_WGCTL0_PRDPCTL2_Pos          (20)                                              /*!< EPWM_T::WGCTL0: PRDPCTL2 Position       */
+#define EPWM_WGCTL0_PRDPCTL2_Msk          (0x3ul << EPWM_WGCTL0_PRDPCTL2_Pos)                /*!< EPWM_T::WGCTL0: PRDPCTL2 Mask           */
+
+#define EPWM_WGCTL0_PRDPCTL3_Pos          (22)                                              /*!< EPWM_T::WGCTL0: PRDPCTL3 Position       */
+#define EPWM_WGCTL0_PRDPCTL3_Msk          (0x3ul << EPWM_WGCTL0_PRDPCTL3_Pos)                /*!< EPWM_T::WGCTL0: PRDPCTL3 Mask           */
+
+#define EPWM_WGCTL0_PRDPCTL4_Pos          (24)                                              /*!< EPWM_T::WGCTL0: PRDPCTL4 Position       */
+#define EPWM_WGCTL0_PRDPCTL4_Msk          (0x3ul << EPWM_WGCTL0_PRDPCTL4_Pos)                /*!< EPWM_T::WGCTL0: PRDPCTL4 Mask           */
+
+#define EPWM_WGCTL0_PRDPCTL5_Pos          (26)                                              /*!< EPWM_T::WGCTL0: PRDPCTL5 Position       */
+#define EPWM_WGCTL0_PRDPCTL5_Msk          (0x3ul << EPWM_WGCTL0_PRDPCTL5_Pos)                /*!< EPWM_T::WGCTL0: PRDPCTL5 Mask           */
+
+#define EPWM_WGCTL1_CMPUCTL0_Pos          (0)                                               /*!< EPWM_T::WGCTL1: CMPUCTL0 Position       */
+#define EPWM_WGCTL1_CMPUCTL0_Msk          (0x3ul << EPWM_WGCTL1_CMPUCTL0_Pos)                /*!< EPWM_T::WGCTL1: CMPUCTL0 Mask           */
+
+#define EPWM_WGCTL1_CMPUCTL1_Pos          (2)                                               /*!< EPWM_T::WGCTL1: CMPUCTL1 Position       */
+#define EPWM_WGCTL1_CMPUCTL1_Msk          (0x3ul << EPWM_WGCTL1_CMPUCTL1_Pos)                /*!< EPWM_T::WGCTL1: CMPUCTL1 Mask           */
+
+#define EPWM_WGCTL1_CMPUCTL2_Pos          (4)                                               /*!< EPWM_T::WGCTL1: CMPUCTL2 Position       */
+#define EPWM_WGCTL1_CMPUCTL2_Msk          (0x3ul << EPWM_WGCTL1_CMPUCTL2_Pos)                /*!< EPWM_T::WGCTL1: CMPUCTL2 Mask           */
+
+#define EPWM_WGCTL1_CMPUCTL3_Pos          (6)                                               /*!< EPWM_T::WGCTL1: CMPUCTL3 Position       */
+#define EPWM_WGCTL1_CMPUCTL3_Msk          (0x3ul << EPWM_WGCTL1_CMPUCTL3_Pos)                /*!< EPWM_T::WGCTL1: CMPUCTL3 Mask           */
+
+#define EPWM_WGCTL1_CMPUCTL4_Pos          (8)                                               /*!< EPWM_T::WGCTL1: CMPUCTL4 Position       */
+#define EPWM_WGCTL1_CMPUCTL4_Msk          (0x3ul << EPWM_WGCTL1_CMPUCTL4_Pos)                /*!< EPWM_T::WGCTL1: CMPUCTL4 Mask           */
+
+#define EPWM_WGCTL1_CMPUCTL5_Pos          (10)                                              /*!< EPWM_T::WGCTL1: CMPUCTL5 Position       */
+#define EPWM_WGCTL1_CMPUCTL5_Msk          (0x3ul << EPWM_WGCTL1_CMPUCTL5_Pos)                /*!< EPWM_T::WGCTL1: CMPUCTL5 Mask           */
+
+#define EPWM_WGCTL1_CMPDCTL0_Pos          (16)                                              /*!< EPWM_T::WGCTL1: CMPDCTL0 Position       */
+#define EPWM_WGCTL1_CMPDCTL0_Msk          (0x3ul << EPWM_WGCTL1_CMPDCTL0_Pos)                /*!< EPWM_T::WGCTL1: CMPDCTL0 Mask           */
+
+#define EPWM_WGCTL1_CMPDCTL1_Pos          (18)                                              /*!< EPWM_T::WGCTL1: CMPDCTL1 Position       */
+#define EPWM_WGCTL1_CMPDCTL1_Msk          (0x3ul << EPWM_WGCTL1_CMPDCTL1_Pos)                /*!< EPWM_T::WGCTL1: CMPDCTL1 Mask           */
+
+#define EPWM_WGCTL1_CMPDCTL2_Pos          (20)                                              /*!< EPWM_T::WGCTL1: CMPDCTL2 Position       */
+#define EPWM_WGCTL1_CMPDCTL2_Msk          (0x3ul << EPWM_WGCTL1_CMPDCTL2_Pos)                /*!< EPWM_T::WGCTL1: CMPDCTL2 Mask           */
+
+#define EPWM_WGCTL1_CMPDCTL3_Pos          (22)                                              /*!< EPWM_T::WGCTL1: CMPDCTL3 Position       */
+#define EPWM_WGCTL1_CMPDCTL3_Msk          (0x3ul << EPWM_WGCTL1_CMPDCTL3_Pos)                /*!< EPWM_T::WGCTL1: CMPDCTL3 Mask           */
+
+#define EPWM_WGCTL1_CMPDCTL4_Pos          (24)                                              /*!< EPWM_T::WGCTL1: CMPDCTL4 Position       */
+#define EPWM_WGCTL1_CMPDCTL4_Msk          (0x3ul << EPWM_WGCTL1_CMPDCTL4_Pos)                /*!< EPWM_T::WGCTL1: CMPDCTL4 Mask           */
+
+#define EPWM_WGCTL1_CMPDCTL5_Pos          (26)                                              /*!< EPWM_T::WGCTL1: CMPDCTL5 Position       */
+#define EPWM_WGCTL1_CMPDCTL5_Msk          (0x3ul << EPWM_WGCTL1_CMPDCTL5_Pos)                /*!< EPWM_T::WGCTL1: CMPDCTL5 Mask           */
+
+#define EPWM_MSKEN_MSKEN0_Pos             (0)                                               /*!< EPWM_T::MSKEN: MSKEN0 Position          */
+#define EPWM_MSKEN_MSKEN0_Msk             (0x1ul << EPWM_MSKEN_MSKEN0_Pos)                   /*!< EPWM_T::MSKEN: MSKEN0 Mask              */
+
+#define EPWM_MSKEN_MSKEN1_Pos             (1)                                               /*!< EPWM_T::MSKEN: MSKEN1 Position          */
+#define EPWM_MSKEN_MSKEN1_Msk             (0x1ul << EPWM_MSKEN_MSKEN1_Pos)                   /*!< EPWM_T::MSKEN: MSKEN1 Mask              */
+
+#define EPWM_MSKEN_MSKEN2_Pos             (2)                                               /*!< EPWM_T::MSKEN: MSKEN2 Position          */
+#define EPWM_MSKEN_MSKEN2_Msk             (0x1ul << EPWM_MSKEN_MSKEN2_Pos)                   /*!< EPWM_T::MSKEN: MSKEN2 Mask              */
+
+#define EPWM_MSKEN_MSKEN3_Pos             (3)                                               /*!< EPWM_T::MSKEN: MSKEN3 Position          */
+#define EPWM_MSKEN_MSKEN3_Msk             (0x1ul << EPWM_MSKEN_MSKEN3_Pos)                   /*!< EPWM_T::MSKEN: MSKEN3 Mask              */
+
+#define EPWM_MSKEN_MSKEN4_Pos             (4)                                               /*!< EPWM_T::MSKEN: MSKEN4 Position          */
+#define EPWM_MSKEN_MSKEN4_Msk             (0x1ul << EPWM_MSKEN_MSKEN4_Pos)                   /*!< EPWM_T::MSKEN: MSKEN4 Mask              */
+
+#define EPWM_MSKEN_MSKEN5_Pos             (5)                                               /*!< EPWM_T::MSKEN: MSKEN5 Position          */
+#define EPWM_MSKEN_MSKEN5_Msk             (0x1ul << EPWM_MSKEN_MSKEN5_Pos)                   /*!< EPWM_T::MSKEN: MSKEN5 Mask              */
+
+#define EPWM_MSK_MSKDAT0_Pos              (0)                                               /*!< EPWM_T::MSK: MSKDAT0 Position           */
+#define EPWM_MSK_MSKDAT0_Msk              (0x1ul << EPWM_MSK_MSKDAT0_Pos)                    /*!< EPWM_T::MSK: MSKDAT0 Mask               */
+
+#define EPWM_MSK_MSKDAT1_Pos              (1)                                               /*!< EPWM_T::MSK: MSKDAT1 Position           */
+#define EPWM_MSK_MSKDAT1_Msk              (0x1ul << EPWM_MSK_MSKDAT1_Pos)                    /*!< EPWM_T::MSK: MSKDAT1 Mask               */
+
+#define EPWM_MSK_MSKDAT2_Pos              (2)                                               /*!< EPWM_T::MSK: MSKDAT2 Position           */
+#define EPWM_MSK_MSKDAT2_Msk              (0x1ul << EPWM_MSK_MSKDAT2_Pos)                    /*!< EPWM_T::MSK: MSKDAT2 Mask               */
+
+#define EPWM_MSK_MSKDAT3_Pos              (3)                                               /*!< EPWM_T::MSK: MSKDAT3 Position           */
+#define EPWM_MSK_MSKDAT3_Msk              (0x1ul << EPWM_MSK_MSKDAT3_Pos)                    /*!< EPWM_T::MSK: MSKDAT3 Mask               */
+
+#define EPWM_MSK_MSKDAT4_Pos              (4)                                               /*!< EPWM_T::MSK: MSKDAT4 Position           */
+#define EPWM_MSK_MSKDAT4_Msk              (0x1ul << EPWM_MSK_MSKDAT4_Pos)                    /*!< EPWM_T::MSK: MSKDAT4 Mask               */
+
+#define EPWM_MSK_MSKDAT5_Pos              (5)                                               /*!< EPWM_T::MSK: MSKDAT5 Position           */
+#define EPWM_MSK_MSKDAT5_Msk              (0x1ul << EPWM_MSK_MSKDAT5_Pos)                    /*!< EPWM_T::MSK: MSKDAT5 Mask               */
+
+#define EPWM_BNF_BRK0NFEN_Pos             (0)                                               /*!< EPWM_T::BNF: BRK0NFEN Position          */
+#define EPWM_BNF_BRK0NFEN_Msk             (0x1ul << EPWM_BNF_BRK0NFEN_Pos)                   /*!< EPWM_T::BNF: BRK0NFEN Mask              */
+
+#define EPWM_BNF_BRK0NFSEL_Pos            (1)                                               /*!< EPWM_T::BNF: BRK0NFSEL Position         */
+#define EPWM_BNF_BRK0NFSEL_Msk            (0x7ul << EPWM_BNF_BRK0NFSEL_Pos)                  /*!< EPWM_T::BNF: BRK0NFSEL Mask             */
+
+#define EPWM_BNF_BRK0FCNT_Pos             (4)                                               /*!< EPWM_T::BNF: BRK0FCNT Position          */
+#define EPWM_BNF_BRK0FCNT_Msk             (0x7ul << EPWM_BNF_BRK0FCNT_Pos)                   /*!< EPWM_T::BNF: BRK0FCNT Mask              */
+
+#define EPWM_BNF_BRK0PINV_Pos             (7)                                               /*!< EPWM_T::BNF: BRK0PINV Position          */
+#define EPWM_BNF_BRK0PINV_Msk             (0x1ul << EPWM_BNF_BRK0PINV_Pos)                   /*!< EPWM_T::BNF: BRK0PINV Mask              */
+
+#define EPWM_BNF_BRK1NFEN_Pos             (8)                                               /*!< EPWM_T::BNF: BRK1NFEN Position          */
+#define EPWM_BNF_BRK1NFEN_Msk             (0x1ul << EPWM_BNF_BRK1NFEN_Pos)                   /*!< EPWM_T::BNF: BRK1NFEN Mask              */
+
+#define EPWM_BNF_BRK1NFSEL_Pos            (9)                                               /*!< EPWM_T::BNF: BRK1NFSEL Position         */
+#define EPWM_BNF_BRK1NFSEL_Msk            (0x7ul << EPWM_BNF_BRK1NFSEL_Pos)                  /*!< EPWM_T::BNF: BRK1NFSEL Mask             */
+
+#define EPWM_BNF_BRK1FCNT_Pos             (12)                                              /*!< EPWM_T::BNF: BRK1FCNT Position          */
+#define EPWM_BNF_BRK1FCNT_Msk             (0x7ul << EPWM_BNF_BRK1FCNT_Pos)                   /*!< EPWM_T::BNF: BRK1FCNT Mask              */
+
+#define EPWM_BNF_BRK1PINV_Pos             (15)                                              /*!< EPWM_T::BNF: BRK1PINV Position          */
+#define EPWM_BNF_BRK1PINV_Msk             (0x1ul << EPWM_BNF_BRK1PINV_Pos)                   /*!< EPWM_T::BNF: BRK1PINV Mask              */
+
+#define EPWM_BNF_BK0SRC_Pos               (16)                                              /*!< EPWM_T::BNF: BK0SRC Position            */
+#define EPWM_BNF_BK0SRC_Msk               (0x1ul << EPWM_BNF_BK0SRC_Pos)                     /*!< EPWM_T::BNF: BK0SRC Mask                */
+
+#define EPWM_BNF_BK1SRC_Pos               (24)                                              /*!< EPWM_T::BNF: BK1SRC Position            */
+#define EPWM_BNF_BK1SRC_Msk               (0x1ul << EPWM_BNF_BK1SRC_Pos)                     /*!< EPWM_T::BNF: BK1SRC Mask                */
+
+#define EPWM_FAILBRK_CSSBRKEN_Pos         (0)                                               /*!< EPWM_T::FAILBRK: CSSBRKEN Position      */
+#define EPWM_FAILBRK_CSSBRKEN_Msk         (0x1ul << EPWM_FAILBRK_CSSBRKEN_Pos)               /*!< EPWM_T::FAILBRK: CSSBRKEN Mask          */
+
+#define EPWM_FAILBRK_BODBRKEN_Pos         (1)                                               /*!< EPWM_T::FAILBRK: BODBRKEN Position      */
+#define EPWM_FAILBRK_BODBRKEN_Msk         (0x1ul << EPWM_FAILBRK_BODBRKEN_Pos)               /*!< EPWM_T::FAILBRK: BODBRKEN Mask          */
+
+#define EPWM_FAILBRK_RAMBRKEN_Pos         (2)                                               /*!< EPWM_T::FAILBRK: RAMBRKEN Position      */
+#define EPWM_FAILBRK_RAMBRKEN_Msk         (0x1ul << EPWM_FAILBRK_RAMBRKEN_Pos)               /*!< EPWM_T::FAILBRK: RAMBRKEN Mask          */
+
+#define EPWM_FAILBRK_CORBRKEN_Pos         (3)                                               /*!< EPWM_T::FAILBRK: CORBRKEN Position      */
+#define EPWM_FAILBRK_CORBRKEN_Msk         (0x1ul << EPWM_FAILBRK_CORBRKEN_Pos)               /*!< EPWM_T::FAILBRK: CORBRKEN Mask          */
+
+#define EPWM_BRKCTL0_1_CPO0EBEN_Pos       (0)                                               /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Position    */
+#define EPWM_BRKCTL0_1_CPO0EBEN_Msk       (0x1ul << EPWM_BRKCTL0_1_CPO0EBEN_Pos)             /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Mask        */
+
+#define EPWM_BRKCTL0_1_CPO1EBEN_Pos       (1)                                               /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Position    */
+#define EPWM_BRKCTL0_1_CPO1EBEN_Msk       (0x1ul << EPWM_BRKCTL0_1_CPO1EBEN_Pos)             /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Mask        */
+
+#define EPWM_BRKCTL0_1_BRKP0EEN_Pos       (4)                                               /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Position    */
+#define EPWM_BRKCTL0_1_BRKP0EEN_Msk       (0x1ul << EPWM_BRKCTL0_1_BRKP0EEN_Pos)             /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Mask        */
+
+#define EPWM_BRKCTL0_1_BRKP1EEN_Pos       (5)                                               /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Position    */
+#define EPWM_BRKCTL0_1_BRKP1EEN_Msk       (0x1ul << EPWM_BRKCTL0_1_BRKP1EEN_Pos)             /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Mask        */
+
+#define EPWM_BRKCTL0_1_SYSEBEN_Pos        (7)                                               /*!< EPWM_T::BRKCTL0_1: SYSEBEN Position     */
+#define EPWM_BRKCTL0_1_SYSEBEN_Msk        (0x1ul << EPWM_BRKCTL0_1_SYSEBEN_Pos)              /*!< EPWM_T::BRKCTL0_1: SYSEBEN Mask         */
+
+#define EPWM_BRKCTL0_1_CPO0LBEN_Pos       (8)                                               /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Position    */
+#define EPWM_BRKCTL0_1_CPO0LBEN_Msk       (0x1ul << EPWM_BRKCTL0_1_CPO0LBEN_Pos)             /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Mask        */
+
+#define EPWM_BRKCTL0_1_CPO1LBEN_Pos       (9)                                               /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Position    */
+#define EPWM_BRKCTL0_1_CPO1LBEN_Msk       (0x1ul << EPWM_BRKCTL0_1_CPO1LBEN_Pos)             /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Mask        */
+
+#define EPWM_BRKCTL0_1_BRKP0LEN_Pos       (12)                                              /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Position    */
+#define EPWM_BRKCTL0_1_BRKP0LEN_Msk       (0x1ul << EPWM_BRKCTL0_1_BRKP0LEN_Pos)             /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Mask        */
+
+#define EPWM_BRKCTL0_1_BRKP1LEN_Pos       (13)                                              /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Position    */
+#define EPWM_BRKCTL0_1_BRKP1LEN_Msk       (0x1ul << EPWM_BRKCTL0_1_BRKP1LEN_Pos)             /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Mask        */
+
+#define EPWM_BRKCTL0_1_SYSLBEN_Pos        (15)                                              /*!< EPWM_T::BRKCTL0_1: SYSLBEN Position     */
+#define EPWM_BRKCTL0_1_SYSLBEN_Msk        (0x1ul << EPWM_BRKCTL0_1_SYSLBEN_Pos)              /*!< EPWM_T::BRKCTL0_1: SYSLBEN Mask         */
+
+#define EPWM_BRKCTL0_1_BRKAEVEN_Pos       (16)                                              /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Position    */
+#define EPWM_BRKCTL0_1_BRKAEVEN_Msk       (0x3ul << EPWM_BRKCTL0_1_BRKAEVEN_Pos)             /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Mask        */
+
+#define EPWM_BRKCTL0_1_BRKAODD_Pos        (18)                                              /*!< EPWM_T::BRKCTL0_1: BRKAODD Position     */
+#define EPWM_BRKCTL0_1_BRKAODD_Msk        (0x3ul << EPWM_BRKCTL0_1_BRKAODD_Pos)              /*!< EPWM_T::BRKCTL0_1: BRKAODD Mask         */
+
+#define EPWM_BRKCTL0_1_EADCEBEN_Pos       (20)                                              /*!< EPWM_T::BRKCTL0_1: EADCEBEN Position    */
+#define EPWM_BRKCTL0_1_EADCEBEN_Msk       (0x1ul << EPWM_BRKCTL0_1_EADCEBEN_Pos)             /*!< EPWM_T::BRKCTL0_1: EADCEBEN Mask        */
+
+#define EPWM_BRKCTL0_1_EADCLBEN_Pos       (28)                                              /*!< EPWM_T::BRKCTL0_1: EADCLBEN Position    */
+#define EPWM_BRKCTL0_1_EADCLBEN_Msk       (0x1ul << EPWM_BRKCTL0_1_EADCLBEN_Pos)             /*!< EPWM_T::BRKCTL0_1: EADCLBEN Mask        */
+
+#define EPWM_BRKCTL2_3_CPO0EBEN_Pos       (0)                                               /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Position    */
+#define EPWM_BRKCTL2_3_CPO0EBEN_Msk       (0x1ul << EPWM_BRKCTL2_3_CPO0EBEN_Pos)             /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Mask        */
+
+#define EPWM_BRKCTL2_3_CPO1EBEN_Pos       (1)                                               /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Position    */
+#define EPWM_BRKCTL2_3_CPO1EBEN_Msk       (0x1ul << EPWM_BRKCTL2_3_CPO1EBEN_Pos)             /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Mask        */
+
+#define EPWM_BRKCTL2_3_BRKP0EEN_Pos       (4)                                               /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Position    */
+#define EPWM_BRKCTL2_3_BRKP0EEN_Msk       (0x1ul << EPWM_BRKCTL2_3_BRKP0EEN_Pos)             /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Mask        */
+
+#define EPWM_BRKCTL2_3_BRKP1EEN_Pos       (5)                                               /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Position    */
+#define EPWM_BRKCTL2_3_BRKP1EEN_Msk       (0x1ul << EPWM_BRKCTL2_3_BRKP1EEN_Pos)             /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Mask        */
+
+#define EPWM_BRKCTL2_3_SYSEBEN_Pos        (7)                                               /*!< EPWM_T::BRKCTL2_3: SYSEBEN Position     */
+#define EPWM_BRKCTL2_3_SYSEBEN_Msk        (0x1ul << EPWM_BRKCTL2_3_SYSEBEN_Pos)              /*!< EPWM_T::BRKCTL2_3: SYSEBEN Mask         */
+
+#define EPWM_BRKCTL2_3_CPO0LBEN_Pos       (8)                                               /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Position    */
+#define EPWM_BRKCTL2_3_CPO0LBEN_Msk       (0x1ul << EPWM_BRKCTL2_3_CPO0LBEN_Pos)             /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Mask        */
+
+#define EPWM_BRKCTL2_3_CPO1LBEN_Pos       (9)                                               /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Position    */
+#define EPWM_BRKCTL2_3_CPO1LBEN_Msk       (0x1ul << EPWM_BRKCTL2_3_CPO1LBEN_Pos)             /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Mask        */
+
+#define EPWM_BRKCTL2_3_BRKP0LEN_Pos       (12)                                              /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Position    */
+#define EPWM_BRKCTL2_3_BRKP0LEN_Msk       (0x1ul << EPWM_BRKCTL2_3_BRKP0LEN_Pos)             /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Mask        */
+
+#define EPWM_BRKCTL2_3_BRKP1LEN_Pos       (13)                                              /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Position    */
+#define EPWM_BRKCTL2_3_BRKP1LEN_Msk       (0x1ul << EPWM_BRKCTL2_3_BRKP1LEN_Pos)             /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Mask        */
+
+#define EPWM_BRKCTL2_3_SYSLBEN_Pos        (15)                                              /*!< EPWM_T::BRKCTL2_3: SYSLBEN Position     */
+#define EPWM_BRKCTL2_3_SYSLBEN_Msk        (0x1ul << EPWM_BRKCTL2_3_SYSLBEN_Pos)              /*!< EPWM_T::BRKCTL2_3: SYSLBEN Mask         */
+
+#define EPWM_BRKCTL2_3_BRKAEVEN_Pos       (16)                                              /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Position    */
+#define EPWM_BRKCTL2_3_BRKAEVEN_Msk       (0x3ul << EPWM_BRKCTL2_3_BRKAEVEN_Pos)             /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Mask        */
+
+#define EPWM_BRKCTL2_3_BRKAODD_Pos        (18)                                              /*!< EPWM_T::BRKCTL2_3: BRKAODD Position     */
+#define EPWM_BRKCTL2_3_BRKAODD_Msk        (0x3ul << EPWM_BRKCTL2_3_BRKAODD_Pos)              /*!< EPWM_T::BRKCTL2_3: BRKAODD Mask         */
+
+#define EPWM_BRKCTL2_3_EADCEBEN_Pos       (20)                                              /*!< EPWM_T::BRKCTL2_3: EADCEBEN Position    */
+#define EPWM_BRKCTL2_3_EADCEBEN_Msk       (0x1ul << EPWM_BRKCTL2_3_EADCEBEN_Pos)             /*!< EPWM_T::BRKCTL2_3: EADCEBEN Mask        */
+
+#define EPWM_BRKCTL2_3_EADCLBEN_Pos       (28)                                              /*!< EPWM_T::BRKCTL2_3: EADCLBEN Position    */
+#define EPWM_BRKCTL2_3_EADCLBEN_Msk       (0x1ul << EPWM_BRKCTL2_3_EADCLBEN_Pos)             /*!< EPWM_T::BRKCTL2_3: EADCLBEN Mask        */
+
+#define EPWM_BRKCTL4_5_CPO0EBEN_Pos       (0)                                               /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Position    */
+#define EPWM_BRKCTL4_5_CPO0EBEN_Msk       (0x1ul << EPWM_BRKCTL4_5_CPO0EBEN_Pos)             /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Mask        */
+
+#define EPWM_BRKCTL4_5_CPO1EBEN_Pos       (1)                                               /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Position    */
+#define EPWM_BRKCTL4_5_CPO1EBEN_Msk       (0x1ul << EPWM_BRKCTL4_5_CPO1EBEN_Pos)             /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Mask        */
+
+#define EPWM_BRKCTL4_5_BRKP0EEN_Pos       (4)                                               /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Position    */
+#define EPWM_BRKCTL4_5_BRKP0EEN_Msk       (0x1ul << EPWM_BRKCTL4_5_BRKP0EEN_Pos)             /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Mask        */
+
+#define EPWM_BRKCTL4_5_BRKP1EEN_Pos       (5)                                               /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Position    */
+#define EPWM_BRKCTL4_5_BRKP1EEN_Msk       (0x1ul << EPWM_BRKCTL4_5_BRKP1EEN_Pos)             /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Mask        */
+
+#define EPWM_BRKCTL4_5_SYSEBEN_Pos        (7)                                               /*!< EPWM_T::BRKCTL4_5: SYSEBEN Position     */
+#define EPWM_BRKCTL4_5_SYSEBEN_Msk        (0x1ul << EPWM_BRKCTL4_5_SYSEBEN_Pos)              /*!< EPWM_T::BRKCTL4_5: SYSEBEN Mask         */
+
+#define EPWM_BRKCTL4_5_CPO0LBEN_Pos       (8)                                               /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Position    */
+#define EPWM_BRKCTL4_5_CPO0LBEN_Msk       (0x1ul << EPWM_BRKCTL4_5_CPO0LBEN_Pos)             /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Mask        */
+
+#define EPWM_BRKCTL4_5_CPO1LBEN_Pos       (9)                                               /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Position    */
+#define EPWM_BRKCTL4_5_CPO1LBEN_Msk       (0x1ul << EPWM_BRKCTL4_5_CPO1LBEN_Pos)             /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Mask        */
+
+#define EPWM_BRKCTL4_5_BRKP0LEN_Pos       (12)                                              /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Position    */
+#define EPWM_BRKCTL4_5_BRKP0LEN_Msk       (0x1ul << EPWM_BRKCTL4_5_BRKP0LEN_Pos)             /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Mask        */
+
+#define EPWM_BRKCTL4_5_BRKP1LEN_Pos       (13)                                              /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Position    */
+#define EPWM_BRKCTL4_5_BRKP1LEN_Msk       (0x1ul << EPWM_BRKCTL4_5_BRKP1LEN_Pos)             /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Mask        */
+
+#define EPWM_BRKCTL4_5_SYSLBEN_Pos        (15)                                              /*!< EPWM_T::BRKCTL4_5: SYSLBEN Position     */
+#define EPWM_BRKCTL4_5_SYSLBEN_Msk        (0x1ul << EPWM_BRKCTL4_5_SYSLBEN_Pos)              /*!< EPWM_T::BRKCTL4_5: SYSLBEN Mask         */
+
+#define EPWM_BRKCTL4_5_BRKAEVEN_Pos       (16)                                              /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Position    */
+#define EPWM_BRKCTL4_5_BRKAEVEN_Msk       (0x3ul << EPWM_BRKCTL4_5_BRKAEVEN_Pos)             /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Mask        */
+
+#define EPWM_BRKCTL4_5_BRKAODD_Pos        (18)                                              /*!< EPWM_T::BRKCTL4_5: BRKAODD Position     */
+#define EPWM_BRKCTL4_5_BRKAODD_Msk        (0x3ul << EPWM_BRKCTL4_5_BRKAODD_Pos)              /*!< EPWM_T::BRKCTL4_5: BRKAODD Mask         */
+
+#define EPWM_BRKCTL4_5_EADCEBEN_Pos       (20)                                              /*!< EPWM_T::BRKCTL4_5: EADCEBEN Position    */
+#define EPWM_BRKCTL4_5_EADCEBEN_Msk       (0x1ul << EPWM_BRKCTL4_5_EADCEBEN_Pos)             /*!< EPWM_T::BRKCTL4_5: EADCEBEN Mask        */
+
+#define EPWM_BRKCTL4_5_EADCLBEN_Pos       (28)                                              /*!< EPWM_T::BRKCTL4_5: EADCLBEN Position    */
+#define EPWM_BRKCTL4_5_EADCLBEN_Msk       (0x1ul << EPWM_BRKCTL4_5_EADCLBEN_Pos)             /*!< EPWM_T::BRKCTL4_5: EADCLBEN Mask        */
+
+#define EPWM_POLCTL_PINV0_Pos             (0)                                               /*!< EPWM_T::POLCTL: PINV0 Position          */
+#define EPWM_POLCTL_PINV0_Msk             (0x1ul << EPWM_POLCTL_PINV0_Pos)                   /*!< EPWM_T::POLCTL: PINV0 Mask              */
+
+#define EPWM_POLCTL_PINV1_Pos             (1)                                               /*!< EPWM_T::POLCTL: PINV1 Position          */
+#define EPWM_POLCTL_PINV1_Msk             (0x1ul << EPWM_POLCTL_PINV1_Pos)                   /*!< EPWM_T::POLCTL: PINV1 Mask              */
+
+#define EPWM_POLCTL_PINV2_Pos             (2)                                               /*!< EPWM_T::POLCTL: PINV2 Position          */
+#define EPWM_POLCTL_PINV2_Msk             (0x1ul << EPWM_POLCTL_PINV2_Pos)                   /*!< EPWM_T::POLCTL: PINV2 Mask              */
+
+#define EPWM_POLCTL_PINV3_Pos             (3)                                               /*!< EPWM_T::POLCTL: PINV3 Position          */
+#define EPWM_POLCTL_PINV3_Msk             (0x1ul << EPWM_POLCTL_PINV3_Pos)                   /*!< EPWM_T::POLCTL: PINV3 Mask              */
+
+#define EPWM_POLCTL_PINV4_Pos             (4)                                               /*!< EPWM_T::POLCTL: PINV4 Position          */
+#define EPWM_POLCTL_PINV4_Msk             (0x1ul << EPWM_POLCTL_PINV4_Pos)                   /*!< EPWM_T::POLCTL: PINV4 Mask              */
+
+#define EPWM_POLCTL_PINV5_Pos             (5)                                               /*!< EPWM_T::POLCTL: PINV5 Position          */
+#define EPWM_POLCTL_PINV5_Msk             (0x1ul << EPWM_POLCTL_PINV5_Pos)                   /*!< EPWM_T::POLCTL: PINV5 Mask              */
+
+#define EPWM_POEN_POEN0_Pos               (0)                                               /*!< EPWM_T::POEN: POEN0 Position            */
+#define EPWM_POEN_POEN0_Msk               (0x1ul << EPWM_POEN_POEN0_Pos)                     /*!< EPWM_T::POEN: POEN0 Mask                */
+
+#define EPWM_POEN_POEN1_Pos               (1)                                               /*!< EPWM_T::POEN: POEN1 Position            */
+#define EPWM_POEN_POEN1_Msk               (0x1ul << EPWM_POEN_POEN1_Pos)                     /*!< EPWM_T::POEN: POEN1 Mask                */
+
+#define EPWM_POEN_POEN2_Pos               (2)                                               /*!< EPWM_T::POEN: POEN2 Position            */
+#define EPWM_POEN_POEN2_Msk               (0x1ul << EPWM_POEN_POEN2_Pos)                     /*!< EPWM_T::POEN: POEN2 Mask                */
+
+#define EPWM_POEN_POEN3_Pos               (3)                                               /*!< EPWM_T::POEN: POEN3 Position            */
+#define EPWM_POEN_POEN3_Msk               (0x1ul << EPWM_POEN_POEN3_Pos)                     /*!< EPWM_T::POEN: POEN3 Mask                */
+
+#define EPWM_POEN_POEN4_Pos               (4)                                               /*!< EPWM_T::POEN: POEN4 Position            */
+#define EPWM_POEN_POEN4_Msk               (0x1ul << EPWM_POEN_POEN4_Pos)                     /*!< EPWM_T::POEN: POEN4 Mask                */
+
+#define EPWM_POEN_POEN5_Pos               (5)                                               /*!< EPWM_T::POEN: POEN5 Position            */
+#define EPWM_POEN_POEN5_Msk               (0x1ul << EPWM_POEN_POEN5_Pos)                     /*!< EPWM_T::POEN: POEN5 Mask                */
+
+#define EPWM_SWBRK_BRKETRG0_Pos           (0)                                               /*!< EPWM_T::SWBRK: BRKETRG0 Position        */
+#define EPWM_SWBRK_BRKETRG0_Msk           (0x1ul << EPWM_SWBRK_BRKETRG0_Pos)                 /*!< EPWM_T::SWBRK: BRKETRG0 Mask            */
+
+#define EPWM_SWBRK_BRKETRG2_Pos           (1)                                               /*!< EPWM_T::SWBRK: BRKETRG2 Position        */
+#define EPWM_SWBRK_BRKETRG2_Msk           (0x1ul << EPWM_SWBRK_BRKETRG2_Pos)                 /*!< EPWM_T::SWBRK: BRKETRG2 Mask            */
+
+#define EPWM_SWBRK_BRKETRG4_Pos           (2)                                               /*!< EPWM_T::SWBRK: BRKETRG4 Position        */
+#define EPWM_SWBRK_BRKETRG4_Msk           (0x1ul << EPWM_SWBRK_BRKETRG4_Pos)                 /*!< EPWM_T::SWBRK: BRKETRG4 Mask            */
+
+#define EPWM_SWBRK_BRKLTRG0_Pos           (8)                                               /*!< EPWM_T::SWBRK: BRKLTRG0 Position        */
+#define EPWM_SWBRK_BRKLTRG0_Msk           (0x1ul << EPWM_SWBRK_BRKLTRG0_Pos)                 /*!< EPWM_T::SWBRK: BRKLTRG0 Mask            */
+
+#define EPWM_SWBRK_BRKLTRG2_Pos           (9)                                               /*!< EPWM_T::SWBRK: BRKLTRG2 Position        */
+#define EPWM_SWBRK_BRKLTRG2_Msk           (0x1ul << EPWM_SWBRK_BRKLTRG2_Pos)                 /*!< EPWM_T::SWBRK: BRKLTRG2 Mask            */
+
+#define EPWM_SWBRK_BRKLTRG4_Pos           (10)                                              /*!< EPWM_T::SWBRK: BRKLTRG4 Position        */
+#define EPWM_SWBRK_BRKLTRG4_Msk           (0x1ul << EPWM_SWBRK_BRKLTRG4_Pos)                 /*!< EPWM_T::SWBRK: BRKLTRG4 Mask            */
+
+#define EPWM_INTEN0_ZIEN0_Pos             (0)                                               /*!< EPWM_T::INTEN0: ZIEN0 Position          */
+#define EPWM_INTEN0_ZIEN0_Msk             (0x1ul << EPWM_INTEN0_ZIEN0_Pos)                   /*!< EPWM_T::INTEN0: ZIEN0 Mask              */
+
+#define EPWM_INTEN0_ZIEN1_Pos             (1)                                               /*!< EPWM_T::INTEN0: ZIEN1 Position          */
+#define EPWM_INTEN0_ZIEN1_Msk             (0x1ul << EPWM_INTEN0_ZIEN1_Pos)                   /*!< EPWM_T::INTEN0: ZIEN1 Mask              */
+
+#define EPWM_INTEN0_ZIEN2_Pos             (2)                                               /*!< EPWM_T::INTEN0: ZIEN2 Position          */
+#define EPWM_INTEN0_ZIEN2_Msk             (0x1ul << EPWM_INTEN0_ZIEN2_Pos)                   /*!< EPWM_T::INTEN0: ZIEN2 Mask              */
+
+#define EPWM_INTEN0_ZIEN3_Pos             (3)                                               /*!< EPWM_T::INTEN0: ZIEN3 Position          */
+#define EPWM_INTEN0_ZIEN3_Msk             (0x1ul << EPWM_INTEN0_ZIEN3_Pos)                   /*!< EPWM_T::INTEN0: ZIEN3 Mask              */
+
+#define EPWM_INTEN0_ZIEN4_Pos             (4)                                               /*!< EPWM_T::INTEN0: ZIEN4 Position          */
+#define EPWM_INTEN0_ZIEN4_Msk             (0x1ul << EPWM_INTEN0_ZIEN4_Pos)                   /*!< EPWM_T::INTEN0: ZIEN4 Mask              */
+
+#define EPWM_INTEN0_ZIEN5_Pos             (5)                                               /*!< EPWM_T::INTEN0: ZIEN5 Position          */
+#define EPWM_INTEN0_ZIEN5_Msk             (0x1ul << EPWM_INTEN0_ZIEN5_Pos)                   /*!< EPWM_T::INTEN0: ZIEN5 Mask              */
+
+#define EPWM_INTEN0_PIEN0_Pos             (8)                                               /*!< EPWM_T::INTEN0: PIEN0 Position          */
+#define EPWM_INTEN0_PIEN0_Msk             (0x1ul << EPWM_INTEN0_PIEN0_Pos)                   /*!< EPWM_T::INTEN0: PIEN0 Mask              */
+
+#define EPWM_INTEN0_PIEN1_Pos             (9)                                               /*!< EPWM_T::INTEN0: PIEN1 Position          */
+#define EPWM_INTEN0_PIEN1_Msk             (0x1ul << EPWM_INTEN0_PIEN1_Pos)                   /*!< EPWM_T::INTEN0: PIEN1 Mask              */
+
+#define EPWM_INTEN0_PIEN2_Pos             (10)                                              /*!< EPWM_T::INTEN0: PIEN2 Position          */
+#define EPWM_INTEN0_PIEN2_Msk             (0x1ul << EPWM_INTEN0_PIEN2_Pos)                   /*!< EPWM_T::INTEN0: PIEN2 Mask              */
+
+#define EPWM_INTEN0_PIEN3_Pos             (11)                                              /*!< EPWM_T::INTEN0: PIEN3 Position          */
+#define EPWM_INTEN0_PIEN3_Msk             (0x1ul << EPWM_INTEN0_PIEN3_Pos)                   /*!< EPWM_T::INTEN0: PIEN3 Mask              */
+
+#define EPWM_INTEN0_PIEN4_Pos             (12)                                              /*!< EPWM_T::INTEN0: PIEN4 Position          */
+#define EPWM_INTEN0_PIEN4_Msk             (0x1ul << EPWM_INTEN0_PIEN4_Pos)                   /*!< EPWM_T::INTEN0: PIEN4 Mask              */
+
+#define EPWM_INTEN0_PIEN5_Pos             (13)                                              /*!< EPWM_T::INTEN0: PIEN5 Position          */
+#define EPWM_INTEN0_PIEN5_Msk             (0x1ul << EPWM_INTEN0_PIEN5_Pos)                   /*!< EPWM_T::INTEN0: PIEN5 Mask              */
+
+#define EPWM_INTEN0_CMPUIEN0_Pos          (16)                                              /*!< EPWM_T::INTEN0: CMPUIEN0 Position       */
+#define EPWM_INTEN0_CMPUIEN0_Msk          (0x1ul << EPWM_INTEN0_CMPUIEN0_Pos)                /*!< EPWM_T::INTEN0: CMPUIEN0 Mask           */
+
+#define EPWM_INTEN0_CMPUIEN1_Pos          (17)                                              /*!< EPWM_T::INTEN0: CMPUIEN1 Position       */
+#define EPWM_INTEN0_CMPUIEN1_Msk          (0x1ul << EPWM_INTEN0_CMPUIEN1_Pos)                /*!< EPWM_T::INTEN0: CMPUIEN1 Mask           */
+
+#define EPWM_INTEN0_CMPUIEN2_Pos          (18)                                              /*!< EPWM_T::INTEN0: CMPUIEN2 Position       */
+#define EPWM_INTEN0_CMPUIEN2_Msk          (0x1ul << EPWM_INTEN0_CMPUIEN2_Pos)                /*!< EPWM_T::INTEN0: CMPUIEN2 Mask           */
+
+#define EPWM_INTEN0_CMPUIEN3_Pos          (19)                                              /*!< EPWM_T::INTEN0: CMPUIEN3 Position       */
+#define EPWM_INTEN0_CMPUIEN3_Msk          (0x1ul << EPWM_INTEN0_CMPUIEN3_Pos)                /*!< EPWM_T::INTEN0: CMPUIEN3 Mask           */
+
+#define EPWM_INTEN0_CMPUIEN4_Pos          (20)                                              /*!< EPWM_T::INTEN0: CMPUIEN4 Position       */
+#define EPWM_INTEN0_CMPUIEN4_Msk          (0x1ul << EPWM_INTEN0_CMPUIEN4_Pos)                /*!< EPWM_T::INTEN0: CMPUIEN4 Mask           */
+
+#define EPWM_INTEN0_CMPUIEN5_Pos          (21)                                              /*!< EPWM_T::INTEN0: CMPUIEN5 Position       */
+#define EPWM_INTEN0_CMPUIEN5_Msk          (0x1ul << EPWM_INTEN0_CMPUIEN5_Pos)                /*!< EPWM_T::INTEN0: CMPUIEN5 Mask           */
+
+#define EPWM_INTEN0_CMPDIEN0_Pos          (24)                                              /*!< EPWM_T::INTEN0: CMPDIEN0 Position       */
+#define EPWM_INTEN0_CMPDIEN0_Msk          (0x1ul << EPWM_INTEN0_CMPDIEN0_Pos)                /*!< EPWM_T::INTEN0: CMPDIEN0 Mask           */
+
+#define EPWM_INTEN0_CMPDIEN1_Pos          (25)                                              /*!< EPWM_T::INTEN0: CMPDIEN1 Position       */
+#define EPWM_INTEN0_CMPDIEN1_Msk          (0x1ul << EPWM_INTEN0_CMPDIEN1_Pos)                /*!< EPWM_T::INTEN0: CMPDIEN1 Mask           */
+
+#define EPWM_INTEN0_CMPDIEN2_Pos          (26)                                              /*!< EPWM_T::INTEN0: CMPDIEN2 Position       */
+#define EPWM_INTEN0_CMPDIEN2_Msk          (0x1ul << EPWM_INTEN0_CMPDIEN2_Pos)                /*!< EPWM_T::INTEN0: CMPDIEN2 Mask           */
+
+#define EPWM_INTEN0_CMPDIEN3_Pos          (27)                                              /*!< EPWM_T::INTEN0: CMPDIEN3 Position       */
+#define EPWM_INTEN0_CMPDIEN3_Msk          (0x1ul << EPWM_INTEN0_CMPDIEN3_Pos)                /*!< EPWM_T::INTEN0: CMPDIEN3 Mask           */
+
+#define EPWM_INTEN0_CMPDIEN4_Pos          (28)                                              /*!< EPWM_T::INTEN0: CMPDIEN4 Position       */
+#define EPWM_INTEN0_CMPDIEN4_Msk          (0x1ul << EPWM_INTEN0_CMPDIEN4_Pos)                /*!< EPWM_T::INTEN0: CMPDIEN4 Mask           */
+
+#define EPWM_INTEN0_CMPDIEN5_Pos          (29)                                              /*!< EPWM_T::INTEN0: CMPDIEN5 Position       */
+#define EPWM_INTEN0_CMPDIEN5_Msk          (0x1ul << EPWM_INTEN0_CMPDIEN5_Pos)                /*!< EPWM_T::INTEN0: CMPDIEN5 Mask           */
+
+#define EPWM_INTEN1_BRKEIEN0_1_Pos        (0)                                               /*!< EPWM_T::INTEN1: BRKEIEN0_1 Position     */
+#define EPWM_INTEN1_BRKEIEN0_1_Msk        (0x1ul << EPWM_INTEN1_BRKEIEN0_1_Pos)              /*!< EPWM_T::INTEN1: BRKEIEN0_1 Mask         */
+
+#define EPWM_INTEN1_BRKEIEN2_3_Pos        (1)                                               /*!< EPWM_T::INTEN1: BRKEIEN2_3 Position     */
+#define EPWM_INTEN1_BRKEIEN2_3_Msk        (0x1ul << EPWM_INTEN1_BRKEIEN2_3_Pos)              /*!< EPWM_T::INTEN1: BRKEIEN2_3 Mask         */
+
+#define EPWM_INTEN1_BRKEIEN4_5_Pos        (2)                                               /*!< EPWM_T::INTEN1: BRKEIEN4_5 Position     */
+#define EPWM_INTEN1_BRKEIEN4_5_Msk        (0x1ul << EPWM_INTEN1_BRKEIEN4_5_Pos)              /*!< EPWM_T::INTEN1: BRKEIEN4_5 Mask         */
+
+#define EPWM_INTEN1_BRKLIEN0_1_Pos        (8)                                               /*!< EPWM_T::INTEN1: BRKLIEN0_1 Position     */
+#define EPWM_INTEN1_BRKLIEN0_1_Msk        (0x1ul << EPWM_INTEN1_BRKLIEN0_1_Pos)              /*!< EPWM_T::INTEN1: BRKLIEN0_1 Mask         */
+
+#define EPWM_INTEN1_BRKLIEN2_3_Pos        (9)                                               /*!< EPWM_T::INTEN1: BRKLIEN2_3 Position     */
+#define EPWM_INTEN1_BRKLIEN2_3_Msk        (0x1ul << EPWM_INTEN1_BRKLIEN2_3_Pos)              /*!< EPWM_T::INTEN1: BRKLIEN2_3 Mask         */
+
+#define EPWM_INTEN1_BRKLIEN4_5_Pos        (10)                                              /*!< EPWM_T::INTEN1: BRKLIEN4_5 Position     */
+#define EPWM_INTEN1_BRKLIEN4_5_Msk        (0x1ul << EPWM_INTEN1_BRKLIEN4_5_Pos)              /*!< EPWM_T::INTEN1: BRKLIEN4_5 Mask         */
+
+#define EPWM_INTSTS0_ZIF0_Pos             (0)                                               /*!< EPWM_T::INTSTS0: ZIF0 Position          */
+#define EPWM_INTSTS0_ZIF0_Msk             (0x1ul << EPWM_INTSTS0_ZIF0_Pos)                   /*!< EPWM_T::INTSTS0: ZIF0 Mask              */
+
+#define EPWM_INTSTS0_ZIF1_Pos             (1)                                               /*!< EPWM_T::INTSTS0: ZIF1 Position          */
+#define EPWM_INTSTS0_ZIF1_Msk             (0x1ul << EPWM_INTSTS0_ZIF1_Pos)                   /*!< EPWM_T::INTSTS0: ZIF1 Mask              */
+
+#define EPWM_INTSTS0_ZIF2_Pos             (2)                                               /*!< EPWM_T::INTSTS0: ZIF2 Position          */
+#define EPWM_INTSTS0_ZIF2_Msk             (0x1ul << EPWM_INTSTS0_ZIF2_Pos)                   /*!< EPWM_T::INTSTS0: ZIF2 Mask              */
+
+#define EPWM_INTSTS0_ZIF3_Pos             (3)                                               /*!< EPWM_T::INTSTS0: ZIF3 Position          */
+#define EPWM_INTSTS0_ZIF3_Msk             (0x1ul << EPWM_INTSTS0_ZIF3_Pos)                   /*!< EPWM_T::INTSTS0: ZIF3 Mask              */
+
+#define EPWM_INTSTS0_ZIF4_Pos             (4)                                               /*!< EPWM_T::INTSTS0: ZIF4 Position          */
+#define EPWM_INTSTS0_ZIF4_Msk             (0x1ul << EPWM_INTSTS0_ZIF4_Pos)                   /*!< EPWM_T::INTSTS0: ZIF4 Mask              */
+
+#define EPWM_INTSTS0_ZIF5_Pos             (5)                                               /*!< EPWM_T::INTSTS0: ZIF5 Position          */
+#define EPWM_INTSTS0_ZIF5_Msk             (0x1ul << EPWM_INTSTS0_ZIF5_Pos)                   /*!< EPWM_T::INTSTS0: ZIF5 Mask              */
+
+#define EPWM_INTSTS0_PIF0_Pos             (8)                                               /*!< EPWM_T::INTSTS0: PIF0 Position          */
+#define EPWM_INTSTS0_PIF0_Msk             (0x1ul << EPWM_INTSTS0_PIF0_Pos)                   /*!< EPWM_T::INTSTS0: PIF0 Mask              */
+
+#define EPWM_INTSTS0_PIF1_Pos             (9)                                               /*!< EPWM_T::INTSTS0: PIF1 Position          */
+#define EPWM_INTSTS0_PIF1_Msk             (0x1ul << EPWM_INTSTS0_PIF1_Pos)                   /*!< EPWM_T::INTSTS0: PIF1 Mask              */
+
+#define EPWM_INTSTS0_PIF2_Pos             (10)                                              /*!< EPWM_T::INTSTS0: PIF2 Position          */
+#define EPWM_INTSTS0_PIF2_Msk             (0x1ul << EPWM_INTSTS0_PIF2_Pos)                   /*!< EPWM_T::INTSTS0: PIF2 Mask              */
+
+#define EPWM_INTSTS0_PIF3_Pos             (11)                                              /*!< EPWM_T::INTSTS0: PIF3 Position          */
+#define EPWM_INTSTS0_PIF3_Msk             (0x1ul << EPWM_INTSTS0_PIF3_Pos)                   /*!< EPWM_T::INTSTS0: PIF3 Mask              */
+
+#define EPWM_INTSTS0_PIF4_Pos             (12)                                              /*!< EPWM_T::INTSTS0: PIF4 Position          */
+#define EPWM_INTSTS0_PIF4_Msk             (0x1ul << EPWM_INTSTS0_PIF4_Pos)                   /*!< EPWM_T::INTSTS0: PIF4 Mask              */
+
+#define EPWM_INTSTS0_PIF5_Pos             (13)                                              /*!< EPWM_T::INTSTS0: PIF5 Position          */
+#define EPWM_INTSTS0_PIF5_Msk             (0x1ul << EPWM_INTSTS0_PIF5_Pos)                   /*!< EPWM_T::INTSTS0: PIF5 Mask              */
+
+#define EPWM_INTSTS0_CMPUIF0_Pos          (16)                                              /*!< EPWM_T::INTSTS0: CMPUIF0 Position       */
+#define EPWM_INTSTS0_CMPUIF0_Msk          (0x1ul << EPWM_INTSTS0_CMPUIF0_Pos)                /*!< EPWM_T::INTSTS0: CMPUIF0 Mask           */
+
+#define EPWM_INTSTS0_CMPUIF1_Pos          (17)                                              /*!< EPWM_T::INTSTS0: CMPUIF1 Position       */
+#define EPWM_INTSTS0_CMPUIF1_Msk          (0x1ul << EPWM_INTSTS0_CMPUIF1_Pos)                /*!< EPWM_T::INTSTS0: CMPUIF1 Mask           */
+
+#define EPWM_INTSTS0_CMPUIF2_Pos          (18)                                              /*!< EPWM_T::INTSTS0: CMPUIF2 Position       */
+#define EPWM_INTSTS0_CMPUIF2_Msk          (0x1ul << EPWM_INTSTS0_CMPUIF2_Pos)                /*!< EPWM_T::INTSTS0: CMPUIF2 Mask           */
+
+#define EPWM_INTSTS0_CMPUIF3_Pos          (19)                                              /*!< EPWM_T::INTSTS0: CMPUIF3 Position       */
+#define EPWM_INTSTS0_CMPUIF3_Msk          (0x1ul << EPWM_INTSTS0_CMPUIF3_Pos)                /*!< EPWM_T::INTSTS0: CMPUIF3 Mask           */
+
+#define EPWM_INTSTS0_CMPUIF4_Pos          (20)                                              /*!< EPWM_T::INTSTS0: CMPUIF4 Position       */
+#define EPWM_INTSTS0_CMPUIF4_Msk          (0x1ul << EPWM_INTSTS0_CMPUIF4_Pos)                /*!< EPWM_T::INTSTS0: CMPUIF4 Mask           */
+
+#define EPWM_INTSTS0_CMPUIF5_Pos          (21)                                              /*!< EPWM_T::INTSTS0: CMPUIF5 Position       */
+#define EPWM_INTSTS0_CMPUIF5_Msk          (0x1ul << EPWM_INTSTS0_CMPUIF5_Pos)                /*!< EPWM_T::INTSTS0: CMPUIF5 Mask           */
+
+#define EPWM_INTSTS0_CMPDIF0_Pos          (24)                                              /*!< EPWM_T::INTSTS0: CMPDIF0 Position       */
+#define EPWM_INTSTS0_CMPDIF0_Msk          (0x1ul << EPWM_INTSTS0_CMPDIF0_Pos)                /*!< EPWM_T::INTSTS0: CMPDIF0 Mask           */
+
+#define EPWM_INTSTS0_CMPDIF1_Pos          (25)                                              /*!< EPWM_T::INTSTS0: CMPDIF1 Position       */
+#define EPWM_INTSTS0_CMPDIF1_Msk          (0x1ul << EPWM_INTSTS0_CMPDIF1_Pos)                /*!< EPWM_T::INTSTS0: CMPDIF1 Mask           */
+
+#define EPWM_INTSTS0_CMPDIF2_Pos          (26)                                              /*!< EPWM_T::INTSTS0: CMPDIF2 Position       */
+#define EPWM_INTSTS0_CMPDIF2_Msk          (0x1ul << EPWM_INTSTS0_CMPDIF2_Pos)                /*!< EPWM_T::INTSTS0: CMPDIF2 Mask           */
+
+#define EPWM_INTSTS0_CMPDIF3_Pos          (27)                                              /*!< EPWM_T::INTSTS0: CMPDIF3 Position       */
+#define EPWM_INTSTS0_CMPDIF3_Msk          (0x1ul << EPWM_INTSTS0_CMPDIF3_Pos)                /*!< EPWM_T::INTSTS0: CMPDIF3 Mask           */
+
+#define EPWM_INTSTS0_CMPDIF4_Pos          (28)                                              /*!< EPWM_T::INTSTS0: CMPDIF4 Position       */
+#define EPWM_INTSTS0_CMPDIF4_Msk          (0x1ul << EPWM_INTSTS0_CMPDIF4_Pos)                /*!< EPWM_T::INTSTS0: CMPDIF4 Mask           */
+
+#define EPWM_INTSTS0_CMPDIF5_Pos          (29)                                              /*!< EPWM_T::INTSTS0: CMPDIF5 Position       */
+#define EPWM_INTSTS0_CMPDIF5_Msk          (0x1ul << EPWM_INTSTS0_CMPDIF5_Pos)                /*!< EPWM_T::INTSTS0: CMPDIF5 Mask           */
+
+#define EPWM_INTSTS1_BRKEIF0_Pos          (0)                                               /*!< EPWM_T::INTSTS1: BRKEIF0 Position       */
+#define EPWM_INTSTS1_BRKEIF0_Msk          (0x1ul << EPWM_INTSTS1_BRKEIF0_Pos)                /*!< EPWM_T::INTSTS1: BRKEIF0 Mask           */
+
+#define EPWM_INTSTS1_BRKEIF1_Pos          (1)                                               /*!< EPWM_T::INTSTS1: BRKEIF1 Position       */
+#define EPWM_INTSTS1_BRKEIF1_Msk          (0x1ul << EPWM_INTSTS1_BRKEIF1_Pos)                /*!< EPWM_T::INTSTS1: BRKEIF1 Mask           */
+
+#define EPWM_INTSTS1_BRKEIF2_Pos          (2)                                               /*!< EPWM_T::INTSTS1: BRKEIF2 Position       */
+#define EPWM_INTSTS1_BRKEIF2_Msk          (0x1ul << EPWM_INTSTS1_BRKEIF2_Pos)                /*!< EPWM_T::INTSTS1: BRKEIF2 Mask           */
+
+#define EPWM_INTSTS1_BRKEIF3_Pos          (3)                                               /*!< EPWM_T::INTSTS1: BRKEIF3 Position       */
+#define EPWM_INTSTS1_BRKEIF3_Msk          (0x1ul << EPWM_INTSTS1_BRKEIF3_Pos)                /*!< EPWM_T::INTSTS1: BRKEIF3 Mask           */
+
+#define EPWM_INTSTS1_BRKEIF4_Pos          (4)                                               /*!< EPWM_T::INTSTS1: BRKEIF4 Position       */
+#define EPWM_INTSTS1_BRKEIF4_Msk          (0x1ul << EPWM_INTSTS1_BRKEIF4_Pos)                /*!< EPWM_T::INTSTS1: BRKEIF4 Mask           */
+
+#define EPWM_INTSTS1_BRKEIF5_Pos          (5)                                               /*!< EPWM_T::INTSTS1: BRKEIF5 Position       */
+#define EPWM_INTSTS1_BRKEIF5_Msk          (0x1ul << EPWM_INTSTS1_BRKEIF5_Pos)                /*!< EPWM_T::INTSTS1: BRKEIF5 Mask           */
+
+#define EPWM_INTSTS1_BRKLIF0_Pos          (8)                                               /*!< EPWM_T::INTSTS1: BRKLIF0 Position       */
+#define EPWM_INTSTS1_BRKLIF0_Msk          (0x1ul << EPWM_INTSTS1_BRKLIF0_Pos)                /*!< EPWM_T::INTSTS1: BRKLIF0 Mask           */
+
+#define EPWM_INTSTS1_BRKLIF1_Pos          (9)                                               /*!< EPWM_T::INTSTS1: BRKLIF1 Position       */
+#define EPWM_INTSTS1_BRKLIF1_Msk          (0x1ul << EPWM_INTSTS1_BRKLIF1_Pos)                /*!< EPWM_T::INTSTS1: BRKLIF1 Mask           */
+
+#define EPWM_INTSTS1_BRKLIF2_Pos          (10)                                              /*!< EPWM_T::INTSTS1: BRKLIF2 Position       */
+#define EPWM_INTSTS1_BRKLIF2_Msk          (0x1ul << EPWM_INTSTS1_BRKLIF2_Pos)                /*!< EPWM_T::INTSTS1: BRKLIF2 Mask           */
+
+#define EPWM_INTSTS1_BRKLIF3_Pos          (11)                                              /*!< EPWM_T::INTSTS1: BRKLIF3 Position       */
+#define EPWM_INTSTS1_BRKLIF3_Msk          (0x1ul << EPWM_INTSTS1_BRKLIF3_Pos)                /*!< EPWM_T::INTSTS1: BRKLIF3 Mask           */
+
+#define EPWM_INTSTS1_BRKLIF4_Pos          (12)                                              /*!< EPWM_T::INTSTS1: BRKLIF4 Position       */
+#define EPWM_INTSTS1_BRKLIF4_Msk          (0x1ul << EPWM_INTSTS1_BRKLIF4_Pos)                /*!< EPWM_T::INTSTS1: BRKLIF4 Mask           */
+
+#define EPWM_INTSTS1_BRKLIF5_Pos          (13)                                              /*!< EPWM_T::INTSTS1: BRKLIF5 Position       */
+#define EPWM_INTSTS1_BRKLIF5_Msk          (0x1ul << EPWM_INTSTS1_BRKLIF5_Pos)                /*!< EPWM_T::INTSTS1: BRKLIF5 Mask           */
+
+#define EPWM_INTSTS1_BRKESTS0_Pos         (16)                                              /*!< EPWM_T::INTSTS1: BRKESTS0 Position      */
+#define EPWM_INTSTS1_BRKESTS0_Msk         (0x1ul << EPWM_INTSTS1_BRKESTS0_Pos)               /*!< EPWM_T::INTSTS1: BRKESTS0 Mask          */
+
+#define EPWM_INTSTS1_BRKESTS1_Pos         (17)                                              /*!< EPWM_T::INTSTS1: BRKESTS1 Position      */
+#define EPWM_INTSTS1_BRKESTS1_Msk         (0x1ul << EPWM_INTSTS1_BRKESTS1_Pos)               /*!< EPWM_T::INTSTS1: BRKESTS1 Mask          */
+
+#define EPWM_INTSTS1_BRKESTS2_Pos         (18)                                              /*!< EPWM_T::INTSTS1: BRKESTS2 Position      */
+#define EPWM_INTSTS1_BRKESTS2_Msk         (0x1ul << EPWM_INTSTS1_BRKESTS2_Pos)               /*!< EPWM_T::INTSTS1: BRKESTS2 Mask          */
+
+#define EPWM_INTSTS1_BRKESTS3_Pos         (19)                                              /*!< EPWM_T::INTSTS1: BRKESTS3 Position      */
+#define EPWM_INTSTS1_BRKESTS3_Msk         (0x1ul << EPWM_INTSTS1_BRKESTS3_Pos)               /*!< EPWM_T::INTSTS1: BRKESTS3 Mask          */
+
+#define EPWM_INTSTS1_BRKESTS4_Pos         (20)                                              /*!< EPWM_T::INTSTS1: BRKESTS4 Position      */
+#define EPWM_INTSTS1_BRKESTS4_Msk         (0x1ul << EPWM_INTSTS1_BRKESTS4_Pos)               /*!< EPWM_T::INTSTS1: BRKESTS4 Mask          */
+
+#define EPWM_INTSTS1_BRKESTS5_Pos         (21)                                              /*!< EPWM_T::INTSTS1: BRKESTS5 Position      */
+#define EPWM_INTSTS1_BRKESTS5_Msk         (0x1ul << EPWM_INTSTS1_BRKESTS5_Pos)               /*!< EPWM_T::INTSTS1: BRKESTS5 Mask          */
+
+#define EPWM_INTSTS1_BRKLSTS0_Pos         (24)                                              /*!< EPWM_T::INTSTS1: BRKLSTS0 Position      */
+#define EPWM_INTSTS1_BRKLSTS0_Msk         (0x1ul << EPWM_INTSTS1_BRKLSTS0_Pos)               /*!< EPWM_T::INTSTS1: BRKLSTS0 Mask          */
+
+#define EPWM_INTSTS1_BRKLSTS1_Pos         (25)                                              /*!< EPWM_T::INTSTS1: BRKLSTS1 Position      */
+#define EPWM_INTSTS1_BRKLSTS1_Msk         (0x1ul << EPWM_INTSTS1_BRKLSTS1_Pos)               /*!< EPWM_T::INTSTS1: BRKLSTS1 Mask          */
+
+#define EPWM_INTSTS1_BRKLSTS2_Pos         (26)                                              /*!< EPWM_T::INTSTS1: BRKLSTS2 Position      */
+#define EPWM_INTSTS1_BRKLSTS2_Msk         (0x1ul << EPWM_INTSTS1_BRKLSTS2_Pos)               /*!< EPWM_T::INTSTS1: BRKLSTS2 Mask          */
+
+#define EPWM_INTSTS1_BRKLSTS3_Pos         (27)                                              /*!< EPWM_T::INTSTS1: BRKLSTS3 Position      */
+#define EPWM_INTSTS1_BRKLSTS3_Msk         (0x1ul << EPWM_INTSTS1_BRKLSTS3_Pos)               /*!< EPWM_T::INTSTS1: BRKLSTS3 Mask          */
+
+#define EPWM_INTSTS1_BRKLSTS4_Pos         (28)                                              /*!< EPWM_T::INTSTS1: BRKLSTS4 Position      */
+#define EPWM_INTSTS1_BRKLSTS4_Msk         (0x1ul << EPWM_INTSTS1_BRKLSTS4_Pos)               /*!< EPWM_T::INTSTS1: BRKLSTS4 Mask          */
+
+#define EPWM_INTSTS1_BRKLSTS5_Pos         (29)                                              /*!< EPWM_T::INTSTS1: BRKLSTS5 Position      */
+#define EPWM_INTSTS1_BRKLSTS5_Msk         (0x1ul << EPWM_INTSTS1_BRKLSTS5_Pos)               /*!< EPWM_T::INTSTS1: BRKLSTS5 Mask          */
+
+#define EPWM_DACTRGEN_ZTE0_Pos            (0)                                               /*!< EPWM_T::DACTRGEN: ZTE0 Position         */
+#define EPWM_DACTRGEN_ZTE0_Msk            (0x1ul << EPWM_DACTRGEN_ZTE0_Pos)                  /*!< EPWM_T::DACTRGEN: ZTE0 Mask             */
+
+#define EPWM_DACTRGEN_ZTE1_Pos            (1)                                               /*!< EPWM_T::DACTRGEN: ZTE1 Position         */
+#define EPWM_DACTRGEN_ZTE1_Msk            (0x1ul << EPWM_DACTRGEN_ZTE1_Pos)                  /*!< EPWM_T::DACTRGEN: ZTE1 Mask             */
+
+#define EPWM_DACTRGEN_ZTE2_Pos            (2)                                               /*!< EPWM_T::DACTRGEN: ZTE2 Position         */
+#define EPWM_DACTRGEN_ZTE2_Msk            (0x1ul << EPWM_DACTRGEN_ZTE2_Pos)                  /*!< EPWM_T::DACTRGEN: ZTE2 Mask             */
+
+#define EPWM_DACTRGEN_ZTE3_Pos            (3)                                               /*!< EPWM_T::DACTRGEN: ZTE3 Position         */
+#define EPWM_DACTRGEN_ZTE3_Msk            (0x1ul << EPWM_DACTRGEN_ZTE3_Pos)                  /*!< EPWM_T::DACTRGEN: ZTE3 Mask             */
+
+#define EPWM_DACTRGEN_ZTE4_Pos            (4)                                               /*!< EPWM_T::DACTRGEN: ZTE4 Position         */
+#define EPWM_DACTRGEN_ZTE4_Msk            (0x1ul << EPWM_DACTRGEN_ZTE4_Pos)                  /*!< EPWM_T::DACTRGEN: ZTE4 Mask             */
+
+#define EPWM_DACTRGEN_ZTE5_Pos            (5)                                               /*!< EPWM_T::DACTRGEN: ZTE5 Position         */
+#define EPWM_DACTRGEN_ZTE5_Msk            (0x1ul << EPWM_DACTRGEN_ZTE5_Pos)                  /*!< EPWM_T::DACTRGEN: ZTE5 Mask             */
+
+#define EPWM_DACTRGEN_PTE0_Pos            (8)                                               /*!< EPWM_T::DACTRGEN: PTE0 Position         */
+#define EPWM_DACTRGEN_PTE0_Msk            (0x1ul << EPWM_DACTRGEN_PTE0_Pos)                  /*!< EPWM_T::DACTRGEN: PTE0 Mask             */
+
+#define EPWM_DACTRGEN_PTE1_Pos            (9)                                               /*!< EPWM_T::DACTRGEN: PTE1 Position         */
+#define EPWM_DACTRGEN_PTE1_Msk            (0x1ul << EPWM_DACTRGEN_PTE1_Pos)                  /*!< EPWM_T::DACTRGEN: PTE1 Mask             */
+
+#define EPWM_DACTRGEN_PTE2_Pos            (10)                                              /*!< EPWM_T::DACTRGEN: PTE2 Position         */
+#define EPWM_DACTRGEN_PTE2_Msk            (0x1ul << EPWM_DACTRGEN_PTE2_Pos)                  /*!< EPWM_T::DACTRGEN: PTE2 Mask             */
+
+#define EPWM_DACTRGEN_PTE3_Pos            (11)                                              /*!< EPWM_T::DACTRGEN: PTE3 Position         */
+#define EPWM_DACTRGEN_PTE3_Msk            (0x1ul << EPWM_DACTRGEN_PTE3_Pos)                  /*!< EPWM_T::DACTRGEN: PTE3 Mask             */
+
+#define EPWM_DACTRGEN_PTE4_Pos            (12)                                              /*!< EPWM_T::DACTRGEN: PTE4 Position         */
+#define EPWM_DACTRGEN_PTE4_Msk            (0x1ul << EPWM_DACTRGEN_PTE4_Pos)                  /*!< EPWM_T::DACTRGEN: PTE4 Mask             */
+
+#define EPWM_DACTRGEN_PTE5_Pos            (13)                                              /*!< EPWM_T::DACTRGEN: PTE5 Position         */
+#define EPWM_DACTRGEN_PTE5_Msk            (0x1ul << EPWM_DACTRGEN_PTE5_Pos)                  /*!< EPWM_T::DACTRGEN: PTE5 Mask             */
+
+#define EPWM_DACTRGEN_CUTRGE0_Pos         (16)                                              /*!< EPWM_T::DACTRGEN: CUTRGE0 Position      */
+#define EPWM_DACTRGEN_CUTRGE0_Msk         (0x1ul << EPWM_DACTRGEN_CUTRGE0_Pos)               /*!< EPWM_T::DACTRGEN: CUTRGE0 Mask          */
+
+#define EPWM_DACTRGEN_CUTRGE1_Pos         (17)                                              /*!< EPWM_T::DACTRGEN: CUTRGE1 Position      */
+#define EPWM_DACTRGEN_CUTRGE1_Msk         (0x1ul << EPWM_DACTRGEN_CUTRGE1_Pos)               /*!< EPWM_T::DACTRGEN: CUTRGE1 Mask          */
+
+#define EPWM_DACTRGEN_CUTRGE2_Pos         (18)                                              /*!< EPWM_T::DACTRGEN: CUTRGE2 Position      */
+#define EPWM_DACTRGEN_CUTRGE2_Msk         (0x1ul << EPWM_DACTRGEN_CUTRGE2_Pos)               /*!< EPWM_T::DACTRGEN: CUTRGE2 Mask          */
+
+#define EPWM_DACTRGEN_CUTRGE3_Pos         (19)                                              /*!< EPWM_T::DACTRGEN: CUTRGE3 Position      */
+#define EPWM_DACTRGEN_CUTRGE3_Msk         (0x1ul << EPWM_DACTRGEN_CUTRGE3_Pos)               /*!< EPWM_T::DACTRGEN: CUTRGE3 Mask          */
+
+#define EPWM_DACTRGEN_CUTRGE4_Pos         (20)                                              /*!< EPWM_T::DACTRGEN: CUTRGE4 Position      */
+#define EPWM_DACTRGEN_CUTRGE4_Msk         (0x1ul << EPWM_DACTRGEN_CUTRGE4_Pos)               /*!< EPWM_T::DACTRGEN: CUTRGE4 Mask          */
+
+#define EPWM_DACTRGEN_CUTRGE5_Pos         (21)                                              /*!< EPWM_T::DACTRGEN: CUTRGE5 Position      */
+#define EPWM_DACTRGEN_CUTRGE5_Msk         (0x1ul << EPWM_DACTRGEN_CUTRGE5_Pos)               /*!< EPWM_T::DACTRGEN: CUTRGE5 Mask          */
+
+#define EPWM_DACTRGEN_CDTRGE0_Pos         (24)                                              /*!< EPWM_T::DACTRGEN: CDTRGE0 Position      */
+#define EPWM_DACTRGEN_CDTRGE0_Msk         (0x1ul << EPWM_DACTRGEN_CDTRGE0_Pos)               /*!< EPWM_T::DACTRGEN: CDTRGE0 Mask          */
+
+#define EPWM_DACTRGEN_CDTRGE1_Pos         (25)                                              /*!< EPWM_T::DACTRGEN: CDTRGE1 Position      */
+#define EPWM_DACTRGEN_CDTRGE1_Msk         (0x1ul << EPWM_DACTRGEN_CDTRGE1_Pos)               /*!< EPWM_T::DACTRGEN: CDTRGE1 Mask          */
+
+#define EPWM_DACTRGEN_CDTRGE2_Pos         (26)                                              /*!< EPWM_T::DACTRGEN: CDTRGE2 Position      */
+#define EPWM_DACTRGEN_CDTRGE2_Msk         (0x1ul << EPWM_DACTRGEN_CDTRGE2_Pos)               /*!< EPWM_T::DACTRGEN: CDTRGE2 Mask          */
+
+#define EPWM_DACTRGEN_CDTRGE3_Pos         (27)                                              /*!< EPWM_T::DACTRGEN: CDTRGE3 Position      */
+#define EPWM_DACTRGEN_CDTRGE3_Msk         (0x1ul << EPWM_DACTRGEN_CDTRGE3_Pos)               /*!< EPWM_T::DACTRGEN: CDTRGE3 Mask          */
+
+#define EPWM_DACTRGEN_CDTRGE4_Pos         (28)                                              /*!< EPWM_T::DACTRGEN: CDTRGE4 Position      */
+#define EPWM_DACTRGEN_CDTRGE4_Msk         (0x1ul << EPWM_DACTRGEN_CDTRGE4_Pos)               /*!< EPWM_T::DACTRGEN: CDTRGE4 Mask          */
+
+#define EPWM_DACTRGEN_CDTRGE5_Pos         (29)                                              /*!< EPWM_T::DACTRGEN: CDTRGE5 Position      */
+#define EPWM_DACTRGEN_CDTRGE5_Msk         (0x1ul << EPWM_DACTRGEN_CDTRGE5_Pos)               /*!< EPWM_T::DACTRGEN: CDTRGE5 Mask          */
+
+#define EPWM_EADCTS0_TRGSEL0_Pos          (0)                                               /*!< EPWM_T::EADCTS0: TRGSEL0 Position       */
+#define EPWM_EADCTS0_TRGSEL0_Msk          (0xful << EPWM_EADCTS0_TRGSEL0_Pos)                /*!< EPWM_T::EADCTS0: TRGSEL0 Mask           */
+
+#define EPWM_EADCTS0_TRGEN0_Pos           (7)                                               /*!< EPWM_T::EADCTS0: TRGEN0 Position        */
+#define EPWM_EADCTS0_TRGEN0_Msk           (0x1ul << EPWM_EADCTS0_TRGEN0_Pos)                 /*!< EPWM_T::EADCTS0: TRGEN0 Mask            */
+
+#define EPWM_EADCTS0_TRGSEL1_Pos          (8)                                               /*!< EPWM_T::EADCTS0: TRGSEL1 Position       */
+#define EPWM_EADCTS0_TRGSEL1_Msk          (0xful << EPWM_EADCTS0_TRGSEL1_Pos)                /*!< EPWM_T::EADCTS0: TRGSEL1 Mask           */
+
+#define EPWM_EADCTS0_TRGEN1_Pos           (15)                                              /*!< EPWM_T::EADCTS0: TRGEN1 Position        */
+#define EPWM_EADCTS0_TRGEN1_Msk           (0x1ul << EPWM_EADCTS0_TRGEN1_Pos)                 /*!< EPWM_T::EADCTS0: TRGEN1 Mask            */
+
+#define EPWM_EADCTS0_TRGSEL2_Pos          (16)                                              /*!< EPWM_T::EADCTS0: TRGSEL2 Position       */
+#define EPWM_EADCTS0_TRGSEL2_Msk          (0xful << EPWM_EADCTS0_TRGSEL2_Pos)                /*!< EPWM_T::EADCTS0: TRGSEL2 Mask           */
+
+#define EPWM_EADCTS0_TRGEN2_Pos           (23)                                              /*!< EPWM_T::EADCTS0: TRGEN2 Position        */
+#define EPWM_EADCTS0_TRGEN2_Msk           (0x1ul << EPWM_EADCTS0_TRGEN2_Pos)                 /*!< EPWM_T::EADCTS0: TRGEN2 Mask            */
+
+#define EPWM_EADCTS0_TRGSEL3_Pos          (24)                                              /*!< EPWM_T::EADCTS0: TRGSEL3 Position       */
+#define EPWM_EADCTS0_TRGSEL3_Msk          (0xful << EPWM_EADCTS0_TRGSEL3_Pos)                /*!< EPWM_T::EADCTS0: TRGSEL3 Mask           */
+
+#define EPWM_EADCTS0_TRGEN3_Pos           (31)                                              /*!< EPWM_T::EADCTS0: TRGEN3 Position        */
+#define EPWM_EADCTS0_TRGEN3_Msk           (0x1ul << EPWM_EADCTS0_TRGEN3_Pos)                 /*!< EPWM_T::EADCTS0: TRGEN3 Mask            */
+
+#define EPWM_EADCTS1_TRGSEL4_Pos          (0)                                               /*!< EPWM_T::EADCTS1: TRGSEL4 Position       */
+#define EPWM_EADCTS1_TRGSEL4_Msk          (0xful << EPWM_EADCTS1_TRGSEL4_Pos)                /*!< EPWM_T::EADCTS1: TRGSEL4 Mask           */
+
+#define EPWM_EADCTS1_TRGEN4_Pos           (7)                                               /*!< EPWM_T::EADCTS1: TRGEN4 Position        */
+#define EPWM_EADCTS1_TRGEN4_Msk           (0x1ul << EPWM_EADCTS1_TRGEN4_Pos)                 /*!< EPWM_T::EADCTS1: TRGEN4 Mask            */
+
+#define EPWM_EADCTS1_TRGSEL5_Pos          (8)                                               /*!< EPWM_T::EADCTS1: TRGSEL5 Position       */
+#define EPWM_EADCTS1_TRGSEL5_Msk          (0xful << EPWM_EADCTS1_TRGSEL5_Pos)                /*!< EPWM_T::EADCTS1: TRGSEL5 Mask           */
+
+#define EPWM_EADCTS1_TRGEN5_Pos           (15)                                              /*!< EPWM_T::EADCTS1: TRGEN5 Position        */
+#define EPWM_EADCTS1_TRGEN5_Msk           (0x1ul << EPWM_EADCTS1_TRGEN5_Pos)                 /*!< EPWM_T::EADCTS1: TRGEN5 Mask            */
+
+#define EPWM_FTCMPDAT0_1_FTCMP_Pos        (0)                                               /*!< EPWM_T::FTCMPDAT0_1: FTCMP Position     */
+#define EPWM_FTCMPDAT0_1_FTCMP_Msk        (0xfffful << EPWM_FTCMPDAT0_1_FTCMP_Pos)           /*!< EPWM_T::FTCMPDAT0_1: FTCMP Mask         */
+
+#define EPWM_FTCMPDAT2_3_FTCMP_Pos        (0)                                               /*!< EPWM_T::FTCMPDAT2_3: FTCMP Position     */
+#define EPWM_FTCMPDAT2_3_FTCMP_Msk        (0xfffful << EPWM_FTCMPDAT2_3_FTCMP_Pos)           /*!< EPWM_T::FTCMPDAT2_3: FTCMP Mask         */
+
+#define EPWM_FTCMPDAT4_5_FTCMP_Pos        (0)                                               /*!< EPWM_T::FTCMPDAT4_5: FTCMP Position     */
+#define EPWM_FTCMPDAT4_5_FTCMP_Msk        (0xfffful << EPWM_FTCMPDAT4_5_FTCMP_Pos)           /*!< EPWM_T::FTCMPDAT4_5: FTCMP Mask         */
+
+#define EPWM_SSCTL_SSEN0_Pos              (0)                                               /*!< EPWM_T::SSCTL: SSEN0 Position           */
+#define EPWM_SSCTL_SSEN0_Msk              (0x1ul << EPWM_SSCTL_SSEN0_Pos)                    /*!< EPWM_T::SSCTL: SSEN0 Mask               */
+
+#define EPWM_SSCTL_SSEN1_Pos              (1)                                               /*!< EPWM_T::SSCTL: SSEN1 Position           */
+#define EPWM_SSCTL_SSEN1_Msk              (0x1ul << EPWM_SSCTL_SSEN1_Pos)                    /*!< EPWM_T::SSCTL: SSEN1 Mask               */
+
+#define EPWM_SSCTL_SSEN2_Pos              (2)                                               /*!< EPWM_T::SSCTL: SSEN2 Position           */
+#define EPWM_SSCTL_SSEN2_Msk              (0x1ul << EPWM_SSCTL_SSEN2_Pos)                    /*!< EPWM_T::SSCTL: SSEN2 Mask               */
+
+#define EPWM_SSCTL_SSEN3_Pos              (3)                                               /*!< EPWM_T::SSCTL: SSEN3 Position           */
+#define EPWM_SSCTL_SSEN3_Msk              (0x1ul << EPWM_SSCTL_SSEN3_Pos)                    /*!< EPWM_T::SSCTL: SSEN3 Mask               */
+
+#define EPWM_SSCTL_SSEN4_Pos              (4)                                               /*!< EPWM_T::SSCTL: SSEN4 Position           */
+#define EPWM_SSCTL_SSEN4_Msk              (0x1ul << EPWM_SSCTL_SSEN4_Pos)                    /*!< EPWM_T::SSCTL: SSEN4 Mask               */
+
+#define EPWM_SSCTL_SSEN5_Pos              (5)                                               /*!< EPWM_T::SSCTL: SSEN5 Position           */
+#define EPWM_SSCTL_SSEN5_Msk              (0x1ul << EPWM_SSCTL_SSEN5_Pos)                    /*!< EPWM_T::SSCTL: SSEN5 Mask               */
+
+#define EPWM_SSCTL_SSRC_Pos               (8)                                               /*!< EPWM_T::SSCTL: SSRC Position            */
+#define EPWM_SSCTL_SSRC_Msk               (0x3ul << EPWM_SSCTL_SSRC_Pos)                     /*!< EPWM_T::SSCTL: SSRC Mask                */
+
+#define EPWM_SSTRG_CNTSEN_Pos             (0)                                               /*!< EPWM_T::SSTRG: CNTSEN Position          */
+#define EPWM_SSTRG_CNTSEN_Msk             (0x1ul << EPWM_SSTRG_CNTSEN_Pos)                   /*!< EPWM_T::SSTRG: CNTSEN Mask              */
+
+#define EPWM_LEBCTL_LEBEN_Pos             (0)                                               /*!< EPWM_T::LEBCTL: LEBEN Position          */
+#define EPWM_LEBCTL_LEBEN_Msk             (0x1ul << EPWM_LEBCTL_LEBEN_Pos)                   /*!< EPWM_T::LEBCTL: LEBEN Mask              */
+
+#define EPWM_LEBCTL_SRCEN0_Pos            (8)                                               /*!< EPWM_T::LEBCTL: SRCEN0 Position         */
+#define EPWM_LEBCTL_SRCEN0_Msk            (0x1ul << EPWM_LEBCTL_SRCEN0_Pos)                  /*!< EPWM_T::LEBCTL: SRCEN0 Mask             */
+
+#define EPWM_LEBCTL_SRCEN2_Pos            (9)                                               /*!< EPWM_T::LEBCTL: SRCEN2 Position         */
+#define EPWM_LEBCTL_SRCEN2_Msk            (0x1ul << EPWM_LEBCTL_SRCEN2_Pos)                  /*!< EPWM_T::LEBCTL: SRCEN2 Mask             */
+
+#define EPWM_LEBCTL_SRCEN4_Pos            (10)                                              /*!< EPWM_T::LEBCTL: SRCEN4 Position         */
+#define EPWM_LEBCTL_SRCEN4_Msk            (0x1ul << EPWM_LEBCTL_SRCEN4_Pos)                  /*!< EPWM_T::LEBCTL: SRCEN4 Mask             */
+
+#define EPWM_LEBCTL_TRGTYPE_Pos           (16)                                              /*!< EPWM_T::LEBCTL: TRGTYPE Position        */
+#define EPWM_LEBCTL_TRGTYPE_Msk           (0x3ul << EPWM_LEBCTL_TRGTYPE_Pos)                 /*!< EPWM_T::LEBCTL: TRGTYPE Mask            */
+
+#define EPWM_LEBCNT_LEBCNT_Pos            (0)                                               /*!< EPWM_T::LEBCNT: LEBCNT Position         */
+#define EPWM_LEBCNT_LEBCNT_Msk            (0x1fful << EPWM_LEBCNT_LEBCNT_Pos)                /*!< EPWM_T::LEBCNT: LEBCNT Mask             */
+
+#define EPWM_STATUS_CNTMAXF0_Pos          (0)                                               /*!< EPWM_T::STATUS: CNTMAXF0 Position       */
+#define EPWM_STATUS_CNTMAXF0_Msk          (0x1ul << EPWM_STATUS_CNTMAXF0_Pos)                /*!< EPWM_T::STATUS: CNTMAXF0 Mask           */
+
+#define EPWM_STATUS_CNTMAXF1_Pos          (1)                                               /*!< EPWM_T::STATUS: CNTMAXF1 Position       */
+#define EPWM_STATUS_CNTMAXF1_Msk          (0x1ul << EPWM_STATUS_CNTMAXF1_Pos)                /*!< EPWM_T::STATUS: CNTMAXF1 Mask           */
+
+#define EPWM_STATUS_CNTMAXF2_Pos          (2)                                               /*!< EPWM_T::STATUS: CNTMAXF2 Position       */
+#define EPWM_STATUS_CNTMAXF2_Msk          (0x1ul << EPWM_STATUS_CNTMAXF2_Pos)                /*!< EPWM_T::STATUS: CNTMAXF2 Mask           */
+
+#define EPWM_STATUS_CNTMAXF3_Pos          (3)                                               /*!< EPWM_T::STATUS: CNTMAXF3 Position       */
+#define EPWM_STATUS_CNTMAXF3_Msk          (0x1ul << EPWM_STATUS_CNTMAXF3_Pos)                /*!< EPWM_T::STATUS: CNTMAXF3 Mask           */
+
+#define EPWM_STATUS_CNTMAXF4_Pos          (4)                                               /*!< EPWM_T::STATUS: CNTMAXF4 Position       */
+#define EPWM_STATUS_CNTMAXF4_Msk          (0x1ul << EPWM_STATUS_CNTMAXF4_Pos)                /*!< EPWM_T::STATUS: CNTMAXF4 Mask           */
+
+#define EPWM_STATUS_CNTMAXF5_Pos          (5)                                               /*!< EPWM_T::STATUS: CNTMAXF5 Position       */
+#define EPWM_STATUS_CNTMAXF5_Msk          (0x1ul << EPWM_STATUS_CNTMAXF5_Pos)                /*!< EPWM_T::STATUS: CNTMAXF5 Mask           */
+
+#define EPWM_STATUS_SYNCINF0_Pos          (8)                                               /*!< EPWM_T::STATUS: SYNCINF0 Position       */
+#define EPWM_STATUS_SYNCINF0_Msk          (0x1ul << EPWM_STATUS_SYNCINF0_Pos)                /*!< EPWM_T::STATUS: SYNCINF0 Mask           */
+
+#define EPWM_STATUS_SYNCINF2_Pos          (9)                                               /*!< EPWM_T::STATUS: SYNCINF2 Position       */
+#define EPWM_STATUS_SYNCINF2_Msk          (0x1ul << EPWM_STATUS_SYNCINF2_Pos)                /*!< EPWM_T::STATUS: SYNCINF2 Mask           */
+
+#define EPWM_STATUS_SYNCINF4_Pos          (10)                                              /*!< EPWM_T::STATUS: SYNCINF4 Position       */
+#define EPWM_STATUS_SYNCINF4_Msk          (0x1ul << EPWM_STATUS_SYNCINF4_Pos)                /*!< EPWM_T::STATUS: SYNCINF4 Mask           */
+
+#define EPWM_STATUS_EADCTRGF0_Pos         (16)                                              /*!< EPWM_T::STATUS: EADCTRGF0 Position      */
+#define EPWM_STATUS_EADCTRGF0_Msk         (0x1ul << EPWM_STATUS_EADCTRGF0_Pos)               /*!< EPWM_T::STATUS: EADCTRGF0 Mask          */
+
+#define EPWM_STATUS_EADCTRGF1_Pos         (17)                                              /*!< EPWM_T::STATUS: EADCTRGF1 Position      */
+#define EPWM_STATUS_EADCTRGF1_Msk         (0x1ul << EPWM_STATUS_EADCTRGF1_Pos)               /*!< EPWM_T::STATUS: EADCTRGF1 Mask          */
+
+#define EPWM_STATUS_EADCTRGF2_Pos         (18)                                              /*!< EPWM_T::STATUS: EADCTRGF2 Position      */
+#define EPWM_STATUS_EADCTRGF2_Msk         (0x1ul << EPWM_STATUS_EADCTRGF2_Pos)               /*!< EPWM_T::STATUS: EADCTRGF2 Mask          */
+
+#define EPWM_STATUS_EADCTRGF3_Pos         (19)                                              /*!< EPWM_T::STATUS: EADCTRGF3 Position      */
+#define EPWM_STATUS_EADCTRGF3_Msk         (0x1ul << EPWM_STATUS_EADCTRGF3_Pos)               /*!< EPWM_T::STATUS: EADCTRGF3 Mask          */
+
+#define EPWM_STATUS_EADCTRGF4_Pos         (20)                                              /*!< EPWM_T::STATUS: EADCTRGF4 Position      */
+#define EPWM_STATUS_EADCTRGF4_Msk         (0x1ul << EPWM_STATUS_EADCTRGF4_Pos)               /*!< EPWM_T::STATUS: EADCTRGF4 Mask          */
+
+#define EPWM_STATUS_EADCTRGF5_Pos         (21)                                              /*!< EPWM_T::STATUS: EADCTRGF5 Position      */
+#define EPWM_STATUS_EADCTRGF5_Msk         (0x1ul << EPWM_STATUS_EADCTRGF5_Pos)               /*!< EPWM_T::STATUS: EADCTRGF5 Mask          */
+
+#define EPWM_STATUS_DACTRGF_Pos           (24)                                              /*!< EPWM_T::STATUS: DACTRGF Position        */
+#define EPWM_STATUS_DACTRGF_Msk           (0x1ul << EPWM_STATUS_DACTRGF_Pos)                 /*!< EPWM_T::STATUS: DACTRGF Mask            */
+
+#define EPWM_IFA0_IFACNT_Pos              (0)                                               /*!< EPWM_T::IFA0: IFACNT Position           */
+#define EPWM_IFA0_IFACNT_Msk              (0xfffful << EPWM_IFA0_IFACNT_Pos)                 /*!< EPWM_T::IFA0: IFACNT Mask               */
+
+#define EPWM_IFA0_STPMOD_Pos              (24)                                              /*!< EPWM_T::IFA0: STPMOD Position           */
+#define EPWM_IFA0_STPMOD_Msk              (0x1ul << EPWM_IFA0_STPMOD_Pos)                    /*!< EPWM_T::IFA0: STPMOD Mask               */
+
+#define EPWM_IFA0_IFASEL_Pos              (28)                                              /*!< EPWM_T::IFA0: IFASEL Position           */
+#define EPWM_IFA0_IFASEL_Msk              (0x3ul << EPWM_IFA0_IFASEL_Pos)                    /*!< EPWM_T::IFA0: IFASEL Mask               */
+
+#define EPWM_IFA0_IFAEN_Pos               (31)                                              /*!< EPWM_T::IFA0: IFAEN Position            */
+#define EPWM_IFA0_IFAEN_Msk               (0x1ul << EPWM_IFA0_IFAEN_Pos)                     /*!< EPWM_T::IFA0: IFAEN Mask                */
+
+#define EPWM_IFA1_IFACNT_Pos              (0)                                               /*!< EPWM_T::IFA1: IFACNT Position           */
+#define EPWM_IFA1_IFACNT_Msk              (0xfffful << EPWM_IFA1_IFACNT_Pos)                 /*!< EPWM_T::IFA1: IFACNT Mask               */
+
+#define EPWM_IFA1_STPMOD_Pos              (24)                                              /*!< EPWM_T::IFA1: STPMOD Position           */
+#define EPWM_IFA1_STPMOD_Msk              (0x1ul << EPWM_IFA1_STPMOD_Pos)                    /*!< EPWM_T::IFA1: STPMOD Mask               */
+
+#define EPWM_IFA1_IFASEL_Pos              (28)                                              /*!< EPWM_T::IFA1: IFASEL Position           */
+#define EPWM_IFA1_IFASEL_Msk              (0x3ul << EPWM_IFA1_IFASEL_Pos)                    /*!< EPWM_T::IFA1: IFASEL Mask               */
+
+#define EPWM_IFA1_IFAEN_Pos               (31)                                              /*!< EPWM_T::IFA1: IFAEN Position            */
+#define EPWM_IFA1_IFAEN_Msk               (0x1ul << EPWM_IFA1_IFAEN_Pos)                     /*!< EPWM_T::IFA1: IFAEN Mask                */
+
+#define EPWM_IFA2_IFACNT_Pos              (0)                                               /*!< EPWM_T::IFA2: IFACNT Position           */
+#define EPWM_IFA2_IFACNT_Msk              (0xfffful << EPWM_IFA2_IFACNT_Pos)                 /*!< EPWM_T::IFA2: IFACNT Mask               */
+
+#define EPWM_IFA2_STPMOD_Pos              (24)                                              /*!< EPWM_T::IFA2: STPMOD Position           */
+#define EPWM_IFA2_STPMOD_Msk              (0x1ul << EPWM_IFA2_STPMOD_Pos)                    /*!< EPWM_T::IFA2: STPMOD Mask               */
+
+#define EPWM_IFA2_IFASEL_Pos              (28)                                              /*!< EPWM_T::IFA2: IFASEL Position           */
+#define EPWM_IFA2_IFASEL_Msk              (0x3ul << EPWM_IFA2_IFASEL_Pos)                    /*!< EPWM_T::IFA2: IFASEL Mask               */
+
+#define EPWM_IFA2_IFAEN_Pos               (31)                                              /*!< EPWM_T::IFA2: IFAEN Position            */
+#define EPWM_IFA2_IFAEN_Msk               (0x1ul << EPWM_IFA2_IFAEN_Pos)                     /*!< EPWM_T::IFA2: IFAEN Mask                */
+
+#define EPWM_IFA3_IFACNT_Pos              (0)                                               /*!< EPWM_T::IFA3: IFACNT Position           */
+#define EPWM_IFA3_IFACNT_Msk              (0xfffful << EPWM_IFA3_IFACNT_Pos)                 /*!< EPWM_T::IFA3: IFACNT Mask               */
+
+#define EPWM_IFA3_STPMOD_Pos              (24)                                              /*!< EPWM_T::IFA3: STPMOD Position           */
+#define EPWM_IFA3_STPMOD_Msk              (0x1ul << EPWM_IFA3_STPMOD_Pos)                    /*!< EPWM_T::IFA3: STPMOD Mask               */
+
+#define EPWM_IFA3_IFASEL_Pos              (28)                                              /*!< EPWM_T::IFA3: IFASEL Position           */
+#define EPWM_IFA3_IFASEL_Msk              (0x3ul << EPWM_IFA3_IFASEL_Pos)                    /*!< EPWM_T::IFA3: IFASEL Mask               */
+
+#define EPWM_IFA3_IFAEN_Pos               (31)                                              /*!< EPWM_T::IFA3: IFAEN Position            */
+#define EPWM_IFA3_IFAEN_Msk               (0x1ul << EPWM_IFA3_IFAEN_Pos)                     /*!< EPWM_T::IFA3: IFAEN Mask                */
+
+#define EPWM_IFA4_IFACNT_Pos              (0)                                               /*!< EPWM_T::IFA4: IFACNT Position           */
+#define EPWM_IFA4_IFACNT_Msk              (0xfffful << EPWM_IFA4_IFACNT_Pos)                 /*!< EPWM_T::IFA4: IFACNT Mask               */
+
+#define EPWM_IFA4_STPMOD_Pos              (24)                                              /*!< EPWM_T::IFA4: STPMOD Position           */
+#define EPWM_IFA4_STPMOD_Msk              (0x1ul << EPWM_IFA4_STPMOD_Pos)                    /*!< EPWM_T::IFA4: STPMOD Mask               */
+
+#define EPWM_IFA4_IFASEL_Pos              (28)                                              /*!< EPWM_T::IFA4: IFASEL Position           */
+#define EPWM_IFA4_IFASEL_Msk              (0x3ul << EPWM_IFA4_IFASEL_Pos)                    /*!< EPWM_T::IFA4: IFASEL Mask               */
+
+#define EPWM_IFA4_IFAEN_Pos               (31)                                              /*!< EPWM_T::IFA4: IFAEN Position            */
+#define EPWM_IFA4_IFAEN_Msk               (0x1ul << EPWM_IFA4_IFAEN_Pos)                     /*!< EPWM_T::IFA4: IFAEN Mask                */
+
+#define EPWM_IFA5_IFACNT_Pos              (0)                                               /*!< EPWM_T::IFA5: IFACNT Position           */
+#define EPWM_IFA5_IFACNT_Msk              (0xfffful << EPWM_IFA5_IFACNT_Pos)                 /*!< EPWM_T::IFA5: IFACNT Mask               */
+
+#define EPWM_IFA5_STPMOD_Pos              (24)                                              /*!< EPWM_T::IFA5: STPMOD Position           */
+#define EPWM_IFA5_STPMOD_Msk              (0x1ul << EPWM_IFA5_STPMOD_Pos)                    /*!< EPWM_T::IFA5: STPMOD Mask               */
+
+#define EPWM_IFA5_IFASEL_Pos              (28)                                              /*!< EPWM_T::IFA5: IFASEL Position           */
+#define EPWM_IFA5_IFASEL_Msk              (0x3ul << EPWM_IFA5_IFASEL_Pos)                    /*!< EPWM_T::IFA5: IFASEL Mask               */
+
+#define EPWM_IFA5_IFAEN_Pos               (31)                                              /*!< EPWM_T::IFA5: IFAEN Position            */
+#define EPWM_IFA5_IFAEN_Msk               (0x1ul << EPWM_IFA5_IFAEN_Pos)                     /*!< EPWM_T::IFA5: IFAEN Mask                */
+
+#define EPWM_AINTSTS_IFAIF0_Pos           (0)                                               /*!< EPWM_T::AINTSTS: IFAIF0 Position        */
+#define EPWM_AINTSTS_IFAIF0_Msk           (0x1ul << EPWM_AINTSTS_IFAIF0_Pos)                 /*!< EPWM_T::AINTSTS: IFAIF0 Mask            */
+
+#define EPWM_AINTSTS_IFAIF1_Pos           (1)                                               /*!< EPWM_T::AINTSTS: IFAIF1 Position        */
+#define EPWM_AINTSTS_IFAIF1_Msk           (0x1ul << EPWM_AINTSTS_IFAIF1_Pos)                 /*!< EPWM_T::AINTSTS: IFAIF1 Mask            */
+
+#define EPWM_AINTSTS_IFAIF2_Pos           (2)                                               /*!< EPWM_T::AINTSTS: IFAIF2 Position        */
+#define EPWM_AINTSTS_IFAIF2_Msk           (0x1ul << EPWM_AINTSTS_IFAIF2_Pos)                 /*!< EPWM_T::AINTSTS: IFAIF2 Mask            */
+
+#define EPWM_AINTSTS_IFAIF3_Pos           (3)                                               /*!< EPWM_T::AINTSTS: IFAIF3 Position        */
+#define EPWM_AINTSTS_IFAIF3_Msk           (0x1ul << EPWM_AINTSTS_IFAIF3_Pos)                 /*!< EPWM_T::AINTSTS: IFAIF3 Mask            */
+
+#define EPWM_AINTSTS_IFAIF4_Pos           (4)                                               /*!< EPWM_T::AINTSTS: IFAIF4 Position        */
+#define EPWM_AINTSTS_IFAIF4_Msk           (0x1ul << EPWM_AINTSTS_IFAIF4_Pos)                 /*!< EPWM_T::AINTSTS: IFAIF4 Mask            */
+
+#define EPWM_AINTSTS_IFAIF5_Pos           (5)                                               /*!< EPWM_T::AINTSTS: IFAIF5 Position        */
+#define EPWM_AINTSTS_IFAIF5_Msk           (0x1ul << EPWM_AINTSTS_IFAIF5_Pos)                 /*!< EPWM_T::AINTSTS: IFAIF5 Mask            */
+
+#define EPWM_AINTEN_IFAIEN0_Pos           (0)                                               /*!< EPWM_T::AINTEN: IFAIEN0 Position        */
+#define EPWM_AINTEN_IFAIEN0_Msk           (0x1ul << EPWM_AINTEN_IFAIEN0_Pos)                 /*!< EPWM_T::AINTEN: IFAIEN0 Mask            */
+
+#define EPWM_AINTEN_IFAIEN1_Pos           (1)                                               /*!< EPWM_T::AINTEN: IFAIEN1 Position        */
+#define EPWM_AINTEN_IFAIEN1_Msk           (0x1ul << EPWM_AINTEN_IFAIEN1_Pos)                 /*!< EPWM_T::AINTEN: IFAIEN1 Mask            */
+
+#define EPWM_AINTEN_IFAIEN2_Pos           (2)                                               /*!< EPWM_T::AINTEN: IFAIEN2 Position        */
+#define EPWM_AINTEN_IFAIEN2_Msk           (0x1ul << EPWM_AINTEN_IFAIEN2_Pos)                 /*!< EPWM_T::AINTEN: IFAIEN2 Mask            */
+
+#define EPWM_AINTEN_IFAIEN3_Pos           (3)                                               /*!< EPWM_T::AINTEN: IFAIEN3 Position        */
+#define EPWM_AINTEN_IFAIEN3_Msk           (0x1ul << EPWM_AINTEN_IFAIEN3_Pos)                 /*!< EPWM_T::AINTEN: IFAIEN3 Mask            */
+
+#define EPWM_AINTEN_IFAIEN4_Pos           (4)                                               /*!< EPWM_T::AINTEN: IFAIEN4 Position        */
+#define EPWM_AINTEN_IFAIEN4_Msk           (0x1ul << EPWM_AINTEN_IFAIEN4_Pos)                 /*!< EPWM_T::AINTEN: IFAIEN4 Mask            */
+
+#define EPWM_AINTEN_IFAIEN5_Pos           (5)                                               /*!< EPWM_T::AINTEN: IFAIEN5 Position        */
+#define EPWM_AINTEN_IFAIEN5_Msk           (0x1ul << EPWM_AINTEN_IFAIEN5_Pos)                 /*!< EPWM_T::AINTEN: IFAIEN5 Mask            */
+
+#define EPWM_APDMACTL_APDMAEN0_Pos        (0)                                               /*!< EPWM_T::APDMACTL: APDMAEN0 Position     */
+#define EPWM_APDMACTL_APDMAEN0_Msk        (0x1ul << EPWM_APDMACTL_APDMAEN0_Pos)              /*!< EPWM_T::APDMACTL: APDMAEN0 Mask         */
+
+#define EPWM_APDMACTL_APDMAEN1_Pos        (1)                                               /*!< EPWM_T::APDMACTL: APDMAEN1 Position     */
+#define EPWM_APDMACTL_APDMAEN1_Msk        (0x1ul << EPWM_APDMACTL_APDMAEN1_Pos)              /*!< EPWM_T::APDMACTL: APDMAEN1 Mask         */
+
+#define EPWM_APDMACTL_APDMAEN2_Pos        (2)                                               /*!< EPWM_T::APDMACTL: APDMAEN2 Position     */
+#define EPWM_APDMACTL_APDMAEN2_Msk        (0x1ul << EPWM_APDMACTL_APDMAEN2_Pos)              /*!< EPWM_T::APDMACTL: APDMAEN2 Mask         */
+
+#define EPWM_APDMACTL_APDMAEN3_Pos        (3)                                               /*!< EPWM_T::APDMACTL: APDMAEN3 Position     */
+#define EPWM_APDMACTL_APDMAEN3_Msk        (0x1ul << EPWM_APDMACTL_APDMAEN3_Pos)              /*!< EPWM_T::APDMACTL: APDMAEN3 Mask         */
+
+#define EPWM_APDMACTL_APDMAEN4_Pos        (4)                                               /*!< EPWM_T::APDMACTL: APDMAEN4 Position     */
+#define EPWM_APDMACTL_APDMAEN4_Msk        (0x1ul << EPWM_APDMACTL_APDMAEN4_Pos)              /*!< EPWM_T::APDMACTL: APDMAEN4 Mask         */
+
+#define EPWM_APDMACTL_APDMAEN5_Pos        (5)                                               /*!< EPWM_T::APDMACTL: APDMAEN5 Position     */
+#define EPWM_APDMACTL_APDMAEN5_Msk        (0x1ul << EPWM_APDMACTL_APDMAEN5_Pos)              /*!< EPWM_T::APDMACTL: APDMAEN5 Mask         */
+
+#define EPWM_FDEN_FDEN0_Pos               (0)                                               /*!< EPWM_T::FDEN: FDEN0 Position            */
+#define EPWM_FDEN_FDEN0_Msk               (0x1ul << EPWM_FDEN_FDEN0_Pos)                     /*!< EPWM_T::FDEN: FDEN0 Mask                */
+
+#define EPWM_FDEN_FDEN1_Pos               (1)                                               /*!< EPWM_T::FDEN: FDEN1 Position            */
+#define EPWM_FDEN_FDEN1_Msk               (0x1ul << EPWM_FDEN_FDEN1_Pos)                     /*!< EPWM_T::FDEN: FDEN1 Mask                */
+
+#define EPWM_FDEN_FDEN2_Pos               (2)                                               /*!< EPWM_T::FDEN: FDEN2 Position            */
+#define EPWM_FDEN_FDEN2_Msk               (0x1ul << EPWM_FDEN_FDEN2_Pos)                     /*!< EPWM_T::FDEN: FDEN2 Mask                */
+
+#define EPWM_FDEN_FDEN3_Pos               (3)                                               /*!< EPWM_T::FDEN: FDEN3 Position            */
+#define EPWM_FDEN_FDEN3_Msk               (0x1ul << EPWM_FDEN_FDEN3_Pos)                     /*!< EPWM_T::FDEN: FDEN3 Mask                */
+
+#define EPWM_FDEN_FDEN4_Pos               (4)                                               /*!< EPWM_T::FDEN: FDEN4 Position            */
+#define EPWM_FDEN_FDEN4_Msk               (0x1ul << EPWM_FDEN_FDEN4_Pos)                     /*!< EPWM_T::FDEN: FDEN4 Mask                */
+
+#define EPWM_FDEN_FDEN5_Pos               (5)                                               /*!< EPWM_T::FDEN: FDEN5 Position            */
+#define EPWM_FDEN_FDEN5_Msk               (0x1ul << EPWM_FDEN_FDEN5_Pos)                     /*!< EPWM_T::FDEN: FDEN5 Mask                */
+
+#define EPWM_FDEN_FDODIS0_Pos             (8)                                               /*!< EPWM_T::FDEN: FDODIS0 Position          */
+#define EPWM_FDEN_FDODIS0_Msk             (0x1ul << EPWM_FDEN_FDODIS0_Pos)                   /*!< EPWM_T::FDEN: FDODIS0 Mask              */
+
+#define EPWM_FDEN_FDODIS1_Pos             (9)                                               /*!< EPWM_T::FDEN: FDODIS1 Position          */
+#define EPWM_FDEN_FDODIS1_Msk             (0x1ul << EPWM_FDEN_FDODIS1_Pos)                   /*!< EPWM_T::FDEN: FDODIS1 Mask              */
+
+#define EPWM_FDEN_FDODIS2_Pos             (10)                                              /*!< EPWM_T::FDEN: FDODIS2 Position          */
+#define EPWM_FDEN_FDODIS2_Msk             (0x1ul << EPWM_FDEN_FDODIS2_Pos)                   /*!< EPWM_T::FDEN: FDODIS2 Mask              */
+
+#define EPWM_FDEN_FDODIS3_Pos             (11)                                              /*!< EPWM_T::FDEN: FDODIS3 Position          */
+#define EPWM_FDEN_FDODIS3_Msk             (0x1ul << EPWM_FDEN_FDODIS3_Pos)                   /*!< EPWM_T::FDEN: FDODIS3 Mask              */
+
+#define EPWM_FDEN_FDODIS4_Pos             (12)                                              /*!< EPWM_T::FDEN: FDODIS4 Position          */
+#define EPWM_FDEN_FDODIS4_Msk             (0x1ul << EPWM_FDEN_FDODIS4_Pos)                   /*!< EPWM_T::FDEN: FDODIS4 Mask              */
+
+#define EPWM_FDEN_FDODIS5_Pos             (13)                                              /*!< EPWM_T::FDEN: FDODIS5 Position          */
+#define EPWM_FDEN_FDODIS5_Msk             (0x1ul << EPWM_FDEN_FDODIS5_Pos)                   /*!< EPWM_T::FDEN: FDODIS5 Mask              */
+
+#define EPWM_FDEN_FDCKS0_Pos              (16)                                              /*!< EPWM_T::FDEN: FDCKS0 Position           */
+#define EPWM_FDEN_FDCKS0_Msk              (0x1ul << EPWM_FDEN_FDCKS0_Pos)                    /*!< EPWM_T::FDEN: FDCKS0 Mask               */
+
+#define EPWM_FDEN_FDCKS1_Pos              (17)                                              /*!< EPWM_T::FDEN: FDCKS1 Position           */
+#define EPWM_FDEN_FDCKS1_Msk              (0x1ul << EPWM_FDEN_FDCKS1_Pos)                    /*!< EPWM_T::FDEN: FDCKS1 Mask               */
+
+#define EPWM_FDEN_FDCKS2_Pos              (18)                                              /*!< EPWM_T::FDEN: FDCKS2 Position           */
+#define EPWM_FDEN_FDCKS2_Msk              (0x1ul << EPWM_FDEN_FDCKS2_Pos)                    /*!< EPWM_T::FDEN: FDCKS2 Mask               */
+
+#define EPWM_FDEN_FDCKS3_Pos              (19)                                              /*!< EPWM_T::FDEN: FDCKS3 Position           */
+#define EPWM_FDEN_FDCKS3_Msk              (0x1ul << EPWM_FDEN_FDCKS3_Pos)                    /*!< EPWM_T::FDEN: FDCKS3 Mask               */
+
+#define EPWM_FDEN_FDCKS4_Pos              (20)                                              /*!< EPWM_T::FDEN: FDCKS4 Position           */
+#define EPWM_FDEN_FDCKS4_Msk              (0x1ul << EPWM_FDEN_FDCKS4_Pos)                    /*!< EPWM_T::FDEN: FDCKS4 Mask               */
+
+#define EPWM_FDEN_FDCKS5_Pos              (21)                                              /*!< EPWM_T::FDEN: FDCKS5 Position           */
+#define EPWM_FDEN_FDCKS5_Msk              (0x1ul << EPWM_FDEN_FDCKS5_Pos)                    /*!< EPWM_T::FDEN: FDCKS5 Mask               */
+
+#define EPWM_FDCTL0_TRMSKCNT_Pos          (0)                                               /*!< EPWM_T::FDCTL0: TRMSKCNT Position       */
+#define EPWM_FDCTL0_TRMSKCNT_Msk          (0x7ful << EPWM_FDCTL0_TRMSKCNT_Pos)               /*!< EPWM_T::FDCTL0: TRMSKCNT Mask           */
+
+#define EPWM_FDCTL0_FDMSKEN_Pos           (15)                                              /*!< EPWM_T::FDCTL0: FDMSKEN Position        */
+#define EPWM_FDCTL0_FDMSKEN_Msk           (0x1ul << EPWM_FDCTL0_FDMSKEN_Pos)                 /*!< EPWM_T::FDCTL0: FDMSKEN Mask            */
+
+#define EPWM_FDCTL0_DGSMPCYC_Pos          (16)                                              /*!< EPWM_T::FDCTL0: DGSMPCYC Position       */
+#define EPWM_FDCTL0_DGSMPCYC_Msk          (0x7ul << EPWM_FDCTL0_DGSMPCYC_Pos)                /*!< EPWM_T::FDCTL0: DGSMPCYC Mask           */
+
+#define EPWM_FDCTL0_FDCKSEL_Pos           (28)                                              /*!< EPWM_T::FDCTL0: FDCKSEL Position        */
+#define EPWM_FDCTL0_FDCKSEL_Msk           (0x3ul << EPWM_FDCTL0_FDCKSEL_Pos)                 /*!< EPWM_T::FDCTL0: FDCKSEL Mask            */
+
+#define EPWM_FDCTL0_FDDGEN_Pos            (31)                                              /*!< EPWM_T::FDCTL0: FDDGEN Position         */
+#define EPWM_FDCTL0_FDDGEN_Msk            (0x1ul << EPWM_FDCTL0_FDDGEN_Pos)                  /*!< EPWM_T::FDCTL0: FDDGEN Mask             */
+
+#define EPWM_FDCTL1_TRMSKCNT_Pos          (0)                                               /*!< EPWM_T::FDCTL1: TRMSKCNT Position       */
+#define EPWM_FDCTL1_TRMSKCNT_Msk          (0x7ful << EPWM_FDCTL1_TRMSKCNT_Pos)               /*!< EPWM_T::FDCTL1: TRMSKCNT Mask           */
+
+#define EPWM_FDCTL1_FDMSKEN_Pos           (15)                                              /*!< EPWM_T::FDCTL1: FDMSKEN Position        */
+#define EPWM_FDCTL1_FDMSKEN_Msk           (0x1ul << EPWM_FDCTL1_FDMSKEN_Pos)                 /*!< EPWM_T::FDCTL1: FDMSKEN Mask            */
+
+#define EPWM_FDCTL1_DGSMPCYC_Pos          (16)                                              /*!< EPWM_T::FDCTL1: DGSMPCYC Position       */
+#define EPWM_FDCTL1_DGSMPCYC_Msk          (0x7ul << EPWM_FDCTL1_DGSMPCYC_Pos)                /*!< EPWM_T::FDCTL1: DGSMPCYC Mask           */
+
+#define EPWM_FDCTL1_FDCKSEL_Pos           (28)                                              /*!< EPWM_T::FDCTL1: FDCKSEL Position        */
+#define EPWM_FDCTL1_FDCKSEL_Msk           (0x3ul << EPWM_FDCTL1_FDCKSEL_Pos)                 /*!< EPWM_T::FDCTL1: FDCKSEL Mask            */
+
+#define EPWM_FDCTL1_FDDGEN_Pos            (31)                                              /*!< EPWM_T::FDCTL1: FDDGEN Position         */
+#define EPWM_FDCTL1_FDDGEN_Msk            (0x1ul << EPWM_FDCTL1_FDDGEN_Pos)                  /*!< EPWM_T::FDCTL1: FDDGEN Mask             */
+
+#define EPWM_FDCTL2_TRMSKCNT_Pos          (0)                                               /*!< EPWM_T::FDCTL2: TRMSKCNT Position       */
+#define EPWM_FDCTL2_TRMSKCNT_Msk          (0x7ful << EPWM_FDCTL2_TRMSKCNT_Pos)               /*!< EPWM_T::FDCTL2: TRMSKCNT Mask           */
+
+#define EPWM_FDCTL2_FDMSKEN_Pos           (15)                                              /*!< EPWM_T::FDCTL2: FDMSKEN Position        */
+#define EPWM_FDCTL2_FDMSKEN_Msk           (0x1ul << EPWM_FDCTL2_FDMSKEN_Pos)                 /*!< EPWM_T::FDCTL2: FDMSKEN Mask            */
+
+#define EPWM_FDCTL2_DGSMPCYC_Pos          (16)                                              /*!< EPWM_T::FDCTL2: DGSMPCYC Position       */
+#define EPWM_FDCTL2_DGSMPCYC_Msk          (0x7ul << EPWM_FDCTL2_DGSMPCYC_Pos)                /*!< EPWM_T::FDCTL2: DGSMPCYC Mask           */
+
+#define EPWM_FDCTL2_FDCKSEL_Pos           (28)                                              /*!< EPWM_T::FDCTL2: FDCKSEL Position        */
+#define EPWM_FDCTL2_FDCKSEL_Msk           (0x3ul << EPWM_FDCTL2_FDCKSEL_Pos)                 /*!< EPWM_T::FDCTL2: FDCKSEL Mask            */
+
+#define EPWM_FDCTL2_FDDGEN_Pos            (31)                                              /*!< EPWM_T::FDCTL2: FDDGEN Position         */
+#define EPWM_FDCTL2_FDDGEN_Msk            (0x1ul << EPWM_FDCTL2_FDDGEN_Pos)                  /*!< EPWM_T::FDCTL2: FDDGEN Mask             */
+
+#define EPWM_FDCTL3_TRMSKCNT_Pos          (0)                                               /*!< EPWM_T::FDCTL3: TRMSKCNT Position       */
+#define EPWM_FDCTL3_TRMSKCNT_Msk          (0x7ful << EPWM_FDCTL3_TRMSKCNT_Pos)               /*!< EPWM_T::FDCTL3: TRMSKCNT Mask           */
+
+#define EPWM_FDCTL3_FDMSKEN_Pos           (15)                                              /*!< EPWM_T::FDCTL3: FDMSKEN Position        */
+#define EPWM_FDCTL3_FDMSKEN_Msk           (0x1ul << EPWM_FDCTL3_FDMSKEN_Pos)                 /*!< EPWM_T::FDCTL3: FDMSKEN Mask            */
+
+#define EPWM_FDCTL3_DGSMPCYC_Pos          (16)                                              /*!< EPWM_T::FDCTL3: DGSMPCYC Position       */
+#define EPWM_FDCTL3_DGSMPCYC_Msk          (0x7ul << EPWM_FDCTL3_DGSMPCYC_Pos)                /*!< EPWM_T::FDCTL3: DGSMPCYC Mask           */
+
+#define EPWM_FDCTL3_FDCKSEL_Pos           (28)                                              /*!< EPWM_T::FDCTL3: FDCKSEL Position        */
+#define EPWM_FDCTL3_FDCKSEL_Msk           (0x3ul << EPWM_FDCTL3_FDCKSEL_Pos)                 /*!< EPWM_T::FDCTL3: FDCKSEL Mask            */
+
+#define EPWM_FDCTL3_FDDGEN_Pos            (31)                                              /*!< EPWM_T::FDCTL3: FDDGEN Position         */
+#define EPWM_FDCTL3_FDDGEN_Msk            (0x1ul << EPWM_FDCTL3_FDDGEN_Pos)                  /*!< EPWM_T::FDCTL3: FDDGEN Mask             */
+
+#define EPWM_FDCTL4_TRMSKCNT_Pos          (0)                                               /*!< EPWM_T::FDCTL4: TRMSKCNT Position       */
+#define EPWM_FDCTL4_TRMSKCNT_Msk          (0x7ful << EPWM_FDCTL4_TRMSKCNT_Pos)               /*!< EPWM_T::FDCTL4: TRMSKCNT Mask           */
+
+#define EPWM_FDCTL4_FDMSKEN_Pos           (15)                                              /*!< EPWM_T::FDCTL4: FDMSKEN Position        */
+#define EPWM_FDCTL4_FDMSKEN_Msk           (0x1ul << EPWM_FDCTL4_FDMSKEN_Pos)                 /*!< EPWM_T::FDCTL4: FDMSKEN Mask            */
+
+#define EPWM_FDCTL4_DGSMPCYC_Pos          (16)                                              /*!< EPWM_T::FDCTL4: DGSMPCYC Position       */
+#define EPWM_FDCTL4_DGSMPCYC_Msk          (0x7ul << EPWM_FDCTL4_DGSMPCYC_Pos)                /*!< EPWM_T::FDCTL4: DGSMPCYC Mask           */
+
+#define EPWM_FDCTL4_FDCKSEL_Pos           (28)                                              /*!< EPWM_T::FDCTL4: FDCKSEL Position        */
+#define EPWM_FDCTL4_FDCKSEL_Msk           (0x3ul << EPWM_FDCTL4_FDCKSEL_Pos)                 /*!< EPWM_T::FDCTL4: FDCKSEL Mask            */
+
+#define EPWM_FDCTL4_FDDGEN_Pos            (31)                                              /*!< EPWM_T::FDCTL4: FDDGEN Position         */
+#define EPWM_FDCTL4_FDDGEN_Msk            (0x1ul << EPWM_FDCTL4_FDDGEN_Pos)                  /*!< EPWM_T::FDCTL4: FDDGEN Mask             */
+
+#define EPWM_FDCTL5_TRMSKCNT_Pos          (0)                                               /*!< EPWM_T::FDCTL5: TRMSKCNT Position       */
+#define EPWM_FDCTL5_TRMSKCNT_Msk          (0x7ful << EPWM_FDCTL5_TRMSKCNT_Pos)               /*!< EPWM_T::FDCTL5: TRMSKCNT Mask           */
+
+#define EPWM_FDCTL5_FDMSKEN_Pos           (15)                                              /*!< EPWM_T::FDCTL5: FDMSKEN Position        */
+#define EPWM_FDCTL5_FDMSKEN_Msk           (0x1ul << EPWM_FDCTL5_FDMSKEN_Pos)                 /*!< EPWM_T::FDCTL5: FDMSKEN Mask            */
+
+#define EPWM_FDCTL5_DGSMPCYC_Pos          (16)                                              /*!< EPWM_T::FDCTL5: DGSMPCYC Position       */
+#define EPWM_FDCTL5_DGSMPCYC_Msk          (0x7ul << EPWM_FDCTL5_DGSMPCYC_Pos)                /*!< EPWM_T::FDCTL5: DGSMPCYC Mask           */
+
+#define EPWM_FDCTL5_FDCKSEL_Pos           (28)                                              /*!< EPWM_T::FDCTL5: FDCKSEL Position        */
+#define EPWM_FDCTL5_FDCKSEL_Msk           (0x3ul << EPWM_FDCTL5_FDCKSEL_Pos)                 /*!< EPWM_T::FDCTL5: FDCKSEL Mask            */
+
+#define EPWM_FDCTL5_FDDGEN_Pos            (31)                                              /*!< EPWM_T::FDCTL5: FDDGEN Position         */
+#define EPWM_FDCTL5_FDDGEN_Msk            (0x1ul << EPWM_FDCTL5_FDDGEN_Pos)                  /*!< EPWM_T::FDCTL5: FDDGEN Mask             */
+
+#define EPWM_FDIEN_FDIEN0_Pos             (0)                                               /*!< EPWM_T::FDIEN: FDIEN0 Position          */
+#define EPWM_FDIEN_FDIEN0_Msk             (0x1ul << EPWM_FDIEN_FDIEN0_Pos)                   /*!< EPWM_T::FDIEN: FDIEN0 Mask              */
+
+#define EPWM_FDIEN_FDIEN1_Pos             (1)                                               /*!< EPWM_T::FDIEN: FDIEN1 Position          */
+#define EPWM_FDIEN_FDIEN1_Msk             (0x1ul << EPWM_FDIEN_FDIEN1_Pos)                   /*!< EPWM_T::FDIEN: FDIEN1 Mask              */
+
+#define EPWM_FDIEN_FDIEN2_Pos             (2)                                               /*!< EPWM_T::FDIEN: FDIEN2 Position          */
+#define EPWM_FDIEN_FDIEN2_Msk             (0x1ul << EPWM_FDIEN_FDIEN2_Pos)                   /*!< EPWM_T::FDIEN: FDIEN2 Mask              */
+
+#define EPWM_FDIEN_FDIEN3_Pos             (3)                                               /*!< EPWM_T::FDIEN: FDIEN3 Position          */
+#define EPWM_FDIEN_FDIEN3_Msk             (0x1ul << EPWM_FDIEN_FDIEN3_Pos)                   /*!< EPWM_T::FDIEN: FDIEN3 Mask              */
+
+#define EPWM_FDIEN_FDIEN4_Pos             (4)                                               /*!< EPWM_T::FDIEN: FDIEN4 Position          */
+#define EPWM_FDIEN_FDIEN4_Msk             (0x1ul << EPWM_FDIEN_FDIEN4_Pos)                   /*!< EPWM_T::FDIEN: FDIEN4 Mask              */
+
+#define EPWM_FDIEN_FDIEN5_Pos             (5)                                               /*!< EPWM_T::FDIEN: FDIEN5 Position          */
+#define EPWM_FDIEN_FDIEN5_Msk             (0x1ul << EPWM_FDIEN_FDIEN5_Pos)                   /*!< EPWM_T::FDIEN: FDIEN5 Mask              */
+
+#define EPWM_FDSTS_FDIF0_Pos              (0)                                               /*!< EPWM_T::FDSTS: FDIF0 Position           */
+#define EPWM_FDSTS_FDIF0_Msk              (0x1ul << EPWM_FDSTS_FDIF0_Pos)                    /*!< EPWM_T::FDSTS: FDIF0 Mask               */
+
+#define EPWM_FDSTS_FDIF1_Pos              (1)                                               /*!< EPWM_T::FDSTS: FDIF1 Position           */
+#define EPWM_FDSTS_FDIF1_Msk              (0x1ul << EPWM_FDSTS_FDIF1_Pos)                    /*!< EPWM_T::FDSTS: FDIF1 Mask               */
+
+#define EPWM_FDSTS_FDIF2_Pos              (2)                                               /*!< EPWM_T::FDSTS: FDIF2 Position           */
+#define EPWM_FDSTS_FDIF2_Msk              (0x1ul << EPWM_FDSTS_FDIF2_Pos)                    /*!< EPWM_T::FDSTS: FDIF2 Mask               */
+
+#define EPWM_FDSTS_FDIF3_Pos              (3)                                               /*!< EPWM_T::FDSTS: FDIF3 Position           */
+#define EPWM_FDSTS_FDIF3_Msk              (0x1ul << EPWM_FDSTS_FDIF3_Pos)                    /*!< EPWM_T::FDSTS: FDIF3 Mask               */
+
+#define EPWM_FDSTS_FDIF4_Pos              (4)                                               /*!< EPWM_T::FDSTS: FDIF4 Position           */
+#define EPWM_FDSTS_FDIF4_Msk              (0x1ul << EPWM_FDSTS_FDIF4_Pos)                    /*!< EPWM_T::FDSTS: FDIF4 Mask               */
+
+#define EPWM_FDSTS_FDIF5_Pos              (5)                                               /*!< EPWM_T::FDSTS: FDIF5 Position           */
+#define EPWM_FDSTS_FDIF5_Msk              (0x1ul << EPWM_FDSTS_FDIF5_Pos)                    /*!< EPWM_T::FDSTS: FDIF5 Mask               */
+
+#define EPWM_EADCPSCCTL_PSCEN0_Pos        (0)                                               /*!< EPWM_T::EADCPSCCTL: PSCEN0 Position     */
+#define EPWM_EADCPSCCTL_PSCEN0_Msk        (0x1ul << EPWM_EADCPSCCTL_PSCEN0_Pos)              /*!< EPWM_T::EADCPSCCTL: PSCEN0 Mask         */
+
+#define EPWM_EADCPSCCTL_PSCEN1_Pos        (1)                                               /*!< EPWM_T::EADCPSCCTL: PSCEN1 Position     */
+#define EPWM_EADCPSCCTL_PSCEN1_Msk        (0x1ul << EPWM_EADCPSCCTL_PSCEN1_Pos)              /*!< EPWM_T::EADCPSCCTL: PSCEN1 Mask         */
+
+#define EPWM_EADCPSCCTL_PSCEN2_Pos        (2)                                               /*!< EPWM_T::EADCPSCCTL: PSCEN2 Position     */
+#define EPWM_EADCPSCCTL_PSCEN2_Msk        (0x1ul << EPWM_EADCPSCCTL_PSCEN2_Pos)              /*!< EPWM_T::EADCPSCCTL: PSCEN2 Mask         */
+
+#define EPWM_EADCPSCCTL_PSCEN3_Pos        (3)                                               /*!< EPWM_T::EADCPSCCTL: PSCEN3 Position     */
+#define EPWM_EADCPSCCTL_PSCEN3_Msk        (0x1ul << EPWM_EADCPSCCTL_PSCEN3_Pos)              /*!< EPWM_T::EADCPSCCTL: PSCEN3 Mask         */
+
+#define EPWM_EADCPSCCTL_PSCEN4_Pos        (4)                                               /*!< EPWM_T::EADCPSCCTL: PSCEN4 Position     */
+#define EPWM_EADCPSCCTL_PSCEN4_Msk        (0x1ul << EPWM_EADCPSCCTL_PSCEN4_Pos)              /*!< EPWM_T::EADCPSCCTL: PSCEN4 Mask         */
+
+#define EPWM_EADCPSCCTL_PSCEN5_Pos        (5)                                               /*!< EPWM_T::EADCPSCCTL: PSCEN5 Position     */
+#define EPWM_EADCPSCCTL_PSCEN5_Msk        (0x1ul << EPWM_EADCPSCCTL_PSCEN5_Pos)              /*!< EPWM_T::EADCPSCCTL: PSCEN5 Mask         */
+
+#define EPWM_EADCPSC0_EADCPSC0_Pos        (0)                                               /*!< EPWM_T::EADCPSC0: EADCPSC0 Position     */
+#define EPWM_EADCPSC0_EADCPSC0_Msk        (0xful << EPWM_EADCPSC0_EADCPSC0_Pos)              /*!< EPWM_T::EADCPSC0: EADCPSC0 Mask         */
+
+#define EPWM_EADCPSC0_EADCPSC1_Pos        (8)                                               /*!< EPWM_T::EADCPSC0: EADCPSC1 Position     */
+#define EPWM_EADCPSC0_EADCPSC1_Msk        (0xful << EPWM_EADCPSC0_EADCPSC1_Pos)              /*!< EPWM_T::EADCPSC0: EADCPSC1 Mask         */
+
+#define EPWM_EADCPSC0_EADCPSC2_Pos        (16)                                              /*!< EPWM_T::EADCPSC0: EADCPSC2 Position     */
+#define EPWM_EADCPSC0_EADCPSC2_Msk        (0xful << EPWM_EADCPSC0_EADCPSC2_Pos)              /*!< EPWM_T::EADCPSC0: EADCPSC2 Mask         */
+
+#define EPWM_EADCPSC0_EADCPSC3_Pos        (24)                                              /*!< EPWM_T::EADCPSC0: EADCPSC3 Position     */
+#define EPWM_EADCPSC0_EADCPSC3_Msk        (0xful << EPWM_EADCPSC0_EADCPSC3_Pos)              /*!< EPWM_T::EADCPSC0: EADCPSC3 Mask         */
+
+#define EPWM_EADCPSC1_EADCPSC4_Pos        (0)                                               /*!< EPWM_T::EADCPSC1: EADCPSC4 Position     */
+#define EPWM_EADCPSC1_EADCPSC4_Msk        (0xful << EPWM_EADCPSC1_EADCPSC4_Pos)              /*!< EPWM_T::EADCPSC1: EADCPSC4 Mask         */
+
+#define EPWM_EADCPSC1_EADCPSC5_Pos        (8)                                               /*!< EPWM_T::EADCPSC1: EADCPSC5 Position     */
+#define EPWM_EADCPSC1_EADCPSC5_Msk        (0xful << EPWM_EADCPSC1_EADCPSC5_Pos)              /*!< EPWM_T::EADCPSC1: EADCPSC5 Mask         */
+
+#define EPWM_EADCPSCNT0_PSCNT0_Pos        (0)                                               /*!< EPWM_T::EADCPSCNT0: PSCNT0 Position     */
+#define EPWM_EADCPSCNT0_PSCNT0_Msk        (0xful << EPWM_EADCPSCNT0_PSCNT0_Pos)              /*!< EPWM_T::EADCPSCNT0: PSCNT0 Mask         */
+
+#define EPWM_EADCPSCNT0_PSCNT1_Pos        (8)                                               /*!< EPWM_T::EADCPSCNT0: PSCNT1 Position     */
+#define EPWM_EADCPSCNT0_PSCNT1_Msk        (0xful << EPWM_EADCPSCNT0_PSCNT1_Pos)              /*!< EPWM_T::EADCPSCNT0: PSCNT1 Mask         */
+
+#define EPWM_EADCPSCNT0_PSCNT2_Pos        (16)                                              /*!< EPWM_T::EADCPSCNT0: PSCNT2 Position     */
+#define EPWM_EADCPSCNT0_PSCNT2_Msk        (0xful << EPWM_EADCPSCNT0_PSCNT2_Pos)              /*!< EPWM_T::EADCPSCNT0: PSCNT2 Mask         */
+
+#define EPWM_EADCPSCNT0_PSCNT3_Pos        (24)                                              /*!< EPWM_T::EADCPSCNT0: PSCNT3 Position     */
+#define EPWM_EADCPSCNT0_PSCNT3_Msk        (0xful << EPWM_EADCPSCNT0_PSCNT3_Pos)              /*!< EPWM_T::EADCPSCNT0: PSCNT3 Mask         */
+
+#define EPWM_EADCPSCNT1_PSCNT4_Pos        (0)                                               /*!< EPWM_T::EADCPSCNT1: PSCNT4 Position     */
+#define EPWM_EADCPSCNT1_PSCNT4_Msk        (0xful << EPWM_EADCPSCNT1_PSCNT4_Pos)              /*!< EPWM_T::EADCPSCNT1: PSCNT4 Mask         */
+
+#define EPWM_EADCPSCNT1_PSCNT5_Pos        (8)                                               /*!< EPWM_T::EADCPSCNT1: PSCNT5 Position     */
+#define EPWM_EADCPSCNT1_PSCNT5_Msk        (0xful << EPWM_EADCPSCNT1_PSCNT5_Pos)              /*!< EPWM_T::EADCPSCNT1: PSCNT5 Mask         */
+
+#define EPWM_CAPINEN_CAPINEN0_Pos         (0)                                               /*!< EPWM_T::CAPINEN: CAPINEN0 Position      */
+#define EPWM_CAPINEN_CAPINEN0_Msk         (0x1ul << EPWM_CAPINEN_CAPINEN0_Pos)               /*!< EPWM_T::CAPINEN: CAPINEN0 Mask          */
+
+#define EPWM_CAPINEN_CAPINEN1_Pos         (1)                                               /*!< EPWM_T::CAPINEN: CAPINEN1 Position      */
+#define EPWM_CAPINEN_CAPINEN1_Msk         (0x1ul << EPWM_CAPINEN_CAPINEN1_Pos)               /*!< EPWM_T::CAPINEN: CAPINEN1 Mask          */
+
+#define EPWM_CAPINEN_CAPINEN2_Pos         (2)                                               /*!< EPWM_T::CAPINEN: CAPINEN2 Position      */
+#define EPWM_CAPINEN_CAPINEN2_Msk         (0x1ul << EPWM_CAPINEN_CAPINEN2_Pos)               /*!< EPWM_T::CAPINEN: CAPINEN2 Mask          */
+
+#define EPWM_CAPINEN_CAPINEN3_Pos         (3)                                               /*!< EPWM_T::CAPINEN: CAPINEN3 Position      */
+#define EPWM_CAPINEN_CAPINEN3_Msk         (0x1ul << EPWM_CAPINEN_CAPINEN3_Pos)               /*!< EPWM_T::CAPINEN: CAPINEN3 Mask          */
+
+#define EPWM_CAPINEN_CAPINEN4_Pos         (4)                                               /*!< EPWM_T::CAPINEN: CAPINEN4 Position      */
+#define EPWM_CAPINEN_CAPINEN4_Msk         (0x1ul << EPWM_CAPINEN_CAPINEN4_Pos)               /*!< EPWM_T::CAPINEN: CAPINEN4 Mask          */
+
+#define EPWM_CAPINEN_CAPINEN5_Pos         (5)                                               /*!< EPWM_T::CAPINEN: CAPINEN5 Position      */
+#define EPWM_CAPINEN_CAPINEN5_Msk         (0x1ul << EPWM_CAPINEN_CAPINEN5_Pos)               /*!< EPWM_T::CAPINEN: CAPINEN5 Mask          */
+
+#define EPWM_CAPCTL_CAPEN0_Pos            (0)                                               /*!< EPWM_T::CAPCTL: CAPEN0 Position         */
+#define EPWM_CAPCTL_CAPEN0_Msk            (0x1ul << EPWM_CAPCTL_CAPEN0_Pos)                  /*!< EPWM_T::CAPCTL: CAPEN0 Mask             */
+
+#define EPWM_CAPCTL_CAPEN1_Pos            (1)                                               /*!< EPWM_T::CAPCTL: CAPEN1 Position         */
+#define EPWM_CAPCTL_CAPEN1_Msk            (0x1ul << EPWM_CAPCTL_CAPEN1_Pos)                  /*!< EPWM_T::CAPCTL: CAPEN1 Mask             */
+
+#define EPWM_CAPCTL_CAPEN2_Pos            (2)                                               /*!< EPWM_T::CAPCTL: CAPEN2 Position         */
+#define EPWM_CAPCTL_CAPEN2_Msk            (0x1ul << EPWM_CAPCTL_CAPEN2_Pos)                  /*!< EPWM_T::CAPCTL: CAPEN2 Mask             */
+
+#define EPWM_CAPCTL_CAPEN3_Pos            (3)                                               /*!< EPWM_T::CAPCTL: CAPEN3 Position         */
+#define EPWM_CAPCTL_CAPEN3_Msk            (0x1ul << EPWM_CAPCTL_CAPEN3_Pos)                  /*!< EPWM_T::CAPCTL: CAPEN3 Mask             */
+
+#define EPWM_CAPCTL_CAPEN4_Pos            (4)                                               /*!< EPWM_T::CAPCTL: CAPEN4 Position         */
+#define EPWM_CAPCTL_CAPEN4_Msk            (0x1ul << EPWM_CAPCTL_CAPEN4_Pos)                  /*!< EPWM_T::CAPCTL: CAPEN4 Mask             */
+
+#define EPWM_CAPCTL_CAPEN5_Pos            (5)                                               /*!< EPWM_T::CAPCTL: CAPEN5 Position         */
+#define EPWM_CAPCTL_CAPEN5_Msk            (0x1ul << EPWM_CAPCTL_CAPEN5_Pos)                  /*!< EPWM_T::CAPCTL: CAPEN5 Mask             */
+
+#define EPWM_CAPCTL_CAPINV0_Pos           (8)                                               /*!< EPWM_T::CAPCTL: CAPINV0 Position        */
+#define EPWM_CAPCTL_CAPINV0_Msk           (0x1ul << EPWM_CAPCTL_CAPINV0_Pos)                 /*!< EPWM_T::CAPCTL: CAPINV0 Mask            */
+
+#define EPWM_CAPCTL_CAPINV1_Pos           (9)                                               /*!< EPWM_T::CAPCTL: CAPINV1 Position        */
+#define EPWM_CAPCTL_CAPINV1_Msk           (0x1ul << EPWM_CAPCTL_CAPINV1_Pos)                 /*!< EPWM_T::CAPCTL: CAPINV1 Mask            */
+
+#define EPWM_CAPCTL_CAPINV2_Pos           (10)                                              /*!< EPWM_T::CAPCTL: CAPINV2 Position        */
+#define EPWM_CAPCTL_CAPINV2_Msk           (0x1ul << EPWM_CAPCTL_CAPINV2_Pos)                 /*!< EPWM_T::CAPCTL: CAPINV2 Mask            */
+
+#define EPWM_CAPCTL_CAPINV3_Pos           (11)                                              /*!< EPWM_T::CAPCTL: CAPINV3 Position        */
+#define EPWM_CAPCTL_CAPINV3_Msk           (0x1ul << EPWM_CAPCTL_CAPINV3_Pos)                 /*!< EPWM_T::CAPCTL: CAPINV3 Mask            */
+
+#define EPWM_CAPCTL_CAPINV4_Pos           (12)                                              /*!< EPWM_T::CAPCTL: CAPINV4 Position        */
+#define EPWM_CAPCTL_CAPINV4_Msk           (0x1ul << EPWM_CAPCTL_CAPINV4_Pos)                 /*!< EPWM_T::CAPCTL: CAPINV4 Mask            */
+
+#define EPWM_CAPCTL_CAPINV5_Pos           (13)                                              /*!< EPWM_T::CAPCTL: CAPINV5 Position        */
+#define EPWM_CAPCTL_CAPINV5_Msk           (0x1ul << EPWM_CAPCTL_CAPINV5_Pos)                 /*!< EPWM_T::CAPCTL: CAPINV5 Mask            */
+
+#define EPWM_CAPCTL_RCRLDEN0_Pos          (16)                                              /*!< EPWM_T::CAPCTL: RCRLDEN0 Position       */
+#define EPWM_CAPCTL_RCRLDEN0_Msk          (0x1ul << EPWM_CAPCTL_RCRLDEN0_Pos)                /*!< EPWM_T::CAPCTL: RCRLDEN0 Mask           */
+
+#define EPWM_CAPCTL_RCRLDEN1_Pos          (17)                                              /*!< EPWM_T::CAPCTL: RCRLDEN1 Position       */
+#define EPWM_CAPCTL_RCRLDEN1_Msk          (0x1ul << EPWM_CAPCTL_RCRLDEN1_Pos)                /*!< EPWM_T::CAPCTL: RCRLDEN1 Mask           */
+
+#define EPWM_CAPCTL_RCRLDEN2_Pos          (18)                                              /*!< EPWM_T::CAPCTL: RCRLDEN2 Position       */
+#define EPWM_CAPCTL_RCRLDEN2_Msk          (0x1ul << EPWM_CAPCTL_RCRLDEN2_Pos)                /*!< EPWM_T::CAPCTL: RCRLDEN2 Mask           */
+
+#define EPWM_CAPCTL_RCRLDEN3_Pos          (19)                                              /*!< EPWM_T::CAPCTL: RCRLDEN3 Position       */
+#define EPWM_CAPCTL_RCRLDEN3_Msk          (0x1ul << EPWM_CAPCTL_RCRLDEN3_Pos)                /*!< EPWM_T::CAPCTL: RCRLDEN3 Mask           */
+
+#define EPWM_CAPCTL_RCRLDEN4_Pos          (20)                                              /*!< EPWM_T::CAPCTL: RCRLDEN4 Position       */
+#define EPWM_CAPCTL_RCRLDEN4_Msk          (0x1ul << EPWM_CAPCTL_RCRLDEN4_Pos)                /*!< EPWM_T::CAPCTL: RCRLDEN4 Mask           */
+
+#define EPWM_CAPCTL_RCRLDEN5_Pos          (21)                                              /*!< EPWM_T::CAPCTL: RCRLDEN5 Position       */
+#define EPWM_CAPCTL_RCRLDEN5_Msk          (0x1ul << EPWM_CAPCTL_RCRLDEN5_Pos)                /*!< EPWM_T::CAPCTL: RCRLDEN5 Mask           */
+
+#define EPWM_CAPCTL_FCRLDEN0_Pos          (24)                                              /*!< EPWM_T::CAPCTL: FCRLDEN0 Position       */
+#define EPWM_CAPCTL_FCRLDEN0_Msk          (0x1ul << EPWM_CAPCTL_FCRLDEN0_Pos)                /*!< EPWM_T::CAPCTL: FCRLDEN0 Mask           */
+
+#define EPWM_CAPCTL_FCRLDEN1_Pos          (25)                                              /*!< EPWM_T::CAPCTL: FCRLDEN1 Position       */
+#define EPWM_CAPCTL_FCRLDEN1_Msk          (0x1ul << EPWM_CAPCTL_FCRLDEN1_Pos)                /*!< EPWM_T::CAPCTL: FCRLDEN1 Mask           */
+
+#define EPWM_CAPCTL_FCRLDEN2_Pos          (26)                                              /*!< EPWM_T::CAPCTL: FCRLDEN2 Position       */
+#define EPWM_CAPCTL_FCRLDEN2_Msk          (0x1ul << EPWM_CAPCTL_FCRLDEN2_Pos)                /*!< EPWM_T::CAPCTL: FCRLDEN2 Mask           */
+
+#define EPWM_CAPCTL_FCRLDEN3_Pos          (27)                                              /*!< EPWM_T::CAPCTL: FCRLDEN3 Position       */
+#define EPWM_CAPCTL_FCRLDEN3_Msk          (0x1ul << EPWM_CAPCTL_FCRLDEN3_Pos)                /*!< EPWM_T::CAPCTL: FCRLDEN3 Mask           */
+
+#define EPWM_CAPCTL_FCRLDEN4_Pos          (28)                                              /*!< EPWM_T::CAPCTL: FCRLDEN4 Position       */
+#define EPWM_CAPCTL_FCRLDEN4_Msk          (0x1ul << EPWM_CAPCTL_FCRLDEN4_Pos)                /*!< EPWM_T::CAPCTL: FCRLDEN4 Mask           */
+
+#define EPWM_CAPCTL_FCRLDEN5_Pos          (29)                                              /*!< EPWM_T::CAPCTL: FCRLDEN5 Position       */
+#define EPWM_CAPCTL_FCRLDEN5_Msk          (0x1ul << EPWM_CAPCTL_FCRLDEN5_Pos)                /*!< EPWM_T::CAPCTL: FCRLDEN5 Mask           */
+
+#define EPWM_CAPSTS_CRLIFOV0_Pos          (0)                                               /*!< EPWM_T::CAPSTS: CRLIFOV0 Position       */
+#define EPWM_CAPSTS_CRLIFOV0_Msk          (0x1ul << EPWM_CAPSTS_CRLIFOV0_Pos)                /*!< EPWM_T::CAPSTS: CRLIFOV0 Mask           */
+
+#define EPWM_CAPSTS_CRLIFOV1_Pos          (1)                                               /*!< EPWM_T::CAPSTS: CRLIFOV1 Position       */
+#define EPWM_CAPSTS_CRLIFOV1_Msk          (0x1ul << EPWM_CAPSTS_CRLIFOV1_Pos)                /*!< EPWM_T::CAPSTS: CRLIFOV1 Mask           */
+
+#define EPWM_CAPSTS_CRLIFOV2_Pos          (2)                                               /*!< EPWM_T::CAPSTS: CRLIFOV2 Position       */
+#define EPWM_CAPSTS_CRLIFOV2_Msk          (0x1ul << EPWM_CAPSTS_CRLIFOV2_Pos)                /*!< EPWM_T::CAPSTS: CRLIFOV2 Mask           */
+
+#define EPWM_CAPSTS_CRLIFOV3_Pos          (3)                                               /*!< EPWM_T::CAPSTS: CRLIFOV3 Position       */
+#define EPWM_CAPSTS_CRLIFOV3_Msk          (0x1ul << EPWM_CAPSTS_CRLIFOV3_Pos)                /*!< EPWM_T::CAPSTS: CRLIFOV3 Mask           */
+
+#define EPWM_CAPSTS_CRLIFOV4_Pos          (4)                                               /*!< EPWM_T::CAPSTS: CRLIFOV4 Position       */
+#define EPWM_CAPSTS_CRLIFOV4_Msk          (0x1ul << EPWM_CAPSTS_CRLIFOV4_Pos)                /*!< EPWM_T::CAPSTS: CRLIFOV4 Mask           */
+
+#define EPWM_CAPSTS_CRLIFOV5_Pos          (5)                                               /*!< EPWM_T::CAPSTS: CRLIFOV5 Position       */
+#define EPWM_CAPSTS_CRLIFOV5_Msk          (0x1ul << EPWM_CAPSTS_CRLIFOV5_Pos)                /*!< EPWM_T::CAPSTS: CRLIFOV5 Mask           */
+
+#define EPWM_CAPSTS_CFLIFOV0_Pos          (8)                                               /*!< EPWM_T::CAPSTS: CFLIFOV0 Position       */
+#define EPWM_CAPSTS_CFLIFOV0_Msk          (0x1ul << EPWM_CAPSTS_CFLIFOV0_Pos)                /*!< EPWM_T::CAPSTS: CFLIFOV0 Mask           */
+
+#define EPWM_CAPSTS_CFLIFOV1_Pos          (9)                                               /*!< EPWM_T::CAPSTS: CFLIFOV1 Position       */
+#define EPWM_CAPSTS_CFLIFOV1_Msk          (0x1ul << EPWM_CAPSTS_CFLIFOV1_Pos)                /*!< EPWM_T::CAPSTS: CFLIFOV1 Mask           */
+
+#define EPWM_CAPSTS_CFLIFOV2_Pos          (10)                                              /*!< EPWM_T::CAPSTS: CFLIFOV2 Position       */
+#define EPWM_CAPSTS_CFLIFOV2_Msk          (0x1ul << EPWM_CAPSTS_CFLIFOV2_Pos)                /*!< EPWM_T::CAPSTS: CFLIFOV2 Mask           */
+
+#define EPWM_CAPSTS_CFLIFOV3_Pos          (11)                                              /*!< EPWM_T::CAPSTS: CFLIFOV3 Position       */
+#define EPWM_CAPSTS_CFLIFOV3_Msk          (0x1ul << EPWM_CAPSTS_CFLIFOV3_Pos)                /*!< EPWM_T::CAPSTS: CFLIFOV3 Mask           */
+
+#define EPWM_CAPSTS_CFLIFOV4_Pos          (12)                                              /*!< EPWM_T::CAPSTS: CFLIFOV4 Position       */
+#define EPWM_CAPSTS_CFLIFOV4_Msk          (0x1ul << EPWM_CAPSTS_CFLIFOV4_Pos)                /*!< EPWM_T::CAPSTS: CFLIFOV4 Mask           */
+
+#define EPWM_CAPSTS_CFLIFOV5_Pos          (13)                                              /*!< EPWM_T::CAPSTS: CFLIFOV5 Position       */
+#define EPWM_CAPSTS_CFLIFOV5_Msk          (0x1ul << EPWM_CAPSTS_CFLIFOV5_Pos)                /*!< EPWM_T::CAPSTS: CFLIFOV5 Mask           */
+
+#define EPWM_RCAPDAT0_RCAPDAT_Pos         (0)                                               /*!< EPWM_T::RCAPDAT0: RCAPDAT Position      */
+#define EPWM_RCAPDAT0_RCAPDAT_Msk         (0xfffful << EPWM_RCAPDAT0_RCAPDAT_Pos)            /*!< EPWM_T::RCAPDAT0: RCAPDAT Mask          */
+
+#define EPWM_FCAPDAT0_FCAPDAT_Pos         (0)                                               /*!< EPWM_T::FCAPDAT0: FCAPDAT Position      */
+#define EPWM_FCAPDAT0_FCAPDAT_Msk         (0xfffful << EPWM_FCAPDAT0_FCAPDAT_Pos)            /*!< EPWM_T::FCAPDAT0: FCAPDAT Mask          */
+
+#define EPWM_RCAPDAT1_RCAPDAT_Pos         (0)                                               /*!< EPWM_T::RCAPDAT1: RCAPDAT Position      */
+#define EPWM_RCAPDAT1_RCAPDAT_Msk         (0xfffful << EPWM_RCAPDAT1_RCAPDAT_Pos)            /*!< EPWM_T::RCAPDAT1: RCAPDAT Mask          */
+
+#define EPWM_FCAPDAT1_FCAPDAT_Pos         (0)                                               /*!< EPWM_T::FCAPDAT1: FCAPDAT Position      */
+#define EPWM_FCAPDAT1_FCAPDAT_Msk         (0xfffful << EPWM_FCAPDAT1_FCAPDAT_Pos)            /*!< EPWM_T::FCAPDAT1: FCAPDAT Mask          */
+
+#define EPWM_RCAPDAT2_RCAPDAT_Pos         (0)                                               /*!< EPWM_T::RCAPDAT2: RCAPDAT Position      */
+#define EPWM_RCAPDAT2_RCAPDAT_Msk         (0xfffful << EPWM_RCAPDAT2_RCAPDAT_Pos)            /*!< EPWM_T::RCAPDAT2: RCAPDAT Mask          */
+
+#define EPWM_FCAPDAT2_FCAPDAT_Pos         (0)                                               /*!< EPWM_T::FCAPDAT2: FCAPDAT Position      */
+#define EPWM_FCAPDAT2_FCAPDAT_Msk         (0xfffful << EPWM_FCAPDAT2_FCAPDAT_Pos)            /*!< EPWM_T::FCAPDAT2: FCAPDAT Mask          */
+
+#define EPWM_RCAPDAT3_RCAPDAT_Pos         (0)                                               /*!< EPWM_T::RCAPDAT3: RCAPDAT Position      */
+#define EPWM_RCAPDAT3_RCAPDAT_Msk         (0xfffful << EPWM_RCAPDAT3_RCAPDAT_Pos)            /*!< EPWM_T::RCAPDAT3: RCAPDAT Mask          */
+
+#define EPWM_FCAPDAT3_FCAPDAT_Pos         (0)                                               /*!< EPWM_T::FCAPDAT3: FCAPDAT Position      */
+#define EPWM_FCAPDAT3_FCAPDAT_Msk         (0xfffful << EPWM_FCAPDAT3_FCAPDAT_Pos)            /*!< EPWM_T::FCAPDAT3: FCAPDAT Mask          */
+
+#define EPWM_RCAPDAT4_RCAPDAT_Pos         (0)                                               /*!< EPWM_T::RCAPDAT4: RCAPDAT Position      */
+#define EPWM_RCAPDAT4_RCAPDAT_Msk         (0xfffful << EPWM_RCAPDAT4_RCAPDAT_Pos)            /*!< EPWM_T::RCAPDAT4: RCAPDAT Mask          */
+
+#define EPWM_FCAPDAT4_FCAPDAT_Pos         (0)                                               /*!< EPWM_T::FCAPDAT4: FCAPDAT Position      */
+#define EPWM_FCAPDAT4_FCAPDAT_Msk         (0xfffful << EPWM_FCAPDAT4_FCAPDAT_Pos)            /*!< EPWM_T::FCAPDAT4: FCAPDAT Mask          */
+
+#define EPWM_RCAPDAT5_RCAPDAT_Pos         (0)                                               /*!< EPWM_T::RCAPDAT5: RCAPDAT Position      */
+#define EPWM_RCAPDAT5_RCAPDAT_Msk         (0xfffful << EPWM_RCAPDAT5_RCAPDAT_Pos)            /*!< EPWM_T::RCAPDAT5: RCAPDAT Mask          */
+
+#define EPWM_FCAPDAT5_FCAPDAT_Pos         (0)                                               /*!< EPWM_T::FCAPDAT5: FCAPDAT Position      */
+#define EPWM_FCAPDAT5_FCAPDAT_Msk         (0xfffful << EPWM_FCAPDAT5_FCAPDAT_Pos)            /*!< EPWM_T::FCAPDAT5: FCAPDAT Mask          */
+
+#define EPWM_PDMACTL_CHEN0_1_Pos          (0)                                               /*!< EPWM_T::PDMACTL: CHEN0_1 Position       */
+#define EPWM_PDMACTL_CHEN0_1_Msk          (0x1ul << EPWM_PDMACTL_CHEN0_1_Pos)                /*!< EPWM_T::PDMACTL: CHEN0_1 Mask           */
+
+#define EPWM_PDMACTL_CAPMOD0_1_Pos        (1)                                               /*!< EPWM_T::PDMACTL: CAPMOD0_1 Position     */
+#define EPWM_PDMACTL_CAPMOD0_1_Msk        (0x3ul << EPWM_PDMACTL_CAPMOD0_1_Pos)              /*!< EPWM_T::PDMACTL: CAPMOD0_1 Mask         */
+
+#define EPWM_PDMACTL_CAPORD0_1_Pos        (3)                                               /*!< EPWM_T::PDMACTL: CAPORD0_1 Position     */
+#define EPWM_PDMACTL_CAPORD0_1_Msk        (0x1ul << EPWM_PDMACTL_CAPORD0_1_Pos)              /*!< EPWM_T::PDMACTL: CAPORD0_1 Mask         */
+
+#define EPWM_PDMACTL_CHSEL0_1_Pos         (4)                                               /*!< EPWM_T::PDMACTL: CHSEL0_1 Position      */
+#define EPWM_PDMACTL_CHSEL0_1_Msk         (0x1ul << EPWM_PDMACTL_CHSEL0_1_Pos)               /*!< EPWM_T::PDMACTL: CHSEL0_1 Mask          */
+
+#define EPWM_PDMACTL_CHEN2_3_Pos          (8)                                               /*!< EPWM_T::PDMACTL: CHEN2_3 Position       */
+#define EPWM_PDMACTL_CHEN2_3_Msk          (0x1ul << EPWM_PDMACTL_CHEN2_3_Pos)                /*!< EPWM_T::PDMACTL: CHEN2_3 Mask           */
+
+#define EPWM_PDMACTL_CAPMOD2_3_Pos        (9)                                               /*!< EPWM_T::PDMACTL: CAPMOD2_3 Position     */
+#define EPWM_PDMACTL_CAPMOD2_3_Msk        (0x3ul << EPWM_PDMACTL_CAPMOD2_3_Pos)              /*!< EPWM_T::PDMACTL: CAPMOD2_3 Mask         */
+
+#define EPWM_PDMACTL_CAPORD2_3_Pos        (11)                                              /*!< EPWM_T::PDMACTL: CAPORD2_3 Position     */
+#define EPWM_PDMACTL_CAPORD2_3_Msk        (0x1ul << EPWM_PDMACTL_CAPORD2_3_Pos)              /*!< EPWM_T::PDMACTL: CAPORD2_3 Mask         */
+
+#define EPWM_PDMACTL_CHSEL2_3_Pos         (12)                                              /*!< EPWM_T::PDMACTL: CHSEL2_3 Position      */
+#define EPWM_PDMACTL_CHSEL2_3_Msk         (0x1ul << EPWM_PDMACTL_CHSEL2_3_Pos)               /*!< EPWM_T::PDMACTL: CHSEL2_3 Mask          */
+
+#define EPWM_PDMACTL_CHEN4_5_Pos          (16)                                              /*!< EPWM_T::PDMACTL: CHEN4_5 Position       */
+#define EPWM_PDMACTL_CHEN4_5_Msk          (0x1ul << EPWM_PDMACTL_CHEN4_5_Pos)                /*!< EPWM_T::PDMACTL: CHEN4_5 Mask           */
+
+#define EPWM_PDMACTL_CAPMOD4_5_Pos        (17)                                              /*!< EPWM_T::PDMACTL: CAPMOD4_5 Position     */
+#define EPWM_PDMACTL_CAPMOD4_5_Msk        (0x3ul << EPWM_PDMACTL_CAPMOD4_5_Pos)              /*!< EPWM_T::PDMACTL: CAPMOD4_5 Mask         */
+
+#define EPWM_PDMACTL_CAPORD4_5_Pos        (19)                                              /*!< EPWM_T::PDMACTL: CAPORD4_5 Position     */
+#define EPWM_PDMACTL_CAPORD4_5_Msk        (0x1ul << EPWM_PDMACTL_CAPORD4_5_Pos)              /*!< EPWM_T::PDMACTL: CAPORD4_5 Mask         */
+
+#define EPWM_PDMACTL_CHSEL4_5_Pos         (20)                                              /*!< EPWM_T::PDMACTL: CHSEL4_5 Position      */
+#define EPWM_PDMACTL_CHSEL4_5_Msk         (0x1ul << EPWM_PDMACTL_CHSEL4_5_Pos)               /*!< EPWM_T::PDMACTL: CHSEL4_5 Mask          */
+
+#define EPWM_PDMACAP0_1_CAPBUF_Pos        (0)                                               /*!< EPWM_T::PDMACAP0_1: CAPBUF Position     */
+#define EPWM_PDMACAP0_1_CAPBUF_Msk        (0xfffful << EPWM_PDMACAP0_1_CAPBUF_Pos)           /*!< EPWM_T::PDMACAP0_1: CAPBUF Mask         */
+
+#define EPWM_PDMACAP2_3_CAPBUF_Pos        (0)                                               /*!< EPWM_T::PDMACAP2_3: CAPBUF Position     */
+#define EPWM_PDMACAP2_3_CAPBUF_Msk        (0xfffful << EPWM_PDMACAP2_3_CAPBUF_Pos)           /*!< EPWM_T::PDMACAP2_3: CAPBUF Mask         */
+
+#define EPWM_PDMACAP4_5_CAPBUF_Pos        (0)                                               /*!< EPWM_T::PDMACAP4_5: CAPBUF Position     */
+#define EPWM_PDMACAP4_5_CAPBUF_Msk        (0xfffful << EPWM_PDMACAP4_5_CAPBUF_Pos)           /*!< EPWM_T::PDMACAP4_5: CAPBUF Mask         */
+
+#define EPWM_CAPIEN_CAPRIEN0_Pos          (0)                                               /*!< EPWM_T::CAPIEN: CAPRIEN0 Position       */
+#define EPWM_CAPIEN_CAPRIEN0_Msk          (0x1ul << EPWM_CAPIEN_CAPRIEN0_Pos)                /*!< EPWM_T::CAPIEN: CAPRIEN0 Mask           */
+
+#define EPWM_CAPIEN_CAPRIEN1_Pos          (1)                                               /*!< EPWM_T::CAPIEN: CAPRIEN1 Position       */
+#define EPWM_CAPIEN_CAPRIEN1_Msk          (0x1ul << EPWM_CAPIEN_CAPRIEN1_Pos)                /*!< EPWM_T::CAPIEN: CAPRIEN1 Mask           */
+
+#define EPWM_CAPIEN_CAPRIEN2_Pos          (2)                                               /*!< EPWM_T::CAPIEN: CAPRIEN2 Position       */
+#define EPWM_CAPIEN_CAPRIEN2_Msk          (0x1ul << EPWM_CAPIEN_CAPRIEN2_Pos)                /*!< EPWM_T::CAPIEN: CAPRIEN2 Mask           */
+
+#define EPWM_CAPIEN_CAPRIEN3_Pos          (3)                                               /*!< EPWM_T::CAPIEN: CAPRIEN3 Position       */
+#define EPWM_CAPIEN_CAPRIEN3_Msk          (0x1ul << EPWM_CAPIEN_CAPRIEN3_Pos)                /*!< EPWM_T::CAPIEN: CAPRIEN3 Mask           */
+
+#define EPWM_CAPIEN_CAPRIEN4_Pos          (4)                                               /*!< EPWM_T::CAPIEN: CAPRIEN4 Position       */
+#define EPWM_CAPIEN_CAPRIEN4_Msk          (0x1ul << EPWM_CAPIEN_CAPRIEN4_Pos)                /*!< EPWM_T::CAPIEN: CAPRIEN4 Mask           */
+
+#define EPWM_CAPIEN_CAPRIEN5_Pos          (5)                                               /*!< EPWM_T::CAPIEN: CAPRIEN5 Position       */
+#define EPWM_CAPIEN_CAPRIEN5_Msk          (0x1ul << EPWM_CAPIEN_CAPRIEN5_Pos)                /*!< EPWM_T::CAPIEN: CAPRIEN5 Mask           */
+
+#define EPWM_CAPIEN_CAPFIEN0_Pos          (8)                                               /*!< EPWM_T::CAPIEN: CAPFIEN0 Position       */
+#define EPWM_CAPIEN_CAPFIEN0_Msk          (0x1ul << EPWM_CAPIEN_CAPFIEN0_Pos)                /*!< EPWM_T::CAPIEN: CAPFIEN0 Mask           */
+
+#define EPWM_CAPIEN_CAPFIEN1_Pos          (9)                                               /*!< EPWM_T::CAPIEN: CAPFIEN1 Position       */
+#define EPWM_CAPIEN_CAPFIEN1_Msk          (0x1ul << EPWM_CAPIEN_CAPFIEN1_Pos)                /*!< EPWM_T::CAPIEN: CAPFIEN1 Mask           */
+
+#define EPWM_CAPIEN_CAPFIEN2_Pos          (10)                                              /*!< EPWM_T::CAPIEN: CAPFIEN2 Position       */
+#define EPWM_CAPIEN_CAPFIEN2_Msk          (0x1ul << EPWM_CAPIEN_CAPFIEN2_Pos)                /*!< EPWM_T::CAPIEN: CAPFIEN2 Mask           */
+
+#define EPWM_CAPIEN_CAPFIEN3_Pos          (11)                                              /*!< EPWM_T::CAPIEN: CAPFIEN3 Position       */
+#define EPWM_CAPIEN_CAPFIEN3_Msk          (0x1ul << EPWM_CAPIEN_CAPFIEN3_Pos)                /*!< EPWM_T::CAPIEN: CAPFIEN3 Mask           */
+
+#define EPWM_CAPIEN_CAPFIEN4_Pos          (12)                                              /*!< EPWM_T::CAPIEN: CAPFIEN4 Position       */
+#define EPWM_CAPIEN_CAPFIEN4_Msk          (0x1ul << EPWM_CAPIEN_CAPFIEN4_Pos)                /*!< EPWM_T::CAPIEN: CAPFIEN4 Mask           */
+
+#define EPWM_CAPIEN_CAPFIEN5_Pos          (13)                                              /*!< EPWM_T::CAPIEN: CAPFIEN5 Position       */
+#define EPWM_CAPIEN_CAPFIEN5_Msk          (0x1ul << EPWM_CAPIEN_CAPFIEN5_Pos)                /*!< EPWM_T::CAPIEN: CAPFIEN5 Mask           */
+
+#define EPWM_CAPIF_CRLIF0_Pos             (0)                                               /*!< EPWM_T::CAPIF: CRLIF0 Position          */
+#define EPWM_CAPIF_CRLIF0_Msk             (0x1ul << EPWM_CAPIF_CRLIF0_Pos)                   /*!< EPWM_T::CAPIF: CRLIF0 Mask              */
+
+#define EPWM_CAPIF_CRLIF1_Pos             (1)                                               /*!< EPWM_T::CAPIF: CRLIF1 Position          */
+#define EPWM_CAPIF_CRLIF1_Msk             (0x1ul << EPWM_CAPIF_CRLIF1_Pos)                   /*!< EPWM_T::CAPIF: CRLIF1 Mask              */
+
+#define EPWM_CAPIF_CRLIF2_Pos             (2)                                               /*!< EPWM_T::CAPIF: CRLIF2 Position          */
+#define EPWM_CAPIF_CRLIF2_Msk             (0x1ul << EPWM_CAPIF_CRLIF2_Pos)                   /*!< EPWM_T::CAPIF: CRLIF2 Mask              */
+
+#define EPWM_CAPIF_CRLIF3_Pos             (3)                                               /*!< EPWM_T::CAPIF: CRLIF3 Position          */
+#define EPWM_CAPIF_CRLIF3_Msk             (0x1ul << EPWM_CAPIF_CRLIF3_Pos)                   /*!< EPWM_T::CAPIF: CRLIF3 Mask              */
+
+#define EPWM_CAPIF_CRLIF4_Pos             (4)                                               /*!< EPWM_T::CAPIF: CRLIF4 Position          */
+#define EPWM_CAPIF_CRLIF4_Msk             (0x1ul << EPWM_CAPIF_CRLIF4_Pos)                   /*!< EPWM_T::CAPIF: CRLIF4 Mask              */
+
+#define EPWM_CAPIF_CRLIF5_Pos             (5)                                               /*!< EPWM_T::CAPIF: CRLIF5 Position          */
+#define EPWM_CAPIF_CRLIF5_Msk             (0x1ul << EPWM_CAPIF_CRLIF5_Pos)                   /*!< EPWM_T::CAPIF: CRLIF5 Mask              */
+
+#define EPWM_CAPIF_CFLIF0_Pos             (8)                                               /*!< EPWM_T::CAPIF: CFLIF0 Position          */
+#define EPWM_CAPIF_CFLIF0_Msk             (0x1ul << EPWM_CAPIF_CFLIF0_Pos)                   /*!< EPWM_T::CAPIF: CFLIF0 Mask              */
+
+#define EPWM_CAPIF_CFLIF1_Pos             (9)                                               /*!< EPWM_T::CAPIF: CFLIF1 Position          */
+#define EPWM_CAPIF_CFLIF1_Msk             (0x1ul << EPWM_CAPIF_CFLIF1_Pos)                   /*!< EPWM_T::CAPIF: CFLIF1 Mask              */
+
+#define EPWM_CAPIF_CFLIF2_Pos             (10)                                              /*!< EPWM_T::CAPIF: CFLIF2 Position          */
+#define EPWM_CAPIF_CFLIF2_Msk             (0x1ul << EPWM_CAPIF_CFLIF2_Pos)                   /*!< EPWM_T::CAPIF: CFLIF2 Mask              */
+
+#define EPWM_CAPIF_CFLIF3_Pos             (11)                                              /*!< EPWM_T::CAPIF: CFLIF3 Position          */
+#define EPWM_CAPIF_CFLIF3_Msk             (0x1ul << EPWM_CAPIF_CFLIF3_Pos)                   /*!< EPWM_T::CAPIF: CFLIF3 Mask              */
+
+#define EPWM_CAPIF_CFLIF4_Pos             (12)                                              /*!< EPWM_T::CAPIF: CFLIF4 Position          */
+#define EPWM_CAPIF_CFLIF4_Msk             (0x1ul << EPWM_CAPIF_CFLIF4_Pos)                   /*!< EPWM_T::CAPIF: CFLIF4 Mask              */
+
+#define EPWM_CAPIF_CFLIF5_Pos             (13)                                              /*!< EPWM_T::CAPIF: CFLIF5 Position          */
+#define EPWM_CAPIF_CFLIF5_Msk             (0x1ul << EPWM_CAPIF_CFLIF5_Pos)                   /*!< EPWM_T::CAPIF: CFLIF5 Mask              */
+
+#define EPWM_PBUF0_PBUF_Pos               (0)                                               /*!< EPWM_T::PBUF0: PBUF Position            */
+#define EPWM_PBUF0_PBUF_Msk               (0xfffful << EPWM_PBUF0_PBUF_Pos)                  /*!< EPWM_T::PBUF0: PBUF Mask                */
+
+#define EPWM_PBUF1_PBUF_Pos               (0)                                               /*!< EPWM_T::PBUF1: PBUF Position            */
+#define EPWM_PBUF1_PBUF_Msk               (0xfffful << EPWM_PBUF1_PBUF_Pos)                  /*!< EPWM_T::PBUF1: PBUF Mask                */
+
+#define EPWM_PBUF2_PBUF_Pos               (0)                                               /*!< EPWM_T::PBUF2: PBUF Position            */
+#define EPWM_PBUF2_PBUF_Msk               (0xfffful << EPWM_PBUF2_PBUF_Pos)                  /*!< EPWM_T::PBUF2: PBUF Mask                */
+
+#define EPWM_PBUF3_PBUF_Pos               (0)                                               /*!< EPWM_T::PBUF3: PBUF Position            */
+#define EPWM_PBUF3_PBUF_Msk               (0xfffful << EPWM_PBUF3_PBUF_Pos)                  /*!< EPWM_T::PBUF3: PBUF Mask                */
+
+#define EPWM_PBUF4_PBUF_Pos               (0)                                               /*!< EPWM_T::PBUF4: PBUF Position            */
+#define EPWM_PBUF4_PBUF_Msk               (0xfffful << EPWM_PBUF4_PBUF_Pos)                  /*!< EPWM_T::PBUF4: PBUF Mask                */
+
+#define EPWM_PBUF5_PBUF_Pos               (0)                                               /*!< EPWM_T::PBUF5: PBUF Position            */
+#define EPWM_PBUF5_PBUF_Msk               (0xfffful << EPWM_PBUF5_PBUF_Pos)                  /*!< EPWM_T::PBUF5: PBUF Mask                */
+
+#define EPWM_CMPBUF0_CMPBUF_Pos           (0)                                               /*!< EPWM_T::CMPBUF0: CMPBUF Position        */
+#define EPWM_CMPBUF0_CMPBUF_Msk           (0xfffful << EPWM_CMPBUF0_CMPBUF_Pos)              /*!< EPWM_T::CMPBUF0: CMPBUF Mask            */
+
+#define EPWM_CMPBUF1_CMPBUF_Pos           (0)                                               /*!< EPWM_T::CMPBUF1: CMPBUF Position        */
+#define EPWM_CMPBUF1_CMPBUF_Msk           (0xfffful << EPWM_CMPBUF1_CMPBUF_Pos)              /*!< EPWM_T::CMPBUF1: CMPBUF Mask            */
+
+#define EPWM_CMPBUF2_CMPBUF_Pos           (0)                                               /*!< EPWM_T::CMPBUF2: CMPBUF Position        */
+#define EPWM_CMPBUF2_CMPBUF_Msk           (0xfffful << EPWM_CMPBUF2_CMPBUF_Pos)              /*!< EPWM_T::CMPBUF2: CMPBUF Mask            */
+
+#define EPWM_CMPBUF3_CMPBUF_Pos           (0)                                               /*!< EPWM_T::CMPBUF3: CMPBUF Position        */
+#define EPWM_CMPBUF3_CMPBUF_Msk           (0xfffful << EPWM_CMPBUF3_CMPBUF_Pos)              /*!< EPWM_T::CMPBUF3: CMPBUF Mask            */
+
+#define EPWM_CMPBUF4_CMPBUF_Pos           (0)                                               /*!< EPWM_T::CMPBUF4: CMPBUF Position        */
+#define EPWM_CMPBUF4_CMPBUF_Msk           (0xfffful << EPWM_CMPBUF4_CMPBUF_Pos)              /*!< EPWM_T::CMPBUF4: CMPBUF Mask            */
+
+#define EPWM_CMPBUF5_CMPBUF_Pos           (0)                                               /*!< EPWM_T::CMPBUF5: CMPBUF Position        */
+#define EPWM_CMPBUF5_CMPBUF_Msk           (0xfffful << EPWM_CMPBUF5_CMPBUF_Pos)              /*!< EPWM_T::CMPBUF5: CMPBUF Mask            */
+
+#define EPWM_CPSCBUF0_1_CPSCBUF_Pos       (0)                                               /*!< EPWM_T::CPSCBUF0_1: CPSCBUF Position    */
+#define EPWM_CPSCBUF0_1_CPSCBUF_Msk       (0xffful << EPWM_CPSCBUF0_1_CPSCBUF_Pos)           /*!< EPWM_T::CPSCBUF0_1: CPSCBUF Mask        */
+
+#define EPWM_CPSCBUF2_3_CPSCBUF_Pos       (0)                                               /*!< EPWM_T::CPSCBUF2_3: CPSCBUF Position    */
+#define EPWM_CPSCBUF2_3_CPSCBUF_Msk       (0xffful << EPWM_CPSCBUF2_3_CPSCBUF_Pos)           /*!< EPWM_T::CPSCBUF2_3: CPSCBUF Mask        */
+
+#define EPWM_CPSCBUF4_5_CPSCBUF_Pos       (0)                                               /*!< EPWM_T::CPSCBUF4_5: CPSCBUF Position    */
+#define EPWM_CPSCBUF4_5_CPSCBUF_Msk       (0xffful << EPWM_CPSCBUF4_5_CPSCBUF_Pos)           /*!< EPWM_T::CPSCBUF4_5: CPSCBUF Mask        */
+
+#define EPWM_FTCBUF0_1_FTCMPBUF_Pos       (0)                                               /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Position    */
+#define EPWM_FTCBUF0_1_FTCMPBUF_Msk       (0xfffful << EPWM_FTCBUF0_1_FTCMPBUF_Pos)          /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Mask        */
+
+#define EPWM_FTCBUF2_3_FTCMPBUF_Pos       (0)                                               /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Position    */
+#define EPWM_FTCBUF2_3_FTCMPBUF_Msk       (0xfffful << EPWM_FTCBUF2_3_FTCMPBUF_Pos)          /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Mask        */
+
+#define EPWM_FTCBUF4_5_FTCMPBUF_Pos       (0)                                               /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Position    */
+#define EPWM_FTCBUF4_5_FTCMPBUF_Msk       (0xfffful << EPWM_FTCBUF4_5_FTCMPBUF_Pos)          /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Mask        */
+
+#define EPWM_FTCI_FTCMU0_Pos              (0)                                               /*!< EPWM_T::FTCI: FTCMU0 Position           */
+#define EPWM_FTCI_FTCMU0_Msk              (0x1ul << EPWM_FTCI_FTCMU0_Pos)                    /*!< EPWM_T::FTCI: FTCMU0 Mask               */
+
+#define EPWM_FTCI_FTCMU2_Pos              (1)                                               /*!< EPWM_T::FTCI: FTCMU2 Position           */
+#define EPWM_FTCI_FTCMU2_Msk              (0x1ul << EPWM_FTCI_FTCMU2_Pos)                    /*!< EPWM_T::FTCI: FTCMU2 Mask               */
+
+#define EPWM_FTCI_FTCMU4_Pos              (2)                                               /*!< EPWM_T::FTCI: FTCMU4 Position           */
+#define EPWM_FTCI_FTCMU4_Msk              (0x1ul << EPWM_FTCI_FTCMU4_Pos)                    /*!< EPWM_T::FTCI: FTCMU4 Mask               */
+
+#define EPWM_FTCI_FTCMD0_Pos              (8)                                               /*!< EPWM_T::FTCI: FTCMD0 Position           */
+#define EPWM_FTCI_FTCMD0_Msk              (0x1ul << EPWM_FTCI_FTCMD0_Pos)                    /*!< EPWM_T::FTCI: FTCMD0 Mask               */
+
+#define EPWM_FTCI_FTCMD2_Pos              (9)                                               /*!< EPWM_T::FTCI: FTCMD2 Position           */
+#define EPWM_FTCI_FTCMD2_Msk              (0x1ul << EPWM_FTCI_FTCMD2_Pos)                    /*!< EPWM_T::FTCI: FTCMD2 Mask               */
+
+#define EPWM_FTCI_FTCMD4_Pos              (10)                                              /*!< EPWM_T::FTCI: FTCMD4 Position           */
+#define EPWM_FTCI_FTCMD4_Msk              (0x1ul << EPWM_FTCI_FTCMD4_Pos)                    /*!< EPWM_T::FTCI: FTCMD4 Mask               */
+
+/**@}*/ /* EPWM_CONST */
+/**@}*/ /* end of EPWM register group */
+/**@}*/ /* end of REGISTER group */
+
+
+
+#endif /* __EPWM_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/ewdt_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/ewdt_reg.h
new file mode 100644
index 0000000000..b8585af630
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/ewdt_reg.h
@@ -0,0 +1,178 @@
+/**************************************************************************//**
+ * @file     ewdt_reg.h
+ * @version  V1.00
+ * @brief    EWDT register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __EWDT_REG_H__
+#define __EWDT_REG_H__
+
+/**
+  @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+
+/*---------------------- Extra Watch Dog Timer Controller -------------------------*/
+/**
+  @addtogroup EWDT Extra Watch Dog Timer Controller(EWDT)
+  Memory Mapped Structure for EWDT Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var EWDT_T::CTL
+     * Offset: 0x00  EWDT Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1]     |RSTEN     |EWDT Time-out Reset Enable Control (Write Protect)
+     * |        |          |Setting this bit will enable the EWDT time-out reset system function If the EWDT up counter value has not been cleared after the specific EWDT reset delay period expires.
+     * |        |          |0 = EWDT time-out reset system function Disabled.
+     * |        |          |1 = EWDT time-out reset system function Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[2]     |RSTF      |EWDT Time-out Reset Flag
+     * |        |          |This bit indicates the system has been reset by EWDT time-out reset system event or not.
+     * |        |          |0 = EWDT time-out reset system event did not occur.
+     * |        |          |1 = EWDT time-out reset system event has been occurred.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[3]     |IF        |EWDT Time-out Interrupt Flag
+     * |        |          |This bit will set to 1 while EWDT up counter value reaches the selected EWDT time-out interval
+     * |        |          |0 = EWDT time-out interrupt event interrupt did not occur.
+     * |        |          |1 = EWDT time-out interrupt interrupt event occurred.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[4]     |WKEN      |EWDT Time-out Wake-up Function Control (Write Protect)
+     * |        |          |If this bit is set to 1, while EWDT time-out interrupt flag IF (EWDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (EWDT_CTL[6]) is enabled, the EWDT time-out interrupt signal will generate a event to trigger CPU wake-up trigger event to chip.
+     * |        |          |0 = Trigger Wake-up trigger event function Disabled if EWDT time-out interrupt signal generated.
+     * |        |          |1 = Trigger Wake-up trigger event function Enabled if EWDT time-out interrupt signal generated.
+     * |        |          |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note2: Chip can be woken-up by while EWDT time-out interrupt signal generated only if EWDT clock source is selected to LIRC or LXT (32 kHz).
+     * |[5]     |WKF       |EWDT Time-out Wake-up Flag (Write Protect)
+     * |        |          |This bit indicates the EWDT time-out event has triggered interrupt chip wake-up or not.flag status of EWDT
+     * |        |          |0 = WDT does not cause chip wake-up.
+     * |        |          |1 = Chip wake-up from Idle or Power-down mode if when WDT time-out interrupt signal is generated.
+     * |        |          |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note2: This bit is cleared by writing 1 to it.
+     * |[6]     |INTEN     |WDT Time-out Interrupt Enable Control (Write Protect)
+     * |        |          |If this bit is enabled, when WDT time-out event occurs, the IF (WDT_CTL[3]) will be set to 1 and the WDT time-out interrupt signal is generated and inform to CPU.
+     * |        |          |0 = WDT time-out interrupt Disabled.
+     * |        |          |1 = WDT time-out interrupt Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[7]     |WDTEN     |WDT Enable Control (Write Protect)
+     * |        |          |0 = Set WDT counter stop Disabled, and (This action will reset the internal up counter value will be reset also).
+     * |        |          |1 = Set WDT counter start Enabled.
+     * |        |          |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note2: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period to become active, user can read SYNC (WDT_CTL[30]) to check enable/disable command is completed or not.
+     * |        |          |Note32: If CWDTEN[2:0] (combined by with Config0[31] and Config0[4:3]) bits is not configure to 0x111, this bit is forced as 1 and user cannot change this bit to 0.
+     * |        |          |Note3: This bit disabled needs 2 * WDT_CLK.
+     * |[11:8]  |TOUTSEL   |WDT Time-out Interval Selection (Write Protect)
+     * |        |          |These three bits select the time-out interval period after for the WDT starts counting.
+     * |        |          |000 = 2^4 * WDT_CLK.
+     * |        |          |001 = 2^6 * WDT_CLK.
+     * |        |          |010 = 2^8 * WDT_CLK.
+     * |        |          |011 = 2^10 * WDT_CLK.
+     * |        |          |100 = 2^12 * WDT_CLK.
+     * |        |          |101 = 2^14 * WDT_CLK.
+     * |        |          |110 = 2^16 * WDT_CLK.
+     * |        |          |111 = 2^18 * WDT_CLK.
+     * |        |          |111 = 2^20 * WDT_CLK.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[30]    |SYNC      |WDT Enable Control SYNC SYNC Flag Indicator (Read Only)
+     * |        |          |If use to synchronization, software er can check execute enable/disable this flag after enable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is become completed or not active or not..
+     * |        |          |SYNC delay is
+     * |        |          |0 = Set WDTEN bit is WDT enable control synccompletedhronizing is completion.
+     * |        |          |1 = Set WDTEN bit WDT enable control is synchronizing and not become active yet..
+     * |        |          |Note: Perform enable or disable WDTEN bit
+     * |        |          |This bit enabled needs 2 * WDT_CLK period to become active.
+     * |[31]    |ICEDEBUG  |ICE Debug Mode Acknowledge Disable Control (Write Protect)
+     * |        |          |0 = ICE debug mode acknowledgment affects WDT counting.
+     * |        |          |WDT up counter will be held while CPU is held by ICE.
+     * |        |          |1 = ICE debug mode acknowledgment Disabled.
+     * |        |          |WDT up counter will keep going no matter CPU is held by ICE or not.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * @var EWDT_T::ALTCTL
+     * Offset: 0x04  EWDT Alternative Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |RSTDSEL   |WDT Reset Delay Period Selection (Write Protect)
+     * |        |          |When WDT time-out event happened, user has a time named WDT Reset Delay Period to clear execute WDT counter by setting RSTCNT (WDT_CTL[0]) reset to prevent WDT time-out reset system occurred happened
+     * |        |          |User can select a suitable setting of RSTDSEL for different application program WDT Reset Delay Period.
+     * |        |          |00 = WDT Reset Delay Period is 1026 * WDT_CLK.
+     * |        |          |01 = WDT Reset Delay Period is 130 * WDT_CLK.
+     * |        |          |10 = WDT Reset Delay Period is 18 * WDT_CLK.
+     * |        |          |11 = WDT Reset Delay Period is 3 * WDT_CLK.
+     * |        |          |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note2: This register will be reset to 0 if WDT time-out reset system event occurred happened.
+     * @var EWDT_T::RSTCNT
+     * Offset: 0x08  EWDT Reset Counter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |RSTCNT    |WDT Reset Counter Register
+     * |        |          |Writing 0x00005AA5 to this register field will reset the internal 18-bit WDT up counter value to 0.
+     * |        |          |Note: This WDT_RSTCNT is not write protected, but this RSTCNT (WDT_CTL[0]) is write protected.
+     * |        |          |Note: Perform RSTCNT to reset counter needs 2 * WDT_CLK period to become active.
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] EWDT Control Register                                             */
+    __IO uint32_t ALTCTL;                /*!< [0x0004] EWDT Alternative Control Register                                 */
+    __O  uint32_t RSTCNT;                /*!< [0x0008] EWDT Reset Counter Register                                       */
+
+} EWDT_T;
+
+/**
+  @addtogroup EWDT_CONST WDT Bit Field Definition
+  Constant Definitions for EWDT Controller
+  @{
+*/
+
+#define EWDT_CTL_RSTEN_Pos                (1)                                               /*!< EWDT_T::CTL: RSTEN Position             */
+#define EWDT_CTL_RSTEN_Msk                (0x1ul << EWDT_CTL_RSTEN_Pos)                     /*!< EWDT_T::CTL: RSTEN Mask                 */
+
+#define EWDT_CTL_RSTF_Pos                 (2)                                               /*!< EWDT_T::CTL: RSTF Position              */
+#define EWDT_CTL_RSTF_Msk                 (0x1ul << EWDT_CTL_RSTF_Pos)                      /*!< EWDT_T::CTL: RSTF Mask                  */
+
+#define EWDT_CTL_IF_Pos                   (3)                                               /*!< EWDT_T::CTL: IF Position                */
+#define EWDT_CTL_IF_Msk                   (0x1ul << EWDT_CTL_IF_Pos)                        /*!< EWDT_T::CTL: IF Mask                    */
+
+#define EWDT_CTL_WKEN_Pos                 (4)                                               /*!< EWDT_T::CTL: WKEN Position              */
+#define EWDT_CTL_WKEN_Msk                 (0x1ul << EWDT_CTL_WKEN_Pos)                      /*!< EWDT_T::CTL: WKEN Mask                  */
+
+#define EWDT_CTL_WKF_Pos                  (5)                                               /*!< EWDT_T::CTL: WKF Position               */
+#define EWDT_CTL_WKF_Msk                  (0x1ul << EWDT_CTL_WKF_Pos)                       /*!< EWDT_T::CTL: WKF Mask                   */
+
+#define EWDT_CTL_INTEN_Pos                (6)                                               /*!< EWDT_T::CTL: INTEN Position             */
+#define EWDT_CTL_INTEN_Msk                (0x1ul << EWDT_CTL_INTEN_Pos)                     /*!< EWDT_T::CTL: INTEN Mask                 */
+
+#define EWDT_CTL_WDTEN_Pos                (7)                                               /*!< EWDT_T::CTL: WDTEN Position             */
+#define EWDT_CTL_WDTEN_Msk                (0x1ul << EWDT_CTL_WDTEN_Pos)                     /*!< EWDT_T::CTL: WDTEN Mask                 */
+
+#define EWDT_CTL_TOUTSEL_Pos              (8)                                               /*!< EWDT_T::CTL: TOUTSEL Position           */
+#define EWDT_CTL_TOUTSEL_Msk              (0xful << EWDT_CTL_TOUTSEL_Pos)                   /*!< EWDT_T::CTL: TOUTSEL Mask               */
+
+#define EWDT_CTL_SYNC_Pos                 (30)                                              /*!< EWDT_T::CTL: SYNC Position              */
+#define EWDT_CTL_SYNC_Msk                 (0x1ul << EWDT_CTL_SYNC_Pos)                      /*!< EWDT_T::CTL: SYNC Mask                  */
+
+#define EWDT_CTL_ICEDEBUG_Pos             (31)                                              /*!< EWDT_T::CTL: ICEDEBUG Position          */
+#define EWDT_CTL_ICEDEBUG_Msk             (0x1ul << EWDT_CTL_ICEDEBUG_Pos)                  /*!< EWDT_T::CTL: ICEDEBUG Mask              */
+
+#define EWDT_ALTCTL_RSTDSEL_Pos           (0)                                               /*!< EWDT_T::ALTCTL: RSTDSEL Position        */
+#define EWDT_ALTCTL_RSTDSEL_Msk           (0x3ul << EWDT_ALTCTL_RSTDSEL_Pos)                /*!< EWDT_T::ALTCTL: RSTDSEL Mask            */
+
+#define EWDT_RSTCNT_RSTCNT_Pos            (0)                                               /*!< EWDT_T::RSTCNT: RSTCNT Position         */
+#define EWDT_RSTCNT_RSTCNT_Msk            (0xfffffffful << EWDT_RSTCNT_RSTCNT_Pos)          /*!< EWDT_T::RSTCNT: RSTCNT Mask             */
+
+
+/**@}*/ /* EWDT_CONST */
+/**@}*/ /* end of EWDT register group */
+/**@}*/ /* end of REGISTER group */
+
+#endif /* __EWDT_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/ewwdt_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/ewwdt_reg.h
new file mode 100644
index 0000000000..3331ccb6ea
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/ewwdt_reg.h
@@ -0,0 +1,148 @@
+/**************************************************************************//**
+ * @file     ewwdt_reg.h
+ * @version  V1.00
+ * @brief    EWWDT register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __EWWDT_REG_H__
+#define __EWWDT_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+
+/*---------------------- Extra Window Watchdog Timer -------------------------*/
+/**
+    @addtogroup EWWDT Extra Window Watchdog Timer(EWWDT)
+    Memory Mapped Structure for EWWDT Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var EWWDT_T::RLDCNT
+     * Offset: 0x00  WWDT Reload Counter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |RLDCNT    |WWDT Reload Counter Register
+     * |        |          |Writing only 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.
+     * |        |          |Note1: User can only write execute WWDT_RLDCNT register to the reload WWDT counter value command when current current WWDT counter value CNTDAT (WWDT_CNT[5:0]) is between 10 and CMPDAT (WWDT_CTL[21:16])
+     * |        |          |If user writes 0x00005AA5 in WWDT_RLDCNT register when current current CNTDATWWDT counter value is larger than CMPDAT, WWDT reset signal system event will be generated immediately.
+     * |        |          |Note2: Execute WWDT counter reload always needs (WWDT_CLK *3) period to reload CNTDAT to 0x3F and internal prescale counter will be reset also.
+     * @var EWWDT_T::CTL
+     * Offset: 0x04  WWDT Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WWDTEN    |WWDT Enable Control Bit
+     * |        |          |Set this bit to enable start WWDT counter counting.
+     * |        |          |0 = WWDT counter is stopped.
+     * |        |          |1 = WWDT counter is starting counting.
+     * |[1]     |INTEN     |WWDT Interrupt Enable Control Bit
+     * |        |          |If this bit is enabled, when WWDTIF (WWDT_STATUS[0]) is set to 1, the WWDT counter compare match interrupt signal is generated and inform to CPU.
+     * |        |          |0 = WWDT counter compare match interrupt Disabled.
+     * |        |          |1 = WWDT counter compare match interrupt Enabled.
+     * |[11:8]  |PSCSEL    |WWDT Counter Prescale Period Selection
+     * |        |          |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK.
+     * |        |          |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK.
+     * |        |          |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK.
+     * |        |          |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK.
+     * |        |          |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK.
+     * |        |          |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK.
+     * |        |          |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK.
+     * |        |          |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK.
+     * |        |          |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK.
+     * |        |          |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK.
+     * |        |          |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK.
+     * |        |          |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK.
+     * |        |          |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK.
+     * |        |          |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK.
+     * |        |          |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK.
+     * |        |          |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK.
+     * |[21:16] |CMPDAT    |WWDT Window Compare Register Value
+     * |        |          |Set this register field to adjust the valid reload window interval when WWDTIF (WWDT_STATUS[0]) is generated..
+     * |        |          |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT CNTDAT (WWDT_CNT[5:]) is counter value between 10 and CMPDAT
+     * |        |          |If user writes 0x00005AA5 in WWDT_RLDCNT register when current WWDT counter value CNTDAT is larger than CMPDAT, WWDT reset system event signal will be generated immediately.
+     * |[31]    |ICEDEBUG  |ICE Debug Mode Acknowledge Disable Control
+     * |        |          |0 = ICE debug mode acknowledgment effects WWDT counter counting.
+     * |        |          |WWDT down counter will be held while CPU is held by ICE.
+     * |        |          |1 = ICE debug mode acknowledgment Disabled.
+     * |        |          |WWDT down counter will keep going counting no matter CPU is held by ICE or not.
+     * @var EWWDT_T::STATUS
+     * Offset: 0x08  WWDT Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WWDTIF    |WWDT Compare Match Interrupt Flag
+     * |        |          |This bit indicates the that current CNTDAT (WWDT_CNT[5:0]) matches the CMPDAT (WWDT_CTL[21:16])interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).
+     * |        |          |0 = No effect.
+     * |        |          |1 = WWDT WWDT CNTDAT counter value matches the CMPDAT.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[1]     |WWDTRF    |WWDT Timer-out Reset System Flag
+     * |        |          |If this bit is set to 1, it This bit indicates the that system has been reset by WWDT counter time-out reset system event.or not.
+     * |        |          |0 = WWDT time-out reset system event did not occur.
+     * |        |          |1 = WWDT time-out reset system event occurred.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * @var EWWDT_T::CNT
+     * Offset: 0x0C  WWDT Counter Value Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[5:0]   |CNTDAT    |WWDT Counter Value
+     * |        |          |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value.
+     */
+    __O  uint32_t RLDCNT;                /*!< [0x0000] EWWDT Reload Counter Register                                     */
+    __IO uint32_t CTL;                   /*!< [0x0004] EWWDT Control Register                                            */
+    __IO uint32_t STATUS;                /*!< [0x0008] EWWDT Status Register                                             */
+    __I  uint32_t CNT;                   /*!< [0x000c] EWWDT Counter Value Register                                      */
+
+} EWWDT_T;
+
+
+/**
+    @addtogroup WWDT_CONST WWDT Bit Field Definition
+    Constant Definitions for WWDT Controller
+  @{
+*/
+
+#define EWWDT_RLDCNT_RLDCNT_Pos           (0)                                               /*!< EWWDT_T::RLDCNT: RLDCNT Position        */
+#define EWWDT_RLDCNT_RLDCNT_Msk           (0xfffffffful << EWWDT_RLDCNT_RLDCNT_Pos)         /*!< EWWDT_T::RLDCNT: RLDCNT Mask            */
+
+#define EWWDT_CTL_WWDTEN_Pos              (0)                                               /*!< EWWDT_T::CTL: WWDTEN Position           */
+#define EWWDT_CTL_WWDTEN_Msk              (0x1ul << EWWDT_CTL_WWDTEN_Pos)                   /*!< EWWDT_T::CTL: WWDTEN Mask               */
+
+#define EWWDT_CTL_INTEN_Pos               (1)                                               /*!< EWWDT_T::CTL: INTEN Position            */
+#define EWWDT_CTL_INTEN_Msk               (0x1ul << EWWDT_CTL_INTEN_Pos)                    /*!< EWWDT_T::CTL: INTEN Mask                */
+
+#define EWWDT_CTL_PSCSEL_Pos              (8)                                               /*!< EWWDT_T::CTL: PSCSEL Position           */
+#define EWWDT_CTL_PSCSEL_Msk              (0xful << EWWDT_CTL_PSCSEL_Pos)                   /*!< EWWDT_T::CTL: PSCSEL Mask               */
+
+#define EWWDT_CTL_CMPDAT_Pos              (16)                                              /*!< EWWDT_T::CTL: CMPDAT Position           */
+#define EWWDT_CTL_CMPDAT_Msk              (0x3ful << EWWDT_CTL_CMPDAT_Pos)                  /*!< EWWDT_T::CTL: CMPDAT Mask               */
+
+#define EWWDT_CTL_ICEDEBUG_Pos            (31)                                              /*!< EWWDT_T::CTL: ICEDEBUG Position         */
+#define EWWDT_CTL_ICEDEBUG_Msk            (0x1ul << EWWDT_CTL_ICEDEBUG_Pos)                 /*!< EWWDT_T::CTL: ICEDEBUG Mask             */
+
+#define EWWDT_STATUS_WWDTIF_Pos           (0)                                               /*!< EWWDT_T::STATUS: WWDTIF Position        */
+#define EWWDT_STATUS_WWDTIF_Msk           (0x1ul << EWWDT_STATUS_WWDTIF_Pos)                /*!< EWWDT_T::STATUS: WWDTIF Mask            */
+
+#define EWWDT_STATUS_WWDTRF_Pos           (1)                                               /*!< EWWDT_T::STATUS: WWDTRF Position        */
+#define EWWDT_STATUS_WWDTRF_Msk           (0x1ul << EWWDT_STATUS_WWDTRF_Pos)                /*!< EWWDT_T::STATUS: WWDTRF Mask            */
+
+#define EWWDT_CNT_CNTDAT_Pos              (0)                                               /*!< EWWDT_T::CNT: CNTDAT Position           */
+#define EWWDT_CNT_CNTDAT_Msk              (0x3ful << EWWDT_CNT_CNTDAT_Pos)                  /*!< EWWDT_T::CNT: CNTDAT Mask               */
+
+/**@}*/ /* EWWDT_CONST */
+/**@}*/ /* end of EWWDT register group */
+/**@}*/ /* end of REGISTER group */
+
+#endif /* __EWWDT_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/fmc_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/fmc_reg.h
new file mode 100644
index 0000000000..95cde7b889
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/fmc_reg.h
@@ -0,0 +1,628 @@
+/**************************************************************************//**
+ * @file     fmc_reg.h
+ * @version  V1.00
+ * @brief    FMC register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __FMC_REG_H__
+#define __FMC_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+
+/*---------------------- Flash Memory Controller -------------------------*/
+/**
+    @addtogroup FMC Flash Memory Controller(FMC)
+    Memory Mapped Structure for FMC Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var FMC_T::ISPCTL
+     * Offset: 0x00  ISP Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ISPEN     |ISP Enable Bit (Write Protect)
+     * |        |          |ISP function enable bit. Set this bit to enable ISP function.
+     * |        |          |0 = ISP function Disabled.
+     * |        |          |1 = ISP function Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[1]     |BS        |Boot Select (Write Protect)
+     * |        |          |When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively
+     * |        |          |This bit also functions as chip booting status flag, which can be used to check where chip booted from
+     * |        |          |This bit is initiated with the inverse value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened
+     * |        |          |0 = Booting from APROM when MBS (CONFIG0[5]) is 1.
+     * |        |          |1 = Booting from LDROM when MBS (CONFIG0[5]) is 1.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[3]     |APUEN     |APROM Update Enable Bit (Write Protect)
+     * |        |          |0 = APROM cannot be updated when the chip runs in APROM.
+     * |        |          |1 = APROM can be updated when the chip runs in APROM.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[4]     |CFGUEN    |CONFIG Update Enable Bit (Write Protect)
+     * |        |          |0 = CONFIG cannot be updated.
+     * |        |          |1 = CONFIG can be updated.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[5]     |LDUEN     |LDROM Update Enable Bit (Write Protect)
+     * |        |          |LDROM update enable bit.
+     * |        |          |0 = LDROM cannot be updated.
+     * |        |          |1 = LDROM can be updated.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[6]     |ISPFF     |ISP Fail Flag (Write Protect)
+     * |        |          |This bit is set by hardware when a triggered ISP meets any of the following conditions:
+     * |        |          |This bit needs to be cleared by writing 1 to it.
+     * |        |          |(1) APROM writes to itself if APUEN is set to 0.
+     * |        |          |(2) LDROM writes to itself if LDUEN is set to 0.
+     * |        |          |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
+     * |        |          |(4) Page Erase command at LOCK mode with ICE connection
+     * |        |          |(5) Erase or Program command at brown-out detected
+     * |        |          |(6) Destination address is illegal, such as over an available range.
+     * |        |          |(7) Invalid ISP commands
+     * |        |          |(8) KPROM is erased/programmed if KEYLOCK is set to 1
+     * |        |          |(9) APROM is erased/programmed if KEYLOCK is set to 1
+     * |        |          |(10) LDROM is erased/programmed if KEYLOCK is set to 1
+     * |        |          |(11) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[0] is 0
+     * |        |          |(12) Read any content of boot loader with ICE connection
+     * |        |          |(13) The address of block erase and bank erase is not in APROM
+     * |        |          |(14) ISP CMD in XOM region, except mass erase, page erase and chksum command
+     * |        |          |(15) The wrong setting of page erase ISP CMD in XOM
+     * |        |          |(16) Violate XOM setting one time protection
+     * |        |          |(17) Page erase ISP CMD in Secure/Non-secure region setting page
+     * |        |          |(18) Mass erase when MERASE (CFG0[13]) is disable
+     * |        |          |(19) Page erase, mass erase , multi-word program or 64-bit word program in OTP
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[16]    |BL        |Boot Loader Booting (Write Protect)
+     * |        |          |This bit is initiated with the inverses value of MBS (CONFIG0[5])
+     * |        |          |Any reset, except CPU reset (CPU is 1) or system reset (SYS), BL will be reloaded
+     * |        |          |This bit is used to check chip boot from Boot Loader or not
+     * |        |          |User should keep original value of this bit when updating FMC_ISPCTL register.
+     * |        |          |0 = Booting from APROM or LDROM.
+     * |        |          |1 = Booting from Boot Loader.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[24]    |INTEN     |Interrupt Enable (Write Protect)
+     * |        |          |0 = ISP INT Disabled.
+     * |        |          |1 = ISP INT Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register. Before use INT, user need to clear the INTFLAG(FMC_ISPSTS[24]) make sure INT happen at correct time.
+     * @var FMC_T::ISPADDR
+     * Offset: 0x04  ISP Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |ISPADDR   |ISP Address
+     * |        |          |The NuMicro M2355 series is equipped with embedded flash
+     * |        |          |ISPADDR[1:0] must be kept 00 for ISP 32-bit operation
+     * |        |          |ISPADDR[2:0] must be kept 000 for ISP 64-bit operation.
+     * |        |          |For CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 2 KBytes alignment is necessary for CRC32 checksum calculation.
+     * |        |          |For FLASH 32-bit Program, ISP address needs word alignment (4-byte)
+     * |        |          |For FLASH 64-bit Program, ISP address needs double word alignment (8-byte).
+     * @var FMC_T::ISPDAT
+     * Offset: 0x08  ISP Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |ISPDAT    |ISP Data
+     * |        |          |Write data to this register before ISP program operation.
+     * |        |          |Read data from this register after ISP read operation.
+     * |        |          |When ISPFF (FMC_ISPCTL[6]) is 1, ISPDAT = 0xffff_ffff
+     * |        |          |For Run CRC32 Checksum Calculation command, ISPDAT is the memory size (byte) and 2 KBytes alignment
+     * |        |          |For ISP Read CRC32 Checksum command, ISPDAT is the checksum result
+     * |        |          |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, or (2) the memory range for checksum calculation is incorrect
+     * |        |          |For XOM page erase function, , ISPDAT = 0x0055_aa03.
+     * @var FMC_T::ISPCMD
+     * Offset: 0x0C  ISP Command Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[6:0]   |CMD       |ISP Command
+     * |        |          |ISP command table is shown below:
+     * |        |          |0x00= FLASH Read.
+     * |        |          |0x04= Read Unique ID.
+     * |        |          |0x08= Read Flash All-One Result.
+     * |        |          |0x0B= Read Company ID.
+     * |        |          |0x0C= Read Device ID.
+     * |        |          |0x0D= Read Checksum.
+     * |        |          |0x21= FLASH 32-bit Program.
+     * |        |          |0x22= FLASH Page Erase. Erase any page in two banks, except for OTP.
+     * |        |          |0x23= FLASH Bank Erase. Erase all pages of APROM in BANK0 or BANK1.
+     * |        |          |0x25= FLASH Block Erase Erase four pages alignment of APROM in BANK0 or BANK1..
+     * |        |          |0x27= FLASH Multi-Word Program.
+     * |        |          |0x28= Run Flash All-One Verification.
+     * |        |          |0x2D= Run Checksum Calculation.
+     * |        |          |0x2E= Vector Remap.
+     * |        |          |0x40= FLASH 64-bit Read.
+     * |        |          |0x61= FLASH 64-bit Program.
+     * |        |          |The other commands are invalid.
+     * @var FMC_T::ISPTRG
+     * Offset: 0x10  ISP Trigger Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ISPGO     |ISP Start Trigger (Write Protect)
+     * |        |          |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished
+     * |        |          |When ISPGO=1, the operation of accessing value from address FMC_BA+0x00 to FMC_BA+0x68 would halt CPU still ISPGO =0
+     * |        |          |If user want to monitor whether ISP finish or not,user can access FMC_MPSTS[0] MPBUSY.
+     * |        |          |0 = ISP operation is finished.
+     * |        |          |1 = ISP is progressed.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * @var FMC_T::ISPSTS
+     * Offset: 0x40  ISP Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ISPBUSY   |ISP Busy Flag (Read Only)
+     * |        |          |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
+     * |        |          |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
+     * |        |          |0 = ISP operation is finished.
+     * |        |          |1 = ISP is progressed.
+     * |[2]     |CBS       |Boot Selection of CONFIG (Read Only)
+     * |        |          |This bit is initiated with the CBS (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened.
+     * |        |          |The following function is valid when MBS (FMC_ISPSTS[3])= 1.
+     * |        |          |0 = LDROM with IAP mode.
+     * |        |          |1 = APROM with IAP mode.
+     * |[3]     |MBS       |Boot From Boot Loader Selection Flag (Read Only)
+     * |        |          |This bit is initiated with the MBS (CONFIG0[5]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened
+     * |        |          |0 = Booting from Boot Loader.
+     * |        |          |1 = Booting from LDROM/APROM.(.see CBS bit setting)
+     * |[4]     |FCYCDIS   |Flash Access Cycle Auto-tuning Disabled Flag (Read Only)
+     * |        |          |This bit is set if flash access cycle auto-tuning function is disabled
+     * |        |          |The auto-tuning function is disabled by FADIS(FMC_CYCCTL[8]) or HIRC clock is not ready.
+     * |        |          |0 = Flash access cycle auto-tuning is Enabled.
+     * |        |          |1 = Flash access cycle auto-tuning is Disabled.
+     * |[5]     |PGFF      |Flash Program with Fast Verification Flag (Read Only)
+     * |        |          |This bit is set if data is mismatched at ISP programming verification
+     * |        |          |This bit is clear by performing ISP flash erase or ISP read CID operation
+     * |        |          |0 = Flash Program is success.
+     * |        |          |1 = Flash Program is fail. Program data is different with data in the flash memory
+     * |[6]     |ISPFF     |ISP Fail Flag (Write Protect)
+     * |        |          |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] if this bit is set.
+     * |        |          |This bit is set by hardware when a triggered ISP meets any of the following conditions:
+     * |        |          |(1) APROM writes to itself if APUEN is set to 0.
+     * |        |          |(2) LDROM writes to itself if LDUEN is set to 0.
+     * |        |          |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
+     * |        |          |(4) Page Erase command at LOCK mode with ICE connection
+     * |        |          |(5) Erase or Program command at brown-out detected
+     * |        |          |(6) Destination address is illegal, such as over an available range.
+     * |        |          |(7) Invalid ISP commands
+     * |        |          |(8) KPROM is erased/programmed if KEYLOCK is set to 1
+     * |        |          |(9) APROM is erased/programmed if KEYLOCK is set to 1
+     * |        |          |(10) LDROM is erased/programmed if KEYLOCK is set to 1
+     * |        |          |(11) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[0] is 0.
+     * |        |          |(12) Read any content of boot loader with ICE connection
+     * |        |          |(13) The address of block erase and bank erase is not in APROM
+     * |        |          |(14) ISP CMD in XOM region, except mass erase, page erase and chksum command
+     * |        |          |(15) The wrong setting of page erase ISP CMD in XOM
+     * |        |          |(16) Violate XOM setting one time protection
+     * |        |          |(17) Page erase ISP CMD in Secure/Non-secure region setting page
+     * |        |          |(18) Mass erase when MERASE (CFG0[13]) is disable
+     * |        |          |(19) Page erase, mass erase , multi-word program or 64-bit word program in OTP
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[7]     |ALLONE    |Flash All-one Verification Flag
+     * |        |          |This bit is set by hardware if all of flash bits are 1, and clear if flash bits are not all 1 after Run Flash All-One Verification complete; this bit also can be clear by writing 1
+     * |        |          |0 = All of flash bits are 1 after Run Flash All-One Verification complete.
+     * |        |          |1 = Flash bits are not all 1 after Run Flash All-One Verification complete.
+     * |[23:9]  |VECMAP    |Vector Page Mapping Address (Read Only)
+     * |        |          |All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0], 9'h000} ~ {VECMAP[14:0], 9'h1FF}
+     * |[24]    |INTFLAG   |Interrupt Flag
+     * |        |          |0 = ISP is not finish.
+     * |        |          |1 = ISP done or ISPFF set.
+     * @var FMC_T::CYCCTL
+     * Offset: 0x4C  Flash Access Cycle Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |CYCLE     |Flash Access Cycle Control (Write Protect)
+     * |        |          |This register is updated automatically by hardware while FCYCDIS (FMC_ISPSTS[4]) is 0, and updated by software while auto-tuning function disabled ( FADIS (FMC_CYCTL[8]) is 1).
+     * |        |          |When auto-tuning function disabled, user needs to check the speed of HCLK and set the cycle >0.
+     * |        |          |0000 = CPU access with zero wait cycle ; Flash access cycle is 1. The HCLK working frequency range is <27MHz; Cache is disabled by hardware.
+     * |        |          |0001 = CPU access with one wait cycle if cache miss; Flash access cycle is 1. The HCLK working frequency range range is<27MHz.
+     * |        |          |0010 = CPU access with two wait cycles if cache miss; Flash access cycle is 2. The optimized HCLK working frequency range is 25~52 MHz.
+     * |        |          |0011 = CPU access with three wait cycles if cache miss; Flash access cycle is 3. The optimized HCLK working frequency range is 49~79MHz.
+     * |        |          |Others = Reserved.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[8]     |FADIS     |Flash Access Cycle Auto-tuning Disabled Control (Write Protect)
+     * |        |          |Set this bit to disable flash access cycle auto-tuning function
+     * |        |          |0 = Flash access cycle auto-tuning is enabled.
+     * |        |          |1 = Flash access cycle auto-tuning is disabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * @var FMC_T::MPDAT0
+     * Offset: 0x80  ISP Data0 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |ISPDAT0   |ISP Data 0
+     * |        |          |This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data
+     * @var FMC_T::MPDAT1
+     * Offset: 0x84  ISP Data1 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |ISPDAT1   |ISP Data 1
+     * |        |          |This register is the second 32-bit data for 64-bit/multi-word programming.
+     * @var FMC_T::MPDAT2
+     * Offset: 0x88  ISP Data2 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |ISPDAT2   |ISP Data 2
+     * |        |          |This register is the third 32-bit data for multi-word programming.
+     * @var FMC_T::MPDAT3
+     * Offset: 0x8C  ISP Data3 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |ISPDAT3   |ISP Data 3
+     * |        |          |This register is the fourth 32-bit data for multi-word programming.
+     * @var FMC_T::MPSTS
+     * Offset: 0xC0  ISP Multi-Program Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |MPBUSY    |ISP Multi-word Program Busy Flag (Read Only)
+     * |        |          |Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.
+     * |        |          |This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
+     * |        |          |0 = ISP Multi-Word program operation is finished.
+     * |        |          |1 = ISP Multi-Word program operation is progressed.
+     * |[1]     |PPGO      |ISP Multi-program Status (Read Only)
+     * |        |          |0 = ISP multi-word program operation is not active.
+     * |        |          |1 = ISP multi-word program operation is in progress.
+     * |[2]     |ISPFF     |ISP Fail Flag (Read Only)
+     * |        |          |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]
+     * |        |          |This bit is set by hardware when a triggered ISP meets any of the following conditions:
+     * |        |          |(1) APROM writes to itself if APUEN is set to 0.
+     * |        |          |(2) LDROM writes to itself if LDUEN is set to 0.
+     * |        |          |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
+     * |        |          |(4) Page Erase command at LOCK mode with ICE connection
+     * |        |          |(5) Erase or Program command at brown-out detected
+     * |        |          |(6) Destination address is illegal, such as over an available range.
+     * |        |          |(7) Invalid ISP commands
+     * |[4]     |D0        |ISP DATA 0 Flag (Read Only)
+     * |        |          |This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete.
+     * |        |          |0 = FMC_MPDAT0 register is empty, or program to flash complete.
+     * |        |          |1 = FMC_MPDAT0 register has been written, and not program to flash complete.
+     * |[5]     |D1        |ISP DATA 1 Flag (Read Only)
+     * |        |          |This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete.
+     * |        |          |0 = FMC_MPDAT1 register is empty, or program to flash complete.
+     * |        |          |1 = FMC_MPDAT1 register has been written, and not program to flash complete.
+     * |[6]     |D2        |ISP DATA 2 Flag (Read Only)
+     * |        |          |This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete.
+     * |        |          |0 = FMC_MPDAT2 register is empty, or program to flash complete.
+     * |        |          |1 = FMC_MPDAT2 register has been written, and not program to flash complete.
+     * |[7]     |D3        |ISP DATA 3 Flag (Read Only)
+     * |        |          |This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete.
+     * |        |          |0 = FMC_MPDAT3 register is empty, or program to flash complete.
+     * |        |          |1 = FMC_MPDAT3 register has been written, and not program to flash complete.
+     * @var FMC_T::MPADDR
+     * Offset: 0xC4  ISP Multi-Program Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |MPADDR    |ISP Multi-word Program Address
+     * |        |          |MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.
+     * |        |          |MPADDR will keep the final ISP address when ISP multi-word program is complete.
+     * @var FMC_T::XOMR0STS
+     * Offset: 0xD0  XOM Region 0 Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |SIZE      |XOM Region 0 Size (Page-aligned)
+     * |        |          |SIZE is the page number of XOM Region 0.
+     * |[31:8]  |BASE      |XOM Region 0 Base Address (Page-aligned)
+     * |        |          |BASE is the base address of XOM Region 0.
+     * @var FMC_T::XOMR1STS
+     * Offset: 0xD4  XOM Region 1 Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |SIZE      |XOM Region 1 Size (Page-aligned)
+     * |        |          |SIZE is the page number of XOM Region 1.
+     * |[31:8]  |BASE      |XOM Region 1 Base Address (Page-aligned)
+     * |        |          |BASE is the base address of XOM Region 1.
+     * @var FMC_T::XOMR2STS
+     * Offset: 0xD8  XOM Region 2 Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |SIZE      |XOM Region 2 Size (Page-aligned)
+     * |        |          |SIZE is the page number of XOM Region 2.
+     * |[31:8]  |BASE      |XOM Region 2 Base Address (Page-aligned)
+     * |        |          |BASE is the base address of XOM Region 2.
+     * @var FMC_T::XOMR3STS
+     * Offset: 0xDC  XOM Region 3 Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |SIZE      |XOM Region 3 Size (Page-aligned)
+     * |        |          |SIZE is the page number of XOM Region 3.
+     * |[31:8]  |BASE      |XOM Region 3 Base Address (Page-aligned)
+     * |        |          |BASE is the base address of XOM Region 3.
+     * @var FMC_T::XOMSTS
+     * Offset: 0xE0  XOM Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |XOMR0ON   |XOM Region 0 On
+     * |        |          |XOM Region 0 active status.
+     * |        |          |0 = No active.
+     * |        |          |1 = XOM region 0 is active.
+     * |[1]     |XOMR1ON   |XOM Region 1 On
+     * |        |          |XOM Region 1 active status.
+     * |        |          |0 = No active.
+     * |        |          |1 = XOM region 1 is active.
+     * |[2]     |XOMR2ON   |XOM Region 2 On
+     * |        |          |XOM Region 2 active status.
+     * |        |          |0 = No active.
+     * |        |          |1 = XOM region 2 is active.
+     * |[3]     |XOMR3ON   |XOM Region 3 On
+     * |        |          |XOM Region 3 active status.
+     * |        |          |0 = No active.
+     * |        |          |1 = XOM region 3 is active.
+     * |[4]     |XOMPEF    |XOM Page Erase Function Fail
+     * |        |          |XOM page erase function status. If XOMPEF is set to 1, user needs to erase XOM region again.
+     * |        |          |0 = Success.
+     * |        |          |1 = Fail.
+     */
+    __IO uint32_t ISPCTL;                /*!< [0x0000] ISP Control Register                                             */
+    __IO uint32_t ISPADDR;               /*!< [0x0004] ISP Address Register                                             */
+    __IO uint32_t ISPDAT;                /*!< [0x0008] ISP Data Register                                                */
+    __IO uint32_t ISPCMD;                /*!< [0x000c] ISP Command Register                                             */
+    __IO uint32_t ISPTRG;                /*!< [0x0010] ISP Trigger Control Register                                     */
+    __I  uint32_t RESERVE0[11];
+    __IO uint32_t ISPSTS;                /*!< [0x0040] ISP Status Register                                              */
+    __I  uint32_t RESERVE1[2];
+    __IO uint32_t CYCCTL;                /*!< [0x004c] Flash Access Cycle Control Register                              */
+    __I  uint32_t RESERVE2[12];
+    __IO uint32_t MPDAT0;                /*!< [0x0080] ISP Data0 Register                                               */
+    __IO uint32_t MPDAT1;                /*!< [0x0084] ISP Data1 Register                                               */
+    __IO uint32_t MPDAT2;                /*!< [0x0088] ISP Data2 Register                                               */
+    __IO uint32_t MPDAT3;                /*!< [0x008c] ISP Data3 Register                                               */
+    __I  uint32_t RESERVE3[12];
+    __I  uint32_t MPSTS;                 /*!< [0x00c0] ISP Multi-Program Status Register                                */
+    __I  uint32_t MPADDR;                /*!< [0x00c4] ISP Multi-Program Address Register                               */
+    __I  uint32_t RESERVE4[2];
+    __I  uint32_t XOMR0STS;              /*!< [0x00d0] XOM Region 0 Status Register                                     */
+    __I  uint32_t XOMR1STS;              /*!< [0x00d4] XOM Region 1 Status Register                                     */
+    __I  uint32_t XOMR2STS;              /*!< [0x00d8] XOM Region 2 Status Register                                     */
+    __I  uint32_t XOMR3STS;              /*!< [0x00dc] XOM Region 3 Status Register                                     */
+    __I  uint32_t XOMSTS;                /*!< [0x00e0] XOM Status Register                                              */
+    __I  uint32_t RESERVE5[7];
+    __IO uint32_t DFCTL;                 /*!< [0x0100] Data Flash Function Control Register                             */
+    __I  uint32_t RESERVE6;
+    __IO uint32_t DFSTS;                 /*!< [0x0108] Data Flash Status Register                                       */
+    __O  uint32_t SCRKEY;                    /*!< [0x010c] Data Flash Scrambling Key Register                               */
+
+} FMC_T;
+
+/**
+    @addtogroup FMC_CONST FMC Bit Field Definition
+    Constant Definitions for FMC Controller
+  @{
+*/
+
+#define FMC_ISPCTL_ISPEN_Pos             (0)                                               /*!< FMC_T::ISPCTL: ISPEN Position          */
+#define FMC_ISPCTL_ISPEN_Msk             (0x1ul << FMC_ISPCTL_ISPEN_Pos)                   /*!< FMC_T::ISPCTL: ISPEN Mask              */
+
+#define FMC_ISPCTL_APUEN_Pos             (3)                                               /*!< FMC_T::ISPCTL: APUEN Position          */
+#define FMC_ISPCTL_APUEN_Msk             (0x1ul << FMC_ISPCTL_APUEN_Pos)                   /*!< FMC_T::ISPCTL: APUEN Mask              */
+
+#define FMC_ISPCTL_CFGUEN_Pos            (4)                                               /*!< FMC_T::ISPCTL: CFGUEN Position         */
+#define FMC_ISPCTL_CFGUEN_Msk            (0x1ul << FMC_ISPCTL_CFGUEN_Pos)                  /*!< FMC_T::ISPCTL: CFGUEN Mask             */
+
+#define FMC_ISPCTL_LDUEN_Pos             (5)                                               /*!< FMC_T::ISPCTL: LDUEN Position          */
+#define FMC_ISPCTL_LDUEN_Msk             (0x1ul << FMC_ISPCTL_LDUEN_Pos)                   /*!< FMC_T::ISPCTL: LDUEN Mask              */
+
+#define FMC_ISPCTL_ISPFF_Pos             (6)                                               /*!< FMC_T::ISPCTL: ISPFF Position          */
+#define FMC_ISPCTL_ISPFF_Msk             (0x1ul << FMC_ISPCTL_ISPFF_Pos)                   /*!< FMC_T::ISPCTL: ISPFF Mask              */
+
+#define FMC_ISPCTL_INTEN_Pos             (24)                                              /*!< FMC_T::ISPCTL: INTEN Position          */
+#define FMC_ISPCTL_INTEN_Msk             (0x1ul << FMC_ISPCTL_INTEN_Pos)                   /*!< FMC_T::ISPCTL: INTEN Mask              */
+
+#define FMC_ISPADDR_ISPADDR_Pos          (0)                                               /*!< FMC_T::ISPADDR: ISPADDR Position       */
+#define FMC_ISPADDR_ISPADDR_Msk          (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos)         /*!< FMC_T::ISPADDR: ISPADDR Mask           */
+
+#define FMC_ISPDAT_ISPDAT_Pos            (0)                                               /*!< FMC_T::ISPDAT: ISPDAT Position         */
+#define FMC_ISPDAT_ISPDAT_Msk            (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos)           /*!< FMC_T::ISPDAT: ISPDAT Mask             */
+
+#define FMC_ISPCMD_CMD_Pos               (0)                                               /*!< FMC_T::ISPCMD: CMD Position            */
+#define FMC_ISPCMD_CMD_Msk               (0x7ful << FMC_ISPCMD_CMD_Pos)                    /*!< FMC_T::ISPCMD: CMD Mask                */
+
+#define FMC_ISPTRG_ISPGO_Pos             (0)                                               /*!< FMC_T::ISPTRG: ISPGO Position          */
+#define FMC_ISPTRG_ISPGO_Msk             (0x1ul << FMC_ISPTRG_ISPGO_Pos)                   /*!< FMC_T::ISPTRG: ISPGO Mask              */
+
+#define FMC_ISPSTS_ISPBUSY_Pos           (0)                                               /*!< FMC_T::ISPSTS: ISPBUSY Position        */
+#define FMC_ISPSTS_ISPBUSY_Msk           (0x1ul << FMC_ISPSTS_ISPBUSY_Pos)                 /*!< FMC_T::ISPSTS: ISPBUSY Mask            */
+
+#define FMC_ISPSTS_CBS_Pos               (2)                                               /*!< FMC_T::ISPSTS: CBS Position            */
+#define FMC_ISPSTS_CBS_Msk               (0x1ul << FMC_ISPSTS_CBS_Pos)                     /*!< FMC_T::ISPSTS: CBS Mask                */
+
+#define FMC_ISPSTS_MBS_Pos               (3)                                               /*!< FMC_T::ISPSTS: MBS Position            */
+#define FMC_ISPSTS_MBS_Msk               (0x1ul << FMC_ISPSTS_MBS_Pos)                     /*!< FMC_T::ISPSTS: MBS Mask                */
+
+#define FMC_ISPSTS_FCYCDIS_Pos           (4)                                               /*!< FMC_T::ISPSTS: FCYCDIS Position        */
+#define FMC_ISPSTS_FCYCDIS_Msk           (0x1ul << FMC_ISPSTS_FCYCDIS_Pos)                 /*!< FMC_T::ISPSTS: FCYCDIS Mask            */
+
+#define FMC_ISPSTS_PGFF_Pos              (5)                                               /*!< FMC_T::ISPSTS: PGFF Position           */
+#define FMC_ISPSTS_PGFF_Msk              (0x1ul << FMC_ISPSTS_PGFF_Pos)                    /*!< FMC_T::ISPSTS: PGFF Mask               */
+
+#define FMC_ISPSTS_ISPFF_Pos             (6)                                               /*!< FMC_T::ISPSTS: ISPFF Position          */
+#define FMC_ISPSTS_ISPFF_Msk             (0x1ul << FMC_ISPSTS_ISPFF_Pos)                   /*!< FMC_T::ISPSTS: ISPFF Mask              */
+
+#define FMC_ISPSTS_ALLONE_Pos            (7)                                               /*!< FMC_T::ISPSTS: ALLONE Position         */
+#define FMC_ISPSTS_ALLONE_Msk            (0x1ul << FMC_ISPSTS_ALLONE_Pos)                  /*!< FMC_T::ISPSTS: ALLONE Mask             */
+
+#define FMC_ISPSTS_VECMAP_Pos            (9)                                               /*!< FMC_T::ISPSTS: VECMAP Position         */
+#define FMC_ISPSTS_VECMAP_Msk            (0x7ffful << FMC_ISPSTS_VECMAP_Pos)               /*!< FMC_T::ISPSTS: VECMAP Mask             */
+
+#define FMC_ISPSTS_INTFLAG_Pos           (24)                                              /*!< FMC_T::ISPSTS: INTFLAG Position        */
+#define FMC_ISPSTS_INTFLAG_Msk           (0x1ul << FMC_ISPSTS_INTFLAG_Pos)                 /*!< FMC_T::ISPSTS: INTFLAG Mask            */
+
+#define FMC_ISPSTS_ISPCERR_Pos           (28)                                              /*!< FMC_T::ISPSTS: ISPCERR Position        */
+#define FMC_ISPSTS_ISPCERR_Msk           (0x1ul << FMC_ISPSTS_ISPCERR_Pos)                 /*!< FMC_T::ISPSTS: ISPCERR Mask            */
+
+#define FMC_ISPSTS_MIRBOUND_Pos          (29)                                              /*!< FMC_T::ISPSTS: MIRBOUND Position       */
+#define FMC_ISPSTS_MIRBOUND_Msk          (0x1ul << FMC_ISPSTS_MIRBOUND_Pos)                /*!< FMC_T::ISPSTS: MIRBOUND Mask           */
+
+#define FMC_ISPSTS_FBS_Pos               (30)                                              /*!< FMC_T::ISPSTS: FBS Position            */
+#define FMC_ISPSTS_FBS_Msk               (0x1ul << FMC_ISPSTS_FBS_Pos)                     /*!< FMC_T::ISPSTS: FBS Mask                */
+
+#define FMC_CYCCTL_CYCLE_Pos             (0)                                               /*!< FMC_T::CYCCTL: CYCLE Position          */
+#define FMC_CYCCTL_CYCLE_Msk             (0xful << FMC_CYCCTL_CYCLE_Pos)                   /*!< FMC_T::CYCCTL: CYCLE Mask              */
+
+#define FMC_CYCCTL_FADIS_Pos             (8)                                               /*!< FMC_T::CYCCTL: FADIS Position          */
+#define FMC_CYCCTL_FADIS_Msk             (0x1ul << FMC_CYCCTL_FADIS_Pos)                   /*!< FMC_T::CYCCTL: FADIS Mask              */
+
+#define FMC_KPKEY0_KPKEY0_Pos            (0)                                               /*!< FMC_T::KPKEY0: KPKEY0 Position         */
+#define FMC_KPKEY0_KPKEY0_Msk            (0xfffffffful << FMC_KPKEY0_KPKEY0_Pos)           /*!< FMC_T::KPKEY0: KPKEY0 Mask             */
+
+#define FMC_KPKEY1_KPKEY1_Pos            (0)                                               /*!< FMC_T::KPKEY1: KPKEY1 Position         */
+#define FMC_KPKEY1_KPKEY1_Msk            (0xfffffffful << FMC_KPKEY1_KPKEY1_Pos)           /*!< FMC_T::KPKEY1: KPKEY1 Mask             */
+
+#define FMC_KPKEY2_KPKEY2_Pos            (0)                                               /*!< FMC_T::KPKEY2: KPKEY2 Position         */
+#define FMC_KPKEY2_KPKEY2_Msk            (0xfffffffful << FMC_KPKEY2_KPKEY2_Pos)           /*!< FMC_T::KPKEY2: KPKEY2 Mask             */
+
+#define FMC_KPKEYTRG_KPKEYGO_Pos         (0)                                               /*!< FMC_T::KPKEYTRG: KPKEYGO Position      */
+#define FMC_KPKEYTRG_KPKEYGO_Msk         (0x1ul << FMC_KPKEYTRG_KPKEYGO_Pos)               /*!< FMC_T::KPKEYTRG: KPKEYGO Mask          */
+
+#define FMC_KPKEYTRG_TCEN_Pos            (1)                                               /*!< FMC_T::KPKEYTRG: TCEN Position         */
+#define FMC_KPKEYTRG_TCEN_Msk            (0x1ul << FMC_KPKEYTRG_TCEN_Pos)                  /*!< FMC_T::KPKEYTRG: TCEN Mask             */
+
+#define FMC_KPKEYSTS_KEYBUSY_Pos         (0)                                               /*!< FMC_T::KPKEYSTS: KEYBUSY Position      */
+#define FMC_KPKEYSTS_KEYBUSY_Msk         (0x1ul << FMC_KPKEYSTS_KEYBUSY_Pos)               /*!< FMC_T::KPKEYSTS: KEYBUSY Mask          */
+
+#define FMC_KPKEYSTS_KEYLOCK_Pos         (1)                                               /*!< FMC_T::KPKEYSTS: KEYLOCK Position      */
+#define FMC_KPKEYSTS_KEYLOCK_Msk         (0x1ul << FMC_KPKEYSTS_KEYLOCK_Pos)               /*!< FMC_T::KPKEYSTS: KEYLOCK Mask          */
+
+#define FMC_KPKEYSTS_KEYMATCH_Pos        (2)                                               /*!< FMC_T::KPKEYSTS: KEYMATCH Position     */
+#define FMC_KPKEYSTS_KEYMATCH_Msk        (0x1ul << FMC_KPKEYSTS_KEYMATCH_Pos)              /*!< FMC_T::KPKEYSTS: KEYMATCH Mask         */
+
+#define FMC_KPKEYSTS_FORBID_Pos          (3)                                               /*!< FMC_T::KPKEYSTS: FORBID Position       */
+#define FMC_KPKEYSTS_FORBID_Msk          (0x1ul << FMC_KPKEYSTS_FORBID_Pos)                /*!< FMC_T::KPKEYSTS: FORBID Mask           */
+
+#define FMC_KPKEYSTS_KEYFLAG_Pos         (4)                                               /*!< FMC_T::KPKEYSTS: KEYFLAG Position      */
+#define FMC_KPKEYSTS_KEYFLAG_Msk         (0x1ul << FMC_KPKEYSTS_KEYFLAG_Pos)               /*!< FMC_T::KPKEYSTS: KEYFLAG Mask          */
+
+#define FMC_KPKEYSTS_CFGFLAG_Pos         (5)                                               /*!< FMC_T::KPKEYSTS: CFGFLAG Position      */
+#define FMC_KPKEYSTS_CFGFLAG_Msk         (0x1ul << FMC_KPKEYSTS_CFGFLAG_Pos)               /*!< FMC_T::KPKEYSTS: CFGFLAG Mask          */
+
+#define FMC_KPKEYSTS_SBKPBUSY_Pos        (8)                                               /*!< FMC_T::KPKEYSTS: SBKPBUSY Position     */
+#define FMC_KPKEYSTS_SBKPBUSY_Msk        (0x1ul << FMC_KPKEYSTS_SBKPBUSY_Pos)              /*!< FMC_T::KPKEYSTS: SBKPBUSY Mask         */
+
+#define FMC_KPKEYSTS_SBKPFLAG_Pos        (9)                                               /*!< FMC_T::KPKEYSTS: SBKPFLAG Position     */
+#define FMC_KPKEYSTS_SBKPFLAG_Msk        (0x1ul << FMC_KPKEYSTS_SBKPFLAG_Pos)              /*!< FMC_T::KPKEYSTS: SBKPFLAG Mask         */
+
+#define FMC_KPKEYCNT_KPKECNT_Pos         (0)                                               /*!< FMC_T::KPKEYCNT: KPKECNT Position      */
+#define FMC_KPKEYCNT_KPKECNT_Msk         (0x3ful << FMC_KPKEYCNT_KPKECNT_Pos)              /*!< FMC_T::KPKEYCNT: KPKECNT Mask          */
+
+#define FMC_KPKEYCNT_KPKEMAX_Pos         (8)                                               /*!< FMC_T::KPKEYCNT: KPKEMAX Position      */
+#define FMC_KPKEYCNT_KPKEMAX_Msk         (0x3ful << FMC_KPKEYCNT_KPKEMAX_Pos)              /*!< FMC_T::KPKEYCNT: KPKEMAX Mask          */
+
+#define FMC_KPCNT_KPCNT_Pos              (0)                                               /*!< FMC_T::KPCNT: KPCNT Position           */
+#define FMC_KPCNT_KPCNT_Msk              (0xful << FMC_KPCNT_KPCNT_Pos)                    /*!< FMC_T::KPCNT: KPCNT Mask               */
+
+#define FMC_KPCNT_KPMAX_Pos              (8)                                               /*!< FMC_T::KPCNT: KPMAX Position           */
+#define FMC_KPCNT_KPMAX_Msk              (0xful << FMC_KPCNT_KPMAX_Pos)                    /*!< FMC_T::KPCNT: KPMAX Mask               */
+
+#define FMC_MPDAT0_ISPDAT0_Pos           (0)                                               /*!< FMC_T::MPDAT0: ISPDAT0 Position        */
+#define FMC_MPDAT0_ISPDAT0_Msk           (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos)          /*!< FMC_T::MPDAT0: ISPDAT0 Mask            */
+
+#define FMC_MPDAT1_ISPDAT1_Pos           (0)                                               /*!< FMC_T::MPDAT1: ISPDAT1 Position        */
+#define FMC_MPDAT1_ISPDAT1_Msk           (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos)          /*!< FMC_T::MPDAT1: ISPDAT1 Mask            */
+
+#define FMC_MPDAT2_ISPDAT2_Pos           (0)                                               /*!< FMC_T::MPDAT2: ISPDAT2 Position        */
+#define FMC_MPDAT2_ISPDAT2_Msk           (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos)          /*!< FMC_T::MPDAT2: ISPDAT2 Mask            */
+
+#define FMC_MPDAT3_ISPDAT3_Pos           (0)                                               /*!< FMC_T::MPDAT3: ISPDAT3 Position        */
+#define FMC_MPDAT3_ISPDAT3_Msk           (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos)          /*!< FMC_T::MPDAT3: ISPDAT3 Mask            */
+
+#define FMC_MPSTS_MPBUSY_Pos             (0)                                               /*!< FMC_T::MPSTS: MPBUSY Position          */
+#define FMC_MPSTS_MPBUSY_Msk             (0x1ul << FMC_MPSTS_MPBUSY_Pos)                   /*!< FMC_T::MPSTS: MPBUSY Mask              */
+
+#define FMC_MPSTS_PPGO_Pos               (1)                                               /*!< FMC_T::MPSTS: PPGO Position            */
+#define FMC_MPSTS_PPGO_Msk               (0x1ul << FMC_MPSTS_PPGO_Pos)                     /*!< FMC_T::MPSTS: PPGO Mask                */
+
+#define FMC_MPSTS_ISPFF_Pos              (2)                                               /*!< FMC_T::MPSTS: ISPFF Position           */
+#define FMC_MPSTS_ISPFF_Msk              (0x1ul << FMC_MPSTS_ISPFF_Pos)                    /*!< FMC_T::MPSTS: ISPFF Mask               */
+
+#define FMC_MPSTS_D0_Pos                 (4)                                               /*!< FMC_T::MPSTS: D0 Position              */
+#define FMC_MPSTS_D0_Msk                 (0x1ul << FMC_MPSTS_D0_Pos)                       /*!< FMC_T::MPSTS: D0 Mask                  */
+
+#define FMC_MPSTS_D1_Pos                 (5)                                               /*!< FMC_T::MPSTS: D1 Position              */
+#define FMC_MPSTS_D1_Msk                 (0x1ul << FMC_MPSTS_D1_Pos)                       /*!< FMC_T::MPSTS: D1 Mask                  */
+
+#define FMC_MPSTS_D2_Pos                 (6)                                               /*!< FMC_T::MPSTS: D2 Position              */
+#define FMC_MPSTS_D2_Msk                 (0x1ul << FMC_MPSTS_D2_Pos)                       /*!< FMC_T::MPSTS: D2 Mask                  */
+
+#define FMC_MPSTS_D3_Pos                 (7)                                               /*!< FMC_T::MPSTS: D3 Position              */
+#define FMC_MPSTS_D3_Msk                 (0x1ul << FMC_MPSTS_D3_Pos)                       /*!< FMC_T::MPSTS: D3 Mask                  */
+
+#define FMC_MPADDR_MPADDR_Pos            (0)                                               /*!< FMC_T::MPADDR: MPADDR Position         */
+#define FMC_MPADDR_MPADDR_Msk            (0xfffffffful << FMC_MPADDR_MPADDR_Pos)           /*!< FMC_T::MPADDR: MPADDR Mask             */
+
+#define FMC_XOMR0STS_SIZE_Pos            (0)                                               /*!< FMC_T::XOMR0STS: SIZE Position         */
+#define FMC_XOMR0STS_SIZE_Msk            (0xfful << FMC_XOMR0STS_SIZE_Pos)                 /*!< FMC_T::XOMR0STS: SIZE Mask             */
+
+#define FMC_XOMR0STS_BASE_Pos            (8)                                               /*!< FMC_T::XOMR0STS: BASE Position         */
+#define FMC_XOMR0STS_BASE_Msk            (0xfffffful << FMC_XOMR0STS_BASE_Pos)             /*!< FMC_T::XOMR0STS: BASE Mask             */
+
+#define FMC_XOMR1STS_SIZE_Pos            (0)                                               /*!< FMC_T::XOMR1STS: SIZE Position         */
+#define FMC_XOMR1STS_SIZE_Msk            (0xfful << FMC_XOMR1STS_SIZE_Pos)                 /*!< FMC_T::XOMR1STS: SIZE Mask             */
+
+#define FMC_XOMR1STS_BASE_Pos            (8)                                               /*!< FMC_T::XOMR1STS: BASE Position         */
+#define FMC_XOMR1STS_BASE_Msk            (0xfffffful << FMC_XOMR1STS_BASE_Pos)             /*!< FMC_T::XOMR1STS: BASE Mask             */
+
+#define FMC_XOMR2STS_SIZE_Pos            (0)                                               /*!< FMC_T::XOMR2STS: SIZE Position         */
+#define FMC_XOMR2STS_SIZE_Msk            (0xfful << FMC_XOMR2STS_SIZE_Pos)                 /*!< FMC_T::XOMR2STS: SIZE Mask             */
+
+#define FMC_XOMR2STS_BASE_Pos            (8)                                               /*!< FMC_T::XOMR2STS: BASE Position         */
+#define FMC_XOMR2STS_BASE_Msk            (0xfffffful << FMC_XOMR2STS_BASE_Pos)             /*!< FMC_T::XOMR2STS: BASE Mask             */
+
+#define FMC_XOMR3STS_SIZE_Pos            (0)                                               /*!< FMC_T::XOMR3STS: SIZE Position         */
+#define FMC_XOMR3STS_SIZE_Msk            (0xfful << FMC_XOMR3STS_SIZE_Pos)                 /*!< FMC_T::XOMR3STS: SIZE Mask             */
+
+#define FMC_XOMR3STS_BASE_Pos            (8)                                               /*!< FMC_T::XOMR3STS: BASE Position         */
+#define FMC_XOMR3STS_BASE_Msk            (0xfffffful << FMC_XOMR3STS_BASE_Pos)             /*!< FMC_T::XOMR3STS: BASE Mask             */
+
+#define FMC_XOMSTS_XOMR0ON_Pos           (0)                                               /*!< FMC_T::XOMSTS: XOMR0ON Position        */
+#define FMC_XOMSTS_XOMR0ON_Msk           (0x1ul << FMC_XOMSTS_XOMR0ON_Pos)                 /*!< FMC_T::XOMSTS: XOMR0ON Mask            */
+
+#define FMC_XOMSTS_XOMR1ON_Pos           (1)                                               /*!< FMC_T::XOMSTS: XOMR1ON Position        */
+#define FMC_XOMSTS_XOMR1ON_Msk           (0x1ul << FMC_XOMSTS_XOMR1ON_Pos)                 /*!< FMC_T::XOMSTS: XOMR1ON Mask            */
+
+#define FMC_XOMSTS_XOMR2ON_Pos           (2)                                               /*!< FMC_T::XOMSTS: XOMR2ON Position        */
+#define FMC_XOMSTS_XOMR2ON_Msk           (0x1ul << FMC_XOMSTS_XOMR2ON_Pos)                 /*!< FMC_T::XOMSTS: XOMR2ON Mask            */
+
+#define FMC_XOMSTS_XOMR3ON_Pos           (3)                                               /*!< FMC_T::XOMSTS: XOMR3ON Position        */
+#define FMC_XOMSTS_XOMR3ON_Msk           (0x1ul << FMC_XOMSTS_XOMR3ON_Pos)                 /*!< FMC_T::XOMSTS: XOMR3ON Mask            */
+
+#define FMC_XOMSTS_XOMPEF_Pos            (4)                                               /*!< FMC_T::XOMSTS: XOMPEF Position         */
+#define FMC_XOMSTS_XOMPEF_Msk            (0x1ul << FMC_XOMSTS_XOMPEF_Pos)                  /*!< FMC_T::XOMSTS: XOMPEF Mask             */
+
+#define FMC_DFCTL_SCRAMEN_Pos            (0)                                               /*!< FMC_T::DFCTL: SCRAMEN Position      */
+#define FMC_DFCTL_SCRAMEN_Msk            (0x1ul << FMC_DFCTL_SCRAMEN_Pos)                  /*!< FMC_T::DFCTL: SCRAMEN Mask          */
+
+#define FMC_DFCTL_SILENTEN_Pos           (1)                                               /*!< FMC_T::DFCTL: SILENTEN Position     */
+#define FMC_DFCTL_SILENTEN_Msk           (0x1ul << FMC_DFCTL_SILENTEN_Pos)                 /*!< FMC_T::DFCTL: SILENTEN Mask         */
+
+#define FMC_DFSTS_TMPCLRDONE_Pos         (0)                                               /*!< FMC_T::DFSTS: TMPCLRDONE Position    */
+#define FMC_DFSTS_TMPCLRDONE_Msk         (0x1ul << FMC_DFSTS_TMPCLRDONE_Pos)               /*!< FMC_T::DFSTS: TMPCLRDONE Mask        */
+
+#define FMC_DFSTS_TMPCLRBUSY_Pos         (1)                                               /*!< FMC_T::DFSTS: TMPCLRBUSY Position    */
+#define FMC_DFSTS_TMPCLRBUSY_Msk         (0x1ul << FMC_DFSTS_TMPCLRBUSY_Pos)               /*!< FMC_T::DFSTS: TMPCLRBUSY Mask        */
+
+#define FMC_SCRKEY_SCRKEY_Pos            (0)                                                 /*!< FMC_T::SCRKEY: SCRKEY Position       */
+#define FMC_SCRKEY_SCRKEY_Msk            (0xfffffffful << FMC_SCRKEY_SCRKEY_Pos)           /*!< FMC_T::SCRKEY: SCRKEY Mask           */
+
+/**@}*/ /* FMC_CONST */
+/**@}*/ /* end of FMC register group */
+/**@}*/ /* end of REGISTER group */
+
+#endif /* __FMC_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/gpio_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/gpio_reg.h
new file mode 100644
index 0000000000..65cdf437e0
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/gpio_reg.h
@@ -0,0 +1,888 @@
+/**************************************************************************//**
+ * @file     gpio_reg.h
+ * @version  V1.00
+ * @brief    GPIO register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __GPIO_REG_H__
+#define __GPIO_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+/*---------------------- General Purpose Input/Output Controller -------------------------*/
+/**
+    @addtogroup GPIO General Purpose Input/Output Controller(GPIO)
+    Memory Mapped Structure for GPIO Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var GPIO_T::MODE
+     * Offset: 0x00/0x40/0x80/0xC0/0x100/0x140/0x180/0x1C0  PA-H I/O Mode Control
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2n+1:2n]|MODEn    |Port A-H I/O Pin[n] Mode Control
+     * |        |          |Determine each I/O mode of Px.n pins.
+     * |        |          |00 = Px.n is in Input mode.
+     * |        |          |01 = Px.n is in Push-pull Output mode.
+     * |        |          |10 = Px.n is in Open-drain Output mode.
+     * |        |          |11 = Px.n is in Quasi-bidirectional mode.
+     * |        |          |Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).
+     * |        |          |If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.
+     * |        |          |If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.
+     * |        |          |Note 2: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
+     * @var GPIO_T::DINOFF
+     * Offset: 0x04/0x44/0x84/0xC4/0x104/0x144/0x184/0x1C4  PA-H Digital Input Path Disable Control
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[n+16]  |DINOFFn   |Port A-H Pin[n] Digital Input Path Disable Control
+     * |        |          |Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled.
+     * |        |          |If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
+     * |        |          |0 = Px.n digital input path Enabled.
+     * |        |          |1 = Px.n digital input path Disabled (digital input tied to low).
+     * |        |          |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
+     * @var GPIO_T::DOUT
+     * Offset: 0x08/0x48/0x88/0xC8/0x108/0x148/0x188/0x1C8  PA-H Data Output Value
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[n]     |DOUTn     |Port A-H Pin[n] Output Value
+     * |        |          |Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
+     * |        |          |0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
+     * |        |          |1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode.
+     * |        |          |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
+     * @var GPIO_T::DATMSK
+     * Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C/0x18C/0x1CC  PA-H Data Output Write Mask
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[n]     |DATMSKn   |Port A-H Pin[n] Data Output Write Mask
+     * |        |          |These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit.
+     * |        |          |When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected.
+     * |        |          |If the write signal is masked, writing data to the protect bit is ignored.
+     * |        |          |0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
+     * |        |          |1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
+     * |        |          |Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
+     * |        |          |Note 2: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
+     * @var GPIO_T::PIN
+     * Offset: 0x10/0x50/0x90/0xD0/0x110/0x150/0x190/0x1D0  PA-H Pin Value
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[n]     |PINn      |Port A-H Pin[n] Pin Value
+     * |        |          |Each bit of the register reflects the actual status of the respective Px.n pin.
+     * |        |          |0 = The corresponding pin status is low.
+     * |        |          |1 = The corresponding pin status is high.
+     * |        |          |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
+     * @var GPIO_T::DBEN
+     * Offset: 0x14/0x54/0x94/0xD4/0x114/0x154/0x194/0x1D4  PA-H De-Bounce Enable Control
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[n]     |DBENn     |Port A-H Pin[n] Input Signal De-bounce Enable Bit
+     * |        |          |The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit.
+     * |        |          |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt.
+     * |        |          |The de-bounce clock source is controlled by DBCLKSRC (Px_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (Px_DBCTL [3:0]).
+     * |        |          |0 = Px.n de-bounce function Disabled.
+     * |        |          |1 = Px.n de-bounce function Enabled.
+     * |        |          |The de-bounce function is valid only for edge triggered interrupt.
+     * |        |          |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
+     * |        |          |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
+     * @var GPIO_T::INTTYPE
+     * Offset: 0x18/0x58/0x98/0xD8/0x118/0x158/0x198/0x1D8  PA-H Interrupt Trigger Type Control
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[n]     |TYPEn     |Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control
+     * |        |          |TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger.
+     * |        |          |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
+     * |        |          |If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
+     * |        |          |0 = Edge trigger interrupt.
+     * |        |          |1 = Level trigger interrupt.
+     * |        |          |If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]).
+     * |        |          |If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
+     * |        |          |The de-bounce function is valid only for edge triggered interrupt.
+     * |        |          |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
+     * |        |          |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
+     * @var GPIO_T::INTEN
+     * Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C/0x19C/0x1DC  PA-H Interrupt Enable Control
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[n]     |FLIENn    |Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
+     * |        |          |The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
+     * |        |          |Set bit to 1 also enable the pin wake-up function.
+     * |        |          |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
+     * |        |          |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
+     * |        |          |If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
+     * |        |          |0 = Px.n level low or high to low interrupt Disabled.
+     * |        |          |1 = Px.n level low or high to low interrupt Enabled.
+     * |        |          |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
+     * |[n+16]  |RHIENn    |Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
+     * |        |          |The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
+     * |        |          |Set bit to 1 also enable the pin wake-up function.
+     * |        |          |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
+     * |        |          |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
+     * |        |          |If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
+     * |        |          |0 = Px.n level high or low to high interrupt Disabled.
+     * |        |          |1 = Px.n level high or low to high interrupt Enabled.
+     * |        |          |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
+     * @var GPIO_T::INTSRC
+     * Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160/0x1A0/0x1E0  PA-H Interrupt Source Flag
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[n]     |INTSRCn   |Port A-H Pin[n] Interrupt Source Flag
+     * |        |          |Write Operation :
+     * |        |          |0 = No action.
+     * |        |          |1 = Clear the corresponding pending interrupt.
+     * |        |          |Read Operation :
+     * |        |          |0 = No interrupt at Px.n.
+     * |        |          |1 = Px.n generates an interrupt.
+     * |        |          |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
+     * @var GPIO_T::SMTEN
+     * Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164/0x1A4/0x1E4  PA-H Input Schmitt Trigger Enable
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[n]     |SMTENn    |Port A-H Pin[n] Input Schmitt Trigger Enable Bit
+     * |        |          |0 = Px.n input Schmitt trigger function Disabled.
+     * |        |          |1 = Px.n input Schmitt trigger function Enabled.
+     * |        |          |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
+     * @var GPIO_T::SLEWCTL
+     * Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168/0x1A8/0x1E8  PA-H High Slew Rate Control
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2n+1:2n]|HSRENn   |Port A-H Pin[n] High Slew Rate Control
+     * |        |          |00 = Px.n output with normal slew rate mode (maximum 40 MHz at 2.7V).
+     * |        |          |01 = Px.n output with high slew rate mode (maximum 80 MHz at 2.7V).
+     * |        |          |10 = Px.n output with fast slew rate mode (maximum 100 MHz at 2.7V.
+     * |        |          |11 = Reserved.
+     * |        |          |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
+     * @var GPIO_T::PUSEL
+     * Offset: 0x30/0x70/0xB0/0xF0/0x130/0x170/0x1B0/0x1F0  PA-H Pull-up and Pull-down Selection Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2n+1:2n]|PUSELn   |Port A-H Pin[n] Pull-up and Pull-down Enable Register
+     * |        |          |Determine each I/O Pull-up/pull-down of Px.n pins.
+     * |        |          |00 = Px.n pull-up and pull-down disabled.
+     * |        |          |01 = Px.n pull-up enabled.
+     * |        |          |10 = Px.n pull-down enabled.
+     * |        |          |11 = Px.n pull-up and pull-down disabled.
+     * |        |          |Note 1:
+     * |        |          |Basically, the pull-up control and pull-down control has following behavior limitation.
+     * |        |          |The independent pull-up control register only valid when MODEn (Px_MODE[2n+1:2n]) set as tri-state and open-drain mode.
+     * |        |          |The independent pull-down control register only valid when MODEn (Px_MODE[2n+1:2n]) set as tri-state mode.
+     * |        |          |When both pull-up pull-down is set as 1 at tri-state mode, keep I/O in tri-state mode.
+     * |        |          |Note 2: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored.
+     * @var GPIO_T::DBCTL
+     * Offset: 0x34/0x74/0xB4/0xF4/0x134/0x174/0x1B4/0x1F4  PA-H Interrupt De-bounce Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |DBCLKSEL  |De-bounce Sampling Cycle Selection
+     * |        |          |0000 = Sample interrupt input once per 1 clocks.
+     * |        |          |0001 = Sample interrupt input once per 2 clocks.
+     * |        |          |0010 = Sample interrupt input once per 4 clocks.
+     * |        |          |0011 = Sample interrupt input once per 8 clocks.
+     * |        |          |0100 = Sample interrupt input once per 16 clocks.
+     * |        |          |0101 = Sample interrupt input once per 32 clocks.
+     * |        |          |0110 = Sample interrupt input once per 64 clocks.
+     * |        |          |0111 = Sample interrupt input once per 128 clocks.
+     * |        |          |1000 = Sample interrupt input once per 256 clocks.
+     * |        |          |1001 = Sample interrupt input once per 2*256 clocks.
+     * |        |          |1010 = Sample interrupt input once per 4*256 clocks.
+     * |        |          |1011 = Sample interrupt input once per 8*256 clocks.
+     * |        |          |1100 = Sample interrupt input once per 16*256 clocks.
+     * |        |          |1101 = Sample interrupt input once per 32*256 clocks.
+     * |        |          |1110 = Sample interrupt input once per 64*256 clocks.
+     * |        |          |1111 = Sample interrupt input once per 128*256 clocks.
+     * |[4]     |DBCLKSRC  |De-bounce Counter Clock Source Selection
+     * |        |          |0 = De-bounce counter clock source is the HCLK.
+     * |        |          |1 = De-bounce counter clock source is the 32 kHz internal low speed RC oscillator (LIRC).
+     * |[5]     |ICLKON    |Interrupt Clock on Mode
+     * |        |          |0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1.
+     * |        |          |1 = All I/O pins edge detection circuit is always active after reset.
+     * |        |          |Note: It is recommended to disable this bit to save system power if no special application concern.
+     */
+
+
+    __IO uint32_t MODE;                  /*!< [0x00/0x40/0x80/0xC0/0x100/0x140/0x180/0x1C0] Port A-H I/O Mode Control                   */
+    __IO uint32_t DINOFF;                /*!< [0x04/0x44/0x84/0xC4/0x104/0x144/0x184/0x1C4] Port A-H Digital Input Path Disable Control */
+    __IO uint32_t DOUT;                  /*!< [0x08/0x48/0x88/0xC8/0x108/0x148/0x188/0x1C8] Port A-H Data Output Value                  */
+    __IO uint32_t DATMSK;                /*!< [0x0C/0x4C/0x8C/0xCC/0x10C/0x14C/0x18C/0x1CC] Port A-H Data Output Write Mask             */
+    __I  uint32_t PIN;                   /*!< [0x10/0x50/0x90/0xD0/0x110/0x150/0x190/0x1D0] Port A-H Pin Value                          */
+    __IO uint32_t DBEN;                  /*!< [0x14/0x54/0x94/0xD4/0x114/0x154/0x194/0x1D4] Port A-H De-Bounce Enable Control           */
+    __IO uint32_t INTTYPE;               /*!< [0x18/0x58/0x98/0xD8/0x118/0x158/0x198/0x1D8] Port A-H Interrupt Trigger Type Control     */
+    __IO uint32_t INTEN;                 /*!< [0x1C/0x5C/0x9C/0xDC/0x11C/0x15C/0x19C/0x1DC] Port A-H Interrupt Enable Control           */
+    __IO uint32_t INTSRC;                /*!< [0x20/0x60/0xA0/0xE0/0x120/0x160/0x1A0/0x1E0] Port A-H Interrupt Source Flag              */
+    __IO uint32_t SMTEN;                 /*!< [0x24/0x64/0xA4/0xE4/0x124/0x164/0x1A4/0x1E4] Port A-H Input Schmitt Trigger Enable       */
+    __IO uint32_t SLEWCTL;               /*!< [0x28/0x68/0xA8/0xE8/0x128/0x168/0x1A8/0x1E8] Port A-H High Slew Rate Control             */
+    __I  uint32_t RESERVE0[1];
+    __IO uint32_t PUSEL;                 /*!< [0x30/0x70/0xB0/0xF0/0x130/0x170/0x1B0/0x1F0] Port A-H Pull-up and Pull-down Selection Register */
+    __IO uint32_t DBCTL;                 /*!< [0x34/0x74/0xB4/0xF4/0x134/0x174/0x1B4/0x1F4] Port A-H Interrupt De-bounce Control        */
+
+} GPIO_T;
+
+
+
+/**
+    @addtogroup GPIO_CONST GPIO Bit Field Definition
+    Constant Definitions for GPIO Controller
+  @{
+*/
+
+#define GPIO_MODE_MODE0_Pos              (0)                                               /*!< GPIO_T::MODE: MODE0 Position           */
+#define GPIO_MODE_MODE0_Msk              (0x3ul << GPIO_MODE_MODE0_Pos)                    /*!< GPIO_T::MODE: MODE0 Mask               */
+
+#define GPIO_MODE_MODE1_Pos              (2)                                               /*!< GPIO_T::MODE: MODE1 Position           */
+#define GPIO_MODE_MODE1_Msk              (0x3ul << GPIO_MODE_MODE1_Pos)                    /*!< GPIO_T::MODE: MODE1 Mask               */
+
+#define GPIO_MODE_MODE2_Pos              (4)                                               /*!< GPIO_T::MODE: MODE2 Position           */
+#define GPIO_MODE_MODE2_Msk              (0x3ul << GPIO_MODE_MODE2_Pos)                    /*!< GPIO_T::MODE: MODE2 Mask               */
+
+#define GPIO_MODE_MODE3_Pos              (6)                                               /*!< GPIO_T::MODE: MODE3 Position           */
+#define GPIO_MODE_MODE3_Msk              (0x3ul << GPIO_MODE_MODE3_Pos)                    /*!< GPIO_T::MODE: MODE3 Mask               */
+
+#define GPIO_MODE_MODE4_Pos              (8)                                               /*!< GPIO_T::MODE: MODE4 Position           */
+#define GPIO_MODE_MODE4_Msk              (0x3ul << GPIO_MODE_MODE4_Pos)                    /*!< GPIO_T::MODE: MODE4 Mask               */
+
+#define GPIO_MODE_MODE5_Pos              (10)                                              /*!< GPIO_T::MODE: MODE5 Position           */
+#define GPIO_MODE_MODE5_Msk              (0x3ul << GPIO_MODE_MODE5_Pos)                    /*!< GPIO_T::MODE: MODE5 Mask               */
+
+#define GPIO_MODE_MODE6_Pos              (12)                                              /*!< GPIO_T::MODE: MODE6 Position           */
+#define GPIO_MODE_MODE6_Msk              (0x3ul << GPIO_MODE_MODE6_Pos)                    /*!< GPIO_T::MODE: MODE6 Mask               */
+
+#define GPIO_MODE_MODE7_Pos              (14)                                              /*!< GPIO_T::MODE: MODE7 Position           */
+#define GPIO_MODE_MODE7_Msk              (0x3ul << GPIO_MODE_MODE7_Pos)                    /*!< GPIO_T::MODE: MODE7 Mask               */
+
+#define GPIO_MODE_MODE8_Pos              (16)                                              /*!< GPIO_T::MODE: MODE8 Position           */
+#define GPIO_MODE_MODE8_Msk              (0x3ul << GPIO_MODE_MODE8_Pos)                    /*!< GPIO_T::MODE: MODE8 Mask               */
+
+#define GPIO_MODE_MODE9_Pos              (18)                                              /*!< GPIO_T::MODE: MODE9 Position           */
+#define GPIO_MODE_MODE9_Msk              (0x3ul << GPIO_MODE_MODE9_Pos)                    /*!< GPIO_T::MODE: MODE9 Mask               */
+
+#define GPIO_MODE_MODE10_Pos             (20)                                              /*!< GPIO_T::MODE: MODE10 Position          */
+#define GPIO_MODE_MODE10_Msk             (0x3ul << GPIO_MODE_MODE10_Pos)                   /*!< GPIO_T::MODE: MODE10 Mask              */
+
+#define GPIO_MODE_MODE11_Pos             (22)                                              /*!< GPIO_T::MODE: MODE11 Position          */
+#define GPIO_MODE_MODE11_Msk             (0x3ul << GPIO_MODE_MODE11_Pos)                   /*!< GPIO_T::MODE: MODE11 Mask              */
+
+#define GPIO_MODE_MODE12_Pos             (24)                                              /*!< GPIO_T::MODE: MODE12 Position          */
+#define GPIO_MODE_MODE12_Msk             (0x3ul << GPIO_MODE_MODE12_Pos)                   /*!< GPIO_T::MODE: MODE12 Mask              */
+
+#define GPIO_MODE_MODE13_Pos             (26)                                              /*!< GPIO_T::MODE: MODE13 Position          */
+#define GPIO_MODE_MODE13_Msk             (0x3ul << GPIO_MODE_MODE13_Pos)                   /*!< GPIO_T::MODE: MODE13 Mask              */
+
+#define GPIO_MODE_MODE14_Pos             (28)                                              /*!< GPIO_T::MODE: MODE14 Position          */
+#define GPIO_MODE_MODE14_Msk             (0x3ul << GPIO_MODE_MODE14_Pos)                   /*!< GPIO_T::MODE: MODE14 Mask              */
+
+#define GPIO_MODE_MODE15_Pos             (30)                                              /*!< GPIO_T::MODE: MODE15 Position          */
+#define GPIO_MODE_MODE15_Msk             (0x3ul << GPIO_MODE_MODE15_Pos)                   /*!< GPIO_T::MODE: MODE15 Mask              */
+
+#define GPIO_DINOFF_DINOFF0_Pos          (16)                                              /*!< GPIO_T::DINOFF: DINOFF0 Position       */
+#define GPIO_DINOFF_DINOFF0_Msk          (0x1ul << GPIO_DINOFF_DINOFF0_Pos)                /*!< GPIO_T::DINOFF: DINOFF0 Mask           */
+
+#define GPIO_DINOFF_DINOFF1_Pos          (17)                                              /*!< GPIO_T::DINOFF: DINOFF1 Position       */
+#define GPIO_DINOFF_DINOFF1_Msk          (0x1ul << GPIO_DINOFF_DINOFF1_Pos)                /*!< GPIO_T::DINOFF: DINOFF1 Mask           */
+
+#define GPIO_DINOFF_DINOFF2_Pos          (18)                                              /*!< GPIO_T::DINOFF: DINOFF2 Position       */
+#define GPIO_DINOFF_DINOFF2_Msk          (0x1ul << GPIO_DINOFF_DINOFF2_Pos)                /*!< GPIO_T::DINOFF: DINOFF2 Mask           */
+
+#define GPIO_DINOFF_DINOFF3_Pos          (19)                                              /*!< GPIO_T::DINOFF: DINOFF3 Position       */
+#define GPIO_DINOFF_DINOFF3_Msk          (0x1ul << GPIO_DINOFF_DINOFF3_Pos)                /*!< GPIO_T::DINOFF: DINOFF3 Mask           */
+
+#define GPIO_DINOFF_DINOFF4_Pos          (20)                                              /*!< GPIO_T::DINOFF: DINOFF4 Position       */
+#define GPIO_DINOFF_DINOFF4_Msk          (0x1ul << GPIO_DINOFF_DINOFF4_Pos)                /*!< GPIO_T::DINOFF: DINOFF4 Mask           */
+
+#define GPIO_DINOFF_DINOFF5_Pos          (21)                                              /*!< GPIO_T::DINOFF: DINOFF5 Position       */
+#define GPIO_DINOFF_DINOFF5_Msk          (0x1ul << GPIO_DINOFF_DINOFF5_Pos)                /*!< GPIO_T::DINOFF: DINOFF5 Mask           */
+
+#define GPIO_DINOFF_DINOFF6_Pos          (22)                                              /*!< GPIO_T::DINOFF: DINOFF6 Position       */
+#define GPIO_DINOFF_DINOFF6_Msk          (0x1ul << GPIO_DINOFF_DINOFF6_Pos)                /*!< GPIO_T::DINOFF: DINOFF6 Mask           */
+
+#define GPIO_DINOFF_DINOFF7_Pos          (23)                                              /*!< GPIO_T::DINOFF: DINOFF7 Position       */
+#define GPIO_DINOFF_DINOFF7_Msk          (0x1ul << GPIO_DINOFF_DINOFF7_Pos)                /*!< GPIO_T::DINOFF: DINOFF7 Mask           */
+
+#define GPIO_DINOFF_DINOFF8_Pos          (24)                                              /*!< GPIO_T::DINOFF: DINOFF8 Position       */
+#define GPIO_DINOFF_DINOFF8_Msk          (0x1ul << GPIO_DINOFF_DINOFF8_Pos)                /*!< GPIO_T::DINOFF: DINOFF8 Mask           */
+
+#define GPIO_DINOFF_DINOFF9_Pos          (25)                                              /*!< GPIO_T::DINOFF: DINOFF9 Position       */
+#define GPIO_DINOFF_DINOFF9_Msk          (0x1ul << GPIO_DINOFF_DINOFF9_Pos)                /*!< GPIO_T::DINOFF: DINOFF9 Mask           */
+
+#define GPIO_DINOFF_DINOFF10_Pos         (26)                                              /*!< GPIO_T::DINOFF: DINOFF10 Position      */
+#define GPIO_DINOFF_DINOFF10_Msk         (0x1ul << GPIO_DINOFF_DINOFF10_Pos)               /*!< GPIO_T::DINOFF: DINOFF10 Mask          */
+
+#define GPIO_DINOFF_DINOFF11_Pos         (27)                                              /*!< GPIO_T::DINOFF: DINOFF11 Position      */
+#define GPIO_DINOFF_DINOFF11_Msk         (0x1ul << GPIO_DINOFF_DINOFF11_Pos)               /*!< GPIO_T::DINOFF: DINOFF11 Mask          */
+
+#define GPIO_DINOFF_DINOFF12_Pos         (28)                                              /*!< GPIO_T::DINOFF: DINOFF12 Position      */
+#define GPIO_DINOFF_DINOFF12_Msk         (0x1ul << GPIO_DINOFF_DINOFF12_Pos)               /*!< GPIO_T::DINOFF: DINOFF12 Mask          */
+
+#define GPIO_DINOFF_DINOFF13_Pos         (29)                                              /*!< GPIO_T::DINOFF: DINOFF13 Position      */
+#define GPIO_DINOFF_DINOFF13_Msk         (0x1ul << GPIO_DINOFF_DINOFF13_Pos)               /*!< GPIO_T::DINOFF: DINOFF13 Mask          */
+
+#define GPIO_DINOFF_DINOFF14_Pos         (30)                                              /*!< GPIO_T::DINOFF: DINOFF14 Position      */
+#define GPIO_DINOFF_DINOFF14_Msk         (0x1ul << GPIO_DINOFF_DINOFF14_Pos)               /*!< GPIO_T::DINOFF: DINOFF14 Mask          */
+
+#define GPIO_DINOFF_DINOFF15_Pos         (31)                                              /*!< GPIO_T::DINOFF: DINOFF15 Position      */
+#define GPIO_DINOFF_DINOFF15_Msk         (0x1ul << GPIO_DINOFF_DINOFF15_Pos)               /*!< GPIO_T::DINOFF: DINOFF15 Mask          */
+
+#define GPIO_DOUT_DOUT0_Pos              (0)                                               /*!< GPIO_T::DOUT: DOUT0 Position           */
+#define GPIO_DOUT_DOUT0_Msk              (0x1ul << GPIO_DOUT_DOUT0_Pos)                    /*!< GPIO_T::DOUT: DOUT0 Mask               */
+
+#define GPIO_DOUT_DOUT1_Pos              (1)                                               /*!< GPIO_T::DOUT: DOUT1 Position           */
+#define GPIO_DOUT_DOUT1_Msk              (0x1ul << GPIO_DOUT_DOUT1_Pos)                    /*!< GPIO_T::DOUT: DOUT1 Mask               */
+
+#define GPIO_DOUT_DOUT2_Pos              (2)                                               /*!< GPIO_T::DOUT: DOUT2 Position           */
+#define GPIO_DOUT_DOUT2_Msk              (0x1ul << GPIO_DOUT_DOUT2_Pos)                    /*!< GPIO_T::DOUT: DOUT2 Mask               */
+
+#define GPIO_DOUT_DOUT3_Pos              (3)                                               /*!< GPIO_T::DOUT: DOUT3 Position           */
+#define GPIO_DOUT_DOUT3_Msk              (0x1ul << GPIO_DOUT_DOUT3_Pos)                    /*!< GPIO_T::DOUT: DOUT3 Mask               */
+
+#define GPIO_DOUT_DOUT4_Pos              (4)                                               /*!< GPIO_T::DOUT: DOUT4 Position           */
+#define GPIO_DOUT_DOUT4_Msk              (0x1ul << GPIO_DOUT_DOUT4_Pos)                    /*!< GPIO_T::DOUT: DOUT4 Mask               */
+
+#define GPIO_DOUT_DOUT5_Pos              (5)                                               /*!< GPIO_T::DOUT: DOUT5 Position           */
+#define GPIO_DOUT_DOUT5_Msk              (0x1ul << GPIO_DOUT_DOUT5_Pos)                    /*!< GPIO_T::DOUT: DOUT5 Mask               */
+
+#define GPIO_DOUT_DOUT6_Pos              (6)                                               /*!< GPIO_T::DOUT: DOUT6 Position           */
+#define GPIO_DOUT_DOUT6_Msk              (0x1ul << GPIO_DOUT_DOUT6_Pos)                    /*!< GPIO_T::DOUT: DOUT6 Mask               */
+
+#define GPIO_DOUT_DOUT7_Pos              (7)                                               /*!< GPIO_T::DOUT: DOUT7 Position           */
+#define GPIO_DOUT_DOUT7_Msk              (0x1ul << GPIO_DOUT_DOUT7_Pos)                    /*!< GPIO_T::DOUT: DOUT7 Mask               */
+
+#define GPIO_DOUT_DOUT8_Pos              (8)                                               /*!< GPIO_T::DOUT: DOUT8 Position           */
+#define GPIO_DOUT_DOUT8_Msk              (0x1ul << GPIO_DOUT_DOUT8_Pos)                    /*!< GPIO_T::DOUT: DOUT8 Mask               */
+
+#define GPIO_DOUT_DOUT9_Pos              (9)                                               /*!< GPIO_T::DOUT: DOUT9 Position           */
+#define GPIO_DOUT_DOUT9_Msk              (0x1ul << GPIO_DOUT_DOUT9_Pos)                    /*!< GPIO_T::DOUT: DOUT9 Mask               */
+
+#define GPIO_DOUT_DOUT10_Pos             (10)                                              /*!< GPIO_T::DOUT: DOUT10 Position          */
+#define GPIO_DOUT_DOUT10_Msk             (0x1ul << GPIO_DOUT_DOUT10_Pos)                   /*!< GPIO_T::DOUT: DOUT10 Mask              */
+
+#define GPIO_DOUT_DOUT11_Pos             (11)                                              /*!< GPIO_T::DOUT: DOUT11 Position          */
+#define GPIO_DOUT_DOUT11_Msk             (0x1ul << GPIO_DOUT_DOUT11_Pos)                   /*!< GPIO_T::DOUT: DOUT11 Mask              */
+
+#define GPIO_DOUT_DOUT12_Pos             (12)                                              /*!< GPIO_T::DOUT: DOUT12 Position          */
+#define GPIO_DOUT_DOUT12_Msk             (0x1ul << GPIO_DOUT_DOUT12_Pos)                   /*!< GPIO_T::DOUT: DOUT12 Mask              */
+
+#define GPIO_DOUT_DOUT13_Pos             (13)                                              /*!< GPIO_T::DOUT: DOUT13 Position          */
+#define GPIO_DOUT_DOUT13_Msk             (0x1ul << GPIO_DOUT_DOUT13_Pos)                   /*!< GPIO_T::DOUT: DOUT13 Mask              */
+
+#define GPIO_DOUT_DOUT14_Pos             (14)                                              /*!< GPIO_T::DOUT: DOUT14 Position          */
+#define GPIO_DOUT_DOUT14_Msk             (0x1ul << GPIO_DOUT_DOUT14_Pos)                   /*!< GPIO_T::DOUT: DOUT14 Mask              */
+
+#define GPIO_DOUT_DOUT15_Pos             (15)                                              /*!< GPIO_T::DOUT: DOUT15 Position          */
+#define GPIO_DOUT_DOUT15_Msk             (0x1ul << GPIO_DOUT_DOUT15_Pos)                   /*!< GPIO_T::DOUT: DOUT15 Mask              */
+
+#define GPIO_DATMSK_DATMSK0_Pos          (0)                                               /*!< GPIO_T::DATMSK: DATMSK0 Position       */
+#define GPIO_DATMSK_DATMSK0_Msk          (0x1ul << GPIO_DATMSK_DATMSK0_Pos)                /*!< GPIO_T::DATMSK: DATMSK0 Mask           */
+
+#define GPIO_DATMSK_DATMSK1_Pos          (1)                                               /*!< GPIO_T::DATMSK: DATMSK1 Position       */
+#define GPIO_DATMSK_DATMSK1_Msk          (0x1ul << GPIO_DATMSK_DATMSK1_Pos)                /*!< GPIO_T::DATMSK: DATMSK1 Mask           */
+
+#define GPIO_DATMSK_DATMSK2_Pos          (2)                                               /*!< GPIO_T::DATMSK: DATMSK2 Position       */
+#define GPIO_DATMSK_DATMSK2_Msk          (0x1ul << GPIO_DATMSK_DATMSK2_Pos)                /*!< GPIO_T::DATMSK: DATMSK2 Mask           */
+
+#define GPIO_DATMSK_DATMSK3_Pos          (3)                                               /*!< GPIO_T::DATMSK: DATMSK3 Position       */
+#define GPIO_DATMSK_DATMSK3_Msk          (0x1ul << GPIO_DATMSK_DATMSK3_Pos)                /*!< GPIO_T::DATMSK: DATMSK3 Mask           */
+
+#define GPIO_DATMSK_DATMSK4_Pos          (4)                                               /*!< GPIO_T::DATMSK: DATMSK4 Position       */
+#define GPIO_DATMSK_DATMSK4_Msk          (0x1ul << GPIO_DATMSK_DATMSK4_Pos)                /*!< GPIO_T::DATMSK: DATMSK4 Mask           */
+
+#define GPIO_DATMSK_DATMSK5_Pos          (5)                                               /*!< GPIO_T::DATMSK: DATMSK5 Position       */
+#define GPIO_DATMSK_DATMSK5_Msk          (0x1ul << GPIO_DATMSK_DATMSK5_Pos)                /*!< GPIO_T::DATMSK: DATMSK5 Mask           */
+
+#define GPIO_DATMSK_DATMSK6_Pos          (6)                                               /*!< GPIO_T::DATMSK: DATMSK6 Position       */
+#define GPIO_DATMSK_DATMSK6_Msk          (0x1ul << GPIO_DATMSK_DATMSK6_Pos)                /*!< GPIO_T::DATMSK: DATMSK6 Mask           */
+
+#define GPIO_DATMSK_DATMSK7_Pos          (7)                                               /*!< GPIO_T::DATMSK: DATMSK7 Position       */
+#define GPIO_DATMSK_DATMSK7_Msk          (0x1ul << GPIO_DATMSK_DATMSK7_Pos)                /*!< GPIO_T::DATMSK: DATMSK7 Mask           */
+
+#define GPIO_DATMSK_DATMSK8_Pos          (8)                                               /*!< GPIO_T::DATMSK: DATMSK8 Position       */
+#define GPIO_DATMSK_DATMSK8_Msk          (0x1ul << GPIO_DATMSK_DATMSK8_Pos)                /*!< GPIO_T::DATMSK: DATMSK8 Mask           */
+
+#define GPIO_DATMSK_DATMSK9_Pos          (9)                                               /*!< GPIO_T::DATMSK: DATMSK9 Position       */
+#define GPIO_DATMSK_DATMSK9_Msk          (0x1ul << GPIO_DATMSK_DATMSK9_Pos)                /*!< GPIO_T::DATMSK: DATMSK9 Mask           */
+
+#define GPIO_DATMSK_DATMSK10_Pos         (10)                                              /*!< GPIO_T::DATMSK: DATMSK10 Position      */
+#define GPIO_DATMSK_DATMSK10_Msk         (0x1ul << GPIO_DATMSK_DATMSK10_Pos)               /*!< GPIO_T::DATMSK: DATMSK10 Mask          */
+
+#define GPIO_DATMSK_DATMSK11_Pos         (11)                                              /*!< GPIO_T::DATMSK: DATMSK11 Position      */
+#define GPIO_DATMSK_DATMSK11_Msk         (0x1ul << GPIO_DATMSK_DATMSK11_Pos)               /*!< GPIO_T::DATMSK: DATMSK11 Mask          */
+
+#define GPIO_DATMSK_DATMSK12_Pos         (12)                                              /*!< GPIO_T::DATMSK: DATMSK12 Position      */
+#define GPIO_DATMSK_DATMSK12_Msk         (0x1ul << GPIO_DATMSK_DATMSK12_Pos)               /*!< GPIO_T::DATMSK: DATMSK12 Mask          */
+
+#define GPIO_DATMSK_DATMSK13_Pos         (13)                                              /*!< GPIO_T::DATMSK: DATMSK13 Position      */
+#define GPIO_DATMSK_DATMSK13_Msk         (0x1ul << GPIO_DATMSK_DATMSK13_Pos)               /*!< GPIO_T::DATMSK: DATMSK13 Mask          */
+
+#define GPIO_DATMSK_DATMSK14_Pos         (14)                                              /*!< GPIO_T::DATMSK: DATMSK14 Position      */
+#define GPIO_DATMSK_DATMSK14_Msk         (0x1ul << GPIO_DATMSK_DATMSK14_Pos)               /*!< GPIO_T::DATMSK: DATMSK14 Mask          */
+
+#define GPIO_DATMSK_DATMSK15_Pos         (15)                                              /*!< GPIO_T::DATMSK: DATMSK15 Position      */
+#define GPIO_DATMSK_DATMSK15_Msk         (0x1ul << GPIO_DATMSK_DATMSK15_Pos)               /*!< GPIO_T::DATMSK: DATMSK15 Mask          */
+
+#define GPIO_PIN_PIN0_Pos                (0)                                               /*!< GPIO_T::PIN: PIN0 Position             */
+#define GPIO_PIN_PIN0_Msk                (0x1ul << GPIO_PIN_PIN0_Pos)                      /*!< GPIO_T::PIN: PIN0 Mask                 */
+
+#define GPIO_PIN_PIN1_Pos                (1)                                               /*!< GPIO_T::PIN: PIN1 Position             */
+#define GPIO_PIN_PIN1_Msk                (0x1ul << GPIO_PIN_PIN1_Pos)                      /*!< GPIO_T::PIN: PIN1 Mask                 */
+
+#define GPIO_PIN_PIN2_Pos                (2)                                               /*!< GPIO_T::PIN: PIN2 Position             */
+#define GPIO_PIN_PIN2_Msk                (0x1ul << GPIO_PIN_PIN2_Pos)                      /*!< GPIO_T::PIN: PIN2 Mask                 */
+
+#define GPIO_PIN_PIN3_Pos                (3)                                               /*!< GPIO_T::PIN: PIN3 Position             */
+#define GPIO_PIN_PIN3_Msk                (0x1ul << GPIO_PIN_PIN3_Pos)                      /*!< GPIO_T::PIN: PIN3 Mask                 */
+
+#define GPIO_PIN_PIN4_Pos                (4)                                               /*!< GPIO_T::PIN: PIN4 Position             */
+#define GPIO_PIN_PIN4_Msk                (0x1ul << GPIO_PIN_PIN4_Pos)                      /*!< GPIO_T::PIN: PIN4 Mask                 */
+
+#define GPIO_PIN_PIN5_Pos                (5)                                               /*!< GPIO_T::PIN: PIN5 Position             */
+#define GPIO_PIN_PIN5_Msk                (0x1ul << GPIO_PIN_PIN5_Pos)                      /*!< GPIO_T::PIN: PIN5 Mask                 */
+
+#define GPIO_PIN_PIN6_Pos                (6)                                               /*!< GPIO_T::PIN: PIN6 Position             */
+#define GPIO_PIN_PIN6_Msk                (0x1ul << GPIO_PIN_PIN6_Pos)                      /*!< GPIO_T::PIN: PIN6 Mask                 */
+
+#define GPIO_PIN_PIN7_Pos                (7)                                               /*!< GPIO_T::PIN: PIN7 Position             */
+#define GPIO_PIN_PIN7_Msk                (0x1ul << GPIO_PIN_PIN7_Pos)                      /*!< GPIO_T::PIN: PIN7 Mask                 */
+
+#define GPIO_PIN_PIN8_Pos                (8)                                               /*!< GPIO_T::PIN: PIN8 Position             */
+#define GPIO_PIN_PIN8_Msk                (0x1ul << GPIO_PIN_PIN8_Pos)                      /*!< GPIO_T::PIN: PIN8 Mask                 */
+
+#define GPIO_PIN_PIN9_Pos                (9)                                               /*!< GPIO_T::PIN: PIN9 Position             */
+#define GPIO_PIN_PIN9_Msk                (0x1ul << GPIO_PIN_PIN9_Pos)                      /*!< GPIO_T::PIN: PIN9 Mask                 */
+
+#define GPIO_PIN_PIN10_Pos               (10)                                              /*!< GPIO_T::PIN: PIN10 Position            */
+#define GPIO_PIN_PIN10_Msk               (0x1ul << GPIO_PIN_PIN10_Pos)                     /*!< GPIO_T::PIN: PIN10 Mask                */
+
+#define GPIO_PIN_PIN11_Pos               (11)                                              /*!< GPIO_T::PIN: PIN11 Position            */
+#define GPIO_PIN_PIN11_Msk               (0x1ul << GPIO_PIN_PIN11_Pos)                     /*!< GPIO_T::PIN: PIN11 Mask                */
+
+#define GPIO_PIN_PIN12_Pos               (12)                                              /*!< GPIO_T::PIN: PIN12 Position            */
+#define GPIO_PIN_PIN12_Msk               (0x1ul << GPIO_PIN_PIN12_Pos)                     /*!< GPIO_T::PIN: PIN12 Mask                */
+
+#define GPIO_PIN_PIN13_Pos               (13)                                              /*!< GPIO_T::PIN: PIN13 Position            */
+#define GPIO_PIN_PIN13_Msk               (0x1ul << GPIO_PIN_PIN13_Pos)                     /*!< GPIO_T::PIN: PIN13 Mask                */
+
+#define GPIO_PIN_PIN14_Pos               (14)                                              /*!< GPIO_T::PIN: PIN14 Position            */
+#define GPIO_PIN_PIN14_Msk               (0x1ul << GPIO_PIN_PIN14_Pos)                     /*!< GPIO_T::PIN: PIN14 Mask                */
+
+#define GPIO_PIN_PIN15_Pos               (15)                                              /*!< GPIO_T::PIN: PIN15 Position            */
+#define GPIO_PIN_PIN15_Msk               (0x1ul << GPIO_PIN_PIN15_Pos)                     /*!< GPIO_T::PIN: PIN15 Mask                */
+
+#define GPIO_DBEN_DBEN0_Pos              (0)                                               /*!< GPIO_T::DBEN: DBEN0 Position           */
+#define GPIO_DBEN_DBEN0_Msk              (0x1ul << GPIO_DBEN_DBEN0_Pos)                    /*!< GPIO_T::DBEN: DBEN0 Mask               */
+
+#define GPIO_DBEN_DBEN1_Pos              (1)                                               /*!< GPIO_T::DBEN: DBEN1 Position           */
+#define GPIO_DBEN_DBEN1_Msk              (0x1ul << GPIO_DBEN_DBEN1_Pos)                    /*!< GPIO_T::DBEN: DBEN1 Mask               */
+
+#define GPIO_DBEN_DBEN2_Pos              (2)                                               /*!< GPIO_T::DBEN: DBEN2 Position           */
+#define GPIO_DBEN_DBEN2_Msk              (0x1ul << GPIO_DBEN_DBEN2_Pos)                    /*!< GPIO_T::DBEN: DBEN2 Mask               */
+
+#define GPIO_DBEN_DBEN3_Pos              (3)                                               /*!< GPIO_T::DBEN: DBEN3 Position           */
+#define GPIO_DBEN_DBEN3_Msk              (0x1ul << GPIO_DBEN_DBEN3_Pos)                    /*!< GPIO_T::DBEN: DBEN3 Mask               */
+
+#define GPIO_DBEN_DBEN4_Pos              (4)                                               /*!< GPIO_T::DBEN: DBEN4 Position           */
+#define GPIO_DBEN_DBEN4_Msk              (0x1ul << GPIO_DBEN_DBEN4_Pos)                    /*!< GPIO_T::DBEN: DBEN4 Mask               */
+
+#define GPIO_DBEN_DBEN5_Pos              (5)                                               /*!< GPIO_T::DBEN: DBEN5 Position           */
+#define GPIO_DBEN_DBEN5_Msk              (0x1ul << GPIO_DBEN_DBEN5_Pos)                    /*!< GPIO_T::DBEN: DBEN5 Mask               */
+
+#define GPIO_DBEN_DBEN6_Pos              (6)                                               /*!< GPIO_T::DBEN: DBEN6 Position           */
+#define GPIO_DBEN_DBEN6_Msk              (0x1ul << GPIO_DBEN_DBEN6_Pos)                    /*!< GPIO_T::DBEN: DBEN6 Mask               */
+
+#define GPIO_DBEN_DBEN7_Pos              (7)                                               /*!< GPIO_T::DBEN: DBEN7 Position           */
+#define GPIO_DBEN_DBEN7_Msk              (0x1ul << GPIO_DBEN_DBEN7_Pos)                    /*!< GPIO_T::DBEN: DBEN7 Mask               */
+
+#define GPIO_DBEN_DBEN8_Pos              (8)                                               /*!< GPIO_T::DBEN: DBEN8 Position           */
+#define GPIO_DBEN_DBEN8_Msk              (0x1ul << GPIO_DBEN_DBEN8_Pos)                    /*!< GPIO_T::DBEN: DBEN8 Mask               */
+
+#define GPIO_DBEN_DBEN9_Pos              (9)                                               /*!< GPIO_T::DBEN: DBEN9 Position           */
+#define GPIO_DBEN_DBEN9_Msk              (0x1ul << GPIO_DBEN_DBEN9_Pos)                    /*!< GPIO_T::DBEN: DBEN9 Mask               */
+
+#define GPIO_DBEN_DBEN10_Pos             (10)                                              /*!< GPIO_T::DBEN: DBEN10 Position          */
+#define GPIO_DBEN_DBEN10_Msk             (0x1ul << GPIO_DBEN_DBEN10_Pos)                   /*!< GPIO_T::DBEN: DBEN10 Mask              */
+
+#define GPIO_DBEN_DBEN11_Pos             (11)                                              /*!< GPIO_T::DBEN: DBEN11 Position          */
+#define GPIO_DBEN_DBEN11_Msk             (0x1ul << GPIO_DBEN_DBEN11_Pos)                   /*!< GPIO_T::DBEN: DBEN11 Mask              */
+
+#define GPIO_DBEN_DBEN12_Pos             (12)                                              /*!< GPIO_T::DBEN: DBEN12 Position          */
+#define GPIO_DBEN_DBEN12_Msk             (0x1ul << GPIO_DBEN_DBEN12_Pos)                   /*!< GPIO_T::DBEN: DBEN12 Mask              */
+
+#define GPIO_DBEN_DBEN13_Pos             (13)                                              /*!< GPIO_T::DBEN: DBEN13 Position          */
+#define GPIO_DBEN_DBEN13_Msk             (0x1ul << GPIO_DBEN_DBEN13_Pos)                   /*!< GPIO_T::DBEN: DBEN13 Mask              */
+
+#define GPIO_DBEN_DBEN14_Pos             (14)                                              /*!< GPIO_T::DBEN: DBEN14 Position          */
+#define GPIO_DBEN_DBEN14_Msk             (0x1ul << GPIO_DBEN_DBEN14_Pos)                   /*!< GPIO_T::DBEN: DBEN14 Mask              */
+
+#define GPIO_DBEN_DBEN15_Pos             (15)                                              /*!< GPIO_T::DBEN: DBEN15 Position          */
+#define GPIO_DBEN_DBEN15_Msk             (0x1ul << GPIO_DBEN_DBEN15_Pos)                   /*!< GPIO_T::DBEN: DBEN15 Mask              */
+
+#define GPIO_INTTYPE_TYPE0_Pos           (0)                                               /*!< GPIO_T::INTTYPE: TYPE0 Position        */
+#define GPIO_INTTYPE_TYPE0_Msk           (0x1ul << GPIO_INTTYPE_TYPE0_Pos)                 /*!< GPIO_T::INTTYPE: TYPE0 Mask            */
+
+#define GPIO_INTTYPE_TYPE1_Pos           (1)                                               /*!< GPIO_T::INTTYPE: TYPE1 Position        */
+#define GPIO_INTTYPE_TYPE1_Msk           (0x1ul << GPIO_INTTYPE_TYPE1_Pos)                 /*!< GPIO_T::INTTYPE: TYPE1 Mask            */
+
+#define GPIO_INTTYPE_TYPE2_Pos           (2)                                               /*!< GPIO_T::INTTYPE: TYPE2 Position        */
+#define GPIO_INTTYPE_TYPE2_Msk           (0x1ul << GPIO_INTTYPE_TYPE2_Pos)                 /*!< GPIO_T::INTTYPE: TYPE2 Mask            */
+
+#define GPIO_INTTYPE_TYPE3_Pos           (3)                                               /*!< GPIO_T::INTTYPE: TYPE3 Position        */
+#define GPIO_INTTYPE_TYPE3_Msk           (0x1ul << GPIO_INTTYPE_TYPE3_Pos)                 /*!< GPIO_T::INTTYPE: TYPE3 Mask            */
+
+#define GPIO_INTTYPE_TYPE4_Pos           (4)                                               /*!< GPIO_T::INTTYPE: TYPE4 Position        */
+#define GPIO_INTTYPE_TYPE4_Msk           (0x1ul << GPIO_INTTYPE_TYPE4_Pos)                 /*!< GPIO_T::INTTYPE: TYPE4 Mask            */
+
+#define GPIO_INTTYPE_TYPE5_Pos           (5)                                               /*!< GPIO_T::INTTYPE: TYPE5 Position        */
+#define GPIO_INTTYPE_TYPE5_Msk           (0x1ul << GPIO_INTTYPE_TYPE5_Pos)                 /*!< GPIO_T::INTTYPE: TYPE5 Mask            */
+
+#define GPIO_INTTYPE_TYPE6_Pos           (6)                                               /*!< GPIO_T::INTTYPE: TYPE6 Position        */
+#define GPIO_INTTYPE_TYPE6_Msk           (0x1ul << GPIO_INTTYPE_TYPE6_Pos)                 /*!< GPIO_T::INTTYPE: TYPE6 Mask            */
+
+#define GPIO_INTTYPE_TYPE7_Pos           (7)                                               /*!< GPIO_T::INTTYPE: TYPE7 Position        */
+#define GPIO_INTTYPE_TYPE7_Msk           (0x1ul << GPIO_INTTYPE_TYPE7_Pos)                 /*!< GPIO_T::INTTYPE: TYPE7 Mask            */
+
+#define GPIO_INTTYPE_TYPE8_Pos           (8)                                               /*!< GPIO_T::INTTYPE: TYPE8 Position        */
+#define GPIO_INTTYPE_TYPE8_Msk           (0x1ul << GPIO_INTTYPE_TYPE8_Pos)                 /*!< GPIO_T::INTTYPE: TYPE8 Mask            */
+
+#define GPIO_INTTYPE_TYPE9_Pos           (9)                                               /*!< GPIO_T::INTTYPE: TYPE9 Position        */
+#define GPIO_INTTYPE_TYPE9_Msk           (0x1ul << GPIO_INTTYPE_TYPE9_Pos)                 /*!< GPIO_T::INTTYPE: TYPE9 Mask            */
+
+#define GPIO_INTTYPE_TYPE10_Pos          (10)                                              /*!< GPIO_T::INTTYPE: TYPE10 Position       */
+#define GPIO_INTTYPE_TYPE10_Msk          (0x1ul << GPIO_INTTYPE_TYPE10_Pos)                /*!< GPIO_T::INTTYPE: TYPE10 Mask           */
+
+#define GPIO_INTTYPE_TYPE11_Pos          (11)                                              /*!< GPIO_T::INTTYPE: TYPE11 Position       */
+#define GPIO_INTTYPE_TYPE11_Msk          (0x1ul << GPIO_INTTYPE_TYPE11_Pos)                /*!< GPIO_T::INTTYPE: TYPE11 Mask           */
+
+#define GPIO_INTTYPE_TYPE12_Pos          (12)                                              /*!< GPIO_T::INTTYPE: TYPE12 Position       */
+#define GPIO_INTTYPE_TYPE12_Msk          (0x1ul << GPIO_INTTYPE_TYPE12_Pos)                /*!< GPIO_T::INTTYPE: TYPE12 Mask           */
+
+#define GPIO_INTTYPE_TYPE13_Pos          (13)                                              /*!< GPIO_T::INTTYPE: TYPE13 Position       */
+#define GPIO_INTTYPE_TYPE13_Msk          (0x1ul << GPIO_INTTYPE_TYPE13_Pos)                /*!< GPIO_T::INTTYPE: TYPE13 Mask           */
+
+#define GPIO_INTTYPE_TYPE14_Pos          (14)                                              /*!< GPIO_T::INTTYPE: TYPE14 Position       */
+#define GPIO_INTTYPE_TYPE14_Msk          (0x1ul << GPIO_INTTYPE_TYPE14_Pos)                /*!< GPIO_T::INTTYPE: TYPE14 Mask           */
+
+#define GPIO_INTTYPE_TYPE15_Pos          (15)                                              /*!< GPIO_T::INTTYPE: TYPE15 Position       */
+#define GPIO_INTTYPE_TYPE15_Msk          (0x1ul << GPIO_INTTYPE_TYPE15_Pos)                /*!< GPIO_T::INTTYPE: TYPE15 Mask           */
+
+#define GPIO_INTEN_FLIEN0_Pos            (0)                                               /*!< GPIO_T::INTEN: FLIEN0 Position         */
+#define GPIO_INTEN_FLIEN0_Msk            (0x1ul << GPIO_INTEN_FLIEN0_Pos)                  /*!< GPIO_T::INTEN: FLIEN0 Mask             */
+
+#define GPIO_INTEN_FLIEN1_Pos            (1)                                               /*!< GPIO_T::INTEN: FLIEN1 Position         */
+#define GPIO_INTEN_FLIEN1_Msk            (0x1ul << GPIO_INTEN_FLIEN1_Pos)                  /*!< GPIO_T::INTEN: FLIEN1 Mask             */
+
+#define GPIO_INTEN_FLIEN2_Pos            (2)                                               /*!< GPIO_T::INTEN: FLIEN2 Position         */
+#define GPIO_INTEN_FLIEN2_Msk            (0x1ul << GPIO_INTEN_FLIEN2_Pos)                  /*!< GPIO_T::INTEN: FLIEN2 Mask             */
+
+#define GPIO_INTEN_FLIEN3_Pos            (3)                                               /*!< GPIO_T::INTEN: FLIEN3 Position         */
+#define GPIO_INTEN_FLIEN3_Msk            (0x1ul << GPIO_INTEN_FLIEN3_Pos)                  /*!< GPIO_T::INTEN: FLIEN3 Mask             */
+
+#define GPIO_INTEN_FLIEN4_Pos            (4)                                               /*!< GPIO_T::INTEN: FLIEN4 Position         */
+#define GPIO_INTEN_FLIEN4_Msk            (0x1ul << GPIO_INTEN_FLIEN4_Pos)                  /*!< GPIO_T::INTEN: FLIEN4 Mask             */
+
+#define GPIO_INTEN_FLIEN5_Pos            (5)                                               /*!< GPIO_T::INTEN: FLIEN5 Position         */
+#define GPIO_INTEN_FLIEN5_Msk            (0x1ul << GPIO_INTEN_FLIEN5_Pos)                  /*!< GPIO_T::INTEN: FLIEN5 Mask             */
+
+#define GPIO_INTEN_FLIEN6_Pos            (6)                                               /*!< GPIO_T::INTEN: FLIEN6 Position         */
+#define GPIO_INTEN_FLIEN6_Msk            (0x1ul << GPIO_INTEN_FLIEN6_Pos)                  /*!< GPIO_T::INTEN: FLIEN6 Mask             */
+
+#define GPIO_INTEN_FLIEN7_Pos            (7)                                               /*!< GPIO_T::INTEN: FLIEN7 Position         */
+#define GPIO_INTEN_FLIEN7_Msk            (0x1ul << GPIO_INTEN_FLIEN7_Pos)                  /*!< GPIO_T::INTEN: FLIEN7 Mask             */
+
+#define GPIO_INTEN_FLIEN8_Pos            (8)                                               /*!< GPIO_T::INTEN: FLIEN8 Position         */
+#define GPIO_INTEN_FLIEN8_Msk            (0x1ul << GPIO_INTEN_FLIEN8_Pos)                  /*!< GPIO_T::INTEN: FLIEN8 Mask             */
+
+#define GPIO_INTEN_FLIEN9_Pos            (9)                                               /*!< GPIO_T::INTEN: FLIEN9 Position         */
+#define GPIO_INTEN_FLIEN9_Msk            (0x1ul << GPIO_INTEN_FLIEN9_Pos)                  /*!< GPIO_T::INTEN: FLIEN9 Mask             */
+
+#define GPIO_INTEN_FLIEN10_Pos           (10)                                              /*!< GPIO_T::INTEN: FLIEN10 Position        */
+#define GPIO_INTEN_FLIEN10_Msk           (0x1ul << GPIO_INTEN_FLIEN10_Pos)                 /*!< GPIO_T::INTEN: FLIEN10 Mask            */
+
+#define GPIO_INTEN_FLIEN11_Pos           (11)                                              /*!< GPIO_T::INTEN: FLIEN11 Position        */
+#define GPIO_INTEN_FLIEN11_Msk           (0x1ul << GPIO_INTEN_FLIEN11_Pos)                 /*!< GPIO_T::INTEN: FLIEN11 Mask            */
+
+#define GPIO_INTEN_FLIEN12_Pos           (12)                                              /*!< GPIO_T::INTEN: FLIEN12 Position        */
+#define GPIO_INTEN_FLIEN12_Msk           (0x1ul << GPIO_INTEN_FLIEN12_Pos)                 /*!< GPIO_T::INTEN: FLIEN12 Mask            */
+
+#define GPIO_INTEN_FLIEN13_Pos           (13)                                              /*!< GPIO_T::INTEN: FLIEN13 Position        */
+#define GPIO_INTEN_FLIEN13_Msk           (0x1ul << GPIO_INTEN_FLIEN13_Pos)                 /*!< GPIO_T::INTEN: FLIEN13 Mask            */
+
+#define GPIO_INTEN_FLIEN14_Pos           (14)                                              /*!< GPIO_T::INTEN: FLIEN14 Position        */
+#define GPIO_INTEN_FLIEN14_Msk           (0x1ul << GPIO_INTEN_FLIEN14_Pos)                 /*!< GPIO_T::INTEN: FLIEN14 Mask            */
+
+#define GPIO_INTEN_FLIEN15_Pos           (15)                                              /*!< GPIO_T::INTEN: FLIEN15 Position        */
+#define GPIO_INTEN_FLIEN15_Msk           (0x1ul << GPIO_INTEN_FLIEN15_Pos)                 /*!< GPIO_T::INTEN: FLIEN15 Mask            */
+
+#define GPIO_INTEN_RHIEN0_Pos            (16)                                              /*!< GPIO_T::INTEN: RHIEN0 Position         */
+#define GPIO_INTEN_RHIEN0_Msk            (0x1ul << GPIO_INTEN_RHIEN0_Pos)                  /*!< GPIO_T::INTEN: RHIEN0 Mask             */
+
+#define GPIO_INTEN_RHIEN1_Pos            (17)                                              /*!< GPIO_T::INTEN: RHIEN1 Position         */
+#define GPIO_INTEN_RHIEN1_Msk            (0x1ul << GPIO_INTEN_RHIEN1_Pos)                  /*!< GPIO_T::INTEN: RHIEN1 Mask             */
+
+#define GPIO_INTEN_RHIEN2_Pos            (18)                                              /*!< GPIO_T::INTEN: RHIEN2 Position         */
+#define GPIO_INTEN_RHIEN2_Msk            (0x1ul << GPIO_INTEN_RHIEN2_Pos)                  /*!< GPIO_T::INTEN: RHIEN2 Mask             */
+
+#define GPIO_INTEN_RHIEN3_Pos            (19)                                              /*!< GPIO_T::INTEN: RHIEN3 Position         */
+#define GPIO_INTEN_RHIEN3_Msk            (0x1ul << GPIO_INTEN_RHIEN3_Pos)                  /*!< GPIO_T::INTEN: RHIEN3 Mask             */
+
+#define GPIO_INTEN_RHIEN4_Pos            (20)                                              /*!< GPIO_T::INTEN: RHIEN4 Position         */
+#define GPIO_INTEN_RHIEN4_Msk            (0x1ul << GPIO_INTEN_RHIEN4_Pos)                  /*!< GPIO_T::INTEN: RHIEN4 Mask             */
+
+#define GPIO_INTEN_RHIEN5_Pos            (21)                                              /*!< GPIO_T::INTEN: RHIEN5 Position         */
+#define GPIO_INTEN_RHIEN5_Msk            (0x1ul << GPIO_INTEN_RHIEN5_Pos)                  /*!< GPIO_T::INTEN: RHIEN5 Mask             */
+
+#define GPIO_INTEN_RHIEN6_Pos            (22)                                              /*!< GPIO_T::INTEN: RHIEN6 Position         */
+#define GPIO_INTEN_RHIEN6_Msk            (0x1ul << GPIO_INTEN_RHIEN6_Pos)                  /*!< GPIO_T::INTEN: RHIEN6 Mask             */
+
+#define GPIO_INTEN_RHIEN7_Pos            (23)                                              /*!< GPIO_T::INTEN: RHIEN7 Position         */
+#define GPIO_INTEN_RHIEN7_Msk            (0x1ul << GPIO_INTEN_RHIEN7_Pos)                  /*!< GPIO_T::INTEN: RHIEN7 Mask             */
+
+#define GPIO_INTEN_RHIEN8_Pos            (24)                                              /*!< GPIO_T::INTEN: RHIEN8 Position         */
+#define GPIO_INTEN_RHIEN8_Msk            (0x1ul << GPIO_INTEN_RHIEN8_Pos)                  /*!< GPIO_T::INTEN: RHIEN8 Mask             */
+
+#define GPIO_INTEN_RHIEN9_Pos            (25)                                              /*!< GPIO_T::INTEN: RHIEN9 Position         */
+#define GPIO_INTEN_RHIEN9_Msk            (0x1ul << GPIO_INTEN_RHIEN9_Pos)                  /*!< GPIO_T::INTEN: RHIEN9 Mask             */
+
+#define GPIO_INTEN_RHIEN10_Pos           (26)                                              /*!< GPIO_T::INTEN: RHIEN10 Position        */
+#define GPIO_INTEN_RHIEN10_Msk           (0x1ul << GPIO_INTEN_RHIEN10_Pos)                 /*!< GPIO_T::INTEN: RHIEN10 Mask            */
+
+#define GPIO_INTEN_RHIEN11_Pos           (27)                                              /*!< GPIO_T::INTEN: RHIEN11 Position        */
+#define GPIO_INTEN_RHIEN11_Msk           (0x1ul << GPIO_INTEN_RHIEN11_Pos)                 /*!< GPIO_T::INTEN: RHIEN11 Mask            */
+
+#define GPIO_INTEN_RHIEN12_Pos           (28)                                              /*!< GPIO_T::INTEN: RHIEN12 Position        */
+#define GPIO_INTEN_RHIEN12_Msk           (0x1ul << GPIO_INTEN_RHIEN12_Pos)                 /*!< GPIO_T::INTEN: RHIEN12 Mask            */
+
+#define GPIO_INTEN_RHIEN13_Pos           (29)                                              /*!< GPIO_T::INTEN: RHIEN13 Position        */
+#define GPIO_INTEN_RHIEN13_Msk           (0x1ul << GPIO_INTEN_RHIEN13_Pos)                 /*!< GPIO_T::INTEN: RHIEN13 Mask            */
+
+#define GPIO_INTEN_RHIEN14_Pos           (30)                                              /*!< GPIO_T::INTEN: RHIEN14 Position        */
+#define GPIO_INTEN_RHIEN14_Msk           (0x1ul << GPIO_INTEN_RHIEN14_Pos)                 /*!< GPIO_T::INTEN: RHIEN14 Mask            */
+
+#define GPIO_INTEN_RHIEN15_Pos           (31)                                              /*!< GPIO_T::INTEN: RHIEN15 Position        */
+#define GPIO_INTEN_RHIEN15_Msk           (0x1ul << GPIO_INTEN_RHIEN15_Pos)                 /*!< GPIO_T::INTEN: RHIEN15 Mask            */
+
+#define GPIO_INTSRC_INTSRC0_Pos          (0)                                               /*!< GPIO_T::INTSRC: INTSRC0 Position       */
+#define GPIO_INTSRC_INTSRC0_Msk          (0x1ul << GPIO_INTSRC_INTSRC0_Pos)                /*!< GPIO_T::INTSRC: INTSRC0 Mask           */
+
+#define GPIO_INTSRC_INTSRC1_Pos          (1)                                               /*!< GPIO_T::INTSRC: INTSRC1 Position       */
+#define GPIO_INTSRC_INTSRC1_Msk          (0x1ul << GPIO_INTSRC_INTSRC1_Pos)                /*!< GPIO_T::INTSRC: INTSRC1 Mask           */
+
+#define GPIO_INTSRC_INTSRC2_Pos          (2)                                               /*!< GPIO_T::INTSRC: INTSRC2 Position       */
+#define GPIO_INTSRC_INTSRC2_Msk          (0x1ul << GPIO_INTSRC_INTSRC2_Pos)                /*!< GPIO_T::INTSRC: INTSRC2 Mask           */
+
+#define GPIO_INTSRC_INTSRC3_Pos          (3)                                               /*!< GPIO_T::INTSRC: INTSRC3 Position       */
+#define GPIO_INTSRC_INTSRC3_Msk          (0x1ul << GPIO_INTSRC_INTSRC3_Pos)                /*!< GPIO_T::INTSRC: INTSRC3 Mask           */
+
+#define GPIO_INTSRC_INTSRC4_Pos          (4)                                               /*!< GPIO_T::INTSRC: INTSRC4 Position       */
+#define GPIO_INTSRC_INTSRC4_Msk          (0x1ul << GPIO_INTSRC_INTSRC4_Pos)                /*!< GPIO_T::INTSRC: INTSRC4 Mask           */
+
+#define GPIO_INTSRC_INTSRC5_Pos          (5)                                               /*!< GPIO_T::INTSRC: INTSRC5 Position       */
+#define GPIO_INTSRC_INTSRC5_Msk          (0x1ul << GPIO_INTSRC_INTSRC5_Pos)                /*!< GPIO_T::INTSRC: INTSRC5 Mask           */
+
+#define GPIO_INTSRC_INTSRC6_Pos          (6)                                               /*!< GPIO_T::INTSRC: INTSRC6 Position       */
+#define GPIO_INTSRC_INTSRC6_Msk          (0x1ul << GPIO_INTSRC_INTSRC6_Pos)                /*!< GPIO_T::INTSRC: INTSRC6 Mask           */
+
+#define GPIO_INTSRC_INTSRC7_Pos          (7)                                               /*!< GPIO_T::INTSRC: INTSRC7 Position       */
+#define GPIO_INTSRC_INTSRC7_Msk          (0x1ul << GPIO_INTSRC_INTSRC7_Pos)                /*!< GPIO_T::INTSRC: INTSRC7 Mask           */
+
+#define GPIO_INTSRC_INTSRC8_Pos          (8)                                               /*!< GPIO_T::INTSRC: INTSRC8 Position       */
+#define GPIO_INTSRC_INTSRC8_Msk          (0x1ul << GPIO_INTSRC_INTSRC8_Pos)                /*!< GPIO_T::INTSRC: INTSRC8 Mask           */
+
+#define GPIO_INTSRC_INTSRC9_Pos          (9)                                               /*!< GPIO_T::INTSRC: INTSRC9 Position       */
+#define GPIO_INTSRC_INTSRC9_Msk          (0x1ul << GPIO_INTSRC_INTSRC9_Pos)                /*!< GPIO_T::INTSRC: INTSRC9 Mask           */
+
+#define GPIO_INTSRC_INTSRC10_Pos         (10)                                              /*!< GPIO_T::INTSRC: INTSRC10 Position      */
+#define GPIO_INTSRC_INTSRC10_Msk         (0x1ul << GPIO_INTSRC_INTSRC10_Pos)               /*!< GPIO_T::INTSRC: INTSRC10 Mask          */
+
+#define GPIO_INTSRC_INTSRC11_Pos         (11)                                              /*!< GPIO_T::INTSRC: INTSRC11 Position      */
+#define GPIO_INTSRC_INTSRC11_Msk         (0x1ul << GPIO_INTSRC_INTSRC11_Pos)               /*!< GPIO_T::INTSRC: INTSRC11 Mask          */
+
+#define GPIO_INTSRC_INTSRC12_Pos         (12)                                              /*!< GPIO_T::INTSRC: INTSRC12 Position      */
+#define GPIO_INTSRC_INTSRC12_Msk         (0x1ul << GPIO_INTSRC_INTSRC12_Pos)               /*!< GPIO_T::INTSRC: INTSRC12 Mask          */
+
+#define GPIO_INTSRC_INTSRC13_Pos         (13)                                              /*!< GPIO_T::INTSRC: INTSRC13 Position      */
+#define GPIO_INTSRC_INTSRC13_Msk         (0x1ul << GPIO_INTSRC_INTSRC13_Pos)               /*!< GPIO_T::INTSRC: INTSRC13 Mask          */
+
+#define GPIO_INTSRC_INTSRC14_Pos         (14)                                              /*!< GPIO_T::INTSRC: INTSRC14 Position      */
+#define GPIO_INTSRC_INTSRC14_Msk         (0x1ul << GPIO_INTSRC_INTSRC14_Pos)               /*!< GPIO_T::INTSRC: INTSRC14 Mask          */
+
+#define GPIO_INTSRC_INTSRC15_Pos         (15)                                              /*!< GPIO_T::INTSRC: INTSRC15 Position      */
+#define GPIO_INTSRC_INTSRC15_Msk         (0x1ul << GPIO_INTSRC_INTSRC15_Pos)               /*!< GPIO_T::INTSRC: INTSRC15 Mask          */
+
+#define GPIO_SMTEN_SMTEN0_Pos            (0)                                               /*!< GPIO_T::SMTEN: SMTEN0 Position         */
+#define GPIO_SMTEN_SMTEN0_Msk            (0x1ul << GPIO_SMTEN_SMTEN0_Pos)                  /*!< GPIO_T::SMTEN: SMTEN0 Mask             */
+
+#define GPIO_SMTEN_SMTEN1_Pos            (1)                                               /*!< GPIO_T::SMTEN: SMTEN1 Position         */
+#define GPIO_SMTEN_SMTEN1_Msk            (0x1ul << GPIO_SMTEN_SMTEN1_Pos)                  /*!< GPIO_T::SMTEN: SMTEN1 Mask             */
+
+#define GPIO_SMTEN_SMTEN2_Pos            (2)                                               /*!< GPIO_T::SMTEN: SMTEN2 Position         */
+#define GPIO_SMTEN_SMTEN2_Msk            (0x1ul << GPIO_SMTEN_SMTEN2_Pos)                  /*!< GPIO_T::SMTEN: SMTEN2 Mask             */
+
+#define GPIO_SMTEN_SMTEN3_Pos            (3)                                               /*!< GPIO_T::SMTEN: SMTEN3 Position         */
+#define GPIO_SMTEN_SMTEN3_Msk            (0x1ul << GPIO_SMTEN_SMTEN3_Pos)                  /*!< GPIO_T::SMTEN: SMTEN3 Mask             */
+
+#define GPIO_SMTEN_SMTEN4_Pos            (4)                                               /*!< GPIO_T::SMTEN: SMTEN4 Position         */
+#define GPIO_SMTEN_SMTEN4_Msk            (0x1ul << GPIO_SMTEN_SMTEN4_Pos)                  /*!< GPIO_T::SMTEN: SMTEN4 Mask             */
+
+#define GPIO_SMTEN_SMTEN5_Pos            (5)                                               /*!< GPIO_T::SMTEN: SMTEN5 Position         */
+#define GPIO_SMTEN_SMTEN5_Msk            (0x1ul << GPIO_SMTEN_SMTEN5_Pos)                  /*!< GPIO_T::SMTEN: SMTEN5 Mask             */
+
+#define GPIO_SMTEN_SMTEN6_Pos            (6)                                               /*!< GPIO_T::SMTEN: SMTEN6 Position         */
+#define GPIO_SMTEN_SMTEN6_Msk            (0x1ul << GPIO_SMTEN_SMTEN6_Pos)                  /*!< GPIO_T::SMTEN: SMTEN6 Mask             */
+
+#define GPIO_SMTEN_SMTEN7_Pos            (7)                                               /*!< GPIO_T::SMTEN: SMTEN7 Position         */
+#define GPIO_SMTEN_SMTEN7_Msk            (0x1ul << GPIO_SMTEN_SMTEN7_Pos)                  /*!< GPIO_T::SMTEN: SMTEN7 Mask             */
+
+#define GPIO_SMTEN_SMTEN8_Pos            (8)                                               /*!< GPIO_T::SMTEN: SMTEN8 Position         */
+#define GPIO_SMTEN_SMTEN8_Msk            (0x1ul << GPIO_SMTEN_SMTEN8_Pos)                  /*!< GPIO_T::SMTEN: SMTEN8 Mask             */
+
+#define GPIO_SMTEN_SMTEN9_Pos            (9)                                               /*!< GPIO_T::SMTEN: SMTEN9 Position         */
+#define GPIO_SMTEN_SMTEN9_Msk            (0x1ul << GPIO_SMTEN_SMTEN9_Pos)                  /*!< GPIO_T::SMTEN: SMTEN9 Mask             */
+
+#define GPIO_SMTEN_SMTEN10_Pos           (10)                                              /*!< GPIO_T::SMTEN: SMTEN10 Position        */
+#define GPIO_SMTEN_SMTEN10_Msk           (0x1ul << GPIO_SMTEN_SMTEN10_Pos)                 /*!< GPIO_T::SMTEN: SMTEN10 Mask            */
+
+#define GPIO_SMTEN_SMTEN11_Pos           (11)                                              /*!< GPIO_T::SMTEN: SMTEN11 Position        */
+#define GPIO_SMTEN_SMTEN11_Msk           (0x1ul << GPIO_SMTEN_SMTEN11_Pos)                 /*!< GPIO_T::SMTEN: SMTEN11 Mask            */
+
+#define GPIO_SMTEN_SMTEN12_Pos           (12)                                              /*!< GPIO_T::SMTEN: SMTEN12 Position        */
+#define GPIO_SMTEN_SMTEN12_Msk           (0x1ul << GPIO_SMTEN_SMTEN12_Pos)                 /*!< GPIO_T::SMTEN: SMTEN12 Mask            */
+
+#define GPIO_SMTEN_SMTEN13_Pos           (13)                                              /*!< GPIO_T::SMTEN: SMTEN13 Position        */
+#define GPIO_SMTEN_SMTEN13_Msk           (0x1ul << GPIO_SMTEN_SMTEN13_Pos)                 /*!< GPIO_T::SMTEN: SMTEN13 Mask            */
+
+#define GPIO_SMTEN_SMTEN14_Pos           (14)                                              /*!< GPIO_T::SMTEN: SMTEN14 Position        */
+#define GPIO_SMTEN_SMTEN14_Msk           (0x1ul << GPIO_SMTEN_SMTEN14_Pos)                 /*!< GPIO_T::SMTEN: SMTEN14 Mask            */
+
+#define GPIO_SMTEN_SMTEN15_Pos           (15)                                              /*!< GPIO_T::SMTEN: SMTEN15 Position        */
+#define GPIO_SMTEN_SMTEN15_Msk           (0x1ul << GPIO_SMTEN_SMTEN15_Pos)                 /*!< GPIO_T::SMTEN: SMTEN15 Mask            */
+
+#define GPIO_SLEWCTL_HSREN0_Pos          (0)                                               /*!< GPIO_T::SLEWCTL: HSREN0 Position       */
+#define GPIO_SLEWCTL_HSREN0_Msk          (0x1ul << GPIO_SLEWCTL_HSREN0_Pos)                /*!< GPIO_T::SLEWCTL: HSREN0 Mask           */
+
+#define GPIO_SLEWCTL_HSREN1_Pos          (1)                                               /*!< GPIO_T::SLEWCTL: HSREN1 Position       */
+#define GPIO_SLEWCTL_HSREN1_Msk          (0x1ul << GPIO_SLEWCTL_HSREN1_Pos)                /*!< GPIO_T::SLEWCTL: HSREN1 Mask           */
+
+#define GPIO_SLEWCTL_HSREN2_Pos          (2)                                               /*!< GPIO_T::SLEWCTL: HSREN2 Position       */
+#define GPIO_SLEWCTL_HSREN2_Msk          (0x1ul << GPIO_SLEWCTL_HSREN2_Pos)                /*!< GPIO_T::SLEWCTL: HSREN2 Mask           */
+
+#define GPIO_SLEWCTL_HSREN3_Pos          (3)                                               /*!< GPIO_T::SLEWCTL: HSREN3 Position       */
+#define GPIO_SLEWCTL_HSREN3_Msk          (0x1ul << GPIO_SLEWCTL_HSREN3_Pos)                /*!< GPIO_T::SLEWCTL: HSREN3 Mask           */
+
+#define GPIO_SLEWCTL_HSREN4_Pos          (4)                                               /*!< GPIO_T::SLEWCTL: HSREN4 Position       */
+#define GPIO_SLEWCTL_HSREN4_Msk          (0x1ul << GPIO_SLEWCTL_HSREN4_Pos)                /*!< GPIO_T::SLEWCTL: HSREN4 Mask           */
+
+#define GPIO_SLEWCTL_HSREN5_Pos          (5)                                               /*!< GPIO_T::SLEWCTL: HSREN5 Position       */
+#define GPIO_SLEWCTL_HSREN5_Msk          (0x1ul << GPIO_SLEWCTL_HSREN5_Pos)                /*!< GPIO_T::SLEWCTL: HSREN5 Mask           */
+
+#define GPIO_SLEWCTL_HSREN6_Pos          (6)                                               /*!< GPIO_T::SLEWCTL: HSREN6 Position       */
+#define GPIO_SLEWCTL_HSREN6_Msk          (0x1ul << GPIO_SLEWCTL_HSREN6_Pos)                /*!< GPIO_T::SLEWCTL: HSREN6 Mask           */
+
+#define GPIO_SLEWCTL_HSREN7_Pos          (7)                                               /*!< GPIO_T::SLEWCTL: HSREN7 Position       */
+#define GPIO_SLEWCTL_HSREN7_Msk          (0x1ul << GPIO_SLEWCTL_HSREN7_Pos)                /*!< GPIO_T::SLEWCTL: HSREN7 Mask           */
+
+#define GPIO_SLEWCTL_HSREN8_Pos          (8)                                               /*!< GPIO_T::SLEWCTL: HSREN8 Position       */
+#define GPIO_SLEWCTL_HSREN8_Msk          (0x1ul << GPIO_SLEWCTL_HSREN8_Pos)                /*!< GPIO_T::SLEWCTL: HSREN8 Mask           */
+
+#define GPIO_SLEWCTL_HSREN9_Pos          (9)                                               /*!< GPIO_T::SLEWCTL: HSREN9 Position       */
+#define GPIO_SLEWCTL_HSREN9_Msk          (0x1ul << GPIO_SLEWCTL_HSREN9_Pos)                /*!< GPIO_T::SLEWCTL: HSREN9 Mask           */
+
+#define GPIO_SLEWCTL_HSREN10_Pos         (10)                                              /*!< GPIO_T::SLEWCTL: HSREN10 Position      */
+#define GPIO_SLEWCTL_HSREN10_Msk         (0x1ul << GPIO_SLEWCTL_HSREN10_Pos)               /*!< GPIO_T::SLEWCTL: HSREN10 Mask          */
+
+#define GPIO_SLEWCTL_HSREN11_Pos         (11)                                              /*!< GPIO_T::SLEWCTL: HSREN11 Position      */
+#define GPIO_SLEWCTL_HSREN11_Msk         (0x1ul << GPIO_SLEWCTL_HSREN11_Pos)               /*!< GPIO_T::SLEWCTL: HSREN11 Mask          */
+
+#define GPIO_SLEWCTL_HSREN12_Pos         (12)                                              /*!< GPIO_T::SLEWCTL: HSREN12 Position      */
+#define GPIO_SLEWCTL_HSREN12_Msk         (0x1ul << GPIO_SLEWCTL_HSREN12_Pos)               /*!< GPIO_T::SLEWCTL: HSREN12 Mask          */
+
+#define GPIO_SLEWCTL_HSREN13_Pos         (13)                                              /*!< GPIO_T::SLEWCTL: HSREN13 Position      */
+#define GPIO_SLEWCTL_HSREN13_Msk         (0x1ul << GPIO_SLEWCTL_HSREN13_Pos)               /*!< GPIO_T::SLEWCTL: HSREN13 Mask          */
+
+#define GPIO_SLEWCTL_HSREN14_Pos         (14)                                              /*!< GPIO_T::SLEWCTL: HSREN14 Position      */
+#define GPIO_SLEWCTL_HSREN14_Msk         (0x1ul << GPIO_SLEWCTL_HSREN14_Pos)               /*!< GPIO_T::SLEWCTL: HSREN14 Mask          */
+
+#define GPIO_SLEWCTL_HSREN15_Pos         (15)                                              /*!< GPIO_T::SLEWCTL: HSREN15 Position      */
+#define GPIO_SLEWCTL_HSREN15_Msk         (0x1ul << GPIO_SLEWCTL_HSREN15_Pos)               /*!< GPIO_T::SLEWCTL: HSREN15 Mask          */
+
+#define GPIO_PUSEL_PUSEL0_Pos            (0)                                               /*!< GPIO_T::PUSEL: PUSEL0 Position         */
+#define GPIO_PUSEL_PUSEL0_Msk            (0x3ul << GPIO_PUSEL_PUSEL0_Pos)                  /*!< GPIO_T::PUSEL: PUSEL0 Mask             */
+
+#define GPIO_PUSEL_PUSEL1_Pos            (2)                                               /*!< GPIO_T::PUSEL: PUSEL1 Position         */
+#define GPIO_PUSEL_PUSEL1_Msk            (0x3ul << GPIO_PUSEL_PUSEL1_Pos)                  /*!< GPIO_T::PUSEL: PUSEL1 Mask             */
+
+#define GPIO_PUSEL_PUSEL2_Pos            (4)                                               /*!< GPIO_T::PUSEL: PUSEL2 Position         */
+#define GPIO_PUSEL_PUSEL2_Msk            (0x3ul << GPIO_PUSEL_PUSEL2_Pos)                  /*!< GPIO_T::PUSEL: PUSEL2 Mask             */
+
+#define GPIO_PUSEL_PUSEL3_Pos            (6)                                               /*!< GPIO_T::PUSEL: PUSEL3 Position         */
+#define GPIO_PUSEL_PUSEL3_Msk            (0x3ul << GPIO_PUSEL_PUSEL3_Pos)                  /*!< GPIO_T::PUSEL: PUSEL3 Mask             */
+
+#define GPIO_PUSEL_PUSEL4_Pos            (8)                                               /*!< GPIO_T::PUSEL: PUSEL4 Position         */
+#define GPIO_PUSEL_PUSEL4_Msk            (0x3ul << GPIO_PUSEL_PUSEL4_Pos)                  /*!< GPIO_T::PUSEL: PUSEL4 Mask             */
+
+#define GPIO_PUSEL_PUSEL5_Pos            (10)                                              /*!< GPIO_T::PUSEL: PUSEL5 Position         */
+#define GPIO_PUSEL_PUSEL5_Msk            (0x3ul << GPIO_PUSEL_PUSEL5_Pos)                  /*!< GPIO_T::PUSEL: PUSEL5 Mask             */
+
+#define GPIO_PUSEL_PUSEL6_Pos            (12)                                              /*!< GPIO_T::PUSEL: PUSEL6 Position         */
+#define GPIO_PUSEL_PUSEL6_Msk            (0x3ul << GPIO_PUSEL_PUSEL6_Pos)                  /*!< GPIO_T::PUSEL: PUSEL6 Mask             */
+
+#define GPIO_PUSEL_PUSEL7_Pos            (14)                                              /*!< GPIO_T::PUSEL: PUSEL7 Position         */
+#define GPIO_PUSEL_PUSEL7_Msk            (0x3ul << GPIO_PUSEL_PUSEL7_Pos)                  /*!< GPIO_T::PUSEL: PUSEL7 Mask             */
+
+#define GPIO_PUSEL_PUSEL8_Pos            (16)                                              /*!< GPIO_T::PUSEL: PUSEL8 Position         */
+#define GPIO_PUSEL_PUSEL8_Msk            (0x3ul << GPIO_PUSEL_PUSEL8_Pos)                  /*!< GPIO_T::PUSEL: PUSEL8 Mask             */
+
+#define GPIO_PUSEL_PUSEL9_Pos            (18)                                              /*!< GPIO_T::PUSEL: PUSEL9 Position         */
+#define GPIO_PUSEL_PUSEL9_Msk            (0x3ul << GPIO_PUSEL_PUSEL9_Pos)                  /*!< GPIO_T::PUSEL: PUSEL9 Mask             */
+
+#define GPIO_PUSEL_PUSEL10_Pos           (20)                                              /*!< GPIO_T::PUSEL: PUSEL10 Position        */
+#define GPIO_PUSEL_PUSEL10_Msk           (0x3ul << GPIO_PUSEL_PUSEL10_Pos)                 /*!< GPIO_T::PUSEL: PUSEL10 Mask            */
+
+#define GPIO_PUSEL_PUSEL11_Pos           (22)                                              /*!< GPIO_T::PUSEL: PUSEL11 Position        */
+#define GPIO_PUSEL_PUSEL11_Msk           (0x3ul << GPIO_PUSEL_PUSEL11_Pos)                 /*!< GPIO_T::PUSEL: PUSEL11 Mask            */
+
+#define GPIO_PUSEL_PUSEL12_Pos           (24)                                              /*!< GPIO_T::PUSEL: PUSEL12 Position        */
+#define GPIO_PUSEL_PUSEL12_Msk           (0x3ul << GPIO_PUSEL_PUSEL12_Pos)                 /*!< GPIO_T::PUSEL: PUSEL12 Mask            */
+
+#define GPIO_PUSEL_PUSEL13_Pos           (26)                                              /*!< GPIO_T::PUSEL: PUSEL13 Position        */
+#define GPIO_PUSEL_PUSEL13_Msk           (0x3ul << GPIO_PUSEL_PUSEL13_Pos)                 /*!< GPIO_T::PUSEL: PUSEL13 Mask            */
+
+#define GPIO_PUSEL_PUSEL14_Pos           (28)                                              /*!< GPIO_T::PUSEL: PUSEL14 Position        */
+#define GPIO_PUSEL_PUSEL14_Msk           (0x3ul << GPIO_PUSEL_PUSEL14_Pos)                 /*!< GPIO_T::PUSEL: PUSEL14 Mask            */
+
+#define GPIO_PUSEL_PUSEL15_Pos           (30)                                              /*!< GPIO_T::PUSEL: PUSEL15 Position        */
+#define GPIO_PUSEL_PUSEL15_Msk           (0x3ul << GPIO_PUSEL_PUSEL15_Pos)                 /*!< GPIO_T::PUSEL: PUSEL15 Mask            */
+
+#define GPIO_DBCTL_DBCLKSEL_Pos          (0)                                               /*!< GPIO_T::DBCTL: DBCLKSEL Position       */
+#define GPIO_DBCTL_DBCLKSEL_Msk          (0xful << GPIO_DBCTL_DBCLKSEL_Pos)                /*!< GPIO_T::DBCTL: DBCLKSEL Mask           */
+
+#define GPIO_DBCTL_DBCLKSRC_Pos          (4)                                               /*!< GPIO_T::DBCTL: DBCLKSRC Position       */
+#define GPIO_DBCTL_DBCLKSRC_Msk          (0x1ul << GPIO_DBCTL_DBCLKSRC_Pos)                /*!< GPIO_T::DBCTL: DBCLKSRC Mask           */
+
+#define GPIO_DBCTL_ICLKON_Pos            (5)                                               /*!< GPIO_T::DBCTL: ICLKON Position         */
+#define GPIO_DBCTL_ICLKON_Msk            (0x1ul << GPIO_DBCTL_ICLKON_Pos)                  /*!< GPIO_T::DBCTL: ICLKON Mask             */
+
+
+/**@}*/ /* GPIO_CONST */
+/**@}*/ /* end of GPIO register group */
+/**@}*/ /* end of REGISTER group */
+
+
+#endif /* __GPIO_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/hdiv_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/hdiv_reg.h
new file mode 100644
index 0000000000..3ed76967cf
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/hdiv_reg.h
@@ -0,0 +1,114 @@
+/**************************************************************************//**
+ * @file     hdiv_reg.h
+ * @version  V1.00
+ * @brief    HDIV register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __HDIV_REG_H__
+#define __HDIV_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+/*---------------------- Hardware Divider --------------------------------*/
+/**
+    @addtogroup HDIV Hardware Divider(HDIV)
+    Memory Mapped Structure for HDIV Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var HDIV_T::DIVIDEND
+     * Offset: 0x00  Dividend Source Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DIVIDEND  |Dividend Source
+     * |        |          |This register is given the dividend of divider before calculation starting.
+     * @var HDIV_T::DIVISOR
+     * Offset: 0x04  Divisor Source Resister
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |DIVISOR   |Divisor Source
+     * |        |          |This register is given the divisor of divider before calculation starts.
+     * |        |          |Note: When this register is written, hardware divider will start calculate.
+     * @var HDIV_T::DIVQUO
+     * Offset: 0x08  Quotient Result Resister
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |QUOTIENT  |Quotient Result
+     * |        |          |This register holds the quotient result of divider after calculation complete.
+     * @var HDIV_T::DIVREM
+     * Offset: 0x0C  Remainder Result Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |REMAINDER |Remainder Result
+     * |        |          |The remainder of hardware divider is 16-bit sign integer (REMAINDER[15:0]), which holds the remainder result of divider after calculation complete.
+     * |        |          |The remainder of hardware divider with sign extension (REMAINDER[31:16]) to 32-bit integer.
+     * |        |          |This register holds the remainder result of divider after calculation complete.
+     * @var HDIV_T::DIVSTS
+     * Offset: 0x10  Divider Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |FINISH    |Division Finish Flag
+     * |        |          |0 = Under Calculation.
+     * |        |          |1 = Calculation finished.
+     * |        |          |The flag will become low when the divider is in calculation.
+     * |        |          |The flag will go back to high once the calculation finished.
+     * |[1]     |DIV0      |Divisor Zero Warning
+     * |        |          |0 = The divisor is not 0.
+     * |        |          |1 = The divisor is 0.
+     * |        |          |Note: The DIV0 flag is used to indicate divide-by-zero situation and updated whenever DIVISOR is written
+     * |        |          |This register is read only.
+     */
+    __IO uint32_t DIVIDEND;              /*!< [0x0000] Dividend Source Register                                         */
+    __IO uint32_t DIVISOR;               /*!< [0x0004] Divisor Source Resister                                          */
+    __IO uint32_t DIVQUO;                /*!< [0x0008] Quotient Result Resister                                         */
+    __IO uint32_t DIVREM;                /*!< [0x000c] Remainder Result Register                                        */
+    __I  uint32_t DIVSTS;                /*!< [0x0010] Divider Status Register                                          */
+
+} HDIV_T;
+
+/**
+    @addtogroup HDIV_CONST HDIV Bit Field Definition
+    Constant Definitions for HDIV Controller
+  @{
+*/
+
+#define HDIV_DIVIDEND_DIVIDEND_Pos       (0)                                               /*!< HDIV_T::DIVIDEND: DIVIDEND Position    */
+#define HDIV_DIVIDEND_DIVIDEND_Msk       (0xfffffffful << HDIV_DIVIDEND_DIVIDEND_Pos)      /*!< HDIV_T::DIVIDEND: DIVIDEND Mask        */
+
+#define HDIV_DIVISOR_DIVISOR_Pos         (0)                                               /*!< HDIV_T::DIVISOR: DIVISOR Position      */
+#define HDIV_DIVISOR_DIVISOR_Msk         (0xfffful << HDIV_DIVISOR_DIVISOR_Pos)            /*!< HDIV_T::DIVISOR: DIVISOR Mask          */
+
+#define HDIV_DIVQUO_QUOTIENT_Pos         (0)                                               /*!< HDIV_T::DIVQUO: QUOTIENT Position      */
+#define HDIV_DIVQUO_QUOTIENT_Msk         (0xfffffffful << HDIV_DIVQUO_QUOTIENT_Pos)        /*!< HDIV_T::DIVQUO: QUOTIENT Mask          */
+
+#define HDIV_DIVREM_REMAINDER_Pos        (0)                                               /*!< HDIV_T::DIVREM: REMAINDER Position     */
+#define HDIV_DIVREM_REMAINDER_Msk        (0xfffffffful << HDIV_DIVREM_REMAINDER_Pos)       /*!< HDIV_T::DIVREM: REMAINDER Mask         */
+
+#define HDIV_DIVSTS_FINISH_Pos           (0)                                               /*!< HDIV_T::DIVSTS: FINISH Position        */
+#define HDIV_DIVSTS_FINISH_Msk           (0x1ul << HDIV_DIVSTS_FINISH_Pos)                 /*!< HDIV_T::DIVSTS: FINISH Mask            */
+
+#define HDIV_DIVSTS_DIV0_Pos             (1)                                               /*!< HDIV_T::DIVSTS: DIV0 Position          */
+#define HDIV_DIVSTS_DIV0_Msk             (0x1ul << HDIV_DIVSTS_DIV0_Pos)                   /*!< HDIV_T::DIVSTS: DIV0 Mask              */
+
+/**@}*/ /* HDIV_CONST */
+/**@}*/ /* end of HDIV register group */
+/**@}*/ /* end of REGISTER group */
+
+
+#endif /* __HDIV_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/i2c_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/i2c_reg.h
new file mode 100644
index 0000000000..6435a0e308
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/i2c_reg.h
@@ -0,0 +1,717 @@
+/**************************************************************************//**
+ * @file     i2c_reg.h
+ * @version  V1.00
+ * @brief    I2C register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __I2C_REG_H__
+#define __I2C_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+/*---------------------- Inter-IC Bus Controller -------------------------*/
+/**
+    @addtogroup I2C Inter-IC Bus Controller(I2C)
+    Memory Mapped Structure for I2C Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var I2C_T::CTL0
+     * Offset: 0x00  I2C Control Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2]     |AA        |Assert Acknowledge Control
+     * |        |          |When AA =1 prior to address or data is received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter
+     * |        |          |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line
+     * |[3]     |SI        |I2C Interrupt Flag
+     * |        |          |When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware
+     * |        |          |If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested
+     * |        |          |SI must be cleared by software
+     * |        |          |Clear SI by writing 1 to this bit.
+     * |        |          |For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer.
+     * |[4]     |STO       |I2C STOP Control
+     * |        |          |In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected
+     * |        |          |This bit will be cleared by hardware automatically.
+     * |[5]     |STA       |I2C START Control
+     * |        |          |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
+     * |[6]     |I2CEN     |I2C Controller Enable Bit
+     * |        |          |Set to enable I2C serial function controller
+     * |        |          |When I2CEN=1 the I2C serial function enable
+     * |        |          |The multi-function pin function must set to SDA, and SCL of I2C function first.
+     * |        |          |0 = I2C controller Disabled.
+     * |        |          |1 = I2C controller Enabled.
+     * |[7]     |INTEN     |Enable Interrupt
+     * |        |          |0 = I2C interrupt Disabled.
+     * |        |          |1 = I2C interrupt Enabled.
+     * @var I2C_T::ADDR0
+     * Offset: 0x04  I2C Slave Address Register0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |GC        |General Call Function
+     * |        |          |0 = General Call Function Disabled.
+     * |        |          |1 = General Call Function Enabled.
+     * |[10:1]  |ADDR      |I2C Address
+     * |        |          |The content of this register is irrelevant when I2C is in Master mode
+     * |        |          |In the slave mode, the seven most significant bits must be loaded with the chip's own address
+     * |        |          |The I2C hardware will react if either of the address is matched.
+     * @var I2C_T::DAT
+     * Offset: 0x08  I2C Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |DAT       |I2C Data
+     * |        |          |Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
+     * @var I2C_T::STATUS0
+     * Offset: 0x0C  I2C Status Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |STATUS    |I2C Status
+     * |        |          |The three least significant bits are always 0
+     * |        |          |The five most significant bits contain the status code
+     * |        |          |There are 28 possible status codes
+     * |        |          |When the content of I2C_STATUS0 is F8H, no serial interrupt is requested
+     * |        |          |Others I2C_STATUS0 values correspond to defined I2C states
+     * |        |          |When each of these states is entered, a status interrupt is requested (SI = 1)
+     * |        |          |A valid status code is present in I2C_STATUS0 one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software
+     * |        |          |In addition, states 00H stands for a Bus Error
+     * |        |          |A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame
+     * |        |          |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.
+     * @var I2C_T::CLKDIV
+     * Offset: 0x10  I2C Clock Divided Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[9:0]   |DIVIDER   |I2C Clock Divided
+     * |        |          |Indicates the I2C clock rate: Data Baud Rate of I2C = (system clock) / (4x (I2C_CLKDIV+1)).
+     * |        |          |Note: The minimum value of I2C_CLKDIV is 4.
+     * @var I2C_T::TOCTL
+     * Offset: 0x14  I2C Time-out Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |TOIF      |Time-out Flag
+     * |        |          |This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.
+     * |        |          |Note: Software can write 1 to clear this bit.
+     * |[1]     |TOCDIV4   |Time-out Counter Input Clock Divided by 4
+     * |        |          |When Enabled, The time-out period is extend 4 times.
+     * |        |          |0 = Time-out period is extend 4 times Disabled.
+     * |        |          |1 = Time-out period is extend 4 times Enabled.
+     * |[2]     |TOCEN     |Time-out Counter Enable Bit
+     * |        |          |When Enabled, the 14-bit time-out counter will start counting when SI is clear
+     * |        |          |Setting flag SI to u20181' will reset counter and re-start up counting after SI is cleared.
+     * |        |          |0 = Time-out counter Disabled.
+     * |        |          |1 = Time-out counter Enabled.
+     * @var I2C_T::ADDR1
+     * Offset: 0x18  I2C Slave Address Register1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |GC        |General Call Function
+     * |        |          |0 = General Call Function Disabled.
+     * |        |          |1 = General Call Function Enabled.
+     * |[10:1]  |ADDR      |I2C Address
+     * |        |          |The content of this register is irrelevant when I2C is in Master mode
+     * |        |          |In the slave mode, the seven most significant bits must be loaded with the chip's own address
+     * |        |          |The I2C hardware will react if either of the address is matched.
+     * @var I2C_T::ADDR2
+     * Offset: 0x1C  I2C Slave Address Register2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |GC        |General Call Function
+     * |        |          |0 = General Call Function Disabled.
+     * |        |          |1 = General Call Function Enabled.
+     * |[10:1]  |ADDR      |I2C Address
+     * |        |          |The content of this register is irrelevant when I2C is in Master mode
+     * |        |          |In the slave mode, the seven most significant bits must be loaded with the chip's own address
+     * |        |          |The I2C hardware will react if either of the address is matched.
+     * @var I2C_T::ADDR3
+     * Offset: 0x20  I2C Slave Address Register3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |GC        |General Call Function
+     * |        |          |0 = General Call Function Disabled.
+     * |        |          |1 = General Call Function Enabled.
+     * |[10:1]  |ADDR      |I2C Address
+     * |        |          |The content of this register is irrelevant when I2C is in Master mode
+     * |        |          |In the slave mode, the seven most significant bits must be loaded with the chip's own address
+     * |        |          |The I2C hardware will react if either of the address is matched.
+     * @var I2C_T::ADDRMSK0
+     * Offset: 0x24  I2C Slave Address Mask Register0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[10:1]  |ADDRMSK   |I2C Address Mask
+     * |        |          |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
+     * |        |          |1 = Mask Enabled (the received corresponding address bit is don't care.).
+     * |        |          |I2C bus controllers support multiple address recognition with four address mask register
+     * |        |          |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
+     * |        |          |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
+     * |        |          |Note: The wake-up function can not use address mask.
+     * @var I2C_T::ADDRMSK1
+     * Offset: 0x28  I2C Slave Address Mask Register1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[10:1]  |ADDRMSK   |I2C Address Mask
+     * |        |          |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
+     * |        |          |1 = Mask Enabled (the received corresponding address bit is don't care.).
+     * |        |          |I2C bus controllers support multiple address recognition with four address mask register
+     * |        |          |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
+     * |        |          |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
+     * |        |          |Note: The wake-up function can not use address mask.
+     * @var I2C_T::ADDRMSK2
+     * Offset: 0x2C  I2C Slave Address Mask Register2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[10:1]  |ADDRMSK   |I2C Address Mask
+     * |        |          |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
+     * |        |          |1 = Mask Enabled (the received corresponding address bit is don't care.).
+     * |        |          |I2C bus controllers support multiple address recognition with four address mask register
+     * |        |          |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
+     * |        |          |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
+     * |        |          |Note: The wake-up function can not use address mask.
+     * @var I2C_T::ADDRMSK3
+     * Offset: 0x30  I2C Slave Address Mask Register3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[10:1]  |ADDRMSK   |I2C Address Mask
+     * |        |          |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
+     * |        |          |1 = Mask Enabled (the received corresponding address bit is don't care.).
+     * |        |          |I2C bus controllers support multiple address recognition with four address mask register
+     * |        |          |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
+     * |        |          |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
+     * |        |          |Note: The wake-up function can not use address mask.
+     * @var I2C_T::WKCTL
+     * Offset: 0x3C  I2C Wake-up Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WKEN      |I2C Wake-up Enable Bit
+     * |        |          |0 = I2C wake-up function Disabled.
+     * |        |          |1= I2C wake-up function Enabled.
+     * |[7]     |NHDBUSEN  |I2C No Hold BUS Enable Bit
+     * |        |          |0 = I2C don't hold bus after wake-up disable.
+     * |        |          |1= I2C don't hold bus after wake-up enable.
+     * |        |          |Note: I2C controller could response when WKIF event is not clear, it may cause error data transmitted or received
+     * |        |          |If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again.
+     * @var I2C_T::WKSTS
+     * Offset: 0x40  I2C Wake-up Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WKIF      |I2C Wake-up Flag
+     * |        |          |When chip is woken up from Power-down mode by I2C, this bit is set to 1
+     * |        |          |Software can write 1 to clear this bit.
+     * |[1]     |WKAKDONE  |Wakeup Address Frame Acknowledge Bit Done
+     * |        |          |0 = The ACK bit cycle of address match frame isn't done.
+     * |        |          |1 = The ACK bit cycle of address match frame is done in power-down.
+     * |        |          |Note: This bit can't release WKIF. Software can write 1 to clear this bit.
+     * |[2]     |WRSTSWK   |Read/Write Status Bit in Address Wakeup Frame
+     * |        |          |0 = Write command be record on the address match wakeup frame.
+     * |        |          |1 = Read command be record on the address match wakeup frame.
+     * |        |          |Note: This bit will be cleared when software can write 1 to WKAKDONE bit.
+     * @var I2C_T::CTL1
+     * Offset: 0x44  I2C Control Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |TXPDMAEN  |PDMA Transmit Channel Available
+     * |        |          |0 = Transmit PDMA function disable.
+     * |        |          |1 = Transmit PDMA function enable.
+     * |[1]     |RXPDMAEN  |PDMA Receive Channel Available
+     * |        |          |0 = Receive PDMA function disable.
+     * |        |          |1 = Receive PDMA function enable.
+     * |[2]     |PDMARST   |PDMA Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset the I2C request to PDMA. This bit will be cleared to 0 automatically.
+     * |[8]     |PDMASTR   |PDMA Stretch Bit
+     * |        |          |0 = I2C send STOP automatically after PDMA transfer done. (only master TX)
+     * |        |          |1 = I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared
+     * |        |          |(only master TX)
+     * |[9]     |ADDR10EN  |Address 10-bit Function Enable
+     * |        |          |0 = Address match 10-bit function is disabled.
+     * |        |          |1 = Address match 10-bit function is enabled.
+     * @var I2C_T::STATUS1
+     * Offset: 0x48  I2C Status Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ADMAT0    |I2C Address 0 Match Status Register
+     * |        |          |When address 0 is matched, hardware will inform which address used
+     * |        |          |This bit will set to 1, and software can write 1 to clear this bit.
+     * |[1]     |ADMAT1    |I2C Address 1 Match Status Register
+     * |        |          |When address 1 is matched, hardware will inform which address used
+     * |        |          |This bit will set to 1, and software can write 1 to clear this bit.
+     * |[2]     |ADMAT2    |I2C Address 2 Match Status Register
+     * |        |          |When address 2 is matched, hardware will inform which address used
+     * |        |          |This bit will set to 1, and software can write 1 to clear this bit.
+     * |[3]     |ADMAT3    |I2C Address 3 Match Status Register
+     * |        |          |When address 3 is matched, hardware will inform which address used
+     * |        |          |This bit will set to 1, and software can write 1 to clear this bit.
+     * |[8]     |ONBUSY    |On Bus Busy
+     * |        |          |Indicates that a communication is in progress on the bus
+     * |        |          |It is set by hardware when a START condition is detected
+     * |        |          |It is cleared by hardware when a STOP condition is detected.
+     * |        |          |0 = The bus is IDLE (both SCLK and SDA High).
+     * |        |          |1 = The bus is busy.
+     * |        |          |Note:This bit is read only.
+     * @var I2C_T::TMCTL
+     * Offset: 0x4C  I2C Timing Configure Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[8:0]   |STCTL     |Setup Time Configure Control Register
+     * |        |          |This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.
+     * |        |          |The delay setup time is numbers of peripheral clock = STCTL x PCLK.
+     * |        |          |Note: Setup time setting should not make SCL output less than three PCLKs.
+     * |[24:16] |HTCTL     |Hold Time Configure Control Register
+     * |        |          |This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode.
+     * |        |          |The delay hold time is numbers of peripheral clock = HTCTL x PCLK.
+     * @var I2C_T::BUSCTL
+     * Offset: 0x50  I2C Bus Management Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ACKMEN    |Acknowledge Control by Manual
+     * |        |          |In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit.
+     * |        |          |0 = Slave byte control Disabled.
+     * |        |          |1 = Slave byte control Enabled
+     * |        |          |The 9th bit can response the ACK or NACK according the received data by user
+     * |        |          |When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse.
+     * |        |          |Note: If the BMDEN =1 and this bit is enabled, the information of I2C_STATUS will be fixed as 0xF0 in slave receive condition.
+     * |[1]     |PECEN     |Packet Error Checking Calculation Enable Bit
+     * |        |          |0 = Packet Error Checking Calculation Disabled.
+     * |        |          |1 = Packet Error Checking Calculation Enabled.
+     * |        |          |Note: When I2C enter power down mode, the bit should be enabled after wake-up if needed PEC calculation.
+     * |[2]     |BMDEN     |Bus Management Device Default Address Enable Bit
+     * |        |          |0 = Device default address Disable
+     * |        |          |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed
+     * |        |          |1 = Device default address Enabled
+     * |        |          |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed.
+     * |[3]     |BMHEN     |Bus Management Host Enable Bit
+     * |        |          |0 = Host function Disabled.
+     * |        |          |1 = Host function Enabled.
+     * |[4]     |ALERTEN   |Bus Management Alert Enable Bit
+     * |        |          |Device Mode (BMHEN =0).
+     * |        |          |0 = Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled.
+     * |        |          |1 = Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled.
+     * |        |          |Host Mode (BMHEN =1).
+     * |        |          |0 = BM_ALERT pin not supported.
+     * |        |          |1 = BM_ALERT pin supported.
+     * |[5]     |SCTLOSTS  |Suspend/Control Data Output Status
+     * |        |          |0 = The output of SUSCON pin is low.
+     * |        |          |1 = The output of SUSCON pin is high.
+     * |[6]     |SCTLOEN   |Suspend or Control Pin Output Enable Bit
+     * |        |          |0 = The SUSCON pin in input.
+     * |        |          |1 = The output enable is active on the SUSCON pin.
+     * |[7]     |BUSEN     |BUS Enable Bit
+     * |        |          |0 = The system management function is Disabled.
+     * |        |          |1 = The system management function is Enable.
+     * |        |          |Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition.
+     * |[8]     |PECTXEN   |Packet Error Checking Byte Transmission/Reception
+     * |        |          |0 = No PEC transfer.
+     * |        |          |1 = PEC transmission is requested.
+     * |        |          |Note: 1.This bit has no effect in slave mode when ACKMEN =0.
+     * |[9]     |TIDLE     |Timer Check in Idle State
+     * |        |          |The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle
+     * |        |          |This bit is used to define which condition is enabled.
+     * |        |          |0 = The BUSTOUT is used to calculate the clock low period in bus active.
+     * |        |          |1 = The BUSTOUT is used to calculate the IDLE period in bus Idle.
+     * |        |          |Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state.
+     * |[10]    |PECCLR    |PEC Clear at Repeat Start
+     * |        |          |The calculation of PEC starts when PECEN is set to 1 and it is clear when the STA or STO bit is detected
+     * |        |          |This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation.
+     * |        |          |0 = The PEC calculation is cleared by Repeat Start function is Disabled.
+     * |        |          |1 = The PEC calculation is cleared by Repeat Start function is Enabled.
+     * |[11]    |ACKM9SI   |Acknowledge Manual Enable Extra SI Interrupt
+     * |        |          |0 = There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1.
+     * |        |          |1 = There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1.
+     * |[12]    |BCDIEN    |Packet Error Checking Byte Count Done Interrupt Enable Bit
+     * |        |          |0 = Indicates the byte count done interrupt is Disabled.
+     * |        |          |1 = Indicates the byte count done interrupt is Enabled.
+     * |        |          |Note: This bit is used in PECEN =1.
+     * |[13]    |PECDIEN   |Packet Error Checking Byte Transfer Done Interrupt Enable Bit
+     * |        |          |0 = Indicates the PEC transfer done interrupt is Disabled.
+     * |        |          |1 = Indicates the PEC transfer done interrupt is Enabled.
+     * |        |          |Note: This bit is used in PECEN =1.
+     * @var I2C_T::BUSTCTL
+     * Offset: 0x54  I2C Bus Management Timer Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BUSTOEN   |Bus Time Out Enable Bit
+     * |        |          |0 = Indicates the bus clock low time-out detection is Disabled.
+     * |        |          |1 = Indicates the bus clock low time-out detection is Enabled (bus clock is low for more than Time-out (in BIDLE=0) or high more than Time-out(in BIDLE =1)
+     * |[1]     |CLKTOEN   |Cumulative Clock Low Time Out Enable Bit
+     * |        |          |0 = Indicates the cumulative clock low time-out detection is Disabled.
+     * |        |          |1 = Indicates the cumulative clock low time-out detection is Enabled.
+     * |        |          |For Master, it calculates the period from START to ACK
+     * |        |          |For Slave, it calculates the period from START to STOP
+     * |[2]     |BUSTOIEN  |Time-out Interrupt Enable Bit
+     * |        |          |BUSY =1.
+     * |        |          |0 = Indicates the SCLK low time-out interrupt is Disabled.
+     * |        |          |1 = Indicates the SCLK low time-out interrupt is Enabled.
+     * |        |          |BUSY =0.
+     * |        |          |0 = Indicates the bus IDLE time-out interrupt is Disabled.
+     * |        |          |1 = Indicates the bus IDLE time-out interrupt is Enabled.
+     * |[3]     |CLKTOIEN  |Extended Clock Time Out Interrupt Enable Bit
+     * |        |          |0 = Indicates the clock time out interrupt is Disabled.
+     * |        |          |1 = Indicates the clock time out interrupt is Enabled.
+     * |[4]     |TORSTEN   |Time Out Reset Enable Bit
+     * |        |          |0 = Indicates the I2C state machine reset is Disable.
+     * |        |          |1 = Indicates the I2C state machine reset is Enable. (The clock and data bus will be released to high)
+     * @var I2C_T::BUSSTS
+     * Offset: 0x58  I2C Bus Management Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BUSY      |Bus Busy
+     * |        |          |Indicates that a communication is in progress on the bus
+     * |        |          |It is set by hardware when a START condition is detected
+     * |        |          |It is cleared by hardware when a STOP condition is detected
+     * |        |          |0 = The bus is IDLE (both SCLK and SDA High).
+     * |        |          |1 = The bus is busy.
+     * |[1]     |BCDONE    |Byte Count Transmission/Receive Done
+     * |        |          |0 = Indicates the byte count transmission/ receive is not finished when the PECEN is set.
+     * |        |          |1 = Indicates the byte count transmission/ receive is finished when the PECEN is set.
+     * |        |          |Note: Software can write 1 to clear this bit.
+     * |[2]     |PECERR    |PEC Error in Reception
+     * |        |          |0 = Indicates the PEC value equal the received PEC data packet.
+     * |        |          |1 = Indicates the PEC value doesn't match the receive PEC data packet.
+     * |        |          |Note: Software can write 1 to clear this bit.
+     * |[3]     |ALERT     |SMBus Alert Status
+     * |        |          |Device Mode (BMHEN =0).
+     * |        |          |0 = Indicates SMBALERT pin state is low.
+     * |        |          |1 = Indicates SMBALERT pin state is high.
+     * |        |          |Host Mode (BMHEN =1).
+     * |        |          |0 = No SMBALERT event.
+     * |        |          |1 = Indicates there is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1.
+     * |        |          |Note: 1
+     * |        |          |The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system
+     * |        |          |2
+     * |        |          |Software can write 1 to clear this bit.
+     * |[4]     |SCTLDIN   |Bus Suspend or Control Signal Input Status
+     * |        |          |0 = The input status of SUSCON pin is 0.
+     * |        |          |1 = The input status of SUSCON pin is 1.
+     * |[5]     |BUSTO     |Bus Time-out Status
+     * |        |          |0 = Indicates that there is no any time-out or external clock time-out.
+     * |        |          |1 = Indicates that a time-out or external clock time-out occurred.
+     * |        |          |In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred.
+     * |        |          |Note: Software can write 1 to clear this bit.
+     * |[6]     |CLKTO     |Clock Low Accumulate Time-out Status
+     * |        |          |0 = Indicates that the cumulative clock low is no any time-out.
+     * |        |          |1 = Indicates that the cumulative clock low time-out occurred.
+     * |        |          |Note: Software can write 1 to clear this bit.
+     * |[7]     |PECDONE   |PEC Byte Transmission/Receive Done
+     * |        |          |0 = Indicates the PEC transmission/ receive is not finished when the PECEN is set.
+     * |        |          |1 = Indicates the PEC transmission/ receive is finished when the PECEN is set.
+     * |        |          |Note: Software can write 1 to clear this bit.
+     * @var I2C_T::PKTSIZE
+     * Offset: 0x5C  I2C Packet Error Checking Byte Number Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[8:0]   |PLDSIZE   |Transfer Byte Number
+     * |        |          |The transmission or receive byte number in one transaction when the PECEN is set
+     * |        |          |The maximum transaction or receive byte is 256 Bytes.
+     * |        |          |Notice: The byte number counting includes address, command code, and data frame.
+     * @var I2C_T::PKTCRC
+     * Offset: 0x60  I2C Packet Error Checking Byte Value Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |PECCRC    |Packet Error Checking Byte Value
+     * |        |          |This byte indicates the packet error checking content after transmission or receive byte count by using the C(x) = X8 + X2 + X + 1
+     * |        |          |It is read only.
+     * @var I2C_T::BUSTOUT
+     * Offset: 0x64  I2C Bus Management Timer Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |BUSTO     |Bus Management Time-out Value
+     * |        |          |Indicate the bus time-out value in bus is IDLE or SCLK low.
+     * |        |          |Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set.
+     * @var I2C_T::CLKTOUT
+     * Offset: 0x68  I2C Bus Management Clock Low Timer Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |CLKTO     |Bus Clock Low Timer
+     * |        |          |The field is used to configure the cumulative clock extension time-out.
+     * |        |          |Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set.
+     */
+    __IO uint32_t CTL0;                  /*!< [0x0000] I2C Control Register 0                                           */
+    __IO uint32_t ADDR0;                 /*!< [0x0004] I2C Slave Address Register0                                      */
+    __IO uint32_t DAT;                   /*!< [0x0008] I2C Data Register                                                */
+    __I  uint32_t STATUS0;               /*!< [0x000c] I2C Status Register 0                                            */
+    __IO uint32_t CLKDIV;                /*!< [0x0010] I2C Clock Divided Register                                       */
+    __IO uint32_t TOCTL;                 /*!< [0x0014] I2C Time-out Control Register                                    */
+    __IO uint32_t ADDR1;                 /*!< [0x0018] I2C Slave Address Register1                                      */
+    __IO uint32_t ADDR2;                 /*!< [0x001c] I2C Slave Address Register2                                      */
+    __IO uint32_t ADDR3;                 /*!< [0x0020] I2C Slave Address Register3                                      */
+    __IO uint32_t ADDRMSK0;              /*!< [0x0024] I2C Slave Address Mask Register0                                 */
+    __IO uint32_t ADDRMSK1;              /*!< [0x0028] I2C Slave Address Mask Register1                                 */
+    __IO uint32_t ADDRMSK2;              /*!< [0x002c] I2C Slave Address Mask Register2                                 */
+    __IO uint32_t ADDRMSK3;              /*!< [0x0030] I2C Slave Address Mask Register3                                 */
+    __I  uint32_t RESERVE0[2];
+    __IO uint32_t WKCTL;                 /*!< [0x003c] I2C Wake-up Control Register                                     */
+    __IO uint32_t WKSTS;                 /*!< [0x0040] I2C Wake-up Status Register                                      */
+    __IO uint32_t CTL1;                  /*!< [0x0044] I2C Control Register 1                                           */
+    __IO uint32_t STATUS1;               /*!< [0x0048] I2C Status Register 1                                            */
+    __IO uint32_t TMCTL;                 /*!< [0x004c] I2C Timing Configure Control Register                            */
+    __IO uint32_t BUSCTL;                /*!< [0x0050] I2C Bus Management Control Register                              */
+    __IO uint32_t BUSTCTL;               /*!< [0x0054] I2C Bus Management Timer Control Register                        */
+    __IO uint32_t BUSSTS;                /*!< [0x0058] I2C Bus Management Status Register                               */
+    __IO uint32_t PKTSIZE;               /*!< [0x005c] I2C Packet Error Checking Byte Number Register                   */
+    __I  uint32_t PKTCRC;                /*!< [0x0060] I2C Packet Error Checking Byte Value Register                    */
+    __IO uint32_t BUSTOUT;               /*!< [0x0064] I2C Bus Management Timer Register                                */
+    __IO uint32_t CLKTOUT;               /*!< [0x0068] I2C Bus Management Clock Low Timer Register                      */
+
+} I2C_T;
+
+/**
+    @addtogroup I2C_CONST I2C Bit Field Definition
+    Constant Definitions for I2C Controller
+  @{
+*/
+
+#define I2C_CTL0_AA_Pos                  (2)                                               /*!< I2C_T::CTL0: AA Position               */
+#define I2C_CTL0_AA_Msk                  (0x1ul << I2C_CTL0_AA_Pos)                        /*!< I2C_T::CTL0: AA Mask                   */
+
+#define I2C_CTL0_SI_Pos                  (3)                                               /*!< I2C_T::CTL0: SI Position               */
+#define I2C_CTL0_SI_Msk                  (0x1ul << I2C_CTL0_SI_Pos)                        /*!< I2C_T::CTL0: SI Mask                   */
+
+#define I2C_CTL0_STO_Pos                 (4)                                               /*!< I2C_T::CTL0: STO Position              */
+#define I2C_CTL0_STO_Msk                 (0x1ul << I2C_CTL0_STO_Pos)                       /*!< I2C_T::CTL0: STO Mask                  */
+
+#define I2C_CTL0_STA_Pos                 (5)                                               /*!< I2C_T::CTL0: STA Position              */
+#define I2C_CTL0_STA_Msk                 (0x1ul << I2C_CTL0_STA_Pos)                       /*!< I2C_T::CTL0: STA Mask                  */
+
+#define I2C_CTL0_I2CEN_Pos               (6)                                               /*!< I2C_T::CTL0: I2CEN Position            */
+#define I2C_CTL0_I2CEN_Msk               (0x1ul << I2C_CTL0_I2CEN_Pos)                     /*!< I2C_T::CTL0: I2CEN Mask                */
+
+#define I2C_CTL0_INTEN_Pos               (7)                                               /*!< I2C_T::CTL0: INTEN Position            */
+#define I2C_CTL0_INTEN_Msk               (0x1ul << I2C_CTL0_INTEN_Pos)                     /*!< I2C_T::CTL0: INTEN Mask                */
+
+#define I2C_ADDR0_GC_Pos                 (0)                                               /*!< I2C_T::ADDR0: GC Position              */
+#define I2C_ADDR0_GC_Msk                 (0x1ul << I2C_ADDR0_GC_Pos)                       /*!< I2C_T::ADDR0: GC Mask                  */
+
+#define I2C_ADDR0_ADDR_Pos               (1)                                               /*!< I2C_T::ADDR0: ADDR Position            */
+#define I2C_ADDR0_ADDR_Msk               (0x3fful << I2C_ADDR0_ADDR_Pos)                   /*!< I2C_T::ADDR0: ADDR Mask                */
+
+#define I2C_DAT_DAT_Pos                  (0)                                               /*!< I2C_T::DAT: DAT Position               */
+#define I2C_DAT_DAT_Msk                  (0xfful << I2C_DAT_DAT_Pos)                       /*!< I2C_T::DAT: DAT Mask                   */
+
+#define I2C_STATUS0_STATUS_Pos           (0)                                               /*!< I2C_T::STATUS0: STATUS Position        */
+#define I2C_STATUS0_STATUS_Msk           (0xfful << I2C_STATUS0_STATUS_Pos)                /*!< I2C_T::STATUS0: STATUS Mask            */
+
+#define I2C_CLKDIV_DIVIDER_Pos           (0)                                               /*!< I2C_T::CLKDIV: DIVIDER Position        */
+#define I2C_CLKDIV_DIVIDER_Msk           (0x3fful << I2C_CLKDIV_DIVIDER_Pos)               /*!< I2C_T::CLKDIV: DIVIDER Mask            */
+
+#define I2C_TOCTL_TOIF_Pos               (0)                                               /*!< I2C_T::TOCTL: TOIF Position            */
+#define I2C_TOCTL_TOIF_Msk               (0x1ul << I2C_TOCTL_TOIF_Pos)                     /*!< I2C_T::TOCTL: TOIF Mask                */
+
+#define I2C_TOCTL_TOCDIV4_Pos            (1)                                               /*!< I2C_T::TOCTL: TOCDIV4 Position         */
+#define I2C_TOCTL_TOCDIV4_Msk            (0x1ul << I2C_TOCTL_TOCDIV4_Pos)                  /*!< I2C_T::TOCTL: TOCDIV4 Mask             */
+
+#define I2C_TOCTL_TOCEN_Pos              (2)                                               /*!< I2C_T::TOCTL: TOCEN Position           */
+#define I2C_TOCTL_TOCEN_Msk              (0x1ul << I2C_TOCTL_TOCEN_Pos)                    /*!< I2C_T::TOCTL: TOCEN Mask               */
+
+#define I2C_ADDR1_GC_Pos                 (0)                                               /*!< I2C_T::ADDR1: GC Position              */
+#define I2C_ADDR1_GC_Msk                 (0x1ul << I2C_ADDR1_GC_Pos)                       /*!< I2C_T::ADDR1: GC Mask                  */
+
+#define I2C_ADDR1_ADDR_Pos               (1)                                               /*!< I2C_T::ADDR1: ADDR Position            */
+#define I2C_ADDR1_ADDR_Msk               (0x3fful << I2C_ADDR1_ADDR_Pos)                   /*!< I2C_T::ADDR1: ADDR Mask                */
+
+#define I2C_ADDR2_GC_Pos                 (0)                                               /*!< I2C_T::ADDR2: GC Position              */
+#define I2C_ADDR2_GC_Msk                 (0x1ul << I2C_ADDR2_GC_Pos)                       /*!< I2C_T::ADDR2: GC Mask                  */
+
+#define I2C_ADDR2_ADDR_Pos               (1)                                               /*!< I2C_T::ADDR2: ADDR Position            */
+#define I2C_ADDR2_ADDR_Msk               (0x3fful << I2C_ADDR2_ADDR_Pos)                   /*!< I2C_T::ADDR2: ADDR Mask                */
+
+#define I2C_ADDR3_GC_Pos                 (0)                                               /*!< I2C_T::ADDR3: GC Position              */
+#define I2C_ADDR3_GC_Msk                 (0x1ul << I2C_ADDR3_GC_Pos)                       /*!< I2C_T::ADDR3: GC Mask                  */
+
+#define I2C_ADDR3_ADDR_Pos               (1)                                               /*!< I2C_T::ADDR3: ADDR Position            */
+#define I2C_ADDR3_ADDR_Msk               (0x3fful << I2C_ADDR3_ADDR_Pos)                   /*!< I2C_T::ADDR3: ADDR Mask                */
+
+#define I2C_ADDRMSK0_ADDRMSK_Pos         (1)                                               /*!< I2C_T::ADDRMSK0: ADDRMSK Position      */
+#define I2C_ADDRMSK0_ADDRMSK_Msk         (0x3fful << I2C_ADDRMSK0_ADDRMSK_Pos)             /*!< I2C_T::ADDRMSK0: ADDRMSK Mask          */
+
+#define I2C_ADDRMSK1_ADDRMSK_Pos         (1)                                               /*!< I2C_T::ADDRMSK1: ADDRMSK Position      */
+#define I2C_ADDRMSK1_ADDRMSK_Msk         (0x3fful << I2C_ADDRMSK1_ADDRMSK_Pos)             /*!< I2C_T::ADDRMSK1: ADDRMSK Mask          */
+
+#define I2C_ADDRMSK2_ADDRMSK_Pos         (1)                                               /*!< I2C_T::ADDRMSK2: ADDRMSK Position      */
+#define I2C_ADDRMSK2_ADDRMSK_Msk         (0x3fful << I2C_ADDRMSK2_ADDRMSK_Pos)             /*!< I2C_T::ADDRMSK2: ADDRMSK Mask          */
+
+#define I2C_ADDRMSK3_ADDRMSK_Pos         (1)                                               /*!< I2C_T::ADDRMSK3: ADDRMSK Position      */
+#define I2C_ADDRMSK3_ADDRMSK_Msk         (0x3fful << I2C_ADDRMSK3_ADDRMSK_Pos)             /*!< I2C_T::ADDRMSK3: ADDRMSK Mask          */
+
+#define I2C_WKCTL_WKEN_Pos               (0)                                               /*!< I2C_T::WKCTL: WKEN Position            */
+#define I2C_WKCTL_WKEN_Msk               (0x1ul << I2C_WKCTL_WKEN_Pos)                     /*!< I2C_T::WKCTL: WKEN Mask                */
+
+#define I2C_WKCTL_NHDBUSEN_Pos           (7)                                               /*!< I2C_T::WKCTL: NHDBUSEN Position        */
+#define I2C_WKCTL_NHDBUSEN_Msk           (0x1ul << I2C_WKCTL_NHDBUSEN_Pos)                 /*!< I2C_T::WKCTL: NHDBUSEN Mask            */
+
+#define I2C_WKSTS_WKIF_Pos               (0)                                               /*!< I2C_T::WKSTS: WKIF Position            */
+#define I2C_WKSTS_WKIF_Msk               (0x1ul << I2C_WKSTS_WKIF_Pos)                     /*!< I2C_T::WKSTS: WKIF Mask                */
+
+#define I2C_WKSTS_WKAKDONE_Pos           (1)                                               /*!< I2C_T::WKSTS: WKAKDONE Position        */
+#define I2C_WKSTS_WKAKDONE_Msk           (0x1ul << I2C_WKSTS_WKAKDONE_Pos)                 /*!< I2C_T::WKSTS: WKAKDONE Mask            */
+
+#define I2C_WKSTS_WRSTSWK_Pos            (2)                                               /*!< I2C_T::WKSTS: WRSTSWK Position         */
+#define I2C_WKSTS_WRSTSWK_Msk            (0x1ul << I2C_WKSTS_WRSTSWK_Pos)                  /*!< I2C_T::WKSTS: WRSTSWK Mask             */
+
+#define I2C_CTL1_TXPDMAEN_Pos            (0)                                               /*!< I2C_T::CTL1: TXPDMAEN Position         */
+#define I2C_CTL1_TXPDMAEN_Msk            (0x1ul << I2C_CTL1_TXPDMAEN_Pos)                  /*!< I2C_T::CTL1: TXPDMAEN Mask             */
+
+#define I2C_CTL1_RXPDMAEN_Pos            (1)                                               /*!< I2C_T::CTL1: RXPDMAEN Position         */
+#define I2C_CTL1_RXPDMAEN_Msk            (0x1ul << I2C_CTL1_RXPDMAEN_Pos)                  /*!< I2C_T::CTL1: RXPDMAEN Mask             */
+
+#define I2C_CTL1_PDMARST_Pos             (2)                                               /*!< I2C_T::CTL1: PDMARST Position          */
+#define I2C_CTL1_PDMARST_Msk             (0x1ul << I2C_CTL1_PDMARST_Pos)                   /*!< I2C_T::CTL1: PDMARST Mask              */
+
+#define I2C_CTL1_PDMASTR_Pos             (8)                                               /*!< I2C_T::CTL1: PDMASTR Position          */
+#define I2C_CTL1_PDMASTR_Msk             (0x1ul << I2C_CTL1_PDMASTR_Pos)                   /*!< I2C_T::CTL1: PDMASTR Mask              */
+
+#define I2C_CTL1_ADDR10EN_Pos            (9)                                               /*!< I2C_T::CTL1: ADDR10EN Position         */
+#define I2C_CTL1_ADDR10EN_Msk            (0x1ul << I2C_CTL1_ADDR10EN_Pos)                  /*!< I2C_T::CTL1: ADDR10EN Mask             */
+
+#define I2C_STATUS1_ADMAT0_Pos           (0)                                               /*!< I2C_T::STATUS1: ADMAT0 Position        */
+#define I2C_STATUS1_ADMAT0_Msk           (0x1ul << I2C_STATUS1_ADMAT0_Pos)                 /*!< I2C_T::STATUS1: ADMAT0 Mask            */
+
+#define I2C_STATUS1_ADMAT1_Pos           (1)                                               /*!< I2C_T::STATUS1: ADMAT1 Position        */
+#define I2C_STATUS1_ADMAT1_Msk           (0x1ul << I2C_STATUS1_ADMAT1_Pos)                 /*!< I2C_T::STATUS1: ADMAT1 Mask            */
+
+#define I2C_STATUS1_ADMAT2_Pos           (2)                                               /*!< I2C_T::STATUS1: ADMAT2 Position        */
+#define I2C_STATUS1_ADMAT2_Msk           (0x1ul << I2C_STATUS1_ADMAT2_Pos)                 /*!< I2C_T::STATUS1: ADMAT2 Mask            */
+
+#define I2C_STATUS1_ADMAT3_Pos           (3)                                               /*!< I2C_T::STATUS1: ADMAT3 Position        */
+#define I2C_STATUS1_ADMAT3_Msk           (0x1ul << I2C_STATUS1_ADMAT3_Pos)                 /*!< I2C_T::STATUS1: ADMAT3 Mask            */
+
+#define I2C_STATUS1_ONBUSY_Pos           (8)                                               /*!< I2C_T::STATUS1: ONBUSY Position        */
+#define I2C_STATUS1_ONBUSY_Msk           (0x1ul << I2C_STATUS1_ONBUSY_Pos)                 /*!< I2C_T::STATUS1: ONBUSY Mask            */
+
+#define I2C_TMCTL_STCTL_Pos              (0)                                               /*!< I2C_T::TMCTL: STCTL Position           */
+#define I2C_TMCTL_STCTL_Msk              (0x1fful << I2C_TMCTL_STCTL_Pos)                  /*!< I2C_T::TMCTL: STCTL Mask               */
+
+#define I2C_TMCTL_HTCTL_Pos              (16)                                              /*!< I2C_T::TMCTL: HTCTL Position           */
+#define I2C_TMCTL_HTCTL_Msk              (0x1fful << I2C_TMCTL_HTCTL_Pos)                  /*!< I2C_T::TMCTL: HTCTL Mask               */
+
+#define I2C_BUSCTL_ACKMEN_Pos            (0)                                               /*!< I2C_T::BUSCTL: ACKMEN Position         */
+#define I2C_BUSCTL_ACKMEN_Msk            (0x1ul << I2C_BUSCTL_ACKMEN_Pos)                  /*!< I2C_T::BUSCTL: ACKMEN Mask             */
+
+#define I2C_BUSCTL_PECEN_Pos             (1)                                               /*!< I2C_T::BUSCTL: PECEN Position          */
+#define I2C_BUSCTL_PECEN_Msk             (0x1ul << I2C_BUSCTL_PECEN_Pos)                   /*!< I2C_T::BUSCTL: PECEN Mask              */
+
+#define I2C_BUSCTL_BMDEN_Pos             (2)                                               /*!< I2C_T::BUSCTL: BMDEN Position          */
+#define I2C_BUSCTL_BMDEN_Msk             (0x1ul << I2C_BUSCTL_BMDEN_Pos)                   /*!< I2C_T::BUSCTL: BMDEN Mask              */
+
+#define I2C_BUSCTL_BMHEN_Pos             (3)                                               /*!< I2C_T::BUSCTL: BMHEN Position          */
+#define I2C_BUSCTL_BMHEN_Msk             (0x1ul << I2C_BUSCTL_BMHEN_Pos)                   /*!< I2C_T::BUSCTL: BMHEN Mask              */
+
+#define I2C_BUSCTL_ALERTEN_Pos           (4)                                               /*!< I2C_T::BUSCTL: ALERTEN Position        */
+#define I2C_BUSCTL_ALERTEN_Msk           (0x1ul << I2C_BUSCTL_ALERTEN_Pos)                 /*!< I2C_T::BUSCTL: ALERTEN Mask            */
+
+#define I2C_BUSCTL_SCTLOSTS_Pos          (5)                                               /*!< I2C_T::BUSCTL: SCTLOSTS Position       */
+#define I2C_BUSCTL_SCTLOSTS_Msk          (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos)                /*!< I2C_T::BUSCTL: SCTLOSTS Mask           */
+
+#define I2C_BUSCTL_SCTLOEN_Pos           (6)                                               /*!< I2C_T::BUSCTL: SCTLOEN Position        */
+#define I2C_BUSCTL_SCTLOEN_Msk           (0x1ul << I2C_BUSCTL_SCTLOEN_Pos)                 /*!< I2C_T::BUSCTL: SCTLOEN Mask            */
+
+#define I2C_BUSCTL_BUSEN_Pos             (7)                                               /*!< I2C_T::BUSCTL: BUSEN Position          */
+#define I2C_BUSCTL_BUSEN_Msk             (0x1ul << I2C_BUSCTL_BUSEN_Pos)                   /*!< I2C_T::BUSCTL: BUSEN Mask              */
+
+#define I2C_BUSCTL_PECTXEN_Pos           (8)                                               /*!< I2C_T::BUSCTL: PECTXEN Position        */
+#define I2C_BUSCTL_PECTXEN_Msk           (0x1ul << I2C_BUSCTL_PECTXEN_Pos)                 /*!< I2C_T::BUSCTL: PECTXEN Mask            */
+
+#define I2C_BUSCTL_TIDLE_Pos             (9)                                               /*!< I2C_T::BUSCTL: TIDLE Position          */
+#define I2C_BUSCTL_TIDLE_Msk             (0x1ul << I2C_BUSCTL_TIDLE_Pos)                   /*!< I2C_T::BUSCTL: TIDLE Mask              */
+
+#define I2C_BUSCTL_PECCLR_Pos            (10)                                              /*!< I2C_T::BUSCTL: PECCLR Position         */
+#define I2C_BUSCTL_PECCLR_Msk            (0x1ul << I2C_BUSCTL_PECCLR_Pos)                  /*!< I2C_T::BUSCTL: PECCLR Mask             */
+
+#define I2C_BUSCTL_ACKM9SI_Pos           (11)                                              /*!< I2C_T::BUSCTL: ACKM9SI Position        */
+#define I2C_BUSCTL_ACKM9SI_Msk           (0x1ul << I2C_BUSCTL_ACKM9SI_Pos)                 /*!< I2C_T::BUSCTL: ACKM9SI Mask            */
+
+#define I2C_BUSCTL_BCDIEN_Pos            (12)                                              /*!< I2C_T::BUSCTL: BCDIEN Position         */
+#define I2C_BUSCTL_BCDIEN_Msk            (0x1ul << I2C_BUSCTL_BCDIEN_Pos)                  /*!< I2C_T::BUSCTL: BCDIEN Mask             */
+
+#define I2C_BUSCTL_PECDIEN_Pos           (13)                                              /*!< I2C_T::BUSCTL: PECDIEN Position        */
+#define I2C_BUSCTL_PECDIEN_Msk           (0x1ul << I2C_BUSCTL_PECDIEN_Pos)                 /*!< I2C_T::BUSCTL: PECDIEN Mask            */
+
+#define I2C_BUSTCTL_BUSTOEN_Pos          (0)                                               /*!< I2C_T::BUSTCTL: BUSTOEN Position       */
+#define I2C_BUSTCTL_BUSTOEN_Msk          (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos)                /*!< I2C_T::BUSTCTL: BUSTOEN Mask           */
+
+#define I2C_BUSTCTL_CLKTOEN_Pos          (1)                                               /*!< I2C_T::BUSTCTL: CLKTOEN Position       */
+#define I2C_BUSTCTL_CLKTOEN_Msk          (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos)                /*!< I2C_T::BUSTCTL: CLKTOEN Mask           */
+
+#define I2C_BUSTCTL_BUSTOIEN_Pos         (2)                                               /*!< I2C_T::BUSTCTL: BUSTOIEN Position      */
+#define I2C_BUSTCTL_BUSTOIEN_Msk         (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos)               /*!< I2C_T::BUSTCTL: BUSTOIEN Mask          */
+
+#define I2C_BUSTCTL_CLKTOIEN_Pos         (3)                                               /*!< I2C_T::BUSTCTL: CLKTOIEN Position      */
+#define I2C_BUSTCTL_CLKTOIEN_Msk         (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos)               /*!< I2C_T::BUSTCTL: CLKTOIEN Mask          */
+
+#define I2C_BUSTCTL_TORSTEN_Pos          (4)                                               /*!< I2C_T::BUSTCTL: TORSTEN Position       */
+#define I2C_BUSTCTL_TORSTEN_Msk          (0x1ul << I2C_BUSTCTL_TORSTEN_Pos)                /*!< I2C_T::BUSTCTL: TORSTEN Mask           */
+
+#define I2C_BUSSTS_BUSY_Pos              (0)                                               /*!< I2C_T::BUSSTS: BUSY Position           */
+#define I2C_BUSSTS_BUSY_Msk              (0x1ul << I2C_BUSSTS_BUSY_Pos)                    /*!< I2C_T::BUSSTS: BUSY Mask               */
+
+#define I2C_BUSSTS_BCDONE_Pos            (1)                                               /*!< I2C_T::BUSSTS: BCDONE Position         */
+#define I2C_BUSSTS_BCDONE_Msk            (0x1ul << I2C_BUSSTS_BCDONE_Pos)                  /*!< I2C_T::BUSSTS: BCDONE Mask             */
+
+#define I2C_BUSSTS_PECERR_Pos            (2)                                               /*!< I2C_T::BUSSTS: PECERR Position         */
+#define I2C_BUSSTS_PECERR_Msk            (0x1ul << I2C_BUSSTS_PECERR_Pos)                  /*!< I2C_T::BUSSTS: PECERR Mask             */
+
+#define I2C_BUSSTS_ALERT_Pos             (3)                                               /*!< I2C_T::BUSSTS: ALERT Position          */
+#define I2C_BUSSTS_ALERT_Msk             (0x1ul << I2C_BUSSTS_ALERT_Pos)                   /*!< I2C_T::BUSSTS: ALERT Mask              */
+
+#define I2C_BUSSTS_SCTLDIN_Pos           (4)                                               /*!< I2C_T::BUSSTS: SCTLDIN Position        */
+#define I2C_BUSSTS_SCTLDIN_Msk           (0x1ul << I2C_BUSSTS_SCTLDIN_Pos)                 /*!< I2C_T::BUSSTS: SCTLDIN Mask            */
+
+#define I2C_BUSSTS_BUSTO_Pos             (5)                                               /*!< I2C_T::BUSSTS: BUSTO Position          */
+#define I2C_BUSSTS_BUSTO_Msk             (0x1ul << I2C_BUSSTS_BUSTO_Pos)                   /*!< I2C_T::BUSSTS: BUSTO Mask              */
+
+#define I2C_BUSSTS_CLKTO_Pos             (6)                                               /*!< I2C_T::BUSSTS: CLKTO Position          */
+#define I2C_BUSSTS_CLKTO_Msk             (0x1ul << I2C_BUSSTS_CLKTO_Pos)                   /*!< I2C_T::BUSSTS: CLKTO Mask              */
+
+#define I2C_BUSSTS_PECDONE_Pos           (7)                                               /*!< I2C_T::BUSSTS: PECDONE Position        */
+#define I2C_BUSSTS_PECDONE_Msk           (0x1ul << I2C_BUSSTS_PECDONE_Pos)                 /*!< I2C_T::BUSSTS: PECDONE Mask            */
+
+#define I2C_PKTSIZE_PLDSIZE_Pos          (0)                                               /*!< I2C_T::PKTSIZE: PLDSIZE Position       */
+#define I2C_PKTSIZE_PLDSIZE_Msk          (0x1fful << I2C_PKTSIZE_PLDSIZE_Pos)              /*!< I2C_T::PKTSIZE: PLDSIZE Mask           */
+
+#define I2C_PKTCRC_PECCRC_Pos            (0)                                               /*!< I2C_T::PKTCRC: PECCRC Position         */
+#define I2C_PKTCRC_PECCRC_Msk            (0xfful << I2C_PKTCRC_PECCRC_Pos)                 /*!< I2C_T::PKTCRC: PECCRC Mask             */
+
+#define I2C_BUSTOUT_BUSTO_Pos            (0)                                               /*!< I2C_T::BUSTOUT: BUSTO Position         */
+#define I2C_BUSTOUT_BUSTO_Msk            (0xfful << I2C_BUSTOUT_BUSTO_Pos)                 /*!< I2C_T::BUSTOUT: BUSTO Mask             */
+
+#define I2C_CLKTOUT_CLKTO_Pos            (0)                                               /*!< I2C_T::CLKTOUT: CLKTO Position         */
+#define I2C_CLKTOUT_CLKTO_Msk            (0xfful << I2C_CLKTOUT_CLKTO_Pos)                 /*!< I2C_T::CLKTOUT: CLKTO Mask             */
+
+/**@}*/ /* I2C_CONST */
+/**@}*/ /* end of I2C register group */
+/**@}*/ /* end of REGISTER group */
+
+
+#endif /* __I2C_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/i2s_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/i2s_reg.h
new file mode 100644
index 0000000000..5dc39514cb
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/i2s_reg.h
@@ -0,0 +1,701 @@
+/**************************************************************************//**
+ * @file     i2s_reg.h
+ * @version  V1.00
+ * @brief    I2S register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __I2S_REG_H__
+#define __I2S_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+/*---------------------- I2S Interface Controller -------------------------*/
+/**
+    @addtogroup I2S I2S Interface Controller(I2S)
+    Memory Mapped Structure for I2S Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var I2S_T::CTL0
+     * Offset: 0x00  I2S Control Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |I2SEN     |I2S Controller Enable Control
+     * |        |          |0 = I2S controller Disabled.
+     * |        |          |1 = I2S controller Enabled.
+     * |[1]     |TXEN      |Transmit Enable Control
+     * |        |          |0 = Data transmission Disabled.
+     * |        |          |1 = Data transmission Enabled.
+     * |[2]     |RXEN      |Receive Enable Control
+     * |        |          |0 = Data receiving Disabled.
+     * |        |          |1 = Data receiving Enabled.
+     * |[3]     |MUTE      |Transmit Mute Enable Control
+     * |        |          |0 = Transmit data is shifted from buffer.
+     * |        |          |1 = Send zero on transmit channel.
+     * |[5:4]   |DATWIDTH  |Data Width
+     * |        |          |This bit field is used to define the bit-width of data word in each audio channel
+     * |        |          |00 = The bit-width of data word is 8-bit.
+     * |        |          |01 = The bit-width of data word is 16-bit.
+     * |        |          |10 = The bit-width of data word is 24-bit.
+     * |        |          |11 = The bit-width of data word is 32-bit.
+     * |[6]     |MONO      |Monaural Data Control
+     * |        |          |0 = Data is stereo format.
+     * |        |          |1 = Data is monaural format.
+     * |        |          |Note: when chip records data, RXLCH (I2S_CTL0[23]) indicates which channel data will be saved if monaural format is selected.
+     * |[7]     |ORDER     |Stereo Data Order in FIFO
+     * |        |          |In 8-bit/16-bit data width, this bit is used to select whether the even or odd channel data is stored in higher byte
+     * |        |          |In 24-bit data width, this is used to select the left/right alignment method of audio data which is stored in data memory consisted of 32-bit FIFO entries.
+     * |        |          |0 = Even channel data at high byte in 8-bit/16-bit data width.
+     * |        |          |LSB of 24-bit audio data in each channel is aligned to right side in 32-bit FIFO entries.
+     * |        |          |1 = Even channel data at low byte.
+     * |        |          | MSB of 24-bit audio data in each channel is aligned to left side in 32-bit FIFO entries.
+     * |[8]     |SLAVE     |Slave Mode Enable Control
+     * |        |          |0 = Master mode.
+     * |        |          |1 = Slave mode.
+     * |        |          |Note: I2S can operate as master or slave
+     * |        |          |For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send out bit clock to Audio CODEC chip
+     * |        |          |In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip.
+     * |[15]    |MCLKEN    |Master Clock Enable Control
+     * |        |          |If MCLKEN is set to 1, I2S controller will generate master clock on I2S_MCLK pin for external audio devices.
+     * |        |          |0 = Master clock Disabled.
+     * |        |          |1 = Master clock Enabled.
+     * |[18]    |TXFBCLR   |Transmit FIFO Buffer Clear
+     * |        |          |0 = No Effect.
+     * |        |          |1 = Clear TX FIFO.
+     * |        |          |Note 1: Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXCNT (I2S_STATUS1[12:8]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed.
+     * |        |          |Note 2: This bit is clear by hardware automatically, read it return zero.
+     * |[19]    |RXFBCLR   |Receive FIFO Buffer Clear
+     * |        |          |0 = No Effect.
+     * |        |          |1 = Clear RX FIFO.
+     * |        |          |Note 1: Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXCNT (I2S_STATUS1[20:16]) returns 0 and receive FIFO becomes empty.
+     * |        |          |Note 2: This bit is cleared by hardware automatically, read it return zero.
+     * |[20]    |TXPDMAEN  |Transmit PDMA Enable Control
+     * |        |          |0 = Transmit PDMA function Disabled.
+     * |        |          |1 = Transmit PDMA function Enabled.
+     * |[21]    |RXPDMAEN  |Receive PDMA Enable Control
+     * |        |          |0 = Receiver PDMA function Disabled.
+     * |        |          |1 = Receiver PDMA function Enabled.
+     * |[23]    |RXLCH     |Receive Left Channel Enable Control
+     * |        |          |When monaural format is selected (MONO = 1), I2S will receive channel1 data if RXLCH is set to 0, and receive channel0 data if RXLCH is set to 1.
+     * |        |          |0 = Receives channel1 data in MONO mode.
+     * |        |          |1 = Receives channel0 data in MONO mode.
+     * |[26:24] |FORMAT    |Data Format Selection
+     * |        |          |000 = I2S standard data format.
+     * |        |          |001 = I2S with MSB justified.
+     * |        |          |010 = I2S with LSB justified.
+     * |        |          |011 = Reserved.
+     * |        |          |100 = PCM standard data format.
+     * |        |          |101 = PCM with MSB justified.
+     * |        |          |110 = PCM with LSB justified.
+     * |        |          |111 = Reserved.
+     * |[27]    |PCMSYNC   |PCM Synchronization Pulse Length Selection
+     * |        |          |This bit field is used to select the high pulse length of frame synchronization signal in PCM protocol.
+     * |        |          |0 = One BCLK period.
+     * |        |          |1 = One channel period.
+     * |        |          |Note: This bit is only available in master mode.
+     * |[29:28] |CHWIDTH   |Channel Width
+     * |        |          |This bit fields are used to define the length of audio channel
+     * |        |          |If CHWIDTH < DATWIDTH, the hardware will set the real channel length as the bit-width of audio data which is defined by DATWIDTH.
+     * |        |          |00 = The bit-width of each audio channel is 8-bit.
+     * |        |          |01 = The bit-width of each audio channel is 16-bit.
+     * |        |          |10 = The bit-width of each audio channel is 24-bit.
+     * |        |          |11 = The bit-width of each audio channel is 32-bit.
+     * |[31:30] |TDMCHNUM  |TDM Channel Number
+     * |        |          |This bit fields are used to define the TDM channel number in one audio frame while PCM mode (FORMAT[2] = 1).
+     * |        |          |00 = 2 channels in audio frame.
+     * |        |          |01 = 4 channels in audio frame.
+     * |        |          |10 = 6 channels in audio frame.
+     * |        |          |11 = 8 channels in audio frame.
+     * @var I2S_T::CLKDIV
+     * Offset: 0x04  I2S Clock Divider Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[5:0]   |MCLKDIV   |Master Clock Divider
+     * |        |          |If chip external crystal frequency is (2 x MCLKDIV) x 256fs then software can program these bits to generate 256fs clock frequency to audio codec chip
+     * |        |          |If MCLKDIV is set to 0, MCLK is the same as external clock input.
+     * |        |          |For example, sampling rate is 24 kHz and chip external crystal clock is 12.288 MHz, set MCLKDIV = 1.
+     * |        |          |F_MCLK = F_I2SCLK/(2 x MCLKDIV) (When MCLKDIV is >= 1 ).
+     * |        |          |F_MCLK = F_I2SCLK (When MCLKDIV is set to 0 ).
+     * |        |          |Note: F_MCLK is the frequency of MCLK, and F_I2SCLK is the frequency of the I2S_CLK.
+     * |[16:8]  |BCLKDIV   |Bit Clock Divider
+     * |        |          |The I2S controller will generate bit clock in Master mode
+     * |        |          |Software can program these bit fields to generate sampling rate clock frequency.
+     * |        |          |F_BCLK= F_I2SCLK / (2 x (BCLKDIV + 1)).
+     * |        |          |Note: F_BCLK is the frequency of BCLK and F_I2SCLK is the frequency of I2S_CLK.
+     * @var I2S_T::IEN
+     * Offset: 0x08  I2S Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RXUDFIEN  |Receive FIFO Underflow Interrupt Enable Control
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note: If software reads receive FIFO when it is empty then RXUDIF (I2S_STATUS0[8]) flag is set to 1.
+     * |[1]     |RXOVFIEN  |Receive FIFO Overflow Interrupt Enable Control
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note: Interrupt occurs if this bit is set to 1 and RXOVIF (I2S_STATUS0[9]) flag is set to 1.
+     * |[2]     |RXTHIEN   |Receive FIFO Threshold Level Interrupt Enable Control
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note: When data word in receive FIFO is equal or higher than RXTH (I2S_CTL1[19:16]) and the RXTHIF (I2S_STATUS0[10]) bit is set to 1
+     * |        |          |If RXTHIEN bit is enabled, interrupt occur.
+     * |[8]     |TXUDFIEN  |Transmit FIFO Underflow Interrupt Enable Control
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note: Interrupt occur if this bit is set to 1 and TXUDIF (I2S_STATUS0[16]) flag is set to 1.
+     * |[9]     |TXOVFIEN  |Transmit FIFO Overflow Interrupt Enable Control
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note: Interrupt occurs if this bit is set to 1 and TXOVIF (I2S_STATUS0[17]) flag is set to 1.
+     * |[10]    |TXTHIEN   |Transmit FIFO Threshold Level Interrupt Enable Control
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH (I2S_CTL1[11:8]).
+     * |[16]    |CH0ZCIEN  |Channel0 Zero-cross Interrupt Enable Control
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note 1: Interrupt occurs if this bit is set to 1 and channel0 zero-cross.
+     * |        |          |Note 2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
+     * |[17]    |CH1ZCIEN  |Channel1 Zero-cross Interrupt Enable Control
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note 1: Interrupt occurs if this bit is set to 1 and channel1 zero-cross.
+     * |        |          |Note 2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
+     * |[18]    |CH2ZCIEN  |Channel2 Zero-cross Interrupt Enable Control
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note 1: Interrupt occurs if this bit is set to 1 and channel2 zero-cross.
+     * |        |          |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |[19]    |CH3ZCIEN  |Channel3 Zero-cross Interrupt Enable Control
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note 1: Interrupt occurs if this bit is set to 1 and channel3 zero-cross.
+     * |        |          |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |[20]    |CH4ZCIEN  |Channel4 Zero-cross Interrupt Enable Control
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note 1: Interrupt occurs if this bit is set to 1 and channel4 zero-cross.
+     * |        |          |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |[21]    |CH5ZCIEN  |Channel5 Zero-cross Interrupt Enable Control
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note 1: Interrupt occurs if this bit is set to 1 and channel5 zero-cross.
+     * |        |          |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |[22]    |CH6ZCIEN  |Channel6 Zero-cross Interrupt Enable Control
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note 1: Interrupt occurs if this bit is set to 1 and channel6 zero-cross.
+     * |        |          |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |[23]    |CH7ZCIEN  |Channel7 Zero-cross Interrupt Enable Control
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note 1: Interrupt occurs if this bit is set to 1 and channel7 zero-cross.
+     * |        |          |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * @var I2S_T::STATUS0
+     * Offset: 0x0C  I2S Status Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |I2SINT    |I2S Interrupt Flag (Read Only)
+     * |        |          |0 = No I2S interrupt.
+     * |        |          |1 = I2S interrupt.
+     * |        |          |Note: It is wire-OR of I2STXINT and I2SRXINT bits.
+     * |[1]     |I2SRXINT  |I2S Receive Interrupt (Read Only)
+     * |        |          |0 = No receive interrupt.
+     * |        |          |1 = Receive interrupt.
+     * |[2]     |I2STXINT  |I2S Transmit Interrupt (Read Only)
+     * |        |          |0 = No transmit interrupt.
+     * |        |          |1 = Transmit interrupt.
+     * |[5:3]   |DATACH    |Transmission Data Channel (Read Only)
+     * |        |          |This bit fields are used to indicate which audio channel is current transmit data belong.
+     * |        |          |000 = channel0 (means left channel while 2-channel I2S/PCM mode).
+     * |        |          |001 = channel1 (means right channel while 2-channel I2S/PCM mode).
+     * |        |          |010 = channel2 (available while 4-channel TDM PCM mode).
+     * |        |          |011 = channel3 (available while 4-channel TDM PCM mode).
+     * |        |          |100 = channel4 (available while 6-channel TDM PCM mode).
+     * |        |          |101 = channel5 (available while 6-channel TDM PCM mode).
+     * |        |          |110 = channel6 (available while 8-channel TDM PCM mode).
+     * |        |          |111 = channel7 (available while 8-channel TDM PCM mode).
+     * |[8]     |RXUDIF    |Receive FIFO Underflow Interrupt Flag
+     * |        |          |0 = No underflow occur.
+     * |        |          |1 = Underflow occur.
+     * |        |          |Note 1: When receive FIFO is empty, and software reads the receive FIFO again
+     * |        |          |This bit will be set to 1, and it indicates underflow situation occurs.
+     * |        |          |Note 2: Write 1 to clear this bit to zero
+     * |[9]     |RXOVIF    |Receive FIFO Overflow Interrupt Flag
+     * |        |          |0 = No overflow occur.
+     * |        |          |1 = Overflow occur.
+     * |        |          |Note 1: When receive FIFO is full and receive hardware attempt to write data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote.
+     * |        |          |Note 2: Write 1 to clear this bit to 0.
+     * |[10]    |RXTHIF    |Receive FIFO Threshold Interrupt Flag (Read Only)
+     * |        |          |0 = Data word(s) in FIFO is not higher than threshold level.
+     * |        |          |1 = Data word(s) in FIFO is higher than threshold level.
+     * |        |          |Note: When data word(s) in receive FIFO is higher than threshold value set in RXTH (I2S_CTL1[19:16]) the RXTHIF bit becomes to 1
+     * |        |          |It keeps at 1 till RXCNT (I2S_STATUS1[20:16]) is not higher than RXTH (I2S_CTL1[19:16]) after software read RXFIFO register.
+     * |[11]    |RXFULL    |Receive FIFO Full (Read Only)
+     * |        |          |0 = Not full.
+     * |        |          |1 = Full.
+     * |        |          |Note: This bit reflects data words number in receive FIFO is 16.
+     * |[12]    |RXEMPTY   |Receive FIFO Empty (Read Only)
+     * |        |          |0 = Not empty.
+     * |        |          |1 = Empty.
+     * |        |          |Note: This bit reflects data words number in receive FIFO is 0.
+     * |[16]    |TXUDIF    |Transmit FIFO Underflow Interrupt Flag
+     * |        |          |0 = No underflow.
+     * |        |          |1 = Underflow.
+     * |        |          |Note 1: This bit will be set to 1 when shift logic hardware read data from transmitting FIFO and the filling data level in transmitting FIFO is not enough for one audio frame.
+     * |        |          |Note 2: Write 1 to clear this bit to 0.
+     * |[17]    |TXOVIF    |Transmit FIFO Overflow Interrupt Flag
+     * |        |          |0 = No overflow.
+     * |        |          |1 = Overflow.
+     * |        |          |Note 1: Write data to transmit FIFO when it is full and this bit set to 1.
+     * |        |          |Note 2: Write 1 to clear this bit to 0.
+     * |[18]    |TXTHIF    |Transmit FIFO Threshold Interrupt Flag (Read Only)
+     * |        |          |0 = Data word(s) in FIFO is higher than threshold level.
+     * |        |          |1 = Data word(s) in FIFO is equal or lower than threshold level.
+     * |        |          |Note: When data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH (I2S_CTL1[11:8]) the TXTHIF bit becomes to 1
+     * |        |          |It keeps at 1 till TXCNT (I2S_STATUS1[12:8]) is higher than TXTH (I2S_CTL1[11:8]) after software write TXFIFO register.
+     * |[19]    |TXFULL    |Transmit FIFO Full (Read Only)
+     * |        |          |0 = Not full.
+     * |        |          |1 = Full.
+     * |        |          |Note: This bit reflects data words number in transmit FIFO is 16.
+     * |[20]    |TXEMPTY   |Transmit FIFO Empty (Read Only)
+     * |        |          |0 = Not empty.
+     * |        |          |1 = Empty.
+     * |        |          |Note: This bit reflects data words number in transmit FIFO is 0.
+     * |[21]    |TXBUSY    |Transmit Busy (Read Only)
+     * |        |          |0 = Transmit shift buffer is empty.
+     * |        |          |1 = Transmit shift buffer is busy.
+     * |        |          |Note: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out
+     * |        |          |And set to 1 when 1st data is load to shift buffer
+     * @var I2S_T::TXFIFO
+     * Offset: 0x10  I2S Transmit FIFO Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |TXFIFO    |Transmit FIFO Bits
+     * |        |          |I2S contains 16 words (16x32 bit) data buffer for data transmit
+     * |        |          |Write data to this register to prepare data for transmit
+     * |        |          |The remaining word number is indicated by TXCNT (I2S_STATUS1[12:8]).
+     * @var I2S_T::RXFIFO
+     * Offset: 0x14  I2S Receive FIFO Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |RXFIFO    |Receive FIFO Bits
+     * |        |          |I2S contains 16 words (16x32 bit) data buffer for data receive
+     * |        |          |Read this register to get data in FIFO
+     * |        |          |The remaining data word number is indicated by RXCNT (I2S_STATUS1[20:16]).
+     * @var I2S_T::CTL1
+     * Offset: 0x20  I2S Control Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CH0ZCEN   |Channel0 Zero-cross Detection Enable Control
+     * |        |          |0 = channel0 zero-cross detect Disabled.
+     * |        |          |1 = channel0 zero-cross detect Enabled.
+     * |        |          |Note 1: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
+     * |        |          |Note 2: If this bit is set to 1, when channel0 data sign bit change or next shift data bits are all zero then CH0ZCIF(I2S_STATUS1[0]) flag is set to 1.
+     * |        |          |Note 3: If CH0ZCIF Flag is set to 1, the channel0 will be mute.
+     * |[1]     |CH1ZCEN   |Channel1 Zero-cross Detect Enable Control
+     * |        |          |0 = channel1 zero-cross detect Disabled.
+     * |        |          |1 = channel1 zero-cross detect Enabled.
+     * |        |          |Note 1: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
+     * |        |          |Note 2: If this bit is set to 1, when channel1 data sign bit change or next shift data bits are all zero then CH1ZCIF(I2S_STATUS1[1]) flag is set to 1.
+     * |        |          |Note 3: If CH1ZCIF Flag is set to 1, the channel1 will be mute.
+     * |[2]     |CH2ZCEN   |Channel2 Zero-cross Detect Enable Control
+     * |        |          |0 = channel2 zero-cross detect Disabled.
+     * |        |          |1 = channel2 zero-cross detect Enabled.
+     * |        |          |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |        |          |Note 2: If this bit is set to 1, when channel2 data sign bit change or next shift data bits are all zero then CH2ZCIF(I2S_STATUS1[2]) flag is set to 1.
+     * |        |          |Note 3: If CH2ZCIF Flag is set to 1, the channel2 will be mute.
+     * |[3]     |CH3ZCEN   |Channel3 Zero-cross Detect Enable Control
+     * |        |          |0 = channel3 zero-cross detect Disabled.
+     * |        |          |1 = channel3 zero-cross detect Enabled.
+     * |        |          |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |        |          |Note 2: If this bit is set to 1, when channel3 data sign bit change or next shift data bits are all zero then CH3ZCIF(I2S_STATUS1[3]) flag is set to 1.
+     * |        |          |Note 3: If CH3ZCIF Flag is set to 1, the channel3 will be mute.
+     * |[4]     |CH4ZCEN   |Channel4 Zero-cross Detect Enable Control
+     * |        |          |0 = channel4 zero-cross detect Disabled.
+     * |        |          |1 = channel4 zero-cross detect Enabled.
+     * |        |          |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |        |          |Note 2: If this bit is set to 1, when channel4 data sign bit change or next shift data bits are all zero then CH4ZCIF(I2S_STATUS1[4]) flag is set to 1.
+     * |        |          |Note 3: If CH4ZCIF Flag is set to 1, the channel4 will be mute.
+     * |[5]     |CH5ZCEN   |Channel5 Zero-cross Detect Enable Control
+     * |        |          |0 = channel5 zero-cross detect Disabled.
+     * |        |          |1 = channel5 zero-cross detect Enabled.
+     * |        |          |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |        |          |Note 2: If this bit is set to 1, when channel5 data sign bit change or next shift data bits are all zero then CH5ZCIF(I2S_STATUS1[5]) flag is set to 1.
+     * |        |          |Note 3: If CH5ZCIF Flag is set to 1, the channel5 will be mute.
+     * |[6]     |CH6ZCEN   |Channel6 Zero-cross Detect Enable Control
+     * |        |          |0 = channel6 zero-cross detect Disabled.
+     * |        |          |1 = channel6 zero-cross detect Enabled.
+     * |        |          |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |        |          |Note 2: If this bit is set to 1, when channel6 data sign bit change or next shift data bits are all zero then CH6ZCIF(I2S_STATUS1[6]) flag is set to 1.
+     * |        |          |Note 3: If CH6ZCIF Flag is set to 1, the channel6 will be mute.
+     * |[7]     |CH7ZCEN   |Channel7 Zero-cross Detect Enable Control
+     * |        |          |0 = channel7 zero-cross detect Disabled.
+     * |        |          |1 = channel7 zero-cross detect Enabled.
+     * |        |          |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |        |          |Note 2: If this bit is set to 1, when channel7 data sign bit change or next shift data bits are all zero then CH7ZCIF (I2S_STATUS1[7]) flag is set to 1.
+     * |        |          |Note 3: If CH7ZCIF Flag is set to 1, the channel7 will be mute.
+     * |[11:8]  |TXTH      |Transmit FIFO Threshold Level
+     * |        |          |0000 = 0 data word in transmit FIFO.
+     * |        |          |0001 = 1 data word in transmit FIFO.
+     * |        |          |0010 = 2 data words in transmit FIFO.
+     * |        |          |...
+     * |        |          |1110 = 14 data words in transmit FIFO.
+     * |        |          |1111 = 15 data words in transmit FIFO.
+     * |        |          |Note: If remain data word number in transmit FIFO is the same or less than threshold level then TXTHIF (I2S_STATUS0[18]) flag is set.
+     * |[19:16] |RXTH      |Receive FIFO Threshold Level
+     * |        |          |0000 = 1 data word in receive FIFO.
+     * |        |          |0001 = 2 data words in receive FIFO.
+     * |        |          |0010 = 3 data words in receive FIFO.
+     * |        |          |...
+     * |        |          |1110 = 15 data words in receive FIFO.
+     * |        |          |1111 = 16 data words in receive FIFO.
+     * |        |          |Note: When received data word number in receive buffer is greater than threshold level then RXTHIF (I2S_STATUS0[10]) flag is set.
+     * |[24]    |PBWIDTH   |Peripheral Bus Data Width Selection
+     * |        |          |This bit is used to choice the available data width of APB bus
+     * |        |          |It must be set to 1 while PDMA function is enable and it is set to 16-bit transmission mode
+     * |        |          |0 = 32 bits data width.
+     * |        |          |1 = 16 bits data width.
+     * |        |          |Note 1: If PBWIDTH=1, the low 16 bits of 32-bit data bus are available.
+     * |        |          |Note 2: If PBWIDTH=1, the transmitting FIFO level will be increased after two FIFO write operations.
+     * |        |          |Note 3: If PBWIDTH=1, the receiving FIFO level will be decreased after two FIFO read operations.
+     * |[25]    |PB16ORD   |FIFO Read/Write Order in 16-bit Width of Peripheral Bus
+     * |        |          |When PBWIDTH = 1, the data FIFO will be increased or decreased by two peripheral bus access
+     * |        |          |This bit is used to select the order of FIFO access operations to meet the 32-bit transmitting/receiving FIFO entries.
+     * |        |          |0 = Low 16-bit read/write access first.
+     * |        |          |1 = High 16-bit read/write access first.
+     * |        |          |Note: This bit is available while PBWIDTH = 1.
+     * @var I2S_T::STATUS1
+     * Offset: 0x24  I2S Status Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CH0ZCIF   |Channel0 Zero-cross Interrupt Flag
+     * |        |          |It indicates channel0 next sample data sign bit is changed or all data bits are zero.
+     * |        |          |0 = No zero-cross in channel0.
+     * |        |          |1 = Channel0 zero-cross is detected.
+     * |        |          |Note 1: Write 1 to clear this bit to 0.
+     * |        |          |Note 2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
+     * |[1]     |CH1ZCIF   |Channel1 Zero-cross Interrupt Flag
+     * |        |          |It indicates channel1 next sample data sign bit is changed or all data bits are zero.
+     * |        |          |0 = No zero-cross in channel1.
+     * |        |          |1 = Channel1 zero-cross is detected.
+     * |        |          |Note 1: Write 1 to clear this bit to 0.
+     * |        |          |Note 2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode.
+     * |[2]     |CH2ZCIF   |Channel2 Zero-cross Interrupt Flag
+     * |        |          |It indicates channel2 next sample data sign bit is changed or all data bits are zero.
+     * |        |          |0 = No zero-cross in channel2.
+     * |        |          |1 = Channel2 zero-cross is detected.
+     * |        |          |Note 1: Write 1 to clear this bit to 0.
+     * |        |          |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |[3]     |CH3ZCIF   |Channel3 Zero-cross Interrupt Flag
+     * |        |          |It indicates channel3 next sample data sign bit is changed or all data bits are zero.
+     * |        |          |0 = No zero-cross in channel3.
+     * |        |          |1 = Channel3 zero-cross is detected.
+     * |        |          |Note 1: Write 1 to clear this bit to 0.
+     * |        |          |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |[4]     |CH4ZCIF   |Channel4 Zero-cross Interrupt Flag
+     * |        |          |It indicates channel4 next sample data sign bit is changed or all data bits are zero.
+     * |        |          |0 = No zero-cross in channel4.
+     * |        |          |1 = Channel4 zero-cross is detected.
+     * |        |          |Note 1: Write 1 to clear this bit to 0.
+     * |        |          |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |[5]     |CH5ZCIF   |Channel5 Zero-cross Interrupt Flag
+     * |        |          |It indicates channel5 next sample data sign bit is changed or all data bits are zero.
+     * |        |          |0 = No zero-cross in channel5.
+     * |        |          |1 = Channel5 zero-cross is detected.
+     * |        |          |Note 1: Write 1 to clear this bit to 0.
+     * |        |          |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |[6]     |CH6ZCIF   |Channel6 Zero-cross Interrupt Flag
+     * |        |          |It indicates channel6 next sample data sign bit is changed or all data bits are zero.
+     * |        |          |0 = No zero-cross in channel6.
+     * |        |          |1 = Channel6 zero-cross is detected.
+     * |        |          |Note 1: Write 1 to clear this bit to 0.
+     * |        |          |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |[7]     |CH7ZCIF   |Channel7 Zero-cross Interrupt Flag
+     * |        |          |It indicates channel7 next sample data sign bit is changed or all data bits are zero.
+     * |        |          |0 = No zero-cross in channel7.
+     * |        |          |1 = Channel7 zero-cross is detected.
+     * |        |          |Note 1: Write 1 to clear this bit to 0.
+     * |        |          |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3.
+     * |[12:8]  |TXCNT     |Transmit FIFO Level (Read Only)
+     * |        |          |These bits indicate the number of available entries in transmit FIFO.
+     * |        |          |00000 = No data.
+     * |        |          |00001 = 1 word in transmit FIFO.
+     * |        |          |00010 = 2 words in transmit FIFO.
+     * |        |          |...
+     * |        |          |01110 = 14 words in transmit FIFO.
+     * |        |          |01111 = 15 words in transmit FIFO.
+     * |        |          |10000 = 16 words in transmit FIFO.
+     * |        |          |Others are reserved.
+     * |[20:16] |RXCNT     |Receive FIFO Level (Read Only)
+     * |        |          |These bits indicate the number of available entries in receive FIFO.
+     * |        |          |00000 = No data.
+     * |        |          |00001 = 1 word in receive FIFO.
+     * |        |          |00010 = 2 words in receive FIFO.
+     * |        |          |...
+     * |        |          |01110 = 14 words in receive FIFO.
+     * |        |          |01111 = 15 words in receive FIFO.
+     * |        |          |10000 = 16 words in receive FIFO.
+     * |        |          |Others are reserved.
+     */
+    __IO uint32_t CTL0;                  /*!< [0x0000] I2S Control Register 0                                           */
+    __IO uint32_t CLKDIV;                /*!< [0x0004] I2S Clock Divider Register                                       */
+    __IO uint32_t IEN;                   /*!< [0x0008] I2S Interrupt Enable Register                                    */
+    __IO uint32_t STATUS0;               /*!< [0x000c] I2S Status Register 0                                            */
+    __O  uint32_t TXFIFO;                /*!< [0x0010] I2S Transmit FIFO Register                                       */
+    __I  uint32_t RXFIFO;                /*!< [0x0014] I2S Receive FIFO Register                                        */
+    __I  uint32_t RESERVE0[2];
+    __IO uint32_t CTL1;                  /*!< [0x0020] I2S Control Register 1                                           */
+    __IO uint32_t STATUS1;               /*!< [0x0024] I2S Status Register 1                                            */
+
+} I2S_T;
+
+/**
+    @addtogroup I2S_CONST I2S Bit Field Definition
+    Constant Definitions for I2S Controller
+  @{
+*/
+
+#define I2S_CTL0_I2SEN_Pos               (0)                                               /*!< I2S_T::CTL0: I2SEN Position            */
+#define I2S_CTL0_I2SEN_Msk               (0x1ul << I2S_CTL0_I2SEN_Pos)                     /*!< I2S_T::CTL0: I2SEN Mask                */
+
+#define I2S_CTL0_TXEN_Pos                (1)                                               /*!< I2S_T::CTL0: TXEN Position             */
+#define I2S_CTL0_TXEN_Msk                (0x1ul << I2S_CTL0_TXEN_Pos)                      /*!< I2S_T::CTL0: TXEN Mask                 */
+
+#define I2S_CTL0_RXEN_Pos                (2)                                               /*!< I2S_T::CTL0: RXEN Position             */
+#define I2S_CTL0_RXEN_Msk                (0x1ul << I2S_CTL0_RXEN_Pos)                      /*!< I2S_T::CTL0: RXEN Mask                 */
+
+#define I2S_CTL0_MUTE_Pos                (3)                                               /*!< I2S_T::CTL0: MUTE Position             */
+#define I2S_CTL0_MUTE_Msk                (0x1ul << I2S_CTL0_MUTE_Pos)                      /*!< I2S_T::CTL0: MUTE Mask                 */
+
+#define I2S_CTL0_DATWIDTH_Pos            (4)                                               /*!< I2S_T::CTL0: DATWIDTH Position         */
+#define I2S_CTL0_DATWIDTH_Msk            (0x3ul << I2S_CTL0_DATWIDTH_Pos)                  /*!< I2S_T::CTL0: DATWIDTH Mask             */
+
+#define I2S_CTL0_MONO_Pos                (6)                                               /*!< I2S_T::CTL0: MONO Position             */
+#define I2S_CTL0_MONO_Msk                (0x1ul << I2S_CTL0_MONO_Pos)                      /*!< I2S_T::CTL0: MONO Mask                 */
+
+#define I2S_CTL0_ORDER_Pos               (7)                                               /*!< I2S_T::CTL0: ORDER Position            */
+#define I2S_CTL0_ORDER_Msk               (0x1ul << I2S_CTL0_ORDER_Pos)                     /*!< I2S_T::CTL0: ORDER Mask                */
+
+#define I2S_CTL0_SLAVE_Pos               (8)                                               /*!< I2S_T::CTL0: SLAVE Position            */
+#define I2S_CTL0_SLAVE_Msk               (0x1ul << I2S_CTL0_SLAVE_Pos)                     /*!< I2S_T::CTL0: SLAVE Mask                */
+
+#define I2S_CTL0_MCLKEN_Pos              (15)                                              /*!< I2S_T::CTL0: MCLKEN Position           */
+#define I2S_CTL0_MCLKEN_Msk              (0x1ul << I2S_CTL0_MCLKEN_Pos)                    /*!< I2S_T::CTL0: MCLKEN Mask               */
+
+#define I2S_CTL0_TXFBCLR_Pos             (18)                                              /*!< I2S_T::CTL0: TXFBCLR Position          */
+#define I2S_CTL0_TXFBCLR_Msk             (0x1ul << I2S_CTL0_TXFBCLR_Pos)                   /*!< I2S_T::CTL0: TXFBCLR Mask              */
+
+#define I2S_CTL0_RXFBCLR_Pos             (19)                                              /*!< I2S_T::CTL0: RXFBCLR Position          */
+#define I2S_CTL0_RXFBCLR_Msk             (0x1ul << I2S_CTL0_RXFBCLR_Pos)                   /*!< I2S_T::CTL0: RXFBCLR Mask              */
+
+#define I2S_CTL0_TXPDMAEN_Pos            (20)                                              /*!< I2S_T::CTL0: TXPDMAEN Position         */
+#define I2S_CTL0_TXPDMAEN_Msk            (0x1ul << I2S_CTL0_TXPDMAEN_Pos)                  /*!< I2S_T::CTL0: TXPDMAEN Mask             */
+
+#define I2S_CTL0_RXPDMAEN_Pos            (21)                                              /*!< I2S_T::CTL0: RXPDMAEN Position         */
+#define I2S_CTL0_RXPDMAEN_Msk            (0x1ul << I2S_CTL0_RXPDMAEN_Pos)                  /*!< I2S_T::CTL0: RXPDMAEN Mask             */
+
+#define I2S_CTL0_RXLCH_Pos               (23)                                              /*!< I2S_T::CTL0: RXLCH Position            */
+#define I2S_CTL0_RXLCH_Msk               (0x1ul << I2S_CTL0_RXLCH_Pos)                     /*!< I2S_T::CTL0: RXLCH Mask                */
+
+#define I2S_CTL0_FORMAT_Pos              (24)                                              /*!< I2S_T::CTL0: FORMAT Position           */
+#define I2S_CTL0_FORMAT_Msk              (0x7ul << I2S_CTL0_FORMAT_Pos)                    /*!< I2S_T::CTL0: FORMAT Mask               */
+
+#define I2S_CTL0_PCMSYNC_Pos             (27)                                              /*!< I2S_T::CTL0: PCMSYNC Position          */
+#define I2S_CTL0_PCMSYNC_Msk             (0x1ul << I2S_CTL0_PCMSYNC_Pos)                   /*!< I2S_T::CTL0: PCMSYNC Mask              */
+
+#define I2S_CTL0_CHWIDTH_Pos             (28)                                              /*!< I2S_T::CTL0: CHWIDTH Position          */
+#define I2S_CTL0_CHWIDTH_Msk             (0x3ul << I2S_CTL0_CHWIDTH_Pos)                   /*!< I2S_T::CTL0: CHWIDTH Mask              */
+
+#define I2S_CTL0_TDMCHNUM_Pos            (30)                                              /*!< I2S_T::CTL0: TDMCHNUM Position         */
+#define I2S_CTL0_TDMCHNUM_Msk            (0x3ul << I2S_CTL0_TDMCHNUM_Pos)                  /*!< I2S_T::CTL0: TDMCHNUM Mask             */
+
+#define I2S_CLKDIV_MCLKDIV_Pos           (0)                                               /*!< I2S_T::CLKDIV: MCLKDIV Position        */
+#define I2S_CLKDIV_MCLKDIV_Msk           (0x3ful << I2S_CLKDIV_MCLKDIV_Pos)                /*!< I2S_T::CLKDIV: MCLKDIV Mask            */
+
+#define I2S_CLKDIV_BCLKDIV_Pos           (8)                                               /*!< I2S_T::CLKDIV: BCLKDIV Position        */
+#define I2S_CLKDIV_BCLKDIV_Msk           (0x1fful << I2S_CLKDIV_BCLKDIV_Pos)               /*!< I2S_T::CLKDIV: BCLKDIV Mask            */
+
+#define I2S_IEN_RXUDFIEN_Pos             (0)                                               /*!< I2S_T::IEN: RXUDFIEN Position          */
+#define I2S_IEN_RXUDFIEN_Msk             (0x1ul << I2S_IEN_RXUDFIEN_Pos)                   /*!< I2S_T::IEN: RXUDFIEN Mask              */
+
+#define I2S_IEN_RXOVFIEN_Pos             (1)                                               /*!< I2S_T::IEN: RXOVFIEN Position          */
+#define I2S_IEN_RXOVFIEN_Msk             (0x1ul << I2S_IEN_RXOVFIEN_Pos)                   /*!< I2S_T::IEN: RXOVFIEN Mask              */
+
+#define I2S_IEN_RXTHIEN_Pos              (2)                                               /*!< I2S_T::IEN: RXTHIEN Position           */
+#define I2S_IEN_RXTHIEN_Msk              (0x1ul << I2S_IEN_RXTHIEN_Pos)                    /*!< I2S_T::IEN: RXTHIEN Mask               */
+
+#define I2S_IEN_TXUDFIEN_Pos             (8)                                               /*!< I2S_T::IEN: TXUDFIEN Position          */
+#define I2S_IEN_TXUDFIEN_Msk             (0x1ul << I2S_IEN_TXUDFIEN_Pos)                   /*!< I2S_T::IEN: TXUDFIEN Mask              */
+
+#define I2S_IEN_TXOVFIEN_Pos             (9)                                               /*!< I2S_T::IEN: TXOVFIEN Position          */
+#define I2S_IEN_TXOVFIEN_Msk             (0x1ul << I2S_IEN_TXOVFIEN_Pos)                   /*!< I2S_T::IEN: TXOVFIEN Mask              */
+
+#define I2S_IEN_TXTHIEN_Pos              (10)                                              /*!< I2S_T::IEN: TXTHIEN Position           */
+#define I2S_IEN_TXTHIEN_Msk              (0x1ul << I2S_IEN_TXTHIEN_Pos)                    /*!< I2S_T::IEN: TXTHIEN Mask               */
+
+#define I2S_IEN_CH0ZCIEN_Pos             (16)                                              /*!< I2S_T::IEN: CH0ZCIEN Position          */
+#define I2S_IEN_CH0ZCIEN_Msk             (0x1ul << I2S_IEN_CH0ZCIEN_Pos)                   /*!< I2S_T::IEN: CH0ZCIEN Mask              */
+
+#define I2S_IEN_CH1ZCIEN_Pos             (17)                                              /*!< I2S_T::IEN: CH1ZCIEN Position          */
+#define I2S_IEN_CH1ZCIEN_Msk             (0x1ul << I2S_IEN_CH1ZCIEN_Pos)                   /*!< I2S_T::IEN: CH1ZCIEN Mask              */
+
+#define I2S_IEN_CH2ZCIEN_Pos             (18)                                              /*!< I2S_T::IEN: CH2ZCIEN Position          */
+#define I2S_IEN_CH2ZCIEN_Msk             (0x1ul << I2S_IEN_CH2ZCIEN_Pos)                   /*!< I2S_T::IEN: CH2ZCIEN Mask              */
+
+#define I2S_IEN_CH3ZCIEN_Pos             (19)                                              /*!< I2S_T::IEN: CH3ZCIEN Position          */
+#define I2S_IEN_CH3ZCIEN_Msk             (0x1ul << I2S_IEN_CH3ZCIEN_Pos)                   /*!< I2S_T::IEN: CH3ZCIEN Mask              */
+
+#define I2S_IEN_CH4ZCIEN_Pos             (20)                                              /*!< I2S_T::IEN: CH4ZCIEN Position          */
+#define I2S_IEN_CH4ZCIEN_Msk             (0x1ul << I2S_IEN_CH4ZCIEN_Pos)                   /*!< I2S_T::IEN: CH4ZCIEN Mask              */
+
+#define I2S_IEN_CH5ZCIEN_Pos             (21)                                              /*!< I2S_T::IEN: CH5ZCIEN Position          */
+#define I2S_IEN_CH5ZCIEN_Msk             (0x1ul << I2S_IEN_CH5ZCIEN_Pos)                   /*!< I2S_T::IEN: CH5ZCIEN Mask              */
+
+#define I2S_IEN_CH6ZCIEN_Pos             (22)                                              /*!< I2S_T::IEN: CH6ZCIEN Position          */
+#define I2S_IEN_CH6ZCIEN_Msk             (0x1ul << I2S_IEN_CH6ZCIEN_Pos)                   /*!< I2S_T::IEN: CH6ZCIEN Mask              */
+
+#define I2S_IEN_CH7ZCIEN_Pos             (23)                                              /*!< I2S_T::IEN: CH7ZCIEN Position          */
+#define I2S_IEN_CH7ZCIEN_Msk             (0x1ul << I2S_IEN_CH7ZCIEN_Pos)                   /*!< I2S_T::IEN: CH7ZCIEN Mask              */
+
+#define I2S_STATUS0_I2SINT_Pos           (0)                                               /*!< I2S_T::STATUS0: I2SINT Position        */
+#define I2S_STATUS0_I2SINT_Msk           (0x1ul << I2S_STATUS0_I2SINT_Pos)                 /*!< I2S_T::STATUS0: I2SINT Mask            */
+
+#define I2S_STATUS0_I2SRXINT_Pos         (1)                                               /*!< I2S_T::STATUS0: I2SRXINT Position      */
+#define I2S_STATUS0_I2SRXINT_Msk         (0x1ul << I2S_STATUS0_I2SRXINT_Pos)               /*!< I2S_T::STATUS0: I2SRXINT Mask          */
+
+#define I2S_STATUS0_I2STXINT_Pos         (2)                                               /*!< I2S_T::STATUS0: I2STXINT Position      */
+#define I2S_STATUS0_I2STXINT_Msk         (0x1ul << I2S_STATUS0_I2STXINT_Pos)               /*!< I2S_T::STATUS0: I2STXINT Mask          */
+
+#define I2S_STATUS0_DATACH_Pos           (3)                                               /*!< I2S_T::STATUS0: DATACH Position        */
+#define I2S_STATUS0_DATACH_Msk           (0x7ul << I2S_STATUS0_DATACH_Pos)                 /*!< I2S_T::STATUS0: DATACH Mask            */
+
+#define I2S_STATUS0_RXUDIF_Pos           (8)                                               /*!< I2S_T::STATUS0: RXUDIF Position        */
+#define I2S_STATUS0_RXUDIF_Msk           (0x1ul << I2S_STATUS0_RXUDIF_Pos)                 /*!< I2S_T::STATUS0: RXUDIF Mask            */
+
+#define I2S_STATUS0_RXOVIF_Pos           (9)                                               /*!< I2S_T::STATUS0: RXOVIF Position        */
+#define I2S_STATUS0_RXOVIF_Msk           (0x1ul << I2S_STATUS0_RXOVIF_Pos)                 /*!< I2S_T::STATUS0: RXOVIF Mask            */
+
+#define I2S_STATUS0_RXTHIF_Pos           (10)                                              /*!< I2S_T::STATUS0: RXTHIF Position        */
+#define I2S_STATUS0_RXTHIF_Msk           (0x1ul << I2S_STATUS0_RXTHIF_Pos)                 /*!< I2S_T::STATUS0: RXTHIF Mask            */
+
+#define I2S_STATUS0_RXFULL_Pos           (11)                                              /*!< I2S_T::STATUS0: RXFULL Position        */
+#define I2S_STATUS0_RXFULL_Msk           (0x1ul << I2S_STATUS0_RXFULL_Pos)                 /*!< I2S_T::STATUS0: RXFULL Mask            */
+
+#define I2S_STATUS0_RXEMPTY_Pos          (12)                                              /*!< I2S_T::STATUS0: RXEMPTY Position       */
+#define I2S_STATUS0_RXEMPTY_Msk          (0x1ul << I2S_STATUS0_RXEMPTY_Pos)                /*!< I2S_T::STATUS0: RXEMPTY Mask           */
+
+#define I2S_STATUS0_TXUDIF_Pos           (16)                                              /*!< I2S_T::STATUS0: TXUDIF Position        */
+#define I2S_STATUS0_TXUDIF_Msk           (0x1ul << I2S_STATUS0_TXUDIF_Pos)                 /*!< I2S_T::STATUS0: TXUDIF Mask            */
+
+#define I2S_STATUS0_TXOVIF_Pos           (17)                                              /*!< I2S_T::STATUS0: TXOVIF Position        */
+#define I2S_STATUS0_TXOVIF_Msk           (0x1ul << I2S_STATUS0_TXOVIF_Pos)                 /*!< I2S_T::STATUS0: TXOVIF Mask            */
+
+#define I2S_STATUS0_TXTHIF_Pos           (18)                                              /*!< I2S_T::STATUS0: TXTHIF Position        */
+#define I2S_STATUS0_TXTHIF_Msk           (0x1ul << I2S_STATUS0_TXTHIF_Pos)                 /*!< I2S_T::STATUS0: TXTHIF Mask            */
+
+#define I2S_STATUS0_TXFULL_Pos           (19)                                              /*!< I2S_T::STATUS0: TXFULL Position        */
+#define I2S_STATUS0_TXFULL_Msk           (0x1ul << I2S_STATUS0_TXFULL_Pos)                 /*!< I2S_T::STATUS0: TXFULL Mask            */
+
+#define I2S_STATUS0_TXEMPTY_Pos          (20)                                              /*!< I2S_T::STATUS0: TXEMPTY Position       */
+#define I2S_STATUS0_TXEMPTY_Msk          (0x1ul << I2S_STATUS0_TXEMPTY_Pos)                /*!< I2S_T::STATUS0: TXEMPTY Mask           */
+
+#define I2S_STATUS0_TXBUSY_Pos           (21)                                              /*!< I2S_T::STATUS0: TXBUSY Position        */
+#define I2S_STATUS0_TXBUSY_Msk           (0x1ul << I2S_STATUS0_TXBUSY_Pos)                 /*!< I2S_T::STATUS0: TXBUSY Mask            */
+
+#define I2S_TXFIFO_TXFIFO_Pos            (0)                                               /*!< I2S_T::TXFIFO: TXFIFO Position         */
+#define I2S_TXFIFO_TXFIFO_Msk            (0xfffffffful << I2S_TXFIFO_TXFIFO_Pos)           /*!< I2S_T::TXFIFO: TXFIFO Mask             */
+
+#define I2S_RXFIFO_RXFIFO_Pos            (0)                                               /*!< I2S_T::RXFIFO: RXFIFO Position         */
+#define I2S_RXFIFO_RXFIFO_Msk            (0xfffffffful << I2S_RXFIFO_RXFIFO_Pos)           /*!< I2S_T::RXFIFO: RXFIFO Mask             */
+
+#define I2S_CTL1_CH0ZCEN_Pos             (0)                                               /*!< I2S_T::CTL1: CH0ZCEN Position          */
+#define I2S_CTL1_CH0ZCEN_Msk             (0x1ul << I2S_CTL1_CH0ZCEN_Pos)                   /*!< I2S_T::CTL1: CH0ZCEN Mask              */
+
+#define I2S_CTL1_CH1ZCEN_Pos             (1)                                               /*!< I2S_T::CTL1: CH1ZCEN Position          */
+#define I2S_CTL1_CH1ZCEN_Msk             (0x1ul << I2S_CTL1_CH1ZCEN_Pos)                   /*!< I2S_T::CTL1: CH1ZCEN Mask              */
+
+#define I2S_CTL1_CH2ZCEN_Pos             (2)                                               /*!< I2S_T::CTL1: CH2ZCEN Position          */
+#define I2S_CTL1_CH2ZCEN_Msk             (0x1ul << I2S_CTL1_CH2ZCEN_Pos)                   /*!< I2S_T::CTL1: CH2ZCEN Mask              */
+
+#define I2S_CTL1_CH3ZCEN_Pos             (3)                                               /*!< I2S_T::CTL1: CH3ZCEN Position          */
+#define I2S_CTL1_CH3ZCEN_Msk             (0x1ul << I2S_CTL1_CH3ZCEN_Pos)                   /*!< I2S_T::CTL1: CH3ZCEN Mask              */
+
+#define I2S_CTL1_CH4ZCEN_Pos             (4)                                               /*!< I2S_T::CTL1: CH4ZCEN Position          */
+#define I2S_CTL1_CH4ZCEN_Msk             (0x1ul << I2S_CTL1_CH4ZCEN_Pos)                   /*!< I2S_T::CTL1: CH4ZCEN Mask              */
+
+#define I2S_CTL1_CH5ZCEN_Pos             (5)                                               /*!< I2S_T::CTL1: CH5ZCEN Position          */
+#define I2S_CTL1_CH5ZCEN_Msk             (0x1ul << I2S_CTL1_CH5ZCEN_Pos)                   /*!< I2S_T::CTL1: CH5ZCEN Mask              */
+
+#define I2S_CTL1_CH6ZCEN_Pos             (6)                                               /*!< I2S_T::CTL1: CH6ZCEN Position          */
+#define I2S_CTL1_CH6ZCEN_Msk             (0x1ul << I2S_CTL1_CH6ZCEN_Pos)                   /*!< I2S_T::CTL1: CH6ZCEN Mask              */
+
+#define I2S_CTL1_CH7ZCEN_Pos             (7)                                               /*!< I2S_T::CTL1: CH7ZCEN Position          */
+#define I2S_CTL1_CH7ZCEN_Msk             (0x1ul << I2S_CTL1_CH7ZCEN_Pos)                   /*!< I2S_T::CTL1: CH7ZCEN Mask              */
+
+#define I2S_CTL1_TXTH_Pos                (8)                                               /*!< I2S_T::CTL1: TXTH Position             */
+#define I2S_CTL1_TXTH_Msk                (0xful << I2S_CTL1_TXTH_Pos)                      /*!< I2S_T::CTL1: TXTH Mask                 */
+
+#define I2S_CTL1_RXTH_Pos                (16)                                              /*!< I2S_T::CTL1: RXTH Position             */
+#define I2S_CTL1_RXTH_Msk                (0xful << I2S_CTL1_RXTH_Pos)                      /*!< I2S_T::CTL1: RXTH Mask                 */
+
+#define I2S_CTL1_PBWIDTH_Pos             (24)                                              /*!< I2S_T::CTL1: PBWIDTH Position          */
+#define I2S_CTL1_PBWIDTH_Msk             (0x1ul << I2S_CTL1_PBWIDTH_Pos)                   /*!< I2S_T::CTL1: PBWIDTH Mask              */
+
+#define I2S_CTL1_PB16ORD_Pos             (25)                                              /*!< I2S_T::CTL1: PB16ORD Position          */
+#define I2S_CTL1_PB16ORD_Msk             (0x1ul << I2S_CTL1_PB16ORD_Pos)                   /*!< I2S_T::CTL1: PB16ORD Mask              */
+
+#define I2S_STATUS1_CH0ZCIF_Pos          (0)                                               /*!< I2S_T::STATUS1: CH0ZCIF Position       */
+#define I2S_STATUS1_CH0ZCIF_Msk          (0x1ul << I2S_STATUS1_CH0ZCIF_Pos)                /*!< I2S_T::STATUS1: CH0ZCIF Mask           */
+
+#define I2S_STATUS1_CH1ZCIF_Pos          (1)                                               /*!< I2S_T::STATUS1: CH1ZCIF Position       */
+#define I2S_STATUS1_CH1ZCIF_Msk          (0x1ul << I2S_STATUS1_CH1ZCIF_Pos)                /*!< I2S_T::STATUS1: CH1ZCIF Mask           */
+
+#define I2S_STATUS1_CH2ZCIF_Pos          (2)                                               /*!< I2S_T::STATUS1: CH2ZCIF Position       */
+#define I2S_STATUS1_CH2ZCIF_Msk          (0x1ul << I2S_STATUS1_CH2ZCIF_Pos)                /*!< I2S_T::STATUS1: CH2ZCIF Mask           */
+
+#define I2S_STATUS1_CH3ZCIF_Pos          (3)                                               /*!< I2S_T::STATUS1: CH3ZCIF Position       */
+#define I2S_STATUS1_CH3ZCIF_Msk          (0x1ul << I2S_STATUS1_CH3ZCIF_Pos)                /*!< I2S_T::STATUS1: CH3ZCIF Mask           */
+
+#define I2S_STATUS1_CH4ZCIF_Pos          (4)                                               /*!< I2S_T::STATUS1: CH4ZCIF Position       */
+#define I2S_STATUS1_CH4ZCIF_Msk          (0x1ul << I2S_STATUS1_CH4ZCIF_Pos)                /*!< I2S_T::STATUS1: CH4ZCIF Mask           */
+
+#define I2S_STATUS1_CH5ZCIF_Pos          (5)                                               /*!< I2S_T::STATUS1: CH5ZCIF Position       */
+#define I2S_STATUS1_CH5ZCIF_Msk          (0x1ul << I2S_STATUS1_CH5ZCIF_Pos)                /*!< I2S_T::STATUS1: CH5ZCIF Mask           */
+
+#define I2S_STATUS1_CH6ZCIF_Pos          (6)                                               /*!< I2S_T::STATUS1: CH6ZCIF Position       */
+#define I2S_STATUS1_CH6ZCIF_Msk          (0x1ul << I2S_STATUS1_CH6ZCIF_Pos)                /*!< I2S_T::STATUS1: CH6ZCIF Mask           */
+
+#define I2S_STATUS1_CH7ZCIF_Pos          (7)                                               /*!< I2S_T::STATUS1: CH7ZCIF Position       */
+#define I2S_STATUS1_CH7ZCIF_Msk          (0x1ul << I2S_STATUS1_CH7ZCIF_Pos)                /*!< I2S_T::STATUS1: CH7ZCIF Mask           */
+
+#define I2S_STATUS1_TXCNT_Pos            (8)                                               /*!< I2S_T::STATUS1: TXCNT Position         */
+#define I2S_STATUS1_TXCNT_Msk            (0x1ful << I2S_STATUS1_TXCNT_Pos)                 /*!< I2S_T::STATUS1: TXCNT Mask             */
+
+#define I2S_STATUS1_RXCNT_Pos            (16)                                              /*!< I2S_T::STATUS1: RXCNT Position         */
+#define I2S_STATUS1_RXCNT_Msk            (0x1ful << I2S_STATUS1_RXCNT_Pos)                 /*!< I2S_T::STATUS1: RXCNT Mask             */
+
+/**@}*/ /* I2S_CONST */
+/**@}*/ /* end of I2S register group */
+/**@}*/ /* end of REGISTER group */
+
+#endif /* __I2S_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/keystore_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/keystore_reg.h
new file mode 100644
index 0000000000..f7d20adda5
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/keystore_reg.h
@@ -0,0 +1,384 @@
+/**************************************************************************//**
+ * @file     keystore_reg.h
+ * @version  V1.00
+ * @brief    Key store register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __KEYSTORE_REG_H__
+#define __KEYSTORE_REG_H__
+
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+
+/*---------------------- Key Store -------------------------*/
+/**
+    @addtogroup KS Key Store(KS)
+    Memory Mapped Structure for KS Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var KS_T::CTL
+     * Offset: 0x00  Key Store Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |START     |Key Store Start Control Bit
+     * |        |          |0 = No operation.
+     * |        |          |1 = Start the setted operation.
+     * |[3:1]   |OPMODE    |Key Store Operation Mode
+     * |        |          |000 = Read operation.
+     * |        |          |001 = Create operation.
+     * |        |          |010 = Erase one key operation (only for key is in SRAM).
+     * |        |          |011 = Erase all keys operation (only for SRAM and Flash).
+     * |        |          |100 = Revoke key operation.
+     * |        |          |101 = Data Remanence prevention opertation (only for SRAM).
+     * |        |          |Others = reserved.
+     * |[7]     |CONT      |Read/Write Key Continue Bit
+     * |        |          |0 = Read/Write key operation is not continuous to previous operation.
+     * |        |          |1 = Read/Write key operation is continuous to previous operation.
+     * |[8]     |INIT      |Key Store Initialization
+     * |        |          |User should to check BUSY(KS_STS[2]) is 0, and then write 1 to this bit and START(KS_CTL[0[), the Key Store will start to be initialized.
+     * |        |          |After KeyStore is initialized, INIT will be cleared.
+     * |        |          |Note: Before executing INIT, user must to checks KS(SYS_SRAMPC1) is 00.
+     * |[10]    |SILENT    |Silent Access Enable Bit
+     * |        |          |0 = Silent Access Disabled.
+     * |        |          |1 = Silent Access Enabled.
+     * |[11]    |SCMB      |Data Scramble Enable Bit
+     * |        |          |0 = Data Scramble Disabled.
+     * |        |          |1 = Data Scramble Enabled.
+     * |[15]    |IEN       |Key Store Interrupt Enable Bit
+     * |        |          |0 = Key Store Interrupt Disabled.
+     * |        |          |1 = Key Store Interrupt Enabled.
+     * @var KS_T::METADATA
+     * Offset: 0x04  Key Store Metadata Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SEC       |Secure Key Selection Bit
+     * |        |          |0 = Set key as the non-secure key.
+     * |        |          |1 = Set key as the secure key.
+     * |[1]     |PRIV      |Privilege Key Selection Bit
+     * |        |          |0 = Set key as the non-privilege key.
+     * |        |          |1 = Set key as the privilege key.
+     * |[2]     |READABLE  |Key Readable Control Bit
+     * |        |          |0 = key is un-readable.
+     * |        |          |1 = key is readable.
+     * |[3]     |RVK       |Key Revoke Control Bit
+     * |        |          |0 = Key current selected will not be changed.
+     * |        |          |1 = key current selected will be change to revoked state.
+     * |[4]     |BS        |Booting State Selection Bit
+     * |        |          |0 = Set key used at all state.
+     * |        |          |1 = Set key used at boot loader state 1 (BL1 state).
+     * |[12:8]  |SIZE      |Key Size Selection Bits
+     * |        |          |00000 = 128 bits.
+     * |        |          |00001 = 163 bits.
+     * |        |          |00010 = 192 bits.
+     * |        |          |00011 = 224 bits.
+     * |        |          |00100 = 233 bits.
+     * |        |          |00101 = 255 bits.
+     * |        |          |00110 = 256 bits.
+     * |        |          |00111 = 283 bits.
+     * |        |          |01000 = 384 bits.
+     * |        |          |01001 = 409 bits.
+     * |        |          |01010 = 512 bits.
+     * |        |          |01011 = 521 bits.
+     * |        |          |01100 = 571 bits.
+     * |        |          |10000 = 1024 bits.
+     * |        |          |10001 = 1536 bits.
+     * |        |          |10010 = 2048 bits.
+     * |        |          |10011 = 3072 bits.
+     * |        |          |10100 = 4096 bits.
+     * |        |          |Others = reserved.
+     * |[18:16] |OWNER     |Key Owner Selection Bits
+     * |        |          |000 = Only for AES used.
+     * |        |          |001 = Only for HMAC engine used.
+     * |        |          |010 = Only for RSA engine exponential used (private key).
+     * |        |          |011 = Only for RSA engine middle data used.
+     * |        |          |100 = Only for ECC engine used.
+     * |        |          |101 = Only for CPU engine use.
+     * |        |          |Others = reserved.
+     * |[25:20] |NUMBER    |Key Number
+     * |        |          |Before read or erase one key operation starts, user should write the key number to be operated
+     * |        |          |When create operation is finished, user can read these bits to get its key number.
+     * |[31:30] |DST       |Key Location Selection Bits
+     * |        |          |00 = Key is in SRAM.
+     * |        |          |01 = Key is in Flash.
+     * |        |          |10 = Key is in OTP.
+     * |        |          |Others = reserved.
+     * @var KS_T::STS
+     * Offset: 0x08  Key Store Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |IF        |Key Store Finish Interrupt Flag
+     * |        |          |This bit is cleared by writing 1 and it has no effect by writing 0.
+     * |        |          |0 = No Key Store interrupt.
+     * |        |          |1 = Key Store operation done interrupt.
+     * |[1]     |EIF       |Key Store Error Flag
+     * |        |          |This bit is cleared by writing 1 and it has no effect by writing 0.
+     * |        |          |0 = No Key Store error.
+     * |        |          |1 = Key Store error interrupt.
+     * |[2]     |BUSY      |Key Store Busy Flag (RO)
+     * |        |          |0 = KeyStore is idle or finished.
+     * |        |          |1 = KeyStore is busy.
+     * |[3]     |SRAMFULL  |Key Storage at SRAM Full Status Bit (RO)
+     * |        |          |0 = Key Storage at SRAM is not full.
+     * |        |          |1 = Key Storage at SRAM is full.
+     * |[4]     |FLASHFULL |Key Storage at Flash Full Status Bit (RO)
+     * |        |          |0 = Key Storage at Flash is not full.
+     * |        |          |1 = Key Storage at Flash is full.
+     * |[7]     |INITDONE  |Key Store Initialization Done Status (RO)
+     * |        |          |0 = Key Store is un-initialized.
+     * |        |          |1 = Key Store is initialized.
+     * |[8]     |RAMINV    |Key Store SRAM Invert Status (RO)
+     * |        |          |0 = Key Store key in SRAM is normal.
+     * |        |          |1 = Key Store key in SRAM is inverted.
+     * @var KS_T::REMAIN
+     * Offset: 0x0C  Key Store Remaining Space Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[12:0]  |RRMNG     |Key Store SRAM Remaining Space
+     * |        |          |The RRMNG shows the remaining byte count space for SRAM.
+     * |[27:16] |FRMNG     |Key Store Flash Remaining Space
+     * |        |          |The FRMNG shows the remaining byte count space for Flash.
+     * @var KS_T::SCMBKEY
+     * Offset: 0x10-0x1C  Key Store Scramble Key Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SCMBKEY   |Key Store Scramble Key
+     * |        |          |When SCMB(KS_CTL[]) is set to 1, user should write the scramble key in this register before new key stores in Key Store
+     * |        |          |If user does not write the scramble key in this register, the Key Store will use previous scramble key to execute data scramble function.
+     * @var KS_T::KEY
+     * Offset: 0x20-0x3C  Key Store Entry Key Word Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |KEY       |Key Data
+     * |        |          |The register will be cleared if the Key Store executes the write operation or CPU completes the reading key.
+     * @var KS_T::OTPSTS
+     * Offset: 0x40  Key Store OTP Keys Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |KEY0      |OTP Key 0 Used Status
+     * |        |          |0 = OTP key 0 is unused.
+     * |        |          |1 = OTP key 0 is used.
+     * |        |          |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization.
+     * |[1]     |KEY1      |OTP Key 1 Used Status
+     * |        |          |0 = OTP key 1 is unused.
+     * |        |          |1 = OTP key 1 is used.
+     * |        |          |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization.
+     * |[2]     |KEY2      |OTP Key 2 Used Status
+     * |        |          |0 = OTP key 2 is unused.
+     * |        |          |1 = OTP key 2 is used.
+     * |        |          |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization.
+     * |[3]     |KEY3      |OTP Key 3 Used Status
+     * |        |          |0 = OTP key 3 is unused.
+     * |        |          |1 = OTP key 3 is used.
+     * |        |          |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization.
+     * |[4]     |KEY4      |OTP Key 4 Used Status
+     * |        |          |0 = OTP key 4 is unused.
+     * |        |          |1 = OTP key 4 is used.
+     * |        |          |Note: If chip is changed to RMA stage, existing key will be revoked after initialization.
+     * |[5]     |KEY5      |OTP Key 5 Used Status
+     * |        |          |0 = OTP key 5 is unused.
+     * |        |          |1 = OTP key 5 is used.
+     * |        |          |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization.
+     * |[6]     |KEY6      |OTP Key 6 Used Status
+     * |        |          |0 = OTP key 6 is unused.
+     * |        |          |1 = OTP key 6 is used.
+     * |        |          |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization.
+     * |[7]     |KEY7      |OTP Key 7 Used Status
+     * |        |          |0 = OTP key 7 is unused.
+     * |        |          |1 = OTP key 7 is used.
+     * |        |          |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization.
+     * @var KS_T::REMKCNT
+     * Offset: 0x44  Key Store Remaining Key Count Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[5:0]   |RRMKCNT   |Key Store SRAM Remaining Key Count
+     * |        |          |The RRMKCNT shows the remaining key count for SRAM.
+     * |[21:16] |FRMKCNT   |Key Store Flash Remaining Key Count
+     * |        |          |The FRMKCNT shows the remaining key count for Flash.
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] Key Store Control Register                                       */
+    __IO uint32_t METADATA;              /*!< [0x0004] Key Store Metadata Register                                      */
+    __IO uint32_t STS;                   /*!< [0x0008] Key Store Status Register                                        */
+    __I  uint32_t REMAIN;                /*!< [0x000c] Key Store Remaining Space Register                               */
+    __IO uint32_t SCMBKEY[4];            /*!< [0x0010 ~ 0x001c] Key Store Scramble Key Word 0 Register                  */
+    __IO uint32_t KEY[8];                /*!< [0x0020 ~ 0x003c] Key Store Entry Key Word 0 Register                     */
+    __I  uint32_t OTPSTS;                /*!< [0x0040] Key Store OTP Keys Status Register                               */
+    __I  uint32_t REMKCNT;               /*!< [0x0044] Key Store Remaining Key Count Register                           */
+
+} KS_T;
+
+/**
+    @addtogroup KS_CONST KS Bit Field Definition
+    Constant Definitions for KS Controller
+  @{
+*/
+
+#define KS_CTL_START_Pos                 (0)                                               /*!< KS_T::CTL: START Position              */
+#define KS_CTL_START_Msk                 (0x1ul << KS_CTL_START_Pos)                       /*!< KS_T::CTL: START Mask                  */
+
+#define KS_CTL_OPMODE_Pos                (1)                                               /*!< KS_T::CTL: OPMODE Position             */
+#define KS_CTL_OPMODE_Msk                (0x7ul << KS_CTL_OPMODE_Pos)                      /*!< KS_T::CTL: OPMODE Mask                 */
+
+#define KS_CTL_CONT_Pos                  (7)                                               /*!< KS_T::CTL: CONT Position               */
+#define KS_CTL_CONT_Msk                  (0x1ul << KS_CTL_CONT_Pos)                        /*!< KS_T::CTL: CONT Mask                   */
+
+#define KS_CTL_INIT_Pos                  (8)                                               /*!< KS_T::CTL: INIT Position               */
+#define KS_CTL_INIT_Msk                  (0x1ul << KS_CTL_INIT_Pos)                        /*!< KS_T::CTL: INIT Mask                   */
+
+#define KS_CTL_SILENT_Pos                (10)                                              /*!< KS_T::CTL: SILENT Position             */
+#define KS_CTL_SILENT_Msk                (0x1ul << KS_CTL_SILENT_Pos)                      /*!< KS_T::CTL: SILENT Mask                 */
+
+#define KS_CTL_SCMB_Pos                  (11)                                              /*!< KS_T::CTL: SCMB Position               */
+#define KS_CTL_SCMB_Msk                  (0x1ul << KS_CTL_SCMB_Pos)                        /*!< KS_T::CTL: SCMB Mask                   */
+
+#define KS_CTL_IEN_Pos                   (15)                                              /*!< KS_T::CTL: IEN Position                */
+#define KS_CTL_IEN_Msk                   (0x1ul << KS_CTL_IEN_Pos)                         /*!< KS_T::CTL: IEN Mask                    */
+
+#define KS_METADATA_SEC_Pos              (0)                                               /*!< KS_T::METADATA: SEC Position           */
+#define KS_METADATA_SEC_Msk              (0x1ul << KS_METADATA_SEC_Pos)                    /*!< KS_T::METADATA: SEC Mask               */
+
+#define KS_METADATA_PRIV_Pos             (1)                                               /*!< KS_T::METADATA: PRIV Position          */
+#define KS_METADATA_PRIV_Msk             (0x1ul << KS_METADATA_PRIV_Pos)                   /*!< KS_T::METADATA: PRIV Mask              */
+
+#define KS_METADATA_READABLE_Pos         (2)                                               /*!< KS_T::METADATA: READABLE Position      */
+#define KS_METADATA_READABLE_Msk         (0x1ul << KS_METADATA_READABLE_Pos)               /*!< KS_T::METADATA: READABLE Mask          */
+
+#define KS_METADATA_RVK_Pos              (3)                                               /*!< KS_T::METADATA: RVK Position           */
+#define KS_METADATA_RVK_Msk              (0x1ul << KS_METADATA_RVK_Pos)                    /*!< KS_T::METADATA: RVK Mask               */
+
+#define KS_METADATA_BS_Pos               (4)                                               /*!< KS_T::METADATA: BS Position            */
+#define KS_METADATA_BS_Msk               (0x1ul << KS_METADATA_BS_Pos)                     /*!< KS_T::METADATA: BS Mask                */
+
+#define KS_METADATA_SIZE_Pos             (8)                                               /*!< KS_T::METADATA: SIZE Position          */
+#define KS_METADATA_SIZE_Msk             (0x1ful << KS_METADATA_SIZE_Pos)                  /*!< KS_T::METADATA: SIZE Mask              */
+
+#define KS_METADATA_OWNER_Pos            (16)                                              /*!< KS_T::METADATA: OWNER Position         */
+#define KS_METADATA_OWNER_Msk            (0x7ul << KS_METADATA_OWNER_Pos)                  /*!< KS_T::METADATA: OWNER Mask             */
+
+#define KS_METADATA_NUMBER_Pos           (20)                                              /*!< KS_T::METADATA: NUMBER Position        */
+#define KS_METADATA_NUMBER_Msk           (0x3ful << KS_METADATA_NUMBER_Pos)                /*!< KS_T::METADATA: NUMBER Mask            */
+
+#define KS_METADATA_DST_Pos              (30)                                              /*!< KS_T::METADATA: DST Position           */
+#define KS_METADATA_DST_Msk              (0x3ul << KS_METADATA_DST_Pos)                    /*!< KS_T::METADATA: DST Mask               */
+
+#define KS_STS_IF_Pos                    (0)                                               /*!< KS_T::STS: IF Position                 */
+#define KS_STS_IF_Msk                    (0x1ul << KS_STS_IF_Pos)                          /*!< KS_T::STS: IF Mask                     */
+
+#define KS_STS_EIF_Pos                   (1)                                               /*!< KS_T::STS: EIF Position                */
+#define KS_STS_EIF_Msk                   (0x1ul << KS_STS_EIF_Pos)                         /*!< KS_T::STS: EIF Mask                    */
+
+#define KS_STS_BUSY_Pos                  (2)                                               /*!< KS_T::STS: BUSY Position               */
+#define KS_STS_BUSY_Msk                  (0x1ul << KS_STS_BUSY_Pos)                        /*!< KS_T::STS: BUSY Mask                   */
+
+#define KS_STS_SRAMFULL_Pos              (3)                                               /*!< KS_T::STS: SRAMFULL Position           */
+#define KS_STS_SRAMFULL_Msk              (0x1ul << KS_STS_SRAMFULL_Pos)                    /*!< KS_T::STS: SRAMFULL Mask               */
+
+#define KS_STS_FLASHFULL_Pos             (4)                                               /*!< KS_T::STS: FLASHFULL Position          */
+#define KS_STS_FLASHFULL_Msk             (0x1ul << KS_STS_FLASHFULL_Pos)                   /*!< KS_T::STS: FLASHFULL Mask              */
+
+#define KS_STS_INITDONE_Pos              (7)                                               /*!< KS_T::STS: INITDONE Position           */
+#define KS_STS_INITDONE_Msk              (0x1ul << KS_STS_INITDONE_Pos)                    /*!< KS_T::STS: INITDONE Mask               */
+
+#define KS_STS_RAMINV_Pos                (8)                                               /*!< KS_T::STS: RAMINV Position             */
+#define KS_STS_RAMINV_Msk                (0x1ul << KS_STS_RAMINV_Pos)                      /*!< KS_T::STS: RAMINV Mask                 */
+
+#define KS_REMAIN_RRMNG_Pos              (0)                                               /*!< KS_T::REMAIN: RRMNG Position           */
+#define KS_REMAIN_RRMNG_Msk              (0x1ffful << KS_REMAIN_RRMNG_Pos)                 /*!< KS_T::REMAIN: RRMNG Mask               */
+
+#define KS_REMAIN_FRMNG_Pos              (16)                                              /*!< KS_T::REMAIN: FRMNG Position           */
+#define KS_REMAIN_FRMNG_Msk              (0xffful << KS_REMAIN_FRMNG_Pos)                  /*!< KS_T::REMAIN: FRMNG Mask               */
+
+#define KS_SCMBKEY0_SCMBKEY_Pos          (0)                                               /*!< KS_T::SCMBKEY0: SCMBKEY Position       */
+#define KS_SCMBKEY0_SCMBKEY_Msk          (0xfffffffful << KS_SCMBKEY0_SCMBKEY_Pos)         /*!< KS_T::SCMBKEY0: SCMBKEY Mask           */
+
+#define KS_SCMBKEY1_SCMBKEY_Pos          (0)                                               /*!< KS_T::SCMBKEY1: SCMBKEY Position       */
+#define KS_SCMBKEY1_SCMBKEY_Msk          (0xfffffffful << KS_SCMBKEY1_SCMBKEY_Pos)         /*!< KS_T::SCMBKEY1: SCMBKEY Mask           */
+
+#define KS_SCMBKEY2_SCMBKEY_Pos          (0)                                               /*!< KS_T::SCMBKEY2: SCMBKEY Position       */
+#define KS_SCMBKEY2_SCMBKEY_Msk          (0xfffffffful << KS_SCMBKEY2_SCMBKEY_Pos)         /*!< KS_T::SCMBKEY2: SCMBKEY Mask           */
+
+#define KS_SCMBKEY3_SCMBKEY_Pos          (0)                                               /*!< KS_T::SCMBKEY3: SCMBKEY Position       */
+#define KS_SCMBKEY3_SCMBKEY_Msk          (0xfffffffful << KS_SCMBKEY3_SCMBKEY_Pos)         /*!< KS_T::SCMBKEY3: SCMBKEY Mask           */
+
+#define KS_KEY0_KEY_Pos                  (0)                                               /*!< KS_T::KEY0: KEY Position               */
+#define KS_KEY0_KEY_Msk                  (0xfffffffful << KS_KEY0_KEY_Pos)                 /*!< KS_T::KEY0: KEY Mask                   */
+
+#define KS_KEY1_KEY_Pos                  (0)                                               /*!< KS_T::KEY1: KEY Position               */
+#define KS_KEY1_KEY_Msk                  (0xfffffffful << KS_KEY1_KEY_Pos)                 /*!< KS_T::KEY1: KEY Mask                   */
+
+#define KS_KEY2_KEY_Pos                  (0)                                               /*!< KS_T::KEY2: KEY Position               */
+#define KS_KEY2_KEY_Msk                  (0xfffffffful << KS_KEY2_KEY_Pos)                 /*!< KS_T::KEY2: KEY Mask                   */
+
+#define KS_KEY3_KEY_Pos                  (0)                                               /*!< KS_T::KEY3: KEY Position               */
+#define KS_KEY3_KEY_Msk                  (0xfffffffful << KS_KEY3_KEY_Pos)                 /*!< KS_T::KEY3: KEY Mask                   */
+
+#define KS_KEY4_KEY_Pos                  (0)                                               /*!< KS_T::KEY4: KEY Position               */
+#define KS_KEY4_KEY_Msk                  (0xfffffffful << KS_KEY4_KEY_Pos)                 /*!< KS_T::KEY4: KEY Mask                   */
+
+#define KS_KEY5_KEY_Pos                  (0)                                               /*!< KS_T::KEY5: KEY Position               */
+#define KS_KEY5_KEY_Msk                  (0xfffffffful << KS_KEY5_KEY_Pos)                 /*!< KS_T::KEY5: KEY Mask                   */
+
+#define KS_KEY6_KEY_Pos                  (0)                                               /*!< KS_T::KEY6: KEY Position               */
+#define KS_KEY6_KEY_Msk                  (0xfffffffful << KS_KEY6_KEY_Pos)                 /*!< KS_T::KEY6: KEY Mask                   */
+
+#define KS_KEY7_KEY_Pos                  (0)                                               /*!< KS_T::KEY7: KEY Position               */
+#define KS_KEY7_KEY_Msk                  (0xfffffffful << KS_KEY7_KEY_Pos)                 /*!< KS_T::KEY7: KEY Mask                   */
+
+#define KS_OTPSTS_KEY0_Pos               (0)                                               /*!< KS_T::OTPSTS: KEY0 Position            */
+#define KS_OTPSTS_KEY0_Msk               (0x1ul << KS_OTPSTS_KEY0_Pos)                     /*!< KS_T::OTPSTS: KEY0 Mask                */
+
+#define KS_OTPSTS_KEY1_Pos               (1)                                               /*!< KS_T::OTPSTS: KEY1 Position            */
+#define KS_OTPSTS_KEY1_Msk               (0x1ul << KS_OTPSTS_KEY1_Pos)                     /*!< KS_T::OTPSTS: KEY1 Mask                */
+
+#define KS_OTPSTS_KEY2_Pos               (2)                                               /*!< KS_T::OTPSTS: KEY2 Position            */
+#define KS_OTPSTS_KEY2_Msk               (0x1ul << KS_OTPSTS_KEY2_Pos)                     /*!< KS_T::OTPSTS: KEY2 Mask                */
+
+#define KS_OTPSTS_KEY3_Pos               (3)                                               /*!< KS_T::OTPSTS: KEY3 Position            */
+#define KS_OTPSTS_KEY3_Msk               (0x1ul << KS_OTPSTS_KEY3_Pos)                     /*!< KS_T::OTPSTS: KEY3 Mask                */
+
+#define KS_OTPSTS_KEY4_Pos               (4)                                               /*!< KS_T::OTPSTS: KEY4 Position            */
+#define KS_OTPSTS_KEY4_Msk               (0x1ul << KS_OTPSTS_KEY4_Pos)                     /*!< KS_T::OTPSTS: KEY4 Mask                */
+
+#define KS_OTPSTS_KEY5_Pos               (5)                                               /*!< KS_T::OTPSTS: KEY5 Position            */
+#define KS_OTPSTS_KEY5_Msk               (0x1ul << KS_OTPSTS_KEY5_Pos)                     /*!< KS_T::OTPSTS: KEY5 Mask                */
+
+#define KS_OTPSTS_KEY6_Pos               (6)                                               /*!< KS_T::OTPSTS: KEY6 Position            */
+#define KS_OTPSTS_KEY6_Msk               (0x1ul << KS_OTPSTS_KEY6_Pos)                     /*!< KS_T::OTPSTS: KEY6 Mask                */
+
+#define KS_OTPSTS_KEY7_Pos               (7)                                               /*!< KS_T::OTPSTS: KEY7 Position            */
+#define KS_OTPSTS_KEY7_Msk               (0x1ul << KS_OTPSTS_KEY7_Pos)                     /*!< KS_T::OTPSTS: KEY7 Mask                */
+
+#define KS_REMKCNT_RRMKCNT_Pos           (0)                                               /*!< KS_T::REMKCNT: RRMKCNT Position        */
+#define KS_REMKCNT_RRMKCNT_Msk           (0x3ful << KS_REMKCNT_RRMKCNT_Pos)                /*!< KS_T::REMKCNT: RRMKCNT Mask            */
+
+#define KS_REMKCNT_FRMKCNT_Pos           (16)                                              /*!< KS_T::REMKCNT: FRMKCNT Position        */
+#define KS_REMKCNT_FRMKCNT_Msk           (0x3ful << KS_REMKCNT_FRMKCNT_Pos)                /*!< KS_T::REMKCNT: FRMKCNT Mask            */
+
+
+/**@}*/ /* KS_CONST */
+/**@}*/ /* end of KS register group */
+
+
+/**@}*/ /* end of REGISTER group */
+
+#endif /* __KEYSTORE_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/lcd_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/lcd_reg.h
new file mode 100644
index 0000000000..2198e861fd
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/lcd_reg.h
@@ -0,0 +1,1050 @@
+/**************************************************************************//**
+ * @file     lcd_reg.h
+ * @version  V1.00
+ * @brief    LCD register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __LCD_REG_H__
+#define __LCD_REG_H__
+
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+
+/*---------------------- Liquid-Crystal Display -------------------------*/
+/**
+    @addtogroup LCD Liquid-Crystal Display(LCD)
+    Memory Mapped Structure for LCD Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var LCD_T::CTL
+     * Offset: 0x00  LCD Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |EN        |LCD Display Enable Bit
+     * |        |          |0 = LCD display function Disabled
+     * |        |          |1 = LCD display function Enabled
+     * |        |          |Note 1: When software writes 1 to this bit, the LCD Controller needs some synchronizing time to completely enable the LCD display function. Before that, the read value of this bit is still 0.
+     * |        |          |Note 2: When software writes 0 to this bit, the LCD Controller needs some synchronizing time to completely disable the LCD display function. Before that, the read value of this bit is still 1.
+     * |[31]    |SYNC      |LCD Enable/Disable Synchronizing Indicator (Read Only)
+     * |        |          |When software writes 0/1 to EN bit (LCD_CTL[0]), the LCD Controller needs some synchronizing time to completely disable/enable the LCD display function. During this time, this bit keeps at 1.
+     * |        |          |0 = LCD display function is completely Disabled/Enabled
+     * |        |          |1 = LCD display function is not yet completely Disabled/Enabled
+     * |        |          |Note 1: The synchronizing time to enable LCD display function is not constant. It is between one and two cycles of LCD_CLK.
+     * |        |          |Note 2: The LCD display function cannot be disabled until the end of a frame. So the maximum synchronizing time to disable LCD display function could be as long as one frame time.
+     * @var LCD_T::PCTL
+     * Offset: 0x04  LCD Panel Control Registerr
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |BIAS      |LCD Bias Level Selection
+     * |        |          |This field is used to select the bias level.
+     * |        |          |0 = Reserved
+     * |        |          |1 = 1/2 Bias
+     * |        |          |2 = 1/3 Bias
+     * |        |          |3 = 1/4 Bias
+     * |[4:2]   |DUTY      |LCD Duty Ratio Selection
+     * |        |          |This field is used to select the duty ratio.
+     * |        |          |0 = 1/1 Duty
+     * |        |          |1 = 1/2 Duty
+     * |        |          |2 = 1/3 Duty
+     * |        |          |3 = 1/4 Duty
+     * |        |          |4 = 1/5 Duty
+     * |        |          |5 = 1/6 Duty
+     * |        |          |6 = 1/7 Duty
+     * |        |          |7 = 1/8 Duty
+     * |[5]     |TYPE      |LCD Waveform Type Selection
+     * |        |          |This bit is used to select the waveform type.
+     * |        |          |0 = Type A
+     * |        |          |1 = Type B
+     * |[6]     |INV       |LCD Waveform Inverse
+     * |        |          |This bit is used to set the inverse LCD waveform.
+     * |        |          |0 = COM/SEG waveform is normal
+     * |        |          |1 = COM/SEG waveform is inversed
+     * |[17:8]  |FREQDIV   |LCD Operating Frequency Divider
+     * |        |          |The field is used to divide LCD_CLK to generate the LCD operating frequency.
+     * |        |          |LCD Operating Frequency = (LCD_CLK Frequency) / (FRRQDIV + 1).
+     * |        |          |Note 1: FREQDIV can be set from 0 to 1023, therefore, the fastest LCD operating frequency is equal to LCD_CLK frequency,
+     * |        |          |and the lowest LCD operating frequency is equal to LCD_CLK frequency divided by 1024.
+     * |        |          |Note 2: LCD frame rate is
+     * |        |          |(LCD Operating Frequency) x (Duty Ratio) x 1/2 for type A waveform, and
+     * |        |          |(LCD Operating Frequency) x (Duty Ratio) for type B waveform.
+     * |        |          |Example: Assume LCD operating frequency is 1 kHz, duty ratio is 1/4, then the LCD frame rate is
+     * |        |          |1 kHz x (1/4) x (1/2) = 128 Hz for type A waveform, and
+     * |        |          |1 kHz x (1/4) = 256 Hz for type B waveform.
+     * |[20:18] |CPVSEL    |LCD Operating Voltage (VLCD) Select (For Charge Pump Only)
+     * |        |          |This field is used to select the LCD operating voltage.
+     * |        |          |0 = 2.6 V
+     * |        |          |1 = 2.8 V
+     * |        |          |2 = 3.0 V
+     * |        |          |3 = 3.2 V
+     * |        |          |4 = 3.4 V
+     * |        |          |5 = 3.6 V
+     * |        |          |Others = (Reserved)
+     * |        |          |Note: This field is meaningful only if the VLCD source is the charge pump. Otherwise, this field is ignored.
+     * |[27:24] |CPVTUNE   |LCD Operating Voltage (VLCD) Fine Tuning (For Charge Pump Only)
+     * |        |          |This field is used to fine tune the LCD operating voltage.
+     * |        |          |0 = No tuning
+     * |        |          |1 = decrease by 1 unit of voltage
+     * |        |          |2 = decrease by 2 unit of voltage
+     * |        |          |3 = decrease by 3 unit of voltage
+     * |        |          |4 = decrease by 4 unit of voltage
+     * |        |          |5 = decrease by 5 unit of voltage
+     * |        |          |6 = decrease by 6 unit of voltage
+     * |        |          |7 = decrease by 7 unit of voltage
+     * |        |          |8 = increase by 8 units of voltage
+     * |        |          |9 = increase by 7 units of voltage
+     * |        |          |10 = increase by 6 units of voltage
+     * |        |          |11 = increase by 5 units of voltage
+     * |        |          |12 = increase by 4 units of voltage
+     * |        |          |13 = increase by 3 units of voltage
+     * |        |          |14 = increase by 2 units of voltage
+     * |        |          |15 = increase by 1 unit of voltage
+     * |        |          |Note 1: A unit of voltage is about 0.03 V.
+     * |        |          |Note 2: This field is meaningful only if the VLCD source is the charge pump. Otherwise, this field is ignored.
+     * @var LCD_T::FCTL
+     * Offset: 0x08  LCD Frame Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BLINK     |LCD Blinking Enable Bit
+     * |        |          |0 = LCD blinking function Disabled
+     * |        |          |1 = LCD blinking function Enabled
+     * |[17:8]  |FCV       |Frame Counting Value
+     * |        |          |This field indicates the maximum value that the frame counter can reach.
+     * |        |          |Note 1: The frame counter automatically increases by 1 at the end of every frame. When the counter reaches FCV, it will recounts from 0 at the end of the next frame.
+     * |        |          |At this moment, the hardware sets a dedicated flag to 1, and triggers a dedicated interrupt if it is enabled.
+     * |        |          |Note 2: For type B waveform, the frame counter increases at the end of odd frames, not even frames.
+     * |[27:24] |NFTIME    |Null Frame Time
+     * |        |          |This field is used to configure the length of a null frame.
+     * |        |          |One null frame time is (1 / LCD_FREQ) x NFTIME.
+     * |        |          |Note: All COM and SEG output voltages are 0 V during a null frame.
+     * |[31:28] |NFNUM     |Number of Frames Inserted By One Null Frame
+     * |        |          |This field is used to specify the number of continuous normal frames inserted by one null frame.
+     * |        |          |The number of continuous normal frames is (NFNUM + 1) frames.
+     * @var LCD_T::DCTL
+     * Offset: 0x0C  LCD Driving Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |VSRC      |LCD Operating Voltage (VLCD) Source
+     * |        |          |0 = VLCD Power
+     * |        |          |1 = AVDD Power
+     * |        |          |2 = Built-In Charge Pump
+     * |        |          |3 = None
+     * |        |          |Note: Whenever the LCD controller is disabled, all VLCD sources are automatically cut off.
+     * |[2]     |RESMODE   |Resistive Network Driving Mode
+     * |        |          |0 = Low-Drive Mode
+     * |        |          |1 = High-Drive Mode
+     * |[3]     |BUFEN     |Voltage Buffer Enable Bit
+     * |        |          |0 = Voltage Buffer Disabled
+     * |        |          |1 = Voltage Buffer Enabled
+     * |        |          |Note: When RESMODE = 1, the voltage buffers are automatically disabled. The setting of BUFEN bit is ignored.
+     * |[4]     |PSVEN     |Power Saving Mode Enable Bit
+     * |        |          |0 = Power Saving Mode Disabled
+     * |        |          |1 = Power Saving Mode Enabled
+     * |        |          |Note: when RESMODE = 0 and BUFEN = 0, the output drivers consumes the least driving current. In this case, the power saving mode is automatically disabled. The setting of PSVEN bit is ignored.
+     * |[5]     |PSVREV    |Power Saving Timing Reverse
+     * |        |          |When the timing is reversed, the original powe-saving period becomes no-power-saving, and the original no-power-saving period becomes power-saving.
+     * |        |          |0 = Timing of power saving is normal
+     * |        |          |1 = Timing of power saving is reversed
+     * |[11:8]  |PSVT1     |Power Saving "Enable Time" Setting
+     * |        |          |The "Enable Time" of the power saving mode is calculated as "Enable Time" = 15.26 us x (PSVT1 + 1),
+     * |        |          |where 15.26 us is the half-cycle time of LCD_CLK, whose frequency is about 32 kHz.
+     * |        |          |PSVT1 can be set as 0, 1, 2, ..., 15, so the minimum "Enable Time" is about 15.26 us, and the maximum "Enable Time" is about 15.26 x 16 = 244.14 us.
+     * |        |          |Note: In the following two cases, the power saving mode is disabled. The setting of PSVT1 bits is ignored.
+     * |        |          |1. PSVEN = 0
+     * |        |          |2. RESMODE = 0 and BUFEN = 0
+     * |[15:12] |PSVT2     |Power Saving "On Time" Setting
+     * |        |          |The "On Time" of the power saving mode is calculated as "On Time" = 15.26 us x (PSVT2 + 1),
+     * |        |          |where 15.26 us is the half-cycle time of LCD_CLK, whose frequency is about 32 kHz.
+     * |        |          |PSVT2 can be set as 0, 1, 2, ..., 15, so the minimum "On Time" is about 15.26 us, and the maximum "On Time" is about 15.26 x 16 = 244.14 us.
+     * |        |          |Note: In the following two cases, the power saving mode is disabled. The setting of PSVT2 bits is ignored.
+     * |        |          |1. PSVEN = 0
+     * |[28:16] |CTOTIME   |Charging Timer Timeout Time
+     * |        |          |This field is used to specify the timeout value for the charging timer. When the charging timer reaches this timeout value, a status bit or an interrupt will occur.
+     * |        |          |The timeout is calculated by the following formula: Timeout = 30.52 us x (CTOTIME + 1), where 30.52 us is the cycle time of LCD_CLK, whose frequency is about 32 kHz.
+     * |        |          |CTOTIME can be set as 0, 1, 2, ..., 8191, so the minimum timeout is 30.52 us, and the maximum timeout is 30.52 x 8192 = 256 ms.
+     * @var LCD_T::PKGSEL
+     * Offset: 0x10  LCD Package Selection Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PKG       |Device Package Type Selection
+     * |        |          |0 = 128-Pin Package
+     * |        |          |1 = 64-Pin Package
+     * @var LCD_T::STS
+     * Offset: 0x14  LCD Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |FCEF      |End of Frame-Counting Flag
+     * |        |          |This flag is automatically set by hardware at the end of a frame, and the frame counter value must be equal to FCV (LCD_FCTL[17:8], Frame Counting Value).
+     * |        |          |0 = End of Frame-Counting did not occur
+     * |        |          |1 = End of Frame-Counting occurred
+     * |        |          |Note 1: User can clear this bit by writing 1 to it.
+     * |        |          |Note 2: For type B waveform, this flag is set only at the end of an odd frame.
+     * |[1]     |FEF       |End of Frame Flag
+     * |        |          |This flag is automatically set by hardware at the end of a frame.
+     * |        |          |0 = End of Frame did not occur
+     * |        |          |1 = End of Frame occurred
+     * |        |          |Note 1: User can clear this bit by writing 1 to it.
+     * |        |          |Note 2: For type B waveform, this flag is set only at the end of an odd frame.
+     * |[2]     |CTOF      |Charging Timeout Flag
+     * |        |          |This flag is automatically set by hardware when the charging timer reaches the timeout value.
+     * |        |          |0 = Charging Timeout did not occur
+     * |        |          |1 = Charging Timeout occurred
+     * |        |          |Note: User can clear this bit by writing 1 to it.
+     * |[28:16] |CTIME     |Charging Timer Value (Read Only)
+     * |        |          |The field contains the value of the charging timer. It records the charging time of the charge pump.
+     * |        |          |The charging timer stops counting when the charge pump stops charging or a timeout occurs. At this moment, the hardware dumps the current charging timer value into this field.
+     * |        |          |Charging Time = 30.52 us x (CTIME + 1), where 30.52 us is the cycle time of LCD_CLK, whose frequency is about 32 kHz.
+     * @var LCD_T::INTEN
+     * Offset: 0x18  LCD Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |FCEIEN    |End of Frame-Counting Interrupt Enable Bit
+     * |        |          |An interrupt occurs at the end of a frame, and the frame counter value must be equal to FCV (LCD_FCTL[17:8], Frame Counting Value).
+     * |        |          |0 = End of Frame-Counting Interrupt Disabled
+     * |        |          |1 = End of Frame-Counting Interrupt Enabled
+     * |        |          |Note: For type B waveform, the interrupt occurs only at the end of an odd frame.
+     * |[1]     |FEIEN     |End of Frame Interrupt Enable Bit
+     * |        |          |An interrupt occurs at the end of a frame.
+     * |        |          |0 = End of Frame Interrupt Disabled
+     * |        |          |1 = End of Frame Interrupt Enabled
+     * |        |          |Note: For type B waveform, the interrupt occurs only at the end of an odd frame.
+     * |[2]     |CTOIEN    |Charging Timeout Interrupt Enable Bit
+     * |        |          |An interrupt occurs when the charging timer reaches the timeout value.
+     * |        |          |0 = Charging Timeout Interrupt Disabled
+     * |        |          |1 = Charging Timeout Interrupt Enabled
+     * @var LCD_T::DATA
+     * Offset: 0x20  LCD Segment Display Data Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |DD0       |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40.
+     * |        |          |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28),
+     * |        |          |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0),
+     * |        |          |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1),
+     * |        |          |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1),
+     * |        |          |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0),
+     * |        |          |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used.
+     * |[15:8]  |DD1       |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41.
+     * |        |          |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29),
+     * |        |          |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0),
+     * |        |          |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1),
+     * |        |          |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1),
+     * |        |          |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0),
+     * |        |          |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used.
+     * |[23:16] |DD2       |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42.
+     * |        |          |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30),
+     * |        |          |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0),
+     * |        |          |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1),
+     * |        |          |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1),
+     * |        |          |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0),
+     * |        |          |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used.
+     * |[31:24] |DD3       |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43.
+     * |        |          |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31),
+     * |        |          |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0),
+     * |        |          |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1),
+     * |        |          |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1),
+     * |        |          |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0),
+     * |        |          |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used.
+     * Offset: 0x24  LCD Segment Display Data Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |DD0       |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40.
+     * |        |          |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28),
+     * |        |          |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0),
+     * |        |          |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1),
+     * |        |          |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1),
+     * |        |          |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0),
+     * |        |          |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used.
+     * |[15:8]  |DD1       |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41.
+     * |        |          |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29),
+     * |        |          |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0),
+     * |        |          |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1),
+     * |        |          |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1),
+     * |        |          |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0),
+     * |        |          |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used.
+     * |[23:16] |DD2       |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42.
+     * |        |          |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30),
+     * |        |          |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0),
+     * |        |          |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1),
+     * |        |          |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1),
+     * |        |          |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0),
+     * |        |          |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used.
+     * |[31:24] |DD3       |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43.
+     * |        |          |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31),
+     * |        |          |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0),
+     * |        |          |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1),
+     * |        |          |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1),
+     * |        |          |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0),
+     * |        |          |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used.
+     * Offset: 0x28  LCD Segment Display Data Register 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |DD0       |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40.
+     * |        |          |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28),
+     * |        |          |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0),
+     * |        |          |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1),
+     * |        |          |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1),
+     * |        |          |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0),
+     * |        |          |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used.
+     * |[15:8]  |DD1       |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41.
+     * |        |          |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29),
+     * |        |          |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0),
+     * |        |          |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1),
+     * |        |          |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1),
+     * |        |          |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0),
+     * |        |          |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used.
+     * |[23:16] |DD2       |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42.
+     * |        |          |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30),
+     * |        |          |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0),
+     * |        |          |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1),
+     * |        |          |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1),
+     * |        |          |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0),
+     * |        |          |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used.
+     * |[31:24] |DD3       |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43.
+     * |        |          |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31),
+     * |        |          |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0),
+     * |        |          |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1),
+     * |        |          |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1),
+     * |        |          |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0),
+     * |        |          |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used.
+     * Offset: 0x2C  LCD Segment Display Data Register 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |DD0       |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40.
+     * |        |          |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28),
+     * |        |          |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0),
+     * |        |          |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1),
+     * |        |          |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1),
+     * |        |          |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0),
+     * |        |          |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used.
+     * |[15:8]  |DD1       |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41.
+     * |        |          |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29),
+     * |        |          |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0),
+     * |        |          |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1),
+     * |        |          |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1),
+     * |        |          |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0),
+     * |        |          |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used.
+     * |[23:16] |DD2       |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42.
+     * |        |          |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30),
+     * |        |          |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0),
+     * |        |          |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1),
+     * |        |          |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1),
+     * |        |          |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0),
+     * |        |          |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used.
+     * |[31:24] |DD3       |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43.
+     * |        |          |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31),
+     * |        |          |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0),
+     * |        |          |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1),
+     * |        |          |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1),
+     * |        |          |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0),
+     * |        |          |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used.
+     * Offset: 0x30  LCD Segment Display Data Register 4
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |DD0       |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40.
+     * |        |          |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28),
+     * |        |          |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0),
+     * |        |          |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1),
+     * |        |          |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1),
+     * |        |          |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0),
+     * |        |          |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used.
+     * |[15:8]  |DD1       |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41.
+     * |        |          |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29),
+     * |        |          |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0),
+     * |        |          |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1),
+     * |        |          |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1),
+     * |        |          |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0),
+     * |        |          |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used.
+     * |[23:16] |DD2       |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42.
+     * |        |          |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30),
+     * |        |          |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0),
+     * |        |          |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1),
+     * |        |          |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1),
+     * |        |          |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0),
+     * |        |          |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used.
+     * |[31:24] |DD3       |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43.
+     * |        |          |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31),
+     * |        |          |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0),
+     * |        |          |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1),
+     * |        |          |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1),
+     * |        |          |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0),
+     * |        |          |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used.
+     * Offset: 0x34  LCD Segment Display Data Register 5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |DD0       |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40.
+     * |        |          |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28),
+     * |        |          |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0),
+     * |        |          |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1),
+     * |        |          |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1),
+     * |        |          |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0),
+     * |        |          |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used.
+     * |[15:8]  |DD1       |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41.
+     * |        |          |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29),
+     * |        |          |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0),
+     * |        |          |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1),
+     * |        |          |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1),
+     * |        |          |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0),
+     * |        |          |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used.
+     * |[23:16] |DD2       |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42.
+     * |        |          |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30),
+     * |        |          |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0),
+     * |        |          |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1),
+     * |        |          |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1),
+     * |        |          |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0),
+     * |        |          |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used.
+     * |[31:24] |DD3       |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43.
+     * |        |          |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31),
+     * |        |          |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0),
+     * |        |          |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1),
+     * |        |          |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1),
+     * |        |          |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0),
+     * |        |          |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used.
+     * Offset: 0x38  LCD Segment Display Data Register 6
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |DD0       |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40.
+     * |        |          |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28),
+     * |        |          |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0),
+     * |        |          |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1),
+     * |        |          |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1),
+     * |        |          |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0),
+     * |        |          |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used.
+     * |[15:8]  |DD1       |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41.
+     * |        |          |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29),
+     * |        |          |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0),
+     * |        |          |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1),
+     * |        |          |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1),
+     * |        |          |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0),
+     * |        |          |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used.
+     * |[23:16] |DD2       |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42.
+     * |        |          |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30),
+     * |        |          |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0),
+     * |        |          |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1),
+     * |        |          |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1),
+     * |        |          |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0),
+     * |        |          |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used.
+     * |[31:24] |DD3       |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43.
+     * |        |          |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31),
+     * |        |          |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0),
+     * |        |          |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1),
+     * |        |          |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1),
+     * |        |          |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0),
+     * |        |          |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used.
+     * Offset: 0x3C  LCD Segment Display Data Register 7
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |DD0       |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40.
+     * |        |          |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28),
+     * |        |          |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0),
+     * |        |          |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1),
+     * |        |          |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1),
+     * |        |          |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0),
+     * |        |          |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used.
+     * |[15:8]  |DD1       |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41.
+     * |        |          |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29),
+     * |        |          |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0),
+     * |        |          |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1),
+     * |        |          |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1),
+     * |        |          |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0),
+     * |        |          |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used.
+     * |[23:16] |DD2       |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42.
+     * |        |          |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30),
+     * |        |          |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0),
+     * |        |          |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1),
+     * |        |          |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1),
+     * |        |          |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0),
+     * |        |          |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used.
+     * |[31:24] |DD3       |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43.
+     * |        |          |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31),
+     * |        |          |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0),
+     * |        |          |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1),
+     * |        |          |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1),
+     * |        |          |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0),
+     * |        |          |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used.
+     * Offset: 0x40  LCD Segment Display Data Register 8
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |DD0       |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40.
+     * |        |          |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28),
+     * |        |          |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0),
+     * |        |          |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1),
+     * |        |          |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1),
+     * |        |          |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0),
+     * |        |          |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used.
+     * |[15:8]  |DD1       |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41.
+     * |        |          |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29),
+     * |        |          |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0),
+     * |        |          |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1),
+     * |        |          |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1),
+     * |        |          |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0),
+     * |        |          |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used.
+     * |[23:16] |DD2       |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42.
+     * |        |          |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30),
+     * |        |          |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0),
+     * |        |          |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1),
+     * |        |          |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1),
+     * |        |          |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0),
+     * |        |          |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used.
+     * |[31:24] |DD3       |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43.
+     * |        |          |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31),
+     * |        |          |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0),
+     * |        |          |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1),
+     * |        |          |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1),
+     * |        |          |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0),
+     * |        |          |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used.
+     * Offset: 0x44  LCD Segment Display Data Register 9
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |DD0       |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40.
+     * |        |          |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28),
+     * |        |          |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0),
+     * |        |          |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1),
+     * |        |          |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1),
+     * |        |          |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0),
+     * |        |          |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used.
+     * |[15:8]  |DD1       |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41.
+     * |        |          |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29),
+     * |        |          |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0),
+     * |        |          |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1),
+     * |        |          |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1),
+     * |        |          |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0),
+     * |        |          |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used.
+     * |[23:16] |DD2       |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42.
+     * |        |          |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30),
+     * |        |          |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0),
+     * |        |          |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1),
+     * |        |          |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1),
+     * |        |          |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0),
+     * |        |          |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used.
+     * |[31:24] |DD3       |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43.
+     * |        |          |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31),
+     * |        |          |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0),
+     * |        |          |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1),
+     * |        |          |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1),
+     * |        |          |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0),
+     * |        |          |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used.
+     * Offset: 0x48  LCD Segment Display Data Register 10
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |DD0       |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40.
+     * |        |          |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28),
+     * |        |          |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0),
+     * |        |          |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1),
+     * |        |          |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1),
+     * |        |          |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0),
+     * |        |          |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used.
+     * |[15:8]  |DD1       |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41.
+     * |        |          |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29),
+     * |        |          |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0),
+     * |        |          |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1),
+     * |        |          |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1),
+     * |        |          |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0),
+     * |        |          |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used.
+     * |[23:16] |DD2       |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42.
+     * |        |          |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30),
+     * |        |          |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0),
+     * |        |          |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1),
+     * |        |          |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1),
+     * |        |          |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0),
+     * |        |          |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used.
+     * |[31:24] |DD3       |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10
+     * |        |          |Each bit specifies the brightness of each pixel in a segment.
+     * |        |          |0 = The pixel is light
+     * |        |          |1 = The pixel is dark
+     * |        |          |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43.
+     * |        |          |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7.
+     * |        |          |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31),
+     * |        |          |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0),
+     * |        |          |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1),
+     * |        |          |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1),
+     * |        |          |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0),
+     * |        |          |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used.
+     */
+    __IO uint32_t CTL;                  /*!< [0x0000] LCD Control Register                                      */
+    __IO uint32_t PCTL;                 /*!< [0x0004] LCD Panel Control Register                                */
+    __IO uint32_t FCTL;                 /*!< [0x0008] LCD Frame Control Register                                */
+    __IO uint32_t DCTL;                 /*!< [0x000C] LCD Driving Control Register                              */
+    __IO uint32_t PKGSEL;               /*!< [0x0010] LCD Package Selection Register                            */
+    __IO uint32_t STS;                  /*!< [0x0014] LCD Status Register                                       */
+    __IO uint32_t INTEN;                /*!< [0x0018] LCD Interrupt Enable Register                             */
+    __I  uint32_t RESERVED0;            /*!< [0x001C] Reserved 0                                                */
+    __IO uint32_t DATA[11];             /*!< [0x0020] ~ [0x0048] LCD Segment Display Data Register 0 ~ 10       */
+
+} LCD_T;
+
+/**
+    @addtogroup LCD_CONST LCD Bit Field Definition
+    Constant Definitions for LCD Controller
+  @{
+*/
+
+#define LCD_CTL_EN_Pos                  (0)                                                 /*!< LCD_T::CTL: EN Position                */
+#define LCD_CTL_EN_Msk                  (0x1ul << LCD_CTL_EN_Pos)                           /*!< LCD_T::CTL: EN Mask                    */
+
+#define LCD_CTL_SYNC_Pos                (31)                                                /*!< LCD_T::CTL: SYNC Position              */
+#define LCD_CTL_SYNC_Msk                (0x1ul << LCD_CTL_SYNC_Pos)                         /*!< LCD_T::CTL: SYNC Mask                  */
+
+#define LCD_PCTL_BIAS_Pos               (0)                                                 /*!< LCD_T::PCTL: BIAS Position             */
+#define LCD_PCTL_BIAS_Msk               (0x3ul << LCD_PCTL_BIAS_Pos)                        /*!< LCD_T::PCTL: BIAS Mask                 */
+
+#define LCD_PCTL_DUTY_Pos               (2)                                                 /*!< LCD_T::PCTL: DUTY Position             */
+#define LCD_PCTL_DUTY_Msk               (0x7ul << LCD_PCTL_DUTY_Pos)                        /*!< LCD_T::PCTL: DUTY Mask                 */
+
+#define LCD_PCTL_TYPE_Pos               (5)                                                 /*!< LCD_T::PCTL: TYPE Position             */
+#define LCD_PCTL_TYPE_Msk               (0x1ul << LCD_PCTL_TYPE_Pos)                        /*!< LCD_T::PCTL: TYPE Mask                 */
+
+#define LCD_PCTL_INV_Pos                (6)                                                 /*!< LCD_T::PCTL: INV Position              */
+#define LCD_PCTL_INV_Msk                (0x1ul << LCD_PCTL_INV_Pos)                         /*!< LCD_T::PCTL: INV Mask                  */
+
+#define LCD_PCTL_FREQDIV_Pos            (8)                                                 /*!< LCD_T::PCTL: FREQDIV Position          */
+#define LCD_PCTL_FREQDIV_Msk            (0x3fful << LCD_PCTL_FREQDIV_Pos)                   /*!< LCD_T::PCTL: FREQDIV Mask              */
+
+#define LCD_PCTL_CPVSEL_Pos             (18)                                                /*!< LCD_T::PCTL: CPVSEL Position           */
+#define LCD_PCTL_CPVSEL_Msk             (0x7ul << LCD_PCTL_CPVSEL_Pos)                      /*!< LCD_T::PCTL: CPVSEL Mask               */
+
+#define LCD_PCTL_CPVTUNE_Pos            (24)                                                /*!< LCD_T::PCTL: CPVTUNE Position          */
+#define LCD_PCTL_CPVTUNE_Msk            (0xful << LCD_PCTL_CPVTUNE_Pos)                     /*!< LCD_T::PCTL: CPVTUNE Mask              */
+
+#define LCD_FCTL_BLINK_Pos              (0)                                                 /*!< LCD_T::FCTL: BLINK Position            */
+#define LCD_FCTL_BLINK_Msk              (0x1ul << LCD_FCTL_BLINK_Pos)                       /*!< LCD_T::FCTL: BLINK Mask                */
+
+#define LCD_FCTL_FCV_Pos                (8)                                                 /*!< LCD_T::FCTL: FCV Position              */
+#define LCD_FCTL_FCV_Msk                (0x3fful << LCD_FCTL_FCV_Pos)                       /*!< LCD_T::FCTL: FCV Mask                  */
+
+#define LCD_FCTL_NFTIME_Pos             (24)                                                /*!< LCD_T::FCTL: NFTIME Position           */
+#define LCD_FCTL_NFTIME_Msk             (0xful << LCD_FCTL_NFTIME_Pos)                      /*!< LCD_T::FCTL: NFTIME Mask               */
+
+#define LCD_FCTL_NFNUM_Pos              (28)                                                /*!< LCD_T::FCTL: NFNUM Position            */
+#define LCD_FCTL_NFNUM_Msk              (0xful << LCD_FCTL_NFNUM_Pos)                       /*!< LCD_T::FCTL: NFNUM Mask                */
+
+#define LCD_DCTL_VSRC_Pos               (0)                                                 /*!< LCD_T::DCTL: VSRC Position             */
+#define LCD_DCTL_VSRC_Msk               (0x3ul << LCD_DCTL_VSRC_Pos)                        /*!< LCD_T::DCTL: VSRC Mask                 */
+
+#define LCD_DCTL_RESMODE_Pos            (2)                                                 /*!< LCD_T::DCTL: RESMODE Position          */
+#define LCD_DCTL_RESMODE_Msk            (0x1ul << LCD_DCTL_RESMODE_Pos)                     /*!< LCD_T::DCTL: RESMODE Mask              */
+
+#define LCD_DCTL_BUFEN_Pos              (3)                                                 /*!< LCD_T::DCTL: BUFEN Position            */
+#define LCD_DCTL_BUFEN_Msk              (0x1ul << LCD_DCTL_BUFEN_Pos)                       /*!< LCD_T::DCTL: BUFEN Mask                */
+
+#define LCD_DCTL_PSVEN_Pos              (4)                                                 /*!< LCD_T::DCTL: PSVEN Position            */
+#define LCD_DCTL_PSVEN_Msk              (0x1ul << LCD_DCTL_PSVEN_Pos)                       /*!< LCD_T::DCTL: PSVEN Mask                */
+
+#define LCD_DCTL_PSVREV_Pos             (5)                                                 /*!< LCD_T::DCTL: PSVREV Position           */
+#define LCD_DCTL_PSVREV_Msk             (0x1ul << LCD_DCTL_PSVREV_Pos)                      /*!< LCD_T::DCTL: PSVREV Mask               */
+
+#define LCD_DCTL_PSVT1_Pos              (8)                                                 /*!< LCD_T::DCTL: PSVT1 Position            */
+#define LCD_DCTL_PSVT1_Msk              (0xful << LCD_DCTL_PSVT1_Pos)                       /*!< LCD_T::DCTL: PSVT1 Mask                */
+
+#define LCD_DCTL_PSVT2_Pos              (12)                                                /*!< LCD_T::DCTL: PSVT2 Position            */
+#define LCD_DCTL_PSVT2_Msk              (0xful << LCD_DCTL_PSVT2_Pos)                       /*!< LCD_T::DCTL: PSVT2 Mask                */
+
+#define LCD_DCTL_CTOTIME_Pos            (16)                                                /*!< LCD_T::DCTL: CTOTIME Position          */
+#define LCD_DCTL_CTOTIME_Msk            (0x1ffful << LCD_DCTL_CTOTIME_Pos)                  /*!< LCD_T::DCTL: CTOTIME Mask              */
+
+#define LCD_PKGSEL_PKG_Pos              (0)                                                 /*!< LCD_T::PKGSEL: PKG Position            */
+#define LCD_PKGSEL_PKG_Msk              (0x1ul << LCD_PKGSEL_PKG_Pos)                       /*!< LCD_T::PKGSEL: PKG Mask                */
+
+#define LCD_STS_FCEF_Pos                (0)                                                 /*!< LCD_T::STS: FCEF Position              */
+#define LCD_STS_FCEF_Msk                (0x1ul << LCD_STS_FCEF_Pos)                         /*!< LCD_T::STS: FCEF Mask                  */
+
+#define LCD_STS_FEF_Pos                 (1)                                                 /*!< LCD_T::STS: FEF Position               */
+#define LCD_STS_FEF_Msk                 (0x1ul << LCD_STS_FEF_Pos)                          /*!< LCD_T::STS: FEF Mask                   */
+
+#define LCD_STS_CTOF_Pos                (2)                                                 /*!< LCD_T::STS: CTOF Position              */
+#define LCD_STS_CTOF_Msk                (0x1ul << LCD_STS_CTOF_Pos)                         /*!< LCD_T::STS: CTOF Mask                  */
+
+#define LCD_STS_CTIME_Pos               (16)                                                /*!< LCD_T::STS: CTIME Position             */
+#define LCD_STS_CTIME_Msk               (0x1ffful << LCD_STS_CTIME_Pos)                     /*!< LCD_T::STS: CTIME Mask                 */
+
+#define LCD_INTEN_FCEIEN_Pos            (0)                                                 /*!< LCD_T::INTEN: FCEIEN Position          */
+#define LCD_INTEN_FCEIEN_Msk            (0x1ul << LCD_INTEN_FCEIEN_Pos)                     /*!< LCD_T::INTEN: FCEIEN Mask              */
+
+#define LCD_INTEN_FEIEN_Pos             (1)                                                 /*!< LCD_T::INTEN: FEIEN Position           */
+#define LCD_INTEN_FEIEN_Msk             (0x1ul << LCD_INTEN_FEIEN_Pos)                      /*!< LCD_T::INTEN: FEIEN Mask               */
+
+#define LCD_INTEN_CTOIEN_Pos            (2)                                                 /*!< LCD_T::INTEN: CYOIEN Position          */
+#define LCD_INTEN_CTOIEN_Msk            (0x1ul << LCD_INTEN_CTOIEN_Pos)                     /*!< LCD_T::INTEN: CTOIEN Mask              */
+
+#define LCD_DATA00_DD0_Pos              (0)                                                 /*!< LCD_T::DATA00: DD0 Position            */
+#define LCD_DATA00_DD0_Msk              (0xfful << LCD_DATA00_DD0_Pos)                      /*!< LCD_T::DATA00: DD0 Mask                */
+
+#define LCD_DATA00_DD1_Pos              (8)                                                 /*!< LCD_T::DATA00: DD1 Position            */
+#define LCD_DATA00_DD1_Msk              (0xfful << LCD_DATA00_DD1_Pos)                      /*!< LCD_T::DATA00: DD1 Mask                */
+
+#define LCD_DATA00_DD2_Pos              (16)                                                /*!< LCD_T::DATA00: DD2 Position            */
+#define LCD_DATA00_DD2_Msk              (0xfful << LCD_DATA00_DD2_Pos)                      /*!< LCD_T::DATA00: DD2 Mask                */
+
+#define LCD_DATA00_DD3_Pos              (24)                                                /*!< LCD_T::DATA00: DD3 Position            */
+#define LCD_DATA00_DD3_Msk              (0xfful << LCD_DATA00_DD3_Pos)                      /*!< LCD_T::DATA00: DD3 Mask                */
+
+#define LCD_DATA01_DD0_Pos              (0)                                                 /*!< LCD_T::DATA01: DD0 Position            */
+#define LCD_DATA01_DD0_Msk              (0xfful << LCD_DATA01_DD0_Pos)                      /*!< LCD_T::DATA01: DD0 Mask                */
+
+#define LCD_DATA01_DD1_Pos              (8)                                                 /*!< LCD_T::DATA01: DD1 Position            */
+#define LCD_DATA01_DD1_Msk              (0xfful << LCD_DATA01_DD1_Pos)                      /*!< LCD_T::DATA01: DD1 Mask                */
+
+#define LCD_DATA01_DD2_Pos              (16)                                                /*!< LCD_T::DATA01: DD2 Position            */
+#define LCD_DATA01_DD2_Msk              (0xfful << LCD_DATA01_DD2_Pos)                      /*!< LCD_T::DATA01: DD2 Mask                */
+
+#define LCD_DATA01_DD3_Pos              (24)                                                /*!< LCD_T::DATA01: DD3 Position            */
+#define LCD_DATA01_DD3_Msk              (0xfful << LCD_DATA01_DD3_Pos)                      /*!< LCD_T::DATA01: DD3 Mask                */
+
+#define LCD_DATA02_DD0_Pos              (0)                                                 /*!< LCD_T::DATA02: DD0 Position            */
+#define LCD_DATA02_DD0_Msk              (0xfful << LCD_DATA02_DD0_Pos)                      /*!< LCD_T::DATA02: DD0 Mask                */
+
+#define LCD_DATA02_DD1_Pos              (8)                                                 /*!< LCD_T::DATA02: DD1 Position            */
+#define LCD_DATA02_DD1_Msk              (0xfful << LCD_DATA02_DD1_Pos)                      /*!< LCD_T::DATA02: DD1 Mask                */
+
+#define LCD_DATA02_DD2_Pos              (16)                                                /*!< LCD_T::DATA02: DD2 Position            */
+#define LCD_DATA02_DD2_Msk              (0xfful << LCD_DATA02_DD2_Pos)                      /*!< LCD_T::DATA02: DD2 Mask                */
+
+#define LCD_DATA02_DD3_Pos              (24)                                                /*!< LCD_T::DATA02: DD3 Position            */
+#define LCD_DATA02_DD3_Msk              (0xfful << LCD_DATA02_DD3_Pos)                      /*!< LCD_T::DATA02: DD3 Mask                */
+
+#define LCD_DATA03_DD0_Pos              (0)                                                 /*!< LCD_T::DATA03: DD0 Position            */
+#define LCD_DATA03_DD0_Msk              (0xfful << LCD_DATA03_DD0_Pos)                      /*!< LCD_T::DATA03: DD0 Mask                */
+
+#define LCD_DATA03_DD1_Pos              (8)                                                 /*!< LCD_T::DATA03: DD1 Position            */
+#define LCD_DATA03_DD1_Msk              (0xfful << LCD_DATA03_DD1_Pos)                      /*!< LCD_T::DATA03: DD1 Mask                */
+
+#define LCD_DATA03_DD2_Pos              (16)                                                /*!< LCD_T::DATA03: DD2 Position            */
+#define LCD_DATA03_DD2_Msk              (0xfful << LCD_DATA03_DD2_Pos)                      /*!< LCD_T::DATA03: DD2 Mask                */
+
+#define LCD_DATA03_DD3_Pos              (24)                                                /*!< LCD_T::DATA03: DD3 Position            */
+#define LCD_DATA03_DD3_Msk              (0xfful << LCD_DATA03_DD3_Pos)                      /*!< LCD_T::DATA03: DD3 Mask                */
+
+#define LCD_DATA04_DD0_Pos              (0)                                                 /*!< LCD_T::DATA04: DD0 Position            */
+#define LCD_DATA04_DD0_Msk              (0xfful << LCD_DATA04_DD0_Pos)                      /*!< LCD_T::DATA04: DD0 Mask                */
+
+#define LCD_DATA04_DD1_Pos              (8)                                                 /*!< LCD_T::DATA04: DD1 Position            */
+#define LCD_DATA04_DD1_Msk              (0xfful << LCD_DATA04_DD1_Pos)                      /*!< LCD_T::DATA04: DD1 Mask                */
+
+#define LCD_DATA04_DD2_Pos              (16)                                                /*!< LCD_T::DATA04: DD2 Position            */
+#define LCD_DATA04_DD2_Msk              (0xfful << LCD_DATA04_DD2_Pos)                      /*!< LCD_T::DATA04: DD2 Mask                */
+
+#define LCD_DATA04_DD3_Pos              (24)                                                /*!< LCD_T::DATA04: DD3 Position            */
+#define LCD_DATA04_DD3_Msk              (0xfful << LCD_DATA04_DD3_Pos)                      /*!< LCD_T::DATA04: DD3 Mask                */
+
+#define LCD_DATA05_DD0_Pos              (0)                                                 /*!< LCD_T::DATA05: DD0 Position            */
+#define LCD_DATA05_DD0_Msk              (0xfful << LCD_DATA05_DD0_Pos)                      /*!< LCD_T::DATA05: DD0 Mask                */
+
+#define LCD_DATA05_DD1_Pos              (8)                                                 /*!< LCD_T::DATA05: DD1 Position            */
+#define LCD_DATA05_DD1_Msk              (0xfful << LCD_DATA05_DD1_Pos)                      /*!< LCD_T::DATA05: DD1 Mask                */
+
+#define LCD_DATA05_DD2_Pos              (16)                                                /*!< LCD_T::DATA05: DD2 Position            */
+#define LCD_DATA05_DD2_Msk              (0xfful << LCD_DATA05_DD2_Pos)                      /*!< LCD_T::DATA05: DD2 Mask                */
+
+#define LCD_DATA05_DD3_Pos              (24)                                                /*!< LCD_T::DATA05: DD3 Position            */
+#define LCD_DATA05_DD3_Msk              (0xfful << LCD_DATA05_DD3_Pos)                      /*!< LCD_T::DATA05: DD3 Mask                */
+
+#define LCD_DATA06_DD0_Pos              (0)                                                 /*!< LCD_T::DATA06: DD0 Position            */
+#define LCD_DATA06_DD0_Msk              (0xfful << LCD_DATA06_DD0_Pos)                      /*!< LCD_T::DATA06: DD0 Mask                */
+
+#define LCD_DATA06_DD1_Pos              (8)                                                 /*!< LCD_T::DATA06: DD1 Position            */
+#define LCD_DATA06_DD1_Msk              (0xfful << LCD_DATA06_DD1_Pos)                      /*!< LCD_T::DATA06: DD1 Mask                */
+
+#define LCD_DATA06_DD2_Pos              (16)                                                /*!< LCD_T::DATA06: DD2 Position            */
+#define LCD_DATA06_DD2_Msk              (0xfful << LCD_DATA06_DD2_Pos)                      /*!< LCD_T::DATA06: DD2 Mask                */
+
+#define LCD_DATA06_DD3_Pos              (24)                                                /*!< LCD_T::DATA06: DD3 Position            */
+#define LCD_DATA06_DD3_Msk              (0xfful << LCD_DATA06_DD3_Pos)                      /*!< LCD_T::DATA06: DD3 Mask                */
+
+#define LCD_DATA07_DD0_Pos              (0)                                                 /*!< LCD_T::DATA07: DD0 Position            */
+#define LCD_DATA07_DD0_Msk              (0xfful << LCD_DATA07_DD0_Pos)                      /*!< LCD_T::DATA07: DD0 Mask                */
+
+#define LCD_DATA07_DD1_Pos              (8)                                                 /*!< LCD_T::DATA07: DD1 Position            */
+#define LCD_DATA07_DD1_Msk              (0xfful << LCD_DATA07_DD1_Pos)                      /*!< LCD_T::DATA07: DD1 Mask                */
+
+#define LCD_DATA07_DD2_Pos              (16)                                                /*!< LCD_T::DATA07: DD2 Position            */
+#define LCD_DATA07_DD2_Msk              (0xfful << LCD_DATA07_DD2_Pos)                      /*!< LCD_T::DATA07: DD2 Mask                */
+
+#define LCD_DATA07_DD3_Pos              (24)                                                /*!< LCD_T::DATA07: DD3 Position            */
+#define LCD_DATA07_DD3_Msk              (0xfful << LCD_DATA07_DD3_Pos)                      /*!< LCD_T::DATA07: DD3 Mask                */
+
+#define LCD_DATA08_DD0_Pos              (0)                                                 /*!< LCD_T::DATA08: DD0 Position            */
+#define LCD_DATA08_DD0_Msk              (0xfful << LCD_DATA08_DD0_Pos)                      /*!< LCD_T::DATA08: DD0 Mask                */
+
+#define LCD_DATA08_DD1_Pos              (8)                                                 /*!< LCD_T::DATA08: DD1 Position            */
+#define LCD_DATA08_DD1_Msk              (0xfful << LCD_DATA08_DD1_Pos)                      /*!< LCD_T::DATA08: DD1 Mask                */
+
+#define LCD_DATA08_DD2_Pos              (16)                                                /*!< LCD_T::DATA08: DD2 Position            */
+#define LCD_DATA08_DD2_Msk              (0xfful << LCD_DATA08_DD2_Pos)                      /*!< LCD_T::DATA08: DD2 Mask                */
+
+#define LCD_DATA08_DD3_Pos              (24)                                                /*!< LCD_T::DATA08: DD3 Position            */
+#define LCD_DATA08_DD3_Msk              (0xfful << LCD_DATA08_DD3_Pos)                      /*!< LCD_T::DATA08: DD3 Mask                */
+
+#define LCD_DATA09_DD0_Pos              (0)                                                 /*!< LCD_T::DATA09: DD0 Position            */
+#define LCD_DATA09_DD0_Msk              (0xfful << LCD_DATA09_DD0_Pos)                      /*!< LCD_T::DATA09: DD0 Mask                */
+
+#define LCD_DATA09_DD1_Pos              (8)                                                 /*!< LCD_T::DATA09: DD1 Position            */
+#define LCD_DATA09_DD1_Msk              (0xfful << LCD_DATA09_DD1_Pos)                      /*!< LCD_T::DATA09: DD1 Mask                */
+
+#define LCD_DATA09_DD2_Pos              (16)                                                /*!< LCD_T::DATA09: DD2 Position            */
+#define LCD_DATA09_DD2_Msk              (0xfful << LCD_DATA09_DD2_Pos)                      /*!< LCD_T::DATA09: DD2 Mask                */
+
+#define LCD_DATA09_DD3_Pos              (24)                                                /*!< LCD_T::DATA09: DD3 Position            */
+#define LCD_DATA09_DD3_Msk              (0xfful << LCD_DATA09_DD3_Pos)                      /*!< LCD_T::DATA09: DD3 Mask                */
+
+#define LCD_DATA10_DD0_Pos              (0)                                                 /*!< LCD_T::DATA10: DD0 Position            */
+#define LCD_DATA10_DD0_Msk              (0xfful << LCD_DATA10_DD0_Pos)                      /*!< LCD_T::DATA10: DD0 Mask                */
+
+#define LCD_DATA10_DD1_Pos              (8)                                                 /*!< LCD_T::DATA10: DD1 Position            */
+#define LCD_DATA10_DD1_Msk              (0xfful << LCD_DATA10_DD1_Pos)                      /*!< LCD_T::DATA10: DD1 Mask                */
+
+#define LCD_DATA10_DD2_Pos              (16)                                                /*!< LCD_T::DATA10: DD2 Position            */
+#define LCD_DATA10_DD2_Msk              (0xfful << LCD_DATA10_DD2_Pos)                      /*!< LCD_T::DATA10: DD2 Mask                */
+
+#define LCD_DATA10_DD3_Pos              (24)                                                /*!< LCD_T::DATA10: DD3 Position            */
+#define LCD_DATA10_DD3_Msk              (0xfful << LCD_DATA10_DD3_Pos)                      /*!< LCD_T::DATA10: DD3 Mask                */
+
+/**@}*/ /* LCD_CONST */
+/**@}*/ /* end of LCD register group */
+/**@}*/ /* end of REGISTER group */
+
+
+#endif /* __LCD_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/otg_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/otg_reg.h
new file mode 100644
index 0000000000..1c7274bf93
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/otg_reg.h
@@ -0,0 +1,394 @@
+/**************************************************************************//**
+ * @file     otg_reg.h
+ * @version  V1.00
+ * @brief    OTG register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __OTG_REG_H__
+#define __OTG_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+/*---------------------- USB On-The-Go Controller -------------------------*/
+/**
+    @addtogroup OTG USB On-The-Go Controller(OTG)
+    Memory Mapped Structure for OTG Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var OTG_T::CTL
+     * Offset: 0x00  OTG Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |VBUSDROP  |Drop VBUS Control
+     * |        |          |If user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS
+     * |        |          |BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device.
+     * |        |          |0 = Not drop the VBUS.
+     * |        |          |1 = Drop the VBUS.
+     * |[1]     |BUSREQ    |OTG Bus Request
+     * |        |          |If OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection
+     * |        |          |If user won't use the bus any more, clearing this bit will drop VBUS to save power
+     * |        |          |This bit will be cleared when A-device goes to A_wait_vfall state
+     * |        |          |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed.
+     * |        |          |If user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol
+     * |        |          |This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues SRP in specified interval, defined in OTG specification)
+     * |        |          |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed.
+     * |        |          |0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device.
+     * |        |          |1 = Launch VBUS in OTG A-device or request SRP in OTG B-device.
+     * |[2]     |HNPREQEN  |OTG HNP Request Enable Bit
+     * |        |          |When USB frame as A-device, set this bit when A-device allows to process HNP protocol -- A-device changes role from Host to Peripheral
+     * |        |          |This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state
+     * |        |          |When USB frame as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change -- B-device changes role from Peripheral to Host
+     * |        |          |This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state.
+     * |        |          |0 = HNP request Disabled.
+     * |        |          |1 = HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host).
+     * |        |          |Note: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state.
+     * |[4]     |OTGEN     |OTG Function Enable Bit
+     * |        |          |User needs to set this bit to enable OTG function while USB frame configured as OTG device
+     * |        |          |When USB frame is not configured as OTG device, this bit must be low.
+     * |        |          |0= OTG function Disabled.
+     * |        |          |1 = OTG function Enabled.
+     * |[5]     |WKEN      |OTG ID Pin Wake-up Enable Bit
+     * |        |          |0 = OTG ID pin status change wake-up function Disabled.
+     * |        |          |1 = OTG ID pin status change wake-up function Enabled.
+     * @var OTG_T::PHYCTL
+     * Offset: 0x04  OTG PHY Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |OTGPHYEN  |OTG PHY Enable Bit
+     * |        |          |When USB frame is configured as OTG device or ID dependent, user needs to set this bit before using OTG function
+     * |        |          |If device is not configured as OTG device nor ID dependent , this bit is "don't care".
+     * |        |          |0 = OTG PHY Disabled.
+     * |        |          |1 = OTG PHY Enabled.
+     * |[1]     |IDDETEN   |ID Detection Enable Bit
+     * |        |          |0 = Detect ID pin status Disabled.
+     * |        |          |1 = Detect ID pin status Enabled.
+     * |[4]     |VBENPOL   |Off-chip USB VBUS Power Switch Enable Polarity
+     * |        |          |The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need
+     * |        |          |A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch.
+     * |        |          |The polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component
+     * |        |          |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
+     * |        |          |0 = The off-chip USB VBUS power switch enable is active high.
+     * |        |          |1 = The off-chip USB VBUS power switch enable is active low.
+     * |[5]     |VBSTSPOL  |Off-chip USB VBUS Power Switch Status Polarity
+     * |        |          |The polarity of off-chip USB VBUS power switch valid signal depends on the selected component
+     * |        |          |A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch
+     * |        |          |Set this bit as following according to the polarity of off-chip USB VBUS power switch.
+     * |        |          |0 = The polarity of off-chip USB VBUS power switch valid status is high.
+     * |        |          |1 = The polarity of off-chip USB VBUS power switch valid status is low.
+     * @var OTG_T::INTEN
+     * Offset: 0x08  OTG Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ROLECHGIEN|Role (Host or Peripheral) Changed Interrupt Enable Bit
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[1]     |VBEIEN    |VBUS Error Interrupt Enable Bit
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG specification.
+     * |[2]     |SRPFIEN   |SRP Fail Interrupt Enable Bit
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[3]     |HNPFIEN   |HNP Fail Interrupt Enable Bit
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[4]     |GOIDLEIEN |OTG Device Goes to IDLE State Interrupt Enable Bit
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |        |          |Note: Going to idle state means going to a_idle or b_idle state
+     * |        |          |Please refer to A-device state diagram and B-device state diagram in OTG spec.
+     * |[5]     |IDCHGIEN  |IDSTS Changed Interrupt Enable Bit
+     * |        |          |If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, an interrupt will be asserted.
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[6]     |PDEVIEN   |Act As Peripheral Interrupt Enable Bit
+     * |        |          |If this bit is set to 1 and the device is changed as a peripheral, an interrupt will be asserted.
+     * |        |          |0 = This device as a peripheral interrupt Disabled.
+     * |        |          |1 = This device as a peripheral interrupt Enabled.
+     * |[7]     |HOSTIEN   |Act As Host Interrupt Enable Bit
+     * |        |          |If this bit is set to 1 and the device is changed as a host, an interrupt will be asserted.
+     * |        |          |0 = This device as a host interrupt Disabled.
+     * |        |          |1 = This device as a host interrupt Enabled.
+     * |[8]     |BVLDCHGIEN|B-device Session Valid Status Changed Interrupt Enable Bit
+     * |        |          |If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, an interrupt will be asserted.
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[9]     |AVLDCHGIEN|A-device Session Valid Status Changed Interrupt Enable Bit
+     * |        |          |If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, an interrupt will be asserted.
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[10]    |VBCHGIEN  |VBUSVLD Status Changed Interrupt Enable Bit
+     * |        |          |If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, an interrupt will be asserted.
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[11]    |SECHGIEN  |SESSEND Status Changed Interrupt Enable Bit
+     * |        |          |If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, an interrupt will be asserted.
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[13]    |SRPDETIEN |SRP Detected Interrupt Enable Bit
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * @var OTG_T::INTSTS
+     * Offset: 0x0C  OTG Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ROLECHGIF |OTG Role Change Interrupt Status
+     * |        |          |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change.
+     * |        |          |0 = OTG device role not changed.
+     * |        |          |1 = OTG device role changed.
+     * |        |          |Note: Write 1 to clear this flag.
+     * |[1]     |VBEIF     |VBUS Error Interrupt Status
+     * |        |          |This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high.
+     * |        |          |0 = OTG A-device drives VBUS over threshold voltage before this interval expires.
+     * |        |          |1 = OTG A-device cannot drive VBUS over threshold voltage before this interval expires.
+     * |        |          |Note: Write 1 to clear this flag and recover from the VBUS error state.
+     * |[2]     |SRPFIF    |SRP Fail Interrupt Status
+     * |        |          |After initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification
+     * |        |          |This flag is set when the OTG B-device does not get VBUS high after this interval.
+     * |        |          |0 = OTG B-device gets VBUS high before this interval.
+     * |        |          |1 = OTG B-device does not get VBUS high before this interval.
+     * |        |          |Note: Write 1 to clear this flag.
+     * |[3]     |HNPFIF    |HNP Fail Interrupt Status
+     * |        |          |When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires.
+     * |        |          |0 = A-device connects to B-device before specified interval expires.
+     * |        |          |1 = A-device does not connect to B-device before specified interval expires.
+     * |        |          |Note: Write 1 to clear this flag.
+     * |[4]     |GOIDLEIF  |OTG Device Goes to IDLE Interrupt Status
+     * |        |          |Flag is set if the OTG device transfers from non-idle state to idle state
+     * |        |          |The OTG device will be neither a host nor a peripheral.
+     * |        |          |0 = OTG device does not go back to idle state (a_idle or b_idle).
+     * |        |          |1 = OTG device goes back to idle state(a_idle or b_idle).
+     * |        |          |Note 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification.
+     * |        |          |Note 2: Write 1 to clear this flag.
+     * |[5]     |IDCHGIF   |ID State Change Interrupt Status
+     * |        |          |0 = IDSTS (OTG_STATUS[1]) not toggled.
+     * |        |          |1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high.
+     * |        |          |Note: Write 1 to clear this flag.
+     * |[6]     |PDEVIF    |Act As Peripheral Interrupt Status
+     * |        |          |0= This device does not act as a peripheral.
+     * |        |          |1 = This device acts as a peripheral.
+     * |        |          |Note: Write 1 to clear this flag.
+     * |[7]     |HOSTIF    |Act As Host Interrupt Status
+     * |        |          |0= This device does not act as a host.
+     * |        |          |1 = This device acts as a host.
+     * |        |          |Note: Write 1 to clear this flag.
+     * |[8]     |BVLDCHGIF |B-device Session Valid State Change Interrupt Status
+     * |        |          |0 = BVLD (OTG_STATUS[3]) is not toggled.
+     * |        |          |1 = BVLD (OTG_STATUS[3]) from high to low or low to high.
+     * |        |          |Note: Write 1 to clear this status.
+     * |[9]     |AVLDCHGIF |A-device Session Valid State Change Interrupt Status
+     * |        |          |0 = AVLD (OTG_STATUS[4]) not toggled.
+     * |        |          |1 = AVLD (OTG_STATUS[4]) from high to low or low to high.
+     * |        |          |Note: Write 1 to clear this status.
+     * |[10]    |VBCHGIF   |VBUSVLD State Change Interrupt Status
+     * |        |          |0 = VBUSVLD (OTG_STATUS[5]) not toggled.
+     * |        |          |1 = VBUSVLD (OTG_STATUS[5]) from high to low or from low to high.
+     * |        |          |Note: Write 1 to clear this status.
+     * |[11]    |SECHGIF   |SESSEND State Change Interrupt Status
+     * |        |          |0 = SESSEND (OTG_STATUS[2]) not toggled.
+     * |        |          |1 = SESSEND (OTG_STATUS[2]) from high to low or from low to high.
+     * |        |          |Note: Write 1 to clear this flag.
+     * |[13]    |SRPDETIF  |SRP Detected Interrupt Status
+     * |        |          |0 = SRP not detected.
+     * |        |          |1 = SRP detected.
+     * |        |          |Note: Write 1 to clear this status.
+     * @var OTG_T::STATUS
+     * Offset: 0x10  OTG Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |OVERCUR   |Over Current Condition
+     * |        |          |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high.
+     * |        |          |0 = OTG A-device drives VBUS successfully.
+     * |        |          |1 = OTG A-device cannot drives VBUS high in this interval.
+     * |[1]     |IDSTS     |USB_ID Pin State of Mini-/Micro- Plug
+     * |        |          |0 = Mini-A/Micro-A plug is attached.
+     * |        |          |1 = Mini-B/Micro-B plug is attached.
+     * |[2]     |SESSEND   |Session End Status
+     * |        |          |When VBUS voltage is lower than 0.4V, this bit will be set to 1
+     * |        |          |Session end means no meaningful power on VBUS.
+     * |        |          |0 = Session is not end.
+     * |        |          |1 = Session is end.
+     * |[3]     |BVLD      |B-device Session Valid Status
+     * |        |          |0 = B-device session is not valid.
+     * |        |          |1 = B-device session is valid.
+     * |[4]     |AVLD      |A-device Session Valid Status
+     * |        |          |0 = A-device session is not valid.
+     * |        |          |1 = A-device session is valid.
+     * |[5]     |VBUSVLD   |VBUS Valid Status
+     * |        |          |When VBUS is larger than 4.7V, this bit will be set to 1.
+     * |        |          |0 = VBUS is not valid.
+     * |        |          |1 = VBUS is valid.
+     * |[6]     |ASPERI    |As Peripheral Status
+     * |        |          |When OTG as peripheral, this bit is set.
+     * |        |          |0: OTG not as peripheral
+     * |        |          |1: OTG as peripheral
+     * |[7]     |ASHOST    |As Host Status
+     * |        |          |When OTG as Host, this bit is set.
+     * |        |          |0: OTG not as Host
+     * |        |          |1: OTG as Host
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] OTG Control Register                                             */
+    __IO uint32_t PHYCTL;                /*!< [0x0004] OTG PHY Control Register                                         */
+    __IO uint32_t INTEN;                 /*!< [0x0008] OTG Interrupt Enable Register                                    */
+    __IO uint32_t INTSTS;                /*!< [0x000c] OTG Interrupt Status Register                                    */
+    __I  uint32_t STATUS;                /*!< [0x0010] OTG Status Register                                              */
+
+} OTG_T;
+
+/**
+    @addtogroup OTG_CONST OTG Bit Field Definition
+    Constant Definitions for OTG Controller
+  @{
+*/
+
+#define OTG_CTL_VBUSDROP_Pos             (0)                                               /*!< OTG_T::CTL: VBUSDROP Position          */
+#define OTG_CTL_VBUSDROP_Msk             (0x1ul << OTG_CTL_VBUSDROP_Pos)                   /*!< OTG_T::CTL: VBUSDROP Mask              */
+
+#define OTG_CTL_BUSREQ_Pos               (1)                                               /*!< OTG_T::CTL: BUSREQ Position            */
+#define OTG_CTL_BUSREQ_Msk               (0x1ul << OTG_CTL_BUSREQ_Pos)                     /*!< OTG_T::CTL: BUSREQ Mask                */
+
+#define OTG_CTL_HNPREQEN_Pos             (2)                                               /*!< OTG_T::CTL: HNPREQEN Position          */
+#define OTG_CTL_HNPREQEN_Msk             (0x1ul << OTG_CTL_HNPREQEN_Pos)                   /*!< OTG_T::CTL: HNPREQEN Mask              */
+
+#define OTG_CTL_OTGEN_Pos                (4)                                               /*!< OTG_T::CTL: OTGEN Position             */
+#define OTG_CTL_OTGEN_Msk                (0x1ul << OTG_CTL_OTGEN_Pos)                      /*!< OTG_T::CTL: OTGEN Mask                 */
+
+#define OTG_CTL_WKEN_Pos                 (5)                                               /*!< OTG_T::CTL: WKEN Position              */
+#define OTG_CTL_WKEN_Msk                 (0x1ul << OTG_CTL_WKEN_Pos)                       /*!< OTG_T::CTL: WKEN Mask                  */
+
+#define OTG_PHYCTL_OTGPHYEN_Pos          (0)                                               /*!< OTG_T::PHYCTL: OTGPHYEN Position       */
+#define OTG_PHYCTL_OTGPHYEN_Msk          (0x1ul << OTG_PHYCTL_OTGPHYEN_Pos)                /*!< OTG_T::PHYCTL: OTGPHYEN Mask           */
+
+#define OTG_PHYCTL_IDDETEN_Pos           (1)                                               /*!< OTG_T::PHYCTL: IDDETEN Position        */
+#define OTG_PHYCTL_IDDETEN_Msk           (0x1ul << OTG_PHYCTL_IDDETEN_Pos)                 /*!< OTG_T::PHYCTL: IDDETEN Mask            */
+
+#define OTG_PHYCTL_VBENPOL_Pos           (4)                                               /*!< OTG_T::PHYCTL: VBENPOL Position        */
+#define OTG_PHYCTL_VBENPOL_Msk           (0x1ul << OTG_PHYCTL_VBENPOL_Pos)                 /*!< OTG_T::PHYCTL: VBENPOL Mask            */
+
+#define OTG_PHYCTL_VBSTSPOL_Pos          (5)                                               /*!< OTG_T::PHYCTL: VBSTSPOL Position       */
+#define OTG_PHYCTL_VBSTSPOL_Msk          (0x1ul << OTG_PHYCTL_VBSTSPOL_Pos)                /*!< OTG_T::PHYCTL: VBSTSPOL Mask           */
+
+#define OTG_INTEN_ROLECHGIEN_Pos         (0)                                               /*!< OTG_T::INTEN: ROLECHGIEN Position      */
+#define OTG_INTEN_ROLECHGIEN_Msk         (0x1ul << OTG_INTEN_ROLECHGIEN_Pos)               /*!< OTG_T::INTEN: ROLECHGIEN Mask          */
+
+#define OTG_INTEN_VBEIEN_Pos             (1)                                               /*!< OTG_T::INTEN: VBEIEN Position          */
+#define OTG_INTEN_VBEIEN_Msk             (0x1ul << OTG_INTEN_VBEIEN_Pos)                   /*!< OTG_T::INTEN: VBEIEN Mask              */
+
+#define OTG_INTEN_SRPFIEN_Pos            (2)                                               /*!< OTG_T::INTEN: SRPFIEN Position         */
+#define OTG_INTEN_SRPFIEN_Msk            (0x1ul << OTG_INTEN_SRPFIEN_Pos)                  /*!< OTG_T::INTEN: SRPFIEN Mask             */
+
+#define OTG_INTEN_HNPFIEN_Pos            (3)                                               /*!< OTG_T::INTEN: HNPFIEN Position         */
+#define OTG_INTEN_HNPFIEN_Msk            (0x1ul << OTG_INTEN_HNPFIEN_Pos)                  /*!< OTG_T::INTEN: HNPFIEN Mask             */
+
+#define OTG_INTEN_GOIDLEIEN_Pos          (4)                                               /*!< OTG_T::INTEN: GOIDLEIEN Position       */
+#define OTG_INTEN_GOIDLEIEN_Msk          (0x1ul << OTG_INTEN_GOIDLEIEN_Pos)                /*!< OTG_T::INTEN: GOIDLEIEN Mask           */
+
+#define OTG_INTEN_IDCHGIEN_Pos           (5)                                               /*!< OTG_T::INTEN: IDCHGIEN Position        */
+#define OTG_INTEN_IDCHGIEN_Msk           (0x1ul << OTG_INTEN_IDCHGIEN_Pos)                 /*!< OTG_T::INTEN: IDCHGIEN Mask            */
+
+#define OTG_INTEN_PDEVIEN_Pos            (6)                                               /*!< OTG_T::INTEN: PDEVIEN Position         */
+#define OTG_INTEN_PDEVIEN_Msk            (0x1ul << OTG_INTEN_PDEVIEN_Pos)                  /*!< OTG_T::INTEN: PDEVIEN Mask             */
+
+#define OTG_INTEN_HOSTIEN_Pos            (7)                                               /*!< OTG_T::INTEN: HOSTIEN Position         */
+#define OTG_INTEN_HOSTIEN_Msk            (0x1ul << OTG_INTEN_HOSTIEN_Pos)                  /*!< OTG_T::INTEN: HOSTIEN Mask             */
+
+#define OTG_INTEN_BVLDCHGIEN_Pos         (8)                                               /*!< OTG_T::INTEN: BVLDCHGIEN Position      */
+#define OTG_INTEN_BVLDCHGIEN_Msk         (0x1ul << OTG_INTEN_BVLDCHGIEN_Pos)               /*!< OTG_T::INTEN: BVLDCHGIEN Mask          */
+
+#define OTG_INTEN_AVLDCHGIEN_Pos         (9)                                               /*!< OTG_T::INTEN: AVLDCHGIEN Position      */
+#define OTG_INTEN_AVLDCHGIEN_Msk         (0x1ul << OTG_INTEN_AVLDCHGIEN_Pos)               /*!< OTG_T::INTEN: AVLDCHGIEN Mask          */
+
+#define OTG_INTEN_VBCHGIEN_Pos           (10)                                              /*!< OTG_T::INTEN: VBCHGIEN Position        */
+#define OTG_INTEN_VBCHGIEN_Msk           (0x1ul << OTG_INTEN_VBCHGIEN_Pos)                 /*!< OTG_T::INTEN: VBCHGIEN Mask            */
+
+#define OTG_INTEN_SECHGIEN_Pos           (11)                                              /*!< OTG_T::INTEN: SECHGIEN Position        */
+#define OTG_INTEN_SECHGIEN_Msk           (0x1ul << OTG_INTEN_SECHGIEN_Pos)                 /*!< OTG_T::INTEN: SECHGIEN Mask            */
+
+#define OTG_INTEN_SRPDETIEN_Pos          (13)                                              /*!< OTG_T::INTEN: SRPDETIEN Position       */
+#define OTG_INTEN_SRPDETIEN_Msk          (0x1ul << OTG_INTEN_SRPDETIEN_Pos)                /*!< OTG_T::INTEN: SRPDETIEN Mask           */
+
+#define OTG_INTSTS_ROLECHGIF_Pos         (0)                                               /*!< OTG_T::INTSTS: ROLECHGIF Position      */
+#define OTG_INTSTS_ROLECHGIF_Msk         (0x1ul << OTG_INTSTS_ROLECHGIF_Pos)               /*!< OTG_T::INTSTS: ROLECHGIF Mask          */
+
+#define OTG_INTSTS_VBEIF_Pos             (1)                                               /*!< OTG_T::INTSTS: VBEIF Position          */
+#define OTG_INTSTS_VBEIF_Msk             (0x1ul << OTG_INTSTS_VBEIF_Pos)                   /*!< OTG_T::INTSTS: VBEIF Mask              */
+
+#define OTG_INTSTS_SRPFIF_Pos            (2)                                               /*!< OTG_T::INTSTS: SRPFIF Position         */
+#define OTG_INTSTS_SRPFIF_Msk            (0x1ul << OTG_INTSTS_SRPFIF_Pos)                  /*!< OTG_T::INTSTS: SRPFIF Mask             */
+
+#define OTG_INTSTS_HNPFIF_Pos            (3)                                               /*!< OTG_T::INTSTS: HNPFIF Position         */
+#define OTG_INTSTS_HNPFIF_Msk            (0x1ul << OTG_INTSTS_HNPFIF_Pos)                  /*!< OTG_T::INTSTS: HNPFIF Mask             */
+
+#define OTG_INTSTS_GOIDLEIF_Pos          (4)                                               /*!< OTG_T::INTSTS: GOIDLEIF Position       */
+#define OTG_INTSTS_GOIDLEIF_Msk          (0x1ul << OTG_INTSTS_GOIDLEIF_Pos)                /*!< OTG_T::INTSTS: GOIDLEIF Mask           */
+
+#define OTG_INTSTS_IDCHGIF_Pos           (5)                                               /*!< OTG_T::INTSTS: IDCHGIF Position        */
+#define OTG_INTSTS_IDCHGIF_Msk           (0x1ul << OTG_INTSTS_IDCHGIF_Pos)                 /*!< OTG_T::INTSTS: IDCHGIF Mask            */
+
+#define OTG_INTSTS_PDEVIF_Pos            (6)                                               /*!< OTG_T::INTSTS: PDEVIF Position         */
+#define OTG_INTSTS_PDEVIF_Msk            (0x1ul << OTG_INTSTS_PDEVIF_Pos)                  /*!< OTG_T::INTSTS: PDEVIF Mask             */
+
+#define OTG_INTSTS_HOSTIF_Pos            (7)                                               /*!< OTG_T::INTSTS: HOSTIF Position         */
+#define OTG_INTSTS_HOSTIF_Msk            (0x1ul << OTG_INTSTS_HOSTIF_Pos)                  /*!< OTG_T::INTSTS: HOSTIF Mask             */
+
+#define OTG_INTSTS_BVLDCHGIF_Pos         (8)                                               /*!< OTG_T::INTSTS: BVLDCHGIF Position      */
+#define OTG_INTSTS_BVLDCHGIF_Msk         (0x1ul << OTG_INTSTS_BVLDCHGIF_Pos)               /*!< OTG_T::INTSTS: BVLDCHGIF Mask          */
+
+#define OTG_INTSTS_AVLDCHGIF_Pos         (9)                                               /*!< OTG_T::INTSTS: AVLDCHGIF Position      */
+#define OTG_INTSTS_AVLDCHGIF_Msk         (0x1ul << OTG_INTSTS_AVLDCHGIF_Pos)               /*!< OTG_T::INTSTS: AVLDCHGIF Mask          */
+
+#define OTG_INTSTS_VBCHGIF_Pos           (10)                                              /*!< OTG_T::INTSTS: VBCHGIF Position        */
+#define OTG_INTSTS_VBCHGIF_Msk           (0x1ul << OTG_INTSTS_VBCHGIF_Pos)                 /*!< OTG_T::INTSTS: VBCHGIF Mask            */
+
+#define OTG_INTSTS_SECHGIF_Pos           (11)                                              /*!< OTG_T::INTSTS: SECHGIF Position        */
+#define OTG_INTSTS_SECHGIF_Msk           (0x1ul << OTG_INTSTS_SECHGIF_Pos)                 /*!< OTG_T::INTSTS: SECHGIF Mask            */
+
+#define OTG_INTSTS_SRPDETIF_Pos          (13)                                              /*!< OTG_T::INTSTS: SRPDETIF Position       */
+#define OTG_INTSTS_SRPDETIF_Msk          (0x1ul << OTG_INTSTS_SRPDETIF_Pos)                /*!< OTG_T::INTSTS: SRPDETIF Mask           */
+
+#define OTG_STATUS_OVERCUR_Pos           (0)                                               /*!< OTG_T::STATUS: OVERCUR Position        */
+#define OTG_STATUS_OVERCUR_Msk           (0x1ul << OTG_STATUS_OVERCUR_Pos)                 /*!< OTG_T::STATUS: OVERCUR Mask            */
+
+#define OTG_STATUS_IDSTS_Pos             (1)                                               /*!< OTG_T::STATUS: IDSTS Position          */
+#define OTG_STATUS_IDSTS_Msk             (0x1ul << OTG_STATUS_IDSTS_Pos)                   /*!< OTG_T::STATUS: IDSTS Mask              */
+
+#define OTG_STATUS_SESSEND_Pos           (2)                                               /*!< OTG_T::STATUS: SESSEND Position        */
+#define OTG_STATUS_SESSEND_Msk           (0x1ul << OTG_STATUS_SESSEND_Pos)                 /*!< OTG_T::STATUS: SESSEND Mask            */
+
+#define OTG_STATUS_BVLD_Pos              (3)                                               /*!< OTG_T::STATUS: BVLD Position           */
+#define OTG_STATUS_BVLD_Msk              (0x1ul << OTG_STATUS_BVLD_Pos)                    /*!< OTG_T::STATUS: BVLD Mask               */
+
+#define OTG_STATUS_AVLD_Pos              (4)                                               /*!< OTG_T::STATUS: AVLD Position           */
+#define OTG_STATUS_AVLD_Msk              (0x1ul << OTG_STATUS_AVLD_Pos)                    /*!< OTG_T::STATUS: AVLD Mask               */
+
+#define OTG_STATUS_VBUSVLD_Pos           (5)                                               /*!< OTG_T::STATUS: VBUSVLD Position        */
+#define OTG_STATUS_VBUSVLD_Msk           (0x1ul << OTG_STATUS_VBUSVLD_Pos)                 /*!< OTG_T::STATUS: VBUSVLD Mask            */
+
+#define OTG_STATUS_ASPERI_Pos            (6)                                               /*!< OTG_T::STATUS: ASPERI Position         */
+#define OTG_STATUS_ASPERI_Msk            (0x1ul << OTG_STATUS_ASPERI_Pos)                  /*!< OTG_T::STATUS: ASPERI Mask             */
+
+#define OTG_STATUS_ASHOST_Pos            (7)                                               /*!< OTG_T::STATUS: ASHOST Position         */
+#define OTG_STATUS_ASHOST_Msk            (0x1ul << OTG_STATUS_ASHOST_Pos)                  /*!< OTG_T::STATUS: ASHOST Mask             */
+
+/**@}*/ /* OTG_CONST */
+/**@}*/ /* end of OTG register group */
+/**@}*/ /* end of REGISTER group */
+
+#endif /* __OTG_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/pdma_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/pdma_reg.h
new file mode 100644
index 0000000000..9ef68cb79d
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/pdma_reg.h
@@ -0,0 +1,814 @@
+/**************************************************************************//**
+ * @file     pdma_reg.h
+ * @version  V1.00
+ * @brief    PDMA register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __PDMA_REG_H__
+#define __PDMA_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+/*---------------------- Peripheral Direct Memory Access Controller -------------------------*/
+/**
+    @addtogroup PDMA Peripheral Direct Memory Access Controller(PDMA)
+    Memory Mapped Structure for PDMA Controller
+  @{
+*/
+
+
+
+typedef struct
+{
+    /**
+     * @var DSCT_T::CTL
+     * Offset: 0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70  Descriptor Table Control Register of PDMA Channel 0~7
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |OPMODE    |PDMA Operation Mode Selection
+     * |        |          |00 = Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically.
+     * |        |          |01 = Basic mode: The descriptor table only has one task
+     * |        |          |When this task is finished, the TDIF(PDMA_INTSTS[1]) will be asserted.
+     * |        |          |10 = Scatter-Gather mode: When operating in this mode, user must give the first descriptor table address in PDMA_DSCT_FIRST register; PDMA controller will ignore this task, then load the next task to execute.
+     * |        |          |11 = Reserved.
+     * |        |          |Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete.
+     * |[2]     |TXTYPE    |Transfer Type
+     * |        |          |0 = Burst transfer type.
+     * |        |          |1 = Single transfer type.
+     * |[6:4]   |BURSIZE   |Burst Size
+     * |        |          |This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.
+     * |        |          |000 = 128 Transfers.
+     * |        |          |001 = 64 Transfers.
+     * |        |          |010 = 32 Transfers.
+     * |        |          |011 = 16 Transfers.
+     * |        |          |100 = 8 Transfers.
+     * |        |          |101 = 4 Transfers.
+     * |        |          |110 = 2 Transfers.
+     * |        |          |111 = 1 Transfers.
+     * |        |          |Note: This field is only useful in burst transfer type.
+     * |[7]     |TBINTDIS  |Table Interrupt Disable Bit
+     * |        |          |This field can be used to decide whether to enable table interrupt or not
+     * |        |          |If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates transfer done interrupt.
+     * |        |          |0 = Table interrupt Enabled.
+     * |        |          |1 = Table interrupt Disabled.
+     * |        |          |Note: If this bit set to 1, the TEMPTYF will not be set.
+     * |[9:8]   |SAINC     |Source Address Increment
+     * |        |          |This field is used to set the source address increment size.
+     * |        |          |11 = No increment (fixed address).
+     * |        |          |Others = Increment and size is depended on TXWIDTH selection.
+     * |[11:10] |DAINC     |Destination Address Increment
+     * |        |          |This field is used to set the destination address increment size.
+     * |        |          |11 = No increment (fixed address).
+     * |        |          |Others = Increment and size is depended on TXWIDTH selection.
+     * |[13:12] |TXWIDTH   |Transfer Width Selection
+     * |        |          |This field is used for transfer width.
+     * |        |          |00 = One byte (8 bit) is transferred for every operation.
+     * |        |          |01 = One half-word (16 bit) is transferred for every operation.
+     * |        |          |10 = One word (32-bit) is transferred for every operation.
+     * |        |          |11 = Reserved.
+     * |        |          |Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection
+     * |        |          |For example, if source address is 0x2000_0202, but TXWIDTH is word transfer, the source address is not word alignment
+     * |        |          |The source address is aligned when TXWIDTH is byte or half-word transfer.
+     * |[14]    |TXACK     |Transfer Acknowledge Selection
+     * |        |          |0 = transfer ack when transfer done.
+     * |        |          |1 = transfer ack when PDMA get transfer data.
+     * |[15]    |STRIDEEN |Stride Mode Enable Bit
+     * |        |          |0 = Stride transfer mode Disabled.
+     * |        |          |1 = Stride transfer mode Enabled.
+     * |[31:16] |TXCNT     |Transfer Count
+     * |        |          |The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 65536, every transfer may be byte, half-word or word that is dependent on TXWIDTH field.
+     * |        |          |Note: When PDMA finish each transfer data, this field will be decrease immediately.
+     * @var DSCT_T::SA
+     * Offset: 0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74  Source Address Register of PDMA Channel 0~7
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SA        |PDMA Transfer Source Address Register
+     * |        |          |This field indicates a 32-bit source address of PDMA controller.
+     * |        |          |Note: The PDMA transfer source address should be aligned with the TXWIDTH(PDMA_DSCTn_CTL[13:12], n=0,1..7) selection.
+     * @var DSCT_T::DA
+     * Offset: 0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78  Destination Address Register of PDMA Channel 0~7
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |DA        |PDMA Transfer Destination Address Register
+     * |        |          |This field indicates a 32-bit destination address of PDMA controller.
+     * |        |          |Note: The PDMA transfer destination address should be aligned with the TXWIDTH(PDMA_DSCTn_CTL[13:12], n=0,1..7) selection.
+     * @var DSCT_T::NEXT
+     * Offset: 0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C  First Scatter-Gather Descriptor Table Offset of PDMA Channel 0~7
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |FIRST     |PDMA First Descriptor Table Offset
+     * |        |          |This field indicates the offset of the first descriptor table address in system memory.
+     * |        |          |Write Operation:
+     * |        |          |If the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the first descriptor table is start from 0x2000_0100, then this field must fill in 0x0100.
+     * |        |          |Read Operation:
+     * |        |          |When operating in scatter-gather mode, the last two bits FIRST[1:0] will become reserved.
+     * |        |          |Note1: The first descriptor table address must be word boundary.
+     * |        |          |Note2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete.
+     * |[31:16] |NEXT      |PDMA Next Descriptor Table Offset
+     * |        |          |This field indicates the offset of next descriptor table address in system memory.
+     * |        |          |Note: write operation is useless in this field.
+     */
+
+    __IO uint32_t CTL;             /*!< [0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70] Descriptor Table Control Register of PDMA Channel 0~7              */
+    __IO uint32_t SA;              /*!< [0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74] Source Address Register of PDMA Channel 0~7                        */
+    __IO uint32_t DA;              /*!< [0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78] Destination Address Register of PDMA Channel 0~7                   */
+    __IO uint32_t NEXT;            /*!< [0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C]Next Scatter-Gather Descriptor Table Offset                         */
+
+} DSCT_T;
+
+typedef struct
+{
+    /**
+     * @var STRIDE_T::STCR
+     * Offset: 0x500/0x508/0x510/0x518/0x520/0x528  Stride Transfer Count Register of PDMA Channel 0~5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |STC       |PDMA Stride Transfer Count
+     * |        |          |The 16-bit register defines the stride transfer count of each row.
+     * @var STRIDE_T::ASOCR
+     * Offset: 0x504/0x50C/0x514/0x51C/0x524/0x52C  Address Stride Offset Register of PDMA Channel 0~5
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |SASOL     |VDMA Source Address Stride Offset Length
+     * |        |          |The 16-bit register defines the source address stride transfer offset count of each row.
+     * |[31:16] |DASOL     |VDMA Destination Address Stride Offset Length
+     * |        |          |The 16-bit register defines the destination address stride transfer offset count of each row.
+     */
+    __IO uint32_t STCR;           /*!< [0x0500/0x508/0x510/0x518/0x520/0x528] Stride Transfer Count Register of PDMA Channel 0~7                 */
+    __IO uint32_t ASOCR;          /*!< [0x0504/0x50C/0x514/0x51C/0x524/0x52C] Address Stride Offset Register of PDMA Channel 0                   */
+} STRIDE_T;
+
+typedef struct
+{
+    /**
+     * @var REPEAT_T::AICTL
+     * Offset: 0x600  Address Interval Control Register of PDMA Channel n
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |SAICNT    |PDMA Source Address Interval Count
+     * |        |          |The 16-bit register defines the source address interval count of each row.
+     * |[31:16] |DAICNT    |PDMA Destination Address Interval Count
+     * |        |          |The 16-bit register defines the destination  address interval count of each row.
+     * @var REPEAT_T::RCNT
+     * Offset: 0x604  Repeat Count Register of PDMA Channe n
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |RCNT      |PDMA Repeat Count
+     * |        |          |The 16-bit register defines the repeat times of block transfer.
+     */
+    __IO uint32_t AICTL;         /*!< [0x0600] Address Interval Control Register of PDMA Channel 0                 */
+    __IO uint32_t RCNT;          /*!< [0x0604] Repeat Count Register of PDMA Channel 0                             */
+} REPEAT_T;
+
+typedef struct
+{
+
+
+    /**
+     * @var PDMA_T::CURSCAT
+     * Offset: 0x80/0x84/0x88/0x8C/0x90/0x94/0x98/0x9C  Current Scatter-Gather Descriptor Table Address of PDMA Channel 0~7
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CURADDR   |PDMA Current Description Address Register (Read Only)
+     * |        |          |This field indicates a 32-bit current external description address of PDMA controller.
+     * |        |          |Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address.
+     * @var PDMA_T::CHCTL
+     * Offset: 0x400  PDMA Channel Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |CHENn     |PDMA Channel Enable Bit
+     * |        |          |Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.
+     * |        |          |0 = PDMA channel [n] Disabled.
+     * |        |          |1 = PDMA channel [n] Enabled.
+     * |        |          |Note: Set corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
+     * @var PDMA_T::PAUSE
+     * Offset: 0x404  PDMA Transfer Pause Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |PAUSEn    |PDMA Transfer Pause Control Register (Write Only)
+     * |        |          |User can set PAUSEn bit field to pause the PDMA transfer
+     * |        |          |When user sets PAUSEn bit, the PDMA controller will pause the on-going transfer, then clear the channel enable bit CHEN(PDMA_CHCTL [n], n=0,1..7) and clear request active flag
+     * |        |          |If re-enable the paused channel again, the remaining transfers will be processed.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Pause PDMA channel n transfer.
+     * @var PDMA_T::SWREQ
+     * Offset: 0x408  PDMA Software Request Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |SWREQn    |PDMA Software Request Register (Write Only)
+     * |        |          |Set this bit to 1 to generate a software request to PDMA [n].
+     * |        |          |0 = No effect.
+     * |        |          |1 = Generate a software request.
+     * |        |          |Note1: User can read PDMA_TRGSTS register to know which channel is on active
+     * |        |          |Active flag may be triggered by software request or peripheral request.
+     * |        |          |Note2: If user does not enable corresponding PDMA channel, the software request will be ignored.
+     * @var PDMA_T::TRGSTS
+     * Offset: 0x40C  PDMA Channel Request Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |REQSTSn   |PDMA Channel Request Status (Read Only)
+     * |        |          |This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral
+     * |        |          |When PDMA controller finishes channel transfer, this bit will be cleared automatically.
+     * |        |          |0 = PDMA Channel n has no request.
+     * |        |          |1 = PDMA Channel n has a request.
+     * |        |          |Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer.
+     * @var PDMA_T::PRISET
+     * Offset: 0x410  PDMA Fixed Priority Setting Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |FPRISETn  |PDMA Fixed Priority Setting Register
+     * |        |          |Set this bit to 1 to enable fixed priority level.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Set PDMA channel [n] to fixed priority channel.
+     * |        |          |Read Operation:
+     * |        |          |0 = Corresponding PDMA channel is round-robin priority.
+     * |        |          |1 = Corresponding PDMA channel is fixed priority.
+     * |        |          |Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
+     * @var PDMA_T::PRICLR
+     * Offset: 0x414  PDMA Fixed Priority Clear Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |FPRICLRn  |PDMA Fixed Priority Clear Register (Write Only)
+     * |        |          |Set this bit to 1 to clear fixed priority level.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear PDMA channel [n] fixed priority setting.
+     * |        |          |Note: User can read PDMA_PRISET register to know the channel priority.
+     * @var PDMA_T::INTEN
+     * Offset: 0x418  PDMA Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |INTENn    |PDMA Interrupt Enable Register
+     * |        |          |This field is used for enabling PDMA channel[n] interrupt.
+     * |        |          |0 = PDMA channel n interrupt Disabled.
+     * |        |          |1 = PDMA channel n interrupt Enabled.
+     * @var PDMA_T::INTSTS
+     * Offset: 0x41C  PDMA Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ABTIF     |PDMA Read/Write Target Abort Interrupt Flag (Read Only)
+     * |        |          |This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error.
+     * |        |          |0 = No AHB bus ERROR response received.
+     * |        |          |1 = AHB bus ERROR response received.
+     * |[1]     |TDIF      |Transfer Done Interrupt Flag (Read Only)
+     * |        |          |This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer.
+     * |        |          |0 = Not finished yet.
+     * |        |          |1 = PDMA channel has finished transmission.
+     * |[2]     |ALIGNF    |Transfer Alignment Interrupt Flag (Read Only)
+     * |        |          |0 = PDMA channel source address and destination address both follow transfer width setting.
+     * |        |          |1 = PDMA channel source address or destination address is not follow transfer width setting.
+     * |[8]     |REQTOF0   |Request Time-out Flag for Channel 0
+     * |        |          |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0, user can write 1 to clear these bits.
+     * |        |          |0 = No request time-out.
+     * |        |          |1 = Peripheral request time-out.
+     * |[9]     |REQTOF1   |Request Time-out Flag for Channel 1
+     * |        |          |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1, user can write 1 to clear these bits.
+     * |        |          |0 = No request time-out.
+     * |        |          |1 = Peripheral request time-out.
+     * @var PDMA_T::ABTSTS
+     * Offset: 0x420  PDMA Channel Read/Write Target Abort Flag Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |ABTIFn    |PDMA Read/Write Target Abort Interrupt Status Flag
+     * |        |          |This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
+     * |        |          |0 = No AHB bus ERROR response received when channel n transfer.
+     * |        |          |1 = AHB bus ERROR response received when channel n transfer.
+     * @var PDMA_T::TDSTS
+     * Offset: 0x424  PDMA Channel Transfer Done Flag Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |TDIFn     |Transfer Done Flag Register
+     * |        |          |This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
+     * |        |          |0 = PDMA channel transfer has not finished.
+     * |        |          |1 = PDMA channel has finished transmission.
+     * @var PDMA_T::ALIGN
+     * Offset: 0x428  PDMA Transfer Alignment Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |ALIGNn    |Transfer Alignment Flag Register
+     * |        |          |0 = PDMA channel source address and destination address both follow transfer width setting.
+     * |        |          |1 = PDMA channel source address or destination address is not follow transfer width setting.
+     * @var PDMA_T::TACTSTS
+     * Offset: 0x42C  PDMA Transfer Active Flag Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |TXACTFn   |Transfer on Active Flag Register (Read Only)
+     * |        |          |This bit indicates which PDMA channel is in active.
+     * |        |          |0 = PDMA channel is not finished.
+     * |        |          |1 = PDMA channel is active.
+     * @var PDMA_T::TOUTPSC
+     * Offset: 0x430  PDMA Time-out Prescaler Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |TOUTPSC0  |PDMA Channel 0 Time-out Clock Source Prescaler Bits
+     * |        |          |000 = PDMA channel 0 time-out clock source is HCLK/2^8.
+     * |        |          |001 = PDMA channel 0 time-out clock source is HCLK/2^9.
+     * |        |          |010 = PDMA channel 0 time-out clock source is HCLK/2^10.
+     * |        |          |011 = PDMA channel 0 time-out clock source is HCLK/2^11.
+     * |        |          |100 = PDMA channel 0 time-out clock source is HCLK/2^12.
+     * |        |          |101 = PDMA channel 0 time-out clock source is HCLK/2^13.
+     * |        |          |110 = PDMA channel 0 time-out clock source is HCLK/2^14.
+     * |        |          |111 = PDMA channel 0 time-out clock source is HCLK/2^15.
+     * |[6:4]   |TOUTPSC1  |PDMA Channel 1 Time-out Clock Source Prescaler Bits
+     * |        |          |000 = PDMA channel 1 time-out clock source is HCLK/2^8.
+     * |        |          |001 = PDMA channel 1 time-out clock source is HCLK/2^9.
+     * |        |          |010 = PDMA channel 1 time-out clock source is HCLK/2^10.
+     * |        |          |011 = PDMA channel 1 time-out clock source is HCLK/2^11.
+     * |        |          |100 = PDMA channel 1 time-out clock source is HCLK/2^12.
+     * |        |          |101 = PDMA channel 1 time-out clock source is HCLK/2^13.
+     * |        |          |110 = PDMA channel 1 time-out clock source is HCLK/2^14.
+     * |        |          |111 = PDMA channel 1 time-out clock source is HCLK/2^15.
+     * @var PDMA_T::TOUTEN
+     * Offset: 0x434  PDMA Time-out Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |TOUTEN0   |PDMA Channel 0 Time-out Enable Bit
+     * |        |          |0 = PDMA Channel 0 time-out function Disable.
+     * |        |          |1 = PDMA Channel 0 time-out function Enable.
+     * |[1]     |TOUTEN1   |PDMA Channel 1 Time-out Enable Bit
+     * |        |          |0 = PDMA Channel 1 time-out function Disable.
+     * |        |          |1 = PDMA Channel 1 time-out function Enable.
+     * @var PDMA_T::TOUTIEN
+     * Offset: 0x438  PDMA Time-out Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |TOUTIEN0  |PDMA Channel 0 Time-out Interrupt Enable Bit
+     * |        |          |0 = PDMA Channel 0 time-out interrupt Disable.
+     * |        |          |1 = PDMA Channel 0 time-out interrupt Enable.
+     * |[1]     |TOUTIEN1  |PDMA Channel 1 Time-out Interrupt Enable Bit
+     * |        |          |0 = PDMA Channel 1 time-out interrupt Disable.
+     * |        |          |1 = PDMA Channel 1 time-out interrupt Enable.
+     * @var PDMA_T::SCATBA
+     * Offset: 0x43C  PDMA Scatter-Gather Descriptor Table Base Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:16] |SCATBA    |PDMA Scatter-gather Descriptor Table Address Register
+     * |        |          |In Scatter-Gather mode, this is the base address for calculating the next link - list address
+     * |        |          |The next link address equation is
+     * |        |          |Next Link Address = PDMA_SCATBA + PDMA_DSCT_NEXT.
+     * |        |          |Note: Only useful in Scatter-Gather mode.
+     * @var PDMA_T::TOC0_1
+     * Offset: 0x440  PDMA Channel 0 and Channel 1 Time-out Counter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |TOC0      |Time-out Counter for Channel 0
+     * |        |          |This controls the period of time-out function for channel 0
+     * |        |          |The calculation unit is based on TOUTPSC0 (PDMA_TOUTPSC[2:0]) clock.
+     * |        |          |Time-out period = (Period of time-out clock) * (16-bit TOCn),n = 0,1.
+     * |[31:16] |TOC1      |Time-out Counter for Channel 1
+     * |        |          |This controls the period of time-out function for channel 1
+     * |        |          |The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC[5:3]) clock
+     * |        |          |The example of time-out period can refer TOC0 bit description.
+     * @var PDMA_T::CHRST
+     * Offset: 0x460  PDMA Channel Reset Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |CHnRST    |Channel N Reset
+     * |        |          |0 = corresponding channel n not reset.
+     * |        |          |1 = corresponding channel n is reset.
+     * @var PDMA_T::REQSEL0_3
+     * Offset: 0x480  PDMA Channel 0 to Channel 3 Request Source Select Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[6:0]   |REQSRC0   |Channel 0 Request Source Selection
+     * |        |          |This filed defines which peripheral is connected to PDMA channel 0
+     * |        |          |User can configure the peripheral by setting REQSRC0.
+     * |        |          |0 = Disable PDMA.
+     * |        |          |1 = Reserved.
+     * |        |          |2 = Channel connects to USB_TX.
+     * |        |          |3 = Channel connects to USB_RX.
+     * |        |          |4 = Channel connects to UART0_TX.
+     * |        |          |5 = Channel connects to UART0_RX.
+     * |        |          |6 = Channel connects to UART1_TX.
+     * |        |          |7 = Channel connects to UART1_RX.
+     * |        |          |8 = Channel connects to UART2_TX.
+     * |        |          |9 = Channel connects to UART2_RX.
+     * |        |          |10 = Channel connects to UART3_TX.
+     * |        |          |11 = Channel connects to UART3_RX.
+     * |        |          |12 = Channel connects to UART4_TX.
+     * |        |          |13 = Channel connects to UART4_RX.
+     * |        |          |14 = Channel connects to UART5_TX.
+     * |        |          |15 = Channel connects to UART5_RX.
+     * |        |          |16 = Channel connects to USCI0_TX.
+     * |        |          |17 = Channel connects to USCI0_RX.
+     * |        |          |18 = Channel connects to USCI1_TX.
+     * |        |          |19 = Channel connects to USCI1_RX.
+     * |        |          |20 = Channel connects to QSPI0_TX.
+     * |        |          |21 = Channel connects to QSPI0_RX.
+     * |        |          |22 = Channel connects to SPI0_TX.
+     * |        |          |23 = Channel connects to SPI0_RX.
+     * |        |          |24 = Channel connects to SPI1_TX.
+     * |        |          |25 = Channel connects to SPI1_RX.
+     * |        |          |26 = Channel connects to SPI2_TX.
+     * |        |          |27 = Channel connects to SPI2_RX.
+     * |        |          |28 = Channel connects to SPI3_TX.
+     * |        |          |29 = Channel connects to SPI3_RX.
+     * |        |          |30 = Channel connects to ADC_RX.
+     * |        |          |32 = Channel connects to EPWM0_P1_RX.
+     * |        |          |33 = Channel connects to EPWM0_P2_RX.
+     * |        |          |34 = Channel connects to EPWM0_P3_RX.
+     * |        |          |35 = Channel connects to EPWM1_P1_RX.
+     * |        |          |36 = Channel connects to EPWM1_P2_RX.
+     * |        |          |37 = Channel connects to EPWM1_P3_RX.
+     * |        |          |38 = Channel connects to I2C0_TX.
+     * |        |          |39 = Channel connects to I2C0_RX.
+     * |        |          |40 = Channel connects to I2C1_TX.
+     * |        |          |41 = Channel connects to I2C1_RX.
+     * |        |          |42 = Channel connects to I2C2_TX.
+     * |        |          |43 = Channel connects to I2C2_RX.
+     * |        |          |44 = Channel connects to I2S0_TX.
+     * |        |          |45 = Channel connects to I2S0_RX.
+     * |        |          |46 = Channel connects to TMR0.
+     * |        |          |47 = Channel connects to TMR1.
+     * |        |          |48 = Channel connects to TMR2.
+     * |        |          |49 = Channel connects to TMR3.
+     * |        |          |50 = Channel connects to TMR4.
+     * |        |          |51 = Channel connects to TMR5.
+     * |        |          |52 = Channel connects to DAC0_TX.
+     * |        |          |53 = Channel connects to DAC1_TX.
+     * |        |          |54 = Channel connects to EPWM0_CH0_TX.
+     * |        |          |55 = Channel connects to EPWM0_CH1_TX.
+     * |        |          |56 = Channel connects to EPWM0_CH2_TX.
+     * |        |          |57 = Channel connects to EPWM0_CH3_TX.
+     * |        |          |58 = Channel connects to EPWM0_CH4_TX.
+     * |        |          |59 = Channel connects to EPWM0_CH5_TX.
+     * |        |          |60 = Channel connects to EPWM1_CH0_TX.
+     * |        |          |61 = Channel connects to EPWM1_CH1_TX.
+     * |        |          |62 = Channel connects to EPWM1_CH2_TX.
+     * |        |          |63 = Channel connects to EPWM1_CH3_TX.
+     * |        |          |64 = Channel connects to EPWM1_CH4_TX.
+     * |        |          |65 = Channel connects to EPWM1_CH5_TX.
+     * |        |          |Others = Reserved.
+     * |        |          |Note 1: A request source cannot assign to two channels at the same time.
+     * |        |          |Note 2: This field is useless when transfer between memory and memory.
+     * |[14:8]  |REQSRC1   |Channel 1 Request Source Selection
+     * |        |          |This filed defines which peripheral is connected to PDMA channel 1
+     * |        |          |User can configure the peripheral setting by REQSRC1.
+     * |        |          |Note: The channel configuration is the same as REQSRC0 field
+     * |        |          |Please refer to the explanation of REQSRC0.
+     * |[22:16] |REQSRC2   |Channel 2 Request Source Selection
+     * |        |          |This filed defines which peripheral is connected to PDMA channel 2
+     * |        |          |User can configure the peripheral setting by REQSRC2.
+     * |        |          |Note: The channel configuration is the same as REQSRC0 field
+     * |        |          |Please refer to the explanation of REQSRC0.
+     * |[30:24] |REQSRC3   |Channel 3 Request Source Selection
+     * |        |          |This filed defines which peripheral is connected to PDMA channel 3
+     * |        |          |User can configure the peripheral setting by REQSRC3.
+     * |        |          |Note: The channel configuration is the same as REQSRC0 field
+     * |        |          |Please refer to the explanation of REQSRC0.
+     * @var PDMA_T::REQSEL4_7
+     * Offset: 0x484  PDMA Request Source Select Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[6:0]   |REQSRC4   |Channel 4 Request Source Selection
+     * |        |          |This filed defines which peripheral is connected to PDMA channel 4
+     * |        |          |User can configure the peripheral setting by REQSRC4.
+     * |        |          |Note: The channel configuration is the same as REQSRC0 field
+     * |        |          |Please refer to the explanation of REQSRC0.
+     * |[14:8]  |REQSRC5   |Channel 5 Request Source Selection
+     * |        |          |This filed defines which peripheral is connected to PDMA channel 5
+     * |        |          |User can configure the peripheral setting by REQSRC5.
+     * |        |          |Note: The channel configuration is the same as REQSRC0 field
+     * |        |          |Please refer to the explanation of REQSRC0.
+     * |[22:16] |REQSRC6   |Channel 6 Request Source Selection
+     * |        |          |This filed defines which peripheral is connected to PDMA channel 6
+     * |        |          |User can configure the peripheral setting by REQSRC6.
+     * |        |          |Note: The channel configuration is the same as REQSRC0 field
+     * |        |          |Please refer to the explanation of REQSRC0.
+     * |[30:24] |REQSRC7   |Channel 7 Request Source Selection
+     * |        |          |This filed defines which peripheral is connected to PDMA channel 7
+     * |        |          |User can configure the peripheral setting by REQSRC7.
+     * |        |          |Note: The channel configuration is the same as REQSRC0 field
+     * |        |          |Please refer to the explanation of REQSRC0.
+     */
+
+    DSCT_T        DSCT[8];               /*!< [0x0000 ~ 0x007C] DMA Embedded Description Table 0~7                      */
+    __I  uint32_t CURSCAT[8];            /*!< [0x0080~0x009C] Current Scatter-Gather Descriptor Table Address of PDMA Channel 0~7 */
+    __I  uint32_t RESERVE0[216];
+    __IO uint32_t CHCTL;                 /*!< [0x0400] PDMA Channel Control Register                                    */
+    __O  uint32_t PAUSE;                 /*!< [0x0404] PDMA Transfer Pause Control Register                             */
+    __O  uint32_t SWREQ;                 /*!< [0x0408] PDMA Software Request Register                                   */
+    __I  uint32_t TRGSTS;                /*!< [0x040c] PDMA Channel Request Status Register                             */
+    __IO uint32_t PRISET;                /*!< [0x0410] PDMA Fixed Priority Setting Register                             */
+    __O  uint32_t PRICLR;                /*!< [0x0414] PDMA Fixed Priority Clear Register                               */
+    __IO uint32_t INTEN;                 /*!< [0x0418] PDMA Interrupt Enable Register                                   */
+    __IO uint32_t INTSTS;                /*!< [0x041c] PDMA Interrupt Status Register                                   */
+    __IO uint32_t ABTSTS;                /*!< [0x0420] PDMA Channel Read/Write Target Abort Flag Register               */
+    __IO uint32_t TDSTS;                 /*!< [0x0424] PDMA Channel Transfer Done Flag Register                         */
+    __IO uint32_t ALIGN;                 /*!< [0x0428] PDMA Transfer Alignment Status Register                          */
+    __I  uint32_t TACTSTS;               /*!< [0x042c] PDMA Transfer Active Flag Register                               */
+    __IO uint32_t TOUTPSC;               /*!< [0x0430] PDMA Time-out Prescaler Register                                 */
+    __IO uint32_t TOUTEN;                /*!< [0x0434] PDMA Time-out Enable Register                                    */
+    __IO uint32_t TOUTIEN;               /*!< [0x0438] PDMA Time-out Interrupt Enable Register                          */
+    __IO uint32_t SCATBA;                /*!< [0x043c] PDMA Scatter-Gather Descriptor Table Base Address Register       */
+    __IO uint32_t TOC0_1;                /*!< [0x0440] PDMA Channel 0 and Channel 1 Time-out Counter Register           */
+    __I  uint32_t RESERVE1[7];
+    __IO uint32_t CHRST;                 /*!< [0x0460] PDMA Channel Reset Register                                      */
+    __I  uint32_t RESERVE2[7];
+    __IO uint32_t REQSEL0_3;             /*!< [0x0480] PDMA Channel 0 to Channel 3 Request Source Select Register       */
+    __IO uint32_t REQSEL4_7;             /*!< [0x0484] PDMA Channel 4 to Channel 7 Request Source Select Register       */
+    __I  uint32_t RESERVE4[30];
+    STRIDE_T      STRIDE[6];             /*!< [0x0500 ~ 0x052C] Stride function control register of PDMA Channel 0 ~ 5  */
+    __IO uint32_t RESERVE5[52];
+    REPEAT_T    REPEAT[2];               /*!< [0x0600 ~ 0x060C] Repeat Count Function Control Register of PDMA Channel 0 ~ 1 */
+} PDMA_T;
+
+
+
+
+/**
+    @addtogroup PDMA_CONST PDMA Bit Field Definition
+    Constant Definitions for PDMA Controller
+  @{
+*/
+
+#define PDMA_DSCT_CTL_OPMODE_Pos        (0)                                               /*!< PDMA_T::DSCT_CTL: OPMODE Position     */
+#define PDMA_DSCT_CTL_OPMODE_Msk        (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos)               /*!< PDMA_T::DSCT_CTL: OPMODE Mask         */
+
+#define PDMA_DSCT_CTL_TXTYPE_Pos        (2)                                               /*!< PDMA_T::DSCT_CTL: TXTYPE Position     */
+#define PDMA_DSCT_CTL_TXTYPE_Msk        (0x1ul << PDMA_DSCT_CTL_TXTYPE_Pos)               /*!< PDMA_T::DSCT_CTL: TXTYPE Mask         */
+
+#define PDMA_DSCT_CTL_BURSIZE_Pos       (4)                                               /*!< PDMA_T::DSCT_CTL: BURSIZE Position    */
+#define PDMA_DSCT_CTL_BURSIZE_Msk       (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos)              /*!< PDMA_T::DSCT_CTL: BURSIZE Mask        */
+
+#define PDMA_DSCT_CTL_TBINTDIS_Pos      (7)                                               /*!< PDMA_T::DSCT_CTL: TBINTDIS Position      */
+#define PDMA_DSCT_CTL_TBINTDIS_Msk      (0x1ul << PDMA_DSCT_CTL_TBINTDIS_Pos)             /*!< PDMA_T::DSCT_CTL: TBINTDIS Mask          */
+
+#define PDMA_DSCT_CTL_SAINC_Pos         (8)                                               /*!< PDMA_T::DSCT_CTL: SAINC Position      */
+#define PDMA_DSCT_CTL_SAINC_Msk         (0x3ul << PDMA_DSCT_CTL_SAINC_Pos)                /*!< PDMA_T::DSCT_CTL: SAINC Mask          */
+
+#define PDMA_DSCT_CTL_DAINC_Pos         (10)                                              /*!< PDMA_T::DSCT_CTL: DAINC Position      */
+#define PDMA_DSCT_CTL_DAINC_Msk         (0x3ul << PDMA_DSCT_CTL_DAINC_Pos)                /*!< PDMA_T::DSCT_CTL: DAINC Mask          */
+
+#define PDMA_DSCT_CTL_TXWIDTH_Pos       (12)                                              /*!< PDMA_T::DSCT_CTL: TXWIDTH Position    */
+#define PDMA_DSCT_CTL_TXWIDTH_Msk       (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos)              /*!< PDMA_T::DSCT_CTL: TXWIDTH Mask        */
+
+#define PDMA_DSCT_CTL_TXACK_Pos         (14)                                              /*!< PDMA_T::DSCT_CTL: TXACK Position      */
+#define PDMA_DSCT_CTL_TXACK_Msk         (0x1ul << PDMA_DSCT_CTL_TXACK_Pos)                /*!< PDMA_T::DSCT_CTL: TXACK Mask          */
+
+#define PDMA_DSCT_CTL_STRIDEEN_Pos     (15)                                               /*!< PDMA_T::DSCT_CTL: STRIDEEN Position  */
+#define PDMA_DSCT_CTL_STRIDEEN_Msk     (0x1ul << PDMA_DSCT_CTL_STRIDEEN_Pos)              /*!< PDMA_T::DSCT_CTL: STRIDEEN Mask      */
+
+#define PDMA_DSCT_CTL_TXCNT_Pos         (16)                                              /*!< PDMA_T::DSCT_CTL: TXCNT Position      */
+#define PDMA_DSCT_CTL_TXCNT_Msk         (0xfffful << PDMA_DSCT_CTL_TXCNT_Pos)             /*!< PDMA_T::DSCT_CTL: TXCNT Mask          */
+
+#define PDMA_DSCT_SA_SA_Pos             (0)                                               /*!< PDMA_T::DSCT_SA: SA Position          */
+#define PDMA_DSCT_SA_SA_Msk             (0xfffffffful << PDMA_DSCT_SA_SA_Pos)             /*!< PDMA_T::DSCT_SA: SA Mask              */
+
+#define PDMA_DSCT_DA_DA_Pos             (0)                                               /*!< PDMA_T::DSCT_DA: DA Position          */
+#define PDMA_DSCT_DA_DA_Msk             (0xfffffffful << PDMA_DSCT_DA_DA_Pos)             /*!< PDMA_T::DSCT_DA: DA Mask              */
+
+#define PDMA_DSCT_NEXT_NEXT_Pos         (0)                                               /*!< PDMA_T::DSCT_NEXT: NEXT Position      */
+#define PDMA_DSCT_NEXT_NEXT_Msk         (0xfffful << PDMA_DSCT_NEXT_NEXT_Pos)             /*!< PDMA_T::DSCT_NEXT: NEXT Mask          */
+
+#define PDMA_DSCT_NEXT_EXENEXT_Pos      (16)                                              /*!< PDMA_T::DSCT_FIRST: NEXT Position     */
+#define PDMA_DSCT_NEXT_EXENEXT_Msk      (0xfffful << PDMA_DSCT_NEXT_EXENEXT_Pos)           /*!< PDMA_T::DSCT_FIRST: NEXT Mask         */
+
+#define PDMA_CURSCAT_CURADDR_Pos        (0)                                               /*!< PDMA_T::CURSCAT: CURADDR Position     */
+#define PDMA_CURSCAT_CURADDR_Msk        (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos)        /*!< PDMA_T::CURSCAT: CURADDR Mask         */
+
+#define PDMA_CHCTL_CHENn_Pos            (0)                                               /*!< PDMA_T::CHCTL: CHENn Position          */
+#define PDMA_CHCTL_CHENn_Msk            (0xfffful << PDMA_CHCTL_CHENn_Pos)                /*!< PDMA_T::CHCTL: CHENn Mask              */
+
+#define PDMA_PAUSE_PAUSEn_Pos           (0)                                               /*!< PDMA_T::PAUSE: PAUSEn Position           */
+#define PDMA_PAUSE_PAUSEn_Msk           (0xfffful << PDMA_PAUSE_PAUSEn_Pos)              /*!< PDMA_T::PAUSE: PAUSEn Mask               */
+
+#define PDMA_SWREQ_SWREQn_Pos            (0)                                               /*!< PDMA_T::SWREQ: SWREQn Position         */
+#define PDMA_SWREQ_SWREQn_Msk            (0xfffful << PDMA_SWREQ_SWREQn_Pos)               /*!< PDMA_T::SWREQ: SWREQn Mask             */
+
+#define PDMA_TRGSTS_REQSTSn_Pos          (0)                                               /*!< PDMA_T::TRGSTS: REQSTSn Position       */
+#define PDMA_TRGSTS_REQSTSn_Msk          (0xfffful << PDMA_TRGSTS_REQSTSn_Pos)             /*!< PDMA_T::TRGSTS: REQSTSn Mask           */
+
+#define PDMA_PRISET_FPRISETn_Pos         (0)                                               /*!< PDMA_T::PRISET: FPRISETn Position      */
+#define PDMA_PRISET_FPRISETn_Msk         (0xfffful << PDMA_PRISET_FPRISETn_Pos)            /*!< PDMA_T::PRISET: FPRISETn Mask          */
+
+#define PDMA_PRICLR_FPRICLRn_Pos         (0)                                               /*!< PDMA_T::PRICLR: FPRICLRn Position      */
+#define PDMA_PRICLR_FPRICLRn_Msk         (0xfffful << PDMA_PRICLR_FPRICLRn_Pos)            /*!< PDMA_T::PRICLR: FPRICLRn Mask          */
+
+#define PDMA_INTEN_INTENn_Pos            (0)                                               /*!< PDMA_T::INTEN: INTENn Position         */
+#define PDMA_INTEN_INTENn_Msk            (0xfffful << PDMA_INTEN_INTENn_Pos)               /*!< PDMA_T::INTEN: INTENn Mask             */
+
+#define PDMA_INTSTS_ABTIF_Pos            (0)                                               /*!< PDMA_T::INTSTS: ABTIF Position         */
+#define PDMA_INTSTS_ABTIF_Msk            (0x1ul << PDMA_INTSTS_ABTIF_Pos)                  /*!< PDMA_T::INTSTS: ABTIF Mask             */
+
+#define PDMA_INTSTS_TDIF_Pos             (1)                                               /*!< PDMA_T::INTSTS: TDIF Position          */
+#define PDMA_INTSTS_TDIF_Msk             (0x1ul << PDMA_INTSTS_TDIF_Pos)                   /*!< PDMA_T::INTSTS: TDIF Mask              */
+
+#define PDMA_INTSTS_ALIGNF_Pos           (2)                                               /*!< PDMA_T::INTSTS: ALIGNF Position        */
+#define PDMA_INTSTS_ALIGNF_Msk           (0x1ul << PDMA_INTSTS_ALIGNF_Pos)                 /*!< PDMA_T::INTSTS: ALIGNF Mask            */
+
+#define PDMA_INTSTS_REQTOF0_Pos          (8)                                               /*!< PDMA_T::INTSTS: REQTOF0 Position       */
+#define PDMA_INTSTS_REQTOF0_Msk          (0x1ul << PDMA_INTSTS_REQTOF0_Pos)                /*!< PDMA_T::INTSTS: REQTOF0 Mask           */
+
+#define PDMA_INTSTS_REQTOF1_Pos          (9)                                               /*!< PDMA_T::INTSTS: REQTOF1 Position       */
+#define PDMA_INTSTS_REQTOF1_Msk          (0x1ul << PDMA_INTSTS_REQTOF1_Pos)                /*!< PDMA_T::INTSTS: REQTOF1 Mask           */
+
+#define PDMA_ABTSTS_ABTIF0_Pos           (0)                                               /*!< PDMA_T::ABTSTS: ABTIF0 Position        */
+#define PDMA_ABTSTS_ABTIF0_Msk           (0x1ul << PDMA_ABTSTS_ABTIF0_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF0 Mask            */
+
+#define PDMA_ABTSTS_ABTIF1_Pos           (1)                                               /*!< PDMA_T::ABTSTS: ABTIF1 Position        */
+#define PDMA_ABTSTS_ABTIF1_Msk           (0x1ul << PDMA_ABTSTS_ABTIF1_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF1 Mask            */
+
+#define PDMA_ABTSTS_ABTIF2_Pos           (2)                                               /*!< PDMA_T::ABTSTS: ABTIF2 Position        */
+#define PDMA_ABTSTS_ABTIF2_Msk           (0x1ul << PDMA_ABTSTS_ABTIF2_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF2 Mask            */
+
+#define PDMA_ABTSTS_ABTIF3_Pos           (3)                                               /*!< PDMA_T::ABTSTS: ABTIF3 Position        */
+#define PDMA_ABTSTS_ABTIF3_Msk           (0x1ul << PDMA_ABTSTS_ABTIF3_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF3 Mask            */
+
+#define PDMA_ABTSTS_ABTIF4_Pos           (4)                                               /*!< PDMA_T::ABTSTS: ABTIF4 Position        */
+#define PDMA_ABTSTS_ABTIF4_Msk           (0x1ul << PDMA_ABTSTS_ABTIF4_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF4 Mask            */
+
+#define PDMA_ABTSTS_ABTIF5_Pos           (5)                                               /*!< PDMA_T::ABTSTS: ABTIF5 Position        */
+#define PDMA_ABTSTS_ABTIF5_Msk           (0x1ul << PDMA_ABTSTS_ABTIF5_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF5 Mask            */
+
+#define PDMA_ABTSTS_ABTIF6_Pos           (6)                                               /*!< PDMA_T::ABTSTS: ABTIF6 Position        */
+#define PDMA_ABTSTS_ABTIF6_Msk           (0x1ul << PDMA_ABTSTS_ABTIF6_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF6 Mask            */
+
+#define PDMA_ABTSTS_ABTIF7_Pos           (7)                                               /*!< PDMA_T::ABTSTS: ABTIF7 Position        */
+#define PDMA_ABTSTS_ABTIF7_Msk           (0x1ul << PDMA_ABTSTS_ABTIF7_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF7 Mask            */
+
+#define PDMA_ABTSTS_ABTIF8_Pos           (8)                                               /*!< PDMA_T::ABTSTS: ABTIF8 Position        */
+#define PDMA_ABTSTS_ABTIF8_Msk           (0x1ul << PDMA_ABTSTS_ABTIF8_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF8 Mask            */
+
+#define PDMA_ABTSTS_ABTIF9_Pos           (9)                                               /*!< PDMA_T::ABTSTS: ABTIF9 Position        */
+#define PDMA_ABTSTS_ABTIF9_Msk           (0x1ul << PDMA_ABTSTS_ABTIF9_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF9 Mask            */
+
+#define PDMA_ABTSTS_ABTIF10_Pos           (10)                                               /*!< PDMA_T::ABTSTS: ABTIF10 Position        */
+#define PDMA_ABTSTS_ABTIF10_Msk           (0x1ul << PDMA_ABTSTS_ABTIF10_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF10 Mask            */
+
+#define PDMA_ABTSTS_ABTIF11_Pos           (11)                                               /*!< PDMA_T::ABTSTS: ABTIF11 Position        */
+#define PDMA_ABTSTS_ABTIF11_Msk           (0x1ul << PDMA_ABTSTS_ABTIF11_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF11 Mask            */
+
+#define PDMA_ABTSTS_ABTIF12_Pos           (12)                                               /*!< PDMA_T::ABTSTS: ABTIF12 Position        */
+#define PDMA_ABTSTS_ABTIF12_Msk           (0x1ul << PDMA_ABTSTS_ABTIF12_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF12 Mask            */
+
+#define PDMA_ABTSTS_ABTIF13_Pos           (13)                                               /*!< PDMA_T::ABTSTS: ABTIF13 Position        */
+#define PDMA_ABTSTS_ABTIF13_Msk           (0x1ul << PDMA_ABTSTS_ABTIF13_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF13 Mask            */
+
+#define PDMA_ABTSTS_ABTIF14_Pos           (14)                                               /*!< PDMA_T::ABTSTS: ABTIF14 Position        */
+#define PDMA_ABTSTS_ABTIF14_Msk           (0x1ul << PDMA_ABTSTS_ABTIF14_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF14 Mask            */
+
+#define PDMA_ABTSTS_ABTIF15_Pos           (15)                                               /*!< PDMA_T::ABTSTS: ABTIF15 Position        */
+#define PDMA_ABTSTS_ABTIF15_Msk           (0x1ul << PDMA_ABTSTS_ABTIF15_Pos)                 /*!< PDMA_T::ABTSTS: ABTIF15 Mask            */
+
+#define PDMA_TDSTS_TDIF0_Pos           (0)                                               /*!< PDMA_T::TDSTS: TDIF0 Position        */
+#define PDMA_TDSTS_TDIF0_Msk           (0x1ul << PDMA_TDSTS_TDIF0_Pos)                   /*!< PDMA_T::TDSTS: TDIF0 Mask            */
+
+#define PDMA_TDSTS_TDIF1_Pos           (1)                                               /*!< PDMA_T::TDSTS: TDIF1 Position        */
+#define PDMA_TDSTS_TDIF1_Msk           (0x1ul << PDMA_TDSTS_TDIF1_Pos)                   /*!< PDMA_T::TDSTS: TDIF1 Mask            */
+
+#define PDMA_TDSTS_TDIF2_Pos           (2)                                               /*!< PDMA_T::TDSTS: TDIF2 Position        */
+#define PDMA_TDSTS_TDIF2_Msk           (0x1ul << PDMA_TDSTS_TDIF2_Pos)                   /*!< PDMA_T::TDSTS: TDIF2 Mask            */
+
+#define PDMA_TDSTS_TDIF3_Pos           (3)                                               /*!< PDMA_T::TDSTS: TDIF3 Position        */
+#define PDMA_TDSTS_TDIF3_Msk           (0x1ul << PDMA_TDSTS_TDIF3_Pos)                   /*!< PDMA_T::TDSTS: TDIF3 Mask            */
+
+#define PDMA_TDSTS_TDIF4_Pos           (4)                                               /*!< PDMA_T::TDSTS: TDIF4 Position        */
+#define PDMA_TDSTS_TDIF4_Msk           (0x1ul << PDMA_TDSTS_TDIF4_Pos)                   /*!< PDMA_T::TDSTS: TDIF4 Mask            */
+
+#define PDMA_TDSTS_TDIF5_Pos           (5)                                               /*!< PDMA_T::TDSTS: TDIF5 Position        */
+#define PDMA_TDSTS_TDIF5_Msk           (0x1ul << PDMA_TDSTS_TDIF5_Pos)                   /*!< PDMA_T::TDSTS: TDIF5 Mask            */
+
+#define PDMA_TDSTS_TDIF6_Pos           (6)                                               /*!< PDMA_T::TDSTS: TDIF6 Position        */
+#define PDMA_TDSTS_TDIF6_Msk           (0x1ul << PDMA_TDSTS_TDIF6_Pos)                   /*!< PDMA_T::TDSTS: TDIF6 Mask            */
+
+#define PDMA_TDSTS_TDIF7_Pos           (7)                                               /*!< PDMA_T::TDSTS: TDIF7 Position        */
+#define PDMA_TDSTS_TDIF7_Msk           (0x1ul << PDMA_TDSTS_TDIF7_Pos)                   /*!< PDMA_T::TDSTS: TDIF7 Mask            */
+
+#define PDMA_TDSTS_TDIF8_Pos           (8)                                               /*!< PDMA_T::TDSTS: TDIF8 Position        */
+#define PDMA_TDSTS_TDIF8_Msk           (0x1ul << PDMA_TDSTS_TDIF8_Pos)                   /*!< PDMA_T::TDSTS: TDIF8 Mask            */
+
+#define PDMA_TDSTS_TDIF9_Pos           (9)                                               /*!< PDMA_T::TDSTS: TDIF9 Position        */
+#define PDMA_TDSTS_TDIF9_Msk           (0x1ul << PDMA_TDSTS_TDIF9_Pos)                   /*!< PDMA_T::TDSTS: TDIF9 Mask            */
+
+#define PDMA_TDSTS_TDIF10_Pos           (10)                                               /*!< PDMA_T::TDSTS: TDIF10 Position        */
+#define PDMA_TDSTS_TDIF10_Msk           (0x1ul << PDMA_TDSTS_TDIF10_Pos)                   /*!< PDMA_T::TDSTS: TDIF10 Mask            */
+
+#define PDMA_TDSTS_TDIF11_Pos           (11)                                               /*!< PDMA_T::TDSTS: TDIF11 Position        */
+#define PDMA_TDSTS_TDIF11_Msk           (0x1ul << PDMA_TDSTS_TDIF11_Pos)                   /*!< PDMA_T::TDSTS: TDIF11 Mask            */
+
+#define PDMA_TDSTS_TDIF12_Pos           (12)                                               /*!< PDMA_T::TDSTS: TDIF12 Position        */
+#define PDMA_TDSTS_TDIF12_Msk           (0x1ul << PDMA_TDSTS_TDIF12_Pos)                   /*!< PDMA_T::TDSTS: TDIF12 Mask            */
+
+#define PDMA_TDSTS_TDIF13_Pos           (13)                                               /*!< PDMA_T::TDSTS: TDIF13 Position        */
+#define PDMA_TDSTS_TDIF13_Msk           (0x1ul << PDMA_TDSTS_TDIF13_Pos)                   /*!< PDMA_T::TDSTS: TDIF13 Mask            */
+
+#define PDMA_TDSTS_TDIF14_Pos           (14)                                               /*!< PDMA_T::TDSTS: TDIF14 Position        */
+#define PDMA_TDSTS_TDIF14_Msk           (0x1ul << PDMA_TDSTS_TDIF14_Pos)                   /*!< PDMA_T::TDSTS: TDIF14 Mask            */
+
+#define PDMA_TDSTS_TDIF15_Pos           (15)                                               /*!< PDMA_T::TDSTS: TDIF15 Position        */
+#define PDMA_TDSTS_TDIF15_Msk           (0x1ul << PDMA_TDSTS_TDIF15_Pos)                   /*!< PDMA_T::TDSTS: TDIF15 Mask            */
+
+#define PDMA_ALIGN_ALIGNn_Pos           (0)                                                /*!< PDMA_T::ALIGN: ALIGNn Position        */
+#define PDMA_ALIGN_ALIGNn_Msk           (0xfffful << PDMA_ALIGN_ALIGNn_Pos)                /*!< PDMA_T::ALIGN: ALIGNn Mask            */
+
+#define PDMA_TACTSTS_TXACTFn_Pos         (0)                                               /*!< PDMA_T::TACTSTS: TXACTFn Position      */
+#define PDMA_TACTSTS_TXACTFn_Msk         (0xfffful << PDMA_TACTSTS_TXACTFn_Pos)            /*!< PDMA_T::TACTSTS: TXACTFn Mask          */
+
+#define PDMA_TOUTPSC_TOUTPSC0_Pos        (0)                                               /*!< PDMA_T::TOUTPSC: TOUTPSC0 Position     */
+#define PDMA_TOUTPSC_TOUTPSC0_Msk        (0x7ul << PDMA_TOUTPSC_TOUTPSC0_Pos)              /*!< PDMA_T::TOUTPSC: TOUTPSC0 Mask         */
+
+#define PDMA_TOUTPSC_TOUTPSC1_Pos        (4)                                               /*!< PDMA_T::TOUTPSC: TOUTPSC1 Position     */
+#define PDMA_TOUTPSC_TOUTPSC1_Msk        (0x7ul << PDMA_TOUTPSC_TOUTPSC1_Pos)              /*!< PDMA_T::TOUTPSC: TOUTPSC1 Mask         */
+
+#define PDMA_TOUTEN_TOUTENn_Pos          (0)                                               /*!< PDMA_T::TOUTEN: TOUTENn Position       */
+#define PDMA_TOUTEN_TOUTENn_Msk          (0x3ul << PDMA_TOUTEN_TOUTENn_Pos)                /*!< PDMA_T::TOUTEN: TOUTENn Mask           */
+
+#define PDMA_TOUTIEN_TOUTIENn_Pos        (0)                                               /*!< PDMA_T::TOUTIEN: TOUTIENn Position     */
+#define PDMA_TOUTIEN_TOUTIENn_Msk        (0x3ul << PDMA_TOUTIEN_TOUTIENn_Pos)              /*!< PDMA_T::TOUTIEN: TOUTIENn Mask         */
+
+#define PDMA_SCATBA_SCATBA_Pos           (16)                                              /*!< PDMA_T::SCATBA: SCATBA Position        */
+#define PDMA_SCATBA_SCATBA_Msk           (0xfffful << PDMA_SCATBA_SCATBA_Pos)              /*!< PDMA_T::SCATBA: SCATBA Mask            */
+
+#define PDMA_TOC0_1_TOC0_Pos             (0)                                               /*!< PDMA_T::TOC0_1: TOC0 Position          */
+#define PDMA_TOC0_1_TOC0_Msk             (0xfffful << PDMA_TOC0_1_TOC0_Pos)                /*!< PDMA_T::TOC0_1: TOC0 Mask              */
+
+#define PDMA_TOC0_1_TOC1_Pos             (16)                                              /*!< PDMA_T::TOC0_1: TOC1 Position          */
+#define PDMA_TOC0_1_TOC1_Msk             (0xfffful << PDMA_TOC0_1_TOC1_Pos)                /*!< PDMA_T::TOC0_1: TOC1 Mask              */
+
+#define PDMA_CHRST_CHnRST_Pos            (0)                                               /*!< PDMA_T::CHRST: CHnRST Position         */
+#define PDMA_CHRST_CHnRST_Msk            (0xfffful << PDMA_CHRST_CHnRST_Pos)               /*!< PDMA_T::CHRST: CHnRST Mask             */
+
+#define PDMA_REQSEL0_3_REQSRC0_Pos       (0)                                               /*!< PDMA_T::REQSEL0_3: REQSRC0 Position    */
+#define PDMA_REQSEL0_3_REQSRC0_Msk       (0x7ful << PDMA_REQSEL0_3_REQSRC0_Pos)            /*!< PDMA_T::REQSEL0_3: REQSRC0 Mask        */
+
+#define PDMA_REQSEL0_3_REQSRC1_Pos       (8)                                               /*!< PDMA_T::REQSEL0_3: REQSRC1 Position    */
+#define PDMA_REQSEL0_3_REQSRC1_Msk       (0x7ful << PDMA_REQSEL0_3_REQSRC1_Pos)            /*!< PDMA_T::REQSEL0_3: REQSRC1 Mask        */
+
+#define PDMA_REQSEL0_3_REQSRC2_Pos       (16)                                              /*!< PDMA_T::REQSEL0_3: REQSRC2 Position    */
+#define PDMA_REQSEL0_3_REQSRC2_Msk       (0x7ful << PDMA_REQSEL0_3_REQSRC2_Pos)            /*!< PDMA_T::REQSEL0_3: REQSRC2 Mask        */
+
+#define PDMA_REQSEL0_3_REQSRC3_Pos       (24)                                              /*!< PDMA_T::REQSEL0_3: REQSRC3 Position    */
+#define PDMA_REQSEL0_3_REQSRC3_Msk       (0x7ful << PDMA_REQSEL0_3_REQSRC3_Pos)            /*!< PDMA_T::REQSEL0_3: REQSRC3 Mask        */
+
+#define PDMA_REQSEL4_7_REQSRC4_Pos       (0)                                               /*!< PDMA_T::REQSEL4_7: REQSRC4 Position    */
+#define PDMA_REQSEL4_7_REQSRC4_Msk       (0x7ful << PDMA_REQSEL4_7_REQSRC4_Pos)            /*!< PDMA_T::REQSEL4_7: REQSRC4 Mask        */
+
+#define PDMA_REQSEL4_7_REQSRC5_Pos       (8)                                               /*!< PDMA_T::REQSEL4_7: REQSRC5 Position    */
+#define PDMA_REQSEL4_7_REQSRC5_Msk       (0x7ful << PDMA_REQSEL4_7_REQSRC5_Pos)            /*!< PDMA_T::REQSEL4_7: REQSRC5 Mask        */
+
+#define PDMA_REQSEL4_7_REQSRC6_Pos       (16)                                              /*!< PDMA_T::REQSEL4_7: REQSRC6 Position    */
+#define PDMA_REQSEL4_7_REQSRC6_Msk       (0x7ful << PDMA_REQSEL4_7_REQSRC6_Pos)            /*!< PDMA_T::REQSEL4_7: REQSRC6 Mask        */
+
+#define PDMA_REQSEL4_7_REQSRC7_Pos       (24)                                              /*!< PDMA_T::REQSEL4_7: REQSRC7 Position    */
+#define PDMA_REQSEL4_7_REQSRC7_Msk       (0x7ful << PDMA_REQSEL4_7_REQSRC7_Pos)            /*!< PDMA_T::REQSEL4_7: REQSRC7 Mask        */
+
+#define PDMA_STCRn_STC_Pos               (0)                                               /*!< PDMA_T::STCRn: STC Position            */
+#define PDMA_STCRn_STC_Msk               (0xfffful << PDMA_STCRn_STC_Pos)                  /*!< PDMA_T::STCRn: STC Mask                */
+
+#define PDMA_ASOCRn_SASOL_Pos            (0)                                               /*!< PDMA_T::ASOCRn: SASOL Position         */
+#define PDMA_ASOCRn_SASOL_Msk            (0xfffful << PDMA_ASOCRn_SASOL_Pos)               /*!< PDMA_T::ASOCRn: SASOL Mask             */
+
+#define PDMA_ASOCRn_DASOL_Pos            (16)                                              /*!< PDMA_T::ASOCRn: DASOL Position         */
+#define PDMA_ASOCRn_DASOL_Msk            (0xfffful << PDMA_ASOCRn_DASOL_Pos)               /*!< PDMA_T::ASOCRn: DASOL Mask             */
+
+#define PDMA_AICTLn_SAICNT_Pos           (0)                                               /*!< PDMA_T::AICTLn: SAICNT Position        */
+#define PDMA_AICTLn_SAICNT_Msk           (0xfffful << PDMA_ASOCRn_SASOL_Pos)               /*!< PDMA_T::AICTLn: SAICNT Mask            */
+
+#define PDMA_AICTLn_DAICNT_Pos           (16)                                              /*!< PDMA_T::AICTLn: DAICNT Position        */
+#define PDMA_AICTLn_DAICNT_Msk           (0xfffful << PDMA_ASOCRn_DASOL_Pos)               /*!< PDMA_T::AICTLn: DAICNT Mask            */
+
+#define PDMA_RCNTn_RCNT_Pos              (0)                                               /*!< PDMA_T::RCNTn: RCNT Position           */
+#define PDMA_RCNTn_RCNT_Msk              (0xfffful << PDMA_STCRn_RCNT_Pos)                 /*!< PDMA_T::RCNTn: RCNT Mask               */
+
+/**@}*/ /* PDMA_CONST */
+/**@}*/ /* end of PDMA register group */
+/**@}*/ /* end of REGISTER group */
+
+
+#endif /* __PDMA_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/qei_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/qei_reg.h
new file mode 100644
index 0000000000..42a14c9d52
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/qei_reg.h
@@ -0,0 +1,308 @@
+/**************************************************************************//**
+ * @file     qei_reg.h
+ * @version  V1.00
+ * @brief    QEI register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __QEI_REG_H__
+#define __QEI_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+/*---------------------- Quadrature Encoder Interface -------------------------*/
+/**
+    @addtogroup QEI Quadrature Encoder Interface(QEI)
+    Memory Mapped Structure for QEI Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var QEI_T::CNT
+     * Offset: 0x00  QEI Counter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CNT       |Quadrature Encoder Interface Counter
+     * |        |          |A 32-bit up/down counter
+     * |        |          |When an effective phase pulse is detected, this counter is increased by one if the bit DIRF (QEI_STATUS[8]) is one or decreased by one if the bit DIRF is zero
+     * |        |          |This register performs an integrator which count value is proportional to the encoder position
+     * |        |          |The pulse counter may be initialized to a predetermined value by one of three events occurs:
+     * |        |          |1. Software is written if QEIEN (QEI_CTL[29]) = 0.
+     * |        |          |2. Compare-match event if QEIEN=1 and QEI is in compare-counting mode.
+     * |        |          |3. Index signal change if QEIEN=1 and IDXRLDEN (QEI_CTL[27])=1.
+     * @var QEI_T::CNTHOLD
+     * Offset: 0x04  QEI Counter Hold Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CNTHOLD   |Quadrature Encoder Interface Counter Hold
+     * |        |          |When bit HOLDCNT (QEI_CTL[24]) goes from low to high, the CNT(QEI_CNT[31:0]) is copied into CNTHOLD (QEI_CNTHOLD[31:0]) register.
+     * @var QEI_T::CNTLATCH
+     * Offset: 0x08  QEI Counter Index Latch Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CNTLATCH  |Quadrature Encoder Interface Counter Index Latch
+     * |        |          |When the IDXF (QEI_STATUS[0]) bit is set, the CNT(QEI_CNT[31:0]) is copied into CNTLATCH (QEI_CNTLATCH[31:0]) register.
+     * @var QEI_T::CNTCMP
+     * Offset: 0x0C  QEI Counter Compare Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CNTCMP    |Quadrature Encoder Interface Counter Compare
+     * |        |          |If the QEI controller is in the compare-counting mode CMPEN (QEI_CTL[28]) =1, when the value of CNT(QEI_CNT[31:0]) matches CNTCMP(QEI_CNTCMP[31:0]), CMPF will be set
+     * |        |          |This register is software writable.
+     * @var QEI_T::CNTMAX
+     * Offset: 0x14  QEI Pre-set Maximum Count Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |CNTMAX    |Quadrature Encoder Interface Preset Maximum Count
+     * |        |          |This register value determined by user stores the maximum value which may be the number of the QEI counter for the QEI controller compare-counting mode
+     * @var QEI_T::CTL
+     * Offset: 0x18  QEI Controller Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |NFCLKSEL  |Noise Filter Clock Pre-divide Selection
+     * |        |          |To determine the sampling frequency of the Noise Filter clock .
+     * |        |          |000 = QEI_CLK.
+     * |        |          |001 = QEI_CLK/2.
+     * |        |          |010 = QEI_CLK/4.
+     * |        |          |011 = QEI_CLK/16.
+     * |        |          |100 = QEI_CLK/32.
+     * |        |          |101 = QEI_CLK/64.
+     * |[3]     |NFDIS     |QEI Controller Input Noise Filter Disable Bit
+     * |        |          |0 = The noise filter of QEI controller Enabled.
+     * |        |          |1 = The noise filter of QEI controller Disabled.
+     * |[4]     |CHAEN     |QEA Input to QEI Controller Enable Bit
+     * |        |          |0 = QEA input to QEI Controller Disabled.
+     * |        |          |1 = QEA input to QEI Controller Enabled.
+     * |[5]     |CHBEN     |QEB Input to QEI Controller Enable Bit
+     * |        |          |0 = QEB input to QEI Controller Disabled.
+     * |        |          |1 = QEB input to QEI Controller Enabled.
+     * |[6]     |IDXEN     |IDX Input to QEI Controller Enable Bit
+     * |        |          |0 = IDX input to QEI Controller Disabled.
+     * |        |          |1 = IDX input to QEI Controller Enabled.
+     * |[9:8]   |MODE      |QEI Counting Mode Selection
+     * |        |          |There are four quadrature encoder pulse counter operation modes.
+     * |        |          |00 = X4 Free-counting Mode.
+     * |        |          |01 = X2 Free-counting Mode.
+     * |        |          |10 = X4 Compare-counting Mode.
+     * |        |          |11 = X2 Compare-counting Mode.
+     * |[12]    |CHAINV    |Inverse QEA Input Polarity
+     * |        |          |0 = Not inverse QEA input polarity.
+     * |        |          |1 = QEA input polarity is inverse to QEI controller.
+     * |[13]    |CHBINV    |Inverse QEB Input Polarity
+     * |        |          |0 = Not inverse QEB input polarity.
+     * |        |          |1 = QEB input polarity is inverse to QEI controller.
+     * |[14]    |IDXINV    |Inverse IDX Input Polarity
+     * |        |          |0 = Not inverse IDX input polarity.
+     * |        |          |1 = IDX input polarity is inverse to QEI controller.
+     * |[16]    |OVUNIEN   |OVUNF Trigger QEI Interrupt Enable Bit
+     * |        |          |0 = OVUNF can trigger QEI controller interrupt Disabled.
+     * |        |          |1 = OVUNF can trigger QEI controller interrupt Enabled.
+     * |[17]    |DIRIEN    |DIRCHGF Trigger QEI Interrupt Enable Bit
+     * |        |          |0 = DIRCHGF can trigger QEI controller interrupt Disabled.
+     * |        |          |1 = DIRCHGF can trigger QEI controller interrupt Enabled.
+     * |[18]    |CMPIEN    |CMPF Trigger QEI Interrupt Enable Bit
+     * |        |          |0 = CMPF can trigger QEI controller interrupt Disabled.
+     * |        |          |1 = CMPF can trigger QEI controller interrupt Enabled.
+     * |[19]    |IDXIEN    |IDXF Trigger QEI Interrupt Enable Bit
+     * |        |          |0 = The IDXF can trigger QEI interrupt Disabled.
+     * |        |          |1 = The IDXF can trigger QEI interrupt Enabled.
+     * |[20]    |HOLDTMR0  |Hold QEI_CNT by Timer 0
+     * |        |          |0 = TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT.
+     * |        |          |1 = A rising edge of bit TIF(TIMER0_INTSTS[0]) in timer 0 sets HOLDCNT to 1.
+     * |[21]    |HOLDTMR1  |Hold QEI_CNT by Timer 1
+     * |        |          |0 = TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT.
+     * |        |          |1 = A rising edge of bit TIF (TIMER1_INTSTS[0]) in timer 1 sets HOLDCNT to 1.
+     * |[22]    |HOLDTMR2  |Hold QEI_CNT by Timer 2
+     * |        |          |0 = TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT.
+     * |        |          |1 = A rising edge of bit TIF(TIMER2_INTSTS[0]) in timer 2 sets HOLDCNT to 1.
+     * |[23]    |HOLDTMR3  |Hold QEI_CNT by Timer 3
+     * |        |          |0 = TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT.
+     * |        |          |1 = A rising edge of bit TIF(TIMER3_INTSTS[0]) in timer 3 sets HOLDCNT to 1.
+     * |[24]    |HOLDCNT   |Hold QEI_CNT Control
+     * |        |          |When this bit is set from low to high, the CNT(QEI_CNT[31:0]) is copied into QEI_CNTHOLD
+     * |        |          |This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TIMERx_INTSTS[0]).
+     * |        |          |0 = No operation.
+     * |        |          |1 = QEI_CNT content is captured and stored in QEI_CNTHOLD.
+     * |        |          |Note: This bit is automatically cleared after QEI_CNTHOLD holds QEI_CNT value.
+     * |[25]    |IDXLATEN  |Index Latch QEI_CNT Enable Bit
+     * |        |          |If this bit is set to high, the QEI_CNT content will be latched into QEI_CNTLATCH at every rising on signal CHX.
+     * |        |          |0 = The index signal latch QEI counter function Disabled.
+     * |        |          |1 = The index signal latch QEI counter function Enabled.
+     * |[27]    |IDXRLDEN  |Index Trigger QEI_CNT Reload Enable Bit
+     * |        |          |When this bit is high and a rising edge comes on signal CHX, the QEI_CNT will be reset to zero if the counter is in up-counting type (DIRF = 1); while the QEI_CNT will be reloaded with CNTMAX (QEI_CNTMAX[31:0]) content if the counter is in down-counting type (DIRF = 0).
+     * |        |          |0 = Reload function Disabled.
+     * |        |          |1 = QEI_CNT re-initialized by Index signal Enabled.
+     * |[28]    |CMPEN     |the Compare Function Enable Bit
+     * |        |          |The compare function in QEI controller is to compare the dynamic counting QEI_CNT with the compare register CNTCMP( QEI_CNTCMP[31:0]), if CNT(QEI_CNT[31:0]) reaches CNTCMP( QEI_CNTCMP[31:0]), the flag CMPF will be set.
+     * |        |          |0 = Compare function Disabled.
+     * |        |          |1 = Compare function Enabled.
+     * |[29]    |QEIEN     |Quadrature Encoder Interface Controller Enable Bit
+     * |        |          |0 = QEI controller function Disabled.
+     * |        |          |1 = QEI controller function Enabled.
+     * @var QEI_T::STATUS
+     * Offset: 0x2C  QEI Controller Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |IDXF      |IDX Detected Flag
+     * |        |          |When the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high.
+     * |        |          |0 = No rising edge detected on signal CHX.
+     * |        |          |1 = A rising edge occurs on signal CHX.
+     * |        |          |Note: This bit is only cleared by writing 1 to it.
+     * |[1]     |CMPF      |Compare-match Flag
+     * |        |          |If the QEI compare function is enabled, the flag is set by hardware while QEI counter up or down counts and reach to the CNTCMP(QEI_CNTCMP[31:0]).
+     * |        |          |0 = QEI counter does not match with CNTCMP(QEI_CNTCMP[31:0]).
+     * |        |          |1 = QEI counter counts to the same as CNTCMP(QEI_CNTCMP[31:0]).
+     * |        |          |Note: This bit is only cleared by writing 1 to it.
+     * |[2]     |OVUNF     |QEI Counter Overflow or Underflow Flag
+     * |        |          |Flag is set by hardware while QEI_CNT overflows from 0xFFFF_FFFF to zero in free-counting mode or from the CNTMAX (QEI_CNTMAX[31:0]) to zero in compare-counting mode
+     * |        |          |Similarly, the flag is set wile QEI counter underflow from zero to 0xFFFF_FFFF or CNTMAX (QEI_CNTMAX[31:0]).
+     * |        |          |0 = No overflow or underflow occurs in QEI counter.
+     * |        |          |1 = QEI counter occurs counting overflow or underflow.
+     * |        |          |Note: This bit is only cleared by writing 1 to it.
+     * |[3]     |DIRCHGF   |Direction Change Flag
+     * |        |          |Flag is set by hardware while QEI counter counting direction is changed
+     * |        |          |Software can clear this bit by writing 1 to it.
+     * |        |          |0 = No change in QEI counter counting direction.
+     * |        |          |1 = QEI counter counting direction is changed.
+     * |        |          |Note: This bit is only cleared by writing 1 to it.
+     * |[8]     |DIRF      |QEI Counter Counting Direction Indication
+     * |        |          |0 = QEI Counter is in down-counting.
+     * |        |          |1 = QEI Counter is in up-counting.
+     * |        |          |Note: This bit is set/reset by hardware according to the phase detection between CHA and CHB.
+     */
+    __IO uint32_t CNT;                   /*!< [0x0000] QEI Counter Register                                             */
+    __IO uint32_t CNTHOLD;               /*!< [0x0004] QEI Counter Hold Register                                        */
+    __IO uint32_t CNTLATCH;              /*!< [0x0008] QEI Counter Index Latch Register                                 */
+    __IO uint32_t CNTCMP;                /*!< [0x000c] QEI Counter Compare Register                                     */
+    __I  uint32_t RESERVE0[1];
+    __IO uint32_t CNTMAX;                /*!< [0x0014] QEI Pre-set Maximum Count Register                               */
+    __IO uint32_t CTL;                   /*!< [0x0018] QEI Controller Control Register                                  */
+    __I  uint32_t RESERVE1[4];
+    __IO uint32_t STATUS;                /*!< [0x002c] QEI Controller Status Register                                   */
+
+} QEI_T;
+
+/**
+    @addtogroup QEI_CONST QEI Bit Field Definition
+    Constant Definitions for QEI Controller
+  @{
+*/
+
+#define QEI_CNT_CNT_Pos                  (0)                                               /*!< QEI_T::CNT: CNT Position               */
+#define QEI_CNT_CNT_Msk                  (0xfffffffful << QEI_CNT_CNT_Pos)                 /*!< QEI_T::CNT: CNT Mask                   */
+
+#define QEI_CNTHOLD_CNTHOLD_Pos          (0)                                               /*!< QEI_T::CNTHOLD: CNTHOLD Position       */
+#define QEI_CNTHOLD_CNTHOLD_Msk          (0xfffffffful << QEI_CNTHOLD_CNTHOLD_Pos)         /*!< QEI_T::CNTHOLD: CNTHOLD Mask           */
+
+#define QEI_CNTLATCH_CNTLATCH_Pos        (0)                                               /*!< QEI_T::CNTLATCH: CNTLATCH Position     */
+#define QEI_CNTLATCH_CNTLATCH_Msk        (0xfffffffful << QEI_CNTLATCH_CNTLATCH_Pos)       /*!< QEI_T::CNTLATCH: CNTLATCH Mask         */
+
+#define QEI_CNTCMP_CNTCMP_Pos            (0)                                               /*!< QEI_T::CNTCMP: CNTCMP Position         */
+#define QEI_CNTCMP_CNTCMP_Msk            (0xfffffffful << QEI_CNTCMP_CNTCMP_Pos)           /*!< QEI_T::CNTCMP: CNTCMP Mask             */
+
+#define QEI_CNTMAX_CNTMAX_Pos            (0)                                               /*!< QEI_T::CNTMAX: CNTMAX Position         */
+#define QEI_CNTMAX_CNTMAX_Msk            (0xfffffffful << QEI_CNTMAX_CNTMAX_Pos)           /*!< QEI_T::CNTMAX: CNTMAX Mask             */
+
+#define QEI_CTL_NFCLKSEL_Pos             (0)                                               /*!< QEI_T::CTL: NFCLKSEL Position          */
+#define QEI_CTL_NFCLKSEL_Msk             (0x7ul << QEI_CTL_NFCLKSEL_Pos)                   /*!< QEI_T::CTL: NFCLKSEL Mask              */
+
+#define QEI_CTL_NFDIS_Pos                (3)                                               /*!< QEI_T::CTL: NFDIS Position             */
+#define QEI_CTL_NFDIS_Msk                (0x1ul << QEI_CTL_NFDIS_Pos)                      /*!< QEI_T::CTL: NFDIS Mask                 */
+
+#define QEI_CTL_CHAEN_Pos                (4)                                               /*!< QEI_T::CTL: CHAEN Position             */
+#define QEI_CTL_CHAEN_Msk                (0x1ul << QEI_CTL_CHAEN_Pos)                      /*!< QEI_T::CTL: CHAEN Mask                 */
+
+#define QEI_CTL_CHBEN_Pos                (5)                                               /*!< QEI_T::CTL: CHBEN Position             */
+#define QEI_CTL_CHBEN_Msk                (0x1ul << QEI_CTL_CHBEN_Pos)                      /*!< QEI_T::CTL: CHBEN Mask                 */
+
+#define QEI_CTL_IDXEN_Pos                (6)                                               /*!< QEI_T::CTL: IDXEN Position             */
+#define QEI_CTL_IDXEN_Msk                (0x1ul << QEI_CTL_IDXEN_Pos)                      /*!< QEI_T::CTL: IDXEN Mask                 */
+
+#define QEI_CTL_MODE_Pos                 (8)                                               /*!< QEI_T::CTL: MODE Position              */
+#define QEI_CTL_MODE_Msk                 (0x3ul << QEI_CTL_MODE_Pos)                       /*!< QEI_T::CTL: MODE Mask                  */
+
+#define QEI_CTL_CHAINV_Pos               (12)                                              /*!< QEI_T::CTL: CHAINV Position            */
+#define QEI_CTL_CHAINV_Msk               (0x1ul << QEI_CTL_CHAINV_Pos)                     /*!< QEI_T::CTL: CHAINV Mask                */
+
+#define QEI_CTL_CHBINV_Pos               (13)                                              /*!< QEI_T::CTL: CHBINV Position            */
+#define QEI_CTL_CHBINV_Msk               (0x1ul << QEI_CTL_CHBINV_Pos)                     /*!< QEI_T::CTL: CHBINV Mask                */
+
+#define QEI_CTL_IDXINV_Pos               (14)                                              /*!< QEI_T::CTL: IDXINV Position            */
+#define QEI_CTL_IDXINV_Msk               (0x1ul << QEI_CTL_IDXINV_Pos)                     /*!< QEI_T::CTL: IDXINV Mask                */
+
+#define QEI_CTL_OVUNIEN_Pos              (16)                                              /*!< QEI_T::CTL: OVUNIEN Position           */
+#define QEI_CTL_OVUNIEN_Msk              (0x1ul << QEI_CTL_OVUNIEN_Pos)                    /*!< QEI_T::CTL: OVUNIEN Mask               */
+
+#define QEI_CTL_DIRIEN_Pos               (17)                                              /*!< QEI_T::CTL: DIRIEN Position            */
+#define QEI_CTL_DIRIEN_Msk               (0x1ul << QEI_CTL_DIRIEN_Pos)                     /*!< QEI_T::CTL: DIRIEN Mask                */
+
+#define QEI_CTL_CMPIEN_Pos               (18)                                              /*!< QEI_T::CTL: CMPIEN Position            */
+#define QEI_CTL_CMPIEN_Msk               (0x1ul << QEI_CTL_CMPIEN_Pos)                     /*!< QEI_T::CTL: CMPIEN Mask                */
+
+#define QEI_CTL_IDXIEN_Pos               (19)                                              /*!< QEI_T::CTL: IDXIEN Position            */
+#define QEI_CTL_IDXIEN_Msk               (0x1ul << QEI_CTL_IDXIEN_Pos)                     /*!< QEI_T::CTL: IDXIEN Mask                */
+
+#define QEI_CTL_HOLDTMR0_Pos             (20)                                              /*!< QEI_T::CTL: HOLDTMR0 Position          */
+#define QEI_CTL_HOLDTMR0_Msk             (0x1ul << QEI_CTL_HOLDTMR0_Pos)                   /*!< QEI_T::CTL: HOLDTMR0 Mask              */
+
+#define QEI_CTL_HOLDTMR1_Pos             (21)                                              /*!< QEI_T::CTL: HOLDTMR1 Position          */
+#define QEI_CTL_HOLDTMR1_Msk             (0x1ul << QEI_CTL_HOLDTMR1_Pos)                   /*!< QEI_T::CTL: HOLDTMR1 Mask              */
+
+#define QEI_CTL_HOLDTMR2_Pos             (22)                                              /*!< QEI_T::CTL: HOLDTMR2 Position          */
+#define QEI_CTL_HOLDTMR2_Msk             (0x1ul << QEI_CTL_HOLDTMR2_Pos)                   /*!< QEI_T::CTL: HOLDTMR2 Mask              */
+
+#define QEI_CTL_HOLDTMR3_Pos             (23)                                              /*!< QEI_T::CTL: HOLDTMR3 Position          */
+#define QEI_CTL_HOLDTMR3_Msk             (0x1ul << QEI_CTL_HOLDTMR3_Pos)                   /*!< QEI_T::CTL: HOLDTMR3 Mask              */
+
+#define QEI_CTL_HOLDCNT_Pos              (24)                                              /*!< QEI_T::CTL: HOLDCNT Position           */
+#define QEI_CTL_HOLDCNT_Msk              (0x1ul << QEI_CTL_HOLDCNT_Pos)                    /*!< QEI_T::CTL: HOLDCNT Mask               */
+
+#define QEI_CTL_IDXLATEN_Pos             (25)                                              /*!< QEI_T::CTL: IDXLATEN Position          */
+#define QEI_CTL_IDXLATEN_Msk             (0x1ul << QEI_CTL_IDXLATEN_Pos)                   /*!< QEI_T::CTL: IDXLATEN Mask              */
+
+#define QEI_CTL_IDXRLDEN_Pos             (27)                                              /*!< QEI_T::CTL: IDXRLDEN Position          */
+#define QEI_CTL_IDXRLDEN_Msk             (0x1ul << QEI_CTL_IDXRLDEN_Pos)                   /*!< QEI_T::CTL: IDXRLDEN Mask              */
+
+#define QEI_CTL_CMPEN_Pos                (28)                                              /*!< QEI_T::CTL: CMPEN Position             */
+#define QEI_CTL_CMPEN_Msk                (0x1ul << QEI_CTL_CMPEN_Pos)                      /*!< QEI_T::CTL: CMPEN Mask                 */
+
+#define QEI_CTL_QEIEN_Pos                (29)                                              /*!< QEI_T::CTL: QEIEN Position             */
+#define QEI_CTL_QEIEN_Msk                (0x1ul << QEI_CTL_QEIEN_Pos)                      /*!< QEI_T::CTL: QEIEN Mask                 */
+
+#define QEI_STATUS_IDXF_Pos              (0)                                               /*!< QEI_T::STATUS: IDXF Position           */
+#define QEI_STATUS_IDXF_Msk              (0x1ul << QEI_STATUS_IDXF_Pos)                    /*!< QEI_T::STATUS: IDXF Mask               */
+
+#define QEI_STATUS_CMPF_Pos              (1)                                               /*!< QEI_T::STATUS: CMPF Position           */
+#define QEI_STATUS_CMPF_Msk              (0x1ul << QEI_STATUS_CMPF_Pos)                    /*!< QEI_T::STATUS: CMPF Mask               */
+
+#define QEI_STATUS_OVUNF_Pos             (2)                                               /*!< QEI_T::STATUS: OVUNF Position          */
+#define QEI_STATUS_OVUNF_Msk             (0x1ul << QEI_STATUS_OVUNF_Pos)                   /*!< QEI_T::STATUS: OVUNF Mask              */
+
+#define QEI_STATUS_DIRCHGF_Pos           (3)                                               /*!< QEI_T::STATUS: DIRCHGF Position        */
+#define QEI_STATUS_DIRCHGF_Msk           (0x1ul << QEI_STATUS_DIRCHGF_Pos)                 /*!< QEI_T::STATUS: DIRCHGF Mask            */
+
+#define QEI_STATUS_DIRF_Pos              (8)                                               /*!< QEI_T::STATUS: DIRF Position           */
+#define QEI_STATUS_DIRF_Msk              (0x1ul << QEI_STATUS_DIRF_Pos)                    /*!< QEI_T::STATUS: DIRF Mask               */
+
+/**@}*/ /* QEI_CONST */
+/**@}*/ /* end of QEI register group */
+/**@}*/ /* end of REGISTER group */
+
+
+#endif /* __QEI_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/qspi_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/qspi_reg.h
new file mode 100644
index 0000000000..23e18e0e31
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/qspi_reg.h
@@ -0,0 +1,622 @@
+/**************************************************************************//**
+ * @file     qspi_reg.h
+ * @version  V1.00
+ * @brief    QSPI register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __QSPI_REG_H__
+#define __QSPI_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+/*---------------------- Quad Serial Peripheral Interface Controller -------------------------*/
+/**
+    @addtogroup QSPI Quad Serial Peripheral Interface Controller(QSPI)
+    Memory Mapped Structure for QSPI Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var QSPI_T::CTL
+     * Offset: 0x00  QSPI Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SPIEN     |QSPI Transfer Control Enable Bit
+     * |        |          |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1
+     * |        |          |In Slave mode, this device is ready to receive data when this bit is set to 1.
+     * |        |          |0 = Transfer control Disabled.
+     * |        |          |1 = Transfer control Enabled.
+     * |        |          |Note: Before changing the configurations of QSPIx_CTL, QSPIx_CLKDIV, QSPIx_SSCTL and QSPIx_FIFOCTL registers, user shall clear the SPIEN (QSPIx_CTL[0]) and confirm the SPIENSTS (QSPIx_STATUS[15]) is 0.
+     * |[1]     |RXNEG     |Receive on Negative Edge
+     * |        |          |0 = Received data input signal is latched on the rising edge of QSPI bus clock.
+     * |        |          |1 = Received data input signal is latched on the falling edge of QSPI bus clock.
+     * |[2]     |TXNEG     |Transmit on Negative Edge
+     * |        |          |0 = Transmitted data output signal is changed on the rising edge of QSPI bus clock.
+     * |        |          |1 = Transmitted data output signal is changed on the falling edge of QSPI bus clock.
+     * |        |          |Note: In TX DTR mode, TXNEG equals to CLKPOL (QSPIx_CTL[3]).
+     * |[3]     |CLKPOL    |Clock Polarity
+     * |        |          |0 = QSPI bus clock is idle low.
+     * |        |          |1 = QSPI bus clock is idle high.
+     * |[7:4]   |SUSPITV   |Suspend Interval
+     * |        |          |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a Master transfer
+     * |        |          |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word
+     * |        |          |The default value is 0x3
+     * |        |          |The period of the suspend interval is obtained according to the following equation.
+     * |        |          |(SUSPITV[3:0] + 0.5) * period of QSPICLK clock cycle
+     * |        |          |Example:
+     * |        |          |SUSPITV = 0x0 .... 0.5 QSPICLK clock cycle.
+     * |        |          |SUSPITV = 0x1 .... 1.5 QSPICLK clock cycle.
+     * |        |          |.....
+     * |        |          |SUSPITV = 0xE .... 14.5 QSPICLK clock cycle.
+     * |        |          |SUSPITV = 0xF .... 15.5 QSPICLK clock cycle.
+     * |        |          |Note: In TX DTR mode, SUSPITV equals to 0x0.
+     * |[12:8]  |DWIDTH    |Data Width
+     * |        |          |This field specifies how many bits can be transmitted / received in one transaction
+     * |        |          |The minimum bit length is 8 bits and can up to 32 bits.
+     * |        |          |DWIDTH = 0x08 .... 8 bits.
+     * |        |          |DWIDTH = 0x09 .... 9 bits.
+     * |        |          |.....
+     * |        |          |DWIDTH = 0x1F .... 31 bits.
+     * |        |          |DWIDTH = 0x00 .... 32 bits.
+     * |        |          |Note: For QSPI0~QSPI3, this bit field will decide the depth of TX/RX FIFO configuration in QSPI mode
+     * |        |          |Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically in QSPI0~QSPI3.
+     * |[13]    |LSB       |Send LSB First
+     * |        |          |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first.
+     * |        |          |1 = The LSB, bit 0 of the QSPI TX register, is sent first to the QSPI data output pin, and the first bit received from the QSPI data input pin will be put in the LSB position of the RX register (bit 0 of QSPI_RX).
+     * |[14]    |HALFDPX   |QSPI Half-duplex Transfer Enable Bit
+     * |        |          |This bit is used to select full-duplex or half-duplex for QSPI transfer
+     * |        |          |The bit field DATDIR (QSPIx_CTL[20]) can be used to set the data direction in half-duplex transfer.
+     * |        |          |0 = QSPI operates in full-duplex transfer.
+     * |        |          |1 = QSPI operates in half-duplex transfer.
+     * |[15]    |RXONLY    |Receive-only Mode Enable Bit
+     * |        |          |This bit field is only available in Master mode
+     * |        |          |In receive-only mode, QSPI Master will generate QSPI bus clock continuously for receiving data bit from QSPI slave device and assert the BUSY status.
+     * |        |          |0 = Receive-only mode Disabled.
+     * |        |          |1 = Receive-only mode Enabled.
+     * |[16]    |TWOBIT    |2-bit Transfer Mode Enable Bit
+     * |        |          |0 = 2-Bit Transfer mode Disabled.
+     * |        |          |1 = 2-Bit Transfer mode Enabled.
+     * |        |          |Note: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data
+     * |        |          |As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
+     * |[17]    |UNITIEN   |Unit Transfer Interrupt Enable Bit
+     * |        |          |0 = QSPI unit transfer interrupt Disabled.
+     * |        |          |1 = QSPI unit transfer interrupt Enabled.
+     * |[18]    |SLAVE     |Slave Mode Control
+     * |        |          |0 = Master mode.
+     * |        |          |1 = Slave mode.
+     * |[19]    |REORDER   |Byte Reorder Function Enable Bit
+     * |        |          |0 = Byte Reorder function Disabled.
+     * |        |          |1 = Byte Reorder function Enabled
+     * |        |          |A byte suspend interval will be inserted among each byte
+     * |        |          |The period of the byte suspend interval depends on the setting of SUSPITV.
+     * |        |          |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
+     * |[20]    |DATDIR    |Data Port Direction Control
+     * |        |          |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer
+     * |        |          |0 = QSPI data is input direction.
+     * |        |          |1 = QSPI data is output direction.
+     * |[21]    |DUALIOEN  |Dual I/O Mode Enable Bit
+     * |        |          |0 = Dual I/O mode Disabled.
+     * |        |          |1 = Dual I/O mode Enabled.
+     * |[22]    |QUADIOEN  |Quad I/O Mode Enable Bit
+     * |        |          |0 = Quad I/O mode Disabled.
+     * |        |          |1 = Quad I/O mode Enabled.
+     * |[23]    |TXDTREN   |Transmit Double Transfer Rate Mode Enable Bit
+     * |        |          |0 = TX DTR mode Disabled.
+     * |        |          |1 = TX DTR mode Enabled.
+     * |        |          |Note: QSPI Master mode supports TXDTR (Transmit Double Transfer Rate) mode, and QSPI Slave mode does not support this mode.
+     * @var QSPI_T::CLKDIV
+     * Offset: 0x04  QSPI Clock Divider Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[8:0]   |DIVIDER   |Clock Divider
+     * |        |          |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the QSPI bus clock of QSPI Master
+     * |        |          |The frequency is obtained according to the following equation.
+     * |        |          |where
+     * |        |          |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.
+     * |        |          |Note: The time interval must be larger than or equal 5 peripheral clock cycles between releasing QSPI IP software reset and setting this clock divider register.
+     * @var QSPI_T::SSCTL
+     * Offset: 0x08  QSPI Slave Select Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SS        |Slave Selection Control
+     * |        |          |If AUTOSS bit is cleared to 0,
+     * |        |          |0 = Set the QSPIx_SS line to inactive state.
+     * |        |          |1 = Set the QSPIx_SS line to active state.
+     * |        |          |If the AUTOSS bit is set to 1,
+     * |        |          |0 = Keep the QSPIx_SS line at inactive state.
+     * |        |          |1 = QSPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time
+     * |        |          |The active state of QSPIx_SS is specified in SSACTPOL (QSPIx_SSCTL[2]).
+     * |        |          |Note: Master mode only.
+     * |[2]     |SSACTPOL  |Slave Selection Active Polarity
+     * |        |          |This bit defines the active polarity of slave selection signal (QSPIx_SS).
+     * |        |          |0 = The slave selection signal QSPIx_SS is active low.
+     * |        |          |1 = The slave selection signal QSPIx_SS is active high.
+     * |[3]     |AUTOSS    |Automatic Slave Selection Function Enable Bit
+     * |        |          |0 = Automatic slave selection function Disabled
+     * |        |          |Slave selection signal will be asserted/de-asserted according to SS (QSPIx_SSCTL[0]).
+     * |        |          |1 = Automatic slave selection function Enabled.
+     * |        |          |Note: Master mode only.
+     * |[4]     |SLV3WIRE  |Slave 3-wire Mode Enable Bit
+     * |        |          |In Slave 3-wire mode, the QSPI controller can work with 3-wire interface including QSPI0_CLK, QSPI0_MISO and QSPI0_MOSI pins.
+     * |        |          |0 = 4-wire bi-direction interface.
+     * |        |          |1 = 3-wire bi-direction interface.
+     * |[5]     |SLVTOIEN  |Slave Mode Time-out Interrupt Enable Bit
+     * |        |          |0 = Slave mode time-out interrupt Disabled.
+     * |        |          |1 = Slave mode time-out interrupt Enabled.
+     * |[6]     |SLVTORST  |Slave Mode Time-out Reset Control
+     * |        |          |0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset.
+     * |        |          |1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware.
+     * |[8]     |SLVBEIEN  |Slave Mode Bit Count Error Interrupt Enable Bit
+     * |        |          |0 = Slave mode bit count error interrupt Disabled.
+     * |        |          |1 = Slave mode bit count error interrupt Enabled.
+     * |[9]     |SLVURIEN  |Slave Mode TX Under Run Interrupt Enable Bit
+     * |        |          |0 = Slave mode TX under run interrupt Disabled.
+     * |        |          |1 = Slave mode TX under run interrupt Enabled.
+     * |[12]    |SSACTIEN  |Slave Select Active Interrupt Enable Bit
+     * |        |          |0 = Slave select active interrupt Disabled.
+     * |        |          |1 = Slave select active interrupt Enabled.
+     * |[13]    |SSINAIEN  |Slave Select Inactive Interrupt Enable Bit
+     * |        |          |0 = Slave select inactive interrupt Disabled.
+     * |        |          |1 = Slave select inactive interrupt Enabled.
+     * |[31:16] |SLVTOCNT  |Slave Mode Time-out Period
+     * |        |          |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active
+     * |        |          |The clock source of the time-out counter is Slave peripheral clock
+     * |        |          |If the value is 0, it indicates the slave mode time-out function is disabled.
+     * @var QSPI_T::PDMACTL
+     * Offset: 0x0C  QSPI PDMA Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |TXPDMAEN  |Transmit PDMA Enable Bit
+     * |        |          |0 = Transmit PDMA function Disabled.
+     * |        |          |1 = Transmit PDMA function Enabled.
+     * |        |          |Note: In QSPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function
+     * |        |          |User can enable TX PDMA function firstly or enable both functions simultaneously.
+     * |[1]     |RXPDMAEN  |Receive PDMA Enable Bit
+     * |        |          |0 = Receive PDMA function Disabled.
+     * |        |          |1 = Receive PDMA function Enabled.
+     * |[2]     |PDMARST   |PDMA Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset the PDMA control logic of the QSPI controller. This bit will be automatically cleared to 0.
+     * @var QSPI_T::FIFOCTL
+     * Offset: 0x10  QSPI FIFO Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RXRST     |Receive Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset receive FIFO pointer and receive circuit
+     * |        |          |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
+     * |        |          |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
+     * |        |          |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not.
+     * |[1]     |TXRST     |Transmit Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset transmit FIFO pointer and transmit circuit
+     * |        |          |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
+     * |        |          |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
+     * |        |          |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not.
+     * |        |          |Note: If TX underflow event occurs in QSPI Slave mode, this bit can be used to make QSPI return to idle state.
+     * |[2]     |RXTHIEN   |Receive FIFO Threshold Interrupt Enable Bit
+     * |        |          |0 = RX FIFO threshold interrupt Disabled.
+     * |        |          |1 = RX FIFO threshold interrupt Enabled.
+     * |[3]     |TXTHIEN   |Transmit FIFO Threshold Interrupt Enable Bit
+     * |        |          |0 = TX FIFO threshold interrupt Disabled.
+     * |        |          |1 = TX FIFO threshold interrupt Enabled.
+     * |[4]     |RXTOIEN   |Receive Time-out Interrupt Enable Bit
+     * |        |          |0 = Receive time-out interrupt Disabled.
+     * |        |          |1 = Receive time-out interrupt Enabled.
+     * |[5]     |RXOVIEN   |Receive FIFO Overrun Interrupt Enable Bit
+     * |        |          |0 = Receive FIFO overrun interrupt Disabled.
+     * |        |          |1 = Receive FIFO overrun interrupt Enabled.
+     * |[6]     |TXUFPOL   |TX Underflow Data Polarity
+     * |        |          |0 = The QSPI data out is kept 0 if there is TX underflow event in Slave mode.
+     * |        |          |1 = The QSPI data out is kept 1 if there is TX underflow event in Slave mode.
+     * |        |          |Note:
+     * |        |          |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.
+     * |        |          |2. When TX underflow event occurs, QSPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward
+     * |        |          |Data stored in TX FIFO will be sent through QSPIx_MISO pin in the next transfer frame.
+     * |[7]     |TXUFIEN   |TX Underflow Interrupt Enable Bit
+     * |        |          |When TX underflow event occurs in Slave mode, TXUFIF (QSPIx_STATUS[19]) will be set to 1
+     * |        |          |This bit is used to enable the TX underflow interrupt.
+     * |        |          |0 = Slave TX underflow interrupt Disabled.
+     * |        |          |1 = Slave TX underflow interrupt Enabled.
+     * |[8]     |RXFBCLR   |Receive FIFO Buffer Clear
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear receive FIFO pointer
+     * |        |          |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
+     * |        |          |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
+     * |        |          |Note: The RX shift register will not be cleared.
+     * |[9]     |TXFBCLR   |Transmit FIFO Buffer Clear
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear transmit FIFO pointer
+     * |        |          |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
+     * |        |          |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
+     * |        |          |Note: The TX shift register will not be cleared.
+     * |[10]    |SLVBERX   |RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error
+     * |        |          |0 = Uncompleted RX data will be dropped from RX FIFO when bit count error event happened in QSPI Slave mode.
+     * |        |          |1 = Uncompleted RX data will be written into RX FIFO when bit count error event happened in QSPI Slave mode
+     * |        |          |User can read SLVBENUM (QSPIx_STATUS2[29:24]) to know that the effective bit number of uncompleted RX data when SPI slave bit count error happened.
+     * |        |          |Note: Slave mode only.
+     * |[26:24] |RXTH      |Receive FIFO Threshold
+     * |        |          |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0
+     * |        |          |For QSPI0~QSPI3, the MSB of this bit field is only meaningful while QSPI mode 8~16 bits of data length.
+     * |[30:28] |TXTH      |Transmit FIFO Threshold
+     * |        |          |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0
+     * |        |          |For QSPI0~QSPI3, the MSB of this bit field is only meaningful while QSPI mode 8~16 bits of data length.
+     * @var QSPI_T::STATUS
+     * Offset: 0x14  QSPI Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BUSY      |Busy Status (Read Only)
+     * |        |          |0 = QSPI controller is in idle state.
+     * |        |          |1 = QSPI controller is in busy state.
+     * |        |          |The following listing are the bus busy conditions:
+     * |        |          |a. QSPIx_CTL[0] = 1 and TXEMPTY = 0.
+     * |        |          |b
+     * |        |          |For QSPI Master mode, QSPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet.
+     * |        |          |c. For QSPI Master mode, QSPIx_CTL[0] = 1 and RXONLY = 1.
+     * |        |          |d.
+     * |        |          |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and there is serial clock input into the QSPI core logic when slave select is active.
+     * |        |          |e.
+     * |        |          |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
+     * |        |          |Note: By applications, this QSPI busy flag should be used with other status registers in QSPIx_STATUS such as TXCNT, RXCNT, TXTHIF, TXFULL, TXEMPTY, RXTHIF, RXFULL, RXEMPTY, and UNITIF
+     * |        |          |Therefore the QSPI transfer done events of TX/RX operations can be obtained at correct timing point.
+     * |[1]     |UNITIF    |Unit Transfer Interrupt Flag
+     * |        |          |0 = No transaction has been finished since this bit was cleared to 0.
+     * |        |          |1 = QSPI controller has finished one unit transfer.
+     * |        |          |Note: This bit will be cleared by writing 1 to it.
+     * |[2]     |SSACTIF   |Slave Select Active Interrupt Flag
+     * |        |          |0 = Slave select active interrupt was cleared or not occurred.
+     * |        |          |1 = Slave select active interrupt event occurred.
+     * |        |          |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
+     * |[3]     |SSINAIF   |Slave Select Inactive Interrupt Flag
+     * |        |          |0 = Slave select inactive interrupt was cleared or not occurred.
+     * |        |          |1 = Slave select inactive interrupt event occurred.
+     * |        |          |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
+     * |[4]     |SSLINE    |Slave Select Line Bus Status (Read Only)
+     * |        |          |0 = The slave select line status is 0.
+     * |        |          |1 = The slave select line status is 1.
+     * |        |          |Note: This bit is only available in Slave mode
+     * |        |          |If SSACTPOL (QSPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the QSPI slave select is in inactive status.
+     * |[5]     |SLVTOIF   |Slave Time-out Interrupt Flag
+     * |        |          |When the slave select is active and the value of SLVTOCNT is not 0, if the bus clock is detected, the slave time-out counter in QSPI controller logic will be started
+     * |        |          |When the value of time-out counter is greater than or equal to the value of SLVTOCNT (QSPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.
+     * |        |          |0 = Slave time-out is not active.
+     * |        |          |1 = Slave time-out is active.
+     * |        |          |Note: This bit will be cleared by writing 1 to it.
+     * |[6]     |SLVBEIF   |Slave Mode Bit Count Error Interrupt Flag
+     * |        |          |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.
+     * |        |          |0 = No Slave mode bit count error event.
+     * |        |          |1 = Slave mode bit count error event occurs.
+     * |        |          |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state
+     * |        |          |This bit will be cleared by writing 1 to it.
+     * |[7]     |SLVURIF   |Slave Mode TX Under Run Interrupt Flag
+     * |        |          |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
+     * |        |          |0 = No Slave TX under run event.
+     * |        |          |1 = Slave TX under run event occurs.
+     * |        |          |Note: This bit will be cleared by writing 1 to it.
+     * |[8]     |RXEMPTY   |Receive FIFO Buffer Empty Indicator (Read Only)
+     * |        |          |0 = Receive FIFO buffer is not empty.
+     * |        |          |1 = Receive FIFO buffer is empty.
+     * |[9]     |RXFULL    |Receive FIFO Buffer Full Indicator (Read Only)
+     * |        |          |0 = Receive FIFO buffer is not full.
+     * |        |          |1 = Receive FIFO buffer is full.
+     * |[10]    |RXTHIF    |Receive FIFO Threshold Interrupt Flag (Read Only)
+     * |        |          |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH.
+     * |        |          |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
+     * |[11]    |RXOVIF    |Receive FIFO Overrun Interrupt Flag
+     * |        |          |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
+     * |        |          |0 = No FIFO is overrun.
+     * |        |          |1 = Receive FIFO is overrun.
+     * |        |          |Note: This bit will be cleared by writing 1 to it.
+     * |[12]    |RXTOIF    |Receive Time-out Interrupt Flag
+     * |        |          |0 = No receive FIFO time-out event.
+     * |        |          |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 QSPI peripheral clock periods in Master mode or over 576 QSPI peripheral clock periods in Slave mode
+     * |        |          |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
+     * |        |          |Note: This bit will be cleared by writing 1 to it.
+     * |[15]    |SPIENSTS  |QSPI Enable Status (Read Only)
+     * |        |          |0 = The QSPI controller is disabled.
+     * |        |          |1 = The QSPI controller is enabled.
+     * |        |          |Note: The QSPI peripheral clock is asynchronous with the system clock
+     * |        |          |In order to make sure the QSPI control logic is disabled, this bit indicates the real status of QSPI controller.
+     * |[16]    |TXEMPTY   |Transmit FIFO Buffer Empty Indicator (Read Only)
+     * |        |          |0 = Transmit FIFO buffer is not empty.
+     * |        |          |1 = Transmit FIFO buffer is empty.
+     * |[17]    |TXFULL    |Transmit FIFO Buffer Full Indicator (Read Only)
+     * |        |          |0 = Transmit FIFO buffer is not full.
+     * |        |          |1 = Transmit FIFO buffer is full.
+     * |[18]    |TXTHIF    |Transmit FIFO Threshold Interrupt Flag (Read Only)
+     * |        |          |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
+     * |        |          |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
+     * |[19]    |TXUFIF    |TX Underflow Interrupt Flag
+     * |        |          |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
+     * |        |          |0 = No effect.
+     * |        |          |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active.
+     * |        |          |Note 1: This bit will be cleared by writing 1 to it.
+     * |        |          |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
+     * |[23]    |TXRXRST   |TX or RX Reset Status (Read Only)
+     * |        |          |0 = The reset function of TXRST or RXRST is done.
+     * |        |          |1 = Doing the reset function of TXRST or RXRST.
+     * |        |          |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles
+     * |        |          |User can check the status of this bit to monitor the reset function is doing or done.
+     * |[27:24] |RXCNT     |Receive FIFO Data Count (Read Only)
+     * |        |          |This bit field indicates the valid data count of receive FIFO buffer.
+     * |[31:28] |TXCNT     |Transmit FIFO Data Count (Read Only)
+     * |        |          |This bit field indicates the valid data count of transmit FIFO buffer.
+     * @var QSPI_T::STATUS2
+     * Offset: 0x18  QSPI Status2 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[29:24] |SLVBENUM  |Effective Bit Number of Uncompleted RX Data
+     * |        |          |This status register indicates that effective bit number of uncompleted RX data when SLVBERX (QSPIx_FIFOCTL[10]) is enabled and RX bit count error event happen in QSPI Slave mode
+     * |        |          |This status register will be fixed to 0x0 when SLVBERX (QSPIx_FIFOCTL[10]) is disabled.
+     * |        |          |Note 1: This register will be cleared to 0x0 when user writes 0x1 to SLVBEIF (QSPIx_STATUS[6]).
+     * |        |          |Note 2: Slave mode only.
+     * @var QSPI_T::TX
+     * Offset: 0x20  QSPI Data Transmit Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |TX        |Data Transmit Register
+     * |        |          |The data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffers
+     * |        |          |The number of valid bits depends on the setting of DWIDTH (QSPIx_CTL[12:8]) in QSPI mode.
+     * |        |          |In QSPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted.
+     * |        |          |If DWIDTH is set to 0x00 , the QSPI controller will perform a 32-bit transfer.
+     * |        |          |Note: In Master mode, QSPI controller will start to transfer the QSPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.
+     * @var QSPI_T::RX
+     * Offset: 0x30  QSPI Data Receive Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |RX        |Data Receive Register (Read Only)
+     * |        |          |There are 8-level FIFO buffers in this controller.
+     * |        |          |The data receive register holds the data received from QSPI data input pin.
+     * |        |          |If the RXEMPTY (QSPIx_STATUS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register.
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] QSPI Control Register                                             */
+    __IO uint32_t CLKDIV;                /*!< [0x0004] QSPI Clock Divider Register                                       */
+    __IO uint32_t SSCTL;                 /*!< [0x0008] QSPI Slave Select Control Register                                */
+    __IO uint32_t PDMACTL;               /*!< [0x000c] QSPI PDMA Control Register                                        */
+    __IO uint32_t FIFOCTL;               /*!< [0x0010] QSPI FIFO Control Register                                        */
+    __IO uint32_t STATUS;                /*!< [0x0014] QSPI Status Register                                              */
+    __I  uint32_t STATUS2;               /*!< [0x0018] QSPI Status2 Register                                             */
+    __I  uint32_t RESERVE0[1];
+    __O  uint32_t TX;                    /*!< [0x0020] QSPI Data Transmit Register                                       */
+    __I  uint32_t RESERVE1[3];
+    __I  uint32_t RX;                    /*!< [0x0030] QSPI Data Receive Register                                        */
+
+} QSPI_T;
+
+/**
+    @addtogroup QSPI_CONST QSPI Bit Field Definition
+    Constant Definitions for QSPI Controller
+  @{
+*/
+
+#define QSPI_CTL_SPIEN_Pos                (0)                                               /*!< QSPI_T::CTL: SPIEN Position             */
+#define QSPI_CTL_SPIEN_Msk                (0x1ul << QSPI_CTL_SPIEN_Pos)                     /*!< QSPI_T::CTL: SPIEN Mask                 */
+
+#define QSPI_CTL_RXNEG_Pos                (1)                                               /*!< QSPI_T::CTL: RXNEG Position             */
+#define QSPI_CTL_RXNEG_Msk                (0x1ul << QSPI_CTL_RXNEG_Pos)                     /*!< QSPI_T::CTL: RXNEG Mask                 */
+
+#define QSPI_CTL_TXNEG_Pos                (2)                                               /*!< QSPI_T::CTL: TXNEG Position             */
+#define QSPI_CTL_TXNEG_Msk                (0x1ul << QSPI_CTL_TXNEG_Pos)                     /*!< QSPI_T::CTL: TXNEG Mask                 */
+
+#define QSPI_CTL_CLKPOL_Pos               (3)                                               /*!< QSPI_T::CTL: CLKPOL Position            */
+#define QSPI_CTL_CLKPOL_Msk               (0x1ul << QSPI_CTL_CLKPOL_Pos)                    /*!< QSPI_T::CTL: CLKPOL Mask                */
+
+#define QSPI_CTL_SUSPITV_Pos              (4)                                               /*!< QSPI_T::CTL: SUSPITV Position           */
+#define QSPI_CTL_SUSPITV_Msk              (0xful << QSPI_CTL_SUSPITV_Pos)                   /*!< QSPI_T::CTL: SUSPITV Mask               */
+
+#define QSPI_CTL_DWIDTH_Pos               (8)                                               /*!< QSPI_T::CTL: DWIDTH Position            */
+#define QSPI_CTL_DWIDTH_Msk               (0x1ful << QSPI_CTL_DWIDTH_Pos)                   /*!< QSPI_T::CTL: DWIDTH Mask                */
+
+#define QSPI_CTL_LSB_Pos                  (13)                                              /*!< QSPI_T::CTL: LSB Position               */
+#define QSPI_CTL_LSB_Msk                  (0x1ul << QSPI_CTL_LSB_Pos)                       /*!< QSPI_T::CTL: LSB Mask                   */
+
+#define QSPI_CTL_HALFDPX_Pos              (14)                                              /*!< QSPI_T::CTL: HALFDPX Position           */
+#define QSPI_CTL_HALFDPX_Msk              (0x1ul << QSPI_CTL_HALFDPX_Pos)                   /*!< QSPI_T::CTL: HALFDPX Mask               */
+
+#define QSPI_CTL_RXONLY_Pos               (15)                                              /*!< QSPI_T::CTL: RXONLY Position            */
+#define QSPI_CTL_RXONLY_Msk               (0x1ul << QSPI_CTL_RXONLY_Pos)                    /*!< QSPI_T::CTL: RXONLY Mask                */
+
+#define QSPI_CTL_TWOBIT_Pos               (16)                                              /*!< QSPI_T::CTL: TWOBIT Position            */
+#define QSPI_CTL_TWOBIT_Msk               (0x1ul << QSPI_CTL_TWOBIT_Pos)                    /*!< QSPI_T::CTL: TWOBIT Mask                */
+
+#define QSPI_CTL_UNITIEN_Pos              (17)                                              /*!< QSPI_T::CTL: UNITIEN Position           */
+#define QSPI_CTL_UNITIEN_Msk              (0x1ul << QSPI_CTL_UNITIEN_Pos)                   /*!< QSPI_T::CTL: UNITIEN Mask               */
+
+#define QSPI_CTL_SLAVE_Pos                (18)                                              /*!< QSPI_T::CTL: SLAVE Position             */
+#define QSPI_CTL_SLAVE_Msk                (0x1ul << QSPI_CTL_SLAVE_Pos)                     /*!< QSPI_T::CTL: SLAVE Mask                 */
+
+#define QSPI_CTL_REORDER_Pos              (19)                                              /*!< QSPI_T::CTL: REORDER Position           */
+#define QSPI_CTL_REORDER_Msk              (0x1ul << QSPI_CTL_REORDER_Pos)                   /*!< QSPI_T::CTL: REORDER Mask               */
+
+#define QSPI_CTL_DATDIR_Pos               (20)                                              /*!< QSPI_T::CTL: DATDIR Position            */
+#define QSPI_CTL_DATDIR_Msk               (0x1ul << QSPI_CTL_DATDIR_Pos)                    /*!< QSPI_T::CTL: DATDIR Mask                */
+
+#define QSPI_CTL_DUALIOEN_Pos             (21)                                              /*!< QSPI_T::CTL: DUALIOEN Position          */
+#define QSPI_CTL_DUALIOEN_Msk             (0x1ul << QSPI_CTL_DUALIOEN_Pos)                  /*!< QSPI_T::CTL: DUALIOEN Mask              */
+
+#define QSPI_CTL_QUADIOEN_Pos             (22)                                              /*!< QSPI_T::CTL: QUADIOEN Position          */
+#define QSPI_CTL_QUADIOEN_Msk             (0x1ul << QSPI_CTL_QUADIOEN_Pos)                  /*!< QSPI_T::CTL: QUADIOEN Mask              */
+
+#define QSPI_CTL_TXDTREN_Pos              (23)                                              /*!< QSPI_T::CTL: TXDTREN Position           */
+#define QSPI_CTL_TXDTREN_Msk              (0x1ul << QSPI_CTL_TXDTREN_Pos)                   /*!< QSPI_T::CTL: TXDTREN Mask               */
+
+#define QSPI_CLKDIV_DIVIDER_Pos           (0)                                               /*!< QSPI_T::CLKDIV: DIVIDER Position        */
+#define QSPI_CLKDIV_DIVIDER_Msk           (0x1fful << QSPI_CLKDIV_DIVIDER_Pos)              /*!< QSPI_T::CLKDIV: DIVIDER Mask            */
+
+#define QSPI_SSCTL_SS_Pos                 (0)                                               /*!< QSPI_T::SSCTL: SS Position              */
+#define QSPI_SSCTL_SS_Msk                 (0x1ul << QSPI_SSCTL_SS_Pos)                      /*!< QSPI_T::SSCTL: SS Mask                  */
+
+#define QSPI_SSCTL_SSACTPOL_Pos           (2)                                               /*!< QSPI_T::SSCTL: SSACTPOL Position        */
+#define QSPI_SSCTL_SSACTPOL_Msk           (0x1ul << QSPI_SSCTL_SSACTPOL_Pos)                /*!< QSPI_T::SSCTL: SSACTPOL Mask            */
+
+#define QSPI_SSCTL_AUTOSS_Pos             (3)                                               /*!< QSPI_T::SSCTL: AUTOSS Position          */
+#define QSPI_SSCTL_AUTOSS_Msk             (0x1ul << QSPI_SSCTL_AUTOSS_Pos)                  /*!< QSPI_T::SSCTL: AUTOSS Mask              */
+
+#define QSPI_SSCTL_SLV3WIRE_Pos           (4)                                               /*!< QSPI_T::SSCTL: SLV3WIRE Position        */
+#define QSPI_SSCTL_SLV3WIRE_Msk           (0x1ul << QSPI_SSCTL_SLV3WIRE_Pos)                /*!< QSPI_T::SSCTL: SLV3WIRE Mask            */
+
+#define QSPI_SSCTL_SLVTOIEN_Pos           (5)                                               /*!< QSPI_T::SSCTL: SLVTOIEN Position        */
+#define QSPI_SSCTL_SLVTOIEN_Msk           (0x1ul << QSPI_SSCTL_SLVTOIEN_Pos)                /*!< QSPI_T::SSCTL: SLVTOIEN Mask            */
+
+#define QSPI_SSCTL_SLVTORST_Pos           (6)                                               /*!< QSPI_T::SSCTL: SLVTORST Position        */
+#define QSPI_SSCTL_SLVTORST_Msk           (0x1ul << QSPI_SSCTL_SLVTORST_Pos)                /*!< QSPI_T::SSCTL: SLVTORST Mask            */
+
+#define QSPI_SSCTL_SLVBEIEN_Pos           (8)                                               /*!< QSPI_T::SSCTL: SLVBEIEN Position        */
+#define QSPI_SSCTL_SLVBEIEN_Msk           (0x1ul << QSPI_SSCTL_SLVBEIEN_Pos)                /*!< QSPI_T::SSCTL: SLVBEIEN Mask            */
+
+#define QSPI_SSCTL_SLVURIEN_Pos           (9)                                               /*!< QSPI_T::SSCTL: SLVURIEN Position        */
+#define QSPI_SSCTL_SLVURIEN_Msk           (0x1ul << QSPI_SSCTL_SLVURIEN_Pos)                /*!< QSPI_T::SSCTL: SLVURIEN Mask            */
+
+#define QSPI_SSCTL_SSACTIEN_Pos           (12)                                              /*!< QSPI_T::SSCTL: SSACTIEN Position        */
+#define QSPI_SSCTL_SSACTIEN_Msk           (0x1ul << QSPI_SSCTL_SSACTIEN_Pos)                /*!< QSPI_T::SSCTL: SSACTIEN Mask            */
+
+#define QSPI_SSCTL_SSINAIEN_Pos           (13)                                              /*!< QSPI_T::SSCTL: SSINAIEN Position        */
+#define QSPI_SSCTL_SSINAIEN_Msk           (0x1ul << QSPI_SSCTL_SSINAIEN_Pos)                /*!< QSPI_T::SSCTL: SSINAIEN Mask            */
+
+#define QSPI_SSCTL_SLVTOCNT_Pos           (16)                                              /*!< QSPI_T::SSCTL: SLVTOCNT Position        */
+#define QSPI_SSCTL_SLVTOCNT_Msk           (0xfffful << QSPI_SSCTL_SLVTOCNT_Pos)             /*!< QSPI_T::SSCTL: SLVTOCNT Mask            */
+
+#define QSPI_PDMACTL_TXPDMAEN_Pos         (0)                                               /*!< QSPI_T::PDMACTL: TXPDMAEN Position      */
+#define QSPI_PDMACTL_TXPDMAEN_Msk         (0x1ul << QSPI_PDMACTL_TXPDMAEN_Pos)              /*!< QSPI_T::PDMACTL: TXPDMAEN Mask          */
+
+#define QSPI_PDMACTL_RXPDMAEN_Pos         (1)                                               /*!< QSPI_T::PDMACTL: RXPDMAEN Position      */
+#define QSPI_PDMACTL_RXPDMAEN_Msk         (0x1ul << QSPI_PDMACTL_RXPDMAEN_Pos)              /*!< QSPI_T::PDMACTL: RXPDMAEN Mask          */
+
+#define QSPI_PDMACTL_PDMARST_Pos          (2)                                               /*!< QSPI_T::PDMACTL: PDMARST Position       */
+#define QSPI_PDMACTL_PDMARST_Msk          (0x1ul << QSPI_PDMACTL_PDMARST_Pos)               /*!< QSPI_T::PDMACTL: PDMARST Mask           */
+
+#define QSPI_FIFOCTL_RXRST_Pos            (0)                                               /*!< QSPI_T::FIFOCTL: RXRST Position         */
+#define QSPI_FIFOCTL_RXRST_Msk            (0x1ul << QSPI_FIFOCTL_RXRST_Pos)                 /*!< QSPI_T::FIFOCTL: RXRST Mask             */
+
+#define QSPI_FIFOCTL_TXRST_Pos            (1)                                               /*!< QSPI_T::FIFOCTL: TXRST Position         */
+#define QSPI_FIFOCTL_TXRST_Msk            (0x1ul << QSPI_FIFOCTL_TXRST_Pos)                 /*!< QSPI_T::FIFOCTL: TXRST Mask             */
+
+#define QSPI_FIFOCTL_RXTHIEN_Pos          (2)                                               /*!< QSPI_T::FIFOCTL: RXTHIEN Position       */
+#define QSPI_FIFOCTL_RXTHIEN_Msk          (0x1ul << QSPI_FIFOCTL_RXTHIEN_Pos)               /*!< QSPI_T::FIFOCTL: RXTHIEN Mask           */
+
+#define QSPI_FIFOCTL_TXTHIEN_Pos          (3)                                               /*!< QSPI_T::FIFOCTL: TXTHIEN Position       */
+#define QSPI_FIFOCTL_TXTHIEN_Msk          (0x1ul << QSPI_FIFOCTL_TXTHIEN_Pos)               /*!< QSPI_T::FIFOCTL: TXTHIEN Mask           */
+
+#define QSPI_FIFOCTL_RXTOIEN_Pos          (4)                                               /*!< QSPI_T::FIFOCTL: RXTOIEN Position       */
+#define QSPI_FIFOCTL_RXTOIEN_Msk          (0x1ul << QSPI_FIFOCTL_RXTOIEN_Pos)               /*!< QSPI_T::FIFOCTL: RXTOIEN Mask           */
+
+#define QSPI_FIFOCTL_RXOVIEN_Pos          (5)                                               /*!< QSPI_T::FIFOCTL: RXOVIEN Position       */
+#define QSPI_FIFOCTL_RXOVIEN_Msk          (0x1ul << QSPI_FIFOCTL_RXOVIEN_Pos)               /*!< QSPI_T::FIFOCTL: RXOVIEN Mask           */
+
+#define QSPI_FIFOCTL_TXUFPOL_Pos          (6)                                               /*!< QSPI_T::FIFOCTL: TXUFPOL Position       */
+#define QSPI_FIFOCTL_TXUFPOL_Msk          (0x1ul << QSPI_FIFOCTL_TXUFPOL_Pos)               /*!< QSPI_T::FIFOCTL: TXUFPOL Mask           */
+
+#define QSPI_FIFOCTL_TXUFIEN_Pos          (7)                                               /*!< QSPI_T::FIFOCTL: TXUFIEN Position       */
+#define QSPI_FIFOCTL_TXUFIEN_Msk          (0x1ul << QSPI_FIFOCTL_TXUFIEN_Pos)               /*!< QSPI_T::FIFOCTL: TXUFIEN Mask           */
+
+#define QSPI_FIFOCTL_RXFBCLR_Pos          (8)                                               /*!< QSPI_T::FIFOCTL: RXFBCLR Position       */
+#define QSPI_FIFOCTL_RXFBCLR_Msk          (0x1ul << QSPI_FIFOCTL_RXFBCLR_Pos)               /*!< QSPI_T::FIFOCTL: RXFBCLR Mask           */
+
+#define QSPI_FIFOCTL_TXFBCLR_Pos          (9)                                               /*!< QSPI_T::FIFOCTL: TXFBCLR Position       */
+#define QSPI_FIFOCTL_TXFBCLR_Msk          (0x1ul << QSPI_FIFOCTL_TXFBCLR_Pos)               /*!< QSPI_T::FIFOCTL: TXFBCLR Mask           */
+
+#define QSPI_FIFOCTL_SLVBERX_Pos          (10)                                              /*!< QSPI_T::FIFOCTL: SLVBERX Position       */
+#define QSPI_FIFOCTL_SLVBERX_Msk          (0x1ul << QSPI_FIFOCTL_SLVBERX_Pos)               /*!< QSPI_T::FIFOCTL: SLVBERX Mask           */
+
+#define QSPI_FIFOCTL_RXTH_Pos             (24)                                              /*!< QSPI_T::FIFOCTL: RXTH Position          */
+#define QSPI_FIFOCTL_RXTH_Msk             (0x7ul << QSPI_FIFOCTL_RXTH_Pos)                  /*!< QSPI_T::FIFOCTL: RXTH Mask              */
+
+#define QSPI_FIFOCTL_TXTH_Pos             (28)                                              /*!< QSPI_T::FIFOCTL: TXTH Position          */
+#define QSPI_FIFOCTL_TXTH_Msk             (0x7ul << QSPI_FIFOCTL_TXTH_Pos)                  /*!< QSPI_T::FIFOCTL: TXTH Mask              */
+
+#define QSPI_STATUS_BUSY_Pos              (0)                                               /*!< QSPI_T::STATUS: BUSY Position           */
+#define QSPI_STATUS_BUSY_Msk              (0x1ul << QSPI_STATUS_BUSY_Pos)                   /*!< QSPI_T::STATUS: BUSY Mask               */
+
+#define QSPI_STATUS_UNITIF_Pos            (1)                                               /*!< QSPI_T::STATUS: UNITIF Position         */
+#define QSPI_STATUS_UNITIF_Msk            (0x1ul << QSPI_STATUS_UNITIF_Pos)                 /*!< QSPI_T::STATUS: UNITIF Mask             */
+
+#define QSPI_STATUS_SSACTIF_Pos           (2)                                               /*!< QSPI_T::STATUS: SSACTIF Position        */
+#define QSPI_STATUS_SSACTIF_Msk           (0x1ul << QSPI_STATUS_SSACTIF_Pos)                /*!< QSPI_T::STATUS: SSACTIF Mask            */
+
+#define QSPI_STATUS_SSINAIF_Pos           (3)                                               /*!< QSPI_T::STATUS: SSINAIF Position        */
+#define QSPI_STATUS_SSINAIF_Msk           (0x1ul << QSPI_STATUS_SSINAIF_Pos)                /*!< QSPI_T::STATUS: SSINAIF Mask            */
+
+#define QSPI_STATUS_SSLINE_Pos            (4)                                               /*!< QSPI_T::STATUS: SSLINE Position         */
+#define QSPI_STATUS_SSLINE_Msk            (0x1ul << QSPI_STATUS_SSLINE_Pos)                 /*!< QSPI_T::STATUS: SSLINE Mask             */
+
+#define QSPI_STATUS_SLVTOIF_Pos           (5)                                               /*!< QSPI_T::STATUS: SLVTOIF Position        */
+#define QSPI_STATUS_SLVTOIF_Msk           (0x1ul << QSPI_STATUS_SLVTOIF_Pos)                /*!< QSPI_T::STATUS: SLVTOIF Mask            */
+
+#define QSPI_STATUS_SLVBEIF_Pos           (6)                                               /*!< QSPI_T::STATUS: SLVBEIF Position        */
+#define QSPI_STATUS_SLVBEIF_Msk           (0x1ul << QSPI_STATUS_SLVBEIF_Pos)                /*!< QSPI_T::STATUS: SLVBEIF Mask            */
+
+#define QSPI_STATUS_SLVURIF_Pos           (7)                                               /*!< QSPI_T::STATUS: SLVURIF Position        */
+#define QSPI_STATUS_SLVURIF_Msk           (0x1ul << QSPI_STATUS_SLVURIF_Pos)                /*!< QSPI_T::STATUS: SLVURIF Mask            */
+
+#define QSPI_STATUS_RXEMPTY_Pos           (8)                                               /*!< QSPI_T::STATUS: RXEMPTY Position        */
+#define QSPI_STATUS_RXEMPTY_Msk           (0x1ul << QSPI_STATUS_RXEMPTY_Pos)                /*!< QSPI_T::STATUS: RXEMPTY Mask            */
+
+#define QSPI_STATUS_RXFULL_Pos            (9)                                               /*!< QSPI_T::STATUS: RXFULL Position         */
+#define QSPI_STATUS_RXFULL_Msk            (0x1ul << QSPI_STATUS_RXFULL_Pos)                 /*!< QSPI_T::STATUS: RXFULL Mask             */
+
+#define QSPI_STATUS_RXTHIF_Pos            (10)                                              /*!< QSPI_T::STATUS: RXTHIF Position         */
+#define QSPI_STATUS_RXTHIF_Msk            (0x1ul << QSPI_STATUS_RXTHIF_Pos)                 /*!< QSPI_T::STATUS: RXTHIF Mask             */
+
+#define QSPI_STATUS_RXOVIF_Pos            (11)                                              /*!< QSPI_T::STATUS: RXOVIF Position         */
+#define QSPI_STATUS_RXOVIF_Msk            (0x1ul << QSPI_STATUS_RXOVIF_Pos)                 /*!< QSPI_T::STATUS: RXOVIF Mask             */
+
+#define QSPI_STATUS_RXTOIF_Pos            (12)                                              /*!< QSPI_T::STATUS: RXTOIF Position         */
+#define QSPI_STATUS_RXTOIF_Msk            (0x1ul << QSPI_STATUS_RXTOIF_Pos)                 /*!< QSPI_T::STATUS: RXTOIF Mask             */
+
+#define QSPI_STATUS_SPIENSTS_Pos          (15)                                              /*!< QSPI_T::STATUS: SPIENSTS Position       */
+#define QSPI_STATUS_SPIENSTS_Msk          (0x1ul << QSPI_STATUS_SPIENSTS_Pos)               /*!< QSPI_T::STATUS: SPIENSTS Mask           */
+
+#define QSPI_STATUS_TXEMPTY_Pos           (16)                                              /*!< QSPI_T::STATUS: TXEMPTY Position        */
+#define QSPI_STATUS_TXEMPTY_Msk           (0x1ul << QSPI_STATUS_TXEMPTY_Pos)                /*!< QSPI_T::STATUS: TXEMPTY Mask            */
+
+#define QSPI_STATUS_TXFULL_Pos            (17)                                              /*!< QSPI_T::STATUS: TXFULL Position         */
+#define QSPI_STATUS_TXFULL_Msk            (0x1ul << QSPI_STATUS_TXFULL_Pos)                 /*!< QSPI_T::STATUS: TXFULL Mask             */
+
+#define QSPI_STATUS_TXTHIF_Pos            (18)                                              /*!< QSPI_T::STATUS: TXTHIF Position         */
+#define QSPI_STATUS_TXTHIF_Msk            (0x1ul << QSPI_STATUS_TXTHIF_Pos)                 /*!< QSPI_T::STATUS: TXTHIF Mask             */
+
+#define QSPI_STATUS_TXUFIF_Pos            (19)                                              /*!< QSPI_T::STATUS: TXUFIF Position         */
+#define QSPI_STATUS_TXUFIF_Msk            (0x1ul << QSPI_STATUS_TXUFIF_Pos)                 /*!< QSPI_T::STATUS: TXUFIF Mask             */
+
+#define QSPI_STATUS_TXRXRST_Pos           (23)                                              /*!< QSPI_T::STATUS: TXRXRST Position        */
+#define QSPI_STATUS_TXRXRST_Msk           (0x1ul << QSPI_STATUS_TXRXRST_Pos)                /*!< QSPI_T::STATUS: TXRXRST Mask            */
+
+#define QSPI_STATUS_RXCNT_Pos             (24)                                              /*!< QSPI_T::STATUS: RXCNT Position          */
+#define QSPI_STATUS_RXCNT_Msk             (0xful << QSPI_STATUS_RXCNT_Pos)                  /*!< QSPI_T::STATUS: RXCNT Mask              */
+
+#define QSPI_STATUS_TXCNT_Pos             (28)                                              /*!< QSPI_T::STATUS: TXCNT Position          */
+#define QSPI_STATUS_TXCNT_Msk             (0xful << QSPI_STATUS_TXCNT_Pos)                  /*!< QSPI_T::STATUS: TXCNT Mask              */
+
+#define QSPI_STATUS2_SLVBENUM_Pos         (24)                                              /*!< QSPI_T::STATUS2: SLVBENUM Position      */
+#define QSPI_STATUS2_SLVBENUM_Msk         (0x3ful << QSPI_STATUS2_SLVBENUM_Pos)             /*!< QSPI_T::STATUS2: SLVBENUM Mask          */
+
+#define QSPI_TX_TX_Pos                    (0)                                               /*!< QSPI_T::TX: TX Position                 */
+#define QSPI_TX_TX_Msk                    (0xfffffffful << QSPI_TX_TX_Pos)                  /*!< QSPI_T::TX: TX Mask                     */
+
+#define QSPI_RX_RX_Pos                    (0)                                               /*!< QSPI_T::RX: RX Position                 */
+#define QSPI_RX_RX_Msk                    (0xfffffffful << QSPI_RX_RX_Pos)                  /*!< QSPI_T::RX: RX Mask                     */
+
+/**@}*/ /* QSPI_CONST */
+/**@}*/ /* end of QSPI register group */
+/**@}*/ /* end of REGISTER group */
+
+#endif /* __QSPI_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/rtc_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/rtc_reg.h
new file mode 100644
index 0000000000..5af6ce5a20
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/rtc_reg.h
@@ -0,0 +1,1302 @@
+/**************************************************************************//**
+ * @file     rtc_reg.h
+ * @version  V1.00
+ * @brief    RTC register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __RTC_REG_H__
+#define __RTC_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+/*---------------------- Real Time Clock Controller -------------------------*/
+/**
+    @addtogroup RTC Real Time Clock Controller(RTC)
+    Memory Mapped Structure for RTC Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var RTC_T::INIT
+     * Offset: 0x00  RTC Initiation Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |INIT_ACTIVE|RTC Active Status (Read Only)
+     * |        |          |0 = RTC is at reset state.
+     * |        |          |1 = RTC is at normal active state.
+     * |[31:1]  |INIT      |RTC Initiation (Write Only)
+     * |        |          |When RTC block is powered on, RTC is at reset state.
+     * |        |          |User has to write a number (0xa5eb1357) to INIT to make RTC leave reset state.
+     * |        |          |Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.
+     * |        |          |The INIT is a write-only field and read value will be always 0.
+     * @var RTC_T::FREQADJ
+     * Offset: 0x08  RTC Frequency Compensation Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[5:0]   |FRACTION  |Fraction Part
+     * |        |          |Formula: FRACTION = (fraction part of detected value) X 64.
+     * |        |          |Note: Digit in FCR must be expressed as hexadecimal number.
+     * |[12:8]  |INTEGER   |Integer Part
+     * |        |          |00000 = Integer part of detected value is 32752.
+     * |        |          |00001 = Integer part of detected value is 32753.
+     * |        |          |00010 = Integer part of detected value is 32754.
+     * |        |          |00011 = Integer part of detected value is 32755.
+     * |        |          |00100 = Integer part of detected value is 32756.
+     * |        |          |00101 = Integer part of detected value is 32757.
+     * |        |          |00110 = Integer part of detected value is 32758.
+     * |        |          |00111 = Integer part of detected value is 32759.
+     * |        |          |01000 = Integer part of detected value is 32760.
+     * |        |          |01001 = Integer part of detected value is 32761.
+     * |        |          |01010 = Integer part of detected value is 32762.
+     * |        |          |01011 = Integer part of detected value is 32763.
+     * |        |          |01100 = Integer part of detected value is 32764.
+     * |        |          |01101 = Integer part of detected value is 32765.
+     * |        |          |01110 = Integer part of detected value is 32766.
+     * |        |          |01111 = Integer part of detected value is 32767.
+     * |        |          |10000 = Integer part of detected value is 32768.
+     * |        |          |10001 = Integer part of detected value is 32769.
+     * |        |          |10010 = Integer part of detected value is 32770.
+     * |        |          |10011 = Integer part of detected value is 32771.
+     * |        |          |10100 = Integer part of detected value is 32772.
+     * |        |          |10101 = Integer part of detected value is 32773.
+     * |        |          |10110 = Integer part of detected value is 32774.
+     * |        |          |10111 = Integer part of detected value is 32775.
+     * |        |          |11000 = Integer part of detected value is 32776.
+     * |        |          |11001 = Integer part of detected value is 32777.
+     * |        |          |11010 = Integer part of detected value is 32778.
+     * |        |          |11011 = Integer part of detected value is 32779.
+     * |        |          |11100 = Integer part of detected value is 32780.
+     * |        |          |11101 = Integer part of detected value is 32781.
+     * |        |          |11110 = Integer part of detected value is 32782.
+     * |        |          |11111 = Integer part of detected value is 32783.
+     * |[31]    |FCRBUSY   |Frequency Compensation Register Write Operation Busy (Read Only)
+     * |        |          |0 = The new register write operation is acceptable.
+     * |        |          |1 = The last write operation is in progress and new register write operation prohibited.
+     * |        |          |Note: This bit is only used when DCOMPEN(RTC_CLKFMT[16]) is enabled.
+     * @var RTC_T::TIME
+     * Offset: 0x0C  RTC Time Loading Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |SEC       |1-Sec Time Digit (0~9)
+     * |[6:4]   |TENSEC    |10-Sec Time Digit (0~5)
+     * |[11:8]  |MIN       |1-Min Time Digit (0~9)
+     * |[14:12] |TENMIN    |10-Min Time Digit (0~5)
+     * |[19:16] |HR        |1-Hour Time Digit (0~9)
+     * |[21:20] |TENHR     |10-Hour Time Digit (0~2)
+     * |        |          |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.)
+     * @var RTC_T::CAL
+     * Offset: 0x10  RTC Calendar Loading Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |DAY       |1-Day Calendar Digit (0~9)
+     * |[5:4]   |TENDAY    |10-Day Calendar Digit (0~3)
+     * |[11:8]  |MON       |1-Month Calendar Digit (0~9)
+     * |[12]    |TENMON    |10-Month Calendar Digit (0~1)
+     * |[19:16] |YEAR      |1-Year Calendar Digit (0~9)
+     * |[23:20] |TENYEAR   |10-Year Calendar Digit (0~9)
+     * @var RTC_T::CLKFMT
+     * Offset: 0x14  RTC Time Scale Selection Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |24HEN     |24-hour / 12-hour Time Scale Selection
+     * |        |          |The RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale.
+     * |        |          |0 = 12-hour time scale with AM and PM indication selected.
+     * |        |          |1 = 24-hour time scale selected.
+     * |[16]    |DCOMPEN   |Dynamic Compensation Enable Bit
+     * |        |          |0 = Dynamic Compensation Disabled.
+     * |        |          |1 = Dynamic Compensation Enabled.
+     * @var RTC_T::WEEKDAY
+     * Offset: 0x18  RTC Day of the Week Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |WEEKDAY   |Day of the Week Register
+     * |        |          |000 = Sunday.
+     * |        |          |001 = Monday.
+     * |        |          |010 = Tuesday.
+     * |        |          |011 = Wednesday.
+     * |        |          |100 = Thursday.
+     * |        |          |101 = Friday.
+     * |        |          |110 = Saturday.
+     * |        |          |111 = Reserved.
+     * @var RTC_T::TALM
+     * Offset: 0x1C  RTC Time Alarm Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |SEC       |1-Sec Time Digit of Alarm Setting (0~9)
+     * |[6:4]   |TENSEC    |10-Sec Time Digit of Alarm Setting (0~5)
+     * |[11:8]  |MIN       |1-Min Time Digit of Alarm Setting (0~9)
+     * |[14:12] |TENMIN    |10-Min Time Digit of Alarm Setting (0~5)
+     * |[19:16] |HR        |1-Hour Time Digit of Alarm Setting (0~9)
+     * |[21:20] |TENHR     |10-Hour Time Digit of Alarm Setting (0~2)
+     * |        |          |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.)
+     * @var RTC_T::CALM
+     * Offset: 0x20  RTC Calendar Alarm Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |DAY       |1-Day Calendar Digit of Alarm Setting (0~9)
+     * |[5:4]   |TENDAY    |10-Day Calendar Digit of Alarm Setting (0~3)
+     * |[11:8]  |MON       |1-Month Calendar Digit of Alarm Setting (0~9)
+     * |[12]    |TENMON    |10-Month Calendar Digit of Alarm Setting (0~1)
+     * |[19:16] |YEAR      |1-Year Calendar Digit of Alarm Setting (0~9)
+     * |[23:20] |TENYEAR   |10-Year Calendar Digit of Alarm Setting (0~9)
+     * @var RTC_T::LEAPYEAR
+     * Offset: 0x24  RTC Leap Year Indicator Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |LEAPYEAR  |Leap Year Indication (Read Only)
+     * |        |          |0 = This year is not a leap year.
+     * |        |          |1 = This year is leap year.
+     * @var RTC_T::INTEN
+     * Offset: 0x28  RTC Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ALMIEN    |Alarm Interrupt Enable Bit
+     * |        |          |Set ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated.
+     * |        |          |0 = RTC Alarm interrupt Disabled.
+     * |        |          |1 = RTC Alarm interrupt Enabled.
+     * |[1]     |TICKIEN   |Time Tick Interrupt Enable Bit
+     * |        |          |Set TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated.
+     * |        |          |0 = RTC Time Tick interrupt Disabled.
+     * |        |          |1 = RTC Time Tick interrupt Enabled.
+     * |[8]     |TAMP0IEN  |Tamper 0 Interrupt Enable Bit
+     * |        |          |Set TAMP0IEN to 1 can also enable chip wake-up function when tamper 0 interrupt event is generated.
+     * |        |          |0 = Tamper 0 interrupt Disabled.
+     * |        |          |1 = Tamper 0 interrupt Enabled.
+     * |[9]     |TAMP1IEN  |Tamper 1 or Pair 0 Interrupt Enable Bit
+     * |        |          |Set TAMP1IEN to 1 can also enable chip wake-up function when tamper 1 interrupt event is generated.
+     * |        |          |0 = Tamper 1 or Pair 0 interrupt Disabled.
+     * |        |          |1 = Tamper 1 or Pair 0 interrupt Enabled.
+     * |[10]    |TAMP2IEN  |Tamper 2 Interrupt Enable Bit
+     * |        |          |Set TAMP2IEN to 1 can also enable chip wake-up function when tamper 2 interrupt event is generated.
+     * |        |          |0 = Tamper 2 interrupt Disabled.
+     * |        |          |1 = Tamper 2 interrupt Enabled.
+     * |[11]    |TAMP3IEN  |Tamper 3 or Pair 1 Interrupt Enable Bit
+     * |        |          |Set TAMP3IEN to 1 can also enable chip wake-up function when tamper 3 interrupt event is generated.
+     * |        |          |0 = Tamper 3 or Pair 1 interrupt Disabled.
+     * |        |          |1 = Tamper 3 or Pair 1 interrupt Enabled.
+     * |[12]    |TAMP4IEN  |Tamper 4 Interrupt Enable Bit
+     * |        |          |Set TAMP4IEN to 1 can also enable chip wake-up function when tamper 4 interrupt event is generated.
+     * |        |          |0 = Tamper 4 interrupt Disabled.
+     * |        |          |1 = Tamper 4 interrupt Enabled.
+     * |[13]    |TAMP5IEN  |Tamper 5 or Pair 2 Interrupt Enable Bit
+     * |        |          |Set TAMP5IEN to 1 can also enable chip wake-up function when tamper 5 interrupt event is generated.
+     * |        |          |0 = Tamper 5 or Pair 2 interrupt Disabled.
+     * |        |          |1 = Tamper 5 or Pair 2 interrupt Enabled.
+     * |[24]    |CLKFIEN   |LXT Clock Frequency Monitor Fail Interrupt Enable Bit
+     * |        |          |0 = LXT Frequency Fail interrupt Disabled.
+     * |        |          |1 = LXT Frequency Fail interrupt Enabled.
+     * |[25]    |CLKSTIEN  |LXT Clock Frequency Monitor Stop Interrupt Enable Bit
+     * |        |          |0 = LXT Frequency Stop interrupt Disabled.
+     * |        |          |1 = LXT Frequency Stop interrupt Enabled.
+     * @var RTC_T::INTSTS
+     * Offset: 0x2C  RTC Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ALMIF     |RTC Alarm Interrupt Flag
+     * |        |          |0 = Alarm condition is not matched.
+     * |        |          |1 = Alarm condition is matched.
+     * |        |          |Note: Write 1 to clear this bit.
+     * |[1]     |TICKIF    |RTC Time Tick Interrupt Flag
+     * |        |          |0 = Tick condition does not occur.
+     * |        |          |1 = Tick condition occur.
+     * |        |          |Note: Write 1 to clear this bit.
+     * |[8]     |TAMP0IF   |Tamper 0 Interrupt Flag
+     * |        |          |This bit is set when TAMP0_PIN detected level non-equal TAMP0LV (RTC_TAMPCTL[9]).
+     * |        |          |0 = No Tamper 0 interrupt flag is generated.
+     * |        |          |1 = Tamper 0 interrupt flag is generated.
+     * |        |          |Note1: Write 1 to clear this bit.
+     * |        |          |Note2: This interrupt flag will be generated again when Tamper setting condition is not restoration.
+     * |        |          |Note3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred.
+     * |[9]     |TAMP1IF   |Tamper 1 or Pair 0 Interrupt Flag
+     * |        |          |This bit is set when TAMP1_PIN detected level non-equal TAMP1LV (RTC_TAMPCTL[13]) or TAMP0_PIN and TAMP1_PIN disconnected during DYNPR0EN (RTC_TAMPCTL[15]) is activated.
+     * |        |          |0 = No Tamper 1 or Pair 0 interrupt flag is generated.
+     * |        |          |1 = Tamper 1 or Pair 0 interrupt flag is generated.
+     * |        |          |Note1: Write 1 to clear this bit.
+     * |        |          |Note2: This interrupt flag will be generated again when Tamper setting condition is not restoration.
+     * |        |          |Note3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred.
+     * |[10]    |TAMP2IF   |Tamper 2 Interrupt Flag
+     * |        |          |This bit is set when TAMP2_PIN detected level non-equal TAMP2LV (RTC_TAMPCTL[17]).
+     * |        |          |0 = No Tamper 2 interrupt flag is generated.
+     * |        |          |1 = Tamper 2 interrupt flag is generated.
+     * |        |          |Note1: Write 1 to clear this bit.
+     * |        |          |Note2: This interrupt flag will be generated again when Tamper setting condition is not restoration.
+     * |        |          |Note3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred.
+     * |[11]    |TAMP3IF   |Tamper 3 or Pair 1 Interrupt Flag
+     * |        |          |This bit is set when TAMP3_PIN detected level non-equal TAMP3LV (RTC_TAMPCTL[21]) or TAMP2_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) is activated or
+     * |        |          |TAMP0_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) and DYN1ISS (RTC_TAMPCTL[0]) are activated.
+     * |        |          |0 = No Tamper 3 or Pair 1 interrupt flag is generated.
+     * |        |          |1 = Tamper 3 or Pair 1 interrupt flag is generated.
+     * |        |          |Note1: Write 1 to clear this bit.
+     * |        |          |Note2: This interrupt flag will be generated again when Tamper setting condition is not restoration.
+     * |        |          |Note3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred.
+     * |[12]    |TAMP4IF   |Tamper 4 Interrupt Flag
+     * |        |          |This bit is set when TAMP4_PIN detected level non-equal TAMP4LV (RTC_TAMPCTL[25]).
+     * |        |          |0 = No Tamper 4 interrupt flag is generated.
+     * |        |          |1 = Tamper 4 interrupt flag is generated.
+     * |        |          |Note1: Write 1 to clear this bit.
+     * |        |          |Note2: This interrupt flag will be generated again when Tamper setting condition is not restoration.
+     * |        |          |Note3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred.
+     * |[13]    |TAMP5IF   |Tamper 5 or Pair 2 Interrupt Flag
+     * |        |          |This bit is set when TAMP5_PIN detected level non-equal TAMP5LV (RTC_TAMPCTL[29]) or TAMP4_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) is activated or
+     * |        |          |TAMP0_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) and DYN2ISS (RTC_TAMPCTL[1]) are activated.
+     * |        |          |0 = No Tamper 5 or Pair 2 interrupt flag is generated.
+     * |        |          |1 = Tamper 5 or Pair 2 interrupt flag is generated.
+     * |        |          |Note1: Write 1 to clear this bit.
+     * |        |          |Note2: This interrupt flag will be generated again when Tamper setting condition is not restoration.
+     * |        |          |Note3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred.
+     * |[24]    |CLKFIF    |LXT Clock Frequency Monitor Fail Interrupt Flag
+     * |        |          |0 = LXT frequency is normal.
+     * |        |          |1 = LXT frequency is abnormal.
+     * |        |          |Note1: Write 1 to clear the bit to 0.
+     * |        |          |Note2: LXT detector will automatic disable when Fail/Stop Flag rise, resume after Fail/Stop Flag clear.
+     * |[25]    |CLKSTIF   |LXT Clock Frequency Monitor Stop Interrupt Flag
+     * |        |          |0 = LXT frequency is normal.
+     * |        |          |1 = LXT frequency is almost stop.
+     * |        |          |Note1: Write 1 to clear the bit to 0.
+     * |        |          |Note2: LXT detector will automatic disable when Fail/Stop Flag rise, resume after Fail/Stop Flag clear.
+     * @var RTC_T::TICK
+     * Offset: 0x30  RTC Time Tick Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |TICK      |Time Tick Register
+     * |        |          |These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request.
+     * |        |          |000 = Time tick is 1 second.
+     * |        |          |001 = Time tick is 1/2 second.
+     * |        |          |010 = Time tick is 1/4 second.
+     * |        |          |011 = Time tick is 1/8 second.
+     * |        |          |100 = Time tick is 1/16 second.
+     * |        |          |101 = Time tick is 1/32 second.
+     * |        |          |110 = Time tick is 1/64 second.
+     * |        |          |111 = Time tick is 1/128 second.
+     * @var RTC_T::TAMSK
+     * Offset: 0x34  RTC Time Alarm Mask Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |MSEC      |Mask 1-Sec Time Digit of Alarm Setting (0~9)
+     * |[1]     |MTENSEC   |Mask 10-Sec Time Digit of Alarm Setting (0~5)
+     * |[2]     |MMIN      |Mask 1-Min Time Digit of Alarm Setting (0~9)
+     * |[3]     |MTENMIN   |Mask 10-Min Time Digit of Alarm Setting (0~5)
+     * |[4]     |MHR       |Mask 1-Hour Time Digit of Alarm Setting (0~9)
+     * |        |          |Note: MHR function is only for 24-hour time scale mode.
+     * |[5]     |MTENHR    |Mask 10-Hour Time Digit of Alarm Setting (0~2)
+     * |        |          |Note: MTENHR function is only for 24-hour time scale mode.
+     * @var RTC_T::CAMSK
+     * Offset: 0x38  RTC Calendar Alarm Mask Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |MDAY      |Mask 1-Day Calendar Digit of Alarm Setting (0~9)
+     * |[1]     |MTENDAY   |Mask 10-Day Calendar Digit of Alarm Setting (0~3)
+     * |[2]     |MMON      |Mask 1-Month Calendar Digit of Alarm Setting (0~9)
+     * |[3]     |MTENMON   |Mask 10-Month Calendar Digit of Alarm Setting (0~1)
+     * |[4]     |MYEAR     |Mask 1-Year Calendar Digit of Alarm Setting (0~9)
+     * |[5]     |MTENYEAR  |Mask 10-Year Calendar Digit of Alarm Setting (0~9)
+     * @var RTC_T::SPRCTL
+     * Offset: 0x3C  RTC Spare Functional Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2]     |SPRRWEN   |Spare Register Enable Bit
+     * |        |          |0 = Spare register Disabled.
+     * |        |          |1 = Spare register Enabled.
+     * |        |          |Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR19 cannot be accessed.
+     * |[5]     |SPRCSTS   |SPR Clear Flag
+     * |        |          |This bit indicates if the RTC_SPR0 ~ RTC_SPR19 content is cleared when specify tamper event is detected.
+     * |        |          |0 = Spare register content is not cleared.
+     * |        |          |1 = Spare register content is cleared.
+     * |        |          |Note 1: Writes 1 to clear this bit.
+     * |        |          |Note 2: This bit keep 1 when RTC_INTSTS[13:8] or RTC_INTSTS[25:24] are not equal zero.
+     * |[16]    |LXTFCLR   |LXT Clock Fail/Stop to Clear Spare Enable Bit
+     * |        |          |0 = LXT Fail/Stop to clear Spare register content Disabled.
+     * |        |          |1 = LXT Fail/Stop to clear Spare register content Enabled.
+     * @var RTC_T::SPR[20]
+     * Offset: 0x40 ~ 0x8C  RTC Spare Register 0 ~ 19
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SPARE     |Spare Register
+     * |        |          |This field is used to store back-up information defined by user.
+     * |        |          |This field will be cleared by hardware automatically in the following conditions, a tamper pin event is detected,
+     * |        |          |LXT clock fail/stop event occurs if LXTFCLR(RTC_SPRCTL[16]) is 1, or after Flash mass operation.
+     * @var RTC_T::LXTCTL
+     * Offset: 0x100  RTC 32.768 kHz Oscillator Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |LIRC32KEN |Enable LIRC32K Source
+     * |        |          |0 = LIRC32K Disabled.
+     * |        |          |1 = LIRC32K Enabled.
+     * |[3:1]   |GAIN      |Oscillator Gain Option
+     * |        |          |User can select oscillator gain according to crystal external loading and operating temperature range.
+     * |        |          |The larger gain value corresponding to stronger driving capability and higher power consumption.
+     * |        |          |000 = L0 mode.
+     * |        |          |001 = L1 mode.
+     * |        |          |010 = L2 mode.
+     * |        |          |011 = L3 mode.
+     * |        |          |100 = L4 mode.
+     * |        |          |101 = L5 mode.
+     * |        |          |110 = L6 mode.
+     * |        |          |111 = L7 mode (Default).
+     * |[6]     |C32KSEL   |Clock 32K Source Selection
+     * |        |          |0 = Clock source from external low speed crystal oscillator (LXT).
+     * |        |          |1 = Clock source from internal low speed RC 32K oscillator (LIRC32K).
+     * |[7]     |RTCCKSEL  |RTC Clock Source Selection
+     * |        |          |0 = Clock source from external low speed crystal oscillator (LXT) or internal low speed RC 32K oscillator (LIRC32K) depended on C32KSEL value.
+     * |        |          |1 = Clock source from internal low speed RC oscillator (LIRC).
+     * |[8]     |IOCTLSEL  |IO Pin Backup Control Selection
+     * |        |          |When low speed 32 kHz oscillator is disabled or TAMPxEN is disabled,
+     * |        |          |PF.4 pin (X32KO pin), PF.5 pin (X32KI pin) or PF.6~11 pin (TAMPERx pin) can be used as GPIO function.
+     * |        |          |User can program IOCTLSEL to decide PF.4~11 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0/1 control register.
+     * |        |          |0 = PF.4~11 pin I/O function is controlled by GPIO module.
+     * |        |          |1 = PF.4~11 pin I/O function is controlled by VBAT power domain.
+     * |        |          |Note: IOCTLSEL will automatically be set by hardware to 1 when system power is off and any writable RTC registers has been written at RTCCKEN(CLK_APBCLK0[1]) enabled.
+     * @var RTC_T::GPIOCTL0
+     * Offset: 0x104  RTC GPIO Control 0 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |OPMODE0   |IO Operation Mode
+     * |        |          |00 = PF.4 is input only mode.
+     * |        |          |01 = PF.4 is output push pull mode.
+     * |        |          |10 = PF.4 is open drain mode.
+     * |        |          |11 = PF.4 is quasi-bidirectional mod.
+     * |[2]     |DOUT0     |IO Output Data
+     * |        |          |0 = PF.4 output low.
+     * |        |          |1 = PF.4 output high.
+     * |[3]     |DINOFF0   |IO Pin Digital Input Path Disable Bit
+     * |        |          |0 = PF.4 digital input path Enabled.
+     * |        |          |1 = PF.4 digital input path Disabled (digital input tied to low).
+     * |[5:4]   |PUSEL0    |IO Pull-up and Pull-down Enable Bits
+     * |        |          |Determine PF.4 I/O pull-up or pull-down.
+     * |        |          |00 = PF.4 pull-up and pull-down Disabled.
+     * |        |          |01 = PF.4 pull-up Enabled.
+     * |        |          |10 = PF.4 pull-down Enabled.
+     * |        |          |11 = PF.4 pull-up and pull-down Disabled.
+     * |        |          |Note: Basically, the pull-up control and pull-down control has following behavior limitation.
+     * |        |          |The independent pull-up/pull-down control register is only valid when OPMODE0 is set as input tri-state and open-drain mode.
+     * |[9:8]   |OPMODE1   |IO Operation Mode
+     * |        |          |00 = PF.5 is input only mode.
+     * |        |          |01 = PF.5 is output push pull mode.
+     * |        |          |10 = PF.5 is open drain mode.
+     * |        |          |11 = PF.5 is quasi-bidirectional mod.
+     * |[10]    |DOUT1     |IO Output Data
+     * |        |          |0 = PF.5 output low.
+     * |        |          |1 = PF.5 output high.
+     * |[11     |DINOFF1   |IO Pin Digital Input Path Disable Bit
+     * |        |          |0 = PF.5 digital input path Enabled.
+     * |        |          |1 = PF.5 digital input path Disabled (digital input tied to low).
+     * |[13:12] |PUSEL1    |IO Pull-up and Pull-down Enable Bits
+     * |        |          |Determine PF.5 I/O pull-up or pull-down.
+     * |        |          |00 = PF.5 pull-up and pull-down Disabled.
+     * |        |          |01 = PF.5 pull-up Enabled.
+     * |        |          |10 = PF.5 pull-down Enabled.
+     * |        |          |11 = PF.5 pull-up and pull-down Disabled.
+     * |        |          |Note: Basically, the pull-up control and pull-down control has following behavior limitation.
+     * |        |          |The independent pull-up/pull-down control register is only valid when OPMODE1 is set as input tri-state and open-drain mode.
+     * |[17:16] |OPMODE2   |IO Operation Mode
+     * |        |          |00 = PF.6 is input only mode.
+     * |        |          |01 = PF.6 is output push pull mode.
+     * |        |          |10 = PF.6 is open drain mode.
+     * |        |          |11 = PF.6 is quasi-bidirectional mod.
+     * |[18]    |DOUT2     |IO Output Data
+     * |        |          |0 = PF.6 output low.
+     * |        |          |1 = PF.6 output high.
+     * |[19     |DINOFF2   |IO Pin Digital Input Path Disable Bit
+     * |        |          |0 = PF.6 digital input path Enabled.
+     * |        |          |1 = PF.6 digital input path Disabled (digital input tied to low).
+     * |[21:20] |PUSEL2    |IO Pull-up and Pull-down Enable Bits
+     * |        |          |Determine PF.6 I/O pull-up or pull-down.
+     * |        |          |00 = PF.6 pull-up and pull-down Disabled.
+     * |        |          |01 = PF.6 pull-up Enabled.
+     * |        |          |10 = PF.6 pull-down Enabled.
+     * |        |          |11 = PF.6 pull-up and pull-down Disabled.
+     * |        |          |Note: Basically, the pull-up control and pull-down control has following behavior limitation.
+     * |        |          |The independent pull-up/pull-down control register is only valid when OPMODE2 is set as input tri-state and open-drain mode.
+     * |[25:24] |OPMODE3   |IO Operation Mode
+     * |        |          |00 = PF.7 is input only mode.
+     * |        |          |01 = PF.7 is output push pull mode.
+     * |        |          |10 = PF.7 is open drain mode.
+     * |        |          |11 = PF.7 is quasi-bidirectional mod.
+     * |[26]    |DOUT3     |IO Output Data
+     * |        |          |0 = PF.7 output low.
+     * |        |          |1 = PF.7 output high.
+     * |[27     |DINOFF3   |IO Pin Digital Input Path Disable Bit
+     * |        |          |0 = PF.7 digital input path Enabled.
+     * |        |          |1 = PF.7 digital input path Disabled (digital input tied to low).
+     * |[29:28] |PUSEL3    |IO Pull-up and Pull-down Enable Bits
+     * |        |          |Determine PF.7 I/O pull-up or pull-down.
+     * |        |          |00 = PF.7 pull-up and pull-down Disabled.
+     * |        |          |01 = PF.7 pull-up Enabled.
+     * |        |          |10 = PF.7 pull-down Enabled.
+     * |        |          |11 = PF.7 pull-up and pull-down Disabled.
+     * |        |          |Note: Basically, the pull-up control and pull-down control has following behavior limitation.
+     * |        |          |The independent pull-up/pull-down control register is only valid when OPMODE3 is set as input tri-state and open-drain mode.
+     * @var RTC_T::GPIOCTL1
+     * Offset: 0x108  RTC GPIO Control 1 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |OPMODE4   |IO Operation Mode
+     * |        |          |00 = PF.8 is input only mode.
+     * |        |          |01 = PF.8 is output push pull mode.
+     * |        |          |10 = PF.8 is open drain mode.
+     * |        |          |11 = PF.8 is quasi-bidirectional mod.
+     * |[2]     |DOUT4     |IO Output Data
+     * |        |          |0 = PF.8 output low.
+     * |        |          |1 = PF.8 output high.
+     * |[3]     |DINOFF4   |IO Pin Digital Input Path Disable Bit
+     * |        |          |0 = PF.8 digital input path Enabled.
+     * |        |          |1 = PF.8 digital input path Disabled (digital input tied to low).
+     * |[5:4]   |PUSEL4    |IO Pull-up and Pull-down Enable Bits
+     * |        |          |Determine PF.8 I/O pull-up or pull-down.
+     * |        |          |00 = PF.8 pull-up and pull-down Disabled.
+     * |        |          |01 = PF.8 pull-up Enabled.
+     * |        |          |10 = PF.8 pull-down Enabled.
+     * |        |          |11 = PF.8 pull-up and pull-down Disabled.
+     * |        |          |Note: Basically, the pull-up control and pull-down control has following behavior limitation.
+     * |        |          |The independent pull-up/pull-down control register is only valid when OPMODE4 is set as input tri-state and open-drain mode.
+     * |[9:8]   |OPMODE5   |IO Operation Mode
+     * |        |          |00 = PF.9 is input only mode.
+     * |        |          |01 = PF.9 is output push pull mode.
+     * |        |          |10 = PF.9 is open drain mode.
+     * |        |          |11 = PF.9 is quasi-bidirectional mod.
+     * |[10]    |DOUT5     |IO Output Data
+     * |        |          |0 = PF.9 output low.
+     * |        |          |1 = PF.9 output high.
+     * |[11     |DINOFF5   |IO Pin Digital Input Path Disable Bit
+     * |        |          |0 = PF.9 digital input path Enabled.
+     * |        |          |1 = PF.9 digital input path Disabled (digital input tied to low).
+     * |[13:12] |PUSEL5    |IO Pull-up and Pull-down Enable Bits
+     * |        |          |Determine PF.9 I/O pull-up or pull-down.
+     * |        |          |00 = PF.9 pull-up and pull-down Disabled.
+     * |        |          |01 = PF.9 pull-up Enabled.
+     * |        |          |10 = PF.9 pull-down Enabled.
+     * |        |          |11 = PF.9 pull-up and pull-down Disabled.
+     * |        |          |Note: Basically, the pull-up control and pull-down control has following behavior limitation.
+     * |        |          |The independent pull-up/pull-down control register is only valid when OPMODE5 is set as input tri-state and open-drain mode.
+     * |[17:16] |OPMODE6   |IO Operation Mode
+     * |        |          |00 = PF.10 is input only mode.
+     * |        |          |01 = PF.10 is output push pull mode.
+     * |        |          |10 = PF.10 is open drain mode.
+     * |        |          |11 = PF.10 is quasi-bidirectional mod.
+     * |[18]    |DOUT6     |IO Output Data
+     * |        |          |0 = PF.10 output low.
+     * |        |          |1 = PF.10 output high.
+     * |[19     |DINOFF6   |IO Pin Digital Input Path Disable Bit
+     * |        |          |0 = PF.10 digital input path Enabled.
+     * |        |          |1 = PF.10 digital input path Disabled (digital input tied to low).
+     * |[21:20] |PUSEL6    |IO Pull-up and Pull-down Enable Bits
+     * |        |          |Determine PF.10 I/O pull-up or pull-down.
+     * |        |          |00 = PF.10 pull-up and pull-down Disabled.
+     * |        |          |01 = PF.10 pull-up Enabled.
+     * |        |          |10 = PF.10 pull-down Enabled.
+     * |        |          |11 = PF.10 pull-up and pull-down Disabled.
+     * |        |          |Note: Basically, the pull-up control and pull-down control has following behavior limitation.
+     * |        |          |The independent pull-up/pull-down control register is only valid when OPMODE6 is set as input tri-state and open-drain mode.
+     * |[25:24] |OPMODE7   |IO Operation Mode
+     * |        |          |00 = PF.11 is input only mode.
+     * |        |          |01 = PF.11 is output push pull mode.
+     * |        |          |10 = PF.11 is open drain mode.
+     * |        |          |11 = PF.11 is quasi-bidirectional mod.
+     * |[26]    |DOUT7     |IO Output Data
+     * |        |          |0 = PF.11 output low.
+     * |        |          |1 = PF.11 output high.
+     * |[27     |DINOFF7   |IO Pin Digital Input Path Disable Bit
+     * |        |          |0 = PF.11 digital input path Enabled.
+     * |        |          |1 = PF.11 digital input path Disabled (digital input tied to low).
+     * |[29:28] |PUSEL7    |IO Pull-up and Pull-down Enable Bits
+     * |        |          |Determine PF.11 I/O pull-up or pull-down.
+     * |        |          |00 = PF.11 pull-up and pull-down Disabled.
+     * |        |          |01 = PF.11 pull-up Enabled.
+     * |        |          |10 = PF.11 pull-down Enabled.
+     * |        |          |11 = PF.11 pull-up and pull-down Disabled.
+     * |        |          |Note: Basically, the pull-up control and pull-down control has following behavior limitation.
+     * |        |          |The independent pull-up/pull-down control register is only valid when OPMODE7 is set as input tri-state and open-drain mode.
+     * @var RTC_T::DSTCTL
+     * Offset: 0x110  RTC Daylight Saving Time Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ADDHR     |Add 1 Hour
+     * |        |          |0 = No effect.
+     * |        |          |1 = Indicates RTC hour digit has been added one hour for summer time change.
+     * |[1]     |SUBHR     |Subtract 1 Hour
+     * |        |          |0 = No effect.
+     * |        |          |1 = Indicates RTC hour digit has been subtracted one hour for winter time change.
+     * |[2]     |DSBAK     |Daylight Saving Back
+     * |        |          |0 = Daylight Saving Change is not performed.
+     * |        |          |1 = Daylight Saving Change is performed.
+     * @var RTC_T::TAMPCTL
+     * Offset: 0x120  RTC Tamper Pin Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |DYN1ISS   |Dynamic Pair 1 Input Source Select
+     * |        |          |This bit determine Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode.
+     * |        |          |0 = Tamper input is from Tamper 2.
+     * |        |          |1 = Tamper input is from Tamper 0.
+     * |        |          |Note: This bit is effective only when DYNPR1EN (RTC_TAMPCTL[23]) and DYNPR0EN (RTC_TAMPCTL[15]) are set.
+     * |[1]     |DYN2ISS   |Dynamic Pair 2 Input Source Select
+     * |        |          |This bit determine Tamper 5 input is from Tamper 4 or Tamper 0 in dynamic mode.
+     * |        |          |0 = Tamper input is from Tamper 4.
+     * |        |          |1 = Tamper input is from Tamper 0.
+     * |        |          |Note: This bit is effective only when DYNPR2EN (RTC_TAMPCTL[31]) and DYNPR0EN (RTC_TAMPCTL[15]) are set.
+     * |[3]     |DYNSRC    |Dynamic Reference Pattern
+     * |        |          |This fields determine the new reference pattern when current pattern run out in dynamic pair mode.
+     * |        |          |0 = The new reference pattern is generated by random number generator when the reference pattern run out.
+     * |        |          |1 = The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out.
+     * |        |          |Note: After this bit is modified, the SEEDRLD (RTC_TAMPCTL[4]) should be set.
+     * |[4]     |SEEDRLD   |Reload New Seed for PRNG Engine
+     * |        |          |Setting this bit, the tamper configuration will be reload.
+     * |        |          |0 = Generating key based on the current seed.
+     * |        |          |1 = Reload new seed.
+     * |        |          |Note 1: Before this bit is set, the tamper configuration should be set to complete and this bit will be auto clear to 0 after reload new seed completed.
+     * |        |          |Note 2: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock.
+     * |[7:5]   |DYNRATE   |Dynamic Change Rate
+     * |        |          |This item is choice the dynamic tamper output change rate.
+     * |        |          |000 = 2^10 * RTC_CLK.
+     * |        |          |001 = 2^11 * RTC_CLK.
+     * |        |          |010 = 2^12 * RTC_CLK.
+     * |        |          |011 = 2^13 * RTC_CLK.
+     * |        |          |100 = 2^14 * RTC_CLK.
+     * |        |          |101 = 2^15 * RTC_CLK.
+     * |        |          |110 = 2^16 * RTC_CLK.
+     * |        |          |111 = 2^17 * RTC_CLK.
+     * |        |          |Note: After revising this field, set SEEDRLD (RTC_TAMPCTL[4]) can reload change rate immediately.
+     * |[8]     |TAMP0EN   |Tamper0 Detect Enable Bit
+     * |        |          |0 = Tamper 0 detect Disabled.
+     * |        |          |1 = Tamper 0 detect Enabled.
+     * |        |          |Note1: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock.
+     * |[9]     |TAMP0LV   |Tamper 0 Level
+     * |        |          |This bit depend on level attribute of tamper pin for static tamper detection.
+     * |        |          |0 = Detect voltage level is low.
+     * |        |          |1 = Detect voltage level is high.
+     * |[10]    |TAMP0DBEN |Tamper 0 De-bounce Enable Bit
+     * |        |          |0 = Tamper 0 de-bounce Disabled.
+     * |        |          |1 = Tamper 0 de-bounce Enabled.
+     * |[12]    |TAMP1EN   |Tamper 1 Detect Enable Bit
+     * |        |          |0 = Tamper 1 detect Disabled.
+     * |        |          |1 = Tamper 1 detect Enabled.
+     * |        |          |Note1: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock.
+     * |[13]    |TAMP1LV   |Tamper 1 Level
+     * |        |          |This bit depend on level attribute of tamper pin for static tamper detection.
+     * |        |          |0 = Detect voltage level is low.
+     * |        |          |1 = Detect voltage level is high.
+     * |[14]    |TAMP1DBEN |Tamper 1 De-bounce Enable Bit
+     * |        |          |0 = Tamper 1 de-bounce Disabled.
+     * |        |          |1 = Tamper 1 de-bounce Enabled.
+     * |[15]    |DYNPR0EN  |Dynamic Pair 0 Enable Bit
+     * |        |          |0 = Static detect.
+     * |        |          |1 = Dynamic detect.
+     * |[16]    |TAMP2EN   |Tamper 2 Detect Enable Bit
+     * |        |          |0 = Tamper 2 detect Disabled.
+     * |        |          |1 = Tamper 2 detect Enabled.
+     * |        |          |Note1: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock.
+     * |[17]    |TAMP2LV   |Tamper 2 Level
+     * |        |          |This bit depend on level attribute of tamper pin for static tamper detection.
+     * |        |          |0 = Detect voltage level is low.
+     * |        |          |1 = Detect voltage level is high.
+     * |[18]    |TAMP2DBEN |Tamper 2 De-bounce Enable Bit
+     * |        |          |0 = Tamper 2 de-bounce Disabled.
+     * |        |          |1 = Tamper 2 de-bounce Enabled.
+     * |[20]    |TAMP3EN   |Tamper 3 Detect Enable Bit
+     * |        |          |0 = Tamper 3 detect Disabled.
+     * |        |          |1 = Tamper 3 detect Enabled.
+     * |        |          |Note1: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock.
+     * |[21]    |TAMP3LV   |Tamper 3 Level
+     * |        |          |This bit depend on level attribute of tamper pin for static tamper detection.
+     * |        |          |0 = Detect voltage level is low.
+     * |        |          |1 = Detect voltage level is high.
+     * |[22]    |TAMP3DBEN |Tamper 3 De-bounce Enable Bit
+     * |        |          |0 = Tamper 3 de-bounce Disabled.
+     * |        |          |1 = Tamper 3 de-bounce Enabled.
+     * |[23]    |DYNPR1EN  |Dynamic Pair 1 Enable Bit
+     * |        |          |0 = Static detect.
+     * |        |          |1 = Dynamic detect.
+     * |[24]    |TAMP4EN   |Tamper4 Detect Enable Bit
+     * |        |          |0 = Tamper 4 detect Disabled.
+     * |        |          |1 = Tamper 4 detect Enabled.
+     * |        |          |Note1: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock.
+     * |[25]    |TAMP4LV   |Tamper 4 Level
+     * |        |          |This bit depend on level attribute of tamper pin for static tamper detection.
+     * |        |          |0 = Detect voltage level is low.
+     * |        |          |1 = Detect voltage level is high.
+     * |[26]    |TAMP4DBEN |Tamper 4 De-bounce Enable Bit
+     * |        |          |0 = Tamper 4 de-bounce Disabled.
+     * |        |          |1 = Tamper 4 de-bounce Enabled.
+     * |[28]    |TAMP5EN   |Tamper 5 Detect Enable Bit
+     * |        |          |0 = Tamper 5 detect Disabled.
+     * |        |          |1 = Tamper 5 detect Enabled.
+     * |        |          |Note1: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock.
+     * |[29]    |TAMP5LV   |Tamper 5 Level
+     * |        |          |This bit depend on level attribute of tamper pin for static tamper detection.
+     * |        |          |0 = Detect voltage level is low.
+     * |        |          |1 = Detect voltage level is high.
+     * |[30]    |TAMP5DBEN |Tamper 5 De-bounce Enable Bit
+     * |        |          |0 = Tamper 5 de-bounce Disabled.
+     * |        |          |1 = Tamper 5 de-bounce Enabled.
+     * |[31]    |DYNPR2EN  |Dynamic Pair 2 Enable Bit
+     * |        |          |0 = Static detect.
+     * |        |          |1 = Dynamic detect.
+     * @var RTC_T::TAMPSEED
+     * Offset: 0x128  RTC Tamper Dynamic Seed Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SEED      |Seed Value
+     * @var RTC_T::TAMPTIME
+     * Offset: 0x130  RTC Tamper Time Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |SEC       |1-Sec Time Digit of TAMPER Time (0~9)
+     * |[6:4]   |TENSEC    |10-Sec Time Digit of TAMPER Time (0~5)
+     * |[11:8]  |MIN       |1-Min Time Digit of TAMPER Time (0~9)
+     * |[14:12] |TENMIN    |10-Min Time Digit of TAMPER Time (0~5)
+     * |[19:16] |HR        |1-Hour Time Digit of TAMPER Time (0~9)
+     * |[21:20] |TENHR     |10-Hour Time Digit of TAMPER Time (0~2)
+     * |        |          |Note: 24-hour time scale only.
+     * @var RTC_T::TAMPCAL
+     * Offset: 0x134  RTC Tamper Calendar Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |DAY       |1-Day Calendar Digit of TAMPER Calendar (0~9)
+     * |[5:4]   |TENDAY    |10-Day Calendar Digit of TAMPER Calendar (0~3)
+     * |[11:8]  |MON       |1-Month Calendar Digit of TAMPER Calendar (0~9)
+     * |[12]    |TENMON    |10-Month Calendar Digit of TAMPER Calendar (0~1)
+     * |[19:16] |YEAR      |1-Year Calendar Digit of TAMPER Calendar (0~9)
+     * |[23:20] |TENYEAR   |10-Year Calendar Digit of TAMPER Calendar (0~9)
+     * @var RTC_T::CLKDCTL
+     * Offset: 0x140  RTC Clock Fail Detector Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |LXTFDEN   |LXT Clock Fail/Stop Detector Enable Bit
+     * |        |          |0 = LXT clock Fail/Stop detector Disabled.
+     * |        |          |1 = LXT clock Fail/Stop detector Enabled.
+     * |        |          |Note: LXT detector will automatic disable when Fail/Stop Flag rise, resume after Fail/Stop Flag clear.
+     * |[1]     |LXTFSW    |LXT Clock Fail Detector Switch LIRC32K Enable Bit
+     * |        |          |0 = LXT clock Fail switch LIRC32K Disabled.
+     * |        |          |1 = LXT clock Fail detector rise, RTC clock source switch from LIRC32K.
+     * |        |          |If LXT clock fail detector flag CLKFIF (RTC_INTSTS[24]) is generated, RTC clock source will switch to LIRC32K automatically.
+     * |[2]     |LXTSTSW   |LXT Clock Stop Detector Switch LIRC32K Enable Bit
+     * |        |          |0 = LXT clock Stop switch LIRC32K Disabled.
+     * |        |          |1 = LXT clock Stop detector rise, RTC clock source switch from LIRC32K.
+     * |        |          |If LXT clock stop detector flag CLKSTIF (RTC_INTSTS[25]) is generated, RTC clock source will switch to LIRC32K automatically
+     * |[16]    |SWLIRCF   |LXT Clock Detector Fail/Stop Switch LIRC32K Flag (Read Only)
+     * |        |          |0 = Indicate RTC clock source from LXT.
+     * |        |          |1 = Indicate RTC clock source from LIRC32K.
+     * |[17]    |LXTSLOWF  |LXT Slower Than LIRC32K Flag (Read Only)
+     * |        |          |0 = LXT frequency faster than LIRC32K.
+     * |        |          |1 = LXT frequency is slowly.
+     * |        |          |Note: LXTSLOWF is vaild during CLKSTIF (RTC_INTSTS[25]) or CLKFIF (RTC_INTSTS[24]) rising.
+     * @var RTC_T::CDBR
+     * Offset: 0x144  RTC Clock Frequency Detector Boundary Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |STOPBD    |LXT Clock Stop Frequency Detector Stop Boundary
+     * |        |          |These bits define the stop value of frequency monitor window.
+     * |        |          |When LXT frequency monitor counter lower than STOPBD, the LXT frequency detect Stop interrupt flag will set to 1.
+     * |        |          |Note: The boundary is defined as the maximum value of LXT among 256 LIRC32K clock time.
+     * |[23:16] |FAILBD    |LXT Clock Frequency Detector Fail Boundary
+     * |        |          |These bits define the fail value of frequency monitor window.
+     * |        |          |When LXT frequency monitor counter lower than FAILBD, the LXT frequency detect fail interrupt flag will set to 1.
+     * |        |          |Note: The boundary is defined as the maximum value of LXT among 256 LIRC32K clock time.
+     */
+    __IO uint32_t INIT;                  /*!< [0x0000] RTC Initiation Register                                          */
+    __I uint32_t  RESERVE0[1];           /* 0x4 */
+    __IO uint32_t FREQADJ;               /*!< [0x0008] RTC Frequency Compensation Register                              */
+    __IO uint32_t TIME;                  /*!< [0x000c] RTC Time Loading Register                                        */
+    __IO uint32_t CAL;                   /*!< [0x0010] RTC Calendar Loading Register                                    */
+    __IO uint32_t CLKFMT;                /*!< [0x0014] RTC Time Scale Selection Register                                */
+    __IO uint32_t WEEKDAY;               /*!< [0x0018] RTC Day of the Week Register                                     */
+    __IO uint32_t TALM;                  /*!< [0x001c] RTC Time Alarm Register                                          */
+    __IO uint32_t CALM;                  /*!< [0x0020] RTC Calendar Alarm Register                                      */
+    __I  uint32_t LEAPYEAR;              /*!< [0x0024] RTC Leap Year Indicator Register                                 */
+    __IO uint32_t INTEN;                 /*!< [0x0028] RTC Interrupt Enable Register                                    */
+    __IO uint32_t INTSTS;                /*!< [0x002c] RTC Interrupt Status Register                                    */
+    __IO uint32_t TICK;                  /*!< [0x0030] RTC Time Tick Register                                           */
+    __IO uint32_t TAMSK;                 /*!< [0x0034] RTC Time Alarm Mask Register                                     */
+    __IO uint32_t CAMSK;                 /*!< [0x0038] RTC Calendar Alarm Mask Register                                 */
+    __IO uint32_t SPRCTL;                /*!< [0x003c] RTC Spare Functional Control Register                            */
+    __IO uint32_t SPR[20];               /*!< [0x0040] ~ [0x008C] RTC Spare Register 0 ~ 19                             */
+    __I  uint32_t RESERVE1[28];          /* 0x90 ~ 0xfc */
+    __IO uint32_t LXTCTL;                /*!< [0x0100] RTC 32.768 kHz Oscillator Control Register                       */
+    __IO uint32_t GPIOCTL0;              /*!< [0x0104] RTC GPIO Control 0 Register                                      */
+    __IO uint32_t GPIOCTL1;              /*!< [0x0108] RTC GPIO Control 1 Register                                      */
+    __I  uint32_t RESERVE2[1];           /* 0x10c */
+    __IO uint32_t DSTCTL;                /*!< [0x0110] RTC Daylight Saving Time Control Register                        */
+    __I  uint32_t RESERVE3[3];           /* 0x114 ~ 0x11c */
+    __IO uint32_t TAMPCTL;               /*!< [0x0120] RTC Tamper Pin Control Register                                  */
+    __I  uint32_t RESERVE4[1];           /* 0x124 */
+    __IO uint32_t TAMPSEED;              /*!< [0x0128] RTC Tamper Dynamic Seed Register                                 */
+    __I  uint32_t RESERVE5[1];           /* 0x12c */
+    __I  uint32_t TAMPTIME;              /*!< [0x0130] RTC Tamper Time Register                                         */
+    __I  uint32_t TAMPCAL;               /*!< [0x0134] RTC Tamper Calendar Register                                     */
+    __I  uint32_t RESERVE6[2];           /* 0x138 ~ 0x13c */
+    __IO uint32_t CLKDCTL;               /*!< [0x0140] RTC Clock Fail Detector Control Register                         */
+    __IO uint32_t CDBR;                  /*!< [0x0144] RTC Clock Frequency Detector Boundary Register                   */
+
+} RTC_T;
+
+/**
+    @addtogroup RTC_CONST RTC Bit Field Definition
+    Constant Definitions for RTC Controller
+  @{
+*/
+
+#define RTC_INIT_ACTIVE_Pos              (0)                                               /*!< RTC_T::INIT: ACTIVE Position           */
+#define RTC_INIT_ACTIVE_Msk              (0x1ul << RTC_INIT_ACTIVE_Pos)                    /*!< RTC_T::INIT: ACTIVE Mask               */
+
+#define RTC_INIT_INIT_Pos                (1)                                               /*!< RTC_T::INIT: INIT Position             */
+#define RTC_INIT_INIT_Msk                (0x7ffffffful << RTC_INIT_INIT_Pos)               /*!< RTC_T::INIT: INIT Mask                 */
+
+#define RTC_FREQADJ_FRACTION_Pos         (0)                                               /*!< RTC_T::FREQADJ: FRACTION Position      */
+#define RTC_FREQADJ_FRACTION_Msk         (0x3ful << RTC_FREQADJ_FRACTION_Pos)              /*!< RTC_T::FREQADJ: FRACTION Mask          */
+
+#define RTC_FREQADJ_INTEGER_Pos          (8)                                               /*!< RTC_T::FREQADJ: INTEGER Position       */
+#define RTC_FREQADJ_INTEGER_Msk          (0x1ful << RTC_FREQADJ_INTEGER_Pos)               /*!< RTC_T::FREQADJ: INTEGER Mask           */
+
+#define RTC_FREQADJ_FCRBUSY_Pos          (31)                                              /*!< RTC_T::FREQADJ: FCRBUSY Position       */
+#define RTC_FREQADJ_FCRBUSY_Msk          (0x1ul << RTC_FREQADJ_FCRBUSY_Pos)                /*!< RTC_T::FREQADJ: FCRBUSY Mask           */
+
+#define RTC_TIME_SEC_Pos                 (0)                                               /*!< RTC_T::TIME: SEC Position              */
+#define RTC_TIME_SEC_Msk                 (0xful << RTC_TIME_SEC_Pos)                       /*!< RTC_T::TIME: SEC Mask                  */
+
+#define RTC_TIME_TENSEC_Pos              (4)                                               /*!< RTC_T::TIME: TENSEC Position           */
+#define RTC_TIME_TENSEC_Msk              (0x7ul << RTC_TIME_TENSEC_Pos)                    /*!< RTC_T::TIME: TENSEC Mask               */
+
+#define RTC_TIME_MIN_Pos                 (8)                                               /*!< RTC_T::TIME: MIN Position              */
+#define RTC_TIME_MIN_Msk                 (0xful << RTC_TIME_MIN_Pos)                       /*!< RTC_T::TIME: MIN Mask                  */
+
+#define RTC_TIME_TENMIN_Pos              (12)                                              /*!< RTC_T::TIME: TENMIN Position           */
+#define RTC_TIME_TENMIN_Msk              (0x7ul << RTC_TIME_TENMIN_Pos)                    /*!< RTC_T::TIME: TENMIN Mask               */
+
+#define RTC_TIME_HR_Pos                  (16)                                              /*!< RTC_T::TIME: HR Position               */
+#define RTC_TIME_HR_Msk                  (0xful << RTC_TIME_HR_Pos)                        /*!< RTC_T::TIME: HR Mask                   */
+
+#define RTC_TIME_TENHR_Pos               (20)                                              /*!< RTC_T::TIME: TENHR Position            */
+#define RTC_TIME_TENHR_Msk               (0x3ul << RTC_TIME_TENHR_Pos)                     /*!< RTC_T::TIME: TENHR Mask                */
+
+#define RTC_CAL_DAY_Pos                  (0)                                               /*!< RTC_T::CAL: DAY Position               */
+#define RTC_CAL_DAY_Msk                  (0xful << RTC_CAL_DAY_Pos)                        /*!< RTC_T::CAL: DAY Mask                   */
+
+#define RTC_CAL_TENDAY_Pos               (4)                                               /*!< RTC_T::CAL: TENDAY Position            */
+#define RTC_CAL_TENDAY_Msk               (0x3ul << RTC_CAL_TENDAY_Pos)                     /*!< RTC_T::CAL: TENDAY Mask                */
+
+#define RTC_CAL_MON_Pos                  (8)                                               /*!< RTC_T::CAL: MON Position               */
+#define RTC_CAL_MON_Msk                  (0xful << RTC_CAL_MON_Pos)                        /*!< RTC_T::CAL: MON Mask                   */
+
+#define RTC_CAL_TENMON_Pos               (12)                                              /*!< RTC_T::CAL: TENMON Position            */
+#define RTC_CAL_TENMON_Msk               (0x1ul << RTC_CAL_TENMON_Pos)                     /*!< RTC_T::CAL: TENMON Mask                */
+
+#define RTC_CAL_YEAR_Pos                 (16)                                              /*!< RTC_T::CAL: YEAR Position              */
+#define RTC_CAL_YEAR_Msk                 (0xful << RTC_CAL_YEAR_Pos)                       /*!< RTC_T::CAL: YEAR Mask                  */
+
+#define RTC_CAL_TENYEAR_Pos              (20)                                              /*!< RTC_T::CAL: TENYEAR Position           */
+#define RTC_CAL_TENYEAR_Msk              (0xful << RTC_CAL_TENYEAR_Pos)                    /*!< RTC_T::CAL: TENYEAR Mask               */
+
+#define RTC_CLKFMT_24HEN_Pos             (0)                                               /*!< RTC_T::CLKFMT: 24HEN Position          */
+#define RTC_CLKFMT_24HEN_Msk             (0x1ul << RTC_CLKFMT_24HEN_Pos)                   /*!< RTC_T::CLKFMT: 24HEN Mask              */
+
+#define RTC_CLKFMT_DCOMPEN_Pos           (16)                                              /*!< RTC_T::CLKFMT: DCOMPEN Position        */
+#define RTC_CLKFMT_DCOMPEN_Msk           (0x1ul << RTC_CLKFMT_DCOMPEN_Pos)                 /*!< RTC_T::CLKFMT: DCOMPEN Mask            */
+
+#define RTC_WEEKDAY_WEEKDAY_Pos          (0)                                               /*!< RTC_T::WEEKDAY: WEEKDAY Position       */
+#define RTC_WEEKDAY_WEEKDAY_Msk          (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos)                /*!< RTC_T::WEEKDAY: WEEKDAY Mask           */
+
+#define RTC_TALM_SEC_Pos                 (0)                                               /*!< RTC_T::TALM: SEC Position              */
+#define RTC_TALM_SEC_Msk                 (0xful << RTC_TALM_SEC_Pos)                       /*!< RTC_T::TALM: SEC Mask                  */
+
+#define RTC_TALM_TENSEC_Pos              (4)                                               /*!< RTC_T::TALM: TENSEC Position           */
+#define RTC_TALM_TENSEC_Msk              (0x7ul << RTC_TALM_TENSEC_Pos)                    /*!< RTC_T::TALM: TENSEC Mask               */
+
+#define RTC_TALM_MIN_Pos                 (8)                                               /*!< RTC_T::TALM: MIN Position              */
+#define RTC_TALM_MIN_Msk                 (0xful << RTC_TALM_MIN_Pos)                       /*!< RTC_T::TALM: MIN Mask                  */
+
+#define RTC_TALM_TENMIN_Pos              (12)                                              /*!< RTC_T::TALM: TENMIN Position           */
+#define RTC_TALM_TENMIN_Msk              (0x7ul << RTC_TALM_TENMIN_Pos)                    /*!< RTC_T::TALM: TENMIN Mask               */
+
+#define RTC_TALM_HR_Pos                  (16)                                              /*!< RTC_T::TALM: HR Position               */
+#define RTC_TALM_HR_Msk                  (0xful << RTC_TALM_HR_Pos)                        /*!< RTC_T::TALM: HR Mask                   */
+
+#define RTC_TALM_TENHR_Pos               (20)                                              /*!< RTC_T::TALM: TENHR Position            */
+#define RTC_TALM_TENHR_Msk               (0x3ul << RTC_TALM_TENHR_Pos)                     /*!< RTC_T::TALM: TENHR Mask                */
+
+#define RTC_CALM_DAY_Pos                 (0)                                               /*!< RTC_T::CALM: DAY Position              */
+#define RTC_CALM_DAY_Msk                 (0xful << RTC_CALM_DAY_Pos)                       /*!< RTC_T::CALM: DAY Mask                  */
+
+#define RTC_CALM_TENDAY_Pos              (4)                                               /*!< RTC_T::CALM: TENDAY Position           */
+#define RTC_CALM_TENDAY_Msk              (0x3ul << RTC_CALM_TENDAY_Pos)                    /*!< RTC_T::CALM: TENDAY Mask               */
+
+#define RTC_CALM_MON_Pos                 (8)                                               /*!< RTC_T::CALM: MON Position              */
+#define RTC_CALM_MON_Msk                 (0xful << RTC_CALM_MON_Pos)                       /*!< RTC_T::CALM: MON Mask                  */
+
+#define RTC_CALM_TENMON_Pos              (12)                                              /*!< RTC_T::CALM: TENMON Position           */
+#define RTC_CALM_TENMON_Msk              (0x1ul << RTC_CALM_TENMON_Pos)                    /*!< RTC_T::CALM: TENMON Mask               */
+
+#define RTC_CALM_YEAR_Pos                (16)                                              /*!< RTC_T::CALM: YEAR Position             */
+#define RTC_CALM_YEAR_Msk                (0xful << RTC_CALM_YEAR_Pos)                      /*!< RTC_T::CALM: YEAR Mask                 */
+
+#define RTC_CALM_TENYEAR_Pos             (20)                                              /*!< RTC_T::CALM: TENYEAR Position          */
+#define RTC_CALM_TENYEAR_Msk             (0xful << RTC_CALM_TENYEAR_Pos)                   /*!< RTC_T::CALM: TENYEAR Mask              */
+
+#define RTC_LEAPYEAR_LEAPYEAR_Pos        (0)                                               /*!< RTC_T::LEAPYEAR: LEAPYEAR Position     */
+#define RTC_LEAPYEAR_LEAPYEAR_Msk        (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos)              /*!< RTC_T::LEAPYEAR: LEAPYEAR Mask         */
+
+#define RTC_INTEN_ALMIEN_Pos             (0)                                               /*!< RTC_T::INTEN: ALMIEN Position          */
+#define RTC_INTEN_ALMIEN_Msk             (0x1ul << RTC_INTEN_ALMIEN_Pos)                   /*!< RTC_T::INTEN: ALMIEN Mask              */
+
+#define RTC_INTEN_TICKIEN_Pos            (1)                                               /*!< RTC_T::INTEN: TICKIEN Position         */
+#define RTC_INTEN_TICKIEN_Msk            (0x1ul << RTC_INTEN_TICKIEN_Pos)                  /*!< RTC_T::INTEN: TICKIEN Mask             */
+
+#define RTC_INTEN_TAMP0IEN_Pos           (8)                                               /*!< RTC_T::INTEN: TAMP0IEN Position        */
+#define RTC_INTEN_TAMP0IEN_Msk           (0x1ul << RTC_INTEN_TAMP0IEN_Pos)                 /*!< RTC_T::INTEN: TAMP0IEN Mask            */
+
+#define RTC_INTEN_TAMP1IEN_Pos           (9)                                               /*!< RTC_T::INTEN: TAMP1IEN Position        */
+#define RTC_INTEN_TAMP1IEN_Msk           (0x1ul << RTC_INTEN_TAMP1IEN_Pos)                 /*!< RTC_T::INTEN: TAMP1IEN Mask            */
+
+#define RTC_INTEN_TAMP2IEN_Pos           (10)                                              /*!< RTC_T::INTEN: TAMP2IEN Position        */
+#define RTC_INTEN_TAMP2IEN_Msk           (0x1ul << RTC_INTEN_TAMP2IEN_Pos)                 /*!< RTC_T::INTEN: TAMP2IEN Mask            */
+
+#define RTC_INTEN_TAMP3IEN_Pos           (11)                                              /*!< RTC_T::INTEN: TAMP3IEN Position        */
+#define RTC_INTEN_TAMP3IEN_Msk           (0x1ul << RTC_INTEN_TAMP3IEN_Pos)                 /*!< RTC_T::INTEN: TAMP3IEN Mask            */
+
+#define RTC_INTEN_TAMP4IEN_Pos           (12)                                              /*!< RTC_T::INTEN: TAMP4IEN Position        */
+#define RTC_INTEN_TAMP4IEN_Msk           (0x1ul << RTC_INTEN_TAMP4IEN_Pos)                 /*!< RTC_T::INTEN: TAMP4IEN Mask            */
+
+#define RTC_INTEN_TAMP5IEN_Pos           (13)                                              /*!< RTC_T::INTEN: TAMP5IEN Position        */
+#define RTC_INTEN_TAMP5IEN_Msk           (0x1ul << RTC_INTEN_TAMP5IEN_Pos)                 /*!< RTC_T::INTEN: TAMP5IEN Mask            */
+
+#define RTC_INTEN_CLKFIEN_Pos            (24)                                              /*!< RTC_T::INTEN: CLKFIEN Position         */
+#define RTC_INTEN_CLKFIEN_Msk            (0x1ul << RTC_INTEN_CLKFIEN_Pos)                  /*!< RTC_T::INTEN: CLKFIEN Mask             */
+
+#define RTC_INTEN_CLKSTIEN_Pos           (25)                                              /*!< RTC_T::INTEN: CLKSTIEN Position        */
+#define RTC_INTEN_CLKSTIEN_Msk           (0x1ul << RTC_INTEN_CLKSTIEN_Pos)                 /*!< RTC_T::INTEN: CLKSTIEN Mask            */
+
+#define RTC_INTSTS_ALMIF_Pos             (0)                                               /*!< RTC_T::INTSTS: ALMIF Position          */
+#define RTC_INTSTS_ALMIF_Msk             (0x1ul << RTC_INTSTS_ALMIF_Pos)                   /*!< RTC_T::INTSTS: ALMIF Mask              */
+
+#define RTC_INTSTS_TICKIF_Pos            (1)                                               /*!< RTC_T::INTSTS: TICKIF Position         */
+#define RTC_INTSTS_TICKIF_Msk            (0x1ul << RTC_INTSTS_TICKIF_Pos)                  /*!< RTC_T::INTSTS: TICKIF Mask             */
+
+#define RTC_INTSTS_TAMP0IF_Pos           (8)                                               /*!< RTC_T::INTSTS: TAMP0IF Position        */
+#define RTC_INTSTS_TAMP0IF_Msk           (0x1ul << RTC_INTSTS_TAMP0IF_Pos)                 /*!< RTC_T::INTSTS: TAMP0IF Mask            */
+
+#define RTC_INTSTS_TAMP1IF_Pos           (9)                                               /*!< RTC_T::INTSTS: TAMP1IF Position        */
+#define RTC_INTSTS_TAMP1IF_Msk           (0x1ul << RTC_INTSTS_TAMP1IF_Pos)                 /*!< RTC_T::INTSTS: TAMP1IF Mask            */
+
+#define RTC_INTSTS_TAMP2IF_Pos           (10)                                              /*!< RTC_T::INTSTS: TAMP2IF Position        */
+#define RTC_INTSTS_TAMP2IF_Msk           (0x1ul << RTC_INTSTS_TAMP2IF_Pos)                 /*!< RTC_T::INTSTS: TAMP2IF Mask            */
+
+#define RTC_INTSTS_TAMP3IF_Pos           (11)                                              /*!< RTC_T::INTSTS: TAMP3IF Position        */
+#define RTC_INTSTS_TAMP3IF_Msk           (0x1ul << RTC_INTSTS_TAMP3IF_Pos)                 /*!< RTC_T::INTSTS: TAMP3IF Mask            */
+
+#define RTC_INTSTS_TAMP4IF_Pos           (12)                                              /*!< RTC_T::INTSTS: TAMP4IF Position        */
+#define RTC_INTSTS_TAMP4IF_Msk           (0x1ul << RTC_INTSTS_TAMP4IF_Pos)                 /*!< RTC_T::INTSTS: TAMP4IF Mask            */
+
+#define RTC_INTSTS_TAMP5IF_Pos           (13)                                              /*!< RTC_T::INTSTS: TAMP5IF Position        */
+#define RTC_INTSTS_TAMP5IF_Msk           (0x1ul << RTC_INTSTS_TAMP5IF_Pos)                 /*!< RTC_T::INTSTS: TAMP5IF Mask            */
+
+#define RTC_INTSTS_CLKFIF_Pos            (24)                                              /*!< RTC_T::INTSTS: CLKFIF Position         */
+#define RTC_INTSTS_CLKFIF_Msk            (0x1ul << RTC_INTSTS_CLKFIF_Pos)                  /*!< RTC_T::INTSTS: CLKFIF Mask             */
+
+#define RTC_INTSTS_CLKSTIF_Pos           (25)                                              /*!< RTC_T::INTSTS: CLKSTIF Position        */
+#define RTC_INTSTS_CLKSTIF_Msk           (0x1ul << RTC_INTSTS_CLKSTIF_Pos)                 /*!< RTC_T::INTSTS: CLKSTIF Mask            */
+
+#define RTC_TICK_TICK_Pos                (0)                                               /*!< RTC_T::TICK: TICK Position             */
+#define RTC_TICK_TICK_Msk                (0x7ul << RTC_TICK_TICK_Pos)                      /*!< RTC_T::TICK: TICK Mask                 */
+
+#define RTC_TAMSK_MSEC_Pos               (0)                                               /*!< RTC_T::TAMSK: MSEC Position            */
+#define RTC_TAMSK_MSEC_Msk               (0x1ul << RTC_TAMSK_MSEC_Pos)                     /*!< RTC_T::TAMSK: MSEC Mask                */
+
+#define RTC_TAMSK_MTENSEC_Pos            (1)                                               /*!< RTC_T::TAMSK: MTENSEC Position         */
+#define RTC_TAMSK_MTENSEC_Msk            (0x1ul << RTC_TAMSK_MTENSEC_Pos)                  /*!< RTC_T::TAMSK: MTENSEC Mask             */
+
+#define RTC_TAMSK_MMIN_Pos               (2)                                               /*!< RTC_T::TAMSK: MMIN Position            */
+#define RTC_TAMSK_MMIN_Msk               (0x1ul << RTC_TAMSK_MMIN_Pos)                     /*!< RTC_T::TAMSK: MMIN Mask                */
+
+#define RTC_TAMSK_MTENMIN_Pos            (3)                                               /*!< RTC_T::TAMSK: MTENMIN Position         */
+#define RTC_TAMSK_MTENMIN_Msk            (0x1ul << RTC_TAMSK_MTENMIN_Pos)                  /*!< RTC_T::TAMSK: MTENMIN Mask             */
+
+#define RTC_TAMSK_MHR_Pos                (4)                                               /*!< RTC_T::TAMSK: MHR Position             */
+#define RTC_TAMSK_MHR_Msk                (0x1ul << RTC_TAMSK_MHR_Pos)                      /*!< RTC_T::TAMSK: MHR Mask                 */
+
+#define RTC_TAMSK_MTENHR_Pos             (5)                                               /*!< RTC_T::TAMSK: MTENHR Position          */
+#define RTC_TAMSK_MTENHR_Msk             (0x1ul << RTC_TAMSK_MTENHR_Pos)                   /*!< RTC_T::TAMSK: MTENHR Mask              */
+
+#define RTC_CAMSK_MDAY_Pos               (0)                                               /*!< RTC_T::CAMSK: MDAY Position            */
+#define RTC_CAMSK_MDAY_Msk               (0x1ul << RTC_CAMSK_MDAY_Pos)                     /*!< RTC_T::CAMSK: MDAY Mask                */
+
+#define RTC_CAMSK_MTENDAY_Pos            (1)                                               /*!< RTC_T::CAMSK: MTENDAY Position         */
+#define RTC_CAMSK_MTENDAY_Msk            (0x1ul << RTC_CAMSK_MTENDAY_Pos)                  /*!< RTC_T::CAMSK: MTENDAY Mask             */
+
+#define RTC_CAMSK_MMON_Pos               (2)                                               /*!< RTC_T::CAMSK: MMON Position            */
+#define RTC_CAMSK_MMON_Msk               (0x1ul << RTC_CAMSK_MMON_Pos)                     /*!< RTC_T::CAMSK: MMON Mask                */
+
+#define RTC_CAMSK_MTENMON_Pos            (3)                                               /*!< RTC_T::CAMSK: MTENMON Position         */
+#define RTC_CAMSK_MTENMON_Msk            (0x1ul << RTC_CAMSK_MTENMON_Pos)                  /*!< RTC_T::CAMSK: MTENMON Mask             */
+
+#define RTC_CAMSK_MYEAR_Pos              (4)                                               /*!< RTC_T::CAMSK: MYEAR Position           */
+#define RTC_CAMSK_MYEAR_Msk              (0x1ul << RTC_CAMSK_MYEAR_Pos)                    /*!< RTC_T::CAMSK: MYEAR Mask               */
+
+#define RTC_CAMSK_MTENYEAR_Pos           (5)                                               /*!< RTC_T::CAMSK: MTENYEAR Position        */
+#define RTC_CAMSK_MTENYEAR_Msk           (0x1ul << RTC_CAMSK_MTENYEAR_Pos)                 /*!< RTC_T::CAMSK: MTENYEAR Mask            */
+
+#define RTC_SPRCTL_SPRRWEN_Pos           (2)                                               /*!< RTC_T::SPRCTL: SPRRWEN Position        */
+#define RTC_SPRCTL_SPRRWEN_Msk           (0x1ul << RTC_SPRCTL_SPRRWEN_Pos)                 /*!< RTC_T::SPRCTL: SPRRWEN Mask            */
+
+#define RTC_SPRCTL_SPRCSTS_Pos           (5)                                               /*!< RTC_T::SPRCTL: SPRCSTS Position        */
+#define RTC_SPRCTL_SPRCSTS_Msk           (0x1ul << RTC_SPRCTL_SPRCSTS_Pos)                 /*!< RTC_T::SPRCTL: SPRCSTS Mask            */
+
+#define RTC_SPRCTL_LXTFCLR_Pos           (16)                                              /*!< RTC_T::SPRCTL: LXTFCLR Position        */
+#define RTC_SPRCTL_LXTFCLR_Msk           (0x1ul << RTC_SPRCTL_LXTFCLR_Pos)                 /*!< RTC_T::SPRCTL: LXTFCLR Mask            */
+
+#define RTC_SPR0_SPARE_Pos               (0)                                               /*!< RTC_T::SPR0: SPARE Position            */
+#define RTC_SPR0_SPARE_Msk               (0xfffffffful << RTC_SPR0_SPARE_Pos)              /*!< RTC_T::SPR0: SPARE Mask                */
+
+#define RTC_SPR1_SPARE_Pos               (0)                                               /*!< RTC_T::SPR1: SPARE Position            */
+#define RTC_SPR1_SPARE_Msk               (0xfffffffful << RTC_SPR1_SPARE_Pos)              /*!< RTC_T::SPR1: SPARE Mask                */
+
+#define RTC_SPR2_SPARE_Pos               (0)                                               /*!< RTC_T::SPR2: SPARE Position            */
+#define RTC_SPR2_SPARE_Msk               (0xfffffffful << RTC_SPR2_SPARE_Pos)              /*!< RTC_T::SPR2: SPARE Mask                */
+
+#define RTC_SPR3_SPARE_Pos               (0)                                               /*!< RTC_T::SPR3: SPARE Position            */
+#define RTC_SPR3_SPARE_Msk               (0xfffffffful << RTC_SPR3_SPARE_Pos)              /*!< RTC_T::SPR3: SPARE Mask                */
+
+#define RTC_SPR4_SPARE_Pos               (0)                                               /*!< RTC_T::SPR4: SPARE Position            */
+#define RTC_SPR4_SPARE_Msk               (0xfffffffful << RTC_SPR4_SPARE_Pos)              /*!< RTC_T::SPR4: SPARE Mask                */
+
+#define RTC_SPR5_SPARE_Pos               (0)                                               /*!< RTC_T::SPR5: SPARE Position            */
+#define RTC_SPR5_SPARE_Msk               (0xfffffffful << RTC_SPR5_SPARE_Pos)              /*!< RTC_T::SPR5: SPARE Mask                */
+
+#define RTC_SPR6_SPARE_Pos               (0)                                               /*!< RTC_T::SPR6: SPARE Position            */
+#define RTC_SPR6_SPARE_Msk               (0xfffffffful << RTC_SPR6_SPARE_Pos)              /*!< RTC_T::SPR6: SPARE Mask                */
+
+#define RTC_SPR7_SPARE_Pos               (0)                                               /*!< RTC_T::SPR7: SPARE Position            */
+#define RTC_SPR7_SPARE_Msk               (0xfffffffful << RTC_SPR7_SPARE_Pos)              /*!< RTC_T::SPR7: SPARE Mask                */
+
+#define RTC_SPR8_SPARE_Pos               (0)                                               /*!< RTC_T::SPR8: SPARE Position            */
+#define RTC_SPR8_SPARE_Msk               (0xfffffffful << RTC_SPR8_SPARE_Pos)              /*!< RTC_T::SPR8: SPARE Mask                */
+
+#define RTC_SPR9_SPARE_Pos               (0)                                               /*!< RTC_T::SPR9: SPARE Position            */
+#define RTC_SPR9_SPARE_Msk               (0xfffffffful << RTC_SPR9_SPARE_Pos)              /*!< RTC_T::SPR9: SPARE Mask                */
+
+#define RTC_SPR10_SPARE_Pos              (0)                                               /*!< RTC_T::SPR10: SPARE Position           */
+#define RTC_SPR10_SPARE_Msk              (0xfffffffful << RTC_SPR10_SPARE_Pos)             /*!< RTC_T::SPR10: SPARE Mask               */
+
+#define RTC_SPR11_SPARE_Pos              (0)                                               /*!< RTC_T::SPR11: SPARE Position           */
+#define RTC_SPR11_SPARE_Msk              (0xfffffffful << RTC_SPR11_SPARE_Pos)             /*!< RTC_T::SPR11: SPARE Mask               */
+
+#define RTC_SPR12_SPARE_Pos              (0)                                               /*!< RTC_T::SPR12: SPARE Position           */
+#define RTC_SPR12_SPARE_Msk              (0xfffffffful << RTC_SPR12_SPARE_Pos)             /*!< RTC_T::SPR12: SPARE Mask               */
+
+#define RTC_SPR13_SPARE_Pos              (0)                                               /*!< RTC_T::SPR13: SPARE Position           */
+#define RTC_SPR13_SPARE_Msk              (0xfffffffful << RTC_SPR13_SPARE_Pos)             /*!< RTC_T::SPR13: SPARE Mask               */
+
+#define RTC_SPR14_SPARE_Pos              (0)                                               /*!< RTC_T::SPR14: SPARE Position           */
+#define RTC_SPR14_SPARE_Msk              (0xfffffffful << RTC_SPR14_SPARE_Pos)             /*!< RTC_T::SPR14: SPARE Mask               */
+
+#define RTC_SPR15_SPARE_Pos              (0)                                               /*!< RTC_T::SPR15: SPARE Position           */
+#define RTC_SPR15_SPARE_Msk              (0xfffffffful << RTC_SPR15_SPARE_Pos)             /*!< RTC_T::SPR15: SPARE Mask               */
+
+#define RTC_SPR16_SPARE_Pos              (0)                                               /*!< RTC_T::SPR16: SPARE Position           */
+#define RTC_SPR16_SPARE_Msk              (0xfffffffful << RTC_SPR16_SPARE_Pos)             /*!< RTC_T::SPR16: SPARE Mask               */
+
+#define RTC_SPR17_SPARE_Pos              (0)                                               /*!< RTC_T::SPR17: SPARE Position           */
+#define RTC_SPR17_SPARE_Msk              (0xfffffffful << RTC_SPR17_SPARE_Pos)             /*!< RTC_T::SPR17: SPARE Mask               */
+
+#define RTC_SPR18_SPARE_Pos              (0)                                               /*!< RTC_T::SPR18: SPARE Position           */
+#define RTC_SPR18_SPARE_Msk              (0xfffffffful << RTC_SPR18_SPARE_Pos)             /*!< RTC_T::SPR18: SPARE Mask               */
+
+#define RTC_SPR19_SPARE_Pos              (0)                                               /*!< RTC_T::SPR19: SPARE Position           */
+#define RTC_SPR19_SPARE_Msk              (0xfffffffful << RTC_SPR19_SPARE_Pos)             /*!< RTC_T::SPR19: SPARE Mask               */
+
+#define RTC_LXTCTL_LIRC32KEN_Pos         (0)                                               /*!< RTC_T::LXTCTL: LIRC32KEN Position      */
+#define RTC_LXTCTL_LIRC32KEN_Msk         (0x1ul << RTC_LXTCTL_LIRC32KEN_Pos)               /*!< RTC_T::LXTCTL: LIRC32KEN Mask          */
+
+#define RTC_LXTCTL_GAIN_Pos              (1)                                               /*!< RTC_T::LXTCTL: GAIN Position           */
+#define RTC_LXTCTL_GAIN_Msk              (0x7ul << RTC_LXTCTL_GAIN_Pos)                    /*!< RTC_T::LXTCTL: GAIN Mask               */
+
+#define RTC_LXTCTL_C32KSEL_Pos           (6)                                               /*!< RTC_T::LXTCTL: C32KSEL Position        */
+#define RTC_LXTCTL_C32KSEL_Msk           (0x1ul << RTC_LXTCTL_C32KSEL_Pos)                 /*!< RTC_T::LXTCTL: C32KSEL Mask            */
+
+#define RTC_LXTCTL_RTCCKSEL_Pos          (7)                                               /*!< RTC_T::LXTCTL: RTCCKSEL Position       */
+#define RTC_LXTCTL_RTCCKSEL_Msk          (0x1ul << RTC_LXTCTL_RTCCKSEL_Pos)                /*!< RTC_T::LXTCTL: RTCCKSEL Mask           */
+
+#define RTC_LXTCTL_IOCTLSEL_Pos          (8)                                               /*!< RTC_T::LXTCTL: IOCTLSEL Position       */
+#define RTC_LXTCTL_IOCTLSEL_Msk          (0x1ul << RTC_LXTCTL_IOCTLSEL_Pos)                /*!< RTC_T::LXTCTL: IOCTLSEL Mask           */
+
+#define RTC_GPIOCTL0_OPMODE0_Pos         (0)                                               /*!< RTC_T::GPIOCTL0: OPMODE0 Position      */
+#define RTC_GPIOCTL0_OPMODE0_Msk         (0x3ul << RTC_GPIOCTL0_OPMODE0_Pos)               /*!< RTC_T::GPIOCTL0: OPMODE0 Mask          */
+
+#define RTC_GPIOCTL0_DOUT0_Pos           (2)                                               /*!< RTC_T::GPIOCTL0: DOUT0 Position        */
+#define RTC_GPIOCTL0_DOUT0_Msk           (0x1ul << RTC_GPIOCTL0_DOUT0_Pos)                 /*!< RTC_T::GPIOCTL0: DOUT0 Mask            */
+
+#define RTC_GPIOCTL0_DINOFF0_Pos         (3)                                               /*!< RTC_T::GPIOCTL0: DINOFF0 Position      */
+#define RTC_GPIOCTL0_DINOFF0_Msk         (0x1ul << RTC_GPIOCTL0_DINOFF0_Pos)               /*!< RTC_T::GPIOCTL0: DINOFF0 Mask          */
+
+#define RTC_GPIOCTL0_PUSEL0_Pos          (4)                                               /*!< RTC_T::GPIOCTL0: PUSEL0 Position       */
+#define RTC_GPIOCTL0_PUSEL0_Msk          (0x3ul << RTC_GPIOCTL0_PUSEL0_Pos)                /*!< RTC_T::GPIOCTL0: PUSEL0 Mask           */
+
+#define RTC_GPIOCTL0_OPMODE1_Pos         (8)                                               /*!< RTC_T::GPIOCTL0: OPMODE1 Position      */
+#define RTC_GPIOCTL0_OPMODE1_Msk         (0x3ul << RTC_GPIOCTL0_OPMODE1_Pos)               /*!< RTC_T::GPIOCTL0: OPMODE1 Mask          */
+
+#define RTC_GPIOCTL0_DOUT1_Pos           (10)                                              /*!< RTC_T::GPIOCTL0: DOUT1 Position        */
+#define RTC_GPIOCTL0_DOUT1_Msk           (0x1ul << RTC_GPIOCTL0_DOUT1_Pos)                 /*!< RTC_T::GPIOCTL0: DOUT1 Mask            */
+
+#define RTC_GPIOCTL0_DINOFF1_Pos         (11)                                              /*!< RTC_T::GPIOCTL0: DINOFF1 Position      */
+#define RTC_GPIOCTL0_DINOFF1_Msk         (0x1ul << RTC_GPIOCTL0_DINOFF1_Pos)               /*!< RTC_T::GPIOCTL0: DINOFF1 Mask          */
+
+#define RTC_GPIOCTL0_PUSEL1_Pos          (12)                                              /*!< RTC_T::GPIOCTL0: PUSEL1 Position       */
+#define RTC_GPIOCTL0_PUSEL1_Msk          (0x3ul << RTC_GPIOCTL0_PUSEL1_Pos)                /*!< RTC_T::GPIOCTL0: PUSEL1 Mask           */
+
+#define RTC_GPIOCTL0_OPMODE2_Pos         (16)                                              /*!< RTC_T::GPIOCTL0: OPMODE2 Position      */
+#define RTC_GPIOCTL0_OPMODE2_Msk         (0x3ul << RTC_GPIOCTL0_OPMODE2_Pos)               /*!< RTC_T::GPIOCTL0: OPMODE2 Mask          */
+
+#define RTC_GPIOCTL0_DOUT2_Pos           (18)                                              /*!< RTC_T::GPIOCTL0: DOUT2 Position        */
+#define RTC_GPIOCTL0_DOUT2_Msk           (0x1ul << RTC_GPIOCTL0_DOUT2_Pos)                 /*!< RTC_T::GPIOCTL0: DOUT2 Mask            */
+
+#define RTC_GPIOCTL0_DINOFF2_Pos         (19)                                              /*!< RTC_T::GPIOCTL0: DINOFF2 Position      */
+#define RTC_GPIOCTL0_DINOFF2_Msk         (0x1ul << RTC_GPIOCTL0_DINOFF2_Pos)               /*!< RTC_T::GPIOCTL0: DINOFF2 Mask          */
+
+#define RTC_GPIOCTL0_PUSEL2_Pos          (20)                                              /*!< RTC_T::GPIOCTL0: PUSEL2 Position       */
+#define RTC_GPIOCTL0_PUSEL2_Msk          (0x3ul << RTC_GPIOCTL0_PUSEL2_Pos)                /*!< RTC_T::GPIOCTL0: PUSEL2 Mask           */
+
+#define RTC_GPIOCTL0_OPMODE3_Pos         (24)                                              /*!< RTC_T::GPIOCTL0: OPMODE3 Position      */
+#define RTC_GPIOCTL0_OPMODE3_Msk         (0x3ul << RTC_GPIOCTL0_OPMODE3_Pos)               /*!< RTC_T::GPIOCTL0: OPMODE3 Mask          */
+
+#define RTC_GPIOCTL0_DOUT3_Pos           (26)                                              /*!< RTC_T::GPIOCTL0: DOUT3 Position        */
+#define RTC_GPIOCTL0_DOUT3_Msk           (0x1ul << RTC_GPIOCTL0_DOUT3_Pos)                 /*!< RTC_T::GPIOCTL0: DOUT3 Mask            */
+
+#define RTC_GPIOCTL0_DINOFF3_Pos         (27)                                              /*!< RTC_T::GPIOCTL0: DINOFF3 Position      */
+#define RTC_GPIOCTL0_DINOFF3_Msk         (0x1ul << RTC_GPIOCTL0_DINOFF3_Pos)               /*!< RTC_T::GPIOCTL0: DINOFF3 Mask          */
+
+#define RTC_GPIOCTL0_PUSEL3_Pos          (28)                                              /*!< RTC_T::GPIOCTL0: PUSEL3 Position       */
+#define RTC_GPIOCTL0_PUSEL3_Msk          (0x3ul << RTC_GPIOCTL0_PUSEL3_Pos)                /*!< RTC_T::GPIOCTL0: PUSEL3 Mask           */
+
+#define RTC_GPIOCTL1_OPMODE4_Pos         (0)                                               /*!< RTC_T::GPIOCTL1: OPMODE4 Position      */
+#define RTC_GPIOCTL1_OPMODE4_Msk         (0x3ul << RTC_GPIOCTL1_OPMODE4_Pos)               /*!< RTC_T::GPIOCTL1: OPMODE4 Mask          */
+
+#define RTC_GPIOCTL1_DOUT4_Pos           (2)                                               /*!< RTC_T::GPIOCTL1: DOUT4 Position        */
+#define RTC_GPIOCTL1_DOUT4_Msk           (0x1ul << RTC_GPIOCTL1_DOUT4_Pos)                 /*!< RTC_T::GPIOCTL1: DOUT4 Mask            */
+
+#define RTC_GPIOCTL0_DINOFF4_Pos         (3)                                               /*!< RTC_T::GPIOCTL1: DINOFF4 Position      */
+#define RTC_GPIOCTL0_DINOFF4_Msk         (0x1ul << RTC_GPIOCTL0_DINOFF4_Pos)               /*!< RTC_T::GPIOCTL1: DINOFF4 Mask          */
+
+#define RTC_GPIOCTL1_PUSEL4_Pos          (4)                                               /*!< RTC_T::GPIOCTL1: PUSEL4 Position       */
+#define RTC_GPIOCTL1_PUSEL4_Msk          (0x3ul << RTC_GPIOCTL1_PUSEL4_Pos)                /*!< RTC_T::GPIOCTL1: PUSEL4 Mask           */
+
+#define RTC_GPIOCTL1_OPMODE5_Pos         (8)                                               /*!< RTC_T::GPIOCTL1: OPMODE5 Position      */
+#define RTC_GPIOCTL1_OPMODE5_Msk         (0x3ul << RTC_GPIOCTL1_OPMODE5_Pos)               /*!< RTC_T::GPIOCTL1: OPMODE5 Mask          */
+
+#define RTC_GPIOCTL1_DOUT5_Pos           (10)                                              /*!< RTC_T::GPIOCTL1: DOUT5 Position        */
+#define RTC_GPIOCTL1_DOUT5_Msk           (0x1ul << RTC_GPIOCTL1_DOUT5_Pos)                 /*!< RTC_T::GPIOCTL1: DOUT5 Mask            */
+
+#define RTC_GPIOCTL0_DINOFF5_Pos         (11)                                              /*!< RTC_T::GPIOCTL1: DINOFF5 Position      */
+#define RTC_GPIOCTL0_DINOFF5_Msk         (0x1ul << RTC_GPIOCTL0_DINOFF5_Pos)               /*!< RTC_T::GPIOCTL1: DINOFF5 Mask          */
+
+#define RTC_GPIOCTL1_PUSEL5_Pos          (12)                                              /*!< RTC_T::GPIOCTL1: PUSEL5 Position       */
+#define RTC_GPIOCTL1_PUSEL5_Msk          (0x3ul << RTC_GPIOCTL1_PUSEL5_Pos)                /*!< RTC_T::GPIOCTL1: PUSEL5 Mask           */
+
+#define RTC_GPIOCTL1_OPMODE6_Pos         (16)                                              /*!< RTC_T::GPIOCTL1: OPMODE6 Position      */
+#define RTC_GPIOCTL1_OPMODE6_Msk         (0x3ul << RTC_GPIOCTL1_OPMODE6_Pos)               /*!< RTC_T::GPIOCTL1: OPMODE6 Mask          */
+
+#define RTC_GPIOCTL1_DOUT6_Pos           (18)                                              /*!< RTC_T::GPIOCTL1: DOUT6 Position        */
+#define RTC_GPIOCTL1_DOUT6_Msk           (0x1ul << RTC_GPIOCTL1_DOUT6_Pos)                 /*!< RTC_T::GPIOCTL1: DOUT6 Mask            */
+
+#define RTC_GPIOCTL0_DINOFF6_Pos         (19)                                              /*!< RTC_T::GPIOCTL1: DINOFF6 Position      */
+#define RTC_GPIOCTL0_DINOFF6_Msk         (0x1ul << RTC_GPIOCTL0_DINOFF6_Pos)               /*!< RTC_T::GPIOCTL1: DINOFF6 Mask          */
+
+#define RTC_GPIOCTL1_PUSEL6_Pos          (20)                                              /*!< RTC_T::GPIOCTL1: PUSEL6 Position       */
+#define RTC_GPIOCTL1_PUSEL6_Msk          (0x3ul << RTC_GPIOCTL1_PUSEL6_Pos)                /*!< RTC_T::GPIOCTL1: PUSEL6 Mask           */
+
+#define RTC_GPIOCTL1_OPMODE7_Pos         (24)                                              /*!< RTC_T::GPIOCTL1: OPMODE7 Position      */
+#define RTC_GPIOCTL1_OPMODE7_Msk         (0x3ul << RTC_GPIOCTL1_OPMODE7_Pos)               /*!< RTC_T::GPIOCTL1: OPMODE7 Mask          */
+
+#define RTC_GPIOCTL1_DOUT7_Pos           (26)                                              /*!< RTC_T::GPIOCTL1: DOUT7 Position        */
+#define RTC_GPIOCTL1_DOUT7_Msk           (0x1ul << RTC_GPIOCTL1_DOUT7_Pos)                 /*!< RTC_T::GPIOCTL1: DOUT7 Mask            */
+
+#define RTC_GPIOCTL0_DINOFF7_Pos         (27)                                              /*!< RTC_T::GPIOCTL1: DINOFF7 Position      */
+#define RTC_GPIOCTL0_DINOFF7_Msk         (0x1ul << RTC_GPIOCTL0_DINOFF7_Pos)               /*!< RTC_T::GPIOCTL1: DINOFF7 Mask          */
+
+#define RTC_GPIOCTL1_PUSEL7_Pos          (28)                                              /*!< RTC_T::GPIOCTL1: PUSEL7 Position       */
+#define RTC_GPIOCTL1_PUSEL7_Msk          (0x3ul << RTC_GPIOCTL1_PUSEL7_Pos)                /*!< RTC_T::GPIOCTL1: PUSEL7 Mask           */
+
+#define RTC_DSTCTL_ADDHR_Pos             (0)                                               /*!< RTC_T::DSTCTL: ADDHR Position          */
+#define RTC_DSTCTL_ADDHR_Msk             (0x1ul << RTC_DSTCTL_ADDHR_Pos)                   /*!< RTC_T::DSTCTL: ADDHR Mask              */
+
+#define RTC_DSTCTL_SUBHR_Pos             (1)                                               /*!< RTC_T::DSTCTL: SUBHR Position          */
+#define RTC_DSTCTL_SUBHR_Msk             (0x1ul << RTC_DSTCTL_SUBHR_Pos)                   /*!< RTC_T::DSTCTL: SUBHR Mask              */
+
+#define RTC_DSTCTL_DSBAK_Pos             (2)                                               /*!< RTC_T::DSTCTL: DSBAK Position          */
+#define RTC_DSTCTL_DSBAK_Msk             (0x1ul << RTC_DSTCTL_DSBAK_Pos)                   /*!< RTC_T::DSTCTL: DSBAK Mask              */
+
+#define RTC_TAMPCTL_DYN1ISS_Pos          (0)                                               /*!< RTC_T::TAMPCTL: DYN1ISS Position       */
+#define RTC_TAMPCTL_DYN1ISS_Msk          (0x1ul << RTC_TAMPCTL_DYN1ISS_Pos)                /*!< RTC_T::TAMPCTL: DYN1ISS Mask           */
+
+#define RTC_TAMPCTL_DYN2ISS_Pos          (1)                                               /*!< RTC_T::TAMPCTL: DYN2ISS Position       */
+#define RTC_TAMPCTL_DYN2ISS_Msk          (0x1ul << RTC_TAMPCTL_DYN2ISS_Pos)                /*!< RTC_T::TAMPCTL: DYN2ISS Mask           */
+
+#define RTC_TAMPCTL_DYNSRC_Pos           (3)                                               /*!< RTC_T::TAMPCTL: DYNSRC Position        */
+#define RTC_TAMPCTL_DYNSRC_Msk           (0x1ul << RTC_TAMPCTL_DYNSRC_Pos)                 /*!< RTC_T::TAMPCTL: DYNSRC Mask            */
+
+#define RTC_TAMPCTL_SEEDRLD_Pos          (4)                                               /*!< RTC_T::TAMPCTL: SEEDRLD Position       */
+#define RTC_TAMPCTL_SEEDRLD_Msk          (0x1ul << RTC_TAMPCTL_SEEDRLD_Pos)                /*!< RTC_T::TAMPCTL: SEEDRLD Mask           */
+
+#define RTC_TAMPCTL_DYNRATE_Pos          (5)                                               /*!< RTC_T::TAMPCTL: DYNRATE Position       */
+#define RTC_TAMPCTL_DYNRATE_Msk          (0x7ul << RTC_TAMPCTL_DYNRATE_Pos)                /*!< RTC_T::TAMPCTL: DYNRATE Mask           */
+
+#define RTC_TAMPCTL_TAMP0EN_Pos          (8)                                               /*!< RTC_T::TAMPCTL: TAMP0EN Position       */
+#define RTC_TAMPCTL_TAMP0EN_Msk          (0x1ul << RTC_TAMPCTL_TAMP0EN_Pos)                /*!< RTC_T::TAMPCTL: TAMP0EN Mask           */
+
+#define RTC_TAMPCTL_TAMP0LV_Pos          (9)                                               /*!< RTC_T::TAMPCTL: TAMP0LV Position       */
+#define RTC_TAMPCTL_TAMP0LV_Msk          (0x1ul << RTC_TAMPCTL_TAMP0LV_Pos)                /*!< RTC_T::TAMPCTL: TAMP0LV Mask           */
+
+#define RTC_TAMPCTL_TAMP0DBEN_Pos        (10)                                              /*!< RTC_T::TAMPCTL: TAMP0DBEN Position     */
+#define RTC_TAMPCTL_TAMP0DBEN_Msk        (0x1ul << RTC_TAMPCTL_TAMP0DBEN_Pos)              /*!< RTC_T::TAMPCTL: TAMP0DBEN Mask         */
+
+#define RTC_TAMPCTL_TAMP1EN_Pos          (12)                                              /*!< RTC_T::TAMPCTL: TAMP1EN Position       */
+#define RTC_TAMPCTL_TAMP1EN_Msk          (0x1ul << RTC_TAMPCTL_TAMP1EN_Pos)                /*!< RTC_T::TAMPCTL: TAMP1EN Mask           */
+
+#define RTC_TAMPCTL_TAMP1LV_Pos          (13)                                              /*!< RTC_T::TAMPCTL: TAMP1LV Position       */
+#define RTC_TAMPCTL_TAMP1LV_Msk          (0x1ul << RTC_TAMPCTL_TAMP1LV_Pos)                /*!< RTC_T::TAMPCTL: TAMP1LV Mask           */
+
+#define RTC_TAMPCTL_TAMP1DBEN_Pos        (14)                                              /*!< RTC_T::TAMPCTL: TAMP1DBEN Position     */
+#define RTC_TAMPCTL_TAMP1DBEN_Msk        (0x1ul << RTC_TAMPCTL_TAMP1DBEN_Pos)              /*!< RTC_T::TAMPCTL: TAMP1DBEN Mask         */
+
+#define RTC_TAMPCTL_DYNPR0EN_Pos         (15)                                              /*!< RTC_T::TAMPCTL: DYNPR0EN Position      */
+#define RTC_TAMPCTL_DYNPR0EN_Msk         (0x1ul << RTC_TAMPCTL_DYNPR0EN_Pos)               /*!< RTC_T::TAMPCTL: DYNPR0EN Mask          */
+
+#define RTC_TAMPCTL_TAMP2EN_Pos          (16)                                              /*!< RTC_T::TAMPCTL: TAMP2EN Position       */
+#define RTC_TAMPCTL_TAMP2EN_Msk          (0x1ul << RTC_TAMPCTL_TAMP2EN_Pos)                /*!< RTC_T::TAMPCTL: TAMP2EN Mask           */
+
+#define RTC_TAMPCTL_TAMP2LV_Pos          (17)                                              /*!< RTC_T::TAMPCTL: TAMP2LV Position       */
+#define RTC_TAMPCTL_TAMP2LV_Msk          (0x1ul << RTC_TAMPCTL_TAMP2LV_Pos)                /*!< RTC_T::TAMPCTL: TAMP2LV Mask           */
+
+#define RTC_TAMPCTL_TAMP2DBEN_Pos        (18)                                              /*!< RTC_T::TAMPCTL: TAMP2DBEN Position     */
+#define RTC_TAMPCTL_TAMP2DBEN_Msk        (0x1ul << RTC_TAMPCTL_TAMP2DBEN_Pos)              /*!< RTC_T::TAMPCTL: TAMP2DBEN Mask         */
+
+#define RTC_TAMPCTL_TAMP3EN_Pos          (20)                                              /*!< RTC_T::TAMPCTL: TAMP3EN Position       */
+#define RTC_TAMPCTL_TAMP3EN_Msk          (0x1ul << RTC_TAMPCTL_TAMP3EN_Pos)                /*!< RTC_T::TAMPCTL: TAMP3EN Mask           */
+
+#define RTC_TAMPCTL_TAMP3LV_Pos          (21)                                              /*!< RTC_T::TAMPCTL: TAMP3LV Position       */
+#define RTC_TAMPCTL_TAMP3LV_Msk          (0x1ul << RTC_TAMPCTL_TAMP3LV_Pos)                /*!< RTC_T::TAMPCTL: TAMP3LV Mask           */
+
+#define RTC_TAMPCTL_TAMP3DBEN_Pos        (22)                                              /*!< RTC_T::TAMPCTL: TAMP3DBEN Position     */
+#define RTC_TAMPCTL_TAMP3DBEN_Msk        (0x1ul << RTC_TAMPCTL_TAMP3DBEN_Pos)              /*!< RTC_T::TAMPCTL: TAMP3DBEN Mask         */
+
+#define RTC_TAMPCTL_DYNPR1EN_Pos         (23)                                              /*!< RTC_T::TAMPCTL: DYNPR1EN Position      */
+#define RTC_TAMPCTL_DYNPR1EN_Msk         (0x1ul << RTC_TAMPCTL_DYNPR1EN_Pos)               /*!< RTC_T::TAMPCTL: DYNPR1EN Mask          */
+
+#define RTC_TAMPCTL_TAMP4EN_Pos          (24)                                              /*!< RTC_T::TAMPCTL: TAMP4EN Position       */
+#define RTC_TAMPCTL_TAMP4EN_Msk          (0x1ul << RTC_TAMPCTL_TAMP4EN_Pos)                /*!< RTC_T::TAMPCTL: TAMP4EN Mask           */
+
+#define RTC_TAMPCTL_TAMP4LV_Pos          (25)                                              /*!< RTC_T::TAMPCTL: TAMP4LV Position       */
+#define RTC_TAMPCTL_TAMP4LV_Msk          (0x1ul << RTC_TAMPCTL_TAMP4LV_Pos)                /*!< RTC_T::TAMPCTL: TAMP4LV Mask           */
+
+#define RTC_TAMPCTL_TAMP4DBEN_Pos        (26)                                              /*!< RTC_T::TAMPCTL: TAMP4DBEN Position     */
+#define RTC_TAMPCTL_TAMP4DBEN_Msk        (0x1ul << RTC_TAMPCTL_TAMP4DBEN_Pos)              /*!< RTC_T::TAMPCTL: TAMP4DBEN Mask         */
+
+#define RTC_TAMPCTL_TAMP5EN_Pos          (28)                                              /*!< RTC_T::TAMPCTL: TAMP5EN Position       */
+#define RTC_TAMPCTL_TAMP5EN_Msk          (0x1ul << RTC_TAMPCTL_TAMP5EN_Pos)                /*!< RTC_T::TAMPCTL: TAMP5EN Mask           */
+
+#define RTC_TAMPCTL_TAMP5LV_Pos          (29)                                              /*!< RTC_T::TAMPCTL: TAMP5LV Position       */
+#define RTC_TAMPCTL_TAMP5LV_Msk          (0x1ul << RTC_TAMPCTL_TAMP5LV_Pos)                /*!< RTC_T::TAMPCTL: TAMP5LV Mask           */
+
+#define RTC_TAMPCTL_TAMP5DBEN_Pos        (30)                                              /*!< RTC_T::TAMPCTL: TAMP5DBEN Position     */
+#define RTC_TAMPCTL_TAMP5DBEN_Msk        (0x1ul << RTC_TAMPCTL_TAMP5DBEN_Pos)              /*!< RTC_T::TAMPCTL: TAMP5DBEN Mask         */
+
+#define RTC_TAMPCTL_DYNPR2EN_Pos         (31)                                              /*!< RTC_T::TAMPCTL: DYNPR2EN Position      */
+#define RTC_TAMPCTL_DYNPR2EN_Msk         (0x1ul << RTC_TAMPCTL_DYNPR2EN_Pos)               /*!< RTC_T::TAMPCTL: DYNPR2EN Mask          */
+
+#define RTC_TAMPSEED_SEED_Pos            (0)                                               /*!< RTC_T::TAMPSEED: SEED Position         */
+#define RTC_TAMPSEED_SEED_Msk            (0xfffffffful << RTC_TAMPSEED_SEED_Pos)           /*!< RTC_T::TAMPSEED: SEED Mask             */
+
+#define RTC_TAMPTIME_SEC_Pos             (0)                                               /*!< RTC_T::TAMPTIME: SEC Position          */
+#define RTC_TAMPTIME_SEC_Msk             (0xful << RTC_TAMPTIME_SEC_Pos)                   /*!< RTC_T::TAMPTIME: SEC Mask              */
+
+#define RTC_TAMPTIME_TENSEC_Pos          (4)                                               /*!< RTC_T::TAMPTIME: TENSEC Position       */
+#define RTC_TAMPTIME_TENSEC_Msk          (0x7ul << RTC_TAMPTIME_TENSEC_Pos)                /*!< RTC_T::TAMPTIME: TENSEC Mask           */
+
+#define RTC_TAMPTIME_MIN_Pos             (8)                                               /*!< RTC_T::TAMPTIME: MIN Position          */
+#define RTC_TAMPTIME_MIN_Msk             (0xful << RTC_TAMPTIME_MIN_Pos)                   /*!< RTC_T::TAMPTIME: MIN Mask              */
+
+#define RTC_TAMPTIME_TENMIN_Pos          (12)                                              /*!< RTC_T::TAMPTIME: TENMIN Position       */
+#define RTC_TAMPTIME_TENMIN_Msk          (0x7ul << RTC_TAMPTIME_TENMIN_Pos)                /*!< RTC_T::TAMPTIME: TENMIN Mask           */
+
+#define RTC_TAMPTIME_HR_Pos              (16)                                              /*!< RTC_T::TAMPTIME: HR Position           */
+#define RTC_TAMPTIME_HR_Msk              (0xful << RTC_TAMPTIME_HR_Pos)                    /*!< RTC_T::TAMPTIME: HR Mask               */
+
+#define RTC_TAMPTIME_TENHR_Pos           (20)                                              /*!< RTC_T::TAMPTIME: TENHR Position        */
+#define RTC_TAMPTIME_TENHR_Msk           (0x3ul << RTC_TAMPTIME_TENHR_Pos)                 /*!< RTC_T::TAMPTIME: TENHR Mask            */
+
+#define RTC_TAMPCAL_DAY_Pos              (0)                                               /*!< RTC_T::TAMPCAL: DAY Position           */
+#define RTC_TAMPCAL_DAY_Msk              (0xful << RTC_TAMPCAL_DAY_Pos)                    /*!< RTC_T::TAMPCAL: DAY Mask               */
+
+#define RTC_TAMPCAL_TENDAY_Pos           (4)                                               /*!< RTC_T::TAMPCAL: TENDAY Position        */
+#define RTC_TAMPCAL_TENDAY_Msk           (0x3ul << RTC_TAMPCAL_TENDAY_Pos)                 /*!< RTC_T::TAMPCAL: TENDAY Mask            */
+
+#define RTC_TAMPCAL_MON_Pos              (8)                                               /*!< RTC_T::TAMPCAL: MON Position           */
+#define RTC_TAMPCAL_MON_Msk              (0xful << RTC_TAMPCAL_MON_Pos)                    /*!< RTC_T::TAMPCAL: MON Mask               */
+
+#define RTC_TAMPCAL_TENMON_Pos           (12)                                              /*!< RTC_T::TAMPCAL: TENMON Position        */
+#define RTC_TAMPCAL_TENMON_Msk           (0x1ul << RTC_TAMPCAL_TENMON_Pos)                 /*!< RTC_T::TAMPCAL: TENMON Mask            */
+
+#define RTC_TAMPCAL_YEAR_Pos             (16)                                              /*!< RTC_T::TAMPCAL: YEAR Position          */
+#define RTC_TAMPCAL_YEAR_Msk             (0xful << RTC_TAMPCAL_YEAR_Pos)                   /*!< RTC_T::TAMPCAL: YEAR Mask              */
+
+#define RTC_TAMPCAL_TENYEAR_Pos          (20)                                              /*!< RTC_T::TAMPCAL: TENYEAR Position       */
+#define RTC_TAMPCAL_TENYEAR_Msk          (0xful << RTC_TAMPCAL_TENYEAR_Pos)                /*!< RTC_T::TAMPCAL: TENYEAR Mask           */
+
+#define RTC_CLKDCTL_LXTFDEN_Pos          (0)                                               /*!< RTC_T::CLKDCTL: LXTFDEN Position       */
+#define RTC_CLKDCTL_LXTFDEN_Msk          (0x1ul << RTC_CLKDCTL_LXTFDEN_Pos)                /*!< RTC_T::CLKDCTL: LXTFDEN Mask           */
+
+#define RTC_CLKDCTL_LXTFSW_Pos           (1)                                               /*!< RTC_T::CLKDCTL: LXTFSW Position        */
+#define RTC_CLKDCTL_LXTFSW_Msk           (0x1ul << RTC_CLKDCTL_LXTFSW_Pos)                 /*!< RTC_T::CLKDCTL: LXTFSW Mask            */
+
+#define RTC_CLKDCTL_LXTSTSW_Pos          (2)                                               /*!< RTC_T::CLKDCTL: LXTSTSW Position       */
+#define RTC_CLKDCTL_LXTSTSW_Msk          (0x1ul << RTC_CLKDCTL_LXTSTSW_Pos)                /*!< RTC_T::CLKDCTL: LXTSTSW Mask           */
+
+#define RTC_CLKDCTL_SWLIRCF_Pos          (16)                                              /*!< RTC_T::CLKDCTL: SWLIRCF Position       */
+#define RTC_CLKDCTL_SWLIRCF_Msk          (0x1ul << RTC_CLKDCTL_SWLIRCF_Pos)                /*!< RTC_T::CLKDCTL: SWLIRCF Mask           */
+
+#define RTC_CLKDCTL_LXTSLOWF_Pos         (17)                                              /*!< RTC_T::CLKDCTL: LXTSLOWF Position      */
+#define RTC_CLKDCTL_LXTSLOWF_Msk         (0x1ul << RTC_CLKDCTL_LXTSLOWF_Pos)               /*!< RTC_T::CLKDCTL: LXTSLOWF Mask          */
+
+#define RTC_CDBR_STOPBD_Pos              (0)                                               /*!< RTC_T::CDBR: STOPBD Position           */
+#define RTC_CDBR_STOPBD_Msk              (0xfful << RTC_CDBR_STOPBD_Pos)                   /*!< RTC_T::CDBR: STOPBD Mask               */
+
+#define RTC_CDBR_FAILBD_Pos              (16)                                              /*!< RTC_T::CDBR: FAILBD Position           */
+#define RTC_CDBR_FAILBD_Msk              (0xfful << RTC_CDBR_FAILBD_Pos)                   /*!< RTC_T::CDBR: FAILBD Mask               */
+
+/**@}*/ /* RTC_CONST */
+/**@}*/ /* end of RTC register group */
+/**@}*/ /* end of REGISTER group */
+
+#endif /* __RTC_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/sc_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/sc_reg.h
new file mode 100644
index 0000000000..4b69e96fd3
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/sc_reg.h
@@ -0,0 +1,980 @@
+/**************************************************************************//**
+ * @file     sc_reg.h
+ * @version  V1.00
+ * @brief    SC register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __SC_REG_H__
+#define __SC_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+/*---------------------- Smart Card Host Interface Controller -------------------------*/
+/**
+    @addtogroup SC Smart Card Host Interface Controller(SC)
+    Memory Mapped Structure for SC Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var SC_T::DAT
+     * Offset: 0x00  SC Receive/Transmit Holding Buffer Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |DAT       |Receive/Transmit Holding Buffer
+     * |        |          |Write Operation:
+     * |        |          |By writing data to DAT, the SC will send out an 8-bit data.
+     * |        |          |Note: If SCEN (SCn_CTL[0]) is not enabled, DAT cannot be programmed.
+     * |        |          |Read Operation:
+     * |        |          |By reading DAT, the SC will return an 8-bit received data.
+     * @var SC_T::CTL
+     * Offset: 0x04  SC Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SCEN      |SC Controller Enable Bit
+     * |        |          |Set this bit to 1 to enable SC operation.
+     * |        |          |0 = SC will force all transition to IDLE state.
+     * |        |          |1 = SC controller is enabled and all function can work correctly.
+     * |        |          |Note1: SCEN must be set to 1 before filling in other SC registers, or smart card will not work properly.
+     * |[1]     |RXOFF     |RX Transition Disable Control Bit
+     * |        |          |This bit is used for disable Rx transition function.
+     * |        |          |0 = The receiver Enabled.
+     * |        |          |1 = The receiver Disabled.
+     * |        |          |Note1: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored.
+     * |[2]     |TXOFF     |TX Transition Disable Control Bit
+     * |        |          |This bit is used for disable Tx transition function.
+     * |        |          |0 = The transceiver Enabled.
+     * |        |          |1 = The transceiver Disabled.
+     * |[3]     |AUTOCEN   |Auto Convention Enable Bit
+     * |        |          |This bit is used for enable auto convention function.
+     * |        |          |0 = Auto-convention Disabled.
+     * |        |          |1 = Auto-convention Enabled.
+     * |        |          |If user enables auto convention function, the setting step must be done before Answer to Reset (ATR) state and the first data must be 0x3B or 0x3F
+     * |        |          |After hardware received first data and stored it at buffer, hardware will decided the convention and change the CONSEL (SCn_CTL[5:4]) bits automatically when received first data is 0x3B or 0x3F
+     * |        |          |If received first byte is 0x3B, TS is direct convention, CONSEL (SCn_CTL[5:4]) will be set to 00 automatically, otherwise the TS is inverse convention, and CONSEL (SCn_CTL[5:4]) will be set to 11.
+     * |        |          |If the first data is not 0x3B or 0x3F, hardware will set ACERRIF (SCn_INTSTS[10]) and generate an interrupt to CPU when ACERRIEN (SCn_INTEN[10]) is enabled.
+     * |[5:4]   |CONSEL    |Convention Selection
+     * |        |          |00 = Direct convention.
+     * |        |          |01 = Reserved.
+     * |        |          |10 = Reserved.
+     * |        |          |11 = Inverse convention.
+     * |        |          |Note: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored.
+     * |[7:6]   |RXTRGLV   |Rx Buffer Trigger Level
+     * |        |          |When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set
+     * |        |          |If RDAIEN (SCn_INTEN[0]) is enabled, an interrupt will be generated to CPU.
+     * |        |          |00 = Rx Buffer Trigger Level with 01 bytes.
+     * |        |          |01 = Rx Buffer Trigger Level with 02 bytes.
+     * |        |          |10 = Rx Buffer Trigger Level with 03 bytes.
+     * |        |          |11 = Reserved.
+     * |[12:8]  |BGT       |Block Guard Time (BGT)
+     * |        |          |Block guard time means the minimum interval between the leading edges of two consecutive characters between different transfer directions
+     * |        |          |This field indicates the counter for the bit length of block guard time
+     * |        |          |According to ISO 7816-3, in T = 0 mode, user must fill 15 (real block guard time = 16.5) to this field; in T = 1 mode, user must fill 21 (real block guard time = 22.5) to it.
+     * |        |          |Note: The real block guard time is BGT + 1.
+     * |[14:13] |TMRSEL    |Timer Channel Selection
+     * |        |          |00 = All internal timer function Disabled.
+     * |        |          |.
+     * |        |          |11 = Internal 24 bit timer and two 8 bit timers Enabled
+     * |        |          |User can configure them by setting SCn_TMRCTL0[23:0], SCn_TMRCTL1[7:0] and SCn_TMRCTL2[7:0].
+     * |        |          |Other configurations are reserve
+     * |[15]    |NSB       |Stop Bit Length
+     * |        |          |This field indicates the length of stop bit.
+     * |        |          |0 = The stop bit length is 2 ETU.(for ISO 7816-3 T=0 mode).
+     * |        |          |1= The stop bit length is 1 ETU.(for ISO 7816-3 T=1 mode).
+     * |        |          |Note1: The default stop bit length is 2. SC and UART adopts NSB to program the stop bit length.
+     * |        |          |Note2: In UART mode, RX can receive the data sequence in 1 stop bit or 2 stop bits with NSB is set to 0.
+     * |[18:16] |RXRTY     |RX Error Retry Count Number
+     * |        |          |This field indicates the maximum number of receiver retries that are allowed when parity error has occurred
+     * |        |          |Note1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.
+     * |        |          |Note2: This field cannot be changed when RXRTYEN enabled
+     * |        |          |The change flow is to disable RXRTYEN first and then fill in new retry value.
+     * |[19]    |RXRTYEN   |RX Error Retry Enable Bit
+     * |        |          |This bit enables receiver retry function when parity error has occurred.
+     * |        |          |0 = RX error retry function Disabled.
+     * |        |          |1 = RX error retry function Enabled.
+     * |        |          |Note: User must fill in the RXRTY value before enabling this bit.
+     * |[22:20] |TXRTY     |TX Error Retry Count Number
+     * |        |          |This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.
+     * |        |          |Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.
+     * |        |          |Note2: This field cannot be changed when TXRTYEN enabled
+     * |        |          |The change flow is to disable TXRTYEN first and then fill in new retry value.
+     * |[23]    |TXRTYEN   |TX Error Retry Enable Bit
+     * |        |          |This bit enables transmitter retry function when parity error has occurred.
+     * |        |          |0 = TX error retry function Disabled.
+     * |        |          |1 = TX error retry function Enabled.
+     * |[25:24] |CDDBSEL   |Card Detect De-bounce Selection
+     * |        |          |This field indicates the card detect de-bounce selection.
+     * |        |          |00 = De-bounce sample card insert once per 384 (128 * 3) SC module clocks and de-bounce sample card removal once per 128 SC module clocks.
+     * |        |          |Other configurations are reserved.
+     * |[26]    |CDLV      |Card Detect Level Selection
+     * |        |          |0 = When hardware detects the card detect pin (SCn_CD) from high to low, it indicates a card is detected.
+     * |        |          |1 = When hardware detects the card detect pin (SCn_CD) from low to high, it indicates a card is detected.
+     * |        |          |Note: User must select card detect level before Smart Card controller enabled.
+     * |[30]    |SYNC      |SYNC Flag Indicator (Read Only)
+     * |        |          |Due to synchronization, user should check this bit before writing a new value to RXRTY and TXRTY fields.
+     * |        |          |0 = Synchronizing is completion, user can write new data to RXRTY and TXRTY.
+     * |        |          |1 = Last value is synchronizing.
+     * @var SC_T::ALTCTL
+     * Offset: 0x08  SC Alternate Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |TXRST     |TX Software Reset
+     * |        |          |When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset the TX internal state machine and pointers.
+     * |        |          |Note: This bit will be auto cleared after reset is complete.
+     * |[1]     |RXRST     |Rx Software Reset
+     * |        |          |When RXRST is set, all the bytes in the receive buffer and Rx internal state machine will be cleared.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset the Rx internal state machine and pointers.
+     * |        |          |Note: This bit will be auto cleared after reset is complete.
+     * |[2]     |DACTEN    |Deactivation Sequence Generator Enable Bit
+     * |        |          |This bit enables SC controller to initiate the card by deactivation sequence.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Deactivation sequence generator Enabled.
+     * |        |          |Note1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.
+     * |        |          |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1])
+     * |        |          |Thus, do not fill in this bit DACTEN, TXRST and RXRST at the same time.
+     * |        |          |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
+     * |[3]     |ACTEN     |Activation Sequence Generator Enable Bit
+     * |        |          |This bit enables SC controller to initiate the card by activation sequence.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Activation sequence generator Enabled.
+     * |        |          |Note1: When the activation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.
+     * |        |          |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1])
+     * |        |          |Thus, do not fill in this bit ACTEN, TXRST and RXRST at the same time.
+     * |        |          |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
+     * |        |          |Note4: During the activation sequence, RX is disabled automatically and can not receive data
+     * |        |          |After the activation sequence completion, RXOFF (SCn_CTL[1]) keeps the state before hardware activation.
+     * |[4]     |WARSTEN   |Warm Reset Sequence Generator Enable Bit
+     * |        |          |This bit enables SC controller to initiate the card by warm reset sequence.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Warm reset sequence generator Enabled.
+     * |        |          |Note1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.
+     * |        |          |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1])
+     * |        |          |Thus, do not fill in this bit WARSTEN, TXRST and RXRST at the same time.
+     * |        |          |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
+     * |        |          |Note4: During the warm reset sequence, RX is disabled automatically and can not receive data
+     * |        |          |After the warm reset sequence completion, RXOFF (SCn_CTL[1]) keeps the state before perform warm reset sequence.
+     * |[5]     |CNTEN0    |Internal Timer0 Start Enable Bit
+     * |        |          |This bit enables Timer 0 to start counting
+     * |        |          |User can fill 0 to stop it and set 1 to reload and count
+     * |        |          |The counter unit is ETU base.
+     * |        |          |0 = Stops counting.
+     * |        |          |1 = Start counting.
+     * |        |          |Note1: This field is used for internal 24 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only.
+     * |        |          |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL0[26] = 0), this bit will be auto-cleared by hardware.
+     * |        |          |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed
+     * |[6]     |CNTEN1    |Internal Timer1 Start Enable Bit
+     * |        |          |This bit enables Timer 1 to start counting
+     * |        |          |User can fill 0 to stop it and set 1 to reload and count
+     * |        |          |The counter unit is ETU base.
+     * |        |          |0 = Stops counting.
+     * |        |          |1 = Start counting.
+     * |        |          |Note1: This field is used for internal 8 bit timer when TMRSEL(SCn_CTL[14:13]) is 11 only
+     * |        |          |Do not fill CNTEN1 when TMRSEL (SCn_CTL[14:13]) is not equal to 11.
+     * |        |          |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL1[26] = 0), this bit will be auto-cleared by hardware.
+     * |        |          |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
+     * |[7]     |CNTEN2    |Internal Timer2 Start Enable Bit
+     * |        |          |This bit enables Timer 2 to start counting
+     * |        |          |User can fill 0 to stop it and set 1 to reload and count
+     * |        |          |The counter unit is ETU base.
+     * |        |          |0 = Stops counting.
+     * |        |          |1 = Start counting.
+     * |        |          |Note1: This field is used for internal 8 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only
+     * |        |          |Do not fill in CNTEN2 when TMRSEL (SCn_CTL[14:13]) is not equal to 11.
+     * |        |          |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL2[26] = 0), this bit will be auto-cleared by hardware.
+     * |        |          |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
+     * |[9:8]   |INITSEL   |Initial Timing Selection
+     * |        |          |This fields indicates the initial timing of hardware activation, warm-reset or deactivation.
+     * |        |          |The unit of initial timing is SC module clock.
+     * |        |          |Activation: refer to SC Activation Sequence in Figure 6.17-4 SC Activation Sequence.
+     * |        |          |Warm-reset: refer to Warm-Reset Sequence in Figure 6.17-5 SC Warm Reset Sequence.
+     * |        |          |Deactivation: refer to Deactivation Sequence in Figure 6.17-6 SC Deactivation Sequence.
+     * |        |          |Note: When set activation and warm reset in Timer0 operation mode 0011, it may have deviation at most 128 SC module clock cycles.
+     * |[11]    |ADACEN    |Auto Deactivation When Card Removal
+     * |        |          |This bit is used for enable hardware auto deactivation when smart card is removed.
+     * |        |          |0 = Auto deactivation Disabled.
+     * |        |          |1 = Auto deactivation Enabled.
+     * |        |          |Note: When the card is removed, hardware will stop any process and then do deactivation sequence if this bit is set
+     * |        |          |If auto deactivation process completes, hardware will set INITIF (SCn_INTSTS[8]) also.
+     * |[12]    |RXBGTEN   |Receiver Block Guard Time Function Enable Bit
+     * |        |          |This bit enables the receiver block guard time function.
+     * |        |          |0 = Receiver block guard time function Disabled.
+     * |        |          |1 = Receiver block guard time function Enabled.
+     * |[13]    |ACTSTS0   |Internal Timer0 Active Status (Read Only)
+     * |        |          |This bit indicates the timer counter status of timer0.
+     * |        |          |0 = Timer0 is not active.
+     * |        |          |1 = Timer0 is active.
+     * |        |          |Note: Timer0 is active does not always mean timer0 is counting the CNT (SCn_TMRCTL0[23:0]).
+     * |[14]    |ACTSTS1   |Internal Timer1 Active Status (Read Only)
+     * |        |          |This bit indicates the timer counter status of timer1.
+     * |        |          |0 = Timer1 is not active.
+     * |        |          |1 = Timer1 is active.
+     * |        |          |Note: Timer1 is active does not always mean timer1 is counting the CNT (SCn_TMRCTL1[7:0]).
+     * |[15]    |ACTSTS2   |Internal Timer2 Active Status (Read Only)
+     * |        |          |This bit indicates the timer counter status of timer2.
+     * |        |          |0 = Timer2 is not active.
+     * |        |          |1 = Timer2 is active.
+     * |        |          |Note: Timer2 is active does not always mean timer2 is counting the CNT (SCn_TMRCTL2[7:0]).
+     * |[31]    |SYNC      |SYNC Flag Indicator (Read Only)
+     * |        |          |Due to synchronization, user should check this bit when writing a new value to SCn_ALTCTL register.
+     * |        |          |0 = Synchronizing is completion, user can write new data to SCn_ALTCTL register.
+     * |        |          |1 = Last value is synchronizing.
+     * @var SC_T::EGT
+     * Offset: 0x0C  SC Extra Guard Time Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |EGT       |Extra Guard Time
+     * |        |          |This field indicates the extra guard time value.
+     * |        |          |Note: The extra guard time unit is ETU base.
+     * @var SC_T::RXTOUT
+     * Offset: 0x10  SC Receive Buffer Time-out Counter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[8:0]   |RFTM      |SC Receiver FIFO Time-out Counter
+     * |        |          |The time-out down counter resets and starts counting whenever the RX buffer received a new data
+     * |        |          |Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SCn_DAT, a receiver time-out flag RXTOIF (SCn_INTSTS[9]) will be set, and hardware will generate an interrupt to CPU when RXTOIEN (SCn_INTEN[9]) is enabled.
+     * |        |          |Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5.
+     * |        |          |Note2: Filling in all 0 to this field indicates to disable this function.
+     * @var SC_T::ETUCTL
+     * Offset: 0x14  SC Element Time Unit Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[11:0]  |ETURDIV   |ETU Rate Divider
+     * |        |          |The field is used for ETU clock rate divider.
+     * |        |          |The real ETU is ETURDIV + 1.
+     * |        |          |Note: User can configure this field, but this field must be greater than 0x04.
+     * @var SC_T::INTEN
+     * Offset: 0x18  SC Interrupt Enable Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RDAIEN    |Receive Data Reach Interrupt Enable Bit
+     * |        |          |This field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt.
+     * |        |          |0 = Receive data reach trigger level interrupt Disabled.
+     * |        |          |1 = Receive data reach trigger level interrupt Enabled.
+     * |[1]     |TBEIEN    |Transmit Buffer Empty Interrupt Enable Bit
+     * |        |          |This field is used to enable transmit buffer empty interrupt.
+     * |        |          |0 = Transmit buffer empty interrupt Disabled.
+     * |        |          |1 = Transmit buffer empty interrupt Enabled.
+     * |[2]     |TERRIEN   |Transfer Error Interrupt Enable Bit
+     * |        |          |This field is used to enable transfer error interrupt
+     * |        |          |The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5]), parity error PEF (SCn_STATUS[4]), receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22]) and transmitter retry over limit error TXOVERR (SCn_STATUS[30]).
+     * |        |          |0 = Transfer error interrupt Disabled.
+     * |        |          |1 = Transfer error interrupt Enabled.
+     * |[3]     |TMR0IEN   |Timer0 Interrupt Enable Bit
+     * |        |          |This field is used to enable Timer0 interrupt function.
+     * |        |          |0 = Timer0 interrupt Disabled.
+     * |        |          |1 = Timer0 interrupt Enabled.
+     * |[4]     |TMR1IEN   |Timer1 Interrupt Enable Bit
+     * |        |          |This field is used to enable the Timer1 interrupt function.
+     * |        |          |0 = Timer1 interrupt Disabled.
+     * |        |          |1 = Timer1 interrupt Enabled.
+     * |[5]     |TMR2IEN   |Timer2 Interrupt Enable Bit
+     * |        |          |This field is used to enable Timer2 interrupt function.
+     * |        |          |0 = Timer2 interrupt Disabled.
+     * |        |          |1 = Timer2 interrupt Enabled.
+     * |[6]     |BGTIEN    |Block Guard Time Interrupt Enable Bit
+     * |        |          |This field is used to enable block guard time interrupt in receive direction.
+     * |        |          |0 = Block guard time interrupt Disabled.
+     * |        |          |1 = Block guard time interrupt Enabled.
+     * |        |          |Note: This bit is valid only for receive receive direction block guard time.
+     * |[7]     |CDIEN     |Card Detect Interrupt Enable Bit
+     * |        |          |This field is used to enable card detect interrupt
+     * |        |          |The card detect status is CDPINSTS (SCn_STATUS[13]).
+     * |        |          |0 = Card detect interrupt Disabled.
+     * |        |          |1 = Card detect interrupt Enabled.
+     * |[8]     |INITIEN   |Initial End Interrupt Enable Bit
+     * |        |          |This field is used to enable activation (ACTEN (SCn_ALTCTL[3] = 1)), deactivation (DACTEN (SCn_ALTCTL[2] = 1)) and warm reset (WARSTEN (SCn_ALTCTL [4])) sequence complete interrupt.
+     * |        |          |0 = Initial end interrupt Disabled.
+     * |        |          |1 = Initial end interrupt Enabled.
+     * |[9]     |RXTOIEN   |Receiver Buffer Time-out Interrupt Enable Bit
+     * |        |          |This field is used to enable receiver buffer time-out interrupt.
+     * |        |          |0 = Receiver buffer time-out interrupt Disabled.
+     * |        |          |1 = Receiver buffer time-out interrupt Enabled.
+     * |[10]    |ACERRIEN  |Auto Convention Error Interrupt Enable Bit
+     * |        |          |This field is used to enable auto-convention error interrupt.
+     * |        |          |0 = Auto-convention error interrupt Disabled.
+     * |        |          |1 = Auto-convention error interrupt Enabled.
+     * @var SC_T::INTSTS
+     * Offset: 0x1C  SC Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RDAIF     |Receive Data Reach Interrupt Status Flag (Read Only)
+     * |        |          |This field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag.
+     * |        |          |0 = Number of receive buffer is less than RXTRGLV setting.
+     * |        |          |1 = Number of receive buffer data equals the RXTRGLV setting.
+     * |        |          |Note: This bit is read only
+     * |        |          |If user reads data from SCn_DAT and receiver buffer data byte number is less than RXTRGLV, this bit will be cleared automatically.
+     * |[1]     |TBEIF     |Transmit Buffer Empty Interrupt Status Flag (Read Only)
+     * |        |          |This field is used for transmit buffer empty interrupt status flag.
+     * |        |          |0 = Transmit buffer is not empty.
+     * |        |          |1 = Transmit buffer is empty.
+     * |        |          |Note: This bit is read only
+     * |        |          |If user wants to clear this bit, user must write data to DAT (SCn_DAT[7:0]) and then this bit will be cleared automatically.
+     * |[2]     |TERRIF    |Transfer Error Interrupt Status Flag
+     * |        |          |This field is used for transfer error interrupt status flag
+     * |        |          |The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5], parity error PEF (SCn_STATUS[4] and receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22] or transmitter retry over limit error TXOVERR (SCn_STATUS[30]).
+     * |        |          |0 = Transfer error interrupt did not occur.
+     * |        |          |1 = Transfer error interrupt occurred.
+     * |        |          |Note1: This field is the status flag of BEF, FEF, PEF, RXOV, TXOV, RXOVERR or TXOVERR.
+     * |        |          |Note2: This bit can be cleared by writing 1 to it.
+     * |[3]     |TMR0IF    |Timer0 Interrupt Status Flag
+     * |        |          |This field is used for Timer0 interrupt status flag.
+     * |        |          |0 = Timer0 interrupt did not occur.
+     * |        |          |1 = Timer0 interrupt occurred.
+     * |        |          |Note: This bit can be cleared by writing 1 to it.
+     * |[4]     |TMR1IF    |Timer1 Interrupt Status Flag
+     * |        |          |This field is used for Timer1 interrupt status flag.
+     * |        |          |0 = Timer1 interrupt did not occur.
+     * |        |          |1 = Timer1 interrupt occurred.
+     * |        |          |Note: This bit can be cleared by writing 1 to it.
+     * |[5]     |TMR2IF    |Timer2 Interrupt Status Flag
+     * |        |          |This field is used for Timer2 interrupt status flag.
+     * |        |          |0 = Timer2 interrupt did not occur.
+     * |        |          |1 = Timer2 interrupt occurred.
+     * |        |          |Note: This bit can be cleared by writing 1 to it.
+     * |[6]     |BGTIF     |Block Guard Time Interrupt Status Flag
+     * |        |          |This field is used for indicate block guard time interrupt status flag in receive direction.
+     * |        |          |0 = Block guard time interrupt did not occur.
+     * |        |          |1 = Block guard time interrupt occurred.
+     * |        |          |Note1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled.
+     * |        |          |Note2: This bit can be cleared by writing 1 to it.
+     * |[7]     |CDIF      |Card Detect Interrupt Status Flag (Read Only)
+     * |        |          |This field is used for card detect interrupt status flag
+     * |        |          |The card detect status is CINSERT (SCn_STATUS[12]) and CREMOVE (SCn_STATUS[11]).
+     * |        |          |0 = Card detect event did not occur.
+     * |        |          |1 = Card detect event occurred.
+     * |        |          |Note: This bit is read only, user must to clear CINSERT or CREMOVE status to clear it.
+     * |[8]     |INITIF    |Initial End Interrupt Status Flag
+     * |        |          |This field is used for activation (ACTEN (SCn_ALTCTL[3])), deactivation (DACTEN (SCn_ALTCTL[2])) and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag.
+     * |        |          |0 = Initial sequence is not complete.
+     * |        |          |1 = Initial sequence is completed.
+     * |        |          |Note: This bit can be cleared by writing 1 to it.
+     * |[9]     |RXTOIF    |Receive Buffer Time-out Interrupt Status Flag (Read Only)
+     * |        |          |This field is used for indicate receive buffer time-out interrupt status flag.
+     * |        |          |0 = Receive buffer time-out interrupt did not occur.
+     * |        |          |1 = Receive buffer time-out interrupt occurred.
+     * |        |          |Note: This bit is read only, user must read all receive buffer remaining data by reading SCn_DAT register to clear it.
+     * |[10]    |ACERRIF   |Auto Convention Error Interrupt Status Flag
+     * |        |          |This field indicates auto convention sequence error.
+     * |        |          |0 = Received TS at ATR state is 0x3B or 0x3F.
+     * |        |          |1 = Received TS at ATR state is neither 0x3B nor 0x3F.
+     * |        |          |Note: This bit can be cleared by writing 1 to it.
+     * @var SC_T::STATUS
+     * Offset: 0x20  SC Transfer Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RXOV      |Receive Overflow Error Status Flag
+     * |        |          |This bit is set when Rx buffer overflow.
+     * |        |          |0 = Rx buffer is not overflow.
+     * |        |          |1 = Rx buffer is overflow when the number of received bytes is greater than Rx buffer size (4 bytes).
+     * |        |          |Note: This bit can be cleared by writing 1 to it.
+     * |[1]     |RXEMPTY   |Receive Buffer Empty Status Flag (Read Only)
+     * |        |          |This bit indicates Rx buffer empty or not.
+     * |        |          |0 = Rx buffer is not empty.
+     * |        |          |1 = Rx buffer is empty, it means the last byte of Rx buffer has read from DAT (SCn_DAT[7:0]) by CPU.
+     * |[2]     |RXFULL    |Receive Buffer Full Status Flag (Read Only)
+     * |        |          |This bit indicates Rx buffer full or not.
+     * |        |          |0 = Rx buffer count is less than 4.
+     * |        |          |1 = Rx buffer count equals to 4.
+     * |[4]     |PEF       |Receiver Parity Error Status Flag
+     * |        |          |This bit is set to logic 1 whenever the received character does not have a valid parity bit.
+     * |        |          |0 = Receiver parity error flag did not occur.
+     * |        |          |1 = Receiver parity error flag occurred.
+     * |        |          |Note1: This bit can be cleared by writing 1 to it.
+     * |        |          |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
+     * |[5]     |FEF       |Receiver Frame Error Status Flag
+     * |        |          |This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
+     * |        |          |0 = Receiver frame error flag did not occur.
+     * |        |          |1 = Receiver frame error flag occurred.
+     * |        |          |Note1: This bit can be cleared by writing 1 to it.
+     * |        |          |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
+     * |[6]     |BEF       |Receiver Break Error Status Flag
+     * |        |          |This bit is set to logic 1 whenever the received data input (Rx) held in the spacing state (logic 0) is longer than a full word transmission time (that is, the total time of start bit + data bits + parity bit + stop bits).
+     * |        |          |0 = Receiver break error flag did not occur.
+     * |        |          |1 = Receiver break error flag occurred.
+     * |        |          |Note1: This bit can be cleared by writing 1 to it.
+     * |        |          |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
+     * |[8]     |TXOV      |Transmit Overflow Error Interrupt Status Flag
+     * |        |          |This bit is set when Tx buffer overflow.
+     * |        |          |0 = Tx buffer is not overflow.
+     * |        |          |1 = Tx buffer is overflow when Tx buffer is full and an additional write operation to DAT (SCn_DAT[7:0]).
+     * |        |          |Note: This bit can be cleared by writing 1 to it.
+     * |[9]     |TXEMPTY   |Transmit Buffer Empty Status Flag (Read Only)
+     * |        |          |This bit indicates TX buffer empty or not.
+     * |        |          |0 = Tx buffer is not empty.
+     * |        |          |1 = Tx buffer is empty, it means the last byte of Tx buffer has been transferred to Transmitter Shift Register.
+     * |        |          |Note: This bit will be cleared when writing data into DAT (SCn_DAT[7:0]).
+     * |[10]    |TXFULL    |Transmit Buffer Full Status Flag (Read Only)
+     * |        |          |This bit indicates Tx buffer full or not.
+     * |        |          |0 = Tx buffer count is less than 4.
+     * |        |          |1 = Tx buffer count equals to 4.
+     * |[11]    |CREMOVE   |Card Removal Status of SCn_CD Pin
+     * |        |          |This bit is set whenever card has been removal.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Card removed.
+     * |        |          |Note1: This bit can be cleared by writing 1 to it.
+     * |        |          |Note2: Card detect function will start after SCEN (SCn_CTL[0]) set.
+     * |[12]    |CINSERT   |Card Insert Status of SCn_CD Pin
+     * |        |          |This bit is set whenever card has been inserted.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Card insert.
+     * |        |          |Note1: This bit can be cleared by writing 1 to it.
+     * |        |          |Note2: The card detect function will start after SCEN (SCn_CTL[0]) set.
+     * |[13]    |CDPINSTS  |Card Detect Pin Status (Read Only)
+     * |        |          |This bit is the pin status of SCn_CD.
+     * |        |          |0 = The SCn_CD pin state at low.
+     * |        |          |1 = The SCn_CD pin state at high.
+     * |[18:16] |RXPOINT   |Receive Buffer Pointer Status (Read Only)
+     * |        |          |This field indicates the Rx buffer pointer status
+     * |        |          |When SC controller receives one byte from external device, RXPOINT increases one
+     * |        |          |When one byte of Rx buffer is read by CPU, RXPOINT decreases one.
+     * |[21]    |RXRERR    |Receiver Retry Error
+     * |        |          |This bit is used for receiver error retry and set by hardware.
+     * |        |          |0 = No Rx retry transfer.
+     * |        |          |1 = Rx has any error and retries transfer.
+     * |        |          |Note1: This bit can be cleared by writing 1 to it.
+     * |        |          |Note2 This bit is a flag and cannot generate any interrupt to CPU.
+     * |        |          |Note3: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
+     * |[22]    |RXOVERR   |Receiver over Retry Error
+     * |        |          |This bit is used for receiver retry counts over than retry number limitation.
+     * |        |          |0 = Receiver retries counts is not over than RXRTY (SCn_CTL[18:16]) + 1.
+     * |        |          |1 = Receiver retries counts over than RXRTY (SCn_CTL[18:16]) + 1.
+     * |        |          |Note1: This bit can be cleared by writing 1 to it.
+     * |        |          |Note2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
+     * |[23]    |RXACT     |Receiver in Active Status Flag (Read Only)
+     * |        |          |This bit indicates Rx transfer status.
+     * |        |          |0 = This bit is cleared automatically when Rx transfer is finished.
+     * |        |          |1 = This bit is set by hardware when Rx transfer is in active.
+     * |        |          |Note: This bit is read only.
+     * |        |          |Note2:
+     * |[26:24] |TXPOINT   |Transmit Buffer Pointer Status (Read Only)
+     * |        |          |This field indicates the Tx buffer pointer status
+     * |        |          |When CPU writes data into SCn_DAT, TXPOINT increases one
+     * |        |          |When one byte of Tx buffer is transferred to transmitter shift register, TXPOINT decreases one.
+     * |[29]    |TXRERR    |Transmitter Retry Error
+     * |        |          |This bit is used for indicate transmitter error retry and set by hardware..
+     * |        |          |0 = No Tx retry transfer.
+     * |        |          |1 = Tx has any error and retries transfer.
+     * |        |          |Note1: This bit can be cleared by writing 1 to it.
+     * |        |          |Note2: This bit is a flag and cannot generate any interrupt to CPU.
+     * |[30]    |TXOVERR   |Transmitter over Retry Error
+     * |        |          |This bit is used for transmitter retry counts over than retry number limitation.
+     * |        |          |0 = Transmitter retries counts is not over than TXRTY (SCn_CTL[22:20]) + 1.
+     * |        |          |1 = Transmitter retries counts over than TXRTY (SCn_CTL[22:20]) + 1.
+     * |        |          |Note: This bit can be cleared by writing 1 to it.
+     * |[31]    |TXACT     |Transmit in Active Status Flag (Read Only)
+     * |        |          |This bit indicates Tx transmit status.
+     * |        |          |0 = This bit is cleared automatically when Tx transfer is finished or the last byte transmission has completed.
+     * |        |          |1 = Transmit is active and this bit is set by hardware when Tx transfer is in active and the STOP bit of the last byte has not been transmitted.
+     * |        |          |Note: This bit is read only.
+     * @var SC_T::PINCTL
+     * Offset: 0x24  SC Pin Control State Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PWREN     |SCn_PWR Pin Signal
+     * |        |          |User can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level.
+     * |        |          |Write this field to drive SCn_PWR pin
+     * |        |          |Refer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage level.
+     * |        |          |Read this field to get SCn_PWR signal status.
+     * |        |          |0 = SCn_PWR signal status is low.
+     * |        |          |1 = SCn_PWR signal status is high.
+     * |        |          |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically
+     * |        |          |Thus, do not fill in this field when operating in these modes.
+     * |[1]     |RSTEN     |SCn_RST Pin Signal
+     * |        |          |User can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level.
+     * |        |          |Write this field to drive SCn_RST pin.
+     * |        |          |0 = Drive SCn_RST pin to low.
+     * |        |          |1 = Drive SCn_RST pin to high.
+     * |        |          |Read this field to get SCn_RST signal status.
+     * |        |          |0 = SCn_RST signal status is low.
+     * |        |          |1 = SCn_RST signal status is high.
+     * |        |          |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically
+     * |        |          |Thus, do not fill in this field when operating in these modes.
+     * |[5]     |CSTOPLV   |SCn_CLK Pin Stop Level
+     * |        |          |This field indicates the SCn_CLK pin status when SC clock in clock stop mode.
+     * |        |          |0 = SCn_CLK pin keeps at low when SC clock stopped.
+     * |        |          |1 = SCn_CLK pin keeps at high when SC clock stopped.
+     * |[6]     |CLKKEEP   |SC Clock Enable Bit
+     * |        |          |0 = SC clock generation Disabled.
+     * |        |          |1 = SC clock always keeps free running.
+     * |        |          |Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically
+     * |        |          |Thus, do not fill in this field when operating in these modes.
+     * |[9]     |SCDATA    |SCn_DATA Pin Signal
+     * |        |          |This bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit.
+     * |        |          |0 = Drive SCn_DATA pin to low.
+     * |        |          |1 = Drive SCn_DATA pin to high.
+     * |        |          |Read this field to get SCn_DATA signal status.
+     * |        |          |0 = SCn_DATA signal status is low.
+     * |        |          |1 = SCn_DATA signal status is high.
+     * |        |          |Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically
+     * |        |          |Thus, do not fill in this field when SC is in these modes.
+     * |[11]    |PWRINV    |SCn_PWR Pin Inverse
+     * |        |          |This bit is used for inverse the SCn_PWR pin.
+     * |        |          |There are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]).
+     * |        |          |0 = SCn_PWR pin inverse Disabled
+     * |        |          |If PWREN is 1, SCn_PWR pin status is 1; if PWREN is 0, SCn_PWR pin status is 0.
+     * |        |          |1 = SCn_PWR pin inverse Enabled
+     * |        |          |If PWREN is 1, SCn_PWR pin status is 0; if PWREN is 0, SCn_PWR pin status is 1.
+     * |        |          |Note: User must select PWRINV (SCn_PINCTL[11]) before smart card is enabled by SCEN (SCn_CTL[0]).
+     * |[16]    |DATASTS   |SCn_DATA Pin Status (Read Only)
+     * |        |          |This bit is the pin status of SCn_DATA.
+     * |        |          |0 = The SCn_DATA pin status is low.
+     * |        |          |1 = The SCn_DATA pin status is high.
+     * |        |          |Note:
+     * |[17]    |PWRSTS    |SCn_PWR Pin Status (Read Only)
+     * |        |          |This bit is the pin status of SCn_PWR.
+     * |        |          |0 = SCn_PWR pin to low.
+     * |        |          |1 = SCn_PWR pin to high.
+     * |[18]    |RSTSTS    |SCn_RST Pin Status (Read Only)
+     * |        |          |This bit is the pin status of SCn_RST.
+     * |        |          |0 = SCn_RST pin is low.
+     * |        |          |1 = SCn_RST pin is high.
+     * |[30]    |SYNC      |SYNC Flag Indicator (Read Only)
+     * |        |          |Due to synchronization, user should check this bit when writing a new value to SCn_PINCTL register.
+     * |        |          |0 = Synchronizing is completion, user can write new data to SCn_PINCTL register.
+     * |        |          |1 = Last value is synchronizing.
+     * @var SC_T::TMRCTL0
+     * Offset: 0x28  SC Internal Timer0 Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:0]  |CNT       |Timer0 Counter Value
+     * |        |          |This field indicates the internal Timer0 counter values.
+     * |        |          |Note: Unit of Timer0 counter is ETU base.
+     * |[27:24] |OPMODE    |Timer0 Operation Mode Selection
+     * |        |          |This field indicates the internal 24-bit Timer0 operation selection.
+     * |        |          |Refer to Table 6.17-3 Timer0/Timer1/Timer2 Operation Mode for programming Timer0.
+     * |[31]    |SYNC      |SYNC Flag Indicator (Read Only)
+     * |        |          |Due to synchronization, user should check this bit when writing a new value to the SCn_TMRCTL0 register.
+     * |        |          |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL0 register.
+     * |        |          |1 = Last value is synchronizing.
+     * @var SC_T::TMRCTL1
+     * Offset: 0x2C  SC Internal Timer1 Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |CNT       |Timer 1 Counter Value
+     * |        |          |This field indicates the internal Timer1 counter values.
+     * |        |          |Note: Unit of Timer1 counter is ETU base.
+     * |[27:24] |OPMODE    |Timer 1 Operation Mode Selection
+     * |        |          |This field indicates the internal 8-bit Timer1 operation selection.
+     * |        |          |Refer to Table 6.17-3 Timer0/Timer1/Timer2 Operation Mode for programming Timer1.
+     * |[31]    |SYNC      |SYNC Flag Indicator (Read Only)
+     * |        |          |Due to synchronization, software should check this bit when writing a new value to SCn_TMRCTL1 register.
+     * |        |          |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL1 register.
+     * |        |          |1 = Last value is synchronizing.
+     * @var SC_T::TMRCTL2
+     * Offset: 0x30  SC Internal Timer2 Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |CNT       |Timer 2 Counter Value
+     * |        |          |This field indicates the internal Timer2 counter values.
+     * |        |          |Note: Unit of Timer2 counter is ETU base.
+     * |[27:24] |OPMODE    |Timer 2 Operation Mode Selection
+     * |        |          |This field indicates the internal 8-bit Timer2 operation selection
+     * |        |          |Refer to Table 6.17-3 Timer0/Timer1/Timer2 Operation Mode for programming Timer2.
+     * |[31]    |SYNC      |SYNC Flag Indicator (Read Only)
+     * |        |          |Due to synchronization, user should check this bit when writing a new value to SCn_TMRCTL2 register.
+     * |        |          |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL2 register.
+     * |        |          |1 = Last value is synchronizing.
+     * @var SC_T::UARTCTL
+     * Offset: 0x34  SC UART Mode Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |UARTEN    |UART Mode Enable Bit
+     * |        |          |Sets this bit to enable UART mode function.
+     * |        |          |0 = Smart Card mode.
+     * |        |          |1 = UART mode.
+     * |        |          |Note1: When operating in UART mode, user must set CONSEL (SCn_CTL[5:4]) = 00 and AUTOCEN (SCn_CTL[3]) = 0.
+     * |        |          |Note2: When operating in Smart Card mode, user must set UARTEN (SCn_UARTCTL[0]) = 0.
+     * |        |          |Note3: When UART mode is enabled, hardware will generate a reset to reset FIFO and internal state machine.
+     * |[5:4]   |WLS       |Word Length Selection
+     * |        |          |This field is used for select UART data length.
+     * |        |          |00 = Word length is 8 bits.
+     * |        |          |01 = Word length is 7 bits.
+     * |        |          |10 = Word length is 6 bits.
+     * |        |          |11 = Word length is 5 bits.
+     * |        |          |Note: In smart card mode, this WLS must be u201800'.
+     * |[6]     |PBOFF     |Parity Bit Disable Control
+     * |        |          |Sets this bit is used for disable parity check function.
+     * |        |          |0 = Parity bit is generated or checked between the last data word bit and stop bit of the serial data.
+     * |        |          |1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer.
+     * |        |          |Note: In smart card mode, this field must be u20180' (default setting is with parity bit).
+     * |[7]     |OPE       |Odd Parity Enable Bit
+     * |        |          |This is used for odd/even parity selection.
+     * |        |          |0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
+     * |        |          |1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
+     * |        |          |Note: This bit has effect only when PBOFF bit is u20180'.
+     * @var SC_T::ACTCTL
+     * Offset: 0x4C  SC Activation Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[4:0]   |T1EXT     |T1 Extend Time of Hardware Activation
+     * |        |          |This field provide the configurable cycles to extend the activation time T1 period.
+     * |        |          |The cycle scaling factor is 2048.
+     * |        |          |Extend cycles = (filled value * 2048) cycles.
+     * |        |          |Refer to SC activation sequence in Figure 6.17-4 SC Activation Sequence.
+     * |        |          |For example,
+     * |        |          |SCLK = 4MHz, each cycle = 0.25us,.
+     * |        |          |Filled 20 to this field
+     * |        |          |Extend time = 20 * 2048 * 0.25us = 10.24 ms.
+     * |        |          |Note: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3
+     */
+    __IO uint32_t DAT;                   /*!< [0x0000] SC Receive/Transmit Holding Buffer Register                      */
+    __IO uint32_t CTL;                   /*!< [0x0004] SC Control Register                                              */
+    __IO uint32_t ALTCTL;                /*!< [0x0008] SC Alternate Control Register                                    */
+    __IO uint32_t EGT;                   /*!< [0x000c] SC Extra Guard Time Register                                     */
+    __IO uint32_t RXTOUT;                /*!< [0x0010] SC Receive Buffer Time-out Counter Register                      */
+    __IO uint32_t ETUCTL;                /*!< [0x0014] SC Element Time Unit Control Register                            */
+    __IO uint32_t INTEN;                 /*!< [0x0018] SC Interrupt Enable Control Register                             */
+    __IO uint32_t INTSTS;                /*!< [0x001c] SC Interrupt Status Register                                     */
+    __IO uint32_t STATUS;                /*!< [0x0020] SC Transfer Status Register                                      */
+    __IO uint32_t PINCTL;                /*!< [0x0024] SC Pin Control State Register                                    */
+    __IO uint32_t TMRCTL0;               /*!< [0x0028] SC Internal Timer0 Control Register                              */
+    __IO uint32_t TMRCTL1;               /*!< [0x002c] SC Internal Timer1 Control Register                              */
+    __IO uint32_t TMRCTL2;               /*!< [0x0030] SC Internal Timer2 Control Register                              */
+    __IO uint32_t UARTCTL;               /*!< [0x0034] SC UART Mode Control Register                                    */
+    __I  uint32_t RESERVE0[5];
+    __IO uint32_t ACTCTL;                /*!< [0x004c] SC Activation Control Register                                   */
+
+} SC_T;
+
+/**
+    @addtogroup SC_CONST SC Bit Field Definition
+    Constant Definitions for SC Controller
+  @{
+*/
+
+#define SC_DAT_DAT_Pos                   (0)                                               /*!< SC_T::DAT: DAT Position                */
+#define SC_DAT_DAT_Msk                   (0xfful << SC_DAT_DAT_Pos)                        /*!< SC_T::DAT: DAT Mask                    */
+
+#define SC_CTL_SCEN_Pos                  (0)                                               /*!< SC_T::CTL: SCEN Position               */
+#define SC_CTL_SCEN_Msk                  (0x1ul << SC_CTL_SCEN_Pos)                        /*!< SC_T::CTL: SCEN Mask                   */
+
+#define SC_CTL_RXOFF_Pos                 (1)                                               /*!< SC_T::CTL: RXOFF Position              */
+#define SC_CTL_RXOFF_Msk                 (0x1ul << SC_CTL_RXOFF_Pos)                       /*!< SC_T::CTL: RXOFF Mask                  */
+
+#define SC_CTL_TXOFF_Pos                 (2)                                               /*!< SC_T::CTL: TXOFF Position              */
+#define SC_CTL_TXOFF_Msk                 (0x1ul << SC_CTL_TXOFF_Pos)                       /*!< SC_T::CTL: TXOFF Mask                  */
+
+#define SC_CTL_AUTOCEN_Pos               (3)                                               /*!< SC_T::CTL: AUTOCEN Position            */
+#define SC_CTL_AUTOCEN_Msk               (0x1ul << SC_CTL_AUTOCEN_Pos)                     /*!< SC_T::CTL: AUTOCEN Mask                */
+
+#define SC_CTL_CONSEL_Pos                (4)                                               /*!< SC_T::CTL: CONSEL Position             */
+#define SC_CTL_CONSEL_Msk                (0x3ul << SC_CTL_CONSEL_Pos)                      /*!< SC_T::CTL: CONSEL Mask                 */
+
+#define SC_CTL_RXTRGLV_Pos               (6)                                               /*!< SC_T::CTL: RXTRGLV Position            */
+#define SC_CTL_RXTRGLV_Msk               (0x3ul << SC_CTL_RXTRGLV_Pos)                     /*!< SC_T::CTL: RXTRGLV Mask                */
+
+#define SC_CTL_BGT_Pos                   (8)                                               /*!< SC_T::CTL: BGT Position                */
+#define SC_CTL_BGT_Msk                   (0x1ful << SC_CTL_BGT_Pos)                        /*!< SC_T::CTL: BGT Mask                    */
+
+#define SC_CTL_TMRSEL_Pos                (13)                                              /*!< SC_T::CTL: TMRSEL Position             */
+#define SC_CTL_TMRSEL_Msk                (0x3ul << SC_CTL_TMRSEL_Pos)                      /*!< SC_T::CTL: TMRSEL Mask                 */
+
+#define SC_CTL_NSB_Pos                   (15)                                              /*!< SC_T::CTL: NSB Position                */
+#define SC_CTL_NSB_Msk                   (0x1ul << SC_CTL_NSB_Pos)                         /*!< SC_T::CTL: NSB Mask                    */
+
+#define SC_CTL_RXRTY_Pos                 (16)                                              /*!< SC_T::CTL: RXRTY Position              */
+#define SC_CTL_RXRTY_Msk                 (0x7ul << SC_CTL_RXRTY_Pos)                       /*!< SC_T::CTL: RXRTY Mask                  */
+
+#define SC_CTL_RXRTYEN_Pos               (19)                                              /*!< SC_T::CTL: RXRTYEN Position            */
+#define SC_CTL_RXRTYEN_Msk               (0x1ul << SC_CTL_RXRTYEN_Pos)                     /*!< SC_T::CTL: RXRTYEN Mask                */
+
+#define SC_CTL_TXRTY_Pos                 (20)                                              /*!< SC_T::CTL: TXRTY Position              */
+#define SC_CTL_TXRTY_Msk                 (0x7ul << SC_CTL_TXRTY_Pos)                       /*!< SC_T::CTL: TXRTY Mask                  */
+
+#define SC_CTL_TXRTYEN_Pos               (23)                                              /*!< SC_T::CTL: TXRTYEN Position            */
+#define SC_CTL_TXRTYEN_Msk               (0x1ul << SC_CTL_TXRTYEN_Pos)                     /*!< SC_T::CTL: TXRTYEN Mask                */
+
+#define SC_CTL_CDDBSEL_Pos               (24)                                              /*!< SC_T::CTL: CDDBSEL Position            */
+#define SC_CTL_CDDBSEL_Msk               (0x3ul << SC_CTL_CDDBSEL_Pos)                     /*!< SC_T::CTL: CDDBSEL Mask                */
+
+#define SC_CTL_CDLV_Pos                  (26)                                              /*!< SC_T::CTL: CDLV Position               */
+#define SC_CTL_CDLV_Msk                  (0x1ul << SC_CTL_CDLV_Pos)                        /*!< SC_T::CTL: CDLV Mask                   */
+
+#define SC_CTL_SYNC_Pos                  (30)                                              /*!< SC_T::CTL: SYNC Position               */
+#define SC_CTL_SYNC_Msk                  (0x1ul << SC_CTL_SYNC_Pos)                        /*!< SC_T::CTL: SYNC Mask                   */
+
+#define SC_ALTCTL_TXRST_Pos              (0)                                               /*!< SC_T::ALTCTL: TXRST Position           */
+#define SC_ALTCTL_TXRST_Msk              (0x1ul << SC_ALTCTL_TXRST_Pos)                    /*!< SC_T::ALTCTL: TXRST Mask               */
+
+#define SC_ALTCTL_RXRST_Pos              (1)                                               /*!< SC_T::ALTCTL: RXRST Position           */
+#define SC_ALTCTL_RXRST_Msk              (0x1ul << SC_ALTCTL_RXRST_Pos)                    /*!< SC_T::ALTCTL: RXRST Mask               */
+
+#define SC_ALTCTL_DACTEN_Pos             (2)                                               /*!< SC_T::ALTCTL: DACTEN Position          */
+#define SC_ALTCTL_DACTEN_Msk             (0x1ul << SC_ALTCTL_DACTEN_Pos)                   /*!< SC_T::ALTCTL: DACTEN Mask              */
+
+#define SC_ALTCTL_ACTEN_Pos              (3)                                               /*!< SC_T::ALTCTL: ACTEN Position           */
+#define SC_ALTCTL_ACTEN_Msk              (0x1ul << SC_ALTCTL_ACTEN_Pos)                    /*!< SC_T::ALTCTL: ACTEN Mask               */
+
+#define SC_ALTCTL_WARSTEN_Pos            (4)                                               /*!< SC_T::ALTCTL: WARSTEN Position         */
+#define SC_ALTCTL_WARSTEN_Msk            (0x1ul << SC_ALTCTL_WARSTEN_Pos)                  /*!< SC_T::ALTCTL: WARSTEN Mask             */
+
+#define SC_ALTCTL_CNTEN0_Pos             (5)                                               /*!< SC_T::ALTCTL: CNTEN0 Position          */
+#define SC_ALTCTL_CNTEN0_Msk             (0x1ul << SC_ALTCTL_CNTEN0_Pos)                   /*!< SC_T::ALTCTL: CNTEN0 Mask              */
+
+#define SC_ALTCTL_CNTEN1_Pos             (6)                                               /*!< SC_T::ALTCTL: CNTEN1 Position          */
+#define SC_ALTCTL_CNTEN1_Msk             (0x1ul << SC_ALTCTL_CNTEN1_Pos)                   /*!< SC_T::ALTCTL: CNTEN1 Mask              */
+
+#define SC_ALTCTL_CNTEN2_Pos             (7)                                               /*!< SC_T::ALTCTL: CNTEN2 Position          */
+#define SC_ALTCTL_CNTEN2_Msk             (0x1ul << SC_ALTCTL_CNTEN2_Pos)                   /*!< SC_T::ALTCTL: CNTEN2 Mask              */
+
+#define SC_ALTCTL_INITSEL_Pos            (8)                                               /*!< SC_T::ALTCTL: INITSEL Position         */
+#define SC_ALTCTL_INITSEL_Msk            (0x3ul << SC_ALTCTL_INITSEL_Pos)                  /*!< SC_T::ALTCTL: INITSEL Mask             */
+
+#define SC_ALTCTL_ADACEN_Pos             (11)                                              /*!< SC_T::ALTCTL: ADACEN Position          */
+#define SC_ALTCTL_ADACEN_Msk             (0x1ul << SC_ALTCTL_ADACEN_Pos)                   /*!< SC_T::ALTCTL: ADACEN Mask              */
+
+#define SC_ALTCTL_RXBGTEN_Pos            (12)                                              /*!< SC_T::ALTCTL: RXBGTEN Position         */
+#define SC_ALTCTL_RXBGTEN_Msk            (0x1ul << SC_ALTCTL_RXBGTEN_Pos)                  /*!< SC_T::ALTCTL: RXBGTEN Mask             */
+
+#define SC_ALTCTL_ACTSTS0_Pos            (13)                                              /*!< SC_T::ALTCTL: ACTSTS0 Position         */
+#define SC_ALTCTL_ACTSTS0_Msk            (0x1ul << SC_ALTCTL_ACTSTS0_Pos)                  /*!< SC_T::ALTCTL: ACTSTS0 Mask             */
+
+#define SC_ALTCTL_ACTSTS1_Pos            (14)                                              /*!< SC_T::ALTCTL: ACTSTS1 Position         */
+#define SC_ALTCTL_ACTSTS1_Msk            (0x1ul << SC_ALTCTL_ACTSTS1_Pos)                  /*!< SC_T::ALTCTL: ACTSTS1 Mask             */
+
+#define SC_ALTCTL_ACTSTS2_Pos            (15)                                              /*!< SC_T::ALTCTL: ACTSTS2 Position         */
+#define SC_ALTCTL_ACTSTS2_Msk            (0x1ul << SC_ALTCTL_ACTSTS2_Pos)                  /*!< SC_T::ALTCTL: ACTSTS2 Mask             */
+
+#define SC_ALTCTL_SYNC_Pos               (31)                                              /*!< SC_T::ALTCTL: SYNC Position            */
+#define SC_ALTCTL_SYNC_Msk               (0x1ul << SC_ALTCTL_SYNC_Pos)                     /*!< SC_T::ALTCTL: SYNC Mask                */
+
+#define SC_EGT_EGT_Pos                   (0)                                               /*!< SC_T::EGT: EGT Position                */
+#define SC_EGT_EGT_Msk                   (0xfful << SC_EGT_EGT_Pos)                        /*!< SC_T::EGT: EGT Mask                    */
+
+#define SC_RXTOUT_RFTM_Pos               (0)                                               /*!< SC_T::RXTOUT: RFTM Position            */
+#define SC_RXTOUT_RFTM_Msk               (0x1fful << SC_RXTOUT_RFTM_Pos)                   /*!< SC_T::RXTOUT: RFTM Mask                */
+
+#define SC_ETUCTL_ETURDIV_Pos            (0)                                               /*!< SC_T::ETUCTL: ETURDIV Position         */
+#define SC_ETUCTL_ETURDIV_Msk            (0xffful << SC_ETUCTL_ETURDIV_Pos)                /*!< SC_T::ETUCTL: ETURDIV Mask             */
+
+#define SC_INTEN_RDAIEN_Pos              (0)                                               /*!< SC_T::INTEN: RDAIEN Position           */
+#define SC_INTEN_RDAIEN_Msk              (0x1ul << SC_INTEN_RDAIEN_Pos)                    /*!< SC_T::INTEN: RDAIEN Mask               */
+
+#define SC_INTEN_TBEIEN_Pos              (1)                                               /*!< SC_T::INTEN: TBEIEN Position           */
+#define SC_INTEN_TBEIEN_Msk              (0x1ul << SC_INTEN_TBEIEN_Pos)                    /*!< SC_T::INTEN: TBEIEN Mask               */
+
+#define SC_INTEN_TERRIEN_Pos             (2)                                               /*!< SC_T::INTEN: TERRIEN Position          */
+#define SC_INTEN_TERRIEN_Msk             (0x1ul << SC_INTEN_TERRIEN_Pos)                   /*!< SC_T::INTEN: TERRIEN Mask              */
+
+#define SC_INTEN_TMR0IEN_Pos             (3)                                               /*!< SC_T::INTEN: TMR0IEN Position          */
+#define SC_INTEN_TMR0IEN_Msk             (0x1ul << SC_INTEN_TMR0IEN_Pos)                   /*!< SC_T::INTEN: TMR0IEN Mask              */
+
+#define SC_INTEN_TMR1IEN_Pos             (4)                                               /*!< SC_T::INTEN: TMR1IEN Position          */
+#define SC_INTEN_TMR1IEN_Msk             (0x1ul << SC_INTEN_TMR1IEN_Pos)                   /*!< SC_T::INTEN: TMR1IEN Mask              */
+
+#define SC_INTEN_TMR2IEN_Pos             (5)                                               /*!< SC_T::INTEN: TMR2IEN Position          */
+#define SC_INTEN_TMR2IEN_Msk             (0x1ul << SC_INTEN_TMR2IEN_Pos)                   /*!< SC_T::INTEN: TMR2IEN Mask              */
+
+#define SC_INTEN_BGTIEN_Pos              (6)                                               /*!< SC_T::INTEN: BGTIEN Position           */
+#define SC_INTEN_BGTIEN_Msk              (0x1ul << SC_INTEN_BGTIEN_Pos)                    /*!< SC_T::INTEN: BGTIEN Mask               */
+
+#define SC_INTEN_CDIEN_Pos               (7)                                               /*!< SC_T::INTEN: CDIEN Position            */
+#define SC_INTEN_CDIEN_Msk               (0x1ul << SC_INTEN_CDIEN_Pos)                     /*!< SC_T::INTEN: CDIEN Mask                */
+
+#define SC_INTEN_INITIEN_Pos             (8)                                               /*!< SC_T::INTEN: INITIEN Position          */
+#define SC_INTEN_INITIEN_Msk             (0x1ul << SC_INTEN_INITIEN_Pos)                   /*!< SC_T::INTEN: INITIEN Mask              */
+
+#define SC_INTEN_RXTOIEN_Pos             (9)                                               /*!< SC_T::INTEN: RXTOIEN Position          */
+#define SC_INTEN_RXTOIEN_Msk             (0x1ul << SC_INTEN_RXTOIEN_Pos)                   /*!< SC_T::INTEN: RXTOIEN Mask              */
+
+#define SC_INTEN_ACERRIEN_Pos            (10)                                              /*!< SC_T::INTEN: ACERRIEN Position         */
+#define SC_INTEN_ACERRIEN_Msk            (0x1ul << SC_INTEN_ACERRIEN_Pos)                  /*!< SC_T::INTEN: ACERRIEN Mask             */
+
+#define SC_INTSTS_RDAIF_Pos              (0)                                               /*!< SC_T::INTSTS: RDAIF Position           */
+#define SC_INTSTS_RDAIF_Msk              (0x1ul << SC_INTSTS_RDAIF_Pos)                    /*!< SC_T::INTSTS: RDAIF Mask               */
+
+#define SC_INTSTS_TBEIF_Pos              (1)                                               /*!< SC_T::INTSTS: TBEIF Position           */
+#define SC_INTSTS_TBEIF_Msk              (0x1ul << SC_INTSTS_TBEIF_Pos)                    /*!< SC_T::INTSTS: TBEIF Mask               */
+
+#define SC_INTSTS_TERRIF_Pos             (2)                                               /*!< SC_T::INTSTS: TERRIF Position          */
+#define SC_INTSTS_TERRIF_Msk             (0x1ul << SC_INTSTS_TERRIF_Pos)                   /*!< SC_T::INTSTS: TERRIF Mask              */
+
+#define SC_INTSTS_TMR0IF_Pos             (3)                                               /*!< SC_T::INTSTS: TMR0IF Position          */
+#define SC_INTSTS_TMR0IF_Msk             (0x1ul << SC_INTSTS_TMR0IF_Pos)                   /*!< SC_T::INTSTS: TMR0IF Mask              */
+
+#define SC_INTSTS_TMR1IF_Pos             (4)                                               /*!< SC_T::INTSTS: TMR1IF Position          */
+#define SC_INTSTS_TMR1IF_Msk             (0x1ul << SC_INTSTS_TMR1IF_Pos)                   /*!< SC_T::INTSTS: TMR1IF Mask              */
+
+#define SC_INTSTS_TMR2IF_Pos             (5)                                               /*!< SC_T::INTSTS: TMR2IF Position          */
+#define SC_INTSTS_TMR2IF_Msk             (0x1ul << SC_INTSTS_TMR2IF_Pos)                   /*!< SC_T::INTSTS: TMR2IF Mask              */
+
+#define SC_INTSTS_BGTIF_Pos              (6)                                               /*!< SC_T::INTSTS: BGTIF Position           */
+#define SC_INTSTS_BGTIF_Msk              (0x1ul << SC_INTSTS_BGTIF_Pos)                    /*!< SC_T::INTSTS: BGTIF Mask               */
+
+#define SC_INTSTS_CDIF_Pos               (7)                                               /*!< SC_T::INTSTS: CDIF Position            */
+#define SC_INTSTS_CDIF_Msk               (0x1ul << SC_INTSTS_CDIF_Pos)                     /*!< SC_T::INTSTS: CDIF Mask                */
+
+#define SC_INTSTS_INITIF_Pos             (8)                                               /*!< SC_T::INTSTS: INITIF Position          */
+#define SC_INTSTS_INITIF_Msk             (0x1ul << SC_INTSTS_INITIF_Pos)                   /*!< SC_T::INTSTS: INITIF Mask              */
+
+#define SC_INTSTS_RXTOIF_Pos             (9)                                               /*!< SC_T::INTSTS: RXTOIF Position          */
+#define SC_INTSTS_RXTOIF_Msk             (0x1ul << SC_INTSTS_RXTOIF_Pos)                   /*!< SC_T::INTSTS: RXTOIF Mask              */
+
+#define SC_INTSTS_ACERRIF_Pos            (10)                                              /*!< SC_T::INTSTS: ACERRIF Position         */
+#define SC_INTSTS_ACERRIF_Msk            (0x1ul << SC_INTSTS_ACERRIF_Pos)                  /*!< SC_T::INTSTS: ACERRIF Mask             */
+
+#define SC_STATUS_RXOV_Pos               (0)                                               /*!< SC_T::STATUS: RXOV Position            */
+#define SC_STATUS_RXOV_Msk               (0x1ul << SC_STATUS_RXOV_Pos)                     /*!< SC_T::STATUS: RXOV Mask                */
+
+#define SC_STATUS_RXEMPTY_Pos            (1)                                               /*!< SC_T::STATUS: RXEMPTY Position         */
+#define SC_STATUS_RXEMPTY_Msk            (0x1ul << SC_STATUS_RXEMPTY_Pos)                  /*!< SC_T::STATUS: RXEMPTY Mask             */
+
+#define SC_STATUS_RXFULL_Pos             (2)                                               /*!< SC_T::STATUS: RXFULL Position          */
+#define SC_STATUS_RXFULL_Msk             (0x1ul << SC_STATUS_RXFULL_Pos)                   /*!< SC_T::STATUS: RXFULL Mask              */
+
+#define SC_STATUS_PEF_Pos                (4)                                               /*!< SC_T::STATUS: PEF Position             */
+#define SC_STATUS_PEF_Msk                (0x1ul << SC_STATUS_PEF_Pos)                      /*!< SC_T::STATUS: PEF Mask                 */
+
+#define SC_STATUS_FEF_Pos                (5)                                               /*!< SC_T::STATUS: FEF Position             */
+#define SC_STATUS_FEF_Msk                (0x1ul << SC_STATUS_FEF_Pos)                      /*!< SC_T::STATUS: FEF Mask                 */
+
+#define SC_STATUS_BEF_Pos                (6)                                               /*!< SC_T::STATUS: BEF Position             */
+#define SC_STATUS_BEF_Msk                (0x1ul << SC_STATUS_BEF_Pos)                      /*!< SC_T::STATUS: BEF Mask                 */
+
+#define SC_STATUS_TXOV_Pos               (8)                                               /*!< SC_T::STATUS: TXOV Position            */
+#define SC_STATUS_TXOV_Msk               (0x1ul << SC_STATUS_TXOV_Pos)                     /*!< SC_T::STATUS: TXOV Mask                */
+
+#define SC_STATUS_TXEMPTY_Pos            (9)                                               /*!< SC_T::STATUS: TXEMPTY Position         */
+#define SC_STATUS_TXEMPTY_Msk            (0x1ul << SC_STATUS_TXEMPTY_Pos)                  /*!< SC_T::STATUS: TXEMPTY Mask             */
+
+#define SC_STATUS_TXFULL_Pos             (10)                                              /*!< SC_T::STATUS: TXFULL Position          */
+#define SC_STATUS_TXFULL_Msk             (0x1ul << SC_STATUS_TXFULL_Pos)                   /*!< SC_T::STATUS: TXFULL Mask              */
+
+#define SC_STATUS_CREMOVE_Pos            (11)                                              /*!< SC_T::STATUS: CREMOVE Position         */
+#define SC_STATUS_CREMOVE_Msk            (0x1ul << SC_STATUS_CREMOVE_Pos)                  /*!< SC_T::STATUS: CREMOVE Mask             */
+
+#define SC_STATUS_CINSERT_Pos            (12)                                              /*!< SC_T::STATUS: CINSERT Position         */
+#define SC_STATUS_CINSERT_Msk            (0x1ul << SC_STATUS_CINSERT_Pos)                  /*!< SC_T::STATUS: CINSERT Mask             */
+
+#define SC_STATUS_CDPINSTS_Pos           (13)                                              /*!< SC_T::STATUS: CDPINSTS Position        */
+#define SC_STATUS_CDPINSTS_Msk           (0x1ul << SC_STATUS_CDPINSTS_Pos)                 /*!< SC_T::STATUS: CDPINSTS Mask            */
+
+#define SC_STATUS_RXPOINT_Pos            (16)                                              /*!< SC_T::STATUS: RXPOINT Position         */
+#define SC_STATUS_RXPOINT_Msk            (0x7ul << SC_STATUS_RXPOINT_Pos)                  /*!< SC_T::STATUS: RXPOINT Mask             */
+
+#define SC_STATUS_RXRERR_Pos             (21)                                              /*!< SC_T::STATUS: RXRERR Position          */
+#define SC_STATUS_RXRERR_Msk             (0x1ul << SC_STATUS_RXRERR_Pos)                   /*!< SC_T::STATUS: RXRERR Mask              */
+
+#define SC_STATUS_RXOVERR_Pos            (22)                                              /*!< SC_T::STATUS: RXOVERR Position         */
+#define SC_STATUS_RXOVERR_Msk            (0x1ul << SC_STATUS_RXOVERR_Pos)                  /*!< SC_T::STATUS: RXOVERR Mask             */
+
+#define SC_STATUS_RXACT_Pos              (23)                                              /*!< SC_T::STATUS: RXACT Position           */
+#define SC_STATUS_RXACT_Msk              (0x1ul << SC_STATUS_RXACT_Pos)                    /*!< SC_T::STATUS: RXACT Mask               */
+
+#define SC_STATUS_TXPOINT_Pos            (24)                                              /*!< SC_T::STATUS: TXPOINT Position         */
+#define SC_STATUS_TXPOINT_Msk            (0x7ul << SC_STATUS_TXPOINT_Pos)                  /*!< SC_T::STATUS: TXPOINT Mask             */
+
+#define SC_STATUS_TXRERR_Pos             (29)                                              /*!< SC_T::STATUS: TXRERR Position          */
+#define SC_STATUS_TXRERR_Msk             (0x1ul << SC_STATUS_TXRERR_Pos)                   /*!< SC_T::STATUS: TXRERR Mask              */
+
+#define SC_STATUS_TXOVERR_Pos            (30)                                              /*!< SC_T::STATUS: TXOVERR Position         */
+#define SC_STATUS_TXOVERR_Msk            (0x1ul << SC_STATUS_TXOVERR_Pos)                  /*!< SC_T::STATUS: TXOVERR Mask             */
+
+#define SC_STATUS_TXACT_Pos              (31)                                              /*!< SC_T::STATUS: TXACT Position           */
+#define SC_STATUS_TXACT_Msk              (0x1ul << SC_STATUS_TXACT_Pos)                    /*!< SC_T::STATUS: TXACT Mask               */
+
+#define SC_PINCTL_PWREN_Pos              (0)                                               /*!< SC_T::PINCTL: PWREN Position           */
+#define SC_PINCTL_PWREN_Msk              (0x1ul << SC_PINCTL_PWREN_Pos)                    /*!< SC_T::PINCTL: PWREN Mask               */
+
+#define SC_PINCTL_RSTEN_Pos              (1)                                               /*!< SC_T::PINCTL: RSTEN Position           */
+#define SC_PINCTL_RSTEN_Msk              (0x1ul << SC_PINCTL_RSTEN_Pos)                    /*!< SC_T::PINCTL: RSTEN Mask               */
+
+#define SC_PINCTL_CSTOPLV_Pos            (5)                                               /*!< SC_T::PINCTL: CSTOPLV Position         */
+#define SC_PINCTL_CSTOPLV_Msk            (0x1ul << SC_PINCTL_CSTOPLV_Pos)                  /*!< SC_T::PINCTL: CSTOPLV Mask             */
+
+#define SC_PINCTL_CLKKEEP_Pos            (6)                                               /*!< SC_T::PINCTL: CLKKEEP Position         */
+#define SC_PINCTL_CLKKEEP_Msk            (0x1ul << SC_PINCTL_CLKKEEP_Pos)                  /*!< SC_T::PINCTL: CLKKEEP Mask             */
+
+#define SC_PINCTL_SCDATA_Pos             (9)                                               /*!< SC_T::PINCTL: SCDATA Position          */
+#define SC_PINCTL_SCDATA_Msk             (0x1ul << SC_PINCTL_SCDATA_Pos)                   /*!< SC_T::PINCTL: SCDATA Mask              */
+
+#define SC_PINCTL_PWRINV_Pos             (11)                                              /*!< SC_T::PINCTL: PWRINV Position          */
+#define SC_PINCTL_PWRINV_Msk             (0x1ul << SC_PINCTL_PWRINV_Pos)                   /*!< SC_T::PINCTL: PWRINV Mask              */
+
+#define SC_PINCTL_DATASTS_Pos            (16)                                              /*!< SC_T::PINCTL: DATASTS Position         */
+#define SC_PINCTL_DATASTS_Msk            (0x1ul << SC_PINCTL_DATASTS_Pos)                  /*!< SC_T::PINCTL: DATASTS Mask             */
+
+#define SC_PINCTL_PWRSTS_Pos             (17)                                              /*!< SC_T::PINCTL: PWRSTS Position          */
+#define SC_PINCTL_PWRSTS_Msk             (0x1ul << SC_PINCTL_PWRSTS_Pos)                   /*!< SC_T::PINCTL: PWRSTS Mask              */
+
+#define SC_PINCTL_RSTSTS_Pos             (18)                                              /*!< SC_T::PINCTL: RSTSTS Position          */
+#define SC_PINCTL_RSTSTS_Msk             (0x1ul << SC_PINCTL_RSTSTS_Pos)                   /*!< SC_T::PINCTL: RSTSTS Mask              */
+
+#define SC_PINCTL_SYNC_Pos               (30)                                              /*!< SC_T::PINCTL: SYNC Position            */
+#define SC_PINCTL_SYNC_Msk               (0x1ul << SC_PINCTL_SYNC_Pos)                     /*!< SC_T::PINCTL: SYNC Mask                */
+
+#define SC_TMRCTL0_CNT_Pos               (0)                                               /*!< SC_T::TMRCTL0: CNT Position            */
+#define SC_TMRCTL0_CNT_Msk               (0xfffffful << SC_TMRCTL0_CNT_Pos)                /*!< SC_T::TMRCTL0: CNT Mask                */
+
+#define SC_TMRCTL0_OPMODE_Pos            (24)                                              /*!< SC_T::TMRCTL0: OPMODE Position         */
+#define SC_TMRCTL0_OPMODE_Msk            (0xful << SC_TMRCTL0_OPMODE_Pos)                  /*!< SC_T::TMRCTL0: OPMODE Mask             */
+
+#define SC_TMRCTL0_SYNC_Pos              (31)                                              /*!< SC_T::TMRCTL0: SYNC Position           */
+#define SC_TMRCTL0_SYNC_Msk              (0x1ul << SC_TMRCTL0_SYNC_Pos)                    /*!< SC_T::TMRCTL0: SYNC Mask               */
+
+#define SC_TMRCTL1_CNT_Pos               (0)                                               /*!< SC_T::TMRCTL1: CNT Position            */
+#define SC_TMRCTL1_CNT_Msk               (0xfful << SC_TMRCTL1_CNT_Pos)                    /*!< SC_T::TMRCTL1: CNT Mask                */
+
+#define SC_TMRCTL1_OPMODE_Pos            (24)                                              /*!< SC_T::TMRCTL1: OPMODE Position         */
+#define SC_TMRCTL1_OPMODE_Msk            (0xful << SC_TMRCTL1_OPMODE_Pos)                  /*!< SC_T::TMRCTL1: OPMODE Mask             */
+
+#define SC_TMRCTL1_SYNC_Pos              (31)                                              /*!< SC_T::TMRCTL1: SYNC Position           */
+#define SC_TMRCTL1_SYNC_Msk              (0x1ul << SC_TMRCTL1_SYNC_Pos)                    /*!< SC_T::TMRCTL1: SYNC Mask               */
+
+#define SC_TMRCTL2_CNT_Pos               (0)                                               /*!< SC_T::TMRCTL2: CNT Position            */
+#define SC_TMRCTL2_CNT_Msk               (0xfful << SC_TMRCTL2_CNT_Pos)                    /*!< SC_T::TMRCTL2: CNT Mask                */
+
+#define SC_TMRCTL2_OPMODE_Pos            (24)                                              /*!< SC_T::TMRCTL2: OPMODE Position         */
+#define SC_TMRCTL2_OPMODE_Msk            (0xful << SC_TMRCTL2_OPMODE_Pos)                  /*!< SC_T::TMRCTL2: OPMODE Mask             */
+
+#define SC_TMRCTL2_SYNC_Pos              (31)                                              /*!< SC_T::TMRCTL2: SYNC Position           */
+#define SC_TMRCTL2_SYNC_Msk              (0x1ul << SC_TMRCTL2_SYNC_Pos)                    /*!< SC_T::TMRCTL2: SYNC Mask               */
+
+#define SC_UARTCTL_UARTEN_Pos            (0)                                               /*!< SC_T::UARTCTL: UARTEN Position         */
+#define SC_UARTCTL_UARTEN_Msk            (0x1ul << SC_UARTCTL_UARTEN_Pos)                  /*!< SC_T::UARTCTL: UARTEN Mask             */
+
+#define SC_UARTCTL_WLS_Pos               (4)                                               /*!< SC_T::UARTCTL: WLS Position            */
+#define SC_UARTCTL_WLS_Msk               (0x3ul << SC_UARTCTL_WLS_Pos)                     /*!< SC_T::UARTCTL: WLS Mask                */
+
+#define SC_UARTCTL_PBOFF_Pos             (6)                                               /*!< SC_T::UARTCTL: PBOFF Position          */
+#define SC_UARTCTL_PBOFF_Msk             (0x1ul << SC_UARTCTL_PBOFF_Pos)                   /*!< SC_T::UARTCTL: PBOFF Mask              */
+
+#define SC_UARTCTL_OPE_Pos               (7)                                               /*!< SC_T::UARTCTL: OPE Position            */
+#define SC_UARTCTL_OPE_Msk               (0x1ul << SC_UARTCTL_OPE_Pos)                     /*!< SC_T::UARTCTL: OPE Mask                */
+
+#define SC_ACTCTL_T1EXT_Pos              (0)                                               /*!< SC_T::ACTCTL: T1EXT Position           */
+#define SC_ACTCTL_T1EXT_Msk              (0x1ful << SC_ACTCTL_T1EXT_Pos)                   /*!< SC_T::ACTCTL: T1EXT Mask               */
+
+/**@}*/ /* SC_CONST */
+/**@}*/ /* end of SC register group */
+/**@}*/ /* end of REGISTER group */
+
+#endif /* __SC_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/scu_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/scu_reg.h
new file mode 100644
index 0000000000..3ba0b96d35
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/scu_reg.h
@@ -0,0 +1,2699 @@
+/**************************************************************************//**
+ * @file     scu_reg.h
+ * @version  V1.00
+ * @brief    SCU register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __SCU_REG_H__
+#define __SCU_REG_H__
+
+/******************************************************************************/
+/*                Device Specific Peripheral registers structures             */
+/******************************************************************************/
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+
+/*---------------------- Booting Flag -------------------------*/
+/**
+    @addtogroup BTF Booting Flag
+    Memory Mapped Structure for BTF Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var BTF_T::BTF
+     * Offset: 0x00  Booting Flag Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BL2       |BL2 Flag
+     * |        |          |Indicating the CPU is running at BL2
+     */
+    __IO uint32_t BTF;                   /*!< [0x0000] Booting Flag Register                                            */
+
+} BTF_T;
+
+/**
+    @addtogroup BTF_CONST BTF Bit Field Definition
+    Constant Definitions for BTF Controller
+  @{
+*/
+
+#define BTF_BTF_BL2_Pos                  (0)                                               /*!< BTF_T::BTF: BL2 Position               */
+#define BTF_BTF_BL2_Msk                  (0x1ul << BTF_BTF_BL2_Pos)                        /*!< BTF_T::BTF: BL2 Mask                   */
+
+/**@}*/ /* BTF_CONST */
+/**@}*/ /* end of BTF register group */
+
+
+/*---------------------- Debug Protection Mechanism -------------------------*/
+/**
+    @addtogroup DPM Debug Protection Mechanism(DPM)
+    Memory Mapped Structure for DPM Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var DPM_T::CTL
+     * Offset: 0x00  Secure DPM Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |DBGDIS    |Set Secure DPM Debug Disable Bit
+     * |        |          |When this bit is read as zero, it can be write to one to configure the Secure DPM DBGDIS bit (DBGDISS).
+     * |        |          |When write:
+     * |        |          |0 = No operation.
+     * |        |          |1 = Trigger the process to set DBGDISS configuration bit.
+     * |        |          |Note: This bit can be set to 1 but cannot be cleared to 0.
+     * |[1]     |LOCK      |Set Secure DPM Debug Lock Bit
+     * |        |          |When this bit is read as zero, it can be write to one to configure the Secure DPM LOCK bit (LOCKS).
+     * |        |          |When write:
+     * |        |          |0 = No operation.
+     * |        |          |1 = Trigger the process to set LOCKS configuration bit.
+     * |        |          |Note: This bit can be set to 1 but cannot be cleared to 0.
+     * |[2]     |PWCMP     |Secure DPM Password Compare Bit
+     * |        |          |Set to enter the process of compare Secure DPM password.
+     * |        |          |0 = No operation.
+     * |        |          |1 = Compare Secure DPM password.
+     * |        |          |Note: This bit will be cleared after the comparison process is finished.
+     * |[3]     |PWUPD     |Secure DPM Password Update Bit
+     * |        |          |Set to enter the process of updating Secure DPM password.
+     * |        |          |0 = No operation.
+     * |        |          |1 = Update Secure DPM password.
+     * |        |          |Note 1: This bit should be set with PWCMP equal to 0.
+     * |        |          |Note 2: This bit will be cleared after the update process is finished.
+     * |[8]     |INTEN     |DPM Interrupt Enable Bit
+     * |        |          |0 = DPM interrupt function Enabled.
+     * |        |          |1 = DPM interrupt function Disabled.
+     * |[12]    |DACCWDIS  |Secure DPM Debug Write Access Disable Bit
+     * |        |          |This bit disables the writability of external debugger to Secure DPM registers for debug authentication.
+     * |        |          |0 = External debugger can write Secure DPM registers.
+     * |        |          |1 = External debugger cannot write Secure DPM registers.
+     * |[13]    |DACCDIS   |Debug Access Disable Bit
+     * |        |          |This bit disables the accessibility of external debugger to all DPM registers.
+     * |        |          |0 = External debugger can read/write DPM registers.
+     * |        |          |1 = External debugger cannot read/write DPM registers.
+     * |[31:24] |WVCODE    |Write Verify Code and Read Verify Code
+     * |        |RVCODE    |Read operation:
+     * |        |          |0xA5 = The read access for DPM_CTL is correct.
+     * |        |          |Others = The read access for DPM_CTL is incorrect.
+     * |        |          |Write operation:
+     * |        |          |0x5A = The write verify code, 0x5A, is needed to do a valid write to DPM_CTL.
+     * |        |          |Others = Invalid write verify code.
+     * @var DPM_T::STS
+     * Offset: 0x04  Secure DPM Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BUSY      |DPM Busy Flag (Read Only)
+     * |        |          |This bit indicates the DPM is busy.
+     * |        |          |0 = DPM is not busy and writing to any register is accepted.
+     * |        |          |1 = DPM is busy and other bits in DPM_STS register are not valid and writing to any register is ignored.
+     * |[1]     |INT       |DPM Interrupt Flag (Read Only)
+     * |        |          |This bit indicates the interrupt is triggered.
+     * |        |          |0 = Interrupt is not enabled or no password comparison flag is set.
+     * |        |          |1 = Interrupt is enabled and PWCERR flag in either DPM_STS or DPM_NSSTS register is not cleared.
+     * |        |          |Note: This bit is cleared automatically when PWCERR flag in both DPM_STS and DPM_NSSTS are zero.
+     * |[4]     |PWCERR    |Secure DPM Password Compared Error Flag
+     * |        |          |This bit indicates the result of Secure DPM password comparison.
+     * |        |          |When read:
+     * |        |          |0 = The result of Secure DPM password is correct.
+     * |        |          |1 = The result of Seucre DPM password is incorrect.
+     * |        |          |Note: This flag is write-one-clear.
+     * |[5]     |PWUOK     |Secure DPM Password Updated Flag
+     * |        |          |This bit indicates Secure DPM password has been updated successfully.
+     * |        |          |When read:
+     * |        |          |0 = No successful updating process has happened.
+     * |        |          |1 = There is at least one successful updating process since last clearing of this bit.
+     * |        |          |Note: This flag is write-one-clear.
+     * |[6]     |PWFMAX    |Secure DPM Password Fail Times Maximum Reached Flag (Read Only)
+     * |        |          |This bit indicates if the fail times of comparing Secure DPM password reached max times.
+     * |        |          |0 = Max time has not reached and Secure DPM password comparison can be triggered.
+     * |        |          |1 = Max time reached and Secure DPM password comparison cannot be processed anymore.
+     * |[10:8]  |PWUCNT    |Secure DPM Password Updated Times (Read Only)
+     * |        |          |This bit indicates how many times of secure password has been updated.
+     * |        |          |The max value is 7. If PWUCNT reached the max value, Secure DPM password cannot be updated anymore.
+     * |[16]    |DBGDIS    |Secure Debug Disable Flag (Read Only)
+     * |        |          |This bit indicates the current value of Secure DPM DBGDIS bit (DBGDISS).
+     * |        |          |{PWOK, LOCK, DBGDIS} bits define the current state of DPM.
+     * |        |          |x00 = DEFAULT state.
+     * |        |          |x1x = LOCKED state.
+     * |        |          |001 = CLOSE state.
+     * |        |          |101 = OPEN state.
+     * |        |          |Others = Unknown.
+     * |[17]    |LOCK      |Secure Debug Lock Flag (Read Only)
+     * |        |          |This bit indicates the current value of Secure DPM LOCK bit (LOCKS).
+     * |[18]    |PWOK      |Secure Password OK Flag (Read Only)
+     * |        |          |This bit indicates the Secure DPM password has been checked and is correct.
+     * |        |          |0 = The Secure DPM password has not been checked pass, yet.
+     * |        |          |1 = The Secure DPM password has been checked pass since last cold reset.
+     * @var DPM_T::SPW
+     * Offset: 0x10  Secure DPM Password 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |PW        |Password
+     * |        |          |Write password[31:0] to this register to update or compare Secure DPM password.
+     * |        |          |It is write-only and always read as 0xFFFFFFFF.
+     * Offset: 0x14  Secure DPM Password 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |PW        |Password
+     * |        |          |Write password[63:32] to this register to update or compare Secure DPM password
+     * |        |          |It is write-only and always read as 0xFFFFFFFF.
+     * Offset: 0x18  Secure DPM Password 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |PW        |Password
+     * |        |          |Write password[95:64] to this register to update or compare Secure DPM password.
+     * |        |          |It is write-only and always read as 0xFFFFFFFF.
+     * Offset: 0x1C  Secure DPM Password 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |PW        |Password
+     * |        |          |Write password[127:96] to this register to update or compare Secure DPM password.
+     * |        |          |It is write-only and always read as 0xFFFFFFFF.
+     * @var DPM_T::NSCTL
+     * Offset: 0x50  Non-secure DPM Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |DBGDIS    |Set Non-secure DPM Debug Disable Bit
+     * |        |          |When this bit is read as zero, it can be write to one to configure the Non-secure DPM DBGDIS bit (DBGDISNS).
+     * |        |          |When write:
+     * |        |          |0 = No operation.
+     * |        |          |1 = Trigger the process to set DBGDISNS configuration bit.
+     * |        |          |Note: This bit can be set to 1 but cannot be cleared to 0.
+     * |[1]     |LOCK      |Set Non-secure DPM Debug Lock Bit
+     * |        |          |When this bit is read as zero, it can be write to one to configure the Non-secure DPM LOCK bit (LOCKNS).
+     * |        |          |When write:
+     * |        |          |0 = No operation.
+     * |        |          |1 = Trigger the process to set LOCKNS configuration bit.
+     * |        |          |Note: This bit can be set to 1 but cannot be cleared to 0.
+     * |[2]     |PWCMP     |Non-secure DPM Password Compare Bit
+     * |        |          |Set to enter the process of compare Non-secure DPM password.
+     * |        |          |0 = No operation.
+     * |        |          |1 = Compare Non-secure DPM password.
+     * |        |          |Note: This bit will be cleared after the comparison process is finished.
+     * |[3]     |PWUPD     |Non-secure DPM Password Update Bit
+     * |        |          |Set to enter the process of updating Non-secure DPM password.
+     * |        |          |0 = No operation.
+     * |        |          |1 = Update Non-secure DPM password.
+     * |        |          |Note 1: This bit should be set with PWCMP equal to 0.
+     * |        |          |Note 2: This bit will be cleared after the update process is finished.
+     * |[12]    |DACCWDIS  |Debug Write Access Disable Bit
+     * |        |          |This bit disables the writability of external debugger to Non-secure DPM registers for debug authentication.
+     * |        |          |0 = External debugger can write Non-secure DPM registers.
+     * |        |          |1 = External debugger cannot write Non-secure DPM registers.
+     * |[31:24] |WVCODE    |Write Verify Code and Read Verify Code
+     * |        |RVCODE    |Read operation:
+     * |        |          |0xA5 = The read access for DPM_NSCTL is correct.
+     * |        |          |Others = The read access for DPM_NSCTL is incorrect.
+     * |        |          |Write operation:
+     * |        |          |0x5A = The write verify code, 0x5A, is needed to do a valid write to DPM_NSCTL.
+     * |        |          |Others = Invalid write verify code.
+     * @var DPM_T::NSSTS
+     * Offset: 0x54  Non-secure DPM Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BUSY      |DPM Busy Flag (Read Only)
+     * |        |          |This bit indicates the DPM is busy.
+     * |        |          |0 = DPM is not busy and writing to any register is accepted.
+     * |        |          |1 = DPM is busy and other bits in DPM_NSSTS register are not valid and writing to any register is ignored.
+     * |[4]     |PWCERR    |Non-secure DPM Password Compared Error Flag
+     * |        |          |This bit indicates the result of Non-secure DPM password comparison.
+     * |        |          |0 = The result of Non-secure DPM password is correct.
+     * |        |          |1 = The result of Non-seucre DPM password is incorrect.
+     * |        |          |Note: This flag is write-one-clear.
+     * |[5]     |PWUOK     |Non-secure DPM Password Updated Flag
+     * |        |          |This bit indicates Non-secure DPM password has been updated correctly.
+     * |        |          |When read:
+     * |        |          |0 = No successful updating process has happened.
+     * |        |          |1 = There is at least one successful updating process since last clearing of this bit.
+     * |        |          |Note: This flag is write-one-clear.
+     * |[6]     |PWFMAX    |Non-secure DPM Password Fail Times Maximum Reached Flag (Read Only)
+     * |        |          |This bit indicates if the fail times of comparing Non-secure DPM password reached max times.
+     * |        |          |0 = Max time has not reached and Non-secure DPM password comparison can be triggered.
+     * |        |          |1 = Max time reached and Non-secure DPM password comparison cannot be processed anymore.
+     * |[10:8]  |PWUCNT    |Non-secure DPM Password Updated Times (Read Only)
+     * |        |          |This bit indicates how many times of non-secure password has been updated.
+     * |        |          |The max value is 7. If PWUCNT reached the max value, Non-secure DPM password cannot be updated anymore.
+     * |[16]    |DBGDIS    |Non-secure Debug Disable Flag (Read Only)
+     * |        |          |This bit indicates the current value of of Non-secure DPM DBGDIS bit (DBGDISNS).
+     * |        |          |{PWOK, LOCK, DBGDIS} bits define the current state of DPM.
+     * |        |          |x00 = DEFAULT state.
+     * |        |          |x1x = LOCKED state.
+     * |        |          |001 = CLOSE state.
+     * |        |          |101 = OPEN state.
+     * |        |          |Others = Unknown.
+     * |[17]    |LOCK      |Non-secure Debug Lock Flag (Read Only)
+     * |        |          |This bit indicates the current value of Non-secure DPM DBGDIS bit (LOCKNS).
+     * |[18]    |PWOK      |Non-secure Password OK Flag (Read Only)
+     * |        |          |This bit indicates the Non-secure DPM password has been checked and is correct.
+     * |        |          |0 = The Non-secure DPM password has not been checked pass, yet.
+     * |        |          |1 = The Non-secure DPM password has been checked pass since last cold reset.
+     * @var DPM_T::NSPW
+     * Offset: 0x60  Non-secure DPM Password 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |PW        |Password
+     * |        |          |Write password[31:0] to this register to update or compare Non-secure DPM password.
+     * |        |          |It is write-only and always read as 0xFFFFFFFF.
+     * Offset: 0x64  Non-secure DPM Password 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |PW        |Password
+     * |        |          |Write password[63:32] to this register to update or compare Non-secure DPM password.
+     * |        |          |It is write-only and always read as 0xFFFFFFFF.
+     * Offset: 0x68  Non-secure DPM Password 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |PW        |Password
+     * |        |          |Write password[95:64] to this register to update or compare Non-secure DPM password.
+     * |        |          |It is write-only and always read as 0xFFFFFFFF.
+     * Offset: 0x6C  Non-secure DPM Password 3
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |PW        |Password
+     * |        |          |Write password[127:96] to this register to update or compare Non-secure DPM password.
+     * |        |          |It is write-only and always read as 0xFFFFFFFF.
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] Secure DPM Control Register                                      */
+    __IO uint32_t STS;                   /*!< [0x0004] Secure DPM Status Register                                       */
+    __I  uint32_t RESERVE0[2];
+    __O  uint32_t SPW[4];                /*!< [0x0010/0x0014/0x0018/0x001c] Secure DPM Password 0/1/2/3                 */
+    __I  uint32_t RESERVE1[12];
+    __IO uint32_t NSCTL;                 /*!< [0x0050] Non-secure DPM Control Register                                  */
+    __IO uint32_t NSSTS;                 /*!< [0x0054] Non-secure DPM Status Register                                   */
+    __I  uint32_t RESERVE2[2];
+    __O  uint32_t NSPW[4];               /*!< [0x00600/0x0064/0x0068/0x006c] Non-secure DPM Password 0/1/2/3            */
+
+
+} DPM_T;
+
+/**
+    @addtogroup DPM_CONST DPM Bit Field Definition
+    Constant Definitions for DPM Controller
+  @{
+*/
+
+#define DPM_CTL_DBGDIS_Pos               (0)                                               /*!< DPM_T::CTL: DBGDIS Position            */
+#define DPM_CTL_DBGDIS_Msk               (0x1ul << DPM_CTL_DBGDIS_Pos)                     /*!< DPM_T::CTL: DBGDIS Mask                */
+
+#define DPM_CTL_LOCK_Pos                 (1)                                               /*!< DPM_T::CTL: LOCK Position              */
+#define DPM_CTL_LOCK_Msk                 (0x1ul << DPM_CTL_LOCK_Pos)                       /*!< DPM_T::CTL: LOCK Mask                  */
+
+#define DPM_CTL_PWCMP_Pos                (2)                                               /*!< DPM_T::CTL: PWCMP Position             */
+#define DPM_CTL_PWCMP_Msk                (0x1ul << DPM_CTL_PWCMP_Pos)                      /*!< DPM_T::CTL: PWCMP Mask                 */
+
+#define DPM_CTL_PWUPD_Pos                (3)                                               /*!< DPM_T::CTL: PWUPD Position             */
+#define DPM_CTL_PWUPD_Msk                (0x1ul << DPM_CTL_PWUPD_Pos)                      /*!< DPM_T::CTL: PWUPD Mask                 */
+
+#define DPM_CTL_INTEN_Pos                (8)                                               /*!< DPM_T::CTL: INTEN Position             */
+#define DPM_CTL_INTEN_Msk                (0x1ul << DPM_CTL_INTEN_Pos)                      /*!< DPM_T::CTL: INTEN Mask                 */
+
+#define DPM_CTL_DACCWDIS_Pos             (12)                                              /*!< DPM_T::CTL: DACCWDIS Position          */
+#define DPM_CTL_DACCWDIS_Msk             (0x1ul << DPM_CTL_DACCWDIS_Pos)                   /*!< DPM_T::CTL: DACCWDIS Mask              */
+
+#define DPM_CTL_DACCDIS_Pos              (13)                                              /*!< DPM_T::CTL: DACCDIS Position           */
+#define DPM_CTL_DACCDIS_Msk              (0x1ul << DPM_CTL_DACCDIS_Pos)                    /*!< DPM_T::CTL: DACCDIS Mask               */
+
+#define DPM_CTL_WVCODE_Pos               (24)                                              /*!< DPM_T::CTL: WVCODE Position            */
+#define DPM_CTL_WVCODE_Msk               (0xfful << DPM_CTL_WVCODE_Pos)                    /*!< DPM_T::CTL: WVCODE Mask                */
+
+#define DPM_CTL_RVCODE_Pos               (24)                                              /*!< DPM_T::CTL: RVCODE Position            */
+#define DPM_CTL_RVCODE_Msk               (0xfful << DPM_CTL_RVCODE_Pos)                    /*!< DPM_T::CTL: RVCODE Mask                */
+
+#define DPM_STS_BUSY_Pos                 (0)                                               /*!< DPM_T::STS: BUSY Position              */
+#define DPM_STS_BUSY_Msk                 (0x1ul << DPM_STS_BUSY_Pos)                       /*!< DPM_T::STS: BUSY Mask                  */
+
+#define DPM_STS_INT_Pos                  (1)                                               /*!< DPM_T::STS: INT Position               */
+#define DPM_STS_INT_Msk                  (0x1ul << DPM_STS_INT_Pos)                        /*!< DPM_T::STS: INT Mask                   */
+
+#define DPM_STS_PWCERR_Pos               (4)                                               /*!< DPM_T::STS: PWCERR Position            */
+#define DPM_STS_PWCERR_Msk               (0x1ul << DPM_STS_PWCERR_Pos)                     /*!< DPM_T::STS: PWCERR Mask                */
+
+#define DPM_STS_PWUOK_Pos                (5)                                               /*!< DPM_T::STS: PWUOK Position             */
+#define DPM_STS_PWUOK_Msk                (0x1ul << DPM_STS_PWUOK_Pos)                      /*!< DPM_T::STS: PWUOK Mask                 */
+
+#define DPM_STS_PWFMAX_Pos               (6)                                               /*!< DPM_T::STS: PWFMAX Position            */
+#define DPM_STS_PWFMAX_Msk               (0x1ul << DPM_STS_PWFMAX_Pos)                     /*!< DPM_T::STS: PWFMAX Mask                */
+
+#define DPM_STS_PWUCNT_Pos               (8)                                               /*!< DPM_T::STS: PWUCNT Position            */
+#define DPM_STS_PWUCNT_Msk               (0x7ul << DPM_STS_PWUCNT_Pos)                     /*!< DPM_T::STS: PWUCNT Mask                */
+
+#define DPM_STS_DBGDIS_Pos               (16)                                              /*!< DPM_T::STS: DBGDIS Position            */
+#define DPM_STS_DBGDIS_Msk               (0x1ul << DPM_STS_DBGDIS_Pos)                     /*!< DPM_T::STS: DBGDIS Mask                */
+
+#define DPM_STS_LOCK_Pos                 (17)                                              /*!< DPM_T::STS: LOCK Position              */
+#define DPM_STS_LOCK_Msk                 (0x1ul << DPM_STS_LOCK_Pos)                       /*!< DPM_T::STS: LOCK Mask                  */
+
+#define DPM_STS_PWOK_Pos                 (18)                                              /*!< DPM_T::STS: PWOK Position              */
+#define DPM_STS_PWOK_Msk                 (0x1ul << DPM_STS_PWOK_Pos)                       /*!< DPM_T::STS: PWOK Mask                  */
+
+#define DPM_SPW0_PW_Pos                  (0)                                               /*!< DPM_T::SPW0: PW Position               */
+#define DPM_SPW0_PW_Msk                  (0xfffffffful << DPM_SPW0_PW_Pos)                 /*!< DPM_T::SPW0: PW Mask                   */
+
+#define DPM_SPW1_PW_Pos                  (0)                                               /*!< DPM_T::SPW1: PW Position               */
+#define DPM_SPW1_PW_Msk                  (0xfffffffful << DPM_SPW1_PW_Pos)                 /*!< DPM_T::SPW1: PW Mask                   */
+
+#define DPM_SPW2_PW_Pos                  (0)                                               /*!< DPM_T::SPW2: PW Position               */
+#define DPM_SPW2_PW_Msk                  (0xfffffffful << DPM_SPW2_PW_Pos)                 /*!< DPM_T::SPW2: PW Mask                   */
+
+#define DPM_SPW3_PW_Pos                  (0)                                               /*!< DPM_T::SPW3: PW Position               */
+#define DPM_SPW3_PW_Msk                  (0xfffffffful << DPM_SPW3_PW_Pos)                 /*!< DPM_T::SPW3: PW Mask                   */
+
+#define DPM_NSCTL_DBGDIS_Pos             (0)                                               /*!< DPM_T::NSCTL: DBGDIS Position          */
+#define DPM_NSCTL_DBGDIS_Msk             (0x1ul << DPM_NSCTL_DBGDIS_Pos)                   /*!< DPM_T::NSCTL: DBGDIS Mask              */
+
+#define DPM_NSCTL_LOCK_Pos               (1)                                               /*!< DPM_T::NSCTL: LOCK Position            */
+#define DPM_NSCTL_LOCK_Msk               (0x1ul << DPM_NSCTL_LOCK_Pos)                     /*!< DPM_T::NSCTL: LOCK Mask                */
+
+#define DPM_NSCTL_PWCMP_Pos              (2)                                               /*!< DPM_T::NSCTL: PWCMP Position           */
+#define DPM_NSCTL_PWCMP_Msk              (0x1ul << DPM_NSCTL_PWCMP_Pos)                    /*!< DPM_T::NSCTL: PWCMP Mask               */
+
+#define DPM_NSCTL_PWUPD_Pos              (3)                                               /*!< DPM_T::NSCTL: PWUPD Position           */
+#define DPM_NSCTL_PWUPD_Msk              (0x1ul << DPM_NSCTL_PWUPD_Pos)                    /*!< DPM_T::NSCTL: PWUPD Mask               */
+
+#define DPM_NSCTL_DACCWDIS_Pos           (12)                                              /*!< DPM_T::NSCTL: DACCWDIS Position        */
+#define DPM_NSCTL_DACCWDIS_Msk           (0x1ul << DPM_NSCTL_DACCWDIS_Pos)                 /*!< DPM_T::NSCTL: DACCWDIS Mask            */
+
+#define DPM_NSCTL_WVCODE_Pos             (24)                                              /*!< DPM_T::NSCTL: WVCODE Position          */
+#define DPM_NSCTL_WVCODE_Msk             (0xfful << DPM_NSCTL_WVCODE_Pos)                  /*!< DPM_T::NSCTL: WVCODE Mask              */
+
+#define DPM_NSCTL_RVCODE_Pos             (24)                                              /*!< DPM_T::NSCTL: RVCODE Position          */
+#define DPM_NSCTL_RVCODE_Msk             (0xfful << DPM_NSCTL_RVCODE_Pos)                  /*!< DPM_T::NSCTL: RVCODE Mask              */
+
+#define DPM_NSSTS_BUSY_Pos               (0)                                               /*!< DPM_T::NSSTS: BUSY Position            */
+#define DPM_NSSTS_BUSY_Msk               (0x1ul << DPM_NSSTS_BUSY_Pos)                     /*!< DPM_T::NSSTS: BUSY Mask                */
+
+#define DPM_NSSTS_PWCERR_Pos             (4)                                               /*!< DPM_T::NSSTS: PWCERR Position          */
+#define DPM_NSSTS_PWCERR_Msk             (0x1ul << DPM_NSSTS_PWCERR_Pos)                   /*!< DPM_T::NSSTS: PWCERR Mask              */
+
+#define DPM_NSSTS_PWUOK_Pos              (5)                                               /*!< DPM_T::NSSTS: PWUOK Position           */
+#define DPM_NSSTS_PWUOK_Msk              (0x1ul << DPM_NSSTS_PWUOK_Pos)                    /*!< DPM_T::NSSTS: PWUOK Mask               */
+
+#define DPM_NSSTS_PWFMAX_Pos             (6)                                               /*!< DPM_T::NSSTS: PWFMAX Position          */
+#define DPM_NSSTS_PWFMAX_Msk             (0x1ul << DPM_NSSTS_PWFMAX_Pos)                   /*!< DPM_T::NSSTS: PWFMAX Mask              */
+
+#define DPM_NSSTS_PWUCNT_Pos             (8)                                               /*!< DPM_T::NSSTS: PWUCNT Position          */
+#define DPM_NSSTS_PWUCNT_Msk             (0x7ul << DPM_NSSTS_PWUCNT_Pos)                   /*!< DPM_T::NSSTS: PWUCNT Mask              */
+
+#define DPM_NSSTS_DBGDIS_Pos             (16)                                              /*!< DPM_T::NSSTS: DBGDIS Position          */
+#define DPM_NSSTS_DBGDIS_Msk             (0x1ul << DPM_NSSTS_DBGDIS_Pos)                   /*!< DPM_T::NSSTS: DBGDIS Mask              */
+
+#define DPM_NSSTS_LOCK_Pos               (17)                                              /*!< DPM_T::NSSTS: LOCK Position            */
+#define DPM_NSSTS_LOCK_Msk               (0x1ul << DPM_NSSTS_LOCK_Pos)                     /*!< DPM_T::NSSTS: LOCK Mask                */
+
+#define DPM_NSSTS_PWOK_Pos               (18)                                              /*!< DPM_T::NSSTS: PWOK Position            */
+#define DPM_NSSTS_PWOK_Msk               (0x1ul << DPM_NSSTS_PWOK_Pos)                     /*!< DPM_T::NSSTS: PWOK Mask                */
+
+#define DPM_NSPW0_PW_Pos                 (0)                                               /*!< DPM_T::NSPW0: PW Position              */
+#define DPM_NSPW0_PW_Msk                 (0xfffffffful << DPM_NSPW0_PW_Pos)                /*!< DPM_T::NSPW0: PW Mask                  */
+
+#define DPM_NSPW1_PW_Pos                 (0)                                               /*!< DPM_T::NSPW1: PW Position              */
+#define DPM_NSPW1_PW_Msk                 (0xfffffffful << DPM_NSPW1_PW_Pos)                /*!< DPM_T::NSPW1: PW Mask                  */
+
+#define DPM_NSPW2_PW_Pos                 (0)                                               /*!< DPM_T::NSPW2: PW Position              */
+#define DPM_NSPW2_PW_Msk                 (0xfffffffful << DPM_NSPW2_PW_Pos)                /*!< DPM_T::NSPW2: PW Mask                  */
+
+#define DPM_NSPW3_PW_Pos                 (0)                                               /*!< DPM_T::NSPW3: PW Position              */
+#define DPM_NSPW3_PW_Msk                 (0xfffffffful << DPM_NSPW3_PW_Pos)                /*!< DPM_T::NSPW3: PW Mask                  */
+
+
+/**@}*/ /* DPM_CONST */
+/**@}*/ /* end of DPM register group */
+
+
+
+/*---------------------- Firmware Version Counter -------------------------*/
+/**
+    @addtogroup FVC Firmware Version Counter(FVC)
+    Memory Mapped Structure for FVC Controller
+@{ */
+
+typedef struct
+{
+
+
+    /**
+     * @var FVC_T::CTL
+     * Offset: 0x00  FVC Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |INIT      |FVC Init Bit
+     * |        |          |Set to 1 to enable FVC
+     * |        |          |This bit is writable when FVC is at Reset state.
+     * |        |          |Note: After set to 1, this bit is cleared to 0 automatically when FVC is back to Reset state.
+     * |[1]     |MONOEN    |Monotonic Enable Bit
+     * |        |          |Set to 1 to enable the monotonic mechanism of FVC.
+     * |        |          |Note: This bit can be set to1 but cannot be cleared to 0.
+     * |[31:16] |WVCODE    |Verification Code
+     * |        |          |When written, this field must be 0x7710
+     * @var FVC_T::STS
+     * Offset: 0x04  FVC Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BUSY      |FVC Busy Bit
+     * |        |          |Indicates the FVC is at busy state.
+     * |[1]     |RDY       |FVC Ready Bit
+     * |        |          |Indicates the FVC is ready after the initial process.
+     * @var FVC_T::NVC0
+     * Offset: 0x10  Non-volatile Version Counter Control Register0 BL2 Firmware
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |FWVER     |Firmware Version
+     * |        |          |Read: Indicates the current firmware version of FVC0.
+     * |        |          |Write: Updates the firmware version of FVC0.
+     * |        |          |The maximum value of this field is 63.
+     * |        |          |Indicating number of 1 in Fuse OTP or number of 0 in Flash
+     * |[31:16] |WVCODE    |Verification Code
+     * |        |          |When written, this field must be the current firmware version number
+     * @var FVC_T::NVC1
+     * Offset: 0x14  Non-volatile Version Counter Control Register1 BL32 Firmware
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |FWVER     |Firmware Version
+     * |        |          |Read: Indicates the current firmware version of NVC1.
+     * |        |          |Write: Updates the firmware version of NVC1.
+     * |        |          |The maximum value of this field is 63.
+     * |        |          |Indicating number of 1 in Fuse OTP or number of 0 in Flash
+     * |[31:16] |WVCODE    |Verification Code
+     * |        |          |When written, this field must be the current firmware version number
+     * @var FVC_T::NVC4
+     * Offset: 0x20  Non-volatile Version Counter Control Register4 BL33 Firmware
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |FWVER     |Firmware Version
+     * |        |          |Read: Indicates the current firmware version of NVC4.
+     * |        |          |Write: Updates the firmware version of NVC4.
+     * |        |          |The maximum value of this field is 255.
+     * |        |          |Indicating number of 1 in Fuse OTP or number of 0 in Flash
+     * |[31:16] |WVCODE    |Verification Code
+     * |        |          |When written, this field must be the current firmware version number
+     * @var FVC_T::NVC5
+     * Offset: 0x24  Non-volatile Version Counter Control Register5 User-defined Firmware
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |FWVER     |Firmware Version
+     * |        |          |Read: Indicates the current firmware version of NVC5.
+     * |        |          |Write: Updates the firmware version of NVC5.
+     * |        |          |The maximum value of this field is 255.
+     * |        |          |Indicating number of 1 in Fuse OTP or number of 0 in Flash
+     * |[31:16] |WVCODE    |Verification Code
+     * |        |          |When written, this field must be the current firmware version number
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] FVC Control Register                                           */
+    __I  uint32_t STS;                   /*!< [0x0004] FVC Status Register                                            */
+    __I  uint32_t RESERVE0[2];
+    __IO uint32_t NVC[6];                /*!< [0x0010-0x24] Non-volatile Version Counter Control Register Firmware. NVC[2], NVC[3] is reserved    */
+} FVC_T;
+
+/**
+    @addtogroup FVC_CONST FVC Bit Field Definition
+    Constant Definitions for FVC Controller
+@{ */
+
+#define FVC_CTL_INIT_Pos                 (0)                                               /*!< FVC_T::CTL: INIT Position              */
+#define FVC_CTL_INIT_Msk                 (0x1ul << FVC_CTL_INIT_Pos)                       /*!< FVC_T::CTL: INIT Mask                  */
+
+#define FVC_CTL_MONOEN_Pos               (1)                                               /*!< FVC_T::CTL: MONOEN Position            */
+#define FVC_CTL_MONOEN_Msk               (0x1ul << FVC_CTL_MONOEN_Pos)                     /*!< FVC_T::CTL: MONOEN Mask                */
+
+#define FVC_CTL_WVCODE_Pos               (16)                                              /*!< FVC_T::CTL: WVCODE Position            */
+#define FVC_CTL_WVCODE_Msk               (0xfffful << FVC_CTL_WVCODE_Pos)                  /*!< FVC_T::CTL: WVCODE Mask                */
+
+#define FVC_STS_BUSY_Pos                 (0)                                               /*!< FVC_T::STS: BUSY Position              */
+#define FVC_STS_BUSY_Msk                 (0x1ul << FVC_STS_BUSY_Pos)                       /*!< FVC_T::STS: BUSY Mask                  */
+
+#define FVC_STS_RDY_Pos                  (1)                                               /*!< FVC_T::STS: RDY Position               */
+#define FVC_STS_RDY_Msk                  (0x1ul << FVC_STS_RDY_Pos)                        /*!< FVC_T::STS: RDY Mask                   */
+
+#define FVC_NVC_FWVER_Pos                (0)                                               /*!< FVC_T::NVC:  FWVER Position            */
+#define FVC_NVC_FWVER_Msk                (0xfffful << FVC_NVC_FWVER_Pos)                   /*!< FVC_T::NVC:  FWVER Mask                */
+
+/**@}*/ /* FVC_CONST */
+/**@}*/ /* end of FVC register group */
+
+
+/*---------------------- Product Life-cycle Manager -------------------------*/
+/**
+    @addtogroup PLM Product Life-cycle Manager(PLM)
+    Memory Mapped Structure for PLM Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var PLM_T::CTL
+     * Offset: 0x00  Product Life-cycle Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |STAGE     |Life-cycle Stage Update Bits
+     * |        |          |Bits to update PLM stage. All bits can be set to one but cannot be cleared to zero.
+     * |        |          |001 = progress to OEM stage.
+     * |        |          |011 = progress to Deployed stage.
+     * |        |          |111 = progress to RMA stage.
+     * |        |          |Other value will be ignored.
+     * |[31:16] |WVCODE    |Write Verify Code
+     * |        |          |The code is 0x475A for a valid write to this register.
+     * @var PLM_T::STS
+     * Offset: 0x04  Product Life-cycle Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |STAGE     |Life-cycle Stage (Read Only)
+     * |        |          |Indicates the current stage of PLM.
+     * |        |          |000 = Vendor Stage.
+     * |        |          |001 = OEM Stage.
+     * |        |          |011 = Deployed Stage.
+     * |        |          |111 = RMA Stage.
+     * |        |          |Others = ERROR Stage.
+     * |[8]     |DIRTY     |DIRTY Bit (Read Only)
+     * |        |          |Indicate the life-cycle stage has been progressed after last cold-reset
+     * |        |          |Value of STAGE bits is not Current stage of PLM
+     * |        |          |It needs a cold reset to make it work.
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] Product Life-cycle Control Register                              */
+    __I  uint32_t STS;                   /*!< [0x0004] Product Life-cycle Status Register                               */
+
+} PLM_T;
+
+/**
+    @addtogroup PLM_CONST PLM Bit Field Definition
+    Constant Definitions for PLM Controller
+  @{
+*/
+
+#define PLM_CTL_STAGE_Pos                (0)                                               /*!< PLM_T::CTL: STAGE Position             */
+#define PLM_CTL_STAGE_Msk                (0x7ul << PLM_CTL_STAGE_Pos)                      /*!< PLM_T::CTL: STAGE Mask                 */
+
+#define PLM_CTL_WVCODE_Pos               (16)                                              /*!< PLM_T::CTL: WVCODE Position            */
+#define PLM_CTL_WVCODE_Msk               (0xfffful << PLM_CTL_WVCODE_Pos)                  /*!< PLM_T::CTL: WVCODE Mask                */
+
+#define PLM_STS_STAGE_Pos                (0)                                               /*!< PLM_T::STS: STAGE Position             */
+#define PLM_STS_STAGE_Msk                (0x7ul << PLM_STS_STAGE_Pos)                      /*!< PLM_T::STS: STAGE Mask                 */
+
+#define PLM_STS_DIRTY_Pos                (8)                                               /*!< PLM_T::STS: DIRTY Position             */
+#define PLM_STS_DIRTY_Msk                (0x1ul << PLM_STS_DIRTY_Pos)                      /*!< PLM_T::STS: DIRTY Mask                 */
+
+/**@}*/ /* PLM_CONST */
+/**@}*/ /* end of PLM register group */
+
+
+/*---------------------- Secure configuration Unit -------------------------*/
+/**
+    @addtogroup SCU Secure configuration Unit(SCU)
+    Memory Mapped Structure for SCU Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var SCU_T::PNSSET
+     * Offset: 0x00  Peripheral Non-secure Attribution Set Register0 (0x4000_0000~0x4001_FFFF)
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[9]     |USBH      |Set USBH to Non-secure State
+     * |        |          |Write 1 to set USBH to non-secure state. Write 0 has no effect.
+     * |        |          |0 = USBH is a secure module (default).
+     * |        |          |1 = USBH is a non-secure module.
+     * |[13]    |SDH0      |Set SDH0 to Non-secure State
+     * |        |          |Write 1 to set SDH0 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = SDH0 is a secure module (default).
+     * |        |          |1 = SDH0 is a non-secure module.
+     * |[16]    |EBI       |Set EBI to Non-secure State
+     * |        |          |Write 1 to set EBI to non-secure state. Write 0 has no effect.
+     * |        |          |0 = EBI is a secure module (default).
+     * |        |          |1 = EBI is a non-secure module.
+     * |[24]    |PDMA1     |Set PDMA1 to Non-secure State
+     * |        |          |Write 1 to set PDMA1 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = PDMA1 is a secure module (default).
+     * |        |          |1 = PDMA1 is a non-secure module.
+     * Offset: 0x04  Peripheral Non-secure Attribution Set Register1 (0x4002_0000~0x4003_FFFF)
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[17]    |CRC       |Set CRC to Non-secure State
+     * |        |          |Write 1 to set CRC to non-secure state. Write 0 has no effect.
+     * |        |          |0 = CRC is a secure module (default).
+     * |        |          |1 = CRC is a non-secure module.
+     * |[18]    |CRPT      |Set CRPT to Non-secure State
+     * |        |          |0 = CRPT is a secure module (default).
+     * |        |          |1 = CRPT is a non-secure module.
+     * Offset: 0x08  Peripheral Non-secure Attribution Set Register2 (0x4004_0000~0x4005_FFFF)
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2]     |EWDT      |Set EWDT to Non-secure State
+     * |        |          |Write 1 to set EWDT to non-secure state. Write 0 has no effect.
+     * |        |          |0 = EWDT is a secure module (default).
+     * |        |          |1 = EWDT is a non-secure module.
+     * |[3]     |EADC      |Set EADC to Non-secure State
+     * |        |          |Write 1 to set EADC to non-secure state. Write 0 has no effect.
+     * |        |          |0 = EADC is a secure module (default).
+     * |        |          |1 = EADC is a non-secure module.
+     * |[5]     |ACMP01    |Set ACMP01 to Non-secure State
+     * |        |          |Write 1 to set ACMP0, ACMP1 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = ACMP0, ACMP1 are secure modules (default).
+     * |        |          |1 = ACMP0, ACMP1 are non-secure modules.
+     * |[7]     |DAC       |Set DAC to Non-secure State
+     * |        |          |Write 1 to set DAC to non-secure state. Write 0 has no effect.
+     * |        |          |0 = DAC is a secure module (default).
+     * |        |          |1 = DAC is a non-secure module.
+     * |[8]     |I2S0      |Set I2S0 to Non-secure State
+     * |        |          |Write 1 to set I2S0 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = I2S0 is a secure module (default).
+     * |        |          |1 = I2S0 is a non-secure module.
+     * |[13]    |OTG       |Set OTG to Non-secure State
+     * |        |          |Write 1 to set OTG to non-secure state. Write 0 has no effect.
+     * |        |          |0 = OTG is a secure module (default).
+     * |        |          |1 = OTG is a non-secure module.
+     * |[17]    |TMR23     |Set TMR23 to Non-secure State
+     * |        |          |Write 1 to set TMR23 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = TMR23 is a secure module (default).
+     * |        |          |1 = TMR23 is a non-secure module.
+     * |[24]    |EPWM0     |Set EPWM0 to Non-secure State
+     * |        |          |Write 1 to set EPWM0 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = EPWM0 is a secure module (default).
+     * |        |          |1 = EPWM0 is a non-secure module.
+     * |[25]    |EPWM1     |Set EPWM1 to Non-secure State
+     * |        |          |Write 1 to set EPWM1 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = EPWM1 is a secure module (default).
+     * |        |          |1 = EPWM1 is a non-secure module.
+     * |[26]    |BPWM0     |Set BPWM0 to Non-secure State
+     * |        |          |Write 1 to set BPWM0 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = BPWM0 is a secure module (default).
+     * |        |          |1 = BPWM0 is a non-secure module.
+     * |[27]    |BPWM1     |Set BPWM1 to Non-secure State
+     * |        |          |Write 1 to set BPWM1 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = BPWM1 is a secure module (default).
+     * |        |          |1 = BPWM1 is a non-secure module.
+     * Offset: 0x0C  Peripheral Non-secure Attribution Set Register3 (0x4006_0000~0x4007_FFFF)
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |QSPI0     |Set QSPI0 to Non-secure State
+     * |        |          |Write 1 to set QSPI0 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = QSPI0 is a secure module (default).
+     * |        |          |1 = QSPI0 is a non-secure module.
+     * |[1]     |SPI0      |Set SPI0 to Non-secure State
+     * |        |          |Write 1 to set SPI0 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = SPI0 is a secure module (default).
+     * |        |          |1 = SPI0 is a non-secure module.
+     * |[2]     |SPI1      |Set SPI1 to Non-secure State
+     * |        |          |Write 1 to set SPI1 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = SPI1 is a secure module (default).
+     * |        |          |1 = SPI1 is a non-secure module.
+     * |[3]     |SPI2      |Set SPI2 to Non-secure State
+     * |        |          |Write 1 to set SPI2 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = SPI2 is a secure module (default).
+     * |        |          |1 = SPI2 is a non-secure module.
+     * |[4]     |SPI3      |Set SPI3 to Non-secure State
+     * |        |          |Write 1 to set SPI3 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = SPI3 is a secure module (default).
+     * |        |          |1 = SPI3 is a non-secure module.
+     * |[16]    |UART0     |Set UART0 to Non-secure State
+     * |        |          |Write 1 to set UART0 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = UART0 is a secure module (default).
+     * |        |          |1 = UART0 is a non-secure module.
+     * |[17]    |UART1     |Set UART1 to Non-secure State
+     * |        |          |Write 1 to set UART1 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = UART1 is a secure module (default).
+     * |        |          |1 = UART1 is a non-secure module.
+     * |[18]    |UART2     |Set UART2 to Non-secure State
+     * |        |          |Write 1 to set UART2 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = UART2 is a secure module (default).
+     * |        |          |1 = UART2 is a non-secure module.
+     * |[19]    |UART3     |Set UART3 to Non-secure State
+     * |        |          |Write 1 to set UART3 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = UART3 is a secure module (default).
+     * |        |          |1 = UART3 is a non-secure module.
+     * |[20]    |UART4     |Set UART4 to Non-secure State
+     * |        |          |Write 1 to set UART4 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = UART4 is a secure module (default).
+     * |        |          |1 = UART4 is a non-secure module.
+     * |[21]    |UART5     |Set UART5 to Non-secure State
+     * |        |          |Write 1 to set UART5 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = UART5 is a secure module (default).
+     * |        |          |1 = UART5 is a non-secure module.
+     * Offset: 0x10  Peripheral Non-secure Attribution Set Register4 (0x4008_0000~0x4009_FFFF)
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |I2C0      |Set I2C0 to Non-secure State
+     * |        |          |Write 1 to set I2C0 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = I2C0 is a secure module (default).
+     * |        |          |1 = I2C0 is a non-secure module.
+     * |[1]     |I2C1      |Set I2C1 to Non-secure State
+     * |        |          |Write 1 to set I2C1 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = I2C1 is a secure module (default).
+     * |        |          |1 = I2C1 is a non-secure module.
+     * |[2]     |I2C2      |Set I2C2 to Non-secure State
+     * |        |          |Write 1 to set I2C2 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = I2C2 is a secure module (default).
+     * |        |          |1 = I2C2 is a non-secure module.
+     * |[16]    |SC0       |Set SC0 to Non-secure State
+     * |        |          |Write 1 to set SC0 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = SC0 is a secure module (default).
+     * |        |          |1 = SC0 is a non-secure module.
+     * |[17]    |SC1       |Set SC1 to Non-secure State
+     * |        |          |Write 1 to set SC1 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = SC1 is a secure module (default).
+     * |        |          |1 = SC1 is a non-secure module.
+     * |[18]    |SC2       |Set SC2 to Non-secure State
+     * |        |          |Write 1 to set SC2 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = SC2 is a secure module (default).
+     * |        |          |1 = SC2 is a non-secure module.
+     * Offset: 0x14  Peripheral Non-secure Attribution Set Register5 (0x400A_0000~0x400B_FFFF)
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CAN0      |Set CAN0 to Non-secure State
+     * |        |          |Write 1 to set CAN0 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = CAN0 is a secure module (default).
+     * |        |          |1 = CAN0 is a non-secure module.
+     * |[16]    |QEI0      |Set QEI0 to Non-secure State
+     * |        |          |Write 1 to set QEI0 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = QEI0 is a secure module (default).
+     * |        |          |1 = QEI0 is a non-secure module.
+     * |[17]    |QEI1      |Set QEI1 to Non-secure State
+     * |        |          |Write 1 to set QEI1 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = QEI1 is a secure module (default).
+     * |        |          |1 = QEI1 is a non-secure module.
+     * |[20]    |ECAP0     |Set ECAP0 to Non-secure State
+     * |        |          |Write 1 to set ECAP0 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = ECAP0 is a secure module (default).
+     * |        |          |1 = ECAP0 is a non-secure module.
+     * |[21]    |ECAP1     |Set ECAP1 to Non-secure State
+     * |        |          |Write 1 to set ECAP1 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = ECAP1 is a secure module (default).
+     * |        |          |1 = ECAP1 is a non-secure module.
+     * |[25]    |TRNG      |Set TRNG to Non-secure State
+     * |        |          |Write 1 to set TRNG to non-secure state. Write 0 has no effect.
+     * |        |          |0 = TRNG is a secure module (default).
+     * |        |          |1 = TRNG is a non-secure module.
+     * |[27]    |LCD       |Set LCD to Non-secure State
+     * |        |          |Write 1 to set LCD to non-secure state. Write 0 has no effect.
+     * |        |          |0 = LCD is a secure module (default).
+     * |        |          |1 = LCD is a non-secure module.
+     * Offset: 0x18  Peripheral Non-secure Attribution Set Register6 (0x400C_0000~0x400D_FFFF)
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |USBD      |Set USBD to Non-secure State
+     * |        |          |Write 1 to set USBD to non-secure state. Write 0 has no effect.
+     * |        |          |0 = USBD is a secure module (default).
+     * |        |          |1 = USBD is a non-secure module.
+     * |[16]    |USCI0     |Set USCI0 to Non-secure State
+     * |        |          |Write 1 to set USCI0 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = USCI0 is a secure module (default).
+     * |        |          |1 = USCI0 is a non-secure module.
+     * |[17]    |USCI1     |Set USCI1 to Non-secure State
+     * |        |          |Write 1 to set USCI1 to non-secure state. Write 0 has no effect.
+     * |        |          |0 = USCI1 is a secure module (default).
+     * |        |          |1 = USCI1 is a non-secure module.
+     * @var SCU_T::IONSSET
+     * Offset: 0x20  IO Non-secure Attribution Set Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PA        |Set GPIO Port a to Non-scecure State
+     * |        |          |Write 1 to set PA to non-secure state. Write 0 has no effect.
+     * |        |          |0 = GPIO port A is secure (default).
+     * |        |          |1 = GPIO port A is non-secure.
+     * |[1]     |PB        |Set GPIO Port B to Non-scecure State
+     * |        |          |Write 1 to set PB to non-secure state. Write 0 has no effect.
+     * |        |          |0 = GPIO port B is secure (default).
+     * |        |          |1 = GPIO port B is non-secure.
+     * |[2]     |PC        |Set GPIO Port C to Non-scecure State
+     * |        |          |Write 1 to set PC to non-secure state. Write 0 has no effect.
+     * |        |          |0 = GPIO port C is secure (default).
+     * |        |          |1 = GPIO port C is non-secure.
+     * |[3]     |PD        |Set GPIO Port D to Non-scecure State
+     * |        |          |Write 1 to set PD to non-secure state. Write 0 has no effect.
+     * |        |          |0 = GPIO port D is secure (default).
+     * |        |          |1 = GPIO port D is non-secure.
+     * |[4]     |PE        |Set GPIO Port E to Non-scecure State
+     * |        |          |Write 1 to set PE to non-secure state. Write 0 has no effect.
+     * |        |          |0 = GPIO port E is secure (default).
+     * |        |          |1 = GPIO port E is non-secure.
+     * |[5]     |PF        |Set GPIO Port F to Non-scecure State
+     * |        |          |Write 1 to set PF to non-secure state. Write 0 has no effect.
+     * |        |          |0 = GPIO port F is secure (default).
+     * |        |          |1 = GPIO port F is non-secure.
+     * |[6]     |PG        |Set GPIO Port G to Non-scecure State
+     * |        |          |Write 1 to set PG to non-secure state. Write 0 has no effect.
+     * |        |          |0 = GPIO port G is secure (default).
+     * |        |          |1 = GPIO port G is non-secure.
+     * |[7]     |PH        |Set GPIO Port H to Non-scecure State
+     * |        |          |Write 1 to set PH to non-secure state. Write 0 has no effect.
+     * |        |          |0 = GPIO port H is secure (default).
+     * |        |          |1 = GPIO port H is non-secure.
+     * @var SCU_T::SRAMNSSET
+     * Offset: 0x24  SRAM Non-secure Attribution Set Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[11:0]  |SECn      |Set SRAM Section n to Non-scecure State
+     * |        |          |Write 1 to set SRAM section n to non-secure state. Write 0 is ignored.
+     * |        |          |0 = SRAM Section n is secure (default).
+     * |        |          |1 = SRAM Section n is non-secure.
+     * |        |          |Size per section is 16 Kbytes.
+     * |        |          |Secure SRAM section n is 0x2000_0000+0x4000*n to 0x2000_0000+0x4000*(n+1)-0x1
+     * |        |          |Non-secure SRAM section n is 0x3000_0000+0x4000*n to 0x3000_0000+0x4000*(n+1)-0x1
+     * @var SCU_T::FNSADDR
+     * Offset: 0x28  Flash Non-secure Boundary Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |FNSADDR   |Flash Non-secure Boundary Address
+     * |        |          |Indicate the base address of Non-secure region set in user configuration
+     * |        |          |Refer to FMC section for more details.
+     * @var SCU_T::SVIOIEN
+     * Offset: 0x2C  Security Violation Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |APB0IEN   |APB0 Security Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from security violation of APB0 Disabled.
+     * |        |          |1 = Interrupt triggered from security violation of APB0 Enabled.
+     * |[1]     |APB1IEN   |APB1 Security Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from security violation of APB1 Disabled.
+     * |        |          |1 = Interrupt triggered from security violation of APB1 Enabled.
+     * |[4]     |GPIOIEN   |GPIO Security Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from security violation of GPIO Disabled.
+     * |        |          |1 = Interrupt triggered from security violation of GPIO Enabled.
+     * |[5]     |EBIIEN    |EBI Security Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from security violation of EBI Disabled.
+     * |        |          |1 = Interrupt triggered from security violation of EBI Enabled.
+     * |[6]     |USBHIEN   |USBH Security Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from security violation of USB host Disabled.
+     * |        |          |1 = Interrupt triggered from security violation of USB host Enabled.
+     * |[7]     |CRCIEN    |CRC Security Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from security violation of CRC Disabled.
+     * |        |          |1 = Interrupt triggered from security violation of CRC Enabled.
+     * |[8]     |SDH0IEN   |SDH0 Security Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from security violation of SD host 0 Disabled.
+     * |        |          |1 = Interrupt triggered from security violation of SD host 0 Enabled.
+     * |[10]    |PDMA0IEN  |PDMA0 Security Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from security violation of PDMA0 Disabled.
+     * |        |          |1 = Interrupt triggered from security violation of PDMA0 Enabled.
+     * |[11]    |PDMA1IEN  |PDMA1 Security Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from security violation of PDMA1 Disabled.
+     * |        |          |1 = Interrupt triggered from security violation of PDMA1 Enabled.
+     * |[12]    |SRAM0IEN  |SRAM Bank 0 Security Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from security violation of SRAM bank0 Disabled.
+     * |        |          |1 = Interrupt triggered from security violation of SRAM bank0 Enabled.
+     * |[13]    |SRAM1IEN  |SRAM Bank 1 Security Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from security violation of SRAM bank1 Disabled.
+     * |        |          |1 = Interrupt triggered from security violation of SRAM bank1 Enabled.
+     * |[14]    |FMCIEN    |FMC Security Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from security violation of FMC Disabled.
+     * |        |          |1 = Interrupt triggered from security violation of FMC Enabled.
+     * |[15]    |FLASHIEN  |FLASH Security Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from security violation of Flash data Disabled.
+     * |        |          |1 = Interrupt triggered from security violation of Flash data Enabled.
+     * |[16]    |SCUIEN    |SCU Security Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from security violation of SCU Disabled.
+     * |        |          |1 = Interrupt triggered from security violation of SCU Enabled.
+     * |[17]    |SYSIEN    |SYS Security Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from security violation of system manager Disabled.
+     * |        |          |1 = Interrupt triggered from security violation of system manager Enabled.
+     * |[18]    |CRPTIEN   |CRPT Security Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from security violation of crypto Disabled.
+     * |        |          |1 = Interrupt triggered from security violation of crypto Enabled.
+     * |[19]    |KSIEN     |KS Security Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from security violation of keystore Disabled.
+     * |        |          |1 = Interrupt triggered from security violation of keystore Enabled.
+     * @var SCU_T::SVINTSTS
+     * Offset: 0x30  Security Violation Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |APB0IF    |APB0 Security Violation Interrupt Status
+     * |        |          |0 = No APB0 violation interrupt event.
+     * |        |          |1 = There is APB0 violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[1]     |APB1IF    |APB1 Security Violation Interrupt Status
+     * |        |          |0 = No APB1 violation interrupt event.
+     * |        |          |1 = There is APB1 violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[4]     |GPIOIF    |GPIO Security Violation Interrupt Status
+     * |        |          |0 = No GPIO violation interrupt event.
+     * |        |          |1 = There is GPIO violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[5]     |EBIIF     |EBI Security Violation Interrupt Status
+     * |        |          |0 = No EBI violation interrupt event.
+     * |        |          |1 = There is EBI violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[6]     |USBHIF    |USBH Security Violation Interrupt Status
+     * |        |          |0 = No USBH violation interrupt event.
+     * |        |          |1 = There is USBH violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[7]     |CRCIF     |CRC Security Violation Interrupt Status
+     * |        |          |0 = No CRC violation interrupt event.
+     * |        |          |1 = There is CRC violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[8]     |SDH0IF    |SDH0 Security Violation Interrupt Status
+     * |        |          |0 = No SDH0 violation interrupt event.
+     * |        |          |1 = There is SDH0 violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[10]    |PDMA0IF   |PDMA0 Security Violation Interrupt Status
+     * |        |          |0 = No PDMA0 violation interrupt event.
+     * |        |          |1 = There is PDMA0 violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[11]    |PDMA1IF   |PDMA1 Security Violation Interrupt Status
+     * |        |          |0 = No PDMA1 violation interrupt event.
+     * |        |          |1 = There is PDMA1 violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[12]    |SRAM0IF   |SRAM0 Security Violation Interrupt Status
+     * |        |          |0 = No SRAM0 violation interrupt event.
+     * |        |          |1 = There is SRAM0 violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[13]    |SRAM1IF   |SRAM Bank 1 Security Violation Interrupt Status
+     * |        |          |0 = No SRAM1 violation interrupt event.
+     * |        |          |1 = There is SRAM1 violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[14]    |FMCIF     |FMC Security Violation Interrupt Status
+     * |        |          |0 = No FMC violation interrupt event.
+     * |        |          |1 = There is FMC violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[15]    |FLASHIF   |FLASH Security Violation Interrupt Status
+     * |        |          |0 = No FLASH violation interrupt event.
+     * |        |          |1 = There is FLASH violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[16]    |SCUIF     |SCU Security Violation Interrupt Status
+     * |        |          |0 = No SCU violation interrupt event.
+     * |        |          |1 = There is SCU violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[17]    |SYSIF     |SYS Security Violation Interrupt Status
+     * |        |          |0 = No SYS violation interrupt event.
+     * |        |          |1 = There is SYS violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[18]    |CRPTIF    |CRPT Security Violation Interrupt Status
+     * |        |          |0 = No CRPT violation interrupt event.
+     * |        |          |1 = There is CRPT violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[19]    |KSIF      |KS Security Violation Interrupt Status
+     * |        |          |0 = No KS violation interrupt event.
+     * |        |          |1 = There is KS violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * @var SCU_T::APB0VSRC
+     * Offset: 0x34  APB0 Security Policy Violation Source
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |MASTER    |Master Violating Security Policy
+     * |        |          |Indicate which master invokes the security violation.
+     * |        |          |0x0 = core processor.
+     * |        |          |0x3 = PDMA0.
+     * |        |          |0x4 = SDH0.
+     * |        |          |0x5 = CRYPTO.
+     * |        |          |0x6 = USH.
+     * |        |          |0xB = PDMA1.
+     * |        |          |Others is undefined.
+     * @var SCU_T::APB0VA
+     * Offset: 0x38  APB0 Violation Address
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |VIOADDR   |Violation Address
+     * |        |          |Indicate the target address of the access, which invokes the security violation.
+     * @var SCU_T::APB1VSRC
+     * Offset: 0x3C  APB1 Security Policy Violation Source
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |MASTER    |Master Violating Security Policy
+     * |        |          |Indicate which master invokes the security violation.
+     * |        |          |0x0 = core processor.
+     * |        |          |0x3 = PDMA0.
+     * |        |          |0x4 = SDH0.
+     * |        |          |0x5 = CRYPTO.
+     * |        |          |0x6 = USH.
+     * |        |          |0xB = PDMA1.
+     * |        |          |Others is undefined.
+     * @var SCU_T::APB1VA
+     * Offset: 0x40  APB1 Violation Address
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |VIOADDR   |Violation Address
+     * |        |          |Indicate the target address of the access, which invokes the security violation.
+     * @var SCU_T::GPIOVSRC
+     * Offset: 0x44  GPIO Security Policy Violation Source
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |MASTER    |Master Violating Security Policy
+     * |        |          |Indicate which master invokes the security violation.
+     * |        |          |0x0 = core processor.
+     * |        |          |0x3 = PDMA0.
+     * |        |          |0x4 = SDH0.
+     * |        |          |0x5 = CRYPTO.
+     * |        |          |0x6 = USH.
+     * |        |          |0xB = PDMA1.
+     * |        |          |Others is undefined.
+     * @var SCU_T::GPIOVA
+     * Offset: 0x48  GPIO Violation Address
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |VIOADDR   |Violation Address
+     * |        |          |Indicate the target address of the access, which invokes the security violation.
+     * @var SCU_T::EBIVSRC
+     * Offset: 0x4C  EBI Security Policy Violation Source
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |MASTER    |Master Violating Security Policy
+     * |        |          |Indicate which master invokes the security violation.
+     * |        |          |0x0 = core processor.
+     * |        |          |0x3 = PDMA0.
+     * |        |          |0x4 = SDH0.
+     * |        |          |0x5 = CRYPTO.
+     * |        |          |0x6 = USH.
+     * |        |          |0xB = PDMA1.
+     * |        |          |Others is undefined.
+     * @var SCU_T::EBIVA
+     * Offset: 0x50  EBI Violation Address
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |VIOADDR   |Violation Address
+     * |        |          |Indicate the target address of the access, which invokes the security violation.
+     * @var SCU_T::USBHVSRC
+     * Offset: 0x54  USBH Security Policy Violation Source
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |MASTER    |Master Violating Security Policy
+     * |        |          |Indicate which master invokes the security violation.
+     * |        |          |0x0 = core processor.
+     * |        |          |0x3 = PDMA0.
+     * |        |          |0x4 = SDH0.
+     * |        |          |0x5 = CRYPTO.
+     * |        |          |0x6 = USH.
+     * |        |          |0xB = PDMA1.
+     * |        |          |Others is undefined.
+     * @var SCU_T::USBHVA
+     * Offset: 0x58  USBH Violation Address
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |VIOADDR   |Violation Address
+     * |        |          |Indicate the target address of the access, which invokes the security violation.
+     * @var SCU_T::CRCVSRC
+     * Offset: 0x5C  CRC Security Policy Violation Source
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |MASTER    |Master Violating Security Policy
+     * |        |          |Indicate which master invokes the security violation.
+     * |        |          |0x0 = core processor.
+     * |        |          |0x3 = PDMA0.
+     * |        |          |0x4 = SDH0.
+     * |        |          |0x5 = CRYPTO.
+     * |        |          |0x6 = USH.
+     * |        |          |0xB = PDMA1.
+     * |        |          |Others is undefined.
+     * @var SCU_T::CRCVA
+     * Offset: 0x60  CRC Violation Address
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |VIOADDR   |Violation Address
+     * |        |          |Indicate the target address of the access, which invokes the security violation.
+     * @var SCU_T::SD0VSRC
+     * Offset: 0x64  SDH0 Security Policy Violation Source
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |MASTER    |Master Violating Security Policy
+     * |        |          |Indicate which master invokes the security violation.
+     * |        |          |0x0 = core processor.
+     * |        |          |0x3 = PDMA0.
+     * |        |          |0x4 = SDH0.
+     * |        |          |0x5 = CRYPTO.
+     * |        |          |0x6 = USH.
+     * |        |          |0xB = PDMA1.
+     * |        |          |Others is undefined.
+     * @var SCU_T::SD0VA
+     * Offset: 0x68  SDH0 Violation Address
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |VIOADDR   |Violation Address
+     * |        |          |Indicate the target address of the access, which invokes the security violation.
+     * @var SCU_T::PDMA0VSRC
+     * Offset: 0x74  PDMA0 Security Policy Violation Source
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |MASTER    |Master Violating Security Policy
+     * |        |          |Indicate which master invokes the security violation.
+     * |        |          |0x0 = core processor.
+     * |        |          |0x3 = PDMA0.
+     * |        |          |0x4 = SDH0.
+     * |        |          |0x5 = CRYPTO.
+     * |        |          |0x6 = USH.
+     * |        |          |0xB = PDMA1.
+     * |        |          |Others is undefined.
+     * @var SCU_T::PDMA0VA
+     * Offset: 0x78  PDMA0 Violation Address
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |VIOADDR   |Violation Address
+     * |        |          |Indicate the target address of the access, which invokes the security violation.
+     * @var SCU_T::PDMA1VSRC
+     * Offset: 0x7C  PDMA1 Security Policy Violation Source
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |MASTER    |Master Violating Security Policy
+     * |        |          |Indicate which master invokes the security violation.
+     * |        |          |0x0 = core processor.
+     * |        |          |0x3 = PDMA0.
+     * |        |          |0x4 = SDH0.
+     * |        |          |0x5 = CRYPTO.
+     * |        |          |0x6 = USH.
+     * |        |          |0xB = PDMA1.
+     * |        |          |Others is undefined.
+     * @var SCU_T::PDMA1VA
+     * Offset: 0x80  PDMA1 Violation Address
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |VIOADDR   |Violation Address
+     * |        |          |Indicate the target address of the access, which invokes the security violation.
+     * @var SCU_T::SRAM0VSRC
+     * Offset: 0x84  SRAM0 Security Policy Violation Source
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |MASTER    |Master Violating Security Policy
+     * |        |          |Indicate which master invokes the security violation.
+     * |        |          |0x0 = core processor.
+     * |        |          |0x3 = PDMA0.
+     * |        |          |0x4 = SDH0.
+     * |        |          |0x5 = CRYPTO.
+     * |        |          |0x6 = USH.
+     * |        |          |0xB = PDMA1.
+     * |        |          |Others is undefined.
+     * @var SCU_T::SRAM0VA
+     * Offset: 0x88  SRAM0 Violation Address
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |VIOADDR   |Violation Address
+     * |        |          |Indicate the target address of the access, which invokes the security violation.
+     * @var SCU_T::SRAM1VSRC
+     * Offset: 0x8C  SRAM1 Security Policy Violation Source
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |MASTER    |Master Violating Security Policy
+     * |        |          |Indicate which master invokes the security violation.
+     * |        |          |0x0 = core processor.
+     * |        |          |0x3 = PDMA0.
+     * |        |          |0x4 = SDH0.
+     * |        |          |0x5 = CRYPTO.
+     * |        |          |0x6 = USH.
+     * |        |          |0xB = PDMA1.
+     * |        |          |Others is undefined.
+     * @var SCU_T::SRAM1VA
+     * Offset: 0x90  SRAM1 Violation Address
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |VIOADDR   |Violation Address
+     * |        |          |Indicate the target address of the access, which invokes the security violation.
+     * @var SCU_T::FMCVSRC
+     * Offset: 0x94  FMC Security Policy Violation Source
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |MASTER    |Master Violating Security Policy
+     * |        |          |Indicate which master invokes the security violation.
+     * |        |          |0x0 = core processor.
+     * |        |          |0x3 = PDMA0.
+     * |        |          |0x4 = SDH0.
+     * |        |          |0x5 = CRYPTO.
+     * |        |          |0x6 = USH.
+     * |        |          |0xB = PDMA1.
+     * |        |          |Others is undefined.
+     * @var SCU_T::FMCVA
+     * Offset: 0x98  FMC Violation Address
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |VIOADDR   |Violation Address
+     * |        |          |Indicate the target address of the access, which invokes the security violation.
+     * @var SCU_T::FLASHVSRC
+     * Offset: 0x9C  Flash Security Policy Violation Source
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |MASTER    |Master Violating Security Policy
+     * |        |          |Indicate which master invokes the security violation.
+     * |        |          |0x0 = core processor.
+     * |        |          |0x3 = PDMA0.
+     * |        |          |0x4 = SDH0.
+     * |        |          |0x5 = CRYPTO.
+     * |        |          |0x6 = USH.
+     * |        |          |0xB = PDMA1.
+     * |        |          |Others is undefined.
+     * @var SCU_T::FLASHVA
+     * Offset: 0xA0  Flash Violation Address
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |VIOADDR   |Violation Address
+     * |        |          |Indicate the target address of the access, which invokes the security violation.
+     * @var SCU_T::SCUVSRC
+     * Offset: 0xA4  SCU Security Policy Violation Source
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |MASTER    |Master Violating Security Policy
+     * |        |          |Indicate which master invokes the security violation.
+     * |        |          |0x0 = core processor.
+     * |        |          |0x3 = PDMA0.
+     * |        |          |0x4 = SDH0.
+     * |        |          |0x5 = CRYPTO.
+     * |        |          |0x6 = USH.
+     * |        |          |0xB = PDMA1.
+     * |        |          |Others is undefined.
+     * @var SCU_T::SCUVA
+     * Offset: 0xA8  SCU Violation Address
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |VIOADDR   |Violation Address
+     * |        |          |Indicate the target address of the access, which invokes the security violation.
+     * @var SCU_T::SYSVSRC
+     * Offset: 0xAC  System(GMISC) Security Policy Violation Source
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |MASTER    |Master Violating Security Policy
+     * |        |          |Indicate which master invokes the security violation.
+     * |        |          |0x0 = core processor.
+     * |        |          |0x3 = PDMA0.
+     * |        |          |0x4 = SDH0.
+     * |        |          |0x5 = CRYPTO.
+     * |        |          |0x6 = USH.
+     * |        |          |0xB = PDMA1.
+     * |        |          |Others is undefined.
+     * @var SCU_T::SYSVA
+     * Offset: 0xB0  System(GMISC) Violation Address
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |VIOADDR   |Violation Address
+     * |        |          |Indicate the target address of the access, which invokes the security violation.
+     * @var SCU_T::CRPTVSRC
+     * Offset: 0xB4  Crypto Security Policy Violation Source
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |MASTER    |Master Violating Security Policy
+     * |        |          |Indicate which master invokes the security violation.
+     * |        |          |0x0 = core processor.
+     * |        |          |0x3 = PDMA0.
+     * |        |          |0x4 = SDH0.
+     * |        |          |0x5 = CRYPTO.
+     * |        |          |0x6 = USH.
+     * |        |          |0xB = PDMA1.
+     * |        |          |Others is undefined.
+     * @var SCU_T::CRPTVA
+     * Offset: 0xB8  Crypto Violation Address
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |VIOADDR   |Violation Address
+     * |        |          |Indicate the target address of the access, which invokes the security violation.
+     * @var SCU_T::KSVSRC
+     * Offset: 0xBC  KS Security Policy Violation Source
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |MASTER    |Master Violating Security Policy
+     * |        |          |Indicate which master invokes the security violation.
+     * |        |          |0x0 = core processor.
+     * |        |          |0x3 = PDMA0.
+     * |        |          |0x4 = SDH0.
+     * |        |          |0x5 = CRYPTO.
+     * |        |          |0x6 = USH.
+     * |        |          |0xB = PDMA1.
+     * |        |          |Others is undefined.
+     * @var SCU_T::KSVA
+     * Offset: 0xC0  KS Violation Address
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |VIOADDR   |Violation Address
+     * |        |          |Indicate the target address of the access, which invokes the security violation.
+     * @var SCU_T::SRAM2VSRC
+     * Offset: 0xC4  SRAM2 Security Policy Violation Source
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |MASTER    |Master Violating Security Policy
+     * |        |          |Indicate which master invokes the security violation.
+     * |        |          |0x0 = core processor.
+     * |        |          |0x3 = PDMA0.
+     * |        |          |0x4 = SDH0.
+     * |        |          |0x5 = CRYPTO.
+     * |        |          |0x6 = USH.
+     * |        |          |0xB = PDMA1.
+     * |        |          |Others is undefined.
+     * @var SCU_T::SRAM2VA
+     * Offset: 0xC8  SRAM2 Violation Address
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |VIOADDR   |Violation Address
+     * |        |          |Indicate the target address of the access, which invokes the security violation.
+     * @var SCU_T::SINFAEN
+     * Offset: 0xF0  Shared Information Access Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SCUSIAEN  |SCU Shared Information Access Enable Bit
+     * |        |          |0 = Non-secure CPU access SCU Shared information Disabled.
+     * |        |          |1 = Non-secure CPU access SCU Shared information Enabled.
+     * |[1]     |SYSSIAEN  |SYS Shared Information Access Enable Bit
+     * |        |          |0 = Non-secure CPU access SYS Shared information Disabled.
+     * |        |          |1 = Non-secure CPU access SYS Shared information Enabled.
+     * |        |          |Note:Include clock information.
+     * |[2]     |FMCSIAEN  |FMC Shared Information Access Enable Bit
+     * |        |          |0 = Non-secure CPU access FMC Shared information Disabled.
+     * |        |          |1 = Non-secure CPU access FMC Shared information Enabled.
+     * @var SCU_T::PNPSET
+     * Offset: 0x100  Peripheral Non-privileged Attribution Set Register0 (0x4000_0000~0x4001_FFFF)
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SYS       |Set SYS to Non-privileged State
+     * |        |          |0 = SYS is a privileged module (default).
+     * |        |          |1 = SYS is a non-privileged module.
+     * |[8]     |PDMA0     |Set PDMA0 to Non-privileged State
+     * |        |          |0 = PDMA0 is a privileged module (default).
+     * |        |          |1 = PDMA0 is a non-privileged module.
+     * |[9]     |USBH      |Set USBH to Non-privileged State
+     * |        |          |0 = USBH is a privileged module (default).
+     * |        |          |1 = USBH is a non-privileged module.
+     * |[12]    |FMC       |Set FMC to Non-privileged State
+     * |        |          |0 = FMC is a privileged module (default).
+     * |        |          |1 = FMC is a non-privileged module.
+     * |[13]    |SDH0      |Set SDH0 to Non-privileged State
+     * |        |          |0 = SDH0 is a privileged module (default).
+     * |        |          |1 = SDH0 is a non-privileged module.
+     * |[16]    |EBI       |Set EBI to Non-privileged State
+     * |        |          |0 = EBI is a privileged module (default).
+     * |        |          |1 = EBI is a non-privileged module.
+     * |[24]    |PDMA1     |Set PDMA1 to Non-privileged State
+     * |        |          |0 = PDMA1 is a privileged module (default).
+     * |        |          |1 = PDMA1 is a non-privileged module.
+     * Offset: 0x104  Peripheral Non-privileged Attribution Set Register1 (0x4002_0000~0x4003_FFFF)
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15]    |SCU       |Set SCU to Non-privileged State
+     * |        |          |0 = SCU is a privileged module (default).
+     * |        |          |1 = SCU is a non-privileged module.
+     * |[17]    |CRC       |Set CRC to Non-privileged State
+     * |        |          |0 = CRC is a privileged module (default).
+     * |        |          |1 = CRC is a non-privileged module.
+     * |[18]    |CRPT      |Set CRPT to Non-privileged State
+     * |        |          |0 = CRPT is a privileged module (default).
+     * |        |          |1 = CRPT is a non-privileged module.
+     * |[21]    |KS        |Set KS to Non-privileged State
+     * |        |          |0 = KS is a privileged module (default).
+     * |        |          |1 = KS is a non-privileged module.
+     * Offset: 0x108  Peripheral Non-privileged Attribution Set Register2 (0x4004_0000~0x4005_FFFF)
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WDT       |Set WDT to Non-privileged State
+     * |        |          |0 = WDT is a privileged module (default).
+     * |        |          |1 = WDT is a non-privileged module.
+     * |[1]     |RTC       |Set RTC to Non-privileged State
+     * |        |          |0 = RTC is a privileged module (default).
+     * |        |          |1 = RTC is a non-privileged module.
+     * |[2]     |EWDT      |Set EWDT to Non-privileged State
+     * |        |          |0 = EWDT is a privileged module (default).
+     * |        |          |1 = EWDT is a non-privileged module.
+     * |[3]     |EADC      |Set EADC to Non-privileged State
+     * |        |          |0 = EADC is a privileged module (default).
+     * |        |          |1 = EADC is a non-privileged module.
+     * |[5]     |ACMP01    |Set ACMP01 to Non-privileged State
+     * |        |          |0 = ACMP0, ACMP1 are privileged modules (default).
+     * |        |          |1 = ACMP0, ACMP1 are non-privileged modules.
+     * |[7]     |DAC       |Set DAC to Non-privileged State
+     * |        |          |0 = DAC is a privileged module (default).
+     * |        |          |1 = DAC is a non-privileged module.
+     * |[8]     |I2S0      |Set I2S0 to Non-privileged State
+     * |        |          |0 = I2S0 is a privileged module (default).
+     * |        |          |1 = I2S0 is a non-privileged module.
+     * |[13]    |OTG       |Set OTG to Non-privileged State
+     * |        |          |0 = OTG is a privileged module (default).
+     * |        |          |1 = OTG is a non-privileged module.
+     * |[16:14] |TMR01     |Set TMR01 to Non-privileged State
+     * |        |          |0 = TMR01 is a privileged module (default).
+     * |        |          |1 = TMR01 is a non-privileged module.
+     * |[17]    |TMR23     |Set TMR23 to Non-privileged State
+     * |        |          |0 = TMR23 is a privileged module (default).
+     * |        |          |1 = TMR23 is a non-privileged module.
+     * |[24]    |EPWM0     |Set EPWM0 to Non-privileged State
+     * |        |          |0 = EPWM0 is a privileged module (default).
+     * |        |          |1 = EPWM0 is a non-privileged module.
+     * |[25]    |EPWM1     |Set EPWM1 to Non-privileged State
+     * |        |          |0 = EPWM1 is a privileged module (default).
+     * |        |          |1 = EPWM1 is a non-privileged module.
+     * |[26]    |BPWM0     |Set BPWM0 to Non-privileged State
+     * |        |          |0 = BPWM0 is a privileged module (default).
+     * |        |          |1 = BPWM0 is a non-privileged module.
+     * |[27]    |BPWM1     |Set BPWM1 to Non-privileged State
+     * |        |          |0 = BPWM1 is a privileged module (default).
+     * |        |          |1 = BPWM1 is a non-privileged module.
+     * Offset: 0x10C  Peripheral Non-privileged Attribution Set Register3 (0x4006_0000~0x4007_FFFF)
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |QSPI0     |Set QSPI0 to Non-privileged State
+     * |        |          |0 = QSPI0 is a privileged module (default).
+     * |        |          |1 = QSPI0 is a non-privileged module.
+     * |[1]     |SPI0      |Set SPI0 to Non-privileged State
+     * |        |          |0 = SPI0 is a privileged module (default).
+     * |        |          |1 = SPI0 is a non-privileged module.
+     * |[2]     |SPI1      |Set SPI1 to Non-privileged State
+     * |        |          |0 = SPI1 is a privileged module (default).
+     * |        |          |1 = SPI1 is a non-privileged module.
+     * |[3]     |SPI2      |Set SPI2 to Non-privileged State
+     * |        |          |0 = SPI2 is a privileged module (default).
+     * |        |          |1 = SPI2 is a non-privileged module.
+     * |[4]     |SPI3      |Set SPI3 to Non-privileged State
+     * |        |          |0 = SPI3 is a privileged module (default).
+     * |        |          |1 = SPI3 is a non-privileged module.
+     * |[16]    |UART0     |Set UART0 to Non-privileged State
+     * |        |          |0 = UART0 is a privileged module (default).
+     * |        |          |1 = UART0 is a non-privileged module.
+     * |[17]    |UART1     |Set UART1 to Non-privileged State
+     * |        |          |0 = UART1 is a privileged module (default).
+     * |        |          |1 = UART1 is a non-privileged module.
+     * |[18]    |UART2     |Set UART2 to Non-privileged State
+     * |        |          |0 = UART2 is a privileged module (default).
+     * |        |          |1 = UART2 is a non-privileged module.
+     * |[19]    |UART3     |Set UART3 to Non-privileged State
+     * |        |          |0 = UART3 is a privileged module (default).
+     * |        |          |1 = UART3 is a non-privileged module.
+     * |[20]    |UART4     |Set UART4 to Non-privileged State
+     * |        |          |0 = UART4 is a privileged module (default).
+     * |        |          |1 = UART4 is a non-privileged module.
+     * |[21]    |UART5     |Set UART5 to Non-privileged State
+     * |        |          |0 = UART5 is a privileged module (default).
+     * |        |          |1 = UART5 is a non-privileged module.
+     * Offset: 0x110  Peripheral Non-privileged Attribution Set Register4 (0x4008_0000~0x4009_FFFF)
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |I2C0      |Set I2C0 to Non-privileged State
+     * |        |          |0 = I2C0 is a privileged module (default).
+     * |        |          |1 = I2C0 is a non-privileged module.
+     * |[1]     |I2C1      |Set I2C1 to Non-privileged State
+     * |        |          |0 = I2C1 is a privileged module (default).
+     * |        |          |1 = I2C1 is a non-privileged module.
+     * |[2]     |I2C2      |Set I2C2 to Non-privileged State
+     * |        |          |0 = I2C2 is a privileged module (default).
+     * |        |          |1 = I2C2 is a non-privileged module.
+     * |[16]    |SC0       |Set SC0 to Non-privileged State
+     * |        |          |0 = SC0 is a privileged module (default).
+     * |        |          |1 = SC0 is a non-privileged module.
+     * |[17]    |SC1       |Set SC1 to Non-privileged State
+     * |        |          |0 = SC1 is a privileged module (default).
+     * |        |          |1 = SC1 is a non-privileged module.
+     * |[18]    |SC2       |Set SC2 to Non-privileged State
+     * |        |          |0 = SC2 is a privileged module (default).
+     * |        |          |1 = SC2 is a non-privileged module.
+     * Offset: 0x114  Peripheral Non-privileged Attribution Set Register5 (0x400A_0000~0x400B_FFFF)
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CAN0      |Set CAN0 to Non-privileged State
+     * |        |          |0 = CAN0 is a privileged module (default).
+     * |        |          |1 = CAN0 is a non-privileged module.
+     * |[16]    |QEI0      |Set QEI0 to Non-privileged State
+     * |        |          |0 = QEI0 is a privileged module (default).
+     * |        |          |1 = QEI0 is a non-privileged module.
+     * |[17]    |QEI1      |Set QEI1 to Non-privileged State
+     * |        |          |0 = QEI1 is a privileged module (default).
+     * |        |          |1 = QEI1 is a non-privileged module.
+     * |[20]    |ECAP0     |Set ECAP0 to Non-privileged State
+     * |        |          |0 = ECAP0 is a privileged module (default).
+     * |        |          |1 = ECAP0 is a non-privileged module.
+     * |[21]    |ECAP1     |Set ECAP1 to Non-privileged State
+     * |        |          |0 = ECAP1 is a privileged module (default).
+     * |        |          |1 = ECAP1 is a non-privileged module.
+     * |[25]    |TRNG      |Set TRNG to Non-privileged State
+     * |        |          |0 = TRNG is a privileged module (default).
+     * |        |          |1 = TRNG is a non-privileged module.
+     * |[27]    |LCD       |Set LCD to Non-privileged State
+     * |        |          |0 = LCD is a privileged module (default).
+     * |        |          |1 = LCD is a non-privileged module.
+     * |[29]    |TAMPER    |Set TAMPER to Non-privileged State
+     * |        |          |0 = TAMPER is a privileged module (default).
+     * |        |          |1 = TAMPER is a non-privileged module.
+     * Offset: 0x118  Peripheral Non-privileged Attribution Set Register6 (0x400C_0000~0x400D_FFFF)
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |USBD      |Set USBD to Non-privileged State
+     * |        |          |0 = USBD is a privileged module (default).
+     * |        |          |1 = USBD is a non-privileged module.
+     * |[16]    |USCI0     |Set USCI0 to Non-privileged State
+     * |        |          |0 = USCI0 is a privileged module (default).
+     * |        |          |1 = USCI0 is a non-privileged module.
+     * |[17]    |USCI1     |Set USCI1 to Non-privileged State
+     * |        |          |0 = USCI1 is a privileged module (default).
+     * |        |          |1 = USCI1 is a non-privileged module.
+     * @var SCU_T::IONPSET
+     * Offset: 0x120  IO Non-privileged Attribution Set Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PA        |Set GPIO Port a to Non-privileged State
+     * |        |          |0 = GPIO port A is privileged (default).
+     * |        |          |1 = GPIO port A is non-privileged.
+     * |[1]     |PB        |Set GPIO Port B to Non-privileged State
+     * |        |          |0 = GPIO port B is privileged (default).
+     * |        |          |1 = GPIO port B is non-privileged.
+     * |[2]     |PC        |Set GPIO Port C to Non-privileged State
+     * |        |          |0 = GPIO port C is privileged (default).
+     * |        |          |1 = GPIO port C is non-privileged.
+     * |[3]     |PD        |Set GPIO Port D to Non-privileged State
+     * |        |          |0 = GPIO port D is privileged (default).
+     * |        |          |1 = GPIO port D is non-privileged.
+     * |[4]     |PE        |Set GPIO Port E to Nonj-privileged State
+     * |        |          |0 = GPIO port E is privileged (default).
+     * |        |          |1 = GPIO port E is non-privileged.
+     * |[5]     |PF        |Set GPIO Port F to Non-privileged State
+     * |        |          |0 = GPIO port F is privileged (default).
+     * |        |          |1 = GPIO port F is non-privileged.
+     * |[6]     |PG        |Set GPIO Port G to Non-privileged State
+     * |        |          |0 = GPIO port G is privileged (default).
+     * |        |          |1 = GPIO port G is non-privileged.
+     * |[7]     |PH        |Set GPIO Port H to Non-privileged State
+     * |        |          |0 = GPIO port H is privileged (default).
+     * |        |          |1 = GPIO port H is non-privileged.
+     * @var SCU_T::SRAMNPSET
+     * Offset: 0x124  SRAM Non-privileged Attribution Set Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[19:0]  |SECn      |Set SRAM Section n to Non-privileged State
+     * |        |          |0 = SRAM Section n is privileged (default).
+     * |        |          |1 = SRAM Section n is non-privileged.
+     * |        |          |Size per section is 16 Kbytes.
+     * |        |          |Secure SRAM section n is 0x2000_0000+0x4000*n to 0x2000_0000+0x4000*(n+1)-0x1
+     * |        |          |Non-secure SRAM section n is 0x3000_0000+0x4000*n to 0x3000_0000+0x4000*(n+1)-0x1
+     * @var SCU_T::MEMNPSET
+     * Offset: 0x128  Other Memory Non-privileged Attribution Set Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |FLASH     |Set Flash to Non-privileged State
+     * |        |          |Set the privileged state of memory ranging from 0x0000_0000 to 0x1FFF_FFFF.
+     * |        |          |0 = Flash is setting to privileged (default).
+     * |        |          |1 = Flash is setting to non-privileged.
+     * |[1]     |EXTMEM    |Set External Memory (EBI Memory) to Non-privileged State
+     * |        |          |Set the privileged state of memory ranging from 0x6000_0000 to 0x7FFF_FFFF.
+     * |        |          |0 = External Memory is setting to privileged (default).
+     * |        |          |1 = External Memory is setting to non-privileged.
+     * @var SCU_T::PVIOIEN
+     * Offset: 0x12C  Privileged Violation Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |APB0IEN   |APB0 Privileged Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from privileged violation of APB0 Disabled.
+     * |        |          |1 = Interrupt triggered from privileged violation of APB0 Enabled.
+     * |[1]     |APB1IEN   |APB1 Privileged Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from privileged violation of APB1 Disabled.
+     * |        |          |1 = Interrupt triggered from privileged violation of APB1 Enabled.
+     * |[4]     |GPIOIEN   |GPIO Privileged Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from privileged violation of GPIO Disabled.
+     * |        |          |1 = Interrupt triggered from privileged violation of GPIO Enabled.
+     * |[5]     |EBIIEN    |EBI Privileged Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from privileged violation of EBI Disabled.
+     * |        |          |1 = Interrupt triggered from privileged violation of EBI Enabled.
+     * |[6]     |USBHIEN   |USBH Privileged Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from privileged violation of USB host Disabled.
+     * |        |          |1 = Interrupt triggered from privileged violation of USB host Enabled.
+     * |[7]     |CRCIEN    |CRC Privileged Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from privileged violation of CRC Disabled.
+     * |        |          |1 = Interrupt triggered from privileged violation of CRC Enabled.
+     * |[8]     |SDH0IEN   |SDH0 Privileged Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from privileged violation of SD host 0 Disabled.
+     * |        |          |1 = Interrupt triggered from privileged violation of SD host 0 Enabled.
+     * |[10]    |PDMA0IEN  |PDMA0 Privileged Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from privileged violation of PDMA0 Disabled.
+     * |        |          |1 = Interrupt triggered from privileged violation of PDMA0 Enabled.
+     * |[11]    |PDMA1IEN  |PDMA1 Privileged Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from privileged violation of PDMA1 Disabled.
+     * |        |          |1 = Interrupt triggered from privileged violation of PDMA1 Enabled.
+     * |[12]    |SRAM0IEN  |SRAM Bank 0 Privileged Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from privileged violation of SRAM bank0 Disabled.
+     * |        |          |1 = Interrupt triggered from privileged violation of SRAM bank0 Enabled.
+     * |[13]    |SRAM1IEN  |SRAM Bank 1 Privileged Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from privileged violation of SRAM bank1 Disabled.
+     * |        |          |1 = Interrupt triggered from privileged violation of SRAM bank1 Enabled.
+     * |[14]    |FMCIEN    |FMC Privileged Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from privileged violation of FMC Disabled.
+     * |        |          |1 = Interrupt triggered from privileged violation of FMC Enabled.
+     * |[15]    |FLASHIEN  |FLASH Privileged Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from privileged violation of Flash data Disabled.
+     * |        |          |1 = Interrupt triggered from privileged violation of Flash data Enabled.
+     * |[16]    |SCUIEN    |SCU Privileged Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from privileged violation of SCU Disabled.
+     * |        |          |1 = Interrupt triggered from privileged violation of SCU Enabled.
+     * |[17]    |SYSIEN    |SYS Privileged Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from privileged violation of system manager Disabled.
+     * |        |          |1 = Interrupt triggered from privileged violation of system manager Enabled.
+     * |[18]    |CRPTIEN   |CRPT Privileged Violation Interrupt Enable Bit
+     * |        |          |0 = Interrupt triggered from privileged violation of crypto Disabled.
+     * |        |          |1 = Interrupt triggered from privileged violation of crypto Enabled.
+     * |[19]    |KSIEN     |KS Privileged Violation Interrupt Enale Bit
+     * |        |          |0 = Interrupt triggered from privileged violation of keystore Disabled.
+     * |        |          |1 = Interrupt triggered from privileged violation of keystore Enabled.
+     * @var SCU_T::PVINTSTS
+     * Offset: 0x130  Privileged Violation Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |APB0IF    |APB0 Privileged Violation Interrupt Status
+     * |        |          |0 = No APB0 violation interrupt event.
+     * |        |          |1 = There is APB0 violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[1]     |APB1IF    |APB1 Privileged Violation Interrupt Status
+     * |        |          |0 = No APB1 violation interrupt event.
+     * |        |          |1 = There is APB1 violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[4]     |GPIOIF    |GPIO Privileged Violation Interrupt Status
+     * |        |          |0 = No GPIO violation interrupt event.
+     * |        |          |1 = There is GPIO violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[5]     |EBIIF     |EBI Privileged Violation Interrupt Status
+     * |        |          |0 = No EBI violation interrupt event.
+     * |        |          |1 = There is EBI violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[6]     |USBHIF    |USBH Privileged Violation Interrupt Status
+     * |        |          |0 = No USBH violation interrupt event.
+     * |        |          |1 = There is USBH violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[7]     |CRCIF     |CRC Privileged Violation Interrupt Status
+     * |        |          |0 = No CRC violation interrupt event.
+     * |        |          |1 = There is CRC violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[8]     |SDH0IF    |SDH0 Privileged Violation Interrupt Status
+     * |        |          |0 = No SDH0 violation interrupt event.
+     * |        |          |1 = There is SDH0 violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[10]    |PDMA0IF   |PDMA0 Privileged Violation Interrupt Status
+     * |        |          |0 = No PDMA0 violation interrupt event.
+     * |        |          |1 = There is PDMA0 violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[11]    |PDMA1IF   |PDMA1 Privileged Violation Interrupt Status
+     * |        |          |0 = No PDMA1 violation interrupt event.
+     * |        |          |1 = There is PDMA1 violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[12]    |SRAM0IF   |SRAM0 Privileged Violation Interrupt Status
+     * |        |          |0 = No SRAM0 violation interrupt event.
+     * |        |          |1 = There is SRAM0 violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[13]    |SRAM1IF   |SRAM Bank 1 Privileged Violation Interrupt Status
+     * |        |          |0 = No SRAM1 violation interrupt event.
+     * |        |          |1 = There is SRAM1 violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[14]    |FMCIF     |FMC Privileged Violation Interrupt Status
+     * |        |          |0 = No FMC violation interrupt event.
+     * |        |          |1 = There is FMC violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[15]    |FLASHIF   |FLASH Privileged Violation Interrupt Status
+     * |        |          |0 = No FLASH violation interrupt event.
+     * |        |          |1 = There is FLASH violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[16]    |SCUIF     |SCU Privileged Violation Interrupt Status
+     * |        |          |0 = No SCU violation interrupt event.
+     * |        |          |1 = There is SCU violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[17]    |SYSIF     |SYS Privileged Violation Interrupt Status
+     * |        |          |0 = No SYS violation interrupt event.
+     * |        |          |1 = There is SYS violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[18]    |CRPTIF    |CRPT Privileged Violation Interrupt Status
+     * |        |          |0 = No CRPT violation interrupt event.
+     * |        |          |1 = There is CRPT violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * |[19]    |KSIF      |KS Privileged Violation Interrupt Status
+     * |        |          |0 = No KS violation interrupt event.
+     * |        |          |1 = There is KS violation interrupt event.
+     * |        |          |Note: Write 1 to clear the interrupt flag.
+     * @var SCU_T::NSMCTL
+     * Offset: 0x200  Non-secure State Monitor Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |PRESCALE  |Pre-scale Value of Non-secure State Monitor Counter
+     * |        |          |0 = Counter Disabled.
+     * |        |          |Others = Counter Enabled and the counter clock source = HCLK/PRESCALE.
+     * |[8]     |NSMIEN    |Non-secure State Monitor Interrupt Enable Bit
+     * |        |          |0 = Non-secure state monitor interrupt Disabled.
+     * |        |          |1 = Non-secure state monitor interrupt Enabled.
+     * |[9]     |AUTORLD   |Auto Reload Non-secure State Monitor Counter When CURRNS Changing to 1
+     * |        |          |0 = Disable clearing non-secure state monitor counter automtically (default).
+     * |        |          |1 = Enable clearing non-secure state monitor counter automatically when the core processor changes from secure state to non-secure state
+     * |        |          |(i.e.when CURRNS chagned from 0 to 1).
+     * |[10]    |TMRMOD    |Non-secure Monitor Mode Enable Bit
+     * |        |          |0 = Monitor mode. The counter will count down when the core processor is in non-secure state. (default)
+     * |        |          |1 = Free-counting mode
+     * |        |          |The counter will keep counting no mater the core processor is in secure or non-secure state.
+     * |[12]    |IDLEON    |Monitor Counter Keep Counting When the Chip Is in Idle Mode Enable Bit
+     * |        |          |0 = The counter will be halted when the chip is in idle mode.
+     * |        |          |1 = The counter will keep counting when the chip is in idle mode. (default)
+     * |        |          |Note: In monitor mode, the counter is always halted when the core processor is in secure state.
+     * |[13]    |DBGON     |Monitor Counter Keep Counting When the Chip Is in Debug Mode Enable Bit
+     * |        |          |0 = The counter will be halted when the core processor is halted by ICE. (default)
+     * |        |          |1 = The counter will keep counting when the core processor is halted by ICE.
+     * @var SCU_T::NSMLOAD
+     * Offset: 0x204  Non-secure State Monitor Reload Value Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:0]  |RELOAD    |Reload Value for Non-secure State Monitor Counter
+     * |        |          |The RELOAD value will be reloaded to the counter whenever the counter counts down to 0.
+     * @var SCU_T::NSMVAL
+     * Offset: 0x208  Non-secure State Monitor Counter Value Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:0]  |VALUE     |Counter Value of Non-secure State Monitor Counter
+     * |        |          |Current value of non-secure state monitor counter
+     * |        |          |This is down counter and counts down only when CURRNS = 1
+     * |        |          |When counting down to 0, VALUE will automatically be reloaded from NSMLOAD register.
+     * |        |          |A write of any value clears the VALUE to 0 and also clears NSMIF.
+     * @var SCU_T::NSMSTS
+     * Offset: 0x20C  Non-secure State Monitor Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CURRNS    |Current Core Processor Secure/Non-secure State (Read Only)
+     * |        |          |0 = Core processor is in secure state.
+     * |        |          |1 = Core processor is in non-secure state.
+     * |        |          |Note: This bit can be used to monitor the current secure/non-secure state of the core processor, even if the non-secure state monitor counter is disabled.
+     * |[1]     |NSMIF     |Non-secure State Monitor Interrupt Flag
+     * |        |          |0 = Counter doesnu2019t count down to 0 since the last NSMIF has been cleared.
+     * |        |          |1 = Counter counts down to 0.
+     * |        |          |Note: This bit is cleared by writing 1.
+     * @var SCU_T::BBE
+     * Offset: 0x300  Block Bus Error Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BBEEN     |Block Bus-error Enable Bit
+     * |        |          |0 = Disable Blocking Bus Error to the core processor.
+     * |        |          |1 = Enable Blocking Bus Error to the core processor.
+     * |        |          |This bit is double write-protected, WRVERY and SYS_REGLCTL register.
+     * |[31:8]  |WVERY     |Write Verify Code
+     * |        |          |In order to write BBEEN bit, the code should be set as 0x59475A.
+     * |        |          |When read access, the return value of this field is always 0.
+     * @var SCU_T::IDAUANS
+     * Offset: 0x304  IDAU All Non-secure Set Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |IDAUANSEN |IDAU All Non-secure Enable Bit
+     * |        |          |0 = Disable IDAU sets all region Non-secure.
+     * |        |          |1 = Enable IDAU sets all region Non-secure.
+     * |        |          |This bit is double write-protected, WRVERY and SYS_REGLCTL register.
+     * |[31:8]  |WVERY     |Write Verify Code
+     * |        |          |In order to write BBEEN bit, the code should be set as 0x59475A.
+     * |        |          |When read access, the return value of this field is always 0.
+     * @var SCU_T::VERSION
+     * Offset: 0xFFC  SCU RTL Design Version Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |MINOR     |SCU RTL Design Minor Version
+     * |        |          |Minor version number is dependent on ECO version control.
+     * |[23:16] |SUB       |SCU RTL Design Sub Version Number
+     * |        |          |Major version number is correlated to product line.
+     * |[31:24] |MAJOR     |SCU RTL Design Major Version Number
+     * |        |          |Major version number is correlated to product line.
+     */
+    __IO uint32_t PNSSET[7];             /*!< [0x0000:0x0018] Peripheral Non-secure Attribution Set Register0 (0x4000_0000~0x400D_FFFF) */
+    __I  uint32_t RESERVE0[2];
+    __IO uint32_t SRAMNSSET;             /*!< [0x0024] SRAM Non-secure Attribution Set Register                         */
+    __I  uint32_t FNSADDR;               /*!< [0x0028] Flash Non-secure Boundary Address Register                       */
+    __IO uint32_t SVIOIEN;               /*!< [0x002c] Security Violation Interrupt Enable Register                     */
+    __IO uint32_t SVINTSTS;              /*!< [0x0030] Security Violation Interrupt Status Register                     */
+    __I  uint32_t APB0VSRC;              /*!< [0x0034] APB0 Security Policy Violation Source                            */
+    __I  uint32_t APB0VA;                /*!< [0x0038] APB0 Violation Address                                           */
+    __I  uint32_t APB1VSRC;              /*!< [0x003c] APB1 Security Policy Violation Source                            */
+    __I  uint32_t APB1VA;                /*!< [0x0040] APB1 Violation Address                                           */
+    __I  uint32_t GPIOVSRC;              /*!< [0x0044] GPIO Security Policy Violation Source                            */
+    __I  uint32_t GPIOVA;                /*!< [0x0048] GPIO Violation Address                                           */
+    __I  uint32_t EBIVSRC;               /*!< [0x004c] EBI Security Policy Violation Source                             */
+    __I  uint32_t EBIVA;                 /*!< [0x0050] EBI Violation Address                                            */
+    __I  uint32_t USBHVSRC;              /*!< [0x0054] USBH Security Policy Violation Source                            */
+    __I  uint32_t USBHVA;                /*!< [0x0058] USBH Violation Address                                           */
+    __I  uint32_t CRCVSRC;               /*!< [0x005c] CRC Security Policy Violation Source                             */
+    __I  uint32_t CRCVA;                 /*!< [0x0060] CRC Violation Address                                            */
+    __I  uint32_t SD0VSRC;               /*!< [0x0064] SDH0 Security Policy Violation Source                            */
+    __I  uint32_t SD0VA;                 /*!< [0x0068] SDH0 Violation Address                                           */
+    __I  uint32_t RESERVE1[2];
+    __I  uint32_t PDMA0VSRC;             /*!< [0x0074] PDMA0 Security Policy Violation Source                           */
+    __I  uint32_t PDMA0VA;               /*!< [0x0078] PDMA0 Violation Address                                          */
+    __I  uint32_t PDMA1VSRC;             /*!< [0x007c] PDMA1 Security Policy Violation Source                           */
+    __I  uint32_t PDMA1VA;               /*!< [0x0080] PDMA1 Violation Address                                          */
+    __I  uint32_t SRAM0VSRC;             /*!< [0x0084] SRAM0 Security Policy Violation Source                           */
+    __I  uint32_t SRAM0VA;               /*!< [0x0088] SRAM0 Violation Address                                          */
+    __I  uint32_t SRAM1VSRC;             /*!< [0x008c] SRAM1 Security Policy Violation Source                           */
+    __I  uint32_t SRAM1VA;               /*!< [0x0090] SRAM1 Violation Address                                          */
+    __I  uint32_t FMCVSRC;               /*!< [0x0094] FMC Security Policy Violation Source                             */
+    __I  uint32_t FMCVA;                 /*!< [0x0098] FMC Violation Address                                            */
+    __I  uint32_t FLASHVSRC;             /*!< [0x009c] Flash Security Policy Violation Source                           */
+    __I  uint32_t FLASHVA;               /*!< [0x00a0] Flash Violation Address                                          */
+    __I  uint32_t SCUVSRC;               /*!< [0x00a4] SCU Security Policy Violation Source                             */
+    __I  uint32_t SCUVA;                 /*!< [0x00a8] SCU Violation Address                                            */
+    __I  uint32_t SYSVSRC;               /*!< [0x00ac] System(GMISC) Security Policy Violation Source                   */
+    __I  uint32_t SYSVA;                 /*!< [0x00b0] System(GMISC) Violation Address                                  */
+    __I  uint32_t CRPTVSRC;              /*!< [0x00b4] Crypto Security Policy Violation Source                          */
+    __I  uint32_t CRPTVA;                /*!< [0x00b8] Crypto Violation Address                                         */
+    __I  uint32_t KSVSRC;                /*!< [0x00bc] KS Security Policy Violation Source                              */
+    __I  uint32_t KSVA;                  /*!< [0x00c0] KS Violation Address                                             */
+    __I  uint32_t SRAM2VSRC;             /*!< [0x00c4] SRAM2 Security Policy Violation Source                           */
+    __I  uint32_t SRAM2VA;               /*!< [0x00c8] SRAM2 Violation Address                                          */
+    __I  uint32_t RESERVE2[9];
+    __IO uint32_t SINFAEN;               /*!< [0x00f0] Shared Information Access Enable Register                        */
+    __I  uint32_t RESERVE3[3];
+    __IO uint32_t PNPSET[7];             /*!< [0x0100:0x0118] Peripheral Non-privileged Attribution Set Register0 (0x4000_0000~0x400D_FFFF) */
+    __I  uint32_t RESERVE4[1];
+    __IO uint32_t IONPSET;               /*!< [0x0120] IO Non-privileged Attribution Set Register                       */
+    __IO uint32_t SRAMNPSET;             /*!< [0x0124] SRAM Non-privileged Attribution Set Register                     */
+    __IO uint32_t MEMNPSET;              /*!< [0x0128] Other Memory Non-privileged Attribution Set Register             */
+    __IO uint32_t PVIOIEN;               /*!< [0x012c] Privileged Violation Interrupt Enable Register                   */
+    __IO uint32_t PVINTSTS;              /*!< [0x0130] Privileged Violation Interrupt Status Register                   */
+    __I  uint32_t RESERVE5[3];
+    __IO uint32_t IONSSET[8];            /*!< [0x0140:0x015C] IO Non-secure Attribution Set Register                    */
+    __I  uint32_t RESERVE6[40];
+    __IO uint32_t NSMCTL;                /*!< [0x0200] Non-secure State Monitor Control Register                        */
+    __IO uint32_t NSMLOAD;               /*!< [0x0204] Non-secure State Monitor Reload Value Register                   */
+    __IO uint32_t NSMVAL;                /*!< [0x0208] Non-secure State Monitor Counter Value Register                  */
+    __IO uint32_t NSMSTS;                /*!< [0x020c] Non-secure State Monitor Status Register                         */
+    __I  uint32_t RESERVE7[60];
+    __IO uint32_t BBE;                   /*!< [0x0300] Block Bus Error Register                                         */
+    __IO uint32_t IDAUANS;               /*!< [0x0304] IDAU All Non-secure Set Register                                 */
+    __I  uint32_t RESERVE8[829];
+    __I  uint32_t VERSION;               /*!< [0x0ffc] SCU RTL Design Version Register                                  */
+
+} SCU_T;
+
+/**
+    @addtogroup SCU_CONST SCU Bit Field Definition
+    Constant Definitions for SCU Controller
+  @{
+*/
+
+#define SCU_PNSSET0_USBH_Pos             (9)                                               /*!< SCU_T::PNSSET0: USBH Position          */
+#define SCU_PNSSET0_USBH_Msk             (0x1ul << SCU_PNSSET0_USBH_Pos)                   /*!< SCU_T::PNSSET0: USBH Mask              */
+
+#define SCU_PNSSET0_SDH0_Pos             (13)                                              /*!< SCU_T::PNSSET0: SDH0 Position          */
+#define SCU_PNSSET0_SDH0_Msk             (0x1ul << SCU_PNSSET0_SDH0_Pos)                   /*!< SCU_T::PNSSET0: SDH0 Mask              */
+
+#define SCU_PNSSET0_EBI_Pos              (16)                                              /*!< SCU_T::PNSSET0: EBI Position           */
+#define SCU_PNSSET0_EBI_Msk              (0x1ul << SCU_PNSSET0_EBI_Pos)                    /*!< SCU_T::PNSSET0: EBI Mask               */
+
+#define SCU_PNSSET0_PDMA1_Pos            (24)                                              /*!< SCU_T::PNSSET0: PDMA1 Position         */
+#define SCU_PNSSET0_PDMA1_Msk            (0x1ul << SCU_PNSSET0_PDMA1_Pos)                  /*!< SCU_T::PNSSET0: PDMA1 Mask             */
+
+#define SCU_PNSSET1_CRC_Pos              (17)                                              /*!< SCU_T::PNSSET1: CRC Position           */
+#define SCU_PNSSET1_CRC_Msk              (0x1ul << SCU_PNSSET1_CRC_Pos)                    /*!< SCU_T::PNSSET1: CRC Mask               */
+
+#define SCU_PNSSET1_CRPT_Pos             (18)                                              /*!< SCU_T::PNSSET1: CRPT Position          */
+#define SCU_PNSSET1_CRPT_Msk             (0x1ul << SCU_PNSSET1_CRPT_Pos)                   /*!< SCU_T::PNSSET1: CRPT Mask              */
+
+#define SCU_PNSSET2_EWDT_Pos             (2)                                               /*!< SCU_T::PNSSET2: EWDT Position          */
+#define SCU_PNSSET2_EWDT_Msk             (0x1ul << SCU_PNSSET2_EWDT_Pos)                   /*!< SCU_T::PNSSET2: EWDT Mask              */
+
+#define SCU_PNSSET2_EADC_Pos             (3)                                               /*!< SCU_T::PNSSET2: EADC Position          */
+#define SCU_PNSSET2_EADC_Msk             (0x1ul << SCU_PNSSET2_EADC_Pos)                   /*!< SCU_T::PNSSET2: EADC Mask              */
+
+#define SCU_PNSSET2_ACMP01_Pos           (5)                                               /*!< SCU_T::PNSSET2: ACMP01 Position        */
+#define SCU_PNSSET2_ACMP01_Msk           (0x1ul << SCU_PNSSET2_ACMP01_Pos)                 /*!< SCU_T::PNSSET2: ACMP01 Mask            */
+
+#define SCU_PNSSET2_DAC_Pos              (7)                                               /*!< SCU_T::PNSSET2: DAC Position           */
+#define SCU_PNSSET2_DAC_Msk              (0x1ul << SCU_PNSSET2_DAC_Pos)                    /*!< SCU_T::PNSSET2: DAC Mask               */
+
+#define SCU_PNSSET2_I2S0_Pos             (8)                                               /*!< SCU_T::PNSSET2: I2S0 Position          */
+#define SCU_PNSSET2_I2S0_Msk             (0x1ul << SCU_PNSSET2_I2S0_Pos)                   /*!< SCU_T::PNSSET2: I2S0 Mask              */
+
+#define SCU_PNSSET2_OTG_Pos              (13)                                              /*!< SCU_T::PNSSET2: OTG Position           */
+#define SCU_PNSSET2_OTG_Msk              (0x1ul << SCU_PNSSET2_OTG_Pos)                    /*!< SCU_T::PNSSET2: OTG Mask               */
+
+#define SCU_PNSSET2_TMR23_Pos            (17)                                              /*!< SCU_T::PNSSET2: TMR23 Position         */
+#define SCU_PNSSET2_TMR23_Msk            (0x1ul << SCU_PNSSET2_TMR23_Pos)                  /*!< SCU_T::PNSSET2: TMR23 Mask             */
+
+#define SCU_PNSSET2_EPWM0_Pos            (24)                                              /*!< SCU_T::PNSSET2: EPWM0 Position         */
+#define SCU_PNSSET2_EPWM0_Msk            (0x1ul << SCU_PNSSET2_EPWM0_Pos)                  /*!< SCU_T::PNSSET2: EPWM0 Mask             */
+
+#define SCU_PNSSET2_EPWM1_Pos            (25)                                              /*!< SCU_T::PNSSET2: EPWM1 Position         */
+#define SCU_PNSSET2_EPWM1_Msk            (0x1ul << SCU_PNSSET2_EPWM1_Pos)                  /*!< SCU_T::PNSSET2: EPWM1 Mask             */
+
+#define SCU_PNSSET2_BPWM0_Pos            (26)                                              /*!< SCU_T::PNSSET2: BPWM0 Position         */
+#define SCU_PNSSET2_BPWM0_Msk            (0x1ul << SCU_PNSSET2_BPWM0_Pos)                  /*!< SCU_T::PNSSET2: BPWM0 Mask             */
+
+#define SCU_PNSSET2_BPWM1_Pos            (27)                                              /*!< SCU_T::PNSSET2: BPWM1 Position         */
+#define SCU_PNSSET2_BPWM1_Msk            (0x1ul << SCU_PNSSET2_BPWM1_Pos)                  /*!< SCU_T::PNSSET2: BPWM1 Mask             */
+
+#define SCU_PNSSET3_QSPI0_Pos            (0)                                               /*!< SCU_T::PNSSET3: QSPI0 Position         */
+#define SCU_PNSSET3_QSPI0_Msk            (0x1ul << SCU_PNSSET3_QSPI0_Pos)                  /*!< SCU_T::PNSSET3: QSPI0 Mask             */
+
+#define SCU_PNSSET3_SPI0_Pos             (1)                                               /*!< SCU_T::PNSSET3: SPI0 Position          */
+#define SCU_PNSSET3_SPI0_Msk             (0x1ul << SCU_PNSSET3_SPI0_Pos)                   /*!< SCU_T::PNSSET3: SPI0 Mask              */
+
+#define SCU_PNSSET3_SPI1_Pos             (2)                                               /*!< SCU_T::PNSSET3: SPI1 Position          */
+#define SCU_PNSSET3_SPI1_Msk             (0x1ul << SCU_PNSSET3_SPI1_Pos)                   /*!< SCU_T::PNSSET3: SPI1 Mask              */
+
+#define SCU_PNSSET3_SPI2_Pos             (3)                                               /*!< SCU_T::PNSSET3: SPI2 Position          */
+#define SCU_PNSSET3_SPI2_Msk             (0x1ul << SCU_PNSSET3_SPI2_Pos)                   /*!< SCU_T::PNSSET3: SPI2 Mask              */
+
+#define SCU_PNSSET3_SPI3_Pos             (4)                                               /*!< SCU_T::PNSSET3: SPI3 Position          */
+#define SCU_PNSSET3_SPI3_Msk             (0x1ul << SCU_PNSSET3_SPI3_Pos)                   /*!< SCU_T::PNSSET3: SPI3 Mask              */
+
+#define SCU_PNSSET3_UART0_Pos            (16)                                              /*!< SCU_T::PNSSET3: UART0 Position         */
+#define SCU_PNSSET3_UART0_Msk            (0x1ul << SCU_PNSSET3_UART0_Pos)                  /*!< SCU_T::PNSSET3: UART0 Mask             */
+
+#define SCU_PNSSET3_UART1_Pos            (17)                                              /*!< SCU_T::PNSSET3: UART1 Position         */
+#define SCU_PNSSET3_UART1_Msk            (0x1ul << SCU_PNSSET3_UART1_Pos)                  /*!< SCU_T::PNSSET3: UART1 Mask             */
+
+#define SCU_PNSSET3_UART2_Pos            (18)                                              /*!< SCU_T::PNSSET3: UART2 Position         */
+#define SCU_PNSSET3_UART2_Msk            (0x1ul << SCU_PNSSET3_UART2_Pos)                  /*!< SCU_T::PNSSET3: UART2 Mask             */
+
+#define SCU_PNSSET3_UART3_Pos            (19)                                              /*!< SCU_T::PNSSET3: UART3 Position         */
+#define SCU_PNSSET3_UART3_Msk            (0x1ul << SCU_PNSSET3_UART3_Pos)                  /*!< SCU_T::PNSSET3: UART3 Mask             */
+
+#define SCU_PNSSET3_UART4_Pos            (20)                                              /*!< SCU_T::PNSSET3: UART4 Position         */
+#define SCU_PNSSET3_UART4_Msk            (0x1ul << SCU_PNSSET3_UART4_Pos)                  /*!< SCU_T::PNSSET3: UART4 Mask             */
+
+#define SCU_PNSSET3_UART5_Pos            (21)                                              /*!< SCU_T::PNSSET3: UART5 Position         */
+#define SCU_PNSSET3_UART5_Msk            (0x1ul << SCU_PNSSET3_UART5_Pos)                  /*!< SCU_T::PNSSET3: UART5 Mask             */
+
+#define SCU_PNSSET4_I2C0_Pos             (0)                                               /*!< SCU_T::PNSSET4: I2C0 Position          */
+#define SCU_PNSSET4_I2C0_Msk             (0x1ul << SCU_PNSSET4_I2C0_Pos)                   /*!< SCU_T::PNSSET4: I2C0 Mask              */
+
+#define SCU_PNSSET4_I2C1_Pos             (1)                                               /*!< SCU_T::PNSSET4: I2C1 Position          */
+#define SCU_PNSSET4_I2C1_Msk             (0x1ul << SCU_PNSSET4_I2C1_Pos)                   /*!< SCU_T::PNSSET4: I2C1 Mask              */
+
+#define SCU_PNSSET4_I2C2_Pos             (2)                                               /*!< SCU_T::PNSSET4: I2C2 Position          */
+#define SCU_PNSSET4_I2C2_Msk             (0x1ul << SCU_PNSSET4_I2C2_Pos)                   /*!< SCU_T::PNSSET4: I2C2 Mask              */
+
+#define SCU_PNSSET4_SC0_Pos              (16)                                              /*!< SCU_T::PNSSET4: SC0 Position           */
+#define SCU_PNSSET4_SC0_Msk              (0x1ul << SCU_PNSSET4_SC0_Pos)                    /*!< SCU_T::PNSSET4: SC0 Mask               */
+
+#define SCU_PNSSET4_SC1_Pos              (17)                                              /*!< SCU_T::PNSSET4: SC1 Position           */
+#define SCU_PNSSET4_SC1_Msk              (0x1ul << SCU_PNSSET4_SC1_Pos)                    /*!< SCU_T::PNSSET4: SC1 Mask               */
+
+#define SCU_PNSSET4_SC2_Pos              (18)                                              /*!< SCU_T::PNSSET4: SC2 Position           */
+#define SCU_PNSSET4_SC2_Msk              (0x1ul << SCU_PNSSET4_SC2_Pos)                    /*!< SCU_T::PNSSET4: SC2 Mask               */
+
+#define SCU_PNSSET5_CAN0_Pos             (0)                                               /*!< SCU_T::PNSSET5: CAN0 Position          */
+#define SCU_PNSSET5_CAN0_Msk             (0x1ul << SCU_PNSSET5_CAN0_Pos)                   /*!< SCU_T::PNSSET5: CAN0 Mask              */
+
+#define SCU_PNSSET5_QEI0_Pos             (16)                                              /*!< SCU_T::PNSSET5: QEI0 Position          */
+#define SCU_PNSSET5_QEI0_Msk             (0x1ul << SCU_PNSSET5_QEI0_Pos)                   /*!< SCU_T::PNSSET5: QEI0 Mask              */
+
+#define SCU_PNSSET5_QEI1_Pos             (17)                                              /*!< SCU_T::PNSSET5: QEI1 Position          */
+#define SCU_PNSSET5_QEI1_Msk             (0x1ul << SCU_PNSSET5_QEI1_Pos)                   /*!< SCU_T::PNSSET5: QEI1 Mask              */
+
+#define SCU_PNSSET5_ECAP0_Pos            (20)                                              /*!< SCU_T::PNSSET5: ECAP0 Position         */
+#define SCU_PNSSET5_ECAP0_Msk            (0x1ul << SCU_PNSSET5_ECAP0_Pos)                  /*!< SCU_T::PNSSET5: ECAP0 Mask             */
+
+#define SCU_PNSSET5_ECAP1_Pos            (21)                                              /*!< SCU_T::PNSSET5: ECAP1 Position         */
+#define SCU_PNSSET5_ECAP1_Msk            (0x1ul << SCU_PNSSET5_ECAP1_Pos)                  /*!< SCU_T::PNSSET5: ECAP1 Mask             */
+
+#define SCU_PNSSET5_TRNG_Pos             (25)                                              /*!< SCU_T::PNSSET5: TRNG Position          */
+#define SCU_PNSSET5_TRNG_Msk             (0x1ul << SCU_PNSSET5_TRNG_Pos)                   /*!< SCU_T::PNSSET5: TRNG Mask              */
+
+#define SCU_PNSSET5_LCD_Pos              (27)                                              /*!< SCU_T::PNSSET5: LCD Position           */
+#define SCU_PNSSET5_LCD_Msk              (0x1ul << SCU_PNSSET5_LCD_Pos)                    /*!< SCU_T::PNSSET5: LCD Mask               */
+
+#define SCU_PNSSET6_USBD_Pos             (0)                                               /*!< SCU_T::PNSSET6: USBD Position          */
+#define SCU_PNSSET6_USBD_Msk             (0x1ul << SCU_PNSSET6_USBD_Pos)                   /*!< SCU_T::PNSSET6: USBD Mask              */
+
+#define SCU_PNSSET6_USCI0_Pos            (16)                                              /*!< SCU_T::PNSSET6: USCI0 Position         */
+#define SCU_PNSSET6_USCI0_Msk            (0x1ul << SCU_PNSSET6_USCI0_Pos)                  /*!< SCU_T::PNSSET6: USCI0 Mask             */
+
+#define SCU_PNSSET6_USCI1_Pos            (17)                                              /*!< SCU_T::PNSSET6: USCI1 Position         */
+#define SCU_PNSSET6_USCI1_Msk            (0x1ul << SCU_PNSSET6_USCI1_Pos)                  /*!< SCU_T::PNSSET6: USCI1 Mask             */
+
+#define SCU_IONSSET_PA_Pos               (0)                                               /*!< SCU_T::IONSSET: PA Position            */
+#define SCU_IONSSET_PA_Msk               (0x1ul << SCU_IONSSET_PA_Pos)                     /*!< SCU_T::IONSSET: PA Mask                */
+
+#define SCU_IONSSET_PB_Pos               (1)                                               /*!< SCU_T::IONSSET: PB Position            */
+#define SCU_IONSSET_PB_Msk               (0x1ul << SCU_IONSSET_PB_Pos)                     /*!< SCU_T::IONSSET: PB Mask                */
+
+#define SCU_IONSSET_PC_Pos               (2)                                               /*!< SCU_T::IONSSET: PC Position            */
+#define SCU_IONSSET_PC_Msk               (0x1ul << SCU_IONSSET_PC_Pos)                     /*!< SCU_T::IONSSET: PC Mask                */
+
+#define SCU_IONSSET_PD_Pos               (3)                                               /*!< SCU_T::IONSSET: PD Position            */
+#define SCU_IONSSET_PD_Msk               (0x1ul << SCU_IONSSET_PD_Pos)                     /*!< SCU_T::IONSSET: PD Mask                */
+
+#define SCU_IONSSET_PE_Pos               (4)                                               /*!< SCU_T::IONSSET: PE Position            */
+#define SCU_IONSSET_PE_Msk               (0x1ul << SCU_IONSSET_PE_Pos)                     /*!< SCU_T::IONSSET: PE Mask                */
+
+#define SCU_IONSSET_PF_Pos               (5)                                               /*!< SCU_T::IONSSET: PF Position            */
+#define SCU_IONSSET_PF_Msk               (0x1ul << SCU_IONSSET_PF_Pos)                     /*!< SCU_T::IONSSET: PF Mask                */
+
+#define SCU_IONSSET_PG_Pos               (6)                                               /*!< SCU_T::IONSSET: PG Position            */
+#define SCU_IONSSET_PG_Msk               (0x1ul << SCU_IONSSET_PG_Pos)                     /*!< SCU_T::IONSSET: PG Mask                */
+
+#define SCU_IONSSET_PH_Pos               (7)                                               /*!< SCU_T::IONSSET: PH Position            */
+#define SCU_IONSSET_PH_Msk               (0x1ul << SCU_IONSSET_PH_Pos)                     /*!< SCU_T::IONSSET: PH Mask                */
+
+#define SCU_SRAMNSSET_SECn_Pos           (0)                                               /*!< SCU_T::SRAMNSSET: SECn Position        */
+#define SCU_SRAMNSSET_SECn_Msk           (0xffful << SCU_SRAMNSSET_SECn_Pos)               /*!< SCU_T::SRAMNSSET: SECn Mask            */
+
+#define SCU_FNSADDR_FNSADDR_Pos          (0)                                               /*!< SCU_T::FNSADDR: FNSADDR Position       */
+#define SCU_FNSADDR_FNSADDR_Msk          (0xfffffffful << SCU_FNSADDR_FNSADDR_Pos)         /*!< SCU_T::FNSADDR: FNSADDR Mask           */
+
+#define SCU_SVIOIEN_APB0IEN_Pos          (0)                                               /*!< SCU_T::SVIOIEN: APB0IEN Position       */
+#define SCU_SVIOIEN_APB0IEN_Msk          (0x1ul << SCU_SVIOIEN_APB0IEN_Pos)                /*!< SCU_T::SVIOIEN: APB0IEN Mask           */
+
+#define SCU_SVIOIEN_APB1IEN_Pos          (1)                                               /*!< SCU_T::SVIOIEN: APB1IEN Position       */
+#define SCU_SVIOIEN_APB1IEN_Msk          (0x1ul << SCU_SVIOIEN_APB1IEN_Pos)                /*!< SCU_T::SVIOIEN: APB1IEN Mask           */
+
+#define SCU_SVIOIEN_GPIOIEN_Pos          (4)                                               /*!< SCU_T::SVIOIEN: GPIOIEN Position       */
+#define SCU_SVIOIEN_GPIOIEN_Msk          (0x1ul << SCU_SVIOIEN_GPIOIEN_Pos)                /*!< SCU_T::SVIOIEN: GPIOIEN Mask           */
+
+#define SCU_SVIOIEN_EBIIEN_Pos           (5)                                               /*!< SCU_T::SVIOIEN: EBIIEN Position        */
+#define SCU_SVIOIEN_EBIIEN_Msk           (0x1ul << SCU_SVIOIEN_EBIIEN_Pos)                 /*!< SCU_T::SVIOIEN: EBIIEN Mask            */
+
+#define SCU_SVIOIEN_USBHIEN_Pos          (6)                                               /*!< SCU_T::SVIOIEN: USBHIEN Position       */
+#define SCU_SVIOIEN_USBHIEN_Msk          (0x1ul << SCU_SVIOIEN_USBHIEN_Pos)                /*!< SCU_T::SVIOIEN: USBHIEN Mask           */
+
+#define SCU_SVIOIEN_CRCIEN_Pos           (7)                                               /*!< SCU_T::SVIOIEN: CRCIEN Position        */
+#define SCU_SVIOIEN_CRCIEN_Msk           (0x1ul << SCU_SVIOIEN_CRCIEN_Pos)                 /*!< SCU_T::SVIOIEN: CRCIEN Mask            */
+
+#define SCU_SVIOIEN_SDH0IEN_Pos          (8)                                               /*!< SCU_T::SVIOIEN: SDH0IEN Position       */
+#define SCU_SVIOIEN_SDH0IEN_Msk          (0x1ul << SCU_SVIOIEN_SDH0IEN_Pos)                /*!< SCU_T::SVIOIEN: SDH0IEN Mask           */
+
+#define SCU_SVIOIEN_PDMA0IEN_Pos         (10)                                              /*!< SCU_T::SVIOIEN: PDMA0IEN Position      */
+#define SCU_SVIOIEN_PDMA0IEN_Msk         (0x1ul << SCU_SVIOIEN_PDMA0IEN_Pos)               /*!< SCU_T::SVIOIEN: PDMA0IEN Mask          */
+
+#define SCU_SVIOIEN_PDMA1IEN_Pos         (11)                                              /*!< SCU_T::SVIOIEN: PDMA1IEN Position      */
+#define SCU_SVIOIEN_PDMA1IEN_Msk         (0x1ul << SCU_SVIOIEN_PDMA1IEN_Pos)               /*!< SCU_T::SVIOIEN: PDMA1IEN Mask          */
+
+#define SCU_SVIOIEN_SRAM0IEN_Pos         (12)                                              /*!< SCU_T::SVIOIEN: SRAM0IEN Position      */
+#define SCU_SVIOIEN_SRAM0IEN_Msk         (0x1ul << SCU_SVIOIEN_SRAM0IEN_Pos)               /*!< SCU_T::SVIOIEN: SRAM0IEN Mask          */
+
+#define SCU_SVIOIEN_SRAM1IEN_Pos         (13)                                              /*!< SCU_T::SVIOIEN: SRAM1IEN Position      */
+#define SCU_SVIOIEN_SRAM1IEN_Msk         (0x1ul << SCU_SVIOIEN_SRAM1IEN_Pos)               /*!< SCU_T::SVIOIEN: SRAM1IEN Mask          */
+
+#define SCU_SVIOIEN_FMCIEN_Pos           (14)                                              /*!< SCU_T::SVIOIEN: FMCIEN Position        */
+#define SCU_SVIOIEN_FMCIEN_Msk           (0x1ul << SCU_SVIOIEN_FMCIEN_Pos)                 /*!< SCU_T::SVIOIEN: FMCIEN Mask            */
+
+#define SCU_SVIOIEN_FLASHIEN_Pos         (15)                                              /*!< SCU_T::SVIOIEN: FLASHIEN Position      */
+#define SCU_SVIOIEN_FLASHIEN_Msk         (0x1ul << SCU_SVIOIEN_FLASHIEN_Pos)               /*!< SCU_T::SVIOIEN: FLASHIEN Mask          */
+
+#define SCU_SVIOIEN_SCUIEN_Pos           (16)                                              /*!< SCU_T::SVIOIEN: SCUIEN Position        */
+#define SCU_SVIOIEN_SCUIEN_Msk           (0x1ul << SCU_SVIOIEN_SCUIEN_Pos)                 /*!< SCU_T::SVIOIEN: SCUIEN Mask            */
+
+#define SCU_SVIOIEN_SYSIEN_Pos           (17)                                              /*!< SCU_T::SVIOIEN: SYSIEN Position        */
+#define SCU_SVIOIEN_SYSIEN_Msk           (0x1ul << SCU_SVIOIEN_SYSIEN_Pos)                 /*!< SCU_T::SVIOIEN: SYSIEN Mask            */
+
+#define SCU_SVIOIEN_CRPTIEN_Pos          (18)                                              /*!< SCU_T::SVIOIEN: CRPTIEN Position       */
+#define SCU_SVIOIEN_CRPTIEN_Msk          (0x1ul << SCU_SVIOIEN_CRPTIEN_Pos)                /*!< SCU_T::SVIOIEN: CRPTIEN Mask           */
+
+#define SCU_SVIOIEN_KSIEN_Pos            (19)                                              /*!< SCU_T::SVIOIEN: KSIEN Position         */
+#define SCU_SVIOIEN_KSIEN_Msk            (0x1ul << SCU_SVIOIEN_KSIEN_Pos)                  /*!< SCU_T::SVIOIEN: KSIEN Mask             */
+
+#define SCU_SVINTSTS_APB0IF_Pos          (0)                                               /*!< SCU_T::SVINTSTS: APB0IF Position       */
+#define SCU_SVINTSTS_APB0IF_Msk          (0x1ul << SCU_SVINTSTS_APB0IF_Pos)                /*!< SCU_T::SVINTSTS: APB0IF Mask           */
+
+#define SCU_SVINTSTS_APB1IF_Pos          (1)                                               /*!< SCU_T::SVINTSTS: APB1IF Position       */
+#define SCU_SVINTSTS_APB1IF_Msk          (0x1ul << SCU_SVINTSTS_APB1IF_Pos)                /*!< SCU_T::SVINTSTS: APB1IF Mask           */
+
+#define SCU_SVINTSTS_GPIOIF_Pos          (4)                                               /*!< SCU_T::SVINTSTS: GPIOIF Position       */
+#define SCU_SVINTSTS_GPIOIF_Msk          (0x1ul << SCU_SVINTSTS_GPIOIF_Pos)                /*!< SCU_T::SVINTSTS: GPIOIF Mask           */
+
+#define SCU_SVINTSTS_EBIIF_Pos           (5)                                               /*!< SCU_T::SVINTSTS: EBIIF Position        */
+#define SCU_SVINTSTS_EBIIF_Msk           (0x1ul << SCU_SVINTSTS_EBIIF_Pos)                 /*!< SCU_T::SVINTSTS: EBIIF Mask            */
+
+#define SCU_SVINTSTS_USBHIF_Pos          (6)                                               /*!< SCU_T::SVINTSTS: USBHIF Position       */
+#define SCU_SVINTSTS_USBHIF_Msk          (0x1ul << SCU_SVINTSTS_USBHIF_Pos)                /*!< SCU_T::SVINTSTS: USBHIF Mask           */
+
+#define SCU_SVINTSTS_CRCIF_Pos           (7)                                               /*!< SCU_T::SVINTSTS: CRCIF Position        */
+#define SCU_SVINTSTS_CRCIF_Msk           (0x1ul << SCU_SVINTSTS_CRCIF_Pos)                 /*!< SCU_T::SVINTSTS: CRCIF Mask            */
+
+#define SCU_SVINTSTS_SDH0IF_Pos          (8)                                               /*!< SCU_T::SVINTSTS: SDH0IF Position       */
+#define SCU_SVINTSTS_SDH0IF_Msk          (0x1ul << SCU_SVINTSTS_SDH0IF_Pos)                /*!< SCU_T::SVINTSTS: SDH0IF Mask           */
+
+#define SCU_SVINTSTS_PDMA0IF_Pos         (10)                                              /*!< SCU_T::SVINTSTS: PDMA0IF Position      */
+#define SCU_SVINTSTS_PDMA0IF_Msk         (0x1ul << SCU_SVINTSTS_PDMA0IF_Pos)               /*!< SCU_T::SVINTSTS: PDMA0IF Mask          */
+
+#define SCU_SVINTSTS_PDMA1IF_Pos         (11)                                              /*!< SCU_T::SVINTSTS: PDMA1IF Position      */
+#define SCU_SVINTSTS_PDMA1IF_Msk         (0x1ul << SCU_SVINTSTS_PDMA1IF_Pos)               /*!< SCU_T::SVINTSTS: PDMA1IF Mask          */
+
+#define SCU_SVINTSTS_SRAM0IF_Pos         (12)                                              /*!< SCU_T::SVINTSTS: SRAM0IF Position      */
+#define SCU_SVINTSTS_SRAM0IF_Msk         (0x1ul << SCU_SVINTSTS_SRAM0IF_Pos)               /*!< SCU_T::SVINTSTS: SRAM0IF Mask          */
+
+#define SCU_SVINTSTS_SRAM1IF_Pos         (13)                                              /*!< SCU_T::SVINTSTS: SRAM1IF Position      */
+#define SCU_SVINTSTS_SRAM1IF_Msk         (0x1ul << SCU_SVINTSTS_SRAM1IF_Pos)               /*!< SCU_T::SVINTSTS: SRAM1IF Mask          */
+
+#define SCU_SVINTSTS_FMCIF_Pos           (14)                                              /*!< SCU_T::SVINTSTS: FMCIF Position        */
+#define SCU_SVINTSTS_FMCIF_Msk           (0x1ul << SCU_SVINTSTS_FMCIF_Pos)                 /*!< SCU_T::SVINTSTS: FMCIF Mask            */
+
+#define SCU_SVINTSTS_FLASHIF_Pos         (15)                                              /*!< SCU_T::SVINTSTS: FLASHIF Position      */
+#define SCU_SVINTSTS_FLASHIF_Msk         (0x1ul << SCU_SVINTSTS_FLASHIF_Pos)               /*!< SCU_T::SVINTSTS: FLASHIF Mask          */
+
+#define SCU_SVINTSTS_SCUIF_Pos           (16)                                              /*!< SCU_T::SVINTSTS: SCUIF Position        */
+#define SCU_SVINTSTS_SCUIF_Msk           (0x1ul << SCU_SVINTSTS_SCUIF_Pos)                 /*!< SCU_T::SVINTSTS: SCUIF Mask            */
+
+#define SCU_SVINTSTS_SYSIF_Pos           (17)                                              /*!< SCU_T::SVINTSTS: SYSIF Position        */
+#define SCU_SVINTSTS_SYSIF_Msk           (0x1ul << SCU_SVINTSTS_SYSIF_Pos)                 /*!< SCU_T::SVINTSTS: SYSIF Mask            */
+
+#define SCU_SVINTSTS_CRPTIF_Pos          (18)                                              /*!< SCU_T::SVINTSTS: CRPTIF Position       */
+#define SCU_SVINTSTS_CRPTIF_Msk          (0x1ul << SCU_SVINTSTS_CRPTIF_Pos)                /*!< SCU_T::SVINTSTS: CRPTIF Mask           */
+
+#define SCU_SVINTSTS_KSIF_Pos            (19)                                              /*!< SCU_T::SVINTSTS: KSIF Position         */
+#define SCU_SVINTSTS_KSIF_Msk            (0x1ul << SCU_SVINTSTS_KSIF_Pos)                  /*!< SCU_T::SVINTSTS: KSIF Mask             */
+
+#define SCU_APB0VSRC_MASTER_Pos          (0)                                               /*!< SCU_T::APB0VSRC: MASTER Position       */
+#define SCU_APB0VSRC_MASTER_Msk          (0xful << SCU_APB0VSRC_MASTER_Pos)                /*!< SCU_T::APB0VSRC: MASTER Mask           */
+
+#define SCU_APB0VA_VIOADDR_Pos           (0)                                               /*!< SCU_T::APB0VA: VIOADDR Position        */
+#define SCU_APB0VA_VIOADDR_Msk           (0xfffffffful << SCU_APB0VA_VIOADDR_Pos)          /*!< SCU_T::APB0VA: VIOADDR Mask            */
+
+#define SCU_APB1VSRC_MASTER_Pos          (0)                                               /*!< SCU_T::APB1VSRC: MASTER Position       */
+#define SCU_APB1VSRC_MASTER_Msk          (0xful << SCU_APB1VSRC_MASTER_Pos)                /*!< SCU_T::APB1VSRC: MASTER Mask           */
+
+#define SCU_APB1VA_VIOADDR_Pos           (0)                                               /*!< SCU_T::APB1VA: VIOADDR Position        */
+#define SCU_APB1VA_VIOADDR_Msk           (0xfffffffful << SCU_APB1VA_VIOADDR_Pos)          /*!< SCU_T::APB1VA: VIOADDR Mask            */
+
+#define SCU_GPIOVSRC_MASTER_Pos          (0)                                               /*!< SCU_T::GPIOVSRC: MASTER Position       */
+#define SCU_GPIOVSRC_MASTER_Msk          (0xful << SCU_GPIOVSRC_MASTER_Pos)                /*!< SCU_T::GPIOVSRC: MASTER Mask           */
+
+#define SCU_GPIOVA_VIOADDR_Pos           (0)                                               /*!< SCU_T::GPIOVA: VIOADDR Position        */
+#define SCU_GPIOVA_VIOADDR_Msk           (0xfffffffful << SCU_GPIOVA_VIOADDR_Pos)          /*!< SCU_T::GPIOVA: VIOADDR Mask            */
+
+#define SCU_EBIVSRC_MASTER_Pos           (0)                                               /*!< SCU_T::EBIVSRC: MASTER Position        */
+#define SCU_EBIVSRC_MASTER_Msk           (0xful << SCU_EBIVSRC_MASTER_Pos)                 /*!< SCU_T::EBIVSRC: MASTER Mask            */
+
+#define SCU_EBIVA_VIOADDR_Pos            (0)                                               /*!< SCU_T::EBIVA: VIOADDR Position         */
+#define SCU_EBIVA_VIOADDR_Msk            (0xfffffffful << SCU_EBIVA_VIOADDR_Pos)           /*!< SCU_T::EBIVA: VIOADDR Mask             */
+
+#define SCU_USBHVSRC_MASTER_Pos          (0)                                               /*!< SCU_T::USBHVSRC: MASTER Position       */
+#define SCU_USBHVSRC_MASTER_Msk          (0xful << SCU_USBHVSRC_MASTER_Pos)                /*!< SCU_T::USBHVSRC: MASTER Mask           */
+
+#define SCU_USBHVA_VIOADDR_Pos           (0)                                               /*!< SCU_T::USBHVA: VIOADDR Position        */
+#define SCU_USBHVA_VIOADDR_Msk           (0xfffffffful << SCU_USBHVA_VIOADDR_Pos)          /*!< SCU_T::USBHVA: VIOADDR Mask            */
+
+#define SCU_CRCVSRC_MASTER_Pos           (0)                                               /*!< SCU_T::CRCVSRC: MASTER Position        */
+#define SCU_CRCVSRC_MASTER_Msk           (0xful << SCU_CRCVSRC_MASTER_Pos)                 /*!< SCU_T::CRCVSRC: MASTER Mask            */
+
+#define SCU_CRCVA_VIOADDR_Pos            (0)                                               /*!< SCU_T::CRCVA: VIOADDR Position         */
+#define SCU_CRCVA_VIOADDR_Msk            (0xfffffffful << SCU_CRCVA_VIOADDR_Pos)           /*!< SCU_T::CRCVA: VIOADDR Mask             */
+
+#define SCU_SD0VSRC_MASTER_Pos           (0)                                               /*!< SCU_T::SD0VSRC: MASTER Position        */
+#define SCU_SD0VSRC_MASTER_Msk           (0xful << SCU_SD0VSRC_MASTER_Pos)                 /*!< SCU_T::SD0VSRC: MASTER Mask            */
+
+#define SCU_SD0VA_VIOADDR_Pos            (0)                                               /*!< SCU_T::SD0VA: VIOADDR Position         */
+#define SCU_SD0VA_VIOADDR_Msk            (0xfffffffful << SCU_SD0VA_VIOADDR_Pos)           /*!< SCU_T::SD0VA: VIOADDR Mask             */
+
+#define SCU_PDMA0VSRC_MASTER_Pos         (0)                                               /*!< SCU_T::PDMA0VSRC: MASTER Position      */
+#define SCU_PDMA0VSRC_MASTER_Msk         (0xful << SCU_PDMA0VSRC_MASTER_Pos)               /*!< SCU_T::PDMA0VSRC: MASTER Mask          */
+
+#define SCU_PDMA0VA_VIOADDR_Pos          (0)                                               /*!< SCU_T::PDMA0VA: VIOADDR Position       */
+#define SCU_PDMA0VA_VIOADDR_Msk          (0xfffffffful << SCU_PDMA0VA_VIOADDR_Pos)         /*!< SCU_T::PDMA0VA: VIOADDR Mask           */
+
+#define SCU_PDMA1VSRC_MASTER_Pos         (0)                                               /*!< SCU_T::PDMA1VSRC: MASTER Position      */
+#define SCU_PDMA1VSRC_MASTER_Msk         (0xful << SCU_PDMA1VSRC_MASTER_Pos)               /*!< SCU_T::PDMA1VSRC: MASTER Mask          */
+
+#define SCU_PDMA1VA_VIOADDR_Pos          (0)                                               /*!< SCU_T::PDMA1VA: VIOADDR Position       */
+#define SCU_PDMA1VA_VIOADDR_Msk          (0xfffffffful << SCU_PDMA1VA_VIOADDR_Pos)         /*!< SCU_T::PDMA1VA: VIOADDR Mask           */
+
+#define SCU_SRAM0VSRC_MASTER_Pos         (0)                                               /*!< SCU_T::SRAM0VSRC: MASTER Position      */
+#define SCU_SRAM0VSRC_MASTER_Msk         (0xful << SCU_SRAM0VSRC_MASTER_Pos)               /*!< SCU_T::SRAM0VSRC: MASTER Mask          */
+
+#define SCU_SRAM0VA_VIOADDR_Pos          (0)                                               /*!< SCU_T::SRAM0VA: VIOADDR Position       */
+#define SCU_SRAM0VA_VIOADDR_Msk          (0xfffffffful << SCU_SRAM0VA_VIOADDR_Pos)         /*!< SCU_T::SRAM0VA: VIOADDR Mask           */
+
+#define SCU_SRAM1VSRC_MASTER_Pos         (0)                                               /*!< SCU_T::SRAM1VSRC: MASTER Position      */
+#define SCU_SRAM1VSRC_MASTER_Msk         (0xful << SCU_SRAM1VSRC_MASTER_Pos)               /*!< SCU_T::SRAM1VSRC: MASTER Mask          */
+
+#define SCU_SRAM1VA_VIOADDR_Pos          (0)                                               /*!< SCU_T::SRAM1VA: VIOADDR Position       */
+#define SCU_SRAM1VA_VIOADDR_Msk          (0xfffffffful << SCU_SRAM1VA_VIOADDR_Pos)         /*!< SCU_T::SRAM1VA: VIOADDR Mask           */
+
+#define SCU_FMCVSRC_MASTER_Pos           (0)                                               /*!< SCU_T::FMCVSRC: MASTER Position        */
+#define SCU_FMCVSRC_MASTER_Msk           (0xful << SCU_FMCVSRC_MASTER_Pos)                 /*!< SCU_T::FMCVSRC: MASTER Mask            */
+
+#define SCU_FMCVA_VIOADDR_Pos            (0)                                               /*!< SCU_T::FMCVA: VIOADDR Position         */
+#define SCU_FMCVA_VIOADDR_Msk            (0xfffffffful << SCU_FMCVA_VIOADDR_Pos)           /*!< SCU_T::FMCVA: VIOADDR Mask             */
+
+#define SCU_FLASHVSRC_MASTER_Pos         (0)                                               /*!< SCU_T::FLASHVSRC: MASTER Position      */
+#define SCU_FLASHVSRC_MASTER_Msk         (0xful << SCU_FLASHVSRC_MASTER_Pos)               /*!< SCU_T::FLASHVSRC: MASTER Mask          */
+
+#define SCU_FLASHVA_VIOADDR_Pos          (0)                                               /*!< SCU_T::FLASHVA: VIOADDR Position       */
+#define SCU_FLASHVA_VIOADDR_Msk          (0xfffffffful << SCU_FLASHVA_VIOADDR_Pos)         /*!< SCU_T::FLASHVA: VIOADDR Mask           */
+
+#define SCU_SCUVSRC_MASTER_Pos           (0)                                               /*!< SCU_T::SCUVSRC: MASTER Position        */
+#define SCU_SCUVSRC_MASTER_Msk           (0xful << SCU_SCUVSRC_MASTER_Pos)                 /*!< SCU_T::SCUVSRC: MASTER Mask            */
+
+#define SCU_SCUVA_VIOADDR_Pos            (0)                                               /*!< SCU_T::SCUVA: VIOADDR Position         */
+#define SCU_SCUVA_VIOADDR_Msk            (0xfffffffful << SCU_SCUVA_VIOADDR_Pos)           /*!< SCU_T::SCUVA: VIOADDR Mask             */
+
+#define SCU_SYSVSRC_MASTER_Pos           (0)                                               /*!< SCU_T::SYSVSRC: MASTER Position        */
+#define SCU_SYSVSRC_MASTER_Msk           (0xful << SCU_SYSVSRC_MASTER_Pos)                 /*!< SCU_T::SYSVSRC: MASTER Mask            */
+
+#define SCU_SYSVA_VIOADDR_Pos            (0)                                               /*!< SCU_T::SYSVA: VIOADDR Position         */
+#define SCU_SYSVA_VIOADDR_Msk            (0xfffffffful << SCU_SYSVA_VIOADDR_Pos)           /*!< SCU_T::SYSVA: VIOADDR Mask             */
+
+#define SCU_CRPTVSRC_MASTER_Pos          (0)                                               /*!< SCU_T::CRPTVSRC: MASTER Position       */
+#define SCU_CRPTVSRC_MASTER_Msk          (0xful << SCU_CRPTVSRC_MASTER_Pos)                /*!< SCU_T::CRPTVSRC: MASTER Mask           */
+
+#define SCU_CRPTVA_VIOADDR_Pos           (0)                                               /*!< SCU_T::CRPTVA: VIOADDR Position        */
+#define SCU_CRPTVA_VIOADDR_Msk           (0xfffffffful << SCU_CRPTVA_VIOADDR_Pos)          /*!< SCU_T::CRPTVA: VIOADDR Mask            */
+
+#define SCU_KSVSRC_MASTER_Pos            (0)                                               /*!< SCU_T::KSVSRC: MASTER Position         */
+#define SCU_KSVSRC_MASTER_Msk            (0xful << SCU_KSVSRC_MASTER_Pos)                  /*!< SCU_T::KSVSRC: MASTER Mask             */
+
+#define SCU_KSVA_VIOADDR_Pos             (0)                                               /*!< SCU_T::KSVA: VIOADDR Position          */
+#define SCU_KSVA_VIOADDR_Msk             (0xfffffffful << SCU_KSVA_VIOADDR_Pos)            /*!< SCU_T::KSVA: VIOADDR Mask              */
+
+#define SCU_SRAM2VSRC_MASTER_Pos         (0)                                               /*!< SCU_T::SRAM2VSRC: MASTER Position      */
+#define SCU_SRAM2VSRC_MASTER_Msk         (0xful << SCU_SRAM2VSRC_MASTER_Pos)               /*!< SCU_T::SRAM2VSRC: MASTER Mask          */
+
+#define SCU_SRAM2VA_VIOADDR_Pos          (0)                                               /*!< SCU_T::SRAM2VA: VIOADDR Position       */
+#define SCU_SRAM2VA_VIOADDR_Msk          (0xfffffffful << SCU_SRAM2VA_VIOADDR_Pos)         /*!< SCU_T::SRAM2VA: VIOADDR Mask           */
+
+#define SCU_SINFAEN_SCUSIAEN_Pos         (0)                                               /*!< SCU_T::SINFAEN: SCUSIAEN Position      */
+#define SCU_SINFAEN_SCUSIAEN_Msk         (0x1ul << SCU_SINFAEN_SCUSIAEN_Pos)               /*!< SCU_T::SINFAEN: SCUSIAEN Mask          */
+
+#define SCU_SINFAEN_SYSSIAEN_Pos         (1)                                               /*!< SCU_T::SINFAEN: SYSSIAEN Position      */
+#define SCU_SINFAEN_SYSSIAEN_Msk         (0x1ul << SCU_SINFAEN_SYSSIAEN_Pos)               /*!< SCU_T::SINFAEN: SYSSIAEN Mask          */
+
+#define SCU_SINFAEN_FMCSIAEN_Pos         (2)                                               /*!< SCU_T::SINFAEN: FMCSIAEN Position      */
+#define SCU_SINFAEN_FMCSIAEN_Msk         (0x1ul << SCU_SINFAEN_FMCSIAEN_Pos)               /*!< SCU_T::SINFAEN: FMCSIAEN Mask          */
+
+#define SCU_PNPSET0_SYS_Pos              (0)                                               /*!< SCU_T::PNPSET0: SYS Position           */
+#define SCU_PNPSET0_SYS_Msk              (0x1ul << SCU_PNPSET0_SYS_Pos)                    /*!< SCU_T::PNPSET0: SYS Mask               */
+
+#define SCU_PNPSET0_PDMA0_Pos            (8)                                               /*!< SCU_T::PNPSET0: PDMA0 Position         */
+#define SCU_PNPSET0_PDMA0_Msk            (0x1ul << SCU_PNPSET0_PDMA0_Pos)                  /*!< SCU_T::PNPSET0: PDMA0 Mask             */
+
+#define SCU_PNPSET0_USBH_Pos             (9)                                               /*!< SCU_T::PNPSET0: USBH Position          */
+#define SCU_PNPSET0_USBH_Msk             (0x1ul << SCU_PNPSET0_USBH_Pos)                   /*!< SCU_T::PNPSET0: USBH Mask              */
+
+#define SCU_PNPSET0_FMC_Pos              (12)                                              /*!< SCU_T::PNPSET0: FMC Position           */
+#define SCU_PNPSET0_FMC_Msk              (0x1ul << SCU_PNPSET0_FMC_Pos)                    /*!< SCU_T::PNPSET0: FMC Mask               */
+
+#define SCU_PNPSET0_SDH0_Pos             (13)                                              /*!< SCU_T::PNPSET0: SDH0 Position          */
+#define SCU_PNPSET0_SDH0_Msk             (0x1ul << SCU_PNPSET0_SDH0_Pos)                   /*!< SCU_T::PNPSET0: SDH0 Mask              */
+
+#define SCU_PNPSET0_EBI_Pos              (16)                                              /*!< SCU_T::PNPSET0: EBI Position           */
+#define SCU_PNPSET0_EBI_Msk              (0x1ul << SCU_PNPSET0_EBI_Pos)                    /*!< SCU_T::PNPSET0: EBI Mask               */
+
+#define SCU_PNPSET0_PDMA1_Pos            (24)                                              /*!< SCU_T::PNPSET0: PDMA1 Position         */
+#define SCU_PNPSET0_PDMA1_Msk            (0x1ul << SCU_PNPSET0_PDMA1_Pos)                  /*!< SCU_T::PNPSET0: PDMA1 Mask             */
+
+#define SCU_PNPSET1_SCU_Pos              (15)                                              /*!< SCU_T::PNPSET1: SCU Position           */
+#define SCU_PNPSET1_SCU_Msk              (0x1ul << SCU_PNPSET1_SCU_Pos)                    /*!< SCU_T::PNPSET1: SCU Mask               */
+
+#define SCU_PNPSET1_CRC_Pos              (17)                                              /*!< SCU_T::PNPSET1: CRC Position           */
+#define SCU_PNPSET1_CRC_Msk              (0x1ul << SCU_PNPSET1_CRC_Pos)                    /*!< SCU_T::PNPSET1: CRC Mask               */
+
+#define SCU_PNPSET1_CRPT_Pos             (18)                                              /*!< SCU_T::PNPSET1: CRPT Position          */
+#define SCU_PNPSET1_CRPT_Msk             (0x1ul << SCU_PNPSET1_CRPT_Pos)                   /*!< SCU_T::PNPSET1: CRPT Mask              */
+
+#define SCU_PNPSET1_KS_Pos               (21)                                              /*!< SCU_T::PNPSET1: KS Position            */
+#define SCU_PNPSET1_KS_Msk               (0x1ul << SCU_PNPSET1_KS_Pos)                     /*!< SCU_T::PNPSET1: KS Mask                */
+
+#define SCU_PNPSET2_WDT_Pos              (0)                                               /*!< SCU_T::PNPSET2: WDT Position           */
+#define SCU_PNPSET2_WDT_Msk              (0x1ul << SCU_PNPSET2_WDT_Pos)                    /*!< SCU_T::PNPSET2: WDT Mask               */
+
+#define SCU_PNPSET2_RTC_Pos              (1)                                               /*!< SCU_T::PNPSET2: RTC Position           */
+#define SCU_PNPSET2_RTC_Msk              (0x1ul << SCU_PNPSET2_RTC_Pos)                    /*!< SCU_T::PNPSET2: RTC Mask               */
+
+#define SCU_PNPSET2_EWDT_Pos             (2)                                               /*!< SCU_T::PNPSET2: EWDT Position          */
+#define SCU_PNPSET2_EWDT_Msk             (0x1ul << SCU_PNPSET2_EWDT_Pos)                   /*!< SCU_T::PNPSET2: EWDT Mask              */
+
+#define SCU_PNPSET2_EADC_Pos             (3)                                               /*!< SCU_T::PNPSET2: EADC Position          */
+#define SCU_PNPSET2_EADC_Msk             (0x1ul << SCU_PNPSET2_EADC_Pos)                   /*!< SCU_T::PNPSET2: EADC Mask              */
+
+#define SCU_PNPSET2_ACMP01_Pos           (5)                                               /*!< SCU_T::PNPSET2: ACMP01 Position        */
+#define SCU_PNPSET2_ACMP01_Msk           (0x1ul << SCU_PNPSET2_ACMP01_Pos)                 /*!< SCU_T::PNPSET2: ACMP01 Mask            */
+
+#define SCU_PNPSET2_DAC_Pos              (7)                                               /*!< SCU_T::PNPSET2: DAC Position           */
+#define SCU_PNPSET2_DAC_Msk              (0x1ul << SCU_PNPSET2_DAC_Pos)                    /*!< SCU_T::PNPSET2: DAC Mask               */
+
+#define SCU_PNPSET2_I2S0_Pos             (8)                                               /*!< SCU_T::PNPSET2: I2S0 Position          */
+#define SCU_PNPSET2_I2S0_Msk             (0x1ul << SCU_PNPSET2_I2S0_Pos)                   /*!< SCU_T::PNPSET2: I2S0 Mask              */
+
+#define SCU_PNPSET2_OTG_Pos              (13)                                              /*!< SCU_T::PNPSET2: OTG Position           */
+#define SCU_PNPSET2_OTG_Msk              (0x1ul << SCU_PNPSET2_OTG_Pos)                    /*!< SCU_T::PNPSET2: OTG Mask               */
+
+#define SCU_PNPSET2_TMR01_Pos            (14)                                              /*!< SCU_T::PNPSET2: TMR01 Position         */
+#define SCU_PNPSET2_TMR01_Msk            (0x7ul << SCU_PNPSET2_TMR01_Pos)                  /*!< SCU_T::PNPSET2: TMR01 Mask             */
+
+#define SCU_PNPSET2_TMR23_Pos            (17)                                              /*!< SCU_T::PNPSET2: TMR23 Position         */
+#define SCU_PNPSET2_TMR23_Msk            (0x1ul << SCU_PNPSET2_TMR23_Pos)                  /*!< SCU_T::PNPSET2: TMR23 Mask             */
+
+#define SCU_PNPSET2_EPWM0_Pos            (24)                                              /*!< SCU_T::PNPSET2: EPWM0 Position         */
+#define SCU_PNPSET2_EPWM0_Msk            (0x1ul << SCU_PNPSET2_EPWM0_Pos)                  /*!< SCU_T::PNPSET2: EPWM0 Mask             */
+
+#define SCU_PNPSET2_EPWM1_Pos            (25)                                              /*!< SCU_T::PNPSET2: EPWM1 Position         */
+#define SCU_PNPSET2_EPWM1_Msk            (0x1ul << SCU_PNPSET2_EPWM1_Pos)                  /*!< SCU_T::PNPSET2: EPWM1 Mask             */
+
+#define SCU_PNPSET2_BPWM0_Pos            (26)                                              /*!< SCU_T::PNPSET2: BPWM0 Position         */
+#define SCU_PNPSET2_BPWM0_Msk            (0x1ul << SCU_PNPSET2_BPWM0_Pos)                  /*!< SCU_T::PNPSET2: BPWM0 Mask             */
+
+#define SCU_PNPSET2_BPWM1_Pos            (27)                                              /*!< SCU_T::PNPSET2: BPWM1 Position         */
+#define SCU_PNPSET2_BPWM1_Msk            (0x1ul << SCU_PNPSET2_BPWM1_Pos)                  /*!< SCU_T::PNPSET2: BPWM1 Mask             */
+
+#define SCU_PNPSET3_QSPI0_Pos            (0)                                               /*!< SCU_T::PNPSET3: QSPI0 Position         */
+#define SCU_PNPSET3_QSPI0_Msk            (0x1ul << SCU_PNPSET3_QSPI0_Pos)                  /*!< SCU_T::PNPSET3: QSPI0 Mask             */
+
+#define SCU_PNPSET3_SPI0_Pos             (1)                                               /*!< SCU_T::PNPSET3: SPI0 Position          */
+#define SCU_PNPSET3_SPI0_Msk             (0x1ul << SCU_PNPSET3_SPI0_Pos)                   /*!< SCU_T::PNPSET3: SPI0 Mask              */
+
+#define SCU_PNPSET3_SPI1_Pos             (2)                                               /*!< SCU_T::PNPSET3: SPI1 Position          */
+#define SCU_PNPSET3_SPI1_Msk             (0x1ul << SCU_PNPSET3_SPI1_Pos)                   /*!< SCU_T::PNPSET3: SPI1 Mask              */
+
+#define SCU_PNPSET3_SPI2_Pos             (3)                                               /*!< SCU_T::PNPSET3: SPI2 Position          */
+#define SCU_PNPSET3_SPI2_Msk             (0x1ul << SCU_PNPSET3_SPI2_Pos)                   /*!< SCU_T::PNPSET3: SPI2 Mask              */
+
+#define SCU_PNPSET3_SPI3_Pos             (4)                                               /*!< SCU_T::PNPSET3: SPI3 Position          */
+#define SCU_PNPSET3_SPI3_Msk             (0x1ul << SCU_PNPSET3_SPI3_Pos)                   /*!< SCU_T::PNPSET3: SPI3 Mask              */
+
+#define SCU_PNPSET3_UART0_Pos            (16)                                              /*!< SCU_T::PNPSET3: UART0 Position         */
+#define SCU_PNPSET3_UART0_Msk            (0x1ul << SCU_PNPSET3_UART0_Pos)                  /*!< SCU_T::PNPSET3: UART0 Mask             */
+
+#define SCU_PNPSET3_UART1_Pos            (17)                                              /*!< SCU_T::PNPSET3: UART1 Position         */
+#define SCU_PNPSET3_UART1_Msk            (0x1ul << SCU_PNPSET3_UART1_Pos)                  /*!< SCU_T::PNPSET3: UART1 Mask             */
+
+#define SCU_PNPSET3_UART2_Pos            (18)                                              /*!< SCU_T::PNPSET3: UART2 Position         */
+#define SCU_PNPSET3_UART2_Msk            (0x1ul << SCU_PNPSET3_UART2_Pos)                  /*!< SCU_T::PNPSET3: UART2 Mask             */
+
+#define SCU_PNPSET3_UART3_Pos            (19)                                              /*!< SCU_T::PNPSET3: UART3 Position         */
+#define SCU_PNPSET3_UART3_Msk            (0x1ul << SCU_PNPSET3_UART3_Pos)                  /*!< SCU_T::PNPSET3: UART3 Mask             */
+
+#define SCU_PNPSET3_UART4_Pos            (20)                                              /*!< SCU_T::PNPSET3: UART4 Position         */
+#define SCU_PNPSET3_UART4_Msk            (0x1ul << SCU_PNPSET3_UART4_Pos)                  /*!< SCU_T::PNPSET3: UART4 Mask             */
+
+#define SCU_PNPSET3_UART5_Pos            (21)                                              /*!< SCU_T::PNPSET3: UART5 Position         */
+#define SCU_PNPSET3_UART5_Msk            (0x1ul << SCU_PNPSET3_UART5_Pos)                  /*!< SCU_T::PNPSET3: UART5 Mask             */
+
+#define SCU_PNPSET4_I2C0_Pos             (0)                                               /*!< SCU_T::PNPSET4: I2C0 Position          */
+#define SCU_PNPSET4_I2C0_Msk             (0x1ul << SCU_PNPSET4_I2C0_Pos)                   /*!< SCU_T::PNPSET4: I2C0 Mask              */
+
+#define SCU_PNPSET4_I2C1_Pos             (1)                                               /*!< SCU_T::PNPSET4: I2C1 Position          */
+#define SCU_PNPSET4_I2C1_Msk             (0x1ul << SCU_PNPSET4_I2C1_Pos)                   /*!< SCU_T::PNPSET4: I2C1 Mask              */
+
+#define SCU_PNPSET4_I2C2_Pos             (2)                                               /*!< SCU_T::PNPSET4: I2C2 Position          */
+#define SCU_PNPSET4_I2C2_Msk             (0x1ul << SCU_PNPSET4_I2C2_Pos)                   /*!< SCU_T::PNPSET4: I2C2 Mask              */
+
+#define SCU_PNPSET4_SC0_Pos              (16)                                              /*!< SCU_T::PNPSET4: SC0 Position           */
+#define SCU_PNPSET4_SC0_Msk              (0x1ul << SCU_PNPSET4_SC0_Pos)                    /*!< SCU_T::PNPSET4: SC0 Mask               */
+
+#define SCU_PNPSET4_SC1_Pos              (17)                                              /*!< SCU_T::PNPSET4: SC1 Position           */
+#define SCU_PNPSET4_SC1_Msk              (0x1ul << SCU_PNPSET4_SC1_Pos)                    /*!< SCU_T::PNPSET4: SC1 Mask               */
+
+#define SCU_PNPSET4_SC2_Pos              (18)                                              /*!< SCU_T::PNPSET4: SC2 Position           */
+#define SCU_PNPSET4_SC2_Msk              (0x1ul << SCU_PNPSET4_SC2_Pos)                    /*!< SCU_T::PNPSET4: SC2 Mask               */
+
+#define SCU_PNPSET5_CAN0_Pos             (0)                                               /*!< SCU_T::PNPSET5: CAN0 Position          */
+#define SCU_PNPSET5_CAN0_Msk             (0x1ul << SCU_PNPSET5_CAN0_Pos)                   /*!< SCU_T::PNPSET5: CAN0 Mask              */
+
+#define SCU_PNPSET5_QEI0_Pos             (16)                                              /*!< SCU_T::PNPSET5: QEI0 Position          */
+#define SCU_PNPSET5_QEI0_Msk             (0x1ul << SCU_PNPSET5_QEI0_Pos)                   /*!< SCU_T::PNPSET5: QEI0 Mask              */
+
+#define SCU_PNPSET5_QEI1_Pos             (17)                                              /*!< SCU_T::PNPSET5: QEI1 Position          */
+#define SCU_PNPSET5_QEI1_Msk             (0x1ul << SCU_PNPSET5_QEI1_Pos)                   /*!< SCU_T::PNPSET5: QEI1 Mask              */
+
+#define SCU_PNPSET5_ECAP0_Pos            (20)                                              /*!< SCU_T::PNPSET5: ECAP0 Position         */
+#define SCU_PNPSET5_ECAP0_Msk            (0x1ul << SCU_PNPSET5_ECAP0_Pos)                  /*!< SCU_T::PNPSET5: ECAP0 Mask             */
+
+#define SCU_PNPSET5_ECAP1_Pos            (21)                                              /*!< SCU_T::PNPSET5: ECAP1 Position         */
+#define SCU_PNPSET5_ECAP1_Msk            (0x1ul << SCU_PNPSET5_ECAP1_Pos)                  /*!< SCU_T::PNPSET5: ECAP1 Mask             */
+
+#define SCU_PNPSET5_TRNG_Pos             (25)                                              /*!< SCU_T::PNPSET5: TRNG Position          */
+#define SCU_PNPSET5_TRNG_Msk             (0x1ul << SCU_PNPSET5_TRNG_Pos)                   /*!< SCU_T::PNPSET5: TRNG Mask              */
+
+#define SCU_PNPSET5_LCD_Pos              (27)                                              /*!< SCU_T::PNPSET5: LCD Position           */
+#define SCU_PNPSET5_LCD_Msk              (0x1ul << SCU_PNPSET5_LCD_Pos)                    /*!< SCU_T::PNPSET5: LCD Mask               */
+
+#define SCU_PNPSET5_TAMPER_Pos           (29)                                              /*!< SCU_T::PNPSET5: TAMPER Position        */
+#define SCU_PNPSET5_TAMPER_Msk           (0x1ul << SCU_PNPSET5_TAMPER_Pos)                 /*!< SCU_T::PNPSET5: TAMPER Mask            */
+
+#define SCU_PNPSET6_USBD_Pos             (0)                                               /*!< SCU_T::PNPSET6: USBD Position          */
+#define SCU_PNPSET6_USBD_Msk             (0x1ul << SCU_PNPSET6_USBD_Pos)                   /*!< SCU_T::PNPSET6: USBD Mask              */
+
+#define SCU_PNPSET6_USCI0_Pos            (16)                                              /*!< SCU_T::PNPSET6: USCI0 Position         */
+#define SCU_PNPSET6_USCI0_Msk            (0x1ul << SCU_PNPSET6_USCI0_Pos)                  /*!< SCU_T::PNPSET6: USCI0 Mask             */
+
+#define SCU_PNPSET6_USCI1_Pos            (17)                                              /*!< SCU_T::PNPSET6: USCI1 Position         */
+#define SCU_PNPSET6_USCI1_Msk            (0x1ul << SCU_PNPSET6_USCI1_Pos)                  /*!< SCU_T::PNPSET6: USCI1 Mask             */
+
+#define SCU_IONPSET_PA_Pos               (0)                                               /*!< SCU_T::IONPSET: PA Position            */
+#define SCU_IONPSET_PA_Msk               (0x1ul << SCU_IONPSET_PA_Pos)                     /*!< SCU_T::IONPSET: PA Mask                */
+
+#define SCU_IONPSET_PB_Pos               (1)                                               /*!< SCU_T::IONPSET: PB Position            */
+#define SCU_IONPSET_PB_Msk               (0x1ul << SCU_IONPSET_PB_Pos)                     /*!< SCU_T::IONPSET: PB Mask                */
+
+#define SCU_IONPSET_PC_Pos               (2)                                               /*!< SCU_T::IONPSET: PC Position            */
+#define SCU_IONPSET_PC_Msk               (0x1ul << SCU_IONPSET_PC_Pos)                     /*!< SCU_T::IONPSET: PC Mask                */
+
+#define SCU_IONPSET_PD_Pos               (3)                                               /*!< SCU_T::IONPSET: PD Position            */
+#define SCU_IONPSET_PD_Msk               (0x1ul << SCU_IONPSET_PD_Pos)                     /*!< SCU_T::IONPSET: PD Mask                */
+
+#define SCU_IONPSET_PE_Pos               (4)                                               /*!< SCU_T::IONPSET: PE Position            */
+#define SCU_IONPSET_PE_Msk               (0x1ul << SCU_IONPSET_PE_Pos)                     /*!< SCU_T::IONPSET: PE Mask                */
+
+#define SCU_IONPSET_PF_Pos               (5)                                               /*!< SCU_T::IONPSET: PF Position            */
+#define SCU_IONPSET_PF_Msk               (0x1ul << SCU_IONPSET_PF_Pos)                     /*!< SCU_T::IONPSET: PF Mask                */
+
+#define SCU_IONPSET_PG_Pos               (6)                                               /*!< SCU_T::IONPSET: PG Position            */
+#define SCU_IONPSET_PG_Msk               (0x1ul << SCU_IONPSET_PG_Pos)                     /*!< SCU_T::IONPSET: PG Mask                */
+
+#define SCU_IONPSET_PH_Pos               (7)                                               /*!< SCU_T::IONPSET: PH Position            */
+#define SCU_IONPSET_PH_Msk               (0x1ul << SCU_IONPSET_PH_Pos)                     /*!< SCU_T::IONPSET: PH Mask                */
+
+#define SCU_SRAMNPSET_SECn_Pos           (0)                                               /*!< SCU_T::SRAMNPSET: SECn Position        */
+#define SCU_SRAMNPSET_SECn_Msk           (0xffffful << SCU_SRAMNPSET_SECn_Pos)             /*!< SCU_T::SRAMNPSET: SECn Mask            */
+
+#define SCU_MEMNPSET_FLASH_Pos           (0)                                               /*!< SCU_T::MEMNPSET: FLASH Position        */
+#define SCU_MEMNPSET_FLASH_Msk           (0x1ul << SCU_MEMNPSET_FLASH_Pos)                 /*!< SCU_T::MEMNPSET: FLASH Mask            */
+
+#define SCU_MEMNPSET_EXTMEM_Pos          (1)                                               /*!< SCU_T::MEMNPSET: EXTMEM Position       */
+#define SCU_MEMNPSET_EXTMEM_Msk          (0x1ul << SCU_MEMNPSET_EXTMEM_Pos)                /*!< SCU_T::MEMNPSET: EXTMEM Mask           */
+
+#define SCU_PVIOIEN_APB0IEN_Pos          (0)                                               /*!< SCU_T::PVIOIEN: APB0IEN Position       */
+#define SCU_PVIOIEN_APB0IEN_Msk          (0x1ul << SCU_PVIOIEN_APB0IEN_Pos)                /*!< SCU_T::PVIOIEN: APB0IEN Mask           */
+
+#define SCU_PVIOIEN_APB1IEN_Pos          (1)                                               /*!< SCU_T::PVIOIEN: APB1IEN Position       */
+#define SCU_PVIOIEN_APB1IEN_Msk          (0x1ul << SCU_PVIOIEN_APB1IEN_Pos)                /*!< SCU_T::PVIOIEN: APB1IEN Mask           */
+
+#define SCU_PVIOIEN_GPIOIEN_Pos          (4)                                               /*!< SCU_T::PVIOIEN: GPIOIEN Position       */
+#define SCU_PVIOIEN_GPIOIEN_Msk          (0x1ul << SCU_PVIOIEN_GPIOIEN_Pos)                /*!< SCU_T::PVIOIEN: GPIOIEN Mask           */
+
+#define SCU_PVIOIEN_EBIIEN_Pos           (5)                                               /*!< SCU_T::PVIOIEN: EBIIEN Position        */
+#define SCU_PVIOIEN_EBIIEN_Msk           (0x1ul << SCU_PVIOIEN_EBIIEN_Pos)                 /*!< SCU_T::PVIOIEN: EBIIEN Mask            */
+
+#define SCU_PVIOIEN_USBHIEN_Pos          (6)                                               /*!< SCU_T::PVIOIEN: USBHIEN Position       */
+#define SCU_PVIOIEN_USBHIEN_Msk          (0x1ul << SCU_PVIOIEN_USBHIEN_Pos)                /*!< SCU_T::PVIOIEN: USBHIEN Mask           */
+
+#define SCU_PVIOIEN_CRCIEN_Pos           (7)                                               /*!< SCU_T::PVIOIEN: CRCIEN Position        */
+#define SCU_PVIOIEN_CRCIEN_Msk           (0x1ul << SCU_PVIOIEN_CRCIEN_Pos)                 /*!< SCU_T::PVIOIEN: CRCIEN Mask            */
+
+#define SCU_PVIOIEN_SDH0IEN_Pos          (8)                                               /*!< SCU_T::PVIOIEN: SDH0IEN Position       */
+#define SCU_PVIOIEN_SDH0IEN_Msk          (0x1ul << SCU_PVIOIEN_SDH0IEN_Pos)                /*!< SCU_T::PVIOIEN: SDH0IEN Mask           */
+
+#define SCU_PVIOIEN_PDMA0IEN_Pos         (10)                                              /*!< SCU_T::PVIOIEN: PDMA0IEN Position      */
+#define SCU_PVIOIEN_PDMA0IEN_Msk         (0x1ul << SCU_PVIOIEN_PDMA0IEN_Pos)               /*!< SCU_T::PVIOIEN: PDMA0IEN Mask          */
+
+#define SCU_PVIOIEN_PDMA1IEN_Pos         (11)                                              /*!< SCU_T::PVIOIEN: PDMA1IEN Position      */
+#define SCU_PVIOIEN_PDMA1IEN_Msk         (0x1ul << SCU_PVIOIEN_PDMA1IEN_Pos)               /*!< SCU_T::PVIOIEN: PDMA1IEN Mask          */
+
+#define SCU_PVIOIEN_SRAM0IEN_Pos         (12)                                              /*!< SCU_T::PVIOIEN: SRAM0IEN Position      */
+#define SCU_PVIOIEN_SRAM0IEN_Msk         (0x1ul << SCU_PVIOIEN_SRAM0IEN_Pos)               /*!< SCU_T::PVIOIEN: SRAM0IEN Mask          */
+
+#define SCU_PVIOIEN_SRAM1IEN_Pos         (13)                                              /*!< SCU_T::PVIOIEN: SRAM1IEN Position      */
+#define SCU_PVIOIEN_SRAM1IEN_Msk         (0x1ul << SCU_PVIOIEN_SRAM1IEN_Pos)               /*!< SCU_T::PVIOIEN: SRAM1IEN Mask          */
+
+#define SCU_PVIOIEN_FMCIEN_Pos           (14)                                              /*!< SCU_T::PVIOIEN: FMCIEN Position        */
+#define SCU_PVIOIEN_FMCIEN_Msk           (0x1ul << SCU_PVIOIEN_FMCIEN_Pos)                 /*!< SCU_T::PVIOIEN: FMCIEN Mask            */
+
+#define SCU_PVIOIEN_FLASHIEN_Pos         (15)                                              /*!< SCU_T::PVIOIEN: FLASHIEN Position      */
+#define SCU_PVIOIEN_FLASHIEN_Msk         (0x1ul << SCU_PVIOIEN_FLASHIEN_Pos)               /*!< SCU_T::PVIOIEN: FLASHIEN Mask          */
+
+#define SCU_PVIOIEN_SCUIEN_Pos           (16)                                              /*!< SCU_T::PVIOIEN: SCUIEN Position        */
+#define SCU_PVIOIEN_SCUIEN_Msk           (0x1ul << SCU_PVIOIEN_SCUIEN_Pos)                 /*!< SCU_T::PVIOIEN: SCUIEN Mask            */
+
+#define SCU_PVIOIEN_SYSIEN_Pos           (17)                                              /*!< SCU_T::PVIOIEN: SYSIEN Position        */
+#define SCU_PVIOIEN_SYSIEN_Msk           (0x1ul << SCU_PVIOIEN_SYSIEN_Pos)                 /*!< SCU_T::PVIOIEN: SYSIEN Mask            */
+
+#define SCU_PVIOIEN_CRPTIEN_Pos          (18)                                              /*!< SCU_T::PVIOIEN: CRPTIEN Position       */
+#define SCU_PVIOIEN_CRPTIEN_Msk          (0x1ul << SCU_PVIOIEN_CRPTIEN_Pos)                /*!< SCU_T::PVIOIEN: CRPTIEN Mask           */
+
+#define SCU_PVIOIEN_KSIEN_Pos            (19)                                              /*!< SCU_T::PVIOIEN: KSIEN Position         */
+#define SCU_PVIOIEN_KSIEN_Msk            (0x1ul << SCU_PVIOIEN_KSIEN_Pos)                  /*!< SCU_T::PVIOIEN: KSIEN Mask             */
+
+#define SCU_PVINTSTS_APB0IF_Pos          (0)                                               /*!< SCU_T::PVINTSTS: APB0IF Position       */
+#define SCU_PVINTSTS_APB0IF_Msk          (0x1ul << SCU_PVINTSTS_APB0IF_Pos)                /*!< SCU_T::PVINTSTS: APB0IF Mask           */
+
+#define SCU_PVINTSTS_APB1IF_Pos          (1)                                               /*!< SCU_T::PVINTSTS: APB1IF Position       */
+#define SCU_PVINTSTS_APB1IF_Msk          (0x1ul << SCU_PVINTSTS_APB1IF_Pos)                /*!< SCU_T::PVINTSTS: APB1IF Mask           */
+
+#define SCU_PVINTSTS_GPIOIF_Pos          (4)                                               /*!< SCU_T::PVINTSTS: GPIOIF Position       */
+#define SCU_PVINTSTS_GPIOIF_Msk          (0x1ul << SCU_PVINTSTS_GPIOIF_Pos)                /*!< SCU_T::PVINTSTS: GPIOIF Mask           */
+
+#define SCU_PVINTSTS_EBIIF_Pos           (5)                                               /*!< SCU_T::PVINTSTS: EBIIF Position        */
+#define SCU_PVINTSTS_EBIIF_Msk           (0x1ul << SCU_PVINTSTS_EBIIF_Pos)                 /*!< SCU_T::PVINTSTS: EBIIF Mask            */
+
+#define SCU_PVINTSTS_USBHIF_Pos          (6)                                               /*!< SCU_T::PVINTSTS: USBHIF Position       */
+#define SCU_PVINTSTS_USBHIF_Msk          (0x1ul << SCU_PVINTSTS_USBHIF_Pos)                /*!< SCU_T::PVINTSTS: USBHIF Mask           */
+
+#define SCU_PVINTSTS_CRCIF_Pos           (7)                                               /*!< SCU_T::PVINTSTS: CRCIF Position        */
+#define SCU_PVINTSTS_CRCIF_Msk           (0x1ul << SCU_PVINTSTS_CRCIF_Pos)                 /*!< SCU_T::PVINTSTS: CRCIF Mask            */
+
+#define SCU_PVINTSTS_SDH0IF_Pos          (8)                                               /*!< SCU_T::PVINTSTS: SDH0IF Position       */
+#define SCU_PVINTSTS_SDH0IF_Msk          (0x1ul << SCU_PVINTSTS_SDH0IF_Pos)                /*!< SCU_T::PVINTSTS: SDH0IF Mask           */
+
+#define SCU_PVINTSTS_PDMA0IF_Pos         (10)                                              /*!< SCU_T::PVINTSTS: PDMA0IF Position      */
+#define SCU_PVINTSTS_PDMA0IF_Msk         (0x1ul << SCU_PVINTSTS_PDMA0IF_Pos)               /*!< SCU_T::PVINTSTS: PDMA0IF Mask          */
+
+#define SCU_PVINTSTS_PDMA1IF_Pos         (11)                                              /*!< SCU_T::PVINTSTS: PDMA1IF Position      */
+#define SCU_PVINTSTS_PDMA1IF_Msk         (0x1ul << SCU_PVINTSTS_PDMA1IF_Pos)               /*!< SCU_T::PVINTSTS: PDMA1IF Mask          */
+
+#define SCU_PVINTSTS_SRAM0IF_Pos         (12)                                              /*!< SCU_T::PVINTSTS: SRAM0IF Position      */
+#define SCU_PVINTSTS_SRAM0IF_Msk         (0x1ul << SCU_PVINTSTS_SRAM0IF_Pos)               /*!< SCU_T::PVINTSTS: SRAM0IF Mask          */
+
+#define SCU_PVINTSTS_SRAM1IF_Pos         (13)                                              /*!< SCU_T::PVINTSTS: SRAM1IF Position      */
+#define SCU_PVINTSTS_SRAM1IF_Msk         (0x1ul << SCU_PVINTSTS_SRAM1IF_Pos)               /*!< SCU_T::PVINTSTS: SRAM1IF Mask          */
+
+#define SCU_PVINTSTS_FMCIF_Pos           (14)                                              /*!< SCU_T::PVINTSTS: FMCIF Position        */
+#define SCU_PVINTSTS_FMCIF_Msk           (0x1ul << SCU_PVINTSTS_FMCIF_Pos)                 /*!< SCU_T::PVINTSTS: FMCIF Mask            */
+
+#define SCU_PVINTSTS_FLASHIF_Pos         (15)                                              /*!< SCU_T::PVINTSTS: FLASHIF Position      */
+#define SCU_PVINTSTS_FLASHIF_Msk         (0x1ul << SCU_PVINTSTS_FLASHIF_Pos)               /*!< SCU_T::PVINTSTS: FLASHIF Mask          */
+
+#define SCU_PVINTSTS_SCUIF_Pos           (16)                                              /*!< SCU_T::PVINTSTS: SCUIF Position        */
+#define SCU_PVINTSTS_SCUIF_Msk           (0x1ul << SCU_PVINTSTS_SCUIF_Pos)                 /*!< SCU_T::PVINTSTS: SCUIF Mask            */
+
+#define SCU_PVINTSTS_SYSIF_Pos           (17)                                              /*!< SCU_T::PVINTSTS: SYSIF Position        */
+#define SCU_PVINTSTS_SYSIF_Msk           (0x1ul << SCU_PVINTSTS_SYSIF_Pos)                 /*!< SCU_T::PVINTSTS: SYSIF Mask            */
+
+#define SCU_PVINTSTS_CRPTIF_Pos          (18)                                              /*!< SCU_T::PVINTSTS: CRPTIF Position       */
+#define SCU_PVINTSTS_CRPTIF_Msk          (0x1ul << SCU_PVINTSTS_CRPTIF_Pos)                /*!< SCU_T::PVINTSTS: CRPTIF Mask           */
+
+#define SCU_PVINTSTS_KSIF_Pos            (19)                                              /*!< SCU_T::PVINTSTS: KSIF Position         */
+#define SCU_PVINTSTS_KSIF_Msk            (0x1ul << SCU_PVINTSTS_KSIF_Pos)                  /*!< SCU_T::PVINTSTS: KSIF Mask             */
+
+#define SCU_NSMCTL_PRESCALE_Pos          (0)                                               /*!< SCU_T::NSMCTL: PRESCALE Position       */
+#define SCU_NSMCTL_PRESCALE_Msk          (0xfful << SCU_NSMCTL_PRESCALE_Pos)               /*!< SCU_T::NSMCTL: PRESCALE Mask           */
+
+#define SCU_NSMCTL_NSMIEN_Pos            (8)                                               /*!< SCU_T::NSMCTL: NSMIEN Position         */
+#define SCU_NSMCTL_NSMIEN_Msk            (0x1ul << SCU_NSMCTL_NSMIEN_Pos)                  /*!< SCU_T::NSMCTL: NSMIEN Mask             */
+
+#define SCU_NSMCTL_AUTORLD_Pos           (9)                                               /*!< SCU_T::NSMCTL: AUTORLD Position        */
+#define SCU_NSMCTL_AUTORLD_Msk           (0x1ul << SCU_NSMCTL_AUTORLD_Pos)                 /*!< SCU_T::NSMCTL: AUTORLD Mask            */
+
+#define SCU_NSMCTL_TMRMOD_Pos            (10)                                              /*!< SCU_T::NSMCTL: TMRMOD Position         */
+#define SCU_NSMCTL_TMRMOD_Msk            (0x1ul << SCU_NSMCTL_TMRMOD_Pos)                  /*!< SCU_T::NSMCTL: TMRMOD Mask             */
+
+#define SCU_NSMCTL_IDLEON_Pos            (12)                                              /*!< SCU_T::NSMCTL: IDLEON Position         */
+#define SCU_NSMCTL_IDLEON_Msk            (0x1ul << SCU_NSMCTL_IDLEON_Pos)                  /*!< SCU_T::NSMCTL: IDLEON Mask             */
+
+#define SCU_NSMCTL_DBGON_Pos             (13)                                              /*!< SCU_T::NSMCTL: DBGON Position          */
+#define SCU_NSMCTL_DBGON_Msk             (0x1ul << SCU_NSMCTL_DBGON_Pos)                   /*!< SCU_T::NSMCTL: DBGON Mask              */
+
+#define SCU_NSMLOAD_RELOAD_Pos           (0)                                               /*!< SCU_T::NSMLOAD: RELOAD Position        */
+#define SCU_NSMLOAD_RELOAD_Msk           (0xfffffful << SCU_NSMLOAD_RELOAD_Pos)            /*!< SCU_T::NSMLOAD: RELOAD Mask            */
+
+#define SCU_NSMVAL_VALUE_Pos             (0)                                               /*!< SCU_T::NSMVAL: VALUE Position          */
+#define SCU_NSMVAL_VALUE_Msk             (0xfffffful << SCU_NSMVAL_VALUE_Pos)              /*!< SCU_T::NSMVAL: VALUE Mask              */
+
+#define SCU_NSMSTS_CURRNS_Pos            (0)                                               /*!< SCU_T::NSMSTS: CURRNS Position         */
+#define SCU_NSMSTS_CURRNS_Msk            (0x1ul << SCU_NSMSTS_CURRNS_Pos)                  /*!< SCU_T::NSMSTS: CURRNS Mask             */
+
+#define SCU_NSMSTS_NSMIF_Pos             (1)                                               /*!< SCU_T::NSMSTS: NSMIF Position          */
+#define SCU_NSMSTS_NSMIF_Msk             (0x1ul << SCU_NSMSTS_NSMIF_Pos)                   /*!< SCU_T::NSMSTS: NSMIF Mask              */
+
+#define SCU_BBE_BBEEN_Pos                (0)                                               /*!< SCU_T::BBE: BBEEN Position             */
+#define SCU_BBE_BBEEN_Msk                (0x1ul << SCU_BBE_BBEEN_Pos)                      /*!< SCU_T::BBE: BBEEN Mask                 */
+
+#define SCU_BBE_WVERY_Pos                (8)                                               /*!< SCU_T::BBE: WVERY Position             */
+#define SCU_BBE_WVERY_Msk                (0xfffffful << SCU_BBE_WVERY_Pos)                 /*!< SCU_T::BBE: WVERY Mask                 */
+
+#define SCU_IDAUANS_IDAUANSEN_Pos        (0)                                               /*!< SCU_T::IDAUANS: IDAUANSEN Position     */
+#define SCU_IDAUANS_IDAUANSEN_Msk        (0x1ul << SCU_IDAUANS_IDAUANSEN_Pos)              /*!< SCU_T::IDAUANS: IDAUANSEN Mask         */
+
+#define SCU_IDAUANS_WVERY_Pos            (8)                                               /*!< SCU_T::IDAUANS: WVERY Position         */
+#define SCU_IDAUANS_WVERY_Msk            (0xfffffful << SCU_IDAUANS_WVERY_Pos)             /*!< SCU_T::IDAUANS: WVERY Mask             */
+
+#define SCU_VERSION_MINOR_Pos            (0)                                               /*!< SCU_T::VERSION: MINOR Position         */
+#define SCU_VERSION_MINOR_Msk            (0xfffful << SCU_VERSION_MINOR_Pos)               /*!< SCU_T::VERSION: MINOR Mask             */
+
+#define SCU_VERSION_SUB_Pos              (16)                                              /*!< SCU_T::VERSION: SUB Position           */
+#define SCU_VERSION_SUB_Msk              (0xfful << SCU_VERSION_SUB_Pos)                   /*!< SCU_T::VERSION: SUB Mask               */
+
+#define SCU_VERSION_MAJOR_Pos            (24)                                              /*!< SCU_T::VERSION: MAJOR Position         */
+#define SCU_VERSION_MAJOR_Msk            (0xfful << SCU_VERSION_MAJOR_Pos)                 /*!< SCU_T::VERSION: MAJOR Mask             */
+
+/**@}*/ /* SCU_CONST */
+/**@}*/ /* end of SCU register group */
+
+
+/**@}*/ /* end of REGISTER group */
+#endif /* __SCU_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/sdh_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/sdh_reg.h
new file mode 100644
index 0000000000..2ce64f3c52
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/sdh_reg.h
@@ -0,0 +1,528 @@
+/**************************************************************************//**
+ * @file     sdh_reg.h
+ * @version  V1.00
+ * @brief    SDH register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __SDH_REG_H__
+#define __SDH_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+/*---------------------- SD Card Host Interface -------------------------*/
+/**
+    @addtogroup SDH SD Card Host Interface(SDH)
+    Memory Mapped Structure for SDH Controller
+  @{
+*/
+
+typedef struct
+{
+
+    /**
+     * @var SDH_T::FB
+     * Offset: 0x00~0x7C  Shared Buffer (FIFO)
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |BUFFER    |Shared Buffer
+     * |        |          |Buffer for DMA transfer
+     * @var SDH_T::DMACTL
+     * Offset: 0x400  DMA Control and Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |DMAEN     |DMA Engine Enable Bit
+     * |        |          |If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state.
+     * |        |          |0 = DMA Disabled.
+     * |        |          |1 = DMA Enabled.
+     * |        |          |Note: If target abort is occurred, DMAEN will be cleared.
+     * |[1]     |DMARST    |Software Engine Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset internal state machine and pointers
+     * |        |          |The contents of control register will not be cleared
+     * |        |          |This bit will auto be cleared after few clock cycles.
+     * |        |          |Note: The software reset DMA related registers.
+     * |[3]     |SGEN      |Scatter-gather Function Enable Bit
+     * |        |          |0 = Scatter-gather function Disabled (DMA will treat the starting address in DMASAR as starting pointer of a single block memory).
+     * |        |          |1 = Scatter-gather function Enabled (DMA will treat the starting address in DMASAR as a starting address of Physical Address Descriptor (PAD) table
+     * |        |          |The format of these Pads' will be described later).
+     * |[9]     |DMABUSY   |DMA Transfer Is in Progress
+     * |        |          |This bit indicates if SD Host is granted and doing DMA transfer or not.
+     * |        |          |0 = DMA transfer is not in progress.
+     * |        |          |1 = DMA transfer is in progress.
+     * @var SDH_T::DMASA
+     * Offset: 0x408  DMA Transfer Starting Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ORDER     |Determined to the PAD Table Fetching Is in Order or Out of Order
+     * |        |          |0 = PAD table is fetched in order.
+     * |        |          |1 = PAD table is fetched out of order.
+     * |        |          |Note: the bit0 is valid in scatter-gather mode when SGEN = 1.
+     * |[31:1]  |DMASA     |DMA Transfer Starting Address
+     * |        |          |This field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMA to retrieve or fill in data.
+     * |        |          |If DMA is not in normal mode, this field will be interpreted as a starting address of Physical Address Descriptor (PAD) table.
+     * |        |          |Note: Starting address of the SRAM must be word aligned, for example, 0x0000_0000, 0x0000_0004.
+     * @var SDH_T::DMABCNT
+     * Offset: 0x40C  DMA Transfer Byte Count Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[25:0]  |BCNT      |DMA Transfer Byte Count (Read Only)
+     * |        |          |This field indicates the remained byte count of DMA transfer
+     * |        |          |The value of this field is valid only when DMA is busy; otherwise, it is 0.
+     * @var SDH_T::DMAINTEN
+     * Offset: 0x410  DMA Interrupt Enable Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ABORTIEN  |DMA Read/Write Target Abort Interrupt Enable Bit
+     * |        |          |0 = Target abort interrupt generation Disabled during DMA transfer.
+     * |        |          |1 = Target abort interrupt generation Enabled during DMA transfer.
+     * |[1]     |WEOTIEN   |Wrong EOT Encountered Interrupt Enable Bit
+     * |        |          |0 = Interrupt generation Disabled when wrong EOT is encountered.
+     * |        |          |1 = Interrupt generation Enabled when wrong EOT is encountered.
+     * @var SDH_T::DMAINTSTS
+     * Offset: 0x414  DMA Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ABORTIF   |DMA Read/Write Target Abort Interrupt Flag
+     * |        |          |0 = No bus ERROR response received.
+     * |        |          |1 = Bus ERROR response received.
+     * |        |          |Note1: This bit is read only, but can be cleared by writing '1' to it.
+     * |        |          |Note2: When DMA's bus master received ERROR response, it means that target abort is happened
+     * |        |          |DMA will stop transfer and respond this event and then go to IDLE state
+     * |        |          |When target abort occurred or WEOTIF is set, software must reset DMA and SD host, and then transfer those data again.
+     * |[1]     |WEOTIF    |Wrong EOT Encountered Interrupt Flag
+     * |        |          |When DMA Scatter-Gather function is enabled, and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of SD host), this bit will be set.
+     * |        |          |0 = No EOT encountered before DMA transfer finished.
+     * |        |          |1 = EOT encountered before DMA transfer finished.
+     * |        |          |Note: This bit is read only, but can be cleared by writing '1' to it.
+     * @var SDH_T::GCTL
+     * Offset: 0x800  Global Control and Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |GCTLRST   |Software Engine Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset SD host
+     * |        |          |The contents of control register will not be cleared
+     * |        |          |This bit will auto cleared after reset complete.
+     * |[1]     |SDEN      |Secure Digital Functionality Enable Bit
+     * |        |          |0 = SD functionality disabled.
+     * |        |          |1 = SD functionality enabled.
+     * @var SDH_T::GINTEN
+     * Offset: 0x804  Global Interrupt Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |DTAIEN    |DMA READ/WRITE Target Abort Interrupt Enable Bit
+     * |        |          |0 = DMA READ/WRITE target abort interrupt generation disabled.
+     * |        |          |1 = DMA READ/WRITE target abort interrupt generation enabled.
+     * @var SDH_T::GINTSTS
+     * Offset: 0x808  Global Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |DTAIF     |DMA READ/WRITE Target Abort Interrupt Flag (Read Only)
+     * |        |          |This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation
+     * |        |          |When Target Abort is occurred, please reset all engine.
+     * |        |          |0 = No bus ERROR response received.
+     * |        |          |1 = Bus ERROR response received.
+     * |        |          |Note: This bit is read only, but can be cleared by writing '1' to it.
+     * @var SDH_T::CTL
+     * Offset: 0x820  SD Control and Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |COEN      |Command Output Enable Bit
+     * |        |          |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
+     * |        |          |1 = Enabled, SD host will output a command to SD card.
+     * |        |          |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
+     * |[1]     |RIEN      |Response Input Enable Bit
+     * |        |          |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
+     * |        |          |1 = Enabled, SD host will wait to receive a response from SD card.
+     * |        |          |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
+     * |[2]     |DIEN      |Data Input Enable Bit
+     * |        |          |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
+     * |        |          |1 = Enabled, SD host will wait to receive block data and the CRC16 value from SD card.
+     * |        |          |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
+     * |[3]     |DOEN      |Data Output Enable Bit
+     * |        |          |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
+     * |        |          |1 = Enabled, SD host will transfer block data and the CRC16 value to SD card.
+     * |        |          |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
+     * |[4]     |R2EN      |Response R2 Input Enable Bit
+     * |        |          |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
+     * |        |          |1 = Enabled, SD host will wait to receive a response R2 from SD card and store the response data into DMC's flash buffer (exclude CRC7).
+     * |        |          |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
+     * |[5]     |CLK74OEN  |Initial 74 Clock Cycles Output Enable Bit
+     * |        |          |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
+     * |        |          |1 = Enabled, SD host will output 74 clock cycles to SD card.
+     * |        |          |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
+     * |[6]     |CLK8OEN   |Generating 8 Clock Cycles Output Enable Bit
+     * |        |          |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
+     * |        |          |1 = Enabled, SD host will output 8 clock cycles.
+     * |        |          |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
+     * |[7]     |CLKKEEP0  |SD Clock Enable Control for Port 0
+     * |        |          |0 = SD host decided when to output clock and when to disable clock output automatically.
+     * |        |          |1 = SD clock always keeps free running.
+     * |[13:8]  |CMDCODE   |SD Command Code
+     * |        |          |This register contains the SD command code (0x00 ~ 0x3F).
+     * |[14]    |CTLRST    |Software Engine Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset the internal state machine and counters
+     * |        |          |The contents of control register will not be cleared (but RIEN, DIEN, DOEN and R2EN will be cleared)
+     * |        |          |This bit will be auto cleared after few clock cycles.
+     * |[15]    |DBW       |SD Data Bus Width (for 1-bit / 4-bit Selection)
+     * |        |          |0 = Data bus width is 1-bit.
+     * |        |          |1 = Data bus width is 4-bit.
+     * |[23:16] |BLKCNT    |Block Counts to Be Transferred or Received
+     * |        |          |This field contains the block counts for data-in and data-out transfer
+     * |        |          |For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, software can use this function to accelerate data transfer and improve performance
+     * |        |          |Don't fill 0x0 to this field.
+     * |        |          |Note: For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, the actual total length is BLKCNT * (BLKLEN +1).
+     * |[27:24] |SDNWR     |NWR Parameter for Block Write Operation
+     * |        |          |This value indicates the NWR parameter for data block write operation in SD clock counts
+     * |        |          |The actual clock cycle will be SDNWR+1.
+     * @var SDH_T::CMDARG
+     * Offset: 0x824  SD Command Argument Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |ARGUMENT  |SD Command Argument
+     * |        |          |This register contains a 32-bit value specifies the argument of SD command from host controller to SD card
+     * |        |          |Before trigger COEN (SDH_CTL [0]), software should fill argument in this field.
+     * @var SDH_T::INTEN
+     * Offset: 0x828  SD Interrupt Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BLKDIEN   |Block Transfer Done Interrupt Enable Bit
+     * |        |          |0 = SD host will not generate interrupt when data-in (out) transfer done.
+     * |        |          |1 = SD host will generate interrupt when data-in (out) transfer done.
+     * |[1]     |CRCIEN    |CRC7, CRC16 and CRC Status Error Interrupt Enable Bit
+     * |        |          |0 = SD host will not generate interrupt when CRC7, CRC16 and CRC status is error.
+     * |        |          |1 = SD host will generate interrupt when CRC7, CRC16 and CRC status is error.
+     * |[8]     |CDIEN0    |SD0 Card Detection Interrupt Enable Bit
+     * |        |          |Enable/Disable interrupts generation of SD controller when card 0 is inserted or removed.
+     * |        |          |0 = SD card detection interrupt Disabled.
+     * |        |          |1 = SD card detection interrupt Enabled.
+     * |[12]    |RTOIEN    |Response Time-out Interrupt Enable Bit
+     * |        |          |Enable/Disable interrupts generation of SD controller when receiving response or R2 time-out
+     * |        |          |Time-out value is specified at TOUT register.
+     * |        |          |0 = Response time-out interrupt Disabled.
+     * |        |          |1 = Response time-out interrupt Enabled.
+     * |[13]    |DITOIEN   |Data Input Time-out Interrupt Enable Bit
+     * |        |          |Enable/Disable interrupts generation of SD controller when data input time-out
+     * |        |          |Time-out value is specified at TOUT register.
+     * |        |          |0 = Data input time-out interrupt Disabled.
+     * |        |          |1 = Data input time-out interrupt Enabled.
+     * |[14]    |WKIEN     |Wake-up Signal Generating Enable Bit
+     * |        |          |Enable/Disable wake-up signal generating of SD host when current using SD card issues an interrupt (wake-up) via DAT [1] to host.
+     * |        |          |0 = Wake-up signal generating Disabled.
+     * |        |          |1 = Wake-up signal generating Enabled.
+     * |[30]    |CDSRC0    |SD0 Card Detect Source Selection
+     * |        |          |0 = From SD0 card's DAT3 pin.
+     * |        |          |Host need clock to got data on pin DAT3
+     * |        |          |Please make sure CLKKEEP0 (SDH_CTL[7]) is 1 in order to generate free running clock for DAT3 pin.
+     * |        |          |1 = From GPIO pin.
+     * @var SDH_T::INTSTS
+     * Offset: 0x82C  SD Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BLKDIF    |Block Transfer Done Interrupt Flag (Read Only)
+     * |        |          |This bit indicates that SD host has finished all data-in or data-out block transfer
+     * |        |          |If there is a CRC16 error or incorrect CRC status during multiple block data transfer, the transfer will be broken and this bit will also be set.
+     * |        |          |0 = Not finished yet.
+     * |        |          |1 = Done.
+     * |        |          |Note: This bit is read only, but can be cleared by writing '1' to it.
+     * |[1]     |CRCIF     |CRC7, CRC16 and CRC Status Error Interrupt Flag (Read Only)
+     * |        |          |This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer
+     * |        |          |When CRC error is occurred, software should reset SD engine
+     * |        |          |Some response (ex
+     * |        |          |R3) doesn't have CRC7 information with it; SD host will still calculate CRC7, get CRC error and set this flag
+     * |        |          |In this condition, software should ignore CRC error and clears this bit manually.
+     * |        |          |0 = No CRC error is occurred.
+     * |        |          |1 = CRC error is occurred.
+     * |        |          |Note: This bit is read only, but can be cleared by writing '1' to it.
+     * |[2]     |CRC7      |CRC7 Check Status (Read Only)
+     * |        |          |SD host will check CRC7 correctness during each response in
+     * |        |          |If that response does not contain CRC7 information (ex
+     * |        |          |R3), then software should turn off CRCIEN (SDH_INTEN[1]) and ignore this bit.
+     * |        |          |0 = Fault.
+     * |        |          |1 = OK.
+     * |[3]     |CRC16     |CRC16 Check Status of Data-in Transfer (Read Only)
+     * |        |          |SD host will check CRC16 correctness after data-in transfer.
+     * |        |          |0 = Fault.
+     * |        |          |1 = OK.
+     * |[6:4]   |CRCSTS    |CRC Status Value of Data-out Transfer (Read Only)
+     * |        |          |SD host will record CRC status of data-out transfer
+     * |        |          |Software could use this value to identify what type of error is during data-out transfer.
+     * |        |          |010 = Positive CRC status.
+     * |        |          |101 = Negative CRC status.
+     * |        |          |111 = SD card programming error occurs.
+     * |[7]     |DAT0STS   |DAT0 Pin Status of Current Selected SD Port (Read Only)
+     * |        |          |This bit is the DAT0 pin status of current selected SD port.
+     * |[8]     |CDIF0     |SD0 Card Detection Interrupt Flag (Read Only)
+     * |        |          |This bit indicates that SD card 0 is inserted or removed
+     * |        |          |Only when CDIEN0 (SDH_INTEN[8]) is set to 1, this bit is active.
+     * |        |          |0 = No card is inserted or removed.
+     * |        |          |1 = There is a card inserted in or removed from SD0.
+     * |        |          |Note: This bit is read only, but can be cleared by writing '1' to it.
+     * |[12]    |RTOIF     |Response Time-out Interrupt Flag (Read Only)
+     * |        |          |This bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit).
+     * |        |          |0 = Not time-out.
+     * |        |          |1 = Response time-out.
+     * |        |          |Note: This bit is read only, but can be cleared by writing '1' to it.
+     * |[13]    |DITOIF    |Data Input Time-out Interrupt Flag (Read Only)
+     * |        |          |This bit indicates that SD host counts to time-out value when receiving data (waiting start bit).
+     * |        |          |0 = Not time-out.
+     * |        |          |1 = Data input time-out.
+     * |        |          |Note: This bit is read only, but can be cleared by writing '1' to it.
+     * |[16]    |CDSTS0    |Card Detect Status of SD0 (Read Only)
+     * |        |          |This bit indicates the card detect pin status of SD0, and is used for card detection
+     * |        |          |When there is a card inserted in or removed from SD0, software should check this bit to confirm if there is really a card insertion or removal.
+     * |        |          |If CDSRC0 (SDH_INTEN[30]) = 0, to select DAT3 for card detection:.
+     * |        |          |0 = Card removed.
+     * |        |          |1 = Card inserted.
+     * |        |          |If CDSRC0 (SDH_INTEN[30]) = 1, to select GPIO for card detection:.
+     * |        |          |0 = Card inserted.
+     * |        |          |1 = Card removed.
+     * |[18]    |DAT1STS   |DAT1 Pin Status of SD Port (Read Only)
+     * |        |          |This bit indicates the DAT1 pin status of SD port.
+     * @var SDH_T::RESP0
+     * Offset: 0x830  SD Receiving Response Token Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |RESPTK0   |SD Receiving Response Token 0
+     * |        |          |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set
+     * |        |          |This field contains response bit 47-16 of the response token.
+     * @var SDH_T::RESP1
+     * Offset: 0x834  SD Receiving Response Token Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |RESPTK1   |SD Receiving Response Token 1
+     * |        |          |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set
+     * |        |          |This register contains the bit 15-8 of the response token.
+     * @var SDH_T::BLEN
+     * Offset: 0x838  SD Block Length Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[10:0]  |BLKLEN    |SD BLOCK LENGTH in Byte Unit
+     * |        |          |An 11-bit value specifies the SD transfer byte count of a block
+     * |        |          |The actual byte count is equal to BLKLEN+1.
+     * |        |          |Note: The default SD block length is 512 bytes
+     * @var SDH_T::TOUT
+     * Offset: 0x83C  SD Response/Data-in Time-out Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:0]  |TOUT      |SD Response/Data-in Time-out Value
+     * |        |          |A 24-bit value specifies the time-out counts of response and data input
+     * |        |          |SD host controller will wait start bit of response or data-in until this value reached
+     * |        |          |The time period depends on SD engine clock frequency
+     * |        |          |Do not write a small number into this field, or you may never get response or data due to time-out.
+     * |        |          |Note: Filling 0x0 into this field will disable hardware time-out function.
+     */
+
+    __IO uint32_t FB[32];                /*!< Shared Buffer (FIFO)                                                      */
+    __I  uint32_t RESERVE0[224];
+    __IO uint32_t DMACTL;                /*!< [0x0400] DMA Control and Status Register                                  */
+    __I  uint32_t RESERVE1[1];
+    __IO uint32_t DMASA;                 /*!< [0x0408] DMA Transfer Starting Address Register                           */
+    __I  uint32_t DMABCNT;               /*!< [0x040c] DMA Transfer Byte Count Register                                 */
+    __IO uint32_t DMAINTEN;              /*!< [0x0410] DMA Interrupt Enable Control Register                            */
+    __IO uint32_t DMAINTSTS;             /*!< [0x0414] DMA Interrupt Status Register                                    */
+    __I  uint32_t RESERVE2[250];
+    __IO uint32_t GCTL;                  /*!< [0x0800] Global Control and Status Register                               */
+    __IO uint32_t GINTEN;                /*!< [0x0804] Global Interrupt Control Register                                */
+    __IO uint32_t GINTSTS;               /*!< [0x0808] Global Interrupt Status Register                                 */
+    __I  uint32_t RESERVE3[5];
+    __IO uint32_t CTL;                   /*!< [0x0820] SD Control and Status Register                                   */
+    __IO uint32_t CMDARG;                /*!< [0x0824] SD Command Argument Register                                     */
+    __IO uint32_t INTEN;                 /*!< [0x0828] SD Interrupt Control Register                                    */
+    __IO uint32_t INTSTS;                /*!< [0x082c] SD Interrupt Status Register                                     */
+    __I  uint32_t RESP0;                 /*!< [0x0830] SD Receiving Response Token Register 0                           */
+    __I  uint32_t RESP1;                 /*!< [0x0834] SD Receiving Response Token Register 1                           */
+    __IO uint32_t BLEN;                  /*!< [0x0838] SD Block Length Register                                         */
+    __IO uint32_t TOUT;                  /*!< [0x083c] SD Response/Data-in Time-out Register                            */
+
+} SDH_T;
+
+/**
+    @addtogroup SDH_CONST SDH Bit Field Definition
+    Constant Definitions for SDH Controller
+  @{
+*/
+
+#define SDH_DMACTL_DMAEN_Pos             (0)                                               /*!< SDH_T::DMACTL: DMAEN Position          */
+#define SDH_DMACTL_DMAEN_Msk             (0x1ul << SDH_DMACTL_DMAEN_Pos)                   /*!< SDH_T::DMACTL: DMAEN Mask              */
+
+#define SDH_DMACTL_DMARST_Pos            (1)                                               /*!< SDH_T::DMACTL: DMARST Position         */
+#define SDH_DMACTL_DMARST_Msk            (0x1ul << SDH_DMACTL_DMARST_Pos)                  /*!< SDH_T::DMACTL: DMARST Mask             */
+
+#define SDH_DMACTL_SGEN_Pos              (3)                                               /*!< SDH_T::DMACTL: SGEN Position           */
+#define SDH_DMACTL_SGEN_Msk              (0x1ul << SDH_DMACTL_SGEN_Pos)                    /*!< SDH_T::DMACTL: SGEN Mask               */
+
+#define SDH_DMACTL_DMABUSY_Pos           (9)                                               /*!< SDH_T::DMACTL: DMABUSY Position        */
+#define SDH_DMACTL_DMABUSY_Msk           (0x1ul << SDH_DMACTL_DMABUSY_Pos)                 /*!< SDH_T::DMACTL: DMABUSY Mask            */
+
+#define SDH_DMASA_ORDER_Pos              (0)                                               /*!< SDH_T::DMASA: ORDER Position           */
+#define SDH_DMASA_ORDER_Msk              (0x1ul << SDH_DMASA_ORDER_Pos)                    /*!< SDH_T::DMASA: ORDER Mask               */
+
+#define SDH_DMASA_DMASA_Pos              (1)                                               /*!< SDH_T::DMASA: DMASA Position           */
+#define SDH_DMASA_DMASA_Msk              (0x7ffffffful << SDH_DMASA_DMASA_Pos)             /*!< SDH_T::DMASA: DMASA Mask               */
+
+#define SDH_DMABCNT_BCNT_Pos             (0)                                               /*!< SDH_T::DMABCNT: BCNT Position          */
+#define SDH_DMABCNT_BCNT_Msk             (0x3fffffful << SDH_DMABCNT_BCNT_Pos)             /*!< SDH_T::DMABCNT: BCNT Mask              */
+
+#define SDH_DMAINTEN_ABORTIEN_Pos        (0)                                               /*!< SDH_T::DMAINTEN: ABORTIEN Position     */
+#define SDH_DMAINTEN_ABORTIEN_Msk        (0x1ul << SDH_DMAINTEN_ABORTIEN_Pos)              /*!< SDH_T::DMAINTEN: ABORTIEN Mask         */
+
+#define SDH_DMAINTEN_WEOTIEN_Pos         (1)                                               /*!< SDH_T::DMAINTEN: WEOTIEN Position      */
+#define SDH_DMAINTEN_WEOTIEN_Msk         (0x1ul << SDH_DMAINTEN_WEOTIEN_Pos)               /*!< SDH_T::DMAINTEN: WEOTIEN Mask          */
+
+#define SDH_DMAINTSTS_ABORTIF_Pos        (0)                                               /*!< SDH_T::DMAINTSTS: ABORTIF Position     */
+#define SDH_DMAINTSTS_ABORTIF_Msk        (0x1ul << SDH_DMAINTSTS_ABORTIF_Pos)              /*!< SDH_T::DMAINTSTS: ABORTIF Mask         */
+
+#define SDH_DMAINTSTS_WEOTIF_Pos         (1)                                               /*!< SDH_T::DMAINTSTS: WEOTIF Position      */
+#define SDH_DMAINTSTS_WEOTIF_Msk         (0x1ul << SDH_DMAINTSTS_WEOTIF_Pos)               /*!< SDH_T::DMAINTSTS: WEOTIF Mask          */
+
+#define SDH_GCTL_GCTLRST_Pos             (0)                                               /*!< SDH_T::GCTL: GCTLRST Position          */
+#define SDH_GCTL_GCTLRST_Msk             (0x1ul << SDH_GCTL_GCTLRST_Pos)                   /*!< SDH_T::GCTL: GCTLRST Mask              */
+
+#define SDH_GCTL_SDEN_Pos                (1)                                               /*!< SDH_T::GCTL: SDEN Position             */
+#define SDH_GCTL_SDEN_Msk                (0x1ul << SDH_GCTL_SDEN_Pos)                      /*!< SDH_T::GCTL: SDEN Mask                 */
+
+#define SDH_GINTEN_DTAIEN_Pos            (0)                                               /*!< SDH_T::GINTEN: DTAIEN Position         */
+#define SDH_GINTEN_DTAIEN_Msk            (0x1ul << SDH_GINTEN_DTAIEN_Pos)                  /*!< SDH_T::GINTEN: DTAIEN Mask             */
+
+#define SDH_GINTSTS_DTAIF_Pos            (0)                                               /*!< SDH_T::GINTSTS: DTAIF Position         */
+#define SDH_GINTSTS_DTAIF_Msk            (0x1ul << SDH_GINTSTS_DTAIF_Pos)                  /*!< SDH_T::GINTSTS: DTAIF Mask             */
+
+#define SDH_CTL_COEN_Pos                 (0)                                               /*!< SDH_T::CTL: COEN Position              */
+#define SDH_CTL_COEN_Msk                 (0x1ul << SDH_CTL_COEN_Pos)                       /*!< SDH_T::CTL: COEN Mask                  */
+
+#define SDH_CTL_RIEN_Pos                 (1)                                               /*!< SDH_T::CTL: RIEN Position              */
+#define SDH_CTL_RIEN_Msk                 (0x1ul << SDH_CTL_RIEN_Pos)                       /*!< SDH_T::CTL: RIEN Mask                  */
+
+#define SDH_CTL_DIEN_Pos                 (2)                                               /*!< SDH_T::CTL: DIEN Position              */
+#define SDH_CTL_DIEN_Msk                 (0x1ul << SDH_CTL_DIEN_Pos)                       /*!< SDH_T::CTL: DIEN Mask                  */
+
+#define SDH_CTL_DOEN_Pos                 (3)                                               /*!< SDH_T::CTL: DOEN Position              */
+#define SDH_CTL_DOEN_Msk                 (0x1ul << SDH_CTL_DOEN_Pos)                       /*!< SDH_T::CTL: DOEN Mask                  */
+
+#define SDH_CTL_R2EN_Pos                 (4)                                               /*!< SDH_T::CTL: R2EN Position              */
+#define SDH_CTL_R2EN_Msk                 (0x1ul << SDH_CTL_R2EN_Pos)                       /*!< SDH_T::CTL: R2EN Mask                  */
+
+#define SDH_CTL_CLK74OEN_Pos             (5)                                               /*!< SDH_T::CTL: CLK74OEN Position          */
+#define SDH_CTL_CLK74OEN_Msk             (0x1ul << SDH_CTL_CLK74OEN_Pos)                   /*!< SDH_T::CTL: CLK74OEN Mask              */
+
+#define SDH_CTL_CLK8OEN_Pos              (6)                                               /*!< SDH_T::CTL: CLK8OEN Position           */
+#define SDH_CTL_CLK8OEN_Msk              (0x1ul << SDH_CTL_CLK8OEN_Pos)                    /*!< SDH_T::CTL: CLK8OEN Mask               */
+
+#define SDH_CTL_CLKKEEP_Pos              (7)                                               /*!< SDH_T::CTL: CLKKEEP Position          */
+#define SDH_CTL_CLKKEEP_Msk              (0x1ul << SDH_CTL_CLKKEEP_Pos)                    /*!< SDH_T::CTL: CLKKEEP Mask              */
+
+#define SDH_CTL_CMDCODE_Pos              (8)                                               /*!< SDH_T::CTL: CMDCODE Position           */
+#define SDH_CTL_CMDCODE_Msk              (0x3ful << SDH_CTL_CMDCODE_Pos)                   /*!< SDH_T::CTL: CMDCODE Mask               */
+
+#define SDH_CTL_CTLRST_Pos               (14)                                              /*!< SDH_T::CTL: CTLRST Position            */
+#define SDH_CTL_CTLRST_Msk               (0x1ul << SDH_CTL_CTLRST_Pos)                     /*!< SDH_T::CTL: CTLRST Mask                */
+
+#define SDH_CTL_DBW_Pos                  (15)                                              /*!< SDH_T::CTL: DBW Position               */
+#define SDH_CTL_DBW_Msk                  (0x1ul << SDH_CTL_DBW_Pos)                        /*!< SDH_T::CTL: DBW Mask                   */
+
+#define SDH_CTL_BLKCNT_Pos               (16)                                              /*!< SDH_T::CTL: BLKCNT Position            */
+#define SDH_CTL_BLKCNT_Msk               (0xfful << SDH_CTL_BLKCNT_Pos)                    /*!< SDH_T::CTL: BLKCNT Mask                */
+
+#define SDH_CTL_SDNWR_Pos                (24)                                              /*!< SDH_T::CTL: SDNWR Position             */
+#define SDH_CTL_SDNWR_Msk                (0xful << SDH_CTL_SDNWR_Pos)                      /*!< SDH_T::CTL: SDNWR Mask                 */
+
+#define SDH_CMDARG_ARGUMENT_Pos          (0)                                               /*!< SDH_T::CMDARG: ARGUMENT Position       */
+#define SDH_CMDARG_ARGUMENT_Msk          (0xfffffffful << SDH_CMDARG_ARGUMENT_Pos)         /*!< SDH_T::CMDARG: ARGUMENT Mask           */
+
+#define SDH_INTEN_BLKDIEN_Pos            (0)                                               /*!< SDH_T::INTEN: BLKDIEN Position         */
+#define SDH_INTEN_BLKDIEN_Msk            (0x1ul << SDH_INTEN_BLKDIEN_Pos)                  /*!< SDH_T::INTEN: BLKDIEN Mask             */
+
+#define SDH_INTEN_CRCIEN_Pos             (1)                                               /*!< SDH_T::INTEN: CRCIEN Position          */
+#define SDH_INTEN_CRCIEN_Msk             (0x1ul << SDH_INTEN_CRCIEN_Pos)                   /*!< SDH_T::INTEN: CRCIEN Mask              */
+
+#define SDH_INTEN_CDIEN_Pos              (8)                                               /*!< SDH_T::INTEN: CDIEN Position          */
+#define SDH_INTEN_CDIEN_Msk              (0x1ul << SDH_INTEN_CDIEN_Pos)                    /*!< SDH_T::INTEN: CDIEN Mask              */
+
+#define SDH_INTEN_RTOIEN_Pos             (12)                                              /*!< SDH_T::INTEN: RTOIEN Position          */
+#define SDH_INTEN_RTOIEN_Msk             (0x1ul << SDH_INTEN_RTOIEN_Pos)                   /*!< SDH_T::INTEN: RTOIEN Mask              */
+
+#define SDH_INTEN_DITOIEN_Pos            (13)                                              /*!< SDH_T::INTEN: DITOIEN Position         */
+#define SDH_INTEN_DITOIEN_Msk            (0x1ul << SDH_INTEN_DITOIEN_Pos)                  /*!< SDH_T::INTEN: DITOIEN Mask             */
+
+#define SDH_INTEN_WKIEN_Pos              (14)                                              /*!< SDH_T::INTEN: WKIEN Position           */
+#define SDH_INTEN_WKIEN_Msk              (0x1ul << SDH_INTEN_WKIEN_Pos)                    /*!< SDH_T::INTEN: WKIEN Mask               */
+
+#define SDH_INTEN_CDSRC_Pos              (30)                                              /*!< SDH_T::INTEN: CDSRC Position          */
+#define SDH_INTEN_CDSRC_Msk              (0x1ul << SDH_INTEN_CDSRC_Pos)                    /*!< SDH_T::INTEN: CDSRC Mask              */
+
+#define SDH_INTSTS_BLKDIF_Pos            (0)                                               /*!< SDH_T::INTSTS: BLKDIF Position         */
+#define SDH_INTSTS_BLKDIF_Msk            (0x1ul << SDH_INTSTS_BLKDIF_Pos)                  /*!< SDH_T::INTSTS: BLKDIF Mask             */
+
+#define SDH_INTSTS_CRCIF_Pos             (1)                                               /*!< SDH_T::INTSTS: CRCIF Position          */
+#define SDH_INTSTS_CRCIF_Msk             (0x1ul << SDH_INTSTS_CRCIF_Pos)                   /*!< SDH_T::INTSTS: CRCIF Mask              */
+
+#define SDH_INTSTS_CRC7_Pos              (2)                                               /*!< SDH_T::INTSTS: CRC7 Position           */
+#define SDH_INTSTS_CRC7_Msk              (0x1ul << SDH_INTSTS_CRC7_Pos)                    /*!< SDH_T::INTSTS: CRC7 Mask               */
+
+#define SDH_INTSTS_CRC16_Pos             (3)                                               /*!< SDH_T::INTSTS: CRC16 Position          */
+#define SDH_INTSTS_CRC16_Msk             (0x1ul << SDH_INTSTS_CRC16_Pos)                   /*!< SDH_T::INTSTS: CRC16 Mask              */
+
+#define SDH_INTSTS_CRCSTS_Pos            (4)                                               /*!< SDH_T::INTSTS: CRCSTS Position         */
+#define SDH_INTSTS_CRCSTS_Msk            (0x7ul << SDH_INTSTS_CRCSTS_Pos)                  /*!< SDH_T::INTSTS: CRCSTS Mask             */
+
+#define SDH_INTSTS_DAT0STS_Pos           (7)                                               /*!< SDH_T::INTSTS: DAT0STS Position        */
+#define SDH_INTSTS_DAT0STS_Msk           (0x1ul << SDH_INTSTS_DAT0STS_Pos)                 /*!< SDH_T::INTSTS: DAT0STS Mask            */
+
+#define SDH_INTSTS_CDIF_Pos              (8)                                               /*!< SDH_T::INTSTS: CDIF Position          */
+#define SDH_INTSTS_CDIF_Msk              (0x1ul << SDH_INTSTS_CDIF_Pos)                    /*!< SDH_T::INTSTS: CDIF Mask              */
+
+#define SDH_INTSTS_RTOIF_Pos             (12)                                              /*!< SDH_T::INTSTS: RTOIF Position          */
+#define SDH_INTSTS_RTOIF_Msk             (0x1ul << SDH_INTSTS_RTOIF_Pos)                   /*!< SDH_T::INTSTS: RTOIF Mask              */
+
+#define SDH_INTSTS_DITOIF_Pos            (13)                                              /*!< SDH_T::INTSTS: DITOIF Position         */
+#define SDH_INTSTS_DITOIF_Msk            (0x1ul << SDH_INTSTS_DITOIF_Pos)                  /*!< SDH_T::INTSTS: DITOIF Mask             */
+
+#define SDH_INTSTS_CDSTS_Pos             (16)                                              /*!< SDH_T::INTSTS: CDSTS Position         */
+#define SDH_INTSTS_CDSTS_Msk             (0x1ul << SDH_INTSTS_CDSTS_Pos)                   /*!< SDH_T::INTSTS: CDSTS Mask             */
+
+#define SDH_INTSTS_DAT1STS_Pos           (18)                                              /*!< SDH_T::INTSTS: DAT1STS Position        */
+#define SDH_INTSTS_DAT1STS_Msk           (0x1ul << SDH_INTSTS_DAT1STS_Pos)                 /*!< SDH_T::INTSTS: DAT1STS Mask            */
+
+#define SDH_RESP0_RESPTK0_Pos            (0)                                               /*!< SDH_T::RESP0: RESPTK0 Position         */
+#define SDH_RESP0_RESPTK0_Msk            (0xfffffffful << SDH_RESP0_RESPTK0_Pos)           /*!< SDH_T::RESP0: RESPTK0 Mask             */
+
+#define SDH_RESP1_RESPTK1_Pos            (0)                                               /*!< SDH_T::RESP1: RESPTK1 Position         */
+#define SDH_RESP1_RESPTK1_Msk            (0xfful << SDH_RESP1_RESPTK1_Pos)                 /*!< SDH_T::RESP1: RESPTK1 Mask             */
+
+#define SDH_BLEN_BLKLEN_Pos              (0)                                               /*!< SDH_T::BLEN: BLKLEN Position           */
+#define SDH_BLEN_BLKLEN_Msk              (0x7fful << SDH_BLEN_BLKLEN_Pos)                  /*!< SDH_T::BLEN: BLKLEN Mask               */
+
+#define SDH_TOUT_TOUT_Pos                (0)                                               /*!< SDH_T::TOUT: TOUT Position             */
+#define SDH_TOUT_TOUT_Msk                (0xfffffful << SDH_TOUT_TOUT_Pos)                 /*!< SDH_T::TOUT: TOUT Mask                 */
+
+/**@}*/ /* SDH_CONST */
+/**@}*/ /* end of SDH register group */
+/**@}*/ /* end of REGISTER group */
+
+
+#endif /* __SDH_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/spi_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/spi_reg.h
new file mode 100644
index 0000000000..343b6239e4
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/spi_reg.h
@@ -0,0 +1,854 @@
+/**************************************************************************//**
+ * @file     spi_reg.h
+ * @version  V1.00
+ * @brief    SPI register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __SPI_REG_H__
+#define __SPI_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+/*---------------------- Serial Peripheral Interface Controller -------------------------*/
+/**
+    @addtogroup SPI Serial Peripheral Interface Controller(SPI)
+    Memory Mapped Structure for SPI Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var SPI_T::CTL
+     * Offset: 0x00  SPI Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SPIEN     |SPI Transfer Control Enable Bit
+     * |        |          |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1
+     * |        |          |In Slave mode, this device is ready to receive data when this bit is set to 1.
+     * |        |          |0 = Transfer control Disabled.
+     * |        |          |1 = Transfer control Enabled.
+     * |        |          |Note: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0.
+     * |[1]     |RXNEG     |Receive on Negative Edge
+     * |        |          |0 = Received data input signal is latched on the rising edge of SPI bus clock.
+     * |        |          |1 = Received data input signal is latched on the falling edge of SPI bus clock.
+     * |[2]     |TXNEG     |Transmit on Negative Edge
+     * |        |          |0 = Transmitted data output signal is changed on the rising edge of SPI bus clock.
+     * |        |          |1 = Transmitted data output signal is changed on the falling edge of SPI bus clock.
+     * |[3]     |CLKPOL    |Clock Polarity
+     * |        |          |0 = SPI bus clock is idle low.
+     * |        |          |1 = SPI bus clock is idle high.
+     * |[7:4]   |SUSPITV   |Suspend Interval (Master Only)
+     * |        |          |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer
+     * |        |          |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word
+     * |        |          |The default value is 0x3
+     * |        |          |The period of the suspend interval is obtained according to the following equation.
+     * |        |          |(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle
+     * |        |          |Example:
+     * |        |          |SUSPITV = 0x0 .... 0.5 SPICLK clock cycle.
+     * |        |          |SUSPITV = 0x1 .... 1.5 SPICLK clock cycle.
+     * |        |          |.....
+     * |        |          |SUSPITV = 0xE .... 14.5 SPICLK clock cycle.
+     * |        |          |SUSPITV = 0xF .... 15.5 SPICLK clock cycle.
+     * |[12:8]  |DWIDTH    |Data Width
+     * |        |          |This field specifies how many bits can be transmitted / received in one transaction
+     * |        |          |The minimum bit length is 8 bits and can up to 32 bits.
+     * |        |          |DWIDTH = 0x08 .... 8 bits.
+     * |        |          |DWIDTH = 0x09 .... 9 bits.
+     * |        |          |.....
+     * |        |          |DWIDTH = 0x1F .... 31 bits.
+     * |        |          |DWIDTH = 0x00 .... 32 bits.
+     * |        |          |Note: For SPI0~SPI3, this bit field will decide the depth of TX/RX FIFO configuration in SPI mode
+     * |        |          |Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically in SPI0~SPI3.
+     * |[13]    |LSB       |Send LSB First
+     * |        |          |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first.
+     * |        |          |1 = The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX).
+     * |[14]    |HALFDPX   |SPI Half-duplex Transfer Enable Bit
+     * |        |          |This bit is used to select full-duplex or half-duplex for SPI transfer
+     * |        |          |The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer.
+     * |        |          |0 = SPI operates in full-duplex transfer.
+     * |        |          |1 = SPI operates in half-duplex transfer.
+     * |[15]    |RXONLY    |Receive-only Mode Enable Bit (Master Only)
+     * |        |          |This bit field is only available in Master mode
+     * |        |          |In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status.
+     * |        |          |0 = Receive-only mode Disabled.
+     * |        |          |1 = Receive-only mode Enabled.
+     * |[17]    |UNITIEN   |Unit Transfer Interrupt Enable Bit
+     * |        |          |0 = SPI unit transfer interrupt Disabled.
+     * |        |          |1 = SPI unit transfer interrupt Enabled.
+     * |[18]    |SLAVE     |Slave Mode Control
+     * |        |          |0 = Master mode.
+     * |        |          |1 = Slave mode.
+     * |[19]    |REORDER   |Byte Reorder Function Enable Bit
+     * |        |          |0 = Byte Reorder function Disabled.
+     * |        |          |1 = Byte Reorder function Enabled
+     * |        |          |A byte suspend interval will be inserted among each byte
+     * |        |          |The period of the byte suspend interval depends on the setting of SUSPITV.
+     * |        |          |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
+     * |[20]    |DATDIR    |Data Port Direction Control
+     * |        |          |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer
+     * |        |          |0 = SPI data is input direction.
+     * |        |          |1 = SPI data is output direction.
+     * @var SPI_T::CLKDIV
+     * Offset: 0x04  SPI Clock Divider Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[8:0]   |DIVIDER   |Clock Divider
+     * |        |          |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master
+     * |        |          |The frequency is obtained according to the following equation.
+     * |        |          |where
+     * |        |          |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2.
+     * |        |          |Note 1: Not supported in I2S mode.
+     * |        |          |Note 2: The time interval must be larger than or equal 5 peripheral clock cycles between releasing SPI IP software reset and setting this clock divider register.
+     * @var SPI_T::SSCTL
+     * Offset: 0x08  SPI Slave Select Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SS        |Slave Selection Control
+     * |        |          |If AUTOSS bit is cleared to 0,
+     * |        |          |0 = set the SPIx_SS line to inactive state.
+     * |        |          |1 = set the SPIx_SS line to active state.
+     * |        |          |If the AUTOSS bit is set to 1,
+     * |        |          |0 = Keep the SPIx_SS line at inactive state.
+     * |        |          |1 = SPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time
+     * |        |          |The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2]).
+     * |        |          |Note: Master mode only.
+     * |[2]     |SSACTPOL  |Slave Selection Active Polarity
+     * |        |          |This bit defines the active polarity of slave selection signal (SPIx_SS).
+     * |        |          |0 = The slave selection signal SPIx_SS is active low.
+     * |        |          |1 = The slave selection signal SPIx_SS is active high.
+     * |[3]     |AUTOSS    |Automatic Slave Selection Function Enable Bit (Master Only)
+     * |        |          |0 = Automatic slave selection function Disabled
+     * |        |          |Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0]).
+     * |        |          |1 = Automatic slave selection function Enabled.
+     * |        |          |Note: Master mode only.
+     * |[4]     |SLV3WIRE  |Slave 3-wire Mode Enable Bit
+     * |        |          |In Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPIx_CLK, SPIx_MISO and SPIx_MOSI pins.
+     * |        |          |0 = 4-wire bi-direction interface.
+     * |        |          |1 = 3-wire bi-direction interface.
+     * |        |          |Note: The value of this register equals to control register SLAVE (SPIx_I2SCTL[8]) when I2S mode is enabled.
+     * |[8]     |SLVBEIEN  |Slave Mode Bit Count Error Interrupt Enable Bit
+     * |        |          |0 = Slave mode bit count error interrupt Disabled.
+     * |        |          |1 = Slave mode bit count error interrupt Enabled.
+     * |[9]     |SLVURIEN  |Slave Mode TX Under Run Interrupt Enable Bit
+     * |        |          |0 = Slave mode TX under run interrupt Disabled.
+     * |        |          |1 = Slave mode TX under run interrupt Enabled.
+     * |[12]    |SSACTIEN  |Slave Select Active Interrupt Enable Bit
+     * |        |          |0 = Slave select active interrupt Disabled.
+     * |        |          |1 = Slave select active interrupt Enabled.
+     * |[13]    |SSINAIEN  |Slave Select Inactive Interrupt Enable Bit
+     * |        |          |0 = Slave select inactive interrupt Disabled.
+     * |        |          |1 = Slave select inactive interrupt Enabled.
+     * @var SPI_T::PDMACTL
+     * Offset: 0x0C  SPI PDMA Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |TXPDMAEN  |Transmit PDMA Enable Bit
+     * |        |          |0 = Transmit PDMA function Disabled.
+     * |        |          |1 = Transmit PDMA function Enabled.
+     * |        |          |Note: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function
+     * |        |          |User can enable TX PDMA function firstly or enable both functions simultaneously.
+     * |[1]     |RXPDMAEN  |Receive PDMA Enable Bit
+     * |        |          |0 = Receive PDMA function Disabled.
+     * |        |          |1 = Receive PDMA function Enabled.
+     * |[2]     |PDMARST   |PDMA Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0.
+     * @var SPI_T::FIFOCTL
+     * Offset: 0x10  SPI FIFO Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RXRST     |Receive Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset receive FIFO pointer and receive circuit
+     * |        |          |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
+     * |        |          |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
+     * |        |          |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not.
+     * |[1]     |TXRST     |Transmit Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset transmit FIFO pointer and transmit circuit
+     * |        |          |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
+     * |        |          |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1
+     * |        |          |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not.
+     * |        |          |Note: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state.
+     * |[2]     |RXTHIEN   |Receive FIFO Threshold Interrupt Enable Bit
+     * |        |          |0 = RX FIFO threshold interrupt Disabled.
+     * |        |          |1 = RX FIFO threshold interrupt Enabled.
+     * |[3]     |TXTHIEN   |Transmit FIFO Threshold Interrupt Enable Bit
+     * |        |          |0 = TX FIFO threshold interrupt Disabled.
+     * |        |          |1 = TX FIFO threshold interrupt Enabled.
+     * |[4]     |RXTOIEN   |Receive Time-out Interrupt Enable Bit
+     * |        |          |0 = Receive time-out interrupt Disabled.
+     * |        |          |1 = Receive time-out interrupt Enabled.
+     * |[5]     |RXOVIEN   |Receive FIFO Overrun Interrupt Enable Bit
+     * |        |          |0 = Receive FIFO overrun interrupt Disabled.
+     * |        |          |1 = Receive FIFO overrun interrupt Enabled.
+     * |[6]     |TXUFPOL   |TX Underflow Data Polarity
+     * |        |          |0 = The SPI data out is keep 0 if there is TX underflow event in Slave mode.
+     * |        |          |1 = The SPI data out is keep 1 if there is TX underflow event in Slave mode.
+     * |        |          |Note:
+     * |        |          |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.
+     * |        |          |2. This bit should be set as 0 in I2S mode.
+     * |        |          |3. When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward
+     * |        |          |Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame.
+     * |[7]     |TXUFIEN   |TX Underflow Interrupt Enable Bit
+     * |        |          |When TX underflow event occurs in Slave mode, TXUFIF (SPIx_STATUS[19]) will be set to 1
+     * |        |          |This bit is used to enable the TX underflow interrupt.
+     * |        |          |0 = Slave TX underflow interrupt Disabled.
+     * |        |          |1 = Slave TX underflow interrupt Enabled.
+     * |[8]     |RXFBCLR   |Receive FIFO Buffer Clear
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear receive FIFO pointer
+     * |        |          |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1
+     * |        |          |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
+     * |        |          |Note: The RX shift register will not be cleared.
+     * |[9]     |TXFBCLR   |Transmit FIFO Buffer Clear
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear transmit FIFO pointer
+     * |        |          |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1
+     * |        |          |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
+     * |        |          |Note: The TX shift register will not be cleared.
+     * |[10]    |SLVBERX   |RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error
+     * |        |          |0 = Uncompleted RX data will be dropped from RX FIFO when bit count error event happened in SPI Slave mode.
+     * |        |          |1 = Uncompleted RX data will be written into RX FIFO when bit count error event happened in SPI Slave mode
+     * |        |          |User can read SLVBENUM (SPIx_STATUS2[29:24]) to know that the effective bit number of uncompleted RX data when SPI slave bit count error happened.
+     * |        |          |Note: Slave mode only.
+     * |[26:24] |RXTH      |Receive FIFO Threshold
+     * |        |          |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0
+     * |        |          |For SPI0~SPI3, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length.
+     * |[30:28] |TXTH      |Transmit FIFO Threshold
+     * |        |          |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0
+     * |        |          |For SPI0~SPI3, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length.
+     * @var SPI_T::STATUS
+     * Offset: 0x14  SPI Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BUSY      |Busy Status (Read Only)
+     * |        |          |0 = SPI controller is in idle state.
+     * |        |          |1 = SPI controller is in busy state.
+     * |        |          |The following listing are the bus busy conditions:
+     * |        |          |a. SPIx_CTL[0] = 1 and TXEMPTY = 0.
+     * |        |          |b
+     * |        |          |For SPI Master mode, SPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet.
+     * |        |          |c. For SPI Master mode, SPIx_CTL[0] = 1 and RXONLY = 1.
+     * |        |          |d.
+     * |        |          |For SPI Slave mode, the SPIx_CTL[0] = 1 and there is serial clock input into the SPI core logic when slave select is active.
+     * |        |          |e.
+     * |        |          |For SPI Slave mode, the SPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
+     * |        |          |Note: By applications, this SPI busy flag should be used with other status registers in SPIx_STATUS such as TXCNT, RXCNT, TXTHIF, TXFULL, TXEMPTY, RXTHIF, RXFULL, RXEMPTY, and UNITIF
+     * |        |          |Therefore the SPI transfer done events of TX/RX operations can be obtained at correct timing point.
+     * |[1]     |UNITIF    |Unit Transfer Interrupt Flag
+     * |        |          |0 = No transaction has been finished since this bit was cleared to 0.
+     * |        |          |1 = SPI controller has finished one unit transfer.
+     * |        |          |Note: This bit will be cleared by writing 1 to it.
+     * |[2]     |SSACTIF   |Slave Select Active Interrupt Flag
+     * |        |          |0 = Slave select active interrupt was cleared or not occurred.
+     * |        |          |1 = Slave select active interrupt event occurred.
+     * |        |          |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
+     * |[3]     |SSINAIF   |Slave Select Inactive Interrupt Flag
+     * |        |          |0 = Slave select inactive interrupt was cleared or not occurred.
+     * |        |          |1 = Slave select inactive interrupt event occurred.
+     * |        |          |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
+     * |[4]     |SSLINE    |Slave Select Line Bus Status (Read Only)
+     * |        |          |0 = The slave select line status is 0.
+     * |        |          |1 = The slave select line status is 1.
+     * |        |          |Note: This bit is only available in Slave mode
+     * |        |          |If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
+     * |[6]     |SLVBEIF   |Slave Mode Bit Count Error Interrupt Flag
+     * |        |          |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.
+     * |        |          |0 = No Slave mode bit count error event.
+     * |        |          |1 = Slave mode bit count error event occurs.
+     * |        |          |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state
+     * |        |          |This bit will be cleared by writing 1 to it.
+     * |[7]     |SLVURIF   |Slave Mode TX Under Run Interrupt Flag
+     * |        |          |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
+     * |        |          |0 = No Slave TX under run event.
+     * |        |          |1 = Slave TX under run event occurs.
+     * |        |          |Note: This bit will be cleared by writing 1 to it.
+     * |[8]     |RXEMPTY   |Receive FIFO Buffer Empty Indicator (Read Only)
+     * |        |          |0 = Receive FIFO buffer is not empty.
+     * |        |          |1 = Receive FIFO buffer is empty.
+     * |[9]     |RXFULL    |Receive FIFO Buffer Full Indicator (Read Only)
+     * |        |          |0 = Receive FIFO buffer is not full.
+     * |        |          |1 = Receive FIFO buffer is full.
+     * |[10]    |RXTHIF    |Receive FIFO Threshold Interrupt Flag (Read Only)
+     * |        |          |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH.
+     * |        |          |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
+     * |[11]    |RXOVIF    |Receive FIFO Overrun Interrupt Flag
+     * |        |          |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
+     * |        |          |0 = No FIFO is overrun.
+     * |        |          |1 = Receive FIFO is overrun.
+     * |        |          |Note: This bit will be cleared by writing 1 to it.
+     * |[12]    |RXTOIF    |Receive Time-out Interrupt Flag
+     * |        |          |0 = No receive FIFO time-out event.
+     * |        |          |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode
+     * |        |          |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
+     * |        |          |Note: This bit will be cleared by writing 1 to it.
+     * |[15]    |SPIENSTS  |SPI Enable Status (Read Only)
+     * |        |          |0 = The SPI controller is disabled.
+     * |        |          |1 = The SPI controller is enabled.
+     * |        |          |Note: The SPI peripheral clock is asynchronous with the system clock
+     * |        |          |In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
+     * |[16]    |TXEMPTY   |Transmit FIFO Buffer Empty Indicator (Read Only)
+     * |        |          |0 = Transmit FIFO buffer is not empty.
+     * |        |          |1 = Transmit FIFO buffer is empty.
+     * |[17]    |TXFULL    |Transmit FIFO Buffer Full Indicator (Read Only)
+     * |        |          |0 = Transmit FIFO buffer is not full.
+     * |        |          |1 = Transmit FIFO buffer is full.
+     * |[18]    |TXTHIF    |Transmit FIFO Threshold Interrupt Flag (Read Only)
+     * |        |          |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
+     * |        |          |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
+     * |[19]    |TXUFIF    |TX Underflow Interrupt Flag
+     * |        |          |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
+     * |        |          |0 = No effect.
+     * |        |          |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active.
+     * |        |          |Note 1: This bit will be cleared by writing 1 to it.
+     * |        |          |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
+     * |[23]    |TXRXRST   |TX or RX Reset Status (Read Only)
+     * |        |          |0 = The reset function of TXRST or RXRST is done.
+     * |        |          |1 = Doing the reset function of TXRST or RXRST.
+     * |        |          |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles
+     * |        |          |User can check the status of this bit to monitor the reset function is doing or done.
+     * |[27:24] |RXCNT     |Receive FIFO Data Count (Read Only)
+     * |        |          |This bit field indicates the valid data count of receive FIFO buffer.
+     * |[31:28] |TXCNT     |Transmit FIFO Data Count (Read Only)
+     * |        |          |This bit field indicates the valid data count of transmit FIFO buffer.
+     * @var SPI_T::STATUS2
+     * Offset: 0x18  SPI Status2 Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[29:24] |SLVBENUM  |Effective Bit Number of Uncompleted RX Data
+     * |        |          |This status register indicates that effective bit number of uncompleted RX data when SLVBERX (SPIx_FIFOCTL[10]) is enabled and RX bit count error event happen in SPI Slave mode
+     * |        |          |This status register will be fixed to 0x0 when SLVBERX (SPIx_FIFOCTL[10]) is disabled.
+     * |        |          |Note 1: This register will be cleared to 0x0 when user writes 0x1 to SLVBEIF (SPIx_STATUS[6]).
+     * |        |          |Note 2: Slave mode only.
+     * @var SPI_T::TX
+     * Offset: 0x20  SPI Data Transmit Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |TX        |Data Transmit Register
+     * |        |          |The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers
+     * |        |          |The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode.
+     * |        |          |In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted
+     * |        |          |If DWIDTH is set to 0x00 , the SPI controller will perform a 32-bit transfer.
+     * |        |          |In I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0]
+     * |        |          |If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section
+     * |        |          |Note: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register.
+     * @var SPI_T::RX
+     * Offset: 0x30  SPI Data Receive Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |RX        |Data Receive Register (Read Only)
+     * |        |          |There are 4-level FIFO buffers in this controller.
+     * |        |          |The data receive register holds the data received from SPI data input pin.
+     * |        |          |If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register.
+     * @var SPI_T::I2SCTL
+     * Offset: 0x60  I2S Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |I2SEN     |I2S Controller Enable Bit
+     * |        |          |0 = Disabled I2S mode.
+     * |        |          |1 = Enabled I2S mode.
+     * |        |          |Note:
+     * |        |          |1. If enable this bit, I2Sx_BCLK will start to output in Master mode.
+     * |        |          |2
+     * |        |          |Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0.
+     * |[1]     |TXEN      |Transmit Enable Bit
+     * |        |          |0 = Data transmit Disabled.
+     * |        |          |1 = Data transmit Enabled.
+     * |[2]     |RXEN      |Receive Enable Bit
+     * |        |          |0 = Data receive Disabled.
+     * |        |          |1 = Data receive Enabled.
+     * |[3]     |MUTE      |Transmit Mute Enable Bit
+     * |        |          |0 = Transmit data is shifted from buffer.
+     * |        |          |1 = Transmit channel zero.
+     * |[5:4]   |WDWIDTH   |Word Width
+     * |        |          |00 = data size is 8-bit.
+     * |        |          |01 = data size is 16-bit.
+     * |        |          |10 = data size is 24-bit.
+     * |        |          |11 = data size is 32-bit.
+     * |[6]     |MONO      |Monaural Data
+     * |        |          |0 = Data is stereo format.
+     * |        |          |1 = Data is monaural format.
+     * |[7]     |ORDER     |Stereo Data Order in FIFO
+     * |        |          |0 = Left channel data at high byte.
+     * |        |          |1 = Left channel data at low byte.
+     * |[8]     |SLAVE     |Slave Mode
+     * |        |          |I2S can operate as master or slave
+     * |        |          |For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from NuMicro M2354 series to audio CODEC chip
+     * |        |          |In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip.
+     * |        |          |0 = Master mode.
+     * |        |          |1 = Slave mode.
+     * |[15]    |MCLKEN    |Master Clock Enable Bit
+     * |        |          |If MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices.
+     * |        |          |0 = Master clock Disabled.
+     * |        |          |1 = Master clock Enabled.
+     * |[16]    |RZCEN     |Right Channel Zero Cross Detection Enable Bit
+     * |        |          |If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1
+     * |        |          |This function is only available in transmit operation.
+     * |        |          |0 = Right channel zero cross detection Disabled.
+     * |        |          |1 = Right channel zero cross detection Enabled.
+     * |[17]    |LZCEN     |Left Channel Zero Cross Detection Enable Bit
+     * |        |          |If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1
+     * |        |          |This function is only available in transmit operation.
+     * |        |          |0 = Left channel zero cross detection Disabled.
+     * |        |          |1 = Left channel zero cross detection Enabled.
+     * |[23]    |RXLCH     |Receive Left Channel Enable Bit
+     * |        |          |When monaural format is selected (MONO = 1), I2S controller will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1.
+     * |        |          |0 = Receive right channel data in Mono mode.
+     * |        |          |1 = Receive left channel data in Mono mode.
+     * |[24]    |RZCIEN    |Right Channel Zero Cross Interrupt Enable Bit
+     * |        |          |Interrupt occurs if this bit is set to 1 and right channel zero cross event occurs.
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[25]    |LZCIEN    |Left Channel Zero Cross Interrupt Enable Bit
+     * |        |          |Interrupt occurs if this bit is set to 1 and left channel zero cross event occurs.
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[29:28] |FORMAT    |Data Format Selection
+     * |        |          |00 = I2S data format.
+     * |        |          |01 = MSB justified data format.
+     * |        |          |10 = PCM mode A.
+     * |        |          |11 = PCM mode B.
+     * |[31]    |SLVERRIEN |Bit Clock Loss Interrupt Enable Bit for Slave Mode
+     * |        |          |Interrupt occurs if this bit is set to 1 and bit clock loss event occurs.
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * @var SPI_T::I2SCLK
+     * Offset: 0x64  I2S Clock Divider Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[6:0]   |MCLKDIV   |Master Clock Divider
+     * |        |          |If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices.
+     * |        |          |The frequency of master clock, F_MCLK, is determined by the following expressions:
+     * |        |          |If MCLKDIV >= 1, F_MCLK = F_I2SCLK/(2x(MCLKDIV)).
+     * |        |          |If MCLKDIV = 0, F_MCLK = F_I2SCLK.
+     * |        |          |where
+     * |        |          |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.
+     * |        |          |F_I2SCLK is the frequency of I2S peripheral clock.
+     * |        |          |In general, the master clock rate is 256 times sampling clock rate.
+     * |[17:8]  |BCLKDIV   |Bit Clock Divider
+     * |        |          |The I2S controller will generate bit clock in Master mode.
+     * |        |          |The clock frequency of bit clock, F_BCLK, is determined by the following expression:
+     * |        |          |F_BCLK = F_I2SCLK/(2x(BCLKDIV + 1)),
+     * |        |          |where
+     * |        |          |F_I2SCLK is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.
+     * |        |          |In I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by F_I2SCLK/(BCLKDIV/2 + 1).
+     * |        |          |The peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock.
+     * |[24]    |I2SMODE   |I2S Clock Divider Number Selection for I2S Mode and SPI Mode
+     * |        |          |User sets I2SMODE to set frequency of peripheral clock of I2S mode or SPI mode when BCLKDIV (SPIx_I2SCLK[17:8]) or DIVIDER (SPIx_CLKDIV[8:0]) is set.
+     * |        |          |User needs to set I2SMODE before I2SEN (SPIx_I2SCTL[0]) or SPIEN (SPIx_CTL[0]) is enabled.
+     * |        |          |0 = The frequency of peripheral clock is set to SPI mode.
+     * |        |          |1 = The frequency of peripheral clock is set to I2S mode.
+     * |[25]    |I2SSLAVE  |I2S Clock Divider Number Selection for I2S Slave Mode and I2S Master Mode
+     * |        |          |User sets I2SSLAVE to set frequency of peripheral clock of I2S master mode and I2S slave mode when BCLKDIV (SPIx_I2SCLK[17:8]) is set.
+     * |        |          |I2SSLAVE needs to set before I2SEN (SPIx_I2SCTL[0]) is enabled.
+     * |        |          |0 = The frequency of peripheral clock is set to I2S Master mode.
+     * |        |          |1 = The frequency of peripheral clock is set to I2S Slave mode.
+     * @var SPI_T::I2SSTS
+     * Offset: 0x68  I2S Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[4]     |RIGHT     |Right Channel (Read Only)
+     * |        |          |This bit indicates the current transmit data is belong to which channel.
+     * |        |          |0 = Left channel.
+     * |        |          |1 = Right channel.
+     * |[8]     |RXEMPTY   |Receive FIFO Buffer Empty Indicator (Read Only)
+     * |        |          |0 = Receive FIFO buffer is not empty.
+     * |        |          |1 = Receive FIFO buffer is empty.
+     * |[9]     |RXFULL    |Receive FIFO Buffer Full Indicator (Read Only)
+     * |        |          |0 = Receive FIFO buffer is not full.
+     * |        |          |1 = Receive FIFO buffer is full.
+     * |[10]    |RXTHIF    |Receive FIFO Threshold Interrupt Flag (Read Only)
+     * |        |          |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH.
+     * |        |          |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
+     * |        |          |Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request.
+     * |[11]    |RXOVIF    |Receive FIFO Overrun Interrupt Flag
+     * |        |          |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
+     * |        |          |Note: This bit will be cleared by writing 1 to it.
+     * |[12]    |RXTOIF    |Receive Time-out Interrupt Flag
+     * |        |          |0 = No receive FIFO time-out event.
+     * |        |          |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode
+     * |        |          |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
+     * |        |          |Note: This bit will be cleared by writing 1 to it.
+     * |[15]    |I2SENSTS  |I2S Enable Status (Read Only)
+     * |        |          |0 = The SPI/I2S control logic is disabled.
+     * |        |          |1 = The SPI/I2S control logic is enabled.
+     * |        |          |Note: The SPI peripheral clock is asynchronous with the system clock
+     * |        |          |In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user.
+     * |[16]    |TXEMPTY   |Transmit FIFO Buffer Empty Indicator (Read Only)
+     * |        |          |0 = Transmit FIFO buffer is not empty.
+     * |        |          |1 = Transmit FIFO buffer is empty.
+     * |[17]    |TXFULL    |Transmit FIFO Buffer Full Indicator (Read Only)
+     * |        |          |0 = Transmit FIFO buffer is not full.
+     * |        |          |1 = Transmit FIFO buffer is full.
+     * |[18]    |TXTHIF    |Transmit FIFO Threshold Interrupt Flag (Read Only)
+     * |        |          |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
+     * |        |          |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
+     * |        |          |Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request.
+     * |[19]    |TXUFIF    |Transmit FIFO Underflow Interrupt Flag
+     * |        |          |When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1.
+     * |        |          |Note: This bit will be cleared by writing 1 to it.
+     * |[20]    |RZCIF     |Right Channel Zero Cross Interrupt Flag
+     * |        |          |0 = No zero cross event occurred on right channel.
+     * |        |          |1 = Zero cross event occurred on right channel.
+     * |[21]    |LZCIF     |Left Channel Zero Cross Interrupt Flag
+     * |        |          |0 = No zero cross event occurred on left channel.
+     * |        |          |1 = Zero cross event occurred on left channel.
+     * |[22]    |SLVERRIF  |Bit Clock Loss Interrupt Flag for Slave Mode
+     * |        |          |0 = No bit clock loss event occurred.
+     * |        |          |1 = Bit clock loss event occurred.
+     * |        |          |Note: This bit will be cleared by writing 1 to it.
+     * |[23]    |TXRXRST   |TX or RX Reset Status (Read Only)
+     * |        |          |0 = The reset function of TXRST or RXRST is done.
+     * |        |          |1 = Doing the reset function of TXRST or RXRST.
+     * |        |          |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles
+     * |        |          |User can check the status of this bit to monitor the reset function is doing or done.
+     * |[26:24] |RXCNT     |Receive FIFO Data Count (Read Only)
+     * |        |          |This bit field indicates the valid data count of receive FIFO buffer.
+     * |[30:28] |TXCNT     |Transmit FIFO Data Count (Read Only)
+     * |        |          |This bit field indicates the valid data count of transmit FIFO buffer.
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] SPI Control Register                                             */
+    __IO uint32_t CLKDIV;                /*!< [0x0004] SPI Clock Divider Register                                       */
+    __IO uint32_t SSCTL;                 /*!< [0x0008] SPI Slave Select Control Register                                */
+    __IO uint32_t PDMACTL;               /*!< [0x000c] SPI PDMA Control Register                                        */
+    __IO uint32_t FIFOCTL;               /*!< [0x0010] SPI FIFO Control Register                                        */
+    __IO uint32_t STATUS;                /*!< [0x0014] SPI Status Register                                              */
+    __I  uint32_t STATUS2;               /*!< [0x0018] SPI Status2 Register                                             */
+    __I  uint32_t RESERVE0[1];
+    __O  uint32_t TX;                    /*!< [0x0020] SPI Data Transmit Register                                       */
+    __I  uint32_t RESERVE1[3];
+    __I  uint32_t RX;                    /*!< [0x0030] SPI Data Receive Register                                        */
+    __I  uint32_t RESERVE2[11];
+    __IO uint32_t I2SCTL;                /*!< [0x0060] I2S Control Register                                             */
+    __IO uint32_t I2SCLK;                /*!< [0x0064] I2S Clock Divider Control Register                               */
+    __IO uint32_t I2SSTS;                /*!< [0x0068] I2S Status Register                                              */
+
+} SPI_T;
+
+/**
+    @addtogroup SPI_CONST SPI Bit Field Definition
+    Constant Definitions for SPI Controller
+  @{
+*/
+
+#define SPI_CTL_SPIEN_Pos                (0)                                               /*!< SPI_T::CTL: SPIEN Position             */
+#define SPI_CTL_SPIEN_Msk                (0x1ul << SPI_CTL_SPIEN_Pos)                      /*!< SPI_T::CTL: SPIEN Mask                 */
+
+#define SPI_CTL_RXNEG_Pos                (1)                                               /*!< SPI_T::CTL: RXNEG Position             */
+#define SPI_CTL_RXNEG_Msk                (0x1ul << SPI_CTL_RXNEG_Pos)                      /*!< SPI_T::CTL: RXNEG Mask                 */
+
+#define SPI_CTL_TXNEG_Pos                (2)                                               /*!< SPI_T::CTL: TXNEG Position             */
+#define SPI_CTL_TXNEG_Msk                (0x1ul << SPI_CTL_TXNEG_Pos)                      /*!< SPI_T::CTL: TXNEG Mask                 */
+
+#define SPI_CTL_CLKPOL_Pos               (3)                                               /*!< SPI_T::CTL: CLKPOL Position            */
+#define SPI_CTL_CLKPOL_Msk               (0x1ul << SPI_CTL_CLKPOL_Pos)                     /*!< SPI_T::CTL: CLKPOL Mask                */
+
+#define SPI_CTL_SUSPITV_Pos              (4)                                               /*!< SPI_T::CTL: SUSPITV Position           */
+#define SPI_CTL_SUSPITV_Msk              (0xful << SPI_CTL_SUSPITV_Pos)                    /*!< SPI_T::CTL: SUSPITV Mask               */
+
+#define SPI_CTL_DWIDTH_Pos               (8)                                               /*!< SPI_T::CTL: DWIDTH Position            */
+#define SPI_CTL_DWIDTH_Msk               (0x1ful << SPI_CTL_DWIDTH_Pos)                    /*!< SPI_T::CTL: DWIDTH Mask                */
+
+#define SPI_CTL_LSB_Pos                  (13)                                              /*!< SPI_T::CTL: LSB Position               */
+#define SPI_CTL_LSB_Msk                  (0x1ul << SPI_CTL_LSB_Pos)                        /*!< SPI_T::CTL: LSB Mask                   */
+
+#define SPI_CTL_HALFDPX_Pos              (14)                                              /*!< SPI_T::CTL: HALFDPX Position           */
+#define SPI_CTL_HALFDPX_Msk              (0x1ul << SPI_CTL_HALFDPX_Pos)                    /*!< SPI_T::CTL: HALFDPX Mask               */
+
+#define SPI_CTL_RXONLY_Pos               (15)                                              /*!< SPI_T::CTL: RXONLY Position            */
+#define SPI_CTL_RXONLY_Msk               (0x1ul << SPI_CTL_RXONLY_Pos)                     /*!< SPI_T::CTL: RXONLY Mask                */
+
+#define SPI_CTL_UNITIEN_Pos              (17)                                              /*!< SPI_T::CTL: UNITIEN Position           */
+#define SPI_CTL_UNITIEN_Msk              (0x1ul << SPI_CTL_UNITIEN_Pos)                    /*!< SPI_T::CTL: UNITIEN Mask               */
+
+#define SPI_CTL_SLAVE_Pos                (18)                                              /*!< SPI_T::CTL: SLAVE Position             */
+#define SPI_CTL_SLAVE_Msk                (0x1ul << SPI_CTL_SLAVE_Pos)                      /*!< SPI_T::CTL: SLAVE Mask                 */
+
+#define SPI_CTL_REORDER_Pos              (19)                                              /*!< SPI_T::CTL: REORDER Position           */
+#define SPI_CTL_REORDER_Msk              (0x1ul << SPI_CTL_REORDER_Pos)                    /*!< SPI_T::CTL: REORDER Mask               */
+
+#define SPI_CTL_DATDIR_Pos               (20)                                              /*!< SPI_T::CTL: DATDIR Position            */
+#define SPI_CTL_DATDIR_Msk               (0x1ul << SPI_CTL_DATDIR_Pos)                     /*!< SPI_T::CTL: DATDIR Mask                */
+
+#define SPI_CLKDIV_DIVIDER_Pos           (0)                                               /*!< SPI_T::CLKDIV: DIVIDER Position        */
+#define SPI_CLKDIV_DIVIDER_Msk           (0x1fful << SPI_CLKDIV_DIVIDER_Pos)               /*!< SPI_T::CLKDIV: DIVIDER Mask            */
+
+#define SPI_SSCTL_SS_Pos                 (0)                                               /*!< SPI_T::SSCTL: SS Position              */
+#define SPI_SSCTL_SS_Msk                 (0x1ul << SPI_SSCTL_SS_Pos)                       /*!< SPI_T::SSCTL: SS Mask                  */
+
+#define SPI_SSCTL_SSACTPOL_Pos           (2)                                               /*!< SPI_T::SSCTL: SSACTPOL Position        */
+#define SPI_SSCTL_SSACTPOL_Msk           (0x1ul << SPI_SSCTL_SSACTPOL_Pos)                 /*!< SPI_T::SSCTL: SSACTPOL Mask            */
+
+#define SPI_SSCTL_AUTOSS_Pos             (3)                                               /*!< SPI_T::SSCTL: AUTOSS Position          */
+#define SPI_SSCTL_AUTOSS_Msk             (0x1ul << SPI_SSCTL_AUTOSS_Pos)                   /*!< SPI_T::SSCTL: AUTOSS Mask              */
+
+#define SPI_SSCTL_SLV3WIRE_Pos           (4)                                               /*!< SPI_T::SSCTL: SLV3WIRE Position        */
+#define SPI_SSCTL_SLV3WIRE_Msk           (0x1ul << SPI_SSCTL_SLV3WIRE_Pos)                 /*!< SPI_T::SSCTL: SLV3WIRE Mask            */
+
+#define SPI_SSCTL_SLVBEIEN_Pos           (8)                                               /*!< SPI_T::SSCTL: SLVBEIEN Position        */
+#define SPI_SSCTL_SLVBEIEN_Msk           (0x1ul << SPI_SSCTL_SLVBEIEN_Pos)                 /*!< SPI_T::SSCTL: SLVBEIEN Mask            */
+
+#define SPI_SSCTL_SLVURIEN_Pos           (9)                                               /*!< SPI_T::SSCTL: SLVURIEN Position        */
+#define SPI_SSCTL_SLVURIEN_Msk           (0x1ul << SPI_SSCTL_SLVURIEN_Pos)                 /*!< SPI_T::SSCTL: SLVURIEN Mask            */
+
+#define SPI_SSCTL_SSACTIEN_Pos           (12)                                              /*!< SPI_T::SSCTL: SSACTIEN Position        */
+#define SPI_SSCTL_SSACTIEN_Msk           (0x1ul << SPI_SSCTL_SSACTIEN_Pos)                 /*!< SPI_T::SSCTL: SSACTIEN Mask            */
+
+#define SPI_SSCTL_SSINAIEN_Pos           (13)                                              /*!< SPI_T::SSCTL: SSINAIEN Position        */
+#define SPI_SSCTL_SSINAIEN_Msk           (0x1ul << SPI_SSCTL_SSINAIEN_Pos)                 /*!< SPI_T::SSCTL: SSINAIEN Mask            */
+
+#define SPI_PDMACTL_TXPDMAEN_Pos         (0)                                               /*!< SPI_T::PDMACTL: TXPDMAEN Position      */
+#define SPI_PDMACTL_TXPDMAEN_Msk         (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos)               /*!< SPI_T::PDMACTL: TXPDMAEN Mask          */
+
+#define SPI_PDMACTL_RXPDMAEN_Pos         (1)                                               /*!< SPI_T::PDMACTL: RXPDMAEN Position      */
+#define SPI_PDMACTL_RXPDMAEN_Msk         (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos)               /*!< SPI_T::PDMACTL: RXPDMAEN Mask          */
+
+#define SPI_PDMACTL_PDMARST_Pos          (2)                                               /*!< SPI_T::PDMACTL: PDMARST Position       */
+#define SPI_PDMACTL_PDMARST_Msk          (0x1ul << SPI_PDMACTL_PDMARST_Pos)                /*!< SPI_T::PDMACTL: PDMARST Mask           */
+
+#define SPI_FIFOCTL_RXRST_Pos            (0)                                               /*!< SPI_T::FIFOCTL: RXRST Position         */
+#define SPI_FIFOCTL_RXRST_Msk            (0x1ul << SPI_FIFOCTL_RXRST_Pos)                  /*!< SPI_T::FIFOCTL: RXRST Mask             */
+
+#define SPI_FIFOCTL_TXRST_Pos            (1)                                               /*!< SPI_T::FIFOCTL: TXRST Position         */
+#define SPI_FIFOCTL_TXRST_Msk            (0x1ul << SPI_FIFOCTL_TXRST_Pos)                  /*!< SPI_T::FIFOCTL: TXRST Mask             */
+
+#define SPI_FIFOCTL_RXTHIEN_Pos          (2)                                               /*!< SPI_T::FIFOCTL: RXTHIEN Position       */
+#define SPI_FIFOCTL_RXTHIEN_Msk          (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos)                /*!< SPI_T::FIFOCTL: RXTHIEN Mask           */
+
+#define SPI_FIFOCTL_TXTHIEN_Pos          (3)                                               /*!< SPI_T::FIFOCTL: TXTHIEN Position       */
+#define SPI_FIFOCTL_TXTHIEN_Msk          (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos)                /*!< SPI_T::FIFOCTL: TXTHIEN Mask           */
+
+#define SPI_FIFOCTL_RXTOIEN_Pos          (4)                                               /*!< SPI_T::FIFOCTL: RXTOIEN Position       */
+#define SPI_FIFOCTL_RXTOIEN_Msk          (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos)                /*!< SPI_T::FIFOCTL: RXTOIEN Mask           */
+
+#define SPI_FIFOCTL_RXOVIEN_Pos          (5)                                               /*!< SPI_T::FIFOCTL: RXOVIEN Position       */
+#define SPI_FIFOCTL_RXOVIEN_Msk          (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos)                /*!< SPI_T::FIFOCTL: RXOVIEN Mask           */
+
+#define SPI_FIFOCTL_TXUFPOL_Pos          (6)                                               /*!< SPI_T::FIFOCTL: TXUFPOL Position       */
+#define SPI_FIFOCTL_TXUFPOL_Msk          (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos)                /*!< SPI_T::FIFOCTL: TXUFPOL Mask           */
+
+#define SPI_FIFOCTL_TXUFIEN_Pos          (7)                                               /*!< SPI_T::FIFOCTL: TXUFIEN Position       */
+#define SPI_FIFOCTL_TXUFIEN_Msk          (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos)                /*!< SPI_T::FIFOCTL: TXUFIEN Mask           */
+
+#define SPI_FIFOCTL_RXFBCLR_Pos          (8)                                               /*!< SPI_T::FIFOCTL: RXFBCLR Position       */
+#define SPI_FIFOCTL_RXFBCLR_Msk          (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos)                /*!< SPI_T::FIFOCTL: RXFBCLR Mask           */
+
+#define SPI_FIFOCTL_TXFBCLR_Pos          (9)                                               /*!< SPI_T::FIFOCTL: TXFBCLR Position       */
+#define SPI_FIFOCTL_TXFBCLR_Msk          (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos)                /*!< SPI_T::FIFOCTL: TXFBCLR Mask           */
+
+#define SPI_FIFOCTL_SLVBERX_Pos          (10)                                              /*!< SPI_T::FIFOCTL: SLVBERX Position       */
+#define SPI_FIFOCTL_SLVBERX_Msk          (0x1ul << SPI_FIFOCTL_SLVBERX_Pos)                /*!< SPI_T::FIFOCTL: SLVBERX Mask           */
+
+#define SPI_FIFOCTL_RXTH_Pos             (24)                                              /*!< SPI_T::FIFOCTL: RXTH Position          */
+#define SPI_FIFOCTL_RXTH_Msk             (0x7ul << SPI_FIFOCTL_RXTH_Pos)                   /*!< SPI_T::FIFOCTL: RXTH Mask              */
+
+#define SPI_FIFOCTL_TXTH_Pos             (28)                                              /*!< SPI_T::FIFOCTL: TXTH Position          */
+#define SPI_FIFOCTL_TXTH_Msk             (0x7ul << SPI_FIFOCTL_TXTH_Pos)                   /*!< SPI_T::FIFOCTL: TXTH Mask              */
+
+#define SPI_STATUS_BUSY_Pos              (0)                                               /*!< SPI_T::STATUS: BUSY Position           */
+#define SPI_STATUS_BUSY_Msk              (0x1ul << SPI_STATUS_BUSY_Pos)                    /*!< SPI_T::STATUS: BUSY Mask               */
+
+#define SPI_STATUS_UNITIF_Pos            (1)                                               /*!< SPI_T::STATUS: UNITIF Position         */
+#define SPI_STATUS_UNITIF_Msk            (0x1ul << SPI_STATUS_UNITIF_Pos)                  /*!< SPI_T::STATUS: UNITIF Mask             */
+
+#define SPI_STATUS_SSACTIF_Pos           (2)                                               /*!< SPI_T::STATUS: SSACTIF Position        */
+#define SPI_STATUS_SSACTIF_Msk           (0x1ul << SPI_STATUS_SSACTIF_Pos)                 /*!< SPI_T::STATUS: SSACTIF Mask            */
+
+#define SPI_STATUS_SSINAIF_Pos           (3)                                               /*!< SPI_T::STATUS: SSINAIF Position        */
+#define SPI_STATUS_SSINAIF_Msk           (0x1ul << SPI_STATUS_SSINAIF_Pos)                 /*!< SPI_T::STATUS: SSINAIF Mask            */
+
+#define SPI_STATUS_SSLINE_Pos            (4)                                               /*!< SPI_T::STATUS: SSLINE Position         */
+#define SPI_STATUS_SSLINE_Msk            (0x1ul << SPI_STATUS_SSLINE_Pos)                  /*!< SPI_T::STATUS: SSLINE Mask             */
+
+#define SPI_STATUS_SLVBEIF_Pos           (6)                                               /*!< SPI_T::STATUS: SLVBEIF Position        */
+#define SPI_STATUS_SLVBEIF_Msk           (0x1ul << SPI_STATUS_SLVBEIF_Pos)                 /*!< SPI_T::STATUS: SLVBEIF Mask            */
+
+#define SPI_STATUS_SLVURIF_Pos           (7)                                               /*!< SPI_T::STATUS: SLVURIF Position        */
+#define SPI_STATUS_SLVURIF_Msk           (0x1ul << SPI_STATUS_SLVURIF_Pos)                 /*!< SPI_T::STATUS: SLVURIF Mask            */
+
+#define SPI_STATUS_RXEMPTY_Pos           (8)                                               /*!< SPI_T::STATUS: RXEMPTY Position        */
+#define SPI_STATUS_RXEMPTY_Msk           (0x1ul << SPI_STATUS_RXEMPTY_Pos)                 /*!< SPI_T::STATUS: RXEMPTY Mask            */
+
+#define SPI_STATUS_RXFULL_Pos            (9)                                               /*!< SPI_T::STATUS: RXFULL Position         */
+#define SPI_STATUS_RXFULL_Msk            (0x1ul << SPI_STATUS_RXFULL_Pos)                  /*!< SPI_T::STATUS: RXFULL Mask             */
+
+#define SPI_STATUS_RXTHIF_Pos            (10)                                              /*!< SPI_T::STATUS: RXTHIF Position         */
+#define SPI_STATUS_RXTHIF_Msk            (0x1ul << SPI_STATUS_RXTHIF_Pos)                  /*!< SPI_T::STATUS: RXTHIF Mask             */
+
+#define SPI_STATUS_RXOVIF_Pos            (11)                                              /*!< SPI_T::STATUS: RXOVIF Position         */
+#define SPI_STATUS_RXOVIF_Msk            (0x1ul << SPI_STATUS_RXOVIF_Pos)                  /*!< SPI_T::STATUS: RXOVIF Mask             */
+
+#define SPI_STATUS_RXTOIF_Pos            (12)                                              /*!< SPI_T::STATUS: RXTOIF Position         */
+#define SPI_STATUS_RXTOIF_Msk            (0x1ul << SPI_STATUS_RXTOIF_Pos)                  /*!< SPI_T::STATUS: RXTOIF Mask             */
+
+#define SPI_STATUS_SPIENSTS_Pos          (15)                                              /*!< SPI_T::STATUS: SPIENSTS Position       */
+#define SPI_STATUS_SPIENSTS_Msk          (0x1ul << SPI_STATUS_SPIENSTS_Pos)                /*!< SPI_T::STATUS: SPIENSTS Mask           */
+
+#define SPI_STATUS_TXEMPTY_Pos           (16)                                              /*!< SPI_T::STATUS: TXEMPTY Position        */
+#define SPI_STATUS_TXEMPTY_Msk           (0x1ul << SPI_STATUS_TXEMPTY_Pos)                 /*!< SPI_T::STATUS: TXEMPTY Mask            */
+
+#define SPI_STATUS_TXFULL_Pos            (17)                                              /*!< SPI_T::STATUS: TXFULL Position         */
+#define SPI_STATUS_TXFULL_Msk            (0x1ul << SPI_STATUS_TXFULL_Pos)                  /*!< SPI_T::STATUS: TXFULL Mask             */
+
+#define SPI_STATUS_TXTHIF_Pos            (18)                                              /*!< SPI_T::STATUS: TXTHIF Position         */
+#define SPI_STATUS_TXTHIF_Msk            (0x1ul << SPI_STATUS_TXTHIF_Pos)                  /*!< SPI_T::STATUS: TXTHIF Mask             */
+
+#define SPI_STATUS_TXUFIF_Pos            (19)                                              /*!< SPI_T::STATUS: TXUFIF Position         */
+#define SPI_STATUS_TXUFIF_Msk            (0x1ul << SPI_STATUS_TXUFIF_Pos)                  /*!< SPI_T::STATUS: TXUFIF Mask             */
+
+#define SPI_STATUS_TXRXRST_Pos           (23)                                              /*!< SPI_T::STATUS: TXRXRST Position        */
+#define SPI_STATUS_TXRXRST_Msk           (0x1ul << SPI_STATUS_TXRXRST_Pos)                 /*!< SPI_T::STATUS: TXRXRST Mask            */
+
+#define SPI_STATUS_RXCNT_Pos             (24)                                              /*!< SPI_T::STATUS: RXCNT Position          */
+#define SPI_STATUS_RXCNT_Msk             (0xful << SPI_STATUS_RXCNT_Pos)                   /*!< SPI_T::STATUS: RXCNT Mask              */
+
+#define SPI_STATUS_TXCNT_Pos             (28)                                              /*!< SPI_T::STATUS: TXCNT Position          */
+#define SPI_STATUS_TXCNT_Msk             (0xful << SPI_STATUS_TXCNT_Pos)                   /*!< SPI_T::STATUS: TXCNT Mask              */
+
+#define SPI_STATUS2_SLVBENUM_Pos         (24)                                              /*!< SPI_T::STATUS2: SLVBENUM Position      */
+#define SPI_STATUS2_SLVBENUM_Msk         (0x3ful << SPI_STATUS2_SLVBENUM_Pos)              /*!< SPI_T::STATUS2: SLVBENUM Mask          */
+
+#define SPI_TX_TX_Pos                    (0)                                               /*!< SPI_T::TX: TX Position                 */
+#define SPI_TX_TX_Msk                    (0xfffffffful << SPI_TX_TX_Pos)                   /*!< SPI_T::TX: TX Mask                     */
+
+#define SPI_RX_RX_Pos                    (0)                                               /*!< SPI_T::RX: RX Position                 */
+#define SPI_RX_RX_Msk                    (0xfffffffful << SPI_RX_RX_Pos)                   /*!< SPI_T::RX: RX Mask                     */
+
+#define SPI_I2SCTL_I2SEN_Pos             (0)                                               /*!< SPI_T::I2SCTL: I2SEN Position          */
+#define SPI_I2SCTL_I2SEN_Msk             (0x1ul << SPI_I2SCTL_I2SEN_Pos)                   /*!< SPI_T::I2SCTL: I2SEN Mask              */
+
+#define SPI_I2SCTL_TXEN_Pos              (1)                                               /*!< SPI_T::I2SCTL: TXEN Position           */
+#define SPI_I2SCTL_TXEN_Msk              (0x1ul << SPI_I2SCTL_TXEN_Pos)                    /*!< SPI_T::I2SCTL: TXEN Mask               */
+
+#define SPI_I2SCTL_RXEN_Pos              (2)                                               /*!< SPI_T::I2SCTL: RXEN Position           */
+#define SPI_I2SCTL_RXEN_Msk              (0x1ul << SPI_I2SCTL_RXEN_Pos)                    /*!< SPI_T::I2SCTL: RXEN Mask               */
+
+#define SPI_I2SCTL_MUTE_Pos              (3)                                               /*!< SPI_T::I2SCTL: MUTE Position           */
+#define SPI_I2SCTL_MUTE_Msk              (0x1ul << SPI_I2SCTL_MUTE_Pos)                    /*!< SPI_T::I2SCTL: MUTE Mask               */
+
+#define SPI_I2SCTL_WDWIDTH_Pos           (4)                                               /*!< SPI_T::I2SCTL: WDWIDTH Position        */
+#define SPI_I2SCTL_WDWIDTH_Msk           (0x3ul << SPI_I2SCTL_WDWIDTH_Pos)                 /*!< SPI_T::I2SCTL: WDWIDTH Mask            */
+
+#define SPI_I2SCTL_MONO_Pos              (6)                                               /*!< SPI_T::I2SCTL: MONO Position           */
+#define SPI_I2SCTL_MONO_Msk              (0x1ul << SPI_I2SCTL_MONO_Pos)                    /*!< SPI_T::I2SCTL: MONO Mask               */
+
+#define SPI_I2SCTL_ORDER_Pos             (7)                                               /*!< SPI_T::I2SCTL: ORDER Position          */
+#define SPI_I2SCTL_ORDER_Msk             (0x1ul << SPI_I2SCTL_ORDER_Pos)                   /*!< SPI_T::I2SCTL: ORDER Mask              */
+
+#define SPI_I2SCTL_SLAVE_Pos             (8)                                               /*!< SPI_T::I2SCTL: SLAVE Position          */
+#define SPI_I2SCTL_SLAVE_Msk             (0x1ul << SPI_I2SCTL_SLAVE_Pos)                   /*!< SPI_T::I2SCTL: SLAVE Mask              */
+
+#define SPI_I2SCTL_MCLKEN_Pos            (15)                                              /*!< SPI_T::I2SCTL: MCLKEN Position         */
+#define SPI_I2SCTL_MCLKEN_Msk            (0x1ul << SPI_I2SCTL_MCLKEN_Pos)                  /*!< SPI_T::I2SCTL: MCLKEN Mask             */
+
+#define SPI_I2SCTL_RZCEN_Pos             (16)                                              /*!< SPI_T::I2SCTL: RZCEN Position          */
+#define SPI_I2SCTL_RZCEN_Msk             (0x1ul << SPI_I2SCTL_RZCEN_Pos)                   /*!< SPI_T::I2SCTL: RZCEN Mask              */
+
+#define SPI_I2SCTL_LZCEN_Pos             (17)                                              /*!< SPI_T::I2SCTL: LZCEN Position          */
+#define SPI_I2SCTL_LZCEN_Msk             (0x1ul << SPI_I2SCTL_LZCEN_Pos)                   /*!< SPI_T::I2SCTL: LZCEN Mask              */
+
+#define SPI_I2SCTL_RXLCH_Pos             (23)                                              /*!< SPI_T::I2SCTL: RXLCH Position          */
+#define SPI_I2SCTL_RXLCH_Msk             (0x1ul << SPI_I2SCTL_RXLCH_Pos)                   /*!< SPI_T::I2SCTL: RXLCH Mask              */
+
+#define SPI_I2SCTL_RZCIEN_Pos            (24)                                              /*!< SPI_T::I2SCTL: RZCIEN Position         */
+#define SPI_I2SCTL_RZCIEN_Msk            (0x1ul << SPI_I2SCTL_RZCIEN_Pos)                  /*!< SPI_T::I2SCTL: RZCIEN Mask             */
+
+#define SPI_I2SCTL_LZCIEN_Pos            (25)                                              /*!< SPI_T::I2SCTL: LZCIEN Position         */
+#define SPI_I2SCTL_LZCIEN_Msk            (0x1ul << SPI_I2SCTL_LZCIEN_Pos)                  /*!< SPI_T::I2SCTL: LZCIEN Mask             */
+
+#define SPI_I2SCTL_FORMAT_Pos            (28)                                              /*!< SPI_T::I2SCTL: FORMAT Position         */
+#define SPI_I2SCTL_FORMAT_Msk            (0x3ul << SPI_I2SCTL_FORMAT_Pos)                  /*!< SPI_T::I2SCTL: FORMAT Mask             */
+
+#define SPI_I2SCTL_SLVERRIEN_Pos         (31)                                              /*!< SPI_T::I2SCTL: SLVERRIEN Position      */
+#define SPI_I2SCTL_SLVERRIEN_Msk         (0x1ul << SPI_I2SCTL_SLVERRIEN_Pos)               /*!< SPI_T::I2SCTL: SLVERRIEN Mask          */
+
+#define SPI_I2SCLK_MCLKDIV_Pos           (0)                                               /*!< SPI_T::I2SCLK: MCLKDIV Position        */
+#define SPI_I2SCLK_MCLKDIV_Msk           (0x7ful << SPI_I2SCLK_MCLKDIV_Pos)                /*!< SPI_T::I2SCLK: MCLKDIV Mask            */
+
+#define SPI_I2SCLK_BCLKDIV_Pos           (8)                                               /*!< SPI_T::I2SCLK: BCLKDIV Position        */
+#define SPI_I2SCLK_BCLKDIV_Msk           (0x3fful << SPI_I2SCLK_BCLKDIV_Pos)               /*!< SPI_T::I2SCLK: BCLKDIV Mask            */
+
+#define SPI_I2SCLK_I2SMODE_Pos           (24)                                              /*!< SPI_T::I2SCLK: I2SMODE Position        */
+#define SPI_I2SCLK_I2SMODE_Msk           (0x1ul << SPI_I2SCLK_I2SMODE_Pos)                 /*!< SPI_T::I2SCLK: I2SMODE Mask            */
+
+#define SPI_I2SCLK_I2SSLAVE_Pos          (25)                                              /*!< SPI_T::I2SCLK: I2SSLAVE Position       */
+#define SPI_I2SCLK_I2SSLAVE_Msk          (0x1ul << SPI_I2SCLK_I2SSLAVE_Pos)                /*!< SPI_T::I2SCLK: I2SSLAVE Mask           */
+
+#define SPI_I2SSTS_RIGHT_Pos             (4)                                               /*!< SPI_T::I2SSTS: RIGHT Position          */
+#define SPI_I2SSTS_RIGHT_Msk             (0x1ul << SPI_I2SSTS_RIGHT_Pos)                   /*!< SPI_T::I2SSTS: RIGHT Mask              */
+
+#define SPI_I2SSTS_RXEMPTY_Pos           (8)                                               /*!< SPI_T::I2SSTS: RXEMPTY Position        */
+#define SPI_I2SSTS_RXEMPTY_Msk           (0x1ul << SPI_I2SSTS_RXEMPTY_Pos)                 /*!< SPI_T::I2SSTS: RXEMPTY Mask            */
+
+#define SPI_I2SSTS_RXFULL_Pos            (9)                                               /*!< SPI_T::I2SSTS: RXFULL Position         */
+#define SPI_I2SSTS_RXFULL_Msk            (0x1ul << SPI_I2SSTS_RXFULL_Pos)                  /*!< SPI_T::I2SSTS: RXFULL Mask             */
+
+#define SPI_I2SSTS_RXTHIF_Pos            (10)                                              /*!< SPI_T::I2SSTS: RXTHIF Position         */
+#define SPI_I2SSTS_RXTHIF_Msk            (0x1ul << SPI_I2SSTS_RXTHIF_Pos)                  /*!< SPI_T::I2SSTS: RXTHIF Mask             */
+
+#define SPI_I2SSTS_RXOVIF_Pos            (11)                                              /*!< SPI_T::I2SSTS: RXOVIF Position         */
+#define SPI_I2SSTS_RXOVIF_Msk            (0x1ul << SPI_I2SSTS_RXOVIF_Pos)                  /*!< SPI_T::I2SSTS: RXOVIF Mask             */
+
+#define SPI_I2SSTS_RXTOIF_Pos            (12)                                              /*!< SPI_T::I2SSTS: RXTOIF Position         */
+#define SPI_I2SSTS_RXTOIF_Msk            (0x1ul << SPI_I2SSTS_RXTOIF_Pos)                  /*!< SPI_T::I2SSTS: RXTOIF Mask             */
+
+#define SPI_I2SSTS_I2SENSTS_Pos          (15)                                              /*!< SPI_T::I2SSTS: I2SENSTS Position       */
+#define SPI_I2SSTS_I2SENSTS_Msk          (0x1ul << SPI_I2SSTS_I2SENSTS_Pos)                /*!< SPI_T::I2SSTS: I2SENSTS Mask           */
+
+#define SPI_I2SSTS_TXEMPTY_Pos           (16)                                              /*!< SPI_T::I2SSTS: TXEMPTY Position        */
+#define SPI_I2SSTS_TXEMPTY_Msk           (0x1ul << SPI_I2SSTS_TXEMPTY_Pos)                 /*!< SPI_T::I2SSTS: TXEMPTY Mask            */
+
+#define SPI_I2SSTS_TXFULL_Pos            (17)                                              /*!< SPI_T::I2SSTS: TXFULL Position         */
+#define SPI_I2SSTS_TXFULL_Msk            (0x1ul << SPI_I2SSTS_TXFULL_Pos)                  /*!< SPI_T::I2SSTS: TXFULL Mask             */
+
+#define SPI_I2SSTS_TXTHIF_Pos            (18)                                              /*!< SPI_T::I2SSTS: TXTHIF Position         */
+#define SPI_I2SSTS_TXTHIF_Msk            (0x1ul << SPI_I2SSTS_TXTHIF_Pos)                  /*!< SPI_T::I2SSTS: TXTHIF Mask             */
+
+#define SPI_I2SSTS_TXUFIF_Pos            (19)                                              /*!< SPI_T::I2SSTS: TXUFIF Position         */
+#define SPI_I2SSTS_TXUFIF_Msk            (0x1ul << SPI_I2SSTS_TXUFIF_Pos)                  /*!< SPI_T::I2SSTS: TXUFIF Mask             */
+
+#define SPI_I2SSTS_RZCIF_Pos             (20)                                              /*!< SPI_T::I2SSTS: RZCIF Position          */
+#define SPI_I2SSTS_RZCIF_Msk             (0x1ul << SPI_I2SSTS_RZCIF_Pos)                   /*!< SPI_T::I2SSTS: RZCIF Mask              */
+
+#define SPI_I2SSTS_LZCIF_Pos             (21)                                              /*!< SPI_T::I2SSTS: LZCIF Position          */
+#define SPI_I2SSTS_LZCIF_Msk             (0x1ul << SPI_I2SSTS_LZCIF_Pos)                   /*!< SPI_T::I2SSTS: LZCIF Mask              */
+
+#define SPI_I2SSTS_SLVERRIF_Pos          (22)                                              /*!< SPI_T::I2SSTS: SLVERRIF Position       */
+#define SPI_I2SSTS_SLVERRIF_Msk          (0x1ul << SPI_I2SSTS_SLVERRIF_Pos)                /*!< SPI_T::I2SSTS: SLVERRIF Mask           */
+
+#define SPI_I2SSTS_TXRXRST_Pos           (23)                                              /*!< SPI_T::I2SSTS: TXRXRST Position        */
+#define SPI_I2SSTS_TXRXRST_Msk           (0x1ul << SPI_I2SSTS_TXRXRST_Pos)                 /*!< SPI_T::I2SSTS: TXRXRST Mask            */
+
+#define SPI_I2SSTS_RXCNT_Pos             (24)                                              /*!< SPI_T::I2SSTS: RXCNT Position          */
+#define SPI_I2SSTS_RXCNT_Msk             (0x7ul << SPI_I2SSTS_RXCNT_Pos)                   /*!< SPI_T::I2SSTS: RXCNT Mask              */
+
+#define SPI_I2SSTS_TXCNT_Pos             (28)                                              /*!< SPI_T::I2SSTS: TXCNT Position          */
+#define SPI_I2SSTS_TXCNT_Msk             (0x7ul << SPI_I2SSTS_TXCNT_Pos)                   /*!< SPI_T::I2SSTS: TXCNT Mask              */
+
+/**@}*/ /* SPI_CONST */
+/**@}*/ /* end of SPI register group */
+/**@}*/ /* end of REGISTER group */
+
+#endif /* __SPI_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/sys_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/sys_reg.h
new file mode 100644
index 0000000000..4dfc39f4a1
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/sys_reg.h
@@ -0,0 +1,2617 @@
+/**************************************************************************//**
+ * @file     sys_reg.h
+ * @version  V1.00
+ * @brief    SYS register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __SYS_REG_H__
+#define __SYS_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+/*---------------------- System Manger Controller -------------------------*/
+/**
+    @addtogroup SYS System Manger Controller(SYS)
+    Memory Mapped Structure for SYS Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var SYS_T::PDID
+     * Offset: 0x00  Part Device Identification Number Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |PDID      |Part Device Identification Number (Read Only)
+     * |        |          |This register reflects device part number code.
+     * |        |          |Software can read this register to identify which device is used.
+     * @var SYS_T::RSTSTS
+     * Offset: 0x04  System Reset Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PORF      |POR Reset Flag
+     * |        |          |The POR reset flag is set by the "Reset Signal" from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.
+     * |        |          |0 = No reset from POR or CHIPRST.
+     * |        |          |1 = Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[1]     |PINRF     |nRESET Pin Reset Flag
+     * |        |          |The nRESET pin reset flag is set by the "Reset Signal" from the nRESET Pin to indicate the previous reset source.
+     * |        |          |0 = No reset from nRESET pin.
+     * |        |          |1 = Pin nRESET had issued the reset signal to reset the system.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[2]     |WDTRF     |WDT Reset Flag
+     * |        |          |The WDT reset flag is set by the "Reset Signal" from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.
+     * |        |          |0 = No reset from watchdog timer or window watchdog timer.
+     * |        |          |1 = The watchdog timer or window watchdog timer had issued the reset signal to reset the system.
+     * |        |          |Note 1: Write 1 to clear this bit to 0.
+     * |        |          |Note 2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset.
+     * |        |          |Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
+     * |        |          |Note 3: Extra Watchdog Timer register RSTF(EWDT_CTL[2]) bit is set if the system has been reset by EWDT time-out reset.
+     * |        |          |Extra Window Watchdog Timer register WWDTRF(EWWDT_STATUS[1]) bit is set if the system has been reset by EWWDT time-out reset.
+     * |[3]     |LVRF      |LVR Reset Flag
+     * |        |          |The LVR reset flag is set by the "Reset Signal" from the Low Voltage Reset Controller to indicate the previous reset source.
+     * |        |          |0 = No reset from LVR.
+     * |        |          |1 = LVR controller had issued the reset signal to reset the system.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[4]     |BODRF     |BOD Reset Flag
+     * |        |          |The BOD reset flag is set by the "Reset Signal" from the Brown-out Detector to indicate the previous reset source.
+     * |        |          |0 = No reset from BOD.
+     * |        |          |1 = The BOD had issued the reset signal to reset the system.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[5]     |SYSRF     |System Reset Flag
+     * |        |          |The system reset flag is set by the "Reset Signal" from the Cortex-M23 Core to indicate the previous reset source.
+     * |        |          |0 = No reset from Cortex-M23.
+     * |        |          |1 = The Cortex-M23 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M23 core.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[7]     |CPURF     |CPU Reset Flag
+     * |        |          |The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M23 Core and Flash Memory Controller (FMC).
+     * |        |          |0 = No reset from CPU.
+     * |        |          |1 = The Cortex-M23 Core and FMC are reset by software setting CPURST to 1.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[8]     |CPULKRF   |CPU Lockup Reset Flag
+     * |        |          |The CPULK reset flag is set by hardware if Cortex-M23 lockup happened.
+     * |        |          |0 = No reset from CPU lockup happened.
+     * |        |          |1 = The Cortex-M23 lockup happened and chip is reset.
+     * |        |          |Note1: Write 1 to clear this bit to 0.
+     * |        |          |Note2: When CPU lockup happened under ICE is connected, This flag will set to 1 but chip will not reset.
+     * @var SYS_T::IPRST0
+     * Offset: 0x08  Peripheral Reset Control Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CHIPRST   |Chip One-shot Reset (Write Protect)
+     * |        |          |Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.
+     * |        |          |The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.
+     * |        |          |0 = Chip normal operation.
+     * |        |          |1 = Chip one-shot reset.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[1]     |CPURST    |Processor Core One-shot Reset (Write Protect)
+     * |        |          |Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles.
+     * |        |          |0 = Processor core normal operation.
+     * |        |          |1 = Processor core one-shot reset.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[2]     |PDMA0RST  |PDMA0 Controller Reset (Write Protect)
+     * |        |          |Setting this bit to 1 will generate a reset signal to the PDMA0 (always secure).
+     * |        |          |User needs to set this bit to 0 to release from reset state.
+     * |        |          |0 = PDMA0 controller normal operation.
+     * |        |          |1 = PDMA0 controller reset.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[3]     |EBIRST    |EBI Controller Reset (Write Protect)
+     * |        |          |Set this bit to 1 will generate a reset signal to the EBI
+     * |        |          |User needs to set this bit to 0 to release from the reset state.
+     * |        |          |0 = EBI controller normal operation.
+     * |        |          |1 = EBI controller reset.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[4]     |USBHRST   |USB Host Controller Reset (Write Protect)
+     * |        |          |Set this bit to 1 will generate a reset signal to the USB Host.
+     * |        |          |User needs to set this bit to 0 to release from the reset state.
+     * |        |          |0 = USB Host controller normal operation.
+     * |        |          |1 = USB Host controller reset.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[6]     |SDH0RST   |SDHOST0 Controller Reset (Write Protect)
+     * |        |          |Setting this bit to 1 will generate a reset signal to the SDHOST0 controller
+     * |        |          |User needs to set this bit to 0 to release from the reset state.
+     * |        |          |0 = SDHOST0 controller normal operation.
+     * |        |          |1 = SDHOST0 controller reset.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[7]     |CRCRST    |CRC Calculation Controller Reset (Write Protect)
+     * |        |          |Set this bit to 1 will generate a reset signal to the CRC calculation controller
+     * |        |          |User needs to set this bit to 0 to release from the reset state.
+     * |        |          |0 = CRC calculation controller normal operation.
+     * |        |          |1 = CRC calculation controller reset.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[12]    |CRPTRST   |CRYPTO Controller Reset (Write Protect)
+     * |        |          |Setting this bit to 1 will generate a reset signal to the CRYPTO controller.
+     * |        |          |User needs to set this bit to 0 to release from the reset state.
+     * |        |          |0 = CRYPTO controller normal operation.
+     * |        |          |1 = CRYPTO controller reset.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[13]    |KSRST     |Key Store Controller Reset (Write Protect)
+     * |        |          |Setting this bit to 1 will generate a reset signal to the CRYPTO controller.
+     * |        |          |User needs to set this bit to 0 to release from the reset state.
+     * |        |          |0 = Key Store controller normal operation.
+     * |        |          |1 = Key Store controller reset.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[29]    |PDMA1RST  |PDMA1 Controller Reset (Write Protect)
+     * |        |          |Setting this bit to 1 will generate a reset signal to the PDMA1.
+     * |        |          |User needs to set this bit to 0 to release from reset state.
+     * |        |          |0 = PDMA1 controller normal operation.
+     * |        |          |1 = PDMA1 controller reset.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * @var SYS_T::IPRST1
+     * Offset: 0x0C  Peripheral Reset Control Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1]     |GPIORST   |GPIO Controller Reset
+     * |        |          |0 = GPIO controller normal operation.
+     * |        |          |1 = GPIO controller reset.
+     * |[2]     |TMR0RST   |Timer0 Controller Reset
+     * |        |          |0 = Timer0 controller normal operation.
+     * |        |          |1 = Timer0 controller reset.
+     * |[3]     |TMR1RST   |Timer1 Controller Reset
+     * |        |          |0 = Timer1 controller normal operation.
+     * |        |          |1 = Timer1 controller reset.
+     * |[4]     |TMR2RST   |Timer2 Controller Reset
+     * |        |          |0 = Timer2 controller normal operation.
+     * |        |          |1 = Timer2 controller reset.
+     * |[5]     |TMR3RST   |Timer3 Controller Reset
+     * |        |          |0 = Timer3 controller normal operation.
+     * |        |          |1 = Timer3 controller reset.
+     * |[7]     |ACMP01RST |Analog Comparator 0/1 Controller Reset
+     * |        |          |0 = Analog Comparator 0/1 controller normal operation.
+     * |        |          |1 = Analog Comparator 0/1 controller reset.
+     * |[8]     |I2C0RST   |I2C0 Controller Reset
+     * |        |          |0 = I2C0 controller normal operation.
+     * |        |          |1 = I2C0 controller reset.
+     * |[9]     |I2C1RST   |I2C1 Controller Reset
+     * |        |          |0 = I2C1 controller normal operation.
+     * |        |          |1 = I2C1 controller reset.
+     * |[10]    |I2C2RST   |I2C2 Controller Reset
+     * |        |          |0 = I2C2 controller normal operation.
+     * |        |          |1 = I2C2 controller reset.
+     * |[12]    |QSPI0RST  |QSPI0 Controller Reset
+     * |        |          |0 = QSPI0 controller normal operation.
+     * |        |          |1 = QSPI0 controller reset.
+     * |[13]    |SPI0RST   |SPI0 Controller Reset
+     * |        |          |0 = SPI0 controller normal operation.
+     * |        |          |1 = SPI0 controller reset.
+     * |[14]    |SPI1RST   |SPI1 Controller Reset
+     * |        |          |0 = SPI1 controller normal operation.
+     * |        |          |1 = SPI1 controller reset.
+     * |[15]    |SPI2RST   |SPI2 Controller Reset
+     * |        |          |0 = SPI2 controller normal operation.
+     * |        |          |1 = SPI2 controller reset.
+     * |[16]    |UART0RST  |UART0 Controller Reset
+     * |        |          |0 = UART0 controller normal operation.
+     * |        |          |1 = UART0 controller reset.
+     * |[17]    |UART1RST  |UART1 Controller Reset
+     * |        |          |0 = UART1 controller normal operation.
+     * |        |          |1 = UART1 controller reset.
+     * |[18]    |UART2RST  |UART2 Controller Reset
+     * |        |          |0 = UART2 controller normal operation.
+     * |        |          |1 = UART2 controller reset.
+     * |[19]    |UART3RST  |UART3 Controller Reset
+     * |        |          |0 = UART3 controller normal operation.
+     * |        |          |1 = UART3 controller reset.
+     * |[20]    |UART4RST  |UART4 Controller Reset
+     * |        |          |0 = UART4 controller normal operation.
+     * |        |          |1 = UART4 controller reset.
+     * |[21]    |UART5RST  |UART5 Controller Reset
+     * |        |          |0 = UART5 controller normal operation.
+     * |        |          |1 = UART5 controller reset.
+     * |[24]    |CAN0RST   |CAN0 Controller Reset
+     * |        |          |0 = CAN0 controller normal operation.
+     * |        |          |1 = CAN0 controller reset.
+     * |[26]    |OTGRST    |OTG Controller Reset
+     * |        |          |0 = OTG controller normal operation.
+     * |        |          |1 = OTG controller reset.
+     * |[27]    |USBDRST   |USBD Controller Reset
+     * |        |          |0 = USBD controller normal operation.
+     * |        |          |1 = USBD controller reset.
+     * |[28]    |EADCRST   |EADC Controller Reset
+     * |        |          |0 = EADC controller normal operation.
+     * |        |          |1 = EADC controller reset.
+     * |[29]    |I2S0RST   |I2S0 Controller Reset
+     * |        |          |0 = I2S0 controller normal operation.
+     * |        |          |1 = I2S0 controller reset.
+     * |[30]    |LCDRST    |LCD Controller Reset
+     * |        |          |0 = LCD controller normal operation.
+     * |        |          |1 = LCD controller reset.
+     * |[31]    |TRNGRST   |TRNG Controller Reset
+     * |        |          |0 = TRNG controller normal operation.
+     * |        |          |1 = TRNG controller reset.
+     * @var SYS_T::IPRST2
+     * Offset: 0x10  Peripheral Reset Control Register 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SC0RST    |SC0 Controller Reset
+     * |        |          |0 = SC0 controller normal operation.
+     * |        |          |1 = SC0 controller reset.
+     * |[1]     |SC1RST    |SC1 Controller Reset
+     * |        |          |0 = SC1 controller normal operation.
+     * |        |          |1 = SC1 controller reset.
+     * |[2]     |SC2RST    |SC2 Controller Reset
+     * |        |          |0 = SC2 controller normal operation.
+     * |        |          |1 = SC2 controller reset.
+     * |[6]     |SPI3RST   |SPI3 Controller Reset
+     * |        |          |0 = SPI3 controller normal operation.
+     * |        |          |1 = SPI3 controller reset.
+     * |[8]     |USCI0RST  |USCI0 Controller Reset
+     * |        |          |0 = USCI0 controller normal operation.
+     * |        |          |1 = USCI0 controller reset.
+     * |[9]     |USCI1RST  |USCI1 Controller Reset
+     * |        |          |0 = USCI1 controller normal operation.
+     * |        |          |1 = USCI1 controller reset.
+     * |[12]    |DACRST    |DAC Controller Reset
+     * |        |          |0 = DAC controller normal operation.
+     * |        |          |1 = DAC controller reset.
+     * |[16]    |EPWM0RST  |EPWM0 Controller Reset
+     * |        |          |0 = EPWM0 controller normal operation.
+     * |        |          |1 = EPWM0 controller reset.
+     * |[17]    |EPWM1RST  |EPWM1 Controller Reset
+     * |        |          |0 = EPWM1 controller normal operation.
+     * |        |          |1 = EPWM1 controller reset.
+     * |[18]    |BPWM0RST  |BPWM0 Controller Reset
+     * |        |          |0 = BPWM0 controller normal operation.
+     * |        |          |1 = BPWM0 controller reset.
+     * |[19]    |BPWM1RST  |BPWM1 Controller Reset
+     * |        |          |0 = BPWM1 controller normal operation.
+     * |        |          |1 = BPWM1 controller reset.
+     * |[20]    |TMR4RST   |Timer4 Controller Reset
+     * |        |          |0 = Timer4 controller normal operation.
+     * |        |          |1 = Timer4 controller reset.
+     * |[21]    |TMR5RST   |Timer5 Controller Reset
+     * |        |          |0 = Timer5 controller normal operation.
+     * |        |          |1 = Timer5 controller reset.
+     * |[22]    |QEI0RST   |QEI0 Controller Reset
+     * |        |          |0 = QEI0 controller normal operation.
+     * |        |          |1 = QEI0 controller reset.
+     * |[23]    |QEI1RST   |QEI1 Controller Reset
+     * |        |          |0 = QEI1 controller normal operation.
+     * |        |          |1 = QEI1 controller reset.
+     * |[26]    |ECAP0RST  |ECAP0 Controller Reset
+     * |        |          |0 = ECAP0 controller normal operation.
+     * |        |          |1 = ECAP0 controller reset.
+     * |[27]    |ECAP1RST  |ECAP1 Controller Reset
+     * |        |          |0 = ECAP1 controller normal operation.
+     * |        |          |1 = ECAP1 controller reset.
+     * @var SYS_T::BODCTL
+     * Offset: 0x18  Brown-out Detector Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BODEN     |Brown-out Detector Enable Bit (Write Protect)
+     * |        |          |The default value is set by flash controller user configuration register CBODEN (CONFIG0 [23]).
+     * |        |          |0 = Brown-out Detector function Disabled.
+     * |        |          |1 = Brown-out Detector function Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[3]     |BODRSTEN  |Brown-out Reset Enable Bit (Write Protect)
+     * |        |          |The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit .
+     * |        |          |0 = Brown-out INTERRUPT function Enabled.
+     * |        |          |1 = Brown-out RESET function Enabled.
+     * |        |          |Note1:
+     * |        |          |While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).
+     * |        |          |While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if AVDD high.than BODVL, BOD interrupt will keep till to the BODIF set to 0.
+     * |        |          |BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low).
+     * |        |          |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[4]     |BODIF     |Brown-out Detector Interrupt Flag
+     * |        |          |0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting.
+     * |        |          |1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled.
+     * |        |          |Note: Write 1 to clear this bit to 0.
+     * |[6]     |BODOUT    |Brown-out Detector Output Status
+     * |        |          |0 = Brown-out Detector output status is 0.
+     * |        |          |It means the detected voltage is higher than BODVL setting or BODEN is 0.
+     * |        |          |1 = Brown-out Detector output status is 1.
+     * |        |          |It means the detected voltage is lower than BODVL setting.
+     * |        |          |If the BODEN is 0, BOD function disabled , this bit always responds 0.
+     * |[7]     |LVREN     |Low Voltage Reset Enable Bit (Write Protect)
+     * |        |          |The LVR function resets the chip when the input power voltage is lower than LVR circuit setting.
+     * |        |          |LVR function is enabled by default.
+     * |        |          |0 = Low Voltage Reset function Disabled.
+     * |        |          |1 = Low Voltage Reset function Enabled.
+     * |        |          |Note1: After enabling the bit, the LVR function will be active with 200us delay for LVR output stable (default).
+     * |        |          |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[10:8]  |BODDGSEL  |Brown-out Detector Output De-glitch Time Select (Write Protect)
+     * |        |          |000 = BOD output is sampled by LIRC clock.
+     * |        |          |001 = 4 system clock (HCLK).
+     * |        |          |010 = 8 system clock (HCLK).
+     * |        |          |011 = 16 system clock (HCLK).
+     * |        |          |100 = 32 system clock (HCLK).
+     * |        |          |101 = 64 system clock (HCLK).
+     * |        |          |110 = 128 system clock (HCLK).
+     * |        |          |111 = 256 system clock (HCLK).
+     * |        |          |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |[14:12] |LVRDGSEL  |LVR Output De-glitch Time Select (Write Protect)
+     * |        |          |000 = Without de-glitch function.
+     * |        |          |001 = 4 system clock (HCLK).
+     * |        |          |010 = 8 system clock (HCLK).
+     * |        |          |011 = 16 system clock (HCLK).
+     * |        |          |100 = 32 system clock (HCLK).
+     * |        |          |101 = 64 system clock (HCLK).
+     * |        |          |110 = 128 system clock (HCLK).
+     * |        |          |111 = 256 system clock (HCLK).
+     * |        |          |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |[23]    |STB       |Circuit Stable Flag (Read Only)
+     * |        |          |This bit indicates LVR and BOD already stable, system cannot detect LVR and BOD event when this bit is not set.
+     * |        |          |0 = LVR and BOD is not stable.
+     * |        |          |1 = LVR and BOD already stable.
+     * |[18:16] |BODVL     |Brown-out Detector Threshold Voltage Selection (Write Protect)
+     * |        |          |The default value is set by flash controller user configuration register CBOV (CONFIG0 [23:21]).
+     * |        |          |000 = Brown-out Detector threshold voltage is 1.6V.
+     * |        |          |001 = Brown-out Detector threshold voltage is 1.8V.
+     * |        |          |010 = Brown-out Detector threshold voltage is 2.0V.
+     * |        |          |011 = Brown-out Detector threshold voltage is 2.2V.
+     * |        |          |100 = Brown-out Detector threshold voltage is 2.4V.
+     * |        |          |101 = Brown-out Detector threshold voltage is 2.6V.
+     * |        |          |110 = Brown-out Detector threshold voltage is 2.8V.
+     * |        |          |111 = Brown-out Detector threshold voltage is 3.0V.
+     * |        |          |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |[31]    |WRBUSY    |Write Busy Flag (Read Only)
+     * |        |          |If SYS_BODCTL is written, this bit is asserted automatically by hardware, and is de-asserted when write procedure is finished.
+     * |        |          |0 = SYS_BODCTL register is ready for write operation.
+     * |        |          |1 = SYS_BODCTL register is busy on the last write operation. Other write operations are ignored.
+     * @var SYS_T::IVSCTL
+     * Offset: 0x1C  Internal Voltage Source Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |VTEMPEN   |Temperature Sensor Enable Bit
+     * |        |          |This bit is used to enable/disable temperature sensor function.
+     * |        |          |0 = Temperature sensor function Disabled (default).
+     * |        |          |1 = Temperature sensor function Enabled.
+     * |        |          |Note: After this bit is set to 1, the value of temperature sensor output can be obtained through GPC.9.
+     * |[1]     |VBATUGEN  |VBAT Unity Gain Buffer Enable Bit
+     * |        |          |This bit is used to enable/disable VBAT unity gain buffer function.
+     * |        |          |0 = VBAT unity gain buffer function Disabled (default).
+     * |        |          |1 = VBAT unity gain buffer function Enabled.
+     * |        |          |Note: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result.
+     * @var SYS_T::PORCTL0
+     * Offset: 0x24  Power-on Reset Controller Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |PORMASK   |Power-on Reset Mask Enable Bit (Write Protect)
+     * |        |          |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again.
+     * |        |          |User can mask  internal POR signal to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
+     * |        |          |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:
+     * |        |          |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function.
+     * |        |          |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * @var SYS_T::VREFCTL
+     * Offset: 0x28  VREF Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[4:0]   |VREFCTL   |VREF Control Bits (Write Protect)
+     * |        |          |00000 = VREF is from external pin.
+     * |        |          |00011 = VREF is internal 1.6V.
+     * |        |          |00111 = VREF is internal 2.0V.
+     * |        |          |01011 = VREF is internal 2.5V.
+     * |        |          |01111 = VREF is internal 3.0V.
+     * |        |          |Others = Reserved.
+     * |        |          |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |[5]     |IBIASSEL  |VREF Bias Current Selection (Write Protect)
+     * |        |          |0 = Bias current from MEGBIAS.
+     * |        |          |1 = Bias current from internal.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[7:6]   |PRELOADSEL|Pre-load Timing Selection (Write Protect)
+     * |        |          |00 = pre-load time is 60us for 0.1uF Capacitor.
+     * |        |          |01 = pre-load time is 310us for 1uF Capacitor.
+     * |        |          |10 = pre-load time is 1270us for 4.7uF Capacitor.
+     * |        |          |11 = pre-load time is 2650us for 10uF Capacitor.
+     * |        |          |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * @var SYS_T::USBPHY
+     * Offset: 0x2C  USB PHY Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |USBROLE   |USB Role Option (Write Protect)
+     * |        |          |These two bits are used to select the role of USB.
+     * |        |          |00 = Standard USB Device mode.
+     * |        |          |01 = Standard USB Host mode.
+     * |        |          |10 = ID dependent mode.
+     * |        |          |11 = On-The-Go device mode (default).
+     * |        |          |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |[2]     |SBO       |Note: This bit must always be kept 1. If set to 0, the result is unpredictable.
+     * |[8]     |OTGPHYEN  |USB OTG PHY Enable
+     * |        |          |This bit is used to enable/disable OTG PHY function.
+     * |        |          |0 = OTG PHY function Disabled (default).
+     * |        |          |1 = OTG PHY function Enabled.
+     * @var SYS_T::GPA_MFPL
+     * Offset: 0x30  GPIOA Low Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |PA0MFP    |PA.0 Multi-function Pin Selection
+     * |[7:4]   |PA1MFP    |PA.1 Multi-function Pin Selection
+     * |[11:8]  |PA2MFP    |PA.2 Multi-function Pin Selection
+     * |[15:12] |PA3MFP    |PA.3 Multi-function Pin Selection
+     * |[19:16] |PA4MFP    |PA.4 Multi-function Pin Selection
+     * |[23:20] |PA5MFP    |PA.5 Multi-function Pin Selection
+     * |[27:24] |PA6MFP    |PA.6 Multi-function Pin Selection
+     * |[31:28] |PA7MFP    |PA.7 Multi-function Pin Selection
+     * @var SYS_T::GPA_MFPH
+     * Offset: 0x34  GPIOA High Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |PA8MFP    |PA.8 Multi-function Pin Selection
+     * |[7:4]   |PA9MFP    |PA.9 Multi-function Pin Selection
+     * |[11:8]  |PA10MFP   |PA.10 Multi-function Pin Selection
+     * |[15:12] |PA11MFP   |PA.11 Multi-function Pin Selection
+     * |[19:16] |PA12MFP   |PA.12 Multi-function Pin Selection
+     * |[23:20] |PA13MFP   |PA.13 Multi-function Pin Selection
+     * |[27:24] |PA14MFP   |PA.14 Multi-function Pin Selection
+     * |[31:28] |PA15MFP   |PA.15 Multi-function Pin Selection
+     * @var SYS_T::GPB_MFPL
+     * Offset: 0x38  GPIOB Low Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |PB0MFP    |PB.0 Multi-function Pin Selection
+     * |[7:4]   |PB1MFP    |PB.1 Multi-function Pin Selection
+     * |[11:8]  |PB2MFP    |PB.2 Multi-function Pin Selection
+     * |[15:12] |PB3MFP    |PB.3 Multi-function Pin Selection
+     * |[19:16] |PB4MFP    |PB.4 Multi-function Pin Selection
+     * |[23:20] |PB5MFP    |PB.5 Multi-function Pin Selection
+     * |[27:24] |PB6MFP    |PB.6 Multi-function Pin Selection
+     * |[31:28] |PB7MFP    |PB.7 Multi-function Pin Selection
+     * @var SYS_T::GPB_MFPH
+     * Offset: 0x3C  GPIOB High Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |PB8MFP    |PB.8 Multi-function Pin Selection
+     * |[7:4]   |PB9MFP    |PB.9 Multi-function Pin Selection
+     * |[11:8]  |PB10MFP   |PB.10 Multi-function Pin Selection
+     * |[15:12] |PB11MFP   |PB.11 Multi-function Pin Selection
+     * |[19:16] |PB12MFP   |PB.12 Multi-function Pin Selection
+     * |[23:20] |PB13MFP   |PB.13 Multi-function Pin Selection
+     * |[27:24] |PB14MFP   |PB.14 Multi-function Pin Selection
+     * |[31:28] |PB15MFP   |PB.15 Multi-function Pin Selection
+     * @var SYS_T::GPC_MFPL
+     * Offset: 0x40  GPIOC Low Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |PC0MFP    |PC.0 Multi-function Pin Selection
+     * |[7:4]   |PC1MFP    |PC.1 Multi-function Pin Selection
+     * |[11:8]  |PC2MFP    |PC.2 Multi-function Pin Selection
+     * |[15:12] |PC3MFP    |PC.3 Multi-function Pin Selection
+     * |[19:16] |PC4MFP    |PC.4 Multi-function Pin Selection
+     * |[23:20] |PC5MFP    |PC.5 Multi-function Pin Selection
+     * |[27:24] |PC6MFP    |PC.6 Multi-function Pin Selection
+     * |[31:28] |PC7MFP    |PC.7 Multi-function Pin Selection
+     * @var SYS_T::GPC_MFPH
+     * Offset: 0x44  GPIOC High Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |PC8MFP    |PC.8 Multi-function Pin Selection
+     * |[7:4]   |PC9MFP    |PC.9 Multi-function Pin Selection
+     * |[11:8]  |PC10MFP   |PC.10 Multi-function Pin Selection
+     * |[15:12] |PC11MFP   |PC.11 Multi-function Pin Selection
+     * |[19:16] |PC12MFP   |PC.12 Multi-function Pin Selection
+     * |[23:20] |PC13MFP   |PC.13 Multi-function Pin Selection
+     * @var SYS_T::GPD_MFPL
+     * Offset: 0x48  GPIOD Low Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |PD0MFP    |PD.0 Multi-function Pin Selection
+     * |[7:4]   |PD1MFP    |PD.1 Multi-function Pin Selection
+     * |[11:8]  |PD2MFP    |PD.2 Multi-function Pin Selection
+     * |[15:12] |PD3MFP    |PD.3 Multi-function Pin Selection
+     * |[19:16] |PD4MFP    |PD.4 Multi-function Pin Selection
+     * |[23:20] |PD5MFP    |PD.5 Multi-function Pin Selection
+     * |[27:24] |PD6MFP    |PD.6 Multi-function Pin Selection
+     * |[31:28] |PD7MFP    |PD.7 Multi-function Pin Selection
+     * @var SYS_T::GPD_MFPH
+     * Offset: 0x4C  GPIOD High Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |PD8MFP    |PD.8 Multi-function Pin Selection
+     * |[7:4]   |PD9MFP    |PD.9 Multi-function Pin Selection
+     * |[11:8]  |PD10MFP   |PD.10 Multi-function Pin Selection
+     * |[15:12] |PD11MFP   |PD.11 Multi-function Pin Selection
+     * |[19:16] |PD12MFP   |PD.12 Multi-function Pin Selection
+     * |[27:24] |PD14MFP   |PD.14 Multi-function Pin Selection
+     * @var SYS_T::GPE_MFPL
+     * Offset: 0x50  GPIOE Low Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |PE0MFP    |PE.0 Multi-function Pin Selection
+     * |[7:4]   |PE1MFP    |PE.1 Multi-function Pin Selection
+     * |[11:8]  |PE2MFP    |PE.2 Multi-function Pin Selection
+     * |[15:12] |PE3MFP    |PE.3 Multi-function Pin Selection
+     * |[19:16] |PE4MFP    |PE.4 Multi-function Pin Selection
+     * |[23:20] |PE5MFP    |PE.5 Multi-function Pin Selection
+     * |[27:24] |PE6MFP    |PE.6 Multi-function Pin Selection
+     * |[31:28] |PE7MFP    |PE.7 Multi-function Pin Selection
+     * @var SYS_T::GPE_MFPH
+     * Offset: 0x54  GPIOE High Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |PE8MFP    |PE.8 Multi-function Pin Selection
+     * |[7:4]   |PE9MFP    |PE.9 Multi-function Pin Selection
+     * |[11:8]  |PE10MFP   |PE.10 Multi-function Pin Selection
+     * |[15:12] |PE11MFP   |PE.11 Multi-function Pin Selection
+     * |[19:16] |PE12MFP   |PE.12 Multi-function Pin Selection
+     * |[23:20] |PE13MFP   |PE.13 Multi-function Pin Selection
+     * |[27:24] |PE14MFP   |PE.14 Multi-function Pin Selection
+     * |[31:28] |PE15MFP   |PE.15 Multi-function Pin Selection
+     * @var SYS_T::GPF_MFPL
+     * Offset: 0x58  GPIOF Low Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |PF0MFP    |PF.0 Multi-function Pin Selection
+     * |[7:4]   |PF1MFP    |PF.1 Multi-function Pin Selection
+     * |[11:8]  |PF2MFP    |PF.2 Multi-function Pin Selection
+     * |[15:12] |PF3MFP    |PF.3 Multi-function Pin Selection
+     * |[19:16] |PF4MFP    |PF.4 Multi-function Pin Selection
+     * |[23:20] |PF5MFP    |PF.5 Multi-function Pin Selection
+     * |[27:24] |PF6MFP    |PF.6 Multi-function Pin Selection
+     * |[31:28] |PF7MFP    |PF.7 Multi-function Pin Selection
+     * @var SYS_T::GPF_MFPH
+     * Offset: 0x5C  GPIOF High Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |PF8MFP    |PF.8 Multi-function Pin Selection
+     * |[7:4]   |PF9MFP    |PF.9 Multi-function Pin Selection
+     * |[11:8]  |PF10MFP   |PF.10 Multi-function Pin Selection
+     * |[15:12] |PF11MFP   |PF.11 Multi-function Pin Selection
+     * @var SYS_T::GPG_MFPL
+     * Offset: 0x60  GPIOG Low Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[11:8]  |PG2MFP    |PG.2 Multi-function Pin Selection
+     * |[15:12] |PG3MFP    |PG.3 Multi-function Pin Selection
+     * |[19:16] |PG4MFP    |PG.4 Multi-function Pin Selection
+     * @var SYS_T::GPG_MFPH
+     * Offset: 0x64  GPIOG High Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:4]   |PG9MFP    |PG.9 Multi-function Pin Selection
+     * |[11:8]  |PG10MFP   |PG.10 Multi-function Pin Selection
+     * |[15:12] |PG11MFP   |PG.11 Multi-function Pin Selection
+     * |[19:16] |PG12MFP   |PG.12 Multi-function Pin Selection
+     * |[23:20] |PG13MFP   |PG.13 Multi-function Pin Selection
+     * |[27:24] |PG14MFP   |PG.14 Multi-function Pin Selection
+     * |[31:28] |PG15MFP   |PG.15 Multi-function Pin Selection
+     * @var SYS_T::GPH_MFPL
+     * Offset: 0x68  GPIOH Low Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[19:16] |PH4MFP    |PH.4 Multi-function Pin Selection
+     * |[23:20] |PH5MFP    |PH.5 Multi-function Pin Selection
+     * |[27:24] |PH6MFP    |PH.6 Multi-function Pin Selection
+     * |[31:28] |PH7MFP    |PH.7 Multi-function Pin Selection
+     * @var SYS_T::GPH_MFPH
+     * Offset: 0x6C  GPIOH High Byte Multiple Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |PH8MFP    |PH.8 Multi-function Pin Selection
+     * |[7:4]   |PH9MFP    |PH.9 Multi-function Pin Selection
+     * |[11:8]  |PH10MFP   |PH.10 Multi-function Pin Selection
+     * |[15:12] |PH11MFP   |PH.11 Multi-function Pin Selection
+     * @var SYS_T::VTORSET
+     * Offset: 0xA0  VTOR Setting Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |VTORSET   |VTOR Setting After SPD Wakeup (Write Protect)
+     * |        |          |This is the register to set the address of vector table after chip is waked up from SPD Power-down mode.
+     * |        |          |The value will be loaded to Vector Table Offset Register, which is at the address 0xE000ED08, when chip wake up from SPD mode.
+     * |        |          |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * @var SYS_T::SRAMICTL
+     * Offset: 0xC0  System SRAM Parity Error Interrupt Enable Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PERRIEN   |SRAM Parity Check Error Interrupt Enable Bit
+     * |        |          |0 = SRAM parity check error interrupt Disabled.
+     * |        |          |1 = SRAM parity check error interrupt Enabled.
+     * @var SYS_T::SRAMSTS
+     * Offset: 0xC4  System SRAM Parity Check Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PERRIF    |SRAM Parity Check Error Flag
+     * |        |          |This bit indicates the System SRAM parity error occurred. Write 1 to clear this to 0.
+     * |        |          |0 = No System SRAM parity error.
+     * |        |          |1 = System SRAM parity error occur.
+     * @var SYS_T::SRAMEADR
+     * Offset: 0xC8  System SRAM Parity Check Error Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |ERRADDR   |System SRAM Parity Error Address
+     * |        |          |This register shows system SRAM parity error byte address.
+     * @var SYS_T::SRAMPC0
+     * Offset: 0xDC  SRAM Power Mode Control Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |SRAM0PM0  |Bank0 SRAM Power Mode Select 0 (Write Protect)
+     * |        |          |This field can control SRAM bank0 selection 0 (4k) power mode for range 0x2000_0000 - 0x2000_0FFF.
+     * |        |          |00 = Normal mode.
+     * |        |          |01 = Retention mode.
+     * |        |          |10 = Power shut down mode.
+     * |        |          |11 = Reserved (Write Ignore).
+     * |        |          |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note 2: Write ignore when PCBUSY is 1.
+     * |[3:2]   |SRAM0PM1  |Bank0 SRAM Power Mode Select 1 (Write Protect)
+     * |        |          |This field can control SRAM bank0 selection 1 power mode for range 0x2000_1000 - 0x2000_1FFF.
+     * |        |          |00 = Normal mode.
+     * |        |          |01 = Retention mode.
+     * |        |          |10 = Power shut down mode.
+     * |        |          |11 = Reserved (Write Ignore).
+     * |        |          |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note 2: Write ignore when PCBUSY is 1.
+     * |[5:4]   |SRAM0PM2  |Bank0 SRAM Power Mode Select 2 (Write Protect)
+     * |        |          |This field can control SRAM bank0 selection 2 (8k) power mode for range 0x2000_2000 - 0x2000_3FFF.
+     * |        |          |00 = Normal mode.
+     * |        |          |01 = Retention mode.
+     * |        |          |10 = Power shut down mode.
+     * |        |          |11 = Reserved (Write Ignore).
+     * |        |          |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note 2: Write ignore when PCBUSY is 1.
+     * |[7:6]   |SRAM0PM3  |Bank0 SRAM Power Mode Select 3 (Write Protect)
+     * |        |          |This field can control SRAM bank0 selection 3 (8k) power mode for range 0x2000_4000 - 0x2000_5FFF.
+     * |        |          |00 = Normal mode.
+     * |        |          |01 = Retention mode.
+     * |        |          |10 = Power shut down mode.
+     * |        |          |11 = Reserved (Write Ignore).
+     * |        |          |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note 2: Write ignore when PCBUSY is 1.
+     * |[9:8]   |SRAM0PM4  |Bank0 SRAM Power Mode Select 4 (Write Protect)
+     * |        |          |This field can control SRAM0 bank0 selection 4 (8k) power mode for range 0x2000_6000 - 0x2000_7FFF.
+     * |        |          |00 = Normal mode.
+     * |        |          |01 = Retention mode.
+     * |        |          |10 = Power shut down mode.
+     * |        |          |11 = Reserved (Write Ignore).
+     * |        |          |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note 2: Write ignore when PCBUSY is 1.
+     * |[11:10] |SRAM1PM0  |Bank1 SRAM Power Mode Select 0 (Write Protect)
+     * |        |          |This field can control SRAM bank1 selection 0 (16k) power mode for range 0x2000_8000 - 0x2000_BFFF.
+     * |        |          |00 = Normal mode.
+     * |        |          |01 = Retention mode.
+     * |        |          |10 = Power shut down mode.
+     * |        |          |11 = Reserved (Write Ignore).
+     * |        |          |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note 2: Write ignore when PCBUSY is 1.
+     * |[13:12] |SRAM1PM1  |Bank1 SRAM Power Mode Select 1 (Write Protect)
+     * |        |          |This field can control SRAM bank1 selection 1 (16k) power mode for range 0x2000_C000 - 0x2000_FFFF.
+     * |        |          |00 = Normal mode.
+     * |        |          |01 = Retention mode.
+     * |        |          |10 = Power shut down mode.
+     * |        |          |11 = Reserved (Write Ignore).
+     * |        |          |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note 2: Write ignore when PCBUSY is 1.
+     * |[15:14] |SRAM1PM2  |Bank1 SRAM Power Mode Select 2 (Write Protect)
+     * |        |          |This field can control SRAM bank1 selection 2 (16k) power mode for range 0x2001_0000 - 0x2001_3FFF.
+     * |        |          |00 = Normal mode.
+     * |        |          |01 = Retention mode.
+     * |        |          |10 = Power shut down mode.
+     * |        |          |11 = Reserved (Write Ignore).
+     * |        |          |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note 2: Write ignore when PCBUSY is 1.
+     * |[17:16] |SRAM1PM3  |Bank1 SRAM Power Mode Select 3 (Write Protect)
+     * |        |          |This field can control SRAM bank1 selection 3 (16k) power mode for range 0x2001_4000 - 0x2001_7FFF.
+     * |        |          |00 = Normal mode.
+     * |        |          |01 = Retention mode.
+     * |        |          |10 = Power shut down mode.
+     * |        |          |11 = Reserved (Write Ignore).
+     * |        |          |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note 2: Write ignore when PCBUSY is 1.
+     * |[19:18] |SRAM1PM4  |Bank1 SRAM Power Mode Select 4 (Write Protect)
+     * |        |          |This field can control SRAM bank1 selection 4 (16k) power mode for range 0x2001_8000 - 0x2001_BFFF.
+     * |        |          |00 = Normal mode.
+     * |        |          |01 = Retention mode.
+     * |        |          |10 = Power shut down mode.
+     * |        |          |11 = Reserved (Write Ignore).
+     * |        |          |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note 2: Write ignore when PCBUSY is 1.
+     * |[21:20] |SRAM1PM5  |Bank1 SRAM Power Mode Select 5 (Write Protect)
+     * |        |          |This field can control SRAM bank1 selection 5 (16k) power mode for range 0x2001_C000 - 0x2001_FFFF.
+     * |        |          |00 = Normal mode.
+     * |        |          |01 = Retention mode.
+     * |        |          |10 = Power shut down mode.
+     * |        |          |11 = Reserved (Write Ignore).
+     * |        |          |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note 2: Write ignore when PCBUSY is 1.
+     * |[23:22] |SRAM1PM6  |Bank1 SRAM Power Mode Select 6 (Write Protect)
+     * |        |          |This field can control SRAM bank1 selection 6 (16k) power mode for range 0x2002_0000 - 0x2002_3FFF.
+     * |        |          |00 = Normal mode.
+     * |        |          |01 = Retention mode.
+     * |        |          |10 = Power shut down mode.
+     * |        |          |11 = Reserved (Write Ignore).
+     * |        |          |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note 2: Write ignore when PCBUSY is 1.
+     * |[25:24] |SRAM1PM7  |Bank1 SRAM Power Mode Select 7 (Write Protect)
+     * |        |          |This field can control SRAM bank1 selection 7 (16k) power mode for range 0x2002_4000 - 0x2002_7FFF.
+     * |        |          |00 = Normal mode.
+     * |        |          |01 = Retention mode.
+     * |        |          |10 = Power shut down mode.
+     * |        |          |11 = Reserved (Write Ignore).
+     * |        |          |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note 2: Write ignore when PCBUSY is 1.
+     * |[27:26] |SRAM2PM0  |Bank2 SRAM Power Mode Select 0 (Write Protect)
+     * |        |          |This field can control SRAM bank2 selection 0 (16k) power mode for range 0x2002_8000 - 0x2002_BFFF.
+     * |        |          |00 = Normal mode.
+     * |        |          |01 = Retention mode.
+     * |        |          |10 = Power shut down mode.
+     * |        |          |11 = Reserved (Write Ignore).
+     * |        |          |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note 2: Write ignore when PCBUSY is 1.
+     * |[29:28] |SRAM2PM1  |Bank2 SRAM Power Mode Select 1 (Write Protect)
+     * |        |          |This field can control SRAM bank2 selection 1 (16k) power mode for range 0x2002_C000 - 0x2002_FFFF.
+     * |        |          |00 = Normal mode.
+     * |        |          |01 = Retention mode.
+     * |        |          |10 = Power shut down mode.
+     * |        |          |11 = Reserved (Write Ignore).
+     * |        |          |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note 2: Write ignore when PCBUSY is 1.
+     * |[31]    |PCBUSY    |Power Changing Busy Flag (Read Only)
+     * |        |          |This bit indicate SRAM power changing.
+     * |        |          |0 = SRAM power change finish.
+     * |        |          |1 = SRAM power changing.
+     * @var SYS_T::SRAMPC1
+     * Offset: 0xE0  SRAM Power Mode Control Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |SRAM2PM2  |Bank2 SRAM Power Mode Select 2 (Write Protect)
+     * |        |          |This field can control SRAM bank2 selection 2 (16k) power mode for range 0x2003_0000 - 0x2003_3FFF.
+     * |        |          |00 = Normal mode.
+     * |        |          |01 = Retention mode.
+     * |        |          |10 = Power shut down mode.
+     * |        |          |11 = Reserved (Write Ignore).
+     * |        |          |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note 2: Write ignore when PCBUSY is 1.
+     * |[3:2]   |SRAM2PM3  |Bank2 SRAM Power Mode Select 3 (Write Protect)
+     * |        |          |This field can control bank2 sram3 (16k) power mode for range 0x2003_4000 - 0x2003_7FFF.
+     * |        |          |00 = Normal mode.
+     * |        |          |01 = Retention mode.
+     * |        |          |10 = Power shut down mode.
+     * |        |          |11 = Reserved (Write Ignore).
+     * |        |          |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note 2: Write ignore when PCBUSY is 1.
+     * |[5:4]   |SRAM2PM4  |Bank2 SRAM Power Mode Select 4 (Write Protect)
+     * |        |          |This field can control SRAM bank2 selection 4 (16k) power mode for range 0x2003_8000 - 0x2003_BFFF.
+     * |        |          |00 = Normal mode.
+     * |        |          |01 = Retention mode.
+     * |        |          |10 = Power shut down mode.
+     * |        |          |11 = Reserved (Write Ignore).
+     * |        |          |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note 2: Write ignore when PCBUSY is 1.
+     * |[7:6]   |SRAM2PM5  |Bank2 SRAM Power Mode Select 5 (Write Protect)
+     * |        |          |This field can control SRAM bank2 selection 5 (16k) power mode for range 0x2003_C000 - 0x2003_FFFF.
+     * |        |          |00 = Normal mode.
+     * |        |          |01 = Retention mode.
+     * |        |          |10 = Power shut down mode.
+     * |        |          |11 = Reserved (Write Ignore).
+     * |        |          |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note 2: Write ignore when PCBUSY is 1.
+     * |[17:16] |CAN       |CAN SRAM Power Mode Select (Write Protect)
+     * |        |          |This field can control CAN sram power mode.
+     * |        |          |00 = Normal mode.
+     * |        |          |01 = Retention mode.
+     * |        |          |10 = Power shut down mode.
+     * |        |          |11 = Reserved.
+     * |        |          |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note 2: Write ignore when PCBUSY is 1.
+     * |[19:18] |USBD      |USB Device SRAM Power Mode Select (Write Protect)
+     * |        |          |This field can control USB device sram power mode.
+     * |        |          |00 = Normal mode.
+     * |        |          |01 = Retention mode.
+     * |        |          |10 = Power shut down mode.
+     * |        |          |11 = Reserved (Write Ignore).
+     * |        |          |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note 2: Write ignore when PCBUSY is 1.
+     * |[21:20] |PDMA0     |PDMA SRAM Power Mode Select (Write Protect)
+     * |        |          |This field can control PDMA0 (always secure) sram power mode.
+     * |        |          |00 = Normal mode.
+     * |        |          |01 = Retention mode.
+     * |        |          |10 = Power shut down mode.
+     * |        |          |11 = Reserved (Write Ignore).
+     * |        |          |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note 2: Write ignore when PCBUSY is 1.
+     * |[23:22] |PDMA1     |PDMA SRAM Power Mode Select (Write Protect)
+     * |        |          |This field can control PDMA1 sram power mode.
+     * |        |          |00 = Normal mode.
+     * |        |          |01 = Retention mode.
+     * |        |          |10 = Power shut down mode.
+     * |        |          |11 = Reserved (Write Ignore).
+     * |        |          |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note 2: Write ignore when PCBUSY is 1.
+     * |[25:24] |FMCCACHE  |FMC Cache SRAM Power Mode Select (Write Protect)
+     * |        |          |This field can control FMC cache sram power mode.
+     * |        |          |00 = Normal mode.
+     * |        |          |01 = Retention mode.
+     * |        |          |10 = Power shut down mode.
+     * |        |          |11 = Reserved (Write Ignore).
+     * |        |          |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note 2: Write ignore when PCBUSY is 1.
+     * |[27:26] |RSA       |RSA SRAM Power Mode Select (Write Protect)
+     * |        |          |This field can control RSA sram power mode.
+     * |        |          |00 = Normal mode.
+     * |        |          |01 = Retention mode.
+     * |        |          |10 = Power shut down mode.
+     * |        |          |11 = Reserved (Write Ignore).
+     * |        |          |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note 2: Write ignore when PCBUSY is 1.
+     * |        |          |Note 3: If CRPTPWREN of SYS_PSWCTL is set to 1, RSA SRAM is auto set to normal mode by hardware.
+     * |[29:28] |KS        |Key Store SRAM Power Mode Select (Write Protect)
+     * |        |          |This field can control Key Store sram power mode.
+     * |        |          |00 = Normal mode.
+     * |        |          |01 = Retention mode.
+     * |        |          |10 = Power shut down mode.
+     * |        |          |11 = Reserved (Write Ignore).
+     * |        |          |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note 2: Write ignore when PCBUSY is 1.
+     * |[31]    |PCBUSY    |Power Changing Busy Flag (Read Only)
+     * |        |          |This bit indicate SRAM power changing.
+     * |        |          |0 = SRAM power change finish.
+     * |        |          |1 = SRAM power changing.
+     * @var SYS_T::TCTL48M
+     * Offset: 0xE4  HIRC 48M Trim Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |FREQSEL   |Trim Frequency Selection
+     * |        |          |This field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC48) auto trim.
+     * |        |          |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
+     * |        |          |00 = Disable HIRC auto trim function.
+     * |        |          |01 = Enable HIRC auto trim function and trim HIRC to 48 MHz.
+     * |        |          |10 = Reserved.
+     * |        |          |11 = Reserved.
+     * |[5:4]   |LOOPSEL   |Trim Calculation Loop Selection
+     * |        |          |This field defines that trim value calculation is based on how many reference clocks.
+     * |        |          |00 = Trim value calculation is based on average difference in 4 clocks of reference clock.
+     * |        |          |01 = Trim value calculation is based on average difference in 8 clocks of reference clock.
+     * |        |          |10 = Trim value calculation is based on average difference in 16 clocks of reference clock.
+     * |        |          |11 = Trim value calculation is based on average difference in 32 clocks of reference clock.
+     * |        |          |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
+     * |[7:6]   |RETRYCNT  |Trim Value Update Limitation Count
+     * |        |          |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.
+     * |        |          |Once the HIRC locked, the internal trim value update counter will be reset.
+     * |        |          |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
+     * |        |          |00 = Trim retry count limitation is 64 loops.
+     * |        |          |01 = Trim retry count limitation is 128 loops.
+     * |        |          |10 = Trim retry count limitation is 256 loops.
+     * |        |          |11 = Trim retry count limitation is 512 loops.
+     * |[9]     |BOUNDEN   |Boundary Enable Bit
+     * |        |          |0 = Boundary function is disable.
+     * |        |          |1 = Boundary function is enable.
+     * |[8]     |CESTOPEN  |Clock Error Stop Enable Bit
+     * |        |          |0 = The trim operation is keep going if clock is inaccuracy.
+     * |        |          |1 = The trim operation is stopped if clock is inaccuracy.
+     * |[10]    |REFCKSEL  |Reference Clock Selection
+     * |        |          |0 = HIRC trim 48M reference clock is from external 32.768 kHz crystal oscillator.
+     * |        |          |1 = HIRC trim 48M reference clock is from internal USB synchronous mode.
+     * |[20:16] |BOUNDARY  |Boundary Selection
+     * |        |          |Fill the boundary range from 0x1 to 0x31, 0x0 is reserved.
+     * |        |          |Note: This field is effective only when the BOUNDEN(SYS_TCTL48M [9]) is enable.
+     * @var SYS_T::TIEN48M
+     * Offset: 0xE8  HIRC 48M Trim Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1]     |TFAILIEN  |Trim Failure Interrupt Enable Bit
+     * |        |          |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_TCTL48M[1:0]).
+     * |        |          |If this bit is high and TFAILIF(SYS_TISTS48M[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
+     * |        |          |0 = Disable TFAILIF(SYS_TISTS48M[1]) status to trigger an interrupt to CPU.
+     * |        |          |1 = Enable TFAILIF(SYS_TISTS48MM[1]) status to trigger an interrupt to CPU.
+     * |[2]     |CLKEIEN   |Clock Error Interrupt Enable Bit
+     * |        |          |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.
+     * |        |          |If this bit is set to1, and CLKERRIF(SYS_TISTS48M[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
+     * |        |          |0 = Disable CLKERRIF(SYS_TISTS48M[2]) status to trigger an interrupt to CPU.
+     * |        |          |1 = Enable CLKERRIF(SYS_TISTS48M[2]) status to trigger an interrupt to CPU.
+     * @var SYS_T::TISTS48M
+     * Offset: 0xEC  HIRC 48M Trim Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |FREQLOCK  |HIRC Frequency Lock Status
+     * |        |          |This bit indicates the HIRC frequency is locked.
+     * |        |          |This is a status bit and doesn't trigger any interrupt.
+     * |        |          |Write 1 to clear this to 0.
+     * |        |          |This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled.
+     * |        |          |0 = The internal high-speed oscillator frequency doesn't lock at 48 MHz yet.
+     * |        |          |1 = The internal high-speed oscillator frequency locked at 48 MHz.
+     * |[1]     |TFAILIF   |Trim Failure Interrupt Status
+     * |        |          |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked.
+     * |        |          |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_TCTL48M[1:0]) will be cleared to 00 by hardware automatically.
+     * |        |          |If this bit is set and TFAILIEN(SYS_TIEN48M[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
+     * |        |          |Write 1 to clear this to 0.
+     * |        |          |0 = Trim value update limitation count does not reach.
+     * |        |          |1 = Trim value update limitation count reached and HIRC frequency still not locked.
+     * |[2]     |CLKERRIF  |Clock Error Interrupt Status
+     * |        |          |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48MHz internal high speed RC oscillator (HIRC48) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy
+     * |        |          |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_TICTL48M[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_TCTL48M[8]) is set to 1.
+     * |        |          |If this bit is set and CLKEIEN(SYS_TIEN48M[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy.
+     * |        |          |Write 1 to clear this to 0.
+     * |        |          |0 = Clock frequency is accuracy.
+     * |        |          |1 = Clock frequency is inaccuracy.
+     * |[3]     |OVBDIF    |Over Boundary Status
+     * |        |          |When the over boundary function is set, if there occurs the over boundary condition, this flag will be set.
+     * |        |          |0 = Over boundary condition did not occur.
+     * |        |          |1 = Over boundary condition occurred.
+     * |        |          |Note: Write 1 to clear this flag.
+     * @var SYS_T::TCTL12M
+     * Offset: 0xF0  HIRC 12M Trim Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |FREQSEL   |Trim Frequency Selection
+     * |        |          |This field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC) auto trim.
+     * |        |          |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
+     * |        |          |00 = Disable HIRC auto trim function.
+     * |        |          |01 = Enable HIRC auto trim function and trim HIRC to 12 MHz.
+     * |        |          |10 = Reserved.
+     * |        |          |11 = Reserved.
+     * |[5:4]   |LOOPSEL   |Trim Calculation Loop Selection
+     * |        |          |This field defines that trim value calculation is based on how many reference clocks.
+     * |        |          |00 = Trim value calculation is based on average difference in 4 clocks of reference clock.
+     * |        |          |01 = Trim value calculation is based on average difference in 8 clocks of reference clock.
+     * |        |          |10 = Trim value calculation is based on average difference in 16 clocks of reference clock.
+     * |        |          |11 = Trim value calculation is based on average difference in 32 clocks of reference clock.
+     * |        |          |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
+     * |[7:6]   |RETRYCNT  |Trim Value Update Limitation Count
+     * |        |          |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.
+     * |        |          |Once the HIRC locked, the internal trim value update counter will be reset.
+     * |        |          |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
+     * |        |          |00 = Trim retry count limitation is 64 loops.
+     * |        |          |01 = Trim retry count limitation is 128 loops.
+     * |        |          |10 = Trim retry count limitation is 256 loops.
+     * |        |          |11 = Trim retry count limitation is 512 loops.
+     * |[9]     |BOUNDEN   |Boundary Enable Bit
+     * |        |          |0 = Boundary function is disable.
+     * |        |          |1 = Boundary function is enable.
+     * |[8]     |CESTOPEN  |Clock Error Stop Enable Bit
+     * |        |          |0 = The trim operation is keep going if clock is inaccuracy.
+     * |        |          |1 = The trim operation is stopped if clock is inaccuracy.
+     * |[10]    |REFCKSEL  |Reference Clock Selection
+     * |        |          |0 = HIRC trim reference clock is from external 32.768 kHz crystal oscillator.
+     * |        |          |1 = HIRC trim reference clock is from internal USB synchronous mode.
+     * |[20:16] |BOUNDARY  |Boundary Selection
+     * |        |          |Fill the boundary range from 0x1 to 0x31, 0x0 is reserved.
+     * |        |          |Note: This field is effective only when the BOUNDEN(SYS_TCTL12M[9]) is enabled.
+     * @var SYS_T::TIEN12M
+     * Offset: 0xF4  HIRC 12M Trim Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1]     |TFAILIEN  |Trim Failure Interrupt Enable Bit
+     * |        |          |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_TCTL12M[1:0]).
+     * |        |          |If this bit is high and TFAILIF(SYS_TISTS12M[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
+     * |        |          |0 = Disable TFAILIF(SYS_TISTS12M[1]) status to trigger an interrupt to CPU.
+     * |        |          |1 = Enable TFAILIF(SYS_TISTS12M[1]) status to trigger an interrupt to CPU.
+     * |[2]     |CLKEIEN   |Clock Error Interrupt Enable Bit
+     * |        |          |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.
+     * |        |          |If this bit is set to1, and CLKERRIF(SYS_TISTS12M[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
+     * |        |          |0 = Disable CLKERRIF(SYS_TISTS12M[2]) status to trigger an interrupt to CPU.
+     * |        |          |1 = Enable CLKERRIF(SYS_TISTS12M[2]) status to trigger an interrupt to CPU.
+     * @var SYS_T::TISTS12M
+     * Offset: 0xF8  HIRC 12M Trim Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |FREQLOCK  |HIRC Frequency Lock Status
+     * |        |          |This bit indicates the HIRC frequency is locked.
+     * |        |          |This is a status bit and doesn't trigger any interrupt.
+     * |        |          |Write 1 to clear this to 0.
+     * |        |          |This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled.
+     * |        |          |0 = The internal high-speed oscillator frequency doesn't lock at 12 MHz yet.
+     * |        |          |1 = The internal high-speed oscillator frequency locked at 12 MHz.
+     * |[1]     |TFAILIF   |Trim Failure Interrupt Status
+     * |        |          |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked.
+     * |        |          |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_TCTL12M[1:0]) will be cleared to 00 by hardware automatically.
+     * |        |          |If this bit is set and TFAILIEN(SYS_TIEN12M[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
+     * |        |          |Write 1 to clear this to 0.
+     * |        |          |0 = Trim value update limitation count does not reach.
+     * |        |          |1 = Trim value update limitation count reached and HIRC frequency still not locked.
+     * |[2]     |CLKERRIF  |Clock Error Interrupt Status
+     * |        |          |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 12MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy
+     * |        |          |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_TICTL12M[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_TCTL12M[8]) is set to 1.
+     * |        |          |If this bit is set and CLKEIEN(SYS_TIEN12M[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy.
+     * |        |          |Write 1 to clear this to 0.
+     * |        |          |0 = Clock frequency is accuracy.
+     * |        |          |1 = Clock frequency is inaccuracy.
+     * |[3]     |OVBDIF    |Over Boundary Status
+     * |        |          |When the over boundary function is set, if there occurs the over boundary condition, this flag will be set.
+     * |        |          |0 = Over boundary condition did not occur.
+     * |        |          |1 = Over boundary condition occurred.
+     * |        |          |Note: Write 1 to clear this flag.
+     * @var SYS_T::REGLCTL
+     * Offset: 0x100  Register Lock Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |REGLCTL   |Register Lock Control Code (Write Only)
+     * |        |          |Some registers have write-protection function
+     * |        |          |Writing these registers have to disable the protected function by writing the sequence value 59h, 16h, 88h to this field.
+     * |        |          |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.
+     * |[0]     |REGLCTL[0]|Register Lock Control Disable Index (Read Only)
+     * |        |          |0 = Write-protection Enabled for writing protected registers.
+     * |        |          |Any write to the protected register is ignored.
+     * |        |          |1 = Write-protection Disabled for writing protected registers.
+     * @var SYS_T::CPUCFG
+     * Offset: 0x1D8  CPU General Configuration Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |INTRTEN   |CPU Interrupt Realtime Enable Bit
+     * |        |          |When this bit is 0, the latency of CPU entering interrupt service routine (ISR) will be various but shorter.
+     * |        |          |When this bit is 1, the latency of CPU entering ISR will be kept constant.
+     * |        |          |0 = CPU Interrupt Realtime Disabled.
+     * |        |          |1 = CPU Interrupt Realtime Enabled.
+     * @var SYS_T::PORCTL1
+     * Offset: 0x1EC  Power-on Reset Controller Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |POROFF    |Power-on Reset Enable Bit (Write Protect)
+     * |        |          |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again.
+     * |        |          |User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
+     * |        |          |The POR function will be active again when  this field is set to another value or chip is reset by other reset source, including:
+     * |        |          |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function.
+     * |        |          |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * @var SYS_T::PSWCTL
+     * Offset: 0x1F4  Power Switch Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[12]    |CRPTPWREN |Cryptographic Accelerator Power Switch Enable Bit (Write Protect)
+     * |        |          |0 = Cryptographic accelerator power supply Disabled.
+     * |        |          |1 = Cryptographic accelerator power supply Enabled.
+     * |        |          |Note 1: If this bit is set 1, RSA of SYS_SRAMPC1 is set to normal mode by hardware.
+     * |        |          |Note 2: Write ignored when PCBUSY(SYS_SRAMPC1[31]) is 1.
+     * |        |          |Note 3: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * @var SYS_T::PLCTL
+     * Offset: 0x1F8  Power Level Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |PLSEL     |Power Level Select (Write Protect)
+     * |        |          |00 = Set to Power level 0 (PL0). Support system clock up to 96MHz.
+     * |        |          |01 = Set to Power level 1 (PL1). Support system clock up to 84MHz.
+     * |        |          |10 = Set to Power level 2 (PL2). Support system clock up to 64MHz.
+     * |        |          |11 = Set to Power level 3 (PL3). Support system clock up to 4MHz.
+     * |        |          |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note 2: These bits not be reset when wake-up from Standby Power-down mode(SPD).
+     * |[4]     |MVRS      |Main Voltage Regulator Type Select (Write Protect)
+     * |        |          |This bit filed sets main voltage regulator type.
+     * |        |          |After setting main voltage regulator type to DCDC (MVRS (SYS_PLCTL[4]) = 1) system will set main voltage regulator type change busy flag MVRCBUSY(SYS_PLSTS[1]), detect inductor connection and update inductor connection status LCONS (SYS_PLSTS[3]).
+     * |        |          |If inductor exist LCONS will be cleared and main voltage regulator type can switch to DCDC (CURMVRS (SYS_PLSTS[12])=1).
+     * |        |          |0 = Set main voltage regulator to LDO.
+     * |        |          |1 = Set main voltage regulator to DCDC.
+     * |        |          |Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note 2: This bit not be reset when wake-up from Standby Power-down mode(SPD).
+     * |[7]     |WRBUSY    |Write Busy Flag
+     * |        |          |If SYS_PLCTL be written, this bit be asserted automatic by hardware, and be de-asserted when write procedure finish.
+     * |        |          |0 = SYS_PLCTL register is ready for write operation.
+     * |        |          |1 = SYS_PLCTL register is busy on the last write operation. Other write operations are ignored.
+     * |[21:16] |LVSSTEP   |LDO Voltage Scaling Step (Write Protect)
+     * |        |          |The LVSSTEP value is LDO voltage rising step.
+     * |        |          |LDO voltage scaling step = (LVSSTEP + 1) * 10mV.
+     * |        |          |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * |[31:24] |LVSPRD    |LDO Voltage Scaling Period (Write Protect)
+     * |        |          |The LVSPRD value is the period of each LDO voltage rising step.
+     * |        |          |LDO voltage scaling period = (LVSPRD + 1) * 1us.
+     * |        |          |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
+     * @var SYS_T::PLSTS
+     * Offset: 0x1FC  Power Level Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PLCBUSY   |Power Level Change Busy Bit (Read Only)
+     * |        |          |This bit is set by hardware when power level is changing.
+     * |        |          |After power level change is completed, this bit will be cleared automatically by hardware.
+     * |        |          |0 = Power level change is completed.
+     * |        |          |1 = Power level change is ongoing.
+     * |[1]     |MVRCBUSY  |Main Voltage Regulator Type Change Busy Bit (Read Only)
+     * |        |          |This bit is set by hardware when main voltage regulator type is changing.
+     * |        |          |After main voltage regulator type change is completed, this bit will be cleared automatically by hardware.
+     * |        |          |0 = Main voltage regulator type change is completed.
+     * |        |          |1 = Main voltage regulator type change is ongoing.
+     * |[2]     |MVRCERR   |Main Voltage Regulator Type Change Error Bit (Write Protect)
+     * |        |          |This bit is set to 1 when main voltage regulator type change from LDO to DCDC error, the following conditions will cause change errors:
+     * |        |          |1.System change to DC-DC mode but LDO change voltage process not finish.
+     * |        |          |2.Detect inductor fail.
+     * |        |          |Read:
+     * |        |          |0 = No main voltage regulator type change error.
+     * |        |          |1 = Main voltage regulator type change to DCDC error occurred.
+     * |        |          |Write:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clears MVRCERR to 0.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[3]     |LCONS     |Inductor for DC-DC Connect Status (Read Only)
+     * |        |          |0 = Inductor connect between Vsw and LDO_CAP pin.
+     * |        |          |This bit is valid when current main voltage regulator type is DCDC (CURMVRS (SYS_PLSTS[12])=1).
+     * |        |          |If current main voltage regulator type is LDO (CURMVRS (SYS_PLSTS[12])=0), this bit is set to 1.
+     * |        |          |0 = Inductor connect between Vsw and LDO_CAP pin.
+     * |        |          |1 = No Inductor connect between Vsw and LDO_CAP pin.
+     * |        |          |Note: This bit is 1 when main voltage regulator is LDO.
+     * |[9:8]   |PLSTATUS  |Power Level Status (Read Only)
+     * |        |          |This bit field reflect the current power level.
+     * |        |          |00 = Power level is PL0. Support system clock up to 96MHz.
+     * |        |          |01 = Power level is PL1. Support system clock up to 84MHz.
+     * |        |          |10 = Power level is PL2. Support system clock up to 48MHz.
+     * |        |          |11 = Power level is PL3. Support system clock up to 4MHz.
+     * |[12]    |CURMVR    |Current Main Voltage Regulator Type (Read Only)
+     * |        |          |This bit field reflects current main voltage regulator type.
+     * |        |          |0 = Current main voltage regulator in active and Idle mode is LDO.
+     * |        |          |1 = Current main voltage regulator in active and Idle mode is DCDC.
+     * @var SYS_T::AHBMCTL
+     * Offset: 0x400  AHB Bus Matrix Priority Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |INTACTEN  |Highest AHB Bus Priority of Cortex-M23 Core Enable Bit (Write Protect)
+     * |        |          |Enable Cortex-M23 core with highest AHB bus priority in AHB bus matrix.
+     * |        |          |0 = Run robin mode.
+     * |        |          |1 = Cortex-M23 CPU with highest bus priority when interrupt occurs.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     */
+
+    __I  uint32_t PDID;                  /*!< [0x0000] Part Device Identification Number Register                       */
+    __IO uint32_t RSTSTS;                /*!< [0x0004] System Reset Status Register                                     */
+    __IO uint32_t IPRST0;                /*!< [0x0008] Peripheral  Reset Control Register 0                             */
+    __IO uint32_t IPRST1;                /*!< [0x000c] Peripheral Reset Control Register 1                              */
+    __IO uint32_t IPRST2;                /*!< [0x0010] Peripheral Reset Control Register 2                              */
+    __I  uint32_t RESERVE0[1];
+    __IO uint32_t BODCTL;                /*!< [0x0018] Brown-out Detector Control Register                              */
+    __IO uint32_t IVSCTL;                /*!< [0x001c] Internal Voltage Source Control Register                         */
+    __I  uint32_t RESERVE1[1];
+    __IO uint32_t PORCTL0;               /*!< [0x0024] Power-on Reset Controller Register 0                             */
+    __IO uint32_t VREFCTL;               /*!< [0x0028] VREF Control Register                                            */
+    __IO uint32_t USBPHY;                /*!< [0x002C] USB PHY Control Register                                         */
+    __IO uint32_t GPA_MFPL;              /*!< [0x0030] GPIOA Low Byte Multiple Function Control Register                */
+    __IO uint32_t GPA_MFPH;              /*!< [0x0034] GPIOA High Byte Multiple Function Control Register               */
+    __IO uint32_t GPB_MFPL;              /*!< [0x0038] GPIOB Low Byte Multiple Function Control Register                */
+    __IO uint32_t GPB_MFPH;              /*!< [0x003c] GPIOB High Byte Multiple Function Control Register               */
+    __IO uint32_t GPC_MFPL;              /*!< [0x0040] GPIOC Low Byte Multiple Function Control Register                */
+    __IO uint32_t GPC_MFPH;              /*!< [0x0044] GPIOC High Byte Multiple Function Control Register               */
+    __IO uint32_t GPD_MFPL;              /*!< [0x0048] GPIOD Low Byte Multiple Function Control Register                */
+    __IO uint32_t GPD_MFPH;              /*!< [0x004c] GPIOD High Byte Multiple Function Control Register               */
+    __IO uint32_t GPE_MFPL;              /*!< [0x0050] GPIOE Low Byte Multiple Function Control Register                */
+    __IO uint32_t GPE_MFPH;              /*!< [0x0054] GPIOE High Byte Multiple Function Control Register               */
+    __IO uint32_t GPF_MFPL;              /*!< [0x0058] GPIOF Low Byte Multiple Function Control Register                */
+    __IO uint32_t GPF_MFPH;              /*!< [0x005C] GPIOF High Byte Multiple Function Control Register               */
+    __IO uint32_t GPG_MFPL;              /*!< [0x0060] GPIOG Low Byte Multiple Function Control Register                */
+    __IO uint32_t GPG_MFPH;              /*!< [0x0064] GPIOG High Byte Multiple Function Control Register               */
+    __IO uint32_t GPH_MFPL;              /*!< [0x0068] GPIOH Low Byte Multiple Function Control Register                */
+    __IO uint32_t GPH_MFPH;              /*!< [0x006C] GPIOH High Byte Multiple Function Control Register               */
+    __I  uint32_t RESERVE2[4];
+    __IO uint32_t GPA_MFOS;              /*!< [0x0080] GPIOA Multiple Function Output Select Register                   */
+    __IO uint32_t GPB_MFOS;              /*!< [0x0084] GPIOB Multiple Function Output Select Register                   */
+    __IO uint32_t GPC_MFOS;              /*!< [0x0088] GPIOC Multiple Function Output Select Register                   */
+    __IO uint32_t GPD_MFOS;              /*!< [0x008c] GPIOD Multiple Function Output Select Register                   */
+    __IO uint32_t GPE_MFOS;              /*!< [0x0090] GPIOE Multiple Function Output Select Register                   */
+    __IO uint32_t GPF_MFOS;              /*!< [0x0094] GPIOF Multiple Function Output Select Register                   */
+    __IO uint32_t GPG_MFOS;              /*!< [0x0098] GPIOG Multiple Function Output Select Register                   */
+    __IO uint32_t GPH_MFOS;              /*!< [0x009c] GPIOH Multiple Function Output Select Register                   */
+    __IO uint32_t VTORSET;               /*!< [0x00A0] VTOR Setting Register                                            */
+    __I  uint32_t RESERVE3[7];
+    __IO uint32_t SRAMICTL;              /*!< [0x00C0] System SRAM Interrupt Enable Control Register                    */
+    __I  uint32_t SRAMSTS;               /*!< [0x00C4] System SRAM Parity Error Status Register                         */
+    __I  uint32_t SRAMEADR;              /*!< [0x00C8] System SRAM Parity Check Error Address Register                  */
+    __IO uint32_t RESERVE4[4];
+    __IO uint32_t SRAMPC0;               /*!< [0x00DC] SRAM Power Mode Control Register 0                               */
+    __IO uint32_t SRAMPC1;               /*!< [0x00E0] SRAM Power Mode Control Register 1                               */
+    __IO uint32_t TCTL48M;               /*!< [0x00E4] HIRC 48M Trim Control Register                                   */
+    __IO uint32_t TIEN48M;               /*!< [0x00E8] HIRC 48M Trim Interrupt Enable Register                          */
+    __IO uint32_t TISTS48M;              /*!< [0x00EC] HIRC 48M Trim Interrupt Status Register                          */
+    __IO uint32_t TCTL12M;               /*!< [0x00F0] HIRC 12M Trim Control Register                                   */
+    __IO uint32_t TIEN12M;               /*!< [0x00F4] HIRC 12M Trim Interrupt Enable Register                          */
+    __IO uint32_t TISTS12M;              /*!< [0x00F8] HIRC 12M Trim Interrupt Status Register                          */
+    __I  uint32_t RESERVE6[1];
+    __IO uint32_t REGLCTL;               /*!< [0x0100] Register Lock Control Register                                   */
+    __I  uint32_t RESERVE7[53];
+    __IO uint32_t CPUCFG;                /*!< [0x01D8] CPU General Configuration Register                               */
+    __IO uint32_t BATLDCTL;              /*!< [0x01DC] Battery Loss Detector Control Register                           */
+    __IO uint32_t OVDCTL;                /*!< [0x01E0] Over Voltage Detector Control Register                           */
+    __I  uint32_t RESERVE8[2];
+    __IO uint32_t PORCTL1;               /*!< [0x01EC] Power-on Reset Controller Register 1                             */
+    __I  uint32_t RESERVE9[1];
+    __IO uint32_t PSWCTL;                /*!< [0x01F4] Power Switch Control Register                                    */
+    __IO uint32_t PLCTL;                 /*!< [0x01F8] Power Level Control Register                                     */
+    __IO uint32_t PLSTS;                 /*!< [0x01FC] Power Level Status Register                                      */
+    __I  uint32_t RESERVE10[128];
+    __IO uint32_t AHBMCTL;               /*!< [0x0400] AHB Bus Matrix Priority Control Register                         */
+
+
+} SYS_T;
+
+/**
+    @addtogroup SYS_CONST SYS Bit Field Definition
+    Constant Definitions for SYS Controller
+  @{
+*/
+
+#define SYS_PDID_PDID_Pos                (0)                                               /*!< SYS_T::PDID: PDID Position             */
+#define SYS_PDID_PDID_Msk                (0xfffffffful << SYS_PDID_PDID_Pos)               /*!< SYS_T::PDID: PDID Mask                 */
+
+#define SYS_RSTSTS_PORF_Pos              (0)                                               /*!< SYS_T::RSTSTS: PORF Position           */
+#define SYS_RSTSTS_PORF_Msk              (0x1ul << SYS_RSTSTS_PORF_Pos)                    /*!< SYS_T::RSTSTS: PORF Mask               */
+
+#define SYS_RSTSTS_PINRF_Pos             (1)                                               /*!< SYS_T::RSTSTS: PINRF Position          */
+#define SYS_RSTSTS_PINRF_Msk             (0x1ul << SYS_RSTSTS_PINRF_Pos)                   /*!< SYS_T::RSTSTS: PINRF Mask              */
+
+#define SYS_RSTSTS_WDTRF_Pos             (2)                                               /*!< SYS_T::RSTSTS: WDTRF Position          */
+#define SYS_RSTSTS_WDTRF_Msk             (0x1ul << SYS_RSTSTS_WDTRF_Pos)                   /*!< SYS_T::RSTSTS: WDTRF Mask              */
+
+#define SYS_RSTSTS_LVRF_Pos              (3)                                               /*!< SYS_T::RSTSTS: LVRF Position           */
+#define SYS_RSTSTS_LVRF_Msk              (0x1ul << SYS_RSTSTS_LVRF_Pos)                    /*!< SYS_T::RSTSTS: LVRF Mask               */
+
+#define SYS_RSTSTS_BODRF_Pos             (4)                                               /*!< SYS_T::RSTSTS: BODRF Position          */
+#define SYS_RSTSTS_BODRF_Msk             (0x1ul << SYS_RSTSTS_BODRF_Pos)                   /*!< SYS_T::RSTSTS: BODRF Mask              */
+
+#define SYS_RSTSTS_SYSRF_Pos             (5)                                               /*!< SYS_T::RSTSTS: SYSRF Position          */
+#define SYS_RSTSTS_SYSRF_Msk             (0x1ul << SYS_RSTSTS_SYSRF_Pos)                   /*!< SYS_T::RSTSTS: SYSRF Mask              */
+
+#define SYS_RSTSTS_CPURF_Pos             (7)                                               /*!< SYS_T::RSTSTS: CPURF Position          */
+#define SYS_RSTSTS_CPURF_Msk             (0x1ul << SYS_RSTSTS_CPURF_Pos)                   /*!< SYS_T::RSTSTS: CPURF Mask              */
+
+#define SYS_RSTSTS_CPULKRF_Pos           (8)                                               /*!< SYS_T::RSTSTS: CPULKRF Position        */
+#define SYS_RSTSTS_CPULKRF_Msk           (0x1ul << SYS_RSTSTS_CPULKRF_Pos)                 /*!< SYS_T::RSTSTS: CPULKRF Mask            */
+
+#define SYS_IPRST0_CHIPRST_Pos           (0)                                               /*!< SYS_T::IPRST0: CHIPRST Position        */
+#define SYS_IPRST0_CHIPRST_Msk           (0x1ul << SYS_IPRST0_CHIPRST_Pos)                 /*!< SYS_T::IPRST0: CHIPRST Mask            */
+
+#define SYS_IPRST0_CPURST_Pos            (1)                                               /*!< SYS_T::IPRST0: CPURST Position         */
+#define SYS_IPRST0_CPURST_Msk            (0x1ul << SYS_IPRST0_CPURST_Pos)                  /*!< SYS_T::IPRST0: CPURST Mask             */
+
+#define SYS_IPRST0_PDMA0RST_Pos          (2)                                               /*!< SYS_T::IPRST0: PDMA0RST Position       */
+#define SYS_IPRST0_PDMA0RST_Msk          (0x1ul << SYS_IPRST0_PDMA0RST_Pos)                /*!< SYS_T::IPRST0: PDMA0RST Mask           */
+
+#define SYS_IPRST0_EBIRST_Pos            (3)                                               /*!< SYS_T::IPRST0: EBIRST Position         */
+#define SYS_IPRST0_EBIRST_Msk            (0x1ul << SYS_IPRST0_EBIRST_Pos)                  /*!< SYS_T::IPRST0: EBIRST Mask             */
+
+#define SYS_IPRST0_USBHRST_Pos           (4)                                               /*!< SYS_T::IPRST0: USBHRST Position        */
+#define SYS_IPRST0_USBHRST_Msk           (0x1ul << SYS_IPRST0_USBHRST_Pos)                 /*!< SYS_T::IPRST0: USBHRST Mask            */
+
+#define SYS_IPRST0_SDH0RST_Pos           (6)                                               /*!< SYS_T::IPRST0: SDH0RST Position        */
+#define SYS_IPRST0_SDH0RST_Msk           (0x1ul << SYS_IPRST0_SDH0RST_Pos)                 /*!< SYS_T::IPRST0: SDH0RST Mask            */
+
+#define SYS_IPRST0_CRCRST_Pos            (7)                                               /*!< SYS_T::IPRST0: CRCRST Position         */
+#define SYS_IPRST0_CRCRST_Msk            (0x1ul << SYS_IPRST0_CRCRST_Pos)                  /*!< SYS_T::IPRST0: CRCRST Mask             */
+
+#define SYS_IPRST0_CRPTRST_Pos           (12)                                              /*!< SYS_T::IPRST0: CRPTRST Position        */
+#define SYS_IPRST0_CRPTRST_Msk           (0x1ul << SYS_IPRST0_CRPTRST_Pos)                 /*!< SYS_T::IPRST0: CRPTRST Mask            */
+
+#define SYS_IPRST0_KSRST_Pos             (13)                                              /*!< SYS_T::IPRST0: KSRST Position          */
+#define SYS_IPRST0_KSRST_Msk             (0x1ul << SYS_IPRST0_KSRST_Pos)                   /*!< SYS_T::IPRST0: KSRST Mask              */
+
+#define SYS_IPRST0_PDMA1RST_Pos          (29)                                              /*!< SYS_T::IPRST0: PDMA1RST Position       */
+#define SYS_IPRST0_PDMA1RST_Msk          (0x1ul << SYS_IPRST0_PDMA1RST_Pos)                /*!< SYS_T::IPRST0: PDMA1RST Mask           */
+
+#define SYS_IPRST1_GPIORST_Pos           (1)                                               /*!< SYS_T::IPRST1: GPIORST Position        */
+#define SYS_IPRST1_GPIORST_Msk           (0x1ul << SYS_IPRST1_GPIORST_Pos)                 /*!< SYS_T::IPRST1: GPIORST Mask            */
+
+#define SYS_IPRST1_TMR0RST_Pos           (2)                                               /*!< SYS_T::IPRST1: TMR0RST Position        */
+#define SYS_IPRST1_TMR0RST_Msk           (0x1ul << SYS_IPRST1_TMR0RST_Pos)                 /*!< SYS_T::IPRST1: TMR0RST Mask            */
+
+#define SYS_IPRST1_TMR1RST_Pos           (3)                                               /*!< SYS_T::IPRST1: TMR1RST Position        */
+#define SYS_IPRST1_TMR1RST_Msk           (0x1ul << SYS_IPRST1_TMR1RST_Pos)                 /*!< SYS_T::IPRST1: TMR1RST Mask            */
+
+#define SYS_IPRST1_TMR2RST_Pos           (4)                                               /*!< SYS_T::IPRST1: TMR2RST Position        */
+#define SYS_IPRST1_TMR2RST_Msk           (0x1ul << SYS_IPRST1_TMR2RST_Pos)                 /*!< SYS_T::IPRST1: TMR2RST Mask            */
+
+#define SYS_IPRST1_TMR3RST_Pos           (5)                                               /*!< SYS_T::IPRST1: TMR3RST Position        */
+#define SYS_IPRST1_TMR3RST_Msk           (0x1ul << SYS_IPRST1_TMR3RST_Pos)                 /*!< SYS_T::IPRST1: TMR3RST Mask            */
+
+#define SYS_IPRST1_ACMP01RST_Pos         (7)                                               /*!< SYS_T::IPRST1: ACMP01RST Position      */
+#define SYS_IPRST1_ACMP01RST_Msk         (0x1ul << SYS_IPRST1_ACMP01RST_Pos)               /*!< SYS_T::IPRST1: ACMP01RST Mask          */
+
+#define SYS_IPRST1_I2C0RST_Pos           (8)                                               /*!< SYS_T::IPRST1: I2C0RST Position        */
+#define SYS_IPRST1_I2C0RST_Msk           (0x1ul << SYS_IPRST1_I2C0RST_Pos)                 /*!< SYS_T::IPRST1: I2C0RST Mask            */
+
+#define SYS_IPRST1_I2C1RST_Pos           (9)                                               /*!< SYS_T::IPRST1: I2C1RST Position        */
+#define SYS_IPRST1_I2C1RST_Msk           (0x1ul << SYS_IPRST1_I2C1RST_Pos)                 /*!< SYS_T::IPRST1: I2C1RST Mask            */
+
+#define SYS_IPRST1_I2C2RST_Pos           (10)                                              /*!< SYS_T::IPRST1: I2C2RST Position        */
+#define SYS_IPRST1_I2C2RST_Msk           (0x1ul << SYS_IPRST1_I2C2RST_Pos)                 /*!< SYS_T::IPRST1: I2C2RST Mask            */
+
+#define SYS_IPRST1_QSPI0RST_Pos          (12)                                              /*!< SYS_T::IPRST1: QSPI0RST Position       */
+#define SYS_IPRST1_QSPI0RST_Msk          (0x1ul << SYS_IPRST1_QSPI0RST_Pos)                /*!< SYS_T::IPRST1: QSPI0RST Mask           */
+
+#define SYS_IPRST1_SPI0RST_Pos           (13)                                              /*!< SYS_T::IPRST1: SPI0RST Position        */
+#define SYS_IPRST1_SPI0RST_Msk           (0x1ul << SYS_IPRST1_SPI0RST_Pos)                 /*!< SYS_T::IPRST1: SPI0RST Mask            */
+
+#define SYS_IPRST1_SPI1RST_Pos           (14)                                              /*!< SYS_T::IPRST1: SPI1RST Position        */
+#define SYS_IPRST1_SPI1RST_Msk           (0x1ul << SYS_IPRST1_SPI1RST_Pos)                 /*!< SYS_T::IPRST1: SPI1RST Mask            */
+
+#define SYS_IPRST1_SPI2RST_Pos           (15)                                              /*!< SYS_T::IPRST1: SPI2RST Position        */
+#define SYS_IPRST1_SPI2RST_Msk           (0x1ul << SYS_IPRST1_SPI2RST_Pos)                 /*!< SYS_T::IPRST1: SPI2RST Mask            */
+
+#define SYS_IPRST1_UART0RST_Pos          (16)                                              /*!< SYS_T::IPRST1: UART0RST Position       */
+#define SYS_IPRST1_UART0RST_Msk          (0x1ul << SYS_IPRST1_UART0RST_Pos)                /*!< SYS_T::IPRST1: UART0RST Mask           */
+
+#define SYS_IPRST1_UART1RST_Pos          (17)                                              /*!< SYS_T::IPRST1: UART1RST Position       */
+#define SYS_IPRST1_UART1RST_Msk          (0x1ul << SYS_IPRST1_UART1RST_Pos)                /*!< SYS_T::IPRST1: UART1RST Mask           */
+
+#define SYS_IPRST1_UART2RST_Pos          (18)                                              /*!< SYS_T::IPRST1: UART2RST Position       */
+#define SYS_IPRST1_UART2RST_Msk          (0x1ul << SYS_IPRST1_UART2RST_Pos)                /*!< SYS_T::IPRST1: UART2RST Mask           */
+
+#define SYS_IPRST1_UART3RST_Pos          (19)                                              /*!< SYS_T::IPRST1: UART3RST Position       */
+#define SYS_IPRST1_UART3RST_Msk          (0x1ul << SYS_IPRST1_UART3RST_Pos)                /*!< SYS_T::IPRST1: UART3RST Mask           */
+
+#define SYS_IPRST1_UART4RST_Pos          (20)                                              /*!< SYS_T::IPRST1: UART4RST Position       */
+#define SYS_IPRST1_UART4RST_Msk          (0x1ul << SYS_IPRST1_UART4RST_Pos)                /*!< SYS_T::IPRST1: UART4RST Mask           */
+
+#define SYS_IPRST1_UART5RST_Pos          (21)                                              /*!< SYS_T::IPRST1: UART5RST Position       */
+#define SYS_IPRST1_UART5RST_Msk          (0x1ul << SYS_IPRST1_UART5RST_Pos)                /*!< SYS_T::IPRST1: UART5RST Mask           */
+
+#define SYS_IPRST1_CAN0RST_Pos           (24)                                              /*!< SYS_T::IPRST1: CAN0RST Position        */
+#define SYS_IPRST1_CAN0RST_Msk           (0x1ul << SYS_IPRST1_CAN0RST_Pos)                 /*!< SYS_T::IPRST1: CAN0RST Mask            */
+
+#define SYS_IPRST1_OTGRST_Pos            (26)                                              /*!< SYS_T::IPRST1: OTGRST Position         */
+#define SYS_IPRST1_OTGRST_Msk            (0x1ul << SYS_IPRST1_OTGRST_Pos)                  /*!< SYS_T::IPRST1: OTGRST Mask             */
+
+#define SYS_IPRST1_USBDRST_Pos           (27)                                              /*!< SYS_T::IPRST1: USBDRST Position        */
+#define SYS_IPRST1_USBDRST_Msk           (0x1ul << SYS_IPRST1_USBDRST_Pos)                 /*!< SYS_T::IPRST1: USBDRST Mask            */
+
+#define SYS_IPRST1_EADCRST_Pos           (28)                                              /*!< SYS_T::IPRST1: EADCRST Position        */
+#define SYS_IPRST1_EADCRST_Msk           (0x1ul << SYS_IPRST1_EADCRST_Pos)                 /*!< SYS_T::IPRST1: EADCRST Mask            */
+
+#define SYS_IPRST1_I2S0RST_Pos           (29)                                              /*!< SYS_T::IPRST1: I2S0RST Position        */
+#define SYS_IPRST1_I2S0RST_Msk           (0x1ul << SYS_IPRST1_I2S0RST_Pos)                 /*!< SYS_T::IPRST1: I2S0RST Mask            */
+
+#define SYS_IPRST1_LCDRST_Pos            (30)                                              /*!< SYS_T::IPRST1: LCDRST Position         */
+#define SYS_IPRST1_LCDRST_Msk            (0x1ul << SYS_IPRST1_LCDRST_Pos)                  /*!< SYS_T::IPRST1: LCDRST Mask             */
+
+#define SYS_IPRST1_TRNGRST_Pos           (31)                                              /*!< SYS_T::IPRST1: TRNGRST Position        */
+#define SYS_IPRST1_TRNGRST_Msk           (0x1ul << SYS_IPRST1_TRNGRST_Pos)                 /*!< SYS_T::IPRST1: TRNGRST Mask            */
+
+#define SYS_IPRST2_SC0RST_Pos            (0)                                               /*!< SYS_T::IPRST2: SC0RST Position         */
+#define SYS_IPRST2_SC0RST_Msk            (0x1ul << SYS_IPRST2_SC0RST_Pos)                  /*!< SYS_T::IPRST2: SC0RST Mask             */
+
+#define SYS_IPRST2_SC1RST_Pos            (1)                                               /*!< SYS_T::IPRST2: SC1RST Position         */
+#define SYS_IPRST2_SC1RST_Msk            (0x1ul << SYS_IPRST2_SC1RST_Pos)                  /*!< SYS_T::IPRST2: SC1RST Mask             */
+
+#define SYS_IPRST2_SC2RST_Pos            (2)                                               /*!< SYS_T::IPRST2: SC2RST Position         */
+#define SYS_IPRST2_SC2RST_Msk            (0x1ul << SYS_IPRST2_SC2RST_Pos)                  /*!< SYS_T::IPRST2: SC2RST Mask             */
+
+#define SYS_IPRST2_SPI3RST_Pos           (6)                                               /*!< SYS_T::IPRST2: SPI3RST Position        */
+#define SYS_IPRST2_SPI3RST_Msk           (0x1ul << SYS_IPRST2_SPI3RST_Pos)                 /*!< SYS_T::IPRST2: SPI3RST Mask            */
+
+#define SYS_IPRST2_USCI0RST_Pos          (8)                                               /*!< SYS_T::IPRST2: USCI0RST Position       */
+#define SYS_IPRST2_USCI0RST_Msk          (0x1ul << SYS_IPRST2_USCI0RST_Pos)                /*!< SYS_T::IPRST2: USCI0RST Mask           */
+
+#define SYS_IPRST2_USCI1RST_Pos          (9)                                               /*!< SYS_T::IPRST2: USCI1RST Position       */
+#define SYS_IPRST2_USCI1RST_Msk          (0x1ul << SYS_IPRST2_USCI1RST_Pos)                /*!< SYS_T::IPRST2: USCI1RST Mask           */
+
+#define SYS_IPRST2_DACRST_Pos            (12)                                              /*!< SYS_T::IPRST2: DACRST Position         */
+#define SYS_IPRST2_DACRST_Msk            (0x1ul << SYS_IPRST2_DACRST_Pos)                  /*!< SYS_T::IPRST2: DACRST Mask             */
+
+#define SYS_IPRST2_EPWM0RST_Pos          (16)                                              /*!< SYS_T::IPRST2: EPWM0RST Position       */
+#define SYS_IPRST2_EPWM0RST_Msk          (0x1ul << SYS_IPRST2_EPWM0RST_Pos)                /*!< SYS_T::IPRST2: EPWM0RST Mask           */
+
+#define SYS_IPRST2_EPWM1RST_Pos          (17)                                              /*!< SYS_T::IPRST2: EPWM1RST Position       */
+#define SYS_IPRST2_EPWM1RST_Msk          (0x1ul << SYS_IPRST2_EPWM1RST_Pos)                /*!< SYS_T::IPRST2: EPWM1RST Mask           */
+
+#define SYS_IPRST2_BPWM0RST_Pos          (18)                                              /*!< SYS_T::IPRST2: BPWM0RST Position       */
+#define SYS_IPRST2_BPWM0RST_Msk          (0x1ul << SYS_IPRST2_BPWM0RST_Pos)                /*!< SYS_T::IPRST2: BPWM0RST Mask           */
+
+#define SYS_IPRST2_BPWM1RST_Pos          (19)                                              /*!< SYS_T::IPRST2: BPWM1RST Position       */
+#define SYS_IPRST2_BPWM1RST_Msk          (0x1ul << SYS_IPRST2_BPWM1RST_Pos)                /*!< SYS_T::IPRST2: BPWM1RST Mask           */
+
+#define SYS_IPRST2_TMR4RST_Pos           (20)                                              /*!< SYS_T::IPRST2: TMR4RST Position        */
+#define SYS_IPRST2_TMR4RST_Msk           (0x1ul << SYS_IPRST2_TMR4RST_Pos)                 /*!< SYS_T::IPRST2: TMR4RST Mask            */
+
+#define SYS_IPRST2_TMR5RST_Pos           (21)                                              /*!< SYS_T::IPRST2: TMR5RST Position        */
+#define SYS_IPRST2_TMR5RST_Msk           (0x1ul << SYS_IPRST2_TMR5RST_Pos)                 /*!< SYS_T::IPRST2: TMR5RST Mask            */
+
+#define SYS_IPRST2_QEI0RST_Pos           (22)                                              /*!< SYS_T::IPRST2: QEI0RST Position        */
+#define SYS_IPRST2_QEI0RST_Msk           (0x1ul << SYS_IPRST2_QEI0RST_Pos)                 /*!< SYS_T::IPRST2: QEI0RST Mask            */
+
+#define SYS_IPRST2_QEI1RST_Pos           (23)                                              /*!< SYS_T::IPRST2: QEI1RST Position        */
+#define SYS_IPRST2_QEI1RST_Msk           (0x1ul << SYS_IPRST2_QEI1RST_Pos)                 /*!< SYS_T::IPRST2: QEI1RST Mask            */
+
+#define SYS_IPRST2_ECAP0RST_Pos          (26)                                              /*!< SYS_T::IPRST2: ECAP0RST Position       */
+#define SYS_IPRST2_ECAP0RST_Msk          (0x1ul << SYS_IPRST2_ECAP0RST_Pos)                /*!< SYS_T::IPRST2: ECAP0RST Mask           */
+
+#define SYS_IPRST2_ECAP1RST_Pos          (27)                                              /*!< SYS_T::IPRST2: ECAP1RST Position       */
+#define SYS_IPRST2_ECAP1RST_Msk          (0x1ul << SYS_IPRST2_ECAP1RST_Pos)                /*!< SYS_T::IPRST2: ECAP1RST Mask           */
+
+#define SYS_BODCTL_BODEN_Pos             (0)                                               /*!< SYS_T::BODCTL: BODEN Position          */
+#define SYS_BODCTL_BODEN_Msk             (0x1ul << SYS_BODCTL_BODEN_Pos)                   /*!< SYS_T::BODCTL: BODEN Mask              */
+
+#define SYS_BODCTL_BODRSTEN_Pos          (3)                                               /*!< SYS_T::BODCTL: BODRSTEN Position       */
+#define SYS_BODCTL_BODRSTEN_Msk          (0x1ul << SYS_BODCTL_BODRSTEN_Pos)                /*!< SYS_T::BODCTL: BODRSTEN Mask           */
+
+#define SYS_BODCTL_BODIF_Pos             (4)                                               /*!< SYS_T::BODCTL: BODIF Position          */
+#define SYS_BODCTL_BODIF_Msk             (0x1ul << SYS_BODCTL_BODIF_Pos)                   /*!< SYS_T::BODCTL: BODIF Mask              */
+
+#define SYS_BODCTL_BODOUT_Pos            (6)                                               /*!< SYS_T::BODCTL: BODOUT Position         */
+#define SYS_BODCTL_BODOUT_Msk            (0x1ul << SYS_BODCTL_BODOUT_Pos)                  /*!< SYS_T::BODCTL: BODOUT Mask             */
+
+#define SYS_BODCTL_LVREN_Pos             (7)                                               /*!< SYS_T::BODCTL: LVREN Position          */
+#define SYS_BODCTL_LVREN_Msk             (0x1ul << SYS_BODCTL_LVREN_Pos)                   /*!< SYS_T::BODCTL: LVREN Mask              */
+
+#define SYS_BODCTL_BODDGSEL_Pos          (8)                                               /*!< SYS_T::BODCTL: BODDGSEL Position       */
+#define SYS_BODCTL_BODDGSEL_Msk          (0x7ul << SYS_BODCTL_BODDGSEL_Pos)                /*!< SYS_T::BODCTL: BODDGSEL Mask           */
+
+#define SYS_BODCTL_LVRDGSEL_Pos          (12)                                              /*!< SYS_T::BODCTL: LVRDGSEL Position       */
+#define SYS_BODCTL_LVRDGSEL_Msk          (0x7ul << SYS_BODCTL_LVRDGSEL_Pos)                /*!< SYS_T::BODCTL: LVRDGSEL Mask           */
+
+#define SYS_BODCTL_BODVL_Pos             (16)                                              /*!< SYS_T::BODCTL: BODVL Position          */
+#define SYS_BODCTL_BODVL_Msk             (0x7ul << SYS_BODCTL_BODVL_Pos)                   /*!< SYS_T::BODCTL: BODVL Mask              */
+
+#define SYS_BODCTL_STB_Pos               (23)                                              /*!< SYS_T::BODCTL: STB Position            */
+#define SYS_BODCTL_STB_Msk               (0x1ul << SYS_BODCTL_STB_Pos)                     /*!< SYS_T::BODCTL: STB Mask                */
+
+#define SYS_BODCTL_WRBUSY_Pos            (31)                                              /*!< SYS_T::BODCTL: WRBUSY Position         */
+#define SYS_BODCTL_WRBUSY_Msk            (0x1ul << SYS_BODCTL_WRBUSY_Pos)                  /*!< SYS_T::BODCTL: WRBUSY Mask             */
+
+#define SYS_IVSCTL_VTEMPEN_Pos           (0)                                               /*!< SYS_T::IVSCTL: VTEMPEN Position        */
+#define SYS_IVSCTL_VTEMPEN_Msk           (0x1ul << SYS_IVSCTL_VTEMPEN_Pos)                 /*!< SYS_T::IVSCTL: VTEMPEN Mask            */
+
+#define SYS_IVSCTL_VBATUGEN_Pos          (1)                                               /*!< SYS_T::IVSCTL: VBATUGEN Position       */
+#define SYS_IVSCTL_VBATUGEN_Msk          (0x1ul << SYS_IVSCTL_VBATUGEN_Pos)                /*!< SYS_T::IVSCTL: VBATUGEN Mask           */
+
+#define SYS_PORCTL0_PORMASK_Pos          (0)                                               /*!< SYS_T::PORCTL0: PORMASK Position       */
+#define SYS_PORCTL0_PORMASK_Msk          (0xfffful << SYS_PORCTL0_PORMASK_Pos)             /*!< SYS_T::PORCTL0: PORMASK Mask           */
+
+#define SYS_VREFCTL_VREFCTL_Pos          (0)                                               /*!< SYS_T::VREFCTL: VREFCTL Position       */
+#define SYS_VREFCTL_VREFCTL_Msk          (0x1ful << SYS_VREFCTL_VREFCTL_Pos)               /*!< SYS_T::VREFCTL: VREFCTL Mask           */
+
+#define SYS_VREFCTL_IBIASSEL_Pos         (5)                                               /*!< SYS_T::VREFCTL: IBIASSEL Position      */
+#define SYS_VREFCTL_IBIASSEL_Msk         (0x1ul << SYS_VREFCTL_IBIASSEL_Pos)               /*!< SYS_T::VREFCTL: IBIASSEL Mask          */
+
+#define SYS_VREFCTL_PRELOADSEL_Pos       (6)                                               /*!< SYS_T::VREFCTL: PRELOADSEL Position    */
+#define SYS_VREFCTL_PRELOADSEL_Msk       (0x3ul << SYS_VREFCTL_PRELOADSEL_Pos)             /*!< SYS_T::VREFCTL: PRELOADSEL Mask        */
+
+#define SYS_USBPHY_USBROLE_Pos           (0)                                               /*!< SYS_T::USBPHY: USBROLE Position        */
+#define SYS_USBPHY_USBROLE_Msk           (0x3ul << SYS_USBPHY_USBROLE_Pos)                 /*!< SYS_T::USBPHY: USBROLE Mask            */
+
+#define SYS_USBPHY_SBO_Pos               (2)                                               /*!< SYS_T::USBPHY: SBO Position            */
+#define SYS_USBPHY_SBO_Msk               (0x1ul << SYS_USBPHY_SBO_Pos)                     /*!< SYS_T::USBPHY: SBO Mask                */
+
+#define SYS_USBPHY_OTGPHYEN_Pos          (8)                                               /*!< SYS_T::USBPHY: OTGPHYEN Position       */
+#define SYS_USBPHY_OTGPHYEN_Msk          (0x1ul << SYS_USBPHY_OTGPHYEN_Pos)                /*!< SYS_T::USBPHY: OTGPHYEN Mask           */
+
+#define SYS_GPA_MFPL_PA0MFP_Pos          (0)                                               /*!< SYS_T::GPA_MFPL: PA0MFP Position       */
+#define SYS_GPA_MFPL_PA0MFP_Msk          (0xful << SYS_GPA_MFPL_PA0MFP_Pos)                /*!< SYS_T::GPA_MFPL: PA0MFP Mask           */
+
+#define SYS_GPA_MFPL_PA1MFP_Pos          (4)                                               /*!< SYS_T::GPA_MFPL: PA1MFP Position       */
+#define SYS_GPA_MFPL_PA1MFP_Msk          (0xful << SYS_GPA_MFPL_PA1MFP_Pos)                /*!< SYS_T::GPA_MFPL: PA1MFP Mask           */
+
+#define SYS_GPA_MFPL_PA2MFP_Pos          (8)                                               /*!< SYS_T::GPA_MFPL: PA2MFP Position       */
+#define SYS_GPA_MFPL_PA2MFP_Msk          (0xful << SYS_GPA_MFPL_PA2MFP_Pos)                /*!< SYS_T::GPA_MFPL: PA2MFP Mask           */
+
+#define SYS_GPA_MFPL_PA3MFP_Pos          (12)                                              /*!< SYS_T::GPA_MFPL: PA3MFP Position       */
+#define SYS_GPA_MFPL_PA3MFP_Msk          (0xful << SYS_GPA_MFPL_PA3MFP_Pos)                /*!< SYS_T::GPA_MFPL: PA3MFP Mask           */
+
+#define SYS_GPA_MFPL_PA4MFP_Pos          (16)                                              /*!< SYS_T::GPA_MFPL: PA4MFP Position       */
+#define SYS_GPA_MFPL_PA4MFP_Msk          (0xful << SYS_GPA_MFPL_PA4MFP_Pos)                /*!< SYS_T::GPA_MFPL: PA4MFP Mask           */
+
+#define SYS_GPA_MFPL_PA5MFP_Pos          (20)                                              /*!< SYS_T::GPA_MFPL: PA5MFP Position       */
+#define SYS_GPA_MFPL_PA5MFP_Msk          (0xful << SYS_GPA_MFPL_PA5MFP_Pos)                /*!< SYS_T::GPA_MFPL: PA5MFP Mask           */
+
+#define SYS_GPA_MFPL_PA6MFP_Pos          (24)                                              /*!< SYS_T::GPA_MFPL: PA6MFP Position       */
+#define SYS_GPA_MFPL_PA6MFP_Msk          (0xful << SYS_GPA_MFPL_PA6MFP_Pos)                /*!< SYS_T::GPA_MFPL: PA6MFP Mask           */
+
+#define SYS_GPA_MFPL_PA7MFP_Pos          (28)                                              /*!< SYS_T::GPA_MFPL: PA7MFP Position       */
+#define SYS_GPA_MFPL_PA7MFP_Msk          (0xful << SYS_GPA_MFPL_PA7MFP_Pos)                /*!< SYS_T::GPA_MFPL: PA7MFP Mask           */
+
+#define SYS_GPA_MFPH_PA8MFP_Pos          (0)                                               /*!< SYS_T::GPA_MFPH: PA8MFP Position       */
+#define SYS_GPA_MFPH_PA8MFP_Msk          (0xful << SYS_GPA_MFPH_PA8MFP_Pos)                /*!< SYS_T::GPA_MFPH: PA8MFP Mask           */
+
+#define SYS_GPA_MFPH_PA9MFP_Pos          (4)                                               /*!< SYS_T::GPA_MFPH: PA9MFP Position       */
+#define SYS_GPA_MFPH_PA9MFP_Msk          (0xful << SYS_GPA_MFPH_PA9MFP_Pos)                /*!< SYS_T::GPA_MFPH: PA9MFP Mask           */
+
+#define SYS_GPA_MFPH_PA10MFP_Pos         (8)                                               /*!< SYS_T::GPA_MFPH: PA10MFP Position      */
+#define SYS_GPA_MFPH_PA10MFP_Msk         (0xful << SYS_GPA_MFPH_PA10MFP_Pos)               /*!< SYS_T::GPA_MFPH: PA10MFP Mask          */
+
+#define SYS_GPA_MFPH_PA11MFP_Pos         (12)                                              /*!< SYS_T::GPA_MFPH: PA11MFP Position      */
+#define SYS_GPA_MFPH_PA11MFP_Msk         (0xful << SYS_GPA_MFPH_PA11MFP_Pos)               /*!< SYS_T::GPA_MFPH: PA11MFP Mask          */
+
+#define SYS_GPA_MFPH_PA12MFP_Pos         (16)                                              /*!< SYS_T::GPA_MFPH: PA12MFP Position      */
+#define SYS_GPA_MFPH_PA12MFP_Msk         (0xful << SYS_GPA_MFPH_PA12MFP_Pos)               /*!< SYS_T::GPA_MFPH: PA12MFP Mask          */
+
+#define SYS_GPA_MFPH_PA13MFP_Pos         (20)                                              /*!< SYS_T::GPA_MFPH: PA13MFP Position      */
+#define SYS_GPA_MFPH_PA13MFP_Msk         (0xful << SYS_GPA_MFPH_PA13MFP_Pos)               /*!< SYS_T::GPA_MFPH: PA13MFP Mask          */
+
+#define SYS_GPA_MFPH_PA14MFP_Pos         (24)                                              /*!< SYS_T::GPA_MFPH: PA14MFP Position      */
+#define SYS_GPA_MFPH_PA14MFP_Msk         (0xful << SYS_GPA_MFPH_PA14MFP_Pos)               /*!< SYS_T::GPA_MFPH: PA14MFP Mask          */
+
+#define SYS_GPA_MFPH_PA15MFP_Pos         (28)                                              /*!< SYS_T::GPA_MFPH: PA15MFP Position      */
+#define SYS_GPA_MFPH_PA15MFP_Msk         (0xful << SYS_GPA_MFPH_PA15MFP_Pos)               /*!< SYS_T::GPA_MFPH: PA15MFP Mask          */
+
+#define SYS_GPB_MFPL_PB0MFP_Pos          (0)                                               /*!< SYS_T::GPB_MFPL: PB0MFP Position       */
+#define SYS_GPB_MFPL_PB0MFP_Msk          (0xful << SYS_GPB_MFPL_PB0MFP_Pos)                /*!< SYS_T::GPB_MFPL: PB0MFP Mask           */
+
+#define SYS_GPB_MFPL_PB1MFP_Pos          (4)                                               /*!< SYS_T::GPB_MFPL: PB1MFP Position       */
+#define SYS_GPB_MFPL_PB1MFP_Msk          (0xful << SYS_GPB_MFPL_PB1MFP_Pos)                /*!< SYS_T::GPB_MFPL: PB1MFP Mask           */
+
+#define SYS_GPB_MFPL_PB2MFP_Pos          (8)                                               /*!< SYS_T::GPB_MFPL: PB2MFP Position       */
+#define SYS_GPB_MFPL_PB2MFP_Msk          (0xful << SYS_GPB_MFPL_PB2MFP_Pos)                /*!< SYS_T::GPB_MFPL: PB2MFP Mask           */
+
+#define SYS_GPB_MFPL_PB3MFP_Pos          (12)                                              /*!< SYS_T::GPB_MFPL: PB3MFP Position       */
+#define SYS_GPB_MFPL_PB3MFP_Msk          (0xful << SYS_GPB_MFPL_PB3MFP_Pos)                /*!< SYS_T::GPB_MFPL: PB3MFP Mask           */
+
+#define SYS_GPB_MFPL_PB4MFP_Pos          (16)                                              /*!< SYS_T::GPB_MFPL: PB4MFP Position       */
+#define SYS_GPB_MFPL_PB4MFP_Msk          (0xful << SYS_GPB_MFPL_PB4MFP_Pos)                /*!< SYS_T::GPB_MFPL: PB4MFP Mask           */
+
+#define SYS_GPB_MFPL_PB5MFP_Pos          (20)                                              /*!< SYS_T::GPB_MFPL: PB5MFP Position       */
+#define SYS_GPB_MFPL_PB5MFP_Msk          (0xful << SYS_GPB_MFPL_PB5MFP_Pos)                /*!< SYS_T::GPB_MFPL: PB5MFP Mask           */
+
+#define SYS_GPB_MFPL_PB6MFP_Pos          (24)                                              /*!< SYS_T::GPB_MFPL: PB6MFP Position       */
+#define SYS_GPB_MFPL_PB6MFP_Msk          (0xful << SYS_GPB_MFPL_PB6MFP_Pos)                /*!< SYS_T::GPB_MFPL: PB6MFP Mask           */
+
+#define SYS_GPB_MFPL_PB7MFP_Pos          (28)                                              /*!< SYS_T::GPB_MFPL: PB7MFP Position       */
+#define SYS_GPB_MFPL_PB7MFP_Msk          (0xful << SYS_GPB_MFPL_PB7MFP_Pos)                /*!< SYS_T::GPB_MFPL: PB7MFP Mask           */
+
+#define SYS_GPB_MFPH_PB8MFP_Pos          (0)                                               /*!< SYS_T::GPB_MFPH: PB8MFP Position       */
+#define SYS_GPB_MFPH_PB8MFP_Msk          (0xful << SYS_GPB_MFPH_PB8MFP_Pos)                /*!< SYS_T::GPB_MFPH: PB8MFP Mask           */
+
+#define SYS_GPB_MFPH_PB9MFP_Pos          (4)                                               /*!< SYS_T::GPB_MFPH: PB9MFP Position       */
+#define SYS_GPB_MFPH_PB9MFP_Msk          (0xful << SYS_GPB_MFPH_PB9MFP_Pos)                /*!< SYS_T::GPB_MFPH: PB9MFP Mask           */
+
+#define SYS_GPB_MFPH_PB10MFP_Pos         (8)                                               /*!< SYS_T::GPB_MFPH: PB10MFP Position      */
+#define SYS_GPB_MFPH_PB10MFP_Msk         (0xful << SYS_GPB_MFPH_PB10MFP_Pos)               /*!< SYS_T::GPB_MFPH: PB10MFP Mask          */
+
+#define SYS_GPB_MFPH_PB11MFP_Pos         (12)                                              /*!< SYS_T::GPB_MFPH: PB11MFP Position      */
+#define SYS_GPB_MFPH_PB11MFP_Msk         (0xful << SYS_GPB_MFPH_PB11MFP_Pos)               /*!< SYS_T::GPB_MFPH: PB11MFP Mask          */
+
+#define SYS_GPB_MFPH_PB12MFP_Pos         (16)                                              /*!< SYS_T::GPB_MFPH: PB12MFP Position      */
+#define SYS_GPB_MFPH_PB12MFP_Msk         (0xful << SYS_GPB_MFPH_PB12MFP_Pos)               /*!< SYS_T::GPB_MFPH: PB12MFP Mask          */
+
+#define SYS_GPB_MFPH_PB13MFP_Pos         (20)                                              /*!< SYS_T::GPB_MFPH: PB13MFP Position      */
+#define SYS_GPB_MFPH_PB13MFP_Msk         (0xful << SYS_GPB_MFPH_PB13MFP_Pos)               /*!< SYS_T::GPB_MFPH: PB13MFP Mask          */
+
+#define SYS_GPB_MFPH_PB14MFP_Pos         (24)                                              /*!< SYS_T::GPB_MFPH: PB14MFP Position      */
+#define SYS_GPB_MFPH_PB14MFP_Msk         (0xful << SYS_GPB_MFPH_PB14MFP_Pos)               /*!< SYS_T::GPB_MFPH: PB14MFP Mask          */
+
+#define SYS_GPB_MFPH_PB15MFP_Pos         (28)                                              /*!< SYS_T::GPB_MFPH: PB15MFP Position      */
+#define SYS_GPB_MFPH_PB15MFP_Msk         (0xful << SYS_GPB_MFPH_PB15MFP_Pos)               /*!< SYS_T::GPB_MFPH: PB15MFP Mask          */
+
+#define SYS_GPC_MFPL_PC0MFP_Pos          (0)                                               /*!< SYS_T::GPC_MFPL: PC0MFP Position       */
+#define SYS_GPC_MFPL_PC0MFP_Msk          (0xful << SYS_GPC_MFPL_PC0MFP_Pos)                /*!< SYS_T::GPC_MFPL: PC0MFP Mask           */
+
+#define SYS_GPC_MFPL_PC1MFP_Pos          (4)                                               /*!< SYS_T::GPC_MFPL: PC1MFP Position       */
+#define SYS_GPC_MFPL_PC1MFP_Msk          (0xful << SYS_GPC_MFPL_PC1MFP_Pos)                /*!< SYS_T::GPC_MFPL: PC1MFP Mask           */
+
+#define SYS_GPC_MFPL_PC2MFP_Pos          (8)                                               /*!< SYS_T::GPC_MFPL: PC2MFP Position       */
+#define SYS_GPC_MFPL_PC2MFP_Msk          (0xful << SYS_GPC_MFPL_PC2MFP_Pos)                /*!< SYS_T::GPC_MFPL: PC2MFP Mask           */
+
+#define SYS_GPC_MFPL_PC3MFP_Pos          (12)                                              /*!< SYS_T::GPC_MFPL: PC3MFP Position       */
+#define SYS_GPC_MFPL_PC3MFP_Msk          (0xful << SYS_GPC_MFPL_PC3MFP_Pos)                /*!< SYS_T::GPC_MFPL: PC3MFP Mask           */
+
+#define SYS_GPC_MFPL_PC4MFP_Pos          (16)                                              /*!< SYS_T::GPC_MFPL: PC4MFP Position       */
+#define SYS_GPC_MFPL_PC4MFP_Msk          (0xful << SYS_GPC_MFPL_PC4MFP_Pos)                /*!< SYS_T::GPC_MFPL: PC4MFP Mask           */
+
+#define SYS_GPC_MFPL_PC5MFP_Pos          (20)                                              /*!< SYS_T::GPC_MFPL: PC5MFP Position       */
+#define SYS_GPC_MFPL_PC5MFP_Msk          (0xful << SYS_GPC_MFPL_PC5MFP_Pos)                /*!< SYS_T::GPC_MFPL: PC5MFP Mask           */
+
+#define SYS_GPC_MFPL_PC6MFP_Pos          (24)                                              /*!< SYS_T::GPC_MFPL: PC6MFP Position       */
+#define SYS_GPC_MFPL_PC6MFP_Msk          (0xful << SYS_GPC_MFPL_PC6MFP_Pos)                /*!< SYS_T::GPC_MFPL: PC6MFP Mask           */
+
+#define SYS_GPC_MFPL_PC7MFP_Pos          (28)                                              /*!< SYS_T::GPC_MFPL: PC7MFP Position       */
+#define SYS_GPC_MFPL_PC7MFP_Msk          (0xful << SYS_GPC_MFPL_PC7MFP_Pos)                /*!< SYS_T::GPC_MFPL: PC7MFP Mask           */
+
+#define SYS_GPC_MFPH_PC8MFP_Pos          (0)                                               /*!< SYS_T::GPC_MFPH: PC8MFP Position       */
+#define SYS_GPC_MFPH_PC8MFP_Msk          (0xful << SYS_GPC_MFPH_PC8MFP_Pos)                /*!< SYS_T::GPC_MFPH: PC8MFP Mask           */
+
+#define SYS_GPC_MFPH_PC9MFP_Pos          (4)                                               /*!< SYS_T::GPC_MFPH: PC9MFP Position       */
+#define SYS_GPC_MFPH_PC9MFP_Msk          (0xful << SYS_GPC_MFPH_PC9MFP_Pos)                /*!< SYS_T::GPC_MFPH: PC9MFP Mask           */
+
+#define SYS_GPC_MFPH_PC10MFP_Pos         (8)                                               /*!< SYS_T::GPC_MFPH: PC10MFP Position      */
+#define SYS_GPC_MFPH_PC10MFP_Msk         (0xful << SYS_GPC_MFPH_PC10MFP_Pos)               /*!< SYS_T::GPC_MFPH: PC10MFP Mask          */
+
+#define SYS_GPC_MFPH_PC11MFP_Pos         (12)                                              /*!< SYS_T::GPC_MFPH: PC11MFP Position      */
+#define SYS_GPC_MFPH_PC11MFP_Msk         (0xful << SYS_GPC_MFPH_PC11MFP_Pos)               /*!< SYS_T::GPC_MFPH: PC11MFP Mask          */
+
+#define SYS_GPC_MFPH_PC12MFP_Pos         (16)                                              /*!< SYS_T::GPC_MFPH: PC12MFP Position      */
+#define SYS_GPC_MFPH_PC12MFP_Msk         (0xful << SYS_GPC_MFPH_PC12MFP_Pos)               /*!< SYS_T::GPC_MFPH: PC12MFP Mask          */
+
+#define SYS_GPC_MFPH_PC13MFP_Pos         (20)                                              /*!< SYS_T::GPC_MFPH: PC13MFP Position      */
+#define SYS_GPC_MFPH_PC13MFP_Msk         (0xful << SYS_GPC_MFPH_PC13MFP_Pos)               /*!< SYS_T::GPC_MFPH: PC13MFP Mask          */
+
+#define SYS_GPD_MFPL_PD0MFP_Pos          (0)                                               /*!< SYS_T::GPD_MFPL: PD0MFP Position       */
+#define SYS_GPD_MFPL_PD0MFP_Msk          (0xful << SYS_GPD_MFPL_PD0MFP_Pos)                /*!< SYS_T::GPD_MFPL: PD0MFP Mask           */
+
+#define SYS_GPD_MFPL_PD1MFP_Pos          (4)                                               /*!< SYS_T::GPD_MFPL: PD1MFP Position       */
+#define SYS_GPD_MFPL_PD1MFP_Msk          (0xful << SYS_GPD_MFPL_PD1MFP_Pos)                /*!< SYS_T::GPD_MFPL: PD1MFP Mask           */
+
+#define SYS_GPD_MFPL_PD2MFP_Pos          (8)                                               /*!< SYS_T::GPD_MFPL: PD2MFP Position       */
+#define SYS_GPD_MFPL_PD2MFP_Msk          (0xful << SYS_GPD_MFPL_PD2MFP_Pos)                /*!< SYS_T::GPD_MFPL: PD2MFP Mask           */
+
+#define SYS_GPD_MFPL_PD3MFP_Pos          (12)                                              /*!< SYS_T::GPD_MFPL: PD3MFP Position       */
+#define SYS_GPD_MFPL_PD3MFP_Msk          (0xful << SYS_GPD_MFPL_PD3MFP_Pos)                /*!< SYS_T::GPD_MFPL: PD3MFP Mask           */
+
+#define SYS_GPD_MFPL_PD4MFP_Pos          (16)                                              /*!< SYS_T::GPD_MFPL: PD4MFP Position       */
+#define SYS_GPD_MFPL_PD4MFP_Msk          (0xful << SYS_GPD_MFPL_PD4MFP_Pos)                /*!< SYS_T::GPD_MFPL: PD4MFP Mask           */
+
+#define SYS_GPD_MFPL_PD5MFP_Pos          (20)                                              /*!< SYS_T::GPD_MFPL: PD5MFP Position       */
+#define SYS_GPD_MFPL_PD5MFP_Msk          (0xful << SYS_GPD_MFPL_PD5MFP_Pos)                /*!< SYS_T::GPD_MFPL: PD5MFP Mask           */
+
+#define SYS_GPD_MFPL_PD6MFP_Pos          (24)                                              /*!< SYS_T::GPD_MFPL: PD6MFP Position       */
+#define SYS_GPD_MFPL_PD6MFP_Msk          (0xful << SYS_GPD_MFPL_PD6MFP_Pos)                /*!< SYS_T::GPD_MFPL: PD6MFP Mask           */
+
+#define SYS_GPD_MFPL_PD7MFP_Pos          (28)                                              /*!< SYS_T::GPD_MFPL: PD7MFP Position       */
+#define SYS_GPD_MFPL_PD7MFP_Msk          (0xful << SYS_GPD_MFPL_PD7MFP_Pos)                /*!< SYS_T::GPD_MFPL: PD7MFP Mask           */
+
+#define SYS_GPD_MFPH_PD8MFP_Pos          (0)                                               /*!< SYS_T::GPD_MFPH: PD8MFP Position       */
+#define SYS_GPD_MFPH_PD8MFP_Msk          (0xful << SYS_GPD_MFPH_PD8MFP_Pos)                /*!< SYS_T::GPD_MFPH: PD8MFP Mask           */
+
+#define SYS_GPD_MFPH_PD9MFP_Pos          (4)                                               /*!< SYS_T::GPD_MFPH: PD9MFP Position       */
+#define SYS_GPD_MFPH_PD9MFP_Msk          (0xful << SYS_GPD_MFPH_PD9MFP_Pos)                /*!< SYS_T::GPD_MFPH: PD9MFP Mask           */
+
+#define SYS_GPD_MFPH_PD10MFP_Pos         (8)                                               /*!< SYS_T::GPD_MFPH: PD10MFP Position      */
+#define SYS_GPD_MFPH_PD10MFP_Msk         (0xful << SYS_GPD_MFPH_PD10MFP_Pos)               /*!< SYS_T::GPD_MFPH: PD10MFP Mask          */
+
+#define SYS_GPD_MFPH_PD11MFP_Pos         (12)                                              /*!< SYS_T::GPD_MFPH: PD11MFP Position      */
+#define SYS_GPD_MFPH_PD11MFP_Msk         (0xful << SYS_GPD_MFPH_PD11MFP_Pos)               /*!< SYS_T::GPD_MFPH: PD11MFP Mask          */
+
+#define SYS_GPD_MFPH_PD12MFP_Pos         (16)                                              /*!< SYS_T::GPD_MFPH: PD12MFP Position      */
+#define SYS_GPD_MFPH_PD12MFP_Msk         (0xful << SYS_GPD_MFPH_PD12MFP_Pos)               /*!< SYS_T::GPD_MFPH: PD12MFP Mask          */
+
+#define SYS_GPD_MFPH_PD14MFP_Pos         (24)                                              /*!< SYS_T::GPD_MFPH: PD14MFP Position      */
+#define SYS_GPD_MFPH_PD14MFP_Msk         (0xful << SYS_GPD_MFPH_PD14MFP_Pos)               /*!< SYS_T::GPD_MFPH: PD14MFP Mask          */
+
+#define SYS_GPE_MFPL_PE0MFP_Pos          (0)                                               /*!< SYS_T::GPE_MFPL: PE0MFP Position       */
+#define SYS_GPE_MFPL_PE0MFP_Msk          (0xful << SYS_GPE_MFPL_PE0MFP_Pos)                /*!< SYS_T::GPE_MFPL: PE0MFP Mask           */
+
+#define SYS_GPE_MFPL_PE1MFP_Pos          (4)                                               /*!< SYS_T::GPE_MFPL: PE1MFP Position       */
+#define SYS_GPE_MFPL_PE1MFP_Msk          (0xful << SYS_GPE_MFPL_PE1MFP_Pos)                /*!< SYS_T::GPE_MFPL: PE1MFP Mask           */
+
+#define SYS_GPE_MFPL_PE2MFP_Pos          (8)                                               /*!< SYS_T::GPE_MFPL: PE2MFP Position       */
+#define SYS_GPE_MFPL_PE2MFP_Msk          (0xful << SYS_GPE_MFPL_PE2MFP_Pos)                /*!< SYS_T::GPE_MFPL: PE2MFP Mask           */
+
+#define SYS_GPE_MFPL_PE3MFP_Pos          (12)                                              /*!< SYS_T::GPE_MFPL: PE3MFP Position       */
+#define SYS_GPE_MFPL_PE3MFP_Msk          (0xful << SYS_GPE_MFPL_PE3MFP_Pos)                /*!< SYS_T::GPE_MFPL: PE3MFP Mask           */
+
+#define SYS_GPE_MFPL_PE4MFP_Pos          (16)                                              /*!< SYS_T::GPE_MFPL: PE4MFP Position       */
+#define SYS_GPE_MFPL_PE4MFP_Msk          (0xful << SYS_GPE_MFPL_PE4MFP_Pos)                /*!< SYS_T::GPE_MFPL: PE4MFP Mask           */
+
+#define SYS_GPE_MFPL_PE5MFP_Pos          (20)                                              /*!< SYS_T::GPE_MFPL: PE5MFP Position       */
+#define SYS_GPE_MFPL_PE5MFP_Msk          (0xful << SYS_GPE_MFPL_PE5MFP_Pos)                /*!< SYS_T::GPE_MFPL: PE5MFP Mask           */
+
+#define SYS_GPE_MFPL_PE6MFP_Pos          (24)                                              /*!< SYS_T::GPE_MFPL: PE6MFP Position       */
+#define SYS_GPE_MFPL_PE6MFP_Msk          (0xful << SYS_GPE_MFPL_PE6MFP_Pos)                /*!< SYS_T::GPE_MFPL: PE6MFP Mask           */
+
+#define SYS_GPE_MFPL_PE7MFP_Pos          (28)                                              /*!< SYS_T::GPE_MFPL: PE7MFP Position       */
+#define SYS_GPE_MFPL_PE7MFP_Msk          (0xful << SYS_GPE_MFPL_PE7MFP_Pos)                /*!< SYS_T::GPE_MFPL: PE7MFP Mask           */
+
+#define SYS_GPE_MFPH_PE8MFP_Pos          (0)                                               /*!< SYS_T::GPE_MFPH: PE8MFP Position       */
+#define SYS_GPE_MFPH_PE8MFP_Msk          (0xful << SYS_GPE_MFPH_PE8MFP_Pos)                /*!< SYS_T::GPE_MFPH: PE8MFP Mask           */
+
+#define SYS_GPE_MFPH_PE9MFP_Pos          (4)                                               /*!< SYS_T::GPE_MFPH: PE9MFP Position       */
+#define SYS_GPE_MFPH_PE9MFP_Msk          (0xful << SYS_GPE_MFPH_PE9MFP_Pos)                /*!< SYS_T::GPE_MFPH: PE9MFP Mask           */
+
+#define SYS_GPE_MFPH_PE10MFP_Pos         (8)                                               /*!< SYS_T::GPE_MFPH: PE10MFP Position      */
+#define SYS_GPE_MFPH_PE10MFP_Msk         (0xful << SYS_GPE_MFPH_PE10MFP_Pos)               /*!< SYS_T::GPE_MFPH: PE10MFP Mask          */
+
+#define SYS_GPE_MFPH_PE11MFP_Pos         (12)                                              /*!< SYS_T::GPE_MFPH: PE11MFP Position      */
+#define SYS_GPE_MFPH_PE11MFP_Msk         (0xful << SYS_GPE_MFPH_PE11MFP_Pos)               /*!< SYS_T::GPE_MFPH: PE11MFP Mask          */
+
+#define SYS_GPE_MFPH_PE12MFP_Pos         (16)                                              /*!< SYS_T::GPE_MFPH: PE12MFP Position      */
+#define SYS_GPE_MFPH_PE12MFP_Msk         (0xful << SYS_GPE_MFPH_PE12MFP_Pos)               /*!< SYS_T::GPE_MFPH: PE12MFP Mask          */
+
+#define SYS_GPE_MFPH_PE13MFP_Pos         (20)                                              /*!< SYS_T::GPE_MFPH: PE13MFP Position      */
+#define SYS_GPE_MFPH_PE13MFP_Msk         (0xful << SYS_GPE_MFPH_PE13MFP_Pos)               /*!< SYS_T::GPE_MFPH: PE13MFP Mask          */
+
+#define SYS_GPE_MFPH_PE14MFP_Pos         (24)                                              /*!< SYS_T::GPE_MFPH: PE14MFP Position      */
+#define SYS_GPE_MFPH_PE14MFP_Msk         (0xful << SYS_GPE_MFPH_PE14MFP_Pos)               /*!< SYS_T::GPE_MFPH: PE14MFP Mask          */
+
+#define SYS_GPE_MFPH_PE15MFP_Pos         (28)                                              /*!< SYS_T::GPE_MFPH: PE15MFP Position      */
+#define SYS_GPE_MFPH_PE15MFP_Msk         (0xful << SYS_GPE_MFPH_PE15MFP_Pos)               /*!< SYS_T::GPE_MFPH: PE15MFP Mask          */
+
+#define SYS_GPF_MFPL_PF0MFP_Pos          (0)                                               /*!< SYS_T::GPF_MFPL: PF0MFP Position       */
+#define SYS_GPF_MFPL_PF0MFP_Msk          (0xful << SYS_GPF_MFPL_PF0MFP_Pos)                /*!< SYS_T::GPF_MFPL: PF0MFP Mask           */
+
+#define SYS_GPF_MFPL_PF1MFP_Pos          (4)                                               /*!< SYS_T::GPF_MFPL: PF1MFP Position       */
+#define SYS_GPF_MFPL_PF1MFP_Msk          (0xful << SYS_GPF_MFPL_PF1MFP_Pos)                /*!< SYS_T::GPF_MFPL: PF1MFP Mask           */
+
+#define SYS_GPF_MFPL_PF2MFP_Pos          (8)                                               /*!< SYS_T::GPF_MFPL: PF2MFP Position       */
+#define SYS_GPF_MFPL_PF2MFP_Msk          (0xful << SYS_GPF_MFPL_PF2MFP_Pos)                /*!< SYS_T::GPF_MFPL: PF2MFP Mask           */
+
+#define SYS_GPF_MFPL_PF3MFP_Pos          (12)                                              /*!< SYS_T::GPF_MFPL: PF3MFP Position       */
+#define SYS_GPF_MFPL_PF3MFP_Msk          (0xful << SYS_GPF_MFPL_PF3MFP_Pos)                /*!< SYS_T::GPF_MFPL: PF3MFP Mask           */
+
+#define SYS_GPF_MFPL_PF4MFP_Pos          (16)                                              /*!< SYS_T::GPF_MFPL: PF4MFP Position       */
+#define SYS_GPF_MFPL_PF4MFP_Msk          (0xful << SYS_GPF_MFPL_PF4MFP_Pos)                /*!< SYS_T::GPF_MFPL: PF4MFP Mask           */
+
+#define SYS_GPF_MFPL_PF5MFP_Pos          (20)                                              /*!< SYS_T::GPF_MFPL: PF5MFP Position       */
+#define SYS_GPF_MFPL_PF5MFP_Msk          (0xful << SYS_GPF_MFPL_PF5MFP_Pos)                /*!< SYS_T::GPF_MFPL: PF5MFP Mask           */
+
+#define SYS_GPF_MFPL_PF6MFP_Pos          (24)                                              /*!< SYS_T::GPF_MFPL: PF6MFP Position       */
+#define SYS_GPF_MFPL_PF6MFP_Msk          (0xful << SYS_GPF_MFPL_PF6MFP_Pos)                /*!< SYS_T::GPF_MFPL: PF6MFP Mask           */
+
+#define SYS_GPF_MFPL_PF7MFP_Pos          (28)                                              /*!< SYS_T::GPF_MFPL: PF7MFP Position       */
+#define SYS_GPF_MFPL_PF7MFP_Msk          (0xful << SYS_GPF_MFPL_PF7MFP_Pos)                /*!< SYS_T::GPF_MFPL: PF7MFP Mask           */
+
+#define SYS_GPF_MFPH_PF8MFP_Pos          (0)                                               /*!< SYS_T::GPF_MFPH: PF8MFP Position       */
+#define SYS_GPF_MFPH_PF8MFP_Msk          (0xful << SYS_GPF_MFPH_PF8MFP_Pos)                /*!< SYS_T::GPF_MFPH: PF8MFP Mask           */
+
+#define SYS_GPF_MFPH_PF9MFP_Pos          (4)                                               /*!< SYS_T::GPF_MFPH: PF9MFP Position       */
+#define SYS_GPF_MFPH_PF9MFP_Msk          (0xful << SYS_GPF_MFPH_PF9MFP_Pos)                /*!< SYS_T::GPF_MFPH: PF9MFP Mask           */
+
+#define SYS_GPF_MFPH_PF10MFP_Pos         (8)                                               /*!< SYS_T::GPF_MFPH: PF10MFP Position      */
+#define SYS_GPF_MFPH_PF10MFP_Msk         (0xful << SYS_GPF_MFPH_PF10MFP_Pos)               /*!< SYS_T::GPF_MFPH: PF10MFP Mask          */
+
+#define SYS_GPF_MFPH_PF11MFP_Pos         (12)                                              /*!< SYS_T::GPF_MFPH: PF11MFP Position      */
+#define SYS_GPF_MFPH_PF11MFP_Msk         (0xful << SYS_GPF_MFPH_PF11MFP_Pos)               /*!< SYS_T::GPF_MFPH: PF11MFP Mask          */
+
+#define SYS_GPG_MFPL_PG2MFP_Pos          (8)                                               /*!< SYS_T::GPG_MFPL: PG2MFP Position       */
+#define SYS_GPG_MFPL_PG2MFP_Msk          (0xful << SYS_GPG_MFPL_PG2MFP_Pos)                /*!< SYS_T::GPG_MFPL: PG2MFP Mask           */
+
+#define SYS_GPG_MFPL_PG3MFP_Pos          (12)                                              /*!< SYS_T::GPG_MFPL: PG3MFP Position       */
+#define SYS_GPG_MFPL_PG3MFP_Msk          (0xful << SYS_GPG_MFPL_PG3MFP_Pos)                /*!< SYS_T::GPG_MFPL: PG3MFP Mask           */
+
+#define SYS_GPG_MFPL_PG4MFP_Pos          (16)                                              /*!< SYS_T::GPG_MFPL: PG4MFP Position       */
+#define SYS_GPG_MFPL_PG4MFP_Msk          (0xful << SYS_GPG_MFPL_PG4MFP_Pos)                /*!< SYS_T::GPG_MFPL: PG4MFP Mask           */
+
+#define SYS_GPG_MFPH_PG9MFP_Pos          (4)                                               /*!< SYS_T::GPG_MFPH: PG9MFP Position       */
+#define SYS_GPG_MFPH_PG9MFP_Msk          (0xful << SYS_GPG_MFPH_PG9MFP_Pos)                /*!< SYS_T::GPG_MFPH: PG9MFP Mask           */
+
+#define SYS_GPG_MFPH_PG10MFP_Pos         (8)                                               /*!< SYS_T::GPG_MFPH: PG10MFP Position      */
+#define SYS_GPG_MFPH_PG10MFP_Msk         (0xful << SYS_GPG_MFPH_PG10MFP_Pos)               /*!< SYS_T::GPG_MFPH: PG10MFP Mask          */
+
+#define SYS_GPG_MFPH_PG11MFP_Pos         (12)                                              /*!< SYS_T::GPG_MFPH: PG11MFP Position      */
+#define SYS_GPG_MFPH_PG11MFP_Msk         (0xful << SYS_GPG_MFPH_PG11MFP_Pos)               /*!< SYS_T::GPG_MFPH: PG11MFP Mask          */
+
+#define SYS_GPG_MFPH_PG12MFP_Pos         (16)                                              /*!< SYS_T::GPG_MFPH: PG12MFP Position      */
+#define SYS_GPG_MFPH_PG12MFP_Msk         (0xful << SYS_GPG_MFPH_PG12MFP_Pos)               /*!< SYS_T::GPG_MFPH: PG12MFP Mask          */
+
+#define SYS_GPG_MFPH_PG13MFP_Pos         (20)                                              /*!< SYS_T::GPG_MFPH: PG13MFP Position      */
+#define SYS_GPG_MFPH_PG13MFP_Msk         (0xful << SYS_GPG_MFPH_PG13MFP_Pos)               /*!< SYS_T::GPG_MFPH: PG13MFP Mask          */
+
+#define SYS_GPG_MFPH_PG14MFP_Pos         (24)                                              /*!< SYS_T::GPG_MFPH: PG14MFP Position      */
+#define SYS_GPG_MFPH_PG14MFP_Msk         (0xful << SYS_GPG_MFPH_PG14MFP_Pos)               /*!< SYS_T::GPG_MFPH: PG14MFP Mask          */
+
+#define SYS_GPG_MFPH_PG15MFP_Pos         (28)                                              /*!< SYS_T::GPG_MFPH: PG15MFP Position      */
+#define SYS_GPG_MFPH_PG15MFP_Msk         (0xful << SYS_GPG_MFPH_PG15MFP_Pos)               /*!< SYS_T::GPG_MFPH: PG15MFP Mask          */
+
+#define SYS_GPH_MFPL_PH4MFP_Pos          (16)                                              /*!< SYS_T::GPH_MFPL: PH4MFP Position       */
+#define SYS_GPH_MFPL_PH4MFP_Msk          (0xful << SYS_GPH_MFPL_PH4MFP_Pos)                /*!< SYS_T::GPH_MFPL: PH4MFP Mask           */
+
+#define SYS_GPH_MFPL_PH5MFP_Pos          (20)                                              /*!< SYS_T::GPH_MFPL: PH5MFP Position       */
+#define SYS_GPH_MFPL_PH5MFP_Msk          (0xful << SYS_GPH_MFPL_PH5MFP_Pos)                /*!< SYS_T::GPH_MFPL: PH5MFP Mask           */
+
+#define SYS_GPH_MFPL_PH6MFP_Pos          (24)                                              /*!< SYS_T::GPH_MFPL: PH6MFP Position       */
+#define SYS_GPH_MFPL_PH6MFP_Msk          (0xful << SYS_GPH_MFPL_PH6MFP_Pos)                /*!< SYS_T::GPH_MFPL: PH6MFP Mask           */
+
+#define SYS_GPH_MFPL_PH7MFP_Pos          (28)                                              /*!< SYS_T::GPH_MFPL: PH7MFP Position       */
+#define SYS_GPH_MFPL_PH7MFP_Msk          (0xful << SYS_GPH_MFPL_PH7MFP_Pos)                /*!< SYS_T::GPH_MFPL: PH7MFP Mask           */
+
+#define SYS_GPH_MFPH_PH8MFP_Pos          (0)                                               /*!< SYS_T::GPH_MFPH: PH8MFP Position       */
+#define SYS_GPH_MFPH_PH8MFP_Msk          (0xful << SYS_GPH_MFPH_PH8MFP_Pos)                /*!< SYS_T::GPH_MFPH: PH8MFP Mask           */
+
+#define SYS_GPH_MFPH_PH9MFP_Pos          (4)                                               /*!< SYS_T::GPH_MFPH: PH9MFP Position       */
+#define SYS_GPH_MFPH_PH9MFP_Msk          (0xful << SYS_GPH_MFPH_PH9MFP_Pos)                /*!< SYS_T::GPH_MFPH: PH9MFP Mask           */
+
+#define SYS_GPH_MFPH_PH10MFP_Pos         (8)                                               /*!< SYS_T::GPH_MFPH: PH10MFP Position      */
+#define SYS_GPH_MFPH_PH10MFP_Msk         (0xful << SYS_GPH_MFPH_PH10MFP_Pos)               /*!< SYS_T::GPH_MFPH: PH10MFP Mask          */
+
+#define SYS_GPH_MFPH_PH11MFP_Pos         (12)                                              /*!< SYS_T::GPH_MFPH: PH11MFP Position      */
+#define SYS_GPH_MFPH_PH11MFP_Msk         (0xful << SYS_GPH_MFPH_PH11MFP_Pos)               /*!< SYS_T::GPH_MFPH: PH11MFP Mask          */
+
+#define SYS_GPA_MFOS_MFOS0_Pos           (0)                                               /*!< SYS_T::GPA_MFOS: MFOS0 Position        */
+#define SYS_GPA_MFOS_MFOS0_Msk           (0x1ul << SYS_GPA_MFOS_MFOS0_Pos)                 /*!< SYS_T::GPA_MFOS: MFOS0 Mask            */
+
+#define SYS_GPA_MFOS_MFOS1_Pos           (1)                                               /*!< SYS_T::GPA_MFOS: MFOS1 Position        */
+#define SYS_GPA_MFOS_MFOS1_Msk           (0x1ul << SYS_GPA_MFOS_MFOS1_Pos)                 /*!< SYS_T::GPA_MFOS: MFOS1 Mask            */
+
+#define SYS_GPA_MFOS_MFOS2_Pos           (2)                                               /*!< SYS_T::GPA_MFOS: MFOS2 Position        */
+#define SYS_GPA_MFOS_MFOS2_Msk           (0x1ul << SYS_GPA_MFOS_MFOS2_Pos)                 /*!< SYS_T::GPA_MFOS: MFOS2 Mask            */
+
+#define SYS_GPA_MFOS_MFOS3_Pos           (3)                                               /*!< SYS_T::GPA_MFOS: MFOS3 Position        */
+#define SYS_GPA_MFOS_MFOS3_Msk           (0x1ul << SYS_GPA_MFOS_MFOS3_Pos)                 /*!< SYS_T::GPA_MFOS: MFOS3 Mask            */
+
+#define SYS_GPA_MFOS_MFOS4_Pos           (4)                                               /*!< SYS_T::GPA_MFOS: MFOS4 Position        */
+#define SYS_GPA_MFOS_MFOS4_Msk           (0x1ul << SYS_GPA_MFOS_MFOS4_Pos)                 /*!< SYS_T::GPA_MFOS: MFOS4 Mask            */
+
+#define SYS_GPA_MFOS_MFOS5_Pos           (5)                                               /*!< SYS_T::GPA_MFOS: MFOS5 Position        */
+#define SYS_GPA_MFOS_MFOS5_Msk           (0x1ul << SYS_GPA_MFOS_MFOS5_Pos)                 /*!< SYS_T::GPA_MFOS: MFOS5 Mask            */
+
+#define SYS_GPA_MFOS_MFOS6_Pos           (6)                                               /*!< SYS_T::GPA_MFOS: MFOS6 Position        */
+#define SYS_GPA_MFOS_MFOS6_Msk           (0x1ul << SYS_GPA_MFOS_MFOS6_Pos)                 /*!< SYS_T::GPA_MFOS: MFOS6 Mask            */
+
+#define SYS_GPA_MFOS_MFOS7_Pos           (7)                                               /*!< SYS_T::GPA_MFOS: MFOS7 Position        */
+#define SYS_GPA_MFOS_MFOS7_Msk           (0x1ul << SYS_GPA_MFOS_MFOS7_Pos)                 /*!< SYS_T::GPA_MFOS: MFOS7 Mask            */
+
+#define SYS_GPA_MFOS_MFOS8_Pos           (8)                                               /*!< SYS_T::GPA_MFOS: MFOS8 Position        */
+#define SYS_GPA_MFOS_MFOS8_Msk           (0x1ul << SYS_GPA_MFOS_MFOS8_Pos)                 /*!< SYS_T::GPA_MFOS: MFOS8 Mask            */
+
+#define SYS_GPA_MFOS_MFOS9_Pos           (9)                                               /*!< SYS_T::GPA_MFOS: MFOS9 Position        */
+#define SYS_GPA_MFOS_MFOS9_Msk           (0x1ul << SYS_GPA_MFOS_MFOS9_Pos)                 /*!< SYS_T::GPA_MFOS: MFOS9 Mask            */
+
+#define SYS_GPA_MFOS_MFOS10_Pos          (10)                                              /*!< SYS_T::GPA_MFOS: MFOS10 Position       */
+#define SYS_GPA_MFOS_MFOS10_Msk          (0x1ul << SYS_GPA_MFOS_MFOS10_Pos)                /*!< SYS_T::GPA_MFOS: MFOS10 Mask           */
+
+#define SYS_GPA_MFOS_MFOS11_Pos          (11)                                              /*!< SYS_T::GPA_MFOS: MFOS11 Position       */
+#define SYS_GPA_MFOS_MFOS11_Msk          (0x1ul << SYS_GPA_MFOS_MFOS11_Pos)                /*!< SYS_T::GPA_MFOS: MFOS11 Mask           */
+
+#define SYS_GPA_MFOS_MFOS12_Pos          (12)                                              /*!< SYS_T::GPA_MFOS: MFOS12 Position       */
+#define SYS_GPA_MFOS_MFOS12_Msk          (0x1ul << SYS_GPA_MFOS_MFOS12_Pos)                /*!< SYS_T::GPA_MFOS: MFOS12 Mask           */
+
+#define SYS_GPA_MFOS_MFOS13_Pos          (13)                                              /*!< SYS_T::GPA_MFOS: MFOS13 Position       */
+#define SYS_GPA_MFOS_MFOS13_Msk          (0x1ul << SYS_GPA_MFOS_MFOS13_Pos)                /*!< SYS_T::GPA_MFOS: MFOS13 Mask           */
+
+#define SYS_GPA_MFOS_MFOS14_Pos          (14)                                              /*!< SYS_T::GPA_MFOS: MFOS14 Position       */
+#define SYS_GPA_MFOS_MFOS14_Msk          (0x1ul << SYS_GPA_MFOS_MFOS14_Pos)                /*!< SYS_T::GPA_MFOS: MFOS14 Mask           */
+
+#define SYS_GPA_MFOS_MFOS15_Pos          (15)                                              /*!< SYS_T::GPA_MFOS: MFOS15 Position       */
+#define SYS_GPA_MFOS_MFOS15_Msk          (0x1ul << SYS_GPA_MFOS_MFOS15_Pos)                /*!< SYS_T::GPA_MFOS: MFOS15 Mask           */
+
+#define SYS_GPB_MFOS_MFOS0_Pos           (0)                                               /*!< SYS_T::GPB_MFOS: MFOS0 Position        */
+#define SYS_GPB_MFOS_MFOS0_Msk           (0x1ul << SYS_GPB_MFOS_MFOS0_Pos)                 /*!< SYS_T::GPB_MFOS: MFOS0 Mask            */
+
+#define SYS_GPB_MFOS_MFOS1_Pos           (1)                                               /*!< SYS_T::GPB_MFOS: MFOS1 Position        */
+#define SYS_GPB_MFOS_MFOS1_Msk           (0x1ul << SYS_GPB_MFOS_MFOS1_Pos)                 /*!< SYS_T::GPB_MFOS: MFOS1 Mask            */
+
+#define SYS_GPB_MFOS_MFOS2_Pos           (2)                                               /*!< SYS_T::GPB_MFOS: MFOS2 Position        */
+#define SYS_GPB_MFOS_MFOS2_Msk           (0x1ul << SYS_GPB_MFOS_MFOS2_Pos)                 /*!< SYS_T::GPB_MFOS: MFOS2 Mask            */
+
+#define SYS_GPB_MFOS_MFOS3_Pos           (3)                                               /*!< SYS_T::GPB_MFOS: MFOS3 Position        */
+#define SYS_GPB_MFOS_MFOS3_Msk           (0x1ul << SYS_GPB_MFOS_MFOS3_Pos)                 /*!< SYS_T::GPB_MFOS: MFOS3 Mask            */
+
+#define SYS_GPB_MFOS_MFOS4_Pos           (4)                                               /*!< SYS_T::GPB_MFOS: MFOS4 Position        */
+#define SYS_GPB_MFOS_MFOS4_Msk           (0x1ul << SYS_GPB_MFOS_MFOS4_Pos)                 /*!< SYS_T::GPB_MFOS: MFOS4 Mask            */
+
+#define SYS_GPB_MFOS_MFOS5_Pos           (5)                                               /*!< SYS_T::GPB_MFOS: MFOS5 Position        */
+#define SYS_GPB_MFOS_MFOS5_Msk           (0x1ul << SYS_GPB_MFOS_MFOS5_Pos)                 /*!< SYS_T::GPB_MFOS: MFOS5 Mask            */
+
+#define SYS_GPB_MFOS_MFOS6_Pos           (6)                                               /*!< SYS_T::GPB_MFOS: MFOS6 Position        */
+#define SYS_GPB_MFOS_MFOS6_Msk           (0x1ul << SYS_GPB_MFOS_MFOS6_Pos)                 /*!< SYS_T::GPB_MFOS: MFOS6 Mask            */
+
+#define SYS_GPB_MFOS_MFOS7_Pos           (7)                                               /*!< SYS_T::GPB_MFOS: MFOS7 Position        */
+#define SYS_GPB_MFOS_MFOS7_Msk           (0x1ul << SYS_GPB_MFOS_MFOS7_Pos)                 /*!< SYS_T::GPB_MFOS: MFOS7 Mask            */
+
+#define SYS_GPB_MFOS_MFOS8_Pos           (8)                                               /*!< SYS_T::GPB_MFOS: MFOS8 Position        */
+#define SYS_GPB_MFOS_MFOS8_Msk           (0x1ul << SYS_GPB_MFOS_MFOS8_Pos)                 /*!< SYS_T::GPB_MFOS: MFOS8 Mask            */
+
+#define SYS_GPB_MFOS_MFOS9_Pos           (9)                                               /*!< SYS_T::GPB_MFOS: MFOS9 Position        */
+#define SYS_GPB_MFOS_MFOS9_Msk           (0x1ul << SYS_GPB_MFOS_MFOS9_Pos)                 /*!< SYS_T::GPB_MFOS: MFOS9 Mask            */
+
+#define SYS_GPB_MFOS_MFOS10_Pos          (10)                                              /*!< SYS_T::GPB_MFOS: MFOS10 Position       */
+#define SYS_GPB_MFOS_MFOS10_Msk          (0x1ul << SYS_GPB_MFOS_MFOS10_Pos)                /*!< SYS_T::GPB_MFOS: MFOS10 Mask           */
+
+#define SYS_GPB_MFOS_MFOS11_Pos          (11)                                              /*!< SYS_T::GPB_MFOS: MFOS11 Position       */
+#define SYS_GPB_MFOS_MFOS11_Msk          (0x1ul << SYS_GPB_MFOS_MFOS11_Pos)                /*!< SYS_T::GPB_MFOS: MFOS11 Mask           */
+
+#define SYS_GPB_MFOS_MFOS12_Pos          (12)                                              /*!< SYS_T::GPB_MFOS: MFOS12 Position       */
+#define SYS_GPB_MFOS_MFOS12_Msk          (0x1ul << SYS_GPB_MFOS_MFOS12_Pos)                /*!< SYS_T::GPB_MFOS: MFOS12 Mask           */
+
+#define SYS_GPB_MFOS_MFOS13_Pos          (13)                                              /*!< SYS_T::GPB_MFOS: MFOS13 Position       */
+#define SYS_GPB_MFOS_MFOS13_Msk          (0x1ul << SYS_GPB_MFOS_MFOS13_Pos)                /*!< SYS_T::GPB_MFOS: MFOS13 Mask           */
+
+#define SYS_GPB_MFOS_MFOS14_Pos          (14)                                              /*!< SYS_T::GPB_MFOS: MFOS14 Position       */
+#define SYS_GPB_MFOS_MFOS14_Msk          (0x1ul << SYS_GPB_MFOS_MFOS14_Pos)                /*!< SYS_T::GPB_MFOS: MFOS14 Mask           */
+
+#define SYS_GPB_MFOS_MFOS15_Pos          (15)                                              /*!< SYS_T::GPB_MFOS: MFOS15 Position       */
+#define SYS_GPB_MFOS_MFOS15_Msk          (0x1ul << SYS_GPB_MFOS_MFOS15_Pos)                /*!< SYS_T::GPB_MFOS: MFOS15 Mask           */
+
+#define SYS_GPC_MFOS_MFOS0_Pos           (0)                                               /*!< SYS_T::GPC_MFOS: MFOS0 Position        */
+#define SYS_GPC_MFOS_MFOS0_Msk           (0x1ul << SYS_GPC_MFOS_MFOS0_Pos)                 /*!< SYS_T::GPC_MFOS: MFOS0 Mask            */
+
+#define SYS_GPC_MFOS_MFOS1_Pos           (1)                                               /*!< SYS_T::GPC_MFOS: MFOS1 Position        */
+#define SYS_GPC_MFOS_MFOS1_Msk           (0x1ul << SYS_GPC_MFOS_MFOS1_Pos)                 /*!< SYS_T::GPC_MFOS: MFOS1 Mask            */
+
+#define SYS_GPC_MFOS_MFOS2_Pos           (2)                                               /*!< SYS_T::GPC_MFOS: MFOS2 Position        */
+#define SYS_GPC_MFOS_MFOS2_Msk           (0x1ul << SYS_GPC_MFOS_MFOS2_Pos)                 /*!< SYS_T::GPC_MFOS: MFOS2 Mask            */
+
+#define SYS_GPC_MFOS_MFOS3_Pos           (3)                                               /*!< SYS_T::GPC_MFOS: MFOS3 Position        */
+#define SYS_GPC_MFOS_MFOS3_Msk           (0x1ul << SYS_GPC_MFOS_MFOS3_Pos)                 /*!< SYS_T::GPC_MFOS: MFOS3 Mask            */
+
+#define SYS_GPC_MFOS_MFOS4_Pos           (4)                                               /*!< SYS_T::GPC_MFOS: MFOS4 Position        */
+#define SYS_GPC_MFOS_MFOS4_Msk           (0x1ul << SYS_GPC_MFOS_MFOS4_Pos)                 /*!< SYS_T::GPC_MFOS: MFOS4 Mask            */
+
+#define SYS_GPC_MFOS_MFOS5_Pos           (5)                                               /*!< SYS_T::GPC_MFOS: MFOS5 Position        */
+#define SYS_GPC_MFOS_MFOS5_Msk           (0x1ul << SYS_GPC_MFOS_MFOS5_Pos)                 /*!< SYS_T::GPC_MFOS: MFOS5 Mask            */
+
+#define SYS_GPC_MFOS_MFOS6_Pos           (6)                                               /*!< SYS_T::GPC_MFOS: MFOS6 Position        */
+#define SYS_GPC_MFOS_MFOS6_Msk           (0x1ul << SYS_GPC_MFOS_MFOS6_Pos)                 /*!< SYS_T::GPC_MFOS: MFOS6 Mask            */
+
+#define SYS_GPC_MFOS_MFOS7_Pos           (7)                                               /*!< SYS_T::GPC_MFOS: MFOS7 Position        */
+#define SYS_GPC_MFOS_MFOS7_Msk           (0x1ul << SYS_GPC_MFOS_MFOS7_Pos)                 /*!< SYS_T::GPC_MFOS: MFOS7 Mask            */
+
+#define SYS_GPC_MFOS_MFOS8_Pos           (8)                                               /*!< SYS_T::GPC_MFOS: MFOS8 Position        */
+#define SYS_GPC_MFOS_MFOS8_Msk           (0x1ul << SYS_GPC_MFOS_MFOS8_Pos)                 /*!< SYS_T::GPC_MFOS: MFOS8 Mask            */
+
+#define SYS_GPC_MFOS_MFOS9_Pos           (9)                                               /*!< SYS_T::GPC_MFOS: MFOS9 Position        */
+#define SYS_GPC_MFOS_MFOS9_Msk           (0x1ul << SYS_GPC_MFOS_MFOS9_Pos)                 /*!< SYS_T::GPC_MFOS: MFOS9 Mask            */
+
+#define SYS_GPC_MFOS_MFOS10_Pos          (10)                                              /*!< SYS_T::GPC_MFOS: MFOS10 Position       */
+#define SYS_GPC_MFOS_MFOS10_Msk          (0x1ul << SYS_GPC_MFOS_MFOS10_Pos)                /*!< SYS_T::GPC_MFOS: MFOS10 Mask           */
+
+#define SYS_GPC_MFOS_MFOS11_Pos          (11)                                              /*!< SYS_T::GPC_MFOS: MFOS11 Position       */
+#define SYS_GPC_MFOS_MFOS11_Msk          (0x1ul << SYS_GPC_MFOS_MFOS11_Pos)                /*!< SYS_T::GPC_MFOS: MFOS11 Mask           */
+
+#define SYS_GPC_MFOS_MFOS12_Pos          (12)                                              /*!< SYS_T::GPC_MFOS: MFOS12 Position       */
+#define SYS_GPC_MFOS_MFOS12_Msk          (0x1ul << SYS_GPC_MFOS_MFOS12_Pos)                /*!< SYS_T::GPC_MFOS: MFOS12 Mask           */
+
+#define SYS_GPC_MFOS_MFOS13_Pos          (13)                                              /*!< SYS_T::GPC_MFOS: MFOS13 Position       */
+#define SYS_GPC_MFOS_MFOS13_Msk          (0x1ul << SYS_GPC_MFOS_MFOS13_Pos)                /*!< SYS_T::GPC_MFOS: MFOS13 Mask           */
+
+#define SYS_GPD_MFOS_MFOS0_Pos           (0)                                               /*!< SYS_T::GPD_MFOS: MFOS0 Position        */
+#define SYS_GPD_MFOS_MFOS0_Msk           (0x1ul << SYS_GPD_MFOS_MFOS0_Pos)                 /*!< SYS_T::GPD_MFOS: MFOS0 Mask            */
+
+#define SYS_GPD_MFOS_MFOS1_Pos           (1)                                               /*!< SYS_T::GPD_MFOS: MFOS1 Position        */
+#define SYS_GPD_MFOS_MFOS1_Msk           (0x1ul << SYS_GPD_MFOS_MFOS1_Pos)                 /*!< SYS_T::GPD_MFOS: MFOS1 Mask            */
+
+#define SYS_GPD_MFOS_MFOS2_Pos           (2)                                               /*!< SYS_T::GPD_MFOS: MFOS2 Position        */
+#define SYS_GPD_MFOS_MFOS2_Msk           (0x1ul << SYS_GPD_MFOS_MFOS2_Pos)                 /*!< SYS_T::GPD_MFOS: MFOS2 Mask            */
+
+#define SYS_GPD_MFOS_MFOS3_Pos           (3)                                               /*!< SYS_T::GPD_MFOS: MFOS3 Position        */
+#define SYS_GPD_MFOS_MFOS3_Msk           (0x1ul << SYS_GPD_MFOS_MFOS3_Pos)                 /*!< SYS_T::GPD_MFOS: MFOS3 Mask            */
+
+#define SYS_GPD_MFOS_MFOS4_Pos           (4)                                               /*!< SYS_T::GPD_MFOS: MFOS4 Position        */
+#define SYS_GPD_MFOS_MFOS4_Msk           (0x1ul << SYS_GPD_MFOS_MFOS4_Pos)                 /*!< SYS_T::GPD_MFOS: MFOS4 Mask            */
+
+#define SYS_GPD_MFOS_MFOS5_Pos           (5)                                               /*!< SYS_T::GPD_MFOS: MFOS5 Position        */
+#define SYS_GPD_MFOS_MFOS5_Msk           (0x1ul << SYS_GPD_MFOS_MFOS5_Pos)                 /*!< SYS_T::GPD_MFOS: MFOS5 Mask            */
+
+#define SYS_GPD_MFOS_MFOS6_Pos           (6)                                               /*!< SYS_T::GPD_MFOS: MFOS6 Position        */
+#define SYS_GPD_MFOS_MFOS6_Msk           (0x1ul << SYS_GPD_MFOS_MFOS6_Pos)                 /*!< SYS_T::GPD_MFOS: MFOS6 Mask            */
+
+#define SYS_GPD_MFOS_MFOS7_Pos           (7)                                               /*!< SYS_T::GPD_MFOS: MFOS7 Position        */
+#define SYS_GPD_MFOS_MFOS7_Msk           (0x1ul << SYS_GPD_MFOS_MFOS7_Pos)                 /*!< SYS_T::GPD_MFOS: MFOS7 Mask            */
+
+#define SYS_GPD_MFOS_MFOS8_Pos           (8)                                               /*!< SYS_T::GPD_MFOS: MFOS8 Position        */
+#define SYS_GPD_MFOS_MFOS8_Msk           (0x1ul << SYS_GPD_MFOS_MFOS8_Pos)                 /*!< SYS_T::GPD_MFOS: MFOS8 Mask            */
+
+#define SYS_GPD_MFOS_MFOS9_Pos           (9)                                               /*!< SYS_T::GPD_MFOS: MFOS9 Position        */
+#define SYS_GPD_MFOS_MFOS9_Msk           (0x1ul << SYS_GPD_MFOS_MFOS9_Pos)                 /*!< SYS_T::GPD_MFOS: MFOS9 Mask            */
+
+#define SYS_GPD_MFOS_MFOS10_Pos          (10)                                              /*!< SYS_T::GPD_MFOS: MFOS10 Position       */
+#define SYS_GPD_MFOS_MFOS10_Msk          (0x1ul << SYS_GPD_MFOS_MFOS10_Pos)                /*!< SYS_T::GPD_MFOS: MFOS10 Mask           */
+
+#define SYS_GPD_MFOS_MFOS11_Pos          (11)                                              /*!< SYS_T::GPD_MFOS: MFOS11 Position       */
+#define SYS_GPD_MFOS_MFOS11_Msk          (0x1ul << SYS_GPD_MFOS_MFOS11_Pos)                /*!< SYS_T::GPD_MFOS: MFOS11 Mask           */
+
+#define SYS_GPD_MFOS_MFOS12_Pos          (12)                                              /*!< SYS_T::GPD_MFOS: MFOS12 Position       */
+#define SYS_GPD_MFOS_MFOS12_Msk          (0x1ul << SYS_GPD_MFOS_MFOS12_Pos)                /*!< SYS_T::GPD_MFOS: MFOS12 Mask           */
+
+#define SYS_GPD_MFOS_MFOS14_Pos          (14)                                              /*!< SYS_T::GPD_MFOS: MFOS14 Position       */
+#define SYS_GPD_MFOS_MFOS14_Msk          (0x1ul << SYS_GPD_MFOS_MFOS14_Pos)                /*!< SYS_T::GPD_MFOS: MFOS14 Mask           */
+
+#define SYS_GPE_MFOS_MFOS0_Pos           (0)                                               /*!< SYS_T::GPE_MFOS: MFOS0 Position        */
+#define SYS_GPE_MFOS_MFOS0_Msk           (0x1ul << SYS_GPE_MFOS_MFOS0_Pos)                 /*!< SYS_T::GPE_MFOS: MFOS0 Mask            */
+
+#define SYS_GPE_MFOS_MFOS1_Pos           (1)                                               /*!< SYS_T::GPE_MFOS: MFOS1 Position        */
+#define SYS_GPE_MFOS_MFOS1_Msk           (0x1ul << SYS_GPE_MFOS_MFOS1_Pos)                 /*!< SYS_T::GPE_MFOS: MFOS1 Mask            */
+
+#define SYS_GPE_MFOS_MFOS2_Pos           (2)                                               /*!< SYS_T::GPE_MFOS: MFOS2 Position        */
+#define SYS_GPE_MFOS_MFOS2_Msk           (0x1ul << SYS_GPE_MFOS_MFOS2_Pos)                 /*!< SYS_T::GPE_MFOS: MFOS2 Mask            */
+
+#define SYS_GPE_MFOS_MFOS3_Pos           (3)                                               /*!< SYS_T::GPE_MFOS: MFOS3 Position        */
+#define SYS_GPE_MFOS_MFOS3_Msk           (0x1ul << SYS_GPE_MFOS_MFOS3_Pos)                 /*!< SYS_T::GPE_MFOS: MFOS3 Mask            */
+
+#define SYS_GPE_MFOS_MFOS4_Pos           (4)                                               /*!< SYS_T::GPE_MFOS: MFOS4 Position        */
+#define SYS_GPE_MFOS_MFOS4_Msk           (0x1ul << SYS_GPE_MFOS_MFOS4_Pos)                 /*!< SYS_T::GPE_MFOS: MFOS4 Mask            */
+
+#define SYS_GPE_MFOS_MFOS5_Pos           (5)                                               /*!< SYS_T::GPE_MFOS: MFOS5 Position        */
+#define SYS_GPE_MFOS_MFOS5_Msk           (0x1ul << SYS_GPE_MFOS_MFOS5_Pos)                 /*!< SYS_T::GPE_MFOS: MFOS5 Mask            */
+
+#define SYS_GPE_MFOS_MFOS6_Pos           (6)                                               /*!< SYS_T::GPE_MFOS: MFOS6 Position        */
+#define SYS_GPE_MFOS_MFOS6_Msk           (0x1ul << SYS_GPE_MFOS_MFOS6_Pos)                 /*!< SYS_T::GPE_MFOS: MFOS6 Mask            */
+
+#define SYS_GPE_MFOS_MFOS7_Pos           (7)                                               /*!< SYS_T::GPE_MFOS: MFOS7 Position        */
+#define SYS_GPE_MFOS_MFOS7_Msk           (0x1ul << SYS_GPE_MFOS_MFOS7_Pos)                 /*!< SYS_T::GPE_MFOS: MFOS7 Mask            */
+
+#define SYS_GPE_MFOS_MFOS8_Pos           (8)                                               /*!< SYS_T::GPE_MFOS: MFOS8 Position        */
+#define SYS_GPE_MFOS_MFOS8_Msk           (0x1ul << SYS_GPE_MFOS_MFOS8_Pos)                 /*!< SYS_T::GPE_MFOS: MFOS8 Mask            */
+
+#define SYS_GPE_MFOS_MFOS9_Pos           (9)                                               /*!< SYS_T::GPE_MFOS: MFOS9 Position        */
+#define SYS_GPE_MFOS_MFOS9_Msk           (0x1ul << SYS_GPE_MFOS_MFOS9_Pos)                 /*!< SYS_T::GPE_MFOS: MFOS9 Mask            */
+
+#define SYS_GPE_MFOS_MFOS10_Pos          (10)                                              /*!< SYS_T::GPE_MFOS: MFOS10 Position       */
+#define SYS_GPE_MFOS_MFOS10_Msk          (0x1ul << SYS_GPE_MFOS_MFOS10_Pos)                /*!< SYS_T::GPE_MFOS: MFOS10 Mask           */
+
+#define SYS_GPE_MFOS_MFOS11_Pos          (11)                                              /*!< SYS_T::GPE_MFOS: MFOS11 Position       */
+#define SYS_GPE_MFOS_MFOS11_Msk          (0x1ul << SYS_GPE_MFOS_MFOS11_Pos)                /*!< SYS_T::GPE_MFOS: MFOS11 Mask           */
+
+#define SYS_GPE_MFOS_MFOS12_Pos          (12)                                              /*!< SYS_T::GPE_MFOS: MFOS12 Position       */
+#define SYS_GPE_MFOS_MFOS12_Msk          (0x1ul << SYS_GPE_MFOS_MFOS12_Pos)                /*!< SYS_T::GPE_MFOS: MFOS12 Mask           */
+
+#define SYS_GPE_MFOS_MFOS13_Pos          (13)                                              /*!< SYS_T::GPE_MFOS: MFOS13 Position       */
+#define SYS_GPE_MFOS_MFOS13_Msk          (0x1ul << SYS_GPE_MFOS_MFOS13_Pos)                /*!< SYS_T::GPE_MFOS: MFOS13 Mask           */
+
+#define SYS_GPE_MFOS_MFOS14_Pos          (14)                                              /*!< SYS_T::GPE_MFOS: MFOS14 Position       */
+#define SYS_GPE_MFOS_MFOS14_Msk          (0x1ul << SYS_GPE_MFOS_MFOS14_Pos)                /*!< SYS_T::GPE_MFOS: MFOS14 Mask           */
+
+#define SYS_GPE_MFOS_MFOS15_Pos          (15)                                              /*!< SYS_T::GPE_MFOS: MFOS15 Position       */
+#define SYS_GPE_MFOS_MFOS15_Msk          (0x1ul << SYS_GPE_MFOS_MFOS15_Pos)                /*!< SYS_T::GPE_MFOS: MFOS15 Mask           */
+
+#define SYS_GPF_MFOS_MFOS0_Pos           (0)                                               /*!< SYS_T::GPF_MFOS: MFOS0 Position        */
+#define SYS_GPF_MFOS_MFOS0_Msk           (0x1ul << SYS_GPF_MFOS_MFOS0_Pos)                 /*!< SYS_T::GPF_MFOS: MFOS0 Mask            */
+
+#define SYS_GPF_MFOS_MFOS1_Pos           (1)                                               /*!< SYS_T::GPF_MFOS: MFOS1 Position        */
+#define SYS_GPF_MFOS_MFOS1_Msk           (0x1ul << SYS_GPF_MFOS_MFOS1_Pos)                 /*!< SYS_T::GPF_MFOS: MFOS1 Mask            */
+
+#define SYS_GPF_MFOS_MFOS2_Pos           (2)                                               /*!< SYS_T::GPF_MFOS: MFOS2 Position        */
+#define SYS_GPF_MFOS_MFOS2_Msk           (0x1ul << SYS_GPF_MFOS_MFOS2_Pos)                 /*!< SYS_T::GPF_MFOS: MFOS2 Mask            */
+
+#define SYS_GPF_MFOS_MFOS3_Pos           (3)                                               /*!< SYS_T::GPF_MFOS: MFOS3 Position        */
+#define SYS_GPF_MFOS_MFOS3_Msk           (0x1ul << SYS_GPF_MFOS_MFOS3_Pos)                 /*!< SYS_T::GPF_MFOS: MFOS3 Mask            */
+
+#define SYS_GPF_MFOS_MFOS4_Pos           (4)                                               /*!< SYS_T::GPF_MFOS: MFOS4 Position        */
+#define SYS_GPF_MFOS_MFOS4_Msk           (0x1ul << SYS_GPF_MFOS_MFOS4_Pos)                 /*!< SYS_T::GPF_MFOS: MFOS4 Mask            */
+
+#define SYS_GPF_MFOS_MFOS5_Pos           (5)                                               /*!< SYS_T::GPF_MFOS: MFOS5 Position        */
+#define SYS_GPF_MFOS_MFOS5_Msk           (0x1ul << SYS_GPF_MFOS_MFOS5_Pos)                 /*!< SYS_T::GPF_MFOS: MFOS5 Mask            */
+
+#define SYS_GPF_MFOS_MFOS6_Pos           (6)                                               /*!< SYS_T::GPF_MFOS: MFOS6 Position        */
+#define SYS_GPF_MFOS_MFOS6_Msk           (0x1ul << SYS_GPF_MFOS_MFOS6_Pos)                 /*!< SYS_T::GPF_MFOS: MFOS6 Mask            */
+
+#define SYS_GPF_MFOS_MFOS7_Pos           (7)                                               /*!< SYS_T::GPF_MFOS: MFOS7 Position        */
+#define SYS_GPF_MFOS_MFOS7_Msk           (0x1ul << SYS_GPF_MFOS_MFOS7_Pos)                 /*!< SYS_T::GPF_MFOS: MFOS7 Mask            */
+
+#define SYS_GPF_MFOS_MFOS8_Pos           (8)                                               /*!< SYS_T::GPF_MFOS: MFOS8 Position        */
+#define SYS_GPF_MFOS_MFOS8_Msk           (0x1ul << SYS_GPF_MFOS_MFOS8_Pos)                 /*!< SYS_T::GPF_MFOS: MFOS8 Mask            */
+
+#define SYS_GPF_MFOS_MFOS9_Pos           (9)                                               /*!< SYS_T::GPF_MFOS: MFOS9 Position        */
+#define SYS_GPF_MFOS_MFOS9_Msk           (0x1ul << SYS_GPF_MFOS_MFOS9_Pos)                 /*!< SYS_T::GPF_MFOS: MFOS9 Mask            */
+
+#define SYS_GPF_MFOS_MFOS10_Pos          (10)                                              /*!< SYS_T::GPF_MFOS: MFOS10 Position       */
+#define SYS_GPF_MFOS_MFOS10_Msk          (0x1ul << SYS_GPF_MFOS_MFOS10_Pos)                /*!< SYS_T::GPF_MFOS: MFOS10 Mask           */
+
+#define SYS_GPF_MFOS_MFOS11_Pos          (11)                                              /*!< SYS_T::GPF_MFOS: MFOS11 Position       */
+#define SYS_GPF_MFOS_MFOS11_Msk          (0x1ul << SYS_GPF_MFOS_MFOS11_Pos)                /*!< SYS_T::GPF_MFOS: MFOS11 Mask           */
+
+#define SYS_GPG_MFOS_MFOS2_Pos           (2)                                               /*!< SYS_T::GPG_MFOS: MFOS2 Position        */
+#define SYS_GPG_MFOS_MFOS2_Msk           (0x1ul << SYS_GPG_MFOS_MFOS2_Pos)                 /*!< SYS_T::GPG_MFOS: MFOS2 Mask            */
+
+#define SYS_GPG_MFOS_MFOS3_Pos           (3)                                               /*!< SYS_T::GPG_MFOS: MFOS3 Position        */
+#define SYS_GPG_MFOS_MFOS3_Msk           (0x1ul << SYS_GPG_MFOS_MFOS3_Pos)                 /*!< SYS_T::GPG_MFOS: MFOS3 Mask            */
+
+#define SYS_GPG_MFOS_MFOS4_Pos           (4)                                               /*!< SYS_T::GPG_MFOS: MFOS4 Position        */
+#define SYS_GPG_MFOS_MFOS4_Msk           (0x1ul << SYS_GPG_MFOS_MFOS4_Pos)                 /*!< SYS_T::GPG_MFOS: MFOS4 Mask            */
+
+#define SYS_GPG_MFOS_MFOS9_Pos           (9)                                               /*!< SYS_T::GPG_MFOS: MFOS9 Position        */
+#define SYS_GPG_MFOS_MFOS9_Msk           (0x1ul << SYS_GPG_MFOS_MFOS9_Pos)                 /*!< SYS_T::GPG_MFOS: MFOS9 Mask            */
+
+#define SYS_GPG_MFOS_MFOS10_Pos          (10)                                              /*!< SYS_T::GPG_MFOS: MFOS10 Position       */
+#define SYS_GPG_MFOS_MFOS10_Msk          (0x1ul << SYS_GPG_MFOS_MFOS10_Pos)                /*!< SYS_T::GPG_MFOS: MFOS10 Mask           */
+
+#define SYS_GPG_MFOS_MFOS11_Pos          (11)                                              /*!< SYS_T::GPG_MFOS: MFOS11 Position       */
+#define SYS_GPG_MFOS_MFOS11_Msk          (0x1ul << SYS_GPG_MFOS_MFOS11_Pos)                /*!< SYS_T::GPG_MFOS: MFOS11 Mask           */
+
+#define SYS_GPG_MFOS_MFOS12_Pos          (12)                                              /*!< SYS_T::GPG_MFOS: MFOS12 Position       */
+#define SYS_GPG_MFOS_MFOS12_Msk          (0x1ul << SYS_GPG_MFOS_MFOS12_Pos)                /*!< SYS_T::GPG_MFOS: MFOS12 Mask           */
+
+#define SYS_GPG_MFOS_MFOS13_Pos          (13)                                              /*!< SYS_T::GPG_MFOS: MFOS13 Position       */
+#define SYS_GPG_MFOS_MFOS13_Msk          (0x1ul << SYS_GPG_MFOS_MFOS13_Pos)                /*!< SYS_T::GPG_MFOS: MFOS13 Mask           */
+
+#define SYS_GPG_MFOS_MFOS14_Pos          (14)                                              /*!< SYS_T::GPG_MFOS: MFOS14 Position       */
+#define SYS_GPG_MFOS_MFOS14_Msk          (0x1ul << SYS_GPG_MFOS_MFOS14_Pos)                /*!< SYS_T::GPG_MFOS: MFOS14 Mask           */
+
+#define SYS_GPG_MFOS_MFOS15_Pos          (15)                                              /*!< SYS_T::GPG_MFOS: MFOS15 Position       */
+#define SYS_GPG_MFOS_MFOS15_Msk          (0x1ul << SYS_GPG_MFOS_MFOS15_Pos)                /*!< SYS_T::GPG_MFOS: MFOS15 Mask           */
+
+#define SYS_GPH_MFOS_MFOS4_Pos           (4)                                               /*!< SYS_T::GPH_MFOS: MFOS4 Position        */
+#define SYS_GPH_MFOS_MFOS4_Msk           (0x1ul << SYS_GPH_MFOS_MFOS4_Pos)                 /*!< SYS_T::GPH_MFOS: MFOS4 Mask            */
+
+#define SYS_GPH_MFOS_MFOS5_Pos           (5)                                               /*!< SYS_T::GPH_MFOS: MFOS5 Position        */
+#define SYS_GPH_MFOS_MFOS5_Msk           (0x1ul << SYS_GPH_MFOS_MFOS5_Pos)                 /*!< SYS_T::GPH_MFOS: MFOS5 Mask            */
+
+#define SYS_GPH_MFOS_MFOS6_Pos           (6)                                               /*!< SYS_T::GPH_MFOS: MFOS6 Position        */
+#define SYS_GPH_MFOS_MFOS6_Msk           (0x1ul << SYS_GPH_MFOS_MFOS6_Pos)                 /*!< SYS_T::GPH_MFOS: MFOS6 Mask            */
+
+#define SYS_GPH_MFOS_MFOS7_Pos           (7)                                               /*!< SYS_T::GPH_MFOS: MFOS7 Position        */
+#define SYS_GPH_MFOS_MFOS7_Msk           (0x1ul << SYS_GPH_MFOS_MFOS7_Pos)                 /*!< SYS_T::GPH_MFOS: MFOS7 Mask            */
+
+#define SYS_GPH_MFOS_MFOS8_Pos           (8)                                               /*!< SYS_T::GPH_MFOS: MFOS8 Position        */
+#define SYS_GPH_MFOS_MFOS8_Msk           (0x1ul << SYS_GPH_MFOS_MFOS8_Pos)                 /*!< SYS_T::GPH_MFOS: MFOS8 Mask            */
+
+#define SYS_GPH_MFOS_MFOS9_Pos           (9)                                               /*!< SYS_T::GPH_MFOS: MFOS9 Position        */
+#define SYS_GPH_MFOS_MFOS9_Msk           (0x1ul << SYS_GPH_MFOS_MFOS9_Pos)                 /*!< SYS_T::GPH_MFOS: MFOS9 Mask            */
+
+#define SYS_GPH_MFOS_MFOS10_Pos          (10)                                              /*!< SYS_T::GPH_MFOS: MFOS10 Position       */
+#define SYS_GPH_MFOS_MFOS10_Msk          (0x1ul << SYS_GPH_MFOS_MFOS10_Pos)                /*!< SYS_T::GPH_MFOS: MFOS10 Mask           */
+
+#define SYS_GPH_MFOS_MFOS11_Pos          (11)                                              /*!< SYS_T::GPH_MFOS: MFOS11 Position       */
+#define SYS_GPH_MFOS_MFOS11_Msk          (0x1ul << SYS_GPH_MFOS_MFOS11_Pos)                /*!< SYS_T::GPH_MFOS: MFOS11 Mask           */
+
+#define SYS_VTORSET_VTORSET_Pos          (11)                                              /*!< SYS_T::VTORSET: VTORSET Position       */
+#define SYS_VTORSET_VTORSET_Msk          (0x3fffful << SYS_VTORSET_VTORSET_Pos)            /*!< SYS_T::VTORSET: VTORSET Mask           */
+
+#define SYS_SRAMICTL_PERRIEN_Pos         (0)                                               /*!< SYS_T::SRAMICTL: PERRIEN Position      */
+#define SYS_SRAMICTL_PERRIEN_Msk         (0x1ul << SYS_SRAMICTL_PERRIEN_Pos)               /*!< SYS_T::SRAMICTL: PERRIEN Mask          */
+
+#define SYS_SRAMSTS_PERRIF_Pos           (0)                                               /*!< SYS_T::SRAMSTS: PERRIF Position        */
+#define SYS_SRAMSTS_PERRIF_Msk           (0x1ul << SYS_SRAMSTS_PERRIF_Pos)                 /*!< SYS_T::SRAMSTS: PERRIF Mask            */
+
+#define SYS_SRAMEADR_ERRADDR_Pos         (0)                                               /*!< SYS_T::SRAMEADR: ERRADDR Position      */
+#define SYS_SRAMEADR_ERRADDR_Msk         (0xfffffffful << SYS_SRAMEADR_ERRADDR_Pos)        /*!< SYS_T::SRAMEADR: ERRADDR Mask          */
+
+#define SYS_SRAMPC0_SRAM0PM0_Pos         (0)                                               /*!< SYS_T::SRAMPC0: SRAM0PM0 Position      */
+#define SYS_SRAMPC0_SRAM0PM0_Msk         (0x3ul << SYS_SRAMPC0_SRAM0PM0_Pos)               /*!< SYS_T::SRAMPC0: SRAM0PM0 Mask          */
+
+#define SYS_SRAMPC0_SRAM0PM1_Pos         (2)                                               /*!< SYS_T::SRAMPC0: SRAM0PM1 Position      */
+#define SYS_SRAMPC0_SRAM0PM1_Msk         (0x3ul << SYS_SRAMPC0_SRAM0PM1_Pos)               /*!< SYS_T::SRAMPC0: SRAM0PM1 Mask          */
+
+#define SYS_SRAMPC0_SRAM0PM2_Pos         (4)                                               /*!< SYS_T::SRAMPC0: SRAM0PM2 Position      */
+#define SYS_SRAMPC0_SRAM0PM2_Msk         (0x3ul << SYS_SRAMPC0_SRAM0PM2_Pos)               /*!< SYS_T::SRAMPC0: SRAM0PM2 Mask          */
+
+#define SYS_SRAMPC0_SRAM0PM3_Pos         (6)                                               /*!< SYS_T::SRAMPC0: SRAM0PM3 Position      */
+#define SYS_SRAMPC0_SRAM0PM3_Msk         (0x3ul << SYS_SRAMPC0_SRAM0PM3_Pos)               /*!< SYS_T::SRAMPC0: SRAM0PM3 Mask          */
+
+#define SYS_SRAMPC0_SRAM0PM4_Pos         (8)                                               /*!< SYS_T::SRAMPC0: SRAM0PM4 Position      */
+#define SYS_SRAMPC0_SRAM0PM4_Msk         (0x3ul << SYS_SRAMPC0_SRAM0PM4_Pos)               /*!< SYS_T::SRAMPC0: SRAM0PM4 Mask          */
+
+#define SYS_SRAMPC0_SRAM1PM0_Pos         (10)                                              /*!< SYS_T::SRAMPC0: SRAM1PM0 Position      */
+#define SYS_SRAMPC0_SRAM1PM0_Msk         (0x3ul << SYS_SRAMPC0_SRAM1PM0_Pos)               /*!< SYS_T::SRAMPC0: SRAM1PM0 Mask          */
+
+#define SYS_SRAMPC0_SRAM1PM1_Pos         (12)                                              /*!< SYS_T::SRAMPC0: SRAM1PM1 Position      */
+#define SYS_SRAMPC0_SRAM1PM1_Msk         (0x3ul << SYS_SRAMPC0_SRAM1PM1_Pos)               /*!< SYS_T::SRAMPC0: SRAM1PM1 Mask          */
+
+#define SYS_SRAMPC0_SRAM1PM2_Pos         (14)                                              /*!< SYS_T::SRAMPC0: SRAM1PM2 Position      */
+#define SYS_SRAMPC0_SRAM1PM2_Msk         (0x3ul << SYS_SRAMPC0_SRAM1PM2_Pos)               /*!< SYS_T::SRAMPC0: SRAM1PM2 Mask          */
+
+#define SYS_SRAMPC0_SRAM1PM3_Pos         (16)                                              /*!< SYS_T::SRAMPC0: SRAM1PM3 Position      */
+#define SYS_SRAMPC0_SRAM1PM3_Msk         (0x3ul << SYS_SRAMPC0_SRAM1PM3_Pos)               /*!< SYS_T::SRAMPC0: SRAM1PM3 Mask          */
+
+#define SYS_SRAMPC0_SRAM1PM4_Pos         (18)                                              /*!< SYS_T::SRAMPC0: SRAM1PM4 Position      */
+#define SYS_SRAMPC0_SRAM1PM4_Msk         (0x3ul << SYS_SRAMPC0_SRAM1PM4_Pos)               /*!< SYS_T::SRAMPC0: SRAM1PM4 Mask          */
+
+#define SYS_SRAMPC0_SRAM1PM5_Pos         (20)                                              /*!< SYS_T::SRAMPC0: SRAM1PM5 Position      */
+#define SYS_SRAMPC0_SRAM1PM5_Msk         (0x3ul << SYS_SRAMPC0_SRAM1PM5_Pos)               /*!< SYS_T::SRAMPC0: SRAM1PM5 Mask          */
+
+#define SYS_SRAMPC0_SRAM1PM6_Pos         (22)                                              /*!< SYS_T::SRAMPC0: SRAM1PM6 Position      */
+#define SYS_SRAMPC0_SRAM1PM6_Msk         (0x3ul << SYS_SRAMPC0_SRAM1PM6_Pos)               /*!< SYS_T::SRAMPC0: SRAM1PM6 Mask          */
+
+#define SYS_SRAMPC0_SRAM1PM7_Pos         (24)                                              /*!< SYS_T::SRAMPC0: SRAM1PM7 Position      */
+#define SYS_SRAMPC0_SRAM1PM7_Msk         (0x3ul << SYS_SRAMPC0_SRAM1PM7_Pos)               /*!< SYS_T::SRAMPC0: SRAM1PM7 Mask          */
+
+#define SYS_SRAMPC0_SRAM2PM0_Pos         (26)                                              /*!< SYS_T::SRAMPC0: SRAM2PM0 Position      */
+#define SYS_SRAMPC0_SRAM2PM0_Msk         (0x3ul << SYS_SRAMPC0_SRAM2PM0_Pos)               /*!< SYS_T::SRAMPC0: SRAM2PM0 Mask          */
+
+#define SYS_SRAMPC0_SRAM2PM1_Pos         (28)                                              /*!< SYS_T::SRAMPC0: SRAM2PM1 Position      */
+#define SYS_SRAMPC0_SRAM2PM1_Msk         (0x3ul << SYS_SRAMPC0_SRAM2PM1_Pos)               /*!< SYS_T::SRAMPC0: SRAM2PM1 Mask          */
+
+#define SYS_SRAMPC0_PCBUSY_Pos           (31)                                              /*!< SYS_T::SRAMPC0: PCBUSY Position        */
+#define SYS_SRAMPC0_PCBUSY_Msk           (0x1ul << SYS_SRAMPC0_PCBUSY_Pos)                 /*!< SYS_T::SRAMPC0: PCBUSY Mask            */
+
+#define SYS_SRAMPC1_SRAM2PM2_Pos         (0)                                               /*!< SYS_T::SRAMPC1: SRAM2PM2 Position      */
+#define SYS_SRAMPC1_SRAM2PM2_Msk         (0x3ul << SYS_SRAMPC1_SRAM2PM2_Pos)               /*!< SYS_T::SRAMPC1: SRAM2PM2 Mask          */
+
+#define SYS_SRAMPC1_SRAM2PM3_Pos         (2)                                               /*!< SYS_T::SRAMPC1: SRAM2PM3 Position      */
+#define SYS_SRAMPC1_SRAM2PM3_Msk         (0x3ul << SYS_SRAMPC1_SRAM2PM3_Pos)               /*!< SYS_T::SRAMPC1: SRAM2PM3 Mask          */
+
+#define SYS_SRAMPC1_SRAM2PM4_Pos         (4)                                               /*!< SYS_T::SRAMPC1: SRAM2PM4 Position      */
+#define SYS_SRAMPC1_SRAM2PM4_Msk         (0x3ul << SYS_SRAMPC1_SRAM2PM4_Pos)               /*!< SYS_T::SRAMPC1: SRAM2PM4 Mask          */
+
+#define SYS_SRAMPC1_SRAM2PM5_Pos         (6)                                               /*!< SYS_T::SRAMPC1: SRAM2PM5 Position      */
+#define SYS_SRAMPC1_SRAM2PM5_Msk         (0x3ul << SYS_SRAMPC1_SRAM2PM5_Pos)               /*!< SYS_T::SRAMPC1: SRAM2PM5 Mask          */
+
+#define SYS_SRAMPC1_CAN_Pos              (16)                                              /*!< SYS_T::SRAMPC1: CAN Position           */
+#define SYS_SRAMPC1_CAN_Msk              (0x3ul << SYS_SRAMPC1_CAN_Pos)                    /*!< SYS_T::SRAMPC1: CAN Mask               */
+
+#define SYS_SRAMPC1_USBD_Pos             (18)                                              /*!< SYS_T::SRAMPC1: USBD Position          */
+#define SYS_SRAMPC1_USBD_Msk             (0x3ul << SYS_SRAMPC1_USBD_Pos)                   /*!< SYS_T::SRAMPC1: USBD Mask              */
+
+#define SYS_SRAMPC1_PDMA0_Pos            (20)                                              /*!< SYS_T::SRAMPC1: PDMA0 Position         */
+#define SYS_SRAMPC1_PDMA0_Msk            (0x3ul << SYS_SRAMPC1_PDMA0_Pos)                  /*!< SYS_T::SRAMPC1: PDMA0 Mask             */
+
+#define SYS_SRAMPC1_PDMA1_Pos            (22)                                              /*!< SYS_T::SRAMPC1: PDMA1 Position         */
+#define SYS_SRAMPC1_PDMA1_Msk            (0x3ul << SYS_SRAMPC1_PDMA1_Pos)                  /*!< SYS_T::SRAMPC1: PDMA1 Mask             */
+
+#define SYS_SRAMPC1_FMCCACHE_Pos         (24)                                              /*!< SYS_T::SRAMPC1: FMCCACHE Position      */
+#define SYS_SRAMPC1_FMCCACHE_Msk         (0x3ul << SYS_SRAMPC1_FMCCACHE_Pos)               /*!< SYS_T::SRAMPC1: FMCCACHE Mask          */
+
+#define SYS_SRAMPC1_RSA_Pos              (26)                                              /*!< SYS_T::SRAMPC1: RSA Position           */
+#define SYS_SRAMPC1_RSA_Msk              (0x3ul << SYS_SRAMPC1_RSA_Pos)                    /*!< SYS_T::SRAMPC1: RSA Mask               */
+
+#define SYS_SRAMPC1_KS_Pos               (28)                                              /*!< SYS_T::SRAMPC1: KS Position            */
+#define SYS_SRAMPC1_KS_Msk               (0x3ul << SYS_SRAMPC1_KS_Pos)                     /*!< SYS_T::SRAMPC1: KS Mask                */
+
+#define SYS_SRAMPC1_PCBUSY_Pos           (31)                                              /*!< SYS_T::SRAMPC1: PCBUSY Position        */
+#define SYS_SRAMPC1_PCBUSY_Msk           (0x1ul << SYS_SRAMPC1_PCBUSY_Pos)                 /*!< SYS_T::SRAMPC1: PCBUSY Mask            */
+
+#define SYS_TCTL48M_FREQSEL_Pos          (0)                                               /*!< SYS_T::TCTL48M: FREQSEL Position       */
+#define SYS_TCTL48M_FREQSEL_Msk          (0x3ul << SYS_TCTL48M_FREQSEL_Pos)                /*!< SYS_T::TCTL48M: FREQSEL Mask           */
+
+#define SYS_TCTL48M_LOOPSEL_Pos          (4)                                               /*!< SYS_T::TCTL48M: LOOPSEL Position       */
+#define SYS_TCTL48M_LOOPSEL_Msk          (0x3ul << SYS_TCTL48M_LOOPSEL_Pos)                /*!< SYS_T::TCTL48M: LOOPSEL Mask           */
+
+#define SYS_TCTL48M_RETRYCNT_Pos         (6)                                               /*!< SYS_T::TCTL48M: RETRYCNT Position      */
+#define SYS_TCTL48M_RETRYCNT_Msk         (0x3ul << SYS_TCTL48M_RETRYCNT_Pos)               /*!< SYS_T::TCTL48M: RETRYCNT Mask          */
+
+#define SYS_TCTL48M_CESTOPEN_Pos         (8)                                               /*!< SYS_T::TCTL48M: CESTOPEN Position      */
+#define SYS_TCTL48M_CESTOPEN_Msk         (0x1ul << SYS_TCTL48M_CESTOPEN_Pos)               /*!< SYS_T::TCTL48M: CESTOPEN Mask          */
+
+#define SYS_TCTL48M_BOUNDEN_Pos          (9)                                               /*!< SYS_T::TCTL48M: BOUNDEN Position       */
+#define SYS_TCTL48M_BOUNDEN_Msk          (0x1ul << SYS_TCTL48M_BOUNDEN_Pos)                /*!< SYS_T::TCTL48M: BOUNDEN Mask           */
+
+#define SYS_TCTL48M_REFCKSEL_Pos         (10)                                              /*!< SYS_T::TCTL48M: REFCKSEL Position      */
+#define SYS_TCTL48M_REFCKSEL_Msk         (0x1ul << SYS_TCTL48M_REFCKSEL_Pos)               /*!< SYS_T::TCTL48M: REFCKSEL Mask          */
+
+#define SYS_TCTL48M_BOUNDARY_Pos         (16)                                              /*!< SYS_T::TCTL48M: BOUNDARY Position      */
+#define SYS_TCTL48M_BOUNDARY_Msk         (0x1ful << SYS_TCTL48M_BOUNDARY_Pos)              /*!< SYS_T::TCTL48M: BOUNDARY Mask          */
+
+#define SYS_TIEN48M_TFAILIEN_Pos         (1)                                               /*!< SYS_T::TIEN48M: TFAILIEN Position      */
+#define SYS_TIEN48M_TFAILIEN_Msk         (0x1ul << SYS_TIEN48M_TFAILIEN_Pos)               /*!< SYS_T::TIEN48M: TFAILIEN Mask          */
+
+#define SYS_TIEN48M_CLKEIEN_Pos          (2)                                               /*!< SYS_T::TIEN48M: CLKEIEN Position       */
+#define SYS_TIEN48M_CLKEIEN_Msk          (0x1ul << SYS_TIEN48M_CLKEIEN_Pos)                /*!< SYS_T::TIEN48M: CLKEIEN Mask           */
+
+#define SYS_TISTS48M_FREQLOCK_Pos        (0)                                               /*!< SYS_T::TISTS48M: FREQLOCK Position     */
+#define SYS_TISTS48M_FREQLOCK_Msk        (0x1ul << SYS_TISTS48M_FREQLOCK_Pos)              /*!< SYS_T::TISTS48M: FREQLOCK Mask         */
+
+#define SYS_TISTS48M_TFAILIF_Pos         (1)                                               /*!< SYS_T::TISTS48M: TFAILIF Position      */
+#define SYS_TISTS48M_TFAILIF_Msk         (0x1ul << SYS_TISTS48M_TFAILIF_Pos)               /*!< SYS_T::TISTS48M: TFAILIF Mask          */
+
+#define SYS_TISTS48M_CLKERRIF_Pos        (2)                                               /*!< SYS_T::TISTS48M: CLKERRIF Position     */
+#define SYS_TISTS48M_CLKERRIF_Msk        (0x1ul << SYS_TISTS48M_CLKERRIF_Pos)              /*!< SYS_T::TISTS48M: CLKERRIF Mask         */
+
+#define SYS_TISTS48M_OVBDIF_Pos          (3)                                               /*!< SYS_T::TISTS48M: OVBDIF Position       */
+#define SYS_TISTS48M_OVBDIF_Msk          (0x1ul << SYS_TISTS48M_OVBDIF_Pos)                /*!< SYS_T::TISTS48M: OVBDIF Mask           */
+
+#define SYS_TCTL12M_FREQSEL_Pos          (0)                                               /*!< SYS_T::TCTL12M: FREQSEL Position       */
+#define SYS_TCTL12M_FREQSEL_Msk          (0x3ul << SYS_TCTL12M_FREQSEL_Pos)                /*!< SYS_T::TCTL12M: FREQSEL Mask           */
+
+#define SYS_TCTL12M_LOOPSEL_Pos          (4)                                               /*!< SYS_T::TCTL12M: LOOPSEL Position       */
+#define SYS_TCTL12M_LOOPSEL_Msk          (0x3ul << SYS_TCTL12M_LOOPSEL_Pos)                /*!< SYS_T::TCTL12M: LOOPSEL Mask           */
+
+#define SYS_TCTL12M_RETRYCNT_Pos         (6)                                               /*!< SYS_T::TCTL12M: RETRYCNT Position      */
+#define SYS_TCTL12M_RETRYCNT_Msk         (0x3ul << SYS_TCTL12M_RETRYCNT_Pos)               /*!< SYS_T::TCTL12M: RETRYCNT Mask          */
+
+#define SYS_TCTL12M_CESTOPEN_Pos         (8)                                               /*!< SYS_T::TCTL12M: CESTOPEN Position      */
+#define SYS_TCTL12M_CESTOPEN_Msk         (0x1ul << SYS_TCTL12M_CESTOPEN_Pos)               /*!< SYS_T::TCTL12M: CESTOPEN Mask          */
+
+#define SYS_TCTL12M_BOUNDEN_Pos          (9)                                               /*!< SYS_T::TCTL12M: BOUNDEN Position       */
+#define SYS_TCTL12M_BOUNDEN_Msk          (0x1ul << SYS_TCTL12M_BOUNDEN_Pos)                /*!< SYS_T::TCTL12M: BOUNDEN Mask           */
+
+#define SYS_TCTL12M_REFCKSEL_Pos         (10)                                              /*!< SYS_T::TCTL12M: REFCKSEL Position      */
+#define SYS_TCTL12M_REFCKSEL_Msk         (0x1ul << SYS_TCTL12M_REFCKSEL_Pos)               /*!< SYS_T::TCTL12M: REFCKSEL Mask          */
+
+#define SYS_TCTL12M_BOUNDARY_Pos         (16)                                              /*!< SYS_T::TCTL12M: BOUNDARY Position      */
+#define SYS_TCTL12M_BOUNDARY_Msk         (0x1ful << SYS_TCTL12M_BOUNDARY_Pos)              /*!< SYS_T::TCTL12M: BOUNDARY Mask          */
+
+#define SYS_TIEN12M_TFAILIEN_Pos         (1)                                               /*!< SYS_T::TIEN12M: TFAILIEN Position      */
+#define SYS_TIEN12M_TFAILIEN_Msk         (0x1ul << SYS_TIEN12M_TFAILIEN_Pos)               /*!< SYS_T::TIEN12M: TFAILIEN Mask          */
+
+#define SYS_TIEN12M_CLKEIEN_Pos          (2)                                               /*!< SYS_T::TIEN12M: CLKEIEN Position       */
+#define SYS_TIEN12M_CLKEIEN_Msk          (0x1ul << SYS_TIEN12M_CLKEIEN_Pos)                /*!< SYS_T::TIEN12M: CLKEIEN Mask           */
+
+#define SYS_TISTS12M_FREQLOCK_Pos        (0)                                               /*!< SYS_T::TISTS12M: FREQLOCK Position     */
+#define SYS_TISTS12M_FREQLOCK_Msk        (0x1ul << SYS_TISTS12M_FREQLOCK_Pos)              /*!< SYS_T::TISTS12M: FREQLOCK Mask         */
+
+#define SYS_TISTS12M_TFAILIF_Pos         (1)                                               /*!< SYS_T::TISTS12M: TFAILIF Position      */
+#define SYS_TISTS12M_TFAILIF_Msk         (0x1ul << SYS_TISTS12M_TFAILIF_Pos)               /*!< SYS_T::TISTS12M: TFAILIF Mask          */
+
+#define SYS_TISTS12M_CLKERRIF_Pos        (2)                                               /*!< SYS_T::TISTS12M: CLKERRIF Position     */
+#define SYS_TISTS12M_CLKERRIF_Msk        (0x1ul << SYS_TISTS12M_CLKERRIF_Pos)              /*!< SYS_T::TISTS12M: CLKERRIF Mask         */
+
+#define SYS_TISTS12M_OVBDIF_Pos          (3)                                               /*!< SYS_T::TISTS12M: OVBDIF Position       */
+#define SYS_TISTS12M_OVBDIF_Msk          (0x1ul << SYS_TISTS12M_OVBDIF_Pos)                /*!< SYS_T::TISTS12M: OVBDIF Mask           */
+
+#define SYS_REGLCTL_REGLCTL_Pos          (0)                                               /*!< SYS_T::REGLCTL: REGLCTL Position       */
+#define SYS_REGLCTL_REGLCTL_Msk          (0xfful << SYS_REGLCTL_REGLCTL_Pos)               /*!< SYS_T::REGLCTL: REGLCTL Mask           */
+
+#define SYS_CPUCFG_INTRTEN_Pos           (0)                                               /*!< SYS_T::CPUCFG: INTRTEN Position        */
+#define SYS_CPUCFG_INTRTEN_Msk           (0x1ul << SYS_CPUCFG_INTRTEN_Pos)                 /*!< SYS_T::CPUCFG: INTRTEN Mask            */
+
+#define SYS_OVDCTL_OVDEN_Pos             (0)                                               /*!< SYS_T::OVDCTL: OVDEN Position          */
+#define SYS_OVDCTL_OVDEN_Msk             (0x1ul << SYS_OVDCTL_OVDEN_Pos)                   /*!< SYS_T::OVDCTL: OVDEN Mask              */
+
+#define SYS_OVDCTL_OVDSTB_Pos            (31)                                              /*!< SYS_T::OVDCTL: OVDSTB Position         */
+#define SYS_OVDCTL_OVDSTB_Msk            (0x1ul << SYS_OVDCTL_OVDSTB_Pos)                  /*!< SYS_T::OVDCTL: OVDSTB Mask             */
+
+#define SYS_PORCTL1_POROFF_Pos           (0)                                               /*!< SYS_T::PORCTL1: POROFF Position        */
+#define SYS_PORCTL1_POROFF_Msk           (0xfffful << SYS_PORCTL1_POROFF_Pos)              /*!< SYS_T::PORCTL1: POROFF Mask            */
+
+#define SYS_PSWCTL_CRPTPWREN_Pos         (12)                                              /*!< SYS_T::PSWCTL: CRPTPWREN Position      */
+#define SYS_PSWCTL_CRPTPWREN_Msk         (0x1ul << SYS_PSWCTL_CRPTPWREN_Pos)               /*!< SYS_T::PSWCTL: CRPTPWREN Mask          */
+
+#define SYS_PLCTL_PLSEL_Pos              (0)                                               /*!< SYS_T::PLCTL: PLSEL Position           */
+#define SYS_PLCTL_PLSEL_Msk              (0x3ul << SYS_PLCTL_PLSEL_Pos)                    /*!< SYS_T::PLCTL: PLSEL Mask               */
+
+#define SYS_PLCTL_MVRS_Pos               (4)                                               /*!< SYS_T::PLCTL: MVRS Position            */
+#define SYS_PLCTL_MVRS_Msk               (0x1ul << SYS_PLCTL_MVRS_Pos)                     /*!< SYS_T::PLCTL: MVRS Mask                */
+
+#define SYS_PLCTL_WRBUSY_Pos             (7)                                               /*!< SYS_T::PLCTL: WRBUSY Position          */
+#define SYS_PLCTL_WRBUSY_Msk             (0x1ul << SYS_PLCTL_WRBUSY_Pos)                   /*!< SYS_T::PLCTL: WRBUSY Mask              */
+
+#define SYS_PLCTL_LVSSTEP_Pos            (16)                                              /*!< SYS_T::PLCTL: LVSSTEP Position         */
+#define SYS_PLCTL_LVSSTEP_Msk            (0x3ful << SYS_PLCTL_LVSSTP_Pos)                  /*!< SYS_T::PLCTL: LVSSTEP Mask             */
+
+#define SYS_PLCTL_LVSPRD_Pos             (24)                                              /*!< SYS_T::PLCTL: LVSPRD Position          */
+#define SYS_PLCTL_LVSPRD_Msk             (0xfful << SYS_PLCTL_LVSPRD_Pos)                  /*!< SYS_T::PLCTL: LVSPRD Mask              */
+
+#define SYS_PLSTS_PLCBUSY_Pos            (0)                                               /*!< SYS_T::PLSTS: PLCBUSY Position         */
+#define SYS_PLSTS_PLCBUSY_Msk            (0x1ul << SYS_PLSTS_PLCBUSY_Pos)                  /*!< SYS_T::PLSTS: PLCBUSY Mask             */
+
+#define SYS_PLSTS_MVRCBUSY_Pos           (1)                                               /*!< SYS_T::PLSTS: MVRCBUSY Position        */
+#define SYS_PLSTS_MVRCBUSY_Msk           (0x1ul << SYS_PLSTS_MVRCBUSY_Pos)                 /*!< SYS_T::PLSTS: MVRCBUSY Mask            */
+
+#define SYS_PLSTS_MVRCERR_Pos            (2)                                               /*!< SYS_T::PLSTS: MVRCERR Position         */
+#define SYS_PLSTS_MVRCERR_Msk            (0x1ul << SYS_PLSTS_MVRCERR_Pos)                  /*!< SYS_T::PLSTS: MVRCERR Mask             */
+
+#define SYS_PLSTS_LCONS_Pos              (3)                                               /*!< SYS_T::PLSTS: LCONS Position           */
+#define SYS_PLSTS_LCONS_Msk              (0x1ul << SYS_PLSTS_LCONS_Pos)                    /*!< SYS_T::PLSTS: LCONS Mask               */
+
+#define SYS_PLSTS_PLSTATUS_Pos           (8)                                               /*!< SYS_T::PLSTS: PLSTATUS Position        */
+#define SYS_PLSTS_PLSTATUS_Msk           (0x3ul << SYS_PLSTS_PLSTATUS_Pos)                 /*!< SYS_T::PLSTS: PLSTATUS Mask            */
+
+#define SYS_PLSTS_CURMVR_Pos             (12)                                              /*!< SYS_T::PLSTS: CURMVR Position          */
+#define SYS_PLSTS_CURMVR_Msk             (0x1ul << SYS_PLSTS_CURMVR_Pos)                   /*!< SYS_T::PLSTS: CURMVR Mask              */
+
+#define SYS_AHBMCTL_INTACTEN_Pos         (0)                                               /*!< SYS_T::AHBMCTL: INTACTEN Position      */
+#define SYS_AHBMCTL_INTACTEN_Msk         (0x1ul << SYS_AHBMCTL_INTACTEN_Pos)               /*!< SYS_T::AHBMCTL: INTACTEN Mask          */
+
+
+/**@}*/ /* SYS_CONST */
+typedef struct
+{
+
+    /**
+     * @var SYS_INT_T::NMIEN
+     * Offset: 0x00  NMI Source Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BODOUT    |BOD NMI Source Enable (Write Protect)
+     * |        |          |0 = BOD NMI source Disabled.
+     * |        |          |1 = BOD NMI source Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[1]     |IRCINT    |IRC TRIM NMI Source Enable (Write Protect)
+     * |        |          |0 = IRC TRIM NMI source Disabled.
+     * |        |          |1 = IRC TRIM NMI source Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[2]     |PWRWUINT  |Power-down Mode Wake-up NMI Source Enable (Write Protect)
+     * |        |          |0 = Power-down mode wake-up NMI source Disabled.
+     * |        |          |1 = Power-down mode wake-up NMI source Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[3]     |SRAMPERR  |SRAM Parity Check Error NMI Source Enable (Write Protect)
+     * |        |          |0 = SRAM parity check error NMI source Disabled.
+     * |        |          |1 = SRAM parity check error NMI source Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[4]     |CLKFAIL   |Clock Fail Detected NMI Source Enable (Write Protect)
+     * |        |          |0 = Clock fail detected interrupt NMI source Disabled.
+     * |        |          |1 = Clock fail detected interrupt NMI source Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[6]     |RTCINT    |RTC NMI Source Enable (Write Protect)
+     * |        |          |0 = RTC NMI source Disabled.
+     * |        |          |1 = RTC NMI source Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[7]     |TAMPERINT |Tamper Interrupt NMI Source Enable (Write Protect)
+     * |        |          |0 = Backup register tamper detected interrupt NMI source Disabled.
+     * |        |          |1 = Backup register tamper detected interrupt NMI source Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[8]     |EINT0     |External Interrupt From PA.6, or PB.5 Pin NMI Source Enable (Write Protect)
+     * |        |          |0 = External interrupt from PA.6, or PB.5 pin NMI source Disabled.
+     * |        |          |1 = External interrupt from PA.6, or PB.5 pin NMI source Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[9]     |EINT1     |External Interrupt From PA.7 or PB.4 Pin NMI Source Enable (Write Protect)
+     * |        |          |0 = External interrupt from PA.7 or PB.4 pin NMI source Disabled.
+     * |        |          |1 = External interrupt from PA.7 or P4.4 pin NMI source Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[10]    |EINT2     |External Interrupt From PB.3 or PC.6 Pin NMI Source Enable (Write Protect)
+     * |        |          |0 = External interrupt from PB.3 or PC.6 pin NMI source Disabled.
+     * |        |          |1 = External interrupt from PB.3 or PC.6 pin NMI source Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[11]    |EINT3     |External Interrupt From PB.2 or PC.7 Pin NMI Source Enable (Write Protect)
+     * |        |          |0 = External interrupt from PB.2 or PC.7pin NMI source Disabled.
+     * |        |          |1 = External interrupt from PB.2 or PC.7 pin NMI source Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[12]    |EINT4     |External Interrupt From PA.8 or PB.6 Pin NMI Source Enable (Write Protect)
+     * |        |          |0 = External interrupt from PA.8 or PB.6 pin NMI source Disabled.
+     * |        |          |1 = External interrupt from PA.8 or PB.6 pin NMI source Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[13]    |EINT5     |External Interrupt From PB.7 or PD.12 Pin NMI Source Enable (Write Protect)
+     * |        |          |0 = External interrupt from PB.7 or PD.12 pin NMI source Disabled.
+     * |        |          |1 = External interrupt from PB.7 or PD.12 pin NMI source Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[14]    |UART0INT  |UART0 NMI Source Enable (Write Protect)
+     * |        |          |0 = UART0 NMI source Disabled.
+     * |        |          |1 = UART0 NMI source Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[15]    |UART1INT  |UART1 NMI Source Enable (Write Protect)
+     * |        |          |0 = UART1 NMI source Disabled.
+     * |        |          |1 = UART1 NMI source Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[16]    |EINT6     |External Interrupt From PB.8 or PD.11 Pin NMI Source Enable (Write Protect)
+     * |        |          |0 = External interrupt from PB.8 or PD.11 pin NMI source Disabled.
+     * |        |          |1 = External interrupt from PB.8 or PD.11 pin NMI source Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[17]    |EINT7     |External Interrupt From PB.9 or PD.10 Pin NMI Source Enable (Write Protect)
+     * |        |          |0 = External interrupt from PB.9 or PD.10 pin NMI source Disabled.
+     * |        |          |1 = External interrupt from PB.9 or PD.10 pin NMI source Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * @var SYS_INT_T::NMISTS
+     * Offset: 0x04  NMI source interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BODOUT    |BOD Interrupt Flag (Read Only)
+     * |        |          |0 = BOD interrupt is de-asserted.
+     * |        |          |1 = BOD interrupt is asserted.
+     * |[1]     |IRCINT    |IRC TRIM Interrupt Flag (Read Only)
+     * |        |          |0 = HIRC TRIM interrupt is de-asserted.
+     * |        |          |1 = HIRC TRIM interrupt is asserted.
+     * |[2]     |PWRWUINT  |Power-down Mode Wake-up Interrupt Flag (Read Only)
+     * |        |          |0 = Power-down mode wake-up interrupt is de-asserted.
+     * |        |          |1 = Power-down mode wake-up interrupt is asserted.
+     * |[3]     |SRAMPERR  |SRAM Parity Check Error Interrupt Flag (Read Only)
+     * |        |          |0 = SRAM parity check error interrupt is de-asserted.
+     * |        |          |1 = SRAM parity check error interrupt is asserted.
+     * |[4]     |CLKFAIL   |Clock Fail Detected Interrupt Flag (Read Only)
+     * |        |          |0 = Clock fail detected interrupt is de-asserted.
+     * |        |          |1 = Clock fail detected interrupt is asserted.
+     * |[6]     |RTCINT    |RTC Interrupt Flag (Read Only)
+     * |        |          |0 = RTC interrupt is de-asserted.
+     * |        |          |1 = RTC interrupt is asserted.
+     * |[7]     |TAMPERINT |Tamper Interrupt Flag (Read Only)
+     * |        |          |0 = Backup register tamper detected interrupt is de-asserted.
+     * |        |          |1 = Backup register tamper detected interrupt is asserted.
+     * |[8]     |EINT0     |External Interrupt From PA.6, or PB.5 Pin Interrupt Flag (Read Only)
+     * |        |          |0 = External Interrupt from PA.6, or PB.5 interrupt is deasserted.
+     * |        |          |1 = External Interrupt from PA.6, or PB.5 interrupt is asserted.
+     * |[9]     |EINT1     |External Interrupt From PA.7, or PB.4 Pin Interrupt Flag (Read Only)
+     * |        |          |0 = External Interrupt from PA.7, or PB.4 interrupt is deasserted.
+     * |        |          |1 = External Interrupt from PA.7, or PB.4 interrupt is asserted.
+     * |[10]    |EINT2     |External Interrupt From PB.3 or PC.6 Pin Interrupt Flag (Read Only)
+     * |        |          |0 = External Interrupt from PB.3 or PC.6 interrupt is deasserted.
+     * |        |          |1 = External Interrupt from PB.3 or PC.6 interrupt is asserted.
+     * |[11]    |EINT3     |External Interrupt From PB.2 or PC.7 Pin Interrupt Flag (Read Only)
+     * |        |          |0 = External Interrupt from PB.2 or PC.7 interrupt is deasserted.
+     * |        |          |1 = External Interrupt from PB.2 or PC.7 interrupt is asserted.
+     * |[12]    |EINT4     |External Interrupt From PA.8 or PB.6 Pin Interrupt Flag (Read Only)
+     * |        |          |0 = External Interrupt from PA.8 or PB.6 interrupt is deasserted.
+     * |        |          |1 = External Interrupt from PA.8 or PB.6 interrupt is asserted.
+     * |[13]    |EINT5     |External Interrupt From PB.7 or PD.12 Pin Interrupt Flag (Read Only)
+     * |        |          |0 = External Interrupt from PB.7 or PD.12 interrupt is deasserted.
+     * |        |          |1 = External Interrupt from PB.7 or PD.12 interrupt is asserted.
+     * |[14]    |UART0INT  |UART0 Interrupt Flag (Read Only)
+     * |        |          |0 = UART1 interrupt is de-asserted.
+     * |        |          |1 = UART1 interrupt is asserted.
+     * |[15]    |UART1INT  |UART1 Interrupt Flag (Read Only)
+     * |        |          |0 = UART1 interrupt is de-asserted.
+     * |        |          |1 = UART1 interrupt is asserted.
+     * |[16]    |EINT6     |External Interrupt From PB.8 or PD.11 Pin Interrupt Flag (Read Only)
+     * |        |          |0 = External Interrupt from PB.8 or PD.11 interrupt is deasserted.
+     * |        |          |1 = External Interrupt from PB.8 or PD.11 interrupt is asserted.
+     * |[17]    |EINT7     |External Interrupt From PB.9 or PD.10 Pin Interrupt Flag (Read Only)
+     * |        |          |0 = External Interrupt from PB.9 or PD.10 interrupt is deasserted.
+     * |        |          |1 = External Interrupt from PB.9 or PD.10 interrupt is asserted.
+     */
+
+    __IO  uint32_t NMIEN;          /* Offset: 0x00  NMI Source Interrupt Enable Register                               */
+    __I   uint32_t NMISTS;         /* Offset: 0x04  NMI source interrupt Status Register                               */
+
+} SYS_INT_T;
+/**
+    @addtogroup INT_CONST INT Bit Field Definition
+    Constant Definitions for INT Controller
+  @{
+*/
+
+#define SYS_NMIEN_BODOUT_Pos             (0)                                               /*!< SYS_INT_T::NMIEN: BODOUT Position         */
+#define SYS_NMIEN_BODOUT_Msk             (0x1ul << SYS_NMIEN_BODOUT_Pos )                  /*!< SYS_INT_T::NMIEN: BODOUT Mask             */
+
+#define SYS_NMIEN_IRCINT_Pos             (1)                                               /*!< SYS_INT_T::NMIEN: IRCINT Position         */
+#define SYS_NMIEN_IRCINT_Msk             (0x1ul << SYS_NMIEN_IRCINT_Pos )                  /*!< SYS_INT_T::NMIEN: IRCINT Mask             */
+
+#define SYS_NMIEN_PWRWUINT_Pos           (2)                                               /*!< SYS_INT_T::NMIEN: PWRWUINT Position       */
+#define SYS_NMIEN_PWRWUINT_Msk           (0x1ul << SYS_NMIEN_PWRWUINT_Pos )                /*!< SYS_INT_T::NMIEN: PWRWUINT Mask           */
+
+#define SYS_NMIEN_SRAMPERR_Pos           (3)                                               /*!< SYS_INT_T::NMIEN: SRAMPERR Position       */
+#define SYS_NMIEN_SRAMPERR_Msk           (0x1ul << SYS_NMIEN_SRAMPERR_Pos )                /*!< SYS_INT_T::NMIEN: SRAMPERR Mask           */
+
+#define SYS_NMIEN_CLKFAIL_Pos            (4)                                               /*!< SYS_INT_T::NMIEN: CLKFAIL Position        */
+#define SYS_NMIEN_CLKFAIL_Msk            (0x1ul << SYS_NMIEN_CLKFAIL_Pos )                 /*!< SYS_INT_T::NMIEN: CLKFAIL Mask            */
+
+#define SYS_NMIEN_RTCINT_Pos             (6)                                               /*!< SYS_INT_T::NMIEN: RTCINT Position         */
+#define SYS_NMIEN_RTCINT_Msk             (0x1ul << SYS_NMIEN_RTCINT_Pos )                  /*!< SYS_INT_T::NMIEN: RTCINT Mask             */
+
+#define SYS_NMIEN_TAMPERINT_Pos          (7)                                               /*!< SYS_INT_T::NMIEN: TAMPERINT Position      */
+#define SYS_NMIEN_TAMPERINT_Msk          (0x1ul << SYS_NMIEN_TAMPERINT_Pos )               /*!< SYS_INT_T::NMIEN: TAMPERINT Mask          */
+
+#define SYS_NMIEN_EINT0_Pos              (8)                                               /*!< SYS_INT_T::NMIEN: EINT0 Position          */
+#define SYS_NMIEN_EINT0_Msk              (0x1ul << SYS_NMIEN_EINT0_Pos )                   /*!< SYS_INT_T::NMIEN: EINT0 Mask              */
+
+#define SYS_NMIEN_EINT1_Pos              (9)                                               /*!< SYS_INT_T::NMIEN: EINT1 Position          */
+#define SYS_NMIEN_EINT1_Msk              (0x1ul << SYS_NMIEN_EINT1_Pos )                   /*!< SYS_INT_T::NMIEN: EINT1 Mask              */
+
+#define SYS_NMIEN_EINT2_Pos              (10)                                              /*!< SYS_INT_T::NMIEN: EINT2 Position          */
+#define SYS_NMIEN_EINT2_Msk              (0x1ul << SYS_NMIEN_EINT2_Pos )                   /*!< SYS_INT_T::NMIEN: EINT2 Mask              */
+
+#define SYS_NMIEN_EINT3_Pos              (11)                                              /*!< SYS_INT_T::NMIEN: EINT3 Position          */
+#define SYS_NMIEN_EINT3_Msk              (0x1ul << SYS_NMIEN_EINT3_Pos )                   /*!< SYS_INT_T::NMIEN: EINT3 Mask              */
+
+#define SYS_NMIEN_EINT4_Pos              (12)                                              /*!< SYS_INT_T::NMIEN: EINT4 Position          */
+#define SYS_NMIEN_EINT4_Msk              (0x1ul << SYS_NMIEN_EINT4_Pos )                   /*!< SYS_INT_T::NMIEN: EINT4 Mask              */
+
+#define SYS_NMIEN_EINT5_Pos              (13)                                              /*!< SYS_INT_T::NMIEN: EINT5 Position          */
+#define SYS_NMIEN_EINT5_Msk              (0x1ul << SYS_NMIEN_EINT5_Pos )                   /*!< SYS_INT_T::NMIEN: EINT5 Mask              */
+
+#define SYS_NMIEN_UART0INT_Pos           (14)                                              /*!< SYS_INT_T::NMIEN: UART0INT Position       */
+#define SYS_NMIEN_UART0INT_Msk           (0x1ul << SYS_NMIEN_UART0INT_Pos )                /*!< SYS_INT_T::NMIEN: UART0INT Mask           */
+
+#define SYS_NMIEN_UART1INT_Pos           (15)                                              /*!< SYS_INT_T::NMIEN: UART1INT Position       */
+#define SYS_NMIEN_UART1INT_Msk           (0x1ul << SYS_NMIEN_UART1INT_Pos )                /*!< SYS_INT_T::NMIEN: UART1INT Mask           */
+
+#define SYS_NMIEN_EINT6_Pos              (16)                                              /*!< SYS_INT_T::NMIEN: EINT6 Position          */
+#define SYS_NMIEN_EINT6_Msk              (0x1ul << SYS_NMIEN_EINT6_Pos )                   /*!< SYS_INT_T::NMIEN: EINT6 Mask              */
+
+#define SYS_NMIEN_EINT7_Pos              (17)                                              /*!< SYS_INT_T::NMIEN: EINT7 Position          */
+#define SYS_NMIEN_EINT7_Msk              (0x1ul << SYS_NMIEN_EINT7_Pos )                   /*!< SYS_INT_T::NMIEN: EINT7 Mask              */
+
+#define SYS_NMISTS_BODOUT_Pos            (0)                                               /*!< SYS_INT_T::NMISTS: BODOUT Position        */
+#define SYS_NMISTS_BODOUT_Msk            (0x1ul << SYS_NMISTS_BODOUT_Pos )                 /*!< SYS_INT_T::NMISTS: BODOUT Mask            */
+
+#define SYS_NMISTS_IRCINT_Pos            (1)                                               /*!< SYS_INT_T::NMISTS: IRCINT Position        */
+#define SYS_NMISTS_IRCINT_Msk            (0x1ul << SYS_NMISTS_IRCINT_Pos )                 /*!< SYS_INT_T::NMISTS: IRCINT Mask            */
+
+#define SYS_NMISTS_PWRWUINT_Pos          (2)                                               /*!< SYS_INT_T::NMISTS: PWRWUINT Position      */
+#define SYS_NMISTS_PWRWUINT_Msk          (0x1ul << SYS_NMISTS_PWRWUINT_Pos )               /*!< SYS_INT_T::NMISTS: PWRWUINT Mask          */
+
+#define SYS_NMISTS_SRAMPERR_Pos          (3)                                               /*!< SYS_INT_T::NMISTS: SRAMPERR Position      */
+#define SYS_NMISTS_SRAMPERR_Msk          (0x1ul << SYS_NMISTS_SRAMPERR_Pos )               /*!< SYS_INT_T::NMISTS: SRAMPERR Mask          */
+
+#define SYS_NMISTS_CLKFAIL_Pos           (4)                                               /*!< SYS_INT_T::NMISTS: CLKFAIL Position       */
+#define SYS_NMISTS_CLKFAIL_Msk           (0x1ul << SYS_NMISTS_CLKFAIL_Pos )                /*!< SYS_INT_T::NMISTS: CLKFAIL Mask           */
+
+#define SYS_NMISTS_RTCINT_Pos            (6)                                               /*!< SYS_INT_T::NMISTS: RTCINT Position        */
+#define SYS_NMISTS_RTCINT_Msk            (0x1ul << SYS_NMISTS_RTCINT_Pos )                 /*!< SYS_INT_T::NMISTS: RTCINT Mask            */
+
+#define SYS_NMISTS_TAMPERINT_Pos         (7)                                               /*!< SYS_INT_T::NMISTS: TAMPERINT Position     */
+#define SYS_NMISTS_TAMPERINT_Msk         (0x1ul << SYS_NMISTS_TAMPERINT_Pos )              /*!< SYS_INT_T::NMISTS: TAMPERINT Mask         */
+
+#define SYS_NMISTS_EINT0_Pos             (8)                                               /*!< SYS_INT_T::NMISTS: EINT0 Position         */
+#define SYS_NMISTS_EINT0_Msk             (0x1ul << SYS_NMISTS_EINT0_Pos )                  /*!< SYS_INT_T::NMISTS: EINT0 Mask             */
+
+#define SYS_NMISTS_EINT1_Pos             (9)                                               /*!< SYS_INT_T::NMISTS: EINT1 Position         */
+#define SYS_NMISTS_EINT1_Msk             (0x1ul << SYS_NMISTS_EINT1_Pos )                  /*!< SYS_INT_T::NMISTS: EINT1 Mask             */
+
+#define SYS_NMISTS_EINT2_Pos             (10)                                              /*!< SYS_INT_T::NMISTS: EINT2 Position         */
+#define SYS_NMISTS_EINT2_Msk             (0x1ul << SYS_NMISTS_EINT2_Pos )                  /*!< SYS_INT_T::NMISTS: EINT2 Mask             */
+
+#define SYS_NMISTS_EINT3_Pos             (11)                                              /*!< SYS_INT_T::NMISTS: EINT3 Position         */
+#define SYS_NMISTS_EINT3_Msk             (0x1ul << SYS_NMISTS_EINT3_Pos )                  /*!< SYS_INT_T::NMISTS: EINT3 Mask             */
+
+#define SYS_NMISTS_EINT4_Pos             (12)                                              /*!< SYS_INT_T::NMISTS: EINT4 Position         */
+#define SYS_NMISTS_EINT4_Msk             (0x1ul << SYS_NMISTS_EINT4_Pos )                  /*!< SYS_INT_T::NMISTS: EINT4 Mask             */
+
+#define SYS_NMISTS_EINT5_Pos             (13)                                              /*!< SYS_INT_T::NMISTS: EINT5 Position         */
+#define SYS_NMISTS_EINT5_Msk             (0x1ul << SYS_NMISTS_EINT5_Pos )                  /*!< SYS_INT_T::NMISTS: EINT5 Mask             */
+
+#define SYS_NMISTS_UART0INT_Pos          (14)                                              /*!< SYS_INT_T::NMISTS: UART0_INT Position     */
+#define SYS_NMISTS_UART0INT_Msk          (0x1ul << SYS_NMISTS_UART0INT_Pos )               /*!< SYS_INT_T::NMISTS: UART0_INT Mask         */
+
+#define SYS_NMISTS_UART1INT_Pos          (15)                                              /*!< SYS_INT_T::NMISTS: UART1_INT Position     */
+#define SYS_NMISTS_UART1INT_Msk          (0x1ul << SYS_NMISTS_UART1INT_Pos )               /*!< SYS_INT_T::NMISTS: UART1_INT Mask         */
+
+#define SYS_NMISTS_EINT6_Pos             (16)                                              /*!< SYS_INT_T::NMISTS: EINT6 Position         */
+#define SYS_NMISTS_EINT6_Msk             (0x1ul << SYS_NMISTS_EINT6_Pos )                  /*!< SYS_INT_T::NMISTS: EINT6 Mask             */
+
+#define SYS_NMISTS_EINT7_Pos             (17)                                              /*!< SYS_INT_T::NMISTS: EINT7 Position         */
+#define SYS_NMISTS_EINT7_Msk             (0x1ul << SYS_NMISTS_EINT7_Pos )                  /*!< SYS_INT_T::NMISTS: EINT7 Mask             */
+
+
+/**@}*/ /* INT_CONST */
+/**@}*/ /* end of SYS register group */
+/**@}*/ /* end of REGISTER group */
+
+
+#endif /* __SYS_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/system_M2354.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/system_M2354.h
new file mode 100644
index 0000000000..edf1e3e6e5
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/system_M2354.h
@@ -0,0 +1,148 @@
+/**************************************************************************//**
+ * @file     system_M2354.h
+ * @version  V3.00
+ * @brief    System Setting Header File
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __SYSTEM_M2354_H__
+#define __SYSTEM_M2354_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*---------------------------------------------------------------------------------------------------------*/
+/* Macro Definition                                                                                        */
+/*---------------------------------------------------------------------------------------------------------*/
+#ifndef DEBUG_PORT
+# define DEBUG_PORT      UART0       /*!< Select Debug Port which is used for retarget.c to output debug message to UART */
+#endif
+
+
+/* Init ETM Interface Multi-function Pins */
+#define ETM_INIT()  { \
+    SYS->GPC_MFPL &= ~(SYS_GPC_MFPL_PC0MFP_ETM_TRACE_Msk | SYS_GPC_MFPL_PC1MFP_ETM_TRACE_Msk | \
+    SYS_GPC_MFPL_PC2MFP_ETM_TRACE_Msk | SYS_GPC_MFPL_PC3MFP_ETM_TRACE_Msk | \
+                     SYS_GPC_MFPL_PC4MFP_ETM_TRACE_Msk); \
+    SYS->GPC_MFPL |= SYS_GPC_MFPL_PC0MFP_ETM_TRACE_CLK | SYS_GPC_MFPL_PC1MFP_ETM_TRACE_DATA0 | \
+                     SYS_GPC_MFPL_PC2MFP_ETM_TRACE_DATA1 | SYS_GPC_MFPL_PC3MFP_ETM_TRACE_DATA2 | \
+                     SYS_GPC_MFPL_PC4MFP_ETM_TRACE_DATA3;}
+
+
+
+
+
+/**
+ *
+ * @details    This is used to enable PLL to speed up booting at startup. Remove it will cause system using
+ *             default clock source (External crystal or internal 22.1184MHz IRC).
+ *             Enable this option will cause system booting in 72MHz(By XTAL) or 71.8848MHz(By IRC22M) according to
+ *             user configuration setting in CONFIG0
+ *
+ */
+
+/*
+#define INIT_SYSCLK_AT_BOOTING
+*/
+
+/*----------------------------------------------------------------------------
+  Define SYSCLK
+ *----------------------------------------------------------------------------*/
+#ifndef __HXT
+#define __HXT       (12000000UL)    /*!< External Crystal Clock Frequency     */
+#endif
+
+#define __LIRC      (32000UL)       /*!< Internal 32K RC Oscillator Frequency */
+#define __HIRC      (12000000UL)    /*!< Internal 12M RC Oscillator Frequency */
+
+#ifndef __LXT
+#define __LXT       (32768UL)       /*!< External Crystal Clock Frequency 32.768KHz */
+#endif
+
+#ifndef __HSI
+#define __HSI       (48000000UL)    /*!< PLL Output Clock Frequency */
+#endif
+
+#define __HIRC48    (48000000UL)    /*!< Internal 48M RC Oscillator Frequency */
+#define __LIRC32    (32000UL)       /*!< Internal 32K RC Oscillator Frequency */
+#define __MIRC      (4000000UL)     /*!< Internal 4M RC Oscillator Frequency */
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3L)
+# if defined (__ICCARM__)
+#  define __NONSECURE_ENTRY       __cmse_nonsecure_entry
+#  define __NONSECURE_ENTRY_WEAK  __cmse_nonsecure_entry //__weak
+#  define __NONSECURE_CALL        __cmse_nonsecure_call
+# else
+#  define __NONSECURE_ENTRY       __attribute__((cmse_nonsecure_entry))
+#  define __NONSECURE_ENTRY_WEAK  __attribute__((cmse_nonsecure_entry,weak))
+#  define __NONSECURE_CALL        __attribute__((cmse_nonsecure_call))
+# endif
+#else
+# define __NONSECURE_ENTRY
+# define __NONSECURE_ENTRY_WEAK
+# define __NONSECURE_CALL
+#endif
+
+
+
+extern uint32_t SystemCoreClock;    /*!< System Clock Frequency (Core Clock)  */
+extern uint32_t CyclesPerUs;        /*!< Cycles per micro second              */
+extern uint32_t PllClock;           /*!< PLL Output Clock Frequency           */
+extern uint32_t __PC(void);         /*!< Return the current program counter value */
+
+#if USE_ASSERT
+/**
+ * @brief      Assert Function
+ *
+ * @param[in]  expr  Expression to be evaluated
+ *
+ * @details    If the expression is false, an error message will be printed out
+ *             from debug port (UART0 or UART1).
+ */
+#define ASSERT_PARAM(expr)  { if (!(expr)) { AssertError((uint8_t*)__FILE__, __LINE__); } }
+
+void AssertError(uint8_t *file, uint32_t line);
+#else
+#define ASSERT_PARAM(expr)
+#endif
+
+#define assert_param(expr)  ASSERT_PARAM(expr)
+
+
+/**
+ * @brief    System Initialization
+ *
+ * @details  The necessary initialization of system.
+ */
+extern void SystemInit(void);
+
+
+/**
+ * @brief    Update the Variable SystemCoreClock
+ *
+ * @details  This function is used to update the variable SystemCoreClock
+ *           and must be called whenever the core clock is changed.
+ */
+extern void SystemCoreClockUpdate(void);
+
+
+
+
+#if (defined(__ICCARM__) && (__VER__ >= 7080000) && (__VER__ < 8020000))
+uint32_t __TZ_get_PSP_NS(void);
+void __TZ_set_PSP_NS(uint32_t topOfProcStack);
+int32_t __TZ_get_MSP_NS(void);
+void __TZ_set_MSP_NS(uint32_t topOfMainStack);
+uint32_t __TZ_get_PRIMASK_NS(void);
+void __TZ_set_PRIMASK_NS(uint32_t priMask);
+#endif
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_M2354_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/tamper_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/tamper_reg.h
new file mode 100644
index 0000000000..147bef87c2
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/tamper_reg.h
@@ -0,0 +1,1042 @@
+/**************************************************************************//**
+ * @file     tamper_reg.h
+ * @version  V1.00
+ * @brief    Tamper register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __TAMPER_REG_H__
+#define __TAMPER_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+
+/*---------------------------- Tamper Controller ----------------------------*/
+/**
+    @addtogroup Tamper Controller(TAMPER)
+    Memory Mapped Structure for Tamper Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var TAMPER_T::INIT
+     * Offset: 0x00  Tamper Function Initiation Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |TCORERST  |Tamper Core Reset
+     * |        |          |0 = Write 0x5500; the Tamper core block reset will be released.
+     * |        |          |1 = Write 0x55AA; the Tamper core block will be reset.
+     * |[31]    |TLDORDY   |Voltage Regulator Power Ready (Read Only)
+     * |        |          |0 = The power status of voltage regulator is not ready.
+     * |        |          |1 = The power status of voltage regulator is ready.
+     * @var TAMPER_T::FUNEN
+     * Offset: 0x04  Tamper Block Function Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |LXTDETEN  |LXT Clock Detection Enable Bit
+     * |        |          |0 = Write 0x40; the LXT clock detection Disabled.
+     * |        |          |1 = Write 0x44; the LXT clock detection Enabled.
+     * |[13:8]  |TMPIOSEL  |Tamper I/O Detection Selection Bit
+     * |        |          |0 = Write 0x90/0xA0/0xB0/0xC0/0xD0/0xE0 for tamper I/O 0~5; the I/O tamper function is detected through RTC block.
+     * |        |          |1 = Write 0x94/0xA4/0xB4/0xC4/0xD4/0xE4 for tamper I/O 0~5; the I/O tamper function is detected through Tamper block.
+     * |[23:16] |HIRC48MEN |HIRC48M Enable Bit
+     * |        |          |The HIRC48M is disabled when these bits equal 0x5A, otherwise it will be enabled with any other values.
+     * |[24]    |VGCHEN0   |Voltage Glitch Channel 0 Enable Bit
+     * |        |          |0 = Voltage glitch channel 0 Disabled.
+     * |        |          |1 = Voltage glitch channel 0 Enabled.
+     * |        |          |Note: To avoid the voltage glitch when the voltage channel is enabled, it is better to detect the voltage glitch about 150us after the channel is enabled.
+     * |[25]    |VGCHEN1   |Voltage Glitch Channel 1 Enable Bit
+     * |        |          |0 = Voltage glitch channel 1 Disabled.
+     * |        |          |1 = Voltage glitch channel 1 Enabled.
+     * |        |          |Note: To avoid the voltage glitch when the voltage channel is enabled, it is better to detect the voltage glitch about 150us after the channel is enabled.
+     * |[26]    |VGCHEN2   |Voltage Glitch Channel 2 Enable Bit
+     * |        |          |0 = Voltage glitch channel 2 Disabled.
+     * |        |          |1 = Voltage glitch channel 2 Enabled.
+     * |        |          |Note: To avoid the voltage glitch when the voltage channel is enabled, it is better to detect the voltage glitch about 150us after the channel is enabled.
+     * |[27]    |VGCHEN3   |Voltage Glitch Channel 3 Enable Bit
+     * |        |          |0 = Voltage glitch channel 3 Disabled.
+     * |        |          |1 = Voltage glitch channel 3 Enabled.
+     * |        |          |Note: To avoid the voltage glitch when the voltage channel is enabled, it is better to detect the voltage glitch about 150us after the channel is enabled.
+     * @var TAMPER_T::TRIEN
+     * Offset: 0x08  Tamper Trigger Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1]     |KSTRIGEN  |Key Store Trigger Enable Bit
+     * |        |          |0 = Tamper event is detected and to trigger Key Store Disabled.
+     * |        |          |1 = Tamper event is detected and to trigger Key Store Enabled.
+     * |[2]     |WAKEUPEN  |Wakeup Enable Bit
+     * |        |          |0 = Tamper wakeup event Disabled.
+     * |        |          |1 = Tamper wakeup event Enabled.
+     * |[3]     |CRYPTOEN  |Crypto Enable Bit
+     * |        |          |0 = Tamper event clear Crypto Disabled.
+     * |        |          |1 = Tamper event clear Crypto Enabled.
+     * |[4]     |CHIPRSTEN |Chip Reset Enable Bit
+     * |        |          |0 = Tamper event trigger chip reset Disabled.
+     * |        |          |1 = Tamper event trigger chip reset Enabled.
+     * |[5]     |RTCSPCLREN|RTC Spare Register Clear Enable Bit
+     * |        |          |0 = Tamper event trigger RTC spare register reset Disabled.
+     * |        |          |1 = Tamper event trigger RTC spare register reset Enabled.
+     * @var TAMPER_T::INTEN
+     * Offset: 0x0C  Tamper Event Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |TAMP0IEN  |Tamper 0 Event Interrupt Enable Bit
+     * |        |          |0 = Tamper 0 event interrupt Disabled.
+     * |        |          |1 = Tamper 0 event interrupt Enabled.
+     * |[1]     |TAMP1IEN  |Tamper 1 or Pair 0 Event Interrupt Enable Bit
+     * |        |          |0 = Tamper 1 or Pair 0 event interrupt Disabled.
+     * |        |          |1 = Tamper 1 or Pair 0 event interrupt Enabled.
+     * |[2]     |TAMP2IEN  |Tamper 2 Event Interrupt Enable Bit
+     * |        |          |0 = Tamper 2 event interrupt Disabled.
+     * |        |          |1 = Tamper 2 event interrupt Enabled.
+     * |[3]     |TAMP3IEN  |Tamper 3 or Pair 1 Event Interrupt Enable Bit
+     * |        |          |0 = Tamper 3 or Pair 1 event interrupt Disabled.
+     * |        |          |1 = Tamper 3 or Pair 1 event interrupt Enabled.
+     * |[4]     |TAMP4IEN  |Tamper 4 Event Interrupt Enable Bit
+     * |        |          |0 = Tamper 4 event interrupt Disabled.
+     * |        |          |1 = Tamper 4 event interrupt Enabled.
+     * |[5]     |TAMP5IEN  |Tamper 5 or Pair 2 Event Interrupt Enable Bit
+     * |        |          |0 = Tamper 5 or Pair 2 event interrupt Disabled.
+     * |        |          |1 = Tamper 5 or Pair 2 event interrupt Enabled.
+     * |[6]     |CLKFIEN   |LXT Clock Frequency Monitor Fail Event Interrupt Enable Bit
+     * |        |          |0 = LXT frequency fail event interrupt Disabled.
+     * |        |          |1 = LXT frequency fail event interrupt Enabled.
+     * |[7]     |CLKSTOPIEN|LXT Clock Frequency Monitor Stop Event Interrupt Enable Bit
+     * |        |          |0 = LXT frequency stop event interrupt Disabled.
+     * |        |          |1 = LXT frequency stop event interrupt Enabled.
+     * |[8]     |OVPIEN    |VDD Over Voltage Protect Detection Interrupt Enable Bit
+     * |        |          |0 = Detect VDD over voltage protect detection interrupt Disabled.
+     * |        |          |1 = Detect VDD over voltage protect detection interrupt Enabled.
+     * |        |          |Note: The function enable of the over voltage detection is defined in system manager.
+     * |[9]     |VGPIEN    |Voltage Glitch Positive Detection Event Interrupt Enable Bit
+     * |        |          |0 = LDO_CAP positive glitch event interrupt Disabled.
+     * |        |          |1 = LDO_CAP positive glitch event interrupt Enabled.
+     * |[10]    |VGNIEN    |Voltage Glitch Negative Detection Event Interrupt Enable Bit
+     * |        |          |0 = LDO_CAP negative glitch event interrupt Disabled.
+     * |        |          |1 = LDO_CAP negative glitch event interrupt Enabled.
+     * |[11]    |ACTSIEN   |Active Shield Event Interrupt Enable Bit
+     * |        |          |0 = Active shield event interrupt Disabled.
+     * |        |          |1 = Active shield event interrupt Enabled.
+     * |[16]    |RTCLVRIEN |RTC Low Voltage Detection Event Interrupt Enable Bit
+     * |        |          |0 = VBAT low voltage detection event interrupt Disabled.
+     * |        |          |1 = VBAT low voltage detection event interrupt Enabled.
+     * |[17]    |RTCIOIEN  |RTC Tamper I/O Event Interrupt Enable Bit
+     * |        |          |0 = RTC tamper I/O detection event interrupt Disabled.
+     * |        |          |1 = RTC tamper I/O detection event interrupt Enabled.
+     * |[18]    |RTCLKIEN  |RTC Clock Monitor Detection Event Interrupt Enable Bit
+     * |        |          |0 = RTC clock monitor event interrupt Disabled.
+     * |        |          |1 = RTC clock monitor event interrupt Enabled.
+     * |[22]    |BODIEN    |BOD Event Interrupt Enable Bit
+     * |        |          |0 = Brown-out event interrupt Disabled.
+     * |        |          |1 = Brown-out event interrupt Enabled.
+     * @var TAMPER_T::INTSTS
+     * Offset: 0x10  Tamper Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |TAMP0IF   |Tamper 0 Event Interrupt Flag
+     * |        |          |0 = No Tamper 0 event interrupt flag is generated.
+     * |        |          |1 = Tamper 0 event interrupt flag is generated.
+     * |        |          |Note: Write 1 to clear this bit.
+     * |[1]     |TAMP1IF   |Tamper 1 Event Interrupt Flag
+     * |        |          |0 = No Tamper 1 event interrupt flag is generated.
+     * |        |          |1 = Tamper 1 event interrupt flag is generated.
+     * |        |          |Note: Write 1 to clear this bit.
+     * |[2]     |TAMP2IF   |Tamper 2 Event Interrupt Flag
+     * |        |          |0 = No Tamper 2 event interrupt flag is generated.
+     * |        |          |1 = Tamper 2 event interrupt flag is generated.
+     * |        |          |Note: Write 1 to clear this bit.
+     * |[3]     |TAMP3IF   |Tamper 3 Event Interrupt Flag
+     * |        |          |0 = No Tamper 3 event interrupt flag is generated.
+     * |        |          |1 = Tamper 3 event interrupt flag is generated.
+     * |        |          |Note: Write 1 to clear this bit.
+     * |[4]     |TAMP4IF   |Tamper 4 Event Interrupt Flag
+     * |        |          |0 = No Tamper 4 event interrupt flag is generated.
+     * |        |          |1 = Tamper 4 event interrupt flag is generated.
+     * |        |          |Note: Write 1 to clear this bit.
+     * |[5]     |TAMP5IF   |Tamper 5 Event Interrupt Flag
+     * |        |          |0 = No Tamper 5 event interrupt flag is generated.
+     * |        |          |1 = Tamper 5 event interrupt flag is generated.
+     * |        |          |Note: Write 1 to clear this bit.
+     * |[6]     |CLKFAILIF |LXT Clock Frequency Monitor Fail Event Interrupt Flag
+     * |        |          |0 = LXT frequency is normal.
+     * |        |          |1 = LXT frequency is abnormal.
+     * |        |          |Note 1: Write 1 to clear this bit to 0.
+     * |        |          |Note 2: LXT detector will be automatically disabled when Fail/Stop flag rises, and resumes after Fail/Stop flag is cleared.
+     * |[7]     |CLKSTOPIF |LXT Clock Frequency Monitor Stop Event Interrupt Flag
+     * |        |          |0 = LXT frequency is normal.
+     * |        |          |1 = LXT frequency is almost stopped.
+     * |        |          |Note 1: Write 1 to clear this bit to 0.
+     * |        |          |Note 2: LXT detector will be automatically disabled when Fail/Stop flag rises, and resumes after Fail/Stop flag is cleared.
+     * |[8]     |OVPOUTIF  |VDD Over Voltage Event Interrupt Flag
+     * |        |          |0 = VDD no over voltage is detected.
+     * |        |          |1 = VDD over voltage is detected.
+     * |        |          |Note: Write 1 to clear this bit.
+     * |[9]     |VGPEVIF   |Voltage Glitch Positive Detection Interrupt Flag
+     * |        |          |0 = LDO_CAP positive glitch is not detected.
+     * |        |          |1 = LDO_CAP positive glitch is detected.
+     * |        |          |Note: It can be written 1 to clear only (No clear by TCORERST)
+     * |[10]    |VGNEVIF   |Voltage Glitch Negative Detection Interrupt Flag
+     * |        |          |0 = LDO_CAP negative glitch is not detected.
+     * |        |          |1 = LDO_CAP negative glitch is detected.
+     * |        |          |Note: It can be written 1 to clear only (No clear by TCORERST)
+     * |[11]    |ACTSEIF   |Active Shield Event Detection Interrupt Flag
+     * |        |          |0 = Active shield event interrupt flag is not detected.
+     * |        |          |1 = Active shield event interrupt flag is detected including the voltage of voltage regulator and GND attack.
+     * |        |          |Note: Write 1 to clear this bit after all of ACTSTxIF bits have been cleaned.
+     * |[13]    |ACTST5IF  |Active Shield Tamper 5 Event Interrupt Flag
+     * |        |          |0 = No Active shield Tamper 5 event interrupt flag is generated.
+     * |        |          |1 = Active shield Tamper 5 event interrupt flag is generated.
+     * |        |          |Note: Write 1 to clear this bit.
+     * |[15]    |ACTST25IF |Active Shield Tamper 5 Event Interrupt Flag
+     * |        |          |0 = No Active shield Tamper 5 event interrupt flag is generated.
+     * |        |          |1 = 2th Active shield Tamper 5 event interrupt flag is generated.
+     * |        |          |Note: Write 1 to clear this bit.
+     * |[16]    |RTCLVRIF  |RTC Low Voltage Detection Event Interrupt Flag
+     * |        |          |0 = VBAT low voltage detection event interrupt flag is not detected.
+     * |        |          |1 = VBAT low voltage detection event interrupt flag is detected.
+     * |[17]    |RIOTRIGIF |RTC Tamper I/O Event Interrupt Flag
+     * |        |          |0 = There is no RTC tamper I/O detection event interrupt flag.
+     * |        |          |1 = There is RTC tamper I/O detection event interrupt flag.
+     * |[18]    |RCLKTRIGIF|RTC Clock Monitor Detection Event Interrupt Flag
+     * |        |          |0 = There is no RTC clock monitor detection event interrupt flag.
+     * |        |          |1 = There is RTC clock monitor detection event interrupt flag.
+     * |[22]    |BODIF     |BOD Event Interrupt Flag
+     * |        |          |0 = Brown-out event interrupt flag is no detected.
+     * |        |          |1 = Brown-out interrupt flag is detected.
+     * |        |          |Note: It is used to detect the LDO_CAP. Write 1 to clear this bit.
+     * |[25]    |ACTST1IF  |Active Shield Tamper 1 Event Interrupt Flag
+     * |        |          |0 = No Active shield Tamper 1 event interrupt flag is generated.
+     * |        |          |1 = Active shield Tamper 1 event interrupt flag is generated.
+     * |        |          |Note: Write 1 to clear this bit.
+     * |[27]    |ACTST3IF  |Active Shield Tamper 3 Event Interrupt Flag
+     * |        |          |0 = No Active shield Tamper 3 event interrupt flag is generated.
+     * |        |          |1 = Active shield Tamper 3 event interrupt flag is generated.
+     * |        |          |Note: Write 1 to clear this bit.
+     * |[29]    |ACTST21IF |2th Active Shield Tamper 1 Event Interrupt Flag
+     * |        |          |0 = No Active shield Tamper 1 event interrupt flag is generated.
+     * |        |          |1 = 2th Active shield Tamper 1 event interrupt flag is generated.
+     * |        |          |Note: Write 1 to clear this bit.
+     * |[31]    |ACTST23IF |2th Active Shield Tamper 3 Event Interrupt Flag
+     * |        |          |0 = No Active shield Tamper 3 event interrupt flag is generated.
+     * |        |          |1 = 2th Active shield Tamper 3 event interrupt flag is generated.
+     * |        |          |Note: Write 1 to clear this bit.
+     * @var TAMPER_T::LIRCTL
+     * Offset: 0x14  Tamper LIRC Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[8:0]   |TLRCTRIM  |Tamper TLIRC32K Trim Value
+     * |        |          |TLIRC32K trim value setting
+     * |[10:9]  |TRIMMOS   |Tamper TLIRC32K Trim MOS Value
+     * |        |          |TLIRC32K trim MOS value setting
+     * @var TAMPER_T::TIOCTL
+     * Offset: 0x18  Tamper I/O Function Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |DYN1ISS   |Dynamic Pair 1 Input Source Select
+     * |        |          |This bit determines Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode.
+     * |        |          |0 = Tamper input is from Tamper 2.
+     * |        |          |1 = Tamper input is from Tamper 0.
+     * |        |          |Note: This bit is effective only when DYNPR1EN (TAMPER_TIOCTL[23]) and DYNPR0EN (TAMPER_TIOCTL[15]) are set.
+     * |[1]     |DYN2ISS   |Dynamic Pair 2 Input Source Select
+     * |        |          |This bit determines Tamper 5 input is from Tamper 4 or Tamper 0 in dynamic mode.
+     * |        |          |0 = Tamper input is from Tamper 4.
+     * |        |          |1 = Tamper input is from Tamper 0.
+     * |        |          |Note: This bit has effect only when DYNPR2EN (TAMPER_TIOCTL[31]) and DYNPR0EN (TAMPER_TIOCTL[15]) are set.
+     * |[3]     |DYNSRC    |Dynamic Reference Pattern
+     * |        |          |This field determines the new reference pattern when current pattern run out in dynamic pair mode.
+     * |        |          |0 = The new reference pattern is generated by random number generator when the reference pattern run out.
+     * |        |          |1 = The new reference pattern is repeated from SEED (TAMPER_SEED[31:0]) when the reference pattern run out.
+     * |        |          |Note: After this bit is modified, the SEEDRLD (TAMPER_TIOCTL[4]) should be set.
+     * |[4]     |SEEDRLD   |Reload New Seed for PRNG Engine
+     * |        |          |Setting this bit, the tamper configuration will be reloaded.
+     * |        |          |0 = Generating key based on the current seed.
+     * |        |          |1 = Reload new seed.
+     * |        |          |Note 1: Before this bit is set, the tamper configuration should be set to complete and this bit will be auto clear to 0 after reload new seed completed.
+     * |        |          |Note 2: The reference is RTC-clock. Tamper detector needs sync 2 ~ 3 RTC-clock.
+     * |[7:5]   |DYNRATE   |Dynamic Change Rate
+     * |        |          |This item is choice the dynamic tamper output change rate.
+     * |        |          |000 = 26 * RTC_CLK.
+     * |        |          |001 = 27 * RTC_CLK.
+     * |        |          |010 = 28 * RTC_CLK.
+     * |        |          |011 = 29 * RTC_CLK.
+     * |        |          |100 = 210 * RTC_CLK.
+     * |        |          |101 = 211 * RTC_CLK.
+     * |        |          |110 = 212 * RTC_CLK.
+     * |        |          |111 = 213 * RTC_CLK.
+     * |        |          |Note: After revising this field, setting SEEDRLD (TAMPER_TIOCTL[4]) can reload change rate immediately.
+     * |[8]     |TAMP0EN   |Tamper0 Detect Enable Bit
+     * |        |          |0 = Tamper 0 detect Disabled.
+     * |        |          |1 = Tamper 0 detect Enabled.
+     * |        |          |Note: The reference is RTC-clock. Tamper detector needs sync 2 ~ 3 RTC-clock.
+     * |[9]     |TAMP0LV   |Tamper 0 Level
+     * |        |          |This bit depends on level attribute of tamper pin for static tamper detection.
+     * |        |          |0 = Detect voltage level is low.
+     * |        |          |1 = Detect voltage level is high.
+     * |[10]    |TAMP0DBEN |Tamper 0 De-bounce Enable Bit
+     * |        |          |0 = Tamper 0 de-bounce Disabled.
+     * |        |          |1 = Tamper 0 de-bounce Enabled. Tamper detection pin will sync 1 RTC clock.
+     * |[12]    |TAMP1EN   |Tamper 1 Detect Enable Bit
+     * |        |          |0 = Tamper 1 detect Disabled.
+     * |        |          |1 = Tamper 1 detect Enabled.
+     * |        |          |Note: The reference is RTC-clock. Tamper detector needs sync 2 ~ 3 RTC-clock.
+     * |[13]    |TAMP1LV   |Tamper 1 Level
+     * |        |          |This bit depends on level attribute of tamper pin for static tamper detection.
+     * |        |          |0 = Detect voltage level is low.
+     * |        |          |1 = Detect voltage level is high.
+     * |[14]    |TAMP1DBEN |Tamper 1 De-bounce Enable Bit
+     * |        |          |0 = Tamper 1 de-bounce Disabled.
+     * |        |          |1 = Tamper 1 de-bounce Enabled, tamper detection pin will sync 1 RTC clock.
+     * |[15]    |DYNPR0EN  |Dynamic Pair 0 Enable Bit
+     * |        |          |0 = Static detect.
+     * |        |          |1 = Dynamic detect.
+     * |[16]    |TAMP2EN   |Tamper 2 Detect Enable Bit
+     * |        |          |0 = Tamper 2 detect Disabled.
+     * |        |          |1 = Tamper 2 detect Enabled.
+     * |        |          |Note: The reference is RTC-clock. Tamper detector need sync 2 ~ 3 RTC-clock.
+     * |[17]    |TAMP2LV   |Tamper 2 Level
+     * |        |          |This bit depends on level attribute of tamper pin for static tamper detection.
+     * |        |          |0 = Detect voltage level is low.
+     * |        |          |1 = Detect voltage level is high.
+     * |[18]    |TAMP2DBEN |Tamper 2 De-bounce Enable Bit
+     * |        |          |0 = Tamper 2 de-bounce Disabled.
+     * |        |          |1 = Tamper 2 de-bounce Enabled. Tamper detection pin will sync 1 RTC clock.
+     * |[20]    |TAMP3EN   |Tamper 3 Detect Enable Bit
+     * |        |          |0 = Tamper 3 detect Disabled.
+     * |        |          |1 = Tamper 3 detect Enabled.
+     * |        |          |Note: The reference is RTC-clock. Tamper detector needs sync 2 ~ 3 RTC-clock.
+     * |[21]    |TAMP3LV   |Tamper 3 Level
+     * |        |          |This bit depends on level attribute of tamper pin for static tamper detection.
+     * |        |          |0 = Detect voltage level is low.
+     * |        |          |1 = Detect voltage level is high.
+     * |[22]    |TAMP3DBEN |Tamper 3 De-bounce Enable Bit
+     * |        |          |0 = Tamper 3 de-bounce Disabled.
+     * |        |          |1 = Tamper 3 de-bounce Enabled. Tamper detection pin will sync 1 RTC clock.
+     * |[23]    |DYNPR1EN  |Dynamic Pair 1 Enable Bit
+     * |        |          |0 = Static detect.
+     * |        |          |1 = Dynamic detect.
+     * |[24]    |TAMP4EN   |Tamper4 Detect Enable Bit
+     * |        |          |0 = Tamper 4 detect Disabled.
+     * |        |          |1 = Tamper 4 detect Enabled.
+     * |        |          |Note: The reference is RTC-clock. Tamper detector needs sync 2 ~ 3 RTC-clock.
+     * |[25]    |TAMP4LV   |Tamper 4 Level
+     * |        |          |This bit depends on level attribute of tamper pin for static tamper detection.
+     * |        |          |0 = Detect voltage level is low.
+     * |        |          |1 = Detect voltage level is high.
+     * |[26]    |TAMP4DBEN |Tamper 4 De-bounce Enable Bit
+     * |        |          |0 = Tamper 4 de-bounce Disabled.
+     * |        |          |1 = Tamper 4 de-bounce Enabled. Tamper detection pin will sync 1 RTC clock.
+     * |[28]    |TAMP5EN   |Tamper 5 Detect Enable Bit
+     * |        |          |0 = Tamper 5 detect Disabled.
+     * |        |          |1 = Tamper 5 detect Enabled.
+     * |        |          |Note: The reference is RTC-clock. Tamper detector needs sync 2 ~ 3 RTC-clock.
+     * |[29]    |TAMP5LV   |Tamper 5 Level
+     * |        |          |This bit depends on level attribute of tamper pin for static tamper detection.
+     * |        |          |0 = Detect voltage level is low.
+     * |        |          |1 = Detect voltage level is high.
+     * |[30]    |TAMP5DBEN |Tamper 5 De-bounce Enable Bit
+     * |        |          |0 = Tamper 5 de-bounce Disabled.
+     * |        |          |1 = Tamper 5 de-bounce Enabled. Tamper detection pin will sync 1 RTC clock.
+     * |[31]    |DYNPR2EN  |Dynamic Pair 2 Enable Bit
+     * |        |          |0 = Static detect.
+     * |        |          |1 = Dynamic detect.
+     * @var TAMPER_T::SEED
+     * Offset: 0x1C  Tamper Seed Value Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SEED      |Seed value.
+     * @var TAMPER_T::SEED2
+     * Offset: 0x20  Tamper 2nd Seed Value Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |SEED2     |Seed value. These seed value are used for 2nd active shield I/O.
+     * @var TAMPER_T::ACTSTIOCTL1
+     * Offset: 0x24  Tamper Active Shield Tamper I/O Function Control Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ADYN1ISS  |Active Shied Dynamic Pair 1 Input Source Select
+     * |        |          |This bit determines Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode.
+     * |        |          |0 = Tamper input is from Tamper 2.
+     * |        |          |1 = Tamper input is from Tamper 0.
+     * |        |          |Note: This bit is effective only when ADYNPR1EN (TAMPER_ACTSTIOCTL1[23]) and ADYNPR0EN (TAMPER_ACTSTIOCTL1[15]) are set.
+     * |[3]     |ADYNSRC   |Active Shied Dynamic Reference Pattern
+     * |        |          |This field determines the new reference pattern when current pattern run out in dynamic pair mode.
+     * |        |          |0 = The new reference pattern is generated by random number generator when the reference pattern run out.
+     * |        |          |1 = The new reference pattern is repeated from SEED (TAMPER_SEED[31:0]) when the reference pattern run out.
+     * |        |          |Note: After this bit is modified, the SEEDRLD (TAMPER_TIOCTL[4]) should be set.
+     * |[7:5]   |ADYNRATE  |Active Shied Dynamic Change Rate
+     * |        |          |Use the bits to choose the dynamic tamper output change rate.
+     * |        |          |000 = 210 * TLIRC32K.
+     * |        |          |001 = 211 * TLIRC32K.
+     * |        |          |010 = 212 * TLIRC32K.
+     * |        |          |011 = 213 * TLIRC32K.
+     * |        |          |100 = 214 * TLIRC32K.
+     * |        |          |101 = 215 * TLIRC32K.
+     * |        |          |110 = 216 * TLIRC32K.
+     * |        |          |111 = 217 * TLIRC32K.
+     * |        |          |Note: After this field is modified, setting SEEDRLD (TAMPER_TIOCTL[4]) can reload the change rate immediately.
+     * |[8]     |ATAMP0EN  |Active Shied Tamper0 Detect Enable Bit
+     * |        |          |0 = Tamper 0 detect Disabled.
+     * |        |          |1 = Tamper 0 detect Enabled.
+     * |        |          |Note: The reference is TLIRC 32K-clock. Tamper detector need sync 2 ~ 3 TLIRC 32K-clock.
+     * |[12]    |ATAMP1EN  |Active Shied Tamper 1 Detect Enable Bit
+     * |        |          |0 = Tamper 1 detect Disabled.
+     * |        |          |1 = Tamper 1 detect Enabled.
+     * |        |          |Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock.
+     * |[15]    |ADYNPR0EN |Active Shied Dynamic Pair 0 Enable Bit
+     * |        |          |0 = Static detect (Not supported).
+     * |        |          |1 = Dynamic detect.
+     * |[16]    |ATAMP2EN  |Active Shied Tamper 2 Detect Enable Bit
+     * |        |          |0 = Tamper 2 detect Disabled.
+     * |        |          |1 = Tamper 2 detect Enabled.
+     * |        |          |Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock.
+     * |[20]    |ATAMP3EN  |Active Shied Tamper 3 Detect Enable Bit
+     * |        |          |0 = Tamper 3 detect Disabled.
+     * |        |          |1 = Tamper 3 detect Enabled.
+     * |        |          |Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock.
+     * |[23]    |ADYNPR1EN |Active Shied Dynamic Pair 1 Enable Bit
+     * |        |          |0 = Static detect (Not supported).
+     * |        |          |1 = Dynamic detect.
+     * |[24]    |ATAMP4EN  |Active Tamper4 Detect Enable Bit
+     * |        |          |0 = Tamper 4 detect Disabled.
+     * |        |          |1 = Tamper 4 detect Enabled.
+     * |        |          |Note: The reference is TLIRC 32K-clock. Tamper detector need sync 2 ~ 3 TLIRC 32K-clock.
+     * |[28]    |ATAMP5EN  |Active Tamper 5 Detect Enable Bit
+     * |        |          |0 = Tamper 5 detect Disabled.
+     * |        |          |1 = Tamper 5 detect Enabled.
+     * |        |          |Note: The reference is TLIRC 32K-clock. Tamper detector need sync 2 ~ 3 TLIRC 32K-clock.
+     * |[31]    |ADYNPR2EN |Active Shied Dynamic Pair 2 Enable Bit
+     * |        |          |0 = Static detect (Not supported).
+     * |        |          |1 = Dynamic detect.
+     * @var TAMPER_T::ACTSTIOCTL2
+     * Offset: 0x28  Tamper Active Shield Tamper I/O Function Control Register 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ADYN1ISS2 |Active Shied Dynamic Pair 1 Input Source Select 2
+     * |        |          |This bit determines if Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode.
+     * |        |          |0 = Tamper input is from Tamper 2.
+     * |        |          |1 = Tamper input is from Tamper 0.
+     * |        |          |Note: This bit is effective only when ADYNPR1EN2 (TAMPER_ACTSTIOCTL2[23]) and ADYNPR0EN2 (TAMPER_ACTSTIOCTL2[15]) are set.
+     * |[3]     |ADYNSRC2  |Active Shied Dynamic Reference Pattern 2
+     * |        |          |This field determines the new reference pattern when current pattern run out in dynamic pair mode.
+     * |        |          |0 = The new reference pattern is generated by random number generator when the reference pattern run out.
+     * |        |          |1 = The new reference pattern is repeated from SEED2 (TAMPER_SEED2[31:0]) when the reference pattern run out.
+     * |        |          |Note: After this bit is modified, the SEEDRLD2 (TAMPER_ACTSTIOCTL2[4]) should be set.
+     * |[4]     |SEEDRLD2  |Reload New Seed for PRNG Engine 2
+     * |        |          |Setting this bit, the tamper configuration will be reloaded.
+     * |        |          |0 = Generating key based on the current seed.
+     * |        |          |1 = Reload new seed.
+     * |        |          |Note 1: Before this bit is set, the tamper configuration should be set to complete and this bit will be auto clear to 0 after reload new seed completed.
+     * |        |          |Note 2: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock.
+     * |[7:5]   |ADYNRATE2 |Active Shied Dynamic Change Rate 2
+     * |        |          |Use the bits to choose the dynamic tamper output change rate.
+     * |        |          |000 = 210 * TLIRC32K.
+     * |        |          |001 = 211 * TLIRC32K.
+     * |        |          |010 = 212 * TLIRC32K.
+     * |        |          |011 = 213 * TLIRC32K.
+     * |        |          |100 = 214 * TLIRC32K.
+     * |        |          |101 = 215 * TLIRC32K.
+     * |        |          |110 = 216 * TLIRC32K.
+     * |        |          |111 = 217 * TLIRC32K.
+     * |        |          |Note: After this field is modified, setting SEEDRLD2 (TAMPER_ACTSTIOCTL2[4]) can reload change rate immediately.
+     * |[8]     |ATAMP0EN2 |Active Shied Tamper0 Detect Enable Bit 2
+     * |        |          |0 = Tamper 0 detect Disabled.
+     * |        |          |1 = Tamper 0 detect Enabled.
+     * |        |          |Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock.
+     * |[12]    |ATAMP1EN2 |Active Shied Tamper 1 Detect Enable Bit 2
+     * |        |          |0 = Tamper 1 detect Disabled.
+     * |        |          |1 = Tamper 1 detect Enabled.
+     * |        |          |Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock.
+     * |[15]    |ADYNPR0EN2|Active Shied Dynamic Pair 0 Enable Bit 2
+     * |        |          |0 = Static detect (Not supported).
+     * |        |          |1 = Dynamic detect.
+     * |[16]    |ATAMP2EN2 |Active Shied Tamper 2 Detect Enable Bit 2
+     * |        |          |0 = Tamper 2 detect Disabled.
+     * |        |          |1 = Tamper 2 detect Enabled.
+     * |        |          |Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock.
+     * |[20]    |ATAMP3EN2 |Active Shied Tamper 3 Detect Enable Bit 2
+     * |        |          |0 = Tamper 3 detect Disabled.
+     * |        |          |1 = Tamper 3 detect Enabled.
+     * |        |          |Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock.
+     * |[23]    |ADYNPR1EN2|Active Shied Dynamic Pair 1 Enable Bit 2
+     * |        |          |0 = Static detect (Not supported).
+     * |        |          |1 = Dynamic detect.
+     * |[24]    |ATAMP4EN2 |Active Shied Tamper4 Detect Enable Bit 2
+     * |        |          |0 = Tamper 4 detect Disabled.
+     * |        |          |1 = Tamper 4 detect Enabled.
+     * |        |          |Note: The reference is TLIRC 32K-clock. Tamper detector need sync 2 ~ 3 TLIRC 32K-clock.
+     * |[28]    |ATAMP5EN2 |Active Tamper 5 Detect Enable Bit 2
+     * |        |          |0 = Tamper 5 detect Disabled.
+     * |        |          |1 = Tamper 5 detect Enabled.
+     * |        |          |Note: The reference is TLIRC 32K-clock. Tamper detector need sync 2 ~ 3 TLIRC 32K-clock.
+     * |[31]    |ADYNPR2EN2|Active Shied Dynamic Pair 2 Enable Bit 2
+     * |        |          |0 = Static detect (Not supported).
+     * |        |          |1 = Dynamic detect.
+     * @var TAMPER_T::CDBR
+     * Offset: 0x2C  Tamper Clock Frequency Detector Boundary Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |STOPBD    |LXT Clock Frequency Detector Stop Boundary
+     * |        |          |The bits define the stop value of frequency monitor window.
+     * |        |          |When LXT frequency monitor counter lower than Clock Frequency Detector Stop Boundary, the LXT frequency detect stop interrupt flag will set to 1.
+     * |        |          |Note: The boundary is defined as the maximum value of LXT among 256 Tamper clock time.
+     * |[23:16] |FAILBD    |LXT Clock Frequency Detector Fail Boundary
+     * |        |          |The bits define the fail value of frequency monitor window.
+     * |        |          |When LXT frequency monitor counter lower than Clock Frequency Detector Fail Boundary, the LXT frequency detect fail interrupt flag will set to 1.
+     * |        |          |Note: The boundary is defined as the minimum value of LXT among 256 Tamper clock time.
+     * @var TAMPER_T::VG
+     * Offset: 0x30  Tamper Voltage Glitch Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |PCLKSEL0  |PL0 Positive Clock Trim Range
+     * |        |          |The setting value of the positive clock tolerance.
+     * |        |          |One step is about 2.5% tolerance. The maximum tolerance is 20%.
+     * |        |          |Note: PL0 means the power level is 1.26V
+     * |        |          |The power level is controlled in system manager
+     * |[7:4]   |NCLKSEL0  |PL0 Negative Clock Trim Range
+     * |        |          |The setting value of the negative clock tolerance.
+     * |        |          |One step is about 2.5% tolerance. The maximum tolerance is 20%.
+     * |[11:8]  |PDATSEL0  |PL0 Positive Data Trim Range
+     * |        |          |The setting value of the positive data tolerance.
+     * |        |          |One step is about 2.5% tolerance. The maximum tolerance is 20%.
+     * |[15:12] |NDATSEL0  |PL0 Negative Data Trim Range
+     * |        |          |The setting value of the negative data tolerance.
+     * |        |          |One step is about 2.5% tolerance. The maximum tolerance is 20%.
+     * |[19:16] |PCLKSEL1  |PL1 Positive Clock Trim Range
+     * |        |          |The setting value of the positive clock tolerance.
+     * |        |          |One step is about 2.5% tolerance. The maximum tolerance is 20%.
+     * |        |          |Note: PL1 means the power level is 1.2V
+     * |[23:20] |NCLKSEL1  |PL1 Negative Clock Trim Range
+     * |        |          |The setting value of the negative clock tolerance.
+     * |        |          |One step is about 2.5% tolerance. The maximum tolerance is 20%.
+     * |[27:24] |PDATSEL1  |PL1 Positive Data Trim Range
+     * |        |          |The setting value of the positive data tolerance.
+     * |        |          |One step is about 2.5% tolerance. The maximum tolerance is 20%.
+     * |[31:28] |NDATSEL1  |PL1 Negative Data Trim Range
+     * |        |          |The setting value of the negative data tolerance.
+     * |        |          |One step is about 2.5% tolerance. The maximum tolerance is 20%.
+     * @var TAMPER_T::VGEV
+     * Offset: 0x34  Tamper Voltage Glitch Event Tolerance Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |VGECNTP   |Positive Voltage Glitch Error Tolerance
+     * |        |          |The value indicates the tolerance count for positive voltage glitch event.
+     * |[15:8]  |VGECNTN   |Negative Voltage Glitch Error Tolerance
+     * |        |          |The value indicates the tolerance count for negative voltage glitch event.
+     * @var TAMPER_T::LDOTRIM
+     * Offset: 0x38  Tamper LDO Trim Value Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |TLDOTRIM  |Voltage Regulator Output Voltage Trim
+     * |        |          |The value indicates the trim value of the voltage regulator output voltage.
+     * |[9:8]   |TLDOIQSEL |Voltage Regulator Qu Current Selection
+     * |        |          |Indicates the Qu current selection of voltage regulator.
+     * @var TAMPER_T::LBSTRIM
+     * Offset: 0x3C  Tamper LDO BIAS Trim Value Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |TLVDSEL   |Under-shoot Detect Level Trim Bits
+     * |        |          |The value indicates the trim value of the under-shoot detection level
+     * |[4]     |TOVDSEL   |Over-shoot Detect Level Trim Bits
+     * |        |          |The value indicates the trim value of the over-shoot detection level
+     * |[9:8]   |BSCMPLV   |Under-shoot Detect Comparator Current Trim Bits
+     * |        |          |The value indicates the trim value of the under-shoot detection comparator current trim level
+     * |[11:10] |BSCMPOV   |Over-shoot Detect Comparator Current Trim Bits
+     * |        |          |The value indicates the trim value of the over-shoot detection comparator current trim level
+     * |[13:12] |HYSCMPLV  |Under-shoot Detect Comparator Hysteresis Trim Bits
+     * |        |          |The value indicates the trim value of the under-shoot detection comparator of hysteresis trim level
+     * |[15:14] |HYSCMPOV  |Over-shoot Detect Comparator Hysteresis Trim Bits
+     * |        |          |The value indicates the trim value of the over-shoot detection comparator of hysteresis trim level
+     * @var TAMPER_T::VG2
+     * Offset: 0x40  Tamper Voltage Glitch Control Register 2
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |PCLKSEL2  |PL2 Positive Clock Trim Range
+     * |        |          |The setting value of the positive clock tolerance.
+     * |        |          |One step is about 2.5% tolerance. The maximum tolerance is 20%.
+     * |        |          |Note: PL2 means the power level is 1.1V
+     * |        |          |The power level is controlled in system manager.
+     * |[7:4]   |NCLKSEL2  |PL2 Negative Clock Trim Range
+     * |        |          |The setting value of the negative clock tolerance.
+     * |        |          |One step is about 2.5% tolerance. The maximum tolerance is 20%.
+     * |[11:8]  |PDATSEL2  |PL2 Positive Data Trim Range
+     * |        |          |The setting value of the positive data tolerance.
+     * |        |          |One step is about 2.5% tolerance. The maximum tolerance is 20%.
+     * |[15:12] |NDATSEL2  |PL2 Negative Data Trim Range
+     * |        |          |The setting value of the negative data tolerance.
+     * |        |          |One step is about 2.5% tolerance. The maximum tolerance is 20%.
+     * |[19:16] |PCLKSEL3  |PL3 Positive Clock Trim Range
+     * |        |          |The setting value of the positive clock tolerance.
+     * |        |          |One step is about 2.5% tolerance. The maximum tolerance is 20%.
+     * |        |          |Note: PL3 means the power level is 0.9V
+     * |[23:20] |NCLKSEL3  |PL3 Negative Clock Trim Range
+     * |        |          |The setting value of the negative clock tolerance.
+     * |        |          |One step is about 2.5% tolerance. The maximum tolerance is 20%.
+     * |[27:24] |PDATSEL3  |PL3 Positive Data Trim Range
+     * |        |          |The setting value of the positive data tolerance.
+     * |        |          |One step is about 2.5% tolerance. The maximum tolerance is 20%.
+     * |[31:28] |NDATSEL3  |PL3 Negative Data Trim Range
+     * |        |          |The setting value of the negative data tolerance.
+     * |        |          |One step is about 2.5% tolerance. The maximum tolerance is 20%.
+     */
+    __IO uint32_t INIT;                  /*!< [0x0000] Tamper Function Initiation Register                              */
+    __IO uint32_t FUNEN;                 /*!< [0x0004] Tamper Block Function Enable Register                            */
+    __IO uint32_t TRIEN;                 /*!< [0x0008] Tamper Trigger Enable Register                                   */
+    __IO uint32_t INTEN;                 /*!< [0x000c] Tamper Event Interrupt Enable Register                           */
+    __IO uint32_t INTSTS;                /*!< [0x0010] Tamper Interrupt Status Register                                 */
+    __IO uint32_t LIRCTL;                /*!< [0x0014] Tamper LIRC Control Register                                     */
+    __IO uint32_t TIOCTL;                /*!< [0x0018] Tamper I/O Function Control Register                             */
+    __IO uint32_t SEED;                  /*!< [0x001c] Tamper Seed Value Control Register                               */
+    __IO uint32_t SEED2;                 /*!< [0x0020] Tamper 2nd Seed Value Control Register                           */
+    __IO uint32_t ACTSTIOCTL1;           /*!< [0x0024] Tamper Active Shield Tamper I/O Function Control Register 1      */
+    __IO uint32_t ACTSTIOCTL2;           /*!< [0x0028] Tamper Active Shield Tamper I/O Function Control Register 2      */
+    __IO uint32_t CDBR;                  /*!< [0x002c] Tamper Clock Frequency Detector Boundary Register                */
+    __IO uint32_t VG;                    /*!< [0x0030] Tamper Voltage Glitch Control Register                           */
+    __IO uint32_t VGEV;                  /*!< [0x0034] Tamper Voltage Glitch Event Tolerance Control Register           */
+    __IO uint32_t LDOTRIM;               /*!< [0x0038] Tamper LDO Trim Value Control Register                           */
+    __IO uint32_t LBSTRIM;               /*!< [0x003c] Tamper LDO BIAS Trim Value Control Register                      */
+    __IO uint32_t VG2;                   /*!< [0x0040] Tamper Voltage Glitch Control Register 2                         */
+
+} TAMPER_T;
+
+/**
+    @addtogroup TAMPER_CONST Tamper Bit Field Definition
+    Constant Definitions for Tamper Controller
+  @{
+*/
+
+#define TAMPER_INIT_TCORERST_Pos         (0)                                               /*!< TAMPER_T::INIT: TCORERST Position      */
+#define TAMPER_INIT_TCORERST_Msk         (0x1ul << TAMPER_INIT_TCORERST_Pos)               /*!< TAMPER_T::INIT: TCORERST Mask          */
+
+#define TAMPER_INIT_TLDORDY_Pos          (31)                                              /*!< TAMPER_T::INIT: TLDORDY Position       */
+#define TAMPER_INIT_TLDORDY_Msk          (0x1ul << TAMPER_INIT_TLDORDY_Pos)                /*!< TAMPER_T::INIT: TLDORDY Mask           */
+
+#define TAMPER_FUNEN_LXTDETEN_Pos        (0)                                               /*!< TAMPER_T::FUNEN: LXTDETEN Position     */
+#define TAMPER_FUNEN_LXTDETEN_Msk        (0x1ul << TAMPER_FUNEN_LXTDETEN_Pos)              /*!< TAMPER_T::FUNEN: LXTDETEN Mask         */
+
+#define TAMPER_FUNEN_TMPIOSEL_Pos        (8)                                               /*!< TAMPER_T::FUNEN: TMPIOSEL Position     */
+#define TAMPER_FUNEN_TMPIOSEL_Msk        (0x3ful << TAMPER_FUNEN_TMPIOSEL_Pos)             /*!< TAMPER_T::FUNEN: TMPIOSEL Mask         */
+
+#define TAMPER_FUNEN_HIRC48MEN_Pos       (16)                                              /*!< TAMPER_T::FUNEN: HIRC48MEN Position    */
+#define TAMPER_FUNEN_HIRC48MEN_Msk       (0xfful << TAMPER_FUNEN_HIRC48MEN_Pos)            /*!< TAMPER_T::FUNEN: HIRC48MEN Mask        */
+
+#define TAMPER_FUNEN_VGCHEN0_Pos         (24)                                              /*!< TAMPER_T::FUNEN: VGCHEN0 Position      */
+#define TAMPER_FUNEN_VGCHEN0_Msk         (0x1ul << TAMPER_FUNEN_VGCHEN0_Pos)               /*!< TAMPER_T::FUNEN: VGCHEN0 Mask          */
+
+#define TAMPER_FUNEN_VGCHEN1_Pos         (25)                                              /*!< TAMPER_T::FUNEN: VGCHEN1 Position      */
+#define TAMPER_FUNEN_VGCHEN1_Msk         (0x1ul << TAMPER_FUNEN_VGCHEN1_Pos)               /*!< TAMPER_T::FUNEN: VGCHEN1 Mask          */
+
+#define TAMPER_FUNEN_VGCHEN2_Pos         (26)                                              /*!< TAMPER_T::FUNEN: VGCHEN2 Position      */
+#define TAMPER_FUNEN_VGCHEN2_Msk         (0x1ul << TAMPER_FUNEN_VGCHEN2_Pos)               /*!< TAMPER_T::FUNEN: VGCHEN2 Mask          */
+
+#define TAMPER_FUNEN_VGCHEN3_Pos         (27)                                              /*!< TAMPER_T::FUNEN: VGCHEN3 Position      */
+#define TAMPER_FUNEN_VGCHEN3_Msk         (0x1ul << TAMPER_FUNEN_VGCHEN3_Pos)               /*!< TAMPER_T::FUNEN: VGCHEN3 Mask          */
+
+#define TAMPER_TRIEN_KSTRIGEN_Pos        (1)                                               /*!< TAMPER_T::TRIEN: KSTRIGEN Position     */
+#define TAMPER_TRIEN_KSTRIGEN_Msk        (0x1ul << TAMPER_TRIEN_KSTRIGEN_Pos)              /*!< TAMPER_T::TRIEN: KSTRIGEN Mask         */
+
+#define TAMPER_TRIEN_WAKEUPEN_Pos        (2)                                               /*!< TAMPER_T::TRIEN: WAKEUPEN Position     */
+#define TAMPER_TRIEN_WAKEUPEN_Msk        (0x1ul << TAMPER_TRIEN_WAKEUPEN_Pos)              /*!< TAMPER_T::TRIEN: WAKEUPEN Mask         */
+
+#define TAMPER_TRIEN_CRYPTOEN_Pos        (3)                                               /*!< TAMPER_T::TRIEN: CRYPTOEN Position     */
+#define TAMPER_TRIEN_CRYPTOEN_Msk        (0x1ul << TAMPER_TRIEN_CRYPTOEN_Pos)              /*!< TAMPER_T::TRIEN: CRYPTOEN Mask         */
+
+#define TAMPER_TRIEN_CHIPRSTEN_Pos       (4)                                               /*!< TAMPER_T::TRIEN: CHIPRSTEN Position    */
+#define TAMPER_TRIEN_CHIPRSTEN_Msk       (0x1ul << TAMPER_TRIEN_CHIPRSTEN_Pos)             /*!< TAMPER_T::TRIEN: CHIPRSTEN Mask        */
+
+#define TAMPER_TRIEN_RTCSPCLREN_Pos      (5)                                               /*!< TAMPER_T::TRIEN: RTCSPCLREN Position   */
+#define TAMPER_TRIEN_RTCSPCLREN_Msk      (0x1ul << TAMPER_TRIEN_RTCSPCLREN_Pos)            /*!< TAMPER_T::TRIEN: RTCSPCLREN Mask       */
+
+#define TAMPER_INTEN_TAMP0IEN_Pos        (0)                                               /*!< TAMPER_T::INTEN: TAMP0IEN Position     */
+#define TAMPER_INTEN_TAMP0IEN_Msk        (0x1ul << TAMPER_INTEN_TAMP0IEN_Pos)              /*!< TAMPER_T::INTEN: TAMP0IEN Mask         */
+
+#define TAMPER_INTEN_TAMP1IEN_Pos        (1)                                               /*!< TAMPER_T::INTEN: TAMP1IEN Position     */
+#define TAMPER_INTEN_TAMP1IEN_Msk        (0x1ul << TAMPER_INTEN_TAMP1IEN_Pos)              /*!< TAMPER_T::INTEN: TAMP1IEN Mask         */
+
+#define TAMPER_INTEN_TAMP2IEN_Pos        (2)                                               /*!< TAMPER_T::INTEN: TAMP2IEN Position     */
+#define TAMPER_INTEN_TAMP2IEN_Msk        (0x1ul << TAMPER_INTEN_TAMP2IEN_Pos)              /*!< TAMPER_T::INTEN: TAMP2IEN Mask         */
+
+#define TAMPER_INTEN_TAMP3IEN_Pos        (3)                                               /*!< TAMPER_T::INTEN: TAMP3IEN Position     */
+#define TAMPER_INTEN_TAMP3IEN_Msk        (0x1ul << TAMPER_INTEN_TAMP3IEN_Pos)              /*!< TAMPER_T::INTEN: TAMP3IEN Mask         */
+
+#define TAMPER_INTEN_TAMP4IEN_Pos        (4)                                               /*!< TAMPER_T::INTEN: TAMP4IEN Position     */
+#define TAMPER_INTEN_TAMP4IEN_Msk        (0x1ul << TAMPER_INTEN_TAMP4IEN_Pos)              /*!< TAMPER_T::INTEN: TAMP4IEN Mask         */
+
+#define TAMPER_INTEN_TAMP5IEN_Pos        (5)                                               /*!< TAMPER_T::INTEN: TAMP5IEN Position     */
+#define TAMPER_INTEN_TAMP5IEN_Msk        (0x1ul << TAMPER_INTEN_TAMP5IEN_Pos)              /*!< TAMPER_T::INTEN: TAMP5IEN Mask         */
+
+#define TAMPER_INTEN_CLKFIEN_Pos         (6)                                               /*!< TAMPER_T::INTEN: CLKFIEN Position      */
+#define TAMPER_INTEN_CLKFIEN_Msk         (0x1ul << TAMPER_INTEN_CLKFIEN_Pos)               /*!< TAMPER_T::INTEN: CLKFIEN Mask          */
+
+#define TAMPER_INTEN_CLKSTOPIEN_Pos      (7)                                               /*!< TAMPER_T::INTEN: CLKSTOPIEN Position   */
+#define TAMPER_INTEN_CLKSTOPIEN_Msk      (0x1ul << TAMPER_INTEN_CLKSTOPIEN_Pos)            /*!< TAMPER_T::INTEN: CLKSTOPIEN Mask       */
+
+#define TAMPER_INTEN_OVPIEN_Pos          (8)                                               /*!< TAMPER_T::INTEN: OVPIEN Position       */
+#define TAMPER_INTEN_OVPIEN_Msk          (0x1ul << TAMPER_INTEN_OVPIEN_Pos)                /*!< TAMPER_T::INTEN: OVPIEN Mask           */
+
+#define TAMPER_INTEN_VGPIEN_Pos          (9)                                               /*!< TAMPER_T::INTEN: VGPIEN Position       */
+#define TAMPER_INTEN_VGPIEN_Msk          (0x1ul << TAMPER_INTEN_VGPIEN_Pos)                /*!< TAMPER_T::INTEN: VGPIEN Mask           */
+
+#define TAMPER_INTEN_VGNIEN_Pos          (10)                                              /*!< TAMPER_T::INTEN: VGNIEN Position       */
+#define TAMPER_INTEN_VGNIEN_Msk          (0x1ul << TAMPER_INTEN_VGNIEN_Pos)                /*!< TAMPER_T::INTEN: VGNIEN Mask           */
+
+#define TAMPER_INTEN_ACTSIEN_Pos         (11)                                              /*!< TAMPER_T::INTEN: ACTSIEN Position      */
+#define TAMPER_INTEN_ACTSIEN_Msk         (0x1ul << TAMPER_INTEN_ACTSIEN_Pos)               /*!< TAMPER_T::INTEN: ACTSIEN Mask          */
+
+#define TAMPER_INTEN_RTCLVRIEN_Pos       (16)                                              /*!< TAMPER_T::INTEN: RTCLVRIEN Position    */
+#define TAMPER_INTEN_RTCLVRIEN_Msk       (0x1ul << TAMPER_INTEN_RTCLVRIEN_Pos)             /*!< TAMPER_T::INTEN: RTCLVRIEN Mask        */
+
+#define TAMPER_INTEN_RTCIOIEN_Pos        (17)                                              /*!< TAMPER_T::INTEN: RTCIOIEN Position     */
+#define TAMPER_INTEN_RTCIOIEN_Msk        (0x1ul << TAMPER_INTEN_RTCIOIEN_Pos)              /*!< TAMPER_T::INTEN: RTCIOIEN Mask         */
+
+#define TAMPER_INTEN_RTCLKIEN_Pos        (18)                                              /*!< TAMPER_T::INTEN: RTCLKIEN Position     */
+#define TAMPER_INTEN_RTCLKIEN_Msk        (0x1ul << TAMPER_INTEN_RTCLKIEN_Pos)              /*!< TAMPER_T::INTEN: RTCLKIEN Mask         */
+
+#define TAMPER_INTEN_BODIEN_Pos          (22)                                              /*!< TAMPER_T::INTEN: BODIEN Position       */
+#define TAMPER_INTEN_BODIEN_Msk          (0x1ul << TAMPER_INTEN_BODIEN_Pos)                /*!< TAMPER_T::INTEN: BODIEN Mask           */
+
+#define TAMPER_INTSTS_TAMP0IF_Pos        (0)                                               /*!< TAMPER_T::INTSTS: TAMP0IF Position     */
+#define TAMPER_INTSTS_TAMP0IF_Msk        (0x1ul << TAMPER_INTSTS_TAMP0IF_Pos)              /*!< TAMPER_T::INTSTS: TAMP0IF Mask         */
+
+#define TAMPER_INTSTS_TAMP1IF_Pos        (1)                                               /*!< TAMPER_T::INTSTS: TAMP1IF Position     */
+#define TAMPER_INTSTS_TAMP1IF_Msk        (0x1ul << TAMPER_INTSTS_TAMP1IF_Pos)              /*!< TAMPER_T::INTSTS: TAMP1IF Mask         */
+
+#define TAMPER_INTSTS_TAMP2IF_Pos        (2)                                               /*!< TAMPER_T::INTSTS: TAMP2IF Position     */
+#define TAMPER_INTSTS_TAMP2IF_Msk        (0x1ul << TAMPER_INTSTS_TAMP2IF_Pos)              /*!< TAMPER_T::INTSTS: TAMP2IF Mask         */
+
+#define TAMPER_INTSTS_TAMP3IF_Pos        (3)                                               /*!< TAMPER_T::INTSTS: TAMP3IF Position     */
+#define TAMPER_INTSTS_TAMP3IF_Msk        (0x1ul << TAMPER_INTSTS_TAMP3IF_Pos)              /*!< TAMPER_T::INTSTS: TAMP3IF Mask         */
+
+#define TAMPER_INTSTS_TAMP4IF_Pos        (4)                                               /*!< TAMPER_T::INTSTS: TAMP4IF Position     */
+#define TAMPER_INTSTS_TAMP4IF_Msk        (0x1ul << TAMPER_INTSTS_TAMP4IF_Pos)              /*!< TAMPER_T::INTSTS: TAMP4IF Mask         */
+
+#define TAMPER_INTSTS_TAMP5IF_Pos        (5)                                               /*!< TAMPER_T::INTSTS: TAMP5IF Position     */
+#define TAMPER_INTSTS_TAMP5IF_Msk        (0x1ul << TAMPER_INTSTS_TAMP5IF_Pos)              /*!< TAMPER_T::INTSTS: TAMP5IF Mask         */
+
+#define TAMPER_INTSTS_CLKFAILIF_Pos      (6)                                               /*!< TAMPER_T::INTSTS: CLKFAILIF Position   */
+#define TAMPER_INTSTS_CLKFAILIF_Msk      (0x1ul << TAMPER_INTSTS_CLKFAILIF_Pos)            /*!< TAMPER_T::INTSTS: CLKFAILIF Mask       */
+
+#define TAMPER_INTSTS_CLKSTOPIF_Pos      (7)                                               /*!< TAMPER_T::INTSTS: CLKSTOPIF Position   */
+#define TAMPER_INTSTS_CLKSTOPIF_Msk      (0x1ul << TAMPER_INTSTS_CLKSTOPIF_Pos)            /*!< TAMPER_T::INTSTS: CLKSTOPIF Mask       */
+
+#define TAMPER_INTSTS_OVPOUTIF_Pos       (8)                                               /*!< TAMPER_T::INTSTS: OVPOUTIF Position    */
+#define TAMPER_INTSTS_OVPOUTIF_Msk       (0x1ul << TAMPER_INTSTS_OVPOUTIF_Pos)             /*!< TAMPER_T::INTSTS: OVPOUTIF Mask        */
+
+#define TAMPER_INTSTS_VGPEVIF_Pos        (9)                                               /*!< TAMPER_T::INTSTS: VGPEVIF Position     */
+#define TAMPER_INTSTS_VGPEVIF_Msk        (0x1ul << TAMPER_INTSTS_VGPEVIF_Pos)              /*!< TAMPER_T::INTSTS: VGPEVIF Mask         */
+
+#define TAMPER_INTSTS_VGNEVIF_Pos        (10)                                              /*!< TAMPER_T::INTSTS: VGNEVIF Position     */
+#define TAMPER_INTSTS_VGNEVIF_Msk        (0x1ul << TAMPER_INTSTS_VGNEVIF_Pos)              /*!< TAMPER_T::INTSTS: VGNEVIF Mask         */
+
+#define TAMPER_INTSTS_ACTSEIF_Pos        (11)                                              /*!< TAMPER_T::INTSTS: ACTSEIF Position     */
+#define TAMPER_INTSTS_ACTSEIF_Msk        (0x1ul << TAMPER_INTSTS_ACTSEIF_Pos)              /*!< TAMPER_T::INTSTS: ACTSEIF Mask         */
+
+#define TAMPER_INTSTS_ACTST5IF_Pos       (13)                                              /*!< TAMPER_T::INTSTS: ACTST5IF Position    */
+#define TAMPER_INTSTS_ACTST5IF_Msk       (0x1ul << TAMPER_INTSTS_ACTST5IF_Pos)             /*!< TAMPER_T::INTSTS: ACTST5IF Mask        */
+
+#define TAMPER_INTSTS_ACTST25IF_Pos      (15)                                              /*!< TAMPER_T::INTSTS: ACTST25IF Position   */
+#define TAMPER_INTSTS_ACTST25IF_Msk      (0x1ul << TAMPER_INTSTS_ACTST25IF_Pos)            /*!< TAMPER_T::INTSTS: ACTST25IF Mask       */
+
+#define TAMPER_INTSTS_RTCLVRIF_Pos       (16)                                              /*!< TAMPER_T::INTSTS: RTCLVRIF Position    */
+#define TAMPER_INTSTS_RTCLVRIF_Msk       (0x1ul << TAMPER_INTSTS_RTCLVRIF_Pos)             /*!< TAMPER_T::INTSTS: RTCLVRIF Mask        */
+
+#define TAMPER_INTSTS_RIOTRIGIF_Pos      (17)                                              /*!< TAMPER_T::INTSTS: RIOTRIGIF Position   */
+#define TAMPER_INTSTS_RIOTRIGIF_Msk      (0x1ul << TAMPER_INTSTS_RIOTRIGIF_Pos)            /*!< TAMPER_T::INTSTS: RIOTRIGIF Mask       */
+
+#define TAMPER_INTSTS_RCLKTRIGIF_Pos     (18)                                              /*!< TAMPER_T::INTSTS: RCLKTRIGIF Position  */
+#define TAMPER_INTSTS_RCLKTRIGIF_Msk     (0x1ul << TAMPER_INTSTS_RCLKTRIGIF_Pos)           /*!< TAMPER_T::INTSTS: RCLKTRIGIF Mask      */
+
+#define TAMPER_INTSTS_BODIF_Pos          (22)                                              /*!< TAMPER_T::INTSTS: BODIF Position       */
+#define TAMPER_INTSTS_BODIF_Msk          (0x1ul << TAMPER_INTSTS_BODIF_Pos)                /*!< TAMPER_T::INTSTS: BODIF Mask           */
+
+#define TAMPER_INTSTS_ACTST1IF_Pos       (25)                                              /*!< TAMPER_T::INTSTS: ACTST1IF Position    */
+#define TAMPER_INTSTS_ACTST1IF_Msk       (0x1ul << TAMPER_INTSTS_ACTST1IF_Pos)             /*!< TAMPER_T::INTSTS: ACTST1IF Mask        */
+
+#define TAMPER_INTSTS_ACTST3IF_Pos       (27)                                              /*!< TAMPER_T::INTSTS: ACTST3IF Position    */
+#define TAMPER_INTSTS_ACTST3IF_Msk       (0x1ul << TAMPER_INTSTS_ACTST3IF_Pos)             /*!< TAMPER_T::INTSTS: ACTST3IF Mask        */
+
+#define TAMPER_INTSTS_ACTST21IF_Pos      (29)                                              /*!< TAMPER_T::INTSTS: ACTST21IF Position   */
+#define TAMPER_INTSTS_ACTST21IF_Msk      (0x1ul << TAMPER_INTSTS_ACTST21IF_Pos)            /*!< TAMPER_T::INTSTS: ACTST21IF Mask       */
+
+#define TAMPER_INTSTS_ACTST23IF_Pos      (31)                                              /*!< TAMPER_T::INTSTS: ACTST23IF Position   */
+#define TAMPER_INTSTS_ACTST23IF_Msk      (0x1ul << TAMPER_INTSTS_ACTST23IF_Pos)            /*!< TAMPER_T::INTSTS: ACTST23IF Mask       */
+
+#define TAMPER_LIRCTL_TLRCTRIM_Pos       (0)                                               /*!< TAMPER_T::LIRCTL: TLRCTRIM Position    */
+#define TAMPER_LIRCTL_TLRCTRIM_Msk       (0x1fful << TAMPER_LIRCTL_TLRCTRIM_Pos)           /*!< TAMPER_T::LIRCTL: TLRCTRIM Mask        */
+
+#define TAMPER_LIRCTL_TRIMMOS_Pos        (9)                                               /*!< TAMPER_T::LIRCTL: TRIMMOS Position     */
+#define TAMPER_LIRCTL_TRIMMOS_Msk        (0x3ul << TAMPER_LIRCTL_TRIMMOS_Pos)              /*!< TAMPER_T::LIRCTL: TRIMMOS Mask         */
+
+#define TAMPER_TIOCTL_DYN1ISS_Pos        (0)                                               /*!< TAMPER_T::TIOCTL: DYN1ISS Position     */
+#define TAMPER_TIOCTL_DYN1ISS_Msk        (0x1ul << TAMPER_TIOCTL_DYN1ISS_Pos)              /*!< TAMPER_T::TIOCTL: DYN1ISS Mask         */
+
+#define TAMPER_TIOCTL_DYN2ISS_Pos        (1)                                               /*!< TAMPER_T::TIOCTL: DYN2ISS Position     */
+#define TAMPER_TIOCTL_DYN2ISS_Msk        (0x1ul << TAMPER_TIOCTL_DYN2ISS_Pos)              /*!< TAMPER_T::TIOCTL: DYN2ISS Mask         */
+
+#define TAMPER_TIOCTL_DYNSRC_Pos         (3)                                               /*!< TAMPER_T::TIOCTL: DYNSRC Position      */
+#define TAMPER_TIOCTL_DYNSRC_Msk         (0x1ul << TAMPER_TIOCTL_DYNSRC_Pos)               /*!< TAMPER_T::TIOCTL: DYNSRC Mask          */
+
+#define TAMPER_TIOCTL_SEEDRLD_Pos        (4)                                               /*!< TAMPER_T::TIOCTL: SEEDRLD Position     */
+#define TAMPER_TIOCTL_SEEDRLD_Msk        (0x1ul << TAMPER_TIOCTL_SEEDRLD_Pos)              /*!< TAMPER_T::TIOCTL: SEEDRLD Mask         */
+
+#define TAMPER_TIOCTL_DYNRATE_Pos        (5)                                               /*!< TAMPER_T::TIOCTL: DYNRATE Position     */
+#define TAMPER_TIOCTL_DYNRATE_Msk        (0x7ul << TAMPER_TIOCTL_DYNRATE_Pos)              /*!< TAMPER_T::TIOCTL: DYNRATE Mask         */
+
+#define TAMPER_TIOCTL_TAMP0EN_Pos        (8)                                               /*!< TAMPER_T::TIOCTL: TAMP0EN Position     */
+#define TAMPER_TIOCTL_TAMP0EN_Msk        (0x1ul << TAMPER_TIOCTL_TAMP0EN_Pos)              /*!< TAMPER_T::TIOCTL: TAMP0EN Mask         */
+
+#define TAMPER_TIOCTL_TAMP0LV_Pos        (9)                                               /*!< TAMPER_T::TIOCTL: TAMP0LV Position     */
+#define TAMPER_TIOCTL_TAMP0LV_Msk        (0x1ul << TAMPER_TIOCTL_TAMP0LV_Pos)              /*!< TAMPER_T::TIOCTL: TAMP0LV Mask         */
+
+#define TAMPER_TIOCTL_TAMP0DBEN_Pos      (10)                                              /*!< TAMPER_T::TIOCTL: TAMP0DBEN Position   */
+#define TAMPER_TIOCTL_TAMP0DBEN_Msk      (0x1ul << TAMPER_TIOCTL_TAMP0DBEN_Pos)            /*!< TAMPER_T::TIOCTL: TAMP0DBEN Mask       */
+
+#define TAMPER_TIOCTL_TAMP1EN_Pos        (12)                                              /*!< TAMPER_T::TIOCTL: TAMP1EN Position     */
+#define TAMPER_TIOCTL_TAMP1EN_Msk        (0x1ul << TAMPER_TIOCTL_TAMP1EN_Pos)              /*!< TAMPER_T::TIOCTL: TAMP1EN Mask         */
+
+#define TAMPER_TIOCTL_TAMP1LV_Pos        (13)                                              /*!< TAMPER_T::TIOCTL: TAMP1LV Position     */
+#define TAMPER_TIOCTL_TAMP1LV_Msk        (0x1ul << TAMPER_TIOCTL_TAMP1LV_Pos)              /*!< TAMPER_T::TIOCTL: TAMP1LV Mask         */
+
+#define TAMPER_TIOCTL_TAMP1DBEN_Pos      (14)                                              /*!< TAMPER_T::TIOCTL: TAMP1DBEN Position   */
+#define TAMPER_TIOCTL_TAMP1DBEN_Msk      (0x1ul << TAMPER_TIOCTL_TAMP1DBEN_Pos)            /*!< TAMPER_T::TIOCTL: TAMP1DBEN Mask       */
+
+#define TAMPER_TIOCTL_DYNPR0EN_Pos       (15)                                              /*!< TAMPER_T::TIOCTL: DYNPR0EN Position    */
+#define TAMPER_TIOCTL_DYNPR0EN_Msk       (0x1ul << TAMPER_TIOCTL_DYNPR0EN_Pos)             /*!< TAMPER_T::TIOCTL: DYNPR0EN Mask        */
+
+#define TAMPER_TIOCTL_TAMP2EN_Pos        (16)                                              /*!< TAMPER_T::TIOCTL: TAMP2EN Position     */
+#define TAMPER_TIOCTL_TAMP2EN_Msk        (0x1ul << TAMPER_TIOCTL_TAMP2EN_Pos)              /*!< TAMPER_T::TIOCTL: TAMP2EN Mask         */
+
+#define TAMPER_TIOCTL_TAMP2LV_Pos        (17)                                              /*!< TAMPER_T::TIOCTL: TAMP2LV Position     */
+#define TAMPER_TIOCTL_TAMP2LV_Msk        (0x1ul << TAMPER_TIOCTL_TAMP2LV_Pos)              /*!< TAMPER_T::TIOCTL: TAMP2LV Mask         */
+
+#define TAMPER_TIOCTL_TAMP2DBEN_Pos      (18)                                              /*!< TAMPER_T::TIOCTL: TAMP2DBEN Position   */
+#define TAMPER_TIOCTL_TAMP2DBEN_Msk      (0x1ul << TAMPER_TIOCTL_TAMP2DBEN_Pos)            /*!< TAMPER_T::TIOCTL: TAMP2DBEN Mask       */
+
+#define TAMPER_TIOCTL_TAMP3EN_Pos        (20)                                              /*!< TAMPER_T::TIOCTL: TAMP3EN Position     */
+#define TAMPER_TIOCTL_TAMP3EN_Msk        (0x1ul << TAMPER_TIOCTL_TAMP3EN_Pos)              /*!< TAMPER_T::TIOCTL: TAMP3EN Mask         */
+
+#define TAMPER_TIOCTL_TAMP3LV_Pos        (21)                                              /*!< TAMPER_T::TIOCTL: TAMP3LV Position     */
+#define TAMPER_TIOCTL_TAMP3LV_Msk        (0x1ul << TAMPER_TIOCTL_TAMP3LV_Pos)              /*!< TAMPER_T::TIOCTL: TAMP3LV Mask         */
+
+#define TAMPER_TIOCTL_TAMP3DBEN_Pos      (22)                                              /*!< TAMPER_T::TIOCTL: TAMP3DBEN Position   */
+#define TAMPER_TIOCTL_TAMP3DBEN_Msk      (0x1ul << TAMPER_TIOCTL_TAMP3DBEN_Pos)            /*!< TAMPER_T::TIOCTL: TAMP3DBEN Mask       */
+
+#define TAMPER_TIOCTL_DYNPR1EN_Pos       (23)                                              /*!< TAMPER_T::TIOCTL: DYNPR1EN Position    */
+#define TAMPER_TIOCTL_DYNPR1EN_Msk       (0x1ul << TAMPER_TIOCTL_DYNPR1EN_Pos)             /*!< TAMPER_T::TIOCTL: DYNPR1EN Mask        */
+
+#define TAMPER_TIOCTL_TAMP4EN_Pos        (24)                                              /*!< TAMPER_T::TIOCTL: TAMP4EN Position     */
+#define TAMPER_TIOCTL_TAMP4EN_Msk        (0x1ul << TAMPER_TIOCTL_TAMP4EN_Pos)              /*!< TAMPER_T::TIOCTL: TAMP4EN Mask         */
+
+#define TAMPER_TIOCTL_TAMP4LV_Pos        (25)                                              /*!< TAMPER_T::TIOCTL: TAMP4LV Position     */
+#define TAMPER_TIOCTL_TAMP4LV_Msk        (0x1ul << TAMPER_TIOCTL_TAMP4LV_Pos)              /*!< TAMPER_T::TIOCTL: TAMP4LV Mask         */
+
+#define TAMPER_TIOCTL_TAMP4DBEN_Pos      (26)                                              /*!< TAMPER_T::TIOCTL: TAMP4DBEN Position   */
+#define TAMPER_TIOCTL_TAMP4DBEN_Msk      (0x1ul << TAMPER_TIOCTL_TAMP4DBEN_Pos)            /*!< TAMPER_T::TIOCTL: TAMP4DBEN Mask       */
+
+#define TAMPER_TIOCTL_TAMP5EN_Pos        (28)                                              /*!< TAMPER_T::TIOCTL: TAMP5EN Position     */
+#define TAMPER_TIOCTL_TAMP5EN_Msk        (0x1ul << TAMPER_TIOCTL_TAMP5EN_Pos)              /*!< TAMPER_T::TIOCTL: TAMP5EN Mask         */
+
+#define TAMPER_TIOCTL_TAMP5LV_Pos        (29)                                              /*!< TAMPER_T::TIOCTL: TAMP5LV Position     */
+#define TAMPER_TIOCTL_TAMP5LV_Msk        (0x1ul << TAMPER_TIOCTL_TAMP5LV_Pos)              /*!< TAMPER_T::TIOCTL: TAMP5LV Mask         */
+
+#define TAMPER_TIOCTL_TAMP5DBEN_Pos      (30)                                              /*!< TAMPER_T::TIOCTL: TAMP5DBEN Position   */
+#define TAMPER_TIOCTL_TAMP5DBEN_Msk      (0x1ul << TAMPER_TIOCTL_TAMP5DBEN_Pos)            /*!< TAMPER_T::TIOCTL: TAMP5DBEN Mask       */
+
+#define TAMPER_TIOCTL_DYNPR2EN_Pos       (31)                                              /*!< TAMPER_T::TIOCTL: DYNPR2EN Position    */
+#define TAMPER_TIOCTL_DYNPR2EN_Msk       (0x1ul << TAMPER_TIOCTL_DYNPR2EN_Pos)             /*!< TAMPER_T::TIOCTL: DYNPR2EN Mask        */
+
+#define TAMPER_SEED_SEED_Pos             (0)                                               /*!< TAMPER_T::SEED: SEED Position          */
+#define TAMPER_SEED_SEED_Msk             (0xfffffffful << TAMPER_SEED_SEED_Pos)            /*!< TAMPER_T::SEED: SEED Mask              */
+
+#define TAMPER_SEED2_SEED2_Pos           (0)                                               /*!< TAMPER_T::SEED2: SEED2 Position        */
+#define TAMPER_SEED2_SEED2_Msk           (0xfffffffful << TAMPER_SEED2_SEED2_Pos)          /*!< TAMPER_T::SEED2: SEED2 Mask            */
+
+#define TAMPER_ACTSTIOCTL1_ADYN1ISS_Pos  (0)                                               /*!< TAMPER_T::ACTSTIOCTL1: ADYN1ISS Position*/
+#define TAMPER_ACTSTIOCTL1_ADYN1ISS_Msk  (0x1ul << TAMPER_ACTSTIOCTL1_ADYN1ISS_Pos)        /*!< TAMPER_T::ACTSTIOCTL1: ADYN1ISS Mask   */
+
+#define TAMPER_ACTSTIOCTL1_ADYNSRC_Pos   (3)                                               /*!< TAMPER_T::ACTSTIOCTL1: ADYNSRC Position*/
+#define TAMPER_ACTSTIOCTL1_ADYNSRC_Msk   (0x1ul << TAMPER_ACTSTIOCTL1_ADYNSRC_Pos)         /*!< TAMPER_T::ACTSTIOCTL1: ADYNSRC Mask    */
+
+#define TAMPER_ACTSTIOCTL1_ADYNRATE_Pos  (5)                                               /*!< TAMPER_T::ACTSTIOCTL1: ADYNRATE Position*/
+#define TAMPER_ACTSTIOCTL1_ADYNRATE_Msk  (0x7ul << TAMPER_ACTSTIOCTL1_ADYNRATE_Pos)        /*!< TAMPER_T::ACTSTIOCTL1: ADYNRATE Mask   */
+
+#define TAMPER_ACTSTIOCTL1_ATAMP0EN_Pos  (8)                                               /*!< TAMPER_T::ACTSTIOCTL1: ATAMP0EN Position*/
+#define TAMPER_ACTSTIOCTL1_ATAMP0EN_Msk  (0x1ul << TAMPER_ACTSTIOCTL1_ATAMP0EN_Pos)        /*!< TAMPER_T::ACTSTIOCTL1: ATAMP0EN Mask   */
+
+#define TAMPER_ACTSTIOCTL1_ATAMP1EN_Pos  (12)                                              /*!< TAMPER_T::ACTSTIOCTL1: ATAMP1EN Position*/
+#define TAMPER_ACTSTIOCTL1_ATAMP1EN_Msk  (0x1ul << TAMPER_ACTSTIOCTL1_ATAMP1EN_Pos)        /*!< TAMPER_T::ACTSTIOCTL1: ATAMP1EN Mask   */
+
+#define TAMPER_ACTSTIOCTL1_ADYNPR0EN_Pos (15)                                              /*!< TAMPER_T::ACTSTIOCTL1: ADYNPR0EN Position*/
+#define TAMPER_ACTSTIOCTL1_ADYNPR0EN_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ADYNPR0EN_Pos)       /*!< TAMPER_T::ACTSTIOCTL1: ADYNPR0EN Mask  */
+
+#define TAMPER_ACTSTIOCTL1_ATAMP2EN_Pos  (16)                                              /*!< TAMPER_T::ACTSTIOCTL1: ATAMP2EN Position*/
+#define TAMPER_ACTSTIOCTL1_ATAMP2EN_Msk  (0x1ul << TAMPER_ACTSTIOCTL1_ATAMP2EN_Pos)        /*!< TAMPER_T::ACTSTIOCTL1: ATAMP2EN Mask   */
+
+#define TAMPER_ACTSTIOCTL1_ATAMP3EN_Pos  (20)                                              /*!< TAMPER_T::ACTSTIOCTL1: ATAMP3EN Position*/
+#define TAMPER_ACTSTIOCTL1_ATAMP3EN_Msk  (0x1ul << TAMPER_ACTSTIOCTL1_ATAMP3EN_Pos)        /*!< TAMPER_T::ACTSTIOCTL1: ATAMP3EN Mask   */
+
+#define TAMPER_ACTSTIOCTL1_ADYNPR1EN_Pos (23)                                              /*!< TAMPER_T::ACTSTIOCTL1: ADYNPR1EN Position*/
+#define TAMPER_ACTSTIOCTL1_ADYNPR1EN_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ADYNPR1EN_Pos)       /*!< TAMPER_T::ACTSTIOCTL1: ADYNPR1EN Mask  */
+
+#define TAMPER_ACTSTIOCTL1_ATAMP4EN_Pos  (24)                                              /*!< TAMPER_T::ACTSTIOCTL1: ATAMP4EN Position*/
+#define TAMPER_ACTSTIOCTL1_ATAMP4EN_Msk  (0x1ul << TAMPER_ACTSTIOCTL1_ATAMP4EN_Pos)        /*!< TAMPER_T::ACTSTIOCTL1: ATAMP4EN Mask   */
+
+#define TAMPER_ACTSTIOCTL1_ATAMP5EN_Pos  (28)                                              /*!< TAMPER_T::ACTSTIOCTL1: ATAMP5EN Position*/
+#define TAMPER_ACTSTIOCTL1_ATAMP5EN_Msk  (0x1ul << TAMPER_ACTSTIOCTL1_ATAMP5EN_Pos)        /*!< TAMPER_T::ACTSTIOCTL1: ATAMP5EN Mask   */
+
+#define TAMPER_ACTSTIOCTL1_ADYNPR2EN_Pos (31)                                              /*!< TAMPER_T::ACTSTIOCTL1: ADYNPR2EN Position*/
+#define TAMPER_ACTSTIOCTL1_ADYNPR2EN_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ADYNPR2EN_Pos)       /*!< TAMPER_T::ACTSTIOCTL1: ADYNPR2EN Mask  */
+
+#define TAMPER_ACTSTIOCTL2_ADYN1ISS2_Pos (0)                                               /*!< TAMPER_T::ACTSTIOCTL2: ADYN1ISS2 Position*/
+#define TAMPER_ACTSTIOCTL2_ADYN1ISS2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ADYN1ISS2_Pos)       /*!< TAMPER_T::ACTSTIOCTL2: ADYN1ISS2 Mask  */
+
+#define TAMPER_ACTSTIOCTL2_ADYNSRC2_Pos  (3)                                               /*!< TAMPER_T::ACTSTIOCTL2: ADYNSRC2 Position*/
+#define TAMPER_ACTSTIOCTL2_ADYNSRC2_Msk  (0x1ul << TAMPER_ACTSTIOCTL2_ADYNSRC2_Pos)        /*!< TAMPER_T::ACTSTIOCTL2: ADYNSRC2 Mask   */
+
+#define TAMPER_ACTSTIOCTL2_SEEDRLD2_Pos  (4)                                               /*!< TAMPER_T::ACTSTIOCTL2: SEEDRLD2 Position*/
+#define TAMPER_ACTSTIOCTL2_SEEDRLD2_Msk  (0x1ul << TAMPER_ACTSTIOCTL2_SEEDRLD2_Pos)        /*!< TAMPER_T::ACTSTIOCTL2: SEEDRLD2 Mask   */
+
+#define TAMPER_ACTSTIOCTL2_ADYNRATE2_Pos (5)                                               /*!< TAMPER_T::ACTSTIOCTL2: ADYNRATE2 Position*/
+#define TAMPER_ACTSTIOCTL2_ADYNRATE2_Msk (0x7ul << TAMPER_ACTSTIOCTL2_ADYNRATE2_Pos)       /*!< TAMPER_T::ACTSTIOCTL2: ADYNRATE2 Mask  */
+
+#define TAMPER_ACTSTIOCTL2_ATAMP0EN2_Pos (8)                                               /*!< TAMPER_T::ACTSTIOCTL2: ATAMP0EN2 Position*/
+#define TAMPER_ACTSTIOCTL2_ATAMP0EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ATAMP0EN2_Pos)       /*!< TAMPER_T::ACTSTIOCTL2: ATAMP0EN2 Mask  */
+
+#define TAMPER_ACTSTIOCTL2_ATAMP1EN2_Pos (12)                                              /*!< TAMPER_T::ACTSTIOCTL2: ATAMP1EN2 Position*/
+#define TAMPER_ACTSTIOCTL2_ATAMP1EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ATAMP1EN2_Pos)       /*!< TAMPER_T::ACTSTIOCTL2: ATAMP1EN2 Mask  */
+
+#define TAMPER_ACTSTIOCTL2_ADYNPR0EN2_Pos (15)                                             /*!< TAMPER_T::ACTSTIOCTL2: ADYNPR0EN2 Position*/
+#define TAMPER_ACTSTIOCTL2_ADYNPR0EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ADYNPR0EN2_Pos)     /*!< TAMPER_T::ACTSTIOCTL2: ADYNPR0EN2 Mask */
+
+#define TAMPER_ACTSTIOCTL2_ATAMP2EN2_Pos (16)                                              /*!< TAMPER_T::ACTSTIOCTL2: ATAMP2EN2 Position*/
+#define TAMPER_ACTSTIOCTL2_ATAMP2EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ATAMP2EN2_Pos)       /*!< TAMPER_T::ACTSTIOCTL2: ATAMP2EN2 Mask  */
+
+#define TAMPER_ACTSTIOCTL2_ATAMP3EN2_Pos (20)                                              /*!< TAMPER_T::ACTSTIOCTL2: ATAMP3EN2 Position*/
+#define TAMPER_ACTSTIOCTL2_ATAMP3EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ATAMP3EN2_Pos)       /*!< TAMPER_T::ACTSTIOCTL2: ATAMP3EN2 Mask  */
+
+#define TAMPER_ACTSTIOCTL2_ADYNPR1EN2_Pos (23)                                             /*!< TAMPER_T::ACTSTIOCTL2: ADYNPR1EN2 Position*/
+#define TAMPER_ACTSTIOCTL2_ADYNPR1EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ADYNPR1EN2_Pos)     /*!< TAMPER_T::ACTSTIOCTL2: ADYNPR1EN2 Mask */
+
+#define TAMPER_ACTSTIOCTL2_ATAMP4EN2_Pos (24)                                              /*!< TAMPER_T::ACTSTIOCTL2: ATAMP4EN2 Position*/
+#define TAMPER_ACTSTIOCTL2_ATAMP4EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ATAMP4EN2_Pos)       /*!< TAMPER_T::ACTSTIOCTL2: ATAMP4EN2 Mask  */
+
+#define TAMPER_ACTSTIOCTL2_ATAMP5EN2_Pos (28)                                              /*!< TAMPER_T::ACTSTIOCTL2: ATAMP5EN2 Position*/
+#define TAMPER_ACTSTIOCTL2_ATAMP5EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ATAMP5EN2_Pos)       /*!< TAMPER_T::ACTSTIOCTL2: ATAMP5EN2 Mask  */
+
+#define TAMPER_ACTSTIOCTL2_ADYNPR2EN2_Pos (31)                                             /*!< TAMPER_T::ACTSTIOCTL2: ADYNPR2EN2 Position*/
+#define TAMPER_ACTSTIOCTL2_ADYNPR2EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ADYNPR2EN2_Pos)     /*!< TAMPER_T::ACTSTIOCTL2: ADYNPR2EN2 Mask */
+
+#define TAMPER_CDBR_STOPBD_Pos           (0)                                               /*!< TAMPER_T::CDBR: STOPBD Position        */
+#define TAMPER_CDBR_STOPBD_Msk           (0xfful << TAMPER_CDBR_STOPBD_Pos)                /*!< TAMPER_T::CDBR: STOPBD Mask            */
+
+#define TAMPER_CDBR_FAILBD_Pos           (16)                                              /*!< TAMPER_T::CDBR: FAILBD Position        */
+#define TAMPER_CDBR_FAILBD_Msk           (0xfful << TAMPER_CDBR_FAILBD_Pos)                /*!< TAMPER_T::CDBR: FAILBD Mask            */
+
+#define TAMPER_VG_PCLKSEL0_Pos           (0)                                               /*!< TAMPER_T::VG: PCLKSEL0 Position        */
+#define TAMPER_VG_PCLKSEL0_Msk           (0xful << TAMPER_VG_PCLKSEL0_Pos)                 /*!< TAMPER_T::VG: PCLKSEL0 Mask            */
+
+#define TAMPER_VG_NCLKSEL0_Pos           (4)                                               /*!< TAMPER_T::VG: NCLKSEL0 Position        */
+#define TAMPER_VG_NCLKSEL0_Msk           (0xful << TAMPER_VG_NCLKSEL0_Pos)                 /*!< TAMPER_T::VG: NCLKSEL0 Mask            */
+
+#define TAMPER_VG_PDATSEL0_Pos           (8)                                               /*!< TAMPER_T::VG: PDATSEL0 Position        */
+#define TAMPER_VG_PDATSEL0_Msk           (0xful << TAMPER_VG_PDATSEL0_Pos)                 /*!< TAMPER_T::VG: PDATSEL0 Mask            */
+
+#define TAMPER_VG_NDATSEL0_Pos           (12)                                              /*!< TAMPER_T::VG: NDATSEL0 Position        */
+#define TAMPER_VG_NDATSEL0_Msk           (0xful << TAMPER_VG_NDATSEL0_Pos)                 /*!< TAMPER_T::VG: NDATSEL0 Mask            */
+
+#define TAMPER_VG_PCLKSEL1_Pos           (16)                                              /*!< TAMPER_T::VG: PCLKSEL1 Position        */
+#define TAMPER_VG_PCLKSEL1_Msk           (0xful << TAMPER_VG_PCLKSEL1_Pos)                 /*!< TAMPER_T::VG: PCLKSEL1 Mask            */
+
+#define TAMPER_VG_NCLKSEL1_Pos           (20)                                              /*!< TAMPER_T::VG: NCLKSEL1 Position        */
+#define TAMPER_VG_NCLKSEL1_Msk           (0xful << TAMPER_VG_NCLKSEL1_Pos)                 /*!< TAMPER_T::VG: NCLKSEL1 Mask            */
+
+#define TAMPER_VG_PDATSEL1_Pos           (24)                                              /*!< TAMPER_T::VG: PDATSEL1 Position        */
+#define TAMPER_VG_PDATSEL1_Msk           (0xful << TAMPER_VG_PDATSEL1_Pos)                 /*!< TAMPER_T::VG: PDATSEL1 Mask            */
+
+#define TAMPER_VG_NDATSEL1_Pos           (28)                                              /*!< TAMPER_T::VG: NDATSEL1 Position        */
+#define TAMPER_VG_NDATSEL1_Msk           (0xful << TAMPER_VG_NDATSEL1_Pos)                 /*!< TAMPER_T::VG: NDATSEL1 Mask            */
+
+#define TAMPER_VGEV_VGECNTP_Pos          (0)                                               /*!< TAMPER_T::VGEV: VGECNTP Position       */
+#define TAMPER_VGEV_VGECNTP_Msk          (0xfful << TAMPER_VGEV_VGECNTP_Pos)               /*!< TAMPER_T::VGEV: VGECNTP Mask           */
+
+#define TAMPER_VGEV_VGECNTN_Pos          (8)                                               /*!< TAMPER_T::VGEV: VGECNTN Position       */
+#define TAMPER_VGEV_VGECNTN_Msk          (0xfful << TAMPER_VGEV_VGECNTN_Pos)               /*!< TAMPER_T::VGEV: VGECNTN Mask           */
+
+#define TAMPER_LDOTRIM_TLDOTRIM_Pos      (0)                                               /*!< TAMPER_T::LDOTRIM: TLDOTRIM Position   */
+#define TAMPER_LDOTRIM_TLDOTRIM_Msk      (0xful << TAMPER_LDOTRIM_TLDOTRIM_Pos)            /*!< TAMPER_T::LDOTRIM: TLDOTRIM Mask       */
+
+#define TAMPER_LDOTRIM_TLDOIQSEL_Pos     (8)                                               /*!< TAMPER_T::LDOTRIM: TLDOIQSEL Position  */
+#define TAMPER_LDOTRIM_TLDOIQSEL_Msk     (0x3ul << TAMPER_LDOTRIM_TLDOIQSEL_Pos)           /*!< TAMPER_T::LDOTRIM: TLDOIQSEL Mask      */
+
+#define TAMPER_LBSTRIM_TLVDSEL_Pos       (0)                                               /*!< TAMPER_T::LBSTRIM: TLVDSEL Position    */
+#define TAMPER_LBSTRIM_TLVDSEL_Msk       (0x7ul << TAMPER_LBSTRIM_TLVDSEL_Pos)             /*!< TAMPER_T::LBSTRIM: TLVDSEL Mask        */
+
+#define TAMPER_LBSTRIM_TOVDSEL_Pos       (4)                                               /*!< TAMPER_T::LBSTRIM: TOVDSEL Position    */
+#define TAMPER_LBSTRIM_TOVDSEL_Msk       (0x1ul << TAMPER_LBSTRIM_TOVDSEL_Pos)             /*!< TAMPER_T::LBSTRIM: TOVDSEL Mask        */
+
+#define TAMPER_LBSTRIM_BSCMPLV_Pos       (8)                                               /*!< TAMPER_T::LBSTRIM: BSCMPLV Position    */
+#define TAMPER_LBSTRIM_BSCMPLV_Msk       (0x3ul << TAMPER_LBSTRIM_BSCMPLV_Pos)             /*!< TAMPER_T::LBSTRIM: BSCMPLV Mask        */
+
+#define TAMPER_LBSTRIM_BSCMPOV_Pos       (10)                                              /*!< TAMPER_T::LBSTRIM: BSCMPOV Position    */
+#define TAMPER_LBSTRIM_BSCMPOV_Msk       (0x3ul << TAMPER_LBSTRIM_BSCMPOV_Pos)             /*!< TAMPER_T::LBSTRIM: BSCMPOV Mask        */
+
+#define TAMPER_LBSTRIM_HYSCMPLV_Pos      (12)                                              /*!< TAMPER_T::LBSTRIM: HYSCMPLV Position   */
+#define TAMPER_LBSTRIM_HYSCMPLV_Msk      (0x3ul << TAMPER_LBSTRIM_HYSCMPLV_Pos)            /*!< TAMPER_T::LBSTRIM: HYSCMPLV Mask       */
+
+#define TAMPER_LBSTRIM_HYSCMPOV_Pos      (14)                                              /*!< TAMPER_T::LBSTRIM: HYSCMPOV Position   */
+#define TAMPER_LBSTRIM_HYSCMPOV_Msk      (0x3ul << TAMPER_LBSTRIM_HYSCMPOV_Pos)            /*!< TAMPER_T::LBSTRIM: HYSCMPOV Mask       */
+
+#define TAMPER_VG2_PCLKSEL2_Pos          (0)                                               /*!< TAMPER_T::VG2: PCLKSEL2 Position       */
+#define TAMPER_VG2_PCLKSEL2_Msk          (0xful << TAMPER_VG2_PCLKSEL2_Pos)                /*!< TAMPER_T::VG2: PCLKSEL2 Mask           */
+
+#define TAMPER_VG2_NCLKSEL2_Pos          (4)                                               /*!< TAMPER_T::VG2: NCLKSEL2 Position       */
+#define TAMPER_VG2_NCLKSEL2_Msk          (0xful << TAMPER_VG2_NCLKSEL2_Pos)                /*!< TAMPER_T::VG2: NCLKSEL2 Mask           */
+
+#define TAMPER_VG2_PDATSEL2_Pos          (8)                                               /*!< TAMPER_T::VG2: PDATSEL2 Position       */
+#define TAMPER_VG2_PDATSEL2_Msk          (0xful << TAMPER_VG2_PDATSEL2_Pos)                /*!< TAMPER_T::VG2: PDATSEL2 Mask           */
+
+#define TAMPER_VG2_NDATSEL2_Pos          (12)                                              /*!< TAMPER_T::VG2: NDATSEL2 Position       */
+#define TAMPER_VG2_NDATSEL2_Msk          (0xful << TAMPER_VG2_NDATSEL2_Pos)                /*!< TAMPER_T::VG2: NDATSEL2 Mask           */
+
+#define TAMPER_VG2_PCLKSEL3_Pos          (16)                                              /*!< TAMPER_T::VG2: PCLKSEL3 Position       */
+#define TAMPER_VG2_PCLKSEL3_Msk          (0xful << TAMPER_VG2_PCLKSEL3_Pos)                /*!< TAMPER_T::VG2: PCLKSEL3 Mask           */
+
+#define TAMPER_VG2_NCLKSEL3_Pos          (20)                                              /*!< TAMPER_T::VG2: NCLKSEL3 Position       */
+#define TAMPER_VG2_NCLKSEL3_Msk          (0xful << TAMPER_VG2_NCLKSEL3_Pos)                /*!< TAMPER_T::VG2: NCLKSEL3 Mask           */
+
+#define TAMPER_VG2_PDATSEL3_Pos          (24)                                              /*!< TAMPER_T::VG2: PDATSEL3 Position       */
+#define TAMPER_VG2_PDATSEL3_Msk          (0xful << TAMPER_VG2_PDATSEL3_Pos)                /*!< TAMPER_T::VG2: PDATSEL3 Mask           */
+
+#define TAMPER_VG2_NDATSEL3_Pos          (28)                                              /*!< TAMPER_T::VG2: NDATSEL3 Position       */
+#define TAMPER_VG2_NDATSEL3_Msk          (0xful << TAMPER_VG2_NDATSEL3_Pos)                /*!< TAMPER_T::VG2: NDATSEL3 Mask           */
+
+/**@}*/ /* TAMPER_CONST */
+/**@}*/ /* end of TAMPER register group */
+/**@}*/ /* end of REGISTER group */
+
+#endif /* __TAMPER_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/timer_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/timer_reg.h
new file mode 100644
index 0000000000..39cf4fa450
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/timer_reg.h
@@ -0,0 +1,1168 @@
+/**************************************************************************//**
+ * @file     timer_reg.h
+ * @version  V1.00
+ * @brief    TIMER register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __TIMER_REG_H__
+#define __TIMER_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+/*---------------------- Timer Controller -------------------------*/
+/**
+    @addtogroup TIMER Timer Controller(TIMER)
+    Memory Mapped Structure for TIMER Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var TIMER_T::CTL
+     * Offset: 0x00  Timer Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |PSC       |Prescale Counter
+     * |        |          |Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter
+     * |        |          |If this field is 0 (PSC = 0), then there is no scaling.
+     * |        |          |Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value.
+     * |[15]    |FUNCSEL   |Function Selection
+     * |        |          |This bit sets the operation mode of Timer4 and Timer5 to PWM function.
+     * |        |          |0 = Timer controller is used as timer function.
+     * |        |          |1 = Timer controller is used as PWM function.
+     * |        |          |Note:  The Timer0 ~ Timer3 function selection is controlled in TIMERx_ALTCTL[0], x= 0~3.
+     * |[19]    |INTRGEN   |Inter-timer Trigger Mode Enable Control
+     * |        |          |Setting this bit will enable the inter-timer trigger capture function.
+     * |        |          |The Timer0/2/4 will be in event counter mode and counting with external clock source or event
+     * |        |          |Also, Timer1/3/5 will be in trigger-counting mode of capture function.
+     * |        |          |0 = Inter-Timer Trigger Capture mode Disabled.
+     * |        |          |1 = Inter-Timer Trigger Capture mode Enabled.
+     * |        |          |Note: For Timer1/3/5, this bit is ignored and the read back value is always 0.
+     * |[20]    |PERIOSEL  |Periodic Mode Behavior Selection Enable Bit
+     * |        |          |0 = The behavior selection in periodic mode is Disabled.
+     * |        |          |When user updates CMPDAT while timer is running in periodic mode, CNT will be reset to default value.
+     * |        |          |1 = The behavior selection in periodic mode is Enabled.
+     * |        |          |When user update CMPDAT while timer is running in periodic mode, the limitations as bellows list,
+     * |        |          |If updated CMPDAT value > CNT, CMPDAT will be updated and CNT keep running continually.
+     * |        |          |If updated CMPDAT value = CNT, timer time-out interrupt will be asserted immediately.
+     * |        |          |If updated CMPDAT value < CNT, CNT will be reset to default value.
+     * |[21]    |TGLPINSEL |Toggle-output Pin Select
+     * |        |          |0 = Toggle mode output to TMx (Timer Event Counter Pin).
+     * |        |          |1 = Toggle mode output to TMx_EXT (Timer External Capture Pin).
+     * |[22]    |CAPSRC    |Capture Pin Source Selection
+     * |        |          |0 = Capture Function source is from TMx_EXT (x= 0~5) pin.
+     * |        |          |1 =  Capture Function source is from internal ACMP output signal, internal clock source (HIRC, LIRC, MIRC) or external clock (HXT, LXT).
+     * |        |          |Note1:  When CAPSRC = 1, user can set INTERCAPSEL (TIMERx_EXTCTL[10:8]) to decide which internal ACMP output signal or which clock is as timer capture source.
+     * |        |          |Note2:  MIRC clock source is only available in Timer4 ~ Timer5.
+     * |[23]    |WKEN      |Wake-up Function Enable Bit
+     * |        |          |If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
+     * |        |          |0 = Wake-up function Disabled if timer interrupt signal generated.
+     * |        |          |1 = Wake-up function Enabled if timer interrupt signal generated.
+     * |[24]    |EXTCNTEN  |Event Counter Mode Enable Bit
+     * |        |          |This bit is for external counting pin function enabled.
+     * |        |          |0 = Event counter mode Disabled.
+     * |        |          |1 = Event counter mode Enabled.
+     * |        |          |Note: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source.
+     * |[25]    |ACTSTS    |Timer Active Status Bit (Read Only)
+     * |        |          |This bit indicates the 24-bit up counter status.
+     * |        |          |0 = 24-bit up counter is not active.
+     * |        |          |1 = 24-bit up counter is active.
+     * |        |          |Note: This bit may active when CNT 0 transition to CNT 1.
+     * |[28:27] |OPMODE    |Timer Counting Mode Select
+     * |        |          |00 = The Timer controller is operated in One-shot mode.
+     * |        |          |01 = The Timer controller is operated in Periodic mode.
+     * |        |          |10 = The Timer controller is operated in Toggle-output mode.
+     * |        |          |11 = The Timer controller is operated in Continuous Counting mode.
+     * |[29]    |INTEN     |Timer Interrupt Enable Bit
+     * |        |          |0 = Timer time-out interrupt Disabled.
+     * |        |          |1 = Timer time-out interrupt Enabled.
+     * |        |          |Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
+     * |[30]    |CNTEN     |Timer Counting Enable Bit
+     * |        |          |0 = Stops/Suspends counting.
+     * |        |          |1 = Starts counting.
+     * |        |          |Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value.
+     * |        |          |Note2: This bit is auto-cleared by hardware in one-shot mode (TIMER_CTL[28:27] = 00) when the timer time-out interrupt flag TIF (TIMERx_INTSTS[0]) is generated.
+     * |        |          |Note3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not.
+     * |[31]    |ICEDEBUG  |ICE Debug Mode Acknowledge Disable Control (Write Protect)
+     * |        |          |0 = ICE debug mode acknowledgment effects TIMER counting.
+     * |        |          |TIMER counter will be held while CPU is held by ICE.
+     * |        |          |1 = ICE debug mode acknowledgment Disabled.
+     * |        |          |TIMER counter will keep going no matter CPU is held by ICE or not.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * @var TIMER_T::CMP
+     * Offset: 0x04  Timer Comparator Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:0]  |CMPDAT    |Timer Comparator Value
+     * |        |          |CMPDAT is a 24-bit compared value register.
+     * |        |          |When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.
+     * |        |          |Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT).
+     * |        |          |Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.
+     * |        |          |Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field.
+     * |        |          |But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
+     * @var TIMER_T::INTSTS
+     * Offset: 0x08  Timer Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |TIF       |Timer Interrupt Flag
+     * |        |          |This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.
+     * |        |          |0 = No effect.
+     * |        |          |1 = CNT value matches the CMPDAT value.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[1]     |TWKF      |Timer Wake-up Flag
+     * |        |          |This bit indicates the interrupt wake-up flag status of timer.
+     * |        |          |0 = Timer does not cause CPU wake-up.
+     * |        |          |1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * @var TIMER_T::CNT
+     * Offset: 0x0C  Timer Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:0]  |CNT       |Timer Data Register
+     * |        |          |Read operation.
+     * |        |          |Read this register to get CNT value. For example:
+     * |        |          |If EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24-bit counter value.
+     * |        |          |If EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24-bit event input counter value.
+     * |        |          |Write operation.
+     * |        |          |Writing any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter.
+     * |[31]    |RSTACT    |Timer Data Register Reset Active (Read Only)
+     * |        |          |This bit indicates if the counter reset operation active.
+     * |        |          |When user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter.
+     * |        |          |At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress.
+     * |        |          |Once the counter reset operation done, timer clear this bit to 0 automatically.
+     * |        |          |0 = Reset operation is done.
+     * |        |          |1 = Reset operation triggered by writing TIMERx_CNT is in progress.
+     * |        |          |Note: This bit is read only.
+     * @var TIMER_T::CAP
+     * Offset: 0x10  Timer Capture Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[23:0]  |CAPDAT    |Timer Capture Data Register
+     * |        |          |When CAPEN (TIMERx_EXTCTL[3]) bit is set,  the transition on the capture source matches the CAPEDGE (TIMERx_EXTCTL[14:12]) setting,
+     * |        |          |CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
+     * @var TIMER_T::EXTCTL
+     * Offset: 0x14  Timer External Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CNTPHASE  |Timer External Count Phase
+     * |        |          |This bit indicates the detection phase of external counting pin TMx (x= 0~5).
+     * |        |          |0 = A falling edge of external counting pin will be counted.
+     * |        |          |1 = A rising edge of external counting pin will be counted.
+     * |[3]     |CAPEN     |Timer Capture Function Enable Bit
+     * |        |          |This bit enables the capture input function.
+     * |        |          |0 = Timer capture function Disabled.
+     * |        |          |1 = Timer capture function Enabled.
+     * |[4]     |CAPFUNCS  |Capture Function Selection
+     * |        |          |0 = Capture Mode Enabled.
+     * |        |          |1 = Reset Mode Enabled.
+     * |        |          |Note1: When CAPFUNCS is 0 and CAPIF becomes 1, the current 24-bit timer counter value (CNT value) will be saved to CAPDAT field.
+     * |        |          |Note2: When CAPFUNCS is 1 and CAPIF becomes 1, the current 24-bit timer counter value (CNT value) will be saved to CAPDAT field then CNT value will be reset immediately.
+     * |[5]     |CAPIEN    |Timer Capture Interrupt Enable Bit
+     * |        |          |0 = TMx_EXT (x= 0~5), ACMP, internal clock, or external clock detection Interrupt Disabled.
+     * |        |          |1 = TMx_EXT (x= 0~5), ACMP, internal clock, or external clock detection Interrupt Enabled.
+     * |        |          |Note: CAPIEN is used to enable timer capture interrupt.
+     * |        |          |If CAPIEN enabled, timer will rise an interrupt when CAPIF (TIMERx_EINTSTS[0]) is 1.
+     * |        |          |For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the TMx_EXT pin, ACMP, internal clock, or external clock
+     * |        |          |will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU.
+     * |[6]     |CAPDBEN   |Timer Capture De-bounce Enable Bit
+     * |        |          |0 = TMx_EXT (x= 0~5) pin de-bounce or ACMP output de-bounce Disabled.
+     * |        |          |1 = TMx_EXT (x= 0~5) pin de-bounce or ACMP output de-bounce Enabled.
+     * |        |          |Note: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit.
+     * |[7]     |CNTDBEN   |Timer External Counter Pin De-bounce Enable Bit
+     * |        |          |0 = TMx (x= 0~5) pin de-bounce Disabled.
+     * |        |          |1 = TMx (x= 0~5) pin de-bounce Enabled.
+     * |        |          |Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
+     * |[10:8]  |INTERCAPSEL|Internal Capture Source Select
+     * |        |          |000 = Capture Function source is from internal ACMP0 output signal.
+     * |        |          |001 = Capture Function source is from internal ACMP1 output signal.
+     * |        |          |010 = Capture Function source is from HXT.
+     * |        |          |011 = Capture Function source is from LXT.
+     * |        |          |100 = Capture Function source is from HIRC.
+     * |        |          |101 = Capture Function source is from LIRC.
+     * |        |          |101 = Capture Function source is from LIRC.
+     * |        |          |110 = Capture Function source is from MIRC, only available in Timer4 and Timer5.
+     * |        |          |111 = Reserved.
+     * |        |          |Note: These bits only available when CAPSRC (TIMERx_CTL[22]) is 1.
+     * |[14:12] |CAPEDGE   |Timer Capture Edge Detect
+     * |        |          |When first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.
+     * |        |          |000 = Capture event occurred when detect falling edge transfer on capture source.
+     * |        |          |001 = Capture event occurred when detect rising edge transfer on capture source.
+     * |        |          |010 = Capture event occurred when detect both falling and rising edge transfer on capture source, and the first capture event occurred at falling edge transfer.
+     * |        |          |011 = Capture event occurred when detect both rising and falling edge transfer on capture source, and the first capture event occurred at rising edge transfer.
+     * |        |          |110 = First capture event occurred at falling edge, follows capture events are at rising edge transfer on capture source.
+     * |        |          |111 = First capture event occurred at rising edge, follows capture events are at falling edge transfer on capture source.
+     * |        |          |100, 101 = Reserved.
+     * |        |          |Note: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL (TIMERx_EXTCTL[10:8]) to select capture source.
+     * |[16]    |ECNTSSEL  |Event Counter Source Selection to Trigger Event Counter Function
+     * |        |          |0 = Event Counter input source is from TMx (x= 0~5) pin.
+     * |        |          |1 = Event Counter input source is from USB internal SOF output signal.
+     * |[31:28] |CAPDIVSCL |Timer Capture Source Divider Scale
+     * |        |          |This bits indicate the divide scale for capture source divider.
+     * |        |          |0000 = Capture source/1.
+     * |        |          |0001 = Capture source/2.
+     * |        |          |0010 = Capture source/4.
+     * |        |          |0011 = Capture source/8.
+     * |        |          |0100 = Capture source/16.
+     * |        |          |0101 = Capture source/32.
+     * |        |          |0110 = Capture source/64.
+     * |        |          |0111 = Capture source/128.
+     * |        |          |1000 = Capture source/256.
+     * |        |          |1001~1111 = Reserved.
+     * |        |          |Note: Sets INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source.
+     * @var TIMER_T::EINTSTS
+     * Offset: 0x18  Timer External Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CAPIF     |Timer Capture Interrupt Flag
+     * |        |          |This bit indicates the timer capture interrupt flag status.
+     * |        |          |0 = TMx_EXT (x= 0~5) pin, ACMP, internal clock, or external clock capture interrupt did not occur.
+     * |        |          |1 = TMx_EXT (x= 0~5) pin, ACMP, internal clock, or external clock capture interrupt occurred.
+     * |        |          |Note1: This bit is cleared by writing 1 to it.
+     * |        |          |Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, the transition on the capture source matches the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, this bit will set to 1 by hardware.
+     * |        |          |Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status.
+     * |        |          |If the above condition occurred, the timer will keep register TIMERx_CAP unchanged and drop the new capture value.
+     * @var TIMER_T::TRGCTL
+     * Offset: 0x1C  Timer Trigger Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |TRGSSEL   |Trigger Source Select Bit
+     * |        |          |This bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal.
+     * |        |          |0 = Time-out interrupt signal is used to internal trigger EPWM/BPWM, PDMA, DAC, and EADC.
+     * |        |          |1 = Capture interrupt signal is used to internal trigger EPWM/BPWM, PDMA, DAC, and EADC.
+     * |[1]     |TRGPWM    |Trigger EPWM and BPWM Enable Bit
+     * |        |          |If this bit is set to 1, each timer time-out event or capture event can be as EPWM and BPWM counter clock source.
+     * |        |          |0 = Timer interrupt trigger EPWM and BPWM Disabled.
+     * |        |          |1 = Timer interrupt trigger EPWM and BPWM Enabled.
+     * |        |          |Note1: This bit is not available in Timer4 and Timer5.
+     * |        |          |Note2: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal as EPWM and BPWM counter clock source.
+     * |        |          |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal as EPWM and BPWM counter clock source.
+     * |[2]     |TRGEADC   |Trigger EADC Enable Bit
+     * |        |          |If this bit is set to 1, each timer time-out event or capture event can be triggered EADC conversion.
+     * |        |          |0 = Timer interrupt trigger EADC Disabled.
+     * |        |          |1 = Timer interrupt trigger EADC Enabled.
+     * |        |          |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger EADC conversion.
+     * |        |          |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger EADC conversion.
+     * |[3]     |TRGDAC    |Trigger DAC Enable Bit
+     * |        |          |If this bit is set to 1, each timer time-out event or capture event can be triggered DAC.
+     * |        |          |0 = Timer interrupt trigger DAC Disabled.
+     * |        |          |1 = Timer interrupt trigger DAC Enabled.
+     * |        |          |Note1: This bit is not available in Timer4 and Timer5.
+     * |        |          |Note2: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger DAC.
+     * |        |          |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger DAC.
+     * |[4]     |TRGPDMA   |Trigger PDMA Enable Bit
+     * |        |          |If this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer.
+     * |        |          |0 = Timer interrupt trigger PDMA Disabled.
+     * |        |          |1 = Timer interrupt trigger PDMA Enabled.
+     * |        |          |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger PDMA transfer.
+     * |        |          |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger PDMA transfer.
+     * @var TIMER_T::ALTCTL
+     * Offset: 0x20  Timer Alternative Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |FUNCSEL   |Function Selection
+     * |        |          |This bit sets the operation mode of Timer0 ~ Timer3 to PWM function.
+     * |        |          |0 = Timer controller is used as timer function.
+     * |        |          |1 = Timer controller is used as PWM function.
+     * |        |          |Note1: The Timer4 and Timer5 function selection is controlled in TIMERx_CTL[15], x= 4~5.
+     * |        |          |Note2: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically.
+     * @var TIMER_T::PWMCTL
+     * Offset: 0x40  Timer PWM Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CNTEN     |PWM Counter Enable Bit
+     * |        |          |0 = PWM counter and clock prescale Stop Running.
+     * |        |          |1 = PWM counter and clock prescale Start Running.
+     * |[2:1]   |CNTTYPE   |PWM Counter Behavior Type
+     * |        |          |These bits are used to set the count type of Timer0 ~ Timer3. The count type of Timer4 and Timer5 is fixed as the up count type.
+     * |        |          |00 = Up count type.
+     * |        |          |01 = Down count type.
+     * |        |          |10 = Up-down count type.
+     * |        |          |11 = Reserved.
+     * |        |          |Note: These bits are not available in Timer4 and Timer5.
+     * |[3]     |CNTMODE   |PWM Counter Mode
+     * |        |          |0 = Auto-reload mode.
+     * |        |          |1 = One-shot mode.
+     * |[8]     |CTRLD     |Center Re-load
+     * |        |          |In up-down count type, PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period.
+     * |        |          |Note: This bit is not available in Timer4 and Timer5.
+     * |[9]     |IMMLDEN   |Immediately Load Enable Bit
+     * |        |          |0 = PERIOD will load to PBUF when current PWM period is completed no matter CTRLD is enabled/disabled.
+     * |        |          |If CTRLD is disabled, CMP will load to CMPBUF when current PWM period is completed; if CTRLD is enabled in up-down count type, CMP will load to CMPBUF at the center point of current period.
+     * |        |          |1 = PERIOD/CMP will load to PBUF/CMPBUF immediately when user update PERIOD/CMP.
+     * |        |          |Note1: This bit is not available in Timer4 and Timer5.
+     * |        |          |Note2: If IMMLDEN is enabled, CTRLD will be invalid.
+     * |[12]    |WKEN      |PWM Wake-up Enable Bit
+     * |        |          |If this bit is set to 1, the Timer4 and Timer5 PWM interrupt eventl will generate a wake-up trigger event to CPU.
+     * |        |          |0 = PWM interrupt wake-up Disabled.
+     * |        |          |1 = PWM interrupt wake-up Enabled.
+     * |        |          |Note: This bit is only available in Timer4 and Timer5.
+     * |[16]    |OUTMODE   |PWM Output Mode
+     * |        |          |This bit controls the output mode of corresponding PWM channel.
+     * |        |          |0 = PWM independent mode.
+     * |        |          |1 = PWM complementary mode.
+     * |        |          |Note: This bit is not available in Timer4 and Timer5.
+     * |[30]    |DBGHALT   |ICE Debug Mode Counter Halt (Write Protect)
+     * |        |          |If debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode.
+     * |        |          |0 = ICE debug mode counter halt disable.
+     * |        |          |1 = ICE debug mode counter halt enable.
+     * |        |          |Note: This bit is write protected. Refer to SYS_REGLCTL register.
+     * |[31]    |DBGTRIOFF |ICE Debug Mode Acknowledge Disable Bit (Write Protect)
+     * |        |          |0 = ICE debug mode acknowledgment effects PWM output.
+     * |        |          |PWM output pin will be forced as tri-state while ICE debug mode acknowledged.
+     * |        |          |1 = ICE debug mode acknowledgment disabled.
+     * |        |          |PWM output pin will keep output no matter ICE debug mode acknowledged or not.
+     * |        |          |Note: This bit is write protected. Refer to SYS_REGLCTL register.
+     * @var TIMER_T::PWMCLKSRC
+     * Offset: 0x44  Timer PWM Counter Clock Source Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |CLKSRC    |PWM Counter Clock Source Select
+     * |        |          |The PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event in Timer0 ~ Timer3.
+     * |        |          |000 = TMRx_CLK.
+     * |        |          |001 = Internal TIMER0 time-out or capture event.
+     * |        |          |010 = Internal TIMER1 time-out or capture event.
+     * |        |          |011 = Internal TIMER2 time-out or capture event.
+     * |        |          |100 = Internal TIMER3 time-out or capture event.
+     * |        |          |Others = Reserved.
+     * |        |          |Note1: These bits are not available in Timer4 and Timer5.
+     * |        |          |Note2: If TIMER0 PWM function is enabled, the PWM counter clock source can be selected from TMR0_CLK, TIMER1 interrupt events, TIMER2 interrupt events, or TIMER3 interrupt events.
+     * @var TIMER_T::PWMCLKPSC
+     * Offset: 0x48  Timer PWM Counter Clock Pre-scale Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[11:0]  |CLKPSC    |PWM Counter Clock Pre-scale
+     * |        |          |The active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1).
+     * |        |          |If CLKPSC is 0, then there is no scaling in PWM counter clock source.
+     * |        |          |Note: The valid value is 12-bit TIMERx_PWMCLKPSC[11:0] in Timer0 ~ Timer3, and 8-bit TIMERx_PWMCLKPSC[7:0] in Timer4 and Timer5.
+     * @var TIMER_T::PWMCNTCLR
+     * Offset: 0x4C  Timer PWM Clear Counter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CNTCLR    |Clear PWM Counter Control Bit
+     * |        |          |It is automatically cleared by hardware.
+     * |        |          |0 = No effect.
+     * |        |          |1 = In Timer0 ~ Timer3, clears 16-bit PWM counter to 0x10000 in up and up-down count type and reset counter value to PERIOD in down count type.
+     * |        |          |In Timer4 and Timer5, clears 16-bit PWM counter to 0x0 in up count type.
+     * @var TIMER_T::PWMPERIOD
+     * Offset: 0x50  Timer PWM Period Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |PERIOD    |PWM Period Register
+     * |        |          |In up count type: PWM counter counts from 0 to PERIOD, and restarts from 0.
+     * |        |          |In down count type: PWM counter counts from PERIOD to 0, and restarts from PERIOD.
+     * |        |          |In up-down count type: PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.
+     * |        |          |In up and down count type:
+     * |        |          |PWM period time = (PERIOD + 1) * (CLKPSC + 1) * TMRx_PWMCLK.
+     * |        |          |In up-down count type:
+     * |        |          |PWM period time = 2 * PERIOD * (CLKPSC+ 1) * TMRx_PWMCLK.
+     * |        |          |Note1: The count type of Timer4 and Timer5 is fixed as up count type.
+     * |        |          |Note2: User should take care DIRF (TIMERx_PWMCNT[16]) bit in up/down/up-down count type to monitor current counter direction in each count type in Timer0 ~ Timer3.
+     * @var TIMER_T::PWMCMPDAT
+     * Offset: 0x54  Timer PWM Comparator Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |CMP       |PWM Comparator Register
+     * |        |          |PWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger EADC and PDMA to start conversion.
+     * @var TIMER_T::PWMDTCTL
+     * Offset: 0x58  Timer PWM Dead-Time Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[11:0]  |DTCNT     |Dead-time Counter (Write Protect)
+     * |        |          |The dead-time can be calculated from the following two formulas:
+     * |        |          |Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK, if DTCKSEL is 0.
+     * |        |          |Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK * (CLKPSC + 1), if DTCKSEL is 1.
+     * |        |          |Note: These bits are write protected. Refer to SYS_REGLCTL register.
+     * |[16]    |DTEN      |Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect)
+     * |        |          |Dead-time insertion function is only active when PWM complementary mode is enabled.
+     * |        |          |If dead-time insertion is inactive, the outputs of PWMx_CH0 and PWMx_CH1 are complementary without any delay.
+     * |        |          |0 = Dead-time insertion Disabled on the pin pair.
+     * |        |          |1 = Dead-time insertion Enabled on the pin pair.
+     * |        |          |Note: This bit is write protected. Refer to SYS_REGLCTL register.
+     * |[24]    |DTCKSEL   |Dead-time Clock Select (Write Protect)
+     * |        |          |0 = Dead-time clock source from TMRx_PWMCLK without counter clock prescale.
+     * |        |          |1 = Dead-time clock source from TMRx_PWMCLK with counter clock prescale.
+     * |        |          |Note: This bit is write protected. Refer to SYS_REGLCTL register.
+     * @var TIMER_T::PWMCNT
+     * Offset: 0x5C  Timer PWM Counter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |CNT       |PWM Counter Value Register (Read Only)
+     * |        |          |User can monitor CNT to know the current counter value in 16-bit period counter.
+     * |[16]    |DIRF      |PWM Counter Direction Indicator Flag (Read Only)
+     * |        |          |0 = Counter is active in down count.
+     * |        |          |1 = Counter is active up count.
+     * |        |          |Note1: This indicator flag is used for Timer0 ~ Timer3 only.
+     * |        |          |Note2: Since the count type of Timer4 ~ Timer5 is fixed as up count, this bit is fixed 0 in Timer4 and Timer5.
+     * @var TIMER_T::PWMMSKEN
+     * Offset: 0x60  Timer PWM Output Mask Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |MSKEN0    |PWMx_CH0 Output Mask Enable Bit
+     * |        |          |The PWMx_CH0 output signal will be masked when this bit is enabled.
+     * |        |          |The PWMx_CH0 will output MSKDAT0 (TIMERx_PWMMSK[0]) data.
+     * |        |          |0 = PWMx_CH0 output signal is non-masked.
+     * |        |          |1 = PWMx_CH0 output signal is masked and output MSKDAT0 data.
+     * |[1]     |MSKEN1    |PWMx_CH1 Output Mask Enable Bit
+     * |        |          |The PWMx_CH1 output signal will be masked when this bit is enabled.
+     * |        |          |The PWMx_CH1 will output MSKDAT1 (TIMERx_PWMMSK[1]) data.
+     * |        |          |0 = PWMx_CH1 output signal is non-masked.
+     * |        |          |1 = PWMx_CH1 output signal is masked and output MSKDAT1 data.
+     * @var TIMER_T::PWMMSK
+     * Offset: 0x64  Timer PWM Output Mask Data Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |MSKDAT0   |PWMx_CH0 Output Mask Data Control Bit
+     * |        |          |This bit is used to control the output state of PWMx_CH0 pin when PWMx_CH0 output mask function is enabled (MSKEN0 = 1).
+     * |        |          |0 = Output logic Low to PWMx_CH0.
+     * |        |          |1 = Output logic High to PWMx_CH0.
+     * |[1]     |MSKDAT1   |PWMx_CH1 Output Mask Data Control Bit
+     * |        |          |This bit is used to control the output state of PWMx_CH1 pin when PWMx_CH1 output mask function is enabled (MSKEN1 = 1).
+     * |        |          |0 = Output logic Low to PWMx_CH1.
+     * |        |          |1 = Output logic High to PWMx_CH1.
+     * @var TIMER_T::PWMBNF
+     * Offset: 0x68  Timer PWM Brake Pin Noise Filter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BRKNFEN   |Brake Pin Noise Filter Enable Bit
+     * |        |          |0 = Pin noise filter detect of PWMx_BRAKEy Disabled.
+     * |        |          |1 = Pin noise filter detect of PWMx_BRAKEy Enabled.
+     * |[3:1]   |BRKNFSEL  |Brake Pin Noise Filter Clock Selection
+     * |        |          |000 = Noise filter clock is PCLKx.
+     * |        |          |001 = Noise filter clock is PCLKx/2.
+     * |        |          |010 = Noise filter clock is PCLKx/4.
+     * |        |          |011 = Noise filter clock is PCLKx/8.
+     * |        |          |100 = Noise filter clock is PCLKx/16.
+     * |        |          |101 = Noise filter clock is PCLKx/32.
+     * |        |          |110 = Noise filter clock is PCLKx/64.
+     * |        |          |111 = Noise filter clock is PCLKx/128.
+     * |[6:4]   |BRKFCNT   |Brake Pin Noise Filter Count
+     * |        |          |The fields is used to control the active noise filter sample time.
+     * |        |          |Once noise filter sample time = (Period time of BRKNFSEL) * (BRKFCNT + 1).
+     * |[7]     |BRKPINV   |Brake Pin Detection Control Bit
+     * |        |          |0 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from low to high in edge-detect, or pin status is high in level-detect.
+     * |        |          |1 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from high to low in edge-detect, or pin status is low in level-detect .
+     * |[17:16] |BKPINSRC  |Brake Pin Source Select
+     * |        |          |00 = Brake pin source comes from PWM0_BRAKE0 pin.
+     * |        |          |01 = Brake pin source comes from PWM0_BRAKE1 pin.
+     * |        |          |10 = Brake pin source comes from PWM1_BRAKE0 pin.
+     * |        |          |11 = Brake pin source comes from PWM1_BRAKE1 pin.
+     * @var TIMER_T::PWMFAILBRK
+     * Offset: 0x6C  Timer PWM System Fail Brake Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CSSBRKEN  |Clock Security System Detection Trigger PWM Brake Function Enable Bit
+     * |        |          |0 = Brake Function triggered by clock fail detection Disabled.
+     * |        |          |1 = Brake Function triggered by clock fail detection Enabled.
+     * |[1]     |BODBRKEN  |Brown-out Detection Trigger PWM Brake Function Enable Bit
+     * |        |          |0 = Brake Function triggered by BOD event Disabled.
+     * |        |          |1 = Brake Function triggered by BOD event Enabled.
+     * |[2]     |RAMBRKEN  |SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit
+     * |        |          |0 = Brake Function triggered by SRAM parity error detection Disabled.
+     * |        |          |1 = Brake Function triggered by SRAM parity error detection Enabled.
+     * |[3]     |CORBRKEN  |Core Lockup Detection Trigger PWM Brake Function Enable Bit
+     * |        |          |0 = Brake Function triggered by core lockup event Disabled.
+     * |        |          |1 = Brake Function triggered by core lockup event Enabled.
+     * @var TIMER_T::PWMBRKCTL
+     * Offset: 0x70  Timer PWM Brake Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CPO0EBEN  |Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)
+     * |        |          |0 = Internal ACMP0_O signal as edge-detect brake source Disabled.
+     * |        |          |1 = Internal ACMP0_O signal as edge-detect brake source Enabled.
+     * |        |          |Note1: Only internal ACMP0_O signal from low to high will be detected as brake event.
+     * |        |          |Note2: This bit is write protected. Refer to SYS_REGLCTL register.
+     * |[1]     |CPO1EBEN  |Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)
+     * |        |          |0 = Internal ACMP1_O signal as edge-detect brake source Disabled.
+     * |        |          |1 = Internal ACMP1_O signal as edge-detect brake source Enabled.
+     * |        |          |Note1: Only internal ACMP1_O signal from low to high will be detected as brake event.
+     * |        |          |Note2: This bit is write protected. Refer to SYS_REGLCTL register.
+     * |[4]     |BRKPEEN   |Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect)
+     * |        |          |0 = PWMx_BRAKEy pin event as edge-detect brake source Disabled.
+     * |        |          |1 = PWMx_BRAKEy pin event as edge-detect brake source Enabled.
+     * |        |          |Note: This bit is write protected. Refer to SYS_REGLCTL register.
+     * |[7]     |SYSEBEN   |Enable System Fail As Edge-detect Brake Source (Write Protect)
+     * |        |          |0 = System fail condition as edge-detect brake source Disabled.
+     * |        |          |1 = System fail condition as edge-detect brake source Enabled.
+     * |        |          |Note: This bit is write protected. Refer to SYS_REGLCTL register.
+     * |[8]     |CPO0LBEN  |Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)
+     * |        |          |0 = Internal ACMP0_O signal as level-detect brake source Disabled.
+     * |        |          |1 = Internal ACMP0_O signal as level-detect brake source Enabled.
+     * |        |          |Note1: Only internal ACMP0_O signal from low to high will be detected as brake event.
+     * |        |          |Note2: This bit is write protected. Refer to SYS_REGLCTL register.
+     * |[9]     |CPO1LBEN  |Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)
+     * |        |          |0 = Internal ACMP1_O signal as level-detect brake source Disabled.
+     * |        |          |1 = Internal ACMP1_O signal as level-detect brake source Enabled.
+     * |        |          |Note1: Only internal ACMP1_O signal from low to high will be detected as brake event.
+     * |        |          |Note: This bit is write protected. Refer to SYS_REGLCTL register.
+     * |[12]    |BRKPLEN   |Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect)
+     * |        |          |0 = PWMx_BRAKEy pin event as level-detect brake source Disabled.
+     * |        |          |1 = PWMx_BRAKEy pin event as level-detect brake source Enabled.
+     * |        |          |Note: This bit is write protected. Refer to SYS_REGLCTL register.
+     * |[15]    |SYSLBEN   |Enable System Fail As Level-detect Brake Source (Write Protect)
+     * |        |          |0 = System fail condition as level-detect brake source Disabled.
+     * |        |          |1 = System fail condition as level-detect brake source Enabled.
+     * |        |          |Note: This bit is write protected. Refer to SYS_REGLCTL register.
+     * |[17:16] |BRKAEVEN  |PWM Brake Action Select for PWMx_CH0 (Write Protect)
+     * |        |          |00 = PWMx_BRAKEy brake event will not affect PWMx_CH0 output.
+     * |        |          |01 = PWMx_CH0 output tri-state when PWMx_BRAKEy brake event happened.
+     * |        |          |10 = PWMx_CH0 output low level when PWMx_BRAKEy brake event happened.
+     * |        |          |11 = PWMx_CH0 output high level when PWMx_BRAKEy brake event happened.
+     * |        |          |Note: These bits are write protected. Refer to SYS_REGLCTL register.
+     * |[19:18] |BRKAODD   |PWM Brake Action Select for PWMx_CH1 (Write Protect)
+     * |        |          |00 = PWMx_BRAKEy brake event will not affect PWMx_CH1 output.
+     * |        |          |01 = PWMx_CH1 output tri-state when PWMx_BRAKEy brake event happened.
+     * |        |          |10 = PWMx_CH1 output low level when PWMx_BRAKEy brake event happened.
+     * |        |          |11 = PWMx_CH1 output high level when PWMx_BRAKEy brake event happened.
+     * |        |          |Note: These bits are write protected. Refer to SYS_REGLCTL register.
+     * @var TIMER_T::PWMPOLCTL
+     * Offset: 0x74  Timer PWM Pin Output Polar Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PINV0     |PWMx_CH0 Output Pin Polar Control Bit
+     * |        |          |The bit is used to control polarity state of PWMx_CH0 output pin.
+     * |        |          |0 = PWMx_CH0 output pin polar inverse Disabled.
+     * |        |          |1 = PWMx_CH0 output pin polar inverse Enabled.
+     * |        |          |Note: In Timer4 and Timer5, the PWMx_CH0 output pin can be selected as TMx or TMx_EXT pin by POSEL (TIMERx_PWMPOEN[8]), x= 4~5.
+     * |[1]     |PINV1     |PWMx_CH1 Output Pin Polar Control Bit
+     * |        |          |The bit is used to control polarity state of PWMx_CH1 output pin.
+     * |        |          |0 = PWMx_CH1 output pin polar inverse Disabled.
+     * |        |          |1 = PWMx_CH1 output pin polar inverse Enabled.
+     * |        |          |Note: This bit is not available in Timer4 and Timer5.
+     * @var TIMER_T::PWMPOEN
+     * Offset: 0x78  Timer PWM Pin Output Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |POEN0     |PWMx_CH0 Output Pin Enable Bit
+     * |        |          |0 = PWMx_CH0 pin at tri-state mode.
+     * |        |          |1 = PWMx_CH0 pin in output mode.
+     * |        |          |Note: In Timer4 and Timer5, the PWMx_CH0 output pin can be selected as TMx or TMx_EXT pin by POSEL (TIMERx_PWMPOEN[8]), x= 4~5.
+     * |[1]     |POEN1     |PWMx_CH1 Output Pin Enable Bit
+     * |        |          |0 = PWMx_CH1 pin at tri-state mode.
+     * |        |          |1 = PWMx_CH1 pin in output mode.
+     * |        |          |Note: This bit is not available in Timer4 and Timer5.
+     * |[8]     |POSEL     |PWMx_CH0 Output Pin Select
+     * |        |          |This bit is used to select the output channel of Timer4 and Timer5 PWM.
+     * |        |          |0 = PWMx_CH0 pin is TMx.
+     * |        |          |1 = PWMx_CH0 pin is TMx_EXT.
+     * |        |          |Note: This bit is only available in Timer4 and Timer5.
+     * @var TIMER_T::PWMSWBRK
+     * Offset: 0x7C  Timer PWM Software Trigger Brake Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BRKETRG   |Software Trigger Edge-detect Brake Source (Write Only) (Write Protect)
+     * |        |          |Write 1 to this bit will trigger PWM edge-detect brake source, then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register.
+     * |        |          |Note: This bit is write protected. Refer to SYS_REGLCTL register.
+     * |[8]     |BRKLTRG   |Software Trigger Level-detect Brake Source (Write Only) (Write Protect)
+     * |        |          |Write 1 to this bit will trigger PWM level-detect brake source, then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register.
+     * |        |          |Note: This bit is write protected. Refer to SYS_REGLCTL register.
+     * @var TIMER_T::PWMINTEN0
+     * Offset: 0x80  Timer PWM Interrupt Enable Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ZIEN      |PWM Zero Point Interrupt Enable Bit
+     * |        |          |0 = Zero point interrupt Disabled.
+     * |        |          |1 = Zero point interrupt Enabled.
+     * |        |          |Note: This bit is not available in Timer4 and Timer5.
+     * |[1]     |PIEN      |PWM Period Point Interrupt Enable Bit
+     * |        |          |0 = Period point interrupt Disabled.
+     * |        |          |1 = Period point interrupt Enabled.
+     * |        |          |Note: In up-down count type, period point means the center point of current PWM period.
+     * |[2]     |CMPUIEN   |PWM Compare Up Count Interrupt Enable Bit
+     * |        |          |0 = Compare up count interrupt Disabled.
+     * |        |          |1 = Compare up count interrupt Enabled.
+     * |[3]     |CMPDIEN   |PWM Compare Down Count Interrupt Enable Bit
+     * |        |          |0 = Compare down count interrupt Disabled.
+     * |        |          |1 = Compare down count interrupt Enabled.
+     * |        |          |Note: This bit is not available in Timer4 and Timer5.
+     * @var TIMER_T::PWMINTEN1
+     * Offset: 0x84  Timer PWM Interrupt Enable Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BRKEIEN   |PWM Edge-detect Brake Interrupt Enable (Write Protect)
+     * |        |          |0 = PWM edge-detect brake interrupt Disabled.
+     * |        |          |1 = PWM edge-detect brake interrupt Enabled.
+     * |        |          |Note: This bit is write protected. Refer to SYS_REGLCTL register.
+     * |[8]     |BRKLIEN   |PWM Level-detect Brake Interrupt Enable (Write Protect)
+     * |        |          |0 = PWM level-detect brake interrupt Disabled.
+     * |        |          |1 = PWM level-detect brake interrupt Enabled.
+     * |        |          |Note: This bit is write protected. Refer to SYS_REGLCTL register.
+     * @var TIMER_T::PWMINTSTS0
+     * Offset: 0x88  Timer PWM Interrupt Status Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ZIF       |PWM Zero Point Interrupt Flag
+     * |        |          |This bit is set by hardware when TIMERx_PWM counter reaches zero.
+     * |        |          |Note1: This bit is not available in Timer4 and Timer5.
+     * |        |          |Note2: This bit is cleared by writing 1 to it.
+     * |[1]     |PIF       |PWM Period Point Interrupt Flag
+     * |        |          |This bit is set by hardware when TIMERx_PWM counter reaches PERIOD.
+     * |        |          |Note1: In up-down count type, PIF flag means the center point flag of current PWM period.
+     * |        |          |Note2: This bit is cleared by writing 1 to it.
+     * |[2]     |CMPUIF    |PWM Compare Up Count Interrupt Flag
+     * |        |          |This bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.
+     * |        |          |Note1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type and up-down count type..
+     * |        |          |Note2: This bit is cleared by writing 1 to it.
+     * |[3]     |CMPDIF    |PWM Compare Down Count Interrupt Flag
+     * |        |          |This bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP.
+     * |        |          |Note1: This bit is not available in Timer4 and Timer5.
+     * |        |          |Note2: If CMP equal to PERIOD, there is no CMPDIF flag in down count type.
+     * |        |          |Note3: This bit is cleared by writing 1 to it.
+     * @var TIMER_T::PWMINTSTS1
+     * Offset: 0x8C  Timer PWM Interrupt Status Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BRKEIF0   |Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)
+     * |        |          |0 = PWMx_CH0 edge-detect brake event do not happened.
+     * |        |          |1 = PWMx_CH0 edge-detect brake event happened.
+     * |        |          |Note1: This bit is cleared by writing 1 to it.
+     * |        |          |Note2: This bit is write protected. Refer to SYS_REGLCTL register.
+     * |[1]     |BRKEIF1   |Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect)
+     * |        |          |0 = PWMx_CH1 edge-detect brake event do not happened.
+     * |        |          |1 = PWMx_CH1 edge-detect brake event happened.
+     * |        |          |Note1: This bit is cleared by writing 1 to it.
+     * |        |          |Note2: This bit is write protected. Refer to SYS_REGLCTL register.
+     * |[8]     |BRKLIF0   |Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)
+     * |        |          |0 = PWMx_CH0 level-detect brake event do not happened.
+     * |        |          |1 = PWMx_CH0 level-detect brake event happened.
+     * |        |          |Note1: This bit is cleared by writing 1 to it.
+     * |        |          |Note2: This bit is write protected. Refer to SYS_REGLCTL register.
+     * |[9]     |BRKLIF1   |Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect)
+     * |        |          |0 = PWMx_CH1 level-detect brake event do not happened.
+     * |        |          |1 = PWMx_CH1 level-detect brake event happened.
+     * |        |          |Note1: This bit is cleared by writing 1 to it.
+     * |        |          |Note2: This bit is write protected. Refer to SYS_REGLCTL register.
+     * |[16]    |BRKESTS0  |Edge -detect Brake Status of PWMx_CH0 (Read Only)
+     * |        |          |0 = PWMx_CH0 edge-detect brake state is released.
+     * |        |          |1 = PWMx_CH0 at edge-detect brake state.
+     * |        |          |Note: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period.
+     * |[17]    |BRKESTS1  |Edge-detect Brake Status of PWMx_CH1 (Read Only)
+     * |        |          |0 = PWMx_CH1 edge-detect brake state is released.
+     * |        |          |1 = PWMx_CH1 at edge-detect brake state.
+     * |        |          |Note: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period.
+     * |[24]    |BRKLSTS0  |Level-detect Brake Status of PWMx_CH0 (Read Only)
+     * |        |          |0 = PWMx_CH0 level-detect brake state is released.
+     * |        |          |1 = PWMx_CH0 at level-detect brake state.
+     * |        |          |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period.
+     * |[25]    |BRKLSTS1  |Level-detect Brake Status of PWMx_CH1 (Read Only)
+     * |        |          |0 = PWMx_CH1 level-detect brake state is released.
+     * |        |          |1 = PWMx_CH1 at level-detect brake state.
+     * |        |          |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period.
+     * @var TIMER_T::PWMTRGCTL
+     * Offset: 0x90  Timer PWM Trigger Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |TRGSEL    |PWM Counter Event Source Select to Trigger Conversion
+     * |        |          |In Timer0 ~ Timer3,
+     * |        |          |000 = Trigger conversion at zero point (ZIF).
+     * |        |          |001 = Trigger conversion at period point (PIF).
+     * |        |          |010 = Trigger conversion at zero or period point (ZIF or PIF).
+     * |        |          |011 = Trigger conversion at compare up count point (CMPUIF).
+     * |        |          |100 = Trigger conversion at compare down count point (CMPDIF).
+     * |        |          |In Timer4 and Timer5,
+     * |        |          |001 = Trigger conversion at period point (PIF).
+     * |        |          |011 = Trigger conversion at compare up count point (CMPUIF).
+     * |        |          |101 = Trigger conversion at period or compare up count point (PIF or CMPUIF).
+     * |        |          |Others = Reserved.
+     * |[7]     |TRGEADC   |PWM Counter Event Trigger EADC Conversion Enable Bit
+     * |        |          |0 = PWM counter event trigger EADC conversion Disabled.
+     * |        |          |1 = PWM counter event trigger EADC conversion Enabled.
+     * |        |          |Note: Set TRGSEL (TIMERx_PWMTRGCTL[2:0]) to select PWM trigger conversion source.
+     * |[9]     |TRGPDMA   |PWM Counter Event Trigger PDMA Conversion Enable Bit
+     * |        |          |0 = PWM counter event trigger PDMA conversion Disabled.
+     * |        |          |1 = PWM counter event trigger PDMA conversion Enabled.
+     * |        |          |Note: Set TRGSEL (TIMERx_PWMTRGCTL[2:0]) to select PWM trigger conversion source.
+     * @var TIMER_T::PWMSCTL
+     * Offset: 0x94  Timer PWM Synchronous Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |SYNCMODE  |PWM Synchronous Mode Enable Select
+     * |        |          |00 = PWM synchronous function Disabled.
+     * |        |          |01 = PWM synchronous counter start function Enabled.
+     * |        |          |10 = Reserved.
+     * |        |          |11 = PWM synchronous counter clear function Enabled.
+     * |[8]     |SYNCSRC   |PWM Synchronous Counter Start/Clear Source Select
+     * |        |          |0 = Counter synchronous start/clear by trigger TIMER0_PWMSTRG STRGEN.
+     * |        |          |1 = Counter synchronous start/clear by trigger TIMER2_PWMSTRG STRGEN.
+     * |        |          |Note1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8], TIMER1_PWMSCTL[8], TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0.
+     * |        |          |Note2: If TIMER0/1/ PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8] and TIMER1_PWMSCTL[8] should be set 0, and TIMER2/3/ PWM counter synchronous source are from TIMER2, TIME2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be set 1.
+     * @var TIMER_T::PWMSTRG
+     * Offset: 0x98  Timer PWM Synchronous Trigger Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |STRGEN    |PWM Counter Synchronous Trigger Enable Bit (Write Only)
+     * |        |          |PMW counter synchronous function is used to make selected PWM channels (include TIMER0/1/2/3 PWM, TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according to TIMERx_PWMSCTL setting.
+     * |        |          |Note: This bit is only available in TIMER0 and TIMER2.
+     * @var TIMER_T::PWMSTATUS
+     * Offset: 0x9C  Timer PWM Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CNTMAXF   |PWM Counter Equal to 0xFFFF Flag
+     * |        |          |0 = The PWM counter value never reached its maximum value 0xFFFF.
+     * |        |          |1 = The PWM counter value has reached its maximum value.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[8]     |WKF       |PWM Wake-up Flag
+     * |        |          |0 = PWM interrupt wake-up has not occurred.
+     * |        |          |1 = PWM interrupt wake-up has occurred.
+     * |        |          |Note1: This bit is only available in Timer4 and Timer5.
+     * |        |          |Note2: This bit is cleared by writing 1 to it.
+     * |[16]    |EADCTRGF  |Trigger EADC Start Conversion Flag
+     * |        |          |0 = PWM counter event trigger EADC start conversion is not occurred.
+     * |        |          |1 = PWM counter event trigger EADC start conversion has occurred.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[19]    |PDMATRGF  |Trigger PDMA Start Conversion Flag
+     * |        |          |0 = PWM counter event trigger PDMA start conversion is not occurred.
+     * |        |          |1 = PWM counter event trigger PDMA start conversion has occurred.
+     * |        |          |Note1: This bit is only available in Timer4 and Timer5.
+     * |        |          |Note2: This bit is cleared by writing 1 to it.
+     * @var TIMER_T::PWMPBUF
+     * Offset: 0xA0  Timer PWM Period Buffer Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |PBUF      |PWM Period Buffer Register (Read Only)
+     * |        |          |Used as PERIOD active register.
+     * @var TIMER_T::PWMCMPBUF
+     * Offset: 0xA4  Timer PWM Comparator Buffer Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |CMPBUF    |PWM Comparator Buffer Register (Read Only)
+     * |        |          |Used as CMP active register.
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] Timer Control Register                                          */
+    __IO uint32_t CMP;                   /*!< [0x0004] Timer Comparator Register                                       */
+    __IO uint32_t INTSTS;                /*!< [0x0008] Timer Interrupt Status Register                                 */
+    __IO uint32_t CNT;                   /*!< [0x000c] Timer Data Register                                             */
+    __I  uint32_t CAP;                   /*!< [0x0010] Timer Capture Data Register                                     */
+    __IO uint32_t EXTCTL;                /*!< [0x0014] Timer External Control Register                                 */
+    __IO uint32_t EINTSTS;               /*!< [0x0018] Timer External Interrupt Status Register                        */
+    __IO uint32_t TRGCTL;                /*!< [0x001c] Timer Trigger Control Register                                  */
+    __IO uint32_t ALTCTL;                /*!< [0x0020] Timer Alternative Control Register                              */
+    __I  uint32_t RESERVE0[7];
+    __IO uint32_t PWMCTL;                /*!< [0x0040] Timer PWM Control Register                                      */
+    __IO uint32_t PWMCLKSRC;             /*!< [0x0044] Timer PWM Counter Clock Source Register                         */
+    __IO uint32_t PWMCLKPSC;             /*!< [0x0048] Timer PWM Counter Clock Pre-scale Register                      */
+    __IO uint32_t PWMCNTCLR;             /*!< [0x004c] Timer PWM Clear Counter Register                                */
+    __IO uint32_t PWMPERIOD;             /*!< [0x0050] Timer PWM Period Register                                       */
+    __IO uint32_t PWMCMPDAT;             /*!< [0x0054] Timer PWM Comparator Register                                   */
+    __IO uint32_t PWMDTCTL;              /*!< [0x0058] Timer PWM Dead-Time Control Register                            */
+    __I  uint32_t PWMCNT;                /*!< [0x005c] Timer PWM Counter Register                                      */
+    __IO uint32_t PWMMSKEN;              /*!< [0x0060] Timer PWM Output Mask Enable Register                           */
+    __IO uint32_t PWMMSK;                /*!< [0x0064] Timer PWM Output Mask Data Control Register                     */
+    __IO uint32_t PWMBNF;                /*!< [0x0068] Timer PWM Brake Pin Noise Filter Register                       */
+    __IO uint32_t PWMFAILBRK;            /*!< [0x006c] Timer PWM System Fail Brake Control Register                    */
+    __IO uint32_t PWMBRKCTL;             /*!< [0x0070] Timer PWM Brake Control Register                                */
+    __IO uint32_t PWMPOLCTL;             /*!< [0x0074] Timer PWM Pin Output Polar Control Register                     */
+    __IO uint32_t PWMPOEN;               /*!< [0x0078] Timer PWM Pin Output Enable Register                            */
+    __O  uint32_t PWMSWBRK;              /*!< [0x007c] Timer PWM Software Trigger Brake Control Register               */
+    __IO uint32_t PWMINTEN0;             /*!< [0x0080] Timer PWM Interrupt Enable Register 0                           */
+    __IO uint32_t PWMINTEN1;             /*!< [0x0084] Timer PWM Interrupt Enable Register 1                           */
+    __IO uint32_t PWMINTSTS0;            /*!< [0x0088] Timer PWM Interrupt Status Register 0                           */
+    __IO uint32_t PWMINTSTS1;            /*!< [0x008c] Timer PWM Interrupt Status Register 1                           */
+    __IO uint32_t PWMTRGCTL;             /*!< [0x0090] Timer PWM Trigger Control Register                              */
+    __IO uint32_t PWMSCTL;               /*!< [0x0094] Timer PWM Synchronous Control Register                          */
+    __O  uint32_t PWMSTRG;               /*!< [0x0098] Timer PWM Synchronous Trigger Register                          */
+    __IO uint32_t PWMSTATUS;             /*!< [0x009c] Timer PWM Status Register                                       */
+    __I  uint32_t PWMPBUF;               /*!< [0x00a0] Timer PWM Period Buffer Register                                */
+    __I  uint32_t PWMCMPBUF;             /*!< [0x00a4] Timer PWM Comparator Buffer Register                            */
+
+} TIMER_T;
+
+/**
+    @addtogroup TIMER_CONST TIMER Bit Field Definition
+    Constant Definitions for TIMER Controller
+  @{
+*/
+
+#define TIMER_CTL_PSC_Pos                (0)                                               /*!< TIMER_T::CTL: PSC Position             */
+#define TIMER_CTL_PSC_Msk                (0xfful << TIMER_CTL_PSC_Pos)                     /*!< TIMER_T::CTL: PSC Mask                 */
+
+#define TIMER_CTL_FUNCSEL_Pos            (15)                                              /*!< TIMER_T::CTL: FUNCSEL Position         */
+#define TIMER_CTL_FUNCSEL_Msk            (0x1ul << TIMER_CTL_FUNCSEL_Pos)                  /*!< TIMER_T::CTL: FUNCSEL Mask             */
+
+#define TIMER_CTL_INTRGEN_Pos            (19)                                              /*!< TIMER_T::CTL: INTRGEN Position         */
+#define TIMER_CTL_INTRGEN_Msk            (0x1ul << TIMER_CTL_INTRGEN_Pos)                  /*!< TIMER_T::CTL: INTRGEN Mask             */
+
+#define TIMER_CTL_PERIOSEL_Pos           (20)                                              /*!< TIMER_T::CTL: PERIOSEL Position        */
+#define TIMER_CTL_PERIOSEL_Msk           (0x1ul << TIMER_CTL_PERIOSEL_Pos)                 /*!< TIMER_T::CTL: PERIOSEL Mask            */
+
+#define TIMER_CTL_TGLPINSEL_Pos          (21)                                              /*!< TIMER_T::CTL: TGLPINSEL Position       */
+#define TIMER_CTL_TGLPINSEL_Msk          (0x1ul << TIMER_CTL_TGLPINSEL_Pos)                /*!< TIMER_T::CTL: TGLPINSEL Mask           */
+
+#define TIMER_CTL_CAPSRC_Pos             (22)                                              /*!< TIMER_T::CTL: CAPSRC Position          */
+#define TIMER_CTL_CAPSRC_Msk             (0x1ul << TIMER_CTL_CAPSRC_Pos)                   /*!< TIMER_T::CTL: CAPSRC Mask              */
+
+#define TIMER_CTL_WKEN_Pos               (23)                                              /*!< TIMER_T::CTL: WKEN Position            */
+#define TIMER_CTL_WKEN_Msk               (0x1ul << TIMER_CTL_WKEN_Pos)                     /*!< TIMER_T::CTL: WKEN Mask                */
+
+#define TIMER_CTL_EXTCNTEN_Pos           (24)                                              /*!< TIMER_T::CTL: EXTCNTEN Position        */
+#define TIMER_CTL_EXTCNTEN_Msk           (0x1ul << TIMER_CTL_EXTCNTEN_Pos)                 /*!< TIMER_T::CTL: EXTCNTEN Mask            */
+
+#define TIMER_CTL_ACTSTS_Pos             (25)                                              /*!< TIMER_T::CTL: ACTSTS Position          */
+#define TIMER_CTL_ACTSTS_Msk             (0x1ul << TIMER_CTL_ACTSTS_Pos)                   /*!< TIMER_T::CTL: ACTSTS Mask              */
+
+#define TIMER_CTL_OPMODE_Pos             (27)                                              /*!< TIMER_T::CTL: OPMODE Position          */
+#define TIMER_CTL_OPMODE_Msk             (0x3ul << TIMER_CTL_OPMODE_Pos)                   /*!< TIMER_T::CTL: OPMODE Mask              */
+
+#define TIMER_CTL_INTEN_Pos              (29)                                              /*!< TIMER_T::CTL: INTEN Position           */
+#define TIMER_CTL_INTEN_Msk              (0x1ul << TIMER_CTL_INTEN_Pos)                    /*!< TIMER_T::CTL: INTEN Mask               */
+
+#define TIMER_CTL_CNTEN_Pos              (30)                                              /*!< TIMER_T::CTL: CNTEN Position           */
+#define TIMER_CTL_CNTEN_Msk              (0x1ul << TIMER_CTL_CNTEN_Pos)                    /*!< TIMER_T::CTL: CNTEN Mask               */
+
+#define TIMER_CTL_ICEDEBUG_Pos           (31)                                              /*!< TIMER_T::CTL: ICEDEBUG Position        */
+#define TIMER_CTL_ICEDEBUG_Msk           (0x1ul << TIMER_CTL_ICEDEBUG_Pos)                 /*!< TIMER_T::CTL: ICEDEBUG Mask            */
+
+#define TIMER_CMP_CMPDAT_Pos             (0)                                               /*!< TIMER_T::CMP: CMPDAT Position          */
+#define TIMER_CMP_CMPDAT_Msk             (0xfffffful << TIMER_CMP_CMPDAT_Pos)              /*!< TIMER_T::CMP: CMPDAT Mask              */
+
+#define TIMER_INTSTS_TIF_Pos             (0)                                               /*!< TIMER_T::INTSTS: TIF Position          */
+#define TIMER_INTSTS_TIF_Msk             (0x1ul << TIMER_INTSTS_TIF_Pos)                   /*!< TIMER_T::INTSTS: TIF Mask              */
+
+#define TIMER_INTSTS_TWKF_Pos            (1)                                               /*!< TIMER_T::INTSTS: TWKF Position         */
+#define TIMER_INTSTS_TWKF_Msk            (0x1ul << TIMER_INTSTS_TWKF_Pos)                  /*!< TIMER_T::INTSTS: TWKF Mask             */
+
+#define TIMER_CNT_CNT_Pos                (0)                                               /*!< TIMER_T::CNT: CNT Position             */
+#define TIMER_CNT_CNT_Msk                (0xfffffful << TIMER_CNT_CNT_Pos)                 /*!< TIMER_T::CNT: CNT Mask                 */
+
+#define TIMER_CNT_RSTACT_Pos             (31)                                              /*!< TIMER_T::CNT: RSTACT Position          */
+#define TIMER_CNT_RSTACT_Msk             (0x1ul << TIMER_CNT_RSTACT_Pos)                   /*!< TIMER_T::CNT: RSTACT Mask              */
+
+#define TIMER_CAP_CAPDAT_Pos             (0)                                               /*!< TIMER_T::CAP: CAPDAT Position          */
+#define TIMER_CAP_CAPDAT_Msk             (0xfffffful << TIMER_CAP_CAPDAT_Pos)              /*!< TIMER_T::CAP: CAPDAT Mask              */
+
+#define TIMER_EXTCTL_CNTPHASE_Pos        (0)                                               /*!< TIMER_T::EXTCTL: CNTPHASE Position     */
+#define TIMER_EXTCTL_CNTPHASE_Msk        (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos)              /*!< TIMER_T::EXTCTL: CNTPHASE Mask         */
+
+#define TIMER_EXTCTL_CAPEN_Pos           (3)                                               /*!< TIMER_T::EXTCTL: CAPEN Position        */
+#define TIMER_EXTCTL_CAPEN_Msk           (0x1ul << TIMER_EXTCTL_CAPEN_Pos)                 /*!< TIMER_T::EXTCTL: CAPEN Mask            */
+
+#define TIMER_EXTCTL_CAPFUNCS_Pos        (4)                                               /*!< TIMER_T::EXTCTL: CAPFUNCS Position     */
+#define TIMER_EXTCTL_CAPFUNCS_Msk        (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos)              /*!< TIMER_T::EXTCTL: CAPFUNCS Mask         */
+
+#define TIMER_EXTCTL_CAPIEN_Pos          (5)                                               /*!< TIMER_T::EXTCTL: CAPIEN Position       */
+#define TIMER_EXTCTL_CAPIEN_Msk          (0x1ul << TIMER_EXTCTL_CAPIEN_Pos)                /*!< TIMER_T::EXTCTL: CAPIEN Mask           */
+
+#define TIMER_EXTCTL_CAPDBEN_Pos         (6)                                               /*!< TIMER_T::EXTCTL: CAPDBEN Position      */
+#define TIMER_EXTCTL_CAPDBEN_Msk         (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos)               /*!< TIMER_T::EXTCTL: CAPDBEN Mask          */
+
+#define TIMER_EXTCTL_CNTDBEN_Pos         (7)                                               /*!< TIMER_T::EXTCTL: CNTDBEN Position      */
+#define TIMER_EXTCTL_CNTDBEN_Msk         (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos)               /*!< TIMER_T::EXTCTL: CNTDBEN Mask          */
+
+#define TIMER_EXTCTL_INTERCAPSEL_Pos     (8)                                               /*!< TIMER_T::EXTCTL: INTERCAPSEL Position  */
+#define TIMER_EXTCTL_INTERCAPSEL_Msk     (0x7ul << TIMER_EXTCTL_INTERCAPSEL_Pos)           /*!< TIMER_T::EXTCTL: INTERCAPSEL Mask      */
+
+#define TIMER_EXTCTL_CAPEDGE_Pos         (12)                                              /*!< TIMER_T::EXTCTL: CAPEDGE Position      */
+#define TIMER_EXTCTL_CAPEDGE_Msk         (0x7ul << TIMER_EXTCTL_CAPEDGE_Pos)               /*!< TIMER_T::EXTCTL: CAPEDGE Mask          */
+
+#define TIMER_EXTCTL_ECNTSSEL_Pos        (16)                                              /*!< TIMER_T::EXTCTL: ECNTSSEL Position     */
+#define TIMER_EXTCTL_ECNTSSEL_Msk        (0x1ul << TIMER_EXTCTL_ECNTSSEL_Pos)              /*!< TIMER_T::EXTCTL: ECNTSSEL Mask         */
+
+#define TIMER_EXTCTL_CAPDIVSCL_Pos       (28)                                              /*!< TIMER_T::EXTCTL: CAPDIVSCL Position    */
+#define TIMER_EXTCTL_CAPDIVSCL_Msk       (0xful << TIMER_EXTCTL_CAPDIVSCL_Pos)             /*!< TIMER_T::EXTCTL: CAPDIVSCL Mask        */
+
+#define TIMER_EINTSTS_CAPIF_Pos          (0)                                               /*!< TIMER_T::EINTSTS: CAPIF Position       */
+#define TIMER_EINTSTS_CAPIF_Msk          (0x1ul << TIMER_EINTSTS_CAPIF_Pos)                /*!< TIMER_T::EINTSTS: CAPIF Mask           */
+
+#define TIMER_TRGCTL_TRGSSEL_Pos         (0)                                               /*!< TIMER_T::TRGCTL: TRGSSEL Position      */
+#define TIMER_TRGCTL_TRGSSEL_Msk         (0x1ul << TIMER_TRGCTL_TRGSSEL_Pos)               /*!< TIMER_T::TRGCTL: TRGSSEL Mask          */
+
+#define TIMER_TRGCTL_TRGPWM_Pos          (1)                                               /*!< TIMER_T::TRGCTL: TRGPWM Position       */
+#define TIMER_TRGCTL_TRGPWM_Msk          (0x1ul << TIMER_TRGCTL_TRGPWM_Pos)                /*!< TIMER_T::TRGCTL: TRGPWM Mask           */
+
+#define TIMER_TRGCTL_TRGEADC_Pos         (2)                                               /*!< TIMER_T::TRGCTL: TRGEADC Position      */
+#define TIMER_TRGCTL_TRGEADC_Msk         (0x1ul << TIMER_TRGCTL_TRGEADC_Pos)               /*!< TIMER_T::TRGCTL: TRGEADC Mask          */
+
+#define TIMER_TRGCTL_TRGDAC_Pos          (3)                                               /*!< TIMER_T::TRGCTL: TRGDAC Position       */
+#define TIMER_TRGCTL_TRGDAC_Msk          (0x1ul << TIMER_TRGCTL_TRGDAC_Pos)                /*!< TIMER_T::TRGCTL: TRGDAC Mask           */
+
+#define TIMER_TRGCTL_TRGPDMA_Pos         (4)                                               /*!< TIMER_T::TRGCTL: TRGPDMA Position      */
+#define TIMER_TRGCTL_TRGPDMA_Msk         (0x1ul << TIMER_TRGCTL_TRGPDMA_Pos)               /*!< TIMER_T::TRGCTL: TRGPDMA Mask          */
+
+#define TIMER_ALTCTL_FUNCSEL_Pos         (0)                                               /*!< TIMER_T::ALTCTL: FUNCSEL Position      */
+#define TIMER_ALTCTL_FUNCSEL_Msk         (0x1ul << TIMER_ALTCTL_FUNCSEL_Pos)               /*!< TIMER_T::ALTCTL: FUNCSEL Mask          */
+
+#define TIMER_PWMCTL_CNTEN_Pos           (0)                                               /*!< TIMER_T::PWMCTL: CNTEN Position        */
+#define TIMER_PWMCTL_CNTEN_Msk           (0x1ul << TIMER_PWMCTL_CNTEN_Pos)                 /*!< TIMER_T::PWMCTL: CNTEN Mask            */
+
+#define TIMER_PWMCTL_CNTTYPE_Pos         (1)                                               /*!< TIMER_T::PWMCTL: CNTTYPE Position      */
+#define TIMER_PWMCTL_CNTTYPE_Msk         (0x3ul << TIMER_PWMCTL_CNTTYPE_Pos)               /*!< TIMER_T::PWMCTL: CNTTYPE Mask          */
+
+#define TIMER_PWMCTL_CNTMODE_Pos         (3)                                               /*!< TIMER_T::PWMCTL: CNTMODE Position      */
+#define TIMER_PWMCTL_CNTMODE_Msk         (0x1ul << TIMER_PWMCTL_CNTMODE_Pos)               /*!< TIMER_T::PWMCTL: CNTMODE Mask          */
+
+#define TIMER_PWMCTL_CTRLD_Pos           (8)                                               /*!< TIMER_T::PWMCTL: CTRLD Position        */
+#define TIMER_PWMCTL_CTRLD_Msk           (0x1ul << TIMER_PWMCTL_CTRLD_Pos)                 /*!< TIMER_T::PWMCTL: CTRLD Mask            */
+
+#define TIMER_PWMCTL_IMMLDEN_Pos         (9)                                               /*!< TIMER_T::PWMCTL: IMMLDEN Position      */
+#define TIMER_PWMCTL_IMMLDEN_Msk         (0x1ul << TIMER_PWMCTL_IMMLDEN_Pos)               /*!< TIMER_T::PWMCTL: IMMLDEN Mask          */
+
+#define TIMER_PWMCTL_WKEN_Pos            (12)                                              /*!< TIMER_T::PWMCTL: WKEN Position         */
+#define TIMER_PWMCTL_WKEN_Msk            (0x1ul << TIMER_PWMCTL_WKEN_Pos)                  /*!< TIMER_T::PWMCTL: WKEN Mask             */
+
+#define TIMER_PWMCTL_OUTMODE_Pos         (16)                                              /*!< TIMER_T::PWMCTL: OUTMODE Position      */
+#define TIMER_PWMCTL_OUTMODE_Msk         (0x1ul << TIMER_PWMCTL_OUTMODE_Pos)               /*!< TIMER_T::PWMCTL: OUTMODE Mask          */
+
+#define TIMER_PWMCTL_DBGHALT_Pos         (30)                                              /*!< TIMER_T::PWMCTL: DBGHALT Position      */
+#define TIMER_PWMCTL_DBGHALT_Msk         (0x1ul << TIMER_PWMCTL_DBGHALT_Pos)               /*!< TIMER_T::PWMCTL: DBGHALT Mask          */
+
+#define TIMER_PWMCTL_DBGTRIOFF_Pos       (31)                                              /*!< TIMER_T::PWMCTL: DBGTRIOFF Position    */
+#define TIMER_PWMCTL_DBGTRIOFF_Msk       (0x1ul << TIMER_PWMCTL_DBGTRIOFF_Pos)             /*!< TIMER_T::PWMCTL: DBGTRIOFF Mask        */
+
+#define TIMER_PWMCLKSRC_CLKSRC_Pos       (0)                                               /*!< TIMER_T::PWMCLKSRC: CLKSRC Position    */
+#define TIMER_PWMCLKSRC_CLKSRC_Msk       (0x7ul << TIMER_PWMCLKSRC_CLKSRC_Pos)             /*!< TIMER_T::PWMCLKSRC: CLKSRC Mask        */
+
+#define TIMER_PWMCLKPSC_CLKPSC_Pos       (0)                                               /*!< TIMER_T::PWMCLKPSC: CLKPSC Position    */
+#define TIMER_PWMCLKPSC_CLKPSC_Msk       (0xffful << TIMER_PWMCLKPSC_CLKPSC_Pos)           /*!< TIMER_T::PWMCLKPSC: CLKPSC Mask        */
+
+#define TIMER_PWMCNTCLR_CNTCLR_Pos       (0)                                               /*!< TIMER_T::PWMCNTCLR: CNTCLR Position    */
+#define TIMER_PWMCNTCLR_CNTCLR_Msk       (0x1ul << TIMER_PWMCNTCLR_CNTCLR_Pos)             /*!< TIMER_T::PWMCNTCLR: CNTCLR Mask        */
+
+#define TIMER_PWMPERIOD_PERIOD_Pos       (0)                                               /*!< TIMER_T::PWMPERIOD: PERIOD Position    */
+#define TIMER_PWMPERIOD_PERIOD_Msk       (0xfffful << TIMER_PWMPERIOD_PERIOD_Pos)          /*!< TIMER_T::PWMPERIOD: PERIOD Mask        */
+
+#define TIMER_PWMCMPDAT_CMP_Pos          (0)                                               /*!< TIMER_T::PWMCMPDAT: CMP Position       */
+#define TIMER_PWMCMPDAT_CMP_Msk          (0xfffful << TIMER_PWMCMPDAT_CMP_Pos)             /*!< TIMER_T::PWMCMPDAT: CMP Mask           */
+
+#define TIMER_PWMDTCTL_DTCNT_Pos         (0)                                               /*!< TIMER_T::PWMDTCTL: DTCNT Position      */
+#define TIMER_PWMDTCTL_DTCNT_Msk         (0xffful << TIMER_PWMDTCTL_DTCNT_Pos)             /*!< TIMER_T::PWMDTCTL: DTCNT Mask          */
+
+#define TIMER_PWMDTCTL_DTEN_Pos          (16)                                              /*!< TIMER_T::PWMDTCTL: DTEN Position       */
+#define TIMER_PWMDTCTL_DTEN_Msk          (0x1ul << TIMER_PWMDTCTL_DTEN_Pos)                /*!< TIMER_T::PWMDTCTL: DTEN Mask           */
+
+#define TIMER_PWMDTCTL_DTCKSEL_Pos       (24)                                              /*!< TIMER_T::PWMDTCTL: DTCKSEL Position    */
+#define TIMER_PWMDTCTL_DTCKSEL_Msk       (0x1ul << TIMER_PWMDTCTL_DTCKSEL_Pos)             /*!< TIMER_T::PWMDTCTL: DTCKSEL Mask        */
+
+#define TIMER_PWMCNT_CNT_Pos             (0)                                               /*!< TIMER_T::PWMCNT: CNT Position          */
+#define TIMER_PWMCNT_CNT_Msk             (0xfffful << TIMER_PWMCNT_CNT_Pos)                /*!< TIMER_T::PWMCNT: CNT Mask              */
+
+#define TIMER_PWMCNT_DIRF_Pos            (16)                                              /*!< TIMER_T::PWMCNT: DIRF Position         */
+#define TIMER_PWMCNT_DIRF_Msk            (0x1ul << TIMER_PWMCNT_DIRF_Pos)                  /*!< TIMER_T::PWMCNT: DIRF Mask             */
+
+#define TIMER_PWMMSKEN_MSKEN0_Pos        (0)                                               /*!< TIMER_T::PWMMSKEN: MSKEN0 Position     */
+#define TIMER_PWMMSKEN_MSKEN0_Msk        (0x1ul << TIMER_PWMMSKEN_MSKEN0_Pos)              /*!< TIMER_T::PWMMSKEN: MSKEN0 Mask         */
+
+#define TIMER_PWMMSKEN_MSKEN1_Pos        (1)                                               /*!< TIMER_T::PWMMSKEN: MSKEN1 Position     */
+#define TIMER_PWMMSKEN_MSKEN1_Msk        (0x1ul << TIMER_PWMMSKEN_MSKEN1_Pos)              /*!< TIMER_T::PWMMSKEN: MSKEN1 Mask         */
+
+#define TIMER_PWMMSK_MSKDAT0_Pos         (0)                                               /*!< TIMER_T::PWMMSK: MSKDAT0 Position      */
+#define TIMER_PWMMSK_MSKDAT0_Msk         (0x1ul << TIMER_PWMMSK_MSKDAT0_Pos)               /*!< TIMER_T::PWMMSK: MSKDAT0 Mask          */
+
+#define TIMER_PWMMSK_MSKDAT1_Pos         (1)                                               /*!< TIMER_T::PWMMSK: MSKDAT1 Position      */
+#define TIMER_PWMMSK_MSKDAT1_Msk         (0x1ul << TIMER_PWMMSK_MSKDAT1_Pos)               /*!< TIMER_T::PWMMSK: MSKDAT1 Mask          */
+
+#define TIMER_PWMBNF_BRKNFEN_Pos         (0)                                               /*!< TIMER_T::PWMBNF: BRKNFEN Position      */
+#define TIMER_PWMBNF_BRKNFEN_Msk         (0x1ul << TIMER_PWMBNF_BRKNFEN_Pos)               /*!< TIMER_T::PWMBNF: BRKNFEN Mask          */
+
+#define TIMER_PWMBNF_BRKNFSEL_Pos        (1)                                               /*!< TIMER_T::PWMBNF: BRKNFSEL Position     */
+#define TIMER_PWMBNF_BRKNFSEL_Msk        (0x7ul << TIMER_PWMBNF_BRKNFSEL_Pos)              /*!< TIMER_T::PWMBNF: BRKNFSEL Mask         */
+
+#define TIMER_PWMBNF_BRKFCNT_Pos         (4)                                               /*!< TIMER_T::PWMBNF: BRKFCNT Position      */
+#define TIMER_PWMBNF_BRKFCNT_Msk         (0x7ul << TIMER_PWMBNF_BRKFCNT_Pos)               /*!< TIMER_T::PWMBNF: BRKFCNT Mask          */
+
+#define TIMER_PWMBNF_BRKPINV_Pos         (7)                                               /*!< TIMER_T::PWMBNF: BRKPINV Position      */
+#define TIMER_PWMBNF_BRKPINV_Msk         (0x1ul << TIMER_PWMBNF_BRKPINV_Pos)               /*!< TIMER_T::PWMBNF: BRKPINV Mask          */
+
+#define TIMER_PWMBNF_BKPINSRC_Pos        (16)                                              /*!< TIMER_T::PWMBNF: BKPINSRC Position     */
+#define TIMER_PWMBNF_BKPINSRC_Msk        (0x3ul << TIMER_PWMBNF_BKPINSRC_Pos)              /*!< TIMER_T::PWMBNF: BKPINSRC Mask         */
+
+#define TIMER_PWMFAILBRK_CSSBRKEN_Pos    (0)                                               /*!< TIMER_T::PWMFAILBRK: CSSBRKEN Position */
+#define TIMER_PWMFAILBRK_CSSBRKEN_Msk    (0x1ul << TIMER_PWMFAILBRK_CSSBRKEN_Pos)          /*!< TIMER_T::PWMFAILBRK: CSSBRKEN Mask     */
+
+#define TIMER_PWMFAILBRK_BODBRKEN_Pos    (1)                                               /*!< TIMER_T::PWMFAILBRK: BODBRKEN Position */
+#define TIMER_PWMFAILBRK_BODBRKEN_Msk    (0x1ul << TIMER_PWMFAILBRK_BODBRKEN_Pos)          /*!< TIMER_T::PWMFAILBRK: BODBRKEN Mask     */
+
+#define TIMER_PWMFAILBRK_RAMBRKEN_Pos    (2)                                               /*!< TIMER_T::PWMFAILBRK: RAMBRKEN Position */
+#define TIMER_PWMFAILBRK_RAMBRKEN_Msk    (0x1ul << TIMER_PWMFAILBRK_RAMBRKEN_Pos)          /*!< TIMER_T::PWMFAILBRK: RAMBRKEN Mask     */
+
+#define TIMER_PWMFAILBRK_CORBRKEN_Pos    (3)                                               /*!< TIMER_T::PWMFAILBRK: CORBRKEN Position */
+#define TIMER_PWMFAILBRK_CORBRKEN_Msk    (0x1ul << TIMER_PWMFAILBRK_CORBRKEN_Pos)          /*!< TIMER_T::PWMFAILBRK: CORBRKEN Mask     */
+
+#define TIMER_PWMBRKCTL_CPO0EBEN_Pos     (0)                                               /*!< TIMER_T::PWMBRKCTL: CPO0EBEN Position  */
+#define TIMER_PWMBRKCTL_CPO0EBEN_Msk     (0x1ul << TIMER_PWMBRKCTL_CPO0EBEN_Pos)           /*!< TIMER_T::PWMBRKCTL: CPO0EBEN Mask      */
+
+#define TIMER_PWMBRKCTL_CPO1EBEN_Pos     (1)                                               /*!< TIMER_T::PWMBRKCTL: CPO1EBEN Position  */
+#define TIMER_PWMBRKCTL_CPO1EBEN_Msk     (0x1ul << TIMER_PWMBRKCTL_CPO1EBEN_Pos)           /*!< TIMER_T::PWMBRKCTL: CPO1EBEN Mask      */
+
+#define TIMER_PWMBRKCTL_BRKPEEN_Pos      (4)                                               /*!< TIMER_T::PWMBRKCTL: BRKPEEN Position   */
+#define TIMER_PWMBRKCTL_BRKPEEN_Msk      (0x1ul << TIMER_PWMBRKCTL_BRKPEEN_Pos)            /*!< TIMER_T::PWMBRKCTL: BRKPEEN Mask       */
+
+#define TIMER_PWMBRKCTL_SYSEBEN_Pos      (7)                                               /*!< TIMER_T::PWMBRKCTL: SYSEBEN Position   */
+#define TIMER_PWMBRKCTL_SYSEBEN_Msk      (0x1ul << TIMER_PWMBRKCTL_SYSEBEN_Pos)            /*!< TIMER_T::PWMBRKCTL: SYSEBEN Mask       */
+
+#define TIMER_PWMBRKCTL_CPO0LBEN_Pos     (8)                                               /*!< TIMER_T::PWMBRKCTL: CPO0LBEN Position  */
+#define TIMER_PWMBRKCTL_CPO0LBEN_Msk     (0x1ul << TIMER_PWMBRKCTL_CPO0LBEN_Pos)           /*!< TIMER_T::PWMBRKCTL: CPO0LBEN Mask      */
+
+#define TIMER_PWMBRKCTL_CPO1LBEN_Pos     (9)                                               /*!< TIMER_T::PWMBRKCTL: CPO1LBEN Position  */
+#define TIMER_PWMBRKCTL_CPO1LBEN_Msk     (0x1ul << TIMER_PWMBRKCTL_CPO1LBEN_Pos)           /*!< TIMER_T::PWMBRKCTL: CPO1LBEN Mask      */
+
+#define TIMER_PWMBRKCTL_BRKPLEN_Pos      (12)                                              /*!< TIMER_T::PWMBRKCTL: BRKPLEN Position   */
+#define TIMER_PWMBRKCTL_BRKPLEN_Msk      (0x1ul << TIMER_PWMBRKCTL_BRKPLEN_Pos)            /*!< TIMER_T::PWMBRKCTL: BRKPLEN Mask       */
+
+#define TIMER_PWMBRKCTL_SYSLBEN_Pos      (15)                                              /*!< TIMER_T::PWMBRKCTL: SYSLBEN Position   */
+#define TIMER_PWMBRKCTL_SYSLBEN_Msk      (0x1ul << TIMER_PWMBRKCTL_SYSLBEN_Pos)            /*!< TIMER_T::PWMBRKCTL: SYSLBEN Mask       */
+
+#define TIMER_PWMBRKCTL_BRKAEVEN_Pos     (16)                                              /*!< TIMER_T::PWMBRKCTL: BRKAEVEN Position  */
+#define TIMER_PWMBRKCTL_BRKAEVEN_Msk     (0x3ul << TIMER_PWMBRKCTL_BRKAEVEN_Pos)           /*!< TIMER_T::PWMBRKCTL: BRKAEVEN Mask      */
+
+#define TIMER_PWMBRKCTL_BRKAODD_Pos      (18)                                              /*!< TIMER_T::PWMBRKCTL: BRKAODD Position   */
+#define TIMER_PWMBRKCTL_BRKAODD_Msk      (0x3ul << TIMER_PWMBRKCTL_BRKAODD_Pos)            /*!< TIMER_T::PWMBRKCTL: BRKAODD Mask       */
+
+#define TIMER_PWMPOLCTL_PINV0_Pos        (0)                                               /*!< TIMER_T::PWMPOLCTL: PINV0 Position     */
+#define TIMER_PWMPOLCTL_PINV0_Msk        (0x1ul << TIMER_PWMPOLCTL_PINV0_Pos)              /*!< TIMER_T::PWMPOLCTL: PINV0 Mask         */
+
+#define TIMER_PWMPOLCTL_PINV1_Pos        (1)                                               /*!< TIMER_T::PWMPOLCTL: PINV1 Position     */
+#define TIMER_PWMPOLCTL_PINV1_Msk        (0x1ul << TIMER_PWMPOLCTL_PINV1_Pos)              /*!< TIMER_T::PWMPOLCTL: PINV1 Mask         */
+
+#define TIMER_PWMPOEN_POEN0_Pos          (0)                                               /*!< TIMER_T::PWMPOEN: POEN0 Position       */
+#define TIMER_PWMPOEN_POEN0_Msk          (0x1ul << TIMER_PWMPOEN_POEN0_Pos)                /*!< TIMER_T::PWMPOEN: POEN0 Mask           */
+
+#define TIMER_PWMPOEN_POEN1_Pos          (1)                                               /*!< TIMER_T::PWMPOEN: POEN1 Position       */
+#define TIMER_PWMPOEN_POEN1_Msk          (0x1ul << TIMER_PWMPOEN_POEN1_Pos)                /*!< TIMER_T::PWMPOEN: POEN1 Mask           */
+
+#define TIMER_PWMPOEN_POSEL_Pos          (8)                                               /*!< TIMER_T::PWMPOEN: POSEL Position       */
+#define TIMER_PWMPOEN_POSEL_Msk          (0x1ul << TIMER_PWMPOEN_POSEL_Pos)                /*!< TIMER_T::PWMPOEN: POSEL Mask           */
+
+#define TIMER_PWMSWBRK_BRKETRG_Pos       (0)                                               /*!< TIMER_T::PWMSWBRK: BRKETRG Position    */
+#define TIMER_PWMSWBRK_BRKETRG_Msk       (0x1ul << TIMER_PWMSWBRK_BRKETRG_Pos)             /*!< TIMER_T::PWMSWBRK: BRKETRG Mask        */
+
+#define TIMER_PWMSWBRK_BRKLTRG_Pos       (8)                                               /*!< TIMER_T::PWMSWBRK: BRKLTRG Position    */
+#define TIMER_PWMSWBRK_BRKLTRG_Msk       (0x1ul << TIMER_PWMSWBRK_BRKLTRG_Pos)             /*!< TIMER_T::PWMSWBRK: BRKLTRG Mask        */
+
+#define TIMER_PWMINTEN0_ZIEN_Pos         (0)                                               /*!< TIMER_T::PWMINTEN0: ZIEN Position      */
+#define TIMER_PWMINTEN0_ZIEN_Msk         (0x1ul << TIMER_PWMINTEN0_ZIEN_Pos)               /*!< TIMER_T::PWMINTEN0: ZIEN Mask          */
+
+#define TIMER_PWMINTEN0_PIEN_Pos         (1)                                               /*!< TIMER_T::PWMINTEN0: PIEN Position      */
+#define TIMER_PWMINTEN0_PIEN_Msk         (0x1ul << TIMER_PWMINTEN0_PIEN_Pos)               /*!< TIMER_T::PWMINTEN0: PIEN Mask          */
+
+#define TIMER_PWMINTEN0_CMPUIEN_Pos      (2)                                               /*!< TIMER_T::PWMINTEN0: CMPUIEN Position   */
+#define TIMER_PWMINTEN0_CMPUIEN_Msk      (0x1ul << TIMER_PWMINTEN0_CMPUIEN_Pos)            /*!< TIMER_T::PWMINTEN0: CMPUIEN Mask       */
+
+#define TIMER_PWMINTEN0_CMPDIEN_Pos      (3)                                               /*!< TIMER_T::PWMINTEN0: CMPDIEN Position   */
+#define TIMER_PWMINTEN0_CMPDIEN_Msk      (0x1ul << TIMER_PWMINTEN0_CMPDIEN_Pos)            /*!< TIMER_T::PWMINTEN0: CMPDIEN Mask       */
+
+#define TIMER_PWMINTEN1_BRKEIEN_Pos      (0)                                               /*!< TIMER_T::PWMINTEN1: BRKEIEN Position   */
+#define TIMER_PWMINTEN1_BRKEIEN_Msk      (0x1ul << TIMER_PWMINTEN1_BRKEIEN_Pos)            /*!< TIMER_T::PWMINTEN1: BRKEIEN Mask       */
+
+#define TIMER_PWMINTEN1_BRKLIEN_Pos      (8)                                               /*!< TIMER_T::PWMINTEN1: BRKLIEN Position   */
+#define TIMER_PWMINTEN1_BRKLIEN_Msk      (0x1ul << TIMER_PWMINTEN1_BRKLIEN_Pos)            /*!< TIMER_T::PWMINTEN1: BRKLIEN Mask       */
+
+#define TIMER_PWMINTSTS0_ZIF_Pos         (0)                                               /*!< TIMER_T::PWMINTSTS0: ZIF Position      */
+#define TIMER_PWMINTSTS0_ZIF_Msk         (0x1ul << TIMER_PWMINTSTS0_ZIF_Pos)               /*!< TIMER_T::PWMINTSTS0: ZIF Mask          */
+
+#define TIMER_PWMINTSTS0_PIF_Pos         (1)                                               /*!< TIMER_T::PWMINTSTS0: PIF Position      */
+#define TIMER_PWMINTSTS0_PIF_Msk         (0x1ul << TIMER_PWMINTSTS0_PIF_Pos)               /*!< TIMER_T::PWMINTSTS0: PIF Mask          */
+
+#define TIMER_PWMINTSTS0_CMPUIF_Pos      (2)                                               /*!< TIMER_T::PWMINTSTS0: CMPUIF Position   */
+#define TIMER_PWMINTSTS0_CMPUIF_Msk      (0x1ul << TIMER_PWMINTSTS0_CMPUIF_Pos)            /*!< TIMER_T::PWMINTSTS0: CMPUIF Mask       */
+
+#define TIMER_PWMINTSTS0_CMPDIF_Pos      (3)                                               /*!< TIMER_T::PWMINTSTS0: CMPDIF Position   */
+#define TIMER_PWMINTSTS0_CMPDIF_Msk      (0x1ul << TIMER_PWMINTSTS0_CMPDIF_Pos)            /*!< TIMER_T::PWMINTSTS0: CMPDIF Mask       */
+
+#define TIMER_PWMINTSTS1_BRKEIF0_Pos     (0)                                               /*!< TIMER_T::PWMINTSTS1: BRKEIF0 Position  */
+#define TIMER_PWMINTSTS1_BRKEIF0_Msk     (0x1ul << TIMER_PWMINTSTS1_BRKEIF0_Pos)           /*!< TIMER_T::PWMINTSTS1: BRKEIF0 Mask      */
+
+#define TIMER_PWMINTSTS1_BRKEIF1_Pos     (1)                                               /*!< TIMER_T::PWMINTSTS1: BRKEIF1 Position  */
+#define TIMER_PWMINTSTS1_BRKEIF1_Msk     (0x1ul << TIMER_PWMINTSTS1_BRKEIF1_Pos)           /*!< TIMER_T::PWMINTSTS1: BRKEIF1 Mask      */
+
+#define TIMER_PWMINTSTS1_BRKLIF0_Pos     (8)                                               /*!< TIMER_T::PWMINTSTS1: BRKLIF0 Position  */
+#define TIMER_PWMINTSTS1_BRKLIF0_Msk     (0x1ul << TIMER_PWMINTSTS1_BRKLIF0_Pos)           /*!< TIMER_T::PWMINTSTS1: BRKLIF0 Mask      */
+
+#define TIMER_PWMINTSTS1_BRKLIF1_Pos     (9)                                               /*!< TIMER_T::PWMINTSTS1: BRKLIF1 Position  */
+#define TIMER_PWMINTSTS1_BRKLIF1_Msk     (0x1ul << TIMER_PWMINTSTS1_BRKLIF1_Pos)           /*!< TIMER_T::PWMINTSTS1: BRKLIF1 Mask      */
+
+#define TIMER_PWMINTSTS1_BRKESTS0_Pos    (16)                                              /*!< TIMER_T::PWMINTSTS1: BRKESTS0 Position */
+#define TIMER_PWMINTSTS1_BRKESTS0_Msk    (0x1ul << TIMER_PWMINTSTS1_BRKESTS0_Pos)          /*!< TIMER_T::PWMINTSTS1: BRKESTS0 Mask     */
+
+#define TIMER_PWMINTSTS1_BRKESTS1_Pos    (17)                                              /*!< TIMER_T::PWMINTSTS1: BRKESTS1 Position */
+#define TIMER_PWMINTSTS1_BRKESTS1_Msk    (0x1ul << TIMER_PWMINTSTS1_BRKESTS1_Pos)          /*!< TIMER_T::PWMINTSTS1: BRKESTS1 Mask     */
+
+#define TIMER_PWMINTSTS1_BRKLSTS0_Pos    (24)                                              /*!< TIMER_T::PWMINTSTS1: BRKLSTS0 Position */
+#define TIMER_PWMINTSTS1_BRKLSTS0_Msk    (0x1ul << TIMER_PWMINTSTS1_BRKLSTS0_Pos)          /*!< TIMER_T::PWMINTSTS1: BRKLSTS0 Mask     */
+
+#define TIMER_PWMINTSTS1_BRKLSTS1_Pos    (25)                                              /*!< TIMER_T::PWMINTSTS1: BRKLSTS1 Position */
+#define TIMER_PWMINTSTS1_BRKLSTS1_Msk    (0x1ul << TIMER_PWMINTSTS1_BRKLSTS1_Pos)          /*!< TIMER_T::PWMINTSTS1: BRKLSTS1 Mask     */
+
+#define TIMER_PWMTRGCTL_TRGSEL_Pos       (0)                                               /*!< TIMER_T::PWMTRGCTL: TRGSEL Position    */
+#define TIMER_PWMTRGCTL_TRGSEL_Msk       (0x7ul << TIMER_PWMTRGCTL_TRGSEL_Pos)             /*!< TIMER_T::PWMTRGCTL: TRGSEL Mask        */
+
+#define TIMER_PWMTRGCTL_TRGEADC_Pos      (7)                                               /*!< TIMER_T::PWMTRGCTL: TRGEADC Position   */
+#define TIMER_PWMTRGCTL_TRGEADC_Msk      (0x1ul << TIMER_PWMTRGCTL_TRGEADC_Pos)            /*!< TIMER_T::PWMTRGCTL: TRGEADC Mask       */
+
+#define TIMER_PWMTRGCTL_TRGPDMA_Pos      (9)                                               /*!< TIMER_T::PWMTRGCTL: TRGPDMA Position   */
+#define TIMER_PWMTRGCTL_TRGPDMA_Msk      (0x1ul << TIMER_PWMTRGCTL_TRGPDMA_Pos)            /*!< TIMER_T::PWMTRGCTL: TRGPDMA Mask       */
+
+#define TIMER_PWMSCTL_SYNCMODE_Pos       (0)                                               /*!< TIMER_T::PWMSCTL: SYNCMODE Position    */
+#define TIMER_PWMSCTL_SYNCMODE_Msk       (0x3ul << TIMER_PWMSCTL_SYNCMODE_Pos)             /*!< TIMER_T::PWMSCTL: SYNCMODE Mask        */
+
+#define TIMER_PWMSCTL_SYNCSRC_Pos        (8)                                               /*!< TIMER_T::PWMSCTL: SYNCSRC Position     */
+#define TIMER_PWMSCTL_SYNCSRC_Msk        (0x1ul << TIMER_PWMSCTL_SYNCSRC_Pos)              /*!< TIMER_T::PWMSCTL: SYNCSRC Mask         */
+
+#define TIMER_PWMSTRG_STRGEN_Pos         (0)                                               /*!< TIMER_T::PWMSTRG: STRGEN Position      */
+#define TIMER_PWMSTRG_STRGEN_Msk         (0x1ul << TIMER_PWMSTRG_STRGEN_Pos)               /*!< TIMER_T::PWMSTRG: STRGEN Mask          */
+
+#define TIMER_PWMSTATUS_CNTMAXF_Pos      (0)                                               /*!< TIMER_T::PWMSTATUS: CNTMAXF Position   */
+#define TIMER_PWMSTATUS_CNTMAXF_Msk      (0x1ul << TIMER_PWMSTATUS_CNTMAXF_Pos)            /*!< TIMER_T::PWMSTATUS: CNTMAXF Mask       */
+
+#define TIMER_PWMSTATUS_WKF_Pos          (8)                                               /*!< TIMER_T::PWMSTATUS: WKF Position       */
+#define TIMER_PWMSTATUS_WKF_Msk          (0x1ul << TIMER_PWMSTATUS_WKF_Pos)                /*!< TIMER_T::PWMSTATUS: WKF Mask           */
+
+#define TIMER_PWMSTATUS_EADCTRGF_Pos     (16)                                              /*!< TIMER_T::PWMSTATUS: EADCTRGF Position  */
+#define TIMER_PWMSTATUS_EADCTRGF_Msk     (0x1ul << TIMER_PWMSTATUS_EADCTRGF_Pos)           /*!< TIMER_T::PWMSTATUS: EADCTRGF Mask      */
+
+#define TIMER_PWMSTATUS_PDMATRGF_Pos     (18)                                              /*!< TIMER_T::PWMSTATUS: PDMATRGF Position  */
+#define TIMER_PWMSTATUS_PDMATRGF_Msk     (0x1ul << TIMER_PWMSTATUS_PDMATRGF_Pos)           /*!< TIMER_T::PWMSTATUS: PDMATRGF Mask      */
+
+#define TIMER_PWMPBUF_PBUF_Pos           (0)                                               /*!< TIMER_T::PWMPBUF: PBUF Position        */
+#define TIMER_PWMPBUF_PBUF_Msk           (0xfffful << TIMER_PWMPBUF_PBUF_Pos)              /*!< TIMER_T::PWMPBUF: PBUF Mask            */
+
+#define TIMER_PWMCMPBUF_CMPBUF_Pos       (0)                                               /*!< TIMER_T::PWMCMPBUF: CMPBUF Position    */
+#define TIMER_PWMCMPBUF_CMPBUF_Msk       (0xfffful << TIMER_PWMCMPBUF_CMPBUF_Pos)          /*!< TIMER_T::PWMCMPBUF: CMPBUF Mask        */
+
+/**@}*/ /* TIMER_CONST */
+/**@}*/ /* end of TIMER register group */
+/**@}*/ /* end of REGISTER group */
+
+#endif /* __TIMER_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/trng_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/trng_reg.h
new file mode 100644
index 0000000000..a10ecfc318
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/trng_reg.h
@@ -0,0 +1,156 @@
+/**************************************************************************//**
+ * @file     trng_reg.h
+ * @version  V1.00
+ * @brief    TRNG register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __TRNG_REG_H__
+#define __TRNG_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+/*---------------------- True Random Number Generator -------------------------*/
+/**
+    @addtogroup TRNG True Random Number Generator(TRNG)
+    Memory Mapped Structure for TRNG Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var TRNG_T::CTL
+     * Offset: 0x00  TRNG Control Register and Status
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |TRNGEN    |Random Number Generator Enable Bit
+     * |        |          |This bit can be set to 1 only after ACT (TRNG_ACT[7]) bit was set to 1 and READY (TRNG_CTL[7]) bit became to 1.
+     * |        |          |0 = TRNG Disabled.
+     * |        |          |1 = TRNG Enabled.
+     * |        |          |Note: TRNGEN is an enable bit of digital part
+     * |        |          |When TRNG is not required to generate random number, TRNGEN bit and ACT (TRNG_ACT[7]) bit should be set to 0 to reduce power consumption.
+     * |[1]     |DVIF      |Data Valid (Read Only)
+     * |        |          |0 = Data is not valid. Reading from RNGD returns 0x00000000.
+     * |        |          |1 = Data is valid. A valid random number can be read form RNGD.
+     * |        |          |This bit is cleared to u20180u2019 by read TRNG_DATA.
+     * |[5:2]   |CLKPSC    |Clock Prescaler
+     * |        |          |The CLKP is the peripheral clock frequency range for the selected value , the CLKP must higher than or equal to the actual peripheral clock frequency (for correct random bit generation)
+     * |        |          |To change the CLKP contents, first set TRNGEN bit to 0 and then change CLKP; finally, set TRNGEN bit to 1 to re-enable the TRNG module.
+     * |        |          |0000 = 80 ~ 100 MHz.
+     * |        |          |0001 = 60 ~ 80 MHz.
+     * |        |          |0010 = 50 ~60 MHz.
+     * |        |          |0011 = 40 ~50 MHz.
+     * |        |          |0100 = 30 ~40 MHz.
+     * |        |          |0101 = 25 ~30 MHz.
+     * |        |          |0110 = 20 ~25 MHz.
+     * |        |          |0111 = 15 ~20 MHz.
+     * |        |          |1000 = 12 ~15 MHz.
+     * |        |          |1001 = 9 ~12 MHz.
+     * |        |          |1010 = 7 ~9 MHz.
+     * |        |          |1011 = 6 ~7 MHz.
+     * |        |          |1100 = 5 ~6 MHz.
+     * |        |          |1101 = 4 ~5 MHz.
+     * |        |          |1111 = Reserved.
+     * |[6]     |DVIEN     |Data Valid Interrupt Enable Bit
+     * |        |          |0 = Interrupt Disabled.
+     * |        |          |1 = Interrupt Enabled.
+     * |[7]     |READY     |Random Number Generator Ready (Read Only)
+     * |        |          |After ACT (TRNG_ACT[7]) bit is set, the READY bit become to 1 after a delay of 90us~120us.
+     * |        |          |0 = RNG is not ready or was not activated.
+     * |        |          |1 = RNG is ready to be enabled..
+     * |[8]     |SEEDGEN   |Random Number Seed Generator Enable Bit [for TRNG+PRNG]
+     * |        |          |This bit can be set to 1 only after ACT (TRNG_ACT[7]) bit was set to 1 and READY (TRNG_CTL[7]) bit became to 1.
+     * |        |          |0 = Seed generator disabled.
+     * |        |          |1 = Seed generator enabled.
+     * |        |          |Note: If users want to execute TRNG+PRNG mode, they should set SEEDGEN to 1
+     * |        |          |When SEEDGEN was set to 1, users canu2019t read the data from TRNG Data Register.
+     * |[9]     |SEEDRDY   |Random Number Seed Ready (Read Only) [for TRNG+PRNG]
+     * |        |          |0 = Seed is not ready or was not activated.
+     * |        |          |1 = Seed is ready for PRNG.
+     * |        |          |Note 1:This bit is cleared to u20180u2019 when SEEDGEN is 1.
+     * |        |          |Note 2: If SEEDRDY become to 1, then SEEDGEN will be cleared to 0.
+     * |[31:10] |Reversed  |Reversed
+     * @var TRNG_T::DATA
+     * Offset: 0x04  TRNG Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |DATA      |Random Number Generator Data (Read Only)
+     * |        |          |The DATA store the random number generated by TRNG and can be read only once.
+     * @var TRNG_T::ACT
+     * Offset: 0x0C  TRNG Activation Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[6:0]   |VER       |TRNG Version
+     * |        |          |TRNG version number is dependent on TRNG module.
+     * |        |          |0x02:(Current Version Number)
+     * |[7]     |ACT       |Random Number Generator Activation
+     * |        |          |After enabling the ACT bit, it will active the TRNG module and wait the READY (TRNG_CTL[7]) bit to become 1.
+     * |        |          |0 = TRNG inactive.
+     * |        |          |1 = TRNG active.
+     * |        |          |Note: ACT is an enable bit of analog part
+     * |        |          |When TRNG is not required to generate random number, TRNGEN (TRNG_CTL[0]) bit and ACT bit should be set to 0 to reduce power consumption.
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] TRNG Control Register and Status                                 */
+    __I  uint32_t DATA;                  /*!< [0x0004] TRNG Data Register                                               */
+    __I  uint32_t RESERVE0[1];
+    __IO uint32_t ACT;                   /*!< [0x000c] TRNG Activation Register                                         */
+
+} TRNG_T;
+
+/**
+    @addtogroup TRNG_CONST TRNG Bit Field Definition
+    Constant Definitions for TRNG Controller
+  @{
+*/
+
+#define TRNG_CTL_TRNGEN_Pos              (0)                                               /*!< TRNG_T::CTL: TRNGEN Position           */
+#define TRNG_CTL_TRNGEN_Msk              (0x1ul << TRNG_CTL_TRNGEN_Pos)                    /*!< TRNG_T::CTL: TRNGEN Mask               */
+
+#define TRNG_CTL_DVIF_Pos                (1)                                               /*!< TRNG_T::CTL: DVIF Position             */
+#define TRNG_CTL_DVIF_Msk                (0x1ul << TRNG_CTL_DVIF_Pos)                      /*!< TRNG_T::CTL: DVIF Mask                 */
+
+#define TRNG_CTL_CLKPSC_Pos              (2)                                               /*!< TRNG_T::CTL: CLKPSC Position           */
+#define TRNG_CTL_CLKPSC_Msk              (0xful << TRNG_CTL_CLKPSC_Pos)                    /*!< TRNG_T::CTL: CLKPSC Mask               */
+
+#define TRNG_CTL_DVIEN_Pos               (6)                                               /*!< TRNG_T::CTL: DVIEN Position            */
+#define TRNG_CTL_DVIEN_Msk               (0x1ul << TRNG_CTL_DVIEN_Pos)                     /*!< TRNG_T::CTL: DVIEN Mask                */
+
+#define TRNG_CTL_READY_Pos               (7)                                               /*!< TRNG_T::CTL: READY Position            */
+#define TRNG_CTL_READY_Msk               (0x1ul << TRNG_CTL_READY_Pos)                     /*!< TRNG_T::CTL: READY Mask                */
+
+#define TRNG_CTL_SEEDGEN_Pos             (8)                                               /*!< TRNG_T::CTL: SEEDGEN Position          */
+#define TRNG_CTL_SEEDGEN_Msk             (0x1ul << TRNG_CTL_SEEDGEN_Pos)                   /*!< TRNG_T::CTL: SEEDGEN Mask              */
+
+#define TRNG_CTL_SEEDRDY_Pos             (9)                                               /*!< TRNG_T::CTL: SEEDRDY Position          */
+#define TRNG_CTL_SEEDRDY_Msk             (0x1ul << TRNG_CTL_SEEDRDY_Pos)                   /*!< TRNG_T::CTL: SEEDRDY Mask              */
+
+#define TRNG_CTL_Reversed_Pos            (10)                                              /*!< TRNG_T::CTL: Reversed Position         */
+#define TRNG_CTL_Reversed_Msk            (0x3ffffful << TRNG_CTL_Reversed_Pos)             /*!< TRNG_T::CTL: Reversed Mask             */
+
+#define TRNG_DATA_DATA_Pos               (0)                                               /*!< TRNG_T::DATA: DATA Position            */
+#define TRNG_DATA_DATA_Msk               (0xfful << TRNG_DATA_DATA_Pos)                    /*!< TRNG_T::DATA: DATA Mask                */
+
+#define TRNG_ACT_VER_Pos                 (0)                                               /*!< TRNG_T::ACT: VER Position              */
+#define TRNG_ACT_VER_Msk                 (0x7ful << TRNG_ACT_VER_Pos)                      /*!< TRNG_T::ACT: VER Mask                  */
+
+#define TRNG_ACT_ACT_Pos                 (7)                                               /*!< TRNG_T::ACT: ACT Position              */
+#define TRNG_ACT_ACT_Msk                 (0x1ul << TRNG_ACT_ACT_Pos)                       /*!< TRNG_T::ACT: ACT Mask                  */
+
+/**@}*/ /* TRNG_CONST */
+/**@}*/ /* end of TRNG register group */
+
+/**@}*/ /* end of REGISTER group */
+
+
+#endif /* __TRNG_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/uart_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/uart_reg.h
new file mode 100644
index 0000000000..0db25a1064
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/uart_reg.h
@@ -0,0 +1,1284 @@
+/**************************************************************************//**
+ * @file     uart_reg.h
+ * @version  V1.00
+ * @brief    UART register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __UART_REG_H__
+#define __UART_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+
+/*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/
+/**
+    @addtogroup UART Universal Asynchronous Receiver/Transmitter Controller(UART)
+    Memory Mapped Structure for UART Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var UART_T::DAT
+     * Offset: 0x00  UART Receive/Transmit Buffer Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |DAT       |Data Receive/Transmit Buffer
+     * |        |          |Write Operation:
+     * |        |          |By writing one byte to this register, the data byte will be stored in transmitter FIFO.
+     * |        |          |The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.
+     * |        |          |Read Operation:
+     * |        |          |By reading this register, the UART controller will return an 8-bit data received from receiver FIFO.
+     * |[8]     |PARITY    |Parity Bit Receive/Transmit Buffer
+     * |        |          |Write Operation:
+     * |        |          |By writing to this bit, the parity bit will be stored in transmitter FIFO.
+     * |        |          |If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD.
+     * |        |          |Read Operation:
+     * |        |          |If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit.
+     * |        |          |Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set.
+     * @var UART_T::INTEN
+     * Offset: 0x04  UART Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RDAIEN    |Receive Data Available Interrupt Enable Bit
+     * |        |          |0 = Receive data available interrupt Disabled.
+     * |        |          |1 = Receive data available interrupt Enabled.
+     * |[1]     |THREIEN   |Transmit Holding Register Empty Interrupt Enable Bit
+     * |        |          |0 = Transmit holding register empty interrupt Disabled.
+     * |        |          |1 = Transmit holding register empty interrupt Enabled.
+     * |[2]     |RLSIEN    |Receive Line Status Interrupt Enable Bit
+     * |        |          |0 = Receive Line Status interrupt Disabled.
+     * |        |          |1 = Receive Line Status interrupt Enabled.
+     * |[3]     |MODEMIEN  |Modem Status Interrupt Enable Bit
+     * |        |          |0 = Modem status interrupt Disabled.
+     * |        |          |1 = Modem status interrupt Enabled.
+     * |[4]     |RXTOIEN   |RX Time-out Interrupt Enable Bit
+     * |        |          |0 = RX time-out interrupt Disabled.
+     * |        |          |1 = RX time-out interrupt Enabled.
+     * |[5]     |BUFERRIEN |Buffer Error Interrupt Enable Bit
+     * |        |          |0 = Buffer error interrupt Disabled.
+     * |        |          |1 = Buffer error interrupt Enabled.
+     * |[6]     |WKIEN     |Wake-up Interrupt Enable Bit
+     * |        |          |0 = Wake-up Interrupt Disabled.
+     * |        |          |1 = Wake-up Interrupt Enabled.
+     * |[8]     |LINIEN    |LIN Bus Interrupt Enable Bit
+     * |        |          |0 = LIN bus interrupt Disabled.
+     * |        |          |1 = LIN bus interrupt Enabled.
+     * |        |          |Note: This bit is used for LIN function mode.
+     * |[11]    |TOCNTEN   |Receive Buffer Time-out Counter Enable Bit
+     * |        |          |0 = Receive Buffer Time-out counter Disabled.
+     * |        |          |1 = Receive Buffer Time-out counter Enabled.
+     * |[12]    |ATORTSEN  |nRTS Auto-flow Control Enable Bit
+     * |        |          |0 = nRTS auto-flow control Disabled.
+     * |        |          |1 = nRTS auto-flow control Enabled.
+     * |        |          |Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
+     * |[13]    |ATOCTSEN  |nCTS Auto-flow Control Enable Bit
+     * |        |          |0 = nCTS auto-flow control Disabled.
+     * |        |          |1 = nCTS auto-flow control Enabled.
+     * |        |          |Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
+     * |[14]    |TXPDMAEN  |TX PDMA Enable Bit
+     * |        |          |This bit can enable or disable TX PDMA service.
+     * |        |          |0 = TX PDMA Disabled.
+     * |        |          |1 = TX PDMA Enabled.
+     * |[15]    |RXPDMAEN  |RX PDMA Enable Bit
+     * |        |          |This bit can enable or disable RX PDMA service.
+     * |        |          |0 = RX PDMA Disabled.
+     * |        |          |1 = RX PDMA Enabled.
+     * |        |          |Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused.
+     * |        |          |If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stop.
+     * |        |          |Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing 1 to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue.
+     * |[16]    |SWBEIEN   |Single-wire Bit Error Detection Interrupt Enable Bit
+     * |        |          |Set this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.
+     * |        |          |0 = Single-wire Bit Error Detect Interrupt Disabled.
+     * |        |          |1 = Single-wire Bit Error Detect Interrupt Enabled.
+     * |        |          |Note: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.
+     * |[18]    |ABRIEN    |Auto-baud Rate Interrupt Enable Bit
+     * |        |          |0 = Auto-baud rate interrupt Disabled.
+     * |        |          |1 = Auto-baud rate interrupt Enabled.
+     * |[22]    |TXENDIEN  |Transmitter Empty Interrupt Enable Bit
+     * |        |          |If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted).
+     * |        |          |0 = Transmitter empty interrupt Disabled.
+     * |        |          |1 = Transmitter empty interrupt Enabled.
+     * @var UART_T::FIFO
+     * Offset: 0x08  UART FIFO Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1]     |RXRST     |RX Field Software Reset
+     * |        |          |When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset the RX internal state machine and pointers.
+     * |        |          |Note1: This bit will automatically clear at least 3 UART peripheral clock cycles.
+     * |        |          |Note2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set.
+     * |[2]     |TXRST     |TX Field Software Reset
+     * |        |          |When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset the TX internal state machine and pointers.
+     * |        |          |Note1: This bit will automatically clear at least 3 UART peripheral clock cycles.
+     * |        |          |Note2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set.
+     * |[7:4]   |RFITL     |RX FIFO Interrupt Trigger Level
+     * |        |          |When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
+     * |        |          |0000 = RX FIFO Interrupt Trigger Level is 1 byte.
+     * |        |          |0001 = RX FIFO Interrupt Trigger Level is 4 bytes.
+     * |        |          |0010 = RX FIFO Interrupt Trigger Level is 8 bytes.
+     * |        |          |0011 = RX FIFO Interrupt Trigger Level is 14 bytes.
+     * |        |          |Others = Reserved.
+     * |[8]     |RXOFF     |Receiver Disable Bit
+     * |        |          |The receiver is disabled or not (set 1 to disable receiver).
+     * |        |          |0 = Receiver Enabled.
+     * |        |          |1 = Receiver Disabled.
+     * |        |          |Note: This bit is used for RS-485 Normal Multi-drop mode.
+     * |        |          |It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
+     * |[19:16] |RTSTRGLV  |nRTS Trigger Level for Auto-flow Control Use
+     * |        |          |0000 = nRTS Trigger Level is 1 byte.
+     * |        |          |0001 = nRTS Trigger Level is 4 bytes.
+     * |        |          |0010 = nRTS Trigger Level is 8 bytes.
+     * |        |          |0011 = nRTS Trigger Level is 14 bytes.
+     * |        |          |Others = Reserved.
+     * |        |          |Note: This field is used for auto nRTS flow control.
+     * @var UART_T::LINE
+     * Offset: 0x0C  UART Line Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |WLS       |Word Length Selection
+     * |        |          |This field sets UART word length.
+     * |        |          |00 = 5 bits.
+     * |        |          |01 = 6 bits.
+     * |        |          |10 = 7 bits.
+     * |        |          |11 = 8 bits.
+     * |[2]     |NSB       |Number of STOP Bit
+     * |        |          |0 = One STOP bit is generated in the transmitted data.
+     * |        |          |1 = When select 5-bit word length, 1.5 STOP bit is generated in the transmitted data.
+     * |        |          |When select 6-, 7- and 8-bit word length, 2 STOP bit is generated in the transmitted data.
+     * |[3]     |PBE       |Parity Bit Enable Bit
+     * |        |          |0 = Parity bit generated Disabled.
+     * |        |          |1 = Parity bit generated Enabled.
+     * |        |          |Note: Parity bit is generated on each outgoing character and is checked on each incoming data.
+     * |[4]     |EPE       |Even Parity Enable Bit
+     * |        |          |0 = Odd number of logic 1's is transmitted and checked in each word.
+     * |        |          |1 = Even number of logic 1's is transmitted and checked in each word.
+     * |        |          |Note: This bit has effect only when PBE (UART_LINE[3]) is set.
+     * |[5]     |SPE       |Stick Parity Enable Bit
+     * |        |          |0 = Stick parity Disabled.
+     * |        |          |1 = Stick parity Enabled.
+     * |        |          |Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0.
+     * |        |          |If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.
+     * |[6]     |BCB       |Break Control Bit
+     * |        |          |0 = Break Control Disabled.
+     * |        |          |1 = Break Control Enabled.
+     * |        |          |Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0)
+     * |        |          |This bit acts only on TX line and has no effect on the transmitter logic.
+     * |[7]     |PSS       |Parity Bit Source Selection
+     * |        |          |The parity bit can be selected to be generated and checked automatically or by software.
+     * |        |          |0 = Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically.
+     * |        |          |1 = Parity bit generated and checked by software.
+     * |        |          |Note1: This bit has effect only when PBE (UART_LINE[3]) is set.
+     * |        |          |Note2: If PSS is 0, the parity bit is transmitted and checked automatically.
+     * |        |          |If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]).
+     * |[8]     |TXDINV    |TX Data Inverted
+     * |        |          |0 = Transmitted data signal inverted Disabled.
+     * |        |          |1 = Transmitted data signal inverted Enabled.
+     * |        |          |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared.
+     * |        |          |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
+     * |        |          |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
+     * |[9]     |RXDINV    |RX Data Inverted
+     * |        |          |0 = Received data signal inverted Disabled.
+     * |        |          |1 = Received data signal inverted Enabled.
+     * |        |          |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared.
+     * |        |          |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
+     * |        |          |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function.
+     * @var UART_T::MODEM
+     * Offset: 0x10  UART Modem Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1]     |RTS       |nRTS (Request-to-send) Signal Control
+     * |        |          |This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.
+     * |        |          |0 = nRTS signal is active.
+     * |        |          |1 = nRTS signal is inactive.
+     * |        |          |Note1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.
+     * |        |          |Note2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
+     * |[9]     |RTSACTLV  |nRTS Pin Active Level
+     * |        |          |This bit defines the active level state of nRTS pin output.
+     * |        |          |0 = nRTS pin output is high level active.
+     * |        |          |1 = nRTS pin output is low level active. (Default)
+     * |        |          |Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared.
+     * |        |          |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
+     * |[13]    |RTSSTS    |nRTS Pin Status (Read Only)
+     * |        |          |This bit mirror from nRTS pin output of voltage logic status.
+     * |        |          |0 = nRTS pin output is low level voltage logic state.
+     * |        |          |1 = nRTS pin output is high level voltage logic state.
+     * @var UART_T::MODEMSTS
+     * Offset: 0x14  UART Modem Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CTSDETF   |Detect nCTS State Change Flag
+     * |        |          |This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.
+     * |        |          |0 = nCTS input has not change state.
+     * |        |          |1 = nCTS input has change state.
+     * |        |          |Note: This bit can be cleared by writing 1 to it.
+     * |[4]     |CTSSTS    |nCTS Pin Status (Read Only)
+     * |        |          |This bit mirror from nCTS pin input of voltage logic status.
+     * |        |          |0 = nCTS pin input is low level voltage logic state.
+     * |        |          |1 = nCTS pin input is high level voltage logic state.
+     * |        |          |Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected.
+     * |[8]     |CTSACTLV  |nCTS Pin Active Level
+     * |        |          |This bit defines the active level state of nCTS pin input.
+     * |        |          |0 = nCTS pin input is high level active.
+     * |        |          |1 = nCTS pin input is low level active. (Default)
+     * |        |          |Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared.
+     * |        |          |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
+     * @var UART_T::FIFOSTS
+     * Offset: 0x18  UART FIFO Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RXOVIF    |RX Overflow Error Interrupt Flag
+     * |        |          |This bit is set when RX FIFO overflow.
+     * |        |          |If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set.
+     * |        |          |0 = RX FIFO is not overflow.
+     * |        |          |1 = RX FIFO is overflow.
+     * |        |          |Note: This bit can be cleared by writing 1 to it.
+     * |[1]     |ABRDIF    |Auto-baud Rate Detect Interrupt Flag
+     * |        |          |This bit is set to logic 1 when auto-baud rate detect function is finished.
+     * |        |          |0 = Auto-baud rate detect function is not finished.
+     * |        |          |1 = Auto-baud rate detect function is finished.
+     * |        |          |Note: This bit can be cleared by writing 1 to it.
+     * |[2]     |ABRDTOIF  |Auto-baud Rate Detect Time-out Interrupt Flag
+     * |        |          |This bit is set to logic 1 in Auto-baud Rate Detect mode when the baud rate counter is overflow.
+     * |        |          |0 = Auto-baud rate counter is underflow.
+     * |        |          |1 = Auto-baud rate counter is overflow.
+     * |        |          |Note: This bit can be cleared by writing 1 to it.
+     * |[3]     |ADDRDETF  |RS-485 Address Byte Detect Flag
+     * |        |          |0 = Receiver detects a data that is not an address bit (bit 9 ='0').
+     * |        |          |1 = Receiver detects a data that is an address bit (bit 9 ='1').
+     * |        |          |Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.
+     * |        |          |Note2: This bit can be cleared by writing 1 to it.
+     * |[4]     |PEF       |Parity Error Flag
+     * |        |          |This bit is set to logic 1 whenever the received character does not have a valid parity bit.
+     * |        |          |0 = No parity error is generated.
+     * |        |          |1 = Parity error is generated.
+     * |        |          |Note: This bit can be cleared by writing 1 to it.
+     * |[5]     |FEF       |Framing Error Flag
+     * |        |          |This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
+     * |        |          |0 = No framing error is generated.
+     * |        |          |1 = Framing error is generated.
+     * |        |          |Note: This bit can be cleared by writing 1 to it.
+     * |[6]     |BIF       |Break Interrupt Flag
+     * |        |          |This bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits).
+     * |        |          |0 = No Break interrupt is generated.
+     * |        |          |1 = Break interrupt is generated.
+     * |        |          |Note: This bit can be cleared by writing 1 to it.
+     * |[13:8]  |RXPTR     |RX FIFO Pointer (Read Only)
+     * |        |          |This field indicates the RX FIFO Buffer Pointer.
+     * |        |          |When UART receives one byte from external device, RXPTR increases one.
+     * |        |          |When one byte of RX FIFO is read by CPU, RXPTR decreases one.
+     * |        |          |The Maximum value shown in RXPTR is 15
+     * |        |          |When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0.
+     * |        |          |As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
+     * |[14]    |RXEMPTY   |Receiver FIFO Empty (Read Only)
+     * |        |          |This bit initiate RX FIFO empty or not.
+     * |        |          |0 = RX FIFO is not empty.
+     * |        |          |1 = RX FIFO is empty.
+     * |        |          |Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high.
+     * |        |          |It will be cleared when UART receives any new data.
+     * |[15]    |RXFULL    |Receiver FIFO Full (Read Only)
+     * |        |          |This bit initiates RX FIFO full or not.
+     * |        |          |0 = RX FIFO is not full.
+     * |        |          |1 = RX FIFO is full.
+     * |        |          |Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
+     * |[21:16] |TXPTR     |TX FIFO Pointer (Read Only)
+     * |        |          |This field indicates the TX FIFO Buffer Pointer.
+     * |        |          |When CPU writes one byte into UART_DAT, TXPTR increases one.
+     * |        |          |When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
+     * |        |          |The Maximum value shown in TXPTR is 15.
+     * |        |          |When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0.
+     * |        |          |As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
+     * |[22]    |TXEMPTY   |Transmitter FIFO Empty (Read Only)
+     * |        |          |This bit indicates TX FIFO empty or not.
+     * |        |          |0 = TX FIFO is not empty.
+     * |        |          |1 = TX FIFO is empty.
+     * |        |          |Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high.
+     * |        |          |It will be cleared when writing data into UART_DAT (TX FIFO not empty).
+     * |[23]    |TXFULL    |Transmitter FIFO Full (Read Only)
+     * |        |          |This bit indicates TX FIFO full or not.
+     * |        |          |0 = TX FIFO is not full.
+     * |        |          |1 = TX FIFO is full.
+     * |        |          |Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware.
+     * |[24]    |TXOVIF    |TX Overflow Error Interrupt Flag
+     * |        |          |If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.
+     * |        |          |0 = TX FIFO is not overflow.
+     * |        |          |1 = TX FIFO is overflow.
+     * |        |          |Note: This bit can be cleared by writing 1 to it.
+     * |[28]    |TXEMPTYF  |Transmitter Empty Flag (Read Only)
+     * |        |          |This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.
+     * |        |          |0 = TX FIFO is not empty or the STOP bit of the last byte has been not transmitted.
+     * |        |          |1 = TX FIFO is empty and the STOP bit of the last byte has been transmitted.
+     * |        |          |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
+     * |[29]    |RXIDLE    |RX Idle Status (Read Only)
+     * |        |          |This bit is set by hardware when RX is idle.
+     * |        |          |0 = RX is busy.
+     * |        |          |1 = RX is idle. (Default)
+     * |[31]    |TXRXACT   |TX and RX Active Status (Read Only)
+     * |        |          |This bit indicates TX and RX are active or inactive.
+     * |        |          |0 = TX and RX are inactive.
+     * |        |          |1 = TX and RX are active. (Default)
+     * |        |          |Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared.
+     * |        |          |The UART controller can not transmit or receive data at this moment.
+     * |        |          |Otherwise this bit is set.
+     * @var UART_T::INTSTS
+     * Offset: 0x1C  UART Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RDAIF     |Receive Data Available Interrupt Flag
+     * |        |          |When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set.
+     * |        |          |If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.
+     * |        |          |0 = No RDA interrupt flag is generated.
+     * |        |          |1 = RDA interrupt flag is generated.
+     * |        |          |Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]).
+     * |[1]     |THREIF    |Transmit Holding Register Empty Interrupt Flag
+     * |        |          |This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register.
+     * |        |          |If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.
+     * |        |          |0 = No THRE interrupt flag is generated.
+     * |        |          |1 = THRE interrupt flag is generated.
+     * |        |          |Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
+     * |[2]     |RLSIF     |Receive Line Interrupt Flag (Read Only)
+     * |        |          |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set).
+     * |        |          |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
+     * |        |          |0 = No RLS interrupt flag is generated.
+     * |        |          |1 = RLS interrupt flag is generated.
+     * |        |          |Note1: In RS-485 function mode, this field is set include receiver detect and received address byte character (bit9 = 1) bit.
+     * |        |          |At the same time, the bit of ADDRDETF (UART_FIFOSTS[3]) is also set.
+     * |        |          |Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
+     * |        |          |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
+     * |[3]     |MODEMIF   |MODEM Interrupt Flag (Read Only)
+     * |        |          |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS[0]) = 1).
+     * |        |          |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated.
+     * |        |          |0 = No Modem interrupt flag is generated.
+     * |        |          |1 = Modem interrupt flag is generated.
+     * |        |          |Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
+     * |[4]     |RXTOIF    |RX Time-out Interrupt Flag (Read Only)
+     * |        |          |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]).
+     * |        |          |If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.
+     * |        |          |0 = No RX time-out interrupt flag is generated.
+     * |        |          |1 = RX time-out interrupt flag is generated.
+     * |        |          |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
+     * |[5]     |BUFERRIF  |Buffer Error Interrupt Flag (Read Only)
+     * |        |          |This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set).
+     * |        |          |When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct.
+     * |        |          |If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
+     * |        |          |0 = No buffer error interrupt flag is generated.
+     * |        |          |1 = Buffer error interrupt flag is generated.
+     * |        |          |Note: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
+     * |[6]     |WKIF      |UART Wake-up Interrupt Flag (Read Only)
+     * |        |          |This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.
+     * |        |          |0 = No UART wake-up interrupt flag is generated.
+     * |        |          |1 = UART wake-up interrupt flag is generated.
+     * |        |          |Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag.
+     * |[7]     |LINIF     |LIN Bus Interrupt Flag
+     * |        |          |This bit is set when LIN slave header detect (SLVHDETF (UART_LINSTS[0]=1)), LIN break detect (BRKDETF(UART_LINSTS[8]=1)), bit error detect (BITEF(UART_LINSTS[9]=1)), LIN slave ID parity error (SLVIDPEF(UART_LINSTS[2] = 1)) or LIN slave header error detect (SLVHEF (UART_LINSTS[1]))
+     * |        |          |If LINIEN (UART_INTEN [8]) is enabled the LIN interrupt will be generated.
+     * |        |          |0 = None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated.
+     * |        |          |1 = At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated.
+     * |        |          |Note: This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing 1 to LINIF(UART_INTSTS[7]).
+     * |[8]     |RDAINT    |Receive Data Available Interrupt Indicator (Read Only)
+     * |        |          |This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
+     * |        |          |0 = No RDA interrupt is generated.
+     * |        |          |1 = RDA interrupt is generated.
+     * |[9]     |THREINT   |Transmit Holding Register Empty Interrupt Indicator (Read Only)
+     * |        |          |This bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1.
+     * |        |          |0 = No THRE interrupt is generated.
+     * |        |          |1 = THRE interrupt is generated.
+     * |[10]    |RLSINT    |Receive Line Status Interrupt Indicator (Read Only)
+     * |        |          |This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
+     * |        |          |0 = No RLS interrupt is generated.
+     * |        |          |1 = RLS interrupt is generated.
+     * |[11]    |MODEMINT  |MODEM Status Interrupt Indicator (Read Only)
+     * |        |          |This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1
+     * |        |          |0 = No Modem interrupt is generated.
+     * |        |          |1 = Modem interrupt is generated..
+     * |[12]    |RXTOINT   |RX Time-out Interrupt Indicator (Read Only)
+     * |        |          |This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
+     * |        |          |0 = No RX time-out interrupt is generated.
+     * |        |          |1 = RX time-out interrupt is generated.
+     * |[13]    |BUFERRINT |Buffer Error Interrupt Indicator (Read Only)
+     * |        |          |This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1.
+     * |        |          |0 = No buffer error interrupt is generated.
+     * |        |          |1 = Buffer error interrupt is generated.
+     * |[14]    |WKINT     |UART Wake-up Interrupt Indicator (Read Only)
+     * |        |          |This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1.
+     * |        |          |0 = No UART wake-up interrupt is generated.
+     * |        |          |1 = UART wake-up interrupt is generated.
+     * |[15]    |LININT    |LIN Bus Interrupt Indicator (Read Only)
+     * |        |          |This bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1.
+     * |        |          |0 = No LIN Bus interrupt is generated.
+     * |        |          |1 = The LIN Bus interrupt is generated.
+     * |[16]    |SWBEIF    |Single-wire Bit Error Detection Interrupt Flag
+     * |        |          |This bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.
+     * |        |          |0 = No single-wire bit error detection interrupt flag is generated.
+     * |        |          |1 = Single-wire bit error detection interrupt flag is generated.
+     * |        |          |Note 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode.
+     * |        |          |Note 2: This bit can be cleared by writing "1" to it.
+     * |[18]    |HWRLSIF   |PDMA Mode Receive Line Status Flag (Read Only)
+     * |        |          |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set).
+     * |        |          |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
+     * |        |          |0 = No RLS interrupt flag is generated in PDMA mode.
+     * |        |          |1 = RLS interrupt flag is generated in PDMA mode.
+     * |        |          |Note1: In RS-485 function mode, this field include receiver detect any address byte received address byte character (bit9 = 1) bit.
+     * |        |          |Note2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
+     * |        |          |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
+     * |[19]    |HWMODIF   |PDMA Mode MODEM Interrupt Flag (Read Only)
+     * |        |          |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS[0]=1)).
+     * |        |          |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated.
+     * |        |          |0 = No Modem interrupt flag is generated in PDMA mode.
+     * |        |          |1 = Modem interrupt flag is generated in PDMA mode.
+     * |        |          |Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]).
+     * |[20]    |HWTOIF    |PDMA Mode RX Time-out Interrupt Flag (Read Only)
+     * |        |          |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]).
+     * |        |          |If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated.
+     * |        |          |0 = No RX time-out interrupt flag is generated in PDMA mode.
+     * |        |          |1 = RX time-out interrupt flag is generated in PDMA mode.
+     * |        |          |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
+     * |[21]    |HWBUFEIF  |PDMA Mode Buffer Error Interrupt Flag (Read Only)
+     * |        |          |This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set).
+     * |        |          |When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct.
+     * |        |          |If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
+     * |        |          |0 = No buffer error interrupt flag is generated in PDMA mode.
+     * |        |          |1 = Buffer error interrupt flag is generated in PDMA mode.
+     * |        |          |Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
+     * |[22]    |TXENDIF   |Transmitter Empty Interrupt Flag
+     * |        |          |This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set).
+     * |        |          |If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated.
+     * |        |          |0 = No transmitter empty interrupt flag is generated.
+     * |        |          |1 = Transmitter empty interrupt flag is generated.
+     * |        |          |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
+     * |[24]    |SWBEINT   |Single-wire Bit Error Detect Interrupt Indicator (Read Only)
+     * |        |          |This bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1.
+     * |        |          |0 = No Single-wire Bit Error Detection Interrupt generated.
+     * |        |          |1 = Single-wire Bit Error Detection Interrupt generated.
+     * |[26]    |HWRLSINT  |PDMA Mode Receive Line Status Interrupt Indicator (Read Only)
+     * |        |          |This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1.
+     * |        |          |0 = No RLS interrupt is generated in PDMA mode.
+     * |        |          |1 = RLS interrupt is generated in PDMA mode.
+     * |[27]    |HWMODINT  |PDMA Mode MODEM Status Interrupt Indicator (Read Only)
+     * |        |          |This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1.
+     * |        |          |0 = No Modem interrupt is generated in PDMA mode.
+     * |        |          |1 = Modem interrupt is generated in PDMA mode.
+     * |[28]    |HWTOINT   |PDMA Mode RX Time-out Interrupt Indicator (Read Only)
+     * |        |          |This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1.
+     * |        |          |0 = No RX time-out interrupt is generated in PDMA mode.
+     * |        |          |1 = RX time-out interrupt is generated in PDMA mode.
+     * |[29]    |HWBUFEINT |PDMA Mode Buffer Error Interrupt Indicator (Read Only)
+     * |        |          |This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1.
+     * |        |          |0 = No buffer error interrupt is generated in PDMA mode.
+     * |        |          |1 = Buffer error interrupt is generated in PDMA mode.
+     * |[30]    |TXENDINT  |Transmitter Empty Interrupt Indicator (Read Only)
+     * |        |          |This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1.
+     * |        |          |0 = No Transmitter Empty interrupt is generated.
+     * |        |          |1 = Transmitter Empty interrupt is generated.
+     * |[31]    |ABRINT    |Auto-baud Rate Interrupt Indicator (Read Only)
+     * |        |          |This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1.
+     * |        |          |0 = No Auto-baud Rate interrupt is generated.
+     * |        |          |1 = The Auto-baud Rate interrupt is generated.
+     * @var UART_T::TOUT
+     * Offset: 0x20  UART Time-out Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |TOIC      |Time-out Interrupt Comparator
+     * |        |          |The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word if time out counter is enabled by setting TOCNTEN (UART_INTEN[11]).
+     * |        |          |Once the content of time-out counter is equal to that of time-out interrupt comparator (TOIC (UART_TOUT[7:0])), a receiver time-out interrupt (RXTOINT(UART_INTSTS[12])) is generated if RXTOIEN (UART_INTEN [4]) enabled.
+     * |        |          |A new incoming data word or RX FIFO empty will clear RXTOIF (UART_INTSTS[4]).
+     * |        |          |In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255.
+     * |        |          |So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer.
+     * |[15:8]  |DLY       |TX Delay Time Value
+     * |        |          |This field is used to programming the transfer delay time between the last stop bit and next start bit.
+     * |        |          |The unit is bit time.
+     * @var UART_T::BAUD
+     * Offset: 0x24  UART Baud Rate Divider Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |BRD       |Baud Rate Divider
+     * |        |          |The field indicates the baud rate divider.
+     * |        |          |This filed is used in baud rate calculation.
+     * |[27:24] |EDIVM1    |Extra Divider for BAUD Rate Mode 1
+     * |        |          |This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2.
+     * |[28]    |BAUDM0    |BAUD Rate Mode Selection Bit 0
+     * |        |          |This bit is baud rate mode selection bit 0
+     * |        |          |UART provides three baud rate calculation modes.
+     * |        |          |This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode.
+     * |[29]    |BAUDM1    |BAUD Rate Mode Selection Bit 1
+     * |        |          |This bit is baud rate mode selection bit 1.
+     * |        |          |UART provides three baud rate calculation modes.
+     * |        |          |This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode.
+     * |        |          |Note: In IrDA mode must be operated in mode 0.
+     * @var UART_T::IRDA
+     * Offset: 0x28  UART IrDA Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1]     |TXEN      |IrDA Receiver/Transmitter Selection Enable Bit
+     * |        |          |0 = IrDA Transmitter Disabled and Receiver Enabled. (Default)
+     * |        |          |1 = IrDA Transmitter Enabled and Receiver Disabled.
+     * |[5]     |TXINV     |IrDA Inverse Transmitting Output Signal
+     * |        |          |0 = None inverse transmitting signal. (Default).
+     * |        |          |1 = Inverse transmitting output signal.
+     * |        |          |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared.
+     * |        |          |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
+     * |        |          |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
+     * |[6]     |RXINV     |IrDA Inverse Receive Input Signal
+     * |        |          |0 = None inverse receiving input signal.
+     * |        |          |1 = Inverse receiving input signal. (Default)
+     * |        |          |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared.
+     * |        |          |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
+     * |        |          |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function.
+     * @var UART_T::ALTCTL
+     * Offset: 0x2C  UART Alternate Control/Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |BRKFL     |UART LIN Break Field Length
+     * |        |          |This field indicates a 4-bit LIN TX break field count.
+     * |        |          |Note1: This break field length is BRKFL + 1.
+     * |        |          |Note2: According to LIN spec, the reset value is 0xC (break field length = 13).
+     * |[6]     |LINRXEN   |LIN RX Enable Bit
+     * |        |          |0 = LIN RX mode Disabled.
+     * |        |          |1 = LIN RX mode Enabled.
+     * |[7]     |LINTXEN   |LIN TX Break Mode Enable Bit
+     * |        |          |0 = LIN TX Break mode Disabled.
+     * |        |          |1 = LIN TX Break mode Enabled.
+     * |        |          |Note: When TX break field transfer operation finished, this bit will be cleared automatically.
+     * |[8]     |RS485NMM  |RS-485 Normal Multi-drop Operation Mode (NMM)
+     * |        |          |0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled.
+     * |        |          |1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled.
+     * |        |          |Note: It cannot be active with RS-485_AAD operation mode.
+     * |[9]     |RS485AAD  |RS-485 Auto Address Detection Operation Mode (AAD)
+     * |        |          |0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled.
+     * |        |          |1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled.
+     * |        |          |Note: It cannot be active with RS-485_NMM operation mode.
+     * |[10]    |RS485AUD  |RS-485 Auto Direction Function (AUD)
+     * |        |          |0 = RS-485 Auto Direction Operation function (AUD) Disabled.
+     * |        |          |1 = RS-485 Auto Direction Operation function (AUD) Enabled.
+     * |        |          |Note: It can be active with RS-485_AAD or RS-485_NMM operation mode.
+     * |[15]    |ADDRDEN   |RS-485 Address Detection Enable Bit
+     * |        |          |This bit is used to enable RS-485 Address Detection mode.
+     * |        |          |0 = Address detection mode Disabled.
+     * |        |          |1 = Address detection mode Enabled.
+     * |        |          |Note: This bit is used for RS-485 any operation mode.
+     * |[17]    |ABRIF     |Auto-baud Rate Interrupt Flag (Read Only)
+     * |        |          |This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated.
+     * |        |          |0 = No auto-baud rate interrupt flag is generated.
+     * |        |          |1 = Auto-baud rate interrupt flag is generated.
+     * |        |          |Note: This bit is read only, but it can be cleared by writing 1 to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]).
+     * |[18]    |ABRDEN    |Auto-baud Rate Detect Enable Bit
+     * |        |          |0 = Auto-baud rate detect function Disabled.
+     * |        |          |1 = Auto-baud rate detect function Enabled.
+     * |        |          |Note : This bit is cleared automatically after auto-baud detection is finished.
+     * |[20:19] |ABRDBITS  |Auto-baud Rate Detect Bit Length
+     * |        |          |00 = 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01.
+     * |        |          |01 = 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02.
+     * |        |          |10 = 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08.
+     * |        |          |11 = 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80.
+     * |        |          |Note : The calculation of bit number includes the START bit.
+     * |[31:24] |ADDRMV    |Address Match Value
+     * |        |          |This field contains the RS-485 address match values.
+     * |        |          |Note: This field is used for RS-485 auto address detection mode.
+     * @var UART_T::FUNCSEL
+     * Offset: 0x30  UART Function Select Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |FUNCSEL   |Function Select
+     * |        |          |000 = UART function.
+     * |        |          |001 = LIN function.
+     * |        |          |010 = IrDA function.
+     * |        |          |011 = RS-485 function.
+     * |        |          |100 = UART Single-wire function.
+     * |        |          |Others = Reserved.
+     * |[3]     |TXRXDIS   |TX and RX Disable Bit
+     * |        |          |Setting this bit can disable TX and RX.
+     * |        |          |0 = TX and RX Enabled.
+     * |        |          |1 = TX and RX Disabled.
+     * |        |          |Note: The TX and RX will not disable immediately when this bit is set.
+     * |        |          |The TX and RX complete current task before disable TX and RX.
+     * |        |          |When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared.
+     * |[6]     |DGE       |Deglitch Enable Bit
+     * |        |          |0 = Deglitch Disabled.
+     * |        |          |1 = Deglitch Enabled.
+     * |        |          |Note: When this bit is set to logic 1, any pulse width less than about 300 ns will be considered a glitch and will be removed in the serial data input (RX).
+     * |        |          |This bit acts only on RX line and has no effect on the transmitter logic.
+     * @var UART_T::LINCTL
+     * Offset: 0x34  UART LIN Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SLVEN     |LIN Slave Mode Enable Bit
+     * |        |          |0 = LIN slave mode Disabled.
+     * |        |          |1 = LIN slave mode Enabled.
+     * |[1]     |SLVHDEN   |LIN Slave Header Detection Enable Bit
+     * |        |          |0 = LIN slave header detection Disabled.
+     * |        |          |1 = LIN slave header detection Enabled.
+     * |        |          |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
+     * |        |          |Note2: In LIN function mode, when detect header field (break + sync + frame ID), SLVHDETF (UART_LINSTS [0]) flag will be asserted.
+     * |        |          |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
+     * |[2]     |SLVAREN   |LIN Slave Automatic Resynchronization Mode Enable Bit
+     * |        |          |0 = LIN automatic resynchronization Disabled.
+     * |        |          |1 = LIN automatic resynchronization Enabled.
+     * |        |          |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
+     * |        |          |Note2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).
+     * |[3]     |SLVDUEN   |LIN Slave Divider Update Method Enable Bit
+     * |        |          |0 = UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time).
+     * |        |          |1 = UART_BAUD is updated at the next received character
+     * |        |          |User must set the bit before checksum reception.
+     * |        |          |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1).
+     * |        |          |Note2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared)
+     * |[4]     |MUTE      |LIN Mute Mode Enable Bit
+     * |        |          |0 = LIN mute mode Disabled.
+     * |        |          |1 = LIN mute mode Enabled.
+     * |        |          |Note: The exit from mute mode condition and each control and interactions of this field are explained in 6.16.5.10 (LIN slave mode).
+     * |[8]     |SENDH     |LIN TX Send Header Enable Bit
+     * |        |          |The LIN TX header can be break field or break and sync field or break, sync and frame ID field, it is depend on setting HSEL (UART_LINCTL[23:22]).
+     * |        |          |0 = Send LIN TX header Disabled.
+     * |        |          |1 = Send LIN TX header Enabled.
+     * |        |          |Note1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]); user can read/write it by setting LINTXEN (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]).
+     * |        |          |Note2: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically.
+     * |[9]     |IDPEN     |LIN ID Parity Enable Bit
+     * |        |          |0 = LIN frame ID parity Disabled.
+     * |        |          |1 = LIN frame ID parity Enabled.
+     * |        |          |Note1: This bit can be used for LIN master to sending header field (SENDH (UART_LINCTL[8])) = 1 and HSEL (UART_LINCTL[23:22]) = 10 or be used for enable LIN slave received frame ID parity checked.
+     * |        |          |Note2: This bit is only used when the operation header transmitter is in HSEL (UART_LINCTL[23:22]) = 10.
+     * |[10]    |BRKDETEN  |LIN Break Detection Enable Bit
+     * |        |          |When detect consecutive dominant greater than 11 bits, and are followed by a delimiter character, the BRKDETF (UART_LINSTS[8]) flag is set at the end of break field.
+     * |        |          |If the LINIEN (UART_INTEN [8])=1, an interrupt will be generated.
+     * |        |          |0 = LIN break detection Disabled .
+     * |        |          |1 = LIN break detection Enabled.
+     * |[11]    |LINRXOFF  |LIN Receiver Disable Bit
+     * |        |          |If the receiver is enabled (RXOFF (UART_LINCTL[11] ) = 0), all received byte data will be accepted and stored in the RX FIFO, and if the receiver is disabled (RXOFF (UART_LINCTL[11] = 1), all received byte data will be ignore.
+     * |        |          |0 = LIN receiver Enabled.
+     * |        |          |1 = LIN receiver Disabled.
+     * |        |          |Note: This bit is only valid when operating in LIN function mode (FUNCSEL (UART_FUNCSEL[1:0]) = 01).
+     * |[12]    |BITERREN  |Bit Error Detect Enable Bit
+     * |        |          |0 = Bit error detection function Disabled.
+     * |        |          |1 = Bit error detection function Enabled.
+     * |        |          |Note: In LIN function mode, when occur bit error, the BITEF (UART_LINSTS[9]) flag will be asserted.
+     * |        |          |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
+     * |[19:16] |BRKFL     |LIN Break Field Length
+     * |        |          |This field indicates a 4-bit LIN TX break field count.
+     * |        |          |Note1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]), User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]).
+     * |        |          |Note2: This break field length is BRKFL + 1.
+     * |        |          |Note3: According to LIN spec, the reset value is 12 (break field length = 13).
+     * |[21:20] |BSL       |LIN Break/Sync Delimiter Length
+     * |        |          |00 = The LIN break/sync delimiter length is 1-bit time.
+     * |        |          |01 = The LIN break/sync delimiter length is 2-bit time.
+     * |        |          |10 = The LIN break/sync delimiter length is 3-bit time.
+     * |        |          |11 = The LIN break/sync delimiter length is 4-bit time.
+     * |        |          |Note: This bit used for LIN master to sending header field.
+     * |[23:22] |HSEL      |LIN Header Select
+     * |        |          |00 = The LIN header includes break field.
+     * |        |          |01 = The LIN header includes break field and sync field.
+     * |        |          |10 = The LIN header includes break field, sync field and frame ID field.
+     * |        |          |11 = Reserved.
+     * |        |          |Note: This bit is used to master mode for LIN to send header field (SENDH (UART_LINCTL [8]) = 1) or used to slave to indicates exit from mute mode condition (MUTE (UART_LINCTL[4] = 1).
+     * |[31:24] |PID       |LIN PID Bits
+     * |        |          |This field contains the LIN frame ID value when in LIN function mode, the frame ID parity can be generated by software or hardware depends on IDPEN (UART_LINCTL[9]) = 1.
+     * |        |          |If the parity generated by hardware, user fill ID0~ID5 (PID [29:24] ), hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field.
+     * |        |          |Note1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).
+     * |        |          |Note2: This field can be used for LIN master mode or slave mode.
+     * @var UART_T::LINSTS
+     * Offset: 0x38  UART LIN Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SLVHDETF  |LIN Slave Header Detection Flag
+     * |        |          |This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.
+     * |        |          |0 = LIN header not detected.
+     * |        |          |1 = LIN header detected (break + sync + frame ID).
+     * |        |          |Note1: This bit can be cleared by writing 1 to it.
+     * |        |          |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enable LIN slave header detection function (SLVHDEN (UART_LINCTL [1])).
+     * |        |          |Note3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header (break + sync + frame ID), the SLVHDETF will be set whether the frame ID correct or not.
+     * |[1]     |SLVHEF    |LIN Slave Header Error Flag
+     * |        |          |This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it
+     * |        |          |The header errors include break delimiter is too short (less than 0.5 bit time), frame error in sync field or Identifier field, sync field data is not 0x55 in Non-Automatic Resynchronization mode, sync field deviation error with Automatic Resynchronization mode, sync field measure time-out with Automatic Resynchronization mode and LIN header reception time-out.
+     * |        |          |0 = LIN header error not detected.
+     * |        |          |1 = LIN header error detected.
+     * |        |          |Note1: This bit can be cleared by writing 1 to it.
+     * |        |          |Note2: This bit is only valid when UART is operated in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enables LIN slave header detection function (SLVHDEN (UART_LINCTL [1])).
+     * |[2]     |SLVIDPEF  |LIN Slave ID Parity Error Flag
+     * |        |          |This bit is set by hardware when receipted frame ID parity is not correct.
+     * |        |          |0 = No active.
+     * |        |          |1 = Receipted frame ID parity is not correct.
+     * |        |          |Note1: This bit can be cleared by writing 1 to it.
+     * |        |          |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enable LIN frame ID parity check function IDPEN (UART_LINCTL [9]).
+     * |[3]     |SLVSYNCF  |LIN Slave Sync Field
+     * |        |          |This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode.
+     * |        |          |When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.
+     * |        |          |0 = The current character is not at LIN sync state.
+     * |        |          |1 = The current character is at LIN sync state.
+     * |        |          |Note1: This bit is only valid when in LIN Slave mode (SLVEN(UART_LINCTL[0]) = 1).
+     * |        |          |Note2: This bit can be cleared by writing 1 to it.
+     * |        |          |Note3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header.
+     * |[8]     |BRKDETF   |LIN Break Detection Flag
+     * |        |          |This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.
+     * |        |          |0 = LIN break not detected.
+     * |        |          |1 = LIN break detected.
+     * |        |          |Note1: This bit can be cleared by writing 1 to it.
+     * |        |          |Note2: This bit is only valid when LIN break detection function is enabled (BRKDETEN (UART_LINCTL[10]) = 1).
+     * |[9]     |BITEF     |Bit Error Detect Status Flag
+     * |        |          |At TX transfer state, hardware will monitor the bus state, if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state, BITEF (UART_LINSTS[9]) will be set.
+     * |        |          |When occur bit error, if the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
+     * |        |          |0 = Bit error not detected.
+     * |        |          |1 = Bit error detected.
+     * |        |          |Note1: This bit can be cleared by writing 1 to it.
+     * |        |          |Note2: This bit is only valid when enable bit error detection function (BITERREN (UART_LINCTL [12]) = 1).
+     * @var UART_T::BRCOMP
+     * Offset: 0x3C  UART Baud Rate Compensation Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[8:0]   |BRCOMP    |Baud Rate Compensation Patten
+     * |        |          |These 9-bits are used to define the relative bit is compensated or not.
+     * |        |          |BRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOMP[8] is used to define the parity bit.
+     * |[31]    |BRCOMPDEC |Baud Rate Compensation Decrease
+     * |        |          |0 = Positive (increase one module clock) compensation for each compensated bit.
+     * |        |          |1 = Negative (decrease one module clock) compensation for each compensated bit.
+     * @var UART_T::WKCTL
+     * Offset: 0x40  UART Wake-up Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WKCTSEN   |nCTS Wake-up Enable Bit
+     * |        |          |0 = nCTS Wake-up system function Disabled.
+     * |        |          |1 = nCTS Wake-up system function Enabled, when the system is in Power-down mode, an external.
+     * |        |          |nCTS change will wake-up system from Power-down mode.
+     * |[1]     |WKDATEN   |Incoming Data Wake-up Enable Bit
+     * |        |          |0 = Incoming data wake-up system function Disabled.
+     * |        |          |1 = Incoming data wake-up system function Enabled, when the system is in Power-down mode,.
+     * |        |          |incoming data will wake-up system from Power-down mode.
+     * |[2]     |WKRFRTEN  |Received Data FIFO Reached Threshold Wake-up Enable Bit
+     * |        |          |0 = Received Data FIFO reached threshold wake-up system function Disabled.
+     * |        |          |1 = Received Data FIFO reached threshold wake-up system function Enabled, when the system is.
+     * |        |          |in Power-down mode, Received Data FIFO reached threshold will wake-up system from
+     * |        |          |Power-down mode.
+     * |[3]     |WKRS485EN |RS-485 Address Match (AAD Mode) Wake-up Enable Bit
+     * |        |          |0 = RS-485 Address Match (AAD mode) wake-up system function Disabled.
+     * |        |          |1 = RS-485 Address Match (AAD mode) wake-up system function Enabled, when the system is in Power-down mode, RS-485 Address Match will wake-up system from Power-down mode.
+     * |        |          |Note: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1.
+     * |[4]     |WKTOUTEN  |Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit
+     * |        |          |0 = Received Data FIFO reached threshold time-out wake-up system function Disabled.
+     * |        |          |1 = Received Data FIFO reached threshold time-out wake-up system function Enabled, when the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake-up system from Power-down mode.
+     * |        |          |Note: It is suggest the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1.
+     * @var UART_T::WKSTS
+     * Offset: 0x44  UART Wake-up Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CTSWKF    |nCTS Wake-up Flag
+     * |        |          |This bit is set if chip wake-up from power-down state by nCTS wake-up.
+     * |        |          |0 = Chip stays in power-down state.
+     * |        |          |1 = Chip wake-up from power-down state by nCTS wake-up.
+     * |        |          |Note1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to 1.
+     * |        |          |Note2: This bit can be cleared by writing 1 to it.
+     * |[1]     |DATWKF    |Incoming Data Wake-up Flag
+     * |        |          |This bit is set if chip wake-up from power-down state by data wake-up.
+     * |        |          |0 = Chip stays in power-down state.
+     * |        |          |1 = Chip wake-up from power-down state by Incoming Data wake-up.
+     * |        |          |Note1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to 1.
+     * |        |          |Note2: This bit can be cleared by writing 1 to it.
+     * |[2]     |RFRTWKF   |Received Data FIFO Reached Threshold Wake-up Flag
+     * |        |          |This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up.
+     * |        |          |0 = Chip stays in power-down state.
+     * |        |          |1 = Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up.
+     * |        |          |Note1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to 1.
+     * |        |          |Note2: This bit can be cleared by writing 1 to it.
+     * |[3]     |RS485WKF  |RS-485 Address Match (AAD Mode) Wake-up Flag
+     * |        |          |This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).
+     * |        |          |0 = Chip stays in power-down state.
+     * |        |          |1 = Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up.
+     * |        |          |Note1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to 1.
+     * |        |          |Note2: This bit can be cleared by writing 1 to it.
+     * |[4]     |TOUTWKF   |Received Data FIFO Threshold Time-out Wake-up Flag
+     * |        |          |This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up.
+     * |        |          |0 = Chip stays in power-down state.
+     * |        |          |1 = Chip wake-up from power-down state by Received Data FIFO reached threshold time-out wake-up.
+     * |        |          |Note1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to 1.
+     * |        |          |Note2: This bit can be cleared by writing 1 to it.
+     * @var UART_T::DWKCOMP
+     * Offset: 0x48  UART Incoming Data Wake-up Compensation Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |STCOMP    |Start Bit Compensation Value
+     * |        |          |These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from power-down mode.
+     * |        |          |Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set.
+     */
+
+
+    __IO uint32_t DAT;                   /*!< [0x0000] UART Receive/Transmit Buffer Register                            */
+    __IO uint32_t INTEN;                 /*!< [0x0004] UART Interrupt Enable Register                                   */
+    __IO uint32_t FIFO;                  /*!< [0x0008] UART FIFO Control Register                                       */
+    __IO uint32_t LINE;                  /*!< [0x000c] UART Line Control Register                                       */
+    __IO uint32_t MODEM;                 /*!< [0x0010] UART Modem Control Register                                      */
+    __IO uint32_t MODEMSTS;              /*!< [0x0014] UART Modem Status Register                                       */
+    __IO uint32_t FIFOSTS;               /*!< [0x0018] UART FIFO Status Register                                        */
+    __IO uint32_t INTSTS;                /*!< [0x001c] UART Interrupt Status Register                                   */
+    __IO uint32_t TOUT;                  /*!< [0x0020] UART Time-out Register                                           */
+    __IO uint32_t BAUD;                  /*!< [0x0024] UART Baud Rate Divider Register                                  */
+    __IO uint32_t IRDA;                  /*!< [0x0028] UART IrDA Control Register                                       */
+    __IO uint32_t ALTCTL;                /*!< [0x002c] UART Alternate Control/Status Register                           */
+    __IO uint32_t FUNCSEL;               /*!< [0x0030] UART Function Select Register                                    */
+    __IO uint32_t LINCTL;                /*!< [0x0034] UART LIN Control Register                                        */
+    __IO uint32_t LINSTS;                /*!< [0x0038] UART LIN Status Register                                         */
+    __IO uint32_t BRCOMP;                /*!< [0x003c] UART Baud Rate Compensation Register                             */
+    __IO uint32_t WKCTL;                 /*!< [0x0040] UART Wake-up Control Register                                    */
+    __IO uint32_t WKSTS;                 /*!< [0x0044] UART Wake-up Status Register                                     */
+    __IO uint32_t DWKCOMP;               /*!< [0x0048] UART Incoming Data Wake-up Compensation Register                 */
+
+
+} UART_T;
+
+/**
+    @addtogroup UART_CONST UART Bit Field Definition
+    Constant Definitions for UART Controller
+  @{
+*/
+
+#define UART_DAT_DAT_Pos                 (0)                                               /*!< UART_T::DAT: DAT Position              */
+#define UART_DAT_DAT_Msk                 (0xfful << UART_DAT_DAT_Pos)                      /*!< UART_T::DAT: DAT Mask                  */
+
+#define UART_DAT_PARITY_Pos              (8)                                               /*!< UART_T::DAT: PARITY Position           */
+#define UART_DAT_PARITY_Msk              (0x1ul << UART_DAT_PARITY_Pos)                    /*!< UART_T::DAT: PARITY Mask               */
+
+#define UART_INTEN_RDAIEN_Pos            (0)                                               /*!< UART_T::INTEN: RDAIEN Position         */
+#define UART_INTEN_RDAIEN_Msk            (0x1ul << UART_INTEN_RDAIEN_Pos)                  /*!< UART_T::INTEN: RDAIEN Mask             */
+
+#define UART_INTEN_THREIEN_Pos           (1)                                               /*!< UART_T::INTEN: THREIEN Position        */
+#define UART_INTEN_THREIEN_Msk           (0x1ul << UART_INTEN_THREIEN_Pos)                 /*!< UART_T::INTEN: THREIEN Mask            */
+
+#define UART_INTEN_RLSIEN_Pos            (2)                                               /*!< UART_T::INTEN: RLSIEN Position         */
+#define UART_INTEN_RLSIEN_Msk            (0x1ul << UART_INTEN_RLSIEN_Pos)                  /*!< UART_T::INTEN: RLSIEN Mask             */
+
+#define UART_INTEN_MODEMIEN_Pos          (3)                                               /*!< UART_T::INTEN: MODEMIEN Position       */
+#define UART_INTEN_MODEMIEN_Msk          (0x1ul << UART_INTEN_MODEMIEN_Pos)                /*!< UART_T::INTEN: MODEMIEN Mask           */
+
+#define UART_INTEN_RXTOIEN_Pos           (4)                                               /*!< UART_T::INTEN: RXTOIEN Position        */
+#define UART_INTEN_RXTOIEN_Msk           (0x1ul << UART_INTEN_RXTOIEN_Pos)                 /*!< UART_T::INTEN: RXTOIEN Mask            */
+
+#define UART_INTEN_BUFERRIEN_Pos         (5)                                               /*!< UART_T::INTEN: BUFERRIEN Position      */
+#define UART_INTEN_BUFERRIEN_Msk         (0x1ul << UART_INTEN_BUFERRIEN_Pos)               /*!< UART_T::INTEN: BUFERRIEN Mask          */
+
+#define UART_INTEN_WKIEN_Pos             (6)                                               /*!< UART_T::INTEN: WKIEN Position          */
+#define UART_INTEN_WKIEN_Msk             (0x1ul << UART_INTEN_WKIEN_Pos)                   /*!< UART_T::INTEN: WKIEN Mask              */
+
+#define UART_INTEN_LINIEN_Pos            (8)                                               /*!< UART_T::INTEN: LINIEN Position         */
+#define UART_INTEN_LINIEN_Msk            (0x1ul << UART_INTEN_LINIEN_Pos)                  /*!< UART_T::INTEN: LINIEN Mask             */
+
+#define UART_INTEN_TOCNTEN_Pos           (11)                                              /*!< UART_T::INTEN: TOCNTEN Position        */
+#define UART_INTEN_TOCNTEN_Msk           (0x1ul << UART_INTEN_TOCNTEN_Pos)                 /*!< UART_T::INTEN: TOCNTEN Mask            */
+
+#define UART_INTEN_ATORTSEN_Pos          (12)                                              /*!< UART_T::INTEN: ATORTSEN Position       */
+#define UART_INTEN_ATORTSEN_Msk          (0x1ul << UART_INTEN_ATORTSEN_Pos)                /*!< UART_T::INTEN: ATORTSEN Mask           */
+
+#define UART_INTEN_ATOCTSEN_Pos          (13)                                              /*!< UART_T::INTEN: ATOCTSEN Position       */
+#define UART_INTEN_ATOCTSEN_Msk          (0x1ul << UART_INTEN_ATOCTSEN_Pos)                /*!< UART_T::INTEN: ATOCTSEN Mask           */
+
+#define UART_INTEN_TXPDMAEN_Pos          (14)                                              /*!< UART_T::INTEN: TXPDMAEN Position       */
+#define UART_INTEN_TXPDMAEN_Msk          (0x1ul << UART_INTEN_TXPDMAEN_Pos)                /*!< UART_T::INTEN: TXPDMAEN Mask           */
+
+#define UART_INTEN_RXPDMAEN_Pos          (15)                                              /*!< UART_T::INTEN: RXPDMAEN Position       */
+#define UART_INTEN_RXPDMAEN_Msk          (0x1ul << UART_INTEN_RXPDMAEN_Pos)                /*!< UART_T::INTEN: RXPDMAEN Mask           */
+
+#define UART_INTEN_SWBEIEN_Pos           (16)                                              /*!< UART_T::INTEN: SWBEIEN Position        */
+#define UART_INTEN_SWBEIEN_Msk           (0x1ul << UART_INTEN_SWBEIEN_Pos)                 /*!< UART_T::INTEN: SWBEIEN Mask            */
+
+#define UART_INTEN_ABRIEN_Pos            (18)                                              /*!< UART_T::INTEN: ABRIEN Position         */
+#define UART_INTEN_ABRIEN_Msk            (0x1ul << UART_INTEN_ABRIEN_Pos)                  /*!< UART_T::INTEN: ABRIEN Mask             */
+
+#define UART_INTEN_TXENDIEN_Pos          (22)                                              /*!< UART_T::INTEN: TXENDIEN Position       */
+#define UART_INTEN_TXENDIEN_Msk          (0x1ul << UART_INTEN_TXENDIEN_Pos)                /*!< UART_T::INTEN: TXENDIEN Mask           */
+
+#define UART_FIFO_RXRST_Pos              (1)                                               /*!< UART_T::FIFO: RXRST Position           */
+#define UART_FIFO_RXRST_Msk              (0x1ul << UART_FIFO_RXRST_Pos)                    /*!< UART_T::FIFO: RXRST Mask               */
+
+#define UART_FIFO_TXRST_Pos              (2)                                               /*!< UART_T::FIFO: TXRST Position           */
+#define UART_FIFO_TXRST_Msk              (0x1ul << UART_FIFO_TXRST_Pos)                    /*!< UART_T::FIFO: TXRST Mask               */
+
+#define UART_FIFO_RFITL_Pos              (4)                                               /*!< UART_T::FIFO: RFITL Position           */
+#define UART_FIFO_RFITL_Msk              (0xful << UART_FIFO_RFITL_Pos)                    /*!< UART_T::FIFO: RFITL Mask               */
+
+#define UART_FIFO_RXOFF_Pos              (8)                                               /*!< UART_T::FIFO: RXOFF Position           */
+#define UART_FIFO_RXOFF_Msk              (0x1ul << UART_FIFO_RXOFF_Pos)                    /*!< UART_T::FIFO: RXOFF Mask               */
+
+#define UART_FIFO_RTSTRGLV_Pos           (16)                                              /*!< UART_T::FIFO: RTSTRGLV Position        */
+#define UART_FIFO_RTSTRGLV_Msk           (0xful << UART_FIFO_RTSTRGLV_Pos)                 /*!< UART_T::FIFO: RTSTRGLV Mask            */
+
+#define UART_LINE_WLS_Pos                (0)                                               /*!< UART_T::LINE: WLS Position             */
+#define UART_LINE_WLS_Msk                (0x3ul << UART_LINE_WLS_Pos)                      /*!< UART_T::LINE: WLS Mask                 */
+
+#define UART_LINE_NSB_Pos                (2)                                               /*!< UART_T::LINE: NSB Position             */
+#define UART_LINE_NSB_Msk                (0x1ul << UART_LINE_NSB_Pos)                      /*!< UART_T::LINE: NSB Mask                 */
+
+#define UART_LINE_PBE_Pos                (3)                                               /*!< UART_T::LINE: PBE Position             */
+#define UART_LINE_PBE_Msk                (0x1ul << UART_LINE_PBE_Pos)                      /*!< UART_T::LINE: PBE Mask                 */
+
+#define UART_LINE_EPE_Pos                (4)                                               /*!< UART_T::LINE: EPE Position             */
+#define UART_LINE_EPE_Msk                (0x1ul << UART_LINE_EPE_Pos)                      /*!< UART_T::LINE: EPE Mask                 */
+
+#define UART_LINE_SPE_Pos                (5)                                               /*!< UART_T::LINE: SPE Position             */
+#define UART_LINE_SPE_Msk                (0x1ul << UART_LINE_SPE_Pos)                      /*!< UART_T::LINE: SPE Mask                 */
+
+#define UART_LINE_BCB_Pos                (6)                                               /*!< UART_T::LINE: BCB Position             */
+#define UART_LINE_BCB_Msk                (0x1ul << UART_LINE_BCB_Pos)                      /*!< UART_T::LINE: BCB Mask                 */
+
+#define UART_LINE_PSS_Pos                (7)                                               /*!< UART_T::LINE: PSS Position             */
+#define UART_LINE_PSS_Msk                (0x1ul << UART_LINE_PSS_Pos)                      /*!< UART_T::LINE: PSS Mask                 */
+
+#define UART_LINE_TXDINV_Pos             (8)                                               /*!< UART_T::LINE: TXDINV Position          */
+#define UART_LINE_TXDINV_Msk             (0x1ul << UART_LINE_TXDINV_Pos)                   /*!< UART_T::LINE: TXDINV Mask              */
+
+#define UART_LINE_RXDINV_Pos             (9)                                               /*!< UART_T::LINE: RXDINV Position          */
+#define UART_LINE_RXDINV_Msk             (0x1ul << UART_LINE_RXDINV_Pos)                   /*!< UART_T::LINE: RXDINV Mask              */
+
+#define UART_MODEM_RTS_Pos               (1)                                               /*!< UART_T::MODEM: RTS Position            */
+#define UART_MODEM_RTS_Msk               (0x1ul << UART_MODEM_RTS_Pos)                     /*!< UART_T::MODEM: RTS Mask                */
+
+#define UART_MODEM_RTSACTLV_Pos          (9)                                               /*!< UART_T::MODEM: RTSACTLV Position       */
+#define UART_MODEM_RTSACTLV_Msk          (0x1ul << UART_MODEM_RTSACTLV_Pos)                /*!< UART_T::MODEM: RTSACTLV Mask           */
+
+#define UART_MODEM_RTSSTS_Pos            (13)                                              /*!< UART_T::MODEM: RTSSTS Position         */
+#define UART_MODEM_RTSSTS_Msk            (0x1ul << UART_MODEM_RTSSTS_Pos)                  /*!< UART_T::MODEM: RTSSTS Mask             */
+
+#define UART_MODEMSTS_CTSDETF_Pos        (0)                                               /*!< UART_T::MODEMSTS: CTSDETF Position     */
+#define UART_MODEMSTS_CTSDETF_Msk        (0x1ul << UART_MODEMSTS_CTSDETF_Pos)              /*!< UART_T::MODEMSTS: CTSDETF Mask         */
+
+#define UART_MODEMSTS_CTSSTS_Pos         (4)                                               /*!< UART_T::MODEMSTS: CTSSTS Position      */
+#define UART_MODEMSTS_CTSSTS_Msk         (0x1ul << UART_MODEMSTS_CTSSTS_Pos)               /*!< UART_T::MODEMSTS: CTSSTS Mask          */
+
+#define UART_MODEMSTS_CTSACTLV_Pos       (8)                                               /*!< UART_T::MODEMSTS: CTSACTLV Position    */
+#define UART_MODEMSTS_CTSACTLV_Msk       (0x1ul << UART_MODEMSTS_CTSACTLV_Pos)             /*!< UART_T::MODEMSTS: CTSACTLV Mask        */
+
+#define UART_FIFOSTS_RXOVIF_Pos          (0)                                               /*!< UART_T::FIFOSTS: RXOVIF Position       */
+#define UART_FIFOSTS_RXOVIF_Msk          (0x1ul << UART_FIFOSTS_RXOVIF_Pos)                /*!< UART_T::FIFOSTS: RXOVIF Mask           */
+
+#define UART_FIFOSTS_ABRDIF_Pos          (1)                                               /*!< UART_T::FIFOSTS: ABRDIF Position       */
+#define UART_FIFOSTS_ABRDIF_Msk          (0x1ul << UART_FIFOSTS_ABRDIF_Pos)                /*!< UART_T::FIFOSTS: ABRDIF Mask           */
+
+#define UART_FIFOSTS_ABRDTOIF_Pos        (2)                                               /*!< UART_T::FIFOSTS: ABRDTOIF Position     */
+#define UART_FIFOSTS_ABRDTOIF_Msk        (0x1ul << UART_FIFOSTS_ABRDTOIF_Pos)              /*!< UART_T::FIFOSTS: ABRDTOIF Mask         */
+
+#define UART_FIFOSTS_ADDRDETF_Pos        (3)                                               /*!< UART_T::FIFOSTS: ADDRDETF Position     */
+#define UART_FIFOSTS_ADDRDETF_Msk        (0x1ul << UART_FIFOSTS_ADDRDETF_Pos)              /*!< UART_T::FIFOSTS: ADDRDETF Mask         */
+
+#define UART_FIFOSTS_PEF_Pos             (4)                                               /*!< UART_T::FIFOSTS: PEF Position          */
+#define UART_FIFOSTS_PEF_Msk             (0x1ul << UART_FIFOSTS_PEF_Pos)                   /*!< UART_T::FIFOSTS: PEF Mask              */
+
+#define UART_FIFOSTS_FEF_Pos             (5)                                               /*!< UART_T::FIFOSTS: FEF Position          */
+#define UART_FIFOSTS_FEF_Msk             (0x1ul << UART_FIFOSTS_FEF_Pos)                   /*!< UART_T::FIFOSTS: FEF Mask              */
+
+#define UART_FIFOSTS_BIF_Pos             (6)                                               /*!< UART_T::FIFOSTS: BIF Position          */
+#define UART_FIFOSTS_BIF_Msk             (0x1ul << UART_FIFOSTS_BIF_Pos)                   /*!< UART_T::FIFOSTS: BIF Mask              */
+
+#define UART_FIFOSTS_RXPTR_Pos           (8)                                               /*!< UART_T::FIFOSTS: RXPTR Position        */
+#define UART_FIFOSTS_RXPTR_Msk           (0x3ful << UART_FIFOSTS_RXPTR_Pos)                /*!< UART_T::FIFOSTS: RXPTR Mask            */
+
+#define UART_FIFOSTS_RXEMPTY_Pos         (14)                                              /*!< UART_T::FIFOSTS: RXEMPTY Position      */
+#define UART_FIFOSTS_RXEMPTY_Msk         (0x1ul << UART_FIFOSTS_RXEMPTY_Pos)               /*!< UART_T::FIFOSTS: RXEMPTY Mask          */
+
+#define UART_FIFOSTS_RXFULL_Pos          (15)                                              /*!< UART_T::FIFOSTS: RXFULL Position       */
+#define UART_FIFOSTS_RXFULL_Msk          (0x1ul << UART_FIFOSTS_RXFULL_Pos)                /*!< UART_T::FIFOSTS: RXFULL Mask           */
+
+#define UART_FIFOSTS_TXPTR_Pos           (16)                                              /*!< UART_T::FIFOSTS: TXPTR Position        */
+#define UART_FIFOSTS_TXPTR_Msk           (0x3ful << UART_FIFOSTS_TXPTR_Pos)                /*!< UART_T::FIFOSTS: TXPTR Mask            */
+
+#define UART_FIFOSTS_TXEMPTY_Pos         (22)                                              /*!< UART_T::FIFOSTS: TXEMPTY Position      */
+#define UART_FIFOSTS_TXEMPTY_Msk         (0x1ul << UART_FIFOSTS_TXEMPTY_Pos)               /*!< UART_T::FIFOSTS: TXEMPTY Mask          */
+
+#define UART_FIFOSTS_TXFULL_Pos          (23)                                              /*!< UART_T::FIFOSTS: TXFULL Position       */
+#define UART_FIFOSTS_TXFULL_Msk          (0x1ul << UART_FIFOSTS_TXFULL_Pos)                /*!< UART_T::FIFOSTS: TXFULL Mask           */
+
+#define UART_FIFOSTS_TXOVIF_Pos          (24)                                              /*!< UART_T::FIFOSTS: TXOVIF Position       */
+#define UART_FIFOSTS_TXOVIF_Msk          (0x1ul << UART_FIFOSTS_TXOVIF_Pos)                /*!< UART_T::FIFOSTS: TXOVIF Mask           */
+
+#define UART_FIFOSTS_TXEMPTYF_Pos        (28)                                              /*!< UART_T::FIFOSTS: TXEMPTYF Position     */
+#define UART_FIFOSTS_TXEMPTYF_Msk        (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos)              /*!< UART_T::FIFOSTS: TXEMPTYF Mask         */
+
+#define UART_FIFOSTS_RXIDLE_Pos          (29)                                              /*!< UART_T::FIFOSTS: RXIDLE Position       */
+#define UART_FIFOSTS_RXIDLE_Msk          (0x1ul << UART_FIFOSTS_RXIDLE_Pos)                /*!< UART_T::FIFOSTS: RXIDLE Mask           */
+
+#define UART_FIFOSTS_TXRXACT_Pos         (31)                                              /*!< UART_T::FIFOSTS: TXRXACT Position      */
+#define UART_FIFOSTS_TXRXACT_Msk         (0x1ul << UART_FIFOSTS_TXRXACT_Pos)               /*!< UART_T::FIFOSTS: TXRXACT Mask          */
+
+#define UART_INTSTS_RDAIF_Pos            (0)                                               /*!< UART_T::INTSTS: RDAIF Position         */
+#define UART_INTSTS_RDAIF_Msk            (0x1ul << UART_INTSTS_RDAIF_Pos)                  /*!< UART_T::INTSTS: RDAIF Mask             */
+
+#define UART_INTSTS_THREIF_Pos           (1)                                               /*!< UART_T::INTSTS: THREIF Position        */
+#define UART_INTSTS_THREIF_Msk           (0x1ul << UART_INTSTS_THREIF_Pos)                 /*!< UART_T::INTSTS: THREIF Mask            */
+
+#define UART_INTSTS_RLSIF_Pos            (2)                                               /*!< UART_T::INTSTS: RLSIF Position         */
+#define UART_INTSTS_RLSIF_Msk            (0x1ul << UART_INTSTS_RLSIF_Pos)                  /*!< UART_T::INTSTS: RLSIF Mask             */
+
+#define UART_INTSTS_MODEMIF_Pos          (3)                                               /*!< UART_T::INTSTS: MODEMIF Position       */
+#define UART_INTSTS_MODEMIF_Msk          (0x1ul << UART_INTSTS_MODEMIF_Pos)                /*!< UART_T::INTSTS: MODEMIF Mask           */
+
+#define UART_INTSTS_RXTOIF_Pos           (4)                                               /*!< UART_T::INTSTS: RXTOIF Position        */
+#define UART_INTSTS_RXTOIF_Msk           (0x1ul << UART_INTSTS_RXTOIF_Pos)                 /*!< UART_T::INTSTS: RXTOIF Mask            */
+
+#define UART_INTSTS_BUFERRIF_Pos         (5)                                               /*!< UART_T::INTSTS: BUFERRIF Position      */
+#define UART_INTSTS_BUFERRIF_Msk         (0x1ul << UART_INTSTS_BUFERRIF_Pos)               /*!< UART_T::INTSTS: BUFERRIF Mask          */
+
+#define UART_INTSTS_WKIF_Pos             (6)                                               /*!< UART_T::INTSTS: WKIF Position          */
+#define UART_INTSTS_WKIF_Msk             (0x1ul << UART_INTSTS_WKIF_Pos)                   /*!< UART_T::INTSTS: WKIF Mask              */
+
+#define UART_INTSTS_LINIF_Pos            (7)                                               /*!< UART_T::INTSTS: LINIF Position         */
+#define UART_INTSTS_LINIF_Msk            (0x1ul << UART_INTSTS_LINIF_Pos)                  /*!< UART_T::INTSTS: LINIF Mask             */
+
+#define UART_INTSTS_RDAINT_Pos           (8)                                               /*!< UART_T::INTSTS: RDAINT Position        */
+#define UART_INTSTS_RDAINT_Msk           (0x1ul << UART_INTSTS_RDAINT_Pos)                 /*!< UART_T::INTSTS: RDAINT Mask            */
+
+#define UART_INTSTS_THREINT_Pos          (9)                                               /*!< UART_T::INTSTS: THREINT Position       */
+#define UART_INTSTS_THREINT_Msk          (0x1ul << UART_INTSTS_THREINT_Pos)                /*!< UART_T::INTSTS: THREINT Mask           */
+
+#define UART_INTSTS_RLSINT_Pos           (10)                                              /*!< UART_T::INTSTS: RLSINT Position        */
+#define UART_INTSTS_RLSINT_Msk           (0x1ul << UART_INTSTS_RLSINT_Pos)                 /*!< UART_T::INTSTS: RLSINT Mask            */
+
+#define UART_INTSTS_MODEMINT_Pos         (11)                                              /*!< UART_T::INTSTS: MODEMINT Position      */
+#define UART_INTSTS_MODEMINT_Msk         (0x1ul << UART_INTSTS_MODEMINT_Pos)               /*!< UART_T::INTSTS: MODEMINT Mask          */
+
+#define UART_INTSTS_RXTOINT_Pos          (12)                                              /*!< UART_T::INTSTS: RXTOINT Position       */
+#define UART_INTSTS_RXTOINT_Msk          (0x1ul << UART_INTSTS_RXTOINT_Pos)                /*!< UART_T::INTSTS: RXTOINT Mask           */
+
+#define UART_INTSTS_BUFERRINT_Pos        (13)                                              /*!< UART_T::INTSTS: BUFERRINT Position     */
+#define UART_INTSTS_BUFERRINT_Msk        (0x1ul << UART_INTSTS_BUFERRINT_Pos)              /*!< UART_T::INTSTS: BUFERRINT Mask         */
+
+#define UART_INTSTS_WKINT_Pos            (14)                                              /*!< UART_T::INTSTS: WKINT Position         */
+#define UART_INTSTS_WKINT_Msk            (0x1ul << UART_INTSTS_WKINT_Pos)                  /*!< UART_T::INTSTS: WKINT Mask             */
+
+#define UART_INTSTS_LININT_Pos           (15)                                              /*!< UART_T::INTSTS: LININT Position        */
+#define UART_INTSTS_LININT_Msk           (0x1ul << UART_INTSTS_LININT_Pos)                 /*!< UART_T::INTSTS: LININT Mask            */
+
+#define UART_INTSTS_SWBEIF_Pos           (16)                                              /*!< UART_T::INTSTS: SWBEIF Position        */
+#define UART_INTSTS_SWBEIF_Msk           (0x1ul << UART_INTSTS_SWBEIF_Pos)                 /*!< UART_T::INTSTS: SWBEIF Mask            */
+
+#define UART_INTSTS_HWRLSIF_Pos          (18)                                              /*!< UART_T::INTSTS: HWRLSIF Position       */
+#define UART_INTSTS_HWRLSIF_Msk          (0x1ul << UART_INTSTS_HWRLSIF_Pos)                /*!< UART_T::INTSTS: HWRLSIF Mask           */
+
+#define UART_INTSTS_HWMODIF_Pos          (19)                                              /*!< UART_T::INTSTS: HWMODIF Position       */
+#define UART_INTSTS_HWMODIF_Msk          (0x1ul << UART_INTSTS_HWMODIF_Pos)                /*!< UART_T::INTSTS: HWMODIF Mask           */
+
+#define UART_INTSTS_HWTOIF_Pos           (20)                                              /*!< UART_T::INTSTS: HWTOIF Position        */
+#define UART_INTSTS_HWTOIF_Msk           (0x1ul << UART_INTSTS_HWTOIF_Pos)                 /*!< UART_T::INTSTS: HWTOIF Mask            */
+
+#define UART_INTSTS_HWBUFEIF_Pos         (21)                                              /*!< UART_T::INTSTS: HWBUFEIF Position      */
+#define UART_INTSTS_HWBUFEIF_Msk         (0x1ul << UART_INTSTS_HWBUFEIF_Pos)               /*!< UART_T::INTSTS: HWBUFEIF Mask          */
+
+#define UART_INTSTS_TXENDIF_Pos          (22)                                              /*!< UART_T::INTSTS: TXENDIF Position       */
+#define UART_INTSTS_TXENDIF_Msk          (0x1ul << UART_INTSTS_TXENDIF_Pos)                /*!< UART_T::INTSTS: TXENDIF Mask           */
+
+#define UART_INTSTS_SWBEINT_Pos          (24)                                              /*!< UART_T::INTSTS: SWBEINT Position       */
+#define UART_INTSTS_SWBEINT_Msk          (0x1ul << UART_INTSTS_SWBEINT_Pos)                /*!< UART_T::INTSTS: SWBEINT Mask           */
+
+#define UART_INTSTS_HWRLSINT_Pos         (26)                                              /*!< UART_T::INTSTS: HWRLSINT Position      */
+#define UART_INTSTS_HWRLSINT_Msk         (0x1ul << UART_INTSTS_HWRLSINT_Pos)               /*!< UART_T::INTSTS: HWRLSINT Mask          */
+
+#define UART_INTSTS_HWMODINT_Pos         (27)                                              /*!< UART_T::INTSTS: HWMODINT Position      */
+#define UART_INTSTS_HWMODINT_Msk         (0x1ul << UART_INTSTS_HWMODINT_Pos)               /*!< UART_T::INTSTS: HWMODINT Mask          */
+
+#define UART_INTSTS_HWTOINT_Pos          (28)                                              /*!< UART_T::INTSTS: HWTOINT Position       */
+#define UART_INTSTS_HWTOINT_Msk          (0x1ul << UART_INTSTS_HWTOINT_Pos)                /*!< UART_T::INTSTS: HWTOINT Mask           */
+
+#define UART_INTSTS_HWBUFEINT_Pos        (29)                                              /*!< UART_T::INTSTS: HWBUFEINT Position     */
+#define UART_INTSTS_HWBUFEINT_Msk        (0x1ul << UART_INTSTS_HWBUFEINT_Pos)              /*!< UART_T::INTSTS: HWBUFEINT Mask         */
+
+#define UART_INTSTS_TXENDINT_Pos         (30)                                              /*!< UART_T::INTSTS: TXENDINT Position      */
+#define UART_INTSTS_TXENDINT_Msk         (0x1ul << UART_INTSTS_TXENDINT_Pos)               /*!< UART_T::INTSTS: TXENDINT Mask          */
+
+#define UART_INTSTS_ABRINT_Pos           (31)                                              /*!< UART_T::INTSTS: ABRINT Position        */
+#define UART_INTSTS_ABRINT_Msk           (0x1ul << UART_INTSTS_ABRINT_Pos)                 /*!< UART_T::INTSTS: ABRINT Mask            */
+
+#define UART_TOUT_TOIC_Pos               (0)                                               /*!< UART_T::TOUT: TOIC Position            */
+#define UART_TOUT_TOIC_Msk               (0xfful << UART_TOUT_TOIC_Pos)                    /*!< UART_T::TOUT: TOIC Mask                */
+
+#define UART_TOUT_DLY_Pos                (8)                                               /*!< UART_T::TOUT: DLY Position             */
+#define UART_TOUT_DLY_Msk                (0xfful << UART_TOUT_DLY_Pos)                     /*!< UART_T::TOUT: DLY Mask                 */
+
+#define UART_BAUD_BRD_Pos                (0)                                               /*!< UART_T::BAUD: BRD Position             */
+#define UART_BAUD_BRD_Msk                (0xfffful << UART_BAUD_BRD_Pos)                   /*!< UART_T::BAUD: BRD Mask                 */
+
+#define UART_BAUD_EDIVM1_Pos             (24)                                              /*!< UART_T::BAUD: EDIVM1 Position          */
+#define UART_BAUD_EDIVM1_Msk             (0xful << UART_BAUD_EDIVM1_Pos)                   /*!< UART_T::BAUD: EDIVM1 Mask              */
+
+#define UART_BAUD_BAUDM0_Pos             (28)                                              /*!< UART_T::BAUD: BAUDM0 Position          */
+#define UART_BAUD_BAUDM0_Msk             (0x1ul << UART_BAUD_BAUDM0_Pos)                   /*!< UART_T::BAUD: BAUDM0 Mask              */
+
+#define UART_BAUD_BAUDM1_Pos             (29)                                              /*!< UART_T::BAUD: BAUDM1 Position          */
+#define UART_BAUD_BAUDM1_Msk             (0x1ul << UART_BAUD_BAUDM1_Pos)                   /*!< UART_T::BAUD: BAUDM1 Mask              */
+
+#define UART_IRDA_TXEN_Pos               (1)                                               /*!< UART_T::IRDA: TXEN Position            */
+#define UART_IRDA_TXEN_Msk               (0x1ul << UART_IRDA_TXEN_Pos)                     /*!< UART_T::IRDA: TXEN Mask                */
+
+#define UART_IRDA_TXINV_Pos              (5)                                               /*!< UART_T::IRDA: TXINV Position           */
+#define UART_IRDA_TXINV_Msk              (0x1ul << UART_IRDA_TXINV_Pos)                    /*!< UART_T::IRDA: TXINV Mask               */
+
+#define UART_IRDA_RXINV_Pos              (6)                                               /*!< UART_T::IRDA: RXINV Position           */
+#define UART_IRDA_RXINV_Msk              (0x1ul << UART_IRDA_RXINV_Pos)                    /*!< UART_T::IRDA: RXINV Mask               */
+
+#define UART_ALTCTL_BRKFL_Pos            (0)                                               /*!< UART_T::ALTCTL: BRKFL Position         */
+#define UART_ALTCTL_BRKFL_Msk            (0xful << UART_ALTCTL_BRKFL_Pos)                  /*!< UART_T::ALTCTL: BRKFL Mask             */
+
+#define UART_ALTCTL_LINRXEN_Pos          (6)                                               /*!< UART_T::ALTCTL: LINRXEN Position       */
+#define UART_ALTCTL_LINRXEN_Msk          (0x1ul << UART_ALTCTL_LINRXEN_Pos)                /*!< UART_T::ALTCTL: LINRXEN Mask           */
+
+#define UART_ALTCTL_LINTXEN_Pos          (7)                                               /*!< UART_T::ALTCTL: LINTXEN Position       */
+#define UART_ALTCTL_LINTXEN_Msk          (0x1ul << UART_ALTCTL_LINTXEN_Pos)                /*!< UART_T::ALTCTL: LINTXEN Mask           */
+
+#define UART_ALTCTL_RS485NMM_Pos         (8)                                               /*!< UART_T::ALTCTL: RS485NMM Position      */
+#define UART_ALTCTL_RS485NMM_Msk         (0x1ul << UART_ALTCTL_RS485NMM_Pos)               /*!< UART_T::ALTCTL: RS485NMM Mask          */
+
+#define UART_ALTCTL_RS485AAD_Pos         (9)                                               /*!< UART_T::ALTCTL: RS485AAD Position      */
+#define UART_ALTCTL_RS485AAD_Msk         (0x1ul << UART_ALTCTL_RS485AAD_Pos)               /*!< UART_T::ALTCTL: RS485AAD Mask          */
+
+#define UART_ALTCTL_RS485AUD_Pos         (10)                                              /*!< UART_T::ALTCTL: RS485AUD Position      */
+#define UART_ALTCTL_RS485AUD_Msk         (0x1ul << UART_ALTCTL_RS485AUD_Pos)               /*!< UART_T::ALTCTL: RS485AUD Mask          */
+
+#define UART_ALTCTL_ADDRDEN_Pos          (15)                                              /*!< UART_T::ALTCTL: ADDRDEN Position       */
+#define UART_ALTCTL_ADDRDEN_Msk          (0x1ul << UART_ALTCTL_ADDRDEN_Pos)                /*!< UART_T::ALTCTL: ADDRDEN Mask           */
+
+#define UART_ALTCTL_ABRIF_Pos            (17)                                              /*!< UART_T::ALTCTL: ABRIF Position         */
+#define UART_ALTCTL_ABRIF_Msk            (0x1ul << UART_ALTCTL_ABRIF_Pos)                  /*!< UART_T::ALTCTL: ABRIF Mask             */
+
+#define UART_ALTCTL_ABRDEN_Pos           (18)                                              /*!< UART_T::ALTCTL: ABRDEN Position        */
+#define UART_ALTCTL_ABRDEN_Msk           (0x1ul << UART_ALTCTL_ABRDEN_Pos)                 /*!< UART_T::ALTCTL: ABRDEN Mask            */
+
+#define UART_ALTCTL_ABRDBITS_Pos         (19)                                              /*!< UART_T::ALTCTL: ABRDBITS Position      */
+#define UART_ALTCTL_ABRDBITS_Msk         (0x3ul << UART_ALTCTL_ABRDBITS_Pos)               /*!< UART_T::ALTCTL: ABRDBITS Mask          */
+
+#define UART_ALTCTL_ADDRMV_Pos           (24)                                              /*!< UART_T::ALTCTL: ADDRMV Position        */
+#define UART_ALTCTL_ADDRMV_Msk           (0xfful << UART_ALTCTL_ADDRMV_Pos)                /*!< UART_T::ALTCTL: ADDRMV Mask            */
+
+#define UART_FUNCSEL_FUNCSEL_Pos         (0)                                               /*!< UART_T::FUNCSEL: FUNCSEL Position      */
+#define UART_FUNCSEL_FUNCSEL_Msk         (0x7ul << UART_FUNCSEL_FUNCSEL_Pos)               /*!< UART_T::FUNCSEL: FUNCSEL Mask          */
+
+#define UART_FUNCSEL_TXRXDIS_Pos         (3)                                               /*!< UART_T::FUNCSEL: TXRXDIS Position      */
+#define UART_FUNCSEL_TXRXDIS_Msk         (0x1ul << UART_FUNCSEL_TXRXDIS_Pos)               /*!< UART_T::FUNCSEL: TXRXDIS Mask          */
+
+#define UART_FUNCSEL_DGE_Pos             (6)                                               /*!< UART_T::FUNCSEL: DGE Position          */
+#define UART_FUNCSEL_DGE_Msk             (0x1ul << UART_FUNCSEL_DGE_Pos)                   /*!< UART_T::FUNCSEL: DGE Mask              */
+
+#define UART_LINCTL_SLVEN_Pos            (0)                                               /*!< UART_T::LINCTL: SLVEN Position         */
+#define UART_LINCTL_SLVEN_Msk            (0x1ul << UART_LINCTL_SLVEN_Pos)                  /*!< UART_T::LINCTL: SLVEN Mask             */
+
+#define UART_LINCTL_SLVHDEN_Pos          (1)                                               /*!< UART_T::LINCTL: SLVHDEN Position       */
+#define UART_LINCTL_SLVHDEN_Msk          (0x1ul << UART_LINCTL_SLVHDEN_Pos)                /*!< UART_T::LINCTL: SLVHDEN Mask           */
+
+#define UART_LINCTL_SLVAREN_Pos          (2)                                               /*!< UART_T::LINCTL: SLVAREN Position       */
+#define UART_LINCTL_SLVAREN_Msk          (0x1ul << UART_LINCTL_SLVAREN_Pos)                /*!< UART_T::LINCTL: SLVAREN Mask           */
+
+#define UART_LINCTL_SLVDUEN_Pos          (3)                                               /*!< UART_T::LINCTL: SLVDUEN Position       */
+#define UART_LINCTL_SLVDUEN_Msk          (0x1ul << UART_LINCTL_SLVDUEN_Pos)                /*!< UART_T::LINCTL: SLVDUEN Mask           */
+
+#define UART_LINCTL_MUTE_Pos             (4)                                               /*!< UART_T::LINCTL: MUTE Position          */
+#define UART_LINCTL_MUTE_Msk             (0x1ul << UART_LINCTL_MUTE_Pos)                   /*!< UART_T::LINCTL: MUTE Mask              */
+
+#define UART_LINCTL_SENDH_Pos            (8)                                               /*!< UART_T::LINCTL: SENDH Position         */
+#define UART_LINCTL_SENDH_Msk            (0x1ul << UART_LINCTL_SENDH_Pos)                  /*!< UART_T::LINCTL: SENDH Mask             */
+
+#define UART_LINCTL_IDPEN_Pos            (9)                                               /*!< UART_T::LINCTL: IDPEN Position         */
+#define UART_LINCTL_IDPEN_Msk            (0x1ul << UART_LINCTL_IDPEN_Pos)                  /*!< UART_T::LINCTL: IDPEN Mask             */
+
+#define UART_LINCTL_BRKDETEN_Pos         (10)                                              /*!< UART_T::LINCTL: BRKDETEN Position      */
+#define UART_LINCTL_BRKDETEN_Msk         (0x1ul << UART_LINCTL_BRKDETEN_Pos)               /*!< UART_T::LINCTL: BRKDETEN Mask          */
+
+#define UART_LINCTL_LINRXOFF_Pos         (11)                                              /*!< UART_T::LINCTL: LINRXOFF Position      */
+#define UART_LINCTL_LINRXOFF_Msk         (0x1ul << UART_LINCTL_LINRXOFF_Pos)               /*!< UART_T::LINCTL: LINRXOFF Mask          */
+
+#define UART_LINCTL_BITERREN_Pos         (12)                                              /*!< UART_T::LINCTL: BITERREN Position      */
+#define UART_LINCTL_BITERREN_Msk         (0x1ul << UART_LINCTL_BITERREN_Pos)               /*!< UART_T::LINCTL: BITERREN Mask          */
+
+#define UART_LINCTL_BRKFL_Pos            (16)                                              /*!< UART_T::LINCTL: BRKFL Position         */
+#define UART_LINCTL_BRKFL_Msk            (0xful << UART_LINCTL_BRKFL_Pos)                  /*!< UART_T::LINCTL: BRKFL Mask             */
+
+#define UART_LINCTL_BSL_Pos              (20)                                              /*!< UART_T::LINCTL: BSL Position           */
+#define UART_LINCTL_BSL_Msk              (0x3ul << UART_LINCTL_BSL_Pos)                    /*!< UART_T::LINCTL: BSL Mask               */
+
+#define UART_LINCTL_HSEL_Pos             (22)                                              /*!< UART_T::LINCTL: HSEL Position          */
+#define UART_LINCTL_HSEL_Msk             (0x3ul << UART_LINCTL_HSEL_Pos)                   /*!< UART_T::LINCTL: HSEL Mask              */
+
+#define UART_LINCTL_PID_Pos              (24)                                              /*!< UART_T::LINCTL: PID Position           */
+#define UART_LINCTL_PID_Msk              (0xfful << UART_LINCTL_PID_Pos)                   /*!< UART_T::LINCTL: PID Mask               */
+
+#define UART_LINSTS_SLVHDETF_Pos         (0)                                               /*!< UART_T::LINSTS: SLVHDETF Position      */
+#define UART_LINSTS_SLVHDETF_Msk         (0x1ul << UART_LINSTS_SLVHDETF_Pos)               /*!< UART_T::LINSTS: SLVHDETF Mask          */
+
+#define UART_LINSTS_SLVHEF_Pos           (1)                                               /*!< UART_T::LINSTS: SLVHEF Position        */
+#define UART_LINSTS_SLVHEF_Msk           (0x1ul << UART_LINSTS_SLVHEF_Pos)                 /*!< UART_T::LINSTS: SLVHEF Mask            */
+
+#define UART_LINSTS_SLVIDPEF_Pos         (2)                                               /*!< UART_T::LINSTS: SLVIDPEF Position      */
+#define UART_LINSTS_SLVIDPEF_Msk         (0x1ul << UART_LINSTS_SLVIDPEF_Pos)               /*!< UART_T::LINSTS: SLVIDPEF Mask          */
+
+#define UART_LINSTS_SLVSYNCF_Pos         (3)                                               /*!< UART_T::LINSTS: SLVSYNCF Position      */
+#define UART_LINSTS_SLVSYNCF_Msk         (0x1ul << UART_LINSTS_SLVSYNCF_Pos)               /*!< UART_T::LINSTS: SLVSYNCF Mask          */
+
+#define UART_LINSTS_BRKDETF_Pos          (8)                                               /*!< UART_T::LINSTS: BRKDETF Position       */
+#define UART_LINSTS_BRKDETF_Msk          (0x1ul << UART_LINSTS_BRKDETF_Pos)                /*!< UART_T::LINSTS: BRKDETF Mask           */
+
+#define UART_LINSTS_BITEF_Pos            (9)                                               /*!< UART_T::LINSTS: BITEF Position         */
+#define UART_LINSTS_BITEF_Msk            (0x1ul << UART_LINSTS_BITEF_Pos)                  /*!< UART_T::LINSTS: BITEF Mask             */
+
+#define UART_BRCOMP_BRCOMP_Pos           (0)                                               /*!< UART_T::BRCOMP: BRCOMP Position        */
+#define UART_BRCOMP_BRCOMP_Msk           (0x1fful << UART_BRCOMP_BRCOMP_Pos)               /*!< UART_T::BRCOMP: BRCOMP Mask            */
+
+#define UART_BRCOMP_BRCOMPDEC_Pos        (31)                                              /*!< UART_T::BRCOMP: BRCOMPDEC Position     */
+#define UART_BRCOMP_BRCOMPDEC_Msk        (0x1ul << UART_BRCOMP_BRCOMPDEC_Pos)              /*!< UART_T::BRCOMP: BRCOMPDEC Mask         */
+
+#define UART_WKCTL_WKCTSEN_Pos           (0)                                               /*!< UART_T::WKCTL: WKCTSEN Position        */
+#define UART_WKCTL_WKCTSEN_Msk           (0x1ul << UART_WKCTL_WKCTSEN_Pos)                 /*!< UART_T::WKCTL: WKCTSEN Mask            */
+
+#define UART_WKCTL_WKDATEN_Pos           (1)                                               /*!< UART_T::WKCTL: WKDATEN Position        */
+#define UART_WKCTL_WKDATEN_Msk           (0x1ul << UART_WKCTL_WKDATEN_Pos)                 /*!< UART_T::WKCTL: WKDATEN Mask            */
+
+#define UART_WKCTL_WKRFRTEN_Pos          (2)                                               /*!< UART_T::WKCTL: WKRFRTEN Position       */
+#define UART_WKCTL_WKRFRTEN_Msk          (0x1ul << UART_WKCTL_WKRFRTEN_Pos)                /*!< UART_T::WKCTL: WKRFRTEN Mask           */
+
+#define UART_WKCTL_WKRS485EN_Pos         (3)                                               /*!< UART_T::WKCTL: WKRS485EN Position      */
+#define UART_WKCTL_WKRS485EN_Msk         (0x1ul << UART_WKCTL_WKRS485EN_Pos)               /*!< UART_T::WKCTL: WKRS485EN Mask          */
+
+#define UART_WKCTL_WKTOUTEN_Pos          (4)                                               /*!< UART_T::WKCTL: WKTOUTEN Position       */
+#define UART_WKCTL_WKTOUTEN_Msk          (0x1ul << UART_WKCTL_WKTOUTEN_Pos)                /*!< UART_T::WKCTL: WKTOUTEN Mask           */
+
+#define UART_WKSTS_CTSWKF_Pos            (0)                                               /*!< UART_T::WKSTS: CTSWKF Position         */
+#define UART_WKSTS_CTSWKF_Msk            (0x1ul << UART_WKSTS_CTSWKF_Pos)                  /*!< UART_T::WKSTS: CTSWKF Mask             */
+
+#define UART_WKSTS_DATWKF_Pos            (1)                                               /*!< UART_T::WKSTS: DATWKF Position         */
+#define UART_WKSTS_DATWKF_Msk            (0x1ul << UART_WKSTS_DATWKF_Pos)                  /*!< UART_T::WKSTS: DATWKF Mask             */
+
+#define UART_WKSTS_RFRTWKF_Pos           (2)                                               /*!< UART_T::WKSTS: RFRTWKF Position        */
+#define UART_WKSTS_RFRTWKF_Msk           (0x1ul << UART_WKSTS_RFRTWKF_Pos)                 /*!< UART_T::WKSTS: RFRTWKF Mask            */
+
+#define UART_WKSTS_RS485WKF_Pos          (3)                                               /*!< UART_T::WKSTS: RS485WKF Position       */
+#define UART_WKSTS_RS485WKF_Msk          (0x1ul << UART_WKSTS_RS485WKF_Pos)                /*!< UART_T::WKSTS: RS485WKF Mask           */
+
+#define UART_WKSTS_TOUTWKF_Pos           (4)                                               /*!< UART_T::WKSTS: TOUTWKF Position        */
+#define UART_WKSTS_TOUTWKF_Msk           (0x1ul << UART_WKSTS_TOUTWKF_Pos)                 /*!< UART_T::WKSTS: TOUTWKF Mask            */
+
+#define UART_DWKCOMP_STCOMP_Pos          (0)                                               /*!< UART_T::DWKCOMP: STCOMP Position       */
+#define UART_DWKCOMP_STCOMP_Msk          (0xfffful << UART_DWKCOMP_STCOMP_Pos)             /*!< UART_T::DWKCOMP: STCOMP Mask           */
+
+/**@}*/ /* UART_CONST */
+/**@}*/ /* end of UART register group */
+/**@}*/ /* end of REGISTER group */
+
+#endif /* __UART_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/ui2c_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/ui2c_reg.h
new file mode 100644
index 0000000000..a2728bfc02
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/ui2c_reg.h
@@ -0,0 +1,568 @@
+/**************************************************************************//**
+ * @file     ui2c_reg.h
+ * @version  V1.00
+ * @brief    UI2C register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __UI2C_REG_H__
+#define __UI2C_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+/*---------------------- I2C Mode of USCI Controller -------------------------*/
+/**
+    @addtogroup UI2C I2C Mode of USCI Controller(UI2C)
+    Memory Mapped Structure for UI2C Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var UI2C_T::CTL
+     * Offset: 0x00  USCI Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |FUNMODE   |Function Mode
+     * |        |          |This bit field selects the protocol for this USCI controller
+     * |        |          |Selecting a protocol that is not available or a reserved combination disables the USCI
+     * |        |          |When switching between two protocols, the USCI has to be disabled before selecting a new protocol
+     * |        |          |Simultaneously, the USCI will be reset when user write 000 to FUNMODE.
+     * |        |          |000 = The USCI is disabled. All protocol related state machines are set to idle state.
+     * |        |          |001 = The SPI protocol is selected.
+     * |        |          |010 = The UART protocol is selected.
+     * |        |          |100 = The I2C protocol is selected.
+     * |        |          |Note: Other bit combinations are reserved.
+     * @var UI2C_T::BRGEN
+     * Offset: 0x08  USCI Baud Rate Generator Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RCLKSEL   |Reference Clock Source Selection
+     * |        |          |This bit selects the source signal of reference clock (fREF_CLK).
+     * |        |          |0 = Peripheral device clock fPCLK.
+     * |        |          |1 = Reserved.
+     * |[1]     |PTCLKSEL  |Protocol Clock Source Selection
+     * |        |          |This bit selects the source signal of protocol clock (fPROT_CLK).
+     * |        |          |0 = Reference clock fREF_CLK.
+     * |        |          |1 = fREF_CLK2 (its frequency is half of fREF_CLK).
+     * |[3:2]   |SPCLKSEL  |Sample Clock Source Selection
+     * |        |          |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
+     * |        |          |00 = fSAMP_CLK = fDIV_CLK.
+     * |        |          |01 = fSAMP_CLK = fPROT_CLK.
+     * |        |          |10 = fSAMP_CLK = fSCLK.
+     * |        |          |11 = fSAMP_CLK = fREF_CLK.
+     * |[4]     |TMCNTEN   |Time Measurement Counter Enable Bit
+     * |        |          |This bit enables the 10-bit timing measurement counter.
+     * |        |          |0 = Time measurement counter is Disabled.
+     * |        |          |1 = Time measurement counter is Enabled.
+     * |[5]     |TMCNTSRC  |Time Measurement Counter Clock Source Selection
+     * |        |          |0 = Time measurement counter with fPROT_CLK.
+     * |        |          |1 = Time measurement counter with fDIV_CLK.
+     * |[9:8]   |PDSCNT    |Pre-divider for Sample Counter
+     * |        |          |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK
+     * |        |          |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1).
+     * |[14:10] |DSCNT     |Denominator for Sample Counter
+     * |        |          |This bit field defines the divide ratio of the sample clock fSAMP_CLK.
+     * |        |          |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1).
+     * |        |          |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value
+     * |[25:16] |CLKDIV    |Clock Divider
+     * |        |          |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ).
+     * |        |          |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UI2C_PROTCTL[6])) is enabled
+     * |        |          |The revised value is the average bit time between bit 5 and bit 6
+     * |        |          |The user can use revised CLKDIV and new BRDETITV (UI2C_PROTCTL[24:16]) to calculate the precise baud rate.
+     * @var UI2C_T::LINECTL
+     * Offset: 0x2C  USCI Line Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |LSB       |LSB First Transmission Selection
+     * |        |          |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first.
+     * |        |          |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first.
+     * |[11:8]  |DWIDTH    |Word Length of Transmission
+     * |        |          |This bit field defines the data word length (amount of bits) for reception and transmission
+     * |        |          |The data word is always right-aligned in the data buffer
+     * |        |          |USCI support word length from 4 to 16 bits.
+     * |        |          |0x0: The data word contains 16 bits located at bit positions [15:0].
+     * |        |          |0x1: Reserved.
+     * |        |          |0x2: Reserved.
+     * |        |          |0x3: Reserved.
+     * |        |          |0x4: The data word contains 4 bits located at bit positions [3:0].
+     * |        |          |0x5: The data word contains 5 bits located at bit positions [4:0].
+     * |        |          |...
+     * |        |          |0xF: The data word contains 15 bits located at bit positions [14:0].
+     * |        |          |Note: In UART protocol, the length can be configured as 6~13 bits.
+     * @var UI2C_T::TXDAT
+     * Offset: 0x30  USCI Transmit Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |TXDAT     |Transmit Data
+     * |        |          |Software can use this bit field to write 16-bit transmit data for transmission.
+     * @var UI2C_T::RXDAT
+     * Offset: 0x34  USCI Receive Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |RXDAT     |Received Data
+     * |        |          |This bit field monitors the received data which stored in receive data buffer.
+     * |        |          |Note 1: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions which defined in I2C.
+     * |        |          |Note 2: In UART protocol, RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UI2C_PROTSTS[7:5]).
+     * @var UI2C_T::DEVADDR0
+     * Offset: 0x44  USCI Device Address Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[9:0]   |DEVADDR   |Device   Address
+     * |        |          |In I2C   protocol, this bit field contains the programmed slave address
+     * |        |          |If the first   received address byte are 1111 0AAXB, the AA bits are compared to   the bits DEVADDR[9:8] to check for address match, where the X is R/W bit
+     * |        |          |Then   the second address byte is also compared to DEVADDR[7:0].
+     * |        |          |Note: The DEVADDR [9:7] must be set 3'b000 when I2C operating in   7-bit address mode.
+     * @var UI2C_T::DEVADDR1
+     * Offset: 0x48  USCI Device Address Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[9:0]   |DEVADDR   |Device   Address
+     * |        |          |In I2C   protocol, this bit field contains the programmed slave address
+     * |        |          |If the first   received address byte are 1111 0AAXB, the AA bits are compared to   the bits DEVADDR[9:8] to check for address match, where the X is R/W bit
+     * |        |          |Then   the second address byte is also compared to DEVADDR[7:0].
+     * |        |          |Note: The DEVADDR [9:7] must be set 3'b000 when I2C operating in   7-bit address mode.
+     * @var UI2C_T::ADDRMSK0
+     * Offset: 0x4C  USCI Device Address Mask Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[9:0]   |ADDRMSK   |USCI Device Address Mask
+     * |        |          |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
+     * |        |          |1 = Mask Enabled (the received corresponding address bit is don't care.).
+     * |        |          |USCI support multiple address recognition with two address mask register
+     * |        |          |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
+     * |        |          |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
+     * |        |          |Note: The wake-up function can not set address mask.
+     * @var UI2C_T::ADDRMSK1
+     * Offset: 0x50  USCI Device Address Mask Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[9:0]   |ADDRMSK   |USCI Device Address Mask
+     * |        |          |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
+     * |        |          |1 = Mask Enabled (the received corresponding address bit is don't care.).
+     * |        |          |USCI support multiple address recognition with two address mask register
+     * |        |          |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care
+     * |        |          |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
+     * |        |          |Note: The wake-up function can not set address mask.
+     * @var UI2C_T::WKCTL
+     * Offset: 0x54  USCI Wake-up Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WKEN      |Wake-up Enable Bit
+     * |        |          |0 = Wake-up function Disabled.
+     * |        |          |1 = Wake-up function Enabled.
+     * |[1]     |WKADDREN  |Wake-up Address Match Enable Bit
+     * |        |          |0 = The chip is woken up according data toggle.
+     * |        |          |1 = The chip is woken up according address match.
+     * @var UI2C_T::WKSTS
+     * Offset: 0x58  USCI Wake-up Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WKF       |Wake-up Flag
+     * |        |          |When chip is woken up from Power-down mode, this bit is set to 1
+     * |        |          |Software can write 1 to clear this bit.
+     * @var UI2C_T::PROTCTL
+     * Offset: 0x5C  USCI Protocol Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |GCFUNC    |General Call Function
+     * |        |          |0 = General Call Function Disabled.
+     * |        |          |1 = General Call Function Enabled.
+     * |[1]     |AA        |Assert Acknowledge Control
+     * |        |          |When AA =1 prior to address or data received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter
+     * |        |          |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line.
+     * |[2]     |STO       |I2C STOP Control
+     * |        |          |In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically
+     * |        |          |In a slave mode, setting STO resets I2C hardware to the defined not addressed slave mode when bus error (UI2C_PROTSTS.ERRIF = 1).
+     * |[3]     |STA       |I2C START Control
+     * |        |          |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
+     * |[4]     |ADDR10EN  |Address 10-bit Function Enable Bit
+     * |        |          |0 = Address match 10 bit function is disabled.
+     * |        |          |1 = Address match 10 bit function is enabled.
+     * |[5]     |PTRG      |I2C Protocol Trigger (Write Only)
+     * |        |          |When a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested
+     * |        |          |It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled.
+     * |        |          |0 = I2C's stretch disabled and the I2C protocol function will go ahead.
+     * |        |          |1 = I2C's stretch active.
+     * |[8]     |SCLOUTEN  |SCL Output Enable Bit
+     * |        |          |This bit enables monitor pulling SCL to low
+     * |        |          |This monitor will pull SCL to low until it has had time to respond to an I2C interrupt.
+     * |        |          |0 = SCL output will be forced high due to open drain mechanism.
+     * |        |          |1 = I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt.
+     * |[9]     |MONEN     |Monitor Mode Enable Bit
+     * |        |          |This bit enables monitor mode
+     * |        |          |In monitor mode the SDA output will be put in high impedance mode
+     * |        |          |This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.
+     * |        |          |0 = The monitor mode is disabled.
+     * |        |          |1 = The monitor mode is enabled.
+     * |        |          |Note: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line.
+     * |[25:16] |TOCNT     |Time-out Clock Cycle
+     * |        |          |This bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear
+     * |        |          |The time-out is enable when TOCNT bigger than 0.
+     * |        |          |Note: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero on I2C mode.
+     * |[31]    |PROTEN    |I2C Protocol Enable Bit
+     * |        |          |0 = I2C Protocol disable.
+     * |        |          |1 = I2C Protocol enable.
+     * @var UI2C_T::PROTIEN
+     * Offset: 0x60  USCI Protocol Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |TOIEN     |Time-out Interrupt Enable Control
+     * |        |          |In I2C protocol, this bit enables the interrupt generation in case of a time-out event.
+     * |        |          |0 = The time-out interrupt is disabled.
+     * |        |          |1 = The time-out interrupt is enabled.
+     * |[1]     |STARIEN   |Start Condition Received Interrupt Enable Control
+     * |        |          |This bit enables the generation of a protocol interrupt if a start condition is detected.
+     * |        |          |0 = The start condition interrupt is disabled.
+     * |        |          |1 = The start condition interrupt is enabled.
+     * |[2]     |STORIEN   |Stop Condition Received Interrupt Enable Control
+     * |        |          |This bit enables the generation of a protocol interrupt if a stop condition is detected.
+     * |        |          |0 = The stop condition interrupt is disabled.
+     * |        |          |1 = The stop condition interrupt is enabled.
+     * |[3]     |NACKIEN   |Non - Acknowledge Interrupt Enable Control
+     * |        |          |This bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master.
+     * |        |          |0 = The non - acknowledge interrupt is disabled.
+     * |        |          |1 = The non - acknowledge interrupt is enabled.
+     * |[4]     |ARBLOIEN  |Arbitration Lost Interrupt Enable Control
+     * |        |          |This bit enables the generation of a protocol interrupt if an arbitration lost event is detected.
+     * |        |          |0 = The arbitration lost interrupt is disabled.
+     * |        |          |1 = The arbitration lost interrupt is enabled.
+     * |[5]     |ERRIEN    |Error Interrupt Enable Control
+     * |        |          |This bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16])).
+     * |        |          |0 = The error interrupt is disabled.
+     * |        |          |1 = The error interrupt is enabled.
+     * |[6]     |ACKIEN    |Acknowledge Interrupt Enable Control
+     * |        |          |This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master.
+     * |        |          |0 = The acknowledge interrupt is disabled.
+     * |        |          |1 = The acknowledge interrupt is enabled.
+     * @var UI2C_T::PROTSTS
+     * Offset: 0x64  USCI Protocol Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[5]     |TOIF      |Time-out Interrupt Flag
+     * |        |          |0 = A time-out interrupt status has not occurred.
+     * |        |          |1 = A time-out interrupt status has occurred.
+     * |        |          |Note: It is cleared by software writing one into this bit
+     * |[6]     |ONBUSY    |On Bus Busy
+     * |        |          |Indicates that a communication is in progress on the bus
+     * |        |          |It is set by hardware when a START condition is detected
+     * |        |          |It is cleared by hardware when a STOP condition is detected
+     * |        |          |0 = The bus is IDLE (both SCLK and SDA High).
+     * |        |          |1 = The bus is busy.
+     * |[8]     |STARIF    |Start Condition Received Interrupt Flag
+     * |        |          |This bit indicates that a start condition or repeated start condition has been detected on master mode
+     * |        |          |However, this bit also indicates that a repeated start condition has been detected on slave mode.
+     * |        |          |A protocol interrupt can be generated if UI2C_PROTCTL.STARIEN = 1.
+     * |        |          |0 = A start condition has not yet been detected.
+     * |        |          |1 = A start condition has been detected.
+     * |        |          |It is cleared by software writing one into this bit
+     * |[9]     |STORIF    |Stop Condition Received Interrupt Flag
+     * |        |          |This bit indicates that a stop condition has been detected on the I2C bus lines
+     * |        |          |A protocol interrupt can be generated if UI2C_PROTCTL.STORIEN = 1.
+     * |        |          |0 = A stop condition has not yet been detected.
+     * |        |          |1 = A stop condition has been detected.
+     * |        |          |It is cleared by software writing one into this bit
+     * |        |          |Note: This bit is set when slave RX mode.
+     * |[10]    |NACKIF    |Non - Acknowledge Received Interrupt Flag
+     * |        |          |This bit indicates that a non - acknowledge has been received in master mode
+     * |        |          |A protocol interrupt can be generated if UI2C_PROTCTL.NACKIEN = 1.
+     * |        |          |0 = A non - acknowledge has not been received.
+     * |        |          |1 = A non - acknowledge has been received.
+     * |        |          |It is cleared by software writing one into this bit
+     * |[11]    |ARBLOIF   |Arbitration Lost Interrupt Flag
+     * |        |          |This bit indicates that an arbitration has been lost
+     * |        |          |A protocol interrupt can be generated if UI2C_PROTCTL.ARBLOIEN = 1.
+     * |        |          |0 = An arbitration has not been lost.
+     * |        |          |1 = An arbitration has been lost.
+     * |        |          |It is cleared by software writing one into this bit
+     * |[12]    |ERRIF     |Error Interrupt Flag
+     * |        |          |This bit indicates that a Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame
+     * |        |          |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit
+     * |        |          |A protocol interrupt can be generated if UI2C_PROTCTL.ERRIEN = 1.
+     * |        |          |0 = An I2C error has not been detected.
+     * |        |          |1 = An I2C error has been detected.
+     * |        |          |It is cleared by software writing one into this bit
+     * |        |          |Note: This bit is set when slave mode, user must write one into STO register to the defined not addressed slave mode.
+     * |[13]    |ACKIF     |Acknowledge Received Interrupt Flag
+     * |        |          |This bit indicates that an acknowledge has been received in master mode
+     * |        |          |A protocol interrupt can be generated if UI2C_PROTCTL.ACKIEN = 1.
+     * |        |          |0 = An acknowledge has not been received.
+     * |        |          |1 = An acknowledge has been received.
+     * |        |          |It is cleared by software writing one into this bit
+     * |[14]    |SLASEL    |Slave Select Status
+     * |        |          |This bit indicates that this device has been selected as slave.
+     * |        |          |0 = The device is not selected as slave.
+     * |        |          |1 = The device is selected as slave.
+     * |        |          |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware.
+     * |[15]    |SLAREAD   |Slave Read Request Status
+     * |        |          |This bit indicates that a slave read request has been detected.
+     * |        |          |0 = A slave R/W bit is 1 has not been detected.
+     * |        |          |1 = A slave R/W bit is 1 has been detected.
+     * |        |          |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware.
+     * |[16]    |WKAKDONE  |Wakeup Address Frame Acknowledge Bit Done
+     * |        |          |0 = The ACK bit cycle of address match frame isn't done.
+     * |        |          |1 = The ACK bit cycle of address match frame is done in power-down.
+     * |        |          |Note: This bit can't release when WKUPIF is set.
+     * |[17]    |WRSTSWK   |Read/Write Status Bit in Address Wakeup Frame
+     * |        |          |0 = Write command be record on the address match wakeup frame.
+     * |        |          |1 = Read command be record on the address match wakeup frame.
+     * |[18]    |BUSHANG   |Bus Hang-up
+     * |        |          |This bit indicates bus hang-up status
+     * |        |          |There is 4-bit counter count when SCL hold high and refer fSAMP_CLK
+     * |        |          |The hang-up counter will count to overflow and set this bit when SDA is low
+     * |        |          |The counter will be reset by falling edge of SCL signal.
+     * |        |          |0 = The bus is normal status for transmission.
+     * |        |          |1 = The bus is hang-up status for transmission.
+     * |        |          |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
+     * |[19]    |ERRARBLO  |Error Arbitration Lost
+     * |        |          |This bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor
+     * |        |          |The I2C can send start condition when ERRARBLO is set
+     * |        |          |Thus this bit doesn't be cared on slave mode.
+     * |        |          |0 = The bus is normal status for transmission.
+     * |        |          |1 = The bus is error arbitration lost status for transmission.
+     * |        |          |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
+     * @var UI2C_T::ADMAT
+     * Offset: 0x88  I2C Slave Match Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |ADMAT0    |USCI Address 0 Match Status Register
+     * |        |          |When address 0 is matched, hardware will inform which address used
+     * |        |          |This bit will set to 1, and software can write 1 to clear this bit.
+     * |[1]     |ADMAT1    |USCI Address 1 Match Status Register
+     * |        |          |When address 1 is matched, hardware will inform which address used
+     * |        |          |This bit will set to 1, and software can write 1 to clear this bit.
+     * @var UI2C_T::TMCTL
+     * Offset: 0x8C  I2C Timing Configure Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[8:0]   |STCTL     |Setup Time Configure Control Register
+     * |        |          |This field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode..
+     * |        |          |The delay setup time is numbers of peripheral clock = STCTL x fPCLK.
+     * |[24:16] |HTCTL     |Hold Time Configure Control Register
+     * |        |          |This field is used to generate the delay timing between SCL falling edge SDA edge in
+     * |        |          |transmission mode.
+     * |        |          |The delay hold time is numbers of peripheral clock = HTCTL x fPCLK.
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] USCI Control Register                                            */
+    __I  uint32_t RESERVE0[1];
+    __IO uint32_t BRGEN;                 /*!< [0x0008] USCI Baud Rate Generator Register                                */
+    __I  uint32_t RESERVE1[8];
+    __IO uint32_t LINECTL;               /*!< [0x002c] USCI Line Control Register                                       */
+    __O  uint32_t TXDAT;                 /*!< [0x0030] USCI Transmit Data Register                                      */
+    __I  uint32_t RXDAT;                 /*!< [0x0034] USCI Receive Data Register                                       */
+    __I  uint32_t RESERVE2[3];
+    __IO uint32_t DEVADDR0;              /*!< [0x0044] USCI Device Address Register 0                                   */
+    __IO uint32_t DEVADDR1;              /*!< [0x0048] USCI Device Address Register 1                                   */
+    __IO uint32_t ADDRMSK0;              /*!< [0x004c] USCI Device Address Mask Register 0                              */
+    __IO uint32_t ADDRMSK1;              /*!< [0x0050] USCI Device Address Mask Register 1                              */
+    __IO uint32_t WKCTL;                 /*!< [0x0054] USCI Wake-up Control Register                                    */
+    __IO uint32_t WKSTS;                 /*!< [0x0058] USCI Wake-up Status Register                                     */
+    __IO uint32_t PROTCTL;               /*!< [0x005c] USCI Protocol Control Register                                   */
+    __IO uint32_t PROTIEN;               /*!< [0x0060] USCI Protocol Interrupt Enable Register                          */
+    __IO uint32_t PROTSTS;               /*!< [0x0064] USCI Protocol Status Register                                    */
+    __I  uint32_t RESERVE3[8];
+    __IO uint32_t ADMAT;                 /*!< [0x0088] I2C Slave Match Address Register                                 */
+    __IO uint32_t TMCTL;                 /*!< [0x008c] I2C Timing Configure Control Register                            */
+
+} UI2C_T;
+
+/**
+    @addtogroup UI2C_CONST UI2C Bit Field Definition
+    Constant Definitions for UI2C Controller
+  @{
+*/
+
+#define UI2C_CTL_FUNMODE_Pos             (0)                                               /*!< UI2C_T::CTL: FUNMODE Position          */
+#define UI2C_CTL_FUNMODE_Msk             (0x7ul << UI2C_CTL_FUNMODE_Pos)                   /*!< UI2C_T::CTL: FUNMODE Mask              */
+
+#define UI2C_BRGEN_RCLKSEL_Pos           (0)                                               /*!< UI2C_T::BRGEN: RCLKSEL Position        */
+#define UI2C_BRGEN_RCLKSEL_Msk           (0x1ul << UI2C_BRGEN_RCLKSEL_Pos)                 /*!< UI2C_T::BRGEN: RCLKSEL Mask            */
+
+#define UI2C_BRGEN_PTCLKSEL_Pos          (1)                                               /*!< UI2C_T::BRGEN: PTCLKSEL Position       */
+#define UI2C_BRGEN_PTCLKSEL_Msk          (0x1ul << UI2C_BRGEN_PTCLKSEL_Pos)                /*!< UI2C_T::BRGEN: PTCLKSEL Mask           */
+
+#define UI2C_BRGEN_SPCLKSEL_Pos          (2)                                               /*!< UI2C_T::BRGEN: SPCLKSEL Position       */
+#define UI2C_BRGEN_SPCLKSEL_Msk          (0x3ul << UI2C_BRGEN_SPCLKSEL_Pos)                /*!< UI2C_T::BRGEN: SPCLKSEL Mask           */
+
+#define UI2C_BRGEN_TMCNTEN_Pos           (4)                                               /*!< UI2C_T::BRGEN: TMCNTEN Position        */
+#define UI2C_BRGEN_TMCNTEN_Msk           (0x1ul << UI2C_BRGEN_TMCNTEN_Pos)                 /*!< UI2C_T::BRGEN: TMCNTEN Mask            */
+
+#define UI2C_BRGEN_TMCNTSRC_Pos          (5)                                               /*!< UI2C_T::BRGEN: TMCNTSRC Position       */
+#define UI2C_BRGEN_TMCNTSRC_Msk          (0x1ul << UI2C_BRGEN_TMCNTSRC_Pos)                /*!< UI2C_T::BRGEN: TMCNTSRC Mask           */
+
+#define UI2C_BRGEN_PDSCNT_Pos            (8)                                               /*!< UI2C_T::BRGEN: PDSCNT Position         */
+#define UI2C_BRGEN_PDSCNT_Msk            (0x3ul << UI2C_BRGEN_PDSCNT_Pos)                  /*!< UI2C_T::BRGEN: PDSCNT Mask             */
+
+#define UI2C_BRGEN_DSCNT_Pos             (10)                                              /*!< UI2C_T::BRGEN: DSCNT Position          */
+#define UI2C_BRGEN_DSCNT_Msk             (0x1ful << UI2C_BRGEN_DSCNT_Pos)                  /*!< UI2C_T::BRGEN: DSCNT Mask              */
+
+#define UI2C_BRGEN_CLKDIV_Pos            (16)                                              /*!< UI2C_T::BRGEN: CLKDIV Position         */
+#define UI2C_BRGEN_CLKDIV_Msk            (0x3fful << UI2C_BRGEN_CLKDIV_Pos)                /*!< UI2C_T::BRGEN: CLKDIV Mask             */
+
+#define UI2C_LINECTL_LSB_Pos             (0)                                               /*!< UI2C_T::LINECTL: LSB Position          */
+#define UI2C_LINECTL_LSB_Msk             (0x1ul << UI2C_LINECTL_LSB_Pos)                   /*!< UI2C_T::LINECTL: LSB Mask              */
+
+#define UI2C_LINECTL_DWIDTH_Pos          (8)                                               /*!< UI2C_T::LINECTL: DWIDTH Position       */
+#define UI2C_LINECTL_DWIDTH_Msk          (0xful << UI2C_LINECTL_DWIDTH_Pos)                /*!< UI2C_T::LINECTL: DWIDTH Mask           */
+
+#define UI2C_TXDAT_TXDAT_Pos             (0)                                               /*!< UI2C_T::TXDAT: TXDAT Position          */
+#define UI2C_TXDAT_TXDAT_Msk             (0xfffful << UI2C_TXDAT_TXDAT_Pos)                /*!< UI2C_T::TXDAT: TXDAT Mask              */
+
+#define UI2C_RXDAT_RXDAT_Pos             (0)                                               /*!< UI2C_T::RXDAT: RXDAT Position          */
+#define UI2C_RXDAT_RXDAT_Msk             (0xfffful << UI2C_RXDAT_RXDAT_Pos)                /*!< UI2C_T::RXDAT: RXDAT Mask              */
+
+#define UI2C_DEVADDR0_DEVADDR_Pos        (0)                                               /*!< UI2C_T::DEVADDR0: DEVADDR Position     */
+#define UI2C_DEVADDR0_DEVADDR_Msk        (0x3fful << UI2C_DEVADDR0_DEVADDR_Pos)            /*!< UI2C_T::DEVADDR0: DEVADDR Mask         */
+
+#define UI2C_DEVADDR1_DEVADDR_Pos        (0)                                               /*!< UI2C_T::DEVADDR1: DEVADDR Position     */
+#define UI2C_DEVADDR1_DEVADDR_Msk        (0x3fful << UI2C_DEVADDR1_DEVADDR_Pos)            /*!< UI2C_T::DEVADDR1: DEVADDR Mask         */
+
+#define UI2C_ADDRMSK0_ADDRMSK_Pos        (0)                                               /*!< UI2C_T::ADDRMSK0: ADDRMSK Position     */
+#define UI2C_ADDRMSK0_ADDRMSK_Msk        (0x3fful << UI2C_ADDRMSK0_ADDRMSK_Pos)            /*!< UI2C_T::ADDRMSK0: ADDRMSK Mask         */
+
+#define UI2C_ADDRMSK1_ADDRMSK_Pos        (0)                                               /*!< UI2C_T::ADDRMSK1: ADDRMSK Position     */
+#define UI2C_ADDRMSK1_ADDRMSK_Msk        (0x3fful << UI2C_ADDRMSK1_ADDRMSK_Pos)            /*!< UI2C_T::ADDRMSK1: ADDRMSK Mask         */
+
+#define UI2C_WKCTL_WKEN_Pos              (0)                                               /*!< UI2C_T::WKCTL: WKEN Position           */
+#define UI2C_WKCTL_WKEN_Msk              (0x1ul << UI2C_WKCTL_WKEN_Pos)                    /*!< UI2C_T::WKCTL: WKEN Mask               */
+
+#define UI2C_WKCTL_WKADDREN_Pos          (1)                                               /*!< UI2C_T::WKCTL: WKADDREN Position       */
+#define UI2C_WKCTL_WKADDREN_Msk          (0x1ul << UI2C_WKCTL_WKADDREN_Pos)                /*!< UI2C_T::WKCTL: WKADDREN Mask           */
+
+#define UI2C_WKSTS_WKF_Pos               (0)                                               /*!< UI2C_T::WKSTS: WKF Position            */
+#define UI2C_WKSTS_WKF_Msk               (0x1ul << UI2C_WKSTS_WKF_Pos)                     /*!< UI2C_T::WKSTS: WKF Mask                */
+
+#define UI2C_PROTCTL_GCFUNC_Pos          (0)                                               /*!< UI2C_T::PROTCTL: GCFUNC Position       */
+#define UI2C_PROTCTL_GCFUNC_Msk          (0x1ul << UI2C_PROTCTL_GCFUNC_Pos)                /*!< UI2C_T::PROTCTL: GCFUNC Mask           */
+
+#define UI2C_PROTCTL_AA_Pos              (1)                                               /*!< UI2C_T::PROTCTL: AA Position           */
+#define UI2C_PROTCTL_AA_Msk              (0x1ul << UI2C_PROTCTL_AA_Pos)                    /*!< UI2C_T::PROTCTL: AA Mask               */
+
+#define UI2C_PROTCTL_STO_Pos             (2)                                               /*!< UI2C_T::PROTCTL: STO Position          */
+#define UI2C_PROTCTL_STO_Msk             (0x1ul << UI2C_PROTCTL_STO_Pos)                   /*!< UI2C_T::PROTCTL: STO Mask              */
+
+#define UI2C_PROTCTL_STA_Pos             (3)                                               /*!< UI2C_T::PROTCTL: STA Position          */
+#define UI2C_PROTCTL_STA_Msk             (0x1ul << UI2C_PROTCTL_STA_Pos)                   /*!< UI2C_T::PROTCTL: STA Mask              */
+
+#define UI2C_PROTCTL_ADDR10EN_Pos        (4)                                               /*!< UI2C_T::PROTCTL: ADDR10EN Position     */
+#define UI2C_PROTCTL_ADDR10EN_Msk        (0x1ul << UI2C_PROTCTL_ADDR10EN_Pos)              /*!< UI2C_T::PROTCTL: ADDR10EN Mask         */
+
+#define UI2C_PROTCTL_PTRG_Pos            (5)                                               /*!< UI2C_T::PROTCTL: PTRG Position         */
+#define UI2C_PROTCTL_PTRG_Msk            (0x1ul << UI2C_PROTCTL_PTRG_Pos)                  /*!< UI2C_T::PROTCTL: PTRG Mask             */
+
+#define UI2C_PROTCTL_SCLOUTEN_Pos        (8)                                               /*!< UI2C_T::PROTCTL: SCLOUTEN Position     */
+#define UI2C_PROTCTL_SCLOUTEN_Msk        (0x1ul << UI2C_PROTCTL_SCLOUTEN_Pos)              /*!< UI2C_T::PROTCTL: SCLOUTEN Mask         */
+
+#define UI2C_PROTCTL_MONEN_Pos           (9)                                               /*!< UI2C_T::PROTCTL: MONEN Position        */
+#define UI2C_PROTCTL_MONEN_Msk           (0x1ul << UI2C_PROTCTL_MONEN_Pos)                 /*!< UI2C_T::PROTCTL: MONEN Mask            */
+
+#define UI2C_PROTCTL_TOCNT_Pos           (16)                                              /*!< UI2C_T::PROTCTL: TOCNT Position        */
+#define UI2C_PROTCTL_TOCNT_Msk           (0x3fful << UI2C_PROTCTL_TOCNT_Pos)               /*!< UI2C_T::PROTCTL: TOCNT Mask            */
+
+#define UI2C_PROTCTL_PROTEN_Pos          (31)                                              /*!< UI2C_T::PROTCTL: PROTEN Position       */
+#define UI2C_PROTCTL_PROTEN_Msk          (0x1ul << UI2C_PROTCTL_PROTEN_Pos)                /*!< UI2C_T::PROTCTL: PROTEN Mask           */
+
+#define UI2C_PROTIEN_TOIEN_Pos           (0)                                               /*!< UI2C_T::PROTIEN: TOIEN Position        */
+#define UI2C_PROTIEN_TOIEN_Msk           (0x1ul << UI2C_PROTIEN_TOIEN_Pos)                 /*!< UI2C_T::PROTIEN: TOIEN Mask            */
+
+#define UI2C_PROTIEN_STARIEN_Pos         (1)                                               /*!< UI2C_T::PROTIEN: STARIEN Position      */
+#define UI2C_PROTIEN_STARIEN_Msk         (0x1ul << UI2C_PROTIEN_STARIEN_Pos)               /*!< UI2C_T::PROTIEN: STARIEN Mask          */
+
+#define UI2C_PROTIEN_STORIEN_Pos         (2)                                               /*!< UI2C_T::PROTIEN: STORIEN Position      */
+#define UI2C_PROTIEN_STORIEN_Msk         (0x1ul << UI2C_PROTIEN_STORIEN_Pos)               /*!< UI2C_T::PROTIEN: STORIEN Mask          */
+
+#define UI2C_PROTIEN_NACKIEN_Pos         (3)                                               /*!< UI2C_T::PROTIEN: NACKIEN Position      */
+#define UI2C_PROTIEN_NACKIEN_Msk         (0x1ul << UI2C_PROTIEN_NACKIEN_Pos)               /*!< UI2C_T::PROTIEN: NACKIEN Mask          */
+
+#define UI2C_PROTIEN_ARBLOIEN_Pos        (4)                                               /*!< UI2C_T::PROTIEN: ARBLOIEN Position     */
+#define UI2C_PROTIEN_ARBLOIEN_Msk        (0x1ul << UI2C_PROTIEN_ARBLOIEN_Pos)              /*!< UI2C_T::PROTIEN: ARBLOIEN Mask         */
+
+#define UI2C_PROTIEN_ERRIEN_Pos          (5)                                               /*!< UI2C_T::PROTIEN: ERRIEN Position       */
+#define UI2C_PROTIEN_ERRIEN_Msk          (0x1ul << UI2C_PROTIEN_ERRIEN_Pos)                /*!< UI2C_T::PROTIEN: ERRIEN Mask           */
+
+#define UI2C_PROTIEN_ACKIEN_Pos          (6)                                               /*!< UI2C_T::PROTIEN: ACKIEN Position       */
+#define UI2C_PROTIEN_ACKIEN_Msk          (0x1ul << UI2C_PROTIEN_ACKIEN_Pos)                /*!< UI2C_T::PROTIEN: ACKIEN Mask           */
+
+#define UI2C_PROTSTS_TOIF_Pos            (5)                                               /*!< UI2C_T::PROTSTS: TOIF Position         */
+#define UI2C_PROTSTS_TOIF_Msk            (0x1ul << UI2C_PROTSTS_TOIF_Pos)                  /*!< UI2C_T::PROTSTS: TOIF Mask             */
+
+#define UI2C_PROTSTS_ONBUSY_Pos          (6)                                               /*!< UI2C_T::PROTSTS: ONBUSY Position       */
+#define UI2C_PROTSTS_ONBUSY_Msk          (0x1ul << UI2C_PROTSTS_ONBUSY_Pos)                /*!< UI2C_T::PROTSTS: ONBUSY Mask           */
+
+#define UI2C_PROTSTS_STARIF_Pos          (8)                                               /*!< UI2C_T::PROTSTS: STARIF Position       */
+#define UI2C_PROTSTS_STARIF_Msk          (0x1ul << UI2C_PROTSTS_STARIF_Pos)                /*!< UI2C_T::PROTSTS: STARIF Mask           */
+
+#define UI2C_PROTSTS_STORIF_Pos          (9)                                               /*!< UI2C_T::PROTSTS: STORIF Position       */
+#define UI2C_PROTSTS_STORIF_Msk          (0x1ul << UI2C_PROTSTS_STORIF_Pos)                /*!< UI2C_T::PROTSTS: STORIF Mask           */
+
+#define UI2C_PROTSTS_NACKIF_Pos          (10)                                              /*!< UI2C_T::PROTSTS: NACKIF Position       */
+#define UI2C_PROTSTS_NACKIF_Msk          (0x1ul << UI2C_PROTSTS_NACKIF_Pos)                /*!< UI2C_T::PROTSTS: NACKIF Mask           */
+
+#define UI2C_PROTSTS_ARBLOIF_Pos         (11)                                              /*!< UI2C_T::PROTSTS: ARBLOIF Position      */
+#define UI2C_PROTSTS_ARBLOIF_Msk         (0x1ul << UI2C_PROTSTS_ARBLOIF_Pos)               /*!< UI2C_T::PROTSTS: ARBLOIF Mask          */
+
+#define UI2C_PROTSTS_ERRIF_Pos           (12)                                              /*!< UI2C_T::PROTSTS: ERRIF Position        */
+#define UI2C_PROTSTS_ERRIF_Msk           (0x1ul << UI2C_PROTSTS_ERRIF_Pos)                 /*!< UI2C_T::PROTSTS: ERRIF Mask            */
+
+#define UI2C_PROTSTS_ACKIF_Pos           (13)                                              /*!< UI2C_T::PROTSTS: ACKIF Position        */
+#define UI2C_PROTSTS_ACKIF_Msk           (0x1ul << UI2C_PROTSTS_ACKIF_Pos)                 /*!< UI2C_T::PROTSTS: ACKIF Mask            */
+
+#define UI2C_PROTSTS_SLASEL_Pos          (14)                                              /*!< UI2C_T::PROTSTS: SLASEL Position       */
+#define UI2C_PROTSTS_SLASEL_Msk          (0x1ul << UI2C_PROTSTS_SLASEL_Pos)                /*!< UI2C_T::PROTSTS: SLASEL Mask           */
+
+#define UI2C_PROTSTS_SLAREAD_Pos         (15)                                              /*!< UI2C_T::PROTSTS: SLAREAD Position      */
+#define UI2C_PROTSTS_SLAREAD_Msk         (0x1ul << UI2C_PROTSTS_SLAREAD_Pos)               /*!< UI2C_T::PROTSTS: SLAREAD Mask          */
+
+#define UI2C_PROTSTS_WKAKDONE_Pos        (16)                                              /*!< UI2C_T::PROTSTS: WKAKDONE Position     */
+#define UI2C_PROTSTS_WKAKDONE_Msk        (0x1ul << UI2C_PROTSTS_WKAKDONE_Pos)              /*!< UI2C_T::PROTSTS: WKAKDONE Mask         */
+
+#define UI2C_PROTSTS_WRSTSWK_Pos         (17)                                              /*!< UI2C_T::PROTSTS: WRSTSWK Position      */
+#define UI2C_PROTSTS_WRSTSWK_Msk         (0x1ul << UI2C_PROTSTS_WRSTSWK_Pos)               /*!< UI2C_T::PROTSTS: WRSTSWK Mask          */
+
+#define UI2C_PROTSTS_BUSHANG_Pos         (18)                                              /*!< UI2C_T::PROTSTS: BUSHANG Position      */
+#define UI2C_PROTSTS_BUSHANG_Msk         (0x1ul << UI2C_PROTSTS_BUSHANG_Pos)               /*!< UI2C_T::PROTSTS: BUSHANG Mask          */
+
+#define UI2C_PROTSTS_ERRARBLO_Pos        (19)                                              /*!< UI2C_T::PROTSTS: ERRARBLO Position     */
+#define UI2C_PROTSTS_ERRARBLO_Msk        (0x1ul << UI2C_PROTSTS_ERRARBLO_Pos)              /*!< UI2C_T::PROTSTS: ERRARBLO Mask         */
+
+#define UI2C_ADMAT_ADMAT0_Pos            (0)                                               /*!< UI2C_T::ADMAT: ADMAT0 Position         */
+#define UI2C_ADMAT_ADMAT0_Msk            (0x1ul << UI2C_ADMAT_ADMAT0_Pos)                  /*!< UI2C_T::ADMAT: ADMAT0 Mask             */
+
+#define UI2C_ADMAT_ADMAT1_Pos            (1)                                               /*!< UI2C_T::ADMAT: ADMAT1 Position         */
+#define UI2C_ADMAT_ADMAT1_Msk            (0x1ul << UI2C_ADMAT_ADMAT1_Pos)                  /*!< UI2C_T::ADMAT: ADMAT1 Mask             */
+
+#define UI2C_TMCTL_STCTL_Pos             (0)                                               /*!< UI2C_T::TMCTL: STCTL Position          */
+#define UI2C_TMCTL_STCTL_Msk             (0x1fful << UI2C_TMCTL_STCTL_Pos)                 /*!< UI2C_T::TMCTL: STCTL Mask              */
+
+#define UI2C_TMCTL_HTCTL_Pos             (16)                                              /*!< UI2C_T::TMCTL: HTCTL Position          */
+#define UI2C_TMCTL_HTCTL_Msk             (0x1fful << UI2C_TMCTL_HTCTL_Pos)                 /*!< UI2C_T::TMCTL: HTCTL Mask              */
+
+/**@}*/ /* UI2C_CONST */
+/**@}*/ /* end of UI2C register group */
+/**@}*/ /* end of REGISTER group */
+
+#endif /* __UI2C_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/usbd_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/usbd_reg.h
new file mode 100644
index 0000000000..e544931a2b
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/usbd_reg.h
@@ -0,0 +1,658 @@
+/**************************************************************************//**
+ * @file     usbd_reg.h
+ * @version  V1.00
+ * @brief    USBD register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __USBD_REG_H__
+#define __USBD_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+/*---------------------- USB Device Controller -------------------------*/
+/**
+    @addtogroup USBD USB Device Controller(USBD)
+    Memory Mapped Structure for USBD Controller
+  @{
+*/
+
+
+
+/**
+  * @brief USBD endpoints register
+  */
+typedef struct
+{
+    /**
+     * @var USBD_EP_T::BUFSEG
+     * Offset: 0x500/0x510/0x520/0x530/0x540/0x550/0x560/0x570/0x580/0x590/0x5A0/0x5B0  Endpoint Buffer Segmentation Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[8:3]   |BUFSEG    |Endpoint Buffer Segmentation
+     * |        |          |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is
+     * |        |          |USBD_SRAM address + {BUFSEG, 3'b000}
+     * |        |          |Where the USBD_SRAM address = USBD_BA+0x100h.
+     * |        |          |Refer to the section 6.32.5.7 for the endpoint SRAM structure and its description.
+     * @var USBD_EP_T::MXPLD
+     * Offset: 0x504/0x514/0x524/0x534/0x544/0x554/0x564/0x574/0x584/0x594/0x5A4/0x5B4  Endpoint Maximal Payload Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[8:0]   |MXPLD     |Maximal Payload
+     * |        |          |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)
+     * |        |          |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.
+     * |        |          |(1) When the register is written by CPU,
+     * |        |          |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.
+     * |        |          |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.
+     * |        |          |(2) When the register is read by CPU,
+     * |        |          |For IN token, the value of MXPLD is indicated by the data length be transmitted to host.
+     * |        |          |For OUT token, the value of MXPLD is indicated the actual data length receiving from host.
+     * |        |          |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
+     * @var USBD_EP_T::CFG
+     * Offset: 0x508/0x518/0x528/0x538/0x548/0x558/0x568/0x578/0x588/0x598/0x5A8/0x5B8  Endpoint Configuration Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |EPNUM     |Endpoint Number
+     * |        |          |These bits are used to define the endpoint number of the current endpoint.
+     * |[4]     |ISOCH     |Isochronous Endpoint
+     * |        |          |This bit is used to set the endpoint as Isochronous endpoint, no handshake.
+     * |        |          |0 = No Isochronous endpoint.
+     * |        |          |1 = Isochronous endpoint.
+     * |[6:5]   |STATE     |Endpoint State
+     * |        |          |00 = Endpoint Disabled.
+     * |        |          |01 = Out endpoint.
+     * |        |          |10 = IN endpoint.
+     * |        |          |11 = Undefined.
+     * |[7]     |DSQSYNC   |Data Sequence Synchronization
+     * |        |          |0 = DATA0 PID.
+     * |        |          |1 = DATA1 PID.
+     * |        |          |For IN token, DSQSYNC specify DATA0 or DATA1 PID in transfer data packet.
+     * |        |          |For OUT token, DSQSYNC specify DATA0 or DATA1 PID in received data packet.
+     * |        |          |DSQSYNC will be toggled automatically by hardware when IN or OUT token transfer successfully in single buffer mode, but won’t be toggled in double buffer mode.
+     * |        |          |Note 1: When double buffer is enabled, hardware will automatically write 0 to DSQSYNC with active double buffer and write 1 to DSQSYNC with inactive double buffer.
+     * |        |          |Note 2: It won’t be toggled by hardware when DBEN = 1. USB data toggle will be guaranteed by changing endpoint.
+     * |[9]     |CSTALL    |Clear STALL Response
+     * |        |          |0 = Disable the device to clear the STALL handshake in setup stage.
+     * |        |          |1 = Clear the device to response STALL handshake in setup stage.
+     * |[10]    |DBTGACTIVE|Double Buffer Toggle Active Bit
+     * |        |          |0 = Inactive in double buffer mode.
+     * |        |          |1 = Active in double buffer mode.
+     * |        |          |When DBEN = 1 and endpoint successful transfer, DBTGACTIVE of each double buffer will be toggled automatically by hardware.
+     * |[11]    |DBEN      |Double Buffer Enable
+     * |        |          |0 = Single buffer mode.
+     * |        |          |1 = Double buffer mode.
+     * @var USBD_EP_T::CFGP
+     * Offset: 0x50C/0x51C/0x52C/0x53C/0x54C/0x55C/0x56C/0x57C/0x58C/0x59C/0x5AC/0x5BC  Endpoint Set Stall and Clear In/Out Ready Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CLRRDY    |Clear Ready
+     * |        |          |When the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data
+     * |        |          |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is automatically cleared to 0.
+     * |        |          |For IN token, write '1' to clear the IN token had ready to transmit the data to USB.
+     * |        |          |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB.
+     * |        |          |This bit is written 1 only and is always 0 when it is read back.
+     * |[1]     |SSTALL    |Set STALL
+     * |        |          |0 = Disable the device to response STALL.
+     * |        |          |1 = Set the device to respond STALL automatically.
+     */
+    __IO uint32_t BUFSEG;                /*!< [0x0000] Endpoint Buffer Segmentation Register                            */
+    __IO uint32_t MXPLD;                 /*!< [0x0004] Endpoint Maximal Payload Register                                */
+    __IO uint32_t CFG;                   /*!< [0x0008] Endpoint Configuration Register                                  */
+    __IO uint32_t CFGP;                  /*!< [0x000c] Endpoint Set Stall and Clear In/Out Ready Control Register       */
+
+} USBD_EP_T;
+
+typedef struct
+{
+
+
+    /**
+     * @var USBD_T::INTEN
+     * Offset: 0x00  USB Device Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BUSIEN    |Bus Event Interrupt Enable Bit
+     * |        |          |0 = BUS event interrupt Disabled.
+     * |        |          |1 = BUS event interrupt Enabled.
+     * |[1]     |USBIEN    |USB Event Interrupt Enable Bit
+     * |        |          |0 = USB event interrupt Disabled.
+     * |        |          |1 = USB event interrupt Enabled.
+     * |[2]     |VBDETIEN  |VBUS Detection Interrupt Enable Bit
+     * |        |          |0 = VBUS detection Interrupt Disabled.
+     * |        |          |1 = VBUS detection Interrupt Enabled.
+     * |[3]     |NEVWKIEN  |USB No-event-wake-up Interrupt Enable Bit
+     * |        |          |0 = No-event-wake-up Interrupt Disabled.
+     * |        |          |1 = No-event-wake-up Interrupt Enabled.
+     * |[4]     |SOFIEN    |Start of Frame Interrupt Enable Bit
+     * |        |          |0 = SOF Interrupt Disabled.
+     * |        |          |1 = SOF Interrupt Enabled.
+     * |[8]     |WKEN      |Wake-up Function Enable Bit
+     * |        |          |0 = USB wake-up function Disabled.
+     * |        |          |1 = USB wake-up function Enabled.
+     * |[15]    |INNAKEN   |Active NAK Function and Its Status in IN Token
+     * |        |          |0 = When device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS0 and USBD_EPSTS1register, so that the USB interrupt event will not be asserted.
+     * |        |          |1 = IN NAK status will be updated to USBD_EPSTS0 and USBD_EPSTS1 register and the USB interrupt event will be asserted, when the device responds NAK after receiving IN token.
+     * @var USBD_T::INTSTS
+     * Offset: 0x04  USB Device Interrupt Event Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |BUSIF     |BUS Interrupt Status
+     * |        |          |The BUS event means that there is one of the suspense or the resume function in the bus.
+     * |        |          |0 = No BUS event occurred.
+     * |        |          |1 = Bus event occurred. Check USBD_ATTR[3:0] to know which kind of bus event was occurred, cleared by writing 1 to USBD_INTSTS[0].
+     * |[1]     |USBIF     |USB Event Interrupt Status
+     * |        |          |The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.
+     * |        |          |0 = No USB event occurred.
+     * |        |          |1 = USB event occurred. Check EPSTS0~11[3:0] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[1] or EPSTS0~11 and SETUP (USBD_INTSTS[31]).
+     * |[2]     |VBDETIF   |VBUS Detection Interrupt Status
+     * |        |          |0 = There is no attached/detached event in the USB.
+     * |        |          |1 = There is attached/detached event in the USB bus and it is cleared by writing 1 to USBD_INTSTS[2].
+     * |[3]     |NEVWKIF   |No-event-wake-up Interrupt Status
+     * |        |          |0 = NEVWK event did not occur.
+     * |        |          |1 = No-event-wake-up event occurred, cleared by writing 1 to USBD_INTSTS[3].
+     * |[4]     |SOFIF     |Start of Frame Interrupt Status
+     * |        |          |0 = SOF event did not occur.
+     * |        |          |1 = SOF event occurred, cleared by writing 1 to USBD_INTSTS[4].
+     * |[16]    |EPEVT0    |Endpoint 0's USB Event Status
+     * |        |          |0 = No event occurred in endpoint 0.
+     * |        |          |1 = USB event occurred on Endpoint 0. Check USBD_EPSTS0[3:0] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[16] or USBD_INTSTS[1].
+     * |[17]    |EPEVT1    |Endpoint 1's USB Event Status
+     * |        |          |0 = No event occurred in endpoint 1.
+     * |        |          |1 = USB event occurred on Endpoint 1. Check USBD_EPSTS0[7:4] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[17] or USBD_INTSTS[1].
+     * |[18]    |EPEVT2    |Endpoint 2's USB Event Status
+     * |        |          |0 = No event occurred in endpoint 2.
+     * |        |          |1 = USB event occurred on Endpoint 2. Check USBD_EPSTS0[11:8] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[18] or USBD_INTSTS[1].
+     * |[19]    |EPEVT3    |Endpoint 3's USB Event Status
+     * |        |          |0 = No event occurred in endpoint 3.
+     * |        |          |1 = USB event occurred on Endpoint 3. Check USBD_EPSTS0[15:12] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[19] or USBD_INTSTS[1].
+     * |[20]    |EPEVT4    |Endpoint 4's USB Event Status
+     * |        |          |0 = No event occurred in endpoint 4.
+     * |        |          |1 = USB event occurred on Endpoint 4. Check USBD_EPSTS0[19:16] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[20] or USBD_INTSTS[1].
+     * |[21]    |EPEVT5    |Endpoint 5's USB Event Status
+     * |        |          |0 = No event occurred in endpoint 5.
+     * |        |          |1 = USB event occurred on Endpoint 5. Check USBD_EPSTS0[23:20] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[21] or USBD_INTSTS[1].
+     * |[22]    |EPEVT6    |Endpoint 6's USB Event Status
+     * |        |          |0 = No event occurred in endpoint 6.
+     * |        |          |1 = USB event occurred on Endpoint 6. Check USBD_EPSTS0[27:24] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[22] or USBD_INTSTS[1].
+     * |[23]    |EPEVT7    |Endpoint 7's USB Event Status
+     * |        |          |0 = No event occurred in endpoint 7.
+     * |        |          |1 = USB event occurred on Endpoint 7. Check USBD_EPSTS0[31:28] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[23] or USBD_INTSTS[1].
+     * |[24]    |EPEVT8    |Endpoint 8's USB Event Status
+     * |        |          |0 = No event occurred in endpoint 8.
+     * |        |          |1 = USB event occurred on Endpoint 8. Check USBD_EPSTS1[3:0] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[24] or USBD_INTSTS[1].
+     * |[25]    |EPEVT9    |Endpoint 9's USB Event Status
+     * |        |          |0 = No event occurred in endpoint 9.
+     * |        |          |1 = USB event occurred on Endpoint 9. Check USBD_EPSTS1[7:4] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[25] or USBD_INTSTS[1].
+     * |[26]    |EPEVT10   |Endpoint 10's USB Event Status
+     * |        |          |0 = No event occurred in endpoint 10.
+     * |        |          |1 = USB event occurred on Endpoint 10. Check USBD_EPSTS1[11:8] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[26] or USBD_INTSTS[1].
+     * |[27]    |EPEVT11   |Endpoint 11's USB Event Status
+     * |        |          |0 = No event occurred in endpoint 11.
+     * |        |          |1 = USB event occurred on Endpoint 11. Check USBD_EPSTS1[15:12] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[27] or USBD_INTSTS[1].
+     * |[31]    |SETUP     |Setup Event Status
+     * |        |          |0 = No Setup event.
+     * |        |          |1 = Setup event occurred, cleared by writing 1 to USBD_INTSTS[31].
+     * @var USBD_T::FADDR
+     * Offset: 0x08  USB Device Function Address Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[6:0]   |FADDR     |USB Device Function Address
+     * @var USBD_T::EPSTS
+     * Offset: 0x0C  USB Device Endpoint Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7]     |OV        |Overrun
+     * |        |          |It indicates that the received data is over the maximum payload number or not.
+     * |        |          |0 = No overrun.
+     * |        |          |1 = Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 bytes.
+     * @var USBD_T::ATTR
+     * Offset: 0x10  USB Device Bus Status and Attribution Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |USBRST    |USB Reset Status (Read Only)
+     * |        |          |0 = Bus no reset.
+     * |        |          |1 = Bus reset when SE0 (single-ended 0) more than 2.5us.
+     * |[1]     |SUSPEND   |Suspend Status (Read Only)
+     * |        |          |0 = Bus no suspend.
+     * |        |          |1 = Bus idle more than 3ms, either cable is plugged-out or host is sleeping.
+     * |[2]     |RESUME    |Resume Status (Read Only)
+     * |        |          |0 = No bus resume.
+     * |        |          |1 = Resume from suspend.
+     * |[3]     |TOUT      |Time-out Status (Read Only)
+     * |        |          |0 = No time-out.
+     * |        |          |1 = No Bus response more than 18 bits time.
+     * |[4]     |PHYEN     |PHY Transceiver Function Enable Bit
+     * |        |          |0 = PHY transceiver function Disabled.
+     * |        |          |1 = PHY transceiver function Enabled.
+     * |[5]     |RWAKEUP   |Remote Wake-up
+     * |        |          |0 = Release the USB bus from K state.
+     * |        |          |1 = Force USB bus to K (USB_D+ low, USB_D-: high) state, used for remote wake-up.
+     * |[7]     |USBEN     |USB Controller Enable Bit
+     * |        |          |0 = USB Controller Disabled.
+     * |        |          |1 = USB Controller Enabled.
+     * |[8]     |DPPUEN    |Pull-up Resistor on USB_DP Enable Bit
+     * |        |          |0 = Pull-up resistor in USB_D+ bus Disabled.
+     * |        |          |1 = Pull-up resistor in USB_D+ bus Active.
+     * |[10]    |BYTEM     |CPU Access USB SRAM Size Mode Selection
+     * |        |          |0 = Word mode: The size of the transfer from CPU to USB SRAM can be Word only.
+     * |        |          |1 = Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only.
+     * |[11]    |LPMACK    |LPM Token Acknowledge Enable Bit
+     * |        |          |The NYET/ACK will be returned only on a successful LPM transaction if no errors in both the EXT token and the LPM token and a valid bLinkState = 0001 (L1) is received, else ERROR and STALL will be returned automatically, respectively.
+     * |        |          |0= The valid LPM Token will be NYET.
+     * |        |          |1= The valid LPM Token will be ACK.
+     * |[12]    |L1SUSPEND |LPM L1 Suspend (Read Only)
+     * |        |          |0 = Bus no L1 state suspend.
+     * |        |          |1 = This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged.
+     * |[13]    |L1RESUME  |LPM L1 Resume (Read Only)
+     * |        |          |0 = Bus no LPM L1 state resume.
+     * |        |          |1 = LPM L1 state resume from LPM L1 state suspend.
+     * @var USBD_T::VBUSDET
+     * Offset: 0x14  USB Device VBUS Detection Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |VBUSDET   |Device VBUS Detection
+     * |        |          |0 = Controller is not attached to the USB host.
+     * |        |          |1 = Controller is attached to the USB host.
+     * @var USBD_T::STBUFSEG
+     * Offset: 0x18  SETUP Token Buffer Segmentation Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[8:3]   |STBUFSEG  |SETUP Token Buffer Segmentation
+     * |        |          |It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is
+     * |        |          |USBD_SRAM address + {STBUFSEG, 3'b000}
+     * |        |          |Where the USBD_SRAM address = USBD_BA+0x100h.
+     * |        |          |Note: It is used for SETUP token only.
+     * @var USBD_T::EPSTS0
+     * Offset: 0x20  USB Device Endpoint Status Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |EPSTS0    |Endpoint 0 Status
+     * |        |          |These bits are used to indicate the current status of this endpoint.
+     * |        |          |0000 = In ACK.
+     * |        |          |0001 = In NAK.
+     * |        |          |0010 = Out Packet Data0 ACK.
+     * |        |          |0110 = Out Packet Data1 ACK.
+     * |        |          |0111 = Isochronous transfer end.
+     * |[7:4]   |EPSTS1    |Endpoint 1 Status
+     * |        |          |These bits are used to indicate the current status of this endpoint.
+     * |        |          |0000 = In ACK.
+     * |        |          |0001 = In NAK.
+     * |        |          |0010 = Out Packet Data0 ACK.
+     * |        |          |0110 = Out Packet Data1 ACK.
+     * |        |          |0111 = Isochronous transfer end.
+     * |[11:8]  |EPSTS2    |Endpoint 2 Status
+     * |        |          |These bits are used to indicate the current status of this endpoint.
+     * |        |          |0000 = In ACK.
+     * |        |          |0001 = In NAK.
+     * |        |          |0010 = Out Packet Data0 ACK.
+     * |        |          |0110 = Out Packet Data1 ACK.
+     * |        |          |0111 = Isochronous transfer end.
+     * |[15:12] |EPSTS3    |Endpoint 3 Status
+     * |        |          |These bits are used to indicate the current status of this endpoint.
+     * |        |          |0000 = In ACK.
+     * |        |          |0001 = In NAK.
+     * |        |          |0010 = Out Packet Data0 ACK.
+     * |        |          |0110 = Out Packet Data1 ACK.
+     * |        |          |0111 = Isochronous transfer end.
+     * |[19:16] |EPSTS4    |Endpoint 4 Status
+     * |        |          |These bits are used to indicate the current status of this endpoint.
+     * |        |          |0000 = In ACK.
+     * |        |          |0001 = In NAK.
+     * |        |          |0010 = Out Packet Data0 ACK.
+     * |        |          |0110 = Out Packet Data1 ACK.
+     * |        |          |0111 = Isochronous transfer end.
+     * |[23:20] |EPSTS5    |Endpoint 5 Status
+     * |        |          |These bits are used to indicate the current status of this endpoint.
+     * |        |          |0000 = In ACK.
+     * |        |          |0001 = In NAK.
+     * |        |          |0010 = Out Packet Data0 ACK.
+     * |        |          |0110 = Out Packet Data1 ACK.
+     * |        |          |0111 = Isochronous transfer end.
+     * |[27:24] |EPSTS6    |Endpoint 6 Status
+     * |        |          |These bits are used to indicate the current status of this endpoint.
+     * |        |          |0000 = In ACK.
+     * |        |          |0001 = In NAK.
+     * |        |          |0010 = Out Packet Data0 ACK.
+     * |        |          |0110 = Out Packet Data1 ACK.
+     * |        |          |0111 = Isochronous transfer end.
+     * |[31:28] |EPSTS7    |Endpoint 7 Status
+     * |        |          |These bits are used to indicate the current status of this endpoint.
+     * |        |          |0000 = In ACK.
+     * |        |          |0001 = In NAK.
+     * |        |          |0010 = Out Packet Data0 ACK.
+     * |        |          |0110 = Out Packet Data1 ACK.
+     * |        |          |0111 = Isochronous transfer end.
+     * @var USBD_T::EPSTS1
+     * Offset: 0x24  USB Device Endpoint Status Register 1
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |EPSTS8    |Endpoint 8 Status
+     * |        |          |These bits are used to indicate the current status of this endpoint.
+     * |        |          |0000 = In ACK.
+     * |        |          |0001 = In NAK.
+     * |        |          |0010 = Out Packet Data0 ACK.
+     * |        |          |0110 = Out Packet Data1 ACK.
+     * |        |          |0111 = Isochronous transfer end.
+     * |[7:4]   |EPSTS9    |Endpoint 9 Status
+     * |        |          |These bits are used to indicate the current status of this endpoint.
+     * |        |          |0000 = In ACK.
+     * |        |          |0001 = In NAK.
+     * |        |          |0010 = Out Packet Data0 ACK.
+     * |        |          |0110 = Out Packet Data1 ACK.
+     * |        |          |0111 = Isochronous transfer end.
+     * |[11:8]  |EPSTS10   |Endpoint 10 Status
+     * |        |          |These bits are used to indicate the current status of this endpoint.
+     * |        |          |0000 = In ACK.
+     * |        |          |0001 = In NAK.
+     * |        |          |0010 = Out Packet Data0 ACK.
+     * |        |          |0110 = Out Packet Data1 ACK.
+     * |        |          |0111 = Isochronous transfer end.
+     * |[15:12] |EPSTS11   |Endpoint 11 Status
+     * |        |          |These bits are used to indicate the current status of this endpoint.
+     * |        |          |0000 = In ACK.
+     * |        |          |0001 = In NAK.
+     * |        |          |0010 = Out Packet Data0 ACK.
+     * |        |          |0110 = Out Packet Data1 ACK.
+     * |        |          |0111 = Isochronous transfer end.
+     * @var USBD_T::LPMATTR
+     * Offset: 0x88  USB LPM Attribution Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[3:0]   |LPMLINKSTS|LPM Link State
+     * |        |          |These bits contain the bLinkState received with last ACK LPM Token.
+     * |        |          |0000 = Reserve.
+     * |        |          |0001 = L1 (Sleep).
+     * |        |          |0010 - 1111 = Reserve.
+     * |[7:4]   |LPMBESL   |LPM Best Effort Service Latency
+     * |        |          |These bits contain the BESL value received with last ACK LPM Token.
+     * |        |          |0000 = 125us.
+     * |        |          |0001 = 150us.
+     * |        |          |0010 = 200us.
+     * |        |          |0011 = 300us.
+     * |        |          |0100 = 400us.
+     * |        |          |0101 = 500us.
+     * |        |          |0110 = 1000us.
+     * |        |          |0111 = 2000us.
+     * |        |          |1000 = 3000us.
+     * |        |          |1001 = 4000us.
+     * |        |          |1010 = 5000us.
+     * |        |          |1011 = 6000us.
+     * |        |          |1100 = 7000us.
+     * |        |          |1101 = 8000us.
+     * |        |          |1110 = 9000us.
+     * |        |          |1111 = 10000us.
+     * |[8]     |LPMRWAKUP |LPM Remote Wakeup
+     * |        |          |This bit contains the bRemoteWake value received with last ACK LPM Token.
+     * @var USBD_T::FN
+     * Offset: 0x8C  USB Frame Number Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[10:0]  |FN        |Frame Number
+     * |        |          |These bits contain the 11-bits frame number in the last received SOF packet.
+     * @var USBD_T::SE0
+     * Offset: 0x90  USB Device Drive SE0 Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SE0       |Drive Single Ended Zero in USB Bus
+     * |        |          |The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low.
+     * |        |          |0 = Normal operation.
+     * |        |          |1 = Force USB PHY transceiver to drive SE0.
+     */
+    __IO uint32_t INTEN;                 /*!< [0x0000] USB Device Interrupt Enable Register                             */
+    __IO uint32_t INTSTS;                /*!< [0x0004] USB Device Interrupt Event Status Register                       */
+    __IO uint32_t FADDR;                 /*!< [0x0008] USB Device Function Address Register                             */
+    __I  uint32_t EPSTS;                 /*!< [0x000c] USB Device Endpoint Status Register                              */
+    __IO uint32_t ATTR;                  /*!< [0x0010] USB Device Bus Status and Attribution Register                   */
+    __I  uint32_t VBUSDET;               /*!< [0x0014] USB Device VBUS Detection Register                               */
+    __IO uint32_t STBUFSEG;              /*!< [0x0018] SETUP Token Buffer Segmentation Register                         */
+    __I  uint32_t RESERVE0[1];
+    __I  uint32_t EPSTS0;                /*!< [0x0020] USB Device Endpoint Status Register 0                            */
+    __I  uint32_t EPSTS1;                /*!< [0x0024] USB Device Endpoint Status Register 1                            */
+    __I  uint32_t RESERVE1[24];
+    __I  uint32_t LPMATTR;               /*!< [0x0088] USB LPM Attribution Register                                     */
+    __I  uint32_t FN;                    /*!< [0x008c] USB Frame Number Register                                        */
+    __IO uint32_t SE0;                   /*!< [0x0090] USB Device Drive SE0 Control Register                            */
+    __I  uint32_t RESERVE2[283];
+    USBD_EP_T     EP[12];                /*!< [0x500~0x5bc] USB End Point 0 ~ 11 Configuration Register                 */
+
+} USBD_T;
+
+/**
+    @addtogroup USBD_CONST USBD Bit Field Definition
+    Constant Definitions for USBD Controller
+  @{
+*/
+
+#define USBD_INTEN_BUSIEN_Pos            (0)                                               /*!< USBD_T::INTEN: BUSIEN Position         */
+#define USBD_INTEN_BUSIEN_Msk            (0x1ul << USBD_INTEN_BUSIEN_Pos)                  /*!< USBD_T::INTEN: BUSIEN Mask             */
+
+#define USBD_INTEN_USBIEN_Pos            (1)                                               /*!< USBD_T::INTEN: USBIEN Position         */
+#define USBD_INTEN_USBIEN_Msk            (0x1ul << USBD_INTEN_USBIEN_Pos)                  /*!< USBD_T::INTEN: USBIEN Mask             */
+
+#define USBD_INTEN_VBDETIEN_Pos          (2)                                               /*!< USBD_T::INTEN: VBDETIEN Position       */
+#define USBD_INTEN_VBDETIEN_Msk          (0x1ul << USBD_INTEN_VBDETIEN_Pos)                /*!< USBD_T::INTEN: VBDETIEN Mask           */
+
+#define USBD_INTEN_NEVWKIEN_Pos          (3)                                               /*!< USBD_T::INTEN: NEVWKIEN Position       */
+#define USBD_INTEN_NEVWKIEN_Msk          (0x1ul << USBD_INTEN_NEVWKIEN_Pos)                /*!< USBD_T::INTEN: NEVWKIEN Mask           */
+
+#define USBD_INTEN_SOFIEN_Pos            (4)                                               /*!< USBD_T::INTEN: SOFIEN Position         */
+#define USBD_INTEN_SOFIEN_Msk            (0x1ul << USBD_INTEN_SOFIEN_Pos)                  /*!< USBD_T::INTEN: SOFIEN Mask             */
+
+#define USBD_INTEN_WKEN_Pos              (8)                                               /*!< USBD_T::INTEN: WKEN Position           */
+#define USBD_INTEN_WKEN_Msk              (0x1ul << USBD_INTEN_WKEN_Pos)                    /*!< USBD_T::INTEN: WKEN Mask               */
+
+#define USBD_INTEN_INNAKEN_Pos           (15)                                              /*!< USBD_T::INTEN: INNAKEN Position        */
+#define USBD_INTEN_INNAKEN_Msk           (0x1ul << USBD_INTEN_INNAKEN_Pos)                 /*!< USBD_T::INTEN: INNAKEN Mask            */
+
+#define USBD_INTSTS_BUSIF_Pos            (0)                                               /*!< USBD_T::INTSTS: BUSIF Position         */
+#define USBD_INTSTS_BUSIF_Msk            (0x1ul << USBD_INTSTS_BUSIF_Pos)                  /*!< USBD_T::INTSTS: BUSIF Mask             */
+
+#define USBD_INTSTS_USBIF_Pos            (1)                                               /*!< USBD_T::INTSTS: USBIF Position         */
+#define USBD_INTSTS_USBIF_Msk            (0x1ul << USBD_INTSTS_USBIF_Pos)                  /*!< USBD_T::INTSTS: USBIF Mask             */
+
+#define USBD_INTSTS_VBDETIF_Pos          (2)                                               /*!< USBD_T::INTSTS: VBDETIF Position       */
+#define USBD_INTSTS_VBDETIF_Msk          (0x1ul << USBD_INTSTS_VBDETIF_Pos)                /*!< USBD_T::INTSTS: VBDETIF Mask           */
+
+#define USBD_INTSTS_NEVWKIF_Pos          (3)                                               /*!< USBD_T::INTSTS: NEVWKIF Position       */
+#define USBD_INTSTS_NEVWKIF_Msk          (0x1ul << USBD_INTSTS_NEVWKIF_Pos)                /*!< USBD_T::INTSTS: NEVWKIF Mask           */
+
+#define USBD_INTSTS_SOFIF_Pos            (4)                                               /*!< USBD_T::INTSTS: SOFIF Position         */
+#define USBD_INTSTS_SOFIF_Msk            (0x1ul << USBD_INTSTS_SOFIF_Pos)                  /*!< USBD_T::INTSTS: SOFIF Mask             */
+
+#define USBD_INTSTS_EPEVT0_Pos           (16)                                              /*!< USBD_T::INTSTS: EPEVT0 Position        */
+#define USBD_INTSTS_EPEVT0_Msk           (0x1ul << USBD_INTSTS_EPEVT0_Pos)                 /*!< USBD_T::INTSTS: EPEVT0 Mask            */
+
+#define USBD_INTSTS_EPEVT1_Pos           (17)                                              /*!< USBD_T::INTSTS: EPEVT1 Position        */
+#define USBD_INTSTS_EPEVT1_Msk           (0x1ul << USBD_INTSTS_EPEVT1_Pos)                 /*!< USBD_T::INTSTS: EPEVT1 Mask            */
+
+#define USBD_INTSTS_EPEVT2_Pos           (18)                                              /*!< USBD_T::INTSTS: EPEVT2 Position        */
+#define USBD_INTSTS_EPEVT2_Msk           (0x1ul << USBD_INTSTS_EPEVT2_Pos)                 /*!< USBD_T::INTSTS: EPEVT2 Mask            */
+
+#define USBD_INTSTS_EPEVT3_Pos           (19)                                              /*!< USBD_T::INTSTS: EPEVT3 Position        */
+#define USBD_INTSTS_EPEVT3_Msk           (0x1ul << USBD_INTSTS_EPEVT3_Pos)                 /*!< USBD_T::INTSTS: EPEVT3 Mask            */
+
+#define USBD_INTSTS_EPEVT4_Pos           (20)                                              /*!< USBD_T::INTSTS: EPEVT4 Position        */
+#define USBD_INTSTS_EPEVT4_Msk           (0x1ul << USBD_INTSTS_EPEVT4_Pos)                 /*!< USBD_T::INTSTS: EPEVT4 Mask            */
+
+#define USBD_INTSTS_EPEVT5_Pos           (21)                                              /*!< USBD_T::INTSTS: EPEVT5 Position        */
+#define USBD_INTSTS_EPEVT5_Msk           (0x1ul << USBD_INTSTS_EPEVT5_Pos)                 /*!< USBD_T::INTSTS: EPEVT5 Mask            */
+
+#define USBD_INTSTS_EPEVT6_Pos           (22)                                              /*!< USBD_T::INTSTS: EPEVT6 Position        */
+#define USBD_INTSTS_EPEVT6_Msk           (0x1ul << USBD_INTSTS_EPEVT6_Pos)                 /*!< USBD_T::INTSTS: EPEVT6 Mask            */
+
+#define USBD_INTSTS_EPEVT7_Pos           (23)                                              /*!< USBD_T::INTSTS: EPEVT7 Position        */
+#define USBD_INTSTS_EPEVT7_Msk           (0x1ul << USBD_INTSTS_EPEVT7_Pos)                 /*!< USBD_T::INTSTS: EPEVT7 Mask            */
+
+#define USBD_INTSTS_EPEVT8_Pos           (24)                                              /*!< USBD_T::INTSTS: EPEVT8 Position        */
+#define USBD_INTSTS_EPEVT8_Msk           (0x1ul << USBD_INTSTS_EPEVT8_Pos)                 /*!< USBD_T::INTSTS: EPEVT8 Mask            */
+
+#define USBD_INTSTS_EPEVT9_Pos           (25)                                              /*!< USBD_T::INTSTS: EPEVT9 Position        */
+#define USBD_INTSTS_EPEVT9_Msk           (0x1ul << USBD_INTSTS_EPEVT9_Pos)                 /*!< USBD_T::INTSTS: EPEVT9 Mask            */
+
+#define USBD_INTSTS_EPEVT10_Pos          (26)                                              /*!< USBD_T::INTSTS: EPEVT10 Position       */
+#define USBD_INTSTS_EPEVT10_Msk          (0x1ul << USBD_INTSTS_EPEVT10_Pos)                /*!< USBD_T::INTSTS: EPEVT10 Mask           */
+
+#define USBD_INTSTS_EPEVT11_Pos          (27)                                              /*!< USBD_T::INTSTS: EPEVT11 Position       */
+#define USBD_INTSTS_EPEVT11_Msk          (0x1ul << USBD_INTSTS_EPEVT11_Pos)                /*!< USBD_T::INTSTS: EPEVT11 Mask           */
+
+#define USBD_INTSTS_SETUP_Pos            (31)                                              /*!< USBD_T::INTSTS: SETUP Position         */
+#define USBD_INTSTS_SETUP_Msk            (0x1ul << USBD_INTSTS_SETUP_Pos)                  /*!< USBD_T::INTSTS: SETUP Mask             */
+
+#define USBD_FADDR_FADDR_Pos             (0)                                               /*!< USBD_T::FADDR: FADDR Position          */
+#define USBD_FADDR_FADDR_Msk             (0x7ful << USBD_FADDR_FADDR_Pos)                  /*!< USBD_T::FADDR: FADDR Mask              */
+
+#define USBD_EPSTS_OV_Pos                (7)                                               /*!< USBD_T::EPSTS: OV Position             */
+#define USBD_EPSTS_OV_Msk                (0x1ul << USBD_EPSTS_OV_Pos)                      /*!< USBD_T::EPSTS: OV Mask                 */
+
+#define USBD_ATTR_USBRST_Pos             (0)                                               /*!< USBD_T::ATTR: USBRST Position          */
+#define USBD_ATTR_USBRST_Msk             (0x1ul << USBD_ATTR_USBRST_Pos)                   /*!< USBD_T::ATTR: USBRST Mask              */
+
+#define USBD_ATTR_SUSPEND_Pos            (1)                                               /*!< USBD_T::ATTR: SUSPEND Position         */
+#define USBD_ATTR_SUSPEND_Msk            (0x1ul << USBD_ATTR_SUSPEND_Pos)                  /*!< USBD_T::ATTR: SUSPEND Mask             */
+
+#define USBD_ATTR_RESUME_Pos             (2)                                               /*!< USBD_T::ATTR: RESUME Position          */
+#define USBD_ATTR_RESUME_Msk             (0x1ul << USBD_ATTR_RESUME_Pos)                   /*!< USBD_T::ATTR: RESUME Mask              */
+
+#define USBD_ATTR_TOUT_Pos               (3)                                               /*!< USBD_T::ATTR: TOUT Position            */
+#define USBD_ATTR_TOUT_Msk               (0x1ul << USBD_ATTR_TOUT_Pos)                     /*!< USBD_T::ATTR: TOUT Mask                */
+
+#define USBD_ATTR_PHYEN_Pos              (4)                                               /*!< USBD_T::ATTR: PHYEN Position           */
+#define USBD_ATTR_PHYEN_Msk              (0x1ul << USBD_ATTR_PHYEN_Pos)                    /*!< USBD_T::ATTR: PHYEN Mask               */
+
+#define USBD_ATTR_RWAKEUP_Pos            (5)                                               /*!< USBD_T::ATTR: RWAKEUP Position         */
+#define USBD_ATTR_RWAKEUP_Msk            (0x1ul << USBD_ATTR_RWAKEUP_Pos)                  /*!< USBD_T::ATTR: RWAKEUP Mask             */
+
+#define USBD_ATTR_USBEN_Pos              (7)                                               /*!< USBD_T::ATTR: USBEN Position           */
+#define USBD_ATTR_USBEN_Msk              (0x1ul << USBD_ATTR_USBEN_Pos)                    /*!< USBD_T::ATTR: USBEN Mask               */
+
+#define USBD_ATTR_DPPUEN_Pos             (8)                                               /*!< USBD_T::ATTR: DPPUEN Position          */
+#define USBD_ATTR_DPPUEN_Msk             (0x1ul << USBD_ATTR_DPPUEN_Pos)                   /*!< USBD_T::ATTR: DPPUEN Mask              */
+
+#define USBD_ATTR_BYTEM_Pos              (10)                                              /*!< USBD_T::ATTR: BYTEM Position           */
+#define USBD_ATTR_BYTEM_Msk              (0x1ul << USBD_ATTR_BYTEM_Pos)                    /*!< USBD_T::ATTR: BYTEM Mask               */
+
+#define USBD_ATTR_LPMACK_Pos             (11)                                              /*!< USBD_T::ATTR: LPMACK Position          */
+#define USBD_ATTR_LPMACK_Msk             (0x1ul << USBD_ATTR_LPMACK_Pos)                   /*!< USBD_T::ATTR: LPMACK Mask              */
+
+#define USBD_ATTR_L1SUSPEND_Pos          (12)                                              /*!< USBD_T::ATTR: L1SUSPEND Position       */
+#define USBD_ATTR_L1SUSPEND_Msk          (0x1ul << USBD_ATTR_L1SUSPEND_Pos)                /*!< USBD_T::ATTR: L1SUSPEND Mask           */
+
+#define USBD_ATTR_L1RESUME_Pos           (13)                                              /*!< USBD_T::ATTR: L1RESUME Position        */
+#define USBD_ATTR_L1RESUME_Msk           (0x1ul << USBD_ATTR_L1RESUME_Pos)                 /*!< USBD_T::ATTR: L1RESUME Mask            */
+
+#define USBD_VBUSDET_VBUSDET_Pos         (0)                                               /*!< USBD_T::VBUSDET: VBUSDET Position      */
+#define USBD_VBUSDET_VBUSDET_Msk         (0x1ul << USBD_VBUSDET_VBUSDET_Pos)               /*!< USBD_T::VBUSDET: VBUSDET Mask          */
+
+#define USBD_STBUFSEG_STBUFSEG_Pos       (3)                                               /*!< USBD_T::STBUFSEG: STBUFSEG Position    */
+#define USBD_STBUFSEG_STBUFSEG_Msk       (0x3ful << USBD_STBUFSEG_STBUFSEG_Pos)            /*!< USBD_T::STBUFSEG: STBUFSEG Mask        */
+
+#define USBD_EPSTS0_EPSTS0_Pos           (0)                                               /*!< USBD_T::EPSTS0: EPSTS0 Position        */
+#define USBD_EPSTS0_EPSTS0_Msk           (0xful << USBD_EPSTS0_EPSTS0_Pos)                 /*!< USBD_T::EPSTS0: EPSTS0 Mask            */
+
+#define USBD_EPSTS0_EPSTS1_Pos           (4)                                               /*!< USBD_T::EPSTS0: EPSTS1 Position        */
+#define USBD_EPSTS0_EPSTS1_Msk           (0xful << USBD_EPSTS0_EPSTS1_Pos)                 /*!< USBD_T::EPSTS0: EPSTS1 Mask            */
+
+#define USBD_EPSTS0_EPSTS2_Pos           (8)                                               /*!< USBD_T::EPSTS0: EPSTS2 Position        */
+#define USBD_EPSTS0_EPSTS2_Msk           (0xful << USBD_EPSTS0_EPSTS2_Pos)                 /*!< USBD_T::EPSTS0: EPSTS2 Mask            */
+
+#define USBD_EPSTS0_EPSTS3_Pos           (12)                                              /*!< USBD_T::EPSTS0: EPSTS3 Position        */
+#define USBD_EPSTS0_EPSTS3_Msk           (0xful << USBD_EPSTS0_EPSTS3_Pos)                 /*!< USBD_T::EPSTS0: EPSTS3 Mask            */
+
+#define USBD_EPSTS0_EPSTS4_Pos           (16)                                              /*!< USBD_T::EPSTS0: EPSTS4 Position        */
+#define USBD_EPSTS0_EPSTS4_Msk           (0xful << USBD_EPSTS0_EPSTS4_Pos)                 /*!< USBD_T::EPSTS0: EPSTS4 Mask            */
+
+#define USBD_EPSTS0_EPSTS5_Pos           (20)                                              /*!< USBD_T::EPSTS0: EPSTS5 Position        */
+#define USBD_EPSTS0_EPSTS5_Msk           (0xful << USBD_EPSTS0_EPSTS5_Pos)                 /*!< USBD_T::EPSTS0: EPSTS5 Mask            */
+
+#define USBD_EPSTS0_EPSTS6_Pos           (24)                                              /*!< USBD_T::EPSTS0: EPSTS6 Position        */
+#define USBD_EPSTS0_EPSTS6_Msk           (0xful << USBD_EPSTS0_EPSTS6_Pos)                 /*!< USBD_T::EPSTS0: EPSTS6 Mask            */
+
+#define USBD_EPSTS0_EPSTS7_Pos           (28)                                              /*!< USBD_T::EPSTS0: EPSTS7 Position        */
+#define USBD_EPSTS0_EPSTS7_Msk           (0xful << USBD_EPSTS0_EPSTS7_Pos)                 /*!< USBD_T::EPSTS0: EPSTS7 Mask            */
+
+#define USBD_EPSTS1_EPSTS8_Pos           (0)                                               /*!< USBD_T::EPSTS1: EPSTS8 Position        */
+#define USBD_EPSTS1_EPSTS8_Msk           (0xful << USBD_EPSTS1_EPSTS8_Pos)                 /*!< USBD_T::EPSTS1: EPSTS8 Mask            */
+
+#define USBD_EPSTS1_EPSTS9_Pos           (4)                                               /*!< USBD_T::EPSTS1: EPSTS9 Position        */
+#define USBD_EPSTS1_EPSTS9_Msk           (0xful << USBD_EPSTS1_EPSTS9_Pos)                 /*!< USBD_T::EPSTS1: EPSTS9 Mask            */
+
+#define USBD_EPSTS1_EPSTS10_Pos          (8)                                               /*!< USBD_T::EPSTS1: EPSTS10 Position       */
+#define USBD_EPSTS1_EPSTS10_Msk          (0xful << USBD_EPSTS1_EPSTS10_Pos)                /*!< USBD_T::EPSTS1: EPSTS10 Mask           */
+
+#define USBD_EPSTS1_EPSTS11_Pos          (12)                                              /*!< USBD_T::EPSTS1: EPSTS11 Position       */
+#define USBD_EPSTS1_EPSTS11_Msk          (0xful << USBD_EPSTS1_EPSTS11_Pos)                /*!< USBD_T::EPSTS1: EPSTS11 Mask           */
+
+#define USBD_LPMATTR_LPMLINKSTS_Pos      (0)                                               /*!< USBD_T::LPMATTR: LPMLINKSTS Position   */
+#define USBD_LPMATTR_LPMLINKSTS_Msk      (0xful << USBD_LPMATTR_LPMLINKSTS_Pos)            /*!< USBD_T::LPMATTR: LPMLINKSTS Mask       */
+
+#define USBD_LPMATTR_LPMBESL_Pos         (4)                                               /*!< USBD_T::LPMATTR: LPMBESL Position      */
+#define USBD_LPMATTR_LPMBESL_Msk         (0xful << USBD_LPMATTR_LPMBESL_Pos)               /*!< USBD_T::LPMATTR: LPMBESL Mask          */
+
+#define USBD_LPMATTR_LPMRWAKUP_Pos       (8)                                               /*!< USBD_T::LPMATTR: LPMRWAKUP Position    */
+#define USBD_LPMATTR_LPMRWAKUP_Msk       (0x1ul << USBD_LPMATTR_LPMRWAKUP_Pos)             /*!< USBD_T::LPMATTR: LPMRWAKUP Mask        */
+
+#define USBD_FN_FN_Pos                   (0)                                               /*!< USBD_T::FN: FN Position                */
+#define USBD_FN_FN_Msk                   (0x7fful << USBD_FN_FN_Pos)                       /*!< USBD_T::FN: FN Mask                    */
+
+#define USBD_SE0_SE0_Pos                 (0)                                               /*!< USBD_T::SE0: SE0 Position              */
+#define USBD_SE0_SE0_Msk                 (0x1ul << USBD_SE0_SE0_Pos)                       /*!< USBD_T::SE0: SE0 Mask                  */
+
+#define USBD_BUFSEG_BUFSEG_Pos           (3)                                               /*!< USBD_EP_T::BUFSEG: BUFSEG Position     */
+#define USBD_BUFSEG_BUFSEG_Msk           (0x3ful << USBD_BUFSEG_BUFSEG_Pos)                /*!< USBD_EP_T::BUFSEG: BUFSEG Mask         */
+
+#define USBD_MXPLD_MXPLD_Pos             (0)                                               /*!< USBD_EP_T::MXPLD: MXPLD Position       */
+#define USBD_MXPLD_MXPLD_Msk             (0x1fful << USBD_MXPLD_MXPLD_Pos)                 /*!< USBD_EP_T::MXPLD: MXPLD Mask           */
+
+#define USBD_CFG_EPNUM_Pos               (0)                                               /*!< USBD_EP_T::CFG: EPNUM Position         */
+#define USBD_CFG_EPNUM_Msk               (0xful << USBD_CFG_EPNUM_Pos)                     /*!< USBD_EP_T::CFG: EPNUM Mask             */
+
+#define USBD_CFG_ISOCH_Pos               (4)                                               /*!< USBD_EP_T::CFG: ISOCH Position         */
+#define USBD_CFG_ISOCH_Msk               (0x1ul << USBD_CFG_ISOCH_Pos)                     /*!< USBD_EP_T::CFG: ISOCH Mask             */
+
+#define USBD_CFG_STATE_Pos               (5)                                               /*!< USBD_EP_T::CFG: STATE Position         */
+#define USBD_CFG_STATE_Msk               (0x3ul << USBD_CFG_STATE_Pos)                     /*!< USBD_EP_T::CFG: STATE Mask             */
+
+#define USBD_CFG_DSQSYNC_Pos             (7)                                               /*!< USBD_EP_T::CFG: DSQSYNC Position       */
+#define USBD_CFG_DSQSYNC_Msk             (0x1ul << USBD_CFG_DSQSYNC_Pos)                   /*!< USBD_EP_T::CFG: DSQSYNC Mask           */
+
+#define USBD_CFG_CSTALL_Pos              (9)                                               /*!< USBD_EP_T::CFG: CSTALL Position        */
+#define USBD_CFG_CSTALL_Msk              (0x1ul << USBD_CFG_CSTALL_Pos)                    /*!< USBD_EP_T::CFG: CSTALL Mask            */
+
+#define USBD_CFG_DBTGACTIVE_Pos          (10)                                              /*!< USBD_EP_T::CFG: DBTGACTIVE Position    */
+#define USBD_CFG_DBTGACTIVE_Msk          (0x1ul << USBD_CFG_DBTGACTIVE_Pos)                /*!< USBD_EP_T::CFG: DBTGACTIVE Mask        */
+
+#define USBD_CFG_DBEN_Pos                (11)                                              /*!< USBD_EP_T::CFG: DBEN Position          */
+#define USBD_CFG_DBEN_Msk                (0x1ul << USBD_CFG_DBEN_Pos)                      /*!< USBD_EP_T::CFG: DBEN Mask              */
+
+#define USBD_CFGP_CLRRDY_Pos             (0)                                               /*!< USBD_EP_T::CFGP: CLRRDY Position       */
+#define USBD_CFGP_CLRRDY_Msk             (0x1ul << USBD_CFGP_CLRRDY_Pos)                   /*!< USBD_EP_T::CFGP: CLRRDY Mask           */
+
+#define USBD_CFGP_SSTALL_Pos             (1)                                               /*!< USBD_EP_T::CFGP: SSTALL Position       */
+#define USBD_CFGP_SSTALL_Msk             (0x1ul << USBD_CFGP_SSTALL_Pos)                   /*!< USBD_EP_T::CFGP: SSTALL Mask           */
+
+/**@}*/ /* USBD_CONST */
+/**@}*/ /* end of USBD register group */
+/**@}*/ /* end of REGISTER group */
+
+#endif /* __USBD_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/usbh_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/usbh_reg.h
new file mode 100644
index 0000000000..38df8f48b5
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/usbh_reg.h
@@ -0,0 +1,799 @@
+/**************************************************************************//**
+ * @file     usbh_reg.h
+ * @version  V1.00
+ * @brief    USBH register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __USBH_REG_H__
+#define __USBH_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+/*---------------------- USB Host Controller -------------------------*/
+/**
+    @addtogroup USBH USB Host Controller(USBH)
+    Memory Mapped Structure for USBH Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var USBH_T::HcRevision
+     * Offset: 0x00  Host Controller Revision Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |REV       |Revision Number
+     * |        |          |Indicates the Open HCI Specification revision number implemented by the Hardware
+     * |        |          |Host Controller supports 1.1 specification.
+     * |        |          |(X.Y = XYh).
+     * @var USBH_T::HcControl
+     * Offset: 0x04  Host Controller Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |CBSR      |Control Bulk Service Ratio
+     * |        |          |This specifies the service ratio between Control and Bulk EDs
+     * |        |          |Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs
+     * |        |          |The internal count will be retained when crossing the frame boundary
+     * |        |          |In case of reset, HCD is responsible for restoring this value.
+     * |        |          |00 = Number of Control EDs over Bulk EDs served is 1:1.
+     * |        |          |01 = Number of Control EDs over Bulk EDs served is 2:1.
+     * |        |          |10 = Number of Control EDs over Bulk EDs served is 3:1.
+     * |        |          |11 = Number of Control EDs over Bulk EDs served is 4:1.
+     * |[2]     |PLE       |Periodic List Enable Bit
+     * |        |          |When set, this bit enables processing of the Periodic (interrupt and isochronous) list
+     * |        |          |The Host Controller checks this bit prior to attempting any periodic transfers in a frame.
+     * |        |          |0 = Processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame) Disabled.
+     * |        |          |1 = Processing of the Periodic (Interrupt and Isochronous) list in the next frame Enabled.
+     * |        |          |Note: To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high.
+     * |[3]     |IE        |Isochronous List Enable Bit
+     * |        |          |Both IE and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list
+     * |        |          |Either IE or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list.
+     * |        |          |0 = Processing of the Isochronous list after next SOF (Start-Of-Frame) Disabled.
+     * |        |          |1 = Processing of the Isochronous list in the next frame Enabled, if the PLE (HcControl[2]) is high, too.
+     * |[4]     |CLE       |Control List Enable Bit
+     * |        |          |0 = Processing of the Control list after next SOF (Start-Of-Frame) Disabled.
+     * |        |          |1 = Processing of the Control list in the next frame Enabled.
+     * |[5]     |BLE       |Bulk List Enable Bit
+     * |        |          |0 = Processing of the Bulk list after next SOF (Start-Of-Frame) Disabled.
+     * |        |          |1 = Processing of the Bulk list in the next frame Enabled.
+     * |[7:6]   |HCFS      |Host Controller Functional State
+     * |        |          |This field sets the Host Controller state
+     * |        |          |The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port
+     * |        |          |States are:
+     * |        |          |00 = USBRESET.
+     * |        |          |01 = USBRESUME.
+     * |        |          |10 = USBOPERATIONAL.
+     * |        |          |11 = USBSUSPEND.
+     * @var USBH_T::HcCommandStatus
+     * Offset: 0x08  Host Controller Command Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |HCR       |Host Controller Reset
+     * |        |          |This bit is set to initiate the software reset of Host Controller
+     * |        |          |This bit is cleared by the Host Controller, upon completed of the reset operation.
+     * |        |          |This bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports.
+     * |        |          |0 = Host Controller is not in software reset state.
+     * |        |          |1 = Host Controller is in software reset state.
+     * |[1]     |CLF       |Control List Filled
+     * |        |          |Set high to indicate there is an active TD on the Control List
+     * |        |          |It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List.
+     * |        |          |0 = No active TD found or Host Controller begins to process the head of the Control list.
+     * |        |          |1 = An active TD added or found on the Control list.
+     * |[2]     |BLF       |Bulk List Filled
+     * |        |          |Set high to indicate there is an active TD on the Bulk list
+     * |        |          |This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list.
+     * |        |          |0 = No active TD found or Host Controller begins to process the head of the Bulk list.
+     * |        |          |1 = An active TD added or found on the Bulk list.
+     * |[17:16] |SOC       |Schedule Overrun Count (Read-Only)
+     * |        |          |These bits are incremented on each scheduling overrun error
+     * |        |          |It is initialized to 00b and wraps around at 11b
+     * |        |          |This will be incremented when a scheduling overrun is detected even if SO (HcInterruptStatus[0]) has already been set.
+     * @var USBH_T::HcInterruptStatus
+     * Offset: 0x0C  Host Controller Interrupt Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SO        |Scheduling Overrun
+     * |        |          |Set when the List Processor determines a Schedule Overrun has occurred.
+     * |        |          |0 = Schedule Overrun didn't occur.
+     * |        |          |1 = Schedule Overrun has occurred.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[1]     |WDH       |Write Back Done Head
+     * |        |          |Set after the Host Controller has written HcDoneHead to HccaDoneHead
+     * |        |          |Further updates of the HccaDoneHead will not occur until this bit has been cleared.
+     * |        |          |0 = Host Controller didn't update HccaDoneHead.
+     * |        |          |1 = Host Controller has written HcDoneHead to HccaDoneHead.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[2]     |SF        |Start of Frame
+     * |        |          |Set when the Frame Management functional block signals a u2018Start of Frame' event
+     * |        |          |Host Control generates a SOF token at the same time.
+     * |        |          |0 = Not the start of a frame.
+     * |        |          |1 = Indicate the start of a frame and Host Controller generates a SOF token.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[3]     |RD        |Resume Detected
+     * |        |          |Set when Host Controller detects resume signaling on a downstream port.
+     * |        |          |0 = No resume signaling detected on a downstream port.
+     * |        |          |1 = Resume signaling detected on a downstream port.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[5]     |FNO       |Frame Number Overflow
+     * |        |          |This bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
+     * |        |          |0 = The bit 15 of Frame Number didn't change.
+     * |        |          |1 = The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[6]     |RHSC      |Root Hub Status Change
+     * |        |          |This bit is set when the content of HcRhStatus or the content of HcRhPortStatus register has changed.
+     * |        |          |0 = The content of HcRhStatus and the content of HcRhPortStatus register didn't change.
+     * |        |          |1 = The content of HcRhStatus or the content of HcRhPortStatus register has changed.
+     * |        |          |Note: This bit is cleared by writing ‘1Fh’ to HcRhPortStatus1[20:16].
+     * @var USBH_T::HcInterruptEnable
+     * Offset: 0x10  Host Controller Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SO        |Scheduling Overrun Enable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.
+     * |        |          |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled.
+     * |[1]     |WDH       |Write Back Done Head Enable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.
+     * |        |          |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled.
+     * |[2]     |SF        |Start of Frame Enable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.
+     * |        |          |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled.
+     * |[3]     |RD        |Resume Detected Enable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.
+     * |        |          |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled.
+     * |[5]     |FNO       |Frame Number Overflow Enable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.
+     * |        |          |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled.
+     * |[6]     |RHSC      |Root Hub Status Change Enable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.
+     * |        |          |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled.
+     * |[31]    |MIE       |Master Interrupt Enable Bit
+     * |        |          |This bit is a global interrupt enable
+     * |        |          |A write of u20181' allows interrupts to be enabled via the specific enable bits listed above.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high.
+     * |        |          |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high.
+     * @var USBH_T::HcInterruptDisable
+     * Offset: 0x14  Host Controller Interrupt Disable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SO        |Scheduling Overrun Disable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled.
+     * |        |          |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled.
+     * |[1]     |WDH       |Write Back Done Head Disable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled.
+     * |        |          |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled.
+     * |[2]     |SF        |Start of Frame Disable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled.
+     * |        |          |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled.
+     * |[3]     |RD        |Resume Detected Disable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled.
+     * |        |          |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled.
+     * |[5]     |FNO       |Frame Number Overflow Disable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled.
+     * |        |          |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled.
+     * |[6]     |RHSC      |Root Hub Status Change Disable Bit
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled.
+     * |        |          |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled.
+     * |[31]    |MIE       |Master Interrupt Disable Bit
+     * |        |          |Global interrupt disable. Writing u20181' to disable all interrupts.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled if the corresponding bit in HcInterruptEnable is high.
+     * |        |          |Read Operation:
+     * |        |          |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high.
+     * |        |          |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high.
+     * @var USBH_T::HcHCCA
+     * Offset: 0x18  Host Controller Communication Area Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:8]  |HCCA      |Host Controller Communication Area
+     * |        |          |Pointer to indicate the base address of the Host Controller Communication Area (HCCA).
+     * @var USBH_T::HcPeriodCurrentED
+     * Offset: 0x1C  Host Controller Period Current ED Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:4]  |PCED      |Periodic Current ED
+     * |        |          |Pointer to indicate the physical address of the current Isochronous or Interrupt Endpoint Descriptor.
+     * @var USBH_T::HcControlHeadED
+     * Offset: 0x20  Host Controller Control ED Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:4]  |CHED      |Control Head ED
+     * |        |          |Pointer to indicate the physical address of the first Endpoint Descriptor of the Control list.
+     * @var USBH_T::HcControlCurrentED
+     * Offset: 0x24  Host Controller Control Current ED Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:4]  |CCED      |Control Current Head ED
+     * |        |          |Pointer to indicate the physical address of the current Endpoint Descriptor of the Control list.
+     * @var USBH_T::HcBulkHeadED
+     * Offset: 0x28  Host Controller Bulk Head ED Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:4]  |BHED      |Bulk Head ED
+     * |        |          |Pointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list.
+     * @var USBH_T::HcBulkCurrentED
+     * Offset: 0x2C  Host Controller Bulk Current ED Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:4]  |BCED      |Bulk Current Head ED
+     * |        |          |Pointer to indicate the physical address of the current endpoint of the Bulk list.
+     * @var USBH_T::HcDoneHead
+     * Offset: 0x30  Host Controller Done Head Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:4]  |DH        |Done Head
+     * |        |          |Pointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue.
+     * @var USBH_T::HcFmInterval
+     * Offset: 0x34  Host Controller Frame Interval Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[13:0]  |FI        |Frame Interval
+     * |        |          |This field specifies the length of a frame as (bit times - 1)
+     * |        |          |For 12,000 bit times in a frame, a value of 11,999 is stored here.
+     * |[29:16] |FSMPS     |FS Largest Data Packet
+     * |        |          |This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame.
+     * |[31]    |FIT       |Frame Interval Toggle
+     * |        |          |This bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0]).
+     * |        |          |0 = Host Controller Driver didn't load new value into FI (HcFmInterval[13:0]).
+     * |        |          |1 = Host Controller Driver loads a new value into FI (HcFmInterval[13:0]).
+     * @var USBH_T::HcFmRemaining
+     * Offset: 0x38  Host Controller Frame Remaining Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[13:0]  |FR        |Frame Remaining
+     * |        |          |When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period
+     * |        |          |When the count reaches 0, (end of frame) the counter reloads with Frame Interval
+     * |        |          |In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL.
+     * |[31]    |FRT       |Frame Remaining Toggle
+     * |        |          |This bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0.
+     * @var USBH_T::HcFmNumber
+     * Offset: 0x3C  Host Controller Frame Number Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |FN        |Frame Number
+     * |        |          |This 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRemaining[13:0])
+     * |        |          |The count rolls over from u2018FFFFh' to u20180h.'
+     * @var USBH_T::HcPeriodicStart
+     * Offset: 0x40  Host Controller Periodic Start Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[13:0]  |PS        |Periodic Start
+     * |        |          |This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin.
+     * @var USBH_T::HcLSThreshold
+     * Offset: 0x44  Host Controller Low-speed Threshold Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[11:0]  |LST       |Low-speed Threshold
+     * |        |          |This field contains a value which is compared to the FR (HcFmRemaining[13:0]) field prior to initiating a Low-speed transaction
+     * |        |          |The transaction is started only if FR (HcFmRemaining[13:0]) >= this field
+     * |        |          |The value is calculated by Host Controller Driver with the consideration of transmission and setup overhead.
+     * @var USBH_T::HcRhDescriptorA
+     * Offset: 0x48  Host Controller Root Hub Descriptor A Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7:0]   |NDP       |Number Downstream Ports
+     * |        |          |USB host control supports two downstream ports and only one port is available in this series of chip.
+     * |        |          |Note: NDP = 1 in this series of chip.
+     * |[8]     |PSM       |Power Switching Mode
+     * |        |          |This bit is used to specify how the power switching of the Root Hub ports is controlled.
+     * |        |          |0 = Global switching.
+     * |        |          |1 = Individual switching.
+     * |[11]    |OCPM      |Over Current Protection Mode
+     * |        |          |This bit describes how the over current status for the Root Hub ports reported
+     * |        |          |This bit is only valid when NOCP (HcRhDescriptorA[12]) is cleared.
+     * |        |          |0 = Global over current.
+     * |        |          |1 = Individual over current.
+     * |[12]    |NOCP      |No Over Current Protection
+     * |        |          |This bit describes how the over current status for the Root Hub ports reported.
+     * |        |          |0 = Over current status is reported.
+     * |        |          |1 = Over current status is not reported.
+     * @var USBH_T::HcRhDescriptorB
+     * Offset: 0x4C  Host Controller Root Hub Descriptor B Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:16] |PPCM      |Port Power Control Mask
+     * |        |          |Global power switching
+     * |        |          |This field is only valid if Power Switching Mode is set (individual port switching)
+     * |        |          |When set, the port only responds to individual port power switching commands (Set/Clear Port Power)
+     * |        |          |When cleared, the port only responds to global power switching commands (Set/Clear Global Power).
+     * |        |          |0 = Port power controlled by global power switching.
+     * |        |          |1 = Port power controlled by port power switching.
+     * |        |          |Note: PPCM[15:2] and PPCM[0] are reserved.
+     * @var USBH_T::HcRhStatus
+     * Offset: 0x50  Host Controller Root Hub Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |LPS       |Clear Global Power
+     * |        |          |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to clear all ports' power.
+     * |        |          |This bit always read as zero.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear global power.
+     * |[1]     |OCI       |Over Current Indicator (Read-Only)
+     * |        |          |This bit reflects the state of the over current status pin
+     * |        |          |This field is only valid if NOCP (HcRhDescriptorA[12]) and OCPM (HcRhDescriptorA[11]) are cleared.
+     * |        |          |0 = No over current condition.
+     * |        |          |1 = Over current condition.
+     * |[15]    |DRWE      |Device Remote Wakeup Enable Bit
+     * |        |          |This bit controls if port's Connect Status Change as a remote wake-up event.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Connect Status Change as a remote wake-up event Enabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Connect Status Change as a remote wake-up event Disabled.
+     * |        |          |1 = Connect Status Change as a remote wake-up event Enabled.
+     * |[16]    |LPSC      |Set Global Power
+     * |        |          |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to enable power to all ports.
+     * |        |          |This bit always read as zero.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Set global power.
+     * |[17]    |OCIC      |Over Current Indicator Change
+     * |        |          |This bit is set by hardware when a change has occurred in OCI (HcRhStatus[1]).
+     * |        |          |Write 1 to clear this bit to zero.
+     * |        |          |0 = OCI (HcRhStatus[1]) didn't change.
+     * |        |          |1 = OCI (HcRhStatus[1]) change.
+     * |[31]    |CRWE      |Clear Remote Wake-up Enable Bit
+     * |        |          |This bit is use to clear DRWE (HcRhStatus[15]).
+     * |        |          |This bit always read as zero.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear DRWE (HcRhStatus[15]).
+     * @var USBH_T::HcRhPortStatus[2]
+     * Offset: 0x54  Host Controller Root Hub Port Status
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |CCS       |Current Connect Status (Read) or Clear Port Enable (Write)
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear port enable.
+     * |        |          |Read Operation:
+     * |        |          |0 = No device connected.
+     * |        |          |1 = Device connected.
+     * |[1]     |PES       |Port Enable Status (Read) or Set Port Enable (Write)
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Set port enable.
+     * |        |          |Read Operation:
+     * |        |          |0 = Port Disabled.
+     * |        |          |1 = Port Enabled.
+     * |[2]     |PSS       |Port Suspend Status (Read) or Set Port Suspend (Write)
+     * |        |          |This bit indicates the port is suspended
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Set port suspend.
+     * |        |          |Read Operation:
+     * |        |          |0 = Port is not suspended.
+     * |        |          |1 = Port is selectively suspended.
+     * |[3]     |POCI      |Port Over Current Indicator (Read) or Clear Port Suspend (Write)
+     * |        |          |This bit reflects the state of the over current status pin dedicated to this port
+     * |        |          |This field is only valid if NOCP (HcRhDescriptorA[12]) is cleared and OCPM (HcRhDescriptorA[11]) is set.
+     * |        |          |This bit is also used to initiate the selective result sequence for the port.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear port suspend.
+     * |        |          |Read Operation:
+     * |        |          |0 = No over current condition.
+     * |        |          |1 = Over current condition.
+     * |[4]     |PRS       |Port Reset Status (Read) or Set Port Reset (Write)
+     * |        |          |This bit reflects the reset state of the port.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Set port reset.
+     * |        |          |Read Operation
+     * |        |          |0 = Port reset signal is not active.
+     * |        |          |1 = Port reset signal is active.
+     * |[8]     |PPS       |Port Power Status (Read) or Set Port Power (Write)
+     * |        |          |This bit reflects the power state of the port regardless of the power switching mode.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Port Power Enabled.
+     * |        |          |Read Operation:
+     * |        |          |0 = Port power is Disabled.
+     * |        |          |1 = Port power is Enabled.
+     * |[9]     |LSDA      |Low Speed Device Attached (Read) or Clear Port Power (Write)
+     * |        |          |This bit defines the speed (and bus idle) of the attached device
+     * |        |          |It is only valid when CCS (HcRhPortStatus[0]) is set.
+     * |        |          |This bit is also used to clear port power.
+     * |        |          |Write Operation:
+     * |        |          |0 = No effect.
+     * |        |          |1 = Clear PPS (HcRhPortStatus[8]).
+     * |        |          |Read Operation:
+     * |        |          |0 = Full Speed device.
+     * |        |          |1 = Low-speed device.
+     * |[16]    |CSC       |Connect Status Change
+     * |        |          |This bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus[0]) changed).
+     * |        |          |Write 1 to clear this bit to zero.
+     * |        |          |0 = No connect/disconnect event (CCS (HcRhPortStatus[0]) didn't change).
+     * |        |          |1 = Hardware detection of connect/disconnect event (CCS (HcRhPortStatus[0]) changed).
+     * |[17]    |PESC      |Port Enable Status Change
+     * |        |          |This bit indicates that the port has been disabled (PES (HcRhPortStatus[1]) cleared) due to a hardware event.
+     * |        |          |Write 1 to clear this bit to zero.
+     * |        |          |0 = PES (HcRhPortStatus[1]) didn't change.
+     * |        |          |1 = PES (HcRhPortStatus[1]) changed.
+     * |[18]    |PSSC      |Port Suspend Status Change
+     * |        |          |This bit indicates the completion of the selective resume sequence for the port.
+     * |        |          |Write 1 to clear this bit to zero.
+     * |        |          |0 = Port resume is not complete.
+     * |        |          |1 = Port resume complete.
+     * |[19]    |OCIC      |Port Over Current Indicator Change
+     * |        |          |This bit is set when POCI (HcRhPortStatus[3]) changes.
+     * |        |          |Write 1 to clear this bit to zero.
+     * |        |          |0 = POCI (HcRhPortStatus[3]) didn't change.
+     * |        |          |1 = POCI (HcRhPortStatus[3]) changes.
+     * |[20]    |PRSC      |Port Reset Status Change
+     * |        |          |This bit indicates that the port reset signal has completed.
+     * |        |          |Write 1 to clear this bit to zero.
+     * |        |          |0 = Port reset is not complete.
+     * |        |          |1 = Port reset is complete.
+     * @var USBH_T::HcPhyControl
+     * Offset: 0x200  Host Controller PHY Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[27]    |STBYEN    |USB Transceiver Standby Enable Bit
+     * |        |          |This bit controls if USB transceiver could enter the standby mode to reduce power consumption.
+     * |        |          |0 = The USB transceiver would never enter the standby mode.
+     * |        |          |1 = The USB transceiver will enter standby mode while port is in power off state (port power is inactive).
+     * @var USBH_T::HcMiscControl
+     * Offset: 0x204  Host Controller Miscellaneous Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1]     |ABORT     |AHB Bus Error Response
+     * |        |          |This bit indicates there is an Error response received in AHB bus.
+     * |        |          |0 = No Error response received.
+     * |        |          |1 = Error response received.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[3]     |OCAL      |over Current Active Low
+     * |        |          |This bit controls the polarity of over current flag from external power IC.
+     * |        |          |0 = Over current flag is high active.
+     * |        |          |1 = Over current flag is low active.
+     * |[16]    |DPRT1     |Disable Port 1
+     * |        |          |This bit controls if the connection between USB host controller and transceiver of port 1 is disabled
+     * |        |          |If the connection is disabled, the USB host controller will not recognize any event of USB bus.
+     * |        |          |Set this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is.
+     * |        |          |0 = The connection between USB host controller and transceiver of port 1 Enabled.
+     * |        |          |1 = The connection between USB host controller and transceiver of port 1 Disabled and the transceiver of port 1 will also be forced into the standby mode.
+     */
+    __I  uint32_t HcRevision;            /*!< [0x0000] Host Controller Revision Register                                */
+    __IO uint32_t HcControl;             /*!< [0x0004] Host Controller Control Register                                 */
+    __IO uint32_t HcCommandStatus;       /*!< [0x0008] Host Controller Command Status Register                          */
+    __IO uint32_t HcInterruptStatus;     /*!< [0x000c] Host Controller Interrupt Status Register                        */
+    __IO uint32_t HcInterruptEnable;     /*!< [0x0010] Host Controller Interrupt Enable Register                        */
+    __IO uint32_t HcInterruptDisable;    /*!< [0x0014] Host Controller Interrupt Disable Register                       */
+    __IO uint32_t HcHCCA;                /*!< [0x0018] Host Controller Communication Area Register                      */
+    __IO uint32_t HcPeriodCurrentED;     /*!< [0x001c] Host Controller Period Current ED Register                       */
+    __IO uint32_t HcControlHeadED;       /*!< [0x0020] Host Controller Control Head ED Register                         */
+    __IO uint32_t HcControlCurrentED;    /*!< [0x0024] Host Controller Control Current ED Register                      */
+    __IO uint32_t HcBulkHeadED;          /*!< [0x0028] Host Controller Bulk Head ED Register                            */
+    __IO uint32_t HcBulkCurrentED;       /*!< [0x002c] Host Controller Bulk Current ED Register                         */
+    __IO uint32_t HcDoneHead;            /*!< [0x0030] Host Controller Done Head Register                               */
+    __IO uint32_t HcFmInterval;          /*!< [0x0034] Host Controller Frame Interval Register                          */
+    __I  uint32_t HcFmRemaining;         /*!< [0x0038] Host Controller Frame Remaining Register                         */
+    __I  uint32_t HcFmNumber;            /*!< [0x003c] Host Controller Frame Number Register                            */
+    __IO uint32_t HcPeriodicStart;       /*!< [0x0040] Host Controller Periodic Start Register                          */
+    __IO uint32_t HcLSThreshold;         /*!< [0x0044] Host Controller Low-speed Threshold Register                     */
+    __IO uint32_t HcRhDescriptorA;       /*!< [0x0048] Host Controller Root Hub Descriptor A Register                   */
+    __IO uint32_t HcRhDescriptorB;       /*!< [0x004c] Host Controller Root Hub Descriptor B Register                   */
+    __IO uint32_t HcRhStatus;            /*!< [0x0050] Host Controller Root Hub Status Register                         */
+    __IO uint32_t HcRhPortStatus[2];     /*!< [0x0054] Host Controller Root Hub Port Status                             */
+    __I  uint32_t RESERVE0[105];
+    __IO uint32_t HcPhyControl;          /*!< [0x0200] Host Controller PHY Control Register                             */
+    __IO uint32_t HcMiscControl;         /*!< [0x0204] Host Controller Miscellaneous Control Register                   */
+
+} USBH_T;
+
+/**
+    @addtogroup USBH_CONST USBH Bit Field Definition
+    Constant Definitions for USBH Controller
+  @{
+*/
+
+#define USBH_HcRevision_REV_Pos          (0)                                               /*!< USBH_T::HcRevision: REV Position       */
+#define USBH_HcRevision_REV_Msk          (0xfful << USBH_HcRevision_REV_Pos)               /*!< USBH_T::HcRevision: REV Mask           */
+
+#define USBH_HcControl_CBSR_Pos          (0)                                               /*!< USBH_T::HcControl: CBSR Position       */
+#define USBH_HcControl_CBSR_Msk          (0x3ul << USBH_HcControl_CBSR_Pos)                /*!< USBH_T::HcControl: CBSR Mask           */
+
+#define USBH_HcControl_PLE_Pos           (2)                                               /*!< USBH_T::HcControl: PLE Position        */
+#define USBH_HcControl_PLE_Msk           (0x1ul << USBH_HcControl_PLE_Pos)                 /*!< USBH_T::HcControl: PLE Mask            */
+
+#define USBH_HcControl_IE_Pos            (3)                                               /*!< USBH_T::HcControl: IE Position         */
+#define USBH_HcControl_IE_Msk            (0x1ul << USBH_HcControl_IE_Pos)                  /*!< USBH_T::HcControl: IE Mask             */
+
+#define USBH_HcControl_CLE_Pos           (4)                                               /*!< USBH_T::HcControl: CLE Position        */
+#define USBH_HcControl_CLE_Msk           (0x1ul << USBH_HcControl_CLE_Pos)                 /*!< USBH_T::HcControl: CLE Mask            */
+
+#define USBH_HcControl_BLE_Pos           (5)                                               /*!< USBH_T::HcControl: BLE Position        */
+#define USBH_HcControl_BLE_Msk           (0x1ul << USBH_HcControl_BLE_Pos)                 /*!< USBH_T::HcControl: BLE Mask            */
+
+#define USBH_HcControl_HCFS_Pos          (6)                                               /*!< USBH_T::HcControl: HCFS Position       */
+#define USBH_HcControl_HCFS_Msk          (0x3ul << USBH_HcControl_HCFS_Pos)                /*!< USBH_T::HcControl: HCFS Mask           */
+
+#define USBH_HcCommandStatus_HCR_Pos     (0)                                               /*!< USBH_T::HcCommandStatus: HCR Position  */
+#define USBH_HcCommandStatus_HCR_Msk     (0x1ul << USBH_HcCommandStatus_HCR_Pos)           /*!< USBH_T::HcCommandStatus: HCR Mask      */
+
+#define USBH_HcCommandStatus_CLF_Pos     (1)                                               /*!< USBH_T::HcCommandStatus: CLF Position  */
+#define USBH_HcCommandStatus_CLF_Msk     (0x1ul << USBH_HcCommandStatus_CLF_Pos)           /*!< USBH_T::HcCommandStatus: CLF Mask      */
+
+#define USBH_HcCommandStatus_BLF_Pos     (2)                                               /*!< USBH_T::HcCommandStatus: BLF Position  */
+#define USBH_HcCommandStatus_BLF_Msk     (0x1ul << USBH_HcCommandStatus_BLF_Pos)           /*!< USBH_T::HcCommandStatus: BLF Mask      */
+
+#define USBH_HcCommandStatus_SOC_Pos     (16)                                              /*!< USBH_T::HcCommandStatus: SOC Position  */
+#define USBH_HcCommandStatus_SOC_Msk     (0x3ul << USBH_HcCommandStatus_SOC_Pos)           /*!< USBH_T::HcCommandStatus: SOC Mask      */
+
+#define USBH_HcInterruptStatus_SO_Pos    (0)                                               /*!< USBH_T::HcInterruptStatus: SO Position */
+#define USBH_HcInterruptStatus_SO_Msk    (0x1ul << USBH_HcInterruptStatus_SO_Pos)          /*!< USBH_T::HcInterruptStatus: SO Mask     */
+
+#define USBH_HcInterruptStatus_WDH_Pos   (1)                                               /*!< USBH_T::HcInterruptStatus: WDH Position*/
+#define USBH_HcInterruptStatus_WDH_Msk   (0x1ul << USBH_HcInterruptStatus_WDH_Pos)         /*!< USBH_T::HcInterruptStatus: WDH Mask    */
+
+#define USBH_HcInterruptStatus_SF_Pos    (2)                                               /*!< USBH_T::HcInterruptStatus: SF Position */
+#define USBH_HcInterruptStatus_SF_Msk    (0x1ul << USBH_HcInterruptStatus_SF_Pos)          /*!< USBH_T::HcInterruptStatus: SF Mask     */
+
+#define USBH_HcInterruptStatus_RD_Pos    (3)                                               /*!< USBH_T::HcInterruptStatus: RD Position */
+#define USBH_HcInterruptStatus_RD_Msk    (0x1ul << USBH_HcInterruptStatus_RD_Pos)          /*!< USBH_T::HcInterruptStatus: RD Mask     */
+
+#define USBH_HcInterruptStatus_FNO_Pos   (5)                                               /*!< USBH_T::HcInterruptStatus: FNO Position*/
+#define USBH_HcInterruptStatus_FNO_Msk   (0x1ul << USBH_HcInterruptStatus_FNO_Pos)         /*!< USBH_T::HcInterruptStatus: FNO Mask    */
+
+#define USBH_HcInterruptStatus_RHSC_Pos  (6)                                               /*!< USBH_T::HcInterruptStatus: RHSC Position*/
+#define USBH_HcInterruptStatus_RHSC_Msk  (0x1ul << USBH_HcInterruptStatus_RHSC_Pos)        /*!< USBH_T::HcInterruptStatus: RHSC Mask   */
+
+#define USBH_HcInterruptEnable_SO_Pos    (0)                                               /*!< USBH_T::HcInterruptEnable: SO Position */
+#define USBH_HcInterruptEnable_SO_Msk    (0x1ul << USBH_HcInterruptEnable_SO_Pos)          /*!< USBH_T::HcInterruptEnable: SO Mask     */
+
+#define USBH_HcInterruptEnable_WDH_Pos   (1)                                               /*!< USBH_T::HcInterruptEnable: WDH Position*/
+#define USBH_HcInterruptEnable_WDH_Msk   (0x1ul << USBH_HcInterruptEnable_WDH_Pos)         /*!< USBH_T::HcInterruptEnable: WDH Mask    */
+
+#define USBH_HcInterruptEnable_SF_Pos    (2)                                               /*!< USBH_T::HcInterruptEnable: SF Position */
+#define USBH_HcInterruptEnable_SF_Msk    (0x1ul << USBH_HcInterruptEnable_SF_Pos)          /*!< USBH_T::HcInterruptEnable: SF Mask     */
+
+#define USBH_HcInterruptEnable_RD_Pos    (3)                                               /*!< USBH_T::HcInterruptEnable: RD Position */
+#define USBH_HcInterruptEnable_RD_Msk    (0x1ul << USBH_HcInterruptEnable_RD_Pos)          /*!< USBH_T::HcInterruptEnable: RD Mask     */
+
+#define USBH_HcInterruptEnable_FNO_Pos   (5)                                               /*!< USBH_T::HcInterruptEnable: FNO Position*/
+#define USBH_HcInterruptEnable_FNO_Msk   (0x1ul << USBH_HcInterruptEnable_FNO_Pos)         /*!< USBH_T::HcInterruptEnable: FNO Mask    */
+
+#define USBH_HcInterruptEnable_RHSC_Pos  (6)                                               /*!< USBH_T::HcInterruptEnable: RHSC Position*/
+#define USBH_HcInterruptEnable_RHSC_Msk  (0x1ul << USBH_HcInterruptEnable_RHSC_Pos)        /*!< USBH_T::HcInterruptEnable: RHSC Mask   */
+
+#define USBH_HcInterruptEnable_MIE_Pos   (31)                                              /*!< USBH_T::HcInterruptEnable: MIE Position*/
+#define USBH_HcInterruptEnable_MIE_Msk   (0x1ul << USBH_HcInterruptEnable_MIE_Pos)         /*!< USBH_T::HcInterruptEnable: MIE Mask    */
+
+#define USBH_HcInterruptDisable_SO_Pos   (0)                                               /*!< USBH_T::HcInterruptDisable: SO Position*/
+#define USBH_HcInterruptDisable_SO_Msk   (0x1ul << USBH_HcInterruptDisable_SO_Pos)         /*!< USBH_T::HcInterruptDisable: SO Mask    */
+
+#define USBH_HcInterruptDisable_WDH_Pos  (1)                                               /*!< USBH_T::HcInterruptDisable: WDH Position*/
+#define USBH_HcInterruptDisable_WDH_Msk  (0x1ul << USBH_HcInterruptDisable_WDH_Pos)        /*!< USBH_T::HcInterruptDisable: WDH Mask   */
+
+#define USBH_HcInterruptDisable_SF_Pos   (2)                                               /*!< USBH_T::HcInterruptDisable: SF Position*/
+#define USBH_HcInterruptDisable_SF_Msk   (0x1ul << USBH_HcInterruptDisable_SF_Pos)         /*!< USBH_T::HcInterruptDisable: SF Mask    */
+
+#define USBH_HcInterruptDisable_RD_Pos   (3)                                               /*!< USBH_T::HcInterruptDisable: RD Position*/
+#define USBH_HcInterruptDisable_RD_Msk   (0x1ul << USBH_HcInterruptDisable_RD_Pos)         /*!< USBH_T::HcInterruptDisable: RD Mask    */
+
+#define USBH_HcInterruptDisable_FNO_Pos  (5)                                               /*!< USBH_T::HcInterruptDisable: FNO Position*/
+#define USBH_HcInterruptDisable_FNO_Msk  (0x1ul << USBH_HcInterruptDisable_FNO_Pos)        /*!< USBH_T::HcInterruptDisable: FNO Mask   */
+
+#define USBH_HcInterruptDisable_RHSC_Pos (6)                                               /*!< USBH_T::HcInterruptDisable: RHSC Position*/
+#define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos)       /*!< USBH_T::HcInterruptDisable: RHSC Mask  */
+
+#define USBH_HcInterruptDisable_MIE_Pos  (31)                                              /*!< USBH_T::HcInterruptDisable: MIE Position*/
+#define USBH_HcInterruptDisable_MIE_Msk  (0x1ul << USBH_HcInterruptDisable_MIE_Pos)        /*!< USBH_T::HcInterruptDisable: MIE Mask   */
+
+#define USBH_HcHCCA_HCCA_Pos             (8)                                               /*!< USBH_T::HcHCCA: HCCA Position          */
+#define USBH_HcHCCA_HCCA_Msk             (0xfffffful << USBH_HcHCCA_HCCA_Pos)              /*!< USBH_T::HcHCCA: HCCA Mask              */
+
+#define USBH_HcPeriodCurrentED_PCED_Pos  (4)                                               /*!< USBH_T::HcPeriodCurrentED: PCED Position*/
+#define USBH_HcPeriodCurrentED_PCED_Msk  (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos)  /*!< USBH_T::HcPeriodCurrentED: PCED Mask   */
+
+#define USBH_HcControlHeadED_CHED_Pos    (4)                                               /*!< USBH_T::HcControlHeadED: CHED Position */
+#define USBH_HcControlHeadED_CHED_Msk    (0xffffffful << USBH_HcControlHeadED_CHED_Pos)    /*!< USBH_T::HcControlHeadED: CHED Mask     */
+
+#define USBH_HcControlCurrentED_CCED_Pos (4)                                               /*!< USBH_T::HcControlCurrentED: CCED Position*/
+#define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) /*!< USBH_T::HcControlCurrentED: CCED Mask  */
+
+#define USBH_HcBulkHeadED_BHED_Pos       (4)                                               /*!< USBH_T::HcBulkHeadED: BHED Position    */
+#define USBH_HcBulkHeadED_BHED_Msk       (0xffffffful << USBH_HcBulkHeadED_BHED_Pos)       /*!< USBH_T::HcBulkHeadED: BHED Mask        */
+
+#define USBH_HcBulkCurrentED_BCED_Pos    (4)                                               /*!< USBH_T::HcBulkCurrentED: BCED Position */
+#define USBH_HcBulkCurrentED_BCED_Msk    (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos)    /*!< USBH_T::HcBulkCurrentED: BCED Mask     */
+
+#define USBH_HcDoneHead_DH_Pos           (4)                                               /*!< USBH_T::HcDoneHead: DH Position        */
+#define USBH_HcDoneHead_DH_Msk           (0xffffffful << USBH_HcDoneHead_DH_Pos)           /*!< USBH_T::HcDoneHead: DH Mask            */
+
+#define USBH_HcFmInterval_FI_Pos         (0)                                               /*!< USBH_T::HcFmInterval: FI Position      */
+#define USBH_HcFmInterval_FI_Msk         (0x3ffful << USBH_HcFmInterval_FI_Pos)            /*!< USBH_T::HcFmInterval: FI Mask          */
+
+#define USBH_HcFmInterval_FSMPS_Pos      (16)                                              /*!< USBH_T::HcFmInterval: FSMPS Position   */
+#define USBH_HcFmInterval_FSMPS_Msk      (0x3ffful << USBH_HcFmInterval_FSMPS_Pos)         /*!< USBH_T::HcFmInterval: FSMPS Mask       */
+
+#define USBH_HcFmInterval_FIT_Pos        (31)                                              /*!< USBH_T::HcFmInterval: FIT Position     */
+#define USBH_HcFmInterval_FIT_Msk        (0x1ul << USBH_HcFmInterval_FIT_Pos)              /*!< USBH_T::HcFmInterval: FIT Mask         */
+
+#define USBH_HcFmRemaining_FR_Pos        (0)                                               /*!< USBH_T::HcFmRemaining: FR Position     */
+#define USBH_HcFmRemaining_FR_Msk        (0x3ffful << USBH_HcFmRemaining_FR_Pos)           /*!< USBH_T::HcFmRemaining: FR Mask         */
+
+#define USBH_HcFmRemaining_FRT_Pos       (31)                                              /*!< USBH_T::HcFmRemaining: FRT Position    */
+#define USBH_HcFmRemaining_FRT_Msk       (0x1ul << USBH_HcFmRemaining_FRT_Pos)             /*!< USBH_T::HcFmRemaining: FRT Mask        */
+
+#define USBH_HcFmNumber_FN_Pos           (0)                                               /*!< USBH_T::HcFmNumber: FN Position        */
+#define USBH_HcFmNumber_FN_Msk           (0xfffful << USBH_HcFmNumber_FN_Pos)              /*!< USBH_T::HcFmNumber: FN Mask            */
+
+#define USBH_HcPeriodicStart_PS_Pos      (0)                                               /*!< USBH_T::HcPeriodicStart: PS Position   */
+#define USBH_HcPeriodicStart_PS_Msk      (0x3ffful << USBH_HcPeriodicStart_PS_Pos)         /*!< USBH_T::HcPeriodicStart: PS Mask       */
+
+#define USBH_HcLSThreshold_LST_Pos       (0)                                               /*!< USBH_T::HcLSThreshold: LST Position    */
+#define USBH_HcLSThreshold_LST_Msk       (0xffful << USBH_HcLSThreshold_LST_Pos)           /*!< USBH_T::HcLSThreshold: LST Mask        */
+
+#define USBH_HcRhDescriptorA_NDP_Pos     (0)                                               /*!< USBH_T::HcRhDescriptorA: NDP Position  */
+#define USBH_HcRhDescriptorA_NDP_Msk     (0xfful << USBH_HcRhDescriptorA_NDP_Pos)          /*!< USBH_T::HcRhDescriptorA: NDP Mask      */
+
+#define USBH_HcRhDescriptorA_PSM_Pos     (8)                                               /*!< USBH_T::HcRhDescriptorA: PSM Position  */
+#define USBH_HcRhDescriptorA_PSM_Msk     (0x1ul << USBH_HcRhDescriptorA_PSM_Pos)           /*!< USBH_T::HcRhDescriptorA: PSM Mask      */
+
+#define USBH_HcRhDescriptorA_OCPM_Pos    (11)                                              /*!< USBH_T::HcRhDescriptorA: OCPM Position */
+#define USBH_HcRhDescriptorA_OCPM_Msk    (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos)          /*!< USBH_T::HcRhDescriptorA: OCPM Mask     */
+
+#define USBH_HcRhDescriptorA_NOCP_Pos    (12)                                              /*!< USBH_T::HcRhDescriptorA: NOCP Position */
+#define USBH_HcRhDescriptorA_NOCP_Msk    (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos)          /*!< USBH_T::HcRhDescriptorA: NOCP Mask     */
+
+#define USBH_HcRhDescriptorB_PPCM_Pos    (16)                                              /*!< USBH_T::HcRhDescriptorB: PPCM Position */
+#define USBH_HcRhDescriptorB_PPCM_Msk    (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos)       /*!< USBH_T::HcRhDescriptorB: PPCM Mask     */
+
+#define USBH_HcRhStatus_LPS_Pos          (0)                                               /*!< USBH_T::HcRhStatus: LPS Position       */
+#define USBH_HcRhStatus_LPS_Msk          (0x1ul << USBH_HcRhStatus_LPS_Pos)                /*!< USBH_T::HcRhStatus: LPS Mask           */
+
+#define USBH_HcRhStatus_OCI_Pos          (1)                                               /*!< USBH_T::HcRhStatus: OCI Position       */
+#define USBH_HcRhStatus_OCI_Msk          (0x1ul << USBH_HcRhStatus_OCI_Pos)                /*!< USBH_T::HcRhStatus: OCI Mask           */
+
+#define USBH_HcRhStatus_DRWE_Pos         (15)                                              /*!< USBH_T::HcRhStatus: DRWE Position      */
+#define USBH_HcRhStatus_DRWE_Msk         (0x1ul << USBH_HcRhStatus_DRWE_Pos)               /*!< USBH_T::HcRhStatus: DRWE Mask          */
+
+#define USBH_HcRhStatus_LPSC_Pos         (16)                                              /*!< USBH_T::HcRhStatus: LPSC Position      */
+#define USBH_HcRhStatus_LPSC_Msk         (0x1ul << USBH_HcRhStatus_LPSC_Pos)               /*!< USBH_T::HcRhStatus: LPSC Mask          */
+
+#define USBH_HcRhStatus_OCIC_Pos         (17)                                              /*!< USBH_T::HcRhStatus: OCIC Position      */
+#define USBH_HcRhStatus_OCIC_Msk         (0x1ul << USBH_HcRhStatus_OCIC_Pos)               /*!< USBH_T::HcRhStatus: OCIC Mask          */
+
+#define USBH_HcRhStatus_CRWE_Pos         (31)                                              /*!< USBH_T::HcRhStatus: CRWE Position      */
+#define USBH_HcRhStatus_CRWE_Msk         (0x1ul << USBH_HcRhStatus_CRWE_Pos)               /*!< USBH_T::HcRhStatus: CRWE Mask          */
+
+#define USBH_HcRhPortStatus_CCS_Pos      (0)                                               /*!< USBH_T::HcRhPortStatus: CCS Position   */
+#define USBH_HcRhPortStatus_CCS_Msk      (0x1ul << USBH_HcRhPortStatus_CCS_Pos)            /*!< USBH_T::HcRhPortStatus: CCS Mask       */
+
+#define USBH_HcRhPortStatus_PES_Pos      (1)                                               /*!< USBH_T::HcRhPortStatus: PES Position   */
+#define USBH_HcRhPortStatus_PES_Msk      (0x1ul << USBH_HcRhPortStatus_PES_Pos)            /*!< USBH_T::HcRhPortStatus: PES Mask       */
+
+#define USBH_HcRhPortStatus_PSS_Pos      (2)                                               /*!< USBH_T::HcRhPortStatus: PSS Position   */
+#define USBH_HcRhPortStatus_PSS_Msk      (0x1ul << USBH_HcRhPortStatus_PSS_Pos)            /*!< USBH_T::HcRhPortStatus: PSS Mask       */
+
+#define USBH_HcRhPortStatus_POCI_Pos     (3)                                               /*!< USBH_T::HcRhPortStatus: POCI Position  */
+#define USBH_HcRhPortStatus_POCI_Msk     (0x1ul << USBH_HcRhPortStatus_POCI_Pos)           /*!< USBH_T::HcRhPortStatus: POCI Mask      */
+
+#define USBH_HcRhPortStatus_PRS_Pos      (4)                                               /*!< USBH_T::HcRhPortStatus: PRS Position   */
+#define USBH_HcRhPortStatus_PRS_Msk      (0x1ul << USBH_HcRhPortStatus_PRS_Pos)            /*!< USBH_T::HcRhPortStatus: PRS Mask       */
+
+#define USBH_HcRhPortStatus_PPS_Pos      (8)                                               /*!< USBH_T::HcRhPortStatus: PPS Position   */
+#define USBH_HcRhPortStatus_PPS_Msk      (0x1ul << USBH_HcRhPortStatus_PPS_Pos)            /*!< USBH_T::HcRhPortStatus: PPS Mask       */
+
+#define USBH_HcRhPortStatus_LSDA_Pos     (9)                                               /*!< USBH_T::HcRhPortStatus: LSDA Position  */
+#define USBH_HcRhPortStatus_LSDA_Msk     (0x1ul << USBH_HcRhPortStatus_LSDA_Pos)           /*!< USBH_T::HcRhPortStatus: LSDA Mask      */
+
+#define USBH_HcRhPortStatus_CSC_Pos      (16)                                              /*!< USBH_T::HcRhPortStatus: CSC Position   */
+#define USBH_HcRhPortStatus_CSC_Msk      (0x1ul << USBH_HcRhPortStatus_CSC_Pos)            /*!< USBH_T::HcRhPortStatus: CSC Mask       */
+
+#define USBH_HcRhPortStatus_PESC_Pos     (17)                                              /*!< USBH_T::HcRhPortStatus: PESC Position  */
+#define USBH_HcRhPortStatus_PESC_Msk     (0x1ul << USBH_HcRhPortStatus_PESC_Pos)           /*!< USBH_T::HcRhPortStatus: PESC Mask      */
+
+#define USBH_HcRhPortStatus_PSSC_Pos     (18)                                              /*!< USBH_T::HcRhPortStatus: PSSC Position  */
+#define USBH_HcRhPortStatus_PSSC_Msk     (0x1ul << USBH_HcRhPortStatus_PSSC_Pos)           /*!< USBH_T::HcRhPortStatus: PSSC Mask      */
+
+#define USBH_HcRhPortStatus_OCIC_Pos     (19)                                              /*!< USBH_T::HcRhPortStatus: OCIC Position  */
+#define USBH_HcRhPortStatus_OCIC_Msk     (0x1ul << USBH_HcRhPortStatus_OCIC_Pos)           /*!< USBH_T::HcRhPortStatus: OCIC Mask      */
+
+#define USBH_HcRhPortStatus_PRSC_Pos     (20)                                              /*!< USBH_T::HcRhPortStatus: PRSC Position  */
+#define USBH_HcRhPortStatus_PRSC_Msk     (0x1ul << USBH_HcRhPortStatus_PRSC_Pos)           /*!< USBH_T::HcRhPortStatus: PRSC Mask      */
+
+#define USBH_HcPhyControl_STBYEN_Pos     (27)                                              /*!< USBH_T::HcPhyControl: STBYEN Position  */
+#define USBH_HcPhyControl_STBYEN_Msk     (0x1ul << USBH_HcPhyControl_STBYEN_Pos)           /*!< USBH_T::HcPhyControl: STBYEN Mask      */
+
+#define USBH_HcMiscControl_ABORT_Pos     (1)                                               /*!< USBH_T::HcMiscControl: ABORT Position  */
+#define USBH_HcMiscControl_ABORT_Msk     (0x1ul << USBH_HcMiscControl_ABORT_Pos)           /*!< USBH_T::HcMiscControl: ABORT Mask      */
+
+#define USBH_HcMiscControl_OCAL_Pos      (3)                                               /*!< USBH_T::HcMiscControl: OCAL Position   */
+#define USBH_HcMiscControl_OCAL_Msk      (0x1ul << USBH_HcMiscControl_OCAL_Pos)            /*!< USBH_T::HcMiscControl: OCAL Mask       */
+
+#define USBH_HcMiscControl_DPRT1_Pos     (16)                                              /*!< USBH_T::HcMiscControl: DPRT1 Position  */
+#define USBH_HcMiscControl_DPRT1_Msk     (0x1ul << USBH_HcMiscControl_DPRT1_Pos)           /*!< USBH_T::HcMiscControl: DPRT1 Mask      */
+
+/**@}*/ /* USBH_CONST */
+/**@}*/ /* end of USBH register group */
+/**@}*/ /* end of REGISTER group */
+
+#endif /* __USBH_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/uspi_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/uspi_reg.h
new file mode 100644
index 0000000000..2d3d5307b2
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/uspi_reg.h
@@ -0,0 +1,666 @@
+/**************************************************************************//**
+ * @file     uspi_reg.h
+ * @version  V1.00
+ * @brief    USPI register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __USPI_REG_H__
+#define __USPI_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+/*---------------------- SPI Mode of USCI Controller -------------------------*/
+/**
+    @addtogroup USPI SPI Mode of USCI Controller(USPI)
+    Memory Mapped Structure for USPI Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var USPI_T::CTL
+     * Offset: 0x00  USCI Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |FUNMODE   |Function Mode
+     * |        |          |This bit field selects the protocol for this USCI controller
+     * |        |          |Selecting a protocol that is not available or a reserved combination disables the USCI
+     * |        |          |When switching between two protocols, the USCI has to be disabled before selecting a new protocol
+     * |        |          |Simultaneously, the USCI will be reset when user write 000 to FUNMODE.
+     * |        |          |000 = The USCI is disabled. All protocol related state machines are set to idle state.
+     * |        |          |001 = The SPI protocol is selected.
+     * |        |          |010 = The UART protocol is selected.
+     * |        |          |100 = The I2C protocol is selected.
+     * |        |          |Note: Other bit combinations are reserved.
+     * @var USPI_T::INTEN
+     * Offset: 0x04  USCI Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1]     |TXSTIEN   |Transmit Start Interrupt Enable Bit
+     * |        |          |This bit enables the interrupt generation in case of a transmit start event.
+     * |        |          |0 = The transmit start interrupt is disabled.
+     * |        |          |1 = The transmit start interrupt is enabled.
+     * |[2]     |TXENDIEN  |Transmit End Interrupt Enable Bit
+     * |        |          |This bit enables the interrupt generation in case of a transmit finish event.
+     * |        |          |0 = The transmit finish interrupt is disabled.
+     * |        |          |1 = The transmit finish interrupt is enabled.
+     * |[3]     |RXSTIEN   |Receive Start Interrupt Enable Bit
+     * |        |          |This bit enables the interrupt generation in case of a receive start event.
+     * |        |          |0 = The receive start interrupt is disabled.
+     * |        |          |1 = The receive start interrupt is enabled.
+     * |[4]     |RXENDIEN  |Receive End Interrupt Enable Bit
+     * |        |          |This bit enables the interrupt generation in case of a receive finish event.
+     * |        |          |0 = The receive end interrupt is disabled.
+     * |        |          |1 = The receive end interrupt is enabled.
+     * @var USPI_T::BRGEN
+     * Offset: 0x08  USCI Baud Rate Generator Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RCLKSEL   |Reference Clock Source Selection
+     * |        |          |This bit selects the source of reference clock (fREF_CLK).
+     * |        |          |0 = Peripheral device clock fPCLK.
+     * |        |          |1 = Reserved.
+     * |[1]     |PTCLKSEL  |Protocol Clock Source Selection
+     * |        |          |This bit selects the source of protocol clock (fPROT_CLK).
+     * |        |          |0 = Reference clock fREF_CLK.
+     * |        |          |1 = fREF_CLK2 (its frequency is half of fREF_CLK).
+     * |[3:2]   |SPCLKSEL  |Sample Clock Source Selection
+     * |        |          |This bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor.
+     * |        |          |00 = fDIV_CLK.
+     * |        |          |01 = fPROT_CLK.
+     * |        |          |10 = fSCLK.
+     * |        |          |11 = fREF_CLK.
+     * |[4]     |TMCNTEN   |Time Measurement Counter Enable Bit
+     * |        |          |This bit enables the 10-bit timing measurement counter.
+     * |        |          |0 = Time measurement counter is Disabled.
+     * |        |          |1 = Time measurement counter is Enabled.
+     * |[5]     |TMCNTSRC  |Time Measurement Counter Clock Source Selection
+     * |        |          |0 = Time measurement counter with fPROT_CLK.
+     * |        |          |1 = Time measurement counter with fDIV_CLK.
+     * |[25:16] |CLKDIV    |Clock Divider
+     * |        |          |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ).
+     * |        |          |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(USPI_PROTCTL[6])) is enabled
+     * |        |          |The revised value is the average bit time between bit 5 and bit 6
+     * |        |          |The user can use revised CLKDIV and new BRDETITV (USPI_PROTCTL[24:16]) to calculate the precise baud rate.
+     * @var USPI_T::DATIN0
+     * Offset: 0x10  USCI Input Data Signal Configuration Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SYNCSEL   |Input Signal Synchronization Selection
+     * |        |          |This bit selects if the un-synchronized input signal (with optionally inverted) or the   synchronized (and optionally filtered) signal can be used as input for the   data shift unit.
+     * |        |          |0 = The un-synchronized signal can be taken as input for the data shift unit.
+     * |        |          |1 = The synchronized signal can be taken as input for the data shift unit.
+     * |        |          |Note: In SPI protocol, it is suggested this bit should be set as 0.
+     * |[2]     |ININV     |Input Signal Inverse Selection
+     * |        |          |This bit defines the inverter enable of the input asynchronous signal.
+     * |        |          |0 = The un-synchronized input signal will not be inverted.
+     * |        |          |1 = The un-synchronized input signal will be inverted.
+     * |        |          |Note: In SPI protocol, it is suggested this bit should be set as 0.
+     * @var USPI_T::CTLIN0
+     * Offset: 0x20  USCI Input Control Signal Configuration Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SYNCSEL   |Input Synchronization Signal Selection
+     * |        |          |This bit selects if the un-synchronized input signal (with optionally inverted) or the   synchronized (and optionally filtered) signal can be used as input for the   data shift unit.
+     * |        |          |0 = The un-synchronized signal can be taken as input for the data shift unit.
+     * |        |          |1 = The synchronized signal can be taken as input for the data shift unit.
+     * |        |          |Note: In SPI protocol, it is suggested this bit should be set as 0.
+     * |[2]     |ININV     |Input Signal Inverse Selection
+     * |        |          |This bit defines the inverter enable of the input asynchronous signal.
+     * |        |          |0 = The un-synchronized input signal will not be inverted.
+     * |        |          |1 = The un-synchronized input signal will be inverted.
+     * @var USPI_T::CLKIN
+     * Offset: 0x28  USCI Input Clock Signal Configuration Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SYNCSEL   |Input Synchronization Signal Selection
+     * |        |          |This bit selects if the un-synchronized input signal or the synchronized (and   optionally filtered) signal can be used as input for the data shift unit.
+     * |        |          |0 = The un-synchronized signal can be taken as input for the data shift unit.
+     * |        |          |1 = The synchronized signal can be taken as input for the data shift unit.
+     * |        |          |Note: In SPI protocol, it is suggested this bit should be set as 0.
+     * @var USPI_T::LINECTL
+     * Offset: 0x2C  USCI Line Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |LSB       |LSB First Transmission Selection
+     * |        |          |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first.
+     * |        |          |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first.
+     * |[5]     |DATOINV   |Data Output Inverse Selection
+     * |        |          |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin.
+     * |        |          |0 = Data output level is not inverted.
+     * |        |          |1 = Data output level is inverted.
+     * |[7]     |CTLOINV   |Control Signal Output Inverse Selection
+     * |        |          |This bit defines the relation between the internal control signal and the output control signal.
+     * |        |          |0 = No effect.
+     * |        |          |1 = The control signal will be inverted before its output.
+     * |        |          |Note: The control signal has different definitions in different protocol
+     * |        |          |In SPI protocol, the control signal means slave select signal
+     * |[11:8]  |DWIDTH    |Word Length of Transmission
+     * |        |          |This bit field defines the data word length (amount of bits) for reception and transmission
+     * |        |          |The data word is always right-aligned in the data buffer
+     * |        |          |USCI support word length from 4 to 16 bits.
+     * |        |          |0x0: The data word contains 16 bits located at bit positions [15:0].
+     * |        |          |0x1: Reserved.
+     * |        |          |0x2: Reserved.
+     * |        |          |0x3: Reserved.
+     * |        |          |0x4: The data word contains 4 bits located at bit positions [3:0].
+     * |        |          |0x5: The data word contains 5 bits located at bit positions [4:0].
+     * |        |          |...
+     * |        |          |0xF: The data word contains 15 bits located at bit positions [14:0].
+     * @var USPI_T::TXDAT
+     * Offset: 0x30  USCI Transmit Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |TXDAT     |Transmit Data
+     * |        |          |Software can use this bit field to write 16-bit transmit data for transmission
+     * |        |          |In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field.
+     * |[16]    |PORTDIR   |Port Direction Control
+     * |        |          |This bit field is only available while USCI operates in SPI protocol (FUNMODE = 0x1) with half-duplex transfer
+     * |        |          |It is used to define the direction of the data port pin
+     * |        |          |When software writes USPI_TXDAT register, the transmit data and its port direction are settled simultaneously.
+     * |        |          |0 = The data pin is configured as output mode.
+     * |        |          |1 = The data pin is configured as input mode.
+     * @var USPI_T::RXDAT
+     * Offset: 0x34  USCI Receive Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |RXDAT     |Received Data
+     * |        |          |This bit field monitors the received data which stored in receive data buffer.
+     * @var USPI_T::BUFCTL
+     * Offset: 0x38  USCI Transmit/Receive Buffer Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[6]     |TXUDRIEN  |Slave Transmit Under-run Interrupt Enable Bit
+     * |        |          |0 = Transmit under-run interrupt Disabled.
+     * |        |          |1 = Transmit under-run interrupt Enabled.
+     * |[7]     |TXCLR     |Clear Transmit Buffer
+     * |        |          |0 = No effect.
+     * |        |          |1 = The transmit buffer is cleared
+     * |        |          |Should only be used while the buffer is not taking part in data traffic.
+     * |        |          |Note: It is cleared automatically after one PCLK cycle.
+     * |[14]    |RXOVIEN   |Receive Buffer Overrun Interrupt Enable Bit
+     * |        |          |0 = Receive overrun interrupt Disabled.
+     * |        |          |1 = Receive overrun interrupt Enabled.
+     * |[15]    |RXCLR     |Clear Receive Buffer
+     * |        |          |0 = No effect.
+     * |        |          |1 = The receive buffer is cleared
+     * |        |          |Should only be used while the buffer is not taking part in data traffic.
+     * |        |          |Note: It is cleared automatically after one PCLK cycle.
+     * |[16]    |TXRST     |Transmit Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer.
+     * |        |          |Note 1: It is cleared automatically after one PCLK cycle.
+     * |        |          |Note 2: Write 1 to this bit will set the output data pin to zero if USPI_PROTCTL[28]=0.
+     * |[17]    |RXRST     |Receive Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer.
+     * |        |          |Note: It is cleared automatically after one PCLK cycle.
+     * @var USPI_T::BUFSTS
+     * Offset: 0x3C  USCI Transmit/Receive Buffer Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RXEMPTY   |Receive Buffer Empty Indicator (Read Only)
+     * |        |          |0 = Receive buffer is not empty.
+     * |        |          |1 = Receive buffer is empty.
+     * |[1]     |RXFULL    |Receive Buffer Full Indicator (Read Only)
+     * |        |          |0 = Receive buffer is not full.
+     * |        |          |1 = Receive buffer is full.
+     * |[3]     |RXOVIF    |Receive Buffer Overrun Interrupt Status
+     * |        |          |This bit indicates that a receive buffer overrun event has been detected
+     * |        |          |If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated
+     * |        |          |It is cleared by software writes 1 to this bit.
+     * |        |          |0 = A receive buffer overrun event has not been detected.
+     * |        |          |1 = A receive buffer overrun event has been detected.
+     * |[8]     |TXEMPTY   |Transmit Buffer Empty Indicator (Read Only)
+     * |        |          |0 = Transmit buffer is not empty.
+     * |        |          |1 = Transmit buffer is empty and available for the next transmission datum.
+     * |[9]     |TXFULL    |Transmit Buffer Full Indicator (Read Only)
+     * |        |          |0 = Transmit buffer is not full.
+     * |        |          |1 = Transmit buffer is full.
+     * |[11]    |TXUDRIF   |Transmit Buffer Under-run Interrupt Status
+     * |        |          |This bit indicates that a transmit buffer under-run event has been detected
+     * |        |          |If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated
+     * |        |          |It is cleared by software writes 1 to this bit
+     * |        |          |0 = A transmit buffer under-run event has not been detected.
+     * |        |          |1 = A transmit buffer under-run event has been detected.
+     * @var USPI_T::PDMACTL
+     * Offset: 0x40  USCI PDMA Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PDMARST   |PDMA Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically.
+     * |[1]     |TXPDMAEN  |PDMA Transmit Channel Available
+     * |        |          |0 = Transmit PDMA function Disabled.
+     * |        |          |1 = Transmit PDMA function Enabled.
+     * |[2]     |RXPDMAEN  |PDMA Receive Channel Available
+     * |        |          |0 = Receive PDMA function Disabled.
+     * |        |          |1 = Receive PDMA function Enabled.
+     * |[3]     |PDMAEN    |PDMA Mode Enable Bit
+     * |        |          |0 = PDMA function Disabled.
+     * |        |          |1 = PDMA function Enabled.
+     * |        |          |Note: The I2C is not supporting PDMA function.
+     * @var USPI_T::WKCTL
+     * Offset: 0x54  USCI Wake-up Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WKEN      |Wake-up Enable Bit
+     * |        |          |0 = Wake-up function Disabled.
+     * |        |          |1 = Wake-up function Enabled.
+     * |[1]     |WKADDREN  |Wake-up Address Match Enable Bit
+     * |        |          |0 = The chip is woken up according data toggle.
+     * |        |          |1 = The chip is woken up according address match.
+     * |[2]     |PDBOPT    |Power Down Blocking Option
+     * |        |          |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately.
+     * |        |          |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately.
+     * @var USPI_T::WKSTS
+     * Offset: 0x58  USCI Wake-up Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WKF       |Wake-up Flag
+     * |        |          |When chip is woken up from Power-down mode, this bit is set to 1
+     * |        |          |Software can write 1 to clear this bit.
+     * @var USPI_T::PROTCTL
+     * Offset: 0x5C  USCI Protocol Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SLAVE     |Slave Mode Selection
+     * |        |          |0 = Master mode.
+     * |        |          |1 = Slave mode.
+     * |[1]     |SLV3WIRE  |Slave 3-wire Mode Selection (Slave Only)
+     * |        |          |The SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode.
+     * |        |          |0 = 4-wire bi-direction interface.
+     * |        |          |1 = 3-wire bi-direction interface.
+     * |[2]     |SS        |Slave Select Control (Master Only)
+     * |        |          |If AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select signal back to inactive state.
+     * |        |          |If the AUTOSS function is enabled (AUTOSS = 1), the setting value of this bit will not affect the current state of slave select signal.
+     * |        |          |Note: In SPI protocol, the internal slave select signal is active high.
+     * |[3]     |AUTOSS    |Automatic Slave Select Function Enable (Master Only)
+     * |        |          |0 = Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit.
+     * |        |          |1 = Slave select signal will be generated automatically
+     * |        |          |The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished.
+     * |[7:6]   |SCLKMODE  |Serial Bus Clock Mode
+     * |        |          |This bit field defines the SCLK idle status, data transmit, and data receive edge.
+     * |        |          |00 = MODE0. The idle state of SPI clock is low level.
+     * |        |          |Data is transmitted with falling edge and received with rising edge.
+     * |        |          |01 = MODE1. The idle state of SPI clock is low level.
+     * |        |          |Data is transmitted with rising edge and received with falling edge.
+     * |        |          |10 = MODE2. The idle state of SPI clock is high level.
+     * |        |          |Data is transmitted with rising edge and received with falling edge.
+     * |        |          |11 = MODE3. The idle state of SPI clock is high level.
+     * |        |          |Data is transmitted with falling edge and received with rising edge.
+     * |[11:8]  |SUSPITV   |Suspend Interval (Master Only)
+     * |        |          |This bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer
+     * |        |          |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word
+     * |        |          |The default value is 0x3
+     * |        |          |The period of the suspend interval is obtained according to the following equation.
+     * |        |          |(SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle
+     * |        |          |Example:
+     * |        |          |SUSPITV = 0x0 ... 0.5 SPI_CLK clock cycle.
+     * |        |          |SUSPITV = 0x1 ... 1.5 SPI_CLK clock cycle.
+     * |        |          |.....
+     * |        |          |SUSPITV = 0xE ... 14.5 SPI_CLK clock cycle.
+     * |        |          |SUSPITV = 0xF ... 15.5 SPI_CLK clock cycle.
+     * |[14:12] |TSMSEL    |Transmit Data Mode Selection
+     * |        |          |This bit field describes how receive and transmit data is shifted in and out.
+     * |        |          |TSMSEL = 000b: Full-duplex SPI.
+     * |        |          |TSMSEL = 100b: Half-duplex SPI.
+     * |        |          |Others = Reserved.
+     * |        |          |Note: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically.
+     * |[25:16] |SLVTOCNT  |Slave Mode Time-out Period (Slave Only)
+     * |        |          |In Slave mode, this bit field is used for Slave time-out period
+     * |        |          |This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event
+     * |        |          |Writing 0x0 into this bit field will disable the Slave time-out function.
+     * |        |          |Example: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK.
+     * |[28]    |TXUDRPOL  |Transmit Under-run Data Polarity (Slave Only)
+     * |        |          |This bit defines the transmitting data level when no data is available for transferring.
+     * |        |          |0 = The output data level is 0 if TX under-run event occurs.
+     * |        |          |1 = The output data level is 1 if TX under-run event occurs.
+     * |[31]    |PROTEN    |SPI Protocol Enable Bit
+     * |        |          |0 = SPI Protocol Disabled.
+     * |        |          |1 = SPI Protocol Enabled.
+     * @var USPI_T::PROTIEN
+     * Offset: 0x60  USCI Protocol Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SSINAIEN  |Slave Select Inactive Interrupt Enable Bit
+     * |        |          |This bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive.
+     * |        |          |0 = Slave select inactive interrupt generation Disabled.
+     * |        |          |1 = Slave select inactive interrupt generation Enabled.
+     * |[1]     |SSACTIEN  |Slave Select Active Interrupt Enable Bit
+     * |        |          |This bit enables/disables the generation of a slave select interrupt if the slave select changes to active.
+     * |        |          |0 = Slave select active interrupt generation Disabled.
+     * |        |          |1 = Slave select active interrupt generation Enabled.
+     * |[2]     |SLVTOIEN  |Slave Time-out Interrupt Enable Bit
+     * |        |          |In SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event.
+     * |        |          |0 = The Slave time-out interrupt Disabled.
+     * |        |          |1 = The Slave time-out interrupt Enabled.
+     * |[3]     |SLVBEIEN  |Slave Mode Bit Count Error Interrupt Enable Bit
+     * |        |          |If data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8])
+     * |        |          |Bit count error event occurs.
+     * |        |          |0 = The Slave mode bit count error interrupt Disabled.
+     * |        |          |1 = The Slave mode bit count error interrupt Enabled.
+     * @var USPI_T::PROTSTS
+     * Offset: 0x64  USCI Protocol Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1]     |TXSTIF    |Transmit Start Interrupt Flag
+     * |        |          |0 = Transmit start event did not occur.
+     * |        |          |1 = Transmit start event occurred.
+     * |        |          |Note: It is cleared by software write 1 to this bit
+     * |[2]     |TXENDIF   |Transmit End Interrupt Flag
+     * |        |          |0 = Transmit end event did not occur.
+     * |        |          |1 = Transmit end event occurred.
+     * |        |          |Note: It is cleared by software write 1 to this bit
+     * |[3]     |RXSTIF    |Receive Start Interrupt Flag
+     * |        |          |0 = Receive start event did not occur.
+     * |        |          |1 = Receive start event occurred.
+     * |        |          |Note: It is cleared by software write 1 to this bit
+     * |[4]     |RXENDIF   |Receive End Interrupt Flag
+     * |        |          |0 = Receive end event did not occur.
+     * |        |          |1 = Receive end event occurred.
+     * |        |          |Note: It is cleared by software write 1 to this bit
+     * |[5]     |SLVTOIF   |Slave Time-out Interrupt Flag (Slave Only)
+     * |        |          |0 = Slave time-out event did not occur.
+     * |        |          |1 = Slave time-out event occurred.
+     * |        |          |Note: It is cleared by software write 1 to this bit
+     * |[6]     |SLVBEIF   |Slave Bit Count Error Interrupt Flag (Slave Only)
+     * |        |          |0 = Slave bit count error event did not occur.
+     * |        |          |1 = Slave bit count error event occurred.
+     * |        |          |Note: It is cleared by software write 1 to this bit.
+     * |[8]     |SSINAIF   |Slave Select Inactive Interrupt Flag (Slave Only)
+     * |        |          |This bit indicates that the internal slave select signal has changed to inactive
+     * |        |          |It is cleared by software writes 1 to this bit
+     * |        |          |0 = The slave select signal has not changed to inactive.
+     * |        |          |1 = The slave select signal has changed to inactive.
+     * |        |          |Note: The internal slave select signal is active high.
+     * |[9]     |SSACTIF   |Slave Select Active Interrupt Flag (Slave Only)
+     * |        |          |This bit indicates that the internal slave select signal has changed to active
+     * |        |          |It is cleared by software writes one to this bit
+     * |        |          |0 = The slave select signal has not changed to active.
+     * |        |          |1 = The slave select signal has changed to active.
+     * |        |          |Note: The internal slave select signal is active high.
+     * |[16]    |SSLINE    |Slave Select Line Bus Status (Read Only)
+     * |        |          |This bit is only available in Slave mode
+     * |        |          |It used to monitor the current status of the input slave select signal on the bus.
+     * |        |          |0 = The slave select line status is 0.
+     * |        |          |1 = The slave select line status is 1.
+     * |[17]    |BUSY      |Busy Status (Read Only)
+     * |        |          |0 = SPI is in idle state.
+     * |        |          |1 = SPI is in busy state.
+     * |        |          |The following listing are the bus busy conditions:
+     * |        |          |a. USPI_PROTCTL[31] = 1 and the TXEMPTY = 0.
+     * |        |          |b. For SPI Master mode, the TXEMPTY = 1 but the current transaction is not finished yet.
+     * |        |          |c. For SPI Slave mode, the USPI_PROTCTL[31] = 1 and there is serial clock input into the SPI core logic when slave select is active.
+     * |        |          |d. For SPI Slave mode, the USPI_PROTCTL[31] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
+     * |[18]    |SLVUDR    |Slave Mode Transmit Under-run Status (Read Only)
+     * |        |          |In Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1
+     * |        |          |This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not.
+     * |        |          |0 = Slave transmit under-run event did not occur.
+     * |        |          |1 = Slave transmit under-run event occurred.
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] USCI Control Register                                            */
+    __IO uint32_t INTEN;                 /*!< [0x0004] USCI Interrupt Enable Register                                   */
+    __IO uint32_t BRGEN;                 /*!< [0x0008] USCI Baud Rate Generator Register                                */
+    __I  uint32_t RESERVE0[1];
+    __IO uint32_t DATIN0;                /*!< [0x0010] USCI Input Data Signal Configuration Register 0                  */
+    __I  uint32_t RESERVE1[3];
+    __IO uint32_t CTLIN0;                /*!< [0x0020] USCI Input Control Signal Configuration Register 0               */
+    __I  uint32_t RESERVE2[1];
+    __IO uint32_t CLKIN;                 /*!< [0x0028] USCI Input Clock Signal Configuration Register                   */
+    __IO uint32_t LINECTL;               /*!< [0x002c] USCI Line Control Register                                       */
+    __O  uint32_t TXDAT;                 /*!< [0x0030] USCI Transmit Data Register                                      */
+    __I  uint32_t RXDAT;                 /*!< [0x0034] USCI Receive Data Register                                       */
+    __IO uint32_t BUFCTL;                /*!< [0x0038] USCI Transmit/Receive Buffer Control Register                    */
+    __IO uint32_t BUFSTS;                /*!< [0x003c] USCI Transmit/Receive Buffer Status Register                     */
+    __IO uint32_t PDMACTL;               /*!< [0x0040] USCI PDMA Control Register                                       */
+    __I  uint32_t RESERVE3[4];
+    __IO uint32_t WKCTL;                 /*!< [0x0054] USCI Wake-up Control Register                                    */
+    __IO uint32_t WKSTS;                 /*!< [0x0058] USCI Wake-up Status Register                                     */
+    __IO uint32_t PROTCTL;               /*!< [0x005c] USCI Protocol Control Register                                   */
+    __IO uint32_t PROTIEN;               /*!< [0x0060] USCI Protocol Interrupt Enable Register                          */
+    __IO uint32_t PROTSTS;               /*!< [0x0064] USCI Protocol Status Register                                    */
+
+} USPI_T;
+
+/**
+    @addtogroup USPI_CONST USPI Bit Field Definition
+    Constant Definitions for USPI Controller
+  @{
+*/
+
+#define USPI_CTL_FUNMODE_Pos             (0)                                               /*!< USPI_T::CTL: FUNMODE Position          */
+#define USPI_CTL_FUNMODE_Msk             (0x7ul << USPI_CTL_FUNMODE_Pos)                   /*!< USPI_T::CTL: FUNMODE Mask              */
+
+#define USPI_INTEN_TXSTIEN_Pos           (1)                                               /*!< USPI_T::INTEN: TXSTIEN Position        */
+#define USPI_INTEN_TXSTIEN_Msk           (0x1ul << USPI_INTEN_TXSTIEN_Pos)                 /*!< USPI_T::INTEN: TXSTIEN Mask            */
+
+#define USPI_INTEN_TXENDIEN_Pos          (2)                                               /*!< USPI_T::INTEN: TXENDIEN Position       */
+#define USPI_INTEN_TXENDIEN_Msk          (0x1ul << USPI_INTEN_TXENDIEN_Pos)                /*!< USPI_T::INTEN: TXENDIEN Mask           */
+
+#define USPI_INTEN_RXSTIEN_Pos           (3)                                               /*!< USPI_T::INTEN: RXSTIEN Position        */
+#define USPI_INTEN_RXSTIEN_Msk           (0x1ul << USPI_INTEN_RXSTIEN_Pos)                 /*!< USPI_T::INTEN: RXSTIEN Mask            */
+
+#define USPI_INTEN_RXENDIEN_Pos          (4)                                               /*!< USPI_T::INTEN: RXENDIEN Position       */
+#define USPI_INTEN_RXENDIEN_Msk          (0x1ul << USPI_INTEN_RXENDIEN_Pos)                /*!< USPI_T::INTEN: RXENDIEN Mask           */
+
+#define USPI_BRGEN_RCLKSEL_Pos           (0)                                               /*!< USPI_T::BRGEN: RCLKSEL Position        */
+#define USPI_BRGEN_RCLKSEL_Msk           (0x1ul << USPI_BRGEN_RCLKSEL_Pos)                 /*!< USPI_T::BRGEN: RCLKSEL Mask            */
+
+#define USPI_BRGEN_PTCLKSEL_Pos          (1)                                               /*!< USPI_T::BRGEN: PTCLKSEL Position       */
+#define USPI_BRGEN_PTCLKSEL_Msk          (0x1ul << USPI_BRGEN_PTCLKSEL_Pos)                /*!< USPI_T::BRGEN: PTCLKSEL Mask           */
+
+#define USPI_BRGEN_SPCLKSEL_Pos          (2)                                               /*!< USPI_T::BRGEN: SPCLKSEL Position       */
+#define USPI_BRGEN_SPCLKSEL_Msk          (0x3ul << USPI_BRGEN_SPCLKSEL_Pos)                /*!< USPI_T::BRGEN: SPCLKSEL Mask           */
+
+#define USPI_BRGEN_TMCNTEN_Pos           (4)                                               /*!< USPI_T::BRGEN: TMCNTEN Position        */
+#define USPI_BRGEN_TMCNTEN_Msk           (0x1ul << USPI_BRGEN_TMCNTEN_Pos)                 /*!< USPI_T::BRGEN: TMCNTEN Mask            */
+
+#define USPI_BRGEN_TMCNTSRC_Pos          (5)                                               /*!< USPI_T::BRGEN: TMCNTSRC Position       */
+#define USPI_BRGEN_TMCNTSRC_Msk          (0x1ul << USPI_BRGEN_TMCNTSRC_Pos)                /*!< USPI_T::BRGEN: TMCNTSRC Mask           */
+
+#define USPI_BRGEN_CLKDIV_Pos            (16)                                              /*!< USPI_T::BRGEN: CLKDIV Position         */
+#define USPI_BRGEN_CLKDIV_Msk            (0x3fful << USPI_BRGEN_CLKDIV_Pos)                /*!< USPI_T::BRGEN: CLKDIV Mask             */
+
+#define USPI_DATIN0_SYNCSEL_Pos          (0)                                               /*!< USPI_T::DATIN0: SYNCSEL Position       */
+#define USPI_DATIN0_SYNCSEL_Msk          (0x1ul << USPI_DATIN0_SYNCSEL_Pos)                /*!< USPI_T::DATIN0: SYNCSEL Mask           */
+
+#define USPI_DATIN0_ININV_Pos            (2)                                               /*!< USPI_T::DATIN0: ININV Position         */
+#define USPI_DATIN0_ININV_Msk            (0x1ul << USPI_DATIN0_ININV_Pos)                  /*!< USPI_T::DATIN0: ININV Mask             */
+
+#define USPI_CTLIN0_SYNCSEL_Pos          (0)                                               /*!< USPI_T::CTLIN0: SYNCSEL Position       */
+#define USPI_CTLIN0_SYNCSEL_Msk          (0x1ul << USPI_CTLIN0_SYNCSEL_Pos)                /*!< USPI_T::CTLIN0: SYNCSEL Mask           */
+
+#define USPI_CTLIN0_ININV_Pos            (2)                                               /*!< USPI_T::CTLIN0: ININV Position         */
+#define USPI_CTLIN0_ININV_Msk            (0x1ul << USPI_CTLIN0_ININV_Pos)                  /*!< USPI_T::CTLIN0: ININV Mask             */
+
+#define USPI_CLKIN_SYNCSEL_Pos           (0)                                               /*!< USPI_T::CLKIN: SYNCSEL Position        */
+#define USPI_CLKIN_SYNCSEL_Msk           (0x1ul << USPI_CLKIN_SYNCSEL_Pos)                 /*!< USPI_T::CLKIN: SYNCSEL Mask            */
+
+#define USPI_LINECTL_LSB_Pos             (0)                                               /*!< USPI_T::LINECTL: LSB Position          */
+#define USPI_LINECTL_LSB_Msk             (0x1ul << USPI_LINECTL_LSB_Pos)                   /*!< USPI_T::LINECTL: LSB Mask              */
+
+#define USPI_LINECTL_DATOINV_Pos         (5)                                               /*!< USPI_T::LINECTL: DATOINV Position      */
+#define USPI_LINECTL_DATOINV_Msk         (0x1ul << USPI_LINECTL_DATOINV_Pos)               /*!< USPI_T::LINECTL: DATOINV Mask          */
+
+#define USPI_LINECTL_CTLOINV_Pos         (7)                                               /*!< USPI_T::LINECTL: CTLOINV Position      */
+#define USPI_LINECTL_CTLOINV_Msk         (0x1ul << USPI_LINECTL_CTLOINV_Pos)               /*!< USPI_T::LINECTL: CTLOINV Mask          */
+
+#define USPI_LINECTL_DWIDTH_Pos          (8)                                               /*!< USPI_T::LINECTL: DWIDTH Position       */
+#define USPI_LINECTL_DWIDTH_Msk          (0xful << USPI_LINECTL_DWIDTH_Pos)                /*!< USPI_T::LINECTL: DWIDTH Mask           */
+
+#define USPI_TXDAT_TXDAT_Pos             (0)                                               /*!< USPI_T::TXDAT: TXDAT Position          */
+#define USPI_TXDAT_TXDAT_Msk             (0xfffful << USPI_TXDAT_TXDAT_Pos)                /*!< USPI_T::TXDAT: TXDAT Mask              */
+
+#define USPI_TXDAT_PORTDIR_Pos           (16)                                              /*!< USPI_T::TXDAT: PORTDIR Position        */
+#define USPI_TXDAT_PORTDIR_Msk           (0x1ul << USPI_TXDAT_PORTDIR_Pos)                 /*!< USPI_T::TXDAT: PORTDIR Mask            */
+
+#define USPI_RXDAT_RXDAT_Pos             (0)                                               /*!< USPI_T::RXDAT: RXDAT Position          */
+#define USPI_RXDAT_RXDAT_Msk             (0xfffful << USPI_RXDAT_RXDAT_Pos)                /*!< USPI_T::RXDAT: RXDAT Mask              */
+
+#define USPI_BUFCTL_TXUDRIEN_Pos         (6)                                               /*!< USPI_T::BUFCTL: TXUDRIEN Position      */
+#define USPI_BUFCTL_TXUDRIEN_Msk         (0x1ul << USPI_BUFCTL_TXUDRIEN_Pos)               /*!< USPI_T::BUFCTL: TXUDRIEN Mask          */
+
+#define USPI_BUFCTL_TXCLR_Pos            (7)                                               /*!< USPI_T::BUFCTL: TXCLR Position         */
+#define USPI_BUFCTL_TXCLR_Msk            (0x1ul << USPI_BUFCTL_TXCLR_Pos)                  /*!< USPI_T::BUFCTL: TXCLR Mask             */
+
+#define USPI_BUFCTL_RXOVIEN_Pos          (14)                                              /*!< USPI_T::BUFCTL: RXOVIEN Position       */
+#define USPI_BUFCTL_RXOVIEN_Msk          (0x1ul << USPI_BUFCTL_RXOVIEN_Pos)                /*!< USPI_T::BUFCTL: RXOVIEN Mask           */
+
+#define USPI_BUFCTL_RXCLR_Pos            (15)                                              /*!< USPI_T::BUFCTL: RXCLR Position         */
+#define USPI_BUFCTL_RXCLR_Msk            (0x1ul << USPI_BUFCTL_RXCLR_Pos)                  /*!< USPI_T::BUFCTL: RXCLR Mask             */
+
+#define USPI_BUFCTL_TXRST_Pos            (16)                                              /*!< USPI_T::BUFCTL: TXRST Position         */
+#define USPI_BUFCTL_TXRST_Msk            (0x1ul << USPI_BUFCTL_TXRST_Pos)                  /*!< USPI_T::BUFCTL: TXRST Mask             */
+
+#define USPI_BUFCTL_RXRST_Pos            (17)                                              /*!< USPI_T::BUFCTL: RXRST Position         */
+#define USPI_BUFCTL_RXRST_Msk            (0x1ul << USPI_BUFCTL_RXRST_Pos)                  /*!< USPI_T::BUFCTL: RXRST Mask             */
+
+#define USPI_BUFSTS_RXEMPTY_Pos          (0)                                               /*!< USPI_T::BUFSTS: RXEMPTY Position       */
+#define USPI_BUFSTS_RXEMPTY_Msk          (0x1ul << USPI_BUFSTS_RXEMPTY_Pos)                /*!< USPI_T::BUFSTS: RXEMPTY Mask           */
+
+#define USPI_BUFSTS_RXFULL_Pos           (1)                                               /*!< USPI_T::BUFSTS: RXFULL Position        */
+#define USPI_BUFSTS_RXFULL_Msk           (0x1ul << USPI_BUFSTS_RXFULL_Pos)                 /*!< USPI_T::BUFSTS: RXFULL Mask            */
+
+#define USPI_BUFSTS_RXOVIF_Pos           (3)                                               /*!< USPI_T::BUFSTS: RXOVIF Position        */
+#define USPI_BUFSTS_RXOVIF_Msk           (0x1ul << USPI_BUFSTS_RXOVIF_Pos)                 /*!< USPI_T::BUFSTS: RXOVIF Mask            */
+
+#define USPI_BUFSTS_TXEMPTY_Pos          (8)                                               /*!< USPI_T::BUFSTS: TXEMPTY Position       */
+#define USPI_BUFSTS_TXEMPTY_Msk          (0x1ul << USPI_BUFSTS_TXEMPTY_Pos)                /*!< USPI_T::BUFSTS: TXEMPTY Mask           */
+
+#define USPI_BUFSTS_TXFULL_Pos           (9)                                               /*!< USPI_T::BUFSTS: TXFULL Position        */
+#define USPI_BUFSTS_TXFULL_Msk           (0x1ul << USPI_BUFSTS_TXFULL_Pos)                 /*!< USPI_T::BUFSTS: TXFULL Mask            */
+
+#define USPI_BUFSTS_TXUDRIF_Pos          (11)                                              /*!< USPI_T::BUFSTS: TXUDRIF Position       */
+#define USPI_BUFSTS_TXUDRIF_Msk          (0x1ul << USPI_BUFSTS_TXUDRIF_Pos)                /*!< USPI_T::BUFSTS: TXUDRIF Mask           */
+
+#define USPI_PDMACTL_PDMARST_Pos         (0)                                               /*!< USPI_T::PDMACTL: PDMARST Position      */
+#define USPI_PDMACTL_PDMARST_Msk         (0x1ul << USPI_PDMACTL_PDMARST_Pos)               /*!< USPI_T::PDMACTL: PDMARST Mask          */
+
+#define USPI_PDMACTL_TXPDMAEN_Pos        (1)                                               /*!< USPI_T::PDMACTL: TXPDMAEN Position     */
+#define USPI_PDMACTL_TXPDMAEN_Msk        (0x1ul << USPI_PDMACTL_TXPDMAEN_Pos)              /*!< USPI_T::PDMACTL: TXPDMAEN Mask         */
+
+#define USPI_PDMACTL_RXPDMAEN_Pos        (2)                                               /*!< USPI_T::PDMACTL: RXPDMAEN Position     */
+#define USPI_PDMACTL_RXPDMAEN_Msk        (0x1ul << USPI_PDMACTL_RXPDMAEN_Pos)              /*!< USPI_T::PDMACTL: RXPDMAEN Mask         */
+
+#define USPI_PDMACTL_PDMAEN_Pos          (3)                                               /*!< USPI_T::PDMACTL: PDMAEN Position       */
+#define USPI_PDMACTL_PDMAEN_Msk          (0x1ul << USPI_PDMACTL_PDMAEN_Pos)                /*!< USPI_T::PDMACTL: PDMAEN Mask           */
+
+#define USPI_WKCTL_WKEN_Pos              (0)                                               /*!< USPI_T::WKCTL: WKEN Position           */
+#define USPI_WKCTL_WKEN_Msk              (0x1ul << USPI_WKCTL_WKEN_Pos)                    /*!< USPI_T::WKCTL: WKEN Mask               */
+
+#define USPI_WKCTL_WKADDREN_Pos          (1)                                               /*!< USPI_T::WKCTL: WKADDREN Position       */
+#define USPI_WKCTL_WKADDREN_Msk          (0x1ul << USPI_WKCTL_WKADDREN_Pos)                /*!< USPI_T::WKCTL: WKADDREN Mask           */
+
+#define USPI_WKCTL_PDBOPT_Pos            (2)                                               /*!< USPI_T::WKCTL: PDBOPT Position         */
+#define USPI_WKCTL_PDBOPT_Msk            (0x1ul << USPI_WKCTL_PDBOPT_Pos)                  /*!< USPI_T::WKCTL: PDBOPT Mask             */
+
+#define USPI_WKSTS_WKF_Pos               (0)                                               /*!< USPI_T::WKSTS: WKF Position            */
+#define USPI_WKSTS_WKF_Msk               (0x1ul << USPI_WKSTS_WKF_Pos)                     /*!< USPI_T::WKSTS: WKF Mask                */
+
+#define USPI_PROTCTL_SLAVE_Pos           (0)                                               /*!< USPI_T::PROTCTL: SLAVE Position        */
+#define USPI_PROTCTL_SLAVE_Msk           (0x1ul << USPI_PROTCTL_SLAVE_Pos)                 /*!< USPI_T::PROTCTL: SLAVE Mask            */
+
+#define USPI_PROTCTL_SLV3WIRE_Pos        (1)                                               /*!< USPI_T::PROTCTL: SLV3WIRE Position     */
+#define USPI_PROTCTL_SLV3WIRE_Msk        (0x1ul << USPI_PROTCTL_SLV3WIRE_Pos)              /*!< USPI_T::PROTCTL: SLV3WIRE Mask         */
+
+#define USPI_PROTCTL_SS_Pos              (2)                                               /*!< USPI_T::PROTCTL: SS Position           */
+#define USPI_PROTCTL_SS_Msk              (0x1ul << USPI_PROTCTL_SS_Pos)                    /*!< USPI_T::PROTCTL: SS Mask               */
+
+#define USPI_PROTCTL_AUTOSS_Pos          (3)                                               /*!< USPI_T::PROTCTL: AUTOSS Position       */
+#define USPI_PROTCTL_AUTOSS_Msk          (0x1ul << USPI_PROTCTL_AUTOSS_Pos)                /*!< USPI_T::PROTCTL: AUTOSS Mask           */
+
+#define USPI_PROTCTL_SCLKMODE_Pos        (6)                                               /*!< USPI_T::PROTCTL: SCLKMODE Position     */
+#define USPI_PROTCTL_SCLKMODE_Msk        (0x3ul << USPI_PROTCTL_SCLKMODE_Pos)              /*!< USPI_T::PROTCTL: SCLKMODE Mask         */
+
+#define USPI_PROTCTL_SUSPITV_Pos         (8)                                               /*!< USPI_T::PROTCTL: SUSPITV Position      */
+#define USPI_PROTCTL_SUSPITV_Msk         (0xful << USPI_PROTCTL_SUSPITV_Pos)               /*!< USPI_T::PROTCTL: SUSPITV Mask          */
+
+#define USPI_PROTCTL_TSMSEL_Pos          (12)                                              /*!< USPI_T::PROTCTL: TSMSEL Position       */
+#define USPI_PROTCTL_TSMSEL_Msk          (0x7ul << USPI_PROTCTL_TSMSEL_Pos)                /*!< USPI_T::PROTCTL: TSMSEL Mask           */
+
+#define USPI_PROTCTL_SLVTOCNT_Pos        (16)                                              /*!< USPI_T::PROTCTL: SLVTOCNT Position     */
+#define USPI_PROTCTL_SLVTOCNT_Msk        (0x3fful << USPI_PROTCTL_SLVTOCNT_Pos)            /*!< USPI_T::PROTCTL: SLVTOCNT Mask         */
+
+#define USPI_PROTCTL_TXUDRPOL_Pos        (28)                                              /*!< USPI_T::PROTCTL: TXUDRPOL Position     */
+#define USPI_PROTCTL_TXUDRPOL_Msk        (0x1ul << USPI_PROTCTL_TXUDRPOL_Pos)              /*!< USPI_T::PROTCTL: TXUDRPOL Mask         */
+
+#define USPI_PROTCTL_PROTEN_Pos          (31)                                              /*!< USPI_T::PROTCTL: PROTEN Position       */
+#define USPI_PROTCTL_PROTEN_Msk          (0x1ul << USPI_PROTCTL_PROTEN_Pos)                /*!< USPI_T::PROTCTL: PROTEN Mask           */
+
+#define USPI_PROTIEN_SSINAIEN_Pos        (0)                                               /*!< USPI_T::PROTIEN: SSINAIEN Position     */
+#define USPI_PROTIEN_SSINAIEN_Msk        (0x1ul << USPI_PROTIEN_SSINAIEN_Pos)              /*!< USPI_T::PROTIEN: SSINAIEN Mask         */
+
+#define USPI_PROTIEN_SSACTIEN_Pos        (1)                                               /*!< USPI_T::PROTIEN: SSACTIEN Position     */
+#define USPI_PROTIEN_SSACTIEN_Msk        (0x1ul << USPI_PROTIEN_SSACTIEN_Pos)              /*!< USPI_T::PROTIEN: SSACTIEN Mask         */
+
+#define USPI_PROTIEN_SLVTOIEN_Pos        (2)                                               /*!< USPI_T::PROTIEN: SLVTOIEN Position     */
+#define USPI_PROTIEN_SLVTOIEN_Msk        (0x1ul << USPI_PROTIEN_SLVTOIEN_Pos)              /*!< USPI_T::PROTIEN: SLVTOIEN Mask         */
+
+#define USPI_PROTIEN_SLVBEIEN_Pos        (3)                                               /*!< USPI_T::PROTIEN: SLVBEIEN Position     */
+#define USPI_PROTIEN_SLVBEIEN_Msk        (0x1ul << USPI_PROTIEN_SLVBEIEN_Pos)              /*!< USPI_T::PROTIEN: SLVBEIEN Mask         */
+
+#define USPI_PROTSTS_TXSTIF_Pos          (1)                                               /*!< USPI_T::PROTSTS: TXSTIF Position       */
+#define USPI_PROTSTS_TXSTIF_Msk          (0x1ul << USPI_PROTSTS_TXSTIF_Pos)                /*!< USPI_T::PROTSTS: TXSTIF Mask           */
+
+#define USPI_PROTSTS_TXENDIF_Pos         (2)                                               /*!< USPI_T::PROTSTS: TXENDIF Position      */
+#define USPI_PROTSTS_TXENDIF_Msk         (0x1ul << USPI_PROTSTS_TXENDIF_Pos)               /*!< USPI_T::PROTSTS: TXENDIF Mask          */
+
+#define USPI_PROTSTS_RXSTIF_Pos          (3)                                               /*!< USPI_T::PROTSTS: RXSTIF Position       */
+#define USPI_PROTSTS_RXSTIF_Msk          (0x1ul << USPI_PROTSTS_RXSTIF_Pos)                /*!< USPI_T::PROTSTS: RXSTIF Mask           */
+
+#define USPI_PROTSTS_RXENDIF_Pos         (4)                                               /*!< USPI_T::PROTSTS: RXENDIF Position      */
+#define USPI_PROTSTS_RXENDIF_Msk         (0x1ul << USPI_PROTSTS_RXENDIF_Pos)               /*!< USPI_T::PROTSTS: RXENDIF Mask          */
+
+#define USPI_PROTSTS_SLVTOIF_Pos         (5)                                               /*!< USPI_T::PROTSTS: SLVTOIF Position      */
+#define USPI_PROTSTS_SLVTOIF_Msk         (0x1ul << USPI_PROTSTS_SLVTOIF_Pos)               /*!< USPI_T::PROTSTS: SLVTOIF Mask          */
+
+#define USPI_PROTSTS_SLVBEIF_Pos         (6)                                               /*!< USPI_T::PROTSTS: SLVBEIF Position      */
+#define USPI_PROTSTS_SLVBEIF_Msk         (0x1ul << USPI_PROTSTS_SLVBEIF_Pos)               /*!< USPI_T::PROTSTS: SLVBEIF Mask          */
+
+#define USPI_PROTSTS_SSINAIF_Pos         (8)                                               /*!< USPI_T::PROTSTS: SSINAIF Position      */
+#define USPI_PROTSTS_SSINAIF_Msk         (0x1ul << USPI_PROTSTS_SSINAIF_Pos)               /*!< USPI_T::PROTSTS: SSINAIF Mask          */
+
+#define USPI_PROTSTS_SSACTIF_Pos         (9)                                               /*!< USPI_T::PROTSTS: SSACTIF Position      */
+#define USPI_PROTSTS_SSACTIF_Msk         (0x1ul << USPI_PROTSTS_SSACTIF_Pos)               /*!< USPI_T::PROTSTS: SSACTIF Mask          */
+
+#define USPI_PROTSTS_SSLINE_Pos          (16)                                              /*!< USPI_T::PROTSTS: SSLINE Position       */
+#define USPI_PROTSTS_SSLINE_Msk          (0x1ul << USPI_PROTSTS_SSLINE_Pos)                /*!< USPI_T::PROTSTS: SSLINE Mask           */
+
+#define USPI_PROTSTS_BUSY_Pos            (17)                                              /*!< USPI_T::PROTSTS: BUSY Position         */
+#define USPI_PROTSTS_BUSY_Msk            (0x1ul << USPI_PROTSTS_BUSY_Pos)                  /*!< USPI_T::PROTSTS: BUSY Mask             */
+
+#define USPI_PROTSTS_SLVUDR_Pos          (18)                                              /*!< USPI_T::PROTSTS: SLVUDR Position       */
+#define USPI_PROTSTS_SLVUDR_Msk          (0x1ul << USPI_PROTSTS_SLVUDR_Pos)                /*!< USPI_T::PROTSTS: SLVUDR Mask           */
+
+/**@}*/ /* USPI_CONST */
+/**@}*/ /* end of USPI register group */
+/**@}*/ /* end of REGISTER group */
+
+#endif /* __USPI_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/uuart_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/uuart_reg.h
new file mode 100644
index 0000000000..75a14cfbcc
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/uuart_reg.h
@@ -0,0 +1,670 @@
+/**************************************************************************//**
+ * @file     uuart_reg.h
+ * @version  V1.00
+ * @brief    UUART register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __UUART_REG_H__
+#define __UUART_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+
+/*---------------------- UART Mode of USCI Controller -------------------------*/
+/**
+    @addtogroup UUART UART Mode of USCI Controller(UUART)
+    Memory Mapped Structure for UUART Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var UUART_T::CTL
+     * Offset: 0x00  USCI Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[2:0]   |FUNMODE   |Function Mode
+     * |        |          |This bit field selects the protocol for this USCI controller.
+     * |        |          |Selecting a protocol that is not available or a reserved combination disables the USCI.
+     * |        |          |When switching between two protocols, the USCI has to be disabled before selecting a new protocol.
+     * |        |          |Simultaneously, the USCI will be reset when user write 000 to FUNMODE.
+     * |        |          |000 = The USCI is disabled. All protocol related state machines are set to idle state.
+     * |        |          |001 = The SPI protocol is selected.
+     * |        |          |010 = The UART protocol is selected.
+     * |        |          |100 = The I2C protocol is selected.
+     * |        |          |Others = Reserved.
+     * @var UUART_T::INTEN
+     * Offset: 0x04  USCI Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1]     |TXSTIEN   |Transmit Start Interrupt Enable Bit
+     * |        |          |This bit enables the interrupt generation in case of a transmit start event.
+     * |        |          |0 = The transmit start interrupt is disabled.
+     * |        |          |1 = The transmit start interrupt is enabled.
+     * |[2]     |TXENDIEN  |Transmit End Interrupt Enable Bit
+     * |        |          |This bit enables the interrupt generation in case of a transmit finish event.
+     * |        |          |0 = The transmit finish interrupt is disabled.
+     * |        |          |1 = The transmit finish interrupt is enabled.
+     * |[3]     |RXSTIEN   |Receive Start Interrupt Enable Bit
+     * |        |          |This bit enables the interrupt generation in case of a receive start event.
+     * |        |          |0 = The receive start interrupt is disabled.
+     * |        |          |1 = The receive start interrupt is enabled.
+     * |[4]     |RXENDIEN  |Receive End Interrupt Enable Bit
+     * |        |          |This bit enables the interrupt generation in case of a receive finish event.
+     * |        |          |0 = The receive end interrupt is disabled.
+     * |        |          |1 = The receive end interrupt is enabled.
+     * @var UUART_T::BRGEN
+     * Offset: 0x08  USCI Baud Rate Generator Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RCLKSEL   |Reference Clock Source Selection
+     * |        |          |This bit selects the source signal of reference clock (fREF_CLK).
+     * |        |          |0 = Peripheral device clock fPCLK.
+     * |        |          |1 = Reserved.
+     * |[1]     |PTCLKSEL  |Protocol Clock Source Selection
+     * |        |          |This bit selects the source signal of protocol clock (fPROT_CLK).
+     * |        |          |0 = Reference clock fREF_CLK.
+     * |        |          |1 = fREF_CLK2 (its frequency is half of fREF_CLK).
+     * |[3:2]   |SPCLKSEL  |Sample Clock Source Selection
+     * |        |          |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
+     * |        |          |00 = fSAMP_CLK frequency is fDIV_CLK.
+     * |        |          |01 = fSAMP_CLK frequency is from fPROT_CLK.
+     * |        |          |10 = fSAMP_CLK frequency is from fSCLK.
+     * |        |          |11 = fSAMP_CLK frequency is from fREF_CLK.
+     * |[4]     |TMCNTEN   |Timing Measurement Counter Enable Bit
+     * |        |          |This bit enables the 10-bit timing measurement counter.
+     * |        |          |0 = Timing measurement counter is Disabled.
+     * |        |          |1 = Timing measurement counter is Enabled.
+     * |[5]     |TMCNTSRC  |Timing Measurement Counter Clock Source Selection
+     * |        |          |0 = Timing measurement counter with fPROT_CLK.
+     * |        |          |1 = Timing measurement counter with fDIV_CLK.
+     * |[9:8]   |PDSCNT    |Pre-divider for Sample Counter
+     * |        |          |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK.
+     * |        |          |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1).
+     * |[14:10] |DSCNT     |Denominator for Sample Counter
+     * |        |          |This bit field defines the divide ratio of the sample clock fSAMP_CLK.
+     * |        |          |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1).
+     * |        |          |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value.
+     * |[25:16] |CLKDIV    |Clock Divider
+     * |        |          |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ).
+     * |        |          |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled.
+     * |        |          |The revised value is the average bit time between bit 5 and bit 6.
+     * |        |          |The user can use revised CLKDIV and new BRDETITV (UUART_PROTCTL[24:16]) to calculate the precise baud rate.
+     * @var UUART_T::DATIN0
+     * Offset: 0x10  USCI Input Data Signal Configuration Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SYNCSEL   |Input Signal Synchronization Selection
+     * |        |          |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data  shift unit.
+     * |        |          |0 = The un-synchronized signal can be taken as input for the data shift unit.
+     * |        |          |1 = The synchronized signal can be taken as input for the data shift unit.
+     * |[2]     |ININV     |Input Signal Inverse Selection
+     * |        |          |This bit defines the inverter enable of the input asynchronous signal.
+     * |        |          |0 = The un-synchronized input signal will not be inverted.
+     * |        |          |1 = The un-synchronized input signal will be inverted.
+     * |[4:3]   |EDGEDET   |Input Signal Edge Detection Mode
+     * |        |          |This bit field selects which edge actives the trigger event of input data signal.
+     * |        |          |00 = The trigger event activation is disabled.
+     * |        |          |01 = A rising edge activates the trigger event of input data signal.
+     * |        |          |10 = A falling edge activates the trigger event of input data signal.
+     * |        |          |11 = Both edges activate the trigger event of input data signal.
+     * |        |          |Note: In UART function mode, it is suggested to set this bit field as 10.
+     * @var UUART_T::CTLIN0
+     * Offset: 0x20  USCI Input Control Signal Configuration Register 0
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SYNCSEL   |Input Synchronization Signal Selection
+     * |        |          |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
+     * |        |          |0 = The un-synchronized signal can be taken as input for the data shift unit.
+     * |        |          |1 = The synchronized signal can be taken as input for the data shift unit.
+     * |[2]     |ININV     |Input Signal Inverse Selection
+     * |        |          |This bit defines the inverter enable of the input asynchronous signal.
+     * |        |          |0 = The un-synchronized input signal will not be inverted.
+     * |        |          |1 = The un-synchronized input signal will be inverted.
+     * @var UUART_T::CLKIN
+     * Offset: 0x28  USCI Input Clock Signal Configuration Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |SYNCSEL   |Input Synchronization Signal Selection
+     * |        |          |This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
+     * |        |          |0 = The un-synchronized   signal can be taken as input for the data shift unit.
+     * |        |          |1 = The synchronized signal can be taken as input for the data shift unit.
+     * @var UUART_T::LINECTL
+     * Offset: 0x2C  USCI Line Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |LSB       |LSB First Transmission Selection
+     * |        |          |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first.
+     * |        |          |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first.
+     * |[5]     |DATOINV   |Data Output Inverse Selection
+     * |        |          |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin.
+     * |        |          |0 = The value of USCIx_DAT1 is equal to the data shift register.
+     * |        |          |1 = The value of USCIx_DAT1 is the inversion of data shift register.
+     * |[7]     |CTLOINV   |Control Signal Output Inverse Selection
+     * |        |          |This bit defines the relation between the internal control signal and the output control signal.
+     * |        |          |0 = No effect.
+     * |        |          |1 = The control signal will be inverted before its output.
+     * |        |          |Note: In UART protocol, the control signal means nRTS signal.
+     * |[11:8]  |DWIDTH    |Word Length of Transmission
+     * |        |          |This bit field defines the data word length (amount of bits) for reception and transmission
+     * |        |          |The data word is always right-aligned in the data buffer
+     * |        |          |USCI support word length from 4 to 16 bits.
+     * |        |          |0x0 = The data word contains 16 bits located at bit positions [15:0].
+     * |        |          |0x1 = Reserved.
+     * |        |          |0x2 = Reserved.
+     * |        |          |0x3 = Reserved.
+     * |        |          |0x4 = The data word contains 4 bits located at bit positions [3:0].
+     * |        |          |0x5 = The data word contains 5 bits located at bit positions [4:0].
+     * |        |          |...
+     * |        |          |0xF = The data word contains 15 bits located at bit positions [14:0].
+     * |        |          |Note: In UART protocol, the length can be configured as 6~13 bits.
+     * @var UUART_T::TXDAT
+     * Offset: 0x30  USCI Transmit Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |TXDAT     |Transmit Data
+     * |        |          |Software can use this bit field to write 16-bit transmit data for transmission.
+     * @var UUART_T::RXDAT
+     * Offset: 0x34  USCI Receive Data Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[15:0]  |RXDAT     |Received Data
+     * |        |          |This bit field monitors the received data which stored in receive data buffer.
+     * |        |          |Note: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UUART_PROTSTS[7:5]).
+     * @var UUART_T::BUFCTL
+     * Offset: 0x38  USCI Transmit/Receive Buffer Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[7]     |TXCLR     |Clear Transmit Buffer
+     * |        |          |0 = No effect.
+     * |        |          |1 = The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value).
+     * |        |          |Should only be used while the buffer is not taking part in data traffic.
+     * |        |          |Note: It is cleared automatically after one PCLK cycle.
+     * |[14]    |RXOVIEN   |Receive Buffer Overrun Error Interrupt Enable Control
+     * |        |          |0 = Receive overrun interrupt Disabled.
+     * |        |          |1 = Receive overrun interrupt Enabled.
+     * |[15]    |RXCLR     |Clear Receive Buffer
+     * |        |          |0 = No effect.
+     * |        |          |1 = The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value).
+     * |        |          |Should only be used while the buffer is not taking part in data traffic.
+     * |        |          |Note: It is cleared automatically after one PCLK cycle.
+     * |[16]    |TXRST     |Transmit Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer.
+     * |        |          |Note: It is cleared automatically after one PCLK cycle.
+     * |[17]    |RXRST     |Receive Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer.
+     * |        |          |Note1: It is cleared automatically after one PCLK cycle.
+     * |        |          |Note2: It is suggest to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1.
+     * @var UUART_T::BUFSTS
+     * Offset: 0x3C  USCI Transmit/Receive Buffer Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |RXEMPTY   |Receive Buffer Empty Indicator
+     * |        |          |0 = Receive buffer is not empty.
+     * |        |          |1 = Receive buffer is empty.
+     * |[1]     |RXFULL    |Receive Buffer Full Indicator
+     * |        |          |0 = Receive buffer is not full.
+     * |        |          |1 = Receive buffer is full.
+     * |[3]     |RXOVIF    |Receive Buffer Over-run Error Interrupt Status
+     * |        |          |This bit indicates that a receive buffer overrun error event has been detected.
+     * |        |          |If RXOVIEN (UUART_BUFCTL[14]) is enabled, the corresponding interrupt request is activated.
+     * |        |          |It is cleared by software writes 1 to this bit.
+     * |        |          |0 = A receive buffer overrun error event has not been detected.
+     * |        |          |1 = A receive buffer overrun error event has been detected.
+     * |[8]     |TXEMPTY   |Transmit Buffer Empty Indicator
+     * |        |          |0 = Transmit buffer is not empty.
+     * |        |          |1 = Transmit buffer is empty.
+     * |[9]     |TXFULL    |Transmit Buffer Full Indicator
+     * |        |          |0 = Transmit buffer is not full.
+     * |        |          |1 = Transmit buffer is full.
+     * @var UUART_T::PDMACTL
+     * Offset: 0x40  USCI PDMA Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |PDMARST   |PDMA Reset
+     * |        |          |0 = No effect.
+     * |        |          |1 = Reset the USCI PDMA control logic. This bit will be cleared to 0 automatically.
+     * |[1]     |TXPDMAEN  |PDMA Transmit Channel Available
+     * |        |          |0 = Transmit PDMA function Disabled.
+     * |        |          |1 = Transmit PDMA function Enabled.
+     * |[2]     |RXPDMAEN  |PDMA Receive Channel Available
+     * |        |          |0 = Receive PDMA function Disabled.
+     * |        |          |1 = Receive PDMA function Enabled.
+     * |[3]     |PDMAEN    |PDMA Mode Enable Bit
+     * |        |          |0 = PDMA function Disabled.
+     * |        |          |1 = PDMA function Enabled.
+     * @var UUART_T::WKCTL
+     * Offset: 0x54  USCI Wake-up Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WKEN      |Wake-up Enable Bit
+     * |        |          |0 = Wake-up function Disabled.
+     * |        |          |1 = Wake-up function Enabled.
+     * |[2]     |PDBOPT    |Power Down Blocking Option
+     * |        |          |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately.
+     * |        |          |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately.
+     * @var UUART_T::WKSTS
+     * Offset: 0x58  USCI Wake-up Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WKF       |Wake-up Flag
+     * |        |          |When chip is woken up from Power-down mode, this bit is set to 1
+     * |        |          |Software can write 1 to clear this bit.
+     * @var UUART_T::PROTCTL
+     * Offset: 0x5C  USCI Protocol Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |STOPB     |Stop Bits
+     * |        |          |This bit defines the number of stop bits in an UART frame.
+     * |        |          |0 = The number of stop bits is 1.
+     * |        |          |1 = The number of stop bits is 2.
+     * |[1]     |PARITYEN  |Parity Enable Bit
+     * |        |          |This bit defines the parity bit is enabled in an UART frame.
+     * |        |          |0 = The parity bit Disabled.
+     * |        |          |1 = The parity bit Enabled.
+     * |[2]     |EVENPARITY|Even Parity Enable Bit
+     * |        |          |0 = Odd number of logic 1's is transmitted and checked in each word.
+     * |        |          |1 = Even number of logic 1's is transmitted and checked in each word.
+     * |        |          |Note: This bit has effect only when PARITYEN is set.
+     * |[3]     |RTSAUTOEN |nRTS Auto-flow Control Enable Bit
+     * |        |          |When nRTS auto-flow is enabled, if the receiver buffer is full (RXFULL (UUART_BUFSTS[1] = 1)), the UART will de-assert nRTS signal.
+     * |        |          |0 = nRTS auto-flow control Disabled.
+     * |        |          |1 = nRTS auto-flow control Enabled.
+     * |        |          |Note: This bit has effect only when the RTSAUDIREN is not set.
+     * |[4]     |CTSAUTOEN |nCTS Auto-flow Control Enable Bit
+     * |        |          |When nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted).
+     * |        |          |0 = nCTS auto-flow control Disabled.
+     * |        |          |1 = nCTS auto-flow control Enabled.
+     * |[5]     |RTSAUDIREN|nRTS Auto Direction Enable Bit
+     * |        |          |When nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the nRTS signal is inactive.
+     * |        |          |0 = nRTS auto direction control Disabled.
+     * |        |          |1 = nRTS auto direction control Enabled.
+     * |        |          |Note1: This bit is used for nRTS auto direction control for RS485.
+     * |        |          |Note2: This bit has effect only when the RTSAUTOEN is not set.
+     * |[6]     |ABREN     |Auto-baud Rate Detect Enable Bit
+     * |        |          |0 = Auto-baud rate detect function Disabled.
+     * |        |          |1 = Auto-baud rate detect function Enabled.
+     * |        |          |Note: When the auto - baud rate detect operation finishes, hardware will clear this bit.
+     * |        |          |The associated interrupt ABRDETIF (UUART_PROTSTS[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled).
+     * |[9]     |DATWKEN   |Data Wake-up Mode Enable Bit
+     * |        |          |0 = Data wake-up mode Disabled.
+     * |        |          |1 = Data wake-up mode Enabled.
+     * |[10]    |CTSWKEN   |nCTS Wake-up Mode Enable Bit
+     * |        |          |0 = nCTS wake-up mode Disabled.
+     * |        |          |1 = nCTS wake-up mode Enabled.
+     * |[14:11] |WAKECNT   |Wake-up Counter
+     * |        |          |These bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode.
+     * |[24:16] |BRDETITV  |Baud Rate Detection Interval
+     * |        |          |This bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits.
+     * |        |          |The order of the bus shall be 1 and 0 step by step (e.g
+     * |        |          |the input data pattern shall be 0x55)
+     * |        |          |The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTCTL[9]) is set.
+     * |        |          |Note: This bit can be cleared to 0 by software writing 1 to the BRDETITV.
+     * |[26]    |STICKEN   |Stick Parity Enable Bit
+     * |        |          |0 = Stick parity Disabled.
+     * |        |          |1 = Stick parity Enabled.
+     * |        |          |Note: Refer to RS-485 Support section for detail information.
+     * |[29]    |BCEN      |Transmit Break Control Enable Bit
+     * |        |          |0 = Transmit Break Control Disabled.
+     * |        |          |1 = Transmit Break Control Enabled.
+     * |        |          |Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0).
+     * |        |          |This bit acts only on TX line and has no effect on the transmitter logic.
+     * |[30]    |DGE       |Deglitch Enable Bit
+     * |        |          |0 = Deglitch Disabled.
+     * |        |          |1 = Deglitch Enabled.
+     * |        |          |Note: When this bit is set to logic 1, any pulse width less than about 300 ns will be considered a glitch and will be removed in the serial data input (RX).
+     * |        |          |This bit acts only on RX line and has no effect on the transmitter logic.
+     * |[31]    |PROTEN    |UART Protocol Enable Bit
+     * |        |          |0 = UART Protocol Disabled.
+     * |        |          |1 = UART Protocol Enabled.
+     * @var UUART_T::PROTIEN
+     * Offset: 0x60  USCI Protocol Interrupt Enable Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1]     |ABRIEN    |Auto-baud Rate Interrupt Enable Bit
+     * |        |          |0 = Auto-baud rate interrupt Disabled.
+     * |        |          |1 = Auto-baud rate interrupt Enabled.
+     * |[2]     |RLSIEN    |Receive Line Status Interrupt Enable Bit
+     * |        |          |0 = Receive line status interrupt Disabled.
+     * |        |          |1 = Receive line status interrupt Enabled.
+     * |        |          |Note: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt.
+     * @var UUART_T::PROTSTS
+     * Offset: 0x64  USCI Protocol Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1]     |TXSTIF    |Transmit Start Interrupt Flag
+     * |        |          |0 = A transmit start interrupt status has not occurred.
+     * |        |          |1 = A transmit start interrupt status has occurred.
+     * |        |          |Note1: It is cleared by software writing one into this bit.
+     * |        |          |Note2: Used for user to load next transmit data when there is no data in transmit buffer.
+     * |[2]     |TXENDIF   |Transmit End Interrupt Flag
+     * |        |          |0 = A transmit end interrupt status has not occurred.
+     * |        |          |1 = A transmit end interrupt status has occurred.
+     * |        |          |Note: It is cleared by software writing one into this bit.
+     * |[3]     |RXSTIF    |Receive Start Interrupt Flag
+     * |        |          |0 = A receive start interrupt status has not occurred.
+     * |        |          |1 = A receive start interrupt status has occurred.
+     * |        |          |Note: It is cleared by software writing one into this bit.
+     * |[4]     |RXENDIF   |Receive End Interrupt Flag
+     * |        |          |0 = A receive finish interrupt status has not occurred.
+     * |        |          |1 = A receive finish interrupt status has occurred.
+     * |        |          |Note: It is cleared by software writing one into this bit.
+     * |[5]     |PARITYERR |Parity Error Flag
+     * |        |          |This bit is set to logic 1 whenever the received character does not have a valid parity bit.
+     * |        |          |0 = No parity error is generated.
+     * |        |          |1 = Parity error is generated.
+     * |        |          |Note: This bit can be cleared by write 1 among the BREAK, FRMERR and PARITYERR bits.
+     * |[6]     |FRMERR    |Framing Error Flag
+     * |        |          |This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
+     * |        |          |0 = No framing error is generated.
+     * |        |          |1 = Framing error is generated.
+     * |        |          |Note: This bit can be cleared by write 1 among the BREAK, FRMERR and PARITYERR bits.
+     * |[7]     |BREAK     |Break Flag
+     * |        |          |This bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits).
+     * |        |          |0 = No Break is generated.
+     * |        |          |1 = Break is generated in the receiver bus.
+     * |        |          |Note: This bit can be cleared by write 1 among the BREAK, FRMERR and PARITYERR bits.
+     * |[9]     |ABRDETIF  |Auto-baud Rate Interrupt Flag
+     * |        |          |This bit is set when auto-baud rate detection is done among the falling edge of the input data.
+     * |        |          |If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated.
+     * |        |          |This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus.
+     * |        |          |0 = Auto-baud rate detect function is not done.
+     * |        |          |1 = One Bit auto-baud rate detect function is done.
+     * |        |          |Note: This bit can be cleared by writing 1 to it.
+     * |[10]    |RXBUSY    |RX Bus Status Flag (Read Only)
+     * |        |          |This bit indicates the busy status of the receiver.
+     * |        |          |0 = The receiver is Idle.
+     * |        |          |1 = The receiver is BUSY.
+     * |[11]    |ABERRSTS  |Auto-baud Rate Error Status
+     * |        |          |This bit is set when auto-baud rate detection counter overrun.
+     * |        |          |When the auto-baud rate counter overrun, the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the correct baud rate again.
+     * |        |          |0 = Auto-baud rate detect counter is not overrun.
+     * |        |          |1 = Auto-baud rate detect counter is overrun.
+     * |        |          |Note1: This bit is set at the same time of ABRDETIF.
+     * |        |          |Note2: This bit can be cleared by writing 1 to ABRDETIF or ABERRSTS.
+     * |[16]    |CTSSYNCLV |nCTS Synchronized Level Status (Read Only)
+     * |        |          |This bit used to indicate the current status of the internal synchronized nCTS signal.
+     * |        |          |0 = The internal synchronized nCTS is low.
+     * |        |          |1 = The internal synchronized nCTS is high.
+     * |[17]    |CTSLV     |nCTS Pin Status (Read Only)
+     * |        |          |This bit used to monitor the current status of nCTS pin input.
+     * |        |          |0 = nCTS pin input is low level voltage logic state.
+     * |        |          |1 = nCTS pin input is high level voltage logic state.
+     */
+
+    __IO uint32_t CTL;                   /*!< [0x0000] USCI Control Register                                            */
+    __IO uint32_t INTEN;                 /*!< [0x0004] USCI Interrupt Enable Register                                   */
+    __IO uint32_t BRGEN;                 /*!< [0x0008] USCI Baud Rate Generator Register                                */
+    __I  uint32_t RESERVE0[1];
+    __IO uint32_t DATIN0;                /*!< [0x0010] USCI Input Data Signal Configuration Register 0                  */
+    __I  uint32_t RESERVE1[3];
+    __IO uint32_t CTLIN0;                /*!< [0x0020] USCI Input Control Signal Configuration Register 0               */
+    __I  uint32_t RESERVE2[1];
+    __IO uint32_t CLKIN;                 /*!< [0x0028] USCI Input Clock Signal Configuration Register                   */
+    __IO uint32_t LINECTL;               /*!< [0x002c] USCI Line Control Register                                       */
+    __O  uint32_t TXDAT;                 /*!< [0x0030] USCI Transmit Data Register                                      */
+    __I  uint32_t RXDAT;                 /*!< [0x0034] USCI Receive Data Register                                       */
+    __IO uint32_t BUFCTL;                /*!< [0x0038] USCI Transmit/Receive Buffer Control Register                    */
+    __IO uint32_t BUFSTS;                /*!< [0x003c] USCI Transmit/Receive Buffer Status Register                     */
+    __IO uint32_t PDMACTL;               /*!< [0x0040] USCI PDMA Control Register                                       */
+    __I  uint32_t RESERVE3[4];
+    __IO uint32_t WKCTL;                 /*!< [0x0054] USCI Wake-up Control Register                                    */
+    __IO uint32_t WKSTS;                 /*!< [0x0058] USCI Wake-up Status Register                                     */
+    __IO uint32_t PROTCTL;               /*!< [0x005c] USCI Protocol Control Register                                   */
+    __IO uint32_t PROTIEN;               /*!< [0x0060] USCI Protocol Interrupt Enable Register                          */
+    __IO uint32_t PROTSTS;               /*!< [0x0064] USCI Protocol Status Register                                    */
+
+} UUART_T;
+
+/**
+    @addtogroup UUART_CONST UUART Bit Field Definition
+    Constant Definitions for UUART Controller
+  @{
+*/
+
+#define UUART_CTL_FUNMODE_Pos            (0)                                               /*!< UUART_T::CTL: FUNMODE Position         */
+#define UUART_CTL_FUNMODE_Msk            (0x7ul << UUART_CTL_FUNMODE_Pos)                  /*!< UUART_T::CTL: FUNMODE Mask             */
+
+#define UUART_INTEN_TXSTIEN_Pos          (1)                                               /*!< UUART_T::INTEN: TXSTIEN Position       */
+#define UUART_INTEN_TXSTIEN_Msk          (0x1ul << UUART_INTEN_TXSTIEN_Pos)                /*!< UUART_T::INTEN: TXSTIEN Mask           */
+
+#define UUART_INTEN_TXENDIEN_Pos         (2)                                               /*!< UUART_T::INTEN: TXENDIEN Position      */
+#define UUART_INTEN_TXENDIEN_Msk         (0x1ul << UUART_INTEN_TXENDIEN_Pos)               /*!< UUART_T::INTEN: TXENDIEN Mask          */
+
+#define UUART_INTEN_RXSTIEN_Pos          (3)                                               /*!< UUART_T::INTEN: RXSTIEN Position       */
+#define UUART_INTEN_RXSTIEN_Msk          (0x1ul << UUART_INTEN_RXSTIEN_Pos)                /*!< UUART_T::INTEN: RXSTIEN Mask           */
+
+#define UUART_INTEN_RXENDIEN_Pos         (4)                                               /*!< UUART_T::INTEN: RXENDIEN Position      */
+#define UUART_INTEN_RXENDIEN_Msk         (0x1ul << UUART_INTEN_RXENDIEN_Pos)               /*!< UUART_T::INTEN: RXENDIEN Mask          */
+
+#define UUART_BRGEN_RCLKSEL_Pos          (0)                                               /*!< UUART_T::BRGEN: RCLKSEL Position       */
+#define UUART_BRGEN_RCLKSEL_Msk          (0x1ul << UUART_BRGEN_RCLKSEL_Pos)                /*!< UUART_T::BRGEN: RCLKSEL Mask           */
+
+#define UUART_BRGEN_PTCLKSEL_Pos         (1)                                               /*!< UUART_T::BRGEN: PTCLKSEL Position      */
+#define UUART_BRGEN_PTCLKSEL_Msk         (0x1ul << UUART_BRGEN_PTCLKSEL_Pos)               /*!< UUART_T::BRGEN: PTCLKSEL Mask          */
+
+#define UUART_BRGEN_SPCLKSEL_Pos         (2)                                               /*!< UUART_T::BRGEN: SPCLKSEL Position      */
+#define UUART_BRGEN_SPCLKSEL_Msk         (0x3ul << UUART_BRGEN_SPCLKSEL_Pos)               /*!< UUART_T::BRGEN: SPCLKSEL Mask          */
+
+#define UUART_BRGEN_TMCNTEN_Pos          (4)                                               /*!< UUART_T::BRGEN: TMCNTEN Position       */
+#define UUART_BRGEN_TMCNTEN_Msk          (0x1ul << UUART_BRGEN_TMCNTEN_Pos)                /*!< UUART_T::BRGEN: TMCNTEN Mask           */
+
+#define UUART_BRGEN_TMCNTSRC_Pos         (5)                                               /*!< UUART_T::BRGEN: TMCNTSRC Position      */
+#define UUART_BRGEN_TMCNTSRC_Msk         (0x1ul << UUART_BRGEN_TMCNTSRC_Pos)               /*!< UUART_T::BRGEN: TMCNTSRC Mask          */
+
+#define UUART_BRGEN_PDSCNT_Pos           (8)                                               /*!< UUART_T::BRGEN: PDSCNT Position        */
+#define UUART_BRGEN_PDSCNT_Msk           (0x3ul << UUART_BRGEN_PDSCNT_Pos)                 /*!< UUART_T::BRGEN: PDSCNT Mask            */
+
+#define UUART_BRGEN_DSCNT_Pos            (10)                                              /*!< UUART_T::BRGEN: DSCNT Position         */
+#define UUART_BRGEN_DSCNT_Msk            (0x1ful << UUART_BRGEN_DSCNT_Pos)                 /*!< UUART_T::BRGEN: DSCNT Mask             */
+
+#define UUART_BRGEN_CLKDIV_Pos           (16)                                              /*!< UUART_T::BRGEN: CLKDIV Position        */
+#define UUART_BRGEN_CLKDIV_Msk           (0x3fful << UUART_BRGEN_CLKDIV_Pos)               /*!< UUART_T::BRGEN: CLKDIV Mask            */
+
+#define UUART_DATIN0_SYNCSEL_Pos         (0)                                               /*!< UUART_T::DATIN0: SYNCSEL Position      */
+#define UUART_DATIN0_SYNCSEL_Msk         (0x1ul << UUART_DATIN0_SYNCSEL_Pos)               /*!< UUART_T::DATIN0: SYNCSEL Mask          */
+
+#define UUART_DATIN0_ININV_Pos           (2)                                               /*!< UUART_T::DATIN0: ININV Position        */
+#define UUART_DATIN0_ININV_Msk           (0x1ul << UUART_DATIN0_ININV_Pos)                 /*!< UUART_T::DATIN0: ININV Mask            */
+
+#define UUART_DATIN0_EDGEDET_Pos         (3)                                               /*!< UUART_T::DATIN0: EDGEDET Position      */
+#define UUART_DATIN0_EDGEDET_Msk         (0x3ul << UUART_DATIN0_EDGEDET_Pos)               /*!< UUART_T::DATIN0: EDGEDET Mask          */
+
+#define UUART_CTLIN0_SYNCSEL_Pos         (0)                                               /*!< UUART_T::CTLIN0: SYNCSEL Position      */
+#define UUART_CTLIN0_SYNCSEL_Msk         (0x1ul << UUART_CTLIN0_SYNCSEL_Pos)               /*!< UUART_T::CTLIN0: SYNCSEL Mask          */
+
+#define UUART_CTLIN0_ININV_Pos           (2)                                               /*!< UUART_T::CTLIN0: ININV Position        */
+#define UUART_CTLIN0_ININV_Msk           (0x1ul << UUART_CTLIN0_ININV_Pos)                 /*!< UUART_T::CTLIN0: ININV Mask            */
+
+#define UUART_CLKIN_SYNCSEL_Pos          (0)                                               /*!< UUART_T::CLKIN: SYNCSEL Position       */
+#define UUART_CLKIN_SYNCSEL_Msk          (0x1ul << UUART_CLKIN_SYNCSEL_Pos)                /*!< UUART_T::CLKIN: SYNCSEL Mask           */
+
+#define UUART_LINECTL_LSB_Pos            (0)                                               /*!< UUART_T::LINECTL: LSB Position         */
+#define UUART_LINECTL_LSB_Msk            (0x1ul << UUART_LINECTL_LSB_Pos)                  /*!< UUART_T::LINECTL: LSB Mask             */
+
+#define UUART_LINECTL_DATOINV_Pos        (5)                                               /*!< UUART_T::LINECTL: DATOINV Position     */
+#define UUART_LINECTL_DATOINV_Msk        (0x1ul << UUART_LINECTL_DATOINV_Pos)              /*!< UUART_T::LINECTL: DATOINV Mask         */
+
+#define UUART_LINECTL_CTLOINV_Pos        (7)                                               /*!< UUART_T::LINECTL: CTLOINV Position     */
+#define UUART_LINECTL_CTLOINV_Msk        (0x1ul << UUART_LINECTL_CTLOINV_Pos)              /*!< UUART_T::LINECTL: CTLOINV Mask         */
+
+#define UUART_LINECTL_DWIDTH_Pos         (8)                                               /*!< UUART_T::LINECTL: DWIDTH Position      */
+#define UUART_LINECTL_DWIDTH_Msk         (0xful << UUART_LINECTL_DWIDTH_Pos)               /*!< UUART_T::LINECTL: DWIDTH Mask          */
+
+#define UUART_TXDAT_TXDAT_Pos            (0)                                               /*!< UUART_T::TXDAT: TXDAT Position         */
+#define UUART_TXDAT_TXDAT_Msk            (0xfffful << UUART_TXDAT_TXDAT_Pos)               /*!< UUART_T::TXDAT: TXDAT Mask             */
+
+#define UUART_RXDAT_RXDAT_Pos            (0)                                               /*!< UUART_T::RXDAT: RXDAT Position         */
+#define UUART_RXDAT_RXDAT_Msk            (0xfffful << UUART_RXDAT_RXDAT_Pos)               /*!< UUART_T::RXDAT: RXDAT Mask             */
+
+#define UUART_BUFCTL_TXCLR_Pos           (7)                                               /*!< UUART_T::BUFCTL: TXCLR Position        */
+#define UUART_BUFCTL_TXCLR_Msk           (0x1ul << UUART_BUFCTL_TXCLR_Pos)                 /*!< UUART_T::BUFCTL: TXCLR Mask            */
+
+#define UUART_BUFCTL_RXOVIEN_Pos         (14)                                              /*!< UUART_T::BUFCTL: RXOVIEN Position      */
+#define UUART_BUFCTL_RXOVIEN_Msk         (0x1ul << UUART_BUFCTL_RXOVIEN_Pos)               /*!< UUART_T::BUFCTL: RXOVIEN Mask          */
+
+#define UUART_BUFCTL_RXCLR_Pos           (15)                                              /*!< UUART_T::BUFCTL: RXCLR Position        */
+#define UUART_BUFCTL_RXCLR_Msk           (0x1ul << UUART_BUFCTL_RXCLR_Pos)                 /*!< UUART_T::BUFCTL: RXCLR Mask            */
+
+#define UUART_BUFCTL_TXRST_Pos           (16)                                              /*!< UUART_T::BUFCTL: TXRST Position        */
+#define UUART_BUFCTL_TXRST_Msk           (0x1ul << UUART_BUFCTL_TXRST_Pos)                 /*!< UUART_T::BUFCTL: TXRST Mask            */
+
+#define UUART_BUFCTL_RXRST_Pos           (17)                                              /*!< UUART_T::BUFCTL: RXRST Position        */
+#define UUART_BUFCTL_RXRST_Msk           (0x1ul << UUART_BUFCTL_RXRST_Pos)                 /*!< UUART_T::BUFCTL: RXRST Mask            */
+
+#define UUART_BUFSTS_RXEMPTY_Pos         (0)                                               /*!< UUART_T::BUFSTS: RXEMPTY Position      */
+#define UUART_BUFSTS_RXEMPTY_Msk         (0x1ul << UUART_BUFSTS_RXEMPTY_Pos)               /*!< UUART_T::BUFSTS: RXEMPTY Mask          */
+
+#define UUART_BUFSTS_RXFULL_Pos          (1)                                               /*!< UUART_T::BUFSTS: RXFULL Position       */
+#define UUART_BUFSTS_RXFULL_Msk          (0x1ul << UUART_BUFSTS_RXFULL_Pos)                /*!< UUART_T::BUFSTS: RXFULL Mask           */
+
+#define UUART_BUFSTS_RXOVIF_Pos          (3)                                               /*!< UUART_T::BUFSTS: RXOVIF Position       */
+#define UUART_BUFSTS_RXOVIF_Msk          (0x1ul << UUART_BUFSTS_RXOVIF_Pos)                /*!< UUART_T::BUFSTS: RXOVIF Mask           */
+
+#define UUART_BUFSTS_TXEMPTY_Pos         (8)                                               /*!< UUART_T::BUFSTS: TXEMPTY Position      */
+#define UUART_BUFSTS_TXEMPTY_Msk         (0x1ul << UUART_BUFSTS_TXEMPTY_Pos)               /*!< UUART_T::BUFSTS: TXEMPTY Mask          */
+
+#define UUART_BUFSTS_TXFULL_Pos          (9)                                               /*!< UUART_T::BUFSTS: TXFULL Position       */
+#define UUART_BUFSTS_TXFULL_Msk          (0x1ul << UUART_BUFSTS_TXFULL_Pos)                /*!< UUART_T::BUFSTS: TXFULL Mask           */
+
+#define UUART_PDMACTL_PDMARST_Pos        (0)                                               /*!< UUART_T::PDMACTL: PDMARST Position     */
+#define UUART_PDMACTL_PDMARST_Msk        (0x1ul << UUART_PDMACTL_PDMARST_Pos)              /*!< UUART_T::PDMACTL: PDMARST Mask         */
+
+#define UUART_PDMACTL_TXPDMAEN_Pos       (1)                                               /*!< UUART_T::PDMACTL: TXPDMAEN Position    */
+#define UUART_PDMACTL_TXPDMAEN_Msk       (0x1ul << UUART_PDMACTL_TXPDMAEN_Pos)             /*!< UUART_T::PDMACTL: TXPDMAEN Mask        */
+
+#define UUART_PDMACTL_RXPDMAEN_Pos       (2)                                               /*!< UUART_T::PDMACTL: RXPDMAEN Position    */
+#define UUART_PDMACTL_RXPDMAEN_Msk       (0x1ul << UUART_PDMACTL_RXPDMAEN_Pos)             /*!< UUART_T::PDMACTL: RXPDMAEN Mask        */
+
+#define UUART_PDMACTL_PDMAEN_Pos         (3)                                               /*!< UUART_T::PDMACTL: PDMAEN Position      */
+#define UUART_PDMACTL_PDMAEN_Msk         (0x1ul << UUART_PDMACTL_PDMAEN_Pos)               /*!< UUART_T::PDMACTL: PDMAEN Mask          */
+
+#define UUART_WKCTL_WKEN_Pos             (0)                                               /*!< UUART_T::WKCTL: WKEN Position          */
+#define UUART_WKCTL_WKEN_Msk             (0x1ul << UUART_WKCTL_WKEN_Pos)                   /*!< UUART_T::WKCTL: WKEN Mask              */
+
+#define UUART_WKCTL_PDBOPT_Pos           (2)                                               /*!< UUART_T::WKCTL: PDBOPT Position        */
+#define UUART_WKCTL_PDBOPT_Msk           (0x1ul << UUART_WKCTL_PDBOPT_Pos)                 /*!< UUART_T::WKCTL: PDBOPT Mask            */
+
+#define UUART_WKSTS_WKF_Pos              (0)                                               /*!< UUART_T::WKSTS: WKF Position           */
+#define UUART_WKSTS_WKF_Msk              (0x1ul << UUART_WKSTS_WKF_Pos)                    /*!< UUART_T::WKSTS: WKF Mask               */
+
+#define UUART_PROTCTL_STOPB_Pos          (0)                                               /*!< UUART_T::PROTCTL: STOPB Position       */
+#define UUART_PROTCTL_STOPB_Msk          (0x1ul << UUART_PROTCTL_STOPB_Pos)                /*!< UUART_T::PROTCTL: STOPB Mask           */
+
+#define UUART_PROTCTL_PARITYEN_Pos       (1)                                               /*!< UUART_T::PROTCTL: PARITYEN Position    */
+#define UUART_PROTCTL_PARITYEN_Msk       (0x1ul << UUART_PROTCTL_PARITYEN_Pos)             /*!< UUART_T::PROTCTL: PARITYEN Mask        */
+
+#define UUART_PROTCTL_EVENPARITY_Pos     (2)                                               /*!< UUART_T::PROTCTL: EVENPARITY Position  */
+#define UUART_PROTCTL_EVENPARITY_Msk     (0x1ul << UUART_PROTCTL_EVENPARITY_Pos)           /*!< UUART_T::PROTCTL: EVENPARITY Mask      */
+
+#define UUART_PROTCTL_RTSAUTOEN_Pos      (3)                                               /*!< UUART_T::PROTCTL: RTSAUTOEN Position   */
+#define UUART_PROTCTL_RTSAUTOEN_Msk      (0x1ul << UUART_PROTCTL_RTSAUTOEN_Pos)            /*!< UUART_T::PROTCTL: RTSAUTOEN Mask       */
+
+#define UUART_PROTCTL_CTSAUTOEN_Pos      (4)                                               /*!< UUART_T::PROTCTL: CTSAUTOEN Position   */
+#define UUART_PROTCTL_CTSAUTOEN_Msk      (0x1ul << UUART_PROTCTL_CTSAUTOEN_Pos)            /*!< UUART_T::PROTCTL: CTSAUTOEN Mask       */
+
+#define UUART_PROTCTL_RTSAUDIREN_Pos     (5)                                               /*!< UUART_T::PROTCTL: RTSAUDIREN Position  */
+#define UUART_PROTCTL_RTSAUDIREN_Msk     (0x1ul << UUART_PROTCTL_RTSAUDIREN_Pos)           /*!< UUART_T::PROTCTL: RTSAUDIREN Mask      */
+
+#define UUART_PROTCTL_ABREN_Pos          (6)                                               /*!< UUART_T::PROTCTL: ABREN Position       */
+#define UUART_PROTCTL_ABREN_Msk          (0x1ul << UUART_PROTCTL_ABREN_Pos)                /*!< UUART_T::PROTCTL: ABREN Mask           */
+
+#define UUART_PROTCTL_DATWKEN_Pos        (9)                                               /*!< UUART_T::PROTCTL: DATWKEN Position     */
+#define UUART_PROTCTL_DATWKEN_Msk        (0x1ul << UUART_PROTCTL_DATWKEN_Pos)              /*!< UUART_T::PROTCTL: DATWKEN Mask         */
+
+#define UUART_PROTCTL_CTSWKEN_Pos        (10)                                              /*!< UUART_T::PROTCTL: CTSWKEN Position     */
+#define UUART_PROTCTL_CTSWKEN_Msk        (0x1ul << UUART_PROTCTL_CTSWKEN_Pos)              /*!< UUART_T::PROTCTL: CTSWKEN Mask         */
+
+#define UUART_PROTCTL_WAKECNT_Pos        (11)                                              /*!< UUART_T::PROTCTL: WAKECNT Position     */
+#define UUART_PROTCTL_WAKECNT_Msk        (0xful << UUART_PROTCTL_WAKECNT_Pos)              /*!< UUART_T::PROTCTL: WAKECNT Mask         */
+
+#define UUART_PROTCTL_BRDETITV_Pos       (16)                                              /*!< UUART_T::PROTCTL: BRDETITV Position    */
+#define UUART_PROTCTL_BRDETITV_Msk       (0x1fful << UUART_PROTCTL_BRDETITV_Pos)           /*!< UUART_T::PROTCTL: BRDETITV Mask        */
+
+#define UUART_PROTCTL_STICKEN_Pos        (26)                                              /*!< UUART_T::PROTCTL: STICKEN Position     */
+#define UUART_PROTCTL_STICKEN_Msk        (0x1ul << UUART_PROTCTL_STICKEN_Pos)              /*!< UUART_T::PROTCTL: STICKEN Mask         */
+
+#define UUART_PROTCTL_BCEN_Pos           (29)                                              /*!< UUART_T::PROTCTL: BCEN Position        */
+#define UUART_PROTCTL_BCEN_Msk           (0x1ul << UUART_PROTCTL_BCEN_Pos)                 /*!< UUART_T::PROTCTL: BCEN Mask            */
+
+#define UUART_PROTCTL_DGE_Pos            (30)                                              /*!< UUART_T::PROTCTL: DGE Position         */
+#define UUART_PROTCTL_DGE_Msk            (0x1ul << UUART_PROTCTL_DGE_Pos)                  /*!< UUART_T::PROTCTL: DGE Mask             */
+
+#define UUART_PROTCTL_PROTEN_Pos         (31)                                              /*!< UUART_T::PROTCTL: PROTEN Position      */
+#define UUART_PROTCTL_PROTEN_Msk         (0x1ul << UUART_PROTCTL_PROTEN_Pos)               /*!< UUART_T::PROTCTL: PROTEN Mask          */
+
+#define UUART_PROTIEN_ABRIEN_Pos         (1)                                               /*!< UUART_T::PROTIEN: ABRIEN Position      */
+#define UUART_PROTIEN_ABRIEN_Msk         (0x1ul << UUART_PROTIEN_ABRIEN_Pos)               /*!< UUART_T::PROTIEN: ABRIEN Mask          */
+
+#define UUART_PROTIEN_RLSIEN_Pos         (2)                                               /*!< UUART_T::PROTIEN: RLSIEN Position      */
+#define UUART_PROTIEN_RLSIEN_Msk         (0x1ul << UUART_PROTIEN_RLSIEN_Pos)               /*!< UUART_T::PROTIEN: RLSIEN Mask          */
+
+#define UUART_PROTSTS_TXSTIF_Pos         (1)                                               /*!< UUART_T::PROTSTS: TXSTIF Position      */
+#define UUART_PROTSTS_TXSTIF_Msk         (0x1ul << UUART_PROTSTS_TXSTIF_Pos)               /*!< UUART_T::PROTSTS: TXSTIF Mask          */
+
+#define UUART_PROTSTS_TXENDIF_Pos        (2)                                               /*!< UUART_T::PROTSTS: TXENDIF Position     */
+#define UUART_PROTSTS_TXENDIF_Msk        (0x1ul << UUART_PROTSTS_TXENDIF_Pos)              /*!< UUART_T::PROTSTS: TXENDIF Mask         */
+
+#define UUART_PROTSTS_RXSTIF_Pos         (3)                                               /*!< UUART_T::PROTSTS: RXSTIF Position      */
+#define UUART_PROTSTS_RXSTIF_Msk         (0x1ul << UUART_PROTSTS_RXSTIF_Pos)               /*!< UUART_T::PROTSTS: RXSTIF Mask          */
+
+#define UUART_PROTSTS_RXENDIF_Pos        (4)                                               /*!< UUART_T::PROTSTS: RXENDIF Position     */
+#define UUART_PROTSTS_RXENDIF_Msk        (0x1ul << UUART_PROTSTS_RXENDIF_Pos)              /*!< UUART_T::PROTSTS: RXENDIF Mask         */
+
+#define UUART_PROTSTS_PARITYERR_Pos      (5)                                               /*!< UUART_T::PROTSTS: PARITYERR Position   */
+#define UUART_PROTSTS_PARITYERR_Msk      (0x1ul << UUART_PROTSTS_PARITYERR_Pos)            /*!< UUART_T::PROTSTS: PARITYERR Mask       */
+
+#define UUART_PROTSTS_FRMERR_Pos         (6)                                               /*!< UUART_T::PROTSTS: FRMERR Position      */
+#define UUART_PROTSTS_FRMERR_Msk         (0x1ul << UUART_PROTSTS_FRMERR_Pos)               /*!< UUART_T::PROTSTS: FRMERR Mask          */
+
+#define UUART_PROTSTS_BREAK_Pos          (7)                                               /*!< UUART_T::PROTSTS: BREAK Position       */
+#define UUART_PROTSTS_BREAK_Msk          (0x1ul << UUART_PROTSTS_BREAK_Pos)                /*!< UUART_T::PROTSTS: BREAK Mask           */
+
+#define UUART_PROTSTS_ABRDETIF_Pos       (9)                                               /*!< UUART_T::PROTSTS: ABRDETIF Position    */
+#define UUART_PROTSTS_ABRDETIF_Msk       (0x1ul << UUART_PROTSTS_ABRDETIF_Pos)             /*!< UUART_T::PROTSTS: ABRDETIF Mask        */
+
+#define UUART_PROTSTS_RXBUSY_Pos         (10)                                              /*!< UUART_T::PROTSTS: RXBUSY Position      */
+#define UUART_PROTSTS_RXBUSY_Msk         (0x1ul << UUART_PROTSTS_RXBUSY_Pos)               /*!< UUART_T::PROTSTS: RXBUSY Mask          */
+
+#define UUART_PROTSTS_ABERRSTS_Pos       (11)                                              /*!< UUART_T::PROTSTS: ABERRSTS Position    */
+#define UUART_PROTSTS_ABERRSTS_Msk       (0x1ul << UUART_PROTSTS_ABERRSTS_Pos)             /*!< UUART_T::PROTSTS: ABERRSTS Mask        */
+
+#define UUART_PROTSTS_CTSSYNCLV_Pos      (16)                                              /*!< UUART_T::PROTSTS: CTSSYNCLV Position   */
+#define UUART_PROTSTS_CTSSYNCLV_Msk      (0x1ul << UUART_PROTSTS_CTSSYNCLV_Pos)            /*!< UUART_T::PROTSTS: CTSSYNCLV Mask       */
+
+#define UUART_PROTSTS_CTSLV_Pos          (17)                                              /*!< UUART_T::PROTSTS: CTSLV Position       */
+#define UUART_PROTSTS_CTSLV_Msk          (0x1ul << UUART_PROTSTS_CTSLV_Pos)                /*!< UUART_T::PROTSTS: CTSLV Mask           */
+
+/**@}*/ /* UUART_CONST */
+/**@}*/ /* end of UUART register group */
+/**@}*/ /* end of REGISTER group */
+
+#endif /* __UUART_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/wdt_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/wdt_reg.h
new file mode 100644
index 0000000000..4d4b79cd4a
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/wdt_reg.h
@@ -0,0 +1,177 @@
+/**************************************************************************//**
+ * @file     wdt_reg.h
+ * @version  V1.00
+ * @brief    WDT register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __WDT_REG_H__
+#define __WDT_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+
+/*---------------------- Watch Dog Timer Controller -------------------------*/
+/**
+    @addtogroup WDT Watch Dog Timer Controller(WDT)
+    Memory Mapped Structure for WDT Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var WDT_T::CTL
+     * Offset: 0x00  WDT Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1]     |RSTEN     |WDT Time-out Reset Enable Control (Write Protect)
+     * |        |          |Setting this bit will enable the WDT time-out reset system function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.
+     * |        |          |0 = WDT time-out reset system function Disabled.
+     * |        |          |1 = WDT time-out reset system function Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[2]     |RSTF      |WDT Time-out Reset Flag
+     * |        |          |This bit indicates the system has been reset by WDT time-out reset system event or not.
+     * |        |          |0 = WDT time-out reset system event did not occur.
+     * |        |          |1 = WDT time-out reset system event has been occurred.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[3]     |IF        |WDT Time-out Interrupt Flag
+     * |        |          |This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval
+     * |        |          |0 = WDT time-out interrupt event interrupt did not occur.
+     * |        |          |1 = WDT time-out interrupt interrupt event occurred.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[4]     |WKEN      |WDT Time-out Wake-up Function Control (Write Protect)
+     * |        |          |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a event to trigger CPU wake-up trigger event to chip.
+     * |        |          |0 = Trigger wWake-up trigger event function Disabled if WDT time-out interrupt signal generated.
+     * |        |          |1 = Trigger Wake-up trigger event function Enabled if WDT time-out interrupt signal generated.
+     * |        |          |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note2: Chip can be woken-up by while WDT time-out interrupt signal generated only if WDT clock source is selected to LIRC or LXT (32 kHz).
+     * |[5]     |WKF       |WDT Time-out Wake-up Flag (Write Protect)
+     * |        |          |This bit indicates the WDT time-out event has triggered interrupt chip wake-up or not.flag status of WDT
+     * |        |          |0 = WDT does not cause chip wake-up.
+     * |        |          |1 = Chip wake-up from Idle or Power-down mode if when WDT time-out interrupt signal is generated.
+     * |        |          |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note2: This bit is cleared by writing 1 to it.
+     * |[6]     |INTEN     |WDT Time-out Interrupt Enable Control (Write Protect)
+     * |        |          |If this bit is enabled, when WDT time-out event occurs, the IF (WDT_CTL[3]) will be set to 1 and the WDT time-out interrupt signal is generated and inform to CPU.
+     * |        |          |0 = WDT time-out interrupt Disabled.
+     * |        |          |1 = WDT time-out interrupt Enabled.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[7]     |WDTEN     |WDT Enable Control (Write Protect)
+     * |        |          |0 = Set WDT counter stop Disabled, and (This action will reset the internal up counter value will be reset also).
+     * |        |          |1 = Set WDT counter start Enabled.
+     * |        |          |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note2: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period to become active, user can read SYNC (WDT_CTL[30]) to check enable/disable command is completed or not.
+     * |        |          |Note32: If CWDTEN[2:0] (combined by with Config0[31] and Config0[4:3]) bits is not configure to 0x111, this bit is forced as 1 and user cannot change this bit to 0.
+     * |        |          |Note3: This bit disabled needs 2 * WDT_CLK.
+     * |[11:8]  |TOUTSEL   |WDT Time-out Interval Selection (Write Protect)
+     * |        |          |These three bits select the time-out interval period after for the WDT starts counting.
+     * |        |          |000 = 2^4 * WDT_CLK.
+     * |        |          |001 = 2^6 * WDT_CLK.
+     * |        |          |010 = 2^8 * WDT_CLK.
+     * |        |          |011 = 2^10 * WDT_CLK.
+     * |        |          |100 = 2^12 * WDT_CLK.
+     * |        |          |101 = 2^14 * WDT_CLK.
+     * |        |          |110 = 2^16 * WDT_CLK.
+     * |        |          |111 = 2^18 * WDT_CLK.
+     * |        |          |111 = 2^20 * WDT_CLK.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |[30]    |SYNC      |WDT Enable Control SYNC SYNC Flag Indicator (Read Only)
+     * |        |          |If use to synchronization, software er can check execute enable/disable this flag after enable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is become completed or not active or not..
+     * |        |          |SYNC delay is
+     * |        |          |0 = Set WDTEN bit is WDT enable control synccompletedhronizing is completion.
+     * |        |          |1 = Set WDTEN bit WDT enable control is synchronizing and not become active yet..
+     * |        |          |Note: Perform enable or disable WDTEN bit
+     * |        |          |This bit enabled needs 2 * WDT_CLK period to become active.
+     * |[31]    |ICEDEBUG  |ICE Debug Mode Acknowledge Disable Control (Write Protect)
+     * |        |          |0 = ICE debug mode acknowledgment affects WDT counting.
+     * |        |          |WDT up counter will be held while CPU is held by ICE.
+     * |        |          |1 = ICE debug mode acknowledgment Disabled.
+     * |        |          |WDT up counter will keep going no matter CPU is held by ICE or not.
+     * |        |          |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * @var WDT_T::ALTCTL
+     * Offset: 0x04  WDT Alternative Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[1:0]   |RSTDSEL   |WDT Reset Delay Period Selection (Write Protect)
+     * |        |          |When WDT time-out event happened, user has a time named WDT Reset Delay Period to clear execute WDT counter by setting RSTCNT (WDT_CTL[0]) reset to prevent WDT time-out reset system occurred happened
+     * |        |          |User can select a suitable setting of RSTDSEL for different application program WDT Reset Delay Period.
+     * |        |          |00 = WDT Reset Delay Period is 1026 * WDT_CLK.
+     * |        |          |01 = WDT Reset Delay Period is 130 * WDT_CLK.
+     * |        |          |10 = WDT Reset Delay Period is 18 * WDT_CLK.
+     * |        |          |11 = WDT Reset Delay Period is 3 * WDT_CLK.
+     * |        |          |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
+     * |        |          |Note2: This register will be reset to 0 if WDT time-out reset system event occurred happened.
+     * @var WDT_T::RSTCNT
+     * Offset: 0x08  WDT Reset Counter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |RSTCNT    |WDT Reset Counter Register
+     * |        |          |Writing 0x00005AA5 to this register field will reset the internal 18-bit WDT up counter value to 0.
+     * |        |          |Note: This WDT_RSTCNT is not write protected, but this RSTCNT (WDT_CTL[0]) is write protected.
+     * |        |          |Note: Perform RSTCNT to reset counter needs 2 * WDT_CLK period to become active.
+     */
+    __IO uint32_t CTL;                   /*!< [0x0000] WDT Control Register                                             */
+    __IO uint32_t ALTCTL;                /*!< [0x0004] WDT Alternative Control Register                                 */
+    __O  uint32_t RSTCNT;                /*!< [0x0008] WDT Reset Counter Register                                       */
+
+} WDT_T;
+
+/**
+    @addtogroup WDT_CONST WDT Bit Field Definition
+    Constant Definitions for WDT Controller
+  @{
+*/
+
+#define WDT_CTL_RSTEN_Pos                (1)                                               /*!< WDT_T::CTL: RSTEN Position             */
+#define WDT_CTL_RSTEN_Msk                (0x1ul << WDT_CTL_RSTEN_Pos)                      /*!< WDT_T::CTL: RSTEN Mask                 */
+
+#define WDT_CTL_RSTF_Pos                 (2)                                               /*!< WDT_T::CTL: RSTF Position              */
+#define WDT_CTL_RSTF_Msk                 (0x1ul << WDT_CTL_RSTF_Pos)                       /*!< WDT_T::CTL: RSTF Mask                  */
+
+#define WDT_CTL_IF_Pos                   (3)                                               /*!< WDT_T::CTL: IF Position                */
+#define WDT_CTL_IF_Msk                   (0x1ul << WDT_CTL_IF_Pos)                         /*!< WDT_T::CTL: IF Mask                    */
+
+#define WDT_CTL_WKEN_Pos                 (4)                                               /*!< WDT_T::CTL: WKEN Position              */
+#define WDT_CTL_WKEN_Msk                 (0x1ul << WDT_CTL_WKEN_Pos)                       /*!< WDT_T::CTL: WKEN Mask                  */
+
+#define WDT_CTL_WKF_Pos                  (5)                                               /*!< WDT_T::CTL: WKF Position               */
+#define WDT_CTL_WKF_Msk                  (0x1ul << WDT_CTL_WKF_Pos)                        /*!< WDT_T::CTL: WKF Mask                   */
+
+#define WDT_CTL_INTEN_Pos                (6)                                               /*!< WDT_T::CTL: INTEN Position             */
+#define WDT_CTL_INTEN_Msk                (0x1ul << WDT_CTL_INTEN_Pos)                      /*!< WDT_T::CTL: INTEN Mask                 */
+
+#define WDT_CTL_WDTEN_Pos                (7)                                               /*!< WDT_T::CTL: WDTEN Position             */
+#define WDT_CTL_WDTEN_Msk                (0x1ul << WDT_CTL_WDTEN_Pos)                      /*!< WDT_T::CTL: WDTEN Mask                 */
+
+#define WDT_CTL_TOUTSEL_Pos              (8)                                               /*!< WDT_T::CTL: TOUTSEL Position           */
+#define WDT_CTL_TOUTSEL_Msk              (0xful << WDT_CTL_TOUTSEL_Pos)                    /*!< WDT_T::CTL: TOUTSEL Mask               */
+
+#define WDT_CTL_SYNC_Pos                 (30)                                              /*!< WDT_T::CTL: SYNC Position              */
+#define WDT_CTL_SYNC_Msk                 (0x1ul << WDT_CTL_SYNC_Pos)                       /*!< WDT_T::CTL: SYNC Mask                  */
+
+#define WDT_CTL_ICEDEBUG_Pos             (31)                                              /*!< WDT_T::CTL: ICEDEBUG Position          */
+#define WDT_CTL_ICEDEBUG_Msk             (0x1ul << WDT_CTL_ICEDEBUG_Pos)                   /*!< WDT_T::CTL: ICEDEBUG Mask              */
+
+#define WDT_ALTCTL_RSTDSEL_Pos           (0)                                               /*!< WDT_T::ALTCTL: RSTDSEL Position        */
+#define WDT_ALTCTL_RSTDSEL_Msk           (0x3ul << WDT_ALTCTL_RSTDSEL_Pos)                 /*!< WDT_T::ALTCTL: RSTDSEL Mask            */
+
+#define WDT_RSTCNT_RSTCNT_Pos            (0)                                               /*!< WDT_T::RSTCNT: RSTCNT Position         */
+#define WDT_RSTCNT_RSTCNT_Msk            (0xfffffffful << WDT_RSTCNT_RSTCNT_Pos)           /*!< WDT_T::RSTCNT: RSTCNT Mask             */
+
+
+/**@}*/ /* WDT_CONST */
+/**@}*/ /* end of WDT register group */
+/**@}*/ /* end of REGISTER group */
+
+#endif /* __WDT_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/wwdt_reg.h b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/wwdt_reg.h
new file mode 100644
index 0000000000..048fea14c1
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Include/wwdt_reg.h
@@ -0,0 +1,148 @@
+/**************************************************************************//**
+ * @file     wwdt_reg.h
+ * @version  V1.00
+ * @brief    WWDT register definition header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __WWDT_REG_H__
+#define __WWDT_REG_H__
+
+/** @addtogroup REGISTER Control Register
+
+  @{
+
+*/
+
+
+/*---------------------- Window Watchdog Timer -------------------------*/
+/**
+    @addtogroup WWDT Window Watchdog Timer(WWDT)
+    Memory Mapped Structure for WWDT Controller
+  @{
+*/
+
+typedef struct
+{
+
+
+    /**
+     * @var WWDT_T::RLDCNT
+     * Offset: 0x00  WWDT Reload Counter Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[31:0]  |RLDCNT    |WWDT Reload Counter Register
+     * |        |          |Writing only 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.
+     * |        |          |Note1: User can only write execute WWDT_RLDCNT register to the reload WWDT counter value command when current current WWDT counter value CNTDAT (WWDT_CNT[5:0]) is between 10 and CMPDAT (WWDT_CTL[21:16])
+     * |        |          |If user writes 0x00005AA5 in WWDT_RLDCNT register when current current CNTDATWWDT counter value is larger than CMPDAT, WWDT reset signal system event will be generated immediately.
+     * |        |          |Note2: Execute WWDT counter reload always needs (WWDT_CLK *3) period to reload CNTDAT to 0x3F and internal prescale counter will be reset also.
+     * @var WWDT_T::CTL
+     * Offset: 0x04  WWDT Control Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WWDTEN    |WWDT Enable Control Bit
+     * |        |          |Set this bit to enable start WWDT counter counting.
+     * |        |          |0 = WWDT counter is stopped.
+     * |        |          |1 = WWDT counter is starting counting.
+     * |[1]     |INTEN     |WWDT Interrupt Enable Control Bit
+     * |        |          |If this bit is enabled, when WWDTIF (WWDT_STATUS[0]) is set to 1, the WWDT counter compare match interrupt signal is generated and inform to CPU.
+     * |        |          |0 = WWDT counter compare match interrupt Disabled.
+     * |        |          |1 = WWDT counter compare match interrupt Enabled.
+     * |[11:8]  |PSCSEL    |WWDT Counter Prescale Period Selection
+     * |        |          |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK.
+     * |        |          |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK.
+     * |        |          |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK.
+     * |        |          |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK.
+     * |        |          |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK.
+     * |        |          |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK.
+     * |        |          |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK.
+     * |        |          |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK.
+     * |        |          |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK.
+     * |        |          |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK.
+     * |        |          |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK.
+     * |        |          |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK.
+     * |        |          |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK.
+     * |        |          |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK.
+     * |        |          |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK.
+     * |        |          |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK.
+     * |[21:16] |CMPDAT    |WWDT Window Compare Register Value
+     * |        |          |Set this register field to adjust the valid reload window interval when WWDTIF (WWDT_STATUS[0]) is generated..
+     * |        |          |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT CNTDAT (WWDT_CNT[5:]) is counter value between 10 and CMPDAT
+     * |        |          |If user writes 0x00005AA5 in WWDT_RLDCNT register when current WWDT counter value CNTDAT is larger than CMPDAT, WWDT reset system event signal will be generated immediately.
+     * |[31]    |ICEDEBUG  |ICE Debug Mode Acknowledge Disable Control
+     * |        |          |0 = ICE debug mode acknowledgment effects WWDT counter counting.
+     * |        |          |WWDT down counter will be held while CPU is held by ICE.
+     * |        |          |1 = ICE debug mode acknowledgment Disabled.
+     * |        |          |WWDT down counter will keep going counting no matter CPU is held by ICE or not.
+     * @var WWDT_T::STATUS
+     * Offset: 0x08  WWDT Status Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[0]     |WWDTIF    |WWDT Compare Match Interrupt Flag
+     * |        |          |This bit indicates the that current CNTDAT (WWDT_CNT[5:0]) matches the CMPDAT (WWDT_CTL[21:16])interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).
+     * |        |          |0 = No effect.
+     * |        |          |1 = WWDT WWDT CNTDAT counter value matches the CMPDAT.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * |[1]     |WWDTRF    |WWDT Timer-out Reset System Flag
+     * |        |          |If this bit is set to 1, it This bit indicates the that system has been reset by WWDT counter time-out reset system event.or not.
+     * |        |          |0 = WWDT time-out reset system event did not occur.
+     * |        |          |1 = WWDT time-out reset system event occurred.
+     * |        |          |Note: This bit is cleared by writing 1 to it.
+     * @var WWDT_T::CNT
+     * Offset: 0x0C  WWDT Counter Value Register
+     * ---------------------------------------------------------------------------------------------------
+     * |Bits    |Field     |Descriptions
+     * | :----: | :----:   | :---- |
+     * |[5:0]   |CNTDAT    |WWDT Counter Value
+     * |        |          |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value.
+     */
+    __O  uint32_t RLDCNT;                /*!< [0x0000] WWDT Reload Counter Register                                     */
+    __IO uint32_t CTL;                   /*!< [0x0004] WWDT Control Register                                            */
+    __IO uint32_t STATUS;                /*!< [0x0008] WWDT Status Register                                             */
+    __I  uint32_t CNT;                   /*!< [0x000c] WWDT Counter Value Register                                      */
+
+} WWDT_T;
+
+
+/**
+    @addtogroup WWDT_CONST WWDT Bit Field Definition
+    Constant Definitions for WWDT Controller
+  @{
+*/
+
+#define WWDT_RLDCNT_RLDCNT_Pos           (0)                                               /*!< WWDT_T::RLDCNT: RLDCNT Position        */
+#define WWDT_RLDCNT_RLDCNT_Msk           (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos)          /*!< WWDT_T::RLDCNT: RLDCNT Mask            */
+
+#define WWDT_CTL_WWDTEN_Pos              (0)                                               /*!< WWDT_T::CTL: WWDTEN Position           */
+#define WWDT_CTL_WWDTEN_Msk              (0x1ul << WWDT_CTL_WWDTEN_Pos)                    /*!< WWDT_T::CTL: WWDTEN Mask               */
+
+#define WWDT_CTL_INTEN_Pos               (1)                                               /*!< WWDT_T::CTL: INTEN Position            */
+#define WWDT_CTL_INTEN_Msk               (0x1ul << WWDT_CTL_INTEN_Pos)                     /*!< WWDT_T::CTL: INTEN Mask                */
+
+#define WWDT_CTL_PSCSEL_Pos              (8)                                               /*!< WWDT_T::CTL: PSCSEL Position           */
+#define WWDT_CTL_PSCSEL_Msk              (0xful << WWDT_CTL_PSCSEL_Pos)                    /*!< WWDT_T::CTL: PSCSEL Mask               */
+
+#define WWDT_CTL_CMPDAT_Pos              (16)                                              /*!< WWDT_T::CTL: CMPDAT Position           */
+#define WWDT_CTL_CMPDAT_Msk              (0x3ful << WWDT_CTL_CMPDAT_Pos)                   /*!< WWDT_T::CTL: CMPDAT Mask               */
+
+#define WWDT_CTL_ICEDEBUG_Pos            (31)                                              /*!< WWDT_T::CTL: ICEDEBUG Position         */
+#define WWDT_CTL_ICEDEBUG_Msk            (0x1ul << WWDT_CTL_ICEDEBUG_Pos)                  /*!< WWDT_T::CTL: ICEDEBUG Mask             */
+
+#define WWDT_STATUS_WWDTIF_Pos           (0)                                               /*!< WWDT_T::STATUS: WWDTIF Position        */
+#define WWDT_STATUS_WWDTIF_Msk           (0x1ul << WWDT_STATUS_WWDTIF_Pos)                 /*!< WWDT_T::STATUS: WWDTIF Mask            */
+
+#define WWDT_STATUS_WWDTRF_Pos           (1)                                               /*!< WWDT_T::STATUS: WWDTRF Position        */
+#define WWDT_STATUS_WWDTRF_Msk           (0x1ul << WWDT_STATUS_WWDTRF_Pos)                 /*!< WWDT_T::STATUS: WWDTRF Mask            */
+
+#define WWDT_CNT_CNTDAT_Pos              (0)                                               /*!< WWDT_T::CNT: CNTDAT Position           */
+#define WWDT_CNT_CNTDAT_Msk              (0x3ful << WWDT_CNT_CNTDAT_Pos)                   /*!< WWDT_T::CNT: CNTDAT Mask               */
+
+/**@}*/ /* WWDT_CONST */
+/**@}*/ /* end of WWDT register group */
+/**@}*/ /* end of REGISTER group */
+
+#endif /* __WWDT_REG_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Source/ARM/startup_M2354.s b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Source/ARM/startup_M2354.s
new file mode 100644
index 0000000000..bc8c118296
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Source/ARM/startup_M2354.s
@@ -0,0 +1,582 @@
+;/**************************************************************************//**
+; * @file     startup_M2354.s
+; * @version  V2.00
+; * $Revision: 9 $
+; * $Date: 16/08/27 12:33p $ 
+; * @brief   Startup Source File
+; *
+; * @note
+; * SPDX-License-Identifier: Apache-2.0
+; * Copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+; *
+; ******************************************************************************/
+		
+		
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+    IF :LNOT: :DEF: Stack_Size
+Stack_Size      EQU     0x00002000
+    ENDIF
+
+                AREA    |.STACK|, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+    IF :LNOT: :DEF: Heap_Size
+Heap_Size       EQU     0x00001000
+    ENDIF
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  g_pfnVectors
+                EXPORT  g_pfnVectors_End
+                EXPORT  g_pfnVectors_Size
+;Wayne			IMPORT  SendChar_ToUART
+                IMPORT  SCU_IRQHandler
+
+g_pfnVectors    DCD     __initial_sp               ;     Top of Stack
+                DCD     Reset_Handler              ;     Reset Handler
+                DCD     NMI_Handler                ;     NMI Handler
+                DCD     HardFault_Handler          ;     Hard Fault Handler
+                DCD     0                          ;     Reserved
+                DCD     0                          ;     Reserved
+                DCD     0                          ;     Reserved
+                DCD     0                          ;     Reserved
+                DCD     0                          ;     Reserved
+                DCD     0                          ;     Reserved
+                DCD     0                          ;     Reserved
+                DCD     SVC_Handler                ;     SVCall Handler
+                DCD     0                          ;     Reserved
+                DCD     0                          ;     Reserved
+                DCD     PendSV_Handler             ;     PendSV Handler
+                DCD     SysTick_Handler            ;     SysTick Handler
+
+                ; External Interrupts
+                                                   ; maximum of 32 External Interrupts are possible
+                DCD     BOD_IRQHandler		       ; 0  
+                DCD     IRC_IRQHandler             ; 1  
+                DCD     PWRWU_IRQHandler           ; 2  
+                DCD     SRAM_IRQHandler            ; 3  
+                DCD     CLKFAIL_IRQHandler         ; 4  
+                DCD     DEFAULT_IRQHandler         ; 5  
+                DCD     RTC_IRQHandler             ; 6  
+                DCD     RTC_TAMPER_IRQHandler      ; 7  
+                DCD     WDT_IRQHandler             ; 8  
+                DCD     WWDT_IRQHandler            ; 9  
+                DCD     EINT0_IRQHandler           ; 10 
+                DCD     EINT1_IRQHandler           ; 11 
+                DCD     EINT2_IRQHandler           ; 12 
+                DCD     EINT3_IRQHandler           ; 13 
+                DCD     EINT4_IRQHandler           ; 14 
+                DCD     EINT5_IRQHandler           ; 15 
+                DCD     GPA_IRQHandler             ; 16 
+                DCD     GPB_IRQHandler             ; 17 
+                DCD     GPC_IRQHandler             ; 18 
+                DCD     GPD_IRQHandler             ; 19 
+                DCD     GPE_IRQHandler             ; 20 
+                DCD     GPF_IRQHandler             ; 21 
+                DCD     QSPI0_IRQHandler           ; 22 
+                DCD     SPI0_IRQHandler            ; 23 
+                DCD     BRAKE0_IRQHandler          ; 24 
+                DCD     EPWM0_P0_IRQHandler        ; 25 
+                DCD     EPWM0_P1_IRQHandler        ; 26 
+                DCD     EPWM0_P2_IRQHandler        ; 27 
+                DCD     BRAKE1_IRQHandler          ; 28 
+                DCD     EPWM1_P0_IRQHandler        ; 29 
+                DCD     EPWM1_P1_IRQHandler        ; 30 
+                DCD     EPWM1_P2_IRQHandler        ; 31 
+                DCD     TMR0_IRQHandler            ; 32 
+                DCD     TMR1_IRQHandler            ; 33 
+                DCD     TMR2_IRQHandler            ; 34 
+                DCD     TMR3_IRQHandler            ; 35 
+                DCD     UART0_IRQHandler           ; 36 
+                DCD     UART1_IRQHandler           ; 37 
+                DCD     I2C0_IRQHandler            ; 38 
+                DCD     I2C1_IRQHandler            ; 39 
+                DCD     PDMA0_IRQHandler           ; 40 
+                DCD     DAC_IRQHandler             ; 41 
+                DCD     EADC0_IRQHandler           ; 42 
+                DCD     EADC1_IRQHandler           ; 43 
+                DCD     ACMP01_IRQHandler          ; 44 
+                DCD     DEFAULT_IRQHandler         ; 45 
+                DCD     EADC2_IRQHandler           ; 46 
+                DCD     EADC3_IRQHandler           ; 47 
+                DCD     UART2_IRQHandler           ; 48 
+                DCD     UART3_IRQHandler           ; 49 
+                DCD     DEFAULT_IRQHandler         ; 50 
+                DCD     SPI1_IRQHandler            ; 51 
+                DCD     SPI2_IRQHandler            ; 52 
+                DCD     USBD_IRQHandler            ; 53 
+                DCD     USBH_IRQHandler            ; 54 
+                DCD     USBOTG_IRQHandler          ; 55 
+                DCD     CAN0_IRQHandler            ; 56 
+                DCD     DEFAULT_IRQHandler         ; 57 
+                DCD     SC0_IRQHandler             ; 58 
+                DCD     SC1_IRQHandler             ; 59 
+                DCD     SC2_IRQHandler             ; 60 
+                DCD     DEFAULT_IRQHandler         ; 61 
+                DCD     SPI3_IRQHandler            ; 62 
+                DCD     DEFAULT_IRQHandler         ; 63 
+                DCD     SDH0_IRQHandler            ; 64 
+                DCD     DEFAULT_IRQHandler         ; 65 
+                DCD     DEFAULT_IRQHandler         ; 66 
+                DCD     DEFAULT_IRQHandler         ; 67 
+                DCD     I2S0_IRQHandler            ; 68 
+                DCD     DEFAULT_IRQHandler         ; 69 
+                DCD     OPA0_IRQHandler            ; 70 
+                DCD     CRPT_IRQHandler            ; 71 
+                DCD     GPG_IRQHandler             ; 72 
+                DCD     EINT6_IRQHandler           ; 73 
+                DCD     UART4_IRQHandler           ; 74 
+                DCD     UART5_IRQHandler           ; 75 
+                DCD     USCI0_IRQHandler           ; 76 
+                DCD     USCI1_IRQHandler           ; 77 
+                DCD     BPWM0_IRQHandler           ; 78 
+                DCD     BPWM1_IRQHandler           ; 79 
+                DCD     DEFAULT_IRQHandler         ; 80 
+                DCD     DEFAULT_IRQHandler         ; 81 
+                DCD     I2C2_IRQHandler            ; 82 
+                DCD     DEFAULT_IRQHandler         ; 83 
+                DCD     QEI0_IRQHandler            ; 84 
+                DCD     QEI1_IRQHandler            ; 85 
+                DCD     ECAP0_IRQHandler           ; 86 
+                DCD     ECAP1_IRQHandler           ; 87 
+                DCD     GPH_IRQHandler             ; 88 
+                DCD     EINT7_IRQHandler           ; 89 
+                DCD     DEFAULT_IRQHandler         ; 90 
+                DCD     DEFAULT_IRQHandler         ; 91 
+                DCD     DEFAULT_IRQHandler         ; 92 
+                DCD     DEFAULT_IRQHandler         ; 93 
+                DCD     DEFAULT_IRQHandler         ; 94 
+                DCD     DEFAULT_IRQHandler         ; 95 
+                DCD     DEFAULT_IRQHandler         ; 96 
+                DCD     DEFAULT_IRQHandler         ; 97 
+                DCD     PDMA1_IRQHandler           ; 98 
+                DCD     SCU_IRQHandler             ; 99 
+                DCD     LCD_IRQHandler             ; 100
+                DCD     TRNG_IRQHandler            ; 101
+                DCD     DEFAULT_IRQHandler         ; 102
+                DCD     DEFAULT_IRQHandler         ; 103
+                DCD     DEFAULT_IRQHandler         ; 104
+                DCD     DEFAULT_IRQHandler         ; 105
+                DCD     DEFAULT_IRQHandler         ; 106
+                DCD     DEFAULT_IRQHandler         ; 107
+                DCD     DEFAULT_IRQHandler         ; 108
+                DCD     KS_IRQHandler              ; 109
+                DCD     TAMPER_IRQHandler          ; 110
+                DCD     EWDT_IRQHandler            ; 111
+                DCD     EWWDT_IRQHandler           ; 112
+                DCD     NS_ISP_IRQHandler          ; 113
+                DCD     TMR4_IRQHandler            ; 114
+                DCD     TMR5_IRQHandler            ; 115
+					
+                                                     
+g_pfnVectors_End
+
+g_pfnVectors_Size  EQU     g_pfnVectors_End - g_pfnVectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+
+                MOV     R0, R15
+                LSLS    R0, R0, #3
+                BMI     GotoSystemInit
+
+                LDR     R0, =0x40000100
+                LDR     R1, =0x59
+                STR     R1, [R0]
+                LDR     R1, =0x16
+                STR     R1, [R0]
+                LDR     R1, =0x88
+                STR     R1, [R0]
+
+                LDR     R0, =0x400001f4
+                LDR     R1, =0xffffffff
+                STR     R1, [R0]
+
+                LDR     R0, =0x400000dC
+                LDR     R1, =0x0
+                STR     R1, [R0]
+
+                LDR     R0, =0x40000200
+                LDR     R1, [R0,#0x4]
+
+                LDR     R2, =0xfff02000
+
+                ORRS    R1, R1, R2
+                STR     R1, [R0,#0x4]
+
+GotoSystemInit
+
+                LDR     R0, =0x40000100
+                MOVS    R1, #0
+                STR     R1, [R0]
+
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+ProcessHardFaultx\
+                PROC
+                EXPORT  ProcessHardFaultx          [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  BOD_IRQHandler		      [WEAK] ; 0  
+                EXPORT  IRC_IRQHandler            [WEAK] ; 1  
+                EXPORT  PWRWU_IRQHandler          [WEAK] ; 2  
+                EXPORT  SRAM_IRQHandler           [WEAK] ; 3  
+                EXPORT  CLKFAIL_IRQHandler        [WEAK] ; 4  
+               ;EXPORT  0                         [WEAK] ; 5  
+                EXPORT  RTC_IRQHandler            [WEAK] ; 6  
+                EXPORT  RTC_TAMPER_IRQHandler     [WEAK] ; 7  
+                EXPORT  WDT_IRQHandler            [WEAK] ; 8  
+                EXPORT  WWDT_IRQHandler           [WEAK] ; 9  
+                EXPORT  EINT0_IRQHandler          [WEAK] ; 10 
+                EXPORT  EINT1_IRQHandler          [WEAK] ; 11 
+                EXPORT  EINT2_IRQHandler          [WEAK] ; 12 
+                EXPORT  EINT3_IRQHandler          [WEAK] ; 13 
+                EXPORT  EINT4_IRQHandler          [WEAK] ; 14 
+                EXPORT  EINT5_IRQHandler          [WEAK] ; 15 
+                EXPORT  GPA_IRQHandler            [WEAK] ; 16 
+                EXPORT  GPB_IRQHandler            [WEAK] ; 17 
+                EXPORT  GPC_IRQHandler            [WEAK] ; 18 
+                EXPORT  GPD_IRQHandler            [WEAK] ; 19 
+                EXPORT  GPE_IRQHandler            [WEAK] ; 20 
+                EXPORT  GPF_IRQHandler            [WEAK] ; 21 
+                EXPORT  QSPI0_IRQHandler          [WEAK] ; 22 
+                EXPORT  SPI0_IRQHandler           [WEAK] ; 23 
+                EXPORT  BRAKE0_IRQHandler         [WEAK] ; 24 
+                EXPORT  EPWM0_P0_IRQHandler       [WEAK] ; 25 
+                EXPORT  EPWM0_P1_IRQHandler       [WEAK] ; 26 
+                EXPORT  EPWM0_P2_IRQHandler       [WEAK] ; 27 
+                EXPORT  BRAKE1_IRQHandler         [WEAK] ; 28 
+                EXPORT  EPWM1_P0_IRQHandler       [WEAK] ; 29 
+                EXPORT  EPWM1_P1_IRQHandler       [WEAK] ; 30 
+                EXPORT  EPWM1_P2_IRQHandler       [WEAK] ; 31 
+                EXPORT  TMR0_IRQHandler           [WEAK] ; 32 
+                EXPORT  TMR1_IRQHandler           [WEAK] ; 33 
+                EXPORT  TMR2_IRQHandler           [WEAK] ; 34 
+                EXPORT  TMR3_IRQHandler           [WEAK] ; 35 
+                EXPORT  UART0_IRQHandler          [WEAK] ; 36 
+                EXPORT  UART1_IRQHandler          [WEAK] ; 37 
+                EXPORT  I2C0_IRQHandler           [WEAK] ; 38 
+                EXPORT  I2C1_IRQHandler           [WEAK] ; 39 
+                EXPORT  PDMA0_IRQHandler          [WEAK] ; 40 
+                EXPORT  DAC_IRQHandler            [WEAK] ; 41 
+                EXPORT  EADC0_IRQHandler          [WEAK] ; 42 
+                EXPORT  EADC1_IRQHandler          [WEAK] ; 43 
+                EXPORT  ACMP01_IRQHandler         [WEAK] ; 44 
+               ;EXPORT  0                         [WEAK] ; 45 
+                EXPORT  EADC2_IRQHandler          [WEAK] ; 46 
+                EXPORT  EADC3_IRQHandler          [WEAK] ; 47 
+                EXPORT  UART2_IRQHandler          [WEAK] ; 48 
+                EXPORT  UART3_IRQHandler          [WEAK] ; 49 
+               ;EXPORT  0                         [WEAK] ; 50 
+                EXPORT  SPI1_IRQHandler           [WEAK] ; 51 
+                EXPORT  SPI2_IRQHandler           [WEAK] ; 52 
+                EXPORT  USBD_IRQHandler           [WEAK] ; 53 
+                EXPORT  USBH_IRQHandler           [WEAK] ; 54 
+                EXPORT  USBOTG_IRQHandler         [WEAK] ; 55 
+                EXPORT  CAN0_IRQHandler           [WEAK] ; 56 
+                EXPORT  CAN1_IRQHandler           [WEAK] ; 57 
+                EXPORT  SC0_IRQHandler            [WEAK] ; 58 
+                EXPORT  SC1_IRQHandler            [WEAK] ; 59 
+                EXPORT  SC2_IRQHandler            [WEAK] ; 60 
+                EXPORT  SC3_IRQHandler            [WEAK] ; 61 
+                EXPORT  SPI3_IRQHandler           [WEAK] ; 62 
+               ;EXPORT  0                         [WEAK] ; 63 
+                EXPORT  SDH0_IRQHandler           [WEAK] ; 64 
+               ;EXPORT  0                         [WEAK] ; 65 
+               ;EXPORT  0                         [WEAK] ; 66 
+               ;EXPORT  0                         [WEAK] ; 67 
+                EXPORT  I2S0_IRQHandler           [WEAK] ; 68 
+               ;EXPORT  0                         [WEAK] ; 69 
+                EXPORT  OPA0_IRQHandler           [WEAK] ; 70 
+                EXPORT  CRPT_IRQHandler           [WEAK] ; 71 
+                EXPORT  GPG_IRQHandler            [WEAK] ; 72 
+                EXPORT  EINT6_IRQHandler          [WEAK] ; 73 
+                EXPORT  UART4_IRQHandler          [WEAK] ; 74 
+                EXPORT  UART5_IRQHandler          [WEAK] ; 75 
+                EXPORT  USCI0_IRQHandler          [WEAK] ; 76 
+                EXPORT  USCI1_IRQHandler          [WEAK] ; 77 
+                EXPORT  BPWM0_IRQHandler          [WEAK] ; 78 
+                EXPORT  BPWM1_IRQHandler          [WEAK] ; 79 
+               ;EXPORT  0                         [WEAK] ; 80 
+               ;EXPORT  0                         [WEAK] ; 81 
+                EXPORT  I2C2_IRQHandler           [WEAK] ; 82 
+               ;EXPORT  0                         [WEAK] ; 83 
+                EXPORT  QEI0_IRQHandler           [WEAK] ; 84 
+                EXPORT  QEI1_IRQHandler           [WEAK] ; 85 
+                EXPORT  ECAP0_IRQHandler          [WEAK] ; 86 
+                EXPORT  ECAP1_IRQHandler          [WEAK] ; 87 
+                EXPORT  GPH_IRQHandler            [WEAK] ; 88 
+                EXPORT   EINT7_IRQHandler          [WEAK] ; 89 
+                EXPORT  SDH1_IRQHandler           [WEAK] ; 90 
+               ;EXPORT  0                         [WEAK] ; 91 
+               ;EXPORT  USBH_IRQHandler           [WEAK] ; 92 
+               ;EXPORT  0                         [WEAK] ; 93 
+               ;EXPORT  0                         [WEAK] ; 94 
+               ;EXPORT  0                         [WEAK] ; 95 
+               ;EXPORT  0                         [WEAK] ; 96 
+               ;EXPORT  0                         [WEAK] ; 97 
+                EXPORT  PDMA1_IRQHandler          [WEAK] ; 98 
+               ;EXPORT  SCU_IRQHandler            [WEAK] ; 99 
+                EXPORT  LCD_IRQHandler            [WEAK] ; 100 
+                EXPORT  TRNG_IRQHandler           [WEAK] ; 101
+               ;EXPORT  0                         [WEAK] ; 102
+               ;EXPORT  0                         [WEAK] ; 103
+               ;EXPORT  0                         [WEAK] ; 104
+               ;EXPORT  0                         [WEAK] ; 105
+               ;EXPORT  0                         [WEAK] ; 106
+               ;EXPORT  0                         [WEAK] ; 107
+               ;EXPORT  0                         [WEAK] ; 108
+                EXPORT  KS_IRQHandler             [WEAK] ; 109
+                EXPORT  TAMPER_IRQHandler         [WEAK] ; 110
+                EXPORT  EWDT_IRQHandler           [WEAK] ; 111
+                EXPORT  EWWDT_IRQHandler          [WEAK] ; 112
+                EXPORT  NS_ISP_IRQHandler         [WEAK] ; 113
+                EXPORT  TMR4_IRQHandler           [WEAK] ; 114 
+                EXPORT  TMR5_IRQHandler           [WEAK] ; 115 
+
+
+                EXPORT	DEFAULT_IRQHandler		  [WEAK]                                                
+                                                                
+BOD_IRQHandler		       ; 0  
+IRC_IRQHandler             ; 1  
+PWRWU_IRQHandler           ; 2  
+SRAM_IRQHandler            ; 3  
+CLKFAIL_IRQHandler         ; 4  
+;0                          ; 5  
+RTC_IRQHandler             ; 6  
+RTC_TAMPER_IRQHandler      ; 7  
+WDT_IRQHandler             ; 8  
+WWDT_IRQHandler            ; 9  
+EINT0_IRQHandler           ; 10 
+EINT1_IRQHandler           ; 11 
+EINT2_IRQHandler           ; 12 
+EINT3_IRQHandler           ; 13 
+EINT4_IRQHandler           ; 14 
+EINT5_IRQHandler           ; 15 
+GPA_IRQHandler             ; 16 
+GPB_IRQHandler             ; 17 
+GPC_IRQHandler             ; 18 
+GPD_IRQHandler             ; 19 
+GPE_IRQHandler             ; 20 
+GPF_IRQHandler             ; 21 
+QSPI0_IRQHandler           ; 22 
+SPI0_IRQHandler            ; 23 
+BRAKE0_IRQHandler          ; 24 
+EPWM0_P0_IRQHandler        ; 25 
+EPWM0_P1_IRQHandler        ; 26 
+EPWM0_P2_IRQHandler        ; 27 
+BRAKE1_IRQHandler          ; 28 
+EPWM1_P0_IRQHandler        ; 29 
+EPWM1_P1_IRQHandler        ; 30 
+EPWM1_P2_IRQHandler        ; 31 
+TMR0_IRQHandler            ; 32 
+TMR1_IRQHandler            ; 33 
+TMR2_IRQHandler            ; 34 
+TMR3_IRQHandler            ; 35 
+UART0_IRQHandler           ; 36 
+UART1_IRQHandler           ; 37 
+I2C0_IRQHandler            ; 38 
+I2C1_IRQHandler            ; 39 
+PDMA0_IRQHandler           ; 40 
+DAC_IRQHandler             ; 41 
+EADC0_IRQHandler           ; 42 
+EADC1_IRQHandler           ; 43 
+ACMP01_IRQHandler          ; 44 
+;0                          ; 45 
+EADC2_IRQHandler           ; 46 
+EADC3_IRQHandler           ; 47 
+UART2_IRQHandler           ; 48 
+UART3_IRQHandler           ; 49 
+;0                          ; 50 
+SPI1_IRQHandler            ; 51 
+SPI2_IRQHandler            ; 52 
+USBD_IRQHandler            ; 53 
+USBH_IRQHandler            ; 54 
+USBOTG_IRQHandler          ; 55 
+CAN0_IRQHandler            ; 56 
+CAN1_IRQHandler            ; 57 
+SC0_IRQHandler             ; 58 
+SC1_IRQHandler             ; 59 
+SC2_IRQHandler             ; 60 
+SC3_IRQHandler             ; 61 
+SPI3_IRQHandler            ; 62 
+;0                          ; 63 
+SDH0_IRQHandler            ; 64 
+;0                          ; 65 
+;0                          ; 66 
+;0                          ; 67 
+I2S0_IRQHandler            ; 68 
+;0                          ; 69 
+OPA0_IRQHandler            ; 70 
+CRPT_IRQHandler            ; 71 
+GPG_IRQHandler             ; 72 
+EINT6_IRQHandler           ; 73 
+UART4_IRQHandler           ; 74 
+UART5_IRQHandler           ; 75 
+USCI0_IRQHandler           ; 76 
+USCI1_IRQHandler           ; 77 
+BPWM0_IRQHandler           ; 78 
+BPWM1_IRQHandler           ; 79 
+;0                          ; 80 
+;0                          ; 81 
+I2C2_IRQHandler            ; 82 
+;0                          ; 83 
+QEI0_IRQHandler            ; 84 
+QEI1_IRQHandler            ; 85 
+ECAP0_IRQHandler           ; 86 
+ECAP1_IRQHandler           ; 87 
+GPH_IRQHandler             ; 88 
+EINT7_IRQHandler           ; 89 
+SDH1_IRQHandler            ; 90 
+;0                          ; 91 
+;USBH_IRQHandler            ; 92 
+;0                          ; 93 
+;0                          ; 94 
+;0                          ; 95 
+;0                          ; 96 
+;0                          ; 97 
+PDMA1_IRQHandler           ; 98 
+;SCU_IRQHandler            ; 99 
+LCD_IRQHandler             ; 100 
+TRNG_IRQHandler            ; 101
+;0                         ; 102
+;0                         ; 103
+;0                         ; 104
+;0                         ; 105
+;0                         ; 106
+;0                         ; 107
+;0                         ; 108
+KS_IRQHandler              ; 109
+TAMPER_IRQHandler          ; 110
+EWDT_IRQHandler            ; 111
+EWWDT_IRQHandler           ; 112
+NS_ISP_IRQHandler          ; 113
+TMR4_IRQHandler            ; 114 
+TMR5_IRQHandler            ; 115 
+
+DEFAULT_IRQHandler
+                B       .
+                ENDP
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap PROC
+                LDR     R0, = Heap_Mem
+                LDR     R1, = (Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+				BX      LR
+                ENDP
+
+
+                ALIGN
+
+                ENDIF
+
+
+__PC            PROC
+                EXPORT      __PC
+                
+                MOV     r0, lr
+                BLX     lr
+                ALIGN
+                    
+                ENDP
+
+SPD_Return      PROC
+                EXPORT  SPD_Return
+                
+                LDR     r0, =0x400002c0 ; SPD_VTOR
+                LDR     r1, =0x20010000    ; New VTOR
+                STR     r1, [r0]
+                MOV     r0, sp
+                STR     r0, [r1]
+                LDR     r0, =SPD_Next
+                STR     r0, [r1,#4]
+                WFI
+                B       .
+                ;LDR     SPD_Next
+SPD_Next                        
+                NOP
+                NOP
+                NOP
+                
+                ENDP
+
+
+                END
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Source/GCC/startup_M2354.S b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Source/GCC/startup_M2354.S
new file mode 100644
index 0000000000..9b27236c82
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Source/GCC/startup_M2354.S
@@ -0,0 +1,418 @@
+/****************************************************************************//**
+ * @file     startup_M2354.S
+ * @version  V1.00
+ * @brief    CMSIS Device Startup File
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2018-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+
+
+    .syntax unified
+    .arch   armv8 - m.base
+    .fpu softvfp
+    .thumb
+
+    .global g_pfnVectors
+    .global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word   _sidata
+/* start address for the .data section. defined in linker script */
+.word   _sdata
+/* end address for the .data section. defined in linker script */
+.word   _edata
+/* start address for the .bss section. defined in linker script */
+.word   _sbss
+/* end address for the .bss section. defined in linker script */
+.word   _ebss
+
+    .section .text.Reset_Handler
+    .weak Reset_Handler
+    .type Reset_Handler, %function
+
+Reset_Handler:
+
+    /* Check SecureWorld */
+    MOV     R0, R15
+    LSLS    R0, R0, #3
+    BMI.N   GotoSystemInit
+
+    /* Unlock Register */
+    LDR     R0, =0x40000100
+    LDR     R1, =0x59
+    STR     R1, [R0]
+    LDR     R1, =0x16
+    STR     R1, [R0]
+    LDR     R1, =0x88
+    STR     R1, [R0]
+
+    /* power gating */
+    /* M32(0x400001f4) = 0xfffffffful; */
+    LDR     R0, =0x400001f4
+    LDR     R1, =0xffffffff
+    STR     R1, [R0]
+
+    /* M32(0x400000dC) = 0ul; */
+    LDR     R0, =0x400000dC
+    LDR     R1, =0x0
+    STR     R1, [R0]
+
+    /* Enable GPIO clks, SRAM clks, Trace clk */
+    /* CLK->AHBCLK |= (0xffful << 20) | (1ul << 14); */
+
+    LDR     R0, =0x40000200
+    LDR     R1, [R0,#0x4]
+
+    LDR     R2, =0xfff02000
+
+    ORRS    R1, R1, R2
+    STR     R1, [R0,#0x4]
+
+GotoSystemInit:
+
+    /* Lock register */
+    LDR     R0, =0x40000100
+    MOVS    R1, #0
+    STR     R1, [R0]
+
+    /* Copy the data segment initializers from flash to SRAM */  
+    movs r1, #0
+    b LoopCopyDataInit
+
+CopyDataInit:
+    ldr r3, =_sidata
+    ldr r3, [r3, r1]
+    str r3, [r0, r1]
+    adds r1, r1, #4
+
+LoopCopyDataInit:
+    ldr r0, =_sdata
+    ldr r3, =_edata
+    adds r2, r0, r1
+    cmp r2, r3
+    bcc CopyDataInit
+    ldr r2, =_sbss
+    b LoopFillZerobss
+
+/* Zero fill the bss segment. */  
+FillZerobss:
+    movs r3, #0
+    str r3, [r2, #4]
+    adds r2, r2, #4
+
+LoopFillZerobss:
+    ldr r3, = _ebss
+    cmp r2, r3
+    bcc FillZerobss
+    /* Call the clock system intitialization function.*/
+    bl  SystemInit
+
+/* Call the application's entry point.*/
+    bl  entry
+    bx  lr
+.size Reset_Handler, .-Reset_Handler
+
+
+    .pool
+    .size   Reset_Handler, . - Reset_Handler
+
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+    b Infinite_Loop
+    .size Default_Handler, .-Default_Handler
+
+    /*    Macro to define default handlers. Default handler
+     *    will be weak symbol and just dead loops. They can be
+     *    overwritten by other handlers */
+
+    .macro  def_irq_handler handler_name
+    .weak   \handler_name
+    .set    \handler_name, Default_Handler
+    .endm
+
+    def_irq_handler NMI_Handler
+    def_irq_handler HardFault_Handler
+    def_irq_handler SVC_Handler
+    def_irq_handler PendSV_Handler
+    def_irq_handler SysTick_Handler
+
+    def_irq_handler BOD_IRQHandler
+    def_irq_handler IRC_IRQHandler
+    def_irq_handler PWRWU_IRQHandler
+    def_irq_handler SRAM_IRQHandler
+    def_irq_handler CLKFAIL_IRQHandler
+
+    def_irq_handler RTC_IRQHandler
+    def_irq_handler RTC_TAMPER_IRQHandler
+    def_irq_handler WDT_IRQHandler
+    def_irq_handler WWDT_IRQHandler
+    def_irq_handler EINT0_IRQHandler
+    def_irq_handler EINT1_IRQHandler
+    def_irq_handler EINT2_IRQHandler
+    def_irq_handler EINT3_IRQHandler
+    def_irq_handler EINT4_IRQHandler
+    def_irq_handler EINT5_IRQHandler
+    def_irq_handler GPA_IRQHandler
+    def_irq_handler GPB_IRQHandler
+    def_irq_handler GPC_IRQHandler
+    def_irq_handler GPD_IRQHandler
+    def_irq_handler GPE_IRQHandler
+    def_irq_handler GPF_IRQHandler
+    def_irq_handler QSPI0_IRQHandler
+    def_irq_handler SPI0_IRQHandler
+    def_irq_handler BRAKE0_IRQHandler
+    def_irq_handler EPWM0_P0_IRQHandler
+    def_irq_handler EPWM0_P1_IRQHandler
+    def_irq_handler EPWM0_P2_IRQHandler
+    def_irq_handler BRAKE1_IRQHandler
+    def_irq_handler EPWM1_P0_IRQHandler
+    def_irq_handler EPWM1_P1_IRQHandler
+    def_irq_handler EPWM1_P2_IRQHandler
+    def_irq_handler TMR0_IRQHandler
+    def_irq_handler TMR1_IRQHandler
+    def_irq_handler TMR2_IRQHandler
+    def_irq_handler TMR3_IRQHandler
+    def_irq_handler UART0_IRQHandler
+    def_irq_handler UART1_IRQHandler
+    def_irq_handler I2C0_IRQHandler
+    def_irq_handler I2C1_IRQHandler
+    def_irq_handler PDMA0_IRQHandler
+    def_irq_handler DAC_IRQHandler
+    def_irq_handler EADC0_IRQHandler
+    def_irq_handler EADC1_IRQHandler
+    def_irq_handler ACMP01_IRQHandler
+
+    def_irq_handler EADC2_IRQHandler
+    def_irq_handler EADC3_IRQHandler
+    def_irq_handler UART2_IRQHandler
+    def_irq_handler UART3_IRQHandler
+
+    def_irq_handler SPI1_IRQHandler
+    def_irq_handler SPI2_IRQHandler
+    def_irq_handler USBD_IRQHandler
+    def_irq_handler USBH_IRQHandler
+    def_irq_handler USBOTG_IRQHandler
+    def_irq_handler CAN0_IRQHandler
+
+    def_irq_handler SC0_IRQHandler
+    def_irq_handler SC1_IRQHandler
+    def_irq_handler SC2_IRQHandler
+
+    def_irq_handler SPI3_IRQHandler
+
+    def_irq_handler SDH0_IRQHandler
+
+
+
+    def_irq_handler I2S0_IRQHandler
+
+    def_irq_handler OPA0_IRQHandler
+    def_irq_handler CRPT_IRQHandler
+    def_irq_handler GPG_IRQHandler
+    def_irq_handler EINT6_IRQHandler
+    def_irq_handler UART4_IRQHandler
+    def_irq_handler UART5_IRQHandler
+    def_irq_handler USCI0_IRQHandler
+    def_irq_handler USCI1_IRQHandler
+    def_irq_handler BPWM0_IRQHandler
+    def_irq_handler BPWM1_IRQHandler
+
+
+    def_irq_handler I2C2_IRQHandler
+
+    def_irq_handler QEI0_IRQHandler
+    def_irq_handler QEI1_IRQHandler
+    def_irq_handler ECAP0_IRQHandler
+    def_irq_handler ECAP1_IRQHandler
+    def_irq_handler GPH_IRQHandler
+    def_irq_handler EINT7_IRQHandler
+
+
+
+
+
+
+
+
+    def_irq_handler PDMA1_IRQHandler
+    def_irq_handler SCU_IRQHandler
+    def_irq_handler LCD_IRQHandler
+    def_irq_handler TRNG_IRQHandler
+
+
+
+
+
+
+
+    def_irq_handler KS_IRQHandler
+    def_irq_handler TAMPER_IRQHandler
+    def_irq_handler EWDT_IRQHandler
+    def_irq_handler EWWDT_IRQHandler
+    def_irq_handler NS_ISP_IRQHandler   
+    def_irq_handler TMR4_IRQHandler
+    def_irq_handler TMR5_IRQHandler
+
+
+    .align  2
+    .thumb_func
+    .global __PC
+    .type   __PC, % function
+
+__PC:
+    MOV     r0, lr
+    BLX     lr
+    .size   __PC, . - __PC
+
+/*******************************************************************************
+*
+* The minimal vector table for a Cortex M23. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*******************************************************************************/
+
+  .section .isr_vector,"a",%progbits
+  .type g_pfnVectors, %object
+  .size g_pfnVectors, . - g_pfnVectors
+
+g_pfnVectors:
+    .long   _estack            /* Top of Stack */
+    .long   Reset_Handler         /* Reset Handler */
+    .long   NMI_Handler           /* NMI Handler */
+    .long   HardFault_Handler     /* Hard Fault Handler */
+    .long   0                     /* Reserved */
+    .long   0                     /* Reserved */
+    .long   0                     /* Reserved */
+    .long   0                     /* Reserved */
+    .long   0                     /* Reserved */
+    .long   0                     /* Reserved */
+    .long   0                     /* Reserved */
+    .long   SVC_Handler           /* SVCall Handler */
+    .long   0                     /* Reserved */
+    .long   0                     /* Reserved */
+    .long   PendSV_Handler        /* PendSV Handler */
+    .long   SysTick_Handler       /* SysTick Handler */
+
+    /* External interrupts */
+    .long   BOD_IRQHandler        /* 0   */
+    .long   IRC_IRQHandler        /* 1   */
+    .long   PWRWU_IRQHandler      /* 2   */
+    .long   SRAM_IRQHandler       /* 3   */
+    .long   CLKFAIL_IRQHandler    /* 4   */
+    .long   Default_Handler       /* 5   */
+    .long   RTC_IRQHandler        /* 6   */
+    .long   RTC_TAMPER_IRQHandler /* 7   */
+    .long   WDT_IRQHandler        /* 8   */
+    .long   WWDT_IRQHandler       /* 9   */
+    .long   EINT0_IRQHandler      /* 10  */
+    .long   EINT1_IRQHandler      /* 11  */
+    .long   EINT2_IRQHandler      /* 12  */
+    .long   EINT3_IRQHandler      /* 13  */
+    .long   EINT4_IRQHandler      /* 14  */
+    .long   EINT5_IRQHandler      /* 15  */
+    .long   GPA_IRQHandler        /* 16  */
+    .long   GPB_IRQHandler        /* 17  */
+    .long   GPC_IRQHandler        /* 18  */
+    .long   GPD_IRQHandler        /* 19  */
+    .long   GPE_IRQHandler        /* 20  */
+    .long   GPF_IRQHandler        /* 21  */
+    .long   QSPI0_IRQHandler      /* 22  */
+    .long   SPI0_IRQHandler       /* 23  */
+    .long   BRAKE0_IRQHandler     /* 24  */
+    .long   EPWM0_P0_IRQHandler   /* 25  */
+    .long   EPWM0_P1_IRQHandler   /* 26  */
+    .long   EPWM0_P2_IRQHandler   /* 27  */
+    .long   BRAKE1_IRQHandler     /* 28  */
+    .long   EPWM1_P0_IRQHandler   /* 29  */
+    .long   EPWM1_P1_IRQHandler   /* 30  */
+    .long   EPWM1_P2_IRQHandler   /* 31  */
+    .long   TMR0_IRQHandler       /* 32  */
+    .long   TMR1_IRQHandler       /* 33  */
+    .long   TMR2_IRQHandler       /* 34  */
+    .long   TMR3_IRQHandler       /* 35  */
+    .long   UART0_IRQHandler      /* 36  */
+    .long   UART1_IRQHandler      /* 37  */
+    .long   I2C0_IRQHandler       /* 38  */
+    .long   I2C1_IRQHandler       /* 39  */
+    .long   PDMA0_IRQHandler      /* 40  */
+    .long   DAC_IRQHandler        /* 41  */
+    .long   EADC0_IRQHandler      /* 42  */
+    .long   EADC1_IRQHandler      /* 43  */
+    .long   ACMP01_IRQHandler     /* 44  */
+    .long   Default_Handler       /* 45  */
+    .long   EADC2_IRQHandler      /* 46  */
+    .long   EADC3_IRQHandler      /* 47  */
+    .long   UART2_IRQHandler      /* 48  */
+    .long   UART3_IRQHandler      /* 49  */
+    .long   Default_Handler       /* 50  */
+    .long   SPI1_IRQHandler       /* 51  */
+    .long   SPI2_IRQHandler       /* 52  */
+    .long   USBD_IRQHandler       /* 53  */
+    .long   USBH_IRQHandler       /* 54  */
+    .long   USBOTG_IRQHandler     /* 55  */
+    .long   CAN0_IRQHandler       /* 56  */
+    .long   Default_Handler       /* 57  */
+    .long   SC0_IRQHandler        /* 58  */
+    .long   SC1_IRQHandler        /* 59  */
+    .long   SC2_IRQHandler        /* 60  */
+    .long   Default_Handler       /* 61  */
+    .long   SPI3_IRQHandler       /* 62  */
+    .long   Default_Handler       /* 63  */
+    .long   SDH0_IRQHandler       /* 64  */
+    .long   Default_Handler       /* 65  */
+    .long   Default_Handler       /* 66  */
+    .long   Default_Handler       /* 67  */
+    .long   I2S0_IRQHandler       /* 68  */
+    .long   Default_Handler       /* 69  */
+    .long   OPA0_IRQHandler       /* 70  */
+    .long   CRPT_IRQHandler       /* 71  */
+    .long   GPG_IRQHandler        /* 72  */
+    .long   EINT6_IRQHandler      /* 73  */
+    .long   UART4_IRQHandler      /* 74  */
+    .long   UART5_IRQHandler      /* 75  */
+    .long   USCI0_IRQHandler      /* 76  */
+    .long   USCI1_IRQHandler      /* 77  */
+    .long   BPWM0_IRQHandler      /* 78  */
+    .long   BPWM1_IRQHandler      /* 79  */
+    .long   Default_Handler       /* 80  */
+    .long   Default_Handler       /* 81  */
+    .long   I2C2_IRQHandler       /* 82  */
+    .long   Default_Handler       /* 83  */
+    .long   QEI0_IRQHandler       /* 84  */
+    .long   QEI1_IRQHandler       /* 85  */
+    .long   ECAP0_IRQHandler      /* 86  */
+    .long   ECAP1_IRQHandler      /* 87  */
+    .long   GPH_IRQHandler        /* 88  */
+    .long   EINT7_IRQHandler      /* 89  */
+    .long   Default_Handler       /* 90  */
+    .long   Default_Handler       /* 91  */
+    .long   Default_Handler       /* 92  */
+    .long   Default_Handler       /* 93  */
+    .long   Default_Handler       /* 94  */
+    .long   Default_Handler       /* 95  */
+    .long   Default_Handler       /* 96  */
+    .long   Default_Handler       /* 97  */
+    .long   PDMA1_IRQHandler      /* 98  */
+    .long   SCU_IRQHandler        /* 99  */
+    .long   LCD_IRQHandler        /* 100 */
+    .long   TRNG_IRQHandler       /* 101 */
+    .long   Default_Handler       /* 102 */
+    .long   Default_Handler       /* 103 */
+    .long   Default_Handler       /* 104 */
+    .long   Default_Handler       /* 105 */
+    .long   Default_Handler       /* 106 */
+    .long   Default_Handler       /* 107 */
+    .long   Default_Handler       /* 108 */
+    .long   KS_IRQHandler         /* 109 */ 
+    .long   TAMPER_IRQHandler     /* 110 */ 
+    .long   EWDT_IRQHandler       /* 111 */ 
+    .long   EWWDT_IRQHandler      /* 112 */ 
+    .long   NS_ISP_IRQHandler     /* 113 */ 
+    .long   TMR4_IRQHandler       /* 114 */ 
+    .long   TMR5_IRQHandler       /* 115 */
+
+    .end
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Source/IAR/startup_M2354.s b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Source/IAR/startup_M2354.s
new file mode 100644
index 0000000000..fe0b86da10
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Source/IAR/startup_M2354.s
@@ -0,0 +1,504 @@
+/****************************************************************************//**
+ * @file     startup_M2354.s
+ * @version  V1.00
+ * @brief    CMSIS Device Startup File
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+    MODULE  ?cstartup
+
+    ;; Forward declaration of sections.
+    SECTION CSTACK:DATA:NOROOT(3) ;; 8 bytes alignment
+
+    SECTION .intvec:CODE:NOROOT(2);; 4 bytes alignment
+
+    EXTERN  SystemInit	
+    EXTERN  __iar_program_start
+    PUBLIC  __vector_table
+    PUBLIC  g_pfnVectors
+
+    DATA
+g_pfnVectors    
+__vector_table
+    DCD     sfe(CSTACK)
+    DCD     Reset_Handler
+
+    DCD     NMI_Handler
+    DCD     HardFault_Handler
+    DCD     0
+    DCD     0
+    DCD     0
+    DCD     0
+    DCD     0
+    DCD     0
+    DCD     0
+    DCD     SVC_Handler
+    DCD     0
+    DCD     0
+    DCD     PendSV_Handler
+    DCD     SysTick_Handler
+
+    ; External Interrupts
+                                                   ; maximum of 32 External Interrupts are possible
+                DCD     BOD_IRQHandler		       ; 0  
+                DCD     IRC_IRQHandler             ; 1  
+                DCD     PWRWU_IRQHandler           ; 2  
+                DCD     SRAM_IRQHandler            ; 3  
+                DCD     CLKFAIL_IRQHandler         ; 4  
+                DCD     DEFAULT_IRQHandler         ; 5  
+                DCD     RTC_IRQHandler             ; 6  
+                DCD     RTC_TAMPER_IRQHandler      ; 7  
+                DCD     WDT_IRQHandler             ; 8  
+                DCD     WWDT_IRQHandler            ; 9  
+                DCD     EINT0_IRQHandler           ; 10 
+                DCD     EINT1_IRQHandler           ; 11 
+                DCD     EINT2_IRQHandler           ; 12 
+                DCD     EINT3_IRQHandler           ; 13 
+                DCD     EINT4_IRQHandler           ; 14 
+                DCD     EINT5_IRQHandler           ; 15 
+                DCD     GPA_IRQHandler             ; 16 
+                DCD     GPB_IRQHandler             ; 17 
+                DCD     GPC_IRQHandler             ; 18 
+                DCD     GPD_IRQHandler             ; 19 
+                DCD     GPE_IRQHandler             ; 20 
+                DCD     GPF_IRQHandler             ; 21 
+                DCD     QSPI0_IRQHandler           ; 22 
+                DCD     SPI0_IRQHandler            ; 23 
+                DCD     BRAKE0_IRQHandler          ; 24 
+                DCD     EPWM0_P0_IRQHandler        ; 25 
+                DCD     EPWM0_P1_IRQHandler        ; 26 
+                DCD     EPWM0_P2_IRQHandler        ; 27 
+                DCD     BRAKE1_IRQHandler          ; 28 
+                DCD     EPWM1_P0_IRQHandler        ; 29 
+                DCD     EPWM1_P1_IRQHandler        ; 30 
+                DCD     EPWM1_P2_IRQHandler        ; 31 
+                DCD     TMR0_IRQHandler            ; 32 
+                DCD     TMR1_IRQHandler            ; 33 
+                DCD     TMR2_IRQHandler            ; 34 
+                DCD     TMR3_IRQHandler            ; 35 
+                DCD     UART0_IRQHandler           ; 36 
+                DCD     UART1_IRQHandler           ; 37 
+                DCD     I2C0_IRQHandler            ; 38 
+                DCD     I2C1_IRQHandler            ; 39 
+                DCD     PDMA0_IRQHandler           ; 40 
+                DCD     DAC_IRQHandler             ; 41 
+                DCD     EADC0_IRQHandler           ; 42 
+                DCD     EADC1_IRQHandler           ; 43 
+                DCD     ACMP01_IRQHandler          ; 44 
+                DCD     DEFAULT_IRQHandler         ; 45 
+                DCD     EADC2_IRQHandler           ; 46 
+                DCD     EADC3_IRQHandler           ; 47 
+                DCD     UART2_IRQHandler           ; 48 
+                DCD     UART3_IRQHandler           ; 49 
+                DCD     DEFAULT_IRQHandler         ; 50 
+                DCD     SPI1_IRQHandler            ; 51 
+                DCD     SPI2_IRQHandler            ; 52 
+                DCD     USBD_IRQHandler            ; 53 
+                DCD     USBH_IRQHandler            ; 54 
+                DCD     USBOTG_IRQHandler          ; 55 
+                DCD     CAN0_IRQHandler            ; 56 
+                DCD     DEFAULT_IRQHandler         ; 57 
+                DCD     SC0_IRQHandler             ; 58 
+                DCD     SC1_IRQHandler             ; 59 
+                DCD     SC2_IRQHandler             ; 60 
+                DCD     DEFAULT_IRQHandler         ; 61 
+                DCD     SPI3_IRQHandler            ; 62 
+                DCD     DEFAULT_IRQHandler         ; 63 
+                DCD     SDH0_IRQHandler            ; 64 
+                DCD     DEFAULT_IRQHandler         ; 65 
+                DCD     DEFAULT_IRQHandler         ; 66 
+                DCD     DEFAULT_IRQHandler         ; 67 
+                DCD     I2S0_IRQHandler            ; 68 
+                DCD     DEFAULT_IRQHandler         ; 69 
+                DCD     OPA0_IRQHandler            ; 70 
+                DCD     CRPT_IRQHandler            ; 71 
+                DCD     GPG_IRQHandler             ; 72 
+                DCD     EINT6_IRQHandler           ; 73 
+                DCD     UART4_IRQHandler           ; 74 
+                DCD     UART5_IRQHandler           ; 75 
+                DCD     USCI0_IRQHandler           ; 76 
+                DCD     USCI1_IRQHandler           ; 77 
+                DCD     BPWM0_IRQHandler           ; 78 
+                DCD     BPWM1_IRQHandler           ; 79 
+                DCD     DEFAULT_IRQHandler         ; 80 
+                DCD     DEFAULT_IRQHandler         ; 81 
+                DCD     I2C2_IRQHandler            ; 82 
+                DCD     DEFAULT_IRQHandler         ; 83 
+                DCD     QEI0_IRQHandler            ; 84 
+                DCD     QEI1_IRQHandler            ; 85 
+                DCD     ECAP0_IRQHandler           ; 86 
+                DCD     ECAP1_IRQHandler           ; 87 
+                DCD     GPH_IRQHandler             ; 88 
+                DCD     EINT7_IRQHandler           ; 89 
+                DCD     SDH1_IRQHandler            ; 90 
+                DCD     DEFAULT_IRQHandler         ; 91 
+                DCD     DEFAULT_IRQHandler         ; 92 
+                DCD     DEFAULT_IRQHandler         ; 93 
+                DCD     DEFAULT_IRQHandler         ; 94 
+                DCD     DEFAULT_IRQHandler         ; 95 
+                DCD     DEFAULT_IRQHandler         ; 96 
+                DCD     DEFAULT_IRQHandler         ; 97 
+                DCD     PDMA1_IRQHandler           ; 98 
+                DCD     SCU_IRQHandler             ; 99 
+                DCD     LCD_IRQHandler             ; 100
+                DCD     TRNG_IRQHandler            ; 101
+                DCD     DEFAULT_IRQHandler         ; 102 
+                DCD     DEFAULT_IRQHandler         ; 103 
+                DCD     DEFAULT_IRQHandler         ; 104 
+                DCD     DEFAULT_IRQHandler         ; 105 
+                DCD     DEFAULT_IRQHandler         ; 106 
+                DCD     DEFAULT_IRQHandler         ; 107 
+                DCD     DEFAULT_IRQHandler         ; 108     
+                DCD     KS_IRQHandler              ; 109     
+                DCD     TAMPER_IRQHandler          ; 110     
+                DCD     EWDT_IRQHandler            ; 111     
+                DCD     EWWDT_IRQHandler           ; 112     
+                DCD     NS_ISP_IRQHandler          ; 113
+                DCD     TMR4_IRQHandler            ; 114 
+                DCD     TMR5_IRQHandler            ; 115 
+                 
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+    THUMB
+    PUBWEAK Reset_Handler   
+    SECTION .text:CODE:NOROOT:REORDER(2)       ; 4 bytes alignment
+Reset_Handler
+
+      ; Check SecureWorld
+      MOV     R0, R15
+      LSLS    R0, R0, #3
+      BMI.N   GotoSystemInit
+
+      ; Unlock Register
+      LDR     R0, =0x40000100
+      LDR     R1, =0x59
+      STR     R1, [R0]
+      LDR     R1, =0x16
+      STR     R1, [R0]
+      LDR     R1, =0x88
+      STR     R1, [R0]
+
+      ; power gating
+      ; M32(0x400001f4) = 0xfffffffful;
+      LDR     R0, =0x400001f4
+      LDR     R1, =0xffffffff
+      STR     R1, [R0]
+
+      ; M32(0x400000dC) = 0ul;
+      LDR     R0, =0x400000dC
+      LDR     R1, =0x0
+      STR     R1, [R0]
+
+      ; Enable GPIO clks, SRAM clks, Trace clk
+      ; CLK->AHBCLK |= (0xffful << 20) | (1ul << 14);
+
+      LDR     R0, =0x40000200   ; R0 = Clock Controller Register Base Address
+      LDR     R1, [R0,#0x4]     ; R1 = 0x40000204  (AHBCLK)
+    
+      LDR     R2, =0xfff02000
+
+      ORRS    R1, R1, R2        ; (0xffful << 20) | (1ul << 14); 
+      STR     R1, [R0,#0x4]     ; CLK->AHBCLK |= (0xffful << 20) | (1ul << 14); ;
+
+GotoSystemInit:
+      LDR      R0, =SystemInit
+      BLX      R0
+
+      ; Lock register
+      LDR     R0, =0x40000100
+      MOVS    R1, #0
+      STR     R1, [R0]
+
+      LDR      R0, =__iar_program_start
+      BX       R0
+
+          PUBWEAK HardFault_Handler
+          PUBWEAK NMI_Handler       
+          PUBWEAK SVC_Handler       
+          PUBWEAK PendSV_Handler    
+          PUBWEAK SysTick_Handler   
+
+          PUBWEAK  BOD_IRQHandler	      ; 0  
+          PUBWEAK  IRC_IRQHandler             ; 1  
+          PUBWEAK  PWRWU_IRQHandler           ; 2  
+          PUBWEAK  SRAM_IRQHandler            ; 3  
+          PUBWEAK  CLKFAIL_IRQHandler         ; 4  
+         ;PUBWEAK  0                          ; 5  
+          PUBWEAK  RTC_IRQHandler             ; 6  
+          PUBWEAK  RTC_TAMPER_IRQHandler      ; 7  
+          PUBWEAK  WDT_IRQHandler             ; 8  
+          PUBWEAK  WWDT_IRQHandler            ; 9  
+          PUBWEAK  EINT0_IRQHandler           ; 10 
+          PUBWEAK  EINT1_IRQHandler           ; 11 
+          PUBWEAK  EINT2_IRQHandler           ; 12 
+          PUBWEAK  EINT3_IRQHandler           ; 13 
+          PUBWEAK  EINT4_IRQHandler           ; 14 
+          PUBWEAK  EINT5_IRQHandler           ; 15 
+          PUBWEAK  GPA_IRQHandler             ; 16 
+          PUBWEAK  GPB_IRQHandler             ; 17 
+          PUBWEAK  GPC_IRQHandler             ; 18 
+          PUBWEAK  GPD_IRQHandler             ; 19 
+          PUBWEAK  GPE_IRQHandler             ; 20 
+          PUBWEAK  GPF_IRQHandler             ; 21 
+          PUBWEAK  QSPI0_IRQHandler           ; 22 
+          PUBWEAK  SPI0_IRQHandler            ; 23 
+          PUBWEAK  BRAKE0_IRQHandler          ; 24 
+          PUBWEAK  EPWM0_P0_IRQHandler        ; 25 
+          PUBWEAK  EPWM0_P1_IRQHandler        ; 26 
+          PUBWEAK  EPWM0_P2_IRQHandler        ; 27 
+          PUBWEAK  BRAKE1_IRQHandler          ; 28 
+          PUBWEAK  EPWM1_P0_IRQHandler        ; 29 
+          PUBWEAK  EPWM1_P1_IRQHandler        ; 30 
+          PUBWEAK  EPWM1_P2_IRQHandler        ; 31 
+          PUBWEAK  TMR0_IRQHandler            ; 32 
+          PUBWEAK  TMR1_IRQHandler            ; 33 
+          PUBWEAK  TMR2_IRQHandler            ; 34 
+          PUBWEAK  TMR3_IRQHandler            ; 35 
+          PUBWEAK  UART0_IRQHandler           ; 36 
+          PUBWEAK  UART1_IRQHandler           ; 37 
+          PUBWEAK  I2C0_IRQHandler            ; 38 
+          PUBWEAK  I2C1_IRQHandler            ; 39 
+          PUBWEAK  PDMA0_IRQHandler           ; 40 
+          PUBWEAK  DAC_IRQHandler             ; 41 
+          PUBWEAK  EADC0_IRQHandler           ; 42 
+          PUBWEAK  EADC1_IRQHandler           ; 43 
+          PUBWEAK  ACMP01_IRQHandler          ; 44 
+         ;PUBWEAK  0                          ; 45 
+          PUBWEAK  EADC2_IRQHandler           ; 46 
+          PUBWEAK  EADC3_IRQHandler           ; 47 
+          PUBWEAK  UART2_IRQHandler           ; 48 
+          PUBWEAK  UART3_IRQHandler           ; 49 
+         ;PUBWEAK  0                          ; 50 
+          PUBWEAK  SPI1_IRQHandler            ; 51 
+          PUBWEAK  SPI2_IRQHandler            ; 52 
+          PUBWEAK  USBD_IRQHandler            ; 53 
+          PUBWEAK  USBH_IRQHandler            ; 54 
+          PUBWEAK  USBOTG_IRQHandler          ; 55 
+          PUBWEAK  CAN0_IRQHandler            ; 56 
+          PUBWEAK  CAN1_IRQHandler            ; 57 
+          PUBWEAK  SC0_IRQHandler             ; 58 
+          PUBWEAK  SC1_IRQHandler             ; 59 
+          PUBWEAK  SC2_IRQHandler             ; 60 
+          PUBWEAK  SC3_IRQHandler             ; 61 
+          PUBWEAK  SPI3_IRQHandler            ; 62 
+         ;PUBWEAK  0                          ; 63 
+          PUBWEAK  SDH0_IRQHandler            ; 64 
+         ;PUBWEAK  0                          ; 65 
+         ;PUBWEAK  0                          ; 66 
+         ;PUBWEAK  0                          ; 67 
+          PUBWEAK  I2S0_IRQHandler            ; 68 
+         ;PUBWEAK  0                          ; 69 
+          PUBWEAK  OPA0_IRQHandler            ; 70 
+          PUBWEAK  CRPT_IRQHandler            ; 71 
+          PUBWEAK  GPG_IRQHandler             ; 72 
+          PUBWEAK  EINT6_IRQHandler           ; 73 
+          PUBWEAK  UART4_IRQHandler           ; 74 
+          PUBWEAK  UART5_IRQHandler           ; 75 
+          PUBWEAK  USCI0_IRQHandler           ; 76 
+          PUBWEAK  USCI1_IRQHandler           ; 77 
+          PUBWEAK  BPWM0_IRQHandler           ; 78 
+          PUBWEAK  BPWM1_IRQHandler           ; 79 
+         ;PUBWEAK  0                          ; 80 
+         ;PUBWEAK  0                          ; 81 
+          PUBWEAK  I2C2_IRQHandler            ; 82 
+         ;PUBWEAK  0                          ; 83 
+          PUBWEAK  QEI0_IRQHandler            ; 84 
+          PUBWEAK  QEI1_IRQHandler            ; 85 
+          PUBWEAK  ECAP0_IRQHandler           ; 86 
+          PUBWEAK  ECAP1_IRQHandler           ; 87 
+          PUBWEAK  GPH_IRQHandler             ; 88 
+          PUBWEAK  EINT7_IRQHandler           ; 89 
+          PUBWEAK  SDH1_IRQHandler            ; 90 
+         ;PUBWEAK  0                          ; 91 
+         ;PUBWEAK  USBH_IRQHandler            ; 92 
+         ;PUBWEAK  0                          ; 93 
+         ;PUBWEAK  0                          ; 94 
+         ;PUBWEAK  0                          ; 95 
+         ;PUBWEAK  0                          ; 96 
+         ;PUBWEAK  0                          ; 97 
+          PUBWEAK  PDMA1_IRQHandler           ; 98 
+          PUBWEAK  SCU_IRQHandler             ; 99 
+          PUBWEAK  LCD_IRQHandler             ; 100
+          PUBWEAK  TRNG_IRQHandler            ; 101
+          ;PUBWEAK  0         ; 102 
+          ;PUBWEAK  0         ; 103 
+          ;PUBWEAK  0         ; 104 
+          ;PUBWEAK  0         ; 105 
+          ;PUBWEAK  0         ; 106 
+          ;PUBWEAK  0         ; 107 
+          ;PUBWEAK  0         ; 108     
+          PUBWEAK  KS_IRQHandler              ; 109     
+          PUBWEAK  TAMPER_IRQHandler          ; 110     
+          PUBWEAK  EWDT_IRQHandler            ; 111     
+          PUBWEAK  EWWDT_IRQHandler           ; 112     
+          PUBWEAK  NS_ISP_IRQHandler          ; 113                         
+          PUBWEAK  TMR4_IRQHandler            ; 114 
+          PUBWEAK  TMR5_IRQHandler            ; 115 
+		
+          PUBWEAK	DEFAULT_IRQHandler		                                                
+
+    SECTION .text:CODE:NOROOT:REORDER(2)
+
+HardFault_Handler
+NMI_Handler       
+SVC_Handler       
+PendSV_Handler    
+SysTick_Handler   
+
+BOD_IRQHandler		       ; 0  
+IRC_IRQHandler             ; 1  
+PWRWU_IRQHandler           ; 2  
+SRAM_IRQHandler            ; 3  
+CLKFAIL_IRQHandler         ; 4  
+;0                          ; 5  
+RTC_IRQHandler             ; 6  
+RTC_TAMPER_IRQHandler      ; 7  
+WDT_IRQHandler             ; 8  
+WWDT_IRQHandler            ; 9  
+EINT0_IRQHandler           ; 10 
+EINT1_IRQHandler           ; 11 
+EINT2_IRQHandler           ; 12 
+EINT3_IRQHandler           ; 13 
+EINT4_IRQHandler           ; 14 
+EINT5_IRQHandler           ; 15 
+GPA_IRQHandler             ; 16 
+GPB_IRQHandler             ; 17 
+GPC_IRQHandler             ; 18 
+GPD_IRQHandler             ; 19 
+GPE_IRQHandler             ; 20 
+GPF_IRQHandler             ; 21 
+QSPI0_IRQHandler           ; 22 
+SPI0_IRQHandler            ; 23 
+BRAKE0_IRQHandler          ; 24 
+EPWM0_P0_IRQHandler        ; 25 
+EPWM0_P1_IRQHandler        ; 26 
+EPWM0_P2_IRQHandler        ; 27 
+BRAKE1_IRQHandler          ; 28 
+EPWM1_P0_IRQHandler        ; 29 
+EPWM1_P1_IRQHandler        ; 30 
+EPWM1_P2_IRQHandler        ; 31 
+TMR0_IRQHandler            ; 32 
+TMR1_IRQHandler            ; 33 
+TMR2_IRQHandler            ; 34 
+TMR3_IRQHandler            ; 35 
+UART0_IRQHandler           ; 36 
+UART1_IRQHandler           ; 37 
+I2C0_IRQHandler            ; 38 
+I2C1_IRQHandler            ; 39 
+PDMA0_IRQHandler           ; 40 
+DAC_IRQHandler             ; 41 
+EADC0_IRQHandler           ; 42 
+EADC1_IRQHandler           ; 43 
+ACMP01_IRQHandler          ; 44 
+;0                          ; 45 
+EADC2_IRQHandler           ; 46 
+EADC3_IRQHandler           ; 47 
+UART2_IRQHandler           ; 48 
+UART3_IRQHandler           ; 49 
+;0                          ; 50 
+SPI1_IRQHandler            ; 51 
+SPI2_IRQHandler            ; 52 
+USBD_IRQHandler            ; 53 
+USBH_IRQHandler            ; 54 
+USBOTG_IRQHandler          ; 55 
+CAN0_IRQHandler            ; 56 
+CAN1_IRQHandler            ; 57 
+SC0_IRQHandler             ; 58 
+SC1_IRQHandler             ; 59 
+SC2_IRQHandler             ; 60 
+SC3_IRQHandler             ; 61 
+SPI3_IRQHandler            ; 62 
+;0                          ; 63 
+SDH0_IRQHandler            ; 64 
+;0                          ; 65 
+;0                          ; 66 
+;0                          ; 67 
+I2S0_IRQHandler            ; 68 
+;0                          ; 69 
+OPA0_IRQHandler            ; 70 
+CRPT_IRQHandler            ; 71 
+GPG_IRQHandler             ; 72 
+EINT6_IRQHandler           ; 73 
+UART4_IRQHandler           ; 74 
+UART5_IRQHandler           ; 75 
+USCI0_IRQHandler           ; 76 
+USCI1_IRQHandler           ; 77 
+BPWM0_IRQHandler           ; 78 
+BPWM1_IRQHandler           ; 79 
+;0                          ; 80 
+;0                          ; 81 
+I2C2_IRQHandler            ; 82 
+;0                          ; 83 
+QEI0_IRQHandler            ; 84 
+QEI1_IRQHandler            ; 85 
+ECAP0_IRQHandler           ; 86 
+ECAP1_IRQHandler           ; 87 
+GPH_IRQHandler             ; 88 
+EINT7_IRQHandler           ; 89 
+SDH1_IRQHandler            ; 90 
+;0                          ; 91 
+;USBH_IRQHandler            ; 92 
+;0                          ; 93 
+;0                          ; 94 
+;0                          ; 95 
+;0                          ; 96 
+;0                          ; 97 
+PDMA1_IRQHandler           ; 98 
+SCU_IRQHandler             ; 99 
+LCD_IRQHandler             ; 100
+TRNG_IRQHandler            ; 101
+;0                          ; 102 
+;0                          ; 103 
+;0                          ; 104 
+;0                          ; 105 
+;0                          ; 106
+;0                          ; 107 
+;0                          ; 108 
+KS_IRQHandler               ; 109     
+TAMPER_IRQHandler           ; 110     
+EWDT_IRQHandler             ; 111     
+EWWDT_IRQHandler            ; 112     
+NS_ISP_IRQHandler           ; 113    
+TMR4_IRQHandler             ; 114 
+TMR5_IRQHandler             ; 115 
+DEFAULT_IRQHandler
+    B DEFAULT_IRQHandler         
+
+
+;void SH_ICE(void)
+    PUBLIC    SH_ICE
+SH_ICE    
+    CMP   R2,#0
+    BEQ   SH_End
+    STR   R0,[R2]   ; Save the return value to *pn32Out_R0
+
+;void SH_End(void)
+    PUBLIC    SH_End
+SH_End
+    MOVS   R0,#1    ; Set return value to 1
+    BX     lr       ; Return
+
+
+;int32_t SH_DoCommand(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0)
+    PUBLIC    SH_DoCommand
+SH_DoCommand
+    BKPT   0xAB             ; This instruction will cause ICE trap or system HardFault
+    B      SH_ICE
+SH_HardFault                ; Captured by HardFault
+    MOVS   R0,#0            ; Set return value to 0
+    BX     lr               ; Return
+    
+    
+    PUBLIC    __PC
+__PC          
+        MOV     r0, lr
+        BLX     lr
+            
+    END
+
diff --git a/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Source/system_M2354.c b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Source/system_M2354.c
new file mode 100644
index 0000000000..4f69903830
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/Nuvoton/M2354/Source/system_M2354.c
@@ -0,0 +1,567 @@
+/**************************************************************************//**
+ * @file     system_M2354.c
+ * @version  V2.00
+ * @brief    System Setting Source File
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)       /* ARM Compiler 6 */
+#include 
+#endif
+
+#include 
+#include 
+#include "NuMicro.h"
+
+#if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)
+#include "nu_partition_M2354.h"
+#endif
+extern void *g_pfnVectors;                   /* see startup file */
+
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock  = __HSI;              /*!< System Clock Frequency (Core Clock) */
+uint32_t CyclesPerUs      = (__HSI / 1000000UL);/*!< Cycles per micro second             */
+uint32_t PllClock         = __HSI;              /*!< PLL Output Clock Frequency          */
+
+void FMC_NSBA_Setup(void);
+void SCU_Setup(void);
+void NSC_Init(void);
+void TZ_SAU_Setup(void);
+
+
+#if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)
+extern void SCU_IRQHandler(void);
+#else
+extern void SCU_IRQHandler(void)__attribute__((noreturn));
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+ * @brief    Setup Non-secure boundary
+ *
+ * @details  This function is used to set Non-secure boundary according to
+ *           the configuration of partition header file
+ */
+void FMC_NSBA_Setup(void)
+{
+    /* Skip NSBA Setupt according config */
+    if(FMC_INIT_NSBA == 0)
+        return;
+
+    /* Check if NSBA value with current active NSBA */
+    if(SCU->FNSADDR != FMC_SECURE_ROM_SIZE)
+    {
+        /* Unlock Protected Register */
+        SYS_UnlockReg();
+
+        /* Enable ISP and config update */
+        FMC->ISPCTL = FMC_ISPCTL_ISPEN_Msk | FMC_ISPCTL_CFGUEN_Msk;
+
+        /* Config Base of NSBA */
+        FMC->ISPADDR = FMC_NSCBA_BASE ;
+
+        /* Read Non-secure base address config */
+        FMC->ISPCMD = FMC_ISPCMD_READ;
+        FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+        while(FMC->ISPTRG);
+
+        //while(PA0);
+
+        /* Setting NSBA when it is empty */
+        if(FMC->ISPDAT != 0xfffffffful)
+        {
+            /* Erase old setting */
+            FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE;
+            FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+            while(FMC->ISPTRG);
+        }
+
+        /* Set new base */
+        FMC->ISPDAT = FMC_SECURE_ROM_SIZE;
+        FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
+        FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+        while(FMC->ISPTRG);
+
+        /* Force Chip Reset to valid new setting */
+        SYS->IPRST0 = SYS_IPRST0_CHIPRST_Msk;
+
+
+    }
+
+}
+
+
+/**
+  \brief   Setup SCU Configuration Unit
+  \details
+
+ */
+void SCU_Setup(void)
+{
+    int32_t i;
+
+    SCU->PNSSET[0] = SCU_INIT_PNSSET0_VAL;
+    SCU->PNSSET[1] = SCU_INIT_PNSSET1_VAL;
+    SCU->PNSSET[2] = SCU_INIT_PNSSET2_VAL;
+    SCU->PNSSET[3] = SCU_INIT_PNSSET3_VAL;
+    SCU->PNSSET[4] = SCU_INIT_PNSSET4_VAL;
+    SCU->PNSSET[5] = SCU_INIT_PNSSET5_VAL;
+    SCU->PNSSET[6] = SCU_INIT_PNSSET6_VAL;
+
+
+    SCU->IONSSET[0] = SCU_INIT_IONSSET0_VAL;
+    SCU->IONSSET[1] = SCU_INIT_IONSSET1_VAL;
+    SCU->IONSSET[2] = SCU_INIT_IONSSET2_VAL;
+    SCU->IONSSET[3] = SCU_INIT_IONSSET3_VAL;
+    SCU->IONSSET[4] = SCU_INIT_IONSSET4_VAL;
+    SCU->IONSSET[5] = SCU_INIT_IONSSET5_VAL;
+    SCU->IONSSET[6] = SCU_INIT_IONSSET6_VAL;
+    SCU->IONSSET[7] = SCU_INIT_IONSSET7_VAL;
+
+    /* Set Non-secure SRAM */
+    for(i = 15; i >= SCU_SECURE_SRAM_SIZE / 16384; i--)
+    {
+        SCU->SRAMNSSET |= (1U << i);
+    }
+
+    /* Set interrupt to non-secure according to PNNSET settings */
+    if(SCU_INIT_PNSSET0_VAL & BIT9) NVIC->ITNS[1] |= BIT22;  /* Int of USBH_INT     */
+    if(SCU_INIT_PNSSET0_VAL & BIT13) NVIC->ITNS[2] |= BIT0 ; /* Int of SDHOST0_INT  */
+    if(SCU_INIT_PNSSET0_VAL & BIT24) NVIC->ITNS[3] |= BIT2 ; /* Int of PDMA1_INT    */
+    if(SCU_INIT_PNSSET1_VAL & BIT18) NVIC->ITNS[2] |= BIT7 ; /* Int of CRYPTO       */
+    if(SCU_INIT_PNSSET2_VAL & BIT2) NVIC->ITNS[3] |= BIT15;  /* Int of EWDT_INT     */
+    if(SCU_INIT_PNSSET2_VAL & BIT2) NVIC->ITNS[3] |= BIT16;  /* Int of EWWDT_INT    */
+    if(SCU_INIT_PNSSET2_VAL & BIT3) NVIC->ITNS[1] |= BIT10;  /* Int of EADC0_INT    */
+    if(SCU_INIT_PNSSET2_VAL & BIT3) NVIC->ITNS[1] |= BIT11;  /* Int of EADC1_INT    */
+    if(SCU_INIT_PNSSET2_VAL & BIT3) NVIC->ITNS[1] |= BIT14;  /* Int of EADC2_INT    */
+    if(SCU_INIT_PNSSET2_VAL & BIT3) NVIC->ITNS[1] |= BIT15;  /* Int of EADC3_INT    */
+    if(SCU_INIT_PNSSET2_VAL & BIT5) NVIC->ITNS[1] |= BIT12;  /* Int of ACMP01_INT   */
+    if(SCU_INIT_PNSSET2_VAL & BIT7) NVIC->ITNS[1] |= BIT9 ;  /* Int of DAC_INT      */
+    if(SCU_INIT_PNSSET2_VAL & BIT8) NVIC->ITNS[2] |= BIT4 ;  /* Int of I2S0_INT     */
+    if(SCU_INIT_PNSSET2_VAL & BIT13) NVIC->ITNS[1] |= BIT23; /* Int of USBOTG_INT   */
+    if(SCU_INIT_PNSSET2_VAL & BIT17) NVIC->ITNS[1] |= BIT2 ; /* Int of TMR2_INT     */
+    if(SCU_INIT_PNSSET2_VAL & BIT17) NVIC->ITNS[1] |= BIT3 ; /* Int of TMR3_INT     */
+    if(SCU_INIT_PNSSET2_VAL & BIT18) NVIC->ITNS[3] |= BIT18; /* Int of TMR4_INT     */
+    if(SCU_INIT_PNSSET2_VAL & BIT18) NVIC->ITNS[3] |= BIT19; /* Int of TMR5_INT     */
+    if(SCU_INIT_PNSSET2_VAL & BIT24) NVIC->ITNS[0] |= BIT25; /* Int of EPWM0_P0_INT */
+    if(SCU_INIT_PNSSET2_VAL & BIT24) NVIC->ITNS[0] |= BIT26; /* Int of EPWM0_P1_INT */
+    if(SCU_INIT_PNSSET2_VAL & BIT24) NVIC->ITNS[0] |= BIT27; /* Int of EPWM0_P2_INT */
+    if(SCU_INIT_PNSSET2_VAL & BIT25) NVIC->ITNS[0] |= BIT29; /* Int of EPWM1_P0_INT */
+    if(SCU_INIT_PNSSET2_VAL & BIT25) NVIC->ITNS[0] |= BIT30; /* Int of EPWM1_P1_INT */
+    if(SCU_INIT_PNSSET2_VAL & BIT25) NVIC->ITNS[0] |= BIT31; /* Int of EPWM1_P2_INT */
+    if(SCU_INIT_PNSSET2_VAL & BIT26) NVIC->ITNS[2] |= BIT14; /* Int of BPWM0_INT    */
+    if(SCU_INIT_PNSSET2_VAL & BIT27) NVIC->ITNS[2] |= BIT15; /* Int of BPWM1_INT    */
+    if(SCU_INIT_PNSSET3_VAL & BIT0) NVIC->ITNS[0] |= BIT22;  /* Int of QSPI0_INT    */
+    if(SCU_INIT_PNSSET3_VAL & BIT1) NVIC->ITNS[0] |= BIT23;  /* Int of SPI0_INT     */
+    if(SCU_INIT_PNSSET3_VAL & BIT2) NVIC->ITNS[1] |= BIT19;  /* Int of SPI1_INT     */
+    if(SCU_INIT_PNSSET3_VAL & BIT3) NVIC->ITNS[1] |= BIT20;  /* Int of SPI2_INT     */
+    if(SCU_INIT_PNSSET3_VAL & BIT4) NVIC->ITNS[1] |= BIT30;  /* Int of SPI3_INT     */
+    if(SCU_INIT_PNSSET3_VAL & BIT16) NVIC->ITNS[1] |= BIT4 ; /* Int of UART0_INT    */
+    if(SCU_INIT_PNSSET3_VAL & BIT17) NVIC->ITNS[1] |= BIT5 ; /* Int of UART1_INT    */
+    if(SCU_INIT_PNSSET3_VAL & BIT18) NVIC->ITNS[1] |= BIT16; /* Int of UART2_INT    */
+    if(SCU_INIT_PNSSET3_VAL & BIT19) NVIC->ITNS[1] |= BIT17; /* Int of UART3_INT    */
+    if(SCU_INIT_PNSSET3_VAL & BIT20) NVIC->ITNS[2] |= BIT10; /* Int of UART4_INT    */
+    if(SCU_INIT_PNSSET3_VAL & BIT21) NVIC->ITNS[2] |= BIT11; /* Int of UART5_INT    */
+    if(SCU_INIT_PNSSET4_VAL & BIT0) NVIC->ITNS[1] |= BIT6 ;  /* Int of I2C0_INT     */
+    if(SCU_INIT_PNSSET4_VAL & BIT1) NVIC->ITNS[1] |= BIT7 ;  /* Int of I2C1_INT     */
+    if(SCU_INIT_PNSSET4_VAL & BIT2) NVIC->ITNS[2] |= BIT18;  /* Int of I2C2_INT     */
+    if(SCU_INIT_PNSSET4_VAL & BIT16) NVIC->ITNS[1] |= BIT26; /* Int of SC0_INT      */
+    if(SCU_INIT_PNSSET4_VAL & BIT17) NVIC->ITNS[1] |= BIT27; /* Int of SC1_INT      */
+    if(SCU_INIT_PNSSET4_VAL & BIT18) NVIC->ITNS[1] |= BIT28; /* Int of SC2_INT      */
+    if(SCU_INIT_PNSSET5_VAL & BIT0) NVIC->ITNS[1] |= BIT24;  /* Int of CAN0_INT     */
+    if(SCU_INIT_PNSSET5_VAL & BIT16) NVIC->ITNS[2] |= BIT20; /* Int of QEI0_INT     */
+    if(SCU_INIT_PNSSET5_VAL & BIT17) NVIC->ITNS[2] |= BIT21; /* Int of QEI1_INT     */
+    if(SCU_INIT_PNSSET5_VAL & BIT20) NVIC->ITNS[2] |= BIT22; /* Int of ECAP0_INT    */
+    if(SCU_INIT_PNSSET5_VAL & BIT21) NVIC->ITNS[2] |= BIT23; /* Int of ECAP1_INT    */
+    if(SCU_INIT_PNSSET5_VAL & BIT25) NVIC->ITNS[3] |= BIT5 ; /* Int of TRNG_INT     */
+    if(SCU_INIT_PNSSET5_VAL & BIT27) NVIC->ITNS[3] |= BIT4 ; /* Int of LCD_INT      */
+    if(SCU_INIT_PNSSET6_VAL & BIT0) NVIC->ITNS[1] |= BIT21;  /* Int of USBD_INT     */
+    if(SCU_INIT_PNSSET6_VAL & BIT16) NVIC->ITNS[2] |= BIT12; /* Int of USCI0_INT    */
+    if(SCU_INIT_PNSSET6_VAL & BIT17) NVIC->ITNS[2] |= BIT13; /* Int of USCI1_INT    */
+    if(SCU_INIT_IONSSET_VAL & BIT0) NVIC->ITNS[0] |= BIT16;  /* Int of PA           */
+    if(SCU_INIT_IONSSET_VAL & BIT1) NVIC->ITNS[0] |= BIT17;  /* Int of PB           */
+    if(SCU_INIT_IONSSET_VAL & BIT2) NVIC->ITNS[0] |= BIT18;  /* Int of PC           */
+    if(SCU_INIT_IONSSET_VAL & BIT3) NVIC->ITNS[0] |= BIT19;  /* Int of PD           */
+    if(SCU_INIT_IONSSET_VAL & BIT4) NVIC->ITNS[0] |= BIT20;  /* Int of PE           */
+    if(SCU_INIT_IONSSET_VAL & BIT5) NVIC->ITNS[0] |= BIT21;  /* Int of PF           */
+    if(SCU_INIT_IONSSET_VAL & BIT6) NVIC->ITNS[2] |= BIT8 ;  /* Int of PG           */
+    if(SCU_INIT_IONSSET_VAL & BIT7) NVIC->ITNS[2] |= BIT24;  /* Int of PH           */
+    if(SCU_INIT_IONSSET_VAL & BIT8) NVIC->ITNS[0] |= BIT10;  /* Int of EINT0        */
+    if(SCU_INIT_IONSSET_VAL & BIT9) NVIC->ITNS[0] |= BIT11;  /* Int of EINT1        */
+    if(SCU_INIT_IONSSET_VAL & BIT10) NVIC->ITNS[0] |= BIT12; /* Int of EINT2        */
+    if(SCU_INIT_IONSSET_VAL & BIT11) NVIC->ITNS[0] |= BIT13; /* Int of EINT3        */
+    if(SCU_INIT_IONSSET_VAL & BIT12) NVIC->ITNS[0] |= BIT14; /* Int of EINT4        */
+    if(SCU_INIT_IONSSET_VAL & BIT13) NVIC->ITNS[0] |= BIT15; /* Int of EINT5        */
+    if(SCU_INIT_IONSSET_VAL & BIT14) NVIC->ITNS[2] |= BIT9;  /* Int of EINT6        */
+    if(SCU_INIT_IONSSET_VAL & BIT15) NVIC->ITNS[2] |= BIT25; /* Int of EINT7        */
+
+    /* Enable SCU Int status */
+    SCU->SVIOIEN = (uint32_t)(-1);
+    SCU->PVIOIEN = (uint32_t)(-1);
+    NVIC_EnableIRQ(SCU_IRQn);
+
+}
+
+
+#if defined( __ICCARM__ )
+__WEAK
+#else
+__attribute__((weak))
+#endif
+void SCU_IRQHandler(void)
+{
+    char const *master[] = {"CPU", 0, 0, "PDMA0", "SDH0", "CRPT", "USBH", 0, 0, 0, 0, "PDMA1"};
+    char const *ipname[] = {"APB0", "APB1", 0, 0, "GPIO", "EBI", "USBH", "CRC", "SDH0", 0, "PDMA0", "PDMA1"
+                            , "SRAM0", "SRAM1", "FMC", "FLASH", "SCU", "SYS", "CRPT", "KS", "SIORAM"
+                           };
+    const uint8_t info[] = {0x34, 0x3C, 0, 0, 0x44, 0x4C, 0x54, 0x5C, 0x64, 0, 0x74, 0x7C, 0x84, 0x8C, 0x94, 0x9C, 0xA4, 0xAC, 0xB4, 0xBC, 0xC4};
+    uint32_t u32Reg, u32Addr;
+    uint32_t i;
+
+    /* TrustZone access policy */
+    u32Reg = SCU->SVINTSTS;
+    if(u32Reg)
+    {
+
+        /* Get violation address and source */
+        for(i = 0; i < sizeof(ipname); i++)
+        {
+            if(u32Reg & (1 << i))
+            {
+                u32Addr = M32(SCU_BASE + info[i] + 4);
+                printf("  %s(0x%08x) Alarm! illegal access by %s\n", ipname[i], u32Addr, master[M32(SCU_BASE + info[i])]);
+                SCU->SVINTSTS = (1 << i);
+                break;
+            }
+
+        }
+    }
+
+    /* Privilege */
+    u32Reg = SCU->PVINTSTS;
+    if(u32Reg)
+    {
+        /* Get violation address and source */
+        for(i = 0; i < sizeof(ipname); i++)
+        {
+            if(u32Reg & (1 << i))
+            {
+                printf("\n%s Alarm! Caused by unprivilege access\n\n", ipname[i]);
+                SCU->PVINTSTS = (1 << i);
+                break;
+            }
+        }
+    }
+
+}
+
+
+/**
+  \brief   Setup a Nonsecure callable Region
+  \details The base and limit of Nonsecure callable region is dependent on the
+           application code size.
+ */
+void NSC_Init(void)
+{
+    uint32_t u32Region;
+    uint32_t u32Base, u32Limit;
+
+#if defined (__ICCARM__)
+# pragma section = "NSC"
+    u32Base = (uint32_t)__section_begin("NSC");
+    u32Limit = (uint32_t)__section_end("NSC");
+#elif defined(__ARMCC_VERSION)
+#pragma clang diagnostic push
+#pragma clang diagnostic ignored "-Wdollar-in-identifier-extension"
+    extern uint32_t Image$$NSC_ROM$$XO$$Base[];
+    extern uint32_t Image$$NSC_ROM$$XO$$Limit[];
+    u32Base = (uint32_t)Image$$NSC_ROM$$XO$$Base;
+    u32Limit = (uint32_t)Image$$NSC_ROM$$XO$$Limit;
+#pragma clang diagnostic pop
+#else
+    extern uint32_t __start_NSC[];
+    extern uint32_t __end_NSC[];
+    u32Base = (uint32_t)__start_NSC;
+    u32Limit = (uint32_t)__end_NSC;
+#endif
+
+    /* SAU region 3 is dedicated for NSC */
+    u32Region = 3;
+    SAU->RNR  = (u32Region & SAU_RNR_REGION_Msk);
+    SAU->RBAR = (u32Base & SAU_RBAR_BADDR_Msk);
+    SAU->RLAR = (u32Limit & SAU_RLAR_LADDR_Msk) |
+                ((1ul << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk) | 1ul;
+
+}
+
+/**
+  \brief   Setup a SAU Region
+  \details Writes the region information contained in SAU_Region to the
+           registers SAU_RNR, SAU_RBAR, and SAU_RLAR
+ */
+void TZ_SAU_Setup(void)
+{
+
+#if defined (__SAU_PRESENT) && (__SAU_PRESENT == 1U)
+
+#if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
+    SAU_INIT_REGION(0);
+#endif
+
+#if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
+    SAU_INIT_REGION(1);
+#endif
+
+#if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
+    SAU_INIT_REGION(2);
+#endif
+
+#if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
+    SAU_INIT_REGION(3);
+#endif
+
+#if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
+    SAU_INIT_REGION(4);
+#endif
+
+#if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
+    SAU_INIT_REGION(5);
+#endif
+
+#if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
+    SAU_INIT_REGION(6);
+#endif
+
+#if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
+    SAU_INIT_REGION(7);
+#endif
+
+    /* repeat this for all possible SAU regions */
+
+
+#if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
+    SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
+                ((SAU_INIT_CTRL_ALLNS  << SAU_CTRL_ALLNS_Pos)  & SAU_CTRL_ALLNS_Msk)   ;
+#endif
+
+#endif /* defined (__SAU_PRESENT) && (__SAU_PRESENT == 1U) */
+
+#if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
+    SCB->SCR   = (SCB->SCR   & ~(SCB_SCR_SLEEPDEEPS_Msk)) |
+                 ((SCB_CSR_DEEPSLEEPS_VAL     << SCB_SCR_SLEEPDEEPS_Pos)     & SCB_SCR_SLEEPDEEPS_Msk);
+
+    SCB->AIRCR = (0x05FA << 16) |
+                 ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
+                 ((SCB_AIRCR_BFHFNMINS_VAL    << SCB_AIRCR_BFHFNMINS_Pos)    & SCB_AIRCR_BFHFNMINS_Msk)    |
+                 ((SCB_AIRCR_PRIS_VAL         << SCB_AIRCR_PRIS_Pos)         & SCB_AIRCR_PRIS_Msk);
+
+
+
+#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
+
+#if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U)
+    SCB->ICSR  = (SCB->ICSR  & ~(SCB_ICSR_STTNS_Msk)) |
+                 ((SCB_ICSR_STTNS_VAL         << SCB_ICSR_STTNS_Pos)         & SCB_ICSR_STTNS_Msk);
+#endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */
+
+    /* repeat this for all possible ITNS elements */
+
+    /* Initial Nonsecure callable region */
+    NSC_Init();
+}
+#else
+#if defined( __ICCARM__ )
+__WEAK
+#else
+__attribute__((weak))
+#endif
+void SCU_IRQHandler(void)
+{
+    while(1);
+}
+#endif
+
+
+/**
+ * @brief    Update the Variable SystemCoreClock
+ *
+ * @details  This function is used to update the variable SystemCoreClock
+ *           and must be called whenever the core clock is changed.
+ */
+void SystemCoreClockUpdate(void)
+{
+    /* Update PLL Clock */
+    PllClock = CLK_GetPLLClockFreq();
+
+    /* Update System Core Clock */
+    SystemCoreClock = CLK_GetCPUFreq();
+
+    /* Update Cycles per micro second */
+    CyclesPerUs = (SystemCoreClock + 500000UL) / 1000000UL;
+}
+
+
+
+/**
+ * @brief    System Initialization
+ *
+ * @details  The necessary initialization of system. Global variables are forbidden here.
+ */
+void SystemInit(void)
+{
+#if 0
+/* Move the scope into Reset_Handler to avoid invalid memory access. */
+/* When push LR to RAM region is not enabled, it will get hardware after exit SystemInit.*/
+    if((__PC() & NS_OFFSET) == 0)
+    {
+        /* Unlock protected registers */
+        do
+        {
+            SYS->REGLCTL = 0x59;
+            SYS->REGLCTL = 0x16;
+            SYS->REGLCTL = 0x88;
+        }
+        while(!SYS->REGLCTL);
+
+        /* Enable Crypto power switch */
+        SYS->PSWCTL = SYS_PSWCTL_CRPTPWREN_Msk;
+
+        /* Enable all GPIO, SRAM and Trace clock */
+        CLK->AHBCLK |= (0xffful << 20) | (1ul << 14);
+    }
+#endif
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+    SCB->VTOR = (uint32_t) &g_pfnVectors;
+#endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
+    TZ_SAU_Setup();
+    SCU_Setup();
+    FMC_NSBA_Setup();
+#endif
+
+#ifdef INIT_SYSCLK_AT_BOOTING
+
+#endif
+
+}
+
+
+#if USE_ASSERT
+
+/**
+ * @brief      Assert Error Message
+ *
+ * @param[in]  file  the source file name
+ * @param[in]  line  line number
+ *
+ * @details    The function prints the source file name and line number where
+ *             the ASSERT_PARAM() error occurs, and then stops in an infinite loop.
+ */
+void AssertError(uint8_t * file, uint32_t line)
+{
+
+    printf("[%s] line %d : wrong parameters.\r\n", file, line);
+
+    /* Infinite loop */
+    while(1) ;
+}
+#endif
+
+
+#if (defined(__ICCARM__) && (__VER__ >= 7080000) && (__VER__ < 8020000))
+
+#if  (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+uint32_t __TZ_get_PSP_NS(void)
+{
+    register uint32_t result;
+
+    __ASM volatile("MRS %0, psp_ns"  : "=r"(result));
+    return(result);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+    __ASM volatile("MSR psp_ns, %0" : : "r"(topOfProcStack));
+}
+
+
+
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+int32_t __TZ_get_MSP_NS(void)
+{
+    register uint32_t result;
+
+    __ASM volatile("MRS %0, msp_ns" : "=r"(result));
+    return(result);
+}
+
+
+
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+    __ASM volatile("MSR msp_ns, %0" : : "r"(topOfMainStack));
+}
+
+
+
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+uint32_t __TZ_get_PRIMASK_NS(void)
+{
+    uint32_t result;
+
+    __ASM volatile("MRS %0, primask_ns" : "=r"(result));
+    return(result);
+}
+
+
+
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+    __ASM volatile("MSR primask_ns, %0" : : "r"(priMask) : "memory");
+}
+
+
+#endif
+
+
+#endif
+
+
+
diff --git a/bsp/nuvoton/libraries/m2354/Device/SConscript b/bsp/nuvoton/libraries/m2354/Device/SConscript
new file mode 100644
index 0000000000..07add1dc67
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/Device/SConscript
@@ -0,0 +1,25 @@
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+src = Split("""
+Nuvoton/M2354/Source/system_M2354.c
+""")
+
+# add for startup script 
+if rtconfig.CROSS_TOOL == 'gcc':
+    src = src + ['Nuvoton/M2354/Source/GCC/startup_M2354.S']
+elif rtconfig.CROSS_TOOL == 'keil':
+    src = src + ['Nuvoton/M2354/Source/ARM/startup_M2354.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+    src = src + ['Nuvoton/M2354/Source/IAR/startup_M2354.s']
+
+path = [cwd + '/Nuvoton/M2354/Include',]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+
+Return('group')
diff --git a/bsp/nuvoton/libraries/m2354/README.md b/bsp/nuvoton/libraries/m2354/README.md
new file mode 100644
index 0000000000..585f6e2227
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/README.md
@@ -0,0 +1,47 @@
+# M2354 Series
+
+## Supported drivers
+
+| Peripheral | rt_device_class_type | Device name |
+| ------ | ----  | :------:  |
+| BPWM | RT_Device_Class_Miscellaneous (PWM) | ***bpwm[0-1]*** |
+| BPWM (Capture function)| RT_Device_Class_Miscellaneous (Input capture) | ***bpwm[0-1]i[0-5]*** |
+| CAN | RT_Device_Class_CAN | ***can0*** |
+| CLK | RT_Device_Class_PM | ***pm*** |
+| CRC | RT_Device_Class_Miscellaneous (HW Crypto) | ***hwcryto*** |
+| CRYPTO | RT_Device_Class_Miscellaneous (HW Crypto) | ***hwcryto*** |
+| EADC | RT_Device_Class_Miscellaneous (ADC) | ***eadc0*** |
+| EBI | N/A | ***N/A*** |
+| ECAP | RT_Device_Class_Miscellaneous (Input capture) | ***ecap[0-1]i[0-2]*** |
+| EPWM | RT_Device_Class_Miscellaneous (PWM) | ***epwm[0-1]*** |
+| EPWM (Capture function) | RT_Device_Class_Miscellaneous (Input capture) | ***epwm[0-1]i[0-5]*** |
+| FMC | FAL | ***N/A*** |
+| GPIO | RT_Device_Class_Miscellaneous (Pin) | ***gpio*** |
+| GPIO | RT_Device_Class_I2CBUS | ***softi2c0[0-1]*** |
+| I2C | RT_Device_Class_I2CBUS | ***i2c[0-2]*** |
+| I2S | RT_Device_Class_Sound/RT_Device_Class_Pipe | ***sound0*** |
+| PDMA | N/A | ***N/A*** |
+| QEI | RT_Device_Class_Miscellaneous (Pulse encoder) | ***qei[0-1]*** |
+| QSPI | RT_Device_Class_SPIBUS | ***qspi0*** |
+| RTC | RT_Device_Class_RTC | ***rtc*** |
+| SC (UART function) | RT_Device_Class_Char | ***scuart[0-2]*** |
+| SDH | RT_Device_Class_Block | ***sdh0*** |
+| SPI | RT_Device_Class_SPIBUS | ***spi[0-3]*** |
+| SPI (I2S function) | RT_Device_Class_Sound/RT_Device_Class_Pipe | ***spii2s[0-3]*** |
+| TIMER | RT_Device_Class_Timer | ***timer[0-5]*** |
+| TIMER (Capture function) | RT_Device_Class_Miscellaneous (Input capture) | ***timer[0-5]i0*** |
+| TIMER (PWM function) | RT_Device_Class_Miscellaneous (PWM) | ***tpwm[0-5]*** |
+| TRNG | RT_Device_Class_Miscellaneous (HW Crypto) | ***hwcryto*** |
+| UART | RT_Device_Class_Char | ***uart[0-5]*** |
+| USBD | RT_Device_Class_USBDevice | ***usbd*** |
+| USBH | RT_Device_Class_USBHost | ***usbh*** |
+| USCI (I2C function) | RT_Device_Class_I2CBUS | ***ui2c[0-1]*** |
+| USCI (SPI function) | RT_Device_Class_SPIBUS | ***uspi[0-1]*** |
+| USCI (UART function) | RT_Device_Class_Char | ***uuart[0-1]*** |
+| WDT | RT_Device_Class_Miscellaneous (Watchdog) | ***wdt*** |
+
+
+## Resources
+* [Download M2354 TRM][1]
+
+  [1]: https://www.nuvoton.com/resource-download.jsp?tp_GUID=DA05-M2354
\ No newline at end of file
diff --git a/bsp/nuvoton/libraries/m2354/SConscript b/bsp/nuvoton/libraries/m2354/SConscript
new file mode 100644
index 0000000000..4c815c49b8
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/SConscript
@@ -0,0 +1,15 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/SConscript b/bsp/nuvoton/libraries/m2354/StdDriver/SConscript
new file mode 100644
index 0000000000..57025d2246
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/SConscript
@@ -0,0 +1,28 @@
+# RT-Thread building script for component
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+libs = []
+src = Glob('*src/*.c') + Glob('src/*.cpp')
+cpppath = [cwd + '/inc']
+libpath = [cwd + '/lib']
+
+if not GetDepend('BSP_USE_STDDRIVER_SOURCE'):
+	if rtconfig.CROSS_TOOL == 'keil':
+		if GetOption('target') == 'mdk5' and os.path.isfile('./lib/libstddriver_keil.lib'):
+			libs += ['libstddriver_keil']
+		elif GetOption('target') == 'mdk4' and os.path.isfile('./lib/libstddriver_keil4.lib'):
+			libs += ['libstddriver_keil4']
+	elif rtconfig.CROSS_TOOL == 'gcc' and os.path.isfile('./lib/libstddriver_gcc.a'):
+		libs += ['libstddriver_gcc']
+	elif os.path.isfile('./lib/libstddriver_iar.a'):
+		libs += ['libstddriver_iar']    
+
+if not libs:
+	group = DefineGroup('Libraries', src, depend = [''], CPPPATH = cpppath)
+else:
+	src = []
+	group = DefineGroup('Libraries', src, depend = [''], CPPPATH = cpppath, LIBS = libs, LIBPATH = libpath)
+
+Return('group')
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_acmp.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_acmp.h
new file mode 100644
index 0000000000..234e98145d
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_acmp.h
@@ -0,0 +1,382 @@
+/**************************************************************************//**
+ * @file     nu_acmp.h
+ * @version  V3.00
+ * @brief    ACMP Driver Header File
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __NU_ACMP_H__
+#define __NU_ACMP_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup ACMP_Driver ACMP Driver
+  @{
+*/
+
+
+/** @addtogroup ACMP_EXPORTED_CONSTANTS ACMP Exported Constants
+  @{
+*/
+
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* ACMP_CTL constant definitions                                                                           */
+/*---------------------------------------------------------------------------------------------------------*/
+#define ACMP_CTL_FILTSEL_OFF         (0UL << 13) /*!< ACMP_CTL setting for filter function disabled. */
+#define ACMP_CTL_FILTSEL_1PCLK       (1UL << 13) /*!< ACMP_CTL setting for 1 PCLK filter count. */
+#define ACMP_CTL_FILTSEL_2PCLK       (2UL << 13) /*!< ACMP_CTL setting for 2 PCLK filter count. */
+#define ACMP_CTL_FILTSEL_4PCLK       (3UL << 13) /*!< ACMP_CTL setting for 4 PCLK filter count. */
+#define ACMP_CTL_FILTSEL_8PCLK       (4UL << 13) /*!< ACMP_CTL setting for 8 PCLK filter count. */
+#define ACMP_CTL_FILTSEL_16PCLK      (5UL << 13) /*!< ACMP_CTL setting for 16 PCLK filter count. */
+#define ACMP_CTL_FILTSEL_32PCLK      (6UL << 13) /*!< ACMP_CTL setting for 32 PCLK filter count. */
+#define ACMP_CTL_FILTSEL_64PCLK      (7UL << 13) /*!< ACMP_CTL setting for 64 PCLK filter count. */
+#define ACMP_CTL_INTPOL_RF           (0UL << 8)  /*!< ACMP_CTL setting for selecting rising edge and falling edge as interrupt condition. */
+#define ACMP_CTL_INTPOL_R            (1UL << 8)  /*!< ACMP_CTL setting for selecting rising edge as interrupt condition. */
+#define ACMP_CTL_INTPOL_F            (2UL << 8)  /*!< ACMP_CTL setting for selecting falling edge as interrupt condition. */
+#define ACMP_CTL_POSSEL_P0           (0UL << 6)  /*!< ACMP_CTL setting for selecting ACMPx_P0 pin as the source of ACMP V+. */
+#define ACMP_CTL_POSSEL_P1           (1UL << 6)  /*!< ACMP_CTL setting for selecting ACMPx_P1 pin as the source of ACMP V+. */
+#define ACMP_CTL_POSSEL_P2           (2UL << 6)  /*!< ACMP_CTL setting for selecting ACMPx_P2 pin as the source of ACMP V+. */
+#define ACMP_CTL_POSSEL_P3           (3UL << 6)  /*!< ACMP_CTL setting for selecting ACMPx_P3 pin as the source of ACMP V+. */
+#define ACMP_CTL_NEGSEL_PIN          (0UL << 4)  /*!< ACMP_CTL setting for selecting the voltage of ACMP negative input pin as the source of ACMP V-. */
+#define ACMP_CTL_NEGSEL_CRV          (1UL << 4)  /*!< ACMP_CTL setting for selecting internal comparator reference voltage as the source of ACMP V-. */
+#define ACMP_CTL_NEGSEL_VBG          (2UL << 4)  /*!< ACMP_CTL setting for selecting internal Band-gap voltage as the source of ACMP V-. */
+#define ACMP_CTL_NEGSEL_DAC          (3UL << 4)  /*!< ACMP_CTL setting for selecting DAC output voltage as the source of ACMP V-. */
+#define ACMP_CTL_HYSTERESIS_30MV     (3UL << 24) /*!< ACMP_CTL setting for enabling the hysteresis function at 30mV. */
+#define ACMP_CTL_HYSTERESIS_20MV     (2UL << 24) /*!< ACMP_CTL setting for enabling the hysteresis function at 20mV. */
+#define ACMP_CTL_HYSTERESIS_10MV     (1UL << 24) /*!< ACMP_CTL setting for enabling the hysteresis function at 10mV. */
+#define ACMP_CTL_HYSTERESIS_DISABLE  (0UL << 2)  /*!< ACMP_CTL setting for disabling the hysteresis function. */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* ACMP_VREF constant definitions                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define ACMP_VREF_CRVSSEL_VDDA       (0UL << 6)  /*!< ACMP_VREF setting for selecting analog supply voltage VDDA as the CRV source voltage */
+#define ACMP_VREF_CRVSSEL_INTVREF    (1UL << 6)  /*!< ACMP_VREF setting for selecting internal reference voltage as the CRV source voltage */
+
+
+/**@}*/ /* end of group ACMP_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Define Macros and functions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+
+
+/**
+  * @brief This macro is used to enable output inverse function
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will set ACMPOINV bit of ACMP_CTL register to enable output inverse function.
+  */
+#define ACMP_ENABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPOINV_Msk)
+
+/**
+  * @brief This macro is used to disable output inverse function
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will clear ACMPOINV bit of ACMP_CTL register to disable output inverse function.
+  */
+#define ACMP_DISABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPOINV_Msk)
+
+/**
+  * @brief This macro is used to select ACMP negative input source
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @param[in] u32Src is comparator negative input selection. Including:
+  *                  - \ref ACMP_CTL_NEGSEL_PIN
+  *                  - \ref ACMP_CTL_NEGSEL_CRV
+  *                  - \ref ACMP_CTL_NEGSEL_VBG
+  *                  - \ref ACMP_CTL_NEGSEL_DAC
+  * @return None
+  * @details This macro will set NEGSEL (ACMP_CTL[5:4]) to determine the source of negative input.
+  */
+#define ACMP_SET_NEG_SRC(acmp, u32ChNum, u32Src) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_NEGSEL_Msk) | (u32Src))
+
+/**
+  * @brief This macro is used to enable hysteresis function
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  */
+#define ACMP_ENABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_HYSTERESIS_30MV)
+
+/**
+  * @brief This macro is used to disable hysteresis function
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will set HYSSEL of ACMP_CTL register to disable hysteresis function.
+  */
+#define ACMP_DISABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_HYSSEL_Msk)
+
+/**
+  * @brief This macro is used to select hysteresis level
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @param[in] u32HysSel The hysteresis function option. Including:
+  *                  - \ref ACMP_CTL_HYSTERESIS_30MV
+  *                  - \ref ACMP_CTL_HYSTERESIS_20MV
+  *                  - \ref ACMP_CTL_HYSTERESIS_10MV
+  *                  - \ref ACMP_CTL_HYSTERESIS_DISABLE
+  * @return None
+  */
+#define ACMP_CONFIG_HYSTERESIS(acmp, u32ChNum, u32HysSel) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_HYSSEL_Msk) | (u32HysSel))
+
+/**
+  * @brief This macro is used to enable interrupt
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will set ACMPIE bit of ACMP_CTL register to enable interrupt function.
+  *          If wake-up function is enabled, the wake-up interrupt will be enabled as well.
+  */
+#define ACMP_ENABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPIE_Msk)
+
+/**
+  * @brief This macro is used to disable interrupt
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will clear ACMPIE bit of ACMP_CTL register to disable interrupt function.
+  */
+#define ACMP_DISABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPIE_Msk)
+
+/**
+  * @brief This macro is used to enable ACMP
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will set ACMPEN bit of ACMP_CTL register to enable analog comparator.
+  */
+#define ACMP_ENABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPEN_Msk)
+
+/**
+  * @brief This macro is used to disable ACMP
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will clear ACMPEN bit of ACMP_CTL register to disable analog comparator.
+  */
+#define ACMP_DISABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPEN_Msk)
+
+/**
+  * @brief This macro is used to get ACMP output value
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return  ACMP output value
+  * @details This macro will return the ACMP output value.
+  */
+#define ACMP_GET_OUTPUT(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPO0_Msk<<((u32ChNum))))?1:0)
+
+/**
+  * @brief This macro is used to get ACMP interrupt flag
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return   ACMP interrupt occurred (1) or not (0)
+  * @details This macro will return the ACMP interrupt flag.
+  */
+#define ACMP_GET_INT_FLAG(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum))))?1:0)
+
+/**
+  * @brief This macro is used to clear ACMP interrupt flag
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return   None
+  * @details This macro will write 1 to ACMPIFn bit of ACMP_STATUS register to clear interrupt flag.
+  */
+#define ACMP_CLR_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum))))
+
+/**
+  * @brief This macro is used to clear ACMP wake-up interrupt flag
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return   None
+  * @details This macro will write 1 to WKIFn bit of ACMP_STATUS register to clear interrupt flag.
+  */
+#define ACMP_CLR_WAKEUP_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_WKIF0_Msk<<((u32ChNum))))
+
+/**
+  * @brief This macro is used to enable ACMP wake-up function
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will set WKEN (ACMP_CTL[16]) to enable ACMP wake-up function.
+  */
+#define ACMP_ENABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WKEN_Msk)
+
+/**
+  * @brief This macro is used to disable ACMP wake-up function
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will clear WKEN (ACMP_CTL[16]) to disable ACMP wake-up function.
+  */
+#define ACMP_DISABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WKEN_Msk)
+
+/**
+  * @brief This macro is used to select ACMP positive input pin
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @param[in] u32Pin Comparator positive pin selection. Including:
+  *                  - \ref ACMP_CTL_POSSEL_P0
+  *                  - \ref ACMP_CTL_POSSEL_P1
+  *                  - \ref ACMP_CTL_POSSEL_P2
+  *                  - \ref ACMP_CTL_POSSEL_P3
+  * @return None
+  * @details This macro will set POSSEL (ACMP_CTL[7:6]) to determine the comparator positive input pin.
+  */
+#define ACMP_SELECT_P(acmp, u32ChNum, u32Pin) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_POSSEL_Msk) | (u32Pin))
+
+/**
+  * @brief This macro is used to enable ACMP filter function
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will set OUTSEL (ACMP_CTL[12]) to enable output filter function.
+  */
+#define ACMP_ENABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_OUTSEL_Msk)
+
+/**
+  * @brief This macro is used to disable ACMP filter function
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will clear OUTSEL (ACMP_CTL[12]) to disable output filter function.
+  */
+#define ACMP_DISABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_OUTSEL_Msk)
+
+/**
+  * @brief This macro is used to set ACMP filter function
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @param[in] u32Cnt is comparator filter count setting.
+  *                  - \ref ACMP_CTL_FILTSEL_OFF
+  *                  - \ref ACMP_CTL_FILTSEL_1PCLK
+  *                  - \ref ACMP_CTL_FILTSEL_2PCLK
+  *                  - \ref ACMP_CTL_FILTSEL_4PCLK
+  *                  - \ref ACMP_CTL_FILTSEL_8PCLK
+  *                  - \ref ACMP_CTL_FILTSEL_16PCLK
+  *                  - \ref ACMP_CTL_FILTSEL_32PCLK
+  *                  - \ref ACMP_CTL_FILTSEL_64PCLK
+  * @return None
+  * @details When ACMP output filter function is enabled, the output sampling count is determined by FILTSEL (ACMP_CTL[15:13]).
+  */
+#define ACMP_SET_FILTER(acmp, u32ChNum, u32Cnt) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_FILTSEL_Msk) | (u32Cnt))
+
+/**
+  * @brief This macro is used to select comparator reference voltage
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32Level  The comparator reference voltage setting.
+  *             The formula is:
+  *                       comparator reference voltage = CRV source voltage x (1/6 + u32Level/24)
+  *             The range of u32Level is 0 ~ 15.
+  * @return   None
+  * @details  When CRV is selected as ACMP negative input source, the CRV level is determined by CRVCTL (ACMP_VREF[3:0]).
+  */
+#define ACMP_CRV_SEL(acmp, u32Level) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRVCTL_Msk) | ((u32Level)<VREF = ((acmp)->VREF & ~ACMP_VREF_CRVSSEL_Msk) | (u32Src))
+
+/**
+  * @brief This macro is used to select ACMP interrupt condition
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @param[in] u32Cond Comparator interrupt condition selection. Including:
+  *                  - \ref ACMP_CTL_INTPOL_RF
+  *                  - \ref ACMP_CTL_INTPOL_R
+  *                  - \ref ACMP_CTL_INTPOL_F
+  * @return None
+  * @details The ACMP output interrupt condition can be rising edge, falling edge or any edge.
+  */
+#define ACMP_SELECT_INT_COND(acmp, u32ChNum, u32Cond) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_INTPOL_Msk) | (u32Cond))
+
+/**
+  * @brief This macro is used to enable ACMP window latch mode
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will set WLATEN (ACMP_CTL[17]) to enable ACMP window latch mode.
+  *          When ACMP0/1_WLAT pin is at high level, ACMPO0/1 passes through window latch
+  *          block; when ACMP0/1_WLAT pin is at low level, the output of window latch block,
+  *          WLATOUT, is frozen.
+  */
+#define ACMP_ENABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WLATEN_Msk)
+
+/**
+  * @brief This macro is used to disable ACMP window latch mode
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will clear WLATEN (ACMP_CTL[17]) to disable ACMP window latch mode.
+  */
+#define ACMP_DISABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WLATEN_Msk)
+
+/**
+  * @brief This macro is used to enable ACMP window compare mode
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will set WCMPSEL (ACMP_CTL[18]) to enable ACMP window compare mode.
+  *          When window compare mode is enabled, user can connect the specific analog voltage
+  *          source to either the positive inputs of both comparators or the negative inputs of
+  *          both comparators. The upper bound and lower bound of the designated range are
+  *          determined by the voltages applied to the other inputs of both comparators. If the
+  *          output of a comparator is low and the other comparator outputs high, which means two
+  *          comparators implies the upper and lower bound. User can directly monitor a specific
+  *          analog voltage source via ACMPWO (ACMP_STATUS[16]).
+  */
+#define ACMP_ENABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WCMPSEL_Msk)
+
+/**
+  * @brief This macro is used to disable ACMP window compare mode
+  * @param[in] acmp The pointer of the specified ACMP module
+  * @param[in] u32ChNum The ACMP number
+  * @return None
+  * @details This macro will clear WCMPSEL (ACMP_CTL[18]) to disable ACMP window compare mode.
+  */
+#define ACMP_DISABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WCMPSEL_Msk)
+
+
+
+
+/* Function prototype declaration */
+void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysSel);
+void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum);
+
+
+/**@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */
+/**@}*/ /* end of group ACMP_Driver */
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_ACMP_H__ */
+
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_bpwm.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_bpwm.h
new file mode 100644
index 0000000000..7708a43759
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_bpwm.h
@@ -0,0 +1,360 @@
+/**************************************************************************//**
+ * @file     nu_bpwm.h
+ * @version  V1.00
+ * @brief    M2354 series BPWM driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_BPWM_H__
+#define __NU_BPWM_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup BPWM_Driver BPWM Driver
+  @{
+*/
+
+/** @addtogroup BPWM_EXPORTED_CONSTANTS BPWM Exported Constants
+  @{
+*/
+#define BPWM_CHANNEL_NUM                          (6UL)      /*!< BPWM channel number */
+#define BPWM_CH_0_MASK                            (0x1UL)    /*!< BPWM channel 0 mask \hideinitializer */
+#define BPWM_CH_1_MASK                            (0x2UL)    /*!< BPWM channel 1 mask \hideinitializer */
+#define BPWM_CH_2_MASK                            (0x4UL)    /*!< BPWM channel 2 mask \hideinitializer */
+#define BPWM_CH_3_MASK                            (0x8UL)    /*!< BPWM channel 3 mask \hideinitializer */
+#define BPWM_CH_4_MASK                            (0x10UL)   /*!< BPWM channel 4 mask \hideinitializer */
+#define BPWM_CH_5_MASK                            (0x20UL)   /*!< BPWM channel 5 mask \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Counter Type Constant Definitions                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define BPWM_UP_COUNTER                           (0UL)      /*!< Up counter type */
+#define BPWM_DOWN_COUNTER                         (1UL)      /*!< Down counter type */
+#define BPWM_UP_DOWN_COUNTER                      (2UL)      /*!< Up-Down counter type */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Aligned Type Constant Definitions                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define BPWM_EDGE_ALIGNED                         (1UL)      /*!< BPWM working in edge aligned type(down count) */
+#define BPWM_CENTER_ALIGNED                       (2UL)      /*!< BPWM working in center aligned type */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Output Level Constant Definitions                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define BPWM_OUTPUT_NOTHING                       (0UL)      /*!< BPWM output nothing */
+#define BPWM_OUTPUT_LOW                           (1UL)      /*!< BPWM output low */
+#define BPWM_OUTPUT_HIGH                          (2UL)      /*!< BPWM output high */
+#define BPWM_OUTPUT_TOGGLE                        (3UL)      /*!< BPWM output toggle */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Synchronous Start Function Control Constant Definitions                                                */
+/*---------------------------------------------------------------------------------------------------------*/
+#define BPWM_SSCTL_SSRC_PWM0                      (0UL<SSCTL = ((bpwm)->SSCTL & ~BPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | BPWM_SSCTL_SSEN0_Msk)
+
+/**
+ * @brief Disable timer synchronous start counting function of specified channel(s)
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
+ * @return None
+ * @details This macro is used to disable timer synchronous start counting function of specified channel(s).
+ * @note All channels share channel 0's setting.
+ * \hideinitializer
+ */
+#define BPWM_DISABLE_TIMER_SYNC(bpwm, u32ChannelMask) ((bpwm)->SSCTL &= ~BPWM_SSCTL_SSEN0_Msk)
+
+/**
+ * @brief This macro enable BPWM counter synchronous start counting function.
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @return None
+ * @details This macro is used to make selected BPWM0 and BPWM1 channel(s) start counting at the same time.
+ *          To configure synchronous start counting channel(s) by BPWM_ENABLE_TIMER_SYNC() and BPWM_DISABLE_TIMER_SYNC().
+ * \hideinitializer
+ */
+#define BPWM_TRIGGER_SYNC_START(bpwm) ((bpwm)->SSTRG = BPWM_SSTRG_CNTSEN_Msk)
+
+/**
+ * @brief This macro enable output inverter of specified channel(s)
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * \hideinitializer
+ */
+#define BPWM_ENABLE_OUTPUT_INVERTER(bpwm, u32ChannelMask) ((bpwm)->POLCTL = (u32ChannelMask))
+
+/**
+ * @brief This macro get captured rising data
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @return None
+ * \hideinitializer
+ */
+#define BPWM_GET_CAPTURE_RISING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].RCAPDAT)
+
+/**
+ * @brief This macro get captured falling data
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @return None
+ * \hideinitializer
+ */
+#define BPWM_GET_CAPTURE_FALLING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].FCAPDAT)
+
+/**
+ * @brief This macro mask output logic to high or low
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32LevelMask Output logic to high or low
+ * @return None
+ * @details This macro is used to mask output logic to high or low of specified channel(s).
+ * @note If u32ChannelMask parameter is 0, then mask function will be disabled.
+ * \hideinitializer
+ */
+#define BPWM_MASK_OUTPUT(bpwm, u32ChannelMask, u32LevelMask) \
+    { \
+        (bpwm)->MSKEN = (u32ChannelMask); \
+        (bpwm)->MSK = (u32LevelMask); \
+    }
+
+/**
+ * @brief This macro set the prescaler of all channels
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFFF
+ * @return None
+ * \hideinitializer
+ */
+#define BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescaler) ((bpwm)->CLKPSC = (u32Prescaler))
+
+/**
+ * @brief This macro set the duty of the selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF
+ * @return None
+ * @note This new setting will take effect on next BPWM period
+ * \hideinitializer
+ */
+#define BPWM_SET_CMR(bpwm, u32ChannelNum, u32CMR) ((bpwm)->CMPDAT[(u32ChannelNum)] = (u32CMR))
+
+/**
+ * @brief This macro get the duty of the selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @return Return the comparator of specified channel. Valid values are between 0~0xFFFF
+ * @details This macro is used to get the comparator of specified channel.
+ * \hideinitializer
+ */
+#define BPWM_GET_CMR(bpwm, u32ChannelNum) ((bpwm)->CMPDAT[(u32ChannelNum)])
+
+/**
+ * @brief This macro set the period of all channels
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
+ * @return None
+ * @note This new setting will take effect on next BPWM period
+ * @note BPWM counter will stop if period length set to 0
+ * \hideinitializer
+ */
+#define BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR) ((bpwm)->PERIOD = (u32CNR))
+
+/**
+ * @brief This macro get the period of all channels
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @return None
+ * \hideinitializer
+ */
+#define BPWM_GET_CNR(bpwm, u32ChannelNum) ((bpwm)->PERIOD)
+
+/**
+ * @brief This macro set the BPWM aligned type
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
+ * @param[in] u32AlignedType BPWM aligned type, valid values are:
+ *              - \ref BPWM_EDGE_ALIGNED
+ *              - \ref BPWM_CENTER_ALIGNED
+ * @return None
+ * @note All channels share channel 0's setting.
+ * \hideinitializer
+ */
+#define BPWM_SET_ALIGNED_TYPE(bpwm, u32ChannelMask, u32AlignedType) ((bpwm)->CTL1 = (u32AlignedType))
+
+/**
+ * @brief Clear counter of channel 0
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
+ * @return None
+ * @details This macro is used to clear counter of channel 0
+ * \hideinitializer
+ */
+#define BPWM_CLR_COUNTER(bpwm, u32ChannelMask) ((bpwm)->CNTCLR = (BPWM_CNTCLR_CNTCLR0_Msk))
+
+/**
+ * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s)
+ * @param[in] bpwm The pointer of the specified BPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32ZeroLevel output level at zero point, valid values are:
+ *              - \ref BPWM_OUTPUT_NOTHING
+ *              - \ref BPWM_OUTPUT_LOW
+ *              - \ref BPWM_OUTPUT_HIGH
+ *              - \ref BPWM_OUTPUT_TOGGLE
+ * @param[in] u32CmpUpLevel output level at compare up point, valid values are:
+ *              - \ref BPWM_OUTPUT_NOTHING
+ *              - \ref BPWM_OUTPUT_LOW
+ *              - \ref BPWM_OUTPUT_HIGH
+ *              - \ref BPWM_OUTPUT_TOGGLE
+ * @param[in] u32PeriodLevel output level at period(center) point, valid values are:
+ *              - \ref BPWM_OUTPUT_NOTHING
+ *              - \ref BPWM_OUTPUT_LOW
+ *              - \ref BPWM_OUTPUT_HIGH
+ *              - \ref BPWM_OUTPUT_TOGGLE
+ * @param[in] u32CmpDownLevel output level at compare down point, valid values are:
+ *              - \ref BPWM_OUTPUT_NOTHING
+ *              - \ref BPWM_OUTPUT_LOW
+ *              - \ref BPWM_OUTPUT_HIGH
+ *              - \ref BPWM_OUTPUT_TOGGLE
+ * @return None
+ * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s)
+ * \hideinitializer
+ */
+#define BPWM_SET_OUTPUT_LEVEL(bpwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \
+   do{ \
+        uint32_t i; \
+        for(i = 0UL; i < 6UL; i++) { \
+            if((u32ChannelMask) & (1UL << i)) { \
+                (bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (i << 1))) | ((u32ZeroLevel) << (i << 1))); \
+                (bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (BPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))) | ((u32PeriodLevel) << (BPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))); \
+                (bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (i << 1))) | ((u32CmpUpLevel) << (i << 1))); \
+                (bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (BPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))) | ((u32CmpDownLevel) << (BPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))); \
+            } \
+        } \
+    }while(0)
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define BPWM functions prototype                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge);
+uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle);
+void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask);
+void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask);
+void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask);
+void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask);
+void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask);
+void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask);
+void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask);
+void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
+void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
+uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum,  uint32_t u32IntPeriodType);
+void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
+uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
+uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
+void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
+void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel);
+uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
+void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
+
+/**@}*/ /* end of group BPWM_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group BPWM_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_BPWM_H__ */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_can.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_can.h
new file mode 100644
index 0000000000..32ee78023e
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_can.h
@@ -0,0 +1,188 @@
+/**************************************************************************//**
+ * @file     nu_can.h
+ * @version  V3.00
+ * @brief    CAN Driver Header File
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __NU_CAN_H__
+#define __NU_CAN_H__
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup CAN_Driver CAN Driver
+  @{
+*/
+
+/** @addtogroup CAN_EXPORTED_CONSTANTS CAN Exported Constants
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/* CAN Test Mode Constant Definitions                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define    CAN_NORMAL_MODE   0U    /*!< CAN select normal mode */
+#define    CAN_BASIC_MODE    1U    /*!< CAN select basic mode */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Message ID Type Constant Definitions                                                                    */
+/*---------------------------------------------------------------------------------------------------------*/
+#define    CAN_STD_ID    0UL    /*!< CAN select standard ID */
+#define    CAN_EXT_ID    1UL    /*!< CAN select extended ID */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Message Frame Type Constant Definitions                                                                 */
+/*---------------------------------------------------------------------------------------------------------*/
+#define    CAN_REMOTE_FRAME    0    /*!< CAN frame select remote frame */
+#define    CAN_DATA_FRAME    1      /*!< CAN frame select data frame */
+
+/**@}*/ /* end of group CAN_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup CAN_EXPORTED_STRUCTS CAN Exported Structs
+  @{
+*/
+/**
+  * @details    CAN message structure
+  */
+typedef struct
+{
+    uint32_t  IdType;       /*!< ID type */
+    uint32_t  FrameType;    /*!< Frame type */
+    uint32_t  Id;           /*!< Message ID */
+    uint8_t   DLC;          /*!< Data length */
+    uint8_t   Data[8];      /*!< Data */
+    uint8_t   padding[3];   /*!< Just for padding for memory alignment*/
+} STR_CANMSG_T;
+
+/**
+  * @details    CAN mask message structure
+  */
+typedef struct
+{
+    uint8_t   u8Xtd;      /*!< Extended ID */
+    uint8_t   u8Dir;      /*!< Direction */
+    uint32_t  u32Id;      /*!< Message ID */
+    uint8_t   u8IdType;   /*!< ID type*/
+} STR_CANMASK_T;
+
+/**@}*/ /* end of group CAN_EXPORTED_STRUCTS */
+
+/** @cond HIDDEN_SYMBOLS */
+#define MSG(id)  (id)
+/** @endcond HIDDEN_SYMBOLS */
+
+/** @addtogroup CAN_EXPORTED_FUNCTIONS CAN Exported Functions
+  @{
+*/
+
+/**
+ * @brief Get interrupt status.
+ *
+ * @param[in] can The base address of can module.
+ *
+ * @return CAN module status register value.
+ *
+ * @details Status Interrupt is generated by bits BOff (CAN_STATUS[7]), EWarn (CAN_STATUS[6]),
+ *          EPass (CAN_STATUS[5]), RxOk (CAN_STATUS[4]), TxOk (CAN_STATUS[3]), and LEC (CAN_STATUS[2:0]).
+ */
+#define CAN_GET_INT_STATUS(can) ((can)->STATUS)
+
+/**
+ * @brief Get specified interrupt pending status.
+ *
+ * @param[in] can The base address of can module.
+ *
+ * @return The source of the interrupt.
+ *
+ * @details If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt
+ *          with the highest priority, disregarding their chronological order.
+ */
+#define CAN_GET_INT_PENDING_STATUS(can) ((can)->IIDR)
+
+/**
+ * @brief Disable wake-up function.
+ *
+ * @param[in] can The base address of can module.
+ *
+ * @return None
+ *
+ * @details  The macro is used to disable wake-up function.
+ */
+#define CAN_DISABLE_WAKEUP(can) ((can)->WU_EN = 0)
+
+/**
+ * @brief Enable wake-up function.
+ *
+ * @param[in] can The base address of can module.
+ *
+ * @return None
+ *
+ * @details User can wake-up system when there is a falling edge in the CAN_Rx pin.
+ */
+#define CAN_ENABLE_WAKEUP(can) ((can)->WU_EN = CAN_WU_EN_WAKUP_EN_Msk)
+
+/**
+ * @brief Get specified Message Object new data into bit value.
+ *
+ * @param[in] can The base address of can module.
+ * @param[in] u32MsgNum Specified Message Object number, valid value are from 0 to 31.
+ *
+ * @return Specified Message Object new data into bit value.
+ *
+ * @details The NewDat bit (CAN_IFn_MCON[15]) of a specific Message Object can be set/reset by the software through the IFn Message Interface Registers
+ *          or by the Message Handler after reception of a Data Frame or after a successful transmission.
+ */
+#define CAN_GET_NEW_DATA_IN_BIT(can, u32MsgNum) ((u32MsgNum) < 16 ? (can)->NDAT1 & (1 << (u32MsgNum)) : (can)->NDAT2 & (1 << ((u32MsgNum)-16)))
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define CAN functions prototype                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate);
+void CAN_Close(CAN_T *tCAN);
+uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode);
+void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum);
+void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask);
+void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask);
+int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg);
+int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg);
+int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID);
+int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID);
+int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask);
+int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg);
+int32_t CAN_TriggerTxMsg(CAN_T  *tCAN, uint32_t u32MsgNum);
+void CAN_EnterInitMode(CAN_T *tCAN, uint8_t u8Mask);
+void CAN_LeaveInitMode(CAN_T *tCAN);
+void CAN_WaitMsg(CAN_T *tCAN);
+uint32_t CAN_GetCANBitRate(CAN_T *tCAN);
+void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask);
+void CAN_LeaveTestMode(CAN_T *tCAN);
+uint32_t CAN_IsNewDataReceived(CAN_T *tCAN, uint8_t u8MsgObj);
+int32_t CAN_BasicSendMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg);
+int32_t CAN_BasicReceiveMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg);
+int32_t CAN_SetRxMsgObjAndMsk(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint32_t u32idmask, uint8_t u8singleOrFifoLast);
+int32_t CAN_SetRxMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint8_t u8singleOrFifoLast);
+int32_t CAN_ReadMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8Release, STR_CANMSG_T* pCanMsg);
+
+
+/**@}*/ /* end of group CAN_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group CAN_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_CAN_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_clk.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_clk.h
new file mode 100644
index 0000000000..ff9fd8b262
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_clk.h
@@ -0,0 +1,1070 @@
+/**************************************************************************//**
+ * @file     nu_clk.h
+ * @version  V3.0
+ * @brief    Clock Controller (CLK) driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __NU_CLK_H__
+#define __NU_CLK_H__
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup CLK_Driver CLK Driver
+  @{
+*/
+
+/** @addtogroup CLK_EXPORTED_CONSTANTS CLK Exported Constants
+  @{
+*/
+
+
+#define FREQ_2MHZ          2000000UL
+#define FREQ_4MHZ          4000000UL
+#define FREQ_8MHZ          8000000UL
+#define FREQ_12MHZ         12000000UL
+#define FREQ_24MHZ         24000000UL
+#define FREQ_25MHZ         25000000UL
+#define FREQ_48MHZ         48000000UL
+#define FREQ_50MHZ         50000000UL
+#define FREQ_64MHZ         64000000UL
+#define FREQ_75MHZ         75000000UL
+#define FREQ_84MHZ         84000000UL
+#define FREQ_96MHZ         96000000UL
+#define FREQ_144MHZ        144000000UL
+#define FREQ_200MHZ        200000000UL
+
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  CLKSEL0 constant definitions.                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_CLKSEL0_HCLKSEL_HXT         (0x00UL<>30) & 0x3UL)    /*!< Calculate AHBCLK/APBCLK offset on MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 */
+#define MODULE_CLKSEL(x)        (((x) >>28) & 0x3UL)    /*!< Calculate CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 */
+#define MODULE_CLKSEL_Msk(x)    (((x) >>25) & 0x7UL)    /*!< Calculate CLKSEL mask offset on MODULE index */
+#define MODULE_CLKSEL_Pos(x)    (((x) >>20) & 0x1fUL)   /*!< Calculate CLKSEL position offset on MODULE index */
+#define MODULE_CLKDIV(x)        (((x) >>18) & 0x3UL)    /*!< Calculate APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x4:CLKDIV4 */
+#define MODULE_CLKDIV_Msk(x)    (((x) >>10) & 0xffUL)   /*!< Calculate CLKDIV mask offset on MODULE index */
+#define MODULE_CLKDIV_Pos(x)    (((x) >>5 ) & 0x1fUL)   /*!< Calculate CLKDIV position offset on MODULE index */
+#define MODULE_IP_EN_Pos(x)     (((x) >>0 ) & 0x1fUL)   /*!< Calculate APBCLK offset on MODULE index */
+#define MODULE_NoMsk            0x0UL                   /*!< Not mask on MODULE index */
+#define NA                      MODULE_NoMsk            /*!< Not Available */
+
+#define MODULE_APBCLK_ENC(x)        (((x) & 0x03UL) << 30)   /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 */
+#define MODULE_CLKSEL_ENC(x)        (((x) & 0x03UL) << 28)   /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 */
+#define MODULE_CLKSEL_Msk_ENC(x)    (((x) & 0x07UL) << 25)   /*!< CLKSEL mask offset on MODULE index */
+#define MODULE_CLKSEL_Pos_ENC(x)    (((x) & 0x1fUL) << 20)   /*!< CLKSEL position offset on MODULE index */
+#define MODULE_CLKDIV_ENC(x)        (((x) & 0x03UL) << 18)   /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV, 0x1:CLKDIV1, 0x4:CLKDIV4 */
+#define MODULE_CLKDIV_Msk_ENC(x)    (((x) & 0xffUL) << 10)   /*!< CLKDIV mask offset on MODULE index */
+#define MODULE_CLKDIV_Pos_ENC(x)    (((x) & 0x1fUL) <<  5)   /*!< CLKDIV position offset on MODULE index */
+#define MODULE_IP_EN_Pos_ENC(x)     (((x) & 0x1fUL) <<  0)   /*!< AHBCLK/APBCLK offset on MODULE index */
+
+
+/* AHBCLK */
+#define PDMA0_MODULE   (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_PDMA0CKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< PDMA Module */
+
+#define PDMA1_MODULE   (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_PDMA1CKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< PDMA Module */
+
+#define ISP_MODULE     (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_ISPCKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< ISP Module */
+
+#define EBI_MODULE     (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_EBICKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< EBI Module */
+
+#define EXST_MODULE    (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_EXSTCKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< EXST Module */
+
+#define SDH0_MODULE    (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_SDH0CKEN_Pos)|\
+                        MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC(   3UL)|MODULE_CLKSEL_Pos_ENC(20UL)|\
+                        MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0xFFUL)|MODULE_CLKDIV_Pos_ENC(24UL))/*!< SDH0 Module */
+
+#define CRC_MODULE     (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_CRCCKEN_Pos)|\
+                        MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))       /*!< CRC Module */
+
+#define CRPT_MODULE    (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_CRPTCKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< CRPT Module */
+
+#define KS_MODULE      (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_KSCKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< KS Module */
+
+#define TRACE_MODULE   (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_TRACECKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< TRACE Module */
+
+#define FMCIDLE_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_FMCIDLE_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< FMCIDLE Module */
+
+#define USBH_MODULE    (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_USBHCKEN_Pos)|\
+                        MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC(  1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\
+                        MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0xFUL)|MODULE_CLKDIV_Pos_ENC( 4UL))  /*!< USBH Module */
+
+#define SRAM0_MODULE   (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_SRAM0CKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< SRAM0 Module */
+
+#define SRAM1_MODULE   (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_SRAM1CKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< SRAM1 Module */
+
+#define SRAM2_MODULE   (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_SRAM2CKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< SRAM2 Module */
+
+#define GPA_MODULE     (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPACKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< GPA Module */
+
+#define GPB_MODULE     (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPBCKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< GPB Module */
+
+#define GPC_MODULE     (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPCCKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< GPC Module */
+
+#define GPD_MODULE     (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPDCKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< GPD Module */
+
+#define GPE_MODULE     (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPECKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< GPE Module */
+
+#define GPF_MODULE     (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPFCKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< GPF Module */
+
+#define GPG_MODULE     (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPGCKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< GPG Module */
+
+#define GPH_MODULE     (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPHCKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< GPH Module */
+
+/* APBCLK0 */
+#define WDT_MODULE     (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_WDTCKEN_Pos)|\
+                        MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 0UL)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(  NA)|MODULE_CLKDIV_Pos_ENC( NA))    /*!< WDT Module */
+
+#define WWDT_MODULE    (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_WDTCKEN_Pos)|\
+                        MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(30UL)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(  NA)|MODULE_CLKDIV_Pos_ENC(NA))     /*!< WWDT Module */
+
+#define RTC_MODULE     (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_RTCCKEN_Pos)|\
+                        MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC( NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC(NA))       /*!< RTC Module */
+
+#define TMR0_MODULE    (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR0CKEN_Pos)|\
+                        MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(  NA)|MODULE_CLKDIV_Pos_ENC(  NA))    /*!< TMR0 Module */
+
+#define TMR1_MODULE    (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR1CKEN_Pos) |\
+                        MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(   NA))     /*!< TMR1 Module */
+
+#define TMR2_MODULE    (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR2CKEN_Pos) |\
+                        MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(16UL)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(    NA))    /*!< TMR2 Module */
+
+#define TMR3_MODULE    (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR3CKEN_Pos) |\
+                        MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(20UL)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(   NA))     /*!< TMR3 Module */
+
+#define TMR4_MODULE    (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_TMR4CKEN_Pos) |\
+                        MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(8UL)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(   NA))     /*!< TMR4 Module */
+
+#define TMR5_MODULE    (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_TMR5CKEN_Pos) |\
+                        MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(   NA))     /*!< TMR5 Module */
+
+#define CLKO_MODULE    (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_CLKOCKEN_Pos) |\
+                        MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC(3UL)|MODULE_CLKSEL_Pos_ENC(28UL)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(   NA))     /*!< CLKO Module */
+
+#define ACMP01_MODULE  (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_ACMP01CKEN_Pos) |\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< ACMP01 Module */
+
+#define I2C0_MODULE    (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2C0CKEN_Pos) |\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< I2C0 Module */
+
+#define I2C1_MODULE    (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2C1CKEN_Pos) |\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< I2C1 Module */
+
+#define I2C2_MODULE    (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2C2CKEN_Pos) |\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< I2C2 Module */
+
+#define QSPI0_MODULE   (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_QSPI0CKEN_Pos) |\
+                        MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 2UL)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(  NA)|MODULE_CLKDIV_Pos_ENC(  NA))    /*!< QSPI0 Module */
+
+#define SPI0_MODULE    (MODULE_APBCLK_ENC(1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_SPI0CKEN_Pos) |\
+                        MODULE_CLKSEL_ENC(2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 4UL)|\
+                        MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(   NA)|MODULE_CLKDIV_Pos_ENC(  NA))     /*!< SPI0 Module */
+
+#define SPI1_MODULE    (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_SPI1CKEN_Pos) |\
+                        MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 6UL)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(  NA)|MODULE_CLKDIV_Pos_ENC(  NA))    /*!< SPI1 Module */
+
+#define SPI2_MODULE    (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_SPI2CKEN_Pos) |\
+                        MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(10UL)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(  NA)|MODULE_CLKDIV_Pos_ENC(  NA))    /*!< SPI2 Module */
+
+#define UART0_MODULE   (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART0CKEN_Pos)|\
+                        MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC(   7UL)|MODULE_CLKSEL_Pos_ENC(16UL)|\
+                        MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 8UL))  /*!< UART0 Module */
+
+#define UART1_MODULE   (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART1CKEN_Pos)|\
+                        MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC(   7UL)|MODULE_CLKSEL_Pos_ENC(20UL)|\
+                        MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(12UL))  /*!< UART1 Module */
+
+#define UART2_MODULE   (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART2CKEN_Pos)|\
+                        MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(24UL)|\
+                        MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 0UL))  /*!< UART2 Module */
+
+#define UART3_MODULE   (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART3CKEN_Pos)|\
+                        MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC(   7UL)|MODULE_CLKSEL_Pos_ENC(28UL)|\
+                        MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 4UL))  /*!< UART3 Module */
+
+#define UART4_MODULE   (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART4CKEN_Pos)|\
+                        MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC(   7UL)|MODULE_CLKSEL_Pos_ENC(24UL)|\
+                        MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 8UL))  /*!< UART4 Module */
+
+#define UART5_MODULE   (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART5CKEN_Pos)|\
+                        MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC(   7UL)|MODULE_CLKSEL_Pos_ENC(28UL)|\
+                        MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(12UL))  /*!< UART5 Module */
+
+#define TAMPER_MODULE  (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TAMPERCKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(  NA)|MODULE_CLKSEL_Pos_ENC(  NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(  NA)|MODULE_CLKDIV_Pos_ENC(  NA))    /*!< TAMPER Module */
+
+#define CAN0_MODULE    (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_CAN0CKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))        /*!< CAN0 Module */
+
+#define OTG_MODULE     (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_OTGCKEN_Pos)|\
+                        MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC(  1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\
+                        MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 4UL))  /*!< OTG Module */
+
+#define USBD_MODULE    (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_USBDCKEN_Pos)|\
+                        MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC(  1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\
+                        MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(4UL))   /*!< USBD Module */
+
+#define EADC_MODULE    (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_EADCCKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(    NA)|MODULE_CLKSEL_Pos_ENC(  NA)|\
+                        MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0xFFUL)|MODULE_CLKDIV_Pos_ENC(16UL))  /*!< EADC Module */
+
+#define I2S0_MODULE    (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2S0CKEN_Pos)|\
+                        MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(16UL)|\
+                        MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(   NA)|MODULE_CLKDIV_Pos_ENC(  NA))    /*!< I2S0 Module */
+
+#define EWDT_MODULE    (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_EWDTCKEN_Pos)|\
+                        MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 4UL)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(  NA)|MODULE_CLKDIV_Pos_ENC( NA))     /*!< EWDT Module */
+
+#define EWWDT_MODULE   (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_EWDTCKEN_Pos)|\
+                        MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 6UL)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(  NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< EWWDT Module */
+
+
+/* APBCLK1 */
+#define SC0_MODULE     (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SC0CKEN_Pos)  |\
+                        MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 0UL)|\
+                        MODULE_CLKDIV_ENC( 1UL)|MODULE_CLKDIV_Msk_ENC(0xFFUL)|MODULE_CLKDIV_Pos_ENC( 0UL))    /*!< SC0 Module */
+
+#define SC1_MODULE     (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SC1CKEN_Pos)  |\
+                        MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 2UL)|\
+                        MODULE_CLKDIV_ENC( 1UL)|MODULE_CLKDIV_Msk_ENC(0xFFUL)|MODULE_CLKDIV_Pos_ENC( 8UL))    /*!< SC1 Module */
+
+#define SC2_MODULE     (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SC2CKEN_Pos)  |\
+                        MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 4UL)|\
+                        MODULE_CLKDIV_ENC( 1UL)|MODULE_CLKDIV_Msk_ENC(0xFFUL)|MODULE_CLKDIV_Pos_ENC(16UL))    /*!< SC2 Module */
+
+#define SPI3_MODULE    (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SPI3CKEN_Pos)  |\
+                        MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< SPI3 Module */
+
+#define USCI0_MODULE   (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_USCI0CKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< USCI0 Module */
+
+#define USCI1_MODULE   (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_USCI1CKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< USCI1 Module */
+
+#define DAC_MODULE     (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_DACCKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< DAC Module */
+
+#define EPWM0_MODULE   (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EPWM0CKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< EPWM0 Module */
+
+#define EPWM1_MODULE   (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EPWM1CKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< EPWM1 Module */
+
+#define BPWM0_MODULE   (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_BPWM0CKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< BPWM0 Module */
+
+#define BPWM1_MODULE   (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_BPWM1CKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< BPWM1 Module */
+
+#define QEI0_MODULE    (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_QEI0CKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< QEI0 Module */
+
+#define QEI1_MODULE    (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_QEI1CKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< QEI1 Module */
+
+#define LCD_MODULE     (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_LCDCKEN_Pos)|\
+                        MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC(1UL)|MODULE_CLKSEL_Pos_ENC(2UL)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< LCD Module */
+
+#define LCDCP_MODULE   (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_LCDCPCKEN_Pos)|\
+                        MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC(1UL)|MODULE_CLKSEL_Pos_ENC(3UL)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< LCDCP Module */
+
+#define TRNG_MODULE    (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_TRNGCKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< TRNG Module */
+
+#define ECAP0_MODULE   (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_ECAP0CKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< ECAP0 Module */
+
+#define ECAP1_MODULE   (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_ECAP1CKEN_Pos)|\
+                        MODULE_CLKSEL_ENC(  NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
+                        MODULE_CLKDIV_ENC(  NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA))      /*!< ECAP1 Module */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  PDMSEL constant definitions.                                                                           */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_PMUCTL_PDMSEL_PD          (0x0UL << CLK_PMUCTL_PDMSEL_Pos)        /*!< Select Power-down mode is Power-down mode */
+#define CLK_PMUCTL_PDMSEL_LLPD        (0x1UL << CLK_PMUCTL_PDMSEL_Pos)        /*!< Select Power-down mode is Low leakage Power-down mode */
+#define CLK_PMUCTL_PDMSEL_FWPD        (0x2UL << CLK_PMUCTL_PDMSEL_Pos)        /*!< Select Power-down mode is Fast Wake-up Power-down mode */
+#define CLK_PMUCTL_PDMSEL_ULLPD       (0x3UL << CLK_PMUCTL_PDMSEL_Pos)        /*!< Select Power-down mode is Ultra Low leakage Power-down mode */
+#define CLK_PMUCTL_PDMSEL_SPD         (0x4UL << CLK_PMUCTL_PDMSEL_Pos)        /*!< Select Power-down mode is Standby Power-down mode */
+#define CLK_PMUCTL_PDMSEL_DPD         (0x6UL << CLK_PMUCTL_PDMSEL_Pos)        /*!< Select Power-down mode is Deep Power-down mode */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  WKTMRIS constant definitions.                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_PMUCTL_WKTMRIS_410          (0x0UL << CLK_PMUCTL_WKTMRIS_Pos)     /*!< Select Wake-up Timer Time-out Interval is 410 LIRC clocks (12.8 ms) */
+#define CLK_PMUCTL_WKTMRIS_819          (0x1UL << CLK_PMUCTL_WKTMRIS_Pos)     /*!< Select Wake-up Timer Time-out Interval is 819 LIRC clocks (25.6 ms) */
+#define CLK_PMUCTL_WKTMRIS_1638         (0x2UL << CLK_PMUCTL_WKTMRIS_Pos)     /*!< Select Wake-up Timer Time-out Interval is 1638 LIRC clocks (51.2 ms) */
+#define CLK_PMUCTL_WKTMRIS_3277         (0x3UL << CLK_PMUCTL_WKTMRIS_Pos)     /*!< Select Wake-up Timer Time-out Interval is 3277 LIRC clocks (102.4ms) */
+#define CLK_PMUCTL_WKTMRIS_13107        (0x4UL << CLK_PMUCTL_WKTMRIS_Pos)     /*!< Select Wake-up Timer Time-out Interval is 13107 LIRC clocks (409.6ms) */
+#define CLK_PMUCTL_WKTMRIS_26214        (0x5UL << CLK_PMUCTL_WKTMRIS_Pos)     /*!< Select Wake-up Timer Time-out Interval is 26214 LIRC clocks (819.2ms) */
+#define CLK_PMUCTL_WKTMRIS_52429        (0x6UL << CLK_PMUCTL_WKTMRIS_Pos)     /*!< Select Wake-up Timer Time-out Interval is 52429 LIRC clocks (1638.4ms) */
+#define CLK_PMUCTL_WKTMRIS_209715       (0x7UL << CLK_PMUCTL_WKTMRIS_Pos)     /*!< Select Wake-up Timer Time-out Interval is 209715 LIRC clocks (6553.6ms) */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  SWKDBCLKSEL constant definitions.                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_SWKDBCTL_SWKDBCLKSEL_1          (0x0UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 1 clocks */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_2          (0x1UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2 clocks */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_4          (0x2UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4 clocks */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_8          (0x3UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8 clocks */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_16         (0x4UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16 clocks */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_32         (0x5UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32 clocks */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_64         (0x6UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64 clocks */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_128        (0x7UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128 clocks */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_256        (0x8UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 256 clocks */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_2x256      (0x9UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2x256 clocks */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_4x256      (0xaUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4x256 clocks */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_8x256      (0xbUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8x256 clocks */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_16x256     (0xcUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16x256 clocks */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_32x256     (0xdUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32x256 clocks */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_64x256     (0xeUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64x256 clocks */
+#define CLK_SWKDBCTL_SWKDBCLKSEL_128x256    (0xfUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos)     /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128x256 clocks */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  DPD Pin Rising/Falling Edge Wake-up Enable constant definitions.                                       */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_DPDWKPIN_DISABLE     (0x0UL << CLK_PMUCTL_WKPINEN_Pos)     /*!< Disable Wake-up pin (GPC.0) at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN_RISING      (0x1UL << CLK_PMUCTL_WKPINEN_Pos)     /*!< Enable Wake-up pin (GPC.0) rising edge at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN_FALLING     (0x2UL << CLK_PMUCTL_WKPINEN_Pos)     /*!< Enable Wake-up pin (GPC.0) falling edge at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN_BOTHEDGE    (0x3UL << CLK_PMUCTL_WKPINEN_Pos)     /*!< Enable Wake-up pin (GPC.0) both edge at Deep Power-down mode \hideinitializer */
+
+#define CLK_DPDWKPIN0_DISABLE    (0x0UL << CLK_PMUCTL_WKPINEN_Pos)     /*!< Disable Wake-up pin0 (GPC.0) at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN0_RISING     (0x1UL << CLK_PMUCTL_WKPINEN_Pos)     /*!< Enable Wake-up pin0 (GPC.0) rising edge at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN0_FALLING    (0x2UL << CLK_PMUCTL_WKPINEN_Pos)     /*!< Enable Wake-up pin0 (GPC.0) falling edge at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN0_BOTHEDGE   (0x3UL << CLK_PMUCTL_WKPINEN_Pos)     /*!< Enable Wake-up pin0 (GPC.0) both edge at Deep Power-down mode \hideinitializer */
+
+#define CLK_DPDWKPIN1_DISABLE    (0x0UL << CLK_PMUCTL_WKPINEN1_Pos)    /*!< Disable Wake-up pin1 (GPB.0) at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN1_RISING     (0x1UL << CLK_PMUCTL_WKPINEN1_Pos)    /*!< Enable Wake-up pin1 (GPB.0) rising edge at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN1_FALLING    (0x2UL << CLK_PMUCTL_WKPINEN1_Pos)    /*!< Enable Wake-up pin1 (GPB.0) falling edge at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN1_BOTHEDGE   (0x3UL << CLK_PMUCTL_WKPINEN1_Pos)    /*!< Enable Wake-up pin1 (GPB.0) both edge at Deep Power-down mode \hideinitializer */
+
+#define CLK_DPDWKPIN2_DISABLE    (0x0UL << CLK_PMUCTL_WKPINEN2_Pos)    /*!< Disable Wake-up pin2 (GPB.2) at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN2_RISING     (0x1UL << CLK_PMUCTL_WKPINEN2_Pos)    /*!< Enable Wake-up pin2 (GPB.2) rising edge at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN2_FALLING    (0x2UL << CLK_PMUCTL_WKPINEN2_Pos)    /*!< Enable Wake-up pin2 (GPB.2) falling edge at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN2_BOTHEDGE   (0x3UL << CLK_PMUCTL_WKPINEN2_Pos)    /*!< Enable Wake-up pin2 (GPB.2) both edge at Deep Power-down mode \hideinitializer */
+
+#define CLK_DPDWKPIN3_DISABLE    (0x0UL << CLK_PMUCTL_WKPINEN3_Pos)    /*!< Disable Wake-up pin3 (GPB.12) at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN3_RISING     (0x1UL << CLK_PMUCTL_WKPINEN3_Pos)    /*!< Enable Wake-up pin3 (GPB.12) rising edge at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN3_FALLING    (0x2UL << CLK_PMUCTL_WKPINEN3_Pos)    /*!< Enable Wake-up pin3 (GPB.12) falling edge at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN3_BOTHEDGE   (0x3UL << CLK_PMUCTL_WKPINEN3_Pos)    /*!< Enable Wake-up pin3 (GPB.12) both edge at Deep Power-down mode \hideinitializer */
+
+#define CLK_DPDWKPIN4_DISABLE    (0x0UL << CLK_PMUCTL_WKPINEN4_Pos)    /*!< Disable Wake-up pin4 (GPF.6) at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN4_RISING     (0x1UL << CLK_PMUCTL_WKPINEN4_Pos)    /*!< Enable Wake-up pin4 (GPF.6) rising edge at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN4_FALLING    (0x2UL << CLK_PMUCTL_WKPINEN4_Pos)    /*!< Enable Wake-up pin4 (GPF.6) falling edge at Deep Power-down mode \hideinitializer */
+#define CLK_DPDWKPIN4_BOTHEDGE   (0x3UL << CLK_PMUCTL_WKPINEN4_Pos)    /*!< Enable Wake-up pin4 (GPF.6) both edge at Deep Power-down mode \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  SPD Pin Rising/Falling Edge Wake-up Enable constant definitions.                                       */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CLK_SPDWKPIN_ENABLE         (0x1UL << 0)     /*!< Enable Standby Power-down Pin Wake-up */
+#define CLK_SPDWKPIN_RISING         (0x1UL << 1)     /*!< Standby Power-down Wake-up on Standby Power-down Pin rising edge */
+#define CLK_SPDWKPIN_FALLING        (0x1UL << 2)     /*!< Standby Power-down Wake-up on Standby Power-down Pin falling edge */
+#define CLK_SPDWKPIN_DEBOUNCEEN     (0x1UL << 8)     /*!< Enable Standby power-down pin De-bounce function */
+#define CLK_SPDWKPIN_DEBOUNCEDIS    (0x0UL << 8)     /*!< Disable Standby power-down pin De-bounce function */
+
+
+/**@}*/ /* end of group CLK_EXPORTED_CONSTANTS */
+
+/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Disable Wake-up Timer
+  * @param      None
+  * @return     None
+  * @details    This macro disables Wake-up timer at Standby or Deep Power-down mode.
+  */
+#define CLK_DISABLE_WKTMR() \
+    do{ \
+        while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \
+        CLK->PMUCTL &= ~CLK_PMUCTL_WKTMREN_Msk; \
+    }while(0)
+
+/**
+  * @brief      Enable Wake-up Timer
+  * @param      None
+  * @return     None
+  * @details    This macro enables Wake-up timer at Standby or Deep Power-down mode.
+  */
+#define CLK_ENABLE_WKTMR() \
+    do{ \
+        while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \
+        CLK->PMUCTL |= CLK_PMUCTL_WKTMREN_Msk; \
+    }while(0)
+
+/**
+  * @brief      Disable DPD Mode Wake-up Pin
+  * @param      None
+  * @return     None
+  * @details    This macro disables Wake-up pin at Deep Power-down mode.
+  */
+#define CLK_DISABLE_DPDWKPIN() \
+    do{ \
+        while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \
+        CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN_Msk; \
+    }while(0)
+
+/**
+  * @brief      Disable DPD Mode Wake-up Pin 0
+  * @param      None
+  * @return     None
+  * @details    This macro disables Wake-up pin 0 (GPC.0) at Deep Power-down mode.
+  */
+#define CLK_DISABLE_DPDWKPIN0() \
+    do{ \
+        while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \
+        CLK->PMUCTL &= ~CLK_PMUCTL_WKPIN0EN_Msk; \
+    }while(0)
+
+/**
+  * @brief      Disable DPD Mode Wake-up Pin 1
+  * @param      None
+  * @return     None
+  * @details    This macro disables Wake-up pin 1 (GPB.0) at Deep Power-down mode.
+  */
+#define CLK_DISABLE_DPDWKPIN1() \
+    do{ \
+        while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \
+        CLK->PMUCTL &= ~CLK_PMUCTL_WKPIN1EN_Msk; \
+    }while(0)
+
+/**
+  * @brief      Disable DPD Mode Wake-up Pin 2
+  * @param      None
+  * @return     None
+  * @details    This macro disables Wake-up pin 2 (GPB.2) at Deep Power-down mode.
+  */
+#define CLK_DISABLE_DPDWKPIN2() \
+    do{ \
+        while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \
+        CLK->PMUCTL &= ~CLK_PMUCTL_WKPIN2EN_Msk; \
+    }while(0)
+
+/**
+  * @brief      Disable DPD Mode Wake-up Pin 3
+  * @param      None
+  * @return     None
+  * @details    This macro disables Wake-up pin 3 (GPB.12) at Deep Power-down mode.
+  */
+#define CLK_DISABLE_DPDWKPIN3() \
+    do{ \
+        while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \
+        CLK->PMUCTL &= ~CLK_PMUCTL_WKPIN3EN_Msk; \
+    }while(0)
+
+/**
+  * @brief      Disable DPD Mode Wake-up Pin 4
+  * @param      None
+  * @return     None
+  * @details    This macro disables Wake-up pin 4 (GPF.6) at Deep Power-down mode.
+  */
+#define CLK_DISABLE_DPDWKPIN4() \
+    do{ \
+        while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \
+        CLK->PMUCTL &= ~CLK_PMUCTL_WKPIN4EN_Msk; \
+    }while(0)
+
+/**
+  * @brief      Disable SPD Mode ACMP Wake-up
+  * @param      None
+  * @return     None
+  * @details    This macro disables ACMP wake-up at Standby Power-down mode.
+  */
+#define CLK_DISABLE_SPDACMP() \
+    do{ \
+        while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \
+        CLK->PMUCTL &= ~CLK_PMUCTL_ACMPSPWK_Msk; \
+    }while(0)
+
+/**
+  * @brief      Enable SPD Mode ACMP Wake-up
+  * @param      None
+  * @return     None
+  * @details    This macro enables ACMP wake-up at Standby Power-down mode.
+  */
+#define CLK_ENABLE_SPDACMP() \
+    do{ \
+        while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \
+        CLK->PMUCTL |= CLK_PMUCTL_ACMPSPWK_Msk; \
+    }while(0)
+
+/**
+  * @brief      Disable SPD and DPD Mode RTC Wake-up
+  * @param      None
+  * @return     None
+  * @details    This macro disables RTC Wake-up at Standby or Deep Power-down mode.
+  */
+#define CLK_DISABLE_RTCWK() \
+    do{ \
+        while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \
+        CLK->PMUCTL &= ~CLK_PMUCTL_RTCWKEN_Msk; \
+    }while(0)
+
+/**
+  * @brief      Enable SPD and DPD Mode RTC Wake-up
+  * @param      None
+  * @return     None
+  * @details    This macro enables RTC Wake-up at Standby or Deep Power-down mode.
+  */
+#define CLK_ENABLE_RTCWK() \
+    do{ \
+        while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \
+        CLK->PMUCTL |= CLK_PMUCTL_RTCWKEN_Msk; \
+    }while(0)
+
+/**
+ * @brief       Set Wake-up Timer Time-out Interval
+ *
+ * @param[in]   u32Interval  The Wake-up Timer Time-out Interval selection. It could be
+ *                             - \ref CLK_PMUCTL_WKTMRIS_410
+ *                             - \ref CLK_PMUCTL_WKTMRIS_819
+ *                             - \ref CLK_PMUCTL_WKTMRIS_1638
+ *                             - \ref CLK_PMUCTL_WKTMRIS_3277
+ *                             - \ref CLK_PMUCTL_WKTMRIS_13107
+ *                             - \ref CLK_PMUCTL_WKTMRIS_26214
+ *                             - \ref CLK_PMUCTL_WKTMRIS_52429
+ *                             - \ref CLK_PMUCTL_WKTMRIS_209715
+ *
+ * @return      None
+ *
+ * @details     This function set Wake-up Timer Time-out Interval.
+ *
+ *
+ */
+#define CLK_SET_WKTMR_INTERVAL(u32Interval) \
+   do{ \
+        while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \
+        CLK->PMUCTL = (CLK->PMUCTL & (~CLK_PMUCTL_WKTMRIS_Msk)) | (u32Interval); \
+    }while(0)
+
+/**
+ * @brief       Set De-bounce Sampling Cycle Time
+ *
+ * @param[in]   u32CycleSel   The de-bounce sampling cycle selection. It could be
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_1
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_256
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2x256
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4x256
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8x256
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16x256
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32x256
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64x256
+ *                             - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128x256
+ *
+ * @return      None
+ *
+ * @details     This function set Set De-bounce Sampling Cycle Time for Standby Power-down pin wake-up.
+ *
+ *
+ */
+#define CLK_SET_SPDDEBOUNCETIME(u32CycleSel)    (CLK->SWKDBCTL = (u32CycleSel))
+
+/**
+  * @brief      Disable SPD Mode Tamper Wake-up
+  * @param      None
+  * @return     None
+  * @details    This macro disables tamper Wake-up at Standby Power-down mode.
+  */
+#define CLK_DISABLE_SPDTAMPER() \
+    do{ \
+        while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \
+        CLK->PMUCTL &= ~CLK_PMUCTL_TAMPERWK_Msk; \
+    }while(0)
+
+/**
+  * @brief      Enable SPD and DPD Mode RTC Wake-up
+  * @param      None
+  * @return     None
+  * @details    This macro enables tamper Wake-up at Standby Power-down mode.
+  */
+#define CLK_ENABLE_SPDTAMPER() \
+    do{ \
+        while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \
+        CLK->PMUCTL |= CLK_PMUCTL_TAMPERWK_Msk; \
+    }while(0)
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* static inline functions                                                                                 */
+/*---------------------------------------------------------------------------------------------------------*/
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
+__STATIC_INLINE void CLK_SysTickDelay(uint32_t us);
+__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us);
+
+
+/**
+  * @brief      This function execute delay function.
+  * @param[in]  us  Delay time. The Max value is (2^24-1) / CPU Clock(MHz). Ex:
+  *                             96MHz => 174762us, 84MHz => 199728us,
+  *                             64MHz => 262143us, 48MHz => 349525us ...
+  * @return     None
+  * @details    Use the SysTick to generate the delay time and the UNIT is in us.
+  *             The SysTick clock source is from HCLK, i.e the same as system core clock.
+  *             User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function.
+  */
+__STATIC_INLINE void CLK_SysTickDelay(uint32_t us)
+{
+    SysTick->LOAD = us * CyclesPerUs;
+    SysTick->VAL  = (0x0UL);
+    SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
+
+    /* Waiting for down-count to zero */
+    while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL)
+    {
+    }
+
+    /* Disable SysTick counter */
+    SysTick->CTRL = 0UL;
+}
+
+/**
+  * @brief      This function execute long delay function.
+  * @param[in]  us  Delay time.
+  * @return     None
+  * @details    Use the SysTick to generate the long delay time and the UNIT is in us.
+  *             The SysTick clock source is from HCLK, i.e the same as system core clock.
+  *             User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function.
+  */
+__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us)
+{
+    uint32_t u32Delay;
+
+    /* It should <= 65536us for each delay loop */
+    u32Delay = 65536UL;
+
+    do
+    {
+        if(us > u32Delay)
+        {
+            us -= u32Delay;
+        }
+        else
+        {
+            u32Delay = us;
+            us = 0UL;
+        }
+
+        SysTick->LOAD = u32Delay * CyclesPerUs;
+        SysTick->VAL  = (0x0UL);
+        SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
+
+        /* Waiting for down-count to zero */
+        while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL);
+
+        /* Disable SysTick counter */
+        SysTick->CTRL = 0UL;
+
+    }
+    while(us > 0UL);
+
+}
+
+
+void CLK_DisableCKO(void);
+void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
+void CLK_PowerDown(void);
+void CLK_Idle(void);
+uint32_t CLK_GetHXTFreq(void);
+uint32_t CLK_GetLXTFreq(void);
+uint32_t CLK_GetHCLKFreq(void);
+uint32_t CLK_GetPCLK0Freq(void);
+uint32_t CLK_GetPCLK1Freq(void);
+uint32_t CLK_GetCPUFreq(void);
+uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
+void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
+void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
+void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);
+void CLK_EnableXtalRC(uint32_t u32ClkMask);
+void CLK_DisableXtalRC(uint32_t u32ClkMask);
+void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
+void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
+uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
+void CLK_DisablePLL(void);
+uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
+void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
+void CLK_DisableSysTick(void);
+void CLK_SetPowerDownMode(uint32_t u32PDMode);
+void CLK_EnableDPDWKPin(uint32_t u32TriggerType);
+uint32_t CLK_GetPMUWKSrc(void);
+void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn);
+uint32_t CLK_GetPLLClockFreq(void);
+uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx);
+uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx);
+
+
+/**@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group CLK_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __NU_CLK_H__ */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_crc.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_crc.h
new file mode 100644
index 0000000000..7a00089e1a
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_crc.h
@@ -0,0 +1,115 @@
+/**************************************************************************//**
+ * @file     nu_crc.h
+ * @version  V3.00
+ * @brief    Cyclic Redundancy Check(CRC) driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_CRC_H__
+#define __NU_CRC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup CRC_Driver CRC Driver
+  @{
+*/
+
+/** @addtogroup CRC_EXPORTED_CONSTANTS CRC Exported Constants
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/*  CRC Polynomial Mode Constant Definitions                                                               */
+/*---------------------------------------------------------------------------------------------------------*/
+#define CRC_CCITT           (0UL << CRC_CTL_CRCMODE_Pos) /*!SEED = (u32Seed); (crc)->CTL |= CRC_CTL_CHKSINIT_Msk; } while(0)
+
+/**
+  * @brief      Get CRC Seed Value
+  *
+  * @param[in]  crc         The pointer of CRC module.
+  *
+  * @return     CRC seed value
+  *
+  * @details    This macro gets the current CRC seed value.
+ * \hideinitializer
+  */
+#define CRC_GET_SEED(crc)                   ((crc)->SEED)
+
+/**
+  * @brief      CRC Write Data
+  *
+  * @param[in]  crc         The pointer of CRC module.
+  * @param[in]  u32Data     Write data
+  *
+  * @return     None
+  *
+  * @details    User can write data directly to CRC Write Data Register(CRC_DAT) by this macro to perform CRC operation.
+ * \hideinitializer
+  */
+#define CRC_WRITE_DATA(crc, u32Data)        ((crc)->DAT = (u32Data))
+
+
+void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen);
+uint32_t CRC_GetChecksum(void);
+
+/**@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group CRC_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_CRC_H__ */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_crypto.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_crypto.h
new file mode 100644
index 0000000000..eebd671d6e
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_crypto.h
@@ -0,0 +1,559 @@
+/**************************************************************************//**
+ * @file     nu_crypto.h
+ * @version  V3.00
+ * @brief    Cryptographic Accelerator driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __NU_CRYPTO_H__
+#define __NU_CRYPTO_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup CRYPTO_Driver CRYPTO Driver
+  @{
+*/
+
+
+/** @addtogroup CRYPTO_EXPORTED_CONSTANTS CRYPTO Exported Constants
+  @{
+*/
+
+
+#define PRNG_KEY_SIZE_128       ( 0UL)     /*!< Select to generate 128-bit random key   \hideinitializer */
+#define PRNG_KEY_SIZE_163       ( 1UL)     /*!< Select to generate 163-bit random key   \hideinitializer */
+#define PRNG_KEY_SIZE_192       ( 2UL)     /*!< Select to generate 192-bit random key   \hideinitializer */
+#define PRNG_KEY_SIZE_224       ( 3UL)     /*!< Select to generate 224-bit random key   \hideinitializer */
+#define PRNG_KEY_SIZE_255       ( 4UL)     /*!< Select to generate 255-bit random key   \hideinitializer */
+#define PRNG_KEY_SIZE_256       ( 6UL)     /*!< Select to generate 256-bit random key   \hideinitializer */
+#define PRNG_KEY_SIZE_283       ( 7UL)     /*!< Select to generate 283-bit random key (Key Store Only)  \hideinitializer */
+#define PRNG_KEY_SIZE_384       ( 8UL)     /*!< Select to generate 384-bit random key (Key Store Only)  \hideinitializer */
+#define PRNG_KEY_SIZE_409       ( 9UL)     /*!< Select to generate 409-bit random key (Key Store Only)  \hideinitializer */
+#define PRNG_KEY_SIZE_512       (10UL)     /*!< Select to generate 512-bit random key (Key Store Only)  \hideinitializer */
+#define PRNG_KEY_SIZE_521       (11UL)     /*!< Select to generate 521-bit random key (Key Store Only)  \hideinitializer */
+#define PRNG_KEY_SIZE_571       (12UL)     /*!< Select to generate 571-bit random key (Key Store Only)  \hideinitializer */
+
+#define PRNG_SEED_CONT          (0UL)     /*!< PRNG using current seed                 \hideinitializer */
+#define PRNG_SEED_RELOAD        (1UL)     /*!< PRNG reload new seed                    \hideinitializer */
+
+#define AES_KEY_SIZE_128        (0UL)     /*!< AES select 128-bit key length           \hideinitializer */
+#define AES_KEY_SIZE_192        (1UL)     /*!< AES select 192-bit key length           \hideinitializer */
+#define AES_KEY_SIZE_256        (2UL)     /*!< AES select 256-bit key length           \hideinitializer */
+
+#define AES_MODE_ECB            (0UL)     /*!< AES select ECB mode                     \hideinitializer */
+#define AES_MODE_CBC            (1UL)     /*!< AES select CBC mode                     \hideinitializer */
+#define AES_MODE_CFB            (2UL)     /*!< AES select CFB mode                     \hideinitializer */
+#define AES_MODE_OFB            (3UL)     /*!< AES select OFB mode                     \hideinitializer */
+#define AES_MODE_CTR            (4UL)     /*!< AES select CTR mode                     \hideinitializer */
+#define AES_MODE_CBC_CS1        (0x10UL)  /*!< AES select CBC CS1 mode                 \hideinitializer */
+#define AES_MODE_CBC_CS2        (0x11UL)  /*!< AES select CBC CS2 mode                 \hideinitializer */
+#define AES_MODE_CBC_CS3        (0x12UL)  /*!< AES select CBC CS3 mode                 \hideinitializer */
+#define AES_MODE_GCM            (0x20UL)
+#define AES_MODE_GHASH          (0x21UL)
+#define AES_MODE_CCM            (0x22UL)
+
+#define SM4_MODE_ECB            (0x200UL)     /*!< SM4 select ECB mode                     \hideinitializer */
+#define SM4_MODE_CBC            (0x201UL)     /*!< SM4 select CBC mode                     \hideinitializer */
+#define SM4_MODE_CFB            (0x202UL)     /*!< SM4 select CFB mode                     \hideinitializer */
+#define SM4_MODE_OFB            (0x203UL)     /*!< SM4 select OFB mode                     \hideinitializer */
+#define SM4_MODE_CTR            (0x204UL)     /*!< SM4 select CTR mode                     \hideinitializer */
+#define SM4_MODE_CBC_CS1        (0x210UL)     /*!< SM4 select CBC CS1 mode                 \hideinitializer */
+#define SM4_MODE_CBC_CS2        (0x211UL)     /*!< SM4 select CBC CS2 mode                 \hideinitializer */
+#define SM4_MODE_CBC_CS3        (0x212UL)     /*!< SM4 select CBC CS3 mode                 \hideinitializer */
+#define SM4_MODE_GCM            (0x220UL)
+#define SM4_MODE_GHASH          (0x221UL)
+#define SM4_MODE_CCM            (0x222UL)
+
+
+#define AES_NO_SWAP             (0UL)     /*!< AES do not swap input and output data   \hideinitializer */
+#define AES_OUT_SWAP            (1UL)     /*!< AES swap output data                    \hideinitializer */
+#define AES_IN_SWAP             (2UL)     /*!< AES swap input data                     \hideinitializer */
+#define AES_IN_OUT_SWAP         (3UL)     /*!< AES swap both input and output data     \hideinitializer */
+
+#define DES_MODE_ECB            (0x000UL) /*!< DES select ECB mode                     \hideinitializer */
+#define DES_MODE_CBC            (0x100UL) /*!< DES select CBC mode                     \hideinitializer */
+#define DES_MODE_CFB            (0x200UL) /*!< DES select CFB mode                     \hideinitializer */
+#define DES_MODE_OFB            (0x300UL) /*!< DES select OFB mode                     \hideinitializer */
+#define DES_MODE_CTR            (0x400UL) /*!< DES select CTR mode                     \hideinitializer */
+#define TDES_MODE_ECB           (0x004UL) /*!< TDES select ECB mode                    \hideinitializer */
+#define TDES_MODE_CBC           (0x104UL) /*!< TDES select CBC mode                    \hideinitializer */
+#define TDES_MODE_CFB           (0x204UL) /*!< TDES select CFB mode                    \hideinitializer */
+#define TDES_MODE_OFB           (0x304UL) /*!< TDES select OFB mode                    \hideinitializer */
+#define TDES_MODE_CTR           (0x404UL) /*!< TDES select CTR mode                    \hideinitializer */
+
+#define TDES_NO_SWAP            (0UL)     /*!< TDES do not swap data                       \hideinitializer */
+#define TDES_WHL_SWAP           (1UL)     /*!< TDES swap high-low word                     \hideinitializer */
+#define TDES_OUT_SWAP           (2UL)     /*!< TDES swap output data                       \hideinitializer */
+#define TDES_OUT_WHL_SWAP       (3UL)     /*!< TDES swap output data and high-low word     \hideinitializer */
+#define TDES_IN_SWAP            (4UL)     /*!< TDES swap input data                        \hideinitializer */
+#define TDES_IN_WHL_SWAP        (5UL)     /*!< TDES swap input data and high-low word      \hideinitializer */
+#define TDES_IN_OUT_SWAP        (6UL)     /*!< TDES swap both input and output data        \hideinitializer */
+#define TDES_IN_OUT_WHL_SWAP    (7UL)     /*!< TDES swap input, output and high-low word   \hideinitializer */
+
+#define SHA_MODE_SHA1           (0UL)     /*!< SHA select SHA-1 160-bit                \hideinitializer */
+#define SHA_MODE_SHA224         (5UL)     /*!< SHA select SHA-224 224-bit              \hideinitializer */
+#define SHA_MODE_SHA256         (4UL)     /*!< SHA select SHA-256 256-bit              \hideinitializer */
+#define SHA_MODE_SHA384         (7UL)     /*!< SHA select SHA-384 384-bit              \hideinitializer */
+#define SHA_MODE_SHA512         (6UL)     /*!< SHA select SHA-512 512-bit              \hideinitializer */
+
+#define HMAC_MODE_SHA1          (8UL)     /*!< HMAC select SHA-1 160-bit                \hideinitializer */
+#define HMAC_MODE_SHA224        (13UL)    /*!< HMAC select SHA-224 224-bit              \hideinitializer */
+#define HMAC_MODE_SHA256        (12UL)    /*!< HMAC select SHA-256 256-bit              \hideinitializer */
+#define HMAC_MODE_SHA384        (15UL)    /*!< HMAC select SHA-384 384-bit              \hideinitializer */
+#define HMAC_MODE_SHA512        (14UL)    /*!< HMAC select SHA-512 512-bit              \hideinitializer */
+
+
+#define SHA_NO_SWAP             (0UL)     /*!< SHA do not swap input and output data   \hideinitializer */
+#define SHA_OUT_SWAP            (1UL)     /*!< SHA swap output data                    \hideinitializer */
+#define SHA_IN_SWAP             (2UL)     /*!< SHA swap input data                     \hideinitializer */
+#define SHA_IN_OUT_SWAP         (3UL)     /*!< SHA swap both input and output data     \hideinitializer */
+
+#define CRYPTO_DMA_FIRST        (0x4UL)   /*!< Do first encrypt/decrypt in DMA cascade \hideinitializer */
+#define CRYPTO_DMA_ONE_SHOT     (0x5UL)   /*!< Do one shot encrypt/decrypt with DMA      \hideinitializer */
+#define CRYPTO_DMA_CONTINUE     (0x6UL)   /*!< Do continuous encrypt/decrypt in DMA cascade \hideinitializer */
+#define CRYPTO_DMA_LAST         (0x7UL)   /*!< Do last encrypt/decrypt in DMA cascade          \hideinitializer */
+
+//---------------------------------------------------
+
+#define RSA_MAX_KLEN            (4096)
+#define RSA_KBUF_HLEN           (RSA_MAX_KLEN/4 + 8)
+#define RSA_KBUF_BLEN           (RSA_MAX_KLEN + 32)
+
+#define RSA_KEY_SIZE_1024       (0UL)     /*!< RSA select 1024-bit key length           \hideinitializer */
+#define RSA_KEY_SIZE_2048       (1UL)     /*!< RSA select 2048-bit key length           \hideinitializer */
+#define RSA_KEY_SIZE_3072       (2UL)     /*!< RSA select 3072-bit key length           \hideinitializer */
+#define RSA_KEY_SIZE_4096       (3UL)     /*!< RSA select 4096-bit key length           \hideinitializer */
+
+#define RSA_MODE_NORMAL         (0x000UL)     /*!< RSA select normal mode                \hideinitializer */
+#define RSA_MODE_CRT            (0x004UL)     /*!< RSA select CRT mode                   \hideinitializer */
+#define RSA_MODE_CRTBYPASS      (0x00CUL)     /*!< RSA select CRT bypass mode            \hideinitializer */
+#define RSA_MODE_SCAP           (0x100UL)     /*!< RSA select SCAP mode                  \hideinitializer */
+#define RSA_MODE_CRT_SCAP       (0x104UL)     /*!< RSA select CRT SCAP mode              \hideinitializer */
+#define RSA_MODE_CRTBYPASS_SCAP (0x10CUL)     /*!< RSA select CRT bypass SCAP mode       \hideinitializer */
+
+
+typedef enum
+{
+    /*!< ECC curve                \hideinitializer */
+    CURVE_P_192,                        /*!< ECC curve P-192          \hideinitializer */
+    CURVE_P_224,                        /*!< ECC curve P-224          \hideinitializer */
+    CURVE_P_256,                        /*!< ECC curve P-256          \hideinitializer */
+    CURVE_P_384,                        /*!< ECC curve P-384          \hideinitializer */
+    CURVE_P_521,                        /*!< ECC curve P-521          \hideinitializer */
+    CURVE_K_163,                        /*!< ECC curve K-163          \hideinitializer */
+    CURVE_K_233,                        /*!< ECC curve K-233          \hideinitializer */
+    CURVE_K_283,                        /*!< ECC curve K-283          \hideinitializer */
+    CURVE_K_409,                        /*!< ECC curve K-409          \hideinitializer */
+    CURVE_K_571,                        /*!< ECC curve K-571          \hideinitializer */
+    CURVE_B_163,                        /*!< ECC curve B-163          \hideinitializer */
+    CURVE_B_233,                        /*!< ECC curve B-233          \hideinitializer */
+    CURVE_B_283,                        /*!< ECC curve B-283          \hideinitializer */
+    CURVE_B_409,                        /*!< ECC curve B-409          \hideinitializer */
+    CURVE_B_571,                        /*!< ECC curve K-571          \hideinitializer */
+    CURVE_KO_192,                       /*!< ECC 192-bits "Koblitz" curve   \hideinitializer */
+    CURVE_KO_224,                       /*!< ECC 224-bits "Koblitz" curve   \hideinitializer */
+    CURVE_KO_256,                       /*!< ECC 256-bits "Koblitz" curve   \hideinitializer */
+    CURVE_BP_256,                       /*!< ECC Brainpool 256-bits curve   \hideinitializer */
+    CURVE_BP_384,                       /*!< ECC Brainpool 256-bits curve   \hideinitializer */
+    CURVE_BP_512,                       /*!< ECC Brainpool 256-bits curve   \hideinitializer */
+    CURVE_25519,                        /*!< ECC curve-25519          \hideinitializer */
+    CURVE_SM2_256,                      /*!< SM2                      \hideinitializer */
+    CURVE_UNDEF = -0x7fffffff,                        /*!< Invalid curve            \hideinitializer */
+}
+E_ECC_CURVE;
+
+
+
+typedef struct e_curve_t
+{
+    E_ECC_CURVE curve_id;
+    int32_t     Echar;
+    char        Ea[144];
+    char        Eb[144];
+    char        Px[144];
+    char        Py[144];
+    int32_t     Epl;
+    char        Pp[176];
+    int32_t     Eol;
+    char        Eorder[176];
+    int32_t     key_len;
+    int32_t     irreducible_k1;
+    int32_t     irreducible_k2;
+    int32_t     irreducible_k3;
+    int32_t     GF;
+}  ECC_CURVE;
+
+
+/* RSA working buffer for normal mode */
+typedef struct
+{
+    uint32_t au32RsaOutput[128]; /* The RSA answer. */
+    uint32_t au32RsaN[128]; /* The base of modulus operation word. */
+    uint32_t au32RsaM[128]; /* The base of exponentiation words. */
+    uint32_t au32RsaE[128]; /* The exponent of exponentiation words. */
+} RSA_BUF_NORMAL_T;
+
+/* RSA working buffer for CRT ( + CRT bypass) mode */
+typedef struct
+{
+    uint32_t au32RsaOutput[128]; /* The RSA answer. */
+    uint32_t au32RsaN[128]; /* The base of modulus operation word. */
+    uint32_t au32RsaM[128]; /* The base of exponentiation words. */
+    uint32_t au32RsaE[128]; /* The exponent of exponentiation words. */
+    uint32_t au32RsaP[128]; /* The Factor of Modulus Operation. */
+    uint32_t au32RsaQ[128]; /* The Factor of Modulus Operation. */
+    uint32_t au32RsaTmpCp[128]; /* The Temporary Value(Cp) of RSA CRT. */
+    uint32_t au32RsaTmpCq[128]; /* The Temporary Value(Cq) of RSA CRT. */
+    uint32_t au32RsaTmpDp[128]; /* The Temporary Value(Dp) of RSA CRT. */
+    uint32_t au32RsaTmpDq[128]; /* The Temporary Value(Dq) of RSA CRT. */
+    uint32_t au32RsaTmpRp[128]; /* The Temporary Value(Rp) of RSA CRT. */
+    uint32_t au32RsaTmpRq[128]; /* The Temporary Value(Rq) of RSA CRT. */
+} RSA_BUF_CRT_T;
+
+/* RSA working buffer for SCAP mode */
+typedef struct
+{
+    uint32_t au32RsaOutput[128]; /* The RSA answer. */
+    uint32_t au32RsaN[128]; /* The base of modulus operation word. */
+    uint32_t au32RsaM[128]; /* The base of exponentiation words. */
+    uint32_t au32RsaE[128]; /* The exponent of exponentiation words. */
+    uint32_t au32RsaP[128]; /* The Factor of Modulus Operation. */
+    uint32_t au32RsaQ[128]; /* The Factor of Modulus Operation. */
+    uint32_t au32RsaTmpBlindKey[128]; /* The Temporary Value(blind key) of RSA SCAP. */
+} RSA_BUF_SCAP_T;
+
+/* RSA working buffer for CRT ( + CRT bypass ) + SCAP mode */
+typedef struct
+{
+    uint32_t au32RsaOutput[128]; /* The RSA answer. */
+    uint32_t au32RsaN[128]; /* The base of modulus operation word. */
+    uint32_t au32RsaM[128]; /* The base of exponentiation words. */
+    uint32_t au32RsaE[128]; /* The exponent of exponentiation words. */
+    uint32_t au32RsaP[128]; /* The Factor of Modulus Operation. */
+    uint32_t au32RsaQ[128]; /* The Factor of Modulus Operation. */
+    uint32_t au32RsaTmpCp[128]; /* The Temporary Value(Cp) of RSA CRT. */
+    uint32_t au32RsaTmpCq[128]; /* The Temporary Value(Cq) of RSA CRT. */
+    uint32_t au32RsaTmpDp[128]; /* The Temporary Value(Dp) of RSA CRT. */
+    uint32_t au32RsaTmpDq[128]; /* The Temporary Value(Dq) of RSA CRT. */
+    uint32_t au32RsaTmpRp[128]; /* The Temporary Value(Rp) of RSA CRT. */
+    uint32_t au32RsaTmpRq[128]; /* The Temporary Value(Rq) of RSA CRT. */
+    uint32_t au32RsaTmpBlindKey[128]; /* The Temporary Value(blind key) of RSA SCAP. */
+} RSA_BUF_CRT_SCAP_T;
+
+/* RSA working buffer for using key store */
+typedef struct
+{
+    uint32_t au32RsaOutput[128]; /* The RSA answer. */
+    uint32_t au32RsaN[128]; /* The base of modulus operation word. */
+    uint32_t au32RsaM[128]; /* The base of exponentiation words. */
+} RSA_BUF_KS_T;
+
+/**@}*/ /* end of group CRYPTO_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup CRYPTO_EXPORTED_MACROS CRYPTO Exported Macros
+  @{
+*/
+
+/*----------------------------------------------------------------------------------------------*/
+/*  Macros                                                                                      */
+/*----------------------------------------------------------------------------------------------*/
+
+/**
+  * @brief This macro enables PRNG interrupt.
+  * @param crpt     Specified crypto module
+  * @return None
+  * \hideinitializer
+  */
+#define PRNG_ENABLE_INT(crpt)       ((crpt)->INTEN |= CRPT_INTEN_PRNGIEN_Msk)
+
+/**
+  * @brief This macro disables PRNG interrupt.
+  * @param crpt     Specified crypto module
+  * @return None
+  * \hideinitializer
+  */
+#define PRNG_DISABLE_INT(crpt)      ((crpt)->INTEN &= ~CRPT_INTEN_PRNGIEN_Msk)
+
+/**
+  * @brief This macro gets PRNG interrupt flag.
+  * @param crpt     Specified crypto module
+  * @return PRNG interrupt flag.
+  * \hideinitializer
+  */
+#define PRNG_GET_INT_FLAG(crpt)     ((crpt)->INTSTS & CRPT_INTSTS_PRNGIF_Msk)
+
+/**
+  * @brief This macro clears PRNG interrupt flag.
+  * @param crpt     Specified crypto module
+  * @return None
+  * \hideinitializer
+  */
+#define PRNG_CLR_INT_FLAG(crpt)     ((crpt)->INTSTS = CRPT_INTSTS_PRNGIF_Msk)
+
+/**
+  * @brief This macro enables AES interrupt.
+  * @param crpt     Specified crypto module
+  * @return None
+  * \hideinitializer
+  */
+#define AES_ENABLE_INT(crpt)        ((crpt)->INTEN |= (CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESEIEN_Msk))
+
+/**
+  * @brief This macro disables AES interrupt.
+  * @param crpt     Specified crypto module
+  * @return None
+  * \hideinitializer
+  */
+#define AES_DISABLE_INT(crpt)       ((crpt)->INTEN &= ~(CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESEIEN_Msk))
+
+/**
+  * @brief This macro gets AES interrupt flag.
+  * @param crpt     Specified crypto module
+  * @return AES interrupt flag.
+  * \hideinitializer
+  */
+#define AES_GET_INT_FLAG(crpt)      ((crpt)->INTSTS & (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESEIF_Msk))
+
+/**
+  * @brief This macro clears AES interrupt flag.
+  * @param crpt     Specified crypto module
+  * @return None
+  * \hideinitializer
+  */
+#define AES_CLR_INT_FLAG(crpt)      ((crpt)->INTSTS = (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESEIF_Msk))
+
+/**
+  * @brief This macro enables AES key protection.
+  * @param crpt     Specified crypto module
+  * @return None
+  * \hideinitializer
+  */
+#define AES_ENABLE_KEY_PROTECT(crpt)  ((crpt)->AES_CTL |= CRPT_AES_CTL_KEYPRT_Msk)
+
+/**
+  * @brief This macro disables AES key protection.
+  * @param crpt     Specified crypto module
+  * @return None
+  * \hideinitializer
+  */
+#define AES_DISABLE_KEY_PROTECT(crpt) ((crpt)->AES_CTL = ((crpt)->AES_CTL & ~CRPT_AES_CTL_KEYPRT_Msk) | (0x16UL<AES_CTL &= ~CRPT_AES_CTL_KEYPRT_Msk)
+
+/**
+  * @brief This macro enables TDES interrupt.
+  * @param crpt     Specified crypto module
+  * @return None
+  * \hideinitializer
+  */
+#define TDES_ENABLE_INT(crpt)       ((crpt)->INTEN |= (CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESEIEN_Msk))
+
+/**
+  * @brief This macro disables TDES interrupt.
+  * @param crpt     Specified crypto module
+  * @return None
+  * \hideinitializer
+  */
+#define TDES_DISABLE_INT(crpt)      ((crpt)->INTEN &= ~(CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESEIEN_Msk))
+
+/**
+  * @brief This macro gets TDES interrupt flag.
+  * @param crpt     Specified crypto module
+  * @return TDES interrupt flag.
+  * \hideinitializer
+  */
+#define TDES_GET_INT_FLAG(crpt)     ((crpt)->INTSTS & (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESEIF_Msk))
+
+/**
+  * @brief This macro clears TDES interrupt flag.
+  * @param crpt     Specified crypto module
+  * @return None
+  * \hideinitializer
+  */
+#define TDES_CLR_INT_FLAG(crpt)     ((crpt)->INTSTS = (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESEIF_Msk))
+
+/**
+  * @brief This macro enables TDES key protection.
+  * @param crpt     Specified crypto module
+  * @return None
+  * \hideinitializer
+  */
+#define TDES_ENABLE_KEY_PROTECT(crpt)  ((crpt)->TDES_CTL |= CRPT_TDES_CTL_KEYPRT_Msk)
+
+/**
+  * @brief This macro disables TDES key protection.
+  * @param crpt     Specified crypto module
+  * @return None
+  * \hideinitializer
+  */
+#define TDES_DISABLE_KEY_PROTECT(crpt) ((crpt)->TDES_CTL = ((crpt)->TDES_CTL & ~CRPT_TDES_CTL_KEYPRT_Msk) | (0x16UL<TDES_CTL &= ~CRPT_TDES_CTL_KEYPRT_Msk)
+
+/**
+  * @brief This macro enables SHA interrupt.
+  * @param crpt     Specified crypto module
+  * @return None
+  * \hideinitializer
+  */
+#define SHA_ENABLE_INT(crpt)        ((crpt)->INTEN |= (CRPT_INTEN_HMACIEN_Msk|CRPT_INTEN_HMACEIEN_Msk))
+
+/**
+  * @brief This macro disables SHA interrupt.
+  * @param crpt     Specified crypto module
+  * @return None
+  * \hideinitializer
+  */
+#define SHA_DISABLE_INT(crpt)       ((crpt)->INTEN &= ~(CRPT_INTEN_HMACIEN_Msk|CRPT_INTEN_HMACEIEN_Msk))
+
+/**
+  * @brief This macro gets SHA interrupt flag.
+  * @param crpt     Specified crypto module
+  * @return SHA interrupt flag.
+  * \hideinitializer
+  */
+#define SHA_GET_INT_FLAG(crpt)      ((crpt)->INTSTS & (CRPT_INTSTS_HMACIF_Msk|CRPT_INTSTS_HMACEIF_Msk))
+
+/**
+  * @brief This macro clears SHA interrupt flag.
+  * @param crpt     Specified crypto module
+  * @return None
+  * \hideinitializer
+  */
+#define SHA_CLR_INT_FLAG(crpt)      ((crpt)->INTSTS = (CRPT_INTSTS_HMACIF_Msk|CRPT_INTSTS_HMACEIF_Msk))
+
+/**
+  * @brief This macro enables ECC interrupt.
+  * @param crpt     Specified crypto module
+  * @return None
+  * \hideinitializer
+  */
+#define ECC_ENABLE_INT(crpt)        ((crpt)->INTEN |= (CRPT_INTEN_ECCIEN_Msk|CRPT_INTEN_ECCEIEN_Msk))
+
+/**
+  * @brief This macro disables ECC interrupt.
+  * @param crpt     Specified crypto module
+  * @return None
+  * \hideinitializer
+  */
+#define ECC_DISABLE_INT(crpt)       ((crpt)->INTEN &= ~(CRPT_INTEN_ECCIEN_Msk|CRPT_INTEN_ECCEIEN_Msk))
+
+/**
+  * @brief This macro gets ECC interrupt flag.
+  * @param crpt     Specified crypto module
+  * @return ECC interrupt flag.
+  * \hideinitializer
+  */
+#define ECC_GET_INT_FLAG(crpt)      ((crpt)->INTSTS & (CRPT_INTSTS_ECCIF_Msk|CRPT_INTSTS_ECCEIF_Msk))
+
+/**
+  * @brief This macro clears ECC interrupt flag.
+  * @param crpt     Specified crypto module
+  * @return None
+  * \hideinitializer
+  */
+#define ECC_CLR_INT_FLAG(crpt)      ((crpt)->INTSTS = (CRPT_INTSTS_ECCIF_Msk|CRPT_INTSTS_ECCEIF_Msk))
+
+/**
+  * @brief This macro enables RSA interrupt.
+  * @param crpt     Specified crypto module
+  * @return None
+  * \hideinitializer
+  */
+#define RSA_ENABLE_INT(crpt)        ((crpt)->INTEN |= (CRPT_INTEN_RSAIEN_Msk|CRPT_INTEN_RSAEIEN_Msk))
+
+/**
+  * @brief This macro disables RSA interrupt.
+  * @param crpt     Specified crypto module
+  * @return None
+  * \hideinitializer
+  */
+#define RSA_DISABLE_INT(crpt)       ((crpt)->INTEN &= ~(CRPT_INTEN_RSAIEN_Msk|CRPT_INTEN_RSAEIEN_Msk))
+
+/**
+  * @brief This macro gets RSA interrupt flag.
+  * @param crpt     Specified crypto module
+  * @return ECC interrupt flag.
+  * \hideinitializer
+  */
+#define RSA_GET_INT_FLAG(crpt)      ((crpt)->INTSTS & (CRPT_INTSTS_RSAIF_Msk|CRPT_INTSTS_RSAEIF_Msk))
+
+/**
+  * @brief This macro clears RSA interrupt flag.
+  * @param crpt     Specified crypto module
+  * @return None
+  * \hideinitializer
+  */
+#define RSA_CLR_INT_FLAG(crpt)      ((crpt)->INTSTS = (CRPT_INTSTS_RSAIF_Msk|CRPT_INTSTS_RSAEIF_Msk))
+
+
+/**@}*/ /* end of group CRYPTO_EXPORTED_MACROS */
+
+
+
+/** @addtogroup CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Functions                                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+
+void PRNG_Open(CRPT_T *crpt, uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed);
+void PRNG_Start(CRPT_T *crpt);
+void PRNG_Read(CRPT_T *crpt, uint32_t u32RandKey[]);
+void AES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType);
+void AES_Start(CRPT_T *crpt, int32_t u32Channel, uint32_t u32DMAMode);
+void AES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize);
+void AES_SetKey_KS(CRPT_T *crpt, KS_MEM_Type mem, int32_t i32KeyIdx);
+void AES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32IV[]);
+void AES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt);
+void SHA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32SwapType, uint32_t hmac_key_len);
+void SHA_Start(CRPT_T *crpt, uint32_t u32DMAMode);
+void SHA_SetDMATransfer(CRPT_T *crpt, uint32_t u32SrcAddr, uint32_t u32TransCnt);
+void SHA_Read(CRPT_T *crpt, uint32_t u32Digest[]);
+void ECC_DriverISR(CRPT_T *crpt);
+int  ECC_IsPrivateKeyValid(CRPT_T *crpt, E_ECC_CURVE ecc_curve,  char private_k[]);
+int32_t  ECC_GenerateSecretZ(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[], char secret_z[]);
+int32_t  ECC_GeneratePublicKey(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[]);
+int32_t  ECC_GenerateSignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, char *d, char *k, char *R, char *S);
+int32_t  ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, char *public_k1, char *public_k2, char *R, char *S);
+
+
+int32_t RSA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32KeySize, void *psRSA_Buf, uint32_t u32BufSize, uint32_t u32UseKS);
+int32_t RSA_SetKey(CRPT_T *crpt, char *Key);
+int32_t RSA_SetDMATransfer(CRPT_T *crpt, char *Src, char *n, char *P, char *Q);
+void RSA_Start(CRPT_T *crpt);
+int32_t RSA_Read(CRPT_T *crpt, char * Output);
+int32_t RSA_SetKey_KS(CRPT_T *crpt, uint32_t u32KeyNum, uint32_t u32KSMemType, uint32_t u32BlindKeyNum);
+int32_t RSA_SetDMATransfer_KS(CRPT_T *crpt, char *Src, char *n, uint32_t u32PNum,
+                              uint32_t u32QNum, uint32_t u32CpNum, uint32_t u32CqNum, uint32_t u32DpNum,
+                              uint32_t u32DqNum, uint32_t u32RpNum, uint32_t u32RqNum);
+int32_t  ECC_GeneratePublicKey_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve, KS_MEM_Type mem, int32_t i32KeyIdx, char public_k1[], char public_k2[], uint32_t u32ExtraOp);
+int32_t  ECC_GenerateSignature_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, KS_MEM_Type mem_d, int32_t i32KeyIdx_d, KS_MEM_Type mem_k, int32_t i32KeyIdx_k, char *R, char *S);
+int32_t  ECC_VerifySignature_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, KS_MEM_Type mem_pk1, int32_t i32KeyIdx_pk1, KS_MEM_Type mem_pk2, int32_t i32KeyIdx_pk2, char *R, char *S);
+int32_t  ECC_GenerateSecretZ_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve, KS_MEM_Type mem, int32_t i32KeyIdx, char public_k1[], char public_k2[]);
+
+void CRPT_Reg2Hex(int32_t count, uint32_t volatile reg[], char output[]);
+void CRPT_Hex2Reg(char input[], uint32_t volatile reg[]);
+int32_t ECC_GetCurve(CRPT_T *crpt, E_ECC_CURVE ecc_curve, ECC_CURVE *curve);
+
+/**@}*/ /* end of group CRYPTO_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group CRYPTO_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __NU_CRYPTO_H__ */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_dac.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_dac.h
new file mode 100644
index 0000000000..f8de627d11
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_dac.h
@@ -0,0 +1,255 @@
+/******************************************************************************
+ * @file     nu_dac.h
+ * @version  V1.00
+ * @brief    M2354 series DAC driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __NU_DAC_H__
+#define __NU_DAC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup DAC_Driver DAC Driver
+  @{
+*/
+
+
+/** @addtogroup DAC_EXPORTED_CONSTANTS DAC Exported Constants
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  DAC_CTL Constant Definitions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+#define DAC_CTL_LALIGN_RIGHT_ALIGN   (0UL<SWTRG = DAC_SWTRG_SWTRG_Msk)
+
+/**
+  * @brief Enable DAC data left-aligned.
+  * @param[in] dac The pointer of the specified DAC module.
+  * @return None
+  * @details User has to load data into DAC_DAT[15:4] bits. DAC_DAT[31:16] and DAC_DAT[3:0] are ignored in DAC conversion.
+  */
+#define DAC_ENABLE_LEFT_ALIGN(dac) ((dac)->CTL |= DAC_CTL_LALIGN_Msk)
+
+/**
+  * @brief Enable DAC data right-aligned.
+  * @param[in] dac The pointer of the specified DAC module.
+  * @return None
+  * @details User has to load data into DAC_DAT[11:0] bits, DAC_DAT[31:12] are ignored in DAC conversion.
+  */
+#define DAC_ENABLE_RIGHT_ALIGN(dac) ((dac)->CTL &= ~DAC_CTL_LALIGN_Msk)
+
+/**
+  * @brief Enable output voltage buffer.
+  * @param[in] dac The pointer of the specified DAC module.
+  * @return None
+  * @details The DAC integrates a voltage output buffer that can be used to reduce output impedance and
+  *         drive external loads directly without having to add an external operational amplifier.
+  */
+#define DAC_ENABLE_BYPASS_BUFFER(dac) ((dac)->CTL |= DAC_CTL_BYPASS_Msk)
+
+/**
+  * @brief Disable output voltage buffer.
+  * @param[in] dac The pointer of the specified DAC module.
+  * @return None
+  * @details This macro is used to disable output voltage buffer.
+  */
+#define DAC_DISABLE_BYPASS_BUFFER(dac) ((dac)->CTL &= ~DAC_CTL_BYPASS_Msk)
+
+/**
+  * @brief Enable the interrupt.
+  * @param[in] dac The pointer of the specified DAC module.
+  * @param[in] u32Ch Not used in M2355 Series DAC.
+  * @return None
+  * @details This macro is used to enable DAC interrupt.
+  */
+#define DAC_ENABLE_INT(dac, u32Ch) ((dac)->CTL |= DAC_CTL_DACIEN_Msk)
+
+/**
+  * @brief Disable the interrupt.
+  * @param[in] dac The pointer of the specified DAC module.
+  * @param[in] u32Ch Not used in M2355 Series DAC.
+  * @return None
+  * @details This macro is used to disable DAC interrupt.
+  */
+#define DAC_DISABLE_INT(dac, u32Ch) ((dac)->CTL &= ~DAC_CTL_DACIEN_Msk)
+
+/**
+  * @brief Enable DMA under-run interrupt.
+  * @param[in] dac The pointer of the specified DAC module.
+  * @return None
+  * @details This macro is used to enable DMA under-run interrupt.
+  */
+#define DAC_ENABLE_DMAUDR_INT(dac) ((dac)->CTL |= DAC_CTL_DMAURIEN_Msk)
+
+/**
+  * @brief Disable DMA under-run interrupt.
+  * @param[in] dac The pointer of the specified DAC module.
+  * @return None
+  * @details This macro is used to disable DMA under-run interrupt.
+  */
+#define DAC_DISABLE_DMAUDR_INT(dac) ((dac)->CTL &= ~DAC_CTL_DMAURIEN_Msk)
+
+/**
+  * @brief Enable PDMA mode.
+  * @param[in] dac The pointer of the specified DAC module.
+  * @return None
+  * @details DAC DMA request is generated when a hardware trigger event occurs while DMAEN (DAC_CTL[2]) is set.
+  */
+#define DAC_ENABLE_PDMA(dac) ((dac)->CTL |= DAC_CTL_DMAEN_Msk)
+
+/**
+  * @brief Disable PDMA mode.
+  * @param[in] dac The pointer of the specified DAC module.
+  * @return None
+  * @details This macro is used to disable DMA mode.
+  */
+#define DAC_DISABLE_PDMA(dac) ((dac)->CTL &= ~DAC_CTL_DMAEN_Msk)
+
+/**
+  * @brief Write data for conversion.
+  * @param[in] dac The pointer of the specified DAC module.
+  * @param[in] u32Ch Not used in M2355 Series DAC.
+  * @param[in] u32Data Decides the data for conversion, valid range are between 0~0xFFF.
+  * @return None
+  * @details 12 bit left alignment: user has to load data into DAC_DAT[15:4] bits.
+  *         12 bit right alignment: user has to load data into DAC_DAT[11:0] bits.
+  */
+#define DAC_WRITE_DATA(dac, u32Ch, u32Data) ((dac)->DAT = (u32Data))
+
+/**
+  * @brief Read DAC 12-bit holding data.
+  * @param[in] dac The pointer of the specified DAC module.
+  * @param[in] u32Ch Not used in M2355 Series DAC.
+  * @return Return DAC 12-bit holding data.
+  * @details This macro is used to read DAC_DAT register.
+  */
+#define DAC_READ_DATA(dac, u32Ch) ((dac)->DAT)
+
+/**
+  * @brief Get the busy state of DAC.
+  * @param[in] dac The pointer of the specified DAC module.
+  * @param[in] u32Ch Not used in M2355 Series DAC.
+  * @retval 0 Idle state.
+  * @retval 1 Busy state.
+  * @details This macro is used to read BUSY bit (DAC_STATUS[8]) to get busy state.
+  */
+#define DAC_IS_BUSY(dac, u32Ch) (((dac)->STATUS & DAC_STATUS_BUSY_Msk) >> DAC_STATUS_BUSY_Pos)
+
+/**
+  * @brief Get the interrupt flag.
+  * @param[in] dac The pointer of the specified DAC module.
+  * @param[in] u32Ch Not used in M2355 Series DAC.
+  * @retval 0 DAC is in conversion state.
+  * @retval 1 DAC conversion finish.
+  * @details This macro is used to read FINISH bit (DAC_STATUS[0]) to get DAC conversion complete finish flag.
+  */
+#define DAC_GET_INT_FLAG(dac, u32Ch) ((dac)->STATUS & DAC_STATUS_FINISH_Msk)
+
+/**
+  * @brief Get the DMA under-run flag.
+  * @param[in] dac The pointer of the specified DAC module.
+  * @retval 0 No DMA under-run error condition occurred.
+  * @retval 1 DMA under-run error condition occurred.
+  * @details This macro is used to read DMAUDR bit (DAC_STATUS[1]) to get DMA under-run state.
+  */
+#define DAC_GET_DMAUDR_FLAG(dac) (((dac)->STATUS & DAC_STATUS_DMAUDR_Msk) >> DAC_STATUS_DMAUDR_Pos)
+
+/**
+  * @brief This macro clear the interrupt status bit.
+  * @param[in] dac The pointer of the specified DAC module.
+  * @param[in] u32Ch Not used in M2355 Series DAC.
+  * @return None
+  * @details User writes FINISH bit (DAC_STATUS[0]) to clear DAC conversion complete finish flag.
+  */
+#define DAC_CLR_INT_FLAG(dac, u32Ch) ((dac)->STATUS = DAC_STATUS_FINISH_Msk)
+
+/**
+  * @brief This macro clear the  DMA under-run flag.
+  * @param[in] dac The pointer of the specified DAC module.
+  * @return None
+  * @details User writes DMAUDR bit (DAC_STATUS[1]) to clear DMA under-run flag.
+  */
+#define DAC_CLR_DMAUDR_FLAG(dac) ((dac)->STATUS = DAC_STATUS_DMAUDR_Msk)
+
+
+/**
+  * @brief Enable DAC group mode
+  * @param[in] dac The pointer of the specified DAC module.
+  * @return None
+  * @note Only DAC0 has this control bit.
+  * \hideinitializer
+  */
+#define DAC_ENABLE_GROUP_MODE(dac) ((dac)->CTL |= DAC_CTL_GRPEN_Msk)
+
+/**
+  * @brief Disable DAC group mode
+  * @param[in] dac The pointer of the specified DAC module.
+  * @return None
+  * @note Only DAC0 has this control bit.
+  * \hideinitializer
+  */
+#define DAC_DISABLE_GROUP_MODE(dac) ((dac)->CTL &= ~DAC_CTL_GRPEN_Msk)
+
+void DAC_Open(DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc);
+void DAC_Close(DAC_T *dac, uint32_t u32Ch);
+uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay);
+
+/**@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group DAC_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_DAC_H__ */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_dpm.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_dpm.h
new file mode 100644
index 0000000000..879b23ab4e
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_dpm.h
@@ -0,0 +1,130 @@
+/**************************************************************************//**
+ * @file     nu_dpm.h
+ * @version  V3.00
+ * @brief    Debug Protection Mechanism (DPM) driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_DPM_H__
+#define __NU_DPM_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup DPM_Driver DPM Driver
+  @{
+*/
+
+/** @addtogroup DPM_EXPORTED_CONSTANTS DPM Exported Constants
+  @{
+*/
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* DPM Control Register Constant Definitions                                                               */
+/*---------------------------------------------------------------------------------------------------------*/
+#define SECURE_DPM          0   /*!< Secure DPM module */
+#define NONSECURE_DPM       1   /*!< Non-secure DPM module */
+
+
+#define DPM_CTL_WVCODE      (0x5AUL<STS & DPM_STS_BUSY_Msk); \
+        DPM->CTL = (DPM->CTL & (~DPM_CTL_WVCODE_Msk)) | (DPM_CTL_WVCODE|DPM_CTL_INTEN_Msk); \
+    }while(0)
+
+/**
+  * @brief      Disable DPM Interrupt
+  * @param      None
+  * @return     None
+  * @details    This macro disables DPM interrupt.
+  *             This macro is for Secure DPM and Secure region only.
+  */
+#define DPM_DISABLE_INT() \
+    do{ \
+        while(DPM->STS & DPM_STS_BUSY_Msk); \
+        DPM->CTL = (DPM->CTL & (~(DPM_CTL_WVCODE_Msk|DPM_CTL_INTEN_Msk))) | (DPM_CTL_WVCODE); \
+    }while(0)
+
+/**
+  * @brief      Enable Debugger to Access DPM Registers
+  * @param      None
+  * @return     None
+  * @details    This macro enables debugger to access Secure and Non-secure DPM registers.
+  *             This macro is for Secure DPM and Secure region only.
+  */
+#define DPM_ENABLE_DBG_ACCESS() \
+    do{ \
+        while(DPM->STS & DPM_STS_BUSY_Msk); \
+        DPM->CTL = (DPM->CTL & (~(DPM_CTL_WVCODE_Msk|DPM_CTL_DACCDIS_Msk))) | (DPM_CTL_WVCODE); \
+    }while(0)
+
+/**
+  * @brief      Disable Debugger to Access DPM Registers
+  * @param      None
+  * @return     None
+  * @details    This macro disables debugger to access Secure and Non-secure DPM registers.
+  *             This macro is for Secure DPM and Secure region only.
+  */
+#define DPM_DISABLE_DBG_ACCESS() \
+    do{ \
+        while(DPM->STS & DPM_STS_BUSY_Msk); \
+        DPM->CTL = (DPM->CTL & (~DPM_CTL_WVCODE_Msk)) | (DPM_CTL_WVCODE|DPM_CTL_DACCDIS_Msk); \
+    }while(0)
+
+
+void DPM_SetDebugDisable(uint32_t u32dpm);
+void DPM_SetDebugLock(uint32_t u32dpm);
+uint32_t DPM_GetDebugDisable(uint32_t u32dpm);
+uint32_t DPM_GetDebugLock(uint32_t u32dpm);
+uint32_t DPM_SetPasswordUpdate(uint32_t u32dpm, uint32_t au32Pwd[]);
+uint32_t DPM_SetPasswordCompare(uint32_t u32dpm, uint32_t au32Pwd[]);
+uint32_t DPM_GetPasswordErrorFlag(uint32_t u32dpm);
+uint32_t DPM_GetIntFlag(void);
+void DPM_ClearPasswordErrorFlag(uint32_t u32dpm);
+void DPM_EnableDebuggerWriteAccess(uint32_t u32dpm);
+void DPM_DisableDebuggerWriteAccess(uint32_t u32dpm);
+
+
+
+/**@}*/ /* end of group DPM_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group DPM_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_DPM_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_eadc.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_eadc.h
new file mode 100644
index 0000000000..c94a2821af
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_eadc.h
@@ -0,0 +1,560 @@
+/******************************************************************************
+ * @file     nu_eadc.h
+ * @version  V0.10
+ * @brief    M2354 series EADC driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __NU_EADC_H__
+#define __NU_EADC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup EADC_Driver EADC Driver
+  @{
+*/
+
+/** @addtogroup EADC_EXPORTED_CONSTANTS EADC Exported Constants
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  EADC_CTL Constant Definitions                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EADC_CTL_DIFFEN_SINGLE_END          (0UL<CTL |= EADC_CTL_ADCRST_Msk)
+
+/**
+  * @brief Enable Sample Module PDMA transfer.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.
+  *                          This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF.
+  * @return None
+  * @details When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register,
+  *         user can enable this bit to generate a PDMA data transfer request.
+  * \hideinitializer
+  */
+#define EADC_ENABLE_SAMPLE_MODULE_PDMA(eadc, u32ModuleMask) ((eadc)->PDMACTL |= u32ModuleMask)
+
+/**
+  * @brief Disable Sample Module PDMA transfer.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.
+  *                          This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF.
+  * @return None
+  * @details This macro is used to disable sample module PDMA transfer.
+  * \hideinitializer
+  */
+#define EADC_DISABLE_SAMPLE_MODULE_PDMA(eadc, u32ModuleMask) ((eadc)->PDMACTL &= (~u32ModuleMask))
+
+/**
+  * @brief Enable double buffer mode.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3.
+  * @return None
+  * @details The ADC controller supports a double buffer mode in sample module 0~3.
+  *         If user enable DBMEN (EADC_SCTLn[23], n=0~3), the double buffer mode will enable.
+  */
+#define EADC_ENABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_DBMEN_Msk)
+
+/**
+  * @brief Disable double buffer mode.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3.
+  * @return None
+  * @details Sample has one sample result register.
+  */
+#define EADC_DISABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_DBMEN_Msk)
+
+/**
+  * @brief Set ADIFn at A/D end of conversion.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
+  * @return None
+  * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the start of conversion.
+  */
+#define EADC_ENABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_INTPOS_Msk)
+
+/**
+  * @brief Set ADIFn at A/D start of conversion.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
+  * @return None
+  * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the end of conversion.
+  */
+#define EADC_DISABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_INTPOS_Msk)
+
+/**
+  * @brief Enable the interrupt.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status.
+  *                    This parameter decides which interrupts will be enabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3.
+  * @return None
+  * @details The A/D converter generates a conversion end ADIFn (EADC_STATUS2[n]) upon the end of specific sample module A/D conversion.
+  *         If ADCIENn bit (EADC_CTL[n+2]) is set then conversion end interrupt request ADINTn is generated (n=0~3).
+  */
+#define EADC_ENABLE_INT(eadc, u32Mask) ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos))
+
+/**
+  * @brief Disable the interrupt.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status.
+  *                    This parameter decides which interrupts will be disabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3.
+  * @return None
+  * @details Specific sample module A/D ADINT0 interrupt function Disabled.
+  */
+#define EADC_DISABLE_INT(eadc, u32Mask) ((eadc)->CTL &= ~((u32Mask) << EADC_CTL_ADCIEN0_Pos))
+
+/**
+  * @brief Enable the sample module interrupt.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3.
+  * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.
+  *                          This parameter decides which sample module interrupts will be enabled, valid range are between 1~0x7FFFF.
+  * @return None
+  * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.
+  */
+#define EADC_ENABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] |= (u32ModuleMask))
+
+/**
+  * @brief Disable the sample module interrupt.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3.
+  * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.
+  *                          This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF.
+  * @return None
+  * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.
+  */
+#define EADC_DISABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] &= (uint32_t)(~(u32ModuleMask)))
+
+/**
+  * @brief Set the input mode output format.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32Format Decides the output format. Valid values are:
+  *                       - \ref EADC_CTL_DMOF_STRAIGHT_BINARY      :Select the straight binary format as the output format of the conversion result.
+  *                       - \ref EADC_CTL_DMOF_TWOS_COMPLEMENT      :Select the 2's complement format as the output format of the conversion result.
+  * @return None
+  * @details The macro is used to set A/D input mode output format.
+  */
+#define EADC_SET_DMOF(eadc, u32Format) ((eadc)->CTL = ((eadc)->CTL & ~EADC_CTL_DMOF_Msk) | (u32Format))
+
+/**
+  * @brief Start the A/D conversion.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module.
+  *                         This parameter decides which sample module will be conversion, valid range are between 1~0x7FFFF.
+  *                         Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module 18.
+  * @return None
+  * @details After write EADC_SWTRG register to start ADC conversion, the EADC_PENDSTS register will show which SAMPLE will conversion.
+  */
+#define EADC_START_CONV(eadc, u32ModuleMask) ((eadc)->SWTRG = (u32ModuleMask))
+
+/**
+  * @brief Cancel the conversion for sample module.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module.
+  *                         This parameter decides which sample module will stop the conversion, valid range are between 1~0x7FFFF.
+  *                         Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module18.
+  * @return None
+  * @details If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.
+  */
+#define EADC_STOP_CONV(eadc, u32ModuleMask) ((eadc)->PENDSTS = (u32ModuleMask))
+
+/**
+  * @brief Get the conversion pending flag.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @return Return the conversion pending sample module.
+  * @details This STPFn(EADC_PENDSTS[18:0]) bit remains 1 during pending state, when the respective ADC conversion is end,
+  *         the STPFn (n=0~18) bit is automatically cleared to 0.
+  */
+#define EADC_GET_PENDING_CONV(eadc) ((eadc)->PENDSTS)
+
+/**
+  * @brief Get the conversion data of the user-specified sample module.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.
+  * @return Return the conversion data of the user-specified sample module.
+  * @details This macro is used to read RESULT bit (EADC_DATn[15:0], n=0~18) field to get conversion data.
+  */
+#define EADC_GET_CONV_DATA(eadc, u32ModuleNum) ((eadc)->DAT[(u32ModuleNum)] & EADC_DAT_RESULT_Msk)
+
+/**
+  * @brief Get the data overrun flag of the user-specified sample module.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleMask The combination of data overrun status bits. Each bit corresponds to a data overrun status, valid range are between 1~0x7FFFF.
+  * @return Return the data overrun flag of the user-specified sample module.
+  * @details This macro is used to read OV bit (EADC_STATUS0[31:16], EADC_STATUS1[18:16]) field to get data overrun status.
+  */
+#define EADC_GET_DATA_OVERRUN_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) | ((eadc)->STATUS1 & EADC_STATUS1_OV_Msk)) & (u32ModuleMask))
+
+/**
+  * @brief Get the data valid flag of the user-specified sample module.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleMask The combination of data valid status bits. Each bit corresponds to a data valid status, valid range are between 1~0x7FFFF.
+  * @return Return the data valid flag of the user-specified sample module.
+  * @details This macro is used to read VALID bit (EADC_STATUS0[15:0], EADC_STATUS1[2:0]) field to get data valid status.
+  */
+#define EADC_GET_DATA_VALID_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) | (((eadc)->STATUS1 & EADC_STATUS1_VALID_Msk) << 16)) & (u32ModuleMask))
+
+/**
+  * @brief Get the double data of the user-specified sample module.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.
+  * @return Return the double data of the user-specified sample module.
+  * @details This macro is used to read RESULT bit (EADC_DDATn[15:0], n=0~3) field to get conversion data.
+  */
+#define EADC_GET_DOUBLE_DATA(eadc, u32ModuleNum) ((eadc)->DDAT[(u32ModuleNum)] & EADC_DDAT0_RESULT_Msk)
+
+/**
+  * @brief Get the user-specified interrupt flags.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32Mask The combination of interrupt status bits. Each bit corresponds to a interrupt status.
+  *                    Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3.
+  *                    Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3.
+  * @return Return the user-specified interrupt flags.
+  * @details This macro is used to get the user-specified interrupt flags.
+  */
+#define EADC_GET_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 & (u32Mask))
+
+/**
+  * @brief Get the user-specified sample module overrun flags.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status, valid range are between 1~0x7FFFF.
+  * @return Return the user-specified sample module overrun flags.
+  * @details This macro is used to get the user-specified sample module overrun flags.
+  */
+#define EADC_GET_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS & (u32ModuleMask))
+
+/**
+  * @brief Clear the selected interrupt status bits.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32Mask The combination of compare interrupt status bits. Each bit corresponds to a compare interrupt status.
+  *                    Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3.
+  *                    Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3.
+  * @return None
+  * @details This macro is used to clear clear the selected interrupt status bits.
+  */
+#define EADC_CLR_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 = (u32Mask))
+
+/**
+  * @brief Clear the selected sample module overrun status bits.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status.
+  *                      Bit 0 is SPOVF0, bit 1 is SPOVF1..., bit 18 is SPOVF18.
+  * @return None
+  * @details This macro is used to clear the selected sample module overrun status bits.
+  */
+#define EADC_CLR_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS = (u32ModuleMask))
+
+/**
+  * @brief Check all sample module A/D result data register overrun flags.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @retval 0 None of sample module data register overrun flag is set to 1.
+  * @retval 1 Any one of sample module data register overrun flag is set to 1.
+  * @details The AOV bit (EADC_STATUS2[27]) will keep 1 when any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
+  */
+#define EADC_IS_DATA_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AOV_Msk) >> EADC_STATUS2_AOV_Pos)
+
+/**
+  * @brief Check all sample module A/D result data register valid flags.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @retval 0 None of sample module data register valid flag is set to 1.
+  * @retval 1 Any one of sample module data register valid flag is set to 1.
+  * @details The AVALID bit (EADC_STATUS2[26]) will keep 1 when any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
+  */
+#define EADC_IS_DATA_VALID(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AVALID_Msk) >> EADC_STATUS2_AVALID_Pos)
+
+/**
+  * @brief Check all A/D sample module start of conversion overrun flags.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @retval 0 None of sample module event overrun flag is set to 1.
+  * @retval 1 Any one of sample module event overrun flag is set to 1.
+  * @details The STOVF bit (EADC_STATUS2[25]) will keep 1 when any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
+  */
+#define EADC_IS_SAMPLE_MODULE_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_STOVF_Msk) >> EADC_STATUS2_STOVF_Pos)
+
+/**
+  * @brief Check all A/D interrupt flag overrun bits.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @retval 0 None of ADINT interrupt flag is overwritten to 1.
+  * @retval 1 Any one of ADINT interrupt flag is overwritten to 1.
+  * @details The ADOVIF bit (EADC_STATUS2[24]) will keep 1 when any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
+  */
+#define EADC_IS_INT_FLAG_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_ADOVIF_Msk) >> EADC_STATUS2_ADOVIF_Pos)
+
+/**
+  * @brief Get the busy state of EADC.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @retval 0 Idle state.
+  * @retval 1 Busy state.
+  * @details This macro is used to read BUSY bit (EADC_STATUS2[23]) to get busy state.
+  */
+#define EADC_IS_BUSY(eadc) (((eadc)->STATUS2 & EADC_STATUS2_BUSY_Msk) >> EADC_STATUS2_BUSY_Pos)
+
+/**
+  * @brief Configure the comparator 0 and enable it.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
+  * @param[in] u32Condition specifies the compare condition. Valid values are:
+  *                        - \ref EADC_CMP_CMPCOND_LESS_THAN            :The compare condition is "less than the compare value"
+  *                        - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL     :The compare condition is "greater than or equal to the compare value
+  * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
+  * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
+  * @return None
+  * @details For example, ADC_ENABLE_CMP0(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE);
+  *         Means EADC will assert comparator 0 flag if sample module 5 conversion result is greater or
+  *         equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
+  */
+#define EADC_ENABLE_CMP0(eadc,\
+                         u32ModuleNum,\
+                         u32Condition,\
+                         u16CMPData,\
+                         u32MatchCount) ((eadc)->CMP[0] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
+                                                            (u32Condition) |\
+                                                            ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
+                                                            (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\
+                                                            EADC_CMP_ADCMPEN_Msk))
+
+/**
+  * @brief Configure the comparator 1 and enable it.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
+  * @param[in] u32Condition specifies the compare condition. Valid values are:
+  *                        - \ref EADC_CMP_CMPCOND_LESS_THAN            :The compare condition is "less than the compare value"
+  *                        - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL     :The compare condition is "greater than or equal to the compare value
+  * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
+  * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
+  * @return None
+  * @details For example, ADC_ENABLE_CMP1(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE);
+  *         Means EADC will assert comparator 1 flag if sample module 5 conversion result is greater or
+  *         equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
+  */
+#define EADC_ENABLE_CMP1(eadc,\
+                         u32ModuleNum,\
+                         u32Condition,\
+                         u16CMPData,\
+                         u32MatchCount) ((eadc)->CMP[1] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
+                                                            (u32Condition) |\
+                                                            ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
+                                                            (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\
+                                                            EADC_CMP_ADCMPEN_Msk))
+
+/**
+  * @brief Configure the comparator 2 and enable it.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
+  * @param[in] u32Condition specifies the compare condition. Valid values are:
+  *                        - \ref EADC_CMP_CMPCOND_LESS_THAN            :The compare condition is "less than the compare value"
+  *                        - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL     :The compare condition is "greater than or equal to the compare value
+  * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
+  * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
+  * @return None
+  * @details For example, ADC_ENABLE_CMP2(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE);
+  *         Means EADC will assert comparator 2 flag if sample module 5 conversion result is greater or
+  *         equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
+  */
+#define EADC_ENABLE_CMP2(eadc,\
+                         u32ModuleNum,\
+                         u32Condition,\
+                         u16CMPData,\
+                         u32MatchCount) ((eadc)->CMP[2] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
+                                                            (u32Condition) |\
+                                                            ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
+                                                            (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\
+                                                            EADC_CMP_ADCMPEN_Msk))
+
+/**
+  * @brief Configure the comparator 3 and enable it.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
+  * @param[in] u32Condition specifies the compare condition. Valid values are:
+  *                        - \ref EADC_CMP_CMPCOND_LESS_THAN            :The compare condition is "less than the compare value"
+  *                        - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL     :The compare condition is "greater than or equal to the compare value
+  * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
+  * @param[in] u32MatchCount specifies the match count setting, valid range are between 1~0xF.
+  * @return None
+  * @details For example, ADC_ENABLE_CMP3(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE);
+  *         Means EADC will assert comparator 3 flag if sample module 5 conversion result is greater or
+  *         equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
+  */
+#define EADC_ENABLE_CMP3(eadc,\
+                         u32ModuleNum,\
+                         u32Condition,\
+                         u16CMPData,\
+                         u32MatchCount) ((eadc)->CMP[3] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
+                                                            (u32Condition) |\
+                                                            ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
+                                                            (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\
+                                                            EADC_CMP_ADCMPEN_Msk))
+
+/**
+  * @brief Enable the compare window mode.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2.
+  * @return None
+  * @details ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched.
+  */
+#define EADC_ENABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_CMPWEN_Msk)
+
+/**
+  * @brief Disable the compare window mode.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2.
+  * @return None
+  * @details ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched.
+  */
+#define EADC_DISABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_CMPWEN_Msk)
+
+/**
+  * @brief Enable the compare interrupt.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3.
+  * @return None
+  * @details If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3)
+  *         and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile,
+  *         if ADCMPIE is set to 1, a compare interrupt request is generated.
+  */
+#define EADC_ENABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_ADCMPIE_Msk)
+
+/**
+  * @brief Disable the compare interrupt.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3.
+  * @return None
+  * @details This macro is used to disable the compare interrupt.
+  */
+#define EADC_DISABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_ADCMPIE_Msk)
+
+/**
+  * @brief Disable comparator 0.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @return None
+  * @details This macro is used to disable comparator 0.
+  */
+#define EADC_DISABLE_CMP0(eadc) ((eadc)->CMP[0] = 0UL)
+
+/**
+  * @brief Disable comparator 1.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @return None
+  * @details This macro is used to disable comparator 1.
+  */
+#define EADC_DISABLE_CMP1(eadc) ((eadc)->CMP[1] = 0UL)
+
+/**
+  * @brief Disable comparator 2.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @return None
+  * @details This macro is used to disable comparator 2.
+  */
+#define EADC_DISABLE_CMP2(eadc) ((eadc)->CMP[2] = 0UL)
+
+/**
+  * @brief Disable comparator 3.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @return None
+  * @details This macro is used to disable comparator 3.
+  */
+#define EADC_DISABLE_CMP3(eadc) ((eadc)->CMP[3] = 0UL)
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define EADC functions prototype                                                                         */
+/*---------------------------------------------------------------------------------------------------------*/
+void EADC_Open(EADC_T *eadc, uint32_t u32InputMode);
+void EADC_Close(EADC_T *eadc);
+void EADC_ConfigSampleModule(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerSrc, uint32_t u32Channel);
+void EADC_SetTriggerDelayTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerDelayTime, uint32_t u32DelayClockDivider);
+void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime);
+
+/**@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group EADC_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_EADC_H__ */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_ebi.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_ebi.h
new file mode 100644
index 0000000000..77c928b869
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_ebi.h
@@ -0,0 +1,369 @@
+/**************************************************************************//**
+ * @file     nu_ebi.h
+ * @version  V3.00
+ * @brief    External Bus Interface(EBI) driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_EBI_H__
+#define __NU_EBI_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup EBI_Driver EBI Driver
+  @{
+*/
+
+/** @addtogroup EBI_EXPORTED_CONSTANTS EBI Exported Constants
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Miscellaneous Constant Definitions                                                                     */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EBI_BANK0_BASE_ADDR     0x60000000UL /*!< EBI bank0 base address \hideinitializer */
+#define EBI_BANK1_BASE_ADDR     0x60100000UL /*!< EBI bank1 base address \hideinitializer */
+#define EBI_BANK2_BASE_ADDR     0x60200000UL /*!< EBI bank2 base address \hideinitializer */
+#define EBI_BANK0_BASE_ADDR_NS  0x70000000UL /*!< EBI bank0 base address for Non-Secure \hideinitializer */
+#define EBI_BANK1_BASE_ADDR_NS  0x70100000UL /*!< EBI bank1 base address for Non-Secure \hideinitializer */
+#define EBI_BANK2_BASE_ADDR_NS  0x70200000UL /*!< EBI bank2 base address for Non-Secure \hideinitializer */
+#define EBI_MAX_SIZE            0x00100000UL /*!< Maximum EBI size for each bank is 1 MB \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Constants for EBI bank number                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EBI_BANK0               0UL    /*!< EBI bank 0 \hideinitializer */
+#define EBI_BANK1               1UL    /*!< EBI bank 1 \hideinitializer */
+#define EBI_BANK2               2UL    /*!< EBI bank 2 \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Constants for EBI data bus width                                                                       */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EBI_BUSWIDTH_8BIT       8UL   /*!< EBI bus width is 8-bit \hideinitializer */
+#define EBI_BUSWIDTH_16BIT      16UL  /*!< EBI bus width is 16-bit \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Constants for EBI CS Active Level                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EBI_CS_ACTIVE_LOW       0UL    /*!< EBI CS active level is low \hideinitializer */
+#define EBI_CS_ACTIVE_HIGH      1UL    /*!< EBI CS active level is high \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Constants for EBI MCLK divider and Timing                                                              */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EBI_MCLKDIV_1           0x0UL /*!< EBI output clock(MCLK) is HCLK/1 \hideinitializer */
+#define EBI_MCLKDIV_2           0x1UL /*!< EBI output clock(MCLK) is HCLK/2 \hideinitializer */
+#define EBI_MCLKDIV_4           0x2UL /*!< EBI output clock(MCLK) is HCLK/4 \hideinitializer */
+#define EBI_MCLKDIV_8           0x3UL /*!< EBI output clock(MCLK) is HCLK/8 \hideinitializer */
+#define EBI_MCLKDIV_16          0x4UL /*!< EBI output clock(MCLK) is HCLK/16 \hideinitializer */
+#define EBI_MCLKDIV_32          0x5UL /*!< EBI output clock(MCLK) is HCLK/32 \hideinitializer */
+#define EBI_MCLKDIV_64          0x6UL /*!< EBI output clock(MCLK) is HCLK/64 \hideinitializer */
+#define EBI_MCLKDIV_128         0x7UL /*!< EBI output clock(MCLK) is HCLK/128 \hideinitializer */
+
+#define EBI_TIMING_FASTEST      0x0UL /*!< EBI timing is the fastest \hideinitializer */
+#define EBI_TIMING_VERYFAST     0x1UL /*!< EBI timing is very fast \hideinitializer */
+#define EBI_TIMING_FAST         0x2UL /*!< EBI timing is fast \hideinitializer */
+#define EBI_TIMING_NORMAL       0x3UL /*!< EBI timing is normal \hideinitializer */
+#define EBI_TIMING_SLOW         0x4UL /*!< EBI timing is slow \hideinitializer */
+#define EBI_TIMING_VERYSLOW     0x5UL /*!< EBI timing is very slow \hideinitializer */
+#define EBI_TIMING_SLOWEST      0x6UL /*!< EBI timing is the slowest \hideinitializer */
+
+#define EBI_OPMODE_NORMAL       0x0UL                 /*!< EBI bus operate in normal mode \hideinitializer */
+#define EBI_OPMODE_CACCESS      (EBI_CTL_CACCESS_Msk) /*!< EBI bus operate in Continuous Data Access mode \hideinitializer */
+#define EBI_OPMODE_ADSEPARATE   (EBI_CTL_ADSEPEN_Msk) /*!< EBI bus operate in AD Separate mode \hideinitializer */
+
+/**@}*/ /* end of group EBI_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Read 8-bit data on EBI bank0
+  *
+  * @param[in]  ebi         The pointer of EBI module.
+  * @param[in]  u32Addr     The data address on EBI bank0.
+  *
+  * @return     8-bit Data
+  *
+  * @details    This macro is used to read 8-bit data from specify address on EBI bank0.
+  * \hideinitializer
+  */
+#define EBI0_READ_DATA8(ebi, u32Addr)               (*((volatile unsigned char *)((((ebi)==EBI_S)? EBI_BANK0_BASE_ADDR:EBI_BANK0_BASE_ADDR_NS)+(u32Addr))))
+
+/**
+  * @brief      Write 8-bit data to EBI bank0
+  *
+  * @param[in]  ebi         The pointer of EBI module.
+  * @param[in]  u32Addr     The data address on EBI bank0.
+  * @param[in]  u32Data     Specify data to be written.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to write 8-bit data to specify address on EBI bank0.
+  * \hideinitializer
+  */
+#define EBI0_WRITE_DATA8(ebi, u32Addr, u32Data)     (*((volatile unsigned char *)((((ebi)==EBI_S)? EBI_BANK0_BASE_ADDR:EBI_BANK0_BASE_ADDR_NS)+(u32Addr))) = (u32Data))
+
+/**
+  * @brief      Read 16-bit data on EBI bank0
+  *
+  * @param[in]  ebi         The pointer of EBI module.
+  * @param[in]  u32Addr     The data address on EBI bank0.
+  *
+  * @return     16-bit Data
+  *
+  * @details    This macro is used to read 16-bit data from specify address on EBI bank0.
+  * \hideinitializer
+  */
+#define EBI0_READ_DATA16(ebi, u32Addr)              (*((volatile unsigned short *)((((ebi)==EBI_S)? EBI_BANK0_BASE_ADDR:EBI_BANK0_BASE_ADDR_NS)+(u32Addr))))
+
+/**
+  * @brief      Write 16-bit data to EBI bank0
+  *
+  * @param[in]  ebi         The pointer of EBI module.
+  * @param[in]  u32Addr     The data address on EBI bank0.
+  * @param[in]  u32Data     Specify data to be written.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to write 16-bit data to specify address on EBI bank0.
+  * \hideinitializer
+  */
+#define EBI0_WRITE_DATA16(ebi, u32Addr, u32Data)    (*((volatile unsigned short *)((((ebi)==EBI_S)? EBI_BANK0_BASE_ADDR:EBI_BANK0_BASE_ADDR_NS)+(u32Addr))) = (u32Data))
+
+/**
+  * @brief      Read 32-bit data on EBI bank0
+  *
+  * @param[in]  ebi         The pointer of EBI module.
+  * @param[in]  u32Addr     The data address on EBI bank0.
+  *
+  * @return     32-bit Data
+  *
+  * @details    This macro is used to read 32-bit data from specify address on EBI bank0.
+  * \hideinitializer
+  */
+#define EBI0_READ_DATA32(ebi, u32Addr)              (*((volatile unsigned int *)((((ebi)==EBI_S)? EBI_BANK0_BASE_ADDR:EBI_BANK0_BASE_ADDR_NS)+(u32Addr))))
+
+/**
+  * @brief      Write 32-bit data to EBI bank0
+  *
+  * @param[in]  ebi         The pointer of EBI module.
+  * @param[in]  u32Addr     The data address on EBI bank0.
+  * @param[in]  u32Data     Specify data to be written.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to write 32-bit data to specify address on EBI bank0.
+  * \hideinitializer
+  */
+#define EBI0_WRITE_DATA32(ebi, u32Addr, u32Data)    (*((volatile unsigned int *)((((ebi)==EBI_S)? EBI_BANK0_BASE_ADDR:EBI_BANK0_BASE_ADDR_NS)+(u32Addr))) = (u32Data))
+
+/**
+  * @brief      Read 8-bit data on EBI bank1
+  *
+  * @param[in]  ebi         The pointer of EBI module.
+  * @param[in]  u32Addr     The data address on EBI bank1.
+  *
+  * @return     8-bit Data
+  *
+  * @details    This macro is used to read 8-bit data from specify address on EBI bank1.
+  * \hideinitializer
+  */
+#define EBI1_READ_DATA8(ebi, u32Addr)               (*((volatile unsigned char *)((((ebi)==EBI_S)? EBI_BANK1_BASE_ADDR:EBI_BANK1_BASE_ADDR_NS)+(u32Addr))))
+
+/**
+  * @brief      Write 8-bit data to EBI bank1
+  *
+  * @param[in]  ebi         The pointer of EBI module.
+  * @param[in]  u32Addr     The data address on EBI bank1.
+  * @param[in]  u32Data     Specify data to be written.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to write 8-bit data to specify address on EBI bank1.
+  * \hideinitializer
+  */
+#define EBI1_WRITE_DATA8(ebi, u32Addr, u32Data)     (*((volatile unsigned char *)((((ebi)==EBI_S)? EBI_BANK1_BASE_ADDR:EBI_BANK1_BASE_ADDR_NS)+(u32Addr))) = (u32Data))
+
+/**
+  * @brief      Read 16-bit data on EBI bank1
+  *
+  * @param[in]  ebi         The pointer of EBI module.
+  * @param[in]  u32Addr     The data address on EBI bank1.
+  *
+  * @return     16-bit Data
+  *
+  * @details    This macro is used to read 16-bit data from specify address on EBI bank1.
+  * \hideinitializer
+  */
+#define EBI1_READ_DATA16(ebi, u32Addr)              (*((volatile unsigned short *)((((ebi)==EBI_S)? EBI_BANK1_BASE_ADDR:EBI_BANK1_BASE_ADDR_NS)+(u32Addr))))
+
+/**
+  * @brief      Write 16-bit data to EBI bank1
+  *
+  * @param[in]  ebi         The pointer of EBI module.
+  * @param[in]  u32Addr     The data address on EBI bank1.
+  * @param[in]  u32Data     Specify data to be written.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to write 16-bit data to specify address on EBI bank1.
+  * \hideinitializer
+  */
+#define EBI1_WRITE_DATA16(ebi, u32Addr, u32Data)    (*((volatile unsigned short *)((((ebi)==EBI_S)? EBI_BANK1_BASE_ADDR:EBI_BANK1_BASE_ADDR_NS)+(u32Addr))) = (u32Data))
+
+/**
+  * @brief      Read 32-bit data on EBI bank1
+  *
+  * @param[in]  ebi         The pointer of EBI module.
+  * @param[in]  u32Addr     The data address on EBI bank1.
+  *
+  * @return     32-bit Data
+  *
+  * @details    This macro is used to read 32-bit data from specify address on EBI bank1.
+  * \hideinitializer
+  */
+#define EBI1_READ_DATA32(ebi, u32Addr)              (*((volatile unsigned int *)((((ebi)==EBI_S)? EBI_BANK1_BASE_ADDR:EBI_BANK1_BASE_ADDR_NS)+(u32Addr))))
+
+/**
+  * @brief      Write 32-bit data to EBI bank1
+  *
+  * @param[in]  ebi         The pointer of EBI module.
+  * @param[in]  u32Addr     The data address on EBI bank1.
+  * @param[in]  u32Data     Specify data to be written.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to write 32-bit data to specify address on EBI bank1.
+  * \hideinitializer
+  */
+#define EBI1_WRITE_DATA32(ebi, u32Addr, u32Data)    (*((volatile unsigned int *)((((ebi)==EBI_S)? EBI_BANK1_BASE_ADDR:EBI_BANK1_BASE_ADDR_NS)+(u32Addr))) = (u32Data))
+
+/**
+  * @brief      Read 8-bit data on EBI bank2
+  *
+  * @param[in]  ebi         The pointer of EBI module.
+  * @param[in]  u32Addr     The data address on EBI bank2.
+  *
+  * @return     8-bit Data
+  *
+  * @details    This macro is used to read 8-bit data from specify address on EBI bank2.
+  * \hideinitializer
+  */
+#define EBI2_READ_DATA8(ebi, u32Addr)               (*((volatile unsigned char *)((((ebi)==EBI_S)? EBI_BANK2_BASE_ADDR:EBI_BANK2_BASE_ADDR_NS)+(u32Addr))))
+
+/**
+  * @brief      Write 8-bit data to EBI bank2
+  *
+  * @param[in]  ebi         The pointer of EBI module.
+  * @param[in]  u32Addr     The data address on EBI bank2.
+  * @param[in]  u32Data     Specify data to be written.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to write 8-bit data to specify address on EBI bank2.
+  * \hideinitializer
+  */
+#define EBI2_WRITE_DATA8(ebi, u32Addr, u32Data)     (*((volatile unsigned char *)((((ebi)==EBI_S)? EBI_BANK2_BASE_ADDR:EBI_BANK2_BASE_ADDR_NS)+(u32Addr))) = (u32Data))
+
+/**
+  * @brief      Read 16-bit data on EBI bank2
+  *
+  * @param[in]  ebi         The pointer of EBI module.
+  * @param[in]  u32Addr     The data address on EBI bank2.
+  *
+  * @return     16-bit Data
+  *
+  * @details    This macro is used to read 16-bit data from specify address on EBI bank2.
+  */
+#define EBI2_READ_DATA16(ebi, u32Addr)              (*((volatile unsigned short *)((((ebi)==EBI_S)? EBI_BANK2_BASE_ADDR:EBI_BANK2_BASE_ADDR_NS)+(u32Addr))))
+
+/**
+  * @brief      Write 16-bit data to EBI bank2
+  *
+  * @param[in]  ebi         The pointer of EBI module.
+  * @param[in]  u32Addr     The data address on EBI bank2.
+  * @param[in]  u32Data     Specify data to be written.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to write 16-bit data to specify address on EBI bank2.
+  * \hideinitializer
+  */
+#define EBI2_WRITE_DATA16(ebi, u32Addr, u32Data)    (*((volatile unsigned short *)((((ebi)==EBI_S)? EBI_BANK2_BASE_ADDR:EBI_BANK2_BASE_ADDR_NS)+(u32Addr))) = (u32Data))
+
+/**
+  * @brief      Read 32-bit data on EBI bank2
+  *
+  * @param[in]  ebi         The pointer of EBI module.
+  * @param[in]  u32Addr     The data address on EBI bank2.
+  *
+  * @return     32-bit Data
+  *
+  * @details    This macro is used to read 32-bit data from specify address on EBI bank2.
+  * \hideinitializer
+  */
+#define EBI2_READ_DATA32(ebi, u32Addr)              (*((volatile unsigned int *)((((ebi)==EBI_S)? EBI_BANK2_BASE_ADDR:EBI_BANK2_BASE_ADDR_NS)+(u32Addr))))
+/**
+  * @brief      Write 32-bit data to EBI bank2
+  *
+  * @param[in]  ebi         The pointer of EBI module.
+  * @param[in]  u32Addr     The data address on EBI bank2.
+  * @param[in]  u32Data     Specify data to be written.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to write 32-bit data to specify address on EBI bank2.
+  * \hideinitializer
+  */
+#define EBI2_WRITE_DATA32(ebi, u32Addr, u32Data)    (*((volatile unsigned int *)((((ebi)==EBI_S)? EBI_BANK2_BASE_ADDR:EBI_BANK2_BASE_ADDR_NS)+(u32Addr))) = (u32Data))
+
+/**
+  * @brief      Enable EBI Write Buffer
+  *
+  * @param[in]  ebi         The pointer of EBI module.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to improve EBI write operation for all EBI banks.
+  * \hideinitializer
+  */
+#define EBI_ENABLE_WRITE_BUFFER(ebi)                ((ebi)->CTL0 |= EBI_CTL_WBUFEN_Msk)
+
+/**
+  * @brief      Disable EBI Write Buffer
+  *
+  * @param[in]  ebi         The pointer of EBI module.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to disable EBI write buffer function.
+  * \hideinitializer
+  */
+#define EBI_DISABLE_WRITE_BUFFER(ebi)               ((ebi)->CTL0 &= ~EBI_CTL_WBUFEN_Msk)
+
+void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel);
+void EBI_Close(uint32_t u32Bank);
+void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv);
+
+/**@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group EBI_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_EBI_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_ecap.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_ecap.h
new file mode 100644
index 0000000000..16abdae832
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_ecap.h
@@ -0,0 +1,458 @@
+/**************************************************************************//**
+ * @file     nu_ecap.h
+ * @version  V3.00
+
+ * @brief    EnHanced Input Capture Timer(ECAP) driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __NU_ECAP_H__
+#define __NU_ECAP_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup ECAP_Driver ECAP Driver
+  @{
+*/
+
+/** @addtogroup ECAP_EXPORTED_CONSTANTS ECAP Exported Constants
+  @{
+*/
+
+#define ECAP_IC0    (0UL)    /*!< ECAP IC0 Unit \hideinitializer */
+#define ECAP_IC1    (1UL)    /*!< ECAP IC1 Unit \hideinitializer */
+#define ECAP_IC2    (2UL)    /*!< ECAP IC2 Unit \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* ECAP CTL0 constant definitions                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define ECAP_NOISE_FILTER_CLKDIV_1            (0UL<CTL0 = ((ecap)->CTL0 & ~ECAP_CTL0_NFCLKSEL_Msk)|(u32ClkSel))
+
+/**
+  * @brief This macro is used to disable noise filter
+  * @param[in] ecap      Specify ECAP port
+  * @return None
+  * @details This macro will disable the noise filter of input capture.
+  * \hideinitializer
+  */
+#define ECAP_NOISE_FILTER_DISABLE(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CAPNFDIS_Msk)
+
+/**
+  * @brief This macro is used to enable noise filter
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32ClkSel Select noise filter clock divide number
+  *                  - \ref ECAP_NOISE_FILTER_CLKDIV_1
+  *                  - \ref ECAP_NOISE_FILTER_CLKDIV_2
+  *                  - \ref ECAP_NOISE_FILTER_CLKDIV_4
+  *                  - \ref ECAP_NOISE_FILTER_CLKDIV_16
+  *                  - \ref ECAP_NOISE_FILTER_CLKDIV_32
+  *                  - \ref ECAP_NOISE_FILTER_CLKDIV_64
+  * @return None
+  * @details This macro will enable the noise filter of input capture and set noise filter clock divide.
+  * \hideinitializer
+  */
+#define ECAP_NOISE_FILTER_ENABLE(ecap, u32ClkSel) ((ecap)->CTL0 = ((ecap)->CTL0 & ~(ECAP_CTL0_CAPNFDIS_Msk|ECAP_CTL0_NFCLKSEL_Msk))|(u32ClkSel))
+
+/**
+  * @brief This macro is used to enable input channel unit
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32Mask   The input channel mask
+  *                  - \ref ECAP_CTL0_IC0EN_Msk
+  *                  - \ref ECAP_CTL0_IC1EN_Msk
+  *                  - \ref ECAP_CTL0_IC2EN_Msk
+  * @return None
+  * @details This macro will enable the input channel_n to input capture.
+  * \hideinitializer
+  */
+#define ECAP_ENABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 |= (u32Mask))
+
+/**
+  * @brief This macro is used to disable input channel unit
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32Mask  The input channel mask
+  *                  - \ref ECAP_CTL0_IC0EN_Msk
+  *                  - \ref ECAP_CTL0_IC1EN_Msk
+  *                  - \ref ECAP_CTL0_IC2EN_Msk
+  * @return None
+  * @details This macro will disable the input channel_n to input capture.
+  * \hideinitializer
+  */
+#define ECAP_DISABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask))
+
+/**
+  * @brief This macro is used to select input channel source
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32Index  The input channel number
+  *                  - \ref ECAP_IC0
+  *                  - \ref ECAP_IC1
+  *                  - \ref ECAP_IC2
+  * @param[in] u32Src    The input source
+  *                  - \ref ECAP_CAP_INPUT_SRC_FROM_IC
+  *                  - \ref ECAP_CAP_INPUT_SRC_FROM_CH
+  * @return None
+  * @details This macro will select the input source from ICx, CHx.
+  * \hideinitializer
+  */
+#define ECAP_SEL_INPUT_SRC(ecap, u32Index, u32Src) ((ecap)->CTL0 = ((ecap)->CTL0 & ~(ECAP_CTL0_CAPSEL0_Msk<<((u32Index)<<1)))|(((u32Src)<CTL0 |= (u32Mask))
+
+/**
+  * @brief This macro is used to disable input channel interrupt
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32Mask   The input channel mask
+  *                  - \ref ECAP_IC0
+  *                  - \ref ECAP_IC1
+  *                  - \ref ECAP_IC2
+  * @return None
+  * @details This macro will disable the input channel_n interrupt.
+  * \hideinitializer
+  */
+#define ECAP_DISABLE_INT(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask))
+
+/**
+  * @brief This macro is used to enable input channel overflow interrupt
+  * @param[in] ecap      Specify ECAP port
+  * @return None
+  * @details This macro will enable the input channel overflow interrupt.
+  * \hideinitializer
+  */
+#define ECAP_ENABLE_OVF_INT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_OVIEN_Msk)
+
+/**
+  * @brief This macro is used to disable input channel overflow interrupt
+  * @param[in] ecap      Specify ECAP port
+  * @return None
+  * @details This macro will disable the input channel overflow interrupt.
+  * \hideinitializer
+  */
+#define ECAP_DISABLE_OVF_INT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_OVIEN_Msk)
+
+/**
+  * @brief This macro is used to enable input channel compare-match interrupt
+  * @param[in] ecap      Specify ECAP port
+  * @return None
+  * @details This macro will enable the input channel compare-match interrupt.
+  * \hideinitializer
+  */
+#define ECAP_ENABLE_CMP_MATCH_INT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CMPIEN_Msk)
+
+/**
+  * @brief This macro is used to disable input channel compare-match interrupt
+  * @param[in] ecap      Specify ECAP port
+  * @return None
+  * @details This macro will disable the input channel compare-match interrupt.
+  * \hideinitializer
+  */
+#define ECAP_DISABLE_CMP_MATCH_INT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CMPIEN_Msk)
+
+/**
+  * @brief This macro is used to start capture counter
+  * @param[in] ecap      Specify ECAP port
+  * @return None
+  * @details This macro will start capture counter up-counting.
+  * \hideinitializer
+  */
+#define ECAP_CNT_START(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CNTEN_Msk)
+
+/**
+  * @brief This macro is used to stop capture counter
+  * @param[in] ecap      Specify ECAP port
+  * @return None
+  * @details This macro will stop capture counter up-counting.
+  * \hideinitializer
+  */
+#define ECAP_CNT_STOP(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CNTEN_Msk)
+
+/**
+  * @brief This macro is used to set event to clear capture counter
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32Event The input channel number
+  *                  - \ref ECAP_CTL0_CMPCLREN_Msk
+  *                  - \ref ECAP_CTL1_CAP0RLDEN_Msk
+  *                  - \ref ECAP_CTL1_CAP1RLDEN_Msk
+  *                  - \ref ECAP_CTL1_CAP2RLDEN_Msk
+  *                  - \ref ECAP_CTL1_OVRLDEN_Msk
+
+  * @return None
+  * @details This macro will enable and select compare or capture event that can clear capture counter.
+  * \hideinitializer
+  */
+#define ECAP_SET_CNT_CLEAR_EVENT(ecap, u32Event) do{ \
+  if((u32Event) & ECAP_CTL0_CMPCLREN_Msk) \
+    (ecap)->CTL0 |= ECAP_CTL0_CMPCLREN_Msk; \
+  else \
+    (ecap)->CTL0 &= ~ECAP_CTL0_CMPCLREN_Msk; \
+  (ecap)->CTL1 = ((ecap)->CTL1 &(uint32_t)(~0xF00)) | ((u32Event) & 0xF00); \
+  }while(0);
+
+/**
+  * @brief This macro is used to enable compare function
+  * @param[in] ecap      Specify ECAP port
+  * @return None
+  * @details This macro will enable the compare function.
+  * \hideinitializer
+  */
+#define ECAP_ENABLE_CMP(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CMPEN_Msk)
+
+/**
+  * @brief This macro is used to disable compare function
+  * @param[in] ecap      Specify ECAP port
+  * @return None
+  * @details This macro will disable the compare function.
+  * \hideinitializer
+  */
+#define ECAP_DISABLE_CMP(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CMPEN_Msk)
+
+/**
+  * @brief This macro is used to enable input capture function.
+  * @param[in] ecap      Specify ECAP port
+  * @return None
+  * @details This macro will enable input capture timer/counter.
+  * \hideinitializer
+  */
+#define ECAP_ENABLE_CNT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CAPEN_Msk)
+
+/**
+  * @brief This macro is used to disable input capture function.
+  * @param[in] ecap      Specify ECAP port
+  * @return None
+  * @details This macro will disable input capture timer/counter.
+  * \hideinitializer
+  */
+#define ECAP_DISABLE_CNT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CAPEN_Msk)
+
+/**
+  * @brief This macro is used to select input channel edge detection
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32Index  The input channel number
+  *                  - \ref ECAP_IC0
+  *                  - \ref ECAP_IC1
+  *                  - \ref ECAP_IC2
+  * @param[in] u32Edge   The input source
+  *                  - \ref ECAP_RISING_EDGE
+  *                  - \ref ECAP_FALLING_EDGE
+  *                  - \ref ECAP_RISING_FALLING_EDGE
+  * @return None
+  * @details This macro will select input capture can detect falling edge, rising edge or either rising or falling edge change.
+  * \hideinitializer
+  */
+#define ECAP_SEL_CAPTURE_EDGE(ecap, u32Index, u32Edge) ((ecap)->CTL1 = ((ecap)->CTL1 & ~(ECAP_CTL1_EDGESEL0_Msk<<((u32Index)<<1)))|((u32Edge)<<((u32Index)<<1)))
+
+/**
+  * @brief This macro is used to select ECAP counter reload trigger source
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32TrigSrc The input source
+  *                  - \ref ECAP_CTL1_CAP0RLDEN_Msk
+  *                  - \ref ECAP_CTL1_CAP1RLDEN_Msk
+  *                  - \ref ECAP_CTL1_CAP2RLDEN_Msk
+  *                  - \ref ECAP_CTL1_OVRLDEN_Msk
+  * @return None
+  * @details This macro will select capture counter reload trigger source.
+  * \hideinitializer
+  */
+#define ECAP_SEL_RELOAD_TRIG_SRC(ecap, u32TrigSrc) ((ecap)->CTL1 = ((ecap)->CTL1 & ~0xF00)|(u32TrigSrc))
+
+/**
+  * @brief This macro is used to select capture timer clock divide.
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32Clkdiv The input source
+  *                  - \ref ECAP_CAPTURE_TIMER_CLKDIV_1
+  *                  - \ref ECAP_CAPTURE_TIMER_CLKDIV_4
+  *                  - \ref ECAP_CAPTURE_TIMER_CLKDIV_16
+  *                  - \ref ECAP_CAPTURE_TIMER_CLKDIV_32
+  *                  - \ref ECAP_CAPTURE_TIMER_CLKDIV_64
+  *                  - \ref ECAP_CAPTURE_TIMER_CLKDIV_96
+  *                  - \ref ECAP_CAPTURE_TIMER_CLKDIV_112
+  *                  - \ref ECAP_CAPTURE_TIMER_CLKDIV_128
+  * @return None
+  * @details This macro will select capture timer clock has a pre-divider with eight divided option.
+  * \hideinitializer
+  */
+#define ECAP_SEL_TIMER_CLK_DIV(ecap, u32Clkdiv) ((ecap)->CTL1 = ((ecap)->CTL1 & ~ECAP_CTL1_CLKSEL_Msk)|(u32Clkdiv))
+
+/**
+  * @brief This macro is used to select capture timer/counter clock source
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32ClkSrc The input source
+  *                  - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP_CLK
+  *                  - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP0
+  *                  - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP1
+  *                  - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP2
+  * @return None
+  * @details This macro will select capture timer/clock clock source.
+  * \hideinitializer
+  */
+#define ECAP_SEL_TIMER_CLK_SRC(ecap, u32ClkSrc) ((ecap)->CTL1 = ((ecap)->CTL1 & ~ECAP_CTL1_CNTSRCSEL_Msk)|(u32ClkSrc))
+
+/**
+  * @brief This macro is used to read input capture status
+  * @param[in] ecap      Specify ECAP port
+  * @return Input capture status flags
+  * @details This macro will get the input capture interrupt status.
+  * \hideinitializer
+  */
+#define ECAP_GET_INT_STATUS(ecap) ((ecap)->STATUS)
+
+/**
+  * @brief This macro is used to get input channel interrupt flag
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32Mask  The input channel mask
+  *                  - \ref ECAP_STATUS_CAPTF0_Msk
+  *                  - \ref ECAP_STATUS_CAPTF1_Msk
+  *                  - \ref ECAP_STATUS_CAPTF2_Msk
+  *                  - \ref ECAP_STATUS_CAPOVF_Msk
+  *                  - \ref ECAP_STATUS_CAPCMPF_Msk
+  * @return None
+  * @details This macro will write 1 to get the input channel_n interrupt flag.
+  * \hideinitializer
+  */
+#define ECAP_GET_CAPTURE_FLAG(ecap, u32Mask) (((ecap)->STATUS & (u32Mask))?1:0)
+
+/**
+  * @brief This macro is used to clear input channel interrupt flag
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32Mask  The input channel mask
+  *                  - \ref ECAP_STATUS_CAPTF0_Msk
+  *                  - \ref ECAP_STATUS_CAPTF1_Msk
+  *                  - \ref ECAP_STATUS_CAPTF2_Msk
+  *                  - \ref ECAP_STATUS_CAPOVF_Msk
+  *                  - \ref ECAP_STATUS_CAPCMPF_Msk
+  * @return None
+  * @details This macro will write 1 to clear the input channel_n interrupt flag.
+  * \hideinitializer
+  */
+#define ECAP_CLR_CAPTURE_FLAG(ecap, u32Mask) ((ecap)->STATUS = (u32Mask))
+
+/**
+  * @brief This macro is used to set input capture counter value
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32Val    Counter value
+  * @return None
+  * @details This macro will set a counter value of input capture.
+  * \hideinitializer
+  */
+#define ECAP_SET_CNT_VALUE(ecap, u32Val) ((ecap)->CNT = (u32Val))
+
+/**
+  * @brief This macro is used to get input capture counter value
+  * @param[in] ecap      Specify ECAP port
+  * @return Capture counter value
+  * @details This macro will get a counter value of input capture.
+  * \hideinitializer
+  */
+#define ECAP_GET_CNT_VALUE(ecap) ((ecap)->CNT)
+
+/**
+  * @brief This macro is used to get input capture counter hold value
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32Index  The input channel number
+  *                  - \ref ECAP_IC0
+  *                  - \ref ECAP_IC1
+  *                  - \ref ECAP_IC2
+  * @return Capture counter hold value
+  * @details This macro will get a hold value of input capture channel_n.
+  * \hideinitializer
+  */
+#define ECAP_GET_CNT_HOLD_VALUE(ecap, u32Index) (*(__IO uint32_t *) (&((ecap)->HLD0) + (u32Index)))
+
+/**
+  * @brief This macro is used to set input capture counter compare value
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32Val    Input capture compare value
+  * @return None
+  * @details This macro will set a compare value of input capture counter.
+  * \hideinitializer
+  */
+#define ECAP_SET_CNT_CMP(ecap, u32Val) ((ecap)->CNTCMP = (u32Val))
+
+void ECAP_Open(ECAP_T* ecap, uint32_t u32FuncMask);
+void ECAP_Close(ECAP_T* ecap);
+void ECAP_EnableINT(ECAP_T* ecap, uint32_t u32Mask);
+void ECAP_DisableINT(ECAP_T* ecap, uint32_t u32Mask);
+/**@}*/ /* end of group ECAP_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group ECAP_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__NU_ECAP_H__*/
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_epwm.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_epwm.h
new file mode 100644
index 0000000000..5d7d7a3e2d
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_epwm.h
@@ -0,0 +1,650 @@
+/**************************************************************************//**
+ * @file     nu_epwm.h
+ * @version  V3.00
+ * @brief    M2354 series EPWM driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_EPWM_H__
+#define __NU_EPWM_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup EPWM_Driver EPWM Driver
+  @{
+*/
+
+/** @addtogroup EPWM_EXPORTED_CONSTANTS EPWM Exported Constants
+  @{
+*/
+#define EPWM_CHANNEL_NUM                          (6UL)      /*!< EPWM channel number */
+#define EPWM_CH_0_MASK                            (0x1UL)    /*!< EPWM channel 0 mask \hideinitializer */
+#define EPWM_CH_1_MASK                            (0x2UL)    /*!< EPWM channel 1 mask \hideinitializer */
+#define EPWM_CH_2_MASK                            (0x4UL)    /*!< EPWM channel 2 mask \hideinitializer */
+#define EPWM_CH_3_MASK                            (0x8UL)    /*!< EPWM channel 3 mask \hideinitializer */
+#define EPWM_CH_4_MASK                            (0x10UL)   /*!< EPWM channel 4 mask \hideinitializer */
+#define EPWM_CH_5_MASK                            (0x20UL)   /*!< EPWM channel 5 mask \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Counter Type Constant Definitions                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_UP_COUNTER                           (0UL)      /*!< Up counter type */
+#define EPWM_DOWN_COUNTER                         (1UL)      /*!< Down counter type */
+#define EPWM_UP_DOWN_COUNTER                      (2UL)      /*!< Up-Down counter type */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Aligned Type Constant Definitions                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_EDGE_ALIGNED                         (1UL)      /*!< EPWM working in edge aligned type(down count) */
+#define EPWM_CENTER_ALIGNED                       (2UL)      /*!< EPWM working in center aligned type */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Output Level Constant Definitions                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_OUTPUT_NOTHING                       (0UL)      /*!< EPWM output nothing */
+#define EPWM_OUTPUT_LOW                           (1UL)      /*!< EPWM output low */
+#define EPWM_OUTPUT_HIGH                          (2UL)      /*!< EPWM output high */
+#define EPWM_OUTPUT_TOGGLE                        (3UL)      /*!< EPWM output toggle */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Synchronous Start Function Control Constant Definitions                                                */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EPWM_SSCTL_SSRC_EPWM0                     (0UL<CTL1 = (epwm)->CTL1 | (0x7ul<CTL1 = (epwm)->CTL1 & ~(0x7ul<CTL0 = (epwm)->CTL0 | EPWM_CTL0_GROUPEN_Msk)
+
+/**
+ * @brief This macro disable group mode
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @return None
+ * @details This macro is used to disable group mode of EPWM module.
+ * \hideinitializer
+ */
+#define EPWM_DISABLE_GROUP_MODE(epwm) ((epwm)->CTL0 = (epwm)->CTL0 & ~EPWM_CTL0_GROUPEN_Msk)
+
+/**
+ * @brief Enable timer synchronous start counting function of specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32SyncSrc Synchronous start source selection, valid values are:
+ *              - \ref EPWM_SSCTL_SSRC_EPWM0
+ *              - \ref EPWM_SSCTL_SSRC_EPWM1
+ *              - \ref EPWM_SSCTL_SSRC_BPWM0
+ *              - \ref EPWM_SSCTL_SSRC_BPWM1
+ * @return None
+ * @details This macro is used to enable timer synchronous start counting function of specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_ENABLE_TIMER_SYNC(epwm, u32ChannelMask, u32SyncSrc) ((epwm)->SSCTL = ((epwm)->SSCTL & ~EPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | (u32ChannelMask))
+
+/**
+ * @brief Disable timer synchronous start counting function of specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * @details This macro is used to disable timer synchronous start counting function of specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_DISABLE_TIMER_SYNC(epwm, u32ChannelMask) \
+    do{ \
+        int i;\
+        for(i = 0; i < 6; i++) { \
+            if((u32ChannelMask) & (1UL << i)) \
+              { \
+                (epwm)->SSCTL &= ~(1UL << i); \
+              } \
+        } \
+    }while(0)
+
+/**
+ * @brief This macro enable EPWM counter synchronous start counting function.
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @return None
+ * @details This macro is used to make selected EPWM0 and EPWM1 channel(s) start counting at the same time.
+ *          To configure synchronous start counting channel(s) by EPWM_ENABLE_TIMER_SYNC() and EPWM_DISABLE_TIMER_SYNC().
+ * \hideinitializer
+ */
+#define EPWM_TRIGGER_SYNC_START(epwm) ((epwm)->SSTRG = EPWM_SSTRG_CNTSEN_Msk)
+
+/**
+ * @brief This macro enable output inverter of specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * @details This macro is used to enable output inverter of specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_ENABLE_OUTPUT_INVERTER(epwm, u32ChannelMask) ((epwm)->POLCTL = (u32ChannelMask))
+
+/**
+ * @brief This macro get captured rising data
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This macro is used to get captured rising data of specified channel.
+ * \hideinitializer
+ */
+#define EPWM_GET_CAPTURE_RISING_DATA(epwm, u32ChannelNum) ((epwm)->CAPDAT[(u32ChannelNum)].RCAPDAT)
+
+/**
+ * @brief This macro get captured falling data
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This macro is used to get captured falling data of specified channel.
+ * \hideinitializer
+ */
+#define EPWM_GET_CAPTURE_FALLING_DATA(epwm, u32ChannelNum) ((epwm)->CAPDAT[(u32ChannelNum)].FCAPDAT)
+
+/**
+ * @brief This macro mask output logic to high or low
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32LevelMask Output logic to high or low
+ * @return None
+ * @details This macro is used to mask output logic to high or low of specified channel(s).
+ * @note If u32ChannelMask parameter is 0, then mask function will be disabled.
+ * \hideinitializer
+ */
+#define EPWM_MASK_OUTPUT(epwm, u32ChannelMask, u32LevelMask) \
+    do{ \
+        (epwm)->MSKEN = (u32ChannelMask); \
+        (epwm)->MSK = (u32LevelMask); \
+    }while(0)
+
+/**
+ * @brief This macro set the prescaler of the selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF
+ * @return None
+ * @details This macro is used to set the prescaler of specified channel.
+ * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected.
+ *       The clock of EPWM counter is divided by (u32Prescaler + 1).
+ * \hideinitializer
+ */
+#define EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescaler) ((epwm)->CLKPSC[(u32ChannelNum) >> 1] = (u32Prescaler))
+
+/**
+ * @brief This macro get the prescaler of the selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Return Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF
+ * @details This macro is used to get the prescaler of specified channel.
+ * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected.
+ *       The clock of EPWM counter is divided by (u32Prescaler + 1).
+ * \hideinitializer
+ */
+#define EPWM_GET_PRESCALER(epwm, u32ChannelNum) ((epwm)->CLKPSC[(u32ChannelNum) >> 1U])
+
+/**
+ * @brief This macro set the comparator of the selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32CMR Comparator of specified channel. Valid values are between 0~0xFFFF
+ * @return None
+ * @details This macro is used to set the comparator of specified channel.
+ * @note This new setting will take effect on next EPWM period.
+ * \hideinitializer
+ */
+#define EPWM_SET_CMR(epwm, u32ChannelNum, u32CMR) ((epwm)->CMPDAT[(u32ChannelNum)]= (u32CMR))
+
+/**
+ * @brief This macro get the comparator of the selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Return the comparator of specified channel. Valid values are between 0~0xFFFF
+ * @details This macro is used to get the comparator of specified channel.
+ * \hideinitializer
+ */
+#define EPWM_GET_CMR(epwm, u32ChannelNum) ((epwm)->CMPDAT[(u32ChannelNum)])
+
+/**
+ * @brief This macro set the free trigger comparator of the selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32FTCMR Free trigger comparator of specified channel. Valid values are between 0~0xFFFF
+ * @return None
+ * @details This macro is used to set the free trigger comparator of specified channel.
+ * @note This new setting will take effect on next EPWM period.
+ * \hideinitializer
+ */
+#define EPWM_SET_FTCMR(epwm, u32ChannelNum, u32FTCMR) (((epwm)->FTCMPDAT[((u32ChannelNum) >> 1U)]) = (u32FTCMR))
+
+/**
+ * @brief This macro set the period of the selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
+ * @return None
+ * @details This macro is used to set the period of specified channel.
+ * @note This new setting will take effect on next EPWM period.
+ * @note EPWM counter will stop if period length set to 0.
+ * \hideinitializer
+ */
+#define EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR)  ((epwm)->PERIOD[(u32ChannelNum)] = (u32CNR))
+
+/**
+ * @brief This macro get the period of the selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Return the period of specified channel. Valid values are between 0~0xFFFF
+ * @details This macro is used to get the period of specified channel.
+ * \hideinitializer
+ */
+#define EPWM_GET_CNR(epwm, u32ChannelNum)  ((epwm)->PERIOD[(u32ChannelNum)])
+
+/**
+ * @brief This macro set the EPWM aligned type
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32AlignedType EPWM aligned type, valid values are:
+ *              - \ref EPWM_EDGE_ALIGNED
+ *              - \ref EPWM_CENTER_ALIGNED
+ * @return None
+ * @details This macro is used to set the EPWM aligned type of specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_SET_ALIGNED_TYPE(epwm, u32ChannelMask, u32AlignedType) \
+   do{ \
+        uint32_t i; \
+        for(i = 0UL; i < 6UL; i++) { \
+            if((u32ChannelMask) & (1UL << i)) \
+              { \
+                (epwm)->CTL1 = (((epwm)->CTL1 & ~(3UL << (i << 1))) | ((u32AlignedType) << (i << 1))); \
+              } \
+        } \
+    }while(0)
+
+/**
+ * @brief Set load window of window loading mode for specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * @details This macro is used to set load window of window loading mode for specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_SET_LOAD_WINDOW(epwm, u32ChannelMask) ((epwm)->LOAD |= (u32ChannelMask))
+
+/**
+ * @brief Trigger synchronous event from specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are 0, 2, 4
+ *                           Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4
+ * @return None
+ * @details This macro is used to trigger synchronous event from specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_TRIGGER_SYNC(epwm, u32ChannelNum) ((epwm)->SWSYNC |= (1U << ((u32ChannelNum) >> 1)))
+
+/**
+ * @brief Clear counter of specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @return None
+ * @details This macro is used to clear counter of specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_CLR_COUNTER(epwm, u32ChannelMask) ((epwm)->CNTCLR |= (u32ChannelMask))
+
+/**
+ * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32ZeroLevel output level at zero point, valid values are:
+ *              - \ref EPWM_OUTPUT_NOTHING
+ *              - \ref EPWM_OUTPUT_LOW
+ *              - \ref EPWM_OUTPUT_HIGH
+ *              - \ref EPWM_OUTPUT_TOGGLE
+ * @param[in] u32CmpUpLevel output level at compare up point, valid values are:
+ *              - \ref EPWM_OUTPUT_NOTHING
+ *              - \ref EPWM_OUTPUT_LOW
+ *              - \ref EPWM_OUTPUT_HIGH
+ *              - \ref EPWM_OUTPUT_TOGGLE
+ * @param[in] u32PeriodLevel output level at period(center) point, valid values are:
+ *              - \ref EPWM_OUTPUT_NOTHING
+ *              - \ref EPWM_OUTPUT_LOW
+ *              - \ref EPWM_OUTPUT_HIGH
+ *              - \ref EPWM_OUTPUT_TOGGLE
+ * @param[in] u32CmpDownLevel output level at compare down point, valid values are:
+ *              - \ref EPWM_OUTPUT_NOTHING
+ *              - \ref EPWM_OUTPUT_LOW
+ *              - \ref EPWM_OUTPUT_HIGH
+ *              - \ref EPWM_OUTPUT_TOGGLE
+ * @return None
+ * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_SET_OUTPUT_LEVEL(epwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \
+   do{ \
+        uint32_t i; \
+        for(i = 0UL; i < 6UL; i++) { \
+            if((u32ChannelMask) & (1UL << i)) { \
+                (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (i << 1))) | ((u32ZeroLevel) << (i << 1))); \
+                (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))) | ((u32PeriodLevel) << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))); \
+                (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (i << 1))) | ((u32CmpUpLevel) << (i << 1))); \
+                (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))) | ((u32CmpDownLevel) << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))); \
+            } \
+        } \
+    }while(0)
+
+/**
+ * @brief Trigger brake event from specified channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4
+ * @param[in] u32BrakeType Type of brake trigger.
+ *              - \ref EPWM_FB_EDGE
+ *              - \ref EPWM_FB_LEVEL
+ * @return None
+ * @details This macro is used to trigger brake event from specified channel(s).
+ * \hideinitializer
+ */
+#define EPWM_TRIGGER_BRAKE(epwm, u32ChannelMask, u32BrakeType) ((epwm)->SWBRK |= ((u32ChannelMask) << (u32BrakeType)))
+
+/**
+ * @brief Set Dead zone clock source
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32AfterPrescaler Dead zone clock source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler).
+ * @return None
+ * @details This macro is used to set Dead zone clock source. Every two channels share the same setting.
+ * @note The write-protection function should be disabled before using this function.
+ * \hideinitializer
+ */
+#define EPWM_SET_DEADZONE_CLK_SRC(epwm, u32ChannelNum, u32AfterPrescaler) \
+    (((epwm)->DTCTL[(u32ChannelNum) >> 1]) = ((epwm)->DTCTL[(u32ChannelNum) >> 1] & ~EPWM_DTCTL0_1_DTCKSEL_Msk) | \
+    ((u32AfterPrescaler) << EPWM_DTCTL0_1_DTCKSEL_Pos))
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define EPWM functions prototype                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge);
+uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle);
+void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_EnableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+void EPWM_DisableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum);
+int32_t EPWM_EnableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Prescale, uint32_t u32PrescaleCnt);
+void EPWM_DisableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition);
+uint32_t EPWM_GetDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource);
+void EPWM_EnableCapture(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_DisableCapture(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_EnablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode);
+void EPWM_DisablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration);
+void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+void EPWM_DisableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+void EPWM_ClearCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge);
+uint32_t EPWM_GetCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
+void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource);
+void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource);
+void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource);
+uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource);
+void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum,  uint32_t u32IntPeriodType);
+void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_DisableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+uint32_t EPWM_GetZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableAcc(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc);
+void EPWM_DisableAcc(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_DisableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearAccInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+uint32_t EPWM_GetAccInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_DisableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_DisableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+uint32_t EPWM_GetFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
+void EPWM_DisableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
+void EPWM_ConfigSyncPhase(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase);
+void EPWM_EnableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_DisableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask);
+void EPWM_EnableSyncNoiseFilter(EPWM_T *epwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel);
+void EPWM_DisableSyncNoiseFilter(EPWM_T *epwm);
+void EPWM_EnableSyncPinInverse(EPWM_T *epwm);
+void EPWM_DisableSyncPinInverse(EPWM_T *epwm);
+void EPWM_SetClockSource(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel);
+void EPWM_EnableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel);
+void EPWM_DisableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum);
+void EPWM_EnableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum);
+void EPWM_DisableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum);
+void EPWM_SetBrakePinSource(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule);
+void EPWM_SetLeadingEdgeBlanking(EPWM_T *epwm, uint32_t u32TrigSrcSel, uint32_t u32TrigType, uint32_t u32BlankingCnt, uint32_t u32BlankingEnable);
+uint32_t EPWM_GetWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32AfterPrescaler, uint32_t u32ClkSel);
+void EPWM_DisableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_DisableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32DeglitchSmpCycle);
+void EPWM_DisableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32MaskCnt);
+void EPWM_DisableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_EnableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_DisableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+void EPWM_ClearFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+uint32_t EPWM_GetFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum);
+
+
+/**@}*/ /* end of group EPWM_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group EPWM_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_EPWM_H__ */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_ewdt.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_ewdt.h
new file mode 100644
index 0000000000..6e07dd6a33
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_ewdt.h
@@ -0,0 +1,218 @@
+/**************************************************************************//**
+ * @file     nu_ewdt.h
+ * @version  V3.00
+ * @brief    Extra Watchdog Timer(EWDT) driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_EWDT_H__
+#define __NU_EWDT_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup EWDT_Driver EWDT Driver
+  @{
+*/
+
+/** @addtogroup EWDT_EXPORTED_CONSTANTS EWDT Exported Constants
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/*  EWDT Time-out Interval Period Constant Definitions                                                     */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EWDT_TIMEOUT_2POW4           (0UL << EWDT_CTL_TOUTSEL_Pos) /*!< Setting EWDT time-out interval to 2^4 * EWDT clocks \hideinitializer */
+#define EWDT_TIMEOUT_2POW6           (1UL << EWDT_CTL_TOUTSEL_Pos) /*!< Setting EWDT time-out interval to 2^6 * EWDT clocks \hideinitializer */
+#define EWDT_TIMEOUT_2POW8           (2UL << EWDT_CTL_TOUTSEL_Pos) /*!< Setting EWDT time-out interval to 2^8 * EWDT clocks \hideinitializer */
+#define EWDT_TIMEOUT_2POW10          (3UL << EWDT_CTL_TOUTSEL_Pos) /*!< Setting EWDT time-out interval to 2^10 * EWDT clocks \hideinitializer */
+#define EWDT_TIMEOUT_2POW12          (4UL << EWDT_CTL_TOUTSEL_Pos) /*!< Setting EWDT time-out interval to 2^12 * EWDT clocks \hideinitializer */
+#define EWDT_TIMEOUT_2POW14          (5UL << EWDT_CTL_TOUTSEL_Pos) /*!< Setting EWDT time-out interval to 2^14 * EWDT clocks \hideinitializer */
+#define EWDT_TIMEOUT_2POW16          (6UL << EWDT_CTL_TOUTSEL_Pos) /*!< Setting EWDT time-out interval to 2^16 * EWDT clocks \hideinitializer */
+#define EWDT_TIMEOUT_2POW18          (7UL << EWDT_CTL_TOUTSEL_Pos) /*!< Setting EWDT time-out interval to 2^18 * EWDT clocks \hideinitializer */
+#define EWDT_TIMEOUT_2POW20          (8UL << EWDT_CTL_TOUTSEL_Pos) /*!< Setting EWDT time-out interval to 2^20 * EWDT clocks \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  EWDT Reset Delay Period Constant Definitions                                                           */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EWDT_RESET_DELAY_1026CLK     (0UL << EWDT_ALTCTL_RSTDSEL_Pos) /*!< Setting EWDT reset delay period to 1026 * EWDT clocks \hideinitializer */
+#define EWDT_RESET_DELAY_130CLK      (1UL << EWDT_ALTCTL_RSTDSEL_Pos) /*!< Setting EWDT reset delay period to 130 * EWDT clocks \hideinitializer */
+#define EWDT_RESET_DELAY_18CLK       (2UL << EWDT_ALTCTL_RSTDSEL_Pos) /*!< Setting EWDT reset delay period to 18 * EWDT clocks \hideinitializer */
+#define EWDT_RESET_DELAY_3CLK        (3UL << EWDT_ALTCTL_RSTDSEL_Pos) /*!< Setting EWDT reset delay period to 3 * EWDT clocks \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  EWDT Free Reset Counter Keyword Constant Definitions                                                   */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EWDT_RESET_COUNTER_KEYWORD   (0x00005AA5UL)    /*!< Fill this value to EWDT_RSTCNT register to free reset EWDT counter \hideinitializer */
+
+/**@}*/ /* end of group EWDT_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup EWDT_EXPORTED_FUNCTIONS EWDT Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Clear EWDT Reset System Flag
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro clears EWDT time-out reset system flag.
+  * \hideinitializer
+  */
+#define EWDT_CLEAR_RESET_FLAG()          (EWDT->CTL = (EWDT->CTL & ~(EWDT_CTL_IF_Msk | EWDT_CTL_WKF_Msk)) | EWDT_CTL_RSTF_Msk)
+
+/**
+  * @brief      Clear EWDT Time-out Interrupt Flag
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro clears EWDT time-out interrupt flag.
+  * \hideinitializer
+  */
+#define EWDT_CLEAR_TIMEOUT_INT_FLAG()    (EWDT->CTL = (EWDT->CTL & ~(EWDT_CTL_RSTF_Msk | EWDT_CTL_WKF_Msk)) | EWDT_CTL_IF_Msk)
+
+/**
+  * @brief      Clear EWDT Wake-up Flag
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro clears EWDT time-out wake-up system flag.
+  * \hideinitializer
+  */
+#define EWDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (EWDT->CTL = (EWDT->CTL & ~(EWDT_CTL_RSTF_Msk | EWDT_CTL_IF_Msk)) | EWDT_CTL_WKF_Msk)
+
+/**
+  * @brief      Get EWDT Time-out Reset Flag
+  *
+  * @param      None
+  *
+  * @retval     0   EWDT time-out reset system did not occur
+  * @retval     1   EWDT time-out reset system occurred
+  *
+  * @details    This macro indicates system has been reset by EWDT time-out reset or not.
+  * \hideinitializer
+  */
+#define EWDT_GET_RESET_FLAG()            ((EWDT->CTL & EWDT_CTL_RSTF_Msk)? 1UL : 0UL)
+
+/**
+  * @brief      Get EWDT Time-out Interrupt Flag
+  *
+  * @param      None
+  *
+  * @retval     0   EWDT time-out interrupt did not occur
+  * @retval     1   EWDT time-out interrupt occurred
+  *
+  * @details    This macro indicates EWDT time-out interrupt occurred or not.
+  * \hideinitializer
+  */
+#define EWDT_GET_TIMEOUT_INT_FLAG()      ((EWDT->CTL & EWDT_CTL_IF_Msk)? 1UL : 0UL)
+
+/**
+  * @brief      Get EWDT Time-out Wake-up Flag
+  *
+  * @param      None
+  *
+  * @retval     0   EWDT time-out interrupt does not cause CPU wake-up
+  * @retval     1   EWDT time-out interrupt event cause CPU wake-up
+  *
+  * @details    This macro indicates EWDT time-out interrupt event has waked up system or not.
+  * \hideinitializer
+  */
+#define EWDT_GET_TIMEOUT_WAKEUP_FLAG()   ((EWDT->CTL & EWDT_CTL_WKF_Msk)? 1UL : 0UL)
+
+/**
+  * @brief      Reset EWDT Counter
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to reset the internal 20-bit EWDT up counter value.
+  * @note       If EWDT is activated and time-out reset system function is enabled also, user should \n
+  *             reset the 20-bit EWDT up counter value to avoid generate EWDT time-out reset signal to \n
+  *             reset system before the EWDT time-out reset delay period expires.
+  * \hideinitializer
+  */
+#define EWDT_RESET_COUNTER()             (EWDT->RSTCNT = EWDT_RESET_COUNTER_KEYWORD)
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* static inline functions                                                                                 */
+/*---------------------------------------------------------------------------------------------------------*/
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
+__STATIC_INLINE void EWDT_Close(void);
+__STATIC_INLINE void EWDT_EnableInt(void);
+__STATIC_INLINE void EWDT_DisableInt(void);
+
+/**
+  * @brief      Stop EWDT Counting
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This function will stop EWDT counting and disable EWDT module.
+  */
+__STATIC_INLINE void EWDT_Close(void)
+{
+    EWDT->CTL = 0UL;
+    while((EWDT->CTL & EWDT_CTL_SYNC_Msk) == EWDT_CTL_SYNC_Msk) {} /* Wait disable WDTEN bit completed, it needs 2 * EWDT_CLK. */
+}
+
+/**
+  * @brief      Enable EWDT Time-out Interrupt
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This function will enable the EWDT time-out interrupt function.
+  */
+__STATIC_INLINE void EWDT_EnableInt(void)
+{
+    EWDT->CTL |= EWDT_CTL_INTEN_Msk;
+}
+
+/**
+  * @brief      Disable EWDT Time-out Interrupt
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This function will disable the EWDT time-out interrupt function.
+  */
+__STATIC_INLINE void EWDT_DisableInt(void)
+{
+    /* Do not touch another write 1 clear bits */
+    EWDT->CTL &= ~(EWDT_CTL_INTEN_Msk | EWDT_CTL_RSTF_Msk | EWDT_CTL_IF_Msk | EWDT_CTL_WKF_Msk);
+}
+
+void EWDT_Open(uint32_t u32TimeoutInterval, uint32_t u32ResetDelay, uint32_t u32EnableReset, uint32_t u32EnableWakeup);
+
+/**@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group WDT_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_EWDT_H__ */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_ewwdt.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_ewwdt.h
new file mode 100644
index 0000000000..a453e8094a
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_ewwdt.h
@@ -0,0 +1,150 @@
+/**************************************************************************//**
+ * @file     nu_ewwdt.h
+ * @version  V3.00
+ * @brief    Extra Window Watchdog Timer(EWWDT) driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_EWWDT_H__
+#define __NU_EWWDT_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup EWWDT_Driver EWWDT Driver
+  @{
+*/
+
+/** @addtogroup EWWDT_EXPORTED_CONSTANTS EWWDT Exported Constants
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/*  EWWDT Prescale Period Constant Definitions                                                             */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EWWDT_PRESCALER_1        (0 << EWWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 1 * (64*EWWDT_CLK) \hideinitializer */
+#define EWWDT_PRESCALER_2        (1 << EWWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 2 * (64*EWWDT_CLK) \hideinitializer */
+#define EWWDT_PRESCALER_4        (2 << EWWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 4 * (64*EWWDT_CLK) \hideinitializer */
+#define EWWDT_PRESCALER_8        (3 << EWWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 8 * (64*EWWDT_CLK) \hideinitializer */
+#define EWWDT_PRESCALER_16       (4 << EWWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 16 * (64*EWWDT_CLK) \hideinitializer */
+#define EWWDT_PRESCALER_32       (5 << EWWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 32 * (64*EWWDT_CLK) \hideinitializer */
+#define EWWDT_PRESCALER_64       (6 << EWWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 64 * (64*EWWDT_CLK) \hideinitializer */
+#define EWWDT_PRESCALER_128      (7 << EWWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 128 * (64*EWWDT_CLK) \hideinitializer */
+#define EWWDT_PRESCALER_192      (8 << EWWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 192 * (64*EWWDT_CLK) \hideinitializer */
+#define EWWDT_PRESCALER_256      (9 << EWWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 256 * (64*EWWDT_CLK) \hideinitializer */
+#define EWWDT_PRESCALER_384      (10 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 384 * (64*EWWDT_CLK) \hideinitializer */
+#define EWWDT_PRESCALER_512      (11 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 512 * (64*EWWDT_CLK) \hideinitializer */
+#define EWWDT_PRESCALER_768      (12 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 768 * (64*EWWDT_CLK) \hideinitializer */
+#define EWWDT_PRESCALER_1024     (13 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1024 * (64*EWWDT_CLK) \hideinitializer */
+#define EWWDT_PRESCALER_1536     (14 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1536 * (64*EWWDT_CLK) \hideinitializer */
+#define EWWDT_PRESCALER_2048     (15 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2048 * (64*EWWDT_CLK) \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  EWWDT Reload Counter Keyword Constant Definitions                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define EWWDT_RELOAD_WORD        (0x00005AA5UL)         /*!< Fill this value to EWWDT_RLDCNT register to reload EWWDT counter \hideinitializer */
+
+/**@}*/ /* end of group EWWDT_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup EWWDT_EXPORTED_FUNCTIONS EWWDT Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Clear EWWDT Reset System Flag
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to clear EWWDT time-out reset system flag.
+  * \hideinitializer
+  */
+#define EWWDT_CLEAR_RESET_FLAG()     (EWWDT->STATUS = EWWDT_STATUS_WWDTRF_Msk)
+
+/**
+  * @brief      Clear EWWDT Compared Match Interrupt Flag
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to clear EWWDT compared match interrupt flag.
+  * \hideinitializer
+  */
+#define EWWDT_CLEAR_INT_FLAG()       (EWWDT->STATUS = EWWDT_STATUS_WWDTIF_Msk)
+
+/**
+  * @brief      Get EWWDT Reset System Flag
+  *
+  * @param      None
+  *
+  * @retval     0   EWWDT time-out reset system did not occur
+  * @retval     1   EWWDT time-out reset system occurred
+  *
+  * @details    This macro is used to indicate system has been reset by EWWDT time-out reset or not.
+  * \hideinitializer
+  */
+#define EWWDT_GET_RESET_FLAG()       ((EWWDT->STATUS & EWWDT_STATUS_WWDTRF_Msk)? 1 : 0)
+
+/**
+  * @brief      Get EWWDT Compared Match Interrupt Flag
+  *
+  * @param      None
+  *
+  * @retval     0   EWWDT compare match interrupt did not occur
+  * @retval     1   EWWDT compare match interrupt occurred
+  *
+  * @details    This macro is used to indicate EWWDT counter value matches CMPDAT value or not.
+  * \hideinitializer
+  */
+#define EWWDT_GET_INT_FLAG()         ((EWWDT->STATUS & EWWDT_STATUS_WWDTIF_Msk)? 1 : 0)
+
+/**
+  * @brief      Get EWWDT Counter
+  *
+  * @param      None
+  *
+  * @return     EWWDT Counter Value
+  *
+  * @details    This macro reflects the current EWWDT counter value.
+  * \hideinitializer
+  */
+#define EWWDT_GET_COUNTER()          (EWWDT->CNT)
+
+/**
+  * @brief      Reload EWWDT Counter
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to reload the EWWDT counter value to 0x3F.
+  * @note       User can only write EWWDT_RLDCNT register to reload EWWDT counter value when current EWWDT counter value \n
+  *             between 0 and CMPDAT value. If user writes EWWDT_RLDCNT when current EWWDT counter value is larger than CMPDAT, \n
+  *             EWWDT reset signal will generate immediately to reset system.
+  * \hideinitializer
+  */
+#define EWWDT_RELOAD_COUNTER()       (EWWDT->RLDCNT = EWWDT_RELOAD_WORD)
+
+void EWWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt);
+
+/**@}*/ /* end of group EWWDT_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group EWWDT_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_EWWDT_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_fmc.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_fmc.h
new file mode 100644
index 0000000000..98700d318c
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_fmc.h
@@ -0,0 +1,588 @@
+/**************************************************************************//**
+ * @file     nu_fmc.h
+ * @version  V3.0
+ * $Revision: 2 $
+ * $Date: 19/11/27 3:11p $
+ * @brief    M2355 Series Flash Memory Controller(FMC) driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __NU_FMC_H__
+#define __NU_FMC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup FMC_Driver FMC Driver
+  @{
+*/
+
+/** @addtogroup FMC_EXPORTED_CONSTANTS FMC Exported Constants
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Global constant definitions                                                                                     */
+/*---------------------------------------------------------------------------------------------------------*/
+#define ISBEN   0UL
+#define FMC_ISP   ( (__PC() & 0x10000000) ? FMC_NS : FMC)
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define Base Address                                                                                     */
+/*---------------------------------------------------------------------------------------------------------*/
+#define FMC_APROM_BASE          0x00000000UL    /*!< APROM  Base Address          */
+#define FMC_APROM_END           0x00100000UL    /*!< APROM end address            */
+#define FMC_APROM_BANK0_END     (FMC_APROM_END/2UL)  /*!< APROM bank0 end address */
+#define FMC_LDROM_BASE          0x00100000UL    /*!< LDROM  Base Address          */
+#define FMC_LDROM_END           0x00104000UL    /*!< LDROM end address            */
+#define FMC_DTFSH_BASE          0x00110000UL    /*!< LDROM  Base Address          */
+#define FMC_DTFSH_END           0x00112000UL    /*!< LDROM end address            */
+#define FMC_XOM_BASE            0x00200000UL    /*!< XOM  Base Address            */
+#define FMC_XOMR0_BASE          0x00200000UL    /*!< XOMR 0 Base Address */
+#define FMC_XOMR1_BASE          0x00200010UL    /*!< XOMR 1 Base Address */
+#define FMC_XOMR2_BASE          0x00200020UL    /*!< XOMR 2 Base Address */
+#define FMC_XOMR3_BASE          0x00200030UL    /*!< XOMR 3 Base Address */
+#define FMC_NSCBA_BASE          0x00210800UL    /*!< Non-Secure base address      */
+#define FMC_SCRLOCK_BASE        0x00610000UL    /*!< Secure Region Lock base address */
+#define FMC_ARLOCK_BASE         0x00610008UL    /*!< All Region Lock base address */
+#define FMC_CONFIG_BASE         0x00300000UL    /*!< CONFIG Base Address          */
+#define FMC_USER_CONFIG_0       0x00300000UL    /*!< CONFIG 0 Address */
+#define FMC_USER_CONFIG_1       0x00300004UL    /*!< CONFIG 1 Address */
+#define FMC_USER_CONFIG_2       0x00300008UL    /*!< CONFIG 2 Address */
+#define FMC_USER_CONFIG_3       0x0030000CUL    /*!< CONFIG 3 Address */
+#define FMC_OTP_BASE            0x00310000UL    /*!< OTP flash base address       */
+
+#define FMC_FLASH_PAGE_SIZE     0x800UL         /*!< Flash Page Size (2048 Bytes) */
+#define FMC_PAGE_ADDR_MASK      0xFFFFF800UL    /*!< Flash page address mask      */
+#define FMC_MULTI_WORD_PROG_LEN 512UL           /*!< The maximum length of a multi-word program.  */
+
+#define FMC_APROM_SIZE          FMC_APROM_END   /*!< APROM Size                  */
+#define FMC_BANK_SIZE           (FMC_APROM_SIZE/2UL) /*!< APROM Bank Size             */
+#define FMC_LDROM_SIZE          0x4000UL        /*!< LDROM Size (4 Kbytes)       */
+#define FMC_OTP_ENTRY_CNT       256UL           /*!< OTP entry number            */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  XOM region number constant definitions                                                                 */
+/*---------------------------------------------------------------------------------------------------------*/
+#define XOMR0   0UL                             /*!< XOM region 0     */
+#define XOMR1   1UL                             /*!< XOM region 1     */
+#define XOMR2   2UL                             /*!< XOM region 2     */
+#define XOMR3   3UL                             /*!< XOM region 3     */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  ISPCTL constant definitions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+#define IS_BOOT_FROM_LDROM      0x1UL     /*!< ISPCTL setting to select to boot from LDROM */
+#define IS_BOOT_FROM_APROM      0x0UL     /*!< ISPCTL setting to select to boot from APROM */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  ISPCMD constant definitions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+#define FMC_ISPCMD_READ         0x00UL     /*!< ISP Command: Read Flash               */
+#define FMC_ISPCMD_READ_UID     0x04UL     /*!< ISP Command: Read Unique ID           */
+#define FMC_ISPCMD_READ_ALL1    0x08UL     /*!< ISP Command: Read all-one result      */
+#define FMC_ISPCMD_READ_CID     0x0BUL     /*!< ISP Command: Read Company ID          */
+#define FMC_ISPCMD_READ_DID     0x0CUL     /*!< ISP Command: Read Device ID           */
+#define FMC_ISPCMD_READ_CKS     0x0DUL     /*!< ISP Command: Read Checksum            */
+#define FMC_ISPCMD_PROGRAM      0x21UL     /*!< ISP Command: 32-bit Program Flash     */
+#define FMC_ISPCMD_PAGE_ERASE   0x22UL     /*!< ISP Command: Page Erase Flash         */
+#define FMC_ISPCMD_BANK_ERASE   0x23UL     /*!< ISP Command: Erase Flash bank 0 or 1  */
+#define FMC_ISPCMD_PROGRAM_MUL  0x27UL     /*!< ISP Command: Flash Multi-Word Program */
+#define FMC_ISPCMD_RUN_ALL1     0x28UL     /*!< ISP Command: Run all-one verification */
+#define FMC_ISPCMD_BANK_REMAP   0x2CUL     /*!< ISP Command: Bank Remap                */
+#define FMC_ISPCMD_RUN_CKS      0x2DUL     /*!< ISP Command: Run Check Calculation    */
+#define FMC_ISPCMD_VECMAP       0x2EUL     /*!< ISP Command: Set vector mapping       */
+#define FMC_ISPCMD_READ_64      0x40UL     /*!< ISP Command: 64-bit read Flash        */
+#define FMC_ISPCMD_PROGRAM_64   0x61UL     /*!< ISP Command: 64-bit program Flash     */
+
+#define READ_ALLONE_YES         0xA11FFFFFUL    /*!< Check-all-one result is all one.     */
+#define READ_ALLONE_NOT         0xA1100000UL    /*!< Check-all-one result is not all one. */
+#define READ_ALLONE_CMD_FAIL    0xFFFFFFFFUL    /*!< Check-all-one command failed.        */
+
+/**@}*/ /* end of group FMC_EXPORTED_CONSTANTS */
+
+/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  FMC Macro Definitions                                                                                  */
+/*---------------------------------------------------------------------------------------------------------*/
+/**
+ * @brief      Enable ISP Function
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function will set ISPEN bit of ISPCTL control register to enable ISP function.
+ *
+ */
+#define FMC_ENABLE_ISP()          (FMC_ISP->ISPCTL |=  FMC_ISPCTL_ISPEN_Msk)  /*!< Enable ISP Function  */
+
+/**
+ * @brief      Disable ISP Function
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function will clear ISPEN bit of ISPCTL control register to disable ISP function.
+ *
+ */
+#define FMC_DISABLE_ISP()         (FMC_ISP->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk)  /*!< Disable ISP Function */
+
+/**
+ * @brief      Disable Non Secure ISP Function
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function will clear ISPEN bit of ISPCTL control register to disable Non Secure ISP function.
+ *
+ */
+
+#define FMC_ENABLE_LD_UPDATE()    (FMC->ISPCTL |=  FMC_ISPCTL_LDUEN_Msk)  /*!< Enable LDROM Update Function   */
+
+/**
+ * @brief      Disable LDROM Update Function
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function will set ISPEN bit of ISPCTL control register to disable LDROM update function.
+ *
+ */
+#define FMC_DISABLE_LD_UPDATE()   (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk)  /*!< Disable LDROM Update Function  */
+
+/**
+ * @brief      Enable User Configuration Update Function
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function will set CFGUEN bit of ISPCTL control register to enable User Configuration update function.
+ *             User needs to set CFGUEN bit before they can update User Configuration area.
+ *
+ */
+#define FMC_ENABLE_CFG_UPDATE()   (FMC->ISPCTL |=  FMC_ISPCTL_CFGUEN_Msk) /*!< Enable CONFIG Update Function  */
+
+/**
+ * @brief      Disable User Configuration Update Function
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function will clear CFGUEN bit of ISPCTL control register to disable User Configuration update function.
+ *
+ */
+#define FMC_DISABLE_CFG_UPDATE()  (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk) /*!< Disable CONFIG Update Function */
+
+
+/**
+ * @brief      Enable APROM Update Function
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function will set APUEN bit of ISPCTL control register to enable APROM update function.
+ *             User needs to set APUEN bit before they can update APROM in APROM boot mode.
+ *
+ */
+#define FMC_ENABLE_AP_UPDATE()    (FMC_ISP->ISPCTL |=  FMC_ISPCTL_APUEN_Msk)  /*!< Enable APROM Update Function   */
+
+/**
+ * @brief      Disable APROM Update Function
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function will clear APUEN bit of ISPCTL control register to disable APROM update function.
+ *
+ */
+#define FMC_DISABLE_AP_UPDATE()   (FMC_ISP->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk)  /*!< Disable APROM Update Function  */
+
+/**
+ * @brief      Get ISP Fail Flag
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function is used to get ISP fail flag when do ISP actoin.
+ *
+ */
+#define FMC_GET_FAIL_FLAG()         ((FMC_ISP->ISPCTL & FMC_ISPCTL_ISPFF_Msk) ? 1UL : 0UL)  /*!< Get ISP fail flag */
+
+/**
+ * @brief      Clear ISP Fail Flag
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function is used to clear ISP fail flag when ISP fail flag set.
+ *
+ */
+#define FMC_CLR_FAIL_FLAG()         (FMC_ISP->ISPCTL |= FMC_ISPCTL_ISPFF_Msk)       /*!< Clear ISP fail flag */
+
+/**
+ * @brief      Enable ISP Interrupt
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function will enable ISP action interrupt.
+ *
+ */
+#define FMC_ENABLE_ISP_INT()     (FMC_ISP->ISPCTL |=  FMC_ISPCTL_INTEN_Msk) /*!< Enable ISP interrupt */
+
+/**
+ * @brief      Disable ISP Interrupt
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function will disable ISP action interrupt.
+ *
+ */
+#define FMC_DISABLE_ISP_INT()     (FMC_ISP->ISPCTL &= ~FMC_ISPCTL_INTEN_Msk) /*!< Disable ISP interrupt */
+
+/**
+ * @brief      Get ISP Interrupt Flag
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function will get ISP action interrupt status
+ *
+ */
+#define FMC_GET_ISP_INT_FLAG()     ((FMC_ISP->ISPSTS & FMC_ISPSTS_INTFLAG_Msk) ? 1UL : 0UL) /*!< Get ISP interrupt flag Status */
+
+/**
+ * @brief      Clear ISP Interrupt Flag
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function will clear ISP interrupt flag
+ *
+ */
+#define FMC_CLEAR_ISP_INT_FLAG()     (FMC_ISP->ISPSTS = FMC_ISPSTS_INTFLAG_Msk) /*!< Clear ISP interrupt flag*/
+
+/**
+ * @brief      Enable Data Flash Scrambling Function
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function will set SCRAMEN bit of DFCTL control register to enable Data Flash Scrambling Function.
+ *
+ */
+#define FMC_ENABLE_SCRAMBLE()          (FMC->DFCTL |= FMC_DFCTL_SCRAMEN_Msk)  /*!< Enable Data Flash Scrambling Function  */
+
+/**
+ * @brief      Disable Data Flash Scrambling Function
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function will clear SCRAMEN bit of DFCTL control register to disable Data Flash Scrambling Function.
+ *
+ */
+#define FMC_DISABLE_SCRAMBLE()          (FMC->DFCTL &= ~FMC_DFCTL_SCRAMEN_Msk)  /*!< Disable Data Flash Scrambling Function  */
+
+/**
+ * @brief      Enable Data Flash Silent Access Function
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function will set SILENTEN bit of DFCTL control register to enable Data Flash Silent Access Function.
+ *
+ */
+#define FMC_ENABLE_SILENT()          (FMC->DFCTL |= FMC_DFCTL_SILENTEN_Msk)  /*!< Enable Data Flash Silent Access Function  */
+
+/**
+ * @brief      Disable Data Flash Silent Access Function
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function will clear SILENTEN bit of DFCTL control register to disable Data Flash Silent Access Function.
+ *
+ */
+#define FMC_DISABLE_SILENT()          (FMC->DFCTL &= ~FMC_DFCTL_SILENTEN_Msk)  /*!< Disable Data Flash Silent Access Function  */
+
+/**
+ * @brief      Enable Data Flash Temper Attack Program Function
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function will set TMPCLR bit of DFCTL control register to enable Data Flash Temper Attack Program Function.
+ *
+ */
+#define FMC_ENABLE_TMPCLR()          (FMC->DFCTL |= FMC_DFCTL_TMPCLR_Msk)  /*!< Enable Data Flash Temper Attack Program Function  */
+
+/**
+ * @brief      Disable Data Flash Temper Attack Program Function
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function will clear TMPCLR bit of DFCTL control register to disable Data Flash Temper Attack Program Function.
+ *
+ */
+#define FMC_DISABLE_TMPCLR()          (FMC->DFCTL &= ~FMC_DFCTL_TMPCLR_Msk)  /*!< Disable Data Flash Temper Attack Program Function  */
+
+/**
+ * @brief      Get Data Flash Temper Attack Programming Done Flag
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function will get Data Flash Temper Attack Programming Done flag
+ *
+ */
+#define FMC_GET_TMPCLRDONE_FLAG()     ((FMC->DFSTS & FMC_DFSTS_TMPCLRDONE_Msk) ? 1UL : 0UL) /*!< Get Data Flash Temper Attack Programming Done Flag */
+
+/**
+ * @brief      Get Data Flash Temper Attack Programming Busy Flag
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function will get Data Flash Temper Attack Programming Busy flag
+ *
+ */
+#define FMC_GET_TMPCLRBUSY_FLAG()     ((FMC->DFSTS & FMC_DFSTS_TMPCLRBUSY_Msk) ? 1UL : 0UL) /*!< Get Data Flash Temper Attack Programming Busy Flag */
+
+/**
+ * @brief      Clear Data Flash Temper Attack Programming Done Flag
+ *
+ * @param      None
+ *
+ * @return     None
+ *
+ * @details    This function will clear Data Flash Temper Attack Programming Done flag
+ *
+ */
+#define FMC_CLEAR_TMPCLRDONE_FLAG()     (FMC->DFSTS |= FMC_DFSTS_TMPCLRDONE_Msk)  /*!< Clear Data Flash Temper Attack Programming Done Flag */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* inline functions                                                                                        */
+/*---------------------------------------------------------------------------------------------------------*/
+__STATIC_INLINE uint32_t FMC_ReadCID(void);
+__STATIC_INLINE uint32_t FMC_ReadPID(void);
+__STATIC_INLINE uint32_t FMC_ReadUID(uint8_t u8Index);
+__STATIC_INLINE uint32_t FMC_ReadUCID(uint32_t u32Index);
+__STATIC_INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr);
+__STATIC_INLINE uint32_t FMC_GetVECMAP(void);
+__STATIC_INLINE void FMC_SetScrambleKey(uint32_t u32ScrambleKey);
+
+/**
+ * @brief       Get current vector mapping address.
+ *
+ * @param       None
+ *
+ * @return      The current vector mapping address.
+ *
+ * @details     To get VECMAP value which is the page address for remapping to vector page (0x0).
+ *
+ */
+__STATIC_INLINE uint32_t FMC_GetVECMAP(void)
+{
+    return (FMC->ISPSTS & FMC_ISPSTS_VECMAP_Msk);
+}
+
+/**
+  * @brief    Read company ID
+  *
+  * @param    None
+  *
+  * @return   The company ID (32-bit)
+  *
+  * @details  The company ID of Nuvoton is fixed to be 0xDA
+  */
+__STATIC_INLINE uint32_t FMC_ReadCID(void)
+{
+    FMC_ISP->ISPCMD = FMC_ISPCMD_READ_CID;           /* Set ISP Command Code */
+    FMC_ISP->ISPADDR = 0x0u;                         /* Must keep 0x0 when read CID */
+    FMC_ISP->ISPTRG = FMC_ISPTRG_ISPGO_Msk;          /* Trigger to start ISP procedure */
+#if ISBEN
+    __ISB();
+#endif                                           /* To make sure ISP/CPU be Synchronized */
+    while(FMC_ISP->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */
+
+    return FMC_ISP->ISPDAT;
+}
+
+/**
+  * @brief    Read product ID
+  *
+  * @param    None
+  *
+  * @return   The product ID (32-bit)
+  *
+  * @details  This function is used to read product ID.
+  */
+__STATIC_INLINE uint32_t FMC_ReadPID(void)
+{
+    FMC_ISP->ISPCMD = FMC_ISPCMD_READ_DID;          /* Set ISP Command Code */
+    FMC_ISP->ISPADDR = 0x04u;                       /* Must keep 0x4 when read PID */
+    FMC_ISP->ISPTRG = FMC_ISPTRG_ISPGO_Msk;         /* Trigger to start ISP procedure */
+#if ISBEN
+    __ISB();
+#endif                                          /* To make sure ISP/CPU be Synchronized */
+    while(FMC_ISP->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */
+
+    return FMC_ISP->ISPDAT;
+}
+
+
+/**
+ * @brief       Read Unique ID
+ *
+ * @param[in]   u8Index  UID index. 0 = UID[31:0], 1 = UID[63:32], 2 = UID[95:64]
+ *
+ * @return      The 32-bit unique ID data of specified UID index.
+ *
+ * @details     To read out 96-bit Unique ID.
+ */
+__STATIC_INLINE uint32_t FMC_ReadUID(uint8_t u8Index)
+{
+    FMC_ISP->ISPCMD = FMC_ISPCMD_READ_UID;
+    FMC_ISP->ISPADDR = ((uint32_t)u8Index << 2u);
+    FMC_ISP->ISPDAT = 0u;
+    FMC_ISP->ISPTRG = 0x1u;
+#if ISBEN
+    __ISB();
+#endif
+    while(FMC_ISP->ISPTRG) {}
+
+    return FMC_ISP->ISPDAT;
+}
+
+/**
+  * @brief      To read UCID
+  *
+  * @param[in]  u32Index    Index of the UCID to read. u32Index must be 0, 1, 2, or 3.
+  *
+  * @return     The UCID of specified index
+  *
+  * @details    This function is used to read unique chip ID (UCID).
+  */
+__STATIC_INLINE uint32_t FMC_ReadUCID(uint32_t u32Index)
+{
+    FMC_ISP->ISPCMD = FMC_ISPCMD_READ_UID;            /* Set ISP Command Code */
+    FMC_ISP->ISPADDR = (0x04u * u32Index) + 0x10u;    /* The UCID is at offset 0x10 with word alignment. */
+    FMC_ISP->ISPTRG = FMC_ISPTRG_ISPGO_Msk;           /* Trigger to start ISP procedure */
+#if ISBEN
+    __ISB();
+#endif                                            /* To make sure ISP/CPU be Synchronized */
+    while(FMC_ISP->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {}  /* Waiting for ISP Done */
+
+    return FMC_ISP->ISPDAT;
+}
+
+
+/**
+ * @brief       Set vector mapping address
+ *
+ * @param[in]   u32PageAddr  The page address to remap to address 0x0. The address must be page alignment.
+ *
+ * @return      To set VECMAP to remap specified page address to 0x0.
+ *
+ * @details     This function is used to set VECMAP to map specified page to vector page (0x0).
+ */
+__STATIC_INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr)
+{
+    FMC->ISPCMD = FMC_ISPCMD_VECMAP;  /* Set ISP Command Code */
+    FMC->ISPADDR = u32PageAddr;       /* The address of specified page which will be map to address 0x0. It must be page alignment. */
+    FMC->ISPTRG = 0x1u;               /* Trigger to start ISP procedure */
+#if ISBEN
+    __ISB();
+#endif                                /* To make sure ISP/CPU be Synchronized */
+    while(FMC->ISPTRG) {}             /* Waiting for ISP Done */
+}
+
+/**
+ * @brief       Set Data Flash scrambling key
+ *
+ * @param[in]   u32ScramKey  The value of scrambling key.
+ *
+ * @return      NULL
+ *
+ * @details     This function is used to set Data Flash scrambling key.
+ */
+__STATIC_INLINE void FMC_SetScrambleKey(uint32_t u32ScrambleKey)
+{
+    FMC->SCRKEY = u32ScrambleKey;
+}
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Functions                                                                                              */
+/*---------------------------------------------------------------------------------------------------------*/
+
+extern uint32_t  FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count);
+extern void FMC_Close(void);
+extern int32_t FMC_ConfigXOM(uint32_t xom_num, uint32_t xom_base, uint8_t xom_page);
+extern int32_t FMC_Erase(uint32_t u32PageAddr);
+extern int32_t FMC_EraseBank(uint32_t u32BankAddr);
+extern int32_t FMC_EraseXOM(uint32_t xom_num);
+extern uint32_t  FMC_GetChkSum(uint32_t u32addr, uint32_t u32count);
+extern int32_t FMC_IsOTPLocked(uint32_t otp_num);
+extern int32_t FMC_GetXOMState(uint32_t xom_num);
+extern int32_t FMC_LockOTP(uint32_t otp_num);
+extern void FMC_Open(void);
+extern uint32_t FMC_Read(uint32_t u32Addr);
+extern int32_t FMC_Read64(uint32_t u32addr, uint32_t * u32data0, uint32_t * u32data1);
+extern int32_t FMC_ReadOTP(uint32_t otp_num, uint32_t *low_word, uint32_t *high_word);
+extern int32_t FMC_ReadConfig(uint32_t u32Config[], uint32_t u32Count);
+extern void FMC_Write(uint32_t u32Addr, uint32_t u32Data);
+extern int32_t FMC_Write8Bytes(uint32_t u32addr, uint32_t u32data0, uint32_t u32data1);
+extern int32_t FMC_WriteConfig(uint32_t au32Config[], uint32_t u32Count);
+extern int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len);
+extern int32_t FMC_WriteOTP(uint32_t otp_num, uint32_t low_word, uint32_t high_word);
+extern int32_t FMC_WriteMultipleA(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len);
+extern int32_t FMC_RemapBank(uint32_t u32Bank);
+
+/**@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group FMC_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_FMC_H__ */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_fvc.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_fvc.h
new file mode 100644
index 0000000000..858ccd3fa1
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_fvc.h
@@ -0,0 +1,55 @@
+/**************************************************************************//**
+ * @file     nu_fvc.h
+ * @version  V3.00
+ * @brief    Firmware Version Counter Driver Header
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_FVC_H__
+#define __NU_FVC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup FVC_Driver FVC Driver
+  @{
+*/
+
+/** @addtogroup FVC_EXPORTED_CONSTANTS FVC Exported Constants
+  @{
+*/
+
+#define FVC_VCODE   (0x77100000ul)  /*!< The key code for FVC_CTL write. */
+
+/**@}*/ /* end of group FVC_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup FVC_EXPORTED_FUNCTIONS FVC Exported Functions
+  @{
+*/
+
+int32_t FVC_Open(void);
+void FVC_EnableMonotone(void);
+int32_t FVC_SetNVC(uint32_t u32NvcIdx, uint32_t u32Cnt);
+int32_t FVC_GetNVC(uint32_t u32NvcIdx);
+
+
+/**@}*/ /* end of group FVC_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group FVC_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_FVC_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_gpio.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_gpio.h
new file mode 100644
index 0000000000..3a8f872452
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_gpio.h
@@ -0,0 +1,1155 @@
+/**************************************************************************//**
+ * @file     nu_gpio.h
+ * @version  V3.0
+ * @brief    M2354 series General Purpose I/O (GPIO) driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __NU_GPIO_H__
+#define __NU_GPIO_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup GPIO_Driver GPIO Driver
+  @{
+*/
+
+/** @addtogroup GPIO_EXPORTED_CONSTANTS GPIO Exported Constants
+  @{
+*/
+
+#define GPIO_PIN_MAX            16UL /*!< Specify Maximum Pins of Each GPIO Port */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  GPIO_MODE Constant Definitions                                                                         */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_MODE_INPUT          0x0UL /*!< Input Mode */
+#define GPIO_MODE_OUTPUT         0x1UL /*!< Output Mode */
+#define GPIO_MODE_OPEN_DRAIN     0x2UL /*!< Open-Drain Mode */
+#define GPIO_MODE_QUASI          0x3UL /*!< Quasi-bidirectional Mode */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  GPIO Interrupt Type Constant Definitions                                                               */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_INT_RISING         0x00010000UL /*!< Interrupt enable by Input Rising Edge */
+#define GPIO_INT_FALLING        0x00000001UL /*!< Interrupt enable by Input Falling Edge */
+#define GPIO_INT_BOTH_EDGE      0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge */
+#define GPIO_INT_HIGH           0x01010000UL /*!< Interrupt enable by Level-High */
+#define GPIO_INT_LOW            0x01000001UL /*!< Interrupt enable by Level-Level */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  GPIO_INTTYPE Constant Definitions                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_INTTYPE_EDGE           0UL /*!< GPIO_INTTYPE Setting for Edge Trigger Mode */
+#define GPIO_INTTYPE_LEVEL          1UL /*!< GPIO_INTTYPE Setting for Edge Level Mode */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  GPIO Slew Rate Type Constant Definitions                                                               */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_SLEWCTL_NORMAL         0x0UL           /*!< GPIO slew setting for normal Mode */
+#define GPIO_SLEWCTL_HIGH           0x1UL           /*!< GPIO slew setting for high Mode */
+#define GPIO_SLEWCTL_FAST           0x2UL           /*!< GPIO slew setting for fast Mode */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  GPIO Pull-up And Pull-down Type Constant Definitions                                                   */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_PUSEL_DISABLE          0x0UL           /*!< GPIO PUSEL setting for Disable Mode */
+#define GPIO_PUSEL_PULL_UP          0x1UL           /*!< GPIO PUSEL setting for Pull-up Mode */
+#define GPIO_PUSEL_PULL_DOWN        0x2UL           /*!< GPIO PUSEL setting for Pull-down Mode */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  GPIO_DBCTL Constant Definitions                                                                        */
+/*---------------------------------------------------------------------------------------------------------*/
+#define GPIO_DBCTL_ICLK_ON            0x00000020UL /*!< GPIO_DBCTL setting for all IO pins edge detection circuit is always active after reset */
+#define GPIO_DBCTL_ICLK_OFF           0x00000000UL /*!< GPIO_DBCTL setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 */
+
+#define GPIO_DBCTL_DBCLKSRC_LIRC      0x00000010UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the internal 10 kHz */
+#define GPIO_DBCTL_DBCLKSRC_HCLK      0x00000000UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the HCLK */
+
+#define GPIO_DBCTL_DBCLKSEL_1         0x00000000UL /*!< GPIO_DBCTL setting for sampling cycle = 1 clocks */
+#define GPIO_DBCTL_DBCLKSEL_2         0x00000001UL /*!< GPIO_DBCTL setting for sampling cycle = 2 clocks */
+#define GPIO_DBCTL_DBCLKSEL_4         0x00000002UL /*!< GPIO_DBCTL setting for sampling cycle = 4 clocks */
+#define GPIO_DBCTL_DBCLKSEL_8         0x00000003UL /*!< GPIO_DBCTL setting for sampling cycle = 8 clocks */
+#define GPIO_DBCTL_DBCLKSEL_16        0x00000004UL /*!< GPIO_DBCTL setting for sampling cycle = 16 clocks */
+#define GPIO_DBCTL_DBCLKSEL_32        0x00000005UL /*!< GPIO_DBCTL setting for sampling cycle = 32 clocks */
+#define GPIO_DBCTL_DBCLKSEL_64        0x00000006UL /*!< GPIO_DBCTL setting for sampling cycle = 64 clocks */
+#define GPIO_DBCTL_DBCLKSEL_128       0x00000007UL /*!< GPIO_DBCTL setting for sampling cycle = 128 clocks */
+#define GPIO_DBCTL_DBCLKSEL_256       0x00000008UL /*!< GPIO_DBCTL setting for sampling cycle = 256 clocks */
+#define GPIO_DBCTL_DBCLKSEL_512       0x00000009UL /*!< GPIO_DBCTL setting for sampling cycle = 512 clocks */
+#define GPIO_DBCTL_DBCLKSEL_1024      0x0000000AUL /*!< GPIO_DBCTL setting for sampling cycle = 1024 clocks */
+#define GPIO_DBCTL_DBCLKSEL_2048      0x0000000BUL /*!< GPIO_DBCTL setting for sampling cycle = 2048 clocks */
+#define GPIO_DBCTL_DBCLKSEL_4096      0x0000000CUL /*!< GPIO_DBCTL setting for sampling cycle = 4096 clocks */
+#define GPIO_DBCTL_DBCLKSEL_8192      0x0000000DUL /*!< GPIO_DBCTL setting for sampling cycle = 8192 clocks */
+#define GPIO_DBCTL_DBCLKSEL_16384     0x0000000EUL /*!< GPIO_DBCTL setting for sampling cycle = 16384 clocks */
+#define GPIO_DBCTL_DBCLKSEL_32768     0x0000000FUL /*!< GPIO_DBCTL setting for sampling cycle = 32768 clocks */
+
+
+/** Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping.
+ *  Example 1:
+ *
+ *      PA0 = 1;
+ *
+ *  It is used to set PA.0 to high;
+ *
+ *  Example 2:
+ *
+ *      if (PA0)
+ *          PA0 = 0;
+ *
+ *  If PA.0 pin status is high, then set PA.0 data output to low.
+ */
+
+
+#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT0 )
+#define PA0             PA0_NS  /*!< Specify PA.0 Pin Data Input/Output */
+#else
+#define PA0             PA0_S   /*!< Specify PA.0 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT1 )
+#define PA1             PA1_NS  /*!< Specify PA.1 Pin Data Input/Output */
+#else
+#define PA1             PA1_S   /*!< Specify PA.1 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT2 )
+#define PA2             PA2_NS  /*!< Specify PA.2 Pin Data Input/Output */
+#else
+#define PA2             PA2_S   /*!< Specify PA.2 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT3 )
+#define PA3             PA3_NS  /*!< Specify PA.3 Pin Data Input/Output */
+#else
+#define PA3             PA3_S   /*!< Specify PA.3 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT4 )
+#define PA4             PA4_NS  /*!< Specify PA.4 Pin Data Input/Output */
+#else
+#define PA4             PA4_S   /*!< Specify PA.4 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT5 )
+#define PA5             PA5_NS  /*!< Specify PA.5 Pin Data Input/Output */
+#else
+#define PA5             PA5_S   /*!< Specify PA.5 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT6 )
+#define PA6             PA6_NS  /*!< Specify PA.6 Pin Data Input/Output */
+#else
+#define PA6             PA6_S   /*!< Specify PA.6 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT7 )
+#define PA7             PA7_NS  /*!< Specify PA.7 Pin Data Input/Output */
+#else
+#define PA7             PA7_S   /*!< Specify PA.7 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT8 )
+#define PA8             PA8_NS  /*!< Specify PA.8 Pin Data Input/Output */
+#else
+#define PA8             PA8_S   /*!< Specify PA.8 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT9 )
+#define PA9             PA9_NS  /*!< Specify PA.9 Pin Data Input/Output */
+#else
+#define PA9             PA9_S   /*!< Specify PA.9 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT10 )
+#define PA10             PA10_NS  /*!< Specify PA.10 Pin Data Input/Output */
+#else
+#define PA10             PA10_S   /*!< Specify PA.10 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT11 )
+#define PA11             PA11_NS  /*!< Specify PA.11 Pin Data Input/Output */
+#else
+#define PA11             PA11_S   /*!< Specify PA.11 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT12 )
+#define PA12             PA12_NS  /*!< Specify PA.12 Pin Data Input/Output */
+#else
+#define PA12             PA12_S   /*!< Specify PA.12 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT13 )
+#define PA13             PA13_NS  /*!< Specify PA.13 Pin Data Input/Output */
+#else
+#define PA13             PA13_S   /*!< Specify PA.13 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT14 )
+#define PA14             PA14_NS  /*!< Specify PA.14 Pin Data Input/Output */
+#else
+#define PA14             PA14_S   /*!< Specify PA.14 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT15 )
+#define PA15             PA15_NS  /*!< Specify PA.15 Pin Data Input/Output */
+#else
+#define PA15             PA15_S   /*!< Specify PA.15 Pin Data Input/Output */
+#endif
+
+#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT0 )
+#define PB0              PB0_NS   /*!< Specify PB.0 Pin Data Input/Output */
+#else
+#define PB0              PB0_S    /*!< Specify PB.0 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT1 )
+#define PB1              PB1_NS   /*!< Specify PB.1 Pin Data Input/Output */
+#else
+#define PB1              PB1_S    /*!< Specify PB.1 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT2 )
+#define PB2              PB2_NS   /*!< Specify PB.2 Pin Data Input/Output */
+#else
+#define PB2              PB2_S    /*!< Specify PB.2 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT3 )
+#define PB3              PB3_NS   /*!< Specify PB.3 Pin Data Input/Output */
+#else
+#define PB3              PB3_S    /*!< Specify PB.3 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT4 )
+#define PB4              PB4_NS   /*!< Specify PB.4 Pin Data Input/Output */
+#else
+#define PB4              PB4_S    /*!< Specify PB.4 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT5 )
+#define PB5              PB5_NS   /*!< Specify PB.5 Pin Data Input/Output */
+#else
+#define PB5              PB5_S    /*!< Specify PB.5 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT6 )
+#define PB6              PB6_NS   /*!< Specify PB.6 Pin Data Input/Output */
+#else
+#define PB6              PB6_S    /*!< Specify PB.6 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT7 )
+#define PB7              PB7_NS   /*!< Specify PB.7 Pin Data Input/Output */
+#else
+#define PB7              PB7_S    /*!< Specify PB.7 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT8 )
+#define PB8              PB8_NS   /*!< Specify PB.8 Pin Data Input/Output */
+#else
+#define PB8              PB8_S    /*!< Specify PB.8 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT9 )
+#define PB9              PB9_NS   /*!< Specify PB.9 Pin Data Input/Output */
+#else
+#define PB9              PB9_S    /*!< Specify PB.9 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT10 )
+#define PB10              PB10_NS   /*!< Specify PB.10 Pin Data Input/Output */
+#else
+#define PB10              PB10_S    /*!< Specify PB.10 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT11 )
+#define PB11              PB11_NS   /*!< Specify PB.11 Pin Data Input/Output */
+#else
+#define PB11              PB11_S    /*!< Specify PB.11 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT12 )
+#define PB12              PB12_NS   /*!< Specify PB.12 Pin Data Input/Output */
+#else
+#define PB12              PB12_S    /*!< Specify PB.12 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT13 )
+#define PB13              PB13_NS   /*!< Specify PB.13 Pin Data Input/Output */
+#else
+#define PB13              PB13_S    /*!< Specify PB.13 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT14 )
+#define PB14              PB14_NS   /*!< Specify PB.14 Pin Data Input/Output */
+#else
+#define PB14              PB14_S    /*!< Specify PB.14 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT15 )
+#define PB15              PB15_NS   /*!< Specify PB.15 Pin Data Input/Output */
+#else
+#define PB15              PB15_S    /*!< Specify PB.15 Pin Data Input/Output */
+#endif
+
+#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT0 )
+#define PC0              PC0_NS   /*!< Specify PC.0 Pin Data Input/Output */
+#else
+#define PC0              PC0_S    /*!< Specify PC.0 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT1 )
+#define PC1              PC1_NS   /*!< Specify PC.1 Pin Data Input/Output */
+#else
+#define PC1              PC1_S    /*!< Specify PC.1 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT2 )
+#define PC2              PC2_NS   /*!< Specify PC.2 Pin Data Input/Output */
+#else
+#define PC2              PC2_S    /*!< Specify PC.2 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT3 )
+#define PC3              PC3_NS   /*!< Specify PC.3 Pin Data Input/Output */
+#else
+#define PC3              PC3_S    /*!< Specify PC.3 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT4 )
+#define PC4              PC4_NS   /*!< Specify PC.4 Pin Data Input/Output */
+#else
+#define PC4              PC4_S    /*!< Specify PC.4 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT5 )
+#define PC5              PC5_NS   /*!< Specify PC.5 Pin Data Input/Output */
+#else
+#define PC5              PC5_S    /*!< Specify PC.5 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT6 )
+#define PC6              PC6_NS   /*!< Specify PC.6 Pin Data Input/Output */
+#else
+#define PC6              PC6_S    /*!< Specify PC.6 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT7 )
+#define PC7              PC7_NS   /*!< Specify PC.7 Pin Data Input/Output */
+#else
+#define PC7              PC7_S    /*!< Specify PC.7 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT8 )
+#define PC8              PC8_NS   /*!< Specify PC.8 Pin Data Input/Output */
+#else
+#define PC8              PC8_S    /*!< Specify PC.8 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT9 )
+#define PC9              PC9_NS   /*!< Specify PC.9 Pin Data Input/Output */
+#else
+#define PC9              PC9_S    /*!< Specify PC.9 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT10 )
+#define PC10              PC10_NS   /*!< Specify PC.10 Pin Data Input/Output */
+#else
+#define PC10              PC10_S    /*!< Specify PC.10 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT11 )
+#define PC11              PC11_NS   /*!< Specify PC.11 Pin Data Input/Output */
+#else
+#define PC11              PC11_S    /*!< Specify PC.11 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT12 )
+#define PC12              PC12_NS   /*!< Specify PC.12 Pin Data Input/Output */
+#else
+#define PC12              PC12_S    /*!< Specify PC.12 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT13 )
+#define PC13              PC13_NS   /*!< Specify PC.13 Pin Data Input/Output */
+#else
+#define PC13              PC13_S    /*!< Specify PC.13 Pin Data Input/Output */
+#endif
+
+#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT0 )
+#define PD0              PD0_NS   /*!< Specify PD.0 Pin Data Input/Output */
+#else
+#define PD0              PD0_S    /*!< Specify PD.0 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT1 )
+#define PD1              PD1_NS   /*!< Specify PD.1 Pin Data Input/Output */
+#else
+#define PD1              PD1_S    /*!< Specify PD.1 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT2 )
+#define PD2              PD2_NS   /*!< Specify PD.2 Pin Data Input/Output */
+#else
+#define PD2              PD2_S    /*!< Specify PD.2 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT3 )
+#define PD3              PD3_NS   /*!< Specify PD.3 Pin Data Input/Output */
+#else
+#define PD3              PD3_S    /*!< Specify PD.3 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT4 )
+#define PD4              PD4_NS   /*!< Specify PD.4 Pin Data Input/Output */
+#else
+#define PD4              PD4_S    /*!< Specify PD.4 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT5 )
+#define PD5              PD5_NS   /*!< Specify PD.5 Pin Data Input/Output */
+#else
+#define PD5              PD5_S    /*!< Specify PD.5 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT6 )
+#define PD6              PD6_NS   /*!< Specify PD.6 Pin Data Input/Output */
+#else
+#define PD6              PD6_S    /*!< Specify PD.6 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT7 )
+#define PD7              PD7_NS   /*!< Specify PD.7 Pin Data Input/Output */
+#else
+#define PD7              PD7_S    /*!< Specify PD.7 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT8 )
+#define PD8              PD8_NS   /*!< Specify PD.8 Pin Data Input/Output */
+#else
+#define PD8              PD8_S    /*!< Specify PD.8 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT9 )
+#define PD9              PD9_NS   /*!< Specify PD.9 Pin Data Input/Output */
+#else
+#define PD9              PD9_S    /*!< Specify PD.9 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT10 )
+#define PD10              PD10_NS   /*!< Specify PD.10 Pin Data Input/Output */
+#else
+#define PD10              PD10_S    /*!< Specify PD.10 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT11 )
+#define PD11              PD11_NS   /*!< Specify PD.11 Pin Data Input/Output */
+#else
+#define PD11              PD11_S    /*!< Specify PD.11 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT12 )
+#define PD12              PD12_NS   /*!< Specify PD.12 Pin Data Input/Output */
+#else
+#define PD12              PD12_S    /*!< Specify PD.12 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT14 )
+#define PD14              PD14_NS   /*!< Specify PD.14 Pin Data Input/Output */
+#else
+#define PD14              PD14_S    /*!< Specify PD.14 Pin Data Input/Output */
+#endif
+
+#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT0 )
+#define PE0              PE0_NS   /*!< Specify PE.0 Pin Data Input/Output */
+#else
+#define PE0              PE0_S    /*!< Specify PE.0 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT1 )
+#define PE1              PE1_NS   /*!< Specify PE.1 Pin Data Input/Output */
+#else
+#define PE1              PE1_S    /*!< Specify PE.1 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT2 )
+#define PE2              PE2_NS   /*!< Specify PE.2 Pin Data Input/Output */
+#else
+#define PE2              PE2_S    /*!< Specify PE.2 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT3 )
+#define PE3              PE3_NS   /*!< Specify PE.3 Pin Data Input/Output */
+#else
+#define PE3              PE3_S    /*!< Specify PE.3 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT4 )
+#define PE4              PE4_NS   /*!< Specify PE.4 Pin Data Input/Output */
+#else
+#define PE4              PE4_S    /*!< Specify PE.4 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT5 )
+#define PE5              PE5_NS   /*!< Specify PE.5 Pin Data Input/Output */
+#else
+#define PE5              PE5_S    /*!< Specify PE.5 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT6 )
+#define PE6              PE6_NS   /*!< Specify PE.6 Pin Data Input/Output */
+#else
+#define PE6              PE6_S    /*!< Specify PE.6 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT7 )
+#define PE7              PE7_NS   /*!< Specify PE.7 Pin Data Input/Output */
+#else
+#define PE7              PE7_S    /*!< Specify PE.7 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT8 )
+#define PE8              PE8_NS   /*!< Specify PE.8 Pin Data Input/Output */
+#else
+#define PE8              PE8_S    /*!< Specify PE.8 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT9 )
+#define PE9              PE9_NS   /*!< Specify PE.9 Pin Data Input/Output */
+#else
+#define PE9              PE9_S    /*!< Specify PE.9 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT10 )
+#define PE10              PE10_NS   /*!< Specify PE.10 Pin Data Input/Output */
+#else
+#define PE10              PE10_S    /*!< Specify PE.10 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT11 )
+#define PE11              PE11_NS   /*!< Specify PE.11 Pin Data Input/Output */
+#else
+#define PE11              PE11_S    /*!< Specify PE.11 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT12 )
+#define PE12              PE12_NS   /*!< Specify PE.12 Pin Data Input/Output */
+#else
+#define PE12              PE12_S    /*!< Specify PE.12 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT13 )
+#define PE13              PE13_NS   /*!< Specify PE.13 Pin Data Input/Output */
+#else
+#define PE13              PE13_S    /*!< Specify PE.13 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT14 )
+#define PE14              PE14_NS   /*!< Specify PE.14 Pin Data Input/Output */
+#else
+#define PE14              PE14_S    /*!< Specify PE.14 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT15 )
+#define PE15              PE15_NS   /*!< Specify PE.15 Pin Data Input/Output */
+#else
+#define PE15              PE15_S    /*!< Specify PE.15 Pin Data Input/Output */
+#endif
+
+#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT0 )
+#define PF0              PF0_NS   /*!< Specify PF.0 Pin Data Input/Output */
+#else
+#define PF0              PF0_S    /*!< Specify PF.0 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT1 )
+#define PF1              PF1_NS   /*!< Specify PF.1 Pin Data Input/Output */
+#else
+#define PF1              PF1_S    /*!< Specify PF.1 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT2 )
+#define PF2              PF2_NS   /*!< Specify PF.2 Pin Data Input/Output */
+#else
+#define PF2              PF2_S    /*!< Specify PF.2 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT3 )
+#define PF3              PF3_NS   /*!< Specify PF.3 Pin Data Input/Output */
+#else
+#define PF3              PF3_S    /*!< Specify PF.3 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT4 )
+#define PF4              PF4_NS   /*!< Specify PF.4 Pin Data Input/Output */
+#else
+#define PF4              PF4_S    /*!< Specify PF.4 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT5 )
+#define PF5              PF5_NS   /*!< Specify PF.5 Pin Data Input/Output */
+#else
+#define PF5              PF5_S    /*!< Specify PF.5 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT6 )
+#define PF6              PF6_NS   /*!< Specify PF.6 Pin Data Input/Output */
+#else
+#define PF6              PF6_S    /*!< Specify PF.6 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT7 )
+#define PF7              PF7_NS   /*!< Specify PF.7 Pin Data Input/Output */
+#else
+#define PF7              PF7_S    /*!< Specify PF.7 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT8 )
+#define PF8              PF8_NS   /*!< Specify PF.8 Pin Data Input/Output */
+#else
+#define PF8              PF8_S    /*!< Specify PF.8 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT9 )
+#define PF9              PF9_NS   /*!< Specify PF.9 Pin Data Input/Output */
+#else
+#define PF9              PF9_S    /*!< Specify PF.9 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT10 )
+#define PF10              PF10_NS   /*!< Specify PF.10 Pin Data Input/Output */
+#else
+#define PF10              PF10_S    /*!< Specify PF.10 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT11 )
+#define PF11              PF11_NS   /*!< Specify PF.11 Pin Data Input/Output */
+#else
+#define PF11              PF11_S    /*!< Specify PF.11 Pin Data Input/Output */
+#endif
+
+#if defined (SCU_INIT_IONSSET6_VAL) && (SCU_INIT_IONSSET6_VAL & BIT2 )
+#define PG2              PG2_NS   /*!< Specify PG.2 Pin Data Input/Output */
+#else
+#define PG2              PG2_S    /*!< Specify PG.2 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET6_VAL) && (SCU_INIT_IONSSET6_VAL & BIT3 )
+#define PG3              PG3_NS   /*!< Specify PG.3 Pin Data Input/Output */
+#else
+#define PG3              PG3_S    /*!< Specify PG.3 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET6_VAL) && (SCU_INIT_IONSSET6_VAL & BIT4 )
+#define PG4              PG4_NS   /*!< Specify PG.4 Pin Data Input/Output */
+#else
+#define PG4              PG4_S    /*!< Specify PG.4 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET6_VAL) && (SCU_INIT_IONSSET6_VAL & BIT9 )
+#define PG9              PG9_NS   /*!< Specify PG.9 Pin Data Input/Output */
+#else
+#define PG9              PG9_S    /*!< Specify PG.9 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET6_VAL) && (SCU_INIT_IONSSET6_VAL & BIT10 )
+#define PG10              PG10_NS   /*!< Specify PG.10 Pin Data Input/Output */
+#else
+#define PG10              PG10_S    /*!< Specify PG.10 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET6_VAL) && (SCU_INIT_IONSSET6_VAL & BIT11 )
+#define PG11              PG11_NS   /*!< Specify PG.11 Pin Data Input/Output */
+#else
+#define PG11              PG11_S    /*!< Specify PG.11 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET6_VAL) && (SCU_INIT_IONSSET6_VAL & BIT12 )
+#define PG12              PG12_NS   /*!< Specify PG.12 Pin Data Input/Output */
+#else
+#define PG12              PG12_S    /*!< Specify PG.12 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET6_VAL) && (SCU_INIT_IONSSET6_VAL & BIT13 )
+#define PG13              PG13_NS   /*!< Specify PG.13 Pin Data Input/Output */
+#else
+#define PG13              PG13_S    /*!< Specify PG.13 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET6_VAL) && (SCU_INIT_IONSSET6_VAL & BIT14 )
+#define PG14              PG14_NS   /*!< Specify PG.14 Pin Data Input/Output */
+#else
+#define PG14              PG14_S    /*!< Specify PG.14 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET6_VAL) && (SCU_INIT_IONSSET6_VAL & BIT15 )
+#define PG15              PG15_NS   /*!< Specify PG.15 Pin Data Input/Output */
+#else
+#define PG15              PG15_S    /*!< Specify PG.15 Pin Data Input/Output */
+#endif
+
+#if defined (SCU_INIT_IONSSET7_VAL) && (SCU_INIT_IONSSET7_VAL & BIT4 )
+#define PH4              PH4_NS   /*!< Specify PH.4 Pin Data Input/Output */
+#else
+#define PH4              PH4_S    /*!< Specify PH.4 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET7_VAL) && (SCU_INIT_IONSSET7_VAL & BIT5 )
+#define PH5              PH5_NS   /*!< Specify PH.5 Pin Data Input/Output */
+#else
+#define PH5              PH5_S    /*!< Specify PH.5 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET7_VAL) && (SCU_INIT_IONSSET7_VAL & BIT6 )
+#define PH6              PH6_NS   /*!< Specify PH.6 Pin Data Input/Output */
+#else
+#define PH6              PH6_S    /*!< Specify PH.6 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET7_VAL) && (SCU_INIT_IONSSET7_VAL & BIT7 )
+#define PH7              PH7_NS   /*!< Specify PH.7 Pin Data Input/Output */
+#else
+#define PH7              PH7_S    /*!< Specify PH.7 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET7_VAL) && (SCU_INIT_IONSSET7_VAL & BIT8 )
+#define PH8              PH8_NS   /*!< Specify PH.8 Pin Data Input/Output */
+#else
+#define PH8              PH8_S    /*!< Specify PH.8 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET7_VAL) && (SCU_INIT_IONSSET7_VAL & BIT9 )
+#define PH9              PH9_NS   /*!< Specify PH.9 Pin Data Input/Output */
+#else
+#define PH9              PH9_S    /*!< Specify PH.9 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET7_VAL) && (SCU_INIT_IONSSET7_VAL & BIT10 )
+#define PH10              PH10_NS   /*!< Specify PH.10 Pin Data Input/Output */
+#else
+#define PH10              PH10_S    /*!< Specify PH.10 Pin Data Input/Output */
+#endif
+#if defined (SCU_INIT_IONSSET7_VAL) && (SCU_INIT_IONSSET7_VAL & BIT11 )
+#define PH11              PH11_NS   /*!< Specify PH.11 Pin Data Input/Output */
+#else
+#define PH11              PH11_S    /*!< Specify PH.11 Pin Data Input/Output */
+#endif
+
+
+/* GPIO bit definitions for secure */
+#define GPIO_PIN_DATA_S(port, pin)    (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2))))
+#define PA0_S            GPIO_PIN_DATA_S(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output */
+#define PA1_S            GPIO_PIN_DATA_S(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output */
+#define PA2_S            GPIO_PIN_DATA_S(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output */
+#define PA3_S            GPIO_PIN_DATA_S(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output */
+#define PA4_S            GPIO_PIN_DATA_S(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output */
+#define PA5_S            GPIO_PIN_DATA_S(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output */
+#define PA6_S            GPIO_PIN_DATA_S(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output */
+#define PA7_S            GPIO_PIN_DATA_S(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output */
+#define PA8_S            GPIO_PIN_DATA_S(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output */
+#define PA9_S            GPIO_PIN_DATA_S(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output */
+#define PA10_S           GPIO_PIN_DATA_S(0, 10) /*!< Specify PA.10 Pin Data Input/Output */
+#define PA11_S           GPIO_PIN_DATA_S(0, 11) /*!< Specify PA.11 Pin Data Input/Output */
+#define PA12_S           GPIO_PIN_DATA_S(0, 12) /*!< Specify PA.12 Pin Data Input/Output */
+#define PA13_S           GPIO_PIN_DATA_S(0, 13) /*!< Specify PA.13 Pin Data Input/Output */
+#define PA14_S           GPIO_PIN_DATA_S(0, 14) /*!< Specify PA.14 Pin Data Input/Output */
+#define PA15_S           GPIO_PIN_DATA_S(0, 15) /*!< Specify PA.15 Pin Data Input/Output */
+#define PB0_S            GPIO_PIN_DATA_S(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output */
+#define PB1_S            GPIO_PIN_DATA_S(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output */
+#define PB2_S            GPIO_PIN_DATA_S(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output */
+#define PB3_S            GPIO_PIN_DATA_S(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output */
+#define PB4_S            GPIO_PIN_DATA_S(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output */
+#define PB5_S            GPIO_PIN_DATA_S(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output */
+#define PB6_S            GPIO_PIN_DATA_S(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output */
+#define PB7_S            GPIO_PIN_DATA_S(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output */
+#define PB8_S            GPIO_PIN_DATA_S(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output */
+#define PB9_S            GPIO_PIN_DATA_S(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output */
+#define PB10_S           GPIO_PIN_DATA_S(1, 10) /*!< Specify PB.10 Pin Data Input/Output */
+#define PB11_S           GPIO_PIN_DATA_S(1, 11) /*!< Specify PB.11 Pin Data Input/Output */
+#define PB12_S           GPIO_PIN_DATA_S(1, 12) /*!< Specify PB.12 Pin Data Input/Output */
+#define PB13_S           GPIO_PIN_DATA_S(1, 13) /*!< Specify PB.13 Pin Data Input/Output */
+#define PB14_S           GPIO_PIN_DATA_S(1, 14) /*!< Specify PB.14 Pin Data Input/Output */
+#define PB15_S           GPIO_PIN_DATA_S(1, 15) /*!< Specify PB.15 Pin Data Input/Output */
+#define PC0_S            GPIO_PIN_DATA_S(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output */
+#define PC1_S            GPIO_PIN_DATA_S(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output */
+#define PC2_S            GPIO_PIN_DATA_S(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output */
+#define PC3_S            GPIO_PIN_DATA_S(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output */
+#define PC4_S            GPIO_PIN_DATA_S(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output */
+#define PC5_S            GPIO_PIN_DATA_S(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output */
+#define PC6_S            GPIO_PIN_DATA_S(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output */
+#define PC7_S            GPIO_PIN_DATA_S(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output */
+#define PC8_S            GPIO_PIN_DATA_S(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output */
+#define PC9_S            GPIO_PIN_DATA_S(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output */
+#define PC10_S           GPIO_PIN_DATA_S(2, 10) /*!< Specify PC.10 Pin Data Input/Output */
+#define PC11_S           GPIO_PIN_DATA_S(2, 11) /*!< Specify PC.11 Pin Data Input/Output */
+#define PC12_S           GPIO_PIN_DATA_S(2, 12) /*!< Specify PC.12 Pin Data Input/Output */
+#define PC13_S           GPIO_PIN_DATA_S(2, 13) /*!< Specify PC.13 Pin Data Input/Output */
+#define PD0_S            GPIO_PIN_DATA_S(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output */
+#define PD1_S            GPIO_PIN_DATA_S(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output */
+#define PD2_S            GPIO_PIN_DATA_S(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output */
+#define PD3_S            GPIO_PIN_DATA_S(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output */
+#define PD4_S            GPIO_PIN_DATA_S(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output */
+#define PD5_S            GPIO_PIN_DATA_S(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output */
+#define PD6_S            GPIO_PIN_DATA_S(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output */
+#define PD7_S            GPIO_PIN_DATA_S(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output */
+#define PD8_S            GPIO_PIN_DATA_S(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output */
+#define PD9_S            GPIO_PIN_DATA_S(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output */
+#define PD10_S           GPIO_PIN_DATA_S(3, 10) /*!< Specify PD.10 Pin Data Input/Output */
+#define PD11_S           GPIO_PIN_DATA_S(3, 11) /*!< Specify PD.11 Pin Data Input/Output */
+#define PD12_S           GPIO_PIN_DATA_S(3, 12) /*!< Specify PD.12 Pin Data Input/Output */
+#define PD14_S           GPIO_PIN_DATA_S(3, 14) /*!< Specify PD.14 Pin Data Input/Output */
+#define PE0_S            GPIO_PIN_DATA_S(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output */
+#define PE1_S            GPIO_PIN_DATA_S(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output */
+#define PE2_S            GPIO_PIN_DATA_S(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output */
+#define PE3_S            GPIO_PIN_DATA_S(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output */
+#define PE4_S            GPIO_PIN_DATA_S(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output */
+#define PE5_S            GPIO_PIN_DATA_S(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output */
+#define PE6_S            GPIO_PIN_DATA_S(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output */
+#define PE7_S            GPIO_PIN_DATA_S(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output */
+#define PE8_S            GPIO_PIN_DATA_S(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output */
+#define PE9_S            GPIO_PIN_DATA_S(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output */
+#define PE10_S           GPIO_PIN_DATA_S(4, 10) /*!< Specify PE.10 Pin Data Input/Output */
+#define PE11_S           GPIO_PIN_DATA_S(4, 11) /*!< Specify PE.11 Pin Data Input/Output */
+#define PE12_S           GPIO_PIN_DATA_S(4, 12) /*!< Specify PE.12 Pin Data Input/Output */
+#define PE13_S           GPIO_PIN_DATA_S(4, 13) /*!< Specify PE.13 Pin Data Input/Output */
+#define PE14_S           GPIO_PIN_DATA_S(4, 14) /*!< Specify PE.14 Pin Data Input/Output */
+#define PE15_S           GPIO_PIN_DATA_S(4, 15) /*!< Specify PE.15 Pin Data Input/Output */
+#define PF0_S            GPIO_PIN_DATA_S(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output */
+#define PF1_S            GPIO_PIN_DATA_S(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output */
+#define PF2_S            GPIO_PIN_DATA_S(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output */
+#define PF3_S            GPIO_PIN_DATA_S(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output */
+#define PF4_S            GPIO_PIN_DATA_S(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output */
+#define PF5_S            GPIO_PIN_DATA_S(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output */
+#define PF6_S            GPIO_PIN_DATA_S(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output */
+#define PF7_S            GPIO_PIN_DATA_S(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output */
+#define PF8_S            GPIO_PIN_DATA_S(5, 8 ) /*!< Specify PF.8 Pin Data Input/Output */
+#define PF9_S            GPIO_PIN_DATA_S(5, 9 ) /*!< Specify PF.9 Pin Data Input/Output */
+#define PF10_S           GPIO_PIN_DATA_S(5, 10) /*!< Specify PF.10 Pin Data Input/Output */
+#define PF11_S           GPIO_PIN_DATA_S(5, 11) /*!< Specify PF.11 Pin Data Input/Output */
+#define PG2_S            GPIO_PIN_DATA_S(6, 2 ) /*!< Specify PG.2 Pin Data Input/Output */
+#define PG3_S            GPIO_PIN_DATA_S(6, 3 ) /*!< Specify PG.3 Pin Data Input/Output */
+#define PG4_S            GPIO_PIN_DATA_S(6, 4 ) /*!< Specify PG.4 Pin Data Input/Output */
+#define PG9_S            GPIO_PIN_DATA_S(6, 9 ) /*!< Specify PG.9 Pin Data Input/Output */
+#define PG10_S           GPIO_PIN_DATA_S(6, 10) /*!< Specify PG.10 Pin Data Input/Output */
+#define PG11_S           GPIO_PIN_DATA_S(6, 11) /*!< Specify PG.11 Pin Data Input/Output */
+#define PG12_S           GPIO_PIN_DATA_S(6, 12) /*!< Specify PG.12 Pin Data Input/Output */
+#define PG13_S           GPIO_PIN_DATA_S(6, 13) /*!< Specify PG.13 Pin Data Input/Output */
+#define PG14_S           GPIO_PIN_DATA_S(6, 14) /*!< Specify PG.14 Pin Data Input/Output */
+#define PG15_S           GPIO_PIN_DATA_S(6, 15) /*!< Specify PG.15 Pin Data Input/Output */
+#define PH4_S            GPIO_PIN_DATA_S(7, 4 ) /*!< Specify PH.4 Pin Data Input/Output */
+#define PH5_S            GPIO_PIN_DATA_S(7, 5 ) /*!< Specify PH.5 Pin Data Input/Output */
+#define PH6_S            GPIO_PIN_DATA_S(7, 6 ) /*!< Specify PH.6 Pin Data Input/Output */
+#define PH7_S            GPIO_PIN_DATA_S(7, 7 ) /*!< Specify PH.7 Pin Data Input/Output */
+#define PH8_S            GPIO_PIN_DATA_S(7, 8 ) /*!< Specify PH.8 Pin Data Input/Output */
+#define PH9_S            GPIO_PIN_DATA_S(7, 9 ) /*!< Specify PH.9 Pin Data Input/Output */
+#define PH10_S           GPIO_PIN_DATA_S(7, 10) /*!< Specify PH.10 Pin Data Input/Output */
+#define PH11_S           GPIO_PIN_DATA_S(7, 11) /*!< Specify PH.11 Pin Data Input/Output */
+
+/* GPIO bit definitions for non-secure */
+#define GPIO_PIN_DATA_NS(port, pin)    (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+NS_OFFSET+(0x40*(port))) + ((pin)<<2))))
+#define PA0_NS            GPIO_PIN_DATA_NS(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output */
+#define PA1_NS            GPIO_PIN_DATA_NS(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output */
+#define PA2_NS            GPIO_PIN_DATA_NS(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output */
+#define PA3_NS            GPIO_PIN_DATA_NS(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output */
+#define PA4_NS            GPIO_PIN_DATA_NS(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output */
+#define PA5_NS            GPIO_PIN_DATA_NS(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output */
+#define PA6_NS            GPIO_PIN_DATA_NS(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output */
+#define PA7_NS            GPIO_PIN_DATA_NS(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output */
+#define PA8_NS            GPIO_PIN_DATA_NS(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output */
+#define PA9_NS            GPIO_PIN_DATA_NS(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output */
+#define PA10_NS           GPIO_PIN_DATA_NS(0, 10) /*!< Specify PA.10 Pin Data Input/Output */
+#define PA11_NS           GPIO_PIN_DATA_NS(0, 11) /*!< Specify PA.11 Pin Data Input/Output */
+#define PA12_NS           GPIO_PIN_DATA_NS(0, 12) /*!< Specify PA.12 Pin Data Input/Output */
+#define PA13_NS           GPIO_PIN_DATA_NS(0, 13) /*!< Specify PA.13 Pin Data Input/Output */
+#define PA14_NS           GPIO_PIN_DATA_NS(0, 14) /*!< Specify PA.14 Pin Data Input/Output */
+#define PA15_NS           GPIO_PIN_DATA_NS(0, 15) /*!< Specify PA.15 Pin Data Input/Output */
+#define PB0_NS            GPIO_PIN_DATA_NS(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output */
+#define PB1_NS            GPIO_PIN_DATA_NS(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output */
+#define PB2_NS            GPIO_PIN_DATA_NS(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output */
+#define PB3_NS            GPIO_PIN_DATA_NS(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output */
+#define PB4_NS            GPIO_PIN_DATA_NS(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output */
+#define PB5_NS            GPIO_PIN_DATA_NS(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output */
+#define PB6_NS            GPIO_PIN_DATA_NS(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output */
+#define PB7_NS            GPIO_PIN_DATA_NS(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output */
+#define PB8_NS            GPIO_PIN_DATA_NS(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output */
+#define PB9_NS            GPIO_PIN_DATA_NS(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output */
+#define PB10_NS           GPIO_PIN_DATA_NS(1, 10) /*!< Specify PB.10 Pin Data Input/Output */
+#define PB11_NS           GPIO_PIN_DATA_NS(1, 11) /*!< Specify PB.11 Pin Data Input/Output */
+#define PB12_NS           GPIO_PIN_DATA_NS(1, 12) /*!< Specify PB.12 Pin Data Input/Output */
+#define PB13_NS           GPIO_PIN_DATA_NS(1, 13) /*!< Specify PB.13 Pin Data Input/Output */
+#define PB14_NS           GPIO_PIN_DATA_NS(1, 14) /*!< Specify PB.14 Pin Data Input/Output */
+#define PB15_NS           GPIO_PIN_DATA_NS(1, 15) /*!< Specify PB.15 Pin Data Input/Output */
+#define PC0_NS            GPIO_PIN_DATA_NS(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output */
+#define PC1_NS            GPIO_PIN_DATA_NS(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output */
+#define PC2_NS            GPIO_PIN_DATA_NS(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output */
+#define PC3_NS            GPIO_PIN_DATA_NS(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output */
+#define PC4_NS            GPIO_PIN_DATA_NS(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output */
+#define PC5_NS            GPIO_PIN_DATA_NS(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output */
+#define PC6_NS            GPIO_PIN_DATA_NS(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output */
+#define PC7_NS            GPIO_PIN_DATA_NS(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output */
+#define PC8_NS            GPIO_PIN_DATA_NS(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output */
+#define PC9_NS            GPIO_PIN_DATA_NS(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output */
+#define PC10_NS           GPIO_PIN_DATA_NS(2, 10) /*!< Specify PC.10 Pin Data Input/Output */
+#define PC11_NS           GPIO_PIN_DATA_NS(2, 11) /*!< Specify PC.11 Pin Data Input/Output */
+#define PC12_NS           GPIO_PIN_DATA_NS(2, 12) /*!< Specify PC.12 Pin Data Input/Output */
+#define PC13_NS           GPIO_PIN_DATA_NS(2, 13) /*!< Specify PC.13 Pin Data Input/Output */
+#define PD0_NS            GPIO_PIN_DATA_NS(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output */
+#define PD1_NS            GPIO_PIN_DATA_NS(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output */
+#define PD2_NS            GPIO_PIN_DATA_NS(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output */
+#define PD3_NS            GPIO_PIN_DATA_NS(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output */
+#define PD4_NS            GPIO_PIN_DATA_NS(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output */
+#define PD5_NS            GPIO_PIN_DATA_NS(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output */
+#define PD6_NS            GPIO_PIN_DATA_NS(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output */
+#define PD7_NS            GPIO_PIN_DATA_NS(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output */
+#define PD8_NS            GPIO_PIN_DATA_NS(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output */
+#define PD9_NS            GPIO_PIN_DATA_NS(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output */
+#define PD10_NS           GPIO_PIN_DATA_NS(3, 10) /*!< Specify PD.10 Pin Data Input/Output */
+#define PD11_NS           GPIO_PIN_DATA_NS(3, 11) /*!< Specify PD.11 Pin Data Input/Output */
+#define PD12_NS           GPIO_PIN_DATA_NS(3, 12) /*!< Specify PD.12 Pin Data Input/Output */
+#define PD14_NS           GPIO_PIN_DATA_NS(3, 14) /*!< Specify PD.14 Pin Data Input/Output */
+#define PE0_NS            GPIO_PIN_DATA_NS(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output */
+#define PE1_NS            GPIO_PIN_DATA_NS(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output */
+#define PE2_NS            GPIO_PIN_DATA_NS(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output */
+#define PE3_NS            GPIO_PIN_DATA_NS(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output */
+#define PE4_NS            GPIO_PIN_DATA_NS(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output */
+#define PE5_NS            GPIO_PIN_DATA_NS(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output */
+#define PE6_NS            GPIO_PIN_DATA_NS(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output */
+#define PE7_NS            GPIO_PIN_DATA_NS(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output */
+#define PE8_NS            GPIO_PIN_DATA_NS(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output */
+#define PE9_NS            GPIO_PIN_DATA_NS(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output */
+#define PE10_NS           GPIO_PIN_DATA_NS(4, 10) /*!< Specify PE.10 Pin Data Input/Output */
+#define PE11_NS           GPIO_PIN_DATA_NS(4, 11) /*!< Specify PE.11 Pin Data Input/Output */
+#define PE12_NS           GPIO_PIN_DATA_NS(4, 12) /*!< Specify PE.12 Pin Data Input/Output */
+#define PE13_NS           GPIO_PIN_DATA_NS(4, 13) /*!< Specify PE.13 Pin Data Input/Output */
+#define PE14_NS           GPIO_PIN_DATA_NS(4, 14) /*!< Specify PE.14 Pin Data Input/Output */
+#define PE15_NS           GPIO_PIN_DATA_NS(4, 15) /*!< Specify PE.15 Pin Data Input/Output */
+#define PF0_NS            GPIO_PIN_DATA_NS(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output */
+#define PF1_NS            GPIO_PIN_DATA_NS(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output */
+#define PF2_NS            GPIO_PIN_DATA_NS(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output */
+#define PF3_NS            GPIO_PIN_DATA_NS(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output */
+#define PF4_NS            GPIO_PIN_DATA_NS(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output */
+#define PF5_NS            GPIO_PIN_DATA_NS(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output */
+#define PF6_NS            GPIO_PIN_DATA_NS(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output */
+#define PF7_NS            GPIO_PIN_DATA_NS(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output */
+#define PF8_NS            GPIO_PIN_DATA_NS(5, 8 ) /*!< Specify PF.8 Pin Data Input/Output */
+#define PF9_NS            GPIO_PIN_DATA_NS(5, 9 ) /*!< Specify PF.9 Pin Data Input/Output */
+#define PF10_NS           GPIO_PIN_DATA_NS(5, 10) /*!< Specify PF.10 Pin Data Input/Output */
+#define PF11_NS           GPIO_PIN_DATA_NS(5, 11) /*!< Specify PF.11 Pin Data Input/Output */
+#define PG2_NS            GPIO_PIN_DATA_NS(6, 2 ) /*!< Specify PG.2 Pin Data Input/Output */
+#define PG3_NS            GPIO_PIN_DATA_NS(6, 3 ) /*!< Specify PG.3 Pin Data Input/Output */
+#define PG4_NS            GPIO_PIN_DATA_NS(6, 4 ) /*!< Specify PG.4 Pin Data Input/Output */
+#define PG9_NS            GPIO_PIN_DATA_NS(6, 9 ) /*!< Specify PG.9 Pin Data Input/Output */
+#define PG10_NS           GPIO_PIN_DATA_NS(6, 10) /*!< Specify PG.10 Pin Data Input/Output */
+#define PG11_NS           GPIO_PIN_DATA_NS(6, 11) /*!< Specify PG.11 Pin Data Input/Output */
+#define PG12_NS           GPIO_PIN_DATA_NS(6, 12) /*!< Specify PG.12 Pin Data Input/Output */
+#define PG13_NS           GPIO_PIN_DATA_NS(6, 13) /*!< Specify PG.13 Pin Data Input/Output */
+#define PG14_NS           GPIO_PIN_DATA_NS(6, 14) /*!< Specify PG.14 Pin Data Input/Output */
+#define PG15_NS           GPIO_PIN_DATA_NS(6, 15) /*!< Specify PG.15 Pin Data Input/Output */
+#define PH4_NS            GPIO_PIN_DATA_NS(7, 4 ) /*!< Specify PH.4 Pin Data Input/Output */
+#define PH5_NS            GPIO_PIN_DATA_NS(7, 5 ) /*!< Specify PH.5 Pin Data Input/Output */
+#define PH6_NS            GPIO_PIN_DATA_NS(7, 6 ) /*!< Specify PH.6 Pin Data Input/Output */
+#define PH7_NS            GPIO_PIN_DATA_NS(7, 7 ) /*!< Specify PH.7 Pin Data Input/Output */
+#define PH8_NS            GPIO_PIN_DATA_NS(7, 8 ) /*!< Specify PH.8 Pin Data Input/Output */
+#define PH9_NS            GPIO_PIN_DATA_NS(7, 9 ) /*!< Specify PH.9 Pin Data Input/Output */
+#define PH10_NS           GPIO_PIN_DATA_NS(7, 10) /*!< Specify PH.10 Pin Data Input/Output */
+#define PH11_NS           GPIO_PIN_DATA_NS(7, 11) /*!< Specify PH.11 Pin Data Input/Output */
+
+
+/**@}*/ /* end of group GPIO_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
+  @{
+*/
+
+/**
+ * @brief       Clear GPIO Pin Interrupt Flag
+ *
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port. \n
+ *                          It could be BIT0 ~ BIT15 for PA, PB and PE. \n
+ *                          It could be BIT0 ~ BIT13 for PC. \n
+ *                          It could be BIT0 ~ BIT12, BIT14 for PD. \n
+ *                          It could be BIT0 ~ BIT11 for PF. \n
+ *                          It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n
+ *                          It could be BIT4 ~ BIT11 for PH.
+ *
+ * @return      None
+ *
+ * @details     Clear the interrupt status of specified GPIO pin.
+ */
+#define GPIO_CLR_INT_FLAG(port, u32PinMask)         ((port)->INTSRC = (u32PinMask))
+
+/**
+ * @brief       Disable Pin De-bounce Function
+ *
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port. \n
+ *                          It could be BIT0 ~ BIT15 for PA, PB and PE. \n
+ *                          It could be BIT0 ~ BIT13 for PC. \n
+ *                          It could be BIT0 ~ BIT12, BIT14 for PD. \n
+ *                          It could be BIT0 ~ BIT11 for PF. \n
+ *                          It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n
+ *                          It could be BIT4 ~ BIT11 for PH.
+ *
+ * @return      None
+ *
+ * @details     Disable the interrupt de-bounce function of specified GPIO pin.
+ */
+#define GPIO_DISABLE_DEBOUNCE(port, u32PinMask)     ((port)->DBEN &= ~(u32PinMask))
+
+/**
+ * @brief       Enable Pin De-bounce Function
+ *
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port. \n
+ *                          It could be BIT0 ~ BIT15 for PA, PB and PE. \n
+ *                          It could be BIT0 ~ BIT13 for PC. \n
+ *                          It could be BIT0 ~ BIT12, BIT14 for PD. \n
+ *                          It could be BIT0 ~ BIT11 for PF. \n
+ *                          It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n
+ *                          It could be BIT4 ~ BIT11 for PH.
+ * @return      None
+ *
+ * @details     Enable the interrupt de-bounce function of specified GPIO pin.
+ */
+#define GPIO_ENABLE_DEBOUNCE(port, u32PinMask)      ((port)->DBEN |= (u32PinMask))
+
+/**
+ * @brief       Disable I/O Digital Input Path
+ *
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port. \n
+ *                          It could be BIT0 ~ BIT15 for PA, PB and PE. \n
+ *                          It could be BIT0 ~ BIT13 for PC. \n
+ *                          It could be BIT0 ~ BIT12, BIT14 for PD. \n
+ *                          It could be BIT0 ~ BIT11 for PF. \n
+ *                          It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n
+ *                          It could be BIT4 ~ BIT11 for PH.
+ *
+ * @return      None
+ *
+ * @details     Disable I/O digital input path of specified GPIO pin.
+ */
+#define GPIO_DISABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF |= ((u32PinMask)<<16))
+
+/**
+ * @brief       Enable I/O Digital Input Path
+ *
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port. \n
+ *                          It could be BIT0 ~ BIT15 for PA, PB and PE. \n
+ *                          It could be BIT0 ~ BIT13 for PC. \n
+ *                          It could be BIT0 ~ BIT12, BIT14 for PD. \n
+ *                          It could be BIT0 ~ BIT11 for PF. \n
+ *                          It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n
+ *                          It could be BIT4 ~ BIT11 for PH.
+ *
+ * @return      None
+ *
+ * @details     Enable I/O digital input path of specified GPIO pin.
+ */
+#define GPIO_ENABLE_DIGITAL_PATH(port, u32PinMask)  ((port)->DINOFF &= ~((u32PinMask)<<16))
+
+/**
+ * @brief       Disable I/O DOUT mask
+ *
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port. \n
+ *                          It could be BIT0 ~ BIT15 for PA, PB and PE. \n
+ *                          It could be BIT0 ~ BIT13 for PC. \n
+ *                          It could be BIT0 ~ BIT12, BIT14 for PD. \n
+ *                          It could be BIT0 ~ BIT11 for PF. \n
+ *                          It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n
+ *                          It could be BIT4 ~ BIT11 for PH.
+ *
+ * @return      None
+ *
+ * @details     Disable I/O DOUT mask of specified GPIO pin.
+ */
+#define GPIO_DISABLE_DOUT_MASK(port, u32PinMask)    ((port)->DATMSK &= ~(u32PinMask))
+
+/**
+ * @brief       Enable I/O DOUT mask
+ *
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port. \n
+ *                          It could be BIT0 ~ BIT15 for PA, PB and PE. \n
+ *                          It could be BIT0 ~ BIT13 for PC. \n
+ *                          It could be BIT0 ~ BIT12, BIT14 for PD. \n
+ *                          It could be BIT0 ~ BIT11 for PF. \n
+ *                          It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n
+ *                          It could be BIT4 ~ BIT11 for PH.
+ *
+ * @return      None
+ *
+ * @details     Enable I/O DOUT mask of specified GPIO pin.
+ */
+#define GPIO_ENABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK |= (u32PinMask))
+
+/**
+ * @brief       Get GPIO Pin Interrupt Flag
+ *
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port. \n
+ *                          It could be BIT0 ~ BIT15 for PA, PB and PE. \n
+ *                          It could be BIT0 ~ BIT13 for PC. \n
+ *                          It could be BIT0 ~ BIT12, BIT14 for PD. \n
+ *                          It could be BIT0 ~ BIT11 for PF. \n
+ *                          It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n
+ *                          It could be BIT4 ~ BIT11 for PH.
+ *
+ * @retval      0           No interrupt at specified GPIO pin
+ * @retval      1           The specified GPIO pin generate an interrupt
+ *
+ * @details     Get the interrupt status of specified GPIO pin.
+ */
+#define GPIO_GET_INT_FLAG(port, u32PinMask)     ((port)->INTSRC & (u32PinMask))
+
+/**
+ * @brief       Set De-bounce Sampling Cycle Time
+ *
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32ClkSrc   The de-bounce counter clock source. It could be GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC.
+ * @param[in]   u32ClkSel   The de-bounce sampling cycle selection. It could be
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_1
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_2
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_4
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_8
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_16
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_32
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_64
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_128
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_256
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_512
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_1024
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_2048
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_4096
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_8192
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_16384
+ *                            - \ref GPIO_DBCTL_DBCLKSEL_32768
+ *
+ * @return      None
+ *
+ * @details     Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n
+ *              Example: _GPIO_SET_DEBOUNCE_TIME(PA, GPIO_DBCTL_DBCLKSRC_LIRC, GPIO_DBCTL_DBCLKSEL_4). \n
+ *              It's meaning the De-debounce counter clock source is internal 10 KHz and sampling cycle selection is 4. \n
+ *              Then the target de-bounce sampling cycle time is (4)*(1/(10*1000)) s = 4*0.0001 s = 400 us,
+ *              and system will sampling interrupt input once per 400 us.
+ */
+#define GPIO_SET_DEBOUNCE_TIME(port, u32ClkSrc, u32ClkSel)    ((port)->DBCTL = (GPIO_DBCTL_ICLKON_Msk | (u32ClkSrc) | (u32ClkSel)))
+
+/**
+ * @brief       Get GPIO Port IN Data
+ *
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ *
+ * @return      The specified port data
+ *
+ * @details     Get the PIN register of specified GPIO port.
+ */
+#define GPIO_GET_IN_DATA(port)  ((port)->PIN)
+
+/**
+ * @brief       Set GPIO Port OUT Data
+ *
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32Data     GPIO port data.
+ *
+ * @return      None
+ *
+ * @details     Set the Data into specified GPIO port.
+ */
+#define GPIO_SET_OUT_DATA(port, u32Data)    ((port)->DOUT = (u32Data))
+
+/**
+ * @brief       Toggle Specified GPIO pin
+ *
+ * @param[in]   u32Pin      Pxy
+ *
+ * @return      None
+ *
+ * @details     Toggle the specified GPIO pint.
+ */
+#define GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1)
+
+
+/**
+ * @brief       Enable External GPIO interrupt
+ *
+ * @param[in]   port            GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32Pin          The pin of specified GPIO port. \n
+ *                              It could be 0 ~ 15 for PA, PB and PE. \n
+ *                              It could be 0 ~ 13 for PC GPIO port. \n
+ *                              It could be 0 ~ 12, 14 for PD GPIO port. \n
+ *                              It could be 0 ~ 11 for PF GPIO port. \n
+ *                              It could be 2 ~ 4, 9 ~ 15 for PG GPIO port. \n
+ *                              It could be 4 ~ 11 for PH GPIO port.
+ * @param[in]   u32IntAttribs   The interrupt attribute of specified GPIO pin. It could be
+ *                              - \ref GPIO_INT_RISING
+ *                              - \ref GPIO_INT_FALLING
+ *                              - \ref GPIO_INT_BOTH_EDGE
+ *                              - \ref GPIO_INT_HIGH
+ *                              - \ref GPIO_INT_LOW
+ *
+ * @return      None
+ *
+ * @details     This function is used to enable specified GPIO pin interrupt.
+ */
+#define GPIO_EnableEINT     GPIO_EnableInt
+
+/**
+ * @brief       Disable External GPIO interrupt
+ *
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32Pin      The pin of specified GPIO port. \n
+ *                          It could be 0 ~ 15 for PA, PB and PE. \n
+ *                          It could be 0 ~ 13 for PC GPIO port. \n
+ *                          It could be 0 ~ 12, 14 for PD GPIO port. \n
+ *                          It could be 0 ~ 11 for PF GPIO port. \n
+ *                          It could be 2 ~ 4, 9 ~ 15 for PG GPIO port. \n
+ *                          It could be 4 ~ 11 for PH GPIO port.
+ *
+ * @return      None
+ *
+ * @details     This function is used to enable specified GPIO pin interrupt.
+ */
+#define GPIO_DisableEINT    GPIO_DisableInt
+
+
+void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);
+void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs);
+void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin);
+void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);
+void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);
+
+
+/**@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group GPIO_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_GPIO_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_i2c.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_i2c.h
new file mode 100644
index 0000000000..4ea5a45748
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_i2c.h
@@ -0,0 +1,523 @@
+/**************************************************************************//**
+ * @file     nu_i2c.h
+ * @version  V3.0
+ * $Revision: 1 $
+ * $Date: 16/07/07 7:50p $
+ * @brief    M2355 series I2C Serial Interface Controller(I2C) driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __NU_I2C_H__
+#define __NU_I2C_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup I2C_Driver I2C Driver
+  @{
+*/
+
+/** @addtogroup I2C_EXPORTED_CONSTANTS I2C Exported Constants
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  I2C_CTL constant definitions.                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define I2C_CTL_STA_SI            (0x28U) /*!< I2C_CTL setting for I2C control bits. It would set STA and SI bits          */
+#define I2C_CTL_STA_SI_AA         (0x2CU) /*!< I2C_CTL setting for I2C control bits. It would set STA, SI and AA bits      */
+#define I2C_CTL_STO_SI            (0x18U) /*!< I2C_CTL setting for I2C control bits. It would set STO and SI bits          */
+#define I2C_CTL_STO_SI_AA         (0x1CU) /*!< I2C_CTL setting for I2C control bits. It would set STO, SI and AA bits      */
+#define I2C_CTL_SI                (0x08U) /*!< I2C_CTL setting for I2C control bits. It would set SI bit                   */
+#define I2C_CTL_SI_AA             (0x0CU) /*!< I2C_CTL setting for I2C control bits. It would set SI and AA bits           */
+#define I2C_CTL_STA               (0x20U) /*!< I2C_CTL setting for I2C control bits. It would set STA bit                  */
+#define I2C_CTL_STO               (0x10U) /*!< I2C_CTL setting for I2C control bits. It would set STO bit                  */
+#define I2C_CTL_AA                (0x04U) /*!< I2C_CTL setting for I2C control bits. It would set AA bit                   */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  I2C GCMode constant definitions.                                                                       */
+/*---------------------------------------------------------------------------------------------------------*/
+#define I2C_GCMODE_ENABLE           (1U)    /*!< Enable  I2C GC Mode                                                         */
+#define I2C_GCMODE_DISABLE          (0U)    /*!< Disable I2C GC Mode                                                         */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  I2C SMBUS constant definitions.                                                                        */
+/*---------------------------------------------------------------------------------------------------------*/
+#define I2C_SMBH_ENABLE             (1U)    /*!< Enable  SMBus Host Mode enable                                              */
+#define I2C_SMBD_ENABLE             (0U)    /*!< Enable  SMBus Device Mode enable                                            */
+#define I2C_PECTX_ENABLE            (1U)    /*!< Enable  SMBus Packet Error Check Transmit function                          */
+#define I2C_PECTX_DISABLE           (0U)    /*!< Disable SMBus Packet Error Check Transmit function                          */
+
+/**@}*/ /* end of group I2C_EXPORTED_CONSTANTS */
+
+/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions
+  @{
+*/
+/**
+ *    @brief        The macro is used to set I2C bus condition at One Time
+ *
+ *    @param[in]    i2c        Specify I2C port
+ *    @param[in]    u8Ctrl     A byte writes to I2C control register
+ *
+ *    @return       None
+ *
+ *    @details      Set I2C_CTL register to control I2C bus conditions of START, STOP, SI, ACK.
+ */
+#define I2C_SET_CONTROL_REG(i2c, u8Ctrl) ((i2c)->CTL0 = ((i2c)->CTL0 & ~0x3Cu) | (u8Ctrl))
+
+/**
+ *    @brief        The macro is used to set START condition of I2C Bus
+ *
+ *    @param[in]    i2c        Specify I2C port
+ *
+ *    @return       None
+ *
+ *    @details      Set the I2C bus START condition in I2C_CTL register.
+ */
+#define I2C_START(i2c)  ((i2c)->CTL0 = ((i2c)->CTL0 | I2C_CTL0_SI_Msk) | I2C_CTL0_STA_Msk)
+
+/**
+ *    @brief        The macro is used to wait I2C bus status get ready
+ *
+ *    @param[in]    i2c        Specify I2C port
+ *
+ *    @return       None
+ *
+ *    @details      When a new status is presented of I2C bus, the SI flag will be set in I2C_CTL register.
+ */
+#define I2C_WAIT_READY(i2c)     while(!((i2c)->CTL0 & I2C_CTL0_SI_Msk))
+
+/**
+ *    @brief        The macro is used to Read I2C Bus Data Register
+ *
+ *    @param[in]    i2c        Specify I2C port
+ *
+ *    @return       A byte of I2C data register
+ *
+ *    @details      I2C controller read data from bus and save it in I2CDAT register.
+ */
+#define I2C_GET_DATA(i2c)   ((i2c)->DAT)
+
+/**
+ *    @brief        Write a Data to I2C Data Register
+ *
+ *    @param[in]    i2c         Specify I2C port
+ *    @param[in]    u8Data      A byte that writes to data register
+ *
+ *    @return       None
+ *
+ *    @details      When write a data to I2C_DAT register, the I2C controller will shift it to I2C bus.
+ */
+#define I2C_SET_DATA(i2c, u8Data) ((i2c)->DAT = (u8Data))
+
+/**
+ *    @brief        Get I2C Bus status code
+ *
+ *    @param[in]    i2c        Specify I2C port
+ *
+ *    @return       I2C status code
+ *
+ *    @details      To get this status code to monitor I2C bus event.
+ */
+#define I2C_GET_STATUS(i2c) ((i2c)->STATUS0)
+
+/**
+ *    @brief        Get Time-out flag from I2C Bus
+ *
+ *    @param[in]    i2c     Specify I2C port
+ *
+ *    @retval       0       I2C Bus time-out is not happened
+ *    @retval       1       I2C Bus time-out is happened
+ *
+ *    @details      When I2C bus occurs time-out event, the time-out flag will be set.
+ */
+#define I2C_GET_TIMEOUT_FLAG(i2c)   ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1u : 0u)
+
+/**
+ *    @brief        To get wake-up flag from I2C Bus
+ *
+ *    @param[in]    i2c     Specify I2C port
+ *
+ *    @retval       0       Chip is not woken-up from power-down mode
+ *    @retval       1       Chip is woken-up from power-down mode
+ *
+ *    @details      I2C bus occurs wake-up event, wake-up flag will be set.
+ */
+#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKIF_Msk) == I2C_WKSTS_WKIF_Msk ? 1u : 0u)
+
+/**
+ *    @brief        To clear wake-up flag
+ *
+ *    @param[in]    i2c     Specify I2C port
+ *
+ *    @return       None
+ *
+ *    @details      If wake-up flag is set, use this macro to clear it.
+ */
+#define I2C_CLEAR_WAKEUP_FLAG(i2c)  ((i2c)->WKSTS = I2C_WKSTS_WKIF_Msk)
+
+/**
+ *    @brief        To get wake-up address frame ACK done flag from I2C Bus
+ *
+ *    @param[in]    i2c     Specify I2C port
+ *
+ *    @retval       0       The ACK bit cycle of address match frame is not done
+ *    @retval       1       The ACK bit cycle of address match frame is done in power-down
+ *
+ *    @details      I2C bus occurs wake-up event and address frame ACK is done, this flag will be set.
+ *
+ *    \hideinitializer
+ */
+#define I2C_GET_WAKEUP_DONE(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKAKDONE_Msk) == I2C_WKSTS_WKAKDONE_Msk ? 1u : 0u)
+
+/**
+ *    @brief        To clear address frame ACK done flag
+ *
+ *    @param[in]    i2c     Specify I2C port
+ *
+ *    @return       None
+ *
+ *    @details      If wake-up done is set, use this macro to clear it.
+ *
+ *    \hideinitializer
+ */
+#define I2C_CLEAR_WAKEUP_DONE(i2c)  ((i2c)->WKSTS = I2C_WKSTS_WKAKDONE_Msk)
+
+/**
+ *    @brief        To get read/write status bit in address wakeup frame
+ *
+ *    @param[in]    i2c     Specify I2C port
+ *
+ *    @retval       0       Write command be record on the address match wakeup frame
+ *    @retval       1       Read command be record on the address match wakeup frame.
+ *
+ *    @details      I2C bus occurs wake-up event and address frame is received, this bit will record read/write status.
+ *
+ *    \hideinitializer
+*/
+#define I2C_GET_WAKEUP_WR_STATUS(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WRSTSWK_Msk) == I2C_WKSTS_WRSTSWK_Msk ? 1u : 0u)
+
+/**
+ * @brief      To get SMBus Status
+ *
+ * @param[in]  i2c          Specify I2C port
+ *
+ * @return     SMBus status
+ *
+ * @details    To get the Bus Management status of I2C_BUSSTS register
+ *
+ */
+#define I2C_SMBUS_GET_STATUS(i2c) ((i2c)->BUSSTS)
+
+/**
+ * @brief      Get SMBus CRC value
+ *
+ * @param[in]  i2c          Specify I2C port
+ *
+ * @return     Packet error check byte value
+ *
+ * @details    The CRC check value after a transmission or a reception by count by using CRC8
+ *
+ */
+#define I2C_SMBUS_GET_PEC_VALUE(i2c) ((i2c)->PKTCRC)
+
+/**
+ * @brief      Set SMBus Bytes number of Transmission or reception
+ *
+ * @param[in]  i2c              Specify I2C port
+ * @param[in]  u32PktSize       Transmit / Receive bytes
+ *
+ * @return     None
+ *
+ * @details    The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes.
+ *
+ */
+#define I2C_SMBUS_SET_PACKET_BYTE_COUNT(i2c, u32PktSize) ((i2c)->PKTSIZE = (u32PktSize))
+
+/**
+ * @brief      Enable SMBus Alert function
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin will pull lo, and reply ACK when get ARP from host
+ *             Host   Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin is supported to receive alert state(Lo trigger)
+ *
+ */
+#define I2C_SMBUS_ENABLE_ALERT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ALERTEN_Msk)
+
+/**
+ * @brief      Disable SMBus Alert pin function
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin will pull hi, and reply NACK when get ARP from host
+ *             Host   Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin is not supported to receive alert state(Lo trigger)
+ *
+ */
+#define I2C_SMBUS_DISABLE_ALERT(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ALERTEN_Msk)
+
+/**
+ * @brief      Set SMBus SUSCON pin is output mode
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    This function to set SUSCON(I2C_BUSCTL[6]) pin is output mode.
+ *
+ *
+ */
+#define I2C_SMBUS_SET_SUSCON_OUT(i2c)   ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOEN_Msk)
+
+/**
+ * @brief      Set SMBus SUSCON pin is input mode
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    This function to set SUSCON(I2C_BUSCTL[6]) pin is input mode.
+ *
+ *
+ */
+#define I2C_SMBUS_SET_SUSCON_IN(i2c)   ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOEN_Msk)
+
+/**
+ * @brief      Set SMBus SUSCON pin output high state
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    This function to set SUSCON(I2C_BUSCTL[6]) pin is output hi state.
+ *
+ */
+#define I2C_SMBUS_SET_SUSCON_HIGH(i2c)   ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOSTS_Msk)
+
+
+/**
+ * @brief      Set SMBus SUSCON pin output low state
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    This function to set SUSCON(I2C_BUSCTL[6]) pin is output lo state.
+ *
+ */
+#define I2C_SMBUS_SET_SUSCON_LOW(i2c)   ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOSTS_Msk)
+
+/**
+ * @brief      Enable SMBus Acknowledge control by manual
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, SCLK line stretching to low between the 8th and 9th SCLK pulse.
+ *
+ */
+#define I2C_SMBUS_ACK_MANUAL(i2c)   ((i2c)->BUSCTL |= I2C_BUSCTL_ACKMEN_Msk)
+
+/**
+ * @brief      Disable SMBus Acknowledge control by manual
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    Disable acknowledge response control by user.
+ *
+ */
+#define I2C_SMBUS_ACK_AUTO(i2c)   ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKMEN_Msk)
+
+/**
+ * @brief      Enable SMBus Acknowledge manual interrupt
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    This function is used to enable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1
+ *
+ */
+#define I2C_SMBUS_9THBIT_INT_ENABLE(i2c)   ((i2c)->BUSCTL |= I2C_BUSCTL_ACKM9SI_Msk)
+
+/**
+ * @brief      Disable SMBus Acknowledge manual interrupt
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    This function is used to disable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1
+ *
+ */
+#define I2C_SMBUS_9THBIT_INT_DISABLE(i2c)   ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKM9SI_Msk)
+
+/**
+ * @brief      Enable SMBus PEC clear at REPEAT START
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    This function is used to enable the condition of REAEAT START can clear the PEC calculation.
+ *
+ */
+#define I2C_SMBUS_RST_PEC_AT_START_ENABLE(i2c)   ((i2c)->BUSCTL |= I2C_BUSCTL_PECCLR_Msk)
+
+/**
+ * @brief      Disable SMBus PEC clear at Repeat START
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    This function is used to disable the condition of Repeat START can clear the PEC calculation.
+ *
+ */
+#define I2C_SMBUS_RST_PEC_AT_START_DISABLE(i2c)   ((i2c)->BUSCTL &= ~I2C_BUSCTL_PECCLR_Msk)
+
+/**
+  * @brief      Enable RX PDMA function.
+  * @param[in]  i2c The pointer of the specified I2C module.
+  * @return     None.
+  * @details    Set RXPDMAEN bit of I2C_CTL1 register to enable RX PDMA transfer function.
+  */
+#define I2C_ENABLE_RX_PDMA(i2c)   ((i2c)->CTL1 |= I2C_CTL1_RXPDMAEN_Msk)
+
+/**
+  * @brief      Enable TX PDMA function.
+  * @param[in]  i2c The pointer of the specified I2C module.
+  * @return     None.
+  * @details    Set TXPDMAEN bit of I2C_CTL1 register to enable TX PDMA transfer function.
+  */
+#define I2C_ENABLE_TX_PDMA(i2c)   ((i2c)->CTL1 |= I2C_CTL1_TXPDMAEN_Msk)
+
+/**
+  * @brief      Disable RX PDMA transfer.
+  * @param[in]  i2c The pointer of the specified I2C module.
+  * @return     None.
+  * @details    Clear RXPDMAEN bit of I2C_CTL1 register to disable RX PDMA transfer function.
+  */
+#define I2C_DISABLE_RX_PDMA(i2c)   ((i2c)->CTL1 &= ~I2C_CTL1_RXPDMAEN_Msk)
+
+/**
+  * @brief      Disable TX PDMA transfer.
+  * @param[in]  i2c The pointer of the specified I2C module.
+  * @return     None.
+  * @details    Clear TXPDMAEN bit of I2C_CTL1 register to disable TX PDMA transfer function.
+  */
+#define I2C_DISABLE_TX_PDMA(i2c)   ((i2c)->CTL1 &= ~I2C_CTL1_TXPDMAEN_Msk)
+
+/**
+  * @brief      Enable PDMA stretch function.
+  * @param[in]  i2c The pointer of the specified I2C module.
+  * @return     None.
+  * @details    Enable this function is to stretch bus by hardware after PDMA transfer is done if SI is not cleared.
+  */
+#define I2C_ENABLE_PDMA_STRETCH(i2c)   ((i2c)->CTL1 |= I2C_CTL1_PDMASTR_Msk)
+
+/**
+  * @brief      Disable PDMA stretch function.
+  * @param[in]  i2c The pointer of the specified I2C module.
+  * @return     None.
+  * @details    I2C wil send STOP after PDMA transfers done automatically.
+  */
+#define I2C_DISABLE_PDMA_STRETCH(i2c)   ((i2c)->CTL1 &= ~I2C_CTL1_PDMASTR_Msk)
+
+/**
+  * @brief      Reset PDMA function.
+  * @param[in]  i2c The pointer of the specified I2C module.
+  * @return     None.
+  * @details    I2C PDMA engine will be reset after this function is called.
+  */
+#define I2C_DISABLE_RST_PDMA(i2c)   ((i2c)->CTL1 |= I2C_CTL1_PDMARST_Msk)
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* inline functions                                                                                        */
+/*---------------------------------------------------------------------------------------------------------*/
+static __INLINE void I2C_STOP(I2C_T *i2c);
+
+/**
+ *    @brief        The macro is used to set STOP condition of I2C Bus
+ *
+ *    @param[in]    i2c        Specify I2C port
+ *
+ *    @return       None
+ *
+ *    @details      Set the I2C bus STOP condition in I2C_CTL register.
+ */
+static __INLINE void I2C_STOP(I2C_T *i2c)
+{
+
+    (i2c)->CTL0 |= (I2C_CTL0_SI_Msk | I2C_CTL0_STO_Msk);
+    while(i2c->CTL0 & I2C_CTL0_STO_Msk) {}
+}
+
+
+void I2C_ClearTimeoutFlag(I2C_T *i2c);
+void I2C_Close(I2C_T *i2c);
+void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack);
+void I2C_DisableInt(I2C_T *i2c);
+void I2C_EnableInt(I2C_T *i2c);
+uint32_t I2C_GetBusClockFreq(I2C_T *i2c);
+uint32_t I2C_GetIntFlag(I2C_T *i2c);
+uint32_t I2C_GetStatus(I2C_T *i2c);
+uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock);
+uint8_t I2C_GetData(I2C_T *i2c);
+void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode);
+void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask);
+uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock);
+void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout);
+void I2C_DisableTimeout(I2C_T *i2c);
+void I2C_EnableWakeup(I2C_T *i2c);
+void I2C_DisableWakeup(I2C_T *i2c);
+void I2C_SetData(I2C_T *i2c, uint8_t u8Data);
+uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8Data);
+uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t au8Data[], uint32_t u32wLen);
+uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t u8Data);
+uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t au8Data[], uint32_t u32wLen);
+uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t u8Data);
+uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t au8Data[], uint32_t u32wLen);
+uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr);
+uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t au8Rdata[], uint32_t u32rLen);
+uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr);
+uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t au8Rdata[], uint32_t u32rLen);
+uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr);
+uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t au8Rdata[], uint32_t u32rLen);
+uint32_t I2C_SMBusGetStatus(I2C_T *i2c);
+void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8ClrSMBusIntFlag);
+void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize);
+void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice);
+void I2C_SMBusClose(I2C_T *i2c);
+void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn);
+uint8_t I2C_SMBusGetPECValue(I2C_T *i2c);
+void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t u32Us, uint32_t u32Hclk);
+void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk);
+void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk);
+
+/**@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group I2C_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_i2s.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_i2s.h
new file mode 100644
index 0000000000..b3ebe0c5de
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_i2s.h
@@ -0,0 +1,355 @@
+/****************************************************************************//**
+ * @file     nu_i2s.h
+ * @version  V3.00
+ * @brief    M2354 series I2S driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __NU_I2S_H__
+#define __NU_I2S_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup I2S_Driver I2S Driver
+  @{
+*/
+
+/** @addtogroup I2S_EXPORTED_CONSTANTS I2S Exported Constants
+  @{
+*/
+
+#define I2S_DATABIT_8           (0UL << I2S_CTL0_DATWIDTH_Pos)       /*!< I2S data width is 8-bit  \hideinitializer */
+#define I2S_DATABIT_16          (1UL << I2S_CTL0_DATWIDTH_Pos)       /*!< I2S data width is 16-bit  \hideinitializer */
+#define I2S_DATABIT_24          (2UL << I2S_CTL0_DATWIDTH_Pos)       /*!< I2S data width is 24-bit  \hideinitializer */
+#define I2S_DATABIT_32          (3UL << I2S_CTL0_DATWIDTH_Pos)       /*!< I2S data width is 32-bit  \hideinitializer */
+
+/* Audio Format */
+#define I2S_MONO                I2S_CTL0_MONO_Msk                    /*!< Mono channel  \hideinitializer */
+#define I2S_STEREO              (0UL)                                /*!< Stereo channel  \hideinitializer */
+#define I2S_ENABLE_MONO         I2S_MONO
+#define I2S_DISABLE_MONO        I2S_STEREO
+
+/* I2S Data Format */
+#define I2S_FORMAT_I2S          (0UL << I2S_CTL0_FORMAT_Pos)         /*!< I2S data format  \hideinitializer */
+#define I2S_FORMAT_I2S_MSB      (1UL << I2S_CTL0_FORMAT_Pos)         /*!< I2S MSB data format  \hideinitializer */
+#define I2S_FORMAT_I2S_LSB      (2UL << I2S_CTL0_FORMAT_Pos)         /*!< I2S LSB data format  \hideinitializer */
+#define I2S_FORMAT_PCM          (4UL << I2S_CTL0_FORMAT_Pos)         /*!< PCM data format  \hideinitializer */
+#define I2S_FORMAT_PCM_MSB      (5UL << I2S_CTL0_FORMAT_Pos)         /*!< PCM MSB data format  \hideinitializer */
+#define I2S_FORMAT_PCM_LSB      (6UL << I2S_CTL0_FORMAT_Pos)         /*!< PCM LSB data format  \hideinitializer */
+
+/* I2S Data Format */
+#define I2S_ORDER_AT_MSB        0UL                                  /*!< Channel data is at MSB  \hideinitializer */
+#define I2S_ORDER_AT_LSB        I2S_CTL0_ORDER_Msk                   /*!< Channel data is at LSB  \hideinitializer */
+
+/* I2S TDM Channel Number */
+#define I2S_TDM_2CH             0UL                                  /*!< Use TDM 2 channel  \hideinitializer */
+#define I2S_TDM_4CH             1UL                                  /*!< Use TDM 4 channel  \hideinitializer */
+#define I2S_TDM_6CH             2UL                                  /*!< Use TDM 6 channel  \hideinitializer */
+#define I2S_TDM_8CH             3UL                                  /*!< Use TDM 8 channel  \hideinitializer */
+
+/* I2S TDM Channel Width */
+#define I2S_TDM_WIDTH_8BIT      0UL                                  /*!< TDM channel witch is 8-bit  \hideinitializer */
+#define I2S_TDM_WIDTH_16BIT     1UL                                  /*!< TDM channel witch is 16-bit  \hideinitializer */
+#define I2S_TDM_WIDTH_24BIT     2UL                                  /*!< TDM channel witch is 24-bit  \hideinitializer */
+#define I2S_TDM_WIDTH_32BIT     3UL                                  /*!< TDM channel witch is 32-bit  \hideinitializer */
+
+/* I2S TDM Sync Width */
+#define I2S_TDM_SYNC_ONE_BCLK       0UL                              /*!< TDM sync widht is one BLCK period  \hideinitializer */
+#define I2S_TDM_SYNC_ONE_CHANNEL    1UL                              /*!< TDM sync widht is one channel period  \hideinitializer */
+
+/* I2S Operation mode */
+#define I2S_MODE_SLAVE          I2S_CTL0_SLAVE_Msk                   /*!< As slave mode  \hideinitializer */
+#define I2S_MODE_MASTER         0UL                                  /*!< As master mode  \hideinitializer */
+
+/* I2S FIFO Threshold */
+#define I2S_FIFO_TX_LEVEL_WORD_0    0UL                              /*!< TX threshold is 0 word  \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_1    (1UL << I2S_CTL1_TXTH_Pos)       /*!< TX threshold is 1 word  \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_2    (2UL << I2S_CTL1_TXTH_Pos)       /*!< TX threshold is 2 words  \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_3    (3UL << I2S_CTL1_TXTH_Pos)       /*!< TX threshold is 3 words  \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_4    (4UL << I2S_CTL1_TXTH_Pos)       /*!< TX threshold is 4 words  \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_5    (5UL << I2S_CTL1_TXTH_Pos)       /*!< TX threshold is 5 words  \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_6    (6UL << I2S_CTL1_TXTH_Pos)       /*!< TX threshold is 6 words  \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_7    (7UL << I2S_CTL1_TXTH_Pos)       /*!< TX threshold is 7 words  \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_8    (8UL << I2S_CTL1_TXTH_Pos)       /*!< TX threshold is 8 words  \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_9    (9UL << I2S_CTL1_TXTH_Pos)       /*!< TX threshold is 9 words  \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_10   (10UL << I2S_CTL1_TXTH_Pos)      /*!< TX threshold is 10 words  \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_11   (11UL << I2S_CTL1_TXTH_Pos)      /*!< TX threshold is 11 words  \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_12   (12UL << I2S_CTL1_TXTH_Pos)      /*!< TX threshold is 12 words  \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_13   (13UL << I2S_CTL1_TXTH_Pos)      /*!< TX threshold is 13 words  \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_14   (14UL << I2S_CTL1_TXTH_Pos)      /*!< TX threshold is 14 words  \hideinitializer */
+#define I2S_FIFO_TX_LEVEL_WORD_15   (15UL << I2S_CTL1_TXTH_Pos)      /*!< TX threshold is 15 words  \hideinitializer */
+
+#define I2S_FIFO_RX_LEVEL_WORD_1    0UL                              /*!< RX threshold is 1 word  \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_2    (1UL << I2S_CTL1_RXTH_Pos)       /*!< RX threshold is 2 words  \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_3    (2UL << I2S_CTL1_RXTH_Pos)       /*!< RX threshold is 3 words  \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_4    (3UL << I2S_CTL1_RXTH_Pos)       /*!< RX threshold is 4 words  \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_5    (4UL << I2S_CTL1_RXTH_Pos)       /*!< RX threshold is 5 words  \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_6    (5UL << I2S_CTL1_RXTH_Pos)       /*!< RX threshold is 6 words  \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_7    (6UL << I2S_CTL1_RXTH_Pos)       /*!< RX threshold is 7 words  \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_8    (7UL << I2S_CTL1_RXTH_Pos)       /*!< RX threshold is 8 words  \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_9    (8UL << I2S_CTL1_RXTH_Pos)       /*!< RX threshold is 9 words  \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_10   (9UL << I2S_CTL1_RXTH_Pos)       /*!< RX threshold is 10 words  \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_11   (10UL << I2S_CTL1_RXTH_Pos)      /*!< RX threshold is 11 words  \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_12   (11UL << I2S_CTL1_RXTH_Pos)      /*!< RX threshold is 12 words  \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_13   (12UL << I2S_CTL1_RXTH_Pos)      /*!< RX threshold is 13 words  \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_14   (13UL << I2S_CTL1_RXTH_Pos)      /*!< RX threshold is 14 words  \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_15   (14UL << I2S_CTL1_RXTH_Pos)      /*!< RX threshold is 15 words  \hideinitializer */
+#define I2S_FIFO_RX_LEVEL_WORD_16   (15UL << I2S_CTL1_RXTH_Pos)      /*!< RX threshold is 16 words  \hideinitializer */
+
+/* I2S Record Channel */
+#define I2S_MONO_RIGHT          0UL                                  /*!< Record mono right channel  \hideinitializer */
+#define I2S_MONO_LEFT           I2S_CTL0_RXLCH_Msk                   /*!< Record mono left channel  \hideinitializer */
+
+/* I2S Channel */
+#define I2S_RIGHT               0UL                                  /*!< Select right channel  \hideinitializer */
+#define I2S_LEFT                1UL                                  /*!< Select left channel  \hideinitializer */
+
+/**@}*/ /* end of group I2S_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup I2S_EXPORTED_FUNCTIONS I2S Exported Functions
+  @{
+*/
+
+
+/**
+  * @brief  Enable zero cross detect function.
+  * @param[in] i2s is the base address of I2S module.
+  * @param[in] u32ChMask is the mask for channel number (valid value is from (1~8).
+  * @return none
+  * \hideinitializer
+  */
+__STATIC_INLINE void I2S_ENABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
+{
+    if((u32ChMask > 0UL) && (u32ChMask < 9UL))
+    {
+        i2s->CTL1 |= (1UL << (u32ChMask - 1UL));
+    }
+}
+
+/**
+  * @brief  Disable zero cross detect function.
+  * @param[in] i2s is the base address of I2S module.
+  * @param[in] u32ChMask is the mask for channel number (valid value is from (1~8).
+  * @return none
+  * \hideinitializer
+  */
+__STATIC_INLINE void I2S_DISABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
+{
+    if((u32ChMask > 0UL) && (u32ChMask < 9UL))
+    {
+        i2s->CTL1 &= ~(1UL << (u32ChMask - 1UL));
+    }
+}
+
+/**
+  * @brief  Enable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO.
+  * @param[in] i2s is the base address of I2S module.
+  * @return none
+  * \hideinitializer
+  */
+#define I2S_ENABLE_TXDMA(i2s)  ( (i2s)->CTL0 |= I2S_CTL0_TXPDMAEN_Msk )
+
+/**
+  * @brief  Disable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO.
+  * @param[in] i2s is the base address of I2S module.
+  * @return none
+  * \hideinitializer
+  */
+#define I2S_DISABLE_TXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXPDMAEN_Msk )
+
+/**
+  * @brief  Enable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO.
+  * @param[in] i2s is the base address of I2S module.
+  * @return none
+  * \hideinitializer
+  */
+#define I2S_ENABLE_RXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXPDMAEN_Msk )
+
+/**
+  * @brief  Disable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO.
+  * @param[in] i2s is the base address of I2S module.
+  * @return none
+  * \hideinitializer
+  */
+#define I2S_DISABLE_RXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXPDMAEN_Msk )
+
+/**
+  * @brief  Enable I2S Tx function .
+  * @param[in] i2s is the base address of I2S module.
+  * @return none
+  * \hideinitializer
+  */
+#define I2S_ENABLE_TX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXEN_Msk )
+
+/**
+  * @brief  Disable I2S Tx function .
+  * @param[in] i2s is the base address of I2S module.
+  * @return none
+  * \hideinitializer
+  */
+#define I2S_DISABLE_TX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXEN_Msk )
+
+/**
+  * @brief  Enable I2S Rx function .
+  * @param[in] i2s is the base address of I2S module.
+  * @return none
+  * \hideinitializer
+  */
+#define I2S_ENABLE_RX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXEN_Msk )
+
+/**
+  * @brief  Disable I2S Rx function .
+  * @param[in] i2s is the base address of I2S module.
+  * @return none
+  * \hideinitializer
+  */
+#define I2S_DISABLE_RX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXEN_Msk )
+
+/**
+  * @brief  Enable Tx Mute function .
+  * @param[in] i2s is the base address of I2S module.
+  * @return none
+  * \hideinitializer
+  */
+#define I2S_ENABLE_TX_MUTE(i2s)  ( (i2s)->CTL0 |= I2S_CTL0_MUTE_Msk )
+
+/**
+  * @brief  Disable Tx Mute function .
+  * @param[in] i2s is the base address of I2S module.
+  * @return none
+  * \hideinitializer
+  */
+#define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_MUTE_Msk )
+
+/**
+  * @brief  Clear Tx FIFO. Internal pointer is reset to FIFO start point.
+  * @param[in] i2s is the base address of I2S module.
+  * @return none
+  * \hideinitializer
+  */
+#define I2S_CLR_TX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXFBCLR_Msk )
+
+/**
+  * @brief  Clear Rx FIFO. Internal pointer is reset to FIFO start point.
+  * @param[in] i2s is the base address of I2S module.
+  * @return none
+  * \hideinitializer
+  */
+#define I2S_CLR_RX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXFBCLR_Msk )
+
+/**
+  * @brief  This function sets the recording source channel when mono mode is used.
+  * @param[in] i2s is the base address of I2S module.
+  * @param[in] u32Ch left or right channel. Valid values are:
+  *                - \ref I2S_MONO_LEFT
+  *                - \ref I2S_MONO_RIGHT
+  * @return none
+  * \hideinitializer
+  */
+__STATIC_INLINE void I2S_SET_MONO_RX_CHANNEL(I2S_T *i2s, uint32_t u32Ch)
+{
+    u32Ch == I2S_MONO_LEFT ?
+    (i2s->CTL0 |= I2S_CTL0_RXLCH_Msk) :
+    (i2s->CTL0 &= ~I2S_CTL0_RXLCH_Msk);
+}
+
+/**
+  * @brief  Write data to I2S Tx FIFO.
+  * @param[in] i2s is the base address of I2S module.
+  * @param[in] u32Data: The data written to FIFO.
+  * @return none
+  * \hideinitializer
+  */
+#define I2S_WRITE_TX_FIFO(i2s, u32Data)  ( (i2s)->TXFIFO = (u32Data) )
+
+/**
+  * @brief  Read Rx FIFO.
+  * @param[in] i2s is the base address of I2S module.
+  * @return Data in Rx FIFO.
+  * \hideinitializer
+  */
+#define I2S_READ_RX_FIFO(i2s) ( (i2s)->RXFIFO )
+
+/**
+  * @brief  This function gets the interrupt flag according to the mask parameter.
+  * @param[in] i2s is the base address of I2S module.
+  * @param[in] u32Mask is the mask for the all interrupt flags.
+  * @return The masked bit value of interrupt flag.
+  * \hideinitializer
+  */
+#define I2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 & (u32Mask) )
+
+/**
+  * @brief  This function clears the interrupt flag according to the mask parameter.
+  * @param[in] i2s is the base address of I2S module.
+  * @param[in] u32Mask is the mask for the all interrupt flags.
+  * @return none
+  * \hideinitializer
+  */
+#define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 |= (u32Mask) )
+
+/**
+  * @brief  This function gets the zero crossing interrupt flag according to the mask parameter.
+  * @param[in] i2s is the base address of I2S module.
+  * @param[in] u32Mask is the mask for the all interrupt flags.
+  * @return The masked bit value of interrupt flag.
+  * \hideinitializer
+  */
+#define I2S_GET_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 & (u32Mask) )
+
+/**
+  * @brief  This function clears the zero crossing interrupt flag according to the mask parameter.
+  * @param[in] i2s is the base address of I2S module.
+  * @param[in] u32Mask is the mask for the all interrupt flags.
+  * @return none
+  * \hideinitializer
+  */
+#define I2S_CLR_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 |= (u32Mask) )
+
+/**
+  * @brief  Get transmit FIFO level
+  * @param[in] i2s is the base address of I2S module.
+  * @return FIFO level
+  * \hideinitializer
+  */
+#define I2S_GET_TX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_TXCNT_Msk) >> I2S_STATUS1_TXCNT_Pos) & 0xF )
+
+/**
+  * @brief  Get receive FIFO level
+  * @param[in] i2s is the base address of I2S module.
+  * @return FIFO level
+  * \hideinitializer
+  */
+#define I2S_GET_RX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_RXCNT_Msk) >> I2S_STATUS1_RXCNT_Pos) & 0xF )
+
+uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat);
+void I2S_Close(I2S_T *i2s);
+void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask);
+void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask);
+uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock);
+void I2S_DisableMCLK(I2S_T *i2s);
+void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
+void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth);
+
+
+/**@}*/ /* end of group I2S_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group I2S_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_I2S_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_keystore.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_keystore.h
new file mode 100644
index 0000000000..eb055a3523
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_keystore.h
@@ -0,0 +1,132 @@
+/**************************************************************************//**
+ * @file     nu_keystore.h
+ * @version  V3.00
+ * @brief    Key Store Driver Header
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_KEYSTORE_H__
+#define __NU_KEYSTORE_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup KS_Driver Key Store Driver
+  @{
+*/
+
+/** @addtogroup KS_EXPORTED_CONSTANTS Key Store Exported Constants
+  @{
+*/
+
+#define KS_TOMETAKEY(x)     (((uint32_t)(x) << KS_METADATA_NUMBER_Pos) & KS_METADATA_NUMBER_Msk)
+#define KS_TOKEYIDX(x)      (((uint32_t)(x) & KS_METADATA_NUMBER_Msk) >> KS_METADATA_NUMBER_Pos)
+
+typedef enum KSMEM
+{
+    KS_SRAM  = 0,     /*!< Volatile Memory                                */
+    KS_FLASH = 1,    /*!< Non-volatile Memory                            */
+    KS_OTP   = 2     /*!< One-Time Programming Memory                    */
+} KS_MEM_Type;
+
+#define KS_OP_READ      (0 << KS_CTL_OPMODE_Pos)
+#define KS_OP_WRITE     (1 << KS_CTL_OPMODE_Pos)
+#define KS_OP_ERASE     (2 << KS_CTL_OPMODE_Pos)
+#define KS_OP_ERASE_ALL (3 << KS_CTL_OPMODE_Pos)
+#define KS_OP_REVOKE    (4 << KS_CTL_OPMODE_Pos)
+#define KS_OP_REMAN     (5 << KS_CTL_OPMODE_Pos)
+
+#define KS_OWNER_AES        (0ul)
+#define KS_OWNER_HMAC       (1ul)
+#define KS_OWNER_RSA_EXP    (2ul)
+#define KS_OWNER_RSA_MID    (3ul)
+#define KS_OWNER_ECC        (4ul)
+#define KS_OWNER_CPU        (5ul)
+
+#define KS_META_AES     (0ul << KS_METADATA_OWNER_Pos)   /*!< AES Access Only                                */
+#define KS_META_HMAC    (1ul << KS_METADATA_OWNER_Pos)   /*!< HMAC Access Only                               */
+#define KS_META_RSA_EXP (2ul << KS_METADATA_OWNER_Pos)   /*!< RSA_EXP Access Only                            */
+#define KS_META_RSA_MID (3ul << KS_METADATA_OWNER_Pos)   /*!< RSA_MID Access Only                            */
+#define KS_META_ECC     (4ul << KS_METADATA_OWNER_Pos)   /*!< ECC Access Only                                */
+#define KS_META_CPU     (5ul << KS_METADATA_OWNER_Pos)   /*!< CPU Access Only                                */
+
+#define KS_META_128     ( 0ul << KS_METADATA_SIZE_Pos)  /*!< Key size 128 bits                              */
+#define KS_META_163     ( 1ul << KS_METADATA_SIZE_Pos)  /*!< Key size 163 bits                              */
+#define KS_META_192     ( 2ul << KS_METADATA_SIZE_Pos)  /*!< Key size 192 bits                              */
+#define KS_META_224     ( 3ul << KS_METADATA_SIZE_Pos)  /*!< Key size 224 bits                              */
+#define KS_META_233     ( 4ul << KS_METADATA_SIZE_Pos)  /*!< Key size 233 bits                              */
+#define KS_META_255     ( 5ul << KS_METADATA_SIZE_Pos)  /*!< Key size 255 bits                              */
+#define KS_META_256     ( 6ul << KS_METADATA_SIZE_Pos)  /*!< Key size 256 bits                              */
+#define KS_META_283     ( 7ul << KS_METADATA_SIZE_Pos)  /*!< Key size 283 bits                              */
+#define KS_META_384     ( 8ul << KS_METADATA_SIZE_Pos)  /*!< Key size 384 bits                              */
+#define KS_META_409     ( 9ul << KS_METADATA_SIZE_Pos)  /*!< Key size 409 bits                              */
+#define KS_META_512     (10ul << KS_METADATA_SIZE_Pos)  /*!< Key size 512 bits                              */
+#define KS_META_521     (11ul << KS_METADATA_SIZE_Pos)  /*!< Key size 521 bits                              */
+#define KS_META_571     (12ul << KS_METADATA_SIZE_Pos)  /*!< Key size 571 bits                              */
+#define KS_META_1024    (16ul << KS_METADATA_SIZE_Pos)  /*!< Key size 1024 bits                             */
+#define KS_META_1536    (17ul << KS_METADATA_SIZE_Pos)  /*!< Key size 1024 bits                             */
+#define KS_META_2048    (18ul << KS_METADATA_SIZE_Pos)  /*!< Key size 2048 bits                             */
+#define KS_META_3072    (19ul << KS_METADATA_SIZE_Pos)  /*!< Key size 1024 bits                             */
+#define KS_META_4096    (20ul << KS_METADATA_SIZE_Pos)  /*!< Key size 4096 bits                             */
+
+#define KS_META_BOOT    ( 1ul << KS_METADATA_BS_Pos)    /*!< Key only used for boot ROM only                */
+
+#define KS_META_READABLE (1ul << KS_METADATA_READABLE_Pos)  /*!< Allow the key to be read by software       */
+
+#define KS_META_PRIV     (1ul << KS_METADATA_PRIV_Pos)  /*!< Privilege key                                  */
+#define KS_META_NONPRIV  (0ul << KS_METADATA_PRIV_Pos)  /*!< Non-privilege key                              */
+
+#define KS_META_SECURE    (1ul << KS_METADATA_SEC_Pos)    /*!< Secure key                                     */
+#define KS_META_NONSECURE (0ul << KS_METADATA_SEC_Pos)    /*!< Non-secure key                                 */
+
+
+/**
+  * @brief      Enable scramble function
+  * @details    This function is used to enable scramle function of Key Store.
+  */
+
+#define KS_SCRAMBLING()     KS->CTL |= KS_CTL_SCMB_Msk
+
+
+
+
+/**@}*/ /* end of group KS_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup KS_EXPORTED_FUNCTIONS Key Store Exported Functions
+  @{
+*/
+
+void KS_Open(void);
+int32_t KS_Read(KS_MEM_Type type, int32_t i32KeyIdx, uint32_t au32Key[], uint32_t u32WordCnt);
+int32_t KS_Write(KS_MEM_Type eType, uint32_t u32Meta, uint32_t au32Key[]);
+int32_t KS_WriteOTP(int32_t i32KeyIdx, uint32_t u32Meta, uint32_t au32Key[]);
+int32_t KS_EraseKey(int32_t i32KeyIdx);
+int32_t KS_EraseAll(KS_MEM_Type eType);
+int32_t KS_RevokeKey(KS_MEM_Type eType, int32_t i32KeyIdx);
+uint32_t KS_GetRemainSize(KS_MEM_Type eType);
+int32_t KS_ToggleSRAM(void);
+uint32_t KS_GetKeyWordCnt(uint32_t u32Meta);
+uint32_t KS_GetRemainKeyCount(KS_MEM_Type mem);
+
+/**@}*/ /* end of group KS_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group KS_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_KEYSTORE_H__ */
+
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_lcd.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_lcd.h
new file mode 100644
index 0000000000..02613ec21d
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_lcd.h
@@ -0,0 +1,531 @@
+/**************************************************************************//**
+ * @file     nu_lcd.h
+ * @version  V3.00
+ * @brief    Liquid-Crystal Display(LCD) driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_LCD_H__
+#define __NU_LCD_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup LCD_Driver LCD Driver
+  @{
+*/
+
+/** @addtogroup LCD_EXPORTED_CONSTANTS LCD Exported Constants
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/*  LCD Bias Voltage Level Selection Constant Definitions                                                  */
+/*---------------------------------------------------------------------------------------------------------*/
+#define LCD_BIAS_LV_1_2                 (1ul << LCD_PCTL_BIAS_Pos) /*!< LCD bias voltage level selection - 1/2 Bias \hideinitializer */
+#define LCD_BIAS_LV_1_3                 (2ul << LCD_PCTL_BIAS_Pos) /*!< LCD bias voltage level selection - 1/3 Bias \hideinitializer */
+#define LCD_BIAS_LV_1_4                 (3ul << LCD_PCTL_BIAS_Pos) /*!< LCD bias voltage level selection - 1/4 Bias \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  LCD COM Duty Ratio Selection Constant Definitions                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define LCD_COM_DUTY_1_1                (0ul << LCD_PCTL_DUTY_Pos) /*!< LCD com duty ratio selection - 1/1 Duty \hideinitializer */
+#define LCD_COM_DUTY_1_2                (1ul << LCD_PCTL_DUTY_Pos) /*!< LCD com duty ratio selection - 1/2 Duty \hideinitializer */
+#define LCD_COM_DUTY_1_3                (2ul << LCD_PCTL_DUTY_Pos) /*!< LCD com duty ratio selection - 1/3 Duty \hideinitializer */
+#define LCD_COM_DUTY_1_4                (3ul << LCD_PCTL_DUTY_Pos) /*!< LCD com duty ratio selection - 1/4 Duty \hideinitializer */
+#define LCD_COM_DUTY_1_5                (4ul << LCD_PCTL_DUTY_Pos) /*!< LCD com duty ratio selection - 1/5 Duty \hideinitializer */
+#define LCD_COM_DUTY_1_6                (5ul << LCD_PCTL_DUTY_Pos) /*!< LCD com duty ratio selection - 1/6 Duty \hideinitializer */
+#define LCD_COM_DUTY_1_7                (6ul << LCD_PCTL_DUTY_Pos) /*!< LCD com duty ratio selection - 1/7 Duty \hideinitializer */
+#define LCD_COM_DUTY_1_8                (7ul << LCD_PCTL_DUTY_Pos) /*!< LCD com duty ratio selection - 1/8 Duty \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  LCD Waveform Attribute Selection Constant Definitions                                                  */
+/*---------------------------------------------------------------------------------------------------------*/
+#define LCD_WAVEFORM_TYPE_A_NORMAL      (0ul << LCD_PCTL_TYPE_Pos) /*!< LCD waveform Type-A, no inverse \hideinitializer */
+#define LCD_WAVEFORM_TYPE_B_NORMAL      (1ul << LCD_PCTL_TYPE_Pos) /*!< LCD waveform Type-B, no inverse \hideinitializer */
+#define LCD_WAVEFORM_TYPE_A_INVERSE     (2ul << LCD_PCTL_TYPE_Pos) /*!< LCD waveform Type-A and inverse \hideinitializer */
+#define LCD_WAVEFORM_TYPE_B_INVERSE     (3ul << LCD_PCTL_TYPE_Pos) /*!< LCD waveform Type-B and inverse \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  LCD Charge Pump Voltage Selection Constant Definitions                                                 */
+/*---------------------------------------------------------------------------------------------------------*/
+#define LCD_CP_VOLTAGE_LV_0             (0ul << LCD_PCTL_CPVSEL_Pos) /*!< Select LCD charge pump voltage 2.6 V \hideinitializer */
+#define LCD_CP_VOLTAGE_LV_1             (1ul << LCD_PCTL_CPVSEL_Pos) /*!< Select LCD charge pump voltage 2.8 V \hideinitializer */
+#define LCD_CP_VOLTAGE_LV_2             (2ul << LCD_PCTL_CPVSEL_Pos) /*!< Select LCD charge pump voltage 3.0 V \hideinitializer */
+#define LCD_CP_VOLTAGE_LV_3             (3ul << LCD_PCTL_CPVSEL_Pos) /*!< Select LCD charge pump voltage 3.2 V \hideinitializer */
+#define LCD_CP_VOLTAGE_LV_4             (4ul << LCD_PCTL_CPVSEL_Pos) /*!< Select LCD charge pump voltage 3.4 V \hideinitializer */
+#define LCD_CP_VOLTAGE_LV_5             (5ul << LCD_PCTL_CPVSEL_Pos) /*!< Select LCD charge pump voltage 3.6 V \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  LCD Interrupt Source Constant Definitions                                                              */
+/*---------------------------------------------------------------------------------------------------------*/
+#define LCD_DISABLE_ALL_INT             (0ul << LCD_INTEN_FCEIEN_Pos)   /*!< Disable all LCD interrupt sources \hideinitializer */
+#define LCD_FRAME_COUNTING_END_INT      (1ul << LCD_INTEN_FCEIEN_Pos)   /*!< Indicate frame count end interrupt \hideinitializer */
+#define LCD_FRAME_END_INT               (1ul << LCD_INTEN_FEIEN_Pos)    /*!< Indicate frame end interrupt \hideinitializer */
+#define LCD_CPTOUT_INT                  (1ul << LCD_INTEN_CTOIEN_Pos)   /*!< Indicate charge pump charging timeout interrupt \hideinitializer */
+#define LCD_ENABLE_ALL_INT              (7ul << LCD_INTEN_FCEIEN_Pos)   /*!< Enable all LCD interrupt sources \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  LCD Operation Voltage Source Constant Definitions                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define LCD_VOLTAGE_SOURCE_VLCD         (0ul << LCD_DCTL_VSRC_Pos) /*!< LCD voltage source from external VLCD power \hideinitializer */
+#define LCD_VOLTAGE_SOURCE_AVDD         (1ul << LCD_DCTL_VSRC_Pos) /*!< LCD voltage source from internal VDD \hideinitializer */
+#define LCD_VOLTAGE_SOURCE_CP           (2ul << LCD_DCTL_VSRC_Pos) /*!< LCD voltage source from built-in charge pump \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  LCD Driving Mode Selection Constant Definitions                                                        */
+/*---------------------------------------------------------------------------------------------------------*/
+#define LCD_LOW_DRIVING_AND_BUF_OFF                     (0ul << LCD_DCTL_RESMODE_Pos) /*!< LCD operates with low-drive and voltage buffer disabled \hideinitializer */
+#define LCD_HIGH_DRIVING_AND_BUF_OFF                    (1ul << LCD_DCTL_RESMODE_Pos) /*!< LCD operates with high-drive and voltage buffer disabled \hideinitializer */
+#define LCD_LOW_DRIVING_AND_BUF_ON                      (2ul << LCD_DCTL_RESMODE_Pos) /*!< LCD operates with low-drive and voltage buffer enabled \hideinitializer */
+#define LCD_HIGH_DRIVING_AND_BUF_OFF_AND_PWR_SAVING     (5ul << LCD_DCTL_RESMODE_Pos) /*!< LCD operates with high-drive, voltage buffer disabled and power saving \hideinitializer */
+#define LCD_LOW_DRIVING_AND_BUF_ON_AND_PWR_SAVING       (6ul << LCD_DCTL_RESMODE_Pos) /*!< LCD operates with low-drive, voltage buffer enabled and power saving \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  LCD Power Saving Mode Constant Definitions                                                             */
+/*---------------------------------------------------------------------------------------------------------*/
+#define LCD_PWR_SAVING_NORMAL_MODE              (0ul << LCD_DCTL_PSVREV_Pos) /*!< The timing of LCD power saving is normal \hideinitializer */
+#define LCD_PWR_SAVING_REVERSE_MODE             (1ul << LCD_DCTL_PSVREV_Pos) /*!< The timing of LCD power saving is reverse \hideinitializer */
+
+/**@}*/ /* end of group LCD_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup LCD_EXPORTED_STRUCTS LCD Exported Structs
+  @{
+*/
+/**
+  * @details    LCD Configuration Data Struct
+  */
+typedef struct
+{
+    uint32_t u32SrcFreq;        /*!< LCD clock source frequency */
+    uint32_t u32ComDuty;        /*!< COM duty */
+    uint32_t u32BiasLevel;      /*!< Bias level */
+    uint32_t u32Framerate;      /*!< Operation frame rate */
+    uint32_t u32WaveformType;   /*!< Waveform type */
+    uint32_t u32IntSrc;         /*!< Interrupt source */
+    uint32_t u32DrivingMode;    /*!< Driving mode */
+    uint32_t u32VSrc;           /*!< Voltage source */
+} S_LCD_CFG_T;
+
+/**@}*/ /* end of group LCD_EXPORTED_STRUCTS */
+
+
+/** @addtogroup LCD_EXPORTED_FUNCTIONS LCD Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Enable LCD Display
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to enable LCD display.
+  */
+#define LCD_ENABLE_DISPLAY()        do{ LCD->CTL |= LCD_CTL_EN_Msk; while(LCD->CTL & LCD_CTL_SYNC_Msk) {} }while(0)
+
+/**
+  * @brief      Disable LCD Display
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to disable LCD display.
+  */
+#define LCD_DISABLE_DISPLAY()       do{ LCD->CTL &= ~LCD_CTL_EN_Msk; while(LCD->CTL & LCD_CTL_SYNC_Msk) {} }while(0)
+
+/**
+  * @brief      Set LCD Waveform Type
+  *
+  * @param[in]  type       The LCD waveform type. It could be one of the following type
+  *                             - \ref LCD_WAVEFORM_TYPE_A_NORMAL
+  *                             - \ref LCD_WAVEFORM_TYPE_B_NORMAL
+  *                             - \ref LCD_WAVEFORM_TYPE_A_INVERSE
+  *                             - \ref LCD_WAVEFORM_TYPE_B_INVERSE
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set the attribute of LCD output waveform.
+  */
+#define LCD_WAVEFORM_TYPE(type)     (LCD->PCTL = (LCD->PCTL & ~LCD_PCTL_TYPE_Msk) | (type))
+
+/**
+  * @brief      Set LCD Source Clock Divider
+  *
+  * @param[in]  div         The frequency divider, valid value is between 1 to 1024.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set the LCD operarion frequency is (LCD source frequency / div).
+  */
+#define LCD_SET_FREQDIV(div)        (LCD->PCTL = (LCD->PCTL & ~LCD_PCTL_FREQDIV_Msk) | (((div)-1) << LCD_PCTL_FREQDIV_Pos))
+
+/**
+  * @brief      Set Charge Pump Voltage
+  *
+  * @param[in]  voltage     The target charge pump voltage. It could be one of the following voltage level
+  *                             - \ref LCD_CP_VOLTAGE_LV_0, 2.6 V
+  *                             - \ref LCD_CP_VOLTAGE_LV_1, 2.8 V
+  *                             - \ref LCD_CP_VOLTAGE_LV_2, 3.0 V
+  *                             - \ref LCD_CP_VOLTAGE_LV_3, 3.2 V
+  *                             - \ref LCD_CP_VOLTAGE_LV_4, 3.4 V
+  *                             - \ref LCD_CP_VOLTAGE_LV_5, 3.6 V
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set charge pump voltage for VLCD.
+  */
+#define LCD_SET_CP_VOLTAGE(voltage) (LCD->PCTL = (LCD->PCTL & ~LCD_PCTL_CPVSEL_Msk) | (voltage))
+
+/**
+  * @brief      Decrease Charge Pump Voltage
+  *
+  * @param[in]  unit        The tuning units, valid value is between 0 to 7.
+  *                         One unit of voltage is about 0.03V, and the charge pump voltage is decreased (unit * 0.03)V.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to decrease charge pump voltage by specific units.
+  */
+#define LCD_CP_VOLTAGE_DECREASE(unit)   (LCD->PCTL = (LCD->PCTL & ~LCD_PCTL_CPVTUNE_Msk) | ((unit) << LCD_PCTL_CPVTUNE_Pos))
+
+/**
+  * @brief      Increase Charge Pump Voltage
+  *
+  * @param[in]  unit        The tuning units, valid value is between 1 to 8.
+  *                         One unit of voltage is about 0.03V, and the charge pump voltage is increased (unit * 0.03)V.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to increase charge pump voltage by specific units.
+  */
+#define LCD_CP_VOLTAGE_INCREASE(unit)   (LCD->PCTL = (LCD->PCTL & ~LCD_PCTL_CPVTUNE_Msk) | ((16-(unit)) << LCD_PCTL_CPVTUNE_Pos))
+
+/**
+  * @brief      Set LCD Blinking ON
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to enable LCD blinking.
+  */
+#define LCD_BLINKING_ON()       (LCD->FCTL |= LCD_FCTL_BLINK_Msk)
+
+/**
+  * @brief      Set LCD Blinking OFF
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to disable LCD blinking.
+  */
+#define LCD_BLINKING_OFF()      (LCD->FCTL &= ~LCD_FCTL_BLINK_Msk)
+
+/**
+  * @brief      Set LCD Frame Counting Value
+  *
+  * @param[in]  value       Frame counting value. Valid value is between 1 to 1024.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set the LCD frame counting value to configure the blink interval.
+  * @note       For type-B waveform, the frame counter increases at the end of odd frames, not even frames.
+  */
+#define LCD_SET_FRAME_COUNTING_VALUE(value)     (LCD->FCTL = (LCD->FCTL & ~LCD_FCTL_FCV_Msk) | (((value)-1) << LCD_FCTL_FCV_Pos))
+
+/**
+  * @brief      Set Null Frame Time
+  *
+  * @param[in]  unit        The unit parameter is used to determine the null frame time, valid value is between 0 to 15.
+  *                         And one unit time is one LCD operation clock period.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set the one null frame time.
+  * @note       All COM and SEG output voltages will keep at 0V during a null frame.
+  */
+#define LCD_SET_NULL_FRAME_TIME(unit)       (LCD->FCTL = (LCD->FCTL & ~LCD_FCTL_NFTIME_Msk) | ((unit) << LCD_FCTL_NFTIME_Pos))
+
+/**
+  * @brief      Set Continuous Frames
+  *
+  * @param[in]  frame       The continuous frames, valid setting is between 1 to 16 frames.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to specify the number of continuous frames reached to insert one null frame.
+  */
+#define LCD_SET_CONTINUOUS_FRAME(frame)     (LCD->FCTL = (LCD->FCTL & ~LCD_FCTL_NFNUM_Msk) | (((frame)-1) << LCD_FCTL_NFNUM_Pos))
+
+/**
+  * @brief      Select LCD Voltage Source
+  *
+  * @param[in]  mode        The LCD operation voltage source. It could be one of the following source
+  *                             - \ref LCD_VOLTAGE_SOURCE_VLCD
+  *                             - \ref LCD_VOLTAGE_SOURCE_AVDD
+  *                             - \ref LCD_VOLTAGE_SOURCE_CP
+  *
+  * @return     None
+  *
+  * @details    This macro is used to select LCD operation voltage source.
+  */
+#define LCD_VOLTAGE_SOURCE(source)  (LCD->DCTL = (LCD->DCTL & ~LCD_DCTL_VSRC_Msk) | (source))
+
+/**
+  * @brief      Set LCD Driving Mode
+  *
+  * @param[in]  mode        The LCD operation driving mode. It could be one of the following mode
+  *                             - \ref LCD_LOW_DRIVING_AND_BUF_OFF
+  *                             - \ref LCD_HIGH_DRIVING_AND_BUF_OFF
+  *                             - \ref LCD_LOW_DRIVING_AND_BUF_ON
+  *                             - \ref LCD_HIGH_DRIVING_AND_BUF_OFF_AND_PWR_SAVING
+  *                             - \ref LCD_LOW_DRIVING_AND_BUF_ON_AND_PWR_SAVING
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set LCD operation drivig mode.
+  */
+#define LCD_DRIVING_MODE(mode)      (LCD->DCTL = (LCD->DCTL & ~(LCD_DCTL_RESMODE_Msk | LCD_DCTL_BUFEN_Msk | LCD_DCTL_PSVEN_Msk)) | (mode))
+
+/**
+  * @brief      Select Power Saving Mode
+  *
+  * @param[in]  mode        The LCD power saving mode selection. It could be one of the following constant definition
+  *                             - \ref LCD_PWR_SAVING_NORMAL_MODE
+  *                             - \ref LCD_PWR_SAVING_REVERSE_MODE
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set the LCD power saving mode.
+  *             When the timing of power saving mode is reversed, the original power saving period becomes no power saving,
+  *             and the original no power saving period becomes power saving.
+  */
+#define LCD_PWR_SAVING_MODE(mode)   (LCD->DCTL = (LCD->DCTL & ~LCD_DCTL_PSVREV_Msk) | (mode))
+
+/**
+  * @brief      Set Power Saving T1 Period
+  *
+  * @param[in]  t1      The number of t1 to determine T1 period, valid value is between 1 to 16.
+  *                     And one unit of t1 period is half of LCD operation clock period.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to configure the T1 (Enable Time) period of power saving.
+  */
+#define LCD_PWR_SAVING_T1_PERIOD(t1)    (LCD->DCTL = (LCD->DCTL & ~LCD_DCTL_PSVT1_Msk) | (((t1)-1) << LCD_DCTL_PSVT1_Pos))
+
+/**
+  * @brief      Set Power Saving T2 Period
+  *
+  * @param[in]  t2      The number of t2 to determine T2 period, valid value is between 1 to 16.
+  *                     And one unit of t1 period is half of LCD operation clock period.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to configure the T2 (On Time) period of power saving.
+  */
+#define LCD_PWR_SAVING_T2_PERIOD(t2)    (LCD->DCTL = (LCD->DCTL & ~LCD_DCTL_PSVT2_Msk) | (((t2)-1) << LCD_DCTL_PSVT2_Pos))
+
+/**
+  * @brief      Set Charging Timeout Time
+  *
+  * @param[in]  value   The maximum timeout value, valid value is between 1 to 8192.
+  *                     And one unit of timeout value is one LCD operation clock period.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set maximum timeout time of charge pump charging timer.
+  */
+#define LCD_SET_CHARGE_TIMEOUT_TIME(value)  (LCD->DCTL = (LCD->DCTL & ~LCD_DCTL_CTOTIME_Msk) | (((value)-1) << LCD_DCTL_CTOTIME_Pos))
+
+/**
+  * @brief      Select Device Package Type
+  *
+  * @param[in]  pak     Select device package type.
+  *                     0 for 128-pin package, and 1 for 64-pin package.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to select device output pins for LCD controller with different package type.
+  */
+#define LCD_SELECT_PACKAGE_TYPE(pkg)    (LCD->PKGSEL = (LCD->PKGSEL & ~LCD_PKGSEL_PKG_Msk) | ((pkg) << LCD_PKGSEL_PKG_Pos))
+
+/**
+  * @brief      Enable LCD Frame Counting End Interrupt
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to enable frame count end interrupt function.
+  */
+#define LCD_ENABLE_FRAME_COUNTING_END_INT()     (LCD->INTEN |= LCD_INTEN_FCEIEN_Msk)
+
+/**
+  * @brief      Disable LCD Frame Counting End Interrupt
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to disable frame count end interrupt function.
+  */
+#define LCD_DISABLE_FRAME_COUNTING_END_INT()    (LCD->INTEN &= ~LCD_INTEN_FCEIEN_Msk)
+
+/**
+  * @brief      Enable LCD Frame End Interrupt
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to enable frame end interrupt function.
+  */
+#define LCD_ENABLE_FRAME_END_INT()      (LCD->INTEN |= LCD_INTEN_FEIEN_Msk)
+
+/**
+  * @brief      Disable LCD Frame End Interrupt
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to disable frame end interrupt function.
+  */
+#define LCD_DISABLE_FRAME_END_INT()     (LCD->INTEN &= ~LCD_INTEN_FEIEN_Msk)
+
+/**
+  * @brief      Enable Charging Timeout Interrupt
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to enable charge pump charging timeout interrupt function.
+  */
+#define LCD_ENABLE_CHARGE_TIMEOUT_INT()     (LCD->INTEN |= LCD_INTEN_CTOIEN_Msk)
+
+/**
+  * @brief      Disable Charging Timeout Interrupt
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to disable charge pump charging timeout interrupt function.
+  */
+#define LCD_DISABLE_CHARGE_TIMEOUT_INT()    (LCD->INTEN &= ~LCD_INTEN_CTOIEN_Msk)
+
+/**
+  * @brief      Get LCD Frame Counting End Flag
+  *
+  * @param      None
+  *
+  * @retval     0   Frame count end flag did not occur
+  * @retval     1   Frame count end flag occurred
+  *
+  * @details    This macro gets frame count end flag.
+  */
+#define LCD_GET_FRAME_COUNTING_END_FLAG()   ((LCD->STS & LCD_STS_FCEF_Msk)? 1UL : 0UL)
+
+/**
+  * @brief      Clear LCD Frame Counting End Flag
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro clears frame count end flag.
+  */
+#define LCD_CLEAR_FRAME_COUNTING_END_FLAG() (LCD->STS = LCD_STS_FCEF_Msk)
+
+/**
+  * @brief      Get LCD Frame End Flag
+  *
+  * @param      None
+  *
+  * @retval     0   Frame end flag did not occur
+  * @retval     1   Frame end flag occurred
+  *
+  * @details    This macro gets frame end flag.
+  */
+#define LCD_GET_FRAME_END_FLAG()            ((LCD->STS & LCD_STS_FEF_Msk)? 1UL : 0UL)
+
+/**
+  * @brief      Clear LCD Frame End Flag
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro clears frame end flag.
+  */
+#define LCD_CLEAR_FRAME_END_FLAG()          (LCD->STS = LCD_STS_FEF_Msk)
+
+/**
+  * @brief      Get Charging Timeout Flag
+  *
+  * @param      None
+  *
+  * @retval     0   Charge pump timer timeout flag did not occur
+  * @retval     1   Charge pump timer timeout flag occurred
+  *
+  * @details    This macro gets charge pump charging timeout flag.
+  */
+#define LCD_GET_CHARGE_TIMEOUT_FLAG()       ((LCD->STS & LCD_STS_CTOF_Msk)? 1UL : 0UL)
+
+/**
+  * @brief      Clear Charging Timeout Flag
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro clears charge pump charging timeout flag.
+  */
+#define LCD_CLEAR_CHARGE_TIMEOUT_FLAG()     (LCD->STS = LCD_STS_CTOF_Msk)
+
+/**
+  * @brief      Get Charging Time
+  *
+  * @param      None
+  *
+  * @return     Current 13-bit charging timer value
+  *
+  * @details    This macro gets charging timer value while stops charge pump charging.
+  */
+#define LCD_GET_CHARGE_TIME()              ((LCD->STS & LCD_STS_CTIME_Msk) >> 16)
+
+
+uint32_t LCD_Open(S_LCD_CFG_T *pLCDCfg);
+void LCD_Close(void);
+void LCD_SetPixel(uint32_t u32Com, uint32_t u32Seg, uint32_t u32OnFlag);
+void LCD_SetAllPixels(uint32_t u32OnOff);
+uint32_t LCD_EnableBlink(uint32_t u32ms);
+void LCD_DisableBlink(void);
+void LCD_EnableInt(uint32_t u32IntSrc);
+void LCD_DisableInt(uint32_t u32IntSrc);
+
+/**@}*/ /* end of group LCD_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group LCD_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_LCD_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_otg.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_otg.h
new file mode 100644
index 0000000000..79a9af8b58
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_otg.h
@@ -0,0 +1,256 @@
+/**************************************************************************//**
+ * @file     nu_otg.h
+ * @version  V3.00
+ * @brief    M2354 series OTG driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __NU_OTG_H__
+#define __NU_OTG_H__
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Include related headers                                                                                 */
+/*---------------------------------------------------------------------------------------------------------*/
+#include "M2354.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup OTG_Driver OTG Driver
+  @{
+*/
+
+
+/** @addtogroup OTG_EXPORTED_CONSTANTS OTG Exported Constants
+  @{
+*/
+
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* OTG constant definitions                                                                                */
+/*---------------------------------------------------------------------------------------------------------*/
+#define OTG_VBUS_EN_ACTIVE_HIGH      (0UL) /*!< USB VBUS power switch enable signal is active high. */
+#define OTG_VBUS_EN_ACTIVE_LOW       (1UL) /*!< USB VBUS power switch enable signal is active low. */
+#define OTG_VBUS_ST_VALID_HIGH       (0UL) /*!< USB VBUS power switch valid status is high. */
+#define OTG_VBUS_ST_VALID_LOW        (1UL) /*!< USB VBUS power switch valid status is low. */
+
+
+/**@}*/ /* end of group OTG_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup OTG_EXPORTED_FUNCTIONS OTG Exported Functions
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Define Macros and functions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+
+
+/**
+  * @brief This macro is used to enable OTG function
+  * @param None
+  * @return None
+  * @details This macro will set OTGEN bit of OTG_CTL register to enable OTG function.
+  */
+#define OTG_ENABLE()    (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->CTL |= OTG_CTL_OTGEN_Msk):(OTG->CTL |= OTG_CTL_OTGEN_Msk))
+
+/**
+  * @brief This macro is used to disable OTG function
+  * @param None
+  * @return None
+  * @details This macro will clear OTGEN bit of OTG_CTL register to disable OTG function.
+  */
+#define OTG_DISABLE()    (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->CTL &= ~OTG_CTL_OTGEN_Msk):(OTG->CTL &= ~OTG_CTL_OTGEN_Msk))
+
+/**
+  * @brief This macro is used to enable USB PHY
+  * @param None
+  * @return None
+  * @details When the USB role is selected as OTG device, use this macro to enable USB PHY.
+  *          This macro will set OTGPHYEN bit of OTG_PHYCTL register to enable USB PHY.
+  */
+#define OTG_ENABLE_PHY()    (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->PHYCTL |= OTG_PHYCTL_OTGPHYEN_Msk):(OTG->PHYCTL |= OTG_PHYCTL_OTGPHYEN_Msk))
+
+/**
+  * @brief This macro is used to disable USB PHY
+  * @param None
+  * @return None
+  * @details This macro will clear OTGPHYEN bit of OTG_PHYCTL register to disable USB PHY.
+  */
+#define OTG_DISABLE_PHY()    (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->PHYCTL &= ~OTG_PHYCTL_OTGPHYEN_Msk):(OTG->PHYCTL &= ~OTG_PHYCTL_OTGPHYEN_Msk))
+
+/**
+  * @brief This macro is used to enable ID detection function
+  * @param None
+  * @return None
+  * @details This macro will set IDDETEN bit of OTG_PHYCTL register to enable ID detection function.
+  */
+#define OTG_ENABLE_ID_DETECT()    (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->PHYCTL |= OTG_PHYCTL_IDDETEN_Msk):(OTG->PHYCTL |= OTG_PHYCTL_IDDETEN_Msk))
+
+/**
+  * @brief This macro is used to disable ID detection function
+  * @param None
+  * @return None
+  * @details This macro will clear IDDETEN bit of OTG_PHYCTL register to disable ID detection function.
+  */
+#define OTG_DISABLE_ID_DETECT()    (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->PHYCTL &= ~OTG_PHYCTL_IDDETEN_Msk):(OTG->PHYCTL &= ~OTG_PHYCTL_IDDETEN_Msk))
+
+/**
+  * @brief This macro is used to enable OTG wake-up function
+  * @param None
+  * @return None
+  * @details This macro will set WKEN bit of OTG_CTL register to enable OTG wake-up function.
+  */
+#define OTG_ENABLE_WAKEUP()    (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->CTL |= OTG_CTL_WKEN_Msk):(OTG->CTL |= OTG_CTL_WKEN_Msk))
+
+/**
+  * @brief This macro is used to disable OTG wake-up function
+  * @param None
+  * @return None
+  * @details This macro will clear WKEN bit of OTG_CTL register to disable OTG wake-up function.
+  */
+#define OTG_DISABLE_WAKEUP()    (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->CTL &= ~OTG_CTL_WKEN_Msk):(OTG->CTL &= ~OTG_CTL_WKEN_Msk))
+
+/**
+  * @brief This macro is used to set the polarity of USB_VBUS_EN pin
+  * @param[in] u32Pol The polarity selection. Valid values are listed below.
+  *                    - \ref OTG_VBUS_EN_ACTIVE_HIGH
+  *                    - \ref OTG_VBUS_EN_ACTIVE_LOW
+  * @return None
+  * @details This macro is used to set the polarity of external USB VBUS power switch enable signal.
+  */
+#define OTG_SET_VBUS_EN_POL(u32Pol)    (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->PHYCTL = (OTG_NS->PHYCTL & (~OTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol)<PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol)<PHYCTL = (OTG_NS->PHYCTL & (~OTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol)<PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol)<INTEN |= (u32Mask)):(OTG->INTEN |= (u32Mask)))
+
+/**
+  * @brief This macro is used to disable OTG related interrupts
+  * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
+  *                    - \ref OTG_INTEN_ROLECHGIEN_Msk
+  *                    - \ref OTG_INTEN_VBEIEN_Msk
+  *                    - \ref OTG_INTEN_SRPFIEN_Msk
+  *                    - \ref OTG_INTEN_HNPFIEN_Msk
+  *                    - \ref OTG_INTEN_GOIDLEIEN_Msk
+  *                    - \ref OTG_INTEN_IDCHGIEN_Msk
+  *                    - \ref OTG_INTEN_PDEVIEN_Msk
+  *                    - \ref OTG_INTEN_HOSTIEN_Msk
+  *                    - \ref OTG_INTEN_BVLDCHGIEN_Msk
+  *                    - \ref OTG_INTEN_AVLDCHGIEN_Msk
+  *                    - \ref OTG_INTEN_VBCHGIEN_Msk
+  *                    - \ref OTG_INTEN_SECHGIEN_Msk
+  *                    - \ref OTG_INTEN_SRPDETIEN_Msk
+  * @return None
+  * @details This macro will disable OTG related interrupts specified by u32Mask parameter.
+  */
+#define OTG_DISABLE_INT(u32Mask)    (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->INTEN &= ~(u32Mask)):(OTG->INTEN &= ~(u32Mask)))
+
+/**
+  * @brief This macro is used to get OTG related interrupt flags
+  * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
+  *                    - \ref OTG_INTSTS_ROLECHGIF_Msk
+  *                    - \ref OTG_INTSTS_VBEIF_Msk
+  *                    - \ref OTG_INTSTS_SRPFIF_Msk
+  *                    - \ref OTG_INTSTS_HNPFIF_Msk
+  *                    - \ref OTG_INTSTS_GOIDLEIF_Msk
+  *                    - \ref OTG_INTSTS_IDCHGIF_Msk
+  *                    - \ref OTG_INTSTS_PDEVIF_Msk
+  *                    - \ref OTG_INTSTS_HOSTIF_Msk
+  *                    - \ref OTG_INTSTS_BVLDCHGIF_Msk
+  *                    - \ref OTG_INTSTS_AVLDCHGIF_Msk
+  *                    - \ref OTG_INTSTS_VBCHGIF_Msk
+  *                    - \ref OTG_INTSTS_SECHGIF_Msk
+  *                    - \ref OTG_INTSTS_SRPDETIF_Msk
+  * @return Interrupt flags of selected sources.
+  * @details This macro will return OTG related interrupt flags specified by u32Mask parameter.
+  */
+#define OTG_GET_INT_FLAG(u32Mask)    (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->INTSTS & (u32Mask)):(OTG->INTSTS & (u32Mask)))
+
+/**
+  * @brief This macro is used to clear OTG related interrupt flags
+  * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
+  *                    - \ref OTG_INTSTS_ROLECHGIF_Msk
+  *                    - \ref OTG_INTSTS_VBEIF_Msk
+  *                    - \ref OTG_INTSTS_SRPFIF_Msk
+  *                    - \ref OTG_INTSTS_HNPFIF_Msk
+  *                    - \ref OTG_INTSTS_GOIDLEIF_Msk
+  *                    - \ref OTG_INTSTS_IDCHGIF_Msk
+  *                    - \ref OTG_INTSTS_PDEVIF_Msk
+  *                    - \ref OTG_INTSTS_HOSTIF_Msk
+  *                    - \ref OTG_INTSTS_BVLDCHGIF_Msk
+  *                    - \ref OTG_INTSTS_AVLDCHGIF_Msk
+  *                    - \ref OTG_INTSTS_VBCHGIF_Msk
+  *                    - \ref OTG_INTSTS_SECHGIF_Msk
+  *                    - \ref OTG_INTSTS_SRPDETIF_Msk
+  * @return None
+  * @details This macro will clear OTG related interrupt flags specified by u32Mask parameter.
+  */
+#define OTG_CLR_INT_FLAG(u32Mask)    (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->INTSTS = (u32Mask)):(OTG->INTSTS = (u32Mask)))
+
+/**
+  * @brief This macro is used to get OTG related status
+  * @param[in] u32Mask The combination of user specified source. Valid values are listed below.
+  *                    - \ref OTG_STATUS_OVERCUR_Msk
+  *                    - \ref OTG_STATUS_IDSTS_Msk
+  *                    - \ref OTG_STATUS_SESSEND_Msk
+  *                    - \ref OTG_STATUS_BVLD_Msk
+  *                    - \ref OTG_STATUS_AVLD_Msk
+  *                    - \ref OTG_STATUS_VBUSVLD_Msk
+  * @return The user specified status.
+  * @details This macro will return OTG related status specified by u32Mask parameter.
+  */
+#define OTG_GET_STATUS(u32Mask)    (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->STATUS & (u32Mask)):(OTG->STATUS & (u32Mask)))
+
+
+
+/**@}*/ /* end of group OTG_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group OTG_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __NU_OTG_H__ */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_partition_M2354.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_partition_M2354.h
new file mode 100644
index 0000000000..4de1664620
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_partition_M2354.h
@@ -0,0 +1,697 @@
+/**************************************************************************//**
+ * @file     nu_partition_M2354.h
+ * @version  V3.00
+ * @brief    TrustZone partition file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+
+#ifndef PARTITION_M2354
+#define PARTITION_M2354
+
+#if defined (__ARM_FEATURE_CMSE) &&  (__ARM_FEATURE_CMSE == 3U)
+
+/*
+   Default M2354 pritition configuration file is for non-TrustZone sample code only.
+   If user wants to use TrurstZone, they should have their partition_m2354.h.
+   For TrustZone projects, path of local partition_m2354.h should be in the
+   front of the include path list to make sure local partition_m2354.h is used.
+
+   It also apply to non-secure project of the TrustZone projects.
+
+*/
+# error "Link to default nu_partition_M2354.h in secure mode. Please check your include path."
+
+#endif
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+*/
+
+
+/*
+    SRAMNSSET
+*/
+/*
+// Bit 0..18
+//  Secure SRAM Size              <0=> 0 KB
+//                                         <0x4000=> 16KB
+//                                         <0x8000=> 32KB
+//                                         <0xc000=> 48KB
+//                                         <0x10000=> 64KB
+//                                         <0x14000=> 80KB
+//                                         <0x18000=> 96KB
+//                                         <0x1C000=> 112KB
+//                                         <0x20000=> 128KB
+//                                         <0x24000=> 144KB
+//                                         <0x28000=> 160KB
+//                                         <0x2C000=> 176KB
+//                                         <0x30000=> 192KB
+//                                         <0x34000=> 208KB
+//                                         <0x38000=> 224KB
+//                                         <0x3C000=> 240KB
+//                                         <0x40000=> 256KB
+*/
+#define SCU_SECURE_SRAM_SIZE      0x18000
+#define NON_SECURE_SRAM_BASE    (0x30000000 + SCU_SECURE_SRAM_SIZE)
+
+
+
+/*--------------------------------------------------------------------------------------------------------*/
+
+/*
+    NSBA
+*/
+#define FMC_INIT_NSBA          1
+/*
+//     Secure Flash ROM Size <0x800-0x80000:0x800>
+*/
+
+#define FMC_SECURE_ROM_SIZE      0x80000
+
+#define FMC_NON_SECURE_BASE     (0x10000000 + FMC_SECURE_ROM_SIZE)
+
+/*--------------------------------------------------------------------------------------------------------*/
+
+
+/*
+//  Peripheral Secure Attribution Configuration
+*/
+
+/*
+    PNSSET0
+*/
+/*
+// Module 0..31
+//     USBH       <0=> Secure <1=> Non-Secure
+//     SD0   <0=> Secure <1=> Non-Secure
+//     EBI    <0=> Secure <1=> Non-Secure
+//     PDMA1      <0=> Secure <1=> Non-Secure
+*/
+#define SCU_INIT_PNSSET0_VAL      0x0
+/*
+    PNSSET1
+*/
+/*
+// Module 0..31
+//     CRC       <0=> Secure <1=> Non-Secure
+//     CRPT   <0=> Secure <1=> Non-Secure
+*/
+#define SCU_INIT_PNSSET1_VAL      0x00000
+/*
+    PNSSET2
+*/
+/*
+// Module 0..31
+//     EWDT        <0=> Secure <1=> Non-Secure
+//     EADC        <0=> Secure <1=> Non-Secure
+//     ACMP01      <0=> Secure <1=> Non-Secure
+//
+//     DAC         <0=> Secure <1=> Non-Secure
+//     I2S0        <0=> Secure <1=> Non-Secure
+//     OTG        <0=> Secure <1=> Non-Secure
+//    TIMER
+//     TMR23      <0=> Secure <1=> Non-Secure
+//     TMR45      <0=> Secure <1=> Non-Secure
+//    EPWM
+//     EPWM0      <0=> Secure <1=> Non-Secure
+//     EPWM1      <0=> Secure <1=> Non-Secure
+//   
+//    BPWM
+//     BPWM0      <0=> Secure <1=> Non-Secure
+//     BPWM1      <0=> Secure <1=> Non-Secure
+//   
+*/
+#define SCU_INIT_PNSSET2_VAL      0x0
+/*
+    PNSSET3
+*/
+/*
+// Module 0..31
+//     SPI
+//     QSPI0       <0=> Secure <1=> Non-Secure
+//     SPI0   <0=> Secure <1=> Non-Secure
+//     SPI1      <0=> Secure <1=> Non-Secure
+//     SPI2    <0=> Secure <1=> Non-Secure
+//     SPI3      <0=> Secure <1=> Non-Secure
+//   
+//    UART
+//     UART0      <0=> Secure <1=> Non-Secure
+//     UART1      <0=> Secure <1=> Non-Secure
+//     UART2      <0=> Secure <1=> Non-Secure
+//     UART3      <0=> Secure <1=> Non-Secure
+//     UART4      <0=> Secure <1=> Non-Secure
+//     UART5      <0=> Secure <1=> Non-Secure
+//   
+*/
+#define SCU_INIT_PNSSET3_VAL      0x00000
+/*
+    PNSSET4
+*/
+/*
+// Module 0..31
+//    I2C
+//     I2C0       <0=> Secure <1=> Non-Secure
+//     I2C1   <0=> Secure <1=> Non-Secure
+//     I2C2      <0=> Secure <1=> Non-Secure
+//   
+//    Smart Card
+//     SC0      <0=> Secure <1=> Non-Secure
+//     SC1      <0=> Secure <1=> Non-Secure
+//     SC2      <0=> Secure <1=> Non-Secure
+//   
+*/
+#define SCU_INIT_PNSSET4_VAL      0x0
+/*
+    PNSSET5
+*/
+/*
+// Module 0..31
+//     CAN0        <0=> Secure <1=> Non-Secure
+//    QEI
+//     QEI0       <0=> Secure <1=> Non-Secure
+//     QEI1       <0=> Secure <1=> Non-Secure
+//   
+//    ECAP
+//     ECAP0      <0=> Secure <1=> Non-Secure
+//     ECAP1      <0=> Secure <1=> Non-Secure
+//   
+//     TRNG       <0=> Secure <1=> Non-Secure
+//     LCD        <0=> Secure <1=> Non-Secure
+*/
+#define SCU_INIT_PNSSET5_VAL      0x0
+/*
+    PNSSET6
+*/
+/*
+// Module 0..31
+//     USBD       <0=> Secure <1=> Non-Secure
+//    USCI
+//     USCI0   <0=> Secure <1=> Non-Secure
+//     USCI1      <0=> Secure <1=> Non-Secure
+//   
+*/
+#define SCU_INIT_PNSSET6_VAL      0x0
+/*
+// 
+*/
+
+
+/*
+//  GPIO Secure Attribution Configuration
+*/
+
+/*
+    IONSSET
+*/
+
+/*
+// Bit 0..31
+//    PA
+//     PA0       <0=> Secure <1=> Non-Secure
+//     PA1       <0=> Secure <1=> Non-Secure
+//     PA2       <0=> Secure <1=> Non-Secure
+//     PA3       <0=> Secure <1=> Non-Secure
+//     PA4       <0=> Secure <1=> Non-Secure
+//     PA5       <0=> Secure <1=> Non-Secure
+//     PA6       <0=> Secure <1=> Non-Secure
+//     PA7       <0=> Secure <1=> Non-Secure
+//     PA8       <0=> Secure <1=> Non-Secure
+//     PA9       <0=> Secure <1=> Non-Secure
+//     PA10       <0=> Secure <1=> Non-Secure
+//     PA11       <0=> Secure <1=> Non-Secure
+//     PA12       <0=> Secure <1=> Non-Secure
+//     PA13       <0=> Secure <1=> Non-Secure
+//     PA14       <0=> Secure <1=> Non-Secure
+//     PA15      <0=> Secure <1=> Non-Secure
+//   
+
+*/
+#define SCU_INIT_IONSSET0_VAL      0x00000000
+
+/*
+// Bit 0..31
+//    PB
+//     PB0       <0=> Secure <1=> Non-Secure
+//     PB1       <0=> Secure <1=> Non-Secure
+//     PB2       <0=> Secure <1=> Non-Secure
+//     PB3       <0=> Secure <1=> Non-Secure
+//     PB4       <0=> Secure <1=> Non-Secure
+//     PB5       <0=> Secure <1=> Non-Secure
+//     PB6       <0=> Secure <1=> Non-Secure
+//     PB7       <0=> Secure <1=> Non-Secure
+//     PB8       <0=> Secure <1=> Non-Secure
+//     PB9       <0=> Secure <1=> Non-Secure
+//     PB10       <0=> Secure <1=> Non-Secure
+//     PB11       <0=> Secure <1=> Non-Secure
+//     PB12       <0=> Secure <1=> Non-Secure
+//     PB13       <0=> Secure <1=> Non-Secure
+//     PB14       <0=> Secure <1=> Non-Secure
+//     PB15       <0=> Secure <1=> Non-Secure
+//   
+*/
+#define SCU_INIT_IONSSET1_VAL      0x00000000
+
+
+/*
+// Bit 0..31
+//    PC
+//     PC0       <0=> Secure <1=> Non-Secure
+//     PC1       <0=> Secure <1=> Non-Secure
+//     PC2       <0=> Secure <1=> Non-Secure
+//     PC3       <0=> Secure <1=> Non-Secure
+//     PC4       <0=> Secure <1=> Non-Secure
+//     PC5       <0=> Secure <1=> Non-Secure
+//     PC6       <0=> Secure <1=> Non-Secure
+//     PC7       <0=> Secure <1=> Non-Secure
+//     PC8       <0=> Secure <1=> Non-Secure
+//     PC9       <0=> Secure <1=> Non-Secure
+//     PC10       <0=> Secure <1=> Non-Secure
+//     PC11       <0=> Secure <1=> Non-Secure
+//     PC12       <0=> Secure <1=> Non-Secure
+//     PC13       <0=> Secure <1=> Non-Secure
+//   
+*/
+#define SCU_INIT_IONSSET2_VAL      0x00000000
+
+/*
+// Bit 0..31
+//    PD
+//     PD0       <0=> Secure <1=> Non-Secure
+//     PD1       <0=> Secure <1=> Non-Secure
+//     PD2       <0=> Secure <1=> Non-Secure
+//     PD3       <0=> Secure <1=> Non-Secure
+//     PD4       <0=> Secure <1=> Non-Secure
+//     PD5       <0=> Secure <1=> Non-Secure
+//     PD6       <0=> Secure <1=> Non-Secure
+//     PD7       <0=> Secure <1=> Non-Secure
+//     PD8       <0=> Secure <1=> Non-Secure
+//     PD9       <0=> Secure <1=> Non-Secure
+//     PD10       <0=> Secure <1=> Non-Secure
+//     PD11       <0=> Secure <1=> Non-Secure
+//     PD12       <0=> Secure <1=> Non-Secure
+//     PD14       <0=> Secure <1=> Non-Secure
+//   
+*/
+#define SCU_INIT_IONSSET3_VAL      0x00000000
+
+
+/*
+// Bit 0..31
+//    PE
+//     PE0       <0=> Secure <1=> Non-Secure
+//     PE1       <0=> Secure <1=> Non-Secure
+//     PE2       <0=> Secure <1=> Non-Secure
+//     PE3       <0=> Secure <1=> Non-Secure
+//     PE4       <0=> Secure <1=> Non-Secure
+//     PE5       <0=> Secure <1=> Non-Secure
+//     PE6       <0=> Secure <1=> Non-Secure
+//     PE7       <0=> Secure <1=> Non-Secure
+//     PE8       <0=> Secure <1=> Non-Secure
+//     PE9       <0=> Secure <1=> Non-Secure
+//     PE10       <0=> Secure <1=> Non-Secure
+//     PE11       <0=> Secure <1=> Non-Secure
+//     PE12       <0=> Secure <1=> Non-Secure
+//     PE13       <0=> Secure <1=> Non-Secure
+//     PE14       <0=> Secure <1=> Non-Secure
+//     PE15       <0=> Secure <1=> Non-Secure
+//   
+*/
+#define SCU_INIT_IONSSET4_VAL      0x00000000
+
+
+/*
+// Bit 0..31
+//    PF
+//     PF0       <0=> Secure <1=> Non-Secure
+//     PF1       <0=> Secure <1=> Non-Secure
+//     PF2       <0=> Secure <1=> Non-Secure
+//     PF3       <0=> Secure <1=> Non-Secure
+//     PF4       <0=> Secure <1=> Non-Secure
+//     PF5       <0=> Secure <1=> Non-Secure
+//     PF6       <0=> Secure <1=> Non-Secure
+//     PF7       <0=> Secure <1=> Non-Secure
+//     PF8       <0=> Secure <1=> Non-Secure
+//     PF9       <0=> Secure <1=> Non-Secure
+//     PF10       <0=> Secure <1=> Non-Secure
+//     PF11       <0=> Secure <1=> Non-Secure
+//   
+*/
+#define SCU_INIT_IONSSET5_VAL      0x00000000
+
+
+/*
+// Bit 0..31
+//    PG
+//     PG2       <0=> Secure <1=> Non-Secure
+//     PG3       <0=> Secure <1=> Non-Secure
+//     PG4       <0=> Secure <1=> Non-Secure
+//     PG9       <0=> Secure <1=> Non-Secure
+//     PG10       <0=> Secure <1=> Non-Secure
+//     PG11       <0=> Secure <1=> Non-Secure
+//     PG12       <0=> Secure <1=> Non-Secure
+//     PG13       <0=> Secure <1=> Non-Secure
+//     PG14       <0=> Secure <1=> Non-Secure
+//     PG15       <0=> Secure <1=> Non-Secure
+//   
+*/
+#define SCU_INIT_IONSSET6_VAL      0x00000000
+
+/*
+// Bit 0..31
+//    PH
+//     PH4       <0=> Secure <1=> Non-Secure
+//     PH5       <0=> Secure <1=> Non-Secure
+//     PH6       <0=> Secure <1=> Non-Secure
+//     PH7       <0=> Secure <1=> Non-Secure
+//     PH8       <0=> Secure <1=> Non-Secure
+//     PH9       <0=> Secure <1=> Non-Secure
+//     PH10       <0=> Secure <1=> Non-Secure
+//     PH11       <0=> Secure <1=> Non-Secure
+//   
+*/
+#define SCU_INIT_IONSSET7_VAL      0x00000000
+
+/*
+// 
+*/
+
+
+
+/*
+// Assign GPIO Interrupt to Secure or Non-secure Vector
+*/
+
+
+/*
+    Initialize GPIO ITNS (Interrupts 0..31)
+*/
+
+/*
+// Bit 0..31
+//     GPA         <0=> Secure <1=> Non-Secure
+//     GPB         <0=> Secure <1=> Non-Secure
+//     GPC         <0=> Secure <1=> Non-Secure
+//     GPD         <0=> Secure <1=> Non-Secure
+//     GPE         <0=> Secure <1=> Non-Secure
+//     GPF         <0=> Secure <1=> Non-Secure
+//     GPG         <0=> Secure <1=> Non-Secure
+//     GPH         <0=> Secure <1=> Non-Secure
+//     EINT0         <0=> Secure <1=> Non-Secure
+//     EINT1         <0=> Secure <1=> Non-Secure
+//     EINT2         <0=> Secure <1=> Non-Secure
+//     EINT3         <0=> Secure <1=> Non-Secure
+//     EINT4         <0=> Secure <1=> Non-Secure
+//     EINT5         <0=> Secure <1=> Non-Secure
+//     EINT6         <0=> Secure <1=> Non-Secure
+//     EINT7         <0=> Secure <1=> Non-Secure
+*/
+#define SCU_INIT_IONSSET_VAL      0x0000
+/*
+// 
+*/
+
+
+
+/* ---------------------------------------------------------------------------------------------------- */
+
+/*
+// Secure Attribute Unit (SAU) Control
+*/
+#define SAU_INIT_CTRL 0
+
+/*
+//    Enable SAU
+//    To enable Secure Attribute Unit (SAU).
+*/
+#define SAU_INIT_CTRL_ENABLE 1
+
+/*
+//    All Memory Attribute When SAU is disabled
+//     <0=> All Memory is Secure
+//     <1=> All Memory is Non-Secure
+//    To set the ALLNS bit in SAU CTRL.
+//    When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
+*/
+#define SAU_INIT_CTRL_ALLNS  0
+
+/*
+// 
+*/
+
+
+/*
+// Enable and Set Secure/Non-Secure region
+*/
+#define SAU_REGIONS_MAX   8                 /* Max. number of SAU regions */
+
+/*
+//   SAU Region 0
+//    Setup SAU Region 0
+*/
+#define SAU_INIT_REGION0    0
+/*
+//     Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START0     0x0003F000      /* start address of SAU region 0 */
+/*
+//     End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END0       0x0003FFFF      /* end address of SAU region 0 */
+/*
+//     Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC0       1
+/*
+//   
+*/
+
+/*
+//   SAU Region 1
+//    Setup SAU Region 1
+*/
+#define SAU_INIT_REGION1    0
+/*
+//     Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START1     0x10040000
+/*
+//     End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END1       0x1007FFFF
+/*
+//     Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC1       0
+/*
+//   
+*/
+
+/*
+//   SAU Region 2
+//    Setup SAU Region 2
+*/
+#define SAU_INIT_REGION2    0
+/*
+//     Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START2     0x2000F000
+/*
+//     End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END2       0x2000FFFF
+/*
+//     Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC2       1
+/*
+//   
+*/
+
+/*
+//   SAU Region 3
+//    Setup SAU Region 3
+*/
+#define SAU_INIT_REGION3    0
+/*
+//     Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START3     0x3f000
+/*
+//     End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END3       0x3f7ff
+/*
+//     Region is
+//         <0=>Non-Secure
+//         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC3       1
+/*
+//   
+*/
+
+/*
+   SAU Region 4
+    Setup SAU Region 4
+*/
+#define SAU_INIT_REGION4    1
+/*
+     Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START4     FMC_NON_SECURE_BASE      /* start address of SAU region 4 */
+
+/*
+     End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END4       0x1007FFFF      /* end address of SAU region 4 */
+
+/*
+     Region is
+         <0=>Non-Secure
+         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC4       0
+/*
+   
+*/
+
+/*
+   SAU Region 5
+    Setup SAU Region 5
+*/
+#define SAU_INIT_REGION5    1
+
+/*
+     Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START5     0x00807E00
+
+/*
+     End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END5       0x00807FFF
+
+/*
+     Region is
+         <0=>Non-Secure
+         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC5       1
+/*
+   
+*/
+
+/*
+   SAU Region 6
+    Setup SAU Region 6
+*/
+#define SAU_INIT_REGION6    1
+
+/*
+     Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START6     NON_SECURE_SRAM_BASE
+
+/*
+     End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END6       0x30017FFF
+
+/*
+     Region is
+         <0=>Non-Secure
+         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC6       0
+/*
+   
+*/
+
+/*
+   SAU Region 7
+    Setup SAU Region 7
+*/
+#define SAU_INIT_REGION7    1
+
+/*
+     Start Address <0-0xFFFFFFE0>
+*/
+#define SAU_INIT_START7     0x50000000
+
+/*
+     End Address <0x1F-0xFFFFFFFF>
+*/
+#define SAU_INIT_END7       0x5FFFFFFF
+
+/*
+     Region is
+         <0=>Non-Secure
+         <1=>Secure, Non-Secure Callable
+*/
+#define SAU_INIT_NSC7       0
+/*
+   
+*/
+
+/*
+// 
+*/
+
+/*
+// Setup behavior of Sleep and Exception Handling
+*/
+#define SCB_CSR_AIRCR_INIT  1
+
+/*
+//    Deep Sleep can be enabled by
+//     <0=>Secure and Non-Secure state
+//     <1=>Secure state only
+//    Value for SCB->CSR register bit DEEPSLEEPS
+*/
+#define SCB_CSR_DEEPSLEEPS_VAL  0
+
+/*
+//   System reset request accessible from
+//     <0=> Secure and Non-Secure state
+//     <1=> Secure state only
+//    Value for SCB->AIRCR register bit SYSRESETREQS
+*/
+#define SCB_AIRCR_SYSRESETREQS_VAL  0
+
+/*
+//   Priority of Non-Secure exceptions is
+//     <0=> Not altered
+//     <1=> Lowered to 0x80-0xFF
+//    Value for SCB->AIRCR register bit PRIS
+*/
+#define SCB_AIRCR_PRIS_VAL      0
+
+/* Assign HardFault to be always secure for safe */
+#define SCB_AIRCR_BFHFNMINS_VAL 0
+
+/*
+// 
+*/
+
+/*
+    max 128 SAU regions.
+    SAU regions are defined in partition.h
+ */
+
+#define SAU_INIT_REGION(n) \
+    SAU->RNR  =  (n                                     & SAU_RNR_REGION_Msk); \
+    SAU->RBAR =  (SAU_INIT_START##n                     & SAU_RBAR_BADDR_Msk); \
+    SAU->RLAR =  (SAU_INIT_END##n                       & SAU_RLAR_LADDR_Msk) | \
+                ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos)  & SAU_RLAR_NSC_Msk)   | 1U
+
+
+#endif  /* PARTITION_M2354 */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_pdma.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_pdma.h
new file mode 100644
index 0000000000..0d4947e783
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_pdma.h
@@ -0,0 +1,380 @@
+/**************************************************************************//**
+ * @file     nu_pdma.h
+ * @version  V3.00
+ * @brief    M2354 series PDMA driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_PDMA_H__
+#define __NU_PDMA_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup PDMA_Driver PDMA Driver
+  @{
+*/
+
+/** @addtogroup PDMA_EXPORTED_CONSTANTS PDMA Exported Constants
+  @{
+*/
+#define PDMA_CH_MAX    8UL   /*!< Specify Maximum Channels of PDMA  \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Operation Mode Constant Definitions                                                                    */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PDMA_OP_STOP        0x00000000UL            /*!INTSTS))
+
+/**
+ * @brief       Get Transfer Done Interrupt Status
+ *
+ * @param[in]   pdma        The pointer of the specified PDMA module
+ *
+ * @return      None
+ *
+ * @details     Get the transfer done Interrupt status.
+ */
+#define PDMA_GET_TD_STS(pdma) ((uint32_t)((pdma)->TDSTS))
+
+/**
+ * @brief       Clear Transfer Done Interrupt Status
+ *
+ * @param[in]   pdma        The pointer of the specified PDMA module
+ * @param[in]   u32Mask     The channel mask
+ *
+ * @return      None
+ *
+ * @details     Clear the transfer done Interrupt status.
+ */
+#define PDMA_CLR_TD_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->TDSTS = (u32Mask)))
+
+/**
+ * @brief       Get Target Abort Interrupt Status
+ *
+ * @param[in]   pdma        The pointer of the specified PDMA module
+ *
+ * @return      None
+ *
+ * @details     Get the target abort Interrupt status.
+ */
+#define PDMA_GET_ABORT_STS(pdma) ((uint32_t)((pdma)->ABTSTS))
+
+/**
+ * @brief       Clear Target Abort Interrupt Status
+ *
+ * @param[in]   pdma        The pointer of the specified PDMA module
+ * @param[in]   u32Mask     The channel mask
+ *
+ * @return      None
+ *
+ * @details     Clear the target abort Interrupt status.
+ */
+#define PDMA_CLR_ABORT_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->ABTSTS = (u32Mask)))
+
+/**
+ * @brief       Get PDMA Transfer Alignment Status
+ *
+ * @param[in]   pdma        The pointer of the specified PDMA module
+ *
+ * @return      None
+ *
+ * @details     Get the PDMA transfer alignment status.
+ */
+#define PDMA_GET_ALIGN_STS(pdma) ((uint32_t)((pdma)->ALIGN))
+
+/**
+ * @brief       Clear PDMA Transfer Alignment Interrupt Status
+ *
+ * @param[in]   pdma        The pointer of the specified PDMA module
+ * @param[in]   u32Mask     The channel mask
+ *
+ * @return      None
+ *
+ * @details     Clear the PDMA transfer alignment Interrupt status.
+ */
+#define PDMA_CLR_ALIGN_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->ALIGN = (u32Mask)))
+
+/**
+ * @brief       Clear Timeout Interrupt Status
+ *
+ * @param[in]   pdma        The pointer of the specified PDMA module
+ * @param[in]   u32Ch       The selected channel
+ *
+ * @return      None
+ *
+ * @details     Clear the selected channel timeout interrupt status.
+ * @note        This function is only supported in channel 0 and channel 1.
+ */
+#define PDMA_CLR_TMOUT_FLAG(pdma, u32Ch) ((uint32_t)((pdma)->INTSTS = (1UL << ((u32Ch) + 8UL))))
+
+/**
+ * @brief       Check Channel Status
+ *
+ * @param[in]   pdma        The pointer of the specified PDMA module
+ * @param[in]   u32Ch       The selected channel
+ *
+ * @retval      0 Idle state
+ * @retval      1 Busy state
+ *
+ * @details     Check the selected channel is busy or not.
+ */
+#define PDMA_IS_CH_BUSY(pdma, u32Ch) ((uint32_t)((pdma)->TRGSTS & (1UL << (u32Ch)))? 1 : 0)
+
+/**
+ * @brief       Set Source Address
+ *
+ * @param[in]   pdma        The pointer of the specified PDMA module
+ * @param[in]   u32Ch       The selected channel
+ * @param[in]   u32Addr     The selected address
+ *
+ * @return      None
+ *
+ * @details     This macro set the selected channel source address.
+ */
+#define PDMA_SET_SRC_ADDR(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].SA = (u32Addr)))
+
+/**
+ * @brief       Set Destination Address
+ *
+ * @param[in]   pdma        The pointer of the specified PDMA module
+ * @param[in]   u32Ch       The selected channel
+ * @param[in]   u32Addr     The selected address
+ *
+ * @return      None
+ *
+ * @details     This macro set the selected channel destination address.
+ */
+#define PDMA_SET_DST_ADDR(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].DA = (u32Addr)))
+
+/**
+ * @brief       Set Transfer Count
+ *
+ * @param[in]   pdma           The pointer of the specified PDMA module
+ * @param[in]   u32Ch          The selected channel
+ * @param[in]   u32TransCount  Transfer Count
+ *
+ * @return      None
+ *
+ * @details     This macro set the selected channel transfer count.
+ */
+#define PDMA_SET_TRANS_CNT(pdma, u32Ch, u32TransCount) ((uint32_t)((pdma)->DSCT[(u32Ch)].CTL=((pdma)->DSCT[(u32Ch)].CTL&~PDMA_DSCT_CTL_TXCNT_Msk)|(((u32TransCount)-1UL) << PDMA_DSCT_CTL_TXCNT_Pos)))
+
+/**
+ * @brief       Set Scatter-gather descriptor Address
+ *
+ * @param[in]   pdma        The pointer of the specified PDMA module
+ * @param[in]   u32Ch       The selected channel
+ * @param[in]   u32Addr     The descriptor address
+ *
+ * @return      None
+ *
+ * @details     This macro set the selected channel scatter-gather descriptor address.
+ */
+#define PDMA_SET_SCATTER_DESC(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].NEXT = (u32Addr) - ((pdma)->SCATBA)))
+
+/**
+ * @brief       Stop the channel
+ *
+ * @param[in]   pdma        The pointer of the specified PDMA module
+ * @param[in]   u32Ch       The selected channel
+ *
+ * @return      None
+ *
+ * @details     This macro stop the selected channel.
+ */
+#define PDMA_STOP(pdma, u32Ch) ((uint32_t)((pdma)->PAUSE = (1UL << (u32Ch))))
+
+/**
+ * @brief       Pause the channel
+ *
+ * @param[in]   pdma        The pointer of the specified PDMA module
+ * @param[in]   u32Ch       The selected channel
+ *
+ * @return      None
+ *
+ * @details     This macro pause the selected channel.
+ */
+#define PDMA_PAUSE(pdma, u32Ch) ((uint32_t)((pdma)->PAUSE = (1UL << (u32Ch))))
+
+/**
+ * @brief       Reset the channel
+ *
+ * @param[in]   pdma        The pointer of the specified PDMA module
+ * @param[in]   u32Ch       The selected channel
+ *
+ * @return      None
+ *
+ * @details     This macro reset the selected channel.
+ */
+#define PDMA_RESET(pdma, u32Ch) ((uint32_t)((pdma)->CHRST = (1UL << (u32Ch))))
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* Define PWM functions prototype                                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+void PDMA_Open(PDMA_T *pdma, uint32_t u32Mask);
+void PDMA_Close(PDMA_T *pdma);
+void PDMA_SetTransferCnt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount);
+void PDMA_SetStride(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount);
+void PDMA_SetRepeat(PDMA_T * pdma, uint32_t u32Ch, uint32_t u32DestInterval, uint32_t u32SrcInterval, uint32_t u32RepeatCount);
+void PDMA_SetTransferAddr(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl);
+void PDMA_SetTransferMode(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr);
+void PDMA_SetBurstType(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize);
+void PDMA_EnableTimeout(PDMA_T *pdma, uint32_t u32Mask);
+void PDMA_DisableTimeout(PDMA_T *pdma, uint32_t u32Mask);
+void PDMA_SetTimeOut(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt);
+void PDMA_Trigger(PDMA_T *pdma, uint32_t u32Ch);
+void PDMA_EnableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask);
+void PDMA_DisableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask);
+
+
+/**@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group PDMA_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_PDMA_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_plm.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_plm.h
new file mode 100644
index 0000000000..e1320d37e4
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_plm.h
@@ -0,0 +1,95 @@
+/**************************************************************************//**
+ * @file     nu_plm.h
+ * @version  V3.00
+ * @brief    Product life cycle management
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_PLM_H__
+#define __NU_PLM_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup PLM_Driver PLM Driver
+  @{
+*/
+
+/** @addtogroup PLM_EXPORTED_CONSTANTS PLM Exported Constants
+  @{
+*/
+
+typedef enum
+{
+    PLM_VENDOR = 0,
+    PLM_OEM = 1,
+    PLM_DEPLOYED = 3,
+    PLM_RMA = 7
+} PLM_STAGE_T;
+
+#define PLM_VCODE   (0x475A0000ul)  /*!< The key code for PLM_CTL write. */
+
+/**@}*/ /* end of group FVC_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup FVC_EXPORTED_FUNCTIONS FVC Exported Functions
+  @{
+*/
+
+
+/**
+  * @brief      Get product life-cycle stage
+  * @return     Current stage of PLM
+  * @details    This function is used to Get PLM stage.
+  */
+#define PLM_GetStage()  (PLM->STS & PLM_STS_STAGE_Msk)
+
+
+/**
+  * @brief      Set product life-cycle stage
+  * @param[in]  stage   Product life-cycle stage. It could be:
+  *                     \ref PLM_VENDOR
+  *                     \ref PLM_OEM
+  *                     \ref PLM_DEPLOYED
+  *                     \ref PLM_RMA
+  * @retval     0   Successful
+  * @retval     -1  Failed
+  * @details    This function is used to set PLM stage. It could be only be VENDOR, OEM, DEPLOYED and RMA.
+  *             The setting of PLM cannot be rollback.
+  */
+__STATIC_INLINE int32_t PLM_SetStage(PLM_STAGE_T stage)
+{
+
+    /* Do nothing when stage is not changed */
+    if(PLM_GetStage() == stage)
+        return 0;
+
+    PLM->CTL = PLM_VCODE | (stage);
+
+    /* The dirty flag should be set when PLM stage set successfully. */
+    if(PLM->STS & PLM_STS_DIRTY_Msk)
+        return -1;
+
+    return 0;
+}
+
+/**@}*/ /* end of group PLM_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group PLM_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_PLM_H__ */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_qei.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_qei.h
new file mode 100644
index 0000000000..c8a16d340b
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_qei.h
@@ -0,0 +1,388 @@
+/**************************************************************************//**
+ * @file     nu_qei.h
+ * @version  V3.00
+ * @brief    Quadrature Encoder Interface (QEI) driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_QEI_H__
+#define __NU_QEI_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup QEI_Driver QEI Driver
+  @{
+*/
+
+/** @addtogroup QEI_EXPORTED_CONSTANTS QEI Exported Constants
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* QEI counting mode selection constants definitions                                                       */
+/*---------------------------------------------------------------------------------------------------------*/
+#define QEI_CTL_X4_FREE_COUNTING_MODE       (0x0<CTL &= (~QEI_CTL_CMPEN_Msk))
+
+/**
+  * @brief      Enable QEI compare function
+  * @param[in]  qei     The pointer of the specified QEI module.
+  * @return     None
+  * @details    This macro enable QEI counter compare function.
+  * \hideinitializer
+  */
+#define QEI_ENABLE_CNT_CMP(qei)     ((qei)->CTL |= QEI_CTL_CMPEN_Msk)
+
+/**
+  * @brief      Disable QEI index latch function
+  * @param[in]  qei     The pointer of the specified QEI module.
+  * @return     None
+  * @details    This macro disable QEI index trigger counter latch function.
+  * \hideinitializer
+  */
+#define QEI_DISABLE_INDEX_LATCH(qei)     ((qei)->CTL &= (~QEI_CTL_IDXLATEN_Msk))
+
+/**
+  * @brief      Enable QEI index latch function
+  * @param[in]  qei     The pointer of the specified QEI module.
+  * @return     None
+  * @details    This macro enable QEI index trigger counter latch function.
+  * \hideinitializer
+  */
+#define QEI_ENABLE_INDEX_LATCH(qei)     ((qei)->CTL |= QEI_CTL_IDXLATEN_Msk)
+
+/**
+  * @brief      Disable QEI index reload function
+  * @param[in]  qei     The pointer of the specified QEI module.
+  * @return     None
+  * @details    This macro disable QEI index trigger counter reload function.
+  * \hideinitializer
+  */
+#define QEI_DISABLE_INDEX_RELOAD(qei)    ((qei)->CTL &= (~QEI_CTL_IDXRLDEN_Msk))
+
+/**
+  * @brief      Enable QEI index reload function
+  * @param[in]  qei     The pointer of the specified QEI module.
+  * @return     None
+  * @details    This macro enable QEI index trigger counter reload function.
+  * \hideinitializer
+  */
+#define QEI_ENABLE_INDEX_RELOAD(qei)    ((qei)->CTL |= QEI_CTL_IDXRLDEN_Msk)
+
+/**
+  * @brief      Disable QEI input
+  * @param[in]  qei             The pointer of the specified QEI module.
+  * @param[in]  u32InputType    Input signal type.
+  *                             - \ref QEI_CTL_CHAEN_Msk    : QEA input
+  *                             - \ref QEI_CTL_CHAEN_Msk    : QEB input
+  *                             - \ref QEI_CTL_IDXEN_Msk    : IDX input
+  * @return     None
+  * @details    This macro disable specified QEI signal input.
+  * \hideinitializer
+  */
+#define QEI_DISABLE_INPUT(qei, u32InputType)     ((qei)->CTL &= ~(u32InputType))
+
+/**
+  * @brief      Enable QEI input
+  * @param[in]  qei             The pointer of the specified QEI module.
+  * @param[in]  u32InputType    Input signal type .
+  *                             - \ref QEI_CTL_CHAEN_Msk    : QEA input
+  *                             - \ref QEI_CTL_CHBEN_Msk    : QEB input
+  *                             - \ref QEI_CTL_IDXEN_Msk    : IDX input
+  * @return     None
+  * @details    This macro enable specified QEI signal input.
+  * \hideinitializer
+  */
+#define QEI_ENABLE_INPUT(qei, u32InputType)     ((qei)->CTL |= (u32InputType))
+
+/**
+  * @brief      Disable inverted input polarity
+  * @param[in]  qei             The pointer of the specified QEI module.
+  * @param[in]  u32InputType    Input signal type .
+  *                             - \ref QEI_CTL_CHAINV_Msk   : QEA Input
+  *                             - \ref QEI_CTL_CHBINV_Msk   : QEB Input
+  *                             - \ref QEI_CTL_IDXINV_Msk   : IDX Input
+  * @return     None
+  * @details    This macro disable specified QEI signal inverted input polarity.
+  * \hideinitializer
+  */
+#define QEI_DISABLE_INPUT_INV(qei, u32InputType)    ((qei)->CTL &= ~(u32InputType))
+
+/**
+  * @brief      Enable inverted input polarity
+  * @param[in]  qei             The pointer of the specified QEI module.
+  * @param[in]  u32InputType    Input signal type.
+  *                             - \ref QEI_CTL_CHAINV_Msk   : QEA Input
+  *                             - \ref QEI_CTL_CHBINV_Msk   : QEB Input
+  *                             - \ref QEI_CTL_IDXINV_Msk   : IDX Input
+  * @return     None
+  * @details    This macro inverse specified QEI signal input polarity.
+  * \hideinitializer
+  */
+#define QEI_ENABLE_INPUT_INV(qei, u32InputType)     ((qei)->CTL |= (u32InputType))
+
+/**
+  * @brief      Disable QEI interrupt
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @param[in]  u32IntSel   Interrupt type selection.
+  *                         - \ref QEI_CTL_DIRIEN_Msk   : Direction change interrupt
+  *                         - \ref QEI_CTL_OVUNIEN_Msk  : Counter overflow or underflow interrupt
+  *                         - \ref QEI_CTL_CMPIEN_Msk   : Compare-match interrupt
+  *                         - \ref QEI_CTL_IDXIEN_Msk   : Index detected interrupt
+  * @return     None
+  * @details    This macro disable specified QEI interrupt.
+  * \hideinitializer
+  */
+#define QEI_DISABLE_INT(qei, u32IntSel)     ((qei)->CTL &= ~(u32IntSel))
+
+/**
+  * @brief      Enable QEI interrupt
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @param[in]  u32IntSel   Interrupt type selection.
+  *                         - \ref QEI_CTL_DIRIEN_Msk   : Direction change interrupt
+  *                         - \ref QEI_CTL_OVUNIEN_Msk  : Counter overflow or underflow interrupt
+  *                         - \ref QEI_CTL_CMPIEN_Msk   : Compare-match interrupt
+  *                         - \ref QEI_CTL_IDXIEN_Msk   : Index detected interrupt
+  * @return     None
+  * @details    This macro enable specified QEI interrupt.
+  * \hideinitializer
+  */
+#define QEI_ENABLE_INT(qei, u32IntSel)      ((qei)->CTL |= (u32IntSel))
+
+/**
+  * @brief      Disable QEI noise filter
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @return     None
+  * @details    This macro disable QEI noise filter function.
+  * \hideinitializer
+  */
+#define QEI_DISABLE_NOISE_FILTER(qei)       ((qei)->CTL |= QEI_CTL_NFDIS_Msk)
+
+/**
+  * @brief      Enable QEI noise filter
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @param[in]  u32ClkSel   The sampling frequency of the noise filter clock.
+  *                         - \ref QEI_CTL_NFCLKSEL_DIV1
+  *                         - \ref QEI_CTL_NFCLKSEL_DIV2
+  *                         - \ref QEI_CTL_NFCLKSEL_DIV4
+  *                         - \ref QEI_CTL_NFCLKSEL_DIV16
+  *                         - \ref QEI_CTL_NFCLKSEL_DIV32
+  *                         - \ref QEI_CTL_NFCLKSEL_DIV64
+  * @return     None
+  * @details    This macro enable QEI noise filter function and select noise filter clock.
+  * \hideinitializer
+  */
+#define QEI_ENABLE_NOISE_FILTER(qei, u32ClkSel)     ((qei)->CTL = ((qei)->CTL & (~(QEI_CTL_NFDIS_Msk|QEI_CTL_NFCLKSEL_Msk))) | (u32ClkSel))
+
+/**
+  * @brief      Get QEI counter value
+  * @param[in]  qei     The pointer of the specified QEI module.
+  * @return     QEI pulse counter register value.
+  * @details    This macro get QEI pulse counter value.
+  * \hideinitializer
+  */
+#define QEI_GET_CNT_VALUE(qei)      ((qei)->CNT)
+
+/**
+  * @brief      Get QEI counting direction
+  * @param[in]  qei     The pointer of the specified QEI module.
+  * @retval     0       QEI counter is in down-counting.
+  * @retval     1       QEI counter is in up-counting.
+  * @details    This macro get QEI counting direction.
+  * \hideinitializer
+  */
+#define QEI_GET_DIR(qei)    (((qei)->STATUS & (QEI_STATUS_DIRF_Msk))?1:0)
+
+/**
+  * @brief      Get QEI counter hold value
+  * @param[in]  qei     The pointer of the specified QEI module.
+  * @return     QEI pulse counter hold register value.
+  * @details    This macro get QEI pulse counter hold value, which is updated with counter value in hold counter value control.
+  * \hideinitializer
+  */
+#define QEI_GET_HOLD_VALUE(qei)     ((qei)->CNTHOLD)
+
+/**
+  * @brief      Get QEI counter index latch value
+  * @param[in]  qei     The pointer of the specified QEI module.
+  * @return     QEI pulse counter index latch value
+  * @details    This macro get QEI pulse counter index latch value, which is updated with counter value when the index is detected.
+  * \hideinitializer
+  */
+#define QEI_GET_INDEX_LATCH_VALUE(qei)     ((qei)->CNTLATCH)
+
+/**
+  * @brief      Set QEI counter index latch value
+  * @param[in]  qei     The pointer of the specified QEI module.
+  * @param[in]  u32Val  The latch value.
+  * @return     QEI pulse counter index latch value
+  * @details    This macro set QEI pulse counter index latch value, which is updated with counter value when the index is detected.
+  * \hideinitializer
+  */
+#define QEI_SET_INDEX_LATCH_VALUE(qei,u32Val)     ((qei)->CNTLATCH = (u32Val))
+
+/**
+  * @brief      Get QEI interrupt flag status
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @param[in]  u32IntSel   Interrupt type selection.
+*                           - \ref QEI_STATUS_DIRF_Msk      : Counting direction flag
+  *                         - \ref QEI_STATUS_DIRCHGF_Msk   : Direction change flag
+  *                         - \ref QEI_STATUS_OVUNF_Msk     : Counter overflow or underflow flag
+  *                         - \ref QEI_STATUS_CMPF_Msk      : Compare-match flag
+  *                         - \ref QEI_STATUS_IDXF_Msk      : Index detected flag
+  * @retval     0           QEI specified interrupt flag is not set.
+  * @retval     1           QEI specified interrupt flag is set.
+  * @details    This macro get QEI specified interrupt flag status.
+  * \hideinitializer
+  */
+#define QEI_GET_INT_FLAG(qei, u32IntSel)        (((qei)->STATUS & (u32IntSel))?1:0)
+
+
+/**
+  * @brief      Clear QEI interrupt flag
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @param[in]  u32IntSel   Interrupt type selection.
+  *                         - \ref QEI_STATUS_DIRCHGF_Msk   : Direction change flag
+  *                         - \ref QEI_STATUS_OVUNF_Msk     : Counter overflow or underflow flag
+  *                         - \ref QEI_STATUS_CMPF_Msk      : Compare-match flag
+  *                         - \ref QEI_STATUS_IDXF_Msk      : Index detected flag
+  * @return     None
+  * @details    This macro clear QEI specified interrupt flag.
+  * \hideinitializer
+  */
+#define QEI_CLR_INT_FLAG(qei, u32IntSel)     ((qei)->STATUS = (u32IntSel))
+
+/**
+  * @brief      Set QEI counter compare value
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @param[in]  u32Value    The counter compare value.
+  * @return     None
+  * @details    This macro set QEI pulse counter compare value.
+  * \hideinitializer
+  */
+#define QEI_SET_CNT_CMP(qei, u32Value)      ((qei)->CNTCMP = (u32Value))
+
+/**
+  * @brief      Set QEI counter value
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @param[in]  u32Value    The counter compare value.
+  * @return     None
+  * @details    This macro set QEI pulse counter value.
+  * \hideinitializer
+  */
+#define QEI_SET_CNT_VALUE(qei, u32Value)      ((qei)->CNT = (u32Value))
+
+/**
+  * @brief      Enable QEI counter hold mode
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @param[in]  u32Type     The triggered type.
+  *                         - \ref QEI_CTL_HOLDCNT_Msk      : Hold QEI_CNT control
+  *                         - \ref QEI_CTL_HOLDTMR0_Msk     : Hold QEI_CNT by Timer0
+  *                         - \ref QEI_CTL_HOLDTMR1_Msk     : Hold QEI_CNT by Timer1
+  *                         - \ref QEI_CTL_HOLDTMR2_Msk     : Hold QEI_CNT by Timer2
+  *                         - \ref QEI_CTL_HOLDTMR3_Msk     : Hold QEI_CNT by Timer3
+  * @return     None
+  * @details    This macro enable QEI counter hold mode.
+  * \hideinitializer
+  */
+#define QEI_ENABLE_HOLD_TRG_SRC(qei, u32Type)      ((qei)->CTL |= (u32Type))
+
+/**
+  * @brief      Disable QEI counter hold mode
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @param[in]  u32Type     The triggered type.
+  *                         - \ref QEI_CTL_HOLDCNT_Msk      : Hold QEI_CNT control
+  *                         - \ref QEI_CTL_HOLDTMR0_Msk     : Hold QEI_CNT by Timer0
+  *                         - \ref QEI_CTL_HOLDTMR1_Msk     : Hold QEI_CNT by Timer1
+  *                         - \ref QEI_CTL_HOLDTMR2_Msk     : Hold QEI_CNT by Timer2
+  *                         - \ref QEI_CTL_HOLDTMR3_Msk     : Hold QEI_CNT by Timer3
+  * @return     None
+  * @details    This macro disable QEI counter hold mode.
+  * \hideinitializer
+  */
+#define QEI_DISABLE_HOLD_TRG_SRC(qei, u32Type)      ((qei)->CTL &= ~(u32Type))
+
+/**
+  * @brief      Set QEI maximum count value
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @param[in]  u32Value    The counter maximum value.
+  * @return     QEI maximum count value
+  * @details    This macro set QEI maximum count value.
+  * \hideinitializer
+  */
+#define QEI_SET_CNT_MAX(qei, u32Value)      ((qei)->CNTMAX = (u32Value))
+
+/**
+  * @brief      Set QEI counting mode
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @param[in]  u32Mode     QEI counting mode.
+  *                         - \ref QEI_CTL_X4_FREE_COUNTING_MODE
+  *                         - \ref QEI_CTL_X2_FREE_COUNTING_MODE
+  *                         - \ref QEI_CTL_X4_COMPARE_COUNTING_MODE
+  *                         - \ref QEI_CTL_X2_COMPARE_COUNTING_MODE
+  * @return     None
+  * @details    This macro set QEI counting mode.
+  * \hideinitializer
+  */
+#define QEI_SET_CNT_MODE(qei, u32Mode)       ((qei)->CTL = ((qei)->CTL & (~QEI_CTL_MODE_Msk)) | (u32Mode))
+
+
+void QEI_Close(QEI_T* qei);
+void QEI_DisableInt(QEI_T* qei, uint32_t u32IntSel);
+void QEI_EnableInt(QEI_T* qei, uint32_t u32IntSel);
+void QEI_Open(QEI_T* qei, uint32_t u32Mode, uint32_t u32Value);
+void QEI_Start(QEI_T* qei);
+void QEI_Stop(QEI_T* qei);
+
+
+/**@}*/ /* end of group QEI_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group QEI_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__NU_QEI_H__*/
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_qspi.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_qspi.h
new file mode 100644
index 0000000000..cff6014861
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_qspi.h
@@ -0,0 +1,399 @@
+/******************************************************************************
+ * @file     nu_qspi.h
+ * @version  V3.00
+ * @brief    M2354 series QSPI driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_QSPI_H__
+#define __NU_QSPI_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup QSPI_Driver QSPI Driver
+  @{
+*/
+
+/** @addtogroup QSPI_EXPORTED_CONSTANTS QSPI Exported Constants
+  @{
+*/
+
+#define QSPI_MODE_0        (QSPI_CTL_TXNEG_Msk)                             /*!< CLKPOL=0; RXNEG=0; TXNEG=1 */
+#define QSPI_MODE_1        (QSPI_CTL_RXNEG_Msk)                             /*!< CLKPOL=0; RXNEG=1; TXNEG=0 */
+#define QSPI_MODE_2        (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_RXNEG_Msk)       /*!< CLKPOL=1; RXNEG=1; TXNEG=0 */
+#define QSPI_MODE_3        (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_TXNEG_Msk)       /*!< CLKPOL=1; RXNEG=0; TXNEG=1 */
+
+#define QSPI_SLAVE         (QSPI_CTL_SLAVE_Msk)                             /*!< Set as slave */
+#define QSPI_MASTER        (0x0UL)                                          /*!< Set as master */
+
+#define QSPI_SS                (QSPI_SSCTL_SS_Msk)                          /*!< Set SS */
+#define QSPI_SS_ACTIVE_HIGH    (QSPI_SSCTL_SSACTPOL_Msk)                    /*!< SS active high */
+#define QSPI_SS_ACTIVE_LOW     (0x0UL)                                      /*!< SS active low */
+
+/* QSPI Interrupt Mask */
+#define QSPI_UNIT_INT_MASK                (0x001UL)                        /*!< Unit transfer interrupt mask */
+#define QSPI_SSACT_INT_MASK               (0x002UL)                        /*!< Slave selection signal active interrupt mask */
+#define QSPI_SSINACT_INT_MASK             (0x004UL)                        /*!< Slave selection signal inactive interrupt mask */
+#define QSPI_SLVUR_INT_MASK               (0x008UL)                        /*!< Slave under run interrupt mask */
+#define QSPI_SLVBE_INT_MASK               (0x010UL)                        /*!< Slave bit count error interrupt mask */
+#define QSPI_SLVTO_INT_MASK               (0x020UL)                        /*!< Slave Mode Time-out interrupt mask */
+#define QSPI_TXUF_INT_MASK                (0x040UL)                        /*!< Slave TX underflow interrupt mask */
+#define QSPI_FIFO_TXTH_INT_MASK           (0x080UL)                        /*!< FIFO TX threshold interrupt mask */
+#define QSPI_FIFO_RXTH_INT_MASK           (0x100UL)                        /*!< FIFO RX threshold interrupt mask */
+#define QSPI_FIFO_RXOV_INT_MASK           (0x200UL)                        /*!< FIFO RX overrun interrupt mask */
+#define QSPI_FIFO_RXTO_INT_MASK           (0x400UL)                        /*!< FIFO RX time-out interrupt mask */
+
+/* QSPI Status Mask */
+#define QSPI_BUSY_MASK                    (0x01UL)                         /*!< Busy status mask */
+#define QSPI_RX_EMPTY_MASK                (0x02UL)                         /*!< RX empty status mask */
+#define QSPI_RX_FULL_MASK                 (0x04UL)                         /*!< RX full status mask */
+#define QSPI_TX_EMPTY_MASK                (0x08UL)                         /*!< TX empty status mask */
+#define QSPI_TX_FULL_MASK                 (0x10UL)                         /*!< TX full status mask */
+#define QSPI_TXRX_RESET_MASK              (0x20UL)                         /*!< TX or RX reset status mask */
+#define QSPI_SPIEN_STS_MASK               (0x40UL)                         /*!< SPIEN status mask */
+#define QSPI_SSLINE_STS_MASK              (0x80UL)                         /*!< QSPIx_SS line status mask */
+
+/* QSPI Status2 Mask */
+#define QSPI_SLVBENUM_MASK                (0x01UL)                         /*!< Effective bit number of uncompleted RX data status mask */
+
+/**@}*/ /* end of group QSPI_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup QSPI_EXPORTED_FUNCTIONS QSPI Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Clear the unit transfer interrupt flag.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return     None.
+  * @details    Write 1 to UNITIF bit of QSPI_STATUS register to clear the unit transfer interrupt flag.
+  */
+#define QSPI_CLR_UNIT_TRANS_INT_FLAG(qspi)   ( (qspi)->STATUS = QSPI_STATUS_UNITIF_Msk )
+
+/**
+  * @brief      Disable 2-bit Transfer mode.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return     None.
+  * @details    Clear TWOBIT bit of QSPI_CTL register to disable 2-bit Transfer mode.
+  */
+#define QSPI_DISABLE_2BIT_MODE(qspi)   ( (qspi)->CTL &= ~QSPI_CTL_TWOBIT_Msk )
+
+/**
+  * @brief      Disable Slave 3-wire mode.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return     None.
+  * @details    Clear SLV3WIRE bit of QSPI_SSCTL register to disable Slave 3-wire mode.
+  */
+#define QSPI_DISABLE_3WIRE_MODE(qspi)   ( (qspi)->SSCTL &= ~QSPI_SSCTL_SLV3WIRE_Msk )
+
+/**
+  * @brief      Disable Dual I/O mode.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return     None.
+  * @details    Clear DUALIOEN bit of QSPI_CTL register to disable Dual I/O mode.
+  */
+#define QSPI_DISABLE_DUAL_MODE(qspi)   ( (qspi)->CTL &= ~QSPI_CTL_DUALIOEN_Msk )
+
+/**
+  * @brief      Disable Quad I/O mode.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return     None.
+  * @details    Clear QUADIOEN bit of QSPI_CTL register to disable Quad I/O mode.
+  */
+#define QSPI_DISABLE_QUAD_MODE(qspi)   ( (qspi)->CTL &= ~QSPI_CTL_QUADIOEN_Msk )
+
+/**
+  * @brief      Disable TX DTR mode.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return     None.
+  * @details    Clear TXDTREN bit of QSPI_CTL register to disable TX DTR mode.
+  */
+#define QSPI_DISABLE_TXDTR_MODE(qspi)   ( (qspi)->CTL &= ~QSPI_CTL_TXDTREN_Msk )
+
+/**
+  * @brief      Enable 2-bit Transfer mode.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return     None.
+  * @details    Set TWOBIT bit of QSPI_CTL register to enable 2-bit Transfer mode.
+  */
+#define QSPI_ENABLE_2BIT_MODE(qspi)   ( (qspi)->CTL |= QSPI_CTL_TWOBIT_Msk )
+
+/**
+  * @brief      Enable Slave 3-wire mode.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return     None.
+  * @details    Set SLV3WIRE bit of QSPI_SSCTL register to enable Slave 3-wire mode.
+  */
+#define QSPI_ENABLE_3WIRE_MODE(qspi)   ( (qspi)->SSCTL |= QSPI_SSCTL_SLV3WIRE_Msk )
+
+/**
+  * @brief      Enable Dual input mode.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return     None.
+  * @details    Clear DATDIR bit and set DUALIOEN bit of QSPI_CTL register to enable Dual input mode.
+  */
+#define QSPI_ENABLE_DUAL_INPUT_MODE(qspi)   ( (qspi)->CTL = ((qspi)->CTL & (~QSPI_CTL_DATDIR_Msk)) | QSPI_CTL_DUALIOEN_Msk )
+
+/**
+  * @brief      Enable Dual output mode.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return     None.
+  * @details    Set DATDIR bit and DUALIOEN bit of QSPI_CTL register to enable Dual output mode.
+  */
+#define QSPI_ENABLE_DUAL_OUTPUT_MODE(qspi)   ( (qspi)->CTL |= (QSPI_CTL_DATDIR_Msk | QSPI_CTL_DUALIOEN_Msk) )
+
+/**
+  * @brief      Enable Quad input mode.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return     None.
+  * @details    Clear DATDIR bit and set QUADIOEN bit of QSPI_CTL register to enable Quad input mode.
+  */
+#define QSPI_ENABLE_QUAD_INPUT_MODE(qspi)   ( (qspi)->CTL = ((qspi)->CTL & (~QSPI_CTL_DATDIR_Msk)) | QSPI_CTL_QUADIOEN_Msk )
+
+/**
+  * @brief      Enable Quad output mode.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return     None.
+  * @details    Set DATDIR bit and QUADIOEN bit of QSPI_CTL register to enable Quad output mode.
+  */
+#define QSPI_ENABLE_QUAD_OUTPUT_MODE(qspi)   ( (qspi)->CTL |= (QSPI_CTL_DATDIR_Msk | QSPI_CTL_QUADIOEN_Msk) )
+
+/**
+  * @brief      Enable TX DTR mode.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return     None.
+  * @details    Set TXDTREN bit of QSPI_CTL register to enable TX DTR mode.
+  */
+#define QSPI_ENABLE_TXDTR_MODE(qspi)   ( (qspi)->CTL |= QSPI_CTL_TXDTREN_Msk )
+
+/**
+  * @brief      Trigger RX PDMA function.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return     None.
+  * @details    Set RXPDMAEN bit of QSPI_PDMACTL register to enable RX PDMA transfer function.
+  */
+#define QSPI_TRIGGER_RX_PDMA(qspi)   ( (qspi)->PDMACTL |= QSPI_PDMACTL_RXPDMAEN_Msk )
+
+/**
+  * @brief      Trigger TX PDMA function.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return     None.
+  * @details    Set TXPDMAEN bit of QSPI_PDMACTL register to enable TX PDMA transfer function.
+  */
+#define QSPI_TRIGGER_TX_PDMA(qspi)   ( (qspi)->PDMACTL |= QSPI_PDMACTL_TXPDMAEN_Msk )
+
+/**
+  * @brief      Trigger TX and RX PDMA function.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return     None.
+  * @details    Set TXPDMAEN bit and RXPDMAEN bit of QSPI_PDMACTL register to enable TX and RX PDMA transfer function.
+  */
+#define QSPI_TRIGGER_TX_RX_PDMA(qspi)   ( (qspi)->PDMACTL |= (QSPI_PDMACTL_TXPDMAEN_Msk | QSPI_PDMACTL_RXPDMAEN_Msk) )
+
+/**
+  * @brief      Disable RX PDMA transfer.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return     None.
+  * @details    Clear RXPDMAEN bit of QSPI_PDMACTL register to disable RX PDMA transfer function.
+  */
+#define QSPI_DISABLE_RX_PDMA(qspi)   ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_RXPDMAEN_Msk )
+
+/**
+  * @brief      Disable TX PDMA transfer.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return     None.
+  * @details    Clear TXPDMAEN bit of QSPI_PDMACTL register to disable TX PDMA transfer function.
+  */
+#define QSPI_DISABLE_TX_PDMA(qspi)   ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_TXPDMAEN_Msk )
+
+/**
+  * @brief      Disable TX and RX PDMA transfer.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return     None.
+  * @details    Clear TXPDMAEN bit and RXPDMAEN bit of QSPI_PDMACTL register to disable TX and RX PDMA transfer function.
+  */
+#define QSPI_DISABLE_TX_RX_PDMA(qspi)   ( (qspi)->PDMACTL &= ~(QSPI_PDMACTL_TXPDMAEN_Msk | QSPI_PDMACTL_RXPDMAEN_Msk) )
+
+/**
+  * @brief      Get the count of available data in RX FIFO.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return     The count of available data in RX FIFO.
+  * @details    Read RXCNT (QSPI_STATUS[27:24]) to get the count of available data in RX FIFO.
+  */
+#define QSPI_GET_RX_FIFO_COUNT(qspi)   ( ((qspi)->STATUS & QSPI_STATUS_RXCNT_Msk) >> QSPI_STATUS_RXCNT_Pos )
+
+/**
+  * @brief      Get the RX FIFO empty flag.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @retval     0 RX FIFO is not empty.
+  * @retval     1 RX FIFO is empty.
+  * @details    Read RXEMPTY bit of QSPI_STATUS register to get the RX FIFO empty flag.
+  */
+#define QSPI_GET_RX_FIFO_EMPTY_FLAG(qspi)   ( ((qspi)->STATUS & QSPI_STATUS_RXEMPTY_Msk) >> QSPI_STATUS_RXEMPTY_Pos )
+
+/**
+  * @brief      Get the TX FIFO empty flag.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @retval     0 TX FIFO is not empty.
+  * @retval     1 TX FIFO is empty.
+  * @details    Read TXEMPTY bit of QSPI_STATUS register to get the TX FIFO empty flag.
+  */
+#define QSPI_GET_TX_FIFO_EMPTY_FLAG(qspi)   ( ((qspi)->STATUS & QSPI_STATUS_TXEMPTY_Msk) >> QSPI_STATUS_TXEMPTY_Pos )
+
+/**
+  * @brief      Get the TX FIFO full flag.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @retval     0 TX FIFO is not full.
+  * @retval     1 TX FIFO is full.
+  * @details    Read TXFULL bit of QSPI_STATUS register to get the TX FIFO full flag.
+  */
+#define QSPI_GET_TX_FIFO_FULL_FLAG(qspi)   ( ((qspi)->STATUS & QSPI_STATUS_TXFULL_Msk) >> QSPI_STATUS_TXFULL_Pos )
+
+/**
+  * @brief      Get the datum read from RX register.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return     Data in RX register.
+  * @details    Read QSPI_RX register to get the received datum.
+  */
+#define QSPI_READ_RX(qspi)   ( (qspi)->RX )
+
+/**
+  * @brief      Write datum to TX register.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @param[in]  u32TxData The datum which user attempt to transfer through QSPI bus.
+  * @return     None.
+  * @details    Write u32TxData to QSPI_TX register.
+  */
+#define QSPI_WRITE_TX(qspi, u32TxData)   ( (qspi)->TX = (u32TxData) )
+
+/**
+  * @brief      Set QSPIx_SS pin to high state.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return     None.
+  * @details    Disable automatic slave selection function and set QSPIx_SS pin to high state.
+  */
+#define QSPI_SET_SS_HIGH(qspi)   ( (qspi)->SSCTL = ((qspi)->SSCTL & (~QSPI_SSCTL_AUTOSS_Msk)) | (QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk) )
+
+/**
+  * @brief      Set QSPIx_SS pin to low state.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return     None.
+  * @details    Disable automatic slave selection function and set QSPIx_SS pin to low state.
+  */
+#define QSPI_SET_SS_LOW(qspi)   ( (qspi)->SSCTL = ((qspi)->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk))) | QSPI_SSCTL_SS_Msk )
+
+/**
+  * @brief      Enable Byte Reorder function.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return     None.
+  * @details    Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (QSPI_CTL[7:4]).
+  */
+#define QSPI_ENABLE_BYTE_REORDER(qspi)   ( (qspi)->CTL |=  QSPI_CTL_REORDER_Msk )
+
+/**
+  * @brief      Disable Byte Reorder function.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return     None.
+  * @details    Clear REORDER bit field of QSPI_CTL register to disable Byte Reorder function.
+  */
+#define QSPI_DISABLE_BYTE_REORDER(qspi)   ( (qspi)->CTL &= ~QSPI_CTL_REORDER_Msk )
+
+/**
+  * @brief      Set the length of suspend interval.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @param[in]  u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15.
+  * @return     None.
+  * @details    Set the length of suspend interval according to u32SuspCycle.
+  *             The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one QSPI bus clock cycle).
+  */
+#define QSPI_SET_SUSPEND_CYCLE(qspi, u32SuspCycle)   ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << QSPI_CTL_SUSPITV_Pos) )
+
+/**
+  * @brief      Set the QSPI transfer sequence with LSB first.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return     None.
+  * @details    Set LSB bit of QSPI_CTL register to set the QSPI transfer sequence with LSB first.
+  */
+#define QSPI_SET_LSB_FIRST(qspi)   ( (qspi)->CTL |= QSPI_CTL_LSB_Msk )
+
+/**
+  * @brief      Set the QSPI transfer sequence with MSB first.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return     None.
+  * @details    Clear LSB bit of QSPI_CTL register to set the QSPI transfer sequence with MSB first.
+  */
+#define QSPI_SET_MSB_FIRST(qspi)   ( (qspi)->CTL &= ~QSPI_CTL_LSB_Msk )
+
+/**
+  * @brief      Set the data width of a QSPI transaction.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @param[in]  u32Width The bit width of one transaction.
+  * @return     None.
+  * @details    The data width can be 8 ~ 32 bits.
+  */
+#define QSPI_SET_DATA_WIDTH(qspi, u32Width)   ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DWIDTH_Msk) | (((u32Width) & 0x1F) << QSPI_CTL_DWIDTH_Pos) )
+
+/**
+  * @brief      Get the QSPI busy state.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @retval     0 QSPI controller is not busy.
+  * @retval     1 QSPI controller is busy.
+  * @details    This macro will return the busy state of QSPI controller.
+  */
+#define QSPI_IS_BUSY(qspi)   ( ((qspi)->STATUS & QSPI_STATUS_BUSY_Msk) >> QSPI_STATUS_BUSY_Pos )
+
+/**
+  * @brief      Enable QSPI controller.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return     None.
+  * @details    Set SPIEN (QSPI_CTL[0]) to enable QSPI controller.
+  */
+#define QSPI_ENABLE(qspi)   ( (qspi)->CTL |= QSPI_CTL_SPIEN_Msk )
+
+/**
+  * @brief      Disable QSPI controller.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return     None.
+  * @details    Clear SPIEN (QSPI_CTL[0]) to disable QSPI controller.
+  */
+#define QSPI_DISABLE(qspi)   ( (qspi)->CTL &= ~QSPI_CTL_SPIEN_Msk )
+
+/* Function prototype declaration */
+uint32_t QSPI_Open(QSPI_T *qspi, uint32_t u32MasterSlave, uint32_t u32QSPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
+void QSPI_Close(QSPI_T *qspi);
+void QSPI_ClearRxFIFO(QSPI_T *qspi);
+void QSPI_ClearTxFIFO(QSPI_T *qspi);
+void QSPI_DisableAutoSS(QSPI_T *qspi);
+void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
+uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock);
+void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
+uint32_t QSPI_GetBusClock(QSPI_T *qspi);
+void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask);
+void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask);
+uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask);
+void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask);
+uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask);
+uint32_t QSPI_GetStatus2(QSPI_T *qspi, uint32_t u32Mask);
+
+
+/**@}*/ /* end of group QSPI_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group QSPI_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_QSPI_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_rng.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_rng.h
new file mode 100644
index 0000000000..a30251ed48
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_rng.h
@@ -0,0 +1,57 @@
+/**************************************************************************//**
+ * @file     nu_rng.h
+ * @version  V3.00
+ * @brief    Random Number Generator Interface Controller (rng) driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_RNG_H__
+#define __NU_RNG_H__
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup RNG_Driver RNG Driver
+  @{
+*/
+
+/** @addtogroup RNG_EXPORTED_CONSTANTS RNG Exported Constants
+  @{
+*/
+
+/**@}*/ /* end of group RNG_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup RNG_EXPORTED_FUNCTIONS RNG Exported Functions
+  @{
+*/
+
+int32_t RNG_Open(void);
+int32_t RNG_Random(uint32_t *pu32Buf, int32_t nWords);
+
+int32_t RNG_ECDSA_Init(uint32_t u32KeySize, uint32_t au32ECC_N[18]);
+int32_t RNG_ECDSA(uint32_t u32KeySize);
+int32_t RNG_ECDH_Init(uint32_t u32KeySize, uint32_t au32ECC_N[18]);
+int32_t RNG_ECDH(uint32_t u32KeySize);
+
+/**@}*/ /* end of group RNG_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group RNG_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_RNG_H__ */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_rtc.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_rtc.h
new file mode 100644
index 0000000000..6854643e7f
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_rtc.h
@@ -0,0 +1,396 @@
+/**************************************************************************//**
+ * @file     nu_rtc.h
+ * @version  V3.00
+ * @brief    Real Time Clock(RTC) driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_RTC_H__
+#define __NU_RTC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup RTC_Driver RTC Driver
+  @{
+*/
+
+/** @addtogroup RTC_EXPORTED_CONSTANTS RTC Exported Constants
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/*  RTC Initial Keyword Constant Definitions                                                               */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_INIT_KEY            0xA5EB1357UL    /*!< RTC Initiation Key to make RTC leaving reset state \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  RTC Time Attribute Constant Definitions                                                                */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_CLOCK_12            0UL             /*!< RTC as 12-hour time scale with AM and PM indication \hideinitializer */
+#define RTC_CLOCK_24            1UL             /*!< RTC as 24-hour time scale \hideinitializer */
+#define RTC_AM                  1UL             /*!< RTC as AM indication \hideinitializer */
+#define RTC_PM                  2UL             /*!< RTC as PM indication \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  RTC Tick Period Constant Definitions                                                                   */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_TICK_1_SEC          0x0UL           /*!< RTC time tick period is 1 second \hideinitializer */
+#define RTC_TICK_1_2_SEC        0x1UL           /*!< RTC time tick period is 1/2 second \hideinitializer */
+#define RTC_TICK_1_4_SEC        0x2UL           /*!< RTC time tick period is 1/4 second \hideinitializer */
+#define RTC_TICK_1_8_SEC        0x3UL           /*!< RTC time tick period is 1/8 second \hideinitializer */
+#define RTC_TICK_1_16_SEC       0x4UL           /*!< RTC time tick period is 1/16 second \hideinitializer */
+#define RTC_TICK_1_32_SEC       0x5UL           /*!< RTC time tick period is 1/32 second \hideinitializer */
+#define RTC_TICK_1_64_SEC       0x6UL           /*!< RTC time tick period is 1/64 second \hideinitializer */
+#define RTC_TICK_1_128_SEC      0x7UL           /*!< RTC time tick period is 1/128 second \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  RTC Day of Week Constant Definitions                                                                   */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_SUNDAY              0x0UL           /*!< Day of the Week is Sunday \hideinitializer */
+#define RTC_MONDAY              0x1UL           /*!< Day of the Week is Monday \hideinitializer */
+#define RTC_TUESDAY             0x2UL           /*!< Day of the Week is Tuesday \hideinitializer */
+#define RTC_WEDNESDAY           0x3UL           /*!< Day of the Week is Wednesday \hideinitializer */
+#define RTC_THURSDAY            0x4UL           /*!< Day of the Week is Thursday \hideinitializer */
+#define RTC_FRIDAY              0x5UL           /*!< Day of the Week is Friday \hideinitializer */
+#define RTC_SATURDAY            0x6UL           /*!< Day of the Week is Saturday \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  RTC Miscellaneous Constant Definitions                                                                 */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_YEAR2000            2000UL          /*!< RTC Reference for compute year data \hideinitializer */
+#define RTC_FCR_REFERENCE       32752           /*!< RTC Reference for frequency compensation */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  RTC Tamper Constant Definitions                                                                        */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_TAMPER0_SELECT      (0x1UL << 0)    /*!< Select Tamper 0 \hideinitializer */
+#define RTC_TAMPER1_SELECT      (0x1UL << 1)    /*!< Select Tamper 1 \hideinitializer */
+#define RTC_TAMPER2_SELECT      (0x1UL << 2)    /*!< Select Tamper 2 \hideinitializer */
+#define RTC_TAMPER3_SELECT      (0x1UL << 3)    /*!< Select Tamper 3 \hideinitializer */
+#define RTC_TAMPER4_SELECT      (0x1UL << 4)    /*!< Select Tamper 4 \hideinitializer */
+#define RTC_TAMPER5_SELECT      (0x1UL << 5)    /*!< Select Tamper 5 \hideinitializer */
+#define RTC_MAX_TAMPER_PIN_NUM  6UL             /*!< Tamper Pin number \hideinitializer */
+
+#define RTC_TAMPER_LOW_LEVEL_DETECT     0UL     /*!< Tamper pin detect voltage level is low  \hideinitializer */
+#define RTC_TAMPER_HIGH_LEVEL_DETECT    1UL     /*!< Tamper pin detect voltage level is high \hideinitializer */
+
+#define RTC_TAMPER_DEBOUNCE_DISABLE     0UL     /*!< Disable RTC tamper pin de-bounce function \hideinitializer */
+#define RTC_TAMPER_DEBOUNCE_ENABLE      1UL     /*!< Enable RTC tamper pin de-bounce function \hideinitializer */
+
+#define RTC_PAIR0_SELECT        (0x1UL << 0)    /*!< Select Pair 0 \hideinitializer */
+#define RTC_PAIR1_SELECT        (0x1UL << 1)    /*!< Select Pair 1 \hideinitializer */
+#define RTC_PAIR2_SELECT        (0x1UL << 2)    /*!< Select Pair 2 \hideinitializer */
+#define RTC_MAX_PAIR_NUM        3UL             /*!< Pair number \hideinitializer */
+
+#define RTC_2POW10_CLK          (0x0UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 RTC clock cycles \hideinitializer */
+#define RTC_2POW11_CLK          (0x1UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 2 RTC clock cycles \hideinitializer */
+#define RTC_2POW12_CLK          (0x2UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 4 RTC clock cycles \hideinitializer */
+#define RTC_2POW13_CLK          (0x3UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 6 RTC clock cycles \hideinitializer */
+#define RTC_2POW14_CLK          (0x4UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 8 RTC clock cycles \hideinitializer */
+#define RTC_2POW15_CLK          (0x5UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 16 RTC clock cycles \hideinitializer */
+#define RTC_2POW16_CLK          (0x6UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 32 RTC clock cycles \hideinitializer */
+#define RTC_2POW17_CLK          (0x7UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 64 RTC clock cycles \hideinitializer */
+
+#define RTC_REF_RANDOM_PATTERN  0x0UL   /*!< The new reference pattern is generated by random number generator when the reference pattern run out \hideinitializer */
+#define RTC_REF_SEED_VALUE      0x1UL   /*!< The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  RTC Clock Source Constant Definitions                                                                  */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_CLOCK_SOURCE_LXT        0UL /*!< Set RTC clock source as external LXT \hideinitializer */
+#define RTC_CLOCK_SOURCE_LIRC       1UL /*!< Set RTC clock source as LIRC \hideinitializer */
+#define RTC_CLOCK_SOURCE_LIRC32K    2UL /*!< Set RTC clock source as LIRC32K \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  RTC GPIO_MODE Constant Definitions                                                                     */
+/*---------------------------------------------------------------------------------------------------------*/
+#define RTC_IO_MODE_INPUT       0x0UL   /*!< Input Mode */
+#define RTC_IO_MODE_OUTPUT      0x1UL   /*!< Output Mode */
+#define RTC_IO_MODE_OPEN_DRAIN  0x2UL   /*!< Open-Drain Mode */
+#define RTC_IO_MODE_QUASI       0x3UL   /*!< Quasi-bidirectional Mode */
+
+#define RTC_IO_DIGITAL_ENABLE   0UL     /*!< I/O digital path is enabled */
+#define RTC_IO_DIGITAL_DISABLE  1UL     /*!< I/O digital path is disabled */
+
+#define RTC_IO_PULL_UP_DOWN_DISABLE     0x0UL   /*!< I/O pull-up and pull-down is disabled */
+#define RTC_IO_PULL_UP_ENABLE           0x1UL   /*!< I/O pull-up is enabled */
+#define RTC_IO_PULL_DOWN_ENABLE         0x2UL   /*!< I/O pull-down is enabled */
+
+
+/**@}*/ /* end of group RTC_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup RTC_EXPORTED_STRUCTS RTC Exported Structs
+  @{
+*/
+/**
+  * @details    RTC define Time Data Struct
+  */
+typedef struct
+{
+    uint32_t u32Year;           /*!< Year value */
+    uint32_t u32Month;          /*!< Month value */
+    uint32_t u32Day;            /*!< Day value */
+    uint32_t u32DayOfWeek;      /*!< Day of week value */
+    uint32_t u32Hour;           /*!< Hour value */
+    uint32_t u32Minute;         /*!< Minute value */
+    uint32_t u32Second;         /*!< Second value */
+    uint32_t u32TimeScale;      /*!< 12-Hour, 24-Hour */
+    uint32_t u32AmPm;           /*!< Only Time Scale select 12-hr used */
+} S_RTC_TIME_DATA_T;
+
+/**@}*/ /* end of group RTC_EXPORTED_STRUCTS */
+
+
+/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Indicate is Leap Year or not
+  *
+  * @param[in]  rtc         The pointer of RTC module.
+  *
+  * @retval     0   This year is not a leap year
+  * @retval     1   This year is a leap year
+  *
+  * @details    According to current date, return this year is leap year or not.
+  * \hideinitializer
+  */
+#define RTC_IS_LEAP_YEAR(rtc)           (((rtc)->LEAPYEAR & RTC_LEAPYEAR_LEAPYEAR_Msk)? 1:0)
+
+/**
+  * @brief      Clear RTC Alarm Interrupt Flag
+  *
+  * @param[in]  rtc         The pointer of RTC module.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to clear RTC alarm interrupt flag.
+  * \hideinitializer
+  */
+#define RTC_CLEAR_ALARM_INT_FLAG(rtc)   ((rtc)->INTSTS = RTC_INTSTS_ALMIF_Msk)
+
+/**
+  * @brief      Clear RTC Tick Interrupt Flag
+  *
+  * @param[in]  rtc         The pointer of RTC module.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to clear RTC tick interrupt flag.
+  * \hideinitializer
+  */
+#define RTC_CLEAR_TICK_INT_FLAG(rtc)    ((rtc)->INTSTS = RTC_INTSTS_TICKIF_Msk)
+
+/**
+  * @brief      Clear RTC Tamper Interrupt Flag
+  *
+  * @param[in]  rtc             The pointer of RTC module.
+  * @param[in]  u32TamperFlag   Tamper interrupt flag. It consists of:    \n
+  *                             - \ref RTC_INTSTS_TAMP0IF_Msk    \n
+  *                             - \ref RTC_INTSTS_TAMP1IF_Msk    \n
+  *                             - \ref RTC_INTSTS_TAMP2IF_Msk    \n
+  *                             - \ref RTC_INTSTS_TAMP3IF_Msk    \n
+  *                             - \ref RTC_INTSTS_TAMP4IF_Msk    \n
+  *                             - \ref RTC_INTSTS_TAMP5IF_Msk
+  *
+  * @return     None
+  *
+  * @details    This macro is used to clear RTC tamper pin interrupt flag.
+  * \hideinitializer
+  */
+#define RTC_CLEAR_TAMPER_INT_FLAG(rtc, u32TamperFlag)   ((rtc)->INTSTS = (u32TamperFlag))
+
+/**
+  * @brief      Get RTC Alarm Interrupt Flag
+  *
+  * @param[in]  rtc         The pointer of RTC module.
+  *
+  * @retval     0   RTC alarm interrupt did not occur
+  * @retval     1   RTC alarm interrupt occurred
+  *
+  * @details    This macro indicates RTC alarm interrupt occurred or not.
+  * \hideinitializer
+  */
+#define RTC_GET_ALARM_INT_FLAG(rtc)         (((rtc)->INTSTS & RTC_INTSTS_ALMIF_Msk)? 1:0)
+
+/**
+  * @brief      Get RTC Time Tick Interrupt Flag
+  *
+  * @param[in]  rtc         The pointer of RTC module.
+  *
+  * @retval     0   RTC time tick interrupt did not occur
+  * @retval     1   RTC time tick interrupt occurred
+  *
+  * @details    This macro indicates RTC time tick interrupt occurred or not.
+  * \hideinitializer
+  */
+#define RTC_GET_TICK_INT_FLAG(rtc)          (((rtc)->INTSTS & RTC_INTSTS_TICKIF_Msk)? 1:0)
+
+/**
+  * @brief      Set I/O Control By GPIO
+  *
+  * @param[in]  rtc         The pointer of RTC module.
+  *
+  * @return     None
+  *
+  * @details    This macro sets the PF.4~11 pin I/O is controlled by GPIO module.
+  * \hideinitializer
+  */
+#define RTC_SET_IOCTL_BY_GPIO(rtc)          ((rtc)->LXTCTL &= ~RTC_LXTCTL_IOCTLSEL_Msk)
+
+/**
+  * @brief      Set I/O Control By RTC
+  *
+  * @param[in]  rtc         The pointer of RTC module.
+  *
+  * @return     None
+  *
+  * @details    This macro sets the PF.4~11 pin I/O is controlled by RTC module.
+  * \hideinitializer
+  */
+#define RTC_SET_IOCTL_BY_RTC(rtc)           ((rtc)->LXTCTL |= RTC_LXTCTL_IOCTLSEL_Msk)
+
+/**
+  * @brief      Get I/O Control Property
+  *
+  * @param[in]  rtc         The pointer of RTC module.
+  *
+  * @retval     0   PF.4~11 pin I/O is controlled by GPIO module
+  * @retval     1   PF.4~11 pin I/O is controlled by RTC module
+  *
+  * @details    This macro indicates the PF.4~11 pin I/O control property.
+  * \hideinitializer
+  */
+#define RTC_GET_IOCTL_PROPERTY(rtc)          (((rtc)->LXTCTL & RTC_LXTCTL_IOCTLSEL_Msk)? 1:0)
+
+/**
+  * @brief      Get RTC Tamper Interrupt Flag
+  *
+  * @param[in]  rtc         The pointer of RTC module.
+  *
+  * @retval     0   RTC tamper event interrupt did not occur
+  * @retval     1   RTC tamper event interrupt occurred
+  *
+  * @details    This macro indicates RTC tamper event occurred or not.
+  * \hideinitializer
+  */
+#define RTC_GET_TAMPER_INT_FLAG(rtc)        (((rtc)->INTSTS & (0x3F00))? 1:0)
+
+/**
+  * @brief      Get RTC Tamper Interrupt Status
+  *
+  * @param[in]  rtc         The pointer of RTC module.
+  *
+  * @retval     RTC_INTSTS_TAMP0IF_Msk    Tamper 0 interrupt flag is generated
+  * @retval     RTC_INTSTS_TAMP1IF_Msk    Tamper 1 interrupt flag is generated
+  * @retval     RTC_INTSTS_TAMP2IF_Msk    Tamper 2 interrupt flag is generated
+  * @retval     RTC_INTSTS_TAMP3IF_Msk    Tamper 3 interrupt flag is generated
+  * @retval     RTC_INTSTS_TAMP4IF_Msk    Tamper 4 interrupt flag is generated
+  * @retval     RTC_INTSTS_TAMP5IF_Msk    Tamper 5 interrupt flag is generated
+  *
+  * @details    This macro indicates RTC tamper interrupt status.
+  * \hideinitializer
+  */
+#define RTC_GET_TAMPER_INT_STATUS(rtc)      (((rtc)->INTSTS & (0x3F00)))
+
+/**
+  * @brief      Enable RTC Tick Wake-up Function
+  *
+  * @param[in]  rtc         The pointer of RTC module.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to enable RTC tick interrupt wake-up function.
+  * \hideinitializer
+  */
+#define RTC_ENABLE_TICK_WAKEUP(rtc)         ((rtc)->INTEN |= RTC_INTEN_TICKIEN_Msk);
+
+/**
+  * @brief      Disable RTC Tick Wake-up Function
+  *
+  * @param[in]  rtc         The pointer of RTC module.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to disable RTC tick interrupt wake-up function.
+  * \hideinitializer
+  */
+#define RTC_DISABLE_TICK_WAKEUP(rtc)        ((rtc)->INTEN &= ~RTC_INTEN_TICKIEN_Msk);
+
+/**
+  * @brief      Read Spare Register
+  *
+  * @param[in]  rtc         The pointer of RTC module.
+  * @param[in]  u32RegNum   The spare register number, 0~19.
+  *
+  * @return     Spare register content
+  *
+  * @details    Read the specify spare register content.
+  * \hideinitializer
+  */
+#define RTC_READ_SPARE_REGISTER(rtc, u32RegNum)     ((rtc)->SPR[(u32RegNum)])
+
+/**
+  * @brief      Write Spare Register
+  *
+  * @param[in]  rtc             The pointer of RTC module.
+  * @param[in]  u32RegNum       The spare register number, 0~19.
+  * @param[in]  u32RegValue     The spare register value.
+  *
+  * @return     None
+  *
+  * @details    Write specify data to spare register.
+  * \hideinitializer
+  */
+#define RTC_WRITE_SPARE_REGISTER(rtc, u32RegNum, u32RegValue)   ((rtc)->SPR[(u32RegNum)] = (u32RegValue))
+
+
+void RTC_Open(S_RTC_TIME_DATA_T *sPt);
+void RTC_Close(void);
+void RTC_32KCalibration(int32_t i32FrequencyX10000);
+void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt);
+void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt);
+void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt);
+void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt);
+void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek);
+void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);
+void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day);
+void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);
+void RTC_SetAlarmDateMask(uint8_t u8IsTenYMsk, uint8_t u8IsYMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenDMsk, uint8_t u8IsDMsk);
+void RTC_SetAlarmTimeMask(uint8_t u8IsTenHMsk, uint8_t u8IsHMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenSMsk, uint8_t u8IsSMsk);
+uint32_t RTC_GetDayOfWeek(void);
+void RTC_SetTickPeriod(uint32_t u32TickSelection);
+void RTC_EnableInt(uint32_t u32IntFlagMask);
+void RTC_DisableInt(uint32_t u32IntFlagMask);
+void RTC_EnableSpareAccess(void);
+void RTC_DisableSpareRegister(void);
+void RTC_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn);
+void RTC_StaticTamperDisable(uint32_t u32TamperSelect);
+void RTC_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32_t u32Pair1Source, uint32_t u32Pair2Source);
+void RTC_DynamicTamperDisable(uint32_t u32PairSel);
+void RTC_DynamicTamperConfig(uint32_t u32ChangeRate, uint32_t u32SeedReload, uint32_t u32RefPattern, uint32_t u32Seed);
+uint32_t RTC_SetClockSource(uint32_t u32ClkSrc);
+void RTC_SetGPIOMode(uint32_t u32PFPin, uint32_t u32Mode, uint32_t u32DigitalCtl, uint32_t u32PullCtl, uint32_t u32OutputLevel);
+void RTC_SetGPIOLevel(uint32_t u32PFPin, uint32_t u32OutputLevel);
+
+/**@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group RTC_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_RTC_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_sc.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_sc.h
new file mode 100644
index 0000000000..5a853e74ca
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_sc.h
@@ -0,0 +1,305 @@
+/**************************************************************************//**
+ * @file     nu_sc.h
+ * @version  V3.00
+ * @brief    Smartcard(SC) driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_SC_H__
+#define __NU_SC_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup SC_Driver SC Driver
+  @{
+*/
+
+/** @addtogroup SC_EXPORTED_CONSTANTS SC Exported Constants
+  @{
+*/
+#define SC_INTERFACE_NUM                (3UL)               /*!< Smartcard interface numbers \hideinitializer */
+#define SC_PIN_STATE_HIGH               (1UL)               /*!< Smartcard pin status high   \hideinitializer */
+#define SC_PIN_STATE_LOW                (0UL)               /*!< Smartcard pin status low    \hideinitializer */
+#define SC_PIN_STATE_IGNORE             (0xFFFFFFFFUL)      /*!< Ignore pin status           \hideinitializer */
+#define SC_CLK_ON                       (1UL)               /*!< Smartcard clock on          \hideinitializer */
+#define SC_CLK_OFF                      (0UL)               /*!< Smartcard clock off         \hideinitializer */
+
+#define SC_TMR_MODE_0                   (0UL << SC_TMRCTL0_OPMODE_Pos)      /*!INTEN |= (u32Mask))
+
+/**
+  * @brief      This macro disable smartcard interrupt
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  * @param[in]  u32Mask Interrupt mask to be disabled. A combination of
+  *                         - \ref SC_INTEN_ACERRIEN_Msk
+  *                         - \ref SC_INTEN_RXTOIEN_Msk
+  *                         - \ref SC_INTEN_INITIEN_Msk
+  *                         - \ref SC_INTEN_CDIEN_Msk
+  *                         - \ref SC_INTEN_BGTIEN_Msk
+  *                         - \ref SC_INTEN_TMR2IEN_Msk
+  *                         - \ref SC_INTEN_TMR1IEN_Msk
+  *                         - \ref SC_INTEN_TMR0IEN_Msk
+  *                         - \ref SC_INTEN_TERRIEN_Msk
+  *                         - \ref SC_INTEN_TBEIEN_Msk
+  *                         - \ref SC_INTEN_RDAIEN_Msk
+  *
+  * @return     None
+  *
+  * @details    The macro is used to disable Auto-convention error interrupt, Receiver buffer time-out interrupt, Initial end interrupt,
+  *             Card detect interrupt, Block guard time interrupt, Timer2 interrupt, Timer1 interrupt, Timer0 interrupt,
+  *             Transfer error interrupt, Transmit buffer empty interrupt or Receive data reach trigger level interrupt.
+  * \hideinitializer
+  */
+#define SC_DISABLE_INT(sc, u32Mask)     ((sc)->INTEN &= ~(u32Mask))
+
+/**
+  * @brief      This macro set VCC pin state of smartcard interface
+  *
+  * @param[in]  sc          The pointer of smartcard module.
+  * @param[in]  u32State    Pin state of VCC pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW.
+  *
+  * @return     None
+  *
+  * @details    User can set PWREN (SC_PINCTL[0]) and PWRINV (SC_PINCTL[11]) to decide SC_PWR pin is in high or low level.
+  * \hideinitializer
+  */
+#define SC_SET_VCC_PIN(sc, u32State) \
+    do {\
+            while(((sc)->PINCTL & SC_PINCTL_SYNC_Msk) == SC_PINCTL_SYNC_Msk);\
+            if(u32State)\
+                (sc)->PINCTL |= SC_PINCTL_PWREN_Msk;\
+            else\
+                (sc)->PINCTL &= ~SC_PINCTL_PWREN_Msk;\
+    }while(0)
+
+
+/**
+  * @brief      This macro turns CLK output on or off
+  *
+  * @param[in]  sc          The pointer of smartcard module.
+  * @param[in] u32OnOff     Clock on or off for selected smartcard module, valid values are \ref SC_CLK_ON and \ref SC_CLK_OFF.
+  *
+  * @return     None
+  *
+  * @details    User can set CLKKEEP (SC_PINCTL[6]) to decide SC_CLK pin always keeps free running or not.
+  * \hideinitializer
+  */
+#define SC_SET_CLK_PIN(sc, u32OnOff)\
+    do {\
+            while(((sc)->PINCTL & SC_PINCTL_SYNC_Msk) == SC_PINCTL_SYNC_Msk);\
+            if(u32OnOff)\
+                (sc)->PINCTL |= SC_PINCTL_CLKKEEP_Msk;\
+            else\
+                (sc)->PINCTL &= ~(SC_PINCTL_CLKKEEP_Msk);\
+    }while(0)
+
+/**
+  * @brief      This macro set I/O pin state of smartcard interface
+  *
+  * @param[in]  sc          The pointer of smartcard module.
+  * @param[in] u32State     Pin state of I/O pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW.
+  *
+  * @return     None
+  *
+  * @details    User can set SCDATA (SC_PINCTL[9]) to decide SC_DATA pin to high or low.
+  * \hideinitializer
+  */
+#define SC_SET_IO_PIN(sc, u32State)\
+    do {\
+            while(((sc)->PINCTL & SC_PINCTL_SYNC_Msk) == SC_PINCTL_SYNC_Msk);\
+            if(u32State)\
+                (sc)->PINCTL |= SC_PINCTL_SCDATA_Msk;\
+            else\
+                (sc)->PINCTL &= ~SC_PINCTL_SCDATA_Msk;\
+    }while(0)
+
+/**
+  * @brief      This macro set RST pin state of smartcard interface
+  *
+  * @param[in]  sc          The pointer of smartcard module.
+  * @param[in] u32State     Pin state of RST pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW.
+  *
+  * @return     None
+  *
+  * @details    User can set SCRST (SC_PINCTL[1]) to decide SC_RST pin to high or low.
+  * \hideinitializer
+  */
+#define SC_SET_RST_PIN(sc, u32State)\
+    do {\
+            while(((sc)->PINCTL & SC_PINCTL_SYNC_Msk) == SC_PINCTL_SYNC_Msk);\
+            if(u32State)\
+                (sc)->PINCTL |= SC_PINCTL_RSTEN_Msk;\
+            else\
+                (sc)->PINCTL &= ~SC_PINCTL_RSTEN_Msk;\
+    }while(0)
+
+/**
+  * @brief      This macro read one byte from smartcard module receive FIFO
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  *
+  * @return     One byte read from receive FIFO
+  *
+  * @details    By reading DAT register, the SC will return an 8-bit received data.
+  * \hideinitializer
+  */
+#define SC_READ(sc)             ((char)((sc)->DAT))
+
+/**
+  * @brief      This macro write one byte to smartcard module transmit FIFO
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  * @param[in]  u8Data  Data to write to transmit FIFO.
+  *
+  * @return     None
+  *
+  * @details    By writing data to DAT register, the SC will send out an 8-bit data.
+  * \hideinitializer
+  */
+#define SC_WRITE(sc, u8Data)    ((sc)->DAT = (u8Data))
+
+/**
+  * @brief      This macro set smartcard stop bit length
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  * @param[in]  u32Len  Stop bit length, ether 1 or 2.
+  *
+  * @return     None
+  *
+  * @details    Stop bit length must be 1 for T = 1 protocol and 2 for T = 0 protocol.
+  * \hideinitializer
+  */
+#define SC_SET_STOP_BIT_LEN(sc, u32Len) ((sc)->CTL = ((sc)->CTL & ~SC_CTL_NSB_Msk) | (((u32Len) == 1)? SC_CTL_NSB_Msk : 0))
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* static inline functions                                                                                 */
+/*---------------------------------------------------------------------------------------------------------*/
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
+__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count);
+__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count);
+
+
+/**
+  * @brief      Enable/Disable Tx error retry, and set Tx error retry count
+  *
+  * @param[in]  sc          The pointer of smartcard module.
+  * @param[in]  u32Count    The number of times of Tx error retry count, between 0~8. 0 means disable Tx error retry.
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable/disable transmitter retry function when parity error has occurred, and set error retry count.
+  */
+__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count)
+{
+    while(((sc)->CTL & SC_CTL_SYNC_Msk) == SC_CTL_SYNC_Msk) {}
+
+    /* Retry count must set while enable bit disabled, so disable it first */
+    (sc)->CTL &= ~(SC_CTL_TXRTY_Msk | SC_CTL_TXRTYEN_Msk);
+
+    if((u32Count) != 0UL)
+    {
+        while(((sc)->CTL & SC_CTL_SYNC_Msk) == SC_CTL_SYNC_Msk) {}
+        (sc)->CTL |= (((u32Count) - 1UL) << SC_CTL_TXRTY_Pos) | SC_CTL_TXRTYEN_Msk;
+    }
+}
+
+/**
+  * @brief      Enable/Disable Rx error retry, and set Rx error retry count
+  *
+  * @param[in]  sc          The pointer of smartcard module.
+  * @param[in]  u32Count    The number of times of Rx error retry count, between 0~8. 0 means disable Rx error retry.
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable/disable receiver retry function when parity error has occurred, and set error retry count.
+  */
+__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count)
+{
+    while(((sc)->CTL & SC_CTL_SYNC_Msk) == SC_CTL_SYNC_Msk) {}
+
+    /* Retry count must set while enable bit disabled, so disable it first */
+    (sc)->CTL &= ~(SC_CTL_RXRTY_Msk | SC_CTL_RXRTYEN_Msk);
+
+    if((u32Count) != 0UL)
+    {
+        while(((sc)->CTL & SC_CTL_SYNC_Msk) == SC_CTL_SYNC_Msk) {}
+        (sc)->CTL |= (((u32Count) - 1UL) << SC_CTL_RXRTY_Pos) | SC_CTL_RXRTYEN_Msk;
+    }
+}
+
+
+uint32_t SC_IsCardInserted(SC_T *sc);
+void SC_ClearFIFO(SC_T *sc);
+void SC_Close(SC_T *sc);
+void SC_Open(SC_T *sc, uint32_t u32CardDet, uint32_t u32PWR);
+void SC_ResetReader(SC_T *sc);
+void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT);
+void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT);
+void SC_StopAllTimer(SC_T *sc);
+void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount);
+void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum);
+uint32_t SC_GetInterfaceClock(SC_T *sc);
+
+/**@}*/ /* end of group SC_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group SC_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_SC_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_scu.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_scu.h
new file mode 100644
index 0000000000..5079c6d175
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_scu.h
@@ -0,0 +1,358 @@
+/**************************************************************************//**
+ * @file     nu_scu.h
+ * @version  V3.00
+ * @brief    Secure Configuration Unit Driver Header
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_SCU_H__
+#define __NU_SCU_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup SCU_Driver SCU Driver
+  @{
+*/
+
+/** @addtogroup SCU_EXPORTED_CONSTANTS SCU Exported Constants
+  @{
+*/
+
+
+
+
+/**
+ * @details  Non-secure Attribution Definition.
+ */
+typedef enum NSATTR
+{
+    /******  PNNSET0 **********************************************************************************/
+    USBH_Attr   =     9,
+    SDH0_Attr   =    13,
+    EBI_Attr    =    16,
+    PDMA1_Attr  =    24,
+
+    /******  PNNSET1 **********************************************************************************/
+    CRC_Attr    = 32 + 17,
+    CRPT_Attr   = 32 + 18,
+
+    /******  PNNSET2 **********************************************************************************/
+    EWDT_Attr   = 64 + 2,
+    EADC_Attr   = 64 + 3,
+    ACMP01_Attr = 64 + 5,
+    DAC_Attr    = 64 + 7,
+    I2S0_Attr   = 64 + 8,
+    OTG_Attr    = 64 + 13,
+    TMR23_Attr  = 64 + 17,
+    TMR45_Attr  = 64 + 18,
+    EPWM0_Attr  = 64 + 24,
+    EPWM1_Attr  = 64 + 25,
+    BPWM0_Attr  = 64 + 26,
+    BPWM1_Attr  = 64 + 27,
+    /******  PNNSET3 **********************************************************************************/
+    QSPI0_Attr  = 96 + 0,
+    SPI0_Attr   = 96 + 1,
+    SPI1_Attr   = 96 + 2,
+    SPI2_Attr   = 96 + 3,
+    SPI3_Attr   = 96 + 4,
+    UART0_Attr  = 96 + 16,
+    UART1_Attr  = 96 + 17,
+    UART2_Attr  = 96 + 18,
+    UART3_Attr  = 96 + 19,
+    UART4_Attr  = 96 + 20,
+    UART5_Attr  = 96 + 21,
+    /******  PNNSET4 **********************************************************************************/
+    I2C0_Attr   = 128 + 0,
+    I2C1_Attr   = 128 + 1,
+    I2C2_Attr   = 128 + 2,
+    SC0_Attr    = 128 + 16,
+    SC1_Attr    = 128 + 17,
+    SC2_Attr    = 128 + 18,
+
+
+    /******  PNNSET5 **********************************************************************************/
+    CAN0_Attr   = 160 + 0,
+    QEI0_Attr   = 160 + 16,
+    QEI1_Attr   = 160 + 17,
+    ECAP0_Attr  = 160 + 20,
+    ECAP1_Attr  = 160 + 21,
+    TRNG_Attr   = 160 + 25,
+    LCD_Attr    = 160 + 27,
+
+    /******  PNNSET6 **********************************************************************************/
+    USBD_Attr   = 192 + 0,
+    USCI0_Attr  = 192 + 16,
+    USCI1_Attr  = 192 + 17
+
+
+} NSATTR_T;
+
+
+/**@}*/ /* end of group SCU_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup SCU_EXPORTED_FUNCTIONS SCU Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Set peripheral non-secure attribution
+  *
+  * @param[in]  nsattr     The secure/non-secure attribution of specified module.
+                           The possible value could be refer to \ref NSATTR.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set a peripheral to be non-secure peripheral.
+  *
+  */
+#define SCU_SET_PNSSET(nsattr)   { SCU->PNSSET[(nsattr)/32] |= (1 << ((nsattr) & 0x1ful)); }
+
+/**
+ * @brief       Get peripheral secure/non-secure attribution
+ *
+  * @param[in]  nsattr     The secure/non-secure attribution of specified module.
+                           The possible value could be refer to \ref NSATTR.
+ *
+ * @return      The secure/non-secure attribution of specified peripheral.
+ * @retval      0 The peripheral is secure
+ * @retval      1 The peripheral is non-secure
+ *
+ * @details     This macro gets the peripheral secure/non-secure attribution.
+ */
+#define SCU_GET_PNSSET(nsattr)   ((SCU->PNSSET[(nsattr)/32] >> ((nsattr) & 0x1ful)) & 1ul)
+
+
+/**
+ * @brief       Set secure/non-secure attribution of specified GPIO pin
+ *
+ * @param[in]   port        GPIO Port. It could be PA, PB, PC, PD, PE, PF, PG and PH.
+ * @param[in]   bitmask     Bit mask of each bit. 0 is secure. 1 is non-secure.
+ *
+ * @return      None
+ *
+ * @details     This macro sets GPIO pin secure/non-secure attribution.
+ */
+#define SCU_SET_IONSSET(port, mask)   (SCU->IONSSET[((uint32_t)(port)-(GPIOA_BASE))/0x40] = (mask))
+
+
+/**
+ * @brief       Get secure/non-secure attribution of specified GPIO port
+ *
+ * @param[in]   port        GPIO Port. It could be PA, PB, PC, PD, PE, PF, PG and PH.
+ *
+ * @return      The secure/non-secure attribution of the port.
+ * @retval      0 The relative bit of specified IO port is secure
+ * @retval      1 The relative bit of specified IO port is non-secure
+ *
+ * @details     This macro gets IO secure/non-secure attribution of specified IO port.
+ */
+#define SCU_GET_IONSSET(port)   (SCU->IONSSET[((uint32_t)(port) - (GPIOA_BASE))/0x40])
+
+
+/**
+ * @brief       Enable sercure violation interrupts
+ *
+ * @param[in]   mask    The mask of each secure violation interrupt source
+ *              - \ref SCU_SVIOIEN_APB0IEN_Msk
+ *              - \ref SCU_SVIOIEN_APB1IEN_Msk
+ *              - \ref SCU_SVIOIEN_GPIOIEN_Msk
+ *              - \ref SCU_SVIOIEN_EBIIEN_Msk
+ *              - \ref SCU_SVIOIEN_USBHIEN_Msk
+ *              - \ref SCU_SVIOIEN_CRCIEN_Msk
+ *              - \ref SCU_SVIOIEN_SDH0IEN_Msk
+ *              - \ref SCU_SVIOIEN_PDMA0IEN_Msk
+ *              - \ref SCU_SVIOIEN_PDMA1IEN_Msk
+ *              - \ref SCU_SVIOIEN_SRAM0IEN_Msk
+ *              - \ref SCU_SVIOIEN_SRAM1IEN_Msk
+ *              - \ref SCU_SVIOIEN_FMCIEN_Msk
+ *              - \ref SCU_SVIOIEN_FLASHIEN_Msk
+ *              - \ref SCU_SVIOIEN_SCUIEN_Msk
+ *              - \ref SCU_SVIOIEN_SYSIEN_Msk
+ *              - \ref SCU_SVIOIEN_CRPTIEN_Msk
+ *
+ * @return      None
+ *
+ * @details     This macro is used to enable secure violation interrupt of SCU.
+ *              The secure violation interrupt could be used to detect attack of secure elements.
+ */
+#define SCU_ENABLE_INT(mask)    (SCU->SVIOIEN |= (mask))
+
+
+/**
+ * @brief       Disable sercure violation interrupts
+ *
+ * @param[in]   mask    The mask of each secure violation interrupt source
+ *              - \ref SCU_SVIOIEN_APB0IEN_Msk
+ *              - \ref SCU_SVIOIEN_APB1IEN_Msk
+ *              - \ref SCU_SVIOIEN_GPIOIEN_Msk
+ *              - \ref SCU_SVIOIEN_EBIIEN_Msk
+ *              - \ref SCU_SVIOIEN_USBHIEN_Msk
+ *              - \ref SCU_SVIOIEN_CRCIEN_Msk
+ *              - \ref SCU_SVIOIEN_SDH0IEN_Msk
+ *              - \ref SCU_SVIOIEN_PDMA0IEN_Msk
+ *              - \ref SCU_SVIOIEN_PDMA1IEN_Msk
+ *              - \ref SCU_SVIOIEN_SRAM0IEN_Msk
+ *              - \ref SCU_SVIOIEN_SRAM1IEN_Msk
+ *              - \ref SCU_SVIOIEN_FMCIEN_Msk
+ *              - \ref SCU_SVIOIEN_FLASHIEN_Msk
+ *              - \ref SCU_SVIOIEN_SCUIEN_Msk
+ *              - \ref SCU_SVIOIEN_SYSIEN_Msk
+ *              - \ref SCU_SVIOIEN_CRPTIEN_Msk
+ *
+ * @return      None
+ *
+ * @details     This macro is used to disable secure violation interrupt of SCU.
+ *
+ */
+#define SCU_DISABLE_INT(mask)    (SCU->SVIOIEN &= (~(mask)))
+
+
+/**
+  * @brief    Get secure violation interrupt status
+  *
+  * @param    mask  The interrupt flag mask bit
+  *
+  * @return   The value of SCU_SVINTSTS register
+  *
+  * @details  Return interrupt flag of SCU_SVINTSTS register.
+  *
+  */
+#define SCU_GET_INT_FLAG(mask)         (SCU->SVINTSTS&(mask))
+
+/**
+  * @brief      Clear secure violation interrupt flag
+  *
+  * @param[in]  flag The combination of the specified interrupt flags.
+  *             Each bit corresponds to a interrupt source.
+  *             This parameter decides which interrupt flags will be cleared.
+  *             - \ref SCU_SVINTSTS_APB0IF_Msk
+  *             - \ref SCU_SVINTSTS_APB1IF_Msk
+  *             - \ref SCU_SVINTSTS_GPIOIF_Msk
+  *             - \ref SCU_SVINTSTS_EBIIF_Msk
+  *             - \ref SCU_SVINTSTS_USBHIF_Msk
+  *             - \ref SCU_SVINTSTS_CRCIF_Msk
+  *             - \ref SCU_SVINTSTS_SDH0IF_Msk
+  *             - \ref SCU_SVINTSTS_PDMA0IF_Msk
+  *             - \ref SCU_SVINTSTS_PDMA1IF_Msk
+  *             - \ref SCU_SVINTSTS_SRAM0IF_Msk
+  *             - \ref SCU_SVINTSTS_SRAM1IF_Msk
+  *             - \ref SCU_SVINTSTS_FMCIF_Msk
+  *             - \ref SCU_SVINTSTS_FLASHIF_Msk
+  *             - \ref SCU_SVINTSTS_SCUIF_Msk
+  *             - \ref SCU_SVINTSTS_SYSIF_Msk
+  *             - \ref SCU_SVINTSTS_CRPTIF_Msk
+  *
+  * @return     None
+  *
+  * @details    Clear SCU related interrupt flags specified by flag parameter.
+  *
+  */
+#define SCU_CLR_INT_FLAG(flag)     (SCU->SVINTSTS = (flag))
+
+
+
+/**
+  * @brief      Control the behavior of non-secure monitor when CPU is in idle state.
+  *
+  * @param[in]  opt Option for behavior control of non-secure monitor when CPU in idle.
+  *              - true     The counter keeps counting when CPU is in idle.
+                 - false    The counter will stop when CPU is in idle.
+  *
+  * @return     None
+  *
+  * @details    To control non-secure monitor counter when CPU is in idle.
+  *
+  */
+#define SCU_NSM_IDLE_ON(opt)    ((opt)?(SCU->NSMCTL |= SCU_NSMCTL_IDLEON_Msk):(SCU->NSMCTL &= ~SCU_NSMCTL_IDLEON_Msk))
+
+/**
+  * @brief      Control the behavior of non-secure monitor when CPU is in debug state.
+  *
+  * @param[in]  opt Option for behavior control of non-secure monitor when CPU in debug.
+  *              - true     The counter keeps counting when CPU is in debug.
+                 - false    The counter will stop when CPU is in debug.
+  *
+  * @return     None
+  *
+  * @details    To control non-secure monitor counter when CPU is in debug.
+  *
+  */
+#define SCU_NSM_DBG_ON(opt)    ((opt)?(SCU->NSMCTL |= SCU_NSMCTL_DBGON_Msk):(SCU->NSMCTL &= ~SCU_NSMCTL_DBGON_Msk))
+
+
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
+__STATIC_INLINE void SCU_NSMConfig(uint32_t u32Ticks, uint32_t u32Prescale);
+__STATIC_INLINE void SCU_TimerConfig(uint32_t u32Ticks, uint32_t u32Prescale);
+
+
+/**
+  * @brief      Config non-secure monitor to detect timeout in non-secure state.
+  *
+  * @param[in]  u32Ticks       A specified period for timeout in non-secure state
+  * @param[in]  u32Prescale    A pre-scale divider to non-secure monitor clock
+
+  *
+  * @return     None
+  *
+  * @details    This function is used to configure non-secure monitor. If the CPU state stay in non-secure state for
+  *             a specified period. The non-secure monitor will timeout and assert an interrupt. Otherwise, the
+  *             non-secure monitor will auto clear whenever returning to secure state. This could be used to avoid
+  *             CPU state in non-secure state too long time for security purpose. User must enable SCU_IRQn if interrupt
+  *             is necessary.
+  *
+  */
+__STATIC_INLINE void SCU_NSMConfig(uint32_t u32Ticks, uint32_t u32Prescale)
+{
+
+    SCU->NSMLOAD = u32Ticks;
+    SCU->NSMVAL  = 0ul;
+    SCU->NSMCTL  = SCU_NSMCTL_AUTORLD_Msk | SCU_NSMCTL_NSMIEN_Msk | (u32Prescale & 0xfful);
+}
+
+
+/**
+  * @brief      Config non-secure monitor to be a timer.
+  *
+  * @param[in]  u32Ticks       A specified period for timer interrupt.
+  * @param[in]  u32Prescale    A pre-scale divider to timer clock source.
+
+  *
+  * @return     None
+  *
+  * @details    This function is used to configure non-secure monitor as a timer. In other words, the timer counter
+  *             keeps counting even CPU is in secure state.
+  *
+  */
+__STATIC_INLINE void SCU_TimerConfig(uint32_t u32Ticks, uint32_t u32Prescale)
+{
+
+    SCU->NSMLOAD = u32Ticks;
+    SCU->NSMVAL  = 0ul;
+    SCU->NSMCTL  = SCU_NSMCTL_AUTORLD_Msk | SCU_NSMCTL_NSMIEN_Msk | SCU_NSMCTL_TMRMOD_Msk | (u32Prescale & 0xfful);
+}
+
+
+
+
+/**@}*/ /* end of group SCU_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group SCU_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_SCU_H__ */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_scuart.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_scuart.h
new file mode 100644
index 0000000000..d9a3756b14
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_scuart.h
@@ -0,0 +1,353 @@
+/**************************************************************************//**
+ * @file     nu_scuart.h
+ * @version  V3.00
+ * @brief    Smartcard UART mode (SCUART) driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_SCUART_H__
+#define __NU_SCUART_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup SCUART_Driver SCUART Driver
+  @{
+*/
+
+/** @addtogroup SCUART_EXPORTED_CONSTANTS SCUART Exported Constants
+  @{
+*/
+#define SCUART_CHAR_LEN_5     (0x3UL << SC_UARTCTL_WLS_Pos)     /*!< Set SCUART word length to 5 bits \hideinitializer */
+#define SCUART_CHAR_LEN_6     (0x2UL << SC_UARTCTL_WLS_Pos)     /*!< Set SCUART word length to 6 bits \hideinitializer */
+#define SCUART_CHAR_LEN_7     (0x1UL << SC_UARTCTL_WLS_Pos)     /*!< Set SCUART word length to 7 bits \hideinitializer */
+#define SCUART_CHAR_LEN_8     (0UL)                             /*!< Set SCUART word length to 8 bits \hideinitializer */
+
+#define SCUART_PARITY_NONE    (SC_UARTCTL_PBOFF_Msk)            /*!< Set SCUART transfer with no parity   \hideinitializer */
+#define SCUART_PARITY_ODD     (SC_UARTCTL_OPE_Msk)              /*!< Set SCUART transfer with odd parity  \hideinitializer */
+#define SCUART_PARITY_EVEN    (0UL)                             /*!< Set SCUART transfer with even parity \hideinitializer */
+
+#define SCUART_STOP_BIT_1     (SC_CTL_NSB_Msk)                  /*!< Set SCUART transfer with one stop bit  \hideinitializer */
+#define SCUART_STOP_BIT_2     (0UL)                             /*!< Set SCUART transfer with two stop bits \hideinitializer */
+
+/**@}*/ /* end of group SCUART_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions
+  @{
+*/
+
+/* TX Macros */
+/**
+  * @brief Write Data to Tx data register
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  * @param[in]  u8Data  Data byte to transmit.
+  *
+  * @return     None
+  *
+  * @details    By writing data to DAT register, the SC will send out an 8-bit data.
+  * \hideinitializer
+  */
+#define SCUART_WRITE(sc, u8Data)    ((sc)->DAT = (u8Data))
+
+/**
+  * @brief      Get Tx FIFO empty flag status from register
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  *
+  * @return     Transmit FIFO empty status
+  * @retval     0                       Transmit FIFO is not empty
+  * @retval     SC_STATUS_TXEMPTY_Msk   Transmit FIFO is empty
+  *
+  * @details    When the last byte of Tx buffer has been transferred to Transmitter Shift Register, hardware sets TXEMPTY (SC_STATUS[9]) high.
+  *             It will be cleared when writing data into DAT (SC_DAT[7:0]).
+  * \hideinitializer
+  */
+#define SCUART_GET_TX_EMPTY(sc)     ((sc)->STATUS & SC_STATUS_TXEMPTY_Msk)
+
+/**
+  * @brief Get Tx FIFO full flag status from register
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  *
+  * @return     Transmit FIFO full status
+  * @retval     0                       Transmit FIFO is not full
+  * @retval     SC_STATUS_TXFULL_Msk    Transmit FIFO is full
+  *
+  * @details    TXFULL (SC_STATUS[10]) is set when Tx buffer counts equals to 4, otherwise is cleared by hardware.
+  * \hideinitializer
+  */
+#define SCUART_GET_TX_FULL(sc)      ((sc)->STATUS & SC_STATUS_TXFULL_Msk)
+
+/**
+  * @brief      Wait specified smartcard port transmission complete
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  *
+  * @return     None
+  *
+  * @details    TXACT (SC_STATUS[31]) is cleared automatically when Tx transfer is finished or the last byte transmission has completed.
+  *
+  * @note       This macro blocks until transmit complete.
+  * \hideinitializer
+  */
+#define SCUART_WAIT_TX_EMPTY(sc)    while(((sc)->STATUS & SC_STATUS_TXACT_Msk) == SC_STATUS_TXACT_Msk)
+
+/**
+  * @brief      Check specified smartcard port transmit FIFO is full or not
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  *
+  * @return     Transmit FIFO full status
+  * @retval     0       Transmit FIFO is not full
+  * @retval     1       Transmit FIFO is full
+  *
+  * @details    TXFULL (SC_STATUS[10]) indicates Tx buffer full or not.
+  *             This bit is set when Tx buffer counts equals to 4, otherwise is cleared by hardware.
+  * \hideinitializer
+  */
+#define SCUART_IS_TX_FULL(sc)       (((sc)->STATUS & SC_STATUS_TXFULL_Msk)? 1 : 0)
+
+/**
+  * @brief      Check specified smartcard port transmission is over
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  *
+  * @return     Transmit complete status
+  * @retval     0       Transmit is not complete
+  * @retval     1       Transmit complete
+  *
+  * @details    TXACT (SC_STATUS[31]) indicates Tx Transmit is complete or not.
+  * \hideinitializer
+  */
+#define SCUART_IS_TX_EMPTY(sc)      (((sc)->STATUS & SC_STATUS_TXACT_Msk)? 0 : 1)
+
+/**
+  * @brief      Check specified smartcard port transmit FIFO empty status
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  *
+  * @return     Transmit FIFO empty status
+  * @retval     0       Transmit FIFO is not empty
+  * @retval     1       Transmit FIFO is empty
+  *
+  * @details    TXEMPTY (SC_STATUS[9]) is set by hardware when the last byte of Tx buffer has been transferred to Transmitter Shift Register.
+  * \hideinitializer
+  */
+#define SCUART_IS_TX_FIFO_EMPTY(sc) (((sc)->STATUS & SC_STATUS_TXEMPTY_Msk)? 1 : 0)
+
+/**
+  * @brief      Check specified Smartcard port Transmission Status
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  *
+  * @retval     0       Transmit is completed
+  * @retval     1       Transmit is active
+  *
+  * @details    TXACT (SC_STATUS[31]) is set by hardware when Tx transfer is in active and the STOP bit of the last byte has been transmitted.
+  * \hideinitializer
+  */
+#define SCUART_IS_TX_ACTIVE(sc)     (((sc)->STATUS & SC_STATUS_TXACT_Msk)? 1 : 0)
+
+
+/* RX Macros */
+/**
+  * @brief      Read Rx data register
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  *
+  * @return     The oldest data byte in RX FIFO
+  *
+  * @details    By reading DAT register, the SC will return an 8-bit received data.
+  * \hideinitializer
+  */
+#define SCUART_READ(sc)         ((sc)->DAT)
+
+/**
+  * @brief      Get Rx FIFO empty flag status from register
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  *
+  * @return     Receive FIFO empty status
+  * @retval     0                       Receive FIFO is not empty
+  * @retval     SC_STATUS_RXEMPTY_Msk   Receive FIFO is empty
+  *
+  * @details    When the last byte of Rx buffer has been read by CPU, hardware sets RXEMPTY (SC_STATUS[1]) high.
+  *             It will be cleared when SC receives any new data.
+  * \hideinitializer
+  */
+#define SCUART_GET_RX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_RXEMPTY_Msk)
+
+/**
+  * @brief      Get Rx FIFO full flag status from register
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  *
+  * @return     Receive FIFO full status
+  * @retval     0                       Receive FIFO is not full
+  * @retval     SC_STATUS_TXFULL_Msk    Receive FIFO is full
+  *
+  * @details    RXFULL (SC_STATUS[2]) is set when Rx buffer counts equals to 4, otherwise it is cleared by hardware.
+  * \hideinitializer
+  */
+#define SCUART_GET_RX_FULL(sc)  ((sc)->STATUS & SC_STATUS_RXFULL_Msk)
+
+/**
+  * @brief      Check if receive data number in FIFO reach FIFO trigger level or not
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  *
+  * @return     Receive FIFO data status
+  * @retval     0       The number of bytes in receive FIFO is less than trigger level
+  * @retval     1       The number of bytes in receive FIFO equals or larger than trigger level
+  *
+  * @details    RDAIF (SC_INTSTS[0]) is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.
+  *
+  * @note       If receive trigger level is \b not 1 byte, this macro return 0 does not necessary indicates there is no data in FIFO.
+  * \hideinitializer
+  */
+#define SCUART_IS_RX_READY(sc)  (((sc)->INTSTS & SC_INTSTS_RDAIF_Msk)? 1 : 0)
+
+/**
+  * @brief      Check specified smartcard port receive FIFO is full or not
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  *
+  * @return     Receive FIFO full status
+  * @retval     0       Receive FIFO is not full
+  * @retval     1       Receive FIFO is full
+  *
+  * @details    RXFULLF( SC_STATUS[2]) is set when Rx buffer counts equals to 4, otherwise it is cleared by hardware.
+  * \hideinitializer
+  */
+#define SCUART_IS_RX_FULL(sc)   (((sc)->STATUS & SC_STATUS_RXFULL_Msk)? 1 : 0)
+
+
+/* Interrupt Macros */
+/**
+  * @brief      Enable specified interrupts
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  * @param[in]  u32Mask Interrupt masks to enable, a combination of following bits,
+  *                         - \ref SC_INTEN_RXTOIEN_Msk
+  *                         - \ref SC_INTEN_TERRIEN_Msk
+  *                         - \ref SC_INTEN_TBEIEN_Msk
+  *                         - \ref SC_INTEN_RDAIEN_Msk
+  *
+  * @return     None
+  *
+  * @details    The macro is used to enable receiver buffer time-out interrupt, transfer error interrupt,
+  *             transmit buffer empty interrupt or receive data reach trigger level interrupt.
+  * \hideinitializer
+  */
+#define SCUART_ENABLE_INT(sc, u32Mask)  ((sc)->INTEN |= (u32Mask))
+
+/**
+  * @brief      Disable specified interrupts
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  * @param[in]  u32Mask Interrupt masks to disable, a combination of following bits,
+  *                         - \ref SC_INTEN_RXTOIEN_Msk
+  *                         - \ref SC_INTEN_TERRIEN_Msk
+  *                         - \ref SC_INTEN_TBEIEN_Msk
+  *                         - \ref SC_INTEN_RDAIEN_Msk
+  *
+  * @return     None
+  *
+  * @details    The macro is used to disable receiver buffer time-out interrupt, transfer error interrupt,
+  *             transmit buffer empty interrupt or receive data reach trigger level interrupt.
+  * \hideinitializer
+  */
+#define SCUART_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask))
+
+/**
+  * @brief      Get specified interrupt flag/status
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  * @param[in] u32Type  Interrupt flag/status to check, could be one of following value
+  *                         - \ref SC_INTSTS_RXTOIF_Msk
+  *                         - \ref SC_INTSTS_TERRIF_Msk
+  *                         - \ref SC_INTSTS_TBEIF_Msk
+  *                         - \ref SC_INTSTS_RDAIF_Msk
+  *
+  * @return     The status of specified interrupt
+  * @retval     0       Specified interrupt does not happened
+  * @retval     1       Specified interrupt happened
+  *
+  * @details    The macro is used to get receiver buffer time-out interrupt status, transfer error interrupt status,
+  *             transmit buffer empty interrupt status or receive data reach interrupt status.
+  * \hideinitializer
+  */
+#define SCUART_GET_INT_FLAG(sc, u32Type)    (((sc)->INTSTS & (u32Type))? 1 : 0)
+
+/**
+  * @brief      Clear specified interrupt flag/status
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  * @param[in] u32Type  Interrupt flag/status to clear, only \ref SC_INTSTS_TERRIF_Msk valid for this macro.
+  *
+  * @return     None
+  *
+  * @details    The macro is used to clear transfer error interrupt flag.
+  * \hideinitializer
+  */
+#define SCUART_CLR_INT_FLAG(sc, u32Type)    ((sc)->INTSTS = (u32Type))
+
+/**
+  * @brief      Get receive error flag/status
+  *
+  * @param[in]  sc  The pointer of smartcard module.
+  *
+  * @return     Current receive error status, could one of following errors:
+  * @retval     SC_STATUS_PEF_Msk   Parity error
+  * @retval     SC_STATUS_FEF_Msk   Frame error
+  * @retval     SC_STATUS_BEF_Msk   Break error
+  *
+  * @details    The macro is used to get receiver parity error status, frame error status or break error status.
+  * \hideinitializer
+  */
+#define SCUART_GET_ERR_FLAG(sc)             ((sc)->STATUS & (SC_STATUS_PEF_Msk | SC_STATUS_FEF_Msk | SC_STATUS_BEF_Msk))
+
+/**
+  * @brief      Clear specified receive error flag/status
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  * @param[in]  u32Mask Receive error flag/status to clear, combination following values
+  *                         - \ref SC_STATUS_PEF_Msk
+  *                         - \ref SC_STATUS_FEF_Msk
+  *                         - \ref SC_STATUS_BEF_Msk
+  *
+  * @return     None
+  *
+  * @details    The macro is used to clear receiver parity error flag, frame error flag or break error flag.
+  * \hideinitializer
+  */
+#define SCUART_CLR_ERR_FLAG(sc, u32Mask)    ((sc)->STATUS = (u32Mask))
+
+void SCUART_Close(SC_T* sc);
+uint32_t SCUART_Open(SC_T* sc, uint32_t u32Baudrate);
+uint32_t SCUART_Read(SC_T* sc, uint8_t pu8RxBuf[], uint32_t u32ReadBytes);
+uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits);
+void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC);
+void SCUART_Write(SC_T* sc, uint8_t pu8TxBuf[], uint32_t u32WriteBytes);
+
+/**@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group SCUART_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_SCUART_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_sdh.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_sdh.h
new file mode 100644
index 0000000000..3304e1af30
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_sdh.h
@@ -0,0 +1,203 @@
+/**************************************************************************//**
+ * @file     nu_sdh.h
+ * @version  V1.00
+ * @brief    M2354 SDH driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __NU_SDH_H__
+#define __NU_SDH_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include 
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup SDH_Driver SDH Driver
+  @{
+*/
+
+
+/** @addtogroup SDH_EXPORTED_CONSTANTS SDH Exported Constants
+  @{
+*/
+
+#define SDH_ERR_ID       0xFFFF0100UL /*!< SDH error ID  \hideinitializer */
+
+#define SDH_TIMEOUT      (SDH_ERR_ID|0x01UL) /*!< Timeout  \hideinitializer */
+#define SDH_NO_MEMORY    (SDH_ERR_ID|0x02UL) /*!< OOM  \hideinitializer */
+
+/* -- function return value */
+#define    Successful  0U   /*!< Success  \hideinitializer */
+#define    Fail        1U   /*!< Failed  \hideinitializer */
+
+/* --- define type of SD card or MMC */
+#define SDH_TYPE_UNKNOWN     0UL /*!< Unknown card type  \hideinitializer */
+#define SDH_TYPE_SD_HIGH     1UL /*!< SDHC card  \hideinitializer */
+#define SDH_TYPE_SD_LOW      2UL /*!< SD card  \hideinitializer */
+#define SDH_TYPE_MMC         3UL /*!< MMC card  \hideinitializer */
+#define SDH_TYPE_EMMC        4UL /*!< eMMC card  \hideinitializer */
+
+/* SD error */
+#define SDH_NO_SD_CARD       (SDH_ERR_ID|0x10UL) /*!< Card removed  \hideinitializer */
+#define SDH_ERR_DEVICE       (SDH_ERR_ID|0x11UL) /*!< Device error  \hideinitializer */
+#define SDH_INIT_TIMEOUT     (SDH_ERR_ID|0x12UL) /*!< Card init timeout  \hideinitializer */
+#define SDH_SELECT_ERROR     (SDH_ERR_ID|0x13UL) /*!< Card select error  \hideinitializer */
+#define SDH_WRITE_PROTECT    (SDH_ERR_ID|0x14UL) /*!< Card write protect  \hideinitializer */
+#define SDH_INIT_ERROR       (SDH_ERR_ID|0x15UL) /*!< Card init error  \hideinitializer */
+#define SDH_CRC7_ERROR       (SDH_ERR_ID|0x16UL) /*!< CRC 7 error  \hideinitializer */
+#define SDH_CRC16_ERROR      (SDH_ERR_ID|0x17UL) /*!< CRC 16 error  \hideinitializer */
+#define SDH_CRC_ERROR        (SDH_ERR_ID|0x18UL) /*!< CRC error  \hideinitializer */
+#define SDH_CMD8_ERROR       (SDH_ERR_ID|0x19UL) /*!< Command 8 error  \hideinitializer */
+
+#define MMC_FREQ        20000UL   /*!< output 20MHz to MMC  \hideinitializer */
+#define SD_FREQ         25000UL   /*!< output 25MHz to SD  \hideinitializer */
+#define SDHC_FREQ       50000UL   /*!< output 50MHz to SDH \hideinitializer */
+
+#define    CardDetect_From_GPIO  (1UL << 8)   /*!< Card detection pin is GPIO \hideinitializer */
+#define    CardDetect_From_DAT3  (1UL << 9)   /*!< Card detection pin is DAT3 \hideinitializer */
+
+/**@}*/ /* end of group SDH_EXPORTED_CONSTANTS */
+
+/** @addtogroup SDH_EXPORTED_TYPEDEF SDH Exported Type Defines
+  @{
+*/
+#if defined ( __ARMCC_VERSION )
+#pragma pack(push)
+#pragma pack(1)
+#endif
+typedef struct SDH_info_t
+{
+    unsigned int    CardType;       /*!< SDHC, SD, or MMC */
+    unsigned int    RCA;            /*!< Relative card address */
+    unsigned char   IsCardInsert;   /*!< Card insert state */
+    unsigned int    totalSectorN;   /*!< Total sector number */
+    unsigned int    diskSize;       /*!< Disk size in K bytes */
+    int             sectorSize;     /*!< Sector size in bytes */
+} SDH_INFO_T;                       /*!< Structure holds SD card info */
+#if defined ( __ARMCC_VERSION )
+#pragma pack(pop)
+#endif
+/**@}*/ /* end of group SDH_EXPORTED_TYPEDEF */
+
+/** @cond HIDDEN_SYMBOLS */
+extern SDH_INFO_T SD0;
+extern uint8_t volatile g_u8SDDataReadyFlag;
+extern uint8_t g_u8R3Flag;
+
+/** @endcond HIDDEN_SYMBOLS */
+
+/** @addtogroup SDH_EXPORTED_FUNCTIONS SDH Exported Functions
+  @{
+*/
+
+/**
+ *  @brief    Enable specified interrupt.
+ *
+ *  @param[in]    sdh    The pointer of the specified SDH module.
+ *  @param[in]    u32IntMask    Interrupt type mask:
+ *                           \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN_Msk /
+ *                           \ref SDH_INTEN_CDSRC_Msk / \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk /
+ *                           \ref SDH_INTEN_WKIEN_Msk
+ *
+ *  @return   None.
+ * \hideinitializer
+ */
+#define SDH_ENABLE_INT(sdh, u32IntMask)    ((sdh)->INTEN |= (u32IntMask))
+
+/**
+ *  @brief    Disable specified interrupt.
+ *
+ *  @param[in]    sdh    The pointer of the specified SDH module.
+ *  @param[in]    u32IntMask    Interrupt type mask:
+ *                           \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN_Msk /
+ *                           \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk / \ref SDH_INTEN_WKIEN_Msk / \ref SDH_INTEN_CDSRC_Msk /
+ *
+ *  @return   None.
+ * \hideinitializer
+ */
+#define SDH_DISABLE_INT(sdh, u32IntMask)    ((sdh)->INTEN &= ~(u32IntMask))
+
+/**
+ *  @brief    Get specified interrupt flag/status.
+ *
+ *  @param[in]    sdh    The pointer of the specified SDH module.
+ *  @param[in]    u32IntMask    Interrupt type mask:
+ *                           \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CRC7_Msk /
+ *                           \ref SDH_INTSTS_CRC16_Msk / \ref SDH_INTSTS_CRCSTS_Msk / \ref SDH_INTSTS_DAT0STS_Msk /
+ *                           \ref SDH_INTSTS_CDIF_Msk / \ref SDH_INTSTS_RTOIF_Msk /
+ *                           \ref SDH_INTSTS_DITOIF_Msk / \ref SDH_INTSTS_CDSTS_Msk /
+ *                           \ref SDH_INTSTS_DAT1STS_Msk
+ *
+ *
+ *  @return  0 = The specified interrupt is not happened.
+ *           1 = The specified interrupt is happened.
+ * \hideinitializer
+ */
+#define SDH_GET_INT_FLAG(sdh, u32IntMask) (((sdh)->INTSTS & (u32IntMask))?1:0)
+
+
+/**
+ *  @brief    Clear specified interrupt flag/status.
+ *
+ *  @param[in]    sdh    The pointer of the specified SDH module.
+ *  @param[in]    u32IntMask    Interrupt type mask:
+ *                           \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CDIF_Msk /
+ *                           \ref SDH_INTSTS_RTOIF_Msk / \ref SDH_INTSTS_DITOIF_Msk
+ *
+ *
+ *  @return   None.
+ * \hideinitializer
+ */
+#define SDH_CLR_INT_FLAG(sdh, u32IntMask) ((sdh)->INTSTS = (u32IntMask))
+
+
+/**
+ *  @brief    Check SD Card inserted or removed.
+ *
+ *  @param[in]    sdh    The pointer of the specified SDH module.
+ *
+ *  @return   1: Card inserted.
+ *            0: Card removed.
+ * \hideinitializer
+ */
+#define SDH_IS_CARD_PRESENT(sdh) ((((sdh) == SDH0)||((sdh) == SDH0_NS))? SD0.IsCardInsert : 0)
+
+/**
+ *  @brief    Get SD Card capacity.
+ *
+ *  @param[in]    sdh    The pointer of the specified SDH module.
+ *
+ *  @return   SD Card capacity. (unit: KByte)
+ * \hideinitializer
+ */
+#define SDH_GET_CARD_CAPACITY(sdh)  ((((sdh) == SDH0)||((sdh) == SDH0_NS))? SD0.diskSize : 0)
+
+
+void SDH_Open(SDH_T *sdh, uint32_t u32CardDetSrc);
+uint32_t SDH_Probe(SDH_T *sdh);
+uint32_t SDH_Read(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount);
+uint32_t SDH_Write(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount);
+
+uint32_t SDH_CardDetection(SDH_T *sdh);
+void SDH_Open_Disk(SDH_T *sdh, uint32_t u32CardDetSrc);
+void SDH_Close_Disk(SDH_T *sdh);
+
+/**@}*/ /* end of group SDH_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group SDH_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* end of __NU_SDH_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_spi.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_spi.h
new file mode 100644
index 0000000000..067a56f6eb
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_spi.h
@@ -0,0 +1,582 @@
+/******************************************************************************
+ * @file     nu_spi.h
+ * @version  V3.00
+ * @brief    M2354 series SPI driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_SPI_H__
+#define __NU_SPI_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup SPI_Driver SPI Driver
+  @{
+*/
+
+/** @addtogroup SPI_EXPORTED_CONSTANTS SPI Exported Constants
+  @{
+*/
+
+#define SPI_MODE_0        (SPI_CTL_TXNEG_Msk)                             /*!< CLKPOL=0; RXNEG=0; TXNEG=1 */
+#define SPI_MODE_1        (SPI_CTL_RXNEG_Msk)                             /*!< CLKPOL=0; RXNEG=1; TXNEG=0 */
+#define SPI_MODE_2        (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk)        /*!< CLKPOL=1; RXNEG=1; TXNEG=0 */
+#define SPI_MODE_3        (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk)        /*!< CLKPOL=1; RXNEG=0; TXNEG=1 */
+
+#define SPI_SLAVE         (SPI_CTL_SLAVE_Msk)                             /*!< Set as slave */
+#define SPI_MASTER        (0x0UL)                                         /*!< Set as master */
+
+#define SPI_SS                (SPI_SSCTL_SS_Msk)                          /*!< Set SS */
+#define SPI_SS_ACTIVE_HIGH    (SPI_SSCTL_SSACTPOL_Msk)                    /*!< SS active high */
+#define SPI_SS_ACTIVE_LOW     (0x0UL)                                     /*!< SS active low */
+
+/* SPI Interrupt Mask */
+#define SPI_UNIT_INT_MASK                (0x001UL)                        /*!< Unit transfer interrupt mask */
+#define SPI_SSACT_INT_MASK               (0x002UL)                        /*!< Slave selection signal active interrupt mask */
+#define SPI_SSINACT_INT_MASK             (0x004UL)                        /*!< Slave selection signal inactive interrupt mask */
+#define SPI_SLVUR_INT_MASK               (0x008UL)                        /*!< Slave under run interrupt mask */
+#define SPI_SLVBE_INT_MASK               (0x010UL)                        /*!< Slave bit count error interrupt mask */
+#define SPI_TXUF_INT_MASK                (0x040UL)                        /*!< Slave TX underflow interrupt mask */
+#define SPI_FIFO_TXTH_INT_MASK           (0x080UL)                        /*!< FIFO TX threshold interrupt mask */
+#define SPI_FIFO_RXTH_INT_MASK           (0x100UL)                        /*!< FIFO RX threshold interrupt mask */
+#define SPI_FIFO_RXOV_INT_MASK           (0x200UL)                        /*!< FIFO RX overrun interrupt mask */
+#define SPI_FIFO_RXTO_INT_MASK           (0x400UL)                        /*!< FIFO RX time-out interrupt mask */
+
+/* SPI Status Mask */
+#define SPI_BUSY_MASK                    (0x01UL)                         /*!< Busy status mask */
+#define SPI_RX_EMPTY_MASK                (0x02UL)                         /*!< RX empty status mask */
+#define SPI_RX_FULL_MASK                 (0x04UL)                         /*!< RX full status mask */
+#define SPI_TX_EMPTY_MASK                (0x08UL)                         /*!< TX empty status mask */
+#define SPI_TX_FULL_MASK                 (0x10UL)                         /*!< TX full status mask */
+#define SPI_TXRX_RESET_MASK              (0x20UL)                         /*!< TX or RX reset status mask */
+#define SPI_SPIEN_STS_MASK               (0x40UL)                         /*!< SPIEN status mask */
+#define SPI_SSLINE_STS_MASK              (0x80UL)                         /*!< SPIx_SS line status mask */
+
+/* SPI Status2 Mask */
+#define SPI_SLVBENUM_MASK                (0x01UL)                         /*!< Effective bit number of uncompleted RX data status mask */
+
+
+/* I2S Data Width */
+#define SPII2S_DATABIT_8           (0UL << SPI_I2SCTL_WDWIDTH_Pos)        /*!< I2S data width is 8-bit */
+#define SPII2S_DATABIT_16          (1UL << SPI_I2SCTL_WDWIDTH_Pos)        /*!< I2S data width is 16-bit */
+#define SPII2S_DATABIT_24          (2UL << SPI_I2SCTL_WDWIDTH_Pos)        /*!< I2S data width is 24-bit */
+#define SPII2S_DATABIT_32          (3UL << SPI_I2SCTL_WDWIDTH_Pos)        /*!< I2S data width is 32-bit */
+
+/* I2S Audio Format */
+#define SPII2S_MONO                SPI_I2SCTL_MONO_Msk                    /*!< Monaural channel */
+#define SPII2S_STEREO              (0UL)                                  /*!< Stereo channel */
+
+/* I2S Data Format */
+#define SPII2S_FORMAT_I2S          (0UL << SPI_I2SCTL_FORMAT_Pos)         /*!< I2S data format */
+#define SPII2S_FORMAT_MSB          (1UL << SPI_I2SCTL_FORMAT_Pos)         /*!< MSB justified data format */
+#define SPII2S_FORMAT_PCMA         (2UL << SPI_I2SCTL_FORMAT_Pos)         /*!< PCM mode A data format */
+#define SPII2S_FORMAT_PCMB         (3UL << SPI_I2SCTL_FORMAT_Pos)         /*!< PCM mode B data format */
+
+/* I2S Operation mode */
+#define SPII2S_MODE_SLAVE          SPI_I2SCTL_SLAVE_Msk                   /*!< As slave mode */
+#define SPII2S_MODE_MASTER         (0UL)                                  /*!< As master mode */
+
+/* I2S TX FIFO Threshold */
+#define SPII2S_FIFO_TX_LEVEL_WORD_0    (0UL)                              /*!< TX threshold is 0 word */
+#define SPII2S_FIFO_TX_LEVEL_WORD_1    (1UL << SPI_FIFOCTL_TXTH_Pos)      /*!< TX threshold is 1 word */
+#define SPII2S_FIFO_TX_LEVEL_WORD_2    (2UL << SPI_FIFOCTL_TXTH_Pos)      /*!< TX threshold is 2 words */
+#define SPII2S_FIFO_TX_LEVEL_WORD_3    (3UL << SPI_FIFOCTL_TXTH_Pos)      /*!< TX threshold is 3 words */
+/* I2S RX FIFO Threshold */
+#define SPII2S_FIFO_RX_LEVEL_WORD_1    (0UL)                              /*!< RX threshold is 1 word */
+#define SPII2S_FIFO_RX_LEVEL_WORD_2    (1UL << SPI_FIFOCTL_RXTH_Pos)      /*!< RX threshold is 2 words */
+#define SPII2S_FIFO_RX_LEVEL_WORD_3    (2UL << SPI_FIFOCTL_RXTH_Pos)      /*!< RX threshold is 3 words */
+#define SPII2S_FIFO_RX_LEVEL_WORD_4    (3UL << SPI_FIFOCTL_RXTH_Pos)      /*!< RX threshold is 4 words */
+
+/* I2S Record Channel */
+#define SPII2S_MONO_RIGHT          (0UL)                                  /*!< Record mono right channel */
+#define SPII2S_MONO_LEFT           SPI_I2SCTL_RXLCH_Msk                   /*!< Record mono left channel */
+
+/* I2S Channel */
+#define SPII2S_RIGHT               (0UL)                                  /*!< Select right channel */
+#define SPII2S_LEFT                (1UL)                                  /*!< Select left channel */
+
+/* I2S Interrupt Mask */
+#define SPII2S_FIFO_TXTH_INT_MASK           (0x01UL)                      /*!< TX FIFO threshold interrupt mask */
+#define SPII2S_FIFO_RXTH_INT_MASK           (0x02UL)                      /*!< RX FIFO threshold interrupt mask */
+#define SPII2S_FIFO_RXOV_INT_MASK           (0x04UL)                      /*!< RX FIFO overrun interrupt mask */
+#define SPII2S_FIFO_RXTO_INT_MASK           (0x08UL)                      /*!< RX FIFO time-out interrupt mask */
+#define SPII2S_TXUF_INT_MASK                (0x10UL)                      /*!< TX FIFO underflow interrupt mask */
+#define SPII2S_RIGHT_ZC_INT_MASK            (0x20UL)                      /*!< Right channel zero cross interrupt mask */
+#define SPII2S_LEFT_ZC_INT_MASK             (0x40UL)                      /*!< Left channel zero cross interrupt mask */
+#define SPII2S_SLAVE_ERR_INT_MASK           (0x80UL)                      /*!< Bit clock loss interrupt mask */
+
+/**@}*/ /* end of group SPI_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Clear the unit transfer interrupt flag.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Write 1 to UNITIF bit of SPI_STATUS register to clear the unit transfer interrupt flag.
+  */
+#define SPI_CLR_UNIT_TRANS_INT_FLAG(spi)   ( (spi)->STATUS = SPI_STATUS_UNITIF_Msk )
+
+/**
+  * @brief      Disable Slave 3-wire mode.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Clear SLV3WIRE bit of SPI_SSCTL register to disable Slave 3-wire mode.
+  */
+#define SPI_DISABLE_3WIRE_MODE(spi)   ( (spi)->SSCTL &= ~SPI_SSCTL_SLV3WIRE_Msk )
+
+/**
+  * @brief      Enable Slave 3-wire mode.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Set SLV3WIRE bit of SPI_SSCTL register to enable Slave 3-wire mode.
+  */
+#define SPI_ENABLE_3WIRE_MODE(spi)   ( (spi)->SSCTL |= SPI_SSCTL_SLV3WIRE_Msk )
+
+/**
+  * @brief      Trigger RX PDMA function.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Set RXPDMAEN bit of SPI_PDMACTL register to enable RX PDMA transfer function.
+  */
+#define SPI_TRIGGER_RX_PDMA(spi)   ( (spi)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk )
+
+/**
+  * @brief      Trigger TX PDMA function.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Set TXPDMAEN bit of SPI_PDMACTL register to enable TX PDMA transfer function.
+  */
+#define SPI_TRIGGER_TX_PDMA(spi)   ( (spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk )
+
+/**
+  * @brief      Trigger TX and RX PDMA function.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Set TXPDMAEN bit and RXPDMAEN bit of SPI_PDMACTL register to enable TX and RX PDMA transfer function.
+  */
+#define SPI_TRIGGER_TX_RX_PDMA(spi)   ( (spi)->PDMACTL |= (SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk) )
+
+/**
+  * @brief      Disable RX PDMA transfer.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Clear RXPDMAEN bit of SPI_PDMACTL register to disable RX PDMA transfer function.
+  */
+#define SPI_DISABLE_RX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
+
+/**
+  * @brief      Disable TX PDMA transfer.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Clear TXPDMAEN bit of SPI_PDMACTL register to disable TX PDMA transfer function.
+  */
+#define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
+
+/**
+  * @brief      Disable TX and RX PDMA transfer.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Clear TXPDMAEN bit and RXPDMAEN bit of SPI_PDMACTL register to disable TX and RX PDMA transfer function.
+  */
+#define SPI_DISABLE_TX_RX_PDMA(spi)   ( (spi)->PDMACTL &= ~(SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk) )
+
+/**
+  * @brief      Get the count of available data in RX FIFO.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     The count of available data in RX FIFO.
+  * @details    Read RXCNT (SPI_STATUS[27:24]) to get the count of available data in RX FIFO.
+  */
+#define SPI_GET_RX_FIFO_COUNT(spi)   ( ((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos )
+
+/**
+  * @brief      Get the RX FIFO empty flag.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @retval     0 RX FIFO is not empty.
+  * @retval     1 RX FIFO is empty.
+  * @details    Read RXEMPTY bit of SPI_STATUS register to get the RX FIFO empty flag.
+  */
+#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi)   ( ((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk) >> SPI_STATUS_RXEMPTY_Pos )
+
+/**
+  * @brief      Get the TX FIFO empty flag.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @retval     0 TX FIFO is not empty.
+  * @retval     1 TX FIFO is empty.
+  * @details    Read TXEMPTY bit of SPI_STATUS register to get the TX FIFO empty flag.
+  */
+#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi)   ( ((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk) >> SPI_STATUS_TXEMPTY_Pos )
+
+/**
+  * @brief      Get the TX FIFO full flag.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @retval     0 TX FIFO is not full.
+  * @retval     1 TX FIFO is full.
+  * @details    Read TXFULL bit of SPI_STATUS register to get the TX FIFO full flag.
+  */
+#define SPI_GET_TX_FIFO_FULL_FLAG(spi)   ( ((spi)->STATUS & SPI_STATUS_TXFULL_Msk) >> SPI_STATUS_TXFULL_Pos )
+
+/**
+  * @brief      Get the datum read from RX register.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     Data in RX register.
+  * @details    Read SPI_RX register to get the received datum.
+  */
+#define SPI_READ_RX(spi)   ( (spi)->RX )
+
+/**
+  * @brief      Write datum to TX register.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32TxData The datum which user attempt to transfer through SPI bus.
+  * @return     None.
+  * @details    Write u32TxData to SPI_TX register.
+  */
+#define SPI_WRITE_TX(spi, u32TxData)   ( (spi)->TX = (u32TxData) )
+
+/**
+  * @brief      Set SPIx_SS pin to high state.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Disable automatic slave selection function and set SPIx_SS pin to high state.
+  */
+#define SPI_SET_SS_HIGH(spi)   ( (spi)->SSCTL = ((spi)->SSCTL & (~SPI_SSCTL_AUTOSS_Msk)) | (SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk) )
+
+/**
+  * @brief      Set SPIx_SS pin to low state.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Disable automatic slave selection function and set SPIx_SS pin to low state.
+  */
+#define SPI_SET_SS_LOW(spi)   ( (spi)->SSCTL = ((spi)->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk))) | SPI_SSCTL_SS_Msk )
+
+/**
+  * @brief      Enable Byte Reorder function.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (SPI_CTL[7:4]).
+  */
+#define SPI_ENABLE_BYTE_REORDER(spi)   ( (spi)->CTL |=  SPI_CTL_REORDER_Msk )
+
+/**
+  * @brief      Disable Byte Reorder function.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Clear REORDER bit field of SPI_CTL register to disable Byte Reorder function.
+  */
+#define SPI_DISABLE_BYTE_REORDER(spi)   ( (spi)->CTL &= ~SPI_CTL_REORDER_Msk )
+
+/**
+  * @brief      Set the length of suspend interval.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15.
+  * @return     None.
+  * @details    Set the length of suspend interval according to u32SuspCycle.
+  *             The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one SPI bus clock cycle).
+  */
+#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle)   ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << SPI_CTL_SUSPITV_Pos) )
+
+/**
+  * @brief      Set the SPI transfer sequence with LSB first.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Set LSB bit of SPI_CTL register to set the SPI transfer sequence with LSB first.
+  */
+#define SPI_SET_LSB_FIRST(spi)   ( (spi)->CTL |= SPI_CTL_LSB_Msk )
+
+/**
+  * @brief      Set the SPI transfer sequence with MSB first.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Clear LSB bit of SPI_CTL register to set the SPI transfer sequence with MSB first.
+  */
+#define SPI_SET_MSB_FIRST(spi)   ( (spi)->CTL &= ~SPI_CTL_LSB_Msk )
+
+/**
+  * @brief      Set the data width of a SPI transaction.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32Width The bit width of one transaction.
+  * @return     None.
+  * @details    The data width can be 8 ~ 32 bits.
+  */
+#define SPI_SET_DATA_WIDTH(spi, u32Width)   ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_DWIDTH_Msk) | (((u32Width) & 0x1F) << SPI_CTL_DWIDTH_Pos) )
+
+/**
+  * @brief      Get the SPI busy state.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @retval     0 SPI controller is not busy.
+  * @retval     1 SPI controller is busy.
+  * @details    This macro will return the busy state of SPI controller.
+  */
+#define SPI_IS_BUSY(spi)   ( ((spi)->STATUS & SPI_STATUS_BUSY_Msk) >> SPI_STATUS_BUSY_Pos )
+
+/**
+  * @brief      Enable SPI controller.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Set SPIEN (SPI_CTL[0]) to enable SPI controller.
+  */
+#define SPI_ENABLE(spi)   ( (spi)->CTL |= SPI_CTL_SPIEN_Msk )
+
+/**
+  * @brief      Disable SPI controller.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return     None.
+  * @details    Clear SPIEN (SPI_CTL[0]) to disable SPI controller.
+  */
+#define SPI_DISABLE(spi)   ( (spi)->CTL &= ~SPI_CTL_SPIEN_Msk )
+
+/**
+  * @brief  Enable zero cross detection function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @param[in] u32ChMask The mask for left or right channel. Valid values are:
+  *                    - \ref SPII2S_RIGHT
+  *                    - \ref SPII2S_LEFT
+  * @return None
+  * @details This function will set RZCEN or LZCEN bit of SPI_I2SCTL register to enable zero cross detection function.
+  */
+__STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
+{
+    if(u32ChMask == SPII2S_RIGHT)
+    {
+        i2s->I2SCTL |= SPI_I2SCTL_RZCEN_Msk;
+    }
+    else
+    {
+        i2s->I2SCTL |= SPI_I2SCTL_LZCEN_Msk;
+    }
+}
+
+/**
+  * @brief  Disable zero cross detection function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @param[in] u32ChMask The mask for left or right channel. Valid values are:
+  *                    - \ref SPII2S_RIGHT
+  *                    - \ref SPII2S_LEFT
+  * @return None
+  * @details This function will clear RZCEN or LZCEN bit of SPI_I2SCTL register to disable zero cross detection function.
+  */
+__STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
+{
+    if(u32ChMask == SPII2S_RIGHT)
+    {
+        i2s->I2SCTL &= ~SPI_I2SCTL_RZCEN_Msk;
+    }
+    else
+    {
+        i2s->I2SCTL &= ~SPI_I2SCTL_LZCEN_Msk;
+    }
+}
+
+/**
+  * @brief  Enable I2S TX DMA function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will set TXPDMAEN bit of SPI_PDMACTL register to transmit data with PDMA.
+  */
+#define SPII2S_ENABLE_TXDMA(i2s)  ( (i2s)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk )
+
+/**
+  * @brief  Disable I2S TX DMA function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will clear TXPDMAEN bit of SPI_PDMACTL register to disable TX DMA function.
+  */
+#define SPII2S_DISABLE_TXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
+
+/**
+  * @brief  Enable I2S RX DMA function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will set RXPDMAEN bit of SPI_PDMACTL register to receive data with PDMA.
+  */
+#define SPII2S_ENABLE_RXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk )
+
+/**
+  * @brief  Disable I2S RX DMA function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will clear RXPDMAEN bit of SPI_PDMACTL register to disable RX DMA function.
+  */
+#define SPII2S_DISABLE_RXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
+
+/**
+  * @brief  Enable I2S TX function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will set TXEN bit of SPI_I2SCTL register to enable I2S TX function.
+  */
+#define SPII2S_ENABLE_TX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_TXEN_Msk )
+
+/**
+  * @brief  Disable I2S TX function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will clear TXEN bit of SPI_I2SCTL register to disable I2S TX function.
+  */
+#define SPII2S_DISABLE_TX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_TXEN_Msk )
+
+/**
+  * @brief  Enable I2S RX function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will set RXEN bit of SPI_I2SCTL register to enable I2S RX function.
+  */
+#define SPII2S_ENABLE_RX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_RXEN_Msk )
+
+/**
+  * @brief  Disable I2S RX function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will clear RXEN bit of SPI_I2SCTL register to disable I2S RX function.
+  */
+#define SPII2S_DISABLE_RX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_RXEN_Msk )
+
+/**
+  * @brief  Enable TX Mute function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will set MUTE bit of SPI_I2SCTL register to enable I2S TX mute function.
+  */
+#define SPII2S_ENABLE_TX_MUTE(i2s)  ( (i2s)->I2SCTL |= SPI_I2SCTL_MUTE_Msk )
+
+/**
+  * @brief  Disable TX Mute function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will clear MUTE bit of SPI_I2SCTL register to disable I2S TX mute function.
+  */
+#define SPII2S_DISABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_MUTE_Msk )
+
+/**
+  * @brief  Clear TX FIFO.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will clear TX FIFO. The internal TX FIFO pointer will be reset to FIFO start point.
+  */
+#define SPII2S_CLR_TX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk )
+
+/**
+  * @brief  Clear RX FIFO.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details This macro will clear RX FIFO. The internal RX FIFO pointer will be reset to FIFO start point.
+  */
+#define SPII2S_CLR_RX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk )
+
+/**
+  * @brief  This function sets the recording source channel when mono mode is used.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @param[in] u32Ch left or right channel. Valid values are:
+  *                - \ref SPII2S_MONO_LEFT
+  *                - \ref SPII2S_MONO_RIGHT
+  * @return None
+  * @details This function selects the recording source channel of monaural mode.
+  */
+__STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch)
+{
+    u32Ch == SPII2S_MONO_LEFT ?
+    (i2s->I2SCTL |= SPI_I2SCTL_RXLCH_Msk) :
+    (i2s->I2SCTL &= ~SPI_I2SCTL_RXLCH_Msk);
+}
+
+/**
+  * @brief  Write data to I2S TX FIFO.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @param[in] u32Data The value written to TX FIFO.
+  * @return None
+  * @details This macro will write a value to TX FIFO.
+  */
+#define SPII2S_WRITE_TX_FIFO(i2s, u32Data)  ( (i2s)->TX = (u32Data) )
+
+/**
+  * @brief  Read RX FIFO.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return The value read from RX FIFO.
+  * @details This function will return a value read from RX FIFO.
+  */
+#define SPII2S_READ_RX_FIFO(i2s) ( (i2s)->RX )
+
+/**
+  * @brief  Get the interrupt flag.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @param[in] u32Mask The mask value for all interrupt flags.
+  * @return The interrupt flags specified by the u32mask parameter.
+  * @details This macro will return the combination interrupt flags of SPI_I2SSTS register. The flags are specified by the u32mask parameter.
+  */
+#define SPII2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS & (u32Mask) )
+
+/**
+  * @brief  Clear the interrupt flag.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @param[in] u32Mask The mask value for all interrupt flags.
+  * @return None
+  * @details This macro will clear the interrupt flags specified by the u32mask parameter.
+  * @note Except TX and RX FIFO threshold interrupt flags, the other interrupt flags can be cleared by writing 1 to itself.
+  */
+#define SPII2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS = (u32Mask) )
+
+/**
+  * @brief  Get transmit FIFO level
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return TX FIFO level
+  * @details This macro will return the number of available words in TX FIFO.
+  */
+#define SPII2S_GET_TX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_TXCNT_Msk) >> SPI_I2SSTS_TXCNT_Pos )
+
+/**
+  * @brief  Get receive FIFO level
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return RX FIFO level
+  * @details This macro will return the number of available words in RX FIFO.
+  */
+#define SPII2S_GET_RX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_RXCNT_Msk) >> SPI_I2SSTS_RXCNT_Pos )
+
+/* Function prototype declaration */
+uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
+void SPI_Close(SPI_T *spi);
+void SPI_ClearRxFIFO(SPI_T *spi);
+void SPI_ClearTxFIFO(SPI_T *spi);
+void SPI_DisableAutoSS(SPI_T *spi);
+void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
+uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
+void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
+uint32_t SPI_GetBusClock(SPI_T *spi);
+void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
+void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
+uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask);
+void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask);
+uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask);
+uint32_t SPI_GetStatus2(SPI_T *spi, uint32_t u32Mask);
+
+uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat);
+void SPII2S_Close(SPI_T *i2s);
+void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask);
+void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask);
+uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock);
+void SPII2S_DisableMCLK(SPI_T *i2s);
+void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
+
+
+/**@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group SPI_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_SPI_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_sys.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_sys.h
new file mode 100644
index 0000000000..08c6246c7a
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_sys.h
@@ -0,0 +1,4313 @@
+/**************************************************************************//**
+ * @file     nu_sys.h
+ * @version  V3
+ * @brief    M2354 series System Manager (SYS) driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __NU_SYS_H__
+#define __NU_SYS_H__
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup SYS_Driver SYS Driver
+  @{
+*/
+
+/** @addtogroup SYS_EXPORTED_CONSTANTS SYS Exported Constants
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Module Reset Control Resister constant definitions.                                                    */
+/*---------------------------------------------------------------------------------------------------------*/
+#define PDMA0_RST   ((0x0UL<<24)|(uint32_t)SYS_IPRST0_PDMA0RST_Pos)     /*!< PDMA0 reset is one of the SYS_ResetModule parameter */
+#define EBI_RST     ((0x0UL<<24)|(uint32_t)SYS_IPRST0_EBIRST_Pos)       /*!< EBI reset is one of the SYS_ResetModule parameter */
+#define USBH_RST    ((0x0UL<<24)|(uint32_t)SYS_IPRST0_USBHRST_Pos)      /*!< USBH reset is one of the SYS_ResetModule parameter */
+#define SDH0_RST    ((0x0UL<<24)|(uint32_t)SYS_IPRST0_SDH0RST_Pos)      /*!< SDH0 reset is one of the SYS_ResetModule parameter */
+#define CRC_RST     ((0x0UL<<24)|(uint32_t)SYS_IPRST0_CRCRST_Pos)       /*!< CRC reset is one of the SYS_ResetModule parameter */
+#define CRPT_RST    ((0x0UL<<24)|(uint32_t)SYS_IPRST0_CRPTRST_Pos)      /*!< CRPT reset is one of the SYS_ResetModule parameter */
+#define KS_RST      ((0x0UL<<24)|(uint32_t)SYS_IPRST0_KSRST_Pos)        /*!< KS reset is one of the SYS_ResetModule parameter */
+#define PDMA1_RST   ((0x0UL<<24)|(uint32_t)SYS_IPRST0_PDMA1RST_Pos)     /*!< PDMA1 reset is one of the SYS_ResetModule parameter */
+
+#define GPIO_RST    ((0x4UL<<24)|(uint32_t)SYS_IPRST1_GPIORST_Pos)      /*!< GPIO reset is one of the SYS_ResetModule parameter */
+#define TMR0_RST    ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TMR0RST_Pos)      /*!< TMR0 reset is one of the SYS_ResetModule parameter */
+#define TMR1_RST    ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TMR1RST_Pos)      /*!< TMR1 reset is one of the SYS_ResetModule parameter */
+#define TMR2_RST    ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TMR2RST_Pos)      /*!< TMR2 reset is one of the SYS_ResetModule parameter */
+#define TMR3_RST    ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TMR3RST_Pos)      /*!< TMR3 reset is one of the SYS_ResetModule parameter */
+#define TMR4_RST    ((0x8UL<<24)|(uint32_t)SYS_IPRST2_TMR4RST_Pos)      /*!< TMR4 reset is one of the SYS_ResetModule parameter */
+#define TMR5_RST    ((0x8UL<<24)|(uint32_t)SYS_IPRST2_TMR5RST_Pos)      /*!< TMR5 reset is one of the SYS_ResetModule parameter */
+
+#define ACMP01_RST  ((0x4UL<<24)|(uint32_t)SYS_IPRST1_ACMP01RST_Pos)    /*!< ACMP01 reset is one of the SYS_ResetModule parameter */
+#define I2C0_RST    ((0x4UL<<24)|(uint32_t)SYS_IPRST1_I2C0RST_Pos)      /*!< I2C0 reset is one of the SYS_ResetModule parameter */
+#define I2C1_RST    ((0x4UL<<24)|(uint32_t)SYS_IPRST1_I2C1RST_Pos)      /*!< I2C1 reset is one of the SYS_ResetModule parameter */
+#define I2C2_RST    ((0x4UL<<24)|(uint32_t)SYS_IPRST1_I2C2RST_Pos)      /*!< I2C2 reset is one of the SYS_ResetModule parameter */
+#define QSPI0_RST   ((0x4UL<<24)|(uint32_t)SYS_IPRST1_QSPI0RST_Pos)     /*!< QSPI0 reset is one of the SYS_ResetModule parameter */
+#define SPI0_RST    ((0x4UL<<24)|(uint32_t)SYS_IPRST1_SPI0RST_Pos)      /*!< SPI0 reset is one of the SYS_ResetModule parameter */
+#define SPI1_RST    ((0x4UL<<24)|(uint32_t)SYS_IPRST1_SPI1RST_Pos)      /*!< SPI1 reset is one of the SYS_ResetModule parameter */
+#define SPI2_RST    ((0x4UL<<24)|(uint32_t)SYS_IPRST1_SPI2RST_Pos)      /*!< SPI2 reset is one of the SYS_ResetModule parameter */
+#define UART0_RST   ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART0RST_Pos)     /*!< UART0 reset is one of the SYS_ResetModule parameter */
+#define UART1_RST   ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART1RST_Pos)     /*!< UART1 reset is one of the SYS_ResetModule parameter */
+#define UART2_RST   ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART2RST_Pos)     /*!< UART2 reset is one of the SYS_ResetModule parameter */
+#define UART3_RST   ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART3RST_Pos)     /*!< UART3 reset is one of the SYS_ResetModule parameter */
+#define UART4_RST   ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART4RST_Pos)     /*!< UART4 reset is one of the SYS_ResetModule parameter */
+#define UART5_RST   ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART5RST_Pos)     /*!< UART5 reset is one of the SYS_ResetModule parameter */
+#define CAN0_RST    ((0x4UL<<24)|(uint32_t)SYS_IPRST1_CAN0RST_Pos)      /*!< CAN0 reset is one of the SYS_ResetModule parameter */
+#define OTG_RST     ((0x4UL<<24)|(uint32_t)SYS_IPRST1_OTGRST_Pos)       /*!< OTG reset is one of the SYS_ResetModule parameter */
+#define USBD_RST    ((0x4UL<<24)|(uint32_t)SYS_IPRST1_USBDRST_Pos)      /*!< USBD reset is one of the SYS_ResetModule parameter */
+#define EADC_RST    ((0x4UL<<24)|(uint32_t)SYS_IPRST1_EADCRST_Pos)      /*!< EADC reset is one of the SYS_ResetModule parameter */
+#define I2S0_RST    ((0x4UL<<24)|(uint32_t)SYS_IPRST1_I2S0RST_Pos)      /*!< I2S0 reset is one of the SYS_ResetModule parameter */
+#define LCD_RST     ((0x4UL<<24)|(uint32_t)SYS_IPRST1_LCDRST_Pos)       /*!< LCD reset is one of the SYS_ResetModule parameter */
+#define TRNG_RST    ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TRNGRST_Pos)      /*!< TRNG reset is one of the SYS_ResetModule parameter */
+
+#define SC0_RST     ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SC0RST_Pos)       /*!< SC0 reset is one of the SYS_ResetModule parameter */
+#define SC1_RST     ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SC1RST_Pos)       /*!< SC1 reset is one of the SYS_ResetModule parameter */
+#define SC2_RST     ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SC2RST_Pos)       /*!< SC2 reset is one of the SYS_ResetModule parameter */
+#define SPI3_RST    ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SPI3RST_Pos)      /*!< SPI3 reset is one of the SYS_ResetModule parameter */
+#define USCI0_RST   ((0x8UL<<24)|(uint32_t)SYS_IPRST2_USCI0RST_Pos)     /*!< USCI0 reset is one of the SYS_ResetModule parameter */
+#define USCI1_RST   ((0x8UL<<24)|(uint32_t)SYS_IPRST2_USCI1RST_Pos)     /*!< USCI1 reset is one of the SYS_ResetModule parameter */
+#define DAC_RST     ((0x8UL<<24)|(uint32_t)SYS_IPRST2_DACRST_Pos)       /*!< DAC reset is one of the SYS_ResetModule parameter */
+#define EPWM0_RST   ((0x8UL<<24)|(uint32_t)SYS_IPRST2_EPWM0RST_Pos)     /*!< EPWM0 reset is one of the SYS_ResetModule parameter */
+#define EPWM1_RST   ((0x8UL<<24)|(uint32_t)SYS_IPRST2_EPWM1RST_Pos)     /*!< EPWM1 reset is one of the SYS_ResetModule parameter */
+#define BPWM0_RST   ((0x8UL<<24)|(uint32_t)SYS_IPRST2_BPWM0RST_Pos)     /*!< BPWM0 reset is one of the SYS_ResetModule parameter */
+#define BPWM1_RST   ((0x8UL<<24)|(uint32_t)SYS_IPRST2_BPWM1RST_Pos)     /*!< BPWM1 reset is one of the SYS_ResetModule parameter */
+#define QEI0_RST    ((0x8UL<<24)|(uint32_t)SYS_IPRST2_QEI0RST_Pos)      /*!< QEI0 reset is one of the SYS_ResetModule parameter */
+#define QEI1_RST    ((0x8UL<<24)|(uint32_t)SYS_IPRST2_QEI1RST_Pos)      /*!< QEI1 reset is one of the SYS_ResetModule parameter */
+#define ECAP0_RST   ((0x8UL<<24)|(uint32_t)SYS_IPRST2_ECAP0RST_Pos)     /*!< ECAP0 reset is one of the SYS_ResetModule parameter */
+#define ECAP1_RST   ((0x8UL<<24)|(uint32_t)SYS_IPRST2_ECAP1RST_Pos)     /*!< ECAP1 reset is one of the SYS_ResetModule parameter */
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Brown Out Detector Threshold Voltage Selection constant definitions.                                   */
+/*---------------------------------------------------------------------------------------------------------*/
+#define SYS_BODCTL_BOD_RST_EN           (1UL<GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk)) | SYS_GPA_MFPL_PA0MFP_UART0_RXD;
+    SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA1MFP_Msk)) | SYS_GPA_MFPL_PA1MFP_UART0_TXD;
+*/
+
+
+/* PA.0 MFP */
+#define SYS_GPA_MFPL_PA0MFP_GPIO            (0x0UL<GPB_MFPL = (SYS->GPB_MFPL & (~ACMP0_N_PB3_Msk)) | ACMP0_N_PB3              /*!< Set PB3 function to ACMP0_N          */
+#define SET_ACMP0_O_PB7()        SYS->GPB_MFPL = (SYS->GPB_MFPL & (~ACMP0_O_PB7_Msk)) | ACMP0_O_PB7              /*!< Set PB7 function to ACMP0_O          */
+#define SET_ACMP0_O_PC1()        SYS->GPC_MFPL = (SYS->GPC_MFPL & (~ACMP0_O_PC1_Msk)) | ACMP0_O_PC1              /*!< Set PC1 function to ACMP0_O          */
+#define SET_ACMP0_O_PC12()       SYS->GPC_MFPH = (SYS->GPC_MFPH & (~ACMP0_O_PC12_Msk)) | ACMP0_O_PC12            /*!< Set PC12 function to ACMP0_O         */
+#define SET_ACMP0_P0_PA11()      SYS->GPA_MFPH = (SYS->GPA_MFPH & (~ACMP0_P0_PA11_Msk)) | ACMP0_P0_PA11          /*!< Set PA11 function to ACMP0_P0        */
+#define SET_ACMP0_P1_PB2()       SYS->GPB_MFPL = (SYS->GPB_MFPL & (~ACMP0_P1_PB2_Msk)) | ACMP0_P1_PB2            /*!< Set PB2 function to ACMP0_P1         */
+#define SET_ACMP0_P2_PB12()      SYS->GPB_MFPH = (SYS->GPB_MFPH & (~ACMP0_P2_PB12_Msk)) | ACMP0_P2_PB12          /*!< Set PB12 function to ACMP0_P2        */
+#define SET_ACMP0_P3_PB13()      SYS->GPB_MFPH = (SYS->GPB_MFPH & (~ACMP0_P3_PB13_Msk)) | ACMP0_P3_PB13          /*!< Set PB13 function to ACMP0_P3        */
+#define SET_ACMP0_WLAT_PA7()     SYS->GPA_MFPL = (SYS->GPA_MFPL & (~ACMP0_WLAT_PA7_Msk)) | ACMP0_WLAT_PA7        /*!< Set PA7 function to ACMP0_WLAT       */
+#define SET_ACMP1_N_PB5()        SYS->GPB_MFPL = (SYS->GPB_MFPL & (~ACMP1_N_PB5_Msk)) | ACMP1_N_PB5              /*!< Set PB5 function to ACMP1_N          */
+#define SET_ACMP1_O_PB6()        SYS->GPB_MFPL = (SYS->GPB_MFPL & (~ACMP1_O_PB6_Msk)) | ACMP1_O_PB6              /*!< Set PB6 function to ACMP1_O          */
+#define SET_ACMP1_O_PC11()       SYS->GPC_MFPH = (SYS->GPC_MFPH & (~ACMP1_O_PC11_Msk)) | ACMP1_O_PC11            /*!< Set PC11 function to ACMP1_O         */
+#define SET_ACMP1_O_PC0()        SYS->GPC_MFPL = (SYS->GPC_MFPL & (~ACMP1_O_PC0_Msk)) | ACMP1_O_PC0              /*!< Set PC0 function to ACMP1_O          */
+#define SET_ACMP1_P0_PA10()      SYS->GPA_MFPH = (SYS->GPA_MFPH & (~ACMP1_P0_PA10_Msk)) | ACMP1_P0_PA10          /*!< Set PA10 function to ACMP1_P0        */
+#define SET_ACMP1_P1_PB4()       SYS->GPB_MFPL = (SYS->GPB_MFPL & (~ACMP1_P1_PB4_Msk)) | ACMP1_P1_PB4            /*!< Set PB4 function to ACMP1_P1         */
+#define SET_ACMP1_P2_PB12()      SYS->GPB_MFPH = (SYS->GPB_MFPH & (~ACMP1_P2_PB12_Msk)) | ACMP1_P2_PB12          /*!< Set PB12 function to ACMP1_P2        */
+#define SET_ACMP1_P3_PB13()      SYS->GPB_MFPH = (SYS->GPB_MFPH & (~ACMP1_P3_PB13_Msk)) | ACMP1_P3_PB13          /*!< Set PB13 function to ACMP1_P3        */
+#define SET_ACMP1_WLAT_PA6()     SYS->GPA_MFPL = (SYS->GPA_MFPL & (~ACMP1_WLAT_PA6_Msk)) | ACMP1_WLAT_PA6        /*!< Set PA6 function to ACMP1_WLAT       */
+#define SET_BPWM0_CH0_PA0()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM0_CH0_PA0_Msk)) | BPWM0_CH0_PA0          /*!< Set PA0 function to BPWM0_CH0        */
+#define SET_BPWM0_CH0_PA11()     SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM0_CH0_PA11_Msk)) | BPWM0_CH0_PA11        /*!< Set PA11 function to BPWM0_CH0       */
+#define SET_BPWM0_CH0_PE2()      SYS->GPE_MFPL = (SYS->GPE_MFPL & (~BPWM0_CH0_PE2_Msk)) | BPWM0_CH0_PE2          /*!< Set PE2 function to BPWM0_CH0        */
+#define SET_BPWM0_CH0_PG14()     SYS->GPG_MFPH = (SYS->GPG_MFPH & (~BPWM0_CH0_PG14_Msk)) | BPWM0_CH0_PG14        /*!< Set PG14 function to BPWM0_CH0       */
+#define SET_BPWM0_CH1_PA1()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM0_CH1_PA1_Msk)) | BPWM0_CH1_PA1          /*!< Set PA1 function to BPWM0_CH1        */
+#define SET_BPWM0_CH1_PE3()      SYS->GPE_MFPL = (SYS->GPE_MFPL & (~BPWM0_CH1_PE3_Msk)) | BPWM0_CH1_PE3          /*!< Set PE3 function to BPWM0_CH1        */
+#define SET_BPWM0_CH1_PG13()     SYS->GPG_MFPH = (SYS->GPG_MFPH & (~BPWM0_CH1_PG13_Msk)) | BPWM0_CH1_PG13        /*!< Set PG13 function to BPWM0_CH1       */
+#define SET_BPWM0_CH1_PA10()     SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM0_CH1_PA10_Msk)) | BPWM0_CH1_PA10        /*!< Set PA10 function to BPWM0_CH1       */
+#define SET_BPWM0_CH2_PE4()      SYS->GPE_MFPL = (SYS->GPE_MFPL & (~BPWM0_CH2_PE4_Msk)) | BPWM0_CH2_PE4          /*!< Set PE4 function to BPWM0_CH2        */
+#define SET_BPWM0_CH2_PG12()     SYS->GPG_MFPH = (SYS->GPG_MFPH & (~BPWM0_CH2_PG12_Msk)) | BPWM0_CH2_PG12        /*!< Set PG12 function to BPWM0_CH2       */
+#define SET_BPWM0_CH2_PA2()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM0_CH2_PA2_Msk)) | BPWM0_CH2_PA2          /*!< Set PA2 function to BPWM0_CH2        */
+#define SET_BPWM0_CH2_PA9()      SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM0_CH2_PA9_Msk)) | BPWM0_CH2_PA9          /*!< Set PA9 function to BPWM0_CH2        */
+#define SET_BPWM0_CH3_PG11()     SYS->GPG_MFPH = (SYS->GPG_MFPH & (~BPWM0_CH3_PG11_Msk)) | BPWM0_CH3_PG11        /*!< Set PG11 function to BPWM0_CH3       */
+#define SET_BPWM0_CH3_PA3()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM0_CH3_PA3_Msk)) | BPWM0_CH3_PA3          /*!< Set PA3 function to BPWM0_CH3        */
+#define SET_BPWM0_CH3_PA8()      SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM0_CH3_PA8_Msk)) | BPWM0_CH3_PA8          /*!< Set PA8 function to BPWM0_CH3        */
+#define SET_BPWM0_CH3_PE5()      SYS->GPE_MFPL = (SYS->GPE_MFPL & (~BPWM0_CH3_PE5_Msk)) | BPWM0_CH3_PE5          /*!< Set PE5 function to BPWM0_CH3        */
+#define SET_BPWM0_CH4_PG10()     SYS->GPG_MFPH = (SYS->GPG_MFPH & (~BPWM0_CH4_PG10_Msk)) | BPWM0_CH4_PG10        /*!< Set PG10 function to BPWM0_CH4       */
+#define SET_BPWM0_CH4_PA4()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM0_CH4_PA4_Msk)) | BPWM0_CH4_PA4          /*!< Set PA4 function to BPWM0_CH4        */
+#define SET_BPWM0_CH4_PC13()     SYS->GPC_MFPH = (SYS->GPC_MFPH & (~BPWM0_CH4_PC13_Msk)) | BPWM0_CH4_PC13        /*!< Set PC13 function to BPWM0_CH4       */
+#define SET_BPWM0_CH4_PE6()      SYS->GPE_MFPL = (SYS->GPE_MFPL & (~BPWM0_CH4_PE6_Msk)) | BPWM0_CH4_PE6          /*!< Set PE6 function to BPWM0_CH4        */
+#define SET_BPWM0_CH4_PF5()      SYS->GPF_MFPL = (SYS->GPF_MFPL & (~BPWM0_CH4_PF5_Msk)) | BPWM0_CH4_PF5          /*!< Set PF5 function to BPWM0_CH4        */
+#define SET_BPWM0_CH5_PA5()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM0_CH5_PA5_Msk)) | BPWM0_CH5_PA5          /*!< Set PA5 function to BPWM0_CH5        */
+#define SET_BPWM0_CH5_PE7()      SYS->GPE_MFPL = (SYS->GPE_MFPL & (~BPWM0_CH5_PE7_Msk)) | BPWM0_CH5_PE7          /*!< Set PE7 function to BPWM0_CH5        */
+#define SET_BPWM0_CH5_PF4()      SYS->GPF_MFPL = (SYS->GPF_MFPL & (~BPWM0_CH5_PF4_Msk)) | BPWM0_CH5_PF4          /*!< Set PF4 function to BPWM0_CH5        */
+#define SET_BPWM0_CH5_PD12()     SYS->GPD_MFPH = (SYS->GPD_MFPH & (~BPWM0_CH5_PD12_Msk)) | BPWM0_CH5_PD12        /*!< Set PD12 function to BPWM0_CH5       */
+#define SET_BPWM0_CH5_PG9()      SYS->GPG_MFPH = (SYS->GPG_MFPH & (~BPWM0_CH5_PG9_Msk)) | BPWM0_CH5_PG9          /*!< Set PG9 function to BPWM0_CH5        */
+#define SET_BPWM1_CH0_PB11()     SYS->GPB_MFPH = (SYS->GPB_MFPH & (~BPWM1_CH0_PB11_Msk)) | BPWM1_CH0_PB11        /*!< Set PB11 function to BPWM1_CH0       */
+#define SET_BPWM1_CH0_PC7()      SYS->GPC_MFPL = (SYS->GPC_MFPL & (~BPWM1_CH0_PC7_Msk)) | BPWM1_CH0_PC7          /*!< Set PC7 function to BPWM1_CH0        */
+#define SET_BPWM1_CH0_PF0()      SYS->GPF_MFPL = (SYS->GPF_MFPL & (~BPWM1_CH0_PF0_Msk)) | BPWM1_CH0_PF0          /*!< Set PF0 function to BPWM1_CH0        */
+#define SET_BPWM1_CH0_PF3()      SYS->GPF_MFPL = (SYS->GPF_MFPL & (~BPWM1_CH0_PF3_Msk)) | BPWM1_CH0_PF3          /*!< Set PF3 function to BPWM1_CH0        */
+#define SET_BPWM1_CH1_PC6()      SYS->GPC_MFPL = (SYS->GPC_MFPL & (~BPWM1_CH1_PC6_Msk)) | BPWM1_CH1_PC6          /*!< Set PC6 function to BPWM1_CH1        */
+#define SET_BPWM1_CH1_PF1()      SYS->GPF_MFPL = (SYS->GPF_MFPL & (~BPWM1_CH1_PF1_Msk)) | BPWM1_CH1_PF1          /*!< Set PF1 function to BPWM1_CH1        */
+#define SET_BPWM1_CH1_PF2()      SYS->GPF_MFPL = (SYS->GPF_MFPL & (~BPWM1_CH1_PF2_Msk)) | BPWM1_CH1_PF2          /*!< Set PF2 function to BPWM1_CH1        */
+#define SET_BPWM1_CH1_PB10()     SYS->GPB_MFPH = (SYS->GPB_MFPH & (~BPWM1_CH1_PB10_Msk)) | BPWM1_CH1_PB10        /*!< Set PB10 function to BPWM1_CH1       */
+#define SET_BPWM1_CH2_PB9()      SYS->GPB_MFPH = (SYS->GPB_MFPH & (~BPWM1_CH2_PB9_Msk)) | BPWM1_CH2_PB9          /*!< Set PB9 function to BPWM1_CH2        */
+#define SET_BPWM1_CH2_PA7()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM1_CH2_PA7_Msk)) | BPWM1_CH2_PA7          /*!< Set PA7 function to BPWM1_CH2        */
+#define SET_BPWM1_CH2_PA12()     SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM1_CH2_PA12_Msk)) | BPWM1_CH2_PA12        /*!< Set PA12 function to BPWM1_CH2       */
+#define SET_BPWM1_CH3_PA6()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM1_CH3_PA6_Msk)) | BPWM1_CH3_PA6          /*!< Set PA6 function to BPWM1_CH3        */
+#define SET_BPWM1_CH3_PA13()     SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM1_CH3_PA13_Msk)) | BPWM1_CH3_PA13        /*!< Set PA13 function to BPWM1_CH3       */
+#define SET_BPWM1_CH3_PB8()      SYS->GPB_MFPH = (SYS->GPB_MFPH & (~BPWM1_CH3_PB8_Msk)) | BPWM1_CH3_PB8          /*!< Set PB8 function to BPWM1_CH3        */
+#define SET_BPWM1_CH4_PA14()     SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM1_CH4_PA14_Msk)) | BPWM1_CH4_PA14        /*!< Set PA14 function to BPWM1_CH4       */
+#define SET_BPWM1_CH4_PC8()      SYS->GPC_MFPH = (SYS->GPC_MFPH & (~BPWM1_CH4_PC8_Msk)) | BPWM1_CH4_PC8          /*!< Set PC8 function to BPWM1_CH4        */
+#define SET_BPWM1_CH4_PB7()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~BPWM1_CH4_PB7_Msk)) | BPWM1_CH4_PB7          /*!< Set PB7 function to BPWM1_CH4        */
+#define SET_BPWM1_CH5_PA15()     SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM1_CH5_PA15_Msk)) | BPWM1_CH5_PA15        /*!< Set PA15 function to BPWM1_CH5       */
+#define SET_BPWM1_CH5_PB6()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~BPWM1_CH5_PB6_Msk)) | BPWM1_CH5_PB6          /*!< Set PB6 function to BPWM1_CH5        */
+#define SET_BPWM1_CH5_PE13()     SYS->GPE_MFPH = (SYS->GPE_MFPH & (~BPWM1_CH5_PE13_Msk)) | BPWM1_CH5_PE13        /*!< Set PE13 function to BPWM1_CH5       */
+#define SET_CAN0_RXD_PA13()      SYS->GPA_MFPH = (SYS->GPA_MFPH & (~CAN0_RXD_PA13_Msk)) | CAN0_RXD_PA13          /*!< Set PA13 function to CAN0_RXD        */
+#define SET_CAN0_RXD_PD10()      SYS->GPD_MFPH = (SYS->GPD_MFPH & (~CAN0_RXD_PD10_Msk)) | CAN0_RXD_PD10          /*!< Set PD10 function to CAN0_RXD        */
+#define SET_CAN0_RXD_PA4()       SYS->GPA_MFPL = (SYS->GPA_MFPL & (~CAN0_RXD_PA4_Msk)) | CAN0_RXD_PA4            /*!< Set PA4 function to CAN0_RXD         */
+#define SET_CAN0_RXD_PC4()       SYS->GPC_MFPL = (SYS->GPC_MFPL & (~CAN0_RXD_PC4_Msk)) | CAN0_RXD_PC4            /*!< Set PC4 function to CAN0_RXD         */
+#define SET_CAN0_RXD_PB10()      SYS->GPB_MFPH = (SYS->GPB_MFPH & (~CAN0_RXD_PB10_Msk)) | CAN0_RXD_PB10          /*!< Set PB10 function to CAN0_RXD        */
+#define SET_CAN0_RXD_PE15()      SYS->GPE_MFPH = (SYS->GPE_MFPH & (~CAN0_RXD_PE15_Msk)) | CAN0_RXD_PE15          /*!< Set PE15 function to CAN0_RXD        */
+#define SET_CAN0_TXD_PD11()      SYS->GPD_MFPH = (SYS->GPD_MFPH & (~CAN0_TXD_PD11_Msk)) | CAN0_TXD_PD11          /*!< Set PD11 function to CAN0_TXD        */
+#define SET_CAN0_TXD_PC5()       SYS->GPC_MFPL = (SYS->GPC_MFPL & (~CAN0_TXD_PC5_Msk)) | CAN0_TXD_PC5            /*!< Set PC5 function to CAN0_TXD         */
+#define SET_CAN0_TXD_PB11()      SYS->GPB_MFPH = (SYS->GPB_MFPH & (~CAN0_TXD_PB11_Msk)) | CAN0_TXD_PB11          /*!< Set PB11 function to CAN0_TXD        */
+#define SET_CAN0_TXD_PA12()      SYS->GPA_MFPH = (SYS->GPA_MFPH & (~CAN0_TXD_PA12_Msk)) | CAN0_TXD_PA12          /*!< Set PA12 function to CAN0_TXD        */
+#define SET_CAN0_TXD_PE14()      SYS->GPE_MFPH = (SYS->GPE_MFPH & (~CAN0_TXD_PE14_Msk)) | CAN0_TXD_PE14          /*!< Set PE14 function to CAN0_TXD        */
+#define SET_CAN0_TXD_PA5()       SYS->GPA_MFPL = (SYS->GPA_MFPL & (~CAN0_TXD_PA5_Msk)) | CAN0_TXD_PA5            /*!< Set PA5 function to CAN0_TXD         */
+#define SET_CLKO_PC13()          SYS->GPC_MFPH = (SYS->GPC_MFPH & (~CLKO_PC13_Msk)) | CLKO_PC13                  /*!< Set PC13 function to CLKO            */
+#define SET_CLKO_PB14()          SYS->GPB_MFPH = (SYS->GPB_MFPH & (~CLKO_PB14_Msk)) | CLKO_PB14                  /*!< Set PB14 function to CLKO            */
+#define SET_CLKO_PD12()          SYS->GPD_MFPH = (SYS->GPD_MFPH & (~CLKO_PD12_Msk)) | CLKO_PD12                  /*!< Set PD12 function to CLKO            */
+#define SET_CLKO_PG15()          SYS->GPG_MFPH = (SYS->GPG_MFPH & (~CLKO_PG15_Msk)) | CLKO_PG15                  /*!< Set PG15 function to CLKO            */
+#define SET_DAC0_OUT_PB12()      SYS->GPB_MFPH = (SYS->GPB_MFPH & (~DAC0_OUT_PB12_Msk)) | DAC0_OUT_PB12          /*!< Set PB12 function to DAC0_OUT        */
+#define SET_DAC0_OUT_PB12()      SYS->GPB_MFPH = (SYS->GPB_MFPH & (~DAC0_OUT_PB12_Msk)) | DAC0_OUT_PB12          /*!< Set PB12 function to DAC0_OUT        */
+#define SET_DAC0_ST_PA0()        SYS->GPA_MFPL = (SYS->GPA_MFPL & (~DAC0_ST_PA0_Msk)) | DAC0_ST_PA0              /*!< Set PA0 function to DAC0_ST          */
+#define SET_DAC0_ST_PA10()       SYS->GPA_MFPH = (SYS->GPA_MFPH & (~DAC0_ST_PA10_Msk)) | DAC0_ST_PA10            /*!< Set PA10 function to DAC0_ST         */
+#define SET_DAC1_OUT_PB13()      SYS->GPB_MFPH = (SYS->GPB_MFPH & (~DAC1_OUT_PB13_Msk)) | DAC1_OUT_PB13          /*!< Set PB13 function to DAC1_OUT        */
+#define SET_DAC1_OUT_PB13()      SYS->GPB_MFPH = (SYS->GPB_MFPH & (~DAC1_OUT_PB13_Msk)) | DAC1_OUT_PB13          /*!< Set PB13 function to DAC1_OUT        */
+#define SET_DAC1_ST_PA1()        SYS->GPA_MFPL = (SYS->GPA_MFPL & (~DAC1_ST_PA1_Msk)) | DAC1_ST_PA1              /*!< Set PA1 function to DAC1_ST          */
+#define SET_DAC1_ST_PA11()       SYS->GPA_MFPH = (SYS->GPA_MFPH & (~DAC1_ST_PA11_Msk)) | DAC1_ST_PA11            /*!< Set PA11 function to DAC1_ST         */
+#define SET_EADC0_CH0_PB0()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH0_PB0_Msk)) | EADC0_CH0_PB0          /*!< Set PB0 function to EADC0_CH0        */
+#define SET_EADC0_CH1_PB1()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH1_PB1_Msk)) | EADC0_CH1_PB1          /*!< Set PB1 function to EADC0_CH1        */
+#define SET_EADC0_CH10_PB10()    SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH10_PB10_Msk)) | EADC0_CH10_PB10      /*!< Set PB10 function to EADC0_CH10      */
+#define SET_EADC0_CH11_PB11()    SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH11_PB11_Msk)) | EADC0_CH11_PB11      /*!< Set PB11 function to EADC0_CH11      */
+#define SET_EADC0_CH12_PB12()    SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH12_PB12_Msk)) | EADC0_CH12_PB12      /*!< Set PB12 function to EADC0_CH12      */
+#define SET_EADC0_CH13_PB13()    SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH13_PB13_Msk)) | EADC0_CH13_PB13      /*!< Set PB13 function to EADC0_CH13      */
+#define SET_EADC0_CH14_PB14()    SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH14_PB14_Msk)) | EADC0_CH14_PB14      /*!< Set PB14 function to EADC0_CH14      */
+#define SET_EADC0_CH15_PB15()    SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH15_PB15_Msk)) | EADC0_CH15_PB15      /*!< Set PB15 function to EADC0_CH15      */
+#define SET_EADC0_CH15_PD10()    SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EADC0_CH15_PD10_Msk)) | EADC0_CH15_PD10      /*!< Set PD10 function to EADC0_CH15      */
+#define SET_EADC0_CH2_PB2()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH2_PB2_Msk)) | EADC0_CH2_PB2          /*!< Set PB2 function to EADC0_CH2        */
+#define SET_EADC0_CH3_PB3()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH3_PB3_Msk)) | EADC0_CH3_PB3          /*!< Set PB3 function to EADC0_CH3        */
+#define SET_EADC0_CH4_PB4()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH4_PB4_Msk)) | EADC0_CH4_PB4          /*!< Set PB4 function to EADC0_CH4        */
+#define SET_EADC0_CH5_PB5()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH5_PB5_Msk)) | EADC0_CH5_PB5          /*!< Set PB5 function to EADC0_CH5        */
+#define SET_EADC0_CH6_PB6()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH6_PB6_Msk)) | EADC0_CH6_PB6          /*!< Set PB6 function to EADC0_CH6        */
+#define SET_EADC0_CH7_PB7()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH7_PB7_Msk)) | EADC0_CH7_PB7          /*!< Set PB7 function to EADC0_CH7        */
+#define SET_EADC0_CH8_PB8()      SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH8_PB8_Msk)) | EADC0_CH8_PB8          /*!< Set PB8 function to EADC0_CH8        */
+#define SET_EADC0_CH9_PB9()      SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH9_PB9_Msk)) | EADC0_CH9_PB9          /*!< Set PB9 function to EADC0_CH9        */
+#define SET_EADC0_ST_PF5()       SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EADC0_ST_PF5_Msk)) | EADC0_ST_PF5            /*!< Set PF5 function to EADC0_ST         */
+#define SET_EADC0_ST_PC13()      SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EADC0_ST_PC13_Msk)) | EADC0_ST_PC13          /*!< Set PC13 function to EADC0_ST        */
+#define SET_EADC0_ST_PC1()       SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EADC0_ST_PC1_Msk)) | EADC0_ST_PC1            /*!< Set PC1 function to EADC0_ST         */
+#define SET_EADC0_ST_PD12()      SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EADC0_ST_PD12_Msk)) | EADC0_ST_PD12          /*!< Set PD12 function to EADC0_ST        */
+#define SET_EADC0_ST_PG15()      SYS->GPG_MFPH = (SYS->GPG_MFPH & (~EADC0_ST_PG15_Msk)) | EADC0_ST_PG15          /*!< Set PG15 function to EADC0_ST        */
+#define SET_EBI_AD0_PC0()        SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD0_PC0_Msk)) | EBI_AD0_PC0              /*!< Set PC0 function to EBI_AD0          */
+#define SET_EBI_AD0_PG9()        SYS->GPG_MFPH = (SYS->GPG_MFPH & (~EBI_AD0_PG9_Msk)) | EBI_AD0_PG9              /*!< Set PG9 function to EBI_AD0          */
+#define SET_EBI_AD1_PG10()       SYS->GPG_MFPH = (SYS->GPG_MFPH & (~EBI_AD1_PG10_Msk)) | EBI_AD1_PG10            /*!< Set PG10 function to EBI_AD1         */
+#define SET_EBI_AD1_PC1()        SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD1_PC1_Msk)) | EBI_AD1_PC1              /*!< Set PC1 function to EBI_AD1          */
+#define SET_EBI_AD10_PE1()       SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EBI_AD10_PE1_Msk)) | EBI_AD10_PE1            /*!< Set PE1 function to EBI_AD10         */
+#define SET_EBI_AD10_PD3()       SYS->GPD_MFPL = (SYS->GPD_MFPL & (~EBI_AD10_PD3_Msk)) | EBI_AD10_PD3            /*!< Set PD3 function to EBI_AD10         */
+#define SET_EBI_AD10_PD13()      SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EBI_AD10_PD13_Msk)) | EBI_AD10_PD13          /*!< Set PD13 function to EBI_AD10        */
+#define SET_EBI_AD11_PE0()       SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EBI_AD11_PE0_Msk)) | EBI_AD11_PE0            /*!< Set PE0 function to EBI_AD11         */
+#define SET_EBI_AD11_PD2()       SYS->GPD_MFPL = (SYS->GPD_MFPL & (~EBI_AD11_PD2_Msk)) | EBI_AD11_PD2            /*!< Set PD2 function to EBI_AD11         */
+#define SET_EBI_AD12_PD1()       SYS->GPD_MFPL = (SYS->GPD_MFPL & (~EBI_AD12_PD1_Msk)) | EBI_AD12_PD1            /*!< Set PD1 function to EBI_AD12         */
+#define SET_EBI_AD12_PB15()      SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_AD12_PB15_Msk)) | EBI_AD12_PB15          /*!< Set PB15 function to EBI_AD12        */
+#define SET_EBI_AD12_PH8()       SYS->GPH_MFPH = (SYS->GPH_MFPH & (~EBI_AD12_PH8_Msk)) | EBI_AD12_PH8            /*!< Set PH8 function to EBI_AD12         */
+#define SET_EBI_AD13_PD0()       SYS->GPD_MFPL = (SYS->GPD_MFPL & (~EBI_AD13_PD0_Msk)) | EBI_AD13_PD0            /*!< Set PD0 function to EBI_AD13         */
+#define SET_EBI_AD13_PB14()      SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_AD13_PB14_Msk)) | EBI_AD13_PB14          /*!< Set PB14 function to EBI_AD13        */
+#define SET_EBI_AD13_PH9()       SYS->GPH_MFPH = (SYS->GPH_MFPH & (~EBI_AD13_PH9_Msk)) | EBI_AD13_PH9            /*!< Set PH9 function to EBI_AD13         */
+#define SET_EBI_AD14_PB13()      SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_AD14_PB13_Msk)) | EBI_AD14_PB13          /*!< Set PB13 function to EBI_AD14        */
+#define SET_EBI_AD14_PH10()      SYS->GPH_MFPH = (SYS->GPH_MFPH & (~EBI_AD14_PH10_Msk)) | EBI_AD14_PH10          /*!< Set PH10 function to EBI_AD14        */
+#define SET_EBI_AD15_PB12()      SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_AD15_PB12_Msk)) | EBI_AD15_PB12          /*!< Set PB12 function to EBI_AD15        */
+#define SET_EBI_AD15_PH11()      SYS->GPH_MFPH = (SYS->GPH_MFPH & (~EBI_AD15_PH11_Msk)) | EBI_AD15_PH11          /*!< Set PH11 function to EBI_AD15        */
+#define SET_EBI_AD2_PC2()        SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD2_PC2_Msk)) | EBI_AD2_PC2              /*!< Set PC2 function to EBI_AD2          */
+#define SET_EBI_AD2_PG11()       SYS->GPG_MFPH = (SYS->GPG_MFPH & (~EBI_AD2_PG11_Msk)) | EBI_AD2_PG11            /*!< Set PG11 function to EBI_AD2         */
+#define SET_EBI_AD3_PG12()       SYS->GPG_MFPH = (SYS->GPG_MFPH & (~EBI_AD3_PG12_Msk)) | EBI_AD3_PG12            /*!< Set PG12 function to EBI_AD3         */
+#define SET_EBI_AD3_PC3()        SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD3_PC3_Msk)) | EBI_AD3_PC3              /*!< Set PC3 function to EBI_AD3          */
+#define SET_EBI_AD4_PC4()        SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD4_PC4_Msk)) | EBI_AD4_PC4              /*!< Set PC4 function to EBI_AD4          */
+#define SET_EBI_AD4_PG13()       SYS->GPG_MFPH = (SYS->GPG_MFPH & (~EBI_AD4_PG13_Msk)) | EBI_AD4_PG13            /*!< Set PG13 function to EBI_AD4         */
+#define SET_EBI_AD5_PG14()       SYS->GPG_MFPH = (SYS->GPG_MFPH & (~EBI_AD5_PG14_Msk)) | EBI_AD5_PG14            /*!< Set PG14 function to EBI_AD5         */
+#define SET_EBI_AD5_PC5()        SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD5_PC5_Msk)) | EBI_AD5_PC5              /*!< Set PC5 function to EBI_AD5          */
+#define SET_EBI_AD6_PD8()        SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EBI_AD6_PD8_Msk)) | EBI_AD6_PD8              /*!< Set PD8 function to EBI_AD6          */
+#define SET_EBI_AD6_PA6()        SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EBI_AD6_PA6_Msk)) | EBI_AD6_PA6              /*!< Set PA6 function to EBI_AD6          */
+#define SET_EBI_AD7_PD9()        SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EBI_AD7_PD9_Msk)) | EBI_AD7_PD9              /*!< Set PD9 function to EBI_AD7          */
+#define SET_EBI_AD7_PA7()        SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EBI_AD7_PA7_Msk)) | EBI_AD7_PA7              /*!< Set PA7 function to EBI_AD7          */
+#define SET_EBI_AD8_PE14()       SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_AD8_PE14_Msk)) | EBI_AD8_PE14            /*!< Set PE14 function to EBI_AD8         */
+#define SET_EBI_AD8_PC6()        SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD8_PC6_Msk)) | EBI_AD8_PC6              /*!< Set PC6 function to EBI_AD8          */
+#define SET_EBI_AD9_PC7()        SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD9_PC7_Msk)) | EBI_AD9_PC7              /*!< Set PC7 function to EBI_AD9          */
+#define SET_EBI_AD9_PE15()       SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_AD9_PE15_Msk)) | EBI_AD9_PE15            /*!< Set PE15 function to EBI_AD9         */
+#define SET_EBI_ADR0_PB5()       SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_ADR0_PB5_Msk)) | EBI_ADR0_PB5            /*!< Set PB5 function to EBI_ADR0         */
+#define SET_EBI_ADR0_PH7()       SYS->GPH_MFPL = (SYS->GPH_MFPL & (~EBI_ADR0_PH7_Msk)) | EBI_ADR0_PH7            /*!< Set PH7 function to EBI_ADR0         */
+#define SET_EBI_ADR1_PH6()       SYS->GPH_MFPL = (SYS->GPH_MFPL & (~EBI_ADR1_PH6_Msk)) | EBI_ADR1_PH6            /*!< Set PH6 function to EBI_ADR1         */
+#define SET_EBI_ADR1_PB4()       SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_ADR1_PB4_Msk)) | EBI_ADR1_PB4            /*!< Set PB4 function to EBI_ADR1         */
+#define SET_EBI_ADR10_PC13()     SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EBI_ADR10_PC13_Msk)) | EBI_ADR10_PC13        /*!< Set PC13 function to EBI_ADR10       */
+#define SET_EBI_ADR10_PE8()      SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_ADR10_PE8_Msk)) | EBI_ADR10_PE8          /*!< Set PE8 function to EBI_ADR10        */
+#define SET_EBI_ADR11_PE9()      SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_ADR11_PE9_Msk)) | EBI_ADR11_PE9          /*!< Set PE9 function to EBI_ADR11        */
+#define SET_EBI_ADR11_PG2()      SYS->GPG_MFPL = (SYS->GPG_MFPL & (~EBI_ADR11_PG2_Msk)) | EBI_ADR11_PG2          /*!< Set PG2 function to EBI_ADR11        */
+#define SET_EBI_ADR12_PE10()     SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_ADR12_PE10_Msk)) | EBI_ADR12_PE10        /*!< Set PE10 function to EBI_ADR12       */
+#define SET_EBI_ADR12_PG3()      SYS->GPG_MFPL = (SYS->GPG_MFPL & (~EBI_ADR12_PG3_Msk)) | EBI_ADR12_PG3          /*!< Set PG3 function to EBI_ADR12        */
+#define SET_EBI_ADR13_PE11()     SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_ADR13_PE11_Msk)) | EBI_ADR13_PE11        /*!< Set PE11 function to EBI_ADR13       */
+#define SET_EBI_ADR13_PG4()      SYS->GPG_MFPL = (SYS->GPG_MFPL & (~EBI_ADR13_PG4_Msk)) | EBI_ADR13_PG4          /*!< Set PG4 function to EBI_ADR13        */
+#define SET_EBI_ADR14_PF11()     SYS->GPF_MFPH = (SYS->GPF_MFPH & (~EBI_ADR14_PF11_Msk)) | EBI_ADR14_PF11        /*!< Set PF11 function to EBI_ADR14       */
+#define SET_EBI_ADR14_PE12()     SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_ADR14_PE12_Msk)) | EBI_ADR14_PE12        /*!< Set PE12 function to EBI_ADR14       */
+#define SET_EBI_ADR15_PE13()     SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_ADR15_PE13_Msk)) | EBI_ADR15_PE13        /*!< Set PE13 function to EBI_ADR15       */
+#define SET_EBI_ADR15_PF10()     SYS->GPF_MFPH = (SYS->GPF_MFPH & (~EBI_ADR15_PF10_Msk)) | EBI_ADR15_PF10        /*!< Set PF10 function to EBI_ADR15       */
+#define SET_EBI_ADR16_PC8()      SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EBI_ADR16_PC8_Msk)) | EBI_ADR16_PC8          /*!< Set PC8 function to EBI_ADR16        */
+#define SET_EBI_ADR16_PF9()      SYS->GPF_MFPH = (SYS->GPF_MFPH & (~EBI_ADR16_PF9_Msk)) | EBI_ADR16_PF9          /*!< Set PF9 function to EBI_ADR16        */
+#define SET_EBI_ADR16_PB11()     SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_ADR16_PB11_Msk)) | EBI_ADR16_PB11        /*!< Set PB11 function to EBI_ADR16       */
+#define SET_EBI_ADR17_PB10()     SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_ADR17_PB10_Msk)) | EBI_ADR17_PB10        /*!< Set PB10 function to EBI_ADR17       */
+#define SET_EBI_ADR17_PF8()      SYS->GPF_MFPH = (SYS->GPF_MFPH & (~EBI_ADR17_PF8_Msk)) | EBI_ADR17_PF8          /*!< Set PF8 function to EBI_ADR17        */
+#define SET_EBI_ADR18_PF7()      SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EBI_ADR18_PF7_Msk)) | EBI_ADR18_PF7          /*!< Set PF7 function to EBI_ADR18        */
+#define SET_EBI_ADR18_PB9()      SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_ADR18_PB9_Msk)) | EBI_ADR18_PB9          /*!< Set PB9 function to EBI_ADR18        */
+#define SET_EBI_ADR19_PB8()      SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_ADR19_PB8_Msk)) | EBI_ADR19_PB8          /*!< Set PB8 function to EBI_ADR19        */
+#define SET_EBI_ADR19_PF6()      SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EBI_ADR19_PF6_Msk)) | EBI_ADR19_PF6          /*!< Set PF6 function to EBI_ADR19        */
+#define SET_EBI_ADR2_PB3()       SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_ADR2_PB3_Msk)) | EBI_ADR2_PB3            /*!< Set PB3 function to EBI_ADR2         */
+#define SET_EBI_ADR2_PH5()       SYS->GPH_MFPL = (SYS->GPH_MFPL & (~EBI_ADR2_PH5_Msk)) | EBI_ADR2_PH5            /*!< Set PH5 function to EBI_ADR2         */
+#define SET_EBI_ADR3_PH4()       SYS->GPH_MFPL = (SYS->GPH_MFPL & (~EBI_ADR3_PH4_Msk)) | EBI_ADR3_PH4            /*!< Set PH4 function to EBI_ADR3         */
+#define SET_EBI_ADR3_PB2()       SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_ADR3_PB2_Msk)) | EBI_ADR3_PB2            /*!< Set PB2 function to EBI_ADR3         */
+#define SET_EBI_ADR4_PC12()      SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EBI_ADR4_PC12_Msk)) | EBI_ADR4_PC12          /*!< Set PC12 function to EBI_ADR4        */
+#define SET_EBI_ADR5_PC11()      SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EBI_ADR5_PC11_Msk)) | EBI_ADR5_PC11          /*!< Set PC11 function to EBI_ADR5        */
+#define SET_EBI_ADR6_PC10()      SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EBI_ADR6_PC10_Msk)) | EBI_ADR6_PC10          /*!< Set PC10 function to EBI_ADR6        */
+#define SET_EBI_ADR7_PC9()       SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EBI_ADR7_PC9_Msk)) | EBI_ADR7_PC9            /*!< Set PC9 function to EBI_ADR7         */
+#define SET_EBI_ADR8_PB1()       SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_ADR8_PB1_Msk)) | EBI_ADR8_PB1            /*!< Set PB1 function to EBI_ADR8         */
+#define SET_EBI_ADR9_PB0()       SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_ADR9_PB0_Msk)) | EBI_ADR9_PB0            /*!< Set PB0 function to EBI_ADR9         */
+#define SET_EBI_ALE_PE2()        SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EBI_ALE_PE2_Msk)) | EBI_ALE_PE2              /*!< Set PE2 function to EBI_ALE          */
+#define SET_EBI_ALE_PA8()        SYS->GPA_MFPH = (SYS->GPA_MFPH & (~EBI_ALE_PA8_Msk)) | EBI_ALE_PA8              /*!< Set PA8 function to EBI_ALE          */
+#define SET_EBI_MCLK_PA9()       SYS->GPA_MFPH = (SYS->GPA_MFPH & (~EBI_MCLK_PA9_Msk)) | EBI_MCLK_PA9            /*!< Set PA9 function to EBI_MCLK         */
+#define SET_EBI_MCLK_PE3()       SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EBI_MCLK_PE3_Msk)) | EBI_MCLK_PE3            /*!< Set PE3 function to EBI_MCLK         */
+#define SET_EBI_nCS0_PD12()      SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EBI_nCS0_PD12_Msk)) | EBI_nCS0_PD12          /*!< Set PD12 function to EBI_nCS0        */
+#define SET_EBI_nCS0_PD14()      SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EBI_nCS0_PD14_Msk)) | EBI_nCS0_PD14          /*!< Set PD14 function to EBI_nCS0        */
+#define SET_EBI_nCS0_PF3()       SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EBI_nCS0_PF3_Msk)) | EBI_nCS0_PF3            /*!< Set PF3 function to EBI_nCS0         */
+#define SET_EBI_nCS0_PB7()       SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_nCS0_PB7_Msk)) | EBI_nCS0_PB7            /*!< Set PB7 function to EBI_nCS0         */
+#define SET_EBI_nCS0_PF6()       SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EBI_nCS0_PF6_Msk)) | EBI_nCS0_PF6            /*!< Set PF6 function to EBI_nCS0         */
+#define SET_EBI_nCS1_PF2()       SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EBI_nCS1_PF2_Msk)) | EBI_nCS1_PF2            /*!< Set PF2 function to EBI_nCS1         */
+#define SET_EBI_nCS1_PB6()       SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_nCS1_PB6_Msk)) | EBI_nCS1_PB6            /*!< Set PB6 function to EBI_nCS1         */
+#define SET_EBI_nCS1_PD11()      SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EBI_nCS1_PD11_Msk)) | EBI_nCS1_PD11          /*!< Set PD11 function to EBI_nCS1        */
+#define SET_EBI_nCS2_PD10()      SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EBI_nCS2_PD10_Msk)) | EBI_nCS2_PD10          /*!< Set PD10 function to EBI_nCS2        */
+#define SET_EBI_nRD_PE5()        SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EBI_nRD_PE5_Msk)) | EBI_nRD_PE5              /*!< Set PE5 function to EBI_nRD          */
+#define SET_EBI_nRD_PA11()       SYS->GPA_MFPH = (SYS->GPA_MFPH & (~EBI_nRD_PA11_Msk)) | EBI_nRD_PA11            /*!< Set PA11 function to EBI_nRD         */
+#define SET_EBI_nWR_PE4()        SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EBI_nWR_PE4_Msk)) | EBI_nWR_PE4              /*!< Set PE4 function to EBI_nWR          */
+#define SET_EBI_nWR_PA10()       SYS->GPA_MFPH = (SYS->GPA_MFPH & (~EBI_nWR_PA10_Msk)) | EBI_nWR_PA10            /*!< Set PA10 function to EBI_nWR         */
+#define SET_EBI_nWRH_PB6()       SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_nWRH_PB6_Msk)) | EBI_nWRH_PB6            /*!< Set PB6 function to EBI_nWRH         */
+#define SET_EBI_nWRL_PB7()       SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_nWRL_PB7_Msk)) | EBI_nWRL_PB7            /*!< Set PB7 function to EBI_nWRL         */
+#define SET_ECAP0_IC0_PE8()      SYS->GPE_MFPH = (SYS->GPE_MFPH & (~ECAP0_IC0_PE8_Msk)) | ECAP0_IC0_PE8          /*!< Set PE8 function to ECAP0_IC0        */
+#define SET_ECAP0_IC0_PA10()     SYS->GPA_MFPH = (SYS->GPA_MFPH & (~ECAP0_IC0_PA10_Msk)) | ECAP0_IC0_PA10        /*!< Set PA10 function to ECAP0_IC0       */
+#define SET_ECAP0_IC1_PA9()      SYS->GPA_MFPH = (SYS->GPA_MFPH & (~ECAP0_IC1_PA9_Msk)) | ECAP0_IC1_PA9          /*!< Set PA9 function to ECAP0_IC1        */
+#define SET_ECAP0_IC1_PE9()      SYS->GPE_MFPH = (SYS->GPE_MFPH & (~ECAP0_IC1_PE9_Msk)) | ECAP0_IC1_PE9          /*!< Set PE9 function to ECAP0_IC1        */
+#define SET_ECAP0_IC2_PE10()     SYS->GPE_MFPH = (SYS->GPE_MFPH & (~ECAP0_IC2_PE10_Msk)) | ECAP0_IC2_PE10        /*!< Set PE10 function to ECAP0_IC2       */
+#define SET_ECAP0_IC2_PA8()      SYS->GPA_MFPH = (SYS->GPA_MFPH & (~ECAP0_IC2_PA8_Msk)) | ECAP0_IC2_PA8          /*!< Set PA8 function to ECAP0_IC2        */
+#define SET_ECAP1_IC0_PE13()     SYS->GPE_MFPH = (SYS->GPE_MFPH & (~ECAP1_IC0_PE13_Msk)) | ECAP1_IC0_PE13        /*!< Set PE13 function to ECAP1_IC0       */
+#define SET_ECAP1_IC0_PC10()     SYS->GPC_MFPH = (SYS->GPC_MFPH & (~ECAP1_IC0_PC10_Msk)) | ECAP1_IC0_PC10        /*!< Set PC10 function to ECAP1_IC0       */
+#define SET_ECAP1_IC1_PC11()     SYS->GPC_MFPH = (SYS->GPC_MFPH & (~ECAP1_IC1_PC11_Msk)) | ECAP1_IC1_PC11        /*!< Set PC11 function to ECAP1_IC1       */
+#define SET_ECAP1_IC1_PE12()     SYS->GPE_MFPH = (SYS->GPE_MFPH & (~ECAP1_IC1_PE12_Msk)) | ECAP1_IC1_PE12        /*!< Set PE12 function to ECAP1_IC1       */
+#define SET_ECAP1_IC2_PC12()     SYS->GPC_MFPH = (SYS->GPC_MFPH & (~ECAP1_IC2_PC12_Msk)) | ECAP1_IC2_PC12        /*!< Set PC12 function to ECAP1_IC2       */
+#define SET_ECAP1_IC2_PE11()     SYS->GPE_MFPH = (SYS->GPE_MFPH & (~ECAP1_IC2_PE11_Msk)) | ECAP1_IC2_PE11        /*!< Set PE11 function to ECAP1_IC2       */
+#define SET_EPWM0_BRAKE0_PE8()   SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_BRAKE0_PE8_Msk)) | EPWM0_BRAKE0_PE8    /*!< Set PE8 function to EPWM0_BRAKE0     */
+#define SET_EPWM0_BRAKE0_PB1()   SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_BRAKE0_PB1_Msk)) | EPWM0_BRAKE0_PB1    /*!< Set PB1 function to EPWM0_BRAKE0     */
+#define SET_EPWM0_BRAKE1_PB14()  SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EPWM0_BRAKE1_PB14_Msk)) | EPWM0_BRAKE1_PB14  /*!< Set PB14 function to EPWM0_BRAKE1    */
+#define SET_EPWM0_BRAKE1_PE9()   SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_BRAKE1_PE9_Msk)) | EPWM0_BRAKE1_PE9    /*!< Set PE9 function to EPWM0_BRAKE1     */
+#define SET_EPWM0_BRAKE1_PB0()   SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_BRAKE1_PB0_Msk)) | EPWM0_BRAKE1_PB0    /*!< Set PB0 function to EPWM0_BRAKE1     */
+#define SET_EPWM0_CH0_PF5()      SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EPWM0_CH0_PF5_Msk)) | EPWM0_CH0_PF5          /*!< Set PF5 function to EPWM0_CH0        */
+#define SET_EPWM0_CH0_PA5()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM0_CH0_PA5_Msk)) | EPWM0_CH0_PA5          /*!< Set PA5 function to EPWM0_CH0        */
+#define SET_EPWM0_CH0_PB5()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_CH0_PB5_Msk)) | EPWM0_CH0_PB5          /*!< Set PB5 function to EPWM0_CH0        */
+#define SET_EPWM0_CH0_PE8()      SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_CH0_PE8_Msk)) | EPWM0_CH0_PE8          /*!< Set PE8 function to EPWM0_CH0        */
+#define SET_EPWM0_CH0_PE7()      SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EPWM0_CH0_PE7_Msk)) | EPWM0_CH0_PE7          /*!< Set PE7 function to EPWM0_CH0        */
+#define SET_EPWM0_CH1_PA4()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM0_CH1_PA4_Msk)) | EPWM0_CH1_PA4          /*!< Set PA4 function to EPWM0_CH1        */
+#define SET_EPWM0_CH1_PE9()      SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_CH1_PE9_Msk)) | EPWM0_CH1_PE9          /*!< Set PE9 function to EPWM0_CH1        */
+#define SET_EPWM0_CH1_PE6()      SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EPWM0_CH1_PE6_Msk)) | EPWM0_CH1_PE6          /*!< Set PE6 function to EPWM0_CH1        */
+#define SET_EPWM0_CH1_PF4()      SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EPWM0_CH1_PF4_Msk)) | EPWM0_CH1_PF4          /*!< Set PF4 function to EPWM0_CH1        */
+#define SET_EPWM0_CH1_PB4()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_CH1_PB4_Msk)) | EPWM0_CH1_PB4          /*!< Set PB4 function to EPWM0_CH1        */
+#define SET_EPWM0_CH2_PE10()     SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_CH2_PE10_Msk)) | EPWM0_CH2_PE10        /*!< Set PE10 function to EPWM0_CH2       */
+#define SET_EPWM0_CH2_PE5()      SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EPWM0_CH2_PE5_Msk)) | EPWM0_CH2_PE5          /*!< Set PE5 function to EPWM0_CH2        */
+#define SET_EPWM0_CH2_PA3()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM0_CH2_PA3_Msk)) | EPWM0_CH2_PA3          /*!< Set PA3 function to EPWM0_CH2        */
+#define SET_EPWM0_CH2_PB3()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_CH2_PB3_Msk)) | EPWM0_CH2_PB3          /*!< Set PB3 function to EPWM0_CH2        */
+#define SET_EPWM0_CH3_PA2()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM0_CH3_PA2_Msk)) | EPWM0_CH3_PA2          /*!< Set PA2 function to EPWM0_CH3        */
+#define SET_EPWM0_CH3_PB2()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_CH3_PB2_Msk)) | EPWM0_CH3_PB2          /*!< Set PB2 function to EPWM0_CH3        */
+#define SET_EPWM0_CH3_PE11()     SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_CH3_PE11_Msk)) | EPWM0_CH3_PE11        /*!< Set PE11 function to EPWM0_CH3       */
+#define SET_EPWM0_CH3_PE4()      SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EPWM0_CH3_PE4_Msk)) | EPWM0_CH3_PE4          /*!< Set PE4 function to EPWM0_CH3        */
+#define SET_EPWM0_CH4_PE3()      SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EPWM0_CH4_PE3_Msk)) | EPWM0_CH4_PE3          /*!< Set PE3 function to EPWM0_CH4        */
+#define SET_EPWM0_CH4_PD14()     SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EPWM0_CH4_PD14_Msk)) | EPWM0_CH4_PD14        /*!< Set PD14 function to EPWM0_CH4       */
+#define SET_EPWM0_CH4_PA1()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM0_CH4_PA1_Msk)) | EPWM0_CH4_PA1          /*!< Set PA1 function to EPWM0_CH4        */
+#define SET_EPWM0_CH4_PE12()     SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_CH4_PE12_Msk)) | EPWM0_CH4_PE12        /*!< Set PE12 function to EPWM0_CH4       */
+#define SET_EPWM0_CH4_PB1()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_CH4_PB1_Msk)) | EPWM0_CH4_PB1          /*!< Set PB1 function to EPWM0_CH4        */
+#define SET_EPWM0_CH5_PA0()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM0_CH5_PA0_Msk)) | EPWM0_CH5_PA0          /*!< Set PA0 function to EPWM0_CH5        */
+#define SET_EPWM0_CH5_PB0()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_CH5_PB0_Msk)) | EPWM0_CH5_PB0          /*!< Set PB0 function to EPWM0_CH5        */
+#define SET_EPWM0_CH5_PE13()     SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_CH5_PE13_Msk)) | EPWM0_CH5_PE13        /*!< Set PE13 function to EPWM0_CH5       */
+#define SET_EPWM0_CH5_PE2()      SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EPWM0_CH5_PE2_Msk)) | EPWM0_CH5_PE2          /*!< Set PE2 function to EPWM0_CH5        */
+#define SET_EPWM0_CH5_PH11()     SYS->GPH_MFPH = (SYS->GPH_MFPH & (~EPWM0_CH5_PH11_Msk)) | EPWM0_CH5_PH11        /*!< Set PH11 function to EPWM0_CH5       */
+#define SET_EPWM0_SYNC_IN_PA15() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~EPWM0_SYNC_IN_PA15_Msk)) | EPWM0_SYNC_IN_PA15/*!< Set PA15 function to EPWM0_SYNC_IN   */
+#define SET_EPWM0_SYNC_OUT_PA11() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~EPWM0_SYNC_OUT_PA11_Msk)) | EPWM0_SYNC_OUT_PA11/*!< Set PA11 function to EPWM0_SYNC_OUT  */
+#define SET_EPWM0_SYNC_OUT_PF5() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EPWM0_SYNC_OUT_PF5_Msk)) | EPWM0_SYNC_OUT_PF5/*!< Set PF5 function to EPWM0_SYNC_OUT   */
+#define SET_EPWM1_BRAKE0_PB7()   SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM1_BRAKE0_PB7_Msk)) | EPWM1_BRAKE0_PB7    /*!< Set PB7 function to EPWM1_BRAKE0     */
+#define SET_EPWM1_BRAKE0_PE10()  SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM1_BRAKE0_PE10_Msk)) | EPWM1_BRAKE0_PE10  /*!< Set PE10 function to EPWM1_BRAKE0    */
+#define SET_EPWM1_BRAKE1_PB6()   SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM1_BRAKE1_PB6_Msk)) | EPWM1_BRAKE1_PB6    /*!< Set PB6 function to EPWM1_BRAKE1     */
+#define SET_EPWM1_BRAKE1_PA3()   SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM1_BRAKE1_PA3_Msk)) | EPWM1_BRAKE1_PA3    /*!< Set PA3 function to EPWM1_BRAKE1     */
+#define SET_EPWM1_BRAKE1_PE11()  SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM1_BRAKE1_PE11_Msk)) | EPWM1_BRAKE1_PE11  /*!< Set PE11 function to EPWM1_BRAKE1    */
+#define SET_EPWM1_CH0_PE13()     SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM1_CH0_PE13_Msk)) | EPWM1_CH0_PE13        /*!< Set PE13 function to EPWM1_CH0       */
+#define SET_EPWM1_CH0_PC12()     SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EPWM1_CH0_PC12_Msk)) | EPWM1_CH0_PC12        /*!< Set PC12 function to EPWM1_CH0       */
+#define SET_EPWM1_CH0_PB15()     SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EPWM1_CH0_PB15_Msk)) | EPWM1_CH0_PB15        /*!< Set PB15 function to EPWM1_CH0       */
+#define SET_EPWM1_CH0_PC5()      SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH0_PC5_Msk)) | EPWM1_CH0_PC5          /*!< Set PC5 function to EPWM1_CH0        */
+#define SET_EPWM1_CH1_PC8()      SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EPWM1_CH1_PC8_Msk)) | EPWM1_CH1_PC8          /*!< Set PC8 function to EPWM1_CH1        */
+#define SET_EPWM1_CH1_PC11()     SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EPWM1_CH1_PC11_Msk)) | EPWM1_CH1_PC11        /*!< Set PC11 function to EPWM1_CH1       */
+#define SET_EPWM1_CH1_PB14()     SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EPWM1_CH1_PB14_Msk)) | EPWM1_CH1_PB14        /*!< Set PB14 function to EPWM1_CH1       */
+#define SET_EPWM1_CH1_PC4()      SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH1_PC4_Msk)) | EPWM1_CH1_PC4          /*!< Set PC4 function to EPWM1_CH1        */
+#define SET_EPWM1_CH2_PC7()      SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH2_PC7_Msk)) | EPWM1_CH2_PC7          /*!< Set PC7 function to EPWM1_CH2        */
+#define SET_EPWM1_CH2_PC3()      SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH2_PC3_Msk)) | EPWM1_CH2_PC3          /*!< Set PC3 function to EPWM1_CH2        */
+#define SET_EPWM1_CH2_PC10()     SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EPWM1_CH2_PC10_Msk)) | EPWM1_CH2_PC10        /*!< Set PC10 function to EPWM1_CH2       */
+#define SET_EPWM1_CH2_PB13()     SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EPWM1_CH2_PB13_Msk)) | EPWM1_CH2_PB13        /*!< Set PB13 function to EPWM1_CH2       */
+#define SET_EPWM1_CH3_PC6()      SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH3_PC6_Msk)) | EPWM1_CH3_PC6          /*!< Set PC6 function to EPWM1_CH3        */
+#define SET_EPWM1_CH3_PC2()      SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH3_PC2_Msk)) | EPWM1_CH3_PC2          /*!< Set PC2 function to EPWM1_CH3        */
+#define SET_EPWM1_CH3_PB12()     SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EPWM1_CH3_PB12_Msk)) | EPWM1_CH3_PB12        /*!< Set PB12 function to EPWM1_CH3       */
+#define SET_EPWM1_CH3_PC9()      SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EPWM1_CH3_PC9_Msk)) | EPWM1_CH3_PC9          /*!< Set PC9 function to EPWM1_CH3        */
+#define SET_EPWM1_CH4_PC1()      SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH4_PC1_Msk)) | EPWM1_CH4_PC1          /*!< Set PC1 function to EPWM1_CH4        */
+#define SET_EPWM1_CH4_PB1()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM1_CH4_PB1_Msk)) | EPWM1_CH4_PB1          /*!< Set PB1 function to EPWM1_CH4        */
+#define SET_EPWM1_CH4_PB7()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM1_CH4_PB7_Msk)) | EPWM1_CH4_PB7          /*!< Set PB7 function to EPWM1_CH4        */
+#define SET_EPWM1_CH4_PA7()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM1_CH4_PA7_Msk)) | EPWM1_CH4_PA7          /*!< Set PA7 function to EPWM1_CH4        */
+#define SET_EPWM1_CH5_PB6()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM1_CH5_PB6_Msk)) | EPWM1_CH5_PB6          /*!< Set PB6 function to EPWM1_CH5        */
+#define SET_EPWM1_CH5_PC0()      SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH5_PC0_Msk)) | EPWM1_CH5_PC0          /*!< Set PC0 function to EPWM1_CH5        */
+#define SET_EPWM1_CH5_PB0()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM1_CH5_PB0_Msk)) | EPWM1_CH5_PB0          /*!< Set PB0 function to EPWM1_CH5        */
+#define SET_EPWM1_CH5_PA6()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM1_CH5_PA6_Msk)) | EPWM1_CH5_PA6          /*!< Set PA6 function to EPWM1_CH5        */
+#define SET_I2C0_SCL_PE13()      SYS->GPE_MFPH = (SYS->GPE_MFPH & (~I2C0_SCL_PE13_Msk)) | I2C0_SCL_PE13          /*!< Set PE13 function to I2C0_SCL        */
+#define SET_I2C0_SCL_PB9()       SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C0_SCL_PB9_Msk)) | I2C0_SCL_PB9            /*!< Set PB9 function to I2C0_SCL         */
+#define SET_I2C0_SCL_PD7()       SYS->GPD_MFPL = (SYS->GPD_MFPL & (~I2C0_SCL_PD7_Msk)) | I2C0_SCL_PD7            /*!< Set PD7 function to I2C0_SCL         */
+#define SET_I2C0_SCL_PA5()       SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C0_SCL_PA5_Msk)) | I2C0_SCL_PA5            /*!< Set PA5 function to I2C0_SCL         */
+#define SET_I2C0_SCL_PB5()       SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2C0_SCL_PB5_Msk)) | I2C0_SCL_PB5            /*!< Set PB5 function to I2C0_SCL         */
+#define SET_I2C0_SCL_PC1()       SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C0_SCL_PC1_Msk)) | I2C0_SCL_PC1            /*!< Set PC1 function to I2C0_SCL         */
+#define SET_I2C0_SCL_PC12()      SYS->GPC_MFPH = (SYS->GPC_MFPH & (~I2C0_SCL_PC12_Msk)) | I2C0_SCL_PC12          /*!< Set PC12 function to I2C0_SCL        */
+#define SET_I2C0_SCL_PF3()       SYS->GPF_MFPL = (SYS->GPF_MFPL & (~I2C0_SCL_PF3_Msk)) | I2C0_SCL_PF3            /*!< Set PF3 function to I2C0_SCL         */
+#define SET_I2C0_SDA_PB4()       SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2C0_SDA_PB4_Msk)) | I2C0_SDA_PB4            /*!< Set PB4 function to I2C0_SDA         */
+#define SET_I2C0_SDA_PD6()       SYS->GPD_MFPL = (SYS->GPD_MFPL & (~I2C0_SDA_PD6_Msk)) | I2C0_SDA_PD6            /*!< Set PD6 function to I2C0_SDA         */
+#define SET_I2C0_SDA_PB8()       SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C0_SDA_PB8_Msk)) | I2C0_SDA_PB8            /*!< Set PB8 function to I2C0_SDA         */
+#define SET_I2C0_SDA_PC11()      SYS->GPC_MFPH = (SYS->GPC_MFPH & (~I2C0_SDA_PC11_Msk)) | I2C0_SDA_PC11          /*!< Set PC11 function to I2C0_SDA        */
+#define SET_I2C0_SDA_PF2()       SYS->GPF_MFPL = (SYS->GPF_MFPL & (~I2C0_SDA_PF2_Msk)) | I2C0_SDA_PF2            /*!< Set PF2 function to I2C0_SDA         */
+#define SET_I2C0_SDA_PC0()       SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C0_SDA_PC0_Msk)) | I2C0_SDA_PC0            /*!< Set PC0 function to I2C0_SDA         */
+#define SET_I2C0_SDA_PC8()       SYS->GPC_MFPH = (SYS->GPC_MFPH & (~I2C0_SDA_PC8_Msk)) | I2C0_SDA_PC8            /*!< Set PC8 function to I2C0_SDA         */
+#define SET_I2C0_SDA_PA4()       SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C0_SDA_PA4_Msk)) | I2C0_SDA_PA4            /*!< Set PA4 function to I2C0_SDA         */
+#define SET_I2C0_SMBAL_PA3()     SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C0_SMBAL_PA3_Msk)) | I2C0_SMBAL_PA3        /*!< Set PA3 function to I2C0_SMBAL       */
+#define SET_I2C0_SMBAL_PG2()     SYS->GPG_MFPL = (SYS->GPG_MFPL & (~I2C0_SMBAL_PG2_Msk)) | I2C0_SMBAL_PG2        /*!< Set PG2 function to I2C0_SMBAL       */
+#define SET_I2C0_SMBAL_PC3()     SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C0_SMBAL_PC3_Msk)) | I2C0_SMBAL_PC3        /*!< Set PC3 function to I2C0_SMBAL       */
+#define SET_I2C0_SMBSUS_PA2()    SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C0_SMBSUS_PA2_Msk)) | I2C0_SMBSUS_PA2      /*!< Set PA2 function to I2C0_SMBSUS      */
+#define SET_I2C0_SMBSUS_PC2()    SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C0_SMBSUS_PC2_Msk)) | I2C0_SMBSUS_PC2      /*!< Set PC2 function to I2C0_SMBSUS      */
+#define SET_I2C0_SMBSUS_PG3()    SYS->GPG_MFPL = (SYS->GPG_MFPL & (~I2C0_SMBSUS_PG3_Msk)) | I2C0_SMBSUS_PG3      /*!< Set PG3 function to I2C0_SMBSUS      */
+#define SET_I2C1_SCL_PB1()       SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2C1_SCL_PB1_Msk)) | I2C1_SCL_PB1            /*!< Set PB1 function to I2C1_SCL         */
+#define SET_I2C1_SCL_PE1()       SYS->GPE_MFPL = (SYS->GPE_MFPL & (~I2C1_SCL_PE1_Msk)) | I2C1_SCL_PE1            /*!< Set PE1 function to I2C1_SCL         */
+#define SET_I2C1_SCL_PF0()       SYS->GPF_MFPL = (SYS->GPF_MFPL & (~I2C1_SCL_PF0_Msk)) | I2C1_SCL_PF0            /*!< Set PF0 function to I2C1_SCL         */
+#define SET_I2C1_SCL_PA12()      SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2C1_SCL_PA12_Msk)) | I2C1_SCL_PA12          /*!< Set PA12 function to I2C1_SCL        */
+#define SET_I2C1_SCL_PA7()       SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C1_SCL_PA7_Msk)) | I2C1_SCL_PA7            /*!< Set PA7 function to I2C1_SCL         */
+#define SET_I2C1_SCL_PB11()      SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C1_SCL_PB11_Msk)) | I2C1_SCL_PB11          /*!< Set PB11 function to I2C1_SCL        */
+#define SET_I2C1_SCL_PG2()       SYS->GPG_MFPL = (SYS->GPG_MFPL & (~I2C1_SCL_PG2_Msk)) | I2C1_SCL_PG2            /*!< Set PG2 function to I2C1_SCL         */
+#define SET_I2C1_SCL_PA3()       SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C1_SCL_PA3_Msk)) | I2C1_SCL_PA3            /*!< Set PA3 function to I2C1_SCL         */
+#define SET_I2C1_SCL_PC5()       SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C1_SCL_PC5_Msk)) | I2C1_SCL_PC5            /*!< Set PC5 function to I2C1_SCL         */
+#define SET_I2C1_SCL_PD5()       SYS->GPD_MFPL = (SYS->GPD_MFPL & (~I2C1_SCL_PD5_Msk)) | I2C1_SCL_PD5            /*!< Set PD5 function to I2C1_SCL         */
+#define SET_I2C1_SCL_PB3()       SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2C1_SCL_PB3_Msk)) | I2C1_SCL_PB3            /*!< Set PB3 function to I2C1_SCL         */
+#define SET_I2C1_SDA_PA2()       SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C1_SDA_PA2_Msk)) | I2C1_SDA_PA2            /*!< Set PA2 function to I2C1_SDA         */
+#define SET_I2C1_SDA_PB10()      SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C1_SDA_PB10_Msk)) | I2C1_SDA_PB10          /*!< Set PB10 function to I2C1_SDA        */
+#define SET_I2C1_SDA_PF1()       SYS->GPF_MFPL = (SYS->GPF_MFPL & (~I2C1_SDA_PF1_Msk)) | I2C1_SDA_PF1            /*!< Set PF1 function to I2C1_SDA         */
+#define SET_I2C1_SDA_PB2()       SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2C1_SDA_PB2_Msk)) | I2C1_SDA_PB2            /*!< Set PB2 function to I2C1_SDA         */
+#define SET_I2C1_SDA_PD4()       SYS->GPD_MFPL = (SYS->GPD_MFPL & (~I2C1_SDA_PD4_Msk)) | I2C1_SDA_PD4            /*!< Set PD4 function to I2C1_SDA         */
+#define SET_I2C1_SDA_PA13()      SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2C1_SDA_PA13_Msk)) | I2C1_SDA_PA13          /*!< Set PA13 function to I2C1_SDA        */
+#define SET_I2C1_SDA_PA6()       SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C1_SDA_PA6_Msk)) | I2C1_SDA_PA6            /*!< Set PA6 function to I2C1_SDA         */
+#define SET_I2C1_SDA_PE0()       SYS->GPE_MFPL = (SYS->GPE_MFPL & (~I2C1_SDA_PE0_Msk)) | I2C1_SDA_PE0            /*!< Set PE0 function to I2C1_SDA         */
+#define SET_I2C1_SDA_PG3()       SYS->GPG_MFPL = (SYS->GPG_MFPL & (~I2C1_SDA_PG3_Msk)) | I2C1_SDA_PG3            /*!< Set PG3 function to I2C1_SDA         */
+#define SET_I2C1_SDA_PC4()       SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C1_SDA_PC4_Msk)) | I2C1_SDA_PC4            /*!< Set PC4 function to I2C1_SDA         */
+#define SET_I2C1_SDA_PB0()       SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2C1_SDA_PB0_Msk)) | I2C1_SDA_PB0            /*!< Set PB0 function to I2C1_SDA         */
+#define SET_I2C1_SMBAL_PB9()     SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C1_SMBAL_PB9_Msk)) | I2C1_SMBAL_PB9        /*!< Set PB9 function to I2C1_SMBAL       */
+#define SET_I2C1_SMBAL_PH8()     SYS->GPH_MFPH = (SYS->GPH_MFPH & (~I2C1_SMBAL_PH8_Msk)) | I2C1_SMBAL_PH8        /*!< Set PH8 function to I2C1_SMBAL       */
+#define SET_I2C1_SMBAL_PC7()     SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C1_SMBAL_PC7_Msk)) | I2C1_SMBAL_PC7        /*!< Set PC7 function to I2C1_SMBAL       */
+#define SET_I2C1_SMBSUS_PC6()    SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C1_SMBSUS_PC6_Msk)) | I2C1_SMBSUS_PC6      /*!< Set PC6 function to I2C1_SMBSUS      */
+#define SET_I2C1_SMBSUS_PB8()    SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C1_SMBSUS_PB8_Msk)) | I2C1_SMBSUS_PB8      /*!< Set PB8 function to I2C1_SMBSUS      */
+#define SET_I2C1_SMBSUS_PH9()    SYS->GPH_MFPH = (SYS->GPH_MFPH & (~I2C1_SMBSUS_PH9_Msk)) | I2C1_SMBSUS_PH9      /*!< Set PH9 function to I2C1_SMBSUS      */
+#define SET_I2C2_SCL_PA14()      SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2C2_SCL_PA14_Msk)) | I2C2_SCL_PA14          /*!< Set PA14 function to I2C2_SCL        */
+#define SET_I2C2_SCL_PH8()       SYS->GPH_MFPH = (SYS->GPH_MFPH & (~I2C2_SCL_PH8_Msk)) | I2C2_SCL_PH8            /*!< Set PH8 function to I2C2_SCL         */
+#define SET_I2C2_SCL_PA11()      SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2C2_SCL_PA11_Msk)) | I2C2_SCL_PA11          /*!< Set PA11 function to I2C2_SCL        */
+#define SET_I2C2_SCL_PB13()      SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C2_SCL_PB13_Msk)) | I2C2_SCL_PB13          /*!< Set PB13 function to I2C2_SCL        */
+#define SET_I2C2_SCL_PD9()       SYS->GPD_MFPH = (SYS->GPD_MFPH & (~I2C2_SCL_PD9_Msk)) | I2C2_SCL_PD9            /*!< Set PD9 function to I2C2_SCL         */
+#define SET_I2C2_SCL_PA1()       SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C2_SCL_PA1_Msk)) | I2C2_SCL_PA1            /*!< Set PA1 function to I2C2_SCL         */
+#define SET_I2C2_SCL_PD1()       SYS->GPD_MFPL = (SYS->GPD_MFPL & (~I2C2_SCL_PD1_Msk)) | I2C2_SCL_PD1            /*!< Set PD1 function to I2C2_SCL         */
+#define SET_I2C2_SDA_PD8()       SYS->GPD_MFPH = (SYS->GPD_MFPH & (~I2C2_SDA_PD8_Msk)) | I2C2_SDA_PD8            /*!< Set PD8 function to I2C2_SDA         */
+#define SET_I2C2_SDA_PD0()       SYS->GPD_MFPL = (SYS->GPD_MFPL & (~I2C2_SDA_PD0_Msk)) | I2C2_SDA_PD0            /*!< Set PD0 function to I2C2_SDA         */
+#define SET_I2C2_SDA_PA15()      SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2C2_SDA_PA15_Msk)) | I2C2_SDA_PA15          /*!< Set PA15 function to I2C2_SDA        */
+#define SET_I2C2_SDA_PH9()       SYS->GPH_MFPH = (SYS->GPH_MFPH & (~I2C2_SDA_PH9_Msk)) | I2C2_SDA_PH9            /*!< Set PH9 function to I2C2_SDA         */
+#define SET_I2C2_SDA_PA10()      SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2C2_SDA_PA10_Msk)) | I2C2_SDA_PA10          /*!< Set PA10 function to I2C2_SDA        */
+#define SET_I2C2_SDA_PA0()       SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C2_SDA_PA0_Msk)) | I2C2_SDA_PA0            /*!< Set PA0 function to I2C2_SDA         */
+#define SET_I2C2_SDA_PB12()      SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C2_SDA_PB12_Msk)) | I2C2_SDA_PB12          /*!< Set PB12 function to I2C2_SDA        */
+#define SET_I2C2_SMBAL_PB15()    SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C2_SMBAL_PB15_Msk)) | I2C2_SMBAL_PB15      /*!< Set PB15 function to I2C2_SMBAL      */
+#define SET_I2C2_SMBSUS_PB14()   SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C2_SMBSUS_PB14_Msk)) | I2C2_SMBSUS_PB14    /*!< Set PB14 function to I2C2_SMBSUS     */
+#define SET_I2S0_BCLK_PF10()     SYS->GPF_MFPH = (SYS->GPF_MFPH & (~I2S0_BCLK_PF10_Msk)) | I2S0_BCLK_PF10        /*!< Set PF10 function to I2S0_BCLK       */
+#define SET_I2S0_BCLK_PB5()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2S0_BCLK_PB5_Msk)) | I2S0_BCLK_PB5          /*!< Set PB5 function to I2S0_BCLK        */
+#define SET_I2S0_BCLK_PE1()      SYS->GPE_MFPL = (SYS->GPE_MFPL & (~I2S0_BCLK_PE1_Msk)) | I2S0_BCLK_PE1          /*!< Set PE1 function to I2S0_BCLK        */
+#define SET_I2S0_BCLK_PA12()     SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2S0_BCLK_PA12_Msk)) | I2S0_BCLK_PA12        /*!< Set PA12 function to I2S0_BCLK       */
+#define SET_I2S0_BCLK_PC4()      SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2S0_BCLK_PC4_Msk)) | I2S0_BCLK_PC4          /*!< Set PC4 function to I2S0_BCLK        */
+#define SET_I2S0_BCLK_PE8()      SYS->GPE_MFPH = (SYS->GPE_MFPH & (~I2S0_BCLK_PE8_Msk)) | I2S0_BCLK_PE8          /*!< Set PE8 function to I2S0_BCLK        */
+#define SET_I2S0_DI_PC2()        SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2S0_DI_PC2_Msk)) | I2S0_DI_PC2              /*!< Set PC2 function to I2S0_DI          */
+#define SET_I2S0_DI_PE10()       SYS->GPE_MFPH = (SYS->GPE_MFPH & (~I2S0_DI_PE10_Msk)) | I2S0_DI_PE10            /*!< Set PE10 function to I2S0_DI         */
+#define SET_I2S0_DI_PF8()        SYS->GPF_MFPH = (SYS->GPF_MFPH & (~I2S0_DI_PF8_Msk)) | I2S0_DI_PF8              /*!< Set PF8 function to I2S0_DI          */
+#define SET_I2S0_DI_PH8()        SYS->GPH_MFPH = (SYS->GPH_MFPH & (~I2S0_DI_PH8_Msk)) | I2S0_DI_PH8              /*!< Set PH8 function to I2S0_DI          */
+#define SET_I2S0_DI_PB3()        SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2S0_DI_PB3_Msk)) | I2S0_DI_PB3              /*!< Set PB3 function to I2S0_DI          */
+#define SET_I2S0_DI_PA14()       SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2S0_DI_PA14_Msk)) | I2S0_DI_PA14            /*!< Set PA14 function to I2S0_DI         */
+#define SET_I2S0_DO_PH9()        SYS->GPH_MFPH = (SYS->GPH_MFPH & (~I2S0_DO_PH9_Msk)) | I2S0_DO_PH9              /*!< Set PH9 function to I2S0_DO          */
+#define SET_I2S0_DO_PC1()        SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2S0_DO_PC1_Msk)) | I2S0_DO_PC1              /*!< Set PC1 function to I2S0_DO          */
+#define SET_I2S0_DO_PA15()       SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2S0_DO_PA15_Msk)) | I2S0_DO_PA15            /*!< Set PA15 function to I2S0_DO         */
+#define SET_I2S0_DO_PB2()        SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2S0_DO_PB2_Msk)) | I2S0_DO_PB2              /*!< Set PB2 function to I2S0_DO          */
+#define SET_I2S0_DO_PF7()        SYS->GPF_MFPL = (SYS->GPF_MFPL & (~I2S0_DO_PF7_Msk)) | I2S0_DO_PF7              /*!< Set PF7 function to I2S0_DO          */
+#define SET_I2S0_DO_PE11()       SYS->GPE_MFPH = (SYS->GPE_MFPH & (~I2S0_DO_PE11_Msk)) | I2S0_DO_PE11            /*!< Set PE11 function to I2S0_DO         */
+#define SET_I2S0_LRCK_PC0()      SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2S0_LRCK_PC0_Msk)) | I2S0_LRCK_PC0          /*!< Set PC0 function to I2S0_LRCK        */
+#define SET_I2S0_LRCK_PB1()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2S0_LRCK_PB1_Msk)) | I2S0_LRCK_PB1          /*!< Set PB1 function to I2S0_LRCK        */
+#define SET_I2S0_LRCK_PH10()     SYS->GPH_MFPH = (SYS->GPH_MFPH & (~I2S0_LRCK_PH10_Msk)) | I2S0_LRCK_PH10        /*!< Set PH10 function to I2S0_LRCK       */
+#define SET_I2S0_LRCK_PF6()      SYS->GPF_MFPL = (SYS->GPF_MFPL & (~I2S0_LRCK_PF6_Msk)) | I2S0_LRCK_PF6          /*!< Set PF6 function to I2S0_LRCK        */
+#define SET_I2S0_LRCK_PE12()     SYS->GPE_MFPH = (SYS->GPE_MFPH & (~I2S0_LRCK_PE12_Msk)) | I2S0_LRCK_PE12        /*!< Set PE12 function to I2S0_LRCK       */
+#define SET_I2S0_MCLK_PC3()      SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2S0_MCLK_PC3_Msk)) | I2S0_MCLK_PC3          /*!< Set PC3 function to I2S0_MCLK        */
+#define SET_I2S0_MCLK_PF9()      SYS->GPF_MFPH = (SYS->GPF_MFPH & (~I2S0_MCLK_PF9_Msk)) | I2S0_MCLK_PF9          /*!< Set PF9 function to I2S0_MCLK        */
+#define SET_I2S0_MCLK_PE0()      SYS->GPE_MFPL = (SYS->GPE_MFPL & (~I2S0_MCLK_PE0_Msk)) | I2S0_MCLK_PE0          /*!< Set PE0 function to I2S0_MCLK        */
+#define SET_I2S0_MCLK_PB4()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2S0_MCLK_PB4_Msk)) | I2S0_MCLK_PB4          /*!< Set PB4 function to I2S0_MCLK        */
+#define SET_I2S0_MCLK_PA13()     SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2S0_MCLK_PA13_Msk)) | I2S0_MCLK_PA13        /*!< Set PA13 function to I2S0_MCLK       */
+#define SET_I2S0_MCLK_PE9()      SYS->GPE_MFPH = (SYS->GPE_MFPH & (~I2S0_MCLK_PE9_Msk)) | I2S0_MCLK_PE9          /*!< Set PE9 function to I2S0_MCLK        */
+#define SET_ICE_CLK_PF1()        SYS->GPF_MFPL = (SYS->GPF_MFPL & (~ICE_CLK_PF1_Msk)) | ICE_CLK_PF1              /*!< Set PF1 function to ICE_CLK          */
+#define SET_ICE_DAT_PF0()        SYS->GPF_MFPL = (SYS->GPF_MFPL & (~ICE_DAT_PF0_Msk)) | ICE_DAT_PF0              /*!< Set PF0 function to ICE_DAT          */
+#define SET_INT0_PA6()           SYS->GPA_MFPL = (SYS->GPA_MFPL & (~INT0_PA6_Msk)) | INT0_PA6                    /*!< Set PA6 function to INT0             */
+#define SET_INT0_PB5()           SYS->GPB_MFPL = (SYS->GPB_MFPL & (~INT0_PB5_Msk)) | INT0_PB5                    /*!< Set PB5 function to INT0             */
+#define SET_INT1_PB4()           SYS->GPB_MFPL = (SYS->GPB_MFPL & (~INT1_PB4_Msk)) | INT1_PB4                    /*!< Set PB4 function to INT1             */
+#define SET_INT1_PA7()           SYS->GPA_MFPL = (SYS->GPA_MFPL & (~INT1_PA7_Msk)) | INT1_PA7                    /*!< Set PA7 function to INT1             */
+#define SET_INT2_PB3()           SYS->GPB_MFPL = (SYS->GPB_MFPL & (~INT2_PB3_Msk)) | INT2_PB3                    /*!< Set PB3 function to INT2             */
+#define SET_INT2_PC6()           SYS->GPC_MFPL = (SYS->GPC_MFPL & (~INT2_PC6_Msk)) | INT2_PC6                    /*!< Set PC6 function to INT2             */
+#define SET_INT3_PB2()           SYS->GPB_MFPL = (SYS->GPB_MFPL & (~INT3_PB2_Msk)) | INT3_PB2                    /*!< Set PB2 function to INT3             */
+#define SET_INT3_PC7()           SYS->GPC_MFPL = (SYS->GPC_MFPL & (~INT3_PC7_Msk)) | INT3_PC7                    /*!< Set PC7 function to INT3             */
+#define SET_INT4_PA8()           SYS->GPA_MFPH = (SYS->GPA_MFPH & (~INT4_PA8_Msk)) | INT4_PA8                    /*!< Set PA8 function to INT4             */
+#define SET_INT4_PB6()           SYS->GPB_MFPL = (SYS->GPB_MFPL & (~INT4_PB6_Msk)) | INT4_PB6                    /*!< Set PB6 function to INT4             */
+#define SET_INT5_PB7()           SYS->GPB_MFPL = (SYS->GPB_MFPL & (~INT5_PB7_Msk)) | INT5_PB7                    /*!< Set PB7 function to INT5             */
+#define SET_INT5_PD12()          SYS->GPD_MFPH = (SYS->GPD_MFPH & (~INT5_PD12_Msk)) | INT5_PD12                  /*!< Set PD12 function to INT5            */
+#define SET_INT6_PD11()          SYS->GPD_MFPH = (SYS->GPD_MFPH & (~INT6_PD11_Msk)) | INT6_PD11                  /*!< Set PD11 function to INT6            */
+#define SET_INT6_PB8()           SYS->GPB_MFPH = (SYS->GPB_MFPH & (~INT6_PB8_Msk)) | INT6_PB8                    /*!< Set PB8 function to INT6             */
+#define SET_INT7_PB9()           SYS->GPB_MFPH = (SYS->GPB_MFPH & (~INT7_PB9_Msk)) | INT7_PB9                    /*!< Set PB9 function to INT7             */
+#define SET_INT7_PD10()          SYS->GPD_MFPH = (SYS->GPD_MFPH & (~INT7_PD10_Msk)) | INT7_PD10                  /*!< Set PD10 function to INT7            */
+#define SET_LCD_COM0_PC0()       SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_COM0_PC0_Msk)) | LCD_COM0_PC0            /*!< Set PC0 function to LCD_COM0         */
+#define SET_LCD_COM1_PC1()       SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_COM1_PC1_Msk)) | LCD_COM1_PC1            /*!< Set PC1 function to LCD_COM1         */
+#define SET_LCD_COM2_PC2()       SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_COM2_PC2_Msk)) | LCD_COM2_PC2            /*!< Set PC2 function to LCD_COM2         */
+#define SET_LCD_COM3_PC3()       SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_COM3_PC3_Msk)) | LCD_COM3_PC3            /*!< Set PC3 function to LCD_COM3         */
+#define SET_LCD_COM4_PC4()       SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_COM4_PC4_Msk)) | LCD_COM4_PC4            /*!< Set PC4 function to LCD_COM4         */
+#define SET_LCD_COM5_PC5()       SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_COM5_PC5_Msk)) | LCD_COM5_PC5            /*!< Set PC5 function to LCD_COM5         */
+#define SET_LCD_COM6_PA0()       SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_COM6_PA0_Msk)) | LCD_COM6_PA0            /*!< Set PA0 function to LCD_COM6         */
+#define SET_LCD_COM6_PD8()       SYS->GPD_MFPH = (SYS->GPD_MFPH & (~LCD_COM6_PD8_Msk)) | LCD_COM6_PD8            /*!< Set PD8 function to LCD_SEG41        */
+#define SET_LCD_COM7_PA1()       SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_COM7_PA1_Msk)) | LCD_COM7_PA1            /*!< Set PA1 function to LCD_COM7         */
+#define SET_LCD_COM7_PD9()       SYS->GPD_MFPH = (SYS->GPD_MFPH & (~LCD_COM7_PD9_Msk)) | LCD_COM7_PD9            /*!< Set PD9 function to LCD_COM7         */
+#define SET_LCD_SEG0_PD14()      SYS->GPD_MFPH = (SYS->GPD_MFPH & (~LCD_SEG0_PD14_Msk)) | LCD_SEG0_PD14          /*!< Set PD14 function to LCD_SEG0        */
+#define SET_LCD_SEG0_PD1()       SYS->GPD_MFPL = (SYS->GPD_MFPL & (~LCD_SEG0_PD1_Msk)) | LCD_SEG0_PD1            /*!< Set PD1 function to LCD_SEG0         */
+#define SET_LCD_SEG1_PD2()       SYS->GPD_MFPL = (SYS->GPD_MFPL & (~LCD_SEG1_PD2_Msk)) | LCD_SEG1_PD2            /*!< Set PD2 function to LCD_SEG1         */
+#define SET_LCD_SEG1_PH11()      SYS->GPH_MFPH = (SYS->GPH_MFPH & (~LCD_SEG1_PH11_Msk)) | LCD_SEG1_PH11          /*!< Set PH11 function to LCD_SEG1        */
+#define SET_LCD_SEG10_PC7()      SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_SEG10_PC7_Msk)) | LCD_SEG10_PC7          /*!< Set PC7 function to LCD_SEG10        */
+#define SET_LCD_SEG10_PE5()      SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG10_PE5_Msk)) | LCD_SEG10_PE5          /*!< Set PE5 function to LCD_SEG10        */
+#define SET_LCD_SEG11_PA8()      SYS->GPA_MFPH = (SYS->GPA_MFPH & (~LCD_SEG11_PA8_Msk)) | LCD_SEG11_PA8          /*!< Set PA8 function to LCD_SEG11        */
+#define SET_LCD_SEG11_PE6()      SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG11_PE6_Msk)) | LCD_SEG11_PE6          /*!< Set PE6 function to LCD_SEG11        */
+#define SET_LCD_SEG12_PA9()      SYS->GPA_MFPH = (SYS->GPA_MFPH & (~LCD_SEG12_PA9_Msk)) | LCD_SEG12_PA9          /*!< Set PA9 function to LCD_SEG12        */
+#define SET_LCD_SEG12_PE7()      SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG12_PE7_Msk)) | LCD_SEG12_PE7          /*!< Set PE7 function to LCD_SEG12        */
+#define SET_LCD_SEG13_PD6()      SYS->GPD_MFPL = (SYS->GPD_MFPL & (~LCD_SEG13_PD6_Msk)) | LCD_SEG13_PD6          /*!< Set PD6 function to LCD_SEG13        */
+#define SET_LCD_SEG13_PA1()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG13_PA1_Msk)) | LCD_SEG13_PA1          /*!< Set PA1 function to LCD_SEG13        */
+#define SET_LCD_SEG14_PD7()      SYS->GPD_MFPL = (SYS->GPD_MFPL & (~LCD_SEG14_PD7_Msk)) | LCD_SEG14_PD7          /*!< Set PD7 function to LCD_SEG14        */
+#define SET_LCD_SEG14_PA0()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG14_PA0_Msk)) | LCD_SEG14_PA0          /*!< Set PA0 function to LCD_SEG14        */
+#define SET_LCD_SEG15_PG15()     SYS->GPG_MFPH = (SYS->GPG_MFPH & (~LCD_SEG15_PG15_Msk)) | LCD_SEG15_PG15        /*!< Set PG15 function to LCD_SEG15       */
+#define SET_LCD_SEG16_PG14()     SYS->GPG_MFPH = (SYS->GPG_MFPH & (~LCD_SEG16_PG14_Msk)) | LCD_SEG16_PG14        /*!< Set PG14 function to LCD_SEG16       */
+#define SET_LCD_SEG17_PG13()     SYS->GPG_MFPH = (SYS->GPG_MFPH & (~LCD_SEG17_PG13_Msk)) | LCD_SEG17_PG13        /*!< Set PG13 function to LCD_SEG17       */
+#define SET_LCD_SEG18_PG12()     SYS->GPG_MFPH = (SYS->GPG_MFPH & (~LCD_SEG18_PG12_Msk)) | LCD_SEG18_PG12        /*!< Set PG12 function to LCD_SEG18       */
+#define SET_LCD_SEG19_PG11()     SYS->GPG_MFPH = (SYS->GPG_MFPH & (~LCD_SEG19_PG11_Msk)) | LCD_SEG19_PG11        /*!< Set PG11 function to LCD_SEG19       */
+#define SET_LCD_SEG2_PH10()      SYS->GPH_MFPH = (SYS->GPH_MFPH & (~LCD_SEG2_PH10_Msk)) | LCD_SEG2_PH10          /*!< Set PH10 function to LCD_SEG2        */
+#define SET_LCD_SEG2_PD3()       SYS->GPD_MFPL = (SYS->GPD_MFPL & (~LCD_SEG2_PD3_Msk)) | LCD_SEG2_PD3            /*!< Set PD3 function to LCD_SEG2         */
+#define SET_LCD_SEG20_PG10()     SYS->GPG_MFPH = (SYS->GPG_MFPH & (~LCD_SEG20_PG10_Msk)) | LCD_SEG20_PG10        /*!< Set PG10 function to LCD_SEG20       */
+#define SET_LCD_SEG21_PG9()      SYS->GPG_MFPH = (SYS->GPG_MFPH & (~LCD_SEG21_PG9_Msk)) | LCD_SEG21_PG9          /*!< Set PG9 function to LCD_SEG21        */
+#define SET_LCD_SEG22_PE15()     SYS->GPE_MFPH = (SYS->GPE_MFPH & (~LCD_SEG22_PE15_Msk)) | LCD_SEG22_PE15        /*!< Set PE15 function to LCD_SEG22       */
+#define SET_LCD_SEG23_PE14()     SYS->GPE_MFPH = (SYS->GPE_MFPH & (~LCD_SEG23_PE14_Msk)) | LCD_SEG23_PE14        /*!< Set PE14 function to LCD_SEG23       */
+#define SET_LCD_SEG24_PA0()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG24_PA0_Msk)) | LCD_SEG24_PA0          /*!< Set PA0 function to LCD_SEG24        */
+#define SET_LCD_SEG25_PA1()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG25_PA1_Msk)) | LCD_SEG25_PA1          /*!< Set PA1 function to LCD_SEG25        */
+#define SET_LCD_SEG26_PA2()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG26_PA2_Msk)) | LCD_SEG26_PA2          /*!< Set PA2 function to LCD_SEG26        */
+#define SET_LCD_SEG27_PA3()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG27_PA3_Msk)) | LCD_SEG27_PA3          /*!< Set PA3 function to LCD_SEG27        */
+#define SET_LCD_SEG28_PA4()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG28_PA4_Msk)) | LCD_SEG28_PA4          /*!< Set PA4 function to LCD_SEG28        */
+#define SET_LCD_SEG29_PA5()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG29_PA5_Msk)) | LCD_SEG29_PA5          /*!< Set PA5 function to LCD_SEG29        */
+#define SET_LCD_SEG3_PA2()       SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG3_PA2_Msk)) | LCD_SEG3_PA2            /*!< Set PA2 function to LCD_SEG3         */
+#define SET_LCD_SEG3_PH9()       SYS->GPH_MFPH = (SYS->GPH_MFPH & (~LCD_SEG3_PH9_Msk)) | LCD_SEG3_PH9            /*!< Set PH9 function to LCD_SEG3         */
+#define SET_LCD_SEG30_PE10()     SYS->GPE_MFPH = (SYS->GPE_MFPH & (~LCD_SEG30_PE10_Msk)) | LCD_SEG30_PE10        /*!< Set PE10 function to LCD_SEG30       */
+#define SET_LCD_SEG31_PE9()      SYS->GPE_MFPH = (SYS->GPE_MFPH & (~LCD_SEG31_PE9_Msk)) | LCD_SEG31_PE9          /*!< Set PE9 function to LCD_SEG31        */
+#define SET_LCD_SEG32_PE8()      SYS->GPE_MFPH = (SYS->GPE_MFPH & (~LCD_SEG32_PE8_Msk)) | LCD_SEG32_PE8          /*!< Set PE8 function to LCD_SEG32        */
+#define SET_LCD_SEG33_PH7()      SYS->GPH_MFPL = (SYS->GPH_MFPL & (~LCD_SEG33_PH7_Msk)) | LCD_SEG33_PH7          /*!< Set PH7 function to LCD_SEG33        */
+#define SET_LCD_SEG34_PH6()      SYS->GPH_MFPL = (SYS->GPH_MFPL & (~LCD_SEG34_PH6_Msk)) | LCD_SEG34_PH6          /*!< Set PH6 function to LCD_SEG34        */
+#define SET_LCD_SEG35_PH5()      SYS->GPH_MFPL = (SYS->GPH_MFPL & (~LCD_SEG35_PH5_Msk)) | LCD_SEG35_PH5          /*!< Set PH5 function to LCD_SEG35        */
+#define SET_LCD_SEG36_PH4()      SYS->GPH_MFPL = (SYS->GPH_MFPL & (~LCD_SEG36_PH4_Msk)) | LCD_SEG36_PH4          /*!< Set PH4 function to LCD_SEG36        */
+#define SET_LCD_SEG37_PG4()      SYS->GPG_MFPL = (SYS->GPG_MFPL & (~LCD_SEG37_PG4_Msk)) | LCD_SEG37_PG4          /*!< Set PG4 function to LCD_SEG37        */
+#define SET_LCD_SEG38_PG3()      SYS->GPG_MFPL = (SYS->GPG_MFPL & (~LCD_SEG38_PG3_Msk)) | LCD_SEG38_PG3          /*!< Set PG3 function to LCD_SEG38        */
+#define SET_LCD_SEG39_PG2()      SYS->GPG_MFPL = (SYS->GPG_MFPL & (~LCD_SEG39_PG2_Msk)) | LCD_SEG39_PG2          /*!< Set PG2 function to LCD_SEG39        */
+#define SET_LCD_SEG4_PH8()       SYS->GPH_MFPH = (SYS->GPH_MFPH & (~LCD_SEG4_PH8_Msk)) | LCD_SEG4_PH8            /*!< Set PH8 function to LCD_SEG4         */
+#define SET_LCD_SEG4_PA3()       SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG4_PA3_Msk)) | LCD_SEG4_PA3            /*!< Set PA3 function to LCD_SEG4         */
+#define SET_LCD_SEG40_PD9()      SYS->GPD_MFPH = (SYS->GPD_MFPH & (~LCD_SEG40_PD9_Msk)) | LCD_SEG40_PD9          /*!< Set PD9 function to LCD_SEG40        */
+#define SET_LCD_SEG41_PD8()      SYS->GPD_MFPH = (SYS->GPD_MFPH & (~LCD_SEG41_PD8_Msk)) | LCD_SEG41_PD8          /*!< Set PD8 function to LCD_SEG41        */
+#define SET_LCD_SEG42_PC5()      SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_SEG42_PC5_Msk)) | LCD_SEG42_PC5          /*!< Set PC5 function to LCD_SEG42        */
+#define SET_LCD_SEG43_PC4()      SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_SEG43_PC4_Msk)) | LCD_SEG43_PC4          /*!< Set PC4 function to LCD_SEG43        */
+#define SET_LCD_SEG5_PA4()       SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG5_PA4_Msk)) | LCD_SEG5_PA4            /*!< Set PA4 function to LCD_SEG5         */
+#define SET_LCD_SEG5_PE0()       SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG5_PE0_Msk)) | LCD_SEG5_PE0            /*!< Set PE0 function to LCD_SEG5         */
+#define SET_LCD_SEG6_PE1()       SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG6_PE1_Msk)) | LCD_SEG6_PE1            /*!< Set PE1 function to LCD_SEG6         */
+#define SET_LCD_SEG6_PA5()       SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG6_PA5_Msk)) | LCD_SEG6_PA5            /*!< Set PA5 function to LCD_SEG6         */
+#define SET_LCD_SEG7_PA6()       SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG7_PA6_Msk)) | LCD_SEG7_PA6            /*!< Set PA6 function to LCD_SEG7         */
+#define SET_LCD_SEG7_PE2()       SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG7_PE2_Msk)) | LCD_SEG7_PE2            /*!< Set PE2 function to LCD_SEG7         */
+#define SET_LCD_SEG8_PE3()       SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG8_PE3_Msk)) | LCD_SEG8_PE3            /*!< Set PE3 function to LCD_SEG8         */
+#define SET_LCD_SEG8_PA7()       SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG8_PA7_Msk)) | LCD_SEG8_PA7            /*!< Set PA7 function to LCD_SEG8         */
+#define SET_LCD_SEG9_PC6()       SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_SEG9_PC6_Msk)) | LCD_SEG9_PC6            /*!< Set PC6 function to LCD_SEG9         */
+#define SET_LCD_SEG9_PE4()       SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG9_PE4_Msk)) | LCD_SEG9_PE4            /*!< Set PE4 function to LCD_SEG9         */
+#define SET_QEI0_A_PD11()        SYS->GPD_MFPH = (SYS->GPD_MFPH & (~QEI0_A_PD11_Msk)) | QEI0_A_PD11              /*!< Set PD11 function to QEI0_A          */
+#define SET_QEI0_A_PA4()         SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QEI0_A_PA4_Msk)) | QEI0_A_PA4                /*!< Set PA4 function to QEI0_A           */
+#define SET_QEI0_A_PE3()         SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QEI0_A_PE3_Msk)) | QEI0_A_PE3                /*!< Set PE3 function to QEI0_A           */
+#define SET_QEI0_B_PE2()         SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QEI0_B_PE2_Msk)) | QEI0_B_PE2                /*!< Set PE2 function to QEI0_B           */
+#define SET_QEI0_B_PD10()        SYS->GPD_MFPH = (SYS->GPD_MFPH & (~QEI0_B_PD10_Msk)) | QEI0_B_PD10              /*!< Set PD10 function to QEI0_B          */
+#define SET_QEI0_B_PA3()         SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QEI0_B_PA3_Msk)) | QEI0_B_PA3                /*!< Set PA3 function to QEI0_B           */
+#define SET_QEI0_INDEX_PE4()     SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QEI0_INDEX_PE4_Msk)) | QEI0_INDEX_PE4        /*!< Set PE4 function to QEI0_INDEX       */
+#define SET_QEI0_INDEX_PA5()     SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QEI0_INDEX_PA5_Msk)) | QEI0_INDEX_PA5        /*!< Set PA5 function to QEI0_INDEX       */
+#define SET_QEI0_INDEX_PD12()    SYS->GPD_MFPH = (SYS->GPD_MFPH & (~QEI0_INDEX_PD12_Msk)) | QEI0_INDEX_PD12      /*!< Set PD12 function to QEI0_INDEX      */
+#define SET_QEI1_A_PA13()        SYS->GPA_MFPH = (SYS->GPA_MFPH & (~QEI1_A_PA13_Msk)) | QEI1_A_PA13              /*!< Set PA13 function to QEI1_A          */
+#define SET_QEI1_A_PE6()         SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QEI1_A_PE6_Msk)) | QEI1_A_PE6                /*!< Set PE6 function to QEI1_A           */
+#define SET_QEI1_A_PA9()         SYS->GPA_MFPH = (SYS->GPA_MFPH & (~QEI1_A_PA9_Msk)) | QEI1_A_PA9                /*!< Set PA9 function to QEI1_A           */
+#define SET_QEI1_B_PE5()         SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QEI1_B_PE5_Msk)) | QEI1_B_PE5                /*!< Set PE5 function to QEI1_B           */
+#define SET_QEI1_B_PA8()         SYS->GPA_MFPH = (SYS->GPA_MFPH & (~QEI1_B_PA8_Msk)) | QEI1_B_PA8                /*!< Set PA8 function to QEI1_B           */
+#define SET_QEI1_B_PA14()        SYS->GPA_MFPH = (SYS->GPA_MFPH & (~QEI1_B_PA14_Msk)) | QEI1_B_PA14              /*!< Set PA14 function to QEI1_B          */
+#define SET_QEI1_INDEX_PA10()    SYS->GPA_MFPH = (SYS->GPA_MFPH & (~QEI1_INDEX_PA10_Msk)) | QEI1_INDEX_PA10      /*!< Set PA10 function to QEI1_INDEX      */
+#define SET_QEI1_INDEX_PE7()     SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QEI1_INDEX_PE7_Msk)) | QEI1_INDEX_PE7        /*!< Set PE7 function to QEI1_INDEX       */
+#define SET_QEI1_INDEX_PA12()    SYS->GPA_MFPH = (SYS->GPA_MFPH & (~QEI1_INDEX_PA12_Msk)) | QEI1_INDEX_PA12      /*!< Set PA12 function to QEI1_INDEX      */
+#define SET_QSPI0_CLK_PH8()      SYS->GPH_MFPH = (SYS->GPH_MFPH & (~QSPI0_CLK_PH8_Msk)) | QSPI0_CLK_PH8          /*!< Set PH8 function to QSPI0_CLK        */
+#define SET_QSPI0_CLK_PF2()      SYS->GPF_MFPL = (SYS->GPF_MFPL & (~QSPI0_CLK_PF2_Msk)) | QSPI0_CLK_PF2          /*!< Set PF2 function to QSPI0_CLK        */
+#define SET_QSPI0_CLK_PA2()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QSPI0_CLK_PA2_Msk)) | QSPI0_CLK_PA2          /*!< Set PA2 function to QSPI0_CLK        */
+#define SET_QSPI0_CLK_PC2()      SYS->GPC_MFPL = (SYS->GPC_MFPL & (~QSPI0_CLK_PC2_Msk)) | QSPI0_CLK_PC2          /*!< Set PC2 function to QSPI0_CLK        */
+#define SET_QSPI0_MISO0_PC1()    SYS->GPC_MFPL = (SYS->GPC_MFPL & (~QSPI0_MISO0_PC1_Msk)) | QSPI0_MISO0_PC1      /*!< Set PC1 function to QSPI0_MISO0      */
+#define SET_QSPI0_MISO0_PE1()    SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QSPI0_MISO0_PE1_Msk)) | QSPI0_MISO0_PE1      /*!< Set PE1 function to QSPI0_MISO0      */
+#define SET_QSPI0_MISO0_PA1()    SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QSPI0_MISO0_PA1_Msk)) | QSPI0_MISO0_PA1      /*!< Set PA1 function to QSPI0_MISO0      */
+#define SET_QSPI0_MISO1_PB1()    SYS->GPB_MFPL = (SYS->GPB_MFPL & (~QSPI0_MISO1_PB1_Msk)) | QSPI0_MISO1_PB1      /*!< Set PB1 function to QSPI0_MISO1      */
+#define SET_QSPI0_MISO1_PC5()    SYS->GPC_MFPL = (SYS->GPC_MFPL & (~QSPI0_MISO1_PC5_Msk)) | QSPI0_MISO1_PC5      /*!< Set PC5 function to QSPI0_MISO1      */
+#define SET_QSPI0_MISO1_PH10()   SYS->GPH_MFPH = (SYS->GPH_MFPH & (~QSPI0_MISO1_PH10_Msk)) | QSPI0_MISO1_PH10    /*!< Set PH10 function to QSPI0_MISO1     */
+#define SET_QSPI0_MISO1_PA5()    SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QSPI0_MISO1_PA5_Msk)) | QSPI0_MISO1_PA5      /*!< Set PA5 function to QSPI0_MISO1      */
+#define SET_QSPI0_MOSI0_PC0()    SYS->GPC_MFPL = (SYS->GPC_MFPL & (~QSPI0_MOSI0_PC0_Msk)) | QSPI0_MOSI0_PC0      /*!< Set PC0 function to QSPI0_MOSI0      */
+#define SET_QSPI0_MOSI0_PE0()    SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QSPI0_MOSI0_PE0_Msk)) | QSPI0_MOSI0_PE0      /*!< Set PE0 function to QSPI0_MOSI0      */
+#define SET_QSPI0_MOSI0_PA0()    SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QSPI0_MOSI0_PA0_Msk)) | QSPI0_MOSI0_PA0      /*!< Set PA0 function to QSPI0_MOSI0      */
+#define SET_QSPI0_MOSI1_PC4()    SYS->GPC_MFPL = (SYS->GPC_MFPL & (~QSPI0_MOSI1_PC4_Msk)) | QSPI0_MOSI1_PC4      /*!< Set PC4 function to QSPI0_MOSI1      */
+#define SET_QSPI0_MOSI1_PH11()   SYS->GPH_MFPH = (SYS->GPH_MFPH & (~QSPI0_MOSI1_PH11_Msk)) | QSPI0_MOSI1_PH11    /*!< Set PH11 function to QSPI0_MOSI1     */
+#define SET_QSPI0_MOSI1_PB0()    SYS->GPB_MFPL = (SYS->GPB_MFPL & (~QSPI0_MOSI1_PB0_Msk)) | QSPI0_MOSI1_PB0      /*!< Set PB0 function to QSPI0_MOSI1      */
+#define SET_QSPI0_MOSI1_PA4()    SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QSPI0_MOSI1_PA4_Msk)) | QSPI0_MOSI1_PA4      /*!< Set PA4 function to QSPI0_MOSI1      */
+#define SET_QSPI0_SS_PA3()       SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QSPI0_SS_PA3_Msk)) | QSPI0_SS_PA3            /*!< Set PA3 function to QSPI0_SS         */
+#define SET_QSPI0_SS_PC3()       SYS->GPC_MFPL = (SYS->GPC_MFPL & (~QSPI0_SS_PC3_Msk)) | QSPI0_SS_PC3            /*!< Set PC3 function to QSPI0_SS         */
+#define SET_QSPI0_SS_PH9()       SYS->GPH_MFPH = (SYS->GPH_MFPH & (~QSPI0_SS_PH9_Msk)) | QSPI0_SS_PH9            /*!< Set PH9 function to QSPI0_SS         */
+#define SET_SC0_CLK_PA0()        SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC0_CLK_PA0_Msk)) | SC0_CLK_PA0              /*!< Set PA0 function to SC0_CLK          */
+#define SET_SC0_CLK_PF6()        SYS->GPF_MFPL = (SYS->GPF_MFPL & (~SC0_CLK_PF6_Msk)) | SC0_CLK_PF6              /*!< Set PF6 function to SC0_CLK          */
+#define SET_SC0_CLK_PE2()        SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SC0_CLK_PE2_Msk)) | SC0_CLK_PE2              /*!< Set PE2 function to SC0_CLK          */
+#define SET_SC0_CLK_PB5()        SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SC0_CLK_PB5_Msk)) | SC0_CLK_PB5              /*!< Set PB5 function to SC0_CLK          */
+#define SET_SC0_DAT_PF7()        SYS->GPF_MFPL = (SYS->GPF_MFPL & (~SC0_DAT_PF7_Msk)) | SC0_DAT_PF7              /*!< Set PF7 function to SC0_DAT          */
+#define SET_SC0_DAT_PA1()        SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC0_DAT_PA1_Msk)) | SC0_DAT_PA1              /*!< Set PA1 function to SC0_DAT          */
+#define SET_SC0_DAT_PE3()        SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SC0_DAT_PE3_Msk)) | SC0_DAT_PE3              /*!< Set PE3 function to SC0_DAT          */
+#define SET_SC0_DAT_PB4()        SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SC0_DAT_PB4_Msk)) | SC0_DAT_PB4              /*!< Set PB4 function to SC0_DAT          */
+#define SET_SC0_PWR_PF9()        SYS->GPF_MFPH = (SYS->GPF_MFPH & (~SC0_PWR_PF9_Msk)) | SC0_PWR_PF9              /*!< Set PF9 function to SC0_PWR          */
+#define SET_SC0_PWR_PE5()        SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SC0_PWR_PE5_Msk)) | SC0_PWR_PE5              /*!< Set PE5 function to SC0_PWR          */
+#define SET_SC0_PWR_PA3()        SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC0_PWR_PA3_Msk)) | SC0_PWR_PA3              /*!< Set PA3 function to SC0_PWR          */
+#define SET_SC0_PWR_PB2()        SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SC0_PWR_PB2_Msk)) | SC0_PWR_PB2              /*!< Set PB2 function to SC0_PWR          */
+#define SET_SC0_RST_PE4()        SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SC0_RST_PE4_Msk)) | SC0_RST_PE4              /*!< Set PE4 function to SC0_RST          */
+#define SET_SC0_RST_PF8()        SYS->GPF_MFPH = (SYS->GPF_MFPH & (~SC0_RST_PF8_Msk)) | SC0_RST_PF8              /*!< Set PF8 function to SC0_RST          */
+#define SET_SC0_RST_PA2()        SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC0_RST_PA2_Msk)) | SC0_RST_PA2              /*!< Set PA2 function to SC0_RST          */
+#define SET_SC0_RST_PB3()        SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SC0_RST_PB3_Msk)) | SC0_RST_PB3              /*!< Set PB3 function to SC0_RST          */
+#define SET_SC0_nCD_PC12()       SYS->GPC_MFPH = (SYS->GPC_MFPH & (~SC0_nCD_PC12_Msk)) | SC0_nCD_PC12            /*!< Set PC12 function to SC0_nCD         */
+#define SET_SC0_nCD_PA4()        SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC0_nCD_PA4_Msk)) | SC0_nCD_PA4              /*!< Set PA4 function to SC0_nCD          */
+#define SET_SC0_nCD_PF10()       SYS->GPF_MFPH = (SYS->GPF_MFPH & (~SC0_nCD_PF10_Msk)) | SC0_nCD_PF10            /*!< Set PF10 function to SC0_nCD         */
+#define SET_SC0_nCD_PE6()        SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SC0_nCD_PE6_Msk)) | SC0_nCD_PE6              /*!< Set PE6 function to SC0_nCD          */
+#define SET_SC1_CLK_PB12()       SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SC1_CLK_PB12_Msk)) | SC1_CLK_PB12            /*!< Set PB12 function to SC1_CLK         */
+#define SET_SC1_CLK_PC0()        SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SC1_CLK_PC0_Msk)) | SC1_CLK_PC0              /*!< Set PC0 function to SC1_CLK          */
+#define SET_SC1_CLK_PD4()        SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC1_CLK_PD4_Msk)) | SC1_CLK_PD4              /*!< Set PD4 function to SC1_CLK          */
+#define SET_SC1_DAT_PD5()        SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC1_DAT_PD5_Msk)) | SC1_DAT_PD5              /*!< Set PD5 function to SC1_DAT          */
+#define SET_SC1_DAT_PC1()        SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SC1_DAT_PC1_Msk)) | SC1_DAT_PC1              /*!< Set PC1 function to SC1_DAT          */
+#define SET_SC1_DAT_PB13()       SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SC1_DAT_PB13_Msk)) | SC1_DAT_PB13            /*!< Set PB13 function to SC1_DAT         */
+#define SET_SC1_PWR_PD7()        SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC1_PWR_PD7_Msk)) | SC1_PWR_PD7              /*!< Set PD7 function to SC1_PWR          */
+#define SET_SC1_PWR_PC3()        SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SC1_PWR_PC3_Msk)) | SC1_PWR_PC3              /*!< Set PC3 function to SC1_PWR          */
+#define SET_SC1_PWR_PB15()       SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SC1_PWR_PB15_Msk)) | SC1_PWR_PB15            /*!< Set PB15 function to SC1_PWR         */
+#define SET_SC1_RST_PD6()        SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC1_RST_PD6_Msk)) | SC1_RST_PD6              /*!< Set PD6 function to SC1_RST          */
+#define SET_SC1_RST_PB14()       SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SC1_RST_PB14_Msk)) | SC1_RST_PB14            /*!< Set PB14 function to SC1_RST         */
+#define SET_SC1_RST_PC2()        SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SC1_RST_PC2_Msk)) | SC1_RST_PC2              /*!< Set PC2 function to SC1_RST          */
+#define SET_SC1_nCD_PD14()       SYS->GPD_MFPH = (SYS->GPD_MFPH & (~SC1_nCD_PD14_Msk)) | SC1_nCD_PD14            /*!< Set PD14 function to SC1_nCD         */
+#define SET_SC1_nCD_PC4()        SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SC1_nCD_PC4_Msk)) | SC1_nCD_PC4              /*!< Set PC4 function to SC1_nCD          */
+#define SET_SC1_nCD_PD3()        SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC1_nCD_PD3_Msk)) | SC1_nCD_PD3              /*!< Set PD3 function to SC1_nCD          */
+#define SET_SC2_CLK_PA6()        SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC2_CLK_PA6_Msk)) | SC2_CLK_PA6              /*!< Set PA6 function to SC2_CLK          */
+#define SET_SC2_CLK_PD0()        SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC2_CLK_PD0_Msk)) | SC2_CLK_PD0              /*!< Set PD0 function to SC2_CLK          */
+#define SET_SC2_CLK_PA15()       SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_CLK_PA15_Msk)) | SC2_CLK_PA15            /*!< Set PA15 function to SC2_CLK         */
+#define SET_SC2_CLK_PA8()        SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_CLK_PA8_Msk)) | SC2_CLK_PA8              /*!< Set PA8 function to SC2_CLK          */
+#define SET_SC2_CLK_PE0()        SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SC2_CLK_PE0_Msk)) | SC2_CLK_PE0              /*!< Set PE0 function to SC2_CLK          */
+#define SET_SC2_DAT_PA9()        SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_DAT_PA9_Msk)) | SC2_DAT_PA9              /*!< Set PA9 function to SC2_DAT          */
+#define SET_SC2_DAT_PD1()        SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC2_DAT_PD1_Msk)) | SC2_DAT_PD1              /*!< Set PD1 function to SC2_DAT          */
+#define SET_SC2_DAT_PA7()        SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC2_DAT_PA7_Msk)) | SC2_DAT_PA7              /*!< Set PA7 function to SC2_DAT          */
+#define SET_SC2_DAT_PA14()       SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_DAT_PA14_Msk)) | SC2_DAT_PA14            /*!< Set PA14 function to SC2_DAT         */
+#define SET_SC2_DAT_PE1()        SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SC2_DAT_PE1_Msk)) | SC2_DAT_PE1              /*!< Set PE1 function to SC2_DAT          */
+#define SET_SC2_PWR_PC7()        SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SC2_PWR_PC7_Msk)) | SC2_PWR_PC7              /*!< Set PC7 function to SC2_PWR          */
+#define SET_SC2_PWR_PH8()        SYS->GPH_MFPH = (SYS->GPH_MFPH & (~SC2_PWR_PH8_Msk)) | SC2_PWR_PH8              /*!< Set PH8 function to SC2_PWR          */
+#define SET_SC2_PWR_PD3()        SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC2_PWR_PD3_Msk)) | SC2_PWR_PD3              /*!< Set PD3 function to SC2_PWR          */
+#define SET_SC2_PWR_PA11()       SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_PWR_PA11_Msk)) | SC2_PWR_PA11            /*!< Set PA11 function to SC2_PWR         */
+#define SET_SC2_PWR_PA12()       SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_PWR_PA12_Msk)) | SC2_PWR_PA12            /*!< Set PA12 function to SC2_PWR         */
+#define SET_SC2_RST_PD2()        SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC2_RST_PD2_Msk)) | SC2_RST_PD2              /*!< Set PD2 function to SC2_RST          */
+#define SET_SC2_RST_PC6()        SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SC2_RST_PC6_Msk)) | SC2_RST_PC6              /*!< Set PC6 function to SC2_RST          */
+#define SET_SC2_RST_PH9()        SYS->GPH_MFPH = (SYS->GPH_MFPH & (~SC2_RST_PH9_Msk)) | SC2_RST_PH9              /*!< Set PH9 function to SC2_RST          */
+#define SET_SC2_RST_PA13()       SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_RST_PA13_Msk)) | SC2_RST_PA13            /*!< Set PA13 function to SC2_RST         */
+#define SET_SC2_RST_PA10()       SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_RST_PA10_Msk)) | SC2_RST_PA10            /*!< Set PA10 function to SC2_RST         */
+#define SET_SC2_nCD_PA5()        SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC2_nCD_PA5_Msk)) | SC2_nCD_PA5              /*!< Set PA5 function to SC2_nCD          */
+#define SET_SC2_nCD_PH10()       SYS->GPH_MFPH = (SYS->GPH_MFPH & (~SC2_nCD_PH10_Msk)) | SC2_nCD_PH10            /*!< Set PH10 function to SC2_nCD         */
+#define SET_SC2_nCD_PD13()       SYS->GPD_MFPH = (SYS->GPD_MFPH & (~SC2_nCD_PD13_Msk)) | SC2_nCD_PD13            /*!< Set PD13 function to SC2_nCD         */
+#define SET_SC2_nCD_PC13()       SYS->GPC_MFPH = (SYS->GPC_MFPH & (~SC2_nCD_PC13_Msk)) | SC2_nCD_PC13            /*!< Set PC13 function to SC2_nCD         */
+#define SET_SD0_CLK_PB1()        SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SD0_CLK_PB1_Msk)) | SD0_CLK_PB1              /*!< Set PB1 function to SD0_CLK          */
+#define SET_SD0_CLK_PE6()        SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SD0_CLK_PE6_Msk)) | SD0_CLK_PE6              /*!< Set PE6 function to SD0_CLK          */
+#define SET_SD0_CMD_PE7()        SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SD0_CMD_PE7_Msk)) | SD0_CMD_PE7              /*!< Set PE7 function to SD0_CMD          */
+#define SET_SD0_CMD_PB0()        SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SD0_CMD_PB0_Msk)) | SD0_CMD_PB0              /*!< Set PB0 function to SD0_CMD          */
+#define SET_SD0_DAT0_PE2()       SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SD0_DAT0_PE2_Msk)) | SD0_DAT0_PE2            /*!< Set PE2 function to SD0_DAT0         */
+#define SET_SD0_DAT0_PB2()       SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SD0_DAT0_PB2_Msk)) | SD0_DAT0_PB2            /*!< Set PB2 function to SD0_DAT0         */
+#define SET_SD0_DAT1_PE3()       SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SD0_DAT1_PE3_Msk)) | SD0_DAT1_PE3            /*!< Set PE3 function to SD0_DAT1         */
+#define SET_SD0_DAT1_PB3()       SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SD0_DAT1_PB3_Msk)) | SD0_DAT1_PB3            /*!< Set PB3 function to SD0_DAT1         */
+#define SET_SD0_DAT2_PE4()       SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SD0_DAT2_PE4_Msk)) | SD0_DAT2_PE4            /*!< Set PE4 function to SD0_DAT2         */
+#define SET_SD0_DAT2_PB4()       SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SD0_DAT2_PB4_Msk)) | SD0_DAT2_PB4            /*!< Set PB4 function to SD0_DAT2         */
+#define SET_SD0_DAT3_PE5()       SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SD0_DAT3_PE5_Msk)) | SD0_DAT3_PE5            /*!< Set PE5 function to SD0_DAT3         */
+#define SET_SD0_DAT3_PB5()       SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SD0_DAT3_PB5_Msk)) | SD0_DAT3_PB5            /*!< Set PB5 function to SD0_DAT3         */
+#define SET_SD0_nCD_PD13()       SYS->GPD_MFPH = (SYS->GPD_MFPH & (~SD0_nCD_PD13_Msk)) | SD0_nCD_PD13            /*!< Set PD13 function to SD0_nCD         */
+#define SET_SD0_nCD_PB12()       SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SD0_nCD_PB12_Msk)) | SD0_nCD_PB12            /*!< Set PB12 function to SD0_nCD         */
+#define SET_SEG15_PC5()          SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SEG15_PC5_Msk)) | SEG15_PC5                  /*!< Set PC5 function to SEG15            */
+#define SET_SEG16_PC4()          SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SEG16_PC4_Msk)) | SEG16_PC4                  /*!< Set PC4 function to SEG16            */
+#define SET_SPI0_CLK_PD2()       SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI0_CLK_PD2_Msk)) | SPI0_CLK_PD2            /*!< Set PD2 function to SPI0_CLK         */
+#define SET_SPI0_CLK_PB14()      SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI0_CLK_PB14_Msk)) | SPI0_CLK_PB14          /*!< Set PB14 function to SPI0_CLK        */
+#define SET_SPI0_CLK_PF8()       SYS->GPF_MFPH = (SYS->GPF_MFPH & (~SPI0_CLK_PF8_Msk)) | SPI0_CLK_PF8            /*!< Set PF8 function to SPI0_CLK         */
+#define SET_SPI0_CLK_PA2()       SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI0_CLK_PA2_Msk)) | SPI0_CLK_PA2            /*!< Set PA2 function to SPI0_CLK         */
+#define SET_SPI0_I2SMCLK_PB11()  SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI0_I2SMCLK_PB11_Msk)) | SPI0_I2SMCLK_PB11  /*!< Set PB11 function to SPI0_I2SMCLK    */
+#define SET_SPI0_I2SMCLK_PB0()   SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI0_I2SMCLK_PB0_Msk)) | SPI0_I2SMCLK_PB0    /*!< Set PB0 function to SPI0_I2SMCLK     */
+#define SET_SPI0_I2SMCLK_PF10()  SYS->GPF_MFPH = (SYS->GPF_MFPH & (~SPI0_I2SMCLK_PF10_Msk)) | SPI0_I2SMCLK_PF10  /*!< Set PF10 function to SPI0_I2SMCLK    */
+#define SET_SPI0_I2SMCLK_PA4()   SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI0_I2SMCLK_PA4_Msk)) | SPI0_I2SMCLK_PA4    /*!< Set PA4 function to SPI0_I2SMCLK     */
+#define SET_SPI0_I2SMCLK_PD14()  SYS->GPD_MFPH = (SYS->GPD_MFPH & (~SPI0_I2SMCLK_PD14_Msk)) | SPI0_I2SMCLK_PD14  /*!< Set PD14 function to SPI0_I2SMCLK    */
+#define SET_SPI0_I2SMCLK_PD13()  SYS->GPD_MFPH = (SYS->GPD_MFPH & (~SPI0_I2SMCLK_PD13_Msk)) | SPI0_I2SMCLK_PD13  /*!< Set PD13 function to SPI0_I2SMCLK    */
+#define SET_SPI0_MISO_PA1()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI0_MISO_PA1_Msk)) | SPI0_MISO_PA1          /*!< Set PA1 function to SPI0_MISO        */
+#define SET_SPI0_MISO_PF7()      SYS->GPF_MFPL = (SYS->GPF_MFPL & (~SPI0_MISO_PF7_Msk)) | SPI0_MISO_PF7          /*!< Set PF7 function to SPI0_MISO        */
+#define SET_SPI0_MISO_PD1()      SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI0_MISO_PD1_Msk)) | SPI0_MISO_PD1          /*!< Set PD1 function to SPI0_MISO        */
+#define SET_SPI0_MISO_PB13()     SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI0_MISO_PB13_Msk)) | SPI0_MISO_PB13        /*!< Set PB13 function to SPI0_MISO       */
+#define SET_SPI0_MOSI_PF6()      SYS->GPF_MFPL = (SYS->GPF_MFPL & (~SPI0_MOSI_PF6_Msk)) | SPI0_MOSI_PF6          /*!< Set PF6 function to SPI0_MOSI        */
+#define SET_SPI0_MOSI_PD0()      SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI0_MOSI_PD0_Msk)) | SPI0_MOSI_PD0          /*!< Set PD0 function to SPI0_MOSI        */
+#define SET_SPI0_MOSI_PB12()     SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI0_MOSI_PB12_Msk)) | SPI0_MOSI_PB12        /*!< Set PB12 function to SPI0_MOSI       */
+#define SET_SPI0_MOSI_PA0()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI0_MOSI_PA0_Msk)) | SPI0_MOSI_PA0          /*!< Set PA0 function to SPI0_MOSI        */
+#define SET_SPI0_SS_PF9()        SYS->GPF_MFPH = (SYS->GPF_MFPH & (~SPI0_SS_PF9_Msk)) | SPI0_SS_PF9              /*!< Set PF9 function to SPI0_SS          */
+#define SET_SPI0_SS_PA3()        SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI0_SS_PA3_Msk)) | SPI0_SS_PA3              /*!< Set PA3 function to SPI0_SS          */
+#define SET_SPI0_SS_PB15()       SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI0_SS_PB15_Msk)) | SPI0_SS_PB15            /*!< Set PB15 function to SPI0_SS         */
+#define SET_SPI0_SS_PD3()        SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI0_SS_PD3_Msk)) | SPI0_SS_PD3              /*!< Set PD3 function to SPI0_SS          */
+#define SET_SPI1_CLK_PD5()       SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI1_CLK_PD5_Msk)) | SPI1_CLK_PD5            /*!< Set PD5 function to SPI1_CLK         */
+#define SET_SPI1_CLK_PH6()       SYS->GPH_MFPL = (SYS->GPH_MFPL & (~SPI1_CLK_PH6_Msk)) | SPI1_CLK_PH6            /*!< Set PH6 function to SPI1_CLK         */
+#define SET_SPI1_CLK_PC1()       SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SPI1_CLK_PC1_Msk)) | SPI1_CLK_PC1            /*!< Set PC1 function to SPI1_CLK         */
+#define SET_SPI1_CLK_PB3()       SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI1_CLK_PB3_Msk)) | SPI1_CLK_PB3            /*!< Set PB3 function to SPI1_CLK         */
+#define SET_SPI1_CLK_PH8()       SYS->GPH_MFPH = (SYS->GPH_MFPH & (~SPI1_CLK_PH8_Msk)) | SPI1_CLK_PH8            /*!< Set PH8 function to SPI1_CLK         */
+#define SET_SPI1_CLK_PA7()       SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI1_CLK_PA7_Msk)) | SPI1_CLK_PA7            /*!< Set PA7 function to SPI1_CLK         */
+#define SET_SPI1_I2SMCLK_PC4()   SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SPI1_I2SMCLK_PC4_Msk)) | SPI1_I2SMCLK_PC4    /*!< Set PC4 function to SPI1_I2SMCLK     */
+#define SET_SPI1_I2SMCLK_PB1()   SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI1_I2SMCLK_PB1_Msk)) | SPI1_I2SMCLK_PB1    /*!< Set PB1 function to SPI1_I2SMCLK     */
+#define SET_SPI1_I2SMCLK_PA5()   SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI1_I2SMCLK_PA5_Msk)) | SPI1_I2SMCLK_PA5    /*!< Set PA5 function to SPI1_I2SMCLK     */
+#define SET_SPI1_I2SMCLK_PD13()  SYS->GPD_MFPH = (SYS->GPD_MFPH & (~SPI1_I2SMCLK_PD13_Msk)) | SPI1_I2SMCLK_PD13  /*!< Set PD13 function to SPI1_I2SMCLK    */
+#define SET_SPI1_I2SMCLK_PH10()  SYS->GPH_MFPH = (SYS->GPH_MFPH & (~SPI1_I2SMCLK_PH10_Msk)) | SPI1_I2SMCLK_PH10  /*!< Set PH10 function to SPI1_I2SMCLK    */
+#define SET_SPI1_MISO_PC3()      SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SPI1_MISO_PC3_Msk)) | SPI1_MISO_PC3          /*!< Set PC3 function to SPI1_MISO        */
+#define SET_SPI1_MISO_PC7()      SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SPI1_MISO_PC7_Msk)) | SPI1_MISO_PC7          /*!< Set PC7 function to SPI1_MISO        */
+#define SET_SPI1_MISO_PH4()      SYS->GPH_MFPL = (SYS->GPH_MFPL & (~SPI1_MISO_PH4_Msk)) | SPI1_MISO_PH4          /*!< Set PH4 function to SPI1_MISO        */
+#define SET_SPI1_MISO_PB5()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI1_MISO_PB5_Msk)) | SPI1_MISO_PB5          /*!< Set PB5 function to SPI1_MISO        */
+#define SET_SPI1_MISO_PE1()      SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SPI1_MISO_PE1_Msk)) | SPI1_MISO_PE1          /*!< Set PE1 function to SPI1_MISO        */
+#define SET_SPI1_MISO_PD7()      SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI1_MISO_PD7_Msk)) | SPI1_MISO_PD7          /*!< Set PD7 function to SPI1_MISO        */
+#define SET_SPI1_MOSI_PE0()      SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SPI1_MOSI_PE0_Msk)) | SPI1_MOSI_PE0          /*!< Set PE0 function to SPI1_MOSI        */
+#define SET_SPI1_MOSI_PB4()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI1_MOSI_PB4_Msk)) | SPI1_MOSI_PB4          /*!< Set PB4 function to SPI1_MOSI        */
+#define SET_SPI1_MOSI_PC6()      SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SPI1_MOSI_PC6_Msk)) | SPI1_MOSI_PC6          /*!< Set PC6 function to SPI1_MOSI        */
+#define SET_SPI1_MOSI_PD6()      SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI1_MOSI_PD6_Msk)) | SPI1_MOSI_PD6          /*!< Set PD6 function to SPI1_MOSI        */
+#define SET_SPI1_MOSI_PH5()      SYS->GPH_MFPL = (SYS->GPH_MFPL & (~SPI1_MOSI_PH5_Msk)) | SPI1_MOSI_PH5          /*!< Set PH5 function to SPI1_MOSI        */
+#define SET_SPI1_MOSI_PC2()      SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SPI1_MOSI_PC2_Msk)) | SPI1_MOSI_PC2          /*!< Set PC2 function to SPI1_MOSI        */
+#define SET_SPI1_SS_PH7()        SYS->GPH_MFPL = (SYS->GPH_MFPL & (~SPI1_SS_PH7_Msk)) | SPI1_SS_PH7              /*!< Set PH7 function to SPI1_SS          */
+#define SET_SPI1_SS_PB2()        SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI1_SS_PB2_Msk)) | SPI1_SS_PB2              /*!< Set PB2 function to SPI1_SS          */
+#define SET_SPI1_SS_PA6()        SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI1_SS_PA6_Msk)) | SPI1_SS_PA6              /*!< Set PA6 function to SPI1_SS          */
+#define SET_SPI1_SS_PD4()        SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI1_SS_PD4_Msk)) | SPI1_SS_PD4              /*!< Set PD4 function to SPI1_SS          */
+#define SET_SPI1_SS_PH9()        SYS->GPH_MFPH = (SYS->GPH_MFPH & (~SPI1_SS_PH9_Msk)) | SPI1_SS_PH9              /*!< Set PH9 function to SPI1_SS          */
+#define SET_SPI1_SS_PC0()        SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SPI1_SS_PC0_Msk)) | SPI1_SS_PC0              /*!< Set PC0 function to SPI1_SS          */
+#define SET_SPI2_CLK_PE8()       SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SPI2_CLK_PE8_Msk)) | SPI2_CLK_PE8            /*!< Set PE8 function to SPI2_CLK         */
+#define SET_SPI2_CLK_PA10()      SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_CLK_PA10_Msk)) | SPI2_CLK_PA10          /*!< Set PA10 function to SPI2_CLK        */
+#define SET_SPI2_CLK_PA13()      SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_CLK_PA13_Msk)) | SPI2_CLK_PA13          /*!< Set PA13 function to SPI2_CLK        */
+#define SET_SPI2_CLK_PG3()       SYS->GPG_MFPL = (SYS->GPG_MFPL & (~SPI2_CLK_PG3_Msk)) | SPI2_CLK_PG3            /*!< Set PG3 function to SPI2_CLK         */
+#define SET_SPI2_I2SMCLK_PE12()  SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SPI2_I2SMCLK_PE12_Msk)) | SPI2_I2SMCLK_PE12  /*!< Set PE12 function to SPI2_I2SMCLK    */
+#define SET_SPI2_I2SMCLK_PC13()  SYS->GPC_MFPH = (SYS->GPC_MFPH & (~SPI2_I2SMCLK_PC13_Msk)) | SPI2_I2SMCLK_PC13  /*!< Set PC13 function to SPI2_I2SMCLK    */
+#define SET_SPI2_I2SMCLK_PB0()   SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI2_I2SMCLK_PB0_Msk)) | SPI2_I2SMCLK_PB0    /*!< Set PB0 function to SPI2_I2SMCLK     */
+#define SET_SPI2_MISO_PE9()      SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SPI2_MISO_PE9_Msk)) | SPI2_MISO_PE9          /*!< Set PE9 function to SPI2_MISO        */
+#define SET_SPI2_MISO_PA9()      SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_MISO_PA9_Msk)) | SPI2_MISO_PA9          /*!< Set PA9 function to SPI2_MISO        */
+#define SET_SPI2_MISO_PA14()     SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_MISO_PA14_Msk)) | SPI2_MISO_PA14        /*!< Set PA14 function to SPI2_MISO       */
+#define SET_SPI2_MISO_PG4()      SYS->GPG_MFPL = (SYS->GPG_MFPL & (~SPI2_MISO_PG4_Msk)) | SPI2_MISO_PG4          /*!< Set PG4 function to SPI2_MISO        */
+#define SET_SPI2_MOSI_PF11()     SYS->GPF_MFPH = (SYS->GPF_MFPH & (~SPI2_MOSI_PF11_Msk)) | SPI2_MOSI_PF11        /*!< Set PF11 function to SPI2_MOSI       */
+#define SET_SPI2_MOSI_PA15()     SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_MOSI_PA15_Msk)) | SPI2_MOSI_PA15        /*!< Set PA15 function to SPI2_MOSI       */
+#define SET_SPI2_MOSI_PE10()     SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SPI2_MOSI_PE10_Msk)) | SPI2_MOSI_PE10        /*!< Set PE10 function to SPI2_MOSI       */
+#define SET_SPI2_MOSI_PA8()      SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_MOSI_PA8_Msk)) | SPI2_MOSI_PA8          /*!< Set PA8 function to SPI2_MOSI        */
+#define SET_SPI2_SS_PE11()       SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SPI2_SS_PE11_Msk)) | SPI2_SS_PE11            /*!< Set PE11 function to SPI2_SS         */
+#define SET_SPI2_SS_PG2()        SYS->GPG_MFPL = (SYS->GPG_MFPL & (~SPI2_SS_PG2_Msk)) | SPI2_SS_PG2              /*!< Set PG2 function to SPI2_SS          */
+#define SET_SPI2_SS_PA11()       SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_SS_PA11_Msk)) | SPI2_SS_PA11            /*!< Set PA11 function to SPI2_SS         */
+#define SET_SPI2_SS_PA12()       SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_SS_PA12_Msk)) | SPI2_SS_PA12            /*!< Set PA12 function to SPI2_SS         */
+#define SET_SPI3_CLK_PC10()      SYS->GPC_MFPH = (SYS->GPC_MFPH & (~SPI3_CLK_PC10_Msk)) | SPI3_CLK_PC10          /*!< Set PC10 function to SPI3_CLK        */
+#define SET_SPI3_CLK_PE4()       SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SPI3_CLK_PE4_Msk)) | SPI3_CLK_PE4            /*!< Set PE4 function to SPI3_CLK         */
+#define SET_SPI3_CLK_PB11()      SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI3_CLK_PB11_Msk)) | SPI3_CLK_PB11          /*!< Set PB11 function to SPI3_CLK        */
+#define SET_SPI3_I2SMCLK_PE6()   SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SPI3_I2SMCLK_PE6_Msk)) | SPI3_I2SMCLK_PE6    /*!< Set PE6 function to SPI3_I2SMCLK     */
+#define SET_SPI3_I2SMCLK_PF6()   SYS->GPF_MFPL = (SYS->GPF_MFPL & (~SPI3_I2SMCLK_PF6_Msk)) | SPI3_I2SMCLK_PF6    /*!< Set PF6 function to SPI3_I2SMCLK     */
+#define SET_SPI3_I2SMCLK_PB1()   SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI3_I2SMCLK_PB1_Msk)) | SPI3_I2SMCLK_PB1    /*!< Set PB1 function to SPI3_I2SMCLK     */
+#define SET_SPI3_I2SMCLK_PD14()  SYS->GPD_MFPH = (SYS->GPD_MFPH & (~SPI3_I2SMCLK_PD14_Msk)) | SPI3_I2SMCLK_PD14  /*!< Set PD14 function to SPI3_I2SMCLK    */
+#define SET_SPI3_MISO_PE3()      SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SPI3_MISO_PE3_Msk)) | SPI3_MISO_PE3          /*!< Set PE3 function to SPI3_MISO        */
+#define SET_SPI3_MISO_PC12()     SYS->GPC_MFPH = (SYS->GPC_MFPH & (~SPI3_MISO_PC12_Msk)) | SPI3_MISO_PC12        /*!< Set PC12 function to SPI3_MISO       */
+#define SET_SPI3_MISO_PB9()      SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI3_MISO_PB9_Msk)) | SPI3_MISO_PB9          /*!< Set PB9 function to SPI3_MISO        */
+#define SET_SPI3_MOSI_PC11()     SYS->GPC_MFPH = (SYS->GPC_MFPH & (~SPI3_MOSI_PC11_Msk)) | SPI3_MOSI_PC11        /*!< Set PC11 function to SPI3_MOSI       */
+#define SET_SPI3_MOSI_PE2()      SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SPI3_MOSI_PE2_Msk)) | SPI3_MOSI_PE2          /*!< Set PE2 function to SPI3_MOSI        */
+#define SET_SPI3_MOSI_PB8()      SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI3_MOSI_PB8_Msk)) | SPI3_MOSI_PB8          /*!< Set PB8 function to SPI3_MOSI        */
+#define SET_SPI3_SS_PE5()        SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SPI3_SS_PE5_Msk)) | SPI3_SS_PE5              /*!< Set PE5 function to SPI3_SS          */
+#define SET_SPI3_SS_PB10()       SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI3_SS_PB10_Msk)) | SPI3_SS_PB10            /*!< Set PB10 function to SPI3_SS         */
+#define SET_SPI3_SS_PC9()        SYS->GPC_MFPH = (SYS->GPC_MFPH & (~SPI3_SS_PC9_Msk)) | SPI3_SS_PC9              /*!< Set PC9 function to SPI3_SS          */
+#define SET_TAMPER0_PF6()        SYS->GPF_MFPL = (SYS->GPF_MFPL & (~TAMPER0_PF6_Msk)) | TAMPER0_PF6              /*!< Set PF6 function to TAMPER0          */
+#define SET_TAMPER1_PF7()        SYS->GPF_MFPL = (SYS->GPF_MFPL & (~TAMPER1_PF7_Msk)) | TAMPER1_PF7              /*!< Set PF7 function to TAMPER1          */
+#define SET_TAMPER2_PF8()        SYS->GPF_MFPH = (SYS->GPF_MFPH & (~TAMPER2_PF8_Msk)) | TAMPER2_PF8              /*!< Set PF8 function to TAMPER2          */
+#define SET_TAMPER3_PF9()        SYS->GPF_MFPH = (SYS->GPF_MFPH & (~TAMPER3_PF9_Msk)) | TAMPER3_PF9              /*!< Set PF9 function to TAMPER3          */
+#define SET_TAMPER4_PF10()       SYS->GPF_MFPH = (SYS->GPF_MFPH & (~TAMPER4_PF10_Msk)) | TAMPER4_PF10            /*!< Set PF10 function to TAMPER4         */
+#define SET_TAMPER5_PF11()       SYS->GPF_MFPH = (SYS->GPF_MFPH & (~TAMPER5_PF11_Msk)) | TAMPER5_PF11            /*!< Set PF11 function to TAMPER5         */
+#define SET_TM0_PG2()            SYS->GPG_MFPL = (SYS->GPG_MFPL & (~TM0_PG2_Msk)) | TM0_PG2                      /*!< Set PG2 function to TM0              */
+#define SET_TM0_PB5()            SYS->GPB_MFPL = (SYS->GPB_MFPL & (~TM0_PB5_Msk)) | TM0_PB5                      /*!< Set PB5 function to TM0              */
+#define SET_TM0_PC7()            SYS->GPC_MFPL = (SYS->GPC_MFPL & (~TM0_PC7_Msk)) | TM0_PC7                      /*!< Set PC7 function to TM0              */
+#define SET_TM0_EXT_PB15()       SYS->GPB_MFPH = (SYS->GPB_MFPH & (~TM0_EXT_PB15_Msk)) | TM0_EXT_PB15            /*!< Set PB15 function to TM0_EXT         */
+#define SET_TM0_EXT_PA11()       SYS->GPA_MFPH = (SYS->GPA_MFPH & (~TM0_EXT_PA11_Msk)) | TM0_EXT_PA11            /*!< Set PA11 function to TM0_EXT         */
+#define SET_TM1_PC6()            SYS->GPC_MFPL = (SYS->GPC_MFPL & (~TM1_PC6_Msk)) | TM1_PC6                      /*!< Set PC6 function to TM1              */
+#define SET_TM1_PB4()            SYS->GPB_MFPL = (SYS->GPB_MFPL & (~TM1_PB4_Msk)) | TM1_PB4                      /*!< Set PB4 function to TM1              */
+#define SET_TM1_PG3()            SYS->GPG_MFPL = (SYS->GPG_MFPL & (~TM1_PG3_Msk)) | TM1_PG3                      /*!< Set PG3 function to TM1              */
+#define SET_TM1_EXT_PB14()       SYS->GPB_MFPH = (SYS->GPB_MFPH & (~TM1_EXT_PB14_Msk)) | TM1_EXT_PB14            /*!< Set PB14 function to TM1_EXT         */
+#define SET_TM1_EXT_PA10()       SYS->GPA_MFPH = (SYS->GPA_MFPH & (~TM1_EXT_PA10_Msk)) | TM1_EXT_PA10            /*!< Set PA10 function to TM1_EXT         */
+#define SET_TM2_PB3()            SYS->GPB_MFPL = (SYS->GPB_MFPL & (~TM2_PB3_Msk)) | TM2_PB3                      /*!< Set PB3 function to TM2              */
+#define SET_TM2_PA7()            SYS->GPA_MFPL = (SYS->GPA_MFPL & (~TM2_PA7_Msk)) | TM2_PA7                      /*!< Set PA7 function to TM2              */
+#define SET_TM2_PD0()            SYS->GPD_MFPL = (SYS->GPD_MFPL & (~TM2_PD0_Msk)) | TM2_PD0                      /*!< Set PD0 function to TM2              */
+#define SET_TM2_PG4()            SYS->GPG_MFPL = (SYS->GPG_MFPL & (~TM2_PG4_Msk)) | TM2_PG4                      /*!< Set PG4 function to TM2              */
+#define SET_TM2_EXT_PB13()       SYS->GPB_MFPH = (SYS->GPB_MFPH & (~TM2_EXT_PB13_Msk)) | TM2_EXT_PB13            /*!< Set PB13 function to TM2_EXT         */
+#define SET_TM2_EXT_PA9()        SYS->GPA_MFPH = (SYS->GPA_MFPH & (~TM2_EXT_PA9_Msk)) | TM2_EXT_PA9              /*!< Set PA9 function to TM2_EXT          */
+#define SET_TM3_PB2()            SYS->GPB_MFPL = (SYS->GPB_MFPL & (~TM3_PB2_Msk)) | TM3_PB2                      /*!< Set PB2 function to TM3              */
+#define SET_TM3_PA6()            SYS->GPA_MFPL = (SYS->GPA_MFPL & (~TM3_PA6_Msk)) | TM3_PA6                      /*!< Set PA6 function to TM3              */
+#define SET_TM3_PF11()           SYS->GPF_MFPH = (SYS->GPF_MFPH & (~TM3_PF11_Msk)) | TM3_PF11                    /*!< Set PF11 function to TM3             */
+#define SET_TM3_EXT_PB12()       SYS->GPB_MFPH = (SYS->GPB_MFPH & (~TM3_EXT_PB12_Msk)) | TM3_EXT_PB12            /*!< Set PB12 function to TM3_EXT         */
+#define SET_TM3_EXT_PA8()        SYS->GPA_MFPH = (SYS->GPA_MFPH & (~TM3_EXT_PA8_Msk)) | TM3_EXT_PA8              /*!< Set PA8 function to TM3_EXT          */
+#define SET_TM4_PA7()            SYS->GPA_MFPL = (SYS->GPA_MFPL & (~TM4_PA7_Msk)) | TM4_PA7                      /*!< Set PA7 function to TM4              */
+#define SET_TM4_PG4()            SYS->GPG_MFPL = (SYS->GPG_MFPL & (~TM4_PG4_Msk)) | TM4_PG4                      /*!< Set PG4 function to TM4              */
+#define SET_TM4_PB3()            SYS->GPB_MFPL = (SYS->GPB_MFPL & (~TM4_PB3_Msk)) | TM4_PB3                      /*!< Set PB3 function to TM4              */
+#define SET_TM4_EXT_PB13()       SYS->GPB_MFPH = (SYS->GPB_MFPH & (~TM4_EXT_PB13_Msk)) | TM4_EXT_PB13            /*!< Set PB13 function to TM4_EXT         */
+#define SET_TM4_EXT_PA9()        SYS->GPA_MFPH = (SYS->GPA_MFPH & (~TM4_EXT_PA9_Msk)) | TM4_EXT_PA9              /*!< Set PA9 function to TM4_EXT          */
+#define SET_TM5_PF11()           SYS->GPF_MFPH = (SYS->GPF_MFPH & (~TM5_PF11_Msk)) | TM5_PF11                    /*!< Set PF11 function to TM5             */
+#define SET_TM5_PB2()            SYS->GPB_MFPL = (SYS->GPB_MFPL & (~TM5_PB2_Msk)) | TM5_PB2                      /*!< Set PB2 function to TM5              */
+#define SET_TM5_PA6()            SYS->GPA_MFPL = (SYS->GPA_MFPL & (~TM5_PA6_Msk)) | TM5_PA6                      /*!< Set PA6 function to TM5              */
+#define SET_TM5_EXT_PA8()        SYS->GPA_MFPH = (SYS->GPA_MFPH & (~TM5_EXT_PA8_Msk)) | TM5_EXT_PA8              /*!< Set PA8 function to TM5_EXT          */
+#define SET_TM5_EXT_PB12()       SYS->GPB_MFPH = (SYS->GPB_MFPH & (~TM5_EXT_PB12_Msk)) | TM5_EXT_PB12            /*!< Set PB12 function to TM5_EXT         */
+#define SET_TRACE_CLK_PE12()     SYS->GPE_MFPH = (SYS->GPE_MFPH & (~TRACE_CLK_PE12_Msk)) | TRACE_CLK_PE12        /*!< Set PE12 function to TRACE_CLK       */
+#define SET_TRACE_DATA0_PE11()   SYS->GPE_MFPH = (SYS->GPE_MFPH & (~TRACE_DATA0_PE11_Msk)) | TRACE_DATA0_PE11    /*!< Set PE11 function to TRACE_DATA0     */
+#define SET_TRACE_DATA1_PE10()   SYS->GPE_MFPH = (SYS->GPE_MFPH & (~TRACE_DATA1_PE10_Msk)) | TRACE_DATA1_PE10    /*!< Set PE10 function to TRACE_DATA1     */
+#define SET_TRACE_DATA2_PE9()    SYS->GPE_MFPH = (SYS->GPE_MFPH & (~TRACE_DATA2_PE9_Msk)) | TRACE_DATA2_PE9      /*!< Set PE9 function to TRACE_DATA2      */
+#define SET_TRACE_DATA3_PE8()    SYS->GPE_MFPH = (SYS->GPE_MFPH & (~TRACE_DATA3_PE8_Msk)) | TRACE_DATA3_PE8      /*!< Set PE8 function to TRACE_DATA3      */
+#define SET_UART0_RXD_PA15()     SYS->GPA_MFPH = (SYS->GPA_MFPH & (~UART0_RXD_PA15_Msk)) | UART0_RXD_PA15        /*!< Set PA15 function to UART0_RXD       */
+#define SET_UART0_RXD_PD2()      SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART0_RXD_PD2_Msk)) | UART0_RXD_PD2          /*!< Set PD2 function to UART0_RXD        */
+#define SET_UART0_RXD_PA4()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_RXD_PA4_Msk)) | UART0_RXD_PA4          /*!< Set PA4 function to UART0_RXD        */
+#define SET_UART0_RXD_PB12()     SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_RXD_PB12_Msk)) | UART0_RXD_PB12        /*!< Set PB12 function to UART0_RXD       */
+#define SET_UART0_RXD_PA0()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_RXD_PA0_Msk)) | UART0_RXD_PA0          /*!< Set PA0 function to UART0_RXD        */
+#define SET_UART0_RXD_PF1()      SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART0_RXD_PF1_Msk)) | UART0_RXD_PF1          /*!< Set PF1 function to UART0_RXD        */
+#define SET_UART0_RXD_PC11()     SYS->GPC_MFPH = (SYS->GPC_MFPH & (~UART0_RXD_PC11_Msk)) | UART0_RXD_PC11        /*!< Set PC11 function to UART0_RXD       */
+#define SET_UART0_RXD_PB8()      SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_RXD_PB8_Msk)) | UART0_RXD_PB8          /*!< Set PB8 function to UART0_RXD        */
+#define SET_UART0_RXD_PH11()     SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART0_RXD_PH11_Msk)) | UART0_RXD_PH11        /*!< Set PH11 function to UART0_RXD       */
+#define SET_UART0_RXD_PA6()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_RXD_PA6_Msk)) | UART0_RXD_PA6          /*!< Set PA6 function to UART0_RXD        */
+#define SET_UART0_RXD_PF2()      SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART0_RXD_PF2_Msk)) | UART0_RXD_PF2          /*!< Set PF2 function to UART0_RXD        */
+#define SET_UART0_TXD_PA5()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_TXD_PA5_Msk)) | UART0_TXD_PA5          /*!< Set PA5 function to UART0_TXD        */
+#define SET_UART0_TXD_PA14()     SYS->GPA_MFPH = (SYS->GPA_MFPH & (~UART0_TXD_PA14_Msk)) | UART0_TXD_PA14        /*!< Set PA14 function to UART0_TXD       */
+#define SET_UART0_TXD_PF3()      SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART0_TXD_PF3_Msk)) | UART0_TXD_PF3          /*!< Set PF3 function to UART0_TXD        */
+#define SET_UART0_TXD_PA1()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_TXD_PA1_Msk)) | UART0_TXD_PA1          /*!< Set PA1 function to UART0_TXD        */
+#define SET_UART0_TXD_PH10()     SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART0_TXD_PH10_Msk)) | UART0_TXD_PH10        /*!< Set PH10 function to UART0_TXD       */
+#define SET_UART0_TXD_PD3()      SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART0_TXD_PD3_Msk)) | UART0_TXD_PD3          /*!< Set PD3 function to UART0_TXD        */
+#define SET_UART0_TXD_PB9()      SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_TXD_PB9_Msk)) | UART0_TXD_PB9          /*!< Set PB9 function to UART0_TXD        */
+#define SET_UART0_TXD_PB13()     SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_TXD_PB13_Msk)) | UART0_TXD_PB13        /*!< Set PB13 function to UART0_TXD       */
+#define SET_UART0_TXD_PA7()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_TXD_PA7_Msk)) | UART0_TXD_PA7          /*!< Set PA7 function to UART0_TXD        */
+#define SET_UART0_TXD_PF0()      SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART0_TXD_PF0_Msk)) | UART0_TXD_PF0          /*!< Set PF0 function to UART0_TXD        */
+#define SET_UART0_TXD_PC12()     SYS->GPC_MFPH = (SYS->GPC_MFPH & (~UART0_TXD_PC12_Msk)) | UART0_TXD_PC12        /*!< Set PC12 function to UART0_TXD       */
+#define SET_UART0_nCTS_PB15()    SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_nCTS_PB15_Msk)) | UART0_nCTS_PB15      /*!< Set PB15 function to UART0_nCTS      */
+#define SET_UART0_nCTS_PB11()    SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_nCTS_PB11_Msk)) | UART0_nCTS_PB11      /*!< Set PB11 function to UART0_nCTS      */
+#define SET_UART0_nCTS_PC7()     SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART0_nCTS_PC7_Msk)) | UART0_nCTS_PC7        /*!< Set PC7 function to UART0_nCTS       */
+#define SET_UART0_nCTS_PA5()     SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_nCTS_PA5_Msk)) | UART0_nCTS_PA5        /*!< Set PA5 function to UART0_nCTS       */
+#define SET_UART0_nRTS_PC6()     SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART0_nRTS_PC6_Msk)) | UART0_nRTS_PC6        /*!< Set PC6 function to UART0_nRTS       */
+#define SET_UART0_nRTS_PB14()    SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_nRTS_PB14_Msk)) | UART0_nRTS_PB14      /*!< Set PB14 function to UART0_nRTS      */
+#define SET_UART0_nRTS_PB10()    SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_nRTS_PB10_Msk)) | UART0_nRTS_PB10      /*!< Set PB10 function to UART0_nRTS      */
+#define SET_UART0_nRTS_PA4()     SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_nRTS_PA4_Msk)) | UART0_nRTS_PA4        /*!< Set PA4 function to UART0_nRTS       */
+#define SET_UART1_RXD_PA8()      SYS->GPA_MFPH = (SYS->GPA_MFPH & (~UART1_RXD_PA8_Msk)) | UART1_RXD_PA8          /*!< Set PA8 function to UART1_RXD        */
+#define SET_UART1_RXD_PB6()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART1_RXD_PB6_Msk)) | UART1_RXD_PB6          /*!< Set PB6 function to UART1_RXD        */
+#define SET_UART1_RXD_PC8()      SYS->GPC_MFPH = (SYS->GPC_MFPH & (~UART1_RXD_PC8_Msk)) | UART1_RXD_PC8          /*!< Set PC8 function to UART1_RXD        */
+#define SET_UART1_RXD_PA2()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART1_RXD_PA2_Msk)) | UART1_RXD_PA2          /*!< Set PA2 function to UART1_RXD        */
+#define SET_UART1_RXD_PH9()      SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART1_RXD_PH9_Msk)) | UART1_RXD_PH9          /*!< Set PH9 function to UART1_RXD        */
+#define SET_UART1_RXD_PD10()     SYS->GPD_MFPH = (SYS->GPD_MFPH & (~UART1_RXD_PD10_Msk)) | UART1_RXD_PD10        /*!< Set PD10 function to UART1_RXD       */
+#define SET_UART1_RXD_PB2()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART1_RXD_PB2_Msk)) | UART1_RXD_PB2          /*!< Set PB2 function to UART1_RXD        */
+#define SET_UART1_RXD_PD6()      SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART1_RXD_PD6_Msk)) | UART1_RXD_PD6          /*!< Set PD6 function to UART1_RXD        */
+#define SET_UART1_RXD_PF1()      SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART1_RXD_PF1_Msk)) | UART1_RXD_PF1          /*!< Set PF1 function to UART1_RXD        */
+#define SET_UART1_TXD_PA9()      SYS->GPA_MFPH = (SYS->GPA_MFPH & (~UART1_TXD_PA9_Msk)) | UART1_TXD_PA9          /*!< Set PA9 function to UART1_TXD        */
+#define SET_UART1_TXD_PD11()     SYS->GPD_MFPH = (SYS->GPD_MFPH & (~UART1_TXD_PD11_Msk)) | UART1_TXD_PD11        /*!< Set PD11 function to UART1_TXD       */
+#define SET_UART1_TXD_PF0()      SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART1_TXD_PF0_Msk)) | UART1_TXD_PF0          /*!< Set PF0 function to UART1_TXD        */
+#define SET_UART1_TXD_PB3()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART1_TXD_PB3_Msk)) | UART1_TXD_PB3          /*!< Set PB3 function to UART1_TXD        */
+#define SET_UART1_TXD_PH8()      SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART1_TXD_PH8_Msk)) | UART1_TXD_PH8          /*!< Set PH8 function to UART1_TXD        */
+#define SET_UART1_TXD_PA3()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART1_TXD_PA3_Msk)) | UART1_TXD_PA3          /*!< Set PA3 function to UART1_TXD        */
+#define SET_UART1_TXD_PD7()      SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART1_TXD_PD7_Msk)) | UART1_TXD_PD7          /*!< Set PD7 function to UART1_TXD        */
+#define SET_UART1_TXD_PE13()     SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART1_TXD_PE13_Msk)) | UART1_TXD_PE13        /*!< Set PE13 function to UART1_TXD       */
+#define SET_UART1_TXD_PB7()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART1_TXD_PB7_Msk)) | UART1_TXD_PB7          /*!< Set PB7 function to UART1_TXD        */
+#define SET_UART1_nCTS_PB9()     SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART1_nCTS_PB9_Msk)) | UART1_nCTS_PB9        /*!< Set PB9 function to UART1_nCTS       */
+#define SET_UART1_nCTS_PE11()    SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART1_nCTS_PE11_Msk)) | UART1_nCTS_PE11      /*!< Set PE11 function to UART1_nCTS      */
+#define SET_UART1_nCTS_PA1()     SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART1_nCTS_PA1_Msk)) | UART1_nCTS_PA1        /*!< Set PA1 function to UART1_nCTS       */
+#define SET_UART1_nRTS_PB8()     SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART1_nRTS_PB8_Msk)) | UART1_nRTS_PB8        /*!< Set PB8 function to UART1_nRTS       */
+#define SET_UART1_nRTS_PA0()     SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART1_nRTS_PA0_Msk)) | UART1_nRTS_PA0        /*!< Set PA0 function to UART1_nRTS       */
+#define SET_UART1_nRTS_PE12()    SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART1_nRTS_PE12_Msk)) | UART1_nRTS_PE12      /*!< Set PE12 function to UART1_nRTS      */
+#define SET_UART2_RXD_PE15()     SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART2_RXD_PE15_Msk)) | UART2_RXD_PE15        /*!< Set PE15 function to UART2_RXD       */
+#define SET_UART2_RXD_PC4()      SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART2_RXD_PC4_Msk)) | UART2_RXD_PC4          /*!< Set PC4 function to UART2_RXD        */
+#define SET_UART2_RXD_PD12()     SYS->GPD_MFPH = (SYS->GPD_MFPH & (~UART2_RXD_PD12_Msk)) | UART2_RXD_PD12        /*!< Set PD12 function to UART2_RXD       */
+#define SET_UART2_RXD_PF5()      SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART2_RXD_PF5_Msk)) | UART2_RXD_PF5          /*!< Set PF5 function to UART2_RXD        */
+#define SET_UART2_RXD_PE9()      SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART2_RXD_PE9_Msk)) | UART2_RXD_PE9          /*!< Set PE9 function to UART2_RXD        */
+#define SET_UART2_RXD_PC0()      SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART2_RXD_PC0_Msk)) | UART2_RXD_PC0          /*!< Set PC0 function to UART2_RXD        */
+#define SET_UART2_RXD_PB0()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART2_RXD_PB0_Msk)) | UART2_RXD_PB0          /*!< Set PB0 function to UART2_RXD        */
+#define SET_UART2_RXD_PB4()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART2_RXD_PB4_Msk)) | UART2_RXD_PB4          /*!< Set PB4 function to UART2_RXD        */
+#define SET_UART2_TXD_PF4()      SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART2_TXD_PF4_Msk)) | UART2_TXD_PF4          /*!< Set PF4 function to UART2_TXD        */
+#define SET_UART2_TXD_PC1()      SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART2_TXD_PC1_Msk)) | UART2_TXD_PC1          /*!< Set PC1 function to UART2_TXD        */
+#define SET_UART2_TXD_PB5()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART2_TXD_PB5_Msk)) | UART2_TXD_PB5          /*!< Set PB5 function to UART2_TXD        */
+#define SET_UART2_TXD_PE14()     SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART2_TXD_PE14_Msk)) | UART2_TXD_PE14        /*!< Set PE14 function to UART2_TXD       */
+#define SET_UART2_TXD_PC13()     SYS->GPC_MFPH = (SYS->GPC_MFPH & (~UART2_TXD_PC13_Msk)) | UART2_TXD_PC13        /*!< Set PC13 function to UART2_TXD       */
+#define SET_UART2_TXD_PC5()      SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART2_TXD_PC5_Msk)) | UART2_TXD_PC5          /*!< Set PC5 function to UART2_TXD        */
+#define SET_UART2_TXD_PE8()      SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART2_TXD_PE8_Msk)) | UART2_TXD_PE8          /*!< Set PE8 function to UART2_TXD        */
+#define SET_UART2_TXD_PB1()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART2_TXD_PB1_Msk)) | UART2_TXD_PB1          /*!< Set PB1 function to UART2_TXD        */
+#define SET_UART2_nCTS_PF5()     SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART2_nCTS_PF5_Msk)) | UART2_nCTS_PF5        /*!< Set PF5 function to UART2_nCTS       */
+#define SET_UART2_nCTS_PD9()     SYS->GPD_MFPH = (SYS->GPD_MFPH & (~UART2_nCTS_PD9_Msk)) | UART2_nCTS_PD9        /*!< Set PD9 function to UART2_nCTS       */
+#define SET_UART2_nCTS_PC2()     SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART2_nCTS_PC2_Msk)) | UART2_nCTS_PC2        /*!< Set PC2 function to UART2_nCTS       */
+#define SET_UART2_nRTS_PC3()     SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART2_nRTS_PC3_Msk)) | UART2_nRTS_PC3        /*!< Set PC3 function to UART2_nRTS       */
+#define SET_UART2_nRTS_PD8()     SYS->GPD_MFPH = (SYS->GPD_MFPH & (~UART2_nRTS_PD8_Msk)) | UART2_nRTS_PD8        /*!< Set PD8 function to UART2_nRTS       */
+#define SET_UART2_nRTS_PF4()     SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART2_nRTS_PF4_Msk)) | UART2_nRTS_PF4        /*!< Set PF4 function to UART2_nRTS       */
+#define SET_UART3_RXD_PD0()      SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART3_RXD_PD0_Msk)) | UART3_RXD_PD0          /*!< Set PD0 function to UART3_RXD        */
+#define SET_UART3_RXD_PC9()      SYS->GPC_MFPH = (SYS->GPC_MFPH & (~UART3_RXD_PC9_Msk)) | UART3_RXD_PC9          /*!< Set PC9 function to UART3_RXD        */
+#define SET_UART3_RXD_PE0()      SYS->GPE_MFPL = (SYS->GPE_MFPL & (~UART3_RXD_PE0_Msk)) | UART3_RXD_PE0          /*!< Set PE0 function to UART3_RXD        */
+#define SET_UART3_RXD_PC2()      SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART3_RXD_PC2_Msk)) | UART3_RXD_PC2          /*!< Set PC2 function to UART3_RXD        */
+#define SET_UART3_RXD_PB14()     SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART3_RXD_PB14_Msk)) | UART3_RXD_PB14        /*!< Set PB14 function to UART3_RXD       */
+#define SET_UART3_RXD_PE11()     SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART3_RXD_PE11_Msk)) | UART3_RXD_PE11        /*!< Set PE11 function to UART3_RXD       */
+#define SET_UART3_TXD_PC10()     SYS->GPC_MFPH = (SYS->GPC_MFPH & (~UART3_TXD_PC10_Msk)) | UART3_TXD_PC10        /*!< Set PC10 function to UART3_TXD       */
+#define SET_UART3_TXD_PB15()     SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART3_TXD_PB15_Msk)) | UART3_TXD_PB15        /*!< Set PB15 function to UART3_TXD       */
+#define SET_UART3_TXD_PE10()     SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART3_TXD_PE10_Msk)) | UART3_TXD_PE10        /*!< Set PE10 function to UART3_TXD       */
+#define SET_UART3_TXD_PC3()      SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART3_TXD_PC3_Msk)) | UART3_TXD_PC3          /*!< Set PC3 function to UART3_TXD        */
+#define SET_UART3_TXD_PD1()      SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART3_TXD_PD1_Msk)) | UART3_TXD_PD1          /*!< Set PD1 function to UART3_TXD        */
+#define SET_UART3_TXD_PE1()      SYS->GPE_MFPL = (SYS->GPE_MFPL & (~UART3_TXD_PE1_Msk)) | UART3_TXD_PE1          /*!< Set PE1 function to UART3_TXD        */
+#define SET_UART3_nCTS_PB12()    SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART3_nCTS_PB12_Msk)) | UART3_nCTS_PB12      /*!< Set PB12 function to UART3_nCTS      */
+#define SET_UART3_nCTS_PH9()     SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART3_nCTS_PH9_Msk)) | UART3_nCTS_PH9        /*!< Set PH9 function to UART3_nCTS       */
+#define SET_UART3_nCTS_PD2()     SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART3_nCTS_PD2_Msk)) | UART3_nCTS_PD2        /*!< Set PD2 function to UART3_nCTS       */
+#define SET_UART3_nRTS_PH8()     SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART3_nRTS_PH8_Msk)) | UART3_nRTS_PH8        /*!< Set PH8 function to UART3_nRTS       */
+#define SET_UART3_nRTS_PD3()     SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART3_nRTS_PD3_Msk)) | UART3_nRTS_PD3        /*!< Set PD3 function to UART3_nRTS       */
+#define SET_UART3_nRTS_PB13()    SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART3_nRTS_PB13_Msk)) | UART3_nRTS_PB13      /*!< Set PB13 function to UART3_nRTS      */
+#define SET_UART4_RXD_PA2()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART4_RXD_PA2_Msk)) | UART4_RXD_PA2          /*!< Set PA2 function to UART4_RXD        */
+#define SET_UART4_RXD_PA13()     SYS->GPA_MFPH = (SYS->GPA_MFPH & (~UART4_RXD_PA13_Msk)) | UART4_RXD_PA13        /*!< Set PA13 function to UART4_RXD       */
+#define SET_UART4_RXD_PC4()      SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART4_RXD_PC4_Msk)) | UART4_RXD_PC4          /*!< Set PC4 function to UART4_RXD        */
+#define SET_UART4_RXD_PH11()     SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART4_RXD_PH11_Msk)) | UART4_RXD_PH11        /*!< Set PH11 function to UART4_RXD       */
+#define SET_UART4_RXD_PF6()      SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART4_RXD_PF6_Msk)) | UART4_RXD_PF6          /*!< Set PF6 function to UART4_RXD        */
+#define SET_UART4_RXD_PB10()     SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART4_RXD_PB10_Msk)) | UART4_RXD_PB10        /*!< Set PB10 function to UART4_RXD       */
+#define SET_UART4_RXD_PC6()      SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART4_RXD_PC6_Msk)) | UART4_RXD_PC6          /*!< Set PC6 function to UART4_RXD        */
+#define SET_UART4_TXD_PA3()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART4_TXD_PA3_Msk)) | UART4_TXD_PA3          /*!< Set PA3 function to UART4_TXD        */
+#define SET_UART4_TXD_PC5()      SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART4_TXD_PC5_Msk)) | UART4_TXD_PC5          /*!< Set PC5 function to UART4_TXD        */
+#define SET_UART4_TXD_PC7()      SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART4_TXD_PC7_Msk)) | UART4_TXD_PC7          /*!< Set PC7 function to UART4_TXD        */
+#define SET_UART4_TXD_PA12()     SYS->GPA_MFPH = (SYS->GPA_MFPH & (~UART4_TXD_PA12_Msk)) | UART4_TXD_PA12        /*!< Set PA12 function to UART4_TXD       */
+#define SET_UART4_TXD_PF7()      SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART4_TXD_PF7_Msk)) | UART4_TXD_PF7          /*!< Set PF7 function to UART4_TXD        */
+#define SET_UART4_TXD_PH10()     SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART4_TXD_PH10_Msk)) | UART4_TXD_PH10        /*!< Set PH10 function to UART4_TXD       */
+#define SET_UART4_TXD_PB11()     SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART4_TXD_PB11_Msk)) | UART4_TXD_PB11        /*!< Set PB11 function to UART4_TXD       */
+#define SET_UART4_nCTS_PC8()     SYS->GPC_MFPH = (SYS->GPC_MFPH & (~UART4_nCTS_PC8_Msk)) | UART4_nCTS_PC8        /*!< Set PC8 function to UART4_nCTS       */
+#define SET_UART4_nCTS_PE1()     SYS->GPE_MFPL = (SYS->GPE_MFPL & (~UART4_nCTS_PE1_Msk)) | UART4_nCTS_PE1        /*!< Set PE1 function to UART4_nCTS       */
+#define SET_UART4_nRTS_PE0()     SYS->GPE_MFPL = (SYS->GPE_MFPL & (~UART4_nRTS_PE0_Msk)) | UART4_nRTS_PE0        /*!< Set PE0 function to UART4_nRTS       */
+#define SET_UART4_nRTS_PE13()    SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART4_nRTS_PE13_Msk)) | UART4_nRTS_PE13      /*!< Set PE13 function to UART4_nRTS      */
+#define SET_UART5_RXD_PB4()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART5_RXD_PB4_Msk)) | UART5_RXD_PB4          /*!< Set PB4 function to UART5_RXD        */
+#define SET_UART5_RXD_PF10()     SYS->GPF_MFPH = (SYS->GPF_MFPH & (~UART5_RXD_PF10_Msk)) | UART5_RXD_PF10        /*!< Set PF10 function to UART5_RXD       */
+#define SET_UART5_RXD_PE6()      SYS->GPE_MFPL = (SYS->GPE_MFPL & (~UART5_RXD_PE6_Msk)) | UART5_RXD_PE6          /*!< Set PE6 function to UART5_RXD        */
+#define SET_UART5_RXD_PA4()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART5_RXD_PA4_Msk)) | UART5_RXD_PA4          /*!< Set PA4 function to UART5_RXD        */
+#define SET_UART5_TXD_PF11()     SYS->GPF_MFPH = (SYS->GPF_MFPH & (~UART5_TXD_PF11_Msk)) | UART5_TXD_PF11        /*!< Set PF11 function to UART5_TXD       */
+#define SET_UART5_TXD_PB5()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART5_TXD_PB5_Msk)) | UART5_TXD_PB5          /*!< Set PB5 function to UART5_TXD        */
+#define SET_UART5_TXD_PE7()      SYS->GPE_MFPL = (SYS->GPE_MFPL & (~UART5_TXD_PE7_Msk)) | UART5_TXD_PE7          /*!< Set PE7 function to UART5_TXD        */
+#define SET_UART5_TXD_PA5()      SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART5_TXD_PA5_Msk)) | UART5_TXD_PA5          /*!< Set PA5 function to UART5_TXD        */
+#define SET_UART5_nCTS_PB2()     SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART5_nCTS_PB2_Msk)) | UART5_nCTS_PB2        /*!< Set PB2 function to UART5_nCTS       */
+#define SET_UART5_nCTS_PF8()     SYS->GPF_MFPH = (SYS->GPF_MFPH & (~UART5_nCTS_PF8_Msk)) | UART5_nCTS_PF8        /*!< Set PF8 function to UART5_nCTS       */
+#define SET_UART5_nRTS_PF9()     SYS->GPF_MFPH = (SYS->GPF_MFPH & (~UART5_nRTS_PF9_Msk)) | UART5_nRTS_PF9        /*!< Set PF9 function to UART5_nRTS       */
+#define SET_UART5_nRTS_PB3()     SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART5_nRTS_PB3_Msk)) | UART5_nRTS_PB3        /*!< Set PB3 function to UART5_nRTS       */
+#define SET_USB_D_P_PA14()       SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USB_D_P_PA14_Msk)) | USB_D_P_PA14            /*!< Set PA14 function to USB_D_P         */
+#define SET_USB_D_N_PA13()       SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USB_D_N_PA13_Msk)) | USB_D_N_PA13            /*!< Set PA13 function to USB_D_N         */
+#define SET_USB_OTG_ID_PA15()    SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USB_OTG_ID_PA15_Msk)) | USB_OTG_ID_PA15      /*!< Set PA15 function to USB_OTG_ID      */
+#define SET_USB_VBUS_PA12()      SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USB_VBUS_PA12_Msk)) | USB_VBUS_PA12          /*!< Set PA12 function to USB_VBUS        */
+#define SET_USB_VBUS_EN_PB15()   SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USB_VBUS_EN_PB15_Msk)) | USB_VBUS_EN_PB15    /*!< Set PB15 function to USB_VBUS_EN     */
+#define SET_USB_VBUS_EN_PB6()    SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USB_VBUS_EN_PB6_Msk)) | USB_VBUS_EN_PB6      /*!< Set PB6 function to USB_VBUS_EN      */
+#define SET_USB_VBUS_ST_PB14()   SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USB_VBUS_ST_PB14_Msk)) | USB_VBUS_ST_PB14    /*!< Set PB14 function to USB_VBUS_ST     */
+#define SET_USB_VBUS_ST_PB7()    SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USB_VBUS_ST_PB7_Msk)) | USB_VBUS_ST_PB7      /*!< Set PB7 function to USB_VBUS_ST      */
+#define SET_USB_VBUS_ST_PD4()    SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USB_VBUS_ST_PD4_Msk)) | USB_VBUS_ST_PD4      /*!< Set PD4 function to USB_VBUS_ST      */
+#define SET_USCI0_CLK_PA11()     SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USCI0_CLK_PA11_Msk)) | USCI0_CLK_PA11        /*!< Set PA11 function to USCI0_CLK       */
+#define SET_USCI0_CLK_PD0()      SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI0_CLK_PD0_Msk)) | USCI0_CLK_PD0          /*!< Set PD0 function to USCI0_CLK        */
+#define SET_USCI0_CLK_PB12()     SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USCI0_CLK_PB12_Msk)) | USCI0_CLK_PB12        /*!< Set PB12 function to USCI0_CLK       */
+#define SET_USCI0_CLK_PE2()      SYS->GPE_MFPL = (SYS->GPE_MFPL & (~USCI0_CLK_PE2_Msk)) | USCI0_CLK_PE2          /*!< Set PE2 function to USCI0_CLK        */
+#define SET_USCI0_CTL0_PC13()    SYS->GPC_MFPH = (SYS->GPC_MFPH & (~USCI0_CTL0_PC13_Msk)) | USCI0_CTL0_PC13      /*!< Set PC13 function to USCI0_CTL0      */
+#define SET_USCI0_CTL0_PD14()    SYS->GPD_MFPH = (SYS->GPD_MFPH & (~USCI0_CTL0_PD14_Msk)) | USCI0_CTL0_PD14      /*!< Set PD14 function to USCI0_CTL0      */
+#define SET_USCI0_CTL0_PE6()     SYS->GPE_MFPL = (SYS->GPE_MFPL & (~USCI0_CTL0_PE6_Msk)) | USCI0_CTL0_PE6        /*!< Set PE6 function to USCI0_CTL0       */
+#define SET_USCI0_CTL0_PD4()     SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI0_CTL0_PD4_Msk)) | USCI0_CTL0_PD4        /*!< Set PD4 function to USCI0_CTL0       */
+#define SET_USCI0_CTL1_PD3()     SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI0_CTL1_PD3_Msk)) | USCI0_CTL1_PD3        /*!< Set PD3 function to USCI0_CTL1       */
+#define SET_USCI0_CTL1_PA8()     SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USCI0_CTL1_PA8_Msk)) | USCI0_CTL1_PA8        /*!< Set PA8 function to USCI0_CTL1       */
+#define SET_USCI0_CTL1_PE5()     SYS->GPE_MFPL = (SYS->GPE_MFPL & (~USCI0_CTL1_PE5_Msk)) | USCI0_CTL1_PE5        /*!< Set PE5 function to USCI0_CTL1       */
+#define SET_USCI0_CTL1_PB15()    SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USCI0_CTL1_PB15_Msk)) | USCI0_CTL1_PB15      /*!< Set PB15 function to USCI0_CTL1      */
+#define SET_USCI0_DAT0_PB13()    SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USCI0_DAT0_PB13_Msk)) | USCI0_DAT0_PB13      /*!< Set PB13 function to USCI0_DAT0      */
+#define SET_USCI0_DAT0_PE3()     SYS->GPE_MFPL = (SYS->GPE_MFPL & (~USCI0_DAT0_PE3_Msk)) | USCI0_DAT0_PE3        /*!< Set PE3 function to USCI0_DAT0       */
+#define SET_USCI0_DAT0_PA10()    SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USCI0_DAT0_PA10_Msk)) | USCI0_DAT0_PA10      /*!< Set PA10 function to USCI0_DAT0      */
+#define SET_USCI0_DAT0_PD1()     SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI0_DAT0_PD1_Msk)) | USCI0_DAT0_PD1        /*!< Set PD1 function to USCI0_DAT0       */
+#define SET_USCI0_DAT1_PA9()     SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USCI0_DAT1_PA9_Msk)) | USCI0_DAT1_PA9        /*!< Set PA9 function to USCI0_DAT1       */
+#define SET_USCI0_DAT1_PE4()     SYS->GPE_MFPL = (SYS->GPE_MFPL & (~USCI0_DAT1_PE4_Msk)) | USCI0_DAT1_PE4        /*!< Set PE4 function to USCI0_DAT1       */
+#define SET_USCI0_DAT1_PB14()    SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USCI0_DAT1_PB14_Msk)) | USCI0_DAT1_PB14      /*!< Set PB14 function to USCI0_DAT1      */
+#define SET_USCI0_DAT1_PD2()     SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI0_DAT1_PD2_Msk)) | USCI0_DAT1_PD2        /*!< Set PD2 function to USCI0_DAT1       */
+#define SET_USCI1_CLK_PE12()     SYS->GPE_MFPH = (SYS->GPE_MFPH & (~USCI1_CLK_PE12_Msk)) | USCI1_CLK_PE12        /*!< Set PE12 function to USCI1_CLK       */
+#define SET_USCI1_CLK_PB1()      SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USCI1_CLK_PB1_Msk)) | USCI1_CLK_PB1          /*!< Set PB1 function to USCI1_CLK        */
+#define SET_USCI1_CLK_PD7()      SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI1_CLK_PD7_Msk)) | USCI1_CLK_PD7          /*!< Set PD7 function to USCI1_CLK        */
+#define SET_USCI1_CLK_PB8()      SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USCI1_CLK_PB8_Msk)) | USCI1_CLK_PB8          /*!< Set PB8 function to USCI1_CLK        */
+#define SET_USCI1_CTL0_PE9()     SYS->GPE_MFPH = (SYS->GPE_MFPH & (~USCI1_CTL0_PE9_Msk)) | USCI1_CTL0_PE9        /*!< Set PE9 function to USCI1_CTL0       */
+#define SET_USCI1_CTL0_PB5()     SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USCI1_CTL0_PB5_Msk)) | USCI1_CTL0_PB5        /*!< Set PB5 function to USCI1_CTL0       */
+#define SET_USCI1_CTL0_PD3()     SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI1_CTL0_PD3_Msk)) | USCI1_CTL0_PD3        /*!< Set PD3 function to USCI1_CTL0       */
+#define SET_USCI1_CTL0_PB10()    SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USCI1_CTL0_PB10_Msk)) | USCI1_CTL0_PB10      /*!< Set PB10 function to USCI1_CTL0      */
+#define SET_USCI1_CTL1_PB4()     SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USCI1_CTL1_PB4_Msk)) | USCI1_CTL1_PB4        /*!< Set PB4 function to USCI1_CTL1       */
+#define SET_USCI1_CTL1_PD4()     SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI1_CTL1_PD4_Msk)) | USCI1_CTL1_PD4        /*!< Set PD4 function to USCI1_CTL1       */
+#define SET_USCI1_CTL1_PE8()     SYS->GPE_MFPH = (SYS->GPE_MFPH & (~USCI1_CTL1_PE8_Msk)) | USCI1_CTL1_PE8        /*!< Set PE8 function to USCI1_CTL1       */
+#define SET_USCI1_CTL1_PB9()     SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USCI1_CTL1_PB9_Msk)) | USCI1_CTL1_PB9        /*!< Set PB9 function to USCI1_CTL1       */
+#define SET_USCI1_DAT0_PB7()     SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USCI1_DAT0_PB7_Msk)) | USCI1_DAT0_PB7        /*!< Set PB7 function to USCI1_DAT0       */
+#define SET_USCI1_DAT0_PE10()    SYS->GPE_MFPH = (SYS->GPE_MFPH & (~USCI1_DAT0_PE10_Msk)) | USCI1_DAT0_PE10      /*!< Set PE10 function to USCI1_DAT0      */
+#define SET_USCI1_DAT0_PB2()     SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USCI1_DAT0_PB2_Msk)) | USCI1_DAT0_PB2        /*!< Set PB2 function to USCI1_DAT0       */
+#define SET_USCI1_DAT0_PD5()     SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI1_DAT0_PD5_Msk)) | USCI1_DAT0_PD5        /*!< Set PD5 function to USCI1_DAT0       */
+#define SET_USCI1_DAT1_PD6()     SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI1_DAT1_PD6_Msk)) | USCI1_DAT1_PD6        /*!< Set PD6 function to USCI1_DAT1       */
+#define SET_USCI1_DAT1_PB6()     SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USCI1_DAT1_PB6_Msk)) | USCI1_DAT1_PB6        /*!< Set PB6 function to USCI1_DAT1       */
+#define SET_USCI1_DAT1_PE11()    SYS->GPE_MFPH = (SYS->GPE_MFPH & (~USCI1_DAT1_PE11_Msk)) | USCI1_DAT1_PE11      /*!< Set PE11 function to USCI1_DAT1      */
+#define SET_USCI1_DAT1_PB3()     SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USCI1_DAT1_PB3_Msk)) | USCI1_DAT1_PB3        /*!< Set PB3 function to USCI1_DAT1       */
+#define SET_X32_IN_PF5()         SYS->GPF_MFPL = (SYS->GPF_MFPL & (~X32_IN_PF5_Msk)) | X32_IN_PF5                /*!< Set PF5 function to X32_IN           */
+#define SET_X32_OUT_PF4()        SYS->GPF_MFPL = (SYS->GPF_MFPL & (~X32_OUT_PF4_Msk)) | X32_OUT_PF4              /*!< Set PF4 function to X32_OUT          */
+#define SET_XT1_IN_PF3()         SYS->GPF_MFPL = (SYS->GPF_MFPL & (~XT1_IN_PF3_Msk)) | XT1_IN_PF3                /*!< Set PF3 function to XT1_IN           */
+#define SET_XT1_OUT_PF2()        SYS->GPF_MFPL = (SYS->GPF_MFPL & (~XT1_OUT_PF2_Msk)) | XT1_OUT_PF2              /*!< Set PF2 function to XT1_OUT          */
+
+
+/**
+  * @brief      Clear Brown-out detector interrupt flag
+  * @param      None
+  * @return     None
+  * @details    This macro clear Brown-out detector interrupt flag.
+  */
+#define SYS_CLEAR_BOD_INT_FLAG() \
+   do{ \
+        while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \
+        SYS->BODCTL |= SYS_BODCTL_BODIF_Msk; \
+    }while(0)
+
+/**
+  * @brief      Disable Brown-out detector function
+  * @param      None
+  * @return     None
+  * @details    This macro disable Brown-out detector function.
+  *             The register write-protection function should be disabled before using this macro.
+  */
+#define SYS_DISABLE_BOD() \
+   do{ \
+        while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \
+        SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk; \
+    }while(0)
+
+/**
+  * @brief      Enable Brown-out detector function
+  * @param      None
+  * @return     None
+  * @details    This macro enable Brown-out detector function.
+  *             The register write-protection function should be disabled before using this macro.
+  */
+#define SYS_ENABLE_BOD() \
+   do{ \
+        while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \
+        SYS->BODCTL |= SYS_BODCTL_BODEN_Msk; \
+    }while(0)
+
+/**
+  * @brief      Get Brown-out detector interrupt flag
+  * @param      None
+  * @retval     0   Brown-out detect interrupt flag is not set.
+  * @retval     >=1 Brown-out detect interrupt flag is set.
+  * @details    This macro get Brown-out detector interrupt flag.
+  */
+#define SYS_GET_BOD_INT_FLAG()          (SYS->BODCTL & SYS_BODCTL_BODIF_Msk)
+
+/**
+  * @brief      Get Brown-out detector status
+  * @param      None
+  * @retval     0   System voltage is higher than BOD threshold voltage setting or BOD function is disabled.
+  * @retval     >=1 System voltage is lower than BOD threshold voltage setting.
+  * @details    This macro get Brown-out detector output status.
+  *             If the BOD function is disabled, this function always return 0.
+  */
+#define SYS_GET_BOD_OUTPUT()            (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk)
+
+/**
+  * @brief      Enable Brown-out detector interrupt function
+  * @param      None
+  * @return     None
+  * @details    This macro enable Brown-out detector interrupt function.
+  *             The register write-protection function should be disabled before using this macro.
+  */
+#define SYS_DISABLE_BOD_RST() \
+   do{ \
+        while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \
+        SYS->BODCTL &= ~SYS_BODCTL_BODRSTEN_Msk; \
+    }while(0)
+
+/**
+  * @brief      Enable Brown-out detector reset function
+  * @param      None
+  * @return     None
+  * @details    This macro enable Brown-out detect reset function.
+  *             The register write-protection function should be disabled before using this macro.
+  */
+#define SYS_ENABLE_BOD_RST() \
+   do{ \
+        while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \
+        SYS->BODCTL |= SYS_BODCTL_BODRSTEN_Msk; \
+    }while(0)
+
+/**
+  * @brief      Set Brown-out detector voltage level
+  * @param[in]  u32Level is Brown-out voltage level. Including :
+  *             - \ref SYS_BODCTL_BODVL_1_6V
+  *             - \ref SYS_BODCTL_BODVL_1_8V
+  *             - \ref SYS_BODCTL_BODVL_2_0V
+  *             - \ref SYS_BODCTL_BODVL_2_2V
+  *             - \ref SYS_BODCTL_BODVL_2_4V
+  *             - \ref SYS_BODCTL_BODVL_2_6V
+  *             - \ref SYS_BODCTL_BODVL_2_8V
+  *             - \ref SYS_BODCTL_BODVL_3_0V
+  * @return     None
+  * @details    This macro set Brown-out detector voltage level.
+  *             The write-protection function should be disabled before using this macro.
+  */
+#define SYS_SET_BOD_LEVEL(u32Level) \
+   do{ \
+        while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \
+        SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | (u32Level); \
+    }while(0)
+
+/**
+  * @brief      Get reset source is from Brown-out detector reset
+  * @param      None
+  * @retval     0   Previous reset source is not from Brown-out detector reset
+  * @retval     >=1 Previous reset source is from Brown-out detector reset
+  * @details    This macro get previous reset source is from Brown-out detect reset or not.
+  */
+#define SYS_IS_BOD_RST()                (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk)
+
+/**
+  * @brief      Get reset source is from CPU reset
+  * @param      None
+  * @retval     0   Previous reset source is not from CPU reset
+  * @retval     >=1 Previous reset source is from CPU reset
+  * @details    This macro get previous reset source is from CPU reset.
+  */
+#define SYS_IS_CPU_RST()                (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk)
+
+/**
+  * @brief      Get reset source is from LVR Reset
+  * @param      None
+  * @retval     0   Previous reset source is not from Low-Voltage-Reset
+  * @retval     >=1 Previous reset source is from Low-Voltage-Reset
+  * @details    This macro get previous reset source is from Low-Voltage-Reset.
+  */
+#define SYS_IS_LVR_RST()                (SYS->RSTSTS & SYS_RSTSTS_LVRF_Msk)
+
+/**
+  * @brief      Get reset source is from Power-on Reset
+  * @param      None
+  * @retval     0   Previous reset source is not from Power-on Reset
+  * @retval     >=1 Previous reset source is from Power-on Reset
+  * @details    This macro get previous reset source is from Power-on Reset.
+  */
+#define SYS_IS_POR_RST()                (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk)
+
+/**
+  * @brief      Get reset source is from reset pin reset
+  * @param      None
+  * @retval     0   Previous reset source is not from reset pin reset
+  * @retval     >=1 Previous reset source is from reset pin reset
+  * @details    This macro get previous reset source is from reset pin reset.
+  */
+#define SYS_IS_RSTPIN_RST()             (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk)
+
+/**
+  * @brief      Get reset source is from system reset
+  * @param      None
+  * @retval     0   Previous reset source is not from system reset
+  * @retval     >=1 Previous reset source is from system reset
+  * @details    This macro get previous reset source is from system reset.
+  */
+#define SYS_IS_SYSTEM_RST()             (SYS->RSTSTS & SYS_RSTSTS_SYSRF_Msk)
+
+/**
+  * @brief      Get reset source is from window watch dog reset
+  * @param      None
+  * @retval     0   Previous reset source is not from window watch dog reset
+  * @retval     >=1 Previous reset source is from window watch dog reset
+  * @details    This macro get previous reset source is from window watch dog reset.
+  */
+#define SYS_IS_WDT_RST()                (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk)
+
+/**
+  * @brief      Disable Low-Voltage-Reset function
+  * @param      None
+  * @return     None
+  * @details    This macro disable Low-Voltage-Reset function.
+  *             The register write-protection function should be disabled before using this macro.
+  */
+#define SYS_DISABLE_LVR() \
+   do{ \
+        while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \
+        SYS->BODCTL &= ~SYS_BODCTL_LVREN_Msk; \
+    }while(0)
+
+/**
+  * @brief      Enable Low-Voltage-Reset function
+  * @param      None
+  * @return     None
+  * @details    This macro enable Low-Voltage-Reset function.
+  *             The register write-protection function should be disabled before using this macro.
+  */
+#define SYS_ENABLE_LVR() \
+   do{ \
+        while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \
+        SYS->BODCTL |= SYS_BODCTL_LVREN_Msk; \
+    }while(0)
+
+/**
+  * @brief      Disable Power-on Reset function
+  * @param      None
+  * @return     None
+  * @details    This macro disable Power-on Reset function.
+  *             The register write-protection function should be disabled before using this macro.
+  */
+#define SYS_DISABLE_POR()               (SYS->PORCTL0 = 0x5AA5)
+
+/**
+  * @brief      Enable Power-on Reset function
+  * @param      None
+  * @return     None
+  * @details    This macro enable Power-on Reset function.
+  *             The register write-protection function should be disabled before using this macro.
+  */
+#define SYS_ENABLE_POR()                (SYS->PORCTL0 = 0)
+
+/**
+  * @brief      Clear reset source flag
+  * @param[in]  u32RstSrc is reset source. Including :
+  *             - \ref SYS_RSTSTS_PORF_Msk
+  *             - \ref SYS_RSTSTS_PINRF_Msk
+  *             - \ref SYS_RSTSTS_WDTRF_Msk
+  *             - \ref SYS_RSTSTS_LVRF_Msk
+  *             - \ref SYS_RSTSTS_BODRF_Msk
+  *             - \ref SYS_RSTSTS_SYSRF_Msk
+  *             - \ref SYS_RSTSTS_CPURF_Msk
+  *             - \ref SYS_RSTSTS_CPULKRF_Msk
+  * @return     None
+  * @details    This macro clear reset source flag.
+  */
+#define SYS_CLEAR_RST_SOURCE(u32RstSrc) ((SYS->RSTSTS) = (u32RstSrc) )
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* static inline functions                                                                                 */
+/*---------------------------------------------------------------------------------------------------------*/
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
+__STATIC_INLINE void SYS_UnlockReg(void);
+__STATIC_INLINE void SYS_LockReg(void);
+
+
+/**
+  * @brief      Disable register write-protection function
+  * @param      None
+  * @return     None
+  * @details    This function disable register write-protection function.
+  *             To unlock the protected register to allow write access.
+  */
+__STATIC_INLINE void SYS_UnlockReg(void)
+{
+    do
+    {
+        SYS->REGLCTL = 0x59UL;
+        SYS->REGLCTL = 0x16UL;
+        SYS->REGLCTL = 0x88UL;
+    }
+    while(SYS->REGLCTL == 0UL);
+}
+
+/**
+  * @brief      Enable register write-protection function
+  * @param      None
+  * @return     None
+  * @details    This function is used to enable register write-protection function.
+  *             To lock the protected register to forbid write access.
+  */
+__STATIC_INLINE void SYS_LockReg(void)
+{
+    SYS->REGLCTL = 0UL;
+}
+
+
+void SYS_ClearResetSrc(uint32_t u32Src);
+uint32_t SYS_GetBODStatus(void);
+uint32_t SYS_GetResetSrc(void);
+uint32_t SYS_IsRegLocked(void);
+uint32_t SYS_ReadPDID(void);
+void SYS_ResetChip(void);
+void SYS_ResetCPU(void);
+void SYS_ResetModule(uint32_t u32ModuleIndex);
+void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel);
+void SYS_DisableBOD(void);
+void SYS_SetPowerLevel(uint32_t u32PowerLevel);
+uint32_t SYS_SetPowerRegulator(uint32_t u32PowerRegulator);
+void SYS_SetSSRAMPowerMode(uint32_t u32SRAMSel, uint32_t u32PowerMode);
+void SYS_SetPSRAMPowerMode(uint32_t u32SRAMSel, uint32_t u32PowerMode);
+void SYS_SetVRef(uint32_t u32VRefCTL);
+
+
+/**@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group SYS_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_SYS_H__ */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_tamper.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_tamper.h
new file mode 100644
index 0000000000..4edf9459cf
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_tamper.h
@@ -0,0 +1,464 @@
+/**************************************************************************//**
+ * @file     nu_tamper.h
+ * @version  V3.00
+ * @brief    M2354 series TAMPER driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_TAMPER_H__
+#define __NU_TAMPER_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup TAMPER_Driver Tamper Driver
+  @{
+*/
+
+/** @addtogroup TAMPER_EXPORTED_CONSTANTS Tamper Exported Constants
+  @{
+*/
+
+#define TAMPER_TAMPER0_SELECT      (0x1UL << 0)    /*!< Select Tamper 0 */
+#define TAMPER_TAMPER1_SELECT      (0x1UL << 1)    /*!< Select Tamper 1 */
+#define TAMPER_TAMPER2_SELECT      (0x1UL << 2)    /*!< Select Tamper 2 */
+#define TAMPER_TAMPER3_SELECT      (0x1UL << 3)    /*!< Select Tamper 3 */
+#define TAMPER_TAMPER4_SELECT      (0x1UL << 4)    /*!< Select Tamper 4 */
+#define TAMPER_TAMPER5_SELECT      (0x1UL << 5)    /*!< Select Tamper 5 */
+#define TAMPER_MAX_TAMPER_PIN_NUM  6UL             /*!< Tamper Pin number */
+
+#define TAMPER_TAMPER_HIGH_LEVEL_DETECT    1UL     /*!< Tamper pin detect voltage level is high */
+#define TAMPER_TAMPER_LOW_LEVEL_DETECT     0UL     /*!< Tamper pin detect voltage level is low */
+
+#define TAMPER_TAMPER_DEBOUNCE_ENABLE      1UL     /*!< Enable tamper pin de-bounce function */
+#define TAMPER_TAMPER_DEBOUNCE_DISABLE     0UL     /*!< Disable tamper pin de-bounce function */
+
+#define TAMPER_PAIR0_SELECT        (0x1UL << 0)    /*!< Select Pair 0 */
+#define TAMPER_PAIR1_SELECT        (0x1UL << 1)    /*!< Select Pair 1 */
+#define TAMPER_PAIR2_SELECT        (0x1UL << 2)    /*!< Select Pair 2 */
+#define TAMPER_MAX_PAIR_NUM        3UL             /*!< Pair number */
+
+#define TAMPER_2POW6_CLK           (0x0UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 RTC clock cycles */
+#define TAMPER_2POW7_CLK           (0x1UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 x 2 RTC clock cycles */
+#define TAMPER_2POW8_CLK           (0x2UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 x 4 RTC clock cycles */
+#define TAMPER_2POW9_CLK           (0x3UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 x 6 RTC clock cycles */
+#define TAMPER_2POW10_CLK          (0x4UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 x 8 RTC clock cycles */
+#define TAMPER_2POW11_CLK          (0x5UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 x 10 RTC clock cycles */
+#define TAMPER_2POW12_CLK          (0x6UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 x 12 RTC clock cycles */
+#define TAMPER_2POW13_CLK          (0x7UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 x 14 RTC clock cycles */
+
+#define TAMPER_ACTS_2POW10_CLK     (0x0UL << 5)    /*!< 1024 LIRC32K clock cycles */
+#define TAMPER_ACTS_2POW11_CLK     (0x1UL << 5)    /*!< 1024 x 2 LIRC32K clock cycles */
+#define TAMPER_ACTS_2POW12_CLK     (0x2UL << 5)    /*!< 1024 x 4 LIRC32K clock cycles */
+#define TAMPER_ACTS_2POW13_CLK     (0x3UL << 5)    /*!< 1024 x 6 LIRC32K clock cycles */
+#define TAMPER_ACTS_2POW14_CLK     (0x4UL << 5)    /*!< 1024 x 8 LIRC32K clock cycles */
+#define TAMPER_ACTS_2POW15_CLK     (0x5UL << 5)    /*!< 1024 x 16 LIRC32K clock cycles */
+#define TAMPER_ACTS_2POW16_CLK     (0x6UL << 5)    /*!< 1024 x 32 LIRC32K clock cycles */
+#define TAMPER_ACTS_2POW17_CLK     (0x7UL << 5)    /*!< 1024 x 64 LIRC32K clock cycles */
+
+#define TAMPER_REF_RANDOM_PATTERN        0x0UL     /*!< The new reference pattern is generated by random number generator when the reference pattern run out */
+#define TAMPER_REF_SEED                  0x1UL     /*!< The new reference pattern is repeated from SEED (TAMPER_SEED[31:0]) when the reference pattern run out */
+
+#define TAMPER_VG_192M_SAMPLE            0x0UL     /*!< Select voltage glitch 192M sampleing rate */
+
+/**@}*/ /* end of group TAMPER_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup TAMPER_EXPORTED_FUNCTIONS Tamper Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Reset Tamper Coreblock
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    To set TAMPER INIT control register to reset the tamper coreblock.
+  *
+  */
+#define TAMPER_CORE_RESET()                 ((uint32_t)(TAMPER->INIT = 0x55AA))
+
+/**
+  * @brief      Release Tamper Coreblock
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    To set TAMPER INIT control register to release the tamper coreblock.
+  *
+  */
+#define TAMPER_CORE_RELEASE()               ((uint32_t)(TAMPER->INIT = 0x5500))
+
+/**
+  * @brief      Get the Voltage Regulator Power Ready Status
+  *
+  * @param      None
+  *
+  * @retval     0   The power status of voltage regulator is not ready.
+  * @retval     1   The power status of voltage regulator is ready.
+  *
+  * @details    This macro will return the power status of voltage regulator.
+  *
+  */
+#define TAMPER_TLDO_IS_READY()              (TAMPER->INIT & TAMPER_INIT_TLDORDY_Msk ? 1:0)
+
+/**
+  * @brief      Enable LXT Clock Detection
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    To set TAMPER FUNEN control register to enable LXT clock detection.
+  *
+  */
+#define TAMPER_ENABLE_LXTDET()              ((uint32_t)(TAMPER->FUNEN = (TAMPER->FUNEN & ~0xFFUL) | 0x44))
+
+/**
+  * @brief      Disable LXT Clock Detection
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    To set TAMPER FUNEN control register to disable LXT clock detection.
+  *
+  */
+#define TAMPER_DISABLE_LXTDET()             ((uint32_t)(TAMPER->FUNEN = (TAMPER->FUNEN & ~0xFFUL) | 0x40))
+
+/**
+  * @brief      Tamper I/O TAMPER Block Detection Selection
+  *
+  * @param[in]  u32TamperSelect   Tamper pin select. Possible options are
+  *                               - \ref TAMPER_TAMPER0_SELECT
+  *                               - \ref TAMPER_TAMPER1_SELECT
+  *                               - \ref TAMPER_TAMPER2_SELECT
+  *                               - \ref TAMPER_TAMPER3_SELECT
+  *                               - \ref TAMPER_TAMPER4_SELECT
+  *                               - \ref TAMPER_TAMPER5_SELECT
+  *
+  * @return     None
+  *
+  * @details    To set TAMPER FUNEN control register to select tamper I/O 0~5 and its function is detected through TAMPER block.
+  *
+  */
+__STATIC_INLINE void TAMPER_IOSEL_TAMPER(uint32_t u32TamperSelect)
+{
+    uint32_t i;
+
+    for(i = 0UL; i < (uint32_t)TAMPER_MAX_TAMPER_PIN_NUM; i++)
+    {
+        if(u32TamperSelect & (0x1UL << i))
+        {
+            TAMPER->FUNEN = (TAMPER->FUNEN & ~0xFFUL) | (0x94 + i * 0x10UL);
+        }
+    }
+}
+
+/**
+  * @brief      Tamper I/O RTC Block Detection Selection
+  *
+  * @param[in]  u32TamperSelect   Tamper pin select. Possible options are
+  *                               - \ref TAMPER_TAMPER0_SELECT
+  *                               - \ref TAMPER_TAMPER1_SELECT
+  *                               - \ref TAMPER_TAMPER2_SELECT
+  *                               - \ref TAMPER_TAMPER3_SELECT
+  *                               - \ref TAMPER_TAMPER4_SELECT
+  *                               - \ref TAMPER_TAMPER5_SELECT
+  *
+  * @return     None
+  *
+  * @details    To set TAMPER FUNEN control register to select tamper I/O 0~5 and its function is detected through RTC block.
+  *
+  */
+__STATIC_INLINE void TAMPER_IOSEL_RTC(uint32_t u32TamperSelect)
+{
+    uint32_t i;
+
+    for(i = 0UL; i < (uint32_t)TAMPER_MAX_TAMPER_PIN_NUM; i++)
+    {
+        if(u32TamperSelect & (0x1UL << i))
+        {
+            TAMPER->FUNEN = (TAMPER->FUNEN & ~0xFFUL) | (0x90 + i * 0x10UL);
+        }
+    }
+}
+
+/**
+  * @brief      Enable HIRC48M
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    To set TAMPER FUNEN control register to enable HIRC48M.
+  *
+  */
+#define TAMPER_ENABLE_HIRC48M()             ((uint32_t)(TAMPER->FUNEN &= (~TAMPER_FUNEN_HIRC48MEN_Msk)))
+
+/**
+  * @brief      Disable HIRC48M
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    To set TAMPER FUNEN control register to disable HIRC48M.
+  *
+  */
+#define TAMPER_DISABLE_HIRC48M()            ((uint32_t)(TAMPER->FUNEN = (TAMPER->FUNEN & (~TAMPER_FUNEN_HIRC48MEN_Msk)) | (0x5A << TAMPER_FUNEN_HIRC48MEN_Pos)))
+
+/**
+  * @brief      Voltage Glitch Sampling Rate Selection
+  *
+  * @param[in]  u32VGSampleRate Voltage Glitch sampling rate select. Possible option is
+  *                             - \ref TAMPER_VG_192M_SAMPLE
+  *
+  * @return     None
+  *
+  * @details    To set TAMPER FUNEN control register to enable voltage glitch channel 0~3 to select voltage glitch sampling rate.
+  *
+  */
+__STATIC_INLINE void TAMPER_VG_SAMPLE_SEL(uint32_t u32VGSampleRate)
+{
+    TAMPER->FUNEN &= ~0xF000000UL;
+
+    if(u32VGSampleRate == TAMPER_VG_192M_SAMPLE)
+    {
+        TAMPER->FUNEN |= TAMPER_FUNEN_VGCHEN0_Msk | TAMPER_FUNEN_VGCHEN1_Msk | TAMPER_FUNEN_VGCHEN2_Msk | TAMPER_FUNEN_VGCHEN3_Msk;
+    }
+}
+
+/**
+  * @brief      Enable to Trigger Key Store
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    Set KSTRIGEN bit of TAMPER TRIEN control register to trigger Key Store when Tamper event is detected.
+  *
+  */
+#define TAMPER_ENABLE_KS_TRIG()             ((uint32_t)(TAMPER->TRIEN |= TAMPER_TRIEN_KSTRIGEN_Msk))
+
+/**
+  * @brief      Disable to Trigger Key Store
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    Clear KSTRIGEN bit of TAMPER TRIEN control register to not trigger Key Store when Tamper event is detected.
+  *
+  */
+#define TAMPER_DISABLE_KS_TRIG()            ((uint32_t)(TAMPER->TRIEN &= (~TAMPER_TRIEN_KSTRIGEN_Msk)))
+
+/**
+  * @brief      Enable Wake-up Function
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    Set WAKEUPEN bit of TAMPER TRIEN control register to wake-up the system when Tamper event is detected.
+  *
+  */
+#define TAMPER_ENABLE_WAKEUP()              ((uint32_t)(TAMPER->TRIEN |= TAMPER_TRIEN_WAKEUPEN_Msk))
+
+/**
+  * @brief      Disable Wake-up Function
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    Clear WAKEUPEN bit of TAMPER TRIEN control register to not wake-up the system when Tamper event is detected.
+  *
+  */
+#define TAMPER_DISABLE_WAKEUP()             ((uint32_t)(TAMPER->TRIEN &= (~TAMPER_TRIEN_WAKEUPEN_Msk)))
+
+/**
+  * @brief      Enable to Clear Crypto Function
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    Set CRYPTOEN bit of TAMPER TRIEN control register to reset Crypto when Tamper event is detected.
+  *
+  */
+#define TAMPER_ENABLE_CRYPTO()              ((uint32_t)(TAMPER->TRIEN |= TAMPER_TRIEN_CRYPTOEN_Msk))
+
+/**
+  * @brief      Disable to Clear Crypto Function
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    Clear CRYPTOEN bit of TAMPER TRIEN control register to not reset Crypto when Tamper event is detected.
+  *
+  */
+#define TAMPER_DISABLE_CRYPTO()             ((uint32_t)(TAMPER->TRIEN &= (~TAMPER_TRIEN_CRYPTOEN_Msk)))
+
+/**
+  * @brief      Enable to Trigger Chip Reset
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    Set CHIPRSTEN bit of TAMPER TRIEN control register to reset the system when Tamper event is detected.
+  *
+  */
+#define TAMPER_ENABLE_CHIPRST()              ((uint32_t)(TAMPER->TRIEN |= TAMPER_TRIEN_CHIPRSTEN_Msk))
+
+/**
+  * @brief      Disable to Trigger Chip Reset
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    Clear CHIPRSTEN bit of TAMPER TRIEN control register to not reset the system when Tamper event is detected.
+  *
+  */
+#define TAMPER_DISABLE_CHIPRST()             ((uint32_t)(TAMPER->TRIEN &= (~TAMPER_TRIEN_CHIPRSTEN_Msk)))
+
+/**
+  * @brief      Enable to Clear RTC Spare Register
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    Set RTCSPCLREN bit of TAMPER TRIEN control register to reset RTC spare register when Tamper event is detected.
+  *
+  */
+#define TAMPER_ENABLE_RTCSPCLR()              ((uint32_t)(TAMPER->TRIEN |= TAMPER_TRIEN_RTCSPCLREN_Msk))
+
+/**
+  * @brief      Disable to Clear RTC Spare Register
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    Clear RTCSPCLREN bit of TAMPER TRIEN control register to not reset RTC spare register when Tamper event is detected.
+  *
+  */
+#define TAMPER_DISABLE_RTCSPCLR()             ((uint32_t)(TAMPER->TRIEN &= (~TAMPER_TRIEN_RTCSPCLREN_Msk)))
+
+/**
+  * @brief      Get Tamper Interrupt Flag
+  *
+  * @param      None
+  *
+  * @retval     0   Tamper event Interrupt did not occur
+  * @retval     1   Tamper event Interrupt occurred
+  *
+  * @details    This macro indicates Tamper event intertupt occurred or not.
+  *
+  */
+#define TAMPER_GET_INT_FLAG()      ((TAMPER->INTSTS & (0xAA7FAFFF))? 1:0)
+
+/**
+  * @brief      Clear Tamper Interrupt Status
+  *
+  * @param[in]  u32TamperFlag   Tamper event interrupt flag. It consists of:
+  *                             - \ref TAMPER_INTSTS_TAMP0IF_Msk
+  *                             - \ref TAMPER_INTSTS_TAMP1IF_Msk
+  *                             - \ref TAMPER_INTSTS_TAMP2IF_Msk
+  *                             - \ref TAMPER_INTSTS_TAMP3IF_Msk
+  *                             - \ref TAMPER_INTSTS_TAMP4IF_Msk
+  *                             - \ref TAMPER_INTSTS_TAMP5IF_Msk
+  *                             - \ref TAMPER_INTSTS_CLKFAILIF_Msk
+  *                             - \ref TAMPER_INTSTS_CLKSTOPIF_Msk
+  *                             - \ref TAMPER_INTSTS_OVPOUTIF_Msk
+  *                             - \ref TAMPER_INTSTS_VGPEVIF_Msk
+  *                             - \ref TAMPER_INTSTS_VGNEVIF_Msk
+  *                             - \ref TAMPER_INTSTS_ACTSEIF_Msk
+  *                             - \ref TAMPER_INTSTS_ACTST5IF_Msk
+  *                             - \ref TAMPER_INTSTS_ACTST25IF_Msk
+  *                             - \ref TAMPER_INTSTS_BODIF_Msk
+  *                             - \ref TAMPER_INTSTS_ACTST1IF_Msk
+  *                             - \ref TAMPER_INTSTS_ACTST3IF_Msk
+  *                             - \ref TAMPER_INTSTS_ACTST21IF_Msk
+  *                             - \ref TAMPER_INTSTS_ACTST23IF_Msk
+  *
+  * @return     None
+  *
+  * @details    This macro is used to clear Tamper event flag.
+  *
+  */
+#define TAMPER_CLR_INT_STATUS(u32TamperFlag)   (TAMPER->INTSTS = (u32TamperFlag))
+
+/**
+  * @brief      Get Tamper Interrupt Status
+  *
+  * @param      None
+  *
+  * @retval     TAMPER_INTSTS_TAMP0IF_Msk
+  * @retval     TAMPER_INTSTS_TAMP1IF_Msk
+  * @retval     TAMPER_INTSTS_TAMP2IF_Msk
+  * @retval     TAMPER_INTSTS_TAMP3IF_Msk
+  * @retval     TAMPER_INTSTS_TAMP4IF_Msk
+  * @retval     TAMPER_INTSTS_TAMP5IF_Msk
+  * @retval     TAMPER_INTSTS_CLKFAILIF_Msk
+  * @retval     TAMPER_INTSTS_CLKSTOPIF_Msk
+  * @retval     TAMPER_INTSTS_OVPOUTIF_Msk
+  * @retval     TAMPER_INTSTS_VGPEVIF_Msk
+  * @retval     TAMPER_INTSTS_VGNEVIF_Msk
+  * @retval     TAMPER_INTSTS_ACTSEFIF_Msk
+  * @retval     TAMPER_INTSTS_ACTST5IF_Msk
+  * @retval     TAMPER_INTSTS_ACTST25IF_Msk
+  * @retval     TAMPER_INTSTS_RTCLVRIF_Msk
+  * @retval     TAMPER_INTSTS_RIOTRIGIF_Msk
+  * @retval     TAMPER_INTSTS_RCLKTRIGIF_Msk
+  * @retval     TAMPER_INTSTS_BODIF_Msk
+  * @retval     TAMPER_INTSTS_ACTST1IF_Msk
+  * @retval     TAMPER_INTSTS_ACTST3IF_Msk
+  * @retval     TAMPER_INTSTS_ACTST21IF_Msk
+  * @retval     TAMPER_INTSTS_ACTST23IF_Msk
+  *
+  * @details    This macro indicates Tamper event status.
+  *
+  */
+#define TAMPER_GET_INT_STATUS()    ((TAMPER->INTSTS & (0xAA7FAFFF)))
+
+void TAMPER_EnableInt(uint32_t u32IntFlagMask);
+void TAMPER_DisableInt(uint32_t u32IntFlagMask);
+void TAMPER_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn);
+void TAMPER_StaticTamperDisable(uint32_t u32TamperSelect);
+void TAMPER_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32_t u32Pair1Source, uint32_t u32Pair2Source);
+void TAMPER_DynamicTamperDisable(uint32_t u32PairSel);
+void TAMPER_DynamicTamperConfig(uint32_t u32ChangeRate, uint32_t u32SeedReload, uint32_t u32RefPattern, uint32_t u32Seed);
+void TAMPER_ActiveShieldDynamicTamperEnable(uint32_t u32PairSel1, uint32_t u32Pair1Source1, uint32_t u32PairSel2, uint32_t u32Pair1Source2);
+void TAMPER_ActiveShieldDynamicTamperDisable(uint32_t u32PairSel1, uint32_t u32PairSe2);
+void TAMPER_ActiveShieldDynamicTamperConfig(uint32_t u32ChangeRate1, uint32_t u32SeedReload1, uint32_t u32RefPattern1, uint32_t u32Seed,
+        uint32_t u32ChangeRate2, uint32_t u32SeedReload2, uint32_t u32RefPattern2, uint32_t u32Seed2);
+
+
+/**@}*/ /* end of group TAMPER_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group TAMPER_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_TAMPER_H__ */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_timer.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_timer.h
new file mode 100644
index 0000000000..21bd179d7e
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_timer.h
@@ -0,0 +1,541 @@
+/**************************************************************************//**
+ * @file     nu_timer.h
+ * @version  V3.00
+ * @brief    Timer Controller(Timer) driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_TIMER_H__
+#define __NU_TIMER_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup TIMER_Driver TIMER Driver
+  @{
+*/
+
+/** @addtogroup TIMER_EXPORTED_CONSTANTS TIMER Exported Constants
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/*  TIMER Operation Mode, External Counter and Capture Mode Constant Definitions                           */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TIMER_ONESHOT_MODE                      (0UL << TIMER_CTL_OPMODE_Pos)      /*!< Timer working in one-shot mode \hideinitializer */
+#define TIMER_PERIODIC_MODE                     (1UL << TIMER_CTL_OPMODE_Pos)      /*!< Timer working in periodic mode \hideinitializer */
+#define TIMER_TOGGLE_MODE                       (2UL << TIMER_CTL_OPMODE_Pos)      /*!< Timer working in toggle-output mode \hideinitializer */
+#define TIMER_CONTINUOUS_MODE                   (3UL << TIMER_CTL_OPMODE_Pos)      /*!< Timer working in continuous counting mode \hideinitializer */
+#define TIMER_TOUT_PIN_FROM_TMX                 (0UL << TIMER_CTL_TGLPINSEL_Pos)   /*!< Timer toggle-output pin is from TMx pin \hideinitializer */
+#define TIMER_TOUT_PIN_FROM_TMX_EXT             (1UL << TIMER_CTL_TGLPINSEL_Pos)   /*!< Timer toggle-output pin is from TMx_EXT pin \hideinitializer */
+
+#define TIMER_COUNTER_EVENT_FALLING             (0UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on falling edge detection \hideinitializer */
+#define TIMER_COUNTER_EVENT_RISING              (1UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on rising edge detection \hideinitializer */
+#define TIMER_CAPTURE_FREE_COUNTING_MODE        (0UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to get timer counter value \hideinitializer */
+#define TIMER_CAPTURE_COUNTER_RESET_MODE        (1UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to reset timer counter \hideinitializer */
+
+#define TIMER_CAPTURE_EVENT_FALLING             (0UL << TIMER_EXTCTL_CAPEDGE_Pos)  /*!< Falling edge detection to trigger capture event \hideinitializer */
+#define TIMER_CAPTURE_EVENT_RISING              (1UL << TIMER_EXTCTL_CAPEDGE_Pos)  /*!< Rising edge detection to trigger capture event \hideinitializer */
+#define TIMER_CAPTURE_EVENT_FALLING_RISING      (2UL << TIMER_EXTCTL_CAPEDGE_Pos)  /*!< Both falling and rising edge detection to trigger capture event, and first event at falling edge \hideinitializer */
+#define TIMER_CAPTURE_EVENT_RISING_FALLING      (3UL << TIMER_EXTCTL_CAPEDGE_Pos)  /*!< Both rising and falling edge detection to trigger capture event, and first event at rising edge \hideinitializer */
+#define TIMER_CAPTURE_EVENT_GET_LOW_PERIOD      (6UL << TIMER_EXTCTL_CAPEDGE_Pos)  /*!< First capture event is at falling edge, follows are at at rising edge \hideinitializer */
+#define TIMER_CAPTURE_EVENT_GET_HIGH_PERIOD     (7UL << TIMER_EXTCTL_CAPEDGE_Pos)  /*!< First capture event is at rising edge, follows are at at falling edge \hideinitializer */
+
+#define TIMER_CAPTURE_SOURCE_FROM_PIN           (0UL << TIMER_CTL_CAPSRC_Pos) /*!< The capture source is from TMx_EXT pin \hideinitializer */
+#define TIMER_CAPTURE_SOURCE_FROM_INTERNAL      (1UL << TIMER_CTL_CAPSRC_Pos) /*!< The capture source is from internal ACMPx signal or clock source \hideinitializer */
+
+#define TIMER_CAPTURE_SOURCE_DIV_1              (0UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 1 \hideinitializer */
+#define TIMER_CAPTURE_SOURCE_DIV_2              (1UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 2 \hideinitializer */
+#define TIMER_CAPTURE_SOURCE_DIV_4              (2UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 4 \hideinitializer */
+#define TIMER_CAPTURE_SOURCE_DIV_8              (3UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 8 \hideinitializer */
+#define TIMER_CAPTURE_SOURCE_DIV_16             (4UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 16 \hideinitializer */
+#define TIMER_CAPTURE_SOURCE_DIV_32             (5UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 32 \hideinitializer */
+#define TIMER_CAPTURE_SOURCE_DIV_64             (6UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 64 \hideinitializer */
+#define TIMER_CAPTURE_SOURCE_DIV_128            (7UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 128 \hideinitializer */
+#define TIMER_CAPTURE_SOURCE_DIV_256            (8UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 256 \hideinitializer */
+
+#define TIMER_INTER_CAPTURE_SOURCE_ACMP0        (0UL << TIMER_EXTCTL_INTERCAPSEL_Pos) /*!< Capture source from internal ACMP0 output signal \hideinitializer */
+#define TIMER_INTER_CAPTURE_SOURCE_ACMP1        (1UL << TIMER_EXTCTL_INTERCAPSEL_Pos) /*!< Capture source from internal ACMP1 output signal \hideinitializer */
+#define TIMER_INTER_CAPTURE_SOURCE_HXT          (2UL << TIMER_EXTCTL_INTERCAPSEL_Pos) /*!< Capture source from HXT \hideinitializer */
+#define TIMER_INTER_CAPTURE_SOURCE_LXT          (3UL << TIMER_EXTCTL_INTERCAPSEL_Pos) /*!< Capture source from LXT \hideinitializer */
+#define TIMER_INTER_CAPTURE_SOURCE_HIRC         (4UL << TIMER_EXTCTL_INTERCAPSEL_Pos) /*!< Capture source from HIRC \hideinitializer */
+#define TIMER_INTER_CAPTURE_SOURCE_LIRC         (5UL << TIMER_EXTCTL_INTERCAPSEL_Pos) /*!< Capture source from LIRC \hideinitializer */
+#define TIMER_INTER_CAPTURE_SOURCE_MIRC         (6UL << TIMER_EXTCTL_INTERCAPSEL_Pos) /*!< Capture source from MIRC. Only available on TIMER4 and TIMER5 \hideinitializer */
+
+#define TIMER_TRGSRC_TIMEOUT_EVENT              (0UL << TIMER_TRGCTL_TRGSSEL_Pos) /*!< Select internal trigger source from timer time-out event \hideinitializer */
+#define TIMER_TRGSRC_CAPTURE_EVENT              (1UL << TIMER_TRGCTL_TRGSSEL_Pos) /*!< Select internal trigger source from timer capture event \hideinitializer */
+#define TIMER_TRG_TO_PWM                        (TIMER_TRGCTL_TRGPWM_Msk)         /*!< Each timer event as EPWM and BPWM counter clock source. NOT supported on TIMER4 and TIMER5 \hideinitializer */
+#define TIMER_TRG_TO_EADC                       (TIMER_TRGCTL_TRGEADC_Msk)        /*!< Each timer event to start ADC conversion \hideinitializer */
+#define TIMER_TRG_TO_DAC                        (TIMER_TRGCTL_TRGDAC_Msk)         /*!< Each timer event to start DAC conversion. NOT supported on TIMER4 and TIMER5 \hideinitializer */
+#define TIMER_TRG_TO_PDMA                       (TIMER_TRGCTL_TRGPDMA_Msk)        /*!< Each timer event to trigger PDMA transfer \hideinitializer */
+
+/**@}*/ /* end of group TIMER_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Set Timer Compared Value
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  * @param[in]  u32Value    Timer compare value. Valid values are between 2 to 0xFFFFFF.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set timer compared value to adjust timer time-out interval.
+  * @note       1. Never write 0x0 or 0x1 in this field, or the core will run into unknown state. \n
+  *             2. If update timer compared value in continuous counting mode, timer counter value will keep counting continuously. \n
+  *                But if timer is operating at other modes, the timer up counter will restart counting and start from 0.
+  * \hideinitializer
+  */
+#define TIMER_SET_CMP_VALUE(timer, u32Value)        ((timer)->CMP = (u32Value))
+
+/**
+  * @brief      Set Timer Prescale Value
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  * @param[in]  u32Value    Timer prescale value. Valid values are between 0 to 0xFF.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set timer prescale value and timer source clock will be divided by (prescale + 1) \n
+  *             before it is fed into timer.
+  * \hideinitializer
+  */
+#define TIMER_SET_PRESCALE_VALUE(timer, u32Value)   ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_PSC_Msk) | (u32Value))
+
+/**
+  * @brief      Check specify Timer Status
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @retval     0   Timer 24-bit up counter is inactive
+  * @retval     1   Timer 24-bit up counter is active
+  *
+  * @details    This macro is used to check if specify Timer counter is inactive or active.
+  * \hideinitializer
+  */
+#define TIMER_IS_ACTIVE(timer)                      ((((timer)->CTL & TIMER_CTL_ACTSTS_Msk) == TIMER_CTL_ACTSTS_Msk)? 1 : 0)
+
+/**
+  * @brief      Select Toggle-output Pin
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  * @param[in]  u32ToutSel  Toggle-output pin selection, valid values are:
+  *                         - \ref TIMER_TOUT_PIN_FROM_TMX
+  *                         - \ref TIMER_TOUT_PIN_FROM_TMX_EXT
+  *
+  * @return     None
+  *
+  * @details    This macro is used to select timer toggle-output pin is output on TMx or TMx_EXT pin.
+  * \hideinitializer
+  */
+#define TIMER_SELECT_TOUT_PIN(timer, u32ToutSel)    ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_TGLPINSEL_Msk) | (u32ToutSel))
+
+/**
+  * @brief      Set Timer Operating Mode
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  * @param[in]  u32OpMode   Operation mode. Possible options are
+  *                         - \ref TIMER_ONESHOT_MODE
+  *                         - \ref TIMER_PERIODIC_MODE
+  *                         - \ref TIMER_TOGGLE_MODE
+  *                         - \ref TIMER_CONTINUOUS_MODE
+  *
+  * @return     None
+  * \hideinitializer
+  */
+#define TIMER_SET_OPMODE(timer, u32OpMode)   ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_OPMODE_Msk) | (u32OpMode))
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* static inline functions                                                                                 */
+/*---------------------------------------------------------------------------------------------------------*/
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
+__STATIC_INLINE void TIMER_Start(TIMER_T *timer);
+__STATIC_INLINE void TIMER_Stop(TIMER_T *timer);
+__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer);
+__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer);
+__STATIC_INLINE void TIMER_StartCapture(TIMER_T *timer);
+__STATIC_INLINE void TIMER_StopCapture(TIMER_T *timer);
+__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer);
+__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer);
+__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer);
+__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer);
+__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer);
+__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer);
+__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer);
+__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer);
+__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer);
+__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer);
+__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer);
+__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer);
+__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer);
+__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer);
+__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer);
+__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer);
+__STATIC_INLINE void TIMER_ResetCounter(TIMER_T *timer);
+
+
+/**
+  * @brief      Start Timer Counting
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This function is used to start Timer counting.
+  */
+__STATIC_INLINE void TIMER_Start(TIMER_T *timer)
+{
+    timer->CTL |= TIMER_CTL_CNTEN_Msk;
+}
+
+/**
+  * @brief      Stop Timer Counting
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This function is used to stop/suspend Timer counting.
+  */
+__STATIC_INLINE void TIMER_Stop(TIMER_T *timer)
+{
+    timer->CTL &= ~TIMER_CTL_CNTEN_Msk;
+}
+
+/**
+  * @brief      Enable Timer Interrupt Wake-up Function
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable the timer interrupt wake-up function and interrupt source could be time-out interrupt, \n
+  *             counter event interrupt or capture trigger interrupt.
+  * @note       To wake the system from Power-down mode, timer clock source must be ether LXT or LIRC.
+  */
+__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer)
+{
+    timer->CTL |= TIMER_CTL_WKEN_Msk;
+}
+
+/**
+  * @brief      Disable Timer Wake-up Function
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This function is used to disable the timer interrupt wake-up function.
+  */
+__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer)
+{
+    timer->CTL &= ~TIMER_CTL_WKEN_Msk;
+}
+
+/**
+  * @brief      Start Timer Capture Function
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This function is used to start Timer capture function.
+  */
+__STATIC_INLINE void TIMER_StartCapture(TIMER_T *timer)
+{
+    timer->EXTCTL |= TIMER_EXTCTL_CAPEN_Msk;
+}
+
+/**
+  * @brief      Stop Timer Capture Function
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This function is used to stop Timer capture function.
+  */
+__STATIC_INLINE void TIMER_StopCapture(TIMER_T *timer)
+{
+    timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk;
+}
+
+/**
+  * @brief      Enable Capture Pin De-bounce
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable the detect de-bounce function of capture pin.
+  */
+__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer)
+{
+    timer->EXTCTL |= TIMER_EXTCTL_CAPDBEN_Msk;
+}
+
+/**
+  * @brief      Disable Capture Pin De-bounce
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This function is used to disable the detect de-bounce function of capture pin.
+  */
+__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer)
+{
+    timer->EXTCTL &= ~TIMER_EXTCTL_CAPDBEN_Msk;
+}
+
+/**
+  * @brief      Enable Counter Pin De-bounce
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable the detect de-bounce function of counter pin.
+  */
+__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer)
+{
+    timer->EXTCTL |= TIMER_EXTCTL_CNTDBEN_Msk;
+}
+
+/**
+  * @brief      Disable Counter Pin De-bounce
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This function is used to disable the detect de-bounce function of counter pin.
+  */
+__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer)
+{
+    timer->EXTCTL &= ~TIMER_EXTCTL_CNTDBEN_Msk;
+}
+
+/**
+  * @brief      Enable Timer Time-out Interrupt
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable the timer time-out interrupt function.
+  */
+__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer)
+{
+    timer->CTL |= TIMER_CTL_INTEN_Msk;
+}
+
+/**
+  * @brief      Disable Timer Time-out Interrupt
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This function is used to disable the timer time-out interrupt function.
+  */
+__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer)
+{
+    timer->CTL &= ~TIMER_CTL_INTEN_Msk;
+}
+
+/**
+  * @brief      Enable Capture Trigger Interrupt
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable the timer capture trigger interrupt function.
+  */
+__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer)
+{
+    timer->EXTCTL |= TIMER_EXTCTL_CAPIEN_Msk;
+}
+
+/**
+  * @brief      Disable Capture Trigger Interrupt
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This function is used to disable the timer capture trigger interrupt function.
+  */
+__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer)
+{
+    timer->EXTCTL &= ~TIMER_EXTCTL_CAPIEN_Msk;
+}
+
+/**
+  * @brief      Get Timer Time-out Interrupt Flag
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @retval     0   Timer time-out interrupt did not occur
+  * @retval     1   Timer time-out interrupt occurred
+  *
+  * @details    This function indicates timer time-out interrupt occurred or not.
+  */
+__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer)
+{
+    return (((timer->INTSTS & TIMER_INTSTS_TIF_Msk) == TIMER_INTSTS_TIF_Msk) ? 1UL : 0UL);
+}
+
+/**
+  * @brief      Clear Timer Time-out Interrupt Flag
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This function clears timer time-out interrupt flag to 0.
+  */
+__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer)
+{
+    timer->INTSTS = TIMER_INTSTS_TIF_Msk;
+}
+
+/**
+  * @brief      Get Timer Capture Interrupt Flag
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @retval     0   Timer capture interrupt did not occur
+  * @retval     1   Timer capture interrupt occurred
+  *
+  * @details    This function indicates timer capture trigger interrupt occurred or not.
+  */
+__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer)
+{
+    return timer->EINTSTS;
+}
+
+/**
+  * @brief      Clear Timer Capture Interrupt Flag
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This function clears timer capture trigger interrupt flag to 0.
+  */
+__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer)
+{
+    timer->EINTSTS = TIMER_EINTSTS_CAPIF_Msk;
+}
+
+/**
+  * @brief      Get Timer Wake-up Flag
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @retval     0   Timer does not cause CPU wake-up
+  * @retval     1   Timer interrupt event cause CPU wake-up
+  *
+  * @details    This function indicates timer interrupt event has waked up system or not.
+  */
+__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer)
+{
+    return (((timer->INTSTS & TIMER_INTSTS_TWKF_Msk) == TIMER_INTSTS_TWKF_Msk) ? 1UL : 0UL);
+}
+
+/**
+  * @brief      Clear Timer Wake-up Flag
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This function clears the timer wake-up system flag to 0.
+  */
+__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer)
+{
+    timer->INTSTS = TIMER_INTSTS_TWKF_Msk;
+}
+
+/**
+  * @brief      Get Capture value
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     24-bit Capture Value
+  *
+  * @details    This function reports the current 24-bit timer capture value.
+  */
+__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer)
+{
+    return timer->CAP;
+}
+
+/**
+  * @brief      Get Counter value
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     24-bit Counter Value
+  *
+  * @details    This function reports the current 24-bit timer counter value.
+  */
+__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer)
+{
+    return timer->CNT;
+}
+
+/**
+  * @brief      Reset Counter
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This function is used to reset current counter value and internal prescale counter value.
+  */
+__STATIC_INLINE void TIMER_ResetCounter(TIMER_T *timer)
+{
+    timer->CNT = 0UL;
+    while((timer->CNT & TIMER_CNT_RSTACT_Msk) == TIMER_CNT_RSTACT_Msk) {}
+}
+
+
+uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq);
+void TIMER_Close(TIMER_T *timer);
+void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec);
+void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge);
+void TIMER_DisableCapture(TIMER_T *timer);
+void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge);
+void TIMER_DisableEventCounter(TIMER_T *timer);
+uint32_t TIMER_GetModuleClock(TIMER_T *timer);
+void TIMER_EnableFreqCounter(TIMER_T *timer, uint32_t u32DropCount, uint32_t u32Timeout, uint32_t u32EnableInt);
+void TIMER_DisableFreqCounter(TIMER_T *timer);
+void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src);
+void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask);
+
+/**@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group TIMER_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_TIMER_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_timer_pwm.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_timer_pwm.h
new file mode 100644
index 0000000000..5627fb9851
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_timer_pwm.h
@@ -0,0 +1,877 @@
+/**************************************************************************//**
+ * @file     timer.h
+ * @version  V3.00
+ * @brief    Timer PWM Controller(Timer PWM) driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_TIMER_PWM_H__
+#define __NU_TIMER_PWM_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup TIMER_PWM_Driver TIMER PWM Driver
+  @{
+*/
+
+/** @addtogroup TIMER_PWM_EXPORTED_CONSTANTS TIMER PWM Exported Constants
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Output Channel Constant Definitions                                                                    */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_CH0                                (BIT0)       /*!< Indicate PWMx_CH0 \hideinitializer */
+#define TPWM_CH1                                (BIT1)       /*!< Indicate PWMx_CH1 \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Counter Type Constant Definitions                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_UP_COUNT                           (0UL << TIMER_PWMCTL_CNTTYPE_Pos)       /*!< Up count type \hideinitializer */
+#define TPWM_DOWN_COUNT                         (1UL << TIMER_PWMCTL_CNTTYPE_Pos)       /*!< Down count type \hideinitializer */
+#define TPWM_UP_DOWN_COUNT                      (2UL << TIMER_PWMCTL_CNTTYPE_Pos)       /*!< Up-Down count type \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Counter Mode Constant Definitions                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_AUTO_RELOAD_MODE                   (0UL)                            /*!< Auto-reload mode \hideinitializer */
+#define TPWM_ONE_SHOT_MODE                      (TIMER_PWMCTL_CNTMODE_Msk)       /*!< One-shot mode \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Output Level Constant Definitions                                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_OUTPUT_TOGGLE                      (0UL)      /*!< Timer PWM output toggle \hideinitializer */
+#define TPWM_OUTPUT_NOTHING                     (1UL)      /*!< Timer PWM output nothing \hideinitializer */
+#define TPWM_OUTPUT_LOW                         (2UL)      /*!< Timer PWM output low \hideinitializer */
+#define TPWM_OUTPUT_HIGH                        (3UL)      /*!< Timer PWM output high \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Trigger Event Source Select Constant Definitions                                                       */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_TRIGGER_EVENT_AT_ZERO_POINT                    (0UL << TIMER_PWMTRGCTL_TRGSEL_Pos)     /*!< Timer PWM trigger event while counter zero point event occurred \hideinitializer */
+#define TPWM_TRIGGER_EVENT_AT_PERIOD_POINT                  (1UL << TIMER_PWMTRGCTL_TRGSEL_Pos)     /*!< Timer PWM trigger event while counter period point event occurred \hideinitializer */
+#define TPWM_TRIGGER_EVENT_AT_ZERO_OR_PERIOD_POINT          (2UL << TIMER_PWMTRGCTL_TRGSEL_Pos)     /*!< Timer PWM trigger event while counter zero or period point event occurred \hideinitializer */
+#define TPWM_TRIGGER_EVENT_AT_COMPARE_UP_POINT              (3UL << TIMER_PWMTRGCTL_TRGSEL_Pos)     /*!< Timer PWM trigger event while counter up count compare point event occurred \hideinitializer */
+#define TPWM_TRIGGER_EVENT_AT_COMPARE_DOWN_POINT            (4UL << TIMER_PWMTRGCTL_TRGSEL_Pos)     /*!< Timer PWM trigger event while counter down count compare point event occurred \hideinitializer */
+#define TPWM_TRIGGER_EVENT_AT_PERIOD_OR_COMPARE_UP_POINT    (5UL << TIMER_PWMTRGCTL_TRGSEL_Pos)     /*!< Timer PWM trigger event while counter period or up count compare point event occurred \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Brake Control Constant Definitions                                                                     */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_BRAKE_SOURCE_EDGE_ACMP0            (TIMER_PWMBRKCTL_CPO0EBEN_Msk) /*!< Comparator 0 as edge-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_EDGE_ACMP1            (TIMER_PWMBRKCTL_CPO1EBEN_Msk) /*!< Comparator 1 as edge-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_EDGE_BKPIN            (TIMER_PWMBRKCTL_BRKPEEN_Msk)  /*!< Brake pin as edge-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_EDGE_SYS_CSS          (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_CSSBRKEN_Msk << 16))    /*!< System fail condition: clock security system detection as edge-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_EDGE_SYS_BOD          (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_BODBRKEN_Msk << 16))    /*!< System fail condition: brown-out detection as edge-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_EDGE_SYS_COR          (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_CORBRKEN_Msk << 16))    /*!< System fail condition: core lockup detection as edge-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_EDGE_SYS_RAM          (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_RAMBRKEN_Msk << 16))    /*!< System fail condition: SRAM parity error detection as edge-detect fault brake source \hideinitializer */
+
+#define TPWM_BRAKE_SOURCE_LEVEL_ACMP0           (TIMER_PWMBRKCTL_CPO0LBEN_Msk)  /*!< Comparator 0 as level-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_LEVEL_ACMP1           (TIMER_PWMBRKCTL_CPO1LBEN_Msk)  /*!< Comparator 1 as level-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_LEVEL_BKPIN           (TIMER_PWMBRKCTL_BRKPLEN_Msk)   /*!< Brake pin as level-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_LEVEL_SYS_CSS         (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_CSSBRKEN_Msk << 16))    /*!< System fail condition: clock security system detection as level-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_LEVEL_SYS_BOD         (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_BODBRKEN_Msk << 16))    /*!< System fail condition: brown-out detection as level-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_LEVEL_SYS_COR         (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_CORBRKEN_Msk << 16))    /*!< System fail condition: core lockup detection as level-detect fault brake source \hideinitializer */
+#define TPWM_BRAKE_SOURCE_LEVEL_SYS_RAM         (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_RAMBRKEN_Msk << 16))    /*!< System fail condition: SRAM parity error detection as level-detect fault brake source \hideinitializer */
+
+#define TPWM_BRAKE_EDGE                         (TIMER_PWMSWBRK_BRKETRG_Msk)    /*!< Edge-detect fault brake \hideinitializer */
+#define TPWM_BRAKE_LEVEL                        (TIMER_PWMSWBRK_BRKLTRG_Msk)    /*!< Level-detect fault brake \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Load Mode Constant Definitions                                                                         */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_LOAD_MODE_PERIOD                   (0UL)                       /*!< Timer PWM period load mode \hideinitializer */
+#define TPWM_LOAD_MODE_IMMEDIATE                (TIMER_PWMCTL_IMMLDEN_Msk)  /*!< Timer PWM immediately load mode \hideinitializer */
+#define TPWM_LOAD_MODE_CENTER                   (TIMER_PWMCTL_CTRLD_Msk)    /*!< Timer PWM center load mode \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Brake Pin De-bounce Clock Source Select Constant Definitions                                           */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_BKP_DBCLK_PCLK_DIV_1               (0UL)    /*!< De-bounce clock is PCLK divide by 1 \hideinitializer */
+#define TPWM_BKP_DBCLK_PCLK_DIV_2               (1UL)    /*!< De-bounce clock is PCLK divide by 2 \hideinitializer */
+#define TPWM_BKP_DBCLK_PCLK_DIV_4               (2UL)    /*!< De-bounce clock is PCLK divide by 4 \hideinitializer */
+#define TPWM_BKP_DBCLK_PCLK_DIV_8               (3UL)    /*!< De-bounce clock is PCLK divide by 8 \hideinitializer */
+#define TPWM_BKP_DBCLK_PCLK_DIV_16              (4UL)    /*!< De-bounce clock is PCLK divide by 16 \hideinitializer */
+#define TPWM_BKP_DBCLK_PCLK_DIV_32              (5UL)    /*!< De-bounce clock is PCLK divide by 32 \hideinitializer */
+#define TPWM_BKP_DBCLK_PCLK_DIV_64              (6UL)    /*!< De-bounce clock is PCLK divide by 64 \hideinitializer */
+#define TPWM_BKP_DBCLK_PCLK_DIV_128             (7UL)    /*!< De-bounce clock is PCLK divide by 128 \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Brake Pin Source Select Constant Definitions                                                           */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_TM_BRAKE0                          (0UL)    /*!< Brake pin source comes from TM_BRAKE0 \hideinitializer */
+#define TPWM_TM_BRAKE1                          (1UL)    /*!< Brake pin source comes from TM_BRAKE1 \hideinitializer */
+#define TPWM_TM_BRAKE2                          (2UL)    /*!< Brake pin source comes from TM_BRAKE2 \hideinitializer */
+#define TPWM_TM_BRAKE3                          (3UL)    /*!< Brake pin source comes from TM_BRAKE3 \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Counter Clock Source Select Constant Definitions                                                       */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_CNTR_CLKSRC_TMR_CLK                (0UL)    /*!< Timer PWM Clock source selects to TMR_CLK \hideinitializer */
+#define TPWM_CNTR_CLKSRC_TIMER0_INT             (1UL)    /*!< Timer PWM Clock source selects to TIMER0 interrupt event \hideinitializer */
+#define TPWM_CNTR_CLKSRC_TIMER1_INT             (2UL)    /*!< Timer PWM Clock source selects to TIMER1 interrupt event \hideinitializer */
+#define TPWM_CNTR_CLKSRC_TIMER2_INT             (3UL)    /*!< Timer PWM Clock source selects to TIMER2 interrupt event \hideinitializer */
+#define TPWM_CNTR_CLKSRC_TIMER3_INT             (4UL)    /*!< Timer PWM Clock source selects to TIMER3 interrupt event \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  Counter Synchronous Mode Constant Definitions                                                          */
+/*---------------------------------------------------------------------------------------------------------*/
+#define TPWM_CNTR_SYNC_DISABLE                  (0UL)    /*!< Disable TIMER PWM synchronous function \hideinitializer */
+#define TPWM_CNTR_SYNC_START_BY_TIMER0          ((0<PWMCTL) & TMR45_BASE) == TMR45_BASE) { \
+            (timer)->CTL |= TIMER_CTL_FUNCSEL_Msk; \
+            while(((timer)->CTL & TIMER_CTL_FUNCSEL_Msk) == 0) {} \
+        } else { \
+            (timer)->ALTCTL = TIMER_ALTCTL_FUNCSEL_Msk; \
+            while(((timer)->ALTCTL & TIMER_ALTCTL_FUNCSEL_Msk) == 0) {} \
+        } \
+    }while(0)
+
+/**
+  * @brief      Disable PWM Counter Mode
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to disable specified Timer channel as PWM counter mode, then timer counter mode is available.
+  * @note       All registers about PWM counter function will be cleared to 0 after executing this macro.
+  * \hideinitializer
+  */
+#define TPWM_DISABLE_PWM_MODE(timer) \
+    do{ \
+        if(((uint32_t)&((timer)->PWMCTL) & TMR45_BASE) == TMR45_BASE) { \
+            (timer)->CTL &= ~TIMER_CTL_FUNCSEL_Msk; \
+            while(((timer)->CTL & TIMER_CTL_FUNCSEL_Msk) == TIMER_CTL_FUNCSEL_Msk) {} \
+        } else { \
+            (timer)->ALTCTL &= ~TIMER_ALTCTL_FUNCSEL_Msk; \
+            while(((timer)->ALTCTL & TIMER_ALTCTL_FUNCSEL_Msk) == TIMER_ALTCTL_FUNCSEL_Msk) {} \
+        } \
+    }while(0)
+
+
+/**
+  * @brief      Enable Independent Mode
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to enable independent mode of TIMER PWM module and complementary mode will be disabled.
+  * @note       NOT available on TIMER4 and TIMER5.
+  * \hideinitializer
+  */
+#define TPWM_ENABLE_INDEPENDENT_MODE(timer)     ((timer)->PWMCTL &= ~(1ul << TIMER_PWMCTL_OUTMODE_Pos))
+
+/**
+  * @brief      Enable Complementary Mode
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to enable complementary mode of Timer PWM module and independent mode will be disabled.
+  * @note       NOT available on TIMER4 and TIMER5.
+  * \hideinitializer
+  */
+#define TPWM_ENABLE_COMPLEMENTARY_MODE(timer)   ((timer)->PWMCTL |= (1 << TIMER_PWMCTL_OUTMODE_Pos))
+
+/**
+  * @brief      Set Counter Type
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  type        Timer PWM count type, could be one of the following type
+  *                             - \ref TPWM_UP_COUNT
+  *                             - \ref TPWM_DOWN_COUNT
+  *                             - \ref TPWM_UP_DOWN_COUNT
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set Timer PWM counter type.
+  * @note       NOT available on TIMER4 and TIMER5. Both TIMER4 and TIMER5 are only support count up.
+  * \hideinitializer
+  */
+#define TPWM_SET_COUNTER_TYPE(timer, type)      ((timer)->PWMCTL = ((timer)->PWMCTL & ~TIMER_PWMCTL_CNTTYPE_Msk) | (type))
+
+/**
+  * @brief      Start PWM Counter
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to enable PWM generator and start counter counting.
+  * \hideinitializer
+  */
+#define TPWM_START_COUNTER(timer)               ((timer)->PWMCTL |= TIMER_PWMCTL_CNTEN_Msk)
+
+/**
+  * @brief      Stop PWM Counter
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to stop PWM counter after current period is completed.
+  * \hideinitializer
+  */
+#define TPWM_STOP_COUNTER(timer)                ((timer)->PWMPERIOD = 0x0)
+
+/**
+  * @brief      Set Counter Clock Prescaler
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @param[in]  prescaler   Clock prescaler of specified channel.
+  *                         Valid values are between 0x0~0xFFF for TIMER0, TIMER1, TIMER2, TIMER3, and
+  *                         valid values are between 0x0~0xFF for TIMER4 and TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set the prescaler of specified TIMER PWM.
+  * @note       If prescaler is 0, then there is no scaling in counter clock source.
+  * \hideinitializer
+  */
+#define TPWM_SET_PRESCALER(timer, prescaler)    ((timer)->PWMCLKPSC = (prescaler))
+
+/**
+  * @brief      Get Counter Clock Prescaler
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     Target prescaler setting, CLKPSC (TIMERx_PWMCLKPSC[11:0])
+  *
+  * @details    Get the prescaler setting, the target counter clock divider is (CLKPSC + 1).
+  * \hideinitializer
+  */
+#define TPWM_GET_PRESCALER(timer)               ((timer)->PWMCLKPSC)
+
+/**
+  * @brief      Set Couner Period
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @param[in]  period      Period of specified channel. Valid values are between 0x0~0xFFFF.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set the period of specified TIMER PWM.
+  * \hideinitializer
+  */
+#define TPWM_SET_PERIOD(timer, period)          ((timer)->PWMPERIOD = (period))
+
+/**
+  * @brief      Get Couner Period
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     Target period setting, PERIOD (TIMERx_PWMPERIOD[15:0])
+  *
+  * @details    This macro is used to get the period of specified TIMER PWM.
+  * \hideinitializer
+  */
+#define TPWM_GET_PERIOD(timer)                  ((timer)->PWMPERIOD)
+
+/**
+  * @brief      Set Comparator Value
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @param[in]  cmp     Comparator of specified channel. Valid values are between 0x0~0xFFFF.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set the comparator value of specified TIMER PWM.
+  * \hideinitializer
+  */
+#define TPWM_SET_CMPDAT(timer, cmp)             ((timer)->PWMCMPDAT = (cmp))
+
+/**
+  * @brief      Get Comparator Value
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     Target comparator setting, CMPDAT (TIMERx_PWMCMPDAT[15:0])
+  *
+  * @details    This macro is used to get the comparator value of specified TIMER PWM.
+  * \hideinitializer
+  */
+#define TPWM_GET_CMPDAT(timer)                  ((timer)->PWMCMPDAT)
+
+/**
+  * @brief      Clear Counter
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to clear counter of specified TIMER PWM.
+  * \hideinitializer
+  */
+#define TPWM_CLEAR_COUNTER(timer)               ((timer)->PWMCNTCLR = TIMER_PWMCNTCLR_CNTCLR_Msk)
+
+/**
+  * @brief      Software Trigger Brake Event
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @param[in]  type        Type of brake trigger. Valid values are:
+  *                             - \ref TPWM_BRAKE_EDGE
+  *                             - \ref TPWM_BRAKE_LEVEL
+  *
+  * @return     None
+  *
+  * @details    This macro is used to trigger brake event by writing PWMSWBRK register.
+  * @note       NOT available on TIMER4 and TIMER5.
+  * \hideinitializer
+  */
+#define TPWM_SW_TRIGGER_BRAKE(timer, type)      ((timer)->PWMSWBRK = (type))
+
+/**
+  * @brief      Enable Output Function
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @param[in]  ch          Enable specified channel output function. Valid values are:
+  *                         For TIMER0 ~ TIMER3, the valid value could be a combination of \ref TPWM_CH0 and \ref TPWM_CH1.
+  *                         For TIMER4, TIMER5, the valid value could be \ref TPWM_CH0 or \ref TPWM_CH1.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to enable output function of specified output pins.
+  * \hideinitializer
+  */
+#define TPWM_ENABLE_OUTPUT(timer, ch) \
+    do{ \
+        if(((uint32_t)&((timer)->PWMCTL) & TMR45_BASE) == TMR45_BASE) { \
+            if((ch) == BIT0) \
+                (timer)->PWMPOEN = BIT0; \
+            else \
+                (timer)->PWMPOEN = (BIT0 | BIT8); \
+        } else { \
+            (timer)->PWMPOEN = (ch); \
+        } \
+    }while(0)
+
+/**
+  * @brief      Set Output Inverse
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @param[in]  ch          Set specified channel output is inversed or not.
+  *                         For TIMER0 ~ TIMER3, the valid value could be a combination of \ref TPWM_CH0 and \ref TPWM_CH1.
+  *                         But this parameter is no effect on TIMER4 and TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to enable output inverse of specified output pins.
+  * \hideinitializer
+  */
+#define TPWM_SET_OUTPUT_INVERSE(timer, ch) \
+    do{ \
+        if(((uint32_t)&((timer)->PWMCTL) & TMR45_BASE) == TMR45_BASE) { \
+            (timer)->PWMPOLCTL = BIT0; \
+        } else { \
+            (timer)->PWMPOLCTL = (ch); \
+        } \
+    }while(0)
+
+/**
+  * @brief      Enable Output Mask Function
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @param[in]  ch       Enable specified channel output mask function. Valid value could be a combination of \ref TPWM_CH0 and \ref TPWM_CH1.
+  *
+  * @param[in]  level    Output to high or low on specified mask channel.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to enable output mask function of specified output pins.
+  * @note       NOT available on TIMER4 and TIMER5.
+  * \hideinitializer
+  */
+#define TPWM_SET_MASK_OUTPUT(timer, ch, level) do {(timer)->PWMMSKEN = (ch); (timer)->PWMMSK = (level); }while(0)
+
+/**
+  * @brief      Set Counter Synchronous Mode
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @param[in]  mode    Synchronous mode. Possible options are:
+  *                         - \ref TPWM_CNTR_SYNC_DISABLE
+  *                         - \ref TPWM_CNTR_SYNC_START_BY_TIMER0
+  *                         - \ref TPWM_CNTR_SYNC_CLEAR_BY_TIMER0
+  *                         - \ref TPWM_CNTR_SYNC_START_BY_TIMER2
+  *                         - \ref TPWM_CNTR_SYNC_CLEAR_BY_TIMER2
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set counter synchronous mode of specified Timer PWM module.
+  * @note       Only support all PWM counters are synchronous by TIMER0 PWM or TIMER0~1 PWM counter synchronous by TIMER0 PWM and
+  *             TIMER2~3 PWM counter synchronous by TIMER2 PWM.
+  * @note       NOT available on TIMER4 and TIMER5.
+  * \hideinitializer
+  */
+#define TPWM_SET_COUNTER_SYNC_MODE(timer, mode)     ((timer)->PWMSCTL = (mode))
+
+/**
+  * @brief      Trigger Counter Synchronous
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to trigger synchronous event by specified TIMER PWM.
+  * @note       1. This macro is only available for TIMER0 PWM and TIMER2 PWM. \n
+  *             2. STRGEN (PWMSTRG[0]) is write only and always read as 0.
+  * @note       NOT available on TIMER4 and TIMER5.
+  * \hideinitializer
+  */
+#define TPWM_TRIGGER_COUNTER_SYNC(timer)            ((timer)->PWMSTRG = TIMER_PWMSTRG_STRGEN_Msk)
+
+/**
+  * @brief      Enable Timer PWM Interrupt Wake-up Function
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER4 or TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to enable the timer pwm interrupt wake-up function.
+  * @note       Only available on TIMER4 and TIMER5.
+  * \hideinitializer
+  */
+#define TPWM_ENABLE_PWMINT_WAKEUP(timer)            ((timer)->PWMCTL |= TIMER_PWMCTL_WKEN_Msk)
+
+/**
+  * @brief      Disable Timer PWM Interrupt Wake-up Function
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER4 or TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to disable the timer pwm interrupt wake-up function.
+  * @note       Only available on TIMER4 and TIMER5.
+  * \hideinitializer
+  */
+#define TPWM_DISABLE_PWMINT_WAKEUP(timer)           ((timer)->PWMCTL &= ~TIMER_PWMCTL_WKEN_Msk)
+
+/**
+  * @brief      Enable Zero Event Interrupt
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to enable the zero event interrupt function.
+  * @note       NOT available on TIMER4 and TIMER5.
+  * \hideinitializer
+  */
+#define TPWM_ENABLE_ZERO_INT(timer)                 ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_ZIEN_Msk)
+
+/**
+  * @brief      Disable Zero Event Interrupt
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to disable the zero event interrupt function.
+  * @note       NOT available on TIMER4 and TIMER5.
+  * \hideinitializer
+  */
+#define TPWM_DISABLE_ZERO_INT(timer)                ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_ZIEN_Msk)
+
+/**
+  * @brief      Get Zero Event Interrupt Flag
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @retval     0   Zero event interrupt did not occur
+  * @retval     1   Zero event interrupt occurred
+  *
+  * @details    This macro indicates zero event occurred or not.
+  * @note       NOT available on TIMER4 and TIMER5.
+  * \hideinitializer
+  */
+#define TPWM_GET_ZERO_INT_FLAG(timer)               (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_ZIF_Msk)? 1 : 0)
+
+/**
+  * @brief      Clear Zero Event Interrupt Flag
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro clears zero event interrupt flag.
+  * @note       NOT available on TIMER4 and TIMER5.
+  * \hideinitializer
+  */
+#define TPWM_CLEAR_ZERO_INT_FLAG(timer)             ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_ZIF_Msk)
+
+/**
+  * @brief      Enable Period Event Interrupt
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to enable the period event interrupt function.
+  * \hideinitializer
+  */
+#define TPWM_ENABLE_PERIOD_INT(timer)               ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_PIEN_Msk)
+
+/**
+  * @brief      Disable Period Event Interrupt
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to disable the period event interrupt function.
+  * \hideinitializer
+  */
+#define TPWM_DISABLE_PERIOD_INT(timer)              ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_PIEN_Msk)
+
+/**
+  * @brief      Get Period Event Interrupt Flag
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @retval     0   Period event interrupt did not occur
+  * @retval     1   Period event interrupt occurred
+  *
+  * @details    This macro indicates period event occurred or not.
+  * \hideinitializer
+  */
+#define TPWM_GET_PERIOD_INT_FLAG(timer)             (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_PIF_Msk)? 1 : 0)
+
+/**
+  * @brief      Clear Period Event Interrupt Flag
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This macro clears period event interrupt flag.
+  * \hideinitializer
+  */
+#define TPWM_CLEAR_PERIOD_INT_FLAG(timer)           ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_PIF_Msk)
+
+/**
+  * @brief      Enable Compare Up Event Interrupt
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to enable the compare up event interrupt function.
+  * \hideinitializer
+  */
+#define TPWM_ENABLE_CMP_UP_INT(timer)               ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_CMPUIEN_Msk)
+
+/**
+  * @brief      Disable Compare Up Event Interrupt
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to disable the compare up event interrupt function.
+  * \hideinitializer
+  */
+#define TPWM_DISABLE_CMP_UP_INT(timer)              ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_CMPUIEN_Msk)
+
+/**
+  * @brief      Get Compare Up Event Interrupt Flag
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @retval     0   Compare up event interrupt did not occur
+  * @retval     1   Compare up event interrupt occurred
+  *
+  * @details    This macro indicates compare up event occurred or not.
+  * \hideinitializer
+  */
+#define TPWM_GET_CMP_UP_INT_FLAG(timer)             (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_CMPUIF_Msk)? 1 : 0)
+
+/**
+  * @brief      Clear Compare Up Event Interrupt Flag
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This macro clears compare up event interrupt flag.
+  * \hideinitializer
+  */
+#define TPWM_CLEAR_CMP_UP_INT_FLAG(timer)           ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_CMPUIF_Msk)
+
+/**
+  * @brief      Enable Compare Down Event Interrupt
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to enable the compare down event interrupt function.
+  * @note       NOT available on TIMER4 and TIMER5.
+  * \hideinitializer
+  */
+#define TPWM_ENABLE_CMP_DOWN_INT(timer)             ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_CMPDIEN_Msk)
+
+/**
+  * @brief      Disable Compare Down Event Interrupt
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to disable the compare down event interrupt function.
+  * @note       NOT available on TIMER4 and TIMER5.
+  * \hideinitializer
+  */
+#define TPWM_DISABLE_CMP_DOWN_INT(timer)            ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_CMPDIEN_Msk)
+
+/**
+  * @brief      Get Compare Down Event Interrupt Flag
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @retval     0   Compare down event interrupt did not occur
+  * @retval     1   Compare down event interrupt occurred
+  *
+  * @details    This macro indicates compare down event occurred or not.
+  * @note       NOT available on TIMER4 and TIMER5.
+  * \hideinitializer
+  */
+#define TPWM_GET_CMP_DOWN_INT_FLAG(timer)           (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_CMPDIF_Msk)? 1 : 0)
+
+/**
+  * @brief      Clear Compare Down Event Interrupt Flag
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro clears compare down event interrupt flag.
+  * @note       NOT available on TIMER4 and TIMER5.
+  * \hideinitializer
+  */
+#define TPWM_CLEAR_CMP_DOWN_INT_FLAG(timer)         ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_CMPDIF_Msk)
+
+/**
+  * @brief      Get Counter Reach Maximum Count Status
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @retval     0   Timer PWM counter never counts to maximum value
+  * @retval     1   Timer PWM counter counts to maximum value, 0xFFFF
+  *
+  * @details    This macro indicates Timer PWM counter has count to 0xFFFF or not.
+  * \hideinitializer
+  */
+#define TPWM_GET_REACH_MAX_CNT_STATUS(timer)        (((timer)->PWMSTATUS & TIMER_PWMSTATUS_CNTMAXF_Msk)? 1 : 0)
+
+/**
+  * @brief      Clear Counter Reach Maximum Count Status
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This macro clears reach maximum count status.
+  * \hideinitializer
+  */
+#define TPWM_CLEAR_REACH_MAX_CNT_STATUS(timer)      ((timer)->PWMSTATUS = TIMER_PWMSTATUS_CNTMAXF_Msk)
+
+/**
+  * @brief      Get Trigger ADC Status
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @retval     0       Trigger ADC start conversion is not occur
+  * @retval     1       Specified counter compare event has trigger ADC start conversion
+  *
+  * @details    This macro is used to indicate PWM counter compare event has triggered ADC start conversion.
+  * \hideinitializer
+  */
+#define TPWM_GET_TRG_ADC_STATUS(timer)              (((timer)->PWMSTATUS & TIMER_PWMSTATUS_EADCTRGF_Msk)? 1 : 0)
+
+/**
+  * @brief      Clear Trigger ADC Status
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to clear PWM counter compare event trigger ADC status.
+  * \hideinitializer
+  */
+#define TPWM_CLEAR_TRG_ADC_STATUS(timer)            ((timer)->PWMSTATUS = TIMER_PWMSTATUS_EADCTRGF_Msk)
+
+/**
+  * @brief      Get Trigger PDMA Status
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER4 ~ TIMER5.
+  *
+  * @retval     0       Trigger PDMA transfer data is not occur
+  * @retval     1       Specified counter compare event has trigger PDMA transfer data
+  *
+  * @details    This macro is used to indicate PWM counter compare event has triggered PDMA start transfer data.
+  * @note       Only available on TIMER4 and TIMER5.
+  * \hideinitializer
+  */
+#define TPWM_GET_TRG_PDMA_STATUS(timer)             (((timer)->PWMSTATUS & TIMER_PWMSTATUS_PDMATRGF_Msk)? 1 : 0)
+
+/**
+  * @brief      Clear Trigger PDMA Status
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER4 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to clear PWM counter compare event trigger PDMA status.
+  * @note       Only available on TIMER4 and TIMER5.
+  * \hideinitializer
+  */
+#define TPWM_CLEAR_TRG_PDMA_STATUS(timer)           ((timer)->PWMSTATUS = TIMER_PWMSTATUS_PDMATRGF_Msk)
+
+/**
+  * @brief      Get PWM Interrupt Wake-up Flag
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER4 ~ TIMER5.
+  *
+  * @retval     0   PWM does not cause CPU wake-up
+  * @retval     1   PWM interrupt event cause CPU wake-up
+  *
+  * @details    This function indicates PWM interrupt event has waked up system or not.
+  * @note       Only available on TIMER4 and TIMER5.
+  */
+#define TPWM_GET_PWMINT_WAKEUP_STATUS(timer)        (((timer)->PWMSTATUS & TIMER_PWMSTATUS_WKF_Msk)? 1 : 0)
+
+/**
+  * @brief      Clear PWM Interrupt Wake-up Flag
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER4 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to clear PWM interrupt wakeup status.
+  * @note       Only available on TIMER4 and TIMER5.
+  * \hideinitializer
+  */
+#define TPWM_CLEAR_PWMINT_WAKEUP_STATUS(timer)           ((timer)->PWMSTATUS = TIMER_PWMSTATUS_WKF_Msk)
+
+/**
+  * @brief      Set Brake Event at Brake Pin High or Low-to-High
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set detect brake event when external brake pin at high level or transfer from low to high.
+  * @note       The default brake pin detection is high level or from low to high.
+  * @note       NOT available on TIMER4 and TIMER5.
+  * \hideinitializer
+  */
+#define TPWM_SET_BRAKE_PIN_HIGH_DETECT(timer)       ((timer)->PWMBNF &= ~TIMER_PWMBNF_BRKPINV_Msk)
+
+/**
+  * @brief      Set Brake Event at Brake Pin Low or High-to-Low
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set detect brake event when external brake pin at low level or transfer from high to low.
+  * @note       NOT available on TIMER4 and TIMER5.
+  * \hideinitializer
+  */
+#define TPWM_SET_BRAKE_PIN_LOW_DETECT(timer)        ((timer)->PWMBNF |= TIMER_PWMBNF_BRKPINV_Msk)
+
+/**
+  * @brief      Set External Brake Pin Source
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  pin         The external brake pin source, could be one of following source
+  *                                 - \ref TPWM_TM_BRAKE0
+  *                                 - \ref TPWM_TM_BRAKE1
+  *                                 - \ref TPWM_TM_BRAKE2
+  *                                 - \ref TPWM_TM_BRAKE3
+  *
+  * @return     None
+  *
+  * @details    This macro is used to set detect brake event when external brake pin at high level or transfer from low to high.
+  * @note       NOT available on TIMER4 and TIMER5.
+  * \hideinitializer
+  */
+#define TPWM_SET_BRAKE_PIN_SOURCE(timer, pin)       ((timer)->PWMBNF = ((timer)->PWMBNF & ~TIMER_PWMBNF_BKPINSRC_Msk) | ((pin)<> 4ul)-2ul)
+
+
+/**
+ *    @brief        Calculate UART baudrate mode2 divider
+ *
+ *    @param[in]    u32SrcFreq      UART clock frequency
+ *    @param[in]    u32BaudRate     Baudrate of UART module
+ *
+ *    @return       UART baudrate mode2 divider
+ *
+ *    @details      This macro calculate UART baudrate mode2 divider.
+ */
+#define UART_BAUD_MODE2_DIVIDER(u32SrcFreq, u32BaudRate)    ((((u32SrcFreq) + ((u32BaudRate)/2ul)) / (u32BaudRate))-2ul)
+
+
+/**
+ *    @brief        Write UART data
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *    @param[in]    u8Data  Data byte to transmit.
+ *
+ *    @return       None
+ *
+ *    @details      This macro write Data to Tx data register.
+ */
+#define UART_WRITE(uart, u8Data)    ((uart)->DAT = (u8Data))
+
+
+/**
+ *    @brief        Read UART data
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @return       The oldest data byte in RX FIFO.
+ *
+ *    @details      This macro read Rx data register.
+ */
+#define UART_READ(uart)    ((uart)->DAT)
+
+
+/**
+ *    @brief        Get Tx empty
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @retval       0   Tx FIFO is not empty
+ *    @retval       >=1 Tx FIFO is empty
+ *
+ *    @details      This macro get Transmitter FIFO empty register value.
+ */
+#define UART_GET_TX_EMPTY(uart)    ((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTY_Msk)
+
+
+/**
+ *    @brief        Get Rx empty
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @retval       0   Rx FIFO is not empty
+ *    @retval       >=1 Rx FIFO is empty
+ *
+ *    @details      This macro get Receiver FIFO empty register value.
+ */
+#define UART_GET_RX_EMPTY(uart)    ((uart)->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk)
+
+
+/**
+ *    @brief        Check specified uart port transmission is over.
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @retval       0 Tx transmission is not over
+ *    @retval       1 Tx transmission is over
+ *
+ *    @details      This macro return Transmitter Empty Flag register bit value.
+ *                  It indicates if specified uart port transmission is over nor not.
+ */
+#define UART_IS_TX_EMPTY(uart)    (((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)
+
+
+/**
+ *    @brief        Wait specified uart port transmission is over
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @return       None
+ *
+ *    @details      This macro wait specified uart port transmission is over.
+ */
+#define UART_WAIT_TX_EMPTY(uart)    while(!((((uart)->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos))
+
+
+/**
+ *    @brief        Check RX is ready or not
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @retval       0 The number of bytes in the RX FIFO is less than the RFITL
+ *    @retval       1 The number of bytes in the RX FIFO equals or larger than RFITL
+ *
+ *    @details      This macro check receive data available interrupt flag is set or not.
+ */
+#define UART_IS_RX_READY(uart)    (((uart)->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos)
+
+
+/**
+ *    @brief        Check TX FIFO is full or not
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @retval       1 TX FIFO is full
+ *    @retval       0 TX FIFO is not full
+ *
+ *    @details      This macro check TX FIFO is full or not.
+ */
+#define UART_IS_TX_FULL(uart)    (((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos)
+
+
+/**
+ *    @brief        Check RX FIFO is full or not
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @retval       1 RX FIFO is full
+ *    @retval       0 RX FIFO is not full
+ *
+ *    @details      This macro check RX FIFO is full or not.
+ */
+#define UART_IS_RX_FULL(uart)    (((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos)
+
+
+/**
+ *    @brief        Get Tx full register value
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @retval       0   Tx FIFO is not full.
+ *    @retval       >=1 Tx FIFO is full.
+ *
+ *    @details      This macro get Tx full register value.
+ */
+#define UART_GET_TX_FULL(uart)    ((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)
+
+
+/**
+ *    @brief        Get Rx full register value
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @retval       0   Rx FIFO is not full.
+ *    @retval       >=1 Rx FIFO is full.
+ *
+ *    @details      This macro get Rx full register value.
+ */
+#define UART_GET_RX_FULL(uart)    ((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)
+
+/**
+ *    @brief        Rx Idle Status register value
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @retval       0 Rx is busy.
+ *    @retval       1 Rx is Idle(Default)
+ *
+ *    @details      This macro get Rx Idle Status register value.
+ *    \hideinitializer
+ */
+#define UART_RX_IDLE(uart) (((uart)->FIFOSTS & UART_FIFOSTS_RXIDLE_Msk )>> UART_FIFOSTS_RXIDLE_Pos)
+
+
+/**
+ *    @brief        Enable specified UART interrupt
+ *
+ *    @param[in]    uart        The pointer of the specified UART module
+ *    @param[in]    u32eIntSel  Interrupt type select
+ *                              - \ref UART_INTEN_TXENDIEN_Msk   : Transmitter empty interrupt
+ *                              - \ref UART_INTEN_ABRIEN_Msk     : Auto baud rate interrupt
+ *                              - \ref UART_INTEN_LINIEN_Msk     : Lin bus interrupt
+ *                              - \ref UART_INTEN_WKIEN_Msk      : Wake-up interrupt
+ *                              - \ref UART_INTEN_BUFERRIEN_Msk  : Buffer Error interrupt
+ *                              - \ref UART_INTEN_RXTOIEN_Msk    : Rx time-out interrupt
+ *                              - \ref UART_INTEN_MODEMIEN_Msk   : Modem interrupt
+ *                              - \ref UART_INTEN_RLSIEN_Msk     : Rx Line status interrupt
+ *                              - \ref UART_INTEN_THREIEN_Msk    : Tx empty interrupt
+ *                              - \ref UART_INTEN_RDAIEN_Msk     : Rx ready interrupt
+ *
+ *    @return       None
+ *
+ *    @details      This macro enable specified UART interrupt.
+ */
+#define UART_ENABLE_INT(uart, u32eIntSel)    ((uart)->INTEN |= (u32eIntSel))
+
+
+/**
+ *    @brief        Disable specified UART interrupt
+ *
+ *    @param[in]    uart        The pointer of the specified UART module
+ *    @param[in]    u32eIntSel  Interrupt type select
+ *                              - \ref UART_INTEN_TXENDIEN_Msk   : Transmitter Empty Interrupt
+ *                              - \ref UART_INTEN_ABRIEN_Msk     : Auto-baud Rate Interrupt
+ *                              - \ref UART_INTEN_LINIEN_Msk     : Lin Bus interrupt
+ *                              - \ref UART_INTEN_WKIEN_Msk      : Wake-up interrupt
+ *                              - \ref UART_INTEN_BUFERRIEN_Msk  : Buffer Error interrupt
+ *                              - \ref UART_INTEN_RXTOIEN_Msk    : Rx Time-out Interrupt
+ *                              - \ref UART_INTEN_MODEMIEN_Msk   : MODEM Status Interrupt
+ *                              - \ref UART_INTEN_RLSIEN_Msk     : Receive Line Status Interrupt
+ *                              - \ref UART_INTEN_THREIEN_Msk    : Transmit Holding Register Empty Interrupt
+ *                              - \ref UART_INTEN_RDAIEN_Msk     : Receive Data Available Interrupt
+ *
+ *    @return       None
+ *
+ *    @details      This macro enable specified UART interrupt.
+ */
+#define UART_DISABLE_INT(uart, u32eIntSel)    ((uart)->INTEN &= ~ (u32eIntSel))
+
+
+/**
+ *    @brief        Get specified interrupt flag/status
+ *
+ *    @param[in]    uart            The pointer of the specified UART module
+ *    @param[in]    u32eIntTypeFlag Interrupt Type Flag, should be
+ *                                  - \ref UART_INTSTS_ABRINT_Msk    : Auto-baud Rate Interrupt Indicator
+ *                                  - \ref UART_INTSTS_HWBUFEINT_Msk : PDMA Mode Buffer Error Interrupt Indicator
+ *                                  - \ref UART_INTSTS_HWTOINT_Msk   : PDMA Mode Rx Time-out Interrupt Indicator
+ *                                  - \ref UART_INTSTS_HWMODINT_Msk  : PDMA Mode MODEM Status Interrupt Indicator
+ *                                  - \ref UART_INTSTS_HWRLSINT_Msk  : PDMA Mode Receive Line Status Interrupt Indicator
+ *                                  - \ref UART_INTSTS_SWBEINT_Msk   : Single-wire Bit Error Detect Interrupt Indicator
+ *                                  - \ref UART_INTSTS_HWBUFEIF_Msk  : PDMA Mode Buffer Error Interrupt Flag
+ *                                  - \ref UART_INTSTS_HWTOIF_Msk    : PDMA Mode Time-out Interrupt Flag
+ *                                  - \ref UART_INTSTS_HWMODIF_Msk   : PDMA Mode MODEM Status Interrupt Flag
+ *                                  - \ref UART_INTSTS_HWRLSIF_Msk   : PDMA Mode Receive Line Status Flag
+ *                                  - \ref UART_INTSTS_SWBEIF_Msk   : Single-wire Bit Error Detect Interrupt Flag
+ *                                  - \ref UART_INTSTS_TXENDINT_Msk  : Transmitter Empty Interrupt Indicator
+ *                                  - \ref UART_INTSTS_LININT_Msk    : LIN Bus Interrupt Indicator
+ *                                  - \ref UART_INTSTS_WKINT_Msk     : Wake-up Interrupt Indicator
+ *                                  - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error Interrupt Indicator
+ *                                  - \ref UART_INTSTS_RXTOINT_Msk   : Rx Time-out Interrupt Indicator
+ *                                  - \ref UART_INTSTS_MODEMINT_Msk  : Modem Status Interrupt Indicator
+ *                                  - \ref UART_INTSTS_RLSINT_Msk    : Receive Line Status Interrupt Indicator
+ *                                  - \ref UART_INTSTS_THREINT_Msk   : Transmit Holding Register Empty Interrupt Indicator
+ *                                  - \ref UART_INTSTS_RDAINT_Msk    : Receive Data Available Interrupt Indicator
+ *                                  - \ref UART_INTSTS_TXENDIF_Msk   : Transmitter Empty Interrupt Flag
+ *                                  - \ref UART_INTSTS_LINIF_Msk     : LIN Bus Interrupt Flag
+ *                                  - \ref UART_INTSTS_WKIF_Msk      : Wake-up Interrupt Flag
+ *                                  - \ref UART_INTSTS_BUFERRIF_Msk  : Buffer Error Interrupt Flag
+ *                                  - \ref UART_INTSTS_RXTOIF_Msk    : Rx Time-out Interrupt Flag
+ *                                  - \ref UART_INTSTS_MODEMIF_Msk   : MODEM Status Interrupt Flag
+ *                                  - \ref UART_INTSTS_RLSIF_Msk     : Receive Line Status Interrupt Flag
+ *                                  - \ref UART_INTSTS_THREIF_Msk    : Transmit Holding Register Empty Interrupt Flag
+ *                                  - \ref UART_INTSTS_RDAIF_Msk     : Receive Data Available Interrupt Flag
+ *
+ *    @retval       0 The specified interrupt is not happened.
+ *                  1 The specified interrupt is happened.
+ *
+ *    @details      This macro get specified interrupt flag or interrupt indicator status.
+ */
+#define UART_GET_INT_FLAG(uart,u32eIntTypeFlag)    (((uart)->INTSTS & (u32eIntTypeFlag))?1:0)
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* static inline functions                                                                                 */
+/*---------------------------------------------------------------------------------------------------------*/
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
+static __INLINE void UART_CLEAR_RTS(UART_T* uart);
+static __INLINE void UART_SET_RTS(UART_T* uart);
+
+
+/**
+ *    @brief        Set RTS pin to low
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @return       None
+ *
+ *    @details      This macro set RTS pin to low.
+ */
+__STATIC_INLINE void UART_CLEAR_RTS(UART_T* uart)
+{
+    uart->MODEM |= UART_MODEM_RTSACTLV_Msk;
+    uart->MODEM &= ~UART_MODEM_RTS_Msk;
+}
+
+
+/**
+ *    @brief        Set RTS pin to high
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @return       None
+ *
+ *    @details      This macro set RTS pin to high.
+ */
+__STATIC_INLINE void UART_SET_RTS(UART_T* uart)
+{
+    uart->MODEM |= UART_MODEM_RTSACTLV_Msk | UART_MODEM_RTS_Msk;
+}
+
+
+/**
+ *    @brief        Clear RS-485 Address Byte Detection Flag
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @return       None
+ *
+ *    @details      This macro clear RS-485 address byte detection flag.
+ */
+#define UART_RS485_CLEAR_ADDR_FLAG(uart)    ((uart)->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk)
+
+
+/**
+ *    @brief        Get RS-485 Address Byte Detection Flag
+ *
+ *    @param[in]    uart    The pointer of the specified UART module
+ *
+ *    @retval       0 Receiver detects a data that is not an address bit.
+ *    @retval       1 Receiver detects a data that is an address bit.
+ *
+ *    @details      This macro get RS-485 address byte detection flag.
+ */
+#define UART_RS485_GET_ADDR_FLAG(uart)    (((uart)->FIFOSTS  & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos)
+
+
+/**
+ *    @brief        Enable specified UART PDMA function
+ *
+ *    @param[in]    uart        The pointer of the specified UART module
+ *    @param[in]    u32FuncSel  Combination of following functions
+ *                             - \ref UART_INTEN_TXPDMAEN_Msk
+ *                             - \ref UART_INTEN_RXPDMAEN_Msk
+ *
+ *    @return       None
+ *
+ *    @details      This macro enable specified UART PDMA function.
+ */
+#define UART_PDMA_ENABLE(uart, u32FuncSel)    ((uart)->INTEN |= (u32FuncSel))
+
+
+/**
+ *    @brief        Disable specified UART PDMA function
+ *
+ *    @param[in]    uart        The pointer of the specified UART module
+ *    @param[in]    u32FuncSel  Combination of following functions
+ *                             - \ref UART_INTEN_TXPDMAEN_Msk
+ *                             - \ref UART_INTEN_RXPDMAEN_Msk
+ *
+ *    @return       None
+ *
+ *    @details      This macro disable specified UART PDMA function.
+ */
+#define UART_PDMA_DISABLE(uart, u32FuncSel)    ((uart)->INTEN &= ~(u32FuncSel))
+
+
+void UART_ClearIntFlag(UART_T* uart, uint32_t u32InterruptFlag);
+void UART_Close(UART_T* uart);
+void UART_DisableFlowCtrl(UART_T* uart);
+void UART_DisableInt(UART_T*  uart, uint32_t u32InterruptFlag);
+void UART_EnableFlowCtrl(UART_T* uart);
+void UART_EnableInt(UART_T*  uart, uint32_t u32InterruptFlag);
+void UART_Open(UART_T* uart, uint32_t u32baudrate);
+uint32_t UART_Read(UART_T* uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes);
+void UART_SetLineConfig(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t  u32stop_bits);
+void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC);
+void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction);
+void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr);
+void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength);
+uint32_t UART_Write(UART_T* uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes);
+void UART_SelectSingleWireMode(UART_T *uart);
+
+
+/**@}*/ /* end of group UART_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group UART_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_UART_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_usbd.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_usbd.h
new file mode 100644
index 0000000000..d0a7c0f130
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_usbd.h
@@ -0,0 +1,796 @@
+/******************************************************************************
+ * @file     nu_usbd.h
+ * @version  V3.00
+ * @brief    M2354 series USBD driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __NU_USBD_H__
+#define __NU_USBD_H__
+
+#define SUPPORT_LPM     // define to support LPM
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup USBD_Driver USBD Driver
+  @{
+*/
+
+/** @addtogroup USBD_EXPORTED_STRUCTS USBD Exported Structs
+  @{
+*/
+
+typedef struct s_usbd_info
+{
+    uint8_t *gu8DevDesc;            /*!< Pointer for USB Device Descriptor          */
+    uint8_t *gu8ConfigDesc;         /*!< Pointer for USB Configuration Descriptor   */
+    uint8_t **gu8StringDesc;        /*!< Pointer for USB String Descriptor pointers */
+    uint8_t **gu8HidReportDesc;     /*!< Pointer for USB HID Report Descriptor      */
+    uint8_t *gu8BosDesc;            /*!< Pointer for USB BOS Descriptor             */
+    uint32_t *gu32HidReportSize;    /*!< Pointer for HID Report descriptor Size */
+    uint32_t *gu32ConfigHidDescIdx; /*!< Pointer for HID Descriptor start index */
+
+} S_USBD_INFO_T;  /*!< Device description structure */
+
+extern const S_USBD_INFO_T gsInfo;
+
+/**@}*/ /* end of group USBD_EXPORTED_STRUCTS */
+
+
+/** @addtogroup USBD_EXPORTED_CONSTANTS USBD Exported Constants
+  @{
+*/
+
+#define USBD_BUF_BASE      (uint32_t)(((__PC() & NS_OFFSET) == NS_OFFSET)? (USBD_BASE+NS_OFFSET+0x100UL):(USBD_BASE+0x100UL))  /*!< USBD buffer base address */
+#define USBD_MAX_EP        12UL  /*!< Total EP number */
+
+#define EP0     0UL       /*!< Endpoint 0 */
+#define EP1     1UL       /*!< Endpoint 1 */
+#define EP2     2UL       /*!< Endpoint 2 */
+#define EP3     3UL       /*!< Endpoint 3 */
+#define EP4     4UL       /*!< Endpoint 4 */
+#define EP5     5UL       /*!< Endpoint 5 */
+#define EP6     6UL       /*!< Endpoint 6 */
+#define EP7     7UL       /*!< Endpoint 7 */
+#define EP8     8UL       /*!< Endpoint 8 */
+#define EP9     9UL       /*!< Endpoint 9 */
+#define EP10    10UL      /*!< Endpoint 10 */
+#define EP11    11UL      /*!< Endpoint 11 */
+
+/** @cond HIDDEN_SYMBOLS */
+/* USB Request Type */
+#define REQ_STANDARD        0x00UL
+#define REQ_CLASS           0x20UL
+#define REQ_VENDOR          0x40UL
+
+/* USB Standard Request */
+#define GET_STATUS          0x00UL
+#define CLEAR_FEATURE       0x01UL
+#define SET_FEATURE         0x03UL
+#define SET_ADDRESS         0x05UL
+#define GET_DESCRIPTOR      0x06UL
+#define SET_DESCRIPTOR      0x07UL
+#define GET_CONFIGURATION   0x08UL
+#define SET_CONFIGURATION   0x09UL
+#define GET_INTERFACE       0x0AUL
+#define SET_INTERFACE       0x0BUL
+#define SYNC_FRAME          0x0CUL
+
+/* USB Descriptor Type */
+#define DESC_DEVICE         0x01UL
+#define DESC_CONFIG         0x02UL
+#define DESC_STRING         0x03UL
+#define DESC_INTERFACE      0x04UL
+#define DESC_ENDPOINT       0x05UL
+#define DESC_QUALIFIER      0x06UL
+#define DESC_OTHERSPEED     0x07UL
+#define DESC_IFPOWER        0x08UL
+#define DESC_OTG            0x09UL
+#define DESC_BOS            0x0FUL
+#define DESC_CAPABILITY     0x10UL
+
+/* USB Device Capability Type */
+#define CAP_WIRELESS        0x01UL
+#define CAP_USB20_EXT       0x02UL
+
+/*! b, then return a. Otherwise, return b.
+  */
+#define USBD_Maximum(a,b)        ((a)>(b) ? (a) : (b))
+
+/**
+  * @brief      Compare two input numbers and return minimum one
+  *
+  * @param[in]  a   First number to be compared
+  * @param[in]  b   Second number to be compared
+  *
+  * @return     Minimum value between a and b
+  *
+  * @details    If a < b, then return a. Otherwise, return b.
+  */
+#define USBD_Minimum(a,b)        ((a)<(b) ? (a) : (b))
+
+/**
+  * @brief    Enable USB
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  To set USB ATTR control register to enable USB and PHY.
+  *
+  */
+#define USBD_ENABLE_USB()           (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->ATTR |= 0x7D0)):((uint32_t)(USBD->ATTR |= 0x7D0)))
+
+/**
+  * @brief    Disable USB
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  To set USB ATTR control register to disable USB.
+  *
+  */
+#define USBD_DISABLE_USB()          (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->ATTR &= ~USBD_USB_EN)):((uint32_t)(USBD->ATTR &= ~USBD_USB_EN)))
+
+/**
+  * @brief    Enable USB PHY
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  To set USB ATTR control register to enable USB PHY.
+  *
+  */
+#define USBD_ENABLE_PHY()           (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->ATTR |= USBD_PHY_EN)):((uint32_t)(USBD->ATTR |= USBD_PHY_EN)))
+
+/**
+  * @brief    Disable USB PHY
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  To set USB ATTR control register to disable USB PHY.
+  *
+  */
+#define USBD_DISABLE_PHY()          (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->ATTR &= ~USBD_PHY_EN)):((uint32_t)(USBD->ATTR &= ~USBD_PHY_EN)))
+
+/**
+  * @brief    Enable SE0. Force USB PHY transceiver to drive SE0.
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  Set DRVSE0 bit of USB_DRVSE0 register to enable software-disconnect function. Force USB PHY transceiver to drive SE0 to bus.
+  *
+  */
+#define USBD_SET_SE0()              (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->SE0 |= USBD_DRVSE0)):((uint32_t)(USBD->SE0 |= USBD_DRVSE0)))
+
+/**
+  * @brief    Disable SE0
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  Clear DRVSE0 bit of USB_DRVSE0 register to disable software-disconnect function.
+  *
+  */
+#define USBD_CLR_SE0()              (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->SE0 &= ~USBD_DRVSE0)):((uint32_t)(USBD->SE0 &= ~USBD_DRVSE0)))
+
+/**
+  * @brief       Set USB device address
+  *
+  * @param[in]   addr The USB device address.
+  *
+  * @return      None
+  *
+  * @details     Write USB device address to USB_FADDR register.
+  *
+  */
+#define USBD_SET_ADDR(addr)         (((__PC() & NS_OFFSET) == NS_OFFSET)? (USBD_NS->FADDR = (addr)):(USBD->FADDR = (addr)))
+
+/**
+  * @brief    Get USB device address
+  *
+  * @param    None
+  *
+  * @return   USB device address
+  *
+  * @details  Read USB_FADDR register to get USB device address.
+  *
+  */
+#define USBD_GET_ADDR()             (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->FADDR)):((uint32_t)(USBD->FADDR)))
+
+/**
+  * @brief      Enable USB interrupt function
+  *
+  * @param[in]  intr The combination of the specified interrupt enable bits.
+  *             Each bit corresponds to a interrupt enable bit.
+  *             This parameter decides which interrupts will be enabled.
+  *             (USBD_INT_WAKEUP, USBD_INT_FLDET, USBD_INT_USB, USBD_INT_BUS)
+  *
+  * @return     None
+  *
+  * @details    Enable USB related interrupt functions specified by intr parameter.
+  *
+  */
+#define USBD_ENABLE_INT(intr)       (((__PC() & NS_OFFSET) == NS_OFFSET)? (USBD_NS->INTEN |= (intr)):(USBD->INTEN |= (intr)))
+
+/**
+  * @brief    Get interrupt status
+  *
+  * @param    None
+  *
+  * @return   The value of USB_INTSTS register
+  *
+  * @details  Return all interrupt flags of USB_INTSTS register.
+  *
+  */
+#define USBD_GET_INT_FLAG()         (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->INTSTS)):((uint32_t)(USBD->INTSTS)))
+
+/**
+  * @brief      Clear USB interrupt flag
+  *
+  * @param[in]  flag The combination of the specified interrupt flags.
+  *             Each bit corresponds to a interrupt source.
+  *             This parameter decides which interrupt flags will be cleared.
+  *             (USBD_INTSTS_WAKEUP, USBD_INTSTS_FLDET, USBD_INTSTS_BUS, USBD_INTSTS_USB)
+  *
+  * @return     None
+  *
+  * @details    Clear USB related interrupt flags specified by flag parameter.
+  *
+  */
+#define USBD_CLR_INT_FLAG(flag)     (((__PC() & NS_OFFSET) == NS_OFFSET)? (USBD_NS->INTSTS = (flag)):(USBD->INTSTS = (flag)))
+
+/**
+  * @brief    Get endpoint status
+  *
+  * @param    None
+  *
+  * @return   The value of USB_EPSTS register.
+  *
+  * @details  Return all endpoint status.
+  *
+  */
+#define USBD_GET_EP_FLAG()          (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->EPSTS)):((uint32_t)(USBD->EPSTS)))
+
+/**
+  * @brief    Get USB bus state
+  *
+  * @param    None
+  *
+  * @return   The value of USB_ATTR[13:12] and USB_ATTR[3:0].
+  *           Bit 0  indicates USB bus reset status.
+  *           Bit 1  indicates USB bus suspend status.
+  *           Bit 2  indicates USB bus resume status.
+  *           Bit 3  indicates USB bus time-out status.
+  *           Bit 12 indicates USB bus LPM L1 suspend status.
+  *           Bit 13 indicates USB bus LPM L1 resume status.
+  *
+  * @details  Return USB_ATTR[13:12] and USB_ATTR[3:0] for USB bus events.
+  *
+  */
+#define USBD_GET_BUS_STATE()        (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->ATTR & 0x300F)):((uint32_t)(USBD->ATTR & 0x300F)))
+
+/**
+  * @brief    Check cable connection state
+  *
+  * @param    None
+  *
+  * @retval   0 USB cable is not attached.
+  * @retval   1 USB cable is attached.
+  *
+  * @details  Check the connection state by FLDET bit of USB_FLDET register.
+  *
+  */
+#define USBD_IS_ATTACHED()          (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->VBUSDET & USBD_VBUSDET_VBUSDET_Msk)):((uint32_t)(USBD->VBUSDET & USBD_VBUSDET_VBUSDET_Msk)))
+
+/**
+  * @brief      Stop USB transaction of the specified endpoint ID
+  *
+  * @param[in]  ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
+  *
+  * @return     None
+  *
+  * @details    Write 1 to CLRRDY bit of USB_CFGPx register to stop USB transaction of the specified endpoint ID.
+  *
+  */
+#define USBD_STOP_TRANSACTION(ep)      (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_CLRRDY_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_CLRRDY_Msk))
+
+/**
+  * @brief      Set USB DATA1 PID for the specified endpoint ID
+  *
+  * @param[in]  ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
+  *
+  * @return     None
+  *
+  * @details    Set DSQ_SYNC bit of USB_CFGx register to specify the DATA1 PID for the following IN token transaction.
+  *             Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions in single buffer mode.
+  *
+  */
+#define USBD_SET_DATA1(ep)          (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DSQSYNC_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DSQSYNC_Msk))
+
+/**
+  * @brief      Set USB DATA0 PID for the specified endpoint ID
+  *
+  * @param[in]  ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
+  *
+  * @return     None
+  *
+  * @details    Clear DSQ_SYNC bit of USB_CFGx register to specify the DATA0 PID for the following IN token transaction.
+  *             Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions in single buffer mode.
+  *
+  */
+#define USBD_SET_DATA0(ep)          (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DSQSYNC_Msk)):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DSQSYNC_Msk)))
+
+/**
+  * @brief      Set USB payload size (IN data)
+  *
+  * @param[in]  ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
+  *
+  * @param[in]  size The transfer length.
+  *
+  * @return     None
+  *
+  * @details    This macro will write the transfer length to USB_MXPLDx register for IN data transaction.
+  *
+  */
+#define USBD_SET_PAYLOAD_LEN(ep, size)  (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].MXPLD + (uint32_t)((ep) << 4))) = (size)):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))) = (size)))
+
+/**
+  * @brief      Get USB payload size (OUT data)
+  *
+  * @param[in]  ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
+  *
+  * @return     The value of USB_MXPLDx register.
+  *
+  * @details    Get the data length of OUT data transaction by reading USB_MXPLDx register.
+  *
+  */
+#define USBD_GET_PAYLOAD_LEN(ep)        (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].MXPLD + (uint32_t)((ep) << 4)))):((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4)))))
+
+/**
+  * @brief      Configure endpoint
+  *
+  * @param[in]  ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
+  *
+  * @param[in]  config The USB configuration.
+  *
+  * @return     None
+  *
+  * @details    This macro will write config parameter to USB_CFGx register of specified endpoint ID.
+  *
+  */
+#define USBD_CONFIG_EP(ep, config)      (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) = (config)):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) = (config)))
+
+/**
+  * @brief      Set USB endpoint buffer
+  *
+  * @param[in]  ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
+  *
+  * @param[in]  offset The SRAM offset.
+  *
+  * @return     None
+  *
+  * @details    This macro will set the SRAM offset for the specified endpoint ID.
+  *
+  */
+#define USBD_SET_EP_BUF_ADDR(ep, offset)    (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].BUFSEG + (uint32_t)((ep) << 4))) = (offset)):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))) = (offset)))
+
+/**
+  * @brief      Get the offset of the specified USB endpoint buffer
+  *
+  * @param[in]  ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
+  *
+  * @return     The offset of the specified endpoint buffer.
+  *
+  * @details    This macro will return the SRAM offset of the specified endpoint ID.
+  *
+  */
+#define USBD_GET_EP_BUF_ADDR(ep)        (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].BUFSEG + (uint32_t)((ep) << 4)))):((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4)))))
+
+/**
+  * @brief       Set USB endpoint stall state
+  *
+  * @param[in]   ep  The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
+  *
+  * @return      None
+  *
+  * @details     Set USB endpoint stall state for the specified endpoint ID. Endpoint will respond STALL token automatically.
+  *
+  */
+#define USBD_SET_EP_STALL(ep)        (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_SSTALL_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_SSTALL_Msk))
+
+/**
+  * @brief       Clear USB endpoint stall state
+  *
+  * @param[in]   ep  The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
+  *
+  * @return      None
+  *
+  * @details     Clear USB endpoint stall state for the specified endpoint ID. Endpoint will respond ACK/NAK token.
+  *
+  */
+#define USBD_CLR_EP_STALL(ep)        (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFGP + (uint32_t)((ep) << 4))) &= ~USBD_CFGP_SSTALL_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) &= ~USBD_CFGP_SSTALL_Msk))
+
+/**
+  * @brief       Get USB endpoint stall state
+  *
+  * @param[in]   ep  The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
+  *
+  * @retval      0      USB endpoint is not stalled.
+  * @retval      Others USB endpoint is stalled.
+  *
+  * @details     Get USB endpoint stall state of the specified endpoint ID.
+  *
+  */
+#define USBD_GET_EP_STALL(ep)        (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFGP + (uint32_t)((ep) << 4))) & USBD_CFGP_SSTALL_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) & USBD_CFGP_SSTALL_Msk))
+
+/**
+  * @brief      Set USB double buffer mode for the specified endpoint ID
+  *
+  * @param[in]  ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
+  *
+  * @return     None
+  *
+  * @details    Set DBEN bit of USB_CFGx register to enable the double buffer mode of the specified endpoint ID.
+  *
+  */
+#define USBD_SET_DB_MODE(ep)          (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DBEN_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DBEN_Msk))
+
+/**
+  * @brief      Set USB single buffer mode for the specified endpoint ID
+  *
+  * @param[in]  ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
+  *
+  * @return     None
+  *
+  * @details    Clear DBEN bit of USB_CFGx register to enable the single buffer mode of the specified endpoint ID.
+  *
+  */
+#define USBD_SET_SB_MODE(ep)          (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DBEN_Msk)):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DBEN_Msk)))
+
+/**
+  * @brief      Get the buffer mode of the specified USB endpoint buffer
+  *
+  * @param[in]  ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
+  *
+  * @retval     0 USB is single buffer mode.
+  * @retval     1 USB is double buffer mode.
+  *
+  * @details    This macro will return the buffer mode of the specified endpoint ID.
+  *
+  */
+#define USBD_IS_DB_MODE(ep)           (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) & USBD_CFG_DBEN_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) & USBD_CFG_DBEN_Msk))
+
+/**
+  * @brief      Set to active in USB double buffer mode for the specified endpoint ID
+  *
+  * @param[in]  ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
+  *
+  * @return     None
+  *
+  * @details    Set DBTGACTIVE bit of USB_CFGx register for toggle active in the double buffer mode of the specified endpoint ID.
+  *
+  */
+#define USBD_SET_DB_ACTIVE(ep)        (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DBTGACTIVE_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DBTGACTIVE_Msk))
+
+/**
+  * @brief      Set to inactive in USB double buffer mode for the specified endpoint ID
+  *
+  * @param[in]  ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
+  *
+  * @return     None
+  *
+  * @details    Clear DBTGACTIVE bit of USB_CFGx register for toggle inactive in the double buffer mode of the specified endpoint ID.
+  *
+  */
+#define USBD_SET_DB_INACTIVE(ep)      (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DBTGACTIVE_Msk)):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DBTGACTIVE_Msk)))
+
+/**
+  * @brief      To support byte access between USB SRAM and system SRAM
+  *
+  * @param[in]  dest Destination pointer.
+  *
+  * @param[in]  src  Source pointer.
+  *
+  * @param[in]  size Byte count.
+  *
+  * @return     None
+  *
+  * @details    This function will copy the number of data specified by size and src parameters to the address specified by dest parameter.
+  *
+  */
+__STATIC_INLINE void USBD_MemCopy(uint8_t dest[], uint8_t src[], uint32_t size)
+{
+    uint32_t volatile i = 0UL;
+
+    while(size--)
+    {
+        dest[i] = src[i];
+        i++;
+    }
+}
+
+/**
+  * @brief       Set USB endpoint stall state
+  *
+  * @param[in]   epnum  USB endpoint number
+  *
+  * @return      None
+  *
+  * @details     Set USB endpoint stall state. Endpoint will respond STALL token automatically.
+  *
+  */
+__STATIC_INLINE void USBD_SetStall(uint8_t epnum)
+{
+    uint32_t u32CfgAddr;
+    uint32_t u32Cfg;
+    uint32_t i;
+    USBD_T *pUSBD;
+
+    if((__PC() & NS_OFFSET) == NS_OFFSET)
+    {
+        pUSBD = USBD_NS;
+    }
+    else
+    {
+        pUSBD = USBD;
+    }
+
+    for(i = 0UL; i < USBD_MAX_EP; i++)
+    {
+        u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&pUSBD->EP[0].CFG; /* USBD_CFG0 */
+        u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
+
+        if((u32Cfg & 0xFUL) == epnum)
+        {
+            u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&pUSBD->EP[0].CFGP; /* USBD_CFGP0 */
+            u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
+
+            *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg | USBD_CFGP_SSTALL);
+            break;
+        }
+    }
+}
+
+/**
+  * @brief       Clear USB endpoint stall state
+  *
+  * @param[in]   epnum  USB endpoint number
+  *
+  * @return      None
+  *
+  * @details     Clear USB endpoint stall state. Endpoint will respond ACK/NAK token.
+  */
+__STATIC_INLINE void USBD_ClearStall(uint8_t epnum)
+{
+    uint32_t u32CfgAddr;
+    uint32_t u32Cfg;
+    uint32_t i;
+    USBD_T *pUSBD;
+
+    if((__PC() & NS_OFFSET) == NS_OFFSET)
+    {
+        pUSBD = USBD_NS;
+    }
+    else
+    {
+        pUSBD = USBD;
+    }
+
+    for(i = 0UL; i < USBD_MAX_EP; i++)
+    {
+        u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&pUSBD->EP[0].CFG; /* USBD_CFG0 */
+        u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
+
+        if((u32Cfg & 0xFUL) == epnum)
+        {
+            u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&pUSBD->EP[0].CFGP; /* USBD_CFGP0 */
+            u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
+
+            *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg & ~USBD_CFGP_SSTALL);
+            break;
+        }
+    }
+}
+
+/**
+  * @brief       Get USB endpoint stall state
+  *
+  * @param[in]   epnum  USB endpoint number
+  *
+  * @retval      0      USB endpoint is not stalled.
+  * @retval      Others USB endpoint is stalled.
+  *
+  * @details     Get USB endpoint stall state.
+  *
+  */
+__STATIC_INLINE uint32_t USBD_GetStall(uint8_t epnum)
+{
+    uint32_t u32CfgAddr = 0UL;
+    uint32_t u32Cfg;
+    uint32_t i;
+    USBD_T *pUSBD;
+
+    if((__PC() & NS_OFFSET) == NS_OFFSET)
+    {
+        pUSBD = USBD_NS;
+    }
+    else
+    {
+        pUSBD = USBD;
+    }
+
+    for(i = 0UL; i < USBD_MAX_EP; i++)
+    {
+        u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&pUSBD->EP[0].CFG; /* USBD_CFG0 */
+        u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
+
+        if((u32Cfg & 0xFUL) == epnum)
+        {
+            u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&pUSBD->EP[0].CFGP; /* USBD_CFGP0 */
+            break;
+        }
+    }
+
+    return ((*((__IO uint32_t *)(u32CfgAddr))) & USBD_CFGP_SSTALL);
+}
+
+extern uint8_t g_USBD_au8SetupPacket[8];
+extern volatile uint8_t g_USBD_u8RemoteWakeupEn;
+
+typedef void (*VENDOR_REQ)(void);           /*!< Functional pointer type definition for Vendor class */
+typedef void (*CLASS_REQ)(void);            /*!< Functional pointer type declaration for USB class request callback handler */
+typedef void (*SET_INTERFACE_REQ)(uint32_t u32AltInterface);    /*!< Functional pointer type declaration for USB set interface request callback handler */
+typedef void (*SET_CONFIG_CB)(void);       /*!< Functional pointer type declaration for USB set configuration request callback handler */
+
+extern const S_USBD_INFO_T *g_USBD_sInfo;
+
+extern VENDOR_REQ g_USBD_pfnVendorRequest;
+extern CLASS_REQ g_USBD_pfnClassRequest;
+extern SET_INTERFACE_REQ g_USBD_pfnSetInterface;
+extern SET_CONFIG_CB g_USBD_pfnSetConfigCallback;
+extern uint32_t g_USBD_u32EpStallLock;
+
+/*--------------------------------------------------------------------*/
+void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface);
+void USBD_Start(void);
+void USBD_GetSetupPacket(uint8_t *buf);
+void USBD_ProcessSetupPacket(void);
+void USBD_GetDescriptor(void);
+void USBD_StandardRequest(void);
+void USBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size);
+void USBD_CtrlIn(void);
+void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size);
+void USBD_CtrlOut(void);
+void USBD_SwReset(void);
+void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq);
+void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback);
+void USBD_LockEpStall(uint32_t u32EpBitmap);
+
+
+/**@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group USBD_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_USBD_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_usci_i2c.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_usci_i2c.h
new file mode 100644
index 0000000000..e62975971e
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_usci_i2c.h
@@ -0,0 +1,318 @@
+/**************************************************************************//**
+ * @file     nu_usci_i2c.h
+ * @version  V3.0
+ * $Revision: 1 $
+ * $Date: 16/07/07 7:50p $
+ * @brief    M2355 series USCI I2C(UI2C) driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef __NU_USCI_I2C_H__
+#define __NU_USCI_I2C_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup USCI_I2C_Driver USCI_I2C Driver
+  @{
+*/
+
+/** @addtogroup USCI_I2C_EXPORTED_CONSTANTS USCI_I2C Exported Constants
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* USCI_I2C master event definitions                                                                       */
+/*---------------------------------------------------------------------------------------------------------*/
+enum UI2C_MASTER_EVENT
+{
+    MASTER_SEND_ADDRESS = 10u,    /*!< Master send address to Slave */
+    MASTER_SEND_H_WR_ADDRESS,    /*!< Master send High address to Slave */
+    MASTER_SEND_H_RD_ADDRESS,    /*!< Master send address to Slave (Read ADDR) */
+    MASTER_SEND_L_ADDRESS,       /*!< Master send Low address to Slave */
+    MASTER_SEND_DATA,            /*!< Master Send Data to Slave */
+    MASTER_SEND_REPEAT_START,    /*!< Master send repeat start to Slave */
+    MASTER_READ_DATA,            /*!< Master Get Data from Slave */
+    MASTER_STOP,                 /*!< Master send stop to Slave */
+    MASTER_SEND_START            /*!< Master send start to Slave */
+};
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* USCI_I2C slave event definitions                                                                        */
+/*---------------------------------------------------------------------------------------------------------*/
+enum UI2C_SLAVE_EVENT
+{
+    SLAVE_ADDRESS_ACK = 100u,      /*!< Slave send address ACK */
+    SLAVE_H_WR_ADDRESS_ACK,       /*!< Slave send High address ACK */
+    SLAVE_L_WR_ADDRESS_ACK,       /*!< Slave send Low address ACK */
+    SLAVE_GET_DATA,               /*!< Slave Get Data from Master (Write CMD) */
+    SLAVE_SEND_DATA,              /*!< Slave Send Data to Master (Read CMD) */
+    SLAVE_H_RD_ADDRESS_ACK,       /*!< Slave send High address ACK */
+    SLAVE_L_RD_ADDRESS_ACK        /*!< Slave send Low address ACK */
+};
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  USCI_CTL constant definitions.                                                                         */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UI2C_CTL_PTRG              (0x20U)    /*!< USCI_CTL setting for I2C control bits. It would set PTRG bit */
+#define UI2C_CTL_STA               (0x08U)    /*!< USCI_CTL setting for I2C control bits. It would set STA bit */
+#define UI2C_CTL_STO               (0x04U)    /*!< USCI_CTL setting for I2C control bits. It would set STO bit */
+#define UI2C_CTL_AA                (0x02U)    /*!< USCI_CTL setting for I2C control bits. It would set AA bit  */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  USCI_I2C GCMode constant definitions.                                                                  */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UI2C_GCMODE_ENABLE         (1U)    /*!< Enable  USCI_I2C GC Mode */
+#define UI2C_GCMODE_DISABLE        (0U)    /*!< Disable USCI_I2C GC Mode */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  USCI_I2C Wakeup Mode constant definitions.                                                             */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UI2C_DATA_TOGGLE_WK        (0x0U << UI2C_WKCTL_WKADDREN_Pos)    /*!< Wakeup according data toggle */
+#define UI2C_ADDR_MATCH_WK         (0x1U << UI2C_WKCTL_WKADDREN_Pos)    /*!< Wakeup according address match */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* USCI_I2C interrupt mask definitions                                                                     */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UI2C_TO_INT_MASK           (0x001U)    /*!< Time-out interrupt mask */
+#define UI2C_STAR_INT_MASK         (0x002U)    /*!< Start condition received interrupt mask */
+#define UI2C_STOR_INT_MASK         (0x004U)    /*!< Stop condition received interrupt mask */
+#define UI2C_NACK_INT_MASK         (0x008U)    /*!< Non-acknowledge interrupt mask */
+#define UI2C_ARBLO_INT_MASK        (0x010U)    /*!< Arbitration lost interrupt mask */
+#define UI2C_ERR_INT_MASK          (0x020U)    /*!< Error interrupt mask */
+#define UI2C_ACK_INT_MASK          (0x040U)    /*!< Acknowledge interrupt mask */
+
+/**@}*/ /* end of group USCI_I2C_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup USCI_I2C_EXPORTED_FUNCTIONS USCI_I2C Exported Functions
+  @{
+*/
+
+/**
+ *    @brief        This macro sets the USCI_I2C protocol control register at one time
+ *
+ *    @param[in]    ui2c      The pointer of the specified USCI_I2C module.
+ *    @param[in]    u8Ctrl    Set the register value of USCI_I2C control register.
+ *
+ *    @return       None
+ *
+ *    @details      Set UI2C_PROTCTL register to control USCI_I2C bus conditions of START, STOP, PTRG, ACK.
+ */
+#define UI2C_SET_CONTROL_REG(ui2c, u8Ctrl) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~0x2EU) | (u8Ctrl))
+
+/**
+ *    @brief        This macro only set START bit to protocol control register of USCI_I2C module.
+ *
+ *    @param[in]    ui2c      The pointer of the specified USCI_I2C module.
+ *
+ *    @return       None
+ *
+ *    @details      Set the USCI_I2C bus START condition in UI2C_PROTCTL register.
+ */
+#define UI2C_START(ui2c) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~UI2C_PROTCTL_PTRG_Msk) | UI2C_PROTCTL_STA_Msk)
+
+/**
+ *    @brief        This macro only set STOP bit to the control register of USCI_I2C module
+ *
+ *    @param[in]    ui2c      The pointer of the specified USCI_I2C module.
+ *
+ *    @return       None
+ *
+ *    @details      Set the USCI_I2C bus STOP condition in UI2C_PROTCTL register.
+ */
+#define UI2C_STOP(ui2c) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~0x2E) | (UI2C_PROTCTL_PTRG_Msk | UI2C_PROTCTL_STO_Msk))
+
+/**
+ *    @brief        This macro returns the data stored in data register of USCI_I2C module
+ *
+ *    @param[in]    ui2c      The pointer of the specified USCI_I2C module.
+ *
+ *    @return       Data
+ *
+ *    @details      Read a byte data value of UI2C_RXDAT register from USCI_I2C bus
+ */
+#define UI2C_GET_DATA(ui2c) ((ui2c)->RXDAT)
+
+/**
+ *    @brief        This macro writes the data to data register of USCI_I2C module
+ *
+ *    @param[in]    ui2c     The pointer of the specified USCI_I2C module.
+ *    @param[in]    u8Data   The data which will be written to data register of USCI_I2C module.
+ *
+ *    @return       None
+ *
+ *    @details      Write a byte data value of UI2C_TXDAT register, then sends address or data to USCI I2C bus
+ */
+#define UI2C_SET_DATA(ui2c, u8Data) ((ui2c)->TXDAT = (u8Data))
+
+/**
+ *    @brief        This macro returns time-out flag
+ *
+ *    @param[in]    ui2c     The pointer of the specified USCI_I2C module.
+ *
+ *    @retval       0        USCI_I2C bus time-out is not happened
+ *    @retval       1        USCI_I2C bus time-out is happened
+ *
+ *    @details      USCI_I2C bus occurs time-out event, the time-out flag will be set. If not occurs time-out event, this bit is cleared.
+ */
+#define UI2C_GET_TIMEOUT_FLAG(ui2c) (((ui2c)->PROTSTS & UI2C_PROTSTS_TOIF_Msk) == UI2C_PROTSTS_TOIF_Msk ? 1:0)
+
+/**
+ *    @brief        This macro returns wake-up flag
+ *
+ *    @param[in]    ui2c     The pointer of the specified USCI_I2C module.
+ *
+ *    @retval       0        Chip is not woken-up from power-down mode
+ *    @retval       1        Chip is woken-up from power-down mode
+ *
+ *    @details      USCI_I2C controller wake-up flag will be set when USCI_I2C bus occurs wake-up from deep-sleep.
+ */
+#define UI2C_GET_WAKEUP_FLAG(ui2c) (((ui2c)->WKSTS & UI2C_WKSTS_WKF_Msk) == UI2C_WKSTS_WKF_Msk ? 1:0)
+
+/**
+ *    @brief        This macro is used to clear USCI_I2C wake-up flag
+ *
+ *    @param[in]    ui2c     The pointer of the specified USCI_I2C module.
+ *
+ *    @return       None
+ *
+ *    @details      If USCI_I2C wake-up flag is set, use this macro to clear it.
+ */
+#define UI2C_CLR_WAKEUP_FLAG(ui2c)  ((ui2c)->WKSTS = UI2C_WKSTS_WKF_Msk)
+
+/**
+ *    @brief        This macro disables the USCI_I2C 10-bit address mode
+ *
+ *    @param[in]    ui2c     The pointer of the specified USCI_I2C module.
+ *
+ *    @return       None
+ *
+ *    @details      The UI2C_I2C is 7-bit address mode, when disable USCI_I2C 10-bit address match function.
+ */
+#define UI2C_DISABLE_10BIT_ADDR_MODE(ui2c)  ((ui2c)->PROTCTL &= ~(UI2C_PROTCTL_ADDR10EN_Msk))
+
+/**
+ *    @brief        This macro enables the 10-bit address mode
+ *
+ *    @param[in]    ui2c     The pointer of the specified USCI_I2C module.
+ *
+ *    @return       None
+ *
+ *    @details      To enable USCI_I2C 10-bit address match function.
+ */
+#define UI2C_ENABLE_10BIT_ADDR_MODE(ui2c)  ((ui2c)->PROTCTL |= UI2C_PROTCTL_ADDR10EN_Msk)
+
+/**
+ *    @brief        This macro gets USCI_I2C protocol interrupt flag or bus status
+ *
+ *    @param[in]    ui2c     The pointer of the specified USCI_I2C module.
+ *
+ *    @return       A word data of USCI_I2C_PROTSTS register
+ *
+ *    @details      Read a word data of USCI_I2C PROTSTS register to get USCI_I2C bus Interrupt flags or status.
+ */
+#define UI2C_GET_PROT_STATUS(ui2c)    ((ui2c)->PROTSTS)
+
+/**
+ *    @brief        This macro clears specified protocol interrupt flag
+ *    @param[in]    ui2c     The pointer of the specified USCI_I2C module.
+ *    @param[in]    u32IntTypeFlag Interrupt Type Flag, should be
+ *                                  - \ref UI2C_PROTSTS_ACKIF_Msk
+ *                                  - \ref UI2C_PROTSTS_ERRIF_Msk
+ *                                  - \ref UI2C_PROTSTS_ARBLOIF_Msk
+ *                                  - \ref UI2C_PROTSTS_NACKIF_Msk
+ *                                  - \ref UI2C_PROTSTS_STORIF_Msk
+ *                                  - \ref UI2C_PROTSTS_STARIF_Msk
+ *                                  - \ref UI2C_PROTSTS_TOIF_Msk
+ *    @return None
+ *
+ *    @details      To clear interrupt flag when USCI_I2C occurs interrupt and set interrupt flag.
+ */
+#define UI2C_CLR_PROT_INT_FLAG(ui2c,u32IntTypeFlag)    ((ui2c)->PROTSTS = (u32IntTypeFlag))
+
+/**
+ *    @brief        This macro enables specified protocol interrupt
+ *    @param[in]    ui2c     The pointer of the specified USCI_I2C module.
+ *    @param[in]    u32IntSel Interrupt Type, should be
+ *                                  - \ref UI2C_PROTIEN_ACKIEN_Msk
+ *                                  - \ref UI2C_PROTIEN_ERRIEN_Msk
+ *                                  - \ref UI2C_PROTIEN_ARBLOIEN_Msk
+ *                                  - \ref UI2C_PROTIEN_NACKIEN_Msk
+ *                                  - \ref UI2C_PROTIEN_STORIEN_Msk
+ *                                  - \ref UI2C_PROTIEN_STARIEN_Msk
+ *                                  - \ref UI2C_PROTIEN_TOIEN_Msk
+ *    @return None
+ *
+ *    @details      Set specified USCI_I2C protocol interrupt bits to enable interrupt function.
+ */
+#define UI2C_ENABLE_PROT_INT(ui2c, u32IntSel)    ((ui2c)->PROTIEN |= (u32IntSel))
+
+/**
+ *    @brief        This macro disables specified protocol interrupt
+ *    @param[in]    ui2c     The pointer of the specified USCI_I2C module.
+ *    @param[in]    u32IntSel Interrupt Type, should be
+ *                                  - \ref UI2C_PROTIEN_ACKIEN_Msk
+ *                                  - \ref UI2C_PROTIEN_ERRIEN_Msk
+ *                                  - \ref UI2C_PROTIEN_ARBLOIEN_Msk
+ *                                  - \ref UI2C_PROTIEN_NACKIEN_Msk
+ *                                  - \ref UI2C_PROTIEN_STORIEN_Msk
+ *                                  - \ref UI2C_PROTIEN_STARIEN_Msk
+ *                                  - \ref UI2C_PROTIEN_TOIEN_Msk
+ *    @return None
+ *
+ *    @details      Clear specified USCI_I2C protocol interrupt bits to disable interrupt funtion.
+ */
+#define UI2C_DISABLE_PROT_INT(ui2c, u32IntSel)    ((ui2c)->PROTIEN &= ~ (u32IntSel))
+
+
+uint32_t UI2C_Open(UI2C_T *ui2c, uint32_t u32BusClock);
+void UI2C_Close(UI2C_T *ui2c);
+void UI2C_ClearTimeoutFlag(UI2C_T *ui2c);
+void UI2C_Trigger(UI2C_T *ui2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Ptrg, uint8_t u8Ack);
+void UI2C_DisableInt(UI2C_T *ui2c, uint32_t u32Mask);
+void UI2C_EnableInt(UI2C_T *ui2c, uint32_t u32Mask);
+uint32_t UI2C_GetBusClockFreq(UI2C_T *ui2c);
+uint32_t UI2C_SetBusClockFreq(UI2C_T *ui2c, uint32_t u32BusClock);
+uint32_t UI2C_GetIntFlag(UI2C_T *ui2c, uint32_t u32Mask);
+void UI2C_ClearIntFlag(UI2C_T* ui2c, uint32_t u32Mask);
+uint32_t UI2C_GetData(UI2C_T *ui2c);
+void UI2C_SetData(UI2C_T *ui2c, uint8_t u8Data);
+void UI2C_SetSlaveAddr(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddr, uint8_t u8GCMode);
+void UI2C_SetSlaveAddrMask(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddrMask);
+void UI2C_EnableTimeout(UI2C_T *ui2c, uint32_t u32TimeoutCnt);
+void UI2C_DisableTimeout(UI2C_T *ui2c);
+void UI2C_EnableWakeup(UI2C_T *ui2c, uint8_t u8WakeupMode);
+void UI2C_DisableWakeup(UI2C_T *ui2c);
+uint8_t UI2C_WriteByte(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t data);
+uint32_t UI2C_WriteMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen);
+uint8_t UI2C_WriteByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data);
+uint32_t UI2C_WriteMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen);
+uint8_t UI2C_WriteByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data);
+uint32_t UI2C_WriteMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen);
+uint8_t UI2C_ReadByte(UI2C_T *ui2c, uint8_t u8SlaveAddr);
+uint32_t UI2C_ReadMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen);
+uint8_t UI2C_ReadByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr);
+uint32_t UI2C_ReadMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen);
+uint8_t UI2C_ReadByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr);
+uint32_t UI2C_ReadMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen);
+/**@}*/ /* end of group USCI_I2C_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group USCI_I2C_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_usci_spi.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_usci_spi.h
new file mode 100644
index 0000000000..6689bd31d7
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_usci_spi.h
@@ -0,0 +1,420 @@
+/****************************************************************************//**
+ * @file     nu_usci_spi.h
+ * @version  V3.00
+ * @brief    M2354 series USCI_SPI driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_USCI_SPI_H__
+#define __NU_USCI_SPI_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup USCI_SPI_Driver USCI_SPI Driver
+  @{
+*/
+
+/** @addtogroup USCI_SPI_EXPORTED_CONSTANTS USCI_SPI Exported Constants
+  @{
+*/
+
+#define USPI_MODE_0        (0x0UL << USPI_PROTCTL_SCLKMODE_Pos)        /*!< SCLK idle low; data transmit with falling edge and receive with rising edge */
+#define USPI_MODE_1        (0x1UL << USPI_PROTCTL_SCLKMODE_Pos)        /*!< SCLK idle low; data transmit with rising edge and receive with falling edge */
+#define USPI_MODE_2        (0x2UL << USPI_PROTCTL_SCLKMODE_Pos)        /*!< SCLK idle high; data transmit with rising edge and receive with falling edge */
+#define USPI_MODE_3        (0x3UL << USPI_PROTCTL_SCLKMODE_Pos)        /*!< SCLK idle high; data transmit with falling edge and receive with rising edge */
+
+#define USPI_SLAVE         (USPI_PROTCTL_SLAVE_Msk)                    /*!< Set as slave */
+#define USPI_MASTER        (0x0UL)                                     /*!< Set as master */
+
+#define USPI_SS                (USPI_PROTCTL_SS_Msk)                   /*!< Set SS */
+#define USPI_SS_ACTIVE_HIGH    (0x0UL)                                 /*!< SS active high */
+#define USPI_SS_ACTIVE_LOW     (USPI_LINECTL_CTLOINV_Msk)              /*!< SS active low */
+
+/* USCI_SPI Interrupt Mask */
+#define USPI_SSINACT_INT_MASK        (0x001UL)                         /*!< Slave Slave Inactive interrupt mask */
+#define USPI_SSACT_INT_MASK          (0x002UL)                         /*!< Slave Slave Active interrupt mask */
+#define USPI_SLVTO_INT_MASK          (0x004UL)                         /*!< Slave Mode Time-out interrupt mask */
+#define USPI_SLVBE_INT_MASK          (0x008UL)                         /*!< Slave Mode Bit Count Error interrupt mask */
+#define USPI_TXUDR_INT_MASK          (0x010UL)                         /*!< Slave Transmit Under Run interrupt mask */
+#define USPI_RXOV_INT_MASK           (0x020UL)                         /*!< Receive Buffer Overrun interrupt mask */
+#define USPI_TXST_INT_MASK           (0x040UL)                         /*!< Transmit Start interrupt mask */
+#define USPI_TXEND_INT_MASK          (0x080UL)                         /*!< Transmit End interrupt mask */
+#define USPI_RXST_INT_MASK           (0x100UL)                         /*!< Receive Start interrupt mask */
+#define USPI_RXEND_INT_MASK          (0x200UL)                         /*!< Receive End interrupt mask */
+
+/* USCI_SPI Status Mask */
+#define USPI_BUSY_MASK               (0x01UL)                          /*!< Busy status mask */
+#define USPI_RX_EMPTY_MASK           (0x02UL)                          /*!< RX empty status mask */
+#define USPI_RX_FULL_MASK            (0x04UL)                          /*!< RX full status mask */
+#define USPI_TX_EMPTY_MASK           (0x08UL)                          /*!< TX empty status mask */
+#define USPI_TX_FULL_MASK            (0x10UL)                          /*!< TX full status mask */
+#define USPI_SSLINE_STS_MASK         (0x20UL)                          /*!< USCI_SPI_SS line status mask */
+
+/**@}*/ /* end of group USCI_SPI_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup USCI_SPI_EXPORTED_FUNCTIONS USCI_SPI Exported Functions
+  @{
+*/
+
+/**
+  * @brief  Disable slave 3-wire mode.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_DISABLE_3WIRE_MODE(uspi) ( (uspi)->PROTCTL &= ~USPI_PROTCTL_SLV3WIRE_Msk )
+
+/**
+  * @brief  Enable slave 3-wire mode.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_ENABLE_3WIRE_MODE(uspi) ( (uspi)->PROTCTL |= USPI_PROTCTL_SLV3WIRE_Msk )
+
+/**
+  * @brief  Get the Rx buffer empty flag.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return Rx buffer flag
+  * @retval 0: Rx buffer is not empty
+  * @retval 1: Rx buffer is empty
+  * \hideinitializer
+  */
+#define USPI_GET_RX_EMPTY_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_RXEMPTY_Msk) == USPI_BUFSTS_RXEMPTY_Msk ? 1:0 )
+
+/**
+  * @brief  Get the Tx buffer empty flag.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return Tx buffer flag
+  * @retval 0: Tx buffer is not empty
+  * @retval 1: Tx buffer is empty
+  * \hideinitializer
+  */
+#define USPI_GET_TX_EMPTY_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_TXEMPTY_Msk) == USPI_BUFSTS_TXEMPTY_Msk ? 1:0 )
+
+/**
+  * @brief  Get the Tx buffer full flag.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return Tx buffer flag
+  * @retval 0: Tx buffer is not full
+  * @retval 1: Tx buffer is full
+  * \hideinitializer
+  */
+#define USPI_GET_TX_FULL_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_TXFULL_Msk) == USPI_BUFSTS_TXFULL_Msk ? 1:0 )
+
+/**
+  * @brief  Get the datum read from RX register.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return data in Rx register
+  * \hideinitializer
+  */
+#define USPI_READ_RX(uspi) ( (uspi)->RXDAT )
+
+/**
+  * @brief  Write datum to TX register.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @param[in]  u32TxData The datum which user attempt to transfer through USCI_SPI bus.
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_WRITE_TX(uspi, u32TxData) ( (uspi)->TXDAT = (u32TxData) )
+
+/**
+  * @brief      Set USCI_SPI_SS pin to high state.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return     None.
+  * @details    Disable automatic slave selection function and set USCI_SPI_SS pin to high state. Only available in Master mode.
+  * \hideinitializer
+  */
+#define USPI_SET_SS_HIGH(uspi) \
+    do{ \
+        (uspi)->LINECTL &= ~USPI_LINECTL_CTLOINV_Msk; \
+        (uspi)->PROTCTL = (((uspi)->PROTCTL & ~USPI_PROTCTL_AUTOSS_Msk) | USPI_PROTCTL_SS_Msk); \
+    }while(0)
+
+/**
+  * @brief      Set USCI_SPI_SS pin to low state.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return     None.
+  * @details    Disable automatic slave selection function and set USCI_SPI_SS pin to low state. Only available in Master mode.
+  * \hideinitializer
+  */
+#define USPI_SET_SS_LOW(uspi) \
+    do{ \
+        (uspi)->LINECTL |= USPI_LINECTL_CTLOINV_Msk; \
+        (uspi)->PROTCTL = (((uspi)->PROTCTL & ~USPI_PROTCTL_AUTOSS_Msk) | USPI_PROTCTL_SS_Msk); \
+    }while(0)
+
+/**
+  * @brief  Set the length of suspend interval.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @param[in]  u32SuspCycle Decide the length of suspend interval.
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_SET_SUSPEND_CYCLE(uspi, u32SuspCycle) ( (uspi)->PROTCTL = ((uspi)->PROTCTL & ~USPI_PROTCTL_SUSPITV_Msk) | ((u32SuspCycle) << USPI_PROTCTL_SUSPITV_Pos) )
+
+/**
+  * @brief  Set the USCI_SPI transfer sequence with LSB first.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_SET_LSB_FIRST(uspi) ( (uspi)->LINECTL |= USPI_LINECTL_LSB_Msk )
+
+/**
+  * @brief  Set the USCI_SPI transfer sequence with MSB first.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_SET_MSB_FIRST(uspi) ( (uspi)->LINECTL &= ~USPI_LINECTL_LSB_Msk )
+
+/**
+  * @brief  Set the data width of a USCI_SPI transaction.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @param[in]  u32Width The data width
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_SET_DATA_WIDTH(uspi, u32Width) \
+    do{ \
+      if((u32Width) == 16ul){ \
+        (uspi)->LINECTL = ((uspi)->LINECTL & ~USPI_LINECTL_DWIDTH_Msk) | (0 << USPI_LINECTL_DWIDTH_Pos); \
+      }else { \
+        (uspi)->LINECTL = ((uspi)->LINECTL & ~USPI_LINECTL_DWIDTH_Msk) | ((u32Width) << USPI_LINECTL_DWIDTH_Pos); \
+      } \
+    }while(0)
+
+/**
+  * @brief  Get the USCI_SPI busy state.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return USCI_SPI busy status
+  * @retval 0: USCI_SPI module is not busy
+  * @retval 1: USCI_SPI module is busy
+  * \hideinitializer
+  */
+#define USPI_IS_BUSY(uspi) ( ((uspi)->PROTSTS & USPI_PROTSTS_BUSY_Msk) == USPI_PROTSTS_BUSY_Msk ? 1:0 )
+
+/**
+  * @brief Get the USCI_SPI wakeup flag.
+  * @param[in] uspi The pointer of the specified USCI_SPI module.
+  * @return Wakeup status.
+  * @retval 0 Flag is not set.
+  * @retval 1 Flag is set.
+  * \hideinitializer
+  */
+#define USPI_GET_WAKEUP_FLAG(uspi) ( ((uspi)->WKSTS & USPI_WKSTS_WKF_Msk) == USPI_WKSTS_WKF_Msk ? 1:0 )
+
+/**
+  * @brief Clear the USCI_SPI wakeup flag.
+  * @param[in] uspi The pointer of the specified USCI_SPI module.
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_CLR_WAKEUP_FLAG(uspi) ( (uspi)->WKSTS |= USPI_WKSTS_WKF_Msk )
+
+/**
+  * @brief Get protocol interrupt flag/status.
+  * @param[in] uspi The pointer of the specified USCI_SPI module.
+  * @return The interrupt flag/status of protocol status register.
+  * \hideinitializer
+  */
+#define USPI_GET_PROT_STATUS(uspi) ( (uspi)->PROTSTS )
+
+/**
+  * @brief Clear specified protocol interrupt flag.
+  * @param[in] uspi The pointer of the specified USCI_SPI module.
+  * @param[in] u32IntTypeFlag Interrupt Type Flag, should be
+  *                                  - \ref USPI_PROTSTS_SSACTIF_Msk
+  *                                  - \ref USPI_PROTSTS_SSINAIF_Msk
+  *                                  - \ref USPI_PROTSTS_SLVBEIF_Msk
+  *                                  - \ref USPI_PROTSTS_SLVTOIF_Msk
+  *                                  - \ref USPI_PROTSTS_RXENDIF_Msk
+  *                                  - \ref USPI_PROTSTS_RXSTIF_Msk
+  *                                  - \ref USPI_PROTSTS_TXENDIF_Msk
+  *                                  - \ref USPI_PROTSTS_TXSTIF_Msk
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_CLR_PROT_INT_FLAG(uspi, u32IntTypeFlag) ( (uspi)->PROTSTS = (u32IntTypeFlag) )
+
+/**
+  * @brief Get buffer interrupt flag/status.
+  * @param[in] uspi The pointer of the specified USCI_SPI module.
+  * @return The interrupt flag/status of buffer status register.
+  * \hideinitializer
+  */
+#define USPI_GET_BUF_STATUS(uspi) ( (uspi)->BUFSTS )
+
+/**
+  * @brief Clear specified buffer interrupt flag.
+  * @param[in] uspi The pointer of the specified USCI_SPI module.
+  * @param[in] u32IntTypeFlag Interrupt Type Flag, should be
+  *                                  - \ref USPI_BUFSTS_TXUDRIF_Msk
+  *                                  - \ref USPI_BUFSTS_RXOVIF_Msk
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_CLR_BUF_INT_FLAG(uspi, u32IntTypeFlag) ( (uspi)->BUFSTS = (u32IntTypeFlag) )
+
+/**
+  * @brief Enable specified protocol interrupt.
+  * @param[in] uspi The pointer of the specified USCI_SPI module.
+  * @param[in] u32IntSel Interrupt Type, should be
+  *                                  - \ref USPI_PROTIEN_SLVBEIEN_Msk
+  *                                  - \ref USPI_PROTIEN_SLVTOIEN_Msk
+  *                                  - \ref USPI_PROTIEN_SSACTIEN_Msk
+  *                                  - \ref USPI_PROTIEN_SSINAIEN_Msk
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_ENABLE_PROT_INT(uspi, u32IntSel) ( (uspi)->PROTIEN |= (u32IntSel) )
+
+/**
+  * @brief Disable specified protocol interrupt.
+  * @param[in] uspi The pointer of the specified USCI_SPI module.
+  * @param[in] u32IntSel Interrupt Type, should be
+  *                                  - \ref USPI_PROTIEN_SLVBEIEN_Msk
+  *                                  - \ref USPI_PROTIEN_SLVTOIEN_Msk
+  *                                  - \ref USPI_PROTIEN_SSACTIEN_Msk
+  *                                  - \ref USPI_PROTIEN_SSINAIEN_Msk
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_DISABLE_PROT_INT(uspi, u32IntSel) ( (uspi)->PROTIEN &= ~ (u32IntSel) )
+
+/**
+  * @brief Enable specified buffer interrupt.
+  * @param[in] uspi The pointer of the specified USCI_SPI module.
+  * @param[in] u32IntSel Interrupt Type, should be
+  *                                  - \ref USPI_BUFCTL_RXOVIEN_Msk
+  *                                  - \ref USPI_BUFCTL_TXUDRIEN_Msk
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_ENABLE_BUF_INT(uspi, u32IntSel) ( (uspi)->BUFCTL |= (u32IntSel) )
+
+/**
+  * @brief Disable specified buffer interrupt.
+  * @param[in] uspi The pointer of the specified USCI_SPI module.
+  * @param[in] u32IntSel Interrupt Type, should be
+  *                                  - \ref USPI_BUFCTL_RXOVIEN_Msk
+  *                                  - \ref USPI_BUFCTL_TXUDRIEN_Msk
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_DISABLE_BUF_INT(uspi, u32IntSel) ( (uspi)->BUFCTL &= ~ (u32IntSel) )
+
+/**
+  * @brief Enable specified transfer interrupt.
+  * @param[in] uspi The pointer of the specified USCI_SPI module.
+  * @param[in] u32IntSel Interrupt Type, should be
+  *                                  - \ref USPI_INTEN_RXENDIEN_Msk
+  *                                  - \ref USPI_INTEN_RXSTIEN_Msk
+  *                                  - \ref USPI_INTEN_TXENDIEN_Msk
+  *                                  - \ref USPI_INTEN_TXSTIEN_Msk
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_ENABLE_TRANS_INT(uspi, u32IntSel) ( (uspi)->INTEN |= (u32IntSel) )
+
+/**
+  * @brief Disable specified transfer interrupt.
+  * @param[in] uspi The pointer of the specified USCI_SPI module.
+  * @param[in] u32IntSel Interrupt Type, should be
+  *                                  - \ref USPI_INTEN_RXENDIEN_Msk
+  *                                  - \ref USPI_INTEN_RXSTIEN_Msk
+  *                                  - \ref USPI_INTEN_TXENDIEN_Msk
+  *                                  - \ref USPI_INTEN_TXSTIEN_Msk
+  * @return None
+  * \hideinitializer
+  */
+#define USPI_DISABLE_TRANS_INT(uspi, u32IntSel) ( (uspi)->INTEN &= ~ (u32IntSel) )
+
+/**
+  * @brief      Trigger RX PDMA function.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return     None.
+  * @details    Set RXPDMAEN bit of USPI_PDMACTL register to enable RX PDMA transfer function.
+  */
+#define USPI_TRIGGER_RX_PDMA(uspi) ( (uspi)->PDMACTL |= USPI_PDMACTL_RXPDMAEN_Msk | USPI_PDMACTL_PDMAEN_Msk )
+
+/**
+  * @brief      Trigger TX PDMA function.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return     None.
+  * @details    Set TXPDMAEN bit of USPI_PDMACTL register to enable TX PDMA transfer function.
+  */
+#define USPI_TRIGGER_TX_PDMA(uspi) ( (uspi)->PDMACTL |= USPI_PDMACTL_TXPDMAEN_Msk | USPI_PDMACTL_PDMAEN_Msk )
+
+/**
+  * @brief      Trigger TX and RX PDMA function.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return     None.
+  * @details    Set TXPDMAEN bit and RXPDMAEN bit of USPI_PDMACTL register to enable TX and RX PDMA transfer function.
+  */
+#define USPI_TRIGGER_TX_RX_PDMA(uspi) ( (uspi)->PDMACTL |= USPI_PDMACTL_TXPDMAEN_Msk | USPI_PDMACTL_RXPDMAEN_Msk | USPI_PDMACTL_PDMAEN_Msk )
+
+/**
+  * @brief      Disable RX PDMA transfer.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return     None.
+  * @details    Clear RXPDMAEN bit of USPI_PDMACTL register to disable RX PDMA transfer function.
+  */
+#define USPI_DISABLE_RX_PDMA(uspi) ( (uspi)->PDMACTL &= ~USPI_PDMACTL_RXPDMAEN_Msk )
+
+/**
+  * @brief      Disable TX PDMA transfer.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return     None.
+  * @details    Clear TXPDMAEN bit of USPI_PDMACTL register to disable TX PDMA transfer function.
+  */
+#define USPI_DISABLE_TX_PDMA(uspi) ( (uspi)->PDMACTL &= ~USPI_PDMACTL_TXPDMAEN_Msk )
+
+/**
+  * @brief      Disable TX and RX PDMA transfer.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return     None.
+  * @details    Clear TXPDMAEN bit and RXPDMAEN bit of USPI_PDMACTL register to disable TX and RX PDMA transfer function.
+  */
+#define USPI_DISABLE_TX_RX_PDMA(uspi) ( (uspi)->PDMACTL &= ~(USPI_PDMACTL_TXPDMAEN_Msk | USPI_PDMACTL_RXPDMAEN_Msk) )
+
+uint32_t USPI_Open(USPI_T *uspi, uint32_t u32MasterSlave, uint32_t u32SPIMode,  uint32_t u32DataWidth, uint32_t u32BusClock);
+void USPI_Close(USPI_T *uspi);
+void USPI_ClearRxBuf(USPI_T *uspi);
+void USPI_ClearTxBuf(USPI_T *uspi);
+void USPI_DisableAutoSS(USPI_T *uspi);
+void USPI_EnableAutoSS(USPI_T *uspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
+uint32_t USPI_SetBusClock(USPI_T *uspi, uint32_t u32BusClock);
+uint32_t USPI_GetBusClock(USPI_T *uspi);
+void USPI_EnableInt(USPI_T *uspi, uint32_t u32Mask);
+void USPI_DisableInt(USPI_T *uspi, uint32_t u32Mask);
+uint32_t USPI_GetIntFlag(USPI_T *uspi, uint32_t u32Mask);
+void USPI_ClearIntFlag(USPI_T *uspi, uint32_t u32Mask);
+uint32_t USPI_GetStatus(USPI_T *uspi, uint32_t u32Mask);
+void USPI_EnableWakeup(USPI_T *uspi);
+void USPI_DisableWakeup(USPI_T *uspi);
+
+
+/**@}*/ /* end of group USCI_SPI_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group USCI_SPI_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_USCI_SPI_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_usci_uart.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_usci_uart.h
new file mode 100644
index 0000000000..550955c252
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_usci_uart.h
@@ -0,0 +1,445 @@
+/******************************************************************************
+ * @file     nu_usci_uart.h
+ * @version  V3.00
+ * @brief    M2354 series USCI UART (UUART) driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#ifndef __NU_USCI_UART_H__
+#define __NU_USCI_UART_H__
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup USCI_UART_Driver USCI_UART Driver
+  @{
+*/
+
+/** @addtogroup USCI_UART_EXPORTED_CONSTANTS USCI_UART Exported Constants
+  @{
+*/
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UUART_LINECTL constants definitions                                                                     */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UUART_WORD_LEN_6     (6UL << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 6 bits */
+#define UUART_WORD_LEN_7     (7UL << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 7 bits */
+#define UUART_WORD_LEN_8     (8UL << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 8 bits */
+#define UUART_WORD_LEN_9     (9UL << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 9 bits */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* UUART_PROTCTL constants definitions                                                                     */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UUART_PARITY_NONE    (0x0UL << UUART_PROTCTL_PARITYEN_Pos)    /*!< UUART_PROTCTL setting to set UART as no parity */
+#define UUART_PARITY_ODD     (0x1UL << UUART_PROTCTL_PARITYEN_Pos)    /*!< UUART_PROTCTL setting to set UART as odd parity */
+#define UUART_PARITY_EVEN    (0x3UL << UUART_PROTCTL_PARITYEN_Pos)    /*!< UUART_PROTCTL setting to set UART as even parity */
+
+#define UUART_STOP_BIT_1     (0x0UL) /*!< UUART_PROTCTL setting for one stop bit */
+#define UUART_STOP_BIT_2     (0x1UL) /*!< UUART_PROTCTL setting for two stop bit */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* USCI UART interrupt mask definitions                                                                            */
+/*---------------------------------------------------------------------------------------------------------*/
+#define UUART_ABR_INT_MASK      (0x002UL) /*!< Auto-baud rate interrupt mask */
+#define UUART_RLS_INT_MASK      (0x004UL) /*!< Receive line status interrupt mask */
+#define UUART_BUF_RXOV_INT_MASK (0x008UL) /*!< Buffer RX overrun interrupt mask */
+#define UUART_TXST_INT_MASK     (0x010UL) /*!< TX start interrupt mask */
+#define UUART_TXEND_INT_MASK    (0x020UL) /*!< Tx end interrupt mask */
+#define UUART_RXST_INT_MASK     (0x040UL) /*!< RX start interrupt mask */
+#define UUART_RXEND_INT_MASK    (0x080UL) /*!< RX end interrupt mask */
+
+
+/**@}*/ /* end of group USCI_UART_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup USCI_UART_EXPORTED_FUNCTIONS USCI_UART Exported Functions
+  @{
+*/
+
+
+/**
+ *    @brief        Write USCI_UART data
+ *
+ *    @param[in]    uuart   The pointer of the specified USCI_UART module
+ *    @param[in]    u8Data  Data byte to transmit.
+ *
+ *    @return       None
+ *
+ *    @details      This macro write Data to Tx data register.
+ */
+#define UUART_WRITE(uuart, u8Data)    ((uuart)->TXDAT = (u8Data))
+
+
+/**
+ *    @brief        Read USCI_UART data
+ *
+ *    @param[in]    uuart    The pointer of the specified USCI_UART module
+ *
+ *    @return       The oldest data byte in RX buffer.
+ *
+ *    @details      This macro read Rx data register.
+ */
+#define UUART_READ(uuart)    ((uuart)->RXDAT)
+
+
+/**
+ *    @brief        Get Tx empty
+ *
+ *    @param[in]    uuart    The pointer of the specified USCI_UART module
+ *
+ *    @retval       0   Tx buffer is not empty
+ *    @retval       >=1 Tx buffer is empty
+ *
+ *    @details      This macro get Transmitter buffer empty register value.
+ */
+#define UUART_GET_TX_EMPTY(uuart)    ((uuart)->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk)
+
+
+/**
+ *    @brief        Get Rx empty
+ *
+ *    @param[in]    uuart    The pointer of the specified USCI_UART module
+ *
+ *    @retval       0   Rx buffer is not empty
+ *    @retval       >=1 Rx buffer is empty
+ *
+ *    @details      This macro get Receiver buffer empty register value.
+ */
+#define UUART_GET_RX_EMPTY(uuart)    ((uuart)->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk)
+
+
+/**
+ *    @brief        Check specified usci_uart port transmission is over.
+ *
+ *    @param[in]    uuart    The pointer of the specified USCI_UART module
+ *
+ *    @retval       0 Tx transmission is not over
+ *    @retval       1 Tx transmission is over
+ *
+ *    @details      This macro return Transmitter Empty Flag register bit value. \n
+ *                  It indicates if specified usci_uart port transmission is over nor not.
+ */
+#define UUART_IS_TX_EMPTY(uuart)    (((uuart)->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) >> UUART_BUFSTS_TXEMPTY_Pos)
+
+
+/**
+ *    @brief        Check specified usci_uart port receiver is empty.
+ *
+ *    @param[in]    uuart    The pointer of the specified USCI_UART module
+ *
+ *    @retval       0 Rx receiver is not empty
+ *    @retval       1 Rx receiver is empty
+ *
+ *    @details      This macro return Receive Empty Flag register bit value. \n
+ *                  It indicates if specified usci_uart port receiver is empty nor not.
+ */
+#define UUART_IS_RX_EMPTY(uuart)    (((uuart)->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) >> UUART_BUFSTS_RXEMPTY_Pos)
+
+
+/**
+ *    @brief        Wait specified usci_uart port transmission is over
+ *
+ *    @param[in]    uuart    The pointer of the specified USCI_UART module
+ *
+ *    @return       None
+ *
+ *    @details      This macro wait specified usci_uart port transmission is over.
+ */
+#define UUART_WAIT_TX_EMPTY(uuart)    while(!((((uuart)->BUFSTS) & UUART_BUFSTS_TXEMPTY_Msk) >> UUART_BUFSTS_TXEMPTY_Pos))
+
+
+/**
+ *    @brief        Check TX buffer is full or not
+ *
+ *    @param[in]    uuart    The pointer of the specified USCI_UART module
+ *
+ *    @retval       1 TX buffer is full
+ *    @retval       0 TX buffer is not full
+ *
+ *    @details      This macro check TX buffer is full or not.
+ */
+#define UUART_IS_TX_FULL(uuart)    (((uuart)->BUFSTS & UUART_BUFSTS_TXFULL_Msk)>>UUART_BUFSTS_TXFULL_Pos)
+
+
+/**
+ *    @brief        Check RX buffer is full or not
+ *
+ *    @param[in]    uuart    The pointer of the specified USCI_UART module
+ *
+ *    @retval       1 RX buffer is full
+ *    @retval       0 RX buffer is not full
+ *
+ *    @details      This macro check RX buffer is full or not.
+ */
+#define UUART_IS_RX_FULL(uuart)    (((uuart)->BUFSTS & UUART_BUFSTS_RXFULL_Msk)>>UUART_BUFSTS_RXFULL_Pos)
+
+
+/**
+ *    @brief        Get Tx full register value
+ *
+ *    @param[in]    uuart    The pointer of the specified USCI_UART module
+ *
+ *    @retval       0   Tx buffer is not full.
+ *    @retval       >=1 Tx buffer is full.
+ *
+ *    @details      This macro get Tx full register value.
+ */
+#define UUART_GET_TX_FULL(uuart)    ((uuart)->BUFSTS & UUART_BUFSTS_TXFULL_Msk)
+
+
+/**
+ *    @brief        Get Rx full register value
+ *
+ *    @param[in]    uuart    The pointer of the specified USCI_UART module
+ *
+ *    @retval       0   Rx buffer is not full.
+ *    @retval       >=1 Rx buffer is full.
+ *
+ *    @details      This macro get Rx full register value.
+ */
+#define UUART_GET_RX_FULL(uuart)    ((uuart)->BUFSTS & UUART_BUFSTS_RXFULL_Msk)
+
+
+/**
+ *    @brief        Enable specified USCI_UART protocol interrupt
+ *
+ *    @param[in]    uuart      The pointer of the specified USCI_UART module
+ *    @param[in]    u32IntSel  Interrupt type select
+ *                             - \ref UUART_PROTIEN_RLSIEN_Msk   : Rx Line status interrupt
+ *                             - \ref UUART_PROTIEN_ABRIEN_Msk   : Auto-baud rate interrupt
+ *
+ *    @return       None
+ *
+ *    @details      This macro enable specified USCI_UART protocol interrupt.
+ */
+#define UUART_ENABLE_PROT_INT(uuart, u32IntSel)    ((uuart)->PROTIEN |= (u32IntSel))
+
+
+/**
+ *    @brief        Disable specified USCI_UART protocol interrupt
+ *
+ *    @param[in]    uuart      The pointer of the specified USCI_UART module
+ *    @param[in]    u32IntSel  Interrupt type select
+ *                             - \ref UUART_PROTIEN_RLSIEN_Msk   : Rx Line status interrupt
+ *                             - \ref UUART_PROTIEN_ABRIEN_Msk   : Auto-baud rate interrupt
+ *
+ *    @return       None
+ *
+ *    @details      This macro disable specified USCI_UART protocol interrupt.
+ */
+#define UUART_DISABLE_PROT_INT(uuart, u32IntSel)    ((uuart)->PROTIEN &= ~(u32IntSel))
+
+
+/**
+ *    @brief        Enable specified USCI_UART buffer interrupt
+ *
+ *    @param[in]    uuart      The pointer of the specified USCI_UART module
+ *    @param[in]    u32IntSel  Interrupt type select
+ *                             - \ref UUART_BUFCTL_RXOVIEN_Msk     : Receive buffer overrun error interrupt
+ *
+ *    @return       None
+ *
+ *    @details      This macro enable specified USCI_UART buffer interrupt.
+ */
+#define UUART_ENABLE_BUF_INT(uuart, u32IntSel)    ((uuart)->BUFCTL |= (u32IntSel))
+
+
+/**
+ *    @brief        Disable specified USCI_UART buffer interrupt
+ *
+ *    @param[in]    uuart      The pointer of the specified USCI_UART module
+ *    @param[in]    u32IntSel  Interrupt type select
+ *                             - \ref UUART_BUFCTL_RXOVIEN_Msk     : Receive buffer overrun error interrupt
+ *
+ *    @return       None
+ *
+ *    @details      This macro disable specified USCI_UART buffer interrupt.
+ */
+#define UUART_DISABLE_BUF_INT(uuart, u32IntSel)    ((uuart)->BUFCTL &= ~ (u32IntSel))
+
+
+/**
+ *    @brief        Enable specified USCI_UART transfer interrupt
+ *
+ *    @param[in]    uuart      The pointer of the specified USCI_UART module
+ *    @param[in]    u32IntSel  Interrupt type select
+ *                             - \ref UUART_INTEN_RXENDIEN_Msk  : Receive end interrupt
+ *                             - \ref UUART_INTEN_RXSTIEN_Msk   : Receive start interrupt
+ *                             - \ref UUART_INTEN_TXENDIEN_Msk  : Transmit end interrupt
+ *                             - \ref UUART_INTEN_TXSTIEN_Msk   : Transmit start interrupt
+ *
+ *    @return       None
+ *
+ *    @details      This macro enable specified USCI_UART transfer interrupt.
+ */
+#define UUART_ENABLE_TRANS_INT(uuart, u32IntSel)    ((uuart)->INTEN |= (u32IntSel))
+
+
+/**
+ *    @brief        Disable specified USCI_UART transfer interrupt
+ *
+ *    @param[in]    uuart      The pointer of the specified USCI_UART module
+ *    @param[in]    u32IntSel  Interrupt type select
+ *                             - \ref UUART_INTEN_RXENDIEN_Msk  : Receive end interrupt
+ *                             - \ref UUART_INTEN_RXSTIEN_Msk   : Receive start interrupt
+ *                             - \ref UUART_INTEN_TXENDIEN_Msk  : Transmit end interrupt
+ *                             - \ref UUART_INTEN_TXSTIEN_Msk   : Transmit start interrupt
+ *
+ *    @return       None
+ *
+ *    @details      This macro disable specified USCI_UART transfer interrupt.
+ */
+#define UUART_DISABLE_TRANS_INT(uuart, u32IntSel)    ((uuart)->INTEN &= ~(u32IntSel))
+
+
+/**
+ *    @brief        Get protocol interrupt flag/status
+ *
+ *    @param[in]    uuart        The pointer of the specified USCI_UART module
+ *
+ *    @return       The interrupt flag/status of protocol status register.
+ *
+ *    @details      This macro get protocol status register value.
+ */
+#define UUART_GET_PROT_STATUS(uuart)    ((uuart)->PROTSTS)
+
+
+/**
+ *    @brief        Clear specified protocol interrupt flag
+ *
+ *    @param[in]    uuart           The pointer of the specified USCI_UART module
+ *    @param[in]    u32IntTypeFlag  Interrupt Type Flag, should be
+ *                                  - \ref UUART_PROTSTS_ABERRSTS_Msk    : Auto-baud Rate Error Interrupt Indicator
+ *                                  - \ref UUART_PROTSTS_ABRDETIF_Msk    : Auto-baud Rate Detected Interrupt Flag
+ *                                  - \ref UUART_PROTSTS_BREAK_Msk       : Break Flag
+ *                                  - \ref UUART_PROTSTS_FRMERR_Msk      : Framing Error Flag
+ *                                  - \ref UUART_PROTSTS_PARITYERR_Msk   : Parity Error Flag
+ *                                  - \ref UUART_PROTSTS_RXENDIF_Msk     : Receive End Interrupt Flag
+ *                                  - \ref UUART_PROTSTS_RXSTIF_Msk      : Receive Start Interrupt Flag
+ *                                  - \ref UUART_PROTSTS_TXENDIF_Msk     : Transmit End Interrupt Flag
+ *                                  - \ref UUART_PROTSTS_TXSTIF_Msk      : Transmit Start Interrupt Flag
+ *
+ *    @return       None
+ *
+ *    @details      This macro clear specified protocol interrupt flag.
+ */
+#define UUART_CLR_PROT_INT_FLAG(uuart,u32IntTypeFlag)    ((uuart)->PROTSTS = (u32IntTypeFlag))
+
+
+/**
+ *    @brief        Get transmit/receive buffer interrupt flag/status
+ *
+ *    @param[in]    uuart        The pointer of the specified USCI_UART module
+ *
+ *    @return       The interrupt flag/status of buffer status register.
+ *
+ *    @details      This macro get buffer status register value.
+ */
+#define UUART_GET_BUF_STATUS(uuart)    ((uuart)->BUFSTS)
+
+
+/**
+ *    @brief        Clear specified buffer interrupt flag
+ *
+ *    @param[in]    uuart           The pointer of the specified USCI_UART module
+ *    @param[in]    u32IntTypeFlag  Interrupt Type Flag, should be
+ *                                  - \ref UUART_BUFSTS_RXOVIF_Msk : Receive Buffer Over-run Error  Interrupt Indicator
+ *
+ *    @return       None
+ *
+ *    @details      This macro clear specified buffer interrupt flag.
+ */
+#define UUART_CLR_BUF_INT_FLAG(uuart,u32IntTypeFlag)    ((uuart)->BUFSTS = (u32IntTypeFlag))
+
+
+/**
+ *    @brief        Get wakeup flag
+ *
+ *    @param[in]    uuart    The pointer of the specified USCI_UART module
+ *
+ *    @retval       0       Chip did not wake up from power-down mode.
+ *    @retval       1       Chip waked up from power-down mode.
+ *
+ *    @details      This macro get wakeup flag.
+ */
+#define UUART_GET_WAKEUP_FLAG(uuart)    ((uuart)->WKSTS & UUART_WKSTS_WKF_Msk ? 1: 0 )
+
+
+/**
+ *    @brief        Clear wakeup flag
+ *
+ *    @param[in]    uuart        The pointer of the specified USCI_UART module
+ *
+ *    @return       None
+ *
+ *    @details      This macro clear wakeup flag.
+ */
+#define UUART_CLR_WAKEUP_FLAG(uuart)    ((uuart)->WKSTS = UUART_WKSTS_WKF_Msk)
+
+
+/**
+ *    @brief        Enable specified USCI_UART PDMA function
+ *
+ *    @param[in]    uuart      The pointer of the specified USCI_UART module
+ *    @param[in]    u32FuncSel Combination of following functions
+ *                             - \ref UUART_PDMACTL_TXPDMAEN_Msk
+ *                             - \ref UUART_PDMACTL_RXPDMAEN_Msk
+ *                             - \ref UUART_PDMACTL_PDMAEN_Msk
+ *
+ *    @return       None
+ *
+ *    @details      This macro enable specified USCI_UART PDMA function.
+ */
+#define UUART_PDMA_ENABLE(uuart, u32FuncSel)   ((uuart)->PDMACTL |= (u32FuncSel))
+
+/**
+ *    @brief        Disable specified USCI_UART PDMA function
+ *
+ *    @param[in]    uuart      The pointer of the specified USCI_UART module
+ *    @param[in]    u32FuncSel Combination of following functions
+ *                             - \ref UUART_PDMACTL_TXPDMAEN_Msk
+ *                             - \ref UUART_PDMACTL_RXPDMAEN_Msk
+ *                             - \ref UUART_PDMACTL_PDMAEN_Msk
+ *
+ *    @return       None
+ *
+ *    @details      This macro disable specified USCI_UART PDMA function.
+ */
+#define UUART_PDMA_DISABLE(uuart, u32FuncSel)   ((uuart)->PDMACTL &= ~(u32FuncSel))
+
+
+void UUART_ClearIntFlag(UUART_T* uuart, uint32_t u32Mask);
+uint32_t UUART_GetIntFlag(UUART_T* uuart, uint32_t u32Mask);
+void UUART_Close(UUART_T* uuart);
+void UUART_DisableInt(UUART_T*  uuart, uint32_t u32Mask);
+void UUART_EnableInt(UUART_T*  uuart, uint32_t u32Mask);
+uint32_t UUART_Open(UUART_T* uuart, uint32_t u32baudrate);
+uint32_t UUART_Read(UUART_T* uuart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes);
+uint32_t UUART_SetLine_Config(UUART_T* uuart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits);
+uint32_t UUART_Write(UUART_T* uuart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes);
+void UUART_EnableWakeup(UUART_T* uuart, uint32_t u32WakeupMode);
+void UUART_DisableWakeup(UUART_T* uuart);
+void UUART_EnableFlowCtrl(UUART_T* uuart);
+void UUART_DisableFlowCtrl(UUART_T* uuart);
+
+
+/**@}*/ /* end of group USCI_UART_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group USCI_UART_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_USCI_UART_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_wdt.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_wdt.h
new file mode 100644
index 0000000000..d85fa241ba
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_wdt.h
@@ -0,0 +1,217 @@
+/**************************************************************************//**
+ * @file     nu_wdt.h
+ * @version  V3.00
+ * @brief    Watchdog Timer(WDT) driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_WDT_H__
+#define __NU_WDT_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup WDT_Driver WDT Driver
+  @{
+*/
+
+/** @addtogroup WDT_EXPORTED_CONSTANTS WDT Exported Constants
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/*  WDT Time-out Interval Period Constant Definitions                                                      */
+/*---------------------------------------------------------------------------------------------------------*/
+#define WDT_TIMEOUT_2POW4           (0UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^4 * WDT clocks \hideinitializer */
+#define WDT_TIMEOUT_2POW6           (1UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^6 * WDT clocks \hideinitializer */
+#define WDT_TIMEOUT_2POW8           (2UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^8 * WDT clocks \hideinitializer */
+#define WDT_TIMEOUT_2POW10          (3UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^10 * WDT clocks \hideinitializer */
+#define WDT_TIMEOUT_2POW12          (4UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^12 * WDT clocks \hideinitializer */
+#define WDT_TIMEOUT_2POW14          (5UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^14 * WDT clocks \hideinitializer */
+#define WDT_TIMEOUT_2POW16          (6UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^16 * WDT clocks \hideinitializer */
+#define WDT_TIMEOUT_2POW18          (7UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^18 * WDT clocks \hideinitializer */
+#define WDT_TIMEOUT_2POW20          (8UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^20 * WDT clocks \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  WDT  Reset Delay Period Constant Definitions                                                           */
+/*---------------------------------------------------------------------------------------------------------*/
+#define WDT_RESET_DELAY_1026CLK     (0UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 1026 * WDT clocks \hideinitializer */
+#define WDT_RESET_DELAY_130CLK      (1UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 130 * WDT clocks \hideinitializer */
+#define WDT_RESET_DELAY_18CLK       (2UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 18 * WDT clocks \hideinitializer */
+#define WDT_RESET_DELAY_3CLK        (3UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 3 * WDT clocks \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  WDT Free Reset Counter Keyword Constant Definitions                                                    */
+/*---------------------------------------------------------------------------------------------------------*/
+#define WDT_RESET_COUNTER_KEYWORD   (0x00005AA5UL)    /*!< Fill this value to WDT_RSTCNT register to free reset WDT counter \hideinitializer */
+
+/**@}*/ /* end of group WDT_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Clear WDT Reset System Flag
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro clears WDT time-out reset system flag.
+  * \hideinitializer
+  */
+#define WDT_CLEAR_RESET_FLAG()          (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_RSTF_Msk)
+
+/**
+  * @brief      Clear WDT Time-out Interrupt Flag
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro clears WDT time-out interrupt flag.
+  * \hideinitializer
+  */
+#define WDT_CLEAR_TIMEOUT_INT_FLAG()    (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_IF_Msk)
+
+/**
+  * @brief      Clear WDT Wake-up Flag
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro clears WDT time-out wake-up system flag.
+  * \hideinitializer
+  */
+#define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk)) | WDT_CTL_WKF_Msk)
+
+/**
+  * @brief      Get WDT Time-out Reset Flag
+  *
+  * @param      None
+  *
+  * @retval     0   WDT time-out reset system did not occur
+  * @retval     1   WDT time-out reset system occurred
+  *
+  * @details    This macro indicates system has been reset by WDT time-out reset or not.
+  * \hideinitializer
+  */
+#define WDT_GET_RESET_FLAG()            ((WDT->CTL & WDT_CTL_RSTF_Msk)? 1UL : 0UL)
+
+/**
+  * @brief      Get WDT Time-out Interrupt Flag
+  *
+  * @param      None
+  *
+  * @retval     0   WDT time-out interrupt did not occur
+  * @retval     1   WDT time-out interrupt occurred
+  *
+  * @details    This macro indicates WDT time-out interrupt occurred or not.
+  * \hideinitializer
+  */
+#define WDT_GET_TIMEOUT_INT_FLAG()      ((WDT->CTL & WDT_CTL_IF_Msk)? 1UL : 0UL)
+
+/**
+  * @brief      Get WDT Time-out Wake-up Flag
+  *
+  * @param      None
+  *
+  * @retval     0   WDT time-out interrupt does not cause CPU wake-up
+  * @retval     1   WDT time-out interrupt event cause CPU wake-up
+  *
+  * @details    This macro indicates WDT time-out interrupt event has waked up system or not.
+  * \hideinitializer
+  */
+#define WDT_GET_TIMEOUT_WAKEUP_FLAG()   ((WDT->CTL & WDT_CTL_WKF_Msk)? 1UL : 0UL)
+
+/**
+  * @brief      Reset WDT Counter
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to reset the internal 20-bit WDT up counter value.
+  * @note       If WDT is activated and time-out reset system function is enabled also, user should \n
+  *             reset the 20-bit WDT up counter value to avoid generate WDT time-out reset signal to \n
+  *             reset system before the WDT time-out reset delay period expires.
+  * \hideinitializer
+  */
+#define WDT_RESET_COUNTER()             (WDT->RSTCNT = WDT_RESET_COUNTER_KEYWORD)
+
+
+/*---------------------------------------------------------------------------------------------------------*/
+/* static inline functions                                                                                 */
+/*---------------------------------------------------------------------------------------------------------*/
+/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
+__STATIC_INLINE void WDT_Close(void);
+__STATIC_INLINE void WDT_EnableInt(void);
+__STATIC_INLINE void WDT_DisableInt(void);
+
+/**
+  * @brief      Stop WDT Counting
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This function will stop WDT counting and disable WDT module.
+  */
+__STATIC_INLINE void WDT_Close(void)
+{
+    WDT->CTL = 0UL;
+    while(WDT->CTL & WDT_CTL_SYNC_Msk) {} /* Wait disable WDTEN bit completed, it needs 2 * WDT_CLK. */
+}
+
+/**
+  * @brief      Enable WDT Time-out Interrupt
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This function will enable the WDT time-out interrupt function.
+  */
+__STATIC_INLINE void WDT_EnableInt(void)
+{
+    WDT->CTL |= WDT_CTL_INTEN_Msk;
+}
+
+/**
+  * @brief      Disable WDT Time-out Interrupt
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This function will disable the WDT time-out interrupt function.
+  */
+__STATIC_INLINE void WDT_DisableInt(void)
+{
+    /* Do not touch another write 1 clear bits */
+    WDT->CTL &= ~(WDT_CTL_INTEN_Msk | WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk);
+}
+
+void WDT_Open(uint32_t u32TimeoutInterval, uint32_t u32ResetDelay, uint32_t u32EnableReset, uint32_t u32EnableWakeup);
+
+/**@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group WDT_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_WDT_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_wwdt.h b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_wwdt.h
new file mode 100644
index 0000000000..da86138202
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/inc/nu_wwdt.h
@@ -0,0 +1,151 @@
+/**************************************************************************//**
+ * @file     nu_wwdt.h
+ * @version  V3.00
+ * @brief    Window Watchdog Timer(WWDT) driver header file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#ifndef __NU_WWDT_H__
+#define __NU_WWDT_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup WWDT_Driver WWDT Driver
+  @{
+*/
+
+/** @addtogroup WWDT_EXPORTED_CONSTANTS WWDT Exported Constants
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/*  WWDT Prescale Period Constant Definitions                                                              */
+/*---------------------------------------------------------------------------------------------------------*/
+#define WWDT_PRESCALER_1        (0 << WWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 1 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_2        (1 << WWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 2 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_4        (2 << WWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 4 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_8        (3 << WWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 8 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_16       (4 << WWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 16 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_32       (5 << WWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 32 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_64       (6 << WWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 64 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_128      (7 << WWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 128 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_192      (8 << WWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 192 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_256      (9 << WWDT_CTL_PSCSEL_Pos)  /*!< Select max time-out period to 256 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_384      (10 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 384 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_512      (11 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 512 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_768      (12 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 768 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_1024     (13 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1024 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_1536     (14 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1536 * (64*WWDT_CLK) \hideinitializer */
+#define WWDT_PRESCALER_2048     (15 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2048 * (64*WWDT_CLK) \hideinitializer */
+
+/*---------------------------------------------------------------------------------------------------------*/
+/*  WWDT Reload Counter Keyword Constant Definitions                                                       */
+/*---------------------------------------------------------------------------------------------------------*/
+#define WWDT_RELOAD_WORD        (0x00005AA5)                /*!< Fill this value to WWDT_RLDCNT register to reload WWDT counter \hideinitializer */
+
+/**@}*/ /* end of group WWDT_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Clear WWDT Reset System Flag
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to clear WWDT time-out reset system flag.
+  * \hideinitializer
+  */
+#define WWDT_CLEAR_RESET_FLAG()     (WWDT->STATUS = WWDT_STATUS_WWDTRF_Msk)
+
+/**
+  * @brief      Clear WWDT Compared Match Interrupt Flag
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to clear WWDT compared match interrupt flag.
+  * \hideinitializer
+  */
+#define WWDT_CLEAR_INT_FLAG()       (WWDT->STATUS = WWDT_STATUS_WWDTIF_Msk)
+
+/**
+  * @brief      Get WWDT Reset System Flag
+  *
+  * @param      None
+  *
+  * @retval     0   WWDT time-out reset system did not occur
+  * @retval     1   WWDT time-out reset system occurred
+  *
+  * @details    This macro is used to indicate system has been reset by WWDT time-out reset or not.
+  * \hideinitializer
+  */
+#define WWDT_GET_RESET_FLAG()       ((WWDT->STATUS & WWDT_STATUS_WWDTRF_Msk)? 1 : 0)
+
+/**
+  * @brief      Get WWDT Compared Match Interrupt Flag
+  *
+  * @param      None
+  *
+  * @retval     0   WWDT compare match interrupt did not occur
+  * @retval     1   WWDT compare match interrupt occurred
+  *
+  * @details    This macro is used to indicate WWDT counter value matches CMPDAT value or not.
+  * \hideinitializer
+  */
+#define WWDT_GET_INT_FLAG()         ((WWDT->STATUS & WWDT_STATUS_WWDTIF_Msk)? 1 : 0)
+
+/**
+  * @brief      Get WWDT Counter
+  *
+  * @param      None
+  *
+  * @return     WWDT Counter Value
+  *
+  * @details    This macro reflects the current WWDT counter value.
+  * \hideinitializer
+  */
+#define WWDT_GET_COUNTER()          (WWDT->CNT)
+
+/**
+  * @brief      Reload WWDT Counter
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This macro is used to reload the WWDT counter value to 0x3F.
+  * @note       User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value \n
+  *             between 0 and CMPDAT value. If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, \n
+  *             WWDT reset signal will generate immediately to reset system.
+  * \hideinitializer
+  */
+#define WWDT_RELOAD_COUNTER()       (WWDT->RLDCNT = WWDT_RELOAD_WORD)
+
+void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt);
+
+/**@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group WWDT_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NU_WWDT_H__ */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/lib/libStdDriver.ewd b/bsp/nuvoton/libraries/m2354/StdDriver/lib/libStdDriver.ewd
new file mode 100644
index 0000000000..4990af44b4
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/lib/libStdDriver.ewd
@@ -0,0 +1,3285 @@
+
+
+
+  2
+  
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+    
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+        
+        
+            $PROJ_DIR$\..\src\nu_spi.c
+        
+        
+            $PROJ_DIR$\..\src\nu_sys.c
+        
+        
+            $PROJ_DIR$\..\src\nu_tamper.c
+        
+        
+            $PROJ_DIR$\..\src\nu_timer.c
+        
+        
+            $PROJ_DIR$\..\src\nu_timer_pwm.c
+        
+        
+            $PROJ_DIR$\..\src\nu_uart.c
+        
+        
+            $PROJ_DIR$\..\src\nu_usbd.c
+        
+        
+            $PROJ_DIR$\..\src\nu_usci_i2c.c
+        
+        
+            $PROJ_DIR$\..\src\nu_usci_spi.c
+        
+        
+            $PROJ_DIR$\..\src\nu_usci_uart.c
+        
+        
+            $PROJ_DIR$\..\src\nu_wdt.c
+        
+        
+            $PROJ_DIR$\..\src\nu_wwdt.c
+        
+    
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/lib/libStdDriver.eww b/bsp/nuvoton/libraries/m2354/StdDriver/lib/libStdDriver.eww
new file mode 100644
index 0000000000..fcdfcdfe30
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/lib/libStdDriver.eww
@@ -0,0 +1,10 @@
+
+
+
+  
+    $WS_DIR$\libStdDriver.ewp
+  
+  
+
+
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/lib/libStdDriver.uvprojx b/bsp/nuvoton/libraries/m2354/StdDriver/lib/libStdDriver.uvprojx
new file mode 100644
index 0000000000..b28ca38daf
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/lib/libStdDriver.uvprojx
@@ -0,0 +1,602 @@
+
+
+
+  2.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      libstddriver-m2354
+      0x4
+      ARM-ADS
+      6130001::V6.13.1::.\ARMCLANG
+      1
+      
+        
+          M2354ES
+          Nuvoton
+          Nuvoton.NuMicro_DFP.1.3.10
+          http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack
+          IRAM(0x20000000,0x8000) IRAM2(0x30008000,0x10000) IROM(0x00000000,0x40000) IROM2(0x10040000,0x40000) CPUTYPE("Cortex-M23") TZ CLOCK(12000000) ESEL ELITTLE
+          
+          
+          UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1200 -FN1 -FF0M2354_AP_1M -FS00 -FL0100000 -FP0($$Device:M2354ES$Flash\M2354_AP_1M.FLM))
+          0
+          $$Device:M2354ES$Device\M2354\Include\M2354.h
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:M2354ES$SVD\Nuvoton\M2354_v1.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          .\build\keil5\
+          libstddriver_keil
+          0
+          1
+          1
+          1
+          1
+          .\build\keil5\
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            1
+            0
+            xcopy /y ".\build\keil5\@L.lib" "."
+            
+            0
+            0
+            0
+            0
+          
+          1
+          
+        
+        
+          0
+          0
+          0
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+          0
+          0
+          0
+          3
+          
+          
+          1
+        
+        
+          
+          
+          
+          
+          SARMV8M.DLL
+           -MPU
+          TCM.DLL
+          -pCM23
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4100
+          
+          1
+          BIN\UL2V8M.DLL
+          "" ()
+          
+          
+          
+          
+          0
+        
+        
+          
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+            1
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+            "Cortex-M23"
+            
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+              
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+                0x8000
+              
+              
+                1
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+                0x40000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
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+                0x0
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+                0x40000
+              
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+                0x10040000
+                0x40000
+              
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+                0x0
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+              
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+                0x20000000
+                0x8000
+              
+              
+                0
+                0x30008000
+                0x10000
+              
+            
+            
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+            0
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+            5
+            3
+            0
+            0
+            0
+            1
+            0
+            
+              
+              
+              
+              ..\inc;..\..\CMSIS\Include;..\..\Device\Nuvoton\M2354\Include;.
+            
+          
+          
+            1
+            0
+            0
+            1
+            0
+            0
+            1
+            0
+            0
+            0
+            
+              
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+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x00000000
+            0x20000000
+            
+            .\linking_scripts\m2354_flash.sct
+            
+            
+            --map --first='startup_M2354.o(RESET)' --datacompressor=off --info=inline --entry Reset_Handler
+            
+            
+          
+        
+      
+      
+        
+          src
+          
+            
+              nu_acmp.c
+              1
+              ..\src\nu_acmp.c
+            
+            
+              nu_bpwm.c
+              1
+              ..\src\nu_bpwm.c
+            
+            
+              nu_can.c
+              1
+              ..\src\nu_can.c
+            
+            
+              nu_clk.c
+              1
+              ..\src\nu_clk.c
+            
+            
+              nu_crc.c
+              1
+              ..\src\nu_crc.c
+            
+            
+              nu_crypto.c
+              1
+              ..\src\nu_crypto.c
+            
+            
+              nu_dac.c
+              1
+              ..\src\nu_dac.c
+            
+            
+              nu_dpm.c
+              1
+              ..\src\nu_dpm.c
+            
+            
+              nu_eadc.c
+              1
+              ..\src\nu_eadc.c
+            
+            
+              nu_ebi.c
+              1
+              ..\src\nu_ebi.c
+            
+            
+              nu_ecap.c
+              1
+              ..\src\nu_ecap.c
+            
+            
+              nu_epwm.c
+              1
+              ..\src\nu_epwm.c
+            
+            
+              nu_ewdt.c
+              1
+              ..\src\nu_ewdt.c
+            
+            
+              nu_ewwdt.c
+              1
+              ..\src\nu_ewwdt.c
+            
+            
+              nu_fmc.c
+              1
+              ..\src\nu_fmc.c
+            
+            
+              nu_fvc.c
+              1
+              ..\src\nu_fvc.c
+            
+            
+              nu_gpio.c
+              1
+              ..\src\nu_gpio.c
+            
+            
+              nu_i2c.c
+              1
+              ..\src\nu_i2c.c
+            
+            
+              nu_i2s.c
+              1
+              ..\src\nu_i2s.c
+            
+            
+              nu_keystore.c
+              1
+              ..\src\nu_keystore.c
+            
+            
+              nu_lcd.c
+              1
+              ..\src\nu_lcd.c
+            
+            
+              nu_pdma.c
+              1
+              ..\src\nu_pdma.c
+            
+            
+              nu_qei.c
+              1
+              ..\src\nu_qei.c
+            
+            
+              nu_qspi.c
+              1
+              ..\src\nu_qspi.c
+            
+            
+              nu_rng.c
+              1
+              ..\src\nu_rng.c
+            
+            
+              nu_rtc.c
+              1
+              ..\src\nu_rtc.c
+            
+            
+              nu_sc.c
+              1
+              ..\src\nu_sc.c
+            
+            
+              nu_scuart.c
+              1
+              ..\src\nu_scuart.c
+            
+            
+              nu_sdh.c
+              1
+              ..\src\nu_sdh.c
+            
+            
+              nu_spi.c
+              1
+              ..\src\nu_spi.c
+            
+            
+              nu_sys.c
+              1
+              ..\src\nu_sys.c
+            
+            
+              nu_tamper.c
+              1
+              ..\src\nu_tamper.c
+            
+            
+              nu_timer.c
+              1
+              ..\src\nu_timer.c
+            
+            
+              nu_timer_pwm.c
+              1
+              ..\src\nu_timer_pwm.c
+            
+            
+              nu_uart.c
+              1
+              ..\src\nu_uart.c
+            
+            
+              nu_usbd.c
+              1
+              ..\src\nu_usbd.c
+            
+            
+              nu_usci_i2c.c
+              1
+              ..\src\nu_usci_i2c.c
+            
+            
+              nu_usci_spi.c
+              1
+              ..\src\nu_usci_spi.c
+            
+            
+              nu_usci_uart.c
+              1
+              ..\src\nu_usci_uart.c
+            
+            
+              nu_wdt.c
+              1
+              ..\src\nu_wdt.c
+            
+            
+              nu_wwdt.c
+              1
+              ..\src\nu_wwdt.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+    
+  
+
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/lib/nutool_clkcfg.h b/bsp/nuvoton/libraries/m2354/StdDriver/lib/nutool_clkcfg.h
new file mode 100644
index 0000000000..950b09946e
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/lib/nutool_clkcfg.h
@@ -0,0 +1,26 @@
+/****************************************************************************
+ * @file     nutool_clkcfg.h
+ * @version  V1.05
+ * @Date     2020/04/15-11:28:38
+ * @brief    NuMicro generated code file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#ifndef __NUTOOL_CLKCFG_H__
+#define __NUTOOL_CLKCFG_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+#undef  __HXT
+#define __HXT         (12000000UL)  /*!< High Speed External Crystal Clock Frequency */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*__NUTOOL_CLKCFG_H__*/
+
+/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_acmp.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_acmp.c
new file mode 100644
index 0000000000..73d9bbb5eb
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_acmp.c
@@ -0,0 +1,82 @@
+/**************************************************************************//**
+ * @file     acmp.c
+ * @version  V3.00
+ * @brief    Analog Comparator(ACMP) driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+#include "NuMicro.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup ACMP_Driver ACMP Driver
+  @{
+*/
+
+
+/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
+  @{
+*/
+
+
+/**
+  * @brief  Configure the specified ACMP module
+  *
+  * @param[in]  acmp      The pointer of the specified ACMP module
+  * @param[in]  u32ChNum  Comparator number.
+  * @param[in]  u32NegSrc Comparator negative input selection.  Including:
+  *                  - \ref ACMP_CTL_NEGSEL_PIN
+  *                  - \ref ACMP_CTL_NEGSEL_CRV
+  *                  - \ref ACMP_CTL_NEGSEL_VBG
+  *                  - \ref ACMP_CTL_NEGSEL_DAC
+  * @param[in]  u32HysSel The hysteresis function option. Including:
+  *                  - \ref ACMP_CTL_HYSTERESIS_30MV
+  *                  - \ref ACMP_CTL_HYSTERESIS_20MV
+  *                  - \ref ACMP_CTL_HYSTERESIS_10MV
+  *                  - \ref ACMP_CTL_HYSTERESIS_DISABLE
+  *
+  * @return     None
+  *
+  * @details    Configure hysteresis function, select the source of negative input and enable analog comparator.
+  */
+void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysSel)
+{
+    acmp->CTL[u32ChNum] = (acmp->CTL[u32ChNum] & (~(ACMP_CTL_NEGSEL_Msk | ACMP_CTL_HYSSEL_Msk))) | (u32NegSrc | u32HysSel | ACMP_CTL_ACMPEN_Msk);
+}
+
+/**
+  * @brief  Close analog comparator
+  *
+  * @param[in]  acmp The pointer of the specified ACMP module
+  * @param[in]  u32ChNum Comparator number.
+  *
+  * @return     None
+  *
+  * @details  This function will clear ACMPEN bit of ACMP_CTL register to disable analog comparator.
+  */
+void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum)
+{
+    acmp->CTL[u32ChNum] &= (~ACMP_CTL_ACMPEN_Msk);
+}
+
+
+
+/**@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group ACMP_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_bpwm.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_bpwm.c
new file mode 100644
index 0000000000..52065381f4
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_bpwm.c
@@ -0,0 +1,713 @@
+/**************************************************************************//**
+ * @file     bpwm.c
+ * @version  V1.00
+ * @brief    M2354 series BPWM driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup BPWM_Driver BPWM Driver
+  @{
+*/
+
+
+/** @addtogroup BPWM_EXPORTED_FUNCTIONS BPWM Exported Functions
+  @{
+*/
+
+/**
+ * @brief Configure BPWM capture and get the nearest unit time.
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32UnitTimeNsec The unit time of counter
+ * @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used
+ * @return The nearest unit time in nano second.
+ * @details This function is used to Configure BPWM capture and get the nearest unit time.
+ */
+uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge)
+{
+    uint32_t u32PWMClockSrc;
+    uint32_t u32NearestUnitTimeNsec = 0U;
+    uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU;
+    uint8_t u8BreakLoop = 0U;
+
+    (void)u32ChannelNum;
+    (void)u32CaptureEdge;
+
+    /* clock source is from PCLK */
+    if((((uint32_t)bpwm) == BPWM0_BASE) || (((uint32_t)bpwm) == BPWM0_BASE + NS_OFFSET))
+    {
+        u32PWMClockSrc = CLK_GetPCLK0Freq();
+    }
+    else/* if((bpwm == BPWM1)||(bpwm == BPWM1_NS)) */
+    {
+        u32PWMClockSrc = CLK_GetPCLK1Freq();
+    }
+
+    u32PWMClockSrc /= 1000UL;
+    for(u32Prescale = 1U; u32Prescale <= 0x1000UL; u32Prescale++)
+    {
+        u32NearestUnitTimeNsec = (1000000UL * u32Prescale) / u32PWMClockSrc;
+        if(u32NearestUnitTimeNsec < u32UnitTimeNsec)
+        {
+            if(u32Prescale == 0x1000U)
+            {
+                /* limit to the maximum unit time(nano second) */
+                u8BreakLoop = 1U;
+            }
+            if(!((1000000UL * (u32Prescale + 1UL) > (u32NearestUnitTimeNsec * u32PWMClockSrc))))
+            {
+                u8BreakLoop = 1U;
+            }
+        }
+        else
+        {
+            u8BreakLoop = 1U;
+        }
+        if(u8BreakLoop)
+        {
+            break;
+        }
+    }
+
+    /* convert to real register value */
+    u32Prescale = u32Prescale - 1U;
+    /* all channels share a prescaler */
+    BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescale);
+
+    /* set BPWM to down count type(edge aligned) */
+    (bpwm)->CTL1 = (1UL);
+
+    BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR);
+
+    return (u32NearestUnitTimeNsec);
+}
+
+/**
+ * @brief This function Configure BPWM generator and get the nearest frequency in edge aligned(up counter type) auto-reload mode
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32Frequency Target generator frequency
+ * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
+ * @return Nearest frequency clock in nano second
+ * @note Since all channels shares a prescaler. Call this API to configure BPWM frequency may affect
+ *       existing frequency of other channel.
+ * @note This function is used for initial stage.
+ *       To change duty cycle later, it should get the configured period value and calculate the new comparator value.
+ */
+uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle)
+{
+    uint32_t u32PWMClockSrc;
+    uint32_t i;
+    uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU;
+
+    /* clock source is from PCLK */
+    if(((uint32_t)bpwm == BPWM0_BASE) || ((uint32_t)bpwm == BPWM0_BASE + NS_OFFSET))
+    {
+        u32PWMClockSrc = CLK_GetPCLK0Freq();
+    }
+    else/* if((bpwm == BPWM1)||(bpwm == BPWM1_NS)) */
+    {
+        u32PWMClockSrc = CLK_GetPCLK1Freq();
+    }
+
+    for(u32Prescale = 1U; u32Prescale < 0xFFFU; u32Prescale++)/* prescale could be 0~0xFFF */
+    {
+        i = (u32PWMClockSrc / u32Frequency) / u32Prescale;
+        /* If target value is larger than CNR, need to use a larger prescaler */
+        if(i <= (0x10000U))
+        {
+            u32CNR = i;
+            break;
+        }
+    }
+    /* Store return value here 'cos we're gonna change u32Prescale & u32CNR to the real value to fill into register */
+    i = u32PWMClockSrc / (u32Prescale * u32CNR);
+
+    /* convert to real register value */
+    u32Prescale = u32Prescale - 1U;
+    /* all channels share a prescaler */
+    BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescale);
+    /* set BPWM to up counter type(edge aligned) */
+    (bpwm)->CTL1 = BPWM_UP_COUNTER;
+
+    u32CNR = u32CNR - 1U;
+    BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR);
+    BPWM_SET_CMR(bpwm, u32ChannelNum, u32DutyCycle * (u32CNR + 1UL) / 100UL);
+
+
+    (bpwm)->WGCTL0 = ((bpwm)->WGCTL0 & ~((BPWM_WGCTL0_PRDPCTL0_Msk | BPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1))) | \
+                     (BPWM_OUTPUT_HIGH << (u32ChannelNum << 1UL << BPWM_WGCTL0_ZPCTL0_Pos));
+    (bpwm)->WGCTL1 = ((bpwm)->WGCTL1 & ~((BPWM_WGCTL1_CMPDCTL0_Msk | BPWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum << 1))) | \
+                     (BPWM_OUTPUT_LOW << (u32ChannelNum << 1UL << BPWM_WGCTL1_CMPUCTL0_Pos));
+
+    return(i);
+}
+
+/**
+ * @brief Start BPWM module
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
+ * @return None
+ * @details This function is used to start BPWM module.
+ * @note All channels share one counter.
+ */
+void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask)
+{
+    (void)u32ChannelMask;
+    (bpwm)->CNTEN = BPWM_CNTEN_CNTEN0_Msk;
+}
+
+/**
+ * @brief Stop BPWM module
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
+ * @return None
+ * @details This function is used to stop BPWM module.
+ * @note All channels share one period.
+ */
+void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask)
+{
+    (void)u32ChannelMask;
+    (bpwm)->PERIOD = 0UL;
+}
+
+/**
+ * @brief Stop BPWM generation immediately by clear channel enable bit
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
+ * @return None
+ * @details This function is used to stop BPWM generation immediately by clear channel enable bit.
+ * @note All channels share one counter.
+ */
+void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask)
+{
+    (void)u32ChannelMask;
+    (bpwm)->CNTEN &= ~BPWM_CNTEN_CNTEN0_Msk;
+}
+
+/**
+ * @brief Enable selected channel to trigger ADC
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32Condition The condition to trigger ADC. Combination of following conditions:
+ *                  - \ref BPWM_TRIGGER_ADC_EVEN_ZERO_POINT
+ *                  - \ref BPWM_TRIGGER_ADC_EVEN_PERIOD_POINT
+ *                  - \ref BPWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT
+ *                  - \ref BPWM_TRIGGER_ADC_EVEN_CMP_UP_COUNT_POINT
+ *                  - \ref BPWM_TRIGGER_ADC_EVEN_CMP_DOWN_COUNT_POINT
+ *                  - \ref BPWM_TRIGGER_ADC_ODD_CMP_UP_COUNT_POINT
+ *                  - \ref BPWM_TRIGGER_ADC_ODD_CMP_DOWN_COUNT_POINT
+ * @return None
+ * @details This function is used to enable selected channel to trigger ADC
+ */
+void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+    if(u32ChannelNum < 4UL)
+    {
+        (bpwm)->EADCTS0 &= ~((BPWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum << 3));
+        (bpwm)->EADCTS0 |= ((BPWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum << 3));
+    }
+    else
+    {
+        (bpwm)->EADCTS1 &= ~((BPWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4UL) << 3));
+        (bpwm)->EADCTS1 |= ((BPWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4UL) << 3));
+    }
+}
+
+/**
+ * @brief Disable selected channel to trigger ADC
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~3
+ * @return None
+ * @details This function is used to disable selected channel to trigger ADC
+ */
+void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+    if(u32ChannelNum < 4UL)
+    {
+        (bpwm)->EADCTS0 &= ~(BPWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum << 3));
+    }
+    else
+    {
+        (bpwm)->EADCTS1 &= ~(BPWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4UL) << 3));
+    }
+}
+
+/**
+ * @brief Clear selected channel trigger ADC flag
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32Condition This parameter is not used
+ * @return None
+ * @details This function is used to clear selected channel trigger ADC flag
+ */
+void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+    (void)u32Condition;
+    (bpwm)->STATUS = (BPWM_STATUS_EADCTRG0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Get selected channel trigger ADC flag
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @retval 0 The specified channel trigger ADC to start of conversion flag is not set
+ * @retval 1 The specified channel trigger ADC to start of conversion flag is set
+ * @details This function is used to get BPWM trigger ADC to start of conversion flag for specified channel
+ */
+uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+    return (((bpwm)->STATUS & (BPWM_STATUS_EADCTRG0_Msk << u32ChannelNum)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable capture of selected channel(s)
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ *                           Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to enable capture of selected channel(s)
+ */
+void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask)
+{
+    (bpwm)->CAPINEN |= u32ChannelMask;
+    (bpwm)->CAPCTL |= u32ChannelMask;
+}
+
+/**
+ * @brief Disable capture of selected channel(s)
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ *                           Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to disable capture of selected channel(s)
+ */
+void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask)
+{
+    (bpwm)->CAPINEN &= ~u32ChannelMask;
+    (bpwm)->CAPCTL &= ~u32ChannelMask;
+}
+
+/**
+ * @brief Enables BPWM output generation of selected channel(s)
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ *                           Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...
+ * @return None
+ * @details This function is used to enables BPWM output generation of selected channel(s)
+ */
+void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask)
+{
+    (bpwm)->POEN |= u32ChannelMask;
+}
+
+/**
+ * @brief Disables BPWM output generation of selected channel(s)
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output...
+ * @return None
+ * @details This function is used to disables BPWM output generation of selected channel(s)
+ */
+void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask)
+{
+    (bpwm)->POEN &= ~u32ChannelMask;
+}
+
+/**
+ * @brief Enable capture interrupt of selected channel.
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32Edge Rising or falling edge to latch counter.
+ *              - \ref BPWM_CAPTURE_INT_RISING_LATCH
+ *              - \ref BPWM_CAPTURE_INT_FALLING_LATCH
+ * @return None
+ * @details This function is used to enable capture interrupt of selected channel.
+ */
+void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+    (bpwm)->CAPIEN |= (u32Edge << u32ChannelNum);
+}
+
+/**
+ * @brief Disable capture interrupt of selected channel.
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32Edge Rising or falling edge to latch counter.
+ *              - \ref BPWM_CAPTURE_INT_RISING_LATCH
+ *              - \ref BPWM_CAPTURE_INT_FALLING_LATCH
+ * @return None
+ * @details This function is used to disable capture interrupt of selected channel.
+ */
+void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+    (bpwm)->CAPIEN &= ~(u32Edge << u32ChannelNum);
+}
+
+/**
+ * @brief Clear capture interrupt of selected channel.
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32Edge Rising or falling edge to latch counter.
+ *              - \ref BPWM_CAPTURE_INT_RISING_LATCH
+ *              - \ref BPWM_CAPTURE_INT_FALLING_LATCH
+ * @return None
+ * @details This function is used to clear capture interrupt of selected channel.
+ */
+void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+    (bpwm)->CAPIF = (u32Edge << u32ChannelNum);
+}
+
+/**
+ * @brief Get capture interrupt of selected channel.
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @retval 0 No capture interrupt
+ * @retval 1 Rising edge latch interrupt
+ * @retval 2 Falling edge latch interrupt
+ * @retval 3 Rising and falling latch interrupt
+ * @details This function is used to get capture interrupt of selected channel.
+ */
+uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+    uint32_t u32CapIf = 0UL;
+
+    u32CapIf = ((((bpwm)->CAPIF & (BPWM_CAPIF_CAPFIF0_Msk << u32ChannelNum)) ? 1UL : 0UL) << 1);
+    u32CapIf |= (((bpwm)->CAPIF & (BPWM_CAPIF_CAPRIF0_Msk << u32ChannelNum)) ? 1UL : 0UL);
+    return u32CapIf;
+}
+
+/**
+ * @brief Enable duty interrupt of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32IntDutyType Duty interrupt type, could be either
+ *              - \ref BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP
+ *              - \ref BPWM_DUTY_INT_UP_COUNT_MATCH_CMP
+ * @return None
+ * @details This function is used to enable duty interrupt of selected channel.
+ */
+void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
+{
+    (bpwm)->INTEN |= (u32IntDutyType << u32ChannelNum);
+}
+
+/**
+ * @brief Disable duty interrupt of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable duty interrupt of selected channel
+ */
+void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+    (bpwm)->INTEN &= (uint32_t)(~((BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | BPWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum));
+}
+
+/**
+ * @brief Clear duty interrupt flag of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear duty interrupt flag of selected channel
+ */
+void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+    (bpwm)->INTSTS = (BPWM_INTSTS_CMPUIF0_Msk | BPWM_INTSTS_CMPDIF0_Msk) << u32ChannelNum;
+}
+
+/**
+ * @brief Get duty interrupt flag of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @return Duty interrupt flag of specified channel
+ * @retval 0 Duty interrupt did not occur
+ * @retval 1 Duty interrupt occurred
+ * @details This function is used to get duty interrupt flag of selected channel
+ */
+uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+    return ((((bpwm)->INTSTS & ((BPWM_INTSTS_CMPDIF0_Msk | BPWM_INTSTS_CMPUIF0_Msk) << u32ChannelNum))) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable period interrupt of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @param[in] u32IntPeriodType Period interrupt type. This parameter is not used.
+ * @return None
+ * @details This function is used to enable period interrupt of selected channel.
+ * @note All channels share channel 0's setting.
+ */
+void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum,  uint32_t u32IntPeriodType)
+{
+    (void)u32ChannelNum;
+    (void)u32IntPeriodType;
+    (bpwm)->INTEN |= BPWM_INTEN_PIEN0_Msk;
+}
+
+/**
+ * @brief Disable period interrupt of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @return None
+ * @details This function is used to disable period interrupt of selected channel.
+ * @note All channels share channel 0's setting.
+ */
+void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+    (void)u32ChannelNum;
+    (bpwm)->INTEN &= ~BPWM_INTEN_PIEN0_Msk;
+}
+
+/**
+ * @brief Clear period interrupt of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @return None
+ * @details This function is used to clear period interrupt of selected channel
+ * @note All channels share channel 0's setting.
+ */
+void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+    (void)u32ChannelNum;
+    (bpwm)->INTSTS = BPWM_INTSTS_PIF0_Msk;
+}
+
+/**
+ * @brief Get period interrupt of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @return Period interrupt flag of specified channel
+ * @retval 0 Period interrupt did not occur
+ * @retval 1 Period interrupt occurred
+ * @details This function is used to get period interrupt of selected channel
+ * @note All channels share channel 0's setting.
+ */
+uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+    (void)u32ChannelNum;
+    return (((bpwm)->INTSTS & BPWM_INTSTS_PIF0_Msk) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable zero interrupt of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @return None
+ * @details This function is used to enable zero interrupt of selected channel.
+ * @note All channels share channel 0's setting.
+ */
+void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+    (void)u32ChannelNum;
+    (bpwm)->INTEN |= BPWM_INTEN_ZIEN0_Msk;
+}
+
+/**
+ * @brief Disable zero interrupt of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @return None
+ * @details This function is used to disable zero interrupt of selected channel.
+ * @note All channels share channel 0's setting.
+ */
+void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+    (void)u32ChannelNum;
+    (bpwm)->INTEN &= ~BPWM_INTEN_ZIEN0_Msk;
+}
+
+/**
+ * @brief Clear zero interrupt of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @return None
+ * @details This function is used to clear zero interrupt of selected channel.
+ * @note All channels share channel 0's setting.
+ */
+void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+    (void)u32ChannelNum;
+    (bpwm)->INTSTS = BPWM_INTSTS_ZIF0_Msk;
+}
+
+/**
+ * @brief Get zero interrupt of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @return zero interrupt flag of specified channel
+ * @retval 0 zero interrupt did not occur
+ * @retval 1 zero interrupt occurred
+ * @details This function is used to get zero interrupt of selected channel.
+ * @note All channels share channel 0's setting.
+ */
+uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+    (void)u32ChannelNum;
+    return (((bpwm)->INTSTS & BPWM_INTSTS_ZIF0_Msk) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable load mode of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32LoadMode BPWM counter loading mode.
+ *              - \ref BPWM_LOAD_MODE_IMMEDIATE
+ *              - \ref BPWM_LOAD_MODE_CENTER
+ * @return None
+ * @details This function is used to enable load mode of selected channel.
+ */
+void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
+{
+    (bpwm)->CTL0 |= (u32LoadMode << u32ChannelNum);
+}
+
+/**
+ * @brief Disable load mode of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
+ * @param[in] u32LoadMode BPWM counter loading mode.
+ *              - \ref BPWM_LOAD_MODE_IMMEDIATE
+ *              - \ref BPWM_LOAD_MODE_CENTER
+ * @return None
+ * @details This function is used to disable load mode of selected channel.
+ */
+void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
+{
+    (bpwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum);
+}
+
+/**
+ * @brief Set BPWM clock source
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @param[in] u32ClkSrcSel BPWM external clock source.
+ *              - \ref BPWM_CLKSRC_BPWM_CLK
+ *              - \ref BPWM_CLKSRC_TIMER0
+ *              - \ref BPWM_CLKSRC_TIMER1
+ *              - \ref BPWM_CLKSRC_TIMER2
+ *              - \ref BPWM_CLKSRC_TIMER3
+ * @return None
+ * @details This function is used to set BPWM clock source.
+ * @note All channels share channel 0's setting.
+ */
+void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel)
+{
+    (void)u32ChannelNum;
+    (bpwm)->CLKSRC = (u32ClkSrcSel);
+}
+
+/**
+ * @brief Get the time-base counter reached its maximum value flag of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @return Count to max interrupt flag of specified channel
+ * @retval 0 Count to max interrupt did not occur
+ * @retval 1 Count to max interrupt occurred
+ * @details This function is used to get the time-base counter reached its maximum value flag of selected channel.
+ * @note All channels share channel 0's setting.
+ */
+uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+    (void)u32ChannelNum;
+    return (((bpwm)->STATUS & BPWM_STATUS_CNTMAX0_Msk) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the time-base counter reached its maximum value flag of selected channel
+ * @param[in] bpwm The pointer of the specified BPWM module
+ *                - BPWM0 : BPWM Group 0
+ *                - BPWM1 : BPWM Group 1
+ * @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
+ * @return None
+ * @details This function is used to clear the time-base counter reached its maximum value flag of selected channel.
+ * @note All channels share channel 0's setting.
+ */
+void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
+{
+    (void)u32ChannelNum;
+    (bpwm)->STATUS = BPWM_STATUS_CNTMAX0_Msk;
+}
+
+
+/**@}*/ /* end of group BPWM_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group BPWM_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_can.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_can.c
new file mode 100644
index 0000000000..1f36804496
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_can.c
@@ -0,0 +1,1191 @@
+/**************************************************************************//**
+ * @file     can.c
+ * @version  V3.00
+ * @brief    CAN driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+
+#if defined(__ICCARM__)
+# pragma diag_suppress=Pm073, Pm143        /* Misra C rule 14.7 */
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup CAN_Driver CAN Driver
+  @{
+*/
+
+/** @addtogroup CAN_EXPORTED_FUNCTIONS CAN Exported Functions
+  @{
+*/
+
+/** @cond HIDDEN_SYMBOLS */
+
+#if defined(CAN1)
+static uint8_t gu8LockCanIf[2][2] = {{0U}};    /* The chip has two CANs. */
+#elif defined(CAN0) || defined(CAN)
+static uint8_t gu8LockCanIf[1][2] = {{0U}};    /* The chip only has one CAN. */
+#endif
+
+#define RETRY_COUNTS    (0x10000000UL)
+
+#define TSEG1_MIN 2
+#define TSEG1_MAX 16
+#define TSEG2_MIN 1
+#define TSEG2_MAX 8
+#define BRP_MIN   1
+#define BRP_MAX   1024  /* 6-bit BRP field + 4-bit BRPE field*/
+#define SJW_MAX   4UL
+#define BRP_INC   1
+
+/* #define DEBUG_PRINTF printf */
+#define DEBUG_PRINTF(...)
+
+
+static uint32_t LockIF(CAN_T *tCAN);
+static uint32_t LockIF_TL(CAN_T *tCAN);
+static void ReleaseIF(CAN_T *tCAN, uint32_t u32IfNo);
+static int can_update_spt(int sampl_pt, int tseg, int *tseg1, int *tseg2);
+
+/**
+  * @brief Check if any interface is available then lock it for usage.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @retval 0 IF0 is free
+  * @retval 1 IF1 is free
+  * @retval 2 No IF is free
+  * @details Search the first free message interface, starting from 0. If a interface is
+  *          available, set a flag to lock the interface.
+  */
+static uint32_t LockIF(CAN_T *tCAN)
+{
+    uint32_t u32CanNo;
+    uint32_t u32FreeIfNo;
+    uint32_t u32IntMask;
+
+#if defined(CAN1)
+    u32CanNo = (tCAN == CAN1) ? 1 : 0;
+#else // defined(CAN0) || defined(CAN)
+    u32CanNo = 0U;
+#endif
+
+    u32FreeIfNo = 2U;
+
+    /* Disable CAN interrupt */
+    u32IntMask = tCAN->CON & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
+    tCAN->CON = tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
+
+    /* Check interface 1 is available or not */
+    if((tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0U)
+    {
+        if(gu8LockCanIf[u32CanNo][0] == (uint8_t)FALSE)
+        {
+            gu8LockCanIf[u32CanNo][0] = (uint8_t)TRUE;
+            u32FreeIfNo = 0U;
+        }
+    }
+
+    /* Or check interface 2 is available or not */
+    if(u32FreeIfNo == 2U)
+    {
+        if((tCAN->IF[1].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0U)
+        {
+            if(gu8LockCanIf[u32CanNo][1] == (uint8_t)FALSE)
+            {
+                gu8LockCanIf[u32CanNo][1] = (uint8_t)TRUE;
+                u32FreeIfNo = 1U;
+            }
+        }
+    }
+
+    /* Enable CAN interrupt */
+    tCAN->CON |= u32IntMask;
+
+    return u32FreeIfNo;
+}
+
+/**
+  * @brief Check if any interface is available in a time limitation then lock it for usage.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @retval 0 IF0 is free
+  * @retval 1 IF1 is free
+  * @retval 2 No IF is free
+  * @details Search the first free message interface, starting from 0. If no interface is
+  *          it will try again until time out. If a interface is available,  set a flag to
+  *          lock the interface.
+  */
+static uint32_t LockIF_TL(CAN_T *tCAN)
+{
+    uint32_t u32Count;
+    uint32_t u32FreeIfNo = 0;
+
+    for(u32Count = 0U; u32Count < (uint32_t)RETRY_COUNTS; u32Count++)
+    {
+        if((u32FreeIfNo = LockIF(tCAN)) != 2U)
+        {
+            break;
+        }
+    }
+
+    return u32FreeIfNo;
+}
+
+/**
+  * @brief Release locked interface.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32Info The interface number, 0 or 1.
+  * @return none
+  * @details Release the locked interface.
+  */
+static void ReleaseIF(CAN_T *tCAN, uint32_t u32IfNo)
+{
+    uint32_t u32IntMask;
+    uint32_t u32CanNo;
+
+    if(u32IfNo < 2U)
+    {
+
+#if defined(CAN1)
+        u32CanNo = (tCAN == CAN1) ? 1U : 0U;
+#else // defined(CAN0) || defined(CAN)
+        u32CanNo = 0U;
+#endif
+
+        /* Disable CAN interrupt */
+        u32IntMask = tCAN->CON & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
+        tCAN->CON = tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
+
+        gu8LockCanIf[u32CanNo][u32IfNo] = (uint8_t)FALSE;
+
+        /* Enable CAN interrupt */
+        tCAN->CON |= u32IntMask;
+    }
+}
+
+/**
+  * @brief Enter initialization mode
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] Following values can be used.
+  *            \ref CAN_CON_DAR_Msk Disable automatic retransmission.
+  *            \ref CAN_CON_EIE_Msk Enable error interrupt.
+  *            \ref CAN_CON_SIE_Msk Enable status interrupt.
+  *            \ref CAN_CON_IE_Msk CAN interrupt.
+  * @return None
+  * @details This function is used to set CAN to enter initialization mode and enable access bit timing
+  *          register. After bit timing configuration ready, user must call CAN_LeaveInitMode()
+  *          to leave initialization mode and lock bit timing register to let new configuration
+  *          take effect.
+  */
+void CAN_EnterInitMode(CAN_T *tCAN, uint8_t u8Mask)
+{
+    tCAN->CON = u8Mask | (CAN_CON_INIT_Msk | CAN_CON_CCE_Msk);
+}
+
+
+/**
+  * @brief Leave initialization mode
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @return None
+  * @details This function is used to set CAN to leave initialization mode to let
+  *          bit timing configuration take effect after configuration ready.
+  */
+void CAN_LeaveInitMode(CAN_T *tCAN)
+{
+    tCAN->CON &= (~(CAN_CON_INIT_Msk | CAN_CON_CCE_Msk));
+    while(tCAN->CON & CAN_CON_INIT_Msk) {} /* Check INIT bit is released */
+}
+
+/**
+  * @brief Wait message into message buffer in basic mode.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @return None
+  * @details This function is used to wait message into message buffer in basic mode. Please notice the
+  *          function is polling NEWDAT bit of MCON register by while loop and it is used in basic mode.
+  */
+void CAN_WaitMsg(CAN_T *tCAN)
+{
+    tCAN->STATUS = 0x0U; /* clr status */
+
+    while(1)
+    {
+        if(tCAN->IF[1].MCON & CAN_IF_MCON_NEWDAT_Msk)   /* check new data */
+        {
+            /* DEBUG_PRINTF("New Data IN\n"); */
+            break;
+        }
+
+        if(tCAN->STATUS & CAN_STATUS_RXOK_Msk)
+        {
+            /* DEBUG_PRINTF("Rx OK\n"); */
+        }
+
+        if(tCAN->STATUS & CAN_STATUS_LEC_Msk)
+        {
+            /* DEBUG_PRINTF("Error\n"); */
+        }
+    }
+}
+
+/**
+  * @brief Get current bit rate
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @return Current Bit-Rate (kilo bit per second)
+  * @details Return current CAN bit rate according to the user bit-timing parameter settings
+  */
+uint32_t CAN_GetCANBitRate(CAN_T *tCAN)
+{
+    uint8_t u8Tseg1, u8Tseg2;
+    uint32_t u32Bpr;
+
+    u8Tseg1 = (uint8_t)((tCAN->BTIME & CAN_BTIME_TSEG1_Msk) >> CAN_BTIME_TSEG1_Pos);
+    u8Tseg2 = (uint8_t)((tCAN->BTIME & CAN_BTIME_TSEG2_Msk) >> CAN_BTIME_TSEG2_Pos);
+    u32Bpr = (tCAN->BTIME & CAN_BTIME_BRP_Msk);
+    u32Bpr |= (tCAN->BRPE << 6);
+
+
+    return (SystemCoreClock / (u32Bpr + 1U) / ((uint32_t)u8Tseg1 + (uint32_t)u8Tseg2 + 3U));
+}
+
+/**
+  * @brief Switch the CAN into test mode.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u8TestMask Specifies the configuration in test modes
+  *                       \ref CAN_TEST_BASIC_Msk Enable basic mode of test mode
+  *                       \ref CAN_TEST_SILENT_Msk Enable silent mode of test mode
+  *                       \ref CAN_TEST_LBACK_Msk Enable Loop Back Mode of test mode
+  *                       \ref CAN_TEST_TX0_Msk / \ref CAN_TEST_TX1_Msk Control CAN_TX pin bit field
+  * @return None
+  * @details Switch the CAN into test mode. There are four test mode (BASIC/SILENT/LOOPBACK/
+  *          LOOPBACK combined SILENT/CONTROL_TX_PIN)could be selected. After setting test mode,user
+  *          must call CAN_LeaveInitMode() to let the setting take effect.
+  */
+void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask)
+{
+    tCAN->CON |= CAN_CON_TEST_Msk;
+    tCAN->TEST = u8TestMask;
+}
+
+
+/**
+  * @brief Leave the test mode
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @return   None
+  * @details  This function is used to Leave the test mode (switch into normal mode).
+  */
+void CAN_LeaveTestMode(CAN_T *tCAN)
+{
+    tCAN->CON |= CAN_CON_TEST_Msk;
+    tCAN->TEST &= ~(CAN_TEST_LBACK_Msk | CAN_TEST_SILENT_Msk | CAN_TEST_BASIC_Msk);
+    tCAN->CON &= (~CAN_CON_TEST_Msk);
+}
+
+/**
+  * @brief Get the waiting status of a received message.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.
+  * @retval non-zero The corresponding message object has a new data bit is set.
+  * @retval 0 No message object has new data.
+  * @details This function is used to get the waiting status of a received message.
+  */
+uint32_t CAN_IsNewDataReceived(CAN_T *tCAN, uint8_t u8MsgObj)
+{
+    uint32_t ret;
+
+    if((uint32_t)u8MsgObj < 16U)
+    {
+        ret = tCAN->NDAT1 & (1UL << u8MsgObj);
+    }
+    else
+    {
+        ret = tCAN->NDAT2 & (1UL << (u8MsgObj - 16U));
+    }
+
+    return ret;
+}
+
+
+/**
+  * @brief Send CAN message in BASIC mode of test mode
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] pCanMsg Pointer to the message structure containing data to transmit.
+  * @return TRUE:  Transmission OK
+  *         FALSE: Check busy flag of interface 0 is timeout
+  * @details The function is used to send CAN message in BASIC mode of test mode. Before call the API,
+  *          the user should be call CAN_EnterTestMode(CAN_TEST_BASIC) and let CAN controller enter
+  *          basic mode of test mode. Please notice IF1 Registers used as Tx Buffer in basic mode.
+  */
+int32_t CAN_BasicSendMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg)
+{
+    uint32_t i = 0UL;
+    while(tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) {}
+
+
+    tCAN->STATUS &= (~CAN_STATUS_TXOK_Msk);
+
+    if(pCanMsg->IdType == CAN_STD_ID)
+    {
+        /* standard ID*/
+        tCAN->IF[0].ARB1 = 0UL;
+        tCAN->IF[0].ARB2 = (((pCanMsg->Id) & 0x7FFUL) << 2) ;
+    }
+    else
+    {
+        /* extended ID*/
+        tCAN->IF[0].ARB1 = (pCanMsg->Id) & 0xFFFFUL;
+        tCAN->IF[0].ARB2 = (((pCanMsg->Id) & 0x1FFF0000UL) >> 16)  | CAN_IF_ARB2_XTD_Msk;
+
+    }
+
+    if(pCanMsg->FrameType)
+    {
+        tCAN->IF[0].ARB2 |= CAN_IF_ARB2_DIR_Msk;
+    }
+    else
+    {
+        tCAN->IF[0].ARB2 &= (~CAN_IF_ARB2_DIR_Msk);
+    }
+
+    tCAN->IF[0].MCON = (tCAN->IF[0].MCON & (~CAN_IF_MCON_DLC_Msk)) | pCanMsg->DLC;
+    tCAN->IF[0].DAT_A1 = ((uint32_t)pCanMsg->Data[1] << 8) | pCanMsg->Data[0];
+    tCAN->IF[0].DAT_A2 = ((uint32_t)pCanMsg->Data[3] << 8) | pCanMsg->Data[2];
+    tCAN->IF[0].DAT_B1 = ((uint32_t)pCanMsg->Data[5] << 8) | pCanMsg->Data[4];
+    tCAN->IF[0].DAT_B2 = ((uint32_t)pCanMsg->Data[7] << 8) | pCanMsg->Data[6];
+
+    /* request transmission*/
+    tCAN->IF[0].CREQ &= (~CAN_IF_CREQ_BUSY_Msk);
+    if(tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk)
+    {
+        /* DEBUG_PRINTF("Cannot clear busy for sending ...\n"); */
+        return (int32_t)FALSE;
+    }
+
+    tCAN->IF[0].CREQ |= CAN_IF_CREQ_BUSY_Msk; /* sending */
+
+    for(i = 0UL; i < 0xFFFFFUL; i++)
+    {
+        if((tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0UL)
+        {
+            break;
+        }
+    }
+
+    if(i >= 0xFFFFFUL)
+    {
+        /* DEBUG_PRINTF("Cannot send out...\n"); */
+        return (int32_t)FALSE;
+    }
+
+
+    return (int32_t)TRUE;
+}
+
+/**
+  * @brief Get a message information in BASIC mode.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] pCanMsg Pointer to the message structure where received data is copied.
+  *
+  * @return FALSE No any message received.
+  *         TRUE Receive a message success.
+  *
+  */
+int32_t CAN_BasicReceiveMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg)
+{
+
+    if((tCAN->IF[1].MCON & CAN_IF_MCON_NEWDAT_Msk) == 0UL)   /* In basic mode, receive data always save in IF2 */
+    {
+        return (int32_t)FALSE;
+    }
+
+    tCAN->STATUS &= (~CAN_STATUS_RXOK_Msk);
+
+    tCAN->IF[1].CMASK = CAN_IF_CMASK_ARB_Msk
+                        | CAN_IF_CMASK_CONTROL_Msk
+                        | CAN_IF_CMASK_DATAA_Msk
+                        | CAN_IF_CMASK_DATAB_Msk;
+
+    if((tCAN->IF[1].ARB2 & CAN_IF_ARB2_XTD_Msk) == 0UL)
+    {
+        /* standard ID*/
+        pCanMsg->IdType = CAN_STD_ID;
+        pCanMsg->Id = (tCAN->IF[1].ARB2 >> 2) & 0x07FFUL;
+
+    }
+    else
+    {
+        /* extended ID*/
+        pCanMsg->IdType = CAN_EXT_ID;
+        pCanMsg->Id  = (tCAN->IF[1].ARB2 & 0x1FFFUL) << 16;
+        pCanMsg->Id |= (uint32_t)tCAN->IF[1].ARB1;
+    }
+
+    /*
+    pCanMsg->FrameType = (uint32_t)(!(uint32_t)((tCAN->IF[1].ARB2 & (uint32_t)CAN_IF_ARB2_DIR_Msk) >> (uint32_t)CAN_IF_ARB2_DIR_Pos));
+    */
+
+    pCanMsg->FrameType = (tCAN->IF[1].ARB2 & CAN_IF_ARB2_DIR_Msk) ? 0UL : 1UL;
+
+    pCanMsg->DLC     = (uint8_t)(tCAN->IF[1].MCON & CAN_IF_MCON_DLC_Msk);
+    pCanMsg->Data[0] = (uint8_t)(tCAN->IF[1].DAT_A1 & CAN_IF_DAT_A1_DATA0_Msk);
+    pCanMsg->Data[1] = (uint8_t)((tCAN->IF[1].DAT_A1 & CAN_IF_DAT_A1_DATA1_Msk) >> CAN_IF_DAT_A1_DATA1_Pos);
+    pCanMsg->Data[2] = (uint8_t)(tCAN->IF[1].DAT_A2 & CAN_IF_DAT_A2_DATA2_Msk);
+    pCanMsg->Data[3] = (uint8_t)((tCAN->IF[1].DAT_A2 & CAN_IF_DAT_A2_DATA3_Msk) >> CAN_IF_DAT_A2_DATA3_Pos);
+    pCanMsg->Data[4] = (uint8_t)(tCAN->IF[1].DAT_B1 & CAN_IF_DAT_B1_DATA4_Msk);
+    pCanMsg->Data[5] = (uint8_t)((tCAN->IF[1].DAT_B1 & CAN_IF_DAT_B1_DATA5_Msk) >> CAN_IF_DAT_B1_DATA5_Pos);
+    pCanMsg->Data[6] = (uint8_t)(tCAN->IF[1].DAT_B2 & CAN_IF_DAT_B2_DATA6_Msk);
+    pCanMsg->Data[7] = (uint8_t)((tCAN->IF[1].DAT_B2 & CAN_IF_DAT_B2_DATA7_Msk) >> CAN_IF_DAT_B2_DATA7_Pos);
+
+    return (int32_t)TRUE;
+}
+
+/**
+  * @brief Set Rx message object, include ID mask.
+  * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.
+  * @param[in] u8idType Specifies the identifier type of the frames that will be transmitted
+  *                     This parameter can be one of the following values:
+  *                     \ref CAN_STD_ID (standard ID, 11-bit)
+  *                     \ref CAN_EXT_ID (extended ID, 29-bit)
+  * @param[in] u32id Specifies the identifier used for acceptance filtering.
+  * @param[in] u8singleOrFifoLast Specifies the end-of-buffer indicator.
+  *                               This parameter can be one of the following values:
+  *                               TRUE: for a single receive object or a FIFO receive object that is the last one of the FIFO.
+  *                               FALSE: for a FIFO receive object that is not the last one.
+  * @retval TRUE SUCCESS
+  * @retval FALSE No useful interface
+  * @details The function is used to configure a receive message object.
+  */
+int32_t CAN_SetRxMsgObjAndMsk(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint32_t u32idmask, uint8_t u8singleOrFifoLast)
+{
+    uint8_t u8MsgIfNum;
+
+    /* Get and lock a free interface */
+    if((u8MsgIfNum = (uint8_t)LockIF_TL(tCAN)) == 2U)
+    {
+        return (int32_t)FALSE;
+    }
+
+    /* Command Setting */
+    tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk |
+                                 CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk;
+
+    if(u8idType == CAN_STD_ID)    /* According STD/EXT ID format,Configure Mask and Arbitration register */
+    {
+        tCAN->IF[u8MsgIfNum].ARB1 = 0U;
+        tCAN->IF[u8MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | (u32id & 0x7FFUL) << 2;
+    }
+    else
+    {
+        tCAN->IF[u8MsgIfNum].ARB1 = u32id & 0xFFFFUL;
+        tCAN->IF[u8MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | CAN_IF_ARB2_XTD_Msk | (u32id & 0x1FFF0000UL) >> 16;
+    }
+
+    tCAN->IF[u8MsgIfNum].MASK1 = (u32idmask & 0xFFFFUL);
+    tCAN->IF[u8MsgIfNum].MASK2 = (u32idmask >> 16) & 0xFFFFUL;
+
+
+    tCAN->IF[u8MsgIfNum].MCON = CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk;
+    if(u8singleOrFifoLast)
+    {
+        tCAN->IF[u8MsgIfNum].MCON |= CAN_IF_MCON_EOB_Msk;
+    }
+    else
+    {
+        tCAN->IF[u8MsgIfNum].MCON &= (~CAN_IF_MCON_EOB_Msk);
+    }
+
+    tCAN->IF[u8MsgIfNum].DAT_A1  = 0U;
+    tCAN->IF[u8MsgIfNum].DAT_A2  = 0U;
+    tCAN->IF[u8MsgIfNum].DAT_B1  = 0U;
+    tCAN->IF[u8MsgIfNum].DAT_B2  = 0U;
+
+    tCAN->IF[u8MsgIfNum].CREQ = 1UL + u8MsgObj;
+    ReleaseIF(tCAN, (uint32_t)u8MsgIfNum);
+
+    return (int32_t)TRUE;
+}
+
+/**
+  * @brief Set Rx message object
+  * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.
+  * @param[in] u8idType Specifies the identifier type of the frames that will be transmitted
+  *                     This parameter can be one of the following values:
+  *                     \ref CAN_STD_ID (standard ID, 11-bit)
+  *                     \ref CAN_EXT_ID (extended ID, 29-bit)
+  * @param[in] u32id Specifies the identifier used for acceptance filtering.
+  * @param[in] u8singleOrFifoLast Specifies the end-of-buffer indicator.
+  *                               This parameter can be one of the following values:
+  *                               TRUE: for a single receive object or a FIFO receive object that is the last one of the FIFO.
+  *                               FALSE: for a FIFO receive object that is not the last one.
+  * @retval TRUE SUCCESS
+  * @retval FALSE No useful interface
+  * @details The function is used to configure a receive message object.
+  */
+int32_t CAN_SetRxMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint8_t u8singleOrFifoLast)
+{
+    uint8_t u8MsgIfNum;
+
+    /* Get and lock a free interface */
+    if((u8MsgIfNum = (uint8_t)LockIF_TL(tCAN)) == 2U)
+    {
+        return (int32_t)FALSE;
+    }
+
+    /* Command Setting */
+    tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk |
+                                 CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk;
+
+    if(u8idType == CAN_STD_ID)    /* According STD/EXT ID format,Configure Mask and Arbitration register */
+    {
+        tCAN->IF[u8MsgIfNum].ARB1 = 0U;
+        tCAN->IF[u8MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | (u32id & 0x7FFUL) << 2;
+    }
+    else
+    {
+        tCAN->IF[u8MsgIfNum].ARB1 = u32id & 0xFFFFUL;
+        tCAN->IF[u8MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | CAN_IF_ARB2_XTD_Msk | (u32id & 0x1FFF0000UL) >> 16;
+    }
+
+
+    tCAN->IF[u8MsgIfNum].MCON = CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk;
+    if(u8singleOrFifoLast)
+    {
+        tCAN->IF[u8MsgIfNum].MCON |= CAN_IF_MCON_EOB_Msk;
+    }
+    else
+    {
+        tCAN->IF[u8MsgIfNum].MCON &= (~CAN_IF_MCON_EOB_Msk);
+    }
+
+    tCAN->IF[u8MsgIfNum].DAT_A1  = 0U;
+    tCAN->IF[u8MsgIfNum].DAT_A2  = 0U;
+    tCAN->IF[u8MsgIfNum].DAT_B1  = 0U;
+    tCAN->IF[u8MsgIfNum].DAT_B2  = 0U;
+
+    tCAN->IF[u8MsgIfNum].CREQ = 1UL + u8MsgObj;
+    ReleaseIF(tCAN, (uint32_t)u8MsgIfNum);
+
+    return (int32_t)TRUE;
+}
+
+/**
+  * @brief Gets the message
+  * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31.
+  * @param[in] u8Release Specifies the message release indicator.
+  *                      This parameter can be one of the following values:
+  *                      TRUE: the message object is released when getting the data.
+  *                      FALSE:the message object is not released.
+  * @param[in] pCanMsg Pointer to the message structure where received data is copied.
+  * @retval TRUE Success
+  * @retval FALSE No any message received
+  * @details Gets the message, if received.
+  */
+int32_t CAN_ReadMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8Release, STR_CANMSG_T* pCanMsg)
+{
+    uint8_t u8MsgIfNum;
+    uint32_t u32Tmp;
+
+    if(!CAN_IsNewDataReceived(tCAN, u8MsgObj))
+    {
+        return (int32_t)FALSE;
+    }
+
+    /* Get and lock a free interface */
+    if((u8MsgIfNum = (uint8_t)LockIF_TL(tCAN)) == 2U)
+    {
+        return (int32_t)FALSE;
+    }
+
+    tCAN->STATUS &= (~CAN_STATUS_RXOK_Msk);
+
+    /* read the message contents*/
+    tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_MASK_Msk
+                                 | CAN_IF_CMASK_ARB_Msk
+                                 | CAN_IF_CMASK_CONTROL_Msk
+                                 | CAN_IF_CMASK_CLRINTPND_Msk
+                                 | (u8Release ? CAN_IF_CMASK_TXRQSTNEWDAT_Msk : 0UL)
+                                 | CAN_IF_CMASK_DATAA_Msk
+                                 | CAN_IF_CMASK_DATAB_Msk;
+
+    tCAN->IF[u8MsgIfNum].CREQ = 1UL + u8MsgObj;
+
+    while(tCAN->IF[u8MsgIfNum].CREQ & CAN_IF_CREQ_BUSY_Msk)
+    {
+        /*Wait*/
+    }
+
+    if((tCAN->IF[u8MsgIfNum].ARB2 & CAN_IF_ARB2_XTD_Msk) == 0U)
+    {
+        /* standard ID*/
+        pCanMsg->IdType = CAN_STD_ID;
+        pCanMsg->Id     = (tCAN->IF[u8MsgIfNum].ARB2 & CAN_IF_ARB2_ID_Msk) >> 2;
+    }
+    else
+    {
+        /* extended ID*/
+        pCanMsg->IdType = CAN_EXT_ID;
+
+        u32Tmp = (((tCAN->IF[u8MsgIfNum].ARB2) & 0x1FFFUL) << 16);
+        u32Tmp |= tCAN->IF[u8MsgIfNum].ARB1;
+
+        pCanMsg->Id  = u32Tmp;
+    }
+
+    pCanMsg->DLC     = (uint8_t)(tCAN->IF[u8MsgIfNum].MCON & CAN_IF_MCON_DLC_Msk);
+    pCanMsg->Data[0] = (uint8_t)(tCAN->IF[u8MsgIfNum].DAT_A1 & CAN_IF_DAT_A1_DATA0_Msk);
+    pCanMsg->Data[1] = (uint8_t)((tCAN->IF[u8MsgIfNum].DAT_A1 & CAN_IF_DAT_A1_DATA1_Msk) >> CAN_IF_DAT_A1_DATA1_Pos);
+    pCanMsg->Data[2] = (uint8_t)(tCAN->IF[u8MsgIfNum].DAT_A2 & CAN_IF_DAT_A2_DATA2_Msk);
+    pCanMsg->Data[3] = (uint8_t)((tCAN->IF[u8MsgIfNum].DAT_A2 & CAN_IF_DAT_A2_DATA3_Msk) >> CAN_IF_DAT_A2_DATA3_Pos);
+    pCanMsg->Data[4] = (uint8_t)(tCAN->IF[u8MsgIfNum].DAT_B1 & CAN_IF_DAT_B1_DATA4_Msk);
+    pCanMsg->Data[5] = (uint8_t)((tCAN->IF[u8MsgIfNum].DAT_B1 & CAN_IF_DAT_B1_DATA5_Msk) >> CAN_IF_DAT_B1_DATA5_Pos);
+    pCanMsg->Data[6] = (uint8_t)(tCAN->IF[u8MsgIfNum].DAT_B2 & CAN_IF_DAT_B2_DATA6_Msk);
+    pCanMsg->Data[7] = (uint8_t)((tCAN->IF[u8MsgIfNum].DAT_B2 & CAN_IF_DAT_B2_DATA7_Msk) >> CAN_IF_DAT_B2_DATA7_Pos);
+
+    ReleaseIF(tCAN, (uint32_t)u8MsgIfNum);
+    return (int32_t)TRUE;
+}
+
+static int can_update_spt(int sampl_pt, int tseg, int *tseg1, int *tseg2)
+{
+    *tseg2 = tseg + 1 - (sampl_pt * (tseg + 1)) / 1000;
+    if(*tseg2 < TSEG2_MIN)
+    {
+        *tseg2 = TSEG2_MIN;
+    }
+    if(*tseg2 > TSEG2_MAX)
+    {
+        *tseg2 = TSEG2_MAX;
+    }
+
+    *tseg1 = tseg - *tseg2;
+
+    if(*tseg1 > TSEG1_MAX)
+    {
+        *tseg1 = TSEG1_MAX;
+        *tseg2 = tseg - *tseg1;
+    }
+    return 1000 * (tseg + 1 - *tseg2) / (tseg + 1);
+}
+
+/** @endcond HIDDEN_SYMBOLS */
+
+/**
+  * @brief Set bus baud-rate.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32BaudRate The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz.
+  *
+  * @return u32CurrentBitRate  Real baud-rate value.
+  *
+  * @details The function is used to set bus timing parameter according current clock and target baud-rate.
+  */
+uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate)
+{
+    long rate;
+    long best_error = 1000000000, error = 0;
+    int best_tseg = 0, best_brp = 0, brp = 0;
+    int tsegall, tseg = 0, tseg1 = 0, tseg2 = 0;
+    int spt_error = 1000, spt = 0, sampl_pt;
+    int64_t clock_freq = 0;
+    uint32_t sjw = 1UL;
+
+    CAN_EnterInitMode(tCAN, 0U);
+
+    clock_freq = (int64_t)CLK_GetPCLK0Freq();
+
+    if(u32BaudRate >= 1000000UL)
+    {
+        u32BaudRate = 1000000UL;
+    }
+
+    /* Use CIA recommended sample points */
+    if(u32BaudRate > 800000UL)
+    {
+        sampl_pt = 750;
+    }
+    else if(u32BaudRate > 500000UL)
+    {
+        sampl_pt = 800;
+    }
+    else
+    {
+        sampl_pt = 875;
+    }
+
+    /* tseg even = round down, odd = round up */
+    for(tseg = (TSEG1_MAX + TSEG2_MAX) * 2 + 1; tseg >= (TSEG1_MIN + TSEG2_MIN) * 2; tseg--)
+    {
+        tsegall = 1 + tseg / 2;
+        /* Compute all possible tseg choices (tseg=tseg1+tseg2) */
+
+        /* brp = (int32_t)(clock_freq / (tsegall * u32BaudRate)) + (tseg % 2); */
+        brp = (int32_t)(clock_freq / ((int64_t)tsegall * (int32_t)u32BaudRate)) + (tseg % 2);
+
+
+        /* chose brp step which is possible in system */
+        brp = (brp / BRP_INC) * BRP_INC;
+
+        if((brp >= BRP_MIN) && (brp <= BRP_MAX))
+        {
+            rate = (int32_t)(clock_freq / ((int64_t)brp * tsegall));
+
+            error = (int32_t)u32BaudRate - rate;
+
+            /* tseg brp biterror */
+            if(error < 0)
+            {
+                error = -error;
+            }
+
+            if(error <= best_error)
+            {
+                best_error = error;
+                if(error == 0)
+                {
+                    spt = can_update_spt(sampl_pt, tseg / 2, &tseg1, &tseg2);
+                    error = sampl_pt - spt;
+                    if(error < 0)
+                    {
+                        error = -error;
+                    }
+                    if(error <= spt_error)
+                    {
+                        spt_error = error;
+                        best_tseg = tseg / 2;
+                        best_brp = brp;
+                        if(error == 0)
+                        {
+                            break;
+                        }
+                    }
+                }
+                else
+                {
+                    best_tseg = tseg / 2;
+                    best_brp = brp;
+                }
+            }
+        }
+    }
+
+    spt = can_update_spt(sampl_pt, best_tseg, &tseg1, &tseg2);
+
+    /* check for sjw user settings */
+    /* bt->sjw is at least 1 -> sanitize upper bound to sjw_max */
+    if(sjw > SJW_MAX)
+    {
+        sjw = SJW_MAX;
+    }
+    /* bt->sjw must not be higher than tseg2 */
+    if(tseg2 < (int32_t)sjw)
+    {
+        sjw = (uint32_t)tseg2;
+    }
+
+    /* real bit-rate */
+    u32BaudRate = (uint32_t)(int32_t)(clock_freq / (int32_t)(best_brp * (tseg1 + tseg2 + 1)));
+
+    tCAN->BTIME = (((uint32_t)tseg2 - 1UL) << CAN_BTIME_TSEG2_Pos) | (((uint32_t)tseg1 - 1UL) << CAN_BTIME_TSEG1_Pos) |
+                  (((uint32_t)best_brp - 1UL) & CAN_BTIME_BRP_Msk) | (sjw << CAN_BTIME_SJW_Pos);
+
+
+    tCAN->BRPE  = (((uint32_t)best_brp - 1UL) >> 6) & 0x0FUL;
+
+    /* DEBUG_PRINTF("\n bitrate = %d \n", CAN_GetCANBitRate(tCAN)); */
+
+    CAN_LeaveInitMode(tCAN);
+
+    return u32BaudRate;
+}
+
+/**
+  * @brief The function is used to disable all CAN interrupt.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  *
+  * @return None
+  *
+  * @details No Status Change Interrupt and Error Status Interrupt will be generated.
+  */
+
+
+void CAN_Close(CAN_T *tCAN)
+{
+    CAN_DisableInt(tCAN, (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk));
+}
+
+
+
+/**
+  * @brief Set CAN operation mode and target baud-rate.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32BaudRate The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz.
+  * @param[in] u32Mode The CAN operation mode. Valid values are:
+  *                    - \ref CAN_NORMAL_MODE Normal operation.
+  *                    - \ref CAN_BASIC_MODE Basic mode.
+  * @return u32CurrentBitRate  Real baud-rate value.
+  *
+  * @details Set bus timing parameter according current clock and target baud-rate.
+  *          In Basic mode, IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer.
+  */
+uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode)
+{
+    uint32_t u32CurrentBitRate;
+
+    u32CurrentBitRate = CAN_SetBaudRate(tCAN, u32BaudRate);
+
+    if(u32Mode == CAN_BASIC_MODE)
+    {
+        CAN_EnterTestMode(tCAN, (uint8_t)CAN_TEST_BASIC_Msk);
+    }
+
+    return u32CurrentBitRate;
+}
+
+/**
+  * @brief The function is used to configure a transmit object.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+  * @param[in] pCanMsg Pointer to the message structure where received data is copied.
+  *
+  * @retval FALSE No useful interface.
+  * @retval TRUE Config message object success.
+  *
+  * @details The two sets of interface registers (IF1 and IF2) control the software access to the Message RAM.
+  *          They buffer the data to be transferred to and from the RAM, avoiding conflicts between software accesses and message reception/transmission.
+  */
+int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg)
+{
+    uint8_t u8MsgIfNum;
+
+    if((u8MsgIfNum = (uint8_t)LockIF_TL(tCAN)) == 2U)
+    {
+        return (int32_t)FALSE;
+    }
+
+    /* update the contents needed for transmission*/
+    tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk |
+                                 CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk  | CAN_IF_CMASK_DATAB_Msk;
+
+    if(pCanMsg->IdType == CAN_STD_ID)
+    {
+        /* standard ID*/
+        tCAN->IF[u8MsgIfNum].ARB1 = 0UL;
+        tCAN->IF[u8MsgIfNum].ARB2 = (((pCanMsg->Id) & 0x7FFUL) << 2) | CAN_IF_ARB2_DIR_Msk | CAN_IF_ARB2_MSGVAL_Msk;
+    }
+    else
+    {
+        /* extended ID*/
+        tCAN->IF[u8MsgIfNum].ARB1 = (pCanMsg->Id) & 0xFFFFUL;
+        tCAN->IF[u8MsgIfNum].ARB2 = (((pCanMsg->Id) & 0x1FFF0000UL) >> 16) | CAN_IF_ARB2_DIR_Msk | CAN_IF_ARB2_XTD_Msk | CAN_IF_ARB2_MSGVAL_Msk;
+    }
+
+    if(pCanMsg->FrameType)
+    {
+        tCAN->IF[u8MsgIfNum].ARB2 |=   CAN_IF_ARB2_DIR_Msk;
+    }
+    else
+    {
+        tCAN->IF[u8MsgIfNum].ARB2 &= (~CAN_IF_ARB2_DIR_Msk);
+    }
+
+
+    tCAN->IF[u8MsgIfNum].DAT_A1 = ((uint32_t)pCanMsg->Data[1] << 8) | (uint32_t)pCanMsg->Data[0];
+    tCAN->IF[u8MsgIfNum].DAT_A2 = ((uint32_t)pCanMsg->Data[3] << 8) | (uint32_t)pCanMsg->Data[2];
+    tCAN->IF[u8MsgIfNum].DAT_B1 = ((uint32_t)pCanMsg->Data[5] << 8) | pCanMsg->Data[4];
+    tCAN->IF[u8MsgIfNum].DAT_B2 = ((uint32_t)pCanMsg->Data[7] << 8) | pCanMsg->Data[6];
+
+    tCAN->IF[u8MsgIfNum].MCON   =  CAN_IF_MCON_NEWDAT_Msk | pCanMsg->DLC | CAN_IF_MCON_TXIE_Msk | CAN_IF_MCON_EOB_Msk;
+    tCAN->IF[u8MsgIfNum].CREQ   = 1UL + u32MsgNum;
+
+    ReleaseIF(tCAN, (uint32_t)u8MsgIfNum);
+
+    return (int32_t)TRUE;
+}
+
+/**
+  * @brief Set transmit request bit.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+  *
+  * @return TRUE: Start transmit message.
+  *
+  * @details If a transmission is requested by programming bit TxRqst/NewDat (IFn_CMASK[2]), the TxRqst (IFn_MCON[8]) will be ignored.
+  */
+int32_t CAN_TriggerTxMsg(CAN_T  *tCAN, uint32_t u32MsgNum)
+{
+    uint8_t u8MsgIfNum;
+
+    if((u8MsgIfNum = (uint8_t)LockIF_TL(tCAN)) == 2U)
+    {
+        return (int32_t)FALSE;
+    }
+
+    tCAN->STATUS &= (~CAN_STATUS_TXOK_Msk);
+
+    /* read the message contents*/
+    tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_CLRINTPND_Msk
+                                 | CAN_IF_CMASK_TXRQSTNEWDAT_Msk;
+
+    tCAN->IF[u8MsgIfNum].CREQ = 1UL + u32MsgNum;
+
+    while(tCAN->IF[u8MsgIfNum].CREQ & CAN_IF_CREQ_BUSY_Msk)
+    {
+        /*Wait*/
+    }
+    tCAN->IF[u8MsgIfNum].CMASK  = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk;
+    tCAN->IF[u8MsgIfNum].CREQ  = 1UL + u32MsgNum;
+
+    ReleaseIF(tCAN, (uint32_t)u8MsgIfNum);
+
+    return (int32_t)TRUE;
+}
+
+/**
+  * @brief Enable CAN interrupt.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32Mask Interrupt Mask. Valid values are:
+  *                    - \ref CAN_CON_IE_Msk Module interrupt enable.
+  *                    - \ref CAN_CON_SIE_Msk Status change interrupt enable.
+  *                    - \ref CAN_CON_EIE_Msk Error interrupt enable.
+  *
+  * @return None
+  *
+  * @details The application software has two possibilities to follow the source of a message interrupt.
+  *          First, it can follow the IntId in the Interrupt Register and second it can poll the Interrupt Pending Register.
+  */
+void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask)
+{
+    tCAN->CON = (tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk)) |
+                (u32Mask & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk));
+}
+
+/**
+  * @brief Disable CAN interrupt.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32Mask Interrupt Mask. (CAN_CON_IE_Msk / CAN_CON_SIE_Msk / CAN_CON_EIE_Msk).
+  *
+  * @return None
+  *
+  * @details The interrupt remains active until the Interrupt Register is back to value zero (the cause of the interrupt is reset) or until IE is reset.
+  */
+void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask)
+{
+    tCAN->CON = tCAN->CON & ~((u32Mask & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk)));
+}
+
+
+/**
+  * @brief The function is used to configure a receive message object.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+  * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are:
+  *                      - \ref CAN_STD_ID The 11-bit identifier.
+  *                      - \ref CAN_EXT_ID The 29-bit identifier.
+  * @param[in] u32ID Specifies the identifier used for acceptance filtering.
+  *
+  * @retval FALSE No useful interface.
+  * @retval TRUE Configure a receive message object success.
+  *
+  * @details If the RxIE bit (CAN_IFn_MCON[10]) is set, the IntPnd bit (CAN_IFn_MCON[13])
+  *          will be set when a received Data Frame is accepted and stored in the Message Object.
+  */
+int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID)
+{
+    uint32_t u32TimeOutCount = 0UL;
+
+    while(CAN_SetRxMsgObj(tCAN, (uint8_t)u32MsgNum, (uint8_t)u32IDType, u32ID, (uint8_t)TRUE) == (int32_t)FALSE)
+    {
+        if(++u32TimeOutCount >= RETRY_COUNTS)
+        {
+            return (int32_t)FALSE;
+        }
+    }
+
+    return (int32_t)TRUE;
+}
+
+/**
+  * @brief The function is used to configure a receive message object.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+  * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are:
+  *                      - \ref CAN_STD_ID The 11-bit identifier.
+  *                      - \ref CAN_EXT_ID The 29-bit identifier.
+  * @param[in] u32ID Specifies the identifier used for acceptance filtering.
+  * @param[in] u32IDMask Specifies the identifier mask used for acceptance filtering.
+  *
+  * @retval FALSE No useful interface.
+  * @retval TRUE Configure a receive message object success.
+  *
+  * @details If the RxIE bit (CAN_IFn_MCON[10]) is set, the IntPnd bit (CAN_IFn_MCON[13])
+  *          will be set when a received Data Frame is accepted and stored in the Message Object.
+  */
+int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask)
+{
+    uint32_t u32TimeOutCount = 0UL;
+
+    while(CAN_SetRxMsgObjAndMsk(tCAN, (uint8_t)u32MsgNum, (uint8_t)u32IDType, u32ID, u32IDMask, (uint8_t)TRUE) == (int32_t)FALSE)
+    {
+        if(++u32TimeOutCount >= RETRY_COUNTS)
+        {
+            return (int32_t)FALSE;
+        }
+    }
+
+    return (int32_t)TRUE;
+}
+
+/**
+  * @brief The function is used to configure several receive message objects.
+  *
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum The starting MSG RAM number(0 ~ 31).
+  * @param[in] u32MsgCount the number of MSG RAM of the FIFO.
+  * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are:
+  *                      - \ref CAN_STD_ID The 11-bit identifier.
+  *                      - \ref CAN_EXT_ID The 29-bit identifier.
+  * @param[in] u32ID Specifies the identifier used for acceptance filtering.
+  *
+  * @retval FALSE No useful interface.
+  * @retval TRUE Configure receive message objects success.
+  *
+  * @details The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message reception
+  *          and transmission by buffering the data to be transferred.
+  */
+int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID)
+{
+    uint32_t i;
+    uint32_t u32TimeOutCount;
+    uint32_t u32EOB_Flag = 0UL;
+
+    for(i = 1UL; i <= u32MsgCount; i++)
+    {
+        u32TimeOutCount = 0UL;
+
+        u32MsgNum += (i - 1UL);
+
+        if(i == u32MsgCount)
+        {
+            u32EOB_Flag = 1UL;
+        }
+
+        while(CAN_SetRxMsgObj(tCAN, (uint8_t)u32MsgNum, (uint8_t)u32IDType, u32ID, (uint8_t)u32EOB_Flag) == (int32_t)FALSE)
+        {
+            if(++u32TimeOutCount >= RETRY_COUNTS)
+            {
+                return (int32_t)FALSE;
+            }
+        }
+    }
+
+    return (int32_t)TRUE;
+}
+
+
+/**
+  * @brief Send CAN message.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+  * @param[in] pCanMsg Pointer to the message structure where received data is copied.
+  *
+  * @retval FALSE 1. When operation in basic mode: Transmit message time out. \n
+  *               2. When operation in normal mode: No useful interface. \n
+  * @retval TRUE Transmit Message success.
+  *
+  * @details The receive/transmit priority for the Message Objects is attached to the message number.
+  *          Message Object 1 has the highest priority, while Message Object 32 has the lowest priority.
+  */
+int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg)
+{
+    uint32_t cond0, cond1;
+
+    cond0 = tCAN->CON & CAN_CON_TEST_Msk;
+    cond1 = tCAN->TEST & CAN_TEST_BASIC_Msk;
+    if(cond0 && cond1)
+    {
+        return (CAN_BasicSendMsg(tCAN, pCanMsg));
+    }
+    else
+    {
+        if(CAN_SetTxMsg(tCAN, u32MsgNum, pCanMsg) == (int32_t)FALSE)
+        {
+            return (int32_t)FALSE;
+        }
+        CAN_TriggerTxMsg(tCAN, u32MsgNum);
+    }
+
+    return (int32_t)TRUE;
+}
+
+
+/**
+  * @brief Gets the message, if received.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+  * @param[in] pCanMsg Pointer to the message structure where received data is copied.
+  *
+  * @retval FALSE No any message received.
+  * @retval TRUE Receive Message success.
+  *
+  * @details The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message reception
+  *          and transmission by buffering the data to be transferred.
+  */
+int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg)
+{
+    uint32_t cond0, cond1;
+
+    cond0 = tCAN->CON & CAN_CON_TEST_Msk;
+    cond1 = tCAN->TEST & CAN_TEST_BASIC_Msk;
+
+    if(cond0 && cond1)
+    {
+        return (CAN_BasicReceiveMsg(tCAN, pCanMsg));
+    }
+    else
+    {
+        return CAN_ReadMsgObj(tCAN, (uint8_t)u32MsgNum, (uint8_t)TRUE, pCanMsg);
+    }
+}
+
+/**
+  * @brief Clear interrupt pending bit.
+  * @param[in] tCAN The pointer to CAN module base address.
+  * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31.
+  *
+  * @return None
+  *
+  * @details An interrupt remains pending until the application software has cleared it.
+  */
+void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum)
+{
+    uint32_t u32MsgIfNum;
+
+    if((u32MsgIfNum = LockIF_TL(tCAN)) == 2UL)
+    {
+        u32MsgIfNum = 0UL;
+    }
+
+    tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_CLRINTPND_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk;
+    tCAN->IF[u32MsgIfNum].CREQ = 1UL + u32MsgNum;
+
+    ReleaseIF(tCAN, u32MsgIfNum);
+}
+
+/**@}*/ /* end of group CAN_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group CAN_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_clk.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_clk.c
new file mode 100644
index 0000000000..00129c15b9
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_clk.c
@@ -0,0 +1,1406 @@
+/**************************************************************************//**
+ * @file     clk.c
+ * @version  V3.00
+ * @brief    M2354 series Clock Controller (CLK) driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup CLK_Driver CLK Driver
+  @{
+*/
+
+
+/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions
+  @{
+*/
+
+
+/**
+  * @brief      Disable frequency output function
+  * @param      None
+  * @return     None
+  * @details    This function disable frequency output function.
+  */
+void CLK_DisableCKO(void)
+{
+    /* Disable CKO clock source */
+    CLK->APBCLK0 &= (~CLK_APBCLK0_CLKOCKEN_Msk);
+}
+
+
+/**
+  * @brief      This function enable frequency divider module clock.
+  *             enable frequency divider clock function and configure frequency divider.
+  * @param[in]  u32ClkSrc is frequency divider function clock source. Including :
+  *             - \ref CLK_CLKSEL1_CLKOSEL_HXT
+  *             - \ref CLK_CLKSEL1_CLKOSEL_LXT
+  *             - \ref CLK_CLKSEL1_CLKOSEL_HCLK
+  *             - \ref CLK_CLKSEL1_CLKOSEL_HIRC
+  * @param[in]  u32ClkDiv is divider output frequency selection.
+  * @param[in]  u32ClkDivBy1En is frequency divided by one enable.
+  * @return     None
+  *
+  * @details    Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv.
+  *             The formula is:
+  *                 CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1)
+  *             This function is just used to set CKO clock.
+  *             User must enable I/O for CKO clock output pin by themselves.
+  */
+void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
+{
+    /* CKO = clock source / 2^(u32ClkDiv + 1) */
+    CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | u32ClkDiv | (u32ClkDivBy1En << CLK_CLKOCTL_DIV1EN_Pos);
+
+    /* Enable CKO clock source */
+    CLK->APBCLK0 |= CLK_APBCLK0_CLKOCKEN_Msk;
+
+    /* Select CKO clock source */
+    CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_CLKOSEL_Msk)) | (u32ClkSrc);
+
+}
+
+/**
+  * @brief      Enter to Power-down mode
+  * @param      None
+  * @return     None
+  * @details    This function is used to let system enter to Power-down mode. \n
+  *             The register write-protection function should be disabled before using this function.
+  */
+void CLK_PowerDown(void)
+{
+    volatile uint32_t u32SysTickTICKINT = 0;    /* Backup Systick interrupt enable bit */
+
+    /* Set the processor uses deep sleep as its low power mode */
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+    /* Set system Power-down enabled */
+    CLK->PWRCTL |= CLK_PWRCTL_PDEN_Msk;
+
+    /* Backup systick interrupt setting */
+    u32SysTickTICKINT = SysTick->CTRL & SysTick_CTRL_TICKINT_Msk;
+
+    /* Disable systick interrupt */
+    SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+
+    /* Chip enter Power-down mode after CPU run WFI instruction */
+    __WFI();
+
+    /* Restore systick interrupt setting */
+    if(u32SysTickTICKINT) SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
+}
+
+
+/**
+  * @brief      Enter to Idle mode
+  * @param      None
+  * @return     None
+  * @details    This function let system enter to Idle mode. \n
+  *             The register write-protection function should be disabled before using this function.
+  */
+void CLK_Idle(void)
+{
+    /* Set the processor uses sleep as its low power mode */
+    SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+
+    /* Set chip in idle mode because of WFI command */
+    CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk;
+
+    /* Chip enter idle mode after CPU run WFI instruction */
+    __WFI();
+}
+
+
+/**
+  * @brief      Get external high speed crystal clock frequency
+  * @param      None
+  * @return     External high frequency crystal frequency
+  * @details    This function get external high frequency crystal frequency. The frequency unit is Hz.
+  */
+__NONSECURE_ENTRY_WEAK
+uint32_t CLK_GetHXTFreq(void)
+{
+    uint32_t u32Freq = 0UL;
+    uint32_t u32HXTEN = CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk;
+
+    if(u32HXTEN)
+    {
+        u32Freq = __HXT;
+    }
+    else
+    {
+        u32Freq = 0UL;
+    }
+
+    return u32Freq;
+}
+
+/**
+  * @brief      Get external low speed crystal clock frequency
+  * @param      None
+  * @return     External low speed crystal clock frequency
+  * @details    This function get external low frequency crystal frequency. The frequency unit is Hz.
+  */
+
+__NONSECURE_ENTRY_WEAK
+uint32_t CLK_GetLXTFreq(void)
+{
+    uint32_t u32Freq = 0UL;
+    uint32_t u32LXTEN = CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk;
+
+    if(u32LXTEN)
+    {
+        u32Freq = __LXT;
+    }
+    else
+    {
+        u32Freq = 0UL;
+    }
+
+    return u32Freq;
+}
+
+/**
+  * @brief      Get HCLK frequency
+  * @param      None
+  * @return     HCLK frequency
+  * @details    This function get HCLK frequency. The frequency unit is Hz.
+  */
+
+__NONSECURE_ENTRY_WEAK
+uint32_t CLK_GetHCLKFreq(void)
+{
+    SystemCoreClockUpdate();
+    return SystemCoreClock;
+}
+
+/**
+  * @brief      Get PCLK0 frequency
+  * @param      None
+  * @return     PCLK0 frequency
+  * @details    This function get PCLK0 frequency. The frequency unit is Hz.
+  */
+
+__NONSECURE_ENTRY_WEAK
+uint32_t CLK_GetPCLK0Freq(void)
+{
+    SystemCoreClockUpdate();
+    return (SystemCoreClock);
+}
+
+/**
+  * @brief      Get PCLK1 frequency
+  * @param      None
+  * @return     PCLK1 frequency
+  * @details    This function get PCLK1 frequency. The frequency unit is Hz.
+  */
+
+__NONSECURE_ENTRY_WEAK
+uint32_t CLK_GetPCLK1Freq(void)
+{
+    SystemCoreClockUpdate();
+    return (SystemCoreClock);
+}
+
+/**
+  * @brief      Get CPU frequency
+  * @param      None
+  * @return     CPU frequency
+  * @details    This function get CPU frequency. The frequency unit is Hz.
+  */
+
+__NONSECURE_ENTRY_WEAK
+uint32_t CLK_GetCPUFreq(void)
+{
+    uint32_t u32Freq, u32HclkSrc, u32HclkDiv;
+    uint32_t au32ClkTbl[] = {__HXT, __LXT, 0UL, __LIRC, 0UL, __HIRC48, __MIRC, __HIRC};
+    uint32_t u32PllReg, u32FIN, u32NF, u32NR, u32NO;
+    uint8_t au8NoTbl[4] = {1U, 2U, 2U, 4U};
+    uint32_t u32RTCCKEN = CLK->APBCLK0 & CLK_APBCLK0_RTCCKEN_Msk;
+
+    /* Update PLL Clock */
+    u32PllReg = CLK->PLLCTL;
+
+    if(u32PllReg & CLK_PLLCTL_PD_Msk)
+    {
+        PllClock = 0UL;         /* PLL is in power down mode */
+    }
+    else                        /* PLL is in normal mode */
+    {
+
+        /* PLL source clock */
+        if(u32PllReg & CLK_PLLCTL_PLLSRC_Msk)
+        {
+            u32FIN = __HIRC;    /* PLL source clock from HIRC */
+        }
+        else
+        {
+            u32FIN = __HXT;     /* PLL source clock from HXT */
+        }
+
+        /* Calculate PLL frequency */
+        if(u32PllReg & CLK_PLLCTL_BP_Msk)
+        {
+            PllClock = u32FIN;  /* PLL is in bypass mode */
+        }
+        else
+        {
+            /* PLL is output enabled in normal work mode */
+            u32NO = au8NoTbl[((u32PllReg & CLK_PLLCTL_OUTDIV_Msk) >> CLK_PLLCTL_OUTDIV_Pos)];
+            u32NF = ((u32PllReg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2UL;
+            u32NR = ((u32PllReg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos) + 1UL;
+
+            /* u32FIN is shifted 2 bits to avoid overflow */
+            PllClock = (((u32FIN >> 2) * (u32NF << 1)) / (u32NR * u32NO) << 2);
+        }
+    }
+
+    /* HCLK clock source */
+    u32HclkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
+
+    if(u32HclkSrc == CLK_CLKSEL0_HCLKSEL_LXT)
+    {
+
+        if(u32RTCCKEN == 0UL)
+        {
+            CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk; /* Enable RTC clock to get LXT clock source */
+        }
+
+        if(RTC->LXTCTL & RTC_LXTCTL_C32KSEL_Msk)
+        {
+            u32Freq = __LIRC32; /* LXT clock source is LIRC32 */
+        }
+        else
+        {
+            u32Freq = __LXT;    /* LXT clock source is external LXT */
+        }
+
+        if(u32RTCCKEN == 0UL)
+        {
+            CLK->APBCLK0 &= (~CLK_APBCLK0_RTCCKEN_Msk); /* Disable RTC clock if it is disabled before */
+        }
+
+    }
+    else if(u32HclkSrc == CLK_CLKSEL0_HCLKSEL_PLL)
+    {
+        u32Freq = PllClock;/* Use PLL clock */
+    }
+    else
+    {
+        u32Freq = au32ClkTbl[u32HclkSrc]; /* Use the clock sources directly */
+    }
+
+    /* HCLK clock source divider */
+    u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1UL;
+
+    /* Update System Core Clock */
+    SystemCoreClock = u32Freq / u32HclkDiv;
+
+    /* Update Cycles per micro second */
+    CyclesPerUs = (SystemCoreClock + 500000UL) / 1000000UL;
+
+    return SystemCoreClock;
+}
+
+/**
+  * @brief      Set HCLK frequency
+  * @param[in]  u32Hclk is HCLK frequency.
+  *             The range of u32Hclk is 24 MHz ~ 96 MHz.
+  * @return     HCLK frequency
+  * @details    This function is used to set HCLK frequency by using PLL. \n
+  *             Power level is also set according to HCLK frequency. The frequency unit is Hz. \n
+  *             The register write-protection function should be disabled before using this function.
+  */
+uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
+{
+    uint32_t u32HIRCSTB;
+
+    /* Read HIRC clock source stable flag */
+    u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
+
+    /* Check HCLK frequency range */
+    if(u32Hclk > FREQ_96MHZ)
+    {
+        u32Hclk = FREQ_96MHZ;
+    }
+    else if(u32Hclk < FREQ_24MHZ)
+    {
+        u32Hclk = FREQ_24MHZ;
+    }
+
+    /* Switch HCLK clock source to HIRC clock for safe */
+    CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
+    CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
+    CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_Msk;
+    CLK->CLKDIV0 &= (~CLK_CLKDIV0_HCLKDIV_Msk);
+
+    /* Configure PLL setting if HXT clock is stable */
+    if(CLK->STATUS & CLK_STATUS_HXTSTB_Msk)
+    {
+        u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HXT, u32Hclk);
+    }
+    /* Configure PLL setting if HXT clock is not stable */
+    else
+    {
+        u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HIRC, u32Hclk);
+
+        /* Read HIRC clock source stable flag */
+        u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
+    }
+
+    /* Select HCLK clock source to PLL,
+       select HCLK clock source divider as 1,
+       adjust power level and update system core clock
+    */
+    CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(1UL));
+
+    /* Disable HIRC if HIRC is disabled before setting core clock */
+    if(u32HIRCSTB == 0UL)
+    {
+        CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
+    }
+
+    /* Return actually HCLK frequency is PLL frequency divide 1 */
+    return u32Hclk;
+}
+
+
+/**
+  * @brief      Set HCLK clock source and HCLK clock divider
+  * @param[in]  u32ClkSrc is HCLK clock source. Including :
+  *             - \ref CLK_CLKSEL0_HCLKSEL_HXT
+  *             - \ref CLK_CLKSEL0_HCLKSEL_LXT
+  *             - \ref CLK_CLKSEL0_HCLKSEL_PLL
+  *             - \ref CLK_CLKSEL0_HCLKSEL_LIRC
+  *             - \ref CLK_CLKSEL0_HCLKSEL_HIRC48
+  *             - \ref CLK_CLKSEL0_HCLKSEL_MIRC
+  *             - \ref CLK_CLKSEL0_HCLKSEL_HIRC
+  * @param[in]  u32ClkDiv is HCLK clock divider. Including :
+  *             - \ref CLK_CLKDIV0_HCLK(x)
+  * @return     None
+  * @details    This function set HCLK clock source and HCLK clock divider. \n
+  *             Power level and flash access cycle are also set according to HCLK operation frequency. \n
+  *             The register write-protection function should be disabled before using this function.
+  */
+void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
+{
+    uint32_t u32HIRCSTB;
+
+    /* Read HIRC clock source stable flag */
+    u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
+
+    /* Switch to HIRC for safe. Avoid HCLK too high when applying new divider. */
+    CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
+    CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
+    CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_Msk;
+
+    /* Switch to power level 0 for safe */
+    while(SYS->PLCTL & SYS_PLCTL_WRBUSY_Msk);
+    SYS->PLCTL = (SYS->PLCTL & (~SYS_PLCTL_PLSEL_Msk)) | SYS_PLCTL_PLSEL_PL0;
+    while(SYS->PLSTS & SYS_PLSTS_PLCBUSY_Msk);
+
+    /* Set Flash Access Cycle to 4 for safe */
+    FMC->CYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | (4);
+
+    /* Apply new Divider */
+    CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | u32ClkDiv;
+
+    /* Switch HCLK to new HCLK source */
+    CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | u32ClkSrc;
+
+    /* Update System Core Clock */
+    SystemCoreClockUpdate();
+
+    /* Set power level according to new HCLK source */
+    while(SYS->PLCTL & SYS_PLCTL_WRBUSY_Msk);
+    if((SystemCoreClock > FREQ_48MHZ) && SystemCoreClock <= FREQ_84MHZ)
+    {
+        SYS->PLCTL = (SYS->PLCTL & (~SYS_PLCTL_PLSEL_Msk)) | SYS_PLCTL_PLSEL_PL1;
+    }
+    else if((SystemCoreClock > FREQ_4MHZ) && SystemCoreClock <= FREQ_48MHZ)
+    {
+        SYS->PLCTL = (SYS->PLCTL & (~SYS_PLCTL_PLSEL_Msk)) | SYS_PLCTL_PLSEL_PL2;
+    }
+    if(SystemCoreClock <= FREQ_4MHZ)
+    {
+        SYS->PLCTL = (SYS->PLCTL & (~SYS_PLCTL_PLSEL_Msk)) | SYS_PLCTL_PLSEL_PL3;
+    }
+    while(SYS->PLSTS & SYS_PLSTS_PLCBUSY_Msk);
+
+    /* Set Flash Access Cycle */
+    if((SystemCoreClock >= FREQ_50MHZ) && SystemCoreClock < FREQ_75MHZ)
+    {
+        FMC->CYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | (3);
+    }
+    else if((SystemCoreClock >= FREQ_25MHZ) && SystemCoreClock < FREQ_50MHZ)
+    {
+        FMC->CYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | (2);
+    }
+    if(SystemCoreClock < FREQ_25MHZ)
+    {
+        FMC->CYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | (1);
+    }
+
+    /* Disable HIRC if HIRC is disabled before switching HCLK source */
+    if(u32HIRCSTB == 0UL)
+    {
+        CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
+    }
+}
+/**
+  * @brief      This function set selected module clock source and module clock divider
+  * @param[in]  u32ModuleIdx is module index.
+  * @param[in]  u32ClkSrc is module clock source.
+  * @param[in]  u32ClkDiv is module clock divider.
+  * @return     None
+  * @details    Valid parameter combinations listed in following table:
+  *
+  * |Module index        |Clock source                           |Divider                   |
+  * | :----------------  | :------------------------------------ | :----------------------- |
+  * |\ref SDH0_MODULE    |\ref CLK_CLKSEL0_SDH0SEL_HXT           |\ref CLK_CLKDIV0_SDH0(x)  |
+  * |\ref SDH0_MODULE    |\ref CLK_CLKSEL0_SDH0SEL_PLL           |\ref CLK_CLKDIV0_SDH0(x)  |
+  * |\ref SDH0_MODULE    |\ref CLK_CLKSEL0_SDH0SEL_HCLK          |\ref CLK_CLKDIV0_SDH0(x)  |
+  * |\ref SDH0_MODULE    |\ref CLK_CLKSEL0_SDH0SEL_HIRC          |\ref CLK_CLKDIV0_SDH0(x)  |
+  * |\ref WDT_MODULE     |\ref CLK_CLKSEL1_WDTSEL_LXT            | x                        |
+  * |\ref WDT_MODULE     |\ref CLK_CLKSEL1_WDTSEL_HCLK_DIV2048   | x                        |
+  * |\ref WDT_MODULE     |\ref CLK_CLKSEL1_WDTSEL_LIRC           | x                        |
+  * |\ref WWDT_MODULE    |\ref CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048  | x                        |
+  * |\ref WWDT_MODULE    |\ref CLK_CLKSEL1_WWDTSEL_LIRC          | x                        |
+  * |\ref LCD_MODULE     |\ref CLK_CLKSEL1_LCDSEL_LIRC           | x                        |
+  * |\ref LCD_MODULE     |\ref CLK_CLKSEL1_LCDSEL_LXT            | x                        |
+  * |\ref LCDCP_MODULE   |\ref CLK_CLKSEL1_LCDCPSEL_MIRC1P2M     | x                        |
+  * |\ref LCDCP_MODULE   |\ref CLK_CLKSEL1_LCDCPSEL_MIRC         | x                        |
+  * |\ref EWDT_MODULE    |\ref CLK_CLKSEL1_EWDTSEL_LXT           | x                        |
+  * |\ref EWDT_MODULE    |\ref CLK_CLKSEL1_EWDTSEL_HCLK_DIV2048  | x                        |
+  * |\ref EWDT_MODULE    |\ref CLK_CLKSEL1_EWDTSEL_LIRC          | x                        |
+  * |\ref EWWDT_MODULE   |\ref CLK_CLKSEL1_EWWDTSEL_HCLK_DIV2048 | x                        |
+  * |\ref EWWDT_MODULE   |\ref CLK_CLKSEL1_EWWDTSEL_LIRC         | x                        |
+  * |\ref EADC_MODULE    | x                                     |\ref CLK_CLKDIV0_EADC(x)  |
+  * |\ref TMR0_MODULE    |\ref CLK_CLKSEL1_TMR0SEL_HXT           | x                        |
+  * |\ref TMR0_MODULE    |\ref CLK_CLKSEL1_TMR0SEL_LXT           | x                        |
+  * |\ref TMR0_MODULE    |\ref CLK_CLKSEL1_TMR0SEL_PCLK0         | x                        |
+  * |\ref TMR0_MODULE    |\ref CLK_CLKSEL1_TMR0SEL_EXT_TRG       | x                        |
+  * |\ref TMR0_MODULE    |\ref CLK_CLKSEL1_TMR0SEL_LIRC          | x                        |
+  * |\ref TMR0_MODULE    |\ref CLK_CLKSEL1_TMR0SEL_HIRC          | x                        |
+  * |\ref TMR1_MODULE    |\ref CLK_CLKSEL1_TMR1SEL_HXT           | x                        |
+  * |\ref TMR1_MODULE    |\ref CLK_CLKSEL1_TMR1SEL_LXT           | x                        |
+  * |\ref TMR1_MODULE    |\ref CLK_CLKSEL1_TMR1SEL_PCLK0         | x                        |
+  * |\ref TMR1_MODULE    |\ref CLK_CLKSEL1_TMR1SEL_EXT_TRG       | x                        |
+  * |\ref TMR1_MODULE    |\ref CLK_CLKSEL1_TMR1SEL_LIRC          | x                        |
+  * |\ref TMR1_MODULE    |\ref CLK_CLKSEL1_TMR1SEL_HIRC          | x                        |
+  * |\ref TMR2_MODULE    |\ref CLK_CLKSEL1_TMR2SEL_HXT           | x                        |
+  * |\ref TMR2_MODULE    |\ref CLK_CLKSEL1_TMR2SEL_LXT           | x                        |
+  * |\ref TMR2_MODULE    |\ref CLK_CLKSEL1_TMR2SEL_PCLK1         | x                        |
+  * |\ref TMR2_MODULE    |\ref CLK_CLKSEL1_TMR2SEL_EXT_TRG       | x                        |
+  * |\ref TMR2_MODULE    |\ref CLK_CLKSEL1_TMR2SEL_LIRC          | x                        |
+  * |\ref TMR2_MODULE    |\ref CLK_CLKSEL1_TMR2SEL_HIRC          | x                        |
+  * |\ref TMR3_MODULE    |\ref CLK_CLKSEL1_TMR3SEL_HXT           | x                        |
+  * |\ref TMR3_MODULE    |\ref CLK_CLKSEL1_TMR3SEL_LXT           | x                        |
+  * |\ref TMR3_MODULE    |\ref CLK_CLKSEL1_TMR3SEL_PCLK1         | x                        |
+  * |\ref TMR3_MODULE    |\ref CLK_CLKSEL1_TMR3SEL_EXT_TRG       | x                        |
+  * |\ref TMR3_MODULE    |\ref CLK_CLKSEL1_TMR3SEL_LIRC          | x                        |
+  * |\ref TMR3_MODULE    |\ref CLK_CLKSEL1_TMR3SEL_HIRC          | x                        |
+  * |\ref TMR4_MODULE    |\ref CLK_CLKSEL3_TMR4SEL_HXT           | x                        |
+  * |\ref TMR4_MODULE    |\ref CLK_CLKSEL3_TMR4SEL_LXT           | x                        |
+  * |\ref TMR4_MODULE    |\ref CLK_CLKSEL3_TMR4SEL_PCLK0         | x                        |
+  * |\ref TMR4_MODULE    |\ref CLK_CLKSEL3_TMR4SEL_EXT_TRG       | x                        |
+  * |\ref TMR4_MODULE    |\ref CLK_CLKSEL3_TMR4SEL_MIRC          | x                        |
+  * |\ref TMR4_MODULE    |\ref CLK_CLKSEL3_TMR4SEL_LIRC          | x                        |
+  * |\ref TMR4_MODULE    |\ref CLK_CLKSEL3_TMR4SEL_HIRC          | x                        |
+  * |\ref TMR5_MODULE    |\ref CLK_CLKSEL3_TMR5SEL_HXT           | x                        |
+  * |\ref TMR5_MODULE    |\ref CLK_CLKSEL3_TMR5SEL_LXT           | x                        |
+  * |\ref TMR5_MODULE    |\ref CLK_CLKSEL3_TMR5SEL_PCLK0         | x                        |
+  * |\ref TMR5_MODULE    |\ref CLK_CLKSEL3_TMR5SEL_EXT_TRG       | x                        |
+  * |\ref TMR5_MODULE    |\ref CLK_CLKSEL3_TMR5SEL_MIRC          | x                        |
+  * |\ref TMR5_MODULE    |\ref CLK_CLKSEL3_TMR5SEL_LIRC          | x                        |
+  * |\ref TMR5_MODULE    |\ref CLK_CLKSEL3_TMR5SEL_HIRC          | x                        |
+  * |\ref UART0_MODULE   |\ref CLK_CLKSEL2_UART0SEL_HXT          |\ref CLK_CLKDIV0_UART0(x) |
+  * |\ref UART0_MODULE   |\ref CLK_CLKSEL2_UART0SEL_PLL          |\ref CLK_CLKDIV0_UART0(x) |
+  * |\ref UART0_MODULE   |\ref CLK_CLKSEL2_UART0SEL_LXT          |\ref CLK_CLKDIV0_UART0(x) |
+  * |\ref UART0_MODULE   |\ref CLK_CLKSEL2_UART0SEL_HIRC         |\ref CLK_CLKDIV0_UART0(x) |
+  * |\ref UART0_MODULE   |\ref CLK_CLKSEL2_UART0SEL_PCLK0        |\ref CLK_CLKDIV0_UART0(x) |
+  * |\ref UART1_MODULE   |\ref CLK_CLKSEL2_UART1SEL_HXT          |\ref CLK_CLKDIV0_UART1(x) |
+  * |\ref UART1_MODULE   |\ref CLK_CLKSEL2_UART1SEL_PLL          |\ref CLK_CLKDIV0_UART1(x) |
+  * |\ref UART1_MODULE   |\ref CLK_CLKSEL2_UART1SEL_LXT          |\ref CLK_CLKDIV0_UART1(x) |
+  * |\ref UART1_MODULE   |\ref CLK_CLKSEL2_UART1SEL_HIRC         |\ref CLK_CLKDIV0_UART1(x) |
+  * |\ref UART1_MODULE   |\ref CLK_CLKSEL2_UART1SEL_PCLK1        |\ref CLK_CLKDIV0_UART1(x) |
+  * |\ref UART2_MODULE   |\ref CLK_CLKSEL2_UART2SEL_HXT          |\ref CLK_CLKDIV4_UART2(x) |
+  * |\ref UART2_MODULE   |\ref CLK_CLKSEL2_UART2SEL_PLL          |\ref CLK_CLKDIV4_UART2(x) |
+  * |\ref UART2_MODULE   |\ref CLK_CLKSEL2_UART2SEL_LXT          |\ref CLK_CLKDIV4_UART2(x) |
+  * |\ref UART2_MODULE   |\ref CLK_CLKSEL2_UART2SEL_HIRC         |\ref CLK_CLKDIV4_UART2(x) |
+  * |\ref UART2_MODULE   |\ref CLK_CLKSEL2_UART2SEL_PCLK0        |\ref CLK_CLKDIV4_UART2(x) |
+  * |\ref UART3_MODULE   |\ref CLK_CLKSEL2_UART3SEL_HXT          |\ref CLK_CLKDIV4_UART3(x) |
+  * |\ref UART3_MODULE   |\ref CLK_CLKSEL2_UART3SEL_PLL          |\ref CLK_CLKDIV4_UART3(x) |
+  * |\ref UART3_MODULE   |\ref CLK_CLKSEL2_UART3SEL_LXT          |\ref CLK_CLKDIV4_UART3(x) |
+  * |\ref UART3_MODULE   |\ref CLK_CLKSEL2_UART3SEL_HIRC         |\ref CLK_CLKDIV4_UART3(x) |
+  * |\ref UART3_MODULE   |\ref CLK_CLKSEL2_UART3SEL_PCLK1        |\ref CLK_CLKDIV4_UART3(x) |
+  * |\ref UART4_MODULE   |\ref CLK_CLKSEL3_UART4SEL_HXT          |\ref CLK_CLKDIV4_UART4(x) |
+  * |\ref UART4_MODULE   |\ref CLK_CLKSEL3_UART4SEL_PLL          |\ref CLK_CLKDIV4_UART4(x) |
+  * |\ref UART4_MODULE   |\ref CLK_CLKSEL3_UART4SEL_LXT          |\ref CLK_CLKDIV4_UART4(x) |
+  * |\ref UART4_MODULE   |\ref CLK_CLKSEL3_UART4SEL_HIRC         |\ref CLK_CLKDIV4_UART4(x) |
+  * |\ref UART4_MODULE   |\ref CLK_CLKSEL3_UART4SEL_PCLK0        |\ref CLK_CLKDIV4_UART4(x) |
+  * |\ref UART5_MODULE   |\ref CLK_CLKSEL3_UART5SEL_HXT          |\ref CLK_CLKDIV4_UART5(x) |
+  * |\ref UART5_MODULE   |\ref CLK_CLKSEL3_UART5SEL_PLL          |\ref CLK_CLKDIV4_UART5(x) |
+  * |\ref UART5_MODULE   |\ref CLK_CLKSEL3_UART5SEL_LXT          |\ref CLK_CLKDIV4_UART5(x) |
+  * |\ref UART5_MODULE   |\ref CLK_CLKSEL3_UART5SEL_HIRC         |\ref CLK_CLKDIV4_UART5(x) |
+  * |\ref UART5_MODULE   |\ref CLK_CLKSEL3_UART5SEL_PCLK1        |\ref CLK_CLKDIV4_UART5(x) |
+  * |\ref CLKO_MODULE    |\ref CLK_CLKSEL1_CLKOSEL_HXT           | x                        |
+  * |\ref CLKO_MODULE    |\ref CLK_CLKSEL1_CLKOSEL_LXT           | x                        |
+  * |\ref CLKO_MODULE    |\ref CLK_CLKSEL1_CLKOSEL_HCLK          | x                        |
+  * |\ref CLKO_MODULE    |\ref CLK_CLKSEL1_CLKOSEL_HIRC          | x                        |
+  * |\ref RTC_MODULE     |\ref RTC_LXTCTL_RTCCKSEL_LXT           | x                        |
+  * |\ref RTC_MODULE     |\ref RTC_LXTCTL_RTCCKSEL_LIRC          | x                        |
+  * |\ref I2S0_MODULE    |\ref CLK_CLKSEL3_I2S0SEL_HXT           | x                        |
+  * |\ref I2S0_MODULE    |\ref CLK_CLKSEL3_I2S0SEL_PLL           | x                        |
+  * |\ref I2S0_MODULE    |\ref CLK_CLKSEL3_I2S0SEL_PCLK0         | x                        |
+  * |\ref I2S0_MODULE    |\ref CLK_CLKSEL3_I2S0SEL_HIRC          | x                        |
+  * |\ref QSPI0_MODULE   |\ref CLK_CLKSEL2_QSPI0SEL_HXT          | x                        |
+  * |\ref QSPI0_MODULE   |\ref CLK_CLKSEL2_QSPI0SEL_PLL          | x                        |
+  * |\ref QSPI0_MODULE   |\ref CLK_CLKSEL2_QSPI0SEL_PCLK0        | x                        |
+  * |\ref QSPI0_MODULE   |\ref CLK_CLKSEL2_QSPI0SEL_HIRC         | x                        |
+  * |\ref SPI0_MODULE    |\ref CLK_CLKSEL2_SPI0SEL_HXT           | x                        |
+  * |\ref SPI0_MODULE    |\ref CLK_CLKSEL2_SPI0SEL_PLL           | x                        |
+  * |\ref SPI0_MODULE    |\ref CLK_CLKSEL2_SPI0SEL_PCLK1         | x                        |
+  * |\ref SPI0_MODULE    |\ref CLK_CLKSEL2_SPI0SEL_HIRC          | x                        |
+  * |\ref SPI1_MODULE    |\ref CLK_CLKSEL2_SPI1SEL_HXT           | x                        |
+  * |\ref SPI1_MODULE    |\ref CLK_CLKSEL2_SPI1SEL_PLL           | x                        |
+  * |\ref SPI1_MODULE    |\ref CLK_CLKSEL2_SPI1SEL_PCLK0         | x                        |
+  * |\ref SPI1_MODULE    |\ref CLK_CLKSEL2_SPI1SEL_HIRC          | x                        |
+  * |\ref SPI2_MODULE    |\ref CLK_CLKSEL2_SPI2SEL_HXT           | x                        |
+  * |\ref SPI2_MODULE    |\ref CLK_CLKSEL2_SPI2SEL_PLL           | x                        |
+  * |\ref SPI2_MODULE    |\ref CLK_CLKSEL2_SPI2SEL_PCLK1         | x                        |
+  * |\ref SPI2_MODULE    |\ref CLK_CLKSEL2_SPI2SEL_HIRC          | x                        |
+  * |\ref SPI3_MODULE    |\ref CLK_CLKSEL2_SPI3SEL_HXT           | x                        |
+  * |\ref SPI3_MODULE    |\ref CLK_CLKSEL2_SPI3SEL_PLL           | x                        |
+  * |\ref SPI3_MODULE    |\ref CLK_CLKSEL2_SPI3SEL_PCLK0         | x                        |
+  * |\ref SPI3_MODULE    |\ref CLK_CLKSEL2_SPI3SEL_HIRC          | x                        |
+  * |\ref SC0_MODULE     |\ref CLK_CLKSEL3_SC0SEL_HXT            |\ref CLK_CLKDIV1_SC0(x)   |
+  * |\ref SC0_MODULE     |\ref CLK_CLKSEL3_SC0SEL_PLL            |\ref CLK_CLKDIV1_SC0(x)   |
+  * |\ref SC0_MODULE     |\ref CLK_CLKSEL3_SC0SEL_PCLK0          |\ref CLK_CLKDIV1_SC0(x)   |
+  * |\ref SC0_MODULE     |\ref CLK_CLKSEL3_SC0SEL_HIRC           |\ref CLK_CLKDIV1_SC0(x)   |
+  * |\ref SC1_MODULE     |\ref CLK_CLKSEL3_SC1SEL_HXT            |\ref CLK_CLKDIV1_SC1(x)   |
+  * |\ref SC1_MODULE     |\ref CLK_CLKSEL3_SC1SEL_PLL            |\ref CLK_CLKDIV1_SC1(x)   |
+  * |\ref SC1_MODULE     |\ref CLK_CLKSEL3_SC1SEL_PCLK1          |\ref CLK_CLKDIV1_SC1(x)   |
+  * |\ref SC1_MODULE     |\ref CLK_CLKSEL3_SC1SEL_HIRC           |\ref CLK_CLKDIV1_SC1(x)   |
+  * |\ref SC2_MODULE     |\ref CLK_CLKSEL3_SC2SEL_HXT            |\ref CLK_CLKDIV1_SC2(x)   |
+  * |\ref SC2_MODULE     |\ref CLK_CLKSEL3_SC2SEL_PLL            |\ref CLK_CLKDIV1_SC2(x)   |
+  * |\ref SC2_MODULE     |\ref CLK_CLKSEL3_SC2SEL_PCLK0          |\ref CLK_CLKDIV1_SC2(x)   |
+  * |\ref SC2_MODULE     |\ref CLK_CLKSEL3_SC2SEL_HIRC           |\ref CLK_CLKDIV1_SC2(x)   |
+  * |\ref USBH_MODULE    |\ref CLK_CLKSEL0_USBSEL_HIRC48         |\ref CLK_CLKDIV0_USB(x)   |
+  * |\ref USBH_MODULE    |\ref CLK_CLKSEL0_USBSEL_PLL            |\ref CLK_CLKDIV0_USB(x)   |
+  * |\ref OTG_MODULE     |\ref CLK_CLKSEL0_USBSEL_HIRC48         |\ref CLK_CLKDIV0_USB(x)   |
+  * |\ref OTG_MODULE     |\ref CLK_CLKSEL0_USBSEL_PLL            |\ref CLK_CLKDIV0_USB(x)   |
+  * |\ref USBD_MODULE    |\ref CLK_CLKSEL0_USBSEL_HIRC48         |\ref CLK_CLKDIV0_USB(x)   |
+  * |\ref USBD_MODULE    |\ref CLK_CLKSEL0_USBSEL_PLL            |\ref CLK_CLKDIV0_USB(x)   |
+  */
+void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
+{
+    uint32_t u32Sel = 0UL, u32Div = 0UL;
+    uint32_t au32SelTbl[4] = {0x0UL, 0x4UL, 0x8UL, 0xCUL};
+    uint32_t au32DivTbl[4] = {0x0UL, 0x4UL, 0x8UL, 0x10UL};
+    uint32_t u32RTCCKEN = CLK->APBCLK0 & CLK_APBCLK0_RTCCKEN_Msk;
+
+    if(u32ModuleIdx == RTC_MODULE)      /* RTC clock source configuration */
+    {
+        if(u32RTCCKEN == 0UL)
+        {
+            CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk; /* Enable RTC clock to get LXT clock source */
+        }
+
+        /* Select RTC clock source */
+        RTC->LXTCTL = (RTC->LXTCTL & (~RTC_LXTCTL_RTCCKSEL_Msk)) | (u32ClkSrc);
+
+        if(u32RTCCKEN == 0UL)
+        {
+            CLK->APBCLK0 &= (~CLK_APBCLK0_RTCCKEN_Msk); /* Disable RTC clock if it is disabled before */
+        }
+
+    }
+    else /* Others clock source configuration */
+    {
+        if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk)
+        {
+            /* Get clock divider control register address */
+            u32Div = (uint32_t)&CLK->CLKDIV0 + (au32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]);
+            /* Apply new divider */
+            M32(u32Div) = (M32(u32Div) & (~(MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx)))) | u32ClkDiv;
+        }
+
+        if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk)
+        {
+            /* Get clock select control register address */
+            u32Sel = (uint32_t)&CLK->CLKSEL0 + (au32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]);
+            /* Set new clock selection setting */
+            M32(u32Sel) = (M32(u32Sel) & (~(MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx)))) | u32ClkSrc;
+        }
+    }
+}
+
+/**
+  * @brief      Set SysTick clock source
+  * @param[in]  u32ClkSrc is module clock source. Including:
+  *             - \ref CLK_CLKSEL0_STCLKSEL_HXT
+  *             - \ref CLK_CLKSEL0_STCLKSEL_LXT
+  *             - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2
+  *             - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
+  *             - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
+  * @return     None
+  * @details    This function set SysTick clock source. \n
+  *             The register write-protection function should be disabled before using this function.
+  */
+void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
+{
+    CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
+}
+
+/**
+  * @brief      Enable clock source
+  * @param[in]  u32ClkMask is clock source mask. Including :
+  *             - \ref CLK_PWRCTL_HXTEN_Msk
+  *             - \ref CLK_PWRCTL_LXTEN_Msk
+  *             - \ref CLK_PWRCTL_HIRCEN_Msk
+  *             - \ref CLK_PWRCTL_LIRCEN_Msk
+  *             - \ref CLK_PWRCTL_HIRC48EN_Msk
+  *             - \ref CLK_PWRCTL_MIRC1P2MEN_Msk
+  *             - \ref CLK_PWRCTL_MIRCEN_Msk
+  * @return     None
+  * @details    This function enable clock source. \n
+  *             The register write-protection function should be disabled before using this function.
+  */
+void CLK_EnableXtalRC(uint32_t u32ClkMask)
+{
+    CLK->PWRCTL |= u32ClkMask;
+}
+
+/**
+  * @brief      Disable clock source
+  * @param[in]  u32ClkMask is clock source mask. Including :
+  *             - \ref CLK_PWRCTL_HXTEN_Msk
+  *             - \ref CLK_PWRCTL_LXTEN_Msk
+  *             - \ref CLK_PWRCTL_HIRCEN_Msk
+  *             - \ref CLK_PWRCTL_LIRCEN_Msk
+  *             - \ref CLK_PWRCTL_HIRC48EN_Msk
+  *             - \ref CLK_PWRCTL_MIRC1P2MEN_Msk
+  *             - \ref CLK_PWRCTL_MIRCEN_Msk
+  * @return     None
+  * @details    This function disable clock source. \n
+  *             The register write-protection function should be disabled before using this function.
+  */
+void CLK_DisableXtalRC(uint32_t u32ClkMask)
+{
+    CLK->PWRCTL &= ~u32ClkMask;
+}
+
+/**
+  * @brief      Enable module clock
+  * @param[in]  u32ModuleIdx is module index. Including :
+  *             - \ref PDMA0_MODULE
+  *             - \ref PDMA1_MODULE
+  *             - \ref ISP_MODULE
+  *             - \ref EBI_MODULE
+  *             - \ref SDH0_MODULE
+  *             - \ref CRC_MODULE
+  *             - \ref CRPT_MODULE
+  *             - \ref KS_MODULE
+  *             - \ref TRACE_MODULE
+  *             - \ref USBH_MODULE
+  *             - \ref SRAM0_MODULE
+  *             - \ref SRAM1_MODULE
+  *             - \ref SRAM2_MODULE
+  *             - \ref GPA_MODULE
+  *             - \ref GPB_MODULE
+  *             - \ref GPC_MODULE
+  *             - \ref GPD_MODULE
+  *             - \ref GPE_MODULE
+  *             - \ref GPF_MODULE
+  *             - \ref GPG_MODULE
+  *             - \ref GPH_MODULE
+  *             - \ref WDT_MODULE
+  *             - \ref WWDT_MODULE
+  *             - \ref EWDT_MODULE
+  *             - \ref EWWDT_MODULE
+  *             - \ref RTC_MODULE
+  *             - \ref TMR0_MODULE
+  *             - \ref TMR1_MODULE
+  *             - \ref TMR2_MODULE
+  *             - \ref TMR3_MODULE
+  *             - \ref TMR4_MODULE
+  *             - \ref TMR5_MODULE
+  *             - \ref CLKO_MODULE
+  *             - \ref ACMP01_MODULE
+  *             - \ref I2C0_MODULE
+  *             - \ref I2C1_MODULE
+  *             - \ref I2C2_MODULE
+  *             - \ref QSPI0_MODULE
+  *             - \ref SPI0_MODULE
+  *             - \ref SPI1_MODULE
+  *             - \ref SPI2_MODULE
+  *             - \ref SPI3_MODULE
+  *             - \ref UART0_MODULE
+  *             - \ref UART1_MODULE
+  *             - \ref UART2_MODULE
+  *             - \ref UART3_MODULE
+  *             - \ref UART4_MODULE
+  *             - \ref UART5_MODULE
+  *             - \ref TAMPER_MODULE
+  *             - \ref CAN0_MODULE
+  *             - \ref OTG_MODULE
+  *             - \ref USBD_MODULE
+  *             - \ref EADC_MODULE
+  *             - \ref I2S0_MODULE
+  *             - \ref SC0_MODULE
+  *             - \ref SC1_MODULE
+  *             - \ref SC2_MODULE
+  *             - \ref USCI0_MODULE
+  *             - \ref USCI1_MODULE
+  *             - \ref DAC_MODULE
+  *             - \ref EPWM0_MODULE
+  *             - \ref EPWM1_MODULE
+  *             - \ref BPWM0_MODULE
+  *             - \ref BPWM1_MODULE
+  *             - \ref QEI0_MODULE
+  *             - \ref QEI1_MODULE
+  *             - \ref QEI0_MODULE
+  *             - \ref LCD_MODULE
+  *             - \ref LCDCP_MODULE
+  *             - \ref TRNG_MODULE
+  *             - \ref ECAP0_MODULE
+  *             - \ref ECAP1_MODULE
+  * @return     None
+  * @details    This function is used to enable module clock.
+  */
+void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
+{
+    uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL;
+
+    u32TmpVal = (1UL << MODULE_IP_EN_Pos(u32ModuleIdx));
+    u32TmpAddr = (uint32_t)&CLK->AHBCLK;
+    u32TmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL));
+
+    *(volatile uint32_t *)u32TmpAddr |= u32TmpVal;
+}
+
+/**
+  * @brief      Disable module clock
+  * @param[in]  u32ModuleIdx is module index
+  *             - \ref PDMA0_MODULE
+  *             - \ref PDMA1_MODULE
+  *             - \ref ISP_MODULE
+  *             - \ref EBI_MODULE
+  *             - \ref SDH0_MODULE
+  *             - \ref CRC_MODULE
+  *             - \ref CRPT_MODULE
+  *             - \ref KS_MODULE
+  *             - \ref TRACE_MODULE
+  *             - \ref USBH_MODULE
+  *             - \ref SRAM0_MODULE
+  *             - \ref SRAM1_MODULE
+  *             - \ref SRAM2_MODULE
+  *             - \ref GPA_MODULE
+  *             - \ref GPB_MODULE
+  *             - \ref GPC_MODULE
+  *             - \ref GPD_MODULE
+  *             - \ref GPE_MODULE
+  *             - \ref GPF_MODULE
+  *             - \ref GPG_MODULE
+  *             - \ref GPH_MODULE
+  *             - \ref WDT_MODULE
+  *             - \ref WWDT_MODULE
+  *             - \ref EWDT_MODULE
+  *             - \ref EWWDT_MODULE
+  *             - \ref RTC_MODULE
+  *             - \ref TMR0_MODULE
+  *             - \ref TMR1_MODULE
+  *             - \ref TMR2_MODULE
+  *             - \ref TMR3_MODULE
+  *             - \ref TMR4_MODULE
+  *             - \ref TMR5_MODULE
+  *             - \ref CLKO_MODULE
+  *             - \ref ACMP01_MODULE
+  *             - \ref I2C0_MODULE
+  *             - \ref I2C1_MODULE
+  *             - \ref I2C2_MODULE
+  *             - \ref QSPI0_MODULE
+  *             - \ref SPI0_MODULE
+  *             - \ref SPI1_MODULE
+  *             - \ref SPI2_MODULE
+  *             - \ref SPI3_MODULE
+  *             - \ref UART0_MODULE
+  *             - \ref UART1_MODULE
+  *             - \ref UART2_MODULE
+  *             - \ref UART3_MODULE
+  *             - \ref UART4_MODULE
+  *             - \ref UART5_MODULE
+  *             - \ref TAMPER_MODULE
+  *             - \ref CAN0_MODULE
+  *             - \ref OTG_MODULE
+  *             - \ref USBD_MODULE
+  *             - \ref EADC_MODULE
+  *             - \ref I2S0_MODULE
+  *             - \ref SC0_MODULE
+  *             - \ref SC1_MODULE
+  *             - \ref SC2_MODULE
+  *             - \ref USCI0_MODULE
+  *             - \ref USCI1_MODULE
+  *             - \ref DAC_MODULE
+  *             - \ref EPWM0_MODULE
+  *             - \ref EPWM1_MODULE
+  *             - \ref BPWM0_MODULE
+  *             - \ref BPWM1_MODULE
+  *             - \ref QEI0_MODULE
+  *             - \ref QEI1_MODULE
+  *             - \ref QEI0_MODULE
+  *             - \ref LCD_MODULE
+  *             - \ref LCDCP_MODULE
+  *             - \ref TRNG_MODULE
+  *             - \ref ECAP0_MODULE
+  *             - \ref ECAP1_MODULE
+  * @return     None
+  * @details    This function is used to disable module clock.
+  */
+void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
+{
+    uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL;
+
+    u32TmpVal = ~(1UL << MODULE_IP_EN_Pos(u32ModuleIdx));
+    u32TmpAddr = (uint32_t)&CLK->AHBCLK;
+    u32TmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL));
+
+    *(uint32_t *)u32TmpAddr &= u32TmpVal;
+}
+
+
+/**
+  * @brief      Set PLL frequency
+  * @param[in]  u32PllClkSrc is PLL clock source. Including :
+  *             - \ref CLK_PLLCTL_PLLSRC_HXT
+  *             - \ref CLK_PLLCTL_PLLSRC_HIRC
+  * @param[in]  u32PllFreq is PLL frequency. The range of u32PllFreq is 24 MHz ~ 200 MHz.
+  * @return     PLL frequency
+  * @details    This function is used to configure PLLCTL register to set specified PLL frequency. \n
+  *             The register write-protection function should be disabled before using this function.
+  */
+uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
+{
+    uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32PllClk;
+    uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR;
+
+    /* Disable PLL first to avoid unstable when setting PLL */
+    CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;
+
+    /* PLL source clock is from HXT */
+    if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT)
+    {
+        /* Enable HXT clock */
+        CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk;
+
+        /* Wait for HXT clock ready */
+        CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
+
+        /* Select PLL source clock from HXT */
+        u32PllSrcClk = __HXT;
+    }
+
+    /* PLL source clock is from HIRC */
+    else
+    {
+        /* Enable HIRC clock */
+        CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
+
+        /* Wait for HIRC clock ready */
+        CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
+
+        /* Select PLL source clock from HIRC */
+        u32PllSrcClk = __HIRC;
+    }
+
+    /* Check PLL frequency range */
+    /* Constraint 1: 24MHz < FOUT < 200MHz */
+    if((u32PllFreq <= FREQ_200MHZ) && (u32PllFreq >= FREQ_24MHZ))
+    {
+
+        /* Select "NO" according to request frequency */
+        if((u32PllFreq < FREQ_48MHZ) && (u32PllFreq >= FREQ_24MHZ))
+        {
+            u32NO = 3UL;
+            u32PllFreq = u32PllFreq << 2;
+        }
+        else if((u32PllFreq < FREQ_96MHZ) && (u32PllFreq >= FREQ_48MHZ))
+        {
+            u32NO = 1UL;
+            u32PllFreq = u32PllFreq << 1;
+        }
+        else
+        {
+            u32NO = 0UL;
+        }
+
+        /* u32NR start from 3 to avoid calculation overflow */
+        u32NR = 3UL;
+
+        /* Find best solution */
+        u32Min = (uint32_t) - 1;    /* initial u32Min to max value of uint32_t (0xFFFFFFFF) */
+        u32MinNR = 0UL;
+        u32MinNF = 0UL;
+
+        for(; u32NR <= 32UL; u32NR++)   /* max NR = 32 since NR = INDIV+1 and INDIV = 0~31 */
+        {
+            u32Tmp = u32PllSrcClk / u32NR;                      /* FREF = FIN/NR */
+            if((u32Tmp >= FREQ_2MHZ) && (u32Tmp <= FREQ_8MHZ))  /* Constraint 2: 2MHz < FREF < 8MHz. */
+            {
+                for(u32NF = 2UL; u32NF <= 513UL; u32NF++)       /* NF = 2~513 since NF = FBDIV+2 and FBDIV = 0~511 */
+                {
+                    u32Tmp2 = (u32Tmp * u32NF) << 1;                            /* FVCO = FREF*2*NF */
+                    if((u32Tmp2 >= FREQ_96MHZ) && (u32Tmp2 <= FREQ_200MHZ))     /* Constraint 3: 96MHz < FVCO < 200MHz */
+                    {
+                        u32Tmp3 = (u32Tmp2 > u32PllFreq) ? u32Tmp2 - u32PllFreq : u32PllFreq - u32Tmp2;
+                        if(u32Tmp3 < u32Min)
+                        {
+                            u32Min = u32Tmp3;
+                            u32MinNR = u32NR;
+                            u32MinNF = u32NF;
+
+                            /* Break when get good results */
+                            if(u32Min == 0UL)
+                            {
+                                break;
+                            }
+                        }
+                    }
+                }
+            }
+        }
+
+        /* Enable and apply new PLL setting. */
+        CLK->PLLCTL = u32PllClkSrc |
+                      (u32NO << CLK_PLLCTL_OUTDIV_Pos) |
+                      ((u32MinNR - 1UL) << CLK_PLLCTL_INDIV_Pos) |
+                      ((u32MinNF - 2UL) << CLK_PLLCTL_FBDIV_Pos);
+
+        /* Actual PLL output clock frequency. FOUT = (FIN/NR)*2*NF*(1/NO) */
+        u32PllClk = u32PllSrcClk / ((u32NO + 1UL) * u32MinNR) * (u32MinNF << 1);
+
+    }
+    else
+    {
+        /* Apply default PLL setting and return */
+        CLK->PLLCTL = u32PllClkSrc | CLK_PLLCTL_48MHz_HXT;
+
+        /* Actual PLL output clock frequency */
+        u32PllClk = FREQ_48MHZ;
+    }
+
+    /* Wait for PLL clock stable */
+    CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
+
+    /* Return actual PLL output clock frequency */
+    return u32PllClk;
+}
+
+/**
+  * @brief      Disable PLL
+  * @param      None
+  * @return     None
+  * @details    This function set PLL in Power-down mode. \n
+  *             The register write-protection function should be disabled before using this function.
+  */
+void CLK_DisablePLL(void)
+{
+    CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;
+}
+
+/**
+  * @brief      This function check selected clock source status
+  * @param[in]  u32ClkMask is selected clock source. Including :
+  *             - \ref CLK_STATUS_HXTSTB_Msk
+  *             - \ref CLK_STATUS_LXTSTB_Msk
+  *             - \ref CLK_STATUS_HIRCSTB_Msk
+  *             - \ref CLK_STATUS_LIRCSTB_Msk
+  *             - \ref CLK_STATUS_PLLSTB_Msk
+  *             - \ref CLK_STATUS_HIRC48STB_Msk
+  *             - \ref CLK_STATUS_EXTLXTSTB_Msk
+  *             - \ref CLK_STATUS_LIRC32STB_Msk
+  *             - \ref CLK_STATUS_MIRCSTB_Msk
+  * @retval     0  clock is not stable
+  * @retval     1  clock is stable
+  * @details    To wait for clock ready by specified clock source stable flag or timeout (~500ms)
+  */
+uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
+{
+    int32_t i32TimeOutCnt = 2400000;
+    uint32_t u32Ret = 1U;
+
+    while((CLK->STATUS & u32ClkMask) != u32ClkMask)
+    {
+        if(i32TimeOutCnt-- <= 0)
+        {
+            u32Ret = 0U;
+            break;
+        }
+    }
+    return u32Ret;
+}
+
+/**
+  * @brief      Enable System Tick counter
+  * @param[in]  u32ClkSrc is System Tick clock source. Including:
+  *             - \ref CLK_CLKSEL0_STCLKSEL_HXT
+  *             - \ref CLK_CLKSEL0_STCLKSEL_LXT
+  *             - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2
+  *             - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
+  *             - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
+  *             - \ref CLK_CLKSEL0_STCLKSEL_HCLK
+  * @param[in]  u32Count is System Tick reload value. It could be 0~0xFFFFFF.
+  * @return     None
+  * @details    This function set System Tick clock source, reload value, enable System Tick counter and interrupt. \n
+  *             The register write-protection function should be disabled before using this function.
+  */
+void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
+{
+    /* Set System Tick counter disabled */
+    SysTick->CTRL = 0UL;
+
+    /* Set System Tick clock source */
+    if(u32ClkSrc == CLK_CLKSEL0_STCLKSEL_HCLK)
+    {
+        SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
+    }
+    else
+    {
+        CLK->AHBCLK |= CLK_AHBCLK_EXSTCKEN_Msk;
+        CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
+    }
+
+    /* Set System Tick reload value */
+    SysTick->LOAD = u32Count;
+
+    /* Clear System Tick current value and counter flag */
+    SysTick->VAL = 0UL;
+
+    /* Set System Tick interrupt enabled and counter enabled */
+    SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk;
+}
+
+/**
+  * @brief      Disable System Tick counter
+  * @param      None
+  * @return     None
+  * @details    This function disable System Tick counter.
+  */
+void CLK_DisableSysTick(void)
+{
+    /* Set System Tick counter disabled */
+    SysTick->CTRL = 0UL;
+}
+
+/**
+  * @brief      Power-down mode selected
+  * @param[in]  u32PDMode is power down mode index. Including :
+  *             - \ref CLK_PMUCTL_PDMSEL_PD
+  *             - \ref CLK_PMUCTL_PDMSEL_LLPD
+  *             - \ref CLK_PMUCTL_PDMSEL_FWPD
+  *             - \ref CLK_PMUCTL_PDMSEL_ULLPD
+  *             - \ref CLK_PMUCTL_PDMSEL_SPD
+  *             - \ref CLK_PMUCTL_PDMSEL_DPD
+  * @return     None
+  * @details    This function is used to set power-down mode.
+  */
+void CLK_SetPowerDownMode(uint32_t u32PDMode)
+{
+    while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk);
+    CLK->PMUCTL = (CLK->PMUCTL & (~CLK_PMUCTL_PDMSEL_Msk)) | (u32PDMode);
+}
+
+/**
+ * @brief       Set Wake-up pin trigger type at Deep Power down mode
+ * @param[in]   u32TriggerType Wake-up pin trigger type
+ *              - \ref CLK_DPDWKPIN_RISING
+ *              - \ref CLK_DPDWKPIN_FALLING
+ *              - \ref CLK_DPDWKPIN_BOTHEDGE
+ *              - \ref CLK_DPDWKPIN1_RISING
+ *              - \ref CLK_DPDWKPIN1_FALLING
+ *              - \ref CLK_DPDWKPIN1_BOTHEDGE
+ *              - \ref CLK_DPDWKPIN2_RISING
+ *              - \ref CLK_DPDWKPIN2_FALLING
+ *              - \ref CLK_DPDWKPIN2_BOTHEDGE
+ *              - \ref CLK_DPDWKPIN3_RISING
+ *              - \ref CLK_DPDWKPIN3_FALLING
+ *              - \ref CLK_DPDWKPIN3_BOTHEDGE
+ *              - \ref CLK_DPDWKPIN4_RISING
+ *              - \ref CLK_DPDWKPIN4_FALLING
+ *              - \ref CLK_DPDWKPIN4_BOTHEDGE
+ * @return      None
+ * @details     This function is used to enable Wake-up pin trigger type.
+ */
+
+void CLK_EnableDPDWKPin(uint32_t u32TriggerType)
+{
+    uint32_t u32Pin1, u32Pin2, u32Pin3, u32Pin4;
+
+    u32Pin1 = (((u32TriggerType) & 0x03UL) >> CLK_PMUCTL_WKPINEN1_Pos);
+    u32Pin2 = (((u32TriggerType) & 0x03UL) >> CLK_PMUCTL_WKPINEN2_Pos);
+    u32Pin3 = (((u32TriggerType) & 0x03UL) >> CLK_PMUCTL_WKPINEN3_Pos);
+    u32Pin4 = (((u32TriggerType) & 0x03UL) >> CLK_PMUCTL_WKPINEN4_Pos);
+
+    while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk);
+
+    if(u32Pin1)
+    {
+        CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN1_Msk)) | u32TriggerType;
+    }
+    else if(u32Pin2)
+    {
+        CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN2_Msk)) | u32TriggerType;
+    }
+    else if(u32Pin3)
+    {
+        CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN3_Msk)) | u32TriggerType;
+    }
+    else if(u32Pin4)
+    {
+        CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN4_Msk)) | u32TriggerType;
+    }
+    else
+    {
+        CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN_Msk)) | u32TriggerType;
+    }
+}
+
+/**
+ * @brief       Get power manager wake up source
+ * @param[in]   None
+ * @return      None
+ * @details     This function get power manager wake up source.
+ */
+
+uint32_t CLK_GetPMUWKSrc(void)
+{
+    return (CLK->PMUSTS);
+}
+
+/**
+ * @brief       Set specified GPIO as wake up source at Standby Power-down mode
+ * @param[in]   u32Port GPIO port. It could be 0~3.
+ * @param[in]   u32Pin  The pin of specified GPIO port. It could be 0 ~ 15.
+ * @param[in]   u32TriggerType Wake-up pin trigger type
+ *              - \ref CLK_SPDWKPIN_RISING
+ *              - \ref CLK_SPDWKPIN_FALLING
+ * @param[in]   u32DebounceEn Standby Power-down mode wake-up pin de-bounce function
+ *              - \ref CLK_SPDWKPIN_DEBOUNCEEN
+ *              - \ref CLK_SPDWKPIN_DEBOUNCEDIS
+ * @return      None
+ * @details     This function is used to set specified GPIO as wake up source at Standby Power-down mode.
+ */
+
+void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn)
+{
+    uint32_t u32TmpAddr = 0UL;
+    uint32_t u32TmpVal = 0UL;
+
+    /* GPx Stand-by Power-down Wake-up Pin Select */
+    u32TmpAddr = (uint32_t)&CLK->PASWKCTL;
+    u32TmpAddr += (0x4UL * u32Port);
+
+    u32TmpVal = inpw((uint32_t *)u32TmpAddr);
+    u32TmpVal = (u32TmpVal & ~(CLK_PASWKCTL_WKPSEL_Msk | CLK_PASWKCTL_PRWKEN_Msk | CLK_PASWKCTL_PFWKEN_Msk | CLK_PASWKCTL_DBEN_Msk | CLK_PASWKCTL_WKEN_Msk)) |
+                (u32Pin << CLK_PASWKCTL_WKPSEL_Pos) | u32TriggerType | u32DebounceEn | CLK_SPDWKPIN_ENABLE;
+    outpw((uint32_t *)u32TmpAddr, u32TmpVal);
+}
+
+/**
+  * @brief      Get PLL clock frequency
+  * @param      None
+  * @return     PLL frequency
+  * @details    This function get PLL frequency. The frequency unit is Hz.
+  */
+
+__NONSECURE_ENTRY_WEAK
+uint32_t CLK_GetPLLClockFreq(void)
+{
+    uint32_t u32PllFreq = 0UL, u32PllReg;
+    uint32_t u32FIN, u32NF, u32NR, u32NO;
+    uint8_t au8NoTbl[4] = {1U, 2U, 2U, 4U};
+
+    u32PllReg = CLK->PLLCTL;
+
+    if(u32PllReg & CLK_PLLCTL_PD_Msk)
+    {
+        u32PllFreq = 0UL;       /* PLL is in power down mode or fix low */
+    }
+    else                        /* PLL is in normal mode */
+    {
+        /* PLL source clock */
+        if(u32PllReg & CLK_PLLCTL_PLLSRC_Msk)
+        {
+            u32FIN = __HIRC;    /* PLL source clock from HIRC */
+        }
+        else
+        {
+            u32FIN = __HXT;     /* PLL source clock from HXT */
+        }
+
+        /* Calculate PLL frequency */
+        if(u32PllReg & CLK_PLLCTL_BP_Msk)
+        {
+            u32PllFreq = u32FIN;  /* PLL is in bypass mode */
+        }
+        else
+        {
+            /* PLL is output enabled in normal work mode */
+            u32NO = au8NoTbl[((u32PllReg & CLK_PLLCTL_OUTDIV_Msk) >> CLK_PLLCTL_OUTDIV_Pos)];
+            u32NF = ((u32PllReg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2UL;
+            u32NR = ((u32PllReg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos) + 1UL;
+
+            /* u32FIN is shifted 2 bits to avoid overflow */
+            u32PllFreq = (((u32FIN >> 2) * (u32NF << 1)) / (u32NR * u32NO) << 2);
+        }
+    }
+
+    return u32PllFreq;
+}
+
+/**
+  * @brief      Get selected module clock source
+  * @param[in]  u32ModuleIdx is module index.
+  *             - \ref SDH0_MODULE
+  *             - \ref USBH_MODULE
+  *             - \ref WDT_MODULE
+  *             - \ref WWDT_MODULE
+  *             - \ref EWDT_MODULE
+  *             - \ref EWWDT_MODULE
+  *             - \ref LCD_MODULE
+  *             - \ref LCDCP_MODULE
+  *             - \ref RTC_MODULE
+  *             - \ref TMR0_MODULE
+  *             - \ref TMR1_MODULE
+  *             - \ref TMR2_MODULE
+  *             - \ref TMR3_MODULE
+  *             - \ref TMR4_MODULE
+  *             - \ref TMR5_MODULE
+  *             - \ref CLKO_MODULE
+  *             - \ref QSPI0_MODULE
+  *             - \ref SPI0_MODULE
+  *             - \ref SPI1_MODULE
+  *             - \ref SPI2_MODULE
+  *             - \ref SPI3_MODULE
+  *             - \ref UART0_MODULE
+  *             - \ref UART1_MODULE
+  *             - \ref UART2_MODULE
+  *             - \ref UART3_MODULE
+  *             - \ref UART4_MODULE
+  *             - \ref UART5_MODULE
+  *             - \ref OTG_MODULE
+  *             - \ref USBD_MODULE
+  *             - \ref I2S0_MODULE
+  *             - \ref SC0_MODULE
+  *             - \ref SC1_MODULE
+  *             - \ref SC2_MODULE
+  *             - \ref EPWM0_MODULE
+  *             - \ref EPWM1_MODULE
+  *             - \ref BPWM0_MODULE
+  *             - \ref BPWM1_MODULE
+  * @return     Selected module clock source setting
+  * @details    This function get selected module clock source.
+  */
+
+__NONSECURE_ENTRY_WEAK
+uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx)
+{
+    uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL;
+    uint32_t au32SelTbl[4] = {0x0UL, 0x4UL, 0x8UL, 0xCUL};
+    uint32_t u32RTCCKEN = CLK->APBCLK0 & CLK_APBCLK0_RTCCKEN_Msk;
+
+    /* Get clock source selection setting */
+    if(u32ModuleIdx == RTC_MODULE)
+    {
+        if(u32RTCCKEN == 0UL)
+        {
+            CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk; /* Enable RTC clock to get LXT clock source */
+        }
+
+        u32TmpVal = ((RTC->LXTCTL & RTC_LXTCTL_RTCCKSEL_Msk) >> RTC_LXTCTL_RTCCKSEL_Pos);
+
+        if(u32RTCCKEN == 0UL)
+        {
+            CLK->APBCLK0 &= (~CLK_APBCLK0_RTCCKEN_Msk); /* Disable RTC clock if it is disabled before */
+        }
+
+    }
+    else if(u32ModuleIdx == EPWM0_MODULE)
+    {
+        u32TmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk) >> CLK_CLKSEL2_EPWM0SEL_Pos);
+    }
+    else if(u32ModuleIdx == EPWM1_MODULE)
+    {
+        u32TmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk) >> CLK_CLKSEL2_EPWM1SEL_Pos);
+    }
+    else if(u32ModuleIdx == BPWM0_MODULE)
+    {
+        u32TmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk) >> CLK_CLKSEL2_BPWM0SEL_Pos);
+    }
+    else if(u32ModuleIdx == BPWM1_MODULE)
+    {
+        u32TmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk) >> CLK_CLKSEL2_BPWM1SEL_Pos);
+    }
+    else if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk)
+    {
+        /* Get clock select control register address */
+        u32TmpAddr = (uint32_t)&CLK->CLKSEL0 + (au32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]);
+
+        /* Get clock source selection setting */
+        u32TmpVal = ((inpw((uint32_t *)u32TmpAddr) & (MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx))) >> MODULE_CLKSEL_Pos(u32ModuleIdx));
+    }
+
+    return u32TmpVal;
+}
+
+/**
+  * @brief      Get selected module clock divider number
+  * @param[in]  u32ModuleIdx is module index.
+  *             - \ref SDH0_MODULE
+  *             - \ref USBH_MODULE
+  *             - \ref UART0_MODULE
+  *             - \ref UART1_MODULE
+  *             - \ref UART2_MODULE
+  *             - \ref UART3_MODULE
+  *             - \ref UART4_MODULE
+  *             - \ref UART5_MODULE
+  *             - \ref OTG_MODULE
+  *             - \ref USBD_MODULE
+  *             - \ref SC0_MODULE
+  *             - \ref SC1_MODULE
+  *             - \ref SC2_MODULE
+  *             - \ref EADC_MODULE
+  * @return     Selected module clock divider number setting
+  * @details    This function get selected module clock divider number.
+  */
+
+__NONSECURE_ENTRY_WEAK
+uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx)
+{
+    uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL;
+    uint32_t au32DivTbl[4] = {0x0UL, 0x4UL, 0x8UL, 0x10UL};
+
+    if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk)
+    {
+        /* Get clock divider control register address */
+        u32TmpAddr = (uint32_t)&CLK->CLKDIV0 + (au32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]);
+        /* Get clock divider number setting */
+        u32TmpVal = ((inpw((uint32_t *)u32TmpAddr) & (MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx))) >> MODULE_CLKDIV_Pos(u32ModuleIdx));
+    }
+
+    return u32TmpVal;
+}
+
+
+/**@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group CLK_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_crc.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_crc.c
new file mode 100644
index 0000000000..e3c9a4b1bf
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_crc.c
@@ -0,0 +1,96 @@
+/**************************************************************************//**
+ * @file     crc.c
+ * @version  V3.00
+ * @brief    Cyclic Redundancy Check(CRC) driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup CRC_Driver CRC Driver
+  @{
+*/
+
+/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions
+  @{
+*/
+
+/**
+  * @brief      CRC Open
+  *
+  * @param[in]  u32Mode         CRC operation polynomial mode. Valid values are:
+  *                             - \ref CRC_CCITT
+  *                             - \ref CRC_8
+  *                             - \ref CRC_16
+  *                             - \ref CRC_32
+  * @param[in]  u32Attribute    CRC operation data attribute. Valid values are combined with:
+  *                             - \ref CRC_CHECKSUM_COM
+  *                             - \ref CRC_CHECKSUM_RVS
+  *                             - \ref CRC_WDATA_COM
+  *                             - \ref CRC_WDATA_RVS
+  * @param[in]  u32Seed         Seed value.
+  * @param[in]  u32DataLen      CPU Write Data Length. Valid values are:
+  *                             - \ref CRC_CPU_WDATA_8
+  *                             - \ref CRC_CPU_WDATA_16
+  *                             - \ref CRC_CPU_WDATA_32
+  *
+  * @return     None
+  *
+  * @details    This function will enable the CRC controller by specify CRC operation mode, attribute, initial seed and write data length. \n
+  *             After that, user can start to perform CRC calculate by calling CRC_WRITE_DATA macro or CRC_DAT register directly.
+  */
+void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen)
+{
+    CRC->SEED = u32Seed;
+    CRC->CTL = u32Mode | u32Attribute | u32DataLen | CRC_CTL_CRCEN_Msk;
+
+    /* Setting CHKSINIT bit will reload the initial seed value(CRC_SEED register) to CRC controller */
+    CRC->CTL |= CRC_CTL_CHKSINIT_Msk;
+}
+
+/**
+  * @brief      Get CRC Checksum
+  *
+  * @param[in]  None
+  *
+  * @return     Checksum Result
+  *
+  * @details    This function gets the CRC checksum result by current CRC polynomial mode.
+  */
+uint32_t CRC_GetChecksum(void)
+{
+    uint32_t u32Checksum = 0UL;
+
+    switch(CRC->CTL & CRC_CTL_CRCMODE_Msk)
+    {
+        case CRC_CCITT:
+        case CRC_16:
+            u32Checksum = (CRC->CHECKSUM & 0xFFFFUL);
+            break;
+
+        case CRC_32:
+            u32Checksum = CRC->CHECKSUM;
+            break;
+
+        case CRC_8:
+            u32Checksum = (CRC->CHECKSUM & 0xFFUL);
+            break;
+
+        default:
+            break;
+    }
+
+    return u32Checksum;
+}
+
+/**@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group CRC_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_crypto.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_crypto.c
new file mode 100644
index 0000000000..3e0bf6480e
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_crypto.c
@@ -0,0 +1,2973 @@
+/**************************************************************************//**
+ * @file     crypto.c
+ * @version  V3.00
+ * @brief  Cryptographic Accelerator driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+#include 
+#include 
+#include "NuMicro.h"
+
+#define ENABLE_DEBUG    0
+
+#define ECC_SCA_PROTECT 1       // Enable Side-Channel Protecton
+
+#if ENABLE_DEBUG
+#define CRPT_DBGMSG   printf
+#else
+#define CRPT_DBGMSG(...)   do { } while (0)       /* disable debug */
+#endif
+
+#if defined(__ICCARM__)
+# pragma diag_suppress=Pm073, Pm143        /* Misra C rule 14.7 */
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup CRYPTO_Driver CRYPTO Driver
+  @{
+*/
+
+
+/** @addtogroup CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions
+  @{
+*/
+
+/* // @cond HIDDEN_SYMBOLS */
+
+
+static char  hex_char_tbl[] = "0123456789abcdef";
+
+static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count);
+static char get_Nth_nibble_char(uint32_t val32, uint32_t idx);
+static void Hex2Reg(char input[], uint32_t volatile reg[]);
+static void Reg2Hex(int32_t count, uint32_t volatile reg[], char output[]);
+static char ch2hex(char ch);
+static void Hex2RegEx(char input[], uint32_t volatile reg[], int shift);
+static int  get_nibble_value(char c);
+int32_t ECC_Mutiply(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char x1[], char y1[], char *k, char x2[], char y2[]);
+void ECC_Complete(CRPT_T *crpt);
+
+
+/* // @endcond HIDDEN_SYMBOLS */
+
+/**
+  * @brief  Open PRNG function
+  * @param[in]  crpt         The pointer of CRYPTO module
+  * @param[in]  u32KeySize   it is PRNG key size, including:
+  *         - \ref PRNG_KEY_SIZE_64
+  *         - \ref PRNG_KEY_SIZE_128
+  *         - \ref PRNG_KEY_SIZE_192
+  *         - \ref PRNG_KEY_SIZE_256
+  * @param[in]  u32SeedReload is PRNG seed reload or not, including:
+  *         - \ref PRNG_SEED_CONT
+  *         - \ref PRNG_SEED_RELOAD
+  * @param[in]  u32Seed  The new seed. Only valid when u32SeedReload is PRNG_SEED_RELOAD.
+  * @return None
+  */
+void PRNG_Open(CRPT_T *crpt, uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed)
+{
+    if(u32SeedReload)
+    {
+        crpt->PRNG_SEED = u32Seed;
+    }
+
+    crpt->PRNG_CTL = (u32KeySize << CRPT_PRNG_CTL_KEYSZ_Pos) |
+                     (u32SeedReload << CRPT_PRNG_CTL_SEEDRLD_Pos);
+}
+
+/**
+  * @brief  Start to generate one PRNG key.
+  * @param[in]  crpt         The pointer of CRYPTO module
+  * @return None
+  */
+void PRNG_Start(CRPT_T *crpt)
+{
+    crpt->PRNG_CTL |= CRPT_PRNG_CTL_START_Msk;
+
+    /* Waiting for PRNG Busy */
+    while(crpt->PRNG_CTL & CRPT_PRNG_CTL_BUSY_Msk) {}
+
+}
+
+/**
+  * @brief  Read the PRNG key.
+  * @param[in]   crpt         The pointer of CRYPTO module
+  * @param[out]  u32RandKey  The key buffer to store newly generated PRNG key.
+  * @return None
+  */
+void PRNG_Read(CRPT_T *crpt, uint32_t u32RandKey[])
+{
+    uint32_t  i, wcnt;
+
+    wcnt = (((crpt->PRNG_CTL & CRPT_PRNG_CTL_KEYSZ_Msk) >> CRPT_PRNG_CTL_KEYSZ_Pos) + 1U) * 2U;
+
+    for(i = 0U; i < wcnt; i++)
+    {
+        u32RandKey[i] = crpt->PRNG_KEY[i];
+    }
+
+    crpt->PRNG_CTL &= ~CRPT_PRNG_CTL_SEEDRLD_Msk;
+}
+
+
+/**
+  * @brief  Open AES encrypt/decrypt function.
+  * @param[in]  crpt         The pointer of CRYPTO module
+  * @param[in]  u32Channel   AES channel. Must be 0~3.
+  * @param[in]  u32EncDec    1: AES encode;  0: AES decode
+  * @param[in]  u32OpMode    AES operation mode, including:
+  *         - \ref AES_MODE_ECB
+  *         - \ref AES_MODE_CBC
+  *         - \ref AES_MODE_CFB
+  *         - \ref AES_MODE_OFB
+  *         - \ref AES_MODE_CTR
+  *         - \ref AES_MODE_CBC_CS1
+  *         - \ref AES_MODE_CBC_CS2
+  *         - \ref AES_MODE_CBC_CS3
+  * @param[in]  u32KeySize is AES key size, including:
+  *         - \ref AES_KEY_SIZE_128
+  *         - \ref AES_KEY_SIZE_192
+  *         - \ref AES_KEY_SIZE_256
+  * @param[in]  u32SwapType is AES input/output data swap control, including:
+  *         - \ref AES_NO_SWAP
+  *         - \ref AES_OUT_SWAP
+  *         - \ref AES_IN_SWAP
+  *         - \ref AES_IN_OUT_SWAP
+  * @return None
+  */
+void AES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec,
+              uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType)
+{
+    (void)u32Channel;
+
+    crpt->AES_CTL = (u32EncDec << CRPT_AES_CTL_ENCRPT_Pos) |
+                    (u32OpMode << CRPT_AES_CTL_OPMODE_Pos) |
+                    (u32KeySize << CRPT_AES_CTL_KEYSZ_Pos) |
+                    (u32SwapType << CRPT_AES_CTL_OUTSWAP_Pos);
+
+}
+
+/**
+  * @brief  Start AES encrypt/decrypt
+  * @param[in]  crpt        The pointer of CRYPTO module
+  * @param[in]  u32Channel  AES channel. Must be 0~3.
+  * @param[in]  u32DMAMode  AES DMA control, including:
+  *         - \ref CRYPTO_DMA_ONE_SHOT   One shot AES encrypt/decrypt.
+  *         - \ref CRYPTO_DMA_CONTINUE   Continuous AES encrypt/decrypt.
+  *         - \ref CRYPTO_DMA_LAST       Last AES encrypt/decrypt of a series of AES_Start.
+  * @return None
+  */
+void AES_Start(CRPT_T *crpt, int32_t u32Channel, uint32_t u32DMAMode)
+{
+    (void)u32Channel;
+
+    crpt->AES_CTL |= CRPT_AES_CTL_START_Msk | (u32DMAMode << CRPT_AES_CTL_DMALAST_Pos);
+}
+
+/**
+  * @brief  Set AES keys
+  * @param[in]  crpt        The pointer of CRYPTO module
+  * @param[in]  u32Channel  AES channel. Must be 0~3.
+  * @param[in]  au32Keys    An word array contains AES keys.
+  * @param[in]  u32KeySize is AES key size, including:
+  *         - \ref AES_KEY_SIZE_128
+  *         - \ref AES_KEY_SIZE_192
+  *         - \ref AES_KEY_SIZE_256
+  * @return None
+  */
+void AES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize)
+{
+    uint32_t  i, wcnt, key_reg_addr;
+
+    (void) u32Channel;
+
+    key_reg_addr = (uint32_t)&crpt->AES_KEY[0];
+    wcnt = 4UL + u32KeySize * 2UL;
+
+    for(i = 0U; i < wcnt; i++)
+    {
+        outpw(key_reg_addr, au32Keys[i]);
+        key_reg_addr += 4UL;
+    }
+}
+
+
+
+/**
+  * @brief  Set AES keys index of Key Store
+  * @param[in]  crpt        The pointer of CRYPTO module
+  * @param[in]  mem         Memory type of Key Store key. it could be:
+  *                              - \ref KS_SRAM
+  *                              - \ref KS_FLASH
+  *                              - \ref KS_OTP
+  * @param[in]  i32KeyIdx   Index of the key in Key Store.
+  * @details    AES could use the key in Key Store. This function is used to set the key index of Key Store.
+  */
+void AES_SetKey_KS(CRPT_T *crpt, KS_MEM_Type mem, int32_t i32KeyIdx)
+{
+    /* Use key in key store */
+    crpt->AES_KSCTL = CRPT_AES_KSCTL_RSRC_Msk /* use KS */  |
+                      (uint32_t)((int)mem << CRPT_AES_KSCTL_RSSRC_Pos) /* KS Memory type */ |
+                      (uint32_t)i32KeyIdx /* key num */ ;
+
+}
+
+
+/**
+  * @brief  Set AES initial vectors
+  * @param[in]  crpt        The pointer of CRYPTO module
+  * @param[in]  u32Channel  AES channel. Must be 0~3.
+  * @param[in]  au32IV      A four entry word array contains AES initial vectors.
+  * @return None
+  */
+void AES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32IV[])
+{
+    uint32_t  i, key_reg_addr;
+
+    (void) u32Channel;
+
+    key_reg_addr = (uint32_t)&crpt->AES_IV[0];
+
+    for(i = 0U; i < 4U; i++)
+    {
+        outpw(key_reg_addr, au32IV[i]);
+        key_reg_addr += 4UL;
+    }
+}
+
+/**
+  * @brief  Set AES DMA transfer configuration.
+  * @param[in]  crpt         The pointer of CRYPTO module
+  * @param[in]  u32Channel   AES channel. Must be 0~3.
+  * @param[in]  u32SrcAddr   AES DMA source address
+  * @param[in]  u32DstAddr   AES DMA destination address
+  * @param[in]  u32TransCnt  AES DMA transfer byte count
+  * @return None
+  */
+void AES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr,
+                        uint32_t u32DstAddr, uint32_t u32TransCnt)
+{
+    (void) u32Channel;
+
+    crpt->AES_SADDR = u32SrcAddr;
+    crpt->AES_DADDR = u32DstAddr;
+    crpt->AES_CNT   = u32TransCnt;
+
+}
+
+/**
+  * @brief  Open SHA encrypt function.
+  * @param[in]  crpt        The pointer of CRYPTO module
+  * @param[in]  u32OpMode   SHA operation mode, including:
+  *         - \ref SHA_MODE_SHA1
+  *         - \ref SHA_MODE_SHA224
+  *         - \ref SHA_MODE_SHA256
+  * @param[in]  u32SwapType is SHA input/output data swap control, including:
+  *         - \ref SHA_NO_SWAP
+  *         - \ref SHA_OUT_SWAP
+  *         - \ref SHA_IN_SWAP
+  *         - \ref SHA_IN_OUT_SWAP
+  * @param[in]  hmac_key_len   HMAC key byte count
+  * @return None
+  */
+void SHA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32SwapType, uint32_t hmac_key_len)
+{
+    crpt->HMAC_CTL = (u32OpMode << CRPT_HMAC_CTL_OPMODE_Pos) |
+                     (u32SwapType << CRPT_HMAC_CTL_OUTSWAP_Pos);
+
+    if(hmac_key_len != 0UL)
+    {
+        crpt->HMAC_KEYCNT = hmac_key_len;
+    }
+}
+
+/**
+  * @brief  Start SHA encrypt
+  * @param[in]  crpt        The pointer of CRYPTO module
+  * @param[in]  u32DMAMode  TDES DMA control, including:
+  *         - \ref CRYPTO_DMA_ONE_SHOT   One shop SHA encrypt.
+  *         - \ref CRYPTO_DMA_CONTINUE   Continuous SHA encrypt.
+  *         - \ref CRYPTO_DMA_LAST       Last SHA encrypt of a series of SHA_Start.
+  * @return None
+  */
+void SHA_Start(CRPT_T *crpt, uint32_t u32DMAMode)
+{
+    crpt->HMAC_CTL &= ~(0x7UL << CRPT_HMAC_CTL_DMALAST_Pos);
+    crpt->HMAC_CTL |= CRPT_HMAC_CTL_START_Msk | (u32DMAMode << CRPT_HMAC_CTL_DMALAST_Pos);
+}
+
+/**
+  * @brief  Set SHA DMA transfer
+  * @param[in]  crpt         The pointer of CRYPTO module
+  * @param[in]  u32SrcAddr   SHA DMA source address
+  * @param[in]  u32TransCnt  SHA DMA transfer byte count
+  * @return None
+  */
+void SHA_SetDMATransfer(CRPT_T *crpt, uint32_t u32SrcAddr, uint32_t u32TransCnt)
+{
+    crpt->HMAC_SADDR = u32SrcAddr;
+    crpt->HMAC_DMACNT = u32TransCnt;
+}
+
+/**
+  * @brief  Read the SHA digest.
+  * @param[in]   crpt       The pointer of CRYPTO module
+  * @param[out]  u32Digest  The SHA encrypt output digest.
+  * @return None
+  */
+void SHA_Read(CRPT_T *crpt, uint32_t u32Digest[])
+{
+    uint32_t  i, wcnt, reg_addr;
+
+    i = (crpt->HMAC_CTL & CRPT_HMAC_CTL_OPMODE_Msk) >> CRPT_HMAC_CTL_OPMODE_Pos;
+
+    if(i == SHA_MODE_SHA1)
+    {
+        wcnt = 5UL;
+    }
+    else if(i == SHA_MODE_SHA224)
+    {
+        wcnt = 7UL;
+    }
+    else if(i == SHA_MODE_SHA256)
+    {
+        wcnt = 8UL;
+    }
+    else if(i == SHA_MODE_SHA384)
+    {
+        wcnt = 12UL;
+    }
+    else
+    {
+        /* SHA_MODE_SHA512 */
+        wcnt = 16UL;
+    }
+
+    reg_addr = (uint32_t) & (crpt->HMAC_DGST[0]);
+    for(i = 0UL; i < wcnt; i++)
+    {
+        u32Digest[i] = inpw(reg_addr);
+        reg_addr += 4UL;
+    }
+}
+
+
+/*-----------------------------------------------------------------------------------------------*/
+/*                                                                                               */
+/*    ECC                                                                                        */
+/*                                                                                               */
+/*-----------------------------------------------------------------------------------------------*/
+
+#define ECCOP_POINT_MUL     (0x0UL << CRPT_ECC_CTL_ECCOP_Pos)
+#define ECCOP_MODULE        (0x1UL << CRPT_ECC_CTL_ECCOP_Pos)
+#define ECCOP_POINT_ADD     (0x2UL << CRPT_ECC_CTL_ECCOP_Pos)
+#define ECCOP_POINT_DOUBLE  (0x0UL << CRPT_ECC_CTL_ECCOP_Pos)
+
+#define MODOP_DIV           (0x0UL << CRPT_ECC_CTL_MODOP_Pos)
+#define MODOP_MUL           (0x1UL << CRPT_ECC_CTL_MODOP_Pos)
+#define MODOP_ADD           (0x2UL << CRPT_ECC_CTL_MODOP_Pos)
+#define MODOP_SUB           (0x3UL << CRPT_ECC_CTL_MODOP_Pos)
+
+#define OP_ECDSAS           (0x1UL << CRPT_ECC_CTL_ECDSAS_Pos)
+#define OP_ECDSAR           (0x1UL << CRPT_ECC_CTL_ECDSAR_Pos)
+
+enum
+{
+    CURVE_GF_P,
+    CURVE_GF_2M,
+};
+
+/*-----------------------------------------------------*/
+/*  Define elliptic curve (EC):                        */
+/*-----------------------------------------------------*/
+static const ECC_CURVE _Curve[] =
+{
+    {
+        /* NIST: Curve P-192 : y^2=x^3-ax+b (mod p) */
+        CURVE_P_192,
+        48,     /* Echar */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFC",   /* "000000000000000000000000000000000000000000000003" */
+        "64210519e59c80e70fa7e9ab72243049feb8deecc146b9b1",
+        "188da80eb03090f67cbf20eb43a18800f4ff0afd82ff1012",
+        "07192b95ffc8da78631011ed6b24cdd573f977a11e794811",
+        58,     /* Epl */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFF",   /* "6277101735386680763835789423207666416083908700390324961279" */
+        58,     /* Eol */
+        "FFFFFFFFFFFFFFFFFFFFFFFF99DEF836146BC9B1B4D22831",   /* "6277101735386680763835789423176059013767194773182842284081" */
+        192,    /* key_len */
+        7,
+        2,
+        1,
+        CURVE_GF_P
+    },
+    {
+        /* NIST: Curve P-224 : y^2=x^3-ax+b (mod p) */
+        CURVE_P_224,
+        56,     /* Echar */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFE",  /* "00000000000000000000000000000000000000000000000000000003" */
+        "b4050a850c04b3abf54132565044b0b7d7bfd8ba270b39432355ffb4",
+        "b70e0cbd6bb4bf7f321390b94a03c1d356c21122343280d6115c1d21",
+        "bd376388b5f723fb4c22dfe6cd4375a05a07476444d5819985007e34",
+        70,     /* Epl */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001",  /* "0026959946667150639794667015087019630673557916260026308143510066298881" */
+        70,     /* Eol */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFF16A2E0B8F03E13DD29455C5C2A3D",  /* "0026959946667150639794667015087019625940457807714424391721682722368061" */
+        224,    /* key_len */
+        9,
+        8,
+        3,
+        CURVE_GF_P
+    },
+    {
+        /* NIST: Curve P-256 : y^2=x^3-ax+b (mod p) */
+        CURVE_P_256,
+        64,     /* Echar */
+        "FFFFFFFF00000001000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFC",  /* "0000000000000000000000000000000000000000000000000000000000000003" */
+        "5ac635d8aa3a93e7b3ebbd55769886bc651d06b0cc53b0f63bce3c3e27d2604b",
+        "6b17d1f2e12c4247f8bce6e563a440f277037d812deb33a0f4a13945d898c296",
+        "4fe342e2fe1a7f9b8ee7eb4a7c0f9e162bce33576b315ececbb6406837bf51f5",
+        78,     /* Epl */
+        "FFFFFFFF00000001000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFF",  /* "115792089210356248762697446949407573530086143415290314195533631308867097853951" */
+        78,     /* Eol */
+        "FFFFFFFF00000000FFFFFFFFFFFFFFFFBCE6FAADA7179E84F3B9CAC2FC632551",  /* "115792089210356248762697446949407573529996955224135760342422259061068512044369" */
+        256,    /* key_len */
+        10,
+        5,
+        2,
+        CURVE_GF_P
+    },
+    {
+        /* NIST: Curve P-384 : y^2=x^3-ax+b (mod p) */
+        CURVE_P_384,
+        96,     /* Echar */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFF0000000000000000FFFFFFFC",  /* "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003" */
+        "b3312fa7e23ee7e4988e056be3f82d19181d9c6efe8141120314088f5013875ac656398d8a2ed19d2a85c8edd3ec2aef",
+        "aa87ca22be8b05378eb1c71ef320ad746e1d3b628ba79b9859f741e082542a385502f25dbf55296c3a545e3872760ab7",
+        "3617de4a96262c6f5d9e98bf9292dc29f8f41dbd289a147ce9da3113b5f0b8c00a60b1ce1d7e819d7a431d7c90ea0e5f",
+        116,    /* Epl */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFF0000000000000000FFFFFFFF",  /* "39402006196394479212279040100143613805079739270465446667948293404245721771496870329047266088258938001861606973112319" */
+        116,    /* Eol */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC7634D81F4372DDF581A0DB248B0A77AECEC196ACCC52973",  /* "39402006196394479212279040100143613805079739270465446667946905279627659399113263569398956308152294913554433653942643" */
+        384,    /* key_len */
+        12,
+        3,
+        2,
+        CURVE_GF_P
+    },
+    {
+        /* NIST: Curve P-521 : y^2=x^3-ax+b (mod p)*/
+        CURVE_P_521,
+        131,    /* Echar */
+        "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC",  /* "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003" */
+        "051953eb9618e1c9a1f929a21a0b68540eea2da725b99b315f3b8b489918ef109e156193951ec7e937b1652c0bd3bb1bf073573df883d2c34f1ef451fd46b503f00",
+        "0c6858e06b70404e9cd9e3ecb662395b4429c648139053fb521f828af606b4d3dbaa14b5e77efe75928fe1dc127a2ffa8de3348b3c1856a429bf97e7e31c2e5bd66",
+        "11839296a789a3bc0045c8a5fb42c7d1bd998f54449579b446817afbd17273e662c97ee72995ef42640c550b9013fad0761353c7086a272c24088be94769fd16650",
+        157,    /* Epl */
+        "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",  /* "6864797660130609714981900799081393217269435300143305409394463459185543183397656052122559640661454554977296311391480858037121987999716643812574028291115057151" */
+        157,    /* Eol */
+        "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA51868783BF2F966B7FCC0148F709A5D03BB5C9B8899C47AEBB6FB71E91386409",  /* "6864797660130609714981900799081393217269435300143305409394463459185543183397655394245057746333217197532963996371363321113864768612440380340372808892707005449" */
+        521,    /* key_len */
+        32,
+        32,
+        32,
+        CURVE_GF_P
+    },
+    {
+        /* NIST: Curve B-163 : y^2+xy=x^3+ax^2+b */
+        CURVE_B_163,
+        41,     /* Echar */
+        "00000000000000000000000000000000000000001",
+        "20a601907b8c953ca1481eb10512f78744a3205fd",
+        "3f0eba16286a2d57ea0991168d4994637e8343e36",
+        "0d51fbc6c71a0094fa2cdd545b11c5c0c797324f1",
+        68,     /* Epl */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001",  /* "26959946667150639794667015087019630673557916260026308143510066298881" */
+        49,     /* Eol */
+        "40000000000000000000292FE77E70C12A4234C33",   /* "5846006549323611672814742442876390689256843201587" */
+        163,    /* key_len */
+        7,
+        6,
+        3,
+        CURVE_GF_2M
+    },
+    {
+        /* NIST: Curve B-233 : y^2+xy=x^3+ax^2+b */
+        CURVE_B_233,
+        59,     /* Echar 59 */
+        "00000000000000000000000000000000000000000000000000000000001",
+        "066647ede6c332c7f8c0923bb58213b333b20e9ce4281fe115f7d8f90ad",
+        "0fac9dfcbac8313bb2139f1bb755fef65bc391f8b36f8f8eb7371fd558b",
+        "1006a08a41903350678e58528bebf8a0beff867a7ca36716f7e01f81052",
+        68,     /* Epl */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001",  /* "26959946667150639794667015087019630673557916260026308143510066298881" */
+        70,     /* Eol */
+        "1000000000000000000000000000013E974E72F8A6922031D2603CFE0D7",  /* "6901746346790563787434755862277025555839812737345013555379383634485463" */
+        233,    /* key_len */
+        74,
+        74,
+        74,
+        CURVE_GF_2M
+    },
+    {
+        /* NIST: Curve B-283 : y^2+xy=x^3+ax^2+b */
+        CURVE_B_283,
+        71,     /* Echar */
+        "00000000000000000000000000000000000000000000000000000000000000000000001",
+        "27b680ac8b8596da5a4af8a19a0303fca97fd7645309fa2a581485af6263e313b79a2f5",
+        "5f939258db7dd90e1934f8c70b0dfec2eed25b8557eac9c80e2e198f8cdbecd86b12053",
+        "3676854fe24141cb98fe6d4b20d02b4516ff702350eddb0826779c813f0df45be8112f4",
+        68,     /* Epl */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001",  /* "26959946667150639794667015087019630673557916260026308143510066298881" */
+        85,     /* Eol */
+        "3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEF90399660FC938A90165B042A7CEFADB307",  /* "7770675568902916283677847627294075626569625924376904889109196526770044277787378692871" */
+        283,    /* key_len */
+        12,
+        7,
+        5,
+        CURVE_GF_2M
+    },
+    {
+        /* NIST: Curve B-409 : y^2+xy=x^3+ax^2+b */
+        CURVE_B_409,
+        103,    /* Echar */
+        "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001",
+        "021a5c2c8ee9feb5c4b9a753b7b476b7fd6422ef1f3dd674761fa99d6ac27c8a9a197b272822f6cd57a55aa4f50ae317b13545f",
+        "15d4860d088ddb3496b0c6064756260441cde4af1771d4db01ffe5b34e59703dc255a868a1180515603aeab60794e54bb7996a7",
+        "061b1cfab6be5f32bbfa78324ed106a7636b9c5a7bd198d0158aa4f5488d08f38514f1fdf4b4f40d2181b3681c364ba0273c706",
+        68,     /* Epl */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001",  /* "26959946667150639794667015087019630673557916260026308143510066298881" */
+        123,    /* Eol */
+        "10000000000000000000000000000000000000000000000000001E2AAD6A612F33307BE5FA47C3C9E052F838164CD37D9A21173",  /* "661055968790248598951915308032771039828404682964281219284648798304157774827374805208143723762179110965979867288366567526771" */
+        409,    /* key_len */
+        87,
+        87,
+        87,
+        CURVE_GF_2M
+    },
+    {
+        /* NIST: Curve B-571 : y^2+xy=x^3+ax^2+b */
+        CURVE_B_571,
+        143,    /* Echar */
+        "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001",
+        "2f40e7e2221f295de297117b7f3d62f5c6a97ffcb8ceff1cd6ba8ce4a9a18ad84ffabbd8efa59332be7ad6756a66e294afd185a78ff12aa520e4de739baca0c7ffeff7f2955727a",
+        "303001d34b856296c16c0d40d3cd7750a93d1d2955fa80aa5f40fc8db7b2abdbde53950f4c0d293cdd711a35b67fb1499ae60038614f1394abfa3b4c850d927e1e7769c8eec2d19",
+        "37bf27342da639b6dccfffeb73d69d78c6c27a6009cbbca1980f8533921e8a684423e43bab08a576291af8f461bb2a8b3531d2f0485c19b16e2f1516e23dd3c1a4827af1b8ac15b",
+        68,     /* Epl */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001",  /* "26959946667150639794667015087019630673557916260026308143510066298881" */
+        172,    /* Eol */
+        "3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE661CE18FF55987308059B186823851EC7DD9CA1161DE93D5174D66E8382E9BB2FE84E47",  /* "3864537523017258344695351890931987344298927329706434998657235251451519142289560424536143999389415773083133881121926944486246872462816813070234528288303332411393191105285703" */
+        571,    /* key_len */
+        10,
+        5,
+        2,
+        CURVE_GF_2M
+    },
+    {
+        /* NIST: Curve K-163 : y^2+xy=x^3+ax^2+b */
+        CURVE_K_163,
+        41,     /* Echar */
+        "00000000000000000000000000000000000000001",
+        "00000000000000000000000000000000000000001",
+        "2fe13c0537bbc11acaa07d793de4e6d5e5c94eee8",
+        "289070fb05d38ff58321f2e800536d538ccdaa3d9",
+        68,     /* Epl */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001",  /* "26959946667150639794667015087019630673557916260026308143510066298881" */
+        49,     /* Eol */
+        "4000000000000000000020108A2E0CC0D99F8A5EF",  /* "5846006549323611672814741753598448348329118574063" */
+        163,    /* key_len */
+        7,
+        6,
+        3,
+        CURVE_GF_2M
+    },
+    {
+        /* NIST: Curve K-233 : y^2+xy=x^3+ax^2+b */
+        CURVE_K_233,
+        59,     /* Echar 59 */
+        "00000000000000000000000000000000000000000000000000000000000",
+        "00000000000000000000000000000000000000000000000000000000001",
+        "17232ba853a7e731af129f22ff4149563a419c26bf50a4c9d6eefad6126",
+        "1db537dece819b7f70f555a67c427a8cd9bf18aeb9b56e0c11056fae6a3",
+        68,     /* Epl */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001",    /* "26959946667150639794667015087019630673557916260026308143510066298881" */
+        70,     /* Eol */
+        "8000000000000000000000000000069D5BB915BCD46EFB1AD5F173ABDF",  /* "3450873173395281893717377931138512760570940988862252126328087024741343" */
+        233,    /* key_len */
+        74,
+        74,
+        74,
+        CURVE_GF_2M
+    },
+    {
+        /* NIST: Curve K-283 : y^2+xy=x^3+ax^2+b */
+        CURVE_K_283,
+        71,     /* Echar */
+        "00000000000000000000000000000000000000000000000000000000000000000000000",
+        "00000000000000000000000000000000000000000000000000000000000000000000001",
+        "503213f78ca44883f1a3b8162f188e553cd265f23c1567a16876913b0c2ac2458492836",
+        "1ccda380f1c9e318d90f95d07e5426fe87e45c0e8184698e45962364e34116177dd2259",
+        68,     /* Epl */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001",  /* "26959946667150639794667015087019630673557916260026308143510066298881" */
+        85,     /* Eol */
+        "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE9AE2ED07577265DFF7F94451E061E163C61",  /* "3885337784451458141838923813647037813284811733793061324295874997529815829704422603873" */
+        283,    /* key_len */
+        12,
+        7,
+        5,
+        CURVE_GF_2M
+    },
+    {
+        /* NIST: Curve K-409 : y^2+xy=x^3+ax^2+b */
+        CURVE_K_409,
+        103,    /* Echar */
+        "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+        "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001",
+        "060f05f658f49c1ad3ab1890f7184210efd0987e307c84c27accfb8f9f67cc2c460189eb5aaaa62ee222eb1b35540cfe9023746",
+        "1e369050b7c4e42acba1dacbf04299c3460782f918ea427e6325165e9ea10e3da5f6c42e9c55215aa9ca27a5863ec48d8e0286b",
+        68,     /* Epl */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001",  /* "26959946667150639794667015087019630673557916260026308143510066298881" */
+        123,    /* Eol */
+        "7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE5F83B2D4EA20400EC4557D5ED3E3E7CA5B4B5C83B8E01E5FCF",  /* "330527984395124299475957654016385519914202341482140609642324395022880711289249191050673258457777458014096366590617731358671" */
+        409,    /* key_len */
+        87,
+        87,
+        87,
+        CURVE_GF_2M
+    },
+    {
+        /* NIST: Curve K-571 : y^2+xy=x^3+ax^2+b */
+        CURVE_K_571,
+        143,    /* Echar */
+        "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
+        "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001",
+        "26eb7a859923fbc82189631f8103fe4ac9ca2970012d5d46024804801841ca44370958493b205e647da304db4ceb08cbbd1ba39494776fb988b47174dca88c7e2945283a01c8972",
+        "349dc807f4fbf374f4aeade3bca95314dd58cec9f307a54ffc61efc006d8a2c9d4979c0ac44aea74fbebbb9f772aedcb620b01a7ba7af1b320430c8591984f601cd4c143ef1c7a3",
+        68,     /* Epl */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001",  /* "26959946667150639794667015087019630673557916260026308143510066298881" */
+        172,    /* Eol */
+        "20000000000000000000000000000000000000000000000000000000000000000000000131850E1F19A63E4B391A8DB917F4138B630D84BE5D639381E91DEB45CFE778F637C1001",  /* "1932268761508629172347675945465993672149463664853217499328617625725759571144780212268133978522706711834706712800825351461273674974066617311929682421617092503555733685276673" */
+        571,    /* key_len */
+        10,
+        5,
+        2,
+        CURVE_GF_2M
+    },
+    {
+        /* Koblitz: Curve secp192k1 : y2 = x3+ax+b over Fp */
+        CURVE_KO_192,
+        48,     /* Echar */
+        "00000000000000000000000000000000000000000",
+        "00000000000000000000000000000000000000003",
+        "DB4FF10EC057E9AE26B07D0280B7F4341DA5D1B1EAE06C7D",
+        "9B2F2F6D9C5628A7844163D015BE86344082AA88D95E2F9D",
+        58,     /* Epl */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFEE37",  /* p */
+        58,     /* Eol */
+        "FFFFFFFFFFFFFFFFFFFFFFFE26F2FC170F69466A74DEFD8D",  /* n */
+        192,    /* key_len */
+        7,
+        2,
+        1,
+        CURVE_GF_P
+    },
+    {
+        /* Koblitz: Curve secp224k1 : y2 = x3+ax+b over Fp */
+        CURVE_KO_224,
+        56,     /* Echar */
+        "00000000000000000000000000000000000000000000000000000000",
+        "00000000000000000000000000000000000000000000000000000005",
+        "A1455B334DF099DF30FC28A169A467E9E47075A90F7E650EB6B7A45C",
+        "7E089FED7FBA344282CAFBD6F7E319F7C0B0BD59E2CA4BDB556D61A5",
+        70,     /* Epl */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFE56D",  /* p */
+        70,     /* Eol */
+        "0000000000000000000000000001DCE8D2EC6184CAF0A971769FB1F7",  /* n */
+        224,    /* key_len */
+        7,
+        2,
+        1,
+        CURVE_GF_P
+    },
+    {
+        /* Koblitz: Curve secp256k1 : y2 = x3+ax+b over Fp */
+        CURVE_KO_256,
+        64,     /* Echar */
+        "0000000000000000000000000000000000000000000000000000000000000000",
+        "0000000000000000000000000000000000000000000000000000000000000007",
+        "79BE667EF9DCBBAC55A06295CE870B07029BFCDB2DCE28D959F2815B16F81798",
+        "483ADA7726A3C4655DA4FBFC0E1108A8FD17B448A68554199C47D08FFB10D4B8",
+        78,     /* Epl */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFC2F",  /* p */
+        78,     /* Eol */
+        "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEBAAEDCE6AF48A03BBFD25E8CD0364141",  /* n */
+        256,    /* key_len */
+        7,
+        2,
+        1,
+        CURVE_GF_P
+    },
+    {
+        /* Brainpool: Curve brainpoolP256r1 */
+        CURVE_BP_256,
+        64,     /* Echar */
+        "7D5A0975FC2C3057EEF67530417AFFE7FB8055C126DC5C6CE94A4B44F330B5D9",  /* A */
+        "26DC5C6CE94A4B44F330B5D9BBD77CBF958416295CF7E1CE6BCCDC18FF8C07B6",  /* B */
+        "8BD2AEB9CB7E57CB2C4B482FFC81B7AFB9DE27E1E3BD23C23A4453BD9ACE3262",  /* x */
+        "547EF835C3DAC4FD97F8461A14611DC9C27745132DED8E545C1D54C72F046997",  /* y */
+        78,     /* Epl */
+        "A9FB57DBA1EEA9BC3E660A909D838D726E3BF623D52620282013481D1F6E5377",  /* p */
+        78,     /* Eol */
+        "A9FB57DBA1EEA9BC3E660A909D838D718C397AA3B561A6F7901E0E82974856A7",  /* q */
+        256,    /* key_len */
+        7,
+        2,
+        1,
+        CURVE_GF_P
+    },
+    {
+        /* Brainpool: Curve brainpoolP384r1 */
+        CURVE_BP_384,
+        96,     /* Echar */
+        "7BC382C63D8C150C3C72080ACE05AFA0C2BEA28E4FB22787139165EFBA91F90F8AA5814A503AD4EB04A8C7DD22CE2826",  /* A */
+        "04A8C7DD22CE28268B39B55416F0447C2FB77DE107DCD2A62E880EA53EEB62D57CB4390295DBC9943AB78696FA504C11",  /* B */
+        "1D1C64F068CF45FFA2A63A81B7C13F6B8847A3E77EF14FE3DB7FCAFE0CBD10E8E826E03436D646AAEF87B2E247D4AF1E",  /* x */
+        "8ABE1D7520F9C2A45CB1EB8E95CFD55262B70B29FEEC5864E19C054FF99129280E4646217791811142820341263C5315",  /* y */
+        116,     /* Epl */
+        "8CB91E82A3386D280F5D6F7E50E641DF152F7109ED5456B412B1DA197FB71123ACD3A729901D1A71874700133107EC53",  /* p */
+        116,     /* Eol */
+        "8CB91E82A3386D280F5D6F7E50E641DF152F7109ED5456B31F166E6CAC0425A7CF3AB6AF6B7FC3103B883202E9046565",  /* q */
+        384,    /* key_len */
+        7,
+        2,
+        1,
+        CURVE_GF_P
+    },
+    {
+        /* Brainpool: Curve brainpoolP512r1 */
+        CURVE_BP_512,
+        128,     /* Echar */
+        "7830A3318B603B89E2327145AC234CC594CBDD8D3DF91610A83441CAEA9863BC2DED5D5AA8253AA10A2EF1C98B9AC8B57F1117A72BF2C7B9E7C1AC4D77FC94CA",  /* A */
+        "3DF91610A83441CAEA9863BC2DED5D5AA8253AA10A2EF1C98B9AC8B57F1117A72BF2C7B9E7C1AC4D77FC94CADC083E67984050B75EBAE5DD2809BD638016F723",  /* B */
+        "81AEE4BDD82ED9645A21322E9C4C6A9385ED9F70B5D916C1B43B62EEF4D0098EFF3B1F78E2D0D48D50D1687B93B97D5F7C6D5047406A5E688B352209BCB9F822",  /* x */
+        "7DDE385D566332ECC0EABFA9CF7822FDF209F70024A57B1AA000C55B881F8111B2DCDE494A5F485E5BCA4BD88A2763AED1CA2B2FA8F0540678CD1E0F3AD80892",  /* y */
+        156,     /* Epl */
+        "AADD9DB8DBE9C48B3FD4E6AE33C9FC07CB308DB3B3C9D20ED6639CCA703308717D4D9B009BC66842AECDA12AE6A380E62881FF2F2D82C68528AA6056583A48F3",  /* p */
+        156,     /* Eol */
+        "AADD9DB8DBE9C48B3FD4E6AE33C9FC07CB308DB3B3C9D20ED6639CCA70330870553E5C414CA92619418661197FAC10471DB1D381085DDADDB58796829CA90069",  /* q */
+        512,    /* key_len */
+        7,
+        2,
+        1,
+        CURVE_GF_P
+    },
+    {
+        CURVE_25519,
+        64,     // Echar
+        "0000000000000000000000000000000000000000000000000000000000076D06",  // "0000000000000000000000000000000000000000000000000000000000000003",
+        "0000000000000000000000000000000000000000000000000000000000000001",
+        "0000000000000000000000000000000000000000000000000000000000000009",
+        "20ae19a1b8a086b4e01edd2c7748d14c923d4d7e6d7c61b229e9c5a27eced3d9",
+        78,     // Epl
+        "7fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffed",  // "115792089210356248762697446949407573530086143415290314195533631308867097853951",
+        78,     // Eol
+        "1000000000000000000000000000000014def9dea2f79cd65812631a5cf5d3ed",  // "115792089210356248762697446949407573529996955224135760342422259061068512044369",
+        255,    // key_len
+        10,
+        5,
+        2,
+        CURVE_GF_P
+    },
+    {
+        /* NIST: Curve P-256 : y^2=x^3-ax+b (mod p) */
+        CURVE_SM2_256,
+        64,     /* Echar */
+        "FFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFC",  /* a */
+        "28E9FA9E9D9F5E344D5A9E4BCF6509A7F39789F515AB8F92DDBCBD414D940E93",  /* b */
+        "32C4AE2C1F1981195F9904466A39C9948FE30BBFF2660BE1715A4589334C74C7",  /* x */
+        "BC3736A2F4F6779C59BDCEE36B692153D0A9877CC62A474002DF32E52139F0A0",  /* y */
+        78,     /* Epl */
+        "FFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFF",  /* p */
+        78,     /* Eol */
+        "FFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFF7203DF6B21C6052B53BBF40939D54123",  /* n */
+        256,    /* key_len */
+        10,
+        5,
+        2,
+        CURVE_GF_P
+    },
+
+};
+
+
+static ECC_CURVE  *pCurve;
+static ECC_CURVE  Curve_Copy;
+
+static ECC_CURVE * get_curve(E_ECC_CURVE ecc_curve);
+static int32_t ecc_init_curve(CRPT_T *crpt, E_ECC_CURVE ecc_curve);
+static void run_ecc_codec(CRPT_T *crpt, uint32_t mode);
+
+static char  temp_hex_str[160];
+
+static volatile uint32_t g_ECC_done, g_ECCERR_done;
+
+void ECC_DriverISR(CRPT_T *crpt)
+{
+    if(crpt->INTSTS & CRPT_INTSTS_ECCIF_Msk)
+    {
+        g_ECC_done = 1UL;
+        crpt->INTSTS = CRPT_INTSTS_ECCIF_Msk;
+        /* printf("ECC done IRQ.\n"); */
+    }
+
+    if(crpt->INTSTS & CRPT_INTSTS_ECCEIF_Msk)
+    {
+        g_ECCERR_done = 1UL;
+        crpt->INTSTS = CRPT_INTSTS_ECCEIF_Msk;
+        /* printf("ECCERRIF is set!!\n"); */
+    }
+}
+
+
+#if ENABLE_DEBUG
+static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count)
+{
+    int32_t  i;
+
+    printf("%s => ", str);
+    for(i = 0; i < count; i++)
+    {
+        printf("0x%08x ", regs[i]);
+    }
+    printf("\n");
+}
+#else
+static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count)
+{
+    (void)str;
+    (void)regs;
+    (void)count;
+}
+#endif
+static char  ch2hex(char ch)
+{
+    if(ch <= '9')
+    {
+        return ch - '0';
+    }
+    else if((ch <= 'z') && (ch >= 'a'))
+    {
+        return ch - 'a' + 10U;
+    }
+    else
+    {
+        return ch - 'A' + 10U;
+    }
+}
+
+static void Hex2Reg(char input[], uint32_t volatile reg[])
+{
+    char      hex;
+    int       si, ri;
+    uint32_t  i, val32;
+
+    si = (int)strlen(input) - 1;
+    ri = 0;
+
+    while(si >= 0)
+    {
+        val32 = 0UL;
+        for(i = 0UL; (i < 8UL) && (si >= 0); i++)
+        {
+            hex = ch2hex(input[si]);
+            val32 |= (uint32_t)hex << (i * 4UL);
+            si--;
+        }
+        reg[ri++] = val32;
+    }
+}
+
+static void Hex2RegEx(char input[], uint32_t volatile reg[], int shift)
+{
+    uint32_t  hex, carry;
+    int       si, ri;
+    uint32_t  i, val32;
+
+    si = (int)strlen(input) - 1;
+    ri = 0;
+    carry = 0U;
+    while(si >= 0)
+    {
+        val32 = 0UL;
+        for(i = 0UL; (i < 8UL) && (si >= 0); i++)
+        {
+            hex = (uint32_t)ch2hex(input[si]);
+            hex <<= shift;
+
+            val32 |= (uint32_t)((hex & 0xFU) | carry) << (i * 4UL);
+            carry = (hex >> 4) & 0xFU;
+            si--;
+        }
+        reg[ri++] = val32;
+    }
+    if(carry != 0U)
+    {
+        reg[ri] = carry;
+    }
+}
+
+/**
+  * @brief  Extract specified nibble from an unsigned word in character format.
+  *         For example:
+  *                Suppose val32 is 0x786543210, get_Nth_nibble_char(val32, 3) will return a '3'.
+  * @param[in]  val32   The input unsigned word
+  * @param[in]  idx     The Nth nibble to be extracted.
+  * @return  The nibble in character format.
+  */
+static char get_Nth_nibble_char(uint32_t val32, uint32_t idx)
+{
+    return hex_char_tbl[(val32 >> (idx * 4U)) & 0xfU ];
+}
+
+
+static void Reg2Hex(int32_t count, uint32_t volatile reg[], char output[])
+{
+    int32_t    idx, ri;
+    uint32_t   i;
+
+    output[count] = 0U;
+    idx = count - 1;
+
+    for(ri = 0; idx >= 0; ri++)
+    {
+        for(i = 0UL; (i < 8UL) && (idx >= 0); i++)
+        {
+            output[idx] = get_Nth_nibble_char(reg[ri], i);
+            idx--;
+        }
+    }
+}
+
+/**
+  * @brief  Translate registers value into hex string
+  * @param[in]  count   The string length of ouptut hex string.
+  * @param[in]  reg     Register array.
+  * @param[in]  output  String buffer for output hex string.
+  */
+void CRPT_Reg2Hex(int32_t count, volatile uint32_t reg[], char output[])
+{
+    Reg2Hex(count, reg, output);
+}
+
+/**
+  * @brief  Translate hex string to registers value
+  * @param[in]  input   hex string.
+  * @param[in]  reg     Register array.
+  */
+void CRPT_Hex2Reg(char input[], uint32_t volatile reg[])
+{
+    Hex2Reg(input, reg);
+}
+
+
+static int32_t ecc_init_curve(CRPT_T *crpt, E_ECC_CURVE ecc_curve)
+{
+    int32_t  i, ret = 0;
+
+    pCurve = get_curve(ecc_curve);
+    if(pCurve == NULL)
+    {
+        CRPT_DBGMSG("Cannot find curve %d!!\n", ecc_curve);
+        ret = -1;
+    }
+
+    if(ret == 0)
+    {
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_A[i] = 0UL;
+            crpt->ECC_B[i] = 0UL;
+            crpt->ECC_X1[i] = 0UL;
+            crpt->ECC_Y1[i] = 0UL;
+            crpt->ECC_N[i] = 0UL;
+        }
+
+        Hex2Reg(pCurve->Ea, crpt->ECC_A);
+        Hex2Reg(pCurve->Eb, crpt->ECC_B);
+        Hex2Reg(pCurve->Px, crpt->ECC_X1);
+        Hex2Reg(pCurve->Py, crpt->ECC_Y1);
+
+        CRPT_DBGMSG("Key length = %d\n", pCurve->key_len);
+        dump_ecc_reg("CRPT_ECC_CURVE_A", crpt->ECC_A, 10);
+        dump_ecc_reg("CRPT_ECC_CURVE_B", crpt->ECC_B, 10);
+        dump_ecc_reg("CRPT_ECC_POINT_X1", crpt->ECC_X1, 10);
+        dump_ecc_reg("CRPT_ECC_POINT_Y1", crpt->ECC_Y1, 10);
+
+        if(pCurve->GF == (int)CURVE_GF_2M)
+        {
+            crpt->ECC_N[0] = 0x1UL;
+            crpt->ECC_N[(pCurve->key_len) / 32] |= (1UL << ((pCurve->key_len) % 32));
+            crpt->ECC_N[(pCurve->irreducible_k1) / 32] |= (1UL << ((pCurve->irreducible_k1) % 32));
+            crpt->ECC_N[(pCurve->irreducible_k2) / 32] |= (1UL << ((pCurve->irreducible_k2) % 32));
+            crpt->ECC_N[(pCurve->irreducible_k3) / 32] |= (1UL << ((pCurve->irreducible_k3) % 32));
+        }
+        else
+        {
+            Hex2Reg(pCurve->Pp, crpt->ECC_N);
+        }
+    }
+    dump_ecc_reg("CRPT_ECC_CURVE_N", crpt->ECC_N, 10);
+    return ret;
+}
+
+
+static int  get_nibble_value(char c)
+{
+    char ch;
+
+    if((c >= '0') && (c <= '9'))
+    {
+        ch = '0';
+        return ((int)c - (int)ch);
+    }
+
+    if((c >= 'a') && (c <= 'f'))
+    {
+        ch = 'a';
+        return ((int)c - (int)ch + 10);
+    }
+
+    if((c >= 'A') && (c <= 'F'))
+    {
+        ch = 'A';
+        return ((int)c - (int)ch + 10);
+    }
+    return 0;
+}
+
+
+/**
+  * @brief  Check if the private key is located in valid range of curve.
+  * @param[in]  crpt        The pointer of CRYPTO module
+  * @param[in]  ecc_curve   The pre-defined ECC curve.
+  * @param[in]  private_k   The input private key.
+  * @return  1    Is valid.
+  * @return  0    Is not valid.
+  * @return  -1   Invalid curve.
+  */
+int ECC_IsPrivateKeyValid(CRPT_T *crpt, E_ECC_CURVE ecc_curve,  char private_k[])
+{
+    uint32_t  i;
+
+    (void)crpt;
+    pCurve = get_curve(ecc_curve);
+    if(pCurve == NULL)
+    {
+        return -1;
+    }
+
+    if(strlen(private_k) < strlen(pCurve->Eorder))
+    {
+        return 1;
+    }
+
+    if(strlen(private_k) > strlen(pCurve->Eorder))
+    {
+        return 0;
+    }
+
+    for(i = 0U; i < strlen(private_k); i++)
+    {
+        if(get_nibble_value(private_k[i]) < get_nibble_value(pCurve->Eorder[i]))
+        {
+            return 1;
+        }
+
+        if(get_nibble_value(private_k[i]) > get_nibble_value(pCurve->Eorder[i]))
+        {
+            return 0;
+        }
+    }
+    return 0;
+}
+
+
+/**
+  * @brief  Given a private key and curve to generate the public key pair.
+  * @param[in]  crpt        The pointer of CRYPTO module
+  * @param[in]  private_k   The input private key.
+  * @param[in]  ecc_curve   The pre-defined ECC curve.
+  * @param[out] public_k1   The output publick key 1.
+  * @param[out] public_k2   The output publick key 2.
+  * @return  0    Success.
+  * @return  -1   "ecc_curve" value is invalid.
+  */
+int32_t  ECC_GeneratePublicKey(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[])
+{
+    int32_t  ret = 0, i;
+    uint32_t u32Tmp;
+
+    if(ecc_init_curve(crpt, ecc_curve) != 0)
+    {
+        ret = -1;
+    }
+
+    if(ret == 0)
+    {
+        CRPT->ECC_KSCTL = 0;
+
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_K[i] = 0UL;
+        }
+
+        Hex2Reg(private_k, crpt->ECC_K);
+
+        /* set FSEL (Field selection) */
+        if(pCurve->GF == (int)CURVE_GF_2M)
+        {
+            crpt->ECC_CTL = 0UL;
+        }
+        else           /*  CURVE_GF_P */
+        {
+            crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk;
+        }
+
+        g_ECC_done = g_ECCERR_done = 0UL;
+        crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) |
+                         ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk;
+
+        do
+        {
+            u32Tmp = g_ECC_done;
+            u32Tmp |= g_ECCERR_done;
+        }
+        while(u32Tmp == 0UL);
+
+        Reg2Hex(pCurve->Echar, crpt->ECC_X1, public_k1);
+        Reg2Hex(pCurve->Echar, crpt->ECC_Y1, public_k2);
+    }
+
+    return ret;
+}
+
+
+
+
+/**
+  * @brief  Given a private key and curve to generate the public key pair.
+  * @param[in]  crpt        The pointer of CRYPTO module
+  * @param[in]  ecc_curve   The pre-defined ECC curve.
+  * @param[in]  mem         Memory type of Key Store. It could be KS_SRAM, KS_FLASH or KS_OTP.
+  * @param[in]  i32KeyIdx   Index of the key in Key Store.
+  * @param[out] public_k1   The output publick key 1.
+  * @param[out] public_k2   The output publick key 2.
+  * @param[in]  u32ExtraOp  Extra options for ECC_KSCTL register.
+
+  * @return  0    Success.
+  * @return  -1   "ecc_curve" value is invalid.
+  */
+int32_t  ECC_GeneratePublicKey_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve, KS_MEM_Type mem, int32_t i32KeyIdx, char public_k1[], char public_k2[], uint32_t u32ExtraOp)
+{
+    int32_t  ret = 0;
+    uint32_t u32Tmp;
+
+    if(ecc_init_curve(crpt, ecc_curve) != 0)
+    {
+        ret = -1;
+    }
+
+    if(ret == 0)
+    {
+
+        // key from key store
+        crpt->ECC_KSCTL = (uint32_t)(mem << 6)/* KS Memory Type */ |
+                          (CRPT_ECC_KSCTL_RSRCK_Msk)/* Key from KS */ |
+                          u32ExtraOp |
+                          (uint32_t)i32KeyIdx;
+
+        /* set FSEL (Field selection) */
+        if(pCurve->GF == (int)CURVE_GF_2M)
+        {
+            crpt->ECC_CTL = 0UL;
+        }
+        else           /*  CURVE_GF_P */
+        {
+            crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk;
+        }
+
+        g_ECC_done = g_ECCERR_done = 0UL;
+        crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) |
+                         ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk;
+
+        do
+        {
+            u32Tmp = g_ECC_done;
+            u32Tmp |= g_ECCERR_done;
+        }
+        while(u32Tmp == 0UL);
+
+        Reg2Hex(pCurve->Echar, crpt->ECC_X1, public_k1);
+        Reg2Hex(pCurve->Echar, crpt->ECC_Y1, public_k2);
+    }
+
+    return ret;
+}
+
+/**
+  * @brief  Given a private key and curve to generate the public key pair.
+  * @param[in]  crpt        Reference to Crypto module.
+  * @param[out] x1          The x-coordinate of input point.
+  * @param[out] y1          The y-coordinate of input point.
+  * @param[in]  k           The private key
+  * @param[in]  ecc_curve   The pre-defined ECC curve.
+  * @param[out] x2          The x-coordinate of output point.
+  * @param[out] y2          The y-coordinate of output point.
+  * @return  0    Success.
+  * @return  -1   "ecc_curve" value is invalid.
+  */
+int32_t  ECC_Mutiply(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char x1[], char y1[], char *k, char x2[], char y2[])
+{
+    int32_t  i, ret = 0;
+
+    if(ecc_init_curve(crpt, ecc_curve) != 0)
+    {
+        ret = -1;
+    }
+
+    if(ret == 0)
+    {
+        for(i = 0; i < 9; i++)
+        {
+            crpt->ECC_X1[i] = 0UL;
+            crpt->ECC_Y1[i] = 0UL;
+            crpt->ECC_K[i] = 0UL;
+        }
+
+        Hex2Reg(x1, crpt->ECC_X1);
+        Hex2Reg(y1, crpt->ECC_Y1);
+        Hex2Reg(k, crpt->ECC_K);
+
+        /* set FSEL (Field selection) */
+        if(pCurve->GF == (int)CURVE_GF_2M)
+        {
+            crpt->ECC_CTL = 0UL;
+        }
+        else
+        {
+            /*  CURVE_GF_P */
+            crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk;
+        }
+
+        g_ECC_done = g_ECCERR_done = 0UL;
+
+        if(ecc_curve == CURVE_25519)
+        {
+            printf("!! Is curve-25519 !!\n");
+            crpt->ECC_CTL |= CRPT_ECC_CTL_SCAP_Msk;
+            crpt->ECC_CTL |= CRPT_ECC_CTL_CSEL_Msk;
+
+            /* If SCAP enabled, the curve order must be written to ECC_X2 */
+            if(crpt->ECC_CTL & CRPT_ECC_CTL_SCAP_Msk)
+            {
+                Hex2Reg(pCurve->Eorder, crpt->ECC_X2);
+            }
+        }
+
+        crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) |
+                         ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk;
+
+        while((g_ECC_done == 0UL) && (g_ECCERR_done == 0UL))
+        {
+        }
+
+        Reg2Hex(pCurve->Echar, crpt->ECC_X1, x2);
+        Reg2Hex(pCurve->Echar, crpt->ECC_Y1, y2);
+
+    }
+
+    return ret;
+}
+
+
+/**
+  * @brief  Given a curve parameter, the other party's public key, and one's own private key to generate the secret Z.
+  * @param[in]  crpt        The pointer of CRYPTO module
+  * @param[in]  ecc_curve   The pre-defined ECC curve.
+  * @param[in]  private_k   One's own private key.
+  * @param[in]  public_k1   The other party's publick key 1.
+  * @param[in]  public_k2   The other party's publick key 2.
+  * @param[out] secret_z    The ECC CDH secret Z.
+  * @return  0    Success.
+  * @return  -1   "ecc_curve" value is invalid.
+  */
+int32_t  ECC_GenerateSecretZ(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[], char secret_z[])
+{
+    int32_t  i, ret = 0;
+    uint32_t u32Tmp;
+
+    if(ecc_init_curve(crpt, ecc_curve) != 0)
+    {
+        ret = -1;
+    }
+
+    if(ret == 0)
+    {
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_K[i] = 0UL;
+            crpt->ECC_X1[i] = 0UL;
+            crpt->ECC_Y1[i] = 0UL;
+        }
+
+        if((ecc_curve == CURVE_B_163) || (ecc_curve == CURVE_B_233) || (ecc_curve == CURVE_B_283) ||
+                (ecc_curve == CURVE_B_409) || (ecc_curve == CURVE_B_571) || (ecc_curve == CURVE_K_163))
+        {
+            Hex2RegEx(private_k, crpt->ECC_K, 1);
+        }
+        else if((ecc_curve == CURVE_K_233) || (ecc_curve == CURVE_K_283) ||
+                (ecc_curve == CURVE_K_409) || (ecc_curve == CURVE_K_571))
+        {
+            Hex2RegEx(private_k, crpt->ECC_K, 2);
+        }
+        else
+        {
+            Hex2Reg(private_k, crpt->ECC_K);
+        }
+
+        Hex2Reg(public_k1, crpt->ECC_X1);
+        Hex2Reg(public_k2, crpt->ECC_Y1);
+
+        /* set FSEL (Field selection) */
+        if(pCurve->GF == (int)CURVE_GF_2M)
+        {
+            crpt->ECC_CTL = 0UL;
+        }
+        else           /*  CURVE_GF_P */
+        {
+            crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk;
+        }
+        g_ECC_done = g_ECCERR_done = 0UL;
+        crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) |
+                         ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk;
+
+        do
+        {
+            u32Tmp = g_ECC_done;
+            u32Tmp |= g_ECCERR_done;
+        }
+        while(u32Tmp == 0UL);
+
+        Reg2Hex(pCurve->Echar, crpt->ECC_X1, secret_z);
+    }
+
+    return ret;
+}
+
+
+/**
+  * @brief  Given a curve parameter, the other party's public key, and one's own private key to generate the secret Z.
+  * @param[in]  crpt        The pointer of CRYPTO module
+  * @param[in]  ecc_curve   The pre-defined ECC curve.
+  * @param[in]  private_k   One's own private key.
+  * @param[in]  public_k1   The other party's publick key 1.
+  * @param[in]  public_k2   The other party's publick key 2.
+  * @param[out] secret_z    The ECC CDH secret Z.
+  * @return  0    Success.
+  * @return  -1   "ecc_curve" value is invalid.
+  */
+int32_t ECC_GenerateSecretZ_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve, KS_MEM_Type mem, int32_t i32KeyIdx, char public_k1[], char public_k2[])
+{
+    int32_t  i;
+    uint32_t u32Tmp;
+
+    if(ecc_init_curve(crpt, ecc_curve) != 0)
+    {
+        return -1;
+    }
+
+    for(i = 0; i < 18; i++)
+    {
+        crpt->ECC_K[i] = 0UL;
+        crpt->ECC_X1[i] = 0UL;
+        crpt->ECC_Y1[i] = 0UL;
+    }
+
+    crpt->ECC_KSCTL = CRPT_ECC_KSCTL_ECDH_Msk | CRPT_ECC_KSCTL_RSRCK_Msk |
+                      (uint32_t)(mem << CRPT_ECC_KSCTL_RSSRCK_Pos)/* KS Memory Type */ |
+                      (uint32_t)i32KeyIdx;
+
+    Hex2Reg(public_k1, crpt->ECC_X1);
+    Hex2Reg(public_k2, crpt->ECC_Y1);
+
+    /* set FSEL (Field selection) */
+    if(pCurve->GF == (int)CURVE_GF_2M)
+    {
+        crpt->ECC_CTL = 0UL;
+    }
+    else /*  CURVE_GF_P */
+    {
+        crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk;
+    }
+
+    g_ECC_done = g_ECCERR_done = 0UL;
+
+    crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) |
+                     ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk;
+
+    do
+    {
+        u32Tmp = g_ECC_done;
+        u32Tmp |= g_ECCERR_done;
+    }
+    while(u32Tmp == 0UL);
+
+    if(g_ECCERR_done)
+        return -1;
+
+    return (crpt->ECC_KSSTS & 0x1f);
+
+}
+
+
+static void run_ecc_codec(CRPT_T *crpt, uint32_t mode)
+{
+    uint32_t u32Tmp;
+    uint32_t eccop;
+
+    eccop = mode & CRPT_ECC_CTL_ECCOP_Msk;
+    if(eccop == ECCOP_MODULE)
+    {
+        crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk;
+    }
+    else
+    {
+        if(pCurve->GF == (int)CURVE_GF_2M)
+        {
+            /* point */
+            crpt->ECC_CTL = 0UL;
+        }
+        else
+        {
+            /* CURVE_GF_P */
+            crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk;
+        }
+
+#ifdef ECC_SCA_PROTECT
+        if(eccop == ECCOP_POINT_MUL)
+        {
+            /* Enable side-channel protection in some operation */
+            crpt->ECC_CTL |= CRPT_ECC_CTL_SCAP_Msk;
+            /* If SCAP enabled, the curve order must be written to ECC_X2 */
+            Hex2Reg(pCurve->Eorder, crpt->ECC_X2);
+        }
+#endif
+
+    }
+
+    g_ECC_done = g_ECCERR_done = 0UL;
+
+    crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) | mode | CRPT_ECC_CTL_START_Msk;
+
+    do
+    {
+        u32Tmp = g_ECC_done;
+        u32Tmp |= g_ECCERR_done;
+    }
+    while(u32Tmp == 0UL);
+
+    while(crpt->ECC_STS & CRPT_ECC_STS_BUSY_Msk) { }
+}
+
+/**
+  * @brief  ECDSA digital signature generation.
+  * @param[in]  crpt        The pointer of CRYPTO module
+  * @param[in]  ecc_curve   The pre-defined ECC curve.
+  * @param[in]  message     The hash value of source context.
+  * @param[in]  d           The private key.
+  * @param[in]  k           The selected random integer.
+  * @param[out] R           R of the (R,S) pair digital signature
+  * @param[out] S           S of the (R,S) pair digital signature
+  * @return  0    Success.
+  * @return  -1   "ecc_curve" value is invalid.
+  */
+int32_t  ECC_GenerateSignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
+                               char *d, char *k, char *R, char *S)
+{
+    uint32_t volatile temp_result1[18], temp_result2[18];
+    int32_t  i, ret = 0;
+
+    if(ecc_init_curve(crpt, ecc_curve) != 0)
+    {
+        ret = -1;
+    }
+
+    if(ret == 0)
+    {
+        CRPT->ECC_KSCTL = 0;
+
+        /*
+         *   1. Calculate e = HASH(m), where HASH is a cryptographic hashing algorithm, (i.e. SHA-1)
+         *      (1) Use SHA to calculate e
+         */
+
+        /*   2. Select a random integer k form [1, n-1]
+         *      (1) Notice that n is order, not prime modulus or irreducible polynomial function
+         */
+
+        /*
+         *   3. Compute r = x1 (mod n), where (x1, y1) = k * G. If r = 0, go to step 2
+         *      (1) Write the curve parameter A, B, and curve length M to corresponding registers
+         *      (2) Write the prime modulus or irreducible polynomial function to N registers according
+         *      (3) Write the point G(x, y) to X1, Y1 registers
+         *      (4) Write the random integer k to K register
+         *      (5) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00
+         *      (6) Set FSEL(CRPT_ECC_CTL[8]) according to used curve of prime field or binary field
+         *      (7) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (8) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (9) Write the curve order and curve length to N ,M registers according
+         *      (10) Write 0x0 to Y1 registers
+         *      (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+         *      (12) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10
+         *      (13) Set START(CRPT_ECC_CTL[0]) to 1         *
+         *      (14) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (15) Read X1 registers to get r
+         */
+
+        /* 3-(4) Write the random integer k to K register */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_K[i] = 0UL;
+        }
+        Hex2Reg(k, crpt->ECC_K);
+
+        run_ecc_codec(crpt, ECCOP_POINT_MUL);
+
+        /*  3-(9) Write the curve order to N registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_N[i] = 0UL;
+        }
+        Hex2Reg(pCurve->Eorder, crpt->ECC_N);
+
+        /* 3-(10) Write 0x0 to Y1 registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_Y1[i] = 0UL;
+        }
+
+        run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD);
+
+        /* 3-(15) Read X1 registers to get r */
+        for(i = 0; i < 18; i++)
+        {
+            temp_result1[i] = crpt->ECC_X1[i];
+        }
+
+        Reg2Hex(pCurve->Echar, temp_result1, R);
+
+        /*
+         *   4. Compute s = k^-1 * (e + d * r)(mod n). If s = 0, go to step 2
+         *      (1) Write the curve order to N registers according
+         *      (2) Write 0x1 to Y1 registers
+         *      (3) Write the random integer k to X1 registers according
+         *      (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+         *      (5) Set MOPOP(CRPT_ECC_CTL[12:11]) to 00
+         *      (6) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (7) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (8) Read X1 registers to get k^-1
+         *      (9) Write the curve order and curve length to N ,M registers
+         *      (10) Write r, d to X1, Y1 registers
+         *      (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+         *      (12) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01
+         *      (13) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (14) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (15) Write the curve order to N registers
+         *      (16) Write e to Y1 registers
+         *      (17) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+         *      (18) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10
+         *      (19) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (20) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (21) Write the curve order and curve length to N ,M registers
+         *      (22) Write k^-1 to Y1 registers
+         *      (23) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+         *      (24) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01
+         *      (25) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (26) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (27) Read X1 registers to get s
+         */
+
+        /* S/W: GFp_add_mod_order(pCurve->key_len+2, 0, x1, a, R); */
+
+        /*  4-(1) Write the curve order to N registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_N[i] = 0UL;
+        }
+        Hex2Reg(pCurve->Eorder, crpt->ECC_N);
+
+        /*  4-(2) Write 0x1 to Y1 registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_Y1[i] = 0UL;
+        }
+        crpt->ECC_Y1[0] = 0x1UL;
+
+        /*  4-(3) Write the random integer k to X1 registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_X1[i] = 0UL;
+        }
+        Hex2Reg(k, crpt->ECC_X1);
+
+        run_ecc_codec(crpt, ECCOP_MODULE | MODOP_DIV);
+
+#if ENABLE_DEBUG
+        Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str);
+        CRPT_DBGMSG("(7) output = %s\n", temp_hex_str);
+#endif
+
+        /*  4-(8) Read X1 registers to get k^-1 */
+
+        for(i = 0; i < 18; i++)
+        {
+            temp_result2[i] = crpt->ECC_X1[i];
+        }
+
+#if ENABLE_DEBUG
+        Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str);
+        CRPT_DBGMSG("k^-1 = %s\n", temp_hex_str);
+#endif
+
+        /*  4-(9) Write the curve order and curve length to N ,M registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_N[i] = 0UL;
+        }
+        Hex2Reg(pCurve->Eorder, crpt->ECC_N);
+
+        /*  4-(10) Write r, d to X1, Y1 registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_X1[i] = temp_result1[i];
+        }
+
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_Y1[i] = 0UL;
+        }
+        Hex2Reg(d, crpt->ECC_Y1);
+
+        run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL);
+
+#if ENABLE_DEBUG
+        Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str);
+        CRPT_DBGMSG("(14) output = %s\n", temp_hex_str);
+#endif
+
+        /*  4-(15) Write the curve order to N registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_N[i] = 0UL;
+        }
+        Hex2Reg(pCurve->Eorder, crpt->ECC_N);
+
+        /*  4-(16) Write e to Y1 registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_Y1[i] = 0UL;
+        }
+
+        Hex2Reg(message, crpt->ECC_Y1);
+
+        run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD);
+
+#if ENABLE_DEBUG
+        Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str);
+        CRPT_DBGMSG("(20) output = %s\n", temp_hex_str);
+#endif
+
+        /*  4-(21) Write the curve order and curve length to N ,M registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_N[i] = 0UL;
+        }
+        Hex2Reg(pCurve->Eorder, crpt->ECC_N);
+
+        /*  4-(22) Write k^-1 to Y1 registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_Y1[i] = temp_result2[i];
+        }
+
+        run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL);
+
+        /*  4-(27) Read X1 registers to get s */
+        for(i = 0; i < 18; i++)
+        {
+            temp_result2[i] = crpt->ECC_X1[i];
+        }
+
+        Reg2Hex(pCurve->Echar, temp_result2, S);
+
+    }  /* ret == 0 */
+
+    return ret;
+}
+
+
+
+/**
+  * @brief  ECDSA digital signature generation.
+  * @param[in]  crpt        The pointer of CRYPTO module
+  * @param[in]  ecc_curve   The pre-defined ECC curve.
+  * @param[in]  message     The hash value of source context.
+  * @param[in]  d           The private key.
+  * @param[in]  k           The selected random integer.
+  * @param[out] R           R of the (R,S) pair digital signature
+  * @param[out] S           S of the (R,S) pair digital signature
+  * @return  0    Success.
+  * @return  -1   "ecc_curve" value is invalid.
+  */
+int32_t  ECC_GenerateSignature_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, KS_MEM_Type mem_d, int32_t i32KeyIdx_d, KS_MEM_Type mem_k, int32_t i32KeyIdx_k, char *R, char *S)
+{
+    uint32_t volatile temp_result1[18], temp_result2[18];
+    int32_t  i, ret = 0;
+
+    if(ecc_init_curve(crpt, ecc_curve) != 0)
+    {
+        ret = -1;
+    }
+
+    if(ret == 0)
+    {
+        CRPT->ECC_KSCTL = 0;
+        CRPT->ECC_KSXY  = 0;
+
+        /*
+         *   1. Calculate e = HASH(m), where HASH is a cryptographic hashing algorithm, (i.e. SHA-1)
+         *      (1) Use SHA to calculate e
+         */
+
+        /*   2. Select a random integer k form [1, n-1]
+         *      (1) Notice that n is order, not prime modulus or irreducible polynomial function
+         */
+
+        /*
+         *   3. Compute r = x1 (mod n), where (x1, y1) = k * G. If r = 0, go to step 2
+         *      (1) Write the curve parameter A, B, and curve length M to corresponding registers
+         *      (2) Write the prime modulus or irreducible polynomial function to N registers according
+         *      (3) Write the point G(x, y) to X1, Y1 registers
+         *      (4) Write the random integer k to K register
+         *      (5) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00
+         *      (6) Set FSEL(CRPT_ECC_CTL[8]) according to used curve of prime field or binary field
+         *      (7) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (8) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (9) Write the curve order and curve length to N ,M registers according
+         *      (10) Write 0x0 to Y1 registers
+         *      (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+         *      (12) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10
+         *      (13) Set START(CRPT_ECC_CTL[0]) to 1         *
+         *      (14) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (15) Read X1 registers to get r
+         */
+
+        /* 3-(4) Use k in Key Store */
+        crpt->ECC_KSCTL = (uint32_t)(mem_k << CRPT_ECC_KSCTL_RSSRCK_Pos)/* KS Memory Type */ |
+                          CRPT_ECC_KSCTL_RSRCK_Msk/* Key from KS */ |
+                          (uint32_t)i32KeyIdx_k;
+
+        run_ecc_codec(crpt, ECCOP_POINT_MUL | OP_ECDSAR);
+
+        /*  3-(9) Write the curve order to N registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_N[i] = 0UL;
+        }
+        Hex2Reg(pCurve->Eorder, crpt->ECC_N);
+
+        /* 3-(10) Write 0x0 to Y1 registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_Y1[i] = 0UL;
+        }
+
+        run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD);
+
+        /* 3-(15) Read X1 registers to get r */
+        for(i = 0; i < 18; i++)
+        {
+            temp_result1[i] = crpt->ECC_X1[i];
+        }
+
+        Reg2Hex(pCurve->Echar, temp_result1, R);
+
+
+        /*
+         *   4. Compute s = k ^-1 * (e + d * r)(mod n). If s = 0, go to step 2
+         *      (1) Write the curve order to N registers according
+         *      (2) Write 0x1 to Y1 registers
+         *      (3) Write the random integer k to X1 registers according
+         *      (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+         *      (5) Set MOPOP(CRPT_ECC_CTL[12:11]) to 00
+         *      (6) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (7) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (8) Read X1 registers to get k^-1
+         *      (9) Write the curve order and curve length to N ,M registers
+         *      (10) Write r, d to X1, Y1 registers
+         *      (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+         *      (12) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01
+         *      (13) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (14) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (15) Write the curve order to N registers
+         *      (16) Write e to Y1 registers
+         *      (17) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+         *      (18) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10
+         *      (19) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (20) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (21) Write the curve order and curve length to N ,M registers
+         *      (22) Write k^-1 to Y1 registers
+         *      (23) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+         *      (24) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01
+         *      (25) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (26) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (27) Read X1 registers to get s
+         */
+
+        /* S/W: GFp_add_mod_order(pCurve->key_len+2, 0, x1, a, R); */
+
+        /*  4-(1) Write the curve order to N registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_N[i] = 0UL;
+        }
+        Hex2Reg(pCurve->Eorder, crpt->ECC_N);
+
+        /* 4-(2)(3)(4)(5) Use d, k in Key Store */
+        crpt->ECC_CTL = 0;
+        crpt->ECC_KSXY = CRPT_ECC_KSXY_RSRCXY_Msk |
+                         (uint32_t)(mem_k << CRPT_ECC_KSXY_RSSRCX_Pos) | ((uint32_t)i32KeyIdx_k << CRPT_ECC_KSXY_NUMX_Pos) | // Key Store index of k
+                         (uint32_t)(mem_d << CRPT_ECC_KSXY_RSSRCY_Pos) | ((uint32_t)i32KeyIdx_d << CRPT_ECC_KSXY_NUMY_Pos);  // Key Store index of d
+
+        // 4-5
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_X2[i] = temp_result1[i];
+            crpt->ECC_Y2[i] = 0;
+        }
+        Hex2Reg(message, crpt->ECC_Y2);
+
+        run_ecc_codec(crpt, ECCOP_MODULE | OP_ECDSAS);
+
+        /*  4-11 Read X1 registers to get s */
+        for(i = 0; i < 18; i++)
+        {
+            temp_result2[i] = crpt->ECC_X1[i];
+        }
+        Reg2Hex(pCurve->Echar, temp_result2, S);
+
+        /* Clear KS Control */
+        CRPT->ECC_KSCTL = 0;
+        CRPT->ECC_KSXY = 0;
+
+    }  /* ret == 0 */
+
+    return ret;
+}
+
+
+/**
+  * @brief  ECDSA dogotal signature verification.
+  * @param[in]  crpt        The pointer of CRYPTO module
+  * @param[in]  ecc_curve   The pre-defined ECC curve.
+  * @param[in]  message     The hash value of source context.
+  * @param[in]  public_k1   The public key 1.
+  * @param[in]  public_k2   The public key 2.
+  * @param[in]  R           R of the (R,S) pair digital signature
+  * @param[in]  S           S of the (R,S) pair digital signature
+  * @return  0    Success.
+  * @return  -1   "ecc_curve" value is invalid.
+  * @return  -2   Verification failed.
+  */
+int32_t  ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
+                             char *public_k1, char *public_k2, char *R, char *S)
+{
+    uint32_t  temp_result1[18], temp_result2[18];
+    uint32_t  temp_x[18], temp_y[18];
+    int32_t   i, ret = 0;
+
+    /*
+     *   1. Verify that r and s are integers in the interval [1, n-1]. If not, the signature is invalid
+     *   2. Compute e = HASH (m), where HASH is the hashing algorithm in signature generation
+     *      (1) Use SHA to calculate e
+     */
+
+    /*
+     *   3. Compute w = s^-1 (mod n)
+     *      (1) Write the curve order to N registers
+     *      (2) Write 0x1 to Y1 registers
+     *      (3) Write s to X1 registers
+     *      (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+     *      (5) Set MOPOP(CRPT_ECC_CTL[12:11]) to 00
+     *      (6) Set FSEL(CRPT_ECC_CTL[8]) according to used curve of prime field or binary field
+     *      (7) Set START(CRPT_ECC_CTL[0]) to 1
+     *      (8) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+     *      (9) Read X1 registers to get w
+     */
+
+    if(ecc_init_curve(crpt, ecc_curve) != 0)
+    {
+        ret = -1;
+    }
+
+    if(ret == 0)
+    {
+
+        /*  3-(1) Write the curve order to N registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_N[i] = 0UL;
+        }
+        Hex2Reg(pCurve->Eorder, crpt->ECC_N);
+
+        /*  3-(2) Write 0x1 to Y1 registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_Y1[i] = 0UL;
+        }
+        crpt->ECC_Y1[0] = 0x1UL;
+
+        /*  3-(3) Write s to X1 registers */
+        for(i = 0; i < 18; i++)
+        {
+            CRPT->ECC_X1[i] = 0UL;
+        }
+        Hex2Reg(S, crpt->ECC_X1);
+
+        run_ecc_codec(crpt, ECCOP_MODULE | MODOP_DIV);
+
+        /*  3-(9) Read X1 registers to get w */
+        for(i = 0; i < 18; i++)
+        {
+            temp_result2[i] = crpt->ECC_X1[i];
+        }
+
+#if ENABLE_DEBUG
+        CRPT_DBGMSG("e = %s\n", message);
+        Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str);
+        CRPT_DBGMSG("w = %s\n", temp_hex_str);
+        CRPT_DBGMSG("o = %s (order)\n", pCurve->Eorder);
+#endif
+
+        /*
+         *   4. Compute u1 = e * w (mod n) and u2 = r * w (mod n)
+         *      (1) Write the curve order and curve length to N ,M registers
+         *      (2) Write e, w to X1, Y1 registers
+         *      (3) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+         *      (4) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01
+         *      (5) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (6) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (7) Read X1 registers to get u1
+         *      (8) Write the curve order and curve length to N ,M registers
+         *      (9) Write r, w to X1, Y1 registers
+         *      (10) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+         *      (11) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01
+         *      (12) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (13) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (14) Read X1 registers to get u2
+         */
+
+        /*  4-(1) Write the curve order and curve length to N ,M registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_N[i] = 0UL;
+        }
+        Hex2Reg(pCurve->Eorder, crpt->ECC_N);
+
+        /* 4-(2) Write e, w to X1, Y1 registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_X1[i] = 0UL;
+        }
+        Hex2Reg(message, crpt->ECC_X1);
+
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_Y1[i] = temp_result2[i];
+        }
+
+        run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL);
+
+        /*  4-(7) Read X1 registers to get u1 */
+        for(i = 0; i < 18; i++)
+        {
+            temp_result1[i] = crpt->ECC_X1[i];
+        }
+
+#if ENABLE_DEBUG
+        Reg2Hex(pCurve->Echar, temp_result1, temp_hex_str);
+        CRPT_DBGMSG("u1 = %s\n", temp_hex_str);
+#endif
+
+        /*  4-(8) Write the curve order and curve length to N ,M registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_N[i] = 0UL;
+        }
+        Hex2Reg(pCurve->Eorder, crpt->ECC_N);
+
+        /* 4-(9) Write r, w to X1, Y1 registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_X1[i] = 0UL;
+        }
+        Hex2Reg(R, crpt->ECC_X1);
+
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_Y1[i] = temp_result2[i];
+        }
+
+        run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL);
+
+        /*  4-(14) Read X1 registers to get u2 */
+        for(i = 0; i < 18; i++)
+        {
+            temp_result2[i] = crpt->ECC_X1[i];
+        }
+
+#if ENABLE_DEBUG
+        Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str);
+        CRPT_DBGMSG("u2 = %s\n", temp_hex_str);
+#endif
+
+        /*
+         *   5. Compute X * (x1', y1') = u1 * G + u2 * Q
+         *      (1) Write the curve parameter A, B, N, and curve length M to corresponding registers
+         *      (2) Write the point G(x, y) to X1, Y1 registers
+         *      (3) Write u1 to K registers
+         *      (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00
+         *      (5) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (6) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (7) Read X1, Y1 registers to get u1*G
+         *      (8) Write the curve parameter A, B, N, and curve length M to corresponding registers
+         *      (9) Write the public key Q(x,y) to X1, Y1 registers
+         *      (10) Write u2 to K registers
+         *      (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00
+         *      (12) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (13) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (14) Write the curve parameter A, B, N, and curve length M to corresponding registers
+         *      (15) Write the result data u1*G to X2, Y2 registers
+         *      (16) Set ECCOP(CRPT_ECC_CTL[10:9]) to 10
+         *      (17) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (18) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (19) Read X1, Y1 registers to get X *(x1', y1')
+         *      (20) Write the curve order and curve length to N ,M registers
+         *      (21) Write x1 * to X1 registers
+         *      (22) Write 0x0 to Y1 registers
+         *      (23) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+         *      (24) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10
+         *      (25) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (26) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (27) Read X1 registers to get x1 * (mod n)
+         *
+         *   6. The signature is valid if x1 * = r, otherwise it is invalid
+         */
+
+        /*
+         *  (1) Write the curve parameter A, B, N, and curve length M to corresponding registers
+         *  (2) Write the point G(x, y) to X1, Y1 registers
+         */
+        ecc_init_curve(crpt, ecc_curve);
+
+        /* (3) Write u1 to K registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_K[i] = temp_result1[i];
+        }
+
+        run_ecc_codec(crpt, ECCOP_POINT_MUL);
+
+        /* (7) Read X1, Y1 registers to get u1*G */
+        for(i = 0; i < 18; i++)
+        {
+            temp_x[i] = crpt->ECC_X1[i];
+            temp_y[i] = crpt->ECC_Y1[i];
+        }
+
+#if ENABLE_DEBUG
+        Reg2Hex(pCurve->Echar, temp_x, temp_hex_str);
+        CRPT_DBGMSG("5-(7) u1*G, x = %s\n", temp_hex_str);
+        Reg2Hex(pCurve->Echar, temp_y, temp_hex_str);
+        CRPT_DBGMSG("5-(7) u1*G, y = %s\n", temp_hex_str);
+#endif
+
+        /* (8) Write the curve parameter A, B, N, and curve length M to corresponding registers */
+        ecc_init_curve(crpt, ecc_curve);
+
+        /* (9) Write the public key Q(x,y) to X1, Y1 registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_X1[i] = 0UL;
+            crpt->ECC_Y1[i] = 0UL;
+        }
+
+        Hex2Reg(public_k1, crpt->ECC_X1);
+        Hex2Reg(public_k2, crpt->ECC_Y1);
+
+        /* (10) Write u2 to K registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_K[i] = temp_result2[i];
+        }
+
+        run_ecc_codec(crpt, ECCOP_POINT_MUL);
+
+        for(i = 0; i < 18; i++)
+        {
+            temp_result1[i] = crpt->ECC_X1[i];
+            temp_result2[i] = crpt->ECC_Y1[i];
+        }
+
+#if ENABLE_DEBUG
+        Reg2Hex(pCurve->Echar, temp_result1, temp_hex_str);
+        CRPT_DBGMSG("5-(13) u2*Q, x = %s\n", temp_hex_str);
+        Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str);
+        CRPT_DBGMSG("5-(13) u2*Q, y = %s\n", temp_hex_str);
+#endif
+
+        /* (14) Write the curve parameter A, B, N, and curve length M to corresponding registers */
+        ecc_init_curve(crpt, ecc_curve);
+
+        /* Write the result data u2*Q to X1, Y1 registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_X1[i] = temp_result1[i];
+            crpt->ECC_Y1[i] = temp_result2[i];
+        }
+
+        /* (15) Write the result data u1*G to X2, Y2 registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_X2[i] = temp_x[i];
+            crpt->ECC_Y2[i] = temp_y[i];
+        }
+
+        run_ecc_codec(crpt, ECCOP_POINT_ADD);
+
+        /* (19) Read X1, Y1 registers to get X * (x1', y1') */
+        for(i = 0; i < 18; i++)
+        {
+            temp_x[i] = crpt->ECC_X1[i];
+            temp_y[i] = crpt->ECC_Y1[i];
+        }
+
+#if ENABLE_DEBUG
+        Reg2Hex(pCurve->Echar, temp_x, temp_hex_str);
+        CRPT_DBGMSG("5-(19) x' = %s\n", temp_hex_str);
+        Reg2Hex(pCurve->Echar, temp_y, temp_hex_str);
+        CRPT_DBGMSG("5-(19) y' = %s\n", temp_hex_str);
+#endif
+
+        /*  (20) Write the curve order and curve length to N ,M registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_N[i] = 0UL;
+        }
+        Hex2Reg(pCurve->Eorder, crpt->ECC_N);
+
+        /*
+         *  (21) Write x1 * to X1 registers
+         *  (22) Write 0x0 to Y1 registers
+         */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_X1[i] = temp_x[i];
+            crpt->ECC_Y1[i] = 0UL;
+        }
+
+#if ENABLE_DEBUG
+        Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str);
+        CRPT_DBGMSG("5-(21) x' = %s\n", temp_hex_str);
+        Reg2Hex(pCurve->Echar, crpt->ECC_Y1, temp_hex_str);
+        CRPT_DBGMSG("5-(22) y' = %s\n", temp_hex_str);
+#endif
+
+        run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD);
+
+        /*  (27) Read X1 registers to get x1 * (mod n) */
+        Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str);
+        CRPT_DBGMSG("5-(27) x1' (mod n) = %s\n", temp_hex_str);
+
+        /* 6. The signature is valid if x1 * = r, otherwise it is invalid */
+
+        /* Compare with test pattern to check if r is correct or not */
+        if(strcasecmp(temp_hex_str, R) != 0)
+        {
+            CRPT_DBGMSG("x1' (mod n) != R Test filed!!\n");
+            CRPT_DBGMSG("Signature R [%s] is not matched with expected R [%s]!\n", temp_hex_str, R);
+            ret = -2;
+        }
+    }  /* ret == 0 */
+
+    return ret;
+}
+
+
+
+/**
+  * @brief  ECDSA signature verification with Key Store
+  * @param[in]  crpt        The pointer of CRYPTO module
+  * @param[in]  ecc_curve   The pre-defined ECC curve.
+  * @param[in]  message     The hash value of source context.
+  * @param[in]  public_k1   The public key 1.
+  * @param[in]  public_k2   The public key 2.
+  * @param[in]  R           R of the (R,S) pair digital signature
+  * @param[in]  S           S of the (R,S) pair digital signature
+  * @return  0    Success.
+  * @return  -1   "ecc_curve" value is invalid.
+  * @return  -2   Verification failed.
+  */
+int32_t  ECC_VerifySignature_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, KS_MEM_Type mem_pk1, int32_t i32KeyIdx_pk1, KS_MEM_Type mem_pk2, int32_t i32KeyIdx_pk2, char *R, char *S)
+{
+    uint32_t  temp_result1[18], temp_result2[18];
+    uint32_t  temp_x[18], temp_y[18];
+    int32_t   i, ret = 0;
+
+    /*
+     *   1. Verify that r and s are integers in the interval [1, n-1]. If not, the signature is invalid
+     *   2. Compute e = HASH (m), where HASH is the hashing algorithm in signature generation
+     *      (1) Use SHA to calculate e
+     */
+
+    /*
+     *   3. Compute w = s^-1 (mod n)
+     *      (1) Write the curve order to N registers
+     *      (2) Write 0x1 to Y1 registers
+     *      (3) Write s to X1 registers
+     *      (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+     *      (5) Set MOPOP(CRPT_ECC_CTL[12:11]) to 00
+     *      (6) Set FSEL(CRPT_ECC_CTL[8]) according to used curve of prime field or binary field
+     *      (7) Set START(CRPT_ECC_CTL[0]) to 1
+     *      (8) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+     *      (9) Read X1 registers to get w
+     */
+
+    if(ecc_init_curve(crpt, ecc_curve) != 0)
+    {
+        ret = -1;
+    }
+
+    if(ret == 0)
+    {
+        crpt->ECC_KSCTL = 0;
+        crpt->ECC_KSXY  = 0;
+
+        /*  3-(1) Write the curve order to N registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_N[i] = 0UL;
+        }
+        Hex2Reg(pCurve->Eorder, crpt->ECC_N);
+
+        /*  3-(2) Write 0x1 to Y1 registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_Y1[i] = 0UL;
+        }
+        crpt->ECC_Y1[0] = 0x1UL;
+
+        /*  3-(3) Write s to X1 registers */
+        for(i = 0; i < 18; i++)
+        {
+            CRPT->ECC_X1[i] = 0UL;
+        }
+        Hex2Reg(S, crpt->ECC_X1);
+
+        run_ecc_codec(crpt, ECCOP_MODULE | MODOP_DIV);
+
+        /*  3-(9) Read X1 registers to get w */
+        for(i = 0; i < 18; i++)
+        {
+            temp_result2[i] = crpt->ECC_X1[i];
+        }
+
+#if ENABLE_DEBUG
+        CRPT_DBGMSG("e = %s\n", message);
+        Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str);
+        CRPT_DBGMSG("w = %s\n", temp_hex_str);
+        CRPT_DBGMSG("o = %s (order)\n", pCurve->Eorder);
+#endif
+
+        /*
+         *   4. Compute u1 = e  * w (mod n) and u2 = r  * w (mod n)
+         *      (1) Write the curve order and curve length to N ,M registers
+         *      (2) Write e, w to X1, Y1 registers
+         *      (3) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+         *      (4) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01
+         *      (5) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (6) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (7) Read X1 registers to get u1
+         *      (8) Write the curve order and curve length to N ,M registers
+         *      (9) Write r, w to X1, Y1 registers
+         *      (10) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+         *      (11) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01
+         *      (12) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (13) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (14) Read X1 registers to get u2
+         */
+
+        /*  4-(1) Write the curve order and curve length to N ,M registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_N[i] = 0UL;
+        }
+        Hex2Reg(pCurve->Eorder, crpt->ECC_N);
+
+        /* 4-(2) Write e, w to X1, Y1 registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_X1[i] = 0UL;
+        }
+        Hex2Reg(message, crpt->ECC_X1);
+
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_Y1[i] = temp_result2[i];
+        }
+
+        run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL);
+
+        /*  4-(7) Read X1 registers to get u1 */
+        for(i = 0; i < 18; i++)
+        {
+            temp_result1[i] = crpt->ECC_X1[i];
+        }
+
+#if ENABLE_DEBUG
+        Reg2Hex(pCurve->Echar, temp_result1, temp_hex_str);
+        CRPT_DBGMSG("u1 = %s\n", temp_hex_str);
+#endif
+
+        /*  4-(8) Write the curve order and curve length to N ,M registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_N[i] = 0UL;
+        }
+        Hex2Reg(pCurve->Eorder, crpt->ECC_N);
+
+        /* 4-(9) Write r, w to X1, Y1 registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_X1[i] = 0UL;
+        }
+        Hex2Reg(R, crpt->ECC_X1);
+
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_Y1[i] = temp_result2[i];
+        }
+
+        run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL);
+
+        /*  4-(14) Read X1 registers to get u2 */
+        for(i = 0; i < 18; i++)
+        {
+            temp_result2[i] = crpt->ECC_X1[i];
+        }
+
+#if ENABLE_DEBUG
+        Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str);
+        CRPT_DBGMSG("u2 = %s\n", temp_hex_str);
+#endif
+
+        /*
+         *   5. Compute X * (x1', y1') = u1 * G + u2 * Q
+         *      (1) Write the curve parameter A, B, N, and curve length M to corresponding registers
+         *      (2) Write the point G(x, y) to X1, Y1 registers
+         *      (3) Write u1 to K registers
+         *      (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00
+         *      (5) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (6) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (7) Read X1, Y1 registers to get u1*G
+         *      (8) Write the curve parameter A, B, N, and curve length M to corresponding registers
+         *      (9) Write the public key Q(x,y) to X1, Y1 registers
+         *      (10) Write u2 to K registers
+         *      (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00
+         *      (12) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (13) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (14) Write the curve parameter A, B, N, and curve length M to corresponding registers
+         *      (15) Write the result data u1*G to X2, Y2 registers
+         *      (16) Set ECCOP(CRPT_ECC_CTL[10:9]) to 10
+         *      (17) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (18) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (19) Read X1, Y1 registers to get X * (x1', y1')
+         *      (20) Write the curve order and curve length to N ,M registers
+         *      (21) Write x1 * to X1 registers
+         *      (22) Write 0x0 to Y1 registers
+         *      (23) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01
+         *      (24) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10
+         *      (25) Set START(CRPT_ECC_CTL[0]) to 1
+         *      (26) Wait for BUSY(CRPT_ECC_STS[0]) be cleared
+         *      (27) Read X1 registers to get x1 * (mod n)
+         *
+         *   6. The signature is valid if x1 * = r, otherwise it is invalid
+         */
+
+        /*
+         *  (1) Write the curve parameter A, B, N, and curve length M to corresponding registers
+         *  (2) Write the point G(x, y) to X1, Y1 registers
+         */
+        ecc_init_curve(crpt, ecc_curve);
+
+        /* (3) Write u1 to K registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_K[i] = temp_result1[i];
+        }
+
+        run_ecc_codec(crpt, ECCOP_POINT_MUL);
+
+        /* (7) Read X1, Y1 registers to get u1*G */
+        for(i = 0; i < 18; i++)
+        {
+            temp_x[i] = crpt->ECC_X1[i];
+            temp_y[i] = crpt->ECC_Y1[i];
+        }
+
+#if ENABLE_DEBUG
+        Reg2Hex(pCurve->Echar, temp_x, temp_hex_str);
+        CRPT_DBGMSG("5-(7) u1*G, x = %s\n", temp_hex_str);
+        Reg2Hex(pCurve->Echar, temp_y, temp_hex_str);
+        CRPT_DBGMSG("5-(7) u1*G, y = %s\n", temp_hex_str);
+#endif
+
+        /* (8) Write the curve parameter A, B, N, and curve length M to corresponding registers */
+        ecc_init_curve(crpt, ecc_curve);
+
+        /* (9) Write the public key Q(x,y) to X1, Y1 registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_X1[i] = 0UL;
+            crpt->ECC_Y1[i] = 0UL;
+        }
+
+
+#if 0
+        Hex2Reg(public_k1, crpt->ECC_X1);
+        Hex2Reg(public_k2, crpt->ECC_Y1);
+#else
+
+        /* 5-(2) Get the public key from key store */
+        crpt->ECC_KSCTL = 0ul;
+        crpt->ECC_KSXY = CRPT_ECC_KSXY_RSRCXY_Msk |
+                         (uint32_t)(mem_pk1 << CRPT_ECC_KSXY_RSSRCX_Pos) | ((uint32_t)i32KeyIdx_pk1 << CRPT_ECC_KSXY_NUMX_Pos) | // Key Store index of pk1
+                         (uint32_t)(mem_pk2 << CRPT_ECC_KSXY_RSSRCY_Pos) | ((uint32_t)i32KeyIdx_pk2 << CRPT_ECC_KSXY_NUMY_Pos);  // Key Store index of pk2
+
+#endif
+
+        /* (10) Write u2 to K registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_K[i] = temp_result2[i];
+        }
+
+        run_ecc_codec(crpt, ECCOP_POINT_MUL);
+
+        for(i = 0; i < 18; i++)
+        {
+            temp_result1[i] = crpt->ECC_X1[i];
+            temp_result2[i] = crpt->ECC_Y1[i];
+        }
+
+#if ENABLE_DEBUG
+        Reg2Hex(pCurve->Echar, temp_result1, temp_hex_str);
+        CRPT_DBGMSG("5-(13) u2*Q, x = %s\n", temp_hex_str);
+        Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str);
+        CRPT_DBGMSG("5-(13) u2*Q, y = %s\n", temp_hex_str);
+#endif
+
+        /* (14) Write the curve parameter A, B, N, and curve length M to corresponding registers */
+        ecc_init_curve(crpt, ecc_curve);
+
+        /* Write the result data u2*Q to X1, Y1 registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_X1[i] = temp_result1[i];
+            crpt->ECC_Y1[i] = temp_result2[i];
+        }
+
+        /* (15) Write the result data u1*G to X2, Y2 registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_X2[i] = temp_x[i];
+            crpt->ECC_Y2[i] = temp_y[i];
+        }
+
+        run_ecc_codec(crpt, ECCOP_POINT_ADD);
+
+        /* (19) Read X1, Y1 registers to get X * (x1', y1') */
+        for(i = 0; i < 18; i++)
+        {
+            temp_x[i] = crpt->ECC_X1[i];
+            temp_y[i] = crpt->ECC_Y1[i];
+        }
+
+#if ENABLE_DEBUG
+        Reg2Hex(pCurve->Echar, temp_x, temp_hex_str);
+        CRPT_DBGMSG("5-(19) x' = %s\n", temp_hex_str);
+        Reg2Hex(pCurve->Echar, temp_y, temp_hex_str);
+        CRPT_DBGMSG("5-(19) y' = %s\n", temp_hex_str);
+#endif
+
+        /*  (20) Write the curve order and curve length to N ,M registers */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_N[i] = 0UL;
+        }
+        Hex2Reg(pCurve->Eorder, crpt->ECC_N);
+
+        /*
+         *  (21) Write x1 * to X1 registers
+         *  (22) Write 0x0 to Y1 registers
+         */
+        for(i = 0; i < 18; i++)
+        {
+            crpt->ECC_X1[i] = temp_x[i];
+            crpt->ECC_Y1[i] = 0UL;
+        }
+
+#if ENABLE_DEBUG
+        Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str);
+        CRPT_DBGMSG("5-(21) x' = %s\n", temp_hex_str);
+        Reg2Hex(pCurve->Echar, crpt->ECC_Y1, temp_hex_str);
+        CRPT_DBGMSG("5-(22) y' = %s\n", temp_hex_str);
+#endif
+
+        run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD);
+
+        /*  (27) Read X1 registers to get x1 * (mod n) */
+        Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str);
+        CRPT_DBGMSG("5-(27) x1' (mod n) = %s\n", temp_hex_str);
+
+        /* 6. The signature is valid if x1 * = r, otherwise it is invalid */
+
+        /* Compare with test pattern to check if r is correct or not */
+        if(strcasecmp(temp_hex_str, R) != 0)
+        {
+            CRPT_DBGMSG("x1' (mod n) != R Test filed!!\n");
+            CRPT_DBGMSG("Signature R [%s] is not matched with expected R [%s]!\n", temp_hex_str, R);
+            ret = -2;
+        }
+    }  /* ret == 0 */
+
+    return ret;
+}
+
+
+static ECC_CURVE * get_curve(E_ECC_CURVE ecc_curve)
+{
+    uint32_t   i;
+    ECC_CURVE  *ret = NULL;
+
+    for(i = 0UL; i < sizeof(_Curve) / sizeof(ECC_CURVE); i++)
+    {
+        if(ecc_curve == _Curve[i].curve_id)
+        {
+            memcpy((char *)&Curve_Copy, &_Curve[i], sizeof(ECC_CURVE));
+            ret = &Curve_Copy;   /* (ECC_CURVE *)&_Curve[i]; */
+        }
+        if(ret != NULL)
+        {
+            break;
+        }
+    }
+    return ret;
+}
+
+
+/**
+  * @brief  ECC interrupt service routine. User application must invoke this function in
+  *         his CRYPTO_IRQHandler() to let Crypto driver know ECC processing was done.
+  * @param[in]  crpt        Reference to Crypto module.
+  * @return   none
+  */
+void ECC_Complete(CRPT_T *crpt)
+{
+    if(crpt->INTSTS & CRPT_INTSTS_ECCIF_Msk)
+    {
+        g_ECC_done = 1UL;
+        crpt->INTSTS = CRPT_INTSTS_ECCIF_Msk;
+        /* printf("ECC done IRQ.\n"); */
+    }
+
+    if(crpt->INTSTS & CRPT_INTSTS_ECCEIF_Msk)
+    {
+        g_ECCERR_done = 1UL;
+        crpt->INTSTS = CRPT_INTSTS_ECCEIF_Msk;
+        printf("ECCEIF flag is set!!\n");
+    }
+}
+
+
+int32_t ECC_GetCurve(CRPT_T *crpt, E_ECC_CURVE ecc_curve, ECC_CURVE *curve)
+{
+    int32_t err;
+
+    /* Update pCurve pointer */
+    err = ecc_init_curve(crpt, ecc_curve);
+    if(err == 0)
+    {
+        /* get curve */
+        memcpy(curve, pCurve, sizeof(ECC_CURVE));
+    }
+
+    return err;
+}
+
+
+/*-----------------------------------------------------------------------------------------------*/
+/*                                                                                               */
+/*    RSA                                                                                        */
+/*                                                                                               */
+/*-----------------------------------------------------------------------------------------------*/
+
+/** @cond HIDDEN_SYMBOLS */
+
+static void *s_pRSABuf;
+static uint32_t s_u32RsaOpMode;
+
+typedef enum
+{
+    BUF_NORMAL,
+    BUF_CRT,
+    BUF_CRTBYPASS,
+    BUF_SCAP,
+    BUF_CRT_SCAP,
+    BUF_CRTBYPASS_SCAP,
+    BUF_KS
+} E_RSA_BUF_SEL;
+
+static int32_t CheckRsaBufferSize(uint32_t u32OpMode, uint32_t u32BufSize, uint32_t u32UseKS);
+
+/** @endcond HIDDEN_SYMBOLS */
+
+/* Check the allocated buffer size for RSA operation. */
+static int32_t CheckRsaBufferSize(uint32_t u32OpMode, uint32_t u32BufSize, uint32_t u32UseKS)
+{
+    /* RSA buffer size for MODE_NORMAL, MODE_CRT, MODE_CRTBYPASS, MODE_SCAP, MODE_CRT_SCAP, MODE_CRTBYPASS_SCAP */
+    uint32_t s_au32RsaBufSizeTbl[] = {sizeof(RSA_BUF_NORMAL_T), sizeof(RSA_BUF_CRT_T), sizeof(RSA_BUF_CRT_T), \
+                                      sizeof(RSA_BUF_SCAP_T), sizeof(RSA_BUF_CRT_SCAP_T), sizeof(RSA_BUF_CRT_SCAP_T), \
+                                      sizeof(RSA_BUF_KS_T)
+                                     };
+
+    if(u32UseKS)
+    {
+        if(u32BufSize != s_au32RsaBufSizeTbl[BUF_KS])
+            return (-1);
+    }
+    else
+    {
+        switch(u32OpMode)
+        {
+            case RSA_MODE_NORMAL:
+                if(u32BufSize != s_au32RsaBufSizeTbl[BUF_NORMAL])
+                    return (-1);
+                break;
+            case RSA_MODE_CRT:
+                if(u32BufSize != s_au32RsaBufSizeTbl[BUF_CRT])
+                    return (-1);
+                break;
+            case RSA_MODE_CRTBYPASS:
+                if(u32BufSize != s_au32RsaBufSizeTbl[BUF_CRTBYPASS])
+                    return (-1);
+                break;
+            case RSA_MODE_SCAP:
+                if(u32BufSize != s_au32RsaBufSizeTbl[BUF_SCAP])
+                    return (-1);
+                break;
+            case RSA_MODE_CRT_SCAP:
+                if(u32BufSize != s_au32RsaBufSizeTbl[BUF_CRT_SCAP])
+                    return (-1);
+                break;
+            case RSA_MODE_CRTBYPASS_SCAP:
+                if(u32BufSize != s_au32RsaBufSizeTbl[BUF_CRTBYPASS_SCAP])
+                    return (-1);
+                break;
+            default:
+                return (-1);
+        }
+    }
+
+    return 0;
+}
+
+/**
+  * @brief  Open RSA encrypt/decrypt function.
+  * @param[in]  crpt         The pointer of CRYPTO module
+  * @param[in]  u32OpMode    RSA operation mode, including:
+  *         - \ref RSA_MODE_NORMAL
+  *         - \ref RSA_MODE_CRT
+  *         - \ref RSA_MODE_CRTBYPASS
+  *         - \ref RSA_MODE_SCAP
+  *         - \ref RSA_MODE_CRT_SCAP
+  *         - \ref RSA_MODE_CRTBYPASS_SCAP
+  * @param[in]  u32KeySize is RSA key size, including:
+  *         - \ref RSA_KEY_SIZE_1024
+  *         - \ref RSA_KEY_SIZE_2048
+  *         - \ref RSA_KEY_SIZE_3072
+  *         - \ref RSA_KEY_SIZE_4096
+  * @param[in]  psRSA_Buf    The pointer of RSA buffer struct. User should declare correct RSA buffer for specific operation mode first.
+  *         - \ref RSA_BUF_NORMAL_T      The struct for normal mode
+  *         - \ref RSA_BUF_CRT_T         The struct for CRT ( + CRT bypass) mode
+  *         - \ref RSA_BUF_SCAP_T        The struct for SCAP mode
+  *         - \ref RSA_BUF_CRT_SCAP_T    The struct for CRT ( + CRT bypass) +SCAP mode
+  *         - \ref RSA_BUF_KS_T          The struct for using key store
+  * @param[in]  u32BufSize is RSA buffer size.
+  * @param[in]  u32UseKS is use key store function.
+  *         - \ref 0    No use key store function
+  *         - \ref 1    Use key store function
+  * @return  0    Success.
+  * @return  -1   The value of pointer of RSA buffer struct is null.
+  */
+int32_t RSA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32KeySize, \
+                 void *psRSA_Buf, uint32_t u32BufSize, uint32_t u32UseKS)
+{
+    if(psRSA_Buf == 0)
+    {
+        return (-1);
+    }
+    if(CheckRsaBufferSize(u32OpMode, u32BufSize, u32UseKS) != 0)
+    {
+        return (-1);
+    }
+
+    s_u32RsaOpMode = u32OpMode;
+    s_pRSABuf = psRSA_Buf;
+    crpt->RSA_CTL = (u32OpMode) | (u32KeySize << CRPT_RSA_CTL_KEYLENG_Pos);
+
+    return 0;
+}
+
+/**
+  * @brief  Set the RSA key
+  * @param[in]  crpt        The pointer of CRYPTO module
+  * @param[in]  Key         The private or public key.
+  * @return  0    Success.
+  * @return  -1   The value of pointer of RSA buffer struct is null.
+  */
+int32_t RSA_SetKey(CRPT_T *crpt, char *Key)
+{
+    if(s_pRSABuf == 0)
+    {
+        return (-1);
+    }
+    Hex2Reg(Key, ((RSA_BUF_NORMAL_T *)s_pRSABuf)->au32RsaE);
+    crpt->RSA_SADDR[2] = (uint32_t) & ((RSA_BUF_NORMAL_T *)s_pRSABuf)->au32RsaE; /* the public key or private key */
+
+    return 0;
+}
+
+/**
+  * @brief  Set RSA DMA transfer configuration.
+  * @param[in]  crpt         The pointer of CRYPTO module
+  * @param[in]  Src   RSA DMA source data
+  * @param[in]  n     The modulus for both the public and private keys
+  * @param[in]  P     The factor of modulus operation(P) for CRT/SCAP mode
+  * @param[in]  Q     The factor of modulus operation(Q) for CRT/SCAP mode
+  * @return  0    Success.
+  * @return  -1   The value of pointer of RSA buffer struct is null.
+  */
+int32_t RSA_SetDMATransfer(CRPT_T *crpt, char *Src, char *n, char *P, char *Q)
+{
+    if(s_pRSABuf == 0)
+    {
+        return (-1);
+    }
+    Hex2Reg(Src, ((RSA_BUF_NORMAL_T *)s_pRSABuf)->au32RsaM);
+    Hex2Reg(n, ((RSA_BUF_NORMAL_T *)s_pRSABuf)->au32RsaN);
+
+    /* Assign the data to DMA */
+    crpt->RSA_SADDR[0] = (uint32_t) & ((RSA_BUF_NORMAL_T *)s_pRSABuf)->au32RsaM; /* plaintext / encrypt data */
+    crpt->RSA_SADDR[1] = (uint32_t) & ((RSA_BUF_NORMAL_T *)s_pRSABuf)->au32RsaN; /* the base of modulus operation */
+    crpt->RSA_DADDR    = (uint32_t) & ((RSA_BUF_NORMAL_T *)s_pRSABuf)->au32RsaOutput; /* encrypt data / decrypt data */
+
+    if((s_u32RsaOpMode & CRPT_RSA_CTL_CRT_Msk) && (s_u32RsaOpMode & CRPT_RSA_CTL_SCAP_Msk))
+    {
+        /* For RSA CRT/SCAP mode, two primes of private key */
+        Hex2Reg(P, ((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaP);
+        Hex2Reg(Q, ((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaQ);
+
+        crpt->RSA_SADDR[3] = (uint32_t) & ((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaP; /* prime P */
+        crpt->RSA_SADDR[4] = (uint32_t) & ((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaQ; /* prime Q */
+
+        crpt->RSA_MADDR[0] = (uint32_t) & ((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaTmpCp; /* for storing the intermediate temporary value(Cp) */
+        crpt->RSA_MADDR[1] = (uint32_t) & ((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaTmpCq; /* for storing the intermediate temporary value(Cq) */
+        crpt->RSA_MADDR[2] = (uint32_t) & ((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaTmpDp; /* for storing the intermediate temporary value(Dp) */
+        crpt->RSA_MADDR[3] = (uint32_t) & ((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaTmpDq; /* for storing the intermediate temporary value(Dq) */
+        crpt->RSA_MADDR[4] = (uint32_t) & ((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaTmpRp; /* for storing the intermediate temporary value(Rp) */
+        crpt->RSA_MADDR[5] = (uint32_t) & ((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaTmpRq; /* for storing the intermediate temporary value(Rq) */
+
+        /* For SCAP mode to store the intermediate temporary value(blind key) */
+        crpt->RSA_MADDR[6] = (uint32_t) & ((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaTmpBlindKey;
+    }
+    else if(s_u32RsaOpMode & CRPT_RSA_CTL_CRT_Msk)
+    {
+        /* For RSA CRT/SCAP mode, two primes of private key */
+        Hex2Reg(P, ((RSA_BUF_CRT_T *)s_pRSABuf)->au32RsaP);
+        Hex2Reg(Q, ((RSA_BUF_CRT_T *)s_pRSABuf)->au32RsaQ);
+
+        crpt->RSA_SADDR[3] = (uint32_t) & ((RSA_BUF_CRT_T *)s_pRSABuf)->au32RsaP; /* prime P */
+        crpt->RSA_SADDR[4] = (uint32_t) & ((RSA_BUF_CRT_T *)s_pRSABuf)->au32RsaQ; /* prime Q */
+
+        crpt->RSA_MADDR[0] = (uint32_t) & ((RSA_BUF_CRT_T *)s_pRSABuf)->au32RsaTmpCp; /* for storing the intermediate temporary value(Cp) */
+        crpt->RSA_MADDR[1] = (uint32_t) & ((RSA_BUF_CRT_T *)s_pRSABuf)->au32RsaTmpCq; /* for storing the intermediate temporary value(Cq) */
+        crpt->RSA_MADDR[2] = (uint32_t) & ((RSA_BUF_CRT_T *)s_pRSABuf)->au32RsaTmpDp; /* for storing the intermediate temporary value(Dp) */
+        crpt->RSA_MADDR[3] = (uint32_t) & ((RSA_BUF_CRT_T *)s_pRSABuf)->au32RsaTmpDq; /* for storing the intermediate temporary value(Dq) */
+        crpt->RSA_MADDR[4] = (uint32_t) & ((RSA_BUF_CRT_T *)s_pRSABuf)->au32RsaTmpRp; /* for storing the intermediate temporary value(Rp) */
+        crpt->RSA_MADDR[5] = (uint32_t) & ((RSA_BUF_CRT_T *)s_pRSABuf)->au32RsaTmpRq; /* for storing the intermediate temporary value(Rq) */
+    }
+    else if(s_u32RsaOpMode & CRPT_RSA_CTL_SCAP_Msk)
+    {
+        /* For RSA CRT/SCAP mode, two primes of private key */
+        Hex2Reg(P, ((RSA_BUF_SCAP_T *)s_pRSABuf)->au32RsaP);
+        Hex2Reg(Q, ((RSA_BUF_SCAP_T *)s_pRSABuf)->au32RsaQ);
+
+        crpt->RSA_SADDR[3] = (uint32_t) & ((RSA_BUF_SCAP_T *)s_pRSABuf)->au32RsaP; /* prime P */
+        crpt->RSA_SADDR[4] = (uint32_t) & ((RSA_BUF_SCAP_T *)s_pRSABuf)->au32RsaQ; /* prime Q */
+
+        /* For SCAP mode to store the intermediate temporary value(blind key) */
+        crpt->RSA_MADDR[6] = (uint32_t) & ((RSA_BUF_SCAP_T *)s_pRSABuf)->au32RsaTmpBlindKey;
+    }
+
+    return 0;
+}
+
+/**
+  * @brief  Start RSA encrypt/decrypt
+  * @param[in]  crpt        The pointer of CRYPTO module
+  * @return None
+  */
+void RSA_Start(CRPT_T *crpt)
+{
+    crpt->RSA_CTL |= CRPT_RSA_CTL_START_Msk;
+}
+
+/**
+  * @brief  Read the RSA output.
+  * @param[in]   crpt       The pointer of CRYPTO module
+  * @param[out]  Output     The RSA operation output data.
+  * @return  0    Success.
+  * @return  -1   The value of pointer of RSA buffer struct is null.
+  */
+int32_t RSA_Read(CRPT_T *crpt, char *Output)
+{
+    if(s_pRSABuf == 0)
+    {
+        return (-1);
+    }
+    uint32_t au32CntTbl[4] = {256, 512, 768, 1024}; /* count is key length divided by 4 */
+    uint32_t u32CntIdx = 0;
+
+    u32CntIdx = (crpt->RSA_CTL & CRPT_RSA_CTL_KEYLENG_Msk) >> CRPT_RSA_CTL_KEYLENG_Pos;
+    Reg2Hex((int32_t)au32CntTbl[u32CntIdx], ((RSA_BUF_NORMAL_T *)s_pRSABuf)->au32RsaOutput, Output);
+
+    return 0;
+}
+
+/**
+  * @brief  Set the RSA key is read from key store
+  * @param[in]  crpt           The pointer of CRYPTO module
+  * @param[in]  u32KeyNum      The number of private or public key in key store.
+  * @param[in]  u32KSMemType   The key is read from selected memory type of key store. It could be:
+                            \ref KS_SRAM
+                            \ref KS_FLASH
+                            \ref KS_OTP
+  * @param[in]  u32BlindKeyNum  The number of blind key in SRAM of key store for SCAP mode. This key is un-readable.
+  * @return  0    Success.
+  * @return  -1   The value of pointer of RSA buffer struct is null.
+  */
+int32_t RSA_SetKey_KS(CRPT_T *crpt, uint32_t u32KeyNum, uint32_t u32KSMemType, uint32_t u32BlindKeyNum)
+{
+    if(s_u32RsaOpMode & CRPT_RSA_CTL_SCAP_Msk)
+    {
+        crpt->RSA_KSCTL = (u32BlindKeyNum << 8) | (u32KSMemType << CRPT_RSA_KSCTL_RSSRC_Pos) | CRPT_RSA_KSCTL_RSRC_Msk | u32KeyNum;
+    }
+    else
+    {
+        crpt->RSA_KSCTL = (u32KSMemType << CRPT_RSA_KSCTL_RSSRC_Pos) | CRPT_RSA_KSCTL_RSRC_Msk | u32KeyNum;
+    }
+    return 0;
+}
+
+/**
+  * @brief  Set RSA DMA transfer configuration while using key store.
+  * @param[in]  crpt         The pointer of CRYPTO module
+  * @param[in]  u32OpMode    RSA operation mode, including:
+  *         - \ref RSA_MODE_NORMAL
+  *         - \ref RSA_MODE_CRT
+  *         - \ref RSA_MODE_CRTBYPASS
+  *         - \ref RSA_MODE_SCAP
+  *         - \ref RSA_MODE_CRT_SCAP
+  *         - \ref RSA_MODE_CRTBYPASS_SCAP
+  * @param[in]  Src   RSA DMA source data
+  * @param[in]  n     The modulus for both the public and private keys
+  * @param[in]  u32PNum         The number of the factor of modulus operation(P) in SRAM of key store for CRT/SCAP mode
+  * @param[in]  u32QNum         The number of the factor of modulus operation(Q) in SRAM of key store for CRT/SCAP mode
+  * @param[in]  u32CpNum        The number of Cp in SRAM of key store for CRT mode
+  * @param[in]  u32CqNum        The number of Cq in SRAM of key store for CRT mode
+  * @param[in]  u32DpNum        The number of Dp in SRAM of key store for CRT mode
+  * @param[in]  u32DqNum        The number of Dq in SRAM of key store for CRT mode
+  * @param[in]  u32RpNum        The number of Rp in SRAM of key store for CRT mode
+  * @param[in]  u32RqNum        The number of Rq in SRAM of key store for CRT mode
+  * @return  0    Success.
+  * @return  -1   The value of pointer of RSA buffer struct is null.
+  * @note P, Q, Dp, Dq are equal to half key length. Cp, Cq, Rp, Rq, Blind key are equal to key length.
+  */
+int32_t RSA_SetDMATransfer_KS(CRPT_T *crpt, char *Src, char *n, uint32_t u32PNum,
+                              uint32_t u32QNum, uint32_t u32CpNum, uint32_t u32CqNum, uint32_t u32DpNum,
+                              uint32_t u32DqNum, uint32_t u32RpNum, uint32_t u32RqNum)
+{
+    if(s_pRSABuf == 0)
+    {
+        return (-1);
+    }
+    Hex2Reg(Src, ((RSA_BUF_KS_T *)s_pRSABuf)->au32RsaM);
+    Hex2Reg(n, ((RSA_BUF_KS_T *)s_pRSABuf)->au32RsaN);
+
+    /* Assign the data to DMA */
+    crpt->RSA_SADDR[0] = (uint32_t) & ((RSA_BUF_KS_T *)s_pRSABuf)->au32RsaM; /* plaintext / encrypt data */
+    crpt->RSA_SADDR[1] = (uint32_t) & ((RSA_BUF_KS_T *)s_pRSABuf)->au32RsaN; /* the base of modulus operation */
+    crpt->RSA_DADDR    = (uint32_t) & ((RSA_BUF_KS_T *)s_pRSABuf)->au32RsaOutput; /* encrypt data / decrypt data */
+
+    if((s_u32RsaOpMode & CRPT_RSA_CTL_CRT_Msk) || (s_u32RsaOpMode & CRPT_RSA_CTL_SCAP_Msk))
+    {
+        /* For RSA CRT/SCAP mode, two primes of private key */
+        crpt->RSA_KSSTS[0] = (crpt->RSA_KSSTS[0] & (~(CRPT_RSA_KSSTS0_NUM0_Msk | CRPT_RSA_KSSTS0_NUM1_Msk))) | \
+                             (u32PNum << CRPT_RSA_KSSTS0_NUM0_Pos) | (u32QNum << CRPT_RSA_KSSTS0_NUM1_Pos);
+
+    }
+    if(s_u32RsaOpMode & CRPT_RSA_CTL_CRT_Msk)
+    {
+        /* For RSA CRT mode, Cp, Cq, Dp, Dq, Rp, Rq */
+        crpt->RSA_KSSTS[0] = (crpt->RSA_KSSTS[0] & (~(CRPT_RSA_KSSTS0_NUM2_Msk | CRPT_RSA_KSSTS0_NUM3_Msk))) | \
+                             (u32CpNum << CRPT_RSA_KSSTS0_NUM2_Pos) | (u32CqNum << CRPT_RSA_KSSTS0_NUM3_Pos);
+        crpt->RSA_KSSTS[1] = (u32DpNum << CRPT_RSA_KSSTS1_NUM4_Pos) | (u32DqNum << CRPT_RSA_KSSTS1_NUM5_Pos) | \
+                             (u32RpNum << CRPT_RSA_KSSTS1_NUM6_Pos) | (u32RqNum << CRPT_RSA_KSSTS1_NUM7_Pos);
+    }
+
+    return 0;
+}
+
+
+/**@}*/ /* end of group CRYPTO_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group CRYPTO_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_dac.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_dac.c
new file mode 100644
index 0000000000..0f12b935bc
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_dac.c
@@ -0,0 +1,91 @@
+/**************************************************************************//**
+ * @file     dac.c
+ * @version  V1.00
+ * @brief    M2354 series DAC driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup DAC_Driver DAC Driver
+  @{
+*/
+
+/** @addtogroup DAC_EXPORTED_FUNCTIONS DAC Exported Functions
+  @{
+*/
+
+/**
+  * @brief This function make DAC module be ready to convert.
+  * @param[in] dac The pointer of the specified DAC module.
+  * @param[in] u32Ch Not used in M2354 Series DAC.
+  * @param[in] u32TrgSrc Decides the trigger source. Valid values are:
+  *                      - \ref DAC_WRITE_DAT_TRIGGER             :Write DAC_DAT trigger
+  *                      - \ref DAC_SOFTWARE_TRIGGER              :Software trigger
+  *                      - \ref DAC_LOW_LEVEL_TRIGGER             :STDAC pin low level trigger
+  *                      - \ref DAC_HIGH_LEVEL_TRIGGER            :STDAC pin high level trigger
+  *                      - \ref DAC_FALLING_EDGE_TRIGGER          :STDAC pin falling edge trigger
+  *                      - \ref DAC_RISING_EDGE_TRIGGER           :STDAC pin rising edge trigger
+  *                      - \ref DAC_TIMER0_TRIGGER                :Timer 0 trigger
+  *                      - \ref DAC_TIMER1_TRIGGER                :Timer 1 trigger
+  *                      - \ref DAC_TIMER2_TRIGGER                :Timer 2 trigger
+  *                      - \ref DAC_TIMER3_TRIGGER                :Timer 3 trigger
+  *                      - \ref DAC_EPWM0_TRIGGER                 :EPWM0 trigger
+  *                      - \ref DAC_EPWM1_TRIGGER                 :EPWM1 trigger
+  * @return None
+  * @details The DAC conversion can be started by writing DAC_DAT, software trigger or hardware trigger.
+  *         When TRGEN (DAC_CTL[4]) is 0, the data conversion is started by writing DAC_DAT register.
+  *         When TRGEN (DAC_CTL[4]) is 1, the data conversion is started by SWTRG (DAC_SWTRG[0]) is set to 1,
+  *         external STDAC pin, timer event, or EPWM event.
+  */
+void DAC_Open(DAC_T *dac,
+              uint32_t u32Ch,
+              uint32_t u32TrgSrc)
+{
+    (void)u32Ch;
+    dac->CTL &= ~(DAC_CTL_ETRGSEL_Msk | DAC_CTL_TRGSEL_Msk | DAC_CTL_TRGEN_Msk);
+
+    dac->CTL |= (u32TrgSrc | DAC_CTL_DACEN_Msk);
+}
+
+/**
+  * @brief Disable DAC analog power.
+  * @param[in] dac The pointer of the specified DAC module.
+  * @param[in] u32Ch Not used in M2354 Series DAC.
+  * @return None
+  * @details Disable DAC analog power for saving power consumption.
+  */
+void DAC_Close(DAC_T *dac, uint32_t u32Ch)
+{
+    (void)u32Ch;
+    dac->CTL &= (~DAC_CTL_DACEN_Msk);
+}
+
+/**
+  * @brief Set delay time for DAC to become stable.
+  * @param[in] dac The pointer of the specified DAC module.
+  * @param[in] u32Delay Decides the DAC conversion settling time, the range is from 0~(1023/PCLK1*1000000) micro seconds.
+  * @return Real DAC conversion settling time (micro second).
+  * @details For example, DAC controller clock speed is 64MHz and DAC conversion setting time is 1 us, SETTLET (DAC_TCTL[9:0]) value must be greater than 0x40.
+  * @note User needs to write appropriate value to meet DAC conversion settling time base on PCLK (APB clock) speed.
+  */
+uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay)
+{
+
+    dac->TCTL = ((CLK_GetPCLK1Freq() * u32Delay / 1000000UL) & 0x3FFUL);
+
+    return ((dac->TCTL) * 1000000UL / CLK_GetPCLK1Freq());
+}
+
+
+
+/**@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group DAC_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_dpm.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_dpm.c
new file mode 100644
index 0000000000..568140e1aa
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_dpm.c
@@ -0,0 +1,409 @@
+/**************************************************************************//**
+ * @file     dpm.c
+ * @version  V3.00
+ * @brief    Debug Protection Mechanism (DPM) driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup DPM_Driver DPM Driver
+  @{
+*/
+
+/** @addtogroup DPM_EXPORTED_FUNCTIONS DPM Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Set Debug Disable
+  * @param[in]  u32dpm  The pointer of the specified DPM module
+  *                     - \ref SECURE_DPM
+  *                     - \ref NONSECURE_DPM
+  * @return     None
+  * @details    This macro sets Secure or Non-secure DPM debug disable.
+  *             The debug disable function works after reset (chip reset or pin reset).
+  */
+void DPM_SetDebugDisable(uint32_t u32dpm)
+{
+    DPM_T *dpm;
+
+    if(__PC()&NS_OFFSET) dpm = DPM_NS;
+    else dpm = DPM;
+
+    if(u32dpm == SECURE_DPM) /* Secure DPM */
+    {
+        while(dpm->STS & DPM_STS_BUSY_Msk);
+        dpm->CTL = (DPM->CTL & (~DPM_CTL_WVCODE_Msk)) | (DPM_CTL_WVCODE | DPM_CTL_DBGDIS_Msk);
+    }
+    else    /* Non-secure DPM */
+    {
+        while(dpm->NSSTS & DPM_NSSTS_BUSY_Msk);
+        dpm->NSCTL = (dpm->NSCTL & (~DPM_NSCTL_WVCODE_Msk)) | (DPM_NSCTL_WVCODE | DPM_NSCTL_DBGDIS_Msk);
+    }
+}
+
+/**
+  * @brief      Set Debug Lock
+  * @param[in]  u32dpm  Select DPM module. Valid values are:
+  *                     - \ref SECURE_DPM
+  *                     - \ref NONSECURE_DPM
+  * @return     None
+  * @details    This macro sets Secure or Non-secure DPM debug lock.
+  *             The debug lock function works after reset (chip reset or pin reset).
+  */
+void DPM_SetDebugLock(uint32_t u32dpm)
+{
+    DPM_T *dpm;
+
+    if(__PC()&NS_OFFSET) dpm = DPM_NS;
+    else dpm = DPM;
+
+    if(u32dpm == SECURE_DPM) /* Secure DPM */
+    {
+        while(dpm->STS & DPM_STS_BUSY_Msk);
+        dpm->CTL = (dpm->CTL & (~DPM_CTL_WVCODE_Msk)) | (DPM_CTL_WVCODE | DPM_CTL_LOCK_Msk);
+    }
+    else    /* Non-secure DPM */
+    {
+        while(dpm->NSSTS & DPM_NSSTS_BUSY_Msk);
+        dpm->NSCTL = (dpm->NSCTL & (~DPM_NSCTL_WVCODE_Msk)) | (DPM_NSCTL_WVCODE | DPM_NSCTL_LOCK_Msk);
+    }
+}
+
+/**
+  * @brief      Get Debug Disable
+  * @param[in]  u32dpm  Select DPM module. Valid values are:
+  *                     - \ref SECURE_DPM
+  *                     - \ref NONSECURE_DPM
+  * @retval     0   Debug is not in disable status
+  * @retval     1   Debug is in disable status
+  * @details    This macro gets Secure or Non-secure DPM debug disable status.
+  *             If Secure debug is disabled, debugger cannot access Secure region and can access Non-secure region only.
+  *             If Non-secure debug is disabled, debugger cannot access all Secure and Non-secure region.
+  */
+uint32_t DPM_GetDebugDisable(uint32_t u32dpm)
+{
+    uint32_t u32RetVal = 0;
+    DPM_T *dpm;
+
+    if(__PC()&NS_OFFSET) dpm = DPM_NS;
+    else dpm = DPM;
+
+    if(u32dpm == SECURE_DPM) /* Secure DPM */
+    {
+        while(dpm->STS & DPM_STS_BUSY_Msk);
+        u32RetVal = (dpm->STS & DPM_STS_DBGDIS_Msk) >> DPM_STS_DBGDIS_Pos;
+    }
+    else    /* Non-secure DPM */
+    {
+        while(dpm->NSSTS & DPM_NSSTS_BUSY_Msk);
+        u32RetVal = (dpm->NSSTS & DPM_NSSTS_DBGDIS_Msk) >> DPM_NSSTS_DBGDIS_Pos;
+    }
+
+    return u32RetVal;
+}
+
+/**
+  * @brief      Get Debug Lock
+  * @param[in]  u32dpm  Select DPM module. Valid values are:
+  *                     - \ref SECURE_DPM
+  *                     - \ref NONSECURE_DPM
+  * @retval     0   Debug is not in lock status
+  * @retval     1   Debug is in lock status
+  * @details    This macro gets Secure or Non-secure DPM debug disable status.
+  *             If Secure debug is locked, debugger cannot access Secure region and can access Non-secure region only.
+  *             If Non-secure debug is locked, debugger cannot access all Secure and Non-secure region.
+  */
+uint32_t DPM_GetDebugLock(uint32_t u32dpm)
+{
+    uint32_t u32RetVal = 0;
+    DPM_T *dpm;
+
+    if(__PC()&NS_OFFSET) dpm = DPM_NS;
+    else dpm = DPM;
+
+    if(u32dpm == SECURE_DPM) /* Secure DPM */
+    {
+        while(dpm->STS & DPM_STS_BUSY_Msk);
+        u32RetVal = (dpm->STS & DPM_STS_LOCK_Msk) >> DPM_STS_LOCK_Pos;
+    }
+    else                    /* Non-secure DPM */
+    {
+        while(dpm->NSSTS & DPM_NSSTS_BUSY_Msk);
+        u32RetVal = (dpm->NSSTS & DPM_NSSTS_LOCK_Msk) >> DPM_NSSTS_LOCK_Pos;
+    }
+
+    return u32RetVal;
+}
+
+/**
+  * @brief      Update DPM Password
+  * @param[in]  u32dpm        Select DPM module. Valid values are:
+  *                           - \ref SECURE_DPM
+  *                           - \ref NONSECURE_DPM
+  * @param[in]  au32Password  Password length is 256 bits.
+  * @retval     0   No password is updated. The password update count has reached the maximum value.
+  * @retval     1   Password update is successful.
+  * @details    This macro updates Secure or Non-secure DPM password.
+  */
+uint32_t DPM_SetPasswordUpdate(uint32_t u32dpm, uint32_t au32Pwd[])
+{
+    uint32_t u32i, u32RetVal = 0;
+    DPM_T *dpm;
+
+    if(__PC()&NS_OFFSET) dpm = DPM_NS;
+    else dpm = DPM;
+
+    if(u32dpm == SECURE_DPM) /* Secure DPM */
+    {
+        /* Set Secure DPM password */
+        for(u32i = 0; u32i < 4; u32i++)
+        {
+            while(dpm->STS & DPM_STS_BUSY_Msk);
+            dpm->SPW[u32i] = au32Pwd[u32i];
+        }
+
+        /* Set Secure DPM password update */
+        while(dpm->STS & DPM_STS_BUSY_Msk);
+        dpm->CTL = (dpm->CTL & (~DPM_CTL_WVCODE_Msk)) | (DPM_CTL_WVCODE | DPM_CTL_PWUPD_Msk);
+
+        /* Check Secure DPM password update flag */
+        while(dpm->STS & DPM_STS_BUSY_Msk);
+        u32RetVal = (dpm->STS & DPM_STS_PWUOK_Msk) >> DPM_STS_PWUOK_Pos;
+
+        /* Clear Secure DPM password update flag */
+        if(u32RetVal) dpm->STS = DPM_STS_PWUOK_Msk;
+    }
+    else    /* Non-secure DPM */
+    {
+        /* Set Non-secure DPM password */
+        for(u32i = 0; u32i < 4; u32i++)
+        {
+            while(dpm->NSSTS & DPM_NSSTS_BUSY_Msk);
+            dpm->NSPW[u32i] = au32Pwd[u32i];
+        }
+
+        /* Set Non-secure DPM password update */
+        while(dpm->NSSTS & DPM_NSSTS_BUSY_Msk);
+        dpm->NSCTL = (dpm->NSCTL & (~DPM_CTL_WVCODE_Msk)) | (DPM_CTL_WVCODE | DPM_NSCTL_PWUPD_Msk);
+
+        /* Check Non-secure DPM password update flag */
+        while(dpm->NSSTS & DPM_NSSTS_BUSY_Msk);
+        u32RetVal = (dpm->NSSTS & DPM_NSSTS_PWUOK_Msk) >> DPM_NSSTS_PWUOK_Pos;
+
+        /* Clear Non-secure DPM password update flag */
+        if(u32RetVal) dpm->NSSTS = DPM_NSSTS_PWUOK_Msk;
+    }
+
+    return u32RetVal;
+}
+
+/**
+  * @brief      Compare DPM Password
+  * @param[in]  u32dpm  Select DPM module. Valid values are:
+  *                     - \ref SECURE_DPM
+  *                     - \ref NONSECURE_DPM
+  * @retval     0   The password comparison can be proccessed.
+  * @retval     1   No more password comparison can be proccessed. \n
+  *                 The password comparison fail times has reached the maximum value.
+  * @details    This macro sets Secure or Non-secure DPM password comparison. \n
+  *             The comparison result is checked by DPM_GetPasswordErrorFlag().
+  */
+uint32_t DPM_SetPasswordCompare(uint32_t u32dpm, uint32_t au32Pwd[])
+{
+    uint32_t u32i, u32RetVal = 0;
+    DPM_T *dpm;
+
+    if(__PC()&NS_OFFSET) dpm = DPM_NS;
+    else dpm = DPM;
+
+    if(u32dpm == SECURE_DPM) /* Secure DPM */
+    {
+        /* Check Secure DPM password compare fail times maximum flag */
+        while(dpm->STS & DPM_STS_BUSY_Msk);
+        if(dpm->STS & DPM_STS_PWFMAX_Msk)
+        {
+            u32RetVal = 1;
+        }
+        else
+        {
+            /* Set Secure DPM password */
+            for(u32i = 0; u32i < 4; u32i++)
+            {
+                while(dpm->STS & DPM_STS_BUSY_Msk);
+                dpm->SPW[u32i] = au32Pwd[u32i];
+            }
+
+            /* Set Secure DPM password cpmpare */
+            while(dpm->STS & DPM_STS_BUSY_Msk);
+            dpm->CTL = (dpm->CTL & (~DPM_CTL_WVCODE_Msk)) | (DPM_CTL_WVCODE | DPM_CTL_PWCMP_Msk);
+        }
+    }
+    else    /* Non-secure DPM */
+    {
+        /* Check Non-secure DPM password compare fail times maximum flag */
+        while(dpm->NSSTS & DPM_NSSTS_BUSY_Msk);
+        if(dpm->NSSTS & DPM_NSSTS_PWFMAX_Msk)
+        {
+            u32RetVal = 1;
+        }
+        else
+        {
+            /* Set Non-secure DPM password */
+            for(u32i = 0; u32i < 4; u32i++)
+            {
+                while(dpm->NSSTS & DPM_NSSTS_BUSY_Msk);
+                dpm->NSPW[u32i] = au32Pwd[u32i];
+            }
+
+            /* Set Non-secure DPM password compare */
+            while(dpm->NSSTS & DPM_NSSTS_BUSY_Msk);
+            dpm->NSCTL = (dpm->NSCTL & (~DPM_NSCTL_WVCODE_Msk)) | (DPM_NSCTL_WVCODE | DPM_NSCTL_PWCMP_Msk);
+        }
+    }
+
+    return u32RetVal;
+}
+
+/**
+  * @brief      Get DPM Password Error Flag
+  * @param[in]  u32dpm        Select DPM module. Valid values are:
+  *                           - \ref SECURE_DPM
+  *                           - \ref NONSECURE_DPM
+  * @return     Specified DPM module password compare error flag.
+  * @details    This macro returns Secure or Non-secure DPM password compare error flag.
+  */
+uint32_t DPM_GetPasswordErrorFlag(uint32_t u32dpm)
+{
+    uint32_t u32RetVal = 0;
+    DPM_T *dpm;
+
+    if(__PC()&NS_OFFSET) dpm = DPM_NS;
+    else dpm = DPM;
+
+    if(u32dpm == SECURE_DPM) /* Secure DPM */
+    {
+        /* Check Secure DPM password compare error flag */
+        while(dpm->STS & DPM_STS_BUSY_Msk);
+        u32RetVal = (dpm->STS & DPM_STS_PWCERR_Msk) >> DPM_STS_PWCERR_Pos;
+    }
+    else    /* Non-secure DPM */
+    {
+        /* Check Non-secure DPM password compare error flag */
+        while(dpm->NSSTS & DPM_NSSTS_BUSY_Msk);
+        u32RetVal = (dpm->NSSTS & DPM_NSSTS_PWCERR_Msk) >> DPM_NSSTS_PWCERR_Pos;
+    }
+
+    return u32RetVal;
+}
+
+/**
+  * @brief      Get DPM Interrupt Flag
+  * @param      None
+  * @return     Secure DPM interrupt flag.
+  * @details    This macro returns Secure DPM interrupt flag.
+  *             Secure DPM interrupt flag includes Secure and Non-secure DPM password compare error flag.
+  *             This macro is for Secure DPM and Secure region only.
+  */
+uint32_t DPM_GetIntFlag(void)
+{
+    while(DPM->STS & DPM_STS_BUSY_Msk);
+    return (DPM->STS & DPM_STS_INT_Msk) >> DPM_STS_INT_Pos;
+}
+
+
+/**
+  * @brief      Clear DPM Password Error Flag
+  * @param[in]  u32dpm        Select DPM module. Valid values are:
+  *                           - \ref SECURE_DPM
+  *                           - \ref NONSECURE_DPM
+  * @return     Specified DPM module interrupt flag.
+  * @details    This macro clears Secure or Non-secure DPM password compare error flag.
+  */
+void DPM_ClearPasswordErrorFlag(uint32_t u32dpm)
+{
+    DPM_T *dpm;
+
+    if(__PC()&NS_OFFSET) dpm = DPM_NS;
+    else dpm = DPM;
+
+    if(u32dpm == SECURE_DPM) /* Secure DPM */
+    {
+        while(dpm->STS & DPM_STS_BUSY_Msk);
+        dpm->STS = DPM_STS_PWCERR_Msk;
+    }
+    else    /* Non-secure DPM */
+    {
+        while(dpm->NSSTS & DPM_NSSTS_BUSY_Msk);
+        dpm->NSSTS = DPM_NSSTS_PWCERR_Msk;
+    }
+}
+
+/**
+  * @brief      Enable Debugger Write Access
+  * @param[in]  u32dpm        Select DPM module. Valid values are:
+  *                           - \ref SECURE_DPM
+  *                           - \ref NONSECURE_DPM
+  * @return     None.
+  * @details    This macro enables external debugger to write Secure or Non-secure DPM registers.
+  */
+void DPM_EnableDebuggerWriteAccess(uint32_t u32dpm)
+{
+    DPM_T *dpm;
+
+    if(__PC()&NS_OFFSET) dpm = DPM_NS;
+    else dpm = DPM;
+
+    if(u32dpm == SECURE_DPM) /* Secure DPM */
+    {
+        while(dpm->STS & DPM_STS_BUSY_Msk);
+        dpm->CTL = (dpm->CTL & (~(DPM_CTL_RVCODE_Msk | DPM_CTL_DACCWDIS_Msk))) | DPM_CTL_WVCODE;
+    }
+    else    /* Non-secure DPM */
+    {
+        while(dpm->NSSTS & DPM_NSSTS_BUSY_Msk);
+        dpm->NSCTL = (dpm->NSCTL & (~(DPM_NSCTL_RVCODE_Msk | DPM_NSCTL_DACCWDIS_Msk))) | DPM_NSCTL_WVCODE;
+    }
+}
+
+/**
+  * @brief      Disable Debugger Write Access
+  * @param[in]  u32dpm        Select DPM module. Valid values are:
+  *                           - \ref SECURE_DPM
+  *                           - \ref NONSECURE_DPM
+  * @return     None.
+  * @details    This macro disables external debugger to write Secure or Non-secure DPM registers.
+  */
+void DPM_DisableDebuggerWriteAccess(uint32_t u32dpm)
+{
+    DPM_T *dpm;
+
+    if(__PC()&NS_OFFSET) dpm = DPM_NS;
+    else dpm = DPM;
+
+    if(u32dpm == SECURE_DPM) /* Secure DPM */
+    {
+        while(dpm->STS & DPM_STS_BUSY_Msk);
+        dpm->CTL = (dpm->CTL & (~DPM_CTL_RVCODE_Msk)) | (DPM_CTL_WVCODE | DPM_CTL_DACCWDIS_Msk);
+    }
+    else    /* Non-secure DPM */
+    {
+        while(dpm->NSSTS & DPM_NSSTS_BUSY_Msk);
+        dpm->NSCTL = (dpm->NSCTL & (~DPM_NSCTL_RVCODE_Msk)) | (DPM_NSCTL_WVCODE | DPM_NSCTL_DACCWDIS_Msk);
+    }
+}
+
+
+/**@}*/ /* end of group DPM_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group DPM_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_eadc.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_eadc.c
new file mode 100644
index 0000000000..dcdc816327
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_eadc.c
@@ -0,0 +1,142 @@
+/**************************************************************************//**
+ * @file     eadc.c
+ * @version  V2.00
+ * @brief    M2354 series EADC driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup EADC_Driver EADC Driver
+  @{
+*/
+
+/** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions
+  @{
+*/
+
+/**
+  * @brief This function make EADC_module be ready to convert.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32InputMode Decides the input mode.
+  *                       - \ref EADC_CTL_DIFFEN_SINGLE_END      :Single end input mode.
+  *                       - \ref EADC_CTL_DIFFEN_DIFFERENTIAL    :Differential input type.
+  * @return None
+  * @details This function is used to set analog input mode and enable A/D Converter.
+  *         Before starting A/D conversion function, ADCEN bit (EADC_CTL[0]) should be set to 1.
+  * @note
+  */
+void EADC_Open(EADC_T *eadc, uint32_t u32InputMode)
+{
+    eadc->CTL &= (~(EADC_CTL_DIFFEN_Msk));
+
+    eadc->CTL |= (u32InputMode | EADC_CTL_ADCEN_Msk);
+
+    while(!(eadc->PWRM & EADC_PWRM_PWUPRDY_Msk)) {}
+}
+
+/**
+  * @brief Disable EADC_module.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @return None
+  * @details Clear ADCEN bit (EADC_CTL[0]) to disable A/D converter analog circuit power consumption.
+  */
+void EADC_Close(EADC_T *eadc)
+{
+    eadc->CTL &= ~EADC_CTL_ADCEN_Msk;
+}
+
+/**
+  * @brief Configure the sample control logic module.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
+  * @param[in] u32TriggerSrc Decides the trigger source. Valid values are:
+  *                            - \ref EADC_SOFTWARE_TRIGGER              : Disable trigger
+  *                            - \ref EADC_FALLING_EDGE_TRIGGER          : STADC pin falling edge trigger
+  *                            - \ref EADC_RISING_EDGE_TRIGGER           : STADC pin rising edge trigger
+  *                            - \ref EADC_FALLING_RISING_EDGE_TRIGGER   : STADC pin both falling and rising edge trigger
+  *                            - \ref EADC_ADINT0_TRIGGER                : ADC ADINT0 interrupt EOC pulse trigger
+  *                            - \ref EADC_ADINT1_TRIGGER                : ADC ADINT1 interrupt EOC pulse trigger
+  *                            - \ref EADC_TIMER0_TRIGGER                : Timer0 overflow pulse trigger
+  *                            - \ref EADC_TIMER1_TRIGGER                : Timer1 overflow pulse trigger
+  *                            - \ref EADC_TIMER2_TRIGGER                : Timer2 overflow pulse trigger
+  *                            - \ref EADC_TIMER3_TRIGGER                : Timer3 overflow pulse trigger
+  *                            - \ref EADC_PWM0TG0_TRIGGER               : EPWM0TG0 trigger
+  *                            - \ref EADC_PWM0TG1_TRIGGER               : EPWM0TG1 trigger
+  *                            - \ref EADC_PWM0TG2_TRIGGER               : EPWM0TG2 trigger
+  *                            - \ref EADC_PWM0TG3_TRIGGER               : EPWM0TG3 trigger
+  *                            - \ref EADC_PWM0TG4_TRIGGER               : EPWM0TG4 trigger
+  *                            - \ref EADC_PWM0TG5_TRIGGER               : EPWM0TG5 trigger
+  *                            - \ref EADC_PWM1TG0_TRIGGER               : EPWM1TG0 trigger
+  *                            - \ref EADC_PWM1TG1_TRIGGER               : EPWM1TG1 trigger
+  *                            - \ref EADC_PWM1TG2_TRIGGER               : EPWM1TG2 trigger
+  *                            - \ref EADC_PWM1TG3_TRIGGER               : EPWM1TG3 trigger
+  *                            - \ref EADC_PWM1TG4_TRIGGER               : EPWM1TG4 trigger
+  *                            - \ref EADC_PWM1TG5_TRIGGER               : EPWM1TG5 trigger
+  *                            - \ref EADC_BPWM0TG_TRIGGER               : BPWM0TG trigger
+  *                            - \ref EADC_BPWM1TG_TRIGGER               : BPWM1TG trigger
+  * @param[in] u32Channel Specifies the sample module channel, valid value are from 0 to 15.
+  * @return None
+  * @details Each of ADC control logic modules 0~15 which is configurable for ADC converter channel EADC_CH0~15 and trigger source.
+  *         sample module 16~18 is fixed for ADC channel 16, 17, 18 input sources as band-gap voltage, temperature sensor, and battery power (VBAT).
+  */
+void EADC_ConfigSampleModule(EADC_T *eadc, \
+                             uint32_t u32ModuleNum, \
+                             uint32_t u32TriggerSrc, \
+                             uint32_t u32Channel)
+{
+    eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | EADC_SCTL_TRGSEL_Msk | EADC_SCTL_CHSEL_Msk);
+    eadc->SCTL[u32ModuleNum] |= (u32TriggerSrc | u32Channel);
+}
+
+
+/**
+  * @brief Set trigger delay time.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
+  * @param[in] u32TriggerDelayTime Decides the trigger delay time, valid range are between 0~0xFF.
+  * @param[in] u32DelayClockDivider Decides the trigger delay clock divider. Valid values are:
+    *                                - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_1    : Trigger delay clock frequency is ADC_CLK/1
+    *                                - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_2    : Trigger delay clock frequency is ADC_CLK/2
+    *                                - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_4    : Trigger delay clock frequency is ADC_CLK/4
+    *                                - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_16   : Trigger delay clock frequency is ADC_CLK/16
+  * @return None
+  * @details User can configure the trigger delay time by setting TRGDLYCNT (EADC_SCTLn[15:8], n=0~15) and TRGDLYDIV (EADC_SCTLn[7:6], n=0~15).
+  *         Trigger delay time = (u32TriggerDelayTime) x Trigger delay clock period.
+  */
+void EADC_SetTriggerDelayTime(EADC_T *eadc, \
+                              uint32_t u32ModuleNum, \
+                              uint32_t u32TriggerDelayTime, \
+                              uint32_t u32DelayClockDivider)
+{
+    eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_TRGDLYDIV_Msk | EADC_SCTL_TRGDLYCNT_Msk);
+    eadc->SCTL[u32ModuleNum] |= ((u32TriggerDelayTime << EADC_SCTL_TRGDLYCNT_Pos) | u32DelayClockDivider);
+}
+
+/**
+  * @brief Set ADC extend sample time.
+  * @param[in] eadc The pointer of the specified EADC module.
+  * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.
+  * @param[in] u32ExtendSampleTime Decides the extend sampling time, the range is from 0~255 ADC clock. Valid value are from 0 to 0xFF.
+  * @return None
+  * @details When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy,
+  *         user can extend A/D sampling time after trigger source is coming to get enough sampling time.
+  */
+void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime)
+{
+    eadc->SCTL[u32ModuleNum] &= ~EADC_SCTL_EXTSMPT_Msk;
+
+    eadc->SCTL[u32ModuleNum] |= (u32ExtendSampleTime << EADC_SCTL_EXTSMPT_Pos);
+
+}
+
+/**@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group EADC_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_ebi.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_ebi.c
new file mode 100644
index 0000000000..e6dd92cfbe
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_ebi.c
@@ -0,0 +1,234 @@
+/**************************************************************************//**
+ * @file     ebi.c
+ * @version  V3.00
+ * @brief    External Bus Interface(EBI) driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup EBI_Driver EBI Driver
+  @{
+*/
+
+/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Initialize EBI for specify Bank
+  *
+  * @param[in]  u32Bank             Bank number for EBI. Valid values are:
+  *                                     - \ref EBI_BANK0
+  *                                     - \ref EBI_BANK1
+  *                                     - \ref EBI_BANK2
+  * @param[in]  u32DataWidth        Data bus width. Valid values are:
+  *                                     - \ref EBI_BUSWIDTH_8BIT
+  *                                     - \ref EBI_BUSWIDTH_16BIT
+  * @param[in]  u32TimingClass      Default timing configuration. Valid values are:
+  *                                     - \ref EBI_TIMING_FASTEST
+  *                                     - \ref EBI_TIMING_VERYFAST
+  *                                     - \ref EBI_TIMING_FAST
+  *                                     - \ref EBI_TIMING_NORMAL
+  *                                     - \ref EBI_TIMING_SLOW
+  *                                     - \ref EBI_TIMING_VERYSLOW
+  *                                     - \ref EBI_TIMING_SLOWEST
+  * @param[in]  u32BusMode          Set EBI bus operate mode. Valid values are:
+  *                                     - \ref EBI_OPMODE_NORMAL
+  *                                     - \ref EBI_OPMODE_CACCESS
+  *                                     - \ref EBI_OPMODE_ADSEPARATE
+  * @param[in]  u32CSActiveLevel    CS is active High/Low. Valid values are:
+  *                                     - \ref EBI_CS_ACTIVE_HIGH
+  *                                     - \ref EBI_CS_ACTIVE_LOW
+  *
+  * @return     None
+  *
+  * @details    This function is used to open specify EBI bank with different bus width, timing setting and \n
+  *             active level of CS pin to access EBI device.
+  * @note       Write Buffer Enable(WBUFEN) and Extend Time Of ALE(TALE) are only available in EBI bank0 control register.
+  */
+void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel)
+{
+    uint32_t u32Index0 = (uint32_t)&EBI->CTL0 + (u32Bank * 0x10UL);
+    uint32_t u32Index1 = (uint32_t)&EBI->TCTL0 + (u32Bank * 0x10UL);
+    volatile uint32_t *pu32EBICTL, *pu32EBITCTL;
+    uint32_t pu32Index0, pu32Index1;
+
+    if((__PC()&NS_OFFSET) == NS_OFFSET)
+    {
+        pu32Index0 = (u32Index0 | NS_OFFSET);
+        pu32Index1 = (u32Index1 | NS_OFFSET);
+    }
+    else
+    {
+        pu32Index0 = u32Index0;
+        pu32Index1 = u32Index1;
+    }
+
+    pu32EBICTL  = (uint32_t *)(pu32Index0);
+    pu32EBITCTL = (uint32_t *)(pu32Index1);
+
+    if(u32DataWidth == EBI_BUSWIDTH_8BIT)
+    {
+        *pu32EBICTL &= ~EBI_CTL_DW16_Msk;
+    }
+    else
+    {
+        *pu32EBICTL |= EBI_CTL_DW16_Msk;
+    }
+
+    *pu32EBICTL |= u32BusMode;
+
+    switch(u32TimingClass)
+    {
+        case EBI_TIMING_FASTEST:
+            *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
+                          (EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) |
+                          (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk;
+            *pu32EBITCTL = 0x0UL;
+            break;
+
+        case EBI_TIMING_VERYFAST:
+            *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
+                          (EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) |
+                          (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
+                          (0x3U << EBI_CTL_TALE_Pos) ;
+            *pu32EBITCTL = 0x03003318UL;
+            break;
+
+        case EBI_TIMING_FAST:
+            *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
+                          (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) |
+                          (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk;
+            *pu32EBITCTL = 0x0UL;
+            break;
+
+        case EBI_TIMING_NORMAL:
+            *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
+                          (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) |
+                          (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
+                          (0x3UL << EBI_CTL_TALE_Pos) ;
+            *pu32EBITCTL = 0x03003318UL;
+            break;
+
+        case EBI_TIMING_SLOW:
+            *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
+                          (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) |
+                          (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
+                          (0x7UL << EBI_CTL_TALE_Pos) ;
+            *pu32EBITCTL = 0x07007738UL;
+            break;
+
+        case EBI_TIMING_VERYSLOW:
+            *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
+                          (EBI_MCLKDIV_4 << EBI_CTL_MCLKDIV_Pos) |
+                          (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
+                          (0x7UL << EBI_CTL_TALE_Pos) ;
+            *pu32EBITCTL = 0x07007738UL;
+            break;
+
+        case EBI_TIMING_SLOWEST:
+            *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
+                          (EBI_MCLKDIV_8 << EBI_CTL_MCLKDIV_Pos) |
+                          (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
+                          (0x7UL << EBI_CTL_TALE_Pos) ;
+            *pu32EBITCTL = 0x07007738UL;
+            break;
+
+        default:
+            *pu32EBICTL &= ~EBI_CTL_EN_Msk;
+            break;
+    }
+}
+
+/**
+  * @brief      Disable EBI on specify Bank
+  *
+  * @param[in]  u32Bank     Bank number for EBI. Valid values are:
+  *                             - \ref EBI_BANK0
+  *                             - \ref EBI_BANK1
+  *                             - \ref EBI_BANK2
+  *
+  * @return     None
+  *
+  * @details    This function is used to close specify EBI function.
+  */
+void EBI_Close(uint32_t u32Bank)
+{
+    uint32_t u32Index = (uint32_t)&EBI->CTL0 + (u32Bank * 0x10UL);
+    volatile uint32_t *pu32EBICTL;
+    uint32_t pu32Index;
+
+    if((__PC()&NS_OFFSET) == NS_OFFSET)
+    {
+        pu32Index = (u32Index | NS_OFFSET);
+    }
+    else
+    {
+        pu32Index = u32Index;
+    }
+
+    pu32EBICTL  = (uint32_t *)(pu32Index);
+
+    *pu32EBICTL &= ~EBI_CTL_EN_Msk;
+}
+
+/**
+  * @brief      Set EBI Bus Timing for specify Bank
+  *
+  * @param[in]  u32Bank             Bank number for EBI. Valid values are:
+  *                                     - \ref EBI_BANK0
+  *                                     - \ref EBI_BANK1
+  *                                     - \ref EBI_BANK2
+  * @param[in]  u32TimingConfig     Configure EBI timing settings, includes TACC, TAHD, W2X and R2R setting.
+  * @param[in]  u32MclkDiv          Divider for MCLK. Valid values are:
+  *                                     - \ref EBI_MCLKDIV_1
+  *                                     - \ref EBI_MCLKDIV_2
+  *                                     - \ref EBI_MCLKDIV_4
+  *                                     - \ref EBI_MCLKDIV_8
+  *                                     - \ref EBI_MCLKDIV_16
+  *                                     - \ref EBI_MCLKDIV_32
+  *                                     - \ref EBI_MCLKDIV_64
+  *                                     - \ref EBI_MCLKDIV_128
+  *
+  * @return     None
+  *
+  * @details    This function is used to configure specify EBI bus timing for access EBI device.
+  */
+void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv)
+{
+    uint32_t u32Index0 = (uint32_t)&EBI->CTL0 + (u32Bank * 0x10UL);
+    uint32_t u32Index1 = (uint32_t)&EBI->TCTL0 + (u32Bank * 0x10UL);
+    volatile uint32_t *pu32EBICTL, *pu32EBITCTL;
+    uint32_t pu32Index0, pu32Index1;
+
+    if((__PC()&NS_OFFSET) == NS_OFFSET)
+    {
+        pu32Index0 = (u32Index0 | NS_OFFSET);
+        pu32Index1 = (u32Index1 | NS_OFFSET);
+    }
+    else
+    {
+        pu32Index0 = u32Index0;
+        pu32Index1 = u32Index1;
+    }
+
+    pu32EBICTL  = (uint32_t *)(pu32Index0);
+    pu32EBITCTL = (uint32_t *)(pu32Index1);
+
+    *pu32EBICTL = (*pu32EBICTL & ~EBI_CTL_MCLKDIV_Msk) | (u32MclkDiv << EBI_CTL_MCLKDIV_Pos);
+    *pu32EBITCTL = u32TimingConfig;
+}
+
+/**@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group EBI_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_ecap.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_ecap.c
new file mode 100644
index 0000000000..1a9d31618e
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_ecap.c
@@ -0,0 +1,119 @@
+/**************************************************************************//**
+ * @file     ecap.c
+ * @version  V3.00
+
+ * @brief    Enhanced Input Capture Timer (ECAP) driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup ECAP_Driver ECAP Driver
+  @{
+*/
+
+/** @addtogroup ECAP_EXPORTED_FUNCTIONS ECAP Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Enable ECAP function
+  * @param[in]  ecap        The pointer of the specified ECAP module.
+  * @param[in]  u32FuncMask Input capture function select
+  *                         - \ref ECAP_DISABLE_COMPARE
+  *                         - \ref ECAP_COMPARE_FUNCTION
+  * @return     None
+  * @details    This macro enable input capture function and select compare and reload function.
+  */
+void ECAP_Open(ECAP_T* ecap, uint32_t u32FuncMask)
+{
+    /* Clear Input capture mode*/
+    ecap->CTL0 = ecap->CTL0 & ~(ECAP_CTL0_CMPEN_Msk);
+
+    /* Enable Input Capture and set mode */
+    ecap->CTL0 |= ECAP_CTL0_CAPEN_Msk | (u32FuncMask);
+}
+
+
+
+/**
+  * @brief      Disable ECAP function
+  * @param[in]  ecap        The pointer of the specified ECAP module.
+  * @return     None
+  * @details    This macro disable input capture function.
+  */
+void ECAP_Close(ECAP_T* ecap)
+{
+    /* Disable Input Capture*/
+    ecap->CTL0 &= ~ECAP_CTL0_CAPEN_Msk;
+}
+
+/**
+  * @brief This macro is used to enable input channel interrupt
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32Mask  The input channel Mask
+  *                  - \ref ECAP_CTL0_CAPIEN0_Msk
+  *                  - \ref ECAP_CTL0_CAPIEN1_Msk
+  *                  - \ref ECAP_CTL0_CAPIEN2_Msk
+  *                  - \ref ECAP_CTL0_OVIEN_Msk
+  *                  - \ref ECAP_CTL0_CMPIEN_Msk
+  * @return None
+  * @details This macro will enable the input channel_n interrupt.
+  */
+void ECAP_EnableINT(ECAP_T* ecap, uint32_t u32Mask)
+{
+    /* Enable input channel interrupt */
+    ecap->CTL0 |= (u32Mask);
+
+    /* Enable NVIC ECAP IRQ */
+    if((ecap == ECAP0) || (ecap == ECAP0_NS))
+    {
+        NVIC_EnableIRQ(ECAP0_IRQn);
+    }
+    else
+    {
+        NVIC_EnableIRQ(ECAP1_IRQn);
+    }
+}
+
+/**
+  * @brief This macro is used to disable input channel interrupt
+  * @param[in] ecap      Specify ECAP port
+  * @param[in] u32Mask  The input channel number
+  *                  - \ref ECAP_CTL0_CAPIEN0_Msk
+  *                  - \ref ECAP_CTL0_CAPIEN1_Msk
+  *                  - \ref ECAP_CTL0_CAPIEN2_Msk
+  *                  - \ref ECAP_CTL0_OVIEN_Msk
+  *                  - \ref ECAP_CTL0_CMPIEN_Msk
+  * @return None
+  * @details This macro will disable the input channel_n interrupt.
+  */
+void ECAP_DisableINT(ECAP_T* ecap, uint32_t u32Mask)
+{
+    /* Disable input channel interrupt */
+    (ecap->CTL0) &= ~(u32Mask);
+
+    /* Disable NVIC ECAP IRQ */
+    if((ecap == ECAP0) || (ecap == ECAP0_NS))
+    {
+        NVIC_DisableIRQ(ECAP0_IRQn);
+    }
+    else
+    {
+        NVIC_DisableIRQ(ECAP1_IRQn);
+    }
+}
+
+/**@}*/ /* end of group ECAP_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group ECAP_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_epwm.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_epwm.c
new file mode 100644
index 0000000000..e9050e1de7
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_epwm.c
@@ -0,0 +1,1659 @@
+/**************************************************************************//**
+ * @file     epwm.c
+ * @version  V3.00
+ * @brief    M2354 series EPWM driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup EPWM_Driver EPWM Driver
+  @{
+*/
+
+
+/** @addtogroup EPWM_EXPORTED_FUNCTIONS EPWM Exported Functions
+  @{
+*/
+
+/**
+ * @brief Configure EPWM capture and get the nearest unit time.
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32UnitTimeNsec The unit time of counter
+ * @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used
+ * @return The nearest unit time in nano second.
+ * @details This function is used to Configure EPWM capture and get the nearest unit time.
+ */
+uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge)
+{
+    uint32_t u32PWMClockSrc;
+    uint32_t u32NearestUnitTimeNsec = 0;
+    uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU;
+    uint8_t u8BreakLoop = 0U;
+
+    (void)u32CaptureEdge;
+
+    /* clock source is from PCLK */
+    if((epwm == EPWM0) || (epwm == EPWM0_NS))
+    {
+        u32PWMClockSrc = CLK_GetPCLK0Freq();
+    }
+    else /* if((epwm == EPWM1)||(epwm == EPWM1_NS)) */
+    {
+        u32PWMClockSrc = CLK_GetPCLK1Freq();
+    }
+
+    u32PWMClockSrc /= 1000UL;
+    for(u32Prescale = 1U; u32Prescale <= 0x1000U; u32Prescale++)
+    {
+        u32NearestUnitTimeNsec = (1000000UL * u32Prescale) / u32PWMClockSrc;
+        if(u32NearestUnitTimeNsec < u32UnitTimeNsec)
+        {
+            if(u32Prescale == 0x1000U)  /* limit to the maximum unit time(nano second) */
+            {
+                u8BreakLoop = 1U;
+            }
+            if(!((1000000UL * (u32Prescale + 1UL) > (u32NearestUnitTimeNsec * u32PWMClockSrc))))
+            {
+                u8BreakLoop = 1U;
+            }
+        }
+        else
+        {
+            u8BreakLoop = 1U;
+        }
+        if(u8BreakLoop)
+        {
+            break;
+        }
+    }
+
+    /* convert to real register value */
+    u32Prescale = u32Prescale - 1U;
+    /* every two channels share a prescaler */
+    EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescale);
+
+    /* set EPWM to down count type(edge aligned) */
+    (epwm)->CTL1 = ((epwm)->CTL1 & ~(EPWM_CTL1_CNTTYPE0_Msk << (u32ChannelNum << 1))) | (1UL << (u32ChannelNum << 1));
+    /* set EPWM to auto-reload mode */
+    (epwm)->CTL1 &= ~(EPWM_CTL1_CNTMODE0_Msk << u32ChannelNum);
+    EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR);
+
+    return (u32NearestUnitTimeNsec);
+}
+
+/**
+ * @brief This function Configure EPWM generator and get the nearest frequency in edge aligned(up counter type) auto-reload mode
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Frequency Target generator frequency
+ * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
+ * @return Nearest frequency clock in nano second
+ * @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure EPWM frequency may affect
+ *       existing frequency of other channel.
+ * @note This function is used for initial stage.
+ *       To change duty cycle later, it should get the configured period value and calculate the new comparator value.
+ */
+uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle)
+{
+    uint32_t u32PWMClockSrc;
+    uint32_t i;
+    uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU;
+
+    /* clock source is from PCLK */
+    if((epwm == EPWM0) || (epwm == EPWM0_NS))
+    {
+        u32PWMClockSrc = CLK_GetPCLK0Freq();
+    }
+    else /* if((epwm == EPWM1)||(epwm == EPWM1_NS)) */
+    {
+        u32PWMClockSrc = CLK_GetPCLK1Freq();
+    }
+
+    for(u32Prescale = 1U; u32Prescale < 0xFFFU; u32Prescale++)/* prescale could be 0~0xFFF */
+    {
+        i = (u32PWMClockSrc / u32Frequency) / u32Prescale;
+        /* If target value is larger than CNR, need to use a larger prescaler */
+        if(i <= (0x10000U))
+        {
+            u32CNR = i;
+            break;
+        }
+    }
+    /* Store return value here 'cos we're gonna change u32Prescale & u32CNR to the real value to fill into register */
+    i = u32PWMClockSrc / (u32Prescale * u32CNR);
+
+    /* convert to real register value */
+    u32Prescale = u32Prescale - 1U;
+    /* every two channels share a prescaler */
+    EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescale);
+    /* set EPWM to up counter type(edge aligned) and auto-reload mode */
+    (epwm)->CTL1 = ((epwm)->CTL1 & ~((EPWM_CTL1_CNTTYPE0_Msk << (u32ChannelNum << 1)) | (EPWM_CTL1_CNTMODE0_Msk << u32ChannelNum)));
+
+    u32CNR = u32CNR - 1U;
+    EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR);
+    EPWM_SET_CMR(epwm, u32ChannelNum, u32DutyCycle * (u32CNR + 1UL) / 100UL);
+
+    (epwm)->WGCTL0 = ((epwm)->WGCTL0 & ~((EPWM_WGCTL0_PRDPCTL0_Msk | EPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1))) | \
+                     (EPWM_OUTPUT_HIGH << (u32ChannelNum << 1UL << EPWM_WGCTL0_ZPCTL0_Pos));
+    (epwm)->WGCTL1 = ((epwm)->WGCTL1 & ~((EPWM_WGCTL1_CMPDCTL0_Msk | EPWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum << 1))) | \
+                     (EPWM_OUTPUT_LOW << (u32ChannelNum << 1UL << EPWM_WGCTL1_CMPUCTL0_Pos));
+
+    return(i);
+}
+
+/**
+ * @brief Start EPWM module
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ *                           Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to start EPWM module.
+ */
+void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+    (epwm)->CNTEN |= u32ChannelMask;
+}
+
+/**
+ * @brief Stop EPWM module
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ *                           Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to stop EPWM module.
+ */
+void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+    uint32_t i;
+    for(i = 0UL; i < EPWM_CHANNEL_NUM; i ++)
+    {
+        if(u32ChannelMask & (1UL << i))
+        {
+            (epwm)->PERIOD[i] = 0UL;
+        }
+    }
+}
+
+/**
+ * @brief Stop EPWM generation immediately by clear channel enable bit
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ *                           Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to stop EPWM generation immediately by clear channel enable bit.
+ */
+void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+    (epwm)->CNTEN &= ~u32ChannelMask;
+}
+
+/**
+ * @brief Enable selected channel to trigger ADC
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Condition The condition to trigger ADC. Combination of following conditions:
+ *                  - \ref EPWM_TRG_ADC_EVEN_ZERO
+ *                  - \ref EPWM_TRG_ADC_EVEN_PERIOD
+ *                  - \ref EPWM_TRG_ADC_EVEN_ZERO_PERIOD
+ *                  - \ref EPWM_TRG_ADC_EVEN_COMPARE_UP
+ *                  - \ref EPWM_TRG_ADC_EVEN_COMPARE_DOWN
+ *                  - \ref EPWM_TRG_ADC_ODD_ZERO
+ *                  - \ref EPWM_TRG_ADC_ODD_PERIOD
+ *                  - \ref EPWM_TRG_ADC_ODD_ZERO_PERIOD
+ *                  - \ref EPWM_TRG_ADC_ODD_COMPARE_UP
+ *                  - \ref EPWM_TRG_ADC_ODD_COMPARE_DOWN
+ *                  - \ref EPWM_TRG_ADC_CH_0_FREE_CMP_UP
+ *                  - \ref EPWM_TRG_ADC_CH_0_FREE_CMP_DOWN
+ *                  - \ref EPWM_TRG_ADC_CH_2_FREE_CMP_UP
+ *                  - \ref EPWM_TRG_ADC_CH_2_FREE_CMP_DOWN
+ *                  - \ref EPWM_TRG_ADC_CH_4_FREE_CMP_UP
+ *                  - \ref EPWM_TRG_ADC_CH_4_FREE_CMP_DOWN
+ * @return None
+ * @details This function is used to enable selected channel to trigger ADC.
+ */
+void EPWM_EnableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+    if(u32ChannelNum < 4UL)
+    {
+        (epwm)->EADCTS0 &= ~((EPWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum << 3));
+        (epwm)->EADCTS0 |= ((EPWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum << 3));
+    }
+    else
+    {
+        (epwm)->EADCTS1 &= ~((EPWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4UL) << 3));
+        (epwm)->EADCTS1 |= ((EPWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4UL) << 3));
+    }
+}
+
+/**
+ * @brief Disable selected channel to trigger ADC
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable selected channel to trigger ADC.
+ */
+void EPWM_DisableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    if(u32ChannelNum < 4UL)
+    {
+        (epwm)->EADCTS0 &= ~(EPWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum << 3));
+    }
+    else
+    {
+        (epwm)->EADCTS1 &= ~(EPWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4UL) << 3));
+    }
+}
+
+/**
+ * @brief Enable and configure trigger ADC prescale
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5.
+ * @param[in] u32Prescale ADC prescale. Valid values are between 0 to 0xF.
+ * @param[in] u32PrescaleCnt ADC prescale counter. Valid values are between 0 to 0xF.
+ * @retval 0 Success.
+ * @retval -1 Failed.
+ * @details This function is used to enable and configure trigger ADC prescale.
+ * @note User can configure only when ADC trigger prescale is disabled.
+ * @note ADC prescale counter must less than ADC prescale.
+ */
+int32_t EPWM_EnableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Prescale, uint32_t u32PrescaleCnt)
+{
+    /* User can write only when PSCENn(n = 0 ~ 5) is 0 */
+    if((epwm)->EADCPSCCTL & (1UL << u32ChannelNum))
+        return (-1);
+
+    if(u32ChannelNum < 4UL)
+    {
+        (epwm)->EADCPSC0 = ((epwm)->EADCPSC0 & ~((EPWM_EADCPSC0_EADCPSC0_Msk) << (u32ChannelNum << 3))) | \
+                           (u32Prescale << (u32ChannelNum << 3));
+        (epwm)->EADCPSCNT0 = ((epwm)->EADCPSCNT0 & ~((EPWM_EADCPSCNT0_PSCNT0_Msk) << (u32ChannelNum << 3))) | \
+                             (u32PrescaleCnt << (u32ChannelNum << 3));
+    }
+    else
+    {
+        (epwm)->EADCPSC1 = ((epwm)->EADCPSC1 & ~((EPWM_EADCPSC1_EADCPSC4_Msk) << ((u32ChannelNum - 4UL) << 3))) | \
+                           (u32Prescale << ((u32ChannelNum - 4UL) << 3));
+        (epwm)->EADCPSCNT1 = ((epwm)->EADCPSCNT1 & ~((EPWM_EADCPSCNT1_PSCNT4_Msk) << ((u32ChannelNum - 4UL) << 3))) | \
+                             (u32PrescaleCnt << ((u32ChannelNum - 4UL) << 3));
+    }
+
+    (epwm)->EADCPSCCTL |= EPWM_EADCPSCCTL_PSCEN0_Msk << u32ChannelNum;
+
+    return 0;
+}
+
+/**
+ * @brief Disable Trigger ADC prescale function
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable trigger ADC prescale.
+ */
+void EPWM_DisableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->EADCPSCCTL &= ~(EPWM_EADCPSCCTL_PSCEN0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Clear selected channel trigger ADC flag
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Condition This parameter is not used
+ * @return None
+ * @details This function is used to clear selected channel trigger ADC flag.
+ */
+void EPWM_ClearADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+    (void)u32Condition;
+    (epwm)->STATUS = (EPWM_STATUS_EADCTRGF0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Get selected channel trigger ADC flag
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @retval 0 The specified channel trigger ADC to start of conversion flag is not set
+ * @retval 1 The specified channel trigger ADC to start of conversion flag is set
+ * @details This function is used to get EPWM trigger ADC to start of conversion flag for specified channel.
+ */
+uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    return (((epwm)->STATUS & (EPWM_STATUS_EADCTRGF0_Msk << u32ChannelNum)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable selected channel to trigger DAC
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Condition The condition to trigger DAC. Combination of following conditions:
+ *                  - \ref EPWM_TRIGGER_DAC_ZERO
+ *                  - \ref EPWM_TRIGGER_DAC_PERIOD
+ *                  - \ref EPWM_TRIGGER_DAC_COMPARE_UP
+ *                  - \ref EPWM_TRIGGER_DAC_COMPARE_DOWN
+ * @return None
+ * @details This function is used to enable selected channel to trigger DAC.
+ */
+void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+    (epwm)->DACTRGEN |= (u32Condition << u32ChannelNum);
+}
+
+/**
+ * @brief Disable selected channel to trigger DAC
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable selected channel to trigger DAC.
+ */
+void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->DACTRGEN &= ~((EPWM_TRIGGER_DAC_ZERO | EPWM_TRIGGER_DAC_PERIOD | EPWM_TRIGGER_DAC_COMPARE_UP | EPWM_TRIGGER_DAC_COMPARE_DOWN) << u32ChannelNum);
+}
+
+/**
+ * @brief Clear selected channel trigger DAC flag
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. This parameter is not used
+ * @param[in] u32Condition The condition to trigger DAC. This parameter is not used
+ * @return None
+ * @details This function is used to clear selected channel trigger DAC flag.
+ */
+void EPWM_ClearDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition)
+{
+    (void)u32ChannelNum;
+    (void)u32Condition;
+    (epwm)->STATUS = EPWM_STATUS_DACTRGF_Msk;
+}
+
+/**
+ * @brief Get selected channel trigger DAC flag
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. This parameter is not used
+ * @retval 0 The specified channel trigger DAC to start of conversion flag is not set
+ * @retval 1 The specified channel trigger DAC to start of conversion flag is set
+ * @details This function is used to get selected channel trigger DAC flag.
+ */
+uint32_t EPWM_GetDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (void)u32ChannelNum;
+    return (((epwm)->STATUS & EPWM_STATUS_DACTRGF_Msk) ? 1UL : 0UL);
+}
+
+/**
+ * @brief This function enable fault brake of selected channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ * @param[in] u32LevelMask Output high or low while fault brake occurs, each bit represent the level of a channel
+ *                         while fault brake occurs. Bit 0 represents channel 0, bit 1 represents channel 1...
+ * @param[in] u32BrakeSource Fault brake source, could be one of following source
+ *                  - \ref EPWM_FB_EDGE_ADCRM
+ *                  - \ref EPWM_FB_EDGE_ACMP0
+ *                  - \ref EPWM_FB_EDGE_ACMP1
+ *                  - \ref EPWM_FB_EDGE_BKP0
+ *                  - \ref EPWM_FB_EDGE_BKP1
+ *                  - \ref EPWM_FB_EDGE_SYS_CSS
+ *                  - \ref EPWM_FB_EDGE_SYS_BOD
+ *                  - \ref EPWM_FB_EDGE_SYS_RAM
+ *                  - \ref EPWM_FB_EDGE_SYS_COR
+ *                  - \ref EPWM_FB_LEVEL_ADCRM
+ *                  - \ref EPWM_FB_LEVEL_ACMP0
+ *                  - \ref EPWM_FB_LEVEL_ACMP1
+ *                  - \ref EPWM_FB_LEVEL_BKP0
+ *                  - \ref EPWM_FB_LEVEL_BKP1
+ *                  - \ref EPWM_FB_LEVEL_SYS_CSS
+ *                  - \ref EPWM_FB_LEVEL_SYS_BOD
+ *                  - \ref EPWM_FB_LEVEL_SYS_RAM
+ *                  - \ref EPWM_FB_LEVEL_SYS_COR
+ * @return None
+ * @details This function is used to enable fault brake of selected channel(s).
+ *          The write-protection function should be disabled before using this function.
+ */
+void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource)
+{
+    uint32_t i;
+
+    for(i = 0UL; i < EPWM_CHANNEL_NUM; i++)
+    {
+        if(u32ChannelMask & (1UL << i))
+        {
+            if((u32BrakeSource == EPWM_FB_EDGE_SYS_CSS) || (u32BrakeSource == EPWM_FB_EDGE_SYS_BOD) || \
+                    (u32BrakeSource == EPWM_FB_EDGE_SYS_RAM) || (u32BrakeSource == EPWM_FB_EDGE_SYS_COR) || \
+                    (u32BrakeSource == EPWM_FB_LEVEL_SYS_CSS) || (u32BrakeSource == EPWM_FB_LEVEL_SYS_BOD) || \
+                    (u32BrakeSource == EPWM_FB_LEVEL_SYS_RAM) || (u32BrakeSource == EPWM_FB_LEVEL_SYS_COR))
+            {
+                (epwm)->BRKCTL[i >> 1] |= (u32BrakeSource & (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_BRKCTL0_1_SYSLBEN_Msk));
+                (epwm)->FAILBRK |= (u32BrakeSource & 0xFUL);
+            }
+            else
+            {
+                (epwm)->BRKCTL[i >> 1] |= u32BrakeSource;
+            }
+        }
+
+        if(u32LevelMask & (1UL << i))
+        {
+            if((i & 0x1UL) == 0UL)
+            {
+                /* set brake action as high level for even channel */
+                (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAEVEN_Msk;
+                (epwm)->BRKCTL[i >> 1] |= ((3UL) << EPWM_BRKCTL0_1_BRKAEVEN_Pos);
+            }
+            else
+            {
+                /* set brake action as high level for odd channel */
+                (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAODD_Msk;
+                (epwm)->BRKCTL[i >> 1] |= ((3UL) << EPWM_BRKCTL0_1_BRKAODD_Pos);
+            }
+        }
+        else
+        {
+            if((i & 0x1UL) == 0UL)
+            {
+                /* set brake action as low level for even channel */
+                (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAEVEN_Msk;
+                (epwm)->BRKCTL[i >> 1] |= ((2UL) << EPWM_BRKCTL0_1_BRKAEVEN_Pos);
+            }
+            else
+            {
+                /* set brake action as low level for odd channel */
+                (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAODD_Msk;
+                (epwm)->BRKCTL[i >> 1] |= ((2UL) << EPWM_BRKCTL0_1_BRKAODD_Pos);
+            }
+        }
+    }
+}
+
+/**
+ * @brief Enable capture of selected channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ *                           Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to enable capture of selected channel(s).
+ */
+void EPWM_EnableCapture(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+    (epwm)->CAPINEN |= u32ChannelMask;
+    (epwm)->CAPCTL |= u32ChannelMask;
+}
+
+/**
+ * @brief Disable capture of selected channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ *                           Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to disable capture of selected channel(s).
+ */
+void EPWM_DisableCapture(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+    (epwm)->CAPINEN &= ~u32ChannelMask;
+    (epwm)->CAPCTL &= ~u32ChannelMask;
+}
+
+/**
+ * @brief Enables EPWM output generation of selected channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ *                           Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...
+ * @return None
+ * @details This function is used to enable EPWM output generation of selected channel(s).
+ */
+void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+    (epwm)->POEN |= u32ChannelMask;
+}
+
+/**
+ * @brief Disables EPWM output generation of selected channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
+ *                           Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output...
+ * @return None
+ * @details This function is used to disable EPWM output generation of selected channel(s).
+ */
+void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+    (epwm)->POEN &= ~u32ChannelMask;
+}
+
+/**
+ * @brief Enables PDMA transfer of selected channel for EPWM capture
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number.
+ * @param[in] u32RisingFirst The capture order is rising, falling first. Every two channels share the same setting. Valid values are TRUE and FALSE.
+ * @param[in] u32Mode Captured data transferred by PDMA interrupt type. It could be either
+ *              - \ref EPWM_CAPTURE_PDMA_RISING_LATCH
+ *              - \ref EPWM_CAPTURE_PDMA_FALLING_LATCH
+ *              - \ref EPWM_CAPTURE_PDMA_RISING_FALLING_LATCH
+ * @return None
+ * @details This function is used to enable PDMA transfer of selected channel(s) for EPWM capture.
+ * @note This function can only selects even or odd channel of pairs to do PDMA transfer.
+ */
+void EPWM_EnablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode)
+{
+    uint32_t u32IsOddCh;
+    u32IsOddCh = u32ChannelNum & 0x1UL;
+    (epwm)->PDMACTL = ((epwm)->PDMACTL & ~((EPWM_PDMACTL_CHSEL0_1_Msk | EPWM_PDMACTL_CAPORD0_1_Msk | EPWM_PDMACTL_CAPMOD0_1_Msk) << ((u32ChannelNum >> 1) << 3))) | \
+                      (((u32IsOddCh << EPWM_PDMACTL_CHSEL0_1_Pos) | (u32RisingFirst << EPWM_PDMACTL_CAPORD0_1_Pos) | \
+                        u32Mode | EPWM_PDMACTL_CHEN0_1_Msk) << ((u32ChannelNum >> 1) << 3));
+}
+
+/**
+ * @brief Disables PDMA transfer of selected channel for EPWM capture
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number.
+ * @return None
+ * @details This function is used to enable PDMA transfer of selected channel(s) for EPWM capture.
+ */
+void EPWM_DisablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->PDMACTL &= ~(EPWM_PDMACTL_CHEN0_1_Msk << ((u32ChannelNum >> 1) << 3));
+}
+
+/**
+ * @brief Enable Dead zone of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Duration Dead zone length in EPWM clock count, valid values are between 0~0xFFF, but 0 means there is no Dead zone.
+ * @return None
+ * @details This function is used to enable Dead zone of selected channel.
+ *          The write-protection function should be disabled before using this function.
+ * @note Every two channels share the same setting.
+ */
+void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration)
+{
+    /* every two channels share the same setting */
+    (epwm)->DTCTL[(u32ChannelNum) >> 1] &= ~EPWM_DTCTL0_1_DTCNT_Msk;
+    (epwm)->DTCTL[(u32ChannelNum) >> 1] |= EPWM_DTCTL0_1_DTEN_Msk | u32Duration;
+}
+
+/**
+ * @brief Disable Dead zone of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable Dead zone of selected channel.
+ *          The write-protection function should be disabled before using this function.
+ */
+void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    /* every two channels shares the same setting */
+    (epwm)->DTCTL[(u32ChannelNum) >> 1] &= ~EPWM_DTCTL0_1_DTEN_Msk;
+}
+
+/**
+ * @brief Enable capture interrupt of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Edge Rising or falling edge to latch counter.
+ *              - \ref EPWM_CAPTURE_INT_RISING_LATCH
+ *              - \ref EPWM_CAPTURE_INT_FALLING_LATCH
+ * @return None
+ * @details This function is used to enable capture interrupt of selected channel.
+ */
+void EPWM_EnableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+    (epwm)->CAPIEN |= (u32Edge << u32ChannelNum);
+}
+
+/**
+ * @brief Disable capture interrupt of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Edge Rising or falling edge to latch counter.
+ *              - \ref EPWM_CAPTURE_INT_RISING_LATCH
+ *              - \ref EPWM_CAPTURE_INT_FALLING_LATCH
+ * @return None
+ * @details This function is used to disable capture interrupt of selected channel.
+ */
+void EPWM_DisableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+    (epwm)->CAPIEN &= ~(u32Edge << u32ChannelNum);
+}
+
+/**
+ * @brief Clear capture interrupt of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32Edge Rising or falling edge to latch counter.
+ *              - \ref EPWM_CAPTURE_INT_RISING_LATCH
+ *              - \ref EPWM_CAPTURE_INT_FALLING_LATCH
+ * @return None
+ * @details This function is used to clear capture interrupt of selected channel.
+ */
+void EPWM_ClearCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge)
+{
+    (epwm)->CAPIF = (u32Edge << u32ChannelNum);
+}
+
+/**
+ * @brief Get capture interrupt of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @retval 0 No capture interrupt
+ * @retval 1 Rising edge latch interrupt
+ * @retval 2 Falling edge latch interrupt
+ * @retval 3 Rising and falling latch interrupt
+ * @details This function is used to get capture interrupt of selected channel.
+ */
+uint32_t EPWM_GetCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    uint32_t u32CapIf = 0UL;
+
+    u32CapIf = ((((epwm)->CAPIF & (EPWM_CAPIF_CFLIF0_Msk << u32ChannelNum)) ? 1UL : 0UL) << 1);
+    u32CapIf |= (((epwm)->CAPIF & (EPWM_CAPIF_CRLIF0_Msk << u32ChannelNum)) ? 1UL : 0UL);
+    return u32CapIf;
+}
+/**
+ * @brief Enable duty interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32IntDutyType Duty interrupt type, could be either
+ *              - \ref EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP
+ *              - \ref EPWM_DUTY_INT_UP_COUNT_MATCH_CMP
+ * @return None
+ * @details This function is used to enable duty interrupt of selected channel.
+ */
+void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
+{
+    (epwm)->INTEN0 |= (u32IntDutyType << u32ChannelNum);
+}
+
+/**
+ * @brief Disable duty interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable duty interrupt of selected channel.
+ */
+void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->INTEN0 &= ~((EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | EPWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum);
+}
+
+/**
+ * @brief Clear duty interrupt flag of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear duty interrupt flag of selected channel.
+ */
+void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->INTSTS0 = (EPWM_INTSTS0_CMPUIF0_Msk | EPWM_INTSTS0_CMPDIF0_Msk) << u32ChannelNum;
+}
+
+/**
+ * @brief Get duty interrupt flag of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Duty interrupt flag of specified channel
+ * @retval 0 Duty interrupt did not occur
+ * @retval 1 Duty interrupt occurred
+ * @details This function is used to get duty interrupt flag of selected channel.
+ */
+uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    return ((((epwm)->INTSTS0 & ((EPWM_INTSTS0_CMPDIF0_Msk | EPWM_INTSTS0_CMPUIF0_Msk) << u32ChannelNum))) ? 1UL : 0UL);
+}
+
+/**
+ * @brief This function enable fault brake interrupt
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32BrakeSource Fault brake source.
+ *              - \ref EPWM_FB_EDGE
+ *              - \ref EPWM_FB_LEVEL
+ * @return None
+ * @details This function is used to enable fault brake interrupt.
+ *          The write-protection function should be disabled before using this function.
+ * @note Every two channels share the same setting.
+ */
+void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource)
+{
+    (epwm)->INTEN1 |= (0x7UL << u32BrakeSource);
+}
+
+/**
+ * @brief This function disable fault brake interrupt
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32BrakeSource Fault brake source.
+ *              - \ref EPWM_FB_EDGE
+ *              - \ref EPWM_FB_LEVEL
+ * @return None
+ * @details This function is used to disable fault brake interrupt.
+ *          The write-protection function should be disabled before using this function.
+ * @note Every two channels share the same setting.
+ */
+void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource)
+{
+    (epwm)->INTEN1 &= ~(0x7UL << u32BrakeSource);
+}
+
+/**
+ * @brief This function clear fault brake interrupt of selected source
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32BrakeSource Fault brake source.
+ *              - \ref EPWM_FB_EDGE
+ *              - \ref EPWM_FB_LEVEL
+ * @return None
+ * @details This function is used to clear fault brake interrupt of selected source.
+ *          The write-protection function should be disabled before using this function.
+ */
+void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource)
+{
+    (epwm)->INTSTS1 = (0x3fUL << u32BrakeSource);
+}
+
+/**
+ * @brief This function get fault brake interrupt flag of selected source
+ * @param[in] epwm The pointer of the specified EPWM module
+ * @param[in] u32BrakeSource Fault brake source, could be either
+ *              - \ref EPWM_FB_EDGE
+ *              - \ref EPWM_FB_LEVEL
+ * @return Fault brake interrupt flag of specified source
+ * @retval 0 Fault brake interrupt did not occurred
+ * @retval 1 Fault brake interrupt occurred
+ * @details This function is used to get fault brake interrupt flag of selected source.
+ */
+uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource)
+{
+    return (((epwm)->INTSTS1 & (0x3fUL << u32BrakeSource)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable period interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32IntPeriodType Period interrupt type. This parameter is not used.
+ * @return None
+ * @details This function is used to enable period interrupt of selected channel.
+ */
+void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum,  uint32_t u32IntPeriodType)
+{
+    (void)u32IntPeriodType;
+    (epwm)->INTEN0 |= (EPWM_INTEN0_PIEN0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Disable period interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable period interrupt of selected channel.
+ */
+void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->INTEN0 &= ~(EPWM_INTEN0_PIEN0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Clear period interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear period interrupt of selected channel.
+ */
+void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->INTSTS0 = (EPWM_INTSTS0_PIF0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Get period interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Period interrupt flag of specified channel
+ * @retval 0 Period interrupt did not occur
+ * @retval 1 Period interrupt occurred
+ * @details This function is used to get period interrupt of selected channel.
+ */
+uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    return ((((epwm)->INTSTS0 & (EPWM_INTSTS0_PIF0_Msk << u32ChannelNum))) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable zero interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to enable zero interrupt of selected channel.
+ */
+void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->INTEN0 |= (EPWM_INTEN0_ZIEN0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Disable zero interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable zero interrupt of selected channel.
+ */
+void EPWM_DisableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->INTEN0 &= ~(EPWM_INTEN0_ZIEN0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Clear zero interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear zero interrupt of selected channel.
+ */
+void EPWM_ClearZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->INTSTS0 = (EPWM_INTSTS0_ZIF0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Get zero interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Zero interrupt flag of specified channel
+ * @retval 0 Zero interrupt did not occur
+ * @retval 1 Zero interrupt occurred
+ * @details This function is used to get zero interrupt of selected channel.
+ */
+uint32_t EPWM_GetZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    return ((((epwm)->INTSTS0 & (EPWM_INTSTS0_ZIF0_Msk << u32ChannelNum))) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable interrupt flag accumulator of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32IntFlagCnt Interrupt flag counter. Valid values are between 0~65535.
+ * @param[in] u32IntAccSrc Interrupt flag accumulator source selection.
+ *              - \ref EPWM_IFA_ZERO_POINT
+ *              - \ref EPWM_IFA_PERIOD_POINT
+ *              - \ref EPWM_IFA_COMPARE_UP_COUNT_POINT
+ *              - \ref EPWM_IFA_COMPARE_DOWN_COUNT_POINT
+ * @return None
+ * @details This function is used to enable interrupt flag accumulator of selected channel.
+ */
+void EPWM_EnableAcc(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc)
+{
+    (epwm)->IFA[u32ChannelNum] = (((epwm)->IFA[u32ChannelNum] & ~((EPWM_IFA0_IFACNT_Msk | EPWM_IFA0_IFASEL_Msk))) | \
+                                  (EPWM_IFA0_IFAEN_Msk | (u32IntAccSrc << EPWM_IFA0_IFASEL_Pos) | u32IntFlagCnt));
+}
+
+/**
+ * @brief Disable interrupt flag accumulator of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to Disable interrupt flag accumulator of selected channel.
+ */
+void EPWM_DisableAcc(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->IFA[u32ChannelNum] = ((epwm)->IFA[u32ChannelNum] & ~(EPWM_IFA0_IFAEN_Msk));
+}
+
+/**
+ * @brief Enable interrupt flag accumulator interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to enable interrupt flag accumulator interrupt of selected channel.
+ */
+void EPWM_EnableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->AINTEN |= (1UL << (u32ChannelNum));
+}
+
+/**
+ * @brief Disable interrupt flag accumulator interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable interrupt flag accumulator interrupt of selected channel.
+ */
+void EPWM_DisableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->AINTEN &= ~(1UL << (u32ChannelNum));
+}
+
+/**
+ * @brief Clear interrupt flag accumulator interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear interrupt flag accumulator interrupt of selected channel.
+ */
+void EPWM_ClearAccInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->AINTSTS = (1UL << (u32ChannelNum));
+}
+
+/**
+ * @brief Get interrupt flag accumulator interrupt of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @retval 0 Accumulator interrupt did not occur
+ * @retval 1 Accumulator interrupt occurred
+ * @details This function is used to Get interrupt flag accumulator interrupt of selected channel.
+ */
+uint32_t EPWM_GetAccInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    return (((epwm)->AINTSTS & (1UL << (u32ChannelNum))) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable accumulator PDMA of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to enable accumulator interrupt trigger PDMA of selected channel.
+ */
+void EPWM_EnableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->APDMACTL |= (1UL << (u32ChannelNum));
+}
+
+/**
+ * @brief Disable accumulator PDMA of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable accumulator interrupt trigger PDMA of selected channel.
+ */
+void EPWM_DisableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->APDMACTL &= ~(1UL << (u32ChannelNum));
+}
+
+/**
+ * @brief Enable interrupt flag accumulator stop mode of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to enable interrupt flag accumulator stop mode of selected channel.
+ */
+void EPWM_EnableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->IFA[u32ChannelNum] |= EPWM_IFA0_STPMOD_Msk;
+}
+
+/**
+ * @brief Disable interrupt flag accumulator stop mode of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to disable interrupt flag accumulator stop mode of selected channel.
+ */
+void EPWM_DisableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->IFA[u32ChannelNum] &= ~EPWM_IFA0_STPMOD_Msk;
+}
+
+/**
+ * @brief Clear free trigger duty interrupt flag of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear free trigger duty interrupt flag of selected channel.
+ */
+void EPWM_ClearFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->FTCI = ((EPWM_FTCI_FTCMU0_Msk | EPWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1));
+}
+
+/**
+ * @brief Get free trigger duty interrupt flag of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Duty interrupt flag of specified channel
+ * @retval 0 Free trigger duty interrupt did not occur
+ * @retval 1 Free trigger duty interrupt occurred
+ * @details This function is used to get free trigger duty interrupt flag of selected channel.
+ */
+uint32_t EPWM_GetFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    return (((epwm)->FTCI & ((EPWM_FTCI_FTCMU0_Msk | EPWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1))) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Enable load mode of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32LoadMode EPWM counter loading mode.
+ *              - \ref EPWM_LOAD_MODE_IMMEDIATE
+ *              - \ref EPWM_LOAD_MODE_WINDOW
+ *              - \ref EPWM_LOAD_MODE_CENTER
+ * @return None
+ * @details This function is used to enable load mode of selected channel.
+ */
+void EPWM_EnableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
+{
+    (epwm)->CTL0 |= (u32LoadMode << u32ChannelNum);
+}
+
+/**
+ * @brief Disable load mode of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32LoadMode EPWM counter loading mode.
+ *              - \ref EPWM_LOAD_MODE_IMMEDIATE
+ *              - \ref EPWM_LOAD_MODE_WINDOW
+ *              - \ref EPWM_LOAD_MODE_CENTER
+ * @return None
+ * @details This function is used to disable load mode of selected channel.
+ */
+void EPWM_DisableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
+{
+    (epwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum);
+}
+
+/**
+ * @brief Configure synchronization phase of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32SyncSrc EPWM synchronize source selection.
+ *              - \ref EPWM_SYNC_OUT_FROM_SYNCIN_SWSYNC
+ *              - \ref EPWM_SYNC_OUT_FROM_COUNT_TO_ZERO
+ *              - \ref EPWM_SYNC_OUT_FROM_COUNT_TO_COMPARATOR
+ *              - \ref EPWM_SYNC_OUT_DISABLE
+ * @param[in] u32Direction Phase direction. Control EPWM counter count decrement or increment  after synchronizing.
+ *              - \ref EPWM_PHS_DIR_DECREMENT
+ *              - \ref EPWM_PHS_DIR_INCREMENT
+ * @param[in] u32StartPhase Synchronous start phase value. Valid values are between 0~65535.
+ * @return None
+ * @details This function is used to configure synchronization phase of selected channel.
+ * @note Every two channels share the same setting.
+ */
+void EPWM_ConfigSyncPhase(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase)
+{
+    /* every two channels shares the same setting */
+    u32ChannelNum >>= 1;
+    (epwm)->SYNC = (((epwm)->SYNC & ~((EPWM_SYNC_SINSRC0_Msk << (u32ChannelNum << 1)) | (EPWM_SYNC_PHSDIR0_Msk << u32ChannelNum))) | \
+                    (u32Direction << EPWM_SYNC_PHSDIR0_Pos << u32ChannelNum) | (u32SyncSrc << EPWM_SYNC_SINSRC0_Pos) << (u32ChannelNum << 1));
+    (epwm)->PHS[(u32ChannelNum)] = u32StartPhase;
+}
+
+
+/**
+ * @brief Enable SYNC phase of selected channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ *                           Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to enable SYNC phase of selected channel(s).
+ * @note Every two channels share the same setting.
+ */
+void EPWM_EnableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+    uint32_t i;
+    for(i = 0UL; i < EPWM_CHANNEL_NUM; i ++)
+    {
+        if(u32ChannelMask & (1UL << i))
+        {
+            (epwm)->SYNC |= (EPWM_SYNC_PHSEN0_Msk << (i >> 1));
+        }
+    }
+}
+
+/**
+ * @brief Disable SYNC phase of selected channel(s)
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
+ *                           Bit 0 is channel 0, bit 1 is channel 1...
+ * @return None
+ * @details This function is used to disable SYNC phase of selected channel(s).
+ * @note Every two channels share the same setting.
+ */
+void EPWM_DisableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask)
+{
+    uint32_t i;
+    for(i = 0UL; i < EPWM_CHANNEL_NUM; i ++)
+    {
+        if(u32ChannelMask & (1UL << i))
+        {
+            (epwm)->SYNC &= ~(EPWM_SYNC_PHSEN0_Msk << (i >> 1));
+        }
+    }
+}
+
+/**
+ * @brief Enable EPWM SYNC_IN noise filter function
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ClkCnt SYNC Edge Detector Filter Count. This controls the counter number of edge detector.
+ *            The valid value is 0~7.
+ * @param[in] u32ClkDivSel SYNC Edge Detector Filter Clock Selection.
+ *              - \ref EPWM_NF_CLK_DIV_1
+ *              - \ref EPWM_NF_CLK_DIV_2
+ *              - \ref EPWM_NF_CLK_DIV_4
+ *              - \ref EPWM_NF_CLK_DIV_8
+ *              - \ref EPWM_NF_CLK_DIV_16
+ *              - \ref EPWM_NF_CLK_DIV_32
+ *              - \ref EPWM_NF_CLK_DIV_64
+ *              - \ref EPWM_NF_CLK_DIV_128
+ * @return None
+ * @details This function is used to enable EPWM SYNC_IN noise filter function.
+ */
+void EPWM_EnableSyncNoiseFilter(EPWM_T *epwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel)
+{
+    (epwm)->SYNC = ((epwm)->SYNC & ~(EPWM_SYNC_SFLTCNT_Msk | EPWM_SYNC_SFLTCSEL_Msk)) | \
+                   ((u32ClkCnt << EPWM_SYNC_SFLTCNT_Pos) | (u32ClkDivSel << EPWM_SYNC_SFLTCSEL_Pos) | EPWM_SYNC_SNFLTEN_Msk);
+}
+
+/**
+ * @brief Disable EPWM SYNC_IN noise filter function
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @return None
+ * @details This function is used to Disable EPWM SYNC_IN noise filter function.
+ */
+void EPWM_DisableSyncNoiseFilter(EPWM_T *epwm)
+{
+    (epwm)->SYNC &= ~EPWM_SYNC_SNFLTEN_Msk;
+}
+
+/**
+ * @brief Enable EPWM SYNC input pin inverse function
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @return None
+ * @details This function is used to enable EPWM SYNC input pin inverse function.
+ */
+void EPWM_EnableSyncPinInverse(EPWM_T *epwm)
+{
+    (epwm)->SYNC |= EPWM_SYNC_SINPINV_Msk;
+}
+
+/**
+ * @brief Disable EPWM SYNC input pin inverse function
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @return None
+ * @details This function is used to Disable EPWM SYNC input pin inverse function.
+ */
+void EPWM_DisableSyncPinInverse(EPWM_T *epwm)
+{
+    (epwm)->SYNC &= (~EPWM_SYNC_SINPINV_Msk);
+}
+
+/**
+ * @brief Set EPWM clock source
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @param[in] u32ClkSrcSel EPWM external clock source.
+ *              - \ref EPWM_CLKSRC_EPWM_CLK
+ *              - \ref EPWM_CLKSRC_TIMER0
+ *              - \ref EPWM_CLKSRC_TIMER1
+ *              - \ref EPWM_CLKSRC_TIMER2
+ *              - \ref EPWM_CLKSRC_TIMER3
+ * @return None
+ * @details This function is used to set EPWM clock source.
+ * @note Every two channels share the same setting.
+ * @note If the clock source of EPWM counter is selected from TIMERn interrupt events, the TRGEPWM(TIMERn_TRGCTL[1], n=0,1..3) bit must be set as 1.
+ */
+void EPWM_SetClockSource(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel)
+{
+    (epwm)->CLKSRC = ((epwm)->CLKSRC & ~(EPWM_CLKSRC_ECLKSRC0_Msk << ((u32ChannelNum >> 1) << 3))) | \
+                     (u32ClkSrcSel << ((u32ChannelNum >> 1) << 3));
+}
+
+/**
+ * @brief Enable EPWM brake noise filter function
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
+ * @param[in] u32ClkCnt SYNC Edge Detector Filter Count. This controls the counter number of edge detector
+ * @param[in] u32ClkDivSel SYNC Edge Detector Filter Clock Selection.
+ *              - \ref EPWM_NF_CLK_DIV_1
+ *              - \ref EPWM_NF_CLK_DIV_2
+ *              - \ref EPWM_NF_CLK_DIV_4
+ *              - \ref EPWM_NF_CLK_DIV_8
+ *              - \ref EPWM_NF_CLK_DIV_16
+ *              - \ref EPWM_NF_CLK_DIV_32
+ *              - \ref EPWM_NF_CLK_DIV_64
+ *              - \ref EPWM_NF_CLK_DIV_128
+ * @return None
+ * @details This function is used to enable EPWM brake noise filter function.
+ */
+void EPWM_EnableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel)
+{
+    (epwm)->BNF = ((epwm)->BNF & ~((EPWM_BNF_BRK0FCNT_Msk | EPWM_BNF_BRK0NFSEL_Msk) << (u32BrakePinNum << 3))) | \
+                  (((u32ClkCnt << EPWM_BNF_BRK0FCNT_Pos) | (u32ClkDivSel << EPWM_BNF_BRK0NFSEL_Pos) | EPWM_BNF_BRK0NFEN_Msk) << (u32BrakePinNum << 3));
+}
+
+/**
+ * @brief Disable EPWM brake noise filter function
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
+ * @return None
+ * @details This function is used to disable EPWM brake noise filter function.
+ */
+void EPWM_DisableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum)
+{
+    (epwm)->BNF &= ~(EPWM_BNF_BRK0NFEN_Msk << (u32BrakePinNum << 3));
+}
+
+/**
+ * @brief Enable EPWM brake pin inverse function
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
+ * @return None
+ * @details This function is used to enable EPWM brake pin inverse function.
+ */
+void EPWM_EnableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum)
+{
+    (epwm)->BNF |= (EPWM_BNF_BRK0PINV_Msk << (u32BrakePinNum << 3));
+}
+
+/**
+ * @brief Disable EPWM brake pin inverse function
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
+ * @return None
+ * @details This function is used to disable EPWM brake pin inverse function.
+ */
+void EPWM_DisableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum)
+{
+    (epwm)->BNF &= ~(EPWM_BNF_BRK0PINV_Msk << (u32BrakePinNum * (uint32_t)EPWM_BNF_BRK1NFEN_Pos));
+}
+
+/**
+ * @brief Set EPWM brake pin source
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1.
+ * @param[in] u32SelAnotherModule Select to another module. Valid values are TRUE or FALSE.
+ * @return None
+ * @details This function is used to set EPWM brake pin source.
+ */
+void EPWM_SetBrakePinSource(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule)
+{
+    (epwm)->BNF = ((epwm)->BNF & ~(EPWM_BNF_BK0SRC_Msk << (u32BrakePinNum << 3))) | (u32SelAnotherModule << ((uint32_t)EPWM_BNF_BK0SRC_Pos + (u32BrakePinNum << 3)));
+}
+
+/**
+ * @brief Set EPWM leading edge blanking function
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32TrigSrcSel Leading edge blanking source selection.
+ *              - \ref EPWM_LEBCTL_SRCEN0
+ *              - \ref EPWM_LEBCTL_SRCEN2
+ *              - \ref EPWM_LEBCTL_SRCEN4
+ *              - \ref EPWM_LEBCTL_SRCEN0_2
+ *              - \ref EPWM_LEBCTL_SRCEN0_4
+ *              - \ref EPWM_LEBCTL_SRCEN2_4
+ *              - \ref EPWM_LEBCTL_SRCEN0_2_4
+ * @param[in] u32TrigType  Leading edge blanking trigger type.
+ *              - \ref EPWM_LEBCTL_TRGTYPE_RISING
+ *              - \ref EPWM_LEBCTL_TRGTYPE_FALLING
+ *              - \ref EPWM_LEBCTL_TRGTYPE_RISING_OR_FALLING
+ * @param[in] u32BlankingCnt  Leading Edge Blanking Counter. Valid values are between 1~512.
+                              This counter value decides leading edge blanking window size, and this counter clock base is ECLK.
+ * @param[in] u32BlankingEnable Enable EPWM leading edge blanking function. Valid values are TRUE (ENABLE) or FALSE (DISABLE).
+ *              - \ref FALSE
+ *              - \ref TRUE
+ * @return None
+ * @details This function is used to configure EPWM leading edge blanking function that blank the false trigger from ACMP brake source which may cause by EPWM output transition.
+ * @note EPWM leading edge blanking function is only used for brake source from ACMP.
+ */
+void EPWM_SetLeadingEdgeBlanking(EPWM_T *epwm, uint32_t u32TrigSrcSel, uint32_t u32TrigType, uint32_t u32BlankingCnt, uint32_t u32BlankingEnable)
+{
+    (epwm)->LEBCTL = (u32TrigType) | (u32TrigSrcSel) | (u32BlankingEnable);
+    /* Blanking window size = LEBCNT + 1, so LEBCNT = u32BlankingCnt - 1 */
+    (epwm)->LEBCNT = (u32BlankingCnt) - 1UL;
+}
+
+/**
+ * @brief Get the time-base counter reached its maximum value flag of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return Count to max interrupt flag of specified channel
+ * @retval 0 Count to max interrupt did not occur
+ * @retval 1 Count to max interrupt occurred
+ * @details This function is used to get the time-base counter reached its maximum value flag of selected channel.
+ */
+uint32_t EPWM_GetWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    return (((epwm)->STATUS & (EPWM_STATUS_CNTMAXF0_Msk << u32ChannelNum)) ? 1UL : 0UL);
+}
+
+/**
+ * @brief Clear the time-base counter reached its maximum value flag of selected channel
+ * @param[in] epwm The pointer of the specified EPWM module
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
+ * @return None
+ * @details This function is used to clear the time-base counter reached its maximum value flag of selected channel.
+ */
+void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->STATUS = (EPWM_STATUS_CNTMAXF0_Msk << u32ChannelNum);
+}
+
+/**
+ * @brief Enable fault detect of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module.
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5.
+ * @param[in] u32AfterPrescaler Fault Detect Clock Source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler).
+ * @param[in] u32ClkSel Fault Detect Clock Select.
+ *              - \ref EPWM_FDCTL_FDCKSEL_CLK_DIV_1
+ *              - \ref EPWM_FDCTL_FDCKSEL_CLK_DIV_2
+ *              - \ref EPWM_FDCTL_FDCKSEL_CLK_DIV_4
+ *              - \ref EPWM_FDCTL_FDCKSEL_CLK_DIV_8
+ * @return None
+ * @details This function is used to enable fault detect of selected channel.
+ */
+void EPWM_EnableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32AfterPrescaler, uint32_t u32ClkSel)
+{
+    (epwm)->FDEN = ((epwm)->FDEN & ~(EPWM_FDEN_FDCKS0_Msk << (u32ChannelNum))) | \
+                   ((EPWM_FDEN_FDEN0_Msk | ((u32AfterPrescaler) << EPWM_FDEN_FDCKS0_Pos)) << (u32ChannelNum));
+    (epwm)->FDCTL[(u32ChannelNum)] = ((epwm)->FDCTL[(u32ChannelNum)] & ~EPWM_FDCTL0_FDCKSEL_Msk) | (u32ClkSel);
+}
+
+/**
+ * @brief Disable fault detect of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module.
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5.
+ * @return None
+ * @details This function is used to disable fault detect of selected channel.
+ */
+void EPWM_DisableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->FDEN &= ~(EPWM_FDEN_FDEN0_Msk << (u32ChannelNum));
+}
+
+/**
+ * @brief Enable fault detect output of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module.
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5.
+ * @return None
+ * @details This function is used to enable fault detect output of selected channel.
+ */
+void EPWM_EnableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->FDEN &= ~(EPWM_FDEN_FDODIS0_Msk << (u32ChannelNum));
+}
+
+/**
+ * @brief Disable fault detect output of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module.
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5.
+ * @return None
+ * @details This function is used to disable fault detect output of selected channel.
+ */
+void EPWM_DisableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->FDEN |= (EPWM_FDEN_FDODIS0_Msk << (u32ChannelNum));
+}
+
+/**
+ * @brief Enable fault detect deglitch function of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module.
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5.
+ * @param[in] u32DeglitchSmpCycle Deglitch Sampling Cycle. Valid values are between 0~7.
+ * @return None
+ * @details This function is used to enable fault detect deglitch function of selected channel.
+ */
+void EPWM_EnableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32DeglitchSmpCycle)
+{
+    (epwm)->FDCTL[(u32ChannelNum)] = ((epwm)->FDCTL[(u32ChannelNum)] & (~EPWM_FDCTL0_DGSMPCYC_Msk)) | \
+                                     (EPWM_FDCTL0_FDDGEN_Msk | ((u32DeglitchSmpCycle) << EPWM_FDCTL0_DGSMPCYC_Pos));
+}
+
+/**
+ * @brief Disable fault detect deglitch function of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module.
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5.
+ * @return None
+ * @details This function is used to disable fault detect deglitch function of selected channel.
+ */
+void EPWM_DisableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->FDCTL[(u32ChannelNum)] &= ~EPWM_FDCTL0_FDDGEN_Msk;
+}
+
+/**
+ * @brief Enable fault detect mask function of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module.
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5.
+ * @param[in] u32MaskCnt Transition mask counter. Valid values are between 0~0x7F.
+ * @return None
+ * @details This function is used to enable fault detect mask function of selected channel.
+ */
+void EPWM_EnableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32MaskCnt)
+{
+    (epwm)->FDCTL[(u32ChannelNum)] = ((epwm)->FDCTL[(u32ChannelNum)] & (~EPWM_FDCTL0_TRMSKCNT_Msk)) | (EPWM_FDCTL0_FDMSKEN_Msk | (u32MaskCnt));
+}
+
+/**
+ * @brief Disable fault detect mask function of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module.
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5.
+ * @return None
+ * @details This function is used to disable fault detect mask function of selected channel.
+ */
+void EPWM_DisableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->FDCTL[(u32ChannelNum)] &= ~EPWM_FDCTL0_FDMSKEN_Msk;
+}
+
+/**
+ * @brief Enable fault detect interrupt of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module.
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5.
+ * @return None
+ * @details This function is used to enable fault detect interrupt of selected channel.
+ */
+void EPWM_EnableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->FDIEN |= (EPWM_FDIEN_FDIEN0_Msk << (u32ChannelNum));
+}
+
+/**
+ * @brief Disable fault detect interrupt of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module.
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5.
+ * @return None
+ * @details This function is used to disable fault detect interrupt of selected channel.
+ */
+void EPWM_DisableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->FDIEN &= ~(EPWM_FDIEN_FDIEN0_Msk << (u32ChannelNum));
+}
+
+/**
+ * @brief Clear fault detect interrupt of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module.
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5.
+ * @return None
+ * @details This function is used to clear fault detect interrupt of selected channel.
+ */
+void EPWM_ClearFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    (epwm)->FDSTS = (EPWM_FDSTS_FDIF0_Msk << (u32ChannelNum));
+}
+
+/**
+ * @brief Get fault detect interrupt of selected channel.
+ * @param[in] epwm The pointer of the specified EPWM module.
+ *                - EPWM0 : EPWM Group 0
+ *                - EPWM1 : EPWM Group 1
+ * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5.
+ * @retval 0 Fault detect interrupt did not occur.
+ * @retval 1 Fault detect interrupt occurred.
+ * @details This function is used to Get fault detect interrupt of selected channel.
+ */
+uint32_t EPWM_GetFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum)
+{
+    return (((epwm)->FDSTS & (EPWM_FDSTS_FDIF0_Msk << (u32ChannelNum))) ? 1UL : 0UL);
+}
+
+/**@}*/ /* end of group EPWM_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group EPWM_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_ewdt.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_ewdt.c
new file mode 100644
index 0000000000..7b97e96525
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_ewdt.c
@@ -0,0 +1,69 @@
+/**************************************************************************//**
+ * @file     ewdt.c
+ * @version  V3.00
+ * @brief    Extra Watchdog Timer(EWDT) driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup EWDT_Driver EWDT Driver
+  @{
+*/
+
+/** @addtogroup EWDT_EXPORTED_FUNCTIONS EWDT Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Initialize EWDT and start counting
+  *
+  * @param[in]  u32TimeoutInterval  Time-out interval period of EWDT module. Valid values are:
+  *                                 - \ref EWDT_TIMEOUT_2POW4
+  *                                 - \ref EWDT_TIMEOUT_2POW6
+  *                                 - \ref EWDT_TIMEOUT_2POW8
+  *                                 - \ref EWDT_TIMEOUT_2POW10
+  *                                 - \ref EWDT_TIMEOUT_2POW12
+  *                                 - \ref EWDT_TIMEOUT_2POW14
+  *                                 - \ref EWDT_TIMEOUT_2POW16
+  *                                 - \ref EWDT_TIMEOUT_2POW18
+  *                                 - \ref EWDT_TIMEOUT_2POW20
+  * @param[in]  u32ResetDelay       Configure EWDT time-out reset delay period. Valid values are:
+  *                                 - \ref EWDT_RESET_DELAY_1026CLK
+  *                                 - \ref EWDT_RESET_DELAY_130CLK
+  *                                 - \ref EWDT_RESET_DELAY_18CLK
+  *                                 - \ref EWDT_RESET_DELAY_3CLK
+  * @param[in]  u32EnableReset      Enable EWDT time-out reset system function. Valid values are TRUE and FALSE.
+  * @param[in]  u32EnableWakeup     Enable EWDT time-out wake-up system function. Valid values are TRUE and FALSE.
+  *
+  * @return     None
+  *
+  * @details    This function makes EWDT module start counting with different time-out interval, reset delay period and choose to \n
+  *             enable or disable EWDT time-out reset system or wake-up system.
+  * @note       Please make sure that Register Write-Protection Function has been disabled before using this function.
+  */
+void EWDT_Open(uint32_t u32TimeoutInterval,
+               uint32_t u32ResetDelay,
+               uint32_t u32EnableReset,
+               uint32_t u32EnableWakeup)
+{
+    EWDT->ALTCTL = u32ResetDelay;
+
+    EWDT->CTL = u32TimeoutInterval | EWDT_CTL_WDTEN_Msk |
+                (u32EnableReset << EWDT_CTL_RSTEN_Pos) |
+                (u32EnableWakeup << EWDT_CTL_WKEN_Pos);
+
+    while((EWDT->CTL & EWDT_CTL_SYNC_Msk) == EWDT_CTL_SYNC_Msk) {} /* Wait enable WDTEN bit completed, it needs 2 * EWDT_CLK. */
+}
+
+/**@}*/ /* end of group EWDT_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group EWDT_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_ewwdt.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_ewwdt.c
new file mode 100644
index 0000000000..2589628010
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_ewwdt.c
@@ -0,0 +1,67 @@
+/**************************************************************************//**
+ * @file     ewwdt.c
+ * @version  V3.00
+ * @brief    Extra Window Watchdog Timer(EWWDT) driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup EWWDT_Driver EWWDT Driver
+  @{
+*/
+
+/** @addtogroup EWWDT_EXPORTED_FUNCTIONS EWWDT Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Open EWWDT and start counting
+  *
+  * @param[in]  u32PreScale     Pre-scale setting of EWWDT counter. Valid values are:
+  *                             - \ref EWWDT_PRESCALER_1
+  *                             - \ref EWWDT_PRESCALER_2
+  *                             - \ref EWWDT_PRESCALER_4
+  *                             - \ref EWWDT_PRESCALER_8
+  *                             - \ref EWWDT_PRESCALER_16
+  *                             - \ref EWWDT_PRESCALER_32
+  *                             - \ref EWWDT_PRESCALER_64
+  *                             - \ref EWWDT_PRESCALER_128
+  *                             - \ref EWWDT_PRESCALER_192
+  *                             - \ref EWWDT_PRESCALER_256
+  *                             - \ref EWWDT_PRESCALER_384
+  *                             - \ref EWWDT_PRESCALER_512
+  *                             - \ref EWWDT_PRESCALER_768
+  *                             - \ref EWWDT_PRESCALER_1024
+  *                             - \ref EWWDT_PRESCALER_1536
+  *                             - \ref EWWDT_PRESCALER_2048
+  * @param[in]  u32CmpValue     Setting the window compared value. Valid values are between 0x0 to 0x3F.
+  * @param[in]  u32EnableInt    Enable WWDT time-out interrupt function. Valid values are TRUE and FALSE.
+  *
+  * @return     None
+  *
+  * @details    This function makes EWWDT module start counting with different counter period by pre-scale setting and compared window value.
+  * @note       Application can call this function only once after boot up.
+  */
+void EWWDT_Open(uint32_t u32PreScale,
+                uint32_t u32CmpValue,
+                uint32_t u32EnableInt)
+{
+    EWWDT->CTL = u32PreScale |
+                 (u32CmpValue << EWWDT_CTL_CMPDAT_Pos) |
+                 ((u32EnableInt == (uint32_t)TRUE) ? EWWDT_CTL_INTEN_Msk : 0UL) |
+                 EWWDT_CTL_WWDTEN_Msk;
+}
+
+/**@}*/ /* end of group EWWDT_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group EWWDT_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_fmc.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_fmc.c
new file mode 100644
index 0000000000..e5cd41614d
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_fmc.c
@@ -0,0 +1,861 @@
+/**************************************************************************//**
+ * @file     fmc.c
+ * @version  V3.00
+ * $Revision: 1 $
+ * $Date: 19/11/27 7:50p $
+ * @brief    M2355 Series Flash Memory Controller(FMC) driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include 
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup FMC_Driver FMC Driver
+  @{
+*/
+
+/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions
+  @{
+*/
+
+/**
+  * @brief Run flash all one verification and get result.
+  *
+  * @param[in] u32addr   Starting flash address. It must be a page aligned address.
+  * @param[in] u32count  Byte count of flash to be calculated. It must be multiple of 512 bytes.
+  *
+  * @retval   READ_ALLONE_YES       The contents of verified flash area are 0xA11FFFFF.
+  * @retval   READ_ALLONE_NOT       Some contents of verified flash area are not 0xA1100000.
+  * @retval   READ_ALLONE_CMD_FAIL  Unexpected error occurred.
+  *
+  * @details  Run ISP check all one command to check specify area is all one or not.
+  */
+uint32_t  FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count)
+{
+    uint32_t  ret = READ_ALLONE_CMD_FAIL;
+
+    FMC_ISP->ISPSTS = 0x80UL;   /* clear check all one bit */
+
+    FMC_ISP->ISPCMD   = FMC_ISPCMD_RUN_ALL1;
+    FMC_ISP->ISPADDR  = u32addr;
+    FMC_ISP->ISPDAT   = u32count;
+    FMC_ISP->ISPTRG   = FMC_ISPTRG_ISPGO_Msk;
+
+    while(FMC_ISP->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
+
+    do
+    {
+        FMC_ISP->ISPCMD = FMC_ISPCMD_READ_ALL1;
+        FMC_ISP->ISPADDR    = u32addr;
+        FMC_ISP->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+        while(FMC_ISP->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
+    }
+    while(FMC_ISP->ISPDAT == 0UL);
+
+    if(FMC_ISP->ISPDAT == READ_ALLONE_YES)
+    {
+        ret = FMC_ISP->ISPDAT;
+    }
+
+    if(FMC_ISP->ISPDAT == READ_ALLONE_NOT)
+    {
+        ret = FMC_ISP->ISPDAT;
+    }
+
+    return ret;
+}
+
+
+/**
+  * @brief    Disable ISP Functions
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  This function will clear ISPEN bit of ISPCON to disable ISP function
+  *
+  */
+void FMC_Close(void)
+{
+    FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk;
+}
+
+/**
+  * @brief     Config XOM Region
+  * @param[in] u32XomNum    The XOM number(0~3)
+  * @param[in] u32XomBase   The XOM region base address.
+  * @param[in] u8XomPage   The XOM page number of region size.
+  *
+  * @retval   0   Success
+  * @retval   1   XOM is has already actived.
+  * @retval   -1  Program failed.
+  * @retval   -2  Invalid XOM number.
+  *
+  * @details  Program XOM base address and XOM size(page)
+  */
+int32_t FMC_ConfigXOM(uint32_t u32XomNum, uint32_t u32XomBase, uint8_t u8XomPage)
+{
+    int32_t  ret = 0;
+
+    if(u32XomNum >= 4UL)
+    {
+        ret = -2;
+    }
+
+    if(ret == 0)
+    {
+        ret = FMC_GetXOMState(u32XomNum);
+    }
+
+    if(ret == 0)
+    {
+        FMC_ISP->ISPCMD = FMC_ISPCMD_PROGRAM;
+        FMC_ISP->ISPADDR = FMC_XOM_BASE + (u32XomNum * 0x10u);
+        FMC_ISP->ISPDAT = u32XomBase;
+        FMC_ISP->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+        while(FMC_ISP->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {}
+
+        if(FMC_ISP->ISPSTS & FMC_ISPSTS_ISPFF_Msk)
+        {
+            FMC_ISP->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+            ret = -1;
+        }
+    }
+
+    if(ret == 0)
+    {
+        FMC_ISP->ISPCMD = FMC_ISPCMD_PROGRAM;
+        FMC_ISP->ISPADDR = FMC_XOM_BASE + (u32XomNum * 0x10u + 0x04u);
+        FMC_ISP->ISPDAT = u8XomPage;
+        FMC_ISP->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+        while(FMC_ISP->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {}
+
+        if(FMC_ISP->ISPSTS & FMC_ISPSTS_ISPFF_Msk)
+        {
+            FMC_ISP->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+            ret = -1;
+        }
+    }
+
+    if(ret == 0)
+    {
+        FMC_ISP->ISPCMD = FMC_ISPCMD_PROGRAM;
+        FMC_ISP->ISPADDR = FMC_XOM_BASE + (u32XomNum * 0x10u + 0x08u);
+        FMC_ISP->ISPDAT = 0u;
+        FMC_ISP->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+        while(FMC_ISP->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {}
+
+        if(FMC_ISP->ISPSTS & FMC_ISPSTS_ISPFF_Msk)
+        {
+            FMC_ISP->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+            ret = -1;
+        }
+    }
+
+    return ret;
+}
+
+/**
+  * @brief      Execute Flash Page erase
+  *
+  * @param[in]  u32PageAddr Address of the flash page to be erased.
+  *             It must be a 2048 bytes aligned address.
+  *
+  * @return     ISP page erase success or not.
+  * @retval     0  Success
+  * @retval     -1  Erase failed
+  *
+  * @details    Execute FMC_ISPCMD_PAGE_ERASE command to erase a flash page. The page size is 2048 bytes.
+  */
+int32_t FMC_Erase(uint32_t u32PageAddr)
+{
+    int32_t  ret = 0;
+
+    if(ret == 0)
+    {
+        FMC_ISP->ISPCMD = FMC_ISPCMD_PAGE_ERASE;
+        FMC_ISP->ISPADDR = u32PageAddr;
+        FMC_ISP->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+        while(FMC_ISP->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+        if(FMC_ISP->ISPCTL & FMC_ISPCTL_ISPFF_Msk)
+        {
+            FMC_ISP->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
+            ret = -1;
+        }
+    }
+    return ret;
+}
+
+/**
+  * @brief      Execute Flash Bank erase
+  *
+  * @param[in]  u32BankAddr Base address of the flash bank to be erased.
+  *
+  * @return     ISP bank erase success or not.
+  * @retval     0  Success
+  * @retval     -1  Erase failed
+  *
+  * @details  Execute FMC_ISPCMD_BANK_ERASE command to erase a flash block.
+  */
+int32_t FMC_EraseBank(uint32_t u32BankAddr)
+{
+    int32_t  ret = 0;
+
+    FMC->ISPCMD = FMC_ISPCMD_BANK_ERASE;
+    FMC->ISPADDR = u32BankAddr;
+    FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+    while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {}
+
+    if(FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk)
+    {
+        FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
+        ret = -1;
+    }
+    return ret;
+}
+
+
+/**
+  * @brief  Execute Erase XOM Region
+  *
+  * @param[in]  u32XomNum  The XOMRn(n=0~3)
+  *
+  * @return   XOM erase success or not.
+  * @retval    0  Success
+  * @retval   -1  Erase failed
+  * @retval   -2  Invalid XOM number.
+  *
+  * @details Execute FMC_ISPCMD_PAGE_ERASE command to erase XOM.
+  */
+int32_t FMC_EraseXOM(uint32_t u32XomNum)
+{
+    uint32_t u32Addr;
+    int32_t i32Active, err = 0;
+
+    if(u32XomNum >= 4UL)
+    {
+        err = -2;
+    }
+
+    if(err == 0)
+    {
+        i32Active = FMC_GetXOMState(u32XomNum);
+
+        if(i32Active)
+        {
+            u32Addr = (((uint32_t)(&FMC->XOMR0STS)[u32XomNum]) & 0xFFFFFF00u) >> 8u;
+
+            FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE;
+            FMC->ISPADDR = u32Addr;
+            FMC->ISPDAT = 0x55aa03u;
+            FMC->ISPTRG = 0x1u;
+#if ISBEN
+            __ISB();
+#endif
+            while(FMC->ISPTRG) {}
+
+            /* Check ISPFF flag to know whether erase OK or fail. */
+            if(FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk)
+            {
+                FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
+                err = -1;
+            }
+        }
+        else
+        {
+            err = -1;
+        }
+    }
+    return err;
+}
+
+/**
+  * @brief     Run CRC32 checksum calculation and get result.
+  *
+  * @param[in] u32addr   Starting flash address. It must be a page aligned address.
+  * @param[in] u32count  Byte count of flash to be calculated. It must be multiple of 2048bytes.
+  *
+  * @return    Success or not.
+  * @retval    0           Success.
+  * @retval    0xFFFFFFFF  Invalid parameter.
+  *
+  * @details  Run ISP CRC32 checksum command to calculate checksum then get and return checksum data.
+  */
+uint32_t  FMC_GetChkSum(uint32_t u32addr, uint32_t u32count)
+{
+    uint32_t   ret;
+
+    if((u32addr % 2048UL) || (u32count % 2048UL))
+    {
+        ret = 0xFFFFFFFF;
+    }
+    else
+    {
+        FMC_ISP->ISPCMD  = FMC_ISPCMD_RUN_CKS;
+        FMC_ISP->ISPADDR = u32addr;
+        FMC_ISP->ISPDAT  = u32count;
+        FMC_ISP->ISPTRG  = FMC_ISPTRG_ISPGO_Msk;
+
+        while(FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
+
+        FMC_ISP->ISPCMD = FMC_ISPCMD_READ_CKS;
+        FMC_ISP->ISPADDR    = u32addr;
+        FMC_ISP->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+        while(FMC_ISP->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
+
+        ret = FMC_ISP->ISPDAT;
+    }
+
+    return ret;
+}
+
+/**
+  * @brief  Check the OTP is locked or not.
+  *
+  * @param[in] u32OtpNum    The OTP number.
+  *
+  * @retval   1   OTP is locked.
+  * @retval   0   OTP is not locked.
+  * @retval   -1  Failed to read OTP lock bits.
+  * @retval   -2  Invalid OTP number.
+  *
+  * @details To get specify OTP lock status
+  */
+int32_t FMC_IsOTPLocked(uint32_t u32OtpNum)
+{
+    int32_t  ret = 0;
+
+    if(u32OtpNum > 255UL)
+    {
+        ret = -2;
+    }
+
+    if(ret == 0)
+    {
+        FMC->ISPCMD = FMC_ISPCMD_READ;
+        FMC->ISPADDR = FMC_OTP_BASE + 0x800UL + u32OtpNum * 4UL;
+        FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+        while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+        if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)
+        {
+            FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+            ret = -1;
+        }
+        else
+        {
+            if(FMC->ISPDAT != 0xFFFFFFFFUL)
+            {
+                ret = 1;   /* Lock work was progrmmed. OTP was locked. */
+            }
+        }
+    }
+    return ret;
+}
+
+/**
+  * @brief  Check the XOM is actived or not.
+  *
+  * @param[in] u32XomNum    The xom number(0~3).
+  *
+  * @retval   1   XOM is actived.
+  * @retval   0   XOM is not actived.
+  * @retval   -2  Invalid XOM number.
+  *
+  * @details To get specify XOMRn(n=0~3) active status
+  */
+int32_t FMC_GetXOMState(uint32_t u32XomNum)
+{
+    uint32_t u32act;
+    int32_t  ret = 0;
+
+    if(u32XomNum >= 4UL)
+    {
+        ret = -2;
+    }
+
+    if(ret >= 0)
+    {
+        u32act = (((FMC_ISP->XOMSTS) & 0xful) & (1ul << u32XomNum)) >> u32XomNum;
+        ret = (int32_t)u32act;
+    }
+    return ret;
+}
+
+/**
+  * @brief  Lock the specified OTP.
+  *
+  * @param[in] u32OtpNum    The OTP number.
+  *
+  * @retval    0   Success
+  * @retval   -1  Failed to write OTP lock bits.
+  * @retval   -2  Invalid OTP number.
+  *
+  * @details  To lock specified OTP number
+  */
+int32_t FMC_LockOTP(uint32_t u32OtpNum)
+{
+    int32_t  ret = 0;
+
+    if(u32OtpNum > 255UL)
+    {
+        ret = -2;
+    }
+
+    if(ret == 0)
+    {
+        FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
+        FMC->ISPADDR = FMC_OTP_BASE + 0x800UL + u32OtpNum * 4UL;
+        FMC->ISPDAT = 0UL;
+        FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+        while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+        if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)
+        {
+            FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+            ret = -1;
+        }
+    }
+    return ret;
+}
+
+/**
+  * @brief    Enable FMC ISP function
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  ISPEN bit of ISPCON must be set before we can use ISP commands.
+  *           Therefore, To use all FMC function APIs, user needs to call FMC_Open() first to enable ISP functions.
+  *
+  * @note     ISP functions are write-protected. user also needs to unlock it by calling SYS_UnlockReg() before using all ISP functions.
+  *
+  */
+void FMC_Open(void)
+{
+    FMC_ISP->ISPCTL |=  FMC_ISPCTL_ISPEN_Msk;
+}
+
+
+/**
+  * @brief      Read a word bytes from flash
+  *
+  * @param[in]  u32Addr Address of the flash location to be read.
+  *             It must be a word aligned address.
+  *
+  * @return     The word data read from specified flash address.
+  *
+  * @details    Execute FMC_ISPCMD_READ command to read a word from flash.
+  */
+uint32_t FMC_Read(uint32_t u32Addr)
+{
+    FMC_ISP->ISPCMD = FMC_ISPCMD_READ;
+    FMC_ISP->ISPADDR = u32Addr;
+    FMC_ISP->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+    while(FMC_ISP->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+    return FMC_ISP->ISPDAT;
+}
+
+/**
+  * @brief      Read a double-word bytes from flash
+  *
+  * @param[in]  u32addr   Address of the flash location to be read.
+  *             It must be a double-word aligned address.
+  *
+  * @param[out] u32data0  Place holder of word 0 read from flash address u32addr.
+  * @param[out] u32data1  Place holder of word 0 read from flash address u32addr+4.
+  *
+  * @return     0   Success
+  * @return     -1  Failed
+  *
+  * @details    Execute FMC_ISPCMD_READ_64 command to read a double-word from flash.
+  */
+int32_t FMC_Read64(uint32_t u32addr, uint32_t * u32data0, uint32_t * u32data1)
+{
+    int32_t  ret = 0;
+
+    FMC->ISPCMD = FMC_ISPCMD_READ_64;
+    FMC->ISPADDR    = u32addr;
+    FMC->ISPDAT = 0x0UL;
+    FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+    while(FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
+
+    if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)
+    {
+        FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+        ret = -1;
+    }
+    else
+    {
+        *u32data0 = FMC->MPDAT0;
+        *u32data1 = FMC->MPDAT1;
+    }
+    return ret;
+}
+
+/**
+  * @brief  Read data from OTP
+  *
+  * @param[in] u32OtpNum    The OTP number(0~255).
+  * @param[in] u32LowWord   Low word of the 64-bits data.
+  * @param[in] u32HighWord   High word of the 64-bits data.
+  *
+  * @retval    0   Success
+  * @retval   -1  Read failed.
+  * @retval   -2  Invalid OTP number.
+  *
+  * @details  Read the 64-bits data from the specified OTP.
+  */
+int32_t FMC_ReadOTP(uint32_t u32OtpNum, uint32_t *u32LowWord, uint32_t *u32HighWord)
+{
+    int32_t  ret = 0;
+
+    if(u32OtpNum > 255UL)
+    {
+        ret = -2;
+    }
+
+    if(ret == 0)
+    {
+        FMC->ISPCMD = FMC_ISPCMD_READ_64;
+        FMC->ISPADDR    = FMC_OTP_BASE + u32OtpNum * 8UL ;
+        FMC->ISPDAT = 0x0UL;
+        FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+        while(FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) {}
+
+        if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)
+        {
+            FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+            ret = -1;
+        }
+        else
+        {
+            *u32LowWord = FMC->MPDAT0;
+            *u32HighWord = FMC->MPDAT1;
+        }
+    }
+    return ret;
+}
+
+/**
+  * @brief       Read the User Configuration words.
+  *
+  * @param[out]  u32Config[]  The word buffer to store the User Configuration data.
+  * @param[in]   u32Count   The word count to be read.
+  *
+  * @return      Success or not.
+  * @retval       0 Success
+  * @retval      -1 Failed
+  *
+  * @details     This function is used to read the settings of user configuration.
+  *              if u32Count = 1, Only CONFIG0 will be returned to the buffer specified by u32Config.
+  *              if u32Count = 2, Both CONFIG0 and CONFIG1 will be returned.
+  */
+int32_t FMC_ReadConfig(uint32_t u32Config[], uint32_t u32Count)
+{
+    uint32_t i;
+
+    for(i = 0u; i < u32Count; i++)
+    {
+        u32Config[i] = FMC_Read(FMC_CONFIG_BASE + i * 4u);
+    }
+    return 0;
+}
+
+/**
+  * @brief      Write a word bytes to flash.
+  *
+  * @param[in]  u32Addr Address of the flash location to be programmed.
+  *             It must be a word aligned address.
+  * @param[in]  u32Data The word data to be programmed.
+  *
+  * @return     None
+  *
+  * @ details   Execute ISP FMC_ISPCMD_PROGRAM to program a word to flash.
+  */
+void FMC_Write(uint32_t u32Addr, uint32_t u32Data)
+{
+    FMC_ISP->ISPCMD = FMC_ISPCMD_PROGRAM;
+    FMC_ISP->ISPADDR = u32Addr;
+    FMC_ISP->ISPDAT = u32Data;
+    FMC_ISP->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+    while(FMC_ISP->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+}
+
+/**
+  * @brief      Write a double-word bytes to flash
+  *
+  * @param[in]  u32addr Address of the flash location to be programmed.
+  *             It must be a double-word aligned address.
+  * @param[in]  u32data0   The word data to be programmed to flash address u32addr.
+  * @param[in]  u32data1   The word data to be programmed to flash address u32addr+4.
+  *
+  * @return     0   Success
+  * @return     -1  Failed
+  *
+  * @ details   Execute ISP FMC_ISPCMD_PROGRAM_64 to program a double-word to flash.
+  */
+int32_t FMC_Write8Bytes(uint32_t u32addr, uint32_t u32data0, uint32_t u32data1)
+{
+    int32_t  ret = 0;
+
+    FMC->ISPCMD  = FMC_ISPCMD_PROGRAM_64;
+    FMC->ISPADDR = u32addr;
+    FMC->MPDAT0  = u32data0;
+    FMC->MPDAT1  = u32data1;
+    FMC->ISPTRG  = FMC_ISPTRG_ISPGO_Msk;
+
+    while(FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
+
+    if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)
+    {
+        FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+        ret = -1;
+    }
+    return ret;
+}
+
+/**
+  * @brief    Write User Configuration
+  *
+  * @param[in]  au32Config[] The word buffer to store the User Configuration data.
+  * @param[in]  u32Count The word count to program to User Configuration.
+  *
+  * @retval     0 Success
+  * @retval    -1 Failed
+  *
+  * @details  User must enable User Configuration update before writing it.
+  *           User must erase User Configuration before writing it.
+  *           User Configuration is also be page erase. User needs to backup necessary data
+  *           before erase User Configuration.
+  */
+int32_t FMC_WriteConfig(uint32_t au32Config[], uint32_t u32Count)
+{
+    int32_t  ret = 0;
+    uint32_t i;
+
+    FMC_ENABLE_CFG_UPDATE();
+    for(i = 0u; i < u32Count; i++)
+    {
+        FMC_Write(FMC_CONFIG_BASE + i * 4u, au32Config[i]);
+        if(FMC_Read(FMC_CONFIG_BASE + i * 4u) != au32Config[i])
+        {
+            ret = -1;
+        }
+    }
+    FMC_DISABLE_CFG_UPDATE();
+    return ret;
+}
+
+/**
+  * @brief      Write Multi-Word bytes to flash
+  *
+  * @param[in]  u32Addr    Start flash address in APROM where the data chunk to be programmed into.
+  *                        This address must be 8-bytes aligned to flash address.
+  * @param[in]  pu32Buf    Buffer that carry the data chunk.
+  * @param[in]  u32Len     Length of the data chunk in bytes.
+  *
+  * @retval     >=0  Number of data bytes were programmed.
+  * @return     -1   Invalid address.
+  *
+  * @details     Program Multi-Word data into specified address of flash.
+  */
+
+int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len)
+{
+
+    uint32_t i, idx, u32OnProg;
+    int32_t err,  retval = 0;
+
+    if((u32Addr >= FMC_APROM_END) || ((u32Addr % 8) != 0))
+    {
+        return -1;
+    }
+
+    idx = 0u;
+    FMC->ISPCMD = FMC_ISPCMD_PROGRAM_MUL;
+    FMC->ISPADDR = u32Addr;
+    retval += 16;
+    do
+    {
+        err = 0;
+        u32OnProg = 1u;
+        FMC->MPDAT0 = pu32Buf[idx + 0u];
+        FMC->MPDAT1 = pu32Buf[idx + 1u];
+        FMC->MPDAT2 = pu32Buf[idx + 2u];
+        FMC->MPDAT3 = pu32Buf[idx + 3u];
+        FMC->ISPTRG = 0x1u;
+        idx += 4u;
+
+        for(i = idx; i < (u32Len / 4u); i += 4u) /* Max data length is 256 bytes (512/4 words)*/
+        {
+            __set_PRIMASK(1u); /* Mask interrupt to avoid status check coherence error*/
+            do
+            {
+                if((FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) == 0u)
+                {
+                    __set_PRIMASK(0u);
+
+                    FMC->ISPADDR = FMC->MPADDR & (~0xful);
+                    idx = (FMC->ISPADDR - u32Addr) / 4u;
+                    err = -1;
+                }
+            }
+            while((FMC->MPSTS & (3u << FMC_MPSTS_D0_Pos)) && (err == 0));
+
+            if(err == 0)
+            {
+                retval += 8;
+
+                /* Update new data for D0 */
+                FMC->MPDAT0 = pu32Buf[i];
+                FMC->MPDAT1 = pu32Buf[i + 1u];
+                do
+                {
+                    if((FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) == 0u)
+                    {
+                        __set_PRIMASK(0u);
+                        FMC->ISPADDR = FMC->MPADDR & (~0xful);
+                        idx = (FMC->ISPADDR - u32Addr) / 4u;
+                        err = -1;
+                    }
+                }
+                while((FMC->MPSTS & (3u << FMC_MPSTS_D2_Pos)) && (err == 0));
+
+                if(err == 0)
+                {
+                    retval += 8;
+
+                    /* Update new data for D2*/
+                    FMC->MPDAT2 = pu32Buf[i + 2u];
+                    FMC->MPDAT3 = pu32Buf[i + 3u];
+                    __set_PRIMASK(0u);
+                }
+            }
+
+            if(err < 0)
+            {
+                break;
+            }
+        }
+        if(err == 0)
+        {
+            u32OnProg = 0u;
+            while(FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) {}
+        }
+    }
+    while(u32OnProg);
+
+    return retval;
+}
+
+/**
+  * @brief     Write data to OTP
+  *
+  * @param[in] u32OtpNum    The OTP number(0~255).
+  * @param[in] u32LowWord   Low word of the 64-bits data.
+  * @param[in] u32HighWord   High word of the 64-bits data.
+  *
+  * @retval    0   Success
+  * @retval    -1  Program failed.
+  * @retval    -2  Invalid OTP number.
+  *
+  * @details  Program a 64-bits data to the specified OTP.
+  */
+int32_t FMC_WriteOTP(uint32_t u32OtpNum, uint32_t u32LowWord, uint32_t u32HighWord)
+{
+    int32_t  ret = 0;
+
+    if(u32OtpNum > 255UL)
+    {
+        ret = -2;
+    }
+
+    if(ret == 0)
+    {
+        FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
+        FMC->ISPADDR = FMC_OTP_BASE + u32OtpNum * 8UL;
+        FMC->ISPDAT = u32LowWord;
+        FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+        while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+        if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)
+        {
+            FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+            ret = -1;
+        }
+    }
+
+    if(ret == 0)
+    {
+        FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
+        FMC->ISPADDR = FMC_OTP_BASE + u32OtpNum * 8UL + 4UL;
+        FMC->ISPDAT = u32HighWord;
+        FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+        while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+        if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk)
+        {
+            FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
+            ret = -1;
+        }
+    }
+
+    return ret;
+}
+
+/**
+  * @brief     Remap Bank0/Bank1
+  *
+  * @param[in] u32Bank    Bank Num which will remap to.
+  *
+  * @retval    0   Success
+  * @retval    -1  Program failed.
+  *
+  * @details  Remap Bank0/Bank1
+  */
+int32_t FMC_RemapBank(uint32_t u32Bank)
+{
+    int32_t  ret = 0;
+
+    FMC->ISPCMD = FMC_ISPCMD_BANK_REMAP;
+    FMC->ISPADDR = u32Bank;
+    FMC->ISPDAT = 0x5AA55AA5UL;
+    FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
+
+    while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
+
+    if(FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk)
+    {
+        FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
+        ret = -1;
+    }
+    return ret;
+}
+
+/**@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group FMC_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_fvc.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_fvc.c
new file mode 100644
index 0000000000..e6a028f170
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_fvc.c
@@ -0,0 +1,132 @@
+/**************************************************************************//**
+ * @file     fvc.c
+ * @version  V3.00
+ * @brief    FVC driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup FVC_Driver FVC Driver
+  @{
+*/
+
+
+/** @addtogroup FVC_EXPORTED_FUNCTIONS FVC Exported Functions
+  @{
+*/
+
+
+/**
+  * @brief      Initial firmware version counter
+  * @param      None
+  * @retval     0       Successful
+  * @retval     -1      Failed
+  * @details    FVC needs to be initialed before using it. This function is used to initial the FVC.
+  *
+  */
+int32_t FVC_Open(void)
+{
+    int32_t timeout;
+
+    /* Just return when it is ready */
+    if(FVC->STS & FVC_STS_RDY_Msk)
+        return 0;
+
+    /* Init FVC */
+    FVC->CTL = FVC_VCODE | FVC_CTL_INIT_Msk;
+
+    /* Waiting for ready */
+    timeout = 0x100000;
+    while((FVC->STS & FVC_STS_RDY_Msk) == 0)
+    {
+        if(timeout-- < 0)
+        {
+            /* Init timeout. */
+            return -1;
+        }
+    }
+
+    return 0;
+}
+
+
+
+/**
+  * @brief      Enable anti version rollback
+  * @details    FVC can limit the version number to be increased only to avoid version rollback.
+  *             This function is used to enable it.
+  *
+  */
+void FVC_EnableMonotone(void)
+{
+    FVC->CTL = FVC_VCODE | FVC_CTL_MONOEN_Msk;
+    /* Waiting if FVC is in busy */
+    while(FVC->STS & FVC->STS & FVC_STS_BUSY_Msk) {}
+}
+
+/**
+  * @brief      Set non-volatile version counter
+  * @param[in]  u32NvcIdx    Index number of non-volatile version counter. It could be 0, 1, 4, 5.
+  * @param[in]  u32Cnt       Version Number. It could be 0~63 for u32NvcIdx=0, 1, and 0~255 for u32NvcIdx=4, 5
+  * @retval     0       Successful
+  * @retval     -1      Failed
+  * @details    Set non-volatile version counter
+  *
+  */
+int32_t FVC_SetNVC(uint32_t u32NvcIdx, uint32_t u32Cnt)
+{
+    if(u32NvcIdx < 2)
+    {
+        if(u32Cnt >= 64)
+            /* The counter value is out of range */
+            return -1;
+    }
+    else if(u32NvcIdx < 4)
+        return -1;
+    else if(u32NvcIdx < 6)
+    {
+        /* The counter value is out of range */
+        if(u32Cnt >= 256)
+            /* The counter value is out of range */
+            return -1;
+    }
+    else
+        return -1;
+
+    FVC->NVC[u32NvcIdx] = (FVC->NVC[u32NvcIdx] << 16) | (u32Cnt & 0x3ful);
+    while(FVC->STS & FVC_STS_BUSY_Msk) {}
+    if(FVC->NVC[u32NvcIdx] != u32Cnt)
+        return -1;
+
+    return 0;
+}
+
+
+/**
+  * @brief      Get non-volatile version counter
+  * @param[in]  u32NvcIdx    Index number of non-volatile version counter. It could be 0, 1, 4, 5.
+  * @retval     the version counter
+  * @retval     -1      Failed
+  * @details    Get non-volatile version counter
+  *
+  */
+int32_t FVC_GetNVC(uint32_t u32NvcIdx)
+{
+    if((u32NvcIdx == 2) || (u32NvcIdx == 3) || (u32NvcIdx > 5))
+        return -1;
+
+    return FVC->NVC[u32NvcIdx];
+}
+
+/**@}*/ /* end of group FVC_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group FVC_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_gpio.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_gpio.c
new file mode 100644
index 0000000000..56513fc1a4
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_gpio.c
@@ -0,0 +1,189 @@
+/**************************************************************************//**
+ * @file     gpio.c
+ * @version  V3.00
+ * @brief    M2354 series General Purpose I/O (GPIO) driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup GPIO_Driver GPIO Driver
+  @{
+*/
+
+/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
+  @{
+*/
+
+/**
+ * @brief       Set GPIO operation mode
+ *
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port. \n
+ *                          It could be BIT0 ~ BIT15 for PA, PB and PE. \n
+ *                          It could be BIT0 ~ BIT13 for PC. \n
+ *                          It could be BIT0 ~ BIT12, BIT14 for PD. \n
+ *                          It could be BIT0 ~ BIT11 for PF. \n
+ *                          It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n
+ *                          It could be BIT4 ~ BIT11 for PH.
+ * @param[in]   u32Mode     Operation mode. It could be
+ *                          - \ref GPIO_MODE_INPUT
+ *                          - \ref GPIO_MODE_OUTPUT
+ *                          - \ref GPIO_MODE_OPEN_DRAIN
+ *                          - \ref GPIO_MODE_QUASI
+ *
+ * @return      None
+ *
+ * @details     This function is used to set specified GPIO operation mode.
+ */
+void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
+{
+    uint32_t u32Idx;
+
+    for(u32Idx = 0ul; u32Idx < GPIO_PIN_MAX; u32Idx++)
+    {
+        if((u32PinMask & (1ul << u32Idx)) == (1ul << u32Idx))
+        {
+            port->MODE = (port->MODE & ~(0x3ul << (u32Idx << 1))) | (u32Mode << (u32Idx << 1));
+        }
+    }
+}
+
+/**
+ * @brief       Enable GPIO interrupt
+ *
+ * @param[in]   port            GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32Pin          The pin of specified GPIO port. \n
+ *                              It could be 0 ~ 15 for PA, PB and PE. \n
+ *                              It could be 0 ~ 13 for PC GPIO port. \n
+ *                              It could be 0 ~ 12, 14 for PD GPIO port. \n
+ *                              It could be 0 ~ 11 for PF GPIO port. \n
+ *                              It could be 2 ~ 4, 9 ~ 15 for PG GPIO port. \n
+ *                              It could be 4 ~ 11 for PH GPIO port.
+ * @param[in]   u32IntAttribs   The interrupt attribute of specified GPIO pin. It could be
+ *                              - \ref GPIO_INT_RISING
+ *                              - \ref GPIO_INT_FALLING
+ *                              - \ref GPIO_INT_BOTH_EDGE
+ *                              - \ref GPIO_INT_HIGH
+ *                              - \ref GPIO_INT_LOW
+ *
+ * @return      None
+ *
+ * @details     This function is used to enable specified GPIO pin interrupt.
+ */
+void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs)
+{
+    /* Configure interrupt mode of specified pin */
+    port->INTTYPE = (port->INTTYPE & ~(1ul << u32Pin)) | (((u32IntAttribs >> 24) & 0xFFUL) << u32Pin);
+
+    /* Enable interrupt function of specified pin */
+    port->INTEN = (port->INTEN & ~(0x00010001ul << u32Pin)) | ((u32IntAttribs & 0xFFFFFFUL) << u32Pin);
+}
+
+
+/**
+ * @brief       Disable GPIO interrupt
+ *
+
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32Pin      The pin of specified GPIO port. \n
+ *                          It could be 0 ~ 15 for PA, PB and PE. \n
+ *                          It could be 0 ~ 13 for PC GPIO port. \n
+ *                          It could be 0 ~ 12, 14 for PD GPIO port. \n
+ *                          It could be 0 ~ 11 for PF GPIO port. \n
+ *                          It could be 2 ~ 4, 9 ~ 15 for PG GPIO port. \n
+ *                          It could be 4 ~ 11 for PH GPIO port.
+ *
+ * @return      None
+ *
+ * @details     This function is used to enable specified GPIO pin interrupt.
+ */
+void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin)
+{
+    /* Configure interrupt mode of specified pin */
+    port->INTTYPE &= ~(1UL << u32Pin);
+
+    /* Disable interrupt function of specified pin */
+    port->INTEN &= ~((0x00010001UL) << u32Pin);
+}
+
+/**
+ * @brief       Set GPIO slew rate control
+ *
+
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port. \n
+ *                          It could be BIT0 ~ BIT15 for PA, PB and PE. \n
+ *                          It could be BIT0 ~ BIT13 for PC. \n
+ *                          It could be BIT0 ~ BIT12, BIT14. \n
+ *                          It could be BIT0 ~ BIT11 for PF. \n
+ *                          It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n
+ *                          It could be BIT4 ~ BIT11 for PH.
+ * @param[in]   u32Mode     Slew rate mode. It could be
+ *                          - \ref GPIO_SLEWCTL_NORMAL (maximum 40 MHz at 2.7V)
+ *                          - \ref GPIO_SLEWCTL_HIGH (maximum 80 MHz at 2.7V)
+ *                          - \ref GPIO_SLEWCTL_FAST (maximum 100 MHz at 2.7V)
+ *
+ * @return      None
+ *
+ * @details     This function is used to set specified GPIO operation mode.
+ */
+void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
+{
+    uint32_t u32Idx;
+
+    for(u32Idx = 0ul; u32Idx < GPIO_PIN_MAX; u32Idx++)
+    {
+        if(u32PinMask & (1ul << u32Idx))
+        {
+            port->SLEWCTL = (port->SLEWCTL & ~(0x3ul << (u32Idx << 1))) | (u32Mode << (u32Idx << 1));
+        }
+    }
+}
+
+/**
+ * @brief       Set GPIO Pull-up and Pull-down control
+ *
+
+ * @param[in]   port        GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH.
+ * @param[in]   u32PinMask  The single or multiple pins of specified GPIO port. \n
+ *                          It could be BIT0 ~ BIT15 for PA, PB and PE. \n
+ *                          It could be BIT0 ~ BIT13 for PC. \n
+ *                          It could be BIT0 ~ BIT12, BIT14 for PD. \n
+ *                          It could be BIT0 ~ BIT11 for PF. \n
+ *                          It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n
+ *                          It could be BIT4 ~ BIT11 for PH.
+ * @param[in]   u32Mode     The pin mode of specified GPIO pin. It could be
+ *                          - \ref GPIO_PUSEL_DISABLE
+ *                          - \ref GPIO_PUSEL_PULL_UP
+ *                          - \ref GPIO_PUSEL_PULL_DOWN
+ *
+ * @return      None
+ *
+ * @details     Set the pin mode of specified GPIO pin.
+ */
+void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
+{
+    uint32_t u32Idx;
+
+    for(u32Idx = 0ul; u32Idx < GPIO_PIN_MAX; u32Idx++)
+    {
+        if(u32PinMask & (1ul << u32Idx))
+        {
+            port->PUSEL = (port->PUSEL & ~(0x3ul << (u32Idx << 1))) | (u32Mode << (u32Idx << 1));
+        }
+    }
+}
+
+/**@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group GPIO_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_i2c.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_i2c.c
new file mode 100644
index 0000000000..b245477592
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_i2c.c
@@ -0,0 +1,1442 @@
+/**************************************************************************//**
+ * @file     i2c.c
+ * @version  V3.00
+ * $Revision: 2 $
+ * $Date: 16/08/02 6:02p $
+ * @brief    M2355 series I2C Serial Interface Controller(I2C) driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup I2C_Driver I2C Driver
+  @{
+*/
+
+
+/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Enable specify I2C Controller and set Clock Divider
+  *
+  * @param[in]  i2c         Specify I2C port
+  * @param[in]  u32BusClock The target I2C bus clock in Hz
+  *
+  * @return     Actual I2C bus clock frequency
+  *
+  * @details    The function enable the specify I2C Controller and set proper Clock Divider
+  *             in I2C CLOCK DIVIDED REGISTER (I2CLK) according to the target I2C Bus clock.
+  *             I2C Bus clock = PCLK / (4*(divider+1).
+  *
+  */
+uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock)
+{
+    uint32_t u32Div;
+    uint32_t u32Pclk;
+
+    if((i2c == I2C1) || (i2c == I2C1_NS))
+    {
+        u32Pclk = CLK_GetPCLK1Freq();
+    }
+    else
+    {
+        u32Pclk = CLK_GetPCLK0Freq();
+    }
+
+    u32Div = (uint32_t)(((u32Pclk * 10u) / (u32BusClock * 4u) + 5u) / 10u - 1u); /* Compute proper divider for I2C clock */
+    i2c->CLKDIV = u32Div;
+
+    /* Enable I2C */
+    i2c->CTL0 |= I2C_CTL0_I2CEN_Msk;
+
+    return (u32Pclk / ((u32Div + 1u) << 2u));
+}
+
+/**
+  * @brief      Disable specify I2C Controller
+  *
+  * @param[in]  i2c         Specify I2C port
+    *
+  * @return     None
+  *
+  * @details    Reset I2C Controller and disable specify I2C port.
+    *
+  */
+
+void I2C_Close(I2C_T *i2c)
+{
+    /* Disable I2C */
+    i2c->CTL0 &= ~I2C_CTL0_I2CEN_Msk;
+}
+
+/**
+  * @brief      Clear Time-out Counter flag
+  *
+  * @param[in]  i2c         Specify I2C port
+    *
+  * @return     None
+  *
+  * @details    When Time-out flag will be set, use this function to clear I2C Bus Time-out counter flag .
+    *
+  */
+void I2C_ClearTimeoutFlag(I2C_T *i2c)
+{
+    i2c->TOCTL |= I2C_TOCTL_TOIF_Msk;
+}
+
+/**
+  * @brief      Set Control bit of I2C Controller
+  *
+  * @param[in]  i2c         Specify I2C port
+  * @param[in]  u8Start     Set I2C START condition
+  * @param[in]  u8Stop      Set I2C STOP condition
+  * @param[in]  u8Si        Clear SI flag
+  * @param[in]  u8Ack       Set I2C ACK bit
+  *
+  * @return     None
+  *
+  * @details    The function set I2C Control bit of I2C Bus protocol.
+  *
+  */
+void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack)
+{
+    uint32_t u32Reg = 0u;
+
+    if(u8Start)
+    {
+        u32Reg |= I2C_CTL_STA;
+    }
+    if(u8Stop)
+    {
+        u32Reg |= I2C_CTL_STO;
+    }
+    if(u8Si)
+    {
+        u32Reg |= I2C_CTL_SI;
+    }
+    if(u8Ack)
+    {
+        u32Reg |= I2C_CTL_AA;
+    }
+
+    i2c->CTL0 = (i2c->CTL0 & ~0x3Cu) | u32Reg;
+}
+
+/**
+  * @brief      Disable Interrupt of I2C Controller
+  *
+  * @param[in]  i2c         Specify I2C port
+  *
+  * @return     None
+  *
+  * @details    The function is used for disable I2C interrupt
+  *
+  */
+void I2C_DisableInt(I2C_T *i2c)
+{
+    i2c->CTL0 &= ~I2C_CTL0_INTEN_Msk;
+}
+
+/**
+  * @brief      Enable Interrupt of I2C Controller
+  *
+  * @param[in]  i2c         Specify I2C port
+  *
+  * @return     None
+  *
+  * @details    The function is used for enable I2C interrupt
+  *
+  */
+void I2C_EnableInt(I2C_T *i2c)
+{
+    i2c->CTL0 |= I2C_CTL0_INTEN_Msk;
+}
+
+/**
+ * @brief      Get I2C Bus Clock
+ *
+ * @param[in]  i2c          Specify I2C port
+ *
+ * @return     The actual I2C Bus clock in Hz
+ *
+ * @details    To get the actual I2C Bus Clock frequency.
+ */
+uint32_t I2C_GetBusClockFreq(I2C_T *i2c)
+{
+    uint32_t u32Divider = i2c->CLKDIV;
+    uint32_t u32Pclk;
+
+    if((i2c == I2C1) || (i2c == I2C1_NS))
+    {
+        u32Pclk = CLK_GetPCLK1Freq();
+    }
+    else
+    {
+        u32Pclk = CLK_GetPCLK0Freq();
+    }
+
+    return (u32Pclk / ((u32Divider + 1u) << 2u));
+}
+
+/**
+ * @brief      Set I2C Bus Clock
+ *
+ * @param[in]  i2c          Specify I2C port
+ * @param[in]  u32BusClock  The target I2C Bus Clock in Hz
+ *
+ * @return     The actual I2C Bus Clock in Hz
+ *
+ * @details    To set the actual I2C Bus Clock frequency.
+ */
+uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock)
+{
+    uint32_t u32Div;
+    uint32_t u32Pclk;
+
+    if((i2c == I2C1) || (i2c == I2C1_NS))
+    {
+        u32Pclk = CLK_GetPCLK1Freq();
+    }
+    else
+    {
+        u32Pclk = CLK_GetPCLK0Freq();
+    }
+
+    u32Div = (uint32_t)(((u32Pclk * 10u) / (u32BusClock * 4u) + 5u) / 10u - 1u); /* Compute proper divider for I2C clock */
+    i2c->CLKDIV = u32Div;
+
+    return (u32Pclk / ((u32Div + 1u) << 2u));
+}
+
+/**
+ * @brief      Get Interrupt Flag
+ *
+ * @param[in]  i2c          Specify I2C port
+ *
+ * @return     I2C interrupt flag status
+ *
+ * @details    To get I2C Bus interrupt flag.
+ */
+uint32_t I2C_GetIntFlag(I2C_T *i2c)
+{
+    return ((i2c->CTL0 & I2C_CTL0_SI_Msk) == I2C_CTL0_SI_Msk ? 1ul : 0ul);
+}
+
+/**
+ * @brief      Get I2C Bus Status Code
+ *
+ * @param[in]  i2c          Specify I2C port
+ *
+ * @return     I2C Status Code
+ *
+ * @details    To get I2C Bus Status Code.
+ */
+uint32_t I2C_GetStatus(I2C_T *i2c)
+{
+    return (i2c->STATUS0);
+}
+
+/**
+ * @brief      Read a Byte from I2C Bus
+ *
+ * @param[in]  i2c          Specify I2C port
+ *
+ * @return     I2C Data
+ *
+ * @details    To read a bytes data from specify I2C port.
+ */
+uint8_t I2C_GetData(I2C_T *i2c)
+{
+    return (uint8_t)(i2c->DAT);
+}
+
+/**
+ * @brief      Send a byte to I2C Bus
+ *
+ * @param[in]  i2c          Specify I2C port
+ * @param[in]  u8Data       The data to send to I2C bus
+ *
+ * @return     None
+ *
+ * @details    This function is used to write a byte to specified I2C port
+ */
+void I2C_SetData(I2C_T *i2c, uint8_t u8Data)
+{
+    i2c->DAT = u8Data;
+}
+
+/**
+ * @brief      Set 7-bit Slave Address and GC Mode
+ *
+ * @param[in]  i2c          Specify I2C port
+ * @param[in]  u8SlaveNo    Set the number of I2C address register (0~3)
+ * @param[in]  u8SlaveAddr  7-bit slave address
+ * @param[in]  u8GCMode     Enable/Disable GC mode (I2C_GCMODE_ENABLE / I2C_GCMODE_DISABLE)
+ *
+ * @return     None
+ *
+ * @details    This function is used to set 7-bit slave addresses in I2C SLAVE ADDRESS REGISTER (I2CADDR0~3)
+ *             and enable GC Mode.
+ *
+ */
+void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode)
+{
+    switch(u8SlaveNo)
+    {
+        case 1:
+            i2c->ADDR1  = ((uint32_t)u8SlaveAddr << 1) | u8GCMode;
+            break;
+        case 2:
+            i2c->ADDR2  = ((uint32_t)u8SlaveAddr << 1) | u8GCMode;
+            break;
+        case 3:
+            i2c->ADDR3  = ((uint32_t)u8SlaveAddr << 1) | u8GCMode;
+            break;
+        case 0:
+        default:
+            i2c->ADDR0  = ((uint32_t)u8SlaveAddr << 1) | u8GCMode;
+            break;
+    }
+}
+
+/**
+ * @brief      Configure the mask bits of 7-bit Slave Address
+ *
+ * @param[in]  i2c              Specify I2C port
+ * @param[in]  u8SlaveNo        Set the number of I2C address mask register (0~3)
+ * @param[in]  u8SlaveAddrMask  A byte for slave address mask
+ *
+ * @return     None
+ *
+ * @details    This function is used to set 7-bit slave addresses.
+ *
+ */
+void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask)
+{
+    switch(u8SlaveNo)
+    {
+        case 1:
+            i2c->ADDRMSK1  = (uint32_t)u8SlaveAddrMask << 1;
+            break;
+        case 2:
+            i2c->ADDRMSK2  = (uint32_t)u8SlaveAddrMask << 1;
+            break;
+        case 3:
+            i2c->ADDRMSK3  = (uint32_t)u8SlaveAddrMask << 1;
+            break;
+        case 0:
+        default:
+            i2c->ADDRMSK0  = (uint32_t)u8SlaveAddrMask << 1;
+            break;
+    }
+}
+
+/**
+ * @brief      Enable Time-out Counter Function and support Long Time-out
+ *
+ * @param[in]  i2c              Specify I2C port
+ * @param[in]  u8LongTimeout    Configure DIV4 to enable Long Time-out (0/1)
+ *
+ * @return     None
+ *
+ * @details    This function enable Time-out Counter function and configure DIV4 to support Long
+ *             Time-out.
+ *
+ */
+void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout)
+{
+    if(u8LongTimeout)
+    {
+        i2c->TOCTL |= I2C_TOCTL_TOCDIV4_Msk;
+    }
+    else
+    {
+        i2c->TOCTL &= ~I2C_TOCTL_TOCDIV4_Msk;
+    }
+
+    i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk;
+}
+
+/**
+ * @brief      Disable Time-out Counter Function
+ *
+ * @param[in]  i2c          Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    To disable Time-out Counter function in I2CTOC register.
+ *
+ */
+void I2C_DisableTimeout(I2C_T *i2c)
+{
+    i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk;
+}
+
+/**
+ * @brief      Enable I2C Wake-up Function
+ *
+ * @param[in]  i2c          Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    To enable Wake-up function of I2C Wake-up control register.
+ *
+ */
+void I2C_EnableWakeup(I2C_T *i2c)
+{
+    i2c->WKCTL |= I2C_WKCTL_WKEN_Msk;
+}
+
+/**
+ * @brief      Disable I2C Wake-up Function
+ *
+ * @param[in]  i2c          Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    To disable Wake-up function of I2C Wake-up control register.
+ *
+ */
+void I2C_DisableWakeup(I2C_T *i2c)
+{
+    i2c->WKCTL &= ~I2C_WKCTL_WKEN_Msk;
+}
+
+/**
+ * @brief      To get SMBus Status
+ *
+ * @param[in]  i2c          Specify I2C port
+ *
+ * @return     SMBus status
+ *
+ * @details    To get the Bus Management status of I2C_BUSSTS register
+ *
+ */
+uint32_t I2C_SMBusGetStatus(I2C_T *i2c)
+{
+    return (i2c->BUSSTS);
+}
+
+/**
+ * @brief      Clear SMBus Interrupt Flag
+ *
+ * @param[in]  i2c              Specify I2C port
+ * @param[in]  u8SMBusIntFlag   Specify SMBus interrupt flag
+ *
+ * @return     None
+ *
+ * @details    To clear flags of I2C_BUSSTS status register if interrupt set.
+ *
+ */
+void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8SMBusIntFlag)
+{
+    i2c->BUSSTS = u8SMBusIntFlag;
+}
+
+/**
+ * @brief      Set SMBus Bytes Counts of Transmission or Reception
+ *
+ * @param[in]  i2c              Specify I2C port
+ * @param[in]  u32PktSize       Transmit / Receive bytes
+ *
+ * @return     None
+ *
+ * @details    The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes.
+ *
+ */
+void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize)
+{
+    i2c->PKTSIZE = u32PktSize;
+}
+
+/**
+ * @brief      Init SMBus Host/Device Mode
+ *
+ * @param[in]  i2c              Specify I2C port
+ * @param[in]  u8HostDevice     Init SMBus port mode(I2C_SMBH_ENABLE(1)/I2C_SMBD_ENABLE(0))
+ *
+ * @return     None
+ *
+ * @details    Using SMBus communication must specify the port is a Host or a Device.
+ *
+ */
+void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice)
+{
+    /* Clear  BMHEN, BMDEN of BUSCTL Register */
+    i2c->BUSCTL &=  ~(I2C_BUSCTL_BMHEN_Msk | I2C_BUSCTL_BMDEN_Msk);
+
+    /* Set SMBus Host/Device Mode, and enable Bus Management*/
+    if(u8HostDevice == (uint8_t)I2C_SMBH_ENABLE)
+    {
+        i2c->BUSCTL |= (I2C_BUSCTL_BMHEN_Msk | I2C_BUSCTL_BUSEN_Msk);
+    }
+    else
+    {
+        i2c->BUSCTL |= (I2C_BUSCTL_BMDEN_Msk | I2C_BUSCTL_BUSEN_Msk);
+    }
+}
+
+/**
+ * @brief      Disable SMBus function
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     None
+ *
+ * @details    Disable all SMBus function include Bus disable, CRC check, Acknowledge by manual, Host/Device Mode.
+ *
+ */
+void I2C_SMBusClose(I2C_T *i2c)
+{
+
+    i2c->BUSCTL = 0x00U;
+}
+
+/**
+ * @brief      Enable SMBus PEC Transmit Function
+ *
+ * @param[in]  i2c              Specify I2C port
+ * @param[in]  u8PECTxEn        CRC transmit enable(PECTX_ENABLE) or disable(PECTX_DISABLE)
+ *
+ * @return     None
+ *
+ * @details    When enable CRC check function, the Host or Device needs to transmit CRC byte.
+ *
+ */
+void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn)
+{
+    i2c->BUSCTL &= ~I2C_BUSCTL_PECTXEN_Msk;
+
+    if(u8PECTxEn)
+    {
+        i2c->BUSCTL |= (I2C_BUSCTL_PECEN_Msk | I2C_BUSCTL_PECTXEN_Msk);
+    }
+    else
+    {
+        i2c->BUSCTL |= I2C_BUSCTL_PECEN_Msk;
+    }
+}
+
+/**
+ * @brief      Get SMBus CRC value
+ *
+ * @param[in]  i2c              Specify I2C port
+ *
+ * @return     A byte is packet error check value
+ *
+ * @details    The CRC check value after a transmission or a reception by count by using CRC8
+ *
+ */
+uint8_t I2C_SMBusGetPECValue(I2C_T *i2c)
+{
+    return (uint8_t)i2c->PKTCRC;
+}
+
+/**
+ * @brief      Calculate Time-out of SMBus idle period
+ *
+ * @param[in]  i2c              Specify I2C port
+ * @param[in]  u32Us               Time-out length(us)
+ * @param[in]  u32Hclk          I2C peripheral clock frequency
+ *
+ * @return     None
+ *
+ * @details    This function is used to set SMBus Time-out length when bus is in Idle state.
+ *
+ */
+
+void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t u32Us, uint32_t u32Hclk)
+{
+    uint32_t  u32Div, u32HclkKHz;
+
+    i2c->BUSCTL |= I2C_BUSCTL_TIDLE_Msk;
+    u32HclkKHz = u32Hclk / 1000U;
+    u32Div = (((u32Us * u32HclkKHz) / 1000U) >> 2U) - 1U;
+    if(u32Div > 255U)
+    {
+        i2c->BUSTOUT = 0xFFU;
+    }
+    else
+    {
+        i2c->BUSTOUT = u32Div;
+    }
+
+}
+
+/**
+ * @brief      Calculate Time-out of SMBus active period
+ *
+ * @param[in]  i2c              Specify I2C port
+ * @param[in]  ms               Time-out length(ms)
+ * @param[in]  u32Pclk          peripheral clock frequency
+ *
+ * @return     None
+ *
+ * @details    This function is used to set SMBus Time-out length when bus is in active state.
+ *             Time-out length is calculate the SCL line "one clock" pull low timing.
+ *
+ */
+
+void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk)
+{
+    uint32_t u32Div, u32Pclk_kHz;
+
+    i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk;
+
+    /* DIV4 disabled */
+    i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk;
+    u32Pclk_kHz = u32Pclk / 1000U;
+    u32Div = ((ms * u32Pclk_kHz) / (16U * 1024U)) - 1U;
+    if(u32Div <= 0xFFU)
+    {
+        i2c->BUSTOUT = u32Div;
+    }
+    else
+    {
+        /* DIV4 enabled */
+        i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk;
+        i2c->BUSTOUT = (((ms * u32Pclk_kHz) / (16U * 1024U * 4U)) - 1U) & 0xFFU; /* The max value is 255 */
+    }
+}
+
+/**
+ * @brief      Calculate Cumulative Clock low Time-out of SMBus active period
+ *
+ * @param[in]  i2c              Specify I2C port
+ * @param[in]  ms               Time-out length(ms)
+ * @param[in]  u32Pclk          peripheral clock frequency
+ *
+ * @return     None
+ *
+ * @details    This function is used to set SMBus Time-out length when bus is in Active state.
+ *             Time-out length is calculate the SCL line "clocks" low cumulative timing.
+ *
+ */
+
+void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk)
+{
+    uint32_t u32Div, u32Pclk_kHz;
+
+    i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk;
+
+    /* DIV4 disabled */
+    i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk;
+    u32Pclk_kHz = u32Pclk / 1000U;
+    u32Div = ((ms * u32Pclk_kHz) / (16U * 1024U)) - 1U;
+    if(u32Div <= 0xFFU)
+    {
+        i2c->CLKTOUT = u32Div;
+    }
+    else
+    {
+        /* DIV4 enabled */
+        i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk;
+        i2c->CLKTOUT = (((ms * u32Pclk_kHz) / (16U * 1024U * 4U)) - 1U) & 0xFFU; /* The max value is 255 */
+    }
+}
+
+/**
+  * @brief      Write a byte to Slave
+  *
+  * @param[in]  *i2c            Point to I2C peripheral
+  * @param[in]  u8SlaveAddr     Access Slave address(7-bit)
+  * @param[in]  u8Data            Write a byte data to Slave
+  *
+  * @retval     0               Write data success
+  * @retval     1               Write data fail, or bus occurs error events
+  *
+  * @details    The function is used for I2C Master write a byte data to Slave.
+  *
+  */
+
+uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8Data)
+{
+    uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;
+
+    I2C_START(i2c);
+    while(u8Xfering && (u8Err == 0u))
+    {
+        I2C_WAIT_READY(i2c) {}
+        switch(I2C_GET_STATUS(i2c))
+        {
+            case 0x08u:
+                I2C_SET_DATA(i2c, (uint32_t)(u8SlaveAddr << 1u | (uint8_t)0x00u));    /* Write SLA+W to Register I2CDAT */
+                u8Ctrl = I2C_CTL_SI;                              /* Clear SI */
+                break;
+            case 0x18u:                                           /* Slave Address ACK */
+                I2C_SET_DATA(i2c, u8Data);                          /* Write data to I2CDAT */
+                break;
+            case 0x20u:                                           /* Slave Address NACK */
+            case 0x30u:                                           /* Master transmit data NACK */
+                u8Ctrl = I2C_CTL_STO_SI;                          /* Clear SI and send STOP */
+                u8Err = 1u;
+                break;
+            case 0x28u:
+                u8Ctrl = I2C_CTL_STO_SI;                          /* Clear SI and send STOP */
+                u8Xfering = 0u;
+                break;
+            case 0x38u:                                           /* Arbitration Lost */
+            default:                                              /* Unknow status */
+                u8Ctrl = I2C_CTL_STO_SI;                          /* Clear SI and send STOP */
+                u8Err = 1u;
+                break;
+        }
+        I2C_SET_CONTROL_REG(i2c, u8Ctrl);                        /* Write controlbit to I2C_CTL register */
+    }
+    return (u8Err | u8Xfering);                                  /* return (Success)/(Fail) status */
+}
+
+/**
+  * @brief      Write multi bytes to Slave
+  *
+  * @param[in]  *i2c            Point to I2C peripheral
+  * @param[in]  u8SlaveAddr     Access Slave address(7-bit)
+  * @param[in]  *au8Data           Pointer to array to write data to Slave
+  * @param[in]  u32wLen         How many bytes need to write to Slave
+  *
+  * @return     A length of how many bytes have been transmitted.
+  *
+  * @details    The function is used for I2C Master write multi bytes data to Slave.
+  *
+  */
+
+uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t au8Data[], uint32_t u32wLen)
+{
+    uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;
+    uint32_t u32txLen = 0u;
+
+    I2C_START(i2c);                                              /* Send START */
+    while(u8Xfering && (u8Err == 0u))
+    {
+        I2C_WAIT_READY(i2c) {}
+        switch(I2C_GET_STATUS(i2c))
+        {
+            case 0x08u:
+                I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | (uint8_t)0x00u));    /* Write SLA+W to Register I2CDAT */
+                u8Ctrl = I2C_CTL_SI;                           /* Clear SI */
+                break;
+            case 0x18u:                                           /* Slave Address ACK */
+            case 0x28u:
+                if(u32txLen < u32wLen)
+                {
+                    I2C_SET_DATA(i2c, au8Data[u32txLen++]);                /* Write Data to I2CDAT */
+                }
+                else
+                {
+                    u8Ctrl = I2C_CTL_STO_SI;                   /* Clear SI and send STOP */
+                    u8Xfering = 0u;
+                }
+                break;
+            case 0x20u:                                           /* Slave Address NACK */
+            case 0x30u:                                           /* Master transmit data NACK */
+                u8Ctrl = I2C_CTL_STO_SI;                       /* Clear SI and send STOP */
+                u8Err = 1u;
+                break;
+            case 0x38u:                                           /* Arbitration Lost */
+            default:                                             /* Unknow status */
+                u8Ctrl = I2C_CTL_STO_SI;                       /* Clear SI and send STOP */
+                u8Err = 1u;
+                break;
+        }
+        I2C_SET_CONTROL_REG(i2c, u8Ctrl);                        /* Write controlbit to I2C_CTL register */
+    }
+    return u32txLen;                                             /* Return bytes length that have been transmitted */
+}
+
+/**
+  * @brief      Specify a byte register address and write a byte to Slave
+  *
+  * @param[in]  *i2c            Point to I2C peripheral
+  * @param[in]  u8SlaveAddr     Access Slave address(7-bit)
+  * @param[in]  u8DataAddr      Specify a address (1 byte) of data write to
+  * @param[in]  u8Data            A byte data to write it to Slave
+  *
+  * @retval     0               Write data success
+  * @retval     1               Write data fail, or bus occurs error events
+  *
+  * @details    The function is used for I2C Master specify a address that data write to in Slave.
+  *
+  */
+
+uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t u8Data)
+{
+    uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;
+    uint32_t u32txLen = 0u;
+
+    I2C_START(i2c);                                              /* Send START */
+    while(u8Xfering && (u8Err == 0u))
+    {
+        I2C_WAIT_READY(i2c) {}
+        switch(I2C_GET_STATUS(i2c))
+        {
+            case 0x08u:
+                I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | (uint8_t)0x00u));    /* Send Slave address with write bit */
+                u8Ctrl = I2C_CTL_SI;                           /* Clear SI */
+                break;
+            case 0x18u:                                           /* Slave Address ACK */
+                I2C_SET_DATA(i2c, u8DataAddr);                   /* Write Lo byte address of register */
+                break;
+            case 0x20u:                                           /* Slave Address NACK */
+            case 0x30u:                                           /* Master transmit data NACK */
+                u8Ctrl = I2C_CTL_STO_SI;                       /* Clear SI and send STOP */
+                u8Err = 1u;
+                break;
+            case 0x28u:
+                if(u32txLen < 1u)
+                {
+                    I2C_SET_DATA(i2c, u8Data);
+                    u32txLen++;
+                }
+                else
+                {
+                    u8Ctrl = I2C_CTL_STO_SI;                   /* Clear SI and send STOP */
+                    u8Xfering = 0u;
+                }
+                break;
+            case 0x38u:                                           /* Arbitration Lost */
+            default:                                             /* Unknow status */
+                u8Ctrl = I2C_CTL_STO_SI;                       /* Clear SI and send STOP */
+                u8Err = 1u;
+                break;
+        }
+        I2C_SET_CONTROL_REG(i2c, u8Ctrl);                        /* Write controlbit to I2C_CTL register */
+    }
+    return (u8Err | u8Xfering);                                  /* return (Success)/(Fail) status */
+}
+
+
+/**
+  * @brief      Specify a byte register address and write multi bytes to Slave
+  *
+  * @param[in]  *i2c            Point to I2C peripheral
+  * @param[in]  u8SlaveAddr     Access Slave address(7-bit)
+  * @param[in]  u8DataAddr      Specify a address (1 byte) of data write to
+  * @param[in]  *au8Data           Pointer to array to write data to Slave
+  * @param[in]  u32wLen         How many bytes need to write to Slave
+  *
+  * @return     A length of how many bytes have been transmitted.
+  *
+  * @details    The function is used for I2C Master specify a byte address that multi data bytes write to in Slave.
+  *
+  */
+
+uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t au8Data[], uint32_t u32wLen)
+{
+    uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;
+    uint32_t u32txLen = 0u;
+
+    I2C_START(i2c);                                              /* Send START */
+    while(u8Xfering && (u8Err == 0u))
+    {
+        I2C_WAIT_READY(i2c) {}
+        switch(I2C_GET_STATUS(i2c))
+        {
+            case 0x08u:
+                I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | (uint8_t)0x00u));    /* Write SLA+W to Register I2CDAT */
+                u8Ctrl = I2C_CTL_SI;
+                break;
+            case 0x18u:                                           /* Slave Address ACK */
+                I2C_SET_DATA(i2c, u8DataAddr);                   /* Write Lo byte address of register */
+                break;
+            case 0x20u:                                           /* Slave Address NACK */
+            case 0x30u:                                           /* Master transmit data NACK */
+                u8Ctrl = I2C_CTL_STO_SI;                       /* Clear SI and send STOP */
+                u8Err = 1u;
+                break;
+            case 0x28u:
+                if(u32txLen < u32wLen)
+                {
+                    I2C_SET_DATA(i2c, au8Data[u32txLen++]);
+                }
+                else
+                {
+                    u8Ctrl = I2C_CTL_STO_SI;                   /* Clear SI and send STOP */
+                    u8Xfering = 0u;
+                }
+                break;
+            case 0x38u:                                           /* Arbitration Lost */
+            default:                                             /* Unknow status */
+                u8Ctrl = I2C_CTL_STO_SI;                       /* Clear SI and send STOP */
+                u8Err = 1u;
+                break;
+        }
+        I2C_SET_CONTROL_REG(i2c, u8Ctrl);                        /* Write controlbit to I2C_CTL register */
+    }
+
+    return u32txLen;                                             /* Return bytes length that have been transmitted */
+}
+
+/**
+  * @brief      Specify two bytes register address and Write a byte to Slave
+  *
+  * @param[in]  *i2c            Point to I2C peripheral
+  * @param[in]  u8SlaveAddr     Access Slave address(7-bit)
+  * @param[in]  u16DataAddr     Specify a address (2 byte) of data write to
+  * @param[in]  u8Data            Write a byte data to Slave
+  *
+  * @retval     0               Write data success
+  * @retval     1               Write data fail, or bus occurs error events
+  *
+  * @details    The function is used for I2C Master specify two bytes address that data write to in Slave.
+  *
+  */
+
+uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t u8Data)
+{
+    uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u;
+    uint32_t u32txLen = 0u;
+
+    I2C_START(i2c);                                                         /* Send START */
+    while(u8Xfering && (u8Err == 0u))
+    {
+        I2C_WAIT_READY(i2c) {}
+        switch(I2C_GET_STATUS(i2c))
+        {
+            case 0x08u:
+                I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | (uint8_t)0x00u));               /* Write SLA+W to Register I2CDAT */
+                u8Ctrl = I2C_CTL_SI;                                      /* Clear SI */
+                break;
+            case 0x18u:                                                      /* Slave Address ACK */
+                I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u));    /* Write Hi byte address of register */
+                break;
+            case 0x20u:                                                      /* Slave Address NACK */
+            case 0x30u:                                                      /* Master transmit data NACK */
+                u8Ctrl = I2C_CTL_STO_SI;                                  /* Clear SI and send STOP */
+                u8Err = 1u;
+                break;
+            case 0x28u:
+                if(u8Addr)
+                {
+                    I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu));       /* Write Lo byte address of register */
+                    u8Addr = 0u;
+                }
+                else if((u32txLen < 1u) && (u8Addr == 0u))
+                {
+                    I2C_SET_DATA(i2c, u8Data);
+                    u32txLen++;
+                }
+                else
+                {
+                    u8Ctrl = I2C_CTL_STO_SI;                              /* Clear SI and send STOP */
+                    u8Xfering = 0u;
+                }
+                break;
+            case 0x38u:                                                      /* Arbitration Lost */
+            default:                                                        /* Unknow status */
+                u8Ctrl = I2C_CTL_STO_SI;                                  /* Clear SI and send STOP */
+                u8Err = 1u;
+                break;
+        }
+        I2C_SET_CONTROL_REG(i2c, u8Ctrl);                                   /* Write controlbit to I2C_CTL register */
+    }
+    return (u8Err | u8Xfering);                                             /* return (Success)/(Fail) status */
+}
+
+
+/**
+  * @brief      Specify two bytes register address and write multi bytes to Slave
+  *
+  * @param[in]  *i2c            Point to I2C peripheral
+  * @param[in]  u8SlaveAddr     Access Slave address(7-bit)
+  * @param[in]  u16DataAddr     Specify a address (2 bytes) of data write to
+  * @param[in]  au8Data[]          A data array for write data to Slave
+  * @param[in]  u32wLen         How many bytes need to write to Slave
+  *
+  * @return     A length of how many bytes have been transmitted.
+  *
+  * @details    The function is used for I2C Master specify a byte address that multi data write to in Slave.
+  *
+  */
+
+uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t au8Data[], uint32_t u32wLen)
+{
+    uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u;
+    uint32_t u32txLen = 0u;
+
+    I2C_START(i2c);                                                         /* Send START */
+    while(u8Xfering && (u8Err == 0u))
+    {
+        I2C_WAIT_READY(i2c) {}
+        switch(I2C_GET_STATUS(i2c))
+        {
+            case 0x08u:
+                I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | (uint8_t)0x00u));               /* Write SLA+W to Register I2CDAT */
+                u8Ctrl = I2C_CTL_SI;                                      /* Clear SI */
+                break;
+            case 0x18u:                                                      /* Slave Address ACK */
+                I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u));    /* Write Hi byte address of register */
+                break;
+            case 0x20u:                                                      /* Slave Address NACK */
+            case 0x30u:                                                      /* Master transmit data NACK */
+                u8Ctrl = I2C_CTL_STO_SI;                                  /* Clear SI and send STOP */
+                u8Err = 1u;
+                break;
+            case 0x28u:
+                if(u8Addr)
+                {
+                    I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu));       /* Write Lo byte address of register */
+                    u8Addr = 0u;
+                }
+                else if((u32txLen < u32wLen) && (u8Addr == 0u))
+                {
+                    I2C_SET_DATA(i2c, au8Data[u32txLen++]);                           /* Write data to Register I2CDAT*/
+                }
+                else
+                {
+                    u8Ctrl = I2C_CTL_STO_SI;                              /* Clear SI and send STOP */
+                    u8Xfering = 0u;
+                }
+                break;
+            case 0x38u:                                                      /* Arbitration Lost */
+            default:                                                        /* Unknow status */
+                u8Ctrl = I2C_CTL_STO_SI;                                  /* Clear SI and send STOP */
+                u8Err = 1u;
+                break;
+        }
+        I2C_SET_CONTROL_REG(i2c, u8Ctrl);                                   /* Write controlbit to I2C_CTL register */
+    }
+    return u32txLen;                                                        /* Return bytes length that have been transmitted */
+}
+
+/**
+  * @brief      Read a byte from Slave
+  *
+  * @param[in]  *i2c            Point to I2C peripheral
+  * @param[in]  u8SlaveAddr     Access Slave address(7-bit)
+  *
+  * @return     Read a byte data from Slave
+  *
+  * @details    The function is used for I2C Master to read a byte data from Slave.
+  *
+  */
+uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr)
+{
+    uint8_t u8Xfering = 1u, u8Err = 0u, rdata = 0u, u8Ctrl = 0u;
+
+    I2C_START(i2c);                                                /* Send START */
+    while(u8Xfering && (u8Err == 0u))
+    {
+        I2C_WAIT_READY(i2c) {}
+        switch(I2C_GET_STATUS(i2c))
+        {
+            case 0x08u:
+                I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | (uint8_t)0x01u));    /* Write SLA+R to Register I2CDAT */
+                u8Ctrl = I2C_CTL_SI;                             /* Clear SI */
+                break;
+            case 0x40u:                                             /* Slave Address ACK */
+                u8Ctrl = I2C_CTL_SI;                             /* Clear SI */
+                break;
+            case 0x48u:                                             /* Slave Address NACK */
+                u8Ctrl = I2C_CTL_STO_SI;                         /* Clear SI and send STOP */
+                u8Err = 1u;
+                break;
+            case 0x58u:
+                rdata = (unsigned char) I2C_GET_DATA(i2c);         /* Receive Data */
+                u8Ctrl = I2C_CTL_STO_SI;                         /* Clear SI and send STOP */
+                u8Xfering = 0u;
+                break;
+            case 0x38u:                                             /* Arbitration Lost */
+            default:                                               /* Unknow status */
+                u8Ctrl = I2C_CTL_STO_SI;                         /* Clear SI and send STOP */
+                u8Err = 1u;
+                break;
+        }
+        I2C_SET_CONTROL_REG(i2c, u8Ctrl);                          /* Write controlbit to I2C_CTL register */
+    }
+    if(u8Err)
+    {
+        rdata = 0u;                                                 /* If occurs error, return 0 */
+    }
+    return rdata;                                                  /* Return read data */
+}
+
+
+/**
+  * @brief      Read multi bytes from Slave
+  *
+  * @param[in]  *i2c            Point to I2C peripheral
+  * @param[in]  u8SlaveAddr     Access Slave address(7-bit)
+  * @param[out] au8Rdata[]         A data array to store data from Slave
+  * @param[in]  u32rLen         How many bytes need to read from Slave
+  *
+  * @return     A length of how many bytes have been received
+  *
+  * @details    The function is used for I2C Master to read multi data bytes from Slave.
+  *
+  *
+  */
+uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t au8Rdata[], uint32_t u32rLen)
+{
+    uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;
+    uint32_t u32rxLen = 0u;
+
+    I2C_START(i2c);                                                /* Send START */
+    while(u8Xfering && (u8Err == 0u))
+    {
+        I2C_WAIT_READY(i2c) {}
+        switch(I2C_GET_STATUS(i2c))
+        {
+            case 0x08u:
+                I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | (uint8_t)0x01u));    /* Write SLA+R to Register I2CDAT */
+                u8Ctrl = I2C_CTL_SI;                             /* Clear SI */
+                break;
+            case 0x40u:                                             /* Slave Address ACK */
+                u8Ctrl = I2C_CTL_SI_AA;                          /* Clear SI and set ACK */
+                break;
+            case 0x48u:                                             /* Slave Address NACK */
+                u8Ctrl = I2C_CTL_STO_SI;                         /* Clear SI and send STOP */
+                u8Err = 1u;
+                break;
+            case 0x50u:
+                au8Rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c);    /* Receive Data */
+                if(u32rxLen < (u32rLen - 1u))
+                {
+                    u8Ctrl = I2C_CTL_SI_AA;                             /* Clear SI and set ACK */
+                }
+                else
+                {
+                    u8Ctrl = I2C_CTL_SI;                                /* Clear SI */
+                }
+                break;
+            case 0x58u:
+                au8Rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c);    /* Receive Data */
+                u8Ctrl = I2C_CTL_STO_SI;                                /* Clear SI and send STOP */
+                u8Xfering = 0u;
+                break;
+            case 0x38u:                                                    /* Arbitration Lost */
+            default:                                                      /* Unknow status */
+                u8Ctrl = I2C_CTL_STO_SI;                                /* Clear SI and send STOP */
+                u8Err = 1u;
+                break;
+        }
+        I2C_SET_CONTROL_REG(i2c, u8Ctrl);                                 /* Write controlbit to I2C_CTL register */
+    }
+    return u32rxLen;                                                      /* Return bytes length that have been received */
+}
+
+
+/**
+  * @brief      Specify a byte register address and read a byte from Slave
+  *
+  * @param[in]  *i2c            Point to I2C peripheral
+  * @param[in]  u8SlaveAddr     Access Slave address(7-bit)
+  * @param[in]  u8DataAddr      Specify a address(1 byte) of data read from
+  *
+  * @return     Read a byte data from Slave
+  *
+  * @details    The function is used for I2C Master specify a byte address that a data byte read from Slave.
+  *
+  *
+  */
+uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr)
+{
+    uint8_t u8Xfering = 1u, u8Err = 0u, u8Rdata = 0u, u8Ctrl = 0u;
+
+    I2C_START(i2c);                                                /* Send START */
+    while(u8Xfering && (u8Err == 0u))
+    {
+        I2C_WAIT_READY(i2c) {}
+        switch(I2C_GET_STATUS(i2c))
+        {
+            case 0x08u:
+                I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | (uint8_t)0x00u));      /* Write SLA+W to Register I2CDAT */
+                u8Ctrl = I2C_CTL_SI;                             /* Clear SI */
+                break;
+            case 0x18u:                                             /* Slave Address ACK */
+                I2C_SET_DATA(i2c, u8DataAddr);                     /* Write Lo byte address of register */
+                break;
+            case 0x20u:                                             /* Slave Address NACK */
+            case 0x30u:                                             /* Master transmit data NACK */
+                u8Ctrl = I2C_CTL_STO_SI;                         /* Clear SI and send STOP */
+                u8Err = 1u;
+                break;
+            case 0x28u:
+                u8Ctrl = I2C_CTL_STA_SI;                         /* Send repeat START */
+                break;
+            case 0x10u:
+                I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | (uint8_t)0x01u));    /* Write SLA+R to Register I2CDAT */
+                u8Ctrl = I2C_CTL_SI;                               /* Clear SI */
+                break;
+            case 0x40u:                                             /* Slave Address ACK */
+                u8Ctrl = I2C_CTL_SI;                             /* Clear SI */
+                break;
+            case 0x48u:                                             /* Slave Address NACK */
+                u8Ctrl = I2C_CTL_STO_SI;                         /* Clear SI and send STOP */
+                u8Err = 1u;
+                break;
+            case 0x58u:
+                u8Rdata = (uint8_t) I2C_GET_DATA(i2c);               /* Receive Data */
+                u8Ctrl = I2C_CTL_STO_SI;                         /* Clear SI and send STOP */
+                u8Xfering = 0u;
+                break;
+            case 0x38u:                                             /* Arbitration Lost */
+            default:                                               /* Unknow status */
+                u8Ctrl = I2C_CTL_STO_SI;                         /* Clear SI and send STOP */
+                u8Err = 1u;
+                break;
+        }
+        I2C_SET_CONTROL_REG(i2c, u8Ctrl);                          /* Write controlbit to I2C_CTL register */
+    }
+    if(u8Err)
+    {
+        u8Rdata = 0u;                                                 /* If occurs error, return 0 */
+    }
+    return u8Rdata;                                                  /* Return read data */
+}
+
+/**
+  * @brief      Specify a byte register address and read multi bytes from Slave
+  *
+  * @param[in]  *i2c            Point to I2C peripheral
+  * @param[in]  u8SlaveAddr     Access Slave address(7-bit)
+  * @param[in]  u8DataAddr      Specify a address (1 bytes) of data read from
+  * @param[out] au8Rdata[]         A data array to store data from Slave
+  * @param[in]  u32rLen         How many bytes need to read from Slave
+  *
+  * @return     A length of how many bytes have been received
+  *
+  * @details    The function is used for I2C Master specify a byte address that multi data bytes read from Slave.
+  *
+  *
+  */
+uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t au8Rdata[], uint32_t u32rLen)
+{
+    uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;
+    uint32_t u32rxLen = 0u;
+
+    I2C_START(i2c);                                                /* Send START */
+    while(u8Xfering && (u8Err == 0u))
+    {
+        I2C_WAIT_READY(i2c) {}
+        switch(I2C_GET_STATUS(i2c))
+        {
+            case 0x08u:
+                I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | (uint8_t)0x00u));      /* Write SLA+W to Register I2CDAT */
+                u8Ctrl = I2C_CTL_SI;                             /* Clear SI */
+                break;
+            case 0x18u:                                             /* Slave Address ACK */
+                I2C_SET_DATA(i2c, u8DataAddr);                     /* Write Lo byte address of register */
+                break;
+            case 0x20u:                                             /* Slave Address NACK */
+            case 0x30u:                                             /* Master transmit data NACK */
+                u8Ctrl = I2C_CTL_STO_SI;                         /* Clear SI and send STOP */
+                u8Err = 1u;
+                break;
+            case 0x28u:
+                u8Ctrl = I2C_CTL_STA_SI;                         /* Send repeat START */
+                break;
+            case 0x10u:
+                I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | (uint8_t)0x01u));    /* Write SLA+R to Register I2CDAT */
+                u8Ctrl = I2C_CTL_SI;                             /* Clear SI */
+                break;
+            case 0x40u:                                             /* Slave Address ACK */
+                u8Ctrl = I2C_CTL_SI_AA;                          /* Clear SI and set ACK */
+                break;
+            case 0x48u:                                             /* Slave Address NACK */
+                u8Ctrl = I2C_CTL_STO_SI;                         /* Clear SI and send STOP */
+                u8Err = 1u;
+                break;
+            case 0x50u:
+                au8Rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c);   /* Receive Data */
+                if(u32rxLen < (u32rLen - 1u))
+                {
+                    u8Ctrl = I2C_CTL_SI_AA;                      /* Clear SI and set ACK */
+                }
+                else
+                {
+                    u8Ctrl = I2C_CTL_SI;                         /* Clear SI */
+                }
+                break;
+            case 0x58u:
+                au8Rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c);   /* Receive Data */
+                u8Ctrl = I2C_CTL_STO_SI;                         /* Clear SI and send STOP */
+                u8Xfering = 0u;
+                break;
+            case 0x38u:                                             /* Arbitration Lost */
+            default:                                               /* Unknow status */
+                u8Ctrl = I2C_CTL_STO_SI;                         /* Clear SI and send STOP */
+                u8Err = 1u;
+                break;
+        }
+        I2C_SET_CONTROL_REG(i2c, u8Ctrl);                          /* Write controlbit to I2C_CTL register */
+    }
+    return u32rxLen;                                               /* Return bytes length that have been received */
+}
+
+/**
+  * @brief      Specify two bytes register address and read a byte from Slave
+  *
+  * @param[in]  *i2c            Point to I2C peripheral
+  * @param[in]  u8SlaveAddr     Access Slave address(7-bit)
+  * @param[in]  u16DataAddr     Specify an address(2 bytes) of data read from
+  *
+  * @return     Read a byte data from Slave
+  *
+  * @details    The function is used for I2C Master specify two bytes address that a data byte read from Slave.
+  *
+  *
+  */
+uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr)
+{
+    uint8_t u8Xfering = 1u, u8Err = 0u, u8Rdata = 0u, u8Addr = 1u, u8Ctrl = 0u;
+
+    I2C_START(i2c);                                                         /* Send START */
+    while(u8Xfering && (u8Err == 0u))
+    {
+        I2C_WAIT_READY(i2c) {}
+        switch(I2C_GET_STATUS(i2c))
+        {
+            case 0x08u:
+                I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | (uint8_t)0x00u));               /* Write SLA+W to Register I2CDAT */
+                u8Ctrl = I2C_CTL_SI;                                      /* Clear SI */
+                break;
+            case 0x18u:                                                      /* Slave Address ACK */
+                I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u));    /* Write Hi byte address of register */
+                break;
+            case 0x20u:                                                      /* Slave Address NACK */
+            case 0x30u:                                                      /* Master transmit data NACK */
+                u8Ctrl = I2C_CTL_STO_SI;                                  /* Clear SI and send STOP */
+                u8Err = 1u;
+                break;
+            case 0x28u:
+                if(u8Addr)
+                {
+                    I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu));       /* Write Lo byte address of register */
+                    u8Addr = 0u;
+                }
+                else
+                {
+                    u8Ctrl = I2C_CTL_STA_SI;                              /* Clear SI and send repeat START */
+                }
+                break;
+            case 0x10u:
+                I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | (uint8_t)0x01u));             /* Write SLA+R to Register I2CDAT */
+                u8Ctrl = I2C_CTL_SI;                                      /* Clear SI */
+                break;
+            case 0x40u:                                                      /* Slave Address ACK */
+                u8Ctrl = I2C_CTL_SI;                                      /* Clear SI */
+                break;
+            case 0x48u:                                                      /* Slave Address NACK */
+                u8Ctrl = I2C_CTL_STO_SI;                                  /* Clear SI and send STOP */
+                u8Err = 1u;
+                break;
+            case 0x58u:
+                u8Rdata = (unsigned char) I2C_GET_DATA(i2c);                  /* Receive Data */
+                u8Ctrl = I2C_CTL_STO_SI;                                  /* Clear SI and send STOP */
+                u8Xfering = 0u;
+                break;
+            case 0x38u:                                                      /* Arbitration Lost */
+            default:                                                        /* Unknow status */
+                u8Ctrl = I2C_CTL_STO_SI;                                  /* Clear SI and send STOP */
+                u8Err = 1u;
+                break;
+        }
+        I2C_SET_CONTROL_REG(i2c, u8Ctrl);                                   /* Write controlbit to I2C_CTL register */
+    }
+    if(u8Err)
+    {
+        u8Rdata = 0u;                                                          /* If occurs error, return 0 */
+    }
+    return u8Rdata;                                                           /* Return read data */
+}
+
+/**
+  * @brief      Specify two bytes register address and read multi bytes from Slave
+  *
+  * @param[in]  *i2c            Point to I2C peripheral
+  * @param[in]  u8SlaveAddr     Access Slave address(7-bit)
+  * @param[in]  u16DataAddr     Specify a address (2 bytes) of data read from
+  * @param[out] au8Rdata[]         A data array to store data from Slave
+  * @param[in]  u32rLen         How many bytes need to read from Slave
+  *
+  * @return     A length of how many bytes have been received
+  *
+  * @details    The function is used for I2C Master specify two bytes address that multi data bytes read from Slave.
+  *
+  *
+  */
+uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t au8Rdata[], uint32_t u32rLen)
+{
+    uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u;
+    uint32_t u32rxLen = 0u;
+
+    I2C_START(i2c);                                                         /* Send START */
+    while(u8Xfering && (u8Err == 0u))
+    {
+        I2C_WAIT_READY(i2c) {}
+        switch(I2C_GET_STATUS(i2c))
+        {
+            case 0x08u:
+                I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | (uint8_t)0x00u));               /* Write SLA+W to Register I2CDAT */
+                u8Ctrl = I2C_CTL_SI;                                      /* Clear SI */
+                break;
+            case 0x18u:                                                      /* Slave Address ACK */
+                I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u));    /* Write Hi byte address of register */
+                break;
+            case 0x20u:                                                      /* Slave Address NACK */
+            case 0x30u:                                                      /* Master transmit data NACK */
+                u8Ctrl = I2C_CTL_STO_SI;                                  /* Clear SI and send STOP */
+                u8Err = 1u;
+                break;
+            case 0x28u:
+                if(u8Addr)
+                {
+                    I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu));       /* Write Lo byte address of register */
+                    u8Addr = 0u;
+                }
+                else
+                {
+                    u8Ctrl = I2C_CTL_STA_SI;                              /* Clear SI and send repeat START */
+                }
+                break;
+            case 0x10u:
+                I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | (uint8_t)0x01u));             /* Write SLA+R to Register I2CDAT */
+                u8Ctrl = I2C_CTL_SI;                                      /* Clear SI */
+                break;
+            case 0x40u:                                                      /* Slave Address ACK */
+                u8Ctrl = I2C_CTL_SI_AA;                                   /* Clear SI and set ACK */
+                break;
+            case 0x48u:                                                      /* Slave Address NACK */
+                u8Ctrl = I2C_CTL_STO_SI;                                  /* Clear SI and send STOP */
+                u8Err = 1u;
+                break;
+            case 0x50u:
+                au8Rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c);      /* Receive Data */
+                if(u32rxLen < (u32rLen - 1u))
+                {
+                    u8Ctrl = I2C_CTL_SI_AA;                               /* Clear SI and set ACK */
+                }
+                else
+                {
+                    u8Ctrl = I2C_CTL_SI;                                  /* Clear SI */
+                }
+                break;
+            case 0x58u:
+                au8Rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c);      /* Receive Data */
+                u8Ctrl = I2C_CTL_STO_SI;                                  /* Clear SI and send STOP */
+                u8Xfering = 0u;
+                break;
+            case 0x38u:                                                      /* Arbitration Lost */
+            default:                                                        /* Unknow status */
+                u8Ctrl = I2C_CTL_STO_SI;                                  /* Clear SI and send STOP */
+                u8Err = 1u;
+                break;
+        }
+        I2C_SET_CONTROL_REG(i2c, u8Ctrl);                                   /* Write controlbit to I2C_CTL register */
+    }
+    return u32rxLen;                                                        /* Return bytes length that have been received */
+}
+
+/**@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group I2C_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_i2s.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_i2s.c
new file mode 100644
index 0000000000..3aa4e4c8f4
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_i2s.c
@@ -0,0 +1,264 @@
+/**************************************************************************//**
+ * @file     i2s.c
+ * @version  V3.00
+ * @brief    M2354 series I2S driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+#include 
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup I2S_Driver I2S Driver
+  @{
+*/
+
+/** @addtogroup I2S_EXPORTED_FUNCTIONS I2S Exported Functions
+  @{
+*/
+
+static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s);
+
+/**
+  * @brief  This function is used to get I2S source clock frequency.
+  * @param[in]  i2s The base address of I2S module.
+  * @return I2S source clock frequency (Hz).
+  * @details Return the source clock frequency according to the setting of I2S0SEL (CLK_CLKSEL3[17:16]).
+  */
+static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s)
+{
+    (void)i2s;
+    uint32_t u32Freq, u32ClkSrcSel;
+
+    u32ClkSrcSel = CLK_GetModuleClockSource(I2S0_MODULE) << CLK_CLKSEL3_I2S0SEL_Pos;
+
+    switch(u32ClkSrcSel)
+    {
+        case CLK_CLKSEL3_I2S0SEL_HXT:
+            u32Freq = __HXT;
+            break;
+
+        case CLK_CLKSEL3_I2S0SEL_PLL:
+            u32Freq = CLK_GetPLLClockFreq();
+            break;
+
+        case CLK_CLKSEL3_I2S0SEL_HIRC:
+            u32Freq = __HIRC;
+            break;
+
+        case CLK_CLKSEL3_I2S0SEL_PCLK0:
+            u32Freq = CLK_GetPCLK0Freq();
+            break;
+
+        default:
+            u32Freq = CLK_GetPCLK0Freq();
+            break;
+    }
+
+    return u32Freq;
+}
+
+/**
+  * @brief  This function configures some parameters of I2S interface for general purpose use.
+  * @param[in] i2s The base address of I2S module.
+  * @param[in] u32MasterSlave I2S operation mode. Valid values are:
+  *                                     - \ref I2S_MODE_MASTER
+  *                                     - \ref I2S_MODE_SLAVE
+  * @param[in] u32SampleRate Sample rate
+  * @param[in] u32WordWidth Data length. Valid values are:
+  *                                     - \ref I2S_DATABIT_8
+  *                                     - \ref I2S_DATABIT_16
+  *                                     - \ref I2S_DATABIT_24
+  *                                     - \ref I2S_DATABIT_32
+  * @param[in] u32MonoData Set audio data to mono or not. Valid values are:
+  *                                     - \ref I2S_ENABLE_MONO
+  *                                     - \ref I2S_DISABLE_MONO
+  * @param[in] u32DataFormat Data format. This is also used to select I2S or PCM(TDM) function. Valid values are:
+  *                                     - \ref I2S_FORMAT_I2S
+  *                                     - \ref I2S_FORMAT_I2S_MSB
+  *                                     - \ref I2S_FORMAT_I2S_LSB
+  *                                     - \ref I2S_FORMAT_PCM
+  *                                     - \ref I2S_FORMAT_PCM_MSB
+  *                                     - \ref I2S_FORMAT_PCM_LSB
+  * @return Real sample rate.
+  * @details Set TX and RX FIFO threshold to middle value.
+  *          The sample rate may not be used from the parameter, it depends on system's clock settings,
+  *          but real sample rate used by system will be returned for reference.
+  * @note   I2S will be reset in initialization only for Secure.
+  */
+uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat)
+{
+    uint16_t u16Divider;
+    uint32_t u32BitRate, u32SrcClk;
+
+    if(!(__PC() & NS_OFFSET))
+    {
+        /* Reset I2S */
+        SYS->IPRST1 |= SYS_IPRST1_I2S0RST_Msk;
+        SYS->IPRST1 &= ~SYS_IPRST1_I2S0RST_Msk;
+    }
+
+    /* Configure I2S controller according to input parameters. */
+    i2s->CTL0 = u32MasterSlave | u32WordWidth | u32MonoData | u32DataFormat;
+    i2s->CTL1 = I2S_FIFO_TX_LEVEL_WORD_8 | I2S_FIFO_RX_LEVEL_WORD_8;
+
+    /* Get I2S source clock frequency */
+    u32SrcClk = I2S_GetSourceClockFreq(i2s);
+
+    /* Calculate bit clock rate */
+    u32BitRate = u32SampleRate * (((u32WordWidth >> 4UL) & 0x3UL) + 1UL) * 16UL;
+    u16Divider = (uint16_t)((((((u32SrcClk * 10UL) / u32BitRate) >> 1UL) + 5UL) / 10UL) - 1UL); /* Round to the nearest integer */
+    i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_BCLKDIV_Msk) | ((uint32_t)u16Divider << 8UL);
+
+    /* Calculate real sample rate */
+    u32BitRate = u32SrcClk / (((uint32_t)u16Divider + 1UL) * 2UL);
+    u32SampleRate = u32BitRate / ((((u32WordWidth >> 4UL) & 0x3UL) + 1UL) * 16UL);
+
+    /* Enable I2S controller */
+    i2s->CTL0 |= I2S_CTL0_I2SEN_Msk;
+
+    return u32SampleRate;
+}
+
+/**
+  * @brief  Disable I2S function.
+  * @param[in]  i2s The base address of I2S module.
+  * @return None
+  * @details Clear I2SEN (I2S_CTL0[0]) to disable I2S function.
+  */
+void I2S_Close(I2S_T *i2s)
+{
+    i2s->CTL0 &= ~I2S_CTL0_I2SEN_Msk;
+}
+
+/**
+  * @brief Enable interrupt function.
+  * @param[in] i2s The base address of I2S module.
+  * @param[in] u32Mask The combination of all related interrupt enable bits.
+  *            Each bit corresponds to a interrupt bit.
+  * @return None
+  * @details This function enables the interrupt according to the mask parameter.
+  */
+void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask)
+{
+    i2s->IEN |= u32Mask;
+}
+
+/**
+  * @brief Disable interrupt function.
+  * @param[in] i2s The base address of I2S module.
+  * @param[in] u32Mask The combination of all related interrupt enable bits.
+  *            Each bit corresponds to a interrupt bit.
+  * @return None
+  * @details This function disables the interrupt according to the mask parameter.
+  */
+void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask)
+{
+    i2s->IEN &= ~u32Mask;
+}
+
+/**
+  * @brief  Enable master clock (MCLK).
+  * @param[in] i2s The base address of I2S module.
+  * @param[in] u32BusClock The target MCLK clock.
+  * @return Actual MCLK clock
+  * @details Set the master clock rate according to u32BusClock parameter and enable master clock output.
+  *          The actual master clock rate may be different from the target master clock rate. The real master clock rate will be returned for reference.
+  */
+uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock)
+{
+    uint8_t u8Divider;
+    uint32_t u32SrcClk, u32Reg, u32Clock;
+
+    u32SrcClk = I2S_GetSourceClockFreq(i2s);
+    if(u32BusClock == u32SrcClk)
+    {
+        u8Divider = (uint8_t)0UL;
+    }
+    else
+    {
+        u8Divider = (uint8_t)(u32SrcClk / u32BusClock) >> 1UL;
+    }
+
+    i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_MCLKDIV_Msk) | u8Divider;
+
+    i2s->CTL0 |= I2S_CTL0_MCLKEN_Msk;
+
+    u32Reg = i2s->CLKDIV & I2S_CLKDIV_MCLKDIV_Msk;
+
+    if(u32Reg == 0UL)
+    {
+        u32Clock = u32SrcClk;
+    }
+    else
+    {
+        u32Clock = ((u32SrcClk >> 1UL) / u32Reg);
+    }
+
+    return u32Clock;
+}
+
+/**
+  * @brief  Disable master clock (MCLK).
+  * @param[in] i2s The base address of I2S module.
+  * @return None
+  * @details Disable master clock output.
+  */
+void I2S_DisableMCLK(I2S_T *i2s)
+{
+    i2s->CTL0 &= ~I2S_CTL0_MCLKEN_Msk;
+}
+
+/**
+  * @brief  Configure FIFO threshold setting.
+  * @param[in]  i2s The pointer of the specified I2S module.
+  * @param[in]  u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 15.
+  * @param[in]  u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 15.
+  * @return None
+  * @details Set TX FIFO threshold and RX FIFO threshold configurations.
+  */
+void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
+{
+    i2s->CTL1 = (i2s->CTL1 & ~(I2S_CTL1_TXTH_Msk | I2S_CTL1_RXTH_Msk)) |
+                (u32TxThreshold << I2S_CTL1_TXTH_Pos) |
+                (u32RxThreshold << I2S_CTL1_RXTH_Pos);
+}
+
+/**
+  * @brief  Configure PCM(TDM) function parameters, such as channel width, channel number and sync pulse width
+  * @param[in]  i2s The pointer of the specified I2S module.
+  * @param[in]  u32ChannelWidth Channel width. Valid values are:
+  *                                                             - \ref I2S_TDM_WIDTH_8BIT
+  *                                                             - \ref I2S_TDM_WIDTH_16BIT
+  *                                                             - \ref I2S_TDM_WIDTH_24BIT
+  *                                                             - \ref I2S_TDM_WIDTH_32BIT
+  * @param[in]  u32ChannelNum Channel number. Valid values are:
+  *                                                             - \ref I2S_TDM_2CH
+  *                                                             - \ref I2S_TDM_4CH
+  *                                                             - \ref I2S_TDM_6CH
+  *                                                             - \ref I2S_TDM_8CH
+  * @param[in]  u32SyncWidth Width for sync pulse. Valid values are:
+  *                                                             - \ref I2S_TDM_SYNC_ONE_BCLK
+  *                                                             - \ref I2S_TDM_SYNC_ONE_CHANNEL
+  * @return None
+  * @details Set TX FIFO threshold and RX FIFO threshold configurations.
+  */
+void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth)
+{
+    i2s->CTL0 = (i2s->CTL0 & ~(I2S_CTL0_TDMCHNUM_Msk | I2S_CTL0_CHWIDTH_Msk | I2S_CTL0_PCMSYNC_Msk)) |
+                (u32ChannelWidth << I2S_CTL0_CHWIDTH_Pos) |
+                (u32ChannelNum << I2S_CTL0_TDMCHNUM_Pos) |
+                (u32SyncWidth << I2S_CTL0_PCMSYNC_Pos);
+}
+
+/**@}*/ /* end of group I2S_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group I2S_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_keystore.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_keystore.c
new file mode 100644
index 0000000000..7238571be5
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_keystore.c
@@ -0,0 +1,561 @@
+/**************************************************************************//**
+ * @file     keystore.c
+ * @version  V3.00
+ * @brief    Key store driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup KS_Driver Key Store Driver
+  @{
+*/
+
+
+/** @addtogroup KS_EXPORTED_FUNCTIONS Key Store Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Initial key store
+  * @return     None
+  * @details    This function is used to initial the key store.
+  *             It is necessary to be called before using other APIs of Key Store.
+  */
+void KS_Open(void)
+{
+    if((KS->STS & KS_STS_INITDONE_Msk) == 0)
+    {
+        /* Waiting for busy */
+        while(KS->STS & KS_STS_BUSY_Msk) {}
+
+        /* Start Key Store Initial */
+        KS->CTL = KS_CTL_INIT_Msk | KS_CTL_START_Msk;
+
+        /* Waiting for initilization */
+        while((KS->STS & KS_STS_INITDONE_Msk) == 0);
+
+    }
+
+    /* Waiting busy to make sure KS is ready. */
+    while(KS->STS & KS_STS_BUSY_Msk);
+
+}
+
+
+/**
+  * @brief      Read key from key store
+  * @param[in]  eType       The memory type. It could be:
+                            \ref KS_SRAM
+                            \ref KS_FLASH
+                            \ref KS_OTP
+  * @param[in]  i32KeyIdx   The key index to read
+  * @param[out] au32Key     The buffer to store the key
+  * @param[in]  u32WordCnt  The word (32-bit) count of the key buffer size
+  * @retval     0           Successful
+  * @retval     -1          Fail
+  * @details    This function is used to read the key.
+  */
+
+int32_t KS_Read(KS_MEM_Type eType, int32_t i32KeyIdx, uint32_t au32Key[], uint32_t u32WordCnt)
+{
+    int32_t i32Cnt;
+    uint32_t u32Cont;
+    int32_t offset, i, cnt;
+
+    /* Just return when key store is in busy */
+    if(KS->STS & KS_STS_BUSY_Msk)
+        return -1;
+
+    /* Specify the key address */
+    KS->METADATA = ((uint32_t)eType << KS_METADATA_DST_Pos) | KS_TOMETAKEY(i32KeyIdx);
+
+    /* Clear error flag */
+    KS->STS = KS_STS_EIF_Msk;
+    offset = 0;
+    u32Cont = 0;
+    i32Cnt = (int32_t)u32WordCnt;
+    do
+    {
+        /* Clear Status */
+        KS->STS = KS_STS_EIF_Msk | KS_STS_IF_Msk;
+
+        /* Trigger to read the key */
+        KS->CTL = u32Cont | KS_OP_READ | KS_CTL_START_Msk | (KS->CTL & (KS_CTL_SILENT_Msk | KS_CTL_SCMB_Msk));
+        /* Waiting for key store processing */
+        while(KS->STS & KS_STS_BUSY_Msk);
+
+        /* Read the key to key buffer */
+        cnt = i32Cnt;
+        if(cnt > 8)
+            cnt = 8;
+        for(i = 0; i < cnt; i++)
+        {
+            au32Key[offset + i] = KS->KEY[i];
+            //printf("R[%d]:0x%08x\n", i, au32Key[offset+i]);
+        }
+
+        u32Cont = KS_CTL_CONT_Msk;
+        i32Cnt -= 8;
+        offset += 8;
+    }
+    while(i32Cnt > 0);
+
+    /* Check error flag */
+    if(KS->STS & KS_STS_EIF_Msk)
+        return -1;
+
+
+    return 0;
+}
+
+/**
+  * @brief      Get the word count of the specified Metadata key length
+  * @param[in]  u32Meta     The metadata define of the key length. It could be
+                                \ref KS_META_128
+                                \ref KS_META_163
+                                \ref KS_META_192
+                                \ref KS_META_224
+                                \ref KS_META_233
+                                \ref KS_META_255
+                                \ref KS_META_256
+                                \ref KS_META_283
+                                \ref KS_META_384
+                                \ref KS_META_409
+                                \ref KS_META_512
+                                \ref KS_META_521
+                                \ref KS_META_571
+                                \ref KS_META_1024
+                                \ref KS_META_2048
+                                \ref KS_META_4096
+  * @return     The word (32-bit) count of the key
+  * @details    This function is used to get word counts of the specified metadata key length.
+  *             It could be used to know how may words needs to allocate for the key.
+  */
+
+uint32_t KS_GetKeyWordCnt(uint32_t u32Meta)
+{
+    const uint16_t au8CntTbl[21] = { 4, 6, 6, 7, 8, 8, 8, 9, 12, 13, 16, 17, 18, 0, 0, 0, 32, 48, 64, 96, 128 };
+    return au8CntTbl[((u32Meta & KS_METADATA_SIZE_Msk) >> KS_METADATA_SIZE_Pos)];
+}
+
+/**
+  * @brief      Write key to key store
+* @param[in]    eType       The memory type. It could be:
+                            \ref KS_SRAM
+                            \ref KS_FLASH
+  * @param[in]  u32Meta     The metadata of the key. It could be the combine of
+                                \ref KS_META_AES
+                                \ref KS_META_HMAC
+                                \ref KS_META_RSA_EXP
+                                \ref KS_META_RSA_MID
+                                \ref KS_META_ECC
+                                \ref KS_META_CPU
+                                \ref KS_META_128
+                                \ref KS_META_163
+                                \ref KS_META_192
+                                \ref KS_META_224
+                                \ref KS_META_233
+                                \ref KS_META_255
+                                \ref KS_META_256
+                                \ref KS_META_283
+                                \ref KS_META_384
+                                \ref KS_META_409
+                                \ref KS_META_512
+                                \ref KS_META_521
+                                \ref KS_META_571
+                                \ref KS_META_1024
+                                \ref KS_META_2048
+                                \ref KS_META_4096
+                                \ref KS_META_BOOT
+                                \ref KS_META_READABLE
+                                \ref KS_META_PRIV
+                                \ref KS_META_NONPRIV
+                                \ref KS_META_SECURE
+                                \ref KS_META_NONSECUR
+
+  * @param[out] au32Key     The buffer to store the key
+  * @param[in]  u32WordCnt  The word (32-bit) count of the key buffer size
+  * @return     Index of the key. Failed when index < 0.
+  * @details    This function is used to write a key to key store.
+  */
+
+int32_t KS_Write(KS_MEM_Type eType, uint32_t u32Meta, uint32_t au32Key[])
+{
+    int32_t i32Cnt;
+    uint32_t u32Cont;
+    int32_t offset, i, cnt;
+
+
+    /* Just return when key store is in busy */
+    if(KS->STS & KS_STS_BUSY_Msk)
+        return -1;
+
+    /* Specify the key address */
+    KS->METADATA = (eType << KS_METADATA_DST_Pos) | u32Meta;
+
+    /* Get size index */
+    i32Cnt = (int32_t)KS_GetKeyWordCnt(u32Meta);
+
+    /* Invalid key length */
+    if(i32Cnt == 0)
+        return -1;
+
+    /* OTP only support maximum 256 bits */
+    if((eType == KS_OTP) && (i32Cnt > 8))
+        return -1;
+
+    /* Clear error flag */
+    KS->STS = KS_STS_EIF_Msk;
+    offset = 0;
+    u32Cont = 0;
+    do
+    {
+        /* Prepare the key to write */
+        cnt = i32Cnt;
+        if(cnt > 8)
+            cnt = 8;
+        for(i = 0; i < cnt; i++)
+        {
+            KS->KEY[i] = au32Key[offset + i];
+        }
+
+        /* Clear Status */
+        KS->STS = KS_STS_EIF_Msk | KS_STS_IF_Msk;
+
+        /* Write the key */
+        KS->CTL = u32Cont | KS_OP_WRITE | KS_CTL_START_Msk | (KS->CTL & (KS_CTL_SILENT_Msk | KS_CTL_SCMB_Msk));
+
+        u32Cont = KS_CTL_CONT_Msk;
+        i32Cnt -= 8;
+        offset += 8;
+
+        /* Waiting for key store processing */
+        while(KS->STS & KS_STS_BUSY_Msk);
+
+    }
+    while(i32Cnt > 0);
+
+    /* Check error flag */
+    if(KS->STS & KS_STS_EIF_Msk)
+    {
+        //printf("KS_Write. EIF!\n");
+        return -1;
+    }
+
+    return KS_TOKEYIDX(KS->METADATA);
+}
+
+/**
+  * @brief      Erase a key from key store
+  * @param[in]  i32KeyIdx   The key index to read
+  * @retval     0           Successful
+  * @retval     -1          Fail
+  * @details    This function is used to erase a key from SRAM of key store.
+   */
+int32_t KS_EraseKey(int32_t i32KeyIdx)
+{
+    /* Just return when key store is in busy */
+    if(KS->STS & KS_STS_BUSY_Msk)
+        return -1;
+
+    /* Clear error flag */
+    KS->STS = KS_STS_EIF_Msk;
+
+    /* Specify the key address */
+    KS->METADATA = (KS_SRAM << KS_METADATA_DST_Pos) | KS_TOMETAKEY(i32KeyIdx);
+
+    /* Clear Status */
+    KS->STS = KS_STS_EIF_Msk | KS_STS_IF_Msk;
+
+    /* Erase the key */
+    KS->CTL = KS_OP_ERASE | KS_CTL_START_Msk  | (KS->CTL & (KS_CTL_SILENT_Msk | KS_CTL_SCMB_Msk));
+
+    /* Waiting for processing */
+    while(KS->STS & KS_STS_BUSY_Msk);
+
+    /* Check error flag */
+    if(KS->STS & KS_STS_EIF_Msk)
+        return -1;
+
+    return 0;
+
+}
+
+
+/**
+  * @brief      Erase all keys from key store
+  * @param[in]  eType       The memory type. It could be:
+                            \ref KS_SRAM
+                            \ref KS_FLASH
+                            \ref KS_OTP
+  * @param[in]  i32KeyIdx   The key index to read
+  * @retval     0           Successful
+  * @retval     -1          Fail
+  * @details    This function is used to erase all keys in SRAM or Flash of key store.
+  */
+int32_t KS_EraseAll(KS_MEM_Type eType)
+{
+    /* Just return when key store is in busy */
+    if(KS->STS & KS_STS_BUSY_Msk)
+        return -1;
+
+    /* Clear error flag */
+    KS->STS = KS_STS_EIF_Msk;
+
+    /* Specify the key address */
+    KS->METADATA = (eType << KS_METADATA_DST_Pos);
+
+    /* Clear Status */
+    KS->STS = KS_STS_EIF_Msk | KS_STS_IF_Msk;
+
+    /* Erase the key */
+    KS->CTL = KS_OP_ERASE_ALL | KS_CTL_START_Msk  | (KS->CTL & (KS_CTL_SILENT_Msk | KS_CTL_SCMB_Msk));
+
+    /* Waiting for processing */
+    while(KS->STS & KS_STS_BUSY_Msk);
+
+    /* Check error flag */
+    if(KS->STS & KS_STS_EIF_Msk)
+        return -1;
+
+    return 0;
+
+}
+
+
+
+/**
+  * @brief      Revoke a key in key store
+  * @param[in]  eType       The memory type. It could be:
+                            \ref KS_SRAM
+                            \ref KS_FLASH
+                            \ref KS_OTP
+  * @param[in]  i32KeyIdx   The key index to read
+  * @retval     0           Successful
+  * @retval     -1          Fail
+  * @details    This function is used to revoke a key in key store.
+  */
+int32_t KS_RevokeKey(KS_MEM_Type eType, int32_t i32KeyIdx)
+{
+    /* Just return when key store is in busy */
+    if(KS->STS & KS_STS_BUSY_Msk)
+        return -1;
+
+    /* Clear error flag */
+    KS->STS = KS_STS_EIF_Msk;
+
+    /* Specify the key address */
+    KS->METADATA = (eType << KS_METADATA_DST_Pos) | KS_TOMETAKEY(i32KeyIdx);
+
+    /* Clear Status */
+    KS->STS = KS_STS_EIF_Msk | KS_STS_IF_Msk;
+
+    /* Erase the key */
+    KS->CTL = KS_OP_REVOKE | KS_CTL_START_Msk | (KS->CTL & (KS_CTL_SILENT_Msk | KS_CTL_SCMB_Msk));
+
+    /* Waiting for processing */
+    while(KS->STS & KS_STS_BUSY_Msk);
+
+    /* Check error flag */
+    if(KS->STS & KS_STS_EIF_Msk)
+        return -1;
+
+    return 0;
+
+}
+
+
+/**
+  * @brief      Get remain size of specified Key Store memory
+  * @param[in]  eType       The memory type. It could be:
+                            \ref KS_SRAM
+                            \ref KS_FLASH
+  * @retval     remain size of specified Key Store memory
+  * @details    This function is used to get remain size of Key Store.
+  */
+uint32_t KS_GetRemainSize(KS_MEM_Type mem)
+{
+    uint32_t u32Reg;
+    uint32_t u32SramRemain, u32FlashRemain;
+
+    u32Reg = KS->REMAIN;
+    //printf("KS Remain 0x%08x\n", u32Reg);
+    //printf("SRAM remain %lu bytes, Flash remain %lu bytes\n",(u32Reg&KS_REMAIN_RRMNG_Msk) >> KS_REMAIN_RRMNG_Pos, (u32Reg&KS_REMAIN_FRMNG_Msk) >> KS_REMAIN_FRMNG_Pos);
+    u32SramRemain = (u32Reg & KS_REMAIN_RRMNG_Msk) >> KS_REMAIN_RRMNG_Pos;
+    u32FlashRemain = (u32Reg & KS_REMAIN_FRMNG_Msk) >> KS_REMAIN_FRMNG_Pos;
+
+    if(mem == KS_SRAM)
+        return u32SramRemain;
+    else
+        return u32FlashRemain;
+}
+
+
+
+/**
+  * @brief      Get remain key count of specified Key Store memory
+  * @param[in]  eType       The memory type. It could be:
+                            \ref KS_SRAM
+                            \ref KS_FLASH
+  * @retval     Remain key count in the specified key store memory
+  * @details    This function is used to get remain key count in specified key store memory.
+  */
+uint32_t KS_GetRemainKeyCount(KS_MEM_Type mem)
+{
+    uint32_t u32Reg;
+    uint32_t u32SramRemain, u32FlashRemain;
+
+    u32Reg = KS->REMKCNT;
+    u32SramRemain = (u32Reg & KS_REMKCNT_RRMKCNT_Msk) >> KS_REMKCNT_RRMKCNT_Pos;
+    u32FlashRemain = (u32Reg & KS_REMKCNT_FRMKCNT_Msk) >> KS_REMKCNT_FRMKCNT_Pos;
+
+    if(mem == KS_SRAM)
+        return u32SramRemain;
+    else
+        return u32FlashRemain;
+}
+
+
+
+/**
+  * @brief      Write OTP key to key store
+  * @param[in]  i32KeyIdx   The OTP key index to store the key. It could be 0~7.
+                            OTP key index 0 is default for ROTPK.
+  * @param[in]  u32Meta     The metadata of the key. It could be the combine of
+                                \ref KS_META_AES
+                                \ref KS_META_HMAC
+                                \ref KS_META_RSA_EXP
+                                \ref KS_META_RSA_MID
+                                \ref KS_META_ECC
+                                \ref KS_META_CPU
+                                \ref KS_META_128
+                                \ref KS_META_163
+                                \ref KS_META_192
+                                \ref KS_META_224
+                                \ref KS_META_233
+                                \ref KS_META_255
+                                \ref KS_META_256
+                                \ref KS_META_BOOT
+                                \ref KS_META_READABLE
+                                \ref KS_META_PRIV
+                                \ref KS_META_NONPRIV
+                                \ref KS_META_SECURE
+                                \ref KS_META_NONSECUR
+
+  * @param[out] au32Key     The buffer to store the key
+  * @param[in]  u32WordCnt  The word (32-bit) count of the key buffer size
+  * @retval     0           Successful
+  * @retval     -1          Fail
+  * @details    This function is used to write a key to OTP key store.
+  */
+int32_t KS_WriteOTP(int32_t i32KeyIdx, uint32_t u32Meta, uint32_t au32Key[])
+{
+    const uint16_t au8CntTbl[7] = {4, 6, 6, 7, 8, 8, 8};
+    int32_t i32Cnt;
+    uint32_t u32Cont;
+    int32_t offset, i, cnt, sidx;
+
+
+    /* Just return when key store is in busy */
+    if(KS->STS & KS_STS_BUSY_Msk)
+        return -1;
+
+    /* Specify the key address */
+    KS->METADATA = ((uint32_t)KS_OTP << KS_METADATA_DST_Pos) | u32Meta | KS_TOMETAKEY(i32KeyIdx);
+
+    /* Get size index */
+    sidx = (u32Meta >> KS_METADATA_SIZE_Pos) & 0xful;
+
+    /* OTP only support maximum 256 bits */
+    if(sidx >= 7)
+        return -1;
+
+    i32Cnt = au8CntTbl[sidx];
+
+    /* Clear error flag */
+    KS->STS = KS_STS_EIF_Msk;
+    offset = 0;
+    u32Cont = 0;
+    do
+    {
+        /* Prepare the key to write */
+        cnt = i32Cnt;
+        if(cnt > 8)
+            cnt = 8;
+        for(i = 0; i < cnt; i++)
+        {
+            KS->KEY[i] = au32Key[offset + i];
+        }
+
+        /* Clear Status */
+        KS->STS = KS_STS_EIF_Msk | KS_STS_IF_Msk;
+
+        /* Write the key */
+        KS->CTL = u32Cont | KS_OP_WRITE | KS_CTL_START_Msk | (KS->CTL & (KS_CTL_SILENT_Msk | KS_CTL_SCMB_Msk));
+
+        u32Cont = KS_CTL_CONT_Msk;
+        i32Cnt -= 8;
+        offset += 8;
+
+        /* Waiting for key store processing */
+        while(KS->STS & KS_STS_BUSY_Msk);
+
+    }
+    while(i32Cnt > 0);
+
+    /* Check error flag */
+    if(KS->STS & KS_STS_EIF_Msk)
+    {
+        //printf("KS_WriteOTP. EIF!\n");
+        return -1;
+    }
+
+    return i32KeyIdx;
+}
+
+
+/**
+  * @brief      Trigger to inverse the date in KS_SRAM.
+  * @retval     1           The data in KS SRAM is inverted.
+  * @retval     0           The data in KS SRAM is non-inverted.
+  * @retval     -1          Fail to invert the date in KS SRAM.
+  * @details    This function is used to trigger anti-remanence procedure by inverse the data in SRAM.
+  *             This won't change the reading key.
+  */
+
+int32_t KS_ToggleSRAM(void)
+{
+    /* Just return when key store is in busy */
+    if(KS->STS & KS_STS_BUSY_Msk)
+        return -1;
+
+
+    /* Specify the key address */
+    KS->METADATA = ((uint32_t)KS_SRAM << KS_METADATA_DST_Pos);
+
+    /* Clear error flag */
+    KS->STS = KS_STS_EIF_Msk | KS_STS_IF_Msk;
+    /* Trigger to do anti-remanence procedure */
+    KS->CTL = KS_OP_REMAN | KS_CTL_START_Msk;
+
+    /* Waiting for key store processing */
+    while(KS->STS & KS_STS_BUSY_Msk);
+
+    /* Check error flag */
+    if(KS->STS & KS_STS_EIF_Msk)
+        return -1;
+
+    return ((KS->STS & KS_STS_RAMINV_Msk) > 0);
+}
+
+
+/**@}*/ /* end of group KS_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group KS_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_lcd.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_lcd.c
new file mode 100644
index 0000000000..cccb4df5a4
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_lcd.c
@@ -0,0 +1,338 @@
+/**************************************************************************//**
+ * @file     lcd.c
+ * @version  V3.00
+ * @brief    Liquid-Crystal Display(LCD) driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup LCD_Driver LCD Driver
+  @{
+*/
+
+
+/// @cond HIDDEN_SYMBOLS
+
+/** @addtogroup LCD_EXPORTED_VARIABLES LCD Exported Variables
+  @{
+*/
+/*---------------------------------------------------------------------------------------------------------*/
+/* Global file scope (static) variables                                                                    */
+/*---------------------------------------------------------------------------------------------------------*/
+static uint32_t g_LCDFrameRate;
+
+/**@}*/ /* end of group LCD_EXPORTED_VARIABLES */
+
+/// @endcond /* HIDDEN_SYMBOLS */
+
+
+/** @addtogroup LCD_EXPORTED_FUNCTIONS LCD Exported Functions
+  @{
+*/
+
+/**
+  * @brief      LCD Initialization routine
+  *
+  * @param[in]  pLCDCfg Specify the LCD property. It includes:
+  *                     u32SrcFreq: Clock source frequency of LCD controller.
+  *                     u32ComDuty: LCD COM duty ratio selection. Valid values are:
+  *                                 - \ref LCD_COM_DUTY_1_1
+  *                                 - \ref LCD_COM_DUTY_1_2
+  *                                 - \ref LCD_COM_DUTY_1_3
+  *                                 - \ref LCD_COM_DUTY_1_4
+  *                                 - \ref LCD_COM_DUTY_1_5
+  *                                 - \ref LCD_COM_DUTY_1_6
+  *                                 - \ref LCD_COM_DUTY_1_7
+  *                                 - \ref LCD_COM_DUTY_1_8
+  *                     u32BiasLevel: LCD Bias level selection. Valid values are:
+  *                                     - \ref LCD_BIAS_LV_1_2
+  *                                     - \ref LCD_BIAS_LV_1_3
+  *                                     - \ref LCD_BIAS_LV_1_4
+  *                     u32Framerate: Specify the target LCD operating frame rate (Hz).
+  *                     u32WaveformType: Specify the LCD waveform type. Valid values are:
+  *                                         - \ref LCD_WAVEFORM_TYPE_A_NORMAL
+  *                                         - \ref LCD_WAVEFORM_TYPE_B_NORMAL
+  *                                         - \ref LCD_WAVEFORM_TYPE_A_INVERSE
+  *                                         - \ref LCD_WAVEFORM_TYPE_B_INVERSE
+  *                     u32IntSrc: Interrupt source selection. Valid values are:
+  *                                 - \ref LCD_DISABLE_ALL_INT
+  *                                 - \ref LCD_FRAME_COUNTING_END_INT
+  *                                 - \ref LCD_FRAME_END_INT
+  *                                 - \ref LCD_CPTOUT_INT
+  *                                 - \ref LCD_ENABLE_ALL_INT
+  *                     u32DrivingMode: LCD operation driving mode selection. Valid values are:
+  *                                 - \ref LCD_LOW_DRIVING_AND_BUF_OFF
+  *                                 - \ref LCD_HIGH_DRIVING_AND_BUF_OFF
+  *                                 - \ref LCD_HIGH_DRIVING_AND_BUF_OFF_AND_PWR_SAVING
+  *                                 - \ref LCD_HIGH_DRIVING_AND_BUF_OFF_AND_PWR_SAVING
+  *                                 - \ref LCD_LOW_DRIVING_AND_BUF_ON_AND_PWR_SAVING
+  *                     u32VSrc: Voltage source selection. Valid values are:
+  *                                 - \ref LCD_VOLTAGE_SOURCE_VLCD
+  *                                 - \ref LCD_VOLTAGE_SOURCE_AVDD
+  *                                 - \ref LCD_VOLTAGE_SOURCE_CP
+  *
+  * @return     The real LCD operating frame rate. Or 0 means LCD_Open failed.
+  *
+  * @details    This function will configure the LCD properties for driving the LCD display well.
+  *             After that, user can perform \ref LCD_ENABLE_DISPLAY() to enable LCD controller for LCD display.
+  */
+uint32_t LCD_Open(S_LCD_CFG_T *pLCDCfg)
+{
+    uint32_t u32ComNum, u32FreqLCD, u32FreqDiv;
+
+    /* Display LCD display first */
+    LCD_DISABLE_DISPLAY();
+
+    /* Turn all segments off */
+    LCD_SetAllPixels(0);
+
+    /* Set com and bias */
+    LCD->PCTL = (pLCDCfg->u32ComDuty | pLCDCfg->u32BiasLevel);
+
+    /* Set waveform type */
+    LCD_WAVEFORM_TYPE(pLCDCfg->u32WaveformType);
+
+    /* Configure interrupt source */
+    LCD->INTEN = pLCDCfg->u32IntSrc;
+
+    /* Set driving mode */
+    LCD_DRIVING_MODE(pLCDCfg->u32DrivingMode);
+
+    /* Select voltage source */
+    LCD_VOLTAGE_SOURCE(pLCDCfg->u32VSrc);
+
+    /*
+        An example for specify frame rate.
+            If LCD source clock is 32768Hz, COM duty 4.
+            In type-A:
+                One frame rate 32Hz, frame end event rate 32Hz.
+                    32 = (1/4) * F_LCD * (1/2)
+                    F_LCD = 32 * 4 * 2 = 256 = (32768 / F_Div)
+                    F_Div = (32768 / F_LCD) = 128
+            In type-B:
+                Each even/odd frame rate 32Hz, frame end event rate 16Hz.
+                    32 = (1/4) * F_LCD
+                    F_LCD = 32 * 4 = (32768 / F_Div)
+                    F_Div = (32768 / F_LCD) = 256
+    */
+    u32ComNum = ((pLCDCfg->u32ComDuty & LCD_PCTL_DUTY_Msk) >> LCD_PCTL_DUTY_Pos) + 1;
+    if((pLCDCfg->u32WaveformType & LCD_PCTL_TYPE_Msk) == LCD_PCTL_TYPE_Msk)
+    {
+        /* In type-B */
+
+        /* Calculate LCD operation frequency */
+        u32FreqLCD = (pLCDCfg->u32Framerate * u32ComNum);
+
+        /* Calculate possible freq. divider */
+        u32FreqDiv = (pLCDCfg->u32SrcFreq  / u32FreqLCD);
+
+        if(u32FreqDiv > 1024)
+        {
+            /* Invalid frame rate */
+            g_LCDFrameRate = 0ul;
+        }
+        else
+        {
+            /* Set freq. divider */
+            LCD_SET_FREQDIV(u32FreqDiv);
+
+            /* Calculate target frame rate */
+            g_LCDFrameRate = pLCDCfg->u32SrcFreq / (u32ComNum * u32FreqDiv);
+        }
+    }
+    else
+    {
+        /* In type-A */
+
+        /* Calculate LCD operation frequency */
+        u32FreqLCD = (pLCDCfg->u32Framerate * u32ComNum) * 2;
+
+        /* Calculate possible freq. divider */
+        u32FreqDiv = (pLCDCfg->u32SrcFreq  / u32FreqLCD);
+
+        if(u32FreqDiv > 1024)
+        {
+            /* Invalid frame rate */
+            g_LCDFrameRate = 0ul;
+        }
+        else
+        {
+            /* Set freq. divider */
+            LCD_SET_FREQDIV(u32FreqDiv);
+
+            /* Calculate target frame rate */
+            g_LCDFrameRate = (pLCDCfg->u32SrcFreq  / (u32ComNum * u32FreqDiv)) / 2;
+        }
+    }
+
+    return g_LCDFrameRate;
+}
+
+/**
+  * @brief      Disable LCD Display
+  *
+  * @param[in]  None
+  *
+  * @return     None
+  *
+  * @details    This function is used to disable LCD display.
+  */
+void LCD_Close(void)
+{
+    LCD_DISABLE_DISPLAY();
+}
+
+/**
+  * @brief      Enables a Segment Display
+  *
+  * @param[in]  u32Com      Specify COM number. Valid values are from 0~7.
+  * @param[in]  u32Seg      Specify Segment number. Valid values are from 0~43.
+  * @param[in]  u32OnFlag   0 : Segment not display
+  *                         1 : Segment display
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable specified segment display on the LCD.
+  */
+void LCD_SetPixel(uint32_t u32Com, uint32_t u32Seg, uint32_t u32OnFlag)
+{
+    uint32_t seg_num = (u32Seg / 4);
+    uint32_t seg_shift = (8 * (u32Seg - (4 * seg_num)));
+
+    if(seg_num < 11)
+    {
+        if(u32OnFlag)
+        {
+            LCD->DATA[seg_num] |= ((uint32_t)(1 << u32Com) << seg_shift);
+        }
+        else
+        {
+            LCD->DATA[seg_num] &= (~((uint32_t)(1 << u32Com) << seg_shift));
+        }
+    }
+}
+
+/**
+  * @brief      Enable/Disable all LCD segments
+  *
+  * @param[in]  u32OnOff    0 : Disable all segments display
+  *                         1 : Enable all segments display
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable/disable all LCD segments display.
+  */
+void LCD_SetAllPixels(uint32_t u32OnOff)
+{
+    uint32_t i, u32Value;
+
+    if(u32OnOff == 1ul)
+    {
+        u32Value = 0xFFFFFFFFul;
+    }
+    else
+    {
+        u32Value = 0x00000000ul;
+    }
+
+    for(i = 0; i < 11; i++)
+        LCD->DATA[i] = u32Value;
+}
+
+/**
+  * @brief      Enable LCD Blinking
+  *
+  * @param[in]  u32ms       Blinking period time(unit: ms)
+  *
+  * @return     Real blinking period time(ms)
+  *
+  * @details    This function is used to enable blink display with specified period.
+  */
+uint32_t LCD_EnableBlink(uint32_t u32ms)
+{
+    uint32_t u32OneCountPeriod, u32TargetCounts;
+
+    if((LCD->PCTL & LCD_PCTL_TYPE_Msk) == LCD_PCTL_TYPE_Msk)
+    {
+        /* In type-B */
+        u32OneCountPeriod = (1000 * 2) / g_LCDFrameRate; // ms
+    }
+    else
+    {
+        /* In type-A */
+        u32OneCountPeriod = 1000 / g_LCDFrameRate; // ms
+    }
+
+    u32TargetCounts = (u32ms / u32OneCountPeriod);
+    if(u32TargetCounts == 0)
+        u32TargetCounts = 1;
+    if(u32TargetCounts > 1024)
+        u32TargetCounts = 1024;
+
+    LCD_SET_FRAME_COUNTING_VALUE(u32TargetCounts);
+
+    /* Enable blink display */
+    LCD_BLINKING_ON();
+
+    return (u32OneCountPeriod * u32TargetCounts);
+}
+
+/**
+  * @brief      Disable LCD Blinking
+  *
+  * @param[in]  None
+  *
+  * @return     None
+  *
+  * @details    This function is used to disable LCD blink display.
+  */
+void LCD_DisableBlink(void)
+{
+    /* Disable blink display */
+    LCD_BLINKING_OFF();
+}
+
+/**
+  * @brief      Enable LCD Interrupt
+  *
+  * @param[in]  IntSrc      Interrupt Source. It could be a combination of
+  *                             \ref LCD_FRAME_COUNTING_END_INT, \ref LCD_FRAME_END_INT and \ref LCD_CPTOUT_INT.
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable the specific LCD interrupt.
+  */
+void LCD_EnableInt(uint32_t u32IntSrc)
+{
+    LCD->INTEN |= (u32IntSrc);
+}
+
+/**
+  * @brief      Disable LCD Interrupt
+  *
+  * @param[in]  IntSrc      Interrupt Source. It could be a combination of
+  *                             \ref LCD_FRAME_COUNTING_END_INT, \ref LCD_FRAME_END_INT and \ref LCD_CPTOUT_INT.
+  *
+  * @return     None
+  *
+  * @details    This function is used to disable the specific LCD interrupt.
+  */
+void LCD_DisableInt(uint32_t u32IntSrc)
+{
+    LCD->INTEN &= ~(u32IntSrc);
+}
+
+
+/**@}*/ /* end of group LCD_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group LCD_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_pdma.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_pdma.c
new file mode 100644
index 0000000000..96c754fae4
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_pdma.c
@@ -0,0 +1,466 @@
+/**************************************************************************//**
+ * @file     pdma.c
+ * @version  V3.00
+ * @brief    M2354 series PDMA driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+
+
+static uint8_t au8ChSelect[PDMA_CH_MAX];
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup PDMA_Driver PDMA Driver
+  @{
+*/
+
+
+/** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions
+  @{
+*/
+
+/**
+ * @brief       PDMA Open
+ *
+ * @param[in]   pdma            The pointer of the specified PDMA module
+ * @param[in]   u32Mask         Channel enable bits.
+ *
+ * @return      None
+ *
+ * @details     This function enable the PDMA channels.
+ */
+void PDMA_Open(PDMA_T *pdma, uint32_t u32Mask)
+{
+    uint32_t i;
+
+    for(i = 0UL; i < (int)PDMA_CH_MAX; i++)
+    {
+        if((1 << i) & u32Mask)
+        {
+            (pdma)->DSCT[i].CTL = 0UL;
+            au8ChSelect[i] = (uint8_t)PDMA_MEM;
+        }
+    }
+
+    (pdma)->CHCTL |= u32Mask;
+}
+
+/**
+ * @brief       PDMA Close
+ *
+ * @param[in]   pdma            The pointer of the specified PDMA module
+ *
+ * @return      None
+ *
+ * @details     This function disable all PDMA channels.
+ */
+void PDMA_Close(PDMA_T *pdma)
+{
+    (pdma)->CHCTL = 0UL;
+}
+
+/**
+ * @brief       Set PDMA Transfer Count
+ *
+ * @param[in]   pdma            The pointer of the specified PDMA module
+ * @param[in]   u32Ch           The selected channel
+ * @param[in]   u32Width        Data width. Valid values are
+ *                - \ref PDMA_WIDTH_8
+ *                - \ref PDMA_WIDTH_16
+ *                - \ref PDMA_WIDTH_32
+ * @param[in]   u32TransCount   Transfer count
+ *
+ * @return      None
+ *
+ * @details     This function set the selected channel data width and transfer count.
+ */
+void PDMA_SetTransferCnt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)
+{
+    (pdma)->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXCNT_Msk | PDMA_DSCT_CTL_TXWIDTH_Msk);
+    (pdma)->DSCT[u32Ch].CTL |= (u32Width | ((u32TransCount - 1UL) << PDMA_DSCT_CTL_TXCNT_Pos));
+}
+
+/**
+ * @brief       Set PDMA Stride Mode
+ *
+ * @param[in]   pdma            The pointer of the specified PDMA module
+ * @param[in]   u32Ch           The selected channel
+ * @param[in]   u32DestLen      Destination stride count
+ * @param[in]   u32SrcLen       Source stride count
+ * @param[in]   u32TransCount   Transfer count
+ *
+ * @return      None
+ *
+ * @details     This function set the selected stride mode.
+ */
+void PDMA_SetStride(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount)
+{
+    (pdma)->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_STRIDEEN_Msk;
+    (pdma)->STRIDE[u32Ch].ASOCR = (u32DestLen << 16) | u32SrcLen;
+    (pdma)->STRIDE[u32Ch].STCR = u32TransCount;
+}
+
+/**
+ * @brief       Set PDMA Repeat
+  *
+ * @param[in]   pdma                The pointer of the specified PDMA module
+ * @param[in]   u32Ch               The selected channel
+ * @param[in]   u32DestInterval     Destination address interval count
+ * @param[in]   u32SrcInterval      Source address interval count
+ * @param[in]   u32RepeatCount      Repeat count
+ *
+ * @return      None
+ *
+ * @details     This function set the selected repeat.
+ */
+void PDMA_SetRepeat(PDMA_T * pdma, uint32_t u32Ch, uint32_t u32DestInterval, uint32_t u32SrcInterval, uint32_t u32RepeatCount)
+{
+    pdma->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_STRIDEEN_Msk;
+    pdma->REPEAT[u32Ch].AICTL = ((u32DestInterval) << 16) | (u32SrcInterval);
+    pdma->REPEAT[u32Ch].RCNT = u32RepeatCount;
+}
+
+/**
+ * @brief       Set PDMA Transfer Address
+ *
+ * @param[in]   pdma            The pointer of the specified PDMA module
+ * @param[in]   u32Ch           The selected channel
+ * @param[in]   u32SrcAddr      Source address
+ * @param[in]   u32SrcCtrl      Source control attribute. Valid values are
+ *                - \ref PDMA_SAR_INC
+ *                - \ref PDMA_SAR_FIX
+ * @param[in]   u32DstAddr      destination address
+ * @param[in]   u32DstCtrl      destination control attribute. Valid values are
+ *                - \ref PDMA_DAR_INC
+ *                - \ref PDMA_DAR_FIX
+ *
+ * @return      None
+ *
+ * @details     This function set the selected channel source/destination address and attribute.
+ */
+void PDMA_SetTransferAddr(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
+{
+    (pdma)->DSCT[u32Ch].SA = u32SrcAddr;
+    (pdma)->DSCT[u32Ch].DA = u32DstAddr;
+    (pdma)->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_SAINC_Msk | PDMA_DSCT_CTL_DAINC_Msk);
+    (pdma)->DSCT[u32Ch].CTL |= (u32SrcCtrl | u32DstCtrl);
+}
+
+/**
+ * @brief       Set PDMA Transfer Mode
+ *
+ * @param[in]   pdma            The pointer of the specified PDMA module
+ * @param[in]   u32Ch           The selected channel
+ * @param[in]   u32Peripheral   The selected peripheral. Valid values are
+ *                - \ref PDMA_MEM
+ *                - \ref PDMA_USB_TX
+ *                - \ref PDMA_USB_RX
+ *                - \ref PDMA_UART0_TX
+ *                - \ref PDMA_UART0_RX
+ *                - \ref PDMA_UART1_TX
+ *                - \ref PDMA_UART1_RX
+ *                - \ref PDMA_UART2_TX
+ *                - \ref PDMA_UART2_RX
+ *                - \ref PDMA_UART3_TX
+ *                - \ref PDMA_UART3_RX
+ *                - \ref PDMA_UART4_TX
+ *                - \ref PDMA_UART4_RX
+ *                - \ref PDMA_UART5_TX
+ *                - \ref PDMA_UART5_RX
+ *                - \ref PDMA_USCI0_TX
+ *                - \ref PDMA_USCI0_RX
+ *                - \ref PDMA_USCI1_TX
+ *                - \ref PDMA_USCI1_RX
+ *                - \ref PDMA_QSPI0_TX
+ *                - \ref PDMA_QSPI0_RX
+ *                - \ref PDMA_SPI0_TX
+ *                - \ref PDMA_SPI0_RX
+ *                - \ref PDMA_SPI1_TX
+ *                - \ref PDMA_SPI1_RX
+ *                - \ref PDMA_SPI2_TX
+ *                - \ref PDMA_SPI2_RX
+ *                - \ref PDMA_SPI3_TX
+ *                - \ref PDMA_SPI3_RX
+ *                - \ref PDMA_EPWM0_P1_RX
+ *                - \ref PDMA_EPWM0_P2_RX
+ *                - \ref PDMA_EPWM0_P3_RX
+ *                - \ref PDMA_EPWM1_P1_RX
+ *                - \ref PDMA_EPWM1_P2_RX
+ *                - \ref PDMA_EPWM1_P3_RX
+ *                - \ref PDMA_I2C0_TX
+ *                - \ref PDMA_I2C0_RX
+ *                - \ref PDMA_I2C1_TX
+ *                - \ref PDMA_I2C1_RX
+ *                - \ref PDMA_I2C2_TX
+ *                - \ref PDMA_I2C2_RX
+ *                - \ref PDMA_I2S0_TX
+ *                - \ref PDMA_I2S0_RX
+ *                - \ref PDMA_TMR0
+ *                - \ref PDMA_TMR1
+ *                - \ref PDMA_TMR2
+ *                - \ref PDMA_TMR3
+ *                - \ref PDMA_ADC_RX
+ *                - \ref PDMA_DAC0_TX
+ *                - \ref PDMA_DAC1_TX
+ *                - \ref PDMA_EPWM0_CH0_TX
+ *                - \ref PDMA_EPWM0_CH1_TX
+ *                - \ref PDMA_EPWM0_CH2_TX
+ *                - \ref PDMA_EPWM0_CH3_TX
+ *                - \ref PDMA_EPWM0_CH4_TX
+ *                - \ref PDMA_EPWM0_CH5_TX
+ *                - \ref PDMA_EPWM1_CH0_TX
+ *                - \ref PDMA_EPWM1_CH1_TX
+ *                - \ref PDMA_EPWM1_CH2_TX
+ *                - \ref PDMA_EPWM1_CH3_TX
+ *                - \ref PDMA_EPWM1_CH4_TX
+ *                - \ref PDMA_EPWM1_CH5_TX
+ * @param[in]   u32ScatterEn    Scatter-gather mode enable
+ * @param[in]   u32DescAddr     Scatter-gather descriptor address
+ *
+ * @return      None
+ *
+ * @details     This function set the selected channel transfer mode. Include peripheral setting.
+ */
+void PDMA_SetTransferMode(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
+{
+    au8ChSelect[u32Ch] = (uint8_t)u32Peripheral;
+    switch(u32Ch)
+    {
+        case 0UL:
+            (pdma)->REQSEL0_3 = ((pdma)->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC0_Msk) | u32Peripheral;
+            break;
+        case 1UL:
+            (pdma)->REQSEL0_3 = ((pdma)->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC1_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC1_Pos);
+            break;
+        case 2UL:
+            (pdma)->REQSEL0_3 = ((pdma)->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC2_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC2_Pos);
+            break;
+        case 3UL:
+            (pdma)->REQSEL0_3 = ((pdma)->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC3_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC3_Pos);
+            break;
+        case 4UL:
+            (pdma)->REQSEL4_7 = ((pdma)->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC4_Msk) | u32Peripheral;
+            break;
+        case 5UL:
+            (pdma)->REQSEL4_7 = ((pdma)->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC5_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC5_Pos);
+            break;
+        case 6UL:
+            (pdma)->REQSEL4_7 = ((pdma)->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC6_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC6_Pos);
+            break;
+        case 7UL:
+            (pdma)->REQSEL4_7 = ((pdma)->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC7_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC7_Pos);
+            break;
+        default:
+            break;
+    }
+
+    if(u32ScatterEn)
+    {
+        (pdma)->DSCT[u32Ch].CTL = ((pdma)->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER;
+        (pdma)->DSCT[u32Ch].NEXT = u32DescAddr - ((pdma)->SCATBA);
+    }
+    else
+    {
+        (pdma)->DSCT[u32Ch].CTL = ((pdma)->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_BASIC;
+    }
+}
+
+/**
+ * @brief       Set PDMA Burst Type and Size
+ *
+ * @param[in]   pdma            The pointer of the specified PDMA module
+ * @param[in]   u32Ch           The selected channel
+ * @param[in]   u32BurstType    Burst mode or single mode. Valid values are
+ *                - \ref PDMA_REQ_SINGLE
+ *                - \ref PDMA_REQ_BURST
+ * @param[in]   u32BurstSize    Set the size of burst mode. Valid values are
+ *                - \ref PDMA_BURST_128
+ *                - \ref PDMA_BURST_64
+ *                - \ref PDMA_BURST_32
+ *                - \ref PDMA_BURST_16
+ *                - \ref PDMA_BURST_8
+ *                - \ref PDMA_BURST_4
+ *                - \ref PDMA_BURST_2
+ *                - \ref PDMA_BURST_1
+ *
+ * @return      None
+ *
+ * @details     This function set the selected channel burst type and size.
+ */
+void PDMA_SetBurstType(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize)
+{
+    (pdma)->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXTYPE_Msk | PDMA_DSCT_CTL_BURSIZE_Msk);
+    (pdma)->DSCT[u32Ch].CTL |= (u32BurstType | u32BurstSize);
+}
+
+/**
+ * @brief       Enable timeout function
+ *
+ * @param[in]   pdma            The pointer of the specified PDMA module
+ * @param[in]   u32Mask         Channel enable bits.
+ *
+ * @return      None
+ *
+ * @details     This function enable timeout function of the selected channel(s).
+ * @note        This function is only supported in channel 0 and channel 1.
+ */
+void PDMA_EnableTimeout(PDMA_T *pdma, uint32_t u32Mask)
+{
+    (pdma)->TOUTEN |= u32Mask;
+}
+
+/**
+ * @brief       Disable timeout function
+ *
+ * @param[in]   pdma            The pointer of the specified PDMA module
+ * @param[in]   u32Mask         Channel enable bits.
+ *
+ * @return      None
+ *
+ * @details     This function disable timeout function of the selected channel(s).
+ * @note        This function is only supported in channel 0 and channel 1.
+ */
+void PDMA_DisableTimeout(PDMA_T *pdma, uint32_t u32Mask)
+{
+    (pdma)->TOUTEN &= ~u32Mask;
+}
+
+/**
+ * @brief       Set PDMA Timeout Count
+ *
+ * @param[in]   pdma            The pointer of the specified PDMA module
+ * @param[in]   u32Ch           The selected channel
+ * @param[in]   u32OnOff        Enable/disable timeout function
+ * @param[in]   u32TimeOutCnt   Timeout count
+ *
+ * @return      None
+ *
+ * @details     This function set the timeout count.
+ * @note        This function is only supported in channel 0 and channel 1.
+ */
+void PDMA_SetTimeOut(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
+{
+    switch(u32Ch)
+    {
+        case 0UL:
+            (pdma)->TOC0_1 = ((pdma)->TOC0_1 & ~PDMA_TOC0_1_TOC0_Msk) | u32TimeOutCnt;
+            break;
+        case 1UL:
+            (pdma)->TOC0_1 = ((pdma)->TOC0_1 & ~PDMA_TOC0_1_TOC1_Msk) | (u32TimeOutCnt << PDMA_TOC0_1_TOC1_Pos);
+            break;
+
+        default:
+            break;
+    }
+    if(u32OnOff)
+    {
+        (pdma)->TOUTEN |= (1UL << u32Ch);
+    }
+    else
+    {
+        (pdma)->TOUTEN &= ~(1UL << u32Ch);
+    }
+}
+
+/**
+ * @brief       Trigger PDMA
+ *
+ * @param[in]   pdma            The pointer of the specified PDMA module
+ * @param[in]   u32Ch           The selected channel
+ *
+ * @return      None
+ *
+ * @details     This function trigger the selected channel.
+ */
+void PDMA_Trigger(PDMA_T *pdma, uint32_t u32Ch)
+{
+    if(au8ChSelect[u32Ch] == PDMA_MEM)
+    {
+        (pdma)->SWREQ = (1UL << u32Ch);
+    }
+}
+
+/**
+ * @brief       Enable Interrupt
+ *
+ * @param[in]   pdma            The pointer of the specified PDMA module
+ * @param[in]   u32Ch           The selected channel
+ * @param[in]   u32Mask         The Interrupt Type. Valid values are
+ *                - \ref PDMA_INT_TRANS_DONE
+ *                - \ref PDMA_INT_TABLE
+ *                - \ref PDMA_INT_TIMEOUT
+ *                - \ref PDMA_INT_ALIGN
+ *
+ * @return      None
+ *
+ * @details     This function enable the selected channel interrupt.
+ * @note        PDMA_INT_TIMEOUT is only supported in channel 0 and channel 1.
+ */
+void PDMA_EnableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask)
+{
+    switch(u32Mask)
+    {
+        case PDMA_INT_TRANS_DONE:
+        case PDMA_INT_ALIGN:
+            (pdma)->INTEN |= (1UL << u32Ch);
+            break;
+        case PDMA_INT_TABLE:
+            (pdma)->DSCT[u32Ch].CTL &= ~PDMA_DSCT_CTL_TBINTDIS_Msk;
+            break;
+        case PDMA_INT_TIMEOUT:
+            (pdma)->TOUTIEN |= (1UL << u32Ch);
+            break;
+
+        default:
+            break;
+    }
+}
+
+/**
+ * @brief       Disable Interrupt
+ *
+ * @param[in]   pdma            The pointer of the specified PDMA module
+ * @param[in]   u32Ch           The selected channel
+ * @param[in]   u32Mask         The Interrupt Type. Valid values are
+ *                - \ref PDMA_INT_TRANS_DONE
+ *                - \ref PDMA_INT_TABLE
+ *                - \ref PDMA_INT_TIMEOUT
+ *                - \ref PDMA_INT_ALIGN
+ *
+ * @return      None
+ *
+ * @details     This function disable the selected channel interrupt.
+ * @note        PDMA_INT_TIMEOUT is only supported in channel 0 and channel 1.
+ * @note        The transfer done interrupt is disabled when table empty interrupt is disabled(PDMA_INT_TEMPTY).
+ */
+void PDMA_DisableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask)
+{
+    switch(u32Mask)
+    {
+        case PDMA_INT_TRANS_DONE:
+        case PDMA_INT_ALIGN:
+            (pdma)->INTEN &= ~(1UL << u32Ch);
+            break;
+        case PDMA_INT_TABLE:
+            (pdma)->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_TBINTDIS_Msk;
+            break;
+        case PDMA_INT_TIMEOUT:
+            (pdma)->TOUTIEN &= ~(1UL << u32Ch);
+            break;
+
+        default:
+            break;
+    }
+}
+
+/**@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group PDMA_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_qei.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_qei.c
new file mode 100644
index 0000000000..cb4f4ecd44
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_qei.c
@@ -0,0 +1,145 @@
+/**************************************************************************//**
+ * @file     qei.c
+ * @version  V3.00
+ * $Revision: 2 $
+ * $Date: 17/09/20 9:33a $
+ * @brief    Quadrature Encoder Interface (QEI) driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup QEI_Driver QEI Driver
+  @{
+*/
+
+/** @addtogroup QEI_EXPORTED_FUNCTIONS QEI Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Close QEI function
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @return     None
+  * @details    This function reset QEI configuration and stop QEI counting.
+  */
+void QEI_Close(QEI_T* qei)
+{
+    /* Reset QEI configuration */
+    qei->CTL = 0UL;
+}
+
+/**
+  * @brief      Disable QEI interrupt
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @param[in]  u32IntSel   Interrupt type selection.
+  *                         - \ref QEI_CTL_DIRIEN_Msk   : Direction change interrupt
+  *                         - \ref QEI_CTL_OVUNIEN_Msk  : Counter overflow or underflow interrupt
+  *                         - \ref QEI_CTL_CMPIEN_Msk   : Compare-match interrupt
+  *                         - \ref QEI_CTL_IDXIEN_Msk   : Index detected interrupt
+  * @return     None
+  * @details    This function disable QEI specified interrupt.
+  */
+void QEI_DisableInt(QEI_T* qei, uint32_t u32IntSel)
+{
+    /* Disable QEI specified interrupt */
+    QEI_DISABLE_INT(qei, u32IntSel);
+
+    /* Disable NVIC QEI IRQ */
+    if((qei == QEI0) || (qei == QEI0_NS))
+    {
+        NVIC_DisableIRQ(QEI0_IRQn);
+    }
+    else
+    {
+        NVIC_DisableIRQ(QEI1_IRQn);
+    }
+}
+
+/**
+  * @brief      Enable QEI interrupt
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @param[in]  u32IntSel   Interrupt type selection.
+  *                         - \ref QEI_CTL_DIRIEN_Msk   : Direction change interrupt
+  *                         - \ref QEI_CTL_OVUNIEN_Msk  : Counter overflow or underflow interrupt
+  *                         - \ref QEI_CTL_CMPIEN_Msk   : Compare-match interrupt
+  *                         - \ref QEI_CTL_IDXIEN_Msk   : Index detected interrupt
+  * @return     None
+  * @details    This function enable QEI specified interrupt.
+  */
+void QEI_EnableInt(QEI_T* qei, uint32_t u32IntSel)
+{
+    /* Enable QEI specified interrupt */
+    QEI_ENABLE_INT(qei, u32IntSel);
+
+    /* Enable NVIC QEI IRQ */
+    if((qei == QEI0) || (qei == QEI0_NS))
+    {
+        NVIC_EnableIRQ(QEI0_IRQn);
+    }
+    else
+    {
+        NVIC_EnableIRQ(QEI1_IRQn);
+    }
+}
+
+/**
+  * @brief      Open QEI in specified mode and enable input
+  * @param[in]  qei         The pointer of the specified QEI module.
+  * @param[in]  u32Mode     QEI counting mode.
+  *                         - \ref QEI_CTL_X4_FREE_COUNTING_MODE
+  *                         - \ref QEI_CTL_X2_FREE_COUNTING_MODE
+  *                         - \ref QEI_CTL_X4_COMPARE_COUNTING_MODE
+  *                         - \ref QEI_CTL_X2_COMPARE_COUNTING_MODE
+  * @param[in]  u32Value    The counter maximum value in compare-counting mode.
+  * @return     None
+  * @details    This function set QEI in specified mode and enable input.
+  */
+void QEI_Open(QEI_T* qei, uint32_t u32Mode, uint32_t u32Value)
+{
+    /* Set QEI function configuration */
+    /* Set QEI counting mode */
+    /* Enable IDX, QEA and QEB input to QEI controller */
+    qei->CTL = (qei->CTL & (~QEI_CTL_MODE_Msk)) | ((u32Mode) | QEI_CTL_CHAEN_Msk | QEI_CTL_CHBEN_Msk | QEI_CTL_IDXEN_Msk);
+
+    /* Set QEI maximum count value in in compare-counting mode */
+    qei->CNTMAX = u32Value;
+}
+
+/**
+  * @brief      Start QEI function
+  * @param[in]  qei     The pointer of the specified QEI module.
+  * @return     None
+  * @details    This function enable QEI function and start QEI counting.
+  */
+void QEI_Start(QEI_T* qei)
+{
+    /* Enable QEI controller function */
+    qei->CTL |= QEI_CTL_QEIEN_Msk;
+}
+
+/**
+  * @brief      Stop QEI function
+  * @param[in]  qei     The pointer of the specified QEI module.
+  * @return     None
+  * @details    This function disable QEI function and stop QEI counting.
+  */
+void QEI_Stop(QEI_T* qei)
+{
+    /* Disable QEI controller function */
+    qei->CTL &= (~QEI_CTL_QEIEN_Msk);
+}
+
+
+/**@}*/ /* end of group QEI_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group QEI_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_qspi.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_qspi.c
new file mode 100644
index 0000000000..5e366d5019
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_qspi.c
@@ -0,0 +1,857 @@
+/**************************************************************************//**
+ * @file     qspi.c
+ * @version  V3.00
+ * @brief    M2354 series QSPI driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup QSPI_Driver QSPI Driver
+  @{
+*/
+
+
+/** @addtogroup QSPI_EXPORTED_FUNCTIONS QSPI Exported Functions
+  @{
+*/
+
+/**
+  * @brief  This function make QSPI module be ready to transfer.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @param[in]  u32MasterSlave Decides the QSPI module is operating in master mode or in slave mode. (QSPI_SLAVE, QSPI_MASTER)
+  * @param[in]  u32QSPIMode Decides the transfer timing. (QSPI_MODE_0, QSPI_MODE_1, QSPI_MODE_2, QSPI_MODE_3)
+  * @param[in]  u32DataWidth Decides the data width of a QSPI transaction.
+  * @param[in]  u32BusClock The expected frequency of QSPI bus clock in Hz.
+  * @return Actual frequency of QSPI peripheral clock.
+  * @details By default, the QSPI transfer sequence is MSB first, the slave selection signal is active low and the automatic
+  *          slave selection function is disabled.
+  *          In Slave mode, the u32BusClock shall be NULL and the QSPI clock divider setting will be 0.
+  *          The actual clock rate may be different from the target QSPI clock rate.
+  *          For example, if the QSPI source clock rate is 12 MHz and the target QSPI bus clock rate is 7 MHz, the
+  *          actual QSPI clock rate will be 6MHz.
+  * @note   If u32BusClock = 0, DIVIDER setting will be set to the maximum value.
+  * @note   If u32BusClock >= system clock frequency for Secure, QSPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0.
+  * @note   If u32BusClock >= system clock frequency for Non-Secure, this function does not do anything to avoid the situation that the frequency of
+  *         QSPI bus clock cannot be faster than the system clock rate. User should set up carefully.
+  * @note   If u32BusClock >= QSPI peripheral clock source, DIVIDER will be set to 0.
+  * @note   In slave mode for Secure, the QSPI peripheral clock rate will equal to APB clock rate.
+  * @note   In slave mode for Non-Secure, the QSPI peripheral clock rate will equal to the clock rate set in secure mode.
+  */
+uint32_t QSPI_Open(QSPI_T *qspi,
+                   uint32_t u32MasterSlave,
+                   uint32_t u32QSPIMode,
+                   uint32_t u32DataWidth,
+                   uint32_t u32BusClock)
+{
+    uint32_t u32ClkSrc = 0UL, u32Div, u32HCLKFreq, u32PCLK0Freq, u32RetValue = 0UL;
+
+    if(u32DataWidth == 32UL)
+    {
+        u32DataWidth = 0UL;
+    }
+
+    /* Get system clock frequency */
+    u32HCLKFreq = CLK_GetHCLKFreq();
+    /* Get APB0 clock frequency */
+    u32PCLK0Freq = CLK_GetPCLK0Freq();
+
+    if(u32MasterSlave == QSPI_MASTER)
+    {
+        /* Default setting: slave selection signal is active low; disable automatic slave selection function. */
+        qspi->SSCTL = QSPI_SS_ACTIVE_LOW;
+
+        /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
+        qspi->CTL = u32MasterSlave | (u32DataWidth << QSPI_CTL_DWIDTH_Pos) | (u32QSPIMode) | QSPI_CTL_SPIEN_Msk;
+
+        if(u32BusClock >= u32HCLKFreq)
+        {
+            if(!(__PC() & NS_OFFSET))
+            {
+                /* Select PCLK as the clock source of QSPI */
+                if((qspi == QSPI0) || (qspi == QSPI0_NS))
+                {
+                    CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0;
+                }
+            }
+        }
+
+        /* Check clock source of QSPI */
+        if((qspi == QSPI0) || (qspi == QSPI0_NS))
+        {
+            if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_HXT)
+            {
+                u32ClkSrc = __HXT; /* Clock source is HXT */
+            }
+            else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PLL)
+            {
+                u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+            }
+            else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PCLK0)
+            {
+                u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */
+            }
+            else
+            {
+                u32ClkSrc = __HIRC; /* Clock source is HIRC */
+            }
+        }
+
+        if(u32BusClock >= u32HCLKFreq)
+        {
+            /* Set DIVIDER = 0 */
+            qspi->CLKDIV = 0UL;
+            /* Return master peripheral clock rate */
+            u32RetValue = u32ClkSrc;
+        }
+        else if(u32BusClock >= u32ClkSrc)
+        {
+            /* Set DIVIDER = 0 */
+            qspi->CLKDIV = 0UL;
+            /* Return master peripheral clock rate */
+            u32RetValue = u32ClkSrc;
+        }
+        else if(u32BusClock == 0UL)
+        {
+            /* Set DIVIDER to the maximum value 0x1FF. f_spi = f_spi_clk_src / (DIVIDER + 1) */
+            qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk;
+            /* Return master peripheral clock rate */
+            u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL));
+        }
+        else
+        {
+            u32Div = (((u32ClkSrc * 10UL) / u32BusClock + 5UL) / 10UL) - 1UL; /* Round to the nearest integer */
+            if(u32Div > 0x1FFUL)
+            {
+                u32Div = 0x1FFUL;
+                qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk;
+                /* Return master peripheral clock rate */
+                u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL));
+            }
+            else
+            {
+                qspi->CLKDIV = (qspi->CLKDIV & (~QSPI_CLKDIV_DIVIDER_Msk)) | (u32Div << QSPI_CLKDIV_DIVIDER_Pos);
+                /* Return master peripheral clock rate */
+                u32RetValue = (u32ClkSrc / (u32Div + 1UL));
+            }
+        }
+    }
+    else     /* For slave mode, force the QSPI peripheral clock rate to equal APB clock rate. */
+    {
+        /* Default setting: slave selection signal is low level active. */
+        qspi->SSCTL = QSPI_SS_ACTIVE_LOW;
+
+        /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
+        qspi->CTL = u32MasterSlave | (u32DataWidth << QSPI_CTL_DWIDTH_Pos) | (u32QSPIMode) | QSPI_CTL_SPIEN_Msk;
+
+        /* Set DIVIDER = 0 */
+        qspi->CLKDIV = 0UL;
+
+        if(!(__PC() & NS_OFFSET))
+        {
+            /* Select PCLK as the clock source of QSPI */
+            if((qspi == QSPI0) || (qspi == QSPI0_NS))
+            {
+                CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0;
+                /* Return slave peripheral clock rate */
+                u32RetValue = u32PCLK0Freq;
+            }
+        }
+        else
+        {
+            /* Check clock source of QSPI */
+            if((qspi == QSPI0) || (qspi == QSPI0_NS))
+            {
+                if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_HXT)
+                {
+                    u32RetValue = __HXT; /* Clock source is HXT */
+                }
+                else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PLL)
+                {
+                    u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+                }
+                else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PCLK0)
+                {
+                    u32RetValue = u32PCLK0Freq; /* Clock source is PCLK0 */
+                }
+                else
+                {
+                    u32RetValue = __HIRC; /* Clock source is HIRC */
+                }
+            }
+        }
+    }
+
+    return u32RetValue;
+}
+
+/**
+  * @brief  Disable QSPI controller.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return None
+  * @details Clear SPIEN bit of QSPI_CTL register to disable QSPI transfer control.
+  */
+void QSPI_Close(QSPI_T *qspi)
+{
+    qspi->CTL &= ~QSPI_CTL_SPIEN_Msk;
+}
+
+/**
+  * @brief  Clear RX FIFO buffer.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return None
+  * @details This function will clear QSPI RX FIFO buffer. The RXEMPTY (QSPI_STATUS[8]) will be set to 1.
+  */
+void QSPI_ClearRxFIFO(QSPI_T *qspi)
+{
+    qspi->FIFOCTL |= QSPI_FIFOCTL_RXFBCLR_Msk;
+}
+
+/**
+  * @brief  Clear TX FIFO buffer.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return None
+  * @details This function will clear QSPI TX FIFO buffer. The TXEMPTY (QSPI_STATUS[16]) will be set to 1.
+  * @note The TX shift register will not be cleared.
+  */
+void QSPI_ClearTxFIFO(QSPI_T *qspi)
+{
+    qspi->FIFOCTL |= QSPI_FIFOCTL_TXFBCLR_Msk;
+}
+
+/**
+  * @brief  Disable the automatic slave selection function.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return None
+  * @details This function will disable the automatic slave selection function and set slave selection signal to inactive state.
+  */
+void QSPI_DisableAutoSS(QSPI_T *qspi)
+{
+    qspi->SSCTL &= ~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SS_Msk);
+}
+
+/**
+  * @brief  Enable the automatic slave selection function.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @param[in]  u32SSPinMask Specifies slave selection pins. (QSPI_SS)
+  * @param[in]  u32ActiveLevel Specifies the active level of slave selection signal. (QSPI_SS_ACTIVE_HIGH, QSPI_SS_ACTIVE_LOW)
+  * @return None
+  * @details This function will enable the automatic slave selection function. Only available in Master mode.
+  *          The slave selection pin and the active level will be set in this function.
+  */
+void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
+{
+    qspi->SSCTL = (qspi->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | QSPI_SSCTL_AUTOSS_Msk);
+}
+
+/**
+  * @brief  Set the QSPI bus clock.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @param[in]  u32BusClock The expected frequency of QSPI bus clock in Hz.
+  * @return Actual frequency of QSPI bus clock.
+  * @details This function is only available in Master mode. The actual clock rate may be different from the target QSPI bus clock rate.
+  *          For example, if the QSPI source clock rate is 12 MHz and the target QSPI bus clock rate is 7 MHz, the actual QSPI bus clock
+  *          rate will be 6 MHz.
+  * @note   If u32BusClock = 0, DIVIDER setting will be set to the maximum value.
+  * @note   If u32BusClock >= system clock frequency for Secure, QSPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0.
+  * @note   If u32BusClock >= system clock frequency for Non-Secure, this function does not do anything to avoid the situation that the frequency of
+  *         QSPI bus clock cannot be faster than the system clock rate. User should set up carefully.
+  * @note   If u32BusClock >= QSPI peripheral clock source, DIVIDER will be set to 0.
+  */
+uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock)
+{
+    uint32_t u32ClkSrc, u32HCLKFreq;
+    uint32_t u32Div, u32RetValue;
+
+    /* Check if valid QSPI exist */
+    if(!((qspi == QSPI0) || (qspi == QSPI0_NS)))
+    {
+        return 0UL;
+    }
+
+    /* Get system clock frequency */
+    u32HCLKFreq = CLK_GetHCLKFreq();
+
+    if(u32BusClock >= u32HCLKFreq)
+    {
+        if(!(__PC() & NS_OFFSET))
+        {
+            /* Select PCLK as the clock source of QSPI */
+            CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0;
+        }
+    }
+
+    /* Check clock source of QSPI */
+    if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_HXT)
+    {
+        u32ClkSrc = __HXT; /* Clock source is HXT */
+    }
+    else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PLL)
+    {
+        u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+    }
+    else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PCLK0)
+    {
+        u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */
+    }
+    else
+    {
+        u32ClkSrc = __HIRC; /* Clock source is HIRC */
+    }
+
+    if(u32BusClock >= u32HCLKFreq)
+    {
+        /* Set DIVIDER = 0 */
+        qspi->CLKDIV = 0UL;
+        /* Return master peripheral clock rate */
+        u32RetValue = u32ClkSrc;
+    }
+    else if(u32BusClock >= u32ClkSrc)
+    {
+        /* Set DIVIDER = 0 */
+        qspi->CLKDIV = 0UL;
+        /* Return master peripheral clock rate */
+        u32RetValue = u32ClkSrc;
+    }
+    else if(u32BusClock == 0UL)
+    {
+        /* Set DIVIDER to the maximum value 0x1FF. f_spi = f_spi_clk_src / (DIVIDER + 1) */
+        qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk;
+        /* Return master peripheral clock rate */
+        u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL));
+    }
+    else
+    {
+        u32Div = (((u32ClkSrc * 10UL) / u32BusClock + 5UL) / 10UL) - 1UL; /* Round to the nearest integer */
+        if(u32Div > 0x1FFUL)
+        {
+            u32Div = 0x1FFUL;
+            qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk;
+            /* Return master peripheral clock rate */
+            u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL));
+        }
+        else
+        {
+            qspi->CLKDIV = (qspi->CLKDIV & (~QSPI_CLKDIV_DIVIDER_Msk)) | (u32Div << QSPI_CLKDIV_DIVIDER_Pos);
+            /* Return master peripheral clock rate */
+            u32RetValue = (u32ClkSrc / (u32Div + 1UL));
+        }
+    }
+
+    return u32RetValue;
+}
+
+/**
+  * @brief  Configure FIFO threshold setting.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @param[in]  u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 7.
+  * @param[in]  u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 7.
+  * @return None
+  * @details Set TX FIFO threshold and RX FIFO threshold configurations.
+  */
+void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
+{
+    qspi->FIFOCTL = (qspi->FIFOCTL & ~(QSPI_FIFOCTL_TXTH_Msk | QSPI_FIFOCTL_RXTH_Msk)) |
+                    (u32TxThreshold << QSPI_FIFOCTL_TXTH_Pos) |
+                    (u32RxThreshold << QSPI_FIFOCTL_RXTH_Pos);
+}
+
+/**
+  * @brief  Get the actual frequency of QSPI bus clock. Only available in Master mode.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @return Actual QSPI bus clock frequency in Hz.
+  * @details This function will calculate the actual QSPI bus clock rate according to the QQSPISEL/QSPIxSEL and DIVIDER settings. Only available in Master mode.
+  */
+uint32_t QSPI_GetBusClock(QSPI_T *qspi)
+{
+    uint32_t u32Div;
+    uint32_t u32ClkSrc;
+
+    /* Check if valid QSPI exist */
+    if(!((qspi == QSPI0) || (qspi == QSPI0_NS)))
+    {
+        return 0UL;
+    }
+
+    /* Get DIVIDER setting */
+    u32Div = (qspi->CLKDIV & QSPI_CLKDIV_DIVIDER_Msk) >> QSPI_CLKDIV_DIVIDER_Pos;
+
+    /* Check clock source of QSPI */
+    if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_HXT)
+    {
+        u32ClkSrc = __HXT; /* Clock source is HXT */
+    }
+    else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PLL)
+    {
+        u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+    }
+    else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PCLK0)
+    {
+        u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */
+    }
+    else
+    {
+        u32ClkSrc = __HIRC; /* Clock source is HIRC */
+    }
+
+    /* Return QSPI bus clock rate */
+    return (u32ClkSrc / (u32Div + 1UL));
+}
+
+/**
+  * @brief  Enable interrupt function.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @param[in]  u32Mask The combination of all related interrupt enable bits.
+  *                     Each bit corresponds to a interrupt enable bit.
+  *                     This parameter decides which interrupts will be enabled. It is combination of:
+  *                       - \ref QSPI_UNIT_INT_MASK
+  *                       - \ref QSPI_SSACT_INT_MASK
+  *                       - \ref QSPI_SSINACT_INT_MASK
+  *                       - \ref QSPI_SLVUR_INT_MASK
+  *                       - \ref QSPI_SLVBE_INT_MASK
+  *                       - \ref QSPI_SLVTO_INT_MASK
+  *                       - \ref QSPI_TXUF_INT_MASK
+  *                       - \ref QSPI_FIFO_TXTH_INT_MASK
+  *                       - \ref QSPI_FIFO_RXTH_INT_MASK
+  *                       - \ref QSPI_FIFO_RXOV_INT_MASK
+  *                       - \ref QSPI_FIFO_RXTO_INT_MASK
+  *
+  * @return None
+  * @details Enable QSPI related interrupts specified by u32Mask parameter.
+  */
+void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask)
+{
+    /* Enable unit transfer interrupt flag */
+    if((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK)
+    {
+        qspi->CTL |= QSPI_CTL_UNITIEN_Msk;
+    }
+
+    /* Enable slave selection signal active interrupt flag */
+    if((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK)
+    {
+        qspi->SSCTL |= QSPI_SSCTL_SSACTIEN_Msk;
+    }
+
+    /* Enable slave selection signal inactive interrupt flag */
+    if((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK)
+    {
+        qspi->SSCTL |= QSPI_SSCTL_SSINAIEN_Msk;
+    }
+
+    /* Enable slave TX under run interrupt flag */
+    if((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK)
+    {
+        qspi->SSCTL |= QSPI_SSCTL_SLVURIEN_Msk;
+    }
+
+    /* Enable slave bit count error interrupt flag */
+    if((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK)
+    {
+        qspi->SSCTL |= QSPI_SSCTL_SLVBEIEN_Msk;
+    }
+
+    /* Enable slave mode time-out interrupt flag */
+    if((u32Mask & QSPI_SLVTO_INT_MASK) == QSPI_SLVTO_INT_MASK)
+    {
+        qspi->SSCTL |= QSPI_SSCTL_SLVTOIEN_Msk;
+    }
+
+    /* Enable slave TX underflow interrupt flag */
+    if((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK)
+    {
+        qspi->FIFOCTL |= QSPI_FIFOCTL_TXUFIEN_Msk;
+    }
+
+    /* Enable TX threshold interrupt flag */
+    if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK)
+    {
+        qspi->FIFOCTL |= QSPI_FIFOCTL_TXTHIEN_Msk;
+    }
+
+    /* Enable RX threshold interrupt flag */
+    if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK)
+    {
+        qspi->FIFOCTL |= QSPI_FIFOCTL_RXTHIEN_Msk;
+    }
+
+    /* Enable RX overrun interrupt flag */
+    if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK)
+    {
+        qspi->FIFOCTL |= QSPI_FIFOCTL_RXOVIEN_Msk;
+    }
+
+    /* Enable RX time-out interrupt flag */
+    if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK)
+    {
+        qspi->FIFOCTL |= QSPI_FIFOCTL_RXTOIEN_Msk;
+    }
+}
+
+/**
+  * @brief  Disable interrupt function.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @param[in]  u32Mask The combination of all related interrupt enable bits.
+  *                     Each bit corresponds to a interrupt bit.
+  *                     This parameter decides which interrupts will be disabled. It is combination of:
+  *                       - \ref QSPI_UNIT_INT_MASK
+  *                       - \ref QSPI_SSACT_INT_MASK
+  *                       - \ref QSPI_SSINACT_INT_MASK
+  *                       - \ref QSPI_SLVUR_INT_MASK
+  *                       - \ref QSPI_SLVBE_INT_MASK
+  *                       - \ref QSPI_SLVTO_INT_MASK
+  *                       - \ref QSPI_TXUF_INT_MASK
+  *                       - \ref QSPI_FIFO_TXTH_INT_MASK
+  *                       - \ref QSPI_FIFO_RXTH_INT_MASK
+  *                       - \ref QSPI_FIFO_RXOV_INT_MASK
+  *                       - \ref QSPI_FIFO_RXTO_INT_MASK
+  *
+  * @return None
+  * @details Disable QSPI related interrupts specified by u32Mask parameter.
+  */
+void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask)
+{
+    /* Disable unit transfer interrupt flag */
+    if((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK)
+    {
+        qspi->CTL &= ~QSPI_CTL_UNITIEN_Msk;
+    }
+
+    /* Disable slave selection signal active interrupt flag */
+    if((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK)
+    {
+        qspi->SSCTL &= ~QSPI_SSCTL_SSACTIEN_Msk;
+    }
+
+    /* Disable slave selection signal inactive interrupt flag */
+    if((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK)
+    {
+        qspi->SSCTL &= ~QSPI_SSCTL_SSINAIEN_Msk;
+    }
+
+    /* Disable slave TX under run interrupt flag */
+    if((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK)
+    {
+        qspi->SSCTL &= ~QSPI_SSCTL_SLVURIEN_Msk;
+    }
+
+    /* Disable slave bit count error interrupt flag */
+    if((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK)
+    {
+        qspi->SSCTL &= ~QSPI_SSCTL_SLVBEIEN_Msk;
+    }
+
+    /* Disable slave mode time-out interrupt flag */
+    if((u32Mask & QSPI_SLVTO_INT_MASK) == QSPI_SLVTO_INT_MASK)
+    {
+        qspi->SSCTL &= ~QSPI_SSCTL_SLVTOIEN_Msk;
+    }
+
+    /* Disable slave TX underflow interrupt flag */
+    if((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK)
+    {
+        qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXUFIEN_Msk;
+    }
+
+    /* Disable TX threshold interrupt flag */
+    if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK)
+    {
+        qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXTHIEN_Msk;
+    }
+
+    /* Disable RX threshold interrupt flag */
+    if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK)
+    {
+        qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTHIEN_Msk;
+    }
+
+    /* Disable RX overrun interrupt flag */
+    if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK)
+    {
+        qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXOVIEN_Msk;
+    }
+
+    /* Disable RX time-out interrupt flag */
+    if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK)
+    {
+        qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTOIEN_Msk;
+    }
+}
+
+/**
+  * @brief  Get interrupt flag.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @param[in]  u32Mask The combination of all related interrupt sources.
+  *                     Each bit corresponds to a interrupt source.
+  *                     This parameter decides which interrupt flags will be read. It is combination of:
+  *                       - \ref QSPI_UNIT_INT_MASK
+  *                       - \ref QSPI_SSACT_INT_MASK
+  *                       - \ref QSPI_SSINACT_INT_MASK
+  *                       - \ref QSPI_SLVUR_INT_MASK
+  *                       - \ref QSPI_SLVBE_INT_MASK
+  *                       - \ref QSPI_SLVTO_INT_MASK
+  *                       - \ref QSPI_TXUF_INT_MASK
+  *                       - \ref QSPI_FIFO_TXTH_INT_MASK
+  *                       - \ref QSPI_FIFO_RXTH_INT_MASK
+  *                       - \ref QSPI_FIFO_RXOV_INT_MASK
+  *                       - \ref QSPI_FIFO_RXTO_INT_MASK
+  *
+  * @return Interrupt flags of selected sources.
+  * @details Get QSPI related interrupt flags specified by u32Mask parameter.
+  */
+uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask)
+{
+    uint32_t u32IntStatus;
+    uint32_t u32IntFlag = 0UL;
+
+    u32IntStatus = qspi->STATUS;
+
+    /* Check unit transfer interrupt flag */
+    if((u32Mask & QSPI_UNIT_INT_MASK) && (u32IntStatus & QSPI_STATUS_UNITIF_Msk))
+    {
+        u32IntFlag |= QSPI_UNIT_INT_MASK;
+    }
+
+    /* Check slave selection signal active interrupt flag */
+    if((u32Mask & QSPI_SSACT_INT_MASK) && (u32IntStatus & QSPI_STATUS_SSACTIF_Msk))
+    {
+        u32IntFlag |= QSPI_SSACT_INT_MASK;
+    }
+
+    /* Check slave selection signal inactive interrupt flag */
+    if((u32Mask & QSPI_SSINACT_INT_MASK) && (u32IntStatus & QSPI_STATUS_SSINAIF_Msk))
+    {
+        u32IntFlag |= QSPI_SSINACT_INT_MASK;
+    }
+
+    /* Check slave TX under run interrupt flag */
+    if((u32Mask & QSPI_SLVUR_INT_MASK) && (u32IntStatus & QSPI_STATUS_SLVURIF_Msk))
+    {
+        u32IntFlag |= QSPI_SLVUR_INT_MASK;
+    }
+
+    /* Check slave bit count error interrupt flag */
+    if((u32Mask & QSPI_SLVBE_INT_MASK) && (u32IntStatus & QSPI_STATUS_SLVBEIF_Msk))
+    {
+        u32IntFlag |= QSPI_SLVBE_INT_MASK;
+    }
+
+    /* Check slave mode time-out interrupt flag */
+    if((u32Mask & QSPI_SLVTO_INT_MASK) && (u32IntStatus & QSPI_STATUS_SLVTOIF_Msk))
+    {
+        u32IntFlag |= QSPI_SLVTO_INT_MASK;
+    }
+
+    /* Check slave TX underflow interrupt flag */
+    if((u32Mask & QSPI_TXUF_INT_MASK) && (u32IntStatus & QSPI_STATUS_TXUFIF_Msk))
+    {
+        u32IntFlag |= QSPI_TXUF_INT_MASK;
+    }
+
+    /* Check TX threshold interrupt flag */
+    if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) && (u32IntStatus & QSPI_STATUS_TXTHIF_Msk))
+    {
+        u32IntFlag |= QSPI_FIFO_TXTH_INT_MASK;
+    }
+
+    /* Check RX threshold interrupt flag */
+    if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) && (u32IntStatus & QSPI_STATUS_RXTHIF_Msk))
+    {
+        u32IntFlag |= QSPI_FIFO_RXTH_INT_MASK;
+    }
+
+    /* Check RX overrun interrupt flag */
+    if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) && (u32IntStatus & QSPI_STATUS_RXOVIF_Msk))
+    {
+        u32IntFlag |= QSPI_FIFO_RXOV_INT_MASK;
+    }
+
+    /* Check RX time-out interrupt flag */
+    if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) && (u32IntStatus & QSPI_STATUS_RXTOIF_Msk))
+    {
+        u32IntFlag |= QSPI_FIFO_RXTO_INT_MASK;
+    }
+
+    return u32IntFlag;
+}
+
+/**
+  * @brief  Clear interrupt flag.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @param[in]  u32Mask The combination of all related interrupt sources.
+  *                     Each bit corresponds to a interrupt source.
+  *                     This parameter decides which interrupt flags will be cleared. It could be the combination of:
+  *                       - \ref QSPI_UNIT_INT_MASK
+  *                       - \ref QSPI_SSACT_INT_MASK
+  *                       - \ref QSPI_SSINACT_INT_MASK
+  *                       - \ref QSPI_SLVUR_INT_MASK
+  *                       - \ref QSPI_SLVBE_INT_MASK
+  *                       - \ref QSPI_SLVTO_INT_MASK
+  *                       - \ref QSPI_TXUF_INT_MASK
+  *                       - \ref QSPI_FIFO_RXOV_INT_MASK
+  *                       - \ref QSPI_FIFO_RXTO_INT_MASK
+  *
+  * @return None
+  * @details Clear QSPI related interrupt flags specified by u32Mask parameter.
+  */
+void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask)
+{
+    if(u32Mask & QSPI_UNIT_INT_MASK)
+    {
+        qspi->STATUS = QSPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */
+    }
+
+    if(u32Mask & QSPI_SSACT_INT_MASK)
+    {
+        qspi->STATUS = QSPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */
+    }
+
+    if(u32Mask & QSPI_SSINACT_INT_MASK)
+    {
+        qspi->STATUS = QSPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */
+    }
+
+    if(u32Mask & QSPI_SLVUR_INT_MASK)
+    {
+        qspi->STATUS = QSPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */
+    }
+
+    if(u32Mask & QSPI_SLVBE_INT_MASK)
+    {
+        qspi->STATUS = QSPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */
+    }
+
+    if(u32Mask & QSPI_SLVTO_INT_MASK)
+    {
+        qspi->STATUS = QSPI_STATUS_SLVTOIF_Msk; /* Clear slave mode time-out interrupt flag */
+    }
+
+    if(u32Mask & QSPI_TXUF_INT_MASK)
+    {
+        qspi->STATUS = QSPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */
+    }
+
+    if(u32Mask & QSPI_FIFO_RXOV_INT_MASK)
+    {
+        qspi->STATUS = QSPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */
+    }
+
+    if(u32Mask & QSPI_FIFO_RXTO_INT_MASK)
+    {
+        qspi->STATUS = QSPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */
+    }
+}
+
+/**
+  * @brief  Get QSPI status.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @param[in]  u32Mask The combination of all related sources.
+  *                     Each bit corresponds to a source.
+  *                     This parameter decides which flags will be read. It is combination of:
+  *                       - \ref QSPI_BUSY_MASK
+  *                       - \ref QSPI_RX_EMPTY_MASK
+  *                       - \ref QSPI_RX_FULL_MASK
+  *                       - \ref QSPI_TX_EMPTY_MASK
+  *                       - \ref QSPI_TX_FULL_MASK
+  *                       - \ref QSPI_TXRX_RESET_MASK
+  *                       - \ref QSPI_SPIEN_STS_MASK
+  *                       - \ref QSPI_SSLINE_STS_MASK
+  *
+  * @return Flags of selected sources.
+  * @details Get QSPI related status specified by u32Mask parameter.
+  */
+uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask)
+{
+    uint32_t u32TmpStatus;
+    uint32_t u32Flag = 0UL;
+
+    u32TmpStatus = qspi->STATUS;
+
+    /* Check busy status */
+    if((u32Mask & QSPI_BUSY_MASK) && (u32TmpStatus & QSPI_STATUS_BUSY_Msk))
+    {
+        u32Flag |= QSPI_BUSY_MASK;
+    }
+
+    /* Check RX empty flag */
+    if((u32Mask & QSPI_RX_EMPTY_MASK) && (u32TmpStatus & QSPI_STATUS_RXEMPTY_Msk))
+    {
+        u32Flag |= QSPI_RX_EMPTY_MASK;
+    }
+
+    /* Check RX full flag */
+    if((u32Mask & QSPI_RX_FULL_MASK) && (u32TmpStatus & QSPI_STATUS_RXFULL_Msk))
+    {
+        u32Flag |= QSPI_RX_FULL_MASK;
+    }
+
+    /* Check TX empty flag */
+    if((u32Mask & QSPI_TX_EMPTY_MASK) && (u32TmpStatus & QSPI_STATUS_TXEMPTY_Msk))
+    {
+        u32Flag |= QSPI_TX_EMPTY_MASK;
+    }
+
+    /* Check TX full flag */
+    if((u32Mask & QSPI_TX_FULL_MASK) && (u32TmpStatus & QSPI_STATUS_TXFULL_Msk))
+    {
+        u32Flag |= QSPI_TX_FULL_MASK;
+    }
+
+    /* Check TX/RX reset flag */
+    if((u32Mask & QSPI_TXRX_RESET_MASK) && (u32TmpStatus & QSPI_STATUS_TXRXRST_Msk))
+    {
+        u32Flag |= QSPI_TXRX_RESET_MASK;
+    }
+
+    /* Check SPIEN flag */
+    if((u32Mask & QSPI_SPIEN_STS_MASK) && (u32TmpStatus & QSPI_STATUS_SPIENSTS_Msk))
+    {
+        u32Flag |= QSPI_SPIEN_STS_MASK;
+    }
+
+    /* Check QSPIx_SS line status */
+    if((u32Mask & QSPI_SSLINE_STS_MASK) && (u32TmpStatus & QSPI_STATUS_SSLINE_Msk))
+    {
+        u32Flag |= QSPI_SSLINE_STS_MASK;
+    }
+
+    return u32Flag;
+}
+
+/**
+  * @brief  Get QSPI status2.
+  * @param[in]  qspi The pointer of the specified QSPI module.
+  * @param[in]  u32Mask The combination of all related sources.
+  *                     Each bit corresponds to a source.
+  *                     This parameter decides which flags will be read. It is combination of:
+  *                       - \ref QSPI_SLVBENUM_MASK
+  *
+  * @return Flags of selected sources.
+  * @details Get QSPI related status specified by u32Mask parameter.
+  */
+uint32_t QSPI_GetStatus2(QSPI_T *qspi, uint32_t u32Mask)
+{
+    uint32_t u32TmpStatus;
+    uint32_t u32Number = 0UL;
+
+    u32TmpStatus = qspi->STATUS2;
+
+    /* Check effective bit number of uncompleted RX data status */
+    if(u32Mask & QSPI_SLVBENUM_MASK)
+    {
+        u32Number = (u32TmpStatus & QSPI_STATUS2_SLVBENUM_Msk) >> QSPI_STATUS2_SLVBENUM_Pos;
+    }
+
+    return u32Number;
+}
+
+/**@}*/ /* end of group QSPI_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group QSPI_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_rng.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_rng.c
new file mode 100644
index 0000000000..c2210c942d
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_rng.c
@@ -0,0 +1,475 @@
+/**************************************************************************//**
+ * @file     rng.c
+ * @version  V3.00
+ * @brief    Show how to get true random number.
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+#include 
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup RNG_Driver RNG Driver
+  @{
+*/
+
+
+/** @addtogroup RNG_EXPORTED_FUNCTIONS RNG Exported Functions
+  @{
+*/
+
+typedef enum _RNG_KEY_SIZE
+{
+    KEY_128 = 0,
+    KEY_192 = 2,
+    KEY_224 = 3,
+    KEY_233 = 4,
+    KEY_255 = 5,
+    KEY_256 = 6,
+    KEY_283 = 7,
+    KEY_384 = 8,
+    KEY_409 = 9,
+    KEY_512 = 10,
+    KEY_521 = 11,
+    KEY_571 = 12
+
+} eRNG_SZ;
+
+
+/**
+ *  @brief      Open random number generator
+ *
+ *  @return      0  Successful
+ *              -1  Failed
+ *
+ *  @details    The function is used to disable rng interrupt.
+ */
+int32_t RNG_Open(void)
+{
+    int32_t i;
+    int32_t timeout = 0x1000000;
+
+    /* Basic Configuration */
+    CLK->AHBCLK  |= CLK_AHBCLK_CRPTCKEN_Msk;
+    CLK->APBCLK1 |= CLK_APBCLK1_TRNGCKEN_Msk;
+    CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk;
+
+    RTC->LXTCTL |= (RTC_LXTCTL_C32KSEL_Msk | RTC_LXTCTL_LIRC32KEN_Msk); //To use LIRC32K
+
+    TRNG->ACT |= TRNG_ACT_ACT_Msk;
+    /* Waiting for ready */
+    i = 0;
+    while((TRNG->CTL & TRNG_CTL_READY_Msk) == 0)
+    {
+        if(i++ > timeout)
+        {
+            /* TRNG ready timeout */
+            return -1;
+        }
+    }
+
+    TRNG->CTL = (0 << TRNG_CTL_CLKPSC_Pos);
+
+
+    /* Enable SEEDGEN */
+    TRNG->CTL |= (1 << 8);
+
+    /* Waiting for seed ready */
+    i = 0;
+    while((TRNG->CTL & (1 << 9)) == 0)
+    {
+        if(i++ > timeout)
+        {
+            /* seed ready timeout */
+            return -1;
+        }
+    }
+
+    // Waiting for PRNG busy
+    i = 0;
+    while(CRPT->PRNG_CTL & (1 << 8))
+    {
+        if(i++ > timeout)
+        {
+            /* PRNG busy timeout */
+            return -1;
+        }
+    }
+
+    /* Set seed select to TRNG */
+    CRPT->PRNG_CTL = CRPT_PRNG_CTL_SEEDSEL_Msk;
+
+    /* Waiting for seed src ok */
+    i = 0;
+    while((CRPT->PRNG_CTL & CRPT_PRNG_CTL_SEEDSRC_Msk) == 0)
+    {
+        if(i++ > timeout)
+        {
+            /* PRNG src timeout */
+            return -1; // Timeout
+        }
+    }
+
+    /* Reload seed only at first time */
+    CRPT->PRNG_CTL |= (PRNG_KEY_SIZE_256 << CRPT_PRNG_CTL_KEYSZ_Pos) | CRPT_PRNG_CTL_START_Msk | CRPT_PRNG_CTL_SEEDRLD_Msk;
+
+    i = 0;
+    while(CRPT->PRNG_CTL & CRPT_PRNG_CTL_BUSY_Msk)
+    {
+        if(i++ > timeout)
+        {
+            /* busy timeout */
+            return -1;
+        }
+    }
+
+    return 0;
+}
+
+
+/**
+ *  @brief      Get random words
+ *
+ *  @param[in]  pu32Buf Buffer pointer to store the random number
+ *
+ *  @param[in]  nWords  Buffer size in word count. nWords must <= 8
+ *
+ *  @return     Word count of random number in buffer
+ *
+ *  @details    The function is used to generate random numbers
+ */
+int32_t RNG_Random(uint32_t *pu32Buf, int32_t nWords)
+{
+    int32_t i;
+    int32_t timeout = 0x10000;
+
+    /* Waiting for Busy */
+    while(CRPT->PRNG_CTL & CRPT_PRNG_CTL_BUSY_Msk) {}
+
+    if(nWords > 8)
+        nWords = 8;
+
+    /* Trig to generate seed 256 bits random number */
+    CRPT->PRNG_CTL = (6 << CRPT_PRNG_CTL_KEYSZ_Pos) | CRPT_PRNG_CTL_START_Msk;
+
+    while(CRPT->PRNG_CTL & CRPT_PRNG_CTL_BUSY_Msk)
+    {
+        if(timeout-- < 0)
+            return 0;
+    }
+
+    for(i = 0; i < nWords; i++)
+    {
+        pu32Buf[i] = CRPT->PRNG_KEY[i];
+    }
+
+    return nWords;
+}
+
+
+
+/**
+ *  @brief      To generate a key to KS SRAM for ECDSA.
+ *
+ *  @param[in]  u32KeySize  It could be PRNG_KEY_SIZE_128 ~ PRNG_KEY_SIZE_571
+ *
+ *  @param[in]  au32ECC_N   The N value of specified ECC curve.
+ *
+ *  @return     -1      Failed
+ *              Others  The key number in KS SRAM
+ *
+ *  @details    The function is used to generate a key to KS SRAM for ECDSA.
+ *              This key is necessary for ECDSA+Key Store function of ECC.
+ */
+int32_t RNG_ECDSA_Init(uint32_t u32KeySize, uint32_t au32ECC_N[18])
+{
+    int32_t i;
+    int32_t timeout = 0x1000000;
+
+    /* Basic Configuration */
+    CLK->AHBCLK  |= CLK_AHBCLK_CRPTCKEN_Msk;
+    CLK->APBCLK1 |= CLK_APBCLK1_TRNGCKEN_Msk;
+    CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk;
+
+    RTC->LXTCTL |= (RTC_LXTCTL_C32KSEL_Msk | RTC_LXTCTL_LIRC32KEN_Msk); //To use LIRC32K
+
+    TRNG->ACT |= TRNG_ACT_ACT_Msk;
+    /* Waiting for ready */
+    i = 0;
+    while((TRNG->CTL & TRNG_CTL_READY_Msk) == 0)
+    {
+        if(i++ > timeout)
+        {
+            return -1; // Timeout
+        }
+    }
+
+    TRNG->CTL = (0 << TRNG_CTL_CLKPSC_Pos);
+
+    /* Reset seed select of PRNG */
+    CRPT->PRNG_CTL = 0;
+
+
+    /* Enable SEEDGEN */
+    TRNG->CTL |= TRNG_CTL_SEEDGEN_Msk;
+
+    /* Waiting for seed ready */
+    i = 0;
+    while((TRNG->CTL & TRNG_CTL_SEEDRDY_Msk) == 0)
+    {
+        if(i++ > timeout)
+        {
+            return -1; // Timeout
+        }
+    }
+
+    // Waiting for PRNG busy
+    i = 0;
+    while(CRPT->PRNG_CTL & CRPT_PRNG_CTL_BUSY_Msk)
+    {
+        if(i++ > timeout)
+        {
+            return -1; // Timeout
+        }
+    }
+
+
+    // Set seed select to TRNG
+    CRPT->PRNG_CTL = 1 << CRPT_PRNG_CTL_SEEDSEL_Pos;
+
+    // Waiting for seed src ok
+    i = 0;
+    while((CRPT->PRNG_CTL & CRPT_PRNG_CTL_SEEDSRC_Msk) == 0)
+    {
+        if(i++ > timeout)
+        {
+            return -1; // Timeout
+        }
+    }
+
+    /* It is necessary to set ECC_N for ECDSA */
+    for(i = 0; i < 18; i++)
+        CRPT->ECC_N[i] = au32ECC_N[i];
+
+    CRPT->PRNG_KSCTL = 0;
+
+    /* Reload seed only at first time */
+    CRPT->PRNG_CTL |= (u32KeySize << CRPT_PRNG_CTL_KEYSZ_Pos) |
+                      CRPT_PRNG_CTL_START_Msk | CRPT_PRNG_CTL_SEEDRLD_Msk;
+
+
+    i = 0;
+    while(CRPT->PRNG_CTL & CRPT_PRNG_CTL_BUSY_Msk)
+    {
+        if(i++ > timeout)
+        {
+            return -1; // Timeout
+        }
+    }
+
+
+    CRPT->PRNG_KSCTL = (KS_OWNER_ECC << CRPT_PRNG_KSCTL_OWNER_Pos) |
+                       CRPT_PRNG_KSCTL_ECDSA_Msk |
+                       (CRPT_PRNG_KSCTL_WDST_Msk) |
+                       (KS_SRAM << CRPT_PRNG_KSCTL_WSDST_Pos);
+
+    return 0;
+}
+
+
+/**
+ *  @brief      To generate a key to KS SRAM for ECDSA.
+ *
+ *  @return     -1      Failed
+ *              Others  The key number in KS SRAM
+ *
+ *  @details    The function is used to generate a key to KS SRAM for ECDSA.
+ *              This key is necessary for ECDSA+Key Store function of ECC.
+ */
+int32_t RNG_ECDSA(uint32_t u32KeySize)
+{
+    int32_t timeout;
+    int32_t i;
+
+    /* Reload seed only at first time */
+    CRPT->PRNG_CTL = (u32KeySize << CRPT_PRNG_CTL_KEYSZ_Pos) |
+                     0xc0 |
+                     CRPT_PRNG_CTL_START_Msk;
+
+    timeout = 0x10000;
+    i = 0;
+    while(CRPT->PRNG_CTL & CRPT_PRNG_CTL_BUSY_Msk)
+    {
+        if(i++ > timeout)
+        {
+            //printf("busy timeout\n");
+            return -1; // Timeout
+        }
+    }
+
+    if(CRPT->PRNG_KSSTS & CRPT_PRNG_KSSTS_KCTLERR_Msk)
+    {
+        //printf("KCTLERR!\n");
+        return -1;
+    }
+
+    return (CRPT->PRNG_KSSTS & CRPT_PRNG_KSCTL_NUM_Msk);
+}
+
+
+
+/**
+ *  @brief      To generate a key to KS SRAM for ECDH.
+ *
+ *  @param[in]  u32KeySize  It could be PRNG_KEY_SIZE_128 ~ PRNG_KEY_SIZE_571
+ *
+ *  @param[in]  au32ECC_N   The N value of specified ECC curve.
+ *
+ *  @return     -1      Failed
+ *              Others  The key number in KS SRAM
+ *
+ *  @details    The function is used to generate a key to KS SRAM for ECDH.
+ *              This key is necessary for ECDH+Key Store function of ECC.
+ */
+int32_t RNG_ECDH_Init(uint32_t u32KeySize, uint32_t au32ECC_N[18])
+{
+    int32_t i;
+    int32_t timeout = 0x1000000;
+
+    /* Basic Configuration */
+    CLK->AHBCLK  |= CLK_AHBCLK_CRPTCKEN_Msk;
+    CLK->APBCLK1 |= CLK_APBCLK1_TRNGCKEN_Msk;
+    CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk;
+
+    RTC->LXTCTL |= (RTC_LXTCTL_C32KSEL_Msk | RTC_LXTCTL_LIRC32KEN_Msk); //To use LIRC32K
+
+    TRNG->ACT |= TRNG_ACT_ACT_Msk;
+    /* Waiting for ready */
+    i = 0;
+    while((TRNG->CTL & TRNG_CTL_READY_Msk) == 0)
+    {
+        if(i++ > timeout)
+        {
+            /* TRNG ready timeout */
+            return -1;
+        }
+    }
+
+    TRNG->CTL = (0 << TRNG_CTL_CLKPSC_Pos);
+
+
+    /* Enable SEEDGEN */
+    TRNG->CTL |= TRNG_CTL_SEEDGEN_Msk;
+
+    /* Waiting for seed ready */
+    i = 0;
+    while((TRNG->CTL & TRNG_CTL_SEEDRDY_Msk) == 0)
+    {
+        if(i++ > timeout)
+        {
+            /* seed ready timeout */
+            return -1;
+        }
+    }
+
+    /* Waiting for PRNG busy */
+    i = 0;
+    while(CRPT->PRNG_CTL & TRNG_CTL_SEEDGEN_Msk)
+    {
+        if(i++ > timeout)
+        {
+            /* PRNG busy timeout */
+            return -1;
+        }
+    }
+
+
+
+    /* Set seed select to TRNG */
+    CRPT->PRNG_CTL = (1 << 6);
+
+    // Waiting for seed src ok
+    i = 0;
+    while((CRPT->PRNG_CTL & (1 << 7)) == 0)
+    {
+        if(i++ > timeout)
+        {
+            /* PRNG src timeout */
+            return -1;
+        }
+    }
+
+    /* It is necessary to set ECC_N for ECDSA */
+    for(i = 0; i < 18; i++)
+        CRPT->ECC_N[i] = au32ECC_N[i];
+
+    CRPT->PRNG_KSCTL = 0;
+
+    /* Reload seed only at first time */
+    CRPT->PRNG_CTL |= (u32KeySize << CRPT_PRNG_CTL_KEYSZ_Pos) |
+                      CRPT_PRNG_CTL_START_Msk | CRPT_PRNG_CTL_SEEDRLD_Msk;
+
+
+    i = 0;
+    while(CRPT->PRNG_CTL & CRPT_PRNG_CTL_BUSY_Msk)
+    {
+        if(i++ > timeout)
+        {
+            /* busy timeout */
+            return -1;
+        }
+    }
+
+    CRPT->PRNG_KSCTL = (KS_OWNER_ECC << CRPT_PRNG_KSCTL_OWNER_Pos) |
+                       (CRPT_PRNG_KSCTL_ECDH_Msk) |
+                       (CRPT_PRNG_KSCTL_WDST_Msk) |
+                       (KS_SRAM << CRPT_PRNG_KSCTL_WSDST_Pos);
+
+    return 0;
+}
+
+
+/**
+ *  @brief      To generate a key to KS SRAM for ECDH.
+ *
+ *  @return     -1      Failed
+ *              Others  The key number in KS SRAM
+ *
+ *  @details    The function is used to generate a key to KS SRAM for ECDH.
+ *              This key is necessary for ECDH+Key Store function of ECC.
+ */
+int32_t RNG_ECDH(uint32_t u32KeySize)
+{
+    int32_t timeout;
+    int32_t i;
+
+    /* Reload seed only at first time */
+    CRPT->PRNG_CTL = (u32KeySize << CRPT_PRNG_CTL_KEYSZ_Pos) |
+                     0xc0 |
+                     CRPT_PRNG_CTL_START_Msk;
+
+    timeout = 0x10000;
+    i = 0;
+    while(CRPT->PRNG_CTL & CRPT_PRNG_CTL_BUSY_Msk)
+    {
+        if(i++ > timeout)
+            return -1;
+    }
+
+    if(CRPT->PRNG_KSSTS & CRPT_PRNG_KSSTS_KCTLERR_Msk)
+        return -1;
+
+    return (CRPT->PRNG_KSSTS & CRPT_PRNG_KSCTL_NUM_Msk);
+}
+
+/**@}*/ /* end of group RNG_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group RNG_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_rtc.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_rtc.c
new file mode 100644
index 0000000000..904958c415
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_rtc.c
@@ -0,0 +1,1174 @@
+/**************************************************************************//**
+ * @file     rtc.c
+ * @version  V3.00
+ * @brief    Real Time Clock(RTC) driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+
+
+/** @cond HIDDEN_SYMBOLS */
+/*---------------------------------------------------------------------------------------------------------*/
+/* Global file scope (static) variables                                                                    */
+/*---------------------------------------------------------------------------------------------------------*/
+static volatile uint32_t g_u32hiYear, g_u32loYear, g_u32hiMonth, g_u32loMonth, g_u32hiDay, g_u32loDay;
+static volatile uint32_t g_u32hiHour, g_u32loHour, g_u32hiMin, g_u32loMin, g_u32hiSec, g_u32loSec;
+
+/** @endcond HIDDEN_SYMBOLS */
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup RTC_Driver RTC Driver
+  @{
+*/
+
+/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Initialize RTC module and start counting
+  *
+  * @param[in]  sPt     Specify the time property and current date and time. It includes:           \n
+  *                     u32Year: Year value, range between 2000 ~ 2099.                             \n
+  *                     u32Month: Month value, range between 1 ~ 12.                                \n
+  *                     u32Day: Day value, range between 1 ~ 31.                                    \n
+  *                     u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
+  *                                                     RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
+  *                                                     RTC_SATURDAY]                               \n
+  *                     u32Hour: Hour value, range between 0 ~ 23.                                  \n
+  *                     u32Minute: Minute value, range between 0 ~ 59.                              \n
+  *                     u32Second: Second value, range between 0 ~ 59.                              \n
+  *                     u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24]                                 \n
+  *                     u8AmPm: [RTC_AM / RTC_PM]                                                   \n
+  *
+  * @return     None
+  *
+  * @details    This function is used to: \n
+  *                 1. Write initial key to let RTC start count.  \n
+  *                 2. Input parameter indicates start date/time. \n
+  *                 3. User has to make sure that parameters of RTC date/time are reasonable. \n
+  *                 4. Enable frequency dynamic compensation function. \n
+  * @note       Null pointer for using default starting date/time.
+  */
+void RTC_Open(S_RTC_TIME_DATA_T *sPt)
+{
+    RTC->INIT = RTC_INIT_KEY;
+
+    if(RTC->INIT != RTC_INIT_ACTIVE_Msk)
+    {
+        RTC->INIT = RTC_INIT_KEY;
+        while(RTC->INIT != RTC_INIT_ACTIVE_Msk) {}
+    }
+
+    if(sPt != 0)
+    {
+        /* Enable frequency dynamic compensation function */
+        RTC->CLKFMT |= RTC_CLKFMT_DCOMPEN_Msk;
+
+        /* Set RTC date and time */
+        RTC_SetDateAndTime(sPt);
+    }
+}
+
+/**
+  * @brief      Disable RTC Clock
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This API will disable RTC peripheral clock.
+  */
+void RTC_Close(void)
+{
+    if((__PC()&NS_OFFSET) != NS_OFFSET)
+    {
+        /* Only available in Secure code */
+        CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk;
+    }
+}
+
+/**
+  * @brief      Set 32K Frequency Compensation Data
+  *
+  * @param[in]  i32FrequencyX10000  Specify the RTC clock X10000, ex: 327736512 means 32773.6512.
+  *
+  * @return     None
+  *
+  * @details    This API is used to compensate the 32 kHz frequency by current LXT frequency for RTC application.
+  */
+void RTC_32KCalibration(int32_t i32FrequencyX10000)
+{
+    int32_t i32RegInt, i32RegFra;
+
+    /* Compute integer and fraction for RTC FCR register */
+    i32RegInt = (i32FrequencyX10000 / 10000) - RTC_FCR_REFERENCE;
+    i32RegFra = ((((i32FrequencyX10000 % 10000)) * 64) + 5000) / 10000;
+
+    if(i32RegFra >= 0x40)
+    {
+        i32RegFra = 0x0;
+        i32RegInt++;
+    }
+
+    /* Judge Integer part is reasonable */
+    if((i32RegInt >= 0) && (i32RegInt <= 31))
+    {
+        while((RTC->FREQADJ & RTC_FREQADJ_FCRBUSY_Msk) == RTC_FREQADJ_FCRBUSY_Msk) {}
+        RTC->FREQADJ = (uint32_t)((i32RegInt << 8) | i32RegFra);
+        while((RTC->FREQADJ & RTC_FREQADJ_FCRBUSY_Msk) == RTC_FREQADJ_FCRBUSY_Msk) {}
+    }
+}
+
+/**
+  * @brief      Get Current RTC Date and Time
+  *
+  * @param[out] sPt     The returned pointer is specified the current RTC value. It includes: \n
+  *                     u32Year: Year value                                                   \n
+  *                     u32Month: Month value                                                 \n
+  *                     u32Day: Day value                                                     \n
+  *                     u32DayOfWeek: Day of week                                             \n
+  *                     u32Hour: Hour value                                                   \n
+  *                     u32Minute: Minute value                                               \n
+  *                     u32Second: Second value                                               \n
+  *                     u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24]                           \n
+  *                     u8AmPm: [RTC_AM / RTC_PM]                                             \n
+  *
+  * @return     None
+  *
+  * @details    This API is used to get the current RTC date and time value.
+  */
+void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt)
+{
+    uint32_t u32Tmp;
+
+    sPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk;     /* 12/24-hour */
+    sPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */
+
+    /* Get [Date digit] data */
+    g_u32hiYear  = (RTC->CAL & RTC_CAL_TENYEAR_Msk) >> RTC_CAL_TENYEAR_Pos;
+    g_u32loYear  = (RTC->CAL & RTC_CAL_YEAR_Msk) >> RTC_CAL_YEAR_Pos;
+    g_u32hiMonth = (RTC->CAL & RTC_CAL_TENMON_Msk) >> RTC_CAL_TENMON_Pos;
+    g_u32loMonth = (RTC->CAL & RTC_CAL_MON_Msk) >> RTC_CAL_MON_Pos;
+    g_u32hiDay   = (RTC->CAL & RTC_CAL_TENDAY_Msk) >> RTC_CAL_TENDAY_Pos;
+    g_u32loDay   = (RTC->CAL & RTC_CAL_DAY_Msk) >> RTC_CAL_DAY_Pos;
+
+    /* Get [Time digit] data */
+    g_u32hiHour = (RTC->TIME & RTC_TIME_TENHR_Msk) >> RTC_TIME_TENHR_Pos;
+    g_u32loHour = (RTC->TIME & RTC_TIME_HR_Msk) >> RTC_TIME_HR_Pos;
+    g_u32hiMin  = (RTC->TIME & RTC_TIME_TENMIN_Msk) >> RTC_TIME_TENMIN_Pos;
+    g_u32loMin  = (RTC->TIME & RTC_TIME_MIN_Msk) >> RTC_TIME_MIN_Pos;
+    g_u32hiSec  = (RTC->TIME & RTC_TIME_TENSEC_Msk) >> RTC_TIME_TENSEC_Pos;
+    g_u32loSec  = (RTC->TIME & RTC_TIME_SEC_Msk) >> RTC_TIME_SEC_Pos;
+
+    /* Compute to 20XX year */
+    u32Tmp  = (g_u32hiYear * 10UL);
+    u32Tmp += g_u32loYear;
+    sPt->u32Year = u32Tmp + (uint32_t)RTC_YEAR2000;
+
+    /* Compute 0~12 month */
+    u32Tmp = (g_u32hiMonth * 10UL);
+    sPt->u32Month = u32Tmp + g_u32loMonth;
+
+    /* Compute 0~31 day */
+    u32Tmp = (g_u32hiDay * 10UL);
+    sPt->u32Day = u32Tmp + g_u32loDay;
+
+    /* Compute 12/24 hour */
+    if(sPt->u32TimeScale == (uint32_t)RTC_CLOCK_12)
+    {
+        u32Tmp  = (g_u32hiHour * 10UL);
+        u32Tmp += g_u32loHour;
+        sPt->u32Hour = u32Tmp;          /* AM: 1~12. PM: 21~32. */
+
+        if(sPt->u32Hour >= 21UL)
+        {
+            sPt->u32AmPm  = (uint32_t)RTC_PM;
+            sPt->u32Hour -= 20UL;
+        }
+        else
+        {
+            sPt->u32AmPm = (uint32_t)RTC_AM;
+        }
+
+        u32Tmp  = (g_u32hiMin  * 10UL);
+        u32Tmp += g_u32loMin;
+        sPt->u32Minute = u32Tmp;
+
+        u32Tmp  = (g_u32hiSec  * 10UL);
+        u32Tmp += g_u32loSec;
+        sPt->u32Second = u32Tmp;
+    }
+    else
+    {
+        u32Tmp  = (g_u32hiHour * 10UL);
+        u32Tmp += g_u32loHour;
+        sPt->u32Hour = u32Tmp;
+
+        u32Tmp  = (g_u32hiMin * 10UL);
+        u32Tmp +=  g_u32loMin;
+        sPt->u32Minute = u32Tmp;
+
+        u32Tmp  = (g_u32hiSec * 10UL);
+        u32Tmp += g_u32loSec;
+        sPt->u32Second = u32Tmp;
+    }
+}
+
+/**
+  * @brief      Get RTC Alarm Date and Time
+  *
+  * @param[out] sPt     The returned pointer is specified the RTC alarm value. It includes: \n
+  *                     u32Year: Year value                                                 \n
+  *                     u32Month: Month value                                               \n
+  *                     u32Day: Day value                                                   \n
+  *                     u32DayOfWeek: Day of week                                           \n
+  *                     u32Hour: Hour value                                                 \n
+  *                     u32Minute: Minute value                                             \n
+  *                     u32Second: Second value                                             \n
+  *                     u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24]                         \n
+  *                     u8AmPm: [RTC_AM / RTC_PM]                                           \n
+  *
+  * @return     None
+  *
+  * @details    This API is used to get the RTC alarm date and time setting.
+  */
+void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt)
+{
+    uint32_t u32Tmp;
+
+    sPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk;     /* 12/24-hour */
+    sPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */
+
+    /* Get alarm [Date digit] data */
+    g_u32hiYear  = (RTC->CALM & RTC_CALM_TENYEAR_Msk) >> RTC_CALM_TENYEAR_Pos;
+    g_u32loYear  = (RTC->CALM & RTC_CALM_YEAR_Msk) >> RTC_CALM_YEAR_Pos;
+    g_u32hiMonth = (RTC->CALM & RTC_CALM_TENMON_Msk) >> RTC_CALM_TENMON_Pos;
+    g_u32loMonth = (RTC->CALM & RTC_CALM_MON_Msk) >> RTC_CALM_MON_Pos;
+    g_u32hiDay   = (RTC->CALM & RTC_CALM_TENDAY_Msk) >> RTC_CALM_TENDAY_Pos;
+    g_u32loDay   = (RTC->CALM & RTC_CALM_DAY_Msk) >> RTC_CALM_DAY_Pos;
+
+    /* Get alarm [Time digit] data */
+    g_u32hiHour = (RTC->TALM & RTC_TALM_TENHR_Msk) >> RTC_TALM_TENHR_Pos;
+    g_u32loHour = (RTC->TALM & RTC_TALM_HR_Msk) >> RTC_TALM_HR_Pos;
+    g_u32hiMin  = (RTC->TALM & RTC_TALM_TENMIN_Msk) >> RTC_TALM_TENMIN_Pos;
+    g_u32loMin  = (RTC->TALM & RTC_TALM_MIN_Msk) >> RTC_TALM_MIN_Pos;
+    g_u32hiSec  = (RTC->TALM & RTC_TALM_TENSEC_Msk) >> RTC_TALM_TENSEC_Pos;
+    g_u32loSec  = (RTC->TALM & RTC_TALM_SEC_Msk) >> RTC_TALM_SEC_Pos;
+
+    /* Compute to 20XX year */
+    u32Tmp  = (g_u32hiYear * 10UL);
+    u32Tmp += g_u32loYear;
+    sPt->u32Year = u32Tmp + (uint32_t)RTC_YEAR2000;
+
+    /* Compute 0~12 month */
+    u32Tmp = (g_u32hiMonth * 10UL);
+    sPt->u32Month = u32Tmp + g_u32loMonth;
+
+    /* Compute 0~31 day */
+    u32Tmp = (g_u32hiDay * 10UL);
+    sPt->u32Day = u32Tmp + g_u32loDay;
+
+    /* Compute 12/24 hour */
+    if(sPt->u32TimeScale == (uint32_t)RTC_CLOCK_12)
+    {
+        u32Tmp  = (g_u32hiHour * 10UL);
+        u32Tmp += g_u32loHour;
+        sPt->u32Hour = u32Tmp;          /* AM: 1~12. PM: 21~32. */
+
+        if(sPt->u32Hour >= 21UL)
+        {
+            sPt->u32AmPm  = (uint32_t)RTC_PM;
+            sPt->u32Hour -= 20UL;
+        }
+        else
+        {
+            sPt->u32AmPm = (uint32_t)RTC_AM;
+        }
+
+        u32Tmp  = (g_u32hiMin * 10UL);
+        u32Tmp += g_u32loMin;
+        sPt->u32Minute = u32Tmp;
+
+        u32Tmp  = (g_u32hiSec * 10UL);
+        u32Tmp += g_u32loSec;
+        sPt->u32Second = u32Tmp;
+    }
+    else
+    {
+        u32Tmp  = (g_u32hiHour * 10UL);
+        u32Tmp +=  g_u32loHour;
+        sPt->u32Hour = u32Tmp;
+
+        u32Tmp  = (g_u32hiMin * 10UL);
+        u32Tmp += g_u32loMin;
+        sPt->u32Minute = u32Tmp;
+
+        u32Tmp  = (g_u32hiSec * 10UL);
+        u32Tmp += g_u32loSec;
+        sPt->u32Second = u32Tmp;
+    }
+}
+
+/**
+  * @brief      Update Current RTC Date and Time
+  *
+  * @param[in]  sPt     Specify the time property and current date and time. It includes:           \n
+  *                     u32Year: Year value, range between 2000 ~ 2099.                             \n
+  *                     u32Month: Month value, range between 1 ~ 12.                                \n
+  *                     u32Day: Day value, range between 1 ~ 31.                                    \n
+  *                     u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
+  *                                                     RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
+  *                                                     RTC_SATURDAY]                               \n
+  *                     u32Hour: Hour value, range between 0 ~ 23.                                  \n
+  *                     u32Minute: Minute value, range between 0 ~ 59.                              \n
+  *                     u32Second: Second value, range between 0 ~ 59.                              \n
+  *                     u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24]                                 \n
+  *                     u8AmPm: [RTC_AM / RTC_PM]                                                   \n
+  *
+  * @return     None
+  *
+  * @details    This API is used to update current date and time to RTC.
+  */
+void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt)
+{
+    uint32_t u32RegCAL, u32RegTIME;
+
+    if(sPt != 0)
+    {
+        /*-----------------------------------------------------------------------------------------------------*/
+        /* Set RTC 24/12 hour setting and Day of the Week                                                      */
+        /*-----------------------------------------------------------------------------------------------------*/
+        if(sPt->u32TimeScale == (uint32_t)RTC_CLOCK_12)
+        {
+            RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
+
+            /*-------------------------------------------------------------------------------------------------*/
+            /* Important, range of 12-hour PM mode is 21 up to 32                                               */
+            /*-------------------------------------------------------------------------------------------------*/
+            if(sPt->u32AmPm == (uint32_t)RTC_PM)
+            {
+                sPt->u32Hour += 20UL;
+            }
+        }
+        else
+        {
+            RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
+        }
+
+        /* Set Day of the Week */
+        RTC->WEEKDAY = sPt->u32DayOfWeek;
+
+        /*-----------------------------------------------------------------------------------------------------*/
+        /* Set RTC Current Date and Time                                                                       */
+        /*-----------------------------------------------------------------------------------------------------*/
+        u32RegCAL  = ((sPt->u32Year - (uint32_t)RTC_YEAR2000) / 10UL) << 20;
+        u32RegCAL |= (((sPt->u32Year - (uint32_t)RTC_YEAR2000) % 10UL) << 16);
+        u32RegCAL |= ((sPt->u32Month  / 10UL) << 12);
+        u32RegCAL |= ((sPt->u32Month  % 10UL) << 8);
+        u32RegCAL |= ((sPt->u32Day    / 10UL) << 4);
+        u32RegCAL |= (sPt->u32Day     % 10UL);
+
+        u32RegTIME  = ((sPt->u32Hour   / 10UL) << 20);
+        u32RegTIME |= ((sPt->u32Hour   % 10UL) << 16);
+        u32RegTIME |= ((sPt->u32Minute / 10UL) << 12);
+        u32RegTIME |= ((sPt->u32Minute % 10UL) << 8);
+        u32RegTIME |= ((sPt->u32Second / 10UL) << 4);
+        u32RegTIME |= (sPt->u32Second % 10UL);
+
+        /*-----------------------------------------------------------------------------------------------------*/
+        /* Set RTC Calender and Time Loading                                                                   */
+        /*-----------------------------------------------------------------------------------------------------*/
+        RTC->CAL  = (uint32_t)u32RegCAL;
+        RTC->TIME = (uint32_t)u32RegTIME;
+    }
+}
+
+/**
+  * @brief      Update RTC Alarm Date and Time
+  *
+  * @param[in]  sPt     Specify the time property and alarm date and time. It includes:             \n
+  *                     u32Year: Year value, range between 2000 ~ 2099.                             \n
+  *                     u32Month: Month value, range between 1 ~ 12.                                \n
+  *                     u32Day: Day value, range between 1 ~ 31.                                    \n
+  *                     u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
+  *                                                     RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
+  *                                                     RTC_SATURDAY]                               \n
+  *                     u32Hour: Hour value, range between 0 ~ 23.                                  \n
+  *                     u32Minute: Minute value, range between 0 ~ 59.                              \n
+  *                     u32Second: Second value, range between 0 ~ 59.                              \n
+  *                     u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24]                                 \n
+  *                     u8AmPm: [RTC_AM / RTC_PM]                                                   \n
+  *
+  * @return     None
+  *
+  * @details    This API is used to update alarm date and time setting to RTC.
+  */
+void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt)
+{
+    uint32_t u32RegCALM, u32RegTALM;
+
+    if(sPt != 0)
+    {
+        /*-----------------------------------------------------------------------------------------------------*/
+        /* Set RTC 24/12 hour setting and Day of the Week                                                      */
+        /*-----------------------------------------------------------------------------------------------------*/
+        if(sPt->u32TimeScale == (uint32_t)RTC_CLOCK_12)
+        {
+            RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
+
+            /*-------------------------------------------------------------------------------------------------*/
+            /* Important, range of 12-hour PM mode is 21 up to 32                                               */
+            /*-------------------------------------------------------------------------------------------------*/
+            if(sPt->u32AmPm == (uint32_t)RTC_PM)
+            {
+                sPt->u32Hour += 20UL;
+            }
+        }
+        else
+        {
+            RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
+        }
+
+        /*-----------------------------------------------------------------------------------------------------*/
+        /* Set RTC Alarm Date and Time                                                                         */
+        /*-----------------------------------------------------------------------------------------------------*/
+        u32RegCALM  = ((sPt->u32Year - (uint32_t)RTC_YEAR2000) / 10UL) << 20;
+        u32RegCALM |= (((sPt->u32Year - (uint32_t)RTC_YEAR2000) % 10UL) << 16);
+        u32RegCALM |= ((sPt->u32Month  / 10UL) << 12);
+        u32RegCALM |= ((sPt->u32Month  % 10UL) << 8);
+        u32RegCALM |= ((sPt->u32Day    / 10UL) << 4);
+        u32RegCALM |= (sPt->u32Day    % 10UL);
+
+        u32RegTALM  = ((sPt->u32Hour   / 10UL) << 20);
+        u32RegTALM |= ((sPt->u32Hour   % 10UL) << 16);
+        u32RegTALM |= ((sPt->u32Minute / 10UL) << 12);
+        u32RegTALM |= ((sPt->u32Minute % 10UL) << 8);
+        u32RegTALM |= ((sPt->u32Second / 10UL) << 4);
+        u32RegTALM |= (sPt->u32Second % 10UL);
+
+        RTC->CALM = (uint32_t)u32RegCALM;
+        RTC->TALM = (uint32_t)u32RegTALM;
+    }
+}
+
+/**
+  * @brief      Update RTC Current Date
+  *
+  * @param[in]  u32Year         The year calendar digit of current RTC setting.
+  * @param[in]  u32Month        The month calendar digit of current RTC setting.
+  * @param[in]  u32Day          The day calendar digit of current RTC setting.
+  * @param[in]  u32DayOfWeek    The Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY /
+  *                                                   RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY /
+  *                                                   RTC_SATURDAY]
+  *
+  * @return     None
+  *
+  * @details    This API is used to update current date to RTC.
+  */
+void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek)
+{
+    uint32_t u32RegCAL;
+
+    u32RegCAL  = ((u32Year - (uint32_t)RTC_YEAR2000) / 10UL) << 20;
+    u32RegCAL |= (((u32Year - (uint32_t)RTC_YEAR2000) % 10UL) << 16);
+    u32RegCAL |= ((u32Month / 10UL) << 12);
+    u32RegCAL |= ((u32Month % 10UL) << 8);
+    u32RegCAL |= ((u32Day   / 10UL) << 4);
+    u32RegCAL |= (u32Day   % 10UL);
+
+
+    /* Set Day of the Week */
+    RTC->WEEKDAY = u32DayOfWeek & RTC_WEEKDAY_WEEKDAY_Msk;
+
+    /* Set RTC Calender Loading */
+    RTC->CAL = (uint32_t)u32RegCAL;
+}
+
+/**
+  * @brief      Update RTC Current Time
+  *
+  * @param[in]  u32Hour         The hour time digit of current RTC setting.
+  * @param[in]  u32Minute       The minute time digit of current RTC setting.
+  * @param[in]  u32Second       The second time digit of current RTC setting.
+  * @param[in]  u32TimeMode     The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24]
+  * @param[in]  u32AmPm         12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM]
+  *
+  * @return     None
+  *
+  * @details    This API is used to update current time to RTC.
+  */
+void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm)
+{
+    uint32_t u32RegTIME;
+
+    /* Important, range of 12-hour PM mode is 21 up to 32 */
+    if((u32TimeMode == (uint32_t)RTC_CLOCK_12) && (u32AmPm == (uint32_t)RTC_PM))
+    {
+        u32Hour += 20UL;
+    }
+
+    u32RegTIME  = ((u32Hour   / 10UL) << 20);
+    u32RegTIME |= ((u32Hour   % 10UL) << 16);
+    u32RegTIME |= ((u32Minute / 10UL) << 12);
+    u32RegTIME |= ((u32Minute % 10UL) << 8);
+    u32RegTIME |= ((u32Second / 10UL) << 4);
+    u32RegTIME |= (u32Second % 10UL);
+
+    /*-----------------------------------------------------------------------------------------------------*/
+    /* Set RTC 24/12 hour setting and Day of the Week                                                      */
+    /*-----------------------------------------------------------------------------------------------------*/
+    if(u32TimeMode == (uint32_t)RTC_CLOCK_12)
+    {
+        RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
+    }
+    else
+    {
+        RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
+    }
+
+    RTC->TIME = (uint32_t)u32RegTIME;
+}
+
+/**
+  * @brief      Update RTC Alarm Date
+  *
+  * @param[in]  u32Year         The year calendar digit of RTC alarm setting.
+  * @param[in]  u32Month        The month calendar digit of RTC alarm setting.
+  * @param[in]  u32Day          The day calendar digit of RTC alarm setting.
+  *
+  * @return     None
+  *
+  * @details    This API is used to update alarm date setting to RTC.
+  */
+void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day)
+{
+    uint32_t u32RegCALM;
+
+    u32RegCALM  = ((u32Year - (uint32_t)RTC_YEAR2000) / 10UL) << 20;
+    u32RegCALM |= (((u32Year - (uint32_t)RTC_YEAR2000) % 10UL) << 16);
+    u32RegCALM |= ((u32Month / 10UL) << 12);
+    u32RegCALM |= ((u32Month % 10UL) << 8);
+    u32RegCALM |= ((u32Day   / 10UL) << 4);
+    u32RegCALM |= (u32Day   % 10UL);
+
+
+    /* Set RTC Alarm Date */
+    RTC->CALM = (uint32_t)u32RegCALM;
+}
+
+/**
+  * @brief      Update RTC Alarm Time
+  *
+  * @param[in]  u32Hour         The hour time digit of RTC alarm setting.
+  * @param[in]  u32Minute       The minute time digit of RTC alarm setting.
+  * @param[in]  u32Second       The second time digit of RTC alarm setting.
+  * @param[in]  u32TimeMode     The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24]
+  * @param[in]  u32AmPm         12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM]
+  *
+  * @return     None
+  *
+  * @details    This API is used to update alarm time setting to RTC.
+  */
+void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm)
+{
+    uint32_t u32RegTALM;
+
+    /* Important, range of 12-hour PM mode is 21 up to 32 */
+    if((u32TimeMode == (uint32_t)RTC_CLOCK_12) && (u32AmPm == (uint32_t)RTC_PM))
+    {
+        u32Hour += 20UL;
+    }
+
+    u32RegTALM  = ((u32Hour   / 10UL) << 20);
+    u32RegTALM |= ((u32Hour   % 10UL) << 16);
+    u32RegTALM |= ((u32Minute / 10UL) << 12);
+    u32RegTALM |= ((u32Minute % 10UL) << 8);
+    u32RegTALM |= ((u32Second / 10UL) << 4);
+    u32RegTALM |= (u32Second % 10UL);
+
+    /*-----------------------------------------------------------------------------------------------------*/
+    /* Set RTC 24/12 hour setting and Day of the Week                                                      */
+    /*-----------------------------------------------------------------------------------------------------*/
+    if(u32TimeMode == (uint32_t)RTC_CLOCK_12)
+    {
+        RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
+    }
+    else
+    {
+        RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
+    }
+
+    /* Set RTC Alarm Time */
+    RTC->TALM = (uint32_t)u32RegTALM;
+}
+
+/**
+  * @brief      Set RTC Alarm Date Mask Function
+  *
+  * @param[in]  u8IsTenYMsk     1: enable 10-Year digit alarm mask; 0: disabled.
+  * @param[in]  u8IsYMsk        1: enable 1-Year digit alarm mask; 0: disabled.
+  * @param[in]  u8IsTenMMsk     1: enable 10-Mon digit alarm mask; 0: disabled.
+  * @param[in]  u8IsMMsk        1: enable 1-Mon digit alarm mask; 0: disabled.
+  * @param[in]  u8IsTenDMsk     1: enable 10-Day digit alarm mask; 0: disabled.
+  * @param[in]  u8IsDMsk        1: enable 1-Day digit alarm mask; 0: disabled.
+  *
+  * @return     None
+  *
+  * @details    This API is used to enable or disable RTC alarm date mask function.
+  */
+void RTC_SetAlarmDateMask(uint8_t u8IsTenYMsk, uint8_t u8IsYMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenDMsk, uint8_t u8IsDMsk)
+{
+    RTC->CAMSK = ((uint32_t)u8IsTenYMsk << RTC_CAMSK_MTENYEAR_Pos) |
+                 ((uint32_t)u8IsYMsk    << RTC_CAMSK_MYEAR_Pos) |
+                 ((uint32_t)u8IsTenMMsk << RTC_CAMSK_MTENMON_Pos) |
+                 ((uint32_t)u8IsMMsk    << RTC_CAMSK_MMON_Pos) |
+                 ((uint32_t)u8IsTenDMsk << RTC_CAMSK_MTENDAY_Pos) |
+                 ((uint32_t)u8IsDMsk    << RTC_CAMSK_MDAY_Pos);
+}
+
+/**
+  * @brief      Set RTC Alarm Time Mask Function
+  *
+  * @param[in]  u8IsTenHMsk     1: enable 10-Hour digit alarm mask; 0: disabled.
+  * @param[in]  u8IsHMsk        1: enable 1-Hour digit alarm mask; 0: disabled.
+  * @param[in]  u8IsTenMMsk     1: enable 10-Min digit alarm mask; 0: disabled.
+  * @param[in]  u8IsMMsk        1: enable 1-Min digit alarm mask; 0: disabled.
+  * @param[in]  u8IsTenSMsk     1: enable 10-Sec digit alarm mask; 0: disabled.
+  * @param[in]  u8IsSMsk        1: enable 1-Sec digit alarm mask; 0: disabled.
+  *
+  * @return     None
+  *
+  * @details    This API is used to enable or disable RTC alarm time mask function.
+  */
+void RTC_SetAlarmTimeMask(uint8_t u8IsTenHMsk, uint8_t u8IsHMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenSMsk, uint8_t u8IsSMsk)
+{
+    RTC->TAMSK = ((uint32_t)u8IsTenHMsk << RTC_TAMSK_MTENHR_Pos) |
+                 ((uint32_t)u8IsHMsk    << RTC_TAMSK_MHR_Pos) |
+                 ((uint32_t)u8IsTenMMsk << RTC_TAMSK_MTENMIN_Pos) |
+                 ((uint32_t)u8IsMMsk    << RTC_TAMSK_MMIN_Pos) |
+                 ((uint32_t)u8IsTenSMsk << RTC_TAMSK_MTENSEC_Pos) |
+                 ((uint32_t)u8IsSMsk    << RTC_TAMSK_MSEC_Pos);
+}
+
+/**
+  * @brief      Get Day of the Week
+  *
+  * @param      None
+  *
+  * @retval     0   Sunday
+  * @retval     1   Monday
+  * @retval     2   Tuesday
+  * @retval     3   Wednesday
+  * @retval     4   Thursday
+  * @retval     5   Friday
+  * @retval     6   Saturday
+  *
+  * @details    This API is used to get day of the week of current RTC date.
+  */
+uint32_t RTC_GetDayOfWeek(void)
+{
+    return (RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk);
+}
+
+/**
+  * @brief      Set RTC Tick Period Time
+  *
+  * @param[in]  u32TickSelection    It is used to set the RTC tick period time for Periodic Time Tick request. \n
+  *                                 It consists of:
+  *                                     - \ref RTC_TICK_1_SEC     : Time tick is 1 second
+  *                                     - \ref RTC_TICK_1_2_SEC   : Time tick is 1/2 second
+  *                                     - \ref RTC_TICK_1_4_SEC   : Time tick is 1/4 second
+  *                                     - \ref RTC_TICK_1_8_SEC   : Time tick is 1/8 second
+  *                                     - \ref RTC_TICK_1_16_SEC  : Time tick is 1/16 second
+  *                                     - \ref RTC_TICK_1_32_SEC  : Time tick is 1/32 second
+  *                                     - \ref RTC_TICK_1_64_SEC  : Time tick is 1/64 second
+  *                                     - \ref RTC_TICK_1_128_SEC : Time tick is 1/128 second
+  *
+  * @return     None
+  *
+  * @details    This API is used to set RTC tick period time for each tick interrupt.
+  */
+void RTC_SetTickPeriod(uint32_t u32TickSelection)
+{
+    RTC->TICK = (RTC->TICK & ~RTC_TICK_TICK_Msk) | u32TickSelection;
+}
+
+/**
+  * @brief      Enable RTC Interrupt
+  *
+  * @param[in]  u32IntFlagMask      Specify the interrupt source. It consists of:
+  *                                     - \ref RTC_INTEN_ALMIEN_Msk   : Alarm interrupt
+  *                                     - \ref RTC_INTEN_TICKIEN_Msk  : Tick interrupt
+  *                                     - \ref RTC_INTEN_TAMP0IEN_Msk : Tamper 0 Pin Event Detection interrupt
+  *                                     - \ref RTC_INTEN_TAMP1IEN_Msk : Tamper 1 or Pair 0 Pin Event Detection interrupt
+  *                                     - \ref RTC_INTEN_TAMP2IEN_Msk : Tamper 2 Pin Event Detection interrupt
+  *                                     - \ref RTC_INTEN_TAMP3IEN_Msk : Tamper 3 or Pair 1 Pin Event Detection interrupt
+  *                                     - \ref RTC_INTEN_TAMP4IEN_Msk : Tamper 4 Pin Event Detection interrupt
+  *                                     - \ref RTC_INTEN_TAMP5IEN_Msk : Tamper 5 or Pair 2 Pin Event Detection interrupt
+  *                                     - \ref RTC_INTEN_CLKFIEN_Msk  : LXT Clock Frequency Monitor Fail interrupt
+  *                                     - \ref RTC_INTEN_CLKSTIEN_Msk : LXT Clock Frequency Monitor Stop interrupt
+  *
+  * @return     None
+  *
+  * @details    This API is used to enable the specify RTC interrupt function.
+  */
+void RTC_EnableInt(uint32_t u32IntFlagMask)
+{
+    RTC->INTEN |= u32IntFlagMask;
+}
+
+/**
+  * @brief      Disable RTC Interrupt
+  *
+  * @param[in]  u32IntFlagMask      Specify the interrupt source. It consists of:
+  *                                     - \ref RTC_INTEN_ALMIEN_Msk   : Alarm interrupt
+  *                                     - \ref RTC_INTEN_TICKIEN_Msk  : Tick interrupt
+  *                                     - \ref RTC_INTEN_TAMP0IEN_Msk : Tamper 0 Pin Event Detection interrupt
+  *                                     - \ref RTC_INTEN_TAMP1IEN_Msk : Tamper 1 or Pair 0 Pin Event Detection interrupt
+  *                                     - \ref RTC_INTEN_TAMP2IEN_Msk : Tamper 2 Pin Event Detection interrupt
+  *                                     - \ref RTC_INTEN_TAMP3IEN_Msk : Tamper 3 or Pair 1 Pin Event Detection interrupt
+  *                                     - \ref RTC_INTEN_TAMP4IEN_Msk : Tamper 4 Pin Event Detection interrupt
+  *                                     - \ref RTC_INTEN_TAMP5IEN_Msk : Tamper 5 or Pair 2 Pin Event Detection interrupt
+  *                                     - \ref RTC_INTEN_CLKFIEN_Msk  : LXT Clock Frequency Monitor Fail interrupt
+  *                                     - \ref RTC_INTEN_CLKSTIEN_Msk : LXT Clock Frequency Monitor Stop interrupt
+  *
+  * @return     None
+  *
+  * @details    This API is used to disable the specify RTC interrupt function.
+  */
+void RTC_DisableInt(uint32_t u32IntFlagMask)
+{
+    RTC->INTEN  &= ~u32IntFlagMask;
+    RTC->INTSTS = u32IntFlagMask;
+}
+
+/**
+  * @brief      Enable Spare Registers Access
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This API is used to enable the spare registers 0~19 can be accessed.
+  */
+void RTC_EnableSpareAccess(void)
+{
+    RTC->SPRCTL |= RTC_SPRCTL_SPRRWEN_Msk;
+}
+
+/**
+  * @brief      Disable Spare Register
+  *
+  * @param      None
+  *
+  * @return     None
+  *
+  * @details    This API is used to disable the spare register 0~19 cannot be accessed.
+  */
+void RTC_DisableSpareRegister(void)
+{
+    RTC->SPRCTL &= ~RTC_SPRCTL_SPRRWEN_Msk;
+}
+
+/**
+  * @brief      Static Tamper Detect
+  *
+  * @param[in]  u32TamperSelect     Tamper pin select. Possible options are
+  *                                 - \ref RTC_TAMPER5_SELECT
+  *                                 - \ref RTC_TAMPER4_SELECT
+  *                                 - \ref RTC_TAMPER3_SELECT
+  *                                 - \ref RTC_TAMPER2_SELECT
+  *                                 - \ref RTC_TAMPER1_SELECT
+  *                                 - \ref RTC_TAMPER0_SELECT
+  *
+  * @param[in]  u32DetecLevel       Tamper pin detection level select. Possible options are
+  *                                 - \ref RTC_TAMPER_HIGH_LEVEL_DETECT
+  *                                 - \ref RTC_TAMPER_LOW_LEVEL_DETECT
+  *
+  * @param[in]  u32DebounceEn       Tamper pin de-bounce enable
+  *                                 - \ref RTC_TAMPER_DEBOUNCE_ENABLE
+  *                                 - \ref RTC_TAMPER_DEBOUNCE_DISABLE
+  *
+  * @return     None
+  *
+  * @details    This API is used to enable the tamper pin detect function with specify trigger condition.
+  *             User need disable dynamic tamper function before use this API.
+  */
+void RTC_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn)
+{
+    uint32_t i;
+    uint32_t u32Reg;
+    uint32_t u32TmpReg;
+
+    u32Reg = RTC->TAMPCTL;
+
+    u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | (u32DetecLevel << RTC_TAMPCTL_TAMP0LV_Pos) |
+                 (u32DebounceEn << RTC_TAMPCTL_TAMP0DBEN_Pos));
+
+    for(i = 0UL; i < (uint32_t)RTC_MAX_TAMPER_PIN_NUM; i++)
+    {
+        if(u32TamperSelect & (0x1UL << i))
+        {
+            u32Reg &= ~((RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP0LV_Msk | RTC_TAMPCTL_TAMP0DBEN_Msk) << (i * 4UL));
+            u32Reg |= (u32TmpReg << (i * 4UL));
+        }
+    }
+
+    RTC->TAMPCTL = u32Reg;
+
+}
+
+/**
+  * @brief      Static Tamper Disable
+  *
+  * @param[in]  u32TamperSelect     Tamper pin select. Possible options are
+  *                                 - \ref RTC_TAMPER5_SELECT
+  *                                 - \ref RTC_TAMPER4_SELECT
+  *                                 - \ref RTC_TAMPER3_SELECT
+  *                                 - \ref RTC_TAMPER2_SELECT
+  *                                 - \ref RTC_TAMPER1_SELECT
+  *                                 - \ref RTC_TAMPER0_SELECT
+  *
+  * @return     None
+  *
+  * @details    This API is used to disable the static tamper pin detect.
+  */
+void RTC_StaticTamperDisable(uint32_t u32TamperSelect)
+{
+    uint32_t i;
+    uint32_t u32Reg;
+    uint32_t u32TmpReg;
+
+    u32Reg = RTC->TAMPCTL;
+
+    u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk);
+
+    for(i = 0UL; i < (uint32_t)RTC_MAX_TAMPER_PIN_NUM; i++)
+    {
+        if(u32TamperSelect & (0x1UL << i))
+        {
+            u32Reg &= ~(u32TmpReg << (i * 4UL));
+        }
+    }
+
+    RTC->TAMPCTL = u32Reg;
+}
+
+/**
+  * @brief      Dynamic Tamper Detect
+  *
+  * @param[in]  u32PairSel          Tamper pin detection enable. Possible options are
+  *                                 - \ref RTC_PAIR0_SELECT
+  *                                 - \ref RTC_PAIR1_SELECT
+  *                                 - \ref RTC_PAIR2_SELECT
+  *
+  * @param[in]  u32DebounceEn       Tamper pin de-bounce enable
+  *                                 - \ref RTC_TAMPER_DEBOUNCE_ENABLE
+  *                                 - \ref RTC_TAMPER_DEBOUNCE_DISABLE
+  *
+  *  @param[in]  u32Pair1Source     Dynamic Pair 1 Input Source Select
+  *                                 0: Pair 1 source select tamper 2
+  *                                 1: Pair 1 source select tamper 0
+  *
+  *  @param[in]  u32Pair2Source     Dynamic Pair 2 Input Source Select
+  *                                 0: Pair 2 source select tamper 4
+  *                                 1: Pair 2 source select tamper 0
+  *
+  * @return     None
+  *
+  * @details    This API is used to enable the dynamic tamper.
+  */
+void RTC_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32_t u32Pair1Source, uint32_t u32Pair2Source)
+{
+    uint32_t i;
+    uint32_t u32Reg;
+    uint32_t u32TmpReg;
+    uint32_t u32Tamper2Debounce, u32Tamper4Debounce;
+
+    u32Reg = RTC->TAMPCTL;
+    u32Reg &= ~(RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_TAMP2EN_Msk |
+                RTC_TAMPCTL_TAMP3EN_Msk | RTC_TAMPCTL_TAMP4EN_Msk | RTC_TAMPCTL_TAMP5EN_Msk);
+
+    u32Tamper2Debounce = u32Reg & RTC_TAMPCTL_TAMP2DBEN_Msk;
+    u32Tamper4Debounce = u32Reg & RTC_TAMPCTL_TAMP4DBEN_Msk;
+
+    u32Reg &= ~(RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_TAMP2EN_Msk |
+                RTC_TAMPCTL_TAMP3EN_Msk | RTC_TAMPCTL_TAMP4EN_Msk | RTC_TAMPCTL_TAMP5EN_Msk);
+    u32Reg &= ~(RTC_TAMPCTL_DYN1ISS_Msk | RTC_TAMPCTL_DYN2ISS_Msk);
+    u32Reg |= ((u32Pair1Source & 0x1UL) << RTC_TAMPCTL_DYN1ISS_Pos) | ((u32Pair2Source & 0x1UL) << RTC_TAMPCTL_DYN2ISS_Pos);
+
+    if(u32DebounceEn)
+    {
+        u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk |
+                     RTC_TAMPCTL_TAMP0DBEN_Msk | RTC_TAMPCTL_TAMP1DBEN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk);
+    }
+    else
+    {
+        u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk);
+    }
+
+    for(i = 0UL; i < (uint32_t)RTC_MAX_PAIR_NUM; i++)
+    {
+        if(u32PairSel & (0x1UL << i))
+        {
+            u32Reg &= ~((RTC_TAMPCTL_TAMP0DBEN_Msk | RTC_TAMPCTL_TAMP1DBEN_Msk) << (i * 8UL));
+            u32Reg |= (u32TmpReg << (i * 8UL));
+        }
+    }
+
+    if((u32Pair1Source) && (u32PairSel & (uint32_t)RTC_PAIR1_SELECT))
+    {
+        u32Reg &= ~RTC_TAMPCTL_TAMP2EN_Msk;
+        u32Reg |= u32Tamper2Debounce;
+    }
+
+    if((u32Pair2Source) && (u32PairSel & (uint32_t)RTC_PAIR2_SELECT))
+    {
+        u32Reg &= ~RTC_TAMPCTL_TAMP4EN_Msk;
+        u32Reg |= u32Tamper4Debounce;
+    }
+
+    RTC->TAMPCTL = u32Reg;
+}
+
+/**
+  * @brief      Dynamic Tamper Disable
+  *
+  * @param[in]  u32PairSel          Tamper pin detection enable. Possible options are
+  *                                 - \ref RTC_PAIR0_SELECT
+  *                                 - \ref RTC_PAIR1_SELECT
+  *                                 - \ref RTC_PAIR2_SELECT
+  *
+  * @return     None
+  *
+  * @details    This API is used to disable the dynamic tamper.
+  */
+void RTC_DynamicTamperDisable(uint32_t u32PairSel)
+{
+    uint32_t i;
+    uint32_t u32Reg;
+    uint32_t u32TmpReg;
+    uint32_t u32Tamper2En = 0UL, u32Tamper4En = 0UL;
+
+    u32Reg = RTC->TAMPCTL;
+
+    if((u32Reg & (uint32_t)RTC_TAMPCTL_DYN1ISS_Msk) && (u32PairSel & (uint32_t)RTC_PAIR1_SELECT))
+    {
+        u32Tamper2En = u32Reg & RTC_TAMPCTL_TAMP2EN_Msk;
+    }
+
+    if((u32Reg & (uint32_t)RTC_TAMPCTL_DYN2ISS_Msk) && (u32PairSel & (uint32_t)RTC_PAIR2_SELECT))
+    {
+        u32Tamper4En = u32Reg & RTC_TAMPCTL_TAMP4EN_Msk;
+    }
+
+    u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk);
+
+    for(i = 0UL; i < (uint32_t)RTC_MAX_PAIR_NUM; i++)
+    {
+        if(u32PairSel & (0x1UL << i))
+        {
+            u32Reg &= ~(u32TmpReg << ((i * 8UL)));
+        }
+    }
+
+    u32Reg |= (u32Tamper2En | u32Tamper4En);
+
+    RTC->TAMPCTL = u32Reg;
+}
+
+/**
+  * @brief      Config Dynamic Tamper
+  *
+  * @param[in]  u32ChangeRate       The dynamic tamper output change rate
+  *                                 - \ref RTC_2POW10_CLK
+  *                                 - \ref RTC_2POW11_CLK
+  *                                 - \ref RTC_2POW12_CLK
+  *                                 - \ref RTC_2POW13_CLK
+  *                                 - \ref RTC_2POW14_CLK
+  *                                 - \ref RTC_2POW15_CLK
+  *                                 - \ref RTC_2POW16_CLK
+  *                                 - \ref RTC_2POW17_CLK
+  *
+  * @param[in]  u32SeedReload       Reload new seed or not
+  *                                 0: not reload new seed
+  *                                 1: reload new seed
+  *
+  * @param[in]  u32RefPattern       Reference pattern
+  *                                 - \ref RTC_REF_RANDOM_PATTERN
+  *                                 - \ref RTC_REF_SEED_VALUE
+  *
+  * @param[in]  u32Seed             Seed Value (0x0 ~ 0xFFFFFFFF)
+  *
+  * @return     None
+  *
+  * @details    This API is used to config dynamic tamper setting.
+  */
+void RTC_DynamicTamperConfig(uint32_t u32ChangeRate, uint32_t u32SeedReload, uint32_t u32RefPattern, uint32_t u32Seed)
+{
+    uint32_t u32Reg;
+
+    u32Reg = RTC->TAMPCTL;
+
+    u32Reg &= ~(RTC_TAMPCTL_DYNSRC_Msk | RTC_TAMPCTL_SEEDRLD_Msk | RTC_TAMPCTL_DYNRATE_Msk);
+
+    u32Reg |= (u32ChangeRate) | ((u32SeedReload & 0x1UL) << RTC_TAMPCTL_SEEDRLD_Pos) |
+              (u32RefPattern << RTC_TAMPCTL_DYNSRC_Pos);
+
+    RTC->TAMPSEED = u32Seed; /* need set seed value before re-loade seed */
+    RTC->TAMPCTL = u32Reg;
+}
+
+/**
+  * @brief      Set RTC Clock Source
+  *
+  * @param[in]  u32ClkSrc       u32ClkSrc is the RTC clock source. It could be
+  *                             - \ref RTC_CLOCK_SOURCE_LXT
+  *                             - \ref RTC_CLOCK_SOURCE_LIRC
+  *                             - \ref RTC_CLOCK_SOURCE_LIRC32K
+  *
+  * @retval     RTC_CLOCK_SOURCE_LXT
+  * @retval     RTC_CLOCK_SOURCE_LIRC
+  * @retval     RTC_CLOCK_SOURCE_LIRC32K
+  *
+  * @details    This API is used to get the setting of RTC clock source.
+  *             User must to enable the selected clock source by themselves executing perform this API.
+  */
+uint32_t RTC_SetClockSource(uint32_t u32ClkSrc)
+{
+    uint32_t u32TrimDefault = inpw(SYS_BASE + 0x14Cul);
+
+    if(u32ClkSrc == RTC_CLOCK_SOURCE_LXT)
+    {
+        /* RTC clock source is external LXT */
+        RTC->LXTCTL &= ~RTC_LXTCTL_RTCCKSEL_Msk;
+        RTC->LXTCTL &= ~RTC_LXTCTL_C32KSEL_Msk;
+
+        return RTC_CLOCK_SOURCE_LXT;
+    }
+    else if(u32ClkSrc == RTC_CLOCK_SOURCE_LIRC32K)
+    {
+        /* Load LIRC32 trim setting */
+        RTC->LXTCTL = ((RTC->LXTCTL & ~(0x1FFul << 16)) | ((u32TrimDefault & 0x1FFul) << 16));
+
+        /* RTC clock source is LIRC32K */
+        RTC->LXTCTL |= RTC_LXTCTL_LIRC32KEN_Msk;
+        RTC->LXTCTL &= ~RTC_LXTCTL_RTCCKSEL_Msk;
+        RTC->LXTCTL |= RTC_LXTCTL_C32KSEL_Msk;
+
+        return RTC_CLOCK_SOURCE_LIRC32K;
+    }
+    else if(u32ClkSrc == RTC_CLOCK_SOURCE_LIRC)
+    {
+        /* RTC clock source is LIRC */
+        RTC->LXTCTL |= RTC_LXTCTL_RTCCKSEL_Msk;
+
+        return RTC_CLOCK_SOURCE_LIRC;
+    }
+    else
+    {
+        /* Set the default RTC clock source is LIRC */
+        RTC->LXTCTL |= RTC_LXTCTL_RTCCKSEL_Msk;
+
+        return RTC_CLOCK_SOURCE_LIRC;
+    }
+}
+
+/**
+ * @brief       Set RTC GPIO Operation Mode
+ *
+ * @param[in]   u32Pin          The single pin of GPIO-F port.
+ *                              It could be 4~11, which means PF.4~PF.11.
+ * @param[in]   u32Mode         Operation mode. It could be
+ *                              - \ref RTC_IO_MODE_INPUT
+ *                              - \ref RTC_IO_MODE_OUTPUT
+ *                              - \ref RTC_IO_MODE_OPEN_DRAIN
+ *                              - \ref RTC_IO_MODE_QUASI
+ * @param[in]   u32DigitalCtl   The digital input path control of specified pin. It could be
+ *                              - \ref RTC_IO_DIGITAL_ENABLE
+ *                              - \ref RTC_IO_DIGITAL_DISABLE
+ * @param[in]   u32PullCtl      The pull-up or pull-down control of specified pin. It could be
+ *                              - \ref RTC_IO_PULL_UP_DOWN_DISABLE
+ *                              - \ref RTC_IO_PULL_UP_ENABLE
+ *                              - \ref RTC_IO_PULL_DOWN_ENABLE
+ * @param[in]   u32OutputLevel  The I/O output level. 0: output low; 1: output high.
+ *
+ * @return      None
+ *
+ * @details     This function is used to set specified GPIO operation mode controlled by RTC module.
+ */
+void RTC_SetGPIOMode(uint32_t u32PFPin, uint32_t u32Mode, uint32_t u32DigitalCtl, uint32_t u32PullCtl, uint32_t u32OutputLevel)
+{
+    uint32_t u32Offset;
+
+    if((u32PFPin == 4) || (u32PFPin == 5) || (u32PFPin == 6) || (u32PFPin == 7))
+    {
+        u32Offset = u32PFPin - 4;
+
+        RTC_SET_IOCTL_BY_RTC(RTC);
+
+        RTC->GPIOCTL0 = (RTC->GPIOCTL0 & ~(0x3FUL << (u32Offset * 8))) |
+                        (u32Mode << (u32Offset * 8)) |
+                        (u32OutputLevel << ((u32Offset * 8) + 2)) |
+                        (u32DigitalCtl << ((u32Offset * 8) + 3)) |
+                        (u32PullCtl << ((u32Offset * 8) + 4));
+    }
+
+    if((u32PFPin == 8) || (u32PFPin == 9) || (u32PFPin == 10) || (u32PFPin == 11))
+    {
+        u32Offset = u32PFPin - 8;
+
+        RTC_SET_IOCTL_BY_RTC(RTC);
+
+        RTC->GPIOCTL1 = (RTC->GPIOCTL1 & ~(0x3FUL << (u32Offset * 8))) |
+                        (u32Mode << (u32Offset * 8)) |
+                        (u32OutputLevel << ((u32Offset * 8) + 2)) |
+                        (u32DigitalCtl << ((u32Offset * 8) + 3)) |
+                        (u32PullCtl << ((u32Offset * 8) + 4));
+    }
+}
+
+/**
+ * @brief       Set RTC GPIO Output Level
+ *
+ * @param[in]   u32Pin          The single pin of GPIO-F port.
+ *                              It could be 4~11, which means PF.4~PF.11.
+ * @param[in]   u32OutputLevel  The I/O output level. 0: output low; 1: output high.
+ *
+ * @return      None
+ *
+ * @details     This function is used to set GPIO output level by RTC module.
+ */
+void RTC_SetGPIOLevel(uint32_t u32PFPin, uint32_t u32OutputLevel)
+{
+    uint32_t u32Offset;
+
+    if((u32PFPin == 4) || (u32PFPin == 5) || (u32PFPin == 6) || (u32PFPin == 7))
+    {
+        u32Offset = u32PFPin - 4;
+
+        RTC->GPIOCTL0 = (RTC->GPIOCTL0 & ~(0x4UL << (u32Offset * 8))) |
+                        (u32OutputLevel << ((u32Offset * 8) + 2));
+    }
+
+    if((u32PFPin == 8) || (u32PFPin == 9) || (u32PFPin == 10) || (u32PFPin == 11))
+    {
+        u32Offset = u32PFPin - 8;
+
+        RTC->GPIOCTL1 = (RTC->GPIOCTL1 & ~(0x4UL << (u32Offset * 8))) |
+                        (u32OutputLevel << ((u32Offset * 8) + 2));
+    }
+}
+
+/**@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group RTC_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_sc.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_sc.c
new file mode 100644
index 0000000000..285fedcc8c
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_sc.c
@@ -0,0 +1,425 @@
+/**************************************************************************//**
+ * @file     sc.c
+ * @version  V3.00
+ * @brief    Smartcard(SC) driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+
+
+/* Below are variables used locally by SC driver and does not want to parse by doxygen unless HIDDEN_SYMBOLS is defined */
+/** @cond HIDDEN_SYMBOLS */
+static uint32_t g_u32CardStateIgnore[SC_INTERFACE_NUM] = {0UL, 0UL, 0UL};
+
+/** @endcond HIDDEN_SYMBOLS */
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup SC_Driver SC Driver
+  @{
+*/
+
+/** @addtogroup SC_EXPORTED_FUNCTIONS SC Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Indicates specified smartcard slot status
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  *
+  * @return     Card insert status
+  * @retval     TRUE    Card insert
+  * @retval     FALSE   Card remove
+  *
+  * @details    This function is used to check if specified smartcard slot is presented.
+  */
+uint32_t SC_IsCardInserted(SC_T *sc)
+{
+    uint32_t u32Ret;
+
+    /* put conditions into two variable to remove IAR compilation warning */
+    uint32_t cond1 = ((sc->STATUS & SC_STATUS_CDPINSTS_Msk) >> SC_STATUS_CDPINSTS_Pos);
+    uint32_t cond2 = ((sc->CTL & SC_CTL_CDLV_Msk) >> SC_CTL_CDLV_Pos);
+
+    if(((sc == SC0) || (sc == SC0_NS)) && (g_u32CardStateIgnore[0] == 1UL))
+    {
+        u32Ret = (uint32_t)TRUE;
+    }
+    else if(((sc == SC1) || (sc == SC1_NS)) && (g_u32CardStateIgnore[1] == 1UL))
+    {
+        u32Ret = (uint32_t)TRUE;
+    }
+    else if(((sc == SC2) || (sc == SC2_NS)) && (g_u32CardStateIgnore[2] == 1UL))
+    {
+        u32Ret = (uint32_t)TRUE;
+    }
+    else if(cond1 != cond2)
+    {
+        u32Ret = (uint32_t)FALSE;
+    }
+    else
+    {
+        u32Ret = (uint32_t)TRUE;
+    }
+
+    return u32Ret;
+}
+
+/*
+  * @brief      Reset the Tx and Rx FIFO of smartcard module
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  *
+  * @return     None
+  *
+  * @details    This function reset both transmit and receive FIFO of specified smartcard module.
+  */
+void SC_ClearFIFO(SC_T *sc)
+{
+    while((sc->ALTCTL & SC_ALTCTL_SYNC_Msk) == SC_ALTCTL_SYNC_Msk) {}
+    sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk);
+}
+
+/**
+  * @brief      Disable specified smartcard module
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  *
+  * @return     None
+  *
+  * @details    This function disable specified smartcard module, and force all transition to IDLE state.
+  */
+void SC_Close(SC_T *sc)
+{
+    sc->INTEN = 0UL;
+
+    while((sc->PINCTL & SC_PINCTL_SYNC_Msk) == SC_PINCTL_SYNC_Msk) {}
+    sc->PINCTL = 0UL;
+    sc->ALTCTL = 0UL;
+
+    while((sc->CTL & SC_CTL_SYNC_Msk) == SC_CTL_SYNC_Msk) {}
+    sc->CTL = 0UL;
+}
+
+/**
+  * @brief      Initialized smartcard module
+  *
+  * @param[in]  sc          The pointer of smartcard module.
+  * @param[in]  u32CardDet  Card detect polarity, select the SC_CD pin state which indicates card absent. Could be:
+  *                         -\ref SC_PIN_STATE_HIGH
+  *                         -\ref SC_PIN_STATE_LOW
+  *                         -\ref SC_PIN_STATE_IGNORE, no card detect pin, always assumes card present.
+  * @param[in]  u32PWR      Power off polarity, select the SC_PWR pin state which could set smartcard VCC to high level. Could be:
+  *                         -\ref SC_PIN_STATE_HIGH
+  *                         -\ref SC_PIN_STATE_LOW
+  *
+  * @return     None
+  *
+  * @details    This function initialized smartcard module.
+  */
+void SC_Open(SC_T *sc, uint32_t u32CardDet, uint32_t u32PWR)
+{
+    uint32_t u32Reg = 0UL, u32Intf;
+
+    if((sc == SC0) || (sc == SC0_NS))
+    {
+        u32Intf = 0UL;
+    }
+    else if((sc == SC1) || (sc == SC1_NS))
+    {
+        u32Intf = 1UL;
+    }
+    else
+    {
+        u32Intf = 2UL;
+    }
+
+    if(u32CardDet != SC_PIN_STATE_IGNORE)
+    {
+        u32Reg = u32CardDet ? 0UL : SC_CTL_CDLV_Msk;
+        g_u32CardStateIgnore[u32Intf] = 0UL;
+    }
+    else
+    {
+        g_u32CardStateIgnore[u32Intf] = 1UL;
+    }
+    sc->PINCTL = u32PWR ? 0UL : SC_PINCTL_PWRINV_Msk;
+
+    while((sc->CTL & SC_CTL_SYNC_Msk) == SC_CTL_SYNC_Msk) {}
+    sc->CTL = SC_CTL_SCEN_Msk | SC_CTL_TMRSEL_Msk | u32Reg;
+}
+
+/**
+  * @brief      Reset specified smartcard module
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  *
+  * @return     None
+  *
+  * @details    This function reset specified smartcard module to its default state for activate smartcard.
+  */
+void SC_ResetReader(SC_T *sc)
+{
+    uint32_t u32Intf;
+
+    if((sc == SC0) || (sc == SC0_NS))
+    {
+        u32Intf = 0UL;
+    }
+    else if((sc == SC1) || (sc == SC1_NS))
+    {
+        u32Intf = 1UL;
+    }
+    else
+    {
+        u32Intf = 2UL;
+    }
+
+    /* Reset FIFO, enable auto de-activation while card removal */
+    sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk | SC_ALTCTL_ADACEN_Msk);
+    /* Set Rx trigger level to 1 character, longest card detect debounce period, disable error retry (EMV ATR does not use error retry) */
+    while((sc->CTL & SC_CTL_SYNC_Msk) == SC_CTL_SYNC_Msk) {}
+    sc->CTL &= ~(SC_CTL_RXTRGLV_Msk |
+                 SC_CTL_CDDBSEL_Msk |
+                 SC_CTL_TXRTY_Msk |
+                 SC_CTL_TXRTYEN_Msk |
+                 SC_CTL_RXRTY_Msk |
+                 SC_CTL_RXRTYEN_Msk);
+    while((sc->CTL & SC_CTL_SYNC_Msk) == SC_CTL_SYNC_Msk) {}
+    /* Enable auto convention, and all three smartcard internal timers */
+    sc->CTL |= SC_CTL_AUTOCEN_Msk | SC_CTL_TMRSEL_Msk;
+    /* Disable Rx timeout */
+    sc->RXTOUT = 0UL;
+    /* 372 clocks per ETU by default */
+    sc->ETUCTL = 371UL;
+
+    /* Enable necessary interrupt for smartcard operation */
+    if(g_u32CardStateIgnore[u32Intf])   /* Do not enable card detect interrupt if card present state ignore */
+    {
+        sc->INTEN = (SC_INTEN_RDAIEN_Msk |
+                     SC_INTEN_TERRIEN_Msk |
+                     SC_INTEN_TMR0IEN_Msk |
+                     SC_INTEN_TMR1IEN_Msk |
+                     SC_INTEN_TMR2IEN_Msk |
+                     SC_INTEN_BGTIEN_Msk |
+                     SC_INTEN_ACERRIEN_Msk);
+    }
+    else
+    {
+        sc->INTEN = (SC_INTEN_RDAIEN_Msk |
+                     SC_INTEN_TERRIEN_Msk |
+                     SC_INTEN_TMR0IEN_Msk |
+                     SC_INTEN_TMR1IEN_Msk |
+                     SC_INTEN_TMR2IEN_Msk |
+                     SC_INTEN_BGTIEN_Msk |
+                     SC_INTEN_ACERRIEN_Msk |
+                     SC_INTEN_CDIEN_Msk);
+    }
+
+    return;
+}
+
+/**
+  * @brief      Set Block Guard Time (BGT)
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  * @param[in]  u32BGT  Block guard time using ETU as unit, valid range are between 1 ~ 32.
+  *
+  * @return     None
+  *
+  * @details    This function is used to configure block guard time (BGT) of specified smartcard module.
+  */
+void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT)
+{
+    sc->CTL = (sc->CTL & ~SC_CTL_BGT_Msk) | ((u32BGT - 1UL) << SC_CTL_BGT_Pos);
+}
+
+/**
+  * @brief      Set Character Guard Time (CGT)
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  * @param[in]  u32CGT  Character guard time using ETU as unit, valid range are between 11 ~ 267.
+  *
+  * @return     None
+  *
+  * @details    This function is used to configure character guard time (CGT) of specified smartcard module.
+  * @note       Before using this API, user should set the correct stop bit length first.
+  */
+void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT)
+{
+    /* CGT is "START bit" + "8-bits" + "Parity bit" + "STOP bit(s)" + "EGT counts" */
+    u32CGT -= ((sc->CTL & SC_CTL_NSB_Msk) == SC_CTL_NSB_Msk) ? 11UL : 12UL;
+    sc->EGT = u32CGT;
+}
+
+/**
+  * @brief      Stop all smartcard timer
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  *
+  * @return     None
+  *
+  * @note       This function stop the timers within specified smartcard module, \b not timer module.
+  */
+void SC_StopAllTimer(SC_T *sc)
+{
+    while((sc->ALTCTL & SC_ALTCTL_SYNC_Msk) == SC_ALTCTL_SYNC_Msk) {}
+    sc->ALTCTL &= ~(SC_ALTCTL_CNTEN0_Msk | SC_ALTCTL_CNTEN1_Msk | SC_ALTCTL_CNTEN2_Msk);
+}
+
+/**
+  * @brief      Configure and start smartcard timer
+  *
+  * @param[in]  sc          The pointer of smartcard module.
+  * @param[in] u32TimerNum  Timer to start. Valid values are 0, 1, 2.
+  * @param[in]  u32Mode     Timer operating mode, valid values are:
+  *                             - \ref SC_TMR_MODE_0
+  *                             - \ref SC_TMR_MODE_1
+  *                             - \ref SC_TMR_MODE_2
+  *                             - \ref SC_TMR_MODE_3
+  *                             - \ref SC_TMR_MODE_4
+  *                             - \ref SC_TMR_MODE_5
+  *                             - \ref SC_TMR_MODE_6
+  *                             - \ref SC_TMR_MODE_7
+  *                             - \ref SC_TMR_MODE_8
+  *                             - \ref SC_TMR_MODE_F
+  * @param[in]  u32ETUCount Timer timeout duration, ETU based. For timer 0, valid  range are between 1 ~ 0x1000000 ETUs.
+  *                         For timer 1 and timer 2, valid range are between 1 ~ 0x100 ETUs.
+  *
+  * @return     None
+  *
+  * @note       This function start the timer within specified smartcard module, \b not timer module.
+  * @note       Depend on the timer operating mode, timer may not start counting immediately and starts when condition match.
+  */
+void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount)
+{
+    uint32_t u32Reg = u32Mode | (SC_TMRCTL0_CNT_Msk & (u32ETUCount - 1UL));
+    while((sc->ALTCTL & SC_ALTCTL_SYNC_Msk) == SC_ALTCTL_SYNC_Msk) {}
+    if(u32TimerNum == 0UL)
+    {
+        while((sc->TMRCTL0 & SC_TMRCTL0_SYNC_Msk) == SC_TMRCTL0_SYNC_Msk) {}
+        sc->TMRCTL0 = u32Reg;
+        sc->ALTCTL |= SC_ALTCTL_CNTEN0_Msk;
+    }
+    else if(u32TimerNum == 1UL)
+    {
+        while((sc->TMRCTL1 & SC_TMRCTL1_SYNC_Msk) == SC_TMRCTL1_SYNC_Msk) {}
+        sc->TMRCTL1 = u32Reg;
+        sc->ALTCTL |= SC_ALTCTL_CNTEN1_Msk;
+    }
+    else       /* timer 2 */
+    {
+        while((sc->TMRCTL2 & SC_TMRCTL2_SYNC_Msk) == SC_TMRCTL2_SYNC_Msk) {}
+        sc->TMRCTL2 = u32Reg;
+        sc->ALTCTL |= SC_ALTCTL_CNTEN2_Msk;
+    }
+}
+
+/**
+  * @brief      Stop a smartcard timer
+  *
+  * @param[in]  sc          The pointer of smartcard module.
+  * @param[in] u32TimerNum  Timer to stop. Valid values are 0, 1, 2.
+  *
+  * @return     None
+  *
+  * @note       This function stop the timer within specified smartcard module, \b not timer module.
+  */
+void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum)
+{
+    while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk) {}
+
+    if(u32TimerNum == 0UL)      /* timer 0 */
+    {
+        sc->ALTCTL &= ~SC_ALTCTL_CNTEN0_Msk;
+    }
+    else if(u32TimerNum == 1UL) /* timer 1 */
+    {
+        sc->ALTCTL &= ~SC_ALTCTL_CNTEN1_Msk;
+    }
+    else                        /* timer 2 */
+    {
+        sc->ALTCTL &= ~SC_ALTCTL_CNTEN2_Msk;
+    }
+}
+
+/**
+  * @brief      Get smartcard clock frequency
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  *
+  * @return     Smartcard frequency in kHZ
+  *
+  * @details    This function is used to get specified smartcard module clock frequency in kHz.
+  */
+uint32_t SC_GetInterfaceClock(SC_T *sc)
+{
+    uint32_t u32ClkSrc = 0, u32Num = 0, u32ClkFreq = __HIRC, u32Div = 0;
+
+    /* Get smartcard module clock source and divider */
+    if((sc == SC0) || (sc == SC0_NS))
+    {
+        u32Num = 0UL;
+        u32ClkSrc = CLK_GetModuleClockSource(SC0_MODULE);
+        u32Div = CLK_GetModuleClockDivider(SC0_MODULE);
+    }
+    else if((sc == SC1) || (sc == SC1_NS))
+    {
+        u32Num = 1UL;
+        u32ClkSrc = CLK_GetModuleClockSource(SC1_MODULE);
+        u32Div = CLK_GetModuleClockDivider(SC1_MODULE);
+    }
+    else if((sc == SC2) || (sc == SC2_NS))
+    {
+        u32Num = 2UL;
+        u32ClkSrc = CLK_GetModuleClockSource(SC2_MODULE);
+        u32Div = CLK_GetModuleClockDivider(SC2_MODULE);
+    }
+    else
+    {
+        u32ClkFreq = 0UL;
+    }
+
+    if(u32ClkFreq != 0UL)
+    {
+        /* Get smartcard module clock */
+        if(u32ClkSrc == 0UL)
+        {
+            u32ClkFreq = __HXT;
+        }
+        else if(u32ClkSrc == 1UL)
+        {
+            u32ClkFreq = CLK_GetPLLClockFreq();
+        }
+        else if(u32ClkSrc == 2UL)
+        {
+            if(u32Num == 1UL)
+            {
+                u32ClkFreq = CLK_GetPCLK1Freq();
+            }
+            else
+            {
+                u32ClkFreq = CLK_GetPCLK0Freq();
+            }
+        }
+        else
+        {
+            u32ClkFreq = __HIRC;
+        }
+
+        u32ClkFreq /= (u32Div + 1UL) * 1000UL;
+    }
+
+    return u32ClkFreq;
+}
+
+/**@}*/ /* end of group SC_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group SC_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_scuart.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_scuart.c
new file mode 100644
index 0000000000..363ebdd6da
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_scuart.c
@@ -0,0 +1,272 @@
+/**************************************************************************//**
+ * @file     scuart.c
+ * @version  V3.00
+ * @brief    Smartcard UART mode (SCUART) driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup SCUART_Driver SCUART Driver
+  @{
+*/
+
+/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Disable smartcard interface
+  *
+  * @param      sc      The pointer of smartcard module.
+  *
+  * @return     None
+  *
+  * @details    The function is used to disable smartcard interface UART mode.
+  */
+void SCUART_Close(SC_T* sc)
+{
+    sc->INTEN = 0UL;
+    sc->UARTCTL = 0UL;
+    sc->CTL = 0UL;
+}
+
+/** @cond HIDDEN_SYMBOLS */
+/**
+  * @brief      Returns module clock of specified SC interface
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  *
+  * @return     Module clock of specified SC interface.
+  */
+static uint32_t SCUART_GetClock(SC_T *sc)
+{
+    uint32_t u32ClkSrc = 0, u32Num = 0, u32ClkFreq = __HIRC, u32Div = 0;
+
+    /* Get smartcard module clock source and divider */
+    if((sc == SC0) || (sc == SC0_NS))
+    {
+        u32Num = 0UL;
+        u32ClkSrc = CLK_GetModuleClockSource(SC0_MODULE);
+        u32Div = CLK_GetModuleClockDivider(SC0_MODULE);
+    }
+    else if((sc == SC1) || (sc == SC1_NS))
+    {
+        u32Num = 1UL;
+        u32ClkSrc = CLK_GetModuleClockSource(SC1_MODULE);
+        u32Div = CLK_GetModuleClockDivider(SC1_MODULE);
+    }
+    else if((sc == SC2) || (sc == SC2_NS))
+    {
+        u32Num = 2UL;
+        u32ClkSrc = CLK_GetModuleClockSource(SC2_MODULE);
+        u32Div = CLK_GetModuleClockDivider(SC2_MODULE);
+    }
+    else
+    {
+        u32ClkFreq = 0UL;
+    }
+
+    if(u32ClkFreq != 0UL)
+    {
+        /* Get smartcard module clock */
+        if(u32ClkSrc == 0UL)
+        {
+            u32ClkFreq = __HXT;
+        }
+        else if(u32ClkSrc == 1UL)
+        {
+            u32ClkFreq = CLK_GetPLLClockFreq();
+        }
+        else if(u32ClkSrc == 2UL)
+        {
+            if(u32Num == 1UL)
+            {
+                u32ClkFreq = CLK_GetPCLK1Freq();
+            }
+            else
+            {
+                u32ClkFreq = CLK_GetPCLK0Freq();
+            }
+        }
+        else
+        {
+            u32ClkFreq = __HIRC;
+        }
+
+        u32ClkFreq /= (u32Div + 1UL);
+    }
+
+    return u32ClkFreq;
+}
+/** @endcond HIDDEN_SYMBOLS */
+
+/**
+  * @brief      Enable smartcard module UART mode and set baudrate
+  *
+  * @param[in]  sc          The pointer of smartcard module.
+  * @param[in]  u32Baudrate Target baudrate of smartcard UART module.
+  *
+  * @return     Actual baudrate of smartcard UART mode
+  *
+  * @details    This function use to enable smartcard module UART mode and set baudrate.
+  *
+  * @note       This function configures character width to 8 bits, 1 stop bit, and no parity.
+  *             And can use \ref SCUART_SetLineConfig function to update these settings.
+  *             The baudrate clock source comes from SC_CLK/SC_DIV, where SC_CLK is controlled
+  *             by SCxSEL in CLKSEL3 register, SC_DIV is controlled by SCxDIV in CLKDIV1
+  *             register. Since the baudrate divider is 12-bit wide and must be larger than 4,
+  *             (clock source / baudrate) must be larger or equal to 5 and smaller or equal to
+  *             4096. Otherwise this function cannot configure SCUART to work with target baudrate.
+  */
+uint32_t SCUART_Open(SC_T* sc, uint32_t u32Baudrate)
+{
+    uint32_t u32ClkFreq = SCUART_GetClock(sc), u32Div;
+
+    /* Calculate divider for target baudrate */
+    u32Div = (u32ClkFreq + (u32Baudrate >> 1) - 1UL) / u32Baudrate - 1UL;
+
+    sc->CTL = SC_CTL_SCEN_Msk | SC_CTL_NSB_Msk;  /* Enable smartcard interface and stop bit = 1 */
+    sc->UARTCTL = SCUART_CHAR_LEN_8 | SCUART_PARITY_NONE | SC_UARTCTL_UARTEN_Msk; /* Enable UART mode, disable parity and 8 bit per character */
+    sc->ETUCTL = u32Div;
+
+    return (u32ClkFreq / (u32Div + 1UL));
+}
+
+/**
+  * @brief      Read Rx data from Rx FIFO
+  *
+  * @param[in]  sc              The pointer of smartcard module.
+  * @param[in]  pu8RxBuf        The buffer to store receive the data.
+  * @param[in] u32ReadBytes     Target number of characters to receive
+  *
+  * @return     Actual character number reads to buffer
+  *
+  * @details    The function is used to read data from Rx FIFO.
+  *
+  * @note       This function does not block and return immediately if there's no data available.
+  */
+uint32_t SCUART_Read(SC_T* sc, uint8_t pu8RxBuf[], uint32_t u32ReadBytes)
+{
+    uint32_t u32Count;
+
+    for(u32Count = 0UL; u32Count < u32ReadBytes; u32Count++)
+    {
+        if(SCUART_GET_RX_EMPTY(sc) == SC_STATUS_RXEMPTY_Msk)
+        {
+            /* No data available */
+            break;
+        }
+        /* Get data from FIFO */
+        pu8RxBuf[u32Count] = (uint8_t)SCUART_READ(sc);
+    }
+
+    return u32Count;
+}
+
+/**
+  * @brief      Configure smartcard UART mode line setting
+  *
+  * @param[in]  sc              The pointer of smartcard module.
+  * @param[in]  u32Baudrate     Target baudrate of smartcard UART mode. If this value is 0, SC UART baudrate will not change.
+  * @param[in]  u32DataWidth    The data length, could be:
+  *                                 - \ref SCUART_CHAR_LEN_5
+  *                                 - \ref SCUART_CHAR_LEN_6
+  *                                 - \ref SCUART_CHAR_LEN_7
+  *                                 - \ref SCUART_CHAR_LEN_8
+  * @param[in]  u32Parity       The parity setting, could be:
+  *                                 - \ref SCUART_PARITY_NONE
+  *                                 - \ref SCUART_PARITY_ODD
+  *                                  - \ref SCUART_PARITY_EVEN
+  * @param[in]  u32StopBits     The stop bit length, could be:
+  *                                 - \ref SCUART_STOP_BIT_1
+  *                                 - \ref SCUART_STOP_BIT_2
+  *
+  * @return     Actual baudrate of smartcard UART mode
+  *
+  * @details    The baudrate clock source comes from SC_CLK/SC_DIV, where SC_CLK is controlled
+  *             by SCxSEL in CLKSEL3 register, SC_DIV is controlled by SCxDIV in CLKDIV1
+  *             register. Since the baudrate divider is 12-bit wide and must be larger than 4,
+  *             (clock source / baudrate) must be larger or equal to 5 and smaller or equal to
+  *             4096. Otherwise this function cannot configure SCUART to work with target baudrate.
+  */
+uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits)
+{
+    uint32_t u32ClkFreq = SCUART_GetClock(sc), u32Div;
+
+    if(u32Baudrate == 0UL)
+    {
+        /* Keep original baudrate setting */
+        u32Div = sc->ETUCTL & SC_ETUCTL_ETURDIV_Msk;
+    }
+    else
+    {
+        /* Calculate divider for target baudrate */
+        u32Div = ((u32ClkFreq + (u32Baudrate >> 1) - 1UL) / u32Baudrate) - 1UL;
+        sc->ETUCTL = u32Div;
+    }
+
+    sc->CTL = u32StopBits | SC_CTL_SCEN_Msk;  /* Set stop bit */
+    sc->UARTCTL = u32Parity | u32DataWidth | SC_UARTCTL_UARTEN_Msk;  /* Set character width and parity */
+
+    return (u32ClkFreq / (u32Div + 1UL));
+}
+
+/**
+  * @brief      Set receive timeout count
+  *
+  * @param[in]  sc      The pointer of smartcard module.
+  * @param[in]  u32TOC  Rx time-out counter, using baudrate as counter unit. Valid range are 0~0x1FF,
+  *                     set this value to 0 will disable time-out counter.
+  *
+  * @return     None
+  *
+  * @details    The time-out counter resets and starts counting whenever the Rx buffer received a
+  *             new data word. Once the counter decrease to 1 and no new data is received or CPU
+  *             does not read any data from FIFO, a receiver time-out interrupt will be generated.
+  */
+void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC)
+{
+    sc->RXTOUT = u32TOC;
+}
+
+/**
+  * @brief      Write data into transmit FIFO to send data out
+  *
+  * @param[in]  sc              The pointer of smartcard module.
+  * @param[in]  pu8TxBuf        The buffer containing data to send to transmit FIFO.
+  * @param[in]  u32WriteBytes   Number of data to send.
+  *
+  * @return     None
+  *
+  * @details    This function is used to write data into Tx FIFO to send data out.
+  *
+  * @note       This function blocks until all data write into FIFO.
+  */
+void SCUART_Write(SC_T* sc, uint8_t pu8TxBuf[], uint32_t u32WriteBytes)
+{
+    uint32_t u32Count;
+
+    for(u32Count = 0UL; u32Count != u32WriteBytes; u32Count++)
+    {
+        /* Wait 'til FIFO not full */
+        while(SCUART_GET_TX_FULL(sc) == SC_STATUS_TXFULL_Msk) {}
+
+        /* Write 1 byte to FIFO */
+        sc->DAT = pu8TxBuf[u32Count];  /* Write 1 byte to FIFO */
+    }
+}
+
+
+/**@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group SCUART_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_sdh.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_sdh.c
new file mode 100644
index 0000000000..75102b603f
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_sdh.c
@@ -0,0 +1,1137 @@
+/**************************************************************************//**
+ * @file     sdh.c
+ * @version  V1.00
+ * @brief    M2354 SDH driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include 
+#include 
+#include 
+#include "NuMicro.h"
+
+#if defined (__ICCARM__)
+# pragma diag_suppress=Pm073, Pm143        /* Misra C 2004 rule 14.7 */
+#endif
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup SDH_Driver SDH Driver
+  @{
+*/
+
+/** @addtogroup SDH_EXPORTED_FUNCTIONS SDH Exported Functions
+  @{
+*/
+
+#define SDH_BLOCK_SIZE   512UL
+
+/* #define DEBUG_PRINTF printf */
+#define DEBUG_PRINTF(...)
+
+/** @cond HIDDEN_SYMBOLS */
+
+/* global variables */
+/* For response R3 (such as ACMD41, CRC-7 is invalid; but SD controller will still */
+/* calculate CRC-7 and get an error result, software should ignore this error and clear SDISR [CRC_IF] flag */
+/* _sd_uR3_CMD is the flag for it. 1 means software should ignore CRC-7 error */
+uint8_t g_u8R3Flag = 0UL;
+uint8_t volatile g_u8SDDataReadyFlag = (uint8_t)FALSE;
+
+static uint32_t _SDH_uR7_CMD = 0UL;
+static uint32_t _SDH_ReferenceClock;
+
+#if defined ( __ICCARM__ ) /*!< IAR Compiler */
+#pragma data_alignment = 4
+static uint8_t _SDH_ucSDHCBuffer[512];
+#else
+static __attribute__((aligned)) uint8_t _SDH_ucSDHCBuffer[512];
+#endif
+
+/* Declare these functions here to avoid MISRA C 2004 rule 8.1 error */
+void SDH_CheckRB(SDH_T *sdh);
+uint32_t SDH_SDCommand(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg);
+uint32_t SDH_SDCmdAndRsp(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg, uint32_t u32TickCount);
+uint32_t SDH_Swap32(uint32_t u32Val);
+uint32_t SDH_SDCmdAndRsp2(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg, uint32_t pu32R2ptr[]);
+uint32_t SDH_SDCmdAndRspDataIn(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg);
+void SDH_Set_clock(SDH_T *sdh, uint32_t u32SDClockKhz);
+uint32_t SDH_CardDetection(SDH_T *sdh);
+uint32_t SDH_Init(SDH_T *sdh);
+uint32_t SDH_SwitchToHighSpeed(SDH_T *sdh, SDH_INFO_T *pSD);
+uint32_t SDH_SelectCardType(SDH_T *sdh);
+void SDH_Get_SD_info(SDH_T *sdh);
+
+SDH_INFO_T SD0;
+
+void SDH_CheckRB(SDH_T *sdh)
+{
+    while(1)
+    {
+        sdh->CTL |= SDH_CTL_CLK8OEN_Msk;
+        while(sdh->CTL & SDH_CTL_CLK8OEN_Msk) {}
+        if(sdh->INTSTS & SDH_INTSTS_DAT0STS_Msk)
+        {
+            break;
+        }
+    }
+}
+
+
+uint32_t SDH_SDCommand(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg)
+{
+    SDH_INFO_T *pSD;
+    volatile uint32_t u32Status = Successful;
+
+    /* M2354 is only support SDH0 */
+    pSD = &SD0;
+
+    sdh->CMDARG = u32Arg;
+    sdh->CTL = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | (u32Cmd << 8) | (SDH_CTL_COEN_Msk);
+
+    while(sdh->CTL & SDH_CTL_COEN_Msk)
+    {
+        if(pSD->IsCardInsert == (uint32_t)FALSE)
+        {
+            u32Status = SDH_NO_SD_CARD;
+        }
+    }
+    return u32Status;
+}
+
+
+uint32_t SDH_SDCmdAndRsp(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg, uint32_t u32TickCount)
+{
+    SDH_INFO_T *pSD;
+
+    /* M2354 is only support SDH0 */
+    pSD = &SD0;
+
+    sdh->CMDARG = u32Arg;
+    sdh->CTL = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | (u32Cmd << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk);
+
+    if(u32TickCount > 0UL)
+    {
+        while(sdh->CTL & SDH_CTL_RIEN_Msk)
+        {
+            if(u32TickCount-- == 0UL)
+            {
+                sdh->CTL |= SDH_CTL_CTLRST_Msk; /* reset SD engine */
+                return 2UL;
+            }
+            if(pSD->IsCardInsert == (uint8_t)FALSE)
+            {
+                return SDH_NO_SD_CARD;
+            }
+        }
+    }
+    else
+    {
+        while(sdh->CTL & SDH_CTL_RIEN_Msk)
+        {
+            if(pSD->IsCardInsert == (uint8_t)FALSE)
+            {
+                return SDH_NO_SD_CARD;
+            }
+        }
+    }
+
+    if(_SDH_uR7_CMD)
+    {
+        if((sdh->RESP1 & 0xffUL) != 0x55UL)
+        {
+            if((sdh->RESP0 & 0xfUL) != 0x01UL)
+            {
+                _SDH_uR7_CMD = 0UL;
+                return SDH_CMD8_ERROR;
+            }
+        }
+    }
+
+    if(!g_u8R3Flag)
+    {
+        if(sdh->INTSTS & SDH_INTSTS_CRC7_Msk)      /* check CRC7 */
+        {
+            return Successful;
+        }
+        else
+        {
+            return SDH_CRC7_ERROR;
+        }
+    }
+    else     /* ignore CRC error for R3 case */
+    {
+        g_u8R3Flag = 0UL;
+        sdh->INTSTS = SDH_INTSTS_CRCIF_Msk;
+        return Successful;
+    }
+}
+
+
+uint32_t SDH_Swap32(uint32_t u32Val)
+{
+    uint32_t u32Buf;
+
+    u32Buf = u32Val;
+    u32Val <<= 24;
+    u32Val |= (u32Buf << 8) & 0xff0000UL;
+    u32Val |= (u32Buf >> 8) & 0xff00UL;
+    u32Val |= (u32Buf >> 24) & 0xffUL;
+    return u32Val;
+}
+
+/* Get 16 bytes CID or CSD */
+uint32_t SDH_SDCmdAndRsp2(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg, uint32_t pu32R2ptr[])
+{
+    uint32_t i;
+    uint32_t au32TmpBuf[5];
+    SDH_INFO_T *pSD;
+
+    /* M2354 is only support SDH0 */
+    pSD = &SD0;
+
+    sdh->CMDARG = u32Arg;
+    sdh->CTL = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | (u32Cmd << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_R2EN_Msk);
+
+    while(sdh->CTL & SDH_CTL_R2EN_Msk)
+    {
+        if(pSD->IsCardInsert == (uint8_t)FALSE)
+        {
+            return SDH_NO_SD_CARD;
+        }
+    }
+
+    if(sdh->INTSTS & SDH_INTSTS_CRC7_Msk)
+    {
+        for(i = 0UL; i < 5UL; i++)
+        {
+            au32TmpBuf[i] = SDH_Swap32(sdh->FB[i]);
+        }
+        for(i = 0UL; i < 4UL; i++)
+        {
+            pu32R2ptr[i] = ((au32TmpBuf[i] & 0x00ffffffUL) << 8) | ((au32TmpBuf[i + 1UL] & 0xff000000UL) >> 24);
+        }
+        return Successful;
+    }
+    else
+    {
+        return SDH_CRC7_ERROR;
+    }
+}
+
+
+uint32_t SDH_SDCmdAndRspDataIn(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg)
+{
+    SDH_INFO_T *pSD;
+
+    /* M2354 is only support SDH0 */
+    pSD = &SD0;
+
+    sdh->CMDARG = u32Arg;
+    sdh->CTL = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | ((uint32_t)u32Cmd << 8) |
+               (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk);
+
+    while(sdh->CTL & SDH_CTL_RIEN_Msk)
+    {
+        if(pSD->IsCardInsert == (uint32_t)FALSE)
+        {
+            return SDH_NO_SD_CARD;
+        }
+    }
+
+    while(sdh->CTL & SDH_CTL_DIEN_Msk)
+    {
+        if(pSD->IsCardInsert == (uint32_t)FALSE)
+        {
+            return SDH_NO_SD_CARD;
+        }
+    }
+
+    if(!(sdh->INTSTS & SDH_INTSTS_CRC7_Msk))       /* check CRC7 */
+    {
+        return SDH_CRC7_ERROR;
+    }
+
+    if(!(sdh->INTSTS & SDH_INTSTS_CRC16_Msk))      /* check CRC16 */
+    {
+        return SDH_CRC16_ERROR;
+    }
+
+    return Successful;
+}
+
+/* there are 8 bits for divider0, maximum is 256 */
+#define SDH_CLK_DIV0_MAX     256UL
+
+void SDH_Set_clock(SDH_T *sdh, uint32_t u32SDClockKhz)
+{
+    (void)sdh;
+    if(!(__PC() & (1UL << 28)))
+    {
+        uint32_t u32Rate, u32Div1;
+        static uint32_t u32SDClkSrc = 0UL;
+
+        /* M2354 is only support SDH0 */
+        u32SDClkSrc = (CLK->CLKSEL0 & CLK_CLKSEL0_SDH0SEL_Msk);
+        if(u32SDClkSrc == CLK_CLKSEL0_SDH0SEL_HXT)
+        {
+            _SDH_ReferenceClock = (CLK_GetHXTFreq() / 1000UL);
+        }
+        else if(u32SDClkSrc == CLK_CLKSEL0_SDH0SEL_HIRC)
+        {
+            _SDH_ReferenceClock = (__HIRC / 1000UL);
+        }
+        else if(u32SDClkSrc == CLK_CLKSEL0_SDH0SEL_PLL)
+        {
+            _SDH_ReferenceClock = (CLK_GetPLLClockFreq() / 1000UL);
+        }
+        else if(u32SDClkSrc == CLK_CLKSEL0_SDH0SEL_HCLK)
+        {
+            _SDH_ReferenceClock = (CLK_GetHCLKFreq() / 1000UL);
+        }
+
+        if(u32SDClockKhz >= 50000UL)
+        {
+            u32SDClockKhz = 50000UL;
+        }
+        u32Rate = _SDH_ReferenceClock / u32SDClockKhz;
+
+        /* choose slower clock if system clock cannot divisible by wanted clock */
+        if(_SDH_ReferenceClock % u32SDClockKhz != 0UL)
+        {
+            u32Rate++;
+        }
+
+        if(u32Rate >= SDH_CLK_DIV0_MAX)
+        {
+            u32Rate = SDH_CLK_DIV0_MAX;
+        }
+
+        /* --- calculate the second divider CLKDIV0[SDHOST_N] */
+        if(u32Rate == 0UL)
+        {
+            u32Div1 = 0UL;
+        }
+        else
+        {
+            u32Div1 = ((u32Rate - 1UL) & 0xFFUL);
+        }
+
+        /* --- setup register */
+        /* M2354 is only support SDH0 */
+        CLK->CLKDIV0 &= ~CLK_CLKDIV0_SDH0DIV_Msk;
+        CLK->CLKDIV0 |= (u32Div1 << CLK_CLKDIV0_SDH0DIV_Pos);
+    }
+}
+
+uint32_t SDH_CardDetection(SDH_T *sdh)
+{
+    uint32_t i, u32Status = (uint32_t)TRUE;
+    SDH_INFO_T *pSD;
+
+    /* M2354 is only support SDH0 */
+    pSD = &SD0;
+
+    if(sdh->INTEN & SDH_INTEN_CDSRC_Msk)   /* Card detect pin from GPIO */
+    {
+        if(sdh->INTSTS & SDH_INTSTS_CDSTS_Msk)   /* Card remove */
+        {
+            pSD->IsCardInsert = (uint8_t)FALSE;
+            u32Status = (uint32_t)FALSE;
+        }
+        else
+        {
+            pSD->IsCardInsert = (uint8_t)TRUE;
+        }
+    }
+    else if(!(sdh->INTEN & SDH_INTEN_CDSRC_Msk))
+    {
+        sdh->CTL |= SDH_CTL_CLKKEEP_Msk;
+        for(i = 0UL; i < 5000UL; i++) {}
+
+        if(sdh->INTSTS & SDH_INTSTS_CDSTS_Msk) /* Card insert */
+        {
+            pSD->IsCardInsert = (uint8_t)TRUE;
+        }
+        else
+        {
+            pSD->IsCardInsert = (uint8_t)FALSE;
+            u32Status = (uint32_t)FALSE;
+        }
+
+        sdh->CTL &= ~SDH_CTL_CLKKEEP_Msk;
+    }
+
+    return u32Status;
+}
+
+
+/* Initial */
+uint32_t SDH_Init(SDH_T *sdh)
+{
+    uint32_t volatile i, u32Status;
+    uint32_t u32Resp;
+    uint32_t au32CIDBuffer[4];
+    uint32_t volatile u32CmdTimeOut;
+    SDH_INFO_T *pSD;
+
+    /* M2354 is only support SDH0 */
+    pSD = &SD0;
+
+    /* set the clock to 300KHz */
+    SDH_Set_clock(sdh, 300UL);
+
+    /* power ON 74 clock */
+    sdh->CTL |= SDH_CTL_CLK74OEN_Msk;
+
+    while(sdh->CTL & SDH_CTL_CLK74OEN_Msk)
+    {
+        if(pSD->IsCardInsert == (uint8_t)FALSE)
+        {
+            return SDH_NO_SD_CARD;
+        }
+    }
+
+    SDH_SDCommand(sdh, 0UL, 0UL);        /* reset all cards */
+    for(i = 0x1000UL; i > 0UL; i--) {}
+
+    /* initial SDHC */
+    _SDH_uR7_CMD = 1UL;
+    u32CmdTimeOut = 0xFFFFFUL;
+
+    i = SDH_SDCmdAndRsp(sdh, 8UL, 0x00000155UL, u32CmdTimeOut);
+    if(i == Successful)
+    {
+        /* SD 2.0 */
+        SDH_SDCmdAndRsp(sdh, 55UL, 0x00UL, u32CmdTimeOut);
+        g_u8R3Flag = 1UL;
+        SDH_SDCmdAndRsp(sdh, 41UL, 0x40ff8000UL, u32CmdTimeOut); /* 2.7v-3.6v */
+        u32Resp = sdh->RESP0;
+
+        while(!(u32Resp & 0x00800000UL))         /* check if card is ready */
+        {
+            SDH_SDCmdAndRsp(sdh, 55UL, 0x00UL, u32CmdTimeOut);
+            g_u8R3Flag = 1UL;
+            SDH_SDCmdAndRsp(sdh, 41UL, 0x40ff8000UL, u32CmdTimeOut); /* 3.0v-3.4v */
+            u32Resp = sdh->RESP0;
+        }
+        if(u32Resp & 0x00400000UL)
+        {
+            pSD->CardType = SDH_TYPE_SD_HIGH;
+        }
+        else
+        {
+            pSD->CardType = SDH_TYPE_SD_LOW;
+        }
+    }
+    else
+    {
+        /* SD 1.1 */
+        SDH_SDCommand(sdh, 0UL, 0UL);        /* reset all cards */
+        for(i = 0x100UL; i > 0UL; i--) {}
+
+        i = SDH_SDCmdAndRsp(sdh, 55UL, 0x00UL, u32CmdTimeOut);
+        if(i == 2UL)      /* MMC memory */
+        {
+            SDH_SDCommand(sdh, 0UL, 0UL);        /* reset */
+            for(i = 0x100UL; i > 0UL; i--) {}
+
+            g_u8R3Flag = 1UL;
+
+            if(SDH_SDCmdAndRsp(sdh, 1UL, 0x40ff8000UL, u32CmdTimeOut) != 2UL)     /* eMMC memory */
+            {
+                u32Resp = sdh->RESP0;
+                while(!(u32Resp & 0x00800000UL))         /* check if card is ready */
+                {
+                    g_u8R3Flag = 1UL;
+
+                    SDH_SDCmdAndRsp(sdh, 1UL, 0x40ff8000UL, u32CmdTimeOut);      /* high voltage */
+                    u32Resp = sdh->RESP0;
+                }
+
+                if(u32Resp & 0x00400000UL)
+                {
+                    pSD->CardType = SDH_TYPE_EMMC;
+                }
+                else
+                {
+                    pSD->CardType = SDH_TYPE_MMC;
+                }
+            }
+            else
+            {
+                pSD->CardType = SDH_TYPE_UNKNOWN;
+                return SDH_ERR_DEVICE;
+            }
+        }
+        else if(i == 0UL)      /* SD Memory */
+        {
+            g_u8R3Flag = 1UL;
+            SDH_SDCmdAndRsp(sdh, 41UL, 0x00ff8000UL, u32CmdTimeOut); /* 3.0v-3.4v */
+            u32Resp = sdh->RESP0;
+            while(!(u32Resp & 0x00800000UL))         /* check if card is ready */
+            {
+                SDH_SDCmdAndRsp(sdh, 55UL, 0x00UL, u32CmdTimeOut);
+                g_u8R3Flag = 1UL;
+                SDH_SDCmdAndRsp(sdh, 41UL, 0x00ff8000UL, u32CmdTimeOut); /* 3.0v-3.4v */
+                u32Resp = sdh->RESP0;
+            }
+            pSD->CardType = SDH_TYPE_SD_LOW;
+        }
+        else
+        {
+            pSD->CardType = SDH_TYPE_UNKNOWN;
+            return SDH_INIT_ERROR;
+        }
+    }
+
+    /* CMD2, CMD3 */
+    if(pSD->CardType != SDH_TYPE_UNKNOWN)
+    {
+        SDH_SDCmdAndRsp2(sdh, 2UL, 0x00UL, au32CIDBuffer);
+        if((pSD->CardType == SDH_TYPE_MMC) || (pSD->CardType == SDH_TYPE_EMMC))
+        {
+            if((u32Status = SDH_SDCmdAndRsp(sdh, 3UL, 0x10000UL, 0UL)) != Successful)         /* set RCA */
+            {
+                return u32Status;
+            }
+            pSD->RCA = 0x10000UL;
+        }
+        else
+        {
+            if((u32Status = SDH_SDCmdAndRsp(sdh, 3UL, 0x00UL, 0UL)) != Successful)        /* get RCA */
+            {
+                return u32Status;
+            }
+            else
+            {
+                pSD->RCA = (sdh->RESP0 << 8) & 0xffff0000UL;
+            }
+        }
+    }
+
+    return Successful;
+}
+
+
+uint32_t SDH_SwitchToHighSpeed(SDH_T *sdh, SDH_INFO_T *pSD)
+{
+    uint32_t volatile u32Status = 0UL;
+    uint16_t u16CurrentComsumption, u16BusyStatus0;
+
+    (void)pSD;
+    sdh->DMASA = (uint32_t)_SDH_ucSDHCBuffer;    /* set DMA transfer starting address */
+    sdh->BLEN = 63UL;    /* 512 bit */
+
+    if((u32Status = SDH_SDCmdAndRspDataIn(sdh, 6UL, 0x00ffff01UL)) != Successful)
+    {
+        return Fail;
+    }
+
+    u16CurrentComsumption = (uint16_t)(_SDH_ucSDHCBuffer[0] << 8);
+    u16CurrentComsumption |= (uint16_t)_SDH_ucSDHCBuffer[1];
+    if(!u16CurrentComsumption)
+    {
+        return Fail;
+    }
+
+    u16BusyStatus0 = (uint16_t)(_SDH_ucSDHCBuffer[28] << 8);
+    u16BusyStatus0 |= (uint16_t)_SDH_ucSDHCBuffer[29];
+
+    if(!u16BusyStatus0)    /* function ready */
+    {
+        sdh->DMASA = (uint32_t)_SDH_ucSDHCBuffer;        /* set DMA transfer starting address */
+        sdh->BLEN = 63UL;    /* 512 bit */
+
+        if((u32Status = SDH_SDCmdAndRspDataIn(sdh, 6UL, 0x80ffff01UL)) != Successful)
+        {
+            return Fail;
+        }
+
+        /* function change timing: 8 clocks */
+        sdh->CTL |= SDH_CTL_CLK8OEN_Msk;
+        while(sdh->CTL & SDH_CTL_CLK8OEN_Msk) {}
+
+        u16CurrentComsumption = (uint16_t)(_SDH_ucSDHCBuffer[0] << 8);
+        u16CurrentComsumption |= (uint16_t)_SDH_ucSDHCBuffer[1];
+        if(!u16CurrentComsumption)
+        {
+            return Fail;
+        }
+
+        return Successful;
+    }
+    else
+    {
+        return Fail;
+    }
+}
+
+
+uint32_t SDH_SelectCardType(SDH_T *sdh)
+{
+    uint32_t volatile u32Status = 0UL;
+    uint32_t u32Param;
+    SDH_INFO_T *pSD;
+
+    /* M2354 is only support SDH0 */
+    pSD = &SD0;
+
+    if((u32Status = SDH_SDCmdAndRsp(sdh, 7UL, pSD->RCA, 0UL)) != Successful)
+    {
+        return u32Status;
+    }
+
+    SDH_CheckRB(sdh);
+
+    /* if SD card set 4bit */
+    if(pSD->CardType == SDH_TYPE_SD_HIGH)
+    {
+        sdh->DMASA = (uint32_t)_SDH_ucSDHCBuffer;    /* set DMA transfer starting address */
+        sdh->BLEN = 0x07UL;  /* 64 bit */
+
+        if((u32Status = SDH_SDCmdAndRsp(sdh, 55UL, pSD->RCA, 0UL)) != Successful)
+        {
+            return u32Status;
+        }
+
+        sdh->DMACTL |= 0x2;
+        while(sdh->DMACTL & 0x2) {}
+
+        if((u32Status = SDH_SDCmdAndRspDataIn(sdh, 51UL, 0x00UL)) != Successful)
+        {
+            return u32Status;
+        }
+
+        if((_SDH_ucSDHCBuffer[0] & 0xfUL) == 0xfUL)
+        {
+            u32Status = SDH_SwitchToHighSpeed(sdh, pSD);
+            if(u32Status == Successful)
+            {
+                /* divider */
+                SDH_Set_clock(sdh, SDHC_FREQ);
+            }
+        }
+
+        if((u32Status = SDH_SDCmdAndRsp(sdh, 55UL, pSD->RCA, 0UL)) != Successful)
+        {
+            return u32Status;
+        }
+        if((u32Status = SDH_SDCmdAndRsp(sdh, 6UL, 0x02UL, 0UL)) != Successful)    /* set bus width */
+        {
+            return u32Status;
+        }
+
+        sdh->CTL |= SDH_CTL_DBW_Msk;
+    }
+    else if(pSD->CardType == SDH_TYPE_SD_LOW)
+    {
+        sdh->DMASA = (uint32_t) _SDH_ucSDHCBuffer; /* set DMA transfer starting address */
+        sdh->BLEN = 0x07UL;  /* 64 bit */
+
+        if((u32Status = SDH_SDCmdAndRsp(sdh, 55UL, pSD->RCA, 0UL)) != Successful)
+        {
+            return u32Status;
+        }
+        if((u32Status = SDH_SDCmdAndRspDataIn(sdh, 51UL, 0x00UL)) != Successful)
+        {
+            return u32Status;
+        }
+
+        /* set data bus width. ACMD6 for SD card, SDCR_DBW for host. */
+        if((u32Status = SDH_SDCmdAndRsp(sdh, 55UL, pSD->RCA, 0UL)) != Successful)
+        {
+            return u32Status;
+        }
+
+        if((u32Status = SDH_SDCmdAndRsp(sdh, 6UL, 0x02UL, 0UL)) != Successful)    /* set bus width */
+        {
+            return u32Status;
+        }
+
+        sdh->CTL |= SDH_CTL_DBW_Msk;
+    }
+    else if((pSD->CardType == SDH_TYPE_MMC) || (pSD->CardType == SDH_TYPE_EMMC))
+    {
+
+        if(pSD->CardType == SDH_TYPE_MMC)
+        {
+            sdh->CTL &= ~SDH_CTL_DBW_Msk;
+        }
+
+        /* --- sent CMD6 to MMC card to set bus width to 4 bits mode */
+        /* set CMD6 argument Access field to 3, Index to 183, Value to 1 (4-bit mode) */
+        u32Param = (3UL << 24) | (183UL << 16) | (1UL << 8);
+        if((u32Status = SDH_SDCmdAndRsp(sdh, 6UL, u32Param, 0UL)) != Successful)
+        {
+            return u32Status;
+        }
+        SDH_CheckRB(sdh);
+
+        sdh->CTL |= SDH_CTL_DBW_Msk; /* set bus width to 4-bit mode for SD host controller */
+    }
+
+    if((u32Status = SDH_SDCmdAndRsp(sdh, 16UL, SDH_BLOCK_SIZE, 0UL)) != Successful)  /* set block length */
+    {
+        return u32Status;
+    }
+    sdh->BLEN = SDH_BLOCK_SIZE - 1UL;           /* set the block size */
+
+    SDH_SDCommand(sdh, 7UL, 0UL);
+    sdh->CTL |= SDH_CTL_CLK8OEN_Msk;
+    while(sdh->CTL & SDH_CTL_CLK8OEN_Msk) {}
+
+    sdh->INTEN |= SDH_INTEN_BLKDIEN_Msk;
+
+    return Successful;
+}
+
+void SDH_Get_SD_info(SDH_T *sdh)
+{
+    uint32_t u32RLen, u32CSize, u32Mult, u32Size;
+    uint32_t au32Buffer[4];
+    SDH_INFO_T *pSD;
+
+    /* M2354 is only support SDH0 */
+    pSD = &SD0;
+
+    SDH_SDCmdAndRsp2(sdh, 9UL, pSD->RCA, au32Buffer);
+
+    if((pSD->CardType == SDH_TYPE_MMC) || (pSD->CardType == SDH_TYPE_EMMC))
+    {
+        /* for MMC/eMMC card */
+        if((au32Buffer[0] & 0xc0000000UL) == 0xc0000000UL)
+        {
+            /* CSD_STRUCTURE [127:126] is 3 */
+            /* CSD version depend on EXT_CSD register in eMMC v4.4 for card size > 2GB */
+            SDH_SDCmdAndRsp(sdh, 7UL, pSD->RCA, 0UL);
+
+            sdh->DMASA = (uint32_t)_SDH_ucSDHCBuffer;  /* set DMA transfer starting address */
+            sdh->BLEN = 511UL;  /* read 512 bytes for EXT_CSD */
+
+            if(SDH_SDCmdAndRspDataIn(sdh, 8UL, 0x00UL) != Successful)
+            {
+                return;
+            }
+
+            SDH_SDCommand(sdh, 7UL, 0UL);
+            sdh->CTL |= SDH_CTL_CLK8OEN_Msk;
+            while(sdh->CTL & SDH_CTL_CLK8OEN_Msk) {}
+
+            pSD->totalSectorN = (uint32_t)_SDH_ucSDHCBuffer[215] << 24;
+            pSD->totalSectorN |= (uint32_t)_SDH_ucSDHCBuffer[214] << 16;
+            pSD->totalSectorN |= (uint32_t)_SDH_ucSDHCBuffer[213] << 8;
+            pSD->totalSectorN |= (uint32_t)_SDH_ucSDHCBuffer[212];
+            pSD->diskSize = pSD->totalSectorN / 2UL;
+        }
+        else
+        {
+            /* CSD version v1.0/1.1/1.2 in eMMC v4.4 spec for card size <= 2GB */
+            u32RLen = (au32Buffer[1] & 0x000f0000UL) >> 16;
+            u32CSize = ((au32Buffer[1] & 0x000003ffUL) << 2) | ((au32Buffer[2] & 0xc0000000UL) >> 30);
+            u32Mult = (au32Buffer[2] & 0x00038000UL) >> 15;
+            u32Size = (u32CSize + 1UL) * (1UL << (u32Mult + 2UL)) * (1UL << u32RLen);
+
+            pSD->diskSize = u32Size / 1024UL;
+            pSD->totalSectorN = u32Size / 512UL;
+        }
+    }
+    else
+    {
+        if(au32Buffer[0] & 0xc0000000UL)
+        {
+            u32CSize = ((au32Buffer[1] & 0x0000003fUL) << 16) | ((au32Buffer[2] & 0xffff0000UL) >> 16);
+            u32Size = (u32CSize + 1UL) * 512UL;  /* Kbytes */
+
+            pSD->diskSize = u32Size;
+            pSD->totalSectorN = u32Size << 1;
+        }
+        else
+        {
+            u32RLen = (au32Buffer[1] & 0x000f0000UL) >> 16;
+            u32CSize = ((au32Buffer[1] & 0x000003ffUL) << 2) | ((au32Buffer[2] & 0xc0000000UL) >> 30);
+            u32Mult = (au32Buffer[2] & 0x00038000UL) >> 15;
+            u32Size = (u32CSize + 1UL) * (1UL << (u32Mult + 2UL)) * (1UL << u32RLen);
+
+            pSD->diskSize = u32Size / 1024UL;
+            pSD->totalSectorN = u32Size / 512UL;
+        }
+    }
+    pSD->sectorSize = (int)512UL;
+}
+
+/** @endcond HIDDEN_SYMBOLS */
+
+
+/**
+ *  @brief  This function use to reset SD function and select card detection source and pin.
+ *
+ *  @param[in]  sdh    The pointer of the specified SDH module.
+ *  @param[in]  u32CardDetSrc   Select card detection pin from GPIO or DAT3 pin. ( \ref CardDetect_From_GPIO / \ref CardDetect_From_DAT3)
+ *
+ *  @return None
+ */
+void SDH_Open(SDH_T *sdh, uint32_t u32CardDetSrc)
+{
+    /* enable DMAC */
+    sdh->DMACTL = SDH_DMACTL_DMARST_Msk;
+    while(sdh->DMACTL & SDH_DMACTL_DMARST_Msk) {}
+
+    sdh->DMACTL = SDH_DMACTL_DMAEN_Msk;
+
+    /* Reset FMI */
+    sdh->GCTL = SDH_GCTL_GCTLRST_Msk | SDH_GCTL_SDEN_Msk;        /* Start reset FMI controller. */
+    while(sdh->GCTL & SDH_GCTL_GCTLRST_Msk) {}
+
+    memset(&SD0, 0, sizeof(SDH_INFO_T));
+
+    /* enable SD */
+    sdh->GCTL = SDH_GCTL_SDEN_Msk;
+
+    if(u32CardDetSrc & CardDetect_From_DAT3)
+    {
+        sdh->INTEN &= ~SDH_INTEN_CDSRC_Msk;
+    }
+    else
+    {
+        sdh->INTEN |= SDH_INTEN_CDSRC_Msk;
+    }
+    sdh->INTEN |= SDH_INTEN_CDIEN_Msk;
+
+    sdh->CTL |= SDH_CTL_CTLRST_Msk;     /* SD software reset */
+    while(sdh->CTL & SDH_CTL_CTLRST_Msk) {}
+
+}
+
+/**
+ *  @brief  This function use to initial SD card.
+ *
+ *  @param[in]    sdh    The pointer of the specified SDH module.
+ *
+ *  @return None
+ *
+ *  @details This function is used to initial SD card.
+ *           SD initial state needs 400KHz clock output, driver will use HIRC for SD initial clock source.
+ *           And then switch back to the user's setting.
+ */
+uint32_t SDH_Probe(SDH_T *sdh)
+{
+    uint32_t u32Val;
+
+    /* Disable FMI/SD host interrupt */
+    sdh->GINTEN = 0UL;
+
+    sdh->CTL &= ~SDH_CTL_SDNWR_Msk;
+    sdh->CTL |=  0x09UL << SDH_CTL_SDNWR_Pos;         /* set SDNWR = 9 */
+    sdh->CTL &= ~SDH_CTL_BLKCNT_Msk;
+    sdh->CTL |=  0x01UL << SDH_CTL_BLKCNT_Pos;           /* set BLKCNT = 1 */
+    sdh->CTL &= ~SDH_CTL_DBW_Msk;               /* SD 1-bit data bus */
+
+    if(!(SDH_CardDetection(sdh)))
+    {
+        return SDH_NO_SD_CARD;
+    }
+
+    if((u32Val = SDH_Init(sdh)) != 0UL)
+    {
+        return u32Val;
+    }
+
+    /* divider */
+    if(SD0.CardType == SDH_TYPE_MMC)
+    {
+        SDH_Set_clock(sdh, MMC_FREQ);
+    }
+    else
+    {
+        SDH_Set_clock(sdh, SD_FREQ);
+    }
+    SDH_Get_SD_info(sdh);
+
+    if((u32Val = SDH_SelectCardType(sdh)) != 0UL)
+    {
+        return u32Val;
+    }
+
+    return 0UL;
+}
+
+/**
+ *  @brief  This function use to read data from SD card.
+ *
+ *  @param[in]     sdh           The pointer of the specified SDH module.
+ *  @param[out]    pu8BufAddr    The buffer to receive the data from SD card.
+ *  @param[in]     u32StartSec   The start read sector address.
+ *  @param[in]     u32SecCount   The the read sector number of data
+ *
+ *  @return None
+ */
+uint32_t SDH_Read(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount)
+{
+    uint32_t volatile u32IsSendCmd = (uint32_t)FALSE;
+    uint32_t volatile u32Reg;
+    uint32_t volatile u32Loop, u32Status;
+    uint32_t u32BlkSize = SDH_BLOCK_SIZE;
+
+    SDH_INFO_T *pSD;
+
+    /* M2354 is only support SDH0 */
+    pSD = &SD0;
+
+    /* --- check input parameters */
+    if(u32SecCount == 0UL)
+    {
+        return SDH_SELECT_ERROR;
+    }
+
+    if((u32Status = SDH_SDCmdAndRsp(sdh, 7UL, pSD->RCA, 0UL)) != Successful)
+    {
+        return u32Status;
+    }
+    SDH_CheckRB(sdh);
+
+    sdh->BLEN = u32BlkSize - 1UL;       /* the actual byte count is equal to (SDBLEN+1) */
+
+    if((pSD->CardType == SDH_TYPE_SD_HIGH) || (pSD->CardType == SDH_TYPE_EMMC))
+    {
+        sdh->CMDARG = u32StartSec;
+    }
+    else
+    {
+        sdh->CMDARG = u32StartSec * u32BlkSize;
+    }
+
+    sdh->DMASA = (uint32_t)pu8BufAddr;
+
+    u32Loop = u32SecCount / 255UL;
+    while(u32Loop > 0UL)
+    {
+        g_u8SDDataReadyFlag = (uint8_t)FALSE;
+        u32Reg = sdh->CTL & ~SDH_CTL_CMDCODE_Msk;
+        u32Reg = u32Reg | 0xff0000UL;   /* set BLK_CNT to 255 */
+        if(u32IsSendCmd == (uint32_t)FALSE)
+        {
+            sdh->CTL = u32Reg | (18UL << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk);
+            u32IsSendCmd = (uint32_t)TRUE;
+        }
+        else
+        {
+            sdh->CTL = u32Reg | SDH_CTL_DIEN_Msk;
+        }
+
+        while(!g_u8SDDataReadyFlag)
+        {
+            if(g_u8SDDataReadyFlag)
+            {
+                break;
+            }
+            if(pSD->IsCardInsert == (uint8_t)FALSE)
+            {
+                return SDH_NO_SD_CARD;
+            }
+        }
+
+        if(!(sdh->INTSTS & SDH_INTSTS_CRC7_Msk))     /* check CRC7 */
+        {
+            return SDH_CRC7_ERROR;
+        }
+
+        if(!(sdh->INTSTS & SDH_INTSTS_CRC16_Msk))    /* check CRC16 */
+        {
+            return SDH_CRC16_ERROR;
+        }
+        u32Loop--;
+    }
+
+    u32Loop = u32SecCount % 255UL;
+    if(u32Loop != 0UL)
+    {
+        uint32_t u32RegTmp;
+        g_u8SDDataReadyFlag = (uint8_t)FALSE;
+        u32Reg = sdh->CTL & (~SDH_CTL_CMDCODE_Msk);
+        u32Reg = u32Reg & (~SDH_CTL_BLKCNT_Msk);
+        u32RegTmp = (u32Loop << 16);
+        u32Reg |= u32RegTmp;    /* setup SDCR_BLKCNT */
+
+        if(u32IsSendCmd == (uint32_t)FALSE)
+        {
+            sdh->CTL = u32Reg | (18UL << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk);
+            u32IsSendCmd = (uint32_t)TRUE;
+        }
+        else
+        {
+            sdh->CTL = u32Reg | SDH_CTL_DIEN_Msk;
+        }
+
+        while(!g_u8SDDataReadyFlag)
+        {
+            if(pSD->IsCardInsert == (uint8_t)FALSE)
+            {
+                return SDH_NO_SD_CARD;
+            }
+        }
+
+        if(!(sdh->INTSTS & SDH_INTSTS_CRC7_Msk))     /* check CRC7 */
+        {
+            return SDH_CRC7_ERROR;
+        }
+
+        if(!(sdh->INTSTS & SDH_INTSTS_CRC16_Msk))     /* check CRC16 */
+        {
+            return SDH_CRC16_ERROR;
+        }
+    }
+
+    if(SDH_SDCmdAndRsp(sdh, 12UL, 0UL, 0UL))     /* stop command */
+    {
+        return SDH_CRC7_ERROR;
+    }
+    SDH_CheckRB(sdh);
+
+    SDH_SDCommand(sdh, 7UL, 0UL);
+    sdh->CTL |= SDH_CTL_CLK8OEN_Msk;
+    while(sdh->CTL & SDH_CTL_CLK8OEN_Msk) {}
+
+    return Successful;
+}
+
+/**
+ *  @brief  This function use to write data to SD card.
+ *
+ *  @param[in]    sdh           The pointer of the specified SDH module.
+ *  @param[in]    pu8BufAddr    The buffer to send the data to SD card.
+ *  @param[in]    u32StartSec   The start write sector address.
+ *  @param[in]    u32SecCount   The the write sector number of data.
+ *
+ *  @return   \ref SDH_SELECT_ERROR : u32SecCount is zero. \n
+ *            \ref SDH_NO_SD_CARD : SD card be removed. \n
+ *            \ref SDH_CRC_ERROR : CRC error happen. \n
+ *            \ref SDH_CRC7_ERROR : CRC7 error happen. \n
+ *            \ref Successful : Write data to SD card success.
+ */
+uint32_t SDH_Write(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount)
+{
+    uint32_t volatile u32IsSendCmd = (uint32_t)FALSE;
+    uint32_t volatile u32Reg;
+    uint32_t volatile u32Loop, u32Status;
+
+    SDH_INFO_T *pSD;
+
+    /* M2354 is only support SDH0 */
+    pSD = &SD0;
+
+    /* --- check input parameters */
+    if(u32SecCount == 0UL)
+    {
+        return SDH_SELECT_ERROR;
+    }
+
+    if((u32Status = SDH_SDCmdAndRsp(sdh, 7UL, pSD->RCA, 0UL)) != Successful)
+    {
+        return u32Status;
+    }
+
+    SDH_CheckRB(sdh);
+
+    /* According to SD Spec v2.0, the write CMD block size MUST be 512, and the start address MUST be 512*n. */
+    sdh->BLEN = SDH_BLOCK_SIZE - 1UL;           /* set the block size */
+
+    if((pSD->CardType == SDH_TYPE_SD_HIGH) || (pSD->CardType == SDH_TYPE_EMMC))
+    {
+        sdh->CMDARG = u32StartSec;
+    }
+    else
+    {
+        sdh->CMDARG = u32StartSec * SDH_BLOCK_SIZE;  /* set start address for SD CMD */
+    }
+
+    sdh->DMASA = (uint32_t)pu8BufAddr;
+    u32Loop = u32SecCount / 255UL;   /* the maximum block count is 0xFF=255 for register SDCR[BLK_CNT] */
+    while(u32Loop > 0UL)
+    {
+        g_u8SDDataReadyFlag = (uint8_t)FALSE;
+        u32Reg = sdh->CTL & 0xff00c080UL;
+        u32Reg = u32Reg | 0xff0000UL;   /* set BLK_CNT to 0xFF=255 */
+        if(!u32IsSendCmd)
+        {
+            sdh->CTL = u32Reg | (25UL << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DOEN_Msk);
+            u32IsSendCmd = (uint32_t)TRUE;
+        }
+        else
+        {
+            sdh->CTL = u32Reg | SDH_CTL_DOEN_Msk;
+        }
+
+        while(!g_u8SDDataReadyFlag)
+        {
+            if(pSD->IsCardInsert == (uint8_t)FALSE)
+            {
+                return SDH_NO_SD_CARD;
+            }
+        }
+
+        if((sdh->INTSTS & SDH_INTSTS_CRCIF_Msk) != 0UL)      /* check CRC */
+        {
+            sdh->INTSTS = SDH_INTSTS_CRCIF_Msk;
+            return SDH_CRC_ERROR;
+        }
+        u32Loop--;
+    }
+
+    u32Loop = u32SecCount % 255UL;
+    if(u32Loop != 0UL)
+    {
+        uint32_t u32RegTmp;
+        g_u8SDDataReadyFlag = (uint8_t)FALSE;
+        u32RegTmp = (u32Loop << 16);
+        u32Reg = (sdh->CTL & 0xff00c080UL) | u32RegTmp;
+        if(!u32IsSendCmd)
+        {
+            sdh->CTL = u32Reg | (25UL << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DOEN_Msk);
+            u32IsSendCmd = (uint32_t)TRUE;
+        }
+        else
+        {
+            sdh->CTL = u32Reg | SDH_CTL_DOEN_Msk;
+        }
+
+        while(!g_u8SDDataReadyFlag)
+        {
+            if(pSD->IsCardInsert == (uint8_t)FALSE)
+            {
+                return SDH_NO_SD_CARD;
+            }
+        }
+
+        if((sdh->INTSTS & SDH_INTSTS_CRCIF_Msk) != 0UL)      /* check CRC */
+        {
+            sdh->INTSTS = SDH_INTSTS_CRCIF_Msk;
+            return SDH_CRC_ERROR;
+        }
+    }
+    sdh->INTSTS = SDH_INTSTS_CRCIF_Msk;
+
+    if(SDH_SDCmdAndRsp(sdh, 12UL, 0UL, 0UL))       /* stop command */
+    {
+        return SDH_CRC7_ERROR;
+    }
+    SDH_CheckRB(sdh);
+
+    SDH_SDCommand(sdh, 7UL, 0UL);
+    sdh->CTL |= SDH_CTL_CLK8OEN_Msk;
+    while(sdh->CTL & SDH_CTL_CLK8OEN_Msk) {}
+
+    return Successful;
+}
+
+
+/**@}*/ /* end of group SDH_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group SDH_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_spi.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_spi.c
new file mode 100644
index 0000000000..d079697b2a
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_spi.c
@@ -0,0 +1,1650 @@
+/**************************************************************************//**
+ * @file     spi.c
+ * @version  V3.00
+ * @brief    M2354 series SPI driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup SPI_Driver SPI Driver
+  @{
+*/
+
+
+/** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions
+  @{
+*/
+
+static uint32_t SPII2S_GetSourceClockFreq(SPI_T *i2s);
+
+/**
+  * @brief  This function make SPI module be ready to transfer.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32MasterSlave Decides the SPI module is operating in master mode or in slave mode. (SPI_SLAVE, SPI_MASTER)
+  * @param[in]  u32SPIMode Decides the transfer timing. (SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3)
+  * @param[in]  u32DataWidth Decides the data width of a SPI transaction.
+  * @param[in]  u32BusClock The expected frequency of SPI bus clock in Hz.
+  * @return Actual frequency of SPI peripheral clock.
+  * @details By default, the SPI transfer sequence is MSB first, the slave selection signal is active low and the automatic
+  *          slave selection function is disabled.
+  *          In Slave mode, the u32BusClock shall be NULL and the SPI clock divider setting will be 0.
+  *          The actual clock rate may be different from the target SPI clock rate.
+  *          For example, if the SPI source clock rate is 12 MHz and the target SPI bus clock rate is 7 MHz, the
+  *          actual SPI clock rate will be 6MHz.
+  * @note   If u32BusClock = 0, DIVIDER setting will be set to the maximum value.
+  * @note   If u32BusClock >= system clock frequency for Secure, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0.
+  * @note   If u32BusClock >= system clock frequency for Non-Secure, this function does not do anything to avoid the situation that the frequency of
+  *         SPI bus clock cannot be faster than the system clock rate. User should set up carefully.
+  * @note   If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0.
+  * @note   In slave mode for Secure, the SPI peripheral clock rate will equal to APB clock rate.
+  * @note   In slave mode for Non-Secure, the SPI peripheral clock rate will equal to the clock rate set in secure mode.
+  */
+uint32_t SPI_Open(SPI_T *spi,
+                  uint32_t u32MasterSlave,
+                  uint32_t u32SPIMode,
+                  uint32_t u32DataWidth,
+                  uint32_t u32BusClock)
+{
+    uint32_t u32ClkSrc = 0UL, u32Div, u32HCLKFreq, u32PCLK0Freq, u32PCLK1Freq, u32RetValue = 0UL;
+
+    /* Disable I2S mode */
+    spi->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk;
+
+    if(u32DataWidth == 32UL)
+    {
+        u32DataWidth = 0UL;
+    }
+
+    /* Get system clock frequency */
+    u32HCLKFreq = CLK_GetHCLKFreq();
+    /* Get APB0 clock frequency */
+    u32PCLK0Freq = CLK_GetPCLK0Freq();
+    /* Get APB1 clock frequency */
+    u32PCLK1Freq = CLK_GetPCLK1Freq();
+
+    if(u32MasterSlave == SPI_MASTER)
+    {
+        /* Default setting: slave selection signal is active low; disable automatic slave selection function. */
+        spi->SSCTL = SPI_SS_ACTIVE_LOW;
+
+        /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
+        spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk;
+
+        if(u32BusClock >= u32HCLKFreq)
+        {
+            if(!(__PC() & NS_OFFSET))
+            {
+                /* Select PCLK as the clock source of SPI */
+                if((spi == SPI0) || (spi == SPI0_NS))
+                {
+                    CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1;
+                }
+                else if((spi == SPI1) || (spi == SPI1_NS))
+                {
+                    CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0;
+                }
+                else if((spi == SPI2) || (spi == SPI2_NS))
+                {
+                    CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1;
+                }
+                else
+                {
+                    CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0;
+                }
+            }
+        }
+
+        /* Check clock source of SPI */
+        if((spi == SPI0) || (spi == SPI0_NS))
+        {
+            if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_HXT)
+            {
+                u32ClkSrc = __HXT; /* Clock source is HXT */
+            }
+            else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PLL)
+            {
+                u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+            }
+            else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PCLK1)
+            {
+                u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */
+            }
+            else
+            {
+                u32ClkSrc = __HIRC; /* Clock source is HIRC */
+            }
+        }
+        else if((spi == SPI1) || (spi == SPI1_NS))
+        {
+            if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_HXT)
+            {
+                u32ClkSrc = __HXT; /* Clock source is HXT */
+            }
+            else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PLL)
+            {
+                u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+            }
+            else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PCLK0)
+            {
+                u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */
+            }
+            else
+            {
+                u32ClkSrc = __HIRC; /* Clock source is HIRC */
+            }
+        }
+        else if((spi == SPI2) || (spi == SPI2_NS))
+        {
+            if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_HXT)
+            {
+                u32ClkSrc = __HXT; /* Clock source is HXT */
+            }
+            else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PLL)
+            {
+                u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+            }
+            else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PCLK1)
+            {
+                u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */
+            }
+            else
+            {
+                u32ClkSrc = __HIRC; /* Clock source is HIRC */
+            }
+        }
+        else
+        {
+            if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_HXT)
+            {
+                u32ClkSrc = __HXT; /* Clock source is HXT */
+            }
+            else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PLL)
+            {
+                u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+            }
+            else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PCLK0)
+            {
+                u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */
+            }
+            else
+            {
+                u32ClkSrc = __HIRC; /* Clock source is HIRC */
+            }
+        }
+
+        if(u32BusClock >= u32HCLKFreq)
+        {
+            /* Set DIVIDER = 0 */
+            spi->CLKDIV = 0UL;
+            /* Return master peripheral clock rate */
+            u32RetValue = u32ClkSrc;
+        }
+        else if(u32BusClock >= u32ClkSrc)
+        {
+            /* Set DIVIDER = 0 */
+            spi->CLKDIV = 0UL;
+            /* Return master peripheral clock rate */
+            u32RetValue = u32ClkSrc;
+        }
+        else if(u32BusClock == 0UL)
+        {
+            /* Set DIVIDER to the maximum value 0x1FF. f_spi = f_spi_clk_src / (DIVIDER + 1) */
+            spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;
+            /* Return master peripheral clock rate */
+            u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL));
+        }
+        else
+        {
+            u32Div = (((u32ClkSrc * 10UL) / u32BusClock + 5UL) / 10UL) - 1UL; /* Round to the nearest integer */
+            if(u32Div > 0x1FFUL)
+            {
+                u32Div = 0x1FFUL;
+                spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;
+                /* Return master peripheral clock rate */
+                u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL));
+            }
+            else
+            {
+                spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos);
+                /* Return master peripheral clock rate */
+                u32RetValue = (u32ClkSrc / (u32Div + 1UL));
+            }
+        }
+    }
+    else     /* For slave mode, force the SPI peripheral clock rate to equal APB clock rate. */
+    {
+        /* Default setting: slave selection signal is low level active. */
+        spi->SSCTL = SPI_SS_ACTIVE_LOW;
+
+        /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
+        spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk;
+
+        /* Set DIVIDER = 0 */
+        spi->CLKDIV = 0UL;
+
+        if(!(__PC() & NS_OFFSET))
+        {
+            /* Select PCLK as the clock source of SPI */
+            if((spi == SPI0) || (spi == SPI0_NS))
+            {
+                CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1;
+                /* Return slave peripheral clock rate */
+                u32RetValue = u32PCLK1Freq;
+            }
+            else if((spi == SPI1) || (spi == SPI1_NS))
+            {
+                CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0;
+                /* Return slave peripheral clock rate */
+                u32RetValue = u32PCLK0Freq;
+            }
+            else if((spi == SPI2) || (spi == SPI2_NS))
+            {
+                CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1;
+                /* Return slave peripheral clock rate */
+                u32RetValue = u32PCLK1Freq;
+            }
+            else
+            {
+                CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0;
+                /* Return slave peripheral clock rate */
+                u32RetValue = u32PCLK0Freq;
+            }
+        }
+        else
+        {
+            /* Check clock source of SPI */
+            if((spi == SPI0) || (spi == SPI0_NS))
+            {
+                if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_HXT)
+                {
+                    u32RetValue = __HXT; /* Clock source is HXT */
+                }
+                else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PLL)
+                {
+                    u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+                }
+                else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PCLK1)
+                {
+                    u32RetValue = u32PCLK1Freq; /* Clock source is PCLK1 */
+                }
+                else
+                {
+                    u32RetValue = __HIRC; /* Clock source is HIRC */
+                }
+            }
+            else if((spi == SPI1) || (spi == SPI1_NS))
+            {
+                if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_HXT)
+                {
+                    u32RetValue = __HXT; /* Clock source is HXT */
+                }
+                else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PLL)
+                {
+                    u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+                }
+                else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PCLK0)
+                {
+                    u32RetValue = u32PCLK0Freq; /* Clock source is PCLK0 */
+                }
+                else
+                {
+                    u32RetValue = __HIRC; /* Clock source is HIRC */
+                }
+            }
+            else if((spi == SPI2) || (spi == SPI2_NS))
+            {
+                if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_HXT)
+                {
+                    u32RetValue = __HXT; /* Clock source is HXT */
+                }
+                else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PLL)
+                {
+                    u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+                }
+                else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PCLK1)
+                {
+                    u32RetValue = u32PCLK1Freq; /* Clock source is PCLK1 */
+                }
+                else
+                {
+                    u32RetValue = __HIRC; /* Clock source is HIRC */
+                }
+            }
+            else
+            {
+                if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_HXT)
+                {
+                    u32RetValue = __HXT; /* Clock source is HXT */
+                }
+                else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PLL)
+                {
+                    u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+                }
+                else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PCLK0)
+                {
+                    u32RetValue = u32PCLK0Freq; /* Clock source is PCLK0 */
+                }
+                else
+                {
+                    u32RetValue = __HIRC; /* Clock source is HIRC */
+                }
+            }
+        }
+    }
+
+    return u32RetValue;
+}
+
+/**
+  * @brief  Disable SPI controller.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return None
+  * @details Clear SPIEN bit of SPI_CTL register to disable SPI transfer control.
+  */
+void SPI_Close(SPI_T *spi)
+{
+    spi->CTL &= ~SPI_CTL_SPIEN_Msk;
+}
+
+/**
+  * @brief  Clear RX FIFO buffer.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return None
+  * @details This function will clear SPI RX FIFO buffer. The RXEMPTY (SPI_STATUS[8]) will be set to 1.
+  */
+void SPI_ClearRxFIFO(SPI_T *spi)
+{
+    spi->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk;
+}
+
+/**
+  * @brief  Clear TX FIFO buffer.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return None
+  * @details This function will clear SPI TX FIFO buffer. The TXEMPTY (SPI_STATUS[16]) will be set to 1.
+  * @note The TX shift register will not be cleared.
+  */
+void SPI_ClearTxFIFO(SPI_T *spi)
+{
+    spi->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk;
+}
+
+/**
+  * @brief  Disable the automatic slave selection function.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return None
+  * @details This function will disable the automatic slave selection function and set slave selection signal to inactive state.
+  */
+void SPI_DisableAutoSS(SPI_T *spi)
+{
+    spi->SSCTL &= ~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SS_Msk);
+}
+
+/**
+  * @brief  Enable the automatic slave selection function.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32SSPinMask Specifies slave selection pins. (SPI_SS)
+  * @param[in]  u32ActiveLevel Specifies the active level of slave selection signal. (SPI_SS_ACTIVE_HIGH, SPI_SS_ACTIVE_LOW)
+  * @return None
+  * @details This function will enable the automatic slave selection function. Only available in Master mode.
+  *          The slave selection pin and the active level will be set in this function.
+  */
+void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
+{
+    spi->SSCTL = (spi->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | SPI_SSCTL_AUTOSS_Msk);
+}
+
+/**
+  * @brief  Set the SPI bus clock.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32BusClock The expected frequency of SPI bus clock in Hz.
+  * @return Actual frequency of SPI bus clock.
+  * @details This function is only available in Master mode. The actual clock rate may be different from the target SPI bus clock rate.
+  *          For example, if the SPI source clock rate is 12 MHz and the target SPI bus clock rate is 7 MHz, the actual SPI bus clock
+  *          rate will be 6 MHz.
+  * @note   If u32BusClock = 0, DIVIDER setting will be set to the maximum value.
+  * @note   If u32BusClock >= system clock frequency for Secure, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0.
+  * @note   If u32BusClock >= system clock frequency for Non-Secure, this function does not do anything to avoid the situation that the frequency of
+  *         SPI bus clock cannot be faster than the system clock rate. User should set up carefully.
+  * @note   If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0.
+  */
+uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
+{
+    uint32_t u32ClkSrc, u32HCLKFreq;
+    uint32_t u32Div, u32RetValue;
+
+    /* Get system clock frequency */
+    u32HCLKFreq = CLK_GetHCLKFreq();
+
+    if(u32BusClock >= u32HCLKFreq)
+    {
+        if(!(__PC() & NS_OFFSET))
+        {
+            /* Select PCLK as the clock source of SPI */
+            if((spi == SPI0) || (spi == SPI0_NS))
+            {
+                CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1;
+            }
+            else if((spi == SPI1) || (spi == SPI1_NS))
+            {
+                CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0;
+            }
+            else if((spi == SPI2) || (spi == SPI2_NS))
+            {
+                CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1;
+            }
+            else
+            {
+                CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0;
+            }
+        }
+    }
+
+    /* Check clock source of SPI */
+    if((spi == SPI0) || (spi == SPI0_NS))
+    {
+        if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_HXT)
+        {
+            u32ClkSrc = __HXT; /* Clock source is HXT */
+        }
+        else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PLL)
+        {
+            u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        }
+        else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PCLK1)
+        {
+            u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */
+        }
+        else
+        {
+            u32ClkSrc = __HIRC; /* Clock source is HIRC */
+        }
+    }
+    else if((spi == SPI1) || (spi == SPI1_NS))
+    {
+        if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_HXT)
+        {
+            u32ClkSrc = __HXT; /* Clock source is HXT */
+        }
+        else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PLL)
+        {
+            u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        }
+        else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PCLK0)
+        {
+            u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */
+        }
+        else
+        {
+            u32ClkSrc = __HIRC; /* Clock source is HIRC */
+        }
+    }
+    else if((spi == SPI2) || (spi == SPI2_NS))
+    {
+        if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_HXT)
+        {
+            u32ClkSrc = __HXT; /* Clock source is HXT */
+        }
+        else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PLL)
+        {
+            u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        }
+        else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PCLK1)
+        {
+            u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */
+        }
+        else
+        {
+            u32ClkSrc = __HIRC; /* Clock source is HIRC */
+        }
+    }
+    else
+    {
+        if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_HXT)
+        {
+            u32ClkSrc = __HXT; /* Clock source is HXT */
+        }
+        else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PLL)
+        {
+            u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        }
+        else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PCLK0)
+        {
+            u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */
+        }
+        else
+        {
+            u32ClkSrc = __HIRC; /* Clock source is HIRC */
+        }
+    }
+
+    if(u32BusClock >= u32HCLKFreq)
+    {
+        /* Set DIVIDER = 0 */
+        spi->CLKDIV = 0UL;
+        /* Return master peripheral clock rate */
+        u32RetValue = u32ClkSrc;
+    }
+    else if(u32BusClock >= u32ClkSrc)
+    {
+        /* Set DIVIDER = 0 */
+        spi->CLKDIV = 0UL;
+        /* Return master peripheral clock rate */
+        u32RetValue = u32ClkSrc;
+    }
+    else if(u32BusClock == 0UL)
+    {
+        /* Set DIVIDER to the maximum value 0x1FF. f_spi = f_spi_clk_src / (DIVIDER + 1) */
+        spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;
+        /* Return master peripheral clock rate */
+        u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL));
+    }
+    else
+    {
+        u32Div = (((u32ClkSrc * 10UL) / u32BusClock + 5UL) / 10UL) - 1UL; /* Round to the nearest integer */
+        if(u32Div > 0x1FFUL)
+        {
+            u32Div = 0x1FFUL;
+            spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk;
+            /* Return master peripheral clock rate */
+            u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL));
+        }
+        else
+        {
+            spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos);
+            /* Return master peripheral clock rate */
+            u32RetValue = (u32ClkSrc / (u32Div + 1UL));
+        }
+    }
+
+    return u32RetValue;
+}
+
+/**
+  * @brief  Configure FIFO threshold setting.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 3. If data width is 8 ~ 16 bits, it could be 0 ~ 7.
+  * @param[in]  u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 3. If data width is 8 ~ 16 bits, it could be 0 ~ 7.
+  * @return None
+  * @details Set TX FIFO threshold and RX FIFO threshold configurations.
+  */
+void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
+{
+    spi->FIFOCTL = (spi->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk)) |
+                   (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) |
+                   (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos);
+}
+
+/**
+  * @brief  Get the actual frequency of SPI bus clock. Only available in Master mode.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @return Actual SPI bus clock frequency in Hz.
+  * @details This function will calculate the actual SPI bus clock rate according to the SPIxSEL and DIVIDER settings. Only available in Master mode.
+  */
+uint32_t SPI_GetBusClock(SPI_T *spi)
+{
+    uint32_t u32Div;
+    uint32_t u32ClkSrc;
+
+    /* Get DIVIDER setting */
+    u32Div = (spi->CLKDIV & SPI_CLKDIV_DIVIDER_Msk) >> SPI_CLKDIV_DIVIDER_Pos;
+
+    /* Check clock source of SPI */
+    if((spi == SPI0) || (spi == SPI0_NS))
+    {
+        if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_HXT)
+        {
+            u32ClkSrc = __HXT; /* Clock source is HXT */
+        }
+        else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PLL)
+        {
+            u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        }
+        else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PCLK1)
+        {
+            u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */
+        }
+        else
+        {
+            u32ClkSrc = __HIRC; /* Clock source is HIRC */
+        }
+    }
+    else if((spi == SPI1) || (spi == SPI1_NS))
+    {
+        if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_HXT)
+        {
+            u32ClkSrc = __HXT; /* Clock source is HXT */
+        }
+        else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PLL)
+        {
+            u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        }
+        else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PCLK0)
+        {
+            u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */
+        }
+        else
+        {
+            u32ClkSrc = __HIRC; /* Clock source is HIRC */
+        }
+    }
+    else if((spi == SPI2) || (spi == SPI2_NS))
+    {
+        if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_HXT)
+        {
+            u32ClkSrc = __HXT; /* Clock source is HXT */
+        }
+        else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PLL)
+        {
+            u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        }
+        else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PCLK1)
+        {
+            u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */
+        }
+        else
+        {
+            u32ClkSrc = __HIRC; /* Clock source is HIRC */
+        }
+    }
+    else
+    {
+        if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_HXT)
+        {
+            u32ClkSrc = __HXT; /* Clock source is HXT */
+        }
+        else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PLL)
+        {
+            u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        }
+        else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PCLK0)
+        {
+            u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */
+        }
+        else
+        {
+            u32ClkSrc = __HIRC; /* Clock source is HIRC */
+        }
+    }
+
+    /* Return SPI bus clock rate */
+    return (u32ClkSrc / (u32Div + 1UL));
+}
+
+/**
+  * @brief  Enable interrupt function.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32Mask The combination of all related interrupt enable bits.
+  *                     Each bit corresponds to a interrupt enable bit.
+  *                     This parameter decides which interrupts will be enabled. It is combination of:
+  *                       - \ref SPI_UNIT_INT_MASK
+  *                       - \ref SPI_SSACT_INT_MASK
+  *                       - \ref SPI_SSINACT_INT_MASK
+  *                       - \ref SPI_SLVUR_INT_MASK
+  *                       - \ref SPI_SLVBE_INT_MASK
+  *                       - \ref SPI_TXUF_INT_MASK
+  *                       - \ref SPI_FIFO_TXTH_INT_MASK
+  *                       - \ref SPI_FIFO_RXTH_INT_MASK
+  *                       - \ref SPI_FIFO_RXOV_INT_MASK
+  *                       - \ref SPI_FIFO_RXTO_INT_MASK
+  *
+  * @return None
+  * @details Enable SPI related interrupts specified by u32Mask parameter.
+  */
+void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
+{
+    /* Enable unit transfer interrupt flag */
+    if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK)
+    {
+        spi->CTL |= SPI_CTL_UNITIEN_Msk;
+    }
+
+    /* Enable slave selection signal active interrupt flag */
+    if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK)
+    {
+        spi->SSCTL |= SPI_SSCTL_SSACTIEN_Msk;
+    }
+
+    /* Enable slave selection signal inactive interrupt flag */
+    if((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK)
+    {
+        spi->SSCTL |= SPI_SSCTL_SSINAIEN_Msk;
+    }
+
+    /* Enable slave TX under run interrupt flag */
+    if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK)
+    {
+        spi->SSCTL |= SPI_SSCTL_SLVURIEN_Msk;
+    }
+
+    /* Enable slave bit count error interrupt flag */
+    if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK)
+    {
+        spi->SSCTL |= SPI_SSCTL_SLVBEIEN_Msk;
+    }
+
+    /* Enable slave TX underflow interrupt flag */
+    if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK)
+    {
+        spi->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk;
+    }
+
+    /* Enable TX threshold interrupt flag */
+    if((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK)
+    {
+        spi->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk;
+    }
+
+    /* Enable RX threshold interrupt flag */
+    if((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK)
+    {
+        spi->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk;
+    }
+
+    /* Enable RX overrun interrupt flag */
+    if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK)
+    {
+        spi->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk;
+    }
+
+    /* Enable RX time-out interrupt flag */
+    if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK)
+    {
+        spi->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk;
+    }
+}
+
+/**
+  * @brief  Disable interrupt function.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32Mask The combination of all related interrupt enable bits.
+  *                     Each bit corresponds to a interrupt bit.
+  *                     This parameter decides which interrupts will be disabled. It is combination of:
+  *                       - \ref SPI_UNIT_INT_MASK
+  *                       - \ref SPI_SSACT_INT_MASK
+  *                       - \ref SPI_SSINACT_INT_MASK
+  *                       - \ref SPI_SLVUR_INT_MASK
+  *                       - \ref SPI_SLVBE_INT_MASK
+  *                       - \ref SPI_TXUF_INT_MASK
+  *                       - \ref SPI_FIFO_TXTH_INT_MASK
+  *                       - \ref SPI_FIFO_RXTH_INT_MASK
+  *                       - \ref SPI_FIFO_RXOV_INT_MASK
+  *                       - \ref SPI_FIFO_RXTO_INT_MASK
+  *
+  * @return None
+  * @details Disable SPI related interrupts specified by u32Mask parameter.
+  */
+void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
+{
+    /* Disable unit transfer interrupt flag */
+    if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK)
+    {
+        spi->CTL &= ~SPI_CTL_UNITIEN_Msk;
+    }
+
+    /* Disable slave selection signal active interrupt flag */
+    if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK)
+    {
+        spi->SSCTL &= ~SPI_SSCTL_SSACTIEN_Msk;
+    }
+
+    /* Disable slave selection signal inactive interrupt flag */
+    if((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK)
+    {
+        spi->SSCTL &= ~SPI_SSCTL_SSINAIEN_Msk;
+    }
+
+    /* Disable slave TX under run interrupt flag */
+    if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK)
+    {
+        spi->SSCTL &= ~SPI_SSCTL_SLVURIEN_Msk;
+    }
+
+    /* Disable slave bit count error interrupt flag */
+    if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK)
+    {
+        spi->SSCTL &= ~SPI_SSCTL_SLVBEIEN_Msk;
+    }
+
+    /* Disable slave TX underflow interrupt flag */
+    if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK)
+    {
+        spi->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk;
+    }
+
+    /* Disable TX threshold interrupt flag */
+    if((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK)
+    {
+        spi->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk;
+    }
+
+    /* Disable RX threshold interrupt flag */
+    if((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK)
+    {
+        spi->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk;
+    }
+
+    /* Disable RX overrun interrupt flag */
+    if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK)
+    {
+        spi->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk;
+    }
+
+    /* Disable RX time-out interrupt flag */
+    if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK)
+    {
+        spi->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk;
+    }
+}
+
+/**
+  * @brief  Get interrupt flag.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32Mask The combination of all related interrupt sources.
+  *                     Each bit corresponds to a interrupt source.
+  *                     This parameter decides which interrupt flags will be read. It is combination of:
+  *                       - \ref SPI_UNIT_INT_MASK
+  *                       - \ref SPI_SSACT_INT_MASK
+  *                       - \ref SPI_SSINACT_INT_MASK
+  *                       - \ref SPI_SLVUR_INT_MASK
+  *                       - \ref SPI_SLVBE_INT_MASK
+  *                       - \ref SPI_TXUF_INT_MASK
+  *                       - \ref SPI_FIFO_TXTH_INT_MASK
+  *                       - \ref SPI_FIFO_RXTH_INT_MASK
+  *                       - \ref SPI_FIFO_RXOV_INT_MASK
+  *                       - \ref SPI_FIFO_RXTO_INT_MASK
+  *
+  * @return Interrupt flags of selected sources.
+  * @details Get SPI related interrupt flags specified by u32Mask parameter.
+  */
+uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask)
+{
+    uint32_t u32IntStatus;
+    uint32_t u32IntFlag = 0UL;
+
+    u32IntStatus = spi->STATUS;
+
+    /* Check unit transfer interrupt flag */
+    if((u32Mask & SPI_UNIT_INT_MASK) && (u32IntStatus & SPI_STATUS_UNITIF_Msk))
+    {
+        u32IntFlag |= SPI_UNIT_INT_MASK;
+    }
+
+    /* Check slave selection signal active interrupt flag */
+    if((u32Mask & SPI_SSACT_INT_MASK) && (u32IntStatus & SPI_STATUS_SSACTIF_Msk))
+    {
+        u32IntFlag |= SPI_SSACT_INT_MASK;
+    }
+
+    /* Check slave selection signal inactive interrupt flag */
+    if((u32Mask & SPI_SSINACT_INT_MASK) && (u32IntStatus & SPI_STATUS_SSINAIF_Msk))
+    {
+        u32IntFlag |= SPI_SSINACT_INT_MASK;
+    }
+
+    /* Check slave TX under run interrupt flag */
+    if((u32Mask & SPI_SLVUR_INT_MASK) && (u32IntStatus & SPI_STATUS_SLVURIF_Msk))
+    {
+        u32IntFlag |= SPI_SLVUR_INT_MASK;
+    }
+
+    /* Check slave bit count error interrupt flag */
+    if((u32Mask & SPI_SLVBE_INT_MASK) && (u32IntStatus & SPI_STATUS_SLVBEIF_Msk))
+    {
+        u32IntFlag |= SPI_SLVBE_INT_MASK;
+    }
+
+    /* Check slave TX underflow interrupt flag */
+    if((u32Mask & SPI_TXUF_INT_MASK) && (u32IntStatus & SPI_STATUS_TXUFIF_Msk))
+    {
+        u32IntFlag |= SPI_TXUF_INT_MASK;
+    }
+
+    /* Check TX threshold interrupt flag */
+    if((u32Mask & SPI_FIFO_TXTH_INT_MASK) && (u32IntStatus & SPI_STATUS_TXTHIF_Msk))
+    {
+        u32IntFlag |= SPI_FIFO_TXTH_INT_MASK;
+    }
+
+    /* Check RX threshold interrupt flag */
+    if((u32Mask & SPI_FIFO_RXTH_INT_MASK) && (u32IntStatus & SPI_STATUS_RXTHIF_Msk))
+    {
+        u32IntFlag |= SPI_FIFO_RXTH_INT_MASK;
+    }
+
+    /* Check RX overrun interrupt flag */
+    if((u32Mask & SPI_FIFO_RXOV_INT_MASK) && (u32IntStatus & SPI_STATUS_RXOVIF_Msk))
+    {
+        u32IntFlag |= SPI_FIFO_RXOV_INT_MASK;
+    }
+
+    /* Check RX time-out interrupt flag */
+    if((u32Mask & SPI_FIFO_RXTO_INT_MASK) && (u32IntStatus & SPI_STATUS_RXTOIF_Msk))
+    {
+        u32IntFlag |= SPI_FIFO_RXTO_INT_MASK;
+    }
+
+    return u32IntFlag;
+}
+
+/**
+  * @brief  Clear interrupt flag.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32Mask The combination of all related interrupt sources.
+  *                     Each bit corresponds to a interrupt source.
+  *                     This parameter decides which interrupt flags will be cleared. It could be the combination of:
+  *                       - \ref SPI_UNIT_INT_MASK
+  *                       - \ref SPI_SSACT_INT_MASK
+  *                       - \ref SPI_SSINACT_INT_MASK
+  *                       - \ref SPI_SLVUR_INT_MASK
+  *                       - \ref SPI_SLVBE_INT_MASK
+  *                       - \ref SPI_TXUF_INT_MASK
+  *                       - \ref SPI_FIFO_RXOV_INT_MASK
+  *                       - \ref SPI_FIFO_RXTO_INT_MASK
+  *
+  * @return None
+  * @details Clear SPI related interrupt flags specified by u32Mask parameter.
+  */
+void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask)
+{
+    if(u32Mask & SPI_UNIT_INT_MASK)
+    {
+        spi->STATUS = SPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */
+    }
+
+    if(u32Mask & SPI_SSACT_INT_MASK)
+    {
+        spi->STATUS = SPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */
+    }
+
+    if(u32Mask & SPI_SSINACT_INT_MASK)
+    {
+        spi->STATUS = SPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */
+    }
+
+    if(u32Mask & SPI_SLVUR_INT_MASK)
+    {
+        spi->STATUS = SPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */
+    }
+
+    if(u32Mask & SPI_SLVBE_INT_MASK)
+    {
+        spi->STATUS = SPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */
+    }
+
+    if(u32Mask & SPI_TXUF_INT_MASK)
+    {
+        spi->STATUS = SPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */
+    }
+
+    if(u32Mask & SPI_FIFO_RXOV_INT_MASK)
+    {
+        spi->STATUS = SPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */
+    }
+
+    if(u32Mask & SPI_FIFO_RXTO_INT_MASK)
+    {
+        spi->STATUS = SPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */
+    }
+}
+
+/**
+  * @brief  Get SPI status.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32Mask The combination of all related sources.
+  *                     Each bit corresponds to a source.
+  *                     This parameter decides which flags will be read. It is combination of:
+  *                       - \ref SPI_BUSY_MASK
+  *                       - \ref SPI_RX_EMPTY_MASK
+  *                       - \ref SPI_RX_FULL_MASK
+  *                       - \ref SPI_TX_EMPTY_MASK
+  *                       - \ref SPI_TX_FULL_MASK
+  *                       - \ref SPI_TXRX_RESET_MASK
+  *                       - \ref SPI_SPIEN_STS_MASK
+  *                       - \ref SPI_SSLINE_STS_MASK
+  *
+  * @return Flags of selected sources.
+  * @details Get SPI related status specified by u32Mask parameter.
+  */
+uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask)
+{
+    uint32_t u32TmpStatus;
+    uint32_t u32Flag = 0UL;
+
+    u32TmpStatus = spi->STATUS;
+
+    /* Check busy status */
+    if((u32Mask & SPI_BUSY_MASK) && (u32TmpStatus & SPI_STATUS_BUSY_Msk))
+    {
+        u32Flag |= SPI_BUSY_MASK;
+    }
+
+    /* Check RX empty flag */
+    if((u32Mask & SPI_RX_EMPTY_MASK) && (u32TmpStatus & SPI_STATUS_RXEMPTY_Msk))
+    {
+        u32Flag |= SPI_RX_EMPTY_MASK;
+    }
+
+    /* Check RX full flag */
+    if((u32Mask & SPI_RX_FULL_MASK) && (u32TmpStatus & SPI_STATUS_RXFULL_Msk))
+    {
+        u32Flag |= SPI_RX_FULL_MASK;
+    }
+
+    /* Check TX empty flag */
+    if((u32Mask & SPI_TX_EMPTY_MASK) && (u32TmpStatus & SPI_STATUS_TXEMPTY_Msk))
+    {
+        u32Flag |= SPI_TX_EMPTY_MASK;
+    }
+
+    /* Check TX full flag */
+    if((u32Mask & SPI_TX_FULL_MASK) && (u32TmpStatus & SPI_STATUS_TXFULL_Msk))
+    {
+        u32Flag |= SPI_TX_FULL_MASK;
+    }
+
+    /* Check TX/RX reset flag */
+    if((u32Mask & SPI_TXRX_RESET_MASK) && (u32TmpStatus & SPI_STATUS_TXRXRST_Msk))
+    {
+        u32Flag |= SPI_TXRX_RESET_MASK;
+    }
+
+    /* Check SPIEN flag */
+    if((u32Mask & SPI_SPIEN_STS_MASK) && (u32TmpStatus & SPI_STATUS_SPIENSTS_Msk))
+    {
+        u32Flag |= SPI_SPIEN_STS_MASK;
+    }
+
+    /* Check SPIx_SS line status */
+    if((u32Mask & SPI_SSLINE_STS_MASK) && (u32TmpStatus & SPI_STATUS_SSLINE_Msk))
+    {
+        u32Flag |= SPI_SSLINE_STS_MASK;
+    }
+
+    return u32Flag;
+}
+
+/**
+  * @brief  Get SPI status2.
+  * @param[in]  spi The pointer of the specified SPI module.
+  * @param[in]  u32Mask The combination of all related sources.
+  *                     Each bit corresponds to a source.
+  *                     This parameter decides which flags will be read. It is combination of:
+  *                       - \ref SPI_SLVBENUM_MASK
+  *
+  * @return Flags of selected sources.
+  * @details Get SPI related status specified by u32Mask parameter.
+  */
+uint32_t SPI_GetStatus2(SPI_T *spi, uint32_t u32Mask)
+{
+    uint32_t u32TmpStatus;
+    uint32_t u32Number = 0UL;
+
+    u32TmpStatus = spi->STATUS2;
+
+    /* Check effective bit number of uncompleted RX data status */
+    if(u32Mask & SPI_SLVBENUM_MASK)
+    {
+        u32Number = (u32TmpStatus & SPI_STATUS2_SLVBENUM_Msk) >> SPI_STATUS2_SLVBENUM_Pos;
+    }
+
+    return u32Number;
+}
+
+
+/**
+  * @brief  This function is used to get I2S source clock frequency.
+  * @param[in]  i2s The pointer of the specified I2S module.
+  * @return I2S source clock frequency (Hz).
+  * @details Return the source clock frequency according to the setting of SPI0SEL (CLK_CLKSEL2[5:4]) or SPI1SEL (CLK_CLKSEL2[7:6]) or SPI2SEL (CLK_CLKSEL2[11:10]) or SPI3SEL (CLK_CLKSEL2[13:12]).
+  */
+static uint32_t SPII2S_GetSourceClockFreq(SPI_T *i2s)
+{
+    uint32_t u32Freq;
+
+    if((i2s == SPI0) || (i2s == SPI0_NS))
+    {
+        if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_HXT)
+        {
+            u32Freq = __HXT; /* Clock source is HXT */
+        }
+        else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PLL)
+        {
+            u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        }
+        else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PCLK1)
+        {
+            u32Freq = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */
+        }
+        else
+        {
+            u32Freq = __HIRC; /* Clock source is HIRC */
+        }
+    }
+    else if((i2s == SPI1) || (i2s == SPI1_NS))
+    {
+        if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_HXT)
+        {
+            u32Freq = __HXT; /* Clock source is HXT */
+        }
+        else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PLL)
+        {
+            u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        }
+        else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PCLK0)
+        {
+            u32Freq = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */
+        }
+        else
+        {
+            u32Freq = __HIRC; /* Clock source is HIRC */
+        }
+    }
+    else if((i2s == SPI2) || (i2s == SPI2_NS))
+    {
+        if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_HXT)
+        {
+            u32Freq = __HXT; /* Clock source is HXT */
+        }
+        else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PLL)
+        {
+            u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        }
+        else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PCLK1)
+        {
+            u32Freq = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */
+        }
+        else
+        {
+            u32Freq = __HIRC; /* Clock source is HIRC */
+        }
+    }
+    else
+    {
+        if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_HXT)
+        {
+            u32Freq = __HXT; /* Clock source is HXT */
+        }
+        else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PLL)
+        {
+            u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+        }
+        else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PCLK0)
+        {
+            u32Freq = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */
+        }
+        else
+        {
+            u32Freq = __HIRC; /* Clock source is HIRC */
+        }
+    }
+
+    return u32Freq;
+}
+
+/**
+  * @brief  This function configures some parameters of I2S interface for general purpose use.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @param[in] u32MasterSlave I2S operation mode. Valid values are listed below.
+  *                                     - \ref SPII2S_MODE_MASTER
+  *                                     - \ref SPII2S_MODE_SLAVE
+  * @param[in] u32SampleRate Sample rate
+  * @param[in] u32WordWidth Data length. Valid values are listed below.
+  *                                     - \ref SPII2S_DATABIT_8
+  *                                     - \ref SPII2S_DATABIT_16
+  *                                     - \ref SPII2S_DATABIT_24
+  *                                     - \ref SPII2S_DATABIT_32
+  * @param[in] u32Channels Audio format. Valid values are listed below.
+  *                                     - \ref SPII2S_MONO
+  *                                     - \ref SPII2S_STEREO
+  * @param[in] u32DataFormat Data format. Valid values are listed below.
+  *                                     - \ref SPII2S_FORMAT_I2S
+  *                                     - \ref SPII2S_FORMAT_MSB
+  *                                     - \ref SPII2S_FORMAT_PCMA
+  *                                     - \ref SPII2S_FORMAT_PCMB
+  * @return Real sample rate of master mode or peripheral clock rate of slave mode.
+  * @details This function will reset SPI/I2S controller and configure I2S controller according to the input parameters.
+  *          Set TX FIFO threshold to 2 and RX FIFO threshold to 1. Both the TX and RX functions will be enabled.
+  *          The actual sample rate may be different from the target sample rate. The real sample rate will be returned for reference.
+  * @note   In slave mode for Secure, the SPI peripheral clock rate will equal to APB clock rate.
+  * @note   In slave mode for Non-Secure, the SPI peripheral clock rate will equal to the clock rate set in secure mode.
+  */
+uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat)
+{
+    uint32_t u32Divider;
+    uint32_t u32BitRate, u32SrcClk, u32RetValue;
+    uint32_t u32PCLK0Freq, u32PCLK1Freq;
+
+    if(!(__PC() & NS_OFFSET))
+    {
+        /* Reset SPI/I2S */
+        if((i2s == SPI0) || (i2s == SPI0_NS))
+        {
+            SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk;
+            SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk;
+        }
+        else if((i2s == SPI1) || (i2s == SPI1_NS))
+        {
+            SYS->IPRST1 |= SYS_IPRST1_SPI1RST_Msk;
+            SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk;
+        }
+        else if((i2s == SPI2) || (i2s == SPI2_NS))
+        {
+            SYS->IPRST1 |= SYS_IPRST1_SPI2RST_Msk;
+            SYS->IPRST1 &= ~SYS_IPRST1_SPI2RST_Msk;
+        }
+        else
+        {
+            SYS->IPRST2 |= SYS_IPRST2_SPI3RST_Msk;
+            SYS->IPRST2 &= ~SYS_IPRST2_SPI3RST_Msk;
+        }
+    }
+
+    /* Configure I2S controller */
+    i2s->I2SCTL = u32MasterSlave | u32WordWidth | u32Channels | u32DataFormat;
+    /* Set TX FIFO threshold to 2 and RX FIFO threshold to 1 */
+    i2s->FIFOCTL = SPII2S_FIFO_TX_LEVEL_WORD_2 | SPII2S_FIFO_RX_LEVEL_WORD_2;
+
+    if(u32MasterSlave == SPII2S_MODE_MASTER)
+    {
+        /* Get the source clock rate */
+        u32SrcClk = SPII2S_GetSourceClockFreq(i2s);
+
+        /* Calculate the bit clock rate */
+        u32BitRate = u32SampleRate * ((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1UL) * 16UL;
+        u32Divider = (((((u32SrcClk * 10UL) / u32BitRate) >> 1UL) + 5UL) / 10UL) - 1UL; /* Round to the nearest integer */
+        /* Set BCLKDIV setting */
+        i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_BCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_BCLKDIV_Pos);
+        /* Enable I2S mode for the frequency of peripheral clock. */
+        i2s->I2SCLK |= SPI_I2SCLK_I2SMODE_Msk;
+
+        /* Calculate bit clock rate */
+        u32BitRate = u32SrcClk / ((u32Divider + 1UL) * 2UL);
+        /* Calculate real sample rate */
+        u32SampleRate = u32BitRate / (((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1UL) * 16UL);
+
+        /* Enable TX function, RX function and I2S mode. */
+        i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);
+
+        /* Return the real sample rate */
+        u32RetValue = u32SampleRate;
+    }
+    else
+    {
+        /* Set BCLKDIV = 0 */
+        i2s->I2SCLK &= ~SPI_I2SCLK_BCLKDIV_Msk;
+        /* Get APB0 clock frequency */
+        u32PCLK0Freq = CLK_GetPCLK0Freq();
+        /* Get APB1 clock frequency */
+        u32PCLK1Freq = CLK_GetPCLK1Freq();
+
+        if((i2s == SPI0) || (i2s == SPI0_NS))
+        {
+            if(!(__PC() & NS_OFFSET))
+            {
+                /* Set the peripheral clock rate to equal APB clock rate */
+                CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1;
+                /* Return slave peripheral clock rate */
+                u32RetValue = u32PCLK1Freq;
+            }
+            else
+            {
+                /* Check clock source of I2S */
+                if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_HXT)
+                {
+                    u32RetValue = __HXT; /* Clock source is HXT */
+                }
+                else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PLL)
+                {
+                    u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+                }
+                else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PCLK1)
+                {
+                    u32RetValue = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */
+                }
+                else
+                {
+                    u32RetValue = __HIRC; /* Clock source is HIRC */
+                }
+            }
+            /* Enable I2S slave mode and I2S mode for the frequency of peripheral clock. */
+            i2s->I2SCLK |= (SPI_I2SCLK_I2SSLAVE_Msk | SPI_I2SCLK_I2SMODE_Msk);
+            /* Enable TX function, RX function and I2S mode. */
+            i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);
+        }
+        else if((i2s == SPI1) || (i2s == SPI1_NS))
+        {
+            if(!(__PC() & NS_OFFSET))
+            {
+                /* Set the peripheral clock rate to equal APB clock rate */
+                CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0;
+                /* Return slave peripheral clock rate */
+                u32RetValue = u32PCLK0Freq;
+            }
+            else
+            {
+                /* Check clock source of I2S */
+                if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_HXT)
+                {
+                    u32RetValue = __HXT; /* Clock source is HXT */
+                }
+                else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PLL)
+                {
+                    u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+                }
+                else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PCLK0)
+                {
+                    u32RetValue = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */
+                }
+                else
+                {
+                    u32RetValue = __HIRC; /* Clock source is HIRC */
+                }
+            }
+            /* Enable I2S slave mode and I2S mode for the frequency of peripheral clock. */
+            i2s->I2SCLK |= (SPI_I2SCLK_I2SSLAVE_Msk | SPI_I2SCLK_I2SMODE_Msk);
+            /* Enable TX function, RX function and I2S mode. */
+            i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);
+        }
+        else if((i2s == SPI2) || (i2s == SPI2_NS))
+        {
+            if(!(__PC() & NS_OFFSET))
+            {
+                /* Set the peripheral clock rate to equal APB clock rate */
+                CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1;
+                /* Return slave peripheral clock rate */
+                u32RetValue = u32PCLK1Freq;
+            }
+            else
+            {
+                /* Check clock source of I2S */
+                if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_HXT)
+                {
+                    u32RetValue = __HXT; /* Clock source is HXT */
+                }
+                else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PLL)
+                {
+                    u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+                }
+                else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PCLK1)
+                {
+                    u32RetValue = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */
+                }
+                else
+                {
+                    u32RetValue = __HIRC; /* Clock source is HIRC */
+                }
+            }
+            /* Enable I2S slave mode and I2S mode for the frequency of peripheral clock. */
+            i2s->I2SCLK |= (SPI_I2SCLK_I2SSLAVE_Msk | SPI_I2SCLK_I2SMODE_Msk);
+            /* Enable TX function, RX function and I2S mode. */
+            i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);
+        }
+        else
+        {
+            if(!(__PC() & NS_OFFSET))
+            {
+                /* Set the peripheral clock rate to equal APB clock rate */
+                CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0;
+                /* Return slave peripheral clock rate */
+                u32RetValue = u32PCLK0Freq;
+            }
+            else
+            {
+                /* Check clock source of I2S */
+                if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_HXT)
+                {
+                    u32RetValue = __HXT; /* Clock source is HXT */
+                }
+                else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PLL)
+                {
+                    u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */
+                }
+                else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PCLK0)
+                {
+                    u32RetValue = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */
+                }
+                else
+                {
+                    u32RetValue = __HIRC; /* Clock source is HIRC */
+                }
+            }
+            /* Enable I2S slave mode and I2S mode for the frequency of peripheral clock. */
+            i2s->I2SCLK |= (SPI_I2SCLK_I2SSLAVE_Msk | SPI_I2SCLK_I2SMODE_Msk);
+            /* Enable TX function, RX function and I2S mode. */
+            i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk);
+        }
+    }
+
+    return u32RetValue;
+}
+
+/**
+  * @brief  Disable I2S function.
+  * @param[in]  i2s The pointer of the specified I2S module.
+  * @return None
+  * @details Disable I2S function.
+  */
+void SPII2S_Close(SPI_T *i2s)
+{
+    i2s->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk;
+}
+
+/**
+  * @brief Enable interrupt function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @param[in] u32Mask The combination of all related interrupt enable bits.
+  *            Each bit corresponds to a interrupt source. Valid values are listed below.
+  *            - \ref SPII2S_FIFO_TXTH_INT_MASK
+  *            - \ref SPII2S_FIFO_RXTH_INT_MASK
+  *            - \ref SPII2S_FIFO_RXOV_INT_MASK
+  *            - \ref SPII2S_FIFO_RXTO_INT_MASK
+  *            - \ref SPII2S_TXUF_INT_MASK
+  *            - \ref SPII2S_RIGHT_ZC_INT_MASK
+  *            - \ref SPII2S_LEFT_ZC_INT_MASK
+  *            - \ref SPII2S_SLAVE_ERR_INT_MASK
+  * @return None
+  * @details This function enables the interrupt according to the u32Mask parameter.
+  */
+void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask)
+{
+    /* Enable TX threshold interrupt flag */
+    if((u32Mask & SPII2S_FIFO_TXTH_INT_MASK) == SPII2S_FIFO_TXTH_INT_MASK)
+    {
+        i2s->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk;
+    }
+
+    /* Enable RX threshold interrupt flag */
+    if((u32Mask & SPII2S_FIFO_RXTH_INT_MASK) == SPII2S_FIFO_RXTH_INT_MASK)
+    {
+        i2s->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk;
+    }
+
+    /* Enable RX overrun interrupt flag */
+    if((u32Mask & SPII2S_FIFO_RXOV_INT_MASK) == SPII2S_FIFO_RXOV_INT_MASK)
+    {
+        i2s->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk;
+    }
+
+    /* Enable RX time-out interrupt flag */
+    if((u32Mask & SPII2S_FIFO_RXTO_INT_MASK) == SPII2S_FIFO_RXTO_INT_MASK)
+    {
+        i2s->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk;
+    }
+
+    /* Enable TX underflow interrupt flag */
+    if((u32Mask & SPII2S_TXUF_INT_MASK) == SPII2S_TXUF_INT_MASK)
+    {
+        i2s->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk;
+    }
+
+    /* Enable right channel zero cross interrupt flag */
+    if((u32Mask & SPII2S_RIGHT_ZC_INT_MASK) == SPII2S_RIGHT_ZC_INT_MASK)
+    {
+        i2s->I2SCTL |= SPI_I2SCTL_RZCIEN_Msk;
+    }
+
+    /* Enable left channel zero cross interrupt flag */
+    if((u32Mask & SPII2S_LEFT_ZC_INT_MASK) == SPII2S_LEFT_ZC_INT_MASK)
+    {
+        i2s->I2SCTL |= SPI_I2SCTL_LZCIEN_Msk;
+    }
+
+    /* Enable bit clock loss interrupt flag */
+    if((u32Mask & SPII2S_SLAVE_ERR_INT_MASK) == SPII2S_SLAVE_ERR_INT_MASK)
+    {
+        i2s->I2SCTL |= SPI_I2SCTL_SLVERRIEN_Msk;
+    }
+}
+
+/**
+  * @brief Disable interrupt function.
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @param[in] u32Mask The combination of all related interrupt enable bits.
+  *            Each bit corresponds to a interrupt source. Valid values are listed below.
+  *            - \ref SPII2S_FIFO_TXTH_INT_MASK
+  *            - \ref SPII2S_FIFO_RXTH_INT_MASK
+  *            - \ref SPII2S_FIFO_RXOV_INT_MASK
+  *            - \ref SPII2S_FIFO_RXTO_INT_MASK
+  *            - \ref SPII2S_TXUF_INT_MASK
+  *            - \ref SPII2S_RIGHT_ZC_INT_MASK
+  *            - \ref SPII2S_LEFT_ZC_INT_MASK
+  *            - \ref SPII2S_SLAVE_ERR_INT_MASK
+  * @return None
+  * @details This function disables the interrupt according to the u32Mask parameter.
+  */
+void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask)
+{
+    /* Disable TX threshold interrupt flag */
+    if((u32Mask & SPII2S_FIFO_TXTH_INT_MASK) == SPII2S_FIFO_TXTH_INT_MASK)
+    {
+        i2s->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk;
+    }
+
+    /* Disable RX threshold interrupt flag */
+    if((u32Mask & SPII2S_FIFO_RXTH_INT_MASK) == SPII2S_FIFO_RXTH_INT_MASK)
+    {
+        i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk;
+    }
+
+    /* Disable RX overrun interrupt flag */
+    if((u32Mask & SPII2S_FIFO_RXOV_INT_MASK) == SPII2S_FIFO_RXOV_INT_MASK)
+    {
+        i2s->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk;
+    }
+
+    /* Disable RX time-out interrupt flag */
+    if((u32Mask & SPII2S_FIFO_RXTO_INT_MASK) == SPII2S_FIFO_RXTO_INT_MASK)
+    {
+        i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk;
+    }
+
+    /* Disable TX underflow interrupt flag */
+    if((u32Mask & SPII2S_TXUF_INT_MASK) == SPII2S_TXUF_INT_MASK)
+    {
+        i2s->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk;
+    }
+
+    /* Disable right channel zero cross interrupt flag */
+    if((u32Mask & SPII2S_RIGHT_ZC_INT_MASK) == SPII2S_RIGHT_ZC_INT_MASK)
+    {
+        i2s->I2SCTL &= ~SPI_I2SCTL_RZCIEN_Msk;
+    }
+
+    /* Disable left channel zero cross interrupt flag */
+    if((u32Mask & SPII2S_LEFT_ZC_INT_MASK) == SPII2S_LEFT_ZC_INT_MASK)
+    {
+        i2s->I2SCTL &= ~SPI_I2SCTL_LZCIEN_Msk;
+    }
+
+    /* Disable bit clock loss interrupt flag */
+    if((u32Mask & SPII2S_SLAVE_ERR_INT_MASK) == SPII2S_SLAVE_ERR_INT_MASK)
+    {
+        i2s->I2SCTL &= ~SPI_I2SCTL_SLVERRIEN_Msk;
+    }
+}
+
+/**
+  * @brief  Enable master clock (MCLK).
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @param[in] u32BusClock The target MCLK clock rate.
+  * @return Actual MCLK clock rate
+  * @details Set the master clock rate according to u32BusClock parameter and enable master clock output.
+  *          The actual master clock rate may be different from the target master clock rate. The real master clock rate will be returned for reference.
+  */
+uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock)
+{
+    uint32_t u32Divider;
+    uint32_t u32SrcClk, u32RetValue;
+
+    u32SrcClk = SPII2S_GetSourceClockFreq(i2s);
+    if(u32BusClock == u32SrcClk)
+    {
+        u32Divider = 0UL;
+    }
+    else
+    {
+        u32Divider = (u32SrcClk / u32BusClock) >> 1UL;
+        /* MCLKDIV is a 7-bit width configuration. The maximum value is 0x7F. */
+        if(u32Divider > 0x7FUL)
+        {
+            u32Divider = 0x7FUL;
+        }
+    }
+
+    /* Write u32Divider to MCLKDIV (SPI_I2SCLK[6:0]) */
+    i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_MCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_MCLKDIV_Pos);
+
+    /* Enable MCLK output */
+    i2s->I2SCTL |= SPI_I2SCTL_MCLKEN_Msk;
+
+    if(u32Divider == 0UL)
+    {
+        u32RetValue = u32SrcClk; /* If MCLKDIV=0, master clock rate is equal to the source clock rate. */
+    }
+    else
+    {
+        u32RetValue = ((u32SrcClk >> 1UL) / u32Divider); /* If MCLKDIV>0, master clock rate = source clock rate / (MCLKDIV * 2) */
+    }
+
+    return u32RetValue;
+}
+
+/**
+  * @brief  Disable master clock (MCLK).
+  * @param[in] i2s The pointer of the specified I2S module.
+  * @return None
+  * @details Clear MCLKEN bit of SPI_I2SCTL register to disable master clock output.
+  */
+void SPII2S_DisableMCLK(SPI_T *i2s)
+{
+    i2s->I2SCTL &= ~SPI_I2SCTL_MCLKEN_Msk;
+}
+
+/**
+  * @brief  Configure FIFO threshold setting.
+  * @param[in]  i2s The pointer of the specified I2S module.
+  * @param[in]  u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 3.
+  * @param[in]  u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 3.
+  * @return None
+  * @details Set TX FIFO threshold and RX FIFO threshold configurations.
+  */
+void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
+{
+    i2s->FIFOCTL = (i2s->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk)) |
+                   (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) |
+                   (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos);
+}
+
+/**@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group SPI_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_sys.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_sys.c
new file mode 100644
index 0000000000..8d383ca5f9
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_sys.c
@@ -0,0 +1,441 @@
+/**************************************************************************//**
+ * @file     sys.c
+ * @version  V3.00
+ * @brief    M2354 series System Manager (SYS) driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup SYS_Driver SYS Driver
+  @{
+*/
+
+
+/** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Clear reset source
+  * @param[in]  u32Src is system reset source. Including :
+  *             - \ref SYS_RSTSTS_CPULKRF_Msk
+  *             - \ref SYS_RSTSTS_CPURF_Msk
+  *             - \ref SYS_RSTSTS_SYSRF_Msk
+  *             - \ref SYS_RSTSTS_BODRF_Msk
+  *             - \ref SYS_RSTSTS_LVRF_Msk
+  *             - \ref SYS_RSTSTS_WDTRF_Msk
+  *             - \ref SYS_RSTSTS_PINRF_Msk
+  *             - \ref SYS_RSTSTS_PORF_Msk
+  * @return     None
+  * @details    This function clear the selected system reset source.
+  */
+void SYS_ClearResetSrc(uint32_t u32Src)
+{
+    SYS->RSTSTS = u32Src;
+}
+
+/**
+  * @brief      Get Brown-out detector output status
+  * @param      None
+  * @retval     0 System voltage is higher than BODVL setting or BODEN is 0.
+  * @retval     1 System voltage is lower than BODVL setting.
+  * @details    This function get Brown-out detector output status.
+  */
+uint32_t SYS_GetBODStatus(void)
+{
+    return ((SYS->BODCTL & SYS_BODCTL_BODOUT_Msk) >> SYS_BODCTL_BODOUT_Pos);
+}
+
+/**
+  * @brief      Get reset status register value
+  * @param      None
+  * @return     Reset source
+  * @details    This function get the system reset status register value.
+  */
+uint32_t SYS_GetResetSrc(void)
+{
+    return (SYS->RSTSTS);
+}
+
+/**
+  * @brief      Check if register is locked nor not
+  * @param      None
+  * @retval     0 Write-protection function is disabled.
+  *             1 Write-protection function is enabled.
+  * @details    This function check register write-protection bit setting.
+  */
+uint32_t SYS_IsRegLocked(void)
+{
+    return SYS->REGLCTL & 1UL ? 0UL : 1UL;
+}
+
+/**
+  * @brief      Get product ID
+  * @param      None
+  * @return     Product ID
+  * @details    This function get product ID.
+  */
+uint32_t  SYS_ReadPDID(void)
+{
+    return SYS->PDID;
+}
+
+/**
+  * @brief      Reset chip with chip reset
+  * @param      None
+  * @return     None
+  * @details    This function reset chip with chip reset.
+  *             The register write-protection function should be disabled before using this function.
+  */
+void SYS_ResetChip(void)
+{
+    SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk;
+}
+
+/**
+  * @brief      Reset chip with CPU reset
+  * @param      None
+  * @return     None
+  * @details    This function reset CPU with CPU reset.
+  *             The register write-protection function should be disabled before using this function.
+  */
+void SYS_ResetCPU(void)
+{
+    SYS->IPRST0 |= SYS_IPRST0_CPURST_Msk;
+}
+
+/**
+  * @brief      Reset selected module
+  * @param[in]  u32ModuleIndex is module index. Including :
+  *             - \ref PDMA0_RST
+  *             - \ref PDMA1_RST
+  *             - \ref EBI_RST
+  *             - \ref USBH_RST
+  *             - \ref SDH0_RST
+  *             - \ref CRC_RST
+  *             - \ref CRPT_RST
+  *             - \ref KS_RST
+  *             - \ref GPIO_RST
+  *             - \ref TMR0_RST
+  *             - \ref TMR1_RST
+  *             - \ref TMR2_RST
+  *             - \ref TMR3_RST
+  *             - \ref TMR4_RST
+  *             - \ref TMR5_RST
+  *             - \ref ACMP01_RST
+  *             - \ref I2C0_RST
+  *             - \ref I2C1_RST
+  *             - \ref I2C2_RST
+  *             - \ref QSPI0_RST
+  *             - \ref SPI0_RST
+  *             - \ref SPI1_RST
+  *             - \ref SPI2_RST
+  *             - \ref SPI3_RST
+  *             - \ref UART0_RST
+  *             - \ref UART1_RST
+  *             - \ref UART2_RST
+  *             - \ref UART3_RST
+  *             - \ref UART4_RST
+  *             - \ref UART5_RST
+  *             - \ref CAN0_RST
+  *             - \ref OTG_RST
+  *             - \ref USBD_RST
+  *             - \ref EADC_RST
+  *             - \ref I2S0_RST
+  *             - \ref LCD_RST
+  *             - \ref TRNG_RST
+  *             - \ref SC0_RST
+  *             - \ref SC1_RST
+  *             - \ref SC2_RST
+  *             - \ref USCI0_RST
+  *             - \ref USCI1_RST
+  *             - \ref DAC_RST
+  *             - \ref EPWM0_RST
+  *             - \ref EPWM1_RST
+  *             - \ref BPWM0_RST
+  *             - \ref BPWM1_RST
+  *             - \ref QEI0_RST
+  *             - \ref QEI1_RST
+  *             - \ref ECAP0_RST
+  *             - \ref ECAP1_RST
+  * @return     None
+  * @details    This function reset selected module.
+  */
+void SYS_ResetModule(uint32_t u32ModuleIndex)
+{
+    uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL;
+
+    /* Generate reset signal to the corresponding module */
+    u32TmpVal = (1UL << (u32ModuleIndex & 0x00ffffffUL));
+    u32TmpAddr = (uint32_t)&SYS->IPRST0 + ((u32ModuleIndex >> 24UL));
+    *(uint32_t *)u32TmpAddr |= u32TmpVal;
+
+    /* Release corresponding module from reset state */
+    u32TmpVal = ~(1UL << (u32ModuleIndex & 0x00ffffffUL));
+    *(uint32_t *)u32TmpAddr &= u32TmpVal;
+}
+
+/**
+  * @brief      Enable and configure Brown-out detector function
+  * @param[in]  i32Mode is reset or interrupt mode. Including :
+  *             - \ref SYS_BODCTL_BOD_RST_EN
+  *             - \ref SYS_BODCTL_BOD_INTERRUPT_EN
+  * @param[in]  u32BODLevel is Brown-out voltage level. Including :
+  *             - \ref SYS_BODCTL_BODVL_1_6V
+  *             - \ref SYS_BODCTL_BODVL_1_8V
+  *             - \ref SYS_BODCTL_BODVL_2_0V
+  *             - \ref SYS_BODCTL_BODVL_2_2V
+  *             - \ref SYS_BODCTL_BODVL_2_4V
+  *             - \ref SYS_BODCTL_BODVL_2_6V
+  *             - \ref SYS_BODCTL_BODVL_2_8V
+  *             - \ref SYS_BODCTL_BODVL_3_0V
+  * @return     None
+  * @details    This function configure Brown-out detector reset or interrupt mode, enable Brown-out function and set Brown-out voltage level.
+  *             The register write-protection function should be disabled before using this function.
+  */
+void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel)
+{
+    /* Enable Brown-out Detector function */
+    /* Enable Brown-out interrupt or reset function */
+    /* Select Brown-out Detector threshold voltage */
+    while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk);
+    SYS->BODCTL = (SYS->BODCTL & ~(SYS_BODCTL_BODRSTEN_Msk | SYS_BODCTL_BODVL_Msk)) |
+                  ((uint32_t)i32Mode) | (u32BODLevel) | (SYS_BODCTL_BODEN_Msk);
+}
+
+/**
+  * @brief      Disable Brown-out detector function
+  * @param      None
+  * @return     None
+  * @details    This function disable Brown-out detector function.
+  *             The register write-protection function should be disabled before using this function.
+  */
+void SYS_DisableBOD(void)
+{
+    while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk);
+    SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk;
+}
+
+
+/**
+  * @brief      Set Power Level
+  * @param[in]  u32PowerLevel is power level setting. Including :
+  *             - \ref SYS_PLCTL_PLSEL_PL0  : Supports system clock up to 96MHz.
+  *             - \ref SYS_PLCTL_PLSEL_PL1  : Supports system clock up to 84MHz.
+  *             - \ref SYS_PLCTL_PLSEL_PL2  : Supports system clock up to 48MHz.
+  *             - \ref SYS_PLCTL_PLSEL_PL3  : Supports system clock up to 4MHz.
+  * @return     None
+  * @details    This function select power level.
+  *             The register write-protection function should be disabled before using this function.
+  */
+void SYS_SetPowerLevel(uint32_t u32PowerLevel)
+{
+    /* Set power voltage level */
+    while(SYS->PLCTL & SYS_PLCTL_WRBUSY_Msk);
+    SYS->PLCTL = (SYS->PLCTL & (~SYS_PLCTL_PLSEL_Msk)) | (u32PowerLevel);
+    while(SYS->PLSTS & SYS_PLSTS_PLCBUSY_Msk);
+}
+
+
+/**
+  * @brief      Set Main Voltage Regulator Type
+  * @param[in]  u32PowerRegulator is main voltage regulator type. Including :
+  *             - \ref SYS_PLCTL_MVRS_LDO
+  *             - \ref SYS_PLCTL_MVRS_DCDC
+  * @retval     0  main voltage regulator type setting is not finished
+  * @retval     1  main voltage regulator type setting is finished
+  * @details    This function set main voltage regulator type.
+  *             The main voltage regulator type setting to DCDC cannot finished if the inductor is not detected.
+  *             The register write-protection function should be disabled before using this function.
+  */
+uint32_t SYS_SetPowerRegulator(uint32_t u32PowerRegulator)
+{
+    int32_t i32TimeOutCnt = 400;
+    uint32_t u32Ret = 1U;
+    uint32_t u32PowerRegStatus;
+
+    /* Get main voltage regulator type status */
+    u32PowerRegStatus = SYS->PLSTS & SYS_PLSTS_CURMVR_Msk;
+
+    /* Set main voltage regulator type */
+    if((u32PowerRegulator == SYS_PLCTL_MVRS_DCDC) && (u32PowerRegStatus == SYS_PLSTS_CURMVR_LDO))
+    {
+
+        /* Set main voltage regulator type to DCDC if status is LDO */
+        while(SYS->PLCTL & SYS_PLCTL_WRBUSY_Msk);
+        SYS->PLCTL |= SYS_PLCTL_MVRS_Msk;
+
+        /* Wait inductor detection and main voltage regulator type change ready */
+        while((SYS->PLSTS & SYS_PLSTS_CURMVR_Msk) != SYS_PLSTS_CURMVR_DCDC)
+        {
+            if(i32TimeOutCnt-- <= 0)
+            {
+                u32Ret = 0U;    /* Main voltage regulator type change time-out */
+                break;
+            }
+        }
+
+    }
+    else if(u32PowerRegulator == SYS_PLCTL_MVRS_LDO)
+    {
+
+        /* Set main voltage regulator type to LDO if status is DCDC */
+        while(SYS->PLCTL & SYS_PLCTL_WRBUSY_Msk);
+        SYS->PLCTL &= (~SYS_PLCTL_MVRS_Msk);
+
+        /* Wait main voltage regulator type change ready */
+        while((SYS->PLSTS & SYS_PLSTS_CURMVR_Msk) != SYS_PLSTS_CURMVR_LDO)
+        {
+            if(i32TimeOutCnt-- <= 0)
+            {
+                u32Ret = 0U;    /* Main voltage regulator type change time-out */
+                break;
+            }
+        }
+
+    }
+
+    /* Clear main voltage regulator type change error flag */
+    if(SYS->PLSTS & SYS_PLSTS_MVRCERR_Msk)
+    {
+        SYS->PLSTS = SYS_PLSTS_MVRCERR_Msk;
+        u32Ret = 0U;
+    }
+
+    return u32Ret;
+}
+
+/**
+  * @brief      Set System SRAM Power Mode
+  * @param[in]  u32SRAMSel is SRAM region selection. Including :
+  *             - \ref SYS_SRAMPC0_SRAM0PM0_Msk     : 0x2000_0000 - 0x2000_0FFF
+  *             - \ref SYS_SRAMPC0_SRAM0PM1_Msk     : 0x2000_1000 - 0x2000_1FFF
+  *             - \ref SYS_SRAMPC0_SRAM0PM2_Msk     : 0x2000_2000 - 0x2000_3FFF
+  *             - \ref SYS_SRAMPC0_SRAM0PM3_Msk     : 0x2000_4000 - 0x2000_5FFF
+  *             - \ref SYS_SRAMPC0_SRAM0PM4_Msk     : 0x2000_6000 - 0x2000_7FFF
+  *             - \ref SYS_SRAMPC0_SRAM1PM0_Msk     : 0x2000_8000 - 0x2000_BFFF
+  *             - \ref SYS_SRAMPC0_SRAM1PM1_Msk     : 0x2000_C000 - 0x2000_FFFF
+  *             - \ref SYS_SRAMPC0_SRAM1PM2_Msk     : 0x2001_0000 - 0x2001_3FFF
+  *             - \ref SYS_SRAMPC0_SRAM1PM3_Msk     : 0x2001_4000 - 0x2001_7FFF
+  *             - \ref SYS_SRAMPC0_SRAM1PM4_Msk     : 0x2001_8000 - 0x2001_BFFF
+  *             - \ref SYS_SRAMPC0_SRAM1PM5_Msk     : 0x2001_C000 - 0x2001_FFFF
+  *             - \ref SYS_SRAMPC0_SRAM1PM6_Msk     : 0x2002_0000 - 0x2002_3FFF
+  *             - \ref SYS_SRAMPC0_SRAM1PM7_Msk     : 0x2002_4000 - 0x2002_7FFF
+  *             - \ref SYS_SRAMPC0_SRAM2PM0_Msk     : 0x2002_8000 - 0x2002_BFFF
+  *             - \ref SYS_SRAMPC0_SRAM2PM1_Msk     : 0x2002_C000 - 0x2002_FFFF
+  *             - \ref SYS_SRAMPC1_SRAM2PM2_Msk     : 0x2003_0000 - 0x2003_3FFF
+  *             - \ref SYS_SRAMPC1_SRAM2PM3_Msk     : 0x2003_4000 - 0x2003_7FFF
+  *             - \ref SYS_SRAMPC1_SRAM2PM4_Msk     : 0x2003_8000 - 0x2003_BFFF
+  *             - \ref SYS_SRAMPC1_SRAM2PM5_Msk     : 0x2003_C000 - 0x2003_FFFF
+  * @param[in]  u32PowerMode is SRAM power mode. Including :
+  *             - \ref SYS_SRAMPC0_SRAM_NORMAL
+  *             - \ref SYS_SRAMPC0_SRAM_RETENTION
+  *             - \ref SYS_SRAMPC0_SRAM_POWER_SHUT_DOWN
+  *             - \ref SYS_SRAMPC1_SRAM_NORMAL
+  *             - \ref SYS_SRAMPC1_SRAM_RETENTION
+  *             - \ref SYS_SRAMPC1_SRAM_POWER_SHUT_DOWN
+  * @return     None
+  * @details    This function set system SRAM power mode.
+  *             The register write-protection function should be disabled before using this function.
+  */
+void SYS_SetSSRAMPowerMode(uint32_t u32SRAMSel, uint32_t u32PowerMode)
+{
+    uint32_t u32SRAMSelPos = 0UL;
+
+    /* Get system SRAM power mode setting position */
+    while(u32SRAMSelPos < 30UL)
+    {
+        if(u32SRAMSel & (1 << u32SRAMSelPos))
+        {
+            break;
+        }
+        else
+        {
+            u32SRAMSelPos++;
+        }
+    }
+
+    /* Set system SRAM power mode setting */
+    if(u32PowerMode & BIT31)
+    {
+        while(SYS->SRAMPC1 & SYS_SRAMPC1_PCBUSY_Msk);
+        SYS->SRAMPC1 = (SYS->SRAMPC1 & (~u32SRAMSel)) | (u32PowerMode << u32SRAMSelPos);
+    }
+    else
+    {
+        while(SYS->SRAMPC0 & SYS_SRAMPC0_PCBUSY_Msk);
+        SYS->SRAMPC0 = (SYS->SRAMPC0 & (~u32SRAMSel)) | (u32PowerMode << u32SRAMSelPos);
+
+    }
+}
+
+/**
+  * @brief      Set Peripheral SRAM Power Mode
+  * @param[in]  u32SRAMSel is SRAM region selection. Including :
+  *             - \ref SYS_SRAMPC1_CAN_Msk
+  *             - \ref SYS_SRAMPC1_USBD_Msk
+  *             - \ref SYS_SRAMPC1_PDMA0_Msk
+  *             - \ref SYS_SRAMPC1_PDMA1_Msk
+  *             - \ref SYS_SRAMPC1_FMCCACHE_Msk
+  *             - \ref SYS_SRAMPC1_RSA_Msk
+  *             - \ref SYS_SRAMPC1_KS_Msk
+  * @param[in]  u32PowerMode is SRAM power mode. Including :
+  *             - \ref SYS_SRAMPC1_SRAM_NORMAL
+  *             - \ref SYS_SRAMPC1_SRAM_RETENTION
+  *             - \ref SYS_SRAMPC1_SRAM_POWER_SHUT_DOWN
+  * @return     None
+  * @details    This function set peripheral SRAM power mode.
+  *             The register write-protection function should be disabled before using this function.
+  */
+void SYS_SetPSRAMPowerMode(uint32_t u32SRAMSel, uint32_t u32PowerMode)
+{
+    uint32_t u32SRAMSelPos = 16UL;
+
+    /* Get peripheral SRAM power mode setting position */
+    while(u32SRAMSelPos < 30UL)
+    {
+        if(u32SRAMSel & (1 << u32SRAMSelPos))
+        {
+            break;
+        }
+        else
+        {
+            u32SRAMSelPos++;
+        }
+    }
+
+    /* Set peripheral SRAM power mode setting */
+    while(SYS->SRAMPC1 & SYS_SRAMPC1_PCBUSY_Msk);
+    SYS->SRAMPC1 = (SYS->SRAMPC1 & (~u32SRAMSel)) | (u32PowerMode << u32SRAMSelPos);
+}
+
+/**
+  * @brief      Set Reference Voltage
+  * @param[in]  u32VRefCTL is reference voltage setting. Including :
+  *             - \ref SYS_VREFCTL_VREF_PIN
+  *             - \ref SYS_VREFCTL_VREF_1_6V
+  *             - \ref SYS_VREFCTL_VREF_2_0V
+  *             - \ref SYS_VREFCTL_VREF_2_5V
+  *             - \ref SYS_VREFCTL_VREF_3_0V
+  *             - \ref SYS_VREFCTL_VREF_AVDD
+  * @return     None
+  * @details    This function select reference voltage.
+  *             The register write-protection function should be disabled before using this function.
+  */
+void SYS_SetVRef(uint32_t u32VRefCTL)
+{
+    /* Set reference voltage */
+    SYS->VREFCTL = (SYS->VREFCTL & (~SYS_VREFCTL_VREFCTL_Msk)) | (u32VRefCTL);
+}
+
+
+/**@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group SYS_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_tamper.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_tamper.c
new file mode 100644
index 0000000000..a704728920
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_tamper.c
@@ -0,0 +1,505 @@
+/**************************************************************************//**
+ * @file     tamper.c
+ * @version  V3.00
+ * @brief    M2354 series TAMPER driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup TAMPER_Driver Tamper Driver
+  @{
+*/
+
+/** @addtogroup TAMPER_EXPORTED_FUNCTIONS Tamper Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Enable Tamper Interrupt
+  *
+  * @param[in]  u32IntFlagMask      Specify the interrupt source. It consists of:
+  *                                 - \ref TAMPER_INTEN_TAMP0IEN_Msk
+  *                                 - \ref TAMPER_INTEN_TAMP1IEN_Msk
+  *                                 - \ref TAMPER_INTEN_TAMP2IEN_Msk
+  *                                 - \ref TAMPER_INTEN_TAMP3IEN_Msk
+  *                                 - \ref TAMPER_INTEN_TAMP4IEN_Msk
+  *                                 - \ref TAMPER_INTEN_TAMP5IEN_Msk
+  *                                 - \ref TAMPER_INTEN_CLKFIEN_Msk
+  *                                 - \ref TAMPER_INTEN_CLKSTOPIEN_Msk
+  *                                 - \ref TAMPER_INTEN_OVPIEN_Msk
+  *                                 - \ref TAMPER_INTEN_VGPIEN_Msk
+  *                                 - \ref TAMPER_INTEN_VGNIEN_Msk
+  *                                 - \ref TAMPER_INTEN_ACTSIEN_Msk
+  *                                 - \ref TAMPER_INTEN_RTCLVRIEN_Msk
+  *                                 - \ref TAMPER_INTEN_RTCIOIEN_Msk
+  *                                 - \ref TAMPER_INTEN_RTCLKIEN_Msk
+  *                                 - \ref TAMPER_INTEN_BODIEN_Msk
+  *
+  * @return     None
+  *
+  * @details    This API is used to enable the specify tamper interrupt function.
+  */
+void TAMPER_EnableInt(uint32_t u32IntFlagMask)
+{
+    TAMPER->INTEN |= u32IntFlagMask;
+}
+
+/**
+  * @brief      Disable Tamper Interrupt
+  *
+  * @param[in]  u32IntFlagMask      Specify the interrupt source. It consists of:
+  *                                 - \ref TAMPER_INTEN_TAMP0IEN_Msk
+  *                                 - \ref TAMPER_INTEN_TAMP1IEN_Msk
+  *                                 - \ref TAMPER_INTEN_TAMP2IEN_Msk
+  *                                 - \ref TAMPER_INTEN_TAMP3IEN_Msk
+  *                                 - \ref TAMPER_INTEN_TAMP4IEN_Msk
+  *                                 - \ref TAMPER_INTEN_TAMP5IEN_Msk
+  *                                 - \ref TAMPER_INTEN_CLKFIEN_Msk
+  *                                 - \ref TAMPER_INTEN_CLKSTOPIEN_Msk
+  *                                 - \ref TAMPER_INTEN_OVPIEN_Msk
+  *                                 - \ref TAMPER_INTEN_VGPIEN_Msk
+  *                                 - \ref TAMPER_INTEN_VGNIEN_Msk
+  *                                 - \ref TAMPER_INTEN_ACTSIEN_Msk
+  *                                 - \ref TAMPER_INTEN_RTCLVRIEN_Msk
+  *                                 - \ref TAMPER_INTEN_RTCIOIEN_Msk
+  *                                 - \ref TAMPER_INTEN_RTCLKIEN_Msk
+  *                                 - \ref TAMPER_INTEN_BODIEN_Msk
+  *
+  * @return     None
+  *
+  * @details    This API is used to disable the specify tamper interrupt function.
+  */
+void TAMPER_DisableInt(uint32_t u32IntFlagMask)
+{
+    TAMPER->INTEN &= ~u32IntFlagMask;
+}
+
+/**
+  * @brief      Static Tamper Detect
+  *
+  * @param[in]  u32TamperSelect     Tamper pin select. Possible options are
+  *                                 - \ref TAMPER_TAMPER0_SELECT
+  *                                 - \ref TAMPER_TAMPER1_SELECT
+  *                                 - \ref TAMPER_TAMPER2_SELECT
+  *                                 - \ref TAMPER_TAMPER3_SELECT
+  *                                 - \ref TAMPER_TAMPER4_SELECT
+  *                                 - \ref TAMPER_TAMPER5_SELECT
+  *
+  * @param[in]  u32DetecLevel       Tamper pin detection level select. Possible options are
+  *                                 - \ref TAMPER_TAMPER_HIGH_LEVEL_DETECT
+  *                                 - \ref TAMPER_TAMPER_LOW_LEVEL_DETECT
+  *
+  * @param[in]  u32DebounceEn       Tamper pin de-bounce enable
+  *                                 - \ref TAMPER_TAMPER_DEBOUNCE_ENABLE
+  *                                 - \ref TAMPER_TAMPER_DEBOUNCE_DISABLE
+  *
+  * @return     None
+  *
+  * @details    This API is used to enable the tamper pin detect function with specify trigger condition.
+  *             User needs to disable dynamic tamper function before use this API.
+  */
+void TAMPER_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn)
+{
+    uint32_t i;
+    uint32_t u32Reg;
+    uint32_t u32TmpReg;
+
+    u32Reg = TAMPER->TIOCTL;
+
+    u32TmpReg = (TAMPER_TIOCTL_TAMP0EN_Msk | (u32DetecLevel << TAMPER_TIOCTL_TAMP0LV_Pos) |
+                 (u32DebounceEn << TAMPER_TIOCTL_TAMP0DBEN_Pos));
+
+    for(i = 0UL; i < (uint32_t)TAMPER_MAX_TAMPER_PIN_NUM; i++)
+    {
+        if(u32TamperSelect & (0x1UL << i))
+        {
+            u32Reg &= ~((TAMPER_TIOCTL_TAMP0EN_Msk | TAMPER_TIOCTL_TAMP0LV_Msk | TAMPER_TIOCTL_TAMP0DBEN_Msk) << (i * 4UL));
+            u32Reg |= (u32TmpReg << (i * 4UL));
+        }
+    }
+
+    TAMPER->TIOCTL = u32Reg;
+}
+
+/**
+  * @brief      Static Tamper Disable
+  *
+  * @param[in]  u32TamperSelect     Tamper pin select. Possible options are
+  *                                 - \ref TAMPER_TAMPER0_SELECT
+  *                                 - \ref TAMPER_TAMPER1_SELECT
+  *                                 - \ref TAMPER_TAMPER2_SELECT
+  *                                 - \ref TAMPER_TAMPER3_SELECT
+  *                                 - \ref TAMPER_TAMPER4_SELECT
+  *                                 - \ref TAMPER_TAMPER5_SELECT
+  *
+  * @return     None
+  *
+  * @details    This API is used to disable the static tamper pin detect.
+  */
+void TAMPER_StaticTamperDisable(uint32_t u32TamperSelect)
+{
+    uint32_t i;
+    uint32_t u32Reg;
+    uint32_t u32TmpReg;
+
+    u32Reg = TAMPER->TIOCTL;
+
+    u32TmpReg = TAMPER_TIOCTL_TAMP0EN_Msk;
+
+    for(i = 0UL; i < (uint32_t)TAMPER_MAX_TAMPER_PIN_NUM; i++)
+    {
+        if(u32TamperSelect & (0x1UL << i))
+        {
+            u32Reg &= ~(u32TmpReg << (i * 4UL));
+        }
+    }
+
+    TAMPER->TIOCTL = u32Reg;
+}
+
+/**
+  * @brief      Dynamic Tamper Detect
+  *
+  * @param[in]  u32PairSel          Tamper pin detection enable. Possible options are
+  *                                 - \ref TAMPER_PAIR0_SELECT
+  *                                 - \ref TAMPER_PAIR1_SELECT
+  *                                 - \ref TAMPER_PAIR2_SELECT
+  *
+  * @param[in]  u32DebounceEn       Tamper pin de-bounce enable
+  *                                 - \ref TAMPER_TAMPER_DEBOUNCE_ENABLE
+  *                                 - \ref TAMPER_TAMPER_DEBOUNCE_DISABLE
+  *
+  *  @param[in]  u32Pair1Source     Dynamic pair 1 input source select
+  *                                 0: Pair 1 source select tamper 2
+  *                                 1: Pair 1 source select tamper 0
+  *
+  *  @param[in]  u32Pair2Source     Dynamic pair 2 input source select
+  *                                 0: Pair 2 source select tamper 4
+  *                                 1: Pair 2 source select tamper 0
+  *
+  * @return     None
+  *
+  * @details    This API is used to enable the dynamic tamper.
+  */
+void TAMPER_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32_t u32Pair1Source, uint32_t u32Pair2Source)
+{
+    uint32_t i;
+    uint32_t u32Reg;
+    uint32_t u32TmpReg;
+    uint32_t u32Tamper2Debounce, u32Tamper4Debounce;
+
+    u32Reg = TAMPER->TIOCTL;
+    u32Reg &= ~(TAMPER_TIOCTL_TAMP0EN_Msk | TAMPER_TIOCTL_TAMP1EN_Msk | TAMPER_TIOCTL_TAMP2EN_Msk |
+                TAMPER_TIOCTL_TAMP3EN_Msk | TAMPER_TIOCTL_TAMP4EN_Msk | TAMPER_TIOCTL_TAMP5EN_Msk);
+
+    u32Tamper2Debounce = u32Reg & TAMPER_TIOCTL_TAMP2DBEN_Msk;
+    u32Tamper4Debounce = u32Reg & TAMPER_TIOCTL_TAMP4DBEN_Msk;
+
+    u32Reg &= ~(TAMPER_TIOCTL_TAMP0EN_Msk | TAMPER_TIOCTL_TAMP1EN_Msk | TAMPER_TIOCTL_TAMP2EN_Msk |
+                TAMPER_TIOCTL_TAMP3EN_Msk | TAMPER_TIOCTL_TAMP4EN_Msk | TAMPER_TIOCTL_TAMP5EN_Msk);
+    u32Reg &= ~(TAMPER_TIOCTL_DYN1ISS_Msk | TAMPER_TIOCTL_DYN2ISS_Msk);
+    u32Reg |= ((u32Pair1Source & 0x1UL) << TAMPER_TIOCTL_DYN1ISS_Pos) | ((u32Pair2Source & 0x1UL) << TAMPER_TIOCTL_DYN2ISS_Pos);
+
+    if(u32DebounceEn)
+    {
+        u32TmpReg = (TAMPER_TIOCTL_TAMP0EN_Msk | TAMPER_TIOCTL_TAMP1EN_Msk |
+                     TAMPER_TIOCTL_TAMP0DBEN_Msk | TAMPER_TIOCTL_TAMP1DBEN_Msk | TAMPER_TIOCTL_DYNPR0EN_Msk);
+    }
+    else
+    {
+        u32TmpReg = (TAMPER_TIOCTL_TAMP0EN_Msk | TAMPER_TIOCTL_TAMP1EN_Msk | TAMPER_TIOCTL_DYNPR0EN_Msk);
+    }
+
+    for(i = 0UL; i < (uint32_t)TAMPER_MAX_PAIR_NUM; i++)
+    {
+        if(u32PairSel & (0x1UL << i))
+        {
+            u32Reg &= ~((TAMPER_TIOCTL_TAMP0DBEN_Msk | TAMPER_TIOCTL_TAMP1DBEN_Msk) << (i * 8UL));
+            u32Reg |= (u32TmpReg << (i * 8UL));
+        }
+    }
+
+    if((u32Pair1Source) && (u32PairSel & (uint32_t)TAMPER_PAIR1_SELECT))
+    {
+        u32Reg &= ~TAMPER_TIOCTL_TAMP2EN_Msk;
+        u32Reg |= u32Tamper2Debounce;
+    }
+
+    if((u32Pair2Source) && (u32PairSel & (uint32_t)TAMPER_PAIR2_SELECT))
+    {
+        u32Reg &= ~TAMPER_TIOCTL_TAMP4EN_Msk;
+        u32Reg |= u32Tamper4Debounce;
+    }
+
+    TAMPER->TIOCTL = u32Reg;
+}
+
+/**
+  * @brief      Dynamic Tamper Disable
+  *
+  * @param[in]  u32PairSel          Tamper pin detection disable. Possible options are
+  *                                 - \ref TAMPER_PAIR0_SELECT
+  *                                 - \ref TAMPER_PAIR1_SELECT
+  *                                 - \ref TAMPER_PAIR2_SELECT
+  *
+  * @return     None
+  *
+  * @details    This API is used to disable the dynamic tamper.
+  */
+void TAMPER_DynamicTamperDisable(uint32_t u32PairSel)
+{
+    uint32_t i;
+    uint32_t u32Reg;
+    uint32_t u32TmpReg;
+    uint32_t u32Tamper2En = 0UL, u32Tamper4En = 0UL;
+
+    u32Reg = TAMPER->TIOCTL;
+
+    if((u32Reg & (uint32_t)TAMPER_TIOCTL_DYN1ISS_Msk) && (u32PairSel & (uint32_t)TAMPER_PAIR1_SELECT))
+    {
+        u32Tamper2En = u32Reg & TAMPER_TIOCTL_TAMP2EN_Msk;
+    }
+
+    if((u32Reg & (uint32_t)TAMPER_TIOCTL_DYN2ISS_Msk) && (u32PairSel & (uint32_t)TAMPER_PAIR2_SELECT))
+    {
+        u32Tamper4En = u32Reg & TAMPER_TIOCTL_TAMP4EN_Msk;
+    }
+
+    u32TmpReg = (TAMPER_TIOCTL_TAMP0EN_Msk | TAMPER_TIOCTL_TAMP1EN_Msk | TAMPER_TIOCTL_DYNPR0EN_Msk);
+
+    for(i = 0UL; i < (uint32_t)TAMPER_MAX_PAIR_NUM; i++)
+    {
+        if(u32PairSel & (0x1UL << i))
+        {
+            u32Reg &= ~(u32TmpReg << ((i * 8UL)));
+        }
+    }
+
+    u32Reg |= (u32Tamper2En | u32Tamper4En);
+
+    TAMPER->TIOCTL = u32Reg;
+}
+
+/**
+  * @brief      Config Dynamic Tamper
+  *
+  * @param[in]  u32ChangeRate       The dynamic tamper output change rate
+  *                                 - \ref TAMPER_2POW6_CLK
+  *                                 - \ref TAMPER_2POW7_CLK
+  *                                 - \ref TAMPER_2POW8_CLK
+  *                                 - \ref TAMPER_2POW9_CLK
+  *                                 - \ref TAMPER_2POW10_CLK
+  *                                 - \ref TAMPER_2POW11_CLK
+  *                                 - \ref TAMPER_2POW12_CLK
+  *                                 - \ref TAMPER_2POW13_CLK
+  *
+  * @param[in]  u32SeedReload       Reload new seed or not
+  *                                 0: not reload new seed
+  *                                 1: reload new seed
+  *
+  * @param[in]  u32RefPattern       Reference pattern
+  *                                 - \ref TAMPER_REF_RANDOM_PATTERN
+  *                                 - \ref TAMPER_REF_SEED
+  *
+  * @param[in]  u32Seed             Seed Value (0x0 ~ 0xFFFFFFFF)
+  *
+  * @return     None
+  *
+  * @details    This API is used to config dynamic tamper setting.
+  */
+void TAMPER_DynamicTamperConfig(uint32_t u32ChangeRate, uint32_t u32SeedReload, uint32_t u32RefPattern, uint32_t u32Seed)
+{
+    uint32_t u32Reg;
+
+    u32Reg = TAMPER->TIOCTL;
+
+    u32Reg &= ~(TAMPER_TIOCTL_DYNSRC_Msk | TAMPER_TIOCTL_SEEDRLD_Msk | TAMPER_TIOCTL_DYNRATE_Msk);
+
+    u32Reg |= (u32ChangeRate) | ((u32SeedReload & 0x1UL) << TAMPER_TIOCTL_SEEDRLD_Pos) |
+              ((u32RefPattern & 0x1UL) << TAMPER_TIOCTL_DYNSRC_Pos);
+
+    TAMPER->SEED = u32Seed; /* Need to set seed value before reloaded seed */
+    TAMPER->TIOCTL = u32Reg;
+}
+
+/**
+  * @brief      Active Shield Dynamic Tamper Detect
+  *
+  * @param[in]  u32PairSel1/2       Active shield 1/2 tamper pin detection enable. Possible options are
+  *                                 - \ref TAMPER_PAIR0_SELECT
+  *                                 - \ref TAMPER_PAIR1_SELECT
+  *                                 - \ref TAMPER_PAIR2_SELECT
+  *
+  *  @param[in]  u32Pair1Source1/2  Active shield 1/2 dynamic pair 1 input source select
+  *                                 0: Pair 1 source select tamper 2
+  *                                 1: Pair 1 source select tamper 0
+  *
+  * @return     None
+  *
+  * @details    This API is used to enable the active shield dynamic tamper.
+  */
+void TAMPER_ActiveShieldDynamicTamperEnable(uint32_t u32PairSel1, uint32_t u32Pair1Source1, uint32_t u32PairSel2, uint32_t u32Pair1Source2)
+{
+    uint32_t i;
+    uint32_t u32Reg1, u32Reg2;
+    uint32_t u32TmpReg1, u32TmpReg2;
+
+    u32Reg1 = TAMPER->ACTSTIOCTL1;
+    u32Reg1 &= ~(TAMPER_ACTSTIOCTL1_ATAMP0EN_Msk | TAMPER_ACTSTIOCTL1_ATAMP1EN_Msk | TAMPER_ACTSTIOCTL1_ATAMP2EN_Msk |
+                 TAMPER_ACTSTIOCTL1_ATAMP3EN_Msk | TAMPER_ACTSTIOCTL1_ATAMP4EN_Msk | TAMPER_ACTSTIOCTL1_ATAMP5EN_Msk);
+    u32Reg2 = TAMPER->ACTSTIOCTL2;
+    u32Reg2 &= ~(TAMPER_ACTSTIOCTL2_ATAMP0EN2_Msk | TAMPER_ACTSTIOCTL2_ATAMP1EN2_Msk | TAMPER_ACTSTIOCTL2_ATAMP2EN2_Msk |
+                 TAMPER_ACTSTIOCTL2_ATAMP3EN2_Msk | TAMPER_ACTSTIOCTL2_ATAMP4EN2_Msk | TAMPER_ACTSTIOCTL2_ATAMP5EN2_Msk);
+
+    u32Reg1 &= ~(TAMPER_ACTSTIOCTL1_ADYN1ISS_Msk);
+    u32Reg1 |= ((u32Pair1Source1 & 0x1UL) << TAMPER_ACTSTIOCTL1_ADYN1ISS_Pos);
+    u32Reg2 &= ~(TAMPER_ACTSTIOCTL2_ADYN1ISS2_Msk);
+    u32Reg2 |= ((u32Pair1Source2 & 0x1UL) << TAMPER_ACTSTIOCTL2_ADYN1ISS2_Pos);
+
+    u32TmpReg1 = (TAMPER_ACTSTIOCTL1_ATAMP0EN_Msk | TAMPER_ACTSTIOCTL1_ATAMP1EN_Msk | TAMPER_ACTSTIOCTL1_ADYNPR0EN_Msk);
+    u32TmpReg2 = (TAMPER_ACTSTIOCTL2_ATAMP0EN2_Msk | TAMPER_ACTSTIOCTL2_ATAMP1EN2_Msk | TAMPER_ACTSTIOCTL2_ADYNPR0EN2_Msk);
+
+    for(i = 0UL; i < (uint32_t)TAMPER_MAX_PAIR_NUM; i++)
+    {
+        if(u32PairSel1 & (0x1UL << i))
+        {
+            u32Reg1 |= (u32TmpReg1 << (i * 8UL));
+        }
+
+        if(u32PairSel2 & (0x1UL << i))
+        {
+            u32Reg2 |= (u32TmpReg2 << (i * 8UL));
+        }
+    }
+
+    if((u32Pair1Source1) && (u32PairSel1 & (uint32_t)TAMPER_PAIR1_SELECT))
+    {
+        u32Reg1 &= ~TAMPER_ACTSTIOCTL1_ATAMP2EN_Msk;
+    }
+
+    if((u32Pair1Source2) && (u32PairSel2 & (uint32_t)TAMPER_PAIR1_SELECT))
+    {
+        u32Reg2 &= ~TAMPER_ACTSTIOCTL2_ATAMP2EN2_Msk;
+    }
+
+    TAMPER->ACTSTIOCTL1 = u32Reg1;
+    TAMPER->ACTSTIOCTL2 = u32Reg2;
+}
+
+/**
+  * @brief      Active Shield Dynamic Tamper Disable
+  *
+  * @param[in]  u32PairSel1/2       Active shield 1/2 tamper pin detection disable. Possible options are
+  *                                 - \ref TAMPER_PAIR0_SELECT
+  *                                 - \ref TAMPER_PAIR1_SELECT
+  *                                 - \ref TAMPER_PAIR2_SELECT
+  *
+  * @return     None
+  *
+  * @details    This API is used to disable the active shield dynamic tamper.
+  */
+void TAMPER_ActiveShieldDynamicTamperDisable(uint32_t u32PairSel1, uint32_t u32PairSel2)
+{
+    uint32_t i;
+    uint32_t u32Reg1, u32Reg2;
+    uint32_t u32TmpReg1, u32TmpReg2;
+    uint32_t u32Tamper2En1 = 0UL, u32Tamper2En2 = 0UL;
+
+    u32Reg1 = TAMPER->ACTSTIOCTL1;
+    u32Reg2 = TAMPER->ACTSTIOCTL2;
+
+    if((u32Reg1 & (uint32_t)TAMPER_ACTSTIOCTL1_ADYN1ISS_Msk) && (u32PairSel1 & (uint32_t)TAMPER_PAIR1_SELECT))
+    {
+        u32Tamper2En1 = u32Reg1 & TAMPER_ACTSTIOCTL1_ATAMP2EN_Msk;
+    }
+
+    if((u32Reg2 & (uint32_t)TAMPER_ACTSTIOCTL2_ADYN1ISS2_Msk) && (u32PairSel2 & (uint32_t)TAMPER_PAIR1_SELECT))
+    {
+        u32Tamper2En2 = u32Reg2 & TAMPER_ACTSTIOCTL2_ATAMP2EN2_Msk;
+    }
+
+    u32TmpReg1 = (TAMPER_ACTSTIOCTL1_ATAMP0EN_Msk | TAMPER_ACTSTIOCTL1_ATAMP1EN_Msk | TAMPER_ACTSTIOCTL1_ADYNPR0EN_Msk);
+    u32TmpReg2 = (TAMPER_ACTSTIOCTL2_ATAMP0EN2_Msk | TAMPER_ACTSTIOCTL2_ATAMP1EN2_Msk | TAMPER_ACTSTIOCTL2_ADYNPR0EN2_Msk);
+
+    for(i = 0UL; i < (uint32_t)TAMPER_MAX_PAIR_NUM; i++)
+    {
+        if(u32PairSel1 & (0x1UL << i))
+        {
+            u32Reg1 &= ~(u32TmpReg1 << ((i * 8UL)));
+        }
+
+        if(u32PairSel2 & (0x1UL << i))
+        {
+            u32Reg2 &= ~(u32TmpReg2 << ((i * 8UL)));
+        }
+    }
+
+    u32Reg1 |= u32Tamper2En1;
+    u32Reg2 |= u32Tamper2En2;
+
+    TAMPER->ACTSTIOCTL1 = u32Reg1;
+    TAMPER->ACTSTIOCTL2 = u32Reg2;
+}
+
+/**
+  * @brief      Config Active Shield Dynamic Tamper
+  *
+  * @param[in]  u32ChangeRate1/2    The dynamic tamper output change rate
+  *                                 - \ref TAMPER_ACTS_2POW10_CLK
+  *                                 - \ref TAMPER_ACTS_2POW11_CLK
+  *                                 - \ref TAMPER_ACTS_2POW12_CLK
+  *                                 - \ref TAMPER_ACTS_2POW13_CLK
+  *                                 - \ref TAMPER_ACTS_2POW14_CLK
+  *                                 - \ref TAMPER_ACTS_2POW15_CLK
+  *                                 - \ref TAMPER_ACTS_2POW16_CLK
+  *                                 - \ref TAMPER_ACTS_2POW17_CLK
+  *
+  * @param[in]  u32SeedReload1/2    Reload new seed or not
+  *                                 0: not reload new seed
+  *                                 1: reload new seed
+  *
+  * @param[in]  u32RefPattern1/2    Reference pattern
+  *                                 - \ref TAMPER_REF_RANDOM_PATTERN
+  *                                 - \ref TAMPER_REF_SEED
+  *
+  * @param[in]  u32Seed/2           Seed Value (0x0 ~ 0xFFFFFFFF)
+  *
+  * @return     None
+  *
+  * @details    This API is used to config active shield dynamic tamper setting.
+  */
+void TAMPER_ActiveShieldDynamicTamperConfig(uint32_t u32ChangeRate1, uint32_t u32SeedReload1, uint32_t u32RefPattern1, uint32_t u32Seed,
+        uint32_t u32ChangeRate2, uint32_t u32SeedReload2, uint32_t u32RefPattern2, uint32_t u32Seed2)
+{
+    uint32_t u32Reg1, u32Reg2;
+
+    u32Reg1 = TAMPER->ACTSTIOCTL1;
+    u32Reg2 = TAMPER->ACTSTIOCTL2;
+
+    u32Reg1 &= ~(TAMPER_ACTSTIOCTL1_ADYNSRC_Msk | TAMPER_ACTSTIOCTL1_ADYNRATE_Msk);
+    u32Reg2 &= ~(TAMPER_ACTSTIOCTL2_ADYNSRC2_Msk | TAMPER_ACTSTIOCTL2_SEEDRLD2_Msk | TAMPER_ACTSTIOCTL2_ADYNRATE2_Msk);
+
+    u32Reg1 |= (u32ChangeRate1) | ((u32RefPattern1 & 0x1UL) << TAMPER_ACTSTIOCTL1_ADYNSRC_Pos);
+    u32Reg2 |= (u32ChangeRate2) | ((u32SeedReload2 & 0x1UL) << TAMPER_ACTSTIOCTL2_SEEDRLD2_Pos) |
+               ((u32RefPattern2 & 0x1UL) << TAMPER_ACTSTIOCTL2_ADYNSRC2_Pos);
+
+    TAMPER->SEED = u32Seed; /* Need to set seed value before reloaded seed */
+    TAMPER->SEED2 = u32Seed2; /* Need to set seed value before reloaded seed */
+
+    TAMPER->ACTSTIOCTL1 = u32Reg1;
+    TAMPER->TIOCTL |= ((u32SeedReload1 & 0x1UL) << TAMPER_TIOCTL_SEEDRLD_Pos);
+    TAMPER->ACTSTIOCTL2 = u32Reg2;
+}
+
+/**@}*/ /* end of group TAMPER_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group TAMPER_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_timer.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_timer.c
new file mode 100644
index 0000000000..ba35aff78a
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_timer.c
@@ -0,0 +1,409 @@
+/**************************************************************************//**
+ * @file     timer.c
+ * @version  V3.00
+ * @brief    Timer Controller(Timer) driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup TIMER_Driver TIMER Driver
+  @{
+*/
+
+/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Open Timer with Operate Mode and Frequency
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  * @param[in]  u32Mode     Operation mode. Possible options are
+  *                         - \ref TIMER_ONESHOT_MODE
+  *                         - \ref TIMER_PERIODIC_MODE
+  *                         - \ref TIMER_TOGGLE_MODE
+  *                         - \ref TIMER_CONTINUOUS_MODE
+  * @param[in]  u32Freq     Target working frequency
+  *
+  * @return     Real timer working frequency
+  *
+  * @details    This API is used to configure timer to operate in specified mode and frequency.
+  *             If timer cannot work in target frequency, a closest frequency will be chose and returned.
+  * @note       After calling this API, Timer is \b NOT running yet. But could start timer running be calling
+  *             \ref TIMER_Start macro or program registers directly.
+  */
+uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq)
+{
+    uint32_t u32ClkFreq = TIMER_GetModuleClock(timer);
+    uint32_t u32Cmpr = 0UL, u32Prescale = 0UL;
+
+    /* Fastest possible timer working freq is (u32Clk / 2). While cmpr = 2, prescaler = 0. */
+    if(u32Freq > (u32ClkFreq / 2UL))
+    {
+        u32Cmpr = 2UL;
+    }
+    else
+    {
+        u32Cmpr = u32ClkFreq / u32Freq;
+        u32Prescale = (u32Cmpr >> 24);  /* for 24 bits CMPDAT */
+        if(u32Prescale > 0UL)
+            u32Cmpr = u32Cmpr / (u32Prescale + 1UL);
+    }
+
+    timer->CTL = u32Mode | u32Prescale;
+    timer->CMP = u32Cmpr;
+
+    return (u32ClkFreq / (u32Cmpr * (u32Prescale + 1UL)));
+}
+
+/**
+  * @brief      Stop Timer Counting
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This API stops timer counting and disable all timer interrupt function.
+  */
+void TIMER_Close(TIMER_T *timer)
+{
+    timer->CTL = 0UL;
+    timer->EXTCTL = 0UL;
+}
+
+/**
+  * @brief      Create a specify Delay Time
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  * @param[in]  u32Usec     Delay period in micro seconds. Valid values are between 100~1000000 (100 micro second ~ 1 second).
+  *
+  * @return     None
+  *
+  * @details    This API is used to create a delay loop for u32usec micro seconds by using timer one-shot mode.
+  * @note       This API overwrites the register setting of the timer used to count the delay time.
+  * @note       This API use polling mode. So there is no need to enable interrupt for the timer module used to generate delay.
+  */
+void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec)
+{
+    uint32_t u32ClkFreq = TIMER_GetModuleClock(timer);
+    uint32_t u32Prescale = 0UL, u32Delay = (SystemCoreClock / u32ClkFreq) + 1UL;
+    uint32_t u32Cmpr, u32NsecPerTick;
+
+    /* Clear current timer configuration */
+    timer->CTL = 0UL;
+    timer->EXTCTL = 0UL;
+
+    if(u32ClkFreq <= 1000000UL)   /* min delay is 1000 us if timer clock source is <= 1 MHz */
+    {
+        if(u32Usec < 1000UL)
+        {
+            u32Usec = 1000UL;
+        }
+        if(u32Usec > 1000000UL)
+        {
+            u32Usec = 1000000UL;
+        }
+    }
+    else
+    {
+        if(u32Usec < 100UL)
+        {
+            u32Usec = 100UL;
+        }
+        if(u32Usec > 1000000UL)
+        {
+            u32Usec = 1000000UL;
+        }
+    }
+
+    if(u32ClkFreq <= 1000000UL)
+    {
+        u32Prescale = 0UL;
+        u32NsecPerTick = 1000000000UL / u32ClkFreq;
+        u32Cmpr = (u32Usec * 1000UL) / u32NsecPerTick;
+    }
+    else
+    {
+        u32Cmpr = u32Usec * (u32ClkFreq / 1000000UL);
+        u32Prescale = (u32Cmpr >> 24);  /* for 24 bits CMPDAT */
+        if(u32Prescale > 0UL)
+            u32Cmpr = u32Cmpr / (u32Prescale + 1UL);
+    }
+
+    timer->CMP = u32Cmpr;
+    timer->CTL = TIMER_CTL_CNTEN_Msk | TIMER_ONESHOT_MODE | u32Prescale;
+
+    /*
+        When system clock is faster than timer clock, it is possible timer active bit cannot set in time while we check it.
+        And the while loop below return immediately, so put a tiny delay here allowing timer start counting and raise active flag.
+    */
+    for(; u32Delay > 0UL; u32Delay--)
+    {
+        __NOP();
+    }
+
+    while((timer->CTL & TIMER_CTL_ACTSTS_Msk) == TIMER_CTL_ACTSTS_Msk) {}
+}
+
+/**
+  * @brief      Enable Timer Capture Function
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  * @param[in]  u32CapMode  Timer capture mode. Could be
+  *                         - \ref TIMER_CAPTURE_FREE_COUNTING_MODE
+  *                         - \ref TIMER_CAPTURE_COUNTER_RESET_MODE
+  * @param[in]  u32Edge     Timer capture trigger edge. Possible values are
+  *                         - \ref TIMER_CAPTURE_EVENT_FALLING
+  *                         - \ref TIMER_CAPTURE_EVENT_RISING
+  *                         - \ref TIMER_CAPTURE_EVENT_FALLING_RISING
+  *                         - \ref TIMER_CAPTURE_EVENT_RISING_FALLING
+  *                         - \ref TIMER_CAPTURE_EVENT_GET_LOW_PERIOD
+  *                         - \ref TIMER_CAPTURE_EVENT_GET_HIGH_PERIOD
+  *
+  * @return     None
+  *
+  * @details    This API is used to enable timer capture function with specify capture trigger edge \n
+  *             to get current counter value or reset counter value to 0.
+  * @note       Timer frequency should be configured separately by using \ref TIMER_Open API, or program registers directly.
+  */
+void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge)
+{
+    timer->EXTCTL = (timer->EXTCTL & ~(TIMER_EXTCTL_CAPFUNCS_Msk | TIMER_EXTCTL_CAPEDGE_Msk)) |
+                    u32CapMode | u32Edge | TIMER_EXTCTL_CAPEN_Msk;
+}
+
+/**
+  * @brief      Disable Timer Capture Function
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This API is used to disable the timer capture function.
+  */
+void TIMER_DisableCapture(TIMER_T *timer)
+{
+    timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk;
+}
+
+/**
+  * @brief      Enable Timer Counter Function
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  * @param[in]  u32Edge     Detection edge of counter pin. Could be ether
+  *                         - \ref TIMER_COUNTER_EVENT_FALLING, or
+  *                         - \ref TIMER_COUNTER_EVENT_RISING
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable the timer counter function with specify detection edge.
+  * @note       Timer compare value should be configured separately by using \ref TIMER_SET_CMP_VALUE macro or program registers directly.
+  * @note       While using event counter function, \ref TIMER_TOGGLE_MODE cannot set as timer operation mode.
+  */
+void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge)
+{
+    timer->EXTCTL = (timer->EXTCTL & ~TIMER_EXTCTL_CNTPHASE_Msk) | u32Edge;
+    timer->CTL |= TIMER_CTL_EXTCNTEN_Msk;
+}
+
+/**
+  * @brief      Disable Timer Counter Function
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This API is used to disable the timer event counter function.
+  */
+void TIMER_DisableEventCounter(TIMER_T *timer)
+{
+    timer->CTL &= ~TIMER_CTL_EXTCNTEN_Msk;
+}
+
+/**
+  * @brief      Get Timer Clock Frequency
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     Timer clock frequency
+  *
+  * @details    This API is used to get the timer clock frequency.
+  * @note       This API cannot return correct clock rate if timer source is from external clock input.
+  */
+uint32_t TIMER_GetModuleClock(TIMER_T *timer)
+{
+    uint32_t u32Src, u32ClkFreq = __HIRC;
+    const uint32_t au32Clk[] = {__HXT, __LXT, 0UL, 0UL, __MIRC, __LIRC, 0UL, __HIRC};
+
+    if(timer == TIMER0)
+    {
+        u32Src = CLK_GetModuleClockSource(TMR0_MODULE);
+    }
+    else if(timer == TIMER1)
+    {
+        u32Src = CLK_GetModuleClockSource(TMR1_MODULE);
+    }
+    else if((timer == TIMER2) || (timer == TIMER2_NS))
+    {
+        u32Src = CLK_GetModuleClockSource(TMR2_MODULE);
+    }
+    else if((timer == TIMER3) || (timer == TIMER3_NS))
+    {
+        u32Src = CLK_GetModuleClockSource(TMR3_MODULE);
+    }
+    else if((timer == TIMER4) || (timer == TIMER4_NS))
+    {
+        u32Src = CLK_GetModuleClockSource(TMR4_MODULE);
+    }
+    else if((timer == TIMER5) || (timer == TIMER5_NS))
+    {
+        u32Src = CLK_GetModuleClockSource(TMR5_MODULE);
+    }
+    else
+    {
+        return 0UL;
+    }
+
+    if(u32Src == 2UL)
+    {
+        if((timer == TIMER0) || (timer == TIMER1) ||
+                (timer == TIMER4) || (timer == TIMER4_NS) || (timer == TIMER5) || (timer == TIMER5_NS))
+        {
+            u32ClkFreq = CLK_GetPCLK0Freq();
+        }
+        else
+        {
+            u32ClkFreq = CLK_GetPCLK1Freq();
+        }
+    }
+    else
+    {
+        u32ClkFreq = au32Clk[u32Src];
+    }
+
+    return u32ClkFreq;
+}
+
+/**
+  * @brief      Enable Timer Frequency Counter Function
+  *
+  * @param[in]  timer           The pointer of the specified Timer module. It could be TIMER0, TIMER2, TIMER4.
+  * @param[in]  u32DropCount    This parameter has no effect in this BSP
+  * @param[in]  u32Timeout      This parameter has no effect in this BSP
+  * @param[in]  u32EnableInt    Enable interrupt assertion after capture complete or not. Valid values are TRUE and FALSE
+  *
+  * @return     None
+  *
+  * @details    This function is used to calculate input event frequency. After enable
+  *             this function, a pair of timers, TIMER0 and TIMER1, TIMER2 and TIMER3, or TIMER4 and TIMER5
+  *             will be configured for this function. The mode used to calculate input
+  *             event frequency is mentioned as "Inter Timer Trigger Mode" in Technical
+  *             Reference Manual.
+  */
+void TIMER_EnableFreqCounter(TIMER_T *timer,
+                             uint32_t u32DropCount,
+                             uint32_t u32Timeout,
+                             uint32_t u32EnableInt)
+{
+    TIMER_T *t;    /* store the timer base to configure compare value */
+
+    (void)u32DropCount;
+    (void)u32Timeout;
+
+    if(timer == TIMER0)
+    {
+        t = TIMER1;
+    }
+    else if(timer == TIMER2)
+    {
+        t = TIMER3;
+    }
+    else if(timer == TIMER2_NS)
+    {
+        t = TIMER3_NS;
+    }
+    else if(timer == TIMER4)
+    {
+        t = TIMER5;
+    }
+    else if(timer == TIMER4_NS)
+    {
+        t = TIMER5_NS;
+    }
+    else
+    {
+        t = 0;
+    }
+
+    if(t != 0)
+    {
+        t->CMP = 0xFFFFFFUL;
+        t->EXTCTL = u32EnableInt ? TIMER_EXTCTL_CAPIEN_Msk : 0UL;
+        timer->CTL = TIMER_CTL_INTRGEN_Msk | TIMER_CTL_CNTEN_Msk;
+    }
+}
+
+/**
+  * @brief      Disable Timer Frequency Counter Function
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @brief      This function is used to disable the Timer frequency counter function.
+  */
+void TIMER_DisableFreqCounter(TIMER_T *timer)
+{
+    timer->CTL &= ~TIMER_CTL_INTRGEN_Msk;
+}
+
+/**
+  * @brief      Select Interrupt Source to Trigger others Module
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  * @param[in]  u32Src  Selects the interrupt source to trigger other modules. Could be:
+  *                     - \ref TIMER_TRGSRC_TIMEOUT_EVENT
+  *                     - \ref TIMER_TRGSRC_CAPTURE_EVENT
+  *
+  * @return     None
+  *
+  * @brief      This function is used to select the interrupt source used to trigger other modules.
+  */
+void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src)
+{
+    timer->TRGCTL = (timer->TRGCTL & ~TIMER_TRGCTL_TRGSSEL_Msk) | u32Src;
+}
+
+/**
+  * @brief      Set Modules Trigger by Timer Interrupt
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  * @param[in]  u32Mask The mask of modules (EPWM, EADC, DAC and PDMA) trigger by timer. It could the combination of
+  *                     - \ref TIMER_TRG_TO_PWM,
+  *                     - \ref TIMER_TRG_TO_EADC,
+  *                     - \ref TIMER_TRG_TO_DAC and
+  *                     - \ref TIMER_TRG_TO_PDMA
+  *
+  * @return     None
+  *
+  * @details    This function is used to set EPWM, EADC, DAC and PDMA module triggered by timer interrupt event.
+  * @note       The \ref TIMER_TRG_TO_PWM and \ref TIMER_TRG_TO_DAC are only available on TIMER0 ~ TIMER3.
+  */
+void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask)
+{
+    timer->TRGCTL = (timer->TRGCTL & ~(TIMER_TRGCTL_TRGPWM_Msk | TIMER_TRGCTL_TRGDAC_Msk | TIMER_TRGCTL_TRGEADC_Msk | TIMER_TRGCTL_TRGPDMA_Msk)) | u32Mask;
+}
+
+/**@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group TIMER_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_timer_pwm.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_timer_pwm.c
new file mode 100644
index 0000000000..c5b0ac475b
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_timer_pwm.c
@@ -0,0 +1,577 @@
+/**************************************************************************//**
+ * @file     timer.c
+ * @version  V3.00
+ * @brief    Timer PWM Controller(Timer PWM) driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup TIMER_PWM_Driver TIMER PWM Driver
+  @{
+*/
+
+/** @addtogroup TIMER_PWM_EXPORTED_FUNCTIONS TIMER PWM Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Set PWM Counter Clock Source
+  *
+  * @param[in]  timer           The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32CntClkSrc    PWM counter clock source, could be one of following source
+  *                                 - \ref TPWM_CNTR_CLKSRC_TMR_CLK
+  *                                 - \ref TPWM_CNTR_CLKSRC_TIMER0_INT
+  *                                 - \ref TPWM_CNTR_CLKSRC_TIMER1_INT
+  *                                 - \ref TPWM_CNTR_CLKSRC_TIMER2_INT
+  *                                 - \ref TPWM_CNTR_CLKSRC_TIMER3_INT
+  *
+  * @return     None
+  *
+  * @details    This function is used to set PWM counter clock source.
+  * @note       NOT available on TIMER4 and TIMER5.
+  */
+void TPWM_SetCounterClockSource(TIMER_T *timer, uint32_t u32CntClkSrc)
+{
+    (timer)->PWMCLKSRC = ((timer)->PWMCLKSRC & ~TIMER_PWMCLKSRC_CLKSRC_Msk) | u32CntClkSrc;
+}
+
+/** @cond HIDDEN_SYMBOLS */
+/**
+  * @brief      Get Timer PWM Clock Frequency
+  *
+  * @param[in]  timer   The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     Timer clock frequency
+  *
+  * @details    This API is used to get the timer pwm clock frequency.
+  * @note       This API cannot return correct clock rate if timer source is from external clock input.
+  */
+static uint32_t TPWM_GetModuleClockFreq(TIMER_T *timer)
+{
+    uint32_t u32Src, u32ClkFreq = __HIRC;
+    const uint32_t au32Clk[] = {__HXT, __LXT, 0UL, 0UL, __MIRC, __LIRC, 0UL, __HIRC};
+
+    if(timer == TIMER0)
+    {
+        u32Src = CLK_GetModuleClockSource(TMR0_MODULE);
+    }
+    else if(timer == TIMER1)
+    {
+        u32Src = CLK_GetModuleClockSource(TMR1_MODULE);
+    }
+    else if((timer == TIMER2) || (timer == TIMER2_NS))
+    {
+        u32Src = CLK_GetModuleClockSource(TMR2_MODULE);
+    }
+    else if((timer == TIMER3) || (timer == TIMER3_NS))
+    {
+        u32Src = CLK_GetModuleClockSource(TMR3_MODULE);
+    }
+    else if((timer == TIMER4) || (timer == TIMER4_NS))
+    {
+        u32Src = CLK_GetModuleClockSource(TMR4_MODULE);
+    }
+    else if((timer == TIMER5) || (timer == TIMER5_NS))
+    {
+        u32Src = CLK_GetModuleClockSource(TMR5_MODULE);
+    }
+    else
+    {
+        return 0UL;
+    }
+
+    if(u32Src == 2UL)
+    {
+        if((timer == TIMER0) || (timer == TIMER1) ||
+                (timer == TIMER4) || (timer == TIMER4_NS) || (timer == TIMER5) || (timer == TIMER5_NS))
+        {
+            u32ClkFreq = CLK_GetPCLK0Freq();
+        }
+        else
+        {
+            u32ClkFreq = CLK_GetPCLK1Freq();
+        }
+    }
+    else
+    {
+        u32ClkFreq = au32Clk[u32Src];
+    }
+
+    return u32ClkFreq;
+}
+/** @endcond HIDDEN_SYMBOLS */
+
+/**
+  * @brief      Configure PWM Output Frequency and Duty Cycle
+  *
+  * @param[in]  timer           The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  * @param[in]  u32Frequency    Target generator frequency.
+  * @param[in]  u32DutyCycle    Target generator duty cycle percentage. Valid range are between 0~100. 10 means 10%, 20 means 20%...
+  *
+  * @return     Nearest frequency clock in nano second
+  *
+  * @details    This API is used to configure PWM output frequency and duty cycle in up count type and auto-reload operation mode.
+  * @note       This API is only available if Timer PWM counter clock source is from TMRx_CLK.
+  */
+uint32_t TPWM_ConfigOutputFreqAndDuty(TIMER_T *timer, uint32_t u32Frequency, uint32_t u32DutyCycle)
+{
+    uint32_t u32PWMClockFreq, u32TargetFreq;
+    uint32_t u32Prescaler = 0x1000UL, u32Period = 1UL, u32CMP, u32MaxCLKPSC = 0x1000UL;
+
+    if((timer == TIMER0) || (timer == TIMER1))
+    {
+        u32PWMClockFreq = CLK_GetPCLK0Freq();
+    }
+    else if((timer == TIMER4) || (timer == TIMER4_NS) || (timer == TIMER5) || (timer == TIMER5_NS))
+    {
+        u32PWMClockFreq = TPWM_GetModuleClockFreq(timer);
+    }
+    else
+    {
+        u32PWMClockFreq = CLK_GetPCLK1Freq();
+    }
+
+    if((timer == TIMER4) || (timer == TIMER4_NS) || (timer == TIMER5) || (timer == TIMER5_NS))
+        u32MaxCLKPSC = 0x100UL; // 8-bit clock prescale on TIMER4 and TIMER5 PWM
+    else
+        u32MaxCLKPSC = 0x1000UL; // 12-bit clock prescale on TIMER0 ~ TIMER3 PWM
+
+    /* Calculate u16PERIOD and u16PSC */
+    for(u32Prescaler = 1UL; u32Prescaler <= u32MaxCLKPSC; u32Prescaler++)
+    {
+        u32Period = (u32PWMClockFreq / u32Prescaler) / u32Frequency;
+
+        /* If target u32Period is larger than 0x10000, need to use a larger prescaler */
+        if(u32Period <= 0x10000UL)
+        {
+            break;
+        }
+    }
+    /* Store return value here 'cos we're gonna change u32Prescaler & u32Period to the real value to fill into register */
+    u32TargetFreq = (u32PWMClockFreq / u32Prescaler) / u32Period;
+
+    /* Set PWM to up count type */
+    timer->PWMCTL = (timer->PWMCTL & ~TIMER_PWMCTL_CNTTYPE_Msk) | (TPWM_UP_COUNT << TIMER_PWMCTL_CNTTYPE_Pos);
+
+    /* Set PWM to auto-reload mode */
+    timer->PWMCTL = (timer->PWMCTL & ~TIMER_PWMCTL_CNTMODE_Msk) | (TPWM_AUTO_RELOAD_MODE << TIMER_PWMCTL_CNTMODE_Pos);
+
+    /* Convert to real register value */
+    TPWM_SET_PERIOD(timer, (u32Period - 1UL));
+    if(u32DutyCycle)
+    {
+        u32CMP = (u32DutyCycle * u32Period) / 100UL;
+    }
+    else
+    {
+        u32CMP = 0UL;
+    }
+
+    TPWM_SET_CMPDAT(timer, u32CMP);
+
+    TPWM_SET_PRESCALER(timer, (u32Prescaler - 1UL));
+
+    return (u32TargetFreq);
+}
+
+/**
+  * @brief      Enable Dead-Time Function
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32DTCount  Dead-Time duration in PWM clock count, valid values are between 0x0~0xFFF, but 0x0 means there is no Dead-Time insertion.
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable Dead-Time function and counter source is the same as Timer PWM clock source.
+  * @note       The register write-protection function should be disabled before using this function.
+  * @note       NOT available on TIMER4 and TIMER5.
+  */
+void TPWM_EnableDeadTime(TIMER_T *timer, uint32_t u32DTCount)
+{
+    timer->PWMDTCTL = TIMER_PWMDTCTL_DTEN_Msk | u32DTCount;
+}
+
+/**
+  * @brief      Enable Dead-Time Function
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32DTCount  Dead-Time duration in PWM clock count, valid values are between 0x0~0xFFF, but 0x0 means there is no Dead-Time insertion.
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable Dead-Time function and counter source is the Timer PWM clock source with prescale.
+  * @note       The register write-protection function should be disabled before using this function.
+  * @note       NOT available on TIMER4 and TIMER5.
+  */
+void TPWM_EnableDeadTimeWithPrescale(TIMER_T *timer, uint32_t u32DTCount)
+{
+    timer->PWMDTCTL = TIMER_PWMDTCTL_DTCKSEL_Msk | TIMER_PWMDTCTL_DTEN_Msk | u32DTCount;
+}
+
+/**
+  * @brief      Disable Dead-Time Function
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to disable Dead-time of selected channel.
+  * @note       The register write-protection function should be disabled before using this function.
+  * @note       NOT available on TIMER4 and TIMER5.
+  */
+void TPWM_DisableDeadTime(TIMER_T *timer)
+{
+    timer->PWMDTCTL = 0x0UL;
+}
+
+/**
+  * @brief      Enable PWM Counter
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable PWM generator and start counter counting.
+  */
+void TPWM_EnableCounter(TIMER_T *timer)
+{
+    timer->PWMCTL |= TIMER_PWMCTL_CNTEN_Msk;
+}
+
+/**
+  * @brief      Disable PWM Generator
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details This function is used to disable PWM counter immediately by clear CNTEN (TIMERx_PWMCTL[0]) bit.
+  */
+void TPWM_DisableCounter(TIMER_T *timer)
+{
+    timer->PWMCTL &= ~TIMER_PWMCTL_CNTEN_Msk;
+}
+
+/**
+  * @brief      Enable Trigger ADC
+  *
+  * @param[in]  timer           The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  * @param[in]  u32Condition    The condition to trigger ADC. It could be one of following conditions:
+  *                                 - \ref TPWM_TRIGGER_EVENT_AT_ZERO_POINT
+  *                                 - \ref TPWM_TRIGGER_EVENT_AT_PERIOD_POINT
+  *                                 - \ref TPWM_TRIGGER_EVENT_AT_ZERO_OR_PERIOD_POINT
+  *                                 - \ref TPWM_TRIGGER_EVENT_AT_COMPARE_UP_POINT
+  *                                 - \ref TPWM_TRIGGER_EVENT_AT_COMPARE_DOWN_POINT
+  *                                 - \ref TPWM_TRIGGER_EVENT_AT_PERIOD_OR_COMPARE_UP_POINT
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable specified counter compare event to trigger ADC.
+  * @note       TIMER4 and TIMER5 only supports \ref TPWM_TRIGGER_EVENT_AT_PERIOD_POINT, \ref TPWM_TRIGGER_EVENT_AT_COMPARE_UP_POINT,
+  *             and \ref TPWM_TRIGGER_EVENT_AT_PERIOD_OR_COMPARE_UP_POINT.
+  */
+void TPWM_EnableTriggerADC(TIMER_T *timer, uint32_t u32Condition)
+{
+    timer->PWMTRGCTL = ((timer->PWMTRGCTL & ~TIMER_PWMTRGCTL_TRGSEL_Msk) | (u32Condition)) | TIMER_PWMTRGCTL_TRGEADC_Msk;
+}
+
+/**
+  * @brief      Disable Trigger ADC
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This function is used to disable counter compare event to trigger ADC.
+  */
+void TPWM_DisableTriggerADC(TIMER_T *timer)
+{
+    timer->PWMTRGCTL &= ~TIMER_PWMTRGCTL_TRGEADC_Msk;
+}
+
+/**
+  * @brief      Enable Trigger PDMA
+  *
+  * @param[in]  timer           The pointer of the specified Timer module. It could be TIMER4 or TIMER5.
+  * @param[in]  u32Condition    The condition to trigger PDMA. It could be one of following conditions:
+  *                                 - \ref TPWM_TRIGGER_EVENT_AT_PERIOD_POINT
+  *                                 - \ref TPWM_TRIGGER_EVENT_AT_COMPARE_UP_POINT
+  *                                 - \ref TPWM_TRIGGER_EVENT_AT_PERIOD_OR_COMPARE_UP_POINT
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable specified counter compare event to trigger PDMA.
+  * @note       Only available on TIMER4 and TIMER5.
+  */
+void TPWM_EnableTriggerPDMA(TIMER_T *timer, uint32_t u32Condition)
+{
+    timer->PWMTRGCTL = ((timer->PWMTRGCTL & ~TIMER_PWMTRGCTL_TRGSEL_Msk) | (u32Condition)) | TIMER_PWMTRGCTL_TRGPDMA_Msk;
+}
+
+/**
+  * @brief      Disable Trigger PDMA
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER4 or TIMER5.
+  *
+  * @return     None
+  *
+  * @details    This function is used to disable counter compare event to trigger ADC.
+  * @note       Only available on TIMER4 and TIMER5.
+  */
+void TPWM_DisableTriggerPDMA(TIMER_T *timer)
+{
+    timer->PWMTRGCTL &= ~TIMER_PWMTRGCTL_TRGPDMA_Msk;
+}
+
+/**
+  * @brief      Enable Fault Brake Function
+  *
+  * @param[in]  timer           The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32CH0Level     PWMx_CH0 output level while fault brake event occurs. Valid value is one of following setting
+  *                                 - \ref TPWM_OUTPUT_TOGGLE
+  *                                 - \ref TPWM_OUTPUT_NOTHING
+  *                                 - \ref TPWM_OUTPUT_LOW
+  *                                 - \ref TPWM_OUTPUT_HIGH
+  * @param[in]  u32CH1Level     PWMx_CH1 output level while fault brake event occurs. Valid value is one of following setting
+  *                                 - \ref TPWM_OUTPUT_TOGGLE
+  *                                 - \ref TPWM_OUTPUT_NOTHING
+  *                                 - \ref TPWM_OUTPUT_LOW
+  *                                 - \ref TPWM_OUTPUT_HIGH
+  * @param[in]  u32BrakeSource  Fault brake source, combination of following source
+  *                                 - \ref TPWM_BRAKE_SOURCE_EDGE_ACMP0
+  *                                 - \ref TPWM_BRAKE_SOURCE_EDGE_ACMP1
+  *                                 - \ref TPWM_BRAKE_SOURCE_EDGE_BKPIN
+  *                                 - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_CSS
+  *                                 - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_BOD
+  *                                 - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_COR
+  *                                 - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_RAM
+  *                                 - \ref TPWM_BRAKE_SOURCE_LEVEL_ACMP0
+  *                                 - \ref TPWM_BRAKE_SOURCE_LEVEL_ACMP1
+  *                                 - \ref TPWM_BRAKE_SOURCE_LEVEL_BKPIN
+  *                                 - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_CSS
+  *                                 - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_BOD
+  *                                 - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_COR
+  *                                 - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_RAM
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable fault brake function.
+  * @note       The register write-protection function should be disabled before using this function.
+  * @note       NOT available on TIMER4 and TIMER5.
+  */
+void TPWM_EnableFaultBrake(TIMER_T *timer, uint32_t u32CH0Level, uint32_t u32CH1Level, uint32_t u32BrakeSource)
+{
+    timer->PWMFAILBRK |= ((u32BrakeSource >> 16) & 0xFUL);
+    timer->PWMBRKCTL = (timer->PWMBRKCTL & ~(TIMER_PWMBRKCTL_BRKAEVEN_Msk | TIMER_PWMBRKCTL_BRKAODD_Msk)) |
+                       (u32BrakeSource & 0xFFFFUL) | (u32CH0Level << TIMER_PWMBRKCTL_BRKAEVEN_Pos) | (u32CH1Level << TIMER_PWMBRKCTL_BRKAODD_Pos);
+}
+
+/**
+  * @brief      Enable Fault Brake Interrupt
+  *
+  * @param[in]  timer           The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32IntSource    Interrupt source, could be one of following source
+  *                                 - \ref TPWM_BRAKE_EDGE
+  *                                 - \ref TPWM_BRAKE_LEVEL
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable fault brake interrupt.
+  * @note       The register write-protection function should be disabled before using this function.
+  * @note       NOT available on TIMER4 and TIMER5.
+  */
+void TPWM_EnableFaultBrakeInt(TIMER_T *timer, uint32_t u32IntSource)
+{
+    timer->PWMINTEN1 |= u32IntSource;
+}
+
+/**
+  * @brief      Disable Fault Brake Interrupt
+  *
+  * @param[in]  timer           The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32IntSource    Interrupt source, could be one of following source
+  *                                 - \ref TPWM_BRAKE_EDGE
+  *                                 - \ref TPWM_BRAKE_LEVEL
+  *
+  * @return     None
+  *
+  * @details    This function is used to disable fault brake interrupt.
+  * @note       The register write-protection function should be disabled before using this function.
+  * @note       NOT available on TIMER4 and TIMER5.
+  */
+void TPWM_DisableFaultBrakeInt(TIMER_T *timer, uint32_t u32IntSource)
+{
+    timer->PWMINTEN1 &= ~u32IntSource;
+}
+
+/**
+  * @brief      Indicate Fault Brake Interrupt Flag
+  *
+  * @param[in]  timer           The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32IntSource    Interrupt source, could be one of following source
+  *                                 - \ref TPWM_BRAKE_EDGE
+  *                                 - \ref TPWM_BRAKE_LEVEL
+  *
+  * @return     Fault brake interrupt flag of specified source
+  * @retval     0       Fault brake interrupt did not occurred
+  * @retval     1       Fault brake interrupt occurred
+  *
+  * @details    This function is used to indicate fault brake interrupt flag occurred or not of selected source.
+  * @note       NOT available on TIMER4 and TIMER5.
+  */
+uint32_t TPWM_GetFaultBrakeIntFlag(TIMER_T *timer, uint32_t u32IntSource)
+{
+    return ((timer->PWMINTSTS1 & (0x3UL << u32IntSource)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief      Clear Fault Brake Interrupt Flags
+  *
+  * @param[in]  timer           The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32IntSource    Interrupt source, could be one of following source
+  *                                 - \ref TPWM_BRAKE_EDGE
+  *                                 - \ref TPWM_BRAKE_LEVEL
+  *
+  * @return     None
+  *
+  * @details    This function is used to clear fault brake interrupt flags of selected source.
+  * @note       The register write-protection function should be disabled before using this function.
+  * @note       NOT available on TIMER4 and TIMER5.
+  */
+void TPWM_ClearFaultBrakeIntFlag(TIMER_T *timer, uint32_t u32IntSource)
+{
+    timer->PWMINTSTS1 = (0x3UL << u32IntSource);
+}
+
+/**
+  * @brief      Enable Load Mode
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32LoadMode  Timer PWM counter loading mode, could be one of following mode
+  *                             - \ref TPWM_LOAD_MODE_PERIOD
+  *                             - \ref TPWM_LOAD_MODE_IMMEDIATE
+  *                             - \ref TPWM_LOAD_MODE_CENTER
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable load mode of selected channel.
+  * @note       The default loading mode is period loading mode.
+  * @note       NOT available on TIMER4 and TIMER5.
+  */
+void TPWM_SetLoadMode(TIMER_T *timer, uint32_t u32LoadMode)
+{
+    timer->PWMCTL = (timer->PWMCTL & ~(TIMER_PWMCTL_IMMLDEN_Msk | TIMER_PWMCTL_CTRLD_Msk)) | u32LoadMode;
+}
+
+/**
+  * @brief      Enable Brake Pin Noise Filter Function
+  *
+  * @param[in]  timer           The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32BrakePinSrc  The external brake pin source, could be one of following source
+  *                                 - \ref TPWM_TM_BRAKE0
+  *                                 - \ref TPWM_TM_BRAKE1
+  *                                 - \ref TPWM_TM_BRAKE2
+  *                                 - \ref TPWM_TM_BRAKE3
+  * @param[in]  u32DebounceCnt  This value controls the real debounce sample time.
+  *                             The target debounce sample time is (debounce sample clock period) * (u32DebounceCnt).
+  * @param[in]  u32ClkSrcSel    Brake pin detector debounce clock source, could be one of following source
+  *                                 - \ref TPWM_BKP_DBCLK_PCLK_DIV_1
+  *                                 - \ref TPWM_BKP_DBCLK_PCLK_DIV_2
+  *                                 - \ref TPWM_BKP_DBCLK_PCLK_DIV_4
+  *                                 - \ref TPWM_BKP_DBCLK_PCLK_DIV_8
+  *                                 - \ref TPWM_BKP_DBCLK_PCLK_DIV_16
+  *                                 - \ref TPWM_BKP_DBCLK_PCLK_DIV_32
+  *                                 - \ref TPWM_BKP_DBCLK_PCLK_DIV_64
+  *                                 - \ref TPWM_BKP_DBCLK_PCLK_DIV_128
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable external brake pin detector noise filter function.
+  * @note       NOT available on TIMER4 and TIMER5.
+  */
+void TPWM_EnableBrakePinDebounce(TIMER_T *timer, uint32_t u32BrakePinSrc, uint32_t u32DebounceCnt, uint32_t u32ClkSrcSel)
+{
+    timer->PWMBNF = (timer->PWMBNF & ~(TIMER_PWMBNF_BKPINSRC_Msk | TIMER_PWMBNF_BRKFCNT_Msk | TIMER_PWMBNF_BRKNFSEL_Msk)) |
+                    (u32BrakePinSrc << TIMER_PWMBNF_BKPINSRC_Pos) |
+                    (u32DebounceCnt << TIMER_PWMBNF_BRKFCNT_Pos) |
+                    (u32ClkSrcSel << TIMER_PWMBNF_BRKNFSEL_Pos) | TIMER_PWMBNF_BRKNFEN_Msk;
+}
+
+/**
+  * @brief      Disable Brake Pin Noise Filter Function
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to disable external brake pin detector noise filter function.
+  * @note       NOT available on TIMER4 and TIMER5.
+  */
+void TPWM_DisableBrakePinDebounce(TIMER_T *timer)
+{
+    timer->PWMBNF &= ~TIMER_PWMBNF_BRKNFEN_Msk;
+}
+
+/**
+  * @brief      Enable Brake Pin Inverse Function
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to enable PWM brake pin inverse function.
+  * @note       NOT available on TIMER4 and TIMER5.
+  */
+void TPWM_EnableBrakePinInverse(TIMER_T *timer)
+{
+    timer->PWMBNF |= TIMER_PWMBNF_BRKPINV_Msk;
+}
+
+/**
+  * @brief      Disable Brake Pin Inverse Function
+  *
+  * @param[in]  timer       The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  *
+  * @return     None
+  *
+  * @details    This function is used to disable PWM brake pin inverse function.
+  * @note       NOT available on TIMER4 and TIMER5.
+  */
+void TPWM_DisableBrakePinInverse(TIMER_T *timer)
+{
+    timer->PWMBNF &= ~TIMER_PWMBNF_BRKPINV_Msk;
+}
+
+/**
+  * @brief      Set Brake Pin Source
+  *
+  * @param[in]  timer           The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
+  * @param[in]  u32BrakePinNum  Brake pin selection. One of the following:
+  *                                 - \ref TPWM_TM_BRAKE0
+  *                                 - \ref TPWM_TM_BRAKE1
+  *                                 - \ref TPWM_TM_BRAKE2
+  *                                 - \ref TPWM_TM_BRAKE3
+  *
+  * @return     None
+  *
+  * @details    This function is used to set PWM brake pin source.
+  * @note       NOT available on TIMER4 and TIMER5.
+  */
+void TPWM_SetBrakePinSource(TIMER_T *timer, uint32_t u32BrakePinNum)
+{
+    timer->PWMBNF = (((timer)->PWMBNF & ~TIMER_PWMBNF_BKPINSRC_Msk) | (u32BrakePinNum << TIMER_PWMBNF_BKPINSRC_Pos));
+}
+
+
+/**@}*/ /* end of group TIMER_PWM_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group TIMER_PWM_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_uart.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_uart.c
new file mode 100644
index 0000000000..20832506f2
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_uart.c
@@ -0,0 +1,687 @@
+/**************************************************************************//**
+ * @file     uart.c
+ * @version  V3.00
+ * @brief    M2354 series UART Interface Controller (UART) driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+#include 
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup UART_Driver UART Driver
+  @{
+*/
+
+
+/** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions
+  @{
+*/
+
+/**
+ *    @brief        Clear UART specified interrupt flag
+ *
+ *    @param[in]    uart                The pointer of the specified UART module.
+ *    @param[in]    u32InterruptFlag    The specified interrupt of UART module.
+ *                                      - \ref UART_INTSTS_SWBEINT_Msk   : Single-wire Bit Error Detect Interrupt
+ *                                      - \ref UART_INTSTS_LININT_Msk    : LIN Bus interrupt
+ *                                      - \ref UART_INTSTS_WKINT_Msk     : Wake-up interrupt
+ *                                      - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error interrupt
+ *                                      - \ref UART_INTSTS_MODEMINT_Msk  : MODEM Status Interrupt
+ *                                      - \ref UART_INTSTS_RLSINT_Msk    : Receive Line Status interrupt
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to clear UART specified interrupt flag.
+ */
+void UART_ClearIntFlag(UART_T* uart, uint32_t u32InterruptFlag)
+{
+    if(u32InterruptFlag & UART_INTSTS_SWBEINT_Msk)      /* Clear Bit Error Detection Interrupt */
+    {
+        uart->FIFOSTS = UART_INTSTS_SWBEIF_Msk;
+    }
+
+    if(u32InterruptFlag & UART_INTSTS_RLSINT_Msk)       /* Clear Receive Line Status Interrupt */
+    {
+        uart->FIFOSTS = UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_ADDRDETF_Msk;
+    }
+
+    if(u32InterruptFlag & UART_INTSTS_MODEMINT_Msk)     /* Clear MODEM Status Interrupt */
+    {
+        uart->MODEMSTS |= UART_MODEMSTS_CTSDETF_Msk;
+    }
+
+    if(u32InterruptFlag & UART_INTSTS_BUFERRINT_Msk)    /* Clear Buffer Error Interrupt */
+    {
+        uart->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk | UART_FIFOSTS_TXOVIF_Msk;
+    }
+
+    if(u32InterruptFlag & UART_INTSTS_WKINT_Msk)        /* Clear Wake-up Interrupt */
+    {
+        uart->WKSTS = UART_WKSTS_CTSWKF_Msk  | UART_WKSTS_DATWKF_Msk   |
+                      UART_WKSTS_RFRTWKF_Msk | UART_WKSTS_RS485WKF_Msk |
+                      UART_WKSTS_TOUTWKF_Msk;
+    }
+
+    if(u32InterruptFlag & UART_INTSTS_LININT_Msk)       /* Clear LIN Bus Interrupt */
+    {
+        uart->INTSTS = UART_INTSTS_LINIF_Msk;
+        uart->LINSTS = UART_LINSTS_BITEF_Msk    | UART_LINSTS_BRKDETF_Msk  |
+                       UART_LINSTS_SLVSYNCF_Msk | UART_LINSTS_SLVIDPEF_Msk |
+                       UART_LINSTS_SLVHEF_Msk   | UART_LINSTS_SLVHDETF_Msk ;
+    }
+
+}
+
+
+/**
+ *  @brief      Disable UART interrupt
+ *
+ *  @param[in]  uart The pointer of the specified UART module.
+ *
+ *  @return     None
+ *
+ *  @details    The function is used to disable UART interrupt.
+ */
+void UART_Close(UART_T* uart)
+{
+    uart->INTEN = 0ul;
+}
+
+
+/**
+ *  @brief      Disable UART auto flow control function
+ *
+ *  @param[in]  uart The pointer of the specified UART module.
+ *
+ *  @return     None
+ *
+ *  @details    The function is used to disable UART auto flow control.
+ */
+void UART_DisableFlowCtrl(UART_T* uart)
+{
+    uart->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk);
+}
+
+
+/**
+ *    @brief        Disable UART specified interrupt
+ *
+ *    @param[in]    uart                The pointer of the specified UART module.
+ *    @param[in]    u32InterruptFlag    The specified interrupt of UART module.
+ *                                      - \ref UART_INTEN_TXENDIEN_Msk   : Transmitter Empty Interrupt
+ *                                      - \ref UART_INTEN_SWBEIEN_Msk    : Single-wire Bit Error Detect Interrupt
+ *                                      - \ref UART_INTEN_ABRIEN_Msk     : Auto-baud Rate Interrupt
+ *                                      - \ref UART_INTEN_LINIEN_Msk     : Lin Bus interrupt
+ *                                      - \ref UART_INTEN_WKIEN_Msk      : Wake-up interrupt
+ *                                      - \ref UART_INTEN_BUFERRIEN_Msk  : Buffer Error interrupt
+ *                                      - \ref UART_INTEN_RXTOIEN_Msk    : Rx Time-out Interrupt
+ *                                      - \ref UART_INTEN_MODEMIEN_Msk   : MODEM Status Interrupt
+ *                                      - \ref UART_INTEN_RLSIEN_Msk     : Receive Line Status Interrupt
+ *                                      - \ref UART_INTEN_THREIEN_Msk    : Transmit Holding Register Empty Interrupt
+ *                                      - \ref UART_INTEN_RDAIEN_Msk     : Receive Data Available Interrupt
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to disable UART specified interrupt and disable NVIC UART IRQ.
+ */
+void UART_DisableInt(UART_T*  uart, uint32_t u32InterruptFlag)
+{
+    /* Disable UART specified interrupt */
+    UART_DISABLE_INT(uart, u32InterruptFlag);
+}
+
+
+/**
+ *    @brief        Enable UART auto flow control function
+ *
+ *    @param[in]    uart    The pointer of the specified UART module.
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to Enable UART auto flow control.
+ */
+/**
+ *    @brief        Enable UART auto flow control function
+ *
+ *    @param[in]    uart    The pointer of the specified UART module.
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to Enable UART auto flow control.
+ */
+void UART_EnableFlowCtrl(UART_T* uart)
+{
+    /* Set RTS pin output is low level active */
+    uart->MODEM |= UART_MODEM_RTSACTLV_Msk;
+
+    /* Set CTS pin input is low level active */
+    uart->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk;
+
+    /* Set RTS and CTS auto flow control enable */
+    uart->INTEN |= UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk;
+}
+
+
+/**
+ *    @brief        Enable UART specified interrupt
+ *
+ *    @param[in]    uart                The pointer of the specified UART module.
+ *    @param[in]    u32InterruptFlag    The specified interrupt of UART module:
+ *                                      - \ref UART_INTEN_TXENDIEN_Msk   : Transmitter Empty Interrupt
+ *                                      - \ref UART_INTEN_ABRIEN_Msk     : Auto-baud Rate Interrupt
+ *                                      - \ref UART_INTEN_LINIEN_Msk     : Lin Bus interrupt
+ *                                      - \ref UART_INTEN_WKIEN_Msk      : Wake-up interrupt
+ *                                      - \ref UART_INTEN_BUFERRIEN_Msk  : Buffer Error interrupt
+ *                                      - \ref UART_INTEN_RXTOIEN_Msk    : Rx Time-out Interrupt
+ *                                      - \ref UART_INTEN_MODEMIEN_Msk   : MODEM Status Interrupt
+ *                                      - \ref UART_INTEN_RLSIEN_Msk     : Receive Line Status Interrupt
+ *                                      - \ref UART_INTEN_THREIEN_Msk    : Transmit Holding Register Empty Interrupt
+ *                                      - \ref UART_INTEN_RDAIEN_Msk     : Receive Data Available Interrupt
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to enable UART specified interrupt and enable NVIC UART IRQ.
+ */
+void UART_EnableInt(UART_T*  uart, uint32_t u32InterruptFlag)
+{
+
+    /* Enable UART specified interrupt */
+    UART_ENABLE_INT(uart, u32InterruptFlag);
+}
+
+
+/**
+ *    @brief        Open and set UART function
+ *
+ *    @param[in]    uart            The pointer of the specified UART module.
+ *    @param[in]    u32baudrate     The baudrate of UART module.
+ *
+ *    @return       None
+ *
+ *    @details      This function use to enable UART function and set baud-rate.
+ */
+void UART_Open(UART_T* uart, uint32_t u32baudrate)
+{
+    uint32_t u32UartClkSrcSel, u32UartClkDivNum;
+    uint32_t au32ClkTbl[8] = { __HXT, 0ul, __LXT, __HIRC, 0ul, 0ul, 0ul, 0ul};
+    uint32_t u32BaudDiv = 0ul;
+
+    /* Get UART clock source selection and UART clock divider number */
+    switch((uint32_t)uart)
+    {
+        case UART0_BASE:
+        case UART0_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART0_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART0_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK0Freq();
+            break;
+        case UART1_BASE:
+        case UART1_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART1_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART1_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK1Freq();
+            break;
+        case UART2_BASE:
+        case UART2_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART2_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART2_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK0Freq();
+            break;
+        case UART3_BASE:
+        case UART3_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART3_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART3_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK1Freq();
+            break;
+        case UART4_BASE:
+        case UART4_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART4_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART4_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK0Freq();
+            break;
+        case UART5_BASE:
+        case UART5_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART5_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART5_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK1Freq();
+            break;
+        default:
+            return;
+    }
+
+    /* Select UART function */
+    uart->FUNCSEL = UART_FUNCSEL_UART;
+
+    /* Set UART line configuration */
+    uart->LINE = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1;
+
+    /* Set UART Rx and RTS trigger level */
+    uart->FIFO &= ~(UART_FIFO_RFITL_Msk | UART_FIFO_RTSTRGLV_Msk);
+
+    /* Get PLL clock frequency if UART clock source selection is PLL */
+    if(u32UartClkSrcSel == 1ul)
+    {
+        au32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq();
+    }
+
+    /* Set UART baud rate */
+    if(u32baudrate != 0ul)
+    {
+        u32BaudDiv = UART_BAUD_MODE2_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate);
+
+        if(u32BaudDiv > 0xFFFFul)
+        {
+            uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate));
+        }
+        else
+        {
+            uart->BAUD = (UART_BAUD_MODE2 | u32BaudDiv);
+        }
+    }
+}
+
+
+/**
+ *    @brief        Read UART data
+ *
+ *    @param[in]    uart            The pointer of the specified UART module.
+ *    @param[in]    pu8RxBuf        The buffer to receive the data of receive FIFO.
+ *    @param[in]    u32ReadBytes    The the read bytes number of data.
+ *
+ *    @return       u32Count Receive byte count
+ *
+ *    @details      The function is used to read Rx data from RX FIFO and the data will be stored in pu8RxBuf.
+ */
+uint32_t UART_Read(UART_T* uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes)
+{
+    uint32_t  u32Count, u32delayno;
+    uint32_t  u32Exit = 0ul;
+
+    for(u32Count = 0ul; u32Count < u32ReadBytes; u32Count++)
+    {
+        u32delayno = 0ul;
+
+        while(uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk)   /* Check RX empty => failed */
+        {
+            u32delayno++;
+            if(u32delayno >= 0x40000000ul)
+            {
+                u32Exit = 1ul;
+                break;
+            }
+            else
+            {
+            }
+        }
+
+        if(u32Exit == 1ul)
+        {
+            break;
+        }
+        else
+        {
+            pu8RxBuf[u32Count] = (uint8_t)uart->DAT; /* Get Data from UART RX  */
+        }
+    }
+
+    return u32Count;
+}
+
+
+/**
+ *    @brief        Set UART line configuration
+ *
+ *    @param[in]    uart            The pointer of the specified UART module.
+ *    @param[in]    u32baudrate     The register value of baudrate of UART module.
+ *                                  If u32baudrate = 0, UART baudrate will not change.
+ *    @param[in]    u32data_width   The data length of UART module.
+ *                                  - \ref UART_WORD_LEN_5
+ *                                  - \ref UART_WORD_LEN_6
+ *                                  - \ref UART_WORD_LEN_7
+ *                                  - \ref UART_WORD_LEN_8
+ *    @param[in]    u32parity       The parity setting (none/odd/even/mark/space) of UART module.
+ *                                  - \ref UART_PARITY_NONE
+ *                                  - \ref UART_PARITY_ODD
+ *                                  - \ref UART_PARITY_EVEN
+ *                                  - \ref UART_PARITY_MARK
+ *                                  - \ref UART_PARITY_SPACE
+ *    @param[in]    u32stop_bits    The stop bit length (1/1.5/2 bit) of UART module.
+ *                                  - \ref UART_STOP_BIT_1
+ *                                  - \ref UART_STOP_BIT_1_5
+ *                                  - \ref UART_STOP_BIT_2
+ *
+ *    @return       None
+ *
+ *    @details      This function use to config UART line setting.
+ */
+void UART_SetLineConfig(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t  u32stop_bits)
+{
+    uint32_t u32UartClkSrcSel, u32UartClkDivNum;
+    uint32_t au32ClkTbl[8] = { __HXT, 0ul, __LXT, __HIRC, 0ul, 0ul, 0ul, 0ul};
+    uint32_t u32BaudDiv = 0ul;
+
+    /* Get UART clock source selection and UART clock divider number */
+    switch((uint32_t)uart)
+    {
+        case UART0_BASE:
+        case UART0_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART0_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART0_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK0Freq();
+            break;
+        case UART1_BASE:
+        case UART1_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART1_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART1_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK1Freq();
+            break;
+        case UART2_BASE:
+        case UART2_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART2_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART2_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK0Freq();
+            break;
+        case UART3_BASE:
+        case UART3_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART3_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART3_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK1Freq();
+            break;
+        case UART4_BASE:
+        case UART4_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART4_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART4_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK0Freq();
+            break;
+        case UART5_BASE:
+        case UART5_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART5_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART5_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK1Freq();
+            break;
+        default:
+            return;
+    }
+
+    /* Get PLL clock frequency if UART clock source selection is PLL */
+    if(u32UartClkSrcSel == 1ul)
+    {
+        au32ClkTbl[1] = CLK_GetPLLClockFreq();
+    }
+
+    /* Set UART baud rate */
+    if(u32baudrate != 0ul)
+    {
+        u32BaudDiv = UART_BAUD_MODE2_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate);
+
+        if(u32BaudDiv > 0xFFFFul)
+        {
+            uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate));
+        }
+        else
+        {
+            uart->BAUD = (UART_BAUD_MODE2 | u32BaudDiv);
+        }
+    }
+
+    /* Set UART line configuration */
+    uart->LINE = u32data_width | u32parity | u32stop_bits;
+}
+
+
+/**
+ *    @brief        Set Rx timeout count
+ *
+ *    @param[in]    uart    The pointer of the specified UART module.
+ *    @param[in]    u32TOC  Rx timeout counter.
+ *
+ *    @return       None
+ *
+ *    @details      This function use to set Rx timeout count.
+ */
+void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC)
+{
+    /* Set time-out interrupt comparator */
+    uart->TOUT = (uart->TOUT & ~UART_TOUT_TOIC_Msk) | (u32TOC);
+
+    /* Set time-out counter enable */
+    uart->INTEN |= UART_INTEN_TOCNTEN_Msk;
+}
+
+
+/**
+ *    @brief        Select and configure IrDA function
+ *
+ *    @param[in]    uart            The pointer of the specified UART module.
+ *    @param[in]    u32Buadrate     The baudrate of UART module.
+ *    @param[in]    u32Direction    The direction of UART module in IrDA mode:
+ *                                  - \ref UART_IRDA_TXEN
+ *                                  - \ref UART_IRDA_RXEN
+ *
+ *    @return       None
+  *
+ *    @details      The function is used to configure IrDA relative settings. It consists of TX or RX mode and baudrate.
+ */
+void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction)
+{
+    uint32_t u32UartClkSrcSel = 0UL, u32UartClkDivNum = 1UL;
+    uint32_t au32ClkTbl[8] = { __HXT, 0ul, __LXT, __HIRC, 0ul, 0ul, 0ul, 0ul};
+    uint32_t u32BaudDiv;
+
+    /* Select IrDA function mode */
+    uart->FUNCSEL = UART_FUNCSEL_IrDA;
+
+    /* Get UART clock source selection and UART clock divider number */
+    switch((uint32_t)uart)
+    {
+        case UART0_BASE:
+        case UART0_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART0_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART0_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK0Freq();
+            break;
+        case UART1_BASE:
+        case UART1_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART1_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART1_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK1Freq();
+            break;
+        case UART2_BASE:
+        case UART2_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART2_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART2_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK0Freq();
+            break;
+        case UART3_BASE:
+        case UART3_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART3_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART3_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK1Freq();
+            break;
+        case UART4_BASE:
+        case UART4_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART4_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART4_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK0Freq();
+            break;
+        case UART5_BASE:
+        case UART5_BASE+NS_OFFSET:
+            u32UartClkSrcSel = CLK_GetModuleClockSource(UART5_MODULE);
+            u32UartClkDivNum = CLK_GetModuleClockDivider(UART5_MODULE);
+            if(u32UartClkSrcSel == 4ul)
+                au32ClkTbl[4] = CLK_GetPCLK1Freq();
+            break;
+        default:
+            return;
+    }
+
+    /* Get PLL clock frequency if UART clock source selection is PLL */
+    if(u32UartClkSrcSel == 1ul)
+    {
+        au32ClkTbl[1] = CLK_GetPLLClockFreq();
+    }
+
+    /* Set UART IrDA baud rate in mode 0 */
+    if(u32Buadrate != 0ul)
+    {
+        u32BaudDiv = UART_BAUD_MODE0_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32Buadrate);
+
+        if(u32BaudDiv < 0xFFFFul)
+        {
+            uart->BAUD = (UART_BAUD_MODE0 | u32BaudDiv);
+        }
+    }
+
+    /* Configure IrDA relative settings */
+    if(u32Direction == UART_IRDA_RXEN)
+    {
+        uart->IRDA |= UART_IRDA_RXINV_Msk;     /* Rx signal is inverse */
+        uart->IRDA &= ~UART_IRDA_TXEN_Msk;
+    }
+    else
+    {
+        uart->IRDA &= ~UART_IRDA_TXINV_Msk;    /* Tx signal is not inverse */
+        uart->IRDA |= UART_IRDA_TXEN_Msk;
+    }
+
+}
+
+
+/**
+ *    @brief        Select and configure RS485 function
+ *
+ *    @param[in]    uart        The pointer of the specified UART module.
+ *    @param[in]    u32Mode     The operation mode(NMM/AUD/AAD).
+ *                              - \ref UART_ALTCTL_RS485NMM_Msk
+ *                              - \ref UART_ALTCTL_RS485AUD_Msk
+ *                              - \ref UART_ALTCTL_RS485AAD_Msk
+ *    @param[in]    u32Addr     The RS485 address.
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to set RS485 relative setting.
+ */
+void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr)
+{
+    /* Select UART RS485 function mode */
+    uart->FUNCSEL = UART_FUNCSEL_RS485;
+
+    /* Set RS585 configuration */
+    uart->ALTCTL &= ~(UART_ALTCTL_RS485NMM_Msk | UART_ALTCTL_RS485AUD_Msk | UART_ALTCTL_RS485AAD_Msk | UART_ALTCTL_ADDRMV_Msk);
+    uart->ALTCTL |= (u32Mode | (u32Addr << UART_ALTCTL_ADDRMV_Pos));
+}
+
+
+/**
+ *    @brief        Select and configure LIN function
+ *
+ *    @param[in]    uart            The pointer of the specified UART module.
+ *    @param[in]    u32Mode         The LIN direction :
+ *                                  - \ref UART_ALTCTL_LINTXEN_Msk
+ *                                  - \ref UART_ALTCTL_LINRXEN_Msk
+ *    @param[in]    u32BreakLength  The breakfield length.
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to set LIN relative setting.
+ */
+void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength)
+{
+    /* Select LIN function mode */
+    uart->FUNCSEL = UART_FUNCSEL_LIN;
+
+    /* Select LIN function setting : Tx enable, Rx enable and break field length */
+    uart->ALTCTL &= ~(UART_ALTCTL_LINTXEN_Msk | UART_ALTCTL_LINRXEN_Msk | UART_ALTCTL_BRKFL_Msk);
+    uart->ALTCTL |= (u32Mode | (u32BreakLength << UART_ALTCTL_BRKFL_Pos));
+}
+
+
+/**
+ *    @brief        Write UART data
+ *
+ *    @param[in]    uart            The pointer of the specified UART module.
+ *    @param[in]    pu8TxBuf        The buffer to send the data to UART transmission FIFO.
+ *    @param[out]   u32WriteBytes   The byte number of data.
+ *
+ *    @return       u32Count transfer byte count
+ *
+ *    @details      The function is to write data into TX buffer to transmit data by UART.
+ */
+uint32_t UART_Write(UART_T* uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes)
+{
+    uint32_t  u32Count, u32delayno;
+    uint32_t  u32Exit = 0ul;
+
+    for(u32Count = 0ul; u32Count != u32WriteBytes; u32Count++)
+    {
+        u32delayno = 0ul;
+        while(UART_IS_TX_FULL(uart))     /* Wait Tx not full and Time-out manner */
+        {
+            u32delayno++;
+            if(u32delayno >= 0x40000000ul)
+            {
+                u32Exit = 1ul;
+                break;
+            }
+            else
+            {
+            }
+        }
+
+        if(u32Exit == 1ul)
+        {
+            break;
+        }
+        else
+        {
+            uart->DAT = pu8TxBuf[u32Count];    /* Send UART Data from buffer */
+        }
+    }
+
+    return u32Count;
+}
+
+/**
+ *    @brief        Select Single Wire mode function
+ *
+ *    @param[in]    uart        The pointer of the specified UART module.
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to select Single Wire mode.
+ */
+void UART_SelectSingleWireMode(UART_T *uart)
+{
+    /* Select UART SingleWire function mode */
+    uart->FUNCSEL = ((uart->FUNCSEL & (~UART_FUNCSEL_FUNCSEL_Msk)) | UART_FUNCSEL_SINGLE_WIRE);
+}
+
+
+/**@}*/ /* end of group UART_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group UART_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_usbd.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_usbd.c
new file mode 100644
index 0000000000..e0e098a9ed
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_usbd.c
@@ -0,0 +1,778 @@
+/**************************************************************************//**
+ * @file     usbd.c
+ * @version  V3.00
+ * @brief    M2354 series USBD driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+#include 
+#include "NuMicro.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup USBD_Driver USBD Driver
+  @{
+*/
+
+
+/** @addtogroup USBD_EXPORTED_FUNCTIONS USBD Exported Functions
+  @{
+*/
+
+/* Global variables for Control Pipe */
+uint8_t g_USBD_au8SetupPacket[8] = {0UL};       /*!< Setup packet buffer */
+volatile uint8_t g_USBD_u8RemoteWakeupEn = 0UL; /*!< Remote wake up function enable flag */
+
+/**
+ * @cond HIDDEN_SYMBOLS
+ */
+static uint8_t *s_USBD_pu8CtrlInPointer = 0;
+static uint8_t *s_USBD_pu8CtrlOutPointer = 0;
+static volatile uint32_t s_USBD_u32CtrlInSize = 0UL;
+static volatile uint32_t s_USBD_u32CtrlOutSize = 0UL;
+static volatile uint32_t s_USBD_u32CtrlOutSizeLimit = 0UL;
+static volatile uint32_t s_USBD_u32UsbAddr = 0UL;
+static volatile uint32_t s_USBD_u32UsbConfig = 0UL;
+static volatile uint32_t s_USBD_u32CtrlMaxPktSize = 8UL;
+static volatile uint32_t s_USBD_u32UsbAltInterface = 0UL;
+static volatile uint8_t  s_USBD_u8CtrlInZeroFlag = 0UL;
+/**
+ * @endcond
+ */
+
+const S_USBD_INFO_T *g_USBD_sInfo;                  /*!< A pointer for USB information structure */
+
+VENDOR_REQ g_USBD_pfnVendorRequest       = NULL;    /*!< USB Vendor Request Functional Pointer */
+CLASS_REQ g_USBD_pfnClassRequest         = NULL;    /*!< USB Class Request Functional Pointer */
+SET_INTERFACE_REQ g_USBD_pfnSetInterface = NULL;    /*!< USB Set Interface Functional Pointer */
+SET_CONFIG_CB g_USBD_pfnSetConfigCallback = NULL;   /*!< USB Set configuration callback function pointer */
+uint32_t g_USBD_u32EpStallLock           = 0UL;     /*!< Bit map flag to lock specified EP when SET_FEATURE */
+
+/**
+  * @brief      This function makes USBD module to be ready to use
+  *
+  * @param[in]  param           The structure of USBD information.
+  * @param[in]  pfnClassReq     USB Class request callback function.
+  * @param[in]  pfnSetInterface USB Set Interface request callback function.
+  *
+  * @return     None
+  *
+  * @details    This function will enable USB controller, USB PHY transceiver and pull-up resistor of USB_D+ pin. USB PHY will drive SE0 to bus.
+  */
+void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface)
+{
+    USBD_T *pUSBD;
+
+    if((__PC() & NS_OFFSET) == NS_OFFSET)
+    {
+        pUSBD = USBD_NS;
+    }
+    else
+    {
+        pUSBD = USBD;
+    }
+
+    g_USBD_sInfo = param;
+    g_USBD_pfnClassRequest = pfnClassReq;
+    g_USBD_pfnSetInterface = pfnSetInterface;
+
+    /* get EP0 maximum packet size */
+    s_USBD_u32CtrlMaxPktSize = g_USBD_sInfo->gu8DevDesc[7];
+
+    /* Initial USB engine */
+#ifdef SUPPORT_LPM
+    pUSBD->ATTR = 0x7D0UL | USBD_LPMACK;
+#else
+    pUSBD->ATTR = 0x7D0UL;
+#endif
+    /* Force SE0 */
+    USBD_SET_SE0();
+}
+
+/**
+  * @brief    This function makes USB host to recognize the device
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  Enable WAKEUP, FLDET, USB and BUS interrupts. Disable software-disconnect function after 100ms delay with SysTick timer.
+  */
+void USBD_Start(void)
+{
+    /* Disable software-disconnect function */
+    USBD_CLR_SE0();
+
+    /* Clear USB-related interrupts before enable interrupt */
+    USBD_CLR_INT_FLAG(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP);
+
+    /* Enable USB-related interrupts. */
+    USBD_ENABLE_INT(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP);
+}
+
+/**
+  * @brief      Get the received SETUP packet
+  *
+  * @param[in]  buf A buffer pointer used to store 8-byte SETUP packet.
+  *
+  * @return     None
+  *
+  * @details    Store SETUP packet to a user-specified buffer.
+  *
+  */
+void USBD_GetSetupPacket(uint8_t *buf)
+{
+    USBD_MemCopy(buf, g_USBD_au8SetupPacket, 8UL);
+}
+
+/**
+  * @brief    Process SETUP packet
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  Parse SETUP packet and perform the corresponding action.
+  *
+  */
+void USBD_ProcessSetupPacket(void)
+{
+    /* Get SETUP packet from USB buffer */
+    USBD_MemCopy(g_USBD_au8SetupPacket, (uint8_t *)USBD_BUF_BASE, 8UL);
+
+    /* Check the request type */
+    switch(g_USBD_au8SetupPacket[0] & 0x60UL)
+    {
+        case REQ_STANDARD:   /* Standard */
+        {
+            USBD_StandardRequest();
+            break;
+        }
+        case REQ_CLASS:   /* Class */
+        {
+            if(g_USBD_pfnClassRequest != NULL)
+            {
+                g_USBD_pfnClassRequest();
+            }
+            break;
+        }
+        case REQ_VENDOR:   /* Vendor */
+        {
+            if(g_USBD_pfnVendorRequest != NULL)
+            {
+                g_USBD_pfnVendorRequest();
+            }
+            break;
+        }
+        default:   /* reserved */
+        {
+            /* Setup error, stall the device */
+            USBD_SET_EP_STALL(EP0);
+            USBD_SET_EP_STALL(EP1);
+            break;
+        }
+    }
+}
+
+/**
+  * @brief    Process GetDescriptor request
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  Parse GetDescriptor request and perform the corresponding action.
+  *
+  */
+void USBD_GetDescriptor(void)
+{
+    uint32_t u32Len;
+
+    s_USBD_u8CtrlInZeroFlag = (uint8_t)0UL;
+    u32Len = 0UL;
+    u32Len = g_USBD_au8SetupPacket[7];
+    u32Len <<= 8UL;
+    u32Len += g_USBD_au8SetupPacket[6];
+
+    switch(g_USBD_au8SetupPacket[3])
+    {
+        /* Get Device Descriptor */
+        case DESC_DEVICE:
+        {
+            u32Len = USBD_Minimum(u32Len, (uint32_t)LEN_DEVICE);
+            USBD_PrepareCtrlIn((uint8_t *)g_USBD_sInfo->gu8DevDesc, u32Len);
+            break;
+        }
+        /* Get Configuration Descriptor */
+        case DESC_CONFIG:
+        {
+            uint32_t u32TotalLen;
+
+            u32TotalLen = g_USBD_sInfo->gu8ConfigDesc[3];
+            u32TotalLen = g_USBD_sInfo->gu8ConfigDesc[2] + (u32TotalLen << 8UL);
+
+            if(u32Len > u32TotalLen)
+            {
+                u32Len = u32TotalLen;
+                if((u32Len % s_USBD_u32CtrlMaxPktSize) == 0UL)
+                {
+                    s_USBD_u8CtrlInZeroFlag = (uint8_t)1UL;
+                }
+            }
+            USBD_PrepareCtrlIn((uint8_t *)g_USBD_sInfo->gu8ConfigDesc, u32Len);
+            break;
+        }
+        /* Get BOS Descriptor */
+        case DESC_BOS:
+        {
+            if(g_USBD_sInfo->gu8BosDesc == 0)
+            {
+                USBD_SET_EP_STALL(EP0);
+                USBD_SET_EP_STALL(EP1);
+            }
+            else
+            {
+                u32Len = USBD_Minimum(u32Len, LEN_BOS + LEN_BOSCAP);
+                USBD_PrepareCtrlIn((uint8_t *)g_USBD_sInfo->gu8BosDesc, u32Len);
+            }
+            break;
+        }
+        /* Get HID Descriptor */
+        case DESC_HID:
+        {
+            /* CV3.0 HID Class Descriptor Test,
+               Need to indicate index of the HID Descriptor within gu8ConfigDescriptor, specifically HID Composite device. */
+            uint32_t u32ConfigDescOffset;   /* u32ConfigDescOffset is configuration descriptor offset (HID descriptor start index) */
+            u32Len = USBD_Minimum(u32Len, LEN_HID);
+            u32ConfigDescOffset = g_USBD_sInfo->gu32ConfigHidDescIdx[g_USBD_au8SetupPacket[4]];
+            USBD_PrepareCtrlIn((uint8_t *)&g_USBD_sInfo->gu8ConfigDesc[u32ConfigDescOffset], u32Len);
+            break;
+        }
+        /* Get Report Descriptor */
+        case DESC_HID_RPT:
+        {
+            if(u32Len > g_USBD_sInfo->gu32HidReportSize[g_USBD_au8SetupPacket[4]])
+            {
+                u32Len = g_USBD_sInfo->gu32HidReportSize[g_USBD_au8SetupPacket[4]];
+                if((u32Len % s_USBD_u32CtrlMaxPktSize) == 0UL)
+                {
+                    s_USBD_u8CtrlInZeroFlag = (uint8_t)1UL;
+                }
+            }
+            USBD_PrepareCtrlIn((uint8_t *)g_USBD_sInfo->gu8HidReportDesc[g_USBD_au8SetupPacket[4]], u32Len);
+            break;
+        }
+        /* Get String Descriptor */
+        case DESC_STRING:
+        {
+            /* Get String Descriptor */
+            if(g_USBD_au8SetupPacket[2] < 4UL)
+            {
+                if(u32Len > g_USBD_sInfo->gu8StringDesc[g_USBD_au8SetupPacket[2]][0])
+                {
+                    u32Len = g_USBD_sInfo->gu8StringDesc[g_USBD_au8SetupPacket[2]][0];
+                    if((u32Len % s_USBD_u32CtrlMaxPktSize) == 0UL)
+                    {
+                        s_USBD_u8CtrlInZeroFlag = (uint8_t)1UL;
+                    }
+                }
+                USBD_PrepareCtrlIn((uint8_t *)g_USBD_sInfo->gu8StringDesc[g_USBD_au8SetupPacket[2]], u32Len);
+                break;
+            }
+            else
+            {
+                /* Not support. Reply STALL. */
+                USBD_SET_EP_STALL(EP0);
+                USBD_SET_EP_STALL(EP1);
+                break;
+            }
+        }
+        default:
+            /* Not support. Reply STALL. */
+            USBD_SET_EP_STALL(EP0);
+            USBD_SET_EP_STALL(EP1);
+            break;
+    }
+}
+
+/**
+  * @brief    Process standard request
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  Parse standard request and perform the corresponding action.
+  *
+  */
+void USBD_StandardRequest(void)
+{
+    uint32_t u32Addr;
+    USBD_T *pUSBD;
+    OTG_T *pOTG;
+
+    if((__PC() & NS_OFFSET) == NS_OFFSET)
+    {
+        pUSBD = USBD_NS;
+        pOTG = OTG_NS;
+    }
+    else
+    {
+        pUSBD = USBD;
+        pOTG = OTG;
+    }
+
+    /* clear global variables for new request */
+    s_USBD_pu8CtrlInPointer = 0;
+    s_USBD_u32CtrlInSize = 0UL;
+
+    if((g_USBD_au8SetupPacket[0] & 0x80UL) == 0x80UL)    /* request data transfer direction */
+    {
+        /* Device to host */
+        switch(g_USBD_au8SetupPacket[1])
+        {
+            case GET_CONFIGURATION:
+            {
+                /* Return current configuration setting */
+                /* Data stage */
+                u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
+                M8(u32Addr) = (uint8_t)s_USBD_u32UsbConfig;
+                USBD_SET_DATA1(EP0);
+                USBD_SET_PAYLOAD_LEN(EP0, 1UL);
+                /* Status stage */
+                USBD_PrepareCtrlOut(0, 0UL);
+                break;
+            }
+            case GET_DESCRIPTOR:
+            {
+                USBD_GetDescriptor();
+                USBD_PrepareCtrlOut(0, 0UL); /* For status stage */
+                break;
+            }
+            case GET_INTERFACE:
+            {
+                /* Return current interface setting */
+                /* Data stage */
+                u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
+                M8(u32Addr) = (uint8_t)s_USBD_u32UsbAltInterface;
+                USBD_SET_DATA1(EP0);
+                USBD_SET_PAYLOAD_LEN(EP0, 1UL);
+                /* Status stage */
+                USBD_PrepareCtrlOut(0, 0UL);
+                break;
+            }
+            case GET_STATUS:
+            {
+                /* Device */
+                if(g_USBD_au8SetupPacket[0] == 0x80UL)
+                {
+                    uint8_t u8Tmp;
+
+                    u8Tmp = (uint8_t)0UL;
+                    if((g_USBD_sInfo->gu8ConfigDesc[7] & 0x40UL) == 0x40UL)
+                    {
+                        u8Tmp |= (uint8_t)1UL; /* Self-Powered/Bus-Powered. */
+                    }
+                    if((g_USBD_sInfo->gu8ConfigDesc[7] & 0x20UL) == 0x20UL)
+                    {
+                        u8Tmp |= (uint8_t)(g_USBD_u8RemoteWakeupEn << 1UL); /* Remote wake up */
+                    }
+
+                    u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
+                    M8(u32Addr) = u8Tmp;
+
+                }
+                /* Interface */
+                else if(g_USBD_au8SetupPacket[0] == 0x81UL)
+                {
+                    u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
+                    M8(u32Addr) = (uint8_t)0UL;
+                }
+                /* Endpoint */
+                else if(g_USBD_au8SetupPacket[0] == 0x82UL)
+                {
+                    uint8_t ep = (uint8_t)(g_USBD_au8SetupPacket[4] & 0xFUL);
+                    u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
+                    M8(u32Addr) = (uint8_t)(USBD_GetStall(ep) ? 1UL : 0UL);
+                }
+
+                u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0) + 1UL;
+                M8(u32Addr) = (uint8_t)0UL;
+                /* Data stage */
+                USBD_SET_DATA1(EP0);
+                USBD_SET_PAYLOAD_LEN(EP0, 2UL);
+                /* Status stage */
+                USBD_PrepareCtrlOut(0, 0UL);
+                break;
+            }
+            default:
+            {
+                /* Setup error, stall the device */
+                USBD_SET_EP_STALL(EP0);
+                USBD_SET_EP_STALL(EP1);
+                break;
+            }
+        }
+    }
+    else
+    {
+        /* Host to device */
+        switch(g_USBD_au8SetupPacket[1])
+        {
+            case CLEAR_FEATURE:
+            {
+                if(g_USBD_au8SetupPacket[2] == FEATURE_ENDPOINT_HALT)
+                {
+                    uint32_t epNum, i;
+
+                    /* EP number stall is not allow to be clear in MSC class "Error Recovery Test".
+                       a flag: g_USBD_u32EpStallLock is added to support it */
+                    epNum = (uint8_t)(g_USBD_au8SetupPacket[4] & 0xFUL);
+                    for(i = 0UL; i < USBD_MAX_EP; i++)
+                    {
+                        if(((pUSBD->EP[i].CFG & 0xFUL) == epNum) && ((g_USBD_u32EpStallLock & (1UL << i)) == 0UL))
+                        {
+                            pUSBD->EP[i].CFGP &= ~USBD_CFGP_SSTALL_Msk;
+                            pUSBD->EP[i].CFG &= ~USBD_CFG_DSQSYNC_Msk;
+                        }
+                    }
+                }
+                else if(g_USBD_au8SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP)
+                {
+                    g_USBD_u8RemoteWakeupEn = (uint8_t)0UL;
+                }
+
+                /* Status stage */
+                USBD_SET_DATA1(EP0);
+                USBD_SET_PAYLOAD_LEN(EP0, 0UL);
+                break;
+            }
+            case SET_ADDRESS:
+            {
+                s_USBD_u32UsbAddr = g_USBD_au8SetupPacket[2];
+
+                /* DATA IN for end of setup */
+                /* Status Stage */
+                USBD_SET_DATA1(EP0);
+                USBD_SET_PAYLOAD_LEN(EP0, 0UL);
+                break;
+            }
+            case SET_CONFIGURATION:
+            {
+                s_USBD_u32UsbConfig = g_USBD_au8SetupPacket[2];
+
+                if(g_USBD_pfnSetConfigCallback)
+                {
+                    g_USBD_pfnSetConfigCallback();
+                }
+
+                /* DATA IN for end of setup */
+                /* Status stage */
+                USBD_SET_DATA1(EP0);
+                USBD_SET_PAYLOAD_LEN(EP0, 0UL);
+                break;
+            }
+            case SET_FEATURE:
+            {
+                if((g_USBD_au8SetupPacket[0] & 0xFUL) == 0UL)   /* 0: device */
+                {
+                    if((g_USBD_au8SetupPacket[2] == 3UL) && (g_USBD_au8SetupPacket[3] == 0UL)) /* 3: HNP enable */
+                    {
+                        pOTG->CTL |= (OTG_CTL_HNPREQEN_Msk | OTG_CTL_BUSREQ_Msk);
+                    }
+                }
+                if(g_USBD_au8SetupPacket[2] == FEATURE_ENDPOINT_HALT)
+                {
+                    USBD_SetStall((uint8_t)(g_USBD_au8SetupPacket[4] & 0xFUL));
+                }
+                else if(g_USBD_au8SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP)
+                {
+                    g_USBD_u8RemoteWakeupEn = (uint8_t)1UL;
+                }
+
+                /* Status stage */
+                USBD_SET_DATA1(EP0);
+                USBD_SET_PAYLOAD_LEN(EP0, 0UL);
+                break;
+            }
+            case SET_INTERFACE:
+            {
+                s_USBD_u32UsbAltInterface = g_USBD_au8SetupPacket[2];
+                if(g_USBD_pfnSetInterface != NULL)
+                {
+                    g_USBD_pfnSetInterface(s_USBD_u32UsbAltInterface);
+                }
+
+                /* Status stage */
+                USBD_SET_DATA1(EP0);
+                USBD_SET_PAYLOAD_LEN(EP0, 0UL);
+                break;
+            }
+            default:
+            {
+                /* Setup error, stall the device */
+                USBD_SET_EP_STALL(EP0);
+                USBD_SET_EP_STALL(EP1);
+                break;
+            }
+        }
+    }
+}
+
+/**
+  * @brief      Prepare the first Control IN pipe
+  *
+  * @param[in]  pu8Buf  The pointer of data sent to USB host.
+  * @param[in]  u32Size The IN transfer size.
+  *
+  * @return     None
+  *
+  * @details    Prepare data for Control IN transfer.
+  *
+  */
+void USBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size)
+{
+    uint32_t u32Addr;
+
+    if(u32Size > s_USBD_u32CtrlMaxPktSize)
+    {
+        /* Data size > MXPLD */
+        s_USBD_pu8CtrlInPointer = pu8Buf + s_USBD_u32CtrlMaxPktSize;
+        s_USBD_u32CtrlInSize = u32Size - s_USBD_u32CtrlMaxPktSize;
+        USBD_SET_DATA1(EP0);
+        u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
+        USBD_MemCopy((uint8_t *)u32Addr, pu8Buf, s_USBD_u32CtrlMaxPktSize);
+        USBD_SET_PAYLOAD_LEN(EP0, s_USBD_u32CtrlMaxPktSize);
+    }
+    else
+    {
+        /* Data size <= MXPLD */
+        s_USBD_pu8CtrlInPointer = 0;
+        s_USBD_u32CtrlInSize = 0UL;
+        USBD_SET_DATA1(EP0);
+        u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
+        USBD_MemCopy((uint8_t *)u32Addr, pu8Buf, u32Size);
+        USBD_SET_PAYLOAD_LEN(EP0, u32Size);
+    }
+}
+
+/**
+  * @brief    Repeat Control IN pipe
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  This function processes the remained data of Control IN transfer.
+  *
+  */
+void USBD_CtrlIn(void)
+{
+    uint32_t u32Addr;
+
+    if(s_USBD_u32CtrlInSize)
+    {
+        /* Process remained data */
+        if(s_USBD_u32CtrlInSize > s_USBD_u32CtrlMaxPktSize)
+        {
+            /* Data size > MXPLD */
+            u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
+            USBD_MemCopy((uint8_t *)u32Addr, (uint8_t *)s_USBD_pu8CtrlInPointer, s_USBD_u32CtrlMaxPktSize);
+            USBD_SET_PAYLOAD_LEN(EP0, s_USBD_u32CtrlMaxPktSize);
+            s_USBD_pu8CtrlInPointer += s_USBD_u32CtrlMaxPktSize;
+            s_USBD_u32CtrlInSize -= s_USBD_u32CtrlMaxPktSize;
+        }
+        else
+        {
+            /* Data size <= MXPLD */
+            u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0);
+            USBD_MemCopy((uint8_t *)u32Addr, (uint8_t *)s_USBD_pu8CtrlInPointer, s_USBD_u32CtrlInSize);
+            USBD_SET_PAYLOAD_LEN(EP0, s_USBD_u32CtrlInSize);
+            s_USBD_pu8CtrlInPointer = 0;
+            s_USBD_u32CtrlInSize = 0UL;
+        }
+    }
+    else /* No more data for IN token */
+    {
+        /* In ACK for Set address */
+        if((g_USBD_au8SetupPacket[0] == REQ_STANDARD) && (g_USBD_au8SetupPacket[1] == SET_ADDRESS))
+        {
+            u32Addr = USBD_GET_ADDR();
+            if((u32Addr != s_USBD_u32UsbAddr) && (u32Addr == 0UL))
+            {
+                USBD_SET_ADDR(s_USBD_u32UsbAddr);
+            }
+        }
+
+        /* For the case of data size is integral times maximum packet size */
+        if(s_USBD_u8CtrlInZeroFlag)
+        {
+            USBD_SET_PAYLOAD_LEN(EP0, 0UL);
+            s_USBD_u8CtrlInZeroFlag = (uint8_t)0UL;
+        }
+    }
+}
+
+/**
+  * @brief      Prepare the first Control OUT pipe
+  *
+  * @param[in]  pu8Buf  The pointer of data received from USB host.
+  * @param[in]  u32Size The OUT transfer size.
+  *
+  * @return     None
+  *
+  * @details    This function is used to prepare the first Control OUT transfer.
+  *
+  */
+void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size)
+{
+    s_USBD_pu8CtrlOutPointer = pu8Buf;
+    s_USBD_u32CtrlOutSize = 0UL;
+    s_USBD_u32CtrlOutSizeLimit = u32Size;
+    USBD_SET_PAYLOAD_LEN(EP1, s_USBD_u32CtrlMaxPktSize);
+}
+
+/**
+  * @brief    Repeat Control OUT pipe
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  This function processes the successive Control OUT transfer.
+  *
+  */
+void USBD_CtrlOut(void)
+{
+    uint32_t u32Size;
+    uint32_t u32Addr;
+
+    if(s_USBD_u32CtrlOutSize < s_USBD_u32CtrlOutSizeLimit)
+    {
+        u32Size = USBD_GET_PAYLOAD_LEN(EP1);
+        u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP1);
+        USBD_MemCopy((uint8_t *)s_USBD_pu8CtrlOutPointer, (uint8_t *)u32Addr, u32Size);
+        s_USBD_pu8CtrlOutPointer += u32Size;
+        s_USBD_u32CtrlOutSize += u32Size;
+
+        if(s_USBD_u32CtrlOutSize < s_USBD_u32CtrlOutSizeLimit)
+        {
+            USBD_SET_PAYLOAD_LEN(EP1, s_USBD_u32CtrlMaxPktSize);
+        }
+    }
+}
+
+/**
+  * @brief    Reset software flags
+  *
+  * @param    None
+  *
+  * @return   None
+  *
+  * @details  This function resets all variables for protocol and resets USB device address to 0.
+  *
+  */
+void USBD_SwReset(void)
+{
+    uint32_t i, u32CFG;
+    USBD_T *pUSBD;
+
+    if((__PC() & NS_OFFSET) == NS_OFFSET)
+    {
+        pUSBD = USBD_NS;
+    }
+    else
+    {
+        pUSBD = USBD;
+    }
+
+    /* Reset all variables for protocol */
+    s_USBD_pu8CtrlInPointer = 0;
+    s_USBD_u32CtrlInSize = 0UL;
+    s_USBD_pu8CtrlOutPointer = 0;
+    s_USBD_u32CtrlOutSize = 0UL;
+    s_USBD_u32CtrlOutSizeLimit = 0UL;
+    g_USBD_u32EpStallLock = 0UL;
+    memset(g_USBD_au8SetupPacket, 0, 8UL);
+
+    for(i = 0UL; i < USBD_MAX_EP; i++)
+    {
+        if(!USBD_IS_DB_MODE(i))
+        {
+            /* Reset PID DATA0 */
+            pUSBD->EP[i].CFG &= ~USBD_CFG_DSQSYNC_Msk;
+        }
+        else
+        {
+            /* Reset double buffer setting */
+            u32CFG = pUSBD->EP[i].CFG;
+            pUSBD->EP[i].CFG = u32CFG;
+        }
+    }
+
+    /* Reset USB device address */
+    USBD_SET_ADDR(0UL);
+}
+
+/**
+ * @brief       USBD Set Vendor Request
+ *
+ * @param[in]   pfnVendorReq    Vendor Request Callback Function
+ *
+ * @return      None
+ *
+ * @details     This function is used to set USBD vendor request callback function
+ */
+void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq)
+{
+    g_USBD_pfnVendorRequest = pfnVendorReq;
+}
+
+/**
+ * @brief       The callback function which called when get SET CONFIGURATION request
+ *
+ * @param[in]   pfnSetConfigCallback    Callback function pointer for SET CONFIGURATION request
+ *
+ * @return      None
+ *
+ * @details     This function is used to set the callback function which will be called at SET CONFIGURATION request.
+ */
+void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback)
+{
+    g_USBD_pfnSetConfigCallback = pfnSetConfigCallback;
+}
+
+
+/**
+ * @brief       EP stall lock function to avoid stall clear by USB SET FEATURE request.
+ *
+ * @param[in]   u32EpBitmap    Use bitmap to select which endpoints will be locked
+ *
+ * @return      None
+ *
+ * @details     This function is used to lock relative endpoint to avoid stall clear by SET FEATURE request.
+ *              If ep stall locked, user needs to reset USB device or re-configure device to clear it.
+ */
+void USBD_LockEpStall(uint32_t u32EpBitmap)
+{
+    g_USBD_u32EpStallLock = u32EpBitmap;
+}
+
+/**@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group USBD_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_usci_i2c.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_usci_i2c.c
new file mode 100644
index 0000000000..f45c055227
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_usci_i2c.c
@@ -0,0 +1,1659 @@
+/****************************************************************************//**
+ * @file     usci_i2c.c
+ * @version  V3.00
+ * $Revision: 1 $
+ * $Date: 16/07/07 7:50p $
+ * @brief    M2355 series USCI I2C(UI2C) driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup USCI_I2C_Driver USCI_I2C Driver
+  @{
+*/
+
+
+/** @addtogroup USCI_I2C_EXPORTED_FUNCTIONS USCI_I2C Exported Functions
+  @{
+*/
+
+/**
+ *    @brief        This function makes USCI_I2C module be ready and set the wanted bus clock
+ *
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *    @param[in]    u32BusClock     The target bus speed of USCI_I2C module.
+ *
+ *    @return       Actual USCI_I2C bus clock frequency.
+ *
+ *    @details      Enable USCI_I2C module and configure USCI_I2C module(bus clock, data format).
+ */
+uint32_t UI2C_Open(UI2C_T *ui2c, uint32_t u32BusClock)
+{
+    uint32_t u32ClkDiv;
+    uint32_t u32Pclk;
+
+    if((ui2c == UI2C1) || (ui2c == UI2C1_NS))
+    {
+        u32Pclk = CLK_GetPCLK1Freq();
+    }
+    else
+    {
+        u32Pclk = CLK_GetPCLK0Freq();
+    }
+
+    u32ClkDiv = (uint32_t)((((((u32Pclk / 2u) * 10u) / (u32BusClock)) + 5u) / 10u) - 1u); /* Compute proper divider for USCI_I2C clock */
+
+    /* Enable USCI_I2C protocol */
+    ui2c->CTL &= ~UI2C_CTL_FUNMODE_Msk;
+    ui2c->CTL = 4u << UI2C_CTL_FUNMODE_Pos;
+
+    /* Data format configuration */
+    /* 8 bit data length */
+    ui2c->LINECTL &= ~UI2C_LINECTL_DWIDTH_Msk;
+    ui2c->LINECTL |= 8u << UI2C_LINECTL_DWIDTH_Pos;
+
+    /* MSB data format */
+    ui2c->LINECTL &= ~UI2C_LINECTL_LSB_Msk;
+
+    /* Set USCI_I2C bus clock */
+    ui2c->BRGEN &= ~UI2C_BRGEN_CLKDIV_Msk;
+    ui2c->BRGEN |= (u32ClkDiv << UI2C_BRGEN_CLKDIV_Pos);
+    ui2c->PROTCTL |=  UI2C_PROTCTL_PROTEN_Msk;
+
+    return (u32Pclk / ((u32ClkDiv + 1u) << 1u));
+}
+
+/**
+ *    @brief        This function closes the USCI_I2C module
+ *
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *
+ *    @return       None
+ *
+ *    @details      Close USCI_I2C protocol function.
+ */
+void UI2C_Close(UI2C_T *ui2c)
+{
+    /* Disable USCI_I2C function */
+    ui2c->CTL &= ~UI2C_CTL_FUNMODE_Msk;
+}
+
+/**
+ *    @brief        This function clears the time-out flag
+ *
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *
+ *    @return       None
+ *
+ *    @details      Clear time-out flag when time-out flag is set.
+ */
+void UI2C_ClearTimeoutFlag(UI2C_T *ui2c)
+{
+    ui2c->PROTSTS = UI2C_PROTSTS_TOIF_Msk;
+}
+
+/**
+ *    @brief        This function sets the control bit of the USCI_I2C module.
+ *
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *    @param[in]    u8Start         Set START bit to USCI_I2C module.
+ *    @param[in]    u8Stop Set      STOP bit to USCI_I2C module.
+ *    @param[in]    u8Ptrg Set      PTRG bit to USCI_I2C module.
+ *    @param[in]    u8Ack Set       ACK bit to USCI_I2C module.
+ *
+ *    @return       None
+ *
+ *    @details      The function set USCI_I2C control bit of USCI_I2C bus protocol.
+ */
+void UI2C_Trigger(UI2C_T *ui2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Ptrg, uint8_t u8Ack)
+{
+    uint32_t u32Reg = 0u;
+    uint32_t u32Val = ui2c->PROTCTL & ~(UI2C_PROTCTL_STA_Msk | UI2C_PROTCTL_STO_Msk | UI2C_PROTCTL_AA_Msk);
+
+    if(u8Start)
+    {
+        u32Reg |= UI2C_PROTCTL_STA_Msk;
+    }
+    if(u8Stop)
+    {
+        u32Reg |= UI2C_PROTCTL_STO_Msk;
+    }
+    if(u8Ptrg)
+    {
+        u32Reg |= UI2C_PROTCTL_PTRG_Msk;
+    }
+    if(u8Ack)
+    {
+        u32Reg |= UI2C_PROTCTL_AA_Msk;
+    }
+    ui2c->PROTCTL = u32Val | u32Reg;
+}
+
+/**
+ *    @brief        This function disables the interrupt of USCI_I2C module
+ *
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *    @param[in]    u32Mask         The combination of all related interrupt enable bits.
+ *                                  Each bit corresponds to an interrupt enable bit.
+ *                                  This parameter decides which interrupts will be disabled. It is combination of:
+ *                                  - \ref UI2C_TO_INT_MASK
+ *                                  - \ref UI2C_STAR_INT_MASK
+ *                                  - \ref UI2C_STOR_INT_MASK
+ *                                  - \ref UI2C_NACK_INT_MASK
+ *                                  - \ref UI2C_ARBLO_INT_MASK
+ *                                  - \ref UI2C_ERR_INT_MASK
+ *                                  - \ref UI2C_ACK_INT_MASK
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to disable USCI_I2C bus interrupt events.
+ */
+void UI2C_DisableInt(UI2C_T *ui2c, uint32_t u32Mask)
+{
+    /* Disable time-out interrupt flag */
+    if((u32Mask & UI2C_TO_INT_MASK) == UI2C_TO_INT_MASK)
+    {
+        ui2c->PROTIEN &= ~UI2C_PROTIEN_TOIEN_Msk;
+    }
+    /* Disable start condition received interrupt flag */
+    if((u32Mask & UI2C_STAR_INT_MASK) == UI2C_STAR_INT_MASK)
+    {
+        ui2c->PROTIEN &= ~UI2C_PROTIEN_STARIEN_Msk;
+    }
+    /* Disable stop condition received interrupt flag */
+    if((u32Mask & UI2C_STOR_INT_MASK) == UI2C_STOR_INT_MASK)
+    {
+        ui2c->PROTIEN &= ~UI2C_PROTIEN_STORIEN_Msk;
+    }
+    /* Disable non-acknowledge interrupt flag */
+    if((u32Mask & UI2C_NACK_INT_MASK) == UI2C_NACK_INT_MASK)
+    {
+        ui2c->PROTIEN &= ~UI2C_PROTIEN_NACKIEN_Msk;
+    }
+    /* Disable arbitration lost interrupt flag */
+    if((u32Mask & UI2C_ARBLO_INT_MASK) == UI2C_ARBLO_INT_MASK)
+    {
+        ui2c->PROTIEN &= ~UI2C_PROTIEN_ARBLOIEN_Msk;
+    }
+
+    /* Disable error interrupt flag */
+    if((u32Mask & UI2C_ERR_INT_MASK) == UI2C_ERR_INT_MASK)
+    {
+        ui2c->PROTIEN &= ~UI2C_PROTIEN_ERRIEN_Msk;
+    }
+    /* Disable acknowledge interrupt flag */
+    if((u32Mask & UI2C_ACK_INT_MASK) == UI2C_ACK_INT_MASK)
+    {
+        ui2c->PROTIEN &= ~UI2C_PROTIEN_ACKIEN_Msk;
+    }
+}
+
+/**
+ *    @brief        This function enables the interrupt of USCI_I2C module.
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *    @param[in]    u32Mask         The combination of all related interrupt enable bits.
+ *                                  Each bit corresponds to a interrupt enable bit.
+ *                                  This parameter decides which interrupts will be enabled. It is combination of:
+ *                                  - \ref UI2C_TO_INT_MASK
+ *                                  - \ref UI2C_STAR_INT_MASK
+ *                                  - \ref UI2C_STOR_INT_MASK
+ *                                  - \ref UI2C_NACK_INT_MASK
+ *                                  - \ref UI2C_ARBLO_INT_MASK
+ *                                  - \ref UI2C_ERR_INT_MASK
+ *                                  - \ref UI2C_ACK_INT_MASK
+ *    @return None
+ *
+ *    @details      The function is used to enable USCI_I2C bus interrupt events.
+ */
+void UI2C_EnableInt(UI2C_T *ui2c, uint32_t u32Mask)
+{
+    /* Enable time-out interrupt flag */
+    if((u32Mask & UI2C_TO_INT_MASK) == UI2C_TO_INT_MASK)
+    {
+        ui2c->PROTIEN |= UI2C_PROTIEN_TOIEN_Msk;
+    }
+    /* Enable start condition received interrupt flag */
+    if((u32Mask & UI2C_STAR_INT_MASK) == UI2C_STAR_INT_MASK)
+    {
+        ui2c->PROTIEN |= UI2C_PROTIEN_STARIEN_Msk;
+    }
+    /* Enable stop condition received interrupt flag */
+    if((u32Mask & UI2C_STOR_INT_MASK) == UI2C_STOR_INT_MASK)
+    {
+        ui2c->PROTIEN |= UI2C_PROTIEN_STORIEN_Msk;
+    }
+    /* Enable non-acknowledge interrupt flag */
+    if((u32Mask & UI2C_NACK_INT_MASK) == UI2C_NACK_INT_MASK)
+    {
+        ui2c->PROTIEN |= UI2C_PROTIEN_NACKIEN_Msk;
+    }
+    /* Enable arbitration lost interrupt flag */
+    if((u32Mask & UI2C_ARBLO_INT_MASK) == UI2C_ARBLO_INT_MASK)
+    {
+        ui2c->PROTIEN |= UI2C_PROTIEN_ARBLOIEN_Msk;
+    }
+    /* Enable error interrupt flag */
+    if((u32Mask & UI2C_ERR_INT_MASK) == UI2C_ERR_INT_MASK)
+    {
+        ui2c->PROTIEN |= UI2C_PROTIEN_ERRIEN_Msk;
+    }
+    /* Enable acknowledge interrupt flag */
+    if((u32Mask & UI2C_ACK_INT_MASK) == UI2C_ACK_INT_MASK)
+    {
+        ui2c->PROTIEN |= UI2C_PROTIEN_ACKIEN_Msk;
+    }
+}
+
+/**
+ *    @brief        This function returns the real bus clock of USCI_I2C module
+ *
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *
+ *    @return       Actual USCI_I2C bus clock frequency.
+ *
+ *    @details      The function returns the actual USCI_I2C module bus clock.
+ */
+uint32_t UI2C_GetBusClockFreq(UI2C_T *ui2c)
+{
+    uint32_t u32Divider;
+    uint32_t u32Pclk;
+
+    if((ui2c == UI2C1) || (ui2c == UI2C1_NS))
+    {
+        u32Pclk = CLK_GetPCLK1Freq();
+    }
+    else
+    {
+        u32Pclk = CLK_GetPCLK0Freq();
+    }
+    u32Divider = (ui2c->BRGEN & UI2C_BRGEN_CLKDIV_Msk) >> UI2C_BRGEN_CLKDIV_Pos;
+
+    return (u32Pclk / ((u32Divider + 1u) << 1u));
+}
+
+/**
+ *    @brief        This function sets bus clock frequency of USCI_I2C module
+ *
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *    @param[in]    u32BusClock     The target bus speed of USCI_I2C module.
+ *
+ *    @return Actual USCI_I2C bus clock frequency.
+ *
+ *    @details      Use this function set USCI_I2C bus clock frequency and return actual bus clock.
+ */
+uint32_t UI2C_SetBusClockFreq(UI2C_T *ui2c, uint32_t u32BusClock)
+{
+    uint32_t u32ClkDiv;
+    uint32_t u32Pclk;
+
+    if((ui2c == UI2C1) || (ui2c == UI2C1_NS))
+    {
+        u32Pclk = CLK_GetPCLK1Freq();
+    }
+    else
+    {
+        u32Pclk = CLK_GetPCLK0Freq();
+    }
+    u32ClkDiv = (uint32_t)((((((u32Pclk / 2u) * 10u) / (u32BusClock)) + 5u) / 10u) - 1u); /* Compute proper divider for USCI_I2C clock */
+
+    /* Set USCI_I2C bus clock */
+    ui2c->BRGEN &= ~UI2C_BRGEN_CLKDIV_Msk;
+    ui2c->BRGEN |= (u32ClkDiv << UI2C_BRGEN_CLKDIV_Pos);
+
+    return (u32Pclk / ((u32ClkDiv + 1u) << 1u));
+}
+
+/**
+ *    @brief        This function gets the interrupt flag of USCI_I2C module
+ *
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *    @param[in]    u32Mask         The combination of all related interrupt sources.
+ *                                  Each bit corresponds to a interrupt source.
+ *                                  This parameter decides which interrupt flags will be read. It is combination of:
+ *                                  - \ref UI2C_TO_INT_MASK
+ *                                  - \ref UI2C_STAR_INT_MASK
+ *                                  - \ref UI2C_STOR_INT_MASK
+ *                                  - \ref UI2C_NACK_INT_MASK
+ *                                  - \ref UI2C_ARBLO_INT_MASK
+ *                                  - \ref UI2C_ERR_INT_MASK
+ *                                  - \ref UI2C_ACK_INT_MASK
+ *
+ *    @return       Interrupt flags of selected sources.
+ *
+ *    @details      Use this function to get USCI_I2C interrupt flag when module occurs interrupt event.
+ */
+uint32_t UI2C_GetIntFlag(UI2C_T *ui2c, uint32_t u32Mask)
+{
+    uint32_t u32IntFlag = 0U;
+    uint32_t u32TmpValue;
+
+    u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_TOIF_Msk;
+    /* Check Time-out Interrupt Flag */
+    if((u32Mask & UI2C_TO_INT_MASK) && (u32TmpValue))
+    {
+        u32IntFlag |= UI2C_TO_INT_MASK;
+    }
+
+    u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_STARIF_Msk;
+    /* Check Start Condition Received Interrupt Flag */
+    if((u32Mask & UI2C_STAR_INT_MASK) && (u32TmpValue))
+    {
+        u32IntFlag |= UI2C_STAR_INT_MASK;
+    }
+
+    u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_STORIF_Msk;
+    /* Check Stop Condition Received Interrupt Flag */
+    if((u32Mask & UI2C_STOR_INT_MASK) && (u32TmpValue))
+    {
+        u32IntFlag |= UI2C_STOR_INT_MASK;
+    }
+
+    u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_NACKIF_Msk;
+    /* Check Non-Acknowledge Interrupt Flag */
+    if((u32Mask & UI2C_NACK_INT_MASK) && (u32TmpValue))
+    {
+        u32IntFlag |= UI2C_NACK_INT_MASK;
+    }
+
+    u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_ARBLOIF_Msk;
+    /* Check Arbitration Lost Interrupt Flag */
+    if((u32Mask & UI2C_ARBLO_INT_MASK) && (u32TmpValue))
+    {
+        u32IntFlag |= UI2C_ARBLO_INT_MASK;
+    }
+
+    u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_ERRIF_Msk;
+    /* Check Error Interrupt Flag */
+    if((u32Mask & UI2C_ERR_INT_MASK) && (u32TmpValue))
+    {
+        u32IntFlag |= UI2C_ERR_INT_MASK;
+    }
+
+    u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_ACKIF_Msk;
+    /* Check Acknowledge Interrupt Flag */
+    if((u32Mask & UI2C_ACK_INT_MASK) && (u32TmpValue))
+    {
+        u32IntFlag |= UI2C_ACK_INT_MASK;
+    }
+
+    return u32IntFlag;
+}
+
+/**
+ *    @brief        This function clears the interrupt flag of USCI_I2C module.
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *    @param[in]    u32Mask         The combination of all related interrupt sources.
+ *                                  Each bit corresponds to a interrupt source.
+ *                                  This parameter decides which interrupt flags will be cleared. It is combination of:
+ *                                  - \ref UI2C_TO_INT_MASK
+ *                                  - \ref UI2C_STAR_INT_MASK
+ *                                  - \ref UI2C_STOR_INT_MASK
+ *                                  - \ref UI2C_NACK_INT_MASK
+ *                                  - \ref UI2C_ARBLO_INT_MASK
+ *                                  - \ref UI2C_ERR_INT_MASK
+ *                                  - \ref UI2C_ACK_INT_MASK
+ *
+ *    @return       None
+ *
+ *    @details      Use this function to clear USCI_I2C interrupt flag when module occurs interrupt event and set flag.
+ */
+void UI2C_ClearIntFlag(UI2C_T *ui2c, uint32_t u32Mask)
+{
+    /* Clear Time-out Interrupt Flag */
+    if(u32Mask & UI2C_TO_INT_MASK)
+    {
+        ui2c->PROTSTS = UI2C_PROTSTS_TOIF_Msk;
+    }
+    /* Clear Start Condition Received Interrupt Flag */
+    if(u32Mask & UI2C_STAR_INT_MASK)
+    {
+        ui2c->PROTSTS = UI2C_PROTSTS_STARIF_Msk;
+    }
+    /* Clear Stop Condition Received Interrupt Flag */
+    if(u32Mask & UI2C_STOR_INT_MASK)
+    {
+        ui2c->PROTSTS = UI2C_PROTSTS_STORIF_Msk;
+    }
+    /* Clear Non-Acknowledge Interrupt Flag */
+    if(u32Mask & UI2C_NACK_INT_MASK)
+    {
+        ui2c->PROTSTS = UI2C_PROTSTS_NACKIF_Msk;
+    }
+    /* Clear Arbitration Lost Interrupt Flag */
+    if(u32Mask & UI2C_ARBLO_INT_MASK)
+    {
+        ui2c->PROTSTS = UI2C_PROTSTS_ARBLOIF_Msk;
+    }
+    /* Clear Error Interrupt Flag */
+    if(u32Mask & UI2C_ERR_INT_MASK)
+    {
+        ui2c->PROTSTS = UI2C_PROTSTS_ERRIF_Msk;
+    }
+    /* Clear Acknowledge Interrupt Flag */
+    if(u32Mask & UI2C_ACK_INT_MASK)
+    {
+        ui2c->PROTSTS = UI2C_PROTSTS_ACKIF_Msk;
+    }
+}
+
+/**
+ *    @brief        This function returns the data stored in data register of USCI_I2C module.
+ *
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *
+ *    @return       USCI_I2C data.
+ *
+ *    @details      To read a byte data from USCI_I2C module receive data register.
+ */
+uint32_t UI2C_GetData(UI2C_T *ui2c)
+{
+    return (ui2c->RXDAT);
+}
+
+/**
+ *    @brief        This function writes a byte data to data register of USCI_I2C module
+ *
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *    @param[in]    u8Data          The data which will be written to data register of USCI_I2C module.
+ *
+ *    @return       None
+ *
+ *    @details      To write a byte data to transmit data register to transmit data.
+ */
+void UI2C_SetData(UI2C_T *ui2c, uint8_t u8Data)
+{
+    ui2c->TXDAT = u8Data;
+}
+
+/**
+ *    @brief        Configure slave address and enable GC mode
+ *
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *    @param[in]    u8SlaveNo       Slave channel number [0/1]
+ *    @param[in]    u16SlaveAddr    The slave address.
+ *    @param[in]    u8GCMode        GC mode enable or not. Valid values are:
+ *                                  - \ref UI2C_GCMODE_ENABLE
+ *                                  - \ref UI2C_GCMODE_DISABLE
+ *
+ *    @return None
+ *
+ *    @details      To configure USCI_I2C module slave address and GC mode.
+ */
+void UI2C_SetSlaveAddr(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddr, uint8_t u8GCMode)
+{
+    if(u8SlaveNo)
+    {
+        ui2c->DEVADDR1  = u16SlaveAddr;
+    }
+    else
+    {
+        ui2c->DEVADDR0  = u16SlaveAddr;
+    }
+    ui2c->PROTCTL  = (ui2c->PROTCTL & ~UI2C_PROTCTL_GCFUNC_Msk) | u8GCMode;
+}
+
+/**
+ *    @brief        Configure the mask bit of slave address.
+ *
+ *    @param[in]    ui2c             The pointer of the specified USCI_I2C module.
+ *    @param[in]    u8SlaveNo        Slave channle number [0/1]
+ *    @param[in]    u16SlaveAddrMask The slave address mask.
+ *
+ *    @return None
+ *
+ *    @details      To configure USCI_I2C module slave  address mask bit.
+ *    @note         The corresponding address bit is "Don't Care".
+ */
+void UI2C_SetSlaveAddrMask(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddrMask)
+{
+    if(u8SlaveNo)
+    {
+        ui2c->ADDRMSK1  = u16SlaveAddrMask;
+    }
+    else
+    {
+        ui2c->ADDRMSK0  = u16SlaveAddrMask;
+    }
+}
+
+/**
+ *    @brief        This function enables time-out function and configures timeout counter
+ *
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *    @param[in]    u32TimeoutCnt   Timeout counter. Valid values are between 0~0x3FF.
+ *
+ *    @return       None
+ *
+ *    @details      To enable USCI_I2C bus time-out function and set time-out counter.
+ */
+void UI2C_EnableTimeout(UI2C_T *ui2c, uint32_t u32TimeoutCnt)
+{
+    ui2c->PROTCTL = (ui2c->PROTCTL & ~UI2C_PROTCTL_TOCNT_Msk) | (u32TimeoutCnt << UI2C_PROTCTL_TOCNT_Pos);
+    ui2c->BRGEN = (ui2c->BRGEN & ~UI2C_BRGEN_TMCNTSRC_Msk) | UI2C_BRGEN_TMCNTEN_Msk;
+}
+
+/**
+ *    @brief        This function disables time-out function
+ *
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *
+ *    @return       None
+ *
+ *    @details      To disable USCI_I2C bus time-out function.
+ */
+void UI2C_DisableTimeout(UI2C_T *ui2c)
+{
+    ui2c->PROTCTL &= ~UI2C_PROTCTL_TOCNT_Msk;
+    ui2c->BRGEN &= ~UI2C_BRGEN_TMCNTEN_Msk;
+}
+
+/**
+ *    @brief        This function enables the wakeup function of USCI_I2C module
+ *
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *    @param[in]    u8WakeupMode    The wake-up mode selection. Valid values are:
+ *                                  - \ref UI2C_DATA_TOGGLE_WK
+ *                                  - \ref UI2C_ADDR_MATCH_WK
+ *
+ *    @return       None
+ *
+ *    @details      To enable USCI_I2C module wake-up function.
+ */
+void UI2C_EnableWakeup(UI2C_T *ui2c, uint8_t u8WakeupMode)
+{
+    ui2c->WKCTL = (ui2c->WKCTL & ~UI2C_WKCTL_WKADDREN_Msk) | (u8WakeupMode | UI2C_WKCTL_WKEN_Msk);
+}
+
+/**
+ *    @brief        This function disables the wakeup function of USCI_I2C module
+ *
+ *    @param[in]    ui2c            The pointer of the specified USCI_I2C module.
+ *
+ *    @return       None
+ *
+ *    @details      To disable USCI_I2C module wake-up function.
+ */
+void UI2C_DisableWakeup(UI2C_T *ui2c)
+{
+    ui2c->WKCTL &= ~UI2C_WKCTL_WKEN_Msk;
+}
+
+/**
+  * @brief      Write a byte to Slave
+  *
+  * @param[in]  *ui2c           The pointer of the specified USCI_I2C module.
+  * @param[in]  u8SlaveAddr     Access Slave address(7-bit)
+  * @param[in]  data            Write a byte data to Slave
+  *
+  * @retval     0               Write data success
+  * @retval     1               Write data fail, or bus occurs error events
+  *
+  * @details    The function is used for USCI_I2C Master write a byte data to Slave.
+  *
+  */
+
+uint8_t UI2C_WriteByte(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t data)
+{
+    uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U;
+    enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START;
+
+    UI2C_START(ui2c);                                                       /* Send START */
+
+    while(u8Xfering)
+    {
+        while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U));                      /* Wait UI2C new status occur */
+
+        switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)
+        {
+            case UI2C_PROTSTS_STARIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk);     /* Clear START INT Flag */
+                UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x00U);              /* Write SLA+W to Register UI2C_TXDAT */
+                eEvent = MASTER_SEND_ADDRESS;
+                u8Ctrl = UI2C_CTL_PTRG;                                     /* Clear SI */
+                break;
+
+            case UI2C_PROTSTS_ACKIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk);      /* Clear ACK INT Flag */
+
+                if(eEvent == MASTER_SEND_ADDRESS)
+                {
+                    UI2C_SET_DATA(ui2c, data);                              /* Write data to UI2C_TXDAT */
+                    eEvent = MASTER_SEND_DATA;
+                }
+                else
+                {
+                    u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO);                /* Clear SI and send STOP */
+                }
+
+                break;
+
+            case UI2C_PROTSTS_NACKIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk);     /* Clear NACK INT Flag */
+                u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO);                    /* Clear SI and send STOP */
+                u8Err = 1U;
+                break;
+
+            case UI2C_PROTSTS_STORIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk);     /* Clear STOP INT Flag */
+                u8Ctrl = UI2C_CTL_PTRG;                                     /* Clear SI */
+                u8Xfering = 0U;
+                break;
+
+            case UI2C_PROTSTS_ARBLOIF_Msk:                                  /* Arbitration Lost */
+            default:                                                        /* Unknow status */
+                u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO);                    /* Clear SI and send STOP */
+                u8Err = 1U;
+                break;
+        }
+
+        UI2C_SET_CONTROL_REG(ui2c, u8Ctrl);                                 /* Write controlbit to UI2C_PROTCTL register */
+    }
+
+    return (u8Err | u8Xfering);                                             /* return (Success)/(Fail) status */
+}
+
+/**
+  * @brief      Write multi bytes to Slave
+  *
+  * @param[in]  *ui2c           The pointer of the specified USCI_I2C module.
+  * @param[in]  u8SlaveAddr     Access Slave address(7-bit)
+  * @param[in]  *data           Pointer to array to write data to Slave
+  * @param[in]  u32wLen         How many bytes need to write to Slave
+  *
+  * @return     A length of how many bytes have been transmitted.
+  *
+  * @details    The function is used for USCI_I2C Master write multi bytes data to Slave.
+  *
+  */
+
+uint32_t UI2C_WriteMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t *data, uint32_t u32wLen)
+{
+    uint8_t u8Xfering = 1U, u8Ctrl = 0U;
+    uint32_t u32txLen = 0U;
+
+    UI2C_START(ui2c);                                                       /* Send START */
+
+    while(u8Xfering)
+    {
+        while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U));                      /* Wait UI2C new status occur */
+
+        switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)
+        {
+            case UI2C_PROTSTS_STARIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk);     /* Clear START INT Flag */
+                UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x00U);              /* Write SLA+W to Register UI2C_TXDAT */
+                u8Ctrl = UI2C_CTL_PTRG;                                     /* Clear SI */
+                break;
+
+            case UI2C_PROTSTS_ACKIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk);      /* Clear ACK INT Flag */
+
+                if(u32txLen < u32wLen)
+                    UI2C_SET_DATA(ui2c, data[u32txLen++]);                  /* Write data to UI2C_TXDAT */
+                else
+                {
+                    u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO);                /* Clear SI and send STOP */
+                }
+
+                break;
+
+            case UI2C_PROTSTS_NACKIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk);     /* Clear NACK INT Flag */
+                u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO);                    /* Clear SI and send STOP */
+                break;
+
+            case UI2C_PROTSTS_STORIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk);     /* Clear STOP INT Flag */
+                u8Ctrl = UI2C_CTL_PTRG;                                     /* Clear SI */
+                u8Xfering = 0U;
+                break;
+
+            case UI2C_PROTSTS_ARBLOIF_Msk:                                  /* Arbitration Lost */
+            default:                                                        /* Unknow status */
+                u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO);                    /* Clear SI and send STOP */
+                break;
+        }
+
+        UI2C_SET_CONTROL_REG(ui2c, u8Ctrl);                                 /* Write controlbit to UI2C_CTL register */
+    }
+
+    return u32txLen;                                                        /* Return bytes length that have been transmitted */
+}
+
+/**
+  * @brief      Specify a byte register address and write a byte to Slave
+  *
+  * @param[in]  *ui2c           The pointer of the specified USCI_I2C module.
+  * @param[in]  u8SlaveAddr     Access Slave address(7-bit)
+  * @param[in]  u8DataAddr      Specify a address (1 byte) of data write to
+  * @param[in]  data            A byte data to write it to Slave
+  *
+  * @retval     0               Write data success
+  * @retval     1               Write data fail, or bus occurs error events
+  *
+  * @details    The function is used for USCI_I2C Master specify a address that data write to in Slave.
+  *
+  */
+
+uint8_t UI2C_WriteByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data)
+{
+    uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U;
+    uint32_t u32txLen = 0U;
+
+    UI2C_START(ui2c);                                                       /* Send START */
+
+    while(u8Xfering)
+    {
+        while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U));                      /* Wait UI2C new status occur */
+
+        switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)
+        {
+            case UI2C_PROTSTS_STARIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk);     /* Clear START INT Flag */
+                UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x00U);              /* Write SLA+W to Register UI2C_TXDAT */
+                u8Ctrl = UI2C_CTL_PTRG;                                     /* Clear SI */
+                break;
+
+            case UI2C_PROTSTS_ACKIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk);      /* Clear ACK INT Flag */
+
+                if(u32txLen == 0U)
+                {
+                    UI2C_SET_DATA(ui2c, u8DataAddr);                        /* Write data address to UI2C_TXDAT */
+                    u32txLen++;
+                }
+                else if(u32txLen == 1U)
+                {
+                    UI2C_SET_DATA(ui2c, data);                              /* Write data to UI2C_TXDAT */
+                    u32txLen++;
+                }
+                else
+                {
+                    u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO);                /* Clear SI and send STOP */
+                }
+
+                break;
+
+            case UI2C_PROTSTS_NACKIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk);     /* Clear NACK INT Flag */
+                u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO);                    /* Clear SI and send STOP */
+                u8Err = 1U;
+                break;
+
+            case UI2C_PROTSTS_STORIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk);     /* Clear STOP INT Flag */
+                u8Ctrl = UI2C_CTL_PTRG;                                     /* Clear SI */
+                u8Xfering = 0U;
+                break;
+
+            case UI2C_PROTSTS_ARBLOIF_Msk:                                  /* Arbitration Lost */
+            default:                                                        /* Unknow status */
+                u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO);                    /* Clear SI and send STOP */
+                u8Err = 1U;
+                break;
+        }
+
+        UI2C_SET_CONTROL_REG(ui2c, u8Ctrl);                                 /* Write controlbit to UI2C_CTL register */
+    }
+
+    return (u8Err | u8Xfering);                                             /* return (Success)/(Fail) status */
+}
+
+
+/**
+  * @brief      Specify a byte register address and write multi bytes to Slave
+  *
+  * @param[in]  *ui2c           The pointer of the specified USCI_I2C module.
+  * @param[in]  u8SlaveAddr     Access Slave address(7-bit)
+  * @param[in]  u8DataAddr      Specify a address (1 byte) of data write to
+  * @param[in]  *data           Pointer to array to write data to Slave
+  * @param[in]  u32wLen         How many bytes need to write to Slave
+  *
+  * @return     A length of how many bytes have been transmitted.
+  *
+  * @details    The function is used for USCI_I2C Master specify a byte address that multi data bytes write to in Slave.
+  *
+  */
+
+uint32_t UI2C_WriteMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *data, uint32_t u32wLen)
+{
+    uint8_t u8Xfering = 1U, u8Ctrl = 0U;
+    uint32_t u32txLen = 0U;
+    enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START;
+
+    UI2C_START(ui2c);                                                       /* Send START */
+
+    while(u8Xfering)
+    {
+        while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U));                      /* Wait UI2C new status occur */
+
+        switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)
+        {
+            case UI2C_PROTSTS_STARIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk);     /* Clear START INT Flag */
+                UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x00U);              /* Write SLA+W to Register UI2C_TXDAT */
+                eEvent = MASTER_SEND_ADDRESS;
+                u8Ctrl = UI2C_CTL_PTRG;                                     /* Clear SI */
+                break;
+
+            case UI2C_PROTSTS_ACKIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk);      /* Clear ACK INT Flag */
+
+                if(eEvent == MASTER_SEND_ADDRESS)
+                {
+                    UI2C_SET_DATA(ui2c, u8DataAddr);                        /* Write data address to UI2C_TXDAT */
+                    eEvent = MASTER_SEND_DATA;
+                }
+                else
+                {
+                    if(u32txLen < u32wLen)
+                        UI2C_SET_DATA(ui2c, data[u32txLen++]);              /* Write data to UI2C_TXDAT */
+                    else
+                    {
+                        u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO);            /* Clear SI and send STOP */
+                    }
+                }
+
+                break;
+
+            case UI2C_PROTSTS_NACKIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk);     /* Clear NACK INT Flag */
+                u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO);                    /* Clear SI and send STOP */
+                break;
+
+            case UI2C_PROTSTS_STORIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk);     /* Clear STOP INT Flag */
+                u8Ctrl = UI2C_CTL_PTRG;                                     /* Clear SI */
+                u8Xfering = 0U;
+                break;
+
+            case UI2C_PROTSTS_ARBLOIF_Msk:                                  /* Arbitration Lost */
+            default:                                                        /* Unknow status */
+                u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO);                    /* Clear SI and send STOP */
+                break;
+        }
+
+        UI2C_SET_CONTROL_REG(ui2c, u8Ctrl);                                 /* Write controlbit to UI2C_CTL register */
+    }
+
+    return u32txLen;                                                        /* Return bytes length that have been transmitted */
+}
+
+/**
+  * @brief      Specify two bytes register address and Write a byte to Slave
+  *
+  * @param[in]  *ui2c            The pointer of the specified USCI_I2C module.
+  * @param[in]  u8SlaveAddr     Access Slave address(7-bit)
+  * @param[in]  u16DataAddr     Specify a address (2 byte) of data write to
+  * @param[in]  data            Write a byte data to Slave
+  *
+  * @retval     0               Write data success
+  * @retval     1               Write data fail, or bus occurs error events
+  *
+  * @details    The function is used for USCI_I2C Master specify two bytes address that data write to in Slave.
+  *
+  */
+
+uint8_t UI2C_WriteByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data)
+{
+    uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U;
+    uint32_t u32txLen = 0U;
+
+    UI2C_START(ui2c);                                                           /* Send START */
+
+    while(u8Xfering)
+    {
+        while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U));                      /* Wait UI2C new status occur */
+
+        switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)
+        {
+            case UI2C_PROTSTS_STARIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk);         /* Clear START INT Flag */
+                UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x00U);                  /* Write SLA+W to Register UI2C_TXDAT */
+                u8Ctrl = UI2C_CTL_PTRG;                                         /* Clear SI */
+                break;
+
+            case UI2C_PROTSTS_ACKIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk);          /* Clear ACK INT Flag */
+
+                if(u32txLen == 0U)
+                {
+                    UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFF00U) >> 8U);  /* Write Hi byte data address to UI2C_TXDAT */
+                    u32txLen++;
+                }
+                else if(u32txLen == 1U)
+                {
+                    UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU));         /* Write Lo byte data address to UI2C_TXDAT */
+                    u32txLen++;
+                }
+                else if(u32txLen == 2U)
+                {
+                    UI2C_SET_DATA(ui2c, data);                                  /* Write data to UI2C_TXDAT */
+                    u32txLen++;
+                }
+                else
+                {
+                    u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO);                /* Clear SI and send STOP */
+                }
+
+                break;
+
+            case UI2C_PROTSTS_NACKIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk);         /* Clear NACK INT Flag */
+                u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO);                        /* Clear SI and send STOP */
+                u8Err = 1U;
+                break;
+
+            case UI2C_PROTSTS_STORIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk);     /* Clear STOP INT Flag */
+                u8Ctrl = UI2C_CTL_PTRG;                                     /* Clear SI */
+                u8Xfering = 0U;
+                break;
+
+            case UI2C_PROTSTS_ARBLOIF_Msk:                                      /* Arbitration Lost */
+            default:                                                            /* Unknow status */
+                u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO);                        /* Clear SI and send STOP */
+                u8Err = 1U;
+                break;
+        }
+
+        UI2C_SET_CONTROL_REG(ui2c, u8Ctrl);                                     /* Write controlbit to UI2C_CTL register */
+    }
+
+    return (u8Err | u8Xfering);
+}
+
+
+/**
+  * @brief      Specify two bytes register address and write multi bytes to Slave
+  *
+  * @param[in]  *ui2c           The pointer of the specified USCI_I2C module.
+  * @param[in]  u8SlaveAddr     Access Slave address(7-bit)
+  * @param[in]  u16DataAddr     Specify a address (2 bytes) of data write to
+  * @param[in]  *data           Pointer to array to write data to Slave
+  * @param[in]  u32wLen         How many bytes need to write to Slave
+  *
+  * @return     A length of how many bytes have been transmitted.
+  *
+  * @details    The function is used for USCI_I2C Master specify a byte address that multi data write to in Slave.
+  *
+  */
+
+uint32_t UI2C_WriteMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *data, uint32_t u32wLen)
+{
+    uint8_t u8Xfering = 1U, u8Addr = 1U, u8Ctrl = 0U;
+    uint32_t u32txLen = 0U;
+    enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START;
+
+    UI2C_START(ui2c);                                                           /* Send START */
+
+    while(u8Xfering)
+    {
+        while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U));                      /* Wait UI2C new status occur */
+
+        switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)
+        {
+            case UI2C_PROTSTS_STARIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk);         /* Clear START INT Flag */
+                UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x00U);                  /* Write SLA+W to Register UI2C_TXDAT */
+                eEvent = MASTER_SEND_ADDRESS;
+                u8Ctrl = UI2C_CTL_PTRG;                                         /* Clear SI */
+                break;
+
+            case UI2C_PROTSTS_ACKIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk);          /* Clear ACK INT Flag */
+
+                if(eEvent == MASTER_SEND_ADDRESS)
+                {
+                    UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFF00U) >> 8U);  /* Write Hi byte data address to UI2C_TXDAT */
+                    eEvent = MASTER_SEND_DATA;
+                }
+                else if(eEvent == MASTER_SEND_DATA)
+                {
+                    if(u8Addr)
+                    {
+                        UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU));         /* Write Lo byte data address to UI2C_TXDAT */
+                        u8Addr = 0;
+                    }
+                    else
+                    {
+                        if(u32txLen < u32wLen)
+                        {
+                            UI2C_SET_DATA(ui2c, data[u32txLen++]);                  /* Write data to UI2C_TXDAT */
+                        }
+                        else
+                        {
+                            u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO);                /* Clear SI and send STOP */
+                        }
+                    }
+                }
+
+                break;
+
+            case UI2C_PROTSTS_NACKIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk);         /* Clear NACK INT Flag */
+                u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO);                        /* Clear SI and send STOP */
+                break;
+
+            case UI2C_PROTSTS_STORIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk);     /* Clear STOP INT Flag */
+                u8Ctrl = UI2C_CTL_PTRG;                                     /* Clear SI */
+                u8Xfering = 0U;
+                break;
+
+            case UI2C_PROTSTS_ARBLOIF_Msk:                                      /* Arbitration Lost */
+            default:                                                            /* Unknow status */
+                u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO);                        /* Clear SI and send STOP */
+                break;
+        }
+
+        UI2C_SET_CONTROL_REG(ui2c, u8Ctrl);                                     /* Write controlbit to UI2C_CTL register */
+    }
+
+    return u32txLen;                                                            /* Return bytes length that have been transmitted */
+}
+
+/**
+  * @brief      Read a byte from Slave
+  *
+  * @param[in]  *ui2c           The pointer of the specified USCI_I2C module.
+  * @param[in]  u8SlaveAddr     Access Slave address(7-bit)
+  *
+  * @return     Read a byte data from Slave
+  *
+  * @details    The function is used for USCI_I2C Master to read a byte data from Slave.
+  *
+  */
+uint8_t UI2C_ReadByte(UI2C_T *ui2c, uint8_t u8SlaveAddr)
+{
+    uint8_t u8Xfering = 1U, u8Err = 0U, rdata = 0U, u8Ctrl = 0U;
+    enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START;
+
+    UI2C_START(ui2c);                                                       /* Send START */
+
+    while(u8Xfering)
+    {
+        while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U));                      /* Wait UI2C new status occur */
+
+        switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)
+        {
+            case UI2C_PROTSTS_STARIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk);     /* Clear START INT Flag */
+                UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x01U);              /* Write SLA+R to Register UI2C_TXDAT */
+                eEvent = MASTER_SEND_H_RD_ADDRESS;
+                u8Ctrl = UI2C_CTL_PTRG;
+                break;
+
+            case UI2C_PROTSTS_ACKIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk);      /* Clear ACK INT Flag */
+                eEvent = MASTER_READ_DATA;
+                break;
+
+            case UI2C_PROTSTS_NACKIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk);     /* Clear NACK INT Flag */
+
+                if(eEvent == MASTER_SEND_H_RD_ADDRESS)
+                {
+                    u8Err = 1U;
+                }
+                else
+                {
+                    rdata = (unsigned char) UI2C_GET_DATA(ui2c);            /* Receive Data */
+                }
+
+                u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO);                        /* Clear SI and send STOP */
+
+                break;
+
+            case UI2C_PROTSTS_STORIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk);     /* Clear STOP INT Flag */
+                u8Ctrl = UI2C_CTL_PTRG;                                     /* Clear SI */
+                u8Xfering = 0U;
+                break;
+
+            case UI2C_PROTSTS_ARBLOIF_Msk:                                  /* Arbitration Lost */
+            default:                                                        /* Unknow status */
+                u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO);                    /* Clear SI and send STOP */
+                u8Err = 1U;
+                break;
+        }
+
+        UI2C_SET_CONTROL_REG(ui2c, u8Ctrl);                                 /* Write controlbit to UI2C_PROTCTL register */
+    }
+
+    if(u8Err)
+        rdata = 0U;
+
+    return rdata;                                                           /* Return read data */
+}
+
+
+/**
+  * @brief      Read multi bytes from Slave
+  *
+  * @param[in]  *ui2c           The pointer of the specified USCI_I2C module.
+  * @param[in]  u8SlaveAddr     Access Slave address(7-bit)
+  * @param[out] *rdata          Point to array to store data from Slave
+  * @param[in]  u32rLen         How many bytes need to read from Slave
+  *
+  * @return     A length of how many bytes have been received
+  *
+  * @details    The function is used for USCI_I2C Master to read multi data bytes from Slave.
+  *
+  *
+  */
+uint32_t UI2C_ReadMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t *rdata, uint32_t u32rLen)
+{
+    uint8_t u8Xfering = 1U, u8Ctrl = 0U;
+    uint32_t u32rxLen = 0U;
+    enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START;
+
+    UI2C_START(ui2c);                                                       /* Send START */
+
+    while(u8Xfering)
+    {
+        while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U));                      /* Wait UI2C new status occur */
+
+        switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)
+        {
+            case UI2C_PROTSTS_STARIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk);     /* Clear START INT Flag */
+                UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x01U);              /* Write SLA+R to Register UI2C_TXDAT */
+                eEvent = MASTER_SEND_H_RD_ADDRESS;
+                u8Ctrl = UI2C_CTL_PTRG;
+                break;
+
+            case UI2C_PROTSTS_ACKIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk);      /* Clear ACK INT Flag */
+
+                if(eEvent == MASTER_SEND_H_RD_ADDRESS)
+                {
+                    u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA);
+                    eEvent = MASTER_READ_DATA;
+                }
+                else
+                {
+                    rdata[u32rxLen++] = (unsigned char) UI2C_GET_DATA(ui2c);    /* Receive Data */
+
+                    if(u32rxLen < (u32rLen - 1U))
+                        u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA);
+                    else
+                        u8Ctrl = UI2C_CTL_PTRG;
+                }
+
+                break;
+
+            case UI2C_PROTSTS_NACKIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk);     /* Clear NACK INT Flag */
+
+                if(eEvent == MASTER_READ_DATA)
+                    rdata[u32rxLen++] = (unsigned char) UI2C_GET_DATA(ui2c);    /* Receive Data */
+
+                u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO);                        /* Clear SI and send STOP */
+
+                break;
+
+            case UI2C_PROTSTS_STORIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk);     /* Clear STOP INT Flag */
+                u8Ctrl = UI2C_CTL_PTRG;                                     /* Clear SI */
+                u8Xfering = 0U;
+                break;
+
+            case UI2C_PROTSTS_ARBLOIF_Msk:                                  /* Arbitration Lost */
+            default:                                                        /* Unknow status */
+                u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO);                    /* Clear SI and send STOP */
+                break;
+        }
+
+        UI2C_SET_CONTROL_REG(ui2c, u8Ctrl);                                 /* Write controlbit to UI2C_PROTCTL register */
+    }
+
+    return u32rxLen;                                                        /* Return bytes length that have been received */
+}
+
+
+/**
+  * @brief      Specify a byte register address and read a byte from Slave
+  *
+  * @param[in]  *ui2c            The pointer of the specified USCI_I2C module.
+  * @param[in]  u8SlaveAddr     Access Slave address(7-bit)
+  * @param[in]  u8DataAddr      Specify a address(1 byte) of data read from
+  *
+  * @return     Read a byte data from Slave
+  *
+  * @details    The function is used for USCI_I2C Master specify a byte address that a data byte read from Slave.
+  *
+  *
+  */
+uint8_t UI2C_ReadByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr)
+{
+    uint8_t u8Xfering = 1U, u8Err = 0U, rdata = 0U, u8Ctrl = 0U;
+    enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START;
+
+    UI2C_START(ui2c);                                                       /* Send START */
+
+    while(u8Xfering)
+    {
+        while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U));                      /* Wait UI2C new status occur */
+
+        switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)
+        {
+            case UI2C_PROTSTS_STARIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk);     /* Clear START INT Flag */
+
+                if(eEvent == MASTER_SEND_START)
+                {
+                    UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x00U);          /* Write SLA+W to Register UI2C_TXDAT */
+                    eEvent = MASTER_SEND_ADDRESS;
+                }
+                else if(eEvent == MASTER_SEND_REPEAT_START)
+                {
+                    UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x01U);         /* Write SLA+R to Register TXDAT */
+                    eEvent = MASTER_SEND_H_RD_ADDRESS;
+                }
+
+                u8Ctrl = UI2C_CTL_PTRG;
+                break;
+
+            case UI2C_PROTSTS_ACKIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk);      /* Clear ACK INT Flag */
+
+                if(eEvent == MASTER_SEND_ADDRESS)
+                {
+                    UI2C_SET_DATA(ui2c, u8DataAddr);                        /* Write data address of register */
+                    u8Ctrl = UI2C_CTL_PTRG;
+                    eEvent = MASTER_SEND_DATA;
+                }
+                else if(eEvent == MASTER_SEND_DATA)
+                {
+                    u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA);                /* Send repeat START signal */
+                    eEvent = MASTER_SEND_REPEAT_START;
+                }
+                else
+                {
+                    /* SLA+R ACK */
+                    u8Ctrl = UI2C_CTL_PTRG;
+                    eEvent = MASTER_READ_DATA;
+                }
+
+                break;
+
+            case UI2C_PROTSTS_NACKIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk);     /* Clear NACK INT Flag */
+
+                if(eEvent == MASTER_READ_DATA)
+                {
+                    rdata = (uint8_t) UI2C_GET_DATA(ui2c);                  /* Receive Data */
+                }
+                else
+                {
+                    u8Err = 1U;
+                }
+
+                u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO);                        /* Clear SI and send STOP */
+
+                break;
+
+            case UI2C_PROTSTS_STORIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk);     /* Clear STOP INT Flag */
+                u8Ctrl = UI2C_CTL_PTRG;                                     /* Clear SI */
+                u8Xfering = 0U;
+                break;
+
+            case UI2C_PROTSTS_ARBLOIF_Msk:                                  /* Arbitration Lost */
+            default:                                                        /* Unknow status */
+                u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO);                    /* Clear SI and send STOP */
+                u8Err = 1U;
+                break;
+        }
+
+        UI2C_SET_CONTROL_REG(ui2c, u8Ctrl);                                 /* Write controlbit to UI2C_PROTCTL register */
+    }
+
+    if(u8Err)
+        rdata = 0U;                                                 /* If occurs error, return 0 */
+
+    return rdata;                                                  /* Return read data */
+}
+
+/**
+  * @brief      Specify a byte register address and read multi bytes from Slave
+  *
+  * @param[in]  *ui2c           The pointer of the specified USCI_I2C module.
+  * @param[in]  u8SlaveAddr     Access Slave address(7-bit)
+  * @param[in]  u8DataAddr      Specify a address (1 bytes) of data read from
+  * @param[out] *rdata          Point to array to store data from Slave
+  * @param[in]  u32rLen         How many bytes need to read from Slave
+  *
+  * @return     A length of how many bytes have been received
+  *
+  * @details    The function is used for USCI_I2C Master specify a byte address that multi data bytes read from Slave.
+  *
+  *
+  */
+uint32_t UI2C_ReadMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *rdata, uint32_t u32rLen)
+{
+    uint8_t u8Xfering = 1U, u8Ctrl = 0U;
+    uint32_t u32rxLen = 0U;
+    enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START;
+
+    UI2C_START(ui2c);                                                       /* Send START */
+
+    while(u8Xfering)
+    {
+        while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U));                      /* Wait UI2C new status occur */
+
+        switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)
+        {
+            case UI2C_PROTSTS_STARIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk);     /* Clear START INT Flag */
+
+                if(eEvent == MASTER_SEND_START)
+                {
+                    UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x00U);          /* Write SLA+W to Register UI2C_TXDAT */
+                    eEvent = MASTER_SEND_ADDRESS;
+                }
+                else if(eEvent == MASTER_SEND_REPEAT_START)
+                {
+                    UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x01U);         /* Write SLA+R to Register TXDAT */
+                    eEvent = MASTER_SEND_H_RD_ADDRESS;
+                }
+
+                u8Ctrl = UI2C_CTL_PTRG;
+                break;
+
+            case UI2C_PROTSTS_ACKIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk);      /* Clear ACK INT Flag */
+
+                if(eEvent == MASTER_SEND_ADDRESS)
+                {
+                    UI2C_SET_DATA(ui2c, u8DataAddr);                        /* Write data address of register */
+                    u8Ctrl = UI2C_CTL_PTRG;
+                    eEvent = MASTER_SEND_DATA;
+                }
+                else if(eEvent == MASTER_SEND_DATA)
+                {
+                    u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA);                /* Send repeat START signal */
+                    eEvent = MASTER_SEND_REPEAT_START;
+                }
+                else if(eEvent == MASTER_SEND_H_RD_ADDRESS)
+                {
+                    /* SLA+R ACK */
+                    u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA);
+                    eEvent = MASTER_READ_DATA;
+                }
+                else
+                {
+                    rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c);      /* Receive Data */
+
+                    if(u32rxLen < u32rLen - 1U)
+                        u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA);
+                    else
+                        u8Ctrl = UI2C_CTL_PTRG;
+                }
+
+                break;
+
+            case UI2C_PROTSTS_NACKIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk);     /* Clear NACK INT Flag */
+
+                if(eEvent == MASTER_READ_DATA)
+                    rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c);                  /* Receive Data */
+
+                u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO);                        /* Clear SI and send STOP */
+
+                break;
+
+            case UI2C_PROTSTS_STORIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk);     /* Clear STOP INT Flag */
+                u8Ctrl = UI2C_CTL_PTRG;                                     /* Clear SI */
+                u8Xfering = 0U;
+                break;
+
+            case UI2C_PROTSTS_ARBLOIF_Msk:                                  /* Arbitration Lost */
+            default:                                                        /* Unknow status */
+                u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO);                    /* Clear SI and send STOP */
+                break;
+        }
+
+        UI2C_SET_CONTROL_REG(ui2c, u8Ctrl);                                 /* Write controlbit to UI2C_PROTCTL register */
+    }
+
+    return u32rxLen;                                               /* Return bytes length that have been received */
+}
+
+/**
+  * @brief      Specify two bytes register address and read a byte from Slave
+  *
+  * @param[in]  *ui2c           The pointer of the specified USCI_I2C module.
+  * @param[in]  u8SlaveAddr     Access Slave address(7-bit)
+  * @param[in]  u16DataAddr     Specify a address(2 byte) of data read from
+  *
+  * @return     Read a byte data from Slave
+  *
+  * @details    The function is used for USCI_I2C Master specify two bytes address that a data byte read from Slave.
+  *
+  *
+  */
+uint8_t UI2C_ReadByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr)
+{
+    uint8_t u8Xfering = 1U, u8Err = 0U, rdata = 0U, u8Addr = 1U, u8Ctrl = 0U;
+    enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START;
+
+    UI2C_START(ui2c);                                                       /* Send START */
+
+    while(u8Xfering)
+    {
+        while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U));                      /* Wait UI2C new status occur */
+
+        switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)
+        {
+            case UI2C_PROTSTS_STARIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk);     /* Clear START INT Flag */
+
+                if(eEvent == MASTER_SEND_START)
+                {
+                    UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x00U);         /* Write SLA+W to Register UI2C_TXDAT */
+                    eEvent = MASTER_SEND_ADDRESS;
+                }
+                else if(eEvent == MASTER_SEND_REPEAT_START)
+                {
+                    UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x01U);         /* Write SLA+R to Register TXDAT */
+                    eEvent = MASTER_SEND_H_RD_ADDRESS;
+                }
+
+                u8Ctrl = UI2C_CTL_PTRG;
+                break;
+
+            case UI2C_PROTSTS_ACKIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk);      /* Clear ACK INT Flag */
+
+                if(eEvent == MASTER_SEND_ADDRESS)
+                {
+                    UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFF00U) >> 8U);  /* Write Hi byte address of register */
+                    eEvent = MASTER_SEND_DATA;
+                }
+                else if(eEvent == MASTER_SEND_DATA)
+                {
+                    if(u8Addr)
+                    {
+                        UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU));       /* Write Lo byte address of register */
+                        u8Addr = 0;
+                    }
+                    else
+                    {
+                        u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA);                /* Send repeat START signal */
+                        eEvent = MASTER_SEND_REPEAT_START;
+                    }
+                }
+                else
+                {
+                    /* SLA+R ACK */
+                    u8Ctrl = UI2C_CTL_PTRG;
+                    eEvent = MASTER_READ_DATA;
+                }
+
+                break;
+
+            case UI2C_PROTSTS_NACKIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk);     /* Clear NACK INT Flag */
+
+                if(eEvent == MASTER_READ_DATA)
+                {
+                    rdata = (uint8_t) UI2C_GET_DATA(ui2c);                  /* Receive Data */
+                }
+                else
+                {
+                    u8Err = 1U;
+                }
+
+                u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO);                        /* Clear SI and send STOP */
+
+                break;
+
+            case UI2C_PROTSTS_STORIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk);     /* Clear STOP INT Flag */
+                u8Ctrl = UI2C_CTL_PTRG;                                     /* Clear SI */
+                u8Xfering = 0U;
+                break;
+
+            case UI2C_PROTSTS_ARBLOIF_Msk:                                  /* Arbitration Lost */
+            default:                                                        /* Unknow status */
+                u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO);                    /* Clear SI and send STOP */
+                u8Err = 1U;
+                break;
+        }
+
+        UI2C_SET_CONTROL_REG(ui2c, u8Ctrl);                                 /* Write controlbit to UI2C_PROTCTL register */
+    }
+
+    if(u8Err)
+        rdata = 0U;                                                 /* If occurs error, return 0 */
+
+    return rdata;                                                  /* Return read data */
+}
+
+/**
+  * @brief      Specify two bytes register address and read multi bytes from Slave
+  *
+  * @param[in]  *ui2c            The pointer of the specified USCI_I2C module.
+  * @param[in]  u8SlaveAddr     Access Slave address(7-bit)
+  * @param[in]  u16DataAddr     Specify a address (2 bytes) of data read from
+  * @param[out] *rdata          Point to array to store data from Slave
+  * @param[in]  u32rLen         How many bytes need to read from Slave
+  *
+  * @return     A length of how many bytes have been received
+  *
+  * @details    The function is used for USCI_I2C Master specify two bytes address that multi data bytes read from Slave.
+  *
+  *
+  */
+uint32_t UI2C_ReadMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *rdata, uint32_t u32rLen)
+{
+    uint8_t u8Xfering = 1U, u8Addr = 1U, u8Ctrl = 0U;
+    uint32_t u32rxLen = 0U;
+    enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START;
+
+    UI2C_START(ui2c);                                                       /* Send START */
+
+    while(u8Xfering)
+    {
+        while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U));                      /* Wait UI2C new status occur */
+
+        switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)
+        {
+            case UI2C_PROTSTS_STARIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk);     /* Clear START INT Flag */
+
+                if(eEvent == MASTER_SEND_START)
+                {
+                    UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x00U);          /* Write SLA+W to Register UI2C_TXDAT */
+                    eEvent = MASTER_SEND_ADDRESS;
+                }
+                else if(eEvent == MASTER_SEND_REPEAT_START)
+                {
+                    UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x01U);         /* Write SLA+R to Register TXDAT */
+                    eEvent = MASTER_SEND_H_RD_ADDRESS;
+                }
+
+                u8Ctrl = UI2C_CTL_PTRG;
+                break;
+
+            case UI2C_PROTSTS_ACKIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk);      /* Clear ACK INT Flag */
+
+                if(eEvent == MASTER_SEND_ADDRESS)
+                {
+                    UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFF00U) >> 8U);  /* Write Hi byte address of register */
+                    eEvent = MASTER_SEND_DATA;
+                }
+                else if(eEvent == MASTER_SEND_DATA)
+                {
+                    if(u8Addr)
+                    {
+                        UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU));       /* Write Lo byte address of register */
+                        u8Addr = 0;
+                    }
+                    else
+                    {
+                        u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA);                /* Send repeat START signal */
+                        eEvent = MASTER_SEND_REPEAT_START;
+                    }
+                }
+                else if(eEvent == MASTER_SEND_H_RD_ADDRESS)
+                {
+                    u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA);
+                    eEvent = MASTER_READ_DATA;
+                }
+                else
+                {
+                    rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c);      /* Receive Data */
+
+                    if(u32rxLen < u32rLen - 1U)
+                        u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA);
+                    else
+                        u8Ctrl = UI2C_CTL_PTRG;
+                }
+
+                break;
+
+            case UI2C_PROTSTS_NACKIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk);     /* Clear NACK INT Flag */
+
+                if(eEvent == MASTER_READ_DATA)
+                    rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c);                  /* Receive Data */
+
+                u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO);                        /* Clear SI and send STOP */
+
+                break;
+
+            case UI2C_PROTSTS_STORIF_Msk:
+                UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk);     /* Clear STOP INT Flag */
+                u8Ctrl = UI2C_CTL_PTRG;                                     /* Clear SI */
+                u8Xfering = 0U;
+                break;
+
+            case UI2C_PROTSTS_ARBLOIF_Msk:                                  /* Arbitration Lost */
+            default:                                                        /* Unknow status */
+                u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO);                    /* Clear SI and send STOP */
+                break;
+        }
+
+        UI2C_SET_CONTROL_REG(ui2c, u8Ctrl);                                 /* Write controlbit to UI2C_PROTCTL register */
+    }
+
+    return u32rxLen;                                                        /* Return bytes length that have been received */
+}
+
+/**@}*/ /* end of group USCI_I2C_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group USCI_I2C_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_usci_spi.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_usci_spi.c
new file mode 100644
index 0000000000..0908e9cb4d
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_usci_spi.c
@@ -0,0 +1,635 @@
+/****************************************************************************//**
+ * @file     usci_spi.c
+ * @version  V3.00
+ * @brief    M2354 series USCI_SPI driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup USCI_SPI_Driver USCI_SPI Driver
+  @{
+*/
+
+
+/** @addtogroup USCI_SPI_EXPORTED_FUNCTIONS USCI_SPI Exported Functions
+  @{
+*/
+
+/**
+  * @brief  This function make USCI_SPI module be ready to transfer.
+  *         By default, the USCI_SPI transfer sequence is MSB first, the slave selection
+  *         signal is active low and the automatic slave select function is disabled. In
+  *         Slave mode, the u32BusClock must be NULL and the USCI_SPI clock
+  *         divider setting will be 0.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @param[in]  u32MasterSlave Decide the USCI_SPI module is operating in master mode or in slave mode. Valid values are:
+  *                    - \ref USPI_SLAVE
+  *                    - \ref USPI_MASTER
+  * @param[in]  u32SPIMode Decide the transfer timing. Valid values are:
+  *                    - \ref USPI_MODE_0
+  *                    - \ref USPI_MODE_1
+  *                    - \ref USPI_MODE_2
+  *                    - \ref USPI_MODE_3
+  * @param[in]  u32DataWidth The data width of a USCI_SPI transaction.
+  * @param[in]  u32BusClock The expected frequency of USCI_SPI bus clock in Hz.
+  * @return Actual frequency of USCI_SPI peripheral clock.
+  */
+uint32_t USPI_Open(USPI_T *uspi, uint32_t u32MasterSlave, uint32_t u32SPIMode,  uint32_t u32DataWidth, uint32_t u32BusClock)
+{
+    uint32_t u32ClkDiv = 0UL;
+    uint32_t u32Pclk;
+    uint32_t u32RetValue = 0UL;
+
+    if((uspi == USPI0) || (uspi == USPI0_NS))
+    {
+        u32Pclk = CLK_GetPCLK0Freq();
+    }
+    else
+    {
+        u32Pclk = CLK_GetPCLK1Freq();
+    }
+
+    if(u32BusClock != 0UL)
+    {
+        u32ClkDiv = (uint32_t)((((((u32Pclk / 2UL) * 10UL) / (u32BusClock)) + 5UL) / 10UL) - 1UL); /* Compute proper divider for USCI_SPI clock */
+    }
+
+    /* Enable USCI_SPI protocol */
+    uspi->CTL &= ~USPI_CTL_FUNMODE_Msk;
+    uspi->CTL = 1UL << USPI_CTL_FUNMODE_Pos;
+
+    /* Data format configuration */
+    if(u32DataWidth == 16UL)
+    {
+        u32DataWidth = 0UL;
+    }
+    uspi->LINECTL &= ~USPI_LINECTL_DWIDTH_Msk;
+    uspi->LINECTL |= (u32DataWidth << USPI_LINECTL_DWIDTH_Pos);
+
+    /* MSB data format */
+    uspi->LINECTL &= ~USPI_LINECTL_LSB_Msk;
+
+    /* Set slave selection signal active low */
+    if(u32MasterSlave == USPI_MASTER)
+    {
+        uspi->LINECTL |= USPI_LINECTL_CTLOINV_Msk;
+    }
+    else
+    {
+        uspi->CTLIN0 |= USPI_CTLIN0_ININV_Msk;
+    }
+
+    /* Set operating mode and transfer timing */
+    uspi->PROTCTL &= ~(USPI_PROTCTL_SCLKMODE_Msk | USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SLAVE_Msk);
+    uspi->PROTCTL |= (u32MasterSlave | u32SPIMode);
+
+    /* Set USCI_SPI bus clock */
+    uspi->BRGEN &= ~USPI_BRGEN_CLKDIV_Msk;
+    uspi->BRGEN |= (u32ClkDiv << USPI_BRGEN_CLKDIV_Pos);
+    uspi->PROTCTL |=  USPI_PROTCTL_PROTEN_Msk;
+
+    if(u32BusClock != 0UL)
+    {
+        u32RetValue = (u32Pclk / ((u32ClkDiv + 1UL) << 1UL));
+    }
+    else
+    {
+        u32RetValue = 0UL;
+    }
+
+    return u32RetValue;
+}
+
+/**
+  * @brief Disable USCI_SPI function mode.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return None
+  */
+void USPI_Close(USPI_T *uspi)
+{
+    uspi->CTL &= ~USPI_CTL_FUNMODE_Msk;
+}
+
+/**
+  * @brief Clear Rx buffer.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return None
+  */
+void USPI_ClearRxBuf(USPI_T *uspi)
+{
+    uspi->BUFCTL |= USPI_BUFCTL_RXCLR_Msk;
+}
+
+/**
+  * @brief Clear Tx buffer.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return None
+  */
+void USPI_ClearTxBuf(USPI_T *uspi)
+{
+    uspi->BUFCTL |= USPI_BUFCTL_TXCLR_Msk;
+}
+
+/**
+  * @brief Disable the automatic slave select function.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return None
+  */
+void USPI_DisableAutoSS(USPI_T *uspi)
+{
+    uspi->PROTCTL &= ~(USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SS_Msk);
+}
+
+/**
+  * @brief Enable the automatic slave select function. Only available in Master mode.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @param[in]  u32SSPinMask This parameter is not used.
+  * @param[in]  u32ActiveLevel The active level of slave select signal. Valid values are:
+  *                     - \ref USPI_SS_ACTIVE_HIGH
+  *                     - \ref USPI_SS_ACTIVE_LOW
+  * @return None
+  */
+void USPI_EnableAutoSS(USPI_T *uspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
+{
+    (void)u32SSPinMask;
+    uspi->LINECTL = (uspi->LINECTL & ~USPI_LINECTL_CTLOINV_Msk) | u32ActiveLevel;
+    uspi->PROTCTL |= USPI_PROTCTL_AUTOSS_Msk;
+}
+
+/**
+  * @brief Set the USCI_SPI bus clock. Only available in Master mode.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @param[in]  u32BusClock The expected frequency of USCI_SPI bus clock.
+  * @return Actual frequency of USCI_SPI peripheral clock.
+  */
+uint32_t USPI_SetBusClock(USPI_T *uspi, uint32_t u32BusClock)
+{
+    uint32_t u32ClkDiv;
+    uint32_t u32Pclk;
+
+    if((uspi == USPI0) || (uspi == USPI0_NS))
+    {
+        u32Pclk = CLK_GetPCLK0Freq();
+    }
+    else
+    {
+        u32Pclk = CLK_GetPCLK1Freq();
+    }
+
+    u32ClkDiv = (uint32_t)((((((u32Pclk / 2UL) * 10UL) / (u32BusClock)) + 5UL) / 10UL) - 1UL); /* Compute proper divider for USCI_SPI clock */
+
+    /* Set USCI_SPI bus clock */
+    uspi->BRGEN &= ~USPI_BRGEN_CLKDIV_Msk;
+    uspi->BRGEN |= (u32ClkDiv << USPI_BRGEN_CLKDIV_Pos);
+
+    return (u32Pclk / ((u32ClkDiv + 1UL) << 1UL));
+}
+
+/**
+  * @brief Get the actual frequency of USCI_SPI bus clock. Only available in Master mode.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return Actual USCI_SPI bus clock frequency.
+  */
+uint32_t USPI_GetBusClock(USPI_T *uspi)
+{
+    uint32_t u32ClkDiv, u32BusClk;
+
+    u32ClkDiv = (uspi->BRGEN & USPI_BRGEN_CLKDIV_Msk) >> USPI_BRGEN_CLKDIV_Pos;
+
+    if((uspi == USPI0) || (uspi == USPI0_NS))
+    {
+        u32BusClk = (CLK_GetPCLK0Freq() / ((u32ClkDiv + 1UL) << 1UL));
+    }
+    else
+    {
+        u32BusClk = (CLK_GetPCLK1Freq() / ((u32ClkDiv + 1UL) << 1UL));
+    }
+
+    return u32BusClk;
+}
+
+/**
+  * @brief Enable related interrupts specified by u32Mask parameter.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @param[in]  u32Mask The combination of all related interrupt enable bits.
+  *         Each bit corresponds to a interrupt bit.
+  *         This parameter decides which interrupts will be enabled. Valid values are:
+  *           - \ref USPI_SSINACT_INT_MASK
+  *           - \ref USPI_SSACT_INT_MASK
+  *           - \ref USPI_SLVTO_INT_MASK
+  *           - \ref USPI_SLVBE_INT_MASK
+  *           - \ref USPI_TXUDR_INT_MASK
+  *           - \ref USPI_RXOV_INT_MASK
+  *           - \ref USPI_TXST_INT_MASK
+  *           - \ref USPI_TXEND_INT_MASK
+  *           - \ref USPI_RXST_INT_MASK
+  *           - \ref USPI_RXEND_INT_MASK
+  * @return None
+  */
+void USPI_EnableInt(USPI_T *uspi, uint32_t u32Mask)
+{
+    /* Enable slave selection signal inactive interrupt flag */
+    if((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK)
+    {
+        uspi->PROTIEN |= USPI_PROTIEN_SSINAIEN_Msk;
+    }
+
+    /* Enable slave selection signal active interrupt flag */
+    if((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK)
+    {
+        uspi->PROTIEN |= USPI_PROTIEN_SSACTIEN_Msk;
+    }
+
+    /* Enable slave time-out interrupt flag */
+    if((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK)
+    {
+        uspi->PROTIEN |= USPI_PROTIEN_SLVTOIEN_Msk;
+    }
+
+    /* Enable slave bit count error interrupt flag */
+    if((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK)
+    {
+        uspi->PROTIEN |= USPI_PROTIEN_SLVBEIEN_Msk;
+    }
+
+    /* Enable TX under run interrupt flag */
+    if((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK)
+    {
+        uspi->BUFCTL |= USPI_BUFCTL_TXUDRIEN_Msk;
+    }
+
+    /* Enable RX overrun interrupt flag */
+    if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK)
+    {
+        uspi->BUFCTL |= USPI_BUFCTL_RXOVIEN_Msk;
+    }
+
+    /* Enable TX start interrupt flag */
+    if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK)
+    {
+        uspi->INTEN |= USPI_INTEN_TXSTIEN_Msk;
+    }
+
+    /* Enable TX end interrupt flag */
+    if((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK)
+    {
+        uspi->INTEN |= USPI_INTEN_TXENDIEN_Msk;
+    }
+
+    /* Enable RX start interrupt flag */
+    if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK)
+    {
+        uspi->INTEN |= USPI_INTEN_RXSTIEN_Msk;
+    }
+
+    /* Enable RX end interrupt flag */
+    if((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK)
+    {
+        uspi->INTEN |= USPI_INTEN_RXENDIEN_Msk;
+    }
+}
+
+/**
+  * @brief Disable related interrupts specified by u32Mask parameter.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @param[in]  u32Mask The combination of all related interrupt enable bits.
+  *         Each bit corresponds to a interrupt bit.
+  *         This parameter decides which interrupts will be disabled. Valid values are:
+  *           - \ref USPI_SSINACT_INT_MASK
+  *           - \ref USPI_SSACT_INT_MASK
+  *           - \ref USPI_SLVTO_INT_MASK
+  *           - \ref USPI_SLVBE_INT_MASK
+  *           - \ref USPI_TXUDR_INT_MASK
+  *           - \ref USPI_RXOV_INT_MASK
+  *           - \ref USPI_TXST_INT_MASK
+  *           - \ref USPI_TXEND_INT_MASK
+  *           - \ref USPI_RXST_INT_MASK
+  *           - \ref USPI_RXEND_INT_MASK
+  * @return None
+  */
+void USPI_DisableInt(USPI_T *uspi, uint32_t u32Mask)
+{
+    /* Disable slave selection signal inactive interrupt flag */
+    if((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK)
+    {
+        uspi->PROTIEN &= ~USPI_PROTIEN_SSINAIEN_Msk;
+    }
+
+    /* Disable slave selection signal active interrupt flag */
+    if((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK)
+    {
+        uspi->PROTIEN &= ~USPI_PROTIEN_SSACTIEN_Msk;
+    }
+
+    /* Disable slave time-out interrupt flag */
+    if((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK)
+    {
+        uspi->PROTIEN &= ~USPI_PROTIEN_SLVTOIEN_Msk;
+    }
+
+    /* Disable slave bit count error interrupt flag */
+    if((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK)
+    {
+        uspi->PROTIEN &= ~USPI_PROTIEN_SLVBEIEN_Msk;
+    }
+
+    /* Disable TX under run interrupt flag */
+    if((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK)
+    {
+        uspi->BUFCTL &= ~USPI_BUFCTL_TXUDRIEN_Msk;
+    }
+
+    /* Disable RX overrun interrupt flag */
+    if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK)
+    {
+        uspi->BUFCTL &= ~USPI_BUFCTL_RXOVIEN_Msk;
+    }
+
+    /* Disable TX start interrupt flag */
+    if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK)
+    {
+        uspi->INTEN &= ~USPI_INTEN_TXSTIEN_Msk;
+    }
+
+    /* Disable TX end interrupt flag */
+    if((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK)
+    {
+        uspi->INTEN &= ~USPI_INTEN_TXENDIEN_Msk;
+    }
+
+    /* Disable RX start interrupt flag */
+    if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK)
+    {
+        uspi->INTEN &= ~USPI_INTEN_RXSTIEN_Msk;
+    }
+
+    /* Disable RX end interrupt flag */
+    if((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK)
+    {
+        uspi->INTEN &= ~USPI_INTEN_RXENDIEN_Msk;
+    }
+}
+
+/**
+  * @brief  Get interrupt flag.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @param[in]  u32Mask The combination of all related interrupt sources.
+  *         Each bit corresponds to a interrupt source.
+  *         This parameter decides which interrupt flags will be read. It is combination of:
+  *           - \ref USPI_SSINACT_INT_MASK
+  *           - \ref USPI_SSACT_INT_MASK
+  *           - \ref USPI_SLVTO_INT_MASK
+  *           - \ref USPI_SLVBE_INT_MASK
+  *           - \ref USPI_TXUDR_INT_MASK
+  *           - \ref USPI_RXOV_INT_MASK
+  *           - \ref USPI_TXST_INT_MASK
+  *           - \ref USPI_TXEND_INT_MASK
+  *           - \ref USPI_RXST_INT_MASK
+  *           - \ref USPI_RXEND_INT_MASK
+  * @return Interrupt flags of selected sources.
+  */
+uint32_t USPI_GetIntFlag(USPI_T *uspi, uint32_t u32Mask)
+{
+    uint32_t u32ProtStatus, u32BufStatus;
+    uint32_t u32IntFlag = 0UL;
+
+    u32ProtStatus = uspi->PROTSTS;
+    u32BufStatus = uspi->BUFSTS;
+
+    /* Check slave selection signal inactive interrupt flag */
+    if((u32Mask & USPI_SSINACT_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_SSINAIF_Msk))
+    {
+        u32IntFlag |= USPI_SSINACT_INT_MASK;
+    }
+
+    /* Check slave selection signal active interrupt flag */
+    if((u32Mask & USPI_SSACT_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_SSACTIF_Msk))
+    {
+        u32IntFlag |= USPI_SSACT_INT_MASK;
+    }
+
+    /* Check slave time-out interrupt flag */
+    if((u32Mask & USPI_SLVTO_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_SLVTOIF_Msk))
+    {
+        u32IntFlag |= USPI_SLVTO_INT_MASK;
+    }
+
+    /* Check slave bit count error interrupt flag */
+    if((u32Mask & USPI_SLVBE_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_SLVBEIF_Msk))
+    {
+        u32IntFlag |= USPI_SLVBE_INT_MASK;
+    }
+
+    /* Check TX under run interrupt flag */
+    if((u32Mask & USPI_TXUDR_INT_MASK) && (u32BufStatus & USPI_BUFSTS_TXUDRIF_Msk))
+    {
+        u32IntFlag |= USPI_TXUDR_INT_MASK;
+    }
+
+    /* Check RX overrun interrupt flag */
+    if((u32Mask & USPI_RXOV_INT_MASK) && (u32BufStatus & USPI_BUFSTS_RXOVIF_Msk))
+    {
+        u32IntFlag |= USPI_RXOV_INT_MASK;
+    }
+
+    /* Check TX start interrupt flag */
+    if((u32Mask & USPI_TXST_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_TXSTIF_Msk))
+    {
+        u32IntFlag |= USPI_TXST_INT_MASK;
+    }
+
+    /* Check TX end interrupt flag */
+    if((u32Mask & USPI_TXEND_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_TXENDIF_Msk))
+    {
+        u32IntFlag |= USPI_TXEND_INT_MASK;
+    }
+
+    /* Check RX start interrupt flag */
+    if((u32Mask & USPI_RXST_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_RXSTIF_Msk))
+    {
+        u32IntFlag |= USPI_RXST_INT_MASK;
+    }
+
+    /* Check RX end interrupt flag */
+    if((u32Mask & USPI_RXEND_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_RXENDIF_Msk))
+    {
+        u32IntFlag |= USPI_RXEND_INT_MASK;
+    }
+
+    return u32IntFlag;
+}
+
+/**
+  * @brief  Clear interrupt flag.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @param[in]  u32Mask The combination of all related interrupt sources.
+  *         Each bit corresponds to a interrupt source.
+  *         This parameter decides which interrupt flags will be cleared. It could be the combination of:
+  *           - \ref USPI_SSINACT_INT_MASK
+  *           - \ref USPI_SSACT_INT_MASK
+  *           - \ref USPI_SLVTO_INT_MASK
+  *           - \ref USPI_SLVBE_INT_MASK
+  *           - \ref USPI_TXUDR_INT_MASK
+  *           - \ref USPI_RXOV_INT_MASK
+  *           - \ref USPI_TXST_INT_MASK
+  *           - \ref USPI_TXEND_INT_MASK
+  *           - \ref USPI_RXST_INT_MASK
+  *           - \ref USPI_RXEND_INT_MASK
+  * @return None
+  */
+void USPI_ClearIntFlag(USPI_T *uspi, uint32_t u32Mask)
+{
+    /* Clear slave selection signal inactive interrupt flag */
+    if(u32Mask & USPI_SSINACT_INT_MASK)
+    {
+        uspi->PROTSTS = USPI_PROTSTS_SSINAIF_Msk;
+    }
+
+    /* Clear slave selection signal active interrupt flag */
+    if(u32Mask & USPI_SSACT_INT_MASK)
+    {
+        uspi->PROTSTS = USPI_PROTSTS_SSACTIF_Msk;
+    }
+
+    /* Clear slave time-out interrupt flag */
+    if(u32Mask & USPI_SLVTO_INT_MASK)
+    {
+        uspi->PROTSTS = USPI_PROTSTS_SLVTOIF_Msk;
+    }
+
+    /* Clear slave bit count error interrupt flag */
+    if(u32Mask & USPI_SLVBE_INT_MASK)
+    {
+        uspi->PROTSTS = USPI_PROTSTS_SLVBEIF_Msk;
+    }
+
+    /* Clear TX under run interrupt flag */
+    if(u32Mask & USPI_TXUDR_INT_MASK)
+    {
+        uspi->BUFSTS = USPI_BUFSTS_TXUDRIF_Msk;
+    }
+
+    /* Clear RX overrun interrupt flag */
+    if(u32Mask & USPI_RXOV_INT_MASK)
+    {
+        uspi->BUFSTS = USPI_BUFSTS_RXOVIF_Msk;
+    }
+
+    /* Clear TX start interrupt flag */
+    if(u32Mask & USPI_TXST_INT_MASK)
+    {
+        uspi->PROTSTS = USPI_PROTSTS_TXSTIF_Msk;
+    }
+
+    /* Clear TX end interrupt flag */
+    if(u32Mask & USPI_TXEND_INT_MASK)
+    {
+        uspi->PROTSTS = USPI_PROTSTS_TXENDIF_Msk;
+    }
+
+    /* Clear RX start interrupt flag */
+    if(u32Mask & USPI_RXST_INT_MASK)
+    {
+        uspi->PROTSTS = USPI_PROTSTS_RXSTIF_Msk;
+    }
+
+    /* Clear RX end interrupt flag */
+    if(u32Mask & USPI_RXEND_INT_MASK)
+    {
+        uspi->PROTSTS = USPI_PROTSTS_RXENDIF_Msk;
+    }
+}
+
+/**
+  * @brief  Get USCI_SPI status.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @param[in]  u32Mask The combination of all related sources.
+  *         Each bit corresponds to a source.
+  *         This parameter decides which flags will be read. It is combination of:
+  *           - \ref USPI_BUSY_MASK
+  *           - \ref USPI_RX_EMPTY_MASK
+  *           - \ref USPI_RX_FULL_MASK
+  *           - \ref USPI_TX_EMPTY_MASK
+  *           - \ref USPI_TX_FULL_MASK
+  *           - \ref USPI_SSLINE_STS_MASK
+  * @return Flags of selected sources.
+  */
+uint32_t USPI_GetStatus(USPI_T *uspi, uint32_t u32Mask)
+{
+    uint32_t u32ProtStatus, u32BufStatus;
+    uint32_t u32Flag = 0UL;
+
+    u32ProtStatus = uspi->PROTSTS;
+    u32BufStatus = uspi->BUFSTS;
+
+    /* Check busy status */
+    if((u32Mask & USPI_BUSY_MASK) && (u32ProtStatus & USPI_PROTSTS_BUSY_Msk))
+    {
+        u32Flag |= USPI_BUSY_MASK;
+    }
+
+    /* Check RX empty flag */
+    if((u32Mask & USPI_RX_EMPTY_MASK) && (u32BufStatus & USPI_BUFSTS_RXEMPTY_Msk))
+    {
+        u32Flag |= USPI_RX_EMPTY_MASK;
+    }
+
+    /* Check RX full flag */
+    if((u32Mask & USPI_RX_FULL_MASK) && (u32BufStatus & USPI_BUFSTS_RXFULL_Msk))
+    {
+        u32Flag |= USPI_RX_FULL_MASK;
+    }
+
+    /* Check TX empty flag */
+    if((u32Mask & USPI_TX_EMPTY_MASK) && (u32BufStatus & USPI_BUFSTS_TXEMPTY_Msk))
+    {
+        u32Flag |= USPI_TX_EMPTY_MASK;
+    }
+
+    /* Check TX full flag */
+    if((u32Mask & USPI_TX_FULL_MASK) && (u32BufStatus & USPI_BUFSTS_TXFULL_Msk))
+    {
+        u32Flag |= USPI_TX_FULL_MASK;
+    }
+
+    /* Check USCI_SPI_SS line status */
+    if((u32Mask & USPI_SSLINE_STS_MASK) && (u32ProtStatus & USPI_PROTSTS_SSLINE_Msk))
+    {
+        u32Flag |= USPI_SSLINE_STS_MASK;
+    }
+
+    return u32Flag;
+}
+
+/**
+  * @brief  Enable USCI_SPI Wake-up Function.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return None
+  */
+void USPI_EnableWakeup(USPI_T *uspi)
+{
+    uspi->WKCTL |= USPI_WKCTL_WKEN_Msk;
+}
+
+/**
+  * @brief  Disable USCI_SPI Wake-up Function.
+  * @param[in]  uspi The pointer of the specified USCI_SPI module.
+  * @return None
+  */
+void USPI_DisableWakeup(USPI_T *uspi)
+{
+    uspi->WKCTL &= ~USPI_WKCTL_WKEN_Msk;
+}
+
+/**@}*/ /* end of group USCI_SPI_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group USCI_SPI_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_usci_uart.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_usci_uart.c
new file mode 100644
index 0000000000..f4c25910b4
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_usci_uart.c
@@ -0,0 +1,729 @@
+/**************************************************************************//**
+ * @file     usci_uart.c
+ * @version  V3.00
+ * @brief    M2354 series USCI UART (UUART) driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+#include 
+#include "NuMicro.h"
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup USCI_UART_Driver USCI_UART Driver
+  @{
+*/
+
+/** @addtogroup USCI_UART_EXPORTED_FUNCTIONS USCI_UART Exported Functions
+  @{
+*/
+
+/**
+ *    @brief        Clear USCI_UART specified interrupt flag
+ *
+ *    @param[in]    uuart   The pointer of the specified USCI_UART module.
+ *    @param[in]    u32Mask The combination of all related interrupt sources.
+ *                          Each bit corresponds to a interrupt source.
+ *                          This parameter decides which interrupt flags will be cleared. It could be the combination of:
+ *                          - \ref UUART_ABR_INT_MASK
+ *                          - \ref UUART_RLS_INT_MASK
+ *                          - \ref UUART_BUF_RXOV_INT_MASK
+ *                          - \ref UUART_TXST_INT_MASK
+ *                          - \ref UUART_TXEND_INT_MASK
+ *                          - \ref UUART_RXST_INT_MASK
+ *                          - \ref UUART_RXEND_INT_MASK
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to clear USCI_UART related interrupt flags specified by u32Mask parameter.
+ */
+
+void UUART_ClearIntFlag(UUART_T* uuart, uint32_t u32Mask)
+{
+
+    if(u32Mask & UUART_ABR_INT_MASK)   /* Clear Auto-baud Rate Interrupt */
+    {
+        uuart->PROTSTS = UUART_PROTSTS_ABRDETIF_Msk;
+    }
+
+    if(u32Mask & UUART_RLS_INT_MASK)   /* Clear Receive Line Status Interrupt */
+    {
+        uuart->PROTSTS = (UUART_PROTSTS_BREAK_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_PARITYERR_Msk);
+    }
+
+    if(u32Mask & UUART_BUF_RXOV_INT_MASK)   /* Clear Receive Buffer Over-run Error Interrupt */
+    {
+        uuart->BUFSTS = UUART_BUFSTS_RXOVIF_Msk;
+    }
+
+    if(u32Mask & UUART_TXST_INT_MASK)   /* Clear Transmit Start Interrupt */
+    {
+        uuart->PROTSTS = UUART_PROTSTS_TXSTIF_Msk;
+    }
+
+    if(u32Mask & UUART_TXEND_INT_MASK)   /* Clear Transmit End Interrupt */
+    {
+        uuart->PROTSTS = UUART_PROTSTS_TXENDIF_Msk;
+    }
+
+    if(u32Mask & UUART_RXST_INT_MASK)   /* Clear Receive Start Interrupt */
+    {
+        uuart->PROTSTS = UUART_PROTSTS_RXSTIF_Msk;
+    }
+
+    if(u32Mask & UUART_RXEND_INT_MASK)   /* Clear Receive End Interrupt */
+    {
+        uuart->PROTSTS = UUART_PROTSTS_RXENDIF_Msk;
+    }
+
+}
+
+
+/**
+ *    @brief        Get USCI_UART specified interrupt flag
+ *
+ *    @param[in]    uuart   The pointer of the specified USCI_UART module.
+ *    @param[in]    u32Mask The combination of all related interrupt sources.
+ *                          Each bit corresponds to a interrupt source.
+ *                          This parameter decides which interrupt flags will be read. It is combination of:
+ *                          - \ref UUART_ABR_INT_MASK
+ *                          - \ref UUART_RLS_INT_MASK
+ *                          - \ref UUART_BUF_RXOV_INT_MASK
+ *                          - \ref UUART_TXST_INT_MASK
+ *                          - \ref UUART_TXEND_INT_MASK
+ *                          - \ref UUART_RXST_INT_MASK
+ *                          - \ref UUART_RXEND_INT_MASK
+ *
+ *    @return       Interrupt flags of selected sources.
+ *
+ *    @details      The function is used to get USCI_UART related interrupt flags specified by u32Mask parameter.
+ */
+
+uint32_t UUART_GetIntFlag(UUART_T* uuart, uint32_t u32Mask)
+{
+    uint32_t u32IntFlag = 0ul;
+    uint32_t u32Tmp1, u32Tmp2;
+
+    /* Check Auto-baud Rate Interrupt Flag */
+    u32Tmp1 = (u32Mask & UUART_ABR_INT_MASK);
+    u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_ABRDETIF_Msk);
+    if(u32Tmp1 && u32Tmp2)
+    {
+        u32IntFlag |= UUART_ABR_INT_MASK;
+    }
+
+    /* Check Receive Line Status Interrupt Flag */
+    u32Tmp1 = (u32Mask & UUART_RLS_INT_MASK);
+    u32Tmp2 = (uuart->PROTSTS & (UUART_PROTSTS_BREAK_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_PARITYERR_Msk));
+    if(u32Tmp1 && u32Tmp2)
+    {
+        u32IntFlag |= UUART_RLS_INT_MASK;
+    }
+
+    /* Check Receive Buffer Over-run Error Interrupt Flag */
+    u32Tmp1 = (u32Mask & UUART_BUF_RXOV_INT_MASK);
+    u32Tmp2 = (uuart->BUFSTS & UUART_BUFSTS_RXOVIF_Msk);
+    if(u32Tmp1 && u32Tmp2)
+    {
+        u32IntFlag |= UUART_BUF_RXOV_INT_MASK;
+    }
+
+    /* Check Transmit Start Interrupt Flag */
+    u32Tmp1 = (u32Mask & UUART_TXST_INT_MASK);
+    u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_TXSTIF_Msk);
+    if(u32Tmp1 && u32Tmp2)
+    {
+        u32IntFlag |= UUART_TXST_INT_MASK;
+    }
+
+    /* Check Transmit End Interrupt Flag */
+    u32Tmp1 = (u32Mask & UUART_TXEND_INT_MASK);
+    u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_TXENDIF_Msk);
+    if(u32Tmp1 && u32Tmp2)
+    {
+        u32IntFlag |= UUART_TXEND_INT_MASK;
+    }
+
+    /* Check Receive Start Interrupt Flag */
+    u32Tmp1 = (u32Mask & UUART_RXST_INT_MASK);
+    u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_RXSTIF_Msk);
+    if(u32Tmp1 && u32Tmp2)
+    {
+        u32IntFlag |= UUART_RXST_INT_MASK;
+    }
+
+    /* Check Receive End Interrupt Flag */
+    u32Tmp1 = (u32Mask & UUART_RXEND_INT_MASK);
+    u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_RXENDIF_Msk);
+    if(u32Tmp1 && u32Tmp2)
+    {
+        u32IntFlag |= UUART_RXEND_INT_MASK;
+    }
+
+    return u32IntFlag;
+}
+
+
+/**
+ *  @brief      Disable USCI_UART function mode
+ *
+ *  @param[in]  uuart The pointer of the specified USCI_UART module.
+ *
+ *  @return     None
+ *
+ *  @details    The function is used to disable USCI_UART function mode.
+ */
+void UUART_Close(UUART_T* uuart)
+{
+    uuart->CTL = 0UL;
+}
+
+
+/**
+ *    @brief        Disable interrupt function.
+ *
+ *    @param[in]    uuart   The pointer of the specified USCI_UART module.
+ *    @param[in]    u32Mask The combination of all related interrupt enable bits.
+ *                          Each bit corresponds to a interrupt enable bit.
+ *                          This parameter decides which interrupts will be disabled. It is combination of:
+ *                          - \ref UUART_ABR_INT_MASK
+ *                          - \ref UUART_RLS_INT_MASK
+ *                          - \ref UUART_BUF_RXOV_INT_MASK
+ *                          - \ref UUART_TXST_INT_MASK
+ *                          - \ref UUART_TXEND_INT_MASK
+ *                          - \ref UUART_RXST_INT_MASK
+ *                          - \ref UUART_RXEND_INT_MASK
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to disabled USCI_UART related interrupts specified by u32Mask parameter.
+ */
+void UUART_DisableInt(UUART_T* uuart, uint32_t u32Mask)
+{
+
+    /* Disable Auto-baud rate interrupt flag */
+    if((u32Mask & UUART_ABR_INT_MASK) == UUART_ABR_INT_MASK)
+    {
+        uuart->PROTIEN &= ~UUART_PROTIEN_ABRIEN_Msk;
+    }
+
+    /* Disable receive line status interrupt flag */
+    if((u32Mask & UUART_RLS_INT_MASK) == UUART_RLS_INT_MASK)
+    {
+        uuart->PROTIEN &= ~UUART_PROTIEN_RLSIEN_Msk;
+    }
+
+    /* Disable RX overrun interrupt flag */
+    if((u32Mask & UUART_BUF_RXOV_INT_MASK) == UUART_BUF_RXOV_INT_MASK)
+    {
+        uuart->BUFCTL &= ~UUART_BUFCTL_RXOVIEN_Msk;
+    }
+
+    /* Disable TX start interrupt flag */
+    if((u32Mask & UUART_TXST_INT_MASK) == UUART_TXST_INT_MASK)
+    {
+        uuart->INTEN &= ~UUART_INTEN_TXSTIEN_Msk;
+    }
+
+    /* Disable TX end interrupt flag */
+    if((u32Mask & UUART_TXEND_INT_MASK) == UUART_TXEND_INT_MASK)
+    {
+        uuart->INTEN &= ~UUART_INTEN_TXENDIEN_Msk;
+    }
+
+    /* Disable RX start interrupt flag */
+    if((u32Mask & UUART_RXST_INT_MASK) == UUART_RXST_INT_MASK)
+    {
+        uuart->INTEN &= ~UUART_INTEN_RXSTIEN_Msk;
+    }
+
+    /* Disable RX end interrupt flag */
+    if((u32Mask & UUART_RXEND_INT_MASK) == UUART_RXEND_INT_MASK)
+    {
+        uuart->INTEN &= ~UUART_INTEN_RXENDIEN_Msk;
+    }
+}
+
+
+/**
+ *    @brief        Enable interrupt function.
+ *
+ *    @param[in]    uuart       The pointer of the specified USCI_UART module.
+ *    @param[in]    u32Mask     The combination of all related interrupt enable bits.
+ *                              Each bit corresponds to a interrupt enable bit.
+ *                              This parameter decides which interrupts will be enabled. It is combination of:
+ *                              - \ref UUART_ABR_INT_MASK
+ *                              - \ref UUART_RLS_INT_MASK
+ *                              - \ref UUART_BUF_RXOV_INT_MASK
+ *                              - \ref UUART_TXST_INT_MASK
+ *                              - \ref UUART_TXEND_INT_MASK
+ *                              - \ref UUART_RXST_INT_MASK
+ *                              - \ref UUART_RXEND_INT_MASK
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to enable USCI_UART related interrupts specified by u32Mask parameter..
+ */
+void UUART_EnableInt(UUART_T*  uuart, uint32_t u32Mask)
+{
+    /* Enable Auto-baud rate interrupt flag */
+    if((u32Mask & UUART_ABR_INT_MASK) == UUART_ABR_INT_MASK)
+    {
+        uuart->PROTIEN |= UUART_PROTIEN_ABRIEN_Msk;
+    }
+
+    /* Enable receive line status interrupt flag */
+    if((u32Mask & UUART_RLS_INT_MASK) == UUART_RLS_INT_MASK)
+    {
+        uuart->PROTIEN |= UUART_PROTIEN_RLSIEN_Msk;
+    }
+
+    /* Enable RX overrun interrupt flag */
+    if((u32Mask & UUART_BUF_RXOV_INT_MASK) == UUART_BUF_RXOV_INT_MASK)
+    {
+        uuart->BUFCTL |= UUART_BUFCTL_RXOVIEN_Msk;
+    }
+
+    /* Enable TX start interrupt flag */
+    if((u32Mask & UUART_TXST_INT_MASK) == UUART_TXST_INT_MASK)
+    {
+        uuart->INTEN |= UUART_INTEN_TXSTIEN_Msk;
+    }
+
+    /* Enable TX end interrupt flag */
+    if((u32Mask & UUART_TXEND_INT_MASK) == UUART_TXEND_INT_MASK)
+    {
+        uuart->INTEN |= UUART_INTEN_TXENDIEN_Msk;
+    }
+
+    /* Enable RX start interrupt flag */
+    if((u32Mask & UUART_RXST_INT_MASK) == UUART_RXST_INT_MASK)
+    {
+        uuart->INTEN |= UUART_INTEN_RXSTIEN_Msk;
+    }
+
+    /* Enable RX end interrupt flag */
+    if((u32Mask & UUART_RXEND_INT_MASK) == UUART_RXEND_INT_MASK)
+    {
+        uuart->INTEN |= UUART_INTEN_RXENDIEN_Msk;
+    }
+}
+
+
+/**
+ *    @brief        Open and set USCI_UART function
+ *
+ *    @param[in]    uuart           The pointer of the specified USCI_UART module.
+ *    @param[in]    u32baudrate     The baud rate of USCI_UART module.
+ *
+ *    @return       Real baud rate of USCI_UART module.
+ *
+ *    @details      This function use to enable USCI_UART function and set baud-rate.
+ */
+uint32_t UUART_Open(UUART_T* uuart, uint32_t u32baudrate)
+{
+    uint32_t u32PCLKFreq, u32PDSCnt, u32DSCnt, u32ClkDiv;
+    uint32_t u32Tmp, u32Tmp2, u32Min, u32MinClkDiv, u32MinDSCnt;
+    uint32_t u32Div;
+
+    /* Get PCLK frequency */
+    if((uuart == UUART0) || (uuart == UUART0_NS))
+    {
+        u32PCLKFreq = CLK_GetPCLK0Freq();
+    }
+    else
+    {
+        u32PCLKFreq = CLK_GetPCLK1Freq();
+    }
+
+    /* Calculate baud rate divider */
+    u32Div = u32PCLKFreq / u32baudrate;
+    u32Tmp = (u32PCLKFreq / u32Div) - u32baudrate;
+    u32Tmp2 = u32baudrate - (u32PCLKFreq / (u32Div + 1ul));
+
+    if(u32Tmp >= u32Tmp2) u32Div = u32Div + 1ul;
+
+    if(u32Div >= 65536ul)
+    {
+
+        /* Set the smallest baud rate that USCI_UART can generate */
+        u32PDSCnt = 0x4ul;
+        u32MinDSCnt = 0x10ul;
+        u32MinClkDiv = 0x400ul;
+
+    }
+    else
+    {
+
+        u32Tmp = 0x400ul * 0x10ul;
+        for(u32PDSCnt = 1ul; u32PDSCnt <= 0x04ul; u32PDSCnt++)
+        {
+            if(u32Div <= (u32Tmp * u32PDSCnt)) break;
+        }
+
+        if(u32PDSCnt > 0x4ul) u32PDSCnt = 0x4ul;
+
+        u32Div = u32Div / u32PDSCnt;
+
+        /* Find best solution */
+        u32Min = (uint32_t) - 1;
+        u32MinDSCnt = 0ul;
+        u32MinClkDiv = 0ul;
+        u32Tmp = 0ul;
+
+        for(u32DSCnt = 6ul; u32DSCnt <= 0x10ul; u32DSCnt++)   /* DSCNT could be 0x5~0xF */
+        {
+
+            u32ClkDiv = u32Div / u32DSCnt;
+
+            if(u32ClkDiv > 0x400ul)
+            {
+                u32ClkDiv = 0x400ul;
+                u32Tmp = u32Div - (u32ClkDiv * u32DSCnt);
+                u32Tmp2 = u32Tmp + 1ul;
+            }
+            else
+            {
+                u32Tmp = u32Div - (u32ClkDiv * u32DSCnt);
+                u32Tmp2 = ((u32ClkDiv + 1ul) * u32DSCnt) - u32Div;
+            }
+
+            if(u32Tmp >= u32Tmp2)
+            {
+                u32ClkDiv = u32ClkDiv + 1ul;
+            }
+            else u32Tmp2 = u32Tmp;
+
+            if(u32Tmp2 < u32Min)
+            {
+                u32Min = u32Tmp2;
+                u32MinDSCnt = u32DSCnt;
+                u32MinClkDiv = u32ClkDiv;
+
+                /* Break when get good results */
+                if(u32Min == 0ul)
+                {
+                    break;
+                }
+            }
+        }
+
+    }
+
+    /* Enable USCI_UART protocol */
+    uuart->CTL &= ~UUART_CTL_FUNMODE_Msk;
+    uuart->CTL = 2ul << UUART_CTL_FUNMODE_Pos;
+
+    /* Set USCI_UART line configuration */
+    uuart->LINECTL = UUART_WORD_LEN_8 | UUART_LINECTL_LSB_Msk;
+    uuart->DATIN0 = (2ul << UUART_DATIN0_EDGEDET_Pos);  /* Set falling edge detection */
+
+    /* Set USCI_UART baud rate */
+    uuart->BRGEN = ((u32MinClkDiv - 1ul) << UUART_BRGEN_CLKDIV_Pos) |
+                   ((u32MinDSCnt - 1ul) << UUART_BRGEN_DSCNT_Pos) |
+                   ((u32PDSCnt - 1ul) << UUART_BRGEN_PDSCNT_Pos);
+
+    uuart->PROTCTL |= UUART_PROTCTL_PROTEN_Msk;
+
+    return (u32PCLKFreq / u32PDSCnt / u32MinDSCnt / u32MinClkDiv);
+}
+
+
+/**
+ *    @brief        Read USCI_UART data
+ *
+ *    @param[in]    uuart           The pointer of the specified USCI_UART module.
+ *    @param[in]    pu8RxBuf        The buffer to receive the data of receive buffer.
+ *    @param[in]    u32ReadBytes    The read bytes number of data.
+ *
+ *    @return       Receive byte count
+ *
+ *    @details      The function is used to read Rx data from RX buffer and the data will be stored in pu8RxBuf.
+ */
+uint32_t UUART_Read(UUART_T* uuart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes)
+{
+    uint32_t  u32Count, u32delayno;
+
+    for(u32Count = 0ul; u32Count < u32ReadBytes; u32Count++)
+    {
+        u32delayno = 0ul;
+
+        while(uuart->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk)   /* Check RX empty => failed */
+        {
+            u32delayno++;
+            if(u32delayno >= 0x40000000ul)
+            {
+                break;
+            }
+        }
+
+        if(u32delayno >= 0x40000000ul)
+        {
+            break;
+        }
+
+        pu8RxBuf[u32Count] = (uint8_t)uuart->RXDAT;    /* Get Data from USCI RX  */
+    }
+
+    return u32Count;
+
+}
+
+
+/**
+ *    @brief        Set USCI_UART line configuration
+ *
+ *    @param[in]    uuart           The pointer of the specified USCI_UART module.
+ *    @param[in]    u32baudrate     The register value of baud rate of USCI_UART module.
+ *                                  If u32baudrate = 0, USCI_UART baud rate will not change.
+ *    @param[in]    u32data_width   The data length of USCI_UART module.
+ *                                  - \ref UUART_WORD_LEN_6
+ *                                  - \ref UUART_WORD_LEN_7
+ *                                  - \ref UUART_WORD_LEN_8
+ *                                  - \ref UUART_WORD_LEN_9
+ *    @param[in]    u32parity       The parity setting (none/odd/even) of USCI_UART module.
+ *                                  - \ref UUART_PARITY_NONE
+ *                                  - \ref UUART_PARITY_ODD
+ *                                  - \ref UUART_PARITY_EVEN
+ *    @param[in]    u32stop_bits    The stop bit length (1/2 bit) of USCI_UART module.
+ *                                  - \ref UUART_STOP_BIT_1
+ *                                  - \ref UUART_STOP_BIT_2
+ *
+ *    @return       Real baud rate of USCI_UART module.
+ *
+ *    @details      This function use to config USCI_UART line setting.
+ */
+uint32_t UUART_SetLine_Config(UUART_T* uuart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits)
+{
+    uint32_t u32PCLKFreq, u32PDSCnt, u32DSCnt, u32ClkDiv;
+    uint32_t u32Tmp, u32Tmp2, u32Min, u32MinClkDiv, u32MinDSCnt;
+    uint32_t u32Div;
+
+    /* Get PCLK frequency */
+    if((uuart == UUART0) || (uuart == UUART0_NS))
+    {
+        u32PCLKFreq = CLK_GetPCLK0Freq();
+    }
+    else     /* UUART1 */
+    {
+        u32PCLKFreq = CLK_GetPCLK1Freq();
+    }
+
+    if(u32baudrate != 0ul)
+    {
+
+        /* Calculate baud rate divider */
+        u32Div = u32PCLKFreq / u32baudrate;
+        u32Tmp = (u32PCLKFreq / u32Div) - u32baudrate;
+        u32Tmp2 = u32baudrate - (u32PCLKFreq / (u32Div + 1ul));
+
+        if(u32Tmp >= u32Tmp2) u32Div = u32Div + 1ul;
+
+        if(u32Div >= 65536ul)
+        {
+
+            /* Set the smallest baud rate that USCI_UART can generate */
+            u32PDSCnt = 0x4ul;
+            u32MinDSCnt = 0x10ul;
+            u32MinClkDiv = 0x400ul;
+
+        }
+        else
+        {
+
+            u32Tmp = 0x400ul * 0x10ul;
+            for(u32PDSCnt = 1ul; u32PDSCnt <= 0x04ul; u32PDSCnt++)
+            {
+                if(u32Div <= (u32Tmp * u32PDSCnt)) break;
+            }
+
+            if(u32PDSCnt > 0x4ul) u32PDSCnt = 0x4ul;
+
+            u32Div = u32Div / u32PDSCnt;
+
+            /* Find best solution */
+            u32Min = (uint32_t) - 1;
+            u32MinDSCnt = 0ul;
+            u32MinClkDiv = 0ul;
+
+            for(u32DSCnt = 6ul; u32DSCnt <= 0x10ul; u32DSCnt++)   /* DSCNT could be 0x5~0xF */
+            {
+                u32ClkDiv = u32Div / u32DSCnt;
+
+                if(u32ClkDiv > 0x400ul)
+                {
+                    u32ClkDiv = 0x400ul;
+                    u32Tmp = u32Div - (u32ClkDiv * u32DSCnt);
+                    u32Tmp2 = u32Tmp + 1ul;
+                }
+                else
+                {
+                    u32Tmp = u32Div - (u32ClkDiv * u32DSCnt);
+                    u32Tmp2 = ((u32ClkDiv + 1ul) * u32DSCnt) - u32Div;
+                }
+
+                if(u32Tmp >= u32Tmp2)
+                {
+                    u32ClkDiv = u32ClkDiv + 1ul;
+                }
+                else u32Tmp2 = u32Tmp;
+
+                if(u32Tmp2 < u32Min)
+                {
+                    u32Min = u32Tmp2;
+                    u32MinDSCnt = u32DSCnt;
+                    u32MinClkDiv = u32ClkDiv;
+
+                    /* Break when get good results */
+                    if(u32Min == 0ul)
+                    {
+                        break;
+                    }
+                }
+            }
+
+        }
+
+        /* Set USCI_UART baud rate */
+        uuart->BRGEN = ((u32MinClkDiv - 1ul) << UUART_BRGEN_CLKDIV_Pos) |
+                       ((u32MinDSCnt - 1ul) << UUART_BRGEN_DSCNT_Pos) |
+                       ((u32PDSCnt - 1ul) << UUART_BRGEN_PDSCNT_Pos);
+    }
+    else
+    {
+        u32PDSCnt = ((uuart->BRGEN & UUART_BRGEN_PDSCNT_Msk) >> UUART_BRGEN_PDSCNT_Pos) + 1ul;
+        u32MinDSCnt = ((uuart->BRGEN & UUART_BRGEN_DSCNT_Msk) >> UUART_BRGEN_DSCNT_Pos) + 1ul;
+        u32MinClkDiv = ((uuart->BRGEN & UUART_BRGEN_CLKDIV_Msk) >> UUART_BRGEN_CLKDIV_Pos) + 1ul;
+    }
+
+    /* Set USCI_UART line configuration */
+    uuart->LINECTL = (uuart->LINECTL & ~UUART_LINECTL_DWIDTH_Msk) | u32data_width;
+    uuart->PROTCTL = (uuart->PROTCTL & ~(UUART_PROTCTL_STICKEN_Msk | UUART_PROTCTL_EVENPARITY_Msk |
+                                         UUART_PROTCTL_PARITYEN_Msk)) | u32parity;
+    uuart->PROTCTL = (uuart->PROTCTL & ~UUART_PROTCTL_STOPB_Msk) | u32stop_bits;
+
+    return (u32PCLKFreq / u32PDSCnt / u32MinDSCnt / u32MinClkDiv);
+}
+
+
+/**
+ *    @brief        Write USCI_UART data
+ *
+ *    @param[in]    uuart           The pointer of the specified USCI_UART module.
+ *    @param[in]    pu8TxBuf        The buffer to send the data to USCI transmission buffer.
+ *    @param[out]   u32WriteBytes   The byte number of data.
+ *
+ *    @return       Transfer byte count
+ *
+ *    @details      The function is to write data into TX buffer to transmit data by USCI_UART.
+ */
+uint32_t UUART_Write(UUART_T* uuart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes)
+{
+    uint32_t  u32Count, u32delayno;
+
+    for(u32Count = 0ul; u32Count != u32WriteBytes; u32Count++)
+    {
+        u32delayno = 0ul;
+        while((uuart->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) == 0ul)   /* Wait Tx empty */
+        {
+            u32delayno++;
+            if(u32delayno >= 0x40000000ul)
+            {
+                break;
+            }
+        }
+
+        if(u32delayno >= 0x40000000ul)
+        {
+            break;
+        }
+
+        uuart->TXDAT = (uint8_t)pu8TxBuf[u32Count];    /* Send USCI_UART Data to buffer */
+    }
+
+    return u32Count;
+}
+
+
+/**
+ *    @brief        Enable USCI_UART Wake-up Function
+ *
+ *    @param[in]    uuart           The pointer of the specified USCI_UART module.
+ *    @param[in]    u32WakeupMode   The wakeup mode of USCI_UART module.
+*                                   - \ref UUART_PROTCTL_DATWKEN_Msk    : Data wake-up Mode
+*                                   - \ref UUART_PROTCTL_CTSWKEN_Msk    : nCTS wake-up Mode
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to enable Wake-up function of USCI_UART.
+ */
+void UUART_EnableWakeup(UUART_T* uuart, uint32_t u32WakeupMode)
+{
+    uuart->PROTCTL |= u32WakeupMode;
+    uuart->WKCTL |= UUART_WKCTL_WKEN_Msk;
+}
+
+
+/**
+ *    @brief        Disable USCI_UART Wake-up Function
+ *
+ *    @param[in]    uuart   The pointer of the specified USCI_UART module.
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to disable Wake-up function of USCI_UART.
+ */
+void UUART_DisableWakeup(UUART_T* uuart)
+{
+    uuart->PROTCTL &= ~(UUART_PROTCTL_DATWKEN_Msk | UUART_PROTCTL_CTSWKEN_Msk);
+    uuart->WKCTL &= ~UUART_WKCTL_WKEN_Msk;
+}
+
+/**
+ *    @brief        Enable USCI_UART auto flow control
+ *
+ *    @param[in]    uuart   The pointer of the specified USCI_UART module.
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to enable USCI_UART auto flow control.
+ */
+void UUART_EnableFlowCtrl(UUART_T* uuart)
+{
+    /* Set RTS signal is low level active */
+    uuart->LINECTL &= ~UUART_LINECTL_CTLOINV_Msk;
+
+    /* Set CTS signal is low level active */
+    uuart->CTLIN0 &= ~UUART_CTLIN0_ININV_Msk;
+
+    /* Enable CTS and RTS auto flow control function */
+    uuart->PROTCTL |= UUART_PROTCTL_RTSAUTOEN_Msk | UUART_PROTCTL_CTSAUTOEN_Msk;
+}
+
+/**
+ *    @brief        Disable USCI_UART auto flow control
+ *
+ *    @param[in]    uuart    The pointer of the specified USCI_UART module.
+ *
+ *    @return       None
+ *
+ *    @details      The function is used to disable USCI_UART auto flow control.
+ */
+void UUART_DisableFlowCtrl(UUART_T* uuart)
+{
+    /* Disable CTS and RTS auto flow control function */
+    uuart->PROTCTL &= ~(UUART_PROTCTL_RTSAUTOEN_Msk | UUART_PROTCTL_CTSAUTOEN_Msk);
+}
+
+
+
+
+/**@}*/ /* end of group USCI_UART_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group USCI_UART_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_wdt.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_wdt.c
new file mode 100644
index 0000000000..6faa070196
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_wdt.c
@@ -0,0 +1,70 @@
+/**************************************************************************//**
+ * @file     wdt.c
+ * @version  V3.00
+ * @brief    Watchdog Timer(WDT) driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup WDT_Driver WDT Driver
+  @{
+*/
+
+/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Initialize WDT and start counting
+  *
+  * @param[in]  u32TimeoutInterval  Time-out interval period of WDT module. Valid values are:
+  *                                 - \ref WDT_TIMEOUT_2POW4
+  *                                 - \ref WDT_TIMEOUT_2POW6
+  *                                 - \ref WDT_TIMEOUT_2POW8
+  *                                 - \ref WDT_TIMEOUT_2POW10
+  *                                 - \ref WDT_TIMEOUT_2POW12
+  *                                 - \ref WDT_TIMEOUT_2POW14
+  *                                 - \ref WDT_TIMEOUT_2POW16
+  *                                 - \ref WDT_TIMEOUT_2POW18
+  *                                 - \ref WDT_TIMEOUT_2POW20
+  * @param[in]  u32ResetDelay       Configure WDT time-out reset delay period. Valid values are:
+  *                                 - \ref WDT_RESET_DELAY_1026CLK
+  *                                 - \ref WDT_RESET_DELAY_130CLK
+  *                                 - \ref WDT_RESET_DELAY_18CLK
+  *                                 - \ref WDT_RESET_DELAY_3CLK
+  * @param[in]  u32EnableReset      Enable WDT time-out reset system function. Valid values are TRUE and FALSE.
+  * @param[in]  u32EnableWakeup     Enable WDT time-out wake-up system function. Valid values are TRUE and FALSE.
+  *
+  * @return     None
+  *
+  * @details    This function makes WDT module start counting with different time-out interval, reset delay period and choose to \n
+  *             enable or disable WDT time-out reset system or wake-up system.
+  * @note       Please make sure that Register Write-Protection Function has been disabled before using this function.
+  */
+void WDT_Open(uint32_t u32TimeoutInterval,
+              uint32_t u32ResetDelay,
+              uint32_t u32EnableReset,
+              uint32_t u32EnableWakeup)
+{
+    WDT->ALTCTL = u32ResetDelay;
+
+    WDT->CTL = u32TimeoutInterval | WDT_CTL_WDTEN_Msk |
+               (u32EnableReset << WDT_CTL_RSTEN_Pos) |
+               (u32EnableWakeup << WDT_CTL_WKEN_Pos);
+
+    while((WDT->CTL & WDT_CTL_SYNC_Msk) == WDT_CTL_SYNC_Msk) {} /* Wait enable WDTEN bit completed, it needs 2 * WDT_CLK. */
+}
+
+/**@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group WDT_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
diff --git a/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_wwdt.c b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_wwdt.c
new file mode 100644
index 0000000000..cdd9c77447
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/StdDriver/src/nu_wwdt.c
@@ -0,0 +1,67 @@
+/**************************************************************************//**
+ * @file     wwdt.c
+ * @version  V3.00
+ * @brief    Window Watchdog Timer(WWDT) driver source file
+ *
+ * @copyright SPDX-License-Identifier: Apache-2.0
+ * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+#include "NuMicro.h"
+
+
+/** @addtogroup Standard_Driver Standard Driver
+  @{
+*/
+
+/** @addtogroup WWDT_Driver WWDT Driver
+  @{
+*/
+
+/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
+  @{
+*/
+
+/**
+  * @brief      Open WWDT and start counting
+  *
+  * @param[in]  u32PreScale     Pre-scale setting of WWDT counter. Valid values are:
+  *                             - \ref WWDT_PRESCALER_1
+  *                             - \ref WWDT_PRESCALER_2
+  *                             - \ref WWDT_PRESCALER_4
+  *                             - \ref WWDT_PRESCALER_8
+  *                             - \ref WWDT_PRESCALER_16
+  *                             - \ref WWDT_PRESCALER_32
+  *                             - \ref WWDT_PRESCALER_64
+  *                             - \ref WWDT_PRESCALER_128
+  *                             - \ref WWDT_PRESCALER_192
+  *                             - \ref WWDT_PRESCALER_256
+  *                             - \ref WWDT_PRESCALER_384
+  *                             - \ref WWDT_PRESCALER_512
+  *                             - \ref WWDT_PRESCALER_768
+  *                             - \ref WWDT_PRESCALER_1024
+  *                             - \ref WWDT_PRESCALER_1536
+  *                             - \ref WWDT_PRESCALER_2048
+  * @param[in]  u32CmpValue     Setting the window compared value. Valid values are between 0x0 to 0x3F.
+  * @param[in]  u32EnableInt    Enable WWDT time-out interrupt function. Valid values are TRUE and FALSE.
+  *
+  * @return     None
+  *
+  * @details    This function makes WWDT module start counting with different counter period by pre-scale setting and compared window value.
+  * @note       Application can call this function only once after boot up.
+  */
+void WWDT_Open(uint32_t u32PreScale,
+               uint32_t u32CmpValue,
+               uint32_t u32EnableInt)
+{
+    WWDT->CTL = u32PreScale |
+                (u32CmpValue << WWDT_CTL_CMPDAT_Pos) |
+                ((u32EnableInt == (uint32_t)TRUE) ? WWDT_CTL_INTEN_Msk : 0UL) |
+                WWDT_CTL_WWDTEN_Msk;
+}
+
+/**@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */
+
+/**@}*/ /* end of group WWDT_Driver */
+
+/**@}*/ /* end of group Standard_Driver */
+
diff --git a/bsp/nuvoton/libraries/m2354/USBHostLib/SConscript b/bsp/nuvoton/libraries/m2354/USBHostLib/SConscript
new file mode 100644
index 0000000000..d4902362e1
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/USBHostLib/SConscript
@@ -0,0 +1,12 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd = GetCurrentDir()
+group = []
+if GetDepend('BSP_USING_USBH'):
+	src = Glob('*src/*.c') + Glob('src/*.cpp')
+	CPPPATH = [cwd + '/inc']
+	group = DefineGroup('m2354_usbhostlib', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/nuvoton/libraries/m2354/USBHostLib/inc/config.h b/bsp/nuvoton/libraries/m2354/USBHostLib/inc/config.h
new file mode 100644
index 0000000000..46a876e17b
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/USBHostLib/inc/config.h
@@ -0,0 +1,96 @@
+/**************************************************************************//**
+ * @file     config.h
+ * @version  V1.00
+ * @brief    This header file defines the configuration of USB Host library.
+ * @note
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+#ifndef  _USBH_CONFIG_H_
+#define  _USBH_CONFIG_H_
+
+/// @cond HIDDEN_SYMBOLS
+
+#include 
+#include 
+/*----------------------------------------------------------------------------------------*/
+/*   Hardware settings                                                                    */
+/*----------------------------------------------------------------------------------------*/
+#define HCLK_MHZ               192          /* used for loop-delay. must be larger than 
+                                               true HCLK clock MHz                        */
+
+#define ENABLE_OHCI_IRQ()      NVIC_EnableIRQ(USBH_IRQn)
+#define DISABLE_OHCI_IRQ()     NVIC_DisableIRQ(USBH_IRQn)
+
+#define ENABLE_OHCI                         /* Enable OHCI host controller                */
+
+#define OHCI_ISO_DELAY         4            /* preserved number frames while scheduling 
+                                               OHCI isochronous transfer                  */
+
+#define MAX_DESC_BUFF_SIZE     512          /* To hold the configuration descriptor, USB 
+                                               core will allocate a buffer with this size
+                                               for each connected device. USB core does 
+                                               not release it until device disconnected.  */
+
+/*----------------------------------------------------------------------------------------*/
+/*   Memory allocation settings                                                           */
+/*----------------------------------------------------------------------------------------*/
+
+#define STATIC_MEMORY_ALLOC    0       /* pre-allocate static memory blocks. No dynamic memory aloocation.
+                                          But the maximum number of connected devices and transfers are
+                                          limited.  */
+
+#define MAX_UDEV_DRIVER        8       /*!< Maximum number of registered drivers                      */
+#define MAX_ALT_PER_IFACE      8       /*!< maximum number of alternative interfaces per interface    */
+#define MAX_EP_PER_IFACE       6       /*!< maximum number of endpoints per interface                 */
+#define MAX_HUB_DEVICE         8       /*!< Maximum number of hub devices                             */
+
+/* Host controller hardware transfer descriptors memory pool. ED/TD/ITD of OHCI and QH/QTD of EHCI
+   are all allocated from this pool. Allocated unit size is determined by MEM_POOL_UNIT_SIZE.
+   May allocate one or more units depend on hardware descriptor type.                                 */
+
+#define MEM_POOL_UNIT_SIZE     64      /*!< A fixed hard coding setting. Do not change it!            */
+#define MEM_POOL_UNIT_NUM     256      /*!< Increase this or heap size if memory allocate failed.     */
+
+/*----------------------------------------------------------------------------------------*/
+/*   Re-defined staff for various compiler                                                */
+/*----------------------------------------------------------------------------------------*/
+#ifdef __ICCARM__
+#define   __inline    inline
+#endif
+
+
+/*----------------------------------------------------------------------------------------*/
+/*   Debug settings                                                                       */
+/*----------------------------------------------------------------------------------------*/
+#define ENABLE_ERROR_MSG                    /* enable debug messages                      */
+#define ENABLE_DEBUG_MSG                    /* enable debug messages                      */
+//#define ENABLE_VERBOSE_DEBUG              /* verbos debug messages                      */
+//#define DUMP_DESCRIPTOR                     /* dump descriptors                           */
+
+#ifdef ENABLE_ERROR_MSG
+#define USB_error            rt_kprintf
+#else
+#define USB_error(...)
+#endif
+
+#ifdef ENABLE_DEBUG_MSG
+#define USB_debug            rt_kprintf
+#ifdef ENABLE_VERBOSE_DEBUG
+#define USB_vdebug          rt_kprintf
+#else
+#define USB_vdebug(...)
+#endif
+#else
+#define USB_debug(...)
+#define USB_vdebug(...)
+#endif
+
+
+/// @endcond HIDDEN_SYMBOLS
+
+#endif  /* _USBH_CONFIG_H_ */
+
+/*** (C) COPYRIGHT 2019-2020 Nuvoton Technology Corp. ***/
+
diff --git a/bsp/nuvoton/libraries/m2354/USBHostLib/inc/hub.h b/bsp/nuvoton/libraries/m2354/USBHostLib/inc/hub.h
new file mode 100644
index 0000000000..11a83dd09e
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/USBHostLib/inc/hub.h
@@ -0,0 +1,136 @@
+/**************************************************************************//**
+ * @file     hub.h
+ * @version  V1.00
+ * @brief    USB Host hub class driver header file.
+ * @note
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+#ifndef _USBH_HUB_H_
+#define _USBH_HUB_H_
+
+
+/// @cond HIDDEN_SYMBOLS
+
+
+/*--------------------------------------------------------------------------*/
+/*   Hub class feature selectors (Table 11-17)                              */
+/*--------------------------------------------------------------------------*/
+#define FS_C_HUB_LOCAL_POWER           0
+#define FS_C_HUB_OVER_CURRENT          1
+
+#define FS_PORT_CONNECTION             0
+#define FS_PORT_ENABLE                 1
+#define FS_PORT_SUSPEND                2
+#define FS_PORT_OVER_CURRENT           3
+#define FS_PORT_RESET                  4
+#define FS_PORT_POWER                  8
+#define FS_C_PORT_CONNECTION           16
+#define FS_C_PORT_ENABLE               17
+#define FS_C_PORT_SUSPEND              18
+#define FS_C_PORT_OVER_CURRENT         19
+#define FS_C_PORT_RESET                20
+
+/*--------------------------------------------------------------------------*/
+/*   Hub/Port staus and change bits                                         */
+/*--------------------------------------------------------------------------*/
+#define HUB_S_LOCAL_POWER              (1UL << 0)
+#define HUB_S_OVERCURRENT              (1UL << 1)
+
+#define HUB_C_LOCAL_POWER              (1UL << 0)
+#define HUB_C_OVERCURRENT              (1UL << 1)
+
+#define PORT_S_CONNECTION              (1UL << 0)
+#define PORT_S_ENABLE                  (1UL << 1)
+#define PORT_S_SUSPEND                 (1UL << 2)
+#define PORT_S_OVERCURRENT             (1UL << 3)
+#define PORT_S_RESET                   (1UL << 4)
+#define PORT_S_PORT_POWER              (1UL << 8)
+#define PORT_S_LOW_SPEED               (1UL << 9)
+#define PORT_S_HIGH_SPEED              (1UL << 10)
+#define PORT_S_TEST                    (1UL << 11)
+#define PORT_S_INDICATOR               (1UL << 12)
+
+#define PORT_C_CONNECTION              (1UL << 0)
+#define PORT_C_ENABLE                  (1UL << 1)
+#define PORT_C_SUSPEND                 (1UL << 2)
+#define PORT_C_OVERCURRENT             (1UL << 3)
+#define PORT_C_RESET                   (1UL << 4)
+
+
+/*--------------------------------------------------------------------------*/
+/*   Hub descriptor                                                         */
+/*--------------------------------------------------------------------------*/
+#ifdef __ICCARM__
+typedef struct
+{
+    __packed uint8_t  bDescLength;
+    __packed uint8_t  bDescriptorType;
+    __packed uint8_t  bNbrPorts;
+    __packed uint16_t wHubCharacteristics;
+    __packed uint8_t  bPwrOn2PwrGood;
+    __packed uint8_t  bHubContrCurrent;
+    __packed uint8_t  bDeviceRemovble;
+    __packed uint8_t  PortPwrCtrlMask[16];
+}  DESC_HUB_T;
+#else
+typedef struct __attribute__((__packed__))
+{
+    uint8_t  bDescLength;
+    uint8_t  bDescriptorType;
+    uint8_t  bNbrPorts;
+    uint16_t wHubCharacteristics;
+    uint8_t  bPwrOn2PwrGood;
+    uint8_t  bHubContrCurrent;
+    uint8_t  bDeviceRemovble;
+    uint8_t  PortPwrCtrlMask[16];
+}  DESC_HUB_T;
+#endif
+
+/*
+ *   wHubCharacteristics bit field mask
+ */
+#define HUB_CHAR_LPSM                  0x0003   /* 00b: global port power, 01b: per port power, 1x: reserved */
+#define HUB_CHAR_COMPOUND              0x0004   /* 1: is part of a compond device, 0: is not.       */
+#define HUB_CHAR_OCPM                  0x0018   /* 00b: global over-current protection, 01b: per port, 1x: reserved  */
+#define HUB_CHAR_TTTT                  0x0060   /* TT think time. 00b: 8FS, 01b: 16FS, 10b: 24FS, 11b: 32FS  */
+#define HUB_CHAR_PORTIND               0x0080   /* 1: port indicator (LED) supported, 0: not      */
+
+/* port indicator status selectors */
+#define HUB_LED_AUTO                   0
+#define HUB_LED_AMBER                  1
+#define HUB_LED_GREEN                  2
+#define HUB_LED_OFF                    3
+
+
+/*--------------------------------------------------------------------------*/
+/*   Port reset retry and time-out settings                                 */
+/*--------------------------------------------------------------------------*/
+#define PORT_RESET_RETRY               3        /* port reset retry times                          */
+#define PORT_RESET_TIME_MS             50       /* port reset time (ms)                            */
+#define PORT_RESET_RETRY_INC_MS        250      /* increased reset time (ms) after reset failed    */
+
+
+#define HUB_STATUS_MAX_BYTE            2        /* maximum number of interrupt-in status bytes     */
+/* 2 can support up to 16 port hubs                */
+/* 4 can support up to 32 port hubs                */
+/* Note!! If modeifed to 4, "uint16_t sc_bitmap"   */
+/*        MUST be changed as "uint32_t sc_bitmap"  */
+typedef struct hub_dev_t
+{
+    IFACE_T    *iface;                 /*!< Interface device of this hub          \hideinitializer */
+    UTR_T      *utr;                   /*!< Interrupt in UTR of this hub          \hideinitializer */
+    uint8_t    buff[HUB_STATUS_MAX_BYTE];   /*!< Interrupt in buffer              \hideinitializer */
+    uint16_t   sc_bitmap;              /*!< Hub and Port Status Change Bitmap     \hideinitializer */
+    uint8_t    bNbrPorts;              /*!< Number of ports                       \hideinitializer */
+    uint8_t    bPwrOn2PwrGood;         /*!< Hub power on to power good time       \hideinitializer */
+    char       pos_id[MAX_HUB_DEVICE+1];   /*!< Hub position identifier           \hideinitializer */
+    int        (*port_reset)(struct hub_dev_t *hub, int port);/*!< Port reset function                   \hideinitializer */
+    UDEV_T     *children;              /*!< Child device list.                    \hideinitializer */
+} HUB_DEV_T;
+
+
+/// @endcond
+
+#endif  /* _USBH_HUB_H_ */
diff --git a/bsp/nuvoton/libraries/m2354/USBHostLib/inc/ohci.h b/bsp/nuvoton/libraries/m2354/USBHostLib/inc/ohci.h
new file mode 100644
index 0000000000..d39d935902
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/USBHostLib/inc/ohci.h
@@ -0,0 +1,147 @@
+/**************************************************************************//**
+ * @file     ohci.h
+ * @version  V1.00
+ * @brief    USB OHCI host controller driver header file.
+ * @note
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+#ifndef _USBH_OHCI_H_
+#define _USBH_OHCI_H_
+
+/// @cond HIDDEN_SYMBOLS
+
+struct utr_t;
+struct udev_t;
+
+/* OHCI CONTROL AND STATUS REGISTER MASKS */
+
+/*
+ * Host controller functional state.
+ * for HCFS(HcControl[7:6])
+ */
+#define HCFS_RESET                (0UL << USBH_HcControl_HCFS_Pos)
+#define HCFS_RESUME               (1UL << USBH_HcControl_HCFS_Pos)
+#define HCFS_OPER                 (2UL << USBH_HcControl_HCFS_Pos)
+#define HCFS_SUSPEND              (3UL << USBH_HcControl_HCFS_Pos)
+
+
+/*----------------------------------------------------------------------------------------*/
+/*   Endpoint descriptor                                                                  */
+/*----------------------------------------------------------------------------------------*/
+typedef struct ed_t
+{
+    /* OHCI spec. Endpoint descriptor  */
+    uint32_t    Info;
+    uint32_t    TailP;
+    uint32_t    HeadP;
+    uint32_t    NextED;
+    /* The following members are used by USB Host libary.   */
+    uint8_t     bInterval;
+    uint16_t    next_sf;          /* for isochronous transfer, recording the next SF      */
+    struct ed_t * next;           /* point to the next ED in remove list                  */
+} ED_T;
+
+#define ED_CTRL_FA_Pos            0         /* Info[6:0]   - Function address             */
+#define ED_CTRL_EN_Pos            7         /* Info[10:7]  - Endpoint number              */
+#define ED_CTRL_DIR_Pos           11        /* Info[12:11] - Direction                    */
+#define ED_CTRL_MPS_Pos           16        /* Info[26:16] - Maximum packet size          */
+
+#define ED_FUNC_ADDR_Msk          (0x7f)
+#define ED_EP_ADDR_Msk            (0xf<<7)
+#define ED_DIR_Msk                (0x3<<11)
+#define ED_SPEED_Msk              (1<<13)
+#define ED_MAX_PK_SIZE_Msk        (0x7ff<<16)
+
+#define ED_DIR_BY_TD              (0<>28) & 0x0F)
+#define TD_CC_SET(td, cc)         (td) = ((td) & 0x0FFFFFFF) | (((cc) & 0x0F) << 28)
+#define TD_T_DATA0                0x02000000
+#define TD_T_DATA1                0x03000000
+#define TD_R                      0x00040000
+#define TD_DP                     0x00180000
+#define TD_DP_IN                  0x00100000
+#define TD_DP_OUT                 0x00080000
+#define MAXPSW                    8
+/* steel TD reserved bits to keep driver data */
+#define TD_TYPE_Msk               (0x3<<16)
+#define TD_TYPE_CTRL              (0x0<<16)
+#define TD_TYPE_BULK              (0x1<<16)
+#define TD_TYPE_INT               (0x2<<16)
+#define TD_TYPE_ISO               (0x3<<16)
+#define TD_CTRL_Msk               (0x7<<15)
+#define TD_CTRL_DATA              (1<<15)
+
+
+/*
+ * The HCCA (Host Controller Communications Area) is a 256 byte
+ * structure defined in the OHCI spec. that the host controller is
+ * told the base address of.  It must be 256-byte aligned.
+ */
+typedef struct
+{
+    uint32_t   int_table[32];               /* Interrupt ED table                         */
+    uint16_t   frame_no;                    /* current frame number                       */
+    uint16_t   pad1;                        /* set to 0 on each frame_no change           */
+    uint32_t   done_head;                   /* info returned for an interrupt             */
+    uint8_t    reserved_for_hc[116];
+} HCCA_T;
+
+
+/// @endcond
+
+#endif  /* _USBH_OHCI_H_ */
diff --git a/bsp/nuvoton/libraries/m2354/USBHostLib/inc/usb.h b/bsp/nuvoton/libraries/m2354/USBHostLib/inc/usb.h
new file mode 100644
index 0000000000..b64eacd33c
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/USBHostLib/inc/usb.h
@@ -0,0 +1,470 @@
+/**************************************************************************//**
+ * @file     usb.h
+ * @version  V1.00
+ * @brief    USB Host library header file.
+ * @note
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved.
+ *****************************************************************************/
+
+#ifndef _USBH_H_
+#define _USBH_H_
+
+#include "config.h"
+#include "usbh_lib.h"
+#include "ohci.h"
+
+/// @cond HIDDEN_SYMBOLS
+
+struct utr_t;
+struct udev_t;
+struct hub_dev_t;
+struct iface_t;
+struct ep_info_t;
+
+/*----------------------------------------------------------------------------------*/
+/*   USB device request setup packet                                                */
+/*----------------------------------------------------------------------------------*/
+#ifdef __ICCARM__
+typedef struct
+{
+    __packed uint8_t  bmRequestType;
+    __packed uint8_t  bRequest;
+    __packed uint16_t wValue;
+    __packed uint16_t wIndex;
+    __packed uint16_t wLength;
+} DEV_REQ_T;
+#else
+typedef struct __attribute__((__packed__))
+{
+    uint8_t  bmRequestType;
+    uint8_t  bRequest;
+    uint16_t wValue;
+    uint16_t wIndex;
+    uint16_t wLength;
+}
+DEV_REQ_T;
+#endif
+
+/*
+ *  bmRequestType[7]    - Data transfer direction
+ */
+#define REQ_TYPE_OUT                   0x00
+#define REQ_TYPE_IN                    0x80
+/*
+ *  bmRequestType[6:5]  - Type
+ */
+#define REQ_TYPE_STD_DEV               0x00
+#define REQ_TYPE_CLASS_DEV             0x20
+#define REQ_TYPE_VENDOR_DEV            0x40
+/*
+ *  bmRequestType[4:0]  - Recipient
+ */
+#define REQ_TYPE_TO_DEV                0x00
+#define REQ_TYPE_TO_IFACE              0x01
+#define REQ_TYPE_TO_EP                 0x02
+#define REQ_TYPE_TO_OTHER              0x03
+/*
+ *  Standard Requests
+ */
+#define USB_REQ_GET_STATUS             0x00
+#define USB_REQ_CLEAR_FEATURE          0x01
+#define USB_REQ_SET_FEATURE            0x03
+#define USB_REQ_SET_ADDRESS            0x05
+#define USB_REQ_GET_DESCRIPTOR         0x06
+#define USB_REQ_SET_CONFIGURATION      0x09
+#define USB_REQ_SET_INTERFACE          0x0B
+/*
+ *  Descriptor Types
+ */
+#define USB_DT_STANDARD                0x00
+#define USB_DT_CLASS                   0x20
+#define USB_DT_VENDOR                  0x40
+
+#define USB_DT_DEVICE                  0x01
+#define USB_DT_CONFIGURATION           0x02
+#define USB_DT_STRING                  0x03
+#define USB_DT_INTERFACE               0x04
+#define USB_DT_ENDPOINT                0x05
+#define USB_DT_DEVICE_QUALIFIER        0x06
+#define USB_DT_OTHER_SPEED_CONF        0x07
+#define USB_DT_IFACE_POWER             0x08
+
+
+
+/*----------------------------------------------------------------------------------*/
+/*  USB standard descriptors                                                        */
+/*----------------------------------------------------------------------------------*/
+
+/* Descriptor header */
+#ifdef __ICCARM__
+typedef struct
+{
+    __packed uint8_t  bLength;
+    __packed uint8_t  bDescriptorType;
+} DESC_HDR_T;
+#else
+typedef struct __attribute__((__packed__))
+{
+    uint8_t  bLength;
+    uint8_t  bDescriptorType;
+}
+DESC_HDR_T;
+#endif
+
+/*----------------------------------------------------------------------------------*/
+/*  USB device descriptor                                                           */
+/*----------------------------------------------------------------------------------*/
+#ifdef __ICCARM__
+typedef struct                          /*!< device descriptor structure            */
+{
+    __packed uint8_t  bLength;          /*!< Length of device descriptor            */
+    __packed uint8_t  bDescriptorType;  /*!< Device descriptor type                 */
+    __packed uint16_t bcdUSB;           /*!< USB version number                     */
+    __packed uint8_t  bDeviceClass;     /*!< Device class code                      */
+    __packed uint8_t  bDeviceSubClass;  /*!< Device subclass code                   */
+    __packed uint8_t  bDeviceProtocol;  /*!< Device protocol code                   */
+    __packed uint8_t  bMaxPacketSize0;  /*!< Maximum packet size of control endpoint*/
+    __packed uint16_t idVendor;         /*!< Vendor ID                              */
+    __packed uint16_t idProduct;        /*!< Product ID                             */
+    __packed uint16_t bcdDevice;        /*!< Device ID                              */
+    __packed uint8_t  iManufacturer;    /*!< Manufacture description string ID      */
+    __packed uint8_t  iProduct;         /*!< Product description string ID          */
+    __packed uint8_t  iSerialNumber;    /*!< Serial number description string ID    */
+    __packed uint8_t  bNumConfigurations; /*!< Total number of configurations       */
+} DESC_DEV_T;                           /*!< device descriptor structure            */
+#else
+/*----------------------------------------------------------------------------------*/
+/*  USB device descriptor                                                           */
+/*----------------------------------------------------------------------------------*/
+typedef struct __attribute__((__packed__))        /*!< device descriptor structure  */
+{
+    uint8_t  bLength;                   /*!< Length of device descriptor            */
+    uint8_t  bDescriptorType;           /*!< Device descriptor type                 */
+    uint16_t bcdUSB;                    /*!< USB version number                     */
+    uint8_t  bDeviceClass;              /*!< Device class code                      */
+    uint8_t  bDeviceSubClass;           /*!< Device subclass code                   */
+    uint8_t  bDeviceProtocol;           /*!< Device protocol code                   */
+    uint8_t  bMaxPacketSize0;           /*!< Maximum packet size of control endpoint*/
+    uint16_t idVendor;                  /*!< Vendor ID                              */
+    uint16_t idProduct;                 /*!< Product ID                             */
+    uint16_t bcdDevice;                 /*!< Device ID                              */
+    uint8_t  iManufacturer;             /*!< Manufacture description string ID      */
+    uint8_t  iProduct;                  /*!< Product description string ID          */
+    uint8_t  iSerialNumber;             /*!< Serial number description string ID    */
+    uint8_t  bNumConfigurations;        /*!< Total number of configurations         */
+}
+DESC_DEV_T;                           /*!< device descriptor structure            */
+#endif
+
+/*
+ *  Configuration Descriptor
+ */
+#ifdef __ICCARM__
+typedef struct usb_config_descriptor    /*!< Configuration descriptor structure     */
+{
+    __packed uint8_t   bLength;         /*!< Length of configuration descriptor     */
+    __packed uint8_t   bDescriptorType; /*!< Descriptor type                        */
+    __packed uint16_t  wTotalLength;    /*!< Total length of this configuration     */
+    __packed uint8_t   bNumInterfaces;  /*!< Total number of interfaces             */
+    __packed uint8_t   bConfigurationValue; /*!< Configuration descriptor number    */
+    __packed uint8_t   iConfiguration;  /*!< String descriptor ID                   */
+    __packed uint8_t   bmAttributes;    /*!< Configuration characteristics          */
+    __packed uint8_t   MaxPower;        /*!< Maximum power consumption              */
+} DESC_CONF_T;                          /*!< Configuration descriptor structure     */
+#else
+typedef struct __attribute__((__packed__)) usb_config_descriptor    /*!< Configuration descriptor structure     */
+{
+    uint8_t   bLength;                  /*!< Length of configuration descriptor     */
+    uint8_t   bDescriptorType;          /*!< Descriptor type                        */
+    uint16_t  wTotalLength;             /*!< Total length of this configuration     */
+    uint8_t   bNumInterfaces;           /*!< Total number of interfaces             */
+    uint8_t   bConfigurationValue;      /*!< Configuration descriptor number        */
+    uint8_t   iConfiguration;           /*!< String descriptor ID                   */
+    uint8_t   bmAttributes;             /*!< Configuration characteristics          */
+    uint8_t   MaxPower;                 /*!< Maximum power consumption              */
+} DESC_CONF_T;                          /*!< Configuration descriptor structure     */
+#endif
+
+/*
+ *  Interface Descriptor
+ */
+#ifdef __ICCARM__
+typedef struct usb_interface_descriptor   /*!< Interface descriptor structure       */
+{
+    __packed uint8_t  bLength;          /*!< Length of interface descriptor         */
+    __packed uint8_t  bDescriptorType;  /*!< Descriptor type                        */
+    __packed uint8_t  bInterfaceNumber; /*!< Interface number                       */
+    __packed uint8_t  bAlternateSetting;/*!< Alternate setting number               */
+    __packed uint8_t  bNumEndpoints;    /*!< Number of endpoints                    */
+    __packed uint8_t  bInterfaceClass;  /*!< Interface class code                   */
+    __packed uint8_t  bInterfaceSubClass; /*!< Interface subclass code              */
+    __packed uint8_t  bInterfaceProtocol; /*!< Interface protocol code              */
+    __packed uint8_t  iInterface;       /*!< Interface ID                           */
+} DESC_IF_T;                            /*!< Interface descriptor structure         */
+#else
+typedef struct __attribute__((__packed__)) usb_interface_descriptor     /*!< Interface descriptor structure       */
+{
+    uint8_t  bLength;                   /*!< Length of interface descriptor         */
+    uint8_t  bDescriptorType;           /*!< Descriptor type                        */
+    uint8_t  bInterfaceNumber;          /*!< Interface number                       */
+    uint8_t  bAlternateSetting;         /*!< Alternate setting number               */
+    uint8_t  bNumEndpoints;             /*!< Number of endpoints                    */
+    uint8_t  bInterfaceClass;           /*!< Interface class code                   */
+    uint8_t  bInterfaceSubClass;        /*!< Interface subclass code                */
+    uint8_t  bInterfaceProtocol;        /*!< Interface protocol code                */
+    uint8_t  iInterface;                /*!< Interface ID                           */
+} DESC_IF_T;                            /*!< Interface descriptor structure         */
+#endif
+
+/*
+ *  Interface descriptor bInterfaceClass[7:0]
+ */
+#if 0
+#define USB_CLASS_AUDIO                0x01
+#define USB_CLASS_COMM                 0x02
+#define USB_CLASS_HID                  0x03
+#define USB_CLASS_PRINTER              0x07
+#define USB_CLASS_MASS_STORAGE         0x08
+#define USB_CLASS_HUB                  0x09
+#define USB_CLASS_DATA                 0x0A
+#define USB_CLASS_VIDEO                0x0E
+#endif
+/*
+ *  Endpoint Descriptor
+ */
+#ifdef __ICCARM__
+typedef struct usb_endpoint_descriptor   /*!< Endpoint descriptor structure         */
+{
+    __packed uint8_t  bLength;          /*!< Length of endpoint descriptor          */
+    __packed uint8_t  bDescriptorType;  /*!< Descriptor type                        */
+    __packed uint8_t  bEndpointAddress; /*!< Endpoint address                       */
+    __packed uint8_t  bmAttributes;     /*!< Endpoint attribute                     */
+    __packed uint16_t wMaxPacketSize;   /*!< Maximum packet size                    */
+    __packed uint8_t  bInterval;        /*!< Synchronous transfer interval          */
+    __packed uint8_t  bRefresh;         /*!< Refresh                                */
+    __packed uint8_t  bSynchAddress;    /*!< Sync address                           */
+} DESC_EP_T;                            /*!< Endpoint descriptor structure          */
+#else
+typedef struct __attribute__((__packed__)) usb_endpoint_descriptor    /*!< Endpoint descriptor structure         */
+{
+    uint8_t  bLength;                   /*!< Length of endpoint descriptor          */
+    uint8_t  bDescriptorType;           /*!< Descriptor type                        */
+    uint8_t  bEndpointAddress;          /*!< Endpoint address                       */
+    uint8_t  bmAttributes;              /*!< Endpoint attribute                     */
+    uint16_t wMaxPacketSize;            /*!< Maximum packet size                    */
+    uint8_t  bInterval;                 /*!< Synchronous transfer interval          */
+    uint8_t  bRefresh;                  /*!< Refresh                                */
+    uint8_t  bSynchAddress;             /*!< Sync address                           */
+} DESC_EP_T;                            /*!< Endpoint descriptor structure          */
+#endif
+
+/*
+ *  Endpoint descriptor bEndpointAddress[7] - direction
+ */
+#define EP_ADDR_DIR_MASK               0x80
+#define EP_ADDR_DIR_IN                 0x80
+#define EP_ADDR_DIR_OUT                0x00
+
+/*
+ *  Endpoint descriptor bmAttributes[1:0] - transfer type
+ */
+#define EP_ATTR_TT_MASK                0x03
+#define EP_ATTR_TT_CTRL                0x00
+#define EP_ATTR_TT_ISO                 0x01
+#define EP_ATTR_TT_BULK                0x02
+#define EP_ATTR_TT_INT                 0x03
+
+
+/*----------------------------------------------------------------------------------*/
+/*  USB Host controller driver                                                      */
+/*----------------------------------------------------------------------------------*/
+typedef struct
+{
+    int   (*init) (void);
+    void  (*shutdown) (void);
+    void  (*suspend) (void);
+    void  (*resume) (void);
+    int   (*ctrl_xfer)(struct utr_t *utr);
+    int   (*bulk_xfer)(struct utr_t *utr);
+    int   (*int_xfer)(struct utr_t *utr);
+    int   (*iso_xfer)(struct utr_t *utr);
+    int   (*quit_xfer)(struct utr_t *utr, struct ep_info_t *ep);
+
+    /* root hub support */
+    int   (*rthub_port_reset)(int port);
+    int   (*rthub_polling) (void);
+} HC_DRV_T;
+
+
+/*----------------------------------------------------------------------------------*/
+/*  USB device driver                                                               */
+/*----------------------------------------------------------------------------------*/
+typedef struct
+{
+    int   (*probe) (struct iface_t *iface);
+    void  (*disconnect) (struct iface_t *iface);
+    void  (*suspend) (struct iface_t *iface);
+    void  (*resume) (struct iface_t *iface);
+} UDEV_DRV_T;
+
+
+/*----------------------------------------------------------------------------------*/
+/*  USB device                                                                      */
+/*----------------------------------------------------------------------------------*/
+
+typedef enum
+{
+    SPEED_LOW,
+    SPEED_FULL,
+    SPEED_HIGH
+} SPEED_E;
+
+typedef struct ep_info_t
+{
+    uint8_t     bEndpointAddress;
+    uint8_t     bmAttributes;
+    uint8_t     bInterval;
+    uint8_t     bToggle;
+    uint16_t    wMaxPacketSize;
+    void        *hw_pipe;               /*!< point to the HC assocaied endpoint    \hideinitializer */
+}   EP_INFO_T;
+
+typedef struct udev_t
+{
+    DESC_DEV_T    descriptor;           /*!< Device descriptor.                    \hideinitializer */
+    struct hub_dev_t *parent;           /*!< parent hub device                     \hideinitializer */
+    uint8_t       port_num;             /*!< The hub port this device connected on \hideinitializer */
+    uint8_t       dev_num;              /*!< device number                         \hideinitializer */
+    int8_t        cur_conf;             /*!< Currentll selected configuration      \hideinitializer */
+    SPEED_E       speed;                /*!< device speed (low/full/high)          \hideinitializer */
+    /*
+     *  The followings are lightweight USB stack internal used .
+    */
+    uint8_t       *cfd_buff;            /*!< Configuration descriptor buffer.      \hideinitializer */
+    EP_INFO_T     ep0;                  /*!< Endpoint 0                            \hideinitializer */
+    HC_DRV_T      *hc_driver;           /*!< host controller driver                \hideinitializer */
+    struct iface_t  *iface_list;        /*!< Working interface list                \hideinitializer */
+    struct udev_t *next;                /*!< link for global usb device list       \hideinitializer */
+} UDEV_T;
+
+typedef struct alt_iface_t
+{
+    DESC_IF_T     *ifd;                 /*!< point to the location of this alternative interface descriptor in UDEV_T->cfd_buff */
+    EP_INFO_T     ep[MAX_EP_PER_IFACE]; /*!< endpoints of this alternative interface                */
+} ALT_IFACE_T;
+
+typedef struct iface_t
+{
+    UDEV_T        *udev;                /*!< USB device                            \hideinitializer */
+    uint8_t       if_num;               /*!< Interface number                      \hideinitializer */
+    uint8_t       num_alt;              /*!< Number of alternative interface       \hideinitializer */
+    ALT_IFACE_T   *aif;                 /*!< Point to the active alternative interface              */
+    ALT_IFACE_T   alt[MAX_ALT_PER_IFACE];  /*!< List of alternative interface      \hideinitializer */
+    UDEV_DRV_T    *driver;              /*!< Interface associated driver           \hideinitializer */
+    void          *context;             /*!< Reference to device context           \hideinitializer */
+    struct iface_t  *next;              /*!< Point to next interface of the same device. Started from UDEV_T->iface_list   \hideinitializer */
+} IFACE_T;
+
+
+/*----------------------------------------------------------------------------------*/
+/*  URB (USB Request Block)                                                         */
+/*----------------------------------------------------------------------------------*/
+
+#define IF_PER_UTR             8      /* number of frames per UTR isochronous transfer (DO NOT modify it!)  */
+
+typedef void (*FUNC_UTR_T)(struct utr_t *);
+
+typedef struct utr_t
+{
+    UDEV_T      *udev;                /*!< point to associated USB device        \hideinitializer */
+    DEV_REQ_T   setup;                /*!< buffer for setup packet               \hideinitializer */
+    EP_INFO_T   *ep;                  /*!< associated endpoint                   \hideinitializer */
+    uint8_t     *buff;                /*!< transfer buffer                       \hideinitializer */
+    uint8_t     bIsTransferDone;      /*!< tansfer done?                         \hideinitializer */
+    uint32_t    data_len;             /*!< length of data to be transferred      \hideinitializer */
+    uint32_t    xfer_len;             /*!< length of transferred data            \hideinitializer */
+    uint8_t     bIsoNewSched;         /*!< New schedule isochronous transfer     \hideinitializer */
+    uint16_t    iso_sf;               /*!< Isochronous start frame number        \hideinitializer */
+    uint16_t    iso_xlen[IF_PER_UTR]; /*!< transfer length of isochronous frames \hideinitializer */
+    uint8_t *   iso_buff[IF_PER_UTR]; /*!< transfer buffer address of isochronous frames \hideinitializer */
+    int         iso_status[IF_PER_UTR]; /*!< transfer status of isochronous frames \hideinitializer */
+    int         td_cnt;               /*!< number of transfer descriptors        \hideinitializer */
+    int         status;               /*!< return status                         \hideinitializer */
+    int         interval;             /*!< interrupt/isochronous interval        \hideinitializer */
+    void        *context;             /*!< point to deivce proprietary data area \hideinitializer */
+    FUNC_UTR_T  func;                 /*!< tansfer done call-back function       \hideinitializer */
+    struct utr_t  *next;              /* point to the next UTR of the same endpoint. \hideinitializer */
+} UTR_T;
+
+
+/*----------------------------------------------------------------------------------*/
+/*  Global variables                                                                */
+/*----------------------------------------------------------------------------------*/
+extern USBH_T      *_ohci;
+
+extern HC_DRV_T    ohci_driver;
+
+extern UDEV_T * g_udev_list;
+
+/*----------------------------------------------------------------------------------*/
+/*  USB stack exported functions                                                    */
+/*----------------------------------------------------------------------------------*/
+extern void usbh_delay_ms(int msec);
+
+extern void dump_ohci_regs(void);
+extern void dump_ohci_ports(void);
+extern void dump_ohci_int_table(void);
+extern void usbh_dump_buff_bytes(uint8_t *buff, int nSize);
+extern void usbh_dump_interface_descriptor(DESC_IF_T *if_desc);
+extern void usbh_dump_endpoint_descriptor(DESC_EP_T *ep_desc);
+extern void usbh_dump_iface(IFACE_T *iface);
+extern void usbh_dump_ep_info(EP_INFO_T *ep);
+
+/*
+ *  Memory management functions
+ */
+extern void usbh_memory_init(void);
+extern uint32_t  usbh_memory_used(void);
+extern void * usbh_alloc_mem(int size);
+extern void usbh_free_mem(void *p, int size);
+extern int  alloc_dev_address(void);
+extern void free_dev_address(int dev_addr);
+extern UDEV_T * alloc_device(void);
+extern void free_device(UDEV_T *udev);
+extern UTR_T * alloc_utr(UDEV_T *udev);
+extern void free_utr(UTR_T *utr);
+extern ED_T * alloc_ohci_ED(void);
+extern void free_ohci_ED(ED_T *ed);
+extern TD_T * alloc_ohci_TD(UTR_T *utr);
+extern void free_ohci_TD(TD_T *td);
+
+
+extern void usbh_hub_init(void);
+extern int  usbh_connect_device(UDEV_T *);
+extern void usbh_disconnect_device(UDEV_T *);
+extern int  usbh_register_driver(UDEV_DRV_T *driver);
+extern EP_INFO_T * usbh_iface_find_ep(IFACE_T *iface, uint8_t ep_addr, uint8_t dir_type);
+extern int  usbh_reset_device(UDEV_T *);
+extern int usbh_reset_port(UDEV_T *);
+
+/*
+ *  USB Standard Request functions
+ */
+extern int usbh_get_device_descriptor(UDEV_T *udev, DESC_DEV_T *desc_buff);
+extern int usbh_get_config_descriptor(UDEV_T *udev, uint8_t *desc_buff, int buff_len);
+extern int usbh_set_configuration(UDEV_T *udev, uint8_t conf_val);
+extern int usbh_set_interface(IFACE_T *iface, uint16_t alt_setting);
+extern int usbh_clear_halt(UDEV_T *udev, uint16_t ep_addr);
+
+extern int usbh_ctrl_xfer(UDEV_T *udev, uint8_t bmRequestType, uint8_t bRequest, uint16_t wValue, uint16_t wIndex, uint16_t wLength, uint8_t *buff, uint32_t *xfer_len, uint32_t timeout);
+extern int usbh_bulk_xfer(UTR_T *utr);
+extern int usbh_int_xfer(UTR_T *utr);
+extern int usbh_iso_xfer(UTR_T *utr);
+extern int usbh_quit_utr(UTR_T *utr);
+extern int usbh_quit_xfer(UDEV_T *udev, EP_INFO_T *ep);
+
+
+/// @endcond HIDDEN_SYMBOLS
+
+#endif  /* _USBH_H_ */
diff --git a/bsp/nuvoton/libraries/m2354/USBHostLib/inc/usbh_lib.h b/bsp/nuvoton/libraries/m2354/USBHostLib/inc/usbh_lib.h
new file mode 100644
index 0000000000..e76eebdfe2
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/USBHostLib/inc/usbh_lib.h
@@ -0,0 +1,254 @@
+/**************************************************************************//**
+ * @file     usbh_lib.h
+ * @version  V1.10
+ * @brief    USB Host library exported header file.
+ *
+ * @note
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved.
+ ******************************************************************************/
+#ifndef  _USBH_LIB_H_
+#define  _USBH_LIB_H_
+
+#include "NuMicro.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/** @addtogroup LIBRARY Library
+  @{
+*/
+
+/** @addtogroup USBH_Library USB Host Library
+  @{
+*/
+
+/** @addtogroup USBH_EXPORTED_CONSTANTS USB Host Exported Constants
+  @{
+*/
+
+#define USBH_OK                     0      /*!< No error.                                       */
+#define USBH_ERR_MEMORY_OUT         -10    /*!< Out of memory.                                  */
+#define USBH_ERR_IF_ALT_LIMIT       -11    /*!< Number of alternative interface > MAX_ALT_PER_IFACE */
+#define USBH_ERR_IF_EP_LIMIT        -15    /*!< Number of endpoints > MAX_EP_PER_IFACE          */
+#define USBH_ERR_NOT_SUPPORTED      -101   /*!< Device/Class/Transfer not supported             */
+#define USBH_ERR_NOT_MATCHED        -103   /*!< Not macthed                                     */
+#define USBH_ERR_NOT_EXPECTED       -104   /*!< Unknown or unexpected                           */
+#define USBH_ERR_INVALID_PARAM      -105   /*!< Invalid parameter                               */
+#define USBH_ERR_NOT_FOUND          -106   /*!< Device or interface not found                   */
+#define USBH_ERR_EP_NOT_FOUND       -107   /*!< Endpoint not found                              */
+#define USBH_ERR_DESCRIPTOR         -137   /*!< Failed to parse USB descriptors                 */
+#define USBH_ERR_SET_DEV_ADDR       -139   /*!< Failed to set device address                    */
+#define USBH_ERR_SET_CONFIG         -151   /*!< Failed to set device configuration              */
+
+#define USBH_ERR_TRANSFER           -201   /*!< USB transfer error                              */
+#define USBH_ERR_TIMEOUT            -203   /*!< USB transfer time-out                           */
+#define USBH_ERR_ABORT              -205   /*!< USB transfer aborted due to disconnect or reset */
+#define USBH_ERR_PORT_RESET         -255   /*!< Hub port reset failed                           */
+#define USBH_ERR_SCH_OVERRUN        -257   /*!< USB isochronous schedule overrun                */
+#define USBH_ERR_DISCONNECTED       -259   /*!< USB device was disconnected                     */
+
+#define USBH_ERR_TRANSACTION        -271   /*!< USB transaction timeout, CRC, Bad PID, etc.     */
+#define USBH_ERR_BABBLE_DETECTED    -272   /*!< A babble is detected during the transaction   */
+#define USBH_ERR_DATA_BUFF          -274   /*!< Data buffer overrun or underrun                 */
+
+#define USBH_ERR_CC_NO_ERR          -280   /*!< OHCI CC code - no error                         */
+#define USBH_ERR_CRC                -281   /*!< USB trasfer CRC error                           */
+#define USBH_ERR_BIT_STUFF          -282   /*!< USB transfer bit stuffing error                 */
+#define USBH_ERR_DATA_TOGGLE        -283   /*!< USB trasfer data toggle error                   */
+#define USBH_ERR_STALL              -284   /*!< USB trasfer STALL error                         */
+#define USBH_ERR_DEV_NO_RESP        -285   /*!< USB trasfer device no response error            */
+#define USBH_ERR_PID_CHECK          -286   /*!< USB trasfer PID check failure                   */
+#define USBH_ERR_UNEXPECT_PID       -287   /*!< USB trasfer unexpected PID error                */
+#define USBH_ERR_DATA_OVERRUN       -288   /*!< USB trasfer data overrun error                  */
+#define USBH_ERR_DATA_UNDERRUN      -289   /*!< USB trasfer data underrun error                 */
+#define USBH_ERR_BUFF_OVERRUN       -292   /*!< USB trasfer buffer overrun error                */
+#define USBH_ERR_BUFF_UNDERRUN      -293   /*!< USB trasfer buffer underrun error               */
+#define USBH_ERR_NOT_ACCESS0        -294   /*!< USB trasfer not accessed error                  */
+#define USBH_ERR_NOT_ACCESS1        -295   /*!< USB trasfer not accessed error                  */
+
+#define USBH_ERR_OHCI_INIT          -301   /*!< Failed to initialize OHIC controller.           */
+#define USBH_ERR_OHCI_EP_BUSY       -303   /*!< The endpoint is under transfer.                 */
+
+#define USBH_ERR_EHCI_INIT          -501   /*!< Failed to initialize EHCI controller.           */
+#define USBH_ERR_EHCI_QH_BUSY       -503   /*!< the Queue Head is busy.                         */
+
+#define UMAS_OK                     0      /*!< No error.                                       */
+#define UMAS_ERR_NO_DEVICE          -1031  /*!< No Mass Stroage Device found.                   */
+#define UMAS_ERR_IO                 -1033  /*!< Device read/write failed.                       */
+#define UMAS_ERR_INIT_DEVICE        -1035  /*!< failed to init MSC device                       */
+#define UMAS_ERR_CMD_STATUS         -1037  /*!< SCSI command status failed                      */
+#define UMAS_ERR_IVALID_PARM        -1038  /*!< Invalid parameter.                              */
+#define UMAS_ERR_DRIVE_NOT_FOUND    -1039  /*!< drive not found                                 */
+
+#define HID_RET_OK                  0      /*!< Return with no errors.                          */
+#define HID_RET_DEV_NOT_FOUND       -1081  /*!< HID device not found or removed.                */
+#define HID_RET_IO_ERR              -1082  /*!< USB transfer failed.                            */
+#define HID_RET_INVALID_PARAMETER   -1083  /*!< Invalid parameter.                              */
+#define HID_RET_OUT_OF_MEMORY       -1084  /*!< Out of memory.                                  */
+#define HID_RET_NOT_SUPPORTED       -1085  /*!< Function not supported.                         */
+#define HID_RET_EP_NOT_FOUND        -1086  /*!< Endpoint not found.                             */
+#define HID_RET_PARSING             -1087  /*!< Failed to parse HID descriptor                  */
+#define HID_RET_XFER_IS_RUNNING     -1089  /*!< The transfer has been enabled.                  */
+#define HID_RET_REPORT_NOT_FOUND    -1090  /*!< The transfer has been enabled.                  */
+
+#define UAC_RET_OK                   0     /*!< Return with no errors.                          */
+#define UAC_RET_DEV_NOT_FOUND       -2001  /*!< Audio Class device not found or removed.        */
+#define UAC_RET_FUNC_NOT_FOUND      -2002  /*!< Audio device has no this function.              */
+#define UAC_RET_IO_ERR              -2003  /*!< USB transfer failed.                            */
+#define UAC_RET_DATA_LEN            -2004  /*!< Unexpected transfer length                      */
+#define UAC_RET_INVALID             -2005  /*!< Invalid parameter or usage.                     */
+#define UAC_RET_OUT_OF_MEMORY       -2007  /*!< Out of memory.                                  */
+#define UAC_RET_DRV_NOT_SUPPORTED   -2009  /*!< Function not supported by this UAC driver.      */
+#define UAC_RET_DEV_NOT_SUPPORTED   -2011  /*!< Function not supported by the UAC device.       */
+#define UAC_RET_PARSER              -2013  /*!< Failed to parse UAC descriptor                  */
+#define UAC_RET_IS_STREAMING        -2015  /*!< Audio pipe is on streaming.                     */
+
+
+/*@}*/ /* end of group USBH_EXPORTED_CONSTANTS */
+
+
+/** @addtogroup USBH_EXPORTED_TYPEDEF USB Host Typedef
+  @{
+*/
+struct udev_t;
+typedef void (CONN_FUNC)(struct udev_t *udev, int param);
+
+struct line_coding_t;
+struct cdc_dev_t;
+typedef void (CDC_CB_FUNC)(struct cdc_dev_t *cdev, uint8_t *rdata, int data_len);
+
+struct usbhid_dev;
+typedef void (HID_IR_FUNC)(struct usbhid_dev *hdev, uint16_t ep_addr, int status, uint8_t *rdata, uint32_t data_len);    /*!< interrupt in callback function \hideinitializer */
+typedef void (HID_IW_FUNC)(struct usbhid_dev *hdev, uint16_t ep_addr, int status, uint8_t *wbuff, uint32_t *data_len);   /*!< interrupt out callback function \hideinitializer */
+
+struct uac_dev_t;
+typedef int (UAC_CB_FUNC)(struct uac_dev_t *dev, uint8_t *data, int len);    /*!< audio in callback function \hideinitializer */
+
+/*@}*/ /* end of group USBH_EXPORTED_STRUCT */
+
+
+
+/** @addtogroup USBH_EXPORTED_FUNCTIONS USB Host Exported Functions
+  @{
+*/
+
+/*------------------------------------------------------------------*/
+/*                                                                  */
+/*  USB Core Library APIs                                           */
+/*                                                                  */
+/*------------------------------------------------------------------*/
+extern void usbh_core_init(void);
+extern int  usbh_polling_root_hubs(void);
+extern void usbh_install_conn_callback(CONN_FUNC *conn_func, CONN_FUNC *disconn_func);
+extern void usbh_suspend(void);
+extern void usbh_resume(void);
+extern struct udev_t * usbh_find_device(char *hub_id, int port);
+/**
+ * @brief  A function return current tick count.
+ * @return Current tick.
+ * @details User application must provide this function to return current tick.
+ *          The tick should increase by 1 for every 10 ms.
+ */
+extern uint32_t usbh_get_ticks(void);   /* This function must be provided by user application. */
+extern uint32_t usbh_tick_from_millisecond(uint32_t msec);   /* This function must be provided by user application. */
+
+/*------------------------------------------------------------------*/
+/*                                                                  */
+/*  USB Communication Device Class Library APIs                     */
+/*                                                                  */
+/*------------------------------------------------------------------*/
+extern void     usbh_cdc_init(void);
+extern struct cdc_dev_t * usbh_cdc_get_device_list(void);
+/// @cond HIDDEN_SYMBOLS
+extern int32_t  usbh_cdc_get_line_coding(struct cdc_dev_t *cdev, struct line_coding_t *line_code);
+extern int32_t  usbh_cdc_set_line_coding(struct cdc_dev_t *cdev, struct line_coding_t *line_code);
+/// @endcond HIDDEN_SYMBOLS
+extern int32_t  usbh_cdc_set_control_line_state(struct cdc_dev_t *cdev, int active_carrier, int DTE_present);
+extern int32_t  usbh_cdc_start_polling_status(struct cdc_dev_t *cdev, CDC_CB_FUNC *func);
+extern int32_t  usbh_cdc_start_to_receive_data(struct cdc_dev_t *cdev, CDC_CB_FUNC *func);
+extern int32_t  usbh_cdc_send_data(struct cdc_dev_t *cdev, uint8_t *buff, int buff_len);
+
+
+/*------------------------------------------------------------------*/
+/*                                                                  */
+/*  USB Human Interface Class Library APIs                          */
+/*                                                                  */
+/*------------------------------------------------------------------*/
+extern void     usbh_hid_init(void);
+extern struct usbhid_dev * usbh_hid_get_device_list(void);
+extern int32_t  usbh_hid_get_report_descriptor(struct usbhid_dev *hdev, uint8_t *desc_buf, int buf_max_len);
+extern int32_t  usbh_hid_get_report(struct usbhid_dev *hdev, int rtp_typ, int rtp_id, uint8_t *data, int len);
+extern int32_t  usbh_hid_set_report(struct usbhid_dev *hdev, int rtp_typ, int rtp_id, uint8_t *data, int len);
+extern int32_t  usbh_hid_get_idle(struct usbhid_dev *hdev, int rtp_id, uint8_t *idle_rate);
+extern int32_t  usbh_hid_set_idle(struct usbhid_dev *hdev, int rtp_id, uint8_t idle_rate);
+extern int32_t  usbh_hid_get_protocol(struct usbhid_dev *hdev, uint8_t *protocol);
+extern int32_t  usbh_hid_set_protocol(struct usbhid_dev *hdev, uint8_t protocol);
+extern int32_t  usbh_hid_start_int_read(struct usbhid_dev *hdev, uint8_t ep_addr, HID_IR_FUNC *func);
+extern int32_t  usbh_hid_stop_int_read(struct usbhid_dev *hdev, uint8_t ep_addr);
+extern int32_t  usbh_hid_start_int_write(struct usbhid_dev *hdev, uint8_t ep_addr, HID_IW_FUNC *func);
+extern int32_t  usbh_hid_stop_int_write(struct usbhid_dev *hdev, uint8_t ep_addr);
+
+/*------------------------------------------------------------------*/
+/*                                                                  */
+/*  USB Mass Storage Class Library APIs                             */
+/*                                                                  */
+/*------------------------------------------------------------------*/
+extern int  usbh_umas_init(void);
+extern int  usbh_umas_disk_status(int drv_no);
+extern int  usbh_umas_read(int drv_no, uint32_t sec_no, int sec_cnt, uint8_t *buff);
+extern int  usbh_umas_write(int drv_no, uint32_t sec_no, int sec_cnt, uint8_t *buff);
+extern int  usbh_umas_ioctl(int drv_no, int cmd, void *buff);
+/// @cond HIDDEN_SYMBOLS
+extern int  usbh_umas_reset_disk(int drv_no);
+/// @endcond HIDDEN_SYMBOLS
+/*------------------------------------------------------------------*/
+/*                                                                  */
+/*  USB Audio Class Library APIs                                    */
+/*                                                                  */
+/*------------------------------------------------------------------*/
+extern void usbh_uac_init(void);
+extern int usbh_uac_open(struct uac_dev_t *audev);
+extern struct uac_dev_t * usbh_uac_get_device_list(void);
+extern int usbh_uac_get_channel_number(struct uac_dev_t *audev, uint8_t target);
+extern int usbh_uac_get_bit_resolution(struct uac_dev_t *audev, uint8_t target, uint8_t *byte_cnt);
+extern int usbh_uac_get_sampling_rate(struct uac_dev_t *audev, uint8_t target, uint32_t *srate_list, int max_cnt, uint8_t *type);
+extern int usbh_uac_sampling_rate_control(struct uac_dev_t *audev, uint8_t target, uint8_t req, uint32_t *srate);
+extern int usbh_uac_mute_control(struct uac_dev_t *audev, uint8_t target, uint8_t req, uint16_t chn, uint8_t *mute);
+extern int usbh_uac_vol_control(struct uac_dev_t *audev, uint8_t target, uint8_t req, uint16_t chn, uint16_t *volume);
+extern int usbh_uac_auto_gain_control(struct uac_dev_t *audev, uint8_t target, uint8_t req, uint16_t chn, uint8_t *bAGC);
+extern int usbh_uac_start_audio_in(struct uac_dev_t *uac, UAC_CB_FUNC *func);
+extern int usbh_uac_stop_audio_in(struct uac_dev_t *audev);
+extern int usbh_uac_start_audio_out(struct uac_dev_t *uac, UAC_CB_FUNC *func);
+extern int usbh_uac_stop_audio_out(struct uac_dev_t *audev);
+
+
+/// @cond HIDDEN_SYMBOLS
+
+extern void dump_ohci_regs(void);
+extern void dump_ehci_regs(void);
+extern void dump_ohci_ports(void);
+extern void dump_ehci_ports(void);
+extern uint32_t  usbh_memory_used(void);
+
+/// @endcond HIDDEN_SYMBOLS
+
+
+/*@}*/ /* end of group USBH_EXPORTED_FUNCTIONS */
+
+/*@}*/ /* end of group USBH_Library */
+
+/*@}*/ /* end of group LIBRARY */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _USBH_LIB_H_ */
+
+/*** (C) COPYRIGHT 2019-2020 Nuvoton Technology Corp. ***/
+
+
+
diff --git a/bsp/nuvoton/libraries/m2354/USBHostLib/src/mem_alloc.c b/bsp/nuvoton/libraries/m2354/USBHostLib/src/mem_alloc.c
new file mode 100644
index 0000000000..97d41ef130
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/USBHostLib/src/mem_alloc.c
@@ -0,0 +1,316 @@
+/**************************************************************************//**
+ * @file     mem_alloc.c
+ * @version  V1.10
+ * @brief   USB host library memory allocation functions.
+ *
+ * @note
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include 
+#include 
+#include 
+
+#include "NuMicro.h"
+
+#include "usb.h"
+
+
+/// @cond HIDDEN_SYMBOLS
+
+//#define MEM_DEBUG
+
+#ifdef MEM_DEBUG
+#define mem_debug       rt_kprintf
+#else
+#define mem_debug(...)
+#endif
+
+#ifdef __ICCARM__
+#pragma data_alignment=32
+static uint8_t  _mem_pool[MEM_POOL_UNIT_NUM][MEM_POOL_UNIT_SIZE];
+#else
+static uint8_t _mem_pool[MEM_POOL_UNIT_NUM][MEM_POOL_UNIT_SIZE] __attribute__((aligned(32)));
+#endif
+static uint8_t  _unit_used[MEM_POOL_UNIT_NUM];
+
+static volatile int  _usbh_mem_used;
+static volatile int  _usbh_max_mem_used;
+static volatile int  _mem_pool_used;
+
+
+UDEV_T * g_udev_list;
+
+uint8_t  _dev_addr_pool[128];
+static volatile int  _device_addr;
+
+/*--------------------------------------------------------------------------*/
+/*   Memory alloc/free recording                                            */
+/*--------------------------------------------------------------------------*/
+
+void usbh_memory_init(void)
+{
+    if(sizeof(TD_T) > MEM_POOL_UNIT_SIZE)
+    {
+        USB_error("TD_T - MEM_POOL_UNIT_SIZE too small!\n");
+        while(1);
+    }
+
+    if(sizeof(ED_T) > MEM_POOL_UNIT_SIZE)
+    {
+        USB_error("ED_T - MEM_POOL_UNIT_SIZE too small!\n");
+        while(1);
+    }
+
+    _usbh_mem_used = 0L;
+    _usbh_max_mem_used = 0L;
+
+    memset(_unit_used, 0, sizeof(_unit_used));
+    _mem_pool_used = 0;
+
+    g_udev_list = NULL;
+
+    memset(_dev_addr_pool, 0, sizeof(_dev_addr_pool));
+    _device_addr = 1;
+}
+
+uint32_t  usbh_memory_used(void)
+{
+    rt_kprintf("USB static memory: %d/%d, heap used: %d\n", _mem_pool_used, MEM_POOL_UNIT_NUM, _usbh_mem_used);
+    return _usbh_mem_used;
+}
+
+static void  memory_counter(int size)
+{
+    _usbh_mem_used += size;
+    if (_usbh_mem_used > _usbh_max_mem_used)
+        _usbh_max_mem_used = _usbh_mem_used;
+}
+
+void * usbh_alloc_mem(int size)
+{
+    void  *p;
+
+    p = malloc(size);
+    if (p == NULL)
+    {
+        USB_error("usbh_alloc_mem failed! %d\n", size);
+        return NULL;
+    }
+
+    memset(p, 0, size);
+    memory_counter(size);
+    return p;
+}
+
+void usbh_free_mem(void *p, int size)
+{
+    free(p);
+    memory_counter(0-size);
+}
+
+
+/*--------------------------------------------------------------------------*/
+/*   USB device allocate/free                                               */
+/*--------------------------------------------------------------------------*/
+
+UDEV_T * alloc_device(void)
+{
+    UDEV_T  *udev;
+
+    udev = malloc(sizeof(*udev));
+    if (udev == NULL)
+    {
+        USB_error("alloc_device failed!\n");
+        return NULL;
+    }
+    memset(udev, 0, sizeof(*udev));
+    memory_counter(sizeof(*udev));
+    udev->cur_conf = -1;                    /* must! used to identify the first SET CONFIGURATION */
+    udev->next = g_udev_list;               /* chain to global device list */
+    g_udev_list = udev;
+    return udev;
+}
+
+void free_device(UDEV_T *udev)
+{
+    UDEV_T  *d;
+
+    if (udev == NULL)
+        return;
+
+    if (udev->cfd_buff != NULL)
+        usbh_free_mem(udev->cfd_buff, MAX_DESC_BUFF_SIZE);
+
+    /*
+     *  Remove it from the global device list
+     */
+    if (g_udev_list == udev)
+    {
+        g_udev_list = g_udev_list->next;
+    }
+    else
+    {
+        d = g_udev_list;
+        while (d != NULL)
+        {
+            if (d->next == udev)
+            {
+                d->next = udev->next;
+                break;
+            }
+            d = d->next;
+        }
+    }
+
+    free(udev);
+    memory_counter(-sizeof(*udev));
+}
+
+int  alloc_dev_address(void)
+{
+    _device_addr++;
+
+    if (_device_addr >= 128)
+        _device_addr = 1;
+
+    while (1)
+    {
+        if (_dev_addr_pool[_device_addr] == 0)
+        {
+            _dev_addr_pool[_device_addr] = 1;
+            return _device_addr;
+        }
+        _device_addr++;
+        if (_device_addr >= 128)
+            _device_addr = 1;
+    }
+}
+
+void  free_dev_address(int dev_addr)
+{
+    if (dev_addr < 128)
+        _dev_addr_pool[dev_addr] = 0;
+}
+
+/*--------------------------------------------------------------------------*/
+/*   UTR (USB Transfer Request) allocate/free                               */
+/*--------------------------------------------------------------------------*/
+
+UTR_T * alloc_utr(UDEV_T *udev)
+{
+    UTR_T  *utr;
+
+    utr = malloc(sizeof(*utr));
+    if (utr == NULL)
+    {
+        USB_error("alloc_utr failed!\n");
+        return NULL;
+    }
+    memory_counter(sizeof(*utr));
+    memset(utr, 0, sizeof(*utr));
+    utr->udev = udev;
+    mem_debug("[ALLOC] [UTR] - 0x%x\n", (int)utr);
+    return utr;
+}
+
+void free_utr(UTR_T *utr)
+{
+    if (utr == NULL)
+        return;
+
+    mem_debug("[FREE] [UTR] - 0x%x\n", (int)utr);
+    free(utr);
+    memory_counter(0-(int)sizeof(*utr));
+}
+
+/*--------------------------------------------------------------------------*/
+/*   OHCI ED allocate/free                                                  */
+/*--------------------------------------------------------------------------*/
+
+ED_T * alloc_ohci_ED(void)
+{
+    int    i;
+    ED_T   *ed;
+
+    for (i = 0; i < MEM_POOL_UNIT_NUM; i++)
+    {
+        if (_unit_used[i] == 0)
+        {
+            _unit_used[i] = 1;
+            _mem_pool_used++;
+            ed = (ED_T *)&_mem_pool[i];
+            memset(ed, 0, sizeof(*ed));
+            mem_debug("[ALLOC] [ED] - 0x%x\n", (int)ed);
+            return ed;
+        }
+    }
+    USB_error("alloc_ohci_ED failed!\n");
+    return NULL;
+}
+
+void free_ohci_ED(ED_T *ed)
+{
+    int      i;
+
+    for (i = 0; i < MEM_POOL_UNIT_NUM; i++)
+    {
+        if ((uint32_t)&_mem_pool[i] == (uint32_t)ed)
+        {
+            mem_debug("[FREE]  [ED] - 0x%x\n", (int)ed);
+            _unit_used[i] = 0;
+            _mem_pool_used--;
+            return;
+        }
+    }
+    USB_debug("free_ohci_ED - not found! (ignored in case of multiple UTR)\n");
+}
+
+/*--------------------------------------------------------------------------*/
+/*   OHCI TD allocate/free                                                  */
+/*--------------------------------------------------------------------------*/
+TD_T * alloc_ohci_TD(UTR_T *utr)
+{
+    int    i;
+    TD_T   *td;
+
+    for (i = 0; i < MEM_POOL_UNIT_NUM; i++)
+    {
+        if (_unit_used[i] == 0)
+        {
+            _unit_used[i] = 1;
+            _mem_pool_used++;
+            td = (TD_T *)&_mem_pool[i];
+
+            memset(td, 0, sizeof(*td));
+            td->utr = utr;
+            mem_debug("[ALLOC] [TD] - 0x%x\n", (int)td);
+            return td;
+        }
+    }
+    USB_error("alloc_ohci_TD failed!\n");
+    return NULL;
+}
+
+void free_ohci_TD(TD_T *td)
+{
+    int   i;
+
+    for (i = 0; i < MEM_POOL_UNIT_NUM; i++)
+    {
+        if ((uint32_t)&_mem_pool[i] == (uint32_t)td)
+        {
+            mem_debug("[FREE]  [TD] - 0x%x\n", (int)td);
+            _unit_used[i] = 0;
+            _mem_pool_used--;
+            return;
+        }
+    }
+    USB_error("free_ohci_TD - not found!\n");
+}
+
+/// @endcond HIDDEN_SYMBOLS
+
+/*** (C) COPYRIGHT 2019-2020 Nuvoton Technology Corp. ***/
+
diff --git a/bsp/nuvoton/libraries/m2354/USBHostLib/src/ohci.c b/bsp/nuvoton/libraries/m2354/USBHostLib/src/ohci.c
new file mode 100644
index 0000000000..ba50055587
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/USBHostLib/src/ohci.c
@@ -0,0 +1,1282 @@
+/**************************************************************************//**
+ * @file     ohci.c
+ * @version  V1.10
+ * @brief   USB Host library OHCI (USB 1.1) host controller driver.
+ *
+ * @note
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include 
+#include 
+#include 
+
+#include "NuMicro.h"
+
+#include "usb.h"
+#include "hub.h"
+#include "ohci.h"
+
+/// @cond HIDDEN_SYMBOLS
+
+//#define TD_debug   printf
+#define TD_debug(...)
+
+//#define ED_debug   printf
+#define ED_debug(...)
+
+#ifdef __ICCARM__
+#pragma data_alignment=256
+HCCA_T _hcca;
+#else
+HCCA_T _hcca __attribute__((aligned(256)));
+#endif
+
+ED_T  * _Ied[6];
+
+
+static ED_T  *ed_remove_list;
+
+static void add_to_ED_remove_list(ED_T *ed)
+{
+    ED_T  *p;
+
+    ED_debug("add_to_ED_remove_list - 0x%x (0x%x)\n", (int)ed, ed->Info);
+    DISABLE_OHCI_IRQ();
+
+    /* check if this ED found in ed_remove_list */
+    p = ed_remove_list;
+    while (p)
+    {
+        if (p == ed)
+        {
+            ENABLE_OHCI_IRQ();              /* This ED found in ed_remove_list            */
+            return;                         /* do nothing                                 */
+        }
+        p = p->next;
+    }
+
+    ed->Info |= ED_SKIP;                    /* ask OHCI controller skip this ED           */
+    ed->next = ed_remove_list;
+    ed_remove_list = ed;                    /* insert to the head of ed_remove_list       */
+    ENABLE_OHCI_IRQ();
+    _ohci->HcInterruptStatus = USBH_HcInterruptStatus_SF_Msk;
+    _ohci->HcInterruptEnable |= USBH_HcInterruptEnable_SF_Msk;
+    usbh_delay_ms(2);                         /* Full speed wait 2 ms is enough             */
+}
+
+static int ohci_reset(void)
+{
+    volatile int  t0;
+
+    /* Disable HC interrupts  */
+    _ohci->HcInterruptDisable = USBH_HcInterruptDisable_MIE_Msk;
+
+    /* HC Reset requires max 10 ms delay  */
+    _ohci->HcControl = 0;
+    _ohci->HcCommandStatus = USBH_HcCommandStatus_HCR_Msk;
+
+    usbh_delay_ms(10);
+
+    /* Check if OHCI reset completed? */
+    if((_ohci->HcCommandStatus & USBH_HcCommandStatus_HCR_Msk) != 0)
+    {
+        USB_error("Error! - USB OHCI reset timed out!\n");
+        return -1;
+    }
+
+    _ohci->HcRhStatus = USBH_HcRhStatus_OCI_Msk | USBH_HcRhStatus_LPS_Msk;
+
+    _ohci->HcControl = HCFS_RESET;
+
+    usbh_delay_ms(10);
+
+    /* Check if OHCI reset completed? */
+    if((_ohci->HcCommandStatus & USBH_HcCommandStatus_HCR_Msk) != 0)
+    {
+        USB_error("Error! - USB HC reset timed out!\n");
+        return -1;
+    }
+    return 0;
+}
+
+static void init_hcca_int_table()
+{
+    ED_T   *ed_p;
+    int    i, idx, interval;
+
+    memset(_hcca.int_table, 0, sizeof(_hcca.int_table));
+
+    for (i = 5; i >= 0; i--)                /* interval = i^2                             */
+    {
+        _Ied[i] = alloc_ohci_ED();
+        _Ied[i]->Info = ED_SKIP;
+
+        interval = 0x1 << i;
+
+        for (idx = interval - 1; idx < 32; idx += interval)
+        {
+            if (_hcca.int_table[idx] == 0)       /* is empty list, insert directly        */
+            {
+                _hcca.int_table[idx] = (uint32_t)_Ied[i];
+            }
+            else
+            {
+                ed_p = (ED_T *)_hcca.int_table[idx];
+
+                while (1)
+                {
+                    if (ed_p == _Ied[i])
+                        break;                   /* already chained by previous visit     */
+
+                    if (ed_p->NextED == 0)       /* reach end of list?                    */
+                    {
+                        ed_p->NextED = (uint32_t)_Ied[i];
+                        break;
+                    }
+                    ed_p = (ED_T *)ed_p->NextED;
+                }
+            }
+        }
+    }
+}
+
+static ED_T * get_int_tree_head_node(int interval)
+{
+    int    i;
+
+    for (i = 0; i < 5; i++)
+    {
+        interval >>= 1;
+        if (interval == 0)
+            return _Ied[i];
+    }
+    return _Ied[5];                         /* for interval >= 32                         */
+}
+
+static int get_ohci_interval(int interval)
+{
+    int    i, bInterval = 1;
+
+    for (i = 0; i < 5; i++)
+    {
+        interval >>= 1;
+        if (interval == 0)
+            return bInterval;
+        bInterval *= 2;
+    }
+    return 32;                              /* for interval >= 32                         */
+}
+
+
+static int  ohci_init(void)
+{
+    uint32_t    fminterval;
+    volatile int    i;
+
+    if (ohci_reset() < 0)
+        return -1;
+
+    ed_remove_list = NULL;
+
+    init_hcca_int_table();
+
+    /* Tell the controller where the control and bulk lists are
+     * The lists are empty now. */
+    _ohci->HcControlHeadED = 0;             /* control ED list head                       */
+    _ohci->HcBulkHeadED = 0;                /* bulk ED list head                          */
+
+    _ohci->HcHCCA = (uint32_t)&_hcca;       /* HCCA area                                  */
+
+    /* periodic start 90% of frame interval       */
+    fminterval = 0x2edf;                    /* 11,999                                     */
+    _ohci->HcPeriodicStart = (fminterval*9)/10;
+
+    /* set FSLargestDataPacket, 10,104 for 0x2edf frame interval */
+    fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
+    _ohci->HcFmInterval = fminterval;
+
+    _ohci->HcLSThreshold = 0x628;
+
+    /* start controller operations                */
+    _ohci->HcControl = HCFS_OPER | (0x3 << USBH_HcControl_CBSR_Pos);
+
+    _ohci->HcRhDescriptorA = (_ohci->HcRhDescriptorA | (1 << 9)) & ~USBH_HcRhDescriptorA_PSM_Msk;
+    _ohci->HcRhStatus = USBH_HcRhStatus_LPSC_Msk;
+
+    _ohci->HcInterruptEnable = USBH_HcInterruptEnable_MIE_Msk | USBH_HcInterruptEnable_WDH_Msk | USBH_HcInterruptEnable_SF_Msk;
+
+    /* POTPGT delay is bits 24-31, in 20 ms units.                                         */
+    usbh_delay_ms(20);
+    return 0;
+}
+
+static void ohci_suspend(void)
+{
+    /* set port suspend if connected */
+    if (_ohci->HcRhPortStatus[0] & 0x1)
+        _ohci->HcRhPortStatus[0] = 0x4;
+
+    if (_ohci->HcRhPortStatus[1] & 0x1)
+        _ohci->HcRhPortStatus[1] = 0x4;
+
+    /* enable Device Remote Wakeup */
+    _ohci->HcRhStatus |= USBH_HcRhStatus_DRWE_Msk;
+
+    /* enable USBH RHSC interrupt for system wakeup */
+    _ohci->HcInterruptEnable |=  USBH_HcInterruptEnable_RHSC_Msk | USBH_HcInterruptEnable_RD_Msk;
+
+    /* set Host Controller enter suspend state */
+    _ohci->HcControl = (_ohci->HcControl & ~USBH_HcControl_HCFS_Msk) | (3 << USBH_HcControl_HCFS_Pos);
+}
+
+static void ohci_resume(void)
+{
+    _ohci->HcControl = (_ohci->HcControl & ~USBH_HcControl_HCFS_Msk) | (1 << USBH_HcControl_HCFS_Pos);
+    _ohci->HcControl = (_ohci->HcControl & ~USBH_HcControl_HCFS_Msk) | (2 << USBH_HcControl_HCFS_Pos);
+
+    if (_ohci->HcRhPortStatus[0] & 0x4)
+        _ohci->HcRhPortStatus[0] = 0x8;
+    if (_ohci->HcRhPortStatus[1] & 0x4)
+        _ohci->HcRhPortStatus[1] = 0x8;
+}
+
+static void ohci_shutdown(void)
+{
+    ohci_suspend();
+    DISABLE_OHCI_IRQ();
+    _ohci->HcRhStatus = USBH_HcRhStatus_LPS_Msk;
+}
+
+
+/*
+ *  Quit current trasnfer via UTR or hardware EP.
+ */
+static int ohci_quit_xfer(UTR_T *utr, EP_INFO_T *ep)
+{
+    ED_T       *ed;
+
+    if (utr != NULL)
+    {
+        if (utr->ep == NULL)
+            return USBH_ERR_NOT_FOUND;
+
+        ed = (ED_T *)(utr->ep->hw_pipe);
+
+        if (!ed)
+            return USBH_ERR_NOT_FOUND;
+
+        /* add the endpoint to remove list, it will be removed on the next start of frame */
+        add_to_ED_remove_list(ed);
+        utr->ep->hw_pipe = NULL;
+    }
+
+    if ((ep != NULL) && (ep->hw_pipe != NULL))
+    {
+        ed = (ED_T *)(ep->hw_pipe);
+        /* add the endpoint to remove list, it will be removed on the next start of frame */
+        add_to_ED_remove_list(ed);
+        ep->hw_pipe = NULL;
+    }
+
+    return 0;
+}
+
+uint32_t ed_make_info(UDEV_T *udev, EP_INFO_T *ep)
+{
+    uint32_t  info;
+
+    if (ep == NULL)                             /* is a control endpoint                   */
+    {
+        /* control endpoint direction is from TD  */
+        if (udev->descriptor.bMaxPacketSize0 == 0)   /* is 0 if device descriptor still not obtained. */
+        {
+            if (udev->speed == SPEED_LOW)       /* give a default maximum packet size     */
+                udev->descriptor.bMaxPacketSize0 = 8;
+            else
+                udev->descriptor.bMaxPacketSize0 = 64;
+        }
+        info = (udev->descriptor.bMaxPacketSize0 << 16) /* Control endpoint Maximum Packet Size from device descriptor */
+               | ED_DIR_BY_TD                   /* Direction (Get direction From TD)      */
+               | ED_FORMAT_GENERAL              /* General format                         */
+               | (0 << ED_CTRL_EN_Pos);         /* Endpoint address 0                     */
+    }
+    else                                        /* Other endpoint direction is from endpoint descriptor */
+    {
+        info = (ep->wMaxPacketSize << 16);      /* Maximum Packet Size from endpoint      */
+
+        info |= ((ep->bEndpointAddress & 0xf) << ED_CTRL_EN_Pos);   /* Endpoint Number     */
+
+        if ((ep->bEndpointAddress & EP_ADDR_DIR_MASK) == EP_ADDR_DIR_IN)
+            info |= ED_DIR_IN;
+        else
+            info |= ED_DIR_OUT;
+
+        if ((ep->bmAttributes & EP_ATTR_TT_MASK) == EP_ATTR_TT_ISO)
+            info |= ED_FORMAT_ISO;
+        else
+            info |= ED_FORMAT_GENERAL;
+    }
+
+    info |= ((udev->speed == SPEED_LOW)  ? ED_SPEED_LOW : ED_SPEED_FULL);  /* Speed       */
+    info |= (udev->dev_num);                  /* Function Address                         */
+
+    return info;
+}
+
+static void write_td(TD_T *td, uint32_t info, uint8_t *buff, uint32_t data_len)
+{
+    td->Info = info;
+    td->CBP  = (uint32_t)((!buff || !data_len) ? 0 : buff);
+    td->BE   = (uint32_t)((!buff || !data_len ) ? 0 : (uint32_t)buff + data_len - 1);
+    td->buff_start = td->CBP;
+    // TD_debug("TD [0x%x]: 0x%x, 0x%x, 0x%x\n", (int)td, td->Info, td->CBP, td->BE);
+}
+
+static int ohci_ctrl_xfer(UTR_T *utr)
+{
+    UDEV_T  *udev;
+    ED_T    *ed;
+    TD_T    *td_setup, *td_data, *td_status;
+    uint32_t  info;
+
+    udev = utr->udev;
+
+    /*------------------------------------------------------------------------------------*/
+    /*  Allocate ED and TDs                                                               */
+    /*------------------------------------------------------------------------------------*/
+    td_setup = alloc_ohci_TD(utr);
+
+    if (utr->data_len > 0)
+        td_data = alloc_ohci_TD(utr);
+    else
+        td_data = NULL;
+
+    td_status = alloc_ohci_TD(utr);
+
+    if (td_status == NULL)
+    {
+        free_ohci_TD(td_setup);
+        if (utr->data_len > 0)
+            free_ohci_TD(td_data);
+        return USBH_ERR_MEMORY_OUT;
+    }
+
+    /* Check if there's any transfer pending on this endpoint... */
+    if (udev->ep0.hw_pipe == NULL)
+    {
+        ed = alloc_ohci_ED();
+        if (ed == NULL)
+        {
+            free_ohci_TD(td_setup);
+            free_ohci_TD(td_status);
+            if (utr->data_len > 0)
+                free_ohci_TD(td_data);
+            return USBH_ERR_MEMORY_OUT;
+        }
+    }
+    else
+        ed = (ED_T *)udev->ep0.hw_pipe;
+
+    /*------------------------------------------------------------------------------------*/
+    /* prepare SETUP stage TD                                                             */
+    /*------------------------------------------------------------------------------------*/
+    info = TD_CC | TD_T_DATA0 | TD_TYPE_CTRL;
+    write_td(td_setup, info, (uint8_t *)&utr->setup, 8);
+    td_setup->ed = ed;
+
+    /*------------------------------------------------------------------------------------*/
+    /* prepare DATA stage TD                                                              */
+    /*------------------------------------------------------------------------------------*/
+    if (utr->data_len > 0)
+    {
+        if ((utr->setup.bmRequestType & 0x80) == REQ_TYPE_OUT)
+            info = (TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 | TD_TYPE_CTRL | TD_CTRL_DATA);
+        else
+            info = (TD_CC | TD_R | TD_DP_IN | TD_T_DATA1 | TD_TYPE_CTRL | TD_CTRL_DATA);
+
+        write_td(td_data, info, utr->buff, utr->data_len);
+        td_data->ed = ed;
+        td_setup->NextTD = (uint32_t)td_data;
+        td_setup->next   = td_data;
+        td_data->NextTD  = (uint32_t)td_status;
+        td_data->next    = td_status;
+    }
+    else
+    {
+        td_setup->NextTD = (uint32_t)td_status;
+        td_setup->next = td_status;
+    }
+
+    /*------------------------------------------------------------------------------------*/
+    /* prepare STATUS stage TD                                                            */
+    /*------------------------------------------------------------------------------------*/
+    ed->Info = ed_make_info(udev, NULL);
+    if ((utr->setup.bmRequestType & 0x80) == REQ_TYPE_OUT)
+        info = (TD_CC | TD_DP_IN | TD_T_DATA1 | TD_TYPE_CTRL);
+    else
+        info = (TD_CC | TD_DP_OUT | TD_T_DATA1 | TD_TYPE_CTRL);
+
+    write_td(td_status, info, NULL, 0);
+    td_status->ed = ed;
+    td_status->NextTD = 0;
+    td_status->next = 0;
+
+    /*------------------------------------------------------------------------------------*/
+    /* prepare ED                                                                         */
+    /*------------------------------------------------------------------------------------*/
+    ed->TailP = 0;
+    ed->HeadP = (uint32_t)td_setup;
+    ed->Info = ed_make_info(udev, NULL);
+    ed->NextED = 0;
+
+    //TD_debug("TD SETUP [0x%x]: 0x%x, 0x%x, 0x%x, 0x%x\n", (int)td_setup, td_setup->Info, td_setup->CBP, td_setup->BE, td_setup->NextTD);
+    //if (td_data)
+    //    TD_debug("TD DATA  [0x%x]: 0x%x, 0x%x, 0x%x, 0x%x\n", (int)td_data, td_data->Info, td_data->CBP, td_data->BE, td_data->NextTD);
+    //TD_debug("TD STATUS [0x%x]: 0x%x, 0x%x, 0x%x, 0x%x\n", (int)td_status, td_status->Info, td_status->CBP, td_status->BE, td_status->NextTD);
+    ED_debug("Xfer ED 0x%x: 0x%x 0x%x 0x%x 0x%x\n", (int)ed, ed->Info, ed->TailP, ed->HeadP, ed->NextED);
+
+    if (utr->data_len > 0)
+        utr->td_cnt = 3;
+    else
+        utr->td_cnt = 2;
+
+    utr->ep = &udev->ep0;                   /* driver can find EP from UTR                */
+    udev->ep0.hw_pipe = (void *)ed;         /* driver can find ED from EP                 */
+
+    /*------------------------------------------------------------------------------------*/
+    /*  Start transfer                                                                    */
+    /*------------------------------------------------------------------------------------*/
+    DISABLE_OHCI_IRQ();
+    _ohci->HcControlHeadED = (uint32_t)ed;                   /* Link ED to OHCI           */
+    _ohci->HcControl |= USBH_HcControl_CLE_Msk;              /* enable control list       */
+    ENABLE_OHCI_IRQ();
+    _ohci->HcCommandStatus = USBH_HcCommandStatus_CLF_Msk;   /* start Control list        */
+
+    return 0;
+}
+
+static int ohci_bulk_xfer(UTR_T *utr)
+{
+    UDEV_T     *udev = utr->udev;
+    EP_INFO_T  *ep = utr->ep;
+    ED_T       *ed;
+    TD_T       *td, *td_p, *td_list = NULL;
+    uint32_t   info;
+    uint32_t   data_len, xfer_len;
+    int8_t     bIsNewED = 0;
+    uint8_t    *buff;
+
+    /*------------------------------------------------------------------------------------*/
+    /*  Check if there's uncompleted transfer on this endpoint...                         */
+    /*  Prepare ED                                                                        */
+    /*------------------------------------------------------------------------------------*/
+    info = ed_make_info(udev, ep);
+
+    /* Check if there's any transfer pending on this endpoint... */
+    ed = (ED_T *)_ohci->HcBulkHeadED;       /* get the head of bulk endpoint list         */
+    while (ed != NULL)
+    {
+        if (ed->Info == info)               /* have transfer of this EP not completed?    */
+        {
+            if ((ed->HeadP & 0xFFFFFFF0) != (ed->TailP & 0xFFFFFFF0))
+                return USBH_ERR_OHCI_EP_BUSY;     /* endpoint is busy                     */
+            else
+                break;                      /* ED already there...                        */
+        }
+        ed = (ED_T *)ed->NextED;
+    }
+
+    if (ed == NULL)
+    {
+        bIsNewED = 1;
+        ed = alloc_ohci_ED();               /* allocate an Endpoint Descriptor            */
+        if (ed == NULL)
+            return USBH_ERR_MEMORY_OUT;
+        ed->Info = info;
+        ed->HeadP = 0;
+        ED_debug("Link BULK ED 0x%x: 0x%x 0x%x 0x%x 0x%x\n", (int)ed, ed->Info, ed->TailP, ed->HeadP, ed->NextED);
+    }
+
+    ep->hw_pipe = (void *)ed;
+
+    /*------------------------------------------------------------------------------------*/
+    /*  Prepare TDs                                                                       */
+    /*------------------------------------------------------------------------------------*/
+    utr->td_cnt = 0;
+    data_len = utr->data_len;
+    buff = utr->buff;
+
+    do
+    {
+        if ((ep->bEndpointAddress & EP_ADDR_DIR_MASK) == EP_ADDR_DIR_OUT)
+            info = (TD_CC | TD_R | TD_DP_OUT | TD_TYPE_BULK);
+        else
+            info = (TD_CC | TD_R | TD_DP_IN | TD_TYPE_BULK);
+
+        info &= ~(1 << 25);                 /* Data toggle from ED toggleCarry bit        */
+
+        if (data_len > 4096)                /* maximum transfer length is 4K for each TD  */
+            xfer_len = 4096;
+        else
+            xfer_len = data_len;            /* remaining data length < 4K                 */
+
+        td = alloc_ohci_TD(utr);            /* allocate a TD                              */
+        if (td == NULL)
+            goto mem_out;
+        /* fill this TD                               */
+        write_td(td, info, buff, xfer_len);
+        td->ed = ed;
+
+        utr->td_cnt++;                      /* increase TD count, for recalim counter     */
+
+        buff += xfer_len;                   /* advanced buffer pointer                    */
+        data_len -= xfer_len;
+
+        /* chain to end of TD list */
+        if (td_list == NULL)
+        {
+            td_list = td;
+        }
+        else
+        {
+            td_p = td_list;
+            while (td_p->NextTD != 0)
+                td_p = (TD_T *)td_p->NextTD;
+            td_p->NextTD = (uint32_t)td;
+        }
+
+    }
+    while (data_len > 0);
+
+    /*------------------------------------------------------------------------------------*/
+    /*  Start transfer                                                                    */
+    /*------------------------------------------------------------------------------------*/
+    utr->status = 0;
+    DISABLE_OHCI_IRQ();
+    ed->HeadP = (ed->HeadP & 0x2) | (uint32_t)td_list;       /* keep toggleCarry bit      */
+    if (bIsNewED)
+    {
+        ed->HeadP = (uint32_t)td_list;
+        /* Link ED to OHCI Bulk List */
+        ed->NextED = _ohci->HcBulkHeadED;
+        _ohci->HcBulkHeadED = (uint32_t)ed;
+    }
+    ENABLE_OHCI_IRQ();
+    _ohci->HcControl |= USBH_HcControl_BLE_Msk;              /* enable bulk list          */
+    _ohci->HcCommandStatus = USBH_HcCommandStatus_BLF_Msk;   /* start bulk list           */
+
+    return 0;
+
+mem_out:
+    while (td_list != NULL)
+    {
+        td = td_list;
+        td_list = (TD_T *)td_list->NextTD;
+        free_ohci_TD(td);
+    }
+    free_ohci_ED(ed);
+    return USBH_ERR_MEMORY_OUT;
+}
+
+static int ohci_int_xfer(UTR_T *utr)
+{
+    UDEV_T     *udev = utr->udev;
+    EP_INFO_T  *ep = utr->ep;
+    ED_T       *ed, *ied;
+    TD_T       *td, *td_new;
+    uint32_t   info;
+    int8_t     bIsNewED = 0;
+
+    if (utr->data_len > 64)             /* USB 1.1 interrupt transfer maximum packet size is 64 */
+        return USBH_ERR_INVALID_PARAM;
+
+    td_new = alloc_ohci_TD(utr);        /* allocate a TD for dummy TD                     */
+    if (td_new == NULL)
+        return USBH_ERR_MEMORY_OUT;
+
+    ied = get_int_tree_head_node(ep->bInterval);  /* get head node of this interval       */
+
+    /*------------------------------------------------------------------------------------*/
+    /*  Find if this ED was already in the list                                           */
+    /*------------------------------------------------------------------------------------*/
+    info = ed_make_info(udev, ep);
+    ed = ied;
+    while (ed != NULL)
+    {
+        if (ed->Info == info)
+            break;                          /* Endpoint found                             */
+        ed = (ED_T *)ed->NextED;
+    }
+
+    if (ed == NULL)                         /* ED not found, create it                    */
+    {
+        bIsNewED = 1;
+        ed = alloc_ohci_ED();               /* allocate an Endpoint Descriptor            */
+        if (ed == NULL)
+            return USBH_ERR_MEMORY_OUT;
+        ed->Info = info;
+        ed->HeadP = 0;
+        ed->bInterval = ep->bInterval;
+
+        td = alloc_ohci_TD(NULL);           /* allocate the initial  dummy TD for ED      */
+        if (td == NULL)
+        {
+            free_ohci_ED(ed);
+            free_ohci_TD(td_new);
+            return USBH_ERR_MEMORY_OUT;
+        }
+        ed->HeadP = (uint32_t)td;           /* Let both HeadP and TailP point to dummy TD */
+        ed->TailP = ed->HeadP;
+    }
+    else
+    {
+        td = (TD_T *)(ed->TailP & ~0xf);    /* TailP always point to the dummy TD         */
+    }
+    ep->hw_pipe = (void *)ed;
+
+    /*------------------------------------------------------------------------------------*/
+    /*  Prepare TD                                                                        */
+    /*------------------------------------------------------------------------------------*/
+    if ((ep->bEndpointAddress & EP_ADDR_DIR_MASK) == EP_ADDR_DIR_OUT)
+        info = (TD_CC | TD_R | TD_DP_OUT | TD_TYPE_INT);
+    else
+        info = (TD_CC | TD_R | TD_DP_IN | TD_TYPE_INT);
+
+    /* Keep data toggle                               */
+    info = (info & ~(1<<25)) | (td->Info & (1<<25));
+
+    /* fill this TD                                   */
+    write_td(td, info, utr->buff, utr->data_len);
+    td->ed = ed;
+    td->NextTD = (uint32_t)td_new;
+    td->utr = utr;
+    utr->td_cnt = 1;                    /* increase TD count, for recalim counter     */
+    utr->status = 0;
+
+    /*------------------------------------------------------------------------------------*/
+    /*  Hook ED and TD list to HCCA interrupt table                                       */
+    /*------------------------------------------------------------------------------------*/
+    DISABLE_OHCI_IRQ();
+
+    ed->TailP = (uint32_t)td_new;
+    if (bIsNewED)
+    {
+        /* Add to list of the same interval */
+        ed->NextED = ied->NextED;
+        ied->NextED = (uint32_t)ed;
+    }
+
+    ENABLE_OHCI_IRQ();
+
+    //printf("Link INT ED 0x%x: 0x%x 0x%x 0x%x 0x%x\n", (int)ed, ed->Info, ed->TailP, ed->HeadP, ed->NextED);
+
+    _ohci->HcControl |= USBH_HcControl_PLE_Msk;              /* periodic list enable      */
+    return 0;
+}
+
+static int ohci_iso_xfer(UTR_T *utr)
+{
+    UDEV_T     *udev = utr->udev;
+    EP_INFO_T  *ep = utr->ep;
+    ED_T       *ed, *ied;
+    TD_T       *td, *td_list, *last_td;
+    int        i;
+    uint32_t   info;
+    uint32_t   buff_addr;
+    int8_t     bIsNewED = 0;
+
+    ied = get_int_tree_head_node(ep->bInterval);  /* get head node of this interval       */
+
+    /*------------------------------------------------------------------------------------*/
+    /*  Find if this ED was already in the list                                           */
+    /*------------------------------------------------------------------------------------*/
+    info = ed_make_info(udev, ep);
+    ed = ied;
+    while (ed != NULL)
+    {
+        if (ed->Info == info)
+            break;                          /* Endpoint found                             */
+        ed = (ED_T *)ed->NextED;
+    }
+
+    if (ed == NULL)                         /* ED not found, create it                    */
+    {
+        bIsNewED = 1;
+        ed = alloc_ohci_ED();               /* allocate an Endpoint Descriptor            */
+        if (ed == NULL)
+            return USBH_ERR_MEMORY_OUT;
+        ed->Info = info;
+        ed->HeadP = 0;
+        ed->bInterval = ep->bInterval;
+    }
+    else
+
+        ep->hw_pipe = (void *)ed;
+
+    /*------------------------------------------------------------------------------------*/
+    /*  Prepare TDs                                                                       */
+    /*------------------------------------------------------------------------------------*/
+    if (utr->bIsoNewSched)                   /* Is the starting of isochronous streaming?  */
+        ed->next_sf = _hcca.frame_no + OHCI_ISO_DELAY;
+
+    utr->td_cnt = 0;
+    utr->iso_sf = ed->next_sf;
+
+    last_td = NULL;
+    td_list = NULL;
+
+    for (i = 0; i < IF_PER_UTR; i++)
+    {
+        utr->iso_status[i] = USBH_ERR_NOT_ACCESS1;
+
+        td = alloc_ohci_TD(utr);            /* allocate a TD                              */
+        if (td == NULL)
+            goto mem_out;
+        /* fill this TD                               */
+        buff_addr = (uint32_t)(utr->iso_buff[i]);
+        td->Info = (TD_CC | TD_TYPE_ISO) | ed->next_sf;
+        ed->next_sf += get_ohci_interval(ed->bInterval);
+        td->CBP  = buff_addr & ~0xFFF;
+        td->BE   = buff_addr + utr->iso_xlen[i] - 1;
+        td->PSW[0] = 0xE000 | (buff_addr & 0xFFF);
+
+        td->ed = ed;
+        utr->td_cnt++;                      /* increase TD count, for reclaim counter     */
+
+        /* chain to end of TD list */
+        if (td_list == NULL)
+            td_list = td;
+        else
+            last_td->NextTD = (uint32_t)td;
+
+        last_td = td;
+    };
+
+    /*------------------------------------------------------------------------------------*/
+    /*  Hook ED and TD list to HCCA interrupt table                                       */
+    /*------------------------------------------------------------------------------------*/
+    utr->status = 0;
+    DISABLE_OHCI_IRQ();
+
+    if ((ed->HeadP & ~0x3) == 0)
+        ed->HeadP = (ed->HeadP & 0x2) | (uint32_t)td_list;   /* keep toggleCarry bit      */
+    else
+    {
+        /* find the tail of TDs under this ED */
+        td = (TD_T *)(ed->HeadP & ~0x3);
+        while (td->NextTD != 0)
+        {
+            td = (TD_T *)td->NextTD;
+        }
+        td->NextTD = (uint32_t)td_list;
+    }
+
+    if (bIsNewED)
+    {
+        /* Add to list of the same interval */
+        ed->NextED = ied->NextED;
+        ied->NextED = (uint32_t)ed;
+    }
+
+    ENABLE_OHCI_IRQ();
+    ED_debug("Link ISO ED 0x%x: 0x%x 0x%x 0x%x 0x%x\n", (int)ed, ed->Info, ed->TailP, ed->HeadP, ed->NextED);
+    _ohci->HcControl |= USBH_HcControl_PLE_Msk | USBH_HcControl_IE_Msk;  /* enable periodic list and isochronous transfer  */
+
+    return 0;
+
+mem_out:
+    while (td_list != NULL)
+    {
+        td = td_list;
+        td_list = (TD_T *)td_list->NextTD;
+        free_ohci_TD(td);
+    }
+    free_ohci_ED(ed);
+    return USBH_ERR_MEMORY_OUT;
+}
+
+static UDEV_T * ohci_find_device_by_port(int port)
+{
+    UDEV_T  *udev;
+
+    udev = g_udev_list;
+    while (udev != NULL)
+    {
+        if ((udev->parent == NULL) && (udev->port_num == port) &&
+                ((udev->speed == SPEED_LOW) || (udev->speed == SPEED_FULL)))
+            return udev;
+        udev = udev->next;
+    }
+    return NULL;
+}
+
+static int ohci_rh_port_reset(int port)
+{
+    int       retry;
+    int       reset_time;
+    uint32_t  t0;
+
+    reset_time = usbh_tick_from_millisecond(PORT_RESET_TIME_MS);
+
+    for (retry = 0; retry < PORT_RESET_RETRY; retry++)
+    {
+        _ohci->HcRhPortStatus[port] = USBH_HcRhPortStatus_PRS_Msk;
+
+        t0 = usbh_get_ticks();
+        while (usbh_get_ticks() - t0 < (reset_time)+1)
+        {
+            /*
+             *  If device is disconnected or port enabled, we can stop port reset.
+             */
+            if (((_ohci->HcRhPortStatus[port] & USBH_HcRhPortStatus_CCS_Msk) == 0) ||
+                    ((_ohci->HcRhPortStatus[port] & (USBH_HcRhPortStatus_PES_Msk | USBH_HcRhPortStatus_CCS_Msk)) == (USBH_HcRhPortStatus_PES_Msk | USBH_HcRhPortStatus_CCS_Msk)))
+                goto port_reset_done;
+        }
+        reset_time += PORT_RESET_RETRY_INC_MS;
+    }
+
+    USB_debug("OHCI port %d - port reset failed!\n", port+1);
+    return USBH_ERR_PORT_RESET;
+
+port_reset_done:
+    if ((_ohci->HcRhPortStatus[port] & USBH_HcRhPortStatus_CCS_Msk) == 0)   /* check again if device disconnected */
+    {
+        _ohci->HcRhPortStatus[port] = USBH_HcRhPortStatus_CSC_Msk;         /* clear CSC */
+        return USBH_ERR_DISCONNECTED;
+    }
+    return USBH_OK;                                                        /* port reset success */
+}
+
+static int ohci_rh_polling(void)
+{
+    int       i, change = 0;
+    UDEV_T    *udev;
+    int       ret;
+
+    for (i = 0; i < 2; i++)
+    {
+
+        /* clear unwanted port change status */
+        _ohci->HcRhPortStatus[i] = USBH_HcRhPortStatus_OCIC_Msk | USBH_HcRhPortStatus_PRSC_Msk |
+                                   USBH_HcRhPortStatus_PSSC_Msk | USBH_HcRhPortStatus_PESC_Msk;
+
+        if ((_ohci->HcRhPortStatus[i] & USBH_HcRhPortStatus_CSC_Msk) == 0)
+            continue;
+
+        /*--------------------------------------------------------------------------------*/
+        /*  connect status change                                                         */
+        /*--------------------------------------------------------------------------------*/
+
+        _ohci->HcRhPortStatus[i] = USBH_HcRhPortStatus_CSC_Msk;     /* clear CSC          */
+
+        if (_ohci->HcRhPortStatus[i] & USBH_HcRhPortStatus_CCS_Msk)
+        {
+            /*----------------------------------------------------------------------------*/
+            /*  First of all, check if there's any previously connected device.           */
+            /*----------------------------------------------------------------------------*/
+            while (1)
+            {
+                udev = ohci_find_device_by_port(i+1);
+                if (udev == NULL)
+                    break;
+                usbh_disconnect_device(udev);
+            }
+
+            if (ohci_rh_port_reset(i) != USBH_OK)
+                continue;
+
+            /*
+             *  Port reset success...
+             */
+            udev = alloc_device();
+            if (udev == NULL)
+                continue;
+
+            udev->parent = NULL;
+            udev->port_num = i+1;
+            if (_ohci->HcRhPortStatus[i] & USBH_HcRhPortStatus_LSDA_Msk)
+                udev->speed = SPEED_LOW;
+            else
+                udev->speed = SPEED_FULL;
+            udev->hc_driver = &ohci_driver;
+
+            ret = usbh_connect_device(udev);
+            if (ret < 0)
+            {
+                USB_error("connect_device error! [%d]\n", ret);
+                free_device(udev);
+            }
+
+            change = 1;
+        }
+        else
+        {
+            /*
+             *  Device disconnected
+             */
+            while (1)
+            {
+                udev = ohci_find_device_by_port(i+1);
+                if (udev == NULL)
+                    break;
+                usbh_disconnect_device(udev);
+            }
+            change = 1;
+        }
+    }
+    return change;
+}
+
+void td_done(TD_T *td)
+{
+    UTR_T       *utr = td->utr;
+    uint32_t    info;
+    int         cc;
+
+    info = td->Info;
+
+    TD_debug("td_done: 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", (int)td, td->Info, td->CBP, td->NextTD, td->BE);
+
+    /* ISO ... drivers see per-TD length/status */
+    if ((info & TD_TYPE_Msk) == TD_TYPE_ISO)
+    {
+        uint16_t    sf;
+        int         idx;
+
+        sf = info & 0xFFFF;
+        idx = ((sf + 0x10000 - utr->iso_sf) & 0xFFFF) / get_ohci_interval(td->ed->bInterval);
+        if (idx >= IF_PER_UTR)
+        {
+            USB_error("ISO invalid index!! %d, %d\n", sf, utr->iso_sf);
+            goto td_out;
+        }
+
+        cc = (td->PSW[0] >> 12) & 0xF;
+        if (cc == 0xF)                      /* this frame was not transferred             */
+        {
+            USB_debug("ISO F %d N/A!\n", sf);
+            utr->iso_status[idx] = USBH_ERR_SCH_OVERRUN;
+            goto td_out;
+        }
+        if ((cc != 0) && (cc != CC_DATA_UNDERRUN))
+        {
+            utr->iso_status[idx] = USBH_ERR_CC_NO_ERR - cc;
+            goto td_out;
+        }
+        utr->iso_status[idx] = 0;
+        utr->iso_xlen[idx] = td->PSW[0] & 0x7FF;
+    }
+    else
+    {
+        cc = TD_CC_GET(info);
+
+        /* short packet is fine */
+        if ((cc != CC_NOERROR) && (cc != CC_DATA_UNDERRUN))
+        {
+            USB_error("TD error, CC = 0x%x\n", cc);
+            if (cc == CC_STALL)
+                utr->status = USBH_ERR_STALL;
+            else
+                utr->status = USBH_ERR_TRANSFER;
+        }
+
+        switch (info & TD_TYPE_Msk)
+        {
+        case TD_TYPE_CTRL:
+            if (info & TD_CTRL_DATA)
+            {
+                if (td->CBP == 0)
+                    utr->xfer_len += td->BE - td->buff_start + 1;
+                else
+                    utr->xfer_len += td->CBP - td->buff_start;
+            }
+            break;
+
+        case TD_TYPE_BULK:
+        case TD_TYPE_INT:
+            if (td->CBP == 0)
+                utr->xfer_len += td->BE - td->buff_start + 1;
+            else
+                utr->xfer_len += td->CBP - td->buff_start;
+            break;
+        }
+    }
+
+td_out:
+
+    utr->td_cnt--;
+
+    /* If all TDs are done, call-back to requester. */
+    if (utr->td_cnt == 0)
+    {
+        utr->bIsTransferDone = 1;
+        if (utr->func)
+            utr->func(utr);
+    }
+}
+
+/* in IRQ context */
+static void remove_ed()
+{
+    ED_T      *ed, *ed_p, *ied;
+    TD_T      *td, *td_next;
+    UTR_T     *utr;
+    int       found;
+
+    while (ed_remove_list != NULL)
+    {
+        ED_debug("Remove ED: 0x%x, %d\n", (int)ed_remove_list, ed_remove_list->bInterval);
+        ed_p = ed_remove_list;
+        found = 0;
+
+        /*--------------------------------------------------------------------------------*/
+        /*  Remove endpoint from Control List if found                                    */
+        /*--------------------------------------------------------------------------------*/
+        if ((ed_p->Info & ED_EP_ADDR_Msk) == 0)
+        {
+            if (_ohci->HcControlHeadED == (uint32_t)ed_p)
+            {
+                _ohci->HcControlHeadED = (uint32_t)ed_p->NextED;
+                found = 1;
+            }
+            else
+            {
+                ed = (ED_T *)_ohci->HcControlHeadED;
+                while (ed != NULL)
+                {
+                    if (ed->NextED == (uint32_t)ed_p)
+                    {
+                        ed->NextED = ed_p->NextED;
+                        found = 1;
+                    }
+                    ed = (ED_T *)ed->NextED;
+                }
+            }
+        }
+
+        /*--------------------------------------------------------------------------------*/
+        /*  Remove INT or ISO endpoint from HCCA interrupt table                          */
+        /*--------------------------------------------------------------------------------*/
+        else if (ed_p->bInterval > 0)
+        {
+            ied = get_int_tree_head_node(ed_p->bInterval);
+
+            ed = ied;
+            while (ed != NULL)
+            {
+                if (ed->NextED == (uint32_t)ed_p)
+                {
+                    ed->NextED = ed_p->NextED;
+                    found = 1;
+                    break;
+                }
+                ed = (ED_T *)ed->NextED;
+            }
+        }
+
+        /*--------------------------------------------------------------------------------*/
+        /*  Remove endpoint from Bulk List if found                                       */
+        /*--------------------------------------------------------------------------------*/
+        else
+        {
+            if (_ohci->HcBulkHeadED == (uint32_t)ed_p)
+            {
+                ed = (ED_T *)ed_p;
+                _ohci->HcBulkHeadED = ed_p->NextED;
+                found = 1;
+            }
+            else
+            {
+                ed = (ED_T *)_ohci->HcBulkHeadED;
+                while (ed != NULL)
+                {
+                    if (ed->NextED == (uint32_t)ed_p)
+                    {
+                        ed->NextED = ed_p->NextED;
+                        found = 1;
+                    }
+                    ed = (ED_T *)ed->NextED;
+                }
+            }
+        }
+
+        /*--------------------------------------------------------------------------------*/
+        /*  Remove and free all TDs under this endpoint                                   */
+        /*--------------------------------------------------------------------------------*/
+        if (found)
+        {
+            td = (TD_T *)(ed_p->HeadP & ~0x3);
+            if (td != NULL)
+            {
+                while (td != NULL)
+                {
+                    utr = td->utr;
+                    td_next = (TD_T *)td->NextTD;
+                    free_ohci_TD(td);
+                    td = td_next;
+
+                    utr->td_cnt--;
+                    if (utr->td_cnt == 0)
+                    {
+                        utr->status = USBH_ERR_ABORT;
+                        utr->bIsTransferDone = 1;
+                        if (utr->func)
+                            utr->func(utr);
+                    }
+                }
+            }
+        }
+
+        /*
+         *  Done. Remove this ED from [ed_remove_list] and free it.
+         */
+        ed_remove_list = ed_p->next;
+        free_ohci_ED(ed_p);
+    }
+}
+
+
+//static irqreturn_t ohci_irq (struct usb_hcd *hcd)
+void USBH_IRQHandler(void)
+{
+    TD_T       *td, *td_prev, *td_next;
+    uint32_t   int_sts;
+
+    int_sts = _ohci->HcInterruptStatus;
+
+    //USB_debug("ohci int_sts = 0x%x\n", int_sts);
+
+    if ((_ohci->HcInterruptEnable & USBH_HcInterruptEnable_SF_Msk) &&
+            (int_sts & USBH_HcInterruptStatus_SF_Msk))
+    {
+        int_sts &= ~USBH_HcInterruptStatus_SF_Msk;
+
+        _ohci->HcInterruptDisable = USBH_HcInterruptDisable_SF_Msk;
+        remove_ed();
+        _ohci->HcInterruptStatus = USBH_HcInterruptStatus_SF_Msk;
+    }
+
+    if (int_sts & USBH_HcInterruptStatus_WDH_Msk)
+    {
+        //printf("!%02x\n", _ohci->HcFmNumber & 0xff);
+        int_sts &= ~USBH_HcInterruptStatus_WDH_Msk;
+        /*
+         *  reverse done list
+         */
+        td = (TD_T *)(_hcca.done_head & TD_ADDR_MASK);
+        _hcca.done_head = 0;
+        td_prev = NULL;
+        _ohci->HcInterruptStatus = USBH_HcInterruptStatus_WDH_Msk;
+
+        while (td != NULL)
+        {
+            //TD_debug("Done list TD 0x%x => 0x%x\n", (int)td, (int)td->NextTD);
+            td_next = (TD_T *)(td->NextTD & TD_ADDR_MASK);
+            td->NextTD = (uint32_t)td_prev;
+            td_prev = td;
+            td = td_next;
+        }
+        td = td_prev;               /* first TD of the reversed done list */
+
+        /*
+         *  reclaim TDs
+         */
+        while (td != NULL)
+        {
+            TD_debug("Reclaim TD 0x%x, next 0x%x\n", (int)td, td->NextTD);
+            td_next = (TD_T *)td->NextTD;
+            td_done(td);
+            free_ohci_TD(td);
+            td = td_next;
+        }
+    }
+
+    if (int_sts & USBH_HcInterruptStatus_RHSC_Msk)
+    {
+        _ohci->HcInterruptDisable = USBH_HcInterruptDisable_RHSC_Msk;
+    }
+
+    _ohci->HcInterruptStatus = int_sts;
+}
+
+#ifdef ENABLE_DEBUG_MSG
+
+void dump_ohci_int_table()
+{
+    int    i;
+    ED_T   *ed;
+
+    for (i = 0; i < 32; i++)
+//    for (i = 0; i < 1; i++)
+
+    {
+        USB_debug("%02d: ", i);
+
+        ed = (ED_T *)_hcca.int_table[i];
+
+        while (ed != NULL)
+        {
+            USB_debug("0x%x (0x%x) => ", (int)ed, ed->HeadP);
+            ed = (ED_T *)ed->NextED;
+        }
+        rt_kprintf("0\n");
+    }
+}
+
+void dump_ohci_regs()
+{
+    USB_debug("Dump OCHI registers:\n");
+    USB_debug("    HcRevision         = 0x%x\n", _ohci->HcRevision);
+    USB_debug("    HcControl          = 0x%x\n", _ohci->HcControl);
+    USB_debug("    HcCommandStatus    = 0x%x\n", _ohci->HcCommandStatus);
+    USB_debug("    HcInterruptStatus  = 0x%x\n", _ohci->HcInterruptStatus);
+    USB_debug("    HcInterruptEnable  = 0x%x\n", _ohci->HcInterruptEnable);
+    USB_debug("    HcInterruptDisable = 0x%x\n", _ohci->HcInterruptDisable);
+    USB_debug("    HcHCCA             = 0x%x\n", _ohci->HcHCCA);
+    USB_debug("    HcPeriodCurrentED  = 0x%x\n", _ohci->HcPeriodCurrentED);
+    USB_debug("    HcControlHeadED    = 0x%x\n", _ohci->HcControlHeadED);
+    USB_debug("    HcControlCurrentED = 0x%x\n", _ohci->HcControlCurrentED);
+    USB_debug("    HcBulkHeadED       = 0x%x\n", _ohci->HcBulkHeadED);
+    USB_debug("    HcBulkCurrentED    = 0x%x\n", _ohci->HcBulkCurrentED);
+    USB_debug("    HcDoneHead         = 0x%x\n", _ohci->HcDoneHead);
+    USB_debug("    HcFmInterval       = 0x%x\n", _ohci->HcFmInterval);
+    USB_debug("    HcFmRemaining      = 0x%x\n", _ohci->HcFmRemaining);
+    USB_debug("    HcFmNumber         = 0x%x\n", _ohci->HcFmNumber);
+    USB_debug("    HcPeriodicStart    = 0x%x\n", _ohci->HcPeriodicStart);
+    USB_debug("    HcLSThreshold      = 0x%x\n", _ohci->HcLSThreshold);
+    USB_debug("    HcRhDescriptorA    = 0x%x\n", _ohci->HcRhDescriptorA);
+    USB_debug("    HcRhDescriptorB    = 0x%x\n", _ohci->HcRhDescriptorB);
+    USB_debug("    HcRhStatus         = 0x%x\n", _ohci->HcRhStatus);
+    USB_debug("    HcRhPortStatus0    = 0x%x\n", _ohci->HcRhPortStatus[0]);
+    USB_debug("    HcRhPortStatus1    = 0x%x\n", _ohci->HcRhPortStatus[1]);
+    USB_debug("    HcPhyControl       = 0x%x\n", _ohci->HcPhyControl);
+    USB_debug("    HcMiscControl      = 0x%x\n", _ohci->HcMiscControl);
+}
+
+void dump_ohci_ports()
+{
+    USB_debug("_ohci port0=0x%x, port1=0x%x\n", _ohci->HcRhPortStatus[0], _ohci->HcRhPortStatus[1]);
+}
+
+#endif  // ENABLE_DEBUG_MSG
+
+HC_DRV_T  ohci_driver =
+{
+    ohci_init,               /* init               */
+    ohci_shutdown,           /* shutdown           */
+    ohci_suspend,            /* suspend            */
+    ohci_resume,             /* resume             */
+    ohci_ctrl_xfer,          /* ctrl_xfer          */
+    ohci_bulk_xfer,          /* bulk_xfer          */
+    ohci_int_xfer,           /* int_xfer           */
+    ohci_iso_xfer,           /* iso_xfer           */
+    ohci_quit_xfer,          /* quit_xfer          */
+    ohci_rh_port_reset,      /* rthub_port_reset   */
+    ohci_rh_polling          /* rthub_polling      */
+};
+
+/// @endcond HIDDEN_SYMBOLS
+
+/*** (C) COPYRIGHT 2019-2020 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/libraries/m2354/USBHostLib/src/usb_core.c b/bsp/nuvoton/libraries/m2354/USBHostLib/src/usb_core.c
new file mode 100644
index 0000000000..fa11e1d357
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/USBHostLib/src/usb_core.c
@@ -0,0 +1,278 @@
+/**************************************************************************//**
+ * @file     usb_core.c
+ * @version  V1.10
+ * @brief   USB Host library core.
+ *
+ * @note
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#include 
+#include 
+#include 
+
+#include "NuMicro.h"
+
+#include "usb.h"
+#include "hub.h"
+
+
+/// @cond HIDDEN_SYMBOLS
+
+USBH_T     *_ohci;
+
+static UDEV_DRV_T *  _drivers[MAX_UDEV_DRIVER];
+static CONN_FUNC  *g_conn_func, *g_disconn_func;
+
+/// @endcond HIDDEN_SYMBOLS
+
+/**
+  * @brief       Initialize M2354 USB Host controller and USB stack.
+  *
+  * @return      None.
+  */
+void  usbh_core_init()
+{
+    if((__PC() & NS_OFFSET) == NS_OFFSET)
+    {
+        _ohci = USBH_NS;
+    }
+    else
+    {
+        _ohci = USBH;
+    }
+
+    DISABLE_OHCI_IRQ();
+
+    memset(_drivers, 0, sizeof(_drivers));
+
+    g_conn_func = NULL;
+    g_disconn_func = NULL;
+
+ //   usbh_hub_init();
+
+    usbh_memory_init();
+
+    _ohci->HcPhyControl &= ~USBH_HcPhyControl_STBYEN_Msk; /* Never enter the standby mode */
+
+    _ohci->HcMiscControl |= USBH_HcMiscControl_OCAL_Msk; /* Over-current active low */
+    //_ohci->HcMiscControl &= ~USBH_HcMiscControl_OCAL_Msk; /* Over-current active high */
+
+#ifdef ENABLE_OHCI
+    ohci_driver.init();
+    ENABLE_OHCI_IRQ();
+#endif
+}
+
+/**
+  * @brief    Let USB stack polls all root hubs. If there's any hub port
+  *           change found, USB stack will manage the hub events in this function call.
+  *           In this function, USB stack enumerates newly connected devices and remove staff
+  *           of disconnected devices. User's application should periodically invoke this
+  *           function.
+  * @return   There's hub port change or not.
+  * @retval   0   No any hub port status changes found.
+  * @retval   1   There's hub port status changes.
+  */
+int  usbh_polling_root_hubs(void)
+{
+    int   ret, change = 0;
+
+#ifdef ENABLE_OHCI
+    do
+    {
+        ret = ohci_driver.rthub_polling();
+        if (ret)
+            change = 1;
+    }
+    while (ret == 1);
+#endif
+
+    return change;
+}
+
+
+/**
+  * @brief    Force to quit an endpoint transfer.
+  * @param[in]  udev     The USB device.
+  * @param[in]  ep       The endpoint to be quit.
+  * @retval   0     Transfer success
+  * @retval   < 0   Failed. Refer to error code definitions.
+  */
+int usbh_quit_xfer(UDEV_T *udev, EP_INFO_T *ep)
+{
+    return udev->hc_driver->quit_xfer(NULL, ep);
+}
+
+int usbh_connect_device(UDEV_T *udev)
+{
+    usbh_delay_ms(100);                   /* initially, give 100 ms delay               */
+
+    if (g_conn_func)
+        g_conn_func(udev, 0);
+    
+    return 0;
+}
+
+
+void usbh_disconnect_device(UDEV_T *udev)
+{
+    USB_debug("disconnect device...\n");
+
+    if (g_disconn_func)
+        g_disconn_func(udev, 0);
+
+    
+#if 1    //CHECK: Maybe create a new API to quit_xfer and free udev for application    
+    usbh_quit_xfer(udev, &(udev->ep0));    /* Quit control transfer if hw_pipe is not NULL.  */
+
+    /* remove device from global device list */
+//    free_dev_address(udev->dev_num);
+    free_device(udev);
+
+//    usbh_memory_used();
+#endif
+}
+
+/**
+  * @brief    Install device connect and disconnect callback function.
+  *
+  * @param[in]  conn_func       Device connect callback function.
+  * @param[in]  disconn_func    Device disconnect callback function.
+  * @return      None.
+  */
+void usbh_install_conn_callback(CONN_FUNC *conn_func, CONN_FUNC *disconn_func)
+{
+    g_conn_func = conn_func;
+    g_disconn_func = disconn_func;
+}
+
+int usbh_reset_port(UDEV_T *udev)
+{
+    if (udev->parent == NULL)
+    {
+        if (udev->hc_driver)
+            return udev->hc_driver->rthub_port_reset(udev->port_num-1);
+        else
+            return USBH_ERR_NOT_FOUND;
+    }
+    else
+    {
+        return udev->parent->port_reset(udev->parent, udev->port_num);
+    }
+}
+
+/**
+  * @brief    Force to quit an UTR transfer.
+  * @param[in]  utr    The UTR transfer to be quit.
+  * @retval   0     Transfer success
+  * @retval   < 0   Failed. Refer to error code definitions.
+  */
+int usbh_quit_utr(UTR_T *utr)
+{
+    if(!utr || !utr->udev)
+        return USBH_ERR_NOT_FOUND;
+
+    return utr->udev->hc_driver->quit_xfer(utr, NULL);
+}
+
+/**
+  * @brief    Execute an USB request in control transfer. This function returns after the request
+  *           was done or aborted.
+  * @param[in]  udev            The target USB device.
+  * @param[in]  bmRequestType   Characteristics of request
+  * @param[in]  bRequest        Specific request
+  * @param[in]  wValue          Word-sized field that varies according to request
+  * @param[in]  wIndex          Word-sized field that varies according to request
+  * @param[in]  wLength         Number of bytes to transfer if there is a Data stage
+  * @param[in]  buff            Data buffer used in data stage
+  * @param[out] xfer_len        Transmitted/received length of data
+  * @param[in]  timeout         Time-out limit (in 10ms - timer tick) of this transfer
+  * @retval   0     Transfer success
+  * @retval   < 0   Transfer failed. Refer to error code definitions.
+  */
+int usbh_ctrl_xfer(UDEV_T *udev, uint8_t bmRequestType, uint8_t bRequest, uint16_t wValue, uint16_t wIndex,
+                   uint16_t wLength, uint8_t *buff, uint32_t *xfer_len, uint32_t timeout)
+{
+    UTR_T      *utr;
+    uint32_t   t0, timeout_tick;
+    int        status;
+
+    *xfer_len = 0;
+
+    //if (check_device(udev))
+    //    return USBH_ERR_INVALID_PARAM;
+
+    utr = alloc_utr(udev);
+    if (utr == NULL)
+        return USBH_ERR_MEMORY_OUT;
+
+    utr->setup.bmRequestType = bmRequestType;
+    utr->setup.bRequest   = bRequest;
+    utr->setup.wValue     = wValue;
+    utr->setup.wIndex     = wIndex;
+    utr->setup.wLength    = wLength;
+
+    utr->buff = buff;
+    utr->data_len = wLength;
+    utr->bIsTransferDone = 0;
+    status = udev->hc_driver->ctrl_xfer(utr);
+    if (status < 0)
+    {
+        udev->ep0.hw_pipe = NULL;
+        free_utr(utr);
+        return status;
+    }
+
+    timeout_tick = usbh_tick_from_millisecond(timeout);
+    t0 = usbh_get_ticks();
+    while (utr->bIsTransferDone == 0)
+    {
+        if (usbh_get_ticks() - t0 > timeout_tick)
+        {
+            usbh_quit_utr(utr);
+            free_utr(utr);
+            udev->ep0.hw_pipe = NULL;
+            return USBH_ERR_TIMEOUT;
+        }
+    }
+
+    status = utr->status;
+
+    if (status == 0)
+    {
+        *xfer_len = utr->xfer_len;
+    }
+    free_utr(utr);
+
+    return status;
+}
+
+/**
+  * @brief    Execute a bulk transfer request. This function will return immediately after
+  *           issued the bulk transfer. USB stack will later call back utr->func() once the bulk
+  *           transfer was done or aborted.
+  * @param[in]  utr    The bulk transfer request.
+  * @retval   0     Transfer success
+  * @retval   < 0   Failed. Refer to error code definitions.
+  */
+int usbh_bulk_xfer(UTR_T *utr)
+{
+    return utr->udev->hc_driver->bulk_xfer(utr);
+}
+
+/**
+  * @brief    Execute an interrupt transfer request. This function will return immediately after
+  *           issued the interrupt transfer. USB stack will later call back utr->func() once the
+  *           interrupt transfer was done or aborted.
+  * @param[in]  utr    The interrupt transfer request.
+  * @retval   0     Transfer success
+  * @retval   < 0   Failed. Refer to error code definitions.
+  */
+int usbh_int_xfer(UTR_T *utr)
+{
+    return utr->udev->hc_driver->int_xfer(utr);
+}
+
+
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/Kconfig b/bsp/nuvoton/libraries/m2354/rtt_port/Kconfig
new file mode 100644
index 0000000000..bf7d2da98d
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/Kconfig
@@ -0,0 +1,958 @@
+config SOC_SERIES_M2354
+    bool
+    select ARCH_ARM_CORTEX_M23
+    select SOC_FAMILY_NUMICRO
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+    config BSP_USE_STDDRIVER_SOURCE
+        bool "Build StdDriver source"
+        default n
+
+    menuconfig BSP_USING_PDMA
+        bool "Enable Peripheral Direct Memory Access Controller(PDMA)"
+        default y
+
+        if BSP_USING_PDMA
+            config  NU_PDMA_MEMFUN_ACTOR_MAX
+            int "Specify maximum mem actor for memfun"
+            range 1 4
+            default 4
+
+            config  NU_PDMA_SGTBL_POOL_SIZE
+            int "Specify maximum scatter-gather pool size"
+            range 1 32
+            default 16
+        endif
+
+    config BSP_USING_FMC
+        bool "Enable Flash Memory Controller(FMC)"
+        select PKG_USING_FAL
+        default n
+
+    config BSP_USING_GPIO
+        bool "Enable General Purpose I/O(GPIO)"
+        select RT_USING_PIN
+        default y
+
+    menuconfig BSP_USING_CLK
+        bool "Enable Clock Controller(CLK)"
+        select RT_USING_PM
+        select BSP_USING_TMR
+        default y
+        help
+            Choose this option if you need CLK/PM function.
+            Notice: Enable the option will hold timer3 resource
+
+        if BSP_USING_CLK
+            config NU_CLK_INVOKE_WKTMR
+            bool "Enable SPD1 and DPD mode wakeup timer. (About 6.6 Secs)"
+            default y
+        endif
+
+    menuconfig BSP_USING_RTC
+        bool "Enable Real Time Clock(RTC)"
+        select RT_USING_RTC
+
+        config NU_RTC_SUPPORT_IO_RW
+            bool "Support device RW entry"
+            depends on BSP_USING_RTC && RT_USING_RTC
+
+        config NU_RTC_SUPPORT_MSH_CMD
+            bool "Support module shell command"
+            depends on BSP_USING_RTC && RT_USING_RTC
+
+    menuconfig BSP_USING_EADC
+        bool "Enable Enhanced Analog-to-Digital Converter(EADC)"
+        select RT_USING_ADC
+
+        if BSP_USING_EADC
+            config BSP_USING_EADC0
+                bool "Enable EADC0"
+        endif
+
+    menuconfig BSP_USING_TMR
+        bool "Enable Timer Controller(TIMER)"
+
+        if BSP_USING_TMR
+
+            config BSP_USING_TIMER
+                bool
+
+            config BSP_USING_TPWM
+                bool
+
+            config BSP_USING_TIMER_CAPTURE
+                bool
+
+            config BSP_USING_TMR0
+                bool "Enable TIMER0"
+                depends on BSP_USING_TMR
+
+            if BSP_USING_TMR0
+                choice
+                    prompt "Select TIMER0 function mode"
+
+                    config BSP_USING_TIMER0
+                        select BSP_USING_TIMER
+                        select RT_USING_HWTIMER
+                        bool "TIMER"
+                    help
+                        Choose this option if you need TIMER function mode.
+
+                    config BSP_USING_TPWM0
+                        select BSP_USING_TPWM
+                        select RT_USING_PWM
+                        bool "TIMER PWM"
+                    help
+                        Choose this option if you need PWM function mode.
+
+                    config BSP_USING_TIMER0_CAPTURE
+                        select BSP_USING_TIMER_CAPTURE
+                        select RT_USING_INPUT_CAPTURE
+                        bool "TIMER CAPTURE"
+                    help
+                        Choose this option if you need CAPTURE function mode.
+
+                endchoice
+            endif
+
+            config BSP_USING_TMR1
+                bool "Enable TIMER1"
+                depends on BSP_USING_TMR
+
+            if BSP_USING_TMR1
+                choice
+                    prompt "Select TIMER1 function mode"
+
+                    config BSP_USING_TIMER1
+                        select BSP_USING_TIMER
+                        select RT_USING_HWTIMER
+                        bool "TIMER"
+                        help
+                        Choose this option if you need TIMER function mode.
+
+                    config BSP_USING_TPWM1
+                        select BSP_USING_TPWM
+                        select RT_USING_PWM
+                        bool "TIMER PWM"
+                    help
+                        Choose this option if you need PWM function mode.
+
+                    config BSP_USING_TIMER1_CAPTURE
+                        select BSP_USING_TIMER_CAPTURE
+                        select RT_USING_INPUT_CAPTURE
+                        bool "TIMER CAPTURE"
+                    help
+                        Choose this option if you need CAPTURE function mode.
+                endchoice
+             endif
+
+            config BSP_USING_TMR2
+                bool "Enable TIMER2"
+                depends on BSP_USING_TMR
+
+             if BSP_USING_TMR2
+                choice
+                    prompt "Select TIMER2 function mode"
+
+                    config BSP_USING_TIMER2
+                        select BSP_USING_TIMER
+                        select RT_USING_HWTIMER
+                        bool "TIMER"
+                    help
+                        Choose this option if you need TIMER function mode.
+
+                    config BSP_USING_TPWM2
+                        select BSP_USING_TPWM
+                        select RT_USING_PWM
+                        bool "TIMER PWM"
+                    help
+                        Choose this option if you need PWM function mode.
+
+                    config BSP_USING_TIMER2_CAPTURE
+                        select BSP_USING_TIMER_CAPTURE
+                        select RT_USING_INPUT_CAPTURE
+                        bool "TIMER CAPTURE"
+                    help
+                        Choose this option if you need CAPTURE function mode.
+                endchoice
+            endif
+
+            config BSP_USING_TMR3
+                bool "Enable TIMER3"
+                depends on BSP_USING_TMR
+
+            if BSP_USING_TMR3
+                choice
+                    prompt "Select TIMER3 function mode"
+
+                    config BSP_USING_TIMER3
+                        select BSP_USING_TIMER
+                        select RT_USING_HWTIMER
+                        bool "TIMER"
+                        help
+                            Choose this option if you need TIMER function mode.
+
+                    config BSP_USING_TPWM3
+                        select BSP_USING_TPWM
+                        select RT_USING_PWM
+                        bool "TIMER PWM"
+                        help
+                            Choose this option if you need PWM function mode.
+
+                    config BSP_USING_TIMER3_CAPTURE
+                        select BSP_USING_TIMER_CAPTURE
+                        select RT_USING_INPUT_CAPTURE
+                        bool "TIMER CAPTURE"
+                    help
+                        Choose this option if you need CAPTURE function mode.
+                endchoice
+            endif
+
+            config BSP_USING_TMR4
+                bool "Enable TIMER4"
+                depends on BSP_USING_TMR
+
+            if BSP_USING_TMR4
+                choice
+                    prompt "Select TIMER4 function mode"
+
+                    config BSP_USING_TIMER4
+                        select BSP_USING_TIMER
+                        select RT_USING_HWTIMER
+                        bool "TIMER"
+                        help
+                            Choose this option if you need TIMER function mode.
+
+                    config BSP_USING_TPWM4
+                        select BSP_USING_TPWM
+                        select RT_USING_PWM
+                        bool "TIMER PWM"
+                        help
+                            Choose this option if you need PWM function mode.
+
+                    config BSP_USING_TIMER4_CAPTURE
+                        select BSP_USING_TIMER_CAPTURE
+                        select RT_USING_INPUT_CAPTURE
+                        bool "TIMER CAPTURE"
+                    help
+                        Choose this option if you need CAPTURE function mode.
+                endchoice
+            endif
+
+            config BSP_USING_TMR5
+                bool "Enable TIMER5"
+                depends on BSP_USING_TMR && !BSP_USING_CLK
+
+            if BSP_USING_TMR5
+                choice
+                    prompt "Select TIMER5 function mode"
+
+                    config BSP_USING_TIMER5
+                        select BSP_USING_TIMER
+                        select RT_USING_HWTIMER
+                        bool "TIMER"
+                        help
+                            Choose this option if you need TIMER function mode.
+
+                    config BSP_USING_TPWM5
+                        select BSP_USING_TPWM
+                        select RT_USING_PWM
+                        bool "TIMER PWM"
+                        help
+                            Choose this option if you need PWM function mode.
+
+                    config BSP_USING_TIMER5_CAPTURE
+                        select BSP_USING_TIMER_CAPTURE
+                        select RT_USING_INPUT_CAPTURE
+                        bool "TIMER CAPTURE"
+                    help
+                        Choose this option if you need CAPTURE function mode.
+                endchoice
+            endif
+    endif
+
+    menuconfig BSP_USING_UART
+        bool "Enable Universal Asynchronous Receiver/Transmitters(UART)"
+        select RT_USING_SERIAL
+
+        if BSP_USING_UART
+            config BSP_USING_UART0
+                bool "Enable UART0"
+
+            config BSP_USING_UART0_TX_DMA
+                bool "Enable UART0 TX DMA"
+                depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+
+            config BSP_USING_UART0_RX_DMA
+                bool "Enable UART0 RX DMA"
+                depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+
+            config BSP_USING_UART1
+                bool "Enable UART1"
+
+            config BSP_USING_UART1_TX_DMA
+                bool "Enable UART1 TX DMA"
+                depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+
+            config BSP_USING_UART1_RX_DMA
+                bool "Enable UART1 RX DMA"
+                depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+
+            config BSP_USING_UART2
+                bool "Enable UART2"
+
+            config BSP_USING_UART2_TX_DMA
+                bool "Enable UART2 TX DMA"
+                depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
+
+            config BSP_USING_UART2_RX_DMA
+                bool "Enable UART2 RX DMA"
+                depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
+
+            config BSP_USING_UART3
+                bool "Enable UART3"
+
+            config BSP_USING_UART3_TX_DMA
+                bool "Enable UART3 TX DMA"
+                depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
+
+            config BSP_USING_UART3_RX_DMA
+                bool "Enable UART3 RX DMA"
+                depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
+
+            config BSP_USING_UART4
+                bool "Enable UART4"
+
+            config BSP_USING_UART4_TX_DMA
+                bool "Enable UART4 TX DMA"
+                depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA
+
+            config BSP_USING_UART4_RX_DMA
+                bool "Enable UART4 RX DMA"
+                depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA
+
+            config BSP_USING_UART5
+                bool "Enable UART5"
+
+            config BSP_USING_UART5_TX_DMA
+                bool "Enable UART5 TX DMA"
+                depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA
+
+            config BSP_USING_UART5_RX_DMA
+                bool "Enable UART5 RX DMA"
+                depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA
+       endif
+
+    menuconfig BSP_USING_I2C
+        bool "Enable I2C Serial Interface Controller(I2C)"
+        select RT_USING_I2C
+
+        if BSP_USING_I2C
+            config BSP_USING_I2C0
+                bool "Enable I2C0"
+
+            config BSP_USING_I2C1
+                bool "Enable I2C1"
+
+            config BSP_USING_I2C2
+                bool "Enable I2C2"
+        endif
+
+    menuconfig BSP_USING_USCI
+        bool "Enable Universal Serial Control Interface Controller(USCI)"
+
+    if BSP_USING_USCI
+
+        config BSP_USING_UUART
+            bool
+
+        config BSP_USING_USPI
+            bool
+
+        config BSP_USING_USPI_PDMA
+            bool
+            default n
+
+        config BSP_USING_UI2C
+            bool
+
+        config BSP_USING_USCI0
+            bool "Enable USCI0"
+
+        if BSP_USING_USCI0
+            choice
+                prompt "Select USCI0 function mode"
+
+                config BSP_USING_UUART0
+                    select RT_USING_SERIAL
+                    select BSP_USING_UUART
+                    bool "UUART0"
+                    help
+                        Choose this option if you need UART function mode.
+
+                config BSP_USING_UI2C0
+                    select RT_USING_I2C
+                    select BSP_USING_UI2C
+                    bool "UI2C0"
+                    help
+                        Choose this option if you need I2C function mode.
+
+                config BSP_USING_USPI0
+                    select RT_USING_SPI
+                    select BSP_USING_USPI
+                    bool "USPI0"
+                    help
+                        Choose this option if you need SPI function mode.
+            endchoice
+
+            config BSP_USING_UUART0_TX_DMA
+                bool "Enable UUART0 TX DMA"
+                depends on BSP_USING_UUART0 && RT_SERIAL_USING_DMA
+
+            config BSP_USING_UUART0_RX_DMA
+                bool "Enable UUART0 RX DMA"
+                depends on BSP_USING_UUART0 && RT_SERIAL_USING_DMA
+
+            config BSP_USING_USPI0_PDMA
+                bool "Use PDMA for data transferring"
+                select BSP_USING_USPI_PDMA
+                depends on BSP_USING_USPI0
+        endif
+
+        config BSP_USING_USCI1
+            bool "Enable USCI1"
+
+            if BSP_USING_USCI1
+                choice
+                    prompt "Select USCI1 function mode"
+
+                    config BSP_USING_UUART1
+                        select RT_USING_SERIAL
+                        select BSP_USING_UUART
+                        bool "UUART1"
+                        help
+                          Choose this option if you need UART function mode.
+
+                    config BSP_USING_UI2C1
+                        select RT_USING_I2C
+                        select BSP_USING_UI2C
+                        bool "UI2C1"
+                        help
+                          Choose this option if you need I2C function mode.
+
+                     config BSP_USING_USPI1
+                        select RT_USING_SPI
+                        select BSP_USING_USPI
+                        bool "USPI1"
+                        help
+                          Choose this option if you need SPI function mode.
+                endchoice
+
+                config BSP_USING_UUART1_TX_DMA
+                    bool "Enable UUART1 TX DMA"
+                    depends on BSP_USING_UUART1 && RT_SERIAL_USING_DMA
+
+                config BSP_USING_UUART1_RX_DMA
+                    bool "Enable UUART1 RX DMA"
+                    depends on BSP_USING_UUART1 && RT_SERIAL_USING_DMA
+
+                config BSP_USING_USPI1_PDMA
+                    bool "Use PDMA for data transferring"
+                    select BSP_USING_USPI_PDMA
+                    depends on BSP_USING_USPI1
+            endif
+
+    endif
+
+    menuconfig BSP_USING_SDH
+        bool "Enable Secure Digital Host Controller(SDH)"
+        select RT_USING_DFS
+
+        if BSP_USING_SDH
+            config BSP_USING_SDH0
+                bool "Enable SDH0"
+
+            config NU_SDH_USING_PDMA
+                bool "Using PDMA"
+                select BSP_USING_PDMA
+
+            config NU_SDH_HOTPLUG
+                bool "Using HOTPLUG"
+                default y
+
+            config NU_SDH_MOUNT_ON_ROOT
+                bool "Mount on root"
+
+        endif
+
+    menuconfig BSP_USING_CAN
+        bool "Enable Controller Area Network(CAN)"
+        select RT_USING_CAN
+
+        if BSP_USING_CAN
+            config BSP_USING_CAN0
+                bool "Enable CAN0"
+        endif
+
+    menuconfig BSP_USING_BPWM
+        bool "Enable Basic PWM Generator and Capture Timer(BPWM)"
+        select RT_USING_PWM
+
+        if BSP_USING_BPWM
+
+            config BSP_USING_BPWM_CAPTURE
+                bool
+
+            choice
+                prompt "Select BPWM0 function mode"
+                config BSP_USING_BPWM0
+                    select RT_USING_PWM
+                    bool "Enable BPWM0"
+                    help
+                        Choose this option if you need PWM function mode.
+
+                config BSP_USING_BPWM0_CAPTURE
+                    select RT_USING_INPUT_CAPTURE
+                    select BSP_USING_BPWM_CAPTURE
+                    bool "Enable BPWM0_CAPTURE"
+                    help
+                        Choose this option if you need PWM capture function mode.
+            endchoice
+
+            if BSP_USING_BPWM0_CAPTURE
+                config BSP_USING_BPWM0_CAPTURE_CHMSK
+                    hex "Specify channel mask for BPWM0_CAP channel."
+                    range 0 0x3F
+                    default 0
+            endif
+
+            choice
+                prompt "Select BPWM1 function mode"
+                config BSP_USING_BPWM1
+                    select RT_USING_PWM
+                    bool "Enable BPWM1"
+                    help
+                        Choose this option if you need PWM function mode.
+
+                config BSP_USING_BPWM1_CAPTURE
+                    select RT_USING_INPUT_CAPTURE
+                    select BSP_USING_BPWM_CAPTURE
+                    bool "Enable BPWM1_CAPTURE"
+                    help
+                        Choose this option if you need PWM capture function mode.
+            endchoice
+
+            if BSP_USING_BPWM1_CAPTURE
+                config BSP_USING_BPWM1_CAPTURE_CHMSK
+                   hex "Specify channel mask for BPWM1_CAP channel."
+                   range 0 0x3F
+                   default 0
+            endif
+
+        endif
+
+    menuconfig BSP_USING_EPWM
+        bool "Enable EPWM Generator and Capture Timer(EPWM)"
+
+        if BSP_USING_EPWM
+
+            config BSP_USING_EPWM_CAPTURE
+                bool
+
+            choice
+                prompt "Select EPWM0 function mode"
+                config BSP_USING_EPWM0
+                    select RT_USING_PWM
+                    bool "Enable EPWM0"
+                    help
+                        Choose this option if you need PWM function mode.
+
+                config BSP_USING_EPWM0_CAPTURE
+                    select RT_USING_INPUT_CAPTURE
+                    select BSP_USING_EPWM_CAPTURE
+                    bool "Enable EPWM0_CAPTURE"
+                    help
+                        Choose this option if you need PWM capture function mode.
+            endchoice
+
+            if BSP_USING_EPWM0_CAPTURE
+                config BSP_USING_EPWM0_CAPTURE_CHMSK
+                    hex "Specify channel mask for EPWM0_CAP channel."
+                    range 0 0x3F
+                    default 0
+            endif
+
+            choice
+                prompt "Select EPWM1 function mode"
+                config BSP_USING_EPWM1
+                    select RT_USING_PWM
+                    bool "Enable EPWM1"
+                    help
+                        Choose this option if you need PWM function mode.
+
+                config BSP_USING_EPWM1_CAPTURE
+                    select RT_USING_INPUT_CAPTURE
+                    select BSP_USING_EPWM_CAPTURE
+                    bool "Enable EPWM1_CAPTURE"
+                    help
+                        Choose this option if you need PWM capture function mode.
+            endchoice
+
+            if BSP_USING_EPWM1_CAPTURE
+                config BSP_USING_EPWM1_CAPTURE_CHMSK
+                   hex "Specify channel mask for EPWM1_CAP channel."
+                   range 0 0x3F
+                   default 0
+            endif
+
+       endif
+
+    menuconfig BSP_USING_SPI
+       bool "Enable Serial Peripheral Interface(SPI)"
+       select RT_USING_SPI
+
+       if BSP_USING_SPI
+            config BSP_USING_SPI_PDMA
+            bool
+            default n
+
+            config BSP_USING_SPII2S
+            bool
+            default n
+
+            choice
+                prompt "Select SPI0 function mode"
+                config BSP_USING_SPI0_NONE
+                bool "NONE"
+                help
+                    Choose this option if you need not SPI0.
+
+                config BSP_USING_SPI0
+                bool "Enable SPI0"
+                help
+                    Choose this option if you need SPI function mode.
+
+                config BSP_USING_SPII2S0
+                    select RT_USING_AUDIO
+                    select BSP_USING_SPII2S
+                    bool "Enable SPII2S0"
+                    help
+                      Choose this option if you need SPII2S function mode.
+            endchoice
+
+            if BSP_USING_SPI0
+                   config BSP_USING_SPI0_PDMA
+                       bool "Enable PDMA for SPI0"
+                       select BSP_USING_SPI_PDMA
+                       depends on BSP_USING_SPI0
+            endif
+
+            choice
+                prompt "Select SPI1 function mode"
+                config BSP_USING_SPI1_NONE
+                bool "NONE"
+                help
+                    Choose this option if you need not SPI1.
+
+                config BSP_USING_SPI1
+                bool "Enable SPI1"
+                help
+                    Choose this option if you need SPI function mode.
+
+                config BSP_USING_SPII2S1
+                    select RT_USING_AUDIO
+                    select BSP_USING_SPII2S
+                    bool "Enable SPII2S1"
+                help
+                    Choose this option if you need SPII2S function mode.
+              endchoice
+
+              if BSP_USING_SPI1
+                   config BSP_USING_SPI1_PDMA
+                       bool "Enable PDMA for SPI1"
+                       select BSP_USING_SPI_PDMA
+                       depends on BSP_USING_SPI1
+              endif
+
+            choice
+                prompt "Select SPI2 function mode"
+                config BSP_USING_SPI2_NONE
+                bool "NONE"
+                help
+                    Choose this option if you need not SPI2.
+
+                config BSP_USING_SPI2
+                bool "Enable SPI2"
+                   help
+                      Choose this option if you need SPI function mode.
+
+                 config BSP_USING_SPII2S2
+                    select RT_USING_AUDIO
+                    select BSP_USING_SPII2S
+                    bool "Enable SPII2S2"
+                    help
+                      Choose this option if you need SPII2S function mode.
+            endchoice
+
+              if BSP_USING_SPI2
+                   config BSP_USING_SPI2_PDMA
+                       bool "Enable PDMA for SPI2"
+                       select BSP_USING_SPI_PDMA
+                       depends on BSP_USING_SPI2
+              endif
+
+            choice
+                prompt "Select SPI3 function mode"
+                config BSP_USING_SPI3_NONE
+                bool "NONE"
+                help
+                    Choose this option if you need not SPI3.
+
+                config BSP_USING_SPI3
+                bool "Enable SPI3"
+                help
+                    Choose this option if you need SPI function mode.
+
+                config BSP_USING_SPII2S3
+                    select RT_USING_AUDIO
+                    select BSP_USING_SPII2S
+                    bool "Enable SPII2S3"
+                    help
+                      Choose this option if you need SPII2S function mode.
+              endchoice
+
+              if BSP_USING_SPI3
+                  config BSP_USING_SPI3_PDMA
+                       bool "Enable PDMA for SPI3"
+                       select BSP_USING_SPI_PDMA
+                       depends on BSP_USING_SPI3
+              endif
+
+         endif
+
+    config BSP_USING_I2S
+        bool "Enable I2S Controller(I2S)"
+        select RT_USING_AUDIO
+
+    if BSP_USING_I2S || BSP_USING_SPII2S
+        config NU_I2S_DMA_FIFO_SIZE
+        int "DMA Buffer size of capture and playback"
+        range 2048 4096
+        default 2048
+    endif
+
+    menuconfig BSP_USING_QSPI
+        bool "Enable Quad Serial Peripheral Interface(QSPI)"
+        select RT_USING_SPI
+        select RT_USING_QSPI
+        select BSP_USING_SPI
+
+        if BSP_USING_QSPI
+           config BSP_USING_QSPI0
+               bool "Enable QSPI0"
+
+           config BSP_USING_QSPI0_PDMA
+                bool "Enable PDMA for QSPI0"
+                select BSP_USING_SPI_PDMA
+                depends on BSP_USING_QSPI0
+        endif
+
+    menuconfig BSP_USING_SCUART
+        bool "Enable Smart Card Host Interface - UART(SCUART)"
+
+           if BSP_USING_SCUART
+           config BSP_USING_SCUART0
+               bool "Enable SCUART0"
+
+           config BSP_USING_SCUART1
+               bool "Enable SCUART1"
+
+           config BSP_USING_SCUART2
+               bool "Enable SCUART2"
+        endif
+
+    menuconfig BSP_USING_ECAP
+        bool "Enable Enhanced Input Capture Timer(ECAP)"
+
+         if BSP_USING_ECAP
+
+            config BSP_USING_ECAP0
+                select RT_USING_INPUT_CAPTURE
+                bool "Enable ECAP0"
+                help
+                    Choose this option if you need ECAP0.
+
+            if BSP_USING_ECAP0
+                config BSP_USING_ECAP0_CHMSK
+                hex "Specify channel mask for ECAP0 channel."
+                range 0 0x7
+                default 0
+            endif
+
+            config BSP_USING_ECAP1
+                select RT_USING_INPUT_CAPTURE
+                bool "Enable ECAP1"
+                help
+                    Choose this option if you need ECAP1.
+
+            if BSP_USING_ECAP1
+                config BSP_USING_ECAP1_CHMSK
+                hex "Specify channel mask for ECAP1 channel."
+                range 0 0x7
+                default 0
+            endif
+
+       endif
+
+    menuconfig BSP_USING_QEI
+        bool "Enable Quadrature Encoder Interface(QEI)"
+
+        if BSP_USING_QEI
+            config BSP_USING_QEI0
+            bool "Enable QEI0"
+            select RT_USING_PULSE_ENCODER
+
+            config BSP_USING_QEI1
+            bool "Enable QEI1"
+            select RT_USING_PULSE_ENCODER
+        endif
+
+    menuconfig BSP_USING_CRYPTO
+        bool "Enable Cryptographic Accelerator(CRYPTO)"
+        select RT_USING_HWCRYPTO
+        select RT_HWCRYPTO_USING_AES
+        select RT_HWCRYPTO_USING_AES_ECB
+        select RT_HWCRYPTO_USING_AES_CBC
+        select RT_HWCRYPTO_USING_AES_CFB
+        select RT_HWCRYPTO_USING_AES_CTR
+        select RT_HWCRYPTO_USING_AES_CFB
+        select RT_HWCRYPTO_USING_AES_OFB
+        select RT_HWCRYPTO_USING_DES
+        select RT_HWCRYPTO_USING_DES_ECB
+        select RT_HWCRYPTO_USING_DES_CBC
+        select RT_HWCRYPTO_USING_3DES
+        select RT_HWCRYPTO_USING_3DES_ECB
+        select RT_HWCRYPTO_USING_3DES_CBC
+        select RT_HWCRYPTO_USING_SHA1
+        select RT_HWCRYPTO_USING_SHA2
+        select RT_HWCRYPTO_USING_SHA2_224
+        select RT_HWCRYPTO_USING_SHA2_256
+        select RT_HWCRYPTO_USING_SHA2_384
+        select RT_HWCRYPTO_USING_SHA2_512
+        select RT_HWCRYPTO_USING_RNG
+
+        if BSP_USING_CRYPTO
+            config NU_PRNG_USE_SEED
+                bool "Use specified seed value."
+                help
+                   Specify the seed value to PRNG.
+
+            if NU_PRNG_USE_SEED
+                config NU_PRNG_SEED_VALUE
+                    hex "Enter seed value"
+                    range 0 0xFFFFFFFF
+                    default 0
+            endif
+        endif
+
+        config BSP_USING_TRNG
+            bool "Enable True Random Number Generator(TRNG)"
+            select BSP_USING_CRYPTO
+            select RT_USING_HWCRYPTO
+            select RT_HWCRYPTO_USING_RNG
+
+        menuconfig BSP_USING_CRC
+            bool "Enable Cyclic Redundancy Check Generator(CRC)"
+            select BSP_USING_CRYPTO
+            select RT_USING_HWCRYPTO
+            select RT_HWCRYPTO_USING_CRC
+            select RT_HWCRYPTO_USING_CRC_07
+            select RT_HWCRYPTO_USING_CRC_8005
+            select RT_HWCRYPTO_USING_CRC_1021
+            select RT_HWCRYPTO_USING_CRC_04C11DB7
+
+            if BSP_USING_CRC
+                config NU_CRC_USE_PDMA
+                bool "Use PDMA for data transferring."
+                select BSP_USING_PDMA
+                default y
+            endif
+
+
+    menuconfig BSP_USING_SOFT_I2C
+        bool "Enable SOFT I2C"
+
+        if BSP_USING_SOFT_I2C
+            config BSP_USING_SOFT_I2C0
+            bool "Enable SOFT I2C0"
+            select RT_USING_I2C
+            select RT_USING_I2C_BITOPS
+            default n
+
+            if BSP_USING_SOFT_I2C0
+                config BSP_SOFT_I2C0_SCL_PIN
+                hex "Specify the pin index of SCL of SOFT I2C0"
+                range 0 0x7F
+                default 0x18
+
+                config BSP_SOFT_I2C0_SDA_PIN
+                hex "Specify the pin index of SDA of SOFT I2C0"
+                range 0 0x7F
+                default 0x17
+            endif
+
+            config BSP_USING_SOFT_I2C1
+            bool "Enable SOFT I2C1"
+            select RT_USING_I2C
+            select RT_USING_I2C_BITOPS
+            default n
+
+            if BSP_USING_SOFT_I2C1
+                config BSP_SOFT_I2C1_SCL_PIN
+                hex "Specify the pin index of SCL of SOFT I2C1"
+                range 0 0x7F
+                default 0x0B
+
+                config BSP_SOFT_I2C1_SDA_PIN
+                hex "Specify the pin index of SDA of SOFT I2C1"
+                range 0 0x7F
+                default 0x0A
+            endif
+        endif
+
+    config BSP_USING_WDT
+        bool "Enable Watchdog Timer(WDT)"
+        select RT_USING_WDT
+        default y
+
+    config BSP_USING_EBI
+        bool "Enable External Bus Interface(EBI)"
+        default n
+
+    config BSP_USING_SLCD
+        bool "Enable Segment LCD Interface(SLCD)"
+        default n
+
+    config BSP_USING_USBD
+        bool "Enable Full-Speed USB Device Controller(USBD)"
+        select RT_USING_USB_DEVICE
+
+    config BSP_USING_USBH
+        bool "Enable Full-Speed USB Host Controller(USBH)"
+        select RT_USING_USB_HOST
+        select RT_USBH_MSTORAGE
+
+    if BSP_USING_USBH
+        config NU_USBHOST_HUB_POLLING_INTERVAL
+            int "USB Root Hub Polling Interval(in Mili-seconds)"
+            range 100 2000
+            default 100
+    endif
+
+    config BSP_USING_OTG
+        bool "Enable Full-Speed USB On-The-Go(OTG)"
+        select BSP_USING_USBH
+        select BSP_USING_USBD
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/SConscript b/bsp/nuvoton/libraries/m2354/rtt_port/SConscript
new file mode 100644
index 0000000000..0822565fbb
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/SConscript
@@ -0,0 +1,23 @@
+# RT-Thread building script for component
+
+Import('RTT_ROOT')
+from building import *
+
+cwd     = GetCurrentDir()
+src = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+group = []
+
+# USB driver constrain
+if GetDepend('BOARD_USING_USBD') and ( GetDepend('BSP_USING_OTG') or GetDepend('BSP_USING_USBH') ):
+    print ('Sorry, wrong selection.')
+    print ('[Hint] You already select BOARD_USING_USBD. Please de-select BSP_USING_OTG and BSP_USING_USBH.')
+    sys.exit(1)
+elif GetDepend('BOARD_USING_USBH') and ( GetDepend('BSP_USING_OTG') or GetDepend('BSP_USING_USBD') ):
+    print ('Sorry, wrong selection.')
+    print ('[Hint] You already select BOARD_USING_USBH. Please de-select BSP_USING_OTG and BSP_USING_USBD options.')
+    sys.exit(1)
+else:
+    group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_bpwm.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_bpwm.c
new file mode 100644
index 0000000000..dd6a8b0692
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_bpwm.c
@@ -0,0 +1,228 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-7-30       YHKuo            First version
+*
+******************************************************************************/
+
+#include 
+
+#if defined(BSP_USING_BPWM)
+
+#define LOG_TAG                 "drv.bpwm"
+#define DBG_ENABLE
+#define DBG_SECTION_NAME        LOG_TAG
+#define DBG_LEVEL               DBG_INFO
+#define DBG_COLOR
+#include 
+
+#include 
+#include 
+#include 
+#include "NuMicro.h"
+
+#define DEFAULT_DUTY                  50
+#define DEFAULT_FREQ                  1000
+
+enum
+{
+    BPWM_START = -1,
+#if defined(BSP_USING_BPWM0)
+    BPWM0_IDX,
+#endif
+#if defined(BSP_USING_BPWM1)
+    BPWM1_IDX,
+#endif
+    BPWM_CNT
+};
+
+struct nu_bpwm
+{
+    struct rt_device_pwm dev;
+    char *name;
+    BPWM_T *bpwm_base;
+    rt_int32_t pwm_period_time;
+};
+
+typedef struct nu_bpwm *nu_bpwm_t;
+
+static struct nu_bpwm nu_bpwm_arr [] =
+{
+#if defined(BSP_USING_BPWM0)
+    {
+        .name = "bpwm0",
+        .bpwm_base = BPWM0,
+    },
+#endif
+
+#if defined(BSP_USING_BPWM1)
+    {
+        .name = "bpwm1",
+        .bpwm_base = BPWM1,
+    },
+#endif
+    {0}
+}; /* bpwm nu_epwm */
+
+static rt_err_t nu_bpwm_control(struct rt_device_pwm *device, int cmd, void *arg);
+
+static struct rt_pwm_ops nu_bpwm_ops =
+{
+    .control = nu_bpwm_control
+};
+
+static rt_err_t nu_bpwm_enable(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration, rt_bool_t enable)
+{
+    rt_err_t result = RT_EOK;
+
+    BPWM_T *pwm_base = ((nu_bpwm_t)device)->bpwm_base;
+    rt_uint32_t pwm_channel = configuration->channel;
+
+    if (enable == RT_TRUE)
+    {
+        BPWM_EnableOutput(pwm_base, 1 << pwm_channel);
+        BPWM_Start(pwm_base, 1 << pwm_channel);
+    }
+    else if (enable == RT_FALSE)
+    {
+        BPWM_DisableOutput(pwm_base, 1 << pwm_channel);
+        BPWM_ForceStop(pwm_base, 1 << pwm_channel);
+    }
+
+    return result;
+}
+
+static rt_err_t nu_bpwm_set(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration)
+{
+    if ((configuration->period) <= 0)
+        return -(RT_ERROR);
+    rt_uint32_t pwm_freq, pwm_dutycycle;
+    BPWM_T *pwm_base = ((nu_bpwm_t)device)->bpwm_base;
+    rt_uint8_t pwm_channel = configuration->channel;
+    rt_uint32_t pwm_period = configuration->period;
+    rt_uint32_t pwm_pulse = configuration->pulse;
+
+    pwm_dutycycle = (pwm_pulse * 100) / pwm_period;
+
+    if (BPWM_GET_CNR(pwm_base, pwm_channel) != 0)
+    {
+        pwm_period = ((nu_bpwm_t)device)->pwm_period_time;
+        LOG_I("%s output frequency is determined, user can only change the duty\n", ((nu_bpwm_t)device)->name);
+    }
+    else
+    {
+        ((nu_bpwm_t)device)->pwm_period_time = pwm_period;
+    }
+
+    pwm_freq = 1000000000 / pwm_period;
+
+
+    BPWM_ConfigOutputChannel(pwm_base, pwm_channel, pwm_freq, pwm_dutycycle) ;
+
+    return RT_EOK;
+}
+
+static rt_uint32_t nu_bpwm_clksr(struct rt_device_pwm *device)
+{
+    rt_uint32_t u32Src, u32BPWMClockSrc;
+    BPWM_T *pwm_base = ((nu_bpwm_t)device)->bpwm_base;
+    if (pwm_base == BPWM0)
+    {
+        u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk;
+    }
+    else     /* (bpwm == BPWM1) */
+    {
+        u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk;
+    }
+
+    if (u32Src == 0U)
+    {
+        /* clock source is from PLL clock */
+        u32BPWMClockSrc = CLK_GetPLLClockFreq();
+    }
+    else
+    {
+        /* clock source is from PCLK */
+        SystemCoreClockUpdate();
+        if (pwm_base == BPWM0)
+        {
+            u32BPWMClockSrc = CLK_GetPCLK0Freq();
+        }
+        else     /* (bpwm == BPWM1) */
+        {
+            u32BPWMClockSrc = CLK_GetPCLK1Freq();
+        }
+    }
+    return u32BPWMClockSrc;
+}
+
+static rt_err_t nu_bpwm_get(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration)
+{
+    rt_uint32_t pwm_real_period, pwm_real_duty, time_tick, u32BPWMClockSrc ;
+
+    BPWM_T *pwm_base = ((nu_bpwm_t)device)->bpwm_base;
+    rt_uint32_t pwm_channel = configuration->channel;
+    rt_uint32_t pwm_prescale = pwm_base->CLKPSC;
+    rt_uint32_t pwm_period = BPWM_GET_CNR(pwm_base, pwm_channel);
+    rt_uint32_t pwm_pulse = BPWM_GET_CMR(pwm_base, pwm_channel);
+
+    u32BPWMClockSrc = nu_bpwm_clksr(device);
+    time_tick = 1000000000000 / u32BPWMClockSrc;
+
+    pwm_real_period = (((pwm_prescale + 1) * (pwm_period + 1)) * time_tick) / 1000;
+    pwm_real_duty = (((pwm_prescale + 1) * pwm_pulse * time_tick)) / 1000;
+    configuration->period = pwm_real_period;
+    configuration->pulse = pwm_real_duty;
+
+    LOG_I("%s %d %d %d\n", ((nu_bpwm_t)device)->name, configuration->channel, configuration->period, configuration->pulse);
+
+    return RT_EOK;
+}
+
+static rt_err_t nu_bpwm_control(struct rt_device_pwm *device, int cmd, void *arg)
+{
+    struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
+
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(configuration != RT_NULL);
+
+    if (((configuration->channel) + 1) > BPWM_CHANNEL_NUM)
+        return -(RT_ERROR);
+
+    switch (cmd)
+    {
+    case PWM_CMD_ENABLE:
+        return nu_bpwm_enable(device, configuration, RT_TRUE);
+    case PWM_CMD_DISABLE:
+        return nu_bpwm_enable(device, configuration, RT_FALSE);
+    case PWM_CMD_SET:
+        return nu_bpwm_set(device, configuration);
+    case PWM_CMD_GET:
+        return nu_bpwm_get(device, configuration);
+    default:
+        return RT_EINVAL;
+    }
+}
+
+int rt_hw_bpwm_init(void)
+{
+    rt_err_t ret;
+    rt_uint8_t i;
+
+    for (i = (BPWM_START + 1); i < BPWM_CNT; i++)
+    {
+        ret = rt_device_pwm_register(&nu_bpwm_arr[i].dev, nu_bpwm_arr[i].name, &nu_bpwm_ops, RT_NULL);
+        RT_ASSERT(ret == RT_EOK);
+    }
+
+    return 0;
+}
+
+INIT_DEVICE_EXPORT(rt_hw_bpwm_init);
+
+#endif
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_bpwm_capture.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_bpwm_capture.c
new file mode 100644
index 0000000000..5c3b634e5e
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_bpwm_capture.c
@@ -0,0 +1,335 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-8-19        Philo            First version
+*
+******************************************************************************/
+#include 
+
+#if defined(BSP_USING_BPWM_CAPTURE)
+#if ((BSP_USING_BPWM0_CAPTURE_CHMSK+BSP_USING_BPWM1_CAPTURE_CHMSK)!=0)
+#include 
+#include "NuMicro.h"
+
+/* Private typedef --------------------------------------------------------------*/
+typedef struct _bpwm_dev
+{
+    BPWM_T      *bpwm_base;
+    IRQn_Type   irq;
+    float       fUsPerTick;
+} nu_bpwm_dev_t;
+
+typedef struct _bpwm
+{
+    struct rt_inputcapture_device   parent;
+    nu_bpwm_dev_t *bpwm_dev;
+    uint8_t     u8Channel;
+    uint8_t     u8DummyData;
+    uint32_t    u32CurrentRisingCnt;
+    uint32_t    u32CurrentFallingCnt;
+    uint32_t    u32LastRisingCnt;
+    uint32_t    u32LastFallingCnt;
+    rt_bool_t   input_data_level;
+} nu_capture_t;
+
+/* Private functions ------------------------------------------------------------*/
+static  rt_err_t nu_capture_init(struct rt_inputcapture_device *inputcapture);
+static  rt_err_t nu_capture_open(struct rt_inputcapture_device *inputcapture);
+static  rt_err_t nu_capture_close(struct rt_inputcapture_device *inputcapture);
+static  rt_err_t nu_capture_get_pulsewidth(struct rt_inputcapture_device *inputcapture, rt_uint32_t *pulsewidth_us);
+
+/* Private define ---------------------------------------------------------------*/
+#define NU_DUMMY_DATA   2   /* First rising and falling edge should be ignore */
+
+#define NU_NO_EDGE      0
+#define NU_RISING_EDGE  1
+#define NU_FALLING_EDGE 2
+
+/* Public functions -------------------------------------------------------------*/
+
+
+/* Private variables ------------------------------------------------------------*/
+#if (BSP_USING_BPWM0_CAPTURE_CHMSK!=0)
+static const char *nu_bpwm0_device_name[BPWM_CHANNEL_NUM] = { "bpwm0i0", "bpwm0i1", "bpwm0i2", "bpwm0i3", "bpwm0i4", "bpwm0i5"};
+static nu_capture_t *nu_bpwm0_capture[BPWM_CHANNEL_NUM] = {0};
+static nu_bpwm_dev_t nu_bpwm0_dev = {.bpwm_base = BPWM0};
+#endif
+
+#if (BSP_USING_BPWM1_CAPTURE_CHMSK!=0)
+static const char *nu_bpwm1_device_name[BPWM_CHANNEL_NUM] = { "bpwm1i0", "bpwm1i1", "bpwm1i2", "bpwm1i3", "bpwm1i4", "bpwm1i5"};
+static nu_capture_t *nu_bpwm1_capture[BPWM_CHANNEL_NUM] = {0};
+static nu_bpwm_dev_t nu_bpwm1_dev = {.bpwm_base = BPWM1};
+#endif
+
+static struct rt_inputcapture_ops nu_capture_ops =
+{
+    .init   =   nu_capture_init,
+    .open   =   nu_capture_open,
+    .close  =   nu_capture_close,
+    .get_pulsewidth =   nu_capture_get_pulsewidth,
+};
+
+/* Functions define ------------------------------------------------------------*/
+void bpwm_interrupt_handler(nu_capture_t *nu_capture[], uint32_t u32ChMsk)
+{
+    uint32_t u32Status;
+
+    for (uint8_t i = 0; i < BPWM_CHANNEL_NUM ; i++)
+    {
+        if ((0x1 << i) & u32ChMsk)
+        {
+            if (nu_capture[i]->u8DummyData < NU_DUMMY_DATA)
+            {
+                nu_capture[i]->u8DummyData++;
+            }
+            else
+            {
+                u32Status = BPWM_GetCaptureIntFlag(nu_capture[i]->bpwm_dev->bpwm_base, nu_capture[i]->u8Channel);
+
+                switch (u32Status)
+                {
+                case NU_NO_EDGE:
+                    break;
+                case NU_RISING_EDGE:
+                    BPWM_ClearCaptureIntFlag(nu_capture[i]->bpwm_dev->bpwm_base, nu_capture[i]->u8Channel, BPWM_CAPTURE_INT_RISING_LATCH);
+                    nu_capture[i]->u32CurrentRisingCnt = BPWM_GET_CAPTURE_RISING_DATA(nu_capture[i]->bpwm_dev->bpwm_base, nu_capture[i]->u8Channel);
+                    rt_hw_inputcapture_isr(&nu_capture[i]->parent, nu_capture[i]->input_data_level);
+
+                    break;
+                case NU_FALLING_EDGE:
+                    BPWM_ClearCaptureIntFlag(nu_capture[i]->bpwm_dev->bpwm_base, nu_capture[i]->u8Channel, BPWM_CAPTURE_INT_FALLING_LATCH);
+                    nu_capture[i]->u32CurrentFallingCnt = BPWM_GET_CAPTURE_FALLING_DATA(nu_capture[i]->bpwm_dev->bpwm_base, nu_capture[i]->u8Channel);
+                    rt_hw_inputcapture_isr(&nu_capture[i]->parent, nu_capture[i]->input_data_level);
+
+                    break;
+                default:
+                    BPWM_ClearCaptureIntFlag(nu_capture[i]->bpwm_dev->bpwm_base, nu_capture[i]->u8Channel, BPWM_CAPTURE_INT_RISING_LATCH | BPWM_CAPTURE_INT_FALLING_LATCH);
+                    BPWM_GET_CAPTURE_RISING_DATA(nu_capture[i]->bpwm_dev->bpwm_base, nu_capture[i]->u8Channel);
+                    BPWM_GET_CAPTURE_FALLING_DATA(nu_capture[i]->bpwm_dev->bpwm_base, nu_capture[i]->u8Channel);
+
+                    break;
+                }
+            }
+        }
+    }
+}
+
+#if (BSP_USING_BPWM0_CAPTURE_CHMSK!=0)
+void BPWM0_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    bpwm_interrupt_handler(nu_bpwm0_capture, BSP_USING_BPWM0_CAPTURE_CHMSK);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif  //(BSP_USING_BPWM0_CAPTURE_CHMSK!=0)
+
+#if (BSP_USING_BPWM1_CAPTURE_CHMSK!=0)
+void BPWM1_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    bpwm_interrupt_handler(nu_bpwm1_capture, BSP_USING_BPWM1_CAPTURE_CHMSK);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif  //(BSP_USING_BPWM1_CAPTURE_CHMSK!=0)
+
+static rt_err_t nu_capture_get_pulsewidth(struct rt_inputcapture_device *inputcapture, rt_uint32_t *pulsewidth_us)
+{
+    rt_err_t ret = RT_EOK;
+    nu_capture_t *nu_capture;
+    float fTempCnt;
+
+    nu_capture = (nu_capture_t *)inputcapture;
+
+    if (nu_capture->u32CurrentFallingCnt)
+    {
+        if (nu_capture->u32CurrentFallingCnt > nu_capture->u32LastRisingCnt)
+            fTempCnt = nu_capture->u32CurrentFallingCnt - nu_capture->u32LastRisingCnt;
+        else    /* Overrun case */
+            fTempCnt = nu_capture->u32CurrentFallingCnt + (0x10000 - nu_capture->u32LastRisingCnt);
+
+        *pulsewidth_us = fTempCnt * nu_capture->bpwm_dev->fUsPerTick;
+        nu_capture->input_data_level = RT_FALSE;
+        nu_capture->u32LastFallingCnt = nu_capture->u32CurrentFallingCnt;
+        nu_capture->u32CurrentFallingCnt = 0;
+    }
+    else if (nu_capture->u32CurrentRisingCnt)
+    {
+        if (nu_capture->u32CurrentRisingCnt > nu_capture->u32LastFallingCnt)
+            fTempCnt = nu_capture->u32CurrentRisingCnt - nu_capture->u32LastFallingCnt;
+        else    /* Overrun case */
+            fTempCnt = nu_capture->u32CurrentRisingCnt + (0x10000 - nu_capture->u32LastFallingCnt);
+
+        *pulsewidth_us = fTempCnt * nu_capture->bpwm_dev->fUsPerTick;
+        nu_capture->input_data_level = RT_TRUE;
+        nu_capture->u32LastRisingCnt = nu_capture->u32CurrentRisingCnt;
+        nu_capture->u32CurrentRisingCnt = 0;
+    }
+    else
+    {
+        ret = RT_ERROR;
+    }
+    return -(ret);
+}
+
+static void bpwm_config(nu_capture_t *nu_capture)
+{
+    /* Set capture time as 500 nano second */
+    nu_capture->bpwm_dev->fUsPerTick = (float)BPWM_ConfigCaptureChannel(nu_capture->bpwm_dev->bpwm_base, 0, 500, 0) / 1000;
+
+    /* Enable BPWM NVIC interrupt */
+    NVIC_EnableIRQ(nu_capture->bpwm_dev->irq);
+
+    /* Set counter type as up count */
+    BPWM_SET_ALIGNED_TYPE(nu_capture->bpwm_dev->bpwm_base, 0, BPWM_UP_COUNTER);
+
+    /* Enable BPWM Timer */
+    BPWM_Start(nu_capture->bpwm_dev->bpwm_base, 0);
+}
+
+static rt_err_t nu_bpwm_init(nu_capture_t *nu_capture)
+{
+    rt_err_t ret = RT_ERROR;
+    static rt_bool_t bBPWM0Inited = RT_FALSE;
+    static rt_bool_t bBPWM1Inited = RT_FALSE;
+
+    if (nu_capture->bpwm_dev->bpwm_base == BPWM0)
+    {
+        if (bBPWM0Inited == RT_FALSE)
+        {
+            /* Enable BPWM0 clock */
+            SYS_UnlockReg();
+            CLK_EnableModuleClock(BPWM0_MODULE);
+            CLK_SetModuleClock(BPWM0_MODULE, CLK_CLKSEL2_BPWM0SEL_PCLK0, 0);
+            SYS_LockReg();
+            bpwm_config(nu_capture);
+            bBPWM0Inited = RT_TRUE;
+        }
+        ret = RT_EOK;
+    }
+    else if (nu_capture->bpwm_dev->bpwm_base == BPWM1)
+    {
+        if (bBPWM1Inited == RT_FALSE)
+        {
+            /* Enable BPWM1 clock */
+            SYS_UnlockReg();
+            CLK_EnableModuleClock(BPWM1_MODULE);
+            CLK_SetModuleClock(BPWM1_MODULE, CLK_CLKSEL2_BPWM1SEL_PCLK1, 0);
+            SYS_LockReg();
+            bpwm_config(nu_capture);
+            bBPWM1Inited = RT_TRUE;
+        }
+        ret = RT_EOK;
+    }
+
+    return -(ret);
+}
+
+static rt_err_t nu_capture_init(struct rt_inputcapture_device *inputcapture)
+{
+    rt_err_t ret = RT_EOK;
+    nu_capture_t *nu_capture;
+
+    RT_ASSERT(inputcapture != RT_NULL);
+
+    nu_capture = (nu_capture_t *) inputcapture;
+
+    if (nu_bpwm_init(nu_capture) != RT_EOK)
+    {
+        rt_kprintf("Failed to initialize BPWM.\n");
+        ret = RT_ERROR;
+    }
+
+    return -(ret);
+}
+
+static rt_err_t nu_capture_open(struct rt_inputcapture_device *inputcapture)
+{
+    nu_capture_t *nu_capture;
+
+    RT_ASSERT(inputcapture != RT_NULL);
+
+    nu_capture = (nu_capture_t *) inputcapture;
+
+    /* Enable capture rising/falling edge interrupt */
+    BPWM_EnableCaptureInt(nu_capture->bpwm_dev->bpwm_base, nu_capture->u8Channel, BPWM_CAPTURE_INT_FALLING_LATCH | BPWM_CAPTURE_INT_RISING_LATCH);
+
+    /* Enable Capture Function for BPWM */
+    BPWM_EnableCapture(nu_capture->bpwm_dev->bpwm_base, 0x1 << nu_capture->u8Channel);
+
+    return RT_EOK;
+}
+
+static rt_err_t nu_capture_close(struct rt_inputcapture_device *inputcapture)
+{
+    nu_capture_t *nu_capture;
+
+    RT_ASSERT(inputcapture != RT_NULL);
+
+    nu_capture = (nu_capture_t *) inputcapture;
+
+    /* Enable Capture Function for BPWM */
+    BPWM_DisableCapture(nu_capture->bpwm_dev->bpwm_base, 0x1 << nu_capture->u8Channel);
+
+    /* Disable capture rising/falling edge interrupt */
+    BPWM_DisableCaptureInt(nu_capture->bpwm_dev->bpwm_base, nu_capture->u8Channel, BPWM_CAPTURE_INT_FALLING_LATCH | BPWM_CAPTURE_INT_RISING_LATCH);
+
+    return RT_EOK;
+}
+
+static void bpwm_init(nu_capture_t *nu_capture, uint8_t u8Channel, nu_bpwm_dev_t *bpwm_dev, const char *device_name, IRQn_Type irq)
+{
+    nu_capture->bpwm_dev = bpwm_dev;
+    nu_capture->bpwm_dev->irq = irq;
+    nu_capture->u8Channel = u8Channel;
+    nu_capture->u8DummyData = 0;
+    nu_capture->u32CurrentFallingCnt = 0;
+    nu_capture->u32CurrentRisingCnt = 0;
+    nu_capture->u32LastRisingCnt = 0;
+    nu_capture->u32LastFallingCnt = 0;
+    nu_capture->parent.ops = &nu_capture_ops;
+
+    /* register inputcapture device */
+    rt_device_inputcapture_register(&nu_capture->parent, device_name, &nu_capture);
+}
+
+/* Init and register bpwm capture */
+static int nu_bpwm_capture_device_init(void)
+{
+    for (int i = 0; i < BPWM_CHANNEL_NUM; i++)
+    {
+#if (BSP_USING_BPWM0_CAPTURE_CHMSK!=0)
+        if (BSP_USING_BPWM0_CAPTURE_CHMSK & (0x1 << i))
+        {
+            nu_bpwm0_capture[i] = (nu_capture_t *)rt_malloc(sizeof(nu_capture_t));
+            bpwm_init(nu_bpwm0_capture[i], i, &nu_bpwm0_dev, nu_bpwm0_device_name[i], BPWM0_IRQn);
+        }
+#endif //#if (BSP_USING_BPWM0_CAPTURE_CHMSK!=0)
+
+#if (BSP_USING_BPWM1_CAPTURE_CHMSK!=0)
+        if (BSP_USING_BPWM1_CAPTURE_CHMSK & (0x1 << i))
+        {
+            nu_bpwm1_capture[i] = (nu_capture_t *)rt_malloc(sizeof(nu_capture_t));
+            bpwm_init(nu_bpwm1_capture[i], i, &nu_bpwm1_dev, nu_bpwm1_device_name[i], BPWM1_IRQn);
+        }
+#endif //#if (BSP_USING_BPWM1_CAPTURE_CHMSK!=0)
+    }
+
+    return 0;
+}
+INIT_DEVICE_EXPORT(nu_bpwm_capture_device_init);
+
+#endif  //#if ((BSP_USING_BPWM0_CAPTURE_CHMSK+BSP_USING_BPWM1_CAPTURE_CHMSK)!=0)
+#endif //#if defined(BSP_USING_BPWM_CAPTURE)
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_can.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_can.c
new file mode 100644
index 0000000000..614705fcc5
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_can.c
@@ -0,0 +1,523 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author       Notes
+* 2020-6-22       ChingI       First version
+*
+******************************************************************************/
+
+#include 
+
+#if defined(BSP_USING_CAN)
+
+#include 
+#include 
+#include "NuMicro.h"
+
+/* Private Define ---------------------------------------------------------------*/
+#define RX_MSG_ID_INDEX        16
+#define IS_CAN_STDID(STDID)   ((STDID) <= 0x7FFU)
+#define IS_CAN_EXTID(EXTID)   ((EXTID) <= 0x1FFFFFFFU)
+#define IS_CAN_DLC(DLC)       ((DLC) <= 8U)
+
+/* Default config for serial_configure structure */
+#define NU_CAN_CONFIG_DEFAULT                  \
+{                                              \
+    CAN1MBaud,           /* 1M bits/s       */ \
+    RT_CANMSG_BOX_SZ,    /* message box max size */ \
+    RT_CANSND_BOX_NUM,   /* message box number   */ \
+    RT_CAN_MODE_NORMAL,  /* Normal mode     */ \
+    0,                   /* privmode        */ \
+    0,                   /* reserved        */ \
+    100,                 /* Timeout Tick    */ \
+}
+
+enum
+{
+    CAN_START = -1,
+#if defined(BSP_USING_CAN0)
+    CAN0_IDX,
+#endif
+    CAN_CNT,
+};
+
+/* Private Typedef --------------------------------------------------------------*/
+struct nu_can
+{
+    struct rt_can_device dev;
+    char *name;
+    CAN_T *can_base;
+    uint32_t can_rst;
+    IRQn_Type can_irq_n;
+};
+typedef struct nu_can *nu_can_t;
+
+/* Private functions ------------------------------------------------------------*/
+static rt_err_t nu_can_configure(struct rt_can_device *can, struct can_configure *cfg);
+static rt_err_t nu_can_control(struct rt_can_device *can, int cmd, void *arg);
+static int nu_can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno);
+static int nu_can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno);
+static void nu_can_isr(nu_can_t can);
+
+static struct nu_can nu_can_arr[] =
+{
+#if defined(BSP_USING_CAN0)
+    {
+        .name = "can0",
+        .can_base = CAN0,
+        .can_rst = CAN0_RST,
+        .can_irq_n =  CAN0_IRQn,
+    },
+#endif
+    {0}
+}; /* struct nu_can */
+
+/* Public functions ------------------------------------------------------------*/
+
+/* Private variables ------------------------------------------------------------*/
+static const struct rt_can_ops nu_can_ops =
+{
+    .configure = nu_can_configure,
+    .control = nu_can_control,
+    .sendmsg = nu_can_sendmsg,
+    .recvmsg = nu_can_recvmsg,
+};
+
+static const struct can_configure nu_can_default_config = NU_CAN_CONFIG_DEFAULT;
+
+/* Interrupt Handle Function  ----------------------------------------------------*/
+#if defined(BSP_USING_CAN0)
+/* CAN0 interrupt entry */
+void CAN0_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    nu_can_isr(&nu_can_arr[CAN0_IDX]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+/* Private Variables ------------------------------------------------------------*/
+
+static void nu_can_isr(nu_can_t can)
+{
+    uint32_t u32IIDRstatus;
+    /* Get base address of CAN register */
+    CAN_T *can_base = ((nu_can_t)can)->can_base;
+
+    /* Get interrupt event */
+    u32IIDRstatus = CAN_GET_INT_PENDING_STATUS(can_base);
+
+    if (u32IIDRstatus == 0x00008000)       /* Check Status Interrupt Flag (Error status Int and Status change Int) */
+    {
+        /**************************/
+        /* Status Change interrupt*/
+        /**************************/
+        if (can_base->STATUS & CAN_STATUS_TXOK_Msk)
+        {
+            can_base->STATUS &= ~CAN_STATUS_TXOK_Msk;    /* Clear Tx Ok status*/
+#ifndef RT_CAN_USING_HDR
+            /* Using as Lisen,Loopback,Loopback+Lisen mode*/
+            rt_hw_can_isr(&can->dev, RT_CAN_EVENT_TX_DONE);
+#endif
+            //rt_kprintf("[%s]TX OK INT\n", can->name) ;
+        }
+
+        if (can_base->STATUS & CAN_STATUS_RXOK_Msk)
+        {
+            can_base->STATUS &= ~CAN_STATUS_RXOK_Msk;   /* Clear Rx Ok status*/
+#ifndef RT_CAN_USING_HDR
+            /* Using as Lisen,Loopback,Loopback+Lisen mode*/
+            rt_hw_can_isr(&can->dev, RT_CAN_EVENT_RX_IND);
+#endif
+            //rt_kprintf("[%s]RX OK INT\n", can->name) ;
+        }
+
+        /**************************/
+        /* Error Status interrupt */
+        /**************************/
+        if (can_base->STATUS & CAN_STATUS_EWARN_Msk)
+        {
+            rt_kprintf("[%s]EWARN INT\n", can->name) ;
+        }
+
+        if (can_base->STATUS & CAN_STATUS_BOFF_Msk)
+        {
+            rt_kprintf("[%s]BUSOFF INT\n", can->name) ;
+
+            /* Do Init to release busoff pin */
+            can_base->CON = (CAN_CON_INIT_Msk | CAN_CON_CCE_Msk);
+            can_base->CON &= (~(CAN_CON_INIT_Msk | CAN_CON_CCE_Msk));
+            while (can_base->CON & CAN_CON_INIT_Msk);
+        }
+    }
+#ifdef RT_CAN_USING_HDR
+    /*IntId: 0x0001-0x0020, Number of Message Object which caused the interrupt.*/
+    else if (u32IIDRstatus > 0 && u32IIDRstatus <= 32)
+    {
+        /*Message RAM 0~RX_MSG_ID_INDEX for CAN Tx using*/
+        if (u32IIDRstatus <= RX_MSG_ID_INDEX)
+        {
+            //rt_kprintf("[%s-Tx]IntId = %d\n", can->name, u32IIDRstatus);
+            rt_hw_can_isr(&can->dev, RT_CAN_EVENT_TX_DONE);
+        }
+        else /*Message RAM RX_MSG_ID_INDEX~31 for CAN Rx using*/
+        {
+            //rt_kprintf("[%s-Rx]IntId = %d\n", can->name, u32IIDRstatus);
+            rt_hw_can_isr(&can->dev, (RT_CAN_EVENT_RX_IND | ((u32IIDRstatus - 1) << 8)));
+        }
+        CAN_CLR_INT_PENDING_BIT(can_base, (u32IIDRstatus - 1));     /* Clear Interrupt Pending */
+    }
+#endif
+
+}
+
+
+static rt_err_t nu_can_configure(struct rt_can_device *can, struct can_configure *cfg)
+{
+
+    RT_ASSERT(can != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+
+    /* Get base address of CAN register */
+    CAN_T *can_base = ((nu_can_t)can)->can_base;
+
+    RT_ASSERT(can_base != RT_NULL);
+
+    /* Reset this module */
+    SYS_ResetModule(((nu_can_t)can)->can_rst);
+
+    switch (cfg->mode)
+    {
+    /* CAN default Normal mode */
+    case RT_CAN_MODE_NORMAL:
+        can->config.mode = CAN_NORMAL_MODE;
+        break;
+    case RT_CAN_MODE_LISEN:
+        can->config.mode = RT_CAN_MODE_LISEN;
+        break;
+    case RT_CAN_MODE_LOOPBACK:
+        can->config.mode = RT_CAN_MODE_LOOPBACK;
+        break;
+    case RT_CAN_MODE_LOOPBACKANLISEN:
+        can->config.mode = RT_CAN_MODE_LOOPBACKANLISEN;
+        break;
+    default:
+        rt_kprintf("Unsupported Operating mode");
+        goto exit_nu_can_configure;
+    }
+
+    /*Set the CAN Bit Rate and Operating mode*/
+    if (CAN_Open(can_base, can->config.baud_rate, can->config.mode) < 1)
+        return -(RT_ERROR);
+
+
+    switch (cfg->mode)
+    {
+    /* CAN default Normal mode */
+    case RT_CAN_MODE_NORMAL:
+#ifdef RT_CAN_USING_HDR
+        CAN_LeaveTestMode(can_base);
+#else
+        CAN_EnterTestMode(can_base, CAN_TEST_BASIC_Msk);
+#endif
+        break;
+    case RT_CAN_MODE_LISEN:
+        CAN_EnterTestMode(can_base, CAN_TEST_BASIC_Msk | CAN_TEST_SILENT_Msk);
+        break;
+    case RT_CAN_MODE_LOOPBACK:
+        CAN_EnterTestMode(can_base, CAN_TEST_BASIC_Msk | CAN_TEST_LBACK_Msk);
+        break;
+    case RT_CAN_MODE_LOOPBACKANLISEN:
+        CAN_EnterTestMode(can_base, CAN_TEST_BASIC_Msk | CAN_TEST_SILENT_Msk | CAN_TEST_LBACK_Msk);
+        break;
+    default:
+        rt_kprintf("Unsupported Operating mode");
+        goto exit_nu_can_configure;
+    }
+
+
+    return RT_EOK;
+
+exit_nu_can_configure:
+
+    CAN_Close(can_base);
+
+    return -(RT_ERROR);
+}
+
+static rt_err_t nu_can_control(struct rt_can_device *can, int cmd, void *arg)
+{
+    rt_uint32_t argval;
+
+#ifdef RT_CAN_USING_HDR
+    struct rt_can_filter_config *filter_cfg;
+#endif
+    /* Get base address of CAN register */
+    CAN_T *can_base = ((nu_can_t)can)->can_base;
+
+    RT_ASSERT(can_base != RT_NULL);
+    /* Check baud rate */
+    RT_ASSERT(can->config.baud_rate != 0);
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        argval = (rt_uint32_t) arg;
+        if ((argval == RT_DEVICE_FLAG_INT_RX) || (argval == RT_DEVICE_FLAG_INT_TX))
+        {
+            /* Disable NVIC interrupt. */
+            NVIC_DisableIRQ(((nu_can_t)can)->can_irq_n);
+            /* Disable Status Change Interrupt  */
+            CAN_DisableInt(can_base, CAN_CON_IE_Msk | CAN_CON_SIE_Msk);
+
+        }
+        else if (argval == RT_DEVICE_CAN_INT_ERR)
+        {
+            /* Disable NVIC interrupt. */
+            NVIC_DisableIRQ(((nu_can_t)can)->can_irq_n);
+            /* Disable Error Interrupt */
+            CAN_DisableInt(can_base, CAN_CON_EIE_Msk);
+        }
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        argval = (rt_uint32_t) arg;
+        if (argval == RT_DEVICE_FLAG_INT_RX || (argval == RT_DEVICE_FLAG_INT_TX))
+        {
+            /* Enable Status Change Interrupt  */
+            CAN_EnableInt(can_base, CAN_CON_IE_Msk | CAN_CON_SIE_Msk);
+            /* Enable NVIC interrupt. */
+            NVIC_EnableIRQ(((nu_can_t)can)->can_irq_n);
+
+        }
+        else if (argval == RT_DEVICE_CAN_INT_ERR)
+        {
+            /* Enable Error Status and Status Change Interrupt  */
+            CAN_EnableInt(can_base, CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk);
+            /* Enable NVIC interrupt. */
+            NVIC_EnableIRQ(((nu_can_t)can)->can_irq_n);
+        }
+        break;
+
+#ifdef RT_CAN_USING_HDR
+    case RT_CAN_CMD_SET_FILTER:
+        filter_cfg = (struct rt_can_filter_config *)arg;
+
+        for (int i = 0; i < filter_cfg->count; i++)
+        {
+
+            /*set the filter message object*/
+            if (filter_cfg->items[i].mode == 1)
+            {
+                if (CAN_SetRxMsgObjAndMsk(can_base, MSG(filter_cfg->items[i].hdr + RX_MSG_ID_INDEX), filter_cfg->items[i].ide, filter_cfg->items[i].id, filter_cfg->items[i].mask, FALSE) == FALSE)
+                {
+                    return -(RT_ERROR);
+                }
+            }
+            else
+
+            {
+                /*set the filter message object*/
+                if (CAN_SetRxMsgAndMsk(can_base, MSG(filter_cfg->items[i].hdr + RX_MSG_ID_INDEX), filter_cfg->items[i].ide, filter_cfg->items[i].id, filter_cfg->items[i].mask) == FALSE)
+                {
+                    return -(RT_ERROR);
+                }
+            }
+        }
+        break;
+#endif
+
+    case RT_CAN_CMD_SET_MODE:
+        argval = (rt_uint32_t) arg;
+        if (argval != RT_CAN_MODE_NORMAL && argval != RT_CAN_MODE_LISEN &&
+                argval != RT_CAN_MODE_LOOPBACK && argval != RT_CAN_MODE_LOOPBACKANLISEN)
+        {
+            return -(RT_ERROR);
+        }
+        if (argval != can->config.mode)
+        {
+            can->config.mode = argval;
+            return nu_can_configure(can, &can->config);
+        }
+        break;
+
+    case RT_CAN_CMD_SET_BAUD:
+        argval = (rt_uint32_t) arg;
+        if (argval != CAN1MBaud && argval != CAN800kBaud && argval != CAN500kBaud && argval != CAN250kBaud &&
+                argval != CAN125kBaud && argval != CAN100kBaud && argval != CAN50kBaud  && argval != CAN20kBaud  && argval != CAN10kBaud)
+        {
+            return -(RT_ERROR);
+        }
+        if (argval != can->config.baud_rate)
+        {
+            can->config.baud_rate = argval;
+            return nu_can_configure(can, &can->config);
+        }
+        break;
+
+    case RT_CAN_CMD_SET_PRIV:
+        argval = (rt_uint32_t) arg;
+        if (argval != RT_CAN_MODE_PRIV && argval != RT_CAN_MODE_NOPRIV)
+        {
+            return -(RT_ERROR);
+        }
+        if (argval != can->config.privmode)
+        {
+            can->config.privmode = argval;
+            return nu_can_configure(can, &can->config);
+        }
+        break;
+    case RT_CAN_CMD_GET_STATUS:
+    {
+        rt_uint32_t errtype;
+        errtype = can_base->ERR;
+        /*Receive Error Counter*/
+        can->status.rcverrcnt = (errtype >> 8);
+        /*Transmit Error Counter*/
+        can->status.snderrcnt = ((errtype >> 24) & 0xFF);
+        can->status.lasterrtype = CAN_GET_INT_STATUS(can_base) & 0x8000;
+        /*status error code*/
+        can->status.errcode = CAN_GET_INT_STATUS(can_base) & 0x07;
+        rt_memcpy(arg, &can->status, sizeof(can->status));
+    }
+    break;
+    default:
+        return -(RT_EINVAL);
+
+    }
+
+    return RT_EOK;
+}
+
+static int nu_can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno)
+{
+    STR_CANMSG_T tMsg;
+    struct rt_can_msg *pmsg = (struct rt_can_msg *) buf;
+    /* Get base address of CAN register */
+    CAN_T *can_base = ((nu_can_t)can)->can_base;
+
+    RT_ASSERT(can_base != RT_NULL);
+    RT_ASSERT(buf != RT_NULL);
+    /* Check the parameters */
+    RT_ASSERT(IS_CAN_DLC(pmsg->len));
+    /* Standard ID (11 bits)*/
+    if (pmsg->ide == RT_CAN_STDID)
+    {
+        tMsg.IdType = CAN_STD_ID;
+        RT_ASSERT(IS_CAN_STDID(pmsg->id))
+        tMsg.Id  = pmsg->id ;
+    }
+    else
+    {
+        /* Extended ID (29 bits)*/
+        tMsg.IdType = CAN_EXT_ID;
+        RT_ASSERT(IS_CAN_EXTID(pmsg->id));
+        tMsg.Id = pmsg->id ;
+    }
+
+    if (pmsg->rtr == RT_CAN_DTR)
+    {
+        /* Data frame */
+        tMsg.FrameType = CAN_DATA_FRAME;
+    }
+    else
+    {
+        /* Remote frame */
+        tMsg.FrameType = CAN_REMOTE_FRAME;
+    }
+    tMsg.DLC = pmsg->len;
+    rt_memcpy(tMsg.Data, pmsg->data, pmsg->len);
+
+    if (CAN_Transmit(can_base, MSG(boxno), &tMsg) == FALSE) // Configure Msg RAM and send the Msg in the RAM
+    {
+        return -(RT_ERROR);
+    }
+
+    return RT_EOK;
+}
+static int nu_can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno)
+{
+    STR_CANMSG_T tMsg;
+    struct rt_can_msg *pmsg = (struct rt_can_msg *) buf;
+    /* Get base address of CAN register */
+    CAN_T *can_base = ((nu_can_t)can)->can_base;
+
+    RT_ASSERT(can_base != RT_NULL);
+    RT_ASSERT(buf != RT_NULL);
+
+    /* get data */
+    if (CAN_Receive(can_base, boxno, &tMsg) == FALSE)
+    {
+        rt_kprintf("No available RX Msg.\n");
+        return -(RT_ERROR);
+    }
+
+#ifdef RT_CAN_USING_HDR
+    /* Hardware filter messages are valid */
+    pmsg->hdr = boxno - RX_MSG_ID_INDEX;
+    can->hdr[pmsg->hdr].connected = 1;
+#endif
+
+    /* Standard ID (11 bits)*/
+    if (tMsg.IdType == CAN_STD_ID)
+    {
+        pmsg->ide = RT_CAN_STDID;
+        pmsg->id  = tMsg.Id;
+    }
+    else /* Extended ID (29 bits)*/
+    {
+        pmsg->ide = RT_CAN_EXTID;
+        pmsg->id  = tMsg.Id;
+    }
+
+    if (tMsg.FrameType == CAN_DATA_FRAME)
+    {
+        /* Data frame */
+        pmsg->rtr = RT_CAN_DTR;
+    }
+    else
+    {
+        /* Remote frame */
+        pmsg->rtr = RT_CAN_RTR;
+    }
+
+    pmsg->len = tMsg.DLC ;
+
+    rt_memcpy(pmsg->data, tMsg.Data, pmsg->len);
+
+    return RT_EOK;
+}
+
+/**
+ * Hardware CAN Initialization
+ */
+static int rt_hw_can_init(void)
+{
+    int i;
+    rt_err_t ret = RT_EOK;
+
+    for (i = (CAN_START + 1); i < CAN_CNT; i++)
+    {
+
+        nu_can_arr[i].dev.ops = &nu_can_ops;
+        nu_can_arr[i].dev.config = nu_can_default_config;
+
+#ifdef RT_CAN_USING_HDR
+        nu_can_arr[i].dev.config.maxhdr = RT_CANMSG_BOX_SZ;
+#endif
+        ret = rt_hw_can_register(&nu_can_arr[i].dev, nu_can_arr[i].name, &nu_can_ops, NULL);
+        RT_ASSERT(ret == RT_EOK);
+    }
+
+    return (int)ret;
+}
+INIT_DEVICE_EXPORT(rt_hw_can_init);
+#endif  //#if defined(BSP_USING_CAN)
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_clk.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_clk.c
new file mode 100644
index 0000000000..92de24a86f
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_clk.c
@@ -0,0 +1,314 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author       Notes
+* 2020-07-15      klcheng      First version
+*
+******************************************************************************/
+
+#include 
+
+#if defined(BSP_USING_CLK)
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "NuMicro.h"
+
+
+/* Private define ---------------------------------------------------------------*/
+
+/* pm run mode speed mapping */
+#define CONFIG_HIGH_SPEED_FREQ      (96000000ul)
+#define CONFIG_NORMAL_SPEED_FREQ    (96000000ul)
+#define CONFIG_MEDIMUM_SPEED_FREQ   (64000000ul)
+#define CONFIG_LOW_SPEED_FREQ       (48000000ul)
+
+/* pm sleep mode mapping */
+#define CONFIG_MODE_LIGHT           (CLK_PMUCTL_PDMSEL_FWPD)
+#define CONFIG_MODE_DEEP            (CLK_PMUCTL_PDMSEL_PD)
+#define CONFIG_MODE_STANDBY         (CLK_PMUCTL_PDMSEL_SPD)
+#define CONFIG_MODE_SHUTDOWN        (CLK_PMUCTL_PDMSEL_DPD)
+
+
+#if defined (NU_CLK_INVOKE_WKTMR)
+    /* Wake-up timer clock source is 32K */
+    #define WKTMR_INTERVAL              (CLK_PMUCTL_WKTMRIS_209715)
+#endif
+
+
+/* Timer module assigned for pm device usage. */
+/* e.g. If TIMERn is reserved for pm, then define the PM_TIMER_USE_INSTANCE
+        macro to n value (without parentheses). */
+#define PM_TIMER_USE_INSTANCE       5
+
+
+/* Concatenate */
+#define _CONCAT2_(x, y)             x##y
+#define _CONCAT3_(x, y, z)          x##y##z
+#define CONCAT2(x, y)               _CONCAT2_(x, y)
+#define CONCAT3(x, y, z)            _CONCAT3_(x,y,z)
+
+/* Concatenate the macros of timer instance for driver usage. */
+#define PM_TIMER                    CONCAT2(TIMER, PM_TIMER_USE_INSTANCE)
+#define PM_TMR                      CONCAT2(TMR, PM_TIMER_USE_INSTANCE)
+#define PM_TIMER_MODULE             CONCAT2(PM_TMR, _MODULE)
+#define PM_TIMER_IRQn               CONCAT2(PM_TMR, _IRQn)
+#define PM_TIMER_IRQHandler         CONCAT2(PM_TMR, _IRQHandler)
+#define PM_TIMER_SEL_LXT            CONCAT3(CLK_CLKSEL3_, PM_TMR, SEL_LXT)
+
+/* Private typedef --------------------------------------------------------------*/
+
+
+/* Private functions ------------------------------------------------------------*/
+static void pm_sleep(struct rt_pm *pm, rt_uint8_t mode);
+static void pm_run(struct rt_pm *pm, rt_uint8_t mode);
+static void pm_timer_start(struct rt_pm *pm, rt_uint32_t timeout);
+static void pm_timer_stop(struct rt_pm *pm);
+static rt_tick_t pm_timer_get_tick(struct rt_pm *pm);
+static rt_tick_t pm_tick_from_os_tick(rt_tick_t os_tick);
+static rt_tick_t os_tick_from_pm_tick(rt_tick_t pm_tick);
+
+/* Public functions -------------------------------------------------------------*/
+int rt_hw_pm_init(void);
+
+/* Private variables ------------------------------------------------------------*/
+static struct rt_pm_ops ops =
+{
+    .sleep = pm_sleep,
+    .run = pm_run,
+    .timer_start = pm_timer_start,
+    .timer_stop = pm_timer_stop,
+    .timer_get_tick = pm_timer_get_tick,
+};
+
+struct rt_device pm;
+
+/* Sleep and power-down mapping */
+const static uint32_t g_au32SleepingMode[PM_SLEEP_MODE_MAX] =
+{
+    0,
+    0,
+    CONFIG_MODE_LIGHT,
+    CONFIG_MODE_DEEP,
+    CONFIG_MODE_STANDBY,
+    CONFIG_MODE_SHUTDOWN
+};
+
+/* pm sleep() entry */
+static void pm_sleep(struct rt_pm *pm, rt_uint8_t mode)
+{
+    RT_ASSERT(mode < PM_SLEEP_MODE_MAX);
+
+    if ((mode == PM_SLEEP_MODE_NONE) || (mode == PM_SLEEP_MODE_IDLE))
+        return;
+
+    /*  wake-up source:                                                    */
+    /*      PM_SLEEP_MODE_LIGHT : TIMERn                                   */
+    /*      PM_SLEEP_MODE_DEEP : TIMERn                                    */
+    /*      PM_SLEEP_MODE_STANDBY : wake-up timer  (optional)              */
+    /*      PM_SLEEP_MODE_SHUTDOWN : wake-up timer  (optional)             */
+
+    SYS_UnlockReg();
+
+#if defined (NU_CLK_INVOKE_WKTMR)
+    if ((mode == PM_SLEEP_MODE_SHUTDOWN) || (mode == PM_SLEEP_MODE_STANDBY))
+    {
+        /* Enable wake-up timer with pre-defined interval if it is invoked */
+        CLK_SET_WKTMR_INTERVAL(WKTMR_INTERVAL);
+        CLK_ENABLE_WKTMR();
+    }
+#endif
+
+    /* Set Power-down Mode */
+    CLK_SetPowerDownMode(g_au32SleepingMode[mode]);
+
+    /* Here, take a break. */
+    CLK_PowerDown();
+
+    SYS_LockReg();
+}
+
+
+/* pm run() entry */
+static void pm_run(struct rt_pm *pm, rt_uint8_t mode)
+{
+    static uint8_t prev_mode = RT_PM_DEFAULT_RUN_MODE;
+
+    /* ignore it if power mode is the same. */
+    if (mode == prev_mode)
+        return;
+
+    prev_mode = mode;
+
+    SYS_UnlockReg();
+
+    /* Switch run mode frequency using PLL + HXT if HXT is enabled.
+       Otherwise, the system clock will use PLL + HIRC. */
+    switch (mode)
+    {
+    case PM_RUN_MODE_HIGH_SPEED:
+
+        CLK_SetCoreClock(CONFIG_HIGH_SPEED_FREQ);
+        break;
+
+    case PM_RUN_MODE_NORMAL_SPEED:
+
+        CLK_SetCoreClock(CONFIG_NORMAL_SPEED_FREQ);
+        break;
+
+    case PM_RUN_MODE_MEDIUM_SPEED:
+
+        CLK_SetCoreClock(CONFIG_MEDIMUM_SPEED_FREQ);
+        break;
+
+    case PM_RUN_MODE_LOW_SPEED:
+
+        CLK_SetCoreClock(CONFIG_LOW_SPEED_FREQ);
+        break;
+
+    default:
+        RT_ASSERT(0);
+        break;
+    }
+
+    SystemCoreClockUpdate();
+    SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+
+    SYS_LockReg();
+}
+
+
+static void hw_timer_init(void)
+{
+    /* Assign a hardware timer for pm usage. */
+    SYS_UnlockReg();
+    CLK_SetModuleClock(PM_TIMER_MODULE, PM_TIMER_SEL_LXT, MODULE_NoMsk);
+    CLK_EnableModuleClock(PM_TIMER_MODULE);
+    SYS_LockReg();
+
+    /* Initialize timer and enable wakeup function. */
+    TIMER_Open(PM_TIMER, TIMER_CONTINUOUS_MODE, 1);
+    TIMER_SET_PRESCALE_VALUE(PM_TIMER, 0);
+    TIMER_EnableInt(PM_TIMER);
+    TIMER_EnableWakeup(PM_TIMER);
+    NVIC_EnableIRQ(PM_TIMER_IRQn);
+}
+
+
+/* convert os tick to pm timer tick */
+static rt_tick_t pm_tick_from_os_tick(rt_tick_t os_tick)
+{
+    rt_uint32_t hz = TIMER_GetModuleClock(PM_TIMER);
+
+    return (rt_tick_t)(hz * os_tick / RT_TICK_PER_SECOND);
+}
+
+
+/* convert pm timer tick to os tick */
+static rt_tick_t os_tick_from_pm_tick(rt_tick_t pm_tick)
+{
+    static rt_uint32_t os_tick_remain = 0;
+    rt_uint32_t ret, hz;
+
+    hz = TIMER_GetModuleClock(PM_TIMER);
+    ret = (pm_tick * RT_TICK_PER_SECOND + os_tick_remain) / hz;
+
+    os_tick_remain += (pm_tick * RT_TICK_PER_SECOND);
+    os_tick_remain %= hz;
+
+    return ret;
+}
+
+
+/* pm_ops timer_get_tick() entry */
+static rt_tick_t pm_timer_get_tick(struct rt_pm *pm)
+{
+    rt_tick_t tick;
+
+    tick = TIMER_GetCounter(PM_TIMER);
+
+    return os_tick_from_pm_tick(tick);
+}
+
+
+/* pm timer_start() entry */
+static void pm_timer_start(struct rt_pm *pm, rt_uint32_t timeout)
+{
+    int tick;
+
+    if (timeout == RT_TICK_MAX)
+        return;
+
+    /* start pm timer to compensate the os tick in power down mode */
+    tick = pm_tick_from_os_tick(timeout);
+    TIMER_SET_CMP_VALUE(PM_TIMER, tick);
+    TIMER_Start(PM_TIMER);
+}
+
+
+/* pm timer_stop() entry */
+static void pm_timer_stop(struct rt_pm *pm)
+{
+    TIMER_Stop(PM_TIMER);
+    TIMER_ResetCounter(PM_TIMER);
+}
+
+
+/* pm device driver initialize. */
+int rt_hw_pm_init(void)
+{
+    rt_uint8_t timer_mask;
+
+    if (CLK_GetPMUWKSrc())
+    {
+        /* Release I/O hold status after wake-up from Standby Power-down Mode (SPD) */
+        CLK->IOPDCTL = 1;
+
+        /* Clear Power Manager Status register */
+        CLK->PMUSTS = CLK_PMUSTS_CLRWK_Msk;
+    }
+
+    hw_timer_init();
+
+    /* initialize timer mask */
+    timer_mask = (1UL << PM_SLEEP_MODE_LIGHT) |
+                 (1UL << PM_SLEEP_MODE_DEEP);
+
+    /* initialize system pm module */
+    rt_system_pm_init(&ops, timer_mask, RT_NULL);
+
+    return RT_EOK;
+}
+INIT_BOARD_EXPORT(rt_hw_pm_init);
+
+extern void rt_pm_exit_critical(rt_uint32_t ctx, rt_uint8_t sleep_mode);
+void rt_pm_exit_critical(rt_uint32_t ctx, rt_uint8_t sleep_mode)
+{
+    if ( (sleep_mode==PM_SLEEP_MODE_LIGHT) || (sleep_mode==PM_SLEEP_MODE_DEEP) )
+    {
+        if (TIMER_GetIntFlag(PM_TIMER))
+        {
+            TIMER_ClearIntFlag(PM_TIMER);
+        }
+
+        if (TIMER_GetWakeupFlag(PM_TIMER))
+        {
+            TIMER_ClearWakeupFlag(PM_TIMER);
+        }
+
+        NVIC_ClearPendingIRQ(PM_TIMER_IRQn);
+    }
+
+    rt_hw_interrupt_enable(ctx);
+}
+
+#endif /* BSP_USING_CLK */
+
+
+
diff --git a/bsp/nuvoton/numaker-pfm-m487/board/board.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_common.c
similarity index 63%
rename from bsp/nuvoton/numaker-pfm-m487/board/board.c
rename to bsp/nuvoton/libraries/m2354/rtt_port/drv_common.c
index 01d68aca61..1dbd98f187 100644
--- a/bsp/nuvoton/numaker-pfm-m487/board/board.c
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_common.c
@@ -12,17 +12,19 @@
 
 #include 
 #include 
-#include 
+#include "NuMicro.h"
+#include 
 #include "drv_uart.h"
 #include "board.h"
 #include "nutool_pincfg.h"
 #include "nutool_modclkcfg.h"
 
 
+
 /**
  * This function will initial M487 board.
  */
-void rt_hw_board_init(void)
+RT_WEAK void rt_hw_board_init(void)
 {
     /* Init System/modules clock */
     nutool_modclkcfg_init();
@@ -60,13 +62,46 @@ void rt_hw_board_init(void)
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
 
-    NVIC_SetPriorityGrouping(7);
-
 #ifdef RT_USING_COMPONENTS_INIT
     rt_components_board_init();
 #endif
 }
 
+/**
+ * The time delay function.
+ *
+ * @param microseconds.
+ */
+void rt_hw_us_delay(rt_uint32_t us)
+{
+    rt_uint32_t ticks;
+    rt_uint32_t told, tnow, tcnt = 0;
+    rt_uint32_t reload = SysTick->LOAD;
+
+    ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
+    told = SysTick->VAL;
+    while (1)
+    {
+        tnow = SysTick->VAL;
+        if (tnow != told)
+        {
+            if (tnow < told)
+            {
+                tcnt += told - tnow;
+            }
+            else
+            {
+                tcnt += reload - tnow + told;
+            }
+            told = tnow;
+            if (tcnt >= ticks)
+            {
+                break;
+            }
+        }
+    }
+}
+
 /**
  * This is the timer interrupt service routine.
  *
@@ -89,9 +124,20 @@ void rt_hw_cpu_reset(void)
     SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk;
 }
 
-int reboot(int argc, char** argv)
+#ifdef RT_USING_CPU_FFS
+int __rt_ffs(int value)
+{
+    if (!value) return 0;
+    return __CLZ(__RBIT(value)) + 1;
+}
+#endif
+
+#ifdef RT_USING_FINSH
+#include 
+static void reboot(uint8_t argc, char **argv)
 {
     rt_hw_cpu_reset();
-    return 0;
 }
-MSH_CMD_EXPORT(reboot, Reboot System);
+FINSH_FUNCTION_EXPORT_ALIAS(reboot, __cmd_reboot, Reboot System);
+#endif /* RT_USING_FINSH */
+
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_crc.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_crc.c
new file mode 100644
index 0000000000..11051deef0
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_crc.c
@@ -0,0 +1,137 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-7-4        YCHuang12        First version
+*
+******************************************************************************/
+
+#include 
+
+#if (defined(BSP_USING_CRC) && defined(RT_HWCRYPTO_USING_CRC))
+
+#include 
+
+#include 
+#include 
+
+#include "NuMicro.h"
+#include "drv_pdma.h"
+
+/* Private define ---------------------------------------------------------------*/
+#define NU_CRYPTO_CRC_NAME  "nu_CRC"
+
+#define CRC_32_POLY     0x04C11DB7
+#define CRC_CCITT_POLY  0x00001021
+#define CRC_16_POLY     0x00008005
+#define CRC_8_POLY      0x00000007
+
+/* Private variables ------------------------------------------------------------*/
+
+static struct rt_mutex s_CRC_mutex;
+
+static rt_uint32_t nu_crc_run(
+    uint32_t u32OpMode,
+    uint32_t u32Seed,
+    uint32_t u32Attr,
+    uint8_t *pu8InData,
+    uint32_t u32DataLen
+)
+{
+    uint32_t u32CalChecksum = 0;
+    uint32_t i = 0;
+
+    rt_mutex_take(&s_CRC_mutex, RT_WAITING_FOREVER);
+
+    /* Configure CRC controller  */
+    CRC_Open(u32OpMode, u32Attr, u32Seed, CRC_CPU_WDATA_8);
+
+    uint8_t *pu8InTempData = pu8InData;
+
+    while (i < u32DataLen)
+    {
+        if (((((uint32_t)pu8InTempData) % 4) != 0) || (u32DataLen - i < 4))
+        {
+            CRC->CTL &= ~CRC_CTL_DATLEN_Msk;
+            CRC_WRITE_DATA(CRC, (*pu8InTempData) & 0xFF);
+            pu8InTempData ++;
+            i++;
+        }
+        else
+        {
+            CRC->CTL &= ~CRC_CTL_DATLEN_Msk;
+            CRC->CTL |= CRC_CPU_WDATA_32;
+#if defined (NU_CRC_USE_PDMA)
+            int32_t i32PDMATransCnt = (u32DataLen - i) / 4 ;
+
+            i32PDMATransCnt = nu_pdma_mempush((void *)&CRC->DAT, pu8InTempData, 32, i32PDMATransCnt);
+
+            if (i32PDMATransCnt > 0)
+            {
+                pu8InTempData += (i32PDMATransCnt * 4);
+                i += (i32PDMATransCnt * 4);
+            }
+#else
+            CRC_WRITE_DATA(CRC, *(uint32_t *)pu8InTempData);
+            pu8InTempData += 4;
+            i += 4;
+#endif
+        }
+    }
+
+    /* Get checksum value */
+    u32CalChecksum = CRC_GetChecksum();
+    rt_mutex_release(&s_CRC_mutex);
+
+    return u32CalChecksum;
+}
+
+rt_err_t nu_crc_init(void)
+{
+    SYS_ResetModule(CRC_RST);
+
+    rt_mutex_init(&s_CRC_mutex, NU_CRYPTO_CRC_NAME, RT_IPC_FLAG_FIFO);
+    return RT_EOK;
+}
+
+rt_uint32_t nu_crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, rt_size_t length)
+{
+    uint32_t u32OpMode;
+    uint32_t u32CRCAttr = 0;
+    rt_uint32_t crc_result = 0;
+
+    //select CRC operation mode
+    switch (ctx->crc_cfg.poly)
+    {
+    case CRC_32_POLY:
+        u32OpMode = CRC_32;
+        break;
+    case CRC_CCITT_POLY:
+        u32OpMode = CRC_CCITT;
+        break;
+    case CRC_16_POLY:
+        u32OpMode = CRC_16;
+        break;
+    case CRC_8_POLY:
+        u32OpMode = CRC_8;
+        break;
+    default:
+        return 0;
+    }
+
+    u32CRCAttr |= (ctx->crc_cfg.flags & CRC_FLAG_REFOUT) ? CRC_CHECKSUM_RVS : 0; //CRC Checksum Reverse
+    u32CRCAttr |= (ctx->crc_cfg.flags & CRC_FLAG_REFIN) ? CRC_WDATA_RVS : 0;  //CRC Write Data Reverse
+
+    //Calculate CRC checksum, using config's last value as CRC seed
+    crc_result = nu_crc_run(u32OpMode, ctx->crc_cfg.last_val, u32CRCAttr, (uint8_t *)in, length);
+
+    //update CRC result to config's last value
+    ctx->crc_cfg.last_val = crc_result;
+    return crc_result ^ 0x00 ^ ctx->crc_cfg.xorout;
+}
+
+#endif //#if (defined(BSP_USING_CRC) && defined(RT_HWCRYPTO_USING_CRC))
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_crc.h b/bsp/nuvoton/libraries/m2354/rtt_port/drv_crc.h
new file mode 100644
index 0000000000..6aad63b638
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_crc.h
@@ -0,0 +1,20 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-7-4        YCHuang12        First version
+*
+******************************************************************************/
+
+#ifndef __DRV_CRC_H__
+#define __DRV_CRC_H__
+
+rt_err_t nu_crc_init(void);
+
+rt_uint32_t nu_crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, rt_size_t length);
+
+#endif
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_crypto.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_crypto.c
new file mode 100644
index 0000000000..c528cdc100
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_crypto.c
@@ -0,0 +1,822 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author         Notes
+* 2020-7-3        YCHuang12      First version
+*
+******************************************************************************/
+
+#include 
+
+#if ((defined(BSP_USING_CRYPTO) || defined(BSP_USING_TRNG) || defined(BSP_USING_CRC)) && defined(RT_USING_HWCRYPTO))
+
+#include 
+#include 
+#include 
+#include "NuMicro.h"
+#include 
+
+#if defined(BSP_USING_TRNG)
+    #include "drv_trng.h"
+#endif
+
+#if defined(BSP_USING_CRC)
+    #include "drv_crc.h"
+#endif
+
+/* Private typedef --------------------------------------------------------------*/
+typedef struct
+{
+    uint8_t *pu8SHATempBuf;
+    uint32_t u32SHATempBufLen;
+    uint32_t u32DMAMode;
+    uint32_t u32BlockSize;
+} S_SHA_CONTEXT;
+
+
+/* Private functions ------------------------------------------------------------*/
+static rt_err_t nu_hwcrypto_create(struct rt_hwcrypto_ctx *ctx);
+static void nu_hwcrypto_destroy(struct rt_hwcrypto_ctx *ctx);
+static rt_err_t nu_hwcrypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcrypto_ctx *src);
+static void nu_hwcrypto_reset(struct rt_hwcrypto_ctx *ctx);
+
+/* Private variables ------------------------------------------------------------*/
+static const struct rt_hwcrypto_ops nu_hwcrypto_ops =
+{
+    .create = nu_hwcrypto_create,
+    .destroy = nu_hwcrypto_destroy,
+    .copy = nu_hwcrypto_clone,
+    .reset = nu_hwcrypto_reset,
+};
+
+/* Crypto engine operation ------------------------------------------------------------*/
+#if defined(BSP_USING_CRYPTO)
+
+#define NU_HWCRYPTO_AES_NAME    "nu_AES"
+#define NU_HWCRYPTO_SHA_NAME    "nu_SHA"
+#if !defined(BSP_USING_TRNG)
+    #define NU_HWCRYPTO_PRNG_NAME   "nu_PRNG"
+#endif
+
+static struct rt_mutex s_AES_mutex;
+static struct rt_mutex s_SHA_mutex;
+
+#if !defined(BSP_USING_TRNG)
+    static struct rt_mutex s_PRNG_mutex;
+    static volatile int s_PRNG_done;
+#endif
+
+static volatile int s_AES_done;
+static volatile int s_SHA_done;
+
+static rt_err_t nu_crypto_init(void)
+{
+    /* Enable Crypto engine interrupt */
+    NVIC_EnableIRQ(CRPT_IRQn);
+
+    AES_ENABLE_INT(CRPT);
+    SHA_ENABLE_INT(CRPT);
+
+    //init cipher mutex
+    rt_mutex_init(&s_AES_mutex, NU_HWCRYPTO_AES_NAME, RT_IPC_FLAG_FIFO);
+    rt_mutex_init(&s_SHA_mutex, NU_HWCRYPTO_SHA_NAME, RT_IPC_FLAG_FIFO);
+#if !defined(BSP_USING_TRNG)
+    PRNG_ENABLE_INT(CRPT);
+    rt_mutex_init(&s_PRNG_mutex, NU_HWCRYPTO_PRNG_NAME, RT_IPC_FLAG_FIFO);
+#endif
+
+    return RT_EOK;
+}
+
+//Crypto engine IRQ handler
+void CRPT_IRQHandler()
+{
+    if (AES_GET_INT_FLAG(CRPT))
+    {
+        if (CRPT->INTSTS & (CRPT_INTSTS_AESEIF_Msk) || (CRPT->AES_STS & (CRPT_AES_STS_BUSERR_Msk | CRPT_AES_STS_CNTERR_Msk | (0x1ul << 21))))
+            rt_kprintf("AES ERROR\n");
+        s_AES_done = 1;
+        AES_CLR_INT_FLAG(CRPT);
+    }
+
+    if (SHA_GET_INT_FLAG(CRPT))
+    {
+        if (CRPT->INTSTS & (CRPT_INTSTS_HMACEIF_Msk) || (CRPT->HMAC_STS & (CRPT_HMAC_STS_DMAERR_Msk | (0x1ul << 9))))
+            rt_kprintf("SHA ERROR\n");
+        s_SHA_done = 1;
+        SHA_CLR_INT_FLAG(CRPT);
+    }
+
+#if !defined(BSP_USING_TRNG)
+    if (PRNG_GET_INT_FLAG(CRPT))
+    {
+        s_PRNG_done = 1;
+        PRNG_CLR_INT_FLAG(CRPT);
+    }
+#endif
+}
+
+static rt_err_t nu_aes_crypt_run(
+    rt_bool_t bEncrypt,
+    uint32_t u32OpMode,
+    uint8_t *pu8Key,
+    uint32_t u32KeySize,
+    uint8_t *pu8IV,
+    uint8_t *pu8InData,
+    uint8_t *pu8OutData,
+    uint32_t u32DataLen
+)
+{
+    uint32_t au32SwapKey[8];
+    uint32_t au32SwapIV[4];
+
+    au32SwapKey[0] = nu_get32_be(&pu8Key[0]);
+    au32SwapKey[1] = nu_get32_be(&pu8Key[4]);
+    au32SwapKey[2] = nu_get32_be(&pu8Key[8]);
+    au32SwapKey[3] = nu_get32_be(&pu8Key[12]);
+
+    if ((u32KeySize == AES_KEY_SIZE_192) || (u32KeySize == AES_KEY_SIZE_256))
+    {
+        au32SwapKey[4] = nu_get32_be(&pu8Key[16]);
+        au32SwapKey[5] = nu_get32_be(&pu8Key[20]);
+    }
+
+    if (u32KeySize == AES_KEY_SIZE_256)
+    {
+        au32SwapKey[6] = nu_get32_be(&pu8Key[24]);
+        au32SwapKey[7] = nu_get32_be(&pu8Key[28]);
+    }
+
+    au32SwapIV[0] = nu_get32_be(&pu8IV[0]);
+    au32SwapIV[1] = nu_get32_be(&pu8IV[4]);
+    au32SwapIV[2] = nu_get32_be(&pu8IV[8]);
+    au32SwapIV[3] = nu_get32_be(&pu8IV[12]);
+
+    rt_mutex_take(&s_AES_mutex, RT_WAITING_FOREVER);
+
+    //Using Channel 0
+    AES_Open(CRPT, 0, bEncrypt, u32OpMode, u32KeySize, AES_IN_OUT_SWAP);
+    AES_SetKey(CRPT, 0, (uint32_t *)au32SwapKey, u32KeySize);
+    AES_SetInitVect(CRPT, 0, (uint32_t *)au32SwapIV);
+
+    //Setup AES DMA
+    AES_SetDMATransfer(CRPT, 0, (uint32_t)pu8InData, (uint32_t)pu8OutData, u32DataLen);
+    AES_CLR_INT_FLAG(CRPT);
+    //Start AES encryption/decryption
+    s_AES_done = 0;
+    AES_Start(CRPT, 0, CRYPTO_DMA_ONE_SHOT);
+    while (!s_AES_done) {};
+
+    rt_mutex_release(&s_AES_mutex);
+
+    return RT_EOK;
+}
+
+#if !defined(BSP_USING_TRNG)
+//Using PRNG instead of TRNG
+static void nu_prng_open(uint32_t u32Seed)
+{
+    rt_mutex_take(&s_PRNG_mutex, RT_WAITING_FOREVER);
+
+    //Open PRNG 128 bits. But always return 32 bits
+    PRNG_Open(CRPT, PRNG_KEY_SIZE_128, PRNG_SEED_RELOAD, u32Seed);
+
+    rt_mutex_release(&s_PRNG_mutex);
+}
+
+static rt_uint32_t nu_prng_run(void)
+{
+    uint32_t au32RNGValue[2];
+
+    rt_mutex_take(&s_PRNG_mutex, RT_WAITING_FOREVER);
+
+    s_PRNG_done = 0;
+    PRNG_Start(CRPT);
+    while (!s_PRNG_done) {};
+
+    PRNG_Read(CRPT, au32RNGValue);
+
+    rt_mutex_release(&s_PRNG_mutex);
+    return au32RNGValue[0];
+}
+
+#endif
+
+static rt_err_t nu_aes_crypt(struct hwcrypto_symmetric *symmetric_ctx, struct hwcrypto_symmetric_info *symmetric_info)
+{
+    uint32_t u32AESOpMode;
+    uint32_t u32AESKeySize;
+    unsigned char *in, *out;
+    unsigned char in_align_flag = 0;
+    unsigned char out_align_flag = 0;
+    unsigned char iv_temp[16];
+
+    if ((symmetric_info->length % 4) != 0)
+    {
+        return -RT_EINVAL;
+    }
+
+    //Checking key length
+    if (symmetric_ctx->key_bitlen == 128)
+    {
+        u32AESKeySize = AES_KEY_SIZE_128;
+    }
+    else if (symmetric_ctx->key_bitlen == 192)
+    {
+        u32AESKeySize = AES_KEY_SIZE_192;
+    }
+    else if (symmetric_ctx->key_bitlen == 256)
+    {
+        u32AESKeySize = AES_KEY_SIZE_256;
+    }
+    else
+    {
+        return -RT_EINVAL;
+    }
+
+    //Select AES operation mode
+    switch (symmetric_ctx->parent.type & (HWCRYPTO_MAIN_TYPE_MASK | HWCRYPTO_SUB_TYPE_MASK))
+    {
+    case HWCRYPTO_TYPE_AES_ECB:
+        u32AESOpMode = AES_MODE_ECB;
+        break;
+    case HWCRYPTO_TYPE_AES_CBC:
+        u32AESOpMode = AES_MODE_CBC;
+        break;
+    case HWCRYPTO_TYPE_AES_CFB:
+        u32AESOpMode = AES_MODE_CFB;
+        break;
+    case HWCRYPTO_TYPE_AES_OFB:
+        u32AESOpMode = AES_MODE_OFB;
+        break;
+    case HWCRYPTO_TYPE_AES_CTR:
+        u32AESOpMode = AES_MODE_CTR;
+        break;
+    default :
+        return -RT_ERROR;
+    }
+
+    in = (unsigned char *)symmetric_info->in;
+    out = (unsigned char *)symmetric_info->out;
+
+    //Checking in/out data buffer address not alignment or out of SRAM
+    if (((rt_uint32_t)in % 4) != 0 || ((rt_uint32_t)in < SRAM_BASE) || ((rt_uint32_t)in > SRAM_END))
+    {
+        in = rt_malloc(symmetric_info->length);
+        if (in == RT_NULL)
+        {
+            LOG_E("fun[%s] memory allocate %d bytes failed!", __FUNCTION__, symmetric_info->length);
+            return -RT_ENOMEM;
+        }
+
+        rt_memcpy(in, symmetric_info->in, symmetric_info->length);
+        in_align_flag = 1;
+    }
+
+    if (((rt_uint32_t)out % 4) != 0 || ((rt_uint32_t)out < SRAM_BASE) || ((rt_uint32_t)out > SRAM_END))
+    {
+        out = rt_malloc(symmetric_info->length);
+        if (out == RT_NULL)
+        {
+            if (in_align_flag)
+                rt_free(in);
+            LOG_E("fun[%s] memory allocate %d bytes failed!", __FUNCTION__, symmetric_info->length);
+            return -RT_ENOMEM;
+        }
+
+        out_align_flag = 1;
+    }
+
+    if ((u32AESOpMode == AES_MODE_CBC) && (symmetric_info->mode == HWCRYPTO_MODE_DECRYPT))
+    {
+        uint32_t loop;
+
+        loop = (symmetric_info->length - 1) / 16;
+        rt_memcpy(iv_temp, in + (loop * 16), 16);
+    }
+
+    nu_aes_crypt_run(symmetric_info->mode == HWCRYPTO_MODE_ENCRYPT ? TRUE : FALSE, u32AESOpMode, symmetric_ctx->key, u32AESKeySize, symmetric_ctx->iv, in, out, symmetric_info->length);
+
+    if (u32AESOpMode == AES_MODE_CBC)
+    {
+        if (symmetric_info->mode == HWCRYPTO_MODE_DECRYPT)
+        {
+            rt_memcpy(symmetric_ctx->iv, iv_temp, 16);
+        }
+        else
+        {
+            uint32_t loop;
+
+            loop = (symmetric_info->length - 1) / 16;
+            rt_memcpy(symmetric_ctx->iv, out + (loop * 16), 16);
+        }
+    }
+
+    if (out_align_flag)
+    {
+        rt_memcpy(symmetric_info->out, out, symmetric_info->length);
+        rt_free(out);
+    }
+
+    if (in_align_flag)
+    {
+        rt_free(in);
+    }
+
+    return RT_EOK;
+}
+
+static void SHABlockUpdate(uint32_t u32OpMode, uint32_t u32SrcAddr, uint32_t u32Len, uint32_t u32Mode)
+{
+    SHA_Open(CRPT, u32OpMode, SHA_IN_OUT_SWAP, 0);
+
+    //Setup SHA DMA
+    SHA_SetDMATransfer(CRPT, u32SrcAddr, u32Len);
+    SHA_CLR_INT_FLAG(CRPT);
+
+    //Start SHA
+    s_SHA_done = 0;
+
+    if (u32Mode == CRYPTO_DMA_FIRST)
+        CRPT->HMAC_CTL |= CRPT_HMAC_CTL_DMAFIRST_Msk;
+    else
+        CRPT->HMAC_CTL &= ~CRPT_HMAC_CTL_DMAFIRST_Msk;
+    SHA_Start(CRPT, u32Mode);
+
+    while (!s_SHA_done) {};
+}
+
+static rt_err_t nu_sha_hash_run(
+    S_SHA_CONTEXT *psSHACtx,
+    uint32_t u32OpMode,
+    uint8_t *pu8InData,
+    uint32_t u32DataLen
+)
+{
+    rt_mutex_take(&s_SHA_mutex, RT_WAITING_FOREVER);
+
+    uint8_t *pu8SrcAddr = (uint8_t *)pu8InData;
+    uint32_t u32CopyLen = 0;
+
+    while ((psSHACtx->u32SHATempBufLen + u32DataLen) >= psSHACtx->u32BlockSize)
+    {
+        if (psSHACtx->pu8SHATempBuf)
+        {
+            if (psSHACtx->u32SHATempBufLen == psSHACtx->u32BlockSize)
+            {
+                //Trigger SHA block update
+                SHABlockUpdate(u32OpMode, (uint32_t)psSHACtx->pu8SHATempBuf, psSHACtx->u32BlockSize, psSHACtx->u32DMAMode);
+                psSHACtx->u32DMAMode = CRYPTO_DMA_CONTINUE;
+                //free SHATempBuff
+                rt_free(psSHACtx->pu8SHATempBuf);
+                psSHACtx->pu8SHATempBuf = NULL;
+                psSHACtx->u32SHATempBufLen = 0;
+                continue;
+            }
+            else
+            {
+                u32CopyLen = psSHACtx->u32BlockSize - psSHACtx->u32SHATempBufLen;
+                if (u32DataLen < u32CopyLen)
+                    u32CopyLen = u32DataLen;
+                rt_memcpy(psSHACtx->pu8SHATempBuf + psSHACtx->u32SHATempBufLen, pu8SrcAddr, u32CopyLen);
+                psSHACtx->u32SHATempBufLen += u32CopyLen;
+                pu8SrcAddr += u32CopyLen;
+                u32DataLen -= u32CopyLen;
+                continue;
+            }
+        }
+
+        if ((uint32_t) pu8SrcAddr & 3)  //address not aligned 4
+        {
+            psSHACtx->pu8SHATempBuf = rt_malloc(psSHACtx->u32BlockSize);
+
+            if (psSHACtx->pu8SHATempBuf == RT_NULL)
+            {
+                LOG_E("fun[%s] memory allocate %d bytes failed!", __FUNCTION__, psSHACtx->u32BlockSize);
+                rt_mutex_release(&s_SHA_mutex);
+                return -RT_ENOMEM;
+            }
+
+            rt_memcpy(psSHACtx->pu8SHATempBuf, pu8SrcAddr, psSHACtx->u32BlockSize);
+            psSHACtx->u32SHATempBufLen = psSHACtx->u32BlockSize;
+            pu8SrcAddr += psSHACtx->u32BlockSize;
+            u32DataLen -= psSHACtx->u32BlockSize;
+            continue;
+        }
+
+        //Trigger SHA block update
+        SHABlockUpdate(u32OpMode, (uint32_t)pu8SrcAddr, psSHACtx->u32BlockSize, psSHACtx->u32DMAMode);
+        psSHACtx->u32DMAMode = CRYPTO_DMA_CONTINUE;
+
+        pu8SrcAddr += psSHACtx->u32BlockSize;
+        u32DataLen -= psSHACtx->u32BlockSize;
+    }
+
+    if (u32DataLen)
+    {
+        if (psSHACtx->pu8SHATempBuf == NULL)
+        {
+            psSHACtx->pu8SHATempBuf = rt_malloc(psSHACtx->u32BlockSize);
+
+            if (psSHACtx->pu8SHATempBuf == RT_NULL)
+            {
+                LOG_E("fun[%s] memory allocate %d bytes failed!", __FUNCTION__, psSHACtx->u32BlockSize);
+                rt_mutex_release(&s_SHA_mutex);
+                return -RT_ENOMEM;
+            }
+
+            psSHACtx->u32SHATempBufLen = 0;
+        }
+
+        rt_memcpy(psSHACtx->pu8SHATempBuf, pu8SrcAddr, u32DataLen);
+        psSHACtx->u32SHATempBufLen += u32DataLen;
+    }
+
+    rt_mutex_release(&s_SHA_mutex);
+
+    return RT_EOK;
+}
+
+static rt_err_t nu_sha_update(struct hwcrypto_hash *hash_ctx, const rt_uint8_t *in, rt_size_t length)
+{
+    uint32_t u32SHAOpMode;
+    unsigned char *nu_in;
+    unsigned char in_align_flag = 0;
+
+    //Select SHA operation mode
+    switch (hash_ctx->parent.type & (HWCRYPTO_MAIN_TYPE_MASK | HWCRYPTO_SUB_TYPE_MASK))
+    {
+    case HWCRYPTO_TYPE_SHA1:
+        u32SHAOpMode = SHA_MODE_SHA1;
+        break;
+    case HWCRYPTO_TYPE_SHA224:
+        u32SHAOpMode = SHA_MODE_SHA224;
+        break;
+    case HWCRYPTO_TYPE_SHA256:
+        u32SHAOpMode = SHA_MODE_SHA256;
+        break;
+    case HWCRYPTO_TYPE_SHA384:
+        u32SHAOpMode = SHA_MODE_SHA384;
+        break;
+    case HWCRYPTO_TYPE_SHA512:
+        u32SHAOpMode = SHA_MODE_SHA512;
+        break;
+    default :
+        return -RT_ERROR;
+    }
+
+    nu_in = (unsigned char *)in;
+
+    //Checking in data buffer address not alignment or out of SRAM
+    if (((rt_uint32_t)nu_in % 4) != 0 || ((rt_uint32_t)nu_in < SRAM_BASE) || ((rt_uint32_t)nu_in > SRAM_END))
+    {
+        nu_in = rt_malloc(length);
+        if (nu_in == RT_NULL)
+        {
+            LOG_E("fun[%s] memory allocate %d bytes failed!", __FUNCTION__, length);
+            return -RT_ENOMEM;
+        }
+
+        rt_memcpy(nu_in, in, length);
+        in_align_flag = 1;
+    }
+
+    nu_sha_hash_run(hash_ctx->parent.contex, u32SHAOpMode, nu_in, length);
+
+    if (in_align_flag)
+    {
+        rt_free(nu_in);
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t nu_sha_finish(struct hwcrypto_hash *hash_ctx, rt_uint8_t *out, rt_size_t length)
+{
+    unsigned char *nu_out;
+    unsigned char out_align_flag = 0;
+    uint32_t u32SHAOpMode;
+    S_SHA_CONTEXT *psSHACtx = hash_ctx->parent.contex;
+
+    //Check SHA Hash value buffer length
+    switch (hash_ctx->parent.type & (HWCRYPTO_MAIN_TYPE_MASK | HWCRYPTO_SUB_TYPE_MASK))
+    {
+    case HWCRYPTO_TYPE_SHA1:
+        u32SHAOpMode = SHA_MODE_SHA1;
+        if (length < 5UL)
+        {
+            return -RT_EINVAL;
+        }
+        break;
+    case HWCRYPTO_TYPE_SHA224:
+        u32SHAOpMode = SHA_MODE_SHA224;
+        if (length < 7UL)
+        {
+            return -RT_EINVAL;
+        }
+        break;
+    case HWCRYPTO_TYPE_SHA256:
+        u32SHAOpMode = SHA_MODE_SHA256;
+        if (length < 8UL)
+        {
+            return -RT_EINVAL;
+        }
+        break;
+    case HWCRYPTO_TYPE_SHA384:
+        u32SHAOpMode = SHA_MODE_SHA384;
+        if (length < 12UL)
+        {
+            return -RT_EINVAL;
+        }
+        break;
+    case HWCRYPTO_TYPE_SHA512:
+        u32SHAOpMode = SHA_MODE_SHA512;
+        if (length < 16UL)
+        {
+            return -RT_EINVAL;
+        }
+        break;
+    default :
+        return -RT_ERROR;
+    }
+
+    nu_out = (unsigned char *)out;
+
+    //Checking out data buffer address alignment or not
+    if (((rt_uint32_t)nu_out % 4) != 0)
+    {
+        nu_out = rt_malloc(length);
+        if (nu_out == RT_NULL)
+        {
+            LOG_E("fun[%s] memory allocate %d bytes failed!", __FUNCTION__, length);
+            return -RT_ENOMEM;
+        }
+
+        out_align_flag = 1;
+    }
+
+    if (psSHACtx->pu8SHATempBuf)
+    {
+        if (psSHACtx->u32DMAMode ==  CRYPTO_DMA_FIRST)
+            SHABlockUpdate(u32SHAOpMode, (uint32_t)psSHACtx->pu8SHATempBuf, psSHACtx->u32SHATempBufLen, CRYPTO_DMA_ONE_SHOT);
+        else
+            SHABlockUpdate(u32SHAOpMode, (uint32_t)psSHACtx->pu8SHATempBuf, psSHACtx->u32SHATempBufLen, CRYPTO_DMA_LAST);
+
+        //free SHATempBuf
+        rt_free(psSHACtx->pu8SHATempBuf);
+        psSHACtx->pu8SHATempBuf = RT_NULL;
+        psSHACtx->u32SHATempBufLen = 0;
+    }
+    else
+    {
+        SHABlockUpdate(u32SHAOpMode, (uint32_t)NULL, 0, CRYPTO_DMA_LAST);
+    }
+
+    SHA_Read(CRPT, (uint32_t *)nu_out);
+
+    if (out_align_flag)
+    {
+        rt_memcpy(out, nu_out, length);
+        rt_free(nu_out);
+    }
+
+    return RT_EOK;
+}
+
+#if !defined(BSP_USING_TRNG)
+static rt_uint32_t nu_prng_rand(struct hwcrypto_rng *ctx)
+{
+    return nu_prng_run();
+}
+
+#endif
+
+static const struct hwcrypto_symmetric_ops nu_aes_ops =
+{
+    .crypt = nu_aes_crypt,
+};
+
+static const struct hwcrypto_hash_ops nu_sha_ops =
+{
+    .update = nu_sha_update,
+    .finish = nu_sha_finish,
+};
+
+#endif
+
+/* CRC operation ------------------------------------------------------------*/
+#if defined(BSP_USING_CRC)
+
+static const struct hwcrypto_crc_ops nu_crc_ops =
+{
+    .update = nu_crc_update,
+};
+
+#endif
+
+/* TRNG operation ------------------------------------------------------------*/
+#if defined(BSP_USING_TRNG)
+
+static const struct hwcrypto_rng_ops nu_rng_ops =
+{
+    .update = nu_trng_rand,
+};
+
+#elif defined(BSP_USING_CRYPTO)
+
+static const struct hwcrypto_rng_ops nu_rng_ops =
+{
+    .update = nu_prng_rand,
+};
+
+#endif
+
+/* Register crypto interface ----------------------------------------------------------*/
+static rt_err_t nu_hwcrypto_create(struct rt_hwcrypto_ctx *ctx)
+{
+    rt_err_t res = RT_EOK;
+
+    switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
+    {
+#if defined(BSP_USING_TRNG)
+    case HWCRYPTO_TYPE_RNG:
+    {
+        ctx->contex = RT_NULL;
+        //Setup RNG operation
+        ((struct hwcrypto_rng *)ctx)->ops = &nu_rng_ops;
+        break;
+    }
+#endif /* BSP_USING_TRNG */
+
+#if defined(BSP_USING_CRC)
+    case HWCRYPTO_TYPE_CRC:
+    {
+        ctx->contex = RT_NULL;
+        //Setup CRC operation
+        ((struct hwcrypto_crc *)ctx)->ops = &nu_crc_ops;
+        break;
+    }
+#endif /* BSP_USING_CRC */
+
+#if defined(BSP_USING_CRYPTO)
+    case HWCRYPTO_TYPE_AES:
+    {
+        ctx->contex = RT_NULL;
+        //Setup AES operation
+        ((struct hwcrypto_symmetric *)ctx)->ops = &nu_aes_ops;
+        break;
+    }
+
+    case HWCRYPTO_TYPE_SHA1:
+    {
+        ctx->contex = rt_malloc(sizeof(S_SHA_CONTEXT));
+
+        if (ctx->contex == RT_NULL)
+            return -RT_ERROR;
+
+        rt_memset(ctx->contex, 0, sizeof(S_SHA_CONTEXT));
+        //Setup SHA1 operation
+        ((struct hwcrypto_hash *)ctx)->ops = &nu_sha_ops;
+        break;
+    }
+
+    case HWCRYPTO_TYPE_SHA2:
+    {
+        ctx->contex = rt_malloc(sizeof(S_SHA_CONTEXT));
+
+        if (ctx->contex == RT_NULL)
+            return -RT_ERROR;
+
+        rt_memset(ctx->contex, 0, sizeof(S_SHA_CONTEXT));
+        //Setup SHA2 operation
+        ((struct hwcrypto_hash *)ctx)->ops = &nu_sha_ops;
+        break;
+    }
+
+#if !defined(BSP_USING_TRNG)
+    case HWCRYPTO_TYPE_RNG:
+    {
+        ctx->contex = RT_NULL;
+        ((struct hwcrypto_rng *)ctx)->ops = &nu_rng_ops;
+#if defined(NU_PRNG_USE_SEED)
+        nu_prng_open(NU_PRNG_SEED_VALUE);
+#else
+        nu_prng_open(rt_tick_get());
+#endif
+        break;
+    }
+#endif /* !BSP_USING_TRNG */
+
+#endif /* BSP_USING_CRYPTO */
+
+    default:
+        res = -RT_ERROR;
+        break;
+    }
+
+    return res;
+}
+
+static void nu_hwcrypto_destroy(struct rt_hwcrypto_ctx *ctx)
+{
+    if (ctx->contex)
+        rt_free(ctx->contex);
+}
+
+static rt_err_t nu_hwcrypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcrypto_ctx *src)
+{
+    rt_err_t res = RT_EOK;
+
+    if (des->contex && src->contex)
+    {
+        rt_memcpy(des->contex, src->contex, sizeof(struct rt_hwcrypto_ctx));
+    }
+    else
+        return -RT_EINVAL;
+    return res;
+}
+
+static void nu_hwcrypto_reset(struct rt_hwcrypto_ctx *ctx)
+{
+    switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
+    {
+#if !defined(BSP_USING_TRNG)
+    case HWCRYPTO_TYPE_RNG:
+    {
+#if defined(NU_PRNG_USE_SEED)
+        nu_prng_open(NU_PRNG_SEED_VALUE);
+#else
+        nu_prng_open(rt_tick_get());
+#endif
+        break;
+    }
+#endif /* !BSP_USING_TRNG */
+#if defined(BSP_USING_CRYPTO)
+    case HWCRYPTO_TYPE_SHA1:
+    case HWCRYPTO_TYPE_SHA2:
+    {
+        S_SHA_CONTEXT *psSHACtx = (S_SHA_CONTEXT *)ctx->contex;
+
+        if (psSHACtx->pu8SHATempBuf)
+        {
+            rt_free(psSHACtx->pu8SHATempBuf);
+        }
+
+        psSHACtx->pu8SHATempBuf = RT_NULL;
+        psSHACtx->u32SHATempBufLen = 0;
+        psSHACtx->u32DMAMode = CRYPTO_DMA_FIRST;
+
+        if ((ctx->type == HWCRYPTO_TYPE_SHA384) || (ctx->type == HWCRYPTO_TYPE_SHA512))
+        {
+            psSHACtx->u32BlockSize = 128;
+        }
+        else
+        {
+            psSHACtx->u32BlockSize = 64;
+        }
+        break;
+    }
+
+#endif
+    default:
+        break;
+    }
+}
+
+/* Init and register nu_hwcrypto_dev */
+
+int nu_hwcrypto_device_init(void)
+{
+    static struct rt_hwcrypto_device nu_hwcrypto_dev;
+
+    nu_hwcrypto_dev.ops = &nu_hwcrypto_ops;
+    nu_hwcrypto_dev.id = 0;
+    nu_hwcrypto_dev.user_data = &nu_hwcrypto_dev;
+
+#if defined(BSP_USING_CRYPTO)
+    nu_crypto_init();
+#endif
+
+#if defined(BSP_USING_CRC)
+    nu_crc_init();
+#endif
+
+#if defined(BSP_USING_TRNG)
+    nu_trng_init();
+#endif
+
+    // register hwcrypto operation
+    if (rt_hwcrypto_register(&nu_hwcrypto_dev, RT_HWCRYPTO_DEFAULT_NAME) != RT_EOK)
+    {
+        return -1;
+    }
+
+    return 0;
+}
+INIT_DEVICE_EXPORT(nu_hwcrypto_device_init);
+
+#endif //#if ((defined(BSP_USING_CRYPTO) || defined(BSP_USING_TRNG) || defined(BSP_USING_CRC)) && defined(RT_USING_HWCRYPTO))
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_eadc.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_eadc.c
new file mode 100644
index 0000000000..3c72536156
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_eadc.c
@@ -0,0 +1,154 @@
+/**************************************************************************//**
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author       Notes
+* 2020-7-10       FYChou       First version
+*
+******************************************************************************/
+
+#include 
+#include 
+#include "NuMicro.h"
+
+#ifdef BSP_USING_EADC
+
+/* Private define ---------------------------------------------------------------*/
+
+/* Private Typedef --------------------------------------------------------------*/
+struct nu_eadc
+{
+    struct rt_adc_device dev;
+    char *name;
+    EADC_T *eadc_base;
+    int eadc_reg_tab;
+    int eadc_max_ch_num;
+
+};
+typedef struct nu_eadc *nu_eadc_t;
+
+/* Private functions ------------------------------------------------------------*/
+static rt_err_t nu_eadc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled);
+static rt_err_t nu_get_eadc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value);
+static rt_err_t nu_get_eadc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value);
+
+
+/* Public functions ------------------------------------------------------------*/
+int rt_hw_eadc_init(void);
+
+/* Private variables ------------------------------------------------------------*/
+
+static struct nu_eadc nu_eadc_arr [] =
+{
+#if defined(BSP_USING_EADC0)
+    {
+        .name = "eadc0",
+        .eadc_base = EADC,
+        .eadc_max_ch_num = 16,
+    },
+#endif
+
+    {0}
+};
+
+static const struct rt_adc_ops nu_adc_ops =
+{
+    nu_eadc_enabled,
+    nu_get_eadc_value,
+};
+typedef struct rt_adc_ops *rt_adc_ops_t;
+
+
+/* nu_adc_enabled - Enable ADC clock and wait for ready */
+static rt_err_t nu_eadc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
+{
+
+    EADC_T *eadc_base = ((nu_eadc_t)device)->eadc_base;
+    int *peadc_reg_tab = &((nu_eadc_t)device)->eadc_reg_tab;
+    RT_ASSERT(device != RT_NULL);
+
+    if (channel >= ((nu_eadc_t)device)->eadc_max_ch_num)
+        return -(RT_EINVAL);
+
+    if (enabled)
+    {
+        if (*peadc_reg_tab == 0)
+        {
+            EADC_Open(eadc_base, EADC_CTL_DIFFEN_SINGLE_END);
+        }
+
+        *peadc_reg_tab |= (0x1 << channel);
+    }
+    else
+    {
+        *peadc_reg_tab &= ~(0x1 << channel);
+
+        if (*peadc_reg_tab == 0)
+        {
+            EADC_Close(eadc_base);
+        }
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t nu_get_eadc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
+{
+
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(value != RT_NULL);
+
+    EADC_T *eadc_base = ((nu_eadc_t)device)->eadc_base;
+    int *peadc_reg_tab = &((nu_eadc_t)device)->eadc_reg_tab;
+
+    if (channel >= ((nu_eadc_t)device)->eadc_max_ch_num)
+    {
+        *value = 0xFFFFFFFF;
+        return -(RT_EINVAL);
+    }
+
+    if ((*peadc_reg_tab & (1 << channel)) == 0)
+    {
+        *value = 0xFFFFFFFF;
+        return -(RT_EBUSY);
+    }
+
+    EADC_ConfigSampleModule(eadc_base, 0, EADC_SOFTWARE_TRIGGER, channel);
+
+    EADC_CLR_INT_FLAG(eadc_base, EADC_STATUS2_ADIF0_Msk);
+
+    EADC_ENABLE_INT(eadc_base, BIT0);
+
+    EADC_ENABLE_SAMPLE_MODULE_INT(eadc_base, 0, BIT0);
+
+    EADC_START_CONV(eadc_base, BIT0);
+
+    while (EADC_GET_INT_FLAG(eadc_base, BIT0) == 0);
+
+    *value = EADC_GET_CONV_DATA(eadc_base, 0);
+
+    return RT_EOK;
+}
+
+int rt_hw_eadc_init(void)
+{
+    rt_err_t result = RT_ERROR;
+    int nu_sel = 0;
+
+    while (nu_eadc_arr[nu_sel].name != 0)
+    {
+        nu_eadc_arr[nu_sel].eadc_reg_tab = 0;
+
+        result = rt_hw_adc_register(&nu_eadc_arr[nu_sel].dev, nu_eadc_arr[nu_sel].name, &nu_adc_ops, NULL);
+        RT_ASSERT(result == RT_EOK);
+        nu_sel++;
+    }
+
+    return (int)result;
+}
+INIT_BOARD_EXPORT(rt_hw_eadc_init);
+
+
+#endif //#if defined(BSP_USING_EADC)
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_ebi.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_ebi.c
new file mode 100644
index 0000000000..4a01c6cf5c
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_ebi.c
@@ -0,0 +1,38 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-7-9        Philo            First version
+*
+******************************************************************************/
+#include 
+
+#ifdef  BSP_USING_EBI
+#define MAX_BANK    EBI_BANK2
+
+/* Private variables ------------------------------------------------------------*/
+static uint8_t nu_ebi_bank_mask = 0;
+
+/* Public functions -------------------------------------------------------------*/
+rt_err_t nu_ebi_init(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel)
+{
+    if (u32Bank > MAX_BANK)
+        return -(RT_ERROR);
+
+    /* Check this bank is not used */
+    if ((1 << u32Bank) & nu_ebi_bank_mask)
+        return -(RT_ERROR);
+
+    /* Initialize EBI */
+    EBI_Open(u32Bank, u32DataWidth, u32TimingClass, u32BusMode, u32CSActiveLevel);
+
+    nu_ebi_bank_mask |= (1 << u32Bank);
+
+    return RT_EOK;
+}
+
+#endif //BSP_USING_EBI
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_ebi.h b/bsp/nuvoton/libraries/m2354/rtt_port/drv_ebi.h
new file mode 100644
index 0000000000..c58fada77d
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_ebi.h
@@ -0,0 +1,48 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-7-9        Philo            First version
+*
+******************************************************************************/
+#ifndef __DRV_EBI_H___
+#define __DRV_EBI_H___
+
+#include 
+#include "NuMicro.h"
+
+/**
+  * @brief      Initialize EBI for specify Bank
+  *
+  * @param[in]  u32Bank             Bank number for EBI. Valid values are:
+  *                                     - \ref EBI_BANK0
+  *                                     - \ref EBI_BANK1
+  *                                     - \ref EBI_BANK2
+  * @param[in]  u32DataWidth        Data bus width. Valid values are:
+  *                                     - \ref EBI_BUSWIDTH_8BIT
+  *                                     - \ref EBI_BUSWIDTH_16BIT
+  * @param[in]  u32TimingClass      Default timing configuration. Valid values are:
+  *                                     - \ref EBI_TIMING_FASTEST
+  *                                     - \ref EBI_TIMING_VERYFAST
+  *                                     - \ref EBI_TIMING_FAST
+  *                                     - \ref EBI_TIMING_NORMAL
+  *                                     - \ref EBI_TIMING_SLOW
+  *                                     - \ref EBI_TIMING_VERYSLOW
+  *                                     - \ref EBI_TIMING_SLOWEST
+  * @param[in]  u32BusMode          Set EBI bus operate mode. Valid values are:
+  *                                     - \ref EBI_OPMODE_NORMAL
+  *                                     - \ref EBI_OPMODE_CACCESS
+  *                                     - \ref EBI_OPMODE_ADSEPARATE
+  * @param[in]  u32CSActiveLevel    CS is active High/Low. Valid values are:
+  *                                     - \ref EBI_CS_ACTIVE_HIGH
+  *                                     - \ref EBI_CS_ACTIVE_LOW
+  *
+  * @return     RT_EOK/RT_ERROR     Bank is used or not
+  */
+rt_err_t nu_ebi_init(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel);
+
+#endif // __DRV_EBI_H___
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_ecap.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_ecap.c
new file mode 100644
index 0000000000..c9e7c66a8d
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_ecap.c
@@ -0,0 +1,452 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-5-21       Philo            First version
+*
+******************************************************************************/
+#include 
+
+#if defined(BSP_USING_ECAP)
+#if ((BSP_USING_ECAP0_CHMSK+BSP_USING_ECAP1_CHMSK)!=0)
+#include 
+#include "NuMicro.h"
+
+#define ECAP_CH0_POS    (0)
+#define ECAP_CH1_POS    (1)
+#define ECAP_CH2_POS    (2)
+
+#define ECAP_CHANNEL_NUM    0x3
+#define ECAP_CLK_DIV    ECAP_CAPTURE_TIMER_CLKDIV_32
+
+/* Private typedef --------------------------------------------------------------*/
+typedef struct _ecap_dev
+{
+    ECAP_T      *ecap_base;
+    float       fUsPerTick;
+} nu_ecap_dev_t;
+
+typedef struct _ecap
+{
+    struct rt_inputcapture_device   parent;
+    nu_ecap_dev_t *ecap_dev;
+    uint8_t     u8Channel;
+    rt_bool_t   bfirstData;
+    uint32_t    u32CurrentCnt;
+    uint32_t    u32LastCnt;
+    rt_bool_t   input_data_level;
+} nu_capture_t;
+
+/* Private functions ------------------------------------------------------------*/
+static  rt_err_t nu_capture_init(struct rt_inputcapture_device *inputcapture);
+static  rt_err_t nu_capture_open(struct rt_inputcapture_device *inputcapture);
+static  rt_err_t nu_capture_close(struct rt_inputcapture_device *inputcapture);
+static  rt_err_t nu_capture_get_pulsewidth(struct rt_inputcapture_device *inputcapture, rt_uint32_t *pulsewidth_us);
+
+/* Private define ---------------------------------------------------------------*/
+#define NU_ECAP_GET_LEVEL(status, channel) ((status&(ECAP_STATUS_CAP0_Msk<CTL1 = ((ecap)->CTL1 & ECAP_CTL1_CLKSEL_Msk)>>ECAP_CTL1_CLKSEL_Pos)
+
+/* Public functions -------------------------------------------------------------*/
+
+
+/* Private variables ------------------------------------------------------------*/
+#if (BSP_USING_ECAP0_CHMSK!=0)
+static const char *nu_ecap0_device_name[ECAP_CHANNEL_NUM] = { "ecap0i0", "ecap0i1", "ecap0i2" };
+static nu_capture_t *nu_ecap0_capture[ECAP_CHANNEL_NUM] = {0};
+static nu_ecap_dev_t nu_ecap0_dev = {.ecap_base = ECAP0};
+#endif
+
+#if (BSP_USING_ECAP1_CHMSK!=0)
+static const char *nu_ecap1_device_name[ECAP_CHANNEL_NUM] = { "ecap1i0", "ecap1i1", "ecap1i2" };
+static nu_capture_t *nu_ecap1_capture[ECAP_CHANNEL_NUM] = {0};
+static nu_ecap_dev_t nu_ecap1_dev = {.ecap_base = ECAP1};
+#endif
+
+static struct rt_inputcapture_ops nu_capture_ops =
+{
+    .init   =   nu_capture_init,
+    .open   =   nu_capture_open,
+    .close  =   nu_capture_close,
+    .get_pulsewidth =   nu_capture_get_pulsewidth,
+};
+
+/* Functions define ------------------------------------------------------------*/
+#if (BSP_USING_ECAP0_CHMSK!=0)
+void ECAP0_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uint32_t u32Status;
+
+    /* Get input Capture status */
+    u32Status = ECAP_GET_INT_STATUS(ECAP0);
+
+#if (BSP_USING_ECAP0_CHMSK & (0x1<input_data_level = RT_FALSE;
+        }
+        else
+        {
+            nu_ecap0_capture[0]->input_data_level = RT_TRUE;
+        }
+
+        nu_ecap0_capture[0]->u32CurrentCnt   = ECAP_GET_CNT_HOLD_VALUE(ECAP0, ECAP_IC0);
+
+        rt_hw_inputcapture_isr(&nu_ecap0_capture[0]->parent, nu_ecap0_capture[0]->input_data_level);
+    }
+#endif
+
+
+#if (BSP_USING_ECAP0_CHMSK & (0x1<input_data_level = RT_FALSE;
+        }
+        else
+        {
+            nu_ecap0_capture[1]->input_data_level = RT_TRUE;
+        }
+
+        nu_ecap0_capture[1]->u32CurrentCnt   = ECAP_GET_CNT_HOLD_VALUE(ECAP0, ECAP_IC1);
+
+        rt_hw_inputcapture_isr(&nu_ecap0_capture[1]->parent, nu_ecap0_capture[1]->input_data_level);
+    }
+#endif
+
+#if (BSP_USING_ECAP0_CHMSK & (0x1<input_data_level = RT_FALSE;
+        }
+        else
+        {
+            nu_ecap0_capture[2]->input_data_level = RT_TRUE;
+        }
+
+        nu_ecap0_capture[2]->u32CurrentCnt   = ECAP_GET_CNT_HOLD_VALUE(ECAP0, ECAP_IC2);
+
+        rt_hw_inputcapture_isr(&nu_ecap0_capture[2]->parent, nu_ecap0_capture[2]->input_data_level);
+    }
+#endif
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif  //(BSP_USING_ECAP0_CHMSK!=0)
+
+
+#if (BSP_USING_ECAP1_CHMSK!=0)
+void ECAP1_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uint32_t u32Status;
+
+    /* Get input Capture status */
+    u32Status = ECAP_GET_INT_STATUS(ECAP1);
+
+#if (BSP_USING_ECAP1_CHMSK & (0x1<input_data_level = RT_FALSE;
+        }
+        else
+        {
+            nu_ecap1_capture[0]->input_data_level = RT_TRUE;
+        }
+
+        nu_ecap1_capture[0]->u32CurrentCnt = ECAP_GET_CNT_HOLD_VALUE(ECAP1, ECAP_IC0);
+
+        rt_hw_inputcapture_isr(&nu_ecap1_capture[0]->parent, nu_ecap1_capture[0]->input_data_level);
+    }
+#endif
+
+
+#if (BSP_USING_ECAP1_CHMSK & (0x1<input_data_level = RT_FALSE;
+        }
+        else
+        {
+            nu_ecap1_capture[1]->input_data_level = RT_TRUE;
+        }
+
+        nu_ecap1_capture[1]->u32CurrentCnt = ECAP_GET_CNT_HOLD_VALUE(ECAP1, ECAP_IC1);
+
+        rt_hw_inputcapture_isr(&nu_ecap1_capture[1]->parent, nu_ecap1_capture[1]->input_data_level);
+    }
+#endif
+
+#if (BSP_USING_ECAP1_CHMSK & (0x1<input_data_level = RT_FALSE;
+        }
+        else
+        {
+            nu_ecap1_capture[2]->input_data_level = RT_TRUE;
+        }
+
+        nu_ecap1_capture[2]->u32CurrentCnt = ECAP_GET_CNT_HOLD_VALUE(ECAP1, ECAP_IC2);
+
+        rt_hw_inputcapture_isr(&nu_ecap1_capture[2]->parent, nu_ecap1_capture[2]->input_data_level);
+    }
+#endif
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif  //(BSP_USING_ECAP1_CHMSK!=0)
+
+static rt_err_t nu_capture_get_pulsewidth(struct rt_inputcapture_device *inputcapture, rt_uint32_t *pulsewidth_us)
+{
+    rt_err_t ret = RT_EOK;
+    nu_capture_t *nu_capture;
+    float fTempCnt;
+
+    nu_capture = (nu_capture_t *)inputcapture;
+
+    if (nu_capture->bfirstData)
+    {
+        nu_capture->bfirstData = RT_FALSE;
+        ret = RT_ERROR;
+
+        return -(ret);
+    }
+
+    if (nu_capture->u32CurrentCnt > nu_capture->u32LastCnt)
+        fTempCnt = nu_capture->u32CurrentCnt - nu_capture->u32LastCnt;
+    else    /* Overrun case */
+        fTempCnt = nu_capture->u32CurrentCnt + ((0x1000000 - nu_capture->u32LastCnt) + 1);
+
+    *pulsewidth_us = (int)(fTempCnt * nu_capture->ecap_dev->fUsPerTick);
+
+    nu_capture->u32LastCnt = nu_capture->u32CurrentCnt;
+
+    return -(ret);
+}
+
+static float get_ecap_tick_time_us(nu_capture_t *nu_capture)
+{
+    uint8_t u8ClockDivider[8] = { 1, 4, 16, 32, 64, 96, 112, 128};
+    if (nu_capture->ecap_dev->ecap_base == ECAP0)
+        return ((float)1000000 / ((float)CLK_GetPCLK0Freq() / u8ClockDivider[(nu_capture->ecap_dev->ecap_base->CTL1 & ECAP_CTL1_CLKSEL_Msk) >> ECAP_CTL1_CLKSEL_Pos]));
+    else
+        return ((float)1000000 / ((float)CLK_GetPCLK1Freq() / u8ClockDivider[(nu_capture->ecap_dev->ecap_base->CTL1 & ECAP_CTL1_CLKSEL_Msk) >> ECAP_CTL1_CLKSEL_Pos]));
+}
+
+static rt_err_t nu_ecap_init(nu_capture_t *nu_capture)
+{
+    rt_err_t ret = RT_ERROR;
+    static rt_bool_t bECAP0Inited = RT_FALSE;
+    static rt_bool_t bECAP1Inited = RT_FALSE;
+
+    if (nu_capture->ecap_dev->ecap_base == ECAP0)
+    {
+        if (bECAP0Inited == RT_FALSE)
+        {
+            /* Enable ECAP0 clock */
+            SYS_UnlockReg();
+            CLK_EnableModuleClock(ECAP0_MODULE);
+            SYS_LockReg();
+
+            NVIC_EnableIRQ(ECAP0_IRQn);
+            bECAP0Inited = RT_TRUE;
+        }
+        else
+        {
+            return ret = RT_EOK;
+        }
+    }
+    else if (nu_capture->ecap_dev->ecap_base == ECAP1)
+    {
+        if (bECAP1Inited == RT_FALSE)
+        {
+            /* Enable ECAP1 clock */
+            SYS_UnlockReg();
+            CLK_EnableModuleClock(ECAP1_MODULE);
+            SYS_LockReg();
+
+            NVIC_EnableIRQ(ECAP1_IRQn);
+            bECAP1Inited = RT_TRUE;
+        }
+        else
+        {
+            return ret = RT_EOK;
+        }
+    }
+    else
+    {
+        return ret;
+    }
+
+    /* Enable ECAP */
+    ECAP_Open(nu_capture->ecap_dev->ecap_base, ECAP_DISABLE_COMPARE);
+
+    ECAP_SEL_TIMER_CLK_DIV(nu_capture->ecap_dev->ecap_base, ECAP_CLK_DIV);
+
+    /* Select Reload function */
+    ECAP_SET_CNT_CLEAR_EVENT(nu_capture->ecap_dev->ecap_base, ECAP_CTL1_OVRLDEN_Msk);
+
+    /* Enable ECAP0 source IC */
+    ECAP_SEL_INPUT_SRC(nu_capture->ecap_dev->ecap_base, ECAP_IC0, ECAP_CAP_INPUT_SRC_FROM_IC);
+    ECAP_SEL_INPUT_SRC(nu_capture->ecap_dev->ecap_base, ECAP_IC1, ECAP_CAP_INPUT_SRC_FROM_IC);
+    ECAP_SEL_INPUT_SRC(nu_capture->ecap_dev->ecap_base, ECAP_IC2, ECAP_CAP_INPUT_SRC_FROM_IC);
+
+    /* Select IC detect rising edge */
+    ECAP_SEL_CAPTURE_EDGE(nu_capture->ecap_dev->ecap_base, ECAP_IC0, ECAP_RISING_FALLING_EDGE);
+    ECAP_SEL_CAPTURE_EDGE(nu_capture->ecap_dev->ecap_base, ECAP_IC1, ECAP_RISING_FALLING_EDGE);
+    ECAP_SEL_CAPTURE_EDGE(nu_capture->ecap_dev->ecap_base, ECAP_IC2, ECAP_RISING_FALLING_EDGE);
+
+    ret = RT_EOK;
+
+    return -(ret);
+}
+
+static rt_err_t nu_capture_init(struct rt_inputcapture_device *inputcapture)
+{
+    rt_err_t ret = RT_EOK;
+    nu_capture_t *nu_capture;
+
+    RT_ASSERT(inputcapture != RT_NULL);
+
+    nu_capture = (nu_capture_t *) inputcapture;
+
+    if (nu_ecap_init(nu_capture) != RT_EOK)
+    {
+        rt_kprintf("Failed to initialize ECAP.\n");
+        ret = RT_ERROR;
+    }
+
+    return -(ret);
+}
+
+static rt_err_t nu_capture_open(struct rt_inputcapture_device *inputcapture)
+{
+    rt_err_t ret = RT_EOK;
+    nu_capture_t *nu_capture;
+
+    RT_ASSERT(inputcapture != RT_NULL);
+
+    nu_capture = (nu_capture_t *) inputcapture;
+
+    nu_capture->ecap_dev->fUsPerTick = get_ecap_tick_time_us(nu_capture);
+
+    /* Enable ECAP Input Channel */
+    ECAP_ENABLE_INPUT_CHANNEL(nu_capture->ecap_dev->ecap_base, 0x1 << (ECAP_CTL0_IC0EN_Pos + nu_capture->u8Channel));
+
+    /* Input Channel interrupt enabled */
+    ECAP_EnableINT(nu_capture->ecap_dev->ecap_base, 0x1 << (ECAP_CTL0_CAPIEN0_Pos + nu_capture->u8Channel));
+
+    /* ECAP_CNT starts up-counting */
+    ECAP_CNT_START(nu_capture->ecap_dev->ecap_base);
+
+    return ret;
+}
+
+static rt_err_t nu_capture_close(struct rt_inputcapture_device *inputcapture)
+{
+    rt_err_t ret = RT_EOK;
+
+    nu_capture_t *nu_capture;
+
+    RT_ASSERT(inputcapture != RT_NULL);
+
+    nu_capture = (nu_capture_t *) inputcapture;
+
+    /* Input Channel interrupt disabled */
+    ECAP_DisableINT(nu_capture->ecap_dev->ecap_base, 0x1 << (ECAP_CTL0_CAPIEN0_Pos + nu_capture->u8Channel));
+
+    /* Disable ECAP Input Channel */
+    ECAP_DISABLE_INPUT_CHANNEL(nu_capture->ecap_dev->ecap_base, 0x1 << (ECAP_CTL0_IC0EN_Pos + nu_capture->u8Channel));
+
+    /* Clear input capture channel flag */
+    ECAP_CLR_CAPTURE_FLAG(nu_capture->ecap_dev->ecap_base, 0x1 << (ECAP_STATUS_CAPTF0_Pos + nu_capture->u8Channel));
+
+    return ret;
+}
+
+static void ecap_init(nu_capture_t *nu_capture, uint8_t u8Channel, nu_ecap_dev_t *ecap_dev, const char *device_name)
+{
+    nu_capture->ecap_dev = ecap_dev;
+    nu_capture->u8Channel = u8Channel;
+    nu_capture->bfirstData = RT_TRUE;
+    nu_capture->u32CurrentCnt = 0;
+    nu_capture->u32LastCnt = 0;
+    nu_capture->parent.ops = &nu_capture_ops;
+
+    /* register inputcapture device */
+    rt_device_inputcapture_register(&nu_capture->parent, device_name, &nu_capture);
+}
+
+/* Init and register ecap capture */
+static int nu_ecap_capture_device_init(void)
+{
+    for (int i = 0; i < ECAP_CHANNEL_NUM; i++)
+    {
+#if (BSP_USING_ECAP0_CHMSK!=0)
+        if (BSP_USING_ECAP0_CHMSK & (0x1 << i))
+        {
+            nu_ecap0_capture[i] = (nu_capture_t *)rt_malloc(sizeof(nu_capture_t));
+            ecap_init(nu_ecap0_capture[i], i, &nu_ecap0_dev, nu_ecap0_device_name[i]);
+        }
+#endif //#if (BSP_USING_ECAP0_CHMSK!=0)
+
+#if (BSP_USING_ECAP1_CHMSK!=0)
+        if (BSP_USING_ECAP1_CHMSK & (0x1 << i))
+        {
+            nu_ecap1_capture[i] = (nu_capture_t *)rt_malloc(sizeof(nu_capture_t));
+            ecap_init(nu_ecap1_capture[i], i, &nu_ecap1_dev, nu_ecap1_device_name[i]);
+        }
+#endif //#if (BSP_USING_ECAP1_CHMSK!=0)
+    }
+
+    return 0;
+}
+INIT_DEVICE_EXPORT(nu_ecap_capture_device_init);
+#endif //#if ((BSP_USING_ECAP0_CHMSK+BSP_USING_ECAP1_CHMSK)!=0)
+#endif //#if defined(BSP_USING_ECAP)
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_epwm.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_epwm.c
new file mode 100644
index 0000000000..027d8f19be
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_epwm.c
@@ -0,0 +1,231 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author       Notes
+* 2020-8-15       YHKuo        First version
+*
+******************************************************************************/
+
+#include 
+
+#if defined(BSP_USING_EPWM)
+
+#define LOG_TAG                 "drv.epwm"
+#define DBG_ENABLE
+#define DBG_SECTION_NAME        LOG_TAG
+#define DBG_LEVEL               DBG_INFO
+#define DBG_COLOR
+#include 
+
+#include 
+#include 
+#include 
+#include "NuMicro.h"
+
+enum
+{
+    EPWM_START = -1,
+#if defined(BSP_USING_EPWM0)
+    EPWM0_IDX,
+#endif
+#if defined(BSP_USING_EPWM1)
+    EPWM1_IDX,
+#endif
+    EPWM_CNT
+};
+
+struct nu_epwm
+{
+    struct rt_device_pwm dev;
+    char *name;
+    EPWM_T *epwm_base;
+};
+
+typedef struct nu_epwm *nu_epwm_t;
+
+static struct nu_epwm nu_epwm_arr [] =
+{
+#if defined(BSP_USING_EPWM0)
+    {
+        .name = "epwm0",
+        .epwm_base = EPWM0,
+    },
+#endif
+
+#if defined(BSP_USING_EPWM1)
+    {
+        .name = "epwm1",
+        .epwm_base = EPWM1,
+    },
+#endif
+    {0}
+}; /* epwm nu_epwm */
+
+static rt_err_t nu_epwm_control(struct rt_device_pwm *device, int cmd, void *arg);
+
+static struct rt_pwm_ops nu_epwm_ops =
+{
+    .control = nu_epwm_control
+};
+
+static rt_err_t nu_epwm_enable(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration, rt_bool_t enable)
+{
+    rt_err_t result = RT_EOK;
+
+    EPWM_T *pwm_base = ((nu_epwm_t)device)->epwm_base;
+    rt_uint32_t pwm_channel = ((struct rt_pwm_configuration *)configuration)->channel;
+
+    if (enable == RT_TRUE)
+    {
+        EPWM_EnableOutput(pwm_base, 1 << pwm_channel);
+        EPWM_Start(pwm_base, 1 << pwm_channel);
+    }
+    else
+    {
+        EPWM_DisableOutput(pwm_base, 1 << pwm_channel);
+        EPWM_ForceStop(pwm_base, 1 << pwm_channel);
+    }
+
+    return result;
+}
+
+static rt_err_t nu_epwm_set(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration)
+{
+    if ((((struct rt_pwm_configuration *)configuration)->period) <= 0)
+        return -(RT_ERROR);
+    rt_uint8_t  pwm_channel_pair;
+    rt_uint32_t pwm_freq, pwm_dutycycle ;
+    EPWM_T *pwm_base = ((nu_epwm_t)device)->epwm_base;
+    rt_uint8_t pwm_channel = ((struct rt_pwm_configuration *)configuration)->channel;
+    rt_uint32_t pwm_period = ((struct rt_pwm_configuration *)configuration)->period;
+    rt_uint32_t pwm_pulse = ((struct rt_pwm_configuration *)configuration)->pulse;
+    rt_uint32_t pre_pwm_prescaler = EPWM_GET_PRESCALER(pwm_base, pwm_channel);
+
+    if ((pwm_channel % 2) == 0)
+        pwm_channel_pair = pwm_channel + 1;
+    else
+        pwm_channel_pair = pwm_channel - 1;
+
+    pwm_freq = 1000000000 / pwm_period;
+    pwm_dutycycle = (pwm_pulse * 100) / pwm_period;
+
+    EPWM_ConfigOutputChannel(pwm_base, pwm_channel, pwm_freq, pwm_dutycycle) ;
+
+    if ((pre_pwm_prescaler != 0) || (EPWM_GET_CNR(pwm_base, pwm_channel_pair) != 0) || (EPWM_GET_CMR(pwm_base, pwm_channel_pair) != 0))
+    {
+        if (pre_pwm_prescaler < EPWM_GET_PRESCALER(pwm_base, pwm_channel))
+        {
+            EPWM_SET_CNR(pwm_base, pwm_channel_pair, ((EPWM_GET_CNR(pwm_base, pwm_channel_pair) + 1) * (pre_pwm_prescaler + 1)) / (EPWM_GET_PRESCALER(pwm_base, pwm_channel) + 1));
+            EPWM_SET_CMR(pwm_base, pwm_channel_pair, (EPWM_GET_CMR(pwm_base, pwm_channel_pair) * (pre_pwm_prescaler + 1)) / (EPWM_GET_PRESCALER(pwm_base, pwm_channel) + 1));
+        }
+        else if (pre_pwm_prescaler > EPWM_GET_PRESCALER(pwm_base, pwm_channel))
+        {
+            EPWM_SET_CNR(pwm_base, pwm_channel, ((EPWM_GET_CNR(pwm_base, pwm_channel) + 1) * (EPWM_GET_PRESCALER(pwm_base, pwm_channel) + 1)) / (pre_pwm_prescaler + 1));
+            EPWM_SET_CMR(pwm_base, pwm_channel, (EPWM_GET_CMR(pwm_base, pwm_channel) * (EPWM_GET_PRESCALER(pwm_base, pwm_channel) + 1)) / (pre_pwm_prescaler + 1));
+        }
+    }
+    return RT_EOK;
+}
+
+static rt_uint32_t nu_epwm_clksr(struct rt_device_pwm *device)
+{
+    rt_uint32_t u32Src, u32EPWMClockSrc;
+    EPWM_T *pwm_base = ((nu_epwm_t)device)->epwm_base;
+    if (pwm_base == EPWM0)
+    {
+        u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk;
+    }
+    else     /* (epwm == EPWM1) */
+    {
+        u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk;
+    }
+
+    if (u32Src == 0U)
+    {
+        /* clock source is from PLL clock */
+        u32EPWMClockSrc = CLK_GetPLLClockFreq();
+    }
+    else
+    {
+        /* clock source is from PCLK */
+        SystemCoreClockUpdate();
+        if (pwm_base == EPWM0)
+        {
+            u32EPWMClockSrc = CLK_GetPCLK0Freq();
+        }
+        else     /* (epwm == EPWM1) */
+        {
+            u32EPWMClockSrc = CLK_GetPCLK1Freq();
+        }
+    }
+    return u32EPWMClockSrc;
+}
+
+static rt_err_t nu_epwm_get(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration)
+{
+    rt_uint32_t pwm_real_period, pwm_real_duty, time_tick, u32EPWMClockSrc ;
+
+    EPWM_T *pwm_base = ((nu_epwm_t)device)->epwm_base;
+    rt_uint32_t pwm_channel = ((struct rt_pwm_configuration *)configuration)->channel;
+    rt_uint32_t pwm_prescale = EPWM_GET_PRESCALER(pwm_base, pwm_channel);
+    rt_uint32_t pwm_period = EPWM_GET_CNR(pwm_base, pwm_channel);
+    rt_uint32_t pwm_pulse = EPWM_GET_CMR(pwm_base, pwm_channel);
+
+    u32EPWMClockSrc = nu_epwm_clksr(device);
+    time_tick = 1000000000000 / u32EPWMClockSrc;
+
+    pwm_real_period = (((pwm_prescale + 1) * (pwm_period + 1)) * time_tick) / 1000;
+    pwm_real_duty = (((pwm_prescale + 1) * pwm_pulse * time_tick)) / 1000;
+    ((struct rt_pwm_configuration *)configuration)->period = pwm_real_period;
+    ((struct rt_pwm_configuration *)configuration)->pulse = pwm_real_duty;
+
+    LOG_I("%s %d %d %d\n", ((nu_epwm_t)device)->name, configuration->channel, configuration->period, configuration->pulse);
+
+    return RT_EOK;
+}
+
+static rt_err_t nu_epwm_control(struct rt_device_pwm *device, int cmd, void *arg)
+{
+    struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
+
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(configuration != RT_NULL);
+
+    if (((((struct rt_pwm_configuration *)configuration)->channel) + 1) > EPWM_CHANNEL_NUM)
+        return -(RT_ERROR);
+
+    switch (cmd)
+    {
+    case PWM_CMD_ENABLE:
+        return nu_epwm_enable(device, configuration, RT_TRUE);
+    case PWM_CMD_DISABLE:
+        return nu_epwm_enable(device, configuration, RT_FALSE);
+    case PWM_CMD_SET:
+        return nu_epwm_set(device, configuration);
+    case PWM_CMD_GET:
+        return nu_epwm_get(device, configuration);
+    }
+    return -(RT_EINVAL);
+}
+
+int rt_hw_epwm_init(void)
+{
+    rt_err_t ret;
+    int i;
+
+    for (i = (EPWM_START + 1); i < EPWM_CNT; i++)
+    {
+        ret = rt_device_pwm_register(&nu_epwm_arr[i].dev, nu_epwm_arr[i].name, &nu_epwm_ops, RT_NULL);
+        RT_ASSERT(ret == RT_EOK);
+    }
+
+    return 0;
+}
+
+INIT_DEVICE_EXPORT(rt_hw_epwm_init);
+
+#endif
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_epwm_capture.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_epwm_capture.c
new file mode 100644
index 0000000000..c98452d44b
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_epwm_capture.c
@@ -0,0 +1,510 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-8-20        Philo            First version
+*
+******************************************************************************/
+#include 
+
+#if defined(BSP_USING_EPWM_CAPTURE)
+#if ((BSP_USING_EPWM0_CAPTURE_CHMSK+BSP_USING_EPWM1_CAPTURE_CHMSK)!=0)
+#include 
+#include "NuMicro.h"
+
+#define EPWM_CH0CH1_POS    (0)
+#define EPWM_CH2CH3_POS    (2)
+#define EPWM_CH4CH5_POS    (4)
+
+/* Private typedef --------------------------------------------------------------*/
+typedef struct nu_capture
+{
+    struct rt_inputcapture_device   parent;
+    EPWM_T      *epwm;
+    uint8_t     u8Channel;
+    IRQn_Type   irq;
+    uint32_t    u32CurrentRisingCnt;
+    uint32_t    u32CurrentFallingCnt;
+    rt_bool_t   input_data_level;
+} nu_capture_t;
+
+/* Private functions ------------------------------------------------------------*/
+static  rt_err_t nu_capture_init(struct rt_inputcapture_device *inputcapture);
+static  rt_err_t nu_capture_open(struct rt_inputcapture_device *inputcapture);
+static  rt_err_t nu_capture_close(struct rt_inputcapture_device *inputcapture);
+static  rt_err_t nu_capture_get_pulsewidth(struct rt_inputcapture_device *inputcapture, rt_uint32_t *pulsewidth_us);
+
+/* Public functions -------------------------------------------------------------*/
+
+
+/* Private variables ------------------------------------------------------------*/
+#if (BSP_USING_EPWM0_CAPTURE_CHMSK!=0)
+static const char *nu_epwm0_device_name[EPWM_CHANNEL_NUM] = { "epwm0i0", "epwm0i1", "epwm0i2", "epwm0i3", "epwm0i4", "epwm0i5"};
+static const IRQn_Type nu_epwm0_irq[EPWM_CHANNEL_NUM / 2] = { EPWM0_P0_IRQn, EPWM0_P1_IRQn, EPWM0_P2_IRQn};
+static nu_capture_t nu_epwm0_capture[EPWM_CHANNEL_NUM] = {0};
+#endif
+
+#if (BSP_USING_EPWM1_CAPTURE_CHMSK!=0)
+static const char *nu_epwm1_device_name[EPWM_CHANNEL_NUM] = {"epwm1i0", "epwm1i1", "epwm1i2", "epwm1i3", "epwm1i4", "epwm1i5", };
+static const IRQn_Type nu_epwm1_irq[EPWM_CHANNEL_NUM / 2] = {EPWM1_P0_IRQn, EPWM1_P1_IRQn, EPWM1_P2_IRQn };
+static nu_capture_t nu_epwm1_capture[EPWM_CHANNEL_NUM] = {0};
+#endif
+
+static struct rt_inputcapture_ops nu_capture_ops =
+{
+    .init   =   nu_capture_init,
+    .open   =   nu_capture_open,
+    .close  =   nu_capture_close,
+    .get_pulsewidth =   nu_capture_get_pulsewidth,
+};
+
+/* Functions define ------------------------------------------------------------*/
+static rt_err_t CalPulseWidth(nu_capture_t *nu_capture)
+{
+    rt_bool_t bWrapAroundFlag = RT_FALSE;
+
+    /* Check rising/falling capture counter is overflow or not */
+    if (EPWM_GetWrapAroundFlag(nu_capture->epwm, nu_capture->u8Channel))
+    {
+        EPWM_ClearWrapAroundFlag(nu_capture->epwm, nu_capture->u8Channel);
+        bWrapAroundFlag = RT_TRUE;
+    }
+
+    /* Read the capture counter value if falling/rising edge */
+    if (EPWM_GetCaptureIntFlag(nu_capture->epwm, nu_capture->u8Channel) == 1)//Rising edge
+    {
+        EPWM_ClearCaptureIntFlag(nu_capture->epwm, nu_capture->u8Channel, EPWM_CAPTURE_INT_RISING_LATCH);
+
+        if (bWrapAroundFlag)
+        {
+            nu_capture->u32CurrentRisingCnt = 0x10000;
+        }
+        nu_capture->u32CurrentRisingCnt += EPWM_GET_CAPTURE_RISING_DATA(nu_capture->epwm, nu_capture->u8Channel);
+    }
+    else if (EPWM_GetCaptureIntFlag(nu_capture->epwm, nu_capture->u8Channel) == 2)//Falling edge
+    {
+        EPWM_ClearCaptureIntFlag(nu_capture->epwm, nu_capture->u8Channel, EPWM_CAPTURE_INT_FALLING_LATCH);
+
+        if (bWrapAroundFlag)
+        {
+            nu_capture->u32CurrentFallingCnt = 0x10000;
+        }
+        nu_capture->u32CurrentFallingCnt += EPWM_GET_CAPTURE_FALLING_DATA(nu_capture->epwm, nu_capture->u8Channel);
+    }
+    else
+    {
+        EPWM_ClearCaptureIntFlag(nu_capture->epwm, nu_capture->u8Channel, EPWM_CAPTURE_INT_RISING_LATCH);
+        EPWM_ClearCaptureIntFlag(nu_capture->epwm, nu_capture->u8Channel, EPWM_CAPTURE_INT_FALLING_LATCH);
+
+        return -(RT_ERROR);
+    }
+
+    return RT_EOK;
+}
+
+#if (BSP_USING_EPWM0_CAPTURE_CHMSK&(0x3<u32CurrentFallingCnt)
+    {
+        *pulsewidth_us = nu_capture->u32CurrentFallingCnt;
+        nu_capture->input_data_level = RT_FALSE;
+        nu_capture->u32CurrentFallingCnt = 0;
+    }
+    else if (nu_capture->u32CurrentRisingCnt)
+    {
+        *pulsewidth_us = nu_capture->u32CurrentRisingCnt;
+        nu_capture->input_data_level = RT_TRUE;
+        nu_capture->u32CurrentRisingCnt = 0;
+    }
+    else
+    {
+        ret = RT_ERROR;
+    }
+    return -(ret);
+}
+
+static rt_err_t nu_epwm_init(nu_capture_t *nu_capture)
+{
+    rt_err_t ret = RT_ERROR;
+    static rt_bool_t bEPWM0Inited = RT_FALSE;
+    static rt_bool_t bEPWM1Inited = RT_FALSE;
+
+    if (nu_capture->epwm == EPWM0)
+    {
+        if (bEPWM0Inited == RT_FALSE)
+        {
+            /* Enable EPWM0 clock */
+            SYS_UnlockReg();
+            CLK_EnableModuleClock(EPWM0_MODULE);
+            CLK_SetModuleClock(EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PCLK0, 0);
+            SYS_LockReg();
+            bEPWM0Inited = RT_TRUE;
+        }
+        ret = RT_EOK;
+    }
+    else if (nu_capture->epwm == EPWM1)
+    {
+        if (bEPWM1Inited == RT_FALSE)
+        {
+            /* Enable EPWM1 clock */
+            SYS_UnlockReg();
+            CLK_EnableModuleClock(EPWM1_MODULE);
+            CLK_SetModuleClock(EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PCLK1, 0);
+            SYS_LockReg();
+            bEPWM1Inited = RT_TRUE;
+        }
+        ret = RT_EOK;
+    }
+
+    return -(ret);
+}
+
+static rt_err_t nu_capture_init(struct rt_inputcapture_device *inputcapture)
+{
+    rt_err_t ret = RT_EOK;
+    nu_capture_t *nu_capture;
+
+    RT_ASSERT(inputcapture != RT_NULL);
+
+    nu_capture = (nu_capture_t *) inputcapture;
+
+    if (nu_epwm_init(nu_capture) != RT_EOK)
+    {
+        rt_kprintf("Failed to initialize EPWM%d.\n", nu_capture->epwm);
+        ret = RT_ERROR;
+    }
+
+    return -(ret);
+}
+
+static rt_err_t nu_capture_open(struct rt_inputcapture_device *inputcapture)
+{
+    rt_err_t ret = RT_EOK;
+    nu_capture_t *nu_capture;
+
+    RT_ASSERT(inputcapture != RT_NULL);
+
+    nu_capture = (nu_capture_t *) inputcapture;
+
+    /* Set capture time as 1000 nanosecond */
+    EPWM_ConfigCaptureChannel(nu_capture->epwm, nu_capture->u8Channel, 1000, 0);
+
+    /* Enable capture rising/falling edge interrupt */
+    EPWM_EnableCaptureInt(nu_capture->epwm, nu_capture->u8Channel, EPWM_CAPTURE_INT_FALLING_LATCH | EPWM_CAPTURE_INT_RISING_LATCH);
+
+    /* Enable EPWM NVIC interrupt */
+    NVIC_EnableIRQ(nu_capture->irq);
+
+    /* Enable Capture Function for EPWM */
+    EPWM_EnableCapture(nu_capture->epwm, 0x1 << nu_capture->u8Channel);
+
+    /* Enable rising/falling capture reload */
+    nu_capture->epwm->CAPCTL |= (0x1 << (EPWM_CAPCTL_RCRLDEN0_Pos + nu_capture->u8Channel))
+                                | (0x1 << (EPWM_CAPCTL_FCRLDEN0_Pos + nu_capture->u8Channel));
+
+    /* Set counter type as down count */
+    EPWM_SET_ALIGNED_TYPE(nu_capture->epwm, 0x1 << nu_capture->u8Channel, EPWM_UP_COUNTER);
+
+    /* Enable EPWM Timer */
+    EPWM_Start(nu_capture->epwm, 0x1 << nu_capture->u8Channel);
+
+    return ret;
+}
+
+static rt_err_t nu_capture_close(struct rt_inputcapture_device *inputcapture)
+{
+    rt_err_t ret = RT_EOK;
+
+    nu_capture_t *nu_capture;
+
+    RT_ASSERT(inputcapture != RT_NULL);
+
+    nu_capture = (nu_capture_t *) inputcapture;
+
+    /* Disable capture rising/falling edge interrupt */
+    EPWM_DisableCaptureInt(nu_capture->epwm, nu_capture->u8Channel, EPWM_CAPTURE_INT_FALLING_LATCH | EPWM_CAPTURE_INT_RISING_LATCH);
+
+    /* Disable EPWM NVIC interrupt */
+    NVIC_DisableIRQ(nu_capture->irq);
+
+    /* Enable EPWM Timer */
+    EPWM_Stop(nu_capture->epwm, 0x1 << nu_capture->u8Channel);
+    return ret;
+}
+
+/* Init and register epwm capture */
+int nu_epwm_capture_device_init(void)
+{
+    /* Init EPWM0 6 channel and EPWM1 6 channel */
+#if (BSP_USING_EPWM0_CAPTURE_CHMSK!=0)
+    for (int i = 0; i < EPWM_CHANNEL_NUM; i++)
+    {
+        if (BSP_USING_EPWM0_CAPTURE_CHMSK & (0x1 << i))
+        {
+            nu_epwm0_capture[i].epwm = EPWM0;
+            nu_epwm0_capture[i].u8Channel = i;
+            nu_epwm0_capture[i].irq = nu_epwm0_irq[i / 2];
+            nu_epwm0_capture[i].u32CurrentRisingCnt = 0;
+            nu_epwm0_capture[i].u32CurrentFallingCnt = 0;
+            nu_epwm0_capture[i].parent.ops = &nu_capture_ops;
+
+            /* register inputcapture device */
+            rt_device_inputcapture_register(&nu_epwm0_capture[i].parent, nu_epwm0_device_name[i], &nu_epwm0_capture[i]);
+
+        }
+    }
+#endif //#if (BSP_USING_EPWM0_CAPTURE_CHMSK!=0)
+#if (BSP_USING_EPWM1_CAPTURE_CHMSK!=0)
+    for (int i = 0; i < EPWM_CHANNEL_NUM; i++)
+    {
+        if (BSP_USING_EPWM1_CAPTURE_CHMSK & (0x1 << i))
+        {
+            nu_epwm1_capture[i].epwm = EPWM1;
+            nu_epwm1_capture[i].u8Channel = i;
+            nu_epwm1_capture[i].irq = nu_epwm1_irq[i / 2];
+            nu_epwm1_capture[i].u32CurrentRisingCnt = 0;
+            nu_epwm1_capture[i].u32CurrentFallingCnt = 0;
+            nu_epwm1_capture[i].parent.ops = &nu_capture_ops;
+
+            /* register inputcapture device */
+            rt_device_inputcapture_register(&nu_epwm1_capture[i].parent, nu_epwm1_device_name[i], &nu_epwm1_capture[i]);
+        }
+    }
+#endif //#if (BSP_USING_EPWM1_CAPTURE_CHMSK!=0)
+    return 0;
+
+}
+INIT_DEVICE_EXPORT(nu_epwm_capture_device_init);
+#endif  //#if ((BSP_USING_EPWM0_CAPTURE_CHMSK+BSP_USING_EPWM1_CAPTURE_CHMSK)!=0)
+#endif //#if defined(BSP_USING_EPWM_CAPTURE)
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_fmc.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_fmc.c
new file mode 100644
index 0000000000..a5a97bea1b
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_fmc.c
@@ -0,0 +1,328 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author       Notes
+* 2020-3-03       FYChou       First version
+*
+******************************************************************************/
+
+#include 
+
+#if defined(BSP_USING_FMC)
+#include 
+#include "NuMicro.h"
+
+#if defined(PKG_USING_FAL)
+    #include 
+#endif
+
+/* Private define ---------------------------------------------------------------*/
+#define NU_GETBYTE_OFST(addr)         (((addr)&0x3)*8)
+#define NU_GET_WALIGN(addr)           ((addr)&~0x3)
+#define NU_GET_LSB2BIT(addr)          ((addr)&0x3)
+/* Private typedef --------------------------------------------------------------*/
+
+/* Private functions ------------------------------------------------------------*/
+static int nu_fmc_init(void);
+#if defined(PKG_USING_FAL)
+    static int aprom_read(long offset, uint8_t *buf, size_t size);
+    static int aprom_write(long offset, const uint8_t *buf, size_t size);
+    static int aprom_erase(long offset, size_t size);
+
+    static int ldrom_read(long offset, uint8_t *buf, size_t size);
+    static int ldrom_write(long offset, const uint8_t *buf, size_t size);
+    static int ldrom_erase(long offset, size_t size);
+#endif  /* PKG_USING_FAL */
+
+/* Public functions -------------------------------------------------------------*/
+int nu_fmc_read(long offset, uint8_t *buf, size_t size);
+int nu_fmc_write(long offset, const uint8_t *buf, size_t size);
+int nu_fmc_erase(long offset, size_t size);
+
+/* Private variables ------------------------------------------------------------*/
+static rt_mutex_t g_mutex_fmc = RT_NULL;
+
+/* Public variables -------------------------------------------------------------*/
+#if defined(PKG_USING_FAL)
+const struct fal_flash_dev Onchip_aprom_flash = { "OnChip_APROM", FMC_APROM_BASE, FMC_APROM_END, FMC_FLASH_PAGE_SIZE, {NULL, aprom_read, aprom_write, aprom_erase} };
+const struct fal_flash_dev Onchip_ldrom_flash = { "OnChip_LDROM", FMC_LDROM_BASE, FMC_LDROM_END, FMC_FLASH_PAGE_SIZE, {NULL, ldrom_read, ldrom_write, ldrom_erase} };
+#endif  /* PKG_USING_FAL */
+
+int nu_fmc_read(long addr, uint8_t *buf, size_t size)
+{
+    size_t read_size = 0;
+    uint32_t addr_end = addr + size;
+    uint32_t isp_rdata = 0;
+    rt_mutex_take(g_mutex_fmc, RT_WAITING_FOREVER);
+    SYS_UnlockReg();
+
+    if (NU_GET_LSB2BIT(addr))
+        isp_rdata = FMC_Read(NU_GET_WALIGN(addr));
+
+
+    for (; addr < addr_end ;)
+    {
+        if (NU_GET_LSB2BIT(addr) == 0)
+        {
+            isp_rdata = FMC_Read(addr);
+            if (addr_end - addr >= 4)
+            {
+                *(uint32_t *)buf = isp_rdata;
+                addr += 4;
+                buf += 4;
+                read_size += 4;
+                continue;
+            }
+        }
+
+        *buf = isp_rdata >> NU_GETBYTE_OFST(addr);
+        addr++;
+        buf++;
+        read_size++;
+
+    }
+
+    SYS_LockReg();
+    rt_mutex_release(g_mutex_fmc);
+
+    return read_size;
+}
+
+int nu_fmc_write(long addr, const uint8_t *buf, size_t size)
+{
+    size_t write_size = 0;
+    uint32_t addr_end = addr + size;
+    uint32_t isp_rdata = 0;
+
+    rt_mutex_take(g_mutex_fmc, RT_WAITING_FOREVER);
+    SYS_UnlockReg();
+
+    if (addr < FMC_APROM_END)
+        FMC_ENABLE_AP_UPDATE();
+    else if ((addr < FMC_LDROM_END) && addr >= FMC_LDROM_BASE)
+        FMC_ENABLE_LD_UPDATE();
+    else
+    {
+        goto Exit2;
+    }
+
+    if (NU_GET_LSB2BIT(addr))
+        isp_rdata = FMC_Read(NU_GET_WALIGN(addr));
+
+    for (; addr < addr_end ;)
+    {
+
+        if (addr_end - addr >= 4 && NU_GET_LSB2BIT(addr) == 0)
+        {
+            FMC_Write(addr, *((uint32_t *)buf));
+            addr += 4;
+            buf += 4;
+            write_size += 4;
+            continue;
+        }
+
+        if ((NU_GET_LSB2BIT(addr)) == 0x0)
+            isp_rdata = FMC_Read(NU_GET_WALIGN(addr));
+
+        isp_rdata = (isp_rdata & ~(0xFF << NU_GETBYTE_OFST(addr))) | ((*buf) << NU_GETBYTE_OFST(addr));
+
+        if ((NU_GET_LSB2BIT(addr)) == 0x3)
+            FMC_Write(NU_GET_WALIGN(addr), isp_rdata);
+
+        addr++;
+        buf++;
+        write_size++;
+
+    }
+
+    if (NU_GET_LSB2BIT(addr))
+        FMC_Write(NU_GET_WALIGN(addr), isp_rdata);
+
+    FMC_DISABLE_AP_UPDATE();
+    FMC_DISABLE_LD_UPDATE();
+Exit2:
+    SYS_LockReg();
+    rt_mutex_release(g_mutex_fmc);
+
+    return write_size;
+
+}
+
+int nu_fmc_erase(long addr, size_t size)
+{
+    size_t erased_size = 0;
+    uint32_t addrptr;
+    uint32_t addr_end = addr + size;
+
+#if defined(NU_SUPPORT_NONALIGN)
+    uint8_t *page_sdtemp = RT_NULL;
+    uint8_t *page_edtemp = RT_NULL;
+
+
+    addrptr = addr & (FMC_FLASH_PAGE_SIZE - 1);
+    if (addrptr)
+    {
+        page_sdtemp = rt_malloc(addrptr);
+        if (page_sdtemp == RT_NULL)
+        {
+            erased_size = 0;
+
+            goto Exit3;
+        }
+
+        if (nu_fmc_read(addr & ~(FMC_FLASH_PAGE_SIZE - 1), page_sdtemp, addrptr) != addrptr)
+        {
+
+            erased_size = 0;
+
+            goto Exit3;
+        }
+
+    }
+
+    addrptr = addr_end & (FMC_FLASH_PAGE_SIZE - 1);
+    if (addrptr)
+    {
+        page_edtemp = rt_malloc(FMC_FLASH_PAGE_SIZE - addrptr);
+        if (page_edtemp == RT_NULL)
+        {
+            erased_size = 0;
+
+            goto Exit3;
+        }
+
+        if (nu_fmc_read(addr_end, page_edtemp, FMC_FLASH_PAGE_SIZE - addrptr) != FMC_FLASH_PAGE_SIZE - addrptr)
+        {
+            erased_size = 0;
+
+            goto Exit3;
+        }
+
+    }
+#endif
+
+    rt_mutex_take(g_mutex_fmc, RT_WAITING_FOREVER);
+    SYS_UnlockReg();
+
+    if (addr <= FMC_APROM_END)
+        FMC_ENABLE_AP_UPDATE();
+    else if ((addr < FMC_LDROM_END) && addr >= FMC_LDROM_BASE)
+        FMC_ENABLE_LD_UPDATE();
+    else
+    {
+        goto Exit2;
+    }
+
+    addrptr = (addr & ~(FMC_FLASH_PAGE_SIZE - 1));
+    while (addrptr < addr_end)
+    {
+        if (FMC_Erase(addrptr) != RT_EOK)
+        {
+            goto Exit1;
+        }
+        erased_size += FMC_FLASH_PAGE_SIZE;
+        addrptr += FMC_FLASH_PAGE_SIZE;
+    }
+
+Exit1:
+    FMC_DISABLE_AP_UPDATE();
+    FMC_DISABLE_LD_UPDATE();
+Exit2:
+    SYS_LockReg();
+    rt_mutex_release(g_mutex_fmc);
+
+#if defined(NU_SUPPORT_NONALIGN)
+
+    if (erased_size >= size)
+    {
+        addrptr = addr & (FMC_FLASH_PAGE_SIZE - 1);
+        if (addrptr)
+        {
+            if (nu_fmc_write(addr & ~(FMC_FLASH_PAGE_SIZE - 1), page_sdtemp, addrptr) != addrptr)
+                goto Exit3;
+
+            erased_size += addrptr;
+        }
+
+        addrptr = addr_end & (FMC_FLASH_PAGE_SIZE - 1);
+        if (addrptr)
+        {
+
+            if (nu_fmc_write(addr_end, page_edtemp, FMC_FLASH_PAGE_SIZE - addrptr) != FMC_FLASH_PAGE_SIZE - addrptr)
+                goto Exit3;
+
+            erased_size += FMC_FLASH_PAGE_SIZE - addrptr;
+
+        }
+    }
+    else
+        erased_size = 0;
+
+
+Exit3:
+    if (page_sdtemp != RT_NULL)
+        rt_free(page_sdtemp);
+
+    if (page_edtemp != RT_NULL)
+        rt_free(page_edtemp);
+#endif
+
+    return erased_size;
+}
+
+#if defined(PKG_USING_FAL)
+
+static int aprom_read(long offset, uint8_t *buf, size_t size)
+{
+    return nu_fmc_read(Onchip_aprom_flash.addr + offset, buf, size);
+}
+
+static int aprom_write(long offset, const uint8_t *buf, size_t size)
+{
+    return nu_fmc_write(Onchip_aprom_flash.addr + offset, buf, size);
+}
+
+static int aprom_erase(long offset, size_t size)
+{
+    return nu_fmc_erase(Onchip_aprom_flash.addr + offset, size);
+}
+
+static int ldrom_read(long offset, uint8_t *buf, size_t size)
+{
+    return nu_fmc_read(Onchip_ldrom_flash.addr + offset, buf, size);
+}
+
+static int ldrom_write(long offset, const uint8_t *buf, size_t size)
+{
+    return nu_fmc_write(Onchip_ldrom_flash.addr + offset, buf, size);
+}
+
+static int ldrom_erase(long offset, size_t size)
+{
+    return nu_fmc_erase(Onchip_ldrom_flash.addr + offset, size);
+}
+
+#endif /* PKG_USING_FAL */
+
+static int nu_fmc_init(void)
+{
+    SYS_UnlockReg();
+    FMC_ENABLE_ISP();
+    SYS_LockReg();
+
+    g_mutex_fmc = rt_mutex_create("nu_fmc_lock", RT_IPC_FLAG_FIFO);
+
+    /* PKG_USING_FAL */
+#if defined(PKG_USING_FAL)
+    fal_init();
+#endif
+
+    return (int)RT_EOK;
+}
+INIT_APP_EXPORT(nu_fmc_init);
+
+#endif /* BSP_USING_FMC */
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_fmc.h b/bsp/nuvoton/libraries/m2354/rtt_port/drv_fmc.h
new file mode 100644
index 0000000000..d189d1102c
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_fmc.h
@@ -0,0 +1,24 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-3-03       FYChou           First version
+*
+******************************************************************************/
+
+#ifndef __DRV_FMC_H__
+#define __DRV_FMC_H__
+
+#include 
+#include "NuMicro.h"
+
+int nu_fmc_read(long offset, uint8_t *buf, size_t size);
+int nu_fmc_write(long offset, const uint8_t *buf, size_t size);
+int nu_fmc_erase(long offset, size_t size);
+
+
+#endif // __DRV_FMC_H___
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_gpio.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_gpio.c
new file mode 100644
index 0000000000..727ef964fa
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_gpio.c
@@ -0,0 +1,422 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-6-17       YCHuang12        First version
+*
+******************************************************************************/
+
+#include 
+
+#if (defined(BSP_USING_GPIO) && defined(RT_USING_PIN))
+
+#include 
+#include 
+#include "NuMicro.h"
+#include 
+#include 
+#include 
+
+/* Private define ---------------------------------------------------------------*/
+
+#define PORT_OFFSET         0x40
+#define IRQ_MAX_NUM         16            //Max support 32
+#define MAX_PORTH_PIN_MAX   11
+
+/* Private functions ------------------------------------------------------------*/
+
+static void nu_gpio_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode);
+static void nu_gpio_write(struct rt_device *device, rt_base_t pin, rt_base_t value);
+static int nu_gpio_read(struct rt_device *device, rt_base_t pin);
+static rt_err_t nu_gpio_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args);
+static rt_err_t nu_gpio_detach_irq(struct rt_device *device, rt_int32_t pin);
+static rt_err_t nu_gpio_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled);
+static rt_base_t nu_gpio_pin_get(const char *name);
+
+/* Private variables ------------------------------------------------------------*/
+static struct rt_pin_irq_hdr pin_irq_hdr_tab[IRQ_MAX_NUM];
+static struct rt_pin_ops nu_gpio_ops =
+{
+    nu_gpio_mode,
+    nu_gpio_write,
+    nu_gpio_read,
+    nu_gpio_attach_irq,
+    nu_gpio_detach_irq,
+    nu_gpio_irq_enable,
+    nu_gpio_pin_get,
+};
+
+static IRQn_Type au32GPIRQ[NU_PORT_CNT] = {GPA_IRQn, GPB_IRQn, GPC_IRQn, GPD_IRQn, GPE_IRQn, GPF_IRQn, GPG_IRQn, GPH_IRQn};
+
+static rt_uint32_t g_u32PinIrqMask = 0x0;
+
+/* Functions define ------------------------------------------------------------*/
+
+static rt_err_t nu_port_check(rt_int32_t pin)
+{
+    if (NU_GET_PORT(pin) >= NU_PORT_CNT)
+        return -(RT_ERROR);
+    else if ((NU_GET_PORT(pin) == NU_PH) && (NU_GET_PINS(pin) > MAX_PORTH_PIN_MAX))
+        return -(RT_ERROR);
+
+    return RT_EOK;
+}
+
+static rt_int32_t nu_find_irqindex(rt_uint32_t pin_index)
+{
+    rt_int32_t irqindex;
+    rt_int32_t u32PinIrqStatus = g_u32PinIrqMask;
+
+    // Find index of pin is attached in pool.
+    while ((irqindex = nu_ctz(u32PinIrqStatus)) < IRQ_MAX_NUM) // Count Trailing Zeros ==> Find First One
+    {
+        if (pin_irq_hdr_tab[irqindex].pin == pin_index)
+            return irqindex;
+
+        u32PinIrqStatus &= ~(1 << irqindex);
+    }
+
+    return -(RT_ERROR);
+}
+
+static void pin_irq_hdr(rt_uint32_t irq_status, rt_uint32_t port_index)
+{
+    rt_int32_t irqindex, i;
+    rt_int32_t pinindex = port_index * GPIO_PIN_MAX ;
+
+    while ((i = nu_ctz(irq_status)) < GPIO_PIN_MAX)// Count Trailing Zeros ==> Find First One
+    {
+        int pin_mask = (1 << i);
+        irqindex = nu_find_irqindex(pinindex + i);
+        if (irqindex != -(RT_ERROR))
+        {
+            if (pin_irq_hdr_tab[irqindex].hdr)
+            {
+                pin_irq_hdr_tab[irqindex].hdr(pin_irq_hdr_tab[irqindex].args);
+            }
+        }
+        // Clear the served bit.
+        irq_status &= ~pin_mask;
+    }
+}
+
+static rt_base_t nu_gpio_pin_get(const char *name)
+{
+    /* Get pin number by name,such as PA.0, PF12 */
+    if ((name[2] == '\0') || ((name[2] == '.') && (name[3] == '\0')))
+        return -(RT_EINVAL);
+
+    long number;
+
+    if ((name[2] == '.'))
+        number = atol(&name[3]);
+    else
+        number = atol(&name[2]);
+
+    if (number > 15)
+        return -(RT_EINVAL);
+
+    if (name[1] >= 'A' && name[1] <= 'H')
+        return ((name[1] - 'A') * 0x10) + number;
+
+    if (name[1] >= 'a' && name[1] <= 'h')
+        return ((name[1] - 'a') * 0x10) + number;
+
+    return -(RT_EINVAL);
+}
+
+static void nu_gpio_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode)
+{
+    GPIO_T *PORT;
+
+    if (nu_port_check(pin))
+        return;
+
+    PORT = (GPIO_T *)(GPIOA_BASE + (NU_GET_PORT(pin) * PORT_OFFSET));
+
+    if (mode == PIN_MODE_INPUT_PULLUP)
+    {
+        GPIO_SetMode(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_MODE_INPUT);
+        GPIO_SetPullCtl(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_PUSEL_PULL_UP);
+    }
+    else if (mode == PIN_MODE_INPUT_PULLDOWN)
+    {
+        GPIO_SetMode(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_MODE_INPUT);
+        GPIO_SetPullCtl(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_PUSEL_PULL_DOWN);
+    }
+    else if (mode == PIN_MODE_OUTPUT)
+    {
+        GPIO_SetMode(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_MODE_OUTPUT);
+    }
+    else if (mode == PIN_MODE_INPUT)
+    {
+        GPIO_SetMode(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_MODE_INPUT);
+        GPIO_SetPullCtl(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_PUSEL_DISABLE);
+    }
+    else if (mode == PIN_MODE_OUTPUT_OD)
+    {
+        GPIO_SetMode(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_MODE_OPEN_DRAIN);
+        GPIO_SetPullCtl(PORT, NU_GET_PIN_MASK(NU_GET_PINS(pin)), GPIO_PUSEL_DISABLE);
+    }
+}
+
+static void nu_gpio_write(struct rt_device *device, rt_base_t pin, rt_base_t value)
+{
+    if (nu_port_check(pin))
+        return;
+
+    GPIO_PIN_DATA_S(NU_GET_PORT(pin), NU_GET_PINS(pin)) = value;
+}
+
+static int nu_gpio_read(struct rt_device *device, rt_base_t pin)
+{
+    if (nu_port_check(pin))
+        return PIN_LOW;
+
+    return GPIO_PIN_DATA_S(NU_GET_PORT(pin), NU_GET_PINS(pin));
+}
+
+static rt_err_t nu_gpio_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+    rt_base_t level;
+    rt_int32_t irqindex;
+
+    if (nu_port_check(pin))
+        return -(RT_ERROR);
+
+    level = rt_hw_interrupt_disable();
+
+    // Find index of pin is attached in pool.
+    if ((irqindex = nu_find_irqindex(pin)) >= 0)
+        goto exit_nu_gpio_attach_irq;
+
+    // Find available index of pin in pool.
+    if ((irqindex = nu_cto(g_u32PinIrqMask)) < IRQ_MAX_NUM)  // Count Trailing Ones ==> Find First Zero
+        goto exit_nu_gpio_attach_irq;
+
+    rt_hw_interrupt_enable(level);
+
+    return -(RT_EBUSY);
+
+exit_nu_gpio_attach_irq:
+
+    pin_irq_hdr_tab[irqindex].pin = pin;
+    pin_irq_hdr_tab[irqindex].hdr = hdr;
+    pin_irq_hdr_tab[irqindex].mode = mode;
+    pin_irq_hdr_tab[irqindex].args = args;
+
+    g_u32PinIrqMask |= (1 << irqindex);
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+
+static rt_err_t nu_gpio_detach_irq(struct rt_device *device, rt_int32_t pin)
+{
+    rt_base_t level;
+    rt_int32_t irqindex;
+    rt_int32_t u32PinIrqStatus;
+
+    if (nu_port_check(pin))
+        return -(RT_ERROR);
+
+    level = rt_hw_interrupt_disable();
+
+    u32PinIrqStatus = g_u32PinIrqMask;
+
+    // Find index of pin is attached in pool.
+    while ((irqindex = nu_ctz(u32PinIrqStatus)) < IRQ_MAX_NUM)// Count Trailing Zeros ==> Find First One
+    {
+        if (pin_irq_hdr_tab[irqindex].pin == pin)
+        {
+            pin_irq_hdr_tab[irqindex].pin = PIN_IRQ_PIN_NONE;
+            pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
+            pin_irq_hdr_tab[irqindex].mode = PIN_IRQ_MODE_RISING;
+            pin_irq_hdr_tab[irqindex].args = RT_NULL;
+            g_u32PinIrqMask &= ~(1 << irqindex);
+            break;
+        }
+        u32PinIrqStatus &= ~(1 << irqindex);
+    }
+
+    rt_hw_interrupt_enable(level);
+    return RT_EOK;
+}
+
+static rt_err_t nu_gpio_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+{
+    GPIO_T *PORT;
+    rt_base_t level;
+    uint32_t u32IntAttribs;
+    rt_int32_t irqindex;
+    rt_err_t ret = RT_EOK;
+
+    if (nu_port_check(pin))
+        return -(RT_ERROR);
+
+    level = rt_hw_interrupt_disable();
+
+    irqindex = nu_find_irqindex(pin);
+    if (irqindex == -(RT_ERROR))
+    {
+        ret = RT_ERROR;
+        goto exit_nu_gpio_irq_enable;
+    }
+
+    PORT = (GPIO_T *)(GPIOA_BASE + (NU_GET_PORT(pin) * PORT_OFFSET));
+
+    if (enabled == PIN_IRQ_ENABLE)
+    {
+        if (pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_RISING)
+            u32IntAttribs = GPIO_INT_RISING;
+        else if (pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_FALLING)
+            u32IntAttribs = GPIO_INT_FALLING;
+        else if (pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_RISING_FALLING)
+            u32IntAttribs = GPIO_INT_BOTH_EDGE;
+        else if (pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_HIGH_LEVEL)
+            u32IntAttribs = GPIO_INT_HIGH;
+        else if (pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_LOW_LEVEL)
+            u32IntAttribs = GPIO_INT_LOW;
+        else
+            goto exit_nu_gpio_irq_enable;
+
+        GPIO_EnableInt(PORT, NU_GET_PINS(pin), u32IntAttribs);
+
+        NVIC_EnableIRQ(au32GPIRQ[NU_GET_PORT(pin)]);
+    }
+    else
+    {
+        GPIO_DisableInt(PORT, NU_GET_PINS(pin));
+    }
+
+exit_nu_gpio_irq_enable:
+
+    rt_hw_interrupt_enable(level);
+    return -(ret);
+}
+
+int rt_hw_gpio_init(void)
+{
+    rt_int32_t irqindex;
+    for (irqindex = 0; irqindex < IRQ_MAX_NUM ; irqindex++)
+    {
+        pin_irq_hdr_tab[irqindex].pin = PIN_IRQ_PIN_NONE;
+        pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
+        pin_irq_hdr_tab[irqindex].mode = PIN_IRQ_MODE_RISING;
+        pin_irq_hdr_tab[irqindex].args = RT_NULL;
+    }
+
+    return rt_device_pin_register("gpio", &nu_gpio_ops, RT_NULL);
+}
+
+INIT_BOARD_EXPORT(rt_hw_gpio_init);
+
+void GPA_IRQHandler(void)
+{
+    rt_uint32_t int_status;
+
+    rt_interrupt_enter();
+
+    int_status = PA->INTSRC;
+    pin_irq_hdr(int_status, NU_PA);
+    PA->INTSRC = int_status;
+
+    rt_interrupt_leave();
+}
+
+void GPB_IRQHandler(void)
+{
+    rt_uint32_t int_status;
+
+    rt_interrupt_enter();
+
+    int_status = PB->INTSRC;
+    pin_irq_hdr(int_status, NU_PB);
+    PB->INTSRC = int_status;
+
+    rt_interrupt_leave();
+}
+
+void GPC_IRQHandler(void)
+{
+    rt_uint32_t int_status;
+
+    rt_interrupt_enter();
+
+    int_status = PC->INTSRC;
+    pin_irq_hdr(int_status, NU_PC);
+    PC->INTSRC = int_status;
+
+    rt_interrupt_leave();
+}
+
+void GPD_IRQHandler(void)
+{
+    rt_uint32_t int_status;
+
+    rt_interrupt_enter();
+
+    int_status = PD->INTSRC;
+    pin_irq_hdr(int_status, NU_PD);
+    PD->INTSRC = int_status;
+
+    rt_interrupt_leave();
+}
+
+void GPE_IRQHandler(void)
+{
+    rt_uint32_t int_status;
+
+    rt_interrupt_enter();
+
+    int_status = PE->INTSRC;
+    pin_irq_hdr(int_status, NU_PE);
+    PE->INTSRC = int_status;
+
+    rt_interrupt_leave();
+}
+
+void GPF_IRQHandler(void)
+{
+    rt_uint32_t int_status;
+
+    rt_interrupt_enter();
+
+    int_status = PF->INTSRC;
+    pin_irq_hdr(int_status, NU_PF);
+    PF->INTSRC = int_status;
+
+    rt_interrupt_leave();
+}
+
+void GPG_IRQHandler(void)
+{
+    rt_uint32_t int_status;
+
+    rt_interrupt_enter();
+
+    int_status = PG->INTSRC;
+    pin_irq_hdr(int_status, NU_PG);
+    PG->INTSRC = int_status;
+
+    rt_interrupt_leave();
+}
+
+void GPH_IRQHandler(void)
+{
+    rt_uint32_t int_status;
+
+    rt_interrupt_enter();
+
+    int_status = PH->INTSRC;
+    pin_irq_hdr(int_status, NU_PH);
+    PH->INTSRC = int_status;
+
+    rt_interrupt_leave();
+}
+
+#endif //#if (defined(BSP_USING_GPIO) && defined(RT_USING_PIN))
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_gpio.h b/bsp/nuvoton/libraries/m2354/rtt_port/drv_gpio.h
new file mode 100644
index 0000000000..636acb85b3
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_gpio.h
@@ -0,0 +1,34 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-6-17       YCHuang12        First version
+*
+******************************************************************************/
+
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+typedef enum
+{
+    NU_PA,
+    NU_PB,
+    NU_PC,
+    NU_PD,
+    NU_PE,
+    NU_PF,
+    NU_PG,
+    NU_PH,
+    NU_PORT_CNT,
+} nu_gpio_port;
+
+#define NU_GET_PININDEX(port, pin)        ((port)*16+(pin))
+#define NU_GET_PINS(rt_pin_index)         ((rt_pin_index) & 0x0000000F)
+#define NU_GET_PORT(rt_pin_index)         (((rt_pin_index)>>4) & 0x0000000F)
+#define NU_GET_PIN_MASK(nu_gpio_pin)      (1 << (nu_gpio_pin))
+
+#endif //__DRV_GPIO_H__
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_i2c.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_i2c.c
new file mode 100644
index 0000000000..eba23ef245
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_i2c.c
@@ -0,0 +1,390 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author         Notes
+* 2020-2-05       HPHuang        First version
+******************************************************************************/
+
+
+#include 
+
+#ifdef BSP_USING_I2C
+#include 
+#include "NuMicro.h"
+
+/* Private define ---------------------------------------------------------------*/
+#define LOG_TAG         "drv.i2c"
+#define DBG_ENABLE
+#define DBG_SECTION_NAME "drv.i2c"
+#define DBG_LEVEL DBG_ERROR
+#define DBG_COLOR
+#include 
+
+const rt_uint32_t u32I2C_MASTER_STATUS_START                  = 0x08UL;
+const rt_uint32_t u32I2C_MASTER_STATUS_REPEAT_START           = 0x10UL;
+const rt_uint32_t u32I2C_MASTER_STATUS_TRANSMIT_ADDRESS_ACK   = 0x18UL;
+const rt_uint32_t u32I2C_MASTER_STATUS_TRANSMIT_ADDRESS_NACK  = 0x20UL;
+const rt_uint32_t u32I2C_MASTER_STATUS_TRANSMIT_DATA_ACK      = 0x28UL;
+const rt_uint32_t u32I2C_MASTER_STATUS_TRANSMIT_DATA_NACK     = 0x30UL;
+const rt_uint32_t u32I2C_MASTER_STATUS_ARBITRATION_LOST       = 0x38UL;
+const rt_uint32_t u32I2C_MASTER_STATUS_RECEIVE_ADDRESS_ACK    = 0x40UL;
+const rt_uint32_t u32I2C_MASTER_STATUS_RECEIVE_ADDRESS_NACK   = 0x48UL;
+const rt_uint32_t u32I2C_MASTER_STATUS_RECEIVE_DATA_ACK       = 0x50UL;
+const rt_uint32_t u32I2C_MASTER_STATUS_RECEIVE_DATA_NACK      = 0x58UL;
+const rt_uint32_t u32I2C_MASTER_STATUS_BUS_ERROR              = 0x00UL;
+const rt_uint32_t u32I2C_MASTER_STATUS_BUS_RELEASED           = 0xF8UL;
+
+/* Private typedef --------------------------------------------------------------*/
+typedef struct _nu_i2c_bus
+{
+    struct rt_i2c_bus_device parent;
+    I2C_T *I2C;
+    struct rt_i2c_msg *msg;
+    char *device_name;
+} nu_i2c_bus_t;
+
+/* Private variables ------------------------------------------------------------*/
+#ifdef BSP_USING_I2C0
+#define I2C0BUS_NAME  "i2c0"
+static nu_i2c_bus_t nu_i2c0 =
+{
+    .I2C = I2C0,
+    .device_name = I2C0BUS_NAME,
+};
+#endif /* BSP_USING_I2C0 */
+
+#ifdef BSP_USING_I2C1
+#define I2C1BUS_NAME  "i2c1"
+static nu_i2c_bus_t nu_i2c1 =
+{
+    .I2C = I2C1,
+    .device_name = I2C1BUS_NAME,
+};
+#endif /* BSP_USING_I2C1 */
+
+#ifdef BSP_USING_I2C2
+#define I2C2BUS_NAME  "i2c2"
+static nu_i2c_bus_t nu_i2c2 =
+{
+    .I2C = I2C2,
+    .device_name = I2C2BUS_NAME,
+};
+#endif /* BSP_USING_I2C2 */
+
+/* Private functions ------------------------------------------------------------*/
+#if (defined(BSP_USING_I2C0) || defined(BSP_USING_I2C1) || defined(BSP_USING_I2C2))
+
+static rt_size_t nu_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
+                                 struct rt_i2c_msg msgs[],
+                                 rt_uint32_t num);
+
+static const struct rt_i2c_bus_device_ops nu_i2c_ops =
+{
+    .master_xfer        = nu_i2c_mst_xfer,
+    .slave_xfer         = NULL,
+    .i2c_bus_control    = NULL,
+};
+
+static rt_err_t nu_i2c_configure(nu_i2c_bus_t *bus)
+{
+    RT_ASSERT(bus != RT_NULL);
+
+    bus->parent.ops = &nu_i2c_ops;
+    I2C_Open(bus->I2C, 100000);
+
+    return RT_EOK;
+}
+
+static inline rt_err_t nu_i2c_wait_ready_with_timeout(nu_i2c_bus_t *bus)
+{
+    rt_tick_t start = rt_tick_get();
+    while (!(bus->I2C->CTL0 & I2C_CTL0_SI_Msk))
+    {
+        if ((rt_tick_get() - start) > bus->parent.timeout)
+        {
+            LOG_E("\ni2c: timeout!\n");
+            return -RT_ETIMEOUT;
+        }
+    }
+
+    return RT_EOK;
+}
+
+static inline rt_err_t nu_i2c_send_data(nu_i2c_bus_t *nu_i2c, rt_uint8_t data)
+{
+    I2C_SET_DATA(nu_i2c->I2C, data);
+    I2C_SET_CONTROL_REG(nu_i2c->I2C, I2C_CTL_SI);
+    return nu_i2c_wait_ready_with_timeout(nu_i2c);
+}
+
+static rt_err_t nu_i2c_send_address(nu_i2c_bus_t *nu_i2c,
+                                    struct rt_i2c_msg  *msg)
+{
+    rt_uint16_t flags = msg->flags;
+    rt_uint16_t ignore_nack = msg->flags & RT_I2C_IGNORE_NACK;
+    rt_uint8_t addr1, addr2;
+    rt_err_t ret;
+
+
+    if (flags & RT_I2C_ADDR_10BIT)
+    {
+        nu_i2c->I2C->CTL1 |= I2C_CTL1_ADDR10EN_Msk;
+        addr1 = 0xf0 | ((msg->addr >> 7) & 0x06);
+        addr2 = msg->addr & 0xff;
+
+        LOG_D("address1: %d, address2: %d\n", addr1, addr2);
+
+        ret = nu_i2c_send_data(nu_i2c, addr1);
+        if (ret != RT_EOK) /* for timeout condition */
+            return -RT_EIO;
+
+        if ((I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_TRANSMIT_ADDRESS_ACK) && !ignore_nack)
+        {
+            LOG_E("NACK: sending first address failed\n");
+
+            return -RT_EIO;
+        }
+
+        ret = nu_i2c_send_data(nu_i2c,  addr2);
+        if (ret != RT_EOK) /* for timeout condition */
+            return -RT_EIO;
+
+        if ((I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_TRANSMIT_ADDRESS_ACK) && !ignore_nack)
+        {
+            LOG_E("NACK: sending second address failed\n");
+
+            return -RT_EIO;
+        }
+
+        if (flags & RT_I2C_RD)
+        {
+            LOG_D("send repeated START signal\n");
+
+            I2C_SET_CONTROL_REG(nu_i2c->I2C, I2C_CTL_STA_SI);
+            ret = nu_i2c_wait_ready_with_timeout(nu_i2c);
+            if (ret != RT_EOK) /* for timeout condition */
+                return -RT_EIO;
+
+            if ((I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_REPEAT_START) && !ignore_nack)
+            {
+                LOG_E("sending repeated START failed\n");
+
+                return -RT_EIO;
+            }
+
+            addr1 |= 0x01;
+
+            ret = nu_i2c_send_data(nu_i2c,  addr1);
+            if (ret != RT_EOK) /* for timeout condition */
+                return -RT_EIO;
+
+            if ((I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_RECEIVE_ADDRESS_ACK) && !ignore_nack)
+            {
+                LOG_E("NACK: sending read address failed\n");
+
+                return -RT_EIO;
+            }
+        }
+    }
+    else
+    {
+        /* 7-bit addr */
+        addr1 = msg->addr << 1;
+        if (flags & RT_I2C_RD)
+            addr1 |= 1;
+
+        /* Send device address */
+        ret = nu_i2c_send_data(nu_i2c,  addr1); /* Send Address */
+        if (ret != RT_EOK) /* for timeout condition */
+            return -RT_EIO;
+
+        if ((I2C_GET_STATUS(nu_i2c->I2C)
+                != ((flags & RT_I2C_RD) ? u32I2C_MASTER_STATUS_RECEIVE_ADDRESS_ACK : u32I2C_MASTER_STATUS_TRANSMIT_ADDRESS_ACK))
+                && !ignore_nack)
+        {
+            LOG_E("sending address failed\n");
+            return -RT_EIO;
+        }
+    }
+
+    return RT_EOK;
+}
+
+static rt_size_t nu_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
+                                 struct rt_i2c_msg msgs[],
+                                 rt_uint32_t num)
+{
+    struct rt_i2c_msg *msg;
+    nu_i2c_bus_t *nu_i2c;
+    rt_size_t i;
+    rt_uint32_t cnt_data;
+    rt_uint16_t ignore_nack;
+    rt_err_t ret;
+
+    RT_ASSERT(bus != RT_NULL);
+    nu_i2c = (nu_i2c_bus_t *) bus;
+
+    nu_i2c->msg = msgs;
+
+    nu_i2c->I2C->CTL0 |= I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk;
+    ret = nu_i2c_wait_ready_with_timeout(nu_i2c);
+    if (ret != RT_EOK) /* for timeout condition */
+    {
+        rt_set_errno(-RT_ETIMEOUT);
+        return 0;
+    }
+    if (I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_START)
+    {
+        i = 0;
+        LOG_E("Send START Failed");
+        return i;
+    }
+
+    for (i = 0; i < num; i++)
+    {
+        msg = &msgs[i];
+        ignore_nack = msg->flags & RT_I2C_IGNORE_NACK;
+
+        if (!(msg->flags & RT_I2C_NO_START))
+        {
+            if (i)
+            {
+                I2C_SET_CONTROL_REG(nu_i2c->I2C, I2C_CTL_STA_SI);
+                ret = nu_i2c_wait_ready_with_timeout(nu_i2c);
+                if (ret != RT_EOK) /* for timeout condition */
+                    break;
+
+                if (I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_REPEAT_START)
+                {
+                    i = 0;
+                    LOG_E("Send repeat START Fail");
+                    break;
+                }
+            }
+
+            if ((RT_EOK != nu_i2c_send_address(nu_i2c, msg))
+                    && !ignore_nack)
+            {
+                i = 0;
+                LOG_E("Send Address Fail");
+                break;
+            }
+        }
+
+
+        if (nu_i2c->msg[i].flags & RT_I2C_RD) /* Receive Bytes */
+        {
+            rt_uint32_t do_rd_nack = (i == (num - 1));
+            for (cnt_data = 0 ; cnt_data < (nu_i2c->msg[i].len) ; cnt_data++)
+            {
+                do_rd_nack += (cnt_data == (nu_i2c->msg[i].len - 1)); /* NACK after last byte  for hardware setting */
+                if (do_rd_nack == 2)
+                {
+                    I2C_SET_CONTROL_REG(nu_i2c->I2C, I2C_CTL_SI);
+                }
+                else
+                {
+                    I2C_SET_CONTROL_REG(nu_i2c->I2C, I2C_CTL_SI_AA);
+                }
+
+                ret = nu_i2c_wait_ready_with_timeout(nu_i2c);
+                if (ret != RT_EOK) /* for timeout condition */
+                    break;
+
+                if (nu_i2c->I2C->CTL0 & I2C_CTL_AA)
+                {
+                    if (I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_RECEIVE_DATA_ACK)
+                    {
+                        i = 0;
+                        break;
+                    }
+                }
+                else
+                {
+                    if (I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_RECEIVE_DATA_NACK)
+                    {
+                        i = 0;
+                        break;
+                    }
+                }
+
+                nu_i2c->msg[i].buf[cnt_data] = nu_i2c->I2C->DAT;
+            }
+        }
+        else /* Send Bytes */
+        {
+            for (cnt_data = 0 ; cnt_data < (nu_i2c->msg[i].len) ; cnt_data++)
+            {
+                /* Send register number and MSB of data */
+                ret = nu_i2c_send_data(nu_i2c, (uint8_t)(nu_i2c->msg[i].buf[cnt_data]));
+                if (ret != RT_EOK) /* for timeout condition */
+                    break;
+
+                if (I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_TRANSMIT_DATA_ACK
+                        && !ignore_nack
+                   ) /* Send aata and get Ack */
+                {
+                    i = 0;
+                    break;
+                }
+            }
+        }
+    }
+
+    I2C_STOP(nu_i2c->I2C);
+
+    RT_ASSERT(I2C_GET_STATUS(nu_i2c->I2C) == u32I2C_MASTER_STATUS_BUS_RELEASED);
+    if (I2C_GET_STATUS(nu_i2c->I2C) != u32I2C_MASTER_STATUS_BUS_RELEASED)
+    {
+        i = 0;
+    }
+
+    nu_i2c->msg = RT_NULL;
+    nu_i2c->I2C->CTL1 = 0; /*clear all sub modes like 10 bit mode*/
+    return i;
+}
+
+#endif
+
+/* Public functions -------------------------------------------------------------*/
+int rt_hw_i2c_init(void)
+{
+    rt_err_t ret = RT_ERROR;
+#if   defined(BSP_USING_I2C0)
+    SYS_UnlockReg();
+    SYS_ResetModule(I2C0_RST);
+    SYS_LockReg();
+    nu_i2c_configure(&nu_i2c0);
+    ret = rt_i2c_bus_device_register(&nu_i2c0.parent, nu_i2c0.device_name);
+    RT_ASSERT(RT_EOK == ret);
+#endif  /* BSP_USING_I2C0 */
+
+#if   defined(BSP_USING_I2C1)
+    SYS_UnlockReg();
+    SYS_ResetModule(I2C1_RST);
+    SYS_LockReg();
+    nu_i2c_configure(&nu_i2c1);
+    ret = rt_i2c_bus_device_register(&nu_i2c1.parent, nu_i2c1.device_name);
+    RT_ASSERT(RT_EOK == ret);
+#endif  /* BSP_USING_I2C1 */
+
+#if   defined(BSP_USING_I2C2)
+    SYS_UnlockReg();
+    SYS_ResetModule(I2C2_RST);
+    SYS_LockReg();
+    nu_i2c_configure(&nu_i2c2);
+    ret = rt_i2c_bus_device_register(&nu_i2c2.parent, nu_i2c2.device_name);
+    RT_ASSERT(RT_EOK == ret);
+#endif  /* BSP_USING_I2C2 */
+
+    return ret;
+}
+
+INIT_DEVICE_EXPORT(rt_hw_i2c_init);
+
+#endif /* BSP_USING_I2C */
+
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_i2s.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_i2s.c
new file mode 100644
index 0000000000..be576e61c6
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_i2s.c
@@ -0,0 +1,591 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-2-7        Wayne Lin        First version
+*
+******************************************************************************/
+
+#include 
+
+#if defined(BSP_USING_I2S)
+
+#include 
+#include 
+#include 
+
+/* Private define ---------------------------------------------------------------*/
+#define DBG_ENABLE
+#define DBG_LEVEL DBG_LOG
+#define DBG_SECTION_NAME  "i2s"
+#define DBG_COLOR
+#include 
+
+/* Private functions ------------------------------------------------------------*/
+static rt_err_t nu_i2s_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps);
+static rt_err_t nu_i2s_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps);
+static rt_err_t nu_i2s_init(struct rt_audio_device *audio);
+static rt_err_t nu_i2s_start(struct rt_audio_device *audio, int stream);
+static rt_err_t nu_i2s_stop(struct rt_audio_device *audio, int stream);
+static void nu_i2s_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info);
+/* Public functions -------------------------------------------------------------*/
+rt_err_t nu_i2s_acodec_register(nu_acodec_ops_t);
+
+/* Private variables ------------------------------------------------------------*/
+static struct nu_i2s g_nu_i2s_dev =
+{
+    .name = "sound0",
+    .i2s_base  = I2S0,
+    .i2s_rst   = I2S0_RST,
+    .i2s_dais = {
+        [NU_I2S_DAI_PLAYBACK] = {
+            .pdma_perp = PDMA_I2S0_TX,
+        },
+        [NU_I2S_DAI_CAPTURE] = {
+            .pdma_perp = PDMA_I2S0_RX,
+        }
+    }
+};
+
+static void nu_pdma_i2s_rx_cb(void *pvUserData, uint32_t u32EventFilter)
+{
+    nu_i2s_t psNuI2s = (nu_i2s_t)pvUserData;
+    nu_i2s_dai_t psNuI2sDai;
+
+    RT_ASSERT(psNuI2s != RT_NULL);
+    psNuI2sDai = &psNuI2s->i2s_dais[NU_I2S_DAI_CAPTURE];
+
+    if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE)
+    {
+        // Report a buffer ready.
+        rt_uint8_t *pbuf_old = &psNuI2sDai->fifo[psNuI2sDai->fifo_block_idx * NU_I2S_DMA_BUF_BLOCK_SIZE] ;
+        psNuI2sDai->fifo_block_idx = (psNuI2sDai->fifo_block_idx + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER;
+
+        /* Report upper layer. */
+        rt_audio_rx_done(&psNuI2s->audio, pbuf_old, NU_I2S_DMA_BUF_BLOCK_SIZE);
+    }
+}
+
+static void nu_pdma_i2s_tx_cb(void *pvUserData, uint32_t u32EventFilter)
+{
+    nu_i2s_t psNuI2s = (nu_i2s_t)pvUserData;
+    nu_i2s_dai_t psNuI2sDai;
+
+    RT_ASSERT(psNuI2s != RT_NULL);
+    psNuI2sDai = &psNuI2s->i2s_dais[NU_I2S_DAI_PLAYBACK];
+
+    if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE)
+    {
+        rt_audio_tx_complete(&psNuI2s->audio);
+        psNuI2sDai->fifo_block_idx = (psNuI2sDai->fifo_block_idx + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER;
+    }
+}
+
+static rt_err_t nu_i2s_pdma_sc_config(nu_i2s_t psNuI2s, E_NU_I2S_DAI dai)
+{
+    rt_err_t result = RT_EOK;
+    I2S_T *i2s_base;
+    nu_i2s_dai_t psNuI2sDai;
+    int i;
+    uint32_t u32Src, u32Dst;
+    nu_pdma_cb_handler_t pfm_pdma_cb;
+
+    RT_ASSERT(psNuI2s != RT_NULL);
+
+    /* Get base address of i2s register */
+    i2s_base = psNuI2s->i2s_base;
+    psNuI2sDai = &psNuI2s->i2s_dais[dai];
+
+    switch ((int)dai)
+    {
+    case NU_I2S_DAI_PLAYBACK:
+        pfm_pdma_cb = nu_pdma_i2s_tx_cb;
+        u32Src = (uint32_t)&psNuI2sDai->fifo[0];
+        u32Dst = (uint32_t)&i2s_base->TXFIFO;
+        break;
+
+    case NU_I2S_DAI_CAPTURE:
+        pfm_pdma_cb = nu_pdma_i2s_rx_cb;
+        u32Src = (uint32_t)&i2s_base->RXFIFO;
+        u32Dst = (uint32_t)&psNuI2sDai->fifo[0];
+        break;
+
+    default:
+        return -RT_EINVAL;
+    }
+
+    result = nu_pdma_callback_register(psNuI2sDai->pdma_chanid,
+                                       pfm_pdma_cb,
+                                       (void *)psNuI2s,
+                                       NU_PDMA_EVENT_TRANSFER_DONE);
+    RT_ASSERT(result == RT_EOK);
+
+    for (i = 0; i < NU_I2S_DMA_BUF_BLOCK_NUMBER; i++)
+    {
+        /* Setup dma descriptor entry */
+        result = nu_pdma_desc_setup(psNuI2sDai->pdma_chanid,    // Channel ID
+                                    psNuI2sDai->pdma_descs[i], // this descriptor
+                                    32, // 32-bits
+                                    (dai == NU_I2S_DAI_PLAYBACK) ? u32Src + (i * NU_I2S_DMA_BUF_BLOCK_SIZE) : u32Src, //Memory or RXFIFO
+                                    (dai == NU_I2S_DAI_PLAYBACK) ? u32Dst : u32Dst + (i * NU_I2S_DMA_BUF_BLOCK_SIZE), //TXFIFO or Memory
+                                    (int32_t)NU_I2S_DMA_BUF_BLOCK_SIZE / 4,   // Transfer count
+                                    psNuI2sDai->pdma_descs[(i + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER]); // Next descriptor
+        RT_ASSERT(result == RT_EOK);
+    }
+
+    /* Assign head descriptor */
+    result = nu_pdma_sg_transfer(psNuI2sDai->pdma_chanid, psNuI2sDai->pdma_descs[0], 0);
+    RT_ASSERT(result == RT_EOK);
+
+    return result;
+}
+
+static rt_bool_t nu_i2s_capacity_check(struct rt_audio_configure *pconfig)
+{
+    switch (pconfig->samplebits)
+    {
+    case  8:
+    case 16:
+    /* case 24: PDMA constrain */
+    case 32:
+        break;
+    default:
+        goto exit_nu_i2s_capacity_check;
+    }
+
+    switch (pconfig->channels)
+    {
+    case 1:
+    case 2:
+        break;
+    default:
+        goto exit_nu_i2s_capacity_check;
+    }
+
+    return RT_TRUE;
+
+exit_nu_i2s_capacity_check:
+
+    return RT_FALSE;
+}
+
+static rt_err_t nu_i2s_dai_setup(nu_i2s_t psNuI2s, struct rt_audio_configure *pconfig)
+{
+    rt_err_t result = RT_EOK;
+    nu_acodec_ops_t pNuACodecOps = RT_NULL;
+    RT_ASSERT(psNuI2s->AcodecOps != RT_NULL);
+    pNuACodecOps = psNuI2s->AcodecOps;
+    rt_uint32_t real_samplerate;
+
+    /* Open I2S */
+    if (nu_i2s_capacity_check(pconfig) == RT_TRUE)
+    {
+        /* Reset audio codec */
+        if (pNuACodecOps->nu_acodec_reset)
+            result = pNuACodecOps->nu_acodec_reset();
+
+        if (result != RT_EOK)
+            goto exit_nu_i2s_dai_setup;
+
+        /* Setup audio codec */
+        if (pNuACodecOps->nu_acodec_init)
+            result = pNuACodecOps->nu_acodec_init();
+
+        if (!pNuACodecOps->nu_acodec_init || result != RT_EOK)
+            goto exit_nu_i2s_dai_setup;
+
+        /* Setup acodec samplerate/samplebit/channel */
+        if (pNuACodecOps->nu_acodec_dsp_control)
+            result = pNuACodecOps->nu_acodec_dsp_control(pconfig);
+
+        if (!pNuACodecOps->nu_acodec_dsp_control || result != RT_EOK)
+            goto exit_nu_i2s_dai_setup;
+
+        real_samplerate = I2S_Open(psNuI2s->i2s_base,
+                                   (psNuI2s->AcodecOps->role == NU_ACODEC_ROLE_MASTER) ? I2S_MODE_SLAVE : I2S_MODE_MASTER,
+                                   pconfig->samplerate,
+                                   (((pconfig->samplebits / 8) - 1) << I2S_CTL0_DATWIDTH_Pos),
+                                   (pconfig->channels == 1) ? I2S_ENABLE_MONO : I2S_DISABLE_MONO,
+                                   I2S_FORMAT_I2S);
+        LOG_I("Open I2S.");
+
+        /* Open I2S0 interface and set to slave mode, stereo channel, I2S format */
+        if (pconfig->samplerate != real_samplerate)
+        {
+            LOG_W("Real sample rate: %d Hz != preferred sample rate: %d Hz\n", real_samplerate, pconfig->samplerate);
+        }
+
+        /* Set MCLK and enable MCLK */
+        /* The target MCLK is related to audio codec setting. */
+        I2S_EnableMCLK(psNuI2s->i2s_base, 12000000);
+
+        /* Set unmute */
+        if (pNuACodecOps->nu_acodec_mixer_control)
+            pNuACodecOps->nu_acodec_mixer_control(AUDIO_MIXER_MUTE, RT_FALSE);
+    }
+    else
+        result = -RT_EINVAL;
+
+exit_nu_i2s_dai_setup:
+
+    return result;
+}
+
+static rt_err_t nu_i2s_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps)
+{
+    rt_err_t result = RT_EOK;
+    nu_i2s_t psNuI2s;
+    nu_acodec_ops_t pNuACodecOps = RT_NULL;
+
+    RT_ASSERT(audio != RT_NULL);
+    RT_ASSERT(caps != RT_NULL);
+
+    psNuI2s = (nu_i2s_t)audio;
+
+    RT_ASSERT(psNuI2s->AcodecOps != RT_NULL);
+
+    pNuACodecOps = psNuI2s->AcodecOps;
+
+    switch (caps->main_type)
+    {
+    case AUDIO_TYPE_QUERY:
+        switch (caps->sub_type)
+        {
+        case AUDIO_TYPE_QUERY:
+            caps->udata.mask = AUDIO_TYPE_INPUT | AUDIO_TYPE_OUTPUT | AUDIO_TYPE_MIXER;
+            break;
+        default:
+            result = -RT_ERROR;
+            break;
+        } // switch (caps->sub_type)
+        break;
+
+    case AUDIO_TYPE_MIXER:
+
+        if (pNuACodecOps->nu_acodec_mixer_query)
+        {
+            switch (caps->sub_type)
+            {
+            case AUDIO_MIXER_QUERY:
+                return pNuACodecOps->nu_acodec_mixer_query(AUDIO_MIXER_QUERY, &caps->udata.mask);
+
+            default:
+                return pNuACodecOps->nu_acodec_mixer_query(caps->sub_type, (rt_uint32_t *)&caps->udata.value);
+            } // switch (caps->sub_type)
+
+        } // if (pNuACodecOps->nu_acodec_mixer_query)
+
+        result = -RT_ERROR;
+        break;
+
+    case AUDIO_TYPE_INPUT:
+    case AUDIO_TYPE_OUTPUT:
+
+        switch (caps->sub_type)
+        {
+        case AUDIO_DSP_PARAM:
+            caps->udata.config.channels = psNuI2s->config.channels;
+            caps->udata.config.samplebits = psNuI2s->config.samplebits;
+            caps->udata.config.samplerate = psNuI2s->config.samplerate;
+            break;
+        case AUDIO_DSP_SAMPLERATE:
+            caps->udata.config.samplerate = psNuI2s->config.samplerate;
+            break;
+        case AUDIO_DSP_CHANNELS:
+            caps->udata.config.channels = psNuI2s->config.channels;
+            break;
+        case AUDIO_DSP_SAMPLEBITS:
+            caps->udata.config.samplebits = psNuI2s->config.samplebits;
+            break;
+        default:
+            result = -RT_ERROR;
+            break;
+        } // switch (caps->sub_type)
+        break;
+
+    default:
+        result = -RT_ERROR;
+        break;
+
+    } // switch (caps->main_type)
+
+    return result;
+}
+
+static rt_err_t nu_i2s_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps)
+{
+    rt_err_t result = RT_EOK;
+    nu_i2s_t psNuI2s;
+    nu_acodec_ops_t pNuACodecOps = RT_NULL;
+    int stream = -1;
+
+    RT_ASSERT(audio != RT_NULL);
+    RT_ASSERT(caps != RT_NULL);
+
+    psNuI2s = (nu_i2s_t)audio;
+
+    RT_ASSERT(psNuI2s->AcodecOps != RT_NULL);
+    pNuACodecOps = psNuI2s->AcodecOps;
+
+    switch (caps->main_type)
+    {
+    case AUDIO_TYPE_MIXER:
+        if (psNuI2s->AcodecOps->nu_acodec_mixer_control)
+            psNuI2s->AcodecOps->nu_acodec_mixer_control(caps->sub_type, caps->udata.value);
+        break;
+
+
+    case AUDIO_TYPE_INPUT:
+        stream = AUDIO_STREAM_RECORD;
+    case AUDIO_TYPE_OUTPUT:
+    {
+        rt_bool_t bNeedReset = RT_FALSE;
+
+        if (stream < 0)
+            stream = AUDIO_STREAM_REPLAY;
+
+        switch (caps->sub_type)
+        {
+        case AUDIO_DSP_PARAM:
+            if (rt_memcmp(&psNuI2s->config, &caps->udata.config, sizeof(struct rt_audio_configure)) != 0)
+            {
+                rt_memcpy(&psNuI2s->config, &caps->udata.config, sizeof(struct rt_audio_configure));
+                bNeedReset = RT_TRUE;
+            }
+            break;
+        case AUDIO_DSP_SAMPLEBITS:
+            if (psNuI2s->config.samplerate != caps->udata.config.samplebits)
+            {
+                psNuI2s->config.samplerate = caps->udata.config.samplebits;
+                bNeedReset = RT_TRUE;
+            }
+            break;
+        case AUDIO_DSP_CHANNELS:
+            if (psNuI2s->config.channels != caps->udata.config.channels)
+            {
+                pNuACodecOps->config.channels = caps->udata.config.channels;
+                bNeedReset = RT_TRUE;
+            }
+            break;
+        case AUDIO_DSP_SAMPLERATE:
+            if (psNuI2s->config.samplerate != caps->udata.config.samplerate)
+            {
+                psNuI2s->config.samplerate = caps->udata.config.samplerate;
+                bNeedReset = RT_TRUE;
+            }
+            break;
+        default:
+            result = -RT_ERROR;
+            break;
+        } // switch (caps->sub_type)
+
+        if (bNeedReset)
+        {
+            return nu_i2s_start(audio, stream);
+        }
+    }
+    break;
+    default:
+        result = -RT_ERROR;
+        break;
+    } // switch (caps->main_type)
+
+    return result;
+}
+
+static rt_err_t nu_i2s_init(struct rt_audio_device *audio)
+{
+    rt_err_t result = RT_EOK;
+    nu_i2s_t psNuI2s;
+
+    RT_ASSERT(audio != RT_NULL);
+
+    psNuI2s = (nu_i2s_t)audio;
+
+    /* Reset this module */
+    SYS_ResetModule(psNuI2s->i2s_rst);
+
+    return -(result);
+}
+
+static rt_err_t nu_i2s_start(struct rt_audio_device *audio, int stream)
+{
+    nu_i2s_t psNuI2s;
+
+    RT_ASSERT(audio != RT_NULL);
+
+    psNuI2s = (nu_i2s_t)audio;
+
+    /* Restart all: I2S and codec. */
+    nu_i2s_stop(audio, stream);
+    if (nu_i2s_dai_setup(psNuI2s, &psNuI2s->config) != RT_EOK)
+        return -RT_ERROR;
+
+    switch (stream)
+    {
+    case AUDIO_STREAM_REPLAY:
+    {
+        nu_i2s_pdma_sc_config(psNuI2s, NU_I2S_DAI_PLAYBACK);
+
+        /* Start TX DMA */
+        I2S_ENABLE_TXDMA(psNuI2s->i2s_base);
+
+        /* Enable I2S Tx function */
+        I2S_ENABLE_TX(psNuI2s->i2s_base);
+
+        LOG_I("Start replay.");
+    }
+    break;
+
+    case AUDIO_STREAM_RECORD:
+    {
+        nu_i2s_pdma_sc_config(psNuI2s, NU_I2S_DAI_CAPTURE);
+
+        /* Start RX DMA */
+        I2S_ENABLE_RXDMA(psNuI2s->i2s_base);
+
+        /* Enable I2S Rx function */
+        I2S_ENABLE_RX(psNuI2s->i2s_base);
+
+        LOG_I("Start record.");
+    }
+    break;
+
+    default:
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t nu_i2s_stop(struct rt_audio_device *audio, int stream)
+{
+    nu_i2s_t psNuI2s;
+    nu_i2s_dai_t psNuI2sDai = RT_NULL;
+
+    RT_ASSERT(audio != RT_NULL);
+
+    psNuI2s = (nu_i2s_t)audio;
+
+    switch (stream)
+    {
+    case AUDIO_STREAM_REPLAY:
+        psNuI2sDai = &psNuI2s->i2s_dais[NU_I2S_DAI_PLAYBACK];
+
+        // Disable TX
+        I2S_DISABLE_TXDMA(psNuI2s->i2s_base);
+        I2S_DISABLE_TX(psNuI2s->i2s_base);
+
+        LOG_I("Stop replay.");
+        break;
+
+    case AUDIO_STREAM_RECORD:
+        psNuI2sDai = &psNuI2s->i2s_dais[NU_I2S_DAI_CAPTURE];
+
+        // Disable RX
+        I2S_DISABLE_RXDMA(psNuI2s->i2s_base);
+        I2S_DISABLE_RX(psNuI2s->i2s_base);
+
+        LOG_I("Stop record.");
+        break;
+
+    default:
+        return -RT_EINVAL;
+    }
+
+    /* Stop DMA transfer. */
+    nu_pdma_channel_terminate(psNuI2sDai->pdma_chanid);
+
+    /* Close I2S */
+    if (!(psNuI2s->i2s_base->CTL0 & (I2S_CTL0_TXEN_Msk | I2S_CTL0_RXEN_Msk)))
+    {
+        I2S_DisableMCLK(psNuI2s->i2s_base);
+        I2S_Close(psNuI2s->i2s_base);
+        LOG_I("Close I2S.");
+    }
+
+    /* Silence */
+    rt_memset((void *)psNuI2sDai->fifo, 0, NU_I2S_DMA_FIFO_SIZE);
+    psNuI2sDai->fifo_block_idx = 0;
+
+    return RT_EOK;
+}
+
+static void nu_i2s_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info)
+{
+    nu_i2s_t psNuI2s;
+
+    RT_ASSERT(audio != RT_NULL);
+    RT_ASSERT(info != RT_NULL);
+
+    psNuI2s = (nu_i2s_t)audio;
+
+    info->buffer = (rt_uint8_t *)psNuI2s->i2s_dais[NU_I2S_DAI_PLAYBACK].fifo ;
+    info->total_size = NU_I2S_DMA_FIFO_SIZE;
+    info->block_size = NU_I2S_DMA_BUF_BLOCK_SIZE;
+    info->block_count = NU_I2S_DMA_BUF_BLOCK_NUMBER;
+
+    return;
+}
+
+static struct rt_audio_ops nu_i2s_audio_ops =
+{
+    .getcaps     = nu_i2s_getcaps,
+    .configure   = nu_i2s_configure,
+
+    .init        = nu_i2s_init,
+    .start       = nu_i2s_start,
+    .stop        = nu_i2s_stop,
+    .transmit    = RT_NULL,
+    .buffer_info = nu_i2s_buffer_info
+};
+
+static rt_err_t nu_hw_i2s_pdma_allocate(nu_i2s_dai_t psNuI2sDai)
+{
+    /* Allocate I2S nu_dma channel */
+    if ((psNuI2sDai->pdma_chanid = nu_pdma_channel_allocate(psNuI2sDai->pdma_perp)) < 0)
+    {
+        goto nu_hw_i2s_pdma_allocate;
+    }
+
+    return RT_EOK;
+
+nu_hw_i2s_pdma_allocate:
+
+    return -(RT_ERROR);
+}
+
+int rt_hw_i2s_init(void)
+{
+    int i = 0;
+    nu_i2s_dai_t psNuI2sDai;
+
+    for (i = 0; i < NU_I2S_DAI_CNT; i++)
+    {
+        uint8_t *pu8ptr = rt_malloc(NU_I2S_DMA_FIFO_SIZE);
+        psNuI2sDai = &g_nu_i2s_dev.i2s_dais[i];
+        psNuI2sDai->fifo = pu8ptr;
+        rt_memset(pu8ptr, 0, NU_I2S_DMA_FIFO_SIZE);
+        RT_ASSERT(psNuI2sDai->fifo != RT_NULL);
+
+        psNuI2sDai->pdma_chanid = -1;
+        psNuI2sDai->fifo_block_idx = 0;
+        RT_ASSERT(nu_hw_i2s_pdma_allocate(psNuI2sDai) == RT_EOK);
+
+        RT_ASSERT(nu_pdma_sgtbls_allocate(&psNuI2sDai->pdma_descs[0], NU_I2S_DMA_BUF_BLOCK_NUMBER) == RT_EOK);
+    }
+
+    /* Register ops of audio device */
+    g_nu_i2s_dev.audio.ops  = &nu_i2s_audio_ops;
+
+    /* Register device, RW: it is with replay and record functions. */
+    rt_audio_register(&g_nu_i2s_dev.audio, g_nu_i2s_dev.name, RT_DEVICE_FLAG_RDWR, &g_nu_i2s_dev);
+
+    return RT_EOK;
+}
+INIT_DEVICE_EXPORT(rt_hw_i2s_init);
+#endif //#if defined(BSP_USING_I2S)
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_i2s.h b/bsp/nuvoton/libraries/m2354/rtt_port/drv_i2s.h
new file mode 100644
index 0000000000..9ee00646b8
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_i2s.h
@@ -0,0 +1,96 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-2-7        Wayne            First version
+*
+******************************************************************************/
+
+#ifndef __DRV_I2S_H__
+#define __DRV_I2S_H__
+
+#include 
+#include "NuMicro.h"
+#include 
+
+#if !defined(NU_I2S_DMA_FIFO_SIZE)
+    #define NU_I2S_DMA_FIFO_SIZE (2048)
+#endif
+
+#if !defined(NU_I2S_DMA_BUF_BLOCK_NUMBER)
+    #define NU_I2S_DMA_BUF_BLOCK_NUMBER (2)
+#endif
+
+#if ( (NU_I2S_DMA_FIFO_SIZE % NU_I2S_DMA_BUF_BLOCK_NUMBER) != 0 )
+    #error "Please give an aligned definition"
+#endif
+#if ( NU_I2S_DMA_FIFO_SIZE < 2048 )
+    #warning "DMA FIFO too small, miss voice?"
+#endif
+
+#define NU_I2S_DMA_BUF_BLOCK_SIZE (NU_I2S_DMA_FIFO_SIZE/NU_I2S_DMA_BUF_BLOCK_NUMBER)
+
+typedef enum
+{
+    NU_I2S_DAI_PLAYBACK,
+    NU_I2S_DAI_CAPTURE,
+    NU_I2S_DAI_CNT
+} E_NU_I2S_DAI;
+
+typedef enum
+{
+    NU_ACODEC_ROLE_MASTER,
+    NU_ACODEC_ROLE_SLAVE,
+} E_NU_ACODEC_ROLE;
+
+typedef struct
+{
+    char *name;
+
+    E_NU_ACODEC_ROLE role;
+
+    struct rt_audio_configure config;
+
+    rt_err_t (*nu_acodec_init)(void);
+
+    rt_err_t (*nu_acodec_reset)(void);
+
+    rt_err_t (*nu_acodec_dsp_control)(struct rt_audio_configure *config);
+
+    rt_err_t (*nu_acodec_mixer_control)(rt_uint32_t ui32Item, rt_uint32_t ui32Value);
+
+    rt_err_t (*nu_acodec_mixer_query)(rt_uint32_t ui32Item, rt_uint32_t *ui32Value);
+
+} nu_acodec_ops;
+
+typedef nu_acodec_ops *nu_acodec_ops_t;
+
+struct nu_i2s_dai
+{
+    int16_t pdma_perp;
+    int8_t  pdma_chanid;
+    rt_uint8_t *fifo;
+    int16_t  fifo_block_idx;
+    nu_pdma_desc_t pdma_descs[NU_I2S_DMA_BUF_BLOCK_NUMBER];
+};
+typedef struct nu_i2s_dai *nu_i2s_dai_t;
+
+struct nu_i2s
+{
+    struct rt_audio_device audio;
+    struct rt_audio_configure config;
+
+    char *name;
+    I2S_T *i2s_base;
+    uint32_t i2s_rst;
+
+    struct nu_i2s_dai i2s_dais[NU_I2S_DAI_CNT];
+    nu_acodec_ops_t AcodecOps;
+};
+typedef struct nu_i2s *nu_i2s_t;
+
+#endif // __DRV_I2S_H___
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_otg.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_otg.c
new file mode 100644
index 0000000000..23cd82f738
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_otg.c
@@ -0,0 +1,107 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author       Notes
+* 2020-09-17      CHChen       First version
+*
+******************************************************************************/
+#include 
+
+#if defined(BSP_USING_OTG)
+#include 
+#include 
+#include "NuMicro.h"
+
+/* This delay must be at least 10 us */
+static void _usb_init_delay(void)
+{
+    volatile uint32_t i = 0x1000;
+
+    while (i--)
+        __NOP();
+
+    return;
+}
+
+/* Check current usb role */
+static void usb_role(void)
+{
+    uint32_t status;
+
+    status = (OTG->STATUS) & (OTG_STATUS_ASHOST_Msk | OTG_STATUS_ASPERI_Msk | OTG_STATUS_IDSTS_Msk);
+
+    if (status == (OTG_STATUS_IDSTS_Msk | OTG_STATUS_ASPERI_Msk))
+        rt_kprintf("usb frame acts as peripheral\n");
+
+    else if (status == OTG_STATUS_ASHOST_Msk)
+        rt_kprintf("usb frame acts as host\n");
+
+    else
+        rt_kprintf("usb frame is unknown state: 0x%x\n", status);
+
+    return;
+}
+MSH_CMD_EXPORT_ALIAS(usb_role, usb_role, check usb role);
+
+static int otg_init(void)
+{
+    SYS_UnlockReg();
+
+    /* Set OTG as ID dependent role */
+    SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_USBROLE_Msk) | SYS_USBPHY_OTGPHYEN_Msk | SYS_USBPHY_SBO_Msk | (0x2 << SYS_USBPHY_USBROLE_Pos);
+
+    OTG_ENABLE();
+    /* Enable OTG and ID detection function */
+    OTG_ENABLE_PHY();
+    /* Enable ID detection function */
+    OTG_ENABLE_ID_DETECT();
+    /* Enable OTG interrupt */
+    NVIC_EnableIRQ(USBOTG_IRQn);
+    _usb_init_delay();
+
+    /* clear interrupt and enable relative interrupts */
+    OTG_ENABLE_INT(OTG_INTEN_IDCHGIEN_Msk | OTG_INTEN_HOSTIEN_Msk | OTG_INTEN_PDEVIEN_Msk |
+                   OTG_INTEN_BVLDCHGIEN_Msk | OTG_INTEN_AVLDCHGIEN_Msk);
+
+    SYS_LockReg();
+
+    return (int)RT_EOK;
+}
+INIT_DEVICE_EXPORT(otg_init);
+
+/* OTG interrupt entry */
+void USBOTG_IRQHandler(void)
+{
+    __IO uint32_t u32INTEN;
+
+    u32INTEN = OTG->INTEN;
+
+    /* usb id pin status change */
+    if (u32INTEN & OTG_INTSTS_IDCHGIF_Msk)
+    {
+        if (OTG_GET_STATUS(OTG_STATUS_IDSTS_Msk))
+            LOG_D("usb frame acts as peripheral\n");
+
+        OTG_CLR_INT_FLAG(OTG_INTSTS_IDCHGIF_Msk);
+        LOG_D("usb id change");
+    }
+
+    /* B-device session valid state change */
+    if (u32INTEN & OTG_INTSTS_BVLDCHGIF_Msk)
+    {
+        if (OTG_GET_STATUS(OTG_STATUS_IDSTS_Msk) == 0)
+            LOG_D("usb frame acts as host\n");
+
+        OTG_CLR_INT_FLAG(OTG_INTSTS_BVLDCHGIF_Msk);
+        LOG_D("usb b-device session valid state change");
+    }
+
+    /* Clear all interrupt flags */
+    OTG->INTSTS = u32INTEN;
+}
+
+#endif /* defined(BSP_USING_OTG) */
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_pdma.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_pdma.c
new file mode 100644
index 0000000000..6cbe151347
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_pdma.c
@@ -0,0 +1,1051 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-2-7        Wayne            First version
+*
+******************************************************************************/
+
+#include 
+
+#if defined(BSP_USING_PDMA)
+
+#include 
+#include 
+#include 
+#include 
+
+/* Private define ---------------------------------------------------------------*/
+// RT_DEV_NAME_PREFIX pdma
+
+#ifndef NU_PDMA_MEMFUN_ACTOR_MAX
+    #define NU_PDMA_MEMFUN_ACTOR_MAX (4)
+#endif
+
+#define NU_PDMA_SG_TBL_MAXSIZE         (NU_PDMA_SG_LIMITED_DISTANCE/sizeof(DSCT_T))
+
+#define NU_PDMA_CH_MAX (2*PDMA_CH_MAX)     /* Specify maximum channels of PDMA */
+#define NU_PDMA_CH_Pos (0)               /* Specify first channel number of PDMA */
+#define NU_PDMA_CH_Msk (((1 << NU_PDMA_CH_MAX) - 1) << NU_PDMA_CH_Pos)
+#define NU_PDMA_CH_HALF_Msk (((1 << PDMA_CH_MAX) - 1) << NU_PDMA_CH_Pos)
+#define NU_PDMA_GET_BASE(ch)   (PDMA_T *)((((ch)/PDMA_CH_MAX)>0)?PDMA1_BASE:PDMA0_BASE)
+#define NU_PDMA_GET_MOD_CHIDX(ch)   ((ch)%PDMA_CH_MAX)
+
+/* Private typedef --------------------------------------------------------------*/
+struct nu_pdma_periph_ctl
+{
+    uint32_t     m_u32Peripheral;
+    nu_pdma_memctrl_t  m_eMemCtl;
+};
+typedef struct nu_pdma_periph_ctl nu_pdma_periph_ctl_t;
+
+struct nu_pdma_chn
+{
+    nu_pdma_cb_handler_t   m_pfnCBHandler;
+    void                  *m_pvUserData;
+    uint32_t               m_u32EventFilter;
+    uint32_t               m_u32IdleTimeout_us;
+    nu_pdma_periph_ctl_t   m_spPeripCtl;
+};
+typedef struct nu_pdma_chn nu_pdma_chn_t;
+
+struct nu_pdma_memfun_actor
+{
+    int         m_i32ChannID;
+    uint32_t    m_u32Result;
+    rt_sem_t    m_psSemMemFun;
+} ;
+typedef struct nu_pdma_memfun_actor *nu_pdma_memfun_actor_t;
+
+/* Private functions ------------------------------------------------------------*/
+static int nu_pdma_peripheral_set(uint32_t u32PeriphType);
+static void nu_pdma_init(void);
+static void nu_pdma_channel_enable(int i32ChannID);
+static void nu_pdma_channel_disable(int i32ChannID);
+static void nu_pdma_channel_reset(int i32ChannID);
+static rt_err_t nu_pdma_timeout_set(int i32ChannID, int i32Timeout_us);
+static void nu_pdma_periph_ctrl_fill(int i32ChannID, int i32CtlPoolIdx);
+static rt_size_t nu_pdma_memfun(void *dest, void *src, uint32_t u32DataWidth, unsigned int count, nu_pdma_memctrl_t eMemCtl);
+static void nu_pdma_memfun_cb(void *pvUserData, uint32_t u32Events);
+static void nu_pdma_memfun_actor_init(void);
+static int nu_pdma_memfun_employ(void);
+static int nu_pdma_non_transfer_count_get(int32_t i32ChannID);
+
+/* Public functions -------------------------------------------------------------*/
+
+
+/* Private variables ------------------------------------------------------------*/
+static volatile int nu_pdma_inited = 0;
+static volatile uint32_t nu_pdma_chn_mask = 0;
+static nu_pdma_chn_t nu_pdma_chn_arr[NU_PDMA_CH_MAX];
+static volatile uint32_t nu_pdma_memfun_actor_mask = 0;
+static volatile uint32_t nu_pdma_memfun_actor_maxnum = 0;
+static rt_sem_t nu_pdma_memfun_actor_pool_sem = RT_NULL;
+static rt_mutex_t nu_pdma_memfun_actor_pool_lock = RT_NULL;
+
+static const nu_pdma_periph_ctl_t g_nu_pdma_peripheral_ctl_pool[ ] =
+{
+    // M2M
+    { PDMA_MEM, eMemCtl_SrcInc_DstInc },
+
+    // M2P
+    { PDMA_USB_TX,   eMemCtl_SrcInc_DstFix },
+
+    { PDMA_UART0_TX, eMemCtl_SrcInc_DstFix },
+    { PDMA_UART1_TX, eMemCtl_SrcInc_DstFix },
+    { PDMA_UART2_TX, eMemCtl_SrcInc_DstFix },
+    { PDMA_UART3_TX, eMemCtl_SrcInc_DstFix },
+    { PDMA_UART4_TX, eMemCtl_SrcInc_DstFix },
+    { PDMA_UART5_TX, eMemCtl_SrcInc_DstFix },
+
+    { PDMA_USCI0_TX, eMemCtl_SrcInc_DstFix },
+    { PDMA_USCI1_TX, eMemCtl_SrcInc_DstFix },
+
+    { PDMA_QSPI0_TX, eMemCtl_SrcInc_DstFix },
+
+    { PDMA_SPI0_TX,  eMemCtl_SrcInc_DstFix },
+    { PDMA_SPI1_TX,  eMemCtl_SrcInc_DstFix },
+    { PDMA_SPI2_TX,  eMemCtl_SrcInc_DstFix },
+    { PDMA_SPI3_TX,  eMemCtl_SrcInc_DstFix },
+
+    { PDMA_I2C0_TX,  eMemCtl_SrcInc_DstFix },
+    { PDMA_I2C1_TX,  eMemCtl_SrcInc_DstFix },
+    { PDMA_I2C2_TX,  eMemCtl_SrcInc_DstFix },
+
+    { PDMA_I2S0_TX,  eMemCtl_SrcInc_DstFix },
+
+    { PDMA_DAC0_TX,  eMemCtl_SrcInc_DstFix },
+    { PDMA_DAC1_TX,  eMemCtl_SrcInc_DstFix },
+
+    { PDMA_EPWM0_CH0_TX, eMemCtl_SrcInc_DstFix },
+    { PDMA_EPWM0_CH1_TX, eMemCtl_SrcInc_DstFix },
+    { PDMA_EPWM0_CH2_TX, eMemCtl_SrcInc_DstFix },
+    { PDMA_EPWM0_CH3_TX, eMemCtl_SrcInc_DstFix },
+    { PDMA_EPWM0_CH4_TX, eMemCtl_SrcInc_DstFix },
+    { PDMA_EPWM0_CH5_TX, eMemCtl_SrcInc_DstFix },
+    { PDMA_EPWM1_CH0_TX, eMemCtl_SrcInc_DstFix },
+    { PDMA_EPWM1_CH1_TX, eMemCtl_SrcInc_DstFix },
+    { PDMA_EPWM1_CH2_TX, eMemCtl_SrcInc_DstFix },
+    { PDMA_EPWM1_CH3_TX, eMemCtl_SrcInc_DstFix },
+    { PDMA_EPWM1_CH4_TX, eMemCtl_SrcInc_DstFix },
+    { PDMA_EPWM1_CH5_TX, eMemCtl_SrcInc_DstFix },
+
+    // P2M
+    { PDMA_USB_RX, eMemCtl_SrcFix_DstInc },
+
+    { PDMA_UART0_RX, eMemCtl_SrcFix_DstInc },
+    { PDMA_UART1_RX, eMemCtl_SrcFix_DstInc },
+    { PDMA_UART2_RX, eMemCtl_SrcFix_DstInc },
+    { PDMA_UART3_RX, eMemCtl_SrcFix_DstInc },
+    { PDMA_UART4_RX, eMemCtl_SrcFix_DstInc },
+    { PDMA_UART5_RX, eMemCtl_SrcFix_DstInc },
+
+    { PDMA_USCI0_RX, eMemCtl_SrcFix_DstInc },
+    { PDMA_USCI1_RX, eMemCtl_SrcFix_DstInc },
+
+    { PDMA_QSPI0_RX, eMemCtl_SrcFix_DstInc },
+
+    { PDMA_SPI0_RX, eMemCtl_SrcFix_DstInc },
+    { PDMA_SPI1_RX, eMemCtl_SrcFix_DstInc },
+    { PDMA_SPI2_RX, eMemCtl_SrcFix_DstInc },
+    { PDMA_SPI3_RX, eMemCtl_SrcFix_DstInc },
+
+    { PDMA_EPWM0_P1_RX, eMemCtl_SrcFix_DstInc },
+    { PDMA_EPWM0_P2_RX, eMemCtl_SrcFix_DstInc },
+    { PDMA_EPWM0_P3_RX, eMemCtl_SrcFix_DstInc },
+    { PDMA_EPWM1_P1_RX, eMemCtl_SrcFix_DstInc },
+    { PDMA_EPWM1_P2_RX, eMemCtl_SrcFix_DstInc },
+    { PDMA_EPWM1_P3_RX, eMemCtl_SrcFix_DstInc },
+
+    { PDMA_I2C0_RX, eMemCtl_SrcFix_DstInc },
+    { PDMA_I2C1_RX, eMemCtl_SrcFix_DstInc },
+    { PDMA_I2C2_RX, eMemCtl_SrcFix_DstInc },
+    { PDMA_I2S0_RX, eMemCtl_SrcFix_DstInc },
+
+    { PDMA_TMR0, eMemCtl_SrcFix_DstInc },
+    { PDMA_TMR1, eMemCtl_SrcFix_DstInc },
+    { PDMA_TMR2, eMemCtl_SrcFix_DstInc },
+    { PDMA_TMR3, eMemCtl_SrcFix_DstInc },
+
+    { PDMA_ADC_RX, eMemCtl_SrcFix_DstInc },
+};
+#define NU_PERIPHERAL_SIZE ( sizeof(g_nu_pdma_peripheral_ctl_pool) / sizeof(g_nu_pdma_peripheral_ctl_pool[0]) )
+
+static struct nu_pdma_memfun_actor nu_pdma_memfun_actor_arr[NU_PDMA_MEMFUN_ACTOR_MAX];
+
+/* SG table pool */
+static DSCT_T nu_pdma_sgtbl_arr[NU_PDMA_SGTBL_POOL_SIZE] = { 0 };
+static uint32_t nu_pdma_sgtbl_token[RT_ALIGN(NU_PDMA_SGTBL_POOL_SIZE, 32) / 32];
+static rt_mutex_t g_mutex_sg = RT_NULL;
+
+static int nu_pdma_peripheral_set(uint32_t u32PeriphType)
+{
+    int idx = 0;
+
+    while (idx < NU_PERIPHERAL_SIZE)
+    {
+        if (g_nu_pdma_peripheral_ctl_pool[idx].m_u32Peripheral == u32PeriphType)
+            return idx;
+        idx++;
+    }
+
+    // Not such peripheral
+    return -1;
+}
+
+static void nu_pdma_periph_ctrl_fill(int i32ChannID, int i32CtlPoolIdx)
+{
+    nu_pdma_chn_t *psPdmaChann = &nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos];
+    psPdmaChann->m_spPeripCtl.m_u32Peripheral = g_nu_pdma_peripheral_ctl_pool[i32CtlPoolIdx].m_u32Peripheral;
+    psPdmaChann->m_spPeripCtl.m_eMemCtl = g_nu_pdma_peripheral_ctl_pool[i32CtlPoolIdx].m_eMemCtl;
+}
+
+static void nu_pdma_init(void)
+{
+    int latest = 0;
+    if (nu_pdma_inited)
+        return;
+
+    g_mutex_sg = rt_mutex_create("sgtbles", RT_IPC_FLAG_FIFO);
+    RT_ASSERT(g_mutex_sg != RT_NULL);
+
+    nu_pdma_chn_mask = ~(NU_PDMA_CH_Msk);
+    rt_memset(nu_pdma_chn_arr, 0x00, sizeof(nu_pdma_chn_t));
+
+    /* Initialize PDMA0 setting */
+    PDMA_Open(PDMA0, NU_PDMA_CH_HALF_Msk);
+    PDMA_Close(PDMA0);
+    NVIC_EnableIRQ(PDMA0_IRQn);
+
+    /* Initialize PDMA1 setting */
+    PDMA_Open(PDMA1, NU_PDMA_CH_HALF_Msk);
+    PDMA_Close(PDMA1);
+    NVIC_EnableIRQ(PDMA1_IRQn);
+
+    rt_memset(&nu_pdma_sgtbl_arr[0], 0x00, sizeof(nu_pdma_sgtbl_arr));
+
+    /* Assign first SG table address as PDMA SG table base address */
+    PDMA0->SCATBA = (uint32_t)&nu_pdma_sgtbl_arr[0];
+    PDMA1->SCATBA = (uint32_t)&nu_pdma_sgtbl_arr[0];
+
+    /* Initialize token pool. */
+    rt_memset(&nu_pdma_sgtbl_token[0], 0xff, sizeof(nu_pdma_sgtbl_token));
+    latest = NU_PDMA_SGTBL_POOL_SIZE / 32;
+    nu_pdma_sgtbl_token[latest] ^= ~((1 << (NU_PDMA_SGTBL_POOL_SIZE % 32)) - 1) ;
+
+    nu_pdma_inited = 1;
+}
+
+static void nu_pdma_channel_enable(int i32ChannID)
+{
+    PDMA_T *PDMA = NU_PDMA_GET_BASE(i32ChannID);
+    PDMA_Open(PDMA, 1 << NU_PDMA_GET_MOD_CHIDX(i32ChannID));
+}
+
+static inline void nu_pdma_channel_disable(int i32ChannID)
+{
+    PDMA_T *PDMA = NU_PDMA_GET_BASE(i32ChannID);
+    PDMA->CHCTL &= ~(1 << NU_PDMA_GET_MOD_CHIDX(i32ChannID));
+}
+
+static inline void nu_pdma_channel_reset(int i32ChannID)
+{
+    PDMA_T *PDMA = NU_PDMA_GET_BASE(i32ChannID);
+    PDMA->CHRST = (1 << NU_PDMA_GET_MOD_CHIDX(i32ChannID));
+}
+
+void nu_pdma_channel_terminate(int i32ChannID)
+{
+    PDMA_T *PDMA;
+
+    if (!(nu_pdma_chn_mask & (1 << i32ChannID)))
+        goto exit_pdma_channel_terminate;
+
+    PDMA = NU_PDMA_GET_BASE(i32ChannID);
+
+    // Reset specified channel ID
+    nu_pdma_channel_reset(i32ChannID);
+
+    // Clean descriptor table control register.
+    PDMA->DSCT[NU_PDMA_GET_MOD_CHIDX(i32ChannID)].CTL = 0UL;
+
+    PDMA->CHCTL |= (1 << NU_PDMA_GET_MOD_CHIDX(i32ChannID));
+
+exit_pdma_channel_terminate:
+
+    return;
+}
+
+static rt_err_t nu_pdma_timeout_set(int i32ChannID, int i32Timeout_us)
+{
+    rt_err_t ret = RT_EINVAL;
+    PDMA_T *PDMA = NULL;
+
+    if (!(nu_pdma_chn_mask & (1 << i32ChannID)))
+        goto exit_nu_pdma_timeout_set;
+
+    PDMA = NU_PDMA_GET_BASE(i32ChannID);
+
+    nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_u32IdleTimeout_us = i32Timeout_us;
+
+    if (i32Timeout_us && NU_PDMA_GET_MOD_CHIDX(i32ChannID) <= 1)   // Limit
+    {
+        uint32_t u32ToClk_Max = 1000000 / (CLK_GetHCLKFreq() / (1 << 8));
+        uint32_t u32Divider     = (i32Timeout_us / u32ToClk_Max) / (1 << 16);
+        uint32_t u32TOutCnt     = (i32Timeout_us / u32ToClk_Max) % (1 << 16);
+
+        PDMA_DisableTimeout(PDMA,  1 << NU_PDMA_GET_MOD_CHIDX(i32ChannID));
+        PDMA_EnableInt(PDMA, NU_PDMA_GET_MOD_CHIDX(i32ChannID), PDMA_INT_TIMEOUT);    // Interrupt type
+
+        if (u32Divider > 7)
+        {
+            u32Divider = 7;
+            u32TOutCnt = (1 << 16);
+        }
+        PDMA->TOUTPSC |= (u32Divider << (PDMA_TOUTPSC_TOUTPSC1_Pos * NU_PDMA_GET_MOD_CHIDX(i32ChannID)));
+        PDMA_SetTimeOut(PDMA,  NU_PDMA_GET_MOD_CHIDX(i32ChannID), 1, u32TOutCnt);
+
+        ret = RT_EOK;
+    }
+    else
+    {
+        PDMA_DisableInt(PDMA, NU_PDMA_GET_MOD_CHIDX(i32ChannID), PDMA_INT_TIMEOUT);    // Interrupt type
+        PDMA_DisableTimeout(PDMA,  1 << NU_PDMA_GET_MOD_CHIDX(i32ChannID));
+    }
+
+exit_nu_pdma_timeout_set:
+
+    return -(ret);
+}
+
+int nu_pdma_channel_allocate(int32_t i32PeripType)
+{
+    int i, i32PeripCtlIdx;
+
+    nu_pdma_init();
+
+    if ((i32PeripCtlIdx = nu_pdma_peripheral_set(i32PeripType)) < 0)
+        goto exit_nu_pdma_channel_allocate;
+
+    /* Find the position of first '0' in nu_pdma_chn_mask. */
+    i = nu_cto(nu_pdma_chn_mask);
+    if (i != 32)
+    {
+        nu_pdma_chn_mask |= (1 << i);
+        rt_memset(nu_pdma_chn_arr + i - NU_PDMA_CH_Pos, 0x00, sizeof(nu_pdma_chn_t));
+
+        /* Set idx number of g_nu_pdma_peripheral_ctl_pool */
+        nu_pdma_periph_ctrl_fill(i, i32PeripCtlIdx);
+
+        /* Reset channel */
+        nu_pdma_channel_reset(i);
+
+        nu_pdma_channel_enable(i);
+
+        return i;
+    }
+
+exit_nu_pdma_channel_allocate:
+    // No channel available
+    return -(RT_ERROR);
+}
+
+rt_err_t nu_pdma_channel_free(int i32ChannID)
+{
+    rt_err_t ret = RT_EINVAL;
+
+    if (! nu_pdma_inited)
+        goto exit_nu_pdma_channel_free;
+
+    if (i32ChannID < NU_PDMA_CH_MAX && i32ChannID >= NU_PDMA_CH_Pos)
+    {
+        nu_pdma_chn_mask &= ~(1 << i32ChannID);
+        nu_pdma_channel_disable(i32ChannID);
+        ret =  RT_EOK;
+    }
+exit_nu_pdma_channel_free:
+
+    return -(ret);
+}
+
+rt_err_t nu_pdma_callback_register(int i32ChannID, nu_pdma_cb_handler_t pfnHandler, void *pvUserData, uint32_t u32EventFilter)
+{
+    rt_err_t ret = RT_EINVAL;
+
+    if (!(nu_pdma_chn_mask & (1 << i32ChannID)))
+        goto exit_nu_pdma_callback_register;
+
+    nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_pfnCBHandler = pfnHandler;
+    nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_pvUserData = pvUserData;
+    nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_u32EventFilter = u32EventFilter;
+
+    ret = RT_EOK;
+
+exit_nu_pdma_callback_register:
+
+    return -(ret) ;
+}
+
+nu_pdma_cb_handler_t nu_pdma_callback_hijack(int i32ChannID, nu_pdma_cb_handler_t *ppfnHandler_Hijack,
+        void **ppvUserData_Hijack, uint32_t *pu32Events_Hijack)
+{
+    nu_pdma_cb_handler_t pfnHandler_Org = NULL;
+    void    *pvUserData_Org;
+    uint32_t u32Events_Org;
+
+    RT_ASSERT(ppfnHandler_Hijack != NULL);
+    RT_ASSERT(ppvUserData_Hijack != NULL);
+    RT_ASSERT(pu32Events_Hijack != NULL);
+
+    if (!(nu_pdma_chn_mask & (1 << i32ChannID)))
+        goto exit_nu_pdma_callback_hijack;
+
+    pfnHandler_Org = nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_pfnCBHandler;
+    pvUserData_Org = nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_pvUserData;
+    u32Events_Org  = nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_u32EventFilter;
+
+    nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_pfnCBHandler = *ppfnHandler_Hijack;
+    nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_pvUserData = *ppvUserData_Hijack;
+    nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_u32EventFilter = *pu32Events_Hijack;
+
+    *ppfnHandler_Hijack = pfnHandler_Org;
+    *ppvUserData_Hijack = pvUserData_Org;
+    *pu32Events_Hijack  = u32Events_Org;
+
+exit_nu_pdma_callback_hijack:
+
+    return pfnHandler_Org;
+}
+
+static int nu_pdma_non_transfer_count_get(int32_t i32ChannID)
+{
+    PDMA_T *PDMA = NU_PDMA_GET_BASE(i32ChannID);
+    return ((PDMA->DSCT[NU_PDMA_GET_MOD_CHIDX(i32ChannID)].CTL & PDMA_DSCT_CTL_TXCNT_Msk) >> PDMA_DSCT_CTL_TXCNT_Pos) + 1;
+}
+
+int nu_pdma_transferred_byte_get(int32_t i32ChannID, int32_t i32TriggerByteLen)
+{
+    int i32BitWidth = 0;
+    int cur_txcnt = 0;
+    PDMA_T *PDMA;
+
+    if (!(nu_pdma_chn_mask & (1 << i32ChannID)))
+        goto exit_nu_pdma_transferred_byte_get;
+
+    PDMA = NU_PDMA_GET_BASE(i32ChannID);
+
+    i32BitWidth = PDMA->DSCT[NU_PDMA_GET_MOD_CHIDX(i32ChannID)].CTL & PDMA_DSCT_CTL_TXWIDTH_Msk;
+    i32BitWidth = (i32BitWidth == PDMA_WIDTH_8) ? 1 : (i32BitWidth == PDMA_WIDTH_16) ? 2 : (i32BitWidth == PDMA_WIDTH_32) ? 4 : 0;
+
+    cur_txcnt = nu_pdma_non_transfer_count_get(i32ChannID);
+
+    return (i32TriggerByteLen - (cur_txcnt) * i32BitWidth);
+
+exit_nu_pdma_transferred_byte_get:
+
+    return -1;
+}
+
+nu_pdma_memctrl_t nu_pdma_channel_memctrl_get(int i32ChannID)
+{
+    nu_pdma_memctrl_t eMemCtrl = eMemCtl_Undefined;
+
+    if (!(nu_pdma_chn_mask & (1 << i32ChannID)))
+        goto exit_nu_pdma_channel_memctrl_get;
+
+    eMemCtrl = nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_spPeripCtl.m_eMemCtl;
+
+exit_nu_pdma_channel_memctrl_get:
+
+    return eMemCtrl;
+}
+
+rt_err_t nu_pdma_channel_memctrl_set(int i32ChannID, nu_pdma_memctrl_t eMemCtrl)
+{
+    rt_err_t ret = RT_EINVAL;
+    nu_pdma_chn_t *psPdmaChann = &nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos];
+
+
+    if (!(nu_pdma_chn_mask & (1 << i32ChannID)))
+        goto exit_nu_pdma_channel_memctrl_set;
+    else if ((eMemCtrl < eMemCtl_SrcFix_DstFix) || (eMemCtrl > eMemCtl_SrcInc_DstInc))
+        goto exit_nu_pdma_channel_memctrl_set;
+
+    /* PDMA_MEM/SAR_FIX/BURST mode is not supported. */
+    if ((psPdmaChann->m_spPeripCtl.m_u32Peripheral == PDMA_MEM) &&
+            ((eMemCtrl == eMemCtl_SrcFix_DstInc) || (eMemCtrl == eMemCtl_SrcFix_DstFix)))
+        goto exit_nu_pdma_channel_memctrl_set;
+
+    nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_spPeripCtl.m_eMemCtl = eMemCtrl;
+
+    ret = RT_EOK;
+
+exit_nu_pdma_channel_memctrl_set:
+
+    return -(ret);
+}
+
+static void nu_pdma_channel_memctrl_fill(nu_pdma_memctrl_t eMemCtl, uint32_t *pu32SrcCtl, uint32_t *pu32DstCtl)
+{
+    switch ((int)eMemCtl)
+    {
+    case eMemCtl_SrcFix_DstFix:
+        *pu32SrcCtl = PDMA_SAR_FIX;
+        *pu32DstCtl = PDMA_DAR_FIX;
+        break;
+    case eMemCtl_SrcFix_DstInc:
+        *pu32SrcCtl = PDMA_SAR_FIX;
+        *pu32DstCtl = PDMA_DAR_INC;
+        break;
+    case eMemCtl_SrcInc_DstFix:
+        *pu32SrcCtl = PDMA_SAR_INC;
+        *pu32DstCtl = PDMA_DAR_FIX;
+        break;
+    case eMemCtl_SrcInc_DstInc:
+        *pu32SrcCtl = PDMA_SAR_INC;
+        *pu32DstCtl = PDMA_DAR_INC;
+        break;
+    default:
+        break;
+    }
+}
+
+/* This is for Scatter-gather DMA. */
+rt_err_t nu_pdma_desc_setup(int i32ChannID, nu_pdma_desc_t dma_desc, uint32_t u32DataWidth, uint32_t u32AddrSrc,
+                            uint32_t u32AddrDst, int32_t i32TransferCnt, nu_pdma_desc_t next)
+{
+    nu_pdma_periph_ctl_t *psPeriphCtl = NULL;
+    PDMA_T *PDMA = NULL;
+
+    uint32_t u32SrcCtl = 0;
+    uint32_t u32DstCtl = 0;
+
+    rt_err_t ret = RT_EINVAL;
+
+    if (!dma_desc)
+        goto exit_nu_pdma_desc_setup;
+    else if (!(nu_pdma_chn_mask & (1 << i32ChannID)))
+        goto exit_nu_pdma_desc_setup;
+    else if (!(u32DataWidth == 8 || u32DataWidth == 16 || u32DataWidth == 32))
+        goto exit_nu_pdma_desc_setup;
+    else if ((u32AddrSrc % (u32DataWidth / 8)) || (u32AddrDst % (u32DataWidth / 8)))
+        goto exit_nu_pdma_desc_setup;
+    else if ( i32TransferCnt > NU_PDMA_MAX_TXCNT )
+        goto exit_nu_pdma_desc_setup;
+
+    PDMA = NU_PDMA_GET_BASE(i32ChannID);
+
+    psPeriphCtl = &nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_spPeripCtl;
+
+    nu_pdma_channel_memctrl_fill(psPeriphCtl->m_eMemCtl, &u32SrcCtl, &u32DstCtl);
+
+    dma_desc->CTL = ((i32TransferCnt - 1) << PDMA_DSCT_CTL_TXCNT_Pos) |
+                    ((u32DataWidth == 8) ? PDMA_WIDTH_8 : (u32DataWidth == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32) |
+                    u32SrcCtl |
+                    u32DstCtl |
+                    PDMA_OP_BASIC;
+
+    dma_desc->SA = u32AddrSrc;
+    dma_desc->DA = u32AddrDst;
+    dma_desc->NEXT = 0;  /* Terminating node by default. */
+
+    if (psPeriphCtl->m_u32Peripheral == PDMA_MEM)
+    {
+        /* For M2M transfer */
+        dma_desc->CTL |= (PDMA_REQ_BURST | PDMA_BURST_32);
+    }
+    else
+    {
+        /* For P2M and M2P transfer */
+        dma_desc->CTL |= (PDMA_REQ_SINGLE);
+    }
+
+    if (next)
+    {
+        /* Link to Next and modify to scatter-gather DMA mode. */
+        dma_desc->CTL = (dma_desc->CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER;
+        dma_desc->NEXT = (uint32_t)next - (PDMA->SCATBA);
+    }
+
+    ret = RT_EOK;
+
+exit_nu_pdma_desc_setup:
+
+    return -(ret);
+}
+
+static int nu_pdma_sgtbls_token_allocate(void)
+{
+    int idx, i;
+
+    int pool_size = sizeof(nu_pdma_sgtbl_token) / sizeof(uint32_t);
+
+    for (i = 0; i < pool_size; i++)
+    {
+        if ((idx = nu_ctz(nu_pdma_sgtbl_token[i])) != 32)
+        {
+            nu_pdma_sgtbl_token[i] &= ~(1 << idx);
+            idx += i * 32;
+            return idx;
+        }
+    }
+
+    /* No available */
+    return -1;
+}
+
+static void nu_pdma_sgtbls_token_free(nu_pdma_desc_t psSgtbls)
+{
+    int idx = (int)(psSgtbls - &nu_pdma_sgtbl_arr[0]);
+    RT_ASSERT(idx >= 0);
+    RT_ASSERT((idx + 1) <= NU_PDMA_SGTBL_POOL_SIZE);
+    nu_pdma_sgtbl_token[idx / 32] |= (1 << (idx % 32));
+}
+
+rt_err_t nu_pdma_sgtbls_allocate(nu_pdma_desc_t *ppsSgtbls, int num)
+{
+    int i, j, idx;
+
+    RT_ASSERT(ppsSgtbls != NULL);
+    RT_ASSERT(num <= NU_PDMA_SG_TBL_MAXSIZE);
+
+    rt_mutex_take(g_mutex_sg, RT_WAITING_FOREVER);
+
+    for (i = 0; i < num; i++)
+    {
+        ppsSgtbls[i] = NULL;
+        /* Get token. */
+        if ((idx = nu_pdma_sgtbls_token_allocate()) < 0)
+        {
+            rt_kprintf("No available sgtbl.\n");
+            goto fail_nu_pdma_sgtbls_allocate;
+        }
+
+        ppsSgtbls[i] = (nu_pdma_desc_t)&nu_pdma_sgtbl_arr[idx];
+    }
+
+    rt_mutex_release(g_mutex_sg);
+
+    return RT_EOK;
+
+fail_nu_pdma_sgtbls_allocate:
+
+    /* Release allocated tables. */
+    for (j = 0; j < i; j++)
+    {
+        if (ppsSgtbls[j] != NULL)
+        {
+            nu_pdma_sgtbls_token_free(ppsSgtbls[j]);
+        }
+        ppsSgtbls[j] = NULL;
+    }
+
+    rt_mutex_release(g_mutex_sg);
+    return -RT_ERROR;
+}
+
+void nu_pdma_sgtbls_free(nu_pdma_desc_t *ppsSgtbls, int num)
+{
+    int i;
+
+    RT_ASSERT(ppsSgtbls != NULL);
+    RT_ASSERT(num <= NU_PDMA_SG_TBL_MAXSIZE);
+
+    rt_mutex_take(g_mutex_sg, RT_WAITING_FOREVER);
+
+    for (i = 0; i < num; i++)
+    {
+        if (ppsSgtbls[i] != NULL)
+        {
+            nu_pdma_sgtbls_token_free(ppsSgtbls[i]);
+        }
+        ppsSgtbls[i] = NULL;
+    }
+
+    rt_mutex_release(g_mutex_sg);
+}
+
+static rt_err_t nu_pdma_sgtbls_valid(nu_pdma_desc_t head)
+{
+    uint32_t node_addr;
+    nu_pdma_desc_t node = head;
+
+    do
+    {
+        node_addr = (uint32_t)node;
+        if ((node_addr < PDMA0->SCATBA) || (node_addr - PDMA0->SCATBA) >= NU_PDMA_SG_LIMITED_DISTANCE)
+        {
+            rt_kprintf("The distance is over %d between 0x%08x and 0x%08x. \n", NU_PDMA_SG_LIMITED_DISTANCE, PDMA0->SCATBA, node);
+            rt_kprintf("Please use nu_pdma_sgtbl_allocate to allocate valid sg-table.\n");
+            return RT_ERROR;
+        }
+
+        node = (nu_pdma_desc_t)(node->NEXT + PDMA0->SCATBA);
+
+    }
+    while (((uint32_t)node != PDMA0->SCATBA) && (node != head));
+
+    return RT_EOK;
+}
+
+static void _nu_pdma_transfer(int i32ChannID, uint32_t u32Peripheral, nu_pdma_desc_t head, uint32_t u32IdleTimeout_us)
+{
+    PDMA_T *PDMA = NU_PDMA_GET_BASE(i32ChannID);
+
+    PDMA_DisableTimeout(PDMA,  1 << NU_PDMA_GET_MOD_CHIDX(i32ChannID));
+
+    PDMA_EnableInt(PDMA, NU_PDMA_GET_MOD_CHIDX(i32ChannID), PDMA_INT_TRANS_DONE);
+
+    nu_pdma_timeout_set(i32ChannID, u32IdleTimeout_us);
+
+    /* Set scatter-gather mode and head */
+    PDMA_SetTransferMode(PDMA,
+                         NU_PDMA_GET_MOD_CHIDX(i32ChannID),
+                         u32Peripheral,
+                         (head->NEXT != 0) ? 1 : 0,
+                         (uint32_t)head);
+
+    /* If peripheral is M2M, trigger it. */
+    if (u32Peripheral == PDMA_MEM)
+        PDMA_Trigger(PDMA, NU_PDMA_GET_MOD_CHIDX(i32ChannID));
+}
+
+rt_err_t nu_pdma_transfer(int i32ChannID, uint32_t u32DataWidth, uint32_t u32AddrSrc, uint32_t u32AddrDst, int32_t i32TransferCnt, uint32_t u32IdleTimeout_us)
+{
+    rt_err_t ret = RT_EINVAL;
+
+    PDMA_T *PDMA = NU_PDMA_GET_BASE(i32ChannID);
+
+    nu_pdma_periph_ctl_t *psPeriphCtl = NULL;
+
+    if (!(nu_pdma_chn_mask & (1 << i32ChannID)))
+        goto exit_nu_pdma_transfer;
+
+    psPeriphCtl = &nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_spPeripCtl;
+
+    ret = nu_pdma_desc_setup(i32ChannID,
+                             &PDMA->DSCT[NU_PDMA_GET_MOD_CHIDX(i32ChannID)],
+                             u32DataWidth,
+                             u32AddrSrc,
+                             u32AddrDst,
+                             i32TransferCnt,
+                             NULL);
+    if (ret != RT_EOK)
+        goto exit_nu_pdma_transfer;
+
+    _nu_pdma_transfer(i32ChannID, psPeriphCtl->m_u32Peripheral, &PDMA->DSCT[NU_PDMA_GET_MOD_CHIDX(i32ChannID)], u32IdleTimeout_us);
+
+    ret = RT_EOK;
+
+exit_nu_pdma_transfer:
+
+    return -(ret);
+}
+
+rt_err_t nu_pdma_sg_transfer(int i32ChannID, nu_pdma_desc_t head, uint32_t u32IdleTimeout_us)
+{
+    rt_err_t ret = RT_EINVAL;
+    nu_pdma_periph_ctl_t *psPeriphCtl = NULL;
+
+    if (!head)
+        goto exit_nu_pdma_sg_transfer;
+    else if (!(nu_pdma_chn_mask & (1 << i32ChannID)))
+        goto exit_nu_pdma_sg_transfer;
+    else if ((ret = nu_pdma_sgtbls_valid(head)) != RT_EOK) /* Check SG-tbls. */
+        goto exit_nu_pdma_sg_transfer;
+
+    psPeriphCtl = &nu_pdma_chn_arr[i32ChannID - NU_PDMA_CH_Pos].m_spPeripCtl;
+
+    _nu_pdma_transfer(i32ChannID, psPeriphCtl->m_u32Peripheral, head, u32IdleTimeout_us);
+
+    ret = RT_EOK;
+
+exit_nu_pdma_sg_transfer:
+
+    return -(ret);
+}
+
+void PDMA_IRQHandler(PDMA_T *PDMA)
+{
+    int i;
+
+    uint32_t intsts = PDMA_GET_INT_STATUS(PDMA);
+    uint32_t abtsts = PDMA_GET_ABORT_STS(PDMA);
+    uint32_t tdsts  = PDMA_GET_TD_STS(PDMA);
+    uint32_t reqto  = intsts & (PDMA_INTSTS_REQTOF0_Msk | PDMA_INTSTS_REQTOF1_Msk);
+    uint32_t reqto_ch = ((reqto & PDMA_INTSTS_REQTOF0_Msk) ? (1 << 0) : 0x0) | ((reqto & PDMA_INTSTS_REQTOF1_Msk) ? (1 << 1) : 0x0);
+
+    int allch_sts = (reqto_ch | tdsts | abtsts);
+
+    // Abort
+    if (intsts & PDMA_INTSTS_ABTIF_Msk)
+    {
+        // Clear all Abort flags
+        PDMA_CLR_ABORT_FLAG(PDMA, abtsts);
+    }
+
+    // Transfer done
+    if (intsts & PDMA_INTSTS_TDIF_Msk)
+    {
+        // Clear all transfer done flags
+        PDMA_CLR_TD_FLAG(PDMA, tdsts);
+    }
+
+    // Timeout
+    if (reqto)
+    {
+        // Clear all Timeout flags
+        PDMA->INTSTS = reqto;
+    }
+
+    // Find the position of first '1' in allch_sts.
+    while ((i = nu_ctz(allch_sts)) != 32)
+    {
+        int j = i;
+        int ch_mask = (1 << i);
+
+        if (PDMA == PDMA1)
+        {
+            j += PDMA_CH_MAX;
+        }
+
+        if (nu_pdma_chn_mask & (1 << j))
+        {
+            int ch_event = 0;
+            nu_pdma_chn_t *dma_chn = nu_pdma_chn_arr + j - NU_PDMA_CH_Pos;
+
+            if (dma_chn->m_pfnCBHandler)
+            {
+                if (abtsts   & ch_mask)
+                {
+                    ch_event |= NU_PDMA_EVENT_ABORT;
+                }
+
+                if (tdsts    & ch_mask) ch_event |= NU_PDMA_EVENT_TRANSFER_DONE;
+
+                if (reqto_ch & ch_mask)
+                {
+                    PDMA_DisableTimeout(PDMA,  ch_mask);
+                    ch_event |= NU_PDMA_EVENT_TIMEOUT;
+                }
+
+                if (dma_chn->m_u32EventFilter & ch_event)
+                    dma_chn->m_pfnCBHandler(dma_chn->m_pvUserData, ch_event);
+
+                if (reqto_ch & ch_mask)
+                    nu_pdma_timeout_set(j, nu_pdma_chn_arr[j - NU_PDMA_CH_Pos].m_u32IdleTimeout_us);
+
+            }//if(dma_chn->handler)
+
+        } //if (nu_pdma_chn_mask & ch_mask)
+
+        // Clear the served bit.
+        allch_sts &= ~ch_mask;
+
+    } //while
+}
+
+void PDMA0_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    PDMA_IRQHandler(PDMA0);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+void PDMA1_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    PDMA_IRQHandler(PDMA1);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+static void nu_pdma_memfun_actor_init(void)
+{
+    int i = 0 ;
+    nu_pdma_init();
+    for (i = 0; i < NU_PDMA_MEMFUN_ACTOR_MAX; i++)
+    {
+        rt_memset(&nu_pdma_memfun_actor_arr[i], 0, sizeof(struct nu_pdma_memfun_actor));
+        if (-(RT_ERROR) != (nu_pdma_memfun_actor_arr[i].m_i32ChannID = nu_pdma_channel_allocate(PDMA_MEM)))
+        {
+            nu_pdma_memfun_actor_arr[i].m_psSemMemFun = rt_sem_create("memactor_sem", 0, RT_IPC_FLAG_FIFO);
+        }
+        else
+            break;
+    }
+    if (i)
+    {
+        nu_pdma_memfun_actor_maxnum = i;
+        nu_pdma_memfun_actor_mask = ~(((1 << i) - 1));
+        nu_pdma_memfun_actor_pool_sem = rt_sem_create("mempool_sem", nu_pdma_memfun_actor_maxnum, RT_IPC_FLAG_FIFO);
+        nu_pdma_memfun_actor_pool_lock = rt_mutex_create("mempool_lock", RT_IPC_FLAG_FIFO);
+    }
+}
+
+static void nu_pdma_memfun_cb(void *pvUserData, uint32_t u32Events)
+{
+    nu_pdma_memfun_actor_t psMemFunActor = (nu_pdma_memfun_actor_t)pvUserData;
+    psMemFunActor->m_u32Result = u32Events;
+    rt_sem_release(psMemFunActor->m_psSemMemFun);
+}
+
+static int nu_pdma_memfun_employ(void)
+{
+    int idx = -1 ;
+
+    /* Headhunter */
+    if (nu_pdma_memfun_actor_pool_sem && (rt_sem_take(nu_pdma_memfun_actor_pool_sem, RT_WAITING_FOREVER) == RT_EOK))
+    {
+        rt_mutex_take(nu_pdma_memfun_actor_pool_lock, RT_WAITING_FOREVER);
+        /* Find the position of first '0' in nu_pdma_memfun_actor_mask. */
+        idx = nu_cto(nu_pdma_memfun_actor_mask);
+        if (idx != 32)
+        {
+            nu_pdma_memfun_actor_mask |= (1 << idx);
+        }
+        else
+        {
+            idx = -1;
+        }
+        rt_mutex_release(nu_pdma_memfun_actor_pool_lock);
+    }
+
+    return idx;
+}
+
+static rt_size_t nu_pdma_memfun(void *dest, void *src, uint32_t u32DataWidth, unsigned int u32TransferCnt, nu_pdma_memctrl_t eMemCtl)
+{
+    nu_pdma_memfun_actor_t psMemFunActor = NULL;
+    int idx;
+    rt_size_t ret = 0;
+    rt_uint32_t u32Offset = 0;
+    rt_uint32_t u32TxCnt = 0;
+
+    while (1)
+    {
+        /* Employ actor */
+        if ((idx = nu_pdma_memfun_employ()) < 0)
+            continue;
+
+        psMemFunActor = &nu_pdma_memfun_actor_arr[idx];
+
+        do
+        {
+
+            u32TxCnt = (u32TransferCnt > NU_PDMA_MAX_TXCNT) ? NU_PDMA_MAX_TXCNT : u32TransferCnt;
+
+            /* Set PDMA memory control to eMemCtl. */
+            nu_pdma_channel_memctrl_set(psMemFunActor->m_i32ChannID, eMemCtl);
+
+            /* Register ISR callback function */
+            nu_pdma_callback_register(psMemFunActor->m_i32ChannID, nu_pdma_memfun_cb, (void *)psMemFunActor, NU_PDMA_EVENT_ABORT | NU_PDMA_EVENT_TRANSFER_DONE);
+
+            psMemFunActor->m_u32Result = 0;
+
+            /* Trigger it */
+            nu_pdma_transfer(psMemFunActor->m_i32ChannID,
+                             u32DataWidth,
+                             (eMemCtl & 0x2ul) ? (uint32_t)src + u32Offset : (uint32_t)src, /* Src address is Inc or not. */
+                             (eMemCtl & 0x1ul) ? (uint32_t)dest + u32Offset : (uint32_t)dest, /* Dst address is Inc or not. */
+                             u32TxCnt,
+                             0);
+
+            /* Wait it done. */
+            rt_sem_take(psMemFunActor->m_psSemMemFun, RT_WAITING_FOREVER);
+
+            /* Give result if get NU_PDMA_EVENT_TRANSFER_DONE.*/
+            if (psMemFunActor->m_u32Result & NU_PDMA_EVENT_TRANSFER_DONE)
+            {
+                ret +=  u32TxCnt;
+            }
+            else
+            {
+                ret += (u32TxCnt - nu_pdma_non_transfer_count_get(psMemFunActor->m_i32ChannID));
+            }
+
+            /* Terminate it if get ABORT event */
+            if (psMemFunActor->m_u32Result & NU_PDMA_EVENT_ABORT)
+            {
+                nu_pdma_channel_terminate(psMemFunActor->m_i32ChannID);
+                break;
+            }
+
+            u32TransferCnt -= u32TxCnt;
+            u32Offset += u32TxCnt;
+        }
+        while (u32TransferCnt > 0);
+
+        rt_mutex_take(nu_pdma_memfun_actor_pool_lock, RT_WAITING_FOREVER);
+        nu_pdma_memfun_actor_mask &= ~(1 << idx);
+        rt_mutex_release(nu_pdma_memfun_actor_pool_lock);
+
+        /* Fire actor */
+        rt_sem_release(nu_pdma_memfun_actor_pool_sem);
+
+        break;
+    }
+
+    return ret;
+}
+
+rt_size_t nu_pdma_mempush(void *dest, void *src, uint32_t data_width, unsigned int transfer_count)
+{
+    if (data_width == 8 || data_width == 16 || data_width == 32)
+        return nu_pdma_memfun(dest, src, data_width, transfer_count, eMemCtl_SrcInc_DstFix);
+    return 0;
+}
+
+void *nu_pdma_memcpy(void *dest, void *src, unsigned int count)
+{
+    int i = 0;
+    uint32_t u32Offset = 0;
+    uint32_t u32Remaining = count;
+
+    for (i = 4; (i > 0) && (u32Remaining > 0) ; i >>= 1)
+    {
+        uint32_t u32src   = (uint32_t)src + u32Offset;
+        uint32_t u32dest  = (uint32_t)dest + u32Offset;
+
+        if (((u32src % i) == (u32dest % i)) &&
+                ((u32src % i) == 0) &&
+                (RT_ALIGN_DOWN(u32Remaining, i) >= i))
+        {
+            uint32_t u32TXCnt = u32Remaining / i;
+            if (u32TXCnt != nu_pdma_memfun((void *)u32dest, (void *)u32src, i * 8, u32TXCnt, eMemCtl_SrcInc_DstInc))
+                goto exit_nu_pdma_memcpy;
+
+            u32Offset += (u32TXCnt * i);
+            u32Remaining -= (u32TXCnt * i);
+        }
+    }
+
+    if (count == u32Offset)
+        return dest;
+
+exit_nu_pdma_memcpy:
+
+    return NULL;
+}
+
+/**
+ * PDMA memfun actor initialization
+ */
+int rt_hw_pdma_memfun_init(void)
+{
+    nu_pdma_memfun_actor_init();
+    return 0;
+}
+INIT_DEVICE_EXPORT(rt_hw_pdma_memfun_init);
+#endif // #if defined(BSP_USING_PDMA)
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_pdma.h b/bsp/nuvoton/libraries/m2354/rtt_port/drv_pdma.h
new file mode 100644
index 0000000000..954582f943
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_pdma.h
@@ -0,0 +1,71 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-2-7        Wayne            First version
+*
+******************************************************************************/
+
+#ifndef __DRV_PDMA_H__
+#define __DRV_PDMA_H__
+
+#include 
+#include 
+#include "NuMicro.h"
+
+#ifndef NU_PDMA_SGTBL_POOL_SIZE
+    #define NU_PDMA_SGTBL_POOL_SIZE (16)
+#endif
+
+#define NU_PDMA_CAP_NONE    (0 << 0)
+
+#define NU_PDMA_EVENT_ABORT             (1 << 0)
+#define NU_PDMA_EVENT_TRANSFER_DONE     (1 << 1)
+#define NU_PDMA_EVENT_TIMEOUT           (1 << 2)
+#define NU_PDMA_EVENT_ALL               (NU_PDMA_EVENT_ABORT | NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT)
+#define NU_PDMA_EVENT_MASK              NU_PDMA_EVENT_ALL
+#define NU_PDMA_UNUSED                  (-1)
+
+#define NU_PDMA_SG_LIMITED_DISTANCE     ((PDMA_DSCT_NEXT_NEXT_Msk>>PDMA_DSCT_NEXT_NEXT_Pos)+1)
+#define NU_PDMA_MAX_TXCNT               ((PDMA_DSCT_CTL_TXCNT_Msk>>PDMA_DSCT_CTL_TXCNT_Pos) + 1)
+
+typedef enum
+{
+    eMemCtl_SrcFix_DstFix,
+    eMemCtl_SrcFix_DstInc,
+    eMemCtl_SrcInc_DstFix,
+    eMemCtl_SrcInc_DstInc,
+    eMemCtl_Undefined = (-1)
+} nu_pdma_memctrl_t;
+
+typedef DSCT_T *nu_pdma_desc_t;
+
+typedef void (*nu_pdma_cb_handler_t)(void *, uint32_t);
+
+int nu_pdma_channel_allocate(int32_t i32PeripType);
+rt_err_t nu_pdma_channel_free(int i32ChannID);
+rt_err_t nu_pdma_callback_register(int i32ChannID, nu_pdma_cb_handler_t pfnHandler, void *pvUserData, uint32_t u32EventFilter);
+rt_err_t nu_pdma_transfer(int i32ChannID, uint32_t u32DataWidth, uint32_t u32AddrSrc, uint32_t u32AddrDst, int32_t i32TransferCnt, uint32_t u32IdleTimeout_us);
+int nu_pdma_transferred_byte_get(int32_t i32ChannID, int32_t i32TriggerByteLen);
+void nu_pdma_channel_terminate(int i32ChannID);
+nu_pdma_memctrl_t nu_pdma_channel_memctrl_get(int i32ChannID);
+rt_err_t nu_pdma_channel_memctrl_set(int i32ChannID, nu_pdma_memctrl_t eMemCtrl);
+
+nu_pdma_cb_handler_t nu_pdma_callback_hijack(int i32ChannID, nu_pdma_cb_handler_t *ppfnHandler_Hijack,
+        void **ppvUserData_Hijack, uint32_t *pu32EventFilter_Hijack);
+
+// For scatter-gather DMA
+rt_err_t nu_pdma_desc_setup(int i32ChannID, nu_pdma_desc_t dma_desc, uint32_t u32DataWidth, uint32_t u32AddrSrc, uint32_t u32AddrDst, int32_t TransferCnt, nu_pdma_desc_t next);
+rt_err_t nu_pdma_sg_transfer(int i32ChannID, nu_pdma_desc_t head, uint32_t u32IdleTimeout_us);
+rt_err_t nu_pdma_sgtbls_allocate(nu_pdma_desc_t *ppsSgtbls, int num);
+void nu_pdma_sgtbls_free(nu_pdma_desc_t *ppsSgtbls, int num);
+
+// For memory actor
+void *nu_pdma_memcpy(void *dest, void *src, unsigned int count);
+rt_size_t nu_pdma_mempush(void *dest, void *src, uint32_t data_width, unsigned int transfer_count);
+
+#endif // __DRV_PDMA_H___
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_qei.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_qei.c
new file mode 100644
index 0000000000..3be7e62b31
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_qei.c
@@ -0,0 +1,305 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author       Notes
+* 2020-4-20       FYChou       First version
+*
+******************************************************************************/
+
+#include 
+
+#if defined(BSP_USING_QEI)
+#include 
+#include "NuMicro.h"
+
+/* Private define ---------------------------------------------------------------*/
+
+/* Private typedef --------------------------------------------------------------*/
+struct nu_qei
+{
+    struct rt_pulse_encoder_device dev;
+    char *name;
+    QEI_T *qei_base;
+    rt_uint32_t max_cntval;
+    rt_uint32_t cmp_val;
+    IRQn_Type IRQn;
+    rt_uint8_t qei_type;
+    rt_uint8_t qei_flag;
+};
+typedef struct nu_qei *nu_qei_t;
+
+
+/* Private functions ------------------------------------------------------------*/
+static rt_uint32_t nu_qei_type(struct rt_pulse_encoder_device *pulse_encoder);
+static rt_err_t nu_qei_init(struct rt_pulse_encoder_device *pulse_encoder);
+static rt_int32_t nu_qei_get_count(struct rt_pulse_encoder_device *pulse_encoder);
+static rt_err_t nu_qei_clear_count(struct rt_pulse_encoder_device *pulse_encoder);
+static rt_err_t nu_qei_control(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t cmd, void *args);
+
+/* Public functions -------------------------------------------------------------*/
+rt_int32_t nu_qei_get_maxval(rt_device_t *pulse_encoder);
+rt_int32_t nu_qei_get_cmpval(rt_device_t *pulse_encoder);
+rt_int32_t nu_qei_get_type(rt_device_t *pulse_encoder);
+void nu_qei_set_maxval_type(rt_device_t *pulse_encoder, rt_uint32_t u32val, rt_uint8_t u8type);
+void nu_qei_set_cmpval(rt_device_t *pulse_encoder, rt_uint32_t u32val);
+
+/* Private variables ------------------------------------------------------------*/
+static struct nu_qei nu_qei_arr [] =
+{
+#if defined(BSP_USING_QEI0)
+    {
+        .name = "qei0",
+        .qei_base = QEI0,
+        .max_cntval = 1000,
+        .cmp_val = 100,
+        .IRQn = QEI0_IRQn,
+        .qei_type = AB_PHASE_PULSE_ENCODER,
+        .qei_flag = 0
+    },
+#endif
+
+#if defined(BSP_USING_QEI1)
+    {
+        .name = "qei1",
+        .qei_base = QEI1,
+        .max_cntval = 1000,
+        .cmp_val = 100,
+        .IRQn = QEI1_IRQn,
+        .qei_type = AB_PHASE_PULSE_ENCODER,
+        .qei_flag = 0
+    },
+#endif
+
+    {0}
+};
+
+static const struct rt_pulse_encoder_ops nu_qei_ops =
+{
+    .init = nu_qei_init,
+    .get_count = nu_qei_get_count,
+    .clear_count = nu_qei_clear_count,
+    .control = nu_qei_control,
+};
+typedef struct rt_pulse_encoder_ops *nu_qei_ops_t;
+
+/* Public variables -------------------------------------------------------------*/
+
+
+static rt_uint32_t nu_qei_type(struct rt_pulse_encoder_device *pulse_encoder)
+{
+    rt_uint32_t u32type;
+    switch (pulse_encoder->type)
+    {
+    case SINGLE_PHASE_PULSE_ENCODER:
+        u32type = (((nu_qei_t)pulse_encoder)->cmp_val) ? QEI_CTL_X2_COMPARE_COUNTING_MODE : QEI_CTL_X2_FREE_COUNTING_MODE;
+        break;
+
+    case UNKNOWN_PULSE_ENCODER_TYPE:
+    case AB_PHASE_PULSE_ENCODER:
+    default:
+        u32type = (((nu_qei_t)pulse_encoder)->cmp_val) ? QEI_CTL_X4_COMPARE_COUNTING_MODE : QEI_CTL_X4_FREE_COUNTING_MODE;
+        break;
+    }
+
+    return u32type;
+}
+
+static rt_err_t nu_qei_init(struct rt_pulse_encoder_device *pulse_encoder)
+{
+    rt_uint32_t u32type;
+    QEI_T *qui_base;
+
+    RT_ASSERT(pulse_encoder != RT_NULL);
+    qui_base = ((nu_qei_t)pulse_encoder)->qei_base;
+
+    /* enable noise filter */
+    QEI_ENABLE_NOISE_FILTER(qui_base, QEI_CTL_NFCLKSEL_DIV2);
+
+    /* set qei mode */
+    u32type = nu_qei_type(pulse_encoder);
+
+    /* set compare value and interrupt */
+    if (((nu_qei_t)pulse_encoder)->cmp_val)
+    {
+        QEI_SET_CNT_CMP(qui_base, ((nu_qei_t)pulse_encoder)->cmp_val);
+        QEI_EnableInt(qui_base, QEI_CTL_CMPIEN_Msk);
+        QEI_ENABLE_CNT_CMP(qui_base);
+        NVIC_EnableIRQ(((nu_qei_t)pulse_encoder)->IRQn);
+    }
+    QEI_Open(qui_base, u32type, ((nu_qei_t)pulse_encoder)->max_cntval);
+
+
+    return RT_EOK;
+}
+
+static rt_int32_t nu_qei_get_count(struct rt_pulse_encoder_device *pulse_encoder)
+{
+    QEI_T *qui_base;
+    RT_ASSERT(pulse_encoder != RT_NULL);
+    qui_base = ((nu_qei_t)pulse_encoder)->qei_base;
+    return (rt_int32_t)QEI_GET_CNT_VALUE(qui_base);
+}
+
+
+static rt_err_t nu_qei_clear_count(struct rt_pulse_encoder_device *pulse_encoder)
+{
+    QEI_T *qui_base;
+    RT_ASSERT(pulse_encoder != RT_NULL);
+    qui_base = ((nu_qei_t)pulse_encoder)->qei_base;
+    QEI_Stop(qui_base);
+    QEI_SET_CNT_VALUE(qui_base, 0);
+    QEI_Start(qui_base);
+    return RT_EOK;
+}
+
+static rt_err_t nu_qei_control(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t cmd, void *args)
+{
+    rt_err_t result;
+    QEI_T *qui_base;
+
+    RT_ASSERT(pulse_encoder != RT_NULL);
+    qui_base = ((nu_qei_t)pulse_encoder)->qei_base;
+
+    RT_ASSERT(cmd != RT_NULL);
+
+    result = RT_EOK;
+
+    switch (cmd)
+    {
+    case PULSE_ENCODER_CMD_ENABLE:
+        QEI_Start(qui_base);
+        if (((nu_qei_t)pulse_encoder)->cmp_val)
+        {
+            QEI_EnableInt(qui_base, QEI_CTL_CMPIEN_Msk);
+            QEI_ENABLE_CNT_CMP(qui_base);
+            NVIC_EnableIRQ(((nu_qei_t)pulse_encoder)->IRQn);
+        }
+        break;
+    case PULSE_ENCODER_CMD_DISABLE:
+        if (((nu_qei_t)pulse_encoder)->cmp_val)
+        {
+            QEI_DisableInt(qui_base, QEI_CTL_CMPIEN_Msk);
+            QEI_DISABLE_CNT_CMP(qui_base);
+            NVIC_DisableIRQ(((nu_qei_t)pulse_encoder)->IRQn);
+        }
+        QEI_Stop(qui_base);
+        break;
+    default:
+        result = -RT_ENOSYS;
+        break;
+    }
+
+    return result;
+}
+
+#if defined(BSP_USING_QEI0)
+/* QEI0 interrupt entry */
+void QEI0_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    if (QEI_GET_INT_FLAG(nu_qei_arr[0].qei_base, QEI_STATUS_CMPF_Msk))
+    {
+        nu_qei_arr[0].qei_flag = 1;
+        QEI_CLR_INT_FLAG(nu_qei_arr[0].qei_base, QEI_STATUS_CMPF_Msk);
+        rt_kprintf("QEI0 CMP flag rising\n") ;
+    }
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_QEI1)
+/* QEI1 interrupt entry */
+void QEI1_IRQHandler(void)
+{
+
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    if (QEI_GET_INT_FLAG(nu_qei_arr[1].qei_base, QEI_STATUS_CMPF_Msk))
+    {
+        nu_qei_arr[1].qei_flag = 1;
+        QEI_CLR_INT_FLAG(nu_qei_arr[1].qei_base, QEI_STATUS_CMPF_Msk);
+        rt_kprintf("QEI1 CMP flag rising\n") ;
+    }
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+rt_int32_t nu_qei_get_maxval(rt_device_t *pulse_encoder)
+{
+    return ((nu_qei_t) * pulse_encoder)->max_cntval;
+}
+
+rt_int32_t nu_qei_get_cmpval(rt_device_t *pulse_encoder)
+{
+    return ((nu_qei_t) * pulse_encoder)->cmp_val;
+}
+
+rt_int32_t nu_qei_get_type(rt_device_t *pulse_encoder)
+{
+    return ((nu_qei_t) * pulse_encoder)->qei_type;
+}
+
+void nu_qei_set_maxval_type(rt_device_t *pulse_encoder, rt_uint32_t u32val, rt_uint8_t u8type)
+{
+    QEI_T *qui_base;
+    RT_ASSERT(pulse_encoder != RT_NULL);
+    qui_base = ((nu_qei_t) * pulse_encoder)->qei_base;
+
+    RT_ASSERT(u8type <= AB_PHASE_PULSE_ENCODER);
+    ((nu_qei_t)*pulse_encoder)->qei_type = u8type;
+    ((nu_qei_t)*pulse_encoder)->dev.type = (enum rt_pulse_encoder_type)u8type;
+    ((nu_qei_t)*pulse_encoder)->max_cntval = u32val;
+    QEI_Open(qui_base, nu_qei_type(&(((nu_qei_t)*pulse_encoder)->dev)), u32val);
+}
+
+void nu_qei_set_cmpval(rt_device_t *pulse_encoder, rt_uint32_t u32val)
+{
+    QEI_T *qui_base;
+    RT_ASSERT(pulse_encoder != RT_NULL);
+    qui_base = ((nu_qei_t) * pulse_encoder)->qei_base;
+
+    ((nu_qei_t)*pulse_encoder)->cmp_val = u32val;
+    QEI_SET_CNT_CMP(qui_base, ((nu_qei_t)*pulse_encoder)->cmp_val);
+
+    if (((nu_qei_t)*pulse_encoder)->cmp_val)
+    {
+        QEI_EnableInt(qui_base, QEI_CTL_CMPIEN_Msk);
+        QEI_ENABLE_CNT_CMP(qui_base);
+        NVIC_EnableIRQ(((nu_qei_t)*pulse_encoder)->IRQn);
+    }
+    else
+    {
+        QEI_DisableInt(qui_base, QEI_CTL_CMPIEN_Msk);
+        QEI_DISABLE_CNT_CMP(qui_base);
+        NVIC_DisableIRQ(((nu_qei_t)*pulse_encoder)->IRQn);
+    }
+}
+
+
+int rt_hw_qei_init(void)
+{
+    int result = RT_ERROR;
+    int nu_sel = 0;
+    while (nu_qei_arr[nu_sel].name != 0)
+    {
+        nu_qei_arr[nu_sel].dev.type = (enum rt_pulse_encoder_type)nu_qei_arr[nu_sel].qei_type;
+        nu_qei_arr[nu_sel].dev.ops = &nu_qei_ops;
+
+        result = rt_device_pulse_encoder_register((void *)&nu_qei_arr[nu_sel], nu_qei_arr[nu_sel].name, &(nu_qei_arr[nu_sel].qei_flag));
+        RT_ASSERT(result == RT_EOK);
+        nu_sel++;
+    }
+    return result;
+}
+INIT_APP_EXPORT(rt_hw_qei_init);
+
+#endif /* BSP_USING_QEI */
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_qei.h b/bsp/nuvoton/libraries/m2354/rtt_port/drv_qei.h
new file mode 100644
index 0000000000..ae8f5a65eb
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_qei.h
@@ -0,0 +1,30 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-4-20       FYChou           First version
+*
+* Tips:
+* QEI compare interrupt flag *(pulse_encoder->user_data): If compare value is
+* not null, after execute device init, compare interrupt will be enabled automatic.
+* When the interrupt occur, interrupt flag will be set 1.
+*
+******************************************************************************/
+
+#ifndef __DRV_QEI_H__
+#define __DRV_QEI_H__
+
+#include 
+
+rt_int32_t nu_qei_get_maxval(rt_device_t *pulse_encoder);
+rt_int32_t nu_qei_get_cmpval(rt_device_t *pulse_encoder);
+rt_int32_t nu_qei_get_type(rt_device_t *pulse_encoder);
+void nu_qei_set_maxval_type(rt_device_t *pulse_encoder, rt_uint32_t u32val, rt_uint8_t u8type);
+void nu_qei_set_cmpval(rt_device_t *pulse_encoder, rt_uint32_t u32val);
+
+
+#endif // __DRV_QEI_H___
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_qspi.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_qspi.c
new file mode 100644
index 0000000000..279d4b4276
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_qspi.c
@@ -0,0 +1,404 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-6-30       YHKuo            First version
+*
+******************************************************************************/
+#include 
+
+#if defined(BSP_USING_QSPI)
+
+#define LOG_TAG                 "drv.qspi"
+#define DBG_ENABLE
+#define DBG_SECTION_NAME        LOG_TAG
+#define DBG_LEVEL               DBG_INFO
+#define DBG_COLOR
+#include 
+
+#include 
+#include 
+
+#include 
+
+/* Private define ---------------------------------------------------------------*/
+enum
+{
+    QSPI_START = -1,
+#if defined(BSP_USING_QSPI0)
+    QSPI0_IDX,
+#endif
+    QSPI_CNT
+};
+
+/* Private typedef --------------------------------------------------------------*/
+
+/* Private functions ------------------------------------------------------------*/
+static rt_err_t nu_qspi_bus_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration);
+static rt_uint32_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message);
+static int nu_qspi_register_bus(struct nu_spi *qspi_bus, const char *name);
+
+/* Public functions -------------------------------------------------------------*/
+
+/* Private variables ------------------------------------------------------------*/
+static struct rt_spi_ops nu_qspi_poll_ops =
+{
+    .configure = nu_qspi_bus_configure,
+    .xfer      = nu_qspi_bus_xfer,
+};
+
+static struct nu_spi nu_qspi_arr [] =
+{
+#if defined(BSP_USING_QSPI0)
+    {
+        .name = "qspi0",
+        .spi_base = (SPI_T *)QSPI0,
+
+#if defined(BSP_USING_SPI_PDMA)
+#if defined(BSP_USING_QSPI0_PDMA)
+        .pdma_perp_tx = PDMA_QSPI0_TX,
+        .pdma_perp_rx = PDMA_QSPI0_RX,
+#else
+        .pdma_perp_tx = NU_PDMA_UNUSED,
+        .pdma_perp_rx = NU_PDMA_UNUSED,
+#endif
+#endif
+    },
+#endif
+    {0}
+}; /* qspi nu_qspi */
+
+static rt_err_t nu_qspi_bus_configure(struct rt_spi_device *device,
+                                      struct rt_spi_configuration *configuration)
+{
+    struct nu_spi *spi_bus;
+    rt_uint32_t u32SPIMode;
+    rt_uint32_t u32BusClock;
+    rt_err_t ret = RT_EOK;
+
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(configuration != RT_NULL);
+
+    spi_bus = (struct nu_spi *) device->bus;
+
+    /* Check mode */
+    switch (configuration->mode & RT_SPI_MODE_3)
+    {
+    case RT_SPI_MODE_0:
+        u32SPIMode = SPI_MODE_0;
+        break;
+    case RT_SPI_MODE_1:
+        u32SPIMode = SPI_MODE_1;
+        break;
+    case RT_SPI_MODE_2:
+        u32SPIMode = SPI_MODE_2;
+        break;
+    case RT_SPI_MODE_3:
+        u32SPIMode = SPI_MODE_3;
+        break;
+    default:
+        ret = RT_EIO;
+        goto exit_nu_qspi_bus_configure;
+    }
+
+    /* Check data width */
+    if (!(configuration->data_width == 8  ||
+            configuration->data_width == 16 ||
+            configuration->data_width == 24 ||
+            configuration->data_width == 32))
+    {
+        ret = RT_EINVAL;
+        goto exit_nu_qspi_bus_configure;
+    }
+
+    /* Try to set clock and get actual spi bus clock */
+    u32BusClock = QSPI_SetBusClock((QSPI_T *)spi_bus->spi_base, configuration->max_hz);
+    if (configuration->max_hz > u32BusClock)
+    {
+        LOG_W("%s clock max frequency is %dHz (!= %dHz)\n", spi_bus->name, u32BusClock, configuration->max_hz);
+        configuration->max_hz = u32BusClock;
+    }
+
+    /* Need to initialize new configuration? */
+    if (rt_memcmp(configuration, &spi_bus->configuration, sizeof(struct rt_spi_configuration)) != 0)
+    {
+        rt_memcpy(&spi_bus->configuration, configuration, sizeof(struct rt_spi_configuration));
+
+        QSPI_Open((QSPI_T *)spi_bus->spi_base, SPI_MASTER, u32SPIMode, configuration->data_width, u32BusClock);
+
+        if (configuration->mode & RT_SPI_CS_HIGH)
+        {
+            /* Set CS pin to LOW */
+            SPI_SET_SS_LOW(spi_bus->spi_base);
+        }
+        else
+        {
+            /* Set CS pin to HIGH */
+            SPI_SET_SS_HIGH(spi_bus->spi_base);
+        }
+
+        if (configuration->mode & RT_SPI_MSB)
+        {
+            /* Set sequence to MSB first */
+            SPI_SET_MSB_FIRST(spi_bus->spi_base);
+        }
+        else
+        {
+            /* Set sequence to LSB first */
+            SPI_SET_LSB_FIRST(spi_bus->spi_base);
+        }
+    }
+
+    /* Clear SPI RX FIFO */
+    nu_spi_drain_rxfifo(spi_bus->spi_base);
+
+exit_nu_qspi_bus_configure:
+
+    return -(ret);
+}
+
+#if defined(RT_SFUD_USING_QSPI)
+static int nu_qspi_mode_config(struct nu_spi *qspi_bus, rt_uint8_t *tx, rt_uint8_t *rx, int qspi_lines)
+{
+    QSPI_T *qspi_base = (QSPI_T *)qspi_bus->spi_base;
+    if (qspi_lines > 1)
+    {
+        if (tx)
+        {
+            switch (qspi_lines)
+            {
+            case 2:
+                QSPI_ENABLE_DUAL_OUTPUT_MODE(qspi_base);
+                break;
+            case 4:
+                QSPI_ENABLE_QUAD_OUTPUT_MODE(qspi_base);
+                break;
+            default:
+                LOG_E("Data line is not supported.\n");
+                break;
+            }
+        }
+        else
+        {
+            switch (qspi_lines)
+            {
+            case 2:
+                QSPI_ENABLE_DUAL_INPUT_MODE(qspi_base);
+                break;
+            case 4:
+                QSPI_ENABLE_QUAD_INPUT_MODE(qspi_base);
+                break;
+            default:
+                LOG_E("Data line is not supported.\n");
+                break;
+            }
+        }
+    }
+    else
+    {
+        QSPI_DISABLE_DUAL_MODE(qspi_base);
+        QSPI_DISABLE_QUAD_MODE(qspi_base);
+    }
+    return qspi_lines;
+}
+#endif
+
+static rt_uint32_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
+{
+    struct nu_spi *qspi_bus;
+    struct rt_qspi_configuration *qspi_configuration;
+#if defined(RT_SFUD_USING_QSPI)
+    struct rt_qspi_message *qspi_message;
+    rt_uint8_t u8last = 1;
+#endif
+    rt_uint8_t bytes_per_word;
+    QSPI_T *qspi_base;
+    rt_uint32_t u32len = 0;
+
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(message != RT_NULL);
+
+    qspi_bus = (struct nu_spi *) device->bus;
+    qspi_base = (QSPI_T *)qspi_bus->spi_base;
+    qspi_configuration = &qspi_bus->configuration;
+
+    bytes_per_word = qspi_configuration->parent.data_width / 8;
+
+    if (message->cs_take && !(qspi_configuration->parent.mode & RT_SPI_NO_CS))
+    {
+        if (qspi_configuration->parent.mode & RT_SPI_CS_HIGH)
+        {
+            QSPI_SET_SS_HIGH(qspi_base);
+        }
+        else
+        {
+            QSPI_SET_SS_LOW(qspi_base);
+        }
+    }
+
+#if defined(RT_SFUD_USING_QSPI)
+    qspi_message = (struct rt_qspi_message *)message;
+
+    /* Command + Address + Dummy + Data */
+    /* Command stage */
+    if (qspi_message->instruction.content != 0)
+    {
+        u8last = nu_qspi_mode_config(qspi_bus, (rt_uint8_t *) &qspi_message->instruction.content, RT_NULL, qspi_message->instruction.qspi_lines);
+        nu_spi_transfer((struct nu_spi *)qspi_bus,
+                        (rt_uint8_t *) &qspi_message->instruction.content,
+                        RT_NULL,
+                        1,
+                        1);
+    }
+
+    /* Address stage */
+    if (qspi_message->address.size != 0)
+    {
+        rt_uint32_t u32ReversedAddr = 0;
+        rt_uint32_t u32AddrNumOfByte = qspi_message->address.size / 8;
+        switch (u32AddrNumOfByte)
+        {
+        case 1:
+            u32ReversedAddr = (qspi_message->address.content & 0xff);
+            break;
+        case 2:
+            nu_set16_be((rt_uint8_t *)&u32ReversedAddr, qspi_message->address.content);
+            break;
+        case 3:
+            nu_set24_be((rt_uint8_t *)&u32ReversedAddr, qspi_message->address.content);
+            break;
+        case 4:
+            nu_set32_be((rt_uint8_t *)&u32ReversedAddr, qspi_message->address.content);
+            break;
+        default:
+            RT_ASSERT(0);
+            break;
+        }
+        u8last = nu_qspi_mode_config(qspi_bus, (rt_uint8_t *)&u32ReversedAddr, RT_NULL, qspi_message->address.qspi_lines);
+        nu_spi_transfer((struct nu_spi *)qspi_bus,
+                        (rt_uint8_t *) &u32ReversedAddr,
+                        RT_NULL,
+                        u32AddrNumOfByte,
+                        1);
+    }
+
+    /* Dummy_cycles stage */
+    if (qspi_message->dummy_cycles != 0)
+    {
+        qspi_bus->dummy = 0x00;
+
+        u8last = nu_qspi_mode_config(qspi_bus, (rt_uint8_t *) &qspi_bus->dummy, RT_NULL, u8last);
+        nu_spi_transfer((struct nu_spi *)qspi_bus,
+                        (rt_uint8_t *) &qspi_bus->dummy,
+                        RT_NULL,
+                        qspi_message->dummy_cycles / (8 / u8last),
+                        1);
+    }
+
+    /* Data stage */
+    nu_qspi_mode_config(qspi_bus, (rt_uint8_t *) message->send_buf, (rt_uint8_t *) message->recv_buf, qspi_message->qspi_data_lines);
+#endif //#if defined(RT_SFUD_USING_QSPI)
+
+    if (message->length != 0)
+    {
+        nu_spi_transfer((struct nu_spi *)qspi_bus,
+                        (rt_uint8_t *) message->send_buf,
+                        (rt_uint8_t *) message->recv_buf,
+                        message->length,
+                        bytes_per_word);
+        u32len = message->length;
+    }
+    else
+    {
+        u32len = 1;
+    }
+
+    if (message->cs_release && !(qspi_configuration->parent.mode & RT_SPI_NO_CS))
+    {
+        if (qspi_configuration->parent.mode & RT_SPI_CS_HIGH)
+        {
+            QSPI_SET_SS_LOW(qspi_base);
+        }
+        else
+        {
+            QSPI_SET_SS_HIGH(qspi_base);
+        }
+    }
+
+    return u32len;
+}
+
+static int nu_qspi_register_bus(struct nu_spi *qspi_bus, const char *name)
+{
+    return rt_qspi_bus_register(&qspi_bus->dev, name, &nu_qspi_poll_ops);
+}
+
+/**
+ * Hardware SPI Initial
+ */
+static int rt_hw_qspi_init(void)
+{
+    rt_uint8_t i;
+
+    for (i = (QSPI_START + 1); i < QSPI_CNT; i++)
+    {
+        nu_qspi_register_bus(&nu_qspi_arr[i], nu_qspi_arr[i].name);
+#if defined(BSP_USING_SPI_PDMA)
+        nu_qspi_arr[i].pdma_chanid_tx = -1;
+        nu_qspi_arr[i].pdma_chanid_rx = -1;
+#endif
+#if defined(BSP_USING_QSPI_PDMA)
+        if ((nu_qspi_arr[i].pdma_perp_tx != NU_PDMA_UNUSED) && (nu_qspi_arr[i].pdma_perp_rx != NU_PDMA_UNUSED))
+        {
+            if (nu_hw_spi_pdma_allocate(&nu_qspi_arr[i]) != RT_EOK)
+            {
+                LOG_E("Failed to allocate DMA channels for %s. We will use poll-mode for this bus.\n", nu_qspi_arr[i].name);
+            }
+        }
+#endif
+    }
+
+    return 0;
+}
+INIT_DEVICE_EXPORT(rt_hw_qspi_init);
+
+rt_err_t nu_qspi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint8_t data_line_width, void (*enter_qspi_mode)(), void (*exit_qspi_mode)())
+{
+    struct rt_qspi_device *qspi_device = RT_NULL;
+    rt_err_t result = RT_EOK;
+
+    RT_ASSERT(bus_name != RT_NULL);
+    RT_ASSERT(device_name != RT_NULL);
+    RT_ASSERT(data_line_width == 1 || data_line_width == 2 || data_line_width == 4);
+
+    qspi_device = (struct rt_qspi_device *)rt_malloc(sizeof(struct rt_qspi_device));
+    if (qspi_device == RT_NULL)
+    {
+        LOG_E("no memory, qspi bus attach device failed!\n");
+        result = -RT_ENOMEM;
+        goto __exit;
+    }
+
+    qspi_device->enter_qspi_mode = enter_qspi_mode;
+    qspi_device->exit_qspi_mode = exit_qspi_mode;
+    qspi_device->config.qspi_dl_width = data_line_width;
+
+    result = rt_spi_bus_attach_device(&qspi_device->parent, device_name, bus_name, RT_NULL);
+
+__exit:
+    if (result != RT_EOK)
+    {
+        if (qspi_device)
+        {
+            rt_free(qspi_device);
+        }
+    }
+
+    return  result;
+}
+
+#endif //#if defined(BSP_USING_QSPI)
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_rtc.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_rtc.c
new file mode 100644
index 0000000000..44c2ee30dd
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_rtc.c
@@ -0,0 +1,355 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author       Notes
+* 2020-06-19      klcheng      First version
+*
+******************************************************************************/
+#include 
+
+#if defined (BSP_USING_RTC)
+
+#include 
+#include 
+#include "NuMicro.h"
+
+/* Private define ---------------------------------------------------------------*/
+
+/* convert the real year and month value to the format of struct tm. */
+#define CONV_TO_TM_YEAR(year)           ((year) - 1900)
+#define CONV_TO_TM_MON(mon)             ((mon) - 1)
+
+/* convert the tm_year and tm_mon from struct tm to the real value. */
+#define CONV_FROM_TM_YEAR(tm_year)      ((tm_year) + 1900)
+#define CONV_FROM_TM_MON(tm_mon)        ((tm_mon) + 1)
+
+/* rtc date upper bound reaches the year of 2099. */
+#define RTC_TM_UPPER_BOUND                                              \
+{   .tm_year = CONV_TO_TM_YEAR(2099),                                   \
+    .tm_mon  = CONV_TO_TM_MON(12),                                      \
+    .tm_mday  = 31,                                                     \
+    .tm_hour  = 23,                                                     \
+    .tm_min = 59,                                                       \
+    .tm_sec  = 59,                                                      \
+}
+
+/* rtc date lower bound reaches the year of 2000. */
+#define RTC_TM_LOWER_BOUND                                              \
+{   .tm_year = CONV_TO_TM_YEAR(2000),                                   \
+    .tm_mon  = CONV_TO_TM_MON(1),                                       \
+    .tm_mday  = 1,                                                      \
+    .tm_hour  = 0,                                                      \
+    .tm_min = 0,                                                        \
+    .tm_sec  = 0,                                                       \
+}
+
+/* Private typedef --------------------------------------------------------------*/
+
+/* Private functions ------------------------------------------------------------*/
+static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args);
+
+#if defined (NU_RTC_SUPPORT_IO_RW)
+    static rt_size_t nu_rtc_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size);
+    static rt_size_t nu_rtc_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size);
+#endif
+
+static rt_err_t nu_rtc_is_date_valid(const time_t *const t);
+static void nu_rtc_init(void);
+
+#if defined(RT_USING_ALARM)
+    static void nu_rtc_alarm_reset(void);
+#endif
+
+/* Public functions -------------------------------------------------------------*/
+#if defined (NU_RTC_SUPPORT_MSH_CMD)
+    extern rt_err_t set_date(rt_uint32_t year, rt_uint32_t month, rt_uint32_t day);
+    extern rt_err_t set_time(rt_uint32_t hour, rt_uint32_t minute, rt_uint32_t second);
+#endif
+
+/* Private variables ------------------------------------------------------------*/
+static struct rt_device device_rtc;
+
+
+static void nu_rtc_init(void)
+{
+    /* hw rtc initialise */
+    RTC_Open(NULL);
+    RTC_DisableInt(RTC_INTEN_ALMIEN_Msk | RTC_INTEN_TICKIEN_Msk | RTC_INTEN_TAMP0IEN_Msk |
+                   RTC_INTEN_TAMP1IEN_Msk | RTC_INTEN_TAMP2IEN_Msk | RTC_INTEN_TAMP3IEN_Msk |
+                   RTC_INTEN_TAMP4IEN_Msk | RTC_INTEN_TAMP5IEN_Msk | RTC_INTEN_CLKFIEN_Msk |
+                   RTC_INTEN_CLKSTIEN_Msk);
+
+#if defined(RT_USING_ALARM)
+
+    nu_rtc_alarm_reset();
+    RTC_EnableInt(RTC_INTEN_ALMIEN_Msk);
+    NVIC_EnableIRQ(RTC_IRQn);
+#endif
+}
+
+
+#if defined(RT_USING_ALARM)
+/* Reset alarm settings to avoid the unwanted values remain in rtc registers. */
+static void nu_rtc_alarm_reset(void)
+{
+    S_RTC_TIME_DATA_T alarm;
+
+    /* Reset alarm time and calendar. */
+    alarm.u32Year       = RTC_YEAR2000;
+    alarm.u32Month      = 0;
+    alarm.u32Day        = 0;
+    alarm.u32Hour       = 0;
+    alarm.u32Minute     = 0;
+    alarm.u32Second     = 0;
+    alarm.u32TimeScale  = RTC_CLOCK_24;
+
+    RTC_SetAlarmDateAndTime(&alarm);
+
+    /* Reset alarm time mask and calendar mask. */
+    RTC_SetAlarmDateMask(0, 0, 0, 0, 0, 0);
+    RTC_SetAlarmTimeMask(0, 0, 0, 0, 0, 0);
+
+    /* Clear alarm flag for safe */
+    RTC_CLEAR_ALARM_INT_FLAG(RTC);
+}
+#endif
+
+
+/* rtc device driver initialise. */
+int rt_hw_rtc_init(void)
+{
+    rt_err_t ret;
+
+    nu_rtc_init();
+
+    /* register rtc device IO operations */
+    device_rtc.type = RT_Device_Class_RTC;
+    device_rtc.init = NULL;
+    device_rtc.open = NULL;
+    device_rtc.close = NULL;
+    device_rtc.control = nu_rtc_control;
+
+#if defined (NU_RTC_SUPPORT_IO_RW)
+    device_rtc.read = nu_rtc_read;
+    device_rtc.write = nu_rtc_write;
+#else
+    device_rtc.read = NULL;
+    device_rtc.write = NULL;
+#endif
+
+    device_rtc.user_data = RT_NULL;
+    device_rtc.rx_indicate = RT_NULL;
+    device_rtc.tx_complete = RT_NULL;
+
+    ret = rt_device_register(&device_rtc, "rtc", RT_DEVICE_FLAG_RDWR);
+
+    return (int)ret;
+}
+INIT_BOARD_EXPORT(rt_hw_rtc_init);
+
+
+#if defined (NU_RTC_SUPPORT_IO_RW)
+/* Register rt-thread device.read() entry. */
+static rt_size_t nu_rtc_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
+{
+    (void) pos;
+    nu_rtc_control(dev, RT_DEVICE_CTRL_RTC_GET_TIME, buffer);
+
+    return size;
+}
+#endif
+
+
+#if defined (NU_RTC_SUPPORT_IO_RW)
+/* Register rt-thread device.write() entry. */
+static rt_size_t nu_rtc_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
+{
+    (void) pos;
+    nu_rtc_control(dev, RT_DEVICE_CTRL_RTC_SET_TIME, (void *)buffer);
+
+    return size;
+}
+#endif
+
+
+static rt_err_t nu_rtc_is_date_valid(const time_t *const t)
+{
+    static struct tm tm_upper = RTC_TM_UPPER_BOUND;
+    static struct tm tm_lower = RTC_TM_LOWER_BOUND;
+    static time_t t_upper, t_lower;
+    static rt_bool_t initialised = RT_FALSE;
+
+    if (!initialised)
+    {
+        t_upper = timegm((struct tm *)&tm_upper);
+        t_lower = timegm((struct tm *)&tm_lower);
+        initialised = RT_TRUE;
+    }
+
+    /* check the date is supported by rtc. */
+    if ((*t > t_upper) || (*t < t_lower))
+        return -(RT_EINVAL);
+
+    return RT_EOK;
+}
+
+
+/* Register rt-thread device.control() entry. */
+static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args)
+{
+    struct tm tm_out, *tm_in;
+    time_t *time;
+    S_RTC_TIME_DATA_T hw_time;
+
+#if defined(RT_USING_ALARM)
+
+    struct rt_rtc_wkalarm *wkalarm;
+    S_RTC_TIME_DATA_T hw_alarm;
+#endif
+
+    if ((dev == NULL) || (args == NULL))
+        return -(RT_EINVAL);
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_RTC_GET_TIME:
+
+        time = (time_t *)args;
+        RTC_GetDateAndTime(&hw_time);
+
+        tm_out.tm_year = CONV_TO_TM_YEAR(hw_time.u32Year);
+        tm_out.tm_mon = CONV_TO_TM_MON(hw_time.u32Month);
+        tm_out.tm_mday = hw_time.u32Day;
+        tm_out.tm_hour = hw_time.u32Hour;
+        tm_out.tm_min = hw_time.u32Minute;
+        tm_out.tm_sec = hw_time.u32Second;
+        *time = timegm(&tm_out);
+        break;
+
+    case RT_DEVICE_CTRL_RTC_SET_TIME:
+
+        time = (time_t *) args;
+        tm_in = gmtime(time);
+
+        if (nu_rtc_is_date_valid(time) != RT_EOK)
+            return RT_ERROR;
+
+        hw_time.u32Year = CONV_FROM_TM_YEAR(tm_in->tm_year);
+        hw_time.u32Month = CONV_FROM_TM_MON(tm_in->tm_mon);
+        hw_time.u32Day = tm_in->tm_mday;
+        hw_time.u32Hour = tm_in->tm_hour;
+        hw_time.u32Minute = tm_in->tm_min;
+        hw_time.u32Second = tm_in->tm_sec;
+        hw_time.u32TimeScale = RTC_CLOCK_24;
+        hw_time.u32AmPm = 0;
+
+        RTC_SetDateAndTime(&hw_time);
+        break;
+
+#if defined(RT_USING_ALARM)
+    case RT_DEVICE_CTRL_RTC_GET_ALARM:
+
+        wkalarm = (struct rt_rtc_wkalarm *) args;
+        RTC_GetAlarmDateAndTime(&hw_alarm);
+
+        wkalarm->tm_hour = hw_alarm.u32Hour;
+        wkalarm->tm_min = hw_alarm.u32Minute;
+        wkalarm->tm_sec = hw_alarm.u32Second;
+        break;
+
+    case RT_DEVICE_CTRL_RTC_SET_ALARM:
+
+        wkalarm = (struct rt_rtc_wkalarm *) args;
+        hw_alarm.u32Hour = wkalarm->tm_hour;
+        hw_alarm.u32Minute = wkalarm->tm_min;
+        hw_alarm.u32Second = wkalarm->tm_sec;
+
+        RTC_SetAlarmDateMask(1, 1, 1, 1, 1, 1);
+        RTC_SetAlarmDateAndTime(&hw_alarm);
+        break;
+
+    default:
+        return -(RT_EINVAL);
+#endif
+    }
+
+    return RT_EOK;
+}
+
+
+#if defined (NU_RTC_SUPPORT_MSH_CMD)
+
+/* Support "rtc_det_date" command line in msh mode */
+static rt_err_t msh_rtc_set_date(int argc, char **argv)
+{
+    rt_uint32_t index, len, arg[3];
+
+    rt_memset(arg, 0, sizeof(arg));
+    len = (argc >= 4) ? 4 : argc;
+
+    /* The date information stored in argv is represented by the following order :
+       argv[0,1,2,3] = [cmd, year, month, day] */
+    for (index = 0; index < (len - 1); index ++)
+    {
+        arg[index] = atol(argv[index + 1]);
+    }
+
+    return set_date(arg[0], arg[1], arg[2]);
+}
+MSH_CMD_EXPORT_ALIAS(msh_rtc_set_date, rtc_set_date, e.g: rtc_set_date 2020 1 20);
+#endif
+
+
+#if defined (NU_RTC_SUPPORT_MSH_CMD)
+
+/* Support "rtc_det_time" command line in msh mode */
+static rt_err_t msh_rtc_set_time(int argc, char **argv)
+{
+    rt_uint32_t index, len, arg[3];
+
+    rt_memset(arg, 0, sizeof(arg));
+    len = (argc >= 4) ? 4 : argc;
+
+    /* The time information stored in argv is represented by the following order :
+       argv[0,1,2,3] = [cmd, hour, minute, second] */
+    for (index = 0; index < (len - 1); index ++)
+    {
+        arg[index] = atol(argv[index + 1]);
+    }
+
+    return set_time(arg[0], arg[1], arg[2]);
+}
+MSH_CMD_EXPORT_ALIAS(msh_rtc_set_time, rtc_set_time, e.g: rtc_set_time 18 30 00);
+#endif
+
+
+/* rtc interrupt entry */
+void RTC_IRQHandler(void)
+{
+    rt_interrupt_enter();
+
+    if (RTC_GET_TICK_INT_FLAG(RTC))
+    {
+        RTC_CLEAR_TICK_INT_FLAG(RTC);
+    }
+
+#if defined(RT_USING_ALARM)
+
+    if (RTC_GET_ALARM_INT_FLAG(RTC))
+    {
+        RTC_CLEAR_ALARM_INT_FLAG(RTC);
+
+        /* Send an alarm event to notify rt-thread alarm service. */
+        rt_alarm_update(&device_rtc, NULL);
+    }
+#endif
+
+    rt_interrupt_leave();
+}
+
+#endif /* BSP_USING_RTC */
+
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_scuart.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_scuart.c
new file mode 100644
index 0000000000..3d83615002
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_scuart.c
@@ -0,0 +1,391 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author       Notes
+* 2020-7-31       Egbert       First version
+*
+******************************************************************************/
+
+#include 
+
+#if defined(BSP_USING_SCUART)
+
+#include "NuMicro.h"
+#include 
+#include 
+
+/* Private definition ---------------------------------------------------------------*/
+#define LOG_TAG         "drv.scuart"
+#define DBG_ENABLE
+#define DBG_SECTION_NAME "drv.scuart"
+#define DBG_LEVEL DBG_ERROR
+#define DBG_COLOR
+#include 
+
+enum
+{
+    SCUART_START = -1,
+#if defined(BSP_USING_SCUART0)
+    SCUART0_IDX,
+#endif
+#if defined(BSP_USING_SCUART1)
+    SCUART1_IDX,
+#endif
+#if defined(BSP_USING_SCUART2)
+    SCUART2_IDX,
+#endif
+    SCUART_CNT
+};
+
+/* Private typedef --------------------------------------------------------------*/
+struct nu_scuart
+{
+    rt_serial_t dev;
+    char *name;
+    SC_T *scuart_base;
+    uint32_t scuart_rst;
+    IRQn_Type scuart_irq_n;
+
+};
+typedef struct nu_scuart *nu_scuart_t;
+
+/* Private functions ------------------------------------------------------------*/
+static rt_err_t nu_scuart_configure(struct rt_serial_device *serial, struct serial_configure *cfg);
+static rt_err_t nu_scuart_control(struct rt_serial_device *serial, int cmd, void *arg);
+static int nu_scuart_send(struct rt_serial_device *serial, char c);
+static int nu_scuart_receive(struct rt_serial_device *serial);
+static void nu_scuart_isr(nu_scuart_t serial);
+
+/* Public functions ------------------------------------------------------------*/
+
+/* Private variables ------------------------------------------------------------*/
+
+static const struct rt_uart_ops nu_scuart_ops =
+{
+    .configure      = nu_scuart_configure,
+    .control        = nu_scuart_control,
+    .putc           = nu_scuart_send,
+    .getc           = nu_scuart_receive,
+    .dma_transmit   = RT_NULL /* not support DMA mode */
+};
+
+static const struct serial_configure nu_scuart_default_config =
+        RT_SERIAL_CONFIG_DEFAULT;
+
+static struct nu_scuart nu_scuart_arr [] =
+{
+#if defined(BSP_USING_SCUART0)
+    {
+        .name = "scuart0",
+        .scuart_base = SC0,
+        .scuart_rst = SC0_RST,
+        .scuart_irq_n = SC0_IRQn,
+    },
+#endif
+
+#if defined(BSP_USING_SCUART1)
+    {
+        .name = "scuart1",
+        .scuart_base = SC1,
+        .scuart_rst = SC1_RST,
+        .scuart_irq_n = SC1_IRQn,
+    },
+#endif
+
+#if defined(BSP_USING_SCUART2)
+    {
+        .name = "scuart2",
+        .scuart_base = SC2,
+        .scuart_rst = SC2_RST,
+        .scuart_irq_n = SC2_IRQn,
+    },
+#endif
+
+    {0}
+}; /* scuart nu_scuart */
+
+/* Interrupt Handle Function  ----------------------------------------------------*/
+#if defined(BSP_USING_SCUART0)
+/* SCUART0 interrupt entry */
+void SC0_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    nu_scuart_isr(&nu_scuart_arr[SCUART0_IDX]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_SCUART1)
+/* SCUART1 interrupt entry */
+void SC1_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    nu_scuart_isr(&nu_scuart_arr[SCUART1_IDX]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_SCUART2)
+/* SCUART2 interrupt entry */
+void SC2_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    nu_scuart_isr(&nu_scuart_arr[SCUART2_IDX]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+
+
+/**
+ * All SCUART interrupt service routine
+ */
+static void nu_scuart_isr(nu_scuart_t serial)
+{
+    /* Get base address of scuart register */
+    SC_T *scuart_base = ((nu_scuart_t)serial)->scuart_base;
+
+    /* Get interrupt event */
+    uint32_t u32IntSts = scuart_base->INTSTS;
+
+    /* Handle RX event */
+    if (u32IntSts & (SC_INTSTS_RDAIF_Msk | SC_INTSTS_RXTOIF_Msk))
+    {
+        rt_hw_serial_isr(&serial->dev, RT_SERIAL_EVENT_RX_IND);
+
+        // RDA is the only interrupt enabled in this driver, this status bit
+        // automatically cleared after Rx FIFO empty. So no need to clear interrupt
+        // status here.
+        scuart_base->INTSTS = SC_INTSTS_RXTOIF_Msk;
+    }
+}
+
+/**
+ * Configure scuart port
+ */
+static rt_err_t nu_scuart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    rt_err_t ret = RT_EOK;
+    uint32_t scuart_word_len = 0;
+    uint32_t scuart_stop_bit = 0;
+    uint32_t scuart_parity = 0;
+
+    /* Get base address of scuart register */
+    SC_T *scuart_base = ((nu_scuart_t)serial)->scuart_base;
+
+    /* Check baudrate */
+    RT_ASSERT(cfg->baud_rate != 0);
+
+    /* Check word len */
+    switch (cfg->data_bits)
+    {
+    case DATA_BITS_5:
+        scuart_word_len = SCUART_CHAR_LEN_5;
+        break;
+
+    case DATA_BITS_6:
+        scuart_word_len = SCUART_CHAR_LEN_6;
+        break;
+
+    case DATA_BITS_7:
+        scuart_word_len = SCUART_CHAR_LEN_7;
+        break;
+
+    case DATA_BITS_8:
+        scuart_word_len = SCUART_CHAR_LEN_8;
+        break;
+
+    default:
+        LOG_E("Unsupported data length");
+        ret = RT_EINVAL;
+        goto exit_nu_scuart_configure;
+    }
+
+    /* Check stop bit */
+    switch (cfg->stop_bits)
+    {
+    case STOP_BITS_1:
+        scuart_stop_bit = SCUART_STOP_BIT_1;
+        break;
+
+    case STOP_BITS_2:
+        scuart_stop_bit = SCUART_STOP_BIT_2;
+        break;
+
+    default:
+        LOG_E("Unsupported stop bit");
+        ret = RT_EINVAL;
+        goto exit_nu_scuart_configure;
+    }
+
+    /* Check parity */
+    switch (cfg->parity)
+    {
+    case PARITY_NONE:
+        scuart_parity = SCUART_PARITY_NONE;
+        break;
+
+    case PARITY_ODD:
+        scuart_parity = SCUART_PARITY_ODD;
+        break;
+
+    case PARITY_EVEN:
+        scuart_parity = SCUART_PARITY_EVEN;
+        break;
+
+    default:
+        LOG_E("Unsupported parity");
+        ret = RT_EINVAL;
+        goto exit_nu_scuart_configure;
+    }
+
+    /* Reset this module */
+    SYS_ResetModule(((nu_scuart_t)serial)->scuart_rst);
+
+    /* Open SCUART and set SCUART Baudrate */
+    SCUART_Open(scuart_base, cfg->baud_rate);
+
+    /* Set line configuration. */
+    SCUART_SetLineConfig(scuart_base, 0, scuart_word_len, scuart_parity, scuart_stop_bit);
+
+    /* Enable NVIC interrupt. */
+    NVIC_EnableIRQ(((nu_scuart_t)serial)->scuart_irq_n);
+
+exit_nu_scuart_configure:
+
+    if (ret != RT_EOK)
+        SCUART_Close(scuart_base);
+
+    return -(ret);
+}
+
+/**
+ * SCUART interrupt control
+ */
+static rt_err_t nu_scuart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    rt_err_t result = RT_EOK;
+    rt_uint32_t flag;
+    rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    /* Get base address of scuart register */
+    SC_T *scuart_base = ((nu_scuart_t)serial)->scuart_base;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Disable INT-RX */
+        {
+            flag = SC_INTEN_RDAIEN_Msk | SC_INTEN_RXTOIEN_Msk;
+            SCUART_DISABLE_INT(scuart_base, flag);
+        }
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Enable INT-RX */
+        {
+            flag = SC_INTEN_RDAIEN_Msk | SC_INTEN_RXTOIEN_Msk;
+            SCUART_ENABLE_INT(scuart_base, flag);
+        }
+        break;
+
+    case RT_DEVICE_CTRL_CLOSE:
+        /* Disable NVIC interrupt. */
+        NVIC_DisableIRQ(((nu_scuart_t)serial)->scuart_irq_n);
+
+        /* Reset this module */
+        SYS_ResetModule(((nu_scuart_t)serial)->scuart_rst);
+
+        /* Close SCUART port */
+        SCUART_Close(scuart_base);
+
+        break;
+
+    default:
+        result = -RT_EINVAL;
+        break;
+    }
+    return result;
+}
+
+/**
+ * SCUART put char
+ */
+static int nu_scuart_send(struct rt_serial_device *serial, char c)
+{
+    RT_ASSERT(serial != RT_NULL);
+
+    /* Get base address of scuart register */
+    SC_T *scuart_base = ((nu_scuart_t)serial)->scuart_base;
+
+    /* Waiting if TX-FIFO is full. */
+    while (SCUART_IS_TX_FULL(scuart_base));
+
+    /* Put char into TX-FIFO */
+    SCUART_WRITE(scuart_base, c);
+
+    return 1;
+}
+
+/**
+ * SCUART get char
+ */
+static int nu_scuart_receive(struct rt_serial_device *serial)
+{
+    RT_ASSERT(serial != RT_NULL);
+
+    /* Get base address of scuart register */
+    SC_T *scuart_base = ((nu_scuart_t)serial)->scuart_base;
+
+    /* Return failure if RX-FIFO is empty. */
+    if (SCUART_GET_RX_EMPTY(scuart_base))
+    {
+        return -1;
+    }
+
+    /* Get char from RX-FIFO */
+    return SCUART_READ(scuart_base);
+}
+
+/**
+ * Hardware SCUART Initialization
+ */
+static int rt_hw_scuart_init(void)
+{
+    int i;
+    rt_uint32_t flag;
+    rt_err_t ret = RT_EOK;
+
+    for (i = (SCUART_START + 1); i < SCUART_CNT; i++)
+    {
+        flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX;
+
+        nu_scuart_arr[i].dev.ops    = &nu_scuart_ops;
+        nu_scuart_arr[i].dev.config = nu_scuart_default_config;
+
+        ret = rt_hw_serial_register(&nu_scuart_arr[i].dev, nu_scuart_arr[i].name, flag, NULL);
+        RT_ASSERT(ret == RT_EOK);
+    }
+
+    return ret;
+}
+INIT_DEVICE_EXPORT(rt_hw_scuart_init);
+#endif //#if defined(BSP_USING_SCUART)
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_sdh.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_sdh.c
new file mode 100644
index 0000000000..708f653d36
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_sdh.c
@@ -0,0 +1,592 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-7-7        Wayne            First version
+*
+******************************************************************************/
+
+#include 
+
+#if defined(BSP_USING_SDH)
+
+#include 
+#include "NuMicro.h"
+#include 
+#include 
+
+#if defined(RT_USING_DFS)
+    #include 
+    #include 
+#endif
+
+/* Private define ---------------------------------------------------------------*/
+
+#if defined(NU_SDH_MOUNT_ON_ROOT)
+
+    #ifndef NU_SDH_MOUNTPOINT_SDH0
+        #define NU_SDH_MOUNTPOINT_SDH0  "/"
+    #endif
+
+#else
+
+    #if !defined(NU_SDH_MOUNTPOINT_ROOT)
+        #define NU_SDH_MOUNTPOINT_ROOT  "/mnt"
+    #endif
+
+#endif
+
+#if !defined(NU_SDH_MOUNTPOINT_SDH0)
+    #define NU_SDH_MOUNTPOINT_SDH0  NU_SDH_MOUNTPOINT_ROOT"/sd0"
+#endif
+
+#if defined(NU_SDH_USING_PDMA)
+    #define NU_SDH_MEMCPY  nu_pdma_memcpy
+#else
+    #define NU_SDH_MEMCPY  memcpy
+#endif
+
+enum
+{
+    SDH_START = -1,
+#if defined(BSP_USING_SDH0)
+    SDH0_IDX,
+#endif
+    SDH_CNT
+};
+
+#define SDH_BLOCK_SIZE   512ul
+
+#if defined(NU_SDH_HOTPLUG)
+    #define NU_SDH_TID_STACK_SIZE  1024
+#endif
+
+#if defined(NU_SDH_HOTPLUG)
+enum
+{
+    NU_SDH_CARD_DETECTED_SD0 = (1 << 0),
+    NU_SDH_CARD_EVENT_ALL = (NU_SDH_CARD_DETECTED_SD0)
+};
+#endif
+
+/* Private typedef --------------------------------------------------------------*/
+struct nu_sdh
+{
+    struct rt_device      dev;
+    char                 *name;
+#if defined(NU_SDH_HOTPLUG)
+    char                 *mounted_point;
+#endif
+    SDH_T                *base;
+    uint32_t              is_card_inserted;
+    SDH_INFO_T           *info;
+    struct rt_semaphore   lock;
+    uint8_t              *pbuf;
+};
+typedef struct nu_sdh *nu_sdh_t;
+
+#if defined(NU_SDH_HOTPLUG)
+    static struct rt_thread sdh_tid;
+    static rt_uint8_t sdh_stack[NU_SDH_TID_STACK_SIZE];
+#endif
+
+/* Private functions ------------------------------------------------------------*/
+static void nu_sdh_isr(nu_sdh_t sdh);
+static rt_err_t nu_sdh_init(rt_device_t dev);
+static rt_err_t nu_sdh_open(rt_device_t dev, rt_uint16_t oflag);
+static rt_err_t nu_sdh_close(rt_device_t dev);
+static rt_size_t nu_sdh_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t blk_nb);
+static rt_err_t nu_sdh_control(rt_device_t dev, int cmd, void *args);
+static int rt_hw_sdh_init(void);
+
+#if defined(NU_SDH_HOTPLUG)
+    static rt_bool_t nu_sdh_hotplug_is_mounted(const char *mounting_path);
+    static void sdh_hotplugger(void *param);
+    static rt_err_t nu_sdh_hotplug_mount(nu_sdh_t sdh);
+    static rt_err_t nu_sdh_hotplug_unmount(nu_sdh_t sdh);
+#endif
+
+/* Public functions -------------------------------------------------------------*/
+
+
+/* Private variables ------------------------------------------------------------*/
+static struct nu_sdh nu_sdh_arr [] =
+{
+#if defined(BSP_USING_SDH0)
+    {
+        .name = "sdh0",
+#if defined(NU_SDH_HOTPLUG)
+        .mounted_point = NU_SDH_MOUNTPOINT_SDH0,
+#endif
+        .base = SDH0,
+        .info = &SD0,
+    },
+#endif
+    {0}
+}; /* struct nu_sdh nu_sdh_arr [] */
+static struct rt_event sdh_event;
+
+static void nu_sdh_isr(nu_sdh_t sdh)
+{
+    SDH_T *sdh_base = sdh->base;
+    unsigned int volatile isr;
+    unsigned int volatile ier;
+
+    // FMI data abort interrupt
+    if (sdh_base->GINTSTS & SDH_GINTSTS_DTAIF_Msk)
+    {
+        /* ResetAllEngine() */
+        sdh_base->GCTL |= SDH_GCTL_GCTLRST_Msk;
+    }
+
+    //----- SD interrupt status
+    isr = sdh_base->INTSTS;
+    if (isr & SDH_INTSTS_BLKDIF_Msk)
+    {
+        // block down
+        g_u8SDDataReadyFlag = TRUE;
+        SDH_CLR_INT_FLAG(sdh_base, SDH_INTSTS_BLKDIF_Msk);
+    }
+
+    if (isr & SDH_INTSTS_CDIF_Msk)   // card detect
+    {
+#if defined(NU_SDH_HOTPLUG)
+        if (sdh->base == SDH0)
+            rt_event_send(&sdh_event, NU_SDH_CARD_DETECTED_SD0);
+#endif
+        /* Clear CDIF interrupt flag */
+        SDH_CLR_INT_FLAG(sdh_base, SDH_INTSTS_CDIF_Msk);
+    }
+
+    // CRC error interrupt
+    if (isr & SDH_INTSTS_CRCIF_Msk)
+    {
+        if (!(isr & SDH_INTSTS_CRC16_Msk))
+        {
+            /* CRC_16 error */
+            // TODO: handle CRC 16 error
+        }
+        else if (!(isr & SDH_INTSTS_CRC7_Msk))
+        {
+            if (!g_u8R3Flag)
+            {
+                /* CRC_7 error */
+                // TODO: handle CRC 7 error
+            }
+        }
+        /* Clear CRCIF interrupt flag */
+        SDH_CLR_INT_FLAG(sdh_base, SDH_INTSTS_CRCIF_Msk);
+    }
+
+    /* Data-in timeout */
+    if (isr & SDH_INTSTS_DITOIF_Msk)
+    {
+        sdh_base->INTSTS |= SDH_INTSTS_DITOIF_Msk;
+    }
+
+    /* Response-in timeout interrupt */
+    if (isr & SDH_INTSTS_RTOIF_Msk)
+    {
+        sdh_base->INTSTS |= SDH_INTSTS_RTOIF_Msk;
+    }
+}
+
+#if defined(BSP_USING_SDH0)
+void SDH0_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    nu_sdh_isr(&nu_sdh_arr[SDH0_IDX]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+/* RT-Thread Device Driver Interface */
+static rt_err_t nu_sdh_init(rt_device_t dev)
+{
+    return RT_EOK;
+}
+
+static rt_err_t nu_sdh_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    nu_sdh_t sdh = (nu_sdh_t)dev;
+
+    RT_ASSERT(dev != RT_NULL);
+
+    return (SDH_Probe(sdh->base) == 0) ? RT_EOK :  -(RT_ERROR);
+}
+
+static rt_err_t nu_sdh_close(rt_device_t dev)
+{
+    return RT_EOK;
+}
+
+static rt_size_t nu_sdh_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t blk_nb)
+{
+    rt_uint32_t ret = 0;
+    nu_sdh_t sdh = (nu_sdh_t)dev;
+
+    RT_ASSERT(dev != RT_NULL);
+    RT_ASSERT(buffer != RT_NULL);
+
+    rt_sem_take(&sdh->lock, RT_WAITING_FOREVER);
+
+    /* Check alignment. */
+    if (((uint32_t)buffer & 0x03) != 0)
+    {
+        /* Non-aligned. */
+        uint32_t i;
+        uint8_t *copy_buffer = (uint8_t *)buffer;
+
+        sdh->pbuf = rt_malloc(SDH_BLOCK_SIZE);
+        if (sdh->pbuf == RT_NULL)
+            goto exit_nu_sdh_read;
+
+        for (i = 0; i < blk_nb; i++)
+        {
+            /* Read to temp buffer from specified sector. */
+            ret = SDH_Read(sdh->base, &sdh->pbuf[0], pos, 1);
+            if (ret != Successful)
+                goto exit_nu_sdh_read;
+
+            /* Move to user's buffer */
+            NU_SDH_MEMCPY((void *)copy_buffer, (void *)&sdh->pbuf[0], SDH_BLOCK_SIZE);
+
+            pos ++;
+            copy_buffer += SDH_BLOCK_SIZE;
+        }
+    }
+    else
+    {
+        /* Read to user's buffer from specified sector. */
+        ret = SDH_Read(sdh->base, (uint8_t *)buffer, pos, blk_nb);
+    }
+
+exit_nu_sdh_read:
+
+    if (sdh->pbuf)
+    {
+        rt_free(sdh->pbuf);
+        sdh->pbuf = RT_NULL;
+    }
+
+    rt_sem_release(&sdh->lock);
+
+    if (ret == Successful)
+        return blk_nb;
+
+    rt_kprintf("Read failed: %d, buffer 0x%08x\n", ret, buffer);
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
+}
+
+static rt_size_t nu_sdh_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t blk_nb)
+{
+    rt_uint32_t ret = 0;
+    nu_sdh_t sdh = (nu_sdh_t)dev;
+
+    RT_ASSERT(dev != RT_NULL);
+    RT_ASSERT(buffer != RT_NULL);
+
+    rt_sem_take(&sdh->lock, RT_WAITING_FOREVER);
+
+    /* Check alignment. */
+    if (((uint32_t)buffer & 0x03) != 0)
+    {
+        /* Non-aligned. */
+        uint32_t i;
+        uint8_t *copy_buffer = (uint8_t *)buffer;
+
+        sdh->pbuf = rt_malloc(SDH_BLOCK_SIZE);
+        if (sdh->pbuf == RT_NULL)
+            goto exit_nu_sdh_write;
+
+        for (i = 0; i < blk_nb; i++)
+        {
+            NU_SDH_MEMCPY((void *)&sdh->pbuf[0], copy_buffer, SDH_BLOCK_SIZE);
+
+            ret = SDH_Write(sdh->base, (uint8_t *)&sdh->pbuf[0], pos, 1);
+            if (ret != Successful)
+                goto exit_nu_sdh_write;
+
+            pos++;
+            copy_buffer += SDH_BLOCK_SIZE;
+        }
+    }
+    else
+    {
+        /* Write to device directly. */
+        ret = SDH_Write(sdh->base, (uint8_t *)buffer, pos, blk_nb);
+    }
+
+exit_nu_sdh_write:
+
+    if (sdh->pbuf)
+    {
+        rt_free(sdh->pbuf);
+        sdh->pbuf = RT_NULL;
+    }
+
+    rt_sem_release(&sdh->lock);
+
+    if (ret == Successful) return blk_nb;
+
+    rt_kprintf("write failed: %d, buffer 0x%08x\n", ret, buffer);
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
+}
+
+static rt_err_t nu_sdh_control(rt_device_t dev, int cmd, void *args)
+{
+    nu_sdh_t sdh = (nu_sdh_t)dev;
+
+    RT_ASSERT(dev != RT_NULL);
+
+    if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME)
+    {
+        SDH_INFO_T *sdh_info = sdh->info;
+
+        struct rt_device_blk_geometry *geometry;
+
+        geometry = (struct rt_device_blk_geometry *)args;
+        if (geometry == RT_NULL) return -RT_ERROR;
+
+        geometry->bytes_per_sector = sdh_info->sectorSize;
+        geometry->block_size = sdh_info->sectorSize;
+        geometry->sector_count = sdh_info->totalSectorN;
+    }
+
+    return RT_EOK;
+}
+
+
+static int rt_hw_sdh_init(void)
+{
+    int i;
+    rt_err_t ret = RT_EOK;
+    rt_uint32_t flags = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE;
+
+    rt_event_init(&sdh_event, "sdh_event", RT_IPC_FLAG_FIFO);
+
+    for (i = (SDH_START + 1); i < SDH_CNT; i++)
+    {
+        /* Register sdcard device */
+        nu_sdh_arr[i].dev.type  = RT_Device_Class_Block;
+        nu_sdh_arr[i].dev.init  = nu_sdh_init;
+        nu_sdh_arr[i].dev.open  = nu_sdh_open;
+        nu_sdh_arr[i].dev.close = nu_sdh_close;
+        nu_sdh_arr[i].dev.read  = nu_sdh_read;
+        nu_sdh_arr[i].dev.write = nu_sdh_write;
+        nu_sdh_arr[i].dev.control = nu_sdh_control;
+
+        /* Private */
+        nu_sdh_arr[i].dev.user_data = (void *)&nu_sdh_arr[i];
+
+        rt_sem_init(&nu_sdh_arr[i].lock, "sdhlock", 1, RT_IPC_FLAG_FIFO);
+
+        SDH_Open(nu_sdh_arr[i].base, CardDetect_From_GPIO);
+
+        /* Enable NVIC IRQ */
+        if (nu_sdh_arr[i].base == SDH0)
+            NVIC_EnableIRQ(SDH0_IRQn);
+
+        nu_sdh_arr[i].pbuf = RT_NULL;
+        ret = rt_device_register(&nu_sdh_arr[i].dev, nu_sdh_arr[i].name, flags);
+        RT_ASSERT(ret == RT_EOK);
+    }
+
+    return (int)ret;
+}
+INIT_BOARD_EXPORT(rt_hw_sdh_init);
+
+#if defined(NU_SDH_HOTPLUG)
+static rt_bool_t nu_sdh_hotplug_is_mounted(const char *mounting_path)
+{
+    rt_bool_t ret = RT_FALSE;
+
+#if defined(RT_USING_DFS)
+
+    struct dfs_filesystem *psFS = dfs_filesystem_lookup(mounting_path);
+    if (psFS == RT_NULL)
+    {
+        goto exit_nu_sdh_hotplug_is_mounted;
+    }
+    else if (!rt_memcmp(psFS->path, mounting_path, rt_strlen(mounting_path)))
+    {
+        ret = RT_TRUE;
+    }
+    else
+    {
+        ret = RT_FALSE;
+    }
+
+#endif
+
+exit_nu_sdh_hotplug_is_mounted:
+
+    return ret;
+}
+static rt_err_t nu_sdh_hotplug_mount(nu_sdh_t sdh)
+{
+    rt_err_t ret = RT_ERROR;
+    DIR *t;
+
+#if defined(RT_USING_DFS)
+
+    if (nu_sdh_hotplug_is_mounted(sdh->mounted_point) == RT_TRUE)
+    {
+        ret = RT_EOK;
+        goto exit_nu_sdh_hotplug_mount;
+    }
+
+    /* Check the SD folder path is valid. */
+    if ((t =  opendir(sdh->mounted_point)) != RT_NULL)
+    {
+        closedir(t);
+    }
+#if !defined(NU_SDH_MOUNT_ON_ROOT)
+    else
+    {
+
+        /* Check the ROOT path is valid. */
+        if ((t =  opendir(NU_SDH_MOUNTPOINT_ROOT)) != RT_NULL)
+        {
+            closedir(t);
+        }
+        else if ((ret = mkdir(NU_SDH_MOUNTPOINT_ROOT, 0)) != RT_EOK)
+        {
+            rt_kprintf("Failed to mkdir %s\n", NU_SDH_MOUNTPOINT_ROOT);
+            goto exit_nu_sdh_hotplug_mount;
+        }
+
+        if ((ret = mkdir(sdh->mounted_point, 0)) != RT_EOK)
+        {
+            rt_kprintf("Failed to mkdir %s\n", sdh->mounted_point);
+            goto exit_nu_sdh_hotplug_mount;
+        }
+
+    } //else
+#endif
+
+    if ((ret = dfs_mount(sdh->name, sdh->mounted_point, "elm", 0, 0)) == 0)
+    {
+        rt_kprintf("Mounted %s on %s\n", sdh->name, sdh->mounted_point);
+    }
+    else
+    {
+        rt_kprintf("Failed to mount %s on %s\n", sdh->name, sdh->mounted_point);
+        ret = RT_ERROR;
+    }
+
+exit_nu_sdh_hotplug_mount:
+
+#endif
+    return -(ret);
+}
+
+static rt_err_t nu_sdh_hotplug_unmount(nu_sdh_t sdh)
+{
+    rt_err_t ret = RT_ERROR;
+
+#if defined(RT_USING_DFS)
+    if (nu_sdh_hotplug_is_mounted(sdh->mounted_point) == RT_FALSE)
+    {
+        ret = RT_EOK;
+        goto exit_nu_sdh_hotplug_unmount;
+    }
+
+    ret = dfs_unmount(sdh->mounted_point);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("Failed to unmount %s.\n", sdh->mounted_point);
+    }
+    else
+    {
+        rt_kprintf("Succeed to unmount %s.\n", sdh->mounted_point);
+        ret = RT_EOK;
+    }
+#endif
+
+exit_nu_sdh_hotplug_unmount:
+
+    return -(ret);
+}
+
+static void nu_card_detector(nu_sdh_t sdh)
+{
+    SDH_T *sdh_base = sdh->base;
+    unsigned int volatile isr = sdh_base->INTSTS;
+    if (isr & SDH_INTSTS_CDSTS_Msk)
+    {
+        /* Card removed */
+        sdh->info->IsCardInsert = FALSE;   // SDISR_CD_Card = 1 means card remove for GPIO mode
+        rt_memset((void *)sdh->info, 0, sizeof(SDH_INFO_T));
+        nu_sdh_hotplug_unmount(sdh);
+    }
+    else
+    {
+        SDH_Open(sdh_base, CardDetect_From_GPIO);
+        if (!SDH_Probe(sdh_base))
+        {
+            /* Card inserted */
+            nu_sdh_hotplug_mount(sdh);
+        }
+    }
+}
+
+static void sdh_hotplugger(void *param)
+{
+    rt_uint32_t e;
+    int i;
+
+    for (i = (SDH_START + 1); i < SDH_CNT; i++)
+    {
+        if (SDH_IS_CARD_PRESENT(nu_sdh_arr[i].base))
+        {
+            nu_sdh_hotplug_mount(&nu_sdh_arr[i]);
+        }
+    }
+
+    while (1)
+    {
+        if (rt_event_recv(&sdh_event, (NU_SDH_CARD_EVENT_ALL),
+                          RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
+                          RT_WAITING_FOREVER, &e) == RT_EOK)
+        {
+            /* Debounce */
+            rt_thread_delay(200);
+            switch (e)
+            {
+#if defined(BSP_USING_SDH0)
+            case NU_SDH_CARD_DETECTED_SD0:
+                nu_card_detector(&nu_sdh_arr[SDH0_IDX]);
+                break;
+#endif
+            default:
+                break;
+
+            } //switch(e)
+
+        } //if
+
+    } /* while(1) */
+}
+
+int mnt_init_sdcard_hotplug(void)
+{
+    rt_thread_init(&sdh_tid, "hotplug", sdh_hotplugger, NULL, sdh_stack, sizeof(sdh_stack), RT_THREAD_PRIORITY_MAX - 2, 10);
+    rt_thread_startup(&sdh_tid);
+
+    return 0;
+}
+INIT_ENV_EXPORT(mnt_init_sdcard_hotplug);
+#endif
+
+#endif //#if defined(BSP_USING_SDH)
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_slcd.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_slcd.c
new file mode 100644
index 0000000000..3a673983a0
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_slcd.c
@@ -0,0 +1,233 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author       Notes
+* 2020-11-11      Wayne        First version
+*
+******************************************************************************/
+
+#include 
+
+#if defined(BSP_USING_SLCD)
+
+#include 
+#include 
+#include "NuMicro.h"
+#include 
+
+/* Private define ---------------------------------------------------------------*/
+#define DBG_ENABLE
+#define DBG_LEVEL DBG_LOG
+#define DBG_SECTION_NAME  "slcd"
+#define DBG_COLOR
+#include 
+
+enum
+{
+    SLCD_START = -1,
+    SLCD_IDX,
+    SLCD_CNT
+};
+#define LCD_ALPHABET_NUM    7
+
+/* Private typedef --------------------------------------------------------------*/
+struct nu_slcd
+{
+    struct rt_device dev;
+    char *name;
+    LCD_T *base;
+    uint32_t rst;
+    rt_mutex_t lock;
+};
+typedef struct nu_slcd *nu_slcd_t;
+
+/* Private functions ------------------------------------------------------------*/
+
+/* Public functions ------------------------------------------------------------*/
+
+/* Private variables ------------------------------------------------------------*/
+static struct nu_slcd nu_slcd_arr [] =
+{
+    {
+        .name = "slcd",
+        .base = LCD,
+        .rst = LCD_RST,
+    }
+}; /* nu_slcd_arr */
+
+static S_LCD_CFG_T g_SLCDCfg =
+{
+    __LXT,                      /*!< LCD clock source frequency */
+    LCD_COM_DUTY_1_8,           /*!< COM duty */
+    LCD_BIAS_LV_1_4,            /*!< Bias level */
+    64,                         /*!< Operation frame rate */
+    LCD_WAVEFORM_TYPE_A_NORMAL, /*!< Waveform type */
+    LCD_DISABLE_ALL_INT,        /*!< Interrupt source */
+    LCD_LOW_DRIVING_AND_BUF_ON, /*!< Driving mode */
+    LCD_VOLTAGE_SOURCE_VLCD,    /*!< Voltage source */
+};
+
+static rt_err_t nu_slcd_open(struct rt_device *dev, rt_uint16_t oflag)
+{
+    if (dev->ref_count == 0)
+    {
+        nu_slcd_t psNuSLcd = (nu_slcd_t)dev;
+
+        /* Reset LCD module */
+        SYS_ResetModule(psNuSLcd->rst);
+
+        uint32_t u32ActiveFPS = LCD_Open(&g_SLCDCfg);
+
+        /* LCD Initialize and calculate real frame rate */
+        LOG_I("Working frame rate is %dHz on Type-%c.\n\n", u32ActiveFPS, (g_SLCDCfg.u32WaveformType == LCD_PCTL_TYPE_Msk) ? 'B' : 'A');
+
+        /* Enable LCD display */
+        LCD_ENABLE_DISPLAY();
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t nu_slcd_close(struct rt_device *dev)
+{
+    if (dev->ref_count == 0)
+    {
+        /* Disable LCD display */
+        LCD_DISABLE_DISPLAY();
+    }
+    return RT_EOK;
+}
+
+static rt_size_t nu_slcd_write(struct rt_device *dev,
+                               rt_off_t          pos,
+                               const void       *buffer,
+                               rt_size_t         size)
+{
+    nu_slcd_pixel_t psSlcdPixel;
+    nu_slcd_t psNuSLCD = (nu_slcd_t)dev;
+
+    RT_ASSERT(buffer != RT_NULL);
+    RT_ASSERT(size == sizeof(struct nu_slcd_pixel));
+
+    psSlcdPixel = (nu_slcd_pixel_t)buffer;
+
+    /* Critical section */
+    rt_mutex_take(psNuSLCD->lock, RT_WAITING_FOREVER);
+    LCD_SetPixel(psSlcdPixel->m_u32Com, psSlcdPixel->m_u32Seg, psSlcdPixel->m_u32OnFlag);
+    rt_mutex_release(psNuSLCD->lock);
+
+    return size;
+}
+
+static rt_err_t nu_slcd_control(struct rt_device *dev,
+                                int              cmd,
+                                void             *args)
+{
+    rt_err_t ret = RT_EOK;
+    switch (cmd)
+    {
+    case NU_SLCD_CMD_SET_LCD_CFG:
+    {
+        S_LCD_CFG_T *psLCDCfg;
+
+        RT_ASSERT(args != RT_NULL);
+        psLCDCfg = (S_LCD_CFG_T *)args;
+
+        rt_memcpy((void *)&g_SLCDCfg, (void *)psLCDCfg, sizeof(S_LCD_CFG_T));
+    }
+    break;
+
+    case NU_SLCD_CMD_SET_CP_VOLTAGE:
+    {
+        /*
+        LCD_CP_VOLTAGE_LV_0  2.6 V
+        LCD_CP_VOLTAGE_LV_1  2.8 V
+        LCD_CP_VOLTAGE_LV_2  3.0 V
+        LCD_CP_VOLTAGE_LV_3  3.2 V
+        LCD_CP_VOLTAGE_LV_4  3.4 V
+        LCD_CP_VOLTAGE_LV_5  3.6 V
+        */
+        uint32_t u32CPVol;
+        RT_ASSERT(args != RT_NULL);
+
+        u32CPVol = *((uint32_t *)args) ;
+        if ((u32CPVol >> LCD_PCTL_CPVSEL_Pos) <= (LCD_CP_VOLTAGE_LV_5 >> LCD_PCTL_CPVSEL_Pos))
+        {
+            LCD_SET_CP_VOLTAGE(u32CPVol);
+        }
+        else
+        {
+            ret = -RT_ERROR;
+        }
+    }
+    break;
+    default:
+        return -RT_EINVAL;
+    }
+    return ret;
+}
+
+#ifdef RT_USING_DEVICE_OPS
+const static struct rt_device_ops slcd_ops =
+{
+    RT_NULL,
+    nu_slcd_open,
+    nu_slcd_close,
+    RT_NULL,
+    nu_slcd_write,
+    nu_slcd_control
+};
+#endif
+
+rt_err_t rt_hw_slcd_register(struct rt_device *device,
+                             const char              *name,
+                             rt_uint32_t              flag,
+                             void                    *data)
+{
+    RT_ASSERT(device != RT_NULL);
+
+    device->type        = RT_Device_Class_Char;
+    device->rx_indicate = RT_NULL;
+    device->tx_complete = RT_NULL;
+
+#ifdef RT_USING_DEVICE_OPS
+    device->ops         = &slcd_ops;
+#else
+    device->init        = RT_NULL;
+    device->open        = nu_slcd_open;
+    device->close       = nu_slcd_close;
+    device->read        = RT_NULL;
+    device->write       = nu_slcd_write;
+    device->control     = nu_slcd_control;
+#endif
+    device->user_data   = data;
+
+    /* register a character device */
+    return rt_device_register(device, name, flag);
+}
+
+/**
+ * Hardware SLCD Initialization
+ */
+static int rt_hw_slcd_init(void)
+{
+    int i;
+    rt_err_t ret = RT_EOK;
+
+    for (i = (SLCD_START + 1); i < SLCD_CNT; i++)
+    {
+        ret = rt_hw_slcd_register(&nu_slcd_arr[i].dev, nu_slcd_arr[i].name, RT_DEVICE_FLAG_RDWR, NULL);
+        RT_ASSERT(ret == RT_EOK);
+        nu_slcd_arr[i].lock = rt_mutex_create(nu_slcd_arr[i].name, RT_IPC_FLAG_FIFO);
+        RT_ASSERT(nu_slcd_arr[i].lock != RT_NULL);
+    }
+
+    return (int)ret;
+}
+INIT_DEVICE_EXPORT(rt_hw_slcd_init);
+
+#endif //#if defined(BSP_USING_SLCD)
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_slcd.h b/bsp/nuvoton/libraries/m2354/rtt_port/drv_slcd.h
new file mode 100644
index 0000000000..46ab04a50f
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_slcd.h
@@ -0,0 +1,34 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-11-11      Wayne            First version
+*
+******************************************************************************/
+
+#ifndef __DRV_SLCD_H__
+#define __DRV_SLCD_H__
+
+#include 
+#include "NuMicro.h"
+
+struct nu_slcd_pixel
+{
+    uint32_t m_u32Com;
+    uint32_t m_u32Seg;
+    uint32_t m_u32OnFlag;
+};
+typedef struct nu_slcd_pixel *nu_slcd_pixel_t;
+
+typedef enum
+{
+    NU_SLCD_CMD_SET_LCD_CFG,       /* SLCD configuration */
+    NU_SLCD_CMD_SET_CP_VOLTAGE,    /* Internal charge pump voltage */
+    NU_SLCD_CMD_CNT
+} NU_SLCD_CMD;
+
+#endif /* __DRV_SLCD_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_softi2c.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_softi2c.c
new file mode 100644
index 0000000000..a2a7ac7cc5
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_softi2c.c
@@ -0,0 +1,217 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-6-28       YCHuang12        First version
+*
+******************************************************************************/
+
+#include 
+
+#if (defined(BSP_USING_SOFT_I2C) && defined(BSP_USING_GPIO) && defined(RT_USING_I2C_BITOPS) && defined(RT_USING_I2C) && defined(RT_USING_PIN))
+
+#include 
+#include 
+#include 
+#include "NuMicro.h"
+
+/* Private define ---------------------------------------------------------------*/
+#define LOG_TAG          "drv.softi2c"
+#define DBG_ENABLE
+#define DBG_SECTION_NAME LOG_TAG
+#define DBG_LEVEL        DBG_INFO
+#include 
+
+#ifdef BSP_USING_SOFT_I2C0
+#define NU_SOFT_I2C0_BUS_CONFIG                          \
+    {                                                    \
+        .scl = BSP_SOFT_I2C0_SCL_PIN,                    \
+        .sda = BSP_SOFT_I2C0_SDA_PIN,                    \
+        .bus_name = "softi2c0",                         \
+    }
+#endif
+
+#ifdef BSP_USING_SOFT_I2C1
+#define NU_SOFT_I2C1_BUS_CONFIG                          \
+    {                                                    \
+        .scl = BSP_SOFT_I2C1_SCL_PIN,                    \
+        .sda = BSP_SOFT_I2C1_SDA_PIN,                    \
+        .bus_name = "softi2c1",                         \
+    }
+#endif
+
+#if (!defined(BSP_USING_SOFT_I2C0) && !defined(BSP_USING_SOFT_I2C1))
+    #error "Please define at least one BSP_USING_SOFT_I2Cx"
+    /* this driver can be disabled at menuconfig ? RT-Thread Components ? Device Drivers */
+#endif
+
+/* Private typedef --------------------------------------------------------------*/
+/* soft i2c config class */
+struct nu_soft_i2c_config
+{
+    rt_uint8_t scl;
+    rt_uint8_t sda;
+    const char *bus_name;
+};
+/* soft i2c driver class */
+struct nu_soft_i2c
+{
+    struct rt_i2c_bit_ops ops;
+    struct rt_i2c_bus_device soft_i2c_bus;
+};
+
+/* Private functions ------------------------------------------------------------*/
+static void nu_soft_i2c_set_sda(void *data, rt_int32_t state);
+static void nu_soft_i2c_set_scl(void *data, rt_int32_t state);
+static rt_int32_t nu_soft_i2c_get_sda(void *data);
+static rt_int32_t nu_soft_i2c_get_scl(void *data);
+
+/* Private variables ------------------------------------------------------------*/
+static const struct nu_soft_i2c_config nu_soft_i2c_cfg[] =
+{
+#ifdef BSP_USING_SOFT_I2C0
+    NU_SOFT_I2C0_BUS_CONFIG,
+#endif
+#ifdef BSP_USING_SOFT_I2C1
+    NU_SOFT_I2C1_BUS_CONFIG,
+#endif
+};
+
+static struct nu_soft_i2c nu_soft_i2c_obj[sizeof(nu_soft_i2c_cfg) / sizeof(nu_soft_i2c_cfg[0])];
+
+static const struct rt_i2c_bit_ops nu_soft_i2c_bit_ops =
+{
+    .data     = RT_NULL,
+    .set_sda  = nu_soft_i2c_set_sda,
+    .set_scl  = nu_soft_i2c_set_scl,
+    .get_sda  = nu_soft_i2c_get_sda,
+    .get_scl  = nu_soft_i2c_get_scl,
+    .udelay   = rt_hw_us_delay,
+    .delay_us = 1,
+    .timeout  = 100
+};
+
+/* Functions define ------------------------------------------------------------*/
+
+/**
+ * This function initializes the soft i2c pin.
+ *
+ * @param soft i2c config class.
+ */
+static void nu_soft_i2c_gpio_init(const struct nu_soft_i2c_config *cfg)
+{
+    rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD);
+    rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD);
+
+    rt_pin_write(cfg->scl, PIN_HIGH);
+    rt_pin_write(cfg->sda, PIN_HIGH);
+}
+
+/**
+ * if i2c is locked, this function will unlock it
+ *
+ * @param soft i2c config class
+ *
+ * @return RT_EOK indicates successful unlock.
+ */
+static rt_err_t nu_soft_i2c_bus_unlock(const struct nu_soft_i2c_config *cfg)
+{
+    rt_int32_t i = 0;
+
+    if (PIN_LOW == rt_pin_read(cfg->sda))
+    {
+        while (i++ < 9)
+        {
+            rt_pin_write(cfg->scl, PIN_HIGH);
+            rt_hw_us_delay(100);
+            rt_pin_write(cfg->scl, PIN_LOW);
+            rt_hw_us_delay(100);
+        }
+    }
+    if (PIN_LOW == rt_pin_read(cfg->sda))
+    {
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+/**
+ * This function sets the sda pin.
+ *
+ * @param soft i2c config class.
+ * @param The sda pin state.
+ */
+static void nu_soft_i2c_set_sda(void *data, rt_int32_t state)
+{
+    struct nu_soft_i2c_config *cfg = (struct nu_soft_i2c_config *)data;
+
+    rt_pin_write(cfg->sda, state ? PIN_HIGH : PIN_LOW);
+}
+
+/**
+ * This function sets the scl pin.
+ *
+ * @param soft i2c config class.
+ * @param The scl pin state.
+ */
+static void nu_soft_i2c_set_scl(void *data, rt_int32_t state)
+{
+    struct nu_soft_i2c_config *cfg = (struct nu_soft_i2c_config *)data;
+
+    rt_pin_write(cfg->scl, state ? PIN_HIGH : PIN_LOW);
+}
+
+/**
+ * This function gets the sda pin state.
+ *
+ * @param The sda pin state.
+ */
+static rt_int32_t nu_soft_i2c_get_sda(void *data)
+{
+    struct nu_soft_i2c_config *cfg = (struct nu_soft_i2c_config *)data;
+    return rt_pin_read(cfg->sda);
+}
+
+/**
+ * This function gets the scl pin state.
+ *
+ * @param The scl pin state.
+ */
+static rt_int32_t nu_soft_i2c_get_scl(void *data)
+{
+    struct nu_soft_i2c_config *cfg = (struct nu_soft_i2c_config *)data;
+    return rt_pin_read(cfg->scl);
+}
+
+/* Soft I2C initialization function */
+int rt_soft_i2c_init(void)
+{
+    rt_size_t obj_num = sizeof(nu_soft_i2c_obj) / sizeof(struct nu_soft_i2c);
+    rt_err_t result;
+
+    for (int i = 0; i < obj_num; i++)
+    {
+        nu_soft_i2c_obj[i].ops = nu_soft_i2c_bit_ops;
+        nu_soft_i2c_obj[i].ops.data = (void *)&nu_soft_i2c_cfg[i];
+        nu_soft_i2c_obj[i].soft_i2c_bus.priv = &nu_soft_i2c_obj[i].ops;
+        nu_soft_i2c_gpio_init(&nu_soft_i2c_cfg[i]);
+        result = rt_i2c_bit_add_bus(&nu_soft_i2c_obj[i].soft_i2c_bus, nu_soft_i2c_cfg[i].bus_name);
+        RT_ASSERT(result == RT_EOK);
+        nu_soft_i2c_bus_unlock(&nu_soft_i2c_cfg[i]);
+
+        LOG_D("software simulation %s init done, pin scl: %d, pin sda %d",
+              nu_soft_i2c_cfg[i].bus_name,
+              nu_soft_i2c_cfg[i].scl,
+              nu_soft_i2c_cfg[i].sda);
+    }
+
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_soft_i2c_init);
+
+#endif //#if (defined(BSP_USING_SOFT_I2C) && defined(BSP_USING_GPIO) && defined(RT_USING_I2C_BITOPS) && defined(RT_USING_I2C) && defined(RT_USING_PIN))
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_spi.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_spi.c
new file mode 100644
index 0000000000..824736cf40
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_spi.c
@@ -0,0 +1,659 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-6-15       YHKuo            First version
+*
+******************************************************************************/
+#include 
+
+#if defined(BSP_USING_SPI)
+
+#define LOG_TAG                 "drv.spi"
+#define DBG_ENABLE
+#define DBG_SECTION_NAME        LOG_TAG
+#define DBG_LEVEL               DBG_INFO
+#define DBG_COLOR
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+
+
+/* Private define ---------------------------------------------------------------*/
+
+#ifndef NU_SPI_USE_PDMA_MIN_THRESHOLD
+    #define NU_SPI_USE_PDMA_MIN_THRESHOLD (128)
+#endif
+
+enum
+{
+    SPI_START = -1,
+#if defined(BSP_USING_SPI0)
+    SPI0_IDX,
+#endif
+#if defined(BSP_USING_SPI1)
+    SPI1_IDX,
+#endif
+#if defined(BSP_USING_SPI2)
+    SPI2_IDX,
+#endif
+#if defined(BSP_USING_SPI3)
+    SPI3_IDX,
+#endif
+    SPI_CNT
+};
+
+/* Private typedef --------------------------------------------------------------*/
+
+/* Private functions ------------------------------------------------------------*/
+static void nu_spi_transmission_with_poll(struct nu_spi *spi_bus,
+        uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word);
+static int nu_spi_register_bus(struct nu_spi *spi_bus, const char *name);
+static rt_uint32_t nu_spi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message);
+static rt_err_t nu_spi_bus_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration);
+
+#if defined(BSP_USING_SPI_PDMA)
+    static void nu_pdma_spi_rx_cb(void *pvUserData, uint32_t u32EventFilter);
+    static rt_err_t nu_pdma_spi_rx_config(struct nu_spi *spi_bus, uint8_t *pu8Buf, int32_t i32RcvLen, uint8_t bytes_per_word);
+    static rt_err_t nu_pdma_spi_tx_config(struct nu_spi *spi_bus, const uint8_t *pu8Buf, int32_t i32SndLen, uint8_t bytes_per_word);
+    static rt_size_t nu_spi_pdma_transmit(struct nu_spi *spi_bus, const uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word);
+#endif
+/* Public functions -------------------------------------------------------------*/
+void nu_spi_transfer(struct nu_spi *spi_bus, uint8_t *tx, uint8_t *rx, int length, uint8_t bytes_per_word);
+void nu_spi_drain_rxfifo(SPI_T *spi_base);
+
+/* Private variables ------------------------------------------------------------*/
+static struct rt_spi_ops nu_spi_poll_ops =
+{
+    .configure = nu_spi_bus_configure,
+    .xfer      = nu_spi_bus_xfer,
+};
+
+static struct nu_spi nu_spi_arr [] =
+{
+#if defined(BSP_USING_SPI0)
+    {
+        .name = "spi0",
+        .spi_base = SPI0,
+
+#if defined(BSP_USING_SPI_PDMA)
+#if defined(BSP_USING_SPI0_PDMA)
+        .pdma_perp_tx = PDMA_SPI0_TX,
+        .pdma_perp_rx = PDMA_SPI0_RX,
+#else
+        .pdma_perp_tx = NU_PDMA_UNUSED,
+        .pdma_perp_rx = NU_PDMA_UNUSED,
+#endif
+#endif
+    },
+#endif
+#if defined(BSP_USING_SPI1)
+    {
+        .name = "spi1",
+        .spi_base = SPI1,
+
+#if defined(BSP_USING_SPI_PDMA)
+#if defined(BSP_USING_SPI1_PDMA)
+        .pdma_perp_tx = PDMA_SPI1_TX,
+        .pdma_perp_rx = PDMA_SPI1_RX,
+#else
+        .pdma_perp_tx = NU_PDMA_UNUSED,
+        .pdma_perp_rx = NU_PDMA_UNUSED,
+#endif
+#endif
+
+    },
+#endif
+#if defined(BSP_USING_SPI2)
+    {
+        .name = "spi2",
+        .spi_base = SPI2,
+
+#if defined(BSP_USING_SPI_PDMA)
+#if defined(BSP_USING_SPI2_PDMA)
+        .pdma_perp_tx = PDMA_SPI2_TX,
+        .pdma_perp_rx = PDMA_SPI2_RX,
+#else
+        .pdma_perp_tx = NU_PDMA_UNUSED,
+        .pdma_perp_rx = NU_PDMA_UNUSED,
+#endif
+#endif
+
+    },
+#endif
+#if defined(BSP_USING_SPI3)
+    {
+        .name = "spi3",
+        .spi_base = SPI3,
+
+#if defined(BSP_USING_SPI_PDMA)
+#if defined(BSP_USING_SPI3_PDMA)
+        .pdma_perp_tx = PDMA_SPI3_TX,
+        .pdma_perp_rx = PDMA_SPI3_RX,
+#else
+        .pdma_perp_tx = NU_PDMA_UNUSED,
+        .pdma_perp_rx = NU_PDMA_UNUSED,
+#endif
+#endif
+
+    },
+#endif
+    {0}
+}; /* spi nu_spi */
+
+static rt_err_t nu_spi_bus_configure(struct rt_spi_device *device,
+                                     struct rt_spi_configuration *configuration)
+{
+    struct nu_spi *spi_bus;
+    uint32_t u32SPIMode;
+    uint32_t u32BusClock;
+    rt_err_t ret = RT_EOK;
+
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(configuration != RT_NULL);
+
+    spi_bus = (struct nu_spi *) device->bus;
+
+    /* Check mode */
+    switch (configuration->mode & RT_SPI_MODE_3)
+    {
+    case RT_SPI_MODE_0:
+        u32SPIMode = SPI_MODE_0;
+        break;
+    case RT_SPI_MODE_1:
+        u32SPIMode = SPI_MODE_1;
+        break;
+    case RT_SPI_MODE_2:
+        u32SPIMode = SPI_MODE_2;
+        break;
+    case RT_SPI_MODE_3:
+        u32SPIMode = SPI_MODE_3;
+        break;
+    default:
+        ret = RT_EIO;
+        goto exit_nu_spi_bus_configure;
+    }
+
+    /* Check data width */
+    if (!(configuration->data_width == 8  ||
+            configuration->data_width == 16 ||
+            configuration->data_width == 24 ||
+            configuration->data_width == 32))
+    {
+        ret = RT_EINVAL;
+        goto exit_nu_spi_bus_configure;
+    }
+
+    /* Try to set clock and get actual spi bus clock */
+    u32BusClock = SPI_SetBusClock(spi_bus->spi_base, configuration->max_hz);
+    if (configuration->max_hz > u32BusClock)
+    {
+        LOG_W("%s clock max frequency is %dHz (!= %dHz)\n", spi_bus->name, u32BusClock, configuration->max_hz);
+        configuration->max_hz = u32BusClock;
+    }
+
+    /* Need to initialize new configuration? */
+    if (rt_memcmp(configuration, &spi_bus->configuration, sizeof(*configuration)) != 0)
+    {
+        rt_memcpy(&spi_bus->configuration, configuration, sizeof(*configuration));
+
+        SPI_Open(spi_bus->spi_base, SPI_MASTER, u32SPIMode, configuration->data_width, u32BusClock);
+
+        if (configuration->mode & RT_SPI_CS_HIGH)
+        {
+            /* Set CS pin to LOW */
+            SPI_SET_SS_LOW(spi_bus->spi_base);
+        }
+        else
+        {
+            /* Set CS pin to HIGH */
+            SPI_SET_SS_HIGH(spi_bus->spi_base);
+        }
+
+        if (configuration->mode & RT_SPI_MSB)
+        {
+            /* Set sequence to MSB first */
+            SPI_SET_MSB_FIRST(spi_bus->spi_base);
+        }
+        else
+        {
+            /* Set sequence to LSB first */
+            SPI_SET_LSB_FIRST(spi_bus->spi_base);
+        }
+    }
+
+    /* Clear SPI RX FIFO */
+    nu_spi_drain_rxfifo(spi_bus->spi_base);
+
+exit_nu_spi_bus_configure:
+
+    return -(ret);
+}
+
+#if defined(BSP_USING_SPI_PDMA)
+static void nu_pdma_spi_rx_cb(void *pvUserData, uint32_t u32EventFilter)
+{
+    rt_err_t result;
+    struct nu_spi *spi_bus = (struct nu_spi *)pvUserData;
+
+    RT_ASSERT(spi_bus != RT_NULL);
+
+    result = rt_sem_release(spi_bus->m_psSemBus);
+    RT_ASSERT(result == RT_EOK);
+}
+static rt_err_t nu_pdma_spi_rx_config(struct nu_spi *spi_bus, uint8_t *pu8Buf, int32_t i32RcvLen, uint8_t bytes_per_word)
+{
+    rt_err_t result = RT_EOK;
+    rt_uint8_t *dst_addr = NULL;
+    nu_pdma_memctrl_t memctrl = eMemCtl_Undefined;
+
+    /* Get base address of spi register */
+    SPI_T *spi_base = spi_bus->spi_base;
+
+    rt_uint8_t spi_pdma_rx_chid = spi_bus->pdma_chanid_rx;
+
+    result = nu_pdma_callback_register(spi_pdma_rx_chid,
+                                       nu_pdma_spi_rx_cb,
+                                       (void *)spi_bus,
+                                       NU_PDMA_EVENT_TRANSFER_DONE);
+    if (result != RT_EOK)
+    {
+        goto exit_nu_pdma_spi_rx_config;
+    }
+
+    if (pu8Buf == RT_NULL)
+    {
+        memctrl  = eMemCtl_SrcFix_DstFix;
+        dst_addr = (rt_uint8_t *) &spi_bus->dummy;
+    }
+    else
+    {
+        memctrl  = eMemCtl_SrcFix_DstInc;
+        dst_addr = pu8Buf;
+    }
+
+    result = nu_pdma_channel_memctrl_set(spi_pdma_rx_chid, memctrl);
+    if (result != RT_EOK)
+    {
+        goto exit_nu_pdma_spi_rx_config;
+    }
+
+    result = nu_pdma_transfer(spi_pdma_rx_chid,
+                              bytes_per_word * 8,
+                              (uint32_t)&spi_base->RX,
+                              (uint32_t)dst_addr,
+                              i32RcvLen / bytes_per_word,
+                              0);
+exit_nu_pdma_spi_rx_config:
+
+    return result;
+}
+
+static rt_err_t nu_pdma_spi_tx_config(struct nu_spi *spi_bus, const uint8_t *pu8Buf, int32_t i32SndLen, uint8_t bytes_per_word)
+{
+    rt_err_t result = RT_EOK;
+    rt_uint8_t *src_addr = NULL;
+    nu_pdma_memctrl_t memctrl = eMemCtl_Undefined;
+
+    /* Get base address of spi register */
+    SPI_T *spi_base = spi_bus->spi_base;
+
+    rt_uint8_t spi_pdma_tx_chid = spi_bus->pdma_chanid_tx;
+
+    if (pu8Buf == RT_NULL)
+    {
+        spi_bus->dummy = 0;
+        memctrl = eMemCtl_SrcFix_DstFix;
+        src_addr = (rt_uint8_t *)&spi_bus->dummy;
+    }
+    else
+    {
+        memctrl = eMemCtl_SrcInc_DstFix;
+        src_addr = (rt_uint8_t *)pu8Buf;
+    }
+
+    result = nu_pdma_channel_memctrl_set(spi_pdma_tx_chid, memctrl);
+    if (result != RT_EOK)
+    {
+        goto exit_nu_pdma_spi_tx_config;
+    }
+
+    result = nu_pdma_transfer(spi_pdma_tx_chid,
+                              bytes_per_word * 8,
+                              (uint32_t)src_addr,
+                              (uint32_t)&spi_base->TX,
+                              i32SndLen / bytes_per_word,
+                              0);
+exit_nu_pdma_spi_tx_config:
+
+    return result;
+}
+
+
+/**
+ * SPI PDMA transfer
+ */
+static rt_size_t nu_spi_pdma_transmit(struct nu_spi *spi_bus, const uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word)
+{
+    rt_err_t result = RT_EOK;
+    rt_uint32_t u32Offset = 0;
+    rt_uint32_t u32TransferCnt = length / bytes_per_word;
+    rt_uint32_t u32TxCnt = 0;
+
+    /* Get base address of spi register */
+    SPI_T *spi_base = spi_bus->spi_base;
+
+    do
+    {
+        u32TxCnt = (u32TransferCnt > NU_PDMA_MAX_TXCNT) ? NU_PDMA_MAX_TXCNT : u32TransferCnt;
+        result = nu_pdma_spi_rx_config(spi_bus, (recv_addr == RT_NULL) ? recv_addr : &recv_addr[u32Offset], (u32TxCnt * bytes_per_word), bytes_per_word);
+        RT_ASSERT(result == RT_EOK);
+
+        result = nu_pdma_spi_tx_config(spi_bus, (send_addr == RT_NULL) ? send_addr : &send_addr[u32Offset], (u32TxCnt * bytes_per_word), bytes_per_word);
+        RT_ASSERT(result == RT_EOK);
+
+        /* Trigger TX/RX PDMA transfer. */
+        SPI_TRIGGER_TX_RX_PDMA(spi_base);
+
+        /* Wait RX-PDMA transfer done */
+        result = rt_sem_take(spi_bus->m_psSemBus, RT_WAITING_FOREVER);
+        RT_ASSERT(result == RT_EOK);
+
+        /* Stop TX/RX DMA transfer. */
+        SPI_DISABLE_TX_RX_PDMA(spi_base);
+
+        u32TransferCnt -= u32TxCnt;
+        u32Offset += u32TxCnt;
+
+    }
+    while (u32TransferCnt > 0);
+
+    return length;
+}
+
+rt_err_t nu_hw_spi_pdma_allocate(struct nu_spi *spi_bus)
+{
+    /* Allocate SPI_TX nu_dma channel */
+    if ((spi_bus->pdma_chanid_tx = nu_pdma_channel_allocate(spi_bus->pdma_perp_tx)) < 0)
+    {
+        goto exit_nu_hw_spi_pdma_allocate;
+    }
+    /* Allocate SPI_RX nu_dma channel */
+    else if ((spi_bus->pdma_chanid_rx = nu_pdma_channel_allocate(spi_bus->pdma_perp_rx)) < 0)
+    {
+        nu_pdma_channel_free(spi_bus->pdma_chanid_tx);
+        goto exit_nu_hw_spi_pdma_allocate;
+    }
+
+    spi_bus->m_psSemBus = rt_sem_create("spibus_sem", 0, RT_IPC_FLAG_FIFO);
+    RT_ASSERT(spi_bus->m_psSemBus != RT_NULL);
+
+    return RT_EOK;
+
+exit_nu_hw_spi_pdma_allocate:
+
+    return -(RT_ERROR);
+}
+#endif /* #if defined(BSP_USING_SPI_PDMA) */
+
+void nu_spi_drain_rxfifo(SPI_T *spi_base)
+{
+    while (SPI_IS_BUSY(spi_base));
+
+    // Drain SPI RX FIFO, make sure RX FIFO is empty
+    while (!SPI_GET_RX_FIFO_EMPTY_FLAG(spi_base))
+    {
+        SPI_ClearRxFIFO(spi_base);
+    }
+}
+
+static int nu_spi_read(SPI_T *spi_base, uint8_t *recv_addr, uint8_t bytes_per_word)
+{
+    int size = 0;
+
+    // Read RX data
+    if (!SPI_GET_RX_FIFO_EMPTY_FLAG(spi_base))
+    {
+        uint32_t val;
+        // Read data from SPI RX FIFO
+        switch (bytes_per_word)
+        {
+        case 4:
+            val = SPI_READ_RX(spi_base);
+            nu_set32_le(recv_addr, val);
+            break;
+        case 3:
+            val = SPI_READ_RX(spi_base);
+            nu_set24_le(recv_addr, val);
+            break;
+        case 2:
+            val = SPI_READ_RX(spi_base);
+            nu_set16_le(recv_addr, val);
+            break;
+        case 1:
+            *recv_addr = SPI_READ_RX(spi_base);
+            break;
+        default:
+            LOG_E("Data length is not supported.\n");
+            break;
+        }
+        size = bytes_per_word;
+    }
+    return size;
+}
+
+static int nu_spi_write(SPI_T *spi_base, const uint8_t *send_addr, uint8_t bytes_per_word)
+{
+    // Wait SPI TX send data
+    while (SPI_GET_TX_FIFO_FULL_FLAG(spi_base));
+
+    // Input data to SPI TX
+    switch (bytes_per_word)
+    {
+    case 4:
+        SPI_WRITE_TX(spi_base, nu_get32_le(send_addr));
+        break;
+    case 3:
+        SPI_WRITE_TX(spi_base, nu_get24_le(send_addr));
+        break;
+    case 2:
+        SPI_WRITE_TX(spi_base, nu_get16_le(send_addr));
+        break;
+    case 1:
+        SPI_WRITE_TX(spi_base, *((uint8_t *)send_addr));
+        break;
+    default:
+        LOG_E("Data length is not supported.\n");
+        break;
+    }
+
+    return bytes_per_word;
+}
+
+/**
+ * @brief SPI bus polling
+ * @param dev : The pointer of the specified SPI module.
+ * @param send_addr : Source address
+ * @param recv_addr : Destination address
+ * @param length    : Data length
+ */
+static void nu_spi_transmission_with_poll(struct nu_spi *spi_bus,
+        uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word)
+{
+    SPI_T *spi_base = spi_bus->spi_base;
+
+    // Write-only
+    if ((send_addr != RT_NULL) && (recv_addr == RT_NULL))
+    {
+        while (length > 0)
+        {
+            send_addr += nu_spi_write(spi_base, send_addr, bytes_per_word);
+            length -= bytes_per_word;
+        }
+    } // if (send_addr != RT_NULL && recv_addr == RT_NULL)
+    // Read-only
+    else if ((send_addr == RT_NULL) && (recv_addr != RT_NULL))
+    {
+        spi_bus->dummy = 0;
+        while (length > 0)
+        {
+            /* Input data to SPI TX FIFO */
+            length -= nu_spi_write(spi_base, (const uint8_t *)&spi_bus->dummy, bytes_per_word);
+
+            /* Read data from RX FIFO */
+            recv_addr += nu_spi_read(spi_base, recv_addr, bytes_per_word);
+        }
+    } // else if (send_addr == RT_NULL && recv_addr != RT_NULL)
+    // Read&Write
+    else
+    {
+        while (length > 0)
+        {
+            /* Input data to SPI TX FIFO */
+            send_addr += nu_spi_write(spi_base, send_addr, bytes_per_word);
+            length -= bytes_per_word;
+
+            /* Read data from RX FIFO */
+            recv_addr += nu_spi_read(spi_base, recv_addr, bytes_per_word);
+        }
+    } // else
+
+    /* Wait RX or drain RX-FIFO */
+    if (recv_addr)
+    {
+        // Wait SPI transmission done
+        while (SPI_IS_BUSY(spi_base))
+        {
+            while (!SPI_GET_RX_FIFO_EMPTY_FLAG(spi_base))
+            {
+                recv_addr += nu_spi_read(spi_base, recv_addr, bytes_per_word);
+            }
+        }
+
+        while (!SPI_GET_RX_FIFO_EMPTY_FLAG(spi_base))
+        {
+            recv_addr += nu_spi_read(spi_base, recv_addr, bytes_per_word);
+        }
+    }
+    else
+    {
+        /* Clear SPI RX FIFO */
+        nu_spi_drain_rxfifo(spi_base);
+    }
+}
+
+void nu_spi_transfer(struct nu_spi *spi_bus, uint8_t *tx, uint8_t *rx, int length, uint8_t bytes_per_word)
+{
+    RT_ASSERT(spi_bus != RT_NULL);
+
+#if defined(BSP_USING_SPI_PDMA)
+    /* DMA transfer constrains */
+    if ((spi_bus->pdma_chanid_rx >= 0) &&
+            !((uint32_t)tx % bytes_per_word) &&
+            !((uint32_t)rx % bytes_per_word) &&
+            (bytes_per_word != 3) &&
+            (length >= NU_SPI_USE_PDMA_MIN_THRESHOLD))
+        nu_spi_pdma_transmit(spi_bus, tx, rx, length, bytes_per_word);
+    else
+        nu_spi_transmission_with_poll(spi_bus, tx, rx, length, bytes_per_word);
+#else
+    nu_spi_transmission_with_poll(spi_bus, tx, rx, length, bytes_per_word);
+#endif
+}
+
+static rt_uint32_t nu_spi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
+{
+    struct nu_spi *spi_bus;
+    struct rt_spi_configuration *configuration;
+    uint8_t bytes_per_word;
+
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(device->bus != RT_NULL);
+    RT_ASSERT(message != RT_NULL);
+
+    spi_bus = (struct nu_spi *) device->bus;
+    configuration = (struct rt_spi_configuration *)&spi_bus->configuration;
+    bytes_per_word = configuration->data_width / 8;
+
+    if ((message->length % bytes_per_word) != 0)
+    {
+        /* Say bye. */
+        LOG_E("%s: error payload length(%d%%%d != 0).\n", spi_bus->name, message->length, bytes_per_word);
+        return 0;
+    }
+
+    if (message->length > 0)
+    {
+        if (message->cs_take && !(configuration->mode & RT_SPI_NO_CS))
+        {
+            if (configuration->mode & RT_SPI_CS_HIGH)
+            {
+                SPI_SET_SS_HIGH(spi_bus->spi_base);
+            }
+            else
+            {
+                SPI_SET_SS_LOW(spi_bus->spi_base);
+            }
+        }
+
+        nu_spi_transfer(spi_bus, (uint8_t *)message->send_buf, (uint8_t *)message->recv_buf, message->length, bytes_per_word);
+
+        if (message->cs_release && !(configuration->mode & RT_SPI_NO_CS))
+        {
+            if (configuration->mode & RT_SPI_CS_HIGH)
+            {
+                SPI_SET_SS_LOW(spi_bus->spi_base);
+            }
+            else
+            {
+                SPI_SET_SS_HIGH(spi_bus->spi_base);
+            }
+        }
+
+    }
+
+    return message->length;
+}
+
+static int nu_spi_register_bus(struct nu_spi *spi_bus, const char *name)
+{
+    return rt_spi_bus_register(&spi_bus->dev, name, &nu_spi_poll_ops);
+}
+
+/**
+ * Hardware SPI Initial
+ */
+static int rt_hw_spi_init(void)
+{
+    int i;
+
+    for (i = (SPI_START + 1); i < SPI_CNT; i++)
+    {
+        nu_spi_register_bus(&nu_spi_arr[i], nu_spi_arr[i].name);
+#if defined(BSP_USING_SPI_PDMA)
+        nu_spi_arr[i].pdma_chanid_tx = -1;
+        nu_spi_arr[i].pdma_chanid_rx = -1;
+        if ((nu_spi_arr[i].pdma_perp_tx != NU_PDMA_UNUSED) && (nu_spi_arr[i].pdma_perp_rx != NU_PDMA_UNUSED))
+        {
+            if (nu_hw_spi_pdma_allocate(&nu_spi_arr[i]) != RT_EOK)
+            {
+                LOG_W("Failed to allocate DMA channels for %s. We will use poll-mode for this bus.\n", nu_spi_arr[i].name);
+            }
+        }
+#endif
+    }
+
+    return 0;
+}
+
+INIT_DEVICE_EXPORT(rt_hw_spi_init);
+
+#endif //#if defined(BSP_USING_SPI)
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_spi.h b/bsp/nuvoton/libraries/m2354/rtt_port/drv_spi.h
new file mode 100644
index 0000000000..d4fbe5358f
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_spi.h
@@ -0,0 +1,51 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-6-15       YHKuo            First version
+*
+******************************************************************************/
+
+#ifndef __DRV_SPI_H__
+#define __DRV_SPI_H__
+
+#include 
+
+#include 
+#include "NuMicro.h"
+#include 
+
+#if defined(BSP_USING_SPI_PDMA)
+    #include 
+#endif
+
+struct nu_spi
+{
+    struct rt_spi_bus dev;
+    char *name;
+    SPI_T *spi_base;
+    uint32_t dummy;
+#if defined(BSP_USING_SPI_PDMA)
+    int16_t pdma_perp_tx;
+    int8_t  pdma_chanid_tx;
+    int16_t pdma_perp_rx;
+    int8_t  pdma_chanid_rx;
+    rt_sem_t m_psSemBus;
+#endif
+    struct rt_qspi_configuration  configuration;
+};
+
+typedef struct nu_spi *nu_spi_t;
+
+void nu_spi_drain_rxfifo(SPI_T *spi_base);
+void nu_spi_transfer(struct nu_spi *spi_bus, uint8_t *tx, uint8_t *rx, int length, uint8_t bytes_per_word);
+
+#if defined(BSP_USING_SPI_PDMA)
+    rt_err_t nu_hw_spi_pdma_allocate(struct nu_spi *spi_bus);
+#endif
+
+#endif // __DRV_SPI_H___
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_spii2s.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_spii2s.c
new file mode 100644
index 0000000000..ba634ea63b
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_spii2s.c
@@ -0,0 +1,648 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-5-29       Wayne            First version
+*
+******************************************************************************/
+
+#include 
+
+#if defined(BSP_USING_SPII2S)
+
+#include 
+#include 
+#include 
+
+/* Private define ---------------------------------------------------------------*/
+#define DBG_ENABLE
+#define DBG_LEVEL DBG_LOG
+#define DBG_SECTION_NAME  "spii2s"
+#define DBG_COLOR
+#include 
+
+enum
+{
+    SPII2S_START = -1,
+#if defined(BSP_USING_SPII2S0)
+    SPII2S0_IDX,
+#endif
+#if defined(BSP_USING_SPII2S1)
+    SPII2S1_IDX,
+#endif
+#if defined(BSP_USING_SPII2S2)
+    SPII2S2_IDX,
+#endif
+#if defined(BSP_USING_SPII2S3)
+    SPII2S3_IDX,
+#endif
+    SPII2S_CNT
+};
+
+/* Private functions ------------------------------------------------------------*/
+static rt_err_t nu_spii2s_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps);
+static rt_err_t nu_spii2s_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps);
+static rt_err_t nu_spii2s_init(struct rt_audio_device *audio);
+static rt_err_t nu_spii2s_start(struct rt_audio_device *audio, int stream);
+static rt_err_t nu_spii2s_stop(struct rt_audio_device *audio, int stream);
+static void nu_spii2s_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info);
+/* Public functions -------------------------------------------------------------*/
+rt_err_t nu_spii2s_acodec_register(struct rt_audio_device *audio, nu_acodec_ops_t);
+
+/* Private variables ------------------------------------------------------------*/
+static struct nu_i2s g_nu_spii2s_arr [] =
+{
+#if defined(BSP_USING_SPII2S0)
+    {
+        .name = "spii2s0",
+        .i2s_base  = (I2S_T *)SPI0, //Avoid warning
+        .i2s_rst   = SPI0_RST,
+        .i2s_dais = {
+            [NU_I2S_DAI_PLAYBACK] = {
+                .pdma_perp = PDMA_SPI0_TX,
+            },
+            [NU_I2S_DAI_CAPTURE] = {
+                .pdma_perp = PDMA_SPI0_RX,
+            }
+        }
+    },
+#endif
+#if defined(BSP_USING_SPII2S1)
+    {
+        .name = "spii2s1",
+        .i2s_base  = (I2S_T *)SPI1, //Avoid warning
+        .i2s_rst   = SPI1_RST,
+        .i2s_dais = {
+            [NU_I2S_DAI_PLAYBACK] = {
+                .pdma_perp = PDMA_SPI1_TX,
+            },
+            [NU_I2S_DAI_CAPTURE] = {
+                .pdma_perp = PDMA_SPI1_RX,
+            }
+        }
+    },
+#endif
+#if defined(BSP_USING_SPII2S2)
+    {
+        .name = "spii2s2",
+        .i2s_base  = (I2S_T *)SPI2, //Avoid warning
+        .i2s_rst   = SPI2_RST,
+        .i2s_dais = {
+            [NU_I2S_DAI_PLAYBACK] = {
+                .pdma_perp = PDMA_SPI2_TX,
+            },
+            [NU_I2S_DAI_CAPTURE] = {
+                .pdma_perp = PDMA_SPI2_RX,
+            }
+        }
+    },
+#endif
+#if defined(BSP_USING_SPII2S3)
+    {
+        .name = "spii2s3",
+        .i2s_base  = (I2S_T *)SPI3, //Avoid warning
+        .i2s_rst   = SPI3_RST,
+        .i2s_dais = {
+            [NU_I2S_DAI_PLAYBACK] = {
+                .pdma_perp = PDMA_SPI3_TX,
+            },
+            [NU_I2S_DAI_CAPTURE] = {
+                .pdma_perp = PDMA_SPI3_RX,
+            }
+        }
+    },
+#endif
+};
+
+static void nu_pdma_spii2s_rx_cb(void *pvUserData, uint32_t u32EventFilter)
+{
+    nu_i2s_t psNuSPII2s = (nu_i2s_t)pvUserData;
+    nu_i2s_dai_t psNuSPII2sDai;
+
+    RT_ASSERT(psNuSPII2s != RT_NULL);
+    psNuSPII2sDai = &psNuSPII2s->i2s_dais[NU_I2S_DAI_CAPTURE];
+
+    if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE)
+    {
+        // Report a buffer ready.
+        rt_uint8_t *pbuf_old = &psNuSPII2sDai->fifo[psNuSPII2sDai->fifo_block_idx * NU_I2S_DMA_BUF_BLOCK_SIZE] ;
+        psNuSPII2sDai->fifo_block_idx = (psNuSPII2sDai->fifo_block_idx + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER;
+
+        /* Report upper layer. */
+        rt_audio_rx_done(&psNuSPII2s->audio, pbuf_old, NU_I2S_DMA_BUF_BLOCK_SIZE);
+    }
+}
+
+static void nu_pdma_spii2s_tx_cb(void *pvUserData, uint32_t u32EventFilter)
+{
+    nu_i2s_t psNuSPII2s = (nu_i2s_t)pvUserData;
+    nu_i2s_dai_t psNuSPII2sDai;
+
+    RT_ASSERT(psNuSPII2s != RT_NULL);
+    psNuSPII2sDai = &psNuSPII2s->i2s_dais[NU_I2S_DAI_PLAYBACK];
+
+    if (u32EventFilter & NU_PDMA_EVENT_TRANSFER_DONE)
+    {
+        rt_audio_tx_complete(&psNuSPII2s->audio);
+        psNuSPII2sDai->fifo_block_idx = (psNuSPII2sDai->fifo_block_idx + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER;
+    }
+}
+
+static rt_err_t nu_spii2s_pdma_sc_config(nu_i2s_t psNuSPII2s, E_NU_I2S_DAI dai)
+{
+    rt_err_t result = RT_EOK;
+    SPI_T *spii2s_base;
+    nu_i2s_dai_t psNuSPII2sDai;
+    int i;
+    uint32_t u32Src, u32Dst;
+    nu_pdma_cb_handler_t pfm_pdma_cb;
+
+    RT_ASSERT(psNuSPII2s != RT_NULL);
+
+    /* Get base address of spii2s register */
+    spii2s_base = (SPI_T *)psNuSPII2s->i2s_base;
+    psNuSPII2sDai = &psNuSPII2s->i2s_dais[dai];
+
+    switch ((int)dai)
+    {
+    case NU_I2S_DAI_PLAYBACK:
+        pfm_pdma_cb = nu_pdma_spii2s_tx_cb;
+        u32Src = (uint32_t)&psNuSPII2sDai->fifo[0];
+        u32Dst = (uint32_t)&spii2s_base->TX;
+        break;
+
+    case NU_I2S_DAI_CAPTURE:
+        pfm_pdma_cb = nu_pdma_spii2s_rx_cb;
+        u32Src = (uint32_t)&spii2s_base->RX;
+        u32Dst = (uint32_t)&psNuSPII2sDai->fifo[0];
+        break;
+
+    default:
+        return -RT_EINVAL;
+    }
+
+    result = nu_pdma_callback_register(psNuSPII2sDai->pdma_chanid,
+                                       pfm_pdma_cb,
+                                       (void *)psNuSPII2s,
+                                       NU_PDMA_EVENT_TRANSFER_DONE);
+    RT_ASSERT(result == RT_EOK);
+
+    for (i = 0; i < NU_I2S_DMA_BUF_BLOCK_NUMBER; i++)
+    {
+        /* Setup dma descriptor entry */
+        result = nu_pdma_desc_setup(psNuSPII2sDai->pdma_chanid,    // Channel ID
+                                    psNuSPII2sDai->pdma_descs[i], // this descriptor
+                                    32, // 32-bits
+                                    (dai == NU_I2S_DAI_PLAYBACK) ? u32Src + (i * NU_I2S_DMA_BUF_BLOCK_SIZE) : u32Src, //Memory or RXFIFO
+                                    (dai == NU_I2S_DAI_PLAYBACK) ? u32Dst : u32Dst + (i * NU_I2S_DMA_BUF_BLOCK_SIZE), //TXFIFO or Memory
+                                    (int32_t)NU_I2S_DMA_BUF_BLOCK_SIZE / 4,   // Transfer count
+                                    psNuSPII2sDai->pdma_descs[(i + 1) % NU_I2S_DMA_BUF_BLOCK_NUMBER]); // Next descriptor
+        RT_ASSERT(result == RT_EOK);
+    }
+
+    /* Assign head descriptor */
+    result = nu_pdma_sg_transfer(psNuSPII2sDai->pdma_chanid, psNuSPII2sDai->pdma_descs[0], 0);
+    RT_ASSERT(result == RT_EOK);
+
+    return result;
+}
+
+static rt_bool_t nu_spii2s_capacity_check(struct rt_audio_configure *pconfig)
+{
+    switch (pconfig->samplebits)
+    {
+    case  8:
+    case 16:
+    /* case 24: PDMA constrain */
+    case 32:
+        break;
+    default:
+        goto exit_nu_spii2s_capacity_check;
+    }
+
+    switch (pconfig->channels)
+    {
+    case 1:
+    case 2:
+        break;
+    default:
+        goto exit_nu_spii2s_capacity_check;
+    }
+
+    return RT_TRUE;
+
+exit_nu_spii2s_capacity_check:
+
+    return RT_FALSE;
+}
+
+static rt_err_t nu_spii2s_dai_setup(nu_i2s_t psNuSPII2s, struct rt_audio_configure *pconfig)
+{
+    rt_err_t result = RT_EOK;
+    nu_acodec_ops_t pNuACodecOps;
+    SPI_T *spii2s_base = (SPI_T *)psNuSPII2s->i2s_base;
+
+    RT_ASSERT(psNuSPII2s->AcodecOps != RT_NULL);
+    pNuACodecOps = psNuSPII2s->AcodecOps;
+
+    /* Open SPII2S */
+    if (nu_spii2s_capacity_check(pconfig) == RT_TRUE)
+    {
+        /* Reset audio codec */
+        if (pNuACodecOps->nu_acodec_reset)
+            result = pNuACodecOps->nu_acodec_reset();
+
+        if (result != RT_EOK)
+            goto exit_nu_spii2s_dai_setup;
+
+        /* Setup audio codec */
+        if (pNuACodecOps->nu_acodec_init)
+            result = pNuACodecOps->nu_acodec_init();
+
+        if (!pNuACodecOps->nu_acodec_init || result != RT_EOK)
+            goto exit_nu_spii2s_dai_setup;
+
+        /* Setup acodec samplerate/samplebit/channel */
+        if (pNuACodecOps->nu_acodec_dsp_control)
+            result = pNuACodecOps->nu_acodec_dsp_control(pconfig);
+
+        if (!pNuACodecOps->nu_acodec_dsp_control || result != RT_EOK)
+            goto exit_nu_spii2s_dai_setup;
+
+        SPII2S_Open(spii2s_base,
+                    (psNuSPII2s->AcodecOps->role == NU_ACODEC_ROLE_MASTER) ? SPII2S_MODE_SLAVE : SPII2S_MODE_MASTER,
+                    pconfig->samplerate,
+                    (((pconfig->samplebits / 8) - 1) << SPI_I2SCTL_WDWIDTH_Pos),
+                    (pconfig->channels == 1) ? SPII2S_MONO : SPII2S_STEREO,
+                    SPII2S_FORMAT_I2S);
+        LOG_I("Open SPII2S.");
+
+        /* Set MCLK and enable MCLK */
+        /* The target MCLK is related to audio codec setting. */
+        SPII2S_EnableMCLK(spii2s_base, 12000000);
+
+        /* Set un-mute */
+        if (pNuACodecOps->nu_acodec_mixer_control)
+            pNuACodecOps->nu_acodec_mixer_control(AUDIO_MIXER_MUTE, RT_FALSE);
+    }
+    else
+        result = -RT_EINVAL;
+
+exit_nu_spii2s_dai_setup:
+
+    return result;
+}
+
+static rt_err_t nu_spii2s_getcaps(struct rt_audio_device *audio, struct rt_audio_caps *caps)
+{
+    rt_err_t result = RT_EOK;
+    nu_i2s_t psNuSPII2s = (nu_i2s_t)audio;
+    nu_acodec_ops_t pNuACodecOps;
+
+    RT_ASSERT(audio != RT_NULL);
+    RT_ASSERT(caps != RT_NULL);
+    RT_ASSERT(psNuSPII2s->AcodecOps != RT_NULL);
+
+    pNuACodecOps = psNuSPII2s->AcodecOps;
+
+    switch (caps->main_type)
+    {
+    case AUDIO_TYPE_QUERY:
+        switch (caps->sub_type)
+        {
+        case AUDIO_TYPE_QUERY:
+            caps->udata.mask = AUDIO_TYPE_INPUT | AUDIO_TYPE_OUTPUT | AUDIO_TYPE_MIXER;
+            break;
+        default:
+            result = -RT_ERROR;
+            break;
+        } // switch (caps->sub_type)
+        break;
+
+    case AUDIO_TYPE_MIXER:
+
+        if (pNuACodecOps->nu_acodec_mixer_query)
+        {
+            switch (caps->sub_type)
+            {
+            case AUDIO_MIXER_QUERY:
+                return pNuACodecOps->nu_acodec_mixer_query(AUDIO_MIXER_QUERY, &caps->udata.mask);
+
+            default:
+                return pNuACodecOps->nu_acodec_mixer_query(caps->sub_type, (rt_uint32_t *)&caps->udata.value);
+            } // switch (caps->sub_type)
+
+        } // if (pNuACodecOps->nu_acodec_mixer_query)
+
+        result = -RT_ERROR;
+        break;
+
+    case AUDIO_TYPE_INPUT:
+    case AUDIO_TYPE_OUTPUT:
+
+        switch (caps->sub_type)
+        {
+        case AUDIO_DSP_PARAM:
+            caps->udata.config.channels = psNuSPII2s->config.channels;
+            caps->udata.config.samplebits = psNuSPII2s->config.samplebits;
+            caps->udata.config.samplerate = psNuSPII2s->config.samplerate;
+            break;
+        case AUDIO_DSP_SAMPLERATE:
+            caps->udata.config.samplerate = psNuSPII2s->config.samplerate;
+            break;
+        case AUDIO_DSP_CHANNELS:
+            caps->udata.config.channels = psNuSPII2s->config.channels;
+            break;
+        case AUDIO_DSP_SAMPLEBITS:
+            caps->udata.config.samplebits = psNuSPII2s->config.samplebits;
+            break;
+        default:
+            result = -RT_ERROR;
+            break;
+        } // switch (caps->sub_type)
+        break;
+
+    default:
+        result = -RT_ERROR;
+        break;
+
+    } // switch (caps->main_type)
+
+    return result;
+}
+
+static rt_err_t nu_spii2s_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps)
+{
+    rt_err_t result = RT_EOK;
+    nu_i2s_t psNuSPII2s = (nu_i2s_t)audio;
+    nu_acodec_ops_t pNuACodecOps;
+    int stream = -1;
+
+    RT_ASSERT(audio != RT_NULL);
+    RT_ASSERT(caps != RT_NULL);
+    RT_ASSERT(psNuSPII2s->AcodecOps != RT_NULL);
+
+    pNuACodecOps = psNuSPII2s->AcodecOps;
+
+    switch (caps->main_type)
+    {
+    case AUDIO_TYPE_MIXER:
+        if (psNuSPII2s->AcodecOps->nu_acodec_mixer_control)
+            psNuSPII2s->AcodecOps->nu_acodec_mixer_control(caps->sub_type, caps->udata.value);
+        break;
+
+    case AUDIO_TYPE_INPUT:
+        stream = AUDIO_STREAM_RECORD;
+    case AUDIO_TYPE_OUTPUT:
+    {
+        rt_bool_t bNeedReset = RT_FALSE;
+
+        if (stream < 0)
+            stream = AUDIO_STREAM_REPLAY;
+
+        switch (caps->sub_type)
+        {
+        case AUDIO_DSP_PARAM:
+            if (rt_memcmp(&psNuSPII2s->config, &caps->udata.config, sizeof(struct rt_audio_configure)) != 0)
+            {
+                rt_memcpy(&psNuSPII2s->config, &caps->udata.config, sizeof(struct rt_audio_configure));
+                bNeedReset = RT_TRUE;
+            }
+            break;
+        case AUDIO_DSP_SAMPLEBITS:
+            if (psNuSPII2s->config.samplerate != caps->udata.config.samplebits)
+            {
+                psNuSPII2s->config.samplerate = caps->udata.config.samplebits;
+                bNeedReset = RT_TRUE;
+            }
+            break;
+        case AUDIO_DSP_CHANNELS:
+            if (psNuSPII2s->config.channels != caps->udata.config.channels)
+            {
+                pNuACodecOps->config.channels = caps->udata.config.channels;
+                bNeedReset = RT_TRUE;
+            }
+            break;
+        case AUDIO_DSP_SAMPLERATE:
+            if (psNuSPII2s->config.samplerate != caps->udata.config.samplerate)
+            {
+                psNuSPII2s->config.samplerate = caps->udata.config.samplerate;
+                bNeedReset = RT_TRUE;
+            }
+            break;
+        default:
+            result = -RT_ERROR;
+            break;
+        } // switch (caps->sub_type)
+
+        if (bNeedReset)
+        {
+            return nu_spii2s_start(audio, stream);
+        }
+    }
+    break;
+
+    default:
+        result = -RT_ERROR;
+        break;
+    } // switch (caps->main_type)
+
+    return result;
+}
+
+static rt_err_t nu_spii2s_init(struct rt_audio_device *audio)
+{
+    rt_err_t result = RT_EOK;
+    nu_i2s_t psNuSPII2s = (nu_i2s_t)audio;
+
+    RT_ASSERT(audio != RT_NULL);
+
+    /* Reset this module */
+    SYS_ResetModule(psNuSPII2s->i2s_rst);
+
+    return -(result);
+}
+
+static rt_err_t nu_spii2s_start(struct rt_audio_device *audio, int stream)
+{
+    nu_i2s_t psNuSPII2s = (nu_i2s_t)audio;
+    SPI_T *spii2s_base;
+
+    RT_ASSERT(audio != RT_NULL);
+
+    spii2s_base = (SPI_T *)psNuSPII2s->i2s_base;
+
+    /* Restart all: SPII2S and codec. */
+    nu_spii2s_stop(audio, stream);
+    if (nu_spii2s_dai_setup(psNuSPII2s, &psNuSPII2s->config) != RT_EOK)
+        return -RT_ERROR;
+
+    switch (stream)
+    {
+    case AUDIO_STREAM_REPLAY:
+    {
+        nu_spii2s_pdma_sc_config(psNuSPII2s, NU_I2S_DAI_PLAYBACK);
+
+        /* Start TX DMA */
+        SPII2S_ENABLE_TXDMA(spii2s_base);
+
+        /* Enable I2S Tx function */
+        SPII2S_ENABLE_TX(spii2s_base);
+
+        LOG_I("Start replay.");
+    }
+    break;
+
+    case AUDIO_STREAM_RECORD:
+    {
+        nu_spii2s_pdma_sc_config(psNuSPII2s, NU_I2S_DAI_CAPTURE);
+
+        /* Start RX DMA */
+        SPII2S_ENABLE_RXDMA(spii2s_base);
+
+        /* Enable I2S Rx function */
+        SPII2S_ENABLE_RX(spii2s_base);
+
+        LOG_I("Start record.");
+    }
+    break;
+    default:
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t nu_spii2s_stop(struct rt_audio_device *audio, int stream)
+{
+    nu_i2s_t psNuSPII2s = (nu_i2s_t)audio;
+    nu_i2s_dai_t psNuSPII2sDai = RT_NULL;
+    SPI_T *spii2s_base;
+
+    RT_ASSERT(audio != RT_NULL);
+
+    spii2s_base = (SPI_T *)psNuSPII2s->i2s_base;
+
+    switch (stream)
+    {
+    case AUDIO_STREAM_REPLAY:
+        psNuSPII2sDai = &psNuSPII2s->i2s_dais[NU_I2S_DAI_PLAYBACK];
+
+        // Disable TX
+        SPII2S_DISABLE_TXDMA(spii2s_base);
+        SPII2S_DISABLE_TX(spii2s_base);
+
+        LOG_I("Stop replay.");
+        break;
+
+    case AUDIO_STREAM_RECORD:
+        psNuSPII2sDai = &psNuSPII2s->i2s_dais[NU_I2S_DAI_CAPTURE];
+
+        // Disable RX
+        SPII2S_DISABLE_RXDMA(spii2s_base);
+        SPII2S_DISABLE_RX(spii2s_base);
+
+        LOG_I("Stop record.");
+        break;
+
+    default:
+        return -RT_EINVAL;
+    }
+
+    /* Stop DMA transfer. */
+    nu_pdma_channel_terminate(psNuSPII2sDai->pdma_chanid);
+
+    /* Close SPII2S */
+    if (!(spii2s_base->I2SCTL & (SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_RXEN_Msk)))
+    {
+        SPII2S_DisableMCLK(spii2s_base);
+        SPII2S_Close(spii2s_base);
+        LOG_I("Close SPII2S.");
+    }
+
+    /* Silence */
+    rt_memset((void *)psNuSPII2sDai->fifo, 0, NU_I2S_DMA_FIFO_SIZE);
+    psNuSPII2sDai->fifo_block_idx = 0;
+
+    return RT_EOK;
+}
+
+static void nu_spii2s_buffer_info(struct rt_audio_device *audio, struct rt_audio_buf_info *info)
+{
+    nu_i2s_t psNuSPII2s = (nu_i2s_t)audio;
+
+    RT_ASSERT(audio != RT_NULL);
+    RT_ASSERT(info != RT_NULL);
+
+    info->buffer = (rt_uint8_t *)psNuSPII2s->i2s_dais[NU_I2S_DAI_PLAYBACK].fifo ;
+    info->total_size = NU_I2S_DMA_FIFO_SIZE;
+    info->block_size = NU_I2S_DMA_BUF_BLOCK_SIZE;
+    info->block_count = NU_I2S_DMA_BUF_BLOCK_NUMBER;
+
+    return;
+}
+
+static struct rt_audio_ops nu_spii2s_audio_ops =
+{
+    .getcaps     = nu_spii2s_getcaps,
+    .configure   = nu_spii2s_configure,
+
+    .init        = nu_spii2s_init,
+    .start       = nu_spii2s_start,
+    .stop        = nu_spii2s_stop,
+    .transmit    = RT_NULL,
+    .buffer_info = nu_spii2s_buffer_info
+};
+
+static rt_err_t nu_hw_spii2s_pdma_allocate(nu_i2s_dai_t psNuSPII2sDai)
+{
+    /* Allocate I2S nu_dma channel */
+    if ((psNuSPII2sDai->pdma_chanid = nu_pdma_channel_allocate(psNuSPII2sDai->pdma_perp)) < 0)
+    {
+        goto nu_hw_spii2s_pdma_allocate;
+    }
+
+    return RT_EOK;
+
+nu_hw_spii2s_pdma_allocate:
+
+    return -(RT_ERROR);
+}
+
+int rt_hw_spii2s_init(void)
+{
+    int j = 0;
+    nu_i2s_dai_t psNuSPII2sDai;
+
+    for (j = (SPII2S_START + 1); j < SPII2S_CNT; j++)
+    {
+        int i = 0;
+        for (i = 0; i < NU_I2S_DAI_CNT; i++)
+        {
+            uint8_t *pu8ptr = rt_malloc(NU_I2S_DMA_FIFO_SIZE);
+            psNuSPII2sDai = &g_nu_spii2s_arr[j].i2s_dais[i];
+            psNuSPII2sDai->fifo = pu8ptr;
+            rt_memset(pu8ptr, 0, NU_I2S_DMA_FIFO_SIZE);
+            RT_ASSERT(psNuSPII2sDai->fifo != RT_NULL);
+
+            psNuSPII2sDai->pdma_chanid = -1;
+            psNuSPII2sDai->fifo_block_idx = 0;
+            RT_ASSERT(nu_hw_spii2s_pdma_allocate(psNuSPII2sDai) == RT_EOK);
+            RT_ASSERT(nu_pdma_sgtbls_allocate(&psNuSPII2sDai->pdma_descs[0], NU_I2S_DMA_BUF_BLOCK_NUMBER) == RT_EOK);
+        }
+
+        /* Register ops of audio device */
+        g_nu_spii2s_arr[j].audio.ops  = &nu_spii2s_audio_ops;
+
+        /* Register device, RW: it is with replay and record functions. */
+        rt_audio_register(&g_nu_spii2s_arr[j].audio, g_nu_spii2s_arr[j].name, RT_DEVICE_FLAG_RDWR, &g_nu_spii2s_arr[j]);
+    }
+
+    return RT_EOK;
+}
+INIT_DEVICE_EXPORT(rt_hw_spii2s_init);
+#endif //#if defined(BSP_USING_SPII2S)
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_timer.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_timer.c
new file mode 100644
index 0000000000..b4d5472ee8
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_timer.c
@@ -0,0 +1,391 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-6-17       YCHuang12        First version
+*
+******************************************************************************/
+
+#include 
+
+#if (defined(BSP_USING_TIMER) && defined(RT_USING_HWTIMER))
+
+#include 
+#include "NuMicro.h"
+
+/* Private define ---------------------------------------------------------------*/
+#define NU_TIMER_DEVICE(timer) (nu_timer_t *)(timer)
+
+/* Private typedef --------------------------------------------------------------*/
+typedef struct nu_timer
+{
+    rt_hwtimer_t parent;
+    TIMER_T *timer_periph;
+    IRQn_Type IRQn;
+} nu_timer_t;
+
+/* Private functions ------------------------------------------------------------*/
+static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state);
+static rt_err_t nu_timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t opmode);
+static void nu_timer_stop(rt_hwtimer_t *timer);
+static rt_uint32_t nu_timer_count_get(rt_hwtimer_t *timer);
+static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args);
+
+/* Public functions -------------------------------------------------------------*/
+
+
+/* Private variables ------------------------------------------------------------*/
+#ifdef BSP_USING_TIMER0
+    static nu_timer_t nu_timer0;
+#endif
+
+#ifdef BSP_USING_TIMER1
+    static nu_timer_t nu_timer1;
+#endif
+
+#ifdef BSP_USING_TIMER2
+    static nu_timer_t nu_timer2;
+#endif
+
+#ifdef BSP_USING_TIMER3
+    static nu_timer_t nu_timer3;
+#endif
+
+#ifdef BSP_USING_TIMER4
+    static nu_timer_t nu_timer4;
+#endif
+
+#ifdef BSP_USING_TIMER5
+    static nu_timer_t nu_timer5;
+#endif
+
+static struct rt_hwtimer_info nu_timer_info =
+{
+    12000000, /* maximum count frequency */
+    46875,        /* minimum count frequency */
+    0xFFFFFF,          /* the maximum counter value */
+    HWTIMER_CNTMODE_UP,/* Increment or Decreasing count mode */
+};
+
+static struct rt_hwtimer_ops nu_timer_ops =
+{
+    nu_timer_init,
+    nu_timer_start,
+    nu_timer_stop,
+    nu_timer_count_get,
+    nu_timer_control
+};
+
+/* Functions define ------------------------------------------------------------*/
+static void nu_timer_init(rt_hwtimer_t *timer, rt_uint32_t state)
+{
+    RT_ASSERT(timer != RT_NULL);
+
+    nu_timer_t *nu_timer = NU_TIMER_DEVICE(timer->parent.user_data);
+    RT_ASSERT(nu_timer != RT_NULL);
+    RT_ASSERT(nu_timer->timer_periph != RT_NULL);
+
+    if (1 == state)
+    {
+        uint32_t timer_clk;
+        struct rt_hwtimer_info *info = &nu_timer_info;
+
+        timer_clk = TIMER_GetModuleClock(nu_timer->timer_periph);
+        info->maxfreq = timer_clk;
+        info->minfreq = timer_clk / 256;
+        TIMER_Open(nu_timer->timer_periph, TIMER_ONESHOT_MODE, 1);
+        TIMER_EnableInt(nu_timer->timer_periph);
+        NVIC_EnableIRQ(nu_timer->IRQn);
+    }
+    else
+    {
+        NVIC_DisableIRQ(nu_timer->IRQn);
+        TIMER_DisableInt(nu_timer->timer_periph);
+        TIMER_Close(nu_timer->timer_periph);
+    }
+}
+
+static rt_err_t nu_timer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t opmode)
+{
+    rt_err_t err = RT_EOK;
+    RT_ASSERT(timer != RT_NULL);
+
+    nu_timer_t *nu_timer = NU_TIMER_DEVICE(timer->parent.user_data);
+    RT_ASSERT(nu_timer != RT_NULL);
+    RT_ASSERT(nu_timer->timer_periph != RT_NULL);
+
+    if (cnt > 1 && cnt <= 0xFFFFFF)
+    {
+        TIMER_SET_CMP_VALUE(nu_timer->timer_periph, cnt);
+    }
+    else
+    {
+        rt_kprintf("nu_timer_start set compared value failed\n");
+        err = RT_ERROR;
+    }
+
+    if (HWTIMER_MODE_PERIOD == opmode)
+    {
+        TIMER_SET_OPMODE(nu_timer->timer_periph, TIMER_PERIODIC_MODE);
+    }
+    else if (HWTIMER_MODE_ONESHOT == opmode)
+    {
+        TIMER_SET_OPMODE(nu_timer->timer_periph, TIMER_ONESHOT_MODE);
+    }
+    else
+    {
+        rt_kprintf("nu_timer_start set operation mode failed\n");
+        err = RT_ERROR;
+    }
+
+    TIMER_Start(nu_timer->timer_periph);
+
+    return err;
+}
+
+static void nu_timer_stop(rt_hwtimer_t *timer)
+{
+    RT_ASSERT(timer != RT_NULL);
+
+    nu_timer_t *nu_timer = NU_TIMER_DEVICE(timer->parent.user_data);
+    RT_ASSERT(nu_timer != RT_NULL);
+    RT_ASSERT(nu_timer->timer_periph != RT_NULL);
+
+    TIMER_Stop(nu_timer->timer_periph);
+}
+
+static rt_uint32_t nu_timer_count_get(rt_hwtimer_t *timer)
+{
+    RT_ASSERT(timer != RT_NULL);
+
+    nu_timer_t *nu_timer = NU_TIMER_DEVICE(timer->parent.user_data);
+    RT_ASSERT(nu_timer != RT_NULL);
+    RT_ASSERT(nu_timer->timer_periph != RT_NULL);
+
+    return TIMER_GetCounter(nu_timer->timer_periph);
+}
+
+static rt_err_t nu_timer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args)
+{
+    rt_err_t ret = RT_EOK;
+
+    RT_ASSERT(timer != RT_NULL);
+
+    nu_timer_t *nu_timer = NU_TIMER_DEVICE(timer->parent.user_data);
+    RT_ASSERT(nu_timer != RT_NULL);
+    RT_ASSERT(nu_timer->timer_periph != RT_NULL);
+
+    switch (cmd)
+    {
+    case HWTIMER_CTRL_FREQ_SET:
+    {
+        uint32_t clk;
+        uint32_t pre;
+
+        clk = TIMER_GetModuleClock(nu_timer->timer_periph);
+        pre = clk / *((uint32_t *)args) - 1;
+        TIMER_SET_PRESCALE_VALUE(nu_timer->timer_periph, pre);
+        *((uint32_t *)args) = clk / (pre + 1) ;
+    }
+    break;
+
+    case HWTIMER_CTRL_STOP:
+        TIMER_Stop(nu_timer->timer_periph);
+        break;
+
+    default:
+        ret = RT_EINVAL;
+        break;
+    }
+
+    return ret;
+}
+
+int rt_hw_timer_init(void)
+{
+    rt_err_t ret = RT_EOK;
+
+#ifdef BSP_USING_TIMER0
+    nu_timer0.timer_periph = TIMER0;
+    nu_timer0.parent.info = &nu_timer_info;
+    nu_timer0.parent.ops = &nu_timer_ops;
+    nu_timer0.IRQn = TMR0_IRQn;
+    ret = rt_device_hwtimer_register(&nu_timer0.parent, "timer0", &nu_timer0);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("timer0 register failed\n");
+    }
+    SYS_ResetModule(TMR0_RST);
+    CLK_EnableModuleClock(TMR0_MODULE);
+#endif
+
+#ifdef BSP_USING_TIMER1
+    nu_timer1.timer_periph = TIMER1;
+    nu_timer1.parent.info = &nu_timer_info;
+    nu_timer1.parent.ops = &nu_timer_ops;
+    nu_timer1.IRQn = TMR1_IRQn;
+    ret = rt_device_hwtimer_register(&nu_timer1.parent, "timer1", &nu_timer1);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("timer1 register failed\n");
+    }
+    SYS_ResetModule(TMR1_RST);
+    CLK_EnableModuleClock(TMR1_MODULE);
+#endif
+
+#ifdef BSP_USING_TIMER2
+    nu_timer2.timer_periph = TIMER2;
+    nu_timer2.parent.info = &nu_timer_info;
+    nu_timer2.parent.ops = &nu_timer_ops;
+    nu_timer2.IRQn = TMR2_IRQn;
+    ret = rt_device_hwtimer_register(&nu_timer2.parent, "timer2", &nu_timer2);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("timer2 register failed\n");
+    }
+    SYS_ResetModule(TMR2_RST);
+    CLK_EnableModuleClock(TMR2_MODULE);
+#endif
+
+#ifdef BSP_USING_TIMER3
+    nu_timer3.timer_periph = TIMER3;
+    nu_timer3.parent.info = &nu_timer_info;
+    nu_timer3.parent.ops = &nu_timer_ops;
+    nu_timer3.IRQn = TMR3_IRQn;
+    ret = rt_device_hwtimer_register(&nu_timer3.parent, "timer3", &nu_timer3);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("timer3 register failed\n");
+    }
+    SYS_ResetModule(TMR3_RST);
+    CLK_EnableModuleClock(TMR3_MODULE);
+#endif
+
+#ifdef BSP_USING_TIMER4
+    nu_timer4.timer_periph = TIMER4;
+    nu_timer4.parent.info = &nu_timer_info;
+    nu_timer4.parent.ops = &nu_timer_ops;
+    nu_timer4.IRQn = TMR4_IRQn;
+    ret = rt_device_hwtimer_register(&nu_timer4.parent, "timer4", &nu_timer4);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("timer4 register failed\n");
+    }
+    SYS_ResetModule(TMR4_RST);
+    CLK_EnableModuleClock(TMR4_MODULE);
+#endif
+
+#ifdef BSP_USING_TIMER5
+    nu_timer5.timer_periph = TIMER5;
+    nu_timer5.parent.info = &nu_timer_info;
+    nu_timer5.parent.ops = &nu_timer_ops;
+    nu_timer5.IRQn = TMR5_IRQn;
+    ret = rt_device_hwtimer_register(&nu_timer5.parent, "timer5", &nu_timer5);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("timer5 register failed\n");
+    }
+    SYS_ResetModule(TMR5_RST);
+    CLK_EnableModuleClock(TMR5_MODULE);
+#endif
+
+    return ret;
+}
+
+INIT_BOARD_EXPORT(rt_hw_timer_init);
+
+#ifdef BSP_USING_TIMER0
+void TMR0_IRQHandler(void)
+{
+    rt_interrupt_enter();
+
+    if (TIMER_GetIntFlag(TIMER0))
+    {
+        TIMER_ClearIntFlag(TIMER0);
+        rt_device_hwtimer_isr(&nu_timer0.parent);
+    }
+
+    rt_interrupt_leave();
+}
+#endif
+
+#ifdef BSP_USING_TIMER1
+void TMR1_IRQHandler(void)
+{
+    rt_interrupt_enter();
+
+    if (TIMER_GetIntFlag(TIMER1))
+    {
+        TIMER_ClearIntFlag(TIMER1);
+        rt_device_hwtimer_isr(&nu_timer1.parent);
+    }
+
+    rt_interrupt_leave();
+}
+#endif
+
+#ifdef BSP_USING_TIMER2
+void TMR2_IRQHandler(void)
+{
+    rt_interrupt_enter();
+
+    if (TIMER_GetIntFlag(TIMER2))
+    {
+        TIMER_ClearIntFlag(TIMER2);
+        rt_device_hwtimer_isr(&nu_timer2.parent);
+    }
+
+    rt_interrupt_leave();
+}
+#endif
+
+#ifdef BSP_USING_TIMER3
+void TMR3_IRQHandler(void)
+{
+    rt_interrupt_enter();
+
+    if (TIMER_GetIntFlag(TIMER3))
+    {
+        TIMER_ClearIntFlag(TIMER3);
+        rt_device_hwtimer_isr(&nu_timer3.parent);
+    }
+
+    rt_interrupt_leave();
+}
+#endif
+
+#ifdef BSP_USING_TIMER4
+void TMR4_IRQHandler(void)
+{
+    rt_interrupt_enter();
+
+    if (TIMER_GetIntFlag(TIMER4))
+    {
+        TIMER_ClearIntFlag(TIMER4);
+        rt_device_hwtimer_isr(&nu_timer4.parent);
+    }
+
+    rt_interrupt_leave();
+}
+#endif
+
+#ifdef BSP_USING_TIMER5
+void TMR5_IRQHandler(void)
+{
+    rt_interrupt_enter();
+
+    if (TIMER_GetIntFlag(TIMER5))
+    {
+        TIMER_ClearIntFlag(TIMER5);
+        rt_device_hwtimer_isr(&nu_timer5.parent);
+    }
+
+    rt_interrupt_leave();
+}
+#endif
+
+#endif //#if (defined(BSP_USING_TIMER) && defined(RT_USING_HWTIMER))
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_timer_capture.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_timer_capture.c
new file mode 100644
index 0000000000..ee1e189307
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_timer_capture.c
@@ -0,0 +1,380 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-8-20       Philo            First version
+*
+******************************************************************************/
+
+#include 
+
+#if defined(BSP_USING_TIMER_CAPTURE)
+#if defined(BSP_USING_TIMER0_CAPTURE)|| \
+    defined(BSP_USING_TIMER1_CAPTURE)|| \
+    defined(BSP_USING_TIMER2_CAPTURE)|| \
+    defined(BSP_USING_TIMER3_CAPTURE)|| \
+    defined(BSP_USING_TIMER4_CAPTURE)|| \
+    defined(BSP_USING_TIMER5_CAPTURE)
+
+#include 
+#include "NuMicro.h"
+
+/* Private typedef --------------------------------------------------------------*/
+typedef struct _timer
+{
+    struct rt_inputcapture_device   parent;
+    TIMER_T     *timer;
+    uint8_t     u8Channel;
+    IRQn_Type   irq;
+    uint32_t    u32CurrentCnt;
+    rt_bool_t   input_data_level;
+    rt_bool_t   first_edge;
+} nu_capture_t;
+
+/* Private functions ------------------------------------------------------------*/
+static  rt_err_t nu_capture_init(struct rt_inputcapture_device *inputcapture);
+static  rt_err_t nu_capture_open(struct rt_inputcapture_device *inputcapture);
+static  rt_err_t nu_capture_close(struct rt_inputcapture_device *inputcapture);
+static  rt_err_t nu_capture_get_pulsewidth(struct rt_inputcapture_device *inputcapture, rt_uint32_t *pulsewidth_us);
+
+/* Private define ---------------------------------------------------------------*/
+#define TIMER_CHANNEL_NUM   (6)
+
+#define TIMER0_POS  (0)
+#define TIMER1_POS  (1)
+#define TIMER2_POS  (2)
+#define TIMER3_POS  (3)
+#define TIMER4_POS  (4)
+#define TIMER5_POS  (5)
+
+/* Timer prescale setting. Since it will affect the pulse width of measure, it is recommended to set to 2. */
+#define PSC_DIV     (2)
+
+/* Public functions -------------------------------------------------------------*/
+
+
+/* Private variables ------------------------------------------------------------*/
+static const char *nu_timer_device_name[TIMER_CHANNEL_NUM] = { "timer0i0", "timer1i0", "timer2i0", "timer3i0", "timer4i0", "timer5i0"};
+static const IRQn_Type nu_timer_irq[TIMER_CHANNEL_NUM] = { TMR0_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn, TMR4_IRQn, TMR5_IRQn};
+static TIMER_T *nu_timer_base[TIMER_CHANNEL_NUM] = { TIMER0, TIMER1, TIMER2, TIMER3, TIMER4, TIMER5};
+static nu_capture_t *nu_timer_capture[TIMER_CHANNEL_NUM] = {0};
+
+static struct rt_inputcapture_ops nu_capture_ops =
+{
+    .init   =   nu_capture_init,
+    .open   =   nu_capture_open,
+    .close  =   nu_capture_close,
+    .get_pulsewidth =   nu_capture_get_pulsewidth,
+};
+
+/* Functions define ------------------------------------------------------------*/
+void timer_interrupt_handler(nu_capture_t *nu_timer_capture)
+{
+    TIMER_ClearCaptureIntFlag(nu_timer_capture->timer);
+
+    /* First event is rising edge */
+    if (nu_timer_capture->first_edge == RT_TRUE)
+    {
+        nu_timer_capture->first_edge = RT_FALSE;
+        nu_timer_capture->input_data_level = RT_FALSE;
+    }
+    else
+    {
+        nu_timer_capture->input_data_level = !nu_timer_capture->input_data_level;
+        nu_timer_capture->u32CurrentCnt = TIMER_GetCaptureData(nu_timer_capture->timer);
+
+        rt_hw_inputcapture_isr(&nu_timer_capture->parent, nu_timer_capture->input_data_level);
+    }
+}
+
+#if defined(BSP_USING_TIMER0_CAPTURE)
+void TMR0_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    timer_interrupt_handler(nu_timer_capture[0]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif  //defined(BSP_USING_TIMER0_CAPTURE)
+
+#if defined(BSP_USING_TIMER1_CAPTURE)
+void TMR1_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    timer_interrupt_handler(nu_timer_capture[1]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+
+}
+#endif  //defined(BSP_USING_TIMER1_CAPTURE)
+
+#if defined(BSP_USING_TIMER2_CAPTURE)
+void TMR2_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    timer_interrupt_handler(nu_timer_capture[2]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif  //defined(BSP_USING_TIMER2_CAPTURE)
+
+#if defined(BSP_USING_TIMER3_CAPTURE)
+void TMR3_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    timer_interrupt_handler(nu_timer_capture[3]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif  //defined(BSP_USING_TIMER3_CAPTURE)
+
+#if defined(BSP_USING_TIMER4_CAPTURE)
+void TMR4_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    timer_interrupt_handler(nu_timer_capture[4]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif  //defined(BSP_USING_TIMER4_CAPTURE)
+
+#if defined(BSP_USING_TIMER5_CAPTURE)
+void TMR5_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    timer_interrupt_handler(nu_timer_capture[5]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif  //defined(BSP_USING_TIMER5_CAPTURE)
+
+static rt_err_t nu_capture_get_pulsewidth(struct rt_inputcapture_device *inputcapture, rt_uint32_t *pulsewidth_us)
+{
+    rt_err_t ret = RT_EOK;
+    nu_capture_t *nu_capture;
+
+    nu_capture = (nu_capture_t *)inputcapture;
+
+    *pulsewidth_us = nu_capture->u32CurrentCnt / PSC_DIV;
+
+    return -(ret);
+}
+
+static rt_err_t nu_timer_init(nu_capture_t *nu_capture)
+{
+    SYS_UnlockReg();
+
+#if defined(BSP_USING_TIMER0_CAPTURE)
+    if (nu_capture->timer == TIMER0)
+    {
+        /* Enable TIMER0 clock */
+        CLK_EnableModuleClock(TMR0_MODULE);
+        CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_PCLK0, 0);
+        goto exit_nu_timer_init;
+    }
+#endif
+#if defined(BSP_USING_TIMER1_CAPTURE)
+    if (nu_capture->timer == TIMER1)
+    {
+        /* Enable TIMER1 clock */
+        CLK_EnableModuleClock(TMR1_MODULE);
+        CLK_SetModuleClock(TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_PCLK0, 0);
+        goto exit_nu_timer_init;
+    }
+#endif
+#if defined(BSP_USING_TIMER2_CAPTURE)
+    if (nu_capture->timer == TIMER2)
+    {
+        /* Enable TIMER2 clock */
+        CLK_EnableModuleClock(TMR2_MODULE);
+        CLK_SetModuleClock(TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_PCLK1, 0);
+        goto exit_nu_timer_init;
+    }
+#endif
+#if defined(BSP_USING_TIMER3_CAPTURE)
+    if (nu_capture->timer == TIMER3)
+    {
+        /* Enable TIMER3 clock */
+        CLK_EnableModuleClock(TMR3_MODULE);
+        CLK_SetModuleClock(TMR3_MODULE, CLK_CLKSEL1_TMR3SEL_PCLK1, 0);
+        goto exit_nu_timer_init;
+    }
+#endif
+#if defined(BSP_USING_TIMER4_CAPTURE)
+    if (nu_capture->timer == TIMER4)
+    {
+        /* Enable TIMER4 clock */
+        CLK_EnableModuleClock(TMR4_MODULE);
+        CLK_SetModuleClock(TMR4_MODULE, CLK_CLKSEL3_TMR4SEL_PCLK0, 0);
+        goto exit_nu_timer_init;
+    }
+#endif
+#if defined(BSP_USING_TIMER5_CAPTURE)
+    if (nu_capture->timer == TIMER5)
+    {
+        /* Enable TIMER3 clock */
+        CLK_EnableModuleClock(TMR5_MODULE);
+        CLK_SetModuleClock(TMR5_MODULE, CLK_CLKSEL3_TMR5SEL_PCLK0, 0);
+        goto exit_nu_timer_init;
+    }
+#endif
+
+    SYS_LockReg();
+    return -(RT_ERROR);
+
+exit_nu_timer_init:
+
+    SYS_LockReg();
+    return RT_EOK;
+}
+
+static rt_err_t nu_capture_init(struct rt_inputcapture_device *inputcapture)
+{
+    rt_err_t ret = RT_EOK;
+    nu_capture_t *nu_capture;
+
+    RT_ASSERT(inputcapture != RT_NULL);
+
+    nu_capture = (nu_capture_t *) inputcapture;
+
+    if (nu_timer_init(nu_capture) != RT_EOK)
+    {
+        rt_kprintf("Failed to initialize TIMER.\n");
+        ret = RT_ERROR;
+    }
+
+    return -(ret);
+}
+
+static uint8_t cal_time_prescale(nu_capture_t *nu_capture)
+{
+    uint32_t u32Clk = TIMER_GetModuleClock(nu_capture->timer);
+
+    /* 1 tick = 1/PSC_DIV us */
+    return (u32Clk / 1000000 / PSC_DIV) - 1;
+}
+
+static rt_err_t nu_capture_open(struct rt_inputcapture_device *inputcapture)
+{
+    rt_err_t ret = RT_EOK;
+    nu_capture_t *nu_capture;
+
+    RT_ASSERT(inputcapture != RT_NULL);
+
+    nu_capture = (nu_capture_t *) inputcapture;
+
+    nu_capture->first_edge = RT_TRUE;
+
+    /* Enable Timer NVIC */
+    NVIC_EnableIRQ(nu_capture->irq);
+
+    /* Reset counter before openning. */
+    TIMER_ResetCounter(nu_capture->timer);
+
+    TIMER_Open(nu_capture->timer, TIMER_CONTINUOUS_MODE, 1);
+    TIMER_SET_PRESCALE_VALUE(nu_capture->timer, cal_time_prescale(nu_capture));
+    TIMER_SET_CMP_VALUE(nu_capture->timer, 0xFFFFFF);
+
+    TIMER_EnableCapture(nu_capture->timer, TIMER_CAPTURE_COUNTER_RESET_MODE, TIMER_CAPTURE_EVENT_RISING_FALLING);
+
+    TIMER_EnableInt(nu_capture->timer);
+
+    TIMER_EnableCaptureInt(nu_capture->timer);
+
+    TIMER_Start(nu_capture->timer);
+
+    return ret;
+}
+
+static rt_err_t nu_capture_close(struct rt_inputcapture_device *inputcapture)
+{
+    rt_err_t ret = RT_EOK;
+
+    nu_capture_t *nu_capture;
+
+    RT_ASSERT(inputcapture != RT_NULL);
+
+    nu_capture = (nu_capture_t *) inputcapture;
+
+    TIMER_Stop(nu_capture->timer);
+
+    TIMER_DisableCaptureInt(nu_capture->timer);
+
+    TIMER_DisableInt(nu_capture->timer);
+
+    TIMER_Close(nu_capture->timer);
+
+    NVIC_DisableIRQ(nu_capture->irq);
+
+    return ret;
+}
+
+/* Init and register timer capture */
+static int nu_timer_capture_device_init(void)
+{
+    uint8_t TIMER_MSK = 0;
+
+#if defined(BSP_USING_TIMER0_CAPTURE)
+    TIMER_MSK |= (0x1 << 0);
+#endif
+#if defined(BSP_USING_TIMER1_CAPTURE)
+    TIMER_MSK |= (0x1 << 1);
+#endif
+#if defined(BSP_USING_TIMER2_CAPTURE)
+    TIMER_MSK |= (0x1 << 2);
+#endif
+#if defined(BSP_USING_TIMER3_CAPTURE)
+    TIMER_MSK |= (0x1 << 3);
+#endif
+#if defined(BSP_USING_TIMER4_CAPTURE)
+    TIMER_MSK |= (0x1 << 4);
+#endif
+#if defined(BSP_USING_TIMER5_CAPTURE)
+    TIMER_MSK |= (0x1 << 5);
+#endif
+
+    for (int i = 0; i < TIMER_CHANNEL_NUM; i++)
+    {
+        if (TIMER_MSK & (0x1 << i))
+        {
+            nu_timer_capture[i] = (nu_capture_t *)rt_malloc(sizeof(nu_capture_t));
+
+            nu_timer_capture[i]->timer = nu_timer_base[i];
+            nu_timer_capture[i]->u8Channel = i;
+            nu_timer_capture[i]->irq =   nu_timer_irq[i];
+            nu_timer_capture[i]->u32CurrentCnt = 0;
+            nu_timer_capture[i]->parent.ops = &nu_capture_ops;
+            nu_timer_capture[i]->first_edge = RT_TRUE;
+
+            /* register inputcapture device */
+            rt_device_inputcapture_register(&nu_timer_capture[i]->parent, nu_timer_device_name[i], &nu_timer_capture[i]);
+        }
+    }
+
+    return 0;
+}
+INIT_DEVICE_EXPORT(nu_timer_capture_device_init);
+#endif //#if defined(BSP_USING_TIMER*_CAPTURE)
+#endif //#if defined(BSP_USING_TIMER_CAPTURE)
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_tpwm.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_tpwm.c
new file mode 100644
index 0000000000..6131afab84
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_tpwm.c
@@ -0,0 +1,272 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-6-17       YCHuang12        First version
+*
+* Note: 2 channels of a tpwm have the same output.
+******************************************************************************/
+
+#include 
+
+#if (defined(BSP_USING_TPWM) && defined(RT_USING_PWM))
+
+#define LOG_TAG                 "drv.tpwm"
+#define DBG_ENABLE
+#define DBG_SECTION_NAME        LOG_TAG
+#define DBG_LEVEL               DBG_INFO
+#define TPWM_CHANNEL_NUM        2
+#include 
+
+#include 
+#include 
+#include 
+#include "NuMicro.h"
+
+/* Private define ---------------------------------------------------------------*/
+#define NU_TPWM_DEVICE(tpwm) (nu_tpwm_t *)(tpwm)
+
+/* Private typedef --------------------------------------------------------------*/
+typedef struct nu_tpwm
+{
+    struct rt_device_pwm tpwm_dev;
+    char *name;
+    TIMER_T *tpwm_base;
+    rt_uint32_t channel_mask; //TPWM_CH0 | TPWM_CH1
+} nu_tpwm_t;
+
+/* Private functions ------------------------------------------------------------*/
+static rt_err_t nu_tpwm_enable(struct rt_device_pwm *tpwm_dev, struct rt_pwm_configuration *tpwm_config, rt_bool_t enable);
+static rt_err_t nu_tpwm_set(struct rt_device_pwm *tpwm_dev, struct rt_pwm_configuration *tpwm_config);
+static rt_err_t nu_tpwm_get(struct rt_device_pwm *tpwm_dev, struct rt_pwm_configuration *tpwm_config);
+static rt_err_t nu_tpwm_control(struct rt_device_pwm *tpwm_dev, int cmd, void *arg);
+
+/* Private variables ------------------------------------------------------------*/
+#ifdef BSP_USING_TPWM0
+    static nu_tpwm_t nu_tpwm0;
+#endif
+
+#ifdef BSP_USING_TPWM1
+    static nu_tpwm_t nu_tpwm1;
+#endif
+
+#ifdef BSP_USING_TPWM2
+    static nu_tpwm_t nu_tpwm2;
+#endif
+
+#ifdef BSP_USING_TPWM3
+    static nu_tpwm_t nu_tpwm3;
+#endif
+
+#ifdef BSP_USING_TPWM4
+    static nu_tpwm_t nu_tpwm4;
+#endif
+
+#ifdef BSP_USING_TPWM5
+    static nu_tpwm_t nu_tpwm5;
+#endif
+
+static struct rt_pwm_ops nu_tpwm_ops =
+{
+    nu_tpwm_control
+};
+
+/* Functions define ------------------------------------------------------------*/
+static rt_err_t nu_tpwm_enable(struct rt_device_pwm *tpwm_dev, struct rt_pwm_configuration *tpwm_config, rt_bool_t enable)
+{
+    rt_err_t result = RT_EOK;
+    rt_uint32_t tpwm_channel = tpwm_config->channel;
+    nu_tpwm_t *nu_tpwm = NU_TPWM_DEVICE(tpwm_dev->parent.user_data);
+
+    if (enable == RT_TRUE)
+    {
+        if (nu_tpwm->channel_mask == 0)
+        {
+            TPWM_START_COUNTER(nu_tpwm->tpwm_base);
+        }
+        nu_tpwm->channel_mask |= (1 << tpwm_channel);
+        TPWM_ENABLE_OUTPUT(nu_tpwm->tpwm_base, nu_tpwm->channel_mask);
+    }
+    else
+    {
+        nu_tpwm->channel_mask &= ~(1 << tpwm_channel);
+        TPWM_ENABLE_OUTPUT(nu_tpwm->tpwm_base, nu_tpwm->channel_mask);
+        if (nu_tpwm->channel_mask == 0)
+        {
+            TPWM_STOP_COUNTER(nu_tpwm->tpwm_base);
+        }
+    }
+
+    return result;
+}
+
+static rt_err_t nu_tpwm_set(struct rt_device_pwm *tpwm_dev, struct rt_pwm_configuration *tpwm_config)
+{
+    if (tpwm_config->period <= 0)
+        return -(RT_ERROR);
+
+    rt_uint32_t tpwm_freq, tpwm_dutycycle ;
+    rt_uint32_t tpwm_period = tpwm_config->period;
+    rt_uint32_t tpwm_pulse = tpwm_config->pulse;
+    nu_tpwm_t *nu_tpwm = NU_TPWM_DEVICE(tpwm_dev->parent.user_data);
+
+    rt_uint32_t pre_tpwm_prescaler = TPWM_GET_PRESCALER(nu_tpwm->tpwm_base);
+
+    tpwm_freq = 1000000000 / tpwm_period;
+    tpwm_dutycycle = (tpwm_pulse * 100) / tpwm_period;
+
+    TPWM_ConfigOutputFreqAndDuty(nu_tpwm->tpwm_base, tpwm_freq, tpwm_dutycycle) ;
+
+    return RT_EOK;
+}
+
+static rt_err_t nu_tpwm_get(struct rt_device_pwm *tpwm_dev, struct rt_pwm_configuration *tpwm_config)
+{
+    rt_uint32_t tpwm_real_period, tpwm_real_duty, time_tick, u32TPWMClockFreq ;
+
+    nu_tpwm_t *nu_tpwm = NU_TPWM_DEVICE(tpwm_dev->parent.user_data);
+    rt_uint32_t tpwm_prescale = TPWM_GET_PRESCALER(nu_tpwm->tpwm_base);
+    rt_uint32_t tpwm_period = TPWM_GET_PERIOD(nu_tpwm->tpwm_base);
+    rt_uint32_t tpwm_pulse = TPWM_GET_CMPDAT(nu_tpwm->tpwm_base);
+
+    u32TPWMClockFreq = TIMER_GetModuleClock(nu_tpwm->tpwm_base);
+    time_tick = 1000000000000 / u32TPWMClockFreq;
+
+    tpwm_real_period = (((tpwm_prescale + 1) * (tpwm_period + 1)) * time_tick) / 1000;
+    tpwm_real_duty = (((tpwm_prescale + 1) * tpwm_pulse * time_tick)) / 1000;
+    tpwm_config->period = tpwm_real_period;
+    tpwm_config->pulse = tpwm_real_duty;
+
+    LOG_I("%s %d %d %d\n", nu_tpwm->name, tpwm_config->channel, tpwm_config->period, tpwm_config->pulse);
+
+    return RT_EOK;
+}
+
+static rt_err_t nu_tpwm_control(struct rt_device_pwm *tpwm_dev, int cmd, void *arg)
+{
+    struct rt_pwm_configuration *tpwm_config = (struct rt_pwm_configuration *)arg;
+
+    RT_ASSERT(tpwm_dev != RT_NULL);
+    RT_ASSERT(tpwm_config != RT_NULL);
+
+    nu_tpwm_t *nu_tpwm = NU_TPWM_DEVICE(tpwm_dev->parent.user_data);
+    RT_ASSERT(nu_tpwm != RT_NULL);
+    RT_ASSERT(nu_tpwm->tpwm_base != RT_NULL);
+
+    if ((tpwm_config->channel + 1) > TPWM_CHANNEL_NUM)
+        return -(RT_ERROR);
+
+    switch (cmd)
+    {
+    case PWM_CMD_ENABLE:
+        return nu_tpwm_enable(tpwm_dev, tpwm_config, RT_TRUE);
+    case PWM_CMD_DISABLE:
+        return nu_tpwm_enable(tpwm_dev, tpwm_config, RT_FALSE);
+    case PWM_CMD_SET:
+        return nu_tpwm_set(tpwm_dev, tpwm_config);
+    case PWM_CMD_GET:
+        return nu_tpwm_get(tpwm_dev, tpwm_config);
+    default:
+        break;
+    }
+    return -(RT_EINVAL);
+}
+
+int rt_hw_tpwm_init(void)
+{
+    rt_err_t ret = RT_EOK;
+
+#ifdef BSP_USING_TPWM0
+    nu_tpwm0.tpwm_base = TIMER0;
+    nu_tpwm0.name = "tpwm0";
+    nu_tpwm0.channel_mask = 0;
+    ret = rt_device_pwm_register(&nu_tpwm0.tpwm_dev, nu_tpwm0.name, &nu_tpwm_ops, &nu_tpwm0);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("tpwm0 register failed\n");
+    }
+    SYS_ResetModule(TMR0_RST);
+    CLK_EnableModuleClock(TMR0_MODULE);
+    TPWM_ENABLE_PWM_MODE(TIMER0);
+#endif
+
+#ifdef BSP_USING_TPWM1
+    nu_tpwm1.tpwm_base = TIMER1;
+    nu_tpwm1.name = "tpwm1";
+    nu_tpwm1.channel_mask = 0;
+    ret = rt_device_pwm_register(&nu_tpwm1.tpwm_dev, nu_tpwm1.name, &nu_tpwm_ops, &nu_tpwm1);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("tpwm1 register failed\n");
+    }
+    SYS_ResetModule(TMR1_RST);
+    CLK_EnableModuleClock(TMR1_MODULE);
+    TPWM_ENABLE_PWM_MODE(TIMER1);
+#endif
+
+#ifdef BSP_USING_TPWM2
+    nu_tpwm2.tpwm_base = TIMER2;
+    nu_tpwm2.name = "tpwm2";
+    nu_tpwm2.channel_mask = 0;
+    ret = rt_device_pwm_register(&nu_tpwm2.tpwm_dev, nu_tpwm2.name, &nu_tpwm_ops, &nu_tpwm2);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("tpwm2 register failed\n");
+    }
+    SYS_ResetModule(TMR2_RST);
+    CLK_EnableModuleClock(TMR2_MODULE);
+    TPWM_ENABLE_PWM_MODE(TIMER2);
+#endif
+
+#ifdef BSP_USING_TPWM3
+    nu_tpwm3.tpwm_base = TIMER3;
+    nu_tpwm3.name = "tpwm3";
+    nu_tpwm3.channel_mask = 0;
+    ret = rt_device_pwm_register(&nu_tpwm3.tpwm_dev, nu_tpwm3.name, &nu_tpwm_ops, &nu_tpwm3);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("tpwm3 register failed\n");
+    }
+    SYS_ResetModule(TMR3_RST);
+    CLK_EnableModuleClock(TMR3_MODULE);
+    TPWM_ENABLE_PWM_MODE(TIMER3);
+#endif
+
+#ifdef BSP_USING_TPWM4
+    nu_tpwm4.tpwm_base = TIMER4;
+    nu_tpwm4.name = "tpwm4";
+    nu_tpwm4.channel_mask = 0;
+    ret = rt_device_pwm_register(&nu_tpwm4.tpwm_dev, nu_tpwm4.name, &nu_tpwm_ops, &nu_tpwm4);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("tpwm4 register failed\n");
+    }
+    SYS_ResetModule(TMR4_RST);
+    CLK_EnableModuleClock(TMR4_MODULE);
+    TPWM_ENABLE_PWM_MODE(TIMER4);
+#endif
+
+#ifdef BSP_USING_TPWM5
+    nu_tpwm5.tpwm_base = TIMER5;
+    nu_tpwm5.name = "tpwm5";
+    nu_tpwm5.channel_mask = 0;
+    ret = rt_device_pwm_register(&nu_tpwm5.tpwm_dev, nu_tpwm5.name, &nu_tpwm_ops, &nu_tpwm5);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("tpwm5 register failed\n");
+    }
+    SYS_ResetModule(TMR5_RST);
+    CLK_EnableModuleClock(TMR5_MODULE);
+    TPWM_ENABLE_PWM_MODE(TIMER5);
+#endif
+
+    return ret;
+}
+
+INIT_DEVICE_EXPORT(rt_hw_tpwm_init);
+
+#endif //#if (defined(BSP_USING_TPWM) && defined(RT_USING_PWM))
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_trng.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_trng.c
new file mode 100644
index 0000000000..5640494ce4
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_trng.c
@@ -0,0 +1,83 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-7-4        YCHuang12        First version
+*
+******************************************************************************/
+
+#include 
+
+#if (defined(BSP_USING_TRNG) && defined(RT_HWCRYPTO_USING_RNG))
+
+#include 
+#include "NuMicro.h"
+#include 
+
+#define NU_CRYPTO_TRNG_NAME "nu_TRNG"
+
+/* Private variables ------------------------------------------------------------*/
+static struct rt_mutex s_TRNG_mutex;
+static int s_i32TRNGEnable = 0;
+
+static rt_uint32_t nu_trng_run(void)
+{
+    uint32_t u32RNGValue;
+    rt_err_t result;
+
+    result = rt_mutex_take(&s_TRNG_mutex, RT_WAITING_FOREVER);
+    RT_ASSERT(result == RT_EOK);
+
+    RNG_Open();
+
+    if (RNG_Random(&u32RNGValue, 1) < 0)
+    {
+        //Failed, use software rand
+        u32RNGValue = rand();
+    }
+
+    result = rt_mutex_release(&s_TRNG_mutex);
+    RT_ASSERT(result == RT_EOK);
+
+    return u32RNGValue;
+}
+
+rt_err_t nu_trng_init(void)
+{
+    rt_err_t result;
+
+    result = rt_mutex_init(&s_TRNG_mutex, NU_CRYPTO_TRNG_NAME, RT_IPC_FLAG_FIFO);
+    RT_ASSERT(result == RT_EOK);
+
+    s_i32TRNGEnable = 1;
+    SYS_ResetModule(TRNG_RST);
+    return RT_EOK;
+}
+
+void nu_trng_open(void)
+{
+#if defined(NU_PRNG_USE_SEED)
+    srand(NU_PRNG_SEED_VALUE);
+#else
+    srand(rt_tick_get());
+#endif
+}
+
+rt_uint32_t nu_trng_rand(struct hwcrypto_rng *ctx)
+{
+    if (!s_i32TRNGEnable)
+    {
+        uint32_t u32RNGValue;
+        //use software rand
+        u32RNGValue = rand();
+        return u32RNGValue;
+    }
+
+    return nu_trng_run();
+}
+
+#endif //#if (defined(BSP_USING_TRNG) && defined(RT_HWCRYPTO_USING_RNG))
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_trng.h b/bsp/nuvoton/libraries/m2354/rtt_port/drv_trng.h
new file mode 100644
index 0000000000..4b68efc619
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_trng.h
@@ -0,0 +1,20 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-7-4        YCHuang12        First version
+*
+******************************************************************************/
+
+#ifndef __DRV_TRNG_H__
+#define __DRV_TRNG_H__
+
+rt_err_t nu_trng_init(void);
+void nu_trng_open(void);
+rt_uint32_t nu_trng_rand(struct hwcrypto_rng *ctx);
+
+#endif
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_uart.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_uart.c
new file mode 100644
index 0000000000..970d918bd1
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_uart.c
@@ -0,0 +1,793 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author       Notes
+* 2020-6-7        Wayne        First version
+*
+******************************************************************************/
+
+#include 
+
+#if defined(BSP_USING_UART)
+
+#include 
+#include 
+#include "NuMicro.h"
+#include 
+
+#if defined(RT_SERIAL_USING_DMA)
+    #include 
+#endif
+
+/* Private define ---------------------------------------------------------------*/
+enum
+{
+    UART_START = -1,
+#if defined(BSP_USING_UART0)
+    UART0_IDX,
+#endif
+#if defined(BSP_USING_UART1)
+    UART1_IDX,
+#endif
+#if defined(BSP_USING_UART2)
+    UART2_IDX,
+#endif
+#if defined(BSP_USING_UART3)
+    UART3_IDX,
+#endif
+#if defined(BSP_USING_UART4)
+    UART4_IDX,
+#endif
+#if defined(BSP_USING_UART5)
+    UART5_IDX,
+#endif
+    UART_CNT
+};
+
+/* Private typedef --------------------------------------------------------------*/
+struct nu_uart
+{
+    rt_serial_t dev;
+    char *name;
+    UART_T *uart_base;
+    uint32_t uart_rst;
+    IRQn_Type uart_irq_n;
+
+#if defined(RT_SERIAL_USING_DMA)
+    uint32_t dma_flag;
+    int16_t pdma_perp_tx;
+    int8_t  pdma_chanid_tx;
+
+    int16_t pdma_perp_rx;
+    int8_t  pdma_chanid_rx;
+    int32_t rx_write_offset;
+    int32_t rxdma_trigger_len;
+#endif
+
+};
+typedef struct nu_uart *nu_uart_t;
+
+/* Private functions ------------------------------------------------------------*/
+static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg);
+static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *arg);
+static int nu_uart_send(struct rt_serial_device *serial, char c);
+static int nu_uart_receive(struct rt_serial_device *serial);
+static void nu_uart_isr(nu_uart_t serial);
+
+#if defined(RT_SERIAL_USING_DMA)
+    static rt_size_t nu_uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction);
+    static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events);
+    static void nu_pdma_uart_tx_cb(void *pvOwner, uint32_t u32Events);
+#endif
+
+/* Public functions ------------------------------------------------------------*/
+
+/* Private variables ------------------------------------------------------------*/
+
+static const struct rt_uart_ops nu_uart_ops =
+{
+    .configure = nu_uart_configure,
+    .control = nu_uart_control,
+    .putc = nu_uart_send,
+    .getc = nu_uart_receive,
+#if defined(RT_SERIAL_USING_DMA)
+    .dma_transmit = nu_uart_dma_transmit
+#else
+    .dma_transmit = RT_NULL
+#endif
+};
+
+static const struct serial_configure nu_uart_default_config =
+        RT_SERIAL_CONFIG_DEFAULT;
+
+static struct nu_uart nu_uart_arr [] =
+{
+#if defined(BSP_USING_UART0)
+    {
+        .name = "uart0",
+        .uart_base = UART0,
+        .uart_rst = UART0_RST,
+        .uart_irq_n = UART0_IRQn,
+
+#if defined(RT_SERIAL_USING_DMA)
+#if defined(BSP_USING_UART0_TX_DMA)
+        .pdma_perp_tx = PDMA_UART0_TX,
+#else
+        .pdma_perp_tx = NU_PDMA_UNUSED,
+#endif
+#if defined(BSP_USING_UART0_RX_DMA)
+        .pdma_perp_rx = PDMA_UART0_RX,
+        .rx_write_offset = 0,
+#else
+        .pdma_perp_rx = NU_PDMA_UNUSED,
+#endif
+#endif
+    },
+#endif
+
+#if defined(BSP_USING_UART1)
+    {
+        .name = "uart1",
+        .uart_base = UART1,
+        .uart_rst = UART1_RST,
+        .uart_irq_n = UART1_IRQn,
+#if defined(RT_SERIAL_USING_DMA)
+#if defined(BSP_USING_UART1_TX_DMA)
+        .pdma_perp_tx = PDMA_UART1_TX,
+#else
+        .pdma_perp_tx = NU_PDMA_UNUSED,
+#endif
+#if defined(BSP_USING_UART1_RX_DMA)
+        .pdma_perp_rx = PDMA_UART1_RX,
+        .rx_write_offset = 0,
+#else
+        .pdma_perp_rx = NU_PDMA_UNUSED,
+#endif
+#endif
+    },
+#endif
+
+#if defined(BSP_USING_UART2)
+    {
+        .name = "uart2",
+        .uart_base = UART2,
+        .uart_rst = UART2_RST,
+        .uart_irq_n = UART2_IRQn,
+#if defined(RT_SERIAL_USING_DMA)
+#if defined(BSP_USING_UART2_TX_DMA)
+        .pdma_perp_tx = PDMA_UART2_TX,
+#else
+        .pdma_perp_tx = NU_PDMA_UNUSED,
+#endif
+#if defined(BSP_USING_UART2_RX_DMA)
+        .pdma_perp_rx = PDMA_UART2_RX,
+        .rx_write_offset = 0,
+#else
+        .pdma_perp_rx = NU_PDMA_UNUSED,
+#endif
+#endif
+    },
+#endif
+
+#if defined(BSP_USING_UART3)
+    {
+        .name = "uart3",
+        .uart_base = UART3,
+        .uart_rst = UART3_RST,
+        .uart_irq_n = UART3_IRQn,
+#if defined(RT_SERIAL_USING_DMA)
+#if defined(BSP_USING_UART3_TX_DMA)
+        .pdma_perp_tx = PDMA_UART3_TX,
+#else
+        .pdma_perp_tx = NU_PDMA_UNUSED,
+#endif
+#if defined(BSP_USING_UART3_RX_DMA)
+        .pdma_perp_rx = PDMA_UART3_RX,
+        .rx_write_offset = 0,
+#else
+        .pdma_perp_rx = NU_PDMA_UNUSED,
+#endif
+#endif
+    },
+#endif
+
+#if defined(BSP_USING_UART4)
+    {
+        .name = "uart4",
+        .uart_base = UART4,
+        .uart_rst = UART4_RST,
+        .uart_irq_n = UART4_IRQn,
+#if defined(RT_SERIAL_USING_DMA)
+#if defined(BSP_USING_UART4_TX_DMA)
+        .pdma_perp_tx = PDMA_UART4_TX,
+#else
+        .pdma_perp_tx = NU_PDMA_UNUSED,
+#endif
+#if defined(BSP_USING_UART4_RX_DMA)
+        .pdma_perp_rx = PDMA_UART4_RX,
+        .rx_write_offset = 0,
+#else
+        .pdma_perp_rx = NU_PDMA_UNUSED,
+#endif
+#endif
+    },
+#endif
+
+#if defined(BSP_USING_UART5)
+    {
+        .name = "uart5",
+        .uart_base = UART5,
+        .uart_rst = UART5_RST,
+        .uart_irq_n = UART5_IRQn,
+#if defined(RT_SERIAL_USING_DMA)
+#if defined(BSP_USING_UART5_TX_DMA)
+        .pdma_perp_tx = PDMA_UART5_TX,
+#else
+        .pdma_perp_tx = NU_PDMA_UNUSED,
+#endif
+#if defined(BSP_USING_UART5_RX_DMA)
+        .pdma_perp_rx = PDMA_UART5_RX,
+        .rx_write_offset = 0,
+#else
+        .pdma_perp_rx = NU_PDMA_UNUSED,
+#endif
+#endif
+    },
+#endif
+    {0}
+}; /* uart nu_uart */
+
+/* Interrupt Handle Function  ----------------------------------------------------*/
+#if defined(BSP_USING_UART0)
+/* UART0 interrupt entry */
+void UART0_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    nu_uart_isr(&nu_uart_arr[UART0_IDX]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_UART1)
+/* UART1 interrupt entry */
+void UART1_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    nu_uart_isr(&nu_uart_arr[UART1_IDX]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_UART2)
+/* UART2 interrupt entry */
+void UART2_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    nu_uart_isr(&nu_uart_arr[UART2_IDX]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_UART3)
+/* UART3 interrupt service routine */
+void UART3_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    nu_uart_isr(&nu_uart_arr[UART3_IDX]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_UART4)
+/* UART4 interrupt entry */
+void UART4_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    nu_uart_isr(&nu_uart_arr[UART4_IDX]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_UART5)
+/* UART5 interrupt entry */
+void UART5_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    nu_uart_isr(&nu_uart_arr[UART5_IDX]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+/**
+ * All UART interrupt service routine
+ */
+static void nu_uart_isr(nu_uart_t serial)
+{
+    /* Get base address of uart register */
+    UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
+
+    /* Get interrupt event */
+    uint32_t u32IntSts = uart_base->INTSTS;
+    uint32_t u32FIFOSts = uart_base->FIFOSTS;
+
+#if defined(RT_SERIAL_USING_DMA)
+    if (u32IntSts & UART_INTSTS_HWRLSIF_Msk)
+    {
+        /* Drain RX FIFO to remove remain FEF frames in FIFO. */
+        uart_base->FIFO |= UART_FIFO_RXRST_Msk;
+        uart_base->FIFOSTS |= (UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_PEF_Msk);
+        return;
+    }
+#endif
+
+    /* Handle RX event */
+    if (u32IntSts & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk))
+    {
+        rt_hw_serial_isr(&serial->dev, RT_SERIAL_EVENT_RX_IND);
+    }
+    uart_base->INTSTS = u32IntSts;
+    uart_base->FIFOSTS = u32FIFOSts;
+}
+
+/**
+ * Configure uart port
+ */
+static rt_err_t nu_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    rt_err_t ret = RT_EOK;
+    uint32_t uart_word_len = 0;
+    uint32_t uart_stop_bit = 0;
+    uint32_t uart_parity = 0;
+
+    /* Get base address of uart register */
+    UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
+
+    /* Check baudrate */
+    RT_ASSERT(cfg->baud_rate != 0);
+
+    /* Check word len */
+    switch (cfg->data_bits)
+    {
+    case DATA_BITS_5:
+        uart_word_len = UART_WORD_LEN_5;
+        break;
+
+    case DATA_BITS_6:
+        uart_word_len = UART_WORD_LEN_6;
+        break;
+
+    case DATA_BITS_7:
+        uart_word_len = UART_WORD_LEN_7;
+        break;
+
+    case DATA_BITS_8:
+        uart_word_len = UART_WORD_LEN_8;
+        break;
+
+    default:
+        rt_kprintf("Unsupported data length");
+        ret = RT_EINVAL;
+        goto exit_nu_uart_configure;
+    }
+
+    /* Check stop bit */
+    switch (cfg->stop_bits)
+    {
+    case STOP_BITS_1:
+        uart_stop_bit = UART_STOP_BIT_1;
+        break;
+
+    case STOP_BITS_2:
+        uart_stop_bit = UART_STOP_BIT_2;
+        break;
+
+    default:
+        rt_kprintf("Unsupported stop bit");
+        ret = RT_EINVAL;
+        goto exit_nu_uart_configure;
+    }
+
+    /* Check parity */
+    switch (cfg->parity)
+    {
+    case PARITY_NONE:
+        uart_parity = UART_PARITY_NONE;
+        break;
+
+    case PARITY_ODD:
+        uart_parity = UART_PARITY_ODD;
+        break;
+
+    case PARITY_EVEN:
+        uart_parity = UART_PARITY_EVEN;
+        break;
+
+    default:
+        rt_kprintf("Unsupported parity");
+        ret = RT_EINVAL;
+        goto exit_nu_uart_configure;
+    }
+
+    /* Reset this module */
+    SYS_ResetModule(((nu_uart_t)serial)->uart_rst);
+
+    /* Open Uart and set UART Baudrate */
+    UART_Open(uart_base, cfg->baud_rate);
+
+    /* Set line configuration. */
+    UART_SetLineConfig(uart_base, 0, uart_word_len, uart_parity, uart_stop_bit);
+
+    /* Enable NVIC interrupt. */
+    NVIC_EnableIRQ(((nu_uart_t)serial)->uart_irq_n);
+
+exit_nu_uart_configure:
+
+    if (ret != RT_EOK)
+        UART_Close(uart_base);
+
+    return -(ret);
+}
+
+#if defined(RT_SERIAL_USING_DMA)
+static rt_err_t nu_pdma_uart_rx_config(struct rt_serial_device *serial, uint8_t *pu8Buf, int32_t i32TriggerLen)
+{
+    rt_err_t result = RT_EOK;
+
+    /* Get base address of uart register */
+    UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
+
+    result = nu_pdma_callback_register(((nu_uart_t)serial)->pdma_chanid_rx,
+                                       nu_pdma_uart_rx_cb,
+                                       (void *)serial,
+                                       NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT);
+    if (result != RT_EOK)
+    {
+        goto exit_nu_pdma_uart_rx_config;
+    }
+
+    result = nu_pdma_transfer(((nu_uart_t)serial)->pdma_chanid_rx,
+                              8,
+                              (uint32_t)uart_base,
+                              (uint32_t)pu8Buf,
+                              i32TriggerLen,
+                              1000);  //Idle-timeout, 1ms
+    if (result != RT_EOK)
+    {
+        goto exit_nu_pdma_uart_rx_config;
+    }
+
+    /* Enable Receive Line interrupt & Start DMA RX transfer. */
+    UART_ENABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk);
+    UART_PDMA_ENABLE(uart_base, UART_INTEN_RXPDMAEN_Msk);
+
+
+exit_nu_pdma_uart_rx_config:
+
+    return result;
+}
+
+static void nu_pdma_uart_rx_cb(void *pvOwner, uint32_t u32Events)
+{
+    rt_size_t recv_len = 0;
+    rt_size_t transferred_rxbyte = 0;
+    struct rt_serial_device *serial = (struct rt_serial_device *)pvOwner;
+    nu_uart_t puart = (nu_uart_t)serial;
+    RT_ASSERT(serial != RT_NULL);
+
+    /* Get base address of uart register */
+    UART_T *uart_base = puart->uart_base;
+
+    transferred_rxbyte = nu_pdma_transferred_byte_get(puart->pdma_chanid_rx, puart->rxdma_trigger_len);
+
+    if (u32Events & (NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT))
+    {
+        if (u32Events & NU_PDMA_EVENT_TRANSFER_DONE)
+        {
+            if (serial->config.bufsz != 0)
+            {
+                struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
+
+                nu_pdma_uart_rx_config(serial, &rx_fifo->buffer[0], puart->rxdma_trigger_len);     // Config & trigger next
+            }
+            else
+            {
+                UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk);
+                UART_PDMA_DISABLE(uart_base, UART_INTEN_RXPDMAEN_Msk);
+            }
+            transferred_rxbyte = puart->rxdma_trigger_len;
+        }
+        else if ((u32Events & NU_PDMA_EVENT_TIMEOUT) && !UART_GET_RX_EMPTY(uart_base))
+        {
+            return;
+        }
+
+        recv_len = transferred_rxbyte - puart->rx_write_offset;
+
+        puart->rx_write_offset = transferred_rxbyte % puart->rxdma_trigger_len;
+
+    }
+
+    if ((serial->config.bufsz == 0) && (u32Events & NU_PDMA_EVENT_TRANSFER_DONE))
+    {
+        recv_len = puart->rxdma_trigger_len;
+    }
+
+    if (recv_len)
+    {
+        rt_hw_serial_isr(&puart->dev, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
+    }
+}
+
+static rt_err_t nu_pdma_uart_tx_config(struct rt_serial_device *serial)
+{
+    rt_err_t result = RT_EOK;
+    RT_ASSERT(serial != RT_NULL);
+
+    result = nu_pdma_callback_register(((nu_uart_t)serial)->pdma_chanid_tx,
+                                       nu_pdma_uart_tx_cb,
+                                       (void *)serial,
+                                       NU_PDMA_EVENT_TRANSFER_DONE);
+
+    return result;
+}
+
+static void nu_pdma_uart_tx_cb(void *pvOwner, uint32_t u32Events)
+{
+    nu_uart_t puart = (nu_uart_t)pvOwner;
+
+    RT_ASSERT(puart != RT_NULL);
+
+    UART_PDMA_DISABLE(puart->uart_base, UART_INTEN_TXPDMAEN_Msk);// Stop DMA TX transfer
+
+    if (u32Events & NU_PDMA_EVENT_TRANSFER_DONE)
+    {
+        rt_hw_serial_isr(&puart->dev, RT_SERIAL_EVENT_TX_DMADONE);
+    }
+}
+
+/**
+ * Uart DMA transfer
+ */
+static rt_size_t nu_uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
+{
+    rt_err_t result = RT_EOK;
+
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(buf != RT_NULL);
+
+    /* Get base address of uart register */
+    UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
+    if (direction == RT_SERIAL_DMA_TX)
+    {
+        result = nu_pdma_transfer(((nu_uart_t)serial)->pdma_chanid_tx,
+                                  8,
+                                  (uint32_t)buf,
+                                  (uint32_t)uart_base,
+                                  size,
+                                  0);  // wait-forever
+        UART_PDMA_ENABLE(uart_base, UART_INTEN_TXPDMAEN_Msk);  // Start DMA TX transfer
+    }
+    else if (direction == RT_SERIAL_DMA_RX)
+    {
+        UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk);
+        UART_PDMA_DISABLE(uart_base, UART_INTEN_RXPDMAEN_Msk);
+        // If config.bufsz = 0, serial will trigger once.
+        ((nu_uart_t)serial)->rxdma_trigger_len = size;
+        ((nu_uart_t)serial)->rx_write_offset = 0;
+        result = nu_pdma_uart_rx_config(serial, buf, size);
+    }
+    else
+    {
+        result = RT_ERROR;
+    }
+
+    return result;
+}
+
+static int nu_hw_uart_dma_allocate(nu_uart_t pusrt)
+{
+    RT_ASSERT(pusrt != RT_NULL);
+
+    /* Allocate UART_TX nu_dma channel */
+    if (pusrt->pdma_perp_tx != NU_PDMA_UNUSED)
+    {
+        pusrt->pdma_chanid_tx = nu_pdma_channel_allocate(pusrt->pdma_perp_tx);
+        if (pusrt->pdma_chanid_tx >= 0)
+        {
+            pusrt->dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+        }
+    }
+
+    /* Allocate UART_RX nu_dma channel */
+    if (pusrt->pdma_perp_rx != NU_PDMA_UNUSED)
+    {
+        pusrt->pdma_chanid_rx = nu_pdma_channel_allocate(pusrt->pdma_perp_rx);
+        if (pusrt->pdma_chanid_rx >= 0)
+        {
+            pusrt->dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+        }
+    }
+
+    return RT_EOK;
+}
+#endif
+
+/**
+ * Uart interrupt control
+ */
+static rt_err_t nu_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    rt_err_t result = RT_EOK;
+    rt_uint32_t flag;
+    rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    /* Get base address of uart register */
+    UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Disable INT-RX */
+        {
+            flag = UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk;
+            UART_DISABLE_INT(uart_base, flag);
+        }
+        else if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Disable DMA-RX */
+        {
+            /* Disable Receive Line interrupt & Stop DMA RX transfer. */
+#if defined(RT_SERIAL_USING_DMA)
+            nu_pdma_channel_terminate(((nu_uart_t)serial)->pdma_chanid_rx);
+            UART_DISABLE_INT(uart_base, UART_INTEN_RLSIEN_Msk);
+            UART_PDMA_DISABLE(uart_base, UART_INTEN_RXPDMAEN_Msk);
+#endif
+        }
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Enable INT-RX */
+        {
+            flag = UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk | UART_INTEN_TOCNTEN_Msk;
+            UART_ENABLE_INT(uart_base, flag);
+        }
+        break;
+
+#if defined(RT_SERIAL_USING_DMA)
+    case RT_DEVICE_CTRL_CONFIG:
+        if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Configure and trigger DMA-RX */
+        {
+            struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
+            ((nu_uart_t)serial)->rxdma_trigger_len = serial->config.bufsz;
+            ((nu_uart_t)serial)->rx_write_offset = 0;
+            result = nu_pdma_uart_rx_config(serial, &rx_fifo->buffer[0], ((nu_uart_t)serial)->rxdma_trigger_len);  // Config & trigger
+        }
+        else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) /* Configure DMA-TX */
+        {
+            result = nu_pdma_uart_tx_config(serial);
+        }
+        break;
+#endif
+
+    case RT_DEVICE_CTRL_CLOSE:
+        /* Disable NVIC interrupt. */
+        NVIC_DisableIRQ(((nu_uart_t)serial)->uart_irq_n);
+
+#if defined(RT_SERIAL_USING_DMA)
+        nu_pdma_channel_terminate(((nu_uart_t)serial)->pdma_chanid_tx);
+        nu_pdma_channel_terminate(((nu_uart_t)serial)->pdma_chanid_rx);
+#endif
+
+        /* Reset this module */
+        SYS_ResetModule(((nu_uart_t)serial)->uart_rst);
+
+        /* Close UART port */
+        UART_Close(uart_base);
+
+        break;
+
+    default:
+        result = -RT_EINVAL;
+        break;
+
+    }
+    return result;
+}
+
+/**
+ * Uart put char
+ */
+static int nu_uart_send(struct rt_serial_device *serial, char c)
+{
+    RT_ASSERT(serial != RT_NULL);
+
+    /* Get base address of uart register */
+    UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
+
+    /* Waiting if TX-FIFO is full. */
+    while (UART_IS_TX_FULL(uart_base));
+
+    /* Put char into TX-FIFO */
+    UART_WRITE(uart_base, c);
+
+    return 1;
+}
+
+/**
+ * Uart get char
+ */
+static int nu_uart_receive(struct rt_serial_device *serial)
+{
+    RT_ASSERT(serial != RT_NULL);
+
+    /* Get base address of uart register */
+    UART_T *uart_base = ((nu_uart_t)serial)->uart_base;
+
+    /* Return failure if RX-FIFO is empty. */
+    if (UART_GET_RX_EMPTY(uart_base))
+    {
+        return -1;
+    }
+
+    /* Get char from RX-FIFO */
+    return UART_READ(uart_base);
+}
+
+/**
+ * Hardware UART Initialization
+ */
+rt_err_t rt_hw_uart_init(void)
+{
+    int i;
+    rt_uint32_t flag;
+    rt_err_t ret = RT_EOK;
+
+    for (i = (UART_START + 1); i < UART_CNT; i++)
+    {
+        flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX;
+
+        nu_uart_arr[i].dev.ops    = &nu_uart_ops;
+        nu_uart_arr[i].dev.config = nu_uart_default_config;
+
+#if defined(RT_SERIAL_USING_DMA)
+        nu_uart_arr[i].dma_flag = 0;
+        nu_hw_uart_dma_allocate(&nu_uart_arr[i]);
+        flag |= nu_uart_arr[i].dma_flag;
+#endif
+
+        ret = rt_hw_serial_register(&nu_uart_arr[i].dev, nu_uart_arr[i].name, flag, NULL);
+        RT_ASSERT(ret == RT_EOK);
+    }
+
+    return ret;
+}
+
+#endif //#if defined(BSP_USING_UART)
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_uart.h b/bsp/nuvoton/libraries/m2354/rtt_port/drv_uart.h
new file mode 100644
index 0000000000..21d8714b99
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_uart.h
@@ -0,0 +1,20 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-2-7        Wayne            First version
+*
+******************************************************************************/
+
+#ifndef __DRV_UART_H__
+#define __DRV_UART_H__
+
+#include 
+
+rt_err_t rt_hw_uart_init(void);
+
+#endif /* __DRV_UART_H__ */
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_ui2c.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_ui2c.c
new file mode 100644
index 0000000000..a2f2648f1a
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_ui2c.c
@@ -0,0 +1,377 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-6-31       Hphuang          First version
+*
+******************************************************************************/
+
+#include 
+
+#if (defined(BSP_USING_UI2C) && defined(RT_USING_I2C))
+
+#include 
+#include "NuMicro.h"
+
+/* Private define ---------------------------------------------------------------*/
+#define LOG_TAG          "drv.ui2c"
+#define DBG_ENABLE
+#define DBG_SECTION_NAME LOG_TAG
+#define DBG_LEVEL        DBG_INFO
+#define DBG_COLOR
+#include 
+
+#define SLV_10BIT_ADDR (0x1E<<2)             //1111+0xx+r/w
+
+/* Private typedef --------------------------------------------------------------*/
+typedef struct nu_ui2c_bus
+{
+    struct rt_i2c_bus_device ui2c_dev;
+    struct rt_i2c_msg *msg;
+    UI2C_T *ui2c_base;
+    char *dev_name;
+} nu_ui2c_bus_t;
+
+/* Private functions ------------------------------------------------------------*/
+static rt_size_t nu_ui2c_mst_xfer(struct rt_i2c_bus_device *ui2c_dev,
+                                  struct rt_i2c_msg msgs[],
+                                  rt_uint32_t num);
+
+static const struct rt_i2c_bus_device_ops nu_ui2c_ops =
+{
+    .master_xfer        = nu_ui2c_mst_xfer,
+    .slave_xfer         = NULL,
+    .i2c_bus_control    = NULL,
+};
+
+/* Private variables ------------------------------------------------------------*/
+#ifdef BSP_USING_UI2C0
+#define UI2C0BUS_NAME  "ui2c0"
+static nu_ui2c_bus_t nu_ui2c0 =
+{
+    .ui2c_base = UI2C0,
+    .dev_name = UI2C0BUS_NAME,
+};
+#endif /* BSP_USING_UI2C0 */
+
+#ifdef BSP_USING_UI2C1
+#define UI2C1BUS_NAME  "ui2c1"
+static nu_ui2c_bus_t nu_ui2c1 =
+{
+    .ui2c_base = UI2C1,
+    .dev_name = UI2C1BUS_NAME,
+};
+#endif /* BSP_USING_UI2C1 */
+
+/* Functions define ------------------------------------------------------------*/
+#if (defined(BSP_USING_UI2C0) || defined(BSP_USING_UI2C1))
+
+static inline rt_err_t nu_ui2c_wait_ready_with_timeout(nu_ui2c_bus_t *nu_ui2c)
+{
+    rt_tick_t start = rt_tick_get();
+    while (!(UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & (UI2C_PROTSTS_STARIF_Msk | UI2C_PROTSTS_ACKIF_Msk | UI2C_PROTSTS_NACKIF_Msk | UI2C_PROTSTS_STORIF_Msk)))
+    {
+        if ((rt_tick_get() - start) > nu_ui2c->ui2c_dev.timeout)
+        {
+            LOG_E("\nui2c: timeout!\n");
+            return -RT_ETIMEOUT;
+        }
+    }
+
+    return RT_EOK;
+}
+
+static inline rt_err_t nu_ui2c_send_data(nu_ui2c_bus_t *nu_ui2c, rt_uint8_t data)
+{
+    UI2C_SET_DATA(nu_ui2c->ui2c_base, data);
+    UI2C_SET_CONTROL_REG(nu_ui2c->ui2c_base, UI2C_CTL_PTRG);
+    return nu_ui2c_wait_ready_with_timeout(nu_ui2c);
+}
+
+static rt_err_t nu_ui2c_send_address(nu_ui2c_bus_t *nu_ui2c,
+                                     struct rt_i2c_msg  *msg)
+{
+    rt_uint16_t flags = msg->flags;
+    rt_uint16_t ignore_nack = msg->flags & RT_I2C_IGNORE_NACK;
+    rt_uint8_t addr1, addr2;
+    rt_err_t ret;
+
+    if (flags & RT_I2C_ADDR_10BIT)
+    {
+        UI2C_ENABLE_10BIT_ADDR_MODE(nu_ui2c->ui2c_base);
+        /* Init Send 10-bit Addr */
+        addr1 = ((msg->addr >> 8) | SLV_10BIT_ADDR) << 1;
+        addr2 = msg->addr & 0xff;
+
+        LOG_D("addr1: %d, addr2: %d\n", addr1, addr2);
+
+        ret = nu_ui2c_send_data(nu_ui2c, addr1);
+        if (ret != RT_EOK) //for timeout condition
+            return -RT_EIO;
+
+        if (((UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & UI2C_PROTSTS_ACKIF_Msk) != UI2C_PROTSTS_ACKIF_Msk) && !ignore_nack)
+        {
+            LOG_E("NACK: sending first addr\n");
+
+            return -RT_EIO;
+        }
+        UI2C_CLR_PROT_INT_FLAG(nu_ui2c->ui2c_base, UI2C_PROTSTS_ACKIF_Msk);
+
+        ret = nu_ui2c_send_data(nu_ui2c,  addr2);
+        if (ret != RT_EOK) //for timeout condition
+            return -RT_EIO;
+
+        if (((UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & UI2C_PROTSTS_ACKIF_Msk) != UI2C_PROTSTS_ACKIF_Msk) && !ignore_nack)
+        {
+            LOG_E("NACK: sending second addr\n");
+
+            return -RT_EIO;
+        }
+        UI2C_CLR_PROT_INT_FLAG(nu_ui2c->ui2c_base, UI2C_PROTSTS_ACKIF_Msk);
+
+        if (flags & RT_I2C_RD)
+        {
+            LOG_D("send repeated start condition\n");
+
+            UI2C_SET_CONTROL_REG(nu_ui2c->ui2c_base, (UI2C_CTL_PTRG | UI2C_CTL_STA));
+            ret = nu_ui2c_wait_ready_with_timeout(nu_ui2c);
+            if (ret != RT_EOK) //for timeout condition
+                return -RT_EIO;
+
+            if (((UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & UI2C_PROTSTS_STARIF_Msk) != UI2C_PROTSTS_STARIF_Msk) && !ignore_nack)
+            {
+                LOG_E("sending repeated START fail\n");
+
+                return -RT_EIO;
+            }
+            UI2C_CLR_PROT_INT_FLAG(nu_ui2c->ui2c_base, UI2C_PROTSTS_STARIF_Msk);
+
+            addr1 |= RT_I2C_RD;
+
+            ret = nu_ui2c_send_data(nu_ui2c,  addr1);
+            if (ret != RT_EOK) //for timeout condition
+                return -RT_EIO;
+
+            if (((UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & UI2C_PROTSTS_ACKIF_Msk) != UI2C_PROTSTS_ACKIF_Msk) && !ignore_nack)
+            {
+                LOG_E("NACK: sending repeated addr\n");
+                return -RT_EIO;
+            }
+            UI2C_CLR_PROT_INT_FLAG(nu_ui2c->ui2c_base, UI2C_PROTSTS_ACKIF_Msk);
+        }
+    }
+    else
+    {
+        /* 7-bit addr */
+        addr1 = msg->addr << 1;
+        if (flags & RT_I2C_RD)
+            addr1 |= RT_I2C_RD;
+
+        /* Send device address */
+        ret = nu_ui2c_send_data(nu_ui2c,  addr1); /* Send Address */
+        if (ret != RT_EOK) //for timeout condition
+            return -RT_EIO;
+
+        if (((UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & UI2C_PROTSTS_ACKIF_Msk) != UI2C_PROTSTS_ACKIF_Msk)
+                && !ignore_nack)
+        {
+            LOG_E("sending addr fail\n");
+            return -RT_EIO;
+        }
+        UI2C_CLR_PROT_INT_FLAG(nu_ui2c->ui2c_base, UI2C_PROTSTS_ACKIF_Msk);
+    }
+
+    return RT_EOK;
+}
+
+static rt_size_t nu_ui2c_mst_xfer(struct rt_i2c_bus_device *bus,
+                                  struct rt_i2c_msg msgs[],
+                                  rt_uint32_t num)
+{
+    struct rt_i2c_msg *msg;
+    nu_ui2c_bus_t *nu_ui2c;
+    rt_size_t i;
+    rt_uint32_t cnt_data;
+    rt_uint16_t ignore_nack;
+    rt_err_t ret;
+
+    RT_ASSERT(bus != RT_NULL);
+    nu_ui2c = (nu_ui2c_bus_t *) bus;
+
+    nu_ui2c->msg = msgs;
+
+    (nu_ui2c->ui2c_base)->PROTSTS = (nu_ui2c->ui2c_base)->PROTSTS;//Clear status
+
+    UI2C_SET_CONTROL_REG(nu_ui2c->ui2c_base, UI2C_CTL_STA);
+    ret = nu_ui2c_wait_ready_with_timeout(nu_ui2c);
+
+    if (ret != RT_EOK) //for timeout condition
+    {
+        rt_set_errno(-RT_ETIMEOUT);
+        return 0;
+    }
+
+    if (((UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & UI2C_PROTSTS_STARIF_Msk) != UI2C_PROTSTS_STARIF_Msk)) /* Check Send START */
+    {
+        i = 0;
+        LOG_E("Send START Fail");
+        return i;
+    }
+    UI2C_CLR_PROT_INT_FLAG(nu_ui2c->ui2c_base, UI2C_PROTSTS_STARIF_Msk);
+
+    for (i = 0; i < num; i++)
+    {
+        msg = &msgs[i];
+        ignore_nack = msg->flags & RT_I2C_IGNORE_NACK;
+
+        if (!(msg->flags & RT_I2C_NO_START))
+        {
+            if (i)
+            {
+                UI2C_SET_CONTROL_REG(nu_ui2c->ui2c_base, (UI2C_CTL_PTRG | UI2C_CTL_STA));/* Send repeat START */
+                ret = nu_ui2c_wait_ready_with_timeout(nu_ui2c);
+                if (ret != RT_EOK) //for timeout condition
+                    break;
+
+                if (((UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & UI2C_PROTSTS_STARIF_Msk) != UI2C_PROTSTS_STARIF_Msk)) /* Check Send repeat START */
+                {
+                    i = 0;
+                    LOG_E("Send repeat START Fail");
+                    break;
+                }
+                UI2C_CLR_PROT_INT_FLAG(nu_ui2c->ui2c_base, UI2C_PROTSTS_STARIF_Msk);
+            }
+
+            if ((RT_EOK != nu_ui2c_send_address(nu_ui2c, msg))
+                    && !ignore_nack)
+            {
+                i = 0;
+                LOG_E("Send Address Fail");
+                break;
+            }
+        }
+
+        if (nu_ui2c->msg[i].flags & RT_I2C_RD) /* Receive Bytes */
+        {
+            rt_uint32_t do_rd_nack = (i == (num - 1));
+            for (cnt_data = 0 ; cnt_data < (nu_ui2c->msg[i].len) ; cnt_data++)
+            {
+                do_rd_nack += (cnt_data == (nu_ui2c->msg[i].len - 1)); /* NACK after last byte  for hardware setting */
+                if (do_rd_nack == 2)
+                {
+                    UI2C_SET_CONTROL_REG(nu_ui2c->ui2c_base, UI2C_CTL_PTRG);
+                }
+                else
+                {
+                    UI2C_SET_CONTROL_REG(nu_ui2c->ui2c_base, (UI2C_CTL_PTRG | UI2C_CTL_AA));
+                }
+
+                ret = nu_ui2c_wait_ready_with_timeout(nu_ui2c);
+                if (ret != RT_EOK) //for timeout condition
+                    break;
+
+                if (nu_ui2c->ui2c_base->PROTCTL & UI2C_CTL_AA)
+                {
+                    if (((UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & UI2C_PROTSTS_ACKIF_Msk) != UI2C_PROTSTS_ACKIF_Msk)) /*Master Receive Data ACK*/
+                    {
+                        i = 0;
+                        break;
+                    }
+                    UI2C_CLR_PROT_INT_FLAG(nu_ui2c->ui2c_base, UI2C_PROTSTS_ACKIF_Msk);
+                }
+                else
+                {
+                    if (((UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & UI2C_PROTSTS_NACKIF_Msk) != UI2C_PROTSTS_NACKIF_Msk)) /*Master Receive Data NACK*/
+                    {
+                        i = 0;
+                        break;
+                    }
+                    UI2C_CLR_PROT_INT_FLAG(nu_ui2c->ui2c_base, UI2C_PROTSTS_NACKIF_Msk);
+                }
+
+                nu_ui2c->msg[i].buf[cnt_data] = nu_ui2c->ui2c_base->RXDAT;
+            }
+        }
+        else /* Send Bytes */
+        {
+            for (cnt_data = 0 ; cnt_data < (nu_ui2c->msg[i].len) ; cnt_data++)
+            {
+                /* Send register number and MSB of data */
+                ret = nu_ui2c_send_data(nu_ui2c, (uint8_t)(nu_ui2c->msg[i].buf[cnt_data]));
+                if (ret != RT_EOK) //for timeout condition
+                    break;
+
+                if (((UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & UI2C_PROTSTS_ACKIF_Msk) != UI2C_PROTSTS_ACKIF_Msk)
+                        && !ignore_nack
+                   ) /* Send data and get Ack */
+                {
+                    i = 0;
+                    break;
+                }
+                UI2C_CLR_PROT_INT_FLAG(nu_ui2c->ui2c_base, UI2C_PROTSTS_ACKIF_Msk);
+            }
+        }
+    }
+
+    UI2C_SET_CONTROL_REG(nu_ui2c->ui2c_base, (UI2C_CTL_PTRG | UI2C_CTL_STO));            /* Send STOP signal */
+    ret = nu_ui2c_wait_ready_with_timeout(nu_ui2c);
+    if (ret != RT_EOK) //for timeout condition
+    {
+        rt_set_errno(-RT_ETIMEOUT);
+        return 0;
+    }
+
+    RT_ASSERT(((UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & UI2C_PROTSTS_STORIF_Msk) == UI2C_PROTSTS_STORIF_Msk));
+    if (((UI2C_GET_PROT_STATUS(nu_ui2c->ui2c_base) & UI2C_PROTSTS_STORIF_Msk) != UI2C_PROTSTS_STORIF_Msk)) /* Bus Free*/
+    {
+        i = 0;
+        LOG_E("Send STOP Fail");
+    }
+
+    UI2C_CLR_PROT_INT_FLAG(nu_ui2c->ui2c_base, UI2C_PROTSTS_STORIF_Msk);
+    UI2C_SET_CONTROL_REG(nu_ui2c->ui2c_base, UI2C_CTL_PTRG);
+    UI2C_DISABLE_10BIT_ADDR_MODE(nu_ui2c->ui2c_base); /*clear all sub modes like 10 bit mode*/
+    nu_ui2c->msg = RT_NULL;
+
+    return i;
+}
+
+#endif //(defined(BSP_USING_UI2C0) || defined(BSP_USING_UI2C1))
+
+/* Public functions -------------------------------------------------------------*/
+int rt_hw_ui2c_init(void)
+{
+    rt_err_t ret = RT_ERROR;
+
+#if defined(BSP_USING_UI2C0)
+    SYS_UnlockReg();
+    SYS_ResetModule(USCI0_RST);
+    SYS_LockReg();
+
+    nu_ui2c0.ui2c_dev.ops = &nu_ui2c_ops;
+    UI2C_Open(nu_ui2c0.ui2c_base, 100000);
+    ret = rt_i2c_bus_device_register(&nu_ui2c0.ui2c_dev, nu_ui2c0.dev_name);
+    RT_ASSERT(RT_EOK == ret);
+#endif  /* BSP_USING_UI2C0 */
+
+#if defined(BSP_USING_UI2C1)
+    SYS_UnlockReg();
+    SYS_ResetModule(USCI1_RST);
+    SYS_LockReg();
+
+    nu_ui2c1.ui2c_dev.ops = &nu_ui2c_ops;
+    UI2C_Open(nu_ui2c1.ui2c_base, 100000);
+    ret = rt_i2c_bus_device_register(&nu_ui2c1.ui2c_dev, nu_ui2c1.dev_name);
+    RT_ASSERT(RT_EOK == ret);
+#endif  /* BSP_USING_UI2C1 */
+
+    return ret;
+}
+
+INIT_DEVICE_EXPORT(rt_hw_ui2c_init);
+
+#endif //#if defined(BSP_USING_UI2C)
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_usbd.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_usbd.c
new file mode 100644
index 0000000000..ce601c4253
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_usbd.c
@@ -0,0 +1,573 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-09-17      CHChen           First version
+*
+******************************************************************************/
+
+#include 
+
+#ifdef BSP_USING_USBD
+#include 
+#include 
+#include 
+#include "NuMicro.h"
+
+#define LOG_TAG         "drv.usbd"
+#define DBG_ENABLE
+#define DBG_SECTION_NAME "drv.usbd"
+#define DBG_LEVEL DBG_ERROR
+#define DBG_COLOR
+#include 
+
+/* Private define ---------------------------------------------------------------*/
+/* Define EP maximum packet size */
+#define EP0_MAX_PKT_SIZE    64
+#define EP1_MAX_PKT_SIZE    EP0_MAX_PKT_SIZE /* EP0 and EP1 are assigned the same size for control endpoint */
+#define EP2_MAX_PKT_SIZE    64
+#define EP3_MAX_PKT_SIZE    64
+#define EP4_MAX_PKT_SIZE    64
+#define EP5_MAX_PKT_SIZE    64
+#define EP6_MAX_PKT_SIZE    64
+#define EP7_MAX_PKT_SIZE    64
+#define EP8_MAX_PKT_SIZE    64
+#define EP9_MAX_PKT_SIZE    64
+#define EP10_MAX_PKT_SIZE   64
+#define EP11_MAX_PKT_SIZE   64
+
+#define SETUP_BUF_BASE  0
+#define SETUP_BUF_LEN   8
+#define EP0_BUF_BASE    (SETUP_BUF_BASE + SETUP_BUF_LEN)
+#define EP0_BUF_LEN     EP0_MAX_PKT_SIZE
+
+#define EP1_BUF_BASE    (SETUP_BUF_BASE + SETUP_BUF_LEN)
+#define EP1_BUF_LEN     EP1_MAX_PKT_SIZE
+#define EP2_BUF_BASE    (EP1_BUF_BASE + EP1_BUF_LEN)
+#define EP2_BUF_LEN     EP2_MAX_PKT_SIZE
+#define EP3_BUF_BASE    (EP2_BUF_BASE + EP2_BUF_LEN)
+#define EP3_BUF_LEN     EP3_MAX_PKT_SIZE
+#define EP4_BUF_BASE    (EP3_BUF_BASE + EP3_BUF_LEN)
+#define EP4_BUF_LEN     EP4_MAX_PKT_SIZE
+#define EP5_BUF_BASE    (EP4_BUF_BASE + EP4_BUF_LEN)
+#define EP5_BUF_LEN     EP5_MAX_PKT_SIZE
+#define EP6_BUF_BASE    (EP5_BUF_BASE + EP5_BUF_LEN)
+#define EP6_BUF_LEN     EP6_MAX_PKT_SIZE
+#define EP7_BUF_BASE    (EP6_BUF_BASE + EP6_BUF_LEN)
+#define EP7_BUF_LEN     EP7_MAX_PKT_SIZE
+#define EP8_BUF_BASE    (EP7_BUF_BASE + EP7_BUF_LEN)
+#define EP8_BUF_LEN     EP8_MAX_PKT_SIZE
+#define EP9_BUF_BASE    (EP8_BUF_BASE + EP8_BUF_LEN)
+#define EP9_BUF_LEN     EP9_MAX_PKT_SIZE
+#define EP10_BUF_BASE   (EP9_BUF_BASE + EP9_BUF_LEN)
+#define EP10_BUF_LEN    EP10_MAX_PKT_SIZE
+#define EP11_BUF_BASE   (EP10_BUF_BASE + EP10_BUF_LEN)
+#define EP11_BUF_LEN    EP11_MAX_PKT_SIZE
+
+#define EPADR_SW2HW(address) ((((address & USB_EPNO_MASK) * 2) +  (!(address & USB_DIR_IN))))
+#define EPADR_HW2SW(address) ((address & USB_EPNO_MASK) / 2)
+/* Private typedef --------------------------------------------------------------*/
+typedef struct _nu_usbd_t
+{
+    USBD_T *Instance;       /* REG base */
+    uint8_t address_tmp;    /* Keep assigned address for flow control */
+} nu_usbd_t;
+
+
+/* Private variables ------------------------------------------------------------*/
+static nu_usbd_t nu_usbd =
+{
+    .Instance       = USBD,
+    .address_tmp    = 0,
+};
+
+static struct udcd _rt_obj_udc;
+
+static struct ep_id _ep_pool[] =
+{
+    {EPADR_HW2SW(EP0),  USB_EP_ATTR_CONTROL,     USB_DIR_INOUT,  EP0_MAX_PKT_SIZE, ID_ASSIGNED  },
+    {EPADR_HW2SW(EP2),  USB_EP_ATTR_BULK,        USB_DIR_IN,     EP2_MAX_PKT_SIZE, ID_UNASSIGNED},
+    {EPADR_HW2SW(EP3),  USB_EP_ATTR_BULK,        USB_DIR_OUT,    EP3_MAX_PKT_SIZE, ID_UNASSIGNED},
+    {EPADR_HW2SW(EP4),  USB_EP_ATTR_INT,         USB_DIR_IN,     EP4_MAX_PKT_SIZE, ID_UNASSIGNED},
+    {EPADR_HW2SW(EP5),  USB_EP_ATTR_INT,         USB_DIR_OUT,    EP5_MAX_PKT_SIZE, ID_UNASSIGNED},
+    {EPADR_HW2SW(EP6),  USB_EP_ATTR_BULK,        USB_DIR_IN,     EP6_MAX_PKT_SIZE, ID_UNASSIGNED},
+    {EPADR_HW2SW(EP7),  USB_EP_ATTR_BULK,        USB_DIR_OUT,    EP7_MAX_PKT_SIZE, ID_UNASSIGNED},
+    {EPADR_HW2SW(EP8),  USB_EP_ATTR_INT,         USB_DIR_IN,     EP8_MAX_PKT_SIZE, ID_UNASSIGNED},
+    {EPADR_HW2SW(EP9),  USB_EP_ATTR_INT,         USB_DIR_OUT,    EP9_MAX_PKT_SIZE, ID_UNASSIGNED},
+    {EPADR_HW2SW(EP10), USB_EP_ATTR_BULK,        USB_DIR_IN,     EP6_MAX_PKT_SIZE, ID_UNASSIGNED},
+    {EPADR_HW2SW(EP11), USB_EP_ATTR_BULK,        USB_DIR_OUT,    EP7_MAX_PKT_SIZE, ID_UNASSIGNED},
+    {0xFF,              USB_EP_ATTR_TYPE_MASK,   USB_DIR_MASK,   0,                ID_ASSIGNED  },
+};
+
+static void _nu_ep_partition(void)
+{
+    /* Init setup packet buffer */
+    /* Buffer range for setup packet -> [0 ~ 0x7] */
+    USBD->STBUFSEG = SETUP_BUF_BASE;
+
+    /*****************************************************/
+    /* EP0 ==> control IN endpoint, address 0 */
+    USBD_CONFIG_EP(EP0, USBD_CFG_CSTALL | USBD_CFG_EPMODE_IN | EPADR_HW2SW(EP0));
+    /* Buffer range for EP0 */
+    USBD_SET_EP_BUF_ADDR(EP0, EP0_BUF_BASE);
+
+    /* EP1 ==> control OUT endpoint, address 0 */
+    USBD_CONFIG_EP(EP1, USBD_CFG_CSTALL | USBD_CFG_EPMODE_OUT | EPADR_HW2SW(EP1));
+    /* Buffer range for EP1 */
+    USBD_SET_EP_BUF_ADDR(EP1, EP1_BUF_BASE);
+
+    /*****************************************************/
+    /* EP2 ==> Bulk IN endpoint, address 1 */
+    USBD_CONFIG_EP(EP2, USBD_CFG_EPMODE_IN | EPADR_HW2SW(EP2));
+    /* Buffer range for EP2 */
+    USBD_SET_EP_BUF_ADDR(EP2, EP2_BUF_BASE);
+
+    /* EP3 ==> Bulk OUT endpoint, address 1 */
+    USBD_CONFIG_EP(EP3, USBD_CFG_EPMODE_OUT | EPADR_HW2SW(EP3));
+    /* Buffer range for EP3 */
+    USBD_SET_EP_BUF_ADDR(EP3, EP3_BUF_BASE);
+
+    /*****************************************************/
+    /* EP4 ==> Interrupt IN endpoint, address 2 */
+    USBD_CONFIG_EP(EP4, USBD_CFG_EPMODE_IN | EPADR_HW2SW(EP4));
+    /* Buffer range for EP4 */
+    USBD_SET_EP_BUF_ADDR(EP4, EP4_BUF_BASE);
+
+    /* EP5 ==> Interrupt Out endpoint, address 2 */
+    USBD_CONFIG_EP(EP5, USBD_CFG_EPMODE_OUT | EPADR_HW2SW(EP5));
+    /* Buffer range for EP5 */
+    USBD_SET_EP_BUF_ADDR(EP5, EP5_BUF_BASE);
+
+    /*****************************************************/
+    /* EP6 ==> Bulk IN endpoint, address 3 */
+    USBD_CONFIG_EP(EP6, USBD_CFG_EPMODE_IN | EPADR_HW2SW(EP6));
+    /* Buffer range for EP4 */
+    USBD_SET_EP_BUF_ADDR(EP6, EP6_BUF_BASE);
+
+    /* EP7 ==> Bulk Out endpoint, address 3 */
+    USBD_CONFIG_EP(EP7, USBD_CFG_EPMODE_OUT | EPADR_HW2SW(EP7));
+    /* Buffer range for EP5 */
+    USBD_SET_EP_BUF_ADDR(EP7, EP7_BUF_BASE);
+
+    /*****************************************************/
+    /* EP8 ==> Interrupt IN endpoint, address 4 */
+    USBD_CONFIG_EP(EP8, USBD_CFG_EPMODE_IN | EPADR_HW2SW(EP8));
+    /* Buffer range for EP4 */
+    USBD_SET_EP_BUF_ADDR(EP8, EP8_BUF_BASE);
+
+    /* EP9 ==> Interrupt Out endpoint, address 4 */
+    USBD_CONFIG_EP(EP9, USBD_CFG_EPMODE_OUT | EPADR_HW2SW(EP9));
+    /* Buffer range for EP9 */
+    USBD_SET_EP_BUF_ADDR(EP9, EP9_BUF_BASE);
+
+    /*****************************************************/
+    /* EP10 ==> Bulk IN endpoint, address 5 */
+    USBD_CONFIG_EP(EP10, USBD_CFG_EPMODE_IN | EPADR_HW2SW(EP10));
+    /* Buffer range for EP10 */
+    USBD_SET_EP_BUF_ADDR(EP10, EP10_BUF_BASE);
+
+    /* EP11 ==> Bulk Out endpoint, address 5 */
+    USBD_CONFIG_EP(EP11, USBD_CFG_EPMODE_OUT | EPADR_HW2SW(EP11));
+    /* Buffer range for EP11 */
+    USBD_SET_EP_BUF_ADDR(EP11, EP11_BUF_BASE);
+
+}
+
+static rt_err_t _ep_set_stall(rt_uint8_t address)
+{
+    USBD_SET_EP_STALL(EPADR_SW2HW(address));
+    return RT_EOK;
+}
+
+static rt_err_t _ep_clear_stall(rt_uint8_t address)
+{
+    USBD_ClearStall(EPADR_SW2HW(address));
+
+    return RT_EOK;
+}
+
+
+static rt_err_t _set_address(rt_uint8_t address)
+{
+    if (0 != address)
+    {
+        nu_usbd.address_tmp = address;
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t _set_config(rt_uint8_t address)
+{
+    return RT_EOK;
+}
+
+static rt_err_t _ep_enable(uep_t ep)
+{
+    RT_ASSERT(ep != RT_NULL);
+    RT_ASSERT(ep->ep_desc != RT_NULL);
+
+    USBD_CONFIG_EP(EPADR_SW2HW(EP_ADDRESS(ep)),
+                   USBD_CFG_CSTALL
+                   | ((EP_ADDRESS(ep) & USB_DIR_IN) ? USBD_CFG_EPMODE_IN : USBD_CFG_EPMODE_OUT)
+                   | (EP_ADDRESS(ep) & USB_EPNO_MASK));
+
+    return RT_EOK;
+}
+
+static rt_err_t _ep_disable(uep_t ep)
+{
+    RT_ASSERT(ep != RT_NULL);
+    RT_ASSERT(ep->ep_desc != RT_NULL);
+
+    USBD_CONFIG_EP(EPADR_SW2HW(EP_ADDRESS(ep)),  USBD_CFG_EPMODE_DISABLE);
+
+    return RT_EOK;
+}
+
+static rt_size_t _ep_read(rt_uint8_t address, void *buffer)
+{
+    rt_size_t size = 0;
+    rt_uint8_t *buf;
+    rt_uint32_t hw_ep_num = EPADR_SW2HW(address);
+
+    RT_ASSERT(!(address & USB_DIR_IN));
+    RT_ASSERT(buffer != RT_NULL);
+
+    size = USBD_GET_PAYLOAD_LEN(hw_ep_num);
+    buf = (uint8_t *)(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(hw_ep_num));
+    USBD_MemCopy(buffer, (uint8_t *)buf, size);
+
+    return size;
+}
+
+static rt_size_t _ep_read_prepare(rt_uint8_t address, void *buffer, rt_size_t size)
+{
+    RT_ASSERT(!(address & USB_DIR_IN));
+
+    USBD_SET_PAYLOAD_LEN(EPADR_SW2HW(address), size);
+
+    return size;
+}
+
+static rt_size_t _ep_write(rt_uint8_t address, void *buffer, rt_size_t size)
+{
+    RT_ASSERT((address & USB_DIR_IN));
+
+    /* even number is for IN endpoint */
+    rt_uint32_t hw_ep_num = EPADR_SW2HW(address);
+    uint8_t *buf;
+    buf = (uint8_t *)(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(hw_ep_num));
+
+    USBD_MemCopy(buf, (uint8_t *)buffer, size);
+
+    USBD_SET_PAYLOAD_LEN(hw_ep_num, size);
+
+    return size;
+}
+
+static rt_err_t _ep0_send_status(void)
+{
+    /* Status stage */
+    USBD_SET_DATA1(EP0);
+    USBD_SET_PAYLOAD_LEN(EP0, 0);
+    return RT_EOK;
+}
+
+static rt_err_t _suspend(void)
+{
+    return RT_EOK;
+}
+
+static rt_err_t _wakeup(void)
+{
+    return RT_EOK;
+}
+
+__STATIC_INLINE void _USBD_IRQHandler(void)
+{
+    rt_uint32_t u32IntSts   = USBD_GET_INT_FLAG();
+    rt_uint32_t u32State    = USBD_GET_BUS_STATE();
+
+//------------------------------------------------------------------
+    if (u32IntSts & USBD_INTSTS_VBDETIF_Msk)
+    {
+        // Floating detect
+        USBD_CLR_INT_FLAG(USBD_INTSTS_VBDETIF_Msk);
+
+        if (USBD_IS_ATTACHED())
+        {
+            /* USB Plug In */
+            USBD_ENABLE_USB();
+            rt_usbd_connect_handler(&_rt_obj_udc);
+        }
+        else
+        {
+            /* USB Unplug */
+            USBD_DISABLE_USB();
+            rt_usbd_disconnect_handler(&_rt_obj_udc);
+        }
+    }
+
+    if (u32IntSts & USBD_INTSTS_SOFIF_Msk)
+    {
+        USBD_CLR_INT_FLAG(USBD_INTSTS_SOFIF_Msk);
+        rt_usbd_sof_handler(&_rt_obj_udc);
+    }
+//------------------------------------------------------------------
+    if (u32IntSts & USBD_INTSTS_BUSIF_Msk)
+    {
+        /* Clear event flag */
+        USBD_CLR_INT_FLAG(USBD_INTSTS_BUSIF_Msk);
+
+        if (u32State & USBD_ATTR_USBRST_Msk)
+        {
+            USBD_ENABLE_USB();
+
+            /* Reset PID DATA0 */
+            for (rt_uint32_t i = 0ul; i < USBD_MAX_EP; i++)
+            {
+                nu_usbd.Instance->EP[i].CFG &= ~USBD_CFG_DSQSYNC_Msk;
+            }
+
+            /* Reset USB device address */
+            USBD_SET_ADDR(0ul);
+
+            /* Bus reset */
+            rt_usbd_reset_handler(&_rt_obj_udc);
+        }
+        if (u32State & USBD_ATTR_SUSPEND_Msk)
+        {
+            /* Enable USB but disable PHY */
+            USBD_DISABLE_PHY();
+        }
+        if (u32State & USBD_ATTR_RESUME_Msk)
+        {
+            /* Enable USB and enable PHY */
+            USBD_ENABLE_USB();
+        }
+    }
+
+//------------------------------------------------------------------
+    if (u32IntSts & USBD_INTSTS_WAKEUP)
+    {
+        /* Clear event flag */
+        USBD_CLR_INT_FLAG(USBD_INTSTS_WAKEUP);
+        USBD_ENABLE_USB();
+    }
+
+    if (u32IntSts & USBD_INTSTS_USBIF_Msk)
+    {
+        // USB event
+        if (u32IntSts & USBD_INTSTS_SETUP_Msk)
+        {
+            // Setup packet
+            /* Clear event flag */
+            USBD_CLR_INT_FLAG(USBD_INTSTS_SETUP_Msk);
+
+            /* Clear the data IN/OUT ready flag of control end-points */
+            USBD_STOP_TRANSACTION(EP0);
+            USBD_STOP_TRANSACTION(EP1);
+
+            USBD_SET_DATA1(EP0);
+            rt_usbd_ep0_setup_handler(&_rt_obj_udc, (struct urequest *)USBD_BUF_BASE);
+        }
+
+        // EP events
+        if (u32IntSts & USBD_INTSTS_EP0)
+        {
+            /* Clear event flag */
+            USBD_CLR_INT_FLAG(USBD_INTSTS_EP0);
+
+            if ((USBD_GET_ADDR() == 0)
+                    && (nu_usbd.address_tmp)
+               )
+            {
+                USBD_SET_ADDR(nu_usbd.address_tmp);
+                LOG_I("SET ADDR: 0x%02x", nu_usbd.address_tmp);
+                nu_usbd.address_tmp = 0;
+            }
+
+            rt_usbd_ep0_in_handler(&_rt_obj_udc);
+        }
+
+        if (u32IntSts & USBD_INTSTS_EP1)
+        {
+            /* Clear event flag */
+            USBD_CLR_INT_FLAG(USBD_INTSTS_EP1);
+            rt_usbd_ep0_out_handler(&_rt_obj_udc, 0);
+        }
+
+        if (u32IntSts & USBD_INTSTS_EP2)
+        {
+            /* Clear event flag */
+            USBD_CLR_INT_FLAG(USBD_INTSTS_EP2);
+            rt_usbd_ep_in_handler(&_rt_obj_udc, USB_DIR_IN | EPADR_HW2SW(EP2), 0);
+        }
+
+        if (u32IntSts & USBD_INTSTS_EP3)
+        {
+            /* Clear event flag */
+            USBD_CLR_INT_FLAG(USBD_INTSTS_EP3);
+            rt_usbd_ep_out_handler(&_rt_obj_udc, USB_DIR_OUT | EPADR_HW2SW(EP3), 0);
+        }
+
+        if (u32IntSts & USBD_INTSTS_EP4)
+        {
+            /* Clear event flag */
+            USBD_CLR_INT_FLAG(USBD_INTSTS_EP4);
+            rt_usbd_ep_in_handler(&_rt_obj_udc, USB_DIR_IN | EPADR_HW2SW(EP4), 0);
+        }
+
+        if (u32IntSts & USBD_INTSTS_EP5)
+        {
+            /* Clear event flag */
+            USBD_CLR_INT_FLAG(USBD_INTSTS_EP5);
+            rt_usbd_ep_out_handler(&_rt_obj_udc, USB_DIR_OUT | EPADR_HW2SW(EP5), 0);
+        }
+
+        if (u32IntSts & USBD_INTSTS_EP6)
+        {
+            /* Clear event flag */
+            USBD_CLR_INT_FLAG(USBD_INTSTS_EP6);
+            rt_usbd_ep_in_handler(&_rt_obj_udc, USB_DIR_IN | EPADR_HW2SW(EP6), 0);
+        }
+
+        if (u32IntSts & USBD_INTSTS_EP7)
+        {
+            /* Clear event flag */
+            USBD_CLR_INT_FLAG(USBD_INTSTS_EP7);
+            rt_usbd_ep_out_handler(&_rt_obj_udc, USB_DIR_OUT | EPADR_HW2SW(EP7), 0);
+        }
+
+        if (u32IntSts & USBD_INTSTS_EP8)
+        {
+            /* Clear event flag */
+            USBD_CLR_INT_FLAG(USBD_INTSTS_EP8);
+            rt_usbd_ep_in_handler(&_rt_obj_udc, USB_DIR_IN | EPADR_HW2SW(EP8), 0);
+        }
+
+        if (u32IntSts & USBD_INTSTS_EP9)
+        {
+            /* Clear event flag */
+            USBD_CLR_INT_FLAG(USBD_INTSTS_EP9);
+            rt_usbd_ep_out_handler(&_rt_obj_udc, USB_DIR_OUT | EPADR_HW2SW(EP9), 0);
+        }
+
+        if (u32IntSts & USBD_INTSTS_EP10)
+        {
+            /* Clear event flag */
+            USBD_CLR_INT_FLAG(USBD_INTSTS_EP10);
+            rt_usbd_ep_in_handler(&_rt_obj_udc, USB_DIR_IN | EPADR_HW2SW(EP10), 0);
+        }
+
+        if (u32IntSts & USBD_INTSTS_EP11)
+        {
+            /* Clear event flag */
+            USBD_CLR_INT_FLAG(USBD_INTSTS_EP11);
+            rt_usbd_ep_out_handler(&_rt_obj_udc, USB_DIR_OUT | EPADR_HW2SW(EP11), 0);
+        }
+
+    }
+}
+
+void USBD_IRQHandler(void)
+{
+    rt_interrupt_enter();
+
+    _USBD_IRQHandler();
+
+    rt_interrupt_leave();
+}
+
+static rt_err_t _init(rt_device_t device)
+{
+    nu_usbd_t *nu_usbd = (nu_usbd_t *)device->user_data;
+
+#if !defined(BSP_USING_OTG)
+
+    /* Initialize USB PHY */
+    SYS_UnlockReg();
+    /* Select USBD */
+    SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_USBROLE_Msk) | SYS_USBPHY_OTGPHYEN_Msk | SYS_USBPHY_SBO_Msk;
+    SYS_ResetModule(USBD_RST);
+    SYS_LockReg();
+#endif
+
+    _nu_ep_partition();
+
+    /* Initial USB engine */
+    nu_usbd->Instance->ATTR = 0x6D0ul;
+
+    /* Force SE0 */
+    USBD_SET_SE0();
+
+    NVIC_EnableIRQ(USBD_IRQn);
+
+    USBD_Start();
+    return RT_EOK;
+}
+
+const static struct udcd_ops _udc_ops =
+{
+    _set_address,
+    _set_config,
+    _ep_set_stall,
+    _ep_clear_stall,
+    _ep_enable,
+    _ep_disable,
+    _ep_read_prepare,
+    _ep_read,
+    _ep_write,
+    _ep0_send_status,
+    _suspend,
+    _wakeup,
+};
+
+#ifdef RT_USING_DEVICE_OPS
+const static struct rt_device_ops _ops =
+{
+    _init,
+    RT_NULL,
+    RT_NULL,
+    RT_NULL,
+    RT_NULL,
+    RT_NULL,
+};
+#endif
+
+int nu_usbd_register(void)
+{
+    if (RT_NULL != rt_device_find("usbd"))
+    {
+        LOG_E("\nUSBD Register failed. Another USBD device registered\n");
+        return -RT_ERROR;
+    }
+
+    rt_memset((void *)&_rt_obj_udc, 0, sizeof(struct udcd));
+    _rt_obj_udc.parent.type = RT_Device_Class_USBDevice;
+
+#ifdef RT_USING_DEVICE_OPS
+    _rt_obj_udc.parent.ops = &_ops;
+#else
+    _rt_obj_udc.parent.init = _init;
+#endif
+
+    _rt_obj_udc.parent.user_data = &nu_usbd;
+    _rt_obj_udc.ops = &_udc_ops;
+    /* Register endpoint information */
+    _rt_obj_udc.ep_pool = _ep_pool;
+    _rt_obj_udc.ep0.id = &_ep_pool[0];
+
+    _rt_obj_udc.device_is_hs = RT_FALSE; /* Support Full-Speed only */
+
+    rt_device_register((rt_device_t)&_rt_obj_udc, "usbd", 0);
+    rt_usb_device_init();
+    return RT_EOK;
+}
+INIT_DEVICE_EXPORT(nu_usbd_register);
+#endif
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_usbhost.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_usbhost.c
new file mode 100644
index 0000000000..b853ffa1c6
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_usbhost.c
@@ -0,0 +1,842 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-5-4        CHChen           First version
+*
+******************************************************************************/
+#include 
+
+#if defined(BSP_USING_USBH)
+
+#include 
+#include 
+#include "NuMicro.h"
+
+#include "usb.h"
+#include "usbh_lib.h"
+
+#if !defined(NU_USBHOST_HUB_POLLING_INTERVAL)
+    #define NU_USBHOST_HUB_POLLING_INTERVAL    (100)
+#endif
+
+#define NU_MAX_USBH_PORT    1        //USB1.1 port
+#define NU_MAX_USBH_PIPE    16
+#define NU_USBH_THREAD_STACK_SIZE    2048
+
+#define NU_MAX_USBH_HUB_PORT_DEV    USB_HUB_PORT_NUM
+
+/* Private typedef --------------------------------------------------------------*/
+typedef struct nu_port_dev
+{
+    rt_bool_t bRHParent;
+    UDEV_T *pUDev;
+    EP_INFO_T *apsEPInfo[NU_MAX_USBH_PIPE];
+    struct urequest asSetupReq[NU_MAX_USBH_PIPE];
+    struct rt_completion utr_completion;
+    int port_num;
+    rt_bool_t bEnumDone;
+} S_NU_PORT_DEV;
+
+
+typedef struct nu_port_ctrl
+{
+    S_NU_PORT_DEV sRHPortDev;
+    S_NU_PORT_DEV asHubPortDev[NU_MAX_USBH_HUB_PORT_DEV];
+} S_NU_RH_PORT_CTRL;
+
+
+struct nu_usbh_dev
+{
+    uhcd_t uhcd;
+    rt_thread_t polling_thread;
+    S_NU_RH_PORT_CTRL asPortCtrl[NU_MAX_USBH_PORT];
+};
+
+/* Private variables ------------------------------------------------------------*/
+static struct nu_usbh_dev s_sUSBHDev =
+{
+    .uhcd = RT_NULL,
+};
+
+static S_NU_RH_PORT_CTRL *
+GetRHPortControlFromPipe(
+    upipe_t pipe
+)
+{
+    uinst_t inst;
+    int port;
+    if (pipe->inst->parent_hub->is_roothub)
+    {
+        //case: device ---> root hub
+        inst = pipe->inst;
+        port = inst->port;
+    }
+    else
+    {
+        //case: device ---> hub ---> root hub
+        inst = pipe->inst->parent_hub->self;
+        port = inst->port;
+    }
+
+    if (port > NU_MAX_USBH_PORT)
+    {
+        RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_open_pipe ERROR: port index over NU_MAX_USBH_PORT\n"));
+        return RT_NULL;
+    }
+
+    return &s_sUSBHDev.asPortCtrl[port - 1];;
+}
+
+static S_NU_PORT_DEV *
+GetPortDevFromPipe(
+    upipe_t pipe
+)
+{
+    S_NU_RH_PORT_CTRL *psRHPortCtrl = GetRHPortControlFromPipe(pipe);
+    int i;
+
+    if (psRHPortCtrl == RT_NULL)
+        return RT_NULL;
+
+    if (pipe->inst->parent_hub->is_roothub)
+    {
+        //case: device ---> root hub
+        return &psRHPortCtrl->sRHPortDev;
+    }
+
+    //case: device ---> hub ---> root hub
+    for (i = 0 ; i < NU_MAX_USBH_HUB_PORT_DEV; i ++)
+    {
+        if (psRHPortCtrl->asHubPortDev[i].port_num == pipe->inst->port)
+            break;
+    }
+
+    if (i >= NU_MAX_USBH_HUB_PORT_DEV)
+        return RT_NULL;
+    return &psRHPortCtrl->asHubPortDev[i];
+}
+
+static  S_NU_PORT_DEV *
+AllocateNewUDev(
+    S_NU_RH_PORT_CTRL *psRHPortCtrl
+)
+{
+    int i;
+    for (i = 0 ; i < NU_MAX_USBH_HUB_PORT_DEV; i ++)
+    {
+        if (psRHPortCtrl->asHubPortDev[i].pUDev == NULL)
+            break;
+    }
+
+    if (i >= NU_MAX_USBH_HUB_PORT_DEV)
+        return RT_NULL;
+
+    psRHPortCtrl->asHubPortDev[i].pUDev = alloc_device();
+
+    if (psRHPortCtrl->asHubPortDev[i].pUDev == NULL)
+        return RT_NULL;
+
+    return &psRHPortCtrl->asHubPortDev[i];
+}
+
+static EP_INFO_T *GetFreePipe(
+    S_NU_RH_PORT_CTRL *psPortCtrl,
+    S_NU_PORT_DEV *psPortDev,
+    rt_uint8_t *pu8PipeIndex
+)
+{
+    rt_uint8_t i;
+    if (psPortCtrl == NULL)
+        return NULL;
+
+    for (i = 1; i < NU_MAX_USBH_PIPE; i ++)
+    {
+        if (psPortDev->apsEPInfo[i] == NULL)
+            break;
+    }
+
+    if (i >= NU_MAX_USBH_PIPE)
+        return RT_NULL;
+
+    EP_INFO_T *psEPInfo = rt_malloc(sizeof(EP_INFO_T));
+
+    psPortDev->apsEPInfo[i] = psEPInfo;
+    *pu8PipeIndex = i;
+    return psEPInfo;
+}
+
+static void FreePipe(
+    S_NU_RH_PORT_CTRL *psPortCtrl,
+    S_NU_PORT_DEV *psPortDev,
+    rt_uint8_t u8PipeIndex
+)
+{
+    if (psPortCtrl == NULL)
+        return;
+
+    if (u8PipeIndex >= NU_MAX_USBH_PIPE)
+        return;
+
+    if (psPortDev->apsEPInfo[u8PipeIndex])
+    {
+        rt_free(psPortDev->apsEPInfo[u8PipeIndex]);
+        psPortDev->apsEPInfo[u8PipeIndex] = RT_NULL;
+    }
+}
+
+static rt_err_t nu_reset_port(rt_uint8_t port)
+{
+    S_NU_RH_PORT_CTRL *psPortCtrl;
+
+    RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_reset_port\n"));
+    if (port > NU_MAX_USBH_PORT)
+    {
+        RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_reset_port ERROR: port index over NU_MAX_USBH_PORT\n"));
+        return RT_EIO;
+    }
+
+    psPortCtrl = &s_sUSBHDev.asPortCtrl[port - 1];
+    if (psPortCtrl->sRHPortDev.pUDev == NULL)
+    {
+        RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_reset_port ERROR: udev not found\n"));
+        return RT_EIO;
+    }
+
+    usbh_reset_port(psPortCtrl->sRHPortDev.pUDev);
+
+    return RT_EOK;
+}
+
+static int nu_ctrl_xfer(
+    S_NU_PORT_DEV *psPortDev,
+    struct urequest *psSetup,
+    void *buffer,
+    int timeouts
+)
+{
+    uint32_t  xfer_len;
+    int    ret;
+
+    ret = usbh_ctrl_xfer(psPortDev->pUDev, psSetup->request_type, psSetup->bRequest, psSetup->wValue, psSetup->wIndex, psSetup->wLength, buffer, &xfer_len, timeouts * 10);
+
+    if (ret < 0)
+    {
+        RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_ctrl_xfer ERROR: xfer failed %d\n", ret));
+        return ret;
+    }
+
+    if (xfer_len != psSetup->wLength)
+    {
+        RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_ctrl_xfer ERROR: xfer length %d %d\n", psSetup->wLength, xfer_len));
+    }
+
+    if ((psSetup->bRequest == USB_REQ_SET_ADDRESS) && ((psSetup->request_type & 0x60) == REQ_TYPE_STD_DEV))
+        psPortDev->pUDev->dev_num = psSetup->wValue;
+
+    if ((psSetup->bRequest == USB_REQ_SET_CONFIGURATION) && ((psSetup->request_type & 0x60) == REQ_TYPE_STD_DEV))
+    {
+        psPortDev->pUDev->cur_conf = psSetup->wValue;
+        psPortDev->bEnumDone = TRUE;
+    }
+
+    return xfer_len;
+}
+
+static int nu_bulk_xfer(
+    S_NU_PORT_DEV *psPortDev,
+    UTR_T *psUTR,
+    int timeouts
+)
+{
+    int ret;
+
+    ret = usbh_bulk_xfer(psUTR);
+
+    if (ret < 0)
+        return ret;
+
+    //wait transfer done
+    rt_completion_wait(&(psPortDev->utr_completion), timeouts);
+    return 0;
+}
+
+static int nu_int_xfer(
+    upipe_t pipe,
+    S_NU_PORT_DEV *psPortDev,
+    UTR_T *psUTR,
+    int timeouts
+)
+{
+    int ret;
+    int retry = 3;
+
+    while (retry > 0)
+    {
+        ret = usbh_int_xfer(psUTR);
+        if (ret == 0)
+            break;
+
+        RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_int_xfer ERROR: failed to submit interrupt request\n"));
+        rt_thread_delay((pipe->ep.bInterval * RT_TICK_PER_SECOND / 1000) > 0 ? (pipe->ep.bInterval * RT_TICK_PER_SECOND / 1000) : 1);
+        retry --;
+    }
+
+    if (ret < 0)
+        return ret;
+
+    return 0;
+}
+
+static void xfer_done_cb(UTR_T *psUTR)
+{
+    S_NU_PORT_DEV *psPortDev = (S_NU_PORT_DEV *)psUTR->context;
+
+    //transfer done, signal utr_completion
+    rt_completion_done(&(psPortDev->utr_completion));
+}
+
+static void int_xfer_done_cb(UTR_T *psUTR)
+{
+    upipe_t pipe = (upipe_t)psUTR->context;
+
+    if (psUTR->status != 0)
+    {
+        rt_kprintf("Interrupt xfer failed %d\n", psUTR->status);
+        free_utr(psUTR);
+        return;
+    }
+
+    if (pipe->callback != RT_NULL)
+    {
+        struct uhost_msg msg;
+        msg.type = USB_MSG_CALLBACK;
+        msg.content.cb.function = pipe->callback;
+        msg.content.cb.context = pipe;
+        rt_usbh_event_signal(&msg);
+    }
+
+    free_utr(psUTR);
+}
+
+static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes, int timeouts)
+{
+    S_NU_RH_PORT_CTRL *psPortCtrl;
+    S_NU_PORT_DEV *psPortDev;
+
+    psPortCtrl = GetRHPortControlFromPipe(pipe);
+    if (psPortCtrl == RT_NULL)
+    {
+        return RT_EIO;
+    }
+
+    psPortDev = GetPortDevFromPipe(pipe);
+
+    if (psPortDev->pUDev == NULL)
+    {
+        RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_pipe_xfer ERROR: udev not found\n"));
+        return -RT_ERROR;
+    }
+
+    //ctrl xfer
+    if (pipe->ep.bmAttributes == USB_EP_ATTR_CONTROL)
+    {
+        if (token == USBH_PID_SETUP)
+        {
+            struct urequest *psSetup;
+            psSetup = (struct urequest *)buffer;
+
+            if (psSetup->request_type & USB_REQ_TYPE_DIR_IN)
+            {
+                //Store setup request
+                rt_memcpy(&psPortCtrl->asHubPortDev->asSetupReq[pipe->pipe_index], psSetup, sizeof(struct urequest));
+            }
+            else
+            {
+                //Trigger USBHostLib Ctril_Xfer
+                nu_ctrl_xfer(psPortDev, psSetup, NULL, timeouts);
+            }
+            return nbytes;
+        }
+        else
+        {
+            //token == USBH_PID_DATA
+            if (buffer == RT_NULL)
+                return nbytes;
+
+            if ((pipe->ep.bEndpointAddress & USB_DIR_MASK) == USB_DIR_IN)
+            {
+                //Trigger USBHostLib Ctril_Xfer
+                nu_ctrl_xfer(psPortDev, &psPortCtrl->asHubPortDev->asSetupReq[pipe->pipe_index], buffer, timeouts);
+            }
+            else
+            {
+                RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_pipe_xfer ERROR: can not handle ctrl xfer case: buffer!=NULL and USB_DIR_OUT\n"));
+            }
+            return nbytes;
+        }
+    }
+
+    //others xfer
+    rt_completion_init(&(psPortDev->utr_completion));
+
+    //setup UTR
+    UTR_T *psUTR;
+    int i32XferLen;
+
+    psUTR = alloc_utr(psPortDev->pUDev);
+    if (!psUTR)
+    {
+        RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_pipe_xfer ERROR: unable alloc UTR\n"));
+        return -(RT_ERROR);
+    }
+
+    psUTR->ep = psPortDev->apsEPInfo[pipe->pipe_index];
+    psUTR->buff = buffer;
+    psUTR->data_len = nbytes;
+    psUTR->xfer_len = 0;
+    psUTR->func = xfer_done_cb;
+    psUTR->context = psPortDev;
+    psUTR->bIsTransferDone = 0;
+    psUTR->status = 0;
+
+    if (pipe->ep.bmAttributes == USB_EP_ATTR_BULK)
+    {
+        if (nu_bulk_xfer(psPortDev, psUTR, timeouts) < 0)
+        {
+            free_utr(psUTR);
+            RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_pipe_xfer ERROR: bulk transfer failed\n"));
+            return -(RT_ERROR);
+        }
+    }
+
+    if (pipe->ep.bmAttributes == USB_EP_ATTR_INT)
+    {
+        psUTR->func = int_xfer_done_cb;
+        psUTR->context = pipe;
+
+        if (nu_int_xfer(pipe, psPortDev, psUTR, timeouts) < 0)
+        {
+            free_utr(psUTR);
+            RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_pipe_xfer ERROR: int transfer failed\n"));
+            return -(RT_ERROR);
+        }
+
+        return nbytes;
+    }
+
+    //TODO: ISO transfer
+    if (pipe->ep.bmAttributes == USB_EP_ATTR_ISOC)
+    {
+        free_utr(psUTR);
+        RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_pipe_xfer ERROR: isoc transfer not support\n"));
+        return -1;
+    }
+
+    if (psUTR->bIsTransferDone == 0)
+    {
+        //Timeout
+        RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_pipe_xfer ERROR: timeout\n"));
+        pipe->status = UPIPE_STATUS_ERROR;
+        usbh_quit_utr(psUTR);
+    }
+    else
+    {
+        // Transfer Done. Get status
+        if (psUTR->status == 0)
+        {
+            pipe->status = UPIPE_STATUS_OK;
+        }
+        else if (psUTR->status == USBH_ERR_STALL)
+        {
+            pipe->status = UPIPE_STATUS_STALL;
+        }
+        else
+        {
+            pipe->status = UPIPE_STATUS_ERROR;
+        }
+    }
+
+    i32XferLen = psUTR->xfer_len;
+    free_utr(psUTR);
+
+    //Call callback
+    if (pipe->callback != RT_NULL)
+    {
+        struct uhost_msg msg;
+        msg.type = USB_MSG_CALLBACK;
+        msg.content.cb.function = pipe->callback;
+        msg.content.cb.context = pipe->user_data;
+        rt_usbh_event_signal(&msg);
+    }
+
+    if (pipe->status != UPIPE_STATUS_OK)
+        return -(RT_ERROR);
+
+    if ((pipe->ep.bEndpointAddress & USB_DIR_MASK) == USB_DIR_IN)
+    {
+        return i32XferLen;
+    }
+    else if ((pipe->ep.bEndpointAddress & USB_DIR_MASK) == USB_DIR_OUT)
+    {
+        return i32XferLen;
+    }
+
+    return nbytes;
+}
+
+static rt_err_t nu_open_pipe(upipe_t pipe)
+{
+    S_NU_RH_PORT_CTRL *psPortCtrl;
+    S_NU_PORT_DEV *psPortDev;
+
+    psPortCtrl = GetRHPortControlFromPipe(pipe);
+    if (psPortCtrl == RT_NULL)
+    {
+        return RT_EIO;
+    }
+
+    if (psPortCtrl->sRHPortDev.pUDev == NULL)
+    {
+        RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_open_pipe ERROR: udev not found\n"));
+        return RT_EIO;
+    }
+
+    psPortDev = GetPortDevFromPipe(pipe);
+
+    if ((psPortDev == NULL) || (psPortDev->pUDev == NULL))
+    {
+        //allocate new dev for hub device
+        psPortDev = AllocateNewUDev(psPortCtrl);
+
+        if (psPortDev == RT_NULL)
+        {
+            RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_open_pipe ERROR: udev allocate failed\n"));
+            return RT_EIO;
+        }
+
+        if (pipe->inst->speed)
+        {
+            psPortDev->pUDev->speed = SPEED_FULL;
+        }
+        else
+        {
+            psPortDev->pUDev->speed = SPEED_HIGH;
+        }
+
+        psPortDev->pUDev->parent = NULL;
+        psPortDev->pUDev->hc_driver = psPortCtrl->sRHPortDev.pUDev->hc_driver;
+        psPortDev->port_num = pipe->inst->port;
+        psPortDev->pUDev->port_num = pipe->inst->port;
+        psPortDev->bEnumDone = FALSE;
+    }
+
+    //For ep0 control transfer
+    if ((pipe->ep.bEndpointAddress & 0x7F) == 0)
+    {
+        pipe->pipe_index = 0;
+        return RT_EOK;
+    }
+
+    EP_INFO_T *psEPInfo = GetFreePipe(psPortCtrl, psPortDev, &pipe->pipe_index);
+
+    if (psEPInfo == RT_NULL)
+    {
+        RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_open_pipe ERROR: get free pipe failed\n"));
+        return RT_ENOMEM;
+    }
+
+    int  pksz;
+
+    psEPInfo->bEndpointAddress = pipe->ep.bEndpointAddress;
+    psEPInfo->bmAttributes = pipe->ep.bmAttributes;
+
+    pksz = pipe->ep.wMaxPacketSize;
+    pksz = (pksz & 0x07ff) * (1 + ((pksz >> 11) & 3));
+    psEPInfo->wMaxPacketSize = pksz;
+
+    psEPInfo->bInterval = pipe->ep.bInterval;
+    psEPInfo->hw_pipe = NULL;
+    psEPInfo->bToggle = 0;
+
+    return RT_EOK;
+}
+
+static rt_err_t nu_close_pipe(upipe_t pipe)
+{
+    S_NU_RH_PORT_CTRL *psPortCtrl;
+    S_NU_PORT_DEV *psPortDev;
+
+    RT_DEBUG_LOG(RT_DEBUG_USB, ("nu_close_pipe\n"));
+    psPortCtrl = GetRHPortControlFromPipe(pipe);
+    if (psPortCtrl == RT_NULL)
+    {
+        return RT_EIO;
+    }
+
+
+    psPortDev = GetPortDevFromPipe(pipe);
+
+    //For ep0 control transfer
+    if ((pipe->ep.bEndpointAddress & 0x7F) == 0)
+    {
+        if ((psPortDev) && (psPortDev->bRHParent == FALSE) && (psPortDev->bEnumDone == TRUE))
+        {
+            if (psPortDev->pUDev)
+            {
+                int i;
+                for (i = 0; i < NU_MAX_USBH_PIPE; i++)
+                {
+                    if (psPortDev->apsEPInfo[i] != NULL)
+                    {
+                        usbh_quit_xfer(psPortDev->pUDev, psPortDev->apsEPInfo[i]);
+                    }
+                }
+
+                free_device(psPortDev->pUDev);
+                psPortDev->pUDev = NULL;
+            }
+        }
+    }
+
+    if (psPortDev != NULL)
+    {
+        FreePipe(psPortCtrl, psPortDev, pipe->pipe_index);
+    }
+
+    return RT_EOK;
+}
+
+//Pooling USB root hub status task
+static void nu_usbh_rh_thread_entry(void *parameter)
+{
+    while (1)
+    {
+        usbh_polling_root_hubs();
+        rt_thread_mdelay(NU_USBHOST_HUB_POLLING_INTERVAL);
+    }
+}
+
+static void nu_hcd_connect_callback(
+    struct udev_t *udev,
+    int param
+)
+{
+    int i;
+    int port_index;
+    S_NU_RH_PORT_CTRL *psPortCtrl;
+
+    for (i = 0; i < NU_MAX_USBH_PORT; i++)
+    {
+        psPortCtrl = &s_sUSBHDev.asPortCtrl[i];
+        if (psPortCtrl->sRHPortDev.pUDev == NULL)
+            break;
+    }
+
+    if (i >= NU_MAX_USBH_PORT)
+    {
+        RT_DEBUG_LOG(RT_DEBUG_USB, ("ERROR: port connect slot is full\n"));
+        return;
+    }
+
+    port_index = i + 1;
+    psPortCtrl->sRHPortDev.pUDev = udev;
+    psPortCtrl->sRHPortDev.bRHParent = TRUE;
+    RT_DEBUG_LOG(RT_DEBUG_USB, ("usb connected\n"));
+    rt_usbh_root_hub_connect_handler(s_sUSBHDev.uhcd, port_index, RT_FALSE);
+}
+
+static void nu_hcd_disconnect_callback(
+    struct udev_t *udev,
+    int param
+)
+{
+    int i;
+    int port_index;
+    S_NU_RH_PORT_CTRL *psPortCtrl;
+
+    for (i = 0; i < NU_MAX_USBH_PORT; i++)
+    {
+        psPortCtrl = &s_sUSBHDev.asPortCtrl[i];
+        if (psPortCtrl->sRHPortDev.pUDev == udev)
+            break;
+    }
+
+    if (i >= NU_MAX_USBH_PORT)
+    {
+        RT_DEBUG_LOG(RT_DEBUG_USB, ("ERROR: udev not found\n"));
+        return;
+    }
+
+    port_index = i + 1;
+
+    for (i = 0; i < NU_MAX_USBH_PIPE; i++)
+    {
+        if (psPortCtrl->sRHPortDev.apsEPInfo[i] != NULL)
+        {
+            usbh_quit_xfer(psPortCtrl->sRHPortDev.pUDev, psPortCtrl->sRHPortDev.apsEPInfo[i]);
+        }
+    }
+
+    psPortCtrl->sRHPortDev.pUDev = NULL;
+
+    RT_DEBUG_LOG(RT_DEBUG_USB, ("usb disconnect\n"));
+    rt_usbh_root_hub_disconnect_handler(s_sUSBHDev.uhcd, port_index);
+}
+
+/* USB host operations -----------------------------------------------------------*/
+static struct uhcd_ops nu_uhcd_ops =
+{
+    nu_reset_port,
+    nu_pipe_xfer,
+    nu_open_pipe,
+    nu_close_pipe,
+};
+
+static rt_err_t nu_hcd_init(rt_device_t device)
+{
+    struct nu_usbh_dev *pNuUSBHDev = (struct nu_usbh_dev *)device;
+    usbh_core_init();
+
+    //install connect/disconnect callback
+    usbh_install_conn_callback(nu_hcd_connect_callback, nu_hcd_disconnect_callback);
+    usbh_polling_root_hubs();
+
+    //create thread for polling usbh port status
+    /* create usb hub thread */
+    pNuUSBHDev->polling_thread = rt_thread_create("usbh_drv", nu_usbh_rh_thread_entry, RT_NULL,
+                                 NU_USBH_THREAD_STACK_SIZE, 8, 20);
+    if (pNuUSBHDev->polling_thread != RT_NULL)
+    {
+        /* startup usb host thread */
+        rt_thread_startup(pNuUSBHDev->polling_thread);
+    }
+    else
+    {
+        return -(RT_EEMPTY);
+    }
+
+    return RT_EOK;
+}
+
+/* global function for USB host library -----------------------------*/
+uint32_t usbh_get_ticks(void)
+{
+    return rt_tick_get();
+}
+
+void usbh_delay_ms(int msec)
+{
+    rt_thread_mdelay(msec);
+}
+
+uint32_t usbh_tick_from_millisecond(uint32_t msec)
+{
+    return rt_tick_from_millisecond(msec);
+}
+
+#if defined(RT_USING_PM)
+
+/* device pm suspend() entry. */
+static int usbhost_pm_suspend(const struct rt_device *device, rt_uint8_t mode)
+{
+    rt_err_t result;
+
+    struct nu_usbh_dev *pNuUSBHDev = (struct nu_usbh_dev *)device;
+
+    RT_ASSERT(pNuUSBHDev != RT_NULL);
+    switch (mode)
+    {
+    case PM_SLEEP_MODE_LIGHT:
+    case PM_SLEEP_MODE_DEEP:
+
+        pNuUSBHDev->polling_thread->stat = RT_THREAD_READY;
+        result = rt_thread_suspend(pNuUSBHDev->polling_thread);
+        RT_ASSERT(result == RT_EOK);
+
+        break;
+
+    default:
+        break;
+    }
+
+    return (int)RT_EOK;
+}
+
+/* device pm resume() entry. */
+static void usbhost_pm_resume(const struct rt_device *device, rt_uint8_t mode)
+{
+    rt_err_t result;
+    struct nu_usbh_dev *pNuUSBHDev = (struct nu_usbh_dev *)device;
+    RT_ASSERT(pNuUSBHDev != RT_NULL);
+
+    switch (mode)
+    {
+    case PM_SLEEP_MODE_LIGHT:
+    case PM_SLEEP_MODE_DEEP:
+        result = rt_thread_resume(pNuUSBHDev->polling_thread);
+        RT_ASSERT(result == RT_EOK);
+        break;
+
+    default:
+        break;
+    }
+}
+
+static struct rt_device_pm_ops device_pm_ops =
+{
+    .suspend = usbhost_pm_suspend,
+    .resume = usbhost_pm_resume,
+    .frequency_change = RT_NULL
+};
+#endif
+
+int nu_usbh_register(void)
+{
+    rt_err_t res = -RT_ERROR;
+
+#if !defined(BSP_USING_OTG)
+    SYS_UnlockReg();
+
+    /* Set OTG as USB Host role */
+    SYS->USBPHY = SYS_USBPHY_OTGPHYEN_Msk | SYS_USBPHY_SBO_Msk | (0x1 << SYS_USBPHY_USBROLE_Pos);
+
+    SYS_LockReg();
+#endif
+
+
+    rt_memset(&s_sUSBHDev, 0x0, sizeof(struct nu_usbh_dev));
+
+    uhcd_t uhcd = (uhcd_t)rt_malloc(sizeof(struct uhcd));
+    RT_ASSERT(res != RT_NULL);
+
+    rt_memset((void *)uhcd, 0, sizeof(struct uhcd));
+
+    uhcd->parent.type = RT_Device_Class_USBHost;
+    uhcd->parent.init = nu_hcd_init;
+    uhcd->parent.user_data = &s_sUSBHDev;
+
+    uhcd->ops = &nu_uhcd_ops;
+    uhcd->num_ports = NU_MAX_USBH_PORT;
+    s_sUSBHDev.uhcd = uhcd;
+
+    res = rt_device_register(&uhcd->parent, "usbh", RT_DEVICE_FLAG_DEACTIVATE);
+    RT_ASSERT(res == RT_EOK);
+
+    /*initialize the usb host function */
+    res = rt_usb_host_init();
+    RT_ASSERT(res == RT_EOK);
+
+#if defined(RT_USING_PM)
+    rt_pm_device_register(&uhcd->parent, &device_pm_ops);
+#endif
+
+    return RT_EOK;
+}
+INIT_DEVICE_EXPORT(nu_usbh_register);
+
+#endif
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_uspi.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_uspi.c
new file mode 100644
index 0000000000..c8efcc81e5
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_uspi.c
@@ -0,0 +1,607 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author           Notes
+* 2020-7-15       YHkuo            First version
+*
+******************************************************************************/
+#include 
+
+#if defined(BSP_USING_USPI)
+
+#define LOG_TAG                 "drv.uspi"
+#define DBG_ENABLE
+#define DBG_SECTION_NAME        LOG_TAG
+#define DBG_LEVEL               DBG_INFO
+#define DBG_COLOR
+#include 
+
+#include 
+#include 
+#include 
+
+#include "NuMicro.h"
+#include 
+
+#if defined(BSP_USING_USPI_PDMA)
+    #include 
+#endif
+/* Private define ---------------------------------------------------------------*/
+enum
+{
+    USPI_START = -1,
+#if defined(BSP_USING_USPI0)
+    USPI0_IDX,
+#endif
+#if defined(BSP_USING_USPI1)
+    USPI1_IDX,
+#endif
+    USPI_CNT
+};
+
+/* Private typedef --------------------------------------------------------------*/
+struct nu_uspi
+{
+    struct  rt_spi_bus  dev;
+    char    *name;
+    USPI_T  *uspi_base;
+    struct  rt_spi_configuration    configuration;
+    uint32_t    dummy;
+#if defined(BSP_USING_USPI_PDMA)
+    int16_t pdma_perp_tx;
+    int8_t  pdma_chanid_tx;
+    int16_t pdma_perp_rx;
+    int8_t  pdma_chanid_rx;
+    rt_sem_t    m_psSemBus;
+#endif
+};
+typedef struct nu_uspi *uspi_t;
+
+/* Private functions ------------------------------------------------------------*/
+static rt_err_t nu_uspi_bus_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration);
+static rt_uint32_t nu_uspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message);
+static void nu_uspi_transmission_with_poll(struct nu_uspi *uspi_bus,
+        uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word);
+static int nu_uspi_register_bus(struct nu_uspi *uspi_bus, const char *name);
+static void nu_uspi_drain_rxfifo(USPI_T *uspi_base);
+
+#if defined(BSP_USING_USPI_PDMA)
+    static void nu_pdma_uspi_rx_cb(void *pvUserData, uint32_t u32EventFilter);
+    static rt_err_t nu_pdma_uspi_rx_config(struct nu_uspi *uspi_bus, uint8_t *pu8Buf, int32_t i32RcvLen, uint8_t bytes_per_word);
+    static rt_err_t nu_pdma_uspi_tx_config(struct nu_uspi *uspi_bus, const uint8_t *pu8Buf, int32_t i32SndLen, uint8_t bytes_per_word);
+    static rt_size_t nu_uspi_pdma_transmit(struct nu_uspi *uspi_bus, const uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word);
+    static rt_err_t nu_hw_uspi_pdma_allocate(struct nu_uspi *uspi_bus);
+#endif
+/* Public functions -------------------------------------------------------------*/
+
+
+/* Private variables ------------------------------------------------------------*/
+static struct rt_spi_ops nu_uspi_poll_ops =
+{
+    .configure = nu_uspi_bus_configure,
+    .xfer      = nu_uspi_bus_xfer,
+};
+
+static struct nu_uspi nu_uspi_arr [] =
+{
+#if defined(BSP_USING_USPI0)
+    {
+        .name = "uspi0",
+        .uspi_base = USPI0,
+
+#if defined(BSP_USING_USPI_PDMA)
+#if defined(BSP_USING_USPI0_PDMA)
+        .pdma_perp_tx = PDMA_USCI0_TX,
+        .pdma_perp_rx = PDMA_USCI0_RX,
+#else
+        .pdma_perp_tx = NU_PDMA_UNUSED,
+        .pdma_perp_rx = NU_PDMA_UNUSED,
+#endif  //BSP_USING_USPI0_PDMA
+#endif  //BSP_USING_USPI_PDMA
+    },
+#endif
+#if defined(BSP_USING_USPI1)
+    {
+        .name = "uspi1",
+        .uspi_base = USPI1,
+
+#if defined(BSP_USING_USPI_PDMA)
+#if defined(BSP_USING_USPI1_PDMA)
+        .pdma_perp_tx = PDMA_USCI1_TX,
+        .pdma_perp_rx = PDMA_USCI1_RX,
+#else
+        .pdma_perp_tx = NU_PDMA_UNUSED,
+        .pdma_perp_rx = NU_PDMA_UNUSED,
+#endif  //BSP_USING_USPI1_PDMA
+#endif  //BSP_USING_USPI_PDMA
+
+    },
+#endif
+    {0}
+}; /* uspi nu_uspi */
+
+static rt_err_t nu_uspi_bus_configure(struct rt_spi_device *device,
+                                      struct rt_spi_configuration *configuration)
+{
+    struct nu_uspi *uspi_bus;
+    uint32_t u32SPIMode;
+    uint32_t u32BusClock;
+    rt_err_t ret = RT_EOK;
+
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(configuration != RT_NULL);
+
+    uspi_bus = (struct nu_uspi *) device->bus;
+
+    /* Check mode */
+    switch (configuration->mode & RT_SPI_MODE_3)
+    {
+    case RT_SPI_MODE_0:
+        u32SPIMode = USPI_MODE_0;
+        break;
+    case RT_SPI_MODE_1:
+        u32SPIMode = USPI_MODE_1;
+        break;
+    case RT_SPI_MODE_2:
+        u32SPIMode = USPI_MODE_2;
+        break;
+    case RT_SPI_MODE_3:
+        u32SPIMode = USPI_MODE_3;
+        break;
+    default:
+        ret = RT_EIO;
+        goto exit_nu_uspi_bus_configure;
+    }
+
+    /* Check data width */
+    if (!(configuration->data_width == 8  ||
+            configuration->data_width == 16))
+    {
+        ret = RT_EINVAL;
+        goto exit_nu_uspi_bus_configure;
+    }
+
+    /* Try to set clock and get actual uspi bus clock */
+    u32BusClock = USPI_SetBusClock(uspi_bus->uspi_base, configuration->max_hz);
+    if (configuration->max_hz > u32BusClock)
+    {
+        LOG_W("%s clock max frequency is %dHz (!= %dHz)\n", uspi_bus->name, u32BusClock, configuration->max_hz);
+        configuration->max_hz = u32BusClock;
+    }
+
+    /* Need to initialize new configuration? */
+    if (rt_memcmp(configuration, &uspi_bus->configuration, sizeof(*configuration)) != 0)
+    {
+        rt_memcpy(&uspi_bus->configuration, configuration, sizeof(*configuration));
+
+        USPI_Open(uspi_bus->uspi_base, USPI_MASTER, u32SPIMode, configuration->data_width, u32BusClock);
+
+        if (configuration->mode & RT_SPI_CS_HIGH)
+        {
+            /* Set CS pin to LOW */
+            USPI_SET_SS_LOW(uspi_bus->uspi_base);
+        }
+        else
+        {
+            /* Set CS pin to HIGH */
+            USPI_SET_SS_HIGH(uspi_bus->uspi_base);
+        }
+
+        if (configuration->mode & RT_SPI_MSB)
+        {
+            /* Set sequence to MSB first */
+            USPI_SET_MSB_FIRST(uspi_bus->uspi_base);
+        }
+        else
+        {
+            /* Set sequence to LSB first */
+            USPI_SET_LSB_FIRST(uspi_bus->uspi_base);
+        }
+    }
+
+    /* Clear USPI RX FIFO */
+    nu_uspi_drain_rxfifo(uspi_bus->uspi_base);
+
+exit_nu_uspi_bus_configure:
+
+    return -(ret);
+}
+
+#if defined(BSP_USING_USPI_PDMA)
+static void nu_pdma_uspi_rx_cb(void *pvUserData, uint32_t u32EventFilter)
+{
+    rt_err_t result;
+    struct nu_uspi *uspi_bus = (struct nu_uspi *)pvUserData;
+
+    RT_ASSERT(uspi_bus != RT_NULL);
+
+    result = rt_sem_release(uspi_bus->m_psSemBus);
+    RT_ASSERT(result == RT_EOK);
+}
+
+static rt_err_t nu_pdma_uspi_rx_config(struct nu_uspi *uspi_bus, uint8_t *pu8Buf, int32_t i32RcvLen, uint8_t bytes_per_word)
+{
+    rt_err_t result;
+    rt_uint8_t *dst_addr = NULL;
+    nu_pdma_memctrl_t memctrl = eMemCtl_Undefined;
+
+    /* Get base address of uspi register */
+    USPI_T *uspi_base = uspi_bus->uspi_base;
+
+    rt_uint8_t uspi_pdma_rx_chid = uspi_bus->pdma_chanid_rx;
+
+    result = nu_pdma_callback_register(uspi_pdma_rx_chid,
+                                       nu_pdma_uspi_rx_cb,
+                                       (void *)uspi_bus,
+                                       NU_PDMA_EVENT_TRANSFER_DONE);
+    if (result != RT_EOK)
+    {
+        goto exit_nu_pdma_uspi_rx_config;
+    }
+
+    if (pu8Buf == RT_NULL)
+    {
+        memctrl  = eMemCtl_SrcFix_DstFix;
+        dst_addr = (rt_uint8_t *) &uspi_bus->dummy;
+    }
+    else
+    {
+        memctrl  = eMemCtl_SrcFix_DstInc;
+        dst_addr = pu8Buf;
+    }
+
+    result = nu_pdma_channel_memctrl_set(uspi_pdma_rx_chid, memctrl);
+    if (result != RT_EOK)
+    {
+        goto exit_nu_pdma_uspi_rx_config;
+    }
+
+    result = nu_pdma_transfer(uspi_pdma_rx_chid,
+                              bytes_per_word * 8,
+                              (uint32_t)&uspi_base->RXDAT,
+                              (uint32_t)dst_addr,
+                              i32RcvLen / bytes_per_word,
+                              0);
+
+exit_nu_pdma_uspi_rx_config:
+
+    return result;
+}
+
+static rt_err_t nu_pdma_uspi_tx_config(struct nu_uspi *uspi_bus, const uint8_t *pu8Buf, int32_t i32SndLen, uint8_t bytes_per_word)
+{
+    rt_err_t result;
+    rt_uint8_t *src_addr = NULL;
+    nu_pdma_memctrl_t memctrl = eMemCtl_Undefined;
+
+    /* Get base address of uspi register */
+    USPI_T *uspi_base = uspi_bus->uspi_base;
+
+    rt_uint8_t uspi_pdma_tx_chid = uspi_bus->pdma_chanid_tx;
+
+    if (pu8Buf == RT_NULL)
+    {
+        uspi_bus->dummy = 0;
+        memctrl = eMemCtl_SrcFix_DstFix;
+        src_addr = (rt_uint8_t *)&uspi_bus->dummy;
+    }
+    else
+    {
+        memctrl = eMemCtl_SrcInc_DstFix;
+        src_addr = (rt_uint8_t *)pu8Buf;
+    }
+
+    result = nu_pdma_channel_memctrl_set(uspi_pdma_tx_chid, memctrl);
+    if (result != RT_EOK)
+    {
+        goto exit_nu_pdma_uspi_tx_config;
+    }
+
+    result = nu_pdma_transfer(uspi_pdma_tx_chid,
+                              bytes_per_word * 8,
+                              (uint32_t)src_addr,
+                              (uint32_t)&uspi_base->TXDAT,
+                              i32SndLen / bytes_per_word,
+                              0);
+
+exit_nu_pdma_uspi_tx_config:
+
+    return result;
+}
+
+
+/**
+ * USPI PDMA transfer
+ **/
+static rt_size_t nu_uspi_pdma_transmit(struct nu_uspi *uspi_bus, const uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word)
+{
+    rt_err_t result;
+
+    /* Get base address of uspi register */
+    USPI_T *uspi_base = uspi_bus->uspi_base;
+
+    result = nu_pdma_uspi_rx_config(uspi_bus, recv_addr, length, bytes_per_word);
+    RT_ASSERT(result == RT_EOK);
+    result = nu_pdma_uspi_tx_config(uspi_bus, send_addr, length, bytes_per_word);
+    RT_ASSERT(result == RT_EOK);
+
+    /* Trigger TX/RX at the same time. */
+    USPI_TRIGGER_TX_RX_PDMA(uspi_base);
+
+    /* Wait PDMA transfer done */
+    result = rt_sem_take(uspi_bus->m_psSemBus, RT_WAITING_FOREVER);
+    RT_ASSERT(result == RT_EOK);
+
+    /* Stop DMA TX/RX transfer */
+    USPI_DISABLE_TX_RX_PDMA(uspi_base);
+
+    return result;
+}
+
+static rt_err_t nu_hw_uspi_pdma_allocate(struct nu_uspi *uspi_bus)
+{
+    /* Allocate USPI_TX nu_dma channel */
+    if ((uspi_bus->pdma_chanid_tx = nu_pdma_channel_allocate(uspi_bus->pdma_perp_tx)) < 0)
+    {
+        goto exit_nu_hw_uspi_pdma_allocate;
+    }
+    /* Allocate USPI_RX nu_dma channel */
+    else if ((uspi_bus->pdma_chanid_rx = nu_pdma_channel_allocate(uspi_bus->pdma_perp_rx)) < 0)
+    {
+        nu_pdma_channel_free(uspi_bus->pdma_chanid_tx);
+        goto exit_nu_hw_uspi_pdma_allocate;
+    }
+
+    uspi_bus->m_psSemBus = rt_sem_create("uspibus_sem", 0, RT_IPC_FLAG_FIFO);
+    RT_ASSERT(uspi_bus->m_psSemBus != RT_NULL);
+
+    return RT_EOK;
+
+exit_nu_hw_uspi_pdma_allocate:
+
+    return -(RT_ERROR);
+}
+
+#endif
+
+static void nu_uspi_drain_rxfifo(USPI_T *uspi_base)
+{
+    while (USPI_IS_BUSY(uspi_base));
+
+    // Drain USPI RX FIFO, make sure RX FIFO is empty
+    while (!USPI_GET_RX_EMPTY_FLAG(uspi_base))
+    {
+        USPI_ClearRxBuf(uspi_base);
+    }
+}
+
+static int nu_uspi_read(USPI_T *uspi_base, uint8_t *recv_addr, uint8_t bytes_per_word)
+{
+    int size = 0;
+
+    // Read RX data
+    if (!USPI_GET_RX_EMPTY_FLAG(uspi_base))
+    {
+        uint32_t val;
+        // Read data from USPI RX FIFO
+        switch (bytes_per_word)
+        {
+        case 2:
+            val = USPI_READ_RX(uspi_base);
+            nu_set16_le(recv_addr, val);
+            break;
+        case 1:
+            *recv_addr = USPI_READ_RX(uspi_base);
+            break;
+        default:
+            LOG_E("Data length is not supported.\n");
+            break;
+        }
+        size = bytes_per_word;
+    }
+    return size;
+}
+
+static int nu_uspi_write(USPI_T *uspi_base, const uint8_t *send_addr, uint8_t bytes_per_word)
+{
+    // Wait USPI TX send data
+    while (USPI_GET_TX_FULL_FLAG(uspi_base));
+
+    // Input data to USPI TX
+    switch (bytes_per_word)
+    {
+    case 2:
+        USPI_WRITE_TX(uspi_base, nu_get16_le(send_addr));
+        break;
+    case 1:
+        USPI_WRITE_TX(uspi_base, *((uint8_t *)send_addr));
+        break;
+    default:
+        LOG_E("Data length is not supported.\n");
+        break;
+    }
+
+    return bytes_per_word;
+}
+
+/**
+ * @brief USPI bus polling
+ * @param dev : The pointer of the specified USPI module.
+ * @param send_addr : Source address
+ * @param recv_addr : Destination address
+ * @param length    : Data length
+ */
+static void nu_uspi_transmission_with_poll(struct nu_uspi *uspi_bus,
+        uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word)
+{
+    USPI_T *uspi_base = uspi_bus->uspi_base;
+
+    // Write-only
+    if ((send_addr != RT_NULL) && (recv_addr == RT_NULL))
+    {
+        while (length > 0)
+        {
+            send_addr += nu_uspi_write(uspi_base, send_addr, bytes_per_word);
+            length -= bytes_per_word;
+        }
+    } // if (send_addr != RT_NULL && recv_addr == RT_NULL)
+    // Read-only
+    else if ((send_addr == RT_NULL) && (recv_addr != RT_NULL))
+    {
+        uspi_bus->dummy = 0;
+        while (length > 0)
+        {
+            /* Input data to USPI TX FIFO */
+            length -= nu_uspi_write(uspi_base, (const uint8_t *)&uspi_bus->dummy, bytes_per_word);
+
+            /* Read data from USPI RX FIFO */
+            while (USPI_GET_RX_EMPTY_FLAG(uspi_base));
+            recv_addr += nu_uspi_read(uspi_base, recv_addr, bytes_per_word);
+        }
+    } // else if (send_addr == RT_NULL && recv_addr != RT_NULL)
+    // Read&Write
+    else
+    {
+        while (length > 0)
+        {
+            /* Input data to USPI TX FIFO */
+            send_addr += nu_uspi_write(uspi_base, send_addr, bytes_per_word);
+            length -= bytes_per_word;
+
+            /* Read data from USPI RX FIFO */
+            while (USPI_GET_RX_EMPTY_FLAG(uspi_base));
+            recv_addr += nu_uspi_read(uspi_base, recv_addr, bytes_per_word);
+        }
+    } // else
+
+    /* Wait USPI RX or drain USPI RX-FIFO */
+    if (recv_addr)
+    {
+        // Wait USPI transmission done
+        while (USPI_IS_BUSY(uspi_base))
+        {
+            while (!USPI_GET_RX_EMPTY_FLAG(uspi_base))
+            {
+                recv_addr += nu_uspi_read(uspi_base, recv_addr, bytes_per_word);
+            }
+        }
+
+        while (!USPI_GET_RX_EMPTY_FLAG(uspi_base))
+        {
+            recv_addr += nu_uspi_read(uspi_base, recv_addr, bytes_per_word);
+        }
+    }
+    else
+    {
+        /* Clear USPI RX FIFO */
+        nu_uspi_drain_rxfifo(uspi_base);
+    }
+}
+
+static void nu_uspi_transfer(struct nu_uspi *uspi_bus, uint8_t *tx, uint8_t *rx, int length, uint8_t bytes_per_word)
+{
+#if defined(BSP_USING_USPI_PDMA)
+    /* PDMA transfer constrains */
+    if ((uspi_bus->pdma_chanid_rx >= 0) &&
+            (!((uint32_t)tx % bytes_per_word)) &&
+            (!((uint32_t)rx % bytes_per_word)))
+        nu_uspi_pdma_transmit(uspi_bus, tx, rx, length, bytes_per_word);
+    else
+        nu_uspi_transmission_with_poll(uspi_bus, tx, rx, length, bytes_per_word);
+#else
+    nu_uspi_transmission_with_poll(uspi_bus, tx, rx, length, bytes_per_word);
+#endif
+}
+
+static rt_uint32_t nu_uspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
+{
+    struct nu_uspi *uspi_bus;
+    struct rt_spi_configuration *configuration;
+    uint8_t bytes_per_word;
+
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(device->bus != RT_NULL);
+    RT_ASSERT(message != RT_NULL);
+
+    uspi_bus = (struct nu_uspi *) device->bus;
+    configuration = &uspi_bus->configuration;
+    bytes_per_word = configuration->data_width / 8;
+
+    if ((message->length % bytes_per_word) != 0)
+    {
+        /* Say bye. */
+        LOG_E("%s: error payload length(%d%%%d != 0).\n", uspi_bus->name, message->length, bytes_per_word);
+        return 0;
+    }
+
+    if (message->length > 0)
+    {
+        if (message->cs_take && !(configuration->mode & RT_SPI_NO_CS))
+        {
+            if (configuration->mode & RT_SPI_CS_HIGH)
+            {
+                USPI_SET_SS_HIGH(uspi_bus->uspi_base);
+            }
+            else
+            {
+                USPI_SET_SS_LOW(uspi_bus->uspi_base);
+            }
+        }
+
+        nu_uspi_transfer(uspi_bus, (uint8_t *)message->send_buf, (uint8_t *)message->recv_buf, message->length, bytes_per_word);
+
+        if (message->cs_release && !(configuration->mode & RT_SPI_NO_CS))
+        {
+            if (configuration->mode & RT_SPI_CS_HIGH)
+            {
+                USPI_SET_SS_LOW(uspi_bus->uspi_base);
+            }
+            else
+            {
+                USPI_SET_SS_HIGH(uspi_bus->uspi_base);
+            }
+        }
+
+    }
+
+    return message->length;
+}
+
+static int nu_uspi_register_bus(struct nu_uspi *uspi_bus, const char *name)
+{
+    return rt_spi_bus_register(&uspi_bus->dev, name, &nu_uspi_poll_ops);
+}
+
+/**
+ * Hardware USPI Initial
+ */
+static int rt_hw_uspi_init(void)
+{
+    int i;
+
+    for (i = (USPI_START + 1); i < USPI_CNT; i++)
+    {
+        nu_uspi_register_bus(&nu_uspi_arr[i], nu_uspi_arr[i].name);
+#if defined(BSP_USING_USPI_PDMA)
+        nu_uspi_arr[i].pdma_chanid_tx = -1;
+        nu_uspi_arr[i].pdma_chanid_rx = -1;
+        if ((nu_uspi_arr[i].pdma_perp_tx != NU_PDMA_UNUSED) && (nu_uspi_arr[i].pdma_perp_rx != NU_PDMA_UNUSED))
+        {
+            if (nu_hw_uspi_pdma_allocate(&nu_uspi_arr[i]) != RT_EOK)
+            {
+                LOG_E("Failed to allocate DMA channels for %s. We will use poll-mode for this bus.\n", nu_uspi_arr[i].name);
+            }
+        }
+#endif
+    }
+
+    return 0;
+}
+
+INIT_DEVICE_EXPORT(rt_hw_uspi_init);
+
+#endif //#if defined(BSP_USING_USPI)
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_uuart.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_uuart.c
new file mode 100644
index 0000000000..04019f3463
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_uuart.c
@@ -0,0 +1,630 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author       Notes
+* 2020-6-20       ChingI       First version
+*
+******************************************************************************/
+
+#include 
+
+#if defined(BSP_USING_UUART)
+
+#include 
+#include 
+#include "NuMicro.h"
+
+#if defined(RT_SERIAL_USING_DMA)
+    #include 
+#endif
+
+/* Private define ---------------------------------------------------------------*/
+enum
+{
+    UUART_START = -1,
+#if defined(BSP_USING_UUART0)
+    UUART0_IDX,
+#endif
+#if defined(BSP_USING_UUART1)
+    UUART1_IDX,
+#endif
+    UUART_CNT
+};
+
+/* Private typedef --------------------------------------------------------------*/
+struct nu_uuart
+{
+    rt_serial_t dev;
+    char *name;
+    UUART_T *uuart_base;
+    uint32_t uuart_rst;
+    IRQn_Type uuart_irq_n;
+#if defined(RT_SERIAL_USING_DMA)
+    uint32_t dma_flag;
+    int16_t pdma_perp_tx;
+    int8_t  pdma_chanid_tx;
+
+    int16_t pdma_perp_rx;
+    int8_t  pdma_chanid_rx;
+    int32_t rx_write_offset;
+    int32_t rxdma_trigger_len;
+#endif
+};
+typedef struct nu_uuart *nu_uuart_t;
+
+/* Private functions ------------------------------------------------------------*/
+static rt_err_t nu_uuart_configure(struct rt_serial_device *serial, struct serial_configure *cfg);
+static rt_err_t nu_uuart_control(struct rt_serial_device *serial, int cmd, void *arg);
+static int nu_uuart_send(struct rt_serial_device *serial, char c);
+static int nu_uuart_receive(struct rt_serial_device *serial);
+static void nu_uuart_isr(nu_uuart_t serial);
+
+#if defined(RT_SERIAL_USING_DMA)
+    static rt_size_t nu_uuart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction);
+    static void nu_pdma_uuart_rx_cb(void *pvOwner, uint32_t u32Events);
+    static void nu_pdma_uuart_tx_cb(void *pvOwner, uint32_t u32Events);
+#endif
+
+/* Public functions ------------------------------------------------------------*/
+
+/* Private variables ------------------------------------------------------------*/
+
+static const struct rt_uart_ops nu_uuart_ops =
+{
+    .configure = nu_uuart_configure,
+    .control = nu_uuart_control,
+    .putc = nu_uuart_send,
+    .getc = nu_uuart_receive,
+#if defined(RT_SERIAL_USING_DMA)
+    .dma_transmit = nu_uuart_dma_transmit
+#else
+    .dma_transmit = RT_NULL
+#endif
+};
+
+static const struct serial_configure nu_uuart_default_config =
+        RT_SERIAL_CONFIG_DEFAULT;
+
+
+static struct nu_uuart nu_uuart_arr [] =
+{
+#if defined(BSP_USING_UUART0)
+    {
+        .name = "uuart0",
+        .uuart_base = UUART0,
+        .uuart_rst = USCI0_RST,
+        .uuart_irq_n = USCI0_IRQn,
+#if defined(RT_SERIAL_USING_DMA)
+#if defined(BSP_USING_UUART0_TX_DMA)
+        .pdma_perp_tx = PDMA_USCI0_TX,
+#else
+        .pdma_perp_tx = NU_PDMA_UNUSED,
+#endif
+#if defined(BSP_USING_UUART0_RX_DMA)
+        .pdma_perp_rx = PDMA_USCI0_RX,
+        .rx_write_offset = 0,
+#else
+        .pdma_perp_rx = NU_PDMA_UNUSED,
+#endif
+#endif
+    },
+#endif
+
+#if defined(BSP_USING_UUART1)
+    {
+        .name = "uuart1",
+        .uuart_base = UUART1,
+        .uuart_rst = USCI1_RST,
+        .uuart_irq_n = USCI1_IRQn,
+#if defined(RT_SERIAL_USING_DMA)
+#if defined(BSP_USING_UUART1_TX_DMA)
+        .pdma_perp_tx = PDMA_USCI1_TX,
+#else
+        .pdma_perp_tx = NU_PDMA_UNUSED,
+#endif
+#if defined(BSP_USING_UUART1_RX_DMA)
+        .pdma_perp_rx = PDMA_USCI1_RX,
+        .rx_write_offset = 0,
+#else
+        .pdma_perp_rx = NU_PDMA_UNUSED,
+#endif
+#endif
+    },
+#endif
+
+    {0}
+}; /* uuart nu_uuart */
+
+/* Interrupt Handle Function  ----------------------------------------------------*/
+#if defined(BSP_USING_UUART0)
+/* USCI0 interrupt entry */
+void USCI0_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    nu_uuart_isr(&nu_uuart_arr[UUART0_IDX]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+#if defined(BSP_USING_UUART1)
+/* USCI1 interrupt entry */
+void USCI1_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    nu_uuart_isr(&nu_uuart_arr[UUART1_IDX]);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+
+/**
+ * All UUART interrupt service routine
+ */
+static void nu_uuart_isr(nu_uuart_t serial)
+{
+    /* Get base address of uuart register */
+    UUART_T *uuart_base = ((nu_uuart_t)serial)->uuart_base;
+
+    /* Get interrupt event */
+    uint32_t u32IntSts = uuart_base->PROTSTS;
+    uint32_t u32FIFOSts = uuart_base->BUFSTS;
+
+    if (u32IntSts & (UUART_PROTSTS_PARITYERR_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_BREAK_Msk))
+    {
+        uuart_base->PROTSTS |= (UUART_PROTSTS_PARITYERR_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_BREAK_Msk);
+        return;
+    }
+
+    /* Handle RX event */
+    if (u32IntSts & UUART_PROTSTS_RXENDIF_Msk)
+    {
+        rt_hw_serial_isr(&serial->dev, RT_SERIAL_EVENT_RX_IND);
+    }
+    uuart_base->PROTSTS = u32IntSts;
+    uuart_base->BUFSTS = u32FIFOSts;
+}
+
+/**
+ * Configure uuart port
+ */
+static rt_err_t nu_uuart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    rt_err_t ret = RT_EOK;
+    uint32_t uuart_word_len = 0;
+    uint32_t uuart_stop_bit = 0;
+    uint32_t uuart_parity = 0;
+
+    /* Get base address of uuart register */
+    UUART_T *uuart_base = ((nu_uuart_t)serial)->uuart_base;
+
+    /* Check baud rate */
+    RT_ASSERT(cfg->baud_rate != 0);
+
+    /* Check word len */
+    switch (cfg->data_bits)
+    {
+    case DATA_BITS_5:
+        rt_kprintf("Unsupported data length");
+        goto exit_nu_uuart_configure;
+
+    case DATA_BITS_6:
+        uuart_word_len = UUART_WORD_LEN_6;
+        break;
+
+    case DATA_BITS_7:
+        uuart_word_len = UUART_WORD_LEN_7;
+        break;
+
+    case DATA_BITS_8:
+        uuart_word_len = UUART_WORD_LEN_8;
+        break;
+
+    default:
+        rt_kprintf("Unsupported data length");
+        ret = RT_EINVAL;
+        goto exit_nu_uuart_configure;
+    }
+
+    /* Check stop bit */
+    switch (cfg->stop_bits)
+    {
+    case STOP_BITS_1:
+        uuart_stop_bit = UUART_STOP_BIT_1;
+        break;
+
+    case STOP_BITS_2:
+        uuart_stop_bit = UUART_STOP_BIT_2;
+        break;
+
+    default:
+        rt_kprintf("Unsupported stop bit");
+        ret = RT_EINVAL;
+        goto exit_nu_uuart_configure;
+    }
+
+    /* Check parity */
+    switch (cfg->parity)
+    {
+    case PARITY_NONE:
+        uuart_parity = UUART_PARITY_NONE;
+        break;
+
+    case PARITY_ODD:
+        uuart_parity = UUART_PARITY_ODD;
+        break;
+
+    case PARITY_EVEN:
+        uuart_parity = UUART_PARITY_EVEN;
+        break;
+
+    default:
+        rt_kprintf("Unsupported parity");
+        ret = RT_EINVAL;
+        goto exit_nu_uuart_configure;
+    }
+    /* Reset this module */
+    SYS_ResetModule(((nu_uuart_t)serial)->uuart_rst);
+
+    /* Open UUart and set UUART baud rate */
+    UUART_Open(uuart_base, cfg->baud_rate);
+
+    /* Set line configuration. */
+    UUART_SetLine_Config(uuart_base, 0, uuart_word_len, uuart_parity, uuart_stop_bit);
+
+    /* Enable NVIC interrupt. */
+    NVIC_EnableIRQ(((nu_uuart_t)serial)->uuart_irq_n);
+
+exit_nu_uuart_configure:
+
+    if (ret != RT_EOK)
+        UUART_Close(uuart_base);
+
+    return -(ret);
+}
+
+#if defined(RT_SERIAL_USING_DMA)
+static rt_err_t nu_pdma_uuart_rx_config(struct rt_serial_device *serial, uint8_t *pu8Buf, int32_t i32TriggerLen)
+{
+    rt_err_t result = RT_EOK;
+
+    /* Get base address of uuart register */
+    UUART_T *uuart_base = ((nu_uuart_t)serial)->uuart_base;
+
+    result = nu_pdma_callback_register(((nu_uuart_t)serial)->pdma_chanid_rx,
+                                       nu_pdma_uuart_rx_cb,
+                                       (void *)serial,
+                                       NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT);
+
+    if (result != RT_EOK)
+    {
+        goto exit_nu_pdma_uuart_rx_config;
+    }
+
+    result = nu_pdma_transfer(((nu_uuart_t)serial)->pdma_chanid_rx,
+                              8,
+                              (uint32_t)&uuart_base->RXDAT,
+                              (uint32_t)pu8Buf,
+                              i32TriggerLen,
+                              1000);  //Idle-timeout, 1ms
+
+    if (result != RT_EOK)
+    {
+        goto exit_nu_pdma_uuart_rx_config;
+    }
+
+    //UUART PDMA reset
+    UUART_PDMA_ENABLE(uuart_base, UUART_PDMACTL_PDMARST_Msk);
+
+    /* Enable Receive Line interrupt & Start DMA RX transfer. */
+    UUART_EnableInt(uuart_base, UUART_RLS_INT_MASK);
+    UUART_PDMA_ENABLE(uuart_base, UUART_PDMACTL_RXPDMAEN_Msk | UUART_PDMACTL_PDMAEN_Msk);
+
+exit_nu_pdma_uuart_rx_config:
+
+    return result;
+}
+
+static void nu_pdma_uuart_rx_cb(void *pvOwner, uint32_t u32Events)
+{
+    rt_size_t recv_len = 0;
+    rt_size_t transferred_rxbyte = 0;
+    struct rt_serial_device *serial = (struct rt_serial_device *)pvOwner;
+    nu_uuart_t puuart = (nu_uuart_t)serial;
+    RT_ASSERT(serial != RT_NULL);
+
+    /* Get base address of uuart register */
+    UUART_T *uuart_base = puuart->uuart_base;
+
+    transferred_rxbyte = nu_pdma_transferred_byte_get(puuart->pdma_chanid_rx, puuart->rxdma_trigger_len);
+
+    if (u32Events & (NU_PDMA_EVENT_TRANSFER_DONE | NU_PDMA_EVENT_TIMEOUT))
+    {
+        if (u32Events & NU_PDMA_EVENT_TRANSFER_DONE)
+        {
+            if (serial->config.bufsz != 0)
+            {
+                struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
+
+                nu_pdma_uuart_rx_config(serial, &rx_fifo->buffer[0], puuart->rxdma_trigger_len);     // Config & trigger next
+            }
+
+            transferred_rxbyte = puuart->rxdma_trigger_len;
+        }
+        else if ((u32Events & NU_PDMA_EVENT_TIMEOUT) && !UUART_GET_RX_EMPTY(uuart_base))
+        {
+            return;
+        }
+
+        recv_len = transferred_rxbyte - puuart->rx_write_offset;
+
+        puuart->rx_write_offset = transferred_rxbyte % puuart->rxdma_trigger_len;
+
+    }
+
+    if ((serial->config.bufsz == 0) && (u32Events & NU_PDMA_EVENT_TRANSFER_DONE))
+    {
+        recv_len = puuart->rxdma_trigger_len;
+    }
+
+    if (recv_len)
+    {
+        rt_hw_serial_isr(&puuart->dev, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
+    }
+}
+
+static rt_err_t nu_pdma_uuart_tx_config(struct rt_serial_device *serial)
+{
+    rt_err_t result = RT_EOK;
+    RT_ASSERT(serial != RT_NULL);
+
+    result = nu_pdma_callback_register(((nu_uuart_t)serial)->pdma_chanid_tx,
+                                       nu_pdma_uuart_tx_cb,
+                                       (void *)serial,
+                                       NU_PDMA_EVENT_TRANSFER_DONE);
+
+    return result;
+}
+
+static void nu_pdma_uuart_tx_cb(void *pvOwner, uint32_t u32Events)
+{
+    nu_uuart_t puuart = (nu_uuart_t)pvOwner;
+
+    RT_ASSERT(puuart != RT_NULL);
+
+    // Stop DMA TX transfer
+    UUART_PDMA_DISABLE(puuart->uuart_base, UUART_PDMACTL_TXPDMAEN_Msk);
+
+    if (u32Events & NU_PDMA_EVENT_TRANSFER_DONE)
+    {
+        rt_hw_serial_isr(&puuart->dev, RT_SERIAL_EVENT_TX_DMADONE);
+    }
+}
+
+/**
+ * UUart DMA transfer
+ */
+static rt_size_t nu_uuart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
+{
+    rt_err_t result = RT_EOK;
+
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(buf != RT_NULL);
+
+    /* Get base address of uuart register */
+    UUART_T *uuart_base = ((nu_uuart_t)serial)->uuart_base;
+    if (direction == RT_SERIAL_DMA_TX)
+    {
+        result = nu_pdma_transfer(((nu_uuart_t)serial)->pdma_chanid_tx,
+                                  8,
+                                  (uint32_t)buf,
+                                  (uint32_t)&uuart_base->TXDAT,
+                                  size,
+                                  0);  // wait-forever
+        // Start DMA TX transfer
+        UUART_PDMA_ENABLE(uuart_base, UUART_PDMACTL_TXPDMAEN_Msk | UUART_PDMACTL_PDMAEN_Msk);
+    }
+    else if (direction == RT_SERIAL_DMA_RX)
+    {
+        // If config.bufsz = 0, serial will trigger once.
+        ((nu_uuart_t)serial)->rxdma_trigger_len = size;
+        ((nu_uuart_t)serial)->rx_write_offset = 0;
+        result = nu_pdma_uuart_rx_config(serial, buf, size);
+    }
+    else
+    {
+        result = RT_ERROR;
+    }
+
+    return result;
+}
+
+static int nu_hw_uuart_dma_allocate(nu_uuart_t puuart)
+{
+    RT_ASSERT(puuart != RT_NULL);
+
+    /* Allocate UUART_TX nu_dma channel */
+    if (puuart->pdma_perp_tx != NU_PDMA_UNUSED)
+    {
+        puuart->pdma_chanid_tx = nu_pdma_channel_allocate(puuart->pdma_perp_tx);
+        if (puuart->pdma_chanid_tx >= 0)
+        {
+            puuart->dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+        }
+    }
+
+    /* Allocate UUART_RX nu_dma channel */
+    if (puuart->pdma_perp_rx != NU_PDMA_UNUSED)
+    {
+        puuart->pdma_chanid_rx = nu_pdma_channel_allocate(puuart->pdma_perp_rx);
+        if (puuart->pdma_chanid_rx >= 0)
+        {
+            puuart->dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+        }
+    }
+
+    return RT_EOK;
+}
+#endif
+
+/**
+ * UUart interrupt control
+ */
+static rt_err_t nu_uuart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    rt_err_t result = RT_EOK;
+    rt_uint32_t flag = 0;
+    rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    /* Get base address of uuart register */
+    UUART_T *uuart_base = ((nu_uuart_t)serial)->uuart_base;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Disable INT-RX */
+        {
+            flag = UUART_RXEND_INT_MASK;
+            UUART_DisableInt(uuart_base, flag);
+        }
+        else if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Disable DMA-RX */
+        {
+            /* Disable Receive Line interrupt & Stop DMA RX transfer. */
+            flag = UUART_RLS_INT_MASK;
+            nu_pdma_channel_terminate(((nu_uuart_t)serial)->pdma_chanid_rx);
+            UUART_PDMA_DISABLE(uuart_base, UUART_PDMACTL_RXPDMAEN_Msk);
+            UUART_DisableInt(uuart_base, flag);
+        }
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) /* Enable INT-RX */
+        {
+            flag = UUART_RXEND_INT_MASK;
+            UUART_EnableInt(uuart_base, flag);
+        }
+        break;
+
+#if defined(RT_SERIAL_USING_DMA)
+    case RT_DEVICE_CTRL_CONFIG:
+        if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) /* Configure and trigger DMA-RX */
+        {
+            struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
+            ((nu_uuart_t)serial)->rxdma_trigger_len = serial->config.bufsz;
+            ((nu_uuart_t)serial)->rx_write_offset = 0;
+            result = nu_pdma_uuart_rx_config(serial, &rx_fifo->buffer[0], ((nu_uuart_t)serial)->rxdma_trigger_len);  // Config & trigger
+        }
+        else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) /* Configure DMA-TX */
+        {
+            result = nu_pdma_uuart_tx_config(serial);
+        }
+        break;
+#endif
+
+    case RT_DEVICE_CTRL_CLOSE:
+        /* Disable NVIC interrupt. */
+        NVIC_DisableIRQ(((nu_uuart_t)serial)->uuart_irq_n);
+
+#if defined(RT_SERIAL_USING_DMA)
+        nu_pdma_channel_terminate(((nu_uuart_t)serial)->pdma_chanid_tx);
+        nu_pdma_channel_terminate(((nu_uuart_t)serial)->pdma_chanid_rx);
+#endif
+
+        /* Reset this module */
+        SYS_ResetModule(((nu_uuart_t)serial)->uuart_rst);
+
+        /* Close UUART port */
+        UUART_Close(uuart_base);
+
+        break;
+    default:
+        result = -RT_EINVAL;
+        break;
+    }
+    return result;
+}
+
+/**
+ * UUart put char
+ */
+static int nu_uuart_send(struct rt_serial_device *serial, char c)
+{
+    RT_ASSERT(serial != RT_NULL);
+
+    /* Get base address of uuart register */
+    UUART_T *uuart_base = ((nu_uuart_t)serial)->uuart_base;
+
+    /* Waiting if TX-FIFO is full. */
+    while (UUART_IS_TX_FULL(uuart_base)) {};
+
+    /* Put char into TX-FIFO */
+    UUART_WRITE(uuart_base, c);
+
+    return 1;
+}
+
+/**
+ * UUart get char
+ */
+static int nu_uuart_receive(struct rt_serial_device *serial)
+{
+    RT_ASSERT(serial != RT_NULL);
+
+    /* Get base address of uuart register */
+    UUART_T *uuart_base = ((nu_uuart_t)serial)->uuart_base;
+
+    /* Return failure if RX-FIFO is empty. */
+    if (UUART_GET_RX_EMPTY(uuart_base) != 0)
+    {
+        return -1;
+    }
+
+    /* Get char from RX-FIFO */
+    return UUART_READ(uuart_base);
+}
+
+/**
+ * Hardware UUART Initialization
+ */
+static int rt_hw_uuart_init(void)
+{
+    int i;
+    rt_uint32_t flag;
+    rt_err_t ret = RT_EOK;
+
+    for (i = (UUART_START + 1); i < UUART_CNT; i++)
+    {
+        flag = RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX;
+
+        nu_uuart_arr[i].dev.ops    = &nu_uuart_ops;
+        nu_uuart_arr[i].dev.config = nu_uuart_default_config;
+
+#if defined(RT_SERIAL_USING_DMA)
+        nu_uuart_arr[i].dma_flag = 0;
+        nu_hw_uuart_dma_allocate(&nu_uuart_arr[i]);
+        flag |= nu_uuart_arr[i].dma_flag;
+#endif
+
+        ret = rt_hw_serial_register(&nu_uuart_arr[i].dev, nu_uuart_arr[i].name, flag, NULL);
+        RT_ASSERT(ret == RT_EOK);
+    }
+
+    return (int)ret;
+}
+
+INIT_DEVICE_EXPORT(rt_hw_uuart_init);
+
+#endif //#if defined(BSP_USING_UUART)
diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_wdt.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_wdt.c
new file mode 100644
index 0000000000..13ff9c13b6
--- /dev/null
+++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_wdt.c
@@ -0,0 +1,480 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author       Notes
+* 2020-07-24      klcheng      First version
+*
+******************************************************************************/
+
+#include 
+
+#if defined(BSP_USING_WDT)
+#include 
+#include 
+#include 
+#include "NuMicro.h"
+
+/*-------------------------------------------------------------------------------*/
+/* watchdog timer timeout look up table                                          */
+/*-------------------------------------------------------------------------------*/
+/* clock = LIRC 32000Hz.                                                         */
+/*                                                                               */
+/*      working hz   toutsel     exp     cycles      timeout (s)                 */
+/*      32000        0           4       16          0.0005                      */
+/*                   1           6       64          0.0020                      */
+/*                   2           8       256         0.0080                      */
+/*                   3           10      1024        0.0320                      */
+/*                   4           12      4096        0.1280                      */
+/*                   5           14      16384       0.5120                      */
+/*                   6           16      65536       2.0480                      */
+/*                   7           18      262144      8.1920                      */
+/*                   8           20      1048576     32.7680                     */
+/*-------------------------------------------------------------------------------*/
+/* clock = LXT 32768Hz.                                                          */
+/*                                                                               */
+/*      working hz   toutsel     exp     cycles      timeout (s)                 */
+/*      32768        0           4       16          0.0005                      */
+/*                   1           6       64          0.0020                      */
+/*                   2           8       256         0.0078                      */
+/*                   3           10      1024        0.0313                      */
+/*                   4           12      4096        0.1250                      */
+/*                   5           14      16384       0.5000                      */
+/*                   6           16      65536       2.0000                      */
+/*                   7           18      262144      8.0000                      */
+/*                   8           20      1048576     32.000                      */
+/*-------------------------------------------------------------------------------*/
+/* clock = 96MHz HCLK divide 2048 = 93750 Hz.                                    */
+/*                                                                               */
+/*      working hz   toutsel     exp     cycles      timeout (s)                 */
+/*      46875        0           4       16          0.00034                     */
+/*                   1           6       64          0.00137                     */
+/*                   2           8       256         0.00546                     */
+/*                   3           10      1024        0.02185                     */
+/*                   4           12      4096        0.08738                     */
+/*                   5           14      16384       0.34953                     */
+/*                   6           16      65536       1.39810                     */
+/*                   7           18      262144      5.59241                     */
+/*                   8           20      1048576     22.3696                     */
+/*-------------------------------------------------------------------------------*/
+
+/* Private define ---------------------------------------------------------------*/
+
+/* Pick a suitable wdt timeout interval, it is a trade-off between the
+   consideration of timeout accuracy and the system performance. The MIN_CYCLES
+   parameter is a numerical value of the toutsel setting, and it must be set to
+   a correct one which matches to the literal meaning of MIN_TOUTSEL. */
+#define MIN_TOUTSEL                 (WDT_TIMEOUT_2POW10)
+#define MIN_CYCLES                  (1024)
+
+
+/* Macros to convert the value between the timeout interval and the soft time iterations. */
+#define ROUND_TO_INTEGER(value)         ((int)(((value) * 10 + 5) / 10))
+#define CONV_SEC_TO_IT(hz, secs)        (ROUND_TO_INTEGER((float)((secs) * (hz)) / (float)(MIN_CYCLES)))
+#define CONV_IT_TO_SEC(hz, iterations)  (ROUND_TO_INTEGER((float)((iterations) * (MIN_CYCLES)) / (float)(hz)))
+
+
+/* Private typedef --------------------------------------------------------------*/
+struct soft_time_handle
+{
+    int clock_hz;
+    int wanted_sec;
+    int report_sec;
+    int left_iterations;
+    int full_iterations;
+    rt_bool_t expired;
+    rt_bool_t feed_dog;
+};
+
+typedef volatile struct soft_time_handle soft_time_handle_t;
+
+/* Private functions ------------------------------------------------------------*/
+static rt_err_t wdt_init(rt_watchdog_t *dev);
+static rt_err_t wdt_control(rt_watchdog_t *dev, int cmd, void *args);
+static uint32_t wdt_get_module_clock(void);
+static uint32_t wdt_get_working_hz(void);
+static void soft_time_init(soft_time_handle_t *const soft_time);
+static void soft_time_setup(uint32_t wanted_sec, uint32_t hz, soft_time_handle_t *const soft_time);
+static void soft_time_feed_dog(soft_time_handle_t *const soft_time);
+
+#if defined(RT_USING_PM)
+    static int wdt_pm_suspend(const struct rt_device *device, rt_uint8_t mode);
+    static void wdt_pm_resume(const struct rt_device *device, rt_uint8_t mode);
+    static int wdt_pm_frequency_change(const struct rt_device *device, rt_uint8_t mode);
+    static void soft_time_freqeucy_change(uint32_t new_hz, soft_time_handle_t *const soft_time);
+#endif
+
+/* Public functions -------------------------------------------------------------*/
+
+/* Private variables ------------------------------------------------------------*/
+static struct soft_time_handle soft_time;
+static struct rt_watchdog_device device_wdt;
+static struct rt_watchdog_ops ops_wdt =
+{
+    .init = wdt_init,
+    .control = wdt_control,
+};
+
+#if defined(RT_USING_PM)
+
+static struct rt_device_pm_ops device_pm_ops =
+{
+    .suspend = wdt_pm_suspend,
+    .resume = wdt_pm_resume,
+    .frequency_change = wdt_pm_frequency_change
+};
+#endif
+
+
+#if defined(RT_USING_PM)
+
+/* device pm suspend() entry. */
+static int wdt_pm_suspend(const struct rt_device *device, rt_uint8_t mode)
+{
+    switch (mode)
+    {
+    case PM_SLEEP_MODE_NONE:
+    case PM_SLEEP_MODE_IDLE:
+    case PM_SLEEP_MODE_STANDBY:
+    case PM_SLEEP_MODE_SHUTDOWN:
+        break;
+
+    case PM_SLEEP_MODE_LIGHT:
+    case PM_SLEEP_MODE_DEEP:
+
+        SYS_UnlockReg();
+        WDT->CTL &= ~WDT_CTL_WDTEN_Msk;
+        SYS_LockReg();
+        break;
+
+    default:
+        break;
+    }
+
+    return (int)RT_EOK;
+}
+
+
+/* device pm resume() entry. */
+static void wdt_pm_resume(const struct rt_device *device, rt_uint8_t mode)
+{
+    switch (mode)
+    {
+    case PM_SLEEP_MODE_NONE:
+    case PM_SLEEP_MODE_IDLE:
+    case PM_SLEEP_MODE_STANDBY:
+    case PM_SLEEP_MODE_SHUTDOWN:
+        break;
+
+    case PM_SLEEP_MODE_LIGHT:
+    case PM_SLEEP_MODE_DEEP:
+
+        SYS_UnlockReg();
+        WDT->CTL |= WDT_CTL_WDTEN_Msk;
+        SYS_LockReg();
+        break;
+
+    default:
+        break;
+    }
+}
+
+
+/* device pm frequency_change() entry. */
+static int wdt_pm_frequency_change(const struct rt_device *device, rt_uint8_t mode)
+{
+    uint32_t clk, new_hz;
+
+    new_hz = wdt_get_working_hz();
+    clk = wdt_get_module_clock();
+
+    if (clk == CLK_CLKSEL1_WDTSEL_HCLK_DIV2048)
+    {
+        if (new_hz == soft_time.clock_hz)
+            return (int)(RT_EOK);
+
+        /* frequency change occurs in critical section */
+        soft_time_freqeucy_change(new_hz, &soft_time);
+    }
+
+    return (int)(RT_EOK);
+}
+
+
+static void soft_time_freqeucy_change(uint32_t new_hz, soft_time_handle_t *const soft_time)
+{
+    rt_base_t level;
+    soft_time_handle_t new_time;
+    rt_bool_t corner_case = RT_FALSE;
+
+    level = rt_hw_interrupt_disable();
+
+    new_time.clock_hz = new_hz;
+    new_time.feed_dog = soft_time->feed_dog;
+    new_time.expired = soft_time->expired;
+    new_time.wanted_sec = soft_time->wanted_sec;
+    new_time.full_iterations = CONV_SEC_TO_IT(new_hz, soft_time->wanted_sec);
+    new_time.report_sec = CONV_IT_TO_SEC(new_hz, new_time.full_iterations);
+
+    new_time.left_iterations = ROUND_TO_INTEGER((float)soft_time->left_iterations *
+                               (float)new_hz / (float)soft_time->clock_hz);
+
+    if ((new_time.left_iterations == 0) && (soft_time->left_iterations > 0))
+    {
+        new_time.left_iterations++;;
+        corner_case = RT_TRUE;
+    }
+
+    *soft_time = new_time;
+    rt_hw_interrupt_enable(level);
+
+    if (corner_case)
+    {
+        LOG_W("pm frequency change cause wdt internal left iterations convert to 0.\n\r  \
+               wdt driver will add another 1 iteration for this corner case.");
+    }
+}
+#endif
+
+
+static void hw_wdt_init(void)
+{
+    SYS_UnlockReg();
+
+    if (WDT_GET_RESET_FLAG())
+    {
+        LOG_W("System re-boots from watchdog timer reset.\n");
+        WDT_CLEAR_RESET_FLAG();
+    }
+
+    SYS_LockReg();
+    NVIC_EnableIRQ(WDT_IRQn);
+}
+
+
+/* wdt device driver initialize. */
+int rt_hw_wdt_init(void)
+{
+    rt_err_t ret;
+
+    hw_wdt_init();
+
+    device_wdt.ops = &ops_wdt;
+    ret = rt_hw_watchdog_register(&device_wdt, "wdt", RT_DEVICE_FLAG_RDWR, RT_NULL);
+
+#if defined(RT_USING_PM)
+
+    rt_pm_device_register((struct rt_device *)&device_wdt, &device_pm_ops);
+#endif
+
+    return (int)ret;
+}
+INIT_BOARD_EXPORT(rt_hw_wdt_init);
+
+
+/* Register rt-thread device.init() entry. */
+static rt_err_t wdt_init(rt_watchdog_t *dev)
+{
+    soft_time_init(&soft_time);
+    hw_wdt_init();
+
+    return RT_EOK;
+}
+
+
+static uint32_t wdt_get_module_clock(void)
+{
+    return (CLK_GetModuleClockSource(WDT_MODULE) << CLK_CLKSEL1_WDTSEL_Pos);
+}
+
+
+static uint32_t wdt_get_working_hz(void)
+{
+    uint32_t clk, hz = 0;
+
+    clk = wdt_get_module_clock();
+
+    switch (clk)
+    {
+    case CLK_CLKSEL1_WDTSEL_LIRC:
+        hz = __LIRC;
+        break;
+
+    case CLK_CLKSEL1_WDTSEL_LXT:
+        hz = __LXT;
+        break;
+
+    case CLK_CLKSEL1_WDTSEL_HCLK_DIV2048:
+        hz = CLK_GetHCLKFreq() / 2048;
+        break;
+
+    default:
+        break;
+    }
+
+    return hz;
+}
+
+
+static void soft_time_init(soft_time_handle_t *const soft_time)
+{
+    rt_memset((void *)soft_time, 0, sizeof(struct soft_time_handle));
+
+}
+
+
+static void soft_time_setup(uint32_t wanted_sec, uint32_t hz, soft_time_handle_t *const soft_time)
+{
+    rt_base_t level;
+
+    level = rt_hw_interrupt_disable();
+
+    soft_time->expired = RT_FALSE;
+    soft_time->feed_dog = RT_FALSE;
+    soft_time->wanted_sec = wanted_sec;
+    soft_time->full_iterations = CONV_SEC_TO_IT(hz, wanted_sec);
+    soft_time->left_iterations = soft_time->full_iterations;
+    soft_time->report_sec = CONV_IT_TO_SEC(hz, soft_time->full_iterations);
+    soft_time->clock_hz = hz;
+
+    rt_hw_interrupt_enable(level);
+}
+
+
+static void soft_time_feed_dog(soft_time_handle_t *const soft_time)
+{
+    soft_time->feed_dog = RT_TRUE;
+}
+
+
+/* Register rt-thread device.control() entry. */
+static rt_err_t wdt_control(rt_watchdog_t *dev, int cmd, void *args)
+{
+    uint32_t wanted_sec, hz;
+    uint32_t *buf;
+    rt_err_t ret = RT_EOK;
+
+    if (dev == NULL)
+        return -(RT_EINVAL);
+
+    SYS_UnlockReg();
+
+    hz = wdt_get_working_hz();
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
+
+        if (args == RT_NULL)
+        {
+            ret = RT_EINVAL;
+            break;
+        }
+
+        buf = (uint32_t *)args;
+        *buf = soft_time.report_sec;
+        break;
+
+    case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
+
+        wanted_sec = *((uint32_t *)args);
+
+        if (wanted_sec == 0)
+        {
+            ret = RT_EINVAL;
+            break;
+        }
+
+        soft_time_setup(wanted_sec, hz, &soft_time);
+        break;
+
+    case RT_DEVICE_CTRL_WDT_GET_TIMELEFT:
+
+        if (args == RT_NULL)
+        {
+            ret = RT_EINVAL;
+            break;
+        }
+
+        buf = (uint32_t *)args;
+        *buf = CONV_IT_TO_SEC(hz, soft_time.left_iterations);
+        break;
+
+    case RT_DEVICE_CTRL_WDT_KEEPALIVE:
+
+        /* Make a mark that the application has fed the watchdog. */
+        soft_time_feed_dog(&soft_time);
+        break;
+
+    case RT_DEVICE_CTRL_WDT_START:
+
+        WDT_RESET_COUNTER();
+        WDT_Open(MIN_TOUTSEL, WDT_RESET_DELAY_1026CLK, TRUE, TRUE);
+        WDT_EnableInt();
+        break;
+
+    case RT_DEVICE_CTRL_WDT_STOP:
+
+        WDT_Close();
+        break;
+
+    default:
+        ret = RT_ERROR;
+    }
+
+    SYS_LockReg();
+
+    return -(ret);
+}
+
+
+/* wdt interrupt entry */
+void WDT_IRQHandler(void)
+{
+    rt_interrupt_enter();
+
+    /* Clear wdt interrupt flag */
+    if (WDT_GET_TIMEOUT_INT_FLAG())
+    {
+        WDT_CLEAR_TIMEOUT_INT_FLAG();
+    }
+
+    /* Clear wdt wakeup flag */
+    if (WDT_GET_TIMEOUT_WAKEUP_FLAG())
+    {
+        WDT_CLEAR_TIMEOUT_WAKEUP_FLAG();
+    }
+
+    /* The soft time has not reached the configured timeout yet. Clear the wdt counter
+       any way to prevent the system from hardware wdt reset. */
+    if (soft_time.left_iterations-- > 0)
+    {
+        WDT_RESET_COUNTER();
+    }
+
+    /* The soft time reaches the configured timeout boundary. Clear the wdt
+       counter if he application has fed the dog at least once until now. */
+    else
+    {
+        if ((soft_time.feed_dog) && (!soft_time.expired))
+        {
+            WDT_RESET_COUNTER();
+            soft_time.feed_dog =  RT_FALSE;
+            soft_time.left_iterations = soft_time.full_iterations;
+        }
+        else
+        {
+            /* Application does not feed the dog in time. */
+            soft_time.expired = RT_TRUE;
+        }
+    }
+
+    rt_interrupt_leave();
+}
+
+#endif /* BSP_USING_WDT */
+
+
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/SConscript b/bsp/nuvoton/libraries/m480/rtt_port/SConscript
index 77bd290714..2e80314127 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/SConscript
+++ b/bsp/nuvoton/libraries/m480/rtt_port/SConscript
@@ -10,24 +10,24 @@ group = []
 
 # USB driver constrain
 if GetDepend('BOARD_USING_HSUSBD') and ( GetDepend('BSP_USING_USBD') or GetDepend('BSP_USING_HSUSBH') or GetDepend('BSP_USING_HSOTG') ):
-    print 'Sorry, wrong selection.'
-    print '[Hint] You already select BOARD_USING_HSUSBD. Please de-select BSP_USING_USBD, BSP_USING_HSUSBH and BSP_USING_HSOTG options.'
+    print ('Sorry, wrong selection.')
+    print ('[Hint] You already select BOARD_USING_HSUSBD. Please de-select BSP_USING_USBD, BSP_USING_HSUSBH and BSP_USING_HSOTG options.')
     sys.exit(1)
 elif GetDepend('BOARD_USING_HSUSBD_USBH') and ( GetDepend('BSP_USING_USBD') or GetDepend('BSP_USING_HSUSBH') or GetDepend('BSP_USING_HSOTG') ):
-    print 'Sorry, wrong selection.'
-    print '[Hint] You already select BOARD_USING_HSUSBD_USBH. Please de-select BSP_USING_USBD, BSP_USING_HSUSBH and BSP_USING_HSOTG options.'
+    print ('Sorry, wrong selection.')
+    print ('[Hint] You already select BOARD_USING_HSUSBD_USBH. Please de-select BSP_USING_USBD, BSP_USING_HSUSBH and BSP_USING_HSOTG options.')
     sys.exit(1)
 elif GetDepend('BOARD_USING_HSUSBH') and ( GetDepend('BSP_USING_USBH') or GetDepend('BSP_USING_HSUSBD') or GetDepend('BSP_USING_HSOTG') ):
-    print 'Sorry, wrong selection.'
-    print '[Hint] You already select BOARD_USING_HSUSBH. Please de-select BSP_USING_USBH, BSP_USING_HSUSBD and BSP_USING_HSOTG options.'
+    print ('Sorry, wrong selection.')
+    print ('[Hint] You already select BOARD_USING_HSUSBH. Please de-select BSP_USING_USBH, BSP_USING_HSUSBD and BSP_USING_HSOTG options.')
     sys.exit(1)
 elif GetDepend('BOARD_USING_HSUSBH_USBD') and ( GetDepend('BSP_USING_USBH') or GetDepend('BSP_USING_HSUSBD') or GetDepend('BSP_USING_HSOTG') ):
-    print 'Sorry, wrong selection.'
-    print '[Hint] You already select BOARD_USING_HSUSBH_USBD. Please de-select BSP_USING_USBH, BSP_USING_HSUSBD and BSP_USING_HSOTG options.'
+    print ('Sorry, wrong selection.')
+    print ('[Hint] You already select BOARD_USING_HSUSBH_USBD. Please de-select BSP_USING_USBH, BSP_USING_HSUSBD and BSP_USING_HSOTG options.')
     sys.exit(1)
 elif GetDepend('BOARD_USING_HSOTG') and ( GetDepend('BSP_USING_USBD') or GetDepend('BSP_USING_USBH') ):
-    print 'Sorry, wrong selection.'
-    print '[Hint] You already select BOARD_USING_HSOTG. Please de-select BSP_USING_USBD and BSP_USING_USBH options.'
+    print ('Sorry, wrong selection.')
+    print ('[Hint] You already select BOARD_USING_HSOTG. Please de-select BSP_USING_USBD and BSP_USING_USBH options.')
     sys.exit(1)
 else:
     group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_bpwm_capture.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_bpwm_capture.c
index a28c1c1d5d..e592196c37 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_bpwm_capture.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_bpwm_capture.c
@@ -14,7 +14,7 @@
 #if defined(BSP_USING_BPWM_CAPTURE)
 #if ((BSP_USING_BPWM0_CAPTURE_CHMSK+BSP_USING_BPWM1_CAPTURE_CHMSK)!=0)
 #include 
-#include 
+#include "NuMicro.h"
 
 /* Private typedef --------------------------------------------------------------*/
 typedef struct _bpwm_dev
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_can.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_can.c
index bee0c04219..a667e34979 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_can.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_can.c
@@ -16,7 +16,7 @@
 
 #include 
 #include 
-#include 
+#include "NuMicro.h"
 
 /* Private Define ---------------------------------------------------------------*/
 #define RX_MSG_ID_INDEX        16
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_clk.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_clk.c
index f61852a0dc..867495804c 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_clk.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_clk.c
@@ -18,7 +18,7 @@
 #include 
 #include 
 #include 
-#include 
+#include "NuMicro.h"
 
 
 /* Private define ---------------------------------------------------------------*/
diff --git a/bsp/nuvoton/numaker-iot-m487/board/board.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_common.c
similarity index 70%
rename from bsp/nuvoton/numaker-iot-m487/board/board.c
rename to bsp/nuvoton/libraries/m480/rtt_port/drv_common.c
index 01d68aca61..8c8cc0abbf 100644
--- a/bsp/nuvoton/numaker-iot-m487/board/board.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_common.c
@@ -12,7 +12,7 @@
 
 #include 
 #include 
-#include 
+#include "NuMicro.h"
 #include "drv_uart.h"
 #include "board.h"
 #include "nutool_pincfg.h"
@@ -20,9 +20,9 @@
 
 
 /**
- * This function will initial M487 board.
+ * This function will initial.
  */
-void rt_hw_board_init(void)
+RT_WEAK void rt_hw_board_init(void)
 {
     /* Init System/modules clock */
     nutool_modclkcfg_init();
@@ -67,6 +67,41 @@ void rt_hw_board_init(void)
 #endif
 }
 
+/**
+ * The time delay function.
+ *
+ * @param microseconds.
+ */
+void rt_hw_us_delay(rt_uint32_t us)
+{
+    rt_uint32_t ticks;
+    rt_uint32_t told, tnow, tcnt = 0;
+    rt_uint32_t reload = SysTick->LOAD;
+
+    ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
+    told = SysTick->VAL;
+    while (1)
+    {
+        tnow = SysTick->VAL;
+        if (tnow != told)
+        {
+            if (tnow < told)
+            {
+                tcnt += told - tnow;
+            }
+            else
+            {
+                tcnt += reload - tnow + told;
+            }
+            told = tnow;
+            if (tcnt >= ticks)
+            {
+                break;
+            }
+        }
+    }
+}
+
 /**
  * This is the timer interrupt service routine.
  *
@@ -89,7 +124,7 @@ void rt_hw_cpu_reset(void)
     SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk;
 }
 
-int reboot(int argc, char** argv)
+int reboot(int argc, char **argv)
 {
     rt_hw_cpu_reset();
     return 0;
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_eadc.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_eadc.c
index 60fb68e44c..eb14a1dc4e 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_eadc.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_eadc.c
@@ -11,7 +11,7 @@
 
 #include 
 #include 
-#include 
+#include "NuMicro.h"
 
 #ifdef BSP_USING_EADC
 
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_ebi.h b/bsp/nuvoton/libraries/m480/rtt_port/drv_ebi.h
index 1b5aa5abd4..f639ec2f3f 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_ebi.h
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_ebi.h
@@ -13,7 +13,7 @@
 #define __DRV_EBI_H___
 
 #include 
-#include 
+#include "NuMicro.h"
 
 /**
   * @brief      Initialize EBI for specify Bank
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_ecap.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_ecap.c
index 0e354373af..c9e7c66a8d 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_ecap.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_ecap.c
@@ -14,7 +14,7 @@
 #if defined(BSP_USING_ECAP)
 #if ((BSP_USING_ECAP0_CHMSK+BSP_USING_ECAP1_CHMSK)!=0)
 #include 
-#include 
+#include "NuMicro.h"
 
 #define ECAP_CH0_POS    (0)
 #define ECAP_CH1_POS    (1)
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_emac.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_emac.c
index 3729553746..24b5eccc5f 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_emac.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_emac.c
@@ -17,7 +17,7 @@
 #if defined(RT_USING_LWIP)
 
 #include 
-#include 
+#include "NuMicro.h"
 #include 
 #include 
 #include 
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_epwm_capture.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_epwm_capture.c
index c95febf8eb..8dcfb92cd7 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_epwm_capture.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_epwm_capture.c
@@ -14,7 +14,7 @@
 #if defined(BSP_USING_EPWM_CAPTURE)
 #if ((BSP_USING_EPWM0_CAPTURE_CHMSK+BSP_USING_EPWM1_CAPTURE_CHMSK)!=0)
 #include 
-#include 
+#include "NuMicro.h"
 
 #define EPWM_CH0CH1_POS    (0)
 #define EPWM_CH2CH3_POS    (2)
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_fmc.h b/bsp/nuvoton/libraries/m480/rtt_port/drv_fmc.h
index 9a9ef373c3..d189d1102c 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_fmc.h
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_fmc.h
@@ -14,7 +14,7 @@
 #define __DRV_FMC_H__
 
 #include 
-#include 
+#include "NuMicro.h"
 
 int nu_fmc_read(long offset, uint8_t *buf, size_t size);
 int nu_fmc_write(long offset, const uint8_t *buf, size_t size);
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.c
index d00677392d..d718c5c06d 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_gpio.c
@@ -16,7 +16,7 @@
 
 #include 
 #include 
-#include 
+#include "NuMicro.h"
 #include 
 #include 
 #include 
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_hsotg.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_hsotg.c
index 17244d5e0a..5859f3244f 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_hsotg.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_hsotg.c
@@ -14,7 +14,7 @@
 #if defined(BSP_USING_HSOTG)
 #include 
 #include 
-#include 
+#include "NuMicro.h"
 
 
 /* This delay must be at least 10 us */
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_i2c.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_i2c.c
index ecf78a5c70..a89bc3156d 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_i2c.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_i2c.c
@@ -14,7 +14,7 @@
 
 #ifdef BSP_USING_I2C
 #include 
-#include 
+#include "NuMicro.h"
 
 /* Private define ---------------------------------------------------------------*/
 #define LOG_TAG         "drv.i2c"
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_i2s.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_i2s.c
index d76cb27314..be576e61c6 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_i2s.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_i2s.c
@@ -220,7 +220,8 @@ static rt_err_t nu_i2s_dai_setup(nu_i2s_t psNuI2s, struct rt_audio_configure *pc
         }
 
         /* Set MCLK and enable MCLK */
-        I2S_EnableMCLK(psNuI2s->i2s_base, __HXT);
+        /* The target MCLK is related to audio codec setting. */
+        I2S_EnableMCLK(psNuI2s->i2s_base, 12000000);
 
         /* Set unmute */
         if (pNuACodecOps->nu_acodec_mixer_control)
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_i2s.h b/bsp/nuvoton/libraries/m480/rtt_port/drv_i2s.h
index 3fe99f3e3b..9ee00646b8 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_i2s.h
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_i2s.h
@@ -14,7 +14,7 @@
 #define __DRV_I2S_H__
 
 #include 
-#include 
+#include "NuMicro.h"
 #include 
 
 #if !defined(NU_I2S_DMA_FIFO_SIZE)
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_pdma.h b/bsp/nuvoton/libraries/m480/rtt_port/drv_pdma.h
index 35082be311..f8a0169c06 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_pdma.h
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_pdma.h
@@ -15,7 +15,7 @@
 
 #include 
 #include 
-#include 
+#include "NuMicro.h"
 
 #ifndef NU_PDMA_SGTBL_POOL_SIZE
     #define NU_PDMA_SGTBL_POOL_SIZE (16)
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_rtc.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_rtc.c
index a80ac79627..d642d0116e 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_rtc.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_rtc.c
@@ -15,7 +15,7 @@
 
 #include 
 #include 
-#include 
+#include "NuMicro.h"
 
 /* Private define ---------------------------------------------------------------*/
 
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_scuart.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_scuart.c
index f187690f33..708435fef4 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_scuart.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_scuart.c
@@ -14,7 +14,7 @@
 
 #if defined(BSP_USING_SCUART)
 
-#include 
+#include "NuMicro.h"
 #include 
 #include 
 
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_sdh.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_sdh.c
index d02017d0cf..7c92743bd3 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_sdh.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_sdh.c
@@ -15,7 +15,7 @@
 #if defined(BSP_USING_SDH)
 
 #include 
-#include 
+#include "NuMicro.h"
 #include 
 #include 
 
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_softi2c.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_softi2c.c
index 7c8fe84a92..1549bf57f2 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_softi2c.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_softi2c.c
@@ -17,7 +17,7 @@
 #include 
 #include 
 #include 
-#include 
+#include "NuMicro.h"
 
 /* Private define ---------------------------------------------------------------*/
 #define LOG_TAG          "drv.softi2c"
@@ -65,7 +65,6 @@ struct nu_soft_i2c
 };
 
 /* Private functions ------------------------------------------------------------*/
-static void nu_soft_i2c_udelay(rt_uint32_t us);
 static void nu_soft_i2c_set_sda(void *data, rt_int32_t state);
 static void nu_soft_i2c_set_scl(void *data, rt_int32_t state);
 static rt_int32_t nu_soft_i2c_get_sda(void *data);
@@ -91,48 +90,13 @@ static const struct rt_i2c_bit_ops nu_soft_i2c_bit_ops =
     .set_scl  = nu_soft_i2c_set_scl,
     .get_sda  = nu_soft_i2c_get_sda,
     .get_scl  = nu_soft_i2c_get_scl,
-    .udelay   = nu_soft_i2c_udelay,
+    .udelay   = rt_hw_us_delay,
     .delay_us = 1,
     .timeout  = 100
 };
 
 /* Functions define ------------------------------------------------------------*/
 
-/**
- * The time delay function.
- *
- * @param microseconds.
- */
-static void nu_soft_i2c_udelay(rt_uint32_t us)
-{
-    rt_uint32_t ticks;
-    rt_uint32_t told, tnow, tcnt = 0;
-    rt_uint32_t reload = SysTick->LOAD;
-
-    ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
-    told = SysTick->VAL;
-    while (1)
-    {
-        tnow = SysTick->VAL;
-        if (tnow != told)
-        {
-            if (tnow < told)
-            {
-                tcnt += told - tnow;
-            }
-            else
-            {
-                tcnt += reload - tnow + told;
-            }
-            told = tnow;
-            if (tcnt >= ticks)
-            {
-                break;
-            }
-        }
-    }
-}
-
 /**
  * This function initializes the soft i2c pin.
  *
@@ -163,9 +127,9 @@ static rt_err_t nu_soft_i2c_bus_unlock(const struct nu_soft_i2c_config *cfg)
         while (i++ < 9)
         {
             rt_pin_write(cfg->scl, PIN_HIGH);
-            nu_soft_i2c_udelay(100);
+            rt_hw_us_delay(100);
             rt_pin_write(cfg->scl, PIN_LOW);
-            nu_soft_i2c_udelay(100);
+            rt_hw_us_delay(100);
         }
     }
     if (PIN_LOW == rt_pin_read(cfg->sda))
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_spi.h b/bsp/nuvoton/libraries/m480/rtt_port/drv_spi.h
index 1e7bd0db44..29a7ec1dce 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_spi.h
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_spi.h
@@ -16,7 +16,7 @@
 #include 
 
 #include 
-#include 
+#include "NuMicro.h"
 #include 
 
 #if defined(BSP_USING_SPI_PDMA)
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_spii2s.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_spii2s.c
index 801c6262c0..6495af5c03 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_spii2s.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_spii2s.c
@@ -282,7 +282,8 @@ static rt_err_t nu_spii2s_dai_setup(nu_i2s_t psNuSPII2s, struct rt_audio_configu
         LOG_I("Open SPII2S.");
 
         /* Set MCLK and enable MCLK */
-        SPII2S_EnableMCLK(spii2s_base, __HXT);
+        /* The target MCLK is related to audio codec setting. */
+        SPII2S_EnableMCLK(spii2s_base, 12000000);
 
         /* Set un-mute */
         if (pNuACodecOps->nu_acodec_mixer_control)
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_timer.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_timer.c
index 331155e258..456cbbc34a 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_timer.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_timer.c
@@ -15,7 +15,7 @@
 #if (defined(BSP_USING_TIMER) && defined(RT_USING_HWTIMER))
 
 #include 
-#include 
+#include "NuMicro.h"
 
 /* Private define ---------------------------------------------------------------*/
 #define NU_TIMER_DEVICE(timer) (nu_timer_t *)(timer)
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_timer_capture.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_timer_capture.c
index 4f9543664f..5f6df13e8a 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_timer_capture.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_timer_capture.c
@@ -19,7 +19,7 @@
     defined(BSP_USING_TIMER3_CAPTURE)
 
 #include 
-#include 
+#include "NuMicro.h"
 
 /* Private typedef --------------------------------------------------------------*/
 typedef struct _timer
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_uart.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_uart.c
index d694ab7d8c..3167bdc9d3 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_uart.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_uart.c
@@ -16,7 +16,7 @@
 
 #include 
 #include 
-#include 
+#include "NuMicro.h"
 #include 
 
 #if defined(RT_SERIAL_USING_DMA)
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_ui2c.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_ui2c.c
index 9130dc878b..2c46f637a4 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_ui2c.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_ui2c.c
@@ -15,7 +15,7 @@
 #if (defined(BSP_USING_UI2C) && defined(RT_USING_I2C))
 
 #include 
-#include 
+#include "NuMicro.h"
 
 /* Private define ---------------------------------------------------------------*/
 #define LOG_TAG          "drv.ui2c"
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_usbhost.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_usbhost.c
index be19dac9e5..65af8ec18c 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_usbhost.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_usbhost.c
@@ -17,7 +17,7 @@
 
 #include 
 #include 
-#include 
+#include "NuMicro.h"
 
 #include "usb.h"
 #include "usbh_lib.h"
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_uspi.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_uspi.c
index 656750144e..9189ff5f03 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_uspi.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_uspi.c
@@ -24,7 +24,7 @@
 #include 
 #include 
 
-#include 
+#include "NuMicro.h"
 #include 
 
 #if defined(BSP_USING_USPI_PDMA)
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_uuart.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_uuart.c
index 6cd29f79fe..1cd9e5a717 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_uuart.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_uuart.c
@@ -16,7 +16,7 @@
 
 #include 
 #include 
-#include 
+#include "NuMicro.h"
 
 #if defined(RT_SERIAL_USING_DMA)
     #include 
diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_wdt.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_wdt.c
index 15521aace9..ffe5f98a1a 100644
--- a/bsp/nuvoton/libraries/m480/rtt_port/drv_wdt.c
+++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_wdt.c
@@ -16,7 +16,7 @@
 #include 
 #include 
 #include 
-#include 
+#include "NuMicro.h"
 
 /*-------------------------------------------------------------------------------*/
 /* watchdog timer timeout look up table                                          */
diff --git a/bsp/nuvoton/libraries/nu_packages/AudioCodec/acodec_nau88l25.c b/bsp/nuvoton/libraries/nu_packages/AudioCodec/acodec_nau88l25.c
index 65b2f4afba..0bd7852e02 100644
--- a/bsp/nuvoton/libraries/nu_packages/AudioCodec/acodec_nau88l25.c
+++ b/bsp/nuvoton/libraries/nu_packages/AudioCodec/acodec_nau88l25.c
@@ -88,10 +88,10 @@ static int I2C_WriteNAU88L25(uint16_t u16addr, uint16_t u16data)
 static int I2C_ReadNAU88L25(uint16_t u16addr, uint16_t *pu16data)
 {
     struct rt_i2c_msg msgs[2];
-    uint16_t u16data = 0;
     char au8TxData[2];
 
     RT_ASSERT(g_I2cBusDev != NULL);
+    RT_ASSERT(pu16data != NULL);
 
     au8TxData[0] = (uint8_t)((u16addr >> 8) & 0x00FF);   //addr [15:8]
     au8TxData[1] = (uint8_t)(u16addr & 0x00FF);          //addr [ 7:0]
@@ -103,8 +103,8 @@ static int I2C_ReadNAU88L25(uint16_t u16addr, uint16_t *pu16data)
 
     msgs[1].addr  = DEF_NAU88L25_ADDR;        /* Slave address */
     msgs[1].flags = RT_I2C_RD;                /* Read flag */
-    msgs[1].buf   = (rt_uint8_t *)&u16data;   /* Read data pointer */
-    msgs[1].len   = sizeof(u16data);          /* Number of bytes read */
+    msgs[1].buf   = (rt_uint8_t *)pu16data;   /* Read data pointer */
+    msgs[1].len   = sizeof(uint16_t);         /* Number of bytes read */
 
     if (rt_i2c_transfer(g_I2cBusDev, &msgs[0], 2) != 2)
     {
diff --git a/bsp/nuvoton/libraries/nu_packages/AudioCodec/audio_test.c b/bsp/nuvoton/libraries/nu_packages/AudioCodec/audio_test.c
index d82641b0c7..b36db998a8 100644
--- a/bsp/nuvoton/libraries/nu_packages/AudioCodec/audio_test.c
+++ b/bsp/nuvoton/libraries/nu_packages/AudioCodec/audio_test.c
@@ -26,6 +26,8 @@
 static int audio_test(int argc, char **argv)
 {
 #define DEF_MAX_ARGV_NUM 8
+#define DEF_MAX_TEST_SECOND 5
+
     int smplrate[] = {8000, 16000, 44100, 48000};
     int smplbit[] = {16};
     int chnum[] = {1, 2};
@@ -54,9 +56,9 @@ static int audio_test(int argc, char **argv)
                     info.samplebits = smplbit[j];
                     info.channels = chnum[k];
                     wavrecorder_start(&info);
-                    rt_thread_mdelay(10000);
+                    rt_thread_mdelay(DEF_MAX_TEST_SECOND * 1000);
                     wavrecorder_stop();
-                    rt_thread_mdelay(1000);
+                    rt_thread_mdelay(DEF_MAX_TEST_SECOND * 1000);
                 }
                 else
                 {
@@ -68,7 +70,7 @@ static int audio_test(int argc, char **argv)
 
                     rt_kprintf("Replay file at %s\n", strbuf);
                     wavplayer_play(strbuf);
-                    rt_thread_mdelay(10000);
+                    rt_thread_mdelay(DEF_MAX_TEST_SECOND * 1000);
                     wavplayer_stop();
                 }
             } // k
diff --git a/bsp/nuvoton/libraries/nu_packages/Demo/slcd_show_tick.c b/bsp/nuvoton/libraries/nu_packages/Demo/slcd_show_tick.c
index 26ef126f6f..7df6a26841 100644
--- a/bsp/nuvoton/libraries/nu_packages/Demo/slcd_show_tick.c
+++ b/bsp/nuvoton/libraries/nu_packages/Demo/slcd_show_tick.c
@@ -19,6 +19,15 @@
 
 #include "slcd_rhe6616tp01.h"
 
+#if defined(RT_USING_NETDEV)
+    #if defined(RT_USING_SAL)
+        #include 
+    #elif defined(RT_USING_LWIP)
+        #include 
+    #endif /* RT_USING_SAL */
+    #include 
+#endif
+
 const uint32_t au32SLCDSymbols [] =
 {
     SYMBOL_NVT,
@@ -69,31 +78,61 @@ const int i32SLCDSymbolsSize  = sizeof(au32SLCDSymbols) / sizeof(au32SLCDSymbols
 
 void slcd_demo_hook(void)
 {
+    static uint32_t u32NextShowTime = 0;
+    static uint32_t u32ShownTime = 0;
     uint32_t u32CurTickCount = rt_tick_get();
+    char au8Str[16];
 
-    /* ZONE_MAIN_DIGIT */
-    LCDLIB_PrintNumber(ZONE_MAIN_DIGIT, u32CurTickCount);
+    if (u32CurTickCount < u32NextShowTime)
+        return;
 
-    /* ZONE_PPM_DIGIT */
-    LCDLIB_PrintNumber(ZONE_PPM_DIGIT, u32CurTickCount);
+    u32NextShowTime = u32CurTickCount + 500;
+    u32ShownTime++;
 
-    /* ZONE_TEMP_DIGIT */
-    LCDLIB_PrintNumber(ZONE_TEMP_DIGIT, u32CurTickCount);
+    /* Show NuMicro Log. */
+    {
+        LCDLIB_SetSymbol(SYMBOL_NVT, 1);
+        LCDLIB_SetSymbol(SYMBOL_NUMICRO, 1);
+        LCDLIB_SetSymbol(SYMBOL_ARROW_UP, 1);
+        LCDLIB_SetSymbol(SYMBOL_ARROW_LEFT, 1);
+        LCDLIB_SetSymbol(SYMBOL_ARROW_DOWN, 1);
+        LCDLIB_SetSymbol(SYMBOL_ARROW_RIGHT, 1);
+        LCDLIB_SetSymbol(SYMBOL_CIRCLE_UP, 1);
+        LCDLIB_SetSymbol(SYMBOL_CIRCLE_LEFT, 1);
+        LCDLIB_SetSymbol(SYMBOL_CIRCLE_RIGHT,  1);
+    }
+    {
+        struct tm *g_pstm;
+        time_t now;
+        /* output current time */
+        now = time(RT_NULL);
+        g_pstm = localtime(&now);
+        rt_snprintf(au8Str, sizeof(au8Str), "%02d%02d", g_pstm->tm_hour, g_pstm->tm_min);
+        LCDLIB_Printf(ZONE_TIME_DIGIT, &au8Str[0]);
+        LCDLIB_SetSymbol(SYMBOL_TIME_DIG_COL1, u32ShownTime % 2);
 
-    /* ZONE_VER_DIGIT */
-    LCDLIB_PrintNumber(ZONE_VER_DIGIT, u32CurTickCount);
+        rt_snprintf(au8Str, sizeof(au8Str), "-%02d", g_pstm->tm_sec);
+        LCDLIB_Printf(ZONE_NUMICRO_DIGIT, &au8Str[0]);
+    }
+    /* Show RTT version. */
+    {
+        LCDLIB_SetSymbol(SYMBOL_VERSION, 1);
+        rt_snprintf(au8Str, sizeof(au8Str), "%d%02d%03d", RT_VERSION, RT_SUBVERSION, RT_REVISION);
+        LCDLIB_Printf(ZONE_VER_DIGIT, &au8Str[0]);
+        LCDLIB_SetSymbol(SYMBOL_VER_DIG_P1, 1);
+        LCDLIB_SetSymbol(SYMBOL_VER_DIG_P2, 1);
+    }
 
-    /* ZONE_TIME_DIGIT */
-    LCDLIB_PrintNumber(ZONE_TIME_DIGIT, u32CurTickCount);
-
-    /* ZONE_NUMICRO_DIGIT */
-    LCDLIB_PrintNumber(ZONE_NUMICRO_DIGIT, u32CurTickCount);
-
-    /* Travel all symbols */
-    LCDLIB_SetSymbol(au32SLCDSymbols[u32CurTickCount % i32SLCDSymbolsSize], (u32CurTickCount / i32SLCDSymbolsSize) % 2);
+#if defined(RT_USING_NETDEV)
+    /* Show Wi-Fi connective if leased an ip address. */
+    {
+        struct netdev *netdev = netdev_get_by_name("esp0");
+        LCDLIB_SetSymbol(SYMBOL_WIFI, netdev_is_dhcp_enabled(netdev));
+    }
+#endif
 
     /* Travel all dots */
-    LCDLIB_SetSymbol(SYMBOL_S(u32CurTickCount % 40 + 1), (u32CurTickCount / 40) % 2);
+    LCDLIB_SetSymbol(SYMBOL_S(u32ShownTime % 40 + 1), (u32ShownTime / 40) % 2);
 }
 
 static int slcd_demo_init(void)
diff --git a/bsp/nuvoton/libraries/nu_packages/SLCD/slcd_rhe6616tp01.c b/bsp/nuvoton/libraries/nu_packages/SLCD/slcd_rhe6616tp01.c
index d58d0b90f4..232d05438f 100644
--- a/bsp/nuvoton/libraries/nu_packages/SLCD/slcd_rhe6616tp01.c
+++ b/bsp/nuvoton/libraries/nu_packages/SLCD/slcd_rhe6616tp01.c
@@ -570,9 +570,24 @@ void LCDLIB_Printf(uint32_t u32Zone, char *InputStr)
             ch = 0x20;
         }
 
-        /* The Main Digit Table is an ASCII table beginning with "SPACE" (hex is 0x20) */
-        ch       = ch - 0x20;
-        DispData = *(g_LCDDispTable[u32Zone] + ch);
+        /* For Main Zone */
+        if (u32Zone == ZONE_MAIN_DIGIT)
+        {
+            /* The Main Digit Table is an ASCII table beginning with "SPACE" (hex is 0x20) */
+            ch = ch - 0x20;
+            DispData = *(g_LCDDispTable[u32Zone] + ch);
+        }
+        /* For Other Zones (Support '0' ~ '9' only) */
+        else if ((ch >= '0') && (ch <= '9'))
+        {
+            ch = ch - '0';
+            DispData = *(g_LCDDispTable[u32Zone] + ch);
+        }
+        /* Out of definition. Will show "SPACE" */
+        else
+        {
+            DispData = 0;
+        }
 
         for (i = 0; i < g_LCDZoneInfo[u32Zone].u32MaxSegNum; i++)
         {
@@ -660,15 +675,30 @@ void LCDLIB_PrintNumber(uint32_t u32Zone, uint32_t InputNum)
  */
 void LCDLIB_PutChar(uint32_t u32Zone, uint32_t u32Index, uint8_t u8Ch)
 {
-    uint32_t    i, ch;
+    uint32_t    i;
     uint16_t    DispData;
     uint32_t    com, seg;
 
     if (u32Index <= g_LCDZoneInfo[u32Zone].u32DigitCnt)
     {
-        /* Defined letters currently starts at "SPACE" - 0x20; */
-        ch       = u8Ch - 0x20;
-        DispData = *(g_LCDDispTable[u32Zone] + ch);
+        /* For Main Zone */
+        if (u32Zone == ZONE_MAIN_DIGIT)
+        {
+            /* The Main Digit Table is an ASCII table beginning with "SPACE" (hex is 0x20) */
+            u8Ch = u8Ch - 0x20;
+            DispData = *(g_LCDDispTable[u32Zone] + u8Ch);
+        }
+        /* For Other Zones (Support '0' ~ '9' only) */
+        else if ((u8Ch >= '0') && (u8Ch <= '9'))
+        {
+            u8Ch = u8Ch - '0';
+            DispData = *(g_LCDDispTable[u32Zone] + u8Ch);
+        }
+        /* Out of definition. Will show "SPACE" */
+        else
+        {
+            DispData = 0;
+        }
 
         for (i = 0; i < g_LCDZoneInfo[u32Zone].u32MaxSegNum; i++)
         {
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/Kconfig b/bsp/nuvoton/libraries/nuc980/rtt_port/Kconfig
index d2c34d6461..e7293b535d 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/Kconfig
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/Kconfig
@@ -30,21 +30,6 @@ config SOC_SERIES_NUC980
         select RT_USING_PIN
         default y
 
-    menuconfig BSP_USING_CLK
-        bool "Enable Clock Controller(CLK)"
-        select RT_USING_PM
-        select BSP_USING_TMR
-        default y
-        help
-            Choose this option if you need CLK/PM function.
-            Notice: Enable the option will hold timer3 resource
-
-        if BSP_USING_CLK
-            config NU_CLK_INVOKE_WKTMR
-            bool "Enable SPD1 and DPD mode wakeup timer. (About 6.6 Secs)"
-            default y
-        endif
-
     menuconfig BSP_USING_EMAC
         bool "Enable Ethernet MAC Controller(EMAC)"
         select RT_USING_LWIP
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_adc.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_adc.c
index a35fe81c8b..721bd5d6c1 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_adc.c
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_adc.c
@@ -14,7 +14,7 @@
 #if defined(BSP_USING_ADC)
 
 #include 
-#include 
+#include "NuMicro.h"
 #include 
 
 /* Private define ---------------------------------------------------------------*/
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_can.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_can.c
index 66d3a8f870..3b48867bb2 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_can.c
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_can.c
@@ -16,7 +16,7 @@
 
 #include 
 #include 
-#include 
+#include "NuMicro.h"
 #include 
 
 /* Private Define ---------------------------------------------------------------*/
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_ebi.h b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_ebi.h
index c42a85e226..a5427aa278 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_ebi.h
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_ebi.h
@@ -13,7 +13,7 @@
 #define __DRV_EBI_H___
 
 #include 
-#include 
+#include "NuMicro.h"
 
 #define MAX_BANK    EBI_BANK2
 
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_emac.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_emac.c
index be0451ec5e..b74189cb84 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_emac.c
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_emac.c
@@ -17,7 +17,7 @@
 #if defined(RT_USING_LWIP)
 
 #include 
-#include 
+#include "NuMicro.h"
 #include 
 #include 
 #include 
@@ -117,7 +117,7 @@ static struct nu_emac nu_emac_arr[] =
         .name           =  "e1",
         .memmgr.psEmac  = (EMAC_T *)EMC1_BA,
         .irqn_tx        =  IRQ_EMC1_TX,
-        .irqn_rx        =  IRQ_EMC1_RX
+        .irqn_rx        =  IRQ_EMC1_RX,
         .rstidx         =  EMAC1RST,
         .clkidx         =  EMAC1CKEN,
     },
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_etimer.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_etimer.c
index c009af16c7..cf7ff232cd 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_etimer.c
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_etimer.c
@@ -15,7 +15,7 @@
 #if defined(BSP_USING_TIMER) && defined(RT_USING_HWTIMER)
 
 #include 
-#include 
+#include "NuMicro.h"
 #include 
 
 /* Private define ---------------------------------------------------------------*/
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_etimer_capture.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_etimer_capture.c
index 0e2ae9384e..761ef73847 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_etimer_capture.c
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_etimer_capture.c
@@ -15,7 +15,7 @@
 #if defined(BSP_USING_TIMER_CAPTURE)
 
 #include 
-#include 
+#include "NuMicro.h"
 #include 
 
 /* Private define ---------------------------------------------------------------*/
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_gpio.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_gpio.c
index 71d8b6f012..ec2b2ac94b 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_gpio.c
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_gpio.c
@@ -16,7 +16,7 @@
 
 #include 
 #include 
-#include 
+#include "NuMicro.h"
 #include 
 #include 
 #include 
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_i2c.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_i2c.c
index b260b7fc18..30bc34ff66 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_i2c.c
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_i2c.c
@@ -15,7 +15,7 @@
 #if defined( BSP_USING_I2C)
 
 #include 
-#include 
+#include "NuMicro.h"
 #include 
 #include 
 
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_i2s.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_i2s.c
index 4c4a01599f..b8646d46a8 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_i2s.c
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_i2s.c
@@ -16,7 +16,7 @@
 
 #include 
 #include 
-#include 
+#include "NuMicro.h"
 
 /* Private define ---------------------------------------------------------------*/
 #define DBG_ENABLE
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_i2s.h b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_i2s.h
index 8f041e4271..2b4c877acb 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_i2s.h
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_i2s.h
@@ -15,7 +15,7 @@
 
 #include 
 #include 
-#include 
+#include "NuMicro.h"
 
 #if !defined(NU_I2S_DMA_FIFO_SIZE)
     #define NU_I2S_DMA_FIFO_SIZE (2048)
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_pdma.h b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_pdma.h
index 66ac50df43..1267dcb9fa 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_pdma.h
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_pdma.h
@@ -15,7 +15,7 @@
 
 #include 
 #include 
-#include 
+#include "NuMicro.h"
 #include 
 
 #define NU_PDMA_CAP_NONE    (0 << 0)
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_rtc.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_rtc.c
index 49418316d1..e3866e7d22 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_rtc.c
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_rtc.c
@@ -15,7 +15,7 @@
 
 #include 
 #include 
-#include 
+#include "NuMicro.h"
 #include 
 
 /* Private define ---------------------------------------------------------------*/
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_scuart.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_scuart.c
index 3b08c224e2..6867eb8827 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_scuart.c
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_scuart.c
@@ -12,12 +12,9 @@
 
 #include 
 
-#define BSP_USING_SCUART
-#define BSP_USING_SCUART0
-
 #if defined(BSP_USING_SCUART)
 
-#include 
+#include "NuMicro.h"
 #include 
 #include 
 #include 
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_sdh.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_sdh.c
index 85f4878518..6990ce215c 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_sdh.c
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_sdh.c
@@ -16,7 +16,7 @@
 
 #include 
 #include 
-#include 
+#include "NuMicro.h"
 #include 
 #include 
 
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_softi2c.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_softi2c.c
index d2e08fbb3b..f638c51ff6 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_softi2c.c
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_softi2c.c
@@ -17,7 +17,7 @@
 #include 
 #include 
 #include 
-#include 
+#include "NuMicro.h"
 #include "drv_sys.h"
 
 /* Private define ---------------------------------------------------------------*/
@@ -106,7 +106,7 @@ static const struct rt_i2c_bit_ops nu_soft_i2c_bit_ops =
  */
 static void nu_soft_i2c_udelay(rt_uint32_t us)
 {
-    nu_systick_udelay(us);
+    rt_hw_us_delay(us);
 }
 
 /**
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_spi.h b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_spi.h
index 30d574528c..32efa3bb0c 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_spi.h
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_spi.h
@@ -16,7 +16,7 @@
 #include 
 
 #include 
-#include 
+#include "NuMicro.h"
 #include 
 
 #if defined(BSP_USING_SPI_PDMA)
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_sys.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_sys.c
index 97b4fff76c..c19d2dd34a 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_sys.c
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_sys.c
@@ -348,4 +348,22 @@ int nu_clocks(int argc, char **argv)
 MSH_CMD_EXPORT(nu_clocks, Get all system clocks);
 #endif
 
+#ifdef RT_USING_INTERRUPT_INFO
+int list_interrupt(int argc, char **argv)
+{
+    int i;
+
+    for (i = 1; i <= SYS_MAX_INT_SOURCE; i++)
+    {
+        if (irq_desc[i].handler != rt_hw_interrupt_dummy_handler)
+        {
+            rt_kprintf("[%d] %s: %d\n", i, irq_desc[i].name, irq_desc[i].counter);
+        }
+    }
+
+    return 0;
+}
+MSH_CMD_EXPORT(list_interrupt, list registered interrupts);
+#endif
+
 #endif
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_systick.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_systick.c
index 0060ec37a9..f6b0f68ffb 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_systick.c
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_systick.c
@@ -49,13 +49,13 @@ void rt_hw_systick_init(void)
     ETIMER_Start(USE_TIMER);
 } /* rt_hw_systick_init */
 
-void nu_systick_udelay(uint32_t delay_us)
+void rt_hw_us_delay(rt_uint32_t us)
 {
     rt_uint32_t ticks;
     rt_uint32_t told, tnow, tcnt = 0;
     rt_uint32_t cmp = ETIMER_GetCompareData(USE_TIMER);
 
-    ticks = delay_us * cmp / (1000000 / RT_TICK_PER_SECOND);
+    ticks = us * cmp / (1000000 / RT_TICK_PER_SECOND);
     told = ETIMER_GetCounter(USE_TIMER);
     while (1)
     {
@@ -82,5 +82,4 @@ void nu_systick_udelay(uint32_t delay_us)
             }
         }
     }
-
-} /* nu_systick_udelay */
+} /* rt_hw_us_delay */
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_uart.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_uart.c
index c4b7f3a393..fbafecee55 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_uart.c
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_uart.c
@@ -16,7 +16,7 @@
 
 #include 
 #include 
-#include 
+#include "NuMicro.h"
 #include 
 #include 
 
@@ -25,6 +25,7 @@
 #endif
 
 /* Private define ---------------------------------------------------------------*/
+
 enum
 {
     UART_START = -1,
@@ -70,6 +71,7 @@ struct nu_uart
     IRQn_Type irqn;
     E_SYS_IPRST rstidx;
     E_SYS_IPCLK clkidx;
+
 #if defined(RT_SERIAL_USING_DMA)
     uint32_t dma_flag;
     int16_t pdma_perp_tx;
@@ -81,7 +83,6 @@ struct nu_uart
     int32_t rxdma_trigger_len;
 
     nu_pdma_desc_t pdma_rx_desc;
-
 #endif
 
 };
@@ -395,6 +396,34 @@ static void nu_uart_isr(int vector, void *param)
     uart_base->FIFOSTS = u32FIFOSts;
 }
 
+/**
+ * Set RS-485 AUD mode
+ */
+void nu_uart_set_rs485aud(struct rt_serial_device *serial, rt_bool_t bRTSActiveLowLevel)
+{
+    UART_T *uart_base;
+    RT_ASSERT(serial != RT_NULL);
+
+    /* Get base address of uart register */
+    uart_base = ((nu_uart_t)serial)->uart_base;
+
+    /* Set RTS as RS-485 phy direction controlling ping. */
+    UART_SelectRS485Mode(uart_base, UART_ALTCTL_RS485AUD_Msk, 0);
+
+    if (bRTSActiveLowLevel)
+    {
+        /* Set direction pin as active-low. */
+        uart_base->MODEM |= UART_MODEM_RTSACTLV_Msk;
+    }
+    else
+    {
+        /* Set direction pin as active-high. */
+        uart_base->MODEM &= ~UART_MODEM_RTSACTLV_Msk;
+    }
+
+    rt_kprintf("Set %s to RS-485 AUD function mode. ActiveLowLevel-%s\n", ((nu_uart_t)serial)->name, bRTSActiveLowLevel ? "YES" : "NO");
+}
+
 /**
  * Configure uart port
  */
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_uart.h b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_uart.h
index 2596c9be0a..cda8e7fb85 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_uart.h
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_uart.h
@@ -16,5 +16,6 @@
 #include 
 
 rt_err_t rt_hw_uart_init(void);
+void nu_uart_set_rs485aud(struct rt_serial_device *serial, rt_bool_t bRTSActiveLowLevel);
 
 #endif /* __DRV_UART_H__ */
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_usbd.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_usbd.c
index 2065ba35a1..ae563d1a1e 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_usbd.c
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_usbd.c
@@ -829,7 +829,7 @@ static rt_err_t _init(rt_device_t device)
 
     nu_sys_ip_reset(nu_usbd.rstidx);
 
-    nu_systick_udelay(1000);
+    rt_hw_us_delay(1000);
 
     /* USBD Open */
     USBD_ENABLE_USB();
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_usbhost.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_usbhost.c
index 0fbb6d24c8..cd6f837c88 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_usbhost.c
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_usbhost.c
@@ -15,7 +15,7 @@
 
 #include 
 #include 
-#include 
+#include "NuMicro.h"
 
 #include "usb.h"
 #include "usbh_lib.h"
diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_wdt.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_wdt.c
index 5564c5885d..d5b696c59f 100644
--- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_wdt.c
+++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_wdt.c
@@ -16,7 +16,7 @@
 #include 
 #include 
 #include 
-#include 
+#include "NuMicro.h"
 #include 
 
 /* Private define ---------------------------------------------------------------*/
diff --git a/bsp/nuvoton/nk-980iot/board/board.h b/bsp/nuvoton/nk-980iot/board/board.h
index 38762245cd..d361487629 100644
--- a/bsp/nuvoton/nk-980iot/board/board.h
+++ b/bsp/nuvoton/nk-980iot/board/board.h
@@ -13,7 +13,7 @@
 #ifndef __BOARD_H__
 #define __BOARD_H__
 
-#include 
+#include "NuMicro.h"
 #include "drv_sys.h"
 
 #if defined(__CC_ARM)
diff --git a/bsp/nuvoton/nk-rtu980/.config b/bsp/nuvoton/nk-rtu980/.config
new file mode 100644
index 0000000000..01cafd396d
--- /dev/null
+++ b/bsp/nuvoton/nk-rtu980/.config
@@ -0,0 +1,828 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=16
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=2048
+# CONFIG_RT_USING_TIMER_SOFT is not set
+CONFIG_RT_DEBUG=y
+CONFIG_RT_DEBUG_COLOR=y
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+CONFIG_RT_USING_SIGNALS=y
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_MEMHEAP=y
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+CONFIG_RT_USING_MEMTRACE=y
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=256
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+CONFIG_RT_VER_NUM=0x40003
+CONFIG_ARCH_ARM=y
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_ARM_ARM9=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+# CONFIG_FINSH_USING_MSH_ONLY is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=16
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=16
+CONFIG_DFS_FD_MAX=64
+CONFIG_RT_USING_DFS_MNTTABLE=y
+CONFIG_RT_USING_DFS_ELMFAT=y
+
+#
+# elm-chan's FatFs, Generic FAT Filesystem Module
+#
+CONFIG_RT_DFS_ELM_CODE_PAGE=437
+CONFIG_RT_DFS_ELM_WORD_ACCESS=y
+# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
+CONFIG_RT_DFS_ELM_USE_LFN_3=y
+CONFIG_RT_DFS_ELM_USE_LFN=3
+CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
+CONFIG_RT_DFS_ELM_LFN_UNICODE=0
+CONFIG_RT_DFS_ELM_MAX_LFN=255
+CONFIG_RT_DFS_ELM_DRIVES=8
+CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096
+# CONFIG_RT_DFS_ELM_USE_ERASE is not set
+CONFIG_RT_DFS_ELM_REENTRANT=y
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_UFFS is not set
+# CONFIG_RT_USING_DFS_JFFS2 is not set
+# CONFIG_RT_USING_DFS_NFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=2048
+CONFIG_RT_USING_CAN=y
+CONFIG_RT_CAN_USING_HDR=y
+CONFIG_RT_USING_HWTIMER=y
+CONFIG_RT_USING_CPUTIME=y
+CONFIG_RT_USING_I2C=y
+# CONFIG_RT_I2C_DEBUG is not set
+CONFIG_RT_USING_I2C_BITOPS=y
+# CONFIG_RT_I2C_BITOPS_DEBUG is not set
+# CONFIG_RT_USING_PHY is not set
+CONFIG_RT_USING_PIN=y
+CONFIG_RT_USING_ADC=y
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+CONFIG_RT_USING_SPI=y
+CONFIG_RT_USING_QSPI=y
+# CONFIG_RT_USING_SPI_MSD is not set
+CONFIG_RT_USING_SFUD=y
+CONFIG_RT_SFUD_USING_SFDP=y
+CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y
+CONFIG_RT_SFUD_USING_QSPI=y
+CONFIG_RT_SFUD_SPI_MAX_HZ=50000000
+CONFIG_RT_DEBUG_SFUD=y
+# CONFIG_RT_USING_ENC28J60 is not set
+# CONFIG_RT_USING_SPI_WIFI is not set
+CONFIG_RT_USING_WDT=y
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+CONFIG_RT_USING_HWCRYPTO=y
+CONFIG_RT_HWCRYPTO_DEFAULT_NAME="hwcryto"
+CONFIG_RT_HWCRYPTO_IV_MAX_SIZE=16
+CONFIG_RT_HWCRYPTO_KEYBIT_MAX_SIZE=256
+# CONFIG_RT_HWCRYPTO_USING_GCM is not set
+CONFIG_RT_HWCRYPTO_USING_AES=y
+CONFIG_RT_HWCRYPTO_USING_AES_ECB=y
+CONFIG_RT_HWCRYPTO_USING_AES_CBC=y
+CONFIG_RT_HWCRYPTO_USING_AES_CFB=y
+CONFIG_RT_HWCRYPTO_USING_AES_CTR=y
+CONFIG_RT_HWCRYPTO_USING_AES_OFB=y
+# CONFIG_RT_HWCRYPTO_USING_DES is not set
+# CONFIG_RT_HWCRYPTO_USING_3DES is not set
+# CONFIG_RT_HWCRYPTO_USING_RC4 is not set
+# CONFIG_RT_HWCRYPTO_USING_MD5 is not set
+CONFIG_RT_HWCRYPTO_USING_SHA1=y
+CONFIG_RT_HWCRYPTO_USING_SHA2=y
+CONFIG_RT_HWCRYPTO_USING_SHA2_224=y
+CONFIG_RT_HWCRYPTO_USING_SHA2_256=y
+CONFIG_RT_HWCRYPTO_USING_SHA2_384=y
+CONFIG_RT_HWCRYPTO_USING_SHA2_512=y
+CONFIG_RT_HWCRYPTO_USING_RNG=y
+# CONFIG_RT_HWCRYPTO_USING_CRC is not set
+# CONFIG_RT_HWCRYPTO_USING_BIGNUM is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+CONFIG_RT_USING_USB_HOST=y
+CONFIG_RT_USBH_MSTORAGE=y
+CONFIG_UDISK_MOUNTPOINT="/mnt/udisk"
+CONFIG_RT_USING_USB_DEVICE=y
+CONFIG_RT_USBD_THREAD_STACK_SZ=4096
+CONFIG_USB_VENDOR_ID=0x0FFE
+CONFIG_USB_PRODUCT_ID=0x0001
+CONFIG_RT_USB_DEVICE_COMPOSITE=y
+CONFIG_RT_USB_DEVICE_CDC=y
+CONFIG_RT_USB_DEVICE_NONE=y
+CONFIG_RT_USB_DEVICE_MSTORAGE=y
+# CONFIG_RT_USB_DEVICE_HID is not set
+# CONFIG_RT_USB_DEVICE_RNDIS is not set
+# CONFIG_RT_USB_DEVICE_ECM is not set
+# CONFIG_RT_USB_DEVICE_WINUSB is not set
+# CONFIG_RT_USB_DEVICE_AUDIO is not set
+CONFIG_RT_VCOM_TASK_STK_SIZE=2048
+CONFIG_RT_CDC_RX_BUFSIZE=128
+# CONFIG_RT_VCOM_TX_USE_DMA is not set
+CONFIG_RT_VCOM_SERNO="32021919830108"
+CONFIG_RT_VCOM_SER_LEN=14
+CONFIG_RT_VCOM_TX_TIMEOUT=1000
+CONFIG_RT_USB_MSTORAGE_DISK_NAME="ramdisk1"
+
+#
+# POSIX layer and C standard library
+#
+CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_PTHREADS is not set
+CONFIG_RT_USING_POSIX=y
+# CONFIG_RT_USING_POSIX_MMAP is not set
+# CONFIG_RT_USING_POSIX_TERMIOS is not set
+# CONFIG_RT_USING_POSIX_GETLINE is not set
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+CONFIG_RT_USING_SAL=y
+CONFIG_SAL_INTERNET_CHECK=y
+
+#
+# protocol stack implement
+#
+CONFIG_SAL_USING_LWIP=y
+CONFIG_SAL_USING_POSIX=y
+
+#
+# Network interface device
+#
+CONFIG_RT_USING_NETDEV=y
+CONFIG_NETDEV_USING_IFCONFIG=y
+CONFIG_NETDEV_USING_PING=y
+CONFIG_NETDEV_USING_NETSTAT=y
+CONFIG_NETDEV_USING_AUTO_DEFAULT=y
+# CONFIG_NETDEV_USING_IPV6 is not set
+CONFIG_NETDEV_IPV4=1
+CONFIG_NETDEV_IPV6=0
+# CONFIG_NETDEV_IPV6_SCOPES is not set
+
+#
+# light weight TCP/IP stack
+#
+CONFIG_RT_USING_LWIP=y
+# CONFIG_RT_USING_LWIP141 is not set
+CONFIG_RT_USING_LWIP202=y
+# CONFIG_RT_USING_LWIP212 is not set
+# CONFIG_RT_USING_LWIP_IPV6 is not set
+CONFIG_RT_LWIP_MEM_ALIGNMENT=4
+CONFIG_RT_LWIP_IGMP=y
+CONFIG_RT_LWIP_ICMP=y
+# CONFIG_RT_LWIP_SNMP is not set
+CONFIG_RT_LWIP_DNS=y
+CONFIG_RT_LWIP_DHCP=y
+CONFIG_IP_SOF_BROADCAST=1
+CONFIG_IP_SOF_BROADCAST_RECV=1
+
+#
+# Static IPv4 Address
+#
+CONFIG_RT_LWIP_IPADDR="192.168.1.30"
+CONFIG_RT_LWIP_GWADDR="192.168.1.1"
+CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
+CONFIG_RT_LWIP_UDP=y
+CONFIG_RT_LWIP_TCP=y
+CONFIG_RT_LWIP_RAW=y
+# CONFIG_RT_LWIP_PPP is not set
+CONFIG_RT_MEMP_NUM_NETCONN=32
+CONFIG_RT_LWIP_PBUF_NUM=256
+CONFIG_RT_LWIP_RAW_PCB_NUM=32
+CONFIG_RT_LWIP_UDP_PCB_NUM=32
+CONFIG_RT_LWIP_TCP_PCB_NUM=32
+CONFIG_RT_LWIP_TCP_SEG_NUM=256
+CONFIG_RT_LWIP_TCP_SND_BUF=32768
+CONFIG_RT_LWIP_TCP_WND=10240
+CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10
+CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=32
+CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=4096
+# CONFIG_LWIP_NO_RX_THREAD is not set
+# CONFIG_LWIP_NO_TX_THREAD is not set
+CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
+CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024
+CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=32
+# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
+CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
+CONFIG_LWIP_NETIF_LINK_CALLBACK=1
+CONFIG_SO_REUSE=1
+CONFIG_LWIP_SO_RCVTIMEO=1
+CONFIG_LWIP_SO_SNDTIMEO=1
+CONFIG_LWIP_SO_RCVBUF=1
+CONFIG_LWIP_SO_LINGER=0
+CONFIG_RT_LWIP_NETIF_LOOPBACK=y
+CONFIG_LWIP_NETIF_LOOPBACK=1
+CONFIG_RT_LWIP_STATS=y
+# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set
+CONFIG_RT_LWIP_USING_PING=y
+# CONFIG_RT_LWIP_DEBUG is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+# CONFIG_LWIP_USING_DHCPD is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+CONFIG_RT_USING_UTEST=y
+CONFIG_UTEST_THR_STACK_SIZE=4096
+CONFIG_UTEST_THR_PRIORITY=20
+# CONFIG_RT_USING_LWP is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+CONFIG_PKG_USING_NETUTILS=y
+CONFIG_PKG_NETUTILS_PATH="/packages/iot/netutils"
+CONFIG_PKG_NETUTILS_TFTP=y
+CONFIG_PKG_NETUTILS_IPERF=y
+# CONFIG_PKG_NETUTILS_NETIO is not set
+CONFIG_PKG_NETUTILS_NTP=y
+CONFIG_NETUTILS_NTP_TIMEZONE=8
+CONFIG_NETUTILS_NTP_HOSTNAME="0.tw.pool.ntp.org"
+CONFIG_NETUTILS_NTP_HOSTNAME2="1.tw.pool.ntp.org"
+CONFIG_NETUTILS_NTP_HOSTNAME3="2.tw.pool.ntp.org"
+# CONFIG_PKG_NETUTILS_TELNET is not set
+# CONFIG_PKG_NETUTILS_TCPDUMP is not set
+CONFIG_PKG_USING_NETUTILS_V120=y
+# CONFIG_PKG_USING_NETUTILS_V110 is not set
+# CONFIG_PKG_USING_NETUTILS_V100 is not set
+# CONFIG_PKG_USING_NETUTILS_LATEST_VERSION is not set
+CONFIG_PKG_NETUTILS_VER="v1.2.0"
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_PERSIMMON is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+CONFIG_PKG_USING_FAL=y
+CONFIG_PKG_FAL_PATH="/packages/system/fal"
+CONFIG_FAL_DEBUG_CONFIG=y
+CONFIG_FAL_DEBUG=1
+CONFIG_FAL_PART_HAS_TABLE_CFG=y
+CONFIG_FAL_USING_SFUD_PORT=y
+CONFIG_FAL_USING_NOR_FLASH_DEV_NAME="norflash0"
+# CONFIG_PKG_USING_FAL_V00500 is not set
+# CONFIG_PKG_USING_FAL_V00400 is not set
+# CONFIG_PKG_USING_FAL_V00300 is not set
+# CONFIG_PKG_USING_FAL_V00200 is not set
+# CONFIG_PKG_USING_FAL_V00100 is not set
+CONFIG_PKG_USING_FAL_LATEST_VERSION=y
+CONFIG_PKG_FAL_VER="latest"
+CONFIG_PKG_FAL_VER_NUM=0x99999
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+CONFIG_PKG_USING_RAMDISK=y
+CONFIG_PKG_RAMDISK_PATH="/packages/system/ramdisk"
+# CONFIG_PKG_USING_RAMDISK_V010 is not set
+CONFIG_PKG_USING_RAMDISK_LATEST_VERSION=y
+CONFIG_PKG_RAMDISK_VER="latest"
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RT_PRINTF is not set
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+CONFIG_PKG_USING_OPTPARSE=y
+CONFIG_PKG_OPTPARSE_PATH="/packages/misc/optparse"
+CONFIG_PKG_USING_OPTPARSE_V100=y
+# CONFIG_PKG_USING_OPTPARSE_LATEST_VERSION is not set
+CONFIG_PKG_OPTPARSE_VER="v1.0.0"
+# CONFIG_OPTPARSE_USING_DEMO is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+CONFIG_PKG_USING_VI=y
+CONFIG_PKG_VI_PATH="/packages/misc/vi"
+CONFIG_VI_MAX_LEN=4096
+# CONFIG_VI_ENABLE_8BIT is not set
+CONFIG_VI_ENABLE_COLON=y
+CONFIG_VI_ENABLE_YANKMARK=y
+CONFIG_VI_ENABLE_SEARCH=y
+CONFIG_VI_ENABLE_DOT_CMD=y
+CONFIG_VI_ENABLE_READONLY=y
+CONFIG_VI_ENABLE_SETOPTS=y
+CONFIG_VI_ENABLE_SET=y
+CONFIG_VI_ENABLE_VI_ASK_TERMINAL=y
+CONFIG_VI_ENABLE_UNDO=y
+CONFIG_VI_ENABLE_UNDO_QUEUE=y
+CONFIG_VI_UNDO_QUEUE_MAX=256
+CONFIG_PKG_USING_VI_LATEST_VERSION=y
+CONFIG_PKG_VI_VER="latest"
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+
+#
+# games: games run on RT-Thread console
+#
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+
+#
+# Nuvoton Packages Config
+#
+CONFIG_NU_PKG_USING_UTILS=y
+CONFIG_NU_PKG_USING_DEMO=y
+# CONFIG_NU_PKG_USING_BMX055 is not set
+# CONFIG_NU_PKG_USING_MAX31875 is not set
+# CONFIG_NU_PKG_USING_NAU88L25 is not set
+# CONFIG_NU_PKG_USING_NAU8822 is not set
+# CONFIG_NU_PKG_USING_ILI9341 is not set
+# CONFIG_NU_PKG_USING_SPINAND is not set
+
+#
+# Hardware Drivers Config
+#
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_SOC_SERIES_NUC980=y
+CONFIG_BSP_USE_STDDRIVER_SOURCE=y
+CONFIG_BSP_USING_MMU=y
+CONFIG_BSP_USING_PDMA=y
+CONFIG_NU_PDMA_MEMFUN_ACTOR_MAX=2
+CONFIG_BSP_USING_GPIO=y
+CONFIG_BSP_USING_EMAC=y
+# CONFIG_BSP_USING_EMAC0 is not set
+CONFIG_BSP_USING_EMAC1=y
+CONFIG_NU_EMAC_PDMA_MEMCOPY=y
+CONFIG_NU_EMAC_PDMA_MEMCOPY_THRESHOLD=128
+# CONFIG_BSP_USING_RTC is not set
+CONFIG_BSP_USING_ADC=y
+CONFIG_BSP_USING_TMR=y
+CONFIG_BSP_USING_TIMER=y
+CONFIG_BSP_USING_TMR0=y
+CONFIG_BSP_USING_TIMER0=y
+# CONFIG_BSP_USING_TIMER0_CAPTURE is not set
+CONFIG_BSP_USING_TMR1=y
+CONFIG_BSP_USING_TIMER1=y
+# CONFIG_BSP_USING_TIMER1_CAPTURE is not set
+CONFIG_BSP_USING_TMR2=y
+CONFIG_BSP_USING_TIMER2=y
+# CONFIG_BSP_USING_TIMER2_CAPTURE is not set
+CONFIG_BSP_USING_TMR3=y
+CONFIG_BSP_USING_TIMER3=y
+# CONFIG_BSP_USING_TIMER3_CAPTURE is not set
+CONFIG_BSP_USING_TMR4=y
+CONFIG_BSP_USING_TIMER4=y
+# CONFIG_BSP_USING_TIMER4_CAPTURE is not set
+CONFIG_BSP_USING_UART=y
+CONFIG_BSP_USING_UART0=y
+# CONFIG_BSP_USING_UART0_TX_DMA is not set
+# CONFIG_BSP_USING_UART0_RX_DMA is not set
+# CONFIG_BSP_USING_UART1 is not set
+# CONFIG_BSP_USING_UART2 is not set
+# CONFIG_BSP_USING_UART3 is not set
+CONFIG_BSP_USING_UART4=y
+CONFIG_BSP_USING_UART4_TX_DMA=y
+CONFIG_BSP_USING_UART4_RX_DMA=y
+# CONFIG_BSP_USING_UART5 is not set
+# CONFIG_BSP_USING_UART6 is not set
+# CONFIG_BSP_USING_UART7 is not set
+CONFIG_BSP_USING_UART8=y
+CONFIG_BSP_USING_UART8_TX_DMA=y
+CONFIG_BSP_USING_UART8_RX_DMA=y
+# CONFIG_BSP_USING_UART9 is not set
+CONFIG_BSP_USING_I2C=y
+# CONFIG_BSP_USING_I2C0 is not set
+CONFIG_BSP_USING_I2C1=y
+# CONFIG_BSP_USING_I2C2 is not set
+# CONFIG_BSP_USING_I2C3 is not set
+# CONFIG_BSP_USING_SDH is not set
+CONFIG_BSP_USING_CAN=y
+# CONFIG_BSP_USING_CAN0 is not set
+# CONFIG_BSP_USING_CAN1 is not set
+# CONFIG_BSP_USING_CAN2 is not set
+CONFIG_BSP_USING_CAN3=y
+# CONFIG_BSP_USING_PWM is not set
+CONFIG_BSP_USING_SPI=y
+CONFIG_BSP_USING_SPI_PDMA=y
+# CONFIG_BSP_USING_SPI0_NONE is not set
+CONFIG_BSP_USING_SPI0=y
+CONFIG_BSP_USING_SPI0_PDMA=y
+CONFIG_BSP_USING_SPI1_NONE=y
+# CONFIG_BSP_USING_SPI1 is not set
+# CONFIG_BSP_USING_I2S is not set
+CONFIG_BSP_USING_QSPI=y
+CONFIG_BSP_USING_QSPI0=y
+CONFIG_BSP_USING_QSPI0_PDMA=y
+# CONFIG_BSP_USING_SCUART is not set
+CONFIG_BSP_USING_CRYPTO=y
+# CONFIG_NU_PRNG_USE_SEED is not set
+# CONFIG_BSP_USING_SOFT_I2C is not set
+CONFIG_BSP_USING_WDT=y
+# CONFIG_BSP_USING_EBI is not set
+CONFIG_BSP_USING_USBD=y
+CONFIG_BSP_USING_USBH=y
+
+#
+# On-board Peripheral Drivers
+#
+CONFIG_BSP_USING_CONSOLE=y
+CONFIG_BOARD_USING_UART8_RS485=y
+CONFIG_BOARD_USING_STORAGE_SPIFLASH=y
+CONFIG_BOARD_USING_USB0_DEVICE_HOST=y
+
+#
+# Board extended module drivers
+#
+CONFIG_BOARD_USING_IP101GR=y
+CONFIG_BOARD_USE_UTEST=y
+CONFIG_UTEST_CMD_PREFIX="bsp.nuvoton.nk-rtu980.test.utest."
diff --git a/bsp/nuvoton/nk-rtu980/Kconfig b/bsp/nuvoton/nk-rtu980/Kconfig
new file mode 100644
index 0000000000..5c55e87c61
--- /dev/null
+++ b/bsp/nuvoton/nk-rtu980/Kconfig
@@ -0,0 +1,29 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+    
+# you can change the RTT_ROOT default "../../.." to your rtthread_root,
+# example : default "F:/git_repositories/rt-thread"
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+config NU_PKGS_DIR
+    string
+    option env="NU_PKGS_ROOT"
+    default "../libraries/nu_packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "$NU_PKGS_DIR/Kconfig"
+source "$BSP_DIR/board/Kconfig"
diff --git a/bsp/nuvoton/nk-rtu980/README.md b/bsp/nuvoton/nk-rtu980/README.md
new file mode 100644
index 0000000000..20294482ea
--- /dev/null
+++ b/bsp/nuvoton/nk-rtu980/README.md
@@ -0,0 +1,106 @@
+# NK-RTU980
+## 1. Introduction
+NuMaker-RTU-NUC980, also known as Chili, is a Nuvoton’s development platform that uses NUC980DR61YC microprocessor with a 64-pin package on a 50 mm x 50 mm dimension PCB. Chili board provides a high-end hardware features including a NUC980DR61YC ARM926EJ-S processor with 64 MB DRAM, 32MB SPI NOR Flash, 10/100 Ethernet MAC interface, USB 2.0 High Speed host/device connector, CAN bus, RS-485 and five GPIOs. Crypto engine supports RSA2048, AES256, ECC, SHA512 algorithm and a Pseudo Random Number Generator for communication security protection.
+
+
+[![NK-RTU980](https://i.imgur.com/gCKG4PN.png "NK-RTU980")](https://i.imgur.com/gCKG4PN.png "NK-RTU980")
+
+
+### 1.1 MCU specification
+
+|  | Features |
+| -- | -- |
+| Part NO. | NUC980DR61YC |
+| CPU ARCH. | 32-bit ARM926EJ-STM |
+| Operation frequency | 300 MHz |
+| Embedded SDRAM size | Built-in 64MB |
+| Crypto engine |  AES, RSA, ECC, HMAC and SHA crypto accelerator |
+| RMII interface |  10/100 Mbps x1 |
+| USB 2.0 |  High Speed Host x1, High Speed Host/Device x1 |
+| Extern storage |  32 MB SPI-NOR Flash |
+
+### 1.2 Interface
+
+| Interface |
+| -- |
+| Arduino UNO |
+| A RJ45 Ethernet |
+| An USB 2.0 HS port |
+| An USB 2.0 HS OTG port |
+| A RS-485 |
+| A CAN bus |
+| An ICE connector |
+
+### 1.3 On-board devices
+
+| Device | Description | Driver supporting status |
+| -- | -- | -- |
+|Ethernet PHY | IP101GR | Supported |
+|Button |  | Supported |
+|LEDs |  | Supported |
+|USB Device | VCOM + MStorage | Supported |
+|USB Host | MStorage | Supported |
+|SPI NOR flash | W25Q256F | Supported |
+|VCOM | For console | Ready.(Need to install VCOM driver) |
+
+## 2. Supported compiler
+Support GCC, MDK4 and MDK5 IDE/compilers. More information of these compiler version as following:
+
+| IDE/Compiler  | Tested version            |
+| ---------- | ---------------------------- |
+| MDK4       | 4.76                         |
+| MDK5       | 5.26.2                       |
+| GCC        | GCC 5.4.1 20160919 (release) |
+
+Notice: Please install ICE driver for development.
+
+## 3. Program firmware
+### 3.1 SDRAM Downloading using NuWriter
+You can use NuWriter to download rtthread.bin into SDRAM, then run it.
+[![SDRAM Downloading using NuWriter](https://i.imgur.com/NvbzsRp.gif "SDRAM Downloading using NuWriter")](https://i.imgur.com/NvbzsRp.gif "SDRAM Downloading using NuWriter")
+

+Choose type: DDR/SRAM

+<< Press Re-Connect >>

+Choose file: Specify your rtthread.bin file.

+Execute Address: 0x0

+Option: Download and run

+<< Press Download >>

+Enjoy!! 

+

+
+### 3.2 SPI NOR flash using NuWriter
+You can use NuWriter to program rtthread.bin into SPI NOR flash.
+[![SPI NOR flash](https://i.imgur.com/8OtXGSQ.gif "SPI NOR flash")](https://i.imgur.com/8OtXGSQ.gif "SPI NOR flash using NuWriter")
+

+Choose type: SPI

+<< Press Re-Connect >>

+Choose file: Specify your rtthread.bin file.

+Image Type: Loader

+Execute Address: 0x0

+<< Press Program >>

+<< Press OK & Wait it down >>

+<< Set Power-on setting to SPI NOR booting >>

+<< Press Reset button on board >>

+Enjoy!! 

+

+
+## 4. Test
+You can use Tera Term terminate emulator (or other software) to type commands of RTT. All parameters of serial communication are shown in below image. Here, you can find out the corresponding port number of Nuvoton Virtual Com Port in window device manager.
+
+[![Serial settings](https://i.imgur.com/5NYuSNM.png "Serial settings")](https://i.imgur.com/5NYuSNM.png "Serial settings")
+
+## 5. Purchase
+* [Nuvoton Direct][1]
+
+## 6. Resources
+* [Download Board Schematics][2]
+* [Download NK-RTU980 Quick Start Guide][3]
+* [Download TRM][4]
+* [Download NuWriter][5]
+
+  [1]: https://direct.nuvoton.com/tw/numaker-rtu-nuc980
+  [2]: https://www.nuvoton.com/resource-download.jsp?tp_GUID=HL1020200508155209
+  [3]: https://www.nuvoton.com/resource-download.jsp?tp_GUID=UG1320200623183237
+  [4]: https://www.nuvoton.com/resource-download.jsp?tp_GUID=DA05-NUC980-1
+  [5]: https://github.com/OpenNuvoton/NUC980_NuWriter
+  
\ No newline at end of file
diff --git a/bsp/zynq7000/SConscript b/bsp/nuvoton/nk-rtu980/SConscript
similarity index 100%
rename from bsp/zynq7000/SConscript
rename to bsp/nuvoton/nk-rtu980/SConscript
diff --git a/bsp/nuvoton/nk-rtu980/SConstruct b/bsp/nuvoton/nk-rtu980/SConstruct
new file mode 100644
index 0000000000..4290749228
--- /dev/null
+++ b/bsp/nuvoton/nk-rtu980/SConstruct
@@ -0,0 +1,55 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+nuvoton_library = 'nuc980'
+rtconfig.BSP_LIBRARY_TYPE = nuvoton_library
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, nuvoton_library, 'SConscript')))
+
+# include nu_pkgs
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'nu_packages', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/components/libc/time/SConscript b/bsp/nuvoton/nk-rtu980/applications/SConscript
similarity index 57%
rename from components/libc/time/SConscript
rename to bsp/nuvoton/nk-rtu980/applications/SConscript
index f7e6f7e8e9..9ffdbcd0f9 100644
--- a/components/libc/time/SConscript
+++ b/bsp/nuvoton/nk-rtu980/applications/SConscript
@@ -4,9 +4,8 @@ from building import *
 
 cwd = GetCurrentDir()
 src = Glob('*.c') + Glob('*.cpp')
-CPPPATH = [cwd]
+CPPPATH = [cwd, str(Dir('#'))]
 
-group = DefineGroup('libc', src, 
-    depend = ['RT_USING_PTHREADS'], CPPPATH = CPPPATH)
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
 
 Return('group')
diff --git a/bsp/nuvoton/nk-rtu980/applications/main.c b/bsp/nuvoton/nk-rtu980/applications/main.c
new file mode 100644
index 0000000000..73992209ed
--- /dev/null
+++ b/bsp/nuvoton/nk-rtu980/applications/main.c
@@ -0,0 +1,71 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author       Notes
+* 2020-12-12      Wayne        First version
+*
+******************************************************************************/
+
+#include 
+#include 
+
+#if defined(RT_USING_PIN)
+#include 
+
+/* defined the LED_G1 pin: PC3 */
+#define LED_G1   NU_GET_PININDEX(NU_PC, 3)
+
+/* defined the LED_G2 pin: PC11 */
+#define LED_G2   NU_GET_PININDEX(NU_PC, 11)
+
+/* defined the BUTTON pin: PC15 */
+#define BUTTON   NU_GET_PININDEX(NU_PC, 15)
+
+static uint32_t u32Button = BUTTON;
+
+void nu_button_cb(void *args)
+{
+    static int u32ToggleFlag = 0;
+    uint32_t u32Key = *((uint32_t *)(args));
+
+    switch (u32Key)
+    {
+    case BUTTON:
+        u32ToggleFlag = ~u32ToggleFlag;
+        rt_pin_write(LED_G1, u32ToggleFlag);
+        break;
+    }
+}
+#endif
+
+int main(int argc, char **argv)
+{
+#if defined(RT_USING_PIN)
+    int counter = 1000;
+
+    /* set LED_G1 pin mode to output */
+    rt_pin_mode(LED_G1, PIN_MODE_OUTPUT);
+
+    /* set LED_G2 pin mode to output */
+    rt_pin_mode(LED_G2, PIN_MODE_OUTPUT);
+
+    /* set BUTTON pin mode to input */
+    rt_pin_mode(BUTTON, PIN_MODE_INPUT_PULLUP);
+    rt_pin_attach_irq(BUTTON, PIN_IRQ_MODE_FALLING, nu_button_cb, &u32Button);
+    rt_pin_irq_enable(BUTTON, PIN_IRQ_ENABLE);
+
+    while (counter--)
+    {
+        rt_pin_write(LED_G2, PIN_HIGH);
+        rt_thread_mdelay(200);
+        rt_pin_write(LED_G2, PIN_LOW);
+        rt_thread_mdelay(200);
+    }
+#endif
+
+    return 0;
+}
diff --git a/bsp/nuvoton/nk-rtu980/applications/mnt.c b/bsp/nuvoton/nk-rtu980/applications/mnt.c
new file mode 100644
index 0000000000..779db2ffe8
--- /dev/null
+++ b/bsp/nuvoton/nk-rtu980/applications/mnt.c
@@ -0,0 +1,237 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author       Notes
+* 2021-3-4        Wayne        First version
+*
+******************************************************************************/
+
+#include "rtconfig.h"
+
+#include 
+
+#define LOG_TAG         "mnt"
+#define DBG_ENABLE
+#define DBG_SECTION_NAME "mnt"
+#define DBG_LEVEL DBG_ERROR
+#define DBG_COLOR
+#include 
+
+#if defined(RT_USING_DFS)
+    #include 
+    #include 
+#endif
+
+#if defined(PKG_USING_FAL)
+    #include 
+#endif
+
+#if defined(PKG_USING_RAMDISK)
+    #define RAMDISK_NAME         "ramdisk0"
+    #define RAMDISK_UDC          "ramdisk1"
+    #define MOUNT_POINT_RAMDISK0 "/"
+#endif
+
+#if defined(BOARD_USING_STORAGE_SPIFLASH)
+    #define PARTITION_NAME_FILESYSTEM "filesystem"
+    #define MOUNT_POINT_SPIFLASH0 "/mnt/"PARTITION_NAME_FILESYSTEM
+#endif
+
+#ifdef RT_USING_DFS_MNTTABLE
+
+/*
+const char   *device_name;
+const char   *path;
+const char   *filesystemtype;
+unsigned long rwflag;
+const void   *data;
+*/
+
+const struct dfs_mount_tbl mount_table[] =
+{
+    { RAMDISK_UDC, "/mnt/ram_usbd", "elm", 0, RT_NULL },
+    {0},
+};
+#endif
+
+
+#if defined(PKG_USING_RAMDISK)
+
+extern rt_err_t ramdisk_init(const char *dev_name, rt_uint8_t *disk_addr, rt_size_t block_size, rt_size_t num_block);
+int ramdisk_device_init(void)
+{
+    rt_err_t result = RT_EOK;
+
+    /* Create a 8MB RAMDISK */
+    result = ramdisk_init(RAMDISK_NAME, NULL, 512, 2 * 8192);
+    RT_ASSERT(result == RT_EOK);
+
+    /* Create a 4MB RAMDISK */
+    result = ramdisk_init(RAMDISK_UDC, NULL, 512, 2 * 4096);
+    RT_ASSERT(result == RT_EOK);
+
+    return 0;
+}
+INIT_DEVICE_EXPORT(ramdisk_device_init);
+
+/* Recursive mkdir */
+static int mkdir_p(const char *dir, const mode_t mode)
+{
+    int ret = -1;
+    char *tmp = NULL;
+    char *p = NULL;
+    struct stat sb;
+    rt_size_t len;
+
+    if (!dir)
+        goto exit_mkdir_p;
+
+    /* Copy path */
+    /* Get the string length */
+    len = strlen(dir);
+    tmp = rt_strdup(dir);
+
+    /* Remove trailing slash */
+    if (tmp[len - 1] == '/')
+    {
+        tmp[len - 1] = '\0';
+        len--;
+    }
+
+    /* check if path exists and is a directory */
+    if (stat(tmp, &sb) == 0)
+    {
+        if (S_ISDIR(sb.st_mode))
+        {
+            ret = 0;
+            goto exit_mkdir_p;
+        }
+    }
+
+    /* Recursive mkdir */
+    for (p = tmp + 1; p - tmp <= len; p++)
+    {
+        if ((*p == '/') || (p - tmp == len))
+        {
+            *p = 0;
+
+            /* Test path */
+            if (stat(tmp, &sb) != 0)
+            {
+                /* Path does not exist - create directory */
+                if (mkdir(tmp, mode) < 0)
+                {
+                    goto exit_mkdir_p;
+                }
+            }
+            else if (!S_ISDIR(sb.st_mode))
+            {
+                /* Not a directory */
+                goto exit_mkdir_p;
+            }
+            if (p - tmp != len)
+                *p = '/';
+        }
+    }
+
+    ret = 0;
+
+exit_mkdir_p:
+
+    if (tmp)
+        rt_free(tmp);
+
+    return ret;
+}
+
+/* Initialize the filesystem */
+int filesystem_init(void)
+{
+    rt_err_t result = RT_EOK;
+
+    // ramdisk as root
+    if (!rt_device_find(RAMDISK_NAME))
+    {
+        LOG_E("cannot find %s device", RAMDISK_NAME);
+        goto exit_filesystem_init;
+    }
+    else
+    {
+        /* Format these ramdisk */
+        result = (rt_err_t)dfs_mkfs("elm", RAMDISK_NAME);
+        RT_ASSERT(result == RT_EOK);
+
+        /* mount ramdisk0 as root directory */
+        if (dfs_mount(RAMDISK_NAME, "/", "elm", 0, RT_NULL) == 0)
+        {
+            LOG_I("ramdisk mounted on \"/\".");
+
+            /* now you can create dir dynamically. */
+            mkdir_p("/mnt", 0x777);
+            mkdir_p("/cache", 0x777);
+            mkdir_p("/download", 0x777);
+            mkdir_p("/mnt/ram_usbd", 0x777);
+            mkdir_p("/mnt/filesystem", 0x777);
+#if defined(RT_USBH_MSTORAGE) && defined(UDISK_MOUNTPOINT)
+            mkdir_p(UDISK_MOUNTPOINT, 0x777);
+#endif
+        }
+        else
+        {
+            LOG_E("root folder creation failed!\n");
+            goto exit_filesystem_init;
+        }
+    }
+
+    if (!rt_device_find(RAMDISK_UDC))
+    {
+        LOG_E("cannot find %s device", RAMDISK_UDC);
+        goto exit_filesystem_init;
+    }
+    else
+    {
+        /* Format these ramdisk */
+        result = (rt_err_t)dfs_mkfs("elm", RAMDISK_UDC);
+        RT_ASSERT(result == RT_EOK);
+    }
+
+exit_filesystem_init:
+
+    return -result;
+}
+INIT_ENV_EXPORT(filesystem_init);
+#endif
+
+#if defined(BOARD_USING_STORAGE_SPIFLASH)
+int mnt_init_spiflash0(void)
+{
+#if defined(PKG_USING_FAL)
+    extern int fal_init_check(void);
+    if (!fal_init_check())
+        fal_init();
+#endif
+    struct rt_device *psNorFlash = fal_blk_device_create(PARTITION_NAME_FILESYSTEM);
+    if (!psNorFlash)
+    {
+        rt_kprintf("Failed to create block device for %s.\n", PARTITION_NAME_FILESYSTEM);
+        goto exit_mnt_init_spiflash0;
+    }
+    else if (dfs_mount(psNorFlash->parent.name, MOUNT_POINT_SPIFLASH0, "elm", 0, 0) != 0)
+    {
+        rt_kprintf("Failed to mount elm on %s.\n", MOUNT_POINT_SPIFLASH0);
+        rt_kprintf("Try to execute 'mkfs -t elm %s' first, then reboot.\n", PARTITION_NAME_FILESYSTEM);
+        goto exit_mnt_init_spiflash0;
+    }
+    rt_kprintf("mount %s with elmfat type: ok\n", PARTITION_NAME_FILESYSTEM);
+
+exit_mnt_init_spiflash0:
+
+    return 0;
+}
+INIT_ENV_EXPORT(mnt_init_spiflash0);
+#endif
+
diff --git a/bsp/nuvoton/nk-rtu980/board/Kconfig b/bsp/nuvoton/nk-rtu980/board/Kconfig
new file mode 100644
index 0000000000..2682f8b89f
--- /dev/null
+++ b/bsp/nuvoton/nk-rtu980/board/Kconfig
@@ -0,0 +1,48 @@
+menu "Hardware Drivers Config"
+
+    menu "On-chip Peripheral Drivers"
+        source "$BSP_DIR/../libraries/nuc980/rtt_port/Kconfig"
+    endmenu
+
+    menu "On-board Peripheral Drivers"
+
+        config BSP_USING_CONSOLE
+            bool "Enable UART0 for RTT Console(uart0)"
+            select BSP_USING_UART
+            select BSP_USING_UART0
+            default y
+
+        config BOARD_USING_UART8_RS485
+            bool "Enable UART8 for RS485(AUD) communication(uart8)"
+            select BSP_USING_UART
+            select BSP_USING_UART8
+            default y
+
+        config BOARD_USING_STORAGE_SPIFLASH
+            bool "SPI NOR FLASH supporting(over qspi0)"
+            select BSP_USING_QSPI
+            select BSP_USING_QSPI0
+            default y
+
+        config BOARD_USING_USB0_DEVICE_HOST
+            select BSP_USING_USBH
+            select BSP_USING_USBD
+            bool "Enable USB0 Device/Host"
+            help
+                Choose this option if you need USB device or host function mode.
+                    If you need USB host, please remember short to ground on JP1 jumper.
+
+    endmenu
+
+    menu "Board extended module drivers"
+
+        config BOARD_USING_IP101GR
+            bool "Enable ethernet phy supporting(over emac/mdio)"
+            select BSP_USING_EMAC
+            select BSP_USING_EMAC1
+            default n
+
+    endmenu
+
+
+endmenu
diff --git a/bsp/nuvoton/nk-rtu980/board/SConscript b/bsp/nuvoton/nk-rtu980/board/SConscript
new file mode 100644
index 0000000000..3f8e1c167f
--- /dev/null
+++ b/bsp/nuvoton/nk-rtu980/board/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [ cwd ]
+
+group = DefineGroup('board', src, depend = [''], CPPPATH = CPPPATH)
+Return('group')
diff --git a/bsp/nuvoton/nk-rtu980/board/board.h b/bsp/nuvoton/nk-rtu980/board/board.h
new file mode 100644
index 0000000000..d361487629
--- /dev/null
+++ b/bsp/nuvoton/nk-rtu980/board/board.h
@@ -0,0 +1,43 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author       Notes
+* 2020-1-16       Wayne        First version
+*
+******************************************************************************/
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include "NuMicro.h"
+#include "drv_sys.h"
+
+#if defined(__CC_ARM)
+    extern int Image$$RW_RAM1$$ZI$$Limit;
+    #define BOARD_HEAP_START    (void*)&Image$$RW_RAM1$$ZI$$Limit
+#else
+    extern int __bss_end;
+    #define BOARD_HEAP_START    ((void *)&__bss_end)
+#endif
+
+#define BOARD_SDRAM_START   0x0
+#define BOARD_SDRAM_SIZE    0x04000000
+#define BOARD_HEAP_END      ((void*)BOARD_SDRAM_SIZE)
+
+#if defined(RT_USING_MTD_NAND)
+    #include 
+    #define MTD_SPINAND_PARTITION_NUM 3
+    extern struct rt_mtd_nand_device mtd_partitions[MTD_SPINAND_PARTITION_NUM];
+#endif
+
+extern void rt_hw_board_init(void);
+extern void nu_clock_init(void);
+extern void nu_clock_deinit(void);
+extern void nu_pin_init(void);
+extern void nu_pin_deinit(void);
+
+#endif /* BOARD_H_ */
diff --git a/bsp/nuvoton/nk-rtu980/board/board_dev.c b/bsp/nuvoton/nk-rtu980/board/board_dev.c
new file mode 100644
index 0000000000..0086fe4595
--- /dev/null
+++ b/bsp/nuvoton/nk-rtu980/board/board_dev.c
@@ -0,0 +1,236 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author       Notes
+* 2020-12-12      Wayne        First version
+*
+******************************************************************************/
+
+#include 
+#include 
+
+#if defined(BOARD_USING_STORAGE_SPIFLASH)
+#if defined(RT_USING_SFUD)
+    #include "spi_flash.h"
+    #include "spi_flash_sfud.h"
+#endif
+
+#include "drv_qspi.h"
+
+#define W25X_REG_READSTATUS    (0x05)
+#define W25X_REG_READSTATUS2   (0x35)
+#define W25X_REG_WRITEENABLE   (0x06)
+#define W25X_REG_WRITESTATUS   (0x01)
+#define W25X_REG_QUADENABLE    (0x02)
+
+static rt_uint8_t SpiFlash_ReadStatusReg(struct rt_qspi_device *qspi_device)
+{
+    rt_uint8_t u8Val;
+    rt_err_t result = RT_EOK;
+    rt_uint8_t w25x_txCMD1 = W25X_REG_READSTATUS;
+
+    result = rt_qspi_send_then_recv(qspi_device, &w25x_txCMD1, 1, &u8Val, 1);
+    RT_ASSERT(result > 0);
+
+    return u8Val;
+}
+
+static rt_uint8_t SpiFlash_ReadStatusReg2(struct rt_qspi_device *qspi_device)
+{
+    rt_uint8_t u8Val;
+    rt_err_t result = RT_EOK;
+    rt_uint8_t w25x_txCMD1 = W25X_REG_READSTATUS2;
+
+    result = rt_qspi_send_then_recv(qspi_device, &w25x_txCMD1, 1, &u8Val, 1);
+    RT_ASSERT(result > 0);
+
+    return u8Val;
+}
+
+static rt_err_t SpiFlash_WriteStatusReg(struct rt_qspi_device *qspi_device, uint8_t u8Value1, uint8_t u8Value2)
+{
+    rt_uint8_t w25x_txCMD1;
+    rt_uint8_t au8Val[2];
+    rt_err_t result;
+    struct rt_qspi_message qspi_message = {0};
+
+    /* Enable WE */
+    w25x_txCMD1 = W25X_REG_WRITEENABLE;
+    result = rt_qspi_send(qspi_device, &w25x_txCMD1, sizeof(w25x_txCMD1));
+    if (result != sizeof(w25x_txCMD1))
+        goto exit_SpiFlash_WriteStatusReg;
+
+    /* Prepare status-1, 2 data */
+    au8Val[0] = u8Value1;
+    au8Val[1] = u8Value2;
+
+    /* 1-bit mode: Instruction+payload */
+    qspi_message.instruction.content = W25X_REG_WRITESTATUS;
+    qspi_message.instruction.qspi_lines = 1;
+
+    qspi_message.qspi_data_lines   = 1;
+    qspi_message.parent.cs_take    = 1;
+    qspi_message.parent.cs_release = 1;
+    qspi_message.parent.send_buf   = &au8Val[0];
+    qspi_message.parent.length     = sizeof(au8Val);
+    qspi_message.parent.next       = RT_NULL;
+
+    if (rt_qspi_transfer_message(qspi_device, &qspi_message) != sizeof(au8Val))
+    {
+        result = -RT_ERROR;
+    }
+
+    result  = RT_EOK;
+
+exit_SpiFlash_WriteStatusReg:
+
+    return result;
+}
+
+static void SpiFlash_WaitReady(struct rt_qspi_device *qspi_device)
+{
+    volatile uint8_t u8ReturnValue;
+
+    do
+    {
+        u8ReturnValue = SpiFlash_ReadStatusReg(qspi_device);
+        u8ReturnValue = u8ReturnValue & 1;
+    }
+    while (u8ReturnValue != 0);   // check the BUSY bit
+}
+
+static void SpiFlash_EnterQspiMode(struct rt_qspi_device *qspi_device)
+{
+    rt_err_t result = RT_EOK;
+
+    uint8_t u8Status1 = SpiFlash_ReadStatusReg(qspi_device);
+    uint8_t u8Status2 = SpiFlash_ReadStatusReg2(qspi_device);
+
+    u8Status2 |= W25X_REG_QUADENABLE;
+
+    result = SpiFlash_WriteStatusReg(qspi_device, u8Status1, u8Status2);
+    RT_ASSERT(result == RT_EOK);
+
+    SpiFlash_WaitReady(qspi_device);
+}
+
+static void SpiFlash_ExitQspiMode(struct rt_qspi_device *qspi_device)
+{
+    rt_err_t result = RT_EOK;
+    uint8_t u8Status1 = SpiFlash_ReadStatusReg(qspi_device);
+    uint8_t u8Status2 = SpiFlash_ReadStatusReg2(qspi_device);
+
+    u8Status2 &= ~W25X_REG_QUADENABLE;
+
+    result = SpiFlash_WriteStatusReg(qspi_device, u8Status1, u8Status2);
+    RT_ASSERT(result == RT_EOK);
+
+    SpiFlash_WaitReady(qspi_device);
+}
+
+static int rt_hw_spiflash_init(void)
+{
+    if (nu_qspi_bus_attach_device("qspi0", "qspi01", 2, SpiFlash_EnterQspiMode, SpiFlash_ExitQspiMode) != RT_EOK)
+        return -1;
+
+#if defined(RT_USING_SFUD)
+    if (rt_sfud_flash_probe(FAL_USING_NOR_FLASH_DEV_NAME, "qspi01") == RT_NULL)
+    {
+        return -(RT_ERROR);
+    }
+#endif
+    return 0;
+}
+INIT_COMPONENT_EXPORT(rt_hw_spiflash_init);
+#endif
+
+#if defined(BOARD_USING_STORAGE_SPINAND) && defined(NU_PKG_USING_SPINAND)
+
+#include "drv_qspi.h"
+#include "spinand.h"
+
+struct rt_mtd_nand_device mtd_partitions[MTD_SPINAND_PARTITION_NUM] =
+{
+    [0] =
+    {
+        .block_start =  0,
+        .block_end   = 23,
+        .block_total = 24,
+    },
+    [1] =
+    {
+        .block_start = 24,
+        .block_end   = 1023,
+        .block_total = 1000,
+    },
+    [2] =
+    {
+        .block_start = 0,
+        .block_end   = 1023,
+        .block_total = 1024,
+    }
+};
+
+static int rt_hw_spinand_init(void)
+{
+    if (nu_qspi_bus_attach_device("qspi0", "qspi01", 4, RT_NULL, RT_NULL) != RT_EOK)
+        return -1;
+
+    if (rt_hw_mtd_spinand_register("qspi01") != RT_EOK)
+        return -1;
+
+    return 0;
+}
+
+INIT_COMPONENT_EXPORT(rt_hw_spinand_init);
+#endif
+
+#if defined(BOARD_USING_UART8_RS485)
+
+#include 
+
+#define NU_UART_DEVNAME "uart8"
+
+int test_rs485(int argc, char **argv)
+{
+    rt_device_t serial;
+    char txbuf[16];
+    rt_err_t ret;
+    int str_len;
+
+    serial = rt_device_find(NU_UART_DEVNAME);
+    if (!serial)
+    {
+        rt_kprintf("Can't find %s. EXIT.\n", NU_UART_DEVNAME);
+        goto exit_test_rs485;
+    }
+
+    /* Interrupt RX */
+    ret = rt_device_open(serial, RT_DEVICE_FLAG_INT_RX);
+    RT_ASSERT(ret == RT_EOK);
+
+    /* Nuvoton private command */
+    nu_uart_set_rs485aud((struct rt_serial_device *)serial, RT_FALSE);
+
+    rt_snprintf(&txbuf[0], sizeof(txbuf), "Hello World!\r\n");
+    str_len = rt_strlen(txbuf);
+
+    /* Say Hello */
+    ret = rt_device_write(serial, 0, &txbuf[0], str_len);
+    RT_ASSERT(ret == str_len);
+
+    ret = rt_device_close(serial);
+    RT_ASSERT(ret == RT_EOK);
+
+exit_test_rs485:
+
+    return 0;
+}
+MSH_CMD_EXPORT(test_rs485, test rs485 communication);
+
+#endif //defined(BOARD_USING_UART8_RS485)
+
diff --git a/bsp/nuvoton/nk-rtu980/board/fal_cfg.h b/bsp/nuvoton/nk-rtu980/board/fal_cfg.h
new file mode 100644
index 0000000000..99ee81b405
--- /dev/null
+++ b/bsp/nuvoton/nk-rtu980/board/fal_cfg.h
@@ -0,0 +1,46 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author       Notes
+* 2020-3-03       FYChou       First version
+*
+******************************************************************************/
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include 
+#include 
+
+/* ===================== Flash device Configuration ========================= */
+#if defined(RT_USING_SFUD)
+extern struct fal_flash_dev nor_flash0;
+
+/* -flash device table------------------------------------------------------- */
+#define FAL_FLASH_DEV_TABLE                                                    \
+{                                                                              \
+    &nor_flash0,                                                               \
+}
+#else
+#define FAL_FLASH_DEV_TABLE                                                    \
+{                                                                              \
+    0                                                                          \
+}
+#endif
+
+/* ====================== Partition Configuration ============================ */
+#ifdef FAL_PART_HAS_TABLE_CFG
+
+/* partition table------------------------------------------------------------ */
+#define FAL_PART_TABLE                                                         \
+{                                                                              \
+    {FAL_PART_MAGIC_WORD, "rtthread",   FAL_USING_NOR_FLASH_DEV_NAME,           0,  4*1024*1024, 0}, \
+    {FAL_PART_MAGIC_WORD, "filesystem", FAL_USING_NOR_FLASH_DEV_NAME, 4*1024*1024, 28*1024*1024, 0}, \
+}
+#endif /* FAL_PART_HAS_TABLE_CFG */
+
+#endif /* _FAL_CFG_H_ */
diff --git a/bsp/nuvoton/nk-rtu980/board/nu_pin_init.c b/bsp/nuvoton/nk-rtu980/board/nu_pin_init.c
new file mode 100644
index 0000000000..af36b98ccd
--- /dev/null
+++ b/bsp/nuvoton/nk-rtu980/board/nu_pin_init.c
@@ -0,0 +1,85 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author       Notes
+* 2020-12-12      Wayne        First version
+*
+******************************************************************************/
+
+#include "board.h"
+
+static void nu_pin_uart_init(void)
+{
+    /* UART0: GPF11, GPF12 */
+    outpw(REG_SYS_GPF_MFPH, (inpw(REG_SYS_GPF_MFPH) & 0xFFF00FFF) | 0x00011000);
+
+    /* UART4: GPC9, GPC10 */
+    outpw(REG_SYS_GPC_MFPH, (inpw(REG_SYS_GPC_MFPH) & 0xFFFFF00F) | 0x00000770);
+
+    /* UART8: GPC12, GPC13, GPC14 */
+    outpw(REG_SYS_GPC_MFPH, (inpw(REG_SYS_GPC_MFPH) & 0xF000FFFF) | 0x07770000);
+}
+
+static void nu_pin_emac_init(void)
+{
+    /* EMAC1  */
+    outpw(REG_SYS_GPF_MFPL, 0x11111111);
+    outpw(REG_SYS_GPF_MFPH, (inpw(REG_SYS_GPF_MFPH) & 0xFFFFFF00) | 0x00000011);
+}
+
+static void nu_pin_qspi_init(void)
+{
+    /* QSPI0: PD[2, 5]  */
+    outpw(REG_SYS_GPD_MFPL, (inpw(REG_SYS_GPD_MFPL) & 0xFF0000FF) | 0x00111100);
+}
+
+static void nu_pin_spi_init(void)
+{
+    /* SPI0: PC[4, 8]  */
+    outpw(REG_SYS_GPC_MFPL, (inpw(REG_SYS_GPC_MFPL) & 0xF000FFFF) | 0x05560000);
+    outpw(REG_SYS_GPC_MFPH, (inpw(REG_SYS_GPC_MFPH) & 0xFFFFFFF0) | 0x00000005);
+}
+
+static void nu_pin_i2c_init(void)
+{
+    /* I2C1: PB4, PB6 */
+    outpw(REG_SYS_GPB_MFPL, (inpw(REG_SYS_GPB_MFPL) & 0xF0F0FFFF) | 0x02020000);
+}
+
+static void nu_pin_can_init(void)
+{
+    /* CAN3: PA0, PA1 */
+    outpw(REG_SYS_GPA_MFPL, (inpw(REG_SYS_GPA_MFPL) & 0xFFFFFF00) | 0x00000077);
+}
+
+static void nu_pin_usbd_init(void)
+{
+    /* USB0_VBUSVLD, PE.11  */
+    outpw(REG_SYS_GPE_MFPH, (inpw(REG_SYS_GPE_MFPH) & 0xFFFF0FFF) | 0x00001000);
+}
+
+static void nu_pin_usbh_init(void)
+{
+}
+
+void nu_pin_init(void)
+{
+    nu_pin_uart_init();
+    nu_pin_emac_init();
+    nu_pin_qspi_init();
+    nu_pin_spi_init();
+    nu_pin_i2c_init();
+    nu_pin_can_init();
+
+    nu_pin_usbd_init();
+    nu_pin_usbh_init();
+}
+
+void nu_pin_deinit(void)
+{
+
+}
diff --git a/bsp/zynq7000/zynq7000.ld b/bsp/nuvoton/nk-rtu980/linking_scripts/nuc980.ld
similarity index 50%
rename from bsp/zynq7000/zynq7000.ld
rename to bsp/nuvoton/nk-rtu980/linking_scripts/nuc980.ld
index ae9b8ea38d..1004f039fb 100644
--- a/bsp/zynq7000/zynq7000.ld
+++ b/bsp/nuvoton/nk-rtu980/linking_scripts/nuc980.ld
@@ -1,40 +1,23 @@
-/*
- * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
- *
- *  This file is part of RT-Thread (http://www.rt-thread.org)
- *
- *  All rights reserved.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
 OUTPUT_ARCH(arm)
+ENTRY(system_vectors)
+
+MEMORY
+{
+    RAM  (rwx)   : ORIGIN = 0x000000, LENGTH = 0x04000000
+}
+
 SECTIONS
 {
-    . = 0x1ff00000;
-    __text_start = .;
-    .text :
+    . = 0x0;
+
+    . = ALIGN(4);
+    .text : 
     {
         *(.vectors)
-        /* make the ISRs close to vectors may be more cache-friendly */
-        *(.text.isr)
-
         *(.text)
-        *(.text.*)
-
+        *(.gnu.linkonce.t*)
+        
         /* section information for finsh shell */
         . = ALIGN(4);
         __fsymtab_start = .;
@@ -44,6 +27,12 @@ SECTIONS
         __vsymtab_start = .;
         KEEP(*(VSymTab))
         __vsymtab_end = .;
+        . = ALIGN(4);   
+
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
         . = ALIGN(4);
 
         /* section information for modules */
@@ -51,18 +40,24 @@ SECTIONS
         __rtmsymtab_start = .;
         KEEP(*(RTMSymTab))
         __rtmsymtab_end = .;
+        . = ALIGN(4);
 
-        /* section information for initialization */
+        /* section information for initial. */
         . = ALIGN(4);
         __rt_init_start = .;
         KEEP(*(SORT(.rti_fn*)))
         __rt_init_end = .;
-    } =0
-    __text_end = .;
+        . = ALIGN(4);
 
-    __rodata_start = .;
-    .rodata   : { *(.rodata) *(.rodata.*) }
-    __rodata_end = .;
+        /* section information for utest */
+        . = ALIGN(4);
+        __rt_utest_tc_tab_start = .;
+        KEEP(*(UtestTcTab))
+        __rt_utest_tc_tab_end = .;
+    }
+
+    . = ALIGN(4);
+    .rodata : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r*) *(.eh_frame) }
 
     . = ALIGN(4);
     .ctors :
@@ -81,29 +76,27 @@ SECTIONS
         PROVIDE(__dtors_end__ = .);
     }
 
-    __data_start = .;
     . = ALIGN(4);
     .data :
     {
-        KEEP(*(.resource_table))
         *(.data)
         *(.data.*)
+        *(.gnu.linkonce.d*)
     }
-    __data_end = .;
 
     . = ALIGN(4);
-    __bss_start = __data_end;
-    .bss       :
-    {
-    *(.bss)
-    *(.bss.*)
-    *(COMMON)
+    .nobss : { *(.nobss) }
+    
     . = ALIGN(4);
-    }
+    __bss_start__ = .;
+    __bss_start = .;
+    .bss : { *(.bss)}
     . = ALIGN(4);
     __bss_end = .;
+    __bss_end__ = .;
+    . = ALIGN(4);
 
-    /* Stabs debugging sections.  */
+    /* stabs debugging sections. */
     .stab 0 : { *(.stab) }
     .stabstr 0 : { *(.stabstr) }
     .stab.excl 0 : { *(.stab.excl) }
@@ -111,6 +104,11 @@ SECTIONS
     .stab.index 0 : { *(.stab.index) }
     .stab.indexstr 0 : { *(.stab.indexstr) }
     .comment 0 : { *(.comment) }
+    .debug_abbrev 0 : { *(.debug_abbrev) }
+    .debug_info 0 : { *(.debug_info) }
+    .debug_line 0 : { *(.debug_line) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    .debug_aranges 0 : { *(.debug_aranges) }
 
     _end = .;
 }
diff --git a/bsp/nuvoton/nk-rtu980/linking_scripts/nuc980.sct b/bsp/nuvoton/nk-rtu980/linking_scripts/nuc980.sct
new file mode 100644
index 0000000000..114b346e8c
--- /dev/null
+++ b/bsp/nuvoton/nk-rtu980/linking_scripts/nuc980.sct
@@ -0,0 +1,11 @@
+LR_IROM1 0x00000000 0x800000  {    ; load region size_region
+    ER_IROM1 0x00000000 0x800000  {  ; load address = execution address
+        *.o (RESET, +First)
+        *(InRoot$$Sections)
+        .ANY (+RO)
+    }
+    RW_RAM1 +0  {  ; RW_RAM1 start address is after ER_ROM1
+        .ANY (+RW +ZI)
+    }
+}
+
diff --git a/bsp/nuvoton/nk-rtu980/rtconfig.py b/bsp/nuvoton/nk-rtu980/rtconfig.py
new file mode 100644
index 0000000000..c246b656ad
--- /dev/null
+++ b/bsp/nuvoton/nk-rtu980/rtconfig.py
@@ -0,0 +1,88 @@
+import os
+# toolchains options
+ARCH     = 'arm'
+CPU      = 'arm926'
+# toolchains options
+CROSS_TOOL 	= 'gcc'
+
+#------- toolchains path -------------------------------------------------------
+if os.getenv('RTT_CC'):
+	CROSS_TOOL = os.getenv('RTT_CC')
+
+if  CROSS_TOOL == 'gcc':
+	PLATFORM = 'gcc'
+	EXEC_PATH = r'C:\Program Files (x86)\GNU Tools ARM Embedded\6 2017-q1-update\bin'
+elif CROSS_TOOL == 'keil':
+	PLATFORM 	= 'armcc'
+	EXEC_PATH 	= r'C:\Keil_v5'
+
+if os.getenv('RTT_EXEC_PATH'):
+	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+#BUILD = 'release'
+
+CORE = 'arm926ej-s'
+MAP_FILE = 'rtthread_nuc980.map'
+LINK_FILE = 'linking_scripts/nuc980'
+TARGET_NAME = 'rtthread.bin'
+
+#------- GCC settings ----------------------------------------------------------
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    CXX = PREFIX + 'g++'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=arm926ej-s'
+    CFLAGS = DEVICE
+    AFLAGS = '-c'+ DEVICE + ' -x assembler-with-cpp'
+    AFLAGS += ' -Iplatform'
+    LFLAGS = DEVICE
+    LFLAGS += ' -Wl,--gc-sections,-cref,-Map=' + MAP_FILE
+    LFLAGS += ' -T ' + LINK_FILE + '.ld'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O2 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET ' + TARGET_NAME + '\n' 
+    POST_ACTION += SIZE + ' $TARGET\n'
+#------- Keil settings ---------------------------------------------------------
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+    EXEC_PATH += '/arm/armcc/bin/'
+
+    DEVICE = ' --cpu=' + CORE
+    CFLAGS = DEVICE + ' --apcs=interwork --diag_suppress=870'
+    AFLAGS = DEVICE + ' -Iplatform'
+    LFLAGS = DEVICE + ' --strict'
+    LFLAGS += ' --info sizes --info totals --info unused --info veneers'
+    LFLAGS += ' --list ' + MAP_FILE
+    LFLAGS += ' --scatter  ' + LINK_FILE + '.sct'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output ' + TARGET_NAME + ' \n'
+    POST_ACTION += 'fromelf -z $TARGET\n'
\ No newline at end of file
diff --git a/bsp/nuvoton/nk-rtu980/template.uvproj b/bsp/nuvoton/nk-rtu980/template.uvproj
new file mode 100644
index 0000000000..23e8dd2bcb
--- /dev/null
+++ b/bsp/nuvoton/nk-rtu980/template.uvproj
@@ -0,0 +1,394 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      rtthread
+      0x4
+      ARM-ADS
+      
+        
+          Nuvoton_ARM9_Series
+          Nuvoton
+          
+          
+          
+          
+          0
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          0
+          
+          
+          
+          Atmel\SAM9260\
+          Atmel\SAM9260\
+          
+            0
+            0
+            0
+            0
+            1
+          
+          .\Objects\
+          rtthread
+          1
+          0
+          0
+          1
+          1
+          .\Listings\
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+        
+        
+          SARM.DLL
+          -cAT91SAM9
+          DARMATS9.DLL
+          -p91SAM9260
+          SARM.DLL
+          
+          TARMATS9.DLL
+          -p91SAM9260
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+          
+          
+            1
+            0
+            0
+            1
+            1
+            1
+            0
+            1
+            1
+          
+          0
+          6
+          
+            
+            
+            
+            
+            
+          
+          
+            
+            
+            
+            
+            ..\libraries\nuc980\Script\NUC980xx61.ini
+            Segger\JLTAgdi.dll
+          
+        
+        
+          
+            1
+            0
+            0
+            0
+            1
+            4098
+          
+          0
+          Segger\JLTAgdi.dll
+          "" ()
+          
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x200000
+                0x1000
+              
+              
+                1
+                0x100000
+                0x8000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            
+              --c99
+              RT_USING_INTERRUPT_INFO
+              
+              
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x20000000
+            0x20800000
+            .\linking_scripts\nuc980.sct
+            
+            
+            
+            
+            
+          
+        
+      
+    
+  
+
+
diff --git a/bsp/nuvoton/nk-rtu980/template.uvprojx b/bsp/nuvoton/nk-rtu980/template.uvprojx
new file mode 100644
index 0000000000..aad158ccc3
--- /dev/null
+++ b/bsp/nuvoton/nk-rtu980/template.uvprojx
@@ -0,0 +1,387 @@
+
+
+
+  2.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      rtthread
+      0x4
+      ARM-ADS
+      0
+      
+        
+          Nuvoton_ARM9_Series
+          Nuvoton
+          
+          
+          
+          
+          0
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          0
+          0
+          
+          
+          
+          Atmel\SAM9260\
+          Atmel\SAM9260\
+          
+            0
+            0
+            0
+            0
+            1
+          
+          .\build\keil5\
+          rtthread
+          1
+          0
+          1
+          1
+          1
+          .\build\keil5\
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            1
+            0
+            fromelf.exe --bin --output "$L@L.bin" "$L@L.axf"
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          1
+        
+        
+          SARM.DLL
+          -cAT91SAM9260
+          DARMATS9.DLL
+          -p91SAM9260
+          SARM.DLL
+          
+          TARMATS9.DLL
+          -p91SAM9260
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            0
+            1
+            4098
+          
+          0
+          Segger\JLTAgdi.dll
+          "" ()
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            ARM926EJ-S
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            8
+            0
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x200000
+                0x1000
+              
+              
+                1
+                0x100000
+                0x8000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x20000000
+                0x800000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x100000
+                0x8000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x20800000
+                0x1800000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x200000
+                0x1000
+              
+              
+                0
+                0x300000
+                0x1000
+              
+            
+            
+          
+          
+            1
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            2
+            0
+            0
+            0
+            0
+            0
+            1
+            1
+            1
+            1
+            0
+            0
+            0
+            
+              --c99
+              
+              
+              
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x20000000
+            0x20800000
+            
+            .\linking_scripts\nuc980.sct
+            
+            
+            
+            
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+    
+  
+
+
diff --git a/bsp/nuvoton/numaker-m2354/.config b/bsp/nuvoton/numaker-m2354/.config
new file mode 100644
index 0000000000..afa50ed670
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/.config
@@ -0,0 +1,796 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=2048
+# CONFIG_RT_USING_TIMER_SOFT is not set
+CONFIG_RT_DEBUG=y
+CONFIG_RT_DEBUG_COLOR=y
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+CONFIG_RT_USING_SIGNALS=y
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=256
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+CONFIG_RT_VER_NUM=0x40003
+# CONFIG_RT_USING_CPU_FFS is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+# CONFIG_FINSH_USING_MSH_ONLY is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=4
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
+CONFIG_DFS_FD_MAX=32
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+CONFIG_RT_USING_DFS_ELMFAT=y
+
+#
+# elm-chan's FatFs, Generic FAT Filesystem Module
+#
+CONFIG_RT_DFS_ELM_CODE_PAGE=437
+CONFIG_RT_DFS_ELM_WORD_ACCESS=y
+# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
+CONFIG_RT_DFS_ELM_USE_LFN_3=y
+CONFIG_RT_DFS_ELM_USE_LFN=3
+CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
+CONFIG_RT_DFS_ELM_LFN_UNICODE=0
+CONFIG_RT_DFS_ELM_MAX_LFN=255
+CONFIG_RT_DFS_ELM_DRIVES=2
+CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096
+# CONFIG_RT_DFS_ELM_USE_ERASE is not set
+CONFIG_RT_DFS_ELM_REENTRANT=y
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_UFFS is not set
+# CONFIG_RT_USING_DFS_JFFS2 is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=64
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=2048
+CONFIG_RT_USING_CAN=y
+# CONFIG_RT_CAN_USING_HDR is not set
+CONFIG_RT_USING_HWTIMER=y
+# CONFIG_RT_USING_CPUTIME is not set
+CONFIG_RT_USING_I2C=y
+# CONFIG_RT_I2C_DEBUG is not set
+CONFIG_RT_USING_I2C_BITOPS=y
+# CONFIG_RT_I2C_BITOPS_DEBUG is not set
+# CONFIG_RT_USING_PHY is not set
+CONFIG_RT_USING_PIN=y
+CONFIG_RT_USING_ADC=y
+# CONFIG_RT_USING_DAC is not set
+CONFIG_RT_USING_PWM=y
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+CONFIG_RT_USING_PM=y
+CONFIG_RT_USING_RTC=y
+# CONFIG_RT_USING_ALARM is not set
+# CONFIG_RT_USING_SOFT_RTC is not set
+CONFIG_RTC_SYNC_USING_NTP=y
+CONFIG_RTC_NTP_FIRST_SYNC_DELAY=30
+CONFIG_RTC_NTP_SYNC_PERIOD=3600
+# CONFIG_RT_USING_SDIO is not set
+CONFIG_RT_USING_SPI=y
+CONFIG_RT_USING_QSPI=y
+# CONFIG_RT_USING_SPI_MSD is not set
+CONFIG_RT_USING_SFUD=y
+CONFIG_RT_SFUD_USING_SFDP=y
+CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y
+CONFIG_RT_SFUD_USING_QSPI=y
+CONFIG_RT_SFUD_SPI_MAX_HZ=50000000
+CONFIG_RT_DEBUG_SFUD=y
+# CONFIG_RT_USING_ENC28J60 is not set
+# CONFIG_RT_USING_SPI_WIFI is not set
+CONFIG_RT_USING_WDT=y
+CONFIG_RT_USING_AUDIO=y
+CONFIG_RT_AUDIO_REPLAY_MP_BLOCK_SIZE=4096
+CONFIG_RT_AUDIO_REPLAY_MP_BLOCK_COUNT=2
+CONFIG_RT_AUDIO_RECORD_PIPE_SIZE=2048
+CONFIG_RT_USING_SENSOR=y
+CONFIG_RT_USING_SENSOR_CMD=y
+# CONFIG_RT_USING_TOUCH is not set
+CONFIG_RT_USING_HWCRYPTO=y
+CONFIG_RT_HWCRYPTO_DEFAULT_NAME="hwcryto"
+CONFIG_RT_HWCRYPTO_IV_MAX_SIZE=16
+CONFIG_RT_HWCRYPTO_KEYBIT_MAX_SIZE=256
+# CONFIG_RT_HWCRYPTO_USING_GCM is not set
+CONFIG_RT_HWCRYPTO_USING_AES=y
+CONFIG_RT_HWCRYPTO_USING_AES_ECB=y
+CONFIG_RT_HWCRYPTO_USING_AES_CBC=y
+CONFIG_RT_HWCRYPTO_USING_AES_CFB=y
+CONFIG_RT_HWCRYPTO_USING_AES_CTR=y
+CONFIG_RT_HWCRYPTO_USING_AES_OFB=y
+CONFIG_RT_HWCRYPTO_USING_DES=y
+CONFIG_RT_HWCRYPTO_USING_DES_ECB=y
+CONFIG_RT_HWCRYPTO_USING_DES_CBC=y
+CONFIG_RT_HWCRYPTO_USING_3DES=y
+CONFIG_RT_HWCRYPTO_USING_3DES_ECB=y
+CONFIG_RT_HWCRYPTO_USING_3DES_CBC=y
+# CONFIG_RT_HWCRYPTO_USING_RC4 is not set
+# CONFIG_RT_HWCRYPTO_USING_MD5 is not set
+CONFIG_RT_HWCRYPTO_USING_SHA1=y
+CONFIG_RT_HWCRYPTO_USING_SHA2=y
+CONFIG_RT_HWCRYPTO_USING_SHA2_224=y
+CONFIG_RT_HWCRYPTO_USING_SHA2_256=y
+CONFIG_RT_HWCRYPTO_USING_SHA2_384=y
+CONFIG_RT_HWCRYPTO_USING_SHA2_512=y
+CONFIG_RT_HWCRYPTO_USING_RNG=y
+CONFIG_RT_HWCRYPTO_USING_CRC=y
+CONFIG_RT_HWCRYPTO_USING_CRC_07=y
+CONFIG_RT_HWCRYPTO_USING_CRC_8005=y
+CONFIG_RT_HWCRYPTO_USING_CRC_1021=y
+# CONFIG_RT_HWCRYPTO_USING_CRC_3D65 is not set
+CONFIG_RT_HWCRYPTO_USING_CRC_04C11DB7=y
+# CONFIG_RT_HWCRYPTO_USING_BIGNUM is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+CONFIG_RT_USING_USB_HOST=y
+CONFIG_RT_USBH_MSTORAGE=y
+CONFIG_UDISK_MOUNTPOINT="/"
+CONFIG_RT_USING_USB_DEVICE=y
+CONFIG_RT_USBD_THREAD_STACK_SZ=4096
+CONFIG_USB_VENDOR_ID=0x0FFE
+CONFIG_USB_PRODUCT_ID=0x0001
+# CONFIG_RT_USB_DEVICE_COMPOSITE is not set
+# CONFIG__RT_USB_DEVICE_NONE is not set
+# CONFIG__RT_USB_DEVICE_CDC is not set
+# CONFIG__RT_USB_DEVICE_MSTORAGE is not set
+CONFIG__RT_USB_DEVICE_HID=y
+# CONFIG__RT_USB_DEVICE_WINUSB is not set
+# CONFIG__RT_USB_DEVICE_AUDIO is not set
+CONFIG_RT_USB_DEVICE_HID=y
+# CONFIG_RT_USB_DEVICE_HID_KEYBOARD is not set
+CONFIG_RT_USB_DEVICE_HID_MOUSE=y
+# CONFIG_RT_USB_DEVICE_HID_GENERAL is not set
+# CONFIG_RT_USB_DEVICE_HID_MEDIA is not set
+
+#
+# POSIX layer and C standard library
+#
+CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_PTHREADS is not set
+CONFIG_RT_USING_POSIX=y
+# CONFIG_RT_USING_POSIX_MMAP is not set
+# CONFIG_RT_USING_POSIX_TERMIOS is not set
+# CONFIG_RT_USING_POSIX_GETLINE is not set
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+CONFIG_RT_USING_SAL=y
+CONFIG_SAL_INTERNET_CHECK=y
+
+#
+# protocol stack implement
+#
+CONFIG_SAL_USING_AT=y
+CONFIG_SAL_USING_POSIX=y
+
+#
+# Network interface device
+#
+CONFIG_RT_USING_NETDEV=y
+CONFIG_NETDEV_USING_IFCONFIG=y
+CONFIG_NETDEV_USING_PING=y
+CONFIG_NETDEV_USING_NETSTAT=y
+CONFIG_NETDEV_USING_AUTO_DEFAULT=y
+# CONFIG_NETDEV_USING_IPV6 is not set
+CONFIG_NETDEV_IPV4=1
+CONFIG_NETDEV_IPV6=0
+# CONFIG_NETDEV_IPV6_SCOPES is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# AT commands
+#
+CONFIG_RT_USING_AT=y
+# CONFIG_AT_DEBUG is not set
+# CONFIG_AT_USING_SERVER is not set
+CONFIG_AT_USING_CLIENT=y
+CONFIG_AT_CLIENT_NUM_MAX=1
+CONFIG_AT_USING_SOCKET=y
+CONFIG_AT_USING_CLI=y
+# CONFIG_AT_PRINT_RAW_CMD is not set
+CONFIG_AT_CMD_MAX_LEN=2048
+CONFIG_AT_SW_VERSION_NUM=0x10301
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+CONFIG_RT_USING_UTEST=y
+CONFIG_UTEST_THR_STACK_SIZE=4096
+CONFIG_UTEST_THR_PRIORITY=20
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+CONFIG_PKG_USING_NETUTILS=y
+CONFIG_PKG_NETUTILS_PATH="/packages/iot/netutils"
+# CONFIG_PKG_NETUTILS_TFTP is not set
+CONFIG_PKG_NETUTILS_IPERF=y
+CONFIG_PKG_NETUTILS_NTP=y
+CONFIG_NETUTILS_NTP_TIMEZONE=8
+CONFIG_NETUTILS_NTP_HOSTNAME="time.stdtime.gov.tw"
+CONFIG_NETUTILS_NTP_HOSTNAME2="ntp.rt-thread.org"
+CONFIG_NETUTILS_NTP_HOSTNAME3="edu.ntp.org.cn"
+# CONFIG_PKG_NETUTILS_TELNET is not set
+# CONFIG_PKG_USING_NETUTILS_V120 is not set
+# CONFIG_PKG_USING_NETUTILS_V110 is not set
+# CONFIG_PKG_USING_NETUTILS_V100 is not set
+CONFIG_PKG_USING_NETUTILS_LATEST_VERSION=y
+CONFIG_PKG_NETUTILS_VER="latest"
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+CONFIG_PKG_USING_AT_DEVICE=y
+CONFIG_PKG_AT_DEVICE_PATH="/packages/iot/at_device"
+# CONFIG_AT_DEVICE_USING_M26 is not set
+# CONFIG_AT_DEVICE_USING_EC20 is not set
+# CONFIG_AT_DEVICE_USING_ESP32 is not set
+CONFIG_AT_DEVICE_USING_ESP8266=y
+CONFIG_AT_DEVICE_ESP8266_INIT_ASYN=y
+# CONFIG_AT_DEVICE_ESP8266_SAMPLE is not set
+# CONFIG_AT_DEVICE_USING_RW007 is not set
+# CONFIG_AT_DEVICE_USING_SIM800C is not set
+# CONFIG_AT_DEVICE_USING_SIM76XX is not set
+# CONFIG_AT_DEVICE_USING_MW31 is not set
+# CONFIG_AT_DEVICE_USING_W60X is not set
+# CONFIG_AT_DEVICE_USING_A9G is not set
+# CONFIG_AT_DEVICE_USING_BC26 is not set
+# CONFIG_AT_DEVICE_USING_AIR720 is not set
+# CONFIG_AT_DEVICE_USING_ME3616 is not set
+# CONFIG_AT_DEVICE_USING_M6315 is not set
+# CONFIG_AT_DEVICE_USING_BC28 is not set
+# CONFIG_AT_DEVICE_USING_EC200X is not set
+# CONFIG_AT_DEVICE_USING_N21 is not set
+# CONFIG_AT_DEVICE_USING_N58 is not set
+# CONFIG_AT_DEVICE_USING_M5311 is not set
+# CONFIG_AT_DEVICE_USING_L610 is not set
+# CONFIG_AT_DEVICE_USING_N720 is not set
+CONFIG_PKG_USING_AT_DEVICE_LATEST_VERSION=y
+CONFIG_PKG_AT_DEVICE_VER="latest"
+CONFIG_PKG_AT_DEVICE_VER_NUM=0x99999
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+CONFIG_PKG_USING_FAL=y
+CONFIG_PKG_FAL_PATH="/packages/system/fal"
+CONFIG_FAL_DEBUG_CONFIG=y
+CONFIG_FAL_DEBUG=1
+CONFIG_FAL_PART_HAS_TABLE_CFG=y
+# CONFIG_FAL_USING_SFUD_PORT is not set
+CONFIG_PKG_USING_FAL_V00500=y
+# CONFIG_PKG_USING_FAL_V00400 is not set
+# CONFIG_PKG_USING_FAL_V00300 is not set
+# CONFIG_PKG_USING_FAL_V00200 is not set
+# CONFIG_PKG_USING_FAL_V00100 is not set
+# CONFIG_PKG_USING_FAL_LATEST_VERSION is not set
+CONFIG_PKG_FAL_VER="v0.5.0"
+CONFIG_PKG_FAL_VER_NUM=0x00500
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RT_PRINTF is not set
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+
+#
+# games: games run on RT-Thread console
+#
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+
+#
+# Nuvoton Packages Config
+#
+CONFIG_NU_PKG_USING_UTILS=y
+CONFIG_NU_PKG_USING_DEMO=y
+# CONFIG_NU_PKG_USING_BMX055 is not set
+# CONFIG_NU_PKG_USING_MAX31875 is not set
+# CONFIG_NU_PKG_USING_NAU88L25 is not set
+# CONFIG_NU_PKG_USING_NAU8822 is not set
+# CONFIG_NU_PKG_USING_ILI9341 is not set
+# CONFIG_NU_PKG_USING_SPINAND is not set
+
+#
+# Hardware Drivers Config
+#
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_SOC_SERIES_M2354=y
+# CONFIG_BSP_USE_STDDRIVER_SOURCE is not set
+CONFIG_BSP_USING_PDMA=y
+CONFIG_NU_PDMA_MEMFUN_ACTOR_MAX=2
+CONFIG_NU_PDMA_SGTBL_POOL_SIZE=16
+CONFIG_BSP_USING_FMC=y
+CONFIG_BSP_USING_GPIO=y
+CONFIG_BSP_USING_CLK=y
+CONFIG_NU_CLK_INVOKE_WKTMR=y
+CONFIG_BSP_USING_RTC=y
+# CONFIG_NU_RTC_SUPPORT_IO_RW is not set
+CONFIG_NU_RTC_SUPPORT_MSH_CMD=y
+CONFIG_BSP_USING_EADC=y
+CONFIG_BSP_USING_EADC0=y
+CONFIG_BSP_USING_TMR=y
+# CONFIG_BSP_USING_TMR0 is not set
+# CONFIG_BSP_USING_TMR1 is not set
+# CONFIG_BSP_USING_TMR2 is not set
+# CONFIG_BSP_USING_TMR3 is not set
+# CONFIG_BSP_USING_TMR4 is not set
+CONFIG_BSP_USING_UART=y
+CONFIG_BSP_USING_UART0=y
+# CONFIG_BSP_USING_UART0_TX_DMA is not set
+# CONFIG_BSP_USING_UART0_RX_DMA is not set
+CONFIG_BSP_USING_UART1=y
+# CONFIG_BSP_USING_UART1_TX_DMA is not set
+# CONFIG_BSP_USING_UART1_RX_DMA is not set
+# CONFIG_BSP_USING_UART2 is not set
+# CONFIG_BSP_USING_UART3 is not set
+CONFIG_BSP_USING_UART4=y
+CONFIG_BSP_USING_UART4_TX_DMA=y
+CONFIG_BSP_USING_UART4_RX_DMA=y
+# CONFIG_BSP_USING_UART5 is not set
+CONFIG_BSP_USING_I2C=y
+# CONFIG_BSP_USING_I2C0 is not set
+CONFIG_BSP_USING_I2C1=y
+# CONFIG_BSP_USING_I2C2 is not set
+# CONFIG_BSP_USING_USCI is not set
+CONFIG_BSP_USING_SDH=y
+CONFIG_BSP_USING_SDH0=y
+CONFIG_NU_SDH_USING_PDMA=y
+CONFIG_NU_SDH_HOTPLUG=y
+CONFIG_NU_SDH_MOUNT_ON_ROOT=y
+# CONFIG_BSP_USING_CAN is not set
+# CONFIG_BSP_USING_BPWM is not set
+# CONFIG_BSP_USING_EPWM is not set
+CONFIG_BSP_USING_SPI=y
+# CONFIG_BSP_USING_SPI_PDMA is not set
+# CONFIG_BSP_USING_SPII2S is not set
+# CONFIG_BSP_USING_SPI0_NONE is not set
+CONFIG_BSP_USING_SPI0=y
+# CONFIG_BSP_USING_SPII2S0 is not set
+# CONFIG_BSP_USING_SPI0_PDMA is not set
+# CONFIG_BSP_USING_SPI1_NONE is not set
+CONFIG_BSP_USING_SPI1=y
+# CONFIG_BSP_USING_SPII2S1 is not set
+# CONFIG_BSP_USING_SPI1_PDMA is not set
+CONFIG_BSP_USING_SPI2_NONE=y
+# CONFIG_BSP_USING_SPI2 is not set
+# CONFIG_BSP_USING_SPII2S2 is not set
+CONFIG_BSP_USING_SPI3_NONE=y
+# CONFIG_BSP_USING_SPI3 is not set
+# CONFIG_BSP_USING_SPII2S3 is not set
+# CONFIG_BSP_USING_I2S is not set
+# CONFIG_BSP_USING_QSPI is not set
+# CONFIG_BSP_USING_SCUART is not set
+# CONFIG_BSP_USING_ECAP is not set
+# CONFIG_BSP_USING_QEI is not set
+CONFIG_BSP_USING_CRYPTO=y
+# CONFIG_NU_PRNG_USE_SEED is not set
+CONFIG_BSP_USING_TRNG=y
+CONFIG_BSP_USING_CRC=y
+CONFIG_NU_CRC_USE_PDMA=y
+# CONFIG_BSP_USING_SOFT_I2C is not set
+CONFIG_BSP_USING_WDT=y
+# CONFIG_BSP_USING_EBI is not set
+CONFIG_BSP_USING_SLCD=y
+CONFIG_BSP_USING_USBD=y
+CONFIG_BSP_USING_USBH=y
+CONFIG_NU_USBHOST_HUB_POLLING_INTERVAL=100
+CONFIG_BSP_USING_OTG=y
+
+#
+# On-board Peripheral Drivers
+#
+CONFIG_BSP_USING_NULINKME=y
+CONFIG_BOARD_USING_ESP8266=y
+CONFIG_BOARD_USING_STORAGE_SDCARD=y
+# CONFIG_BOARD_USING_USBD is not set
+# CONFIG_BOARD_USING_USBH is not set
+CONFIG_BOARD_USING_OTG=y
+# CONFIG_BOARD_USING_USB_NONE is not set
+
+#
+# Board extended module drivers
+#
+CONFIG_BOARD_USING_SEGMENT_LCD=y
+CONFIG_BOARD_USE_UTEST=y
+CONFIG_UTEST_CMD_PREFIX="bsp.nuvoton.numaker-m2354.test.utest."
diff --git a/bsp/nuvoton/numaker-m2354/Kconfig b/bsp/nuvoton/numaker-m2354/Kconfig
new file mode 100644
index 0000000000..90354447b3
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/Kconfig
@@ -0,0 +1,29 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+# you can change the RTT_ROOT default "../../.." to your rtthread_root,
+# example : default "F:/git_repositories/rt-thread"
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+config NU_PKGS_DIR
+    string
+    option env="NU_PKGS_ROOT"
+    default "../libraries/nu_packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "$NU_PKGS_DIR/Kconfig"
+source "$BSP_DIR/board/Kconfig"
diff --git a/bsp/nuvoton/numaker-m2354/Nu_Link_Driver.ini b/bsp/nuvoton/numaker-m2354/Nu_Link_Driver.ini
new file mode 100644
index 0000000000..51ce76204b
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/Nu_Link_Driver.ini
@@ -0,0 +1,1037 @@
+[Version]
+Nu_LinkVersion=V5.14
+[Process]
+ProcessID=0x00003fc4
+ProcessCreationTime_L=0xfa4b822c
+ProcessCreationTime_H=0x01d6fb6d
+NuLinkID=0x1800002d
+NuLinkIDs_Count=0x00000001
+NuLinkID0=0x1800002d
+[ChipSelect]
+;ChipName=
+ChipName=M2354
+[NUC505]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x4000
+ProgramAlgorithm=NUC505_SPIFLASH.FLM
+[NUC4xx]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x4000
+ProgramAlgorithm=NUC400_AP_512.FLM
+TraceConf0=0x00000002
+TraceConf1=0x014fb180
+TraceConf2=0x00000800
+TraceConf3=0x00000000
+TraceConf4=0x00000001
+TraceConf5=0x00000000
+[NUC2xx]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=NUC200_AP_128.FLM
+[NUC1311]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=NUC1311_AP_64.FLM
+[NUC126]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x2000
+ProgramAlgorithm=NUC126_AP_256.FLM
+[NUC121]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=NUC121_AP_32.FLM
+[NUC1xx]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=NUC100_AP_128.FLM
+[NUC029]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x800
+ProgramAlgorithm=NUC029_AP_16.FLM
+[NM1820]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x800
+ProgramAlgorithm=NM1820_AP_17_5.FLM
+[NM1810]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x800
+ProgramAlgorithm=NM1810_AP_29_5.FLM
+[NM1500]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=NM1500_AP_128.FLM
+[NM1330]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=NM1330_AP_64.FLM
+[NM1320]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=NM1320_AP_32.FLM
+[NM1240]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=NM1240_AP_64.FLM
+[NM1230]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=NM1230_AP_64.FLM
+[NM1200]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x800
+ProgramAlgorithm=NM1200_AP_8.FLM
+[NM1120]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x800
+ProgramAlgorithm=NM1120_AP_29_5.FLM
+[TF5100]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=TF5100_AP_64.FLM
+[NDA102]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x800
+ProgramAlgorithm=NDA102_AP_29_5.FLM
+[Nano103]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=Nano103_AP_64.FLM
+[Nano100]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=Nano100_AP_64.FLM
+[N576]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=N576_AP_145.FLM
+[N575]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=N575_AP_145.FLM
+[N572]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x2000
+ProgramAlgorithm=N572Fxxx.FLM
+[N571]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x2000
+ProgramAlgorithm=N571E000.FLM
+[N570]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=N570_AP_64.FLM
+[N569]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=N569_AP_64.FLM
+[N512]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=N512_AP_64.FLM
+[Mini57]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x800
+ProgramAlgorithm=Mini57_AP_29_5.FLM
+[Mini51]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x800
+ProgramAlgorithm=Mini51_AP_16.FLM
+[M481]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x4000
+ProgramAlgorithm=M481_AP_512.FLM
+TraceConf0=0x00000002
+TraceConf1=0x00b71b00
+TraceConf2=0x00000800
+TraceConf3=0x00000000
+TraceConf4=0x00000001
+TraceConf5=0x00000000
+[M480LD]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x4000
+ProgramAlgorithm=M480LD_AP_256.FLM
+[M479]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x4000
+ProgramAlgorithm=M479_AP_256.FLM
+[M451]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x4000
+ProgramAlgorithm=M451_AP_256.FLM
+[M471]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Bank=0
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=1
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x4000
+ProgramAlgorithm=M471_AP_512.FLM
+TraceConf0=0x00000002
+TraceConf1=0x00b71b00
+TraceConf2=0x00000800
+TraceConf3=0x00000000
+TraceConf4=0x00000001
+TraceConf5=0x00000000
+[M251]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x2000
+ProgramAlgorithm=M251_AP_192.FLM
+[M2351]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=1
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x4000
+ProgramAlgorithm=M2351_AP_512.FLM
+TraceConf0=0x00000002
+TraceConf1=0x00b71b00
+TraceConf2=0x00000800
+TraceConf3=0x00000000
+TraceConf4=0x00000001
+TraceConf5=0x00000000
+[M261]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=1
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x4000
+ProgramAlgorithm=M261_AP_512.FLM
+TraceConf0=0x00000002
+TraceConf1=0x00b71b00
+TraceConf2=0x00000800
+TraceConf3=0x00000000
+TraceConf4=0x00000001
+TraceConf5=0x00000000
+[MR63]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=1
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x4000
+ProgramAlgorithm=MR63_AP_512.FLM
+TraceConf0=0x00000002
+TraceConf1=0x00b71b00
+TraceConf2=0x00000800
+TraceConf3=0x00000000
+TraceConf4=0x00000001
+TraceConf5=0x00000000
+[M2354]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Bank=0
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=1
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+CheckDPM=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x4000
+ProgramAlgorithm=M2354_AP_1M.FLM
+TraceConf0=0x00000002
+TraceConf1=0x00b71b00
+TraceConf2=0x00000800
+TraceConf3=0x00000000
+TraceConf4=0x00000001
+TraceConf5=0x00000000
+DisableTimeoutDetect=0
+[M071]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x2000
+ProgramAlgorithm=M071_AP_128.FLM
+[M0564]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x2000
+ProgramAlgorithm=M0564_AP_256.FLM
+[M0519]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=M0519_AP_128.FLM
+[M0518]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=M0518_AP_64.FLM
+[M05x]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=1
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x800
+ProgramAlgorithm=M0516_AP_64.FLM
+[M0A21]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=1
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x800
+ProgramAlgorithm=M0A21_AP_32.FLM
+[M030G]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=1
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+DisableTimeoutDetect=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x800
+ProgramAlgorithm=M030G_AP_64.FLM
+[M031]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Bank=0
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=1
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x800
+ProgramAlgorithm=M031_AP_128.FLM
+[NPCX]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x4000
+ProgramAlgorithm=NPCX_AP_512.FLM
+[I96000]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+Erase=2
+Program=0
+Verify=0
+ResetAndRun=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x8000
+ProgramAlgorithm=
+[I94000]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x4000
+ProgramAlgorithm=I94000_AP_512.FLM
+[ISD9300]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=ISD9300_AP_145.FLM
+[I9200]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=I9200_AP_128.FLM
+[ISD9xxx]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=ISD9100_AP_145.FLM
+[ISD9000]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=ISD9000_AP_64.FLM
+[AU9xxx]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+FlashSelect=APROM
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableFlashBreakpoint=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x1000
+ProgramAlgorithm=AU9100_AP_145.FLM
+[Autodetect]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x4000
+ProgramAlgorithm=
+[General]
+Connect=0
+Reset=Autodetect
+MaxClock=1MHz
+MemoryVerify=0
+IOVoltage=3300
+Erase=1
+Program=1
+Verify=1
+ResetAndRun=0
+EnableLog=0
+MemAccessWhileRun=0
+RAMForAlgorithmStart=0x20000000
+RAMForAlgorithmSize=0x4000
+ProgramAlgorithm=
diff --git a/bsp/nuvoton/numaker-m2354/README.md b/bsp/nuvoton/numaker-m2354/README.md
new file mode 100644
index 0000000000..5cc0d34fb8
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/README.md
@@ -0,0 +1,75 @@
+# NuMaker-M2354
+## 1. Introduction
+The NuMaker-M2354 is an evaluation board for Nuvoton NuMicro M2354 microcontrollers. The NuMaker-M2354 consists of two parts, a M2354 target board and an on-board Nu-Link2-Me debugger and programmer. The NuMaker-M2354 is designed for secure evaluation, prototype development and validation with power consumption monitoring function.
+
+[![NuMaker-M2354](https://i.imgur.com/uncXX0g.jpg "NuMaker-M2354")](https://i.imgur.com/uncXX0g.jpg "NuMaker-M2354")
+
+### 1.1 MCU specification
+
+|  | Features |
+| -- | -- |
+| MCU | M2354KJFAE |
+| Operation frequency | 96MHz |
+| embedded Flash size | 1MB, Dual Bank |
+| SRAM size | 256kB |
+| Crypto engine | PRNG, AES, ECC, RSA, HMAC and SHA crypto accelerator |
+
+### 1.2 Interface
+
+| Interface |
+| -- |
+| Arduino UNO |
+| USB 1.1 OTG ports |
+| A microSD slot |
+| A segment LCD port |
+
+### 1.3 On-board devices
+
+| Device | Description | Driver supporting status |
+| -- | -- | -- |
+|Wi-Fi module| ESP8266-ESP12, AT firmware v1.7 | Supported |
+|Segment LCD module| | Supported |
+
+## 2. Supported compiler
+Support GCC, MDK5, IAR IDE/compilers. More information of these compiler version as following:
+
+| IDE/Compiler  | Tested version                    |
+| ---------- | ------------------------------------ |
+| MDK5       | 5.26.2                               |
+| IAR        | 8.32                                 |
+| GCC        | GCC 6.3.1 20170620 (Need update env) |
+
+Notice: 
+(1) Please install Nu-Link_Keil_Driver or Nu-Link_IAR_Driver for development.
+(2) You must remove '--c99' flag in /components/drivers/spi/SConscript before generating MDK5 project file.
+
+## 3. Program firmware
+### Step 1:
+At first, you need to configure ISW1 switch on the NuMaker-M2354 board. Set the four switches to ‘ON’ position. After the configuration is done, connect the NuMaker-M2354 board and your computer using the USB Micro cable. After that, window manager will show a ‘NuMicro MCU’ virtual disk. Finally, you will use this virtual disk to burn firmware.
+
+[![NuLinkMe](https://i.imgur.com/us0Fhhu.png "NuLinkMe")](https://i.imgur.com/us0Fhhu.png "NuLinkMe")
+
+[![NuMicro MCU](https://i.imgur.com/lWnNtpM.png "NuMicro MCU")](https://i.imgur.com/lWnNtpM.png "NuMicro MCU")
+
+### Step 2:
+A simple firmware burning method is that you can drag and drop the binary image file to NuMicro MCU virtual disk or copy the binary file to NuMicro MCU disk to burn firmware.
+
+[![CopyTo](https://i.imgur.com/6NfGS7m.png "CopyTo")](https://i.imgur.com/6NfGS7m.png "CopyTo")
+
+## 4. Test
+You can use Tera Term terminate emulator (or other software) to type commands of RTT. All parameters of serial communication are shown in below image. Here, you can find out the corresponding port number of Nuvoton Virtual Com Port in window device manager.
+
+[![Serial settings](https://i.imgur.com/5NYuSNM.png "Serial settings")](https://i.imgur.com/5NYuSNM.png "Serial settings")
+
+## 5. Purchase
+* [Nuvoton Direct][1]
+
+## 6. Resources
+* [Board Introduction][2]
+* [Download Board Schematics][3]
+* [Download MCU TRM][4]
+
+  [1]: https://direct.nuvoton.com/en/numaker-m2354
+  [2]: https://www.nuvoton.com/board/numaker-m2354/index.html
+  [3]: https://www.nuvoton.com/resource-download.jsp?tp_GUID=HL1020201102161956
+  [4]: https://www.nuvoton.com/resource-download.jsp?tp_GUID=DA05-M2354
diff --git a/bsp/nuvoton/numaker-m2354/SConscript b/bsp/nuvoton/numaker-m2354/SConscript
new file mode 100644
index 0000000000..fe0ae941ae
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/nuvoton/numaker-m2354/SConstruct b/bsp/nuvoton/numaker-m2354/SConstruct
new file mode 100644
index 0000000000..4f80ca57dc
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/SConstruct
@@ -0,0 +1,59 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+nuvoton_library = 'm2354'
+rtconfig.BSP_LIBRARY_TYPE = nuvoton_library
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, nuvoton_library, 'SConscript')))
+
+# include nu_pkgs
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'nu_packages', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/stm32/stm32f103-mini-system/applications/SConscript b/bsp/nuvoton/numaker-m2354/applications/SConscript
similarity index 56%
rename from bsp/stm32/stm32f103-mini-system/applications/SConscript
rename to bsp/nuvoton/numaker-m2354/applications/SConscript
index ef1c39fd83..9ffdbcd0f9 100644
--- a/bsp/stm32/stm32f103-mini-system/applications/SConscript
+++ b/bsp/nuvoton/numaker-m2354/applications/SConscript
@@ -1,10 +1,10 @@
-Import('RTT_ROOT')
-Import('rtconfig')
+# RT-Thread building script for component
+
 from building import *
 
 cwd = GetCurrentDir()
-src = Glob('*.c')
-CPPPATH = [cwd, ]
+src = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd, str(Dir('#'))]
 
 group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
 
diff --git a/bsp/nuvoton/numaker-m2354/applications/main.c b/bsp/nuvoton/numaker-m2354/applications/main.c
new file mode 100644
index 0000000000..d234a7f725
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/applications/main.c
@@ -0,0 +1,36 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author       Notes
+* 2020-8-26       Wayne        First version
+*
+******************************************************************************/
+
+#include 
+#include 
+#include 
+
+/* defined the LEDR pin: PD3 */
+#define LEDR   NU_GET_PININDEX(NU_PD, 3)
+
+int main(int argc, char **argv)
+{
+#if defined(RT_USING_PIN)
+    int counter = 100;
+    /* set LEDR pin mode to output */
+    rt_pin_mode(LEDR, PIN_MODE_OUTPUT);
+
+    while (counter--)
+    {
+        rt_pin_write(LEDR, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LEDR, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+#endif
+    return 0;
+}
diff --git a/bsp/nuvoton/numaker-m2354/applications/mnt.c b/bsp/nuvoton/numaker-m2354/applications/mnt.c
new file mode 100644
index 0000000000..6762e067b1
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/applications/mnt.c
@@ -0,0 +1,12 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author       Notes
+* 2020-8-26       Wayne        First version
+*
+******************************************************************************/
+
diff --git a/bsp/nuvoton/numaker-m2354/board/Kconfig b/bsp/nuvoton/numaker-m2354/board/Kconfig
new file mode 100644
index 0000000000..a3e751aa42
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/board/Kconfig
@@ -0,0 +1,71 @@
+menu "Hardware Drivers Config"
+
+    menu "On-chip Peripheral Drivers"
+        source "$BSP_DIR/../libraries/m2354/rtt_port/Kconfig"
+    endmenu
+
+    menu "On-board Peripheral Drivers"
+
+        config BSP_USING_NULINKME
+            bool "Enable UART0 for RTT Console.(uart0)"
+            select BSP_USING_UART
+            select BSP_USING_UART0
+            default y
+        config BOARD_USING_ESP8266
+            bool "ESP8266 Wi-Fi module supporting(over uart4)"
+            select BSP_USING_UART
+            select BSP_USING_UART4
+            select BSP_USING_UART4_RX_DMA
+            select BSP_USING_UART4_TX_DMA
+            select PKG_USING_AT_DEVICE
+            select AT_DEVICE_USING_ESP8266
+            select AT_DEVICE_ESP8266_INIT_ASYN
+            default n
+
+        config BOARD_USING_STORAGE_SDCARD
+            bool "SDCARD supporting.(over sdh0)"
+            select BSP_USING_SDH
+            select BSP_USING_SDH0
+            default n
+
+        choice
+            prompt "Select FS USB Ports"
+
+            config BOARD_USING_USBD
+                select BSP_USING_USBD
+                bool "Enable USBD(over USB1.1)"
+                help
+                    Choose this option if you need USBD function mode.
+
+            config BOARD_USING_USBH
+                select BSP_USING_USBH
+                bool "Enable USBH(over USB1.1)"
+                help
+                    Choose this option if you need USBH function mode.
+
+            config BOARD_USING_OTG
+                select BSP_USING_OTG
+                bool "Enable OTG(over USB1.1)"
+                help
+                    Choose this option if you need OTG function mode.
+
+            config BOARD_USING_USB_NONE
+                select BSP_USING_USB_NONE
+                bool "Disable USB1.1 port"
+                help
+                    Choose this option if you need not USB function.
+
+        endchoice
+
+
+    endmenu
+
+    menu "Board extended module drivers"
+        config BOARD_USING_SEGMENT_LCD
+            bool "Segment LCD supporting.(over lcd)"
+            select BSP_USING_SLCD
+            default n
+
+    endmenu
+
+endmenu
diff --git a/bsp/nuvoton/numaker-m2354/board/NuClockConfig/nutool_clkcfg.h b/bsp/nuvoton/numaker-m2354/board/NuClockConfig/nutool_clkcfg.h
new file mode 100644
index 0000000000..757323f65d
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/board/NuClockConfig/nutool_clkcfg.h
@@ -0,0 +1,27 @@
+/****************************************************************************
+ * @file     nutool_clkcfg.h
+ * @version  V1.05
+ * @Date     2020/11/11-11:43:32 
+ * @brief    NuMicro generated code file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#ifndef __NUTOOL_CLKCFG_H__
+#define __NUTOOL_CLKCFG_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+#undef  __HXT
+#define __HXT         (12000000UL)  /*!< High Speed External Crystal Clock Frequency */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*__NUTOOL_CLKCFG_H__*/
+
+/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/numaker-m2354/board/NuClockConfig/nutool_modclkcfg.c b/bsp/nuvoton/numaker-m2354/board/NuClockConfig/nutool_modclkcfg.c
new file mode 100644
index 0000000000..ea2c7a2f3a
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/board/NuClockConfig/nutool_modclkcfg.c
@@ -0,0 +1,1409 @@
+/****************************************************************************
+ * @file     nutool_modclkcfg.c
+ * @version  V1.05
+ * @Date     2020/11/11-11:43:32 
+ * @brief    NuMicro generated code file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+/********************
+MCU:M2354KJFAE(LQFP128)
+Base Clocks:
+HIRC:12MHz
+HIRC48:48MHz
+MIRC:4MHz
+LXT:32.7680kHz
+HXT:12MHz
+PLL:96MHz
+HCLK:96MHz
+PCLK0:96MHz
+PCLK1:96MHz
+Enabled-Module Frequencies:
+ACMP01=Bus Clock(PCLK1):96MHz
+BPWM0=Bus Clock(PCLK0):96MHz/Engine Clock:96MHz
+BPWM1=Bus Clock(PCLK1):96MHz/Engine Clock:96MHz
+CAN0=Bus Clock(PCLK0):96MHz
+CRC=Bus Clock(HCLK):96MHz
+CRPT=Bus Clock(HCLK):96MHz
+DAC=Bus Clock(PCLK1):96MHz
+EADC=Bus Clock(PCLK0):96MHz/Engine Clock:96MHz
+EBI=Bus Clock(HCLK):96MHz
+ECAP0=Bus Clock(PCLK0):96MHz
+ECAP1=Bus Clock(PCLK1):96MHz
+EPWM0=Bus Clock(PCLK0):96MHz/Engine Clock:96MHz
+EPWM1=Bus Clock(PCLK1):96MHz/Engine Clock:96MHz
+EWDT=Bus Clock(PCLK0):96MHz/Engine Clock:32.7680kHz
+EWWDT=Bus Clock(PCLK0):96MHz/Engine Clock:46.8750kHz
+FMCIDLE=Bus Clock(HCLK):96MHz/Engine Clock:12MHz
+GPA=Bus Clock(HCLK):96MHz
+GPB=Bus Clock(HCLK):96MHz
+GPC=Bus Clock(HCLK):96MHz
+GPD=Bus Clock(HCLK):96MHz
+GPE=Bus Clock(HCLK):96MHz
+GPF=Bus Clock(HCLK):96MHz
+GPG=Bus Clock(HCLK):96MHz
+GPH=Bus Clock(HCLK):96MHz
+I2C0=Bus Clock(PCLK0):96MHz
+I2C1=Bus Clock(PCLK1):96MHz
+I2C2=Bus Clock(PCLK0):96MHz
+I2S0=Bus Clock(PCLK0):96MHz/Engine Clock:96MHz
+ISP=Bus Clock(HCLK):96MHz/Engine Clock:12MHz
+KS=Bus Clock(HCLK):96MHz
+LCD=Bus Clock(PCLK1):96MHz/Engine Clock:32.7680kHz
+OTG=Bus Clock(PCLK1):96MHz/Engine Clock:48MHz
+PDMA0=Bus Clock(HCLK):96MHz
+PDMA1=Bus Clock(HCLK):96MHz
+QEI0=Bus Clock(PCLK0):96MHz
+QEI1=Bus Clock(PCLK1):96MHz
+QSPI0=Bus Clock(PCLK0):96MHz/Engine Clock:96MHz
+RTC=Bus Clock(PCLK0):96MHz/Engine Clock:32.7680kHz
+SC0=Bus Clock(PCLK0):96MHz/Engine Clock:12MHz
+SC1=Bus Clock(PCLK1):96MHz/Engine Clock:12MHz
+SC2=Bus Clock(PCLK0):96MHz/Engine Clock:12MHz
+SDH0=Bus Clock(HCLK):96MHz/Engine Clock:96MHz
+SPI0=Bus Clock(PCLK1):96MHz/Engine Clock:96MHz
+SPI1=Bus Clock(PCLK0):96MHz/Engine Clock:96MHz
+SPI2=Bus Clock(PCLK1):96MHz/Engine Clock:96MHz
+SPI3=Bus Clock(PCLK0):96MHz/Engine Clock:96MHz
+SRAM0=Bus Clock(HCLK):96MHz
+SRAM1=Bus Clock(HCLK):96MHz
+SRAM2=Bus Clock(HCLK):96MHz
+SYSTICK=Bus Clock(HCLK):96MHz/Engine Clock:96MHz
+TAMPER=Bus Clock(PCLK0):96MHz
+TMR0=Bus Clock(PCLK0):96MHz/Engine Clock:12MHz
+TMR1=Bus Clock(PCLK0):96MHz/Engine Clock:12MHz
+TMR2=Bus Clock(PCLK1):96MHz/Engine Clock:12MHz
+TMR3=Bus Clock(PCLK1):96MHz/Engine Clock:12MHz
+TMR4=Bus Clock(PCLK0):96MHz/Engine Clock:12MHz
+TMR5=Bus Clock(PCLK0):96MHz/Engine Clock:12MHz
+TRNG=Bus Clock(PCLK0):96MHz/Engine Clock:32.7680kHz
+UART0=Bus Clock(PCLK0):96MHz/Engine Clock:12MHz
+UART1=Bus Clock(PCLK1):96MHz/Engine Clock:12MHz
+UART2=Bus Clock(PCLK0):96MHz/Engine Clock:12MHz
+UART3=Bus Clock(PCLK1):96MHz/Engine Clock:12MHz
+UART4=Bus Clock(PCLK0):96MHz/Engine Clock:12MHz
+UART5=Bus Clock(PCLK1):96MHz/Engine Clock:12MHz
+USBD=Bus Clock(PCLK0):96MHz/Engine Clock:48MHz
+USBH=Bus Clock(HCLK):96MHz/Engine Clock:48MHz
+USCI0=Bus Clock(PCLK0):96MHz
+USCI1=Bus Clock(PCLK1):96MHz
+WDT=Bus Clock(PCLK0):96MHz/Engine Clock:32.7680kHz
+WWDT=Bus Clock(PCLK0):96MHz/Engine Clock:46.8750kHz
+********************/
+
+#include "M2354.h"
+#include "rtconfig.h"
+
+void nutool_modclkcfg_init_acmp01(void)
+{
+    CLK_EnableModuleClock(ACMP01_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_acmp01(void)
+{
+    CLK_DisableModuleClock(ACMP01_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_bpwm0(void)
+{
+    CLK_EnableModuleClock(BPWM0_MODULE);
+    CLK_SetModuleClock(BPWM0_MODULE, CLK_CLKSEL2_BPWM0SEL_PCLK0, MODULE_NoMsk);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_bpwm0(void)
+{
+    CLK_DisableModuleClock(BPWM0_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_bpwm1(void)
+{
+    CLK_EnableModuleClock(BPWM1_MODULE);
+    CLK_SetModuleClock(BPWM1_MODULE, CLK_CLKSEL2_BPWM1SEL_PCLK1, MODULE_NoMsk);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_bpwm1(void)
+{
+    CLK_DisableModuleClock(BPWM1_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_can0(void)
+{
+    CLK_EnableModuleClock(CAN0_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_can0(void)
+{
+    CLK_DisableModuleClock(CAN0_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_crc(void)
+{
+    CLK_EnableModuleClock(CRC_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_crc(void)
+{
+    CLK_DisableModuleClock(CRC_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_crpt(void)
+{
+    CLK_EnableModuleClock(CRPT_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_crpt(void)
+{
+    CLK_DisableModuleClock(CRPT_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_dac(void)
+{
+    CLK_EnableModuleClock(DAC_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_dac(void)
+{
+    CLK_DisableModuleClock(DAC_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_eadc(void)
+{
+    CLK_EnableModuleClock(EADC_MODULE);
+    CLK_SetModuleClock(EADC_MODULE, MODULE_NoMsk, CLK_CLKDIV0_EADC(8));
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_eadc(void)
+{
+    CLK_DisableModuleClock(EADC_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_ebi(void)
+{
+    CLK_EnableModuleClock(EBI_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_ebi(void)
+{
+    CLK_DisableModuleClock(EBI_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_ecap0(void)
+{
+    CLK_EnableModuleClock(ECAP0_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_ecap0(void)
+{
+    CLK_DisableModuleClock(ECAP0_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_ecap1(void)
+{
+    CLK_EnableModuleClock(ECAP1_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_ecap1(void)
+{
+    CLK_DisableModuleClock(ECAP1_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_epwm0(void)
+{
+    CLK_EnableModuleClock(EPWM0_MODULE);
+    CLK_SetModuleClock(EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PCLK0, MODULE_NoMsk);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_epwm0(void)
+{
+    CLK_DisableModuleClock(EPWM0_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_epwm1(void)
+{
+    CLK_EnableModuleClock(EPWM1_MODULE);
+    CLK_SetModuleClock(EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PCLK1, MODULE_NoMsk);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_epwm1(void)
+{
+    CLK_DisableModuleClock(EPWM1_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_ewdt(void)
+{
+    CLK_EnableModuleClock(EWDT_MODULE);
+    CLK_SetModuleClock(EWDT_MODULE, CLK_CLKSEL1_EWDTSEL_LXT, MODULE_NoMsk);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_ewdt(void)
+{
+    CLK_DisableModuleClock(EWDT_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_ewwdt(void)
+{
+    CLK_EnableModuleClock(EWWDT_MODULE);
+    CLK_SetModuleClock(EWWDT_MODULE, CLK_CLKSEL1_EWWDTSEL_HCLK_DIV2048, MODULE_NoMsk);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_ewwdt(void)
+{
+    CLK_DisableModuleClock(EWWDT_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_exst(void)
+{
+    CLK_EnableModuleClock(EXST_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_exst(void)
+{
+    CLK_DisableModuleClock(EXST_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_fmcidle(void)
+{
+    CLK_EnableModuleClock(FMCIDLE_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_fmcidle(void)
+{
+    CLK_DisableModuleClock(FMCIDLE_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_gpa(void)
+{
+    CLK_EnableModuleClock(GPA_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_gpa(void)
+{
+    CLK_DisableModuleClock(GPA_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_gpb(void)
+{
+    CLK_EnableModuleClock(GPB_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_gpb(void)
+{
+    CLK_DisableModuleClock(GPB_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_gpc(void)
+{
+    CLK_EnableModuleClock(GPC_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_gpc(void)
+{
+    CLK_DisableModuleClock(GPC_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_gpd(void)
+{
+    CLK_EnableModuleClock(GPD_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_gpd(void)
+{
+    CLK_DisableModuleClock(GPD_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_gpe(void)
+{
+    CLK_EnableModuleClock(GPE_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_gpe(void)
+{
+    CLK_DisableModuleClock(GPE_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_gpf(void)
+{
+    CLK_EnableModuleClock(GPF_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_gpf(void)
+{
+    CLK_DisableModuleClock(GPF_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_gpg(void)
+{
+    CLK_EnableModuleClock(GPG_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_gpg(void)
+{
+    CLK_DisableModuleClock(GPG_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_gph(void)
+{
+    CLK_EnableModuleClock(GPH_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_gph(void)
+{
+    CLK_DisableModuleClock(GPH_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_i2c0(void)
+{
+    CLK_EnableModuleClock(I2C0_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_i2c0(void)
+{
+    CLK_DisableModuleClock(I2C0_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_i2c1(void)
+{
+    CLK_EnableModuleClock(I2C1_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_i2c1(void)
+{
+    CLK_DisableModuleClock(I2C1_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_i2c2(void)
+{
+    CLK_EnableModuleClock(I2C2_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_i2c2(void)
+{
+    CLK_DisableModuleClock(I2C2_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_i2s0(void)
+{
+    CLK_EnableModuleClock(I2S0_MODULE);
+    CLK_SetModuleClock(I2S0_MODULE, CLK_CLKSEL3_I2S0SEL_PCLK0, MODULE_NoMsk);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_i2s0(void)
+{
+    CLK_DisableModuleClock(I2S0_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_isp(void)
+{
+    CLK_EnableModuleClock(ISP_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_isp(void)
+{
+    CLK_DisableModuleClock(ISP_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_ks(void)
+{
+    CLK_EnableModuleClock(KS_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_ks(void)
+{
+    CLK_DisableModuleClock(KS_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_lcd(void)
+{
+    CLK_EnableModuleClock(LCD_MODULE);
+    CLK_SetModuleClock(LCD_MODULE, CLK_CLKSEL1_LCDSEL_LXT, MODULE_NoMsk);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_lcd(void)
+{
+    CLK_DisableModuleClock(LCD_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_lcdcp(void)
+{
+    CLK_EnableModuleClock(LCDCP_MODULE);
+    CLK_SetModuleClock(LCDCP_MODULE, CLK_CLKSEL1_LCDCPSEL_MIRC, MODULE_NoMsk);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_lcdcp(void)
+{
+    CLK_DisableModuleClock(LCDCP_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_otg(void)
+{
+    CLK_EnableModuleClock(OTG_MODULE);
+    CLK_SetModuleClock(OTG_MODULE, CLK_CLKSEL0_USBSEL_PLL, CLK_CLKDIV0_USB(2));
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_otg(void)
+{
+    CLK_DisableModuleClock(OTG_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_pdma0(void)
+{
+    CLK_EnableModuleClock(PDMA0_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_pdma0(void)
+{
+    CLK_DisableModuleClock(PDMA0_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_pdma1(void)
+{
+    CLK_EnableModuleClock(PDMA1_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_pdma1(void)
+{
+    CLK_DisableModuleClock(PDMA1_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_qei0(void)
+{
+    CLK_EnableModuleClock(QEI0_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_qei0(void)
+{
+    CLK_DisableModuleClock(QEI0_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_qei1(void)
+{
+    CLK_EnableModuleClock(QEI1_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_qei1(void)
+{
+    CLK_DisableModuleClock(QEI1_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_qspi0(void)
+{
+    CLK_EnableModuleClock(QSPI0_MODULE);
+    CLK_SetModuleClock(QSPI0_MODULE, CLK_CLKSEL2_QSPI0SEL_PCLK0, MODULE_NoMsk);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_qspi0(void)
+{
+    CLK_DisableModuleClock(QSPI0_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_rtc(void)
+{
+    CLK_EnableModuleClock(RTC_MODULE);
+    RTC->LXTCTL = RTC->LXTCTL & ~RTC_LXTCTL_RTCCKSEL_Msk;
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_rtc(void)
+{
+    CLK_DisableModuleClock(RTC_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_sc0(void)
+{
+    CLK_EnableModuleClock(SC0_MODULE);
+    CLK_SetModuleClock(SC0_MODULE, CLK_CLKSEL3_SC0SEL_HXT, CLK_CLKDIV1_SC0(1));
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_sc0(void)
+{
+    CLK_DisableModuleClock(SC0_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_sc1(void)
+{
+    CLK_EnableModuleClock(SC1_MODULE);
+    CLK_SetModuleClock(SC1_MODULE, CLK_CLKSEL3_SC1SEL_HXT, CLK_CLKDIV1_SC1(1));
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_sc1(void)
+{
+    CLK_DisableModuleClock(SC1_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_sc2(void)
+{
+    CLK_EnableModuleClock(SC2_MODULE);
+    CLK_SetModuleClock(SC2_MODULE, CLK_CLKSEL3_SC2SEL_HXT, CLK_CLKDIV1_SC2(1));
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_sc2(void)
+{
+    CLK_DisableModuleClock(SC2_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_sdh0(void)
+{
+    CLK_EnableModuleClock(SDH0_MODULE);
+    CLK_SetModuleClock(SDH0_MODULE, CLK_CLKSEL0_SDH0SEL_HCLK, CLK_CLKDIV0_SDH0(1));
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_sdh0(void)
+{
+    CLK_DisableModuleClock(SDH0_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_spi0(void)
+{
+    CLK_EnableModuleClock(SPI0_MODULE);
+    CLK_SetModuleClock(SPI0_MODULE, CLK_CLKSEL2_SPI0SEL_PCLK1, MODULE_NoMsk);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_spi0(void)
+{
+    CLK_DisableModuleClock(SPI0_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_spi1(void)
+{
+    CLK_EnableModuleClock(SPI1_MODULE);
+    CLK_SetModuleClock(SPI1_MODULE, CLK_CLKSEL2_SPI1SEL_PCLK0, MODULE_NoMsk);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_spi1(void)
+{
+    CLK_DisableModuleClock(SPI1_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_spi2(void)
+{
+    CLK_EnableModuleClock(SPI2_MODULE);
+    CLK_SetModuleClock(SPI2_MODULE, CLK_CLKSEL2_SPI2SEL_PCLK1, MODULE_NoMsk);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_spi2(void)
+{
+    CLK_DisableModuleClock(SPI2_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_spi3(void)
+{
+    CLK_EnableModuleClock(SPI3_MODULE);
+    CLK_SetModuleClock(SPI3_MODULE, CLK_CLKSEL2_SPI3SEL_PCLK0, MODULE_NoMsk);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_spi3(void)
+{
+    CLK_DisableModuleClock(SPI3_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_sram0(void)
+{
+    CLK_EnableModuleClock(SRAM0_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_sram0(void)
+{
+    CLK_DisableModuleClock(SRAM0_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_sram1(void)
+{
+    CLK_EnableModuleClock(SRAM1_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_sram1(void)
+{
+    CLK_DisableModuleClock(SRAM1_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_sram2(void)
+{
+    CLK_EnableModuleClock(SRAM2_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_sram2(void)
+{
+    CLK_DisableModuleClock(SRAM2_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_systick(void)
+{
+    CLK_EnableSysTick(CLK_CLKSEL0_STCLKSEL_HCLK, 0);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_systick(void)
+{
+    CLK_DisableSysTick();
+
+    return;
+}
+
+void nutool_modclkcfg_init_tamper(void)
+{
+    CLK_EnableModuleClock(TAMPER_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_tamper(void)
+{
+    CLK_DisableModuleClock(TAMPER_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_tmr0(void)
+{
+    CLK_EnableModuleClock(TMR0_MODULE);
+    CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_HXT, MODULE_NoMsk);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_tmr0(void)
+{
+    CLK_DisableModuleClock(TMR0_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_tmr1(void)
+{
+    CLK_EnableModuleClock(TMR1_MODULE);
+    CLK_SetModuleClock(TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_HXT, MODULE_NoMsk);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_tmr1(void)
+{
+    CLK_DisableModuleClock(TMR1_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_tmr2(void)
+{
+    CLK_EnableModuleClock(TMR2_MODULE);
+    CLK_SetModuleClock(TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_HXT, MODULE_NoMsk);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_tmr2(void)
+{
+    CLK_DisableModuleClock(TMR2_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_tmr3(void)
+{
+    CLK_EnableModuleClock(TMR3_MODULE);
+    CLK_SetModuleClock(TMR3_MODULE, CLK_CLKSEL1_TMR3SEL_HXT, MODULE_NoMsk);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_tmr3(void)
+{
+    CLK_DisableModuleClock(TMR3_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_tmr4(void)
+{
+    CLK_EnableModuleClock(TMR4_MODULE);
+    CLK_SetModuleClock(TMR4_MODULE, CLK_CLKSEL3_TMR4SEL_HXT, MODULE_NoMsk);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_tmr4(void)
+{
+    CLK_DisableModuleClock(TMR4_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_tmr5(void)
+{
+    CLK_EnableModuleClock(TMR5_MODULE);
+    CLK_SetModuleClock(TMR5_MODULE, CLK_CLKSEL3_TMR5SEL_HXT, MODULE_NoMsk);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_tmr5(void)
+{
+    CLK_DisableModuleClock(TMR5_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_trace(void)
+{
+    CLK_EnableModuleClock(TRACE_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_trace(void)
+{
+    CLK_DisableModuleClock(TRACE_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_trng(void)
+{
+    CLK_EnableModuleClock(TRNG_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_trng(void)
+{
+    CLK_DisableModuleClock(TRNG_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_uart0(void)
+{
+    CLK_EnableModuleClock(UART0_MODULE);
+    CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL2_UART0SEL_HXT, CLK_CLKDIV0_UART0(1));
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_uart0(void)
+{
+    CLK_DisableModuleClock(UART0_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_uart1(void)
+{
+    CLK_EnableModuleClock(UART1_MODULE);
+    CLK_SetModuleClock(UART1_MODULE, CLK_CLKSEL2_UART1SEL_HXT, CLK_CLKDIV0_UART1(1));
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_uart1(void)
+{
+    CLK_DisableModuleClock(UART1_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_uart2(void)
+{
+    CLK_EnableModuleClock(UART2_MODULE);
+    CLK_SetModuleClock(UART2_MODULE, CLK_CLKSEL2_UART2SEL_HXT, CLK_CLKDIV4_UART2(1));
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_uart2(void)
+{
+    CLK_DisableModuleClock(UART2_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_uart3(void)
+{
+    CLK_EnableModuleClock(UART3_MODULE);
+    CLK_SetModuleClock(UART3_MODULE, CLK_CLKSEL2_UART3SEL_HXT, CLK_CLKDIV4_UART3(1));
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_uart3(void)
+{
+    CLK_DisableModuleClock(UART3_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_uart4(void)
+{
+    CLK_EnableModuleClock(UART4_MODULE);
+    CLK_SetModuleClock(UART4_MODULE, CLK_CLKSEL3_UART4SEL_HXT, CLK_CLKDIV4_UART4(1));
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_uart4(void)
+{
+    CLK_DisableModuleClock(UART4_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_uart5(void)
+{
+    CLK_EnableModuleClock(UART5_MODULE);
+    CLK_SetModuleClock(UART5_MODULE, CLK_CLKSEL3_UART5SEL_HXT, CLK_CLKDIV4_UART5(1));
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_uart5(void)
+{
+    CLK_DisableModuleClock(UART5_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_usbd(void)
+{
+    CLK_EnableModuleClock(USBD_MODULE);
+    CLK_SetModuleClock(USBD_MODULE, CLK_CLKSEL0_USBSEL_HIRC48, CLK_CLKDIV0_USB(1));
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_usbd(void)
+{
+    CLK_DisableModuleClock(USBD_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_usbh(void)
+{
+    CLK_EnableModuleClock(USBH_MODULE);
+    CLK_SetModuleClock(USBH_MODULE, CLK_CLKSEL0_USBSEL_HIRC48, CLK_CLKDIV0_USB(1));
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_usbh(void)
+{
+    CLK_DisableModuleClock(USBH_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_usci0(void)
+{
+    CLK_EnableModuleClock(USCI0_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_usci0(void)
+{
+    CLK_DisableModuleClock(USCI0_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_usci1(void)
+{
+    CLK_EnableModuleClock(USCI1_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_usci1(void)
+{
+    CLK_DisableModuleClock(USCI1_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_wdt(void)
+{
+    CLK_EnableModuleClock(WDT_MODULE);
+    CLK_SetModuleClock(WDT_MODULE, CLK_CLKSEL1_WDTSEL_LXT, MODULE_NoMsk);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_wdt(void)
+{
+    CLK_DisableModuleClock(WDT_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_wwdt(void)
+{
+    CLK_EnableModuleClock(WWDT_MODULE);
+    CLK_SetModuleClock(WWDT_MODULE, CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048, MODULE_NoMsk);
+
+    return;
+}
+
+void nutool_modclkcfg_deinit_wwdt(void)
+{
+    CLK_DisableModuleClock(WWDT_MODULE);
+
+    return;
+}
+
+void nutool_modclkcfg_init_base(void)
+{
+    /* LXT source from external LXT */
+    CLK_EnableModuleClock(RTC_MODULE);
+    RTC->LXTCTL &= ~(RTC_LXTCTL_LIRC32KEN_Msk|RTC_LXTCTL_C32KSEL_Msk);
+    CLK_DisableModuleClock(RTC_MODULE);
+
+    /* Enable clock source */
+    CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk|CLK_PWRCTL_LXTEN_Msk|CLK_PWRCTL_HXTEN_Msk|CLK_PWRCTL_HIRC48EN_Msk|CLK_PWRCTL_MIRCEN_Msk);
+
+    /* Waiting for clock source ready */
+    CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk|CLK_STATUS_LXTSTB_Msk|CLK_STATUS_HXTSTB_Msk|CLK_STATUS_HIRC48STB_Msk|CLK_STATUS_MIRCSTB_Msk);
+
+    /* Disable PLL first to avoid unstable when setting PLL */
+    CLK_DisablePLL();
+
+    /* Set PLL frequency */
+    /* Set core clock as PLL_CLOCK from PLL */
+    CLK_SetCoreClock(FREQ_96MHZ);
+
+    /* Waiting for PLL ready */
+    CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
+
+    /* If the defines do not exist in your project, please refer to the related clk.h in the Header folder appended to the tool package. */
+    /* Set HCLK clock */
+    CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(1));
+
+    return;
+}
+
+void nutool_modclkcfg_init(void)
+{
+    /*---------------------------------------------------------------------------------------------------------*/
+    /* Init System Clock                                                                                       */
+    /*---------------------------------------------------------------------------------------------------------*/
+    //RTC->LXTCTL = (RTC->LXTCTL & ~(0x000000C1UL)) | 0x0000000EUL;
+    //CLK->PWRCTL = (CLK->PWRCTL & ~(0x0034000FUL)) | 0x00240007UL;
+    //CLK->PLLCTL = (CLK->PLLCTL & ~(0x000BFFFFUL)) | 0x00000206UL;
+    //CLK->CLKDIV0 = (CLK->CLKDIV0 & ~(0xFFFFFFFFUL)) | 0x00000010UL;
+    //CLK->CLKDIV1 = (CLK->CLKDIV1 & ~(0x00FFFFFFUL)) | 0x00000000UL;
+    //CLK->CLKDIV4 = (CLK->CLKDIV4 & ~(0x0000FFFFUL)) | 0x00000000UL;
+    //CLK->PCLKDIV = (CLK->PCLKDIV & ~(0x00000077UL)) | 0x00000000UL;
+    //CLK->CLKSEL0 = (CLK->CLKSEL0 & ~(0x0030013FUL)) | 0x0020011AUL;
+    //CLK->CLKSEL1 = (CLK->CLKSEL1 & ~(0xF07777FFUL)) | 0xB000009DUL;
+    //CLK->CLKSEL2 = (CLK->CLKSEL2 & ~(0x77773FFFUL)) | 0x00002BABUL;
+    //CLK->CLKSEL3 = (CLK->CLKSEL3 & ~(0x7703773FUL)) | 0x00020000UL;
+    //CLK->AHBCLK = (CLK->AHBCLK & ~(0xFF71F0DFUL)) | 0xFFFFFFFFUL;
+    //CLK->APBCLK0 = (CLK->APBCLK0 & ~(0xBD7FF7FFUL)) | 0xFFFFFFFFUL;
+    //CLK->APBCLK1 = (CLK->APBCLK1 & ~(0x1FCF1377UL)) | 0xFFFFFFFFUL;
+    //CLK->CLKOCTL = (CLK->CLKOCTL & ~(0x0000007FUL)) | 0x00000000UL;
+    //SysTick->CTRL = (SysTick->CTRL & ~(0x00000005UL)) | 0x00000005UL;
+
+    /* Unlock protected registers */
+    SYS_UnlockReg();
+
+    /* Enable base clock */
+    nutool_modclkcfg_init_base();
+
+    /* Enable module clock and set clock source */
+    nutool_modclkcfg_init_sram0();
+    nutool_modclkcfg_init_sram1();
+    nutool_modclkcfg_init_sram2();
+    nutool_modclkcfg_init_systick();
+
+#if defined(BSP_USING_ACMP01)
+    nutool_modclkcfg_init_acmp01();
+#endif
+#if defined(BSP_USING_BPWM0)
+    nutool_modclkcfg_init_bpwm0();
+#endif
+#if defined(BSP_USING_BPWM1)
+    nutool_modclkcfg_init_bpwm1();
+#endif
+#if defined(BSP_USING_CAN0)
+    nutool_modclkcfg_init_can0();
+#endif
+#if defined(BSP_USING_CRC)
+    nutool_modclkcfg_init_crc();
+#endif
+#if defined(BSP_USING_CRYPTO)
+    nutool_modclkcfg_init_crpt();
+#endif
+#if defined(BSP_USING_DAC)
+    nutool_modclkcfg_init_dac();
+#endif
+#if defined(BSP_USING_EADC)
+    nutool_modclkcfg_init_eadc();
+#endif
+#if defined(BSP_USING_EBI)
+    nutool_modclkcfg_init_ebi();
+#endif
+#if defined(BSP_USING_ECAP0)
+    nutool_modclkcfg_init_ecap0();
+#endif
+#if defined(BSP_USING_ECAP1)
+    nutool_modclkcfg_init_ecap1();
+#endif
+#if defined(BSP_USING_EPWM0)
+    nutool_modclkcfg_init_epwm0();
+#endif
+#if defined(BSP_USING_EPWM1)
+    nutool_modclkcfg_init_epwm1();
+#endif
+    /*nutool_modclkcfg_init_ewdt();*/
+    /*nutool_modclkcfg_init_ewwdt();*/
+    /*nutool_modclkcfg_init_exst();*/
+#if defined(BSP_USING_FMC)
+    nutool_modclkcfg_init_fmcidle();
+    nutool_modclkcfg_init_isp();
+#endif
+#if defined(BSP_USING_GPIO)
+    nutool_modclkcfg_init_gpa();
+    nutool_modclkcfg_init_gpb();
+    nutool_modclkcfg_init_gpc();
+    nutool_modclkcfg_init_gpd();
+    nutool_modclkcfg_init_gpe();
+    nutool_modclkcfg_init_gpf();
+    nutool_modclkcfg_init_gpg();
+    nutool_modclkcfg_init_gph();
+#endif
+#if defined(BSP_USING_I2C0)
+    nutool_modclkcfg_init_i2c0();
+#endif
+#if defined(BSP_USING_I2C1)
+    nutool_modclkcfg_init_i2c1();
+#endif
+#if defined(BSP_USING_I2C2)
+    nutool_modclkcfg_init_i2c2();
+#endif
+#if defined(BSP_USING_I2S)
+    nutool_modclkcfg_init_i2s0();
+#endif
+    /*nutool_modclkcfg_init_ks();*/
+#if defined(BSP_USING_SLCD)
+    nutool_modclkcfg_init_lcd();
+    nutool_modclkcfg_init_lcdcp();
+#endif
+#if defined(BSP_USING_OTG) || defined(BSP_USING_USBH)
+    nutool_modclkcfg_init_otg();
+#endif
+#if defined(BSP_USING_PDMA)
+    nutool_modclkcfg_init_pdma0();
+    nutool_modclkcfg_init_pdma1();
+#endif
+#if defined(BSP_USING_QEI0)
+    nutool_modclkcfg_init_qei0();
+#endif
+#if defined(BSP_USING_QEI1)
+    nutool_modclkcfg_init_qei1();
+#endif
+#if defined(BSP_USING_QSPI0)
+    nutool_modclkcfg_init_qspi0();
+#endif
+#if defined(BSP_USING_RTC)
+    nutool_modclkcfg_init_rtc();
+#endif
+#if defined(BSP_USING_SCUART0)
+    nutool_modclkcfg_init_sc0();
+#endif
+#if defined(BSP_USING_SCUART1)
+    nutool_modclkcfg_init_sc1();
+#endif
+#if defined(BSP_USING_SCUART2)
+    nutool_modclkcfg_init_sc2();
+#endif
+#if defined(BSP_USING_SDH0)
+    nutool_modclkcfg_init_sdh0();
+#endif
+#if defined(BSP_USING_SPI0) || defined(BSP_USING_SPII2S0)
+    nutool_modclkcfg_init_spi0();
+#endif
+#if defined(BSP_USING_SPI1) || defined(BSP_USING_SPII2S1)
+    nutool_modclkcfg_init_spi1();
+#endif
+#if defined(BSP_USING_SPI2) || defined(BSP_USING_SPII2S2)
+    nutool_modclkcfg_init_spi2();
+#endif
+#if defined(BSP_USING_SPI3) || defined(BSP_USING_SPII2S3)
+    nutool_modclkcfg_init_spi3();
+#endif
+
+    /*nutool_modclkcfg_init_tamper();*/
+#if defined(BSP_USING_TMR0)
+    nutool_modclkcfg_init_tmr0();
+#endif
+#if defined(BSP_USING_TMR1)
+    nutool_modclkcfg_init_tmr1();
+#endif
+#if defined(BSP_USING_TMR2)
+    nutool_modclkcfg_init_tmr2();
+#endif
+#if defined(BSP_USING_TMR3)
+    nutool_modclkcfg_init_tmr3();
+#endif
+#if defined(BSP_USING_TMR4)
+    nutool_modclkcfg_init_tmr4();
+#endif
+#if defined(BSP_USING_TMR5)
+    nutool_modclkcfg_init_tmr5();
+#endif
+#if defined(BSP_USING_TRNG)
+    nutool_modclkcfg_init_trng();
+#endif
+#if defined(BSP_USING_UART0)
+    nutool_modclkcfg_init_uart0();
+#endif
+#if defined(BSP_USING_UART1)
+    nutool_modclkcfg_init_uart1();
+#endif
+#if defined(BSP_USING_UART2)
+    nutool_modclkcfg_init_uart2();
+#endif
+#if defined(BSP_USING_UART3)
+    nutool_modclkcfg_init_uart3();
+#endif
+#if defined(BSP_USING_UART4)
+    nutool_modclkcfg_init_uart4();
+#endif
+#if defined(BSP_USING_UART5)
+    nutool_modclkcfg_init_uart5();
+#endif
+#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH)
+    nutool_modclkcfg_init_usbd();
+#endif
+#if defined(BSP_USING_USBH)
+    nutool_modclkcfg_init_usbh();
+#endif
+#if defined(BSP_USING_USCI0)
+    nutool_modclkcfg_init_usci0();
+#endif
+#if defined(BSP_USING_USCI1)
+    nutool_modclkcfg_init_usci1();
+#endif
+#if defined(BSP_USING_WDT)
+    nutool_modclkcfg_init_wdt();
+#endif
+#if defined(BSP_USING_WWDT)
+    nutool_modclkcfg_init_wwdt();
+#endif
+
+    /* Update System Core Clock */
+    /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
+    SystemCoreClockUpdate();
+
+    /* Lock protected registers */
+    SYS_LockReg();
+
+    return;
+}
+
+/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/numaker-m2354/board/NuClockConfig/nutool_modclkcfg.cfg b/bsp/nuvoton/numaker-m2354/board/NuClockConfig/nutool_modclkcfg.cfg
new file mode 100644
index 0000000000..c1f49b4428
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/board/NuClockConfig/nutool_modclkcfg.cfg
@@ -0,0 +1,35 @@
+/****************************************************************************
+ * @file     nutool_modclkcfg.cfg
+ * @version  V1.05
+ * @Date     2020/11/11-11:43:32 
+ * @brief    NuMicro clock config file
+ *
+ * @note Please do not modify this file.
+ *       Otherwise, it may not be loaded successfully.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+MCU:M2354KJFAE(LQFP128)
+Reg:CLKDIV0 = 0x00000010
+Reg:CLKDIV1 = 0x00000000
+Reg:CLKDIV4 = 0x00000000
+Reg:PCLKDIV = 0x00000000
+Reg:CLKSEL0 = 0x0020011A
+Reg:CLKSEL1 = 0xB000009D
+Reg:CLKSEL2 = 0x00002BAB
+Reg:CLKSEL3 = 0x00020000
+Reg:PWRCTL = 0x00240007
+Reg:AHBCLK = 0xFFFFFFFF
+Reg:APBCLK0 = 0xFFFFFFFF
+Reg:APBCLK1 = 0xFFFFFFFF
+Reg:PLLCTL = 0x00000206
+Reg:CLKOCTL = 0x00000000
+Reg:SYST_CTRL = 0x00000005
+Reg:RTC_LXTCTL = 0x0000000E
+LXT:32768
+HXT:12000000
+PLL:96000000
+Step:4
+/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/numaker-m2354/board/NuClockConfig/nutool_modclkcfg.h b/bsp/nuvoton/numaker-m2354/board/NuClockConfig/nutool_modclkcfg.h
new file mode 100644
index 0000000000..704cd6adc1
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/board/NuClockConfig/nutool_modclkcfg.h
@@ -0,0 +1,172 @@
+/****************************************************************************
+ * @file     nutool_modclkcfg.h
+ * @version  V1.05
+ * @Date     2020/11/11-11:43:32 
+ * @brief    NuMicro generated code file
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#ifndef __NUTOOL_MODCLKCFG_H__
+#define __NUTOOL_MODCLKCFG_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+void nutool_modclkcfg_init_acmp01(void);
+void nutool_modclkcfg_deinit_acmp01(void);
+void nutool_modclkcfg_init_bpwm0(void);
+void nutool_modclkcfg_deinit_bpwm0(void);
+void nutool_modclkcfg_init_bpwm1(void);
+void nutool_modclkcfg_deinit_bpwm1(void);
+void nutool_modclkcfg_init_can0(void);
+void nutool_modclkcfg_deinit_can0(void);
+void nutool_modclkcfg_init_crc(void);
+void nutool_modclkcfg_deinit_crc(void);
+void nutool_modclkcfg_init_crpt(void);
+void nutool_modclkcfg_deinit_crpt(void);
+void nutool_modclkcfg_init_dac(void);
+void nutool_modclkcfg_deinit_dac(void);
+void nutool_modclkcfg_init_eadc(void);
+void nutool_modclkcfg_deinit_eadc(void);
+void nutool_modclkcfg_init_ebi(void);
+void nutool_modclkcfg_deinit_ebi(void);
+void nutool_modclkcfg_init_ecap0(void);
+void nutool_modclkcfg_deinit_ecap0(void);
+void nutool_modclkcfg_init_ecap1(void);
+void nutool_modclkcfg_deinit_ecap1(void);
+void nutool_modclkcfg_init_epwm0(void);
+void nutool_modclkcfg_deinit_epwm0(void);
+void nutool_modclkcfg_init_epwm1(void);
+void nutool_modclkcfg_deinit_epwm1(void);
+void nutool_modclkcfg_init_ewdt(void);
+void nutool_modclkcfg_deinit_ewdt(void);
+void nutool_modclkcfg_init_ewwdt(void);
+void nutool_modclkcfg_deinit_ewwdt(void);
+void nutool_modclkcfg_init_exst(void);
+void nutool_modclkcfg_deinit_exst(void);
+void nutool_modclkcfg_init_fmcidle(void);
+void nutool_modclkcfg_deinit_fmcidle(void);
+void nutool_modclkcfg_init_gpa(void);
+void nutool_modclkcfg_deinit_gpa(void);
+void nutool_modclkcfg_init_gpb(void);
+void nutool_modclkcfg_deinit_gpb(void);
+void nutool_modclkcfg_init_gpc(void);
+void nutool_modclkcfg_deinit_gpc(void);
+void nutool_modclkcfg_init_gpd(void);
+void nutool_modclkcfg_deinit_gpd(void);
+void nutool_modclkcfg_init_gpe(void);
+void nutool_modclkcfg_deinit_gpe(void);
+void nutool_modclkcfg_init_gpf(void);
+void nutool_modclkcfg_deinit_gpf(void);
+void nutool_modclkcfg_init_gpg(void);
+void nutool_modclkcfg_deinit_gpg(void);
+void nutool_modclkcfg_init_gph(void);
+void nutool_modclkcfg_deinit_gph(void);
+void nutool_modclkcfg_init_i2c0(void);
+void nutool_modclkcfg_deinit_i2c0(void);
+void nutool_modclkcfg_init_i2c1(void);
+void nutool_modclkcfg_deinit_i2c1(void);
+void nutool_modclkcfg_init_i2c2(void);
+void nutool_modclkcfg_deinit_i2c2(void);
+void nutool_modclkcfg_init_i2s0(void);
+void nutool_modclkcfg_deinit_i2s0(void);
+void nutool_modclkcfg_init_isp(void);
+void nutool_modclkcfg_deinit_isp(void);
+void nutool_modclkcfg_init_ks(void);
+void nutool_modclkcfg_deinit_ks(void);
+void nutool_modclkcfg_init_lcd(void);
+void nutool_modclkcfg_deinit_lcd(void);
+void nutool_modclkcfg_init_lcdcp(void);
+void nutool_modclkcfg_deinit_lcdcp(void);
+void nutool_modclkcfg_init_otg(void);
+void nutool_modclkcfg_deinit_otg(void);
+void nutool_modclkcfg_init_pdma0(void);
+void nutool_modclkcfg_deinit_pdma0(void);
+void nutool_modclkcfg_init_pdma1(void);
+void nutool_modclkcfg_deinit_pdma1(void);
+void nutool_modclkcfg_init_qei0(void);
+void nutool_modclkcfg_deinit_qei0(void);
+void nutool_modclkcfg_init_qei1(void);
+void nutool_modclkcfg_deinit_qei1(void);
+void nutool_modclkcfg_init_qspi0(void);
+void nutool_modclkcfg_deinit_qspi0(void);
+void nutool_modclkcfg_init_rtc(void);
+void nutool_modclkcfg_deinit_rtc(void);
+void nutool_modclkcfg_init_sc0(void);
+void nutool_modclkcfg_deinit_sc0(void);
+void nutool_modclkcfg_init_sc1(void);
+void nutool_modclkcfg_deinit_sc1(void);
+void nutool_modclkcfg_init_sc2(void);
+void nutool_modclkcfg_deinit_sc2(void);
+void nutool_modclkcfg_init_sdh0(void);
+void nutool_modclkcfg_deinit_sdh0(void);
+void nutool_modclkcfg_init_spi0(void);
+void nutool_modclkcfg_deinit_spi0(void);
+void nutool_modclkcfg_init_spi1(void);
+void nutool_modclkcfg_deinit_spi1(void);
+void nutool_modclkcfg_init_spi2(void);
+void nutool_modclkcfg_deinit_spi2(void);
+void nutool_modclkcfg_init_spi3(void);
+void nutool_modclkcfg_deinit_spi3(void);
+void nutool_modclkcfg_init_sram0(void);
+void nutool_modclkcfg_deinit_sram0(void);
+void nutool_modclkcfg_init_sram1(void);
+void nutool_modclkcfg_deinit_sram1(void);
+void nutool_modclkcfg_init_sram2(void);
+void nutool_modclkcfg_deinit_sram2(void);
+void nutool_modclkcfg_init_systick(void);
+void nutool_modclkcfg_deinit_systick(void);
+void nutool_modclkcfg_init_tamper(void);
+void nutool_modclkcfg_deinit_tamper(void);
+void nutool_modclkcfg_init_tmr0(void);
+void nutool_modclkcfg_deinit_tmr0(void);
+void nutool_modclkcfg_init_tmr1(void);
+void nutool_modclkcfg_deinit_tmr1(void);
+void nutool_modclkcfg_init_tmr2(void);
+void nutool_modclkcfg_deinit_tmr2(void);
+void nutool_modclkcfg_init_tmr3(void);
+void nutool_modclkcfg_deinit_tmr3(void);
+void nutool_modclkcfg_init_tmr4(void);
+void nutool_modclkcfg_deinit_tmr4(void);
+void nutool_modclkcfg_init_tmr5(void);
+void nutool_modclkcfg_deinit_tmr5(void);
+void nutool_modclkcfg_init_trace(void);
+void nutool_modclkcfg_deinit_trace(void);
+void nutool_modclkcfg_init_trng(void);
+void nutool_modclkcfg_deinit_trng(void);
+void nutool_modclkcfg_init_uart0(void);
+void nutool_modclkcfg_deinit_uart0(void);
+void nutool_modclkcfg_init_uart1(void);
+void nutool_modclkcfg_deinit_uart1(void);
+void nutool_modclkcfg_init_uart2(void);
+void nutool_modclkcfg_deinit_uart2(void);
+void nutool_modclkcfg_init_uart3(void);
+void nutool_modclkcfg_deinit_uart3(void);
+void nutool_modclkcfg_init_uart4(void);
+void nutool_modclkcfg_deinit_uart4(void);
+void nutool_modclkcfg_init_uart5(void);
+void nutool_modclkcfg_deinit_uart5(void);
+void nutool_modclkcfg_init_usbd(void);
+void nutool_modclkcfg_deinit_usbd(void);
+void nutool_modclkcfg_init_usbh(void);
+void nutool_modclkcfg_deinit_usbh(void);
+void nutool_modclkcfg_init_usci0(void);
+void nutool_modclkcfg_deinit_usci0(void);
+void nutool_modclkcfg_init_usci1(void);
+void nutool_modclkcfg_deinit_usci1(void);
+void nutool_modclkcfg_init_wdt(void);
+void nutool_modclkcfg_deinit_wdt(void);
+void nutool_modclkcfg_init_wwdt(void);
+void nutool_modclkcfg_deinit_wwdt(void);
+void nutool_modclkcfg_init_base(void);
+void nutool_modclkcfg_init(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /*__NUTOOL_MODCLKCFG_H__*/
+
+/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/numaker-m2354/board/NuPinConfig/nutool_pincfg.c b/bsp/nuvoton/numaker-m2354/board/NuPinConfig/nutool_pincfg.c
new file mode 100644
index 0000000000..55d8c8c99c
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/board/NuPinConfig/nutool_pincfg.c
@@ -0,0 +1,428 @@
+/****************************************************************************
+ * @file     nutool_pincfg.c
+ * @version  V1.21
+ * @Date     2020/11/11-12:06:36 
+ * @brief    NuMicro generated code file
+ *
+ * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+/********************
+MCU:M2354KJFAE(LQFP128)
+Pin Configuration:
+Pin1:SD0_DAT3
+Pin2:SD0_DAT2
+Pin3:SD0_DAT1
+Pin4:SD0_DAT0
+Pin5:EPWM1_CH0
+Pin6:EPWM1_CH1
+Pin7:EPWM1_CH2
+Pin8:EPWM1_CH3
+Pin9:SD0_CLK
+Pin10:SD0_CMD
+Pin15:UART1_TXD
+Pin16:UART1_RXD
+Pin21:I2C1_SCL
+Pin22:I2C1_SDA
+Pin25:I2S0_BCLK
+Pin26:I2S0_MCLK
+Pin27:I2S0_DI
+Pin28:I2S0_DO
+Pin29:I2S0_LRCK
+Pin48:UART4_TXD
+Pin49:UART4_RXD
+Pin50:UART0_TXD
+Pin51:UART0_RXD
+Pin57:SPI0_SS
+Pin58:SPI0_CLK
+Pin59:SPI0_MISO
+Pin60:SPI0_MOSI
+Pin65:ICE_DAT
+Pin66:ICE_CLK
+Pin73:EPWM1_CH4
+Pin74:EPWM1_CH5
+Pin93:USB_VBUS
+Pin94:USB_D-
+Pin95:USB_D+
+Pin96:USB_OTG_ID
+Pin97:EPWM0_CH0
+Pin98:EPWM0_CH1
+Pin105:SPI1_MISO
+Pin106:SPI1_MOSI
+Pin107:SPI1_CLK
+Pin108:SPI1_SS
+Pin109:PH.10
+Pin116:USB_VBUS_EN
+Pin117:USB_VBUS_ST
+Pin119:SD0_nCD
+Pin123:EADC0_CH11
+Pin124:EADC0_CH10
+Pin125:EADC0_CH9
+Pin126:EADC0_CH8
+Pin127:EADC0_CH7
+Pin128:EADC0_CH6
+********************/
+
+#include "M2354.h"
+#include "rtconfig.h"
+
+void nutool_pincfg_init_eadc0(void)
+{
+    SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB11MFP_Msk | SYS_GPB_MFPH_PB10MFP_Msk | SYS_GPB_MFPH_PB9MFP_Msk | SYS_GPB_MFPH_PB8MFP_Msk);
+    SYS->GPB_MFPH |= (SYS_GPB_MFPH_PB11MFP_EADC0_CH11 | SYS_GPB_MFPH_PB10MFP_EADC0_CH10 | SYS_GPB_MFPH_PB9MFP_EADC0_CH9 | SYS_GPB_MFPH_PB8MFP_EADC0_CH8);
+    SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB7MFP_Msk | SYS_GPB_MFPL_PB6MFP_Msk);
+    SYS->GPB_MFPL |= (SYS_GPB_MFPL_PB7MFP_EADC0_CH7 | SYS_GPB_MFPL_PB6MFP_EADC0_CH6);
+
+    /* Disable digital path on these EADC pins */
+    GPIO_DISABLE_DIGITAL_PATH(PB, BIT6 | BIT7 | BIT8 | BIT9 | BIT10 | BIT11);
+
+    return;
+}
+
+void nutool_pincfg_deinit_eadc0(void)
+{
+    SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB11MFP_Msk | SYS_GPB_MFPH_PB10MFP_Msk | SYS_GPB_MFPH_PB9MFP_Msk | SYS_GPB_MFPH_PB8MFP_Msk);
+    SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB7MFP_Msk | SYS_GPB_MFPL_PB6MFP_Msk);
+
+    /* Enable digital path on these EADC pins */
+    GPIO_ENABLE_DIGITAL_PATH(PB, BIT6 | BIT7 | BIT8 | BIT9 | BIT10 | BIT11);
+
+    return;
+}
+
+void nutool_pincfg_init_epwm0(void)
+{
+    SYS->GPE_MFPL &= ~(SYS_GPE_MFPL_PE7MFP_Msk | SYS_GPE_MFPL_PE6MFP_Msk);
+    SYS->GPE_MFPL |= (SYS_GPE_MFPL_PE7MFP_EPWM0_CH0 | SYS_GPE_MFPL_PE6MFP_EPWM0_CH1);
+
+    return;
+}
+
+void nutool_pincfg_deinit_epwm0(void)
+{
+    SYS->GPE_MFPL &= ~(SYS_GPE_MFPL_PE7MFP_Msk | SYS_GPE_MFPL_PE6MFP_Msk);
+
+    return;
+}
+
+void nutool_pincfg_init_epwm1(void)
+{
+    SYS->GPC_MFPH &= ~(SYS_GPC_MFPH_PC12MFP_Msk | SYS_GPC_MFPH_PC11MFP_Msk | SYS_GPC_MFPH_PC10MFP_Msk | SYS_GPC_MFPH_PC9MFP_Msk);
+    SYS->GPC_MFPH |= (SYS_GPC_MFPH_PC12MFP_EPWM1_CH0 | SYS_GPC_MFPH_PC11MFP_EPWM1_CH1 | SYS_GPC_MFPH_PC10MFP_EPWM1_CH2 | SYS_GPC_MFPH_PC9MFP_EPWM1_CH3);
+    SYS->GPC_MFPL &= ~(SYS_GPC_MFPL_PC1MFP_Msk | SYS_GPC_MFPL_PC0MFP_Msk);
+    SYS->GPC_MFPL |= (SYS_GPC_MFPL_PC1MFP_EPWM1_CH4 | SYS_GPC_MFPL_PC0MFP_EPWM1_CH5);
+
+    return;
+}
+
+void nutool_pincfg_deinit_epwm1(void)
+{
+    SYS->GPC_MFPH &= ~(SYS_GPC_MFPH_PC12MFP_Msk | SYS_GPC_MFPH_PC11MFP_Msk | SYS_GPC_MFPH_PC10MFP_Msk | SYS_GPC_MFPH_PC9MFP_Msk);
+    SYS->GPC_MFPL &= ~(SYS_GPC_MFPL_PC1MFP_Msk | SYS_GPC_MFPL_PC0MFP_Msk);
+
+    return;
+}
+
+void nutool_pincfg_init_i2c1(void)
+{
+    SYS->GPG_MFPL &= ~(SYS_GPG_MFPL_PG3MFP_Msk | SYS_GPG_MFPL_PG2MFP_Msk);
+    SYS->GPG_MFPL |= (SYS_GPG_MFPL_PG3MFP_I2C1_SDA | SYS_GPG_MFPL_PG2MFP_I2C1_SCL);
+
+    return;
+}
+
+void nutool_pincfg_deinit_i2c1(void)
+{
+    SYS->GPG_MFPL &= ~(SYS_GPG_MFPL_PG3MFP_Msk | SYS_GPG_MFPL_PG2MFP_Msk);
+
+    return;
+}
+
+void nutool_pincfg_init_i2s0(void)
+{
+    SYS->GPF_MFPH &= ~(SYS_GPF_MFPH_PF10MFP_Msk | SYS_GPF_MFPH_PF9MFP_Msk | SYS_GPF_MFPH_PF8MFP_Msk);
+    SYS->GPF_MFPH |= (SYS_GPF_MFPH_PF10MFP_I2S0_BCLK | SYS_GPF_MFPH_PF9MFP_I2S0_MCLK | SYS_GPF_MFPH_PF8MFP_I2S0_DI);
+    SYS->GPF_MFPL &= ~(SYS_GPF_MFPL_PF7MFP_Msk | SYS_GPF_MFPL_PF6MFP_Msk);
+    SYS->GPF_MFPL |= (SYS_GPF_MFPL_PF7MFP_I2S0_DO | SYS_GPF_MFPL_PF6MFP_I2S0_LRCK);
+
+    return;
+}
+
+void nutool_pincfg_deinit_i2s0(void)
+{
+    SYS->GPF_MFPH &= ~(SYS_GPF_MFPH_PF10MFP_Msk | SYS_GPF_MFPH_PF9MFP_Msk | SYS_GPF_MFPH_PF8MFP_Msk);
+    SYS->GPF_MFPL &= ~(SYS_GPF_MFPL_PF7MFP_Msk | SYS_GPF_MFPL_PF6MFP_Msk);
+
+    return;
+}
+
+void nutool_pincfg_init_ice(void)
+{
+    SYS->GPF_MFPL &= ~(SYS_GPF_MFPL_PF1MFP_Msk | SYS_GPF_MFPL_PF0MFP_Msk);
+    SYS->GPF_MFPL |= (SYS_GPF_MFPL_PF1MFP_ICE_CLK | SYS_GPF_MFPL_PF0MFP_ICE_DAT);
+
+    return;
+}
+
+void nutool_pincfg_deinit_ice(void)
+{
+    SYS->GPF_MFPL &= ~(SYS_GPF_MFPL_PF1MFP_Msk | SYS_GPF_MFPL_PF0MFP_Msk);
+
+    return;
+}
+
+void nutool_pincfg_init_ph(void)
+{
+    SYS->GPH_MFPH &= ~(SYS_GPH_MFPH_PH10MFP_Msk);
+    SYS->GPH_MFPH |= (SYS_GPH_MFPH_PH10MFP_GPIO);
+
+    return;
+}
+
+void nutool_pincfg_deinit_ph(void)
+{
+    SYS->GPH_MFPH &= ~(SYS_GPH_MFPH_PH10MFP_Msk);
+
+    return;
+}
+
+void nutool_pincfg_init_sd0(void)
+{
+    SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB12MFP_Msk);
+    SYS->GPB_MFPH |= (SYS_GPB_MFPH_PB12MFP_SD0_nCD);
+    SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB5MFP_Msk | SYS_GPB_MFPL_PB4MFP_Msk | SYS_GPB_MFPL_PB3MFP_Msk | SYS_GPB_MFPL_PB2MFP_Msk | SYS_GPB_MFPL_PB1MFP_Msk | SYS_GPB_MFPL_PB0MFP_Msk);
+    SYS->GPB_MFPL |= (SYS_GPB_MFPL_PB5MFP_SD0_DAT3 | SYS_GPB_MFPL_PB4MFP_SD0_DAT2 | SYS_GPB_MFPL_PB3MFP_SD0_DAT1 | SYS_GPB_MFPL_PB2MFP_SD0_DAT0 | SYS_GPB_MFPL_PB1MFP_SD0_CLK | SYS_GPB_MFPL_PB0MFP_SD0_CMD);
+
+    return;
+}
+
+void nutool_pincfg_deinit_sd0(void)
+{
+    SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB12MFP_Msk);
+    SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB5MFP_Msk | SYS_GPB_MFPL_PB4MFP_Msk | SYS_GPB_MFPL_PB3MFP_Msk | SYS_GPB_MFPL_PB2MFP_Msk | SYS_GPB_MFPL_PB1MFP_Msk | SYS_GPB_MFPL_PB0MFP_Msk);
+
+    return;
+}
+
+void nutool_pincfg_init_spi0(void)
+{
+    SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA3MFP_Msk | SYS_GPA_MFPL_PA2MFP_Msk | SYS_GPA_MFPL_PA1MFP_Msk | SYS_GPA_MFPL_PA0MFP_Msk);
+    SYS->GPA_MFPL |= (SYS_GPA_MFPL_PA3MFP_SPI0_SS | SYS_GPA_MFPL_PA2MFP_SPI0_CLK | SYS_GPA_MFPL_PA1MFP_SPI0_MISO | SYS_GPA_MFPL_PA0MFP_SPI0_MOSI);
+
+    return;
+}
+
+void nutool_pincfg_deinit_spi0(void)
+{
+    SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA3MFP_Msk | SYS_GPA_MFPL_PA2MFP_Msk | SYS_GPA_MFPL_PA1MFP_Msk | SYS_GPA_MFPL_PA0MFP_Msk);
+
+    return;
+}
+
+void nutool_pincfg_init_spi1(void)
+{
+    SYS->GPE_MFPL &= ~(SYS_GPE_MFPL_PE1MFP_Msk | SYS_GPE_MFPL_PE0MFP_Msk);
+    SYS->GPE_MFPL |= (SYS_GPE_MFPL_PE1MFP_SPI1_MISO | SYS_GPE_MFPL_PE0MFP_SPI1_MOSI);
+    SYS->GPH_MFPH &= ~(SYS_GPH_MFPH_PH9MFP_Msk | SYS_GPH_MFPH_PH8MFP_Msk);
+    SYS->GPH_MFPH |= (SYS_GPH_MFPH_PH9MFP_SPI1_SS | SYS_GPH_MFPH_PH8MFP_SPI1_CLK);
+
+    return;
+}
+
+void nutool_pincfg_deinit_spi1(void)
+{
+    SYS->GPE_MFPL &= ~(SYS_GPE_MFPL_PE1MFP_Msk | SYS_GPE_MFPL_PE0MFP_Msk);
+    SYS->GPH_MFPH &= ~(SYS_GPH_MFPH_PH9MFP_Msk | SYS_GPH_MFPH_PH8MFP_Msk);
+
+    return;
+}
+
+void nutool_pincfg_init_uart0(void)
+{
+    SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA7MFP_Msk | SYS_GPA_MFPL_PA6MFP_Msk);
+    SYS->GPA_MFPL |= (SYS_GPA_MFPL_PA7MFP_UART0_TXD | SYS_GPA_MFPL_PA6MFP_UART0_RXD);
+
+    return;
+}
+
+void nutool_pincfg_deinit_uart0(void)
+{
+    SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA7MFP_Msk | SYS_GPA_MFPL_PA6MFP_Msk);
+
+    return;
+}
+
+void nutool_pincfg_init_uart1(void)
+{
+    SYS->GPA_MFPH &= ~(SYS_GPA_MFPH_PA9MFP_Msk | SYS_GPA_MFPH_PA8MFP_Msk);
+    SYS->GPA_MFPH |= (SYS_GPA_MFPH_PA9MFP_UART1_TXD | SYS_GPA_MFPH_PA8MFP_UART1_RXD);
+
+    return;
+}
+
+void nutool_pincfg_deinit_uart1(void)
+{
+    SYS->GPA_MFPH &= ~(SYS_GPA_MFPH_PA9MFP_Msk | SYS_GPA_MFPH_PA8MFP_Msk);
+
+    return;
+}
+
+void nutool_pincfg_init_uart4(void)
+{
+    SYS->GPC_MFPL &= ~(SYS_GPC_MFPL_PC7MFP_Msk | SYS_GPC_MFPL_PC6MFP_Msk);
+    SYS->GPC_MFPL |= (SYS_GPC_MFPL_PC7MFP_UART4_TXD | SYS_GPC_MFPL_PC6MFP_UART4_RXD);
+
+    return;
+}
+
+void nutool_pincfg_deinit_uart4(void)
+{
+    SYS->GPC_MFPL &= ~(SYS_GPC_MFPL_PC7MFP_Msk | SYS_GPC_MFPL_PC6MFP_Msk);
+
+    return;
+}
+
+void nutool_pincfg_init_usb(void)
+{
+    SYS->GPA_MFPH &= ~(SYS_GPA_MFPH_PA15MFP_Msk | SYS_GPA_MFPH_PA14MFP_Msk | SYS_GPA_MFPH_PA13MFP_Msk | SYS_GPA_MFPH_PA12MFP_Msk);
+    SYS->GPA_MFPH |= (SYS_GPA_MFPH_PA15MFP_USB_OTG_ID | SYS_GPA_MFPH_PA14MFP_USB_D_P | SYS_GPA_MFPH_PA13MFP_USB_D_N | SYS_GPA_MFPH_PA12MFP_USB_VBUS);
+    SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB15MFP_Msk | SYS_GPB_MFPH_PB14MFP_Msk);
+    SYS->GPB_MFPH |= (SYS_GPB_MFPH_PB15MFP_USB_VBUS_EN | SYS_GPB_MFPH_PB14MFP_USB_VBUS_ST);
+
+    return;
+}
+
+void nutool_pincfg_deinit_usb(void)
+{
+    SYS->GPA_MFPH &= ~(SYS_GPA_MFPH_PA15MFP_Msk | SYS_GPA_MFPH_PA14MFP_Msk | SYS_GPA_MFPH_PA13MFP_Msk | SYS_GPA_MFPH_PA12MFP_Msk);
+    SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB15MFP_Msk | SYS_GPB_MFPH_PB14MFP_Msk);
+
+    return;
+}
+
+
+void pincfg_init_slcd(void)
+{
+    /*
+        Summary of LCD pin usage:
+            COM 0~5   : PC.0, PC.1, PC.2, PC.3, PC.4, PC.5
+            COM 6~7   : PD.8, PD.9
+            SEG 0     : PD.14
+            SEG 1~4   : PH.11, PH.10, PH.9, PH.8
+            SEG 5~12  : PE.0, PE.1, PE.2, PE.3, PE.4, PE.5, PE.6, PE.7
+            SEG 13~14 : PD.6, PD.7
+            SEG 15~21 : PG.15, PG.14, PG.13, PG.12, PG.11, PG.10, PG.9
+            SEG 22~23 : PE.15, PE.14
+            SEG 24~29 : PA.0, PA.1, PA.2, PA.3, PA.4, PA.5
+            SEG 30~32 : PE.10, PE.9, PE.8
+            SEG 33~36 : PH.7, PH.6, PH.5, PH.4
+            SEG 37~39 : PG.4, PG.3, PG.2
+    */
+    
+    /* COM 0~5 */
+    SYS->GPC_MFPL = (SYS->GPC_MFPL & 
+                    ~(SYS_GPC_MFPL_PC0MFP_Msk | SYS_GPC_MFPL_PC1MFP_Msk | SYS_GPC_MFPL_PC2MFP_Msk | SYS_GPC_MFPL_PC3MFP_Msk | 
+                      SYS_GPC_MFPL_PC4MFP_Msk | SYS_GPC_MFPL_PC5MFP_Msk)) |
+                    (LCD_COM0_PC0 | LCD_COM1_PC1 | LCD_COM2_PC2 | LCD_COM3_PC3 | LCD_COM4_PC4 | LCD_COM5_PC5);
+    /* COM 6~7 */
+    SYS->GPD_MFPH = (SYS->GPD_MFPH & ~(SYS_GPD_MFPH_PD8MFP_Msk | SYS_GPD_MFPH_PD9MFP_Msk)) |
+                    (LCD_COM6_PD8 | LCD_COM7_PD9);
+    
+    /* SEG 0 */
+    SYS->GPD_MFPH = (SYS->GPD_MFPH & ~SYS_GPD_MFPH_PD14MFP_Msk) | LCD_SEG0_PD14;
+    /* SEG 1~4 */
+    SYS->GPH_MFPH = (SYS->GPH_MFPH & ~(SYS_GPH_MFPH_PH11MFP_Msk | SYS_GPH_MFPH_PH10MFP_Msk | SYS_GPH_MFPH_PH9MFP_Msk | SYS_GPH_MFPH_PH8MFP_Msk)) |
+                    (LCD_SEG1_PH11 | LCD_SEG2_PH10 | LCD_SEG3_PH9 | LCD_SEG4_PH8);
+    /* SEG 5~12 */
+    SYS->GPE_MFPL = (SYS->GPE_MFPL & 
+                    ~(SYS_GPE_MFPL_PE0MFP_Msk | SYS_GPE_MFPL_PE1MFP_Msk | SYS_GPE_MFPL_PE2MFP_Msk | SYS_GPE_MFPL_PE3MFP_Msk |
+                      SYS_GPE_MFPL_PE4MFP_Msk | SYS_GPE_MFPL_PE5MFP_Msk | SYS_GPE_MFPL_PE6MFP_Msk | SYS_GPE_MFPL_PE7MFP_Msk)) |
+                    (LCD_SEG5_PE0 | LCD_SEG6_PE1 | LCD_SEG7_PE2 | LCD_SEG8_PE3 |
+                     LCD_SEG9_PE4 | LCD_SEG10_PE5 | LCD_SEG11_PE6 | LCD_SEG12_PE7);
+    /* SEG 13~14 */
+    SYS->GPD_MFPL = (SYS->GPD_MFPL & ~(SYS_GPD_MFPL_PD6MFP_Msk | SYS_GPD_MFPL_PD7MFP_Msk)) | (LCD_SEG13_PD6 | LCD_SEG14_PD7);
+    /* SEG 15~21 */
+    SYS->GPG_MFPH = (SYS->GPG_MFPH & 
+                    ~(SYS_GPG_MFPH_PG15MFP_Msk | SYS_GPG_MFPH_PG14MFP_Msk | SYS_GPG_MFPH_PG13MFP_Msk | SYS_GPG_MFPH_PG12MFP_Msk |
+                      SYS_GPG_MFPH_PG11MFP_Msk | SYS_GPG_MFPH_PG10MFP_Msk | SYS_GPG_MFPH_PG9MFP_Msk)) |
+                    (LCD_SEG15_PG15 | LCD_SEG16_PG14 | LCD_SEG17_PG13 | LCD_SEG18_PG12 |
+                     LCD_SEG19_PG11 | LCD_SEG20_PG10 | LCD_SEG21_PG9);
+    /* SEG 22~23 */
+    SYS->GPE_MFPH = (SYS->GPE_MFPH & ~(SYS_GPE_MFPH_PE15MFP_Msk | SYS_GPE_MFPH_PE14MFP_Msk)) | (LCD_SEG22_PE15 | LCD_SEG23_PE14);
+    /* SEG 24~29 */
+    SYS->GPA_MFPL = (SYS->GPA_MFPL & 
+                    ~(SYS_GPA_MFPL_PA0MFP_Msk | SYS_GPA_MFPL_PA1MFP_Msk | SYS_GPA_MFPL_PA2MFP_Msk | SYS_GPA_MFPL_PA3MFP_Msk |
+                      SYS_GPA_MFPL_PA4MFP_Msk | SYS_GPA_MFPL_PA5MFP_Msk)) |
+                    (LCD_SEG24_PA0 | LCD_SEG25_PA1 | LCD_SEG26_PA2 | LCD_SEG27_PA3 | LCD_SEG28_PA4 |LCD_SEG29_PA5);
+    /* SEG 30~32 */
+    SYS->GPE_MFPH = (SYS->GPE_MFPH & ~(SYS_GPE_MFPH_PE10MFP_Msk | SYS_GPE_MFPH_PE9MFP_Msk | SYS_GPE_MFPH_PE8MFP_Msk)) | 
+                    (LCD_SEG30_PE10 | LCD_SEG31_PE9 | LCD_SEG32_PE8);
+    /* SEG 33~36 */
+    SYS->GPH_MFPL = (SYS->GPH_MFPL & ~(SYS_GPH_MFPL_PH7MFP_Msk | SYS_GPH_MFPL_PH6MFP_Msk | SYS_GPH_MFPL_PH5MFP_Msk | SYS_GPH_MFPL_PH4MFP_Msk)) |
+                    (LCD_SEG33_PH7 | LCD_SEG34_PH6 | LCD_SEG35_PH5 | LCD_SEG36_PH4);
+    /* SEG 37~39 */
+    SYS->GPG_MFPL = (SYS->GPG_MFPL & ~(SYS_GPG_MFPL_PG4MFP_Msk | SYS_GPG_MFPL_PG3MFP_Msk | SYS_GPG_MFPL_PG2MFP_Msk)) |
+                    (LCD_SEG37_PG4 | LCD_SEG38_PG3 | LCD_SEG39_PG2);
+}
+
+
+void nutool_pincfg_init(void)
+{
+    //SYS->GPA_MFPH = 0xEEEE0077;
+    //SYS->GPA_MFPL = 0x77004444;
+    //SYS->GPB_MFPH = 0xEF091111;
+    //SYS->GPB_MFPL = 0x11333333;
+    //SYS->GPC_MFPH = 0x000CCCC0;
+    //SYS->GPC_MFPL = 0x550000CC;
+    //SYS->GPD_MFPH = 0x00000000;
+    //SYS->GPD_MFPL = 0x00000000;
+    //SYS->GPE_MFPH = 0x00000000;
+    //SYS->GPE_MFPL = 0xCC000066;
+    //SYS->GPF_MFPH = 0x00000444;
+    //SYS->GPF_MFPL = 0x440000EE;
+    //SYS->GPG_MFPH = 0x00000000;
+    //SYS->GPG_MFPL = 0x00005500;
+    //SYS->GPH_MFPH = 0x00000066;
+    //SYS->GPH_MFPL = 0x00000000;
+
+    nutool_pincfg_init_eadc0();
+    nutool_pincfg_init_epwm0();
+    nutool_pincfg_init_epwm1();
+    nutool_pincfg_init_i2c1();
+    nutool_pincfg_init_i2s0();
+    nutool_pincfg_init_ice();
+    nutool_pincfg_init_ph();
+    nutool_pincfg_init_sd0();
+    nutool_pincfg_init_spi0();
+    nutool_pincfg_init_spi1();
+    nutool_pincfg_init_uart0();
+    nutool_pincfg_init_uart1();
+    nutool_pincfg_init_uart4();
+    nutool_pincfg_init_usb();
+
+#if defined(BSP_USING_SLCD)
+    pincfg_init_slcd();
+#endif
+    return;
+}
+
+void nutool_pincfg_deinit(void)
+{
+    nutool_pincfg_deinit_eadc0();
+    nutool_pincfg_deinit_epwm0();
+    nutool_pincfg_deinit_epwm1();
+    nutool_pincfg_deinit_i2c1();
+    nutool_pincfg_deinit_i2s0();
+    nutool_pincfg_deinit_ice();
+    nutool_pincfg_deinit_ph();
+    nutool_pincfg_deinit_sd0();
+    nutool_pincfg_deinit_spi0();
+    nutool_pincfg_deinit_spi1();
+    nutool_pincfg_deinit_uart0();
+    nutool_pincfg_deinit_uart1();
+    nutool_pincfg_deinit_uart4();
+    nutool_pincfg_deinit_usb();
+
+    return;
+}
+/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/numaker-m2354/board/NuPinConfig/nutool_pincfg.cfg b/bsp/nuvoton/numaker-m2354/board/NuPinConfig/nutool_pincfg.cfg
new file mode 100644
index 0000000000..4db2d24dd5
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/board/NuPinConfig/nutool_pincfg.cfg
@@ -0,0 +1,157 @@
+/****************************************************************************
+ * @file     nutool_pincfg.cfg
+ * @version  V1.21
+ * @Date     2020/11/11-12:06:37 
+ * @brief    NuMicro config file
+ *
+ * @note Please do not modify this file.
+ *       Otherwise, it may not be loaded successfully.
+ * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+MCU:M2354KJFAE(LQFP128)
+Pin1:SD0_DAT3
+Pin2:SD0_DAT2
+Pin3:SD0_DAT1
+Pin4:SD0_DAT0
+Pin5:EPWM1_CH0
+Pin6:EPWM1_CH1
+Pin7:EPWM1_CH2
+Pin8:EPWM1_CH3
+Pin9:SD0_CLK
+Pin10:SD0_CMD
+Pin11:VSS
+Pin12:VDD
+Pin13:PA.11
+Pin14:PA.10
+Pin15:UART1_TXD
+Pin16:UART1_RXD
+Pin17:PC.13
+Pin18:PD.12
+Pin19:PD.11
+Pin20:PD.10
+Pin21:I2C1_SCL
+Pin22:I2C1_SDA
+Pin23:PG.4
+Pin24:PF.11
+Pin25:I2S0_BCLK
+Pin26:I2S0_MCLK
+Pin27:I2S0_DI
+Pin28:I2S0_DO
+Pin29:I2S0_LRCK
+Pin30:VBAT
+Pin31:PF.5
+Pin32:PF.4
+Pin33:PH.4
+Pin34:PH.5
+Pin35:PH.6
+Pin36:PH.7
+Pin37:PF.3
+Pin38:PF.2
+Pin39:VSS
+Pin40:VDD
+Pin41:PE.8
+Pin42:PE.9
+Pin43:PE.10
+Pin44:PE.11
+Pin45:PE.12
+Pin46:PE.13
+Pin47:PC.8
+Pin48:UART4_TXD
+Pin49:UART4_RXD
+Pin50:UART0_TXD
+Pin51:UART0_RXD
+Pin52:VSS
+Pin53:VDD
+Pin54:LDO_CAP
+Pin55:PA.5
+Pin56:PA.4
+Pin57:SPI0_SS
+Pin58:SPI0_CLK
+Pin59:SPI0_MISO
+Pin60:SPI0_MOSI
+Pin61:VDDIO
+Pin62:PE.14
+Pin63:PE.15
+Pin64:nRESET
+Pin65:ICE_DAT
+Pin66:ICE_CLK
+Pin67:PD.9
+Pin68:PD.8
+Pin69:PC.5
+Pin70:PC.4
+Pin71:PC.3
+Pin72:PC.2
+Pin73:EPWM1_CH4
+Pin74:EPWM1_CH5
+Pin75:VSS
+Pin76:VDD
+Pin77:PG.9
+Pin78:PG.10
+Pin79:PG.11
+Pin80:PG.12
+Pin81:PG.13
+Pin82:PG.14
+Pin83:PG.15
+Pin84:PD.7
+Pin85:PD.6
+Pin86:PD.5
+Pin87:PD.4
+Pin88:PD.3
+Pin89:PD.2
+Pin90:PD.1
+Pin91:PD.0
+Pin92:VLCD
+Pin93:USB_VBUS
+Pin94:USB_D-
+Pin95:USB_D+
+Pin96:USB_OTG_ID
+Pin97:EPWM0_CH0
+Pin98:EPWM0_CH1
+Pin99:PE.5
+Pin100:PE.4
+Pin101:PE.3
+Pin102:PE.2
+Pin103:VSS
+Pin104:VDD
+Pin105:SPI1_MISO
+Pin106:SPI1_MOSI
+Pin107:SPI1_CLK
+Pin108:SPI1_SS
+Pin109:PH.10
+Pin110:PH.11
+Pin111:PD.14
+Pin112:VSS
+Pin113:Vsw
+Pin114:VDD
+Pin115:LDO_CAP
+Pin116:USB_VBUS_EN
+Pin117:USB_VBUS_ST
+Pin118:PB.13
+Pin119:SD0_nCD
+Pin120:AVDD
+Pin121:VREF
+Pin122:AVSS
+Pin123:EADC0_CH11
+Pin124:EADC0_CH10
+Pin125:EADC0_CH9
+Pin126:EADC0_CH8
+Pin127:EADC0_CH7
+Pin128:EADC0_CH6
+GPIOpin:108
+SYS->GPA_MFPH = 0xEEEE0077
+SYS->GPA_MFPL = 0x77004444
+SYS->GPB_MFPH = 0xEF091111
+SYS->GPB_MFPL = 0x11333333
+SYS->GPC_MFPH = 0x000CCCC0
+SYS->GPC_MFPL = 0x550000CC
+SYS->GPD_MFPH = 0x00000000
+SYS->GPD_MFPL = 0x00000000
+SYS->GPE_MFPH = 0x00000000
+SYS->GPE_MFPL = 0xCC000066
+SYS->GPF_MFPH = 0x00000444
+SYS->GPF_MFPL = 0x440000EE
+SYS->GPG_MFPH = 0x00000000
+SYS->GPG_MFPL = 0x00005500
+SYS->GPH_MFPH = 0x00000066
+SYS->GPH_MFPL = 0x00000000
+/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/numaker-m2354/board/NuPinConfig/nutool_pincfg.h b/bsp/nuvoton/numaker-m2354/board/NuPinConfig/nutool_pincfg.h
new file mode 100644
index 0000000000..c3222715fc
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/board/NuPinConfig/nutool_pincfg.h
@@ -0,0 +1,52 @@
+/****************************************************************************
+ * @file     nutool_pincfg.h
+ * @version  V1.21
+ * @Date     2020/11/11-12:06:36 
+ * @brief    NuMicro generated code file
+ *
+ * Copyright (C) 2013-2020 Nuvoton Technology Corp. All rights reserved.
+*****************************************************************************/
+
+#ifndef __NUTOOL_PINCFG_H__
+#define __NUTOOL_PINCFG_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+void nutool_pincfg_init_eadc0(void);
+void nutool_pincfg_deinit_eadc0(void);
+void nutool_pincfg_init_epwm0(void);
+void nutool_pincfg_deinit_epwm0(void);
+void nutool_pincfg_init_epwm1(void);
+void nutool_pincfg_deinit_epwm1(void);
+void nutool_pincfg_init_i2c1(void);
+void nutool_pincfg_deinit_i2c1(void);
+void nutool_pincfg_init_i2s0(void);
+void nutool_pincfg_deinit_i2s0(void);
+void nutool_pincfg_init_ice(void);
+void nutool_pincfg_deinit_ice(void);
+void nutool_pincfg_init_ph(void);
+void nutool_pincfg_deinit_ph(void);
+void nutool_pincfg_init_sd0(void);
+void nutool_pincfg_deinit_sd0(void);
+void nutool_pincfg_init_spi0(void);
+void nutool_pincfg_deinit_spi0(void);
+void nutool_pincfg_init_spi1(void);
+void nutool_pincfg_deinit_spi1(void);
+void nutool_pincfg_init_uart0(void);
+void nutool_pincfg_deinit_uart0(void);
+void nutool_pincfg_init_uart1(void);
+void nutool_pincfg_deinit_uart1(void);
+void nutool_pincfg_init_uart4(void);
+void nutool_pincfg_deinit_uart4(void);
+void nutool_pincfg_init_usb(void);
+void nutool_pincfg_deinit_usb(void);
+void nutool_pincfg_init(void);
+void nutool_pincfg_deinit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /*__NUTOOL_PINCFG_H__*/
+
+/*** (C) COPYRIGHT 2013-2020 Nuvoton Technology Corp. ***/
diff --git a/bsp/nuvoton/numaker-m2354/board/SConscript b/bsp/nuvoton/numaker-m2354/board/SConscript
new file mode 100644
index 0000000000..6ed8f178ba
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/board/SConscript
@@ -0,0 +1,20 @@
+# RT-Thread building script for component
+
+from building import *
+
+
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+src = Split("""
+NuClockConfig/nutool_modclkcfg.c
+NuPinConfig/nutool_pincfg.c
+""")
+
+src += Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd, cwd + '/NuClockConfig', cwd + '/NuPinConfig']
+
+group = DefineGroup('board', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/nuvoton/numaker-m2354/board/board.h b/bsp/nuvoton/numaker-m2354/board/board.h
new file mode 100644
index 0000000000..e783166fef
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/board/board.h
@@ -0,0 +1,37 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author       Notes
+* 2020-1-16       Wayne        First version
+*
+******************************************************************************/
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+//  Internal SRAM memory size[Kbytes] <8-64>
+#define SRAM_SIZE         (256)
+#define SRAM_END          (0x20000000 + SRAM_SIZE * 1024)
+
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN      ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="CSTACK"
+#define HEAP_BEGIN      (__segment_end("CSTACK"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN      ((void *)&__bss_end)
+#endif
+
+#define HEAP_END        (void *)SRAM_END
+
+
+void rt_hw_board_init(void);
+void rt_hw_cpu_reset(void);
+
+#endif /* BOARD_H_ */
diff --git a/bsp/nuvoton/numaker-m2354/board/board_dev.c b/bsp/nuvoton/numaker-m2354/board/board_dev.c
new file mode 100644
index 0000000000..3cf1d862b7
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/board/board_dev.c
@@ -0,0 +1,82 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author       Notes
+* 2020-1-16       Wayne        First version
+*
+******************************************************************************/
+
+#include 
+#include 
+
+#if defined(BOARD_USING_ESP8266)
+#include 
+
+#define LOG_TAG     "at.sample.esp"
+#undef DBG_TAG
+#include 
+
+static struct at_device_esp8266 esp0 =
+{
+    "esp0",          /* esp8266 device name */
+    "uart4",         /* esp8266 serial device name, EX: uart1, uuart1 */
+
+    "NT_ZY_BUFFALO", /* Wi-Fi SSID */
+    "12345678",      /* Wi-Fi PASSWORD */
+    1024             /* Receive buffer length */
+};
+
+static int rt_hw_esp8266_port(void)
+{
+    struct at_device_esp8266 *esp8266 = &esp0;
+    rt_base_t esp_rst_pin = NU_GET_PININDEX(NU_PC, 13);
+    rt_base_t esp_fwupdate_pin = NU_GET_PININDEX(NU_PD, 12);
+
+    /* ESP8266 reset pin PC.13 */
+    rt_pin_mode(esp_rst_pin, PIN_MODE_OUTPUT);
+    rt_pin_write(esp_rst_pin, 1);
+
+    /* ESP8266 reset pin PD.12 */
+    rt_pin_mode(esp_fwupdate_pin, PIN_MODE_OUTPUT);
+    rt_pin_write(esp_fwupdate_pin, 1);
+
+    return at_device_register(&(esp8266->device),
+                              esp8266->device_name,
+                              esp8266->client_name,
+                              AT_DEVICE_CLASS_ESP8266,
+                              (void *) esp8266);
+}
+INIT_APP_EXPORT(rt_hw_esp8266_port);
+
+static void at_wifi_set(int argc, char **argv)
+{
+    struct at_device_ssid_pwd sATDConf;
+    struct at_device *at_dev = RT_NULL;
+
+    /* If the number of arguments less than 2 */
+    if (argc != 3)
+    {
+        rt_kprintf("\n");
+        rt_kprintf("at_wifi_set  \n");
+        return ;
+    }
+
+    sATDConf.ssid     = argv[1]; //ssid
+    sATDConf.password = argv[2]; //password
+
+    if ((at_dev = at_device_get_first_initialized()) != RT_NULL)
+        at_device_control(at_dev, AT_DEVICE_CTRL_SET_WIFI_INFO, &sATDConf);
+    else
+    {
+        rt_kprintf("Can't find any initialized AT device.\n");
+    }
+}
+#ifdef FINSH_USING_MSH
+    MSH_CMD_EXPORT(at_wifi_set, AT device wifi set ssid / password function);
+#endif
+#endif /* BOARD_USING_ESP8266  */
+
diff --git a/bsp/nuvoton/numaker-m2354/board/fal_cfg.h b/bsp/nuvoton/numaker-m2354/board/fal_cfg.h
new file mode 100644
index 0000000000..ff56e4a368
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/board/fal_cfg.h
@@ -0,0 +1,42 @@
+/**************************************************************************//**
+*
+* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Change Logs:
+* Date            Author       Notes
+* 2020-3-03       FYChou       First version
+*
+******************************************************************************/
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include 
+#include 
+
+
+/* ===================== Flash device Configuration ========================= */
+extern const struct fal_flash_dev Onchip_aprom_flash;
+extern const struct fal_flash_dev Onchip_ldrom_flash;
+
+/* -flash device table------------------------------------------------------- */
+#define FAL_FLASH_DEV_TABLE                                                                   \
+{                                                                                             \
+    &Onchip_aprom_flash,                                                                      \
+    &Onchip_ldrom_flash,                                                                      \
+}
+
+/* ====================== Partition Configuration ============================ */
+#ifdef FAL_PART_HAS_TABLE_CFG
+
+/* -partition table----------------------------------------------------------- */
+#define FAL_PART_TABLE                                                                        \
+{                                                                                             \
+    {FAL_PART_MAGIC_WORD,        "ldrom",     "OnChip_LDROM",         0,          0x1000,  0},   \
+    {FAL_PART_MAGIC_WORD,        "aprom",     "OnChip_APROM",         0xF0000,    0x10000, 0},   \
+}
+#endif /* FAL_PART_HAS_TABLE_CFG */
+
+#endif /* _FAL_CFG_H_ */
diff --git a/bsp/nuvoton/numaker-m2354/linking_scripts/m2354_flash.icf b/bsp/nuvoton/numaker-m2354/linking_scripts/m2354_flash.icf
new file mode 100644
index 0000000000..ed18f7e818
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/linking_scripts/m2354_flash.icf
@@ -0,0 +1,28 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x000fffff;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2003ffff;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x2000;
+define symbol __ICFEDIT_size_heap__   = 0x0000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite, last block CSTACK};
diff --git a/bsp/nuvoton/numaker-m2354/linking_scripts/m2354_flash.sct b/bsp/nuvoton/numaker-m2354/linking_scripts/m2354_flash.sct
new file mode 100644
index 0000000000..a2f8ebd922
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/linking_scripts/m2354_flash.sct
@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x100000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x100000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20000000 0x40000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+
diff --git a/bsp/nuvoton/numaker-m2354/linking_scripts/m2354_link.ld b/bsp/nuvoton/numaker-m2354/linking_scripts/m2354_link.ld
new file mode 100644
index 0000000000..cf15cb0896
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/linking_scripts/m2354_link.ld
@@ -0,0 +1,159 @@
+/*
+ * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-05-2      Wayne        First version
+ */
+
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+    CODE (rx) : ORIGIN = 0x00000000, LENGTH = 1024K   /* 1024K flash */
+    DATA (rw) : ORIGIN = 0x20000000, LENGTH = 256K    /* 256K sram */
+}
+ENTRY(Reset_Handler)
+_system_stack_size = 0x2000;
+
+SECTIONS
+{
+    .vector :
+    {
+        . = ALIGN(4);
+        _stext = .;
+        KEEP(*(.isr_vector))            /* Startup code */
+    } > CODE = 0
+    
+    .text :
+    {
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        /* section information for utest */
+        . = ALIGN(4);
+        __rt_utest_tc_tab_start = .;
+        KEEP(*(UtestTcTab))
+        __rt_utest_tc_tab_end = .;
+
+        . = ALIGN(4);
+        _etext = .;
+    } > CODE = 0
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+        /* This is used by the startup in order to initialize the .data section */
+        _sidata = .;
+    } > CODE
+    __exidx_end = .;
+
+    .stack : 
+    {
+        _sstack = .;
+        . = . + _system_stack_size;
+        . = ALIGN(4);
+        _estack = .;
+    } >DATA
+
+    /* .data section which is used for initialized data */
+    .data : AT (_sidata)
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data section */
+        _sdata = . ;
+
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d*)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data section */
+        _edata = . ;
+    } >DATA
+
+    __bss_start = .;
+    .bss :
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss section */
+        _sbss = .;
+
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss section */
+        _ebss = . ;
+        
+        *(.bss.init)
+    } > DATA
+    __bss_end = .;
+
+    _end = .;
+    
+    __ram_top = ORIGIN(DATA) + LENGTH(DATA);
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
diff --git a/bsp/nuvoton/numaker-m2354/rtconfig.py b/bsp/nuvoton/numaker-m2354/rtconfig.py
new file mode 100644
index 0000000000..aba7250bc3
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/rtconfig.py
@@ -0,0 +1,124 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m23'
+CROSS_TOOL='keil'
+
+if os.getenv('RTT_CC'):
+	CROSS_TOOL = os.getenv('RTT_CC')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+
+if  CROSS_TOOL == 'gcc':
+	PLATFORM 	= 'gcc'
+	EXEC_PATH 	= r'C:\Program Files (x86)\GNU Tools ARM Embedded\6 2017-q1-update\bin'
+elif CROSS_TOOL == 'keil':
+	PLATFORM 	= 'armcc'
+	EXEC_PATH 	= r'C:\Keil_v5'
+elif CROSS_TOOL == 'iar':
+	PLATFORM 	= 'iar'
+	EXEC_PATH 	= r'C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.2'
+
+if os.getenv('RTT_EXEC_PATH'):
+	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = ''
+# BUILD = 'debug'
+
+
+if PLATFORM == 'gcc':
+    # tool-chains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=cortex-m23 -mthumb -ffunction-sections -fdata-sections -Wuninitialized'
+    CFLAGS = DEVICE + ' -Dgcc' # -D' + PART_TYPE
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T ./linking_scripts/m2354_link.ld'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2 -g'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --cpu Cortex-M23'
+    CFLAGS = DEVICE + ' --apcs=interwork'
+    AFLAGS = DEVICE
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter ./linking_scripts/m2354_flash.sct'
+
+    LFLAGS += ' --keep *.o(.rti_fn.*)   --keep *.o(FSymTab) --keep *.o(VSymTab)'
+
+    EXEC_PATH += '/ARM/ARMCC/bin'
+    print(EXEC_PATH)
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+    # toolchains
+    CC = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    CFLAGS = DEVICE
+    CFLAGS += ' --diag_suppress Pa050'
+    CFLAGS += ' --no_cse'
+    CFLAGS += ' --no_unroll'
+    CFLAGS += ' --no_inline'
+    CFLAGS += ' --no_code_motion'
+    CFLAGS += ' --no_tbaa'
+    CFLAGS += ' --no_clustering'
+    CFLAGS += ' --no_scheduling'
+    CFLAGS += ' --debug'
+    CFLAGS += ' --endian=little'
+    CFLAGS += ' --cpu=Cortex-M23'
+    CFLAGS += ' -e'
+    CFLAGS += ' --fpu=None'
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+    CFLAGS += ' -Ol'
+    CFLAGS += ' --use_c++_inline'
+
+    AFLAGS = ''
+    AFLAGS += ' -s+'
+    AFLAGS += ' -w+'
+    AFLAGS += ' -r'
+    AFLAGS += ' --cpu Cortex-M23'
+    AFLAGS += ' --fpu None'
+
+    LFLAGS = ' --config ./linking_scripts/m2354_flash.icf'
+    LFLAGS += ' --redirect _Printf=_PrintfTiny'
+    LFLAGS += ' --redirect _Scanf=_ScanfSmall'
+    LFLAGS += ' --entry __iar_program_start'
+
+    EXEC_PATH += '/arm/bin/'
+    POST_ACTION = ''
diff --git a/bsp/nuvoton/numaker-m2354/template.ewd b/bsp/nuvoton/numaker-m2354/template.ewd
new file mode 100644
index 0000000000..984061a030
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/template.ewd
@@ -0,0 +1,2966 @@
+
+
+    3
+    
+        Release
+        
+            ARM
+        
+        0
+        
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+            2
+            
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+                1
+                0
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+        
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+            2
+            
+                1
+                1
+                0
+                
+                
+                
+                
+            
+        
+        
+            CADI_ID
+            2
+            
+                0
+                1
+                0
+                
+                
+                
+                
+                
+            
+        
+        
+            CMSISDAP_ID
+            2
+            
+                4
+                1
+                0
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+            2
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+            2
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+            PEMICRO_ID
+            2
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+            STLINK_ID
+            2
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+                
+                
+                
+                
+                
+                
+            
+        
+        
+            
+                $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+                0
+            
+            
+                $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+                1
+            
+            
+                $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+                0
+            
+            
+                $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+                0
+            
+            
+                $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+                0
+            
+        
+    
+    
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+        
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+        
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+        
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+            2
+            
+                30
+                1
+                1
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+            2
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+                1
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+            
+        
+        
+            STLINK_ID
+            2
+            
+                6
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
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+                
+                
+                
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+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            THIRDPARTY_ID
+            2
+            
+                0
+                1
+                1
+                
+                
+                
+                
+            
+        
+        
+            TIFET_ID
+            2
+            
+                1
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            XDS100_ID
+            2
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+                8
+                1
+                1
+                
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+                
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+                
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+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            
+                $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+                0
+            
+            
+                $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin
+                1
+            
+            
+                $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+                0
+            
+            
+                $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+                0
+            
+            
+                $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+                0
+            
+        
+    
+
diff --git a/bsp/nuvoton/numaker-m2354/template.ewp b/bsp/nuvoton/numaker-m2354/template.ewp
new file mode 100644
index 0000000000..a4c4d55957
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/template.ewp
@@ -0,0 +1,2074 @@
+
+
+    3
+    
+        Release
+        
+            ARM
+        
+        0
+        
+            General
+            3
+            
+                31
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            ICCARM
+            2
+            
+                35
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            AARM
+            2
+            
+                10
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            OBJCOPY
+            0
+            
+                1
+                1
+                0
+                
+                
+                
+                
+                
+            
+        
+        
+            CUSTOM
+            3
+            
+                
+                
+                0
+            
+        
+        
+            BICOMP
+            0
+            
+        
+        
+            BUILDACTION
+            1
+            
+                
+                
+            
+        
+        
+            ILINK
+            0
+            
+                22
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            IARCHIVE
+            0
+            
+                0
+                1
+                0
+                
+                
+                
+            
+        
+        
+            BILINK
+            0
+            
+        
+    
+    
+        Debug
+        
+            ARM
+        
+        1
+        
+            General
+            3
+            
+                31
+                1
+                1
+                
+                
+                
+                
+                
+                
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+                
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+                
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+                
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+                
+                
+                
+                
+                
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+                
+                
+            
+        
+        
+            AARM
+            2
+            
+                10
+                1
+                1
+                
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+                
+                
+                
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+                1
+                
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+            
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+        
+            CUSTOM
+            3
+            
+                
+                
+                0
+            
+        
+        
+            BICOMP
+            0
+            
+        
+        
+            BUILDACTION
+            1
+            
+                
+                
+            
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+        
+            ILINK
+            0
+            
+                22
+                1
+                1
+                
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+                
+                
+                
+                
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+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
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+        
+            IARCHIVE
+            0
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+                0
+                1
+                1
+                
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+                
+            
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+        
+            BILINK
+            0
+            
+        
+    
+
diff --git a/bsp/stm32/stm32f103-mini-system/template.eww b/bsp/nuvoton/numaker-m2354/template.eww
similarity index 100%
rename from bsp/stm32/stm32f103-mini-system/template.eww
rename to bsp/nuvoton/numaker-m2354/template.eww
diff --git a/bsp/nuvoton/numaker-m2354/template.uvprojx b/bsp/nuvoton/numaker-m2354/template.uvprojx
new file mode 100644
index 0000000000..cf94da054b
--- /dev/null
+++ b/bsp/nuvoton/numaker-m2354/template.uvprojx
@@ -0,0 +1,390 @@
+
+
+
+  2.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      rtthread-m2354
+      0x4
+      ARM-ADS
+      6100001::V6.10.1::.\ARMCLANG
+      1
+      
+        
+          M2354KJFAE
+          Nuvoton
+          Nuvoton.NuMicro_DFP.1.3.10
+          http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack
+          IRAM(0x20000000,0x40000) IROM(0x00000000,0x100000) CPUTYPE("Cortex-M23") TZ CLOCK(12000000) ESEL ELITTLE
+          
+          
+          UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0M2354_AP_1M -FS00 -FL0100000 -FP0($$Device:M2354KJFAE$Flash\M2354_AP_1M.FLM))
+          0
+          $$Device:M2354KJFAE$Device\M2354\Include\M2354.h
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:M2354KJFAE$SVD\Nuvoton\M2354.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          .\build\keil5\
+          rtthread
+          1
+          0
+          1
+          1
+          1
+          .\build\keil5\
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            1
+            1
+            fromelf --bin ".\build\keil5\\@L.axf" --output ".\build\keil5\\@L.bin"
+            fromelf --text -c ".\build\keil5\\@L.axf" --output ".\build\keil5\\@L.txt"
+            0
+            0
+            0
+            0
+          
+          1
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          1
+        
+        
+          
+          
+          
+          
+          SARMV8M.DLL
+           -MPU
+          TCM.DLL
+          -pCM23
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4101
+          
+          1
+          BIN\UL2V8M.DLL
+          "" ()
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
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+            1
+            1
+            0
+            1
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+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M23"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            8
+            0
+            1
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x40000
+              
+              
+                1
+                0x0
+                0x100000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x100000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x40000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            5
+            3
+            0
+            0
+            0
+            1
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            1
+            0
+            0
+            1
+            0
+            0
+            1
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x00000000
+            0x20000000
+            
+            .\linking_scripts\m2354_flash.sct
+            
+            
+            --map --first='startup_M2354.o(RESET)' --datacompressor=off --info=inline --entry Reset_Handler
+            
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+    
+  
+
+
diff --git a/bsp/nv32f100x/app/src/ledapp.c b/bsp/nv32f100x/app/src/ledapp.c
index 2464f0e34b..129b906a96 100644
--- a/bsp/nv32f100x/app/src/ledapp.c
+++ b/bsp/nv32f100x/app/src/ledapp.c
@@ -1,17 +1,13 @@
 /*
- * File      : ledapp.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2017-09-19     Quintin.Z    the first version
  */
- 
+
 #include 
 #include 
 #include 
@@ -25,11 +21,11 @@ void led_thread_entry(void* parameter)
 {
 
     GPIO_Init  (GPIOA, GPIO_PTB5_MASK, GPIO_PinOutput);
-    
-	while(1)
-	{
+
+    while(1)
+    {
         GPIO_Toggle  (GPIOA, GPIO_PTB5_MASK);
         rt_thread_delay(RT_TICK_PER_SECOND / 10);
 
-	}
+    }
 }
diff --git a/bsp/nv32f100x/app/src/main.c b/bsp/nv32f100x/app/src/main.c
index b63fa2f4dc..813878bc9f 100644
--- a/bsp/nv32f100x/app/src/main.c
+++ b/bsp/nv32f100x/app/src/main.c
@@ -1,21 +1,7 @@
 /*
- * File      : _main.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/nv32f100x/board/inc/board.h b/bsp/nv32f100x/board/inc/board.h
index 3639fa0b03..08acc7a77b 100644
--- a/bsp/nv32f100x/board/inc/board.h
+++ b/bsp/nv32f100x/board/inc/board.h
@@ -1,11 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/nv32f100x/board/inc/drv_uart.h b/bsp/nv32f100x/board/inc/drv_uart.h
index d1e0c6c109..4a98e3ee14 100644
--- a/bsp/nv32f100x/board/inc/drv_uart.h
+++ b/bsp/nv32f100x/board/inc/drv_uart.h
@@ -1,11 +1,7 @@
 /*
- * File      : drv_uart.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/nv32f100x/board/src/board.c b/bsp/nv32f100x/board/src/board.c
index 43c7910384..372099a6ba 100644
--- a/bsp/nv32f100x/board/src/board.c
+++ b/bsp/nv32f100x/board/src/board.c
@@ -1,11 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -54,11 +50,11 @@ extern int __bss_end;
 *******************************************************************************/
 void assert_failed(uint8_t* file, uint32_t line)
 {
-	rt_kprintf("\n\r Wrong parameter value detected on\r\n");
-	rt_kprintf("       file  %s\r\n", file);
-	rt_kprintf("       line  %d\r\n", line);
+    rt_kprintf("\n\r Wrong parameter value detected on\r\n");
+    rt_kprintf("       file  %s\r\n", file);
+    rt_kprintf("       line  %d\r\n", line);
 
-	while (1) ;
+    while (1) ;
 }
 
 /**
@@ -98,7 +94,7 @@ void rt_hw_board_init()
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
 
-    
+
 #ifdef RT_USING_HEAP
     rt_system_heap_init((void*)NV32_SRAM_BEGIN, (void*)NV32_SRAM_END);
 #endif
diff --git a/bsp/nv32f100x/board/src/drv_uart.c b/bsp/nv32f100x/board/src/drv_uart.c
index d8629d804d..89bac6eb76 100644
--- a/bsp/nv32f100x/board/src/drv_uart.c
+++ b/bsp/nv32f100x/board/src/drv_uart.c
@@ -1,11 +1,7 @@
 /*
- * File      : drv_uart.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/pic32ethernet/application.c b/bsp/pic32ethernet/application.c
index 234a5acc50..ae2238f60b 100644
--- a/bsp/pic32ethernet/application.c
+++ b/bsp/pic32ethernet/application.c
@@ -1,11 +1,7 @@
 /*
- * File      : application.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -33,7 +29,7 @@ void thread_led1_entry(void* parameter)
 
 static void thread_led2_entry(void* parameter)
 {
-	// configure PORTD.RD2 = output
+    // configure PORTD.RD2 = output
     mPORTDSetPinsDigitalOut(BIT_2);
 
     while (1)
diff --git a/bsp/pic32ethernet/board.c b/bsp/pic32ethernet/board.c
index 8daa9b7123..5a738af8b1 100644
--- a/bsp/pic32ethernet/board.c
+++ b/bsp/pic32ethernet/board.c
@@ -1,11 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2011, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -36,12 +32,12 @@
 #pragma config DEBUG    = OFF           // Debugger Disabled for Starter Kit
 
 //  The following is used by the main application
-#define SYS_FREQ		(80000000UL)
+#define SYS_FREQ        (80000000UL)
 
-#define PB_DIV         		(1 << ((OSCCON&_OSCCON_PBDIV0_MASK)>>_OSCCON_PBDIV0_POSITION) )
-#define PRESCALE       		256
-#define TOGGLES_PER_SEC		RT_TICK_PER_SECOND
-#define T1_TICK       		(SYS_FREQ/PB_DIV/PRESCALE/TOGGLES_PER_SEC)
+#define PB_DIV              (1 << ((OSCCON&_OSCCON_PBDIV0_MASK)>>_OSCCON_PBDIV0_POSITION) )
+#define PRESCALE            256
+#define TOGGLES_PER_SEC     RT_TICK_PER_SECOND
+#define T1_TICK             (SYS_FREQ/PB_DIV/PRESCALE/TOGGLES_PER_SEC)
 
 static void rt_hw_show_info(void)
 {
@@ -68,18 +64,18 @@ static void rt_hw_timer_handler(void)
 void rt_hw_board_init()
 {
     // Configure the device for maximum performance, but do not change the PBDIV clock divisor.
-	// Given the options, this function will change the program Flash wait states,
-	// RAM wait state and enable prefetch cache, but will not change the PBDIV.
+    // Given the options, this function will change the program Flash wait states,
+    // RAM wait state and enable prefetch cache, but will not change the PBDIV.
     // The PBDIV value is already set via the pragma FPBDIV option above.
-   	SYSTEMConfig(SYS_FREQ, SYS_CFG_WAIT_STATES | SYS_CFG_PCACHE);
+    SYSTEMConfig(SYS_FREQ, SYS_CFG_WAIT_STATES | SYS_CFG_PCACHE);
 
-   	/* use DBPRINTF */
-   	/* rt_hw_console_init(); */
+    /* use DBPRINTF */
+    /* rt_hw_console_init(); */
 
-	rt_hw_usart_init();
-	rt_console_set_device("uart1");
+    rt_hw_usart_init();
+    rt_console_set_device("uart1");
 
-   	rt_hw_show_info();
+    rt_hw_show_info();
 
     // enable multi-vector interrupts
     INTEnableSystemMultiVectoredInt();
@@ -97,7 +93,7 @@ void rt_hw_board_init()
     ConfigIntTimer1(T1_INT_ON | T1_INT_PRIOR_2);
 
     /* Setup the software interrupt. */
-	mConfigIntCoreSW0( CSW_INT_ON | CSW_INT_PRIOR_1 | CSW_INT_SUB_PRIOR_0 );
+    mConfigIntCoreSW0( CSW_INT_ON | CSW_INT_PRIOR_1 | CSW_INT_SUB_PRIOR_0 );
 }
 
 void __ISR(_TIMER_1_VECTOR, ipl2) Timer1Handler(void)
diff --git a/bsp/pic32ethernet/console.c b/bsp/pic32ethernet/console.c
index fe8566203b..35c6725cf2 100644
--- a/bsp/pic32ethernet/console.c
+++ b/bsp/pic32ethernet/console.c
@@ -1,11 +1,7 @@
 /*
- * File      : console.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2011, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -23,8 +19,8 @@
 
 void rt_hw_console_init(void)
 {
-	//Initialize the DB_UTILS IO channel
-//	DBINIT();
+    //Initialize the DB_UTILS IO channel
+//  DBINIT();
 }
 
 /**
diff --git a/bsp/pic32ethernet/startup.c b/bsp/pic32ethernet/startup.c
index e139dfefca..372440d711 100644
--- a/bsp/pic32ethernet/startup.c
+++ b/bsp/pic32ethernet/startup.c
@@ -1,11 +1,7 @@
 /*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -29,55 +25,55 @@ extern void finsh_set_device(const char* device);
  */
 void rtthread_startup(void)
 {
-	/* init board */
-	rt_hw_board_init();
+    /* init board */
+    rt_hw_board_init();
 
-	/* show version */
-	rt_show_version();
+    /* show version */
+    rt_show_version();
 
-	/* init timer system */
-	rt_system_timer_init();
+    /* init timer system */
+    rt_system_timer_init();
 
 #ifdef RT_USING_HEAP
     /* init memory system */
     rt_system_heap_init((void*)&_ramfunc_end, (void*)PIC32_SRAM_END);
 #endif
 
-	/* init scheduler system */
-	rt_system_scheduler_init();
+    /* init scheduler system */
+    rt_system_scheduler_init();
 
-	/* init application */
-	rt_application_init();
+    /* init application */
+    rt_application_init();
 
 #ifdef RT_USING_FINSH
-	/* init finsh */
-	finsh_system_init();
+    /* init finsh */
+    finsh_system_init();
 #ifdef RT_USING_DEVICE
-	finsh_set_device("uart1");
+    finsh_set_device("uart1");
 #endif
 #endif
 
     /* init timer thread */
     rt_system_timer_thread_init();
 
-	/* init idle thread */
-	rt_thread_idle_init();
+    /* init idle thread */
+    rt_thread_idle_init();
 
-	/* start scheduler */
-	rt_system_scheduler_start();
+    /* start scheduler */
+    rt_system_scheduler_start();
 
-	/* never reach here */
-	return ;
+    /* never reach here */
+    return ;
 }
 
 int main(void)
 {
-	/* disable interrupt first */
-	rt_hw_interrupt_disable();
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
 
-	/* startup RT-Thread RTOS */
-	rtthread_startup();
+    /* startup RT-Thread RTOS */
+    rtthread_startup();
 
-	return 0;
+    return 0;
 }
 
diff --git a/bsp/qemu-vexpress-gemini/applications/application.c b/bsp/qemu-vexpress-gemini/applications/application.c
index c0160df189..b65c758208 100644
--- a/bsp/qemu-vexpress-gemini/applications/application.c
+++ b/bsp/qemu-vexpress-gemini/applications/application.c
@@ -1,11 +1,7 @@
 /*
- * File      : application.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -23,7 +19,7 @@ int rt_application_init()
 {
     rt_thread_t tid;
 
-    tid = rt_thread_create("init", init_thread, RT_NULL, 
+    tid = rt_thread_create("init", init_thread, RT_NULL,
         1024, RT_THREAD_PRIORITY_MAX/3, 10);
     if (tid != RT_NULL) rt_thread_startup(tid);
 
diff --git a/bsp/qemu-vexpress-gemini/applications/startup.c b/bsp/qemu-vexpress-gemini/applications/startup.c
index fa17c0571b..2c37bb4726 100644
--- a/bsp/qemu-vexpress-gemini/applications/startup.c
+++ b/bsp/qemu-vexpress-gemini/applications/startup.c
@@ -1,11 +1,7 @@
 /*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/qemu-vexpress-gemini/cpu/context_gcc.S b/bsp/qemu-vexpress-gemini/cpu/context_gcc.S
index 01593a7c0a..2b8206b01b 100644
--- a/bsp/qemu-vexpress-gemini/cpu/context_gcc.S
+++ b/bsp/qemu-vexpress-gemini/cpu/context_gcc.S
@@ -1,21 +1,7 @@
 /*
- * File      : context.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/qemu-vexpress-gemini/cpu/cp15_gcc.S b/bsp/qemu-vexpress-gemini/cpu/cp15_gcc.S
index f1ed6492aa..f299cc4acb 100644
--- a/bsp/qemu-vexpress-gemini/cpu/cp15_gcc.S
+++ b/bsp/qemu-vexpress-gemini/cpu/cp15_gcc.S
@@ -1,22 +1,7 @@
 /*
- * File      : cp15_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013, RT-Thread Development Team
- * http://www.rt-thread.org
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/qemu-vexpress-gemini/cpu/cpu.c b/bsp/qemu-vexpress-gemini/cpu/cpu.c
index 7dd426e4dd..5f82671c1b 100644
--- a/bsp/qemu-vexpress-gemini/cpu/cpu.c
+++ b/bsp/qemu-vexpress-gemini/cpu/cpu.c
@@ -1,11 +1,7 @@
 /*
- * File      : cpu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -24,14 +20,14 @@
 /** shutdown CPU */
 void rt_hw_cpu_shutdown()
 {
-	rt_uint32_t level;
-	rt_kprintf("shutdown...\n");
+    rt_uint32_t level;
+    rt_kprintf("shutdown...\n");
 
-	level = rt_hw_interrupt_disable();
-	while (level)
-	{
-		RT_ASSERT(0);
-	}
+    level = rt_hw_interrupt_disable();
+    while (level)
+    {
+        RT_ASSERT(0);
+    }
 }
 
 /*@}*/
diff --git a/bsp/qemu-vexpress-gemini/cpu/gic.c b/bsp/qemu-vexpress-gemini/cpu/gic.c
index 4cff1bad3e..962317821a 100644
--- a/bsp/qemu-vexpress-gemini/cpu/gic.c
+++ b/bsp/qemu-vexpress-gemini/cpu/gic.c
@@ -1,11 +1,7 @@
 /*
- * File      : gic.c, ARM Generic Interrupt Controller
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013-2014, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/qemu-vexpress-gemini/cpu/gic.h b/bsp/qemu-vexpress-gemini/cpu/gic.h
index 41a7727da2..7c781ad4d9 100644
--- a/bsp/qemu-vexpress-gemini/cpu/gic.h
+++ b/bsp/qemu-vexpress-gemini/cpu/gic.h
@@ -1,11 +1,7 @@
 /*
- * File      : gic.h, ARM Generic Interrupt Controller
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/qemu-vexpress-gemini/cpu/interrupt.c b/bsp/qemu-vexpress-gemini/cpu/interrupt.c
index 889f74b5ca..70f745a120 100644
--- a/bsp/qemu-vexpress-gemini/cpu/interrupt.c
+++ b/bsp/qemu-vexpress-gemini/cpu/interrupt.c
@@ -1,11 +1,7 @@
 /*
- * File      : interrupt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013-2014, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/qemu-vexpress-gemini/cpu/interrupt.h b/bsp/qemu-vexpress-gemini/cpu/interrupt.h
index d81f1c81ae..90f392f407 100644
--- a/bsp/qemu-vexpress-gemini/cpu/interrupt.h
+++ b/bsp/qemu-vexpress-gemini/cpu/interrupt.h
@@ -1,11 +1,7 @@
 /*
- * File      : interrupt.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2011, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -18,28 +14,28 @@
 #define INT_IRQ     0x00
 #define INT_FIQ     0x01
 
-#define INTC_REVISION(hw_base) 		    REG32((hw_base) + 0x0)
-#define INTC_SYSCONFIG(hw_base) 		REG32((hw_base) + 0x10)
-#define INTC_SYSSTATUS(hw_base) 		REG32((hw_base) + 0x14)
-#define INTC_SIR_IRQ(hw_base) 		    REG32((hw_base) + 0x40)
-#define INTC_SIR_FIQ(hw_base) 		    REG32((hw_base) + 0x44)
-#define INTC_CONTROL(hw_base) 		    REG32((hw_base) + 0x48)
-#define INTC_PROTECTION(hw_base) 	    REG32((hw_base) + 0x4c)
-#define INTC_IDLE(hw_base)  			REG32((hw_base) + 0x50)
-#define INTC_IRQ_PRIORITY(hw_base) 	    REG32((hw_base) + 0x60)
-#define INTC_FIQ_PRIORITY(hw_base) 	    REG32((hw_base) + 0x64)
-#define INTC_THRESHOLD(hw_base) 		REG32((hw_base) + 0x68)
-#define INTC_SICR(hw_base)  			REG32((hw_base) + 0x6c)
-#define INTC_SCR(hw_base, n) 		    REG32((hw_base) + 0x70 + ((n) * 0x04))
-#define INTC_ITR(hw_base, n) 		    REG32((hw_base) + 0x80 + ((n) * 0x20))
-#define INTC_MIR(hw_base, n) 		    REG32((hw_base) + 0x84 + ((n) * 0x20))
-#define INTC_MIR_CLEAR(hw_base, n)  	REG32((hw_base) + 0x88 + ((n) * 0x20))
-#define INTC_MIR_SET(hw_base, n) 	    REG32((hw_base) + 0x8c + ((n) * 0x20))
-#define INTC_ISR_SET(hw_base, n) 	    REG32((hw_base) + 0x90 + ((n) * 0x20))
-#define INTC_ISR_CLEAR(hw_base, n) 	    REG32((hw_base) + 0x94 + ((n) * 0x20))
+#define INTC_REVISION(hw_base)          REG32((hw_base) + 0x0)
+#define INTC_SYSCONFIG(hw_base)         REG32((hw_base) + 0x10)
+#define INTC_SYSSTATUS(hw_base)         REG32((hw_base) + 0x14)
+#define INTC_SIR_IRQ(hw_base)           REG32((hw_base) + 0x40)
+#define INTC_SIR_FIQ(hw_base)           REG32((hw_base) + 0x44)
+#define INTC_CONTROL(hw_base)           REG32((hw_base) + 0x48)
+#define INTC_PROTECTION(hw_base)        REG32((hw_base) + 0x4c)
+#define INTC_IDLE(hw_base)              REG32((hw_base) + 0x50)
+#define INTC_IRQ_PRIORITY(hw_base)      REG32((hw_base) + 0x60)
+#define INTC_FIQ_PRIORITY(hw_base)      REG32((hw_base) + 0x64)
+#define INTC_THRESHOLD(hw_base)         REG32((hw_base) + 0x68)
+#define INTC_SICR(hw_base)              REG32((hw_base) + 0x6c)
+#define INTC_SCR(hw_base, n)            REG32((hw_base) + 0x70 + ((n) * 0x04))
+#define INTC_ITR(hw_base, n)            REG32((hw_base) + 0x80 + ((n) * 0x20))
+#define INTC_MIR(hw_base, n)            REG32((hw_base) + 0x84 + ((n) * 0x20))
+#define INTC_MIR_CLEAR(hw_base, n)      REG32((hw_base) + 0x88 + ((n) * 0x20))
+#define INTC_MIR_SET(hw_base, n)        REG32((hw_base) + 0x8c + ((n) * 0x20))
+#define INTC_ISR_SET(hw_base, n)        REG32((hw_base) + 0x90 + ((n) * 0x20))
+#define INTC_ISR_CLEAR(hw_base, n)      REG32((hw_base) + 0x94 + ((n) * 0x20))
 #define INTC_PENDING_IRQ(hw_base, n)    REG32((hw_base) + 0x98 + ((n) * 0x20))
 #define INTC_PENDING_FIQ(hw_base, n)    REG32((hw_base) + 0x9c + ((n) * 0x20))
-#define INTC_ILR(hw_base, n)  		    REG32((hw_base) + 0x100 + ((n) * 0x04))
+#define INTC_ILR(hw_base, n)            REG32((hw_base) + 0x100 + ((n) * 0x04))
 
 void rt_hw_interrupt_control(int vector, int priority, int route);
 int rt_hw_interrupt_get_active(int fiq_irq);
diff --git a/bsp/qemu-vexpress-gemini/cpu/mmu.c b/bsp/qemu-vexpress-gemini/cpu/mmu.c
index b2503e4260..f4d6068099 100644
--- a/bsp/qemu-vexpress-gemini/cpu/mmu.c
+++ b/bsp/qemu-vexpress-gemini/cpu/mmu.c
@@ -1,11 +1,7 @@
 /*
- * File      : mmu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/qemu-vexpress-gemini/cpu/stack.c b/bsp/qemu-vexpress-gemini/cpu/stack.c
index 4ae1536a20..c1d9262d4b 100644
--- a/bsp/qemu-vexpress-gemini/cpu/stack.c
+++ b/bsp/qemu-vexpress-gemini/cpu/stack.c
@@ -1,11 +1,7 @@
 /*
- * File      : stack.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2011, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -24,42 +20,42 @@
  * This function will initialize thread stack
  *
  * @param tentry the entry of thread
- * @param parameter the parameter of entry 
+ * @param parameter the parameter of entry
  * @param stack_addr the beginning stack address
  * @param texit the function will be called when thread exit
  *
  * @return stack address
  */
 rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
-	rt_uint8_t *stack_addr, void *texit)
+    rt_uint8_t *stack_addr, void *texit)
 {
-	rt_uint32_t *stk;
+    rt_uint32_t *stk;
 
-	stk 	 = (rt_uint32_t*)stack_addr;
-	*(stk) 	 = (rt_uint32_t)tentry;			/* entry point */
-	*(--stk) = (rt_uint32_t)texit;			/* lr */
-	*(--stk) = 0;							/* r12 */
-	*(--stk) = 0;							/* r11 */
-	*(--stk) = 0;							/* r10 */
-	*(--stk) = 0;							/* r9 */
-	*(--stk) = 0;							/* r8 */
-	*(--stk) = 0;							/* r7 */
-	*(--stk) = 0;							/* r6 */
-	*(--stk) = 0;							/* r5 */
-	*(--stk) = 0;							/* r4 */
-	*(--stk) = 0;							/* r3 */
-	*(--stk) = 0;							/* r2 */
-	*(--stk) = 0;							/* r1 */
-	*(--stk) = (rt_uint32_t)parameter;		/* r0 : argument */
+    stk      = (rt_uint32_t*)stack_addr;
+    *(stk)   = (rt_uint32_t)tentry;         /* entry point */
+    *(--stk) = (rt_uint32_t)texit;          /* lr */
+    *(--stk) = 0;                           /* r12 */
+    *(--stk) = 0;                           /* r11 */
+    *(--stk) = 0;                           /* r10 */
+    *(--stk) = 0;                           /* r9 */
+    *(--stk) = 0;                           /* r8 */
+    *(--stk) = 0;                           /* r7 */
+    *(--stk) = 0;                           /* r6 */
+    *(--stk) = 0;                           /* r5 */
+    *(--stk) = 0;                           /* r4 */
+    *(--stk) = 0;                           /* r3 */
+    *(--stk) = 0;                           /* r2 */
+    *(--stk) = 0;                           /* r1 */
+    *(--stk) = (rt_uint32_t)parameter;      /* r0 : argument */
 
-	/* cpsr */
-	if ((rt_uint32_t)tentry & 0x01)
-		*(--stk) = SVCMODE | 0x20;			/* thumb mode */
-	else
-		*(--stk) = SVCMODE;					/* arm mode   */
+    /* cpsr */
+    if ((rt_uint32_t)tentry & 0x01)
+        *(--stk) = SVCMODE | 0x20;          /* thumb mode */
+    else
+        *(--stk) = SVCMODE;                 /* arm mode   */
 
-	/* return task's current stack address */
-	return (rt_uint8_t *)stk;
+    /* return task's current stack address */
+    return (rt_uint8_t *)stk;
 }
 
 /*@}*/
diff --git a/bsp/qemu-vexpress-gemini/cpu/start_gcc.S b/bsp/qemu-vexpress-gemini/cpu/start_gcc.S
index 0c64d9fecf..404e1df9c3 100644
--- a/bsp/qemu-vexpress-gemini/cpu/start_gcc.S
+++ b/bsp/qemu-vexpress-gemini/cpu/start_gcc.S
@@ -1,21 +1,7 @@
 /*
- * File      : start_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013-2014, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -215,35 +201,35 @@ rt_hw_context_switch_interrupt_do:
 .endm
 
     .align  5
-    .globl	vector_swi
+    .globl  vector_swi
 vector_swi:
     push_svc_reg
     bl      rt_hw_trap_swi
     b       .
 
     .align  5
-    .globl	vector_undef
+    .globl  vector_undef
 vector_undef:
     push_svc_reg
     bl      rt_hw_trap_undef
     b       .
 
     .align  5
-    .globl	vector_pabt
+    .globl  vector_pabt
 vector_pabt:
     push_svc_reg
     bl      rt_hw_trap_pabt
     b       .
 
     .align  5
-    .globl	vector_dabt
+    .globl  vector_dabt
 vector_dabt:
     push_svc_reg
     bl      rt_hw_trap_dabt
     b       .
 
     .align  5
-    .globl	vector_resv
+    .globl  vector_resv
 vector_resv:
     push_svc_reg
     bl      rt_hw_trap_resv
diff --git a/bsp/qemu-vexpress-gemini/cpu/trap.c b/bsp/qemu-vexpress-gemini/cpu/trap.c
index a6397d20d2..c6ca45aee7 100644
--- a/bsp/qemu-vexpress-gemini/cpu/trap.c
+++ b/bsp/qemu-vexpress-gemini/cpu/trap.c
@@ -1,11 +1,7 @@
 /*
- * File      : trap.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -135,7 +131,7 @@ void rt_hw_trap_resv(struct rt_hw_exp_stack *regs)
     rt_hw_cpu_shutdown();
 }
 
-#define GIC_ACK_INTID_MASK					0x000003ff
+#define GIC_ACK_INTID_MASK                  0x000003ff
 
 void rt_hw_trap_irq(void)
 {
diff --git a/bsp/qemu-vexpress-gemini/cpu/vector_gcc.S b/bsp/qemu-vexpress-gemini/cpu/vector_gcc.S
index 4a44a7395c..b5ab2042d9 100644
--- a/bsp/qemu-vexpress-gemini/cpu/vector_gcc.S
+++ b/bsp/qemu-vexpress-gemini/cpu/vector_gcc.S
@@ -1,21 +1,7 @@
 /*
- * File      : vector_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -62,4 +48,4 @@ _vector_irq:
 _vector_fiq:
     .word vector_fiq
 
-.balignl 	16,0xdeadbeef
+.balignl    16,0xdeadbeef
diff --git a/bsp/qemu-vexpress-gemini/drivers/board.c b/bsp/qemu-vexpress-gemini/drivers/board.c
index 3de322c52e..990ec3779a 100644
--- a/bsp/qemu-vexpress-gemini/drivers/board.c
+++ b/bsp/qemu-vexpress-gemini/drivers/board.c
@@ -1,11 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/qemu-vexpress-gemini/drivers/board.h b/bsp/qemu-vexpress-gemini/drivers/board.h
index 0a9bb3670c..23ccc52233 100644
--- a/bsp/qemu-vexpress-gemini/drivers/board.h
+++ b/bsp/qemu-vexpress-gemini/drivers/board.h
@@ -1,11 +1,7 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/qemu-vexpress-gemini/drivers/serial.c b/bsp/qemu-vexpress-gemini/drivers/serial.c
index 92e8b949fa..eff3205a2d 100644
--- a/bsp/qemu-vexpress-gemini/drivers/serial.c
+++ b/bsp/qemu-vexpress-gemini/drivers/serial.c
@@ -1,26 +1,7 @@
 /*
- *  serial.c UART driver
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd
- *
- *  This file is part of RT-Thread (http://www.rt-thread.org)
- *  Maintainer: bernard.xiong 
- *
- *  All rights reserved.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/qemu-vexpress-gemini/drivers/serial.h b/bsp/qemu-vexpress-gemini/drivers/serial.h
index 52e6f07ea3..dceea68d1f 100644
--- a/bsp/qemu-vexpress-gemini/drivers/serial.h
+++ b/bsp/qemu-vexpress-gemini/drivers/serial.h
@@ -1,26 +1,7 @@
 /*
- *  UART driver
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd
- *
- *  This file is part of RT-Thread (http://www.rt-thread.org)
- *  Maintainer: bernard.xiong 
- *
- *  All rights reserved.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/qemu-vexpress-gemini/drivers/vbus_drv.c b/bsp/qemu-vexpress-gemini/drivers/vbus_drv.c
index 0f522a271d..939838b67c 100644
--- a/bsp/qemu-vexpress-gemini/drivers/vbus_drv.c
+++ b/bsp/qemu-vexpress-gemini/drivers/vbus_drv.c
@@ -1,26 +1,7 @@
 /*
- * VMM Bus Driver
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * COPYRIGHT (C) 2015, Shanghai Real-Thread Technology Co., Ltd
- *      http://www.rt-thread.com
- *
- *  This file is part of RT-Thread (http://www.rt-thread.org)
- *
- *  All rights reserved.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/qemu-vexpress-gemini/drivers/vbus_hw.h b/bsp/qemu-vexpress-gemini/drivers/vbus_hw.h
index 19c6fcc902..6ad9c4d561 100644
--- a/bsp/qemu-vexpress-gemini/drivers/vbus_hw.h
+++ b/bsp/qemu-vexpress-gemini/drivers/vbus_hw.h
@@ -1,25 +1,7 @@
 /*
- * VMM Bus
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * COPYRIGHT (C) 2015, Shanghai Real-Thread Technology Co., Ltd
- *
- *  This file is part of RT-Thread (http://www.rt-thread.org)
- *
- *  All rights reserved.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/raspberry-pi/raspi2/applications/main.c b/bsp/raspberry-pi/raspi2/applications/main.c
index 101386fdfd..548881ae4b 100644
--- a/bsp/raspberry-pi/raspi2/applications/main.c
+++ b/bsp/raspberry-pi/raspi2/applications/main.c
@@ -1,21 +1,7 @@
 /*
- * File      : main.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/raspberry-pi/raspi2/applications/mnt.c b/bsp/raspberry-pi/raspi2/applications/mnt.c
index 8da1dc1ece..db45518cfb 100644
--- a/bsp/raspberry-pi/raspi2/applications/mnt.c
+++ b/bsp/raspberry-pi/raspi2/applications/mnt.c
@@ -1,21 +1,7 @@
 /*
- * File      : mnt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/raspberry-pi/raspi2/cpu/context_gcc.S b/bsp/raspberry-pi/raspi2/cpu/context_gcc.S
index 48402739f9..9d95d833c0 100644
--- a/bsp/raspberry-pi/raspi2/cpu/context_gcc.S
+++ b/bsp/raspberry-pi/raspi2/cpu/context_gcc.S
@@ -1,21 +1,7 @@
 /*
- * File      : context.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/raspberry-pi/raspi2/cpu/cp15_gcc.S b/bsp/raspberry-pi/raspi2/cpu/cp15_gcc.S
index f1ed6492aa..f299cc4acb 100644
--- a/bsp/raspberry-pi/raspi2/cpu/cp15_gcc.S
+++ b/bsp/raspberry-pi/raspi2/cpu/cp15_gcc.S
@@ -1,22 +1,7 @@
 /*
- * File      : cp15_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013, RT-Thread Development Team
- * http://www.rt-thread.org
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/raspberry-pi/raspi2/cpu/cpu.c b/bsp/raspberry-pi/raspi2/cpu/cpu.c
index 8bf16d19e8..5f82671c1b 100644
--- a/bsp/raspberry-pi/raspi2/cpu/cpu.c
+++ b/bsp/raspberry-pi/raspi2/cpu/cpu.c
@@ -1,11 +1,7 @@
 /*
- * File      : cpu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/raspberry-pi/raspi2/cpu/interrupt.c b/bsp/raspberry-pi/raspi2/cpu/interrupt.c
index 93513f3da3..7a48eaa9fd 100644
--- a/bsp/raspberry-pi/raspi2/cpu/interrupt.c
+++ b/bsp/raspberry-pi/raspi2/cpu/interrupt.c
@@ -1,11 +1,7 @@
 /*
- * File      : interrupt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013-2014, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/raspberry-pi/raspi2/cpu/mmu.c b/bsp/raspberry-pi/raspi2/cpu/mmu.c
index b2503e4260..f4d6068099 100644
--- a/bsp/raspberry-pi/raspi2/cpu/mmu.c
+++ b/bsp/raspberry-pi/raspi2/cpu/mmu.c
@@ -1,11 +1,7 @@
 /*
- * File      : mmu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/raspberry-pi/raspi2/cpu/stack.c b/bsp/raspberry-pi/raspi2/cpu/stack.c
index e60e8c7170..3fe42b5db9 100644
--- a/bsp/raspberry-pi/raspi2/cpu/stack.c
+++ b/bsp/raspberry-pi/raspi2/cpu/stack.c
@@ -1,11 +1,7 @@
 /*
- * File      : stack.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2011, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/raspberry-pi/raspi2/cpu/start_gcc.S b/bsp/raspberry-pi/raspi2/cpu/start_gcc.S
index b60ad6a38f..cde901515d 100644
--- a/bsp/raspberry-pi/raspi2/cpu/start_gcc.S
+++ b/bsp/raspberry-pi/raspi2/cpu/start_gcc.S
@@ -1,21 +1,7 @@
 /*
- * File      : start_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013-2014, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -59,25 +45,25 @@ stack_top:
 /* reset entry */
 .globl _reset
 _reset:
-	/* Disable IRQ & FIQ */
-	cpsid if
+    /* Disable IRQ & FIQ */
+    cpsid if
 
-	/* Check for HYP mode */
-	mrs r0, cpsr_all
-	and r0, r0, #0x1F
-	mov r8, #0x1A
-	cmp r0, r8
-	beq overHyped
-	b continue
+    /* Check for HYP mode */
+    mrs r0, cpsr_all
+    and r0, r0, #0x1F
+    mov r8, #0x1A
+    cmp r0, r8
+    beq overHyped
+    b continue
 
 overHyped: /* Get out of HYP mode */
-	ldr r1, =continue
-	msr ELR_hyp, r1
-	mrs r1, cpsr_all
-	and r1, r1, #0x1f	;@ CPSR_MODE_MASK
-	orr r1, r1, #0x13	;@ CPSR_MODE_SUPERVISOR
-	msr SPSR_hyp, r1
-	eret
+    ldr r1, =continue
+    msr ELR_hyp, r1
+    mrs r1, cpsr_all
+    and r1, r1, #0x1f   ;@ CPSR_MODE_MASK
+    orr r1, r1, #0x13   ;@ CPSR_MODE_SUPERVISOR
+    msr SPSR_hyp, r1
+    eret
 
 continue:
 
@@ -115,7 +101,7 @@ stack_setup:
 
     @  Set the startup stack for svc
     mov     sp, r0
-	sub     r0, r0, #SVC_Stack_Size
+    sub     r0, r0, #SVC_Stack_Size
 
     @  Enter Undefined Instruction Mode and set its Stack Pointer
     msr     cpsr_c, #Mode_UND|I_Bit|F_Bit
diff --git a/bsp/raspberry-pi/raspi2/cpu/trap.c b/bsp/raspberry-pi/raspi2/cpu/trap.c
index 3012c26e2c..8a1eb33c65 100644
--- a/bsp/raspberry-pi/raspi2/cpu/trap.c
+++ b/bsp/raspberry-pi/raspi2/cpu/trap.c
@@ -1,11 +1,7 @@
 /*
- * File      : trap.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/raspberry-pi/raspi2/cpu/vector_gcc.S b/bsp/raspberry-pi/raspi2/cpu/vector_gcc.S
index 17c2d69c30..b5ab2042d9 100644
--- a/bsp/raspberry-pi/raspi2/cpu/vector_gcc.S
+++ b/bsp/raspberry-pi/raspi2/cpu/vector_gcc.S
@@ -1,21 +1,7 @@
 /*
- * File      : vector_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/raspberry-pi/raspi2/driver/bcm283x.h b/bsp/raspberry-pi/raspi2/driver/bcm283x.h
index 85422e2a22..8339133652 100644
--- a/bsp/raspberry-pi/raspi2/driver/bcm283x.h
+++ b/bsp/raspberry-pi/raspi2/driver/bcm283x.h
@@ -3,8 +3,8 @@
 
 #include 
 
-#define PER_BASE    		(0x3F000000)
-#define PER_BASE_40000000 	(0x40000000)
+#define PER_BASE            (0x3F000000)
+#define PER_BASE_40000000   (0x40000000)
 
 /*
  *  GPIO
@@ -50,17 +50,17 @@
 /*
  * ARM Timer
  */
-#define ARM_TIMER_BASE		(PER_BASE + 0xB000)
+#define ARM_TIMER_BASE      (PER_BASE + 0xB000)
 
-#define ARM_TIMER_LOAD		HWREG32(ARM_TIMER_BASE + 0x400)
-#define ARM_TIMER_VALUE		HWREG32(ARM_TIMER_BASE + 0x404)
-#define ARM_TIMER_CTRL		HWREG32(ARM_TIMER_BASE + 0x408)
-#define ARM_TIMER_IRQCLR	HWREG32(ARM_TIMER_BASE + 0x40C)
-#define ARM_TIMER_RAWIRQ	HWREG32(ARM_TIMER_BASE + 0x410)
-#define ARM_TIMER_MASKIRQ	HWREG32(ARM_TIMER_BASE + 0x414)
-#define ARM_TIMER_RELOAD	HWREG32(ARM_TIMER_BASE + 0x418)
-#define ARM_TIMER_PREDIV	HWREG32(ARM_TIMER_BASE + 0x41C)
-#define ARM_TIMER_CNTR		HWREG32(ARM_TIMER_BASE + 0x420)
+#define ARM_TIMER_LOAD      HWREG32(ARM_TIMER_BASE + 0x400)
+#define ARM_TIMER_VALUE     HWREG32(ARM_TIMER_BASE + 0x404)
+#define ARM_TIMER_CTRL      HWREG32(ARM_TIMER_BASE + 0x408)
+#define ARM_TIMER_IRQCLR    HWREG32(ARM_TIMER_BASE + 0x40C)
+#define ARM_TIMER_RAWIRQ    HWREG32(ARM_TIMER_BASE + 0x410)
+#define ARM_TIMER_MASKIRQ   HWREG32(ARM_TIMER_BASE + 0x414)
+#define ARM_TIMER_RELOAD    HWREG32(ARM_TIMER_BASE + 0x418)
+#define ARM_TIMER_PREDIV    HWREG32(ARM_TIMER_BASE + 0x41C)
+#define ARM_TIMER_CNTR      HWREG32(ARM_TIMER_BASE + 0x420)
 
 /*
  *  Core Timer
diff --git a/bsp/raspberry-pi/raspi2/driver/board.c b/bsp/raspberry-pi/raspi2/driver/board.c
index 78cac6ba4d..a5e822f168 100644
--- a/bsp/raspberry-pi/raspi2/driver/board.c
+++ b/bsp/raspberry-pi/raspi2/driver/board.c
@@ -1,21 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/raspberry-pi/raspi2/driver/board.h b/bsp/raspberry-pi/raspi2/driver/board.h
index 92ef5de76c..1c71cd7744 100644
--- a/bsp/raspberry-pi/raspi2/driver/board.h
+++ b/bsp/raspberry-pi/raspi2/driver/board.h
@@ -1,21 +1,7 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/raspberry-pi/raspi2/driver/drv_uart.c b/bsp/raspberry-pi/raspi2/driver/drv_uart.c
index de7b987c2a..b25a3a5c8b 100644
--- a/bsp/raspberry-pi/raspi2/driver/drv_uart.c
+++ b/bsp/raspberry-pi/raspi2/driver/drv_uart.c
@@ -1,21 +1,7 @@
 /*
- * File      : drv_uart.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/raspberry-pi/raspi2/driver/drv_uart.h b/bsp/raspberry-pi/raspi2/driver/drv_uart.h
index e489eaae65..76072f938e 100644
--- a/bsp/raspberry-pi/raspi2/driver/drv_uart.h
+++ b/bsp/raspberry-pi/raspi2/driver/drv_uart.h
@@ -1,21 +1,7 @@
 /*
- * File      : drv_uart.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/raspberry-pi/raspi2/link.lds b/bsp/raspberry-pi/raspi2/link.lds
index 75e0845943..2624a5a95d 100644
--- a/bsp/raspberry-pi/raspi2/link.lds
+++ b/bsp/raspberry-pi/raspi2/link.lds
@@ -1,20 +1,7 @@
 /*
- * File      : link.lds
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * 2017-5-30     bernard       first version
diff --git a/bsp/raspberry-pi/raspi3-32/applications/main.c b/bsp/raspberry-pi/raspi3-32/applications/main.c
index cda0e0d711..de0fe56137 100644
--- a/bsp/raspberry-pi/raspi3-32/applications/main.c
+++ b/bsp/raspberry-pi/raspi3-32/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-32/applications/mnt.c b/bsp/raspberry-pi/raspi3-32/applications/mnt.c
index 88b714022c..44450fe9b6 100644
--- a/bsp/raspberry-pi/raspi3-32/applications/mnt.c
+++ b/bsp/raspberry-pi/raspi3-32/applications/mnt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-32/applications/test_device.c b/bsp/raspberry-pi/raspi3-32/applications/test_device.c
index 7efb1cfb64..ec7e480212 100644
--- a/bsp/raspberry-pi/raspi3-32/applications/test_device.c
+++ b/bsp/raspberry-pi/raspi3-32/applications/test_device.c
@@ -1,6 +1,6 @@
 /*
  * File      : test_driver.h
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -50,7 +50,7 @@ void test_hdmi()
     int i=0;
     for (; i < 20; i++)  colors[i] = COLOR_RED;
     rt_graphix_ops(hdmi) -> blit_line((char *)colors, 20, 20, 20);
-    
+
 #endif
 }
 
@@ -73,8 +73,8 @@ void test_cpusmp(void)
 {
     rt_kprintf("Hello Test SMP!\n");
 #ifdef RT_USING_SMP
-    int i;    
-    char test_name[RT_NAME_MAX]; 
+    int i;
+    char test_name[RT_NAME_MAX];
     for (i = 0; i < _CPUS_NR; i++)
     {
         rt_sprintf(test_name, "smp%d", i);
@@ -162,17 +162,17 @@ void test_i2c(void)
         rt_kprintf("can't find %s device!\n", name);
     else
     {
-    	read_regs(i2c_bus, 7, buf);
-    	buf[0] = buf[0]&0x7F; //sec
-    	buf[1] = buf[1]&0x7F; //min
-    	buf[2] = buf[2]&0x3F; //hour
-    	buf[3] = buf[3]&0x07; //week
-    	buf[4] = buf[4]&0x3F; //day
-    	buf[5] = buf[5]&0x1F; //mouth
-    	//year/month/day
-    	rt_kprintf("20%02x-%02x-%02x ",buf[6],buf[5],buf[4]);
-    	//hour:minute/second
-    	rt_kprintf("%02x:%02x:%02x \n",buf[2],buf[1],buf[0]);
+        read_regs(i2c_bus, 7, buf);
+        buf[0] = buf[0]&0x7F; //sec
+        buf[1] = buf[1]&0x7F; //min
+        buf[2] = buf[2]&0x3F; //hour
+        buf[3] = buf[3]&0x07; //week
+        buf[4] = buf[4]&0x3F; //day
+        buf[5] = buf[5]&0x1F; //mouth
+        //year/month/day
+        rt_kprintf("20%02x-%02x-%02x ",buf[6],buf[5],buf[4]);
+        //hour:minute/second
+        rt_kprintf("%02x:%02x:%02x \n",buf[2],buf[1],buf[0]);
     }
 #endif
 }
diff --git a/bsp/raspberry-pi/raspi3-32/cpu/armv7.h b/bsp/raspberry-pi/raspi3-32/cpu/armv7.h
index 859b0371b7..a992fdebd0 100644
--- a/bsp/raspberry-pi/raspi3-32/cpu/armv7.h
+++ b/bsp/raspberry-pi/raspi3-32/cpu/armv7.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-32/cpu/cp15.h b/bsp/raspberry-pi/raspi3-32/cpu/cp15.h
index 14b85b7e64..d8075c84df 100644
--- a/bsp/raspberry-pi/raspi3-32/cpu/cp15.h
+++ b/bsp/raspberry-pi/raspi3-32/cpu/cp15.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -57,7 +57,7 @@ static inline void send_ipi_msg(int cpu, int ipi_vector)
 
 static inline void setup_bootstrap_addr(int cpu, int addr)
 {
-	CORE_MAILBOX3_SET(cpu) = addr;
+    CORE_MAILBOX3_SET(cpu) = addr;
 }
 
 static inline void enable_cpu_ipi_intr(int cpu)
@@ -67,7 +67,7 @@ static inline void enable_cpu_ipi_intr(int cpu)
 
 static inline void enable_cpu_timer_intr(int cpu)
 {
-	CORETIMER_INTCTL(cpu) = 0x8;
+    CORETIMER_INTCTL(cpu) = 0x8;
 }
 
 static inline void enable_cntv(void)
diff --git a/bsp/raspberry-pi/raspi3-32/cpu/cpu.c b/bsp/raspberry-pi/raspi3-32/cpu/cpu.c
index 4d02ca35e1..b43b804597 100644
--- a/bsp/raspberry-pi/raspi3-32/cpu/cpu.c
+++ b/bsp/raspberry-pi/raspi3-32/cpu/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -52,7 +52,7 @@ void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
             : "r" (&lock->slock), "I" (1 << 16)
             : "cc");
 
-    while (lockval.tickets.next != lockval.tickets.owner) 
+    while (lockval.tickets.next != lockval.tickets.owner)
     {
         __WFE();
         lockval.tickets.owner = *(volatile unsigned short *)(&lock->tickets.owner);
diff --git a/bsp/raspberry-pi/raspi3-32/cpu/interrupt.c b/bsp/raspberry-pi/raspi3-32/cpu/interrupt.c
index c9e7c17f8f..11cfdb3d25 100644
--- a/bsp/raspberry-pi/raspi3-32/cpu/interrupt.c
+++ b/bsp/raspberry-pi/raspi3-32/cpu/interrupt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018/5/3       Bernard      first version
  * 2019-07-28     zdzn         add smp support
- * 2019-08-09     zhangjun     fixup the problem of smp startup and scheduling issues, 
+ * 2019-08-09     zhangjun     fixup the problem of smp startup and scheduling issues,
  *                             write addr to mailbox3 to startup smp, and we use mailbox0 for ipi
  */
 
@@ -163,15 +163,15 @@ void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
     }
     if (cpu_mask & 0x2)
     {
-    	send_ipi_msg(1, ipi_vector);
+        send_ipi_msg(1, ipi_vector);
     }
     if (cpu_mask & 0x4)
     {
-    	send_ipi_msg(2, ipi_vector);
+        send_ipi_msg(2, ipi_vector);
     }
     if (cpu_mask & 0x8)
     {
-    	send_ipi_msg(3, ipi_vector);
+        send_ipi_msg(3, ipi_vector);
     }
     __DSB();
 }
diff --git a/bsp/raspberry-pi/raspi3-32/cpu/mmu.c b/bsp/raspberry-pi/raspi3-32/cpu/mmu.c
index b3541d2ad4..f642dc235c 100644
--- a/bsp/raspberry-pi/raspi3-32/cpu/mmu.c
+++ b/bsp/raspberry-pi/raspi3-32/cpu/mmu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-32/cpu/mmu.h b/bsp/raspberry-pi/raspi3-32/cpu/mmu.h
index 6b0c25e990..6b994cac77 100644
--- a/bsp/raspberry-pi/raspi3-32/cpu/mmu.h
+++ b/bsp/raspberry-pi/raspi3-32/cpu/mmu.h
@@ -43,7 +43,7 @@
 /* normal memory mapping type */
 #define NORMAL_MEM     (SHARED | AP_RW | DOMAIN0 | MEMWBWA | DESC_SEC)
 #define STRONG_ORDER_MEM (SHARED | AP_RO | XN | DESC_SEC)
-#define BUS_ADDRESS(phys)	(((phys) & ~0xC0000000)  |  0xC0000000)
+#define BUS_ADDRESS(phys)   (((phys) & ~0xC0000000)  |  0xC0000000)
 
 void rt_hw_change_mmu_table(rt_uint32_t vaddrStart,
                       rt_uint32_t size,
diff --git a/bsp/raspberry-pi/raspi3-32/cpu/stack.c b/bsp/raspberry-pi/raspi3-32/cpu/stack.c
index c2c60fbf49..4d20ad7879 100644
--- a/bsp/raspberry-pi/raspi3-32/cpu/stack.c
+++ b/bsp/raspberry-pi/raspi3-32/cpu/stack.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-32/cpu/trap.c b/bsp/raspberry-pi/raspi3-32/cpu/trap.c
index f83f183695..b9fa6bb1c5 100644
--- a/bsp/raspberry-pi/raspi3-32/cpu/trap.c
+++ b/bsp/raspberry-pi/raspi3-32/cpu/trap.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2013-07-20     Bernard      first version
  * 2019-07-28     zdzn         add smp support
- * 2019-08-09     zhangjun     fixup the problem of smp startup and scheduling issues, 
+ * 2019-08-09     zhangjun     fixup the problem of smp startup and scheduling issues,
  *                             write addr to mailbox3 to startup smp, and we use mailbox0 for ipi
  */
 
@@ -164,7 +164,7 @@ void rt_hw_trap_irq(void)
         if (mailbox_data & 0x1)
         {
             /* clear mailbox */
-            IPI_MAILBOX_CLEAR(cpu_id) = mailbox_data;    
+            IPI_MAILBOX_CLEAR(cpu_id) = mailbox_data;
             isr_func = isr_table[IRQ_ARM_MAILBOX].handler;
 #ifdef RT_USING_INTERRUPT_INFO
             isr_table[IRQ_ARM_MAILBOX].counter++;
@@ -175,7 +175,7 @@ void rt_hw_trap_irq(void)
                 isr_func(IRQ_ARM_MAILBOX, param);
             }
         }
-        else 
+        else
             CORE_MAILBOX3_CLEAR(cpu_id) = mailbox_data;
     }
 #endif
diff --git a/bsp/raspberry-pi/raspi3-32/driver/board.c b/bsp/raspberry-pi/raspi3-32/driver/board.c
index 9cd929662e..920d284c07 100644
--- a/bsp/raspberry-pi/raspi3-32/driver/board.c
+++ b/bsp/raspberry-pi/raspi3-32/driver/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-32/driver/board.h b/bsp/raspberry-pi/raspi3-32/driver/board.h
index 8736027c06..bc5be3f9c8 100644
--- a/bsp/raspberry-pi/raspi3-32/driver/board.h
+++ b/bsp/raspberry-pi/raspi3-32/driver/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_fb.c b/bsp/raspberry-pi/raspi3-32/driver/drv_fb.c
index cc915351af..f004edad8c 100644
--- a/bsp/raspberry-pi/raspi3-32/driver/drv_fb.c
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_fb.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -306,7 +306,7 @@ rt_err_t hdmi_fb_control(rt_device_t dev, int cmd, void *args)
     return RT_EOK;
 }
 
-const static struct rt_device_ops hdmi_fb_ops = 
+const static struct rt_device_ops hdmi_fb_ops =
 {
     RT_NULL,
     hdmi_fb_open,
@@ -368,7 +368,7 @@ static void hdmi_blit_line(const char* pixels, int x, int y, rt_size_t size)
     }
 }
 
-static struct rt_device_graphic_ops hdmi_ops = 
+static struct rt_device_graphic_ops hdmi_ops =
 {
     hdmi_set_pixel,
     hdmi_get_pixel,
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_fb.h b/bsp/raspberry-pi/raspi3-32/driver/drv_fb.h
index 4926fa3ab1..1d447aeab1 100644
--- a/bsp/raspberry-pi/raspi3-32/driver/drv_fb.h
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_fb.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -14,15 +14,15 @@
 
 #define COLOR_BLACK RGB(0, 0, 0)
 
-#define COLOR_GREEN RGB(0, 255, 0)  
- 
-#define COLOR_CYAN RGB(0, 255, 255) 
+#define COLOR_GREEN RGB(0, 255, 0)
 
-#define COLOR_RED RGB(255, 0, 0)  
+#define COLOR_CYAN RGB(0, 255, 255)
 
-#define COLOR_YELLOW RGB(255, 255, 0) 
+#define COLOR_RED RGB(255, 0, 0)
 
-#define COLOR_WHITE RGB(255, 255, 255)   
+#define COLOR_YELLOW RGB(255, 255, 0)
+
+#define COLOR_WHITE RGB(255, 255, 255)
 
 #define CONSOLE_WHITE COLOR_WHITE
 #define CONSOLE_BLACK COLOR_BLACK
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.c b/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.c
index 205d7f10aa..721643f515 100644
--- a/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.c
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.h b/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.h
index ce0be096e8..18f95fecfd 100644
--- a/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.h
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_gpio.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_i2c.c b/bsp/raspberry-pi/raspi3-32/driver/drv_i2c.c
index 35ab7c36d7..5d1080eadb 100644
--- a/bsp/raspberry-pi/raspi3-32/driver/drv_i2c.c
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_i2c.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_i2c.h b/bsp/raspberry-pi/raspi3-32/driver/drv_i2c.h
index ff9e8ca724..2412631852 100644
--- a/bsp/raspberry-pi/raspi3-32/driver/drv_i2c.h
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_i2c.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.c b/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.c
index 147504bd16..3d7b97e8ac 100644
--- a/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.c
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.h b/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.h
index d850defa68..1fd8453e6f 100644
--- a/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.h
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_sdio.c b/bsp/raspberry-pi/raspi3-32/driver/drv_sdio.c
index 46df0372e9..4ab2e4c25b 100644
--- a/bsp/raspberry-pi/raspi3-32/driver/drv_sdio.c
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_sdio.c
@@ -1,6 +1,6 @@
 /*
  * File      : drv_sdio.c
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -125,7 +125,7 @@ rt_err_t sd_status(struct sdhci_pdata_t * pdat, unsigned int mask)
     else if (read32(pdat->virt + EMMC_INTERRUPT) & INT_ERROR_MASK)
     {
         return  -RT_ERROR;
-    }  
+    }
     return RT_EOK;
 }
 
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_sdio.h b/bsp/raspberry-pi/raspi3-32/driver/drv_sdio.h
index 5c052de90a..917c002daf 100644
--- a/bsp/raspberry-pi/raspi3-32/driver/drv_sdio.h
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_sdio.h
@@ -1,6 +1,6 @@
 /*
  * File      : drv_sdio.h
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_spi.c b/bsp/raspberry-pi/raspi3-32/driver/drv_spi.c
index eab7a08b39..c42d1cf013 100644
--- a/bsp/raspberry-pi/raspi3-32/driver/drv_spi.c
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_spi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_spi.h b/bsp/raspberry-pi/raspi3-32/driver/drv_spi.h
index 9e4623b327..58ede93ef4 100644
--- a/bsp/raspberry-pi/raspi3-32/driver/drv_spi.h
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_spi.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_timer.c b/bsp/raspberry-pi/raspi3-32/driver/drv_timer.c
index 36a4fd2baf..117026e91c 100644
--- a/bsp/raspberry-pi/raspi3-32/driver/drv_timer.c
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_timer.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -27,24 +27,24 @@ static rt_err_t raspi_systimer_start(rt_hwtimer_t *hwtimer, rt_uint32_t cnt, rt_
     if (mode == HWTIMER_MODE_PERIOD)
         timer->cnt = cnt;
     else
-        timer->cnt = 0; 
+        timer->cnt = 0;
 
     __sync_synchronize();
     if (timer_id == 1)
     {
         rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_1);
         STIMER_C1 = STIMER_CLO + cnt;
-    } 
+    }
     else if (timer_id == 3)
     {
         rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_3);
         STIMER_C3 = STIMER_CLO + cnt;
     }
-    else    
+    else
         result = -RT_ERROR;
 
     __sync_synchronize();
-         
+
     return result;
 }
 
@@ -56,7 +56,7 @@ static void raspi_systimer_stop(rt_hwtimer_t *hwtimer)
         rt_hw_interrupt_mask(IRQ_SYSTEM_TIMER_1);
     else if (timer_id == 3)
         rt_hw_interrupt_mask(IRQ_SYSTEM_TIMER_3);
- 
+
 }
 
 static rt_err_t raspi_systimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
@@ -75,7 +75,7 @@ static rt_err_t raspi_systimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *
 
 void rt_device_systimer_isr(int vector, void *param)
 {
-    
+
     rt_hwtimer_t *hwtimer = (rt_hwtimer_t *) param;
     rt_systimer_t *timer = (rt_systimer_t *)hwtimer->parent.user_data;
     RT_ASSERT(timer != RT_NULL);
@@ -86,18 +86,18 @@ void rt_device_systimer_isr(int vector, void *param)
     if (timer_id == 1)
     {
         STIMER_CS = 0x2;
-        STIMER_C1 = STIMER_CLO + timer->cnt;               
-    }   
+        STIMER_C1 = STIMER_CLO + timer->cnt;
+    }
     else if (timer_id == 3)
     {
         STIMER_CS = 0x8;
-        STIMER_C3 = STIMER_CLO + timer->cnt;                 
+        STIMER_C3 = STIMER_CLO + timer->cnt;
     }
     __sync_synchronize();
 
     rt_device_hwtimer_isr(hwtimer);
 }
-    
+
 static struct rt_hwtimer_device _hwtimer1;
 static struct rt_hwtimer_device _hwtimer3;
 
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_timer.h b/bsp/raspberry-pi/raspi3-32/driver/drv_timer.h
index c85d4c9d1f..7fca63f6b7 100644
--- a/bsp/raspberry-pi/raspi3-32/driver/drv_timer.h
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_timer.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_uart.c b/bsp/raspberry-pi/raspi3-32/driver/drv_uart.c
index 18501b7849..293570e7ab 100644
--- a/bsp/raspberry-pi/raspi3-32/driver/drv_uart.c
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_uart.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -125,7 +125,7 @@ static const struct rt_uart_ops _uart_ops =
 
 static void rt_hw_uart_isr(int irqno, void *param)
 {
-    struct rt_serial_device *serial = (struct rt_serial_device*)param; 
+    struct rt_serial_device *serial = (struct rt_serial_device*)param;
     rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
 }
 
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_uart.h b/bsp/raspberry-pi/raspi3-32/driver/drv_uart.h
index 5211c19989..4f0a31bf52 100644
--- a/bsp/raspberry-pi/raspi3-32/driver/drv_uart.h
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_uart.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_wdt.c b/bsp/raspberry-pi/raspi3-32/driver/drv_wdt.c
index ad511913cb..b748a7b472 100644
--- a/bsp/raspberry-pi/raspi3-32/driver/drv_wdt.c
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_wdt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -129,9 +129,9 @@ int reboot(void)
     PM_RSTS = PM_PASSWORD | r;   // boot from partition 0
     PM_WDOG = PM_PASSWORD | 10;
     PM_RSTC = PM_PASSWORD | PM_RSTC_WRCFG_FULL_RESET;
-    
+
     while (1);
-    
+
     return 0;
 }
 MSH_CMD_EXPORT(reboot,reboot system...);
diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_wdt.h b/bsp/raspberry-pi/raspi3-32/driver/drv_wdt.h
index 0b59ab79f3..ffb07ff5da 100644
--- a/bsp/raspberry-pi/raspi3-32/driver/drv_wdt.h
+++ b/bsp/raspberry-pi/raspi3-32/driver/drv_wdt.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-32/driver/mbox.c b/bsp/raspberry-pi/raspi3-32/driver/mbox.c
index bbd5183aa8..041017e471 100644
--- a/bsp/raspberry-pi/raspi3-32/driver/mbox.c
+++ b/bsp/raspberry-pi/raspi3-32/driver/mbox.c
@@ -1,6 +1,6 @@
 /*
  * File      : mbox.c
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -41,7 +41,7 @@ int mbox_call(unsigned char ch, int mmu_enable)
         do
         {
             asm volatile("nop");
-        } 
+        }
         while (*MBOX_STATUS & MBOX_EMPTY);
         /* is it a response to our message? */
         if (r == *MBOX_READ)
diff --git a/bsp/raspberry-pi/raspi3-32/driver/mbox.h b/bsp/raspberry-pi/raspi3-32/driver/mbox.h
index 5c59fd608c..3190603e8f 100644
--- a/bsp/raspberry-pi/raspi3-32/driver/mbox.h
+++ b/bsp/raspberry-pi/raspi3-32/driver/mbox.h
@@ -1,6 +1,6 @@
 /*
  * File      : mbox.h
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-32/driver/raspi.h b/bsp/raspberry-pi/raspi3-32/driver/raspi.h
index 19daa3541d..fedf4bcff8 100644
--- a/bsp/raspberry-pi/raspi3-32/driver/raspi.h
+++ b/bsp/raspberry-pi/raspi3-32/driver/raspi.h
@@ -1,6 +1,6 @@
 /*
  * File      : rsapi.h
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-32/link.lds b/bsp/raspberry-pi/raspi3-32/link.lds
index 75e0845943..2624a5a95d 100644
--- a/bsp/raspberry-pi/raspi3-32/link.lds
+++ b/bsp/raspberry-pi/raspi3-32/link.lds
@@ -1,20 +1,7 @@
 /*
- * File      : link.lds
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * 2017-5-30     bernard       first version
diff --git a/bsp/raspberry-pi/raspi3-64/applications/main.c b/bsp/raspberry-pi/raspi3-64/applications/main.c
index 397f40126b..bd7c917e64 100644
--- a/bsp/raspberry-pi/raspi3-64/applications/main.c
+++ b/bsp/raspberry-pi/raspi3-64/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,10 +16,10 @@
 void set_led(int state) //set state LED nyala atau mati
 {
     if (state==1)                       //LED nyala
-    { 
+    {
         mbox[0] = 8*4;                  // length of the message
         mbox[1] = MBOX_REQUEST;         // this is a request message
-    
+
         mbox[2] = 0x00038041;   // get serial number command
         mbox[3] = 8;                    // buffer size
         mbox[4] = 0;
@@ -29,10 +29,10 @@ void set_led(int state) //set state LED nyala atau mati
         mbox_call(8, MMU_DISABLE);
     }
     else if (state==0)                  //LED mati
-    { 
+    {
         mbox[0] = 8*4;                  // length of the message
         mbox[1] = MBOX_REQUEST;         // this is a request message
-    
+
         mbox[2] = 0x00038041;   // get serial number command
         mbox[3] = 8;                    // buffer size
         mbox[4] = 0;
diff --git a/bsp/raspberry-pi/raspi3-64/applications/mnt.c b/bsp/raspberry-pi/raspi3-64/applications/mnt.c
index 33b466434c..01e97b325b 100644
--- a/bsp/raspberry-pi/raspi3-64/applications/mnt.c
+++ b/bsp/raspberry-pi/raspi3-64/applications/mnt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-64/driver/board.c b/bsp/raspberry-pi/raspi3-64/driver/board.c
index 5d15dda987..531a0a0dfa 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/board.c
+++ b/bsp/raspberry-pi/raspi3-64/driver/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -62,7 +62,7 @@ void rt_hw_timer_init(void)
     timerStep = rt_hw_get_gtimer_frq();
     __DSB();
     timerStep /= RT_TICK_PER_SECOND;
-    
+
     rt_hw_gtimer_enable();
     rt_hw_set_gtimer_val(timerStep);
     core0_timer_enable_interrupt_controller();
@@ -90,7 +90,7 @@ void idle_wfi(void)
 }
 
 /**
- *  Initialize the Hardware related stuffs. Called from rtthread_startup() 
+ *  Initialize the Hardware related stuffs. Called from rtthread_startup()
  *  after interrupt disabled.
  */
 void rt_hw_board_init(void)
@@ -105,7 +105,7 @@ void rt_hw_board_init(void)
     armv8_map(0x3f804000, 0x3f804000, 0x1000, MEM_ATTR_IO);//i2c0
     armv8_map(0x3f205000, 0x3f205000, 0x1000, MEM_ATTR_IO);//i2c1
     mmu_enable();
-    
+
     /* initialize hardware interrupt */
     rt_hw_interrupt_init(); // in libcpu/interrupt.c. Set some data structures, no operation on device
     rt_hw_vector_init();    // in libcpu/interrupt.c. == rt_cpu_vector_set_base((rt_ubase_t)&system_vectors);
diff --git a/bsp/raspberry-pi/raspi3-64/driver/board.h b/bsp/raspberry-pi/raspi3-64/driver/board.h
index b44c245a17..6b51f0408e 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/board.h
+++ b/bsp/raspberry-pi/raspi3-64/driver/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_fb.c b/bsp/raspberry-pi/raspi3-64/driver/drv_fb.c
index cabaded5fd..204fa0c868 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/drv_fb.c
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_fb.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -116,7 +116,7 @@ rt_err_t hdmi_fb_control(rt_device_t dev, int cmd, void *args)
     return RT_EOK;
 }
 
-const static struct rt_device_ops hdmi_fb_ops = 
+const static struct rt_device_ops hdmi_fb_ops =
 {
     RT_NULL,
     hdmi_fb_open,
@@ -157,7 +157,7 @@ rt_uint32_t bcm283x_mbox_fb_get_gpiovirt(void)
 {
     mbox[0] = 8*4;                      // length of the message
     mbox[1] = MBOX_REQUEST;             // this is a request message
-    
+
     mbox[2] = MBOX_TAG_FB_GET_GPIOVIRT;
     mbox[3] = 4;                        // buffer size
     mbox[4] = 0;                        // len
@@ -174,7 +174,7 @@ rt_uint32_t bcm283x_mbox_fb_get_pitch(void)
 {
     mbox[0] = 8*4;                  // length of the message
     mbox[1] = MBOX_REQUEST;         // this is a request message
-    
+
     mbox[2] = MBOX_TAG_FB_GET_PITCH;
     mbox[3] = 4;                    // buffer size
     mbox[4] = 0;                    // len
@@ -191,7 +191,7 @@ void bcm283x_mbox_fb_set_porder(int rgb)
 {
     mbox[0] = 8*4;                      // length of the message
     mbox[1] = MBOX_REQUEST;             // this is a request message
-    
+
     mbox[2] = MBOX_TAG_FB_SET_PIXEL_ORDER;
     mbox[3] = 4;                        // buffer size
     mbox[4] = 4;                        // len
@@ -207,7 +207,7 @@ void bcm283x_mbox_fb_setoffset(int xoffset, int yoffset)
 {
     mbox[0] = 8*4;                      // length of the message
     mbox[1] = MBOX_REQUEST;             // this is a request message
-    
+
     mbox[2] = MBOX_TAG_FB_SET_VIRT_OFFSET;
     mbox[3] = 8;                        // buffer size
     mbox[4] = 8;                        // len
@@ -225,7 +225,7 @@ void bcm283x_mbox_fb_setalpha(int alpha)
 
     mbox[0] = 8*4;                      // length of the message
     mbox[1] = MBOX_REQUEST;             // this is a request message
-    
+
     mbox[2] = MBOX_TAG_FB_SET_ALPHA_MODE;
     mbox[3] = 4;                        // buffer size
     mbox[4] = 4;                        // len
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_fb.h b/bsp/raspberry-pi/raspi3-64/driver/drv_fb.h
index 9fdac754cd..1074dc79c7 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/drv_fb.h
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_fb.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.c b/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.c
index 0cd6abb84e..04b5cdf162 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.c
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.h b/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.h
index f51817b035..009f4e3edc 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.h
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_gpio.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_i2c.c b/bsp/raspberry-pi/raspi3-64/driver/drv_i2c.c
index ce0fd7ae74..b7c6067ae4 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/drv_i2c.c
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_i2c.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -130,7 +130,7 @@ static rt_size_t raspi_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
     volatile rt_base_t base = (volatile rt_base_t)(bus->parent.user_data);
 
     if (bus->addr == 0)
-        base = BCM283X_BSC0_BASE; 
+        base = BCM283X_BSC0_BASE;
     else
         base = BCM283X_BSC1_BASE;
 
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_i2c.h b/bsp/raspberry-pi/raspi3-64/driver/drv_i2c.h
index 9b652b746f..2412631852 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/drv_i2c.h
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_i2c.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.c b/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.c
index 18fd6474a2..5d43c39073 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.c
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.h b/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.h
index 82306068ca..4af28efa17 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.h
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_sdio.c b/bsp/raspberry-pi/raspi3-64/driver/drv_sdio.c
index 785f335ebb..a46115804a 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/drv_sdio.c
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_sdio.c
@@ -1,6 +1,6 @@
 /*
  * File      : drv_sdio.c
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -128,7 +128,7 @@ rt_err_t sd_status(struct sdhci_pdata_t * pdat, unsigned int mask)
     else if (read32(pdat->virt + EMMC_INTERRUPT) & INT_ERROR_MASK)
     {
         return  -RT_ERROR;
-    } 
+    }
 
     return RT_EOK;
 }
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_sdio.h b/bsp/raspberry-pi/raspi3-64/driver/drv_sdio.h
index 5c052de90a..917c002daf 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/drv_sdio.h
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_sdio.h
@@ -1,6 +1,6 @@
 /*
  * File      : drv_sdio.h
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_spi.c b/bsp/raspberry-pi/raspi3-64/driver/drv_spi.c
index 0b0c8881a8..4c63fe9aae 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/drv_spi.c
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_spi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_spi.h b/bsp/raspberry-pi/raspi3-64/driver/drv_spi.h
index 9e4623b327..58ede93ef4 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/drv_spi.h
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_spi.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_timer.c b/bsp/raspberry-pi/raspi3-64/driver/drv_timer.c
index 00b31897d8..a8cb5149d4 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/drv_timer.c
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_timer.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -29,24 +29,24 @@ static rt_err_t raspi_systimer_start(rt_hwtimer_t *hwtimer, rt_uint32_t cnt, rt_
     if (mode == HWTIMER_MODE_PERIOD)
         timer->cnt = cnt;
     else
-        timer->cnt = 0; 
+        timer->cnt = 0;
 
     __sync_synchronize();
     if (timer_id == 1)
     {
         rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_1);
         STIMER_C1 = STIMER_CLO + cnt;
-    } 
+    }
     else if (timer_id == 3)
     {
         rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_3);
         STIMER_C3 = STIMER_CLO + cnt;
     }
-    else    
+    else
         result = -RT_ERROR;
 
     __sync_synchronize();
-         
+
     return result;
 }
 
@@ -58,7 +58,7 @@ static void raspi_systimer_stop(rt_hwtimer_t *hwtimer)
         rt_hw_interrupt_mask(IRQ_SYSTEM_TIMER_1);
     else if (timer_id == 3)
         rt_hw_interrupt_mask(IRQ_SYSTEM_TIMER_3);
- 
+
 }
 
 static rt_err_t raspi_systimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
@@ -77,7 +77,7 @@ static rt_err_t raspi_systimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *
 
 void rt_device_systimer_isr(int vector, void *param)
 {
-    
+
     rt_hwtimer_t *hwtimer = (rt_hwtimer_t *) param;
     rt_systimer_t *timer = (rt_systimer_t *)hwtimer->parent.user_data;
     RT_ASSERT(timer != RT_NULL);
@@ -88,12 +88,12 @@ void rt_device_systimer_isr(int vector, void *param)
     if (timer_id == 1)
     {
         STIMER_CS = 0x2;
-        STIMER_C1 = STIMER_CLO + timer->cnt;               
-    }   
+        STIMER_C1 = STIMER_CLO + timer->cnt;
+    }
     else if (timer_id == 3)
     {
         STIMER_CS = 0x8;
-        STIMER_C3 = STIMER_CLO + timer->cnt;                 
+        STIMER_C3 = STIMER_CLO + timer->cnt;
     }
     __sync_synchronize();
 
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_timer.h b/bsp/raspberry-pi/raspi3-64/driver/drv_timer.h
index c18e3d893c..ebe5536fa5 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/drv_timer.h
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_timer.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_uart.c b/bsp/raspberry-pi/raspi3-64/driver/drv_uart.c
index 62fcb966b4..6eb7a46f10 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/drv_uart.c
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_uart.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -124,7 +124,7 @@ static const struct rt_uart_ops _uart_ops =
 
 static void rt_hw_uart_isr(int irqno, void *param)
 {
-    struct rt_serial_device *serial = (struct rt_serial_device*)param; 
+    struct rt_serial_device *serial = (struct rt_serial_device*)param;
     rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
 }
 
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_uart.h b/bsp/raspberry-pi/raspi3-64/driver/drv_uart.h
index 894c6098db..76072f938e 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/drv_uart.h
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_uart.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_wdt.c b/bsp/raspberry-pi/raspi3-64/driver/drv_wdt.c
index 245f4df197..f90a251ad0 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/drv_wdt.c
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_wdt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -130,9 +130,9 @@ int reboot(void)
     PM_RSTS = PM_PASSWORD | r;   // boot from partition 0
     PM_WDOG = PM_PASSWORD | 10;
     PM_RSTC = PM_PASSWORD | PM_RSTC_WRCFG_FULL_RESET;
-    
+
     while (1);
-    
+
     return 0;
 }
 MSH_CMD_EXPORT(reboot,reboot system...);
diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_wdt.h b/bsp/raspberry-pi/raspi3-64/driver/drv_wdt.h
index 0b59ab79f3..ffb07ff5da 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/drv_wdt.h
+++ b/bsp/raspberry-pi/raspi3-64/driver/drv_wdt.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-64/driver/mbox.c b/bsp/raspberry-pi/raspi3-64/driver/mbox.c
index dc09ecab4b..fbfc456b4d 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/mbox.c
+++ b/bsp/raspberry-pi/raspi3-64/driver/mbox.c
@@ -1,6 +1,6 @@
 /*
  * File      : mbox.c
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -41,7 +41,7 @@ int mbox_call(unsigned char ch, int mmu_enable)
         /* is it a response to our message? */
         if (r == *MBOX_READ){
             /* is it a valid successful response? */
-        //	rt_kprintf("mbox: %x, %x, %x, %x, %x, %x, %x, %x\n", mbox[0], mbox[1], mbox[2], mbox[3], mbox[4], mbox[5], mbox[6], mbox[7]);
+        //  rt_kprintf("mbox: %x, %x, %x, %x, %x, %x, %x, %x\n", mbox[0], mbox[1], mbox[2], mbox[3], mbox[4], mbox[5], mbox[6], mbox[7]);
             return mbox[1] == MBOX_RESPONSE;
         }
     }
@@ -52,12 +52,12 @@ int bcm283x_mbox_hardware_get_model(void)
 {
     mbox[0] = 8*4;                          // length of the message
     mbox[1] = MBOX_REQUEST;                 // this is a request message
-    
+
     mbox[2] = MBOX_TAG_HARDWARE_GET_MODEL;
     mbox[3] = 4;                            // buffer size
     mbox[4] = 0;                            // len
 
-    mbox[5] = 0;                            
+    mbox[5] = 0;
     mbox[6] = 0;
 
     mbox[7] = MBOX_TAG_LAST;
@@ -70,12 +70,12 @@ int bcm283x_mbox_hardware_get_revison(void)
 {
     mbox[0] = 8*4;                          // length of the message
     mbox[1] = MBOX_REQUEST;                 // this is a request message
-    
-    mbox[2] = MBOX_TAG_HARDWARE_GET_REV;   
+
+    mbox[2] = MBOX_TAG_HARDWARE_GET_REV;
     mbox[3] = 4;                            // buffer size
     mbox[4] = 0;                            // len
 
-    mbox[5] = 0;                    
+    mbox[5] = 0;
     mbox[6] = 0;
 
     mbox[7] = MBOX_TAG_LAST;
@@ -88,12 +88,12 @@ int bcm283x_mbox_hardware_get_mac_address(uint8_t * mac)
 {
     mbox[0] = 8*4;                                 // length of the message
     mbox[1] = MBOX_REQUEST;                        // this is a request message
-    
-    mbox[2] = MBOX_TAG_HARDWARE_GET_MAC_ADDRESS;   
+
+    mbox[2] = MBOX_TAG_HARDWARE_GET_MAC_ADDRESS;
     mbox[3] = 6;                                   // buffer size
     mbox[4] = 0;                                   // len
 
-    mbox[5] = 0;                    
+    mbox[5] = 0;
     mbox[6] = 0;
 
     mbox[7] = MBOX_TAG_LAST;
@@ -114,12 +114,12 @@ int bcm283x_mbox_hardware_get_serial(rt_uint64_t* sn)
 {
     mbox[0] = 8*4;                              // length of the message
     mbox[1] = MBOX_REQUEST;                     // this is a request message
-    
-    mbox[2] = MBOX_TAG_HARDWARE_GET_SERIAL;    
+
+    mbox[2] = MBOX_TAG_HARDWARE_GET_SERIAL;
     mbox[3] = 8;                                // buffer size
     mbox[4] = 0;                                // len
 
-    mbox[5] = 0;                    
+    mbox[5] = 0;
     mbox[6] = 0;
 
     mbox[7] = MBOX_TAG_LAST;
@@ -134,12 +134,12 @@ int bcm283x_mbox_hardware_get_arm_memory(rt_uint32_t * base, rt_uint32_t * size)
 {
     mbox[0] = 8*4;                                  // length of the message
     mbox[1] = MBOX_REQUEST;                         // this is a request message
-    
-    mbox[2] = MBOX_TAG_HARDWARE_GET_ARM_MEMORY;   
+
+    mbox[2] = MBOX_TAG_HARDWARE_GET_ARM_MEMORY;
     mbox[3] = 8;                                    // buffer size
     mbox[4] = 0;                                    // len
 
-    mbox[5] = 0;                    
+    mbox[5] = 0;
     mbox[6] = 0;
 
     mbox[7] = MBOX_TAG_LAST;
@@ -147,7 +147,7 @@ int bcm283x_mbox_hardware_get_arm_memory(rt_uint32_t * base, rt_uint32_t * size)
 
     *base = mbox[5];
     *size = mbox[6];
-    
+
     return 0;
 
 }
@@ -156,12 +156,12 @@ int bcm283x_mbox_hardware_get_vc_memory(rt_uint32_t * base, rt_uint32_t * size)
 {
     mbox[0] = 8*4;                               // length of the message
     mbox[1] = MBOX_REQUEST;                      // this is a request message
-    
+
     mbox[2] = MBOX_TAG_HARDWARE_GET_VC_MEMORY;
     mbox[3] = 8;                                 // buffer size
     mbox[4] = 0;                                 // len
 
-    mbox[5] = 0;                    
+    mbox[5] = 0;
     mbox[6] = 0;
 
     mbox[7] = MBOX_TAG_LAST;
@@ -169,7 +169,7 @@ int bcm283x_mbox_hardware_get_vc_memory(rt_uint32_t * base, rt_uint32_t * size)
 
     *base = mbox[5];
     *size = mbox[6];
-    
+
     return 0;
 }
 
@@ -177,8 +177,8 @@ int bcm283x_mbox_clock_get_turbo(void)
 {
     mbox[0] = 8*4;                      // length of the message
     mbox[1] = MBOX_REQUEST;             // this is a request message
-    
-    mbox[2] = MBOX_TAG_CLOCK_GET_TURBO; 
+
+    mbox[2] = MBOX_TAG_CLOCK_GET_TURBO;
     mbox[3] = 8;                        // buffer size
     mbox[4] = 4;                        // len
 
@@ -200,8 +200,8 @@ int bcm283x_mbox_clock_set_turbo(int level)
 {
     mbox[0] = 8*4;                      // length of the message
     mbox[1] = MBOX_REQUEST;             // this is a request message
-    
-    mbox[2] = MBOX_TAG_CLOCK_SET_TURBO;  
+
+    mbox[2] = MBOX_TAG_CLOCK_SET_TURBO;
     mbox[3] = 8;                        // buffer size
     mbox[4] = 8;                        // len
 
@@ -223,7 +223,7 @@ int bcm283x_mbox_clock_get_state(int id)
 {
     mbox[0] = 8*4;                       // length of the message
     mbox[1] = MBOX_REQUEST;              // this is a request message
-    
+
     mbox[2] = MBOX_TAG_CLOCK_GET_STATE;
     mbox[3] = 8;                         // buffer size
     mbox[4] = 4;                         // len
@@ -246,7 +246,7 @@ int bcm283x_mbox_clock_set_state(int id, int state)
 {
     mbox[0] = 8*4;                      // length of the message
     mbox[1] = MBOX_REQUEST;             // this is a request message
-    
+
     mbox[2] = MBOX_TAG_CLOCK_SET_STATE;
     mbox[3] = 8;                        // buffer size
     mbox[4] = 8;                        // len
@@ -269,8 +269,8 @@ int bcm283x_mbox_clock_get_rate(int id)
 {
     mbox[0] = 8*4;                      // length of the message
     mbox[1] = MBOX_REQUEST;             // this is a request message
-    
-    mbox[2] = MBOX_TAG_CLOCK_GET_RATE; 
+
+    mbox[2] = MBOX_TAG_CLOCK_GET_RATE;
     mbox[3] = 8;                        // buffer size
     mbox[4] = 4;                        // len
 
@@ -292,7 +292,7 @@ int bcm283x_mbox_clock_set_rate(int id, int rate)
 {
     mbox[0] = 8*4;                      // length of the message
     mbox[1] = MBOX_REQUEST;             // this is a request message
-    
+
     mbox[2] = MBOX_TAG_CLOCK_SET_RATE;
     mbox[3] = 8;                        // buffer size
     mbox[4] = 8;                        // len
@@ -315,7 +315,7 @@ int bcm283x_mbox_clock_get_max_rate(int id)
 {
     mbox[0] = 8*4;                          // length of the message
     mbox[1] = MBOX_REQUEST;                 // this is a request message
-    
+
     mbox[2] = MBOX_TAG_CLOCK_GET_MAX_RATE;
     mbox[3] = 8;                            // buffer size
     mbox[4] = 4;                            // len
@@ -338,8 +338,8 @@ int bcm283x_mbox_clock_get_min_rate(int id)
 {
     mbox[0] = 8*4;                          // length of the message
     mbox[1] = MBOX_REQUEST;                 // this is a request message
-    
-    mbox[2] = MBOX_TAG_CLOCK_GET_MIN_RATE; 
+
+    mbox[2] = MBOX_TAG_CLOCK_GET_MIN_RATE;
     mbox[3] = 8;                            // buffer size
     mbox[4] = 4;                            // len
 
@@ -361,7 +361,7 @@ int bcm283x_mbox_power_get_state(int id)
 {
     mbox[0] = 8*4;                  // length of the message
     mbox[1] = MBOX_REQUEST;         // this is a request message
-    
+
     mbox[2] = MBOX_TAG_POWER_GET_STATE;
     mbox[3] = 8;                    // buffer size
     mbox[4] = 4;                    // len
@@ -384,7 +384,7 @@ int bcm283x_mbox_power_set_state(int id, int state)
 {
     mbox[0] = 8*4;                  // length of the message
     mbox[1] = MBOX_REQUEST;         // this is a request message
-    
+
     mbox[2] = MBOX_TAG_POWER_SET_STATE;
     mbox[3] = 8;                    // buffer size
     mbox[4] = 8;                    // len
@@ -407,7 +407,7 @@ int bcm283x_mbox_temp_get(void)
 {
     mbox[0] = 8*4;                  // length of the message
     mbox[1] = MBOX_REQUEST;         // this is a request message
-    
+
     mbox[2] = MBOX_TAG_TEMP_GET;
     mbox[3] = 8;                    // buffer size
     mbox[4] = 4;                    // len
@@ -430,7 +430,7 @@ int bcm283x_mbox_temp_get_max(void)
 {
     mbox[0] = 8*4;                  // length of the message
     mbox[1] = MBOX_REQUEST;         // this is a request message
-    
+
     mbox[2] = MBOX_TAG_TEMP_GET_MAX;
     mbox[3] = 8;                    // buffer size
     mbox[4] = 4;                    // len
diff --git a/bsp/raspberry-pi/raspi3-64/driver/mbox.h b/bsp/raspberry-pi/raspi3-64/driver/mbox.h
index f235691d7b..b7aa2e95c9 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/mbox.h
+++ b/bsp/raspberry-pi/raspi3-64/driver/mbox.h
@@ -1,6 +1,6 @@
 /*
  * File      : mbox.h
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -32,7 +32,7 @@ extern volatile unsigned int* mbox;
 /* tags */
 #define MBOX_TAG_SETPOWER       0x28001
 #define MBOX_TAG_SETCLKRATE     0x38002
-#define MBOX_GET_MAC_ADDRESS	0x10003
+#define MBOX_GET_MAC_ADDRESS    0x10003
 #define MBOX_TAG_LAST           0
 
 #define MMIO_BASE       0x3F000000
@@ -47,12 +47,12 @@ extern volatile unsigned int* mbox;
 #define MBOX_FULL       0x80000000
 #define MBOX_EMPTY      0x40000000
 
-#define DEVICE_ID_SD_CARD	0
-#define DEVICE_ID_USB_HCD	3
-#define POWER_STATE_OFF		(0 << 0)
-#define POWER_STATE_ON		(1 << 0)
-#define POWER_STATE_WAIT	(1 << 1)
-#define POWER_STATE_NO_DEVICE	(1 << 1)	// in response
+#define DEVICE_ID_SD_CARD   0
+#define DEVICE_ID_USB_HCD   3
+#define POWER_STATE_OFF     (0 << 0)
+#define POWER_STATE_ON      (1 << 0)
+#define POWER_STATE_WAIT    (1 << 1)
+#define POWER_STATE_NO_DEVICE   (1 << 1)    // in response
 #define MMU_ENABLE 1
 #define MMU_DISABLE 0
 
diff --git a/bsp/raspberry-pi/raspi3-64/driver/raspi.h b/bsp/raspberry-pi/raspi3-64/driver/raspi.h
index 9a5de2af02..a24640d07d 100644
--- a/bsp/raspberry-pi/raspi3-64/driver/raspi.h
+++ b/bsp/raspberry-pi/raspi3-64/driver/raspi.h
@@ -1,6 +1,6 @@
 /*
  * File      : rsapi.h
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi3-64/link.lds b/bsp/raspberry-pi/raspi3-64/link.lds
index b7b2dcc32c..a624a973b4 100644
--- a/bsp/raspberry-pi/raspi3-64/link.lds
+++ b/bsp/raspberry-pi/raspi3-64/link.lds
@@ -1,20 +1,7 @@
 /*
- * File      : link.lds
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * 2017-5-30     bernard       first version
@@ -40,7 +27,7 @@ SECTIONS
         *(.gnu.linkonce.t*)
 
         *(COMMON)
-        
+
         /* section information for finsh shell */
         . = ALIGN(16);
         __fsymtab_start = .;
@@ -110,7 +97,7 @@ SECTIONS
         *(.bss)
         *(.bss.*)
         *(.dynbss)
-        
+
         PROVIDE(__bss_end = .);
     }
     _end = .;
diff --git a/bsp/raspberry-pi/raspi4-32/applications/main.c b/bsp/raspberry-pi/raspi4-32/applications/main.c
index 15dc74dc58..f2248e1660 100644
--- a/bsp/raspberry-pi/raspi4-32/applications/main.c
+++ b/bsp/raspberry-pi/raspi4-32/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,7 +17,7 @@
 int main(int argc, char** argv)
 {
     rt_kprintf("Hi, this is RT-Thread!!\n");
-    
+
     rt_pin_mode(ACTLED, PIN_MODE_OUTPUT);
 
     while(1)
diff --git a/bsp/raspberry-pi/raspi4-32/applications/mnt.c b/bsp/raspberry-pi/raspi4-32/applications/mnt.c
index ae224e8e89..ea67a4a46a 100644
--- a/bsp/raspberry-pi/raspi4-32/applications/mnt.c
+++ b/bsp/raspberry-pi/raspi4-32/applications/mnt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi4-32/driver/board.c b/bsp/raspberry-pi/raspi4-32/driver/board.c
index 455bd28ee2..c9571316d1 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/board.c
+++ b/bsp/raspberry-pi/raspi4-32/driver/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -22,7 +22,7 @@ struct mem_desc platform_mem_desc[] = {
     {0x0, 0x6400000, 0x0, NORMAL_MEM},
     {0x8000000, 0x8800000, 0x8000000, DEVICE_MEM},    //mbox msg
     {0x0E000000, 0x0EE00000, 0x0E000000, DEVICE_MEM}, //framebuffer
-    {0x0F400000, 0x0FA00000, 0x0F400000, DEVICE_MEM}, //dsi_touch 
+    {0x0F400000, 0x0FA00000, 0x0F400000, DEVICE_MEM}, //dsi_touch
     {0xFD500000, 0xFDA00000, 0xFD500000, DEVICE_MEM}, //gmac
     {0xFE000000, 0xFF000000, 0xFE000000, DEVICE_MEM}, //peripheral
     {0xFF800000, 0xFFA00000, 0xFF800000, DEVICE_MEM}  //gic
@@ -65,7 +65,7 @@ void idle_wfi(void)
 }
 
 /**
- *  Initialize the Hardware related stuffs. Called from rtthread_startup() 
+ *  Initialize the Hardware related stuffs. Called from rtthread_startup()
  *  after interrupt disabled.
  */
 void rt_hw_board_init(void)
diff --git a/bsp/raspberry-pi/raspi4-32/driver/board.h b/bsp/raspberry-pi/raspi4-32/driver/board.h
index d675cc658e..29019514b9 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/board.h
+++ b/bsp/raspberry-pi/raspi4-32/driver/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_bluetooth.c b/bsp/raspberry-pi/raspi4-32/driver/drv_bluetooth.c
index 6b839f5e23..cdf809cc77 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/drv_bluetooth.c
+++ b/bsp/raspberry-pi/raspi4-32/driver/drv_bluetooth.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_bluetooth.h b/bsp/raspberry-pi/raspi4-32/driver/drv_bluetooth.h
index 9de47bf191..0e7453ca3d 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/drv_bluetooth.h
+++ b/bsp/raspberry-pi/raspi4-32/driver/drv_bluetooth.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_dma.c b/bsp/raspberry-pi/raspi4-32/driver/drv_dma.c
index 4ec94896c1..a258dd41e4 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/drv_dma.c
+++ b/bsp/raspberry-pi/raspi4-32/driver/drv_dma.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_dma.h b/bsp/raspberry-pi/raspi4-32/driver/drv_dma.h
index 1b79eb1c95..83fbcbdd0e 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/drv_dma.h
+++ b/bsp/raspberry-pi/raspi4-32/driver/drv_dma.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_eth.c b/bsp/raspberry-pi/raspi4-32/driver/drv_eth.c
index a2f78ffd61..58683b422d 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/drv_eth.c
+++ b/bsp/raspberry-pi/raspi4-32/driver/drv_eth.c
@@ -1,6 +1,6 @@
 
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -670,7 +670,7 @@ struct pbuf *rt_eth_rx(rt_device_t device)
 int rt_hw_eth_init(void)
 {
     rt_uint8_t mac_addr[6];
-    
+
     rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
     rt_sem_init(&link_ack, "link_ack", 0, RT_IPC_FLAG_FIFO);
 
diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_eth.h b/bsp/raspberry-pi/raspi4-32/driver/drv_eth.h
index f7916ee5e1..39bfc87913 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/drv_eth.h
+++ b/bsp/raspberry-pi/raspi4-32/driver/drv_eth.h
@@ -1,6 +1,6 @@
 
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c b/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c
index b2d2ed79c4..7a3d2604a1 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c
+++ b/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -102,7 +102,7 @@ static void gpio_set_pud(GPIO_PIN pin, GPIO_PUPD_FUNC mode)
     case 3:
         reg_value = GPIO_PUP_PDN_CNTRL_REG3(GPIO_BASE);
         GPIO_PUP_PDN_CNTRL_REG3(GPIO_BASE) = (reg_value | (mode << (fselrest*2)));
-        break;    
+        break;
     default:
         break;
     }
@@ -194,7 +194,7 @@ static int raspi_pin_read(struct rt_device *device, rt_base_t pin)
         else
         {
             pin_level = 0;
-        }  
+        }
 
     }
     else
@@ -422,7 +422,7 @@ int rt_hw_gpio_init(void)
 
     GPIO_REG_GPAFEN0(GPIO_BASE) = 0x0;
     GPIO_REG_GPAFEN0(GPIO_BASE) = 0x0;
-    
+
     rt_hw_interrupt_install(IRQ_GPIO0, gpio_irq_handler, &_g_gpio_irq_tbl[0], "gpio0_irq");
     rt_hw_interrupt_umask(IRQ_GPIO0);
 
diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.h b/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.h
index 7594759f97..78c1709965 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.h
+++ b/bsp/raspberry-pi/raspi4-32/driver/drv_gpio.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_i2c.c b/bsp/raspberry-pi/raspi4-32/driver/drv_i2c.c
index f596eccc89..3a7503a04d 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/drv_i2c.c
+++ b/bsp/raspberry-pi/raspi4-32/driver/drv_i2c.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,7 +16,7 @@
 /*
 * (3.3v)          -1   2-
 * (SDA1/SDA3)     -3   4-
-* (SCL1/SCL3)     -5   6-  
+* (SCL1/SCL3)     -5   6-
 * (SDA3)          -7   8-
 *                 -9  10-
 *                 -11 12-
@@ -268,7 +268,7 @@ static struct raspi_i2c_hw_config hw_device4 =
     .scl_pin = GPIO_PIN_7,
 #else
     .sda_pin = GPIO_PIN_8,
-    .scl_pin = GPIO_PIN_9, 
+    .scl_pin = GPIO_PIN_9,
 #endif
     .sda_mode = ALT5,
     .scl_mode = ALT5,
diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_i2c.h b/bsp/raspberry-pi/raspi4-32/driver/drv_i2c.h
index e02c8887f0..bfb724ad93 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/drv_i2c.h
+++ b/bsp/raspberry-pi/raspi4-32/driver/drv_i2c.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_sdio.c b/bsp/raspberry-pi/raspi4-32/driver/drv_sdio.c
index 4d88668eee..d0f63cfce0 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/drv_sdio.c
+++ b/bsp/raspberry-pi/raspi4-32/driver/drv_sdio.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -128,7 +128,7 @@ rt_err_t sd_status(struct sdhci_pdata_t * pdat, unsigned int mask)
     else if (read32(pdat->virt + EMMC_INTERRUPT) & INT_ERROR_MASK)
     {
         return  -RT_ERROR;
-    } 
+    }
 
     return RT_EOK;
 }
@@ -450,7 +450,7 @@ static rt_err_t sdhci_setclock(struct sdhci_t * sdhci, rt_uint32_t clock)
     sdHostVer = (temp & HOST_SPEC_NUM) >> HOST_SPEC_NUM_SHIFT;
     int cdiv = sd_get_clock_divider(sdHostVer, mmc_base_clock, clock);
     temp = read32((pdat->virt + EMMC_CONTROL1));
-    temp |= 1;    
+    temp |= 1;
     temp |= cdiv;
     temp |= (7 << 16);
 
@@ -639,7 +639,7 @@ int raspi_sdmmc_init(void)
 #endif
     mmcsd_change(host);
 #endif
-    return RT_EOK;   
+    return RT_EOK;
 err:
     if (host)  rt_free(host);
     if (sdhci) rt_free(sdhci);
diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_sdio.h b/bsp/raspberry-pi/raspi4-32/driver/drv_sdio.h
index 5919bd64d3..0481a82e6d 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/drv_sdio.h
+++ b/bsp/raspberry-pi/raspi4-32/driver/drv_sdio.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -85,7 +85,7 @@ struct sdhci_t
     rt_uint32_t width;
     rt_uint32_t clock;
     rt_err_t removeable;
-    void * sdcard; 
+    void * sdcard;
 
     rt_err_t (*detect)(struct sdhci_t * sdhci);
     rt_err_t (*setwidth)(struct sdhci_t * sdhci, rt_uint32_t width);
diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_spi.c b/bsp/raspberry-pi/raspi4-32/driver/drv_spi.c
index f0c6351d7f..9c188a8fa9 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/drv_spi.c
+++ b/bsp/raspberry-pi/raspi4-32/driver/drv_spi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -98,11 +98,11 @@ static rt_err_t raspi_spi_configure(struct rt_spi_device *device, struct rt_spi_
 
     if(cfg->mode & RT_SPI_CS_HIGH)
     {
-        SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CSPOL_HIGH;   
+        SPI_REG_CS(hwcfg->hw_base) |= SPI_CS_CSPOL_HIGH;
     }
     else
     {
-        SPI_REG_CS(hwcfg->hw_base) &= ~SPI_CS_CSPOL_HIGH;   
+        SPI_REG_CS(hwcfg->hw_base) &= ~SPI_CS_CSPOL_HIGH;
     }
     return RT_EOK;
 }
@@ -157,7 +157,7 @@ static rt_uint32_t raspi_spi_xfer(struct rt_spi_device *device, struct rt_spi_me
     if (config.mode & RT_SPI_MSB)
     {
         flag = 1;
-    }   
+    }
     else
     {
         flag = 0;
@@ -172,7 +172,7 @@ static rt_uint32_t raspi_spi_xfer(struct rt_spi_device *device, struct rt_spi_me
     {
         SPI_REG_CLK(hwcfg->hw_base) = (RPI_CORE_CLK_HZ / (config.max_hz));
     }
-    
+
     //cs_pin spi0.0
     if(cs_pin == GPIO_PIN_8)
     {
diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_spi.h b/bsp/raspberry-pi/raspi4-32/driver/drv_spi.h
index 9cd8e031e4..8fa8baabe0 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/drv_spi.h
+++ b/bsp/raspberry-pi/raspi4-32/driver/drv_spi.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -70,7 +70,7 @@ struct raspi_spi_hw_config
     GPIO_FUNC  ce2_mode;
 #endif
     rt_ubase_t hw_base;
-    
+
 };
 
 struct raspi_spi_device
diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_uart.c b/bsp/raspberry-pi/raspi4-32/driver/drv_uart.c
index 34b9e1d945..1a3100c745 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/drv_uart.c
+++ b/bsp/raspberry-pi/raspi4-32/driver/drv_uart.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -211,7 +211,7 @@ static const struct rt_uart_ops _uart_ops =
 #ifdef RT_USING_UART1
 static void rt_hw_aux_uart_isr(int irqno, void *param)
 {
-    struct rt_serial_device *serial = (struct rt_serial_device*)param; 
+    struct rt_serial_device *serial = (struct rt_serial_device*)param;
     rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
 }
 #endif
@@ -220,7 +220,7 @@ static void rt_hw_uart_isr(int irqno, void *param)
 {
 #ifdef RT_USING_UART0
     if((PACTL_CS & IRQ_UART0) == IRQ_UART0)
-    {   
+    {
         PACTL_CS &=  ~(IRQ_UART0);
         rt_hw_serial_isr(&_serial0, RT_SERIAL_EVENT_RX_IND);
         PL011_REG_ICR(UART0_BASE) = PL011_INTERRUPT_RECEIVE;
diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_uart.h b/bsp/raspberry-pi/raspi4-32/driver/drv_uart.h
index d57f4e52f4..b2a4552872 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/drv_uart.h
+++ b/bsp/raspberry-pi/raspi4-32/driver/drv_uart.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_wdt.c b/bsp/raspberry-pi/raspi4-32/driver/drv_wdt.c
index 3c091354bb..a9b2e8fc0c 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/drv_wdt.c
+++ b/bsp/raspberry-pi/raspi4-32/driver/drv_wdt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -128,7 +128,7 @@ void reboot(void)
     PM_RSTS |= (PM_PASSWORD | r);   // boot from partition 0
     PM_WDOG |= (PM_PASSWORD | 0x0A);
     PM_RSTC |= (PM_PASSWORD | PM_RSTC_WRCFG_FULL_RESET);
-    
+
     while (1);
 }
 MSH_CMD_EXPORT(reboot,reboot system...);
diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_wdt.h b/bsp/raspberry-pi/raspi4-32/driver/drv_wdt.h
index 4c9454ed91..6998792e0d 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/drv_wdt.h
+++ b/bsp/raspberry-pi/raspi4-32/driver/drv_wdt.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi4-32/driver/lcd/drv_hdmi.c b/bsp/raspberry-pi/raspi4-32/driver/lcd/drv_hdmi.c
index 955e55bcf5..175c6cd907 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/lcd/drv_hdmi.c
+++ b/bsp/raspberry-pi/raspi4-32/driver/lcd/drv_hdmi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -123,7 +123,7 @@ rt_err_t hdmi_fb_control(rt_device_t dev, int cmd, void *args)
 }
 
 #ifdef RT_USING_DEVICE_OPS
-const static struct rt_device_ops hdmi_fb_ops = 
+const static struct rt_device_ops hdmi_fb_ops =
 {
     RT_NULL,
     hdmi_fb_open,
@@ -165,7 +165,7 @@ rt_uint32_t bcm271x_mbox_fb_get_gpiovirt(void)
 {
     mbox[0] = 8*4;                      // length of the message
     mbox[1] = MBOX_REQUEST;             // this is a request message
-    
+
     mbox[2] = MBOX_TAG_FB_GET_GPIOVIRT;
     mbox[3] = 4;                        // buffer size
     mbox[4] = 0;                        // len
@@ -182,7 +182,7 @@ rt_uint32_t bcm271x_mbox_fb_get_pitch(void)
 {
     mbox[0] = 8*4;                  // length of the message
     mbox[1] = MBOX_REQUEST;         // this is a request message
-    
+
     mbox[2] = MBOX_TAG_FB_GET_PITCH;
     mbox[3] = 4;                    // buffer size
     mbox[4] = 0;                    // len
@@ -199,7 +199,7 @@ void bcm271x_mbox_fb_set_porder(int rgb)
 {
     mbox[0] = 8*4;                      // length of the message
     mbox[1] = MBOX_REQUEST;             // this is a request message
-    
+
     mbox[2] = MBOX_TAG_FB_SET_PIXEL_ORDER;
     mbox[3] = 4;                        // buffer size
     mbox[4] = 4;                        // len
@@ -215,7 +215,7 @@ void bcm271x_mbox_fb_setoffset(int xoffset, int yoffset)
 {
     mbox[0] = 8*4;                      // length of the message
     mbox[1] = MBOX_REQUEST;             // this is a request message
-    
+
     mbox[2] = MBOX_TAG_FB_SET_VIRT_OFFSET;
     mbox[3] = 8;                        // buffer size
     mbox[4] = 8;                        // len
@@ -233,7 +233,7 @@ void bcm271x_mbox_fb_setalpha(int alpha)
 
     mbox[0] = 8*4;                      // length of the message
     mbox[1] = MBOX_REQUEST;             // this is a request message
-    
+
     mbox[2] = MBOX_TAG_FB_SET_ALPHA_MODE;
     mbox[3] = 4;                        // buffer size
     mbox[4] = 4;                        // len
diff --git a/bsp/raspberry-pi/raspi4-32/driver/lcd/drv_hdmi.h b/bsp/raspberry-pi/raspi4-32/driver/lcd/drv_hdmi.h
index c9a06358d0..b9901e204b 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/lcd/drv_hdmi.h
+++ b/bsp/raspberry-pi/raspi4-32/driver/lcd/drv_hdmi.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi4-32/driver/lcd/drv_ili9486.c b/bsp/raspberry-pi/raspi4-32/driver/lcd/drv_ili9486.c
index c2317bd112..7db4940c97 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/lcd/drv_ili9486.c
+++ b/bsp/raspberry-pi/raspi4-32/driver/lcd/drv_ili9486.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -89,7 +89,7 @@ void lcd_write_data(rt_uint8_t data)
 }
 
 /*Ser rotation of the screen - changes x0 and y0*/
-static inline void lcd_set_rotation(uint8_t rotation) 
+static inline void lcd_set_rotation(uint8_t rotation)
 {
     writeCommand(lcd_dev, 0x36);
     rt_thread_mdelay(100);
@@ -134,7 +134,7 @@ static inline void lcd_set_rotation(uint8_t rotation)
         lcd_write_data(0x01);
         lcd_write_data(0xE0);
     }
-    
+
     if((rotation == SCREEN_HORIZONTAL_1) || (rotation == SCREEN_HORIZONTAL_2))
     {
         lcd_write_commmand(0x2B);
@@ -177,7 +177,7 @@ static inline void fast_send_data(void)
     rt_sem_release(&lcd_spi_lock);
 }
 
-static inline void lcd_show(void) 
+static inline void lcd_show(void)
 {
 
     lcd_write_commmand(0x2C); // Memory write?
@@ -188,11 +188,11 @@ static inline void lcd_show(void)
     fast_send_data();
 #else
     int i, j;
-    for (i = 0 ; i < 30  ; i ++) 
+    for (i = 0 ; i < 30  ; i ++)
     {
         uint16_t *tx_data = (uint16_t*)&send_buffer[5120* i];
         int32_t data_sz = 5120;
-        for( j=0; jdepth >= 3)
         {
-            uint32_t *addr_32bit = (uint32_t*) (fb->vaddr) + (fb->height - CHAR_H) * fb->width;        
+            uint32_t *addr_32bit = (uint32_t*) (fb->vaddr) + (fb->height - CHAR_H) * fb->width;
 
             for (i = 0; i < (CHAR_H * fb->width); i++)
             {
@@ -64,7 +64,7 @@ static void newline(fb_t* fb)
         }
         else
         {
-            uint16_t *addr_16bit = (uint16_t*) (fb->vaddr) + (fb->height - CHAR_H) * fb->width;        
+            uint16_t *addr_16bit = (uint16_t*) (fb->vaddr) + (fb->height - CHAR_H) * fb->width;
 
             for (i = 0; i < (CHAR_H * fb->width); i++)
             {
@@ -107,7 +107,7 @@ static void fb_draw_char(fb_t *fb, char s)
             {
                 *((unsigned short*) (addr + line)) = ((int) *(glyph + ((i)/8)) * 1) & mask ? fb->fore : fb->back;
             }
-            
+
             mask >>= 1;
             if(mask == 0)
             {
@@ -170,12 +170,12 @@ void fb_print(char *s)
     {
         rt_device_control(console_dev,RTGRAPHIC_CTRL_RECT_UPDATE, RT_NULL);
     }
-#endif 
+#endif
 }
 
 #ifndef LCD_CONSOLE_FLUSH_NOW
 void lcd_console_task_entry(void *param)
-{   
+{
     fb_t *fb = (fb_t *)param;
     while (1)
     {
@@ -186,7 +186,7 @@ void lcd_console_task_entry(void *param)
         }
         rt_thread_mdelay(LCD_CONSOLE_DELAY);
     }
-    
+
 }
 #endif
 
@@ -199,7 +199,7 @@ int lcd_console_init(void)
         rt_kprintf("no console dev!\n");
         return 0;
     }
-    
+
     if(console_dev->ref_count >= 1)
     {
         rt_kprintf("lcd console has open!\n");
@@ -209,7 +209,7 @@ int lcd_console_init(void)
     rt_device_open(console_dev,RT_DEVICE_OFLAG_RDWR);
 
     rt_device_control(console_dev, RTGRAPHIC_CTRL_GET_INFO, &info);
-        
+
     virt_buffer = (rt_uint8_t* )rt_malloc(info.width * info.height * (info.bits_per_pixel/8));
     rt_memset(virt_buffer, 0 , info.width * info.height * (info.bits_per_pixel/8));
     console_fb.width = info.width;
@@ -246,7 +246,7 @@ int lcd_console_init(void)
     * #ifdef USING_LCD_CONSOLE
     *     fb_print((char*)rt_log_buf);
     * #endif
-    * 
+    *
     * remove rt_console_set_device(CONSOLE_NAME);
     */
     rt_console_set_device(CONSOLE_NAME);
diff --git a/bsp/raspberry-pi/raspi4-32/driver/lcd/lcd_console.h b/bsp/raspberry-pi/raspi4-32/driver/lcd/lcd_console.h
index ebe6afa068..2bc7a1ceb1 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/lcd/lcd_console.h
+++ b/bsp/raspberry-pi/raspi4-32/driver/lcd/lcd_console.h
@@ -1,6 +1,6 @@
 
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,10 +15,10 @@
 
 #define RGB(r, g, b) ((((r))<<16) | (((g))<<8) | ((b)))
 #define COLOR_BLACK RGB(0, 0, 0)
-#define COLOR_GREEN RGB(0, 255, 0)  
-#define COLOR_CYAN RGB(0, 255, 255) 
-#define COLOR_RED RGB(255, 0, 0)  
-#define COLOR_YELLOW RGB(255, 255, 0) 
+#define COLOR_GREEN RGB(0, 255, 0)
+#define COLOR_CYAN RGB(0, 255, 255)
+#define COLOR_RED RGB(255, 0, 0)
+#define COLOR_YELLOW RGB(255, 255, 0)
 #define COLOR_WHITE RGB(255, 255, 255)
 
 #define CONSOLE_WHITE_32 COLOR_WHITE
diff --git a/bsp/raspberry-pi/raspi4-32/driver/lcd/lcd_font_20.h b/bsp/raspberry-pi/raspi4-32/driver/lcd/lcd_font_20.h
index 7ef56d7e3c..55610713d9 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/lcd/lcd_font_20.h
+++ b/bsp/raspberry-pi/raspi4-32/driver/lcd/lcd_font_20.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi4-32/driver/mbox.c b/bsp/raspberry-pi/raspi4-32/driver/mbox.c
index 0f993f945a..ecb357c82d 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/mbox.c
+++ b/bsp/raspberry-pi/raspi4-32/driver/mbox.c
@@ -1,6 +1,6 @@
 /*
  * File      : mbox.c
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,7 +15,7 @@
 #include "mmu.h"
 //volatile unsigned int  __attribute__((aligned(16))) mbox[36];
 volatile unsigned int *mbox = (volatile unsigned int *) MBOX_ADDR;
-#define BUS_ADDRESS(phys)	(((phys) & ~0xC0000000)  |  0xC0000000)
+#define BUS_ADDRESS(phys)   (((phys) & ~0xC0000000)  |  0xC0000000)
 
 /**
  * Make a mailbox call. Returns 0 on failure, non-zero on success
@@ -53,8 +53,8 @@ int bcm271x_mbox_get_touch(void)
 {
     mbox[0] = 8*4;                      // length of the message
     mbox[1] = MBOX_REQUEST;             // this is a request message
-    
-    mbox[2] = MBOX_TAG_GET_TOUCHBUF; 
+
+    mbox[2] = MBOX_TAG_GET_TOUCHBUF;
     mbox[3] = 4;                        // buffer size
     mbox[4] = 0;                        // len
 
@@ -76,7 +76,7 @@ int bcm271x_notify_reboot(void)
     mbox[4] = 0x00000000;                   // size of the data
     mbox[5] = 0x00000000;                   // request
 
-    mbox[6] = MBOX_TAG_LAST; 
+    mbox[6] = MBOX_TAG_LAST;
     mbox_call(8, MMU_DISABLE);
     return 0;
 }
@@ -89,7 +89,7 @@ int bcm271x_notify_xhci_reset(void)
     mbox[3] = 0x00000004;                   // length + 4
     mbox[4] = 0x00000004;                   // size of the data
     mbox[5] = 0x00100000;                   // request
-    mbox[6] = MBOX_TAG_LAST; 
+    mbox[6] = MBOX_TAG_LAST;
     mbox_call(8, MMU_DISABLE);
     return 0;
 }
@@ -98,7 +98,7 @@ int bcm271x_gpu_enable(void)
 {
     mbox[0] = 12*4;                          // length of the message
     mbox[1] = MBOX_REQUEST;                  // this is a request message
-    
+
     mbox[2] = MBOX_TAG_CLOCK_SET_RATE;
     mbox[3] = 0x00000008;                   // (the tag id)
     mbox[4] = 0x00000008;                   // (the tag id)
@@ -117,12 +117,12 @@ int bcm271x_mbox_hardware_get_model(void)
 {
     mbox[0] = 8*4;                          // length of the message
     mbox[1] = MBOX_REQUEST;                 // this is a request message
-    
+
     mbox[2] = MBOX_TAG_HARDWARE_GET_MODEL;
     mbox[3] = 4;                            // buffer size
     mbox[4] = 0;                            // len
 
-    mbox[5] = 0;                            
+    mbox[5] = 0;
     mbox[6] = 0;
 
     mbox[7] = MBOX_TAG_LAST;
@@ -135,12 +135,12 @@ int bcm271x_mbox_hardware_get_revison(void)
 {
     mbox[0] = 8*4;                          // length of the message
     mbox[1] = MBOX_REQUEST;                 // this is a request message
-    
-    mbox[2] = MBOX_TAG_HARDWARE_GET_REV;   
+
+    mbox[2] = MBOX_TAG_HARDWARE_GET_REV;
     mbox[3] = 4;                            // buffer size
     mbox[4] = 0;                            // len
 
-    mbox[5] = 0;                    
+    mbox[5] = 0;
     mbox[6] = 0;
 
     mbox[7] = MBOX_TAG_LAST;
@@ -153,12 +153,12 @@ int bcm271x_mbox_hardware_get_mac_address(uint8_t * mac)
 {
     mbox[0] = 8*4;                                 // length of the message
     mbox[1] = MBOX_REQUEST;                        // this is a request message
-    
-    mbox[2] = MBOX_TAG_HARDWARE_GET_MAC_ADDRESS;   
+
+    mbox[2] = MBOX_TAG_HARDWARE_GET_MAC_ADDRESS;
     mbox[3] = 6;                                   // buffer size
     mbox[4] = 0;                                   // len
 
-    mbox[5] = 0;                    
+    mbox[5] = 0;
     mbox[6] = 0;
 
     mbox[7] = MBOX_TAG_LAST;
@@ -179,12 +179,12 @@ int bcm271x_mbox_hardware_get_serial(rt_uint64_t* sn)
 {
     mbox[0] = 8*4;                              // length of the message
     mbox[1] = MBOX_REQUEST;                     // this is a request message
-    
-    mbox[2] = MBOX_TAG_HARDWARE_GET_SERIAL;    
+
+    mbox[2] = MBOX_TAG_HARDWARE_GET_SERIAL;
     mbox[3] = 8;                                // buffer size
     mbox[4] = 0;                                // len
 
-    mbox[5] = 0;                    
+    mbox[5] = 0;
     mbox[6] = 0;
 
     mbox[7] = MBOX_TAG_LAST;
@@ -199,12 +199,12 @@ int bcm271x_mbox_hardware_get_arm_memory(rt_uint32_t * base, rt_uint32_t * size)
 {
     mbox[0] = 8*4;                                  // length of the message
     mbox[1] = MBOX_REQUEST;                         // this is a request message
-    
-    mbox[2] = MBOX_TAG_HARDWARE_GET_ARM_MEMORY;   
+
+    mbox[2] = MBOX_TAG_HARDWARE_GET_ARM_MEMORY;
     mbox[3] = 8;                                    // buffer size
     mbox[4] = 0;                                    // len
 
-    mbox[5] = 0;                    
+    mbox[5] = 0;
     mbox[6] = 0;
 
     mbox[7] = MBOX_TAG_LAST;
@@ -212,7 +212,7 @@ int bcm271x_mbox_hardware_get_arm_memory(rt_uint32_t * base, rt_uint32_t * size)
 
     *base = mbox[5];
     *size = mbox[6];
-    
+
     return 0;
 
 }
@@ -221,12 +221,12 @@ int bcm271x_mbox_hardware_get_vc_memory(rt_uint32_t * base, rt_uint32_t * size)
 {
     mbox[0] = 8*4;                               // length of the message
     mbox[1] = MBOX_REQUEST;                      // this is a request message
-    
+
     mbox[2] = MBOX_TAG_HARDWARE_GET_VC_MEMORY;
     mbox[3] = 8;                                 // buffer size
     mbox[4] = 0;                                 // len
 
-    mbox[5] = 0;                    
+    mbox[5] = 0;
     mbox[6] = 0;
 
     mbox[7] = MBOX_TAG_LAST;
@@ -234,7 +234,7 @@ int bcm271x_mbox_hardware_get_vc_memory(rt_uint32_t * base, rt_uint32_t * size)
 
     *base = mbox[5];
     *size = mbox[6];
-    
+
     return 0;
 }
 
@@ -242,8 +242,8 @@ int bcm271x_mbox_clock_get_turbo(void)
 {
     mbox[0] = 8*4;                      // length of the message
     mbox[1] = MBOX_REQUEST;             // this is a request message
-    
-    mbox[2] = MBOX_TAG_CLOCK_GET_TURBO; 
+
+    mbox[2] = MBOX_TAG_CLOCK_GET_TURBO;
     mbox[3] = 8;                        // buffer size
     mbox[4] = 4;                        // len
 
@@ -265,8 +265,8 @@ int bcm271x_mbox_clock_set_turbo(int level)
 {
     mbox[0] = 8*4;                      // length of the message
     mbox[1] = MBOX_REQUEST;             // this is a request message
-    
-    mbox[2] = MBOX_TAG_CLOCK_SET_TURBO;  
+
+    mbox[2] = MBOX_TAG_CLOCK_SET_TURBO;
     mbox[3] = 8;                        // buffer size
     mbox[4] = 8;                        // len
 
@@ -288,7 +288,7 @@ int bcm271x_mbox_clock_get_state(int id)
 {
     mbox[0] = 8*4;                       // length of the message
     mbox[1] = MBOX_REQUEST;              // this is a request message
-    
+
     mbox[2] = MBOX_TAG_CLOCK_GET_STATE;
     mbox[3] = 8;                         // buffer size
     mbox[4] = 4;                         // len
@@ -311,7 +311,7 @@ int bcm271x_mbox_clock_set_state(int id, int state)
 {
     mbox[0] = 8*4;                      // length of the message
     mbox[1] = MBOX_REQUEST;             // this is a request message
-    
+
     mbox[2] = MBOX_TAG_CLOCK_SET_STATE;
     mbox[3] = 8;                        // buffer size
     mbox[4] = 8;                        // len
@@ -334,8 +334,8 @@ int bcm271x_mbox_clock_get_rate(int id)
 {
     mbox[0] = 8*4;                      // length of the message
     mbox[1] = MBOX_REQUEST;             // this is a request message
-    
-    mbox[2] = MBOX_TAG_CLOCK_GET_RATE; 
+
+    mbox[2] = MBOX_TAG_CLOCK_GET_RATE;
     mbox[3] = 8;                        // buffer size
     mbox[4] = 4;                        // len
 
@@ -357,7 +357,7 @@ int bcm271x_mbox_clock_set_rate(int id, int rate)
 {
     mbox[0] = 8*4;                      // length of the message
     mbox[1] = MBOX_REQUEST;             // this is a request message
-    
+
     mbox[2] = MBOX_TAG_CLOCK_SET_RATE;
     mbox[3] = 8;                        // buffer size
     mbox[4] = 8;                        // len
@@ -380,7 +380,7 @@ int bcm271x_mbox_clock_get_max_rate(int id)
 {
     mbox[0] = 8*4;                          // length of the message
     mbox[1] = MBOX_REQUEST;                 // this is a request message
-    
+
     mbox[2] = MBOX_TAG_CLOCK_GET_MAX_RATE;
     mbox[3] = 8;                            // buffer size
     mbox[4] = 4;                            // len
@@ -403,8 +403,8 @@ int bcm271x_mbox_clock_get_min_rate(int id)
 {
     mbox[0] = 8*4;                          // length of the message
     mbox[1] = MBOX_REQUEST;                 // this is a request message
-    
-    mbox[2] = MBOX_TAG_CLOCK_GET_MIN_RATE; 
+
+    mbox[2] = MBOX_TAG_CLOCK_GET_MIN_RATE;
     mbox[3] = 8;                            // buffer size
     mbox[4] = 4;                            // len
 
@@ -426,7 +426,7 @@ int bcm271x_mbox_power_get_state(int id)
 {
     mbox[0] = 8*4;                  // length of the message
     mbox[1] = MBOX_REQUEST;         // this is a request message
-    
+
     mbox[2] = MBOX_TAG_POWER_GET_STATE;
     mbox[3] = 8;                    // buffer size
     mbox[4] = 4;                    // len
@@ -449,7 +449,7 @@ int bcm271x_mbox_power_set_state(int id, int state)
 {
     mbox[0] = 8*4;                  // length of the message
     mbox[1] = MBOX_REQUEST;         // this is a request message
-    
+
     mbox[2] = MBOX_TAG_POWER_SET_STATE;
     mbox[3] = 8;                    // buffer size
     mbox[4] = 8;                    // len
@@ -472,7 +472,7 @@ int bcm271x_mbox_temp_get(void)
 {
     mbox[0] = 8*4;                  // length of the message
     mbox[1] = MBOX_REQUEST;         // this is a request message
-    
+
     mbox[2] = MBOX_TAG_TEMP_GET;
     mbox[3] = 8;                    // buffer size
     mbox[4] = 4;                    // len
@@ -495,7 +495,7 @@ int bcm271x_mbox_temp_get_max(void)
 {
     mbox[0] = 8*4;                  // length of the message
     mbox[1] = MBOX_REQUEST;         // this is a request message
-    
+
     mbox[2] = MBOX_TAG_TEMP_GET_MAX;
     mbox[3] = 8;                    // buffer size
     mbox[4] = 4;                    // len
diff --git a/bsp/raspberry-pi/raspi4-32/driver/mbox.h b/bsp/raspberry-pi/raspi4-32/driver/mbox.h
index 7a05597de4..2c69bcf55a 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/mbox.h
+++ b/bsp/raspberry-pi/raspi4-32/driver/mbox.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi4-32/driver/raspi4.h b/bsp/raspberry-pi/raspi4-32/driver/raspi4.h
index 72e212ff85..bba81ea311 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/raspi4.h
+++ b/bsp/raspberry-pi/raspi4-32/driver/raspi4.h
@@ -149,8 +149,8 @@ typedef enum {
     } while (0) \
 
 //External Mass Media Controller (SD Card)
-#define MMC0_BASE_ADDR		(PER_BASE+0x300000)   
-#define MMC2_BASE_ADDR		(PER_BASE+0x340000)
+#define MMC0_BASE_ADDR      (PER_BASE+0x300000)
+#define MMC2_BASE_ADDR      (PER_BASE+0x340000)
 
 #define ETH_IRQ                 (160+29)
 
@@ -162,7 +162,7 @@ typedef enum {
 #define BSC5_BASE_OFFSET            (0x205A80)
 #define BSC6_BASE_OFFSET            (0x205C00)
 
-//BSC2 and BSC7 masters are dedicated for use by the 
+//BSC2 and BSC7 masters are dedicated for use by the
 //HDMI interfaces and should not be accessed byuser programs.
 #define BSC0_BASE                   (PER_BASE + BSC0_BASE_OFFSET)
 #define BSC1_BASE                   (PER_BASE + BSC1_BASE_OFFSET)
diff --git a/bsp/raspberry-pi/raspi4-32/driver/touch/drv_dsi_touch.c b/bsp/raspberry-pi/raspi4-32/driver/touch/drv_dsi_touch.c
index 894ef1f25c..3f9dbb83ad 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/touch/drv_dsi_touch.c
+++ b/bsp/raspberry-pi/raspi4-32/driver/touch/drv_dsi_touch.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -58,7 +58,7 @@ static void dsi_touch_thread_entry(void *param)
         rt_kprintf("init dsi touch err!\n");
         return;
     }
-    
+
     while (1)
     {
         struct touch_regs *regs = (struct touch_regs *)touchbuf;
@@ -73,7 +73,7 @@ static void dsi_touch_thread_entry(void *param)
         {
             touch_state = 0;
         }
-        rt_thread_mdelay(50); 
+        rt_thread_mdelay(50);
     }
 }
 
diff --git a/bsp/raspberry-pi/raspi4-32/driver/touch/drv_dsi_touch.h b/bsp/raspberry-pi/raspi4-32/driver/touch/drv_dsi_touch.h
index 6d6439f199..ea70191dde 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/touch/drv_dsi_touch.h
+++ b/bsp/raspberry-pi/raspi4-32/driver/touch/drv_dsi_touch.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi4-32/driver/touch/drv_xpt2046.c b/bsp/raspberry-pi/raspi4-32/driver/touch/drv_xpt2046.c
index 489701f079..5911b5b6e3 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/touch/drv_xpt2046.c
+++ b/bsp/raspberry-pi/raspi4-32/driver/touch/drv_xpt2046.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -104,7 +104,7 @@ no pressed:(0x800,0xfff)
 ------------------------------------
 */
 #define XMIN 0x800
-#define YMAX 0xfff 
+#define YMAX 0xfff
 void read_tp(void *dev, rt_uint16_t *x, rt_uint16_t *y)
 {
     struct rt_spi_device *touch_dev = (struct rt_spi_device *)dev;
diff --git a/bsp/raspberry-pi/raspi4-32/driver/touch/drv_xpt2046.h b/bsp/raspberry-pi/raspi4-32/driver/touch/drv_xpt2046.h
index 5b28c0a7dd..0a88546250 100644
--- a/bsp/raspberry-pi/raspi4-32/driver/touch/drv_xpt2046.h
+++ b/bsp/raspberry-pi/raspi4-32/driver/touch/drv_xpt2046.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi4-32/link.lds b/bsp/raspberry-pi/raspi4-32/link.lds
index 92ec03c8f4..df4ecb5ad3 100644
--- a/bsp/raspberry-pi/raspi4-32/link.lds
+++ b/bsp/raspberry-pi/raspi4-32/link.lds
@@ -1,20 +1,7 @@
 /*
- * File      : link.lds
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * 2017-5-30     bernard       first version
@@ -40,7 +27,7 @@ SECTIONS
         *(.gnu.linkonce.t*)
 
         *(COMMON)
-        
+
         /* section information for finsh shell */
         . = ALIGN(16);
         __fsymtab_start = .;
@@ -118,7 +105,7 @@ SECTIONS
         *(.bss)
         *(.bss.*)
         *(.dynbss)
-        
+
         PROVIDE(__bss_end = .);
     }
     _end = .;
diff --git a/bsp/raspberry-pi/raspi4-64/applications/main.c b/bsp/raspberry-pi/raspi4-64/applications/main.c
index 9664e67d01..9400e2a598 100644
--- a/bsp/raspberry-pi/raspi4-64/applications/main.c
+++ b/bsp/raspberry-pi/raspi4-64/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi4-64/driver/board.c b/bsp/raspberry-pi/raspi4-64/driver/board.c
index 79a24d184f..0fbd4921f8 100644
--- a/bsp/raspberry-pi/raspi4-64/driver/board.c
+++ b/bsp/raspberry-pi/raspi4-64/driver/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -44,7 +44,7 @@ void rt_hw_timer_init(void)
     timerStep = rt_hw_get_gtimer_frq();
     __DSB();
     timerStep /= RT_TICK_PER_SECOND;
-    
+
     rt_hw_gtimer_enable();
     rt_hw_set_gtimer_val(timerStep);
     core0_timer_enable_interrupt_controller();
@@ -56,7 +56,7 @@ void idle_wfi(void)
 }
 
 /**
- *  Initialize the Hardware related stuffs. Called from rtthread_startup() 
+ *  Initialize the Hardware related stuffs. Called from rtthread_startup()
  *  after interrupt disabled.
  */
 void rt_hw_board_init(void)
diff --git a/bsp/raspberry-pi/raspi4-64/driver/board.h b/bsp/raspberry-pi/raspi4-64/driver/board.h
index d675cc658e..29019514b9 100644
--- a/bsp/raspberry-pi/raspi4-64/driver/board.h
+++ b/bsp/raspberry-pi/raspi4-64/driver/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi4-64/driver/drv_gpio.c b/bsp/raspberry-pi/raspi4-64/driver/drv_gpio.c
index bba20a86a4..f526ff99e6 100644
--- a/bsp/raspberry-pi/raspi4-64/driver/drv_gpio.c
+++ b/bsp/raspberry-pi/raspi4-64/driver/drv_gpio.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -71,7 +71,7 @@ static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t valu
         {
             GPIO_REG_GPCLR1(GPIO_BASE) = 1 << (pin % 32);
         }
-        
+
     }
 }
 
diff --git a/bsp/raspberry-pi/raspi4-64/driver/drv_gpio.h b/bsp/raspberry-pi/raspi4-64/driver/drv_gpio.h
index c4658fcebb..3627b51593 100644
--- a/bsp/raspberry-pi/raspi4-64/driver/drv_gpio.h
+++ b/bsp/raspberry-pi/raspi4-64/driver/drv_gpio.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi4-64/driver/drv_uart.c b/bsp/raspberry-pi/raspi4-64/driver/drv_uart.c
index 6a70cdfb3a..597682df34 100644
--- a/bsp/raspberry-pi/raspi4-64/driver/drv_uart.c
+++ b/bsp/raspberry-pi/raspi4-64/driver/drv_uart.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -117,7 +117,7 @@ static const struct rt_uart_ops _uart_ops =
 
 static void rt_hw_uart_isr(int irqno, void *param)
 {
-    struct rt_serial_device *serial = (struct rt_serial_device*)param; 
+    struct rt_serial_device *serial = (struct rt_serial_device*)param;
     rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
     PL011_REG_ICR(UART0_BASE) = PL011_INTERRUPT_RECEIVE;
 }
diff --git a/bsp/raspberry-pi/raspi4-64/driver/drv_uart.h b/bsp/raspberry-pi/raspi4-64/driver/drv_uart.h
index 714043efd3..1dfb9b7e04 100644
--- a/bsp/raspberry-pi/raspi4-64/driver/drv_uart.h
+++ b/bsp/raspberry-pi/raspi4-64/driver/drv_uart.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/raspberry-pi/raspi4-64/link.lds b/bsp/raspberry-pi/raspi4-64/link.lds
index b7b2dcc32c..a624a973b4 100644
--- a/bsp/raspberry-pi/raspi4-64/link.lds
+++ b/bsp/raspberry-pi/raspi4-64/link.lds
@@ -1,20 +1,7 @@
 /*
- * File      : link.lds
- * COPYRIGHT (C) 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * 2017-5-30     bernard       first version
@@ -40,7 +27,7 @@ SECTIONS
         *(.gnu.linkonce.t*)
 
         *(COMMON)
-        
+
         /* section information for finsh shell */
         . = ALIGN(16);
         __fsymtab_start = .;
@@ -110,7 +97,7 @@ SECTIONS
         *(.bss)
         *(.bss.*)
         *(.dynbss)
-        
+
         PROVIDE(__bss_end = .);
     }
     _end = .;
diff --git a/bsp/raspberry-pico/README.md b/bsp/raspberry-pico/README.md
index c238850b9b..eaac07017b 100644
--- a/bsp/raspberry-pico/README.md
+++ b/bsp/raspberry-pico/README.md
@@ -64,14 +64,14 @@ msh >
 
 ## Peripheral Condition
 
-| Drive | Support | Remark |
-| ----- | ------- | ------ |
-| UART  | Support | UART0  |
-| GPIO  | Support | 0-29   |
-| I2C   | -       | -      |
-| RTC   | -       | -      |
-| SDIO  | -       | -      |
-| SPI   | -       | -      |
-| TIMER | -       | -      |
-| WDT   | -       | -      |
+| Drive | Support | Remark  |
+| ----- | ------- | ------- |
+| UART  | Support | UART0/1 |
+| GPIO  | Support | 0-29    |
+| I2C   | -       | -       |
+| RTC   | -       | -       |
+| SDIO  | -       | -       |
+| SPI   | -       | -       |
+| TIMER | -       | -       |
+| WDT   | -       | -       |
 
diff --git a/bsp/raspberry-pico/drivers/board.c b/bsp/raspberry-pico/drivers/board.c
index af8bcb4f80..ff99bbfe86 100644
--- a/bsp/raspberry-pico/drivers/board.c
+++ b/bsp/raspberry-pico/drivers/board.c
@@ -16,8 +16,6 @@
 #include "board.h"
 #include "hardware/structs/systick.h"
 
-uint8_t heap[1024 * 80];
-
 void isr_systick(void)
 {
     /* enter interrupt */
@@ -45,11 +43,25 @@ uint32_t systick_config(uint32_t ticks)
 
 void rt_hw_board_init()
 {
+    rt_system_heap_init(HEAP_BEGIN, HEAP_END);
+
+    alarm_pool_init_default();
+
+    // Start and end points of the constructor list,
+    // defined by the linker script.
+    extern void (*__init_array_start)();
+    extern void (*__init_array_end)();
+
+    // Call each function in the list.
+    // We have to take the address of the symbols, as __init_array_start *is*
+    // the first function pointer, not the address of it.
+    for (void (**p)() = &__init_array_start; p < &__init_array_end; ++p) {
+        (*p)();
+    }
+
     /* Configure the SysTick */
     systick_config(frequency_count_khz(CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC)*10000/RT_TICK_PER_SECOND);
 
-    rt_system_heap_init(heap, (uint8_t *)heap + sizeof(heap));
-
     stdio_init_all();
     rt_hw_uart_init();
 
diff --git a/bsp/raspberry-pico/drivers/board.h b/bsp/raspberry-pico/drivers/board.h
index e762b479f8..0c418d5c4e 100644
--- a/bsp/raspberry-pico/drivers/board.h
+++ b/bsp/raspberry-pico/drivers/board.h
@@ -20,9 +20,9 @@
 #define PICO_SRAM_SIZE         256
 #define PICO_SRAM_END          (0x20000000 + PICO_SRAM_SIZE * 1024)
 
-extern int __bss_end;
-#define HEAP_BEGIN      (&__bss_end)
-#define HEAP_END        PICO_SRAM_END
+extern int __bss_end__;
+#define HEAP_BEGIN      (&__bss_end__)
+#define HEAP_END        ((void *)PICO_SRAM_END)
 
 int rt_hw_uart_init(void);
 
diff --git a/bsp/raspberry-pico/drivers/drv_uart.c b/bsp/raspberry-pico/drivers/drv_uart.c
index 48599e01f8..6077b60f92 100644
--- a/bsp/raspberry-pico/drivers/drv_uart.c
+++ b/bsp/raspberry-pico/drivers/drv_uart.c
@@ -60,6 +60,23 @@ static rt_err_t pico_uart_configure(struct rt_serial_device *serial, struct seri
 
 static rt_err_t pico_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
 {
+    // Select correct interrupt for the UART we are using
+    int UART_IRQ = UART_ID == uart0 ? UART0_IRQ : UART1_IRQ;
+
+    switch (cmd)
+    {
+    /* enable interrupt */
+    case RT_DEVICE_CTRL_SET_INT:
+        // Set up a RX interrupt
+        // We need to set up the handler first
+        // And set up and enable the interrupt handlers
+        irq_set_exclusive_handler(UART_IRQ, pico_uart_isr);
+        irq_set_enabled(UART_IRQ, true);
+
+        // Now enable the UART to send interrupts - RX only
+        uart_set_irq_enables(UART_ID, true, false);
+        break;
+    }
     return RT_EOK;
 }
 
@@ -125,18 +142,6 @@ int rt_hw_uart_init(void)
     // Turn off FIFO's - we want to do this character by character
     uart_set_fifo_enabled(UART_ID, false);
 
-    // Set up a RX interrupt
-    // We need to set up the handler first
-    // Select correct interrupt for the UART we are using
-    int UART_IRQ = UART_ID == uart0 ? UART0_IRQ : UART1_IRQ;
-
-    // And set up and enable the interrupt handlers
-    irq_set_exclusive_handler(UART_IRQ, pico_uart_isr);
-    irq_set_enabled(UART_IRQ, true);
-
-    // Now enable the UART to send interrupts - RX only
-    uart_set_irq_enables(UART_ID, true, false);
-
     uart0_dev.parent.ops = &_uart_ops;
     uart0_dev.parent.config = config;
 
@@ -148,3 +153,130 @@ int rt_hw_uart_init(void)
     return ret;
 }
 // INIT_DEVICE_EXPORT(rt_hw_uart_init);
+
+// We are using pins 0 and 1, but see the GPIO function select table in the
+// datasheet for information on which other pins can be used.
+#define UART1_TX_PIN 4
+#define UART1_RX_PIN 5
+
+static struct pico_uart1_dev uart1_dev;
+
+struct pico_uart1_dev
+{
+    struct rt_serial_device parent;
+    rt_uint32_t uart_periph;
+    rt_uint32_t irqno;
+};
+
+void pico_uart1_isr(void)
+{
+    rt_interrupt_enter();
+    /* read interrupt status and clear it */
+    if (uart_is_readable(uart1)) /* rx ind */
+    {
+        rt_hw_serial_isr(&uart1_dev.parent, RT_SERIAL_EVENT_RX_IND);
+    }
+
+    rt_interrupt_leave();
+}
+
+/*
+ * UART interface
+ */
+static rt_err_t pico_uart1_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    return RT_EOK;
+}
+
+static rt_err_t pico_uart1_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    switch (cmd)
+    {
+    /* enable interrupt */
+    case RT_DEVICE_CTRL_SET_INT:
+        // Set up a RX interrupt
+        // We need to set up the handler first
+        // And set up and enable the interrupt handlers
+        irq_set_exclusive_handler(UART1_IRQ, pico_uart1_isr);
+        irq_set_enabled(UART1_IRQ, true);
+
+        // Now enable the UART to send interrupts - RX only
+        uart_set_irq_enables(uart1, true, false);
+        break;
+    }
+    return RT_EOK;
+}
+
+static int pico_uart1_putc(struct rt_serial_device *serial, char c)
+{
+    uart_putc_raw(uart1, c);
+
+    return 1;
+}
+
+static int pico_uart1_getc(struct rt_serial_device *serial)
+{
+    int ch;
+
+    if (uart_is_readable(uart1))
+    {
+        ch = uart_get_hw(uart1)->dr;
+    }
+    else
+    {
+        ch =-1;
+    }
+
+    return ch;
+}
+
+const static struct rt_uart_ops _uart1_ops =
+{
+    pico_uart1_configure,
+    pico_uart1_control,
+    pico_uart1_putc,
+    pico_uart1_getc,
+    RT_NULL,
+};
+
+/*
+ * UART Initiation
+ */
+int rt_hw_uart1_init(void)
+{
+    rt_err_t ret = RT_EOK;
+
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+    uart_init(uart1, 115200);
+
+    // Set the TX and RX pins by using the function select on the GPIO
+    // Set datasheet for more information on function select
+    gpio_set_function(UART1_TX_PIN, GPIO_FUNC_UART);
+    gpio_set_function(UART1_RX_PIN, GPIO_FUNC_UART);
+
+    // Actually, we want a different speed
+    // The call will return the actual baud rate selected, which will be as close as
+    // possible to that requested
+    uart_set_baudrate(uart1, BAUD_RATE);
+
+    // Set UART flow control CTS/RTS, we don't want these, so turn them off
+    uart_set_hw_flow(uart1, false, false);
+
+    // Set our data format
+    uart_set_format(uart1, DATA_BITS, STOP_BITS, PARITY);
+
+    // Turn off FIFO's - we want to do this character by character
+    uart_set_fifo_enabled(uart1, false);
+
+    uart1_dev.parent.ops = &_uart1_ops;
+    uart1_dev.parent.config = config;
+
+    ret = rt_hw_serial_register(&uart1_dev.parent,
+                                "uart1",
+                                RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                                &uart1_dev);
+
+    return ret;
+}
+INIT_DEVICE_EXPORT(rt_hw_uart1_init);
diff --git a/bsp/raspberry-pico/libraries/pico-sdk/src/rp2_common/pico_runtime/runtime.c b/bsp/raspberry-pico/libraries/pico-sdk/src/rp2_common/pico_runtime/runtime.c
index 98104db73a..98f124f0a3 100644
--- a/bsp/raspberry-pico/libraries/pico-sdk/src/rp2_common/pico_runtime/runtime.c
+++ b/bsp/raspberry-pico/libraries/pico-sdk/src/rp2_common/pico_runtime/runtime.c
@@ -27,6 +27,7 @@
 #endif
 
 extern char __StackLimit; /* Set by linker.  */
+extern void _exit(int status);
 
 uint32_t __attribute__((section(".ram_vector_table"))) ram_vector_table[48];
 
@@ -136,57 +137,6 @@ void runtime_init(void) {
 
     spin_locks_reset();
     irq_init_priorities();
-    alarm_pool_init_default();
-
-    // Start and end points of the constructor list,
-    // defined by the linker script.
-    extern void (*__init_array_start)();
-    extern void (*__init_array_end)();
-
-    // Call each function in the list.
-    // We have to take the address of the symbols, as __init_array_start *is*
-    // the first function pointer, not the address of it.
-    for (void (**p)() = &__init_array_start; p < &__init_array_end; ++p) {
-        (*p)();
-    }
-
-}
-
-void _exit(int status) {
-#if PICO_ENTER_USB_BOOT_ON_EXIT
-    reset_usb_boot(0,0);
-#else
-    while (1) {
-        __breakpoint();
-    }
-#endif
-}
-
-void *_sbrk(int incr) {
-    extern char end; /* Set by linker.  */
-    static char *heap_end;
-    char *prev_heap_end;
-
-    if (heap_end == 0)
-        heap_end = &end;
-
-    prev_heap_end = heap_end;
-    char *next_heap_end = heap_end + incr;
-
-    if (__builtin_expect(next_heap_end >= (&__StackLimit), false)) {
-#if PICO_USE_OPTIMISTIC_SBRK
-        if (next_heap_end == &__StackLimit) {
-//        errno = ENOMEM;
-            return (char *) -1;
-        }
-        next_heap_end = &__StackLimit;
-#else
-        return (char *) -1;
-#endif
-    }
-
-    heap_end = next_heap_end;
-    return (void *) prev_heap_end;
 }
 
 // exit is not useful... no desire to pull in __call_exitprocs
diff --git a/bsp/raspberry-pico/link.ld b/bsp/raspberry-pico/link.ld
index 898139432f..ae2889b0fd 100644
--- a/bsp/raspberry-pico/link.ld
+++ b/bsp/raspberry-pico/link.ld
@@ -224,13 +224,6 @@ SECTIONS
         __bss_end__ = .;
     } > RAM
 
-    .heap (COPY):
-    {
-        __end__ = .;
-        end = __end__;
-        *(.heap*)
-        __HeapLimit = .;
-    } > RAM
 
     /* .stack*_dummy section doesn't contains any symbols. It is only
      * used for linker to calculate size of stack sections, and assign
@@ -263,7 +256,7 @@ SECTIONS
     PROVIDE(__stack = __StackTop);
 
     /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed")
+    ASSERT(__StackLimit >= __bss_end__, "region RAM overflowed")
     /* todo assert on extra code */
 }
 
diff --git a/bsp/realview-a8/applications/application.c b/bsp/realview-a8/applications/application.c
index 072cd6d98f..0b8f14b1db 100644
--- a/bsp/realview-a8/applications/application.c
+++ b/bsp/realview-a8/applications/application.c
@@ -1,11 +1,7 @@
 /*
- * File      : application.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -23,7 +19,7 @@ int rt_application_init()
 {
     rt_thread_t tid;
 
-    tid = rt_thread_create("init", init_thread, RT_NULL, 
+    tid = rt_thread_create("init", init_thread, RT_NULL,
         1024, RT_THREAD_PRIORITY_MAX/3, 10);
     if (tid != RT_NULL) rt_thread_startup(tid);
 
diff --git a/bsp/realview-a8/applications/startup.c b/bsp/realview-a8/applications/startup.c
index fa17c0571b..2c37bb4726 100644
--- a/bsp/realview-a8/applications/startup.c
+++ b/bsp/realview-a8/applications/startup.c
@@ -1,11 +1,7 @@
 /*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/realview-a8/drivers/board.c b/bsp/realview-a8/drivers/board.c
index 7a5f80e454..013603b684 100644
--- a/bsp/realview-a8/drivers/board.c
+++ b/bsp/realview-a8/drivers/board.c
@@ -1,11 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/realview-a8/drivers/board.h b/bsp/realview-a8/drivers/board.h
index 89ba3cbe03..f1d30314ba 100644
--- a/bsp/realview-a8/drivers/board.h
+++ b/bsp/realview-a8/drivers/board.h
@@ -1,11 +1,7 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/realview-a8/drivers/serial.c b/bsp/realview-a8/drivers/serial.c
index 7df953a282..75fca59401 100644
--- a/bsp/realview-a8/drivers/serial.c
+++ b/bsp/realview-a8/drivers/serial.c
@@ -1,26 +1,7 @@
 /*
- *  serial.c UART driver
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd
- *
- *  This file is part of RT-Thread (http://www.rt-thread.org)
- *  Maintainer: bernard.xiong 
- *
- *  All rights reserved.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/realview-a8/drivers/serial.h b/bsp/realview-a8/drivers/serial.h
index 52e6f07ea3..dceea68d1f 100644
--- a/bsp/realview-a8/drivers/serial.h
+++ b/bsp/realview-a8/drivers/serial.h
@@ -1,26 +1,7 @@
 /*
- *  UART driver
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd
- *
- *  This file is part of RT-Thread (http://www.rt-thread.org)
- *  Maintainer: bernard.xiong 
- *
- *  All rights reserved.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/realview-a8/rtt_api.h b/bsp/realview-a8/rtt_api.h
index 365e756351..cf8e8ddb1a 100644
--- a/bsp/realview-a8/rtt_api.h
+++ b/bsp/realview-a8/rtt_api.h
@@ -1,25 +1,7 @@
 /*
- *  serial.c UART driver
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * COPYRIGHT (C) 2014, Shanghai Real-Thread Technology Co., Ltd
- *
- *  This file is part of RT-Thread (http://www.rt-thread.org)
- *
- *  All rights reserved.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -149,11 +131,11 @@ struct vmm_domain
 
 struct vmm_iomap
 {
-	const char name[16];        /* iomap name       */
+    const char name[16];        /* iomap name       */
 
-	unsigned long pa;           /* physical address */
-	volatile void __iomem * va; /* virtual address  */
-	size_t size;                /* memory size      */
+    unsigned long pa;           /* physical address */
+    volatile void __iomem * va; /* virtual address  */
+    size_t size;                /* memory size      */
 };
 
 struct vmm_entry_param
diff --git a/bsp/rm48x50/application/startup.c b/bsp/rm48x50/application/startup.c
index 40b69e2c95..a49c9f1810 100644
--- a/bsp/rm48x50/application/startup.c
+++ b/bsp/rm48x50/application/startup.c
@@ -1,11 +1,7 @@
 /*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2013, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -75,21 +71,21 @@ void rtthread_startup(void)
      *rt_hw_cpu_dcache_enable();
      */
 
-	/* init hardware interrupt */
-	rt_hw_interrupt_init();
+    /* init hardware interrupt */
+    rt_hw_interrupt_init();
 
-	/* init board */
-	rt_hw_board_init();
+    /* init board */
+    rt_hw_board_init();
 
-	rt_show_version();
+    rt_show_version();
 
-	/* init timer system */
-	rt_system_timer_init();
+    /* init timer system */
+    rt_system_timer_init();
 
-	/* init memory system */
+    /* init memory system */
 #ifdef RT_USING_HEAP
 #ifdef __CC_ARM
-	rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)MEMEND);
+    rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)MEMEND);
 #elif defined(__GNUC__)
     rt_system_heap_init((void*)&__bss_end, (void*)MEMEND);
 #elif defined(__TI_COMPILER_VERSION__)
@@ -99,40 +95,40 @@ void rtthread_startup(void)
 #endif
 #endif
 
-	/* init scheduler system */
-	rt_system_scheduler_init();
+    /* init scheduler system */
+    rt_system_scheduler_init();
 
-	/* init application */
-	rt_application_init();
+    /* init application */
+    rt_application_init();
 
 #ifdef RT_USING_FINSH
-	/* init finsh */
-	finsh_system_init();
-	finsh_set_device("sci2");
+    /* init finsh */
+    finsh_system_init();
+    finsh_set_device("sci2");
 #endif
 
-	/* init soft timer thread */
-	rt_system_timer_thread_init();
+    /* init soft timer thread */
+    rt_system_timer_thread_init();
 
-	/* init idle thread */
-	rt_thread_idle_init();
+    /* init idle thread */
+    rt_thread_idle_init();
 
-	/* start scheduler */
-	rt_system_scheduler_start();
+    /* start scheduler */
+    rt_system_scheduler_start();
 
-	/* never reach here */
-	return ;
+    /* never reach here */
+    return ;
 }
 
 int main(void)
 {
-	/* disable interrupt first */
-	rt_hw_interrupt_disable();
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
 
-	/* invoke rtthread_startup */
-	rtthread_startup();
+    /* invoke rtthread_startup */
+    rtthread_startup();
 
-	return 0;
+    return 0;
 }
 
 /*@}*/
diff --git a/bsp/rx/ReadMe.txt b/bsp/rx/README.md
similarity index 100%
rename from bsp/rx/ReadMe.txt
rename to bsp/rx/README.md
diff --git a/bsp/rx/applications/application.c b/bsp/rx/applications/application.c
index 4a6e250429..2013a3c69a 100644
--- a/bsp/rx/applications/application.c
+++ b/bsp/rx/applications/application.c
@@ -1,11 +1,7 @@
 /*
- * File      : application.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -14,7 +10,7 @@
  */
 
 /**
- * @addtogroup STM32
+ * @addtogroup
  */
 /*@{*/
 
diff --git a/bsp/rx/applications/startup.c b/bsp/rx/applications/startup.c
index 4b195492f6..92d415c620 100644
--- a/bsp/rx/applications/startup.c
+++ b/bsp/rx/applications/startup.c
@@ -1,11 +1,7 @@
 /*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -90,7 +86,7 @@ int main(void)
 {
 
   rt_hw_system_freq_init();
-   
+
   __enable_interrupt();
     /* disable interrupt first */
     rt_hw_interrupt_disable();
diff --git a/bsp/rx/drivers/Uart.h b/bsp/rx/drivers/Uart.h
index 9354861ca3..cc8aeaf5df 100644
--- a/bsp/rx/drivers/Uart.h
+++ b/bsp/rx/drivers/Uart.h
@@ -1,3 +1,11 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
 
 #ifndef __UART_H__
 #define __UART_H__
diff --git a/bsp/rx/drivers/board.c b/bsp/rx/drivers/board.c
index 4e02325325..aa80014066 100644
--- a/bsp/rx/drivers/board.c
+++ b/bsp/rx/drivers/board.c
@@ -1,3 +1,12 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
 #include 
 #include 
 #include "board.h"
@@ -17,7 +26,7 @@
  *
  */
 #pragma vector = VECT_CMT0_CMI0
-__interrupt 
+__interrupt
 void SysTick_Handler(void)
 {
    // __enable_interrupt();
@@ -56,7 +65,7 @@ void  rt_hw_systick_init(void)
 }
 
 void rt_hw_system_freq_init(void)
-{ 
+{
    /* Declare error flag */
   bool err = true;
 
@@ -69,15 +78,15 @@ void rt_hw_system_freq_init(void)
     24E6,
     PDL_NO_DATA
     );
-  /* 
+  /*
   Clock Description              Frequency
   ----------------------------------------
   Input Clock Frequency..............12MHz
-  Internal Clock Frequency...........96MHz    
+  Internal Clock Frequency...........96MHz
   Peripheral Clock Frequency.........48MHz
   External Bus Clock Frequency.......24MHz */
 
-  /* Halt in while loop when RPDL errors detected */    
+  /* Halt in while loop when RPDL errors detected */
   while (!err);
 }
 
@@ -86,8 +95,8 @@ void rt_hw_system_freq_init(void)
  */
 void rt_hw_board_init()
 {
-    
-    rt_hw_system_freq_init();               
+
+    rt_hw_system_freq_init();
     rt_hw_systick_init();
     rt_hw_uart_init();
 #ifdef RT_USING_CONSOLE
diff --git a/bsp/rx/drivers/board.h b/bsp/rx/drivers/board.h
index 870e805a99..117521d033 100644
--- a/bsp/rx/drivers/board.h
+++ b/bsp/rx/drivers/board.h
@@ -1,11 +1,21 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
+
 #ifndef __BOARD_H__
 #define __BOARD_H__
 
 
-#define		XTAL_FREQUENCY (12000000L)
-#define		ICLK_MUL (8)
-#define		PCLK_MUL (4)
-#define		BCLK_MUL (2)
+#define     XTAL_FREQUENCY (12000000L)
+#define     ICLK_MUL (8)
+#define     PCLK_MUL (4)
+#define     BCLK_MUL (2)
 
 #define RX62N_SRAM_END 0x0000ffff
 
diff --git a/bsp/rx/drivers/uart.c b/bsp/rx/drivers/uart.c
index 9e304ac95c..37d65ba8c0 100644
--- a/bsp/rx/drivers/uart.c
+++ b/bsp/rx/drivers/uart.c
@@ -1,9 +1,11 @@
 /*
-*********************************************************************************************************
-* Filename      : uart.c
-*********************************************************************************************************
-*/
-
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
 
 #include 
 #include 
@@ -22,18 +24,18 @@
 
 
                           /* Clock selection control */
-#define SCI_CKS_MIN		0
-#define SCI_CKS_MAX		3
-#define SCI_CKS_STEP	1
+#define SCI_CKS_MIN     0
+#define SCI_CKS_MAX     3
+#define SCI_CKS_STEP    1
 
 
-#define	IPR_ADDRESS(a) ((volatile unsigned char *)&ICU.IPR[IPR_SCI0_ + a])
+#define IPR_ADDRESS(a) ((volatile unsigned char *)&ICU.IPR[IPR_SCI0_ + a])
 //#define IER_ADDRESS(a) ((volatile unsigned char *)&(ICU.IER[IER_SCI0_ERI0 + a])/sizeof(unsigned char))
-#define	ERI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_ERI0] + ((4 * a) / sizeof(unsigned char)) )
-#define	IER_ADDRESS(a) ((volatile unsigned char *)&ICU.IER[IER_SCI0_ERI0] + ((4 * a) / sizeof(unsigned char)) )
-#define	RXI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_RXI0] + ((4 * a) / sizeof(unsigned char)) )
-#define	TXI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_TXI0] + ((4 * a) / sizeof(unsigned char)) )
-#define	TEI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_TEI0] + ((4 * a) / sizeof(unsigned char)) )
+#define ERI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_ERI0] + ((4 * a) / sizeof(unsigned char)) )
+#define IER_ADDRESS(a) ((volatile unsigned char *)&ICU.IER[IER_SCI0_ERI0] + ((4 * a) / sizeof(unsigned char)) )
+#define RXI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_RXI0] + ((4 * a) / sizeof(unsigned char)) )
+#define TXI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_TXI0] + ((4 * a) / sizeof(unsigned char)) )
+#define TEI_ADDRESS(a) ((volatile unsigned char *)&ICU.IR[IR_SCI0_TEI0] + ((4 * a) / sizeof(unsigned char)) )
 #define  RXI_DTCER_ADDRESS(a) (( volatile unsigned char *)&ICU.DTCER[IR_SCI0_RXI0]+ ((4*a)/sizeof(unsigned char)))
 #define  TXI_DTCER_ADDRESS(a) (( volatile unsigned char *)&ICU.DTCER[IR_SCI0_TXI0]+ ((4*a) / sizeof(unsigned char)))
 //#define SCI1_USE_B
@@ -44,8 +46,8 @@
 #define SourceClk 12000000
 #define rpdl_CGC_f_pclk SourceClk * 4
 /* Idle output options */
-#define SPACE	0
-#define MARK	1
+#define SPACE   0
+#define MARK    1
 
 typedef int UART_ID_Type;
 typedef int IRQn_Type;
@@ -55,14 +57,14 @@ typedef int IRQn_Type;
 struct rx_uart
 {
     UART_ID_Type UART;
-    volatile struct st_sci __sfr * sci;    
+    volatile struct st_sci __sfr * sci;
 };
 
 static rt_err_t rx_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
 {
     #if 1
     struct rx_uart *uart;
-    
+
     unsigned char smr_copy;
     unsigned char semr_copy;
     unsigned char scr_copy;
@@ -81,7 +83,7 @@ static rt_err_t rx_configure(struct rt_serial_device *serial, struct serial_conf
     semr_copy = 0x00u;
     scmr_copy = 0x72u;
     brr_divider = 0;
-    
+
     switch (uart->UART) {
 case 0:
         SYSTEM.MSTPCRB.BIT.MSTPB31 = 0;
@@ -257,11 +259,11 @@ case 0:
     }
 
     /*parity*/
-    if (cfg->parity == PARITY_ODD) 
+    if (cfg->parity == PARITY_ODD)
         smr_copy |= BIT_5;
-        else if (cfg->parity == PARITY_EVEN) 
+        else if (cfg->parity == PARITY_EVEN)
             smr_copy |= BIT_4 | BIT_5;
-    
+
 
 
     brr_divider = rpdl_CGC_f_pclk / cfg->baud_rate;
@@ -304,13 +306,13 @@ case 0:
     }while (bit_interval_counter != 0);
 
     scr_copy = 0x00u;
-	
+
     /*enable rx an tx*/
     scr_copy |= BIT_5  | BIT_4 ;
 
     uart->sci->SCR.BYTE &= 0x5B;
     uart->sci->SCR.BYTE |= scr_copy;
-                             
+
     *(IPR_ADDRESS(uart->UART)) = 5;
     uart->sci->SSR.BYTE = 0xC0;
     uart->sci->SSR.BYTE &= INV_BIT_5;
@@ -363,9 +365,9 @@ case 0:
           break;
   }
 
-  flag |= PDL_SCI_ASYNC | 
-      PDL_SCI_TX_CONNECTED | 
-      PDL_SCI_RX_CONNECTED | 
+  flag |= PDL_SCI_ASYNC |
+      PDL_SCI_TX_CONNECTED |
+      PDL_SCI_RX_CONNECTED |
       PDL_SCI_CLK_INT_IO ;
   /* Configure the RS232 port */
   err &=    R_SCI_Create(
@@ -373,12 +375,12 @@ case 0:
     flag,
     cfg->baud_rate,
     5);
-                  
+
   uart->sci->SCR.BYTE |= BIT_4|BIT_5;
 
  __enable_interrupt();
     #endif
-                          
+
     switch (uart->UART) {
     case 0:
 
@@ -430,7 +432,7 @@ case 0:
 
         break;
     }
-    
+
     return RT_EOK;
 }
 
@@ -464,7 +466,7 @@ static int rx_putc(struct rt_serial_device *serial, char c)
     uart = (struct rx_uart *)serial->parent.user_data;
     while (uart->sci->SSR.BIT.TDRE == 0);
     uart->sci->TDR = c;
-    return 1; 
+    return 1;
 }
 
 static int rx_getc(struct rt_serial_device *serial)
@@ -528,15 +530,15 @@ void rt_hw_uart_init(void)
     config.parity    = PARITY_NONE;
     config.stop_bits = STOP_BITS_1;
     config.invert    = NRZ_NORMAL;
-	config.bufsz     = RT_SERIAL_RB_BUFSZ;
+    config.bufsz     = RT_SERIAL_RB_BUFSZ;
 
     serial2.ops    = &rx_uart_ops;
     serial2.config = config;
 
     /* register UART1 device */
     rt_hw_serial_register(&serial2, "uart2",
-                          RT_DEVICE_FLAG_RDWR | 
-                          RT_DEVICE_FLAG_INT_RX | 
+                          RT_DEVICE_FLAG_RDWR |
+                          RT_DEVICE_FLAG_INT_RX |
                           RT_DEVICE_FLAG_STREAM,
                           uart);
 #endif
diff --git a/bsp/rx/rtconfig.h b/bsp/rx/rtconfig.h
index 6f055dce1a..57524271da 100644
--- a/bsp/rx/rtconfig.h
+++ b/bsp/rx/rtconfig.h
@@ -3,16 +3,16 @@
 #define __RTTHREAD_CFG_H__
 
 /* RT_NAME_MAX*/
-#define RT_NAME_MAX	8
+#define RT_NAME_MAX 8
 
 /* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE	4
+#define RT_ALIGN_SIZE   4
 
 /* PRIORITY_MAX */
-#define RT_THREAD_PRIORITY_MAX	32
+#define RT_THREAD_PRIORITY_MAX  32
 
 /* Tick per Second */
-#define RT_TICK_PER_SECOND	100
+#define RT_TICK_PER_SECOND  100
 
 /* SECTION: RT_DEBUG */
 /* Thread Debug */
@@ -27,9 +27,9 @@
 
 /* Using Software Timer */
 /* #define RT_USING_TIMER_SOFT */
-#define RT_TIMER_THREAD_PRIO		4
-#define RT_TIMER_THREAD_STACK_SIZE	512
-#define RT_TIMER_TICK_PER_SECOND	10
+#define RT_TIMER_THREAD_PRIO        4
+#define RT_TIMER_THREAD_STACK_SIZE  512
+#define RT_TIMER_TICK_PER_SECOND    10
 
 /* SECTION: IPC */
 /* Using Semaphore*/
@@ -72,9 +72,9 @@
 /* SECTION: Console options */
 #define RT_USING_CONSOLE
 /* the buffer size of console*/
-#define RT_CONSOLEBUF_SIZE	        128
+#define RT_CONSOLEBUF_SIZE          128
 // 
-#define RT_CONSOLE_DEVICE_NAME	    "uart2"
+#define RT_CONSOLE_DEVICE_NAME      "uart2"
 
 /* SECTION: finsh, a C-Express shell */
 #define RT_USING_FINSH
@@ -89,17 +89,17 @@
 /* Reentrancy (thread safe) of the FatFs module.  */
 #define RT_DFS_ELM_REENTRANT
 /* Number of volumes (logical drives) to be used. */
-#define RT_DFS_ELM_DRIVES			2
-/* #define RT_DFS_ELM_USE_LFN			1 */
-/* #define RT_DFS_ELM_CODE_PAGE			936 */
-#define RT_DFS_ELM_MAX_LFN			255
+#define RT_DFS_ELM_DRIVES           2
+/* #define RT_DFS_ELM_USE_LFN           1 */
+/* #define RT_DFS_ELM_CODE_PAGE         936 */
+#define RT_DFS_ELM_MAX_LFN          255
 /* Maximum sector size to be handled. */
 #define RT_DFS_ELM_MAX_SECTOR_SIZE  512
 
 /* the max number of mounted filesystem */
-#define DFS_FILESYSTEMS_MAX			2
-/* the max number of opened files 		*/
-#define DFS_FD_MAX					4
+#define DFS_FILESYSTEMS_MAX         2
+/* the max number of opened files       */
+#define DFS_FD_MAX                  4
 
 /* SECTION: lwip, a lighwight TCP/IP protocol stack */
 /* #define RT_USING_LWIP */
@@ -113,49 +113,49 @@
 #define RT_LWIP_DNS
 
 /* the number of simulatenously active TCP connections*/
-#define RT_LWIP_TCP_PCB_NUM	5
+#define RT_LWIP_TCP_PCB_NUM 5
 
 /* Using DHCP */
 /* #define RT_LWIP_DHCP */
 
 /* ip address of target*/
-#define RT_LWIP_IPADDR0	192
-#define RT_LWIP_IPADDR1	168
-#define RT_LWIP_IPADDR2	1
-#define RT_LWIP_IPADDR3	30
+#define RT_LWIP_IPADDR0 192
+#define RT_LWIP_IPADDR1 168
+#define RT_LWIP_IPADDR2 1
+#define RT_LWIP_IPADDR3 30
 
 /* gateway address of target*/
-#define RT_LWIP_GWADDR0	192
-#define RT_LWIP_GWADDR1	168
-#define RT_LWIP_GWADDR2	1
-#define RT_LWIP_GWADDR3	1
+#define RT_LWIP_GWADDR0 192
+#define RT_LWIP_GWADDR1 168
+#define RT_LWIP_GWADDR2 1
+#define RT_LWIP_GWADDR3 1
 
 /* mask address of target*/
-#define RT_LWIP_MSKADDR0	255
-#define RT_LWIP_MSKADDR1	255
-#define RT_LWIP_MSKADDR2	255
-#define RT_LWIP_MSKADDR3	0
+#define RT_LWIP_MSKADDR0    255
+#define RT_LWIP_MSKADDR1    255
+#define RT_LWIP_MSKADDR2    255
+#define RT_LWIP_MSKADDR3    0
 
 /* tcp thread options */
-#define RT_LWIP_TCPTHREAD_PRIORITY		12
-#define RT_LWIP_TCPTHREAD_MBOX_SIZE		10
-#define RT_LWIP_TCPTHREAD_STACKSIZE		1024
+#define RT_LWIP_TCPTHREAD_PRIORITY      12
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE     10
+#define RT_LWIP_TCPTHREAD_STACKSIZE     1024
 
 /* ethernet if thread options */
-#define RT_LWIP_ETHTHREAD_PRIORITY		15
-#define RT_LWIP_ETHTHREAD_MBOX_SIZE		10
-#define RT_LWIP_ETHTHREAD_STACKSIZE		512
+#define RT_LWIP_ETHTHREAD_PRIORITY      15
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE     10
+#define RT_LWIP_ETHTHREAD_STACKSIZE     512
 
 /* TCP sender buffer space */
-#define RT_LWIP_TCP_SND_BUF	8192
+#define RT_LWIP_TCP_SND_BUF 8192
 /* TCP receive window. */
-#define RT_LWIP_TCP_WND		8192
+#define RT_LWIP_TCP_WND     8192
 
 /* SECTION: RT-Thread/GUI */
 /* #define RT_USING_RTGUI */
 
 /* name length of RTGUI object */
-#define RTGUI_NAME_MAX		12
+#define RTGUI_NAME_MAX      12
 /* support 16 weight font */
 #define RTGUI_USING_FONT16
 /* support Chinese font */
@@ -171,7 +171,7 @@
 /* use mouse cursor */
 /* #define RTGUI_USING_MOUSE_CURSOR */
 /* default font size in RTGUI */
-#define RTGUI_DEFAULT_FONT_SIZE	16
+#define RTGUI_DEFAULT_FONT_SIZE 16
 
 /* image support */
 /* #define RTGUI_IMAGE_XPM */
diff --git a/bsp/sam7x/applications/application.c b/bsp/sam7x/applications/application.c
index 2b52802115..6500ddfa10 100644
--- a/bsp/sam7x/applications/application.c
+++ b/bsp/sam7x/applications/application.c
@@ -1,11 +1,7 @@
 /*
- * File      : app.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -44,49 +40,49 @@ void rt_init_thread_entry(void *parameter)
 {
 /* Filesystem Initialization */
 #ifdef RT_USING_DFS
-	{
-		/* init the device filesystem */
-		dfs_init();
-		/* init the efsl filesystam*/
-		efsl_init();
+    {
+        /* init the device filesystem */
+        dfs_init();
+        /* init the efsl filesystam*/
+        efsl_init();
 
-		/* mount sd card fat partition 1 as root directory */
-		if (dfs_mount("sd0", "/", "efs", 0, 0) == 0)
-			rt_kprintf("File System initialized!\n");
-		else
-			rt_kprintf("File System init failed!\n");
-	}
+        /* mount sd card fat partition 1 as root directory */
+        if (dfs_mount("sd0", "/", "efs", 0, 0) == 0)
+            rt_kprintf("File System initialized!\n");
+        else
+            rt_kprintf("File System init failed!\n");
+    }
 #endif
 
 /* LwIP Initialization */
 #ifdef RT_USING_LWIP
-	{
-		extern void lwip_sys_init(void);
+    {
+        extern void lwip_sys_init(void);
 
-		eth_system_device_init();
+        eth_system_device_init();
 
-		/* register AT91 EMAC device */
-		sam7xether_register("E0");
+        /* register AT91 EMAC device */
+        sam7xether_register("E0");
 
-		/* init lwip system */
-		lwip_sys_init();
-		rt_kprintf("TCP/IP initialized!\n");
-	}
+        /* init lwip system */
+        lwip_sys_init();
+        rt_kprintf("TCP/IP initialized!\n");
+    }
 #endif
 }
 
 int rt_application_init()
 {
-	rt_thread_t init_thread;
+    rt_thread_t init_thread;
 
-	init_thread = rt_thread_create("init",
-								rt_init_thread_entry, RT_NULL,
-								1024, 8, 5);
-	rt_thread_startup(init_thread);
+    init_thread = rt_thread_create("init",
+                                rt_init_thread_entry, RT_NULL,
+                                1024, 8, 5);
+    rt_thread_startup(init_thread);
 
-	rt_kprintf("enter list() to get function list!\n");
+    rt_kprintf("enter list() to get function list!\n");
 
-	return 0;
+    return 0;
 }
 
 /*@}*/
diff --git a/bsp/sam7x/applications/startup.c b/bsp/sam7x/applications/startup.c
index d167d9ebcb..528d6127f3 100644
--- a/bsp/sam7x/applications/startup.c
+++ b/bsp/sam7x/applications/startup.c
@@ -1,11 +1,7 @@
 /*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -56,17 +52,17 @@ extern int finsh_system_init(void);
 
 void led_flash()
 {
-	int i;
-	static int j = 0;
+    int i;
+    static int j = 0;
 
-	rt_hw_board_led_off(j);
-	for (i = 0; i < 2000000; i ++);
+    rt_hw_board_led_off(j);
+    for (i = 0; i < 2000000; i ++);
 
-	j ++;
-	if (j >= 4) j = 0;
+    j ++;
+    if (j >= 4) j = 0;
 
-	rt_hw_board_led_on(j);
-	for (i = 0; i < 2000000; i ++);
+    rt_hw_board_led_on(j);
+    for (i = 0; i < 2000000; i ++);
 }
 
 /**
@@ -74,70 +70,70 @@ void led_flash()
  */
 void rtthread_startup(void)
 {
-	/* init hardware interrupt */
-	rt_hw_interrupt_init();
+    /* init hardware interrupt */
+    rt_hw_interrupt_init();
 
-	/* init board */
-	rt_hw_board_init();
+    /* init board */
+    rt_hw_board_init();
 
-	rt_show_version();
+    rt_show_version();
 
-	/* init timer system */
-	rt_system_timer_init();
+    /* init timer system */
+    rt_system_timer_init();
 
 #ifdef RT_USING_HEAP
 #ifdef __CC_ARM
-	rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x00210000);
+    rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x00210000);
 #elif __ICCARM__
     rt_system_heap_init(__segment_end("HEAP"), (void*)0x00210000);
 #else
-	rt_system_heap_init(&__bss_end, (void*)0x00210000);
+    rt_system_heap_init(&__bss_end, (void*)0x00210000);
 #endif
 #endif
 
-	/* init scheduler system */
-	rt_system_scheduler_init();
+    /* init scheduler system */
+    rt_system_scheduler_init();
 
 #ifdef RT_USING_HOOK /* if the hook is used */
-	/* set idle thread hook */
-	rt_thread_idle_sethook(led_flash);
+    /* set idle thread hook */
+    rt_thread_idle_sethook(led_flash);
 #endif
 
 #ifdef RT_USING_DEVICE
-	/* init hardware serial device */
-	rt_hw_serial_init();
+    /* init hardware serial device */
+    rt_hw_serial_init();
 
 #ifdef RT_USING_DFS
-	rt_hw_sdcard_init();
+    rt_hw_sdcard_init();
 #endif
 #endif
 
-	/* init application */
-	rt_application_init();
+    /* init application */
+    rt_application_init();
 
 #ifdef RT_USING_FINSH
-	/* init finsh */
-	finsh_system_init();
-	finsh_set_device("uart1");
+    /* init finsh */
+    finsh_system_init();
+    finsh_set_device("uart1");
 #endif
 
-	/* init idle thread */
-	rt_thread_idle_init();
+    /* init idle thread */
+    rt_thread_idle_init();
 
-	/* start scheduler */
-	rt_system_scheduler_start();
+    /* start scheduler */
+    rt_system_scheduler_start();
 
-	/* never reach here */
-	return ;
+    /* never reach here */
+    return ;
 }
 
 #ifdef __CC_ARM
 int main (void)
 {
-	/* invoke rtthread_startup */
-	rtthread_startup();
+    /* invoke rtthread_startup */
+    rtthread_startup();
 
-	return 0;
+    return 0;
 }
 #endif
 
diff --git a/bsp/sam7x/rtconfig.h b/bsp/sam7x/rtconfig.h
index bb3e3546d0..ae74c2535e 100644
--- a/bsp/sam7x/rtconfig.h
+++ b/bsp/sam7x/rtconfig.h
@@ -72,10 +72,6 @@
 #define FINSH_USING_SYMTAB
 #define FINSH_USING_DESCRIPTION
 
-/* SECTION: a mini libc */
-/* Using mini libc library*/
-/* #define RT_USING_MINILIBC */
-
 /* SECTION: C++ support */
 /* Using C++ support*/
 /* #define RT_USING_CPLUSPLUS */
diff --git a/bsp/sep6200/application/application.c b/bsp/sep6200/application/application.c
index cbc4cd4d47..5a032933b4 100644
--- a/bsp/sep6200/application/application.c
+++ b/bsp/sep6200/application/application.c
@@ -1,24 +1,10 @@
 /*
- * File      : application.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
+ * Date           Author        Notes
  * 2013-7-14      Peng Fan  Simple application
  */
 
@@ -59,31 +45,31 @@ void rt_test2_thread_entry(void *parameter)
 
 int rt_application_init(void)
 {
-	rt_thread_t init_thread;
-	rt_thread_t test1_thread;
-	rt_thread_t test2_thread;
+    rt_thread_t init_thread;
+    rt_thread_t test1_thread;
+    rt_thread_t test2_thread;
 
-	init_thread = rt_thread_create("init",
-								rt_init_thread_entry, RT_NULL,
-								RT_INIT_THREAD_STACK_SIZE, 8, 20);
+    init_thread = rt_thread_create("init",
+                                rt_init_thread_entry, RT_NULL,
+                                RT_INIT_THREAD_STACK_SIZE, 8, 20);
 
-	test1_thread = rt_thread_create("test1",
-								rt_test1_thread_entry, RT_NULL,
-								512, 200, 20);
-	test2_thread = rt_thread_create("test2",
-								rt_test2_thread_entry, RT_NULL,
-								512, 200, 20);
+    test1_thread = rt_thread_create("test1",
+                                rt_test1_thread_entry, RT_NULL,
+                                512, 200, 20);
+    test2_thread = rt_thread_create("test2",
+                                rt_test2_thread_entry, RT_NULL,
+                                512, 200, 20);
 
-	if (init_thread != RT_NULL)
-		rt_thread_startup(init_thread);
+    if (init_thread != RT_NULL)
+        rt_thread_startup(init_thread);
 
-	if (test1_thread != RT_NULL)
-		rt_thread_startup(test1_thread);
+    if (test1_thread != RT_NULL)
+        rt_thread_startup(test1_thread);
 
-	if (test2_thread != RT_NULL)
-		rt_thread_startup(test2_thread);
+    if (test2_thread != RT_NULL)
+        rt_thread_startup(test2_thread);
 
-	return 0;
+    return 0;
 }
 
 /*@}*/
diff --git a/bsp/sep6200/application/startup.c b/bsp/sep6200/application/startup.c
index 78b9c30c5f..0d67f08256 100644
--- a/bsp/sep6200/application/startup.c
+++ b/bsp/sep6200/application/startup.c
@@ -1,21 +1,7 @@
 /*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -54,44 +40,44 @@ extern void sd_init(void);
 
 void rtthread_startup()
 {
-	/* init hardware interrupt */
-	rt_hw_interrupt_init();
+    /* init hardware interrupt */
+    rt_hw_interrupt_init();
 
-	/* init board */
-	rt_hw_board_init();
+    /* init board */
+    rt_hw_board_init();
 
-	/* show version */
-	rt_show_version();
+    /* show version */
+    rt_show_version();
 
-	/* init timer system */
-	rt_system_timer_init();
+    /* init timer system */
+    rt_system_timer_init();
 
-	/* init heap memory system */
-	rt_system_heap_init(&__bss_end, (void*)0x45000000);
+    /* init heap memory system */
+    rt_system_heap_init(&__bss_end, (void*)0x45000000);
 
-	/* init scheduler system */
-	rt_system_scheduler_init();
+    /* init scheduler system */
+    rt_system_scheduler_init();
 
-	/* init application */
-	rt_application_init();
+    /* init application */
+    rt_application_init();
 
 #ifdef RT_USING_FINSH
-	/* init finsh */
-	finsh_system_init();
+    /* init finsh */
+    finsh_system_init();
 #ifdef RT_USING_DEVICE
-	finsh_set_device("uart0");
+    finsh_set_device("uart0");
 #endif
 #endif
 
   rt_system_timer_thread_init();
 
-	/* init idle thread */
-	rt_thread_idle_init();
+    /* init idle thread */
+    rt_thread_idle_init();
 
-	/* start scheduler */
-	rt_system_scheduler_start();
+    /* start scheduler */
+    rt_system_scheduler_start();
 
-	/* never reach here */
-	return ;
+    /* never reach here */
+    return ;
 
 }
diff --git a/bsp/sep6200/board.h b/bsp/sep6200/board.h
index 91b745b516..51079875dc 100644
--- a/bsp/sep6200/board.h
+++ b/bsp/sep6200/board.h
@@ -1,21 +1,7 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/sep6200/drivers/board.c b/bsp/sep6200/drivers/board.c
index bc8756c9a1..3a1ade2752 100644
--- a/bsp/sep6200/drivers/board.c
+++ b/bsp/sep6200/drivers/board.c
@@ -1,21 +1,7 @@
 /*
- * File		: board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -36,14 +22,14 @@
 
 void rt_hw_serial_putc(const char c);
 
-#define UART0	((struct uartport *)SEP6200_UART0_BASE)
+#define UART0   ((struct uartport *)SEP6200_UART0_BASE)
 
 struct rt_device uart0_device;
 struct serial_int_rx uart0_int_rx;
 struct serial_device uart0 =
 {
-	UART0,
-	&uart0_int_rx,
+    UART0,
+    &uart0_int_rx,
   RT_NULL
 };
 
@@ -52,13 +38,13 @@ struct serial_device uart0 =
  */
 void rt_timer_handler(int vector, void *param)
 {
-	rt_uint32_t clear_int;
+    rt_uint32_t clear_int;
 
-	/* clear timer interrupt */
-	if (read_reg(SEP6200_TIMER_T2IMSR) & 0x1)
-		clear_int = read_reg(SEP6200_TIMER_T2ISCR);
+    /* clear timer interrupt */
+    if (read_reg(SEP6200_TIMER_T2IMSR) & 0x1)
+        clear_int = read_reg(SEP6200_TIMER_T2ISCR);
 
-	rt_tick_increase();
+    rt_tick_increase();
 }
 
 /*
@@ -66,47 +52,47 @@ void rt_timer_handler(int vector, void *param)
  */
 void rt_serial_handler(int vector, void *param)
 {
-	rt_uint32_t num;
-	switch (vector) {
-		case INTSRC_UART0:
+    rt_uint32_t num;
+    switch (vector) {
+        case INTSRC_UART0:
 
       /*No interrupt*/
-			if ((*(RP)SEP6200_UART0_IIR & 0x1))
-				return;
+            if ((*(RP)SEP6200_UART0_IIR & 0x1))
+                return;
 
       /*Get the serial interrupt num*/
-			num = (*(RP)SEP6200_UART0_IIR >> 1) & 0x7;
+            num = (*(RP)SEP6200_UART0_IIR >> 1) & 0x7;
 
       /*Receive or timeout*/
       if ((num == 6) || (num == 2))
-			  rt_hw_serial_isr(&uart0_device);
-			break;
-		/*1,2,3 not implemented now, do in future*/
-		case INTSRC_UART1:
-			break;
-		case INTSRC_UART2:
-			break;
-		case INTSRC_UART3:
-			break;
-	}
+              rt_hw_serial_isr(&uart0_device);
+            break;
+        /*1,2,3 not implemented now, do in future*/
+        case INTSRC_UART1:
+            break;
+        case INTSRC_UART2:
+            break;
+        case INTSRC_UART3:
+            break;
+    }
 }
 
 /*
  * This function will init timer2 for system ticks
  */
-#define BUS4_FREQ	320000000UL
-#define TIMER_CLK	BUS4_FREQ
+#define BUS4_FREQ   320000000UL
+#define TIMER_CLK   BUS4_FREQ
 #define HZ 100
 void rt_hw_timer_init(void)
 {
-	*(RP)SEP6200_TIMER_T2LCR = (TIMER_CLK + HZ / 2) / HZ;
-	*(RP)SEP6200_TIMER_T2CR	 = 0x6;
+    *(RP)SEP6200_TIMER_T2LCR = (TIMER_CLK + HZ / 2) / HZ;
+    *(RP)SEP6200_TIMER_T2CR  = 0x6;
 
-	rt_hw_interrupt_install(INTSRC_TIMER1, rt_timer_handler, RT_NULL, "timer");
-	rt_hw_interrupt_umask(INTSRC_TIMER1);
+    rt_hw_interrupt_install(INTSRC_TIMER1, rt_timer_handler, RT_NULL, "timer");
+    rt_hw_interrupt_umask(INTSRC_TIMER1);
 
-	/* start the timer */
-	*(RP)SEP6200_TIMER_T2CR |= 0x1;
+    /* start the timer */
+    *(RP)SEP6200_TIMER_T2CR |= 0x1;
 }
 
 /*
@@ -115,35 +101,35 @@ void rt_hw_timer_init(void)
 #define UART_CLK 60000000UL
 void rt_hw_uart_init(void)
 {
-	const rt_uint32_t uartclk = UART_CLK;
+    const rt_uint32_t uartclk = UART_CLK;
 
-	*(RP)(SEP6200_UART0_LCR) = 0x83;
-	*(RP)(SEP6200_UART0_DLBH) = (uartclk/16/115200) >> 8;
-	*(RP)(SEP6200_UART0_DLBL) = (uartclk/16/115200) & 0xff;
-	*(RP)(SEP6200_UART0_LCR) = 0x83 & (~(0x1 << 7));
+    *(RP)(SEP6200_UART0_LCR) = 0x83;
+    *(RP)(SEP6200_UART0_DLBH) = (uartclk/16/115200) >> 8;
+    *(RP)(SEP6200_UART0_DLBL) = (uartclk/16/115200) & 0xff;
+    *(RP)(SEP6200_UART0_LCR) = 0x83 & (~(0x1 << 7));
 
-	*(RP)(SEP6200_UART0_FCR) = 0x0;
-	*(RP)(SEP6200_UART0_MCR) = 0x0;
+    *(RP)(SEP6200_UART0_FCR) = 0x0;
+    *(RP)(SEP6200_UART0_MCR) = 0x0;
 
-	*(RP)(SEP6200_UART0_IER) = 0x0;
-	/* Enable rx interrupt*/
-	*(RP)(SEP6200_UART0_IER) |= 0x1;
-	/* Disable tx interrupt*/
-	*(RP)(SEP6200_UART0_IER) &= ~(0x1 << 1);
+    *(RP)(SEP6200_UART0_IER) = 0x0;
+    /* Enable rx interrupt*/
+    *(RP)(SEP6200_UART0_IER) |= 0x1;
+    /* Disable tx interrupt*/
+    *(RP)(SEP6200_UART0_IER) &= ~(0x1 << 1);
 
-	rt_hw_interrupt_install(INTSRC_UART0, rt_serial_handler, RT_NULL, "uart0");
-	rt_hw_interrupt_umask(INTSRC_UART0);
+    rt_hw_interrupt_install(INTSRC_UART0, rt_serial_handler, RT_NULL, "uart0");
+    rt_hw_interrupt_umask(INTSRC_UART0);
 
-	rt_hw_serial_register(&uart0_device, "uart0",
-			RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
-			&uart0);
+    rt_hw_serial_register(&uart0_device, "uart0",
+            RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+            &uart0);
 }
 
 void rt_hw_board_init(void)
 {
   int i = 0;
-	rt_hw_uart_init();
-	rt_hw_timer_init();
+    rt_hw_uart_init();
+    rt_hw_timer_init();
 }
 
 /*
@@ -151,12 +137,12 @@ void rt_hw_board_init(void)
  */
 void rt_hw_serial_putc(const char c)
 {
-	if (c == '\n')
-		rt_hw_serial_putc('\r');
+    if (c == '\n')
+        rt_hw_serial_putc('\r');
 
-	while (!((*(RP)SEP6200_UART0_LSR) & 0x40));
+    while (!((*(RP)SEP6200_UART0_LSR) & 0x40));
 
-	*(RP)(SEP6200_UART0_TXFIFO) = c;
+    *(RP)(SEP6200_UART0_TXFIFO) = c;
 }
 
 /**
diff --git a/bsp/simulator/.config b/bsp/simulator/.config
index 8a449bc6fd..c7e94f08ad 100644
--- a/bsp/simulator/.config
+++ b/bsp/simulator/.config
@@ -52,6 +52,7 @@ CONFIG_RT_USING_MEMPOOL=y
 # CONFIG_RT_USING_NOHEAP is not set
 CONFIG_RT_USING_SMALL_MEM=y
 # CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_USERHEAP is not set
 # CONFIG_RT_USING_MEMTRACE is not set
 CONFIG_RT_USING_HEAP=y
 
@@ -64,14 +65,17 @@ CONFIG_RT_USING_DEVICE=y
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="console"
-CONFIG_RT_VER_NUM=0x40002
+CONFIG_RT_VER_NUM=0x40003
 # CONFIG_RT_USING_CPU_FFS is not set
 # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
 
 #
 # RT-Thread Components
 #
-# CONFIG_RT_USING_COMPONENTS_INIT is not set
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
 
 #
 # C++ features
@@ -118,6 +122,11 @@ CONFIG_RT_DFS_ELM_USE_LFN_0=y
 # CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
 # CONFIG_RT_DFS_ELM_USE_LFN_3 is not set
 CONFIG_RT_DFS_ELM_USE_LFN=0
+CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
+# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
+CONFIG_RT_DFS_ELM_LFN_UNICODE=0
 CONFIG_RT_DFS_ELM_MAX_LFN=255
 CONFIG_RT_DFS_ELM_DRIVES=2
 CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
@@ -126,8 +135,6 @@ CONFIG_RT_DFS_ELM_REENTRANT=y
 CONFIG_RT_USING_DFS_DEVFS=y
 # CONFIG_RT_USING_DFS_ROMFS is not set
 # CONFIG_RT_USING_DFS_RAMFS is not set
-# CONFIG_RT_USING_DFS_UFFS is not set
-# CONFIG_RT_USING_DFS_JFFS2 is not set
 
 #
 # Device Drivers
@@ -142,8 +149,10 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_HWTIMER is not set
 # CONFIG_RT_USING_CPUTIME is not set
 # CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
 # CONFIG_RT_USING_PIN is not set
 # CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
 # CONFIG_RT_USING_PWM is not set
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
@@ -156,6 +165,8 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_SENSOR is not set
 # CONFIG_RT_USING_TOUCH is not set
 # CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
 # CONFIG_RT_USING_WIFI is not set
 
 #
@@ -169,6 +180,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 #
 # CONFIG_RT_USING_LIBC is not set
 # CONFIG_RT_USING_PTHREADS is not set
+CONFIG_RT_LIBC_USING_TIME=y
 
 #
 # Network
@@ -213,10 +225,15 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 #
 # IoT - internet of things
 #
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
 # CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
 # CONFIG_PKG_USING_WEBCLIENT is not set
 # CONFIG_PKG_USING_WEBNET is not set
 # CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
 # CONFIG_PKG_USING_WEBTERMINAL is not set
 # CONFIG_PKG_USING_CJSON is not set
 # CONFIG_PKG_USING_JSMN is not set
@@ -243,6 +260,8 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_PKG_USING_COAP is not set
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
 # CONFIG_PKG_USING_AT_DEVICE is not set
 # CONFIG_PKG_USING_ATSRV_SOCKET is not set
 # CONFIG_PKG_USING_WIZNET is not set
@@ -254,7 +273,10 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_PKG_USING_GAGENT_CLOUD is not set
 # CONFIG_PKG_USING_ALI_IOTKIT is not set
 # CONFIG_PKG_USING_AZURE is not set
-# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
 # CONFIG_PKG_USING_NIMBLE is not set
 # CONFIG_PKG_USING_OTA_DOWNLOADER is not set
 # CONFIG_PKG_USING_IPMSG is not set
@@ -262,6 +284,25 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_PKG_USING_AIRKISS_OPEN is not set
 # CONFIG_PKG_USING_LIBRWS is not set
 # CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
 
 #
 # security packages
@@ -269,6 +310,8 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_PKG_USING_MBEDTLS is not set
 # CONFIG_PKG_USING_libsodium is not set
 # CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
 
 #
 # language packages
@@ -283,6 +326,11 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_PKG_USING_OPENMV is not set
 # CONFIG_PKG_USING_MUPDF is not set
 # CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
 
 #
 # tools packages
@@ -294,7 +342,31 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_PKG_USING_RDB is not set
 # CONFIG_PKG_USING_QRCODE is not set
 # CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
+# CONFIG_PKG_USING_LOGMGR is not set
 # CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
 
 #
 # system packages
@@ -305,13 +377,43 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_PKG_USING_LWEXT4 is not set
 # CONFIG_PKG_USING_PARTITION is not set
 # CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_FLASHDB is not set
 # CONFIG_PKG_USING_SQLITE is not set
 # CONFIG_PKG_USING_RTI is not set
 # CONFIG_PKG_USING_LITTLEVGL2RTT is not set
 # CONFIG_PKG_USING_CMSIS is not set
 # CONFIG_PKG_USING_DFS_YAFFS is not set
 # CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
 # CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
 
 #
 # peripheral libraries and drivers
@@ -319,6 +421,8 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_PKG_USING_SENSORS_DRIVERS is not set
 # CONFIG_PKG_USING_REALTEK_AMEBA is not set
 # CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AS7341 is not set
 # CONFIG_PKG_USING_STM32_SDIO is not set
 # CONFIG_PKG_USING_ICM20608 is not set
 # CONFIG_PKG_USING_U8G2 is not set
@@ -327,10 +431,16 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_PKG_USING_SX12XX is not set
 # CONFIG_PKG_USING_SIGNAL_LED is not set
 # CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
 # CONFIG_PKG_USING_WM_LIBRARIES is not set
 # CONFIG_PKG_USING_KENDRYTE_SDK is not set
 # CONFIG_PKG_USING_INFRARED is not set
 # CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
 # CONFIG_PKG_USING_AT24CXX is not set
 # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
 # CONFIG_PKG_USING_AD7746 is not set
@@ -338,7 +448,51 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_PKG_USING_I2C_TOOLS is not set
 # CONFIG_PKG_USING_NRF24L01 is not set
 # CONFIG_PKG_USING_TOUCH_DRIVERS is not set
-# CONFIG_PKG_USING_LCD_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
 
 #
 # miscellaneous packages
@@ -348,13 +502,17 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_PKG_USING_FASTLZ is not set
 # CONFIG_PKG_USING_MINILZO is not set
 # CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
 # CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
 # CONFIG_PKG_USING_CANFESTIVAL is not set
 # CONFIG_PKG_USING_ZLIB is not set
 # CONFIG_PKG_USING_DSTR is not set
 # CONFIG_PKG_USING_TINYFRAME is not set
 # CONFIG_PKG_USING_KENDRYTE_DEMO is not set
 # CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
 
 #
 # samples: kernel and components samples
@@ -365,6 +523,24 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
 # CONFIG_PKG_USING_HELLO is not set
 # CONFIG_PKG_USING_VI is not set
-# CONFIG_PKG_USING_NNOM is not set
-# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_COWSAY is not set
+CONFIG_SOC_SIMULATOR=y
 CONFIG_RT_USING_DFS_WINSHAREDIR=y
diff --git a/bsp/simulator/Kconfig b/bsp/simulator/Kconfig
index 1832033b4e..c5e4618d76 100644
--- a/bsp/simulator/Kconfig
+++ b/bsp/simulator/Kconfig
@@ -18,8 +18,16 @@ config PKGS_DIR
 source "$RTT_DIR/Kconfig"
 source "$PKGS_DIR/Kconfig"
 
+config SOC_SIMULATOR
+    bool 
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
 if RT_USING_DFS
     config RT_USING_DFS_WINSHAREDIR
     bool "Enable shared file system between windows"
     default n
 endif
+
+
diff --git a/bsp/simulator/SConstruct b/bsp/simulator/SConstruct
index b9854bb343..e165ce6fef 100755
--- a/bsp/simulator/SConstruct
+++ b/bsp/simulator/SConstruct
@@ -86,6 +86,19 @@ def ObjRemove(objs, remove):
              objs.remove(item)
     return
 
+def ProjectRemove(group, remove):
+    global Projects
+    for item in Projects:
+        if item['name'] == group:
+            for src in item['src']:
+                if os.path.basename(str(src)) in remove:
+                    # print(type(src), os.path.basename(str(src)) )
+                    item['src'].remove(src)
+    return
+
+ObjRemove(objs, ['components.obj', 'components.o', 'components.c'])
+ProjectRemove('Kernel', ['components.obj', 'components.o', 'components.c'])
+
 # build program  -shared
 if GetDepend('RT_USING_MODULE'):
     # Remove module.c in $RTT_ROOT/src
diff --git a/bsp/simulator/SDL2-2.0.7/include/SDL_config.h b/bsp/simulator/SDL2-2.0.7/include/SDL_config.h
index 1bbb838481..24c81ec14b 100644
--- a/bsp/simulator/SDL2-2.0.7/include/SDL_config.h
+++ b/bsp/simulator/SDL2-2.0.7/include/SDL_config.h
@@ -194,7 +194,7 @@ typedef unsigned int uintptr_t;
 #define SDL_VIDEO_RENDER_D3D    1
 #endif
 #ifndef SDL_VIDEO_RENDER_D3D11
-#define SDL_VIDEO_RENDER_D3D11	0
+#define SDL_VIDEO_RENDER_D3D11  0
 #endif
 
 /* Enable OpenGL support */
diff --git a/bsp/simulator/SDL2-2.0.7/include/SDL_config_android.h b/bsp/simulator/SDL2-2.0.7/include/SDL_config_android.h
index 361bad8b77..27cfd9540c 100644
--- a/bsp/simulator/SDL2-2.0.7/include/SDL_config_android.h
+++ b/bsp/simulator/SDL2-2.0.7/include/SDL_config_android.h
@@ -108,7 +108,7 @@
 #define HAVE_SETJMP 1
 #define HAVE_NANOSLEEP  1
 #define HAVE_SYSCONF    1
-#define HAVE_CLOCK_GETTIME	1
+#define HAVE_CLOCK_GETTIME  1
 
 #define SIZEOF_VOIDP 4
 
diff --git a/bsp/simulator/SDL2-2.0.7/include/SDL_config_windows.h b/bsp/simulator/SDL2-2.0.7/include/SDL_config_windows.h
index 2456c843fe..2a5724a4c9 100644
--- a/bsp/simulator/SDL2-2.0.7/include/SDL_config_windows.h
+++ b/bsp/simulator/SDL2-2.0.7/include/SDL_config_windows.h
@@ -185,7 +185,7 @@ typedef unsigned int uintptr_t;
 #define SDL_VIDEO_RENDER_D3D    1
 #endif
 #ifndef SDL_VIDEO_RENDER_D3D11
-#define SDL_VIDEO_RENDER_D3D11	0
+#define SDL_VIDEO_RENDER_D3D11  0
 #endif
 
 /* Enable OpenGL support */
diff --git a/bsp/simulator/SDL2-2.0.7/include/SDL_config_winrt.h b/bsp/simulator/SDL2-2.0.7/include/SDL_config_winrt.h
index 24f9e17f20..621c8116b6 100644
--- a/bsp/simulator/SDL2-2.0.7/include/SDL_config_winrt.h
+++ b/bsp/simulator/SDL2-2.0.7/include/SDL_config_winrt.h
@@ -44,7 +44,7 @@
 
 #if !defined(_STDINT_H_) && (!defined(HAVE_STDINT_H) || !_HAVE_STDINT_H)
 #if defined(__GNUC__) || defined(__DMC__) || defined(__WATCOMC__)
-#define HAVE_STDINT_H	1
+#define HAVE_STDINT_H   1
 #elif defined(_MSC_VER)
 typedef signed __int8 int8_t;
 typedef unsigned __int8 uint8_t;
@@ -121,13 +121,13 @@ typedef unsigned int uintptr_t;
 #define HAVE_STRLEN 1
 #define HAVE__STRREV 1
 #define HAVE__STRUPR 1
-//#define HAVE__STRLWR 1	// TODO, WinRT: consider using _strlwr_s instead
+//#define HAVE__STRLWR 1    // TODO, WinRT: consider using _strlwr_s instead
 #define HAVE_STRCHR 1
 #define HAVE_STRRCHR 1
 #define HAVE_STRSTR 1
 //#define HAVE_ITOA 1   // TODO, WinRT: consider using _itoa_s instead
-//#define HAVE__LTOA 1	// TODO, WinRT: consider using _ltoa_s instead
-//#define HAVE__ULTOA 1	// TODO, WinRT: consider using _ultoa_s instead
+//#define HAVE__LTOA 1  // TODO, WinRT: consider using _ltoa_s instead
+//#define HAVE__ULTOA 1 // TODO, WinRT: consider using _ultoa_s instead
 #define HAVE_STRTOL 1
 #define HAVE_STRTOUL 1
 //#define HAVE_STRTOLL 1
@@ -139,7 +139,7 @@ typedef unsigned int uintptr_t;
 #define HAVE__STRICMP 1
 #define HAVE__STRNICMP 1
 #define HAVE_VSNPRINTF 1
-//#define HAVE_SSCANF 1	// TODO, WinRT: consider using sscanf_s instead
+//#define HAVE_SSCANF 1 // TODO, WinRT: consider using sscanf_s instead
 #define HAVE_M_PI 1
 #define HAVE_ATAN 1
 #define HAVE_ATAN2 1
@@ -162,21 +162,21 @@ typedef unsigned int uintptr_t;
 #define HAVE__FSEEKI64 1
 
 /* Enable various audio drivers */
-#define SDL_AUDIO_DRIVER_XAUDIO2	1
-#define SDL_AUDIO_DRIVER_DISK	1
-#define SDL_AUDIO_DRIVER_DUMMY	1
+#define SDL_AUDIO_DRIVER_XAUDIO2    1
+#define SDL_AUDIO_DRIVER_DISK   1
+#define SDL_AUDIO_DRIVER_DUMMY  1
 
 /* Enable various input drivers */
 #if WINAPI_FAMILY == WINAPI_FAMILY_PHONE_APP
 #define SDL_JOYSTICK_DISABLED 1
-#define SDL_HAPTIC_DISABLED	1
+#define SDL_HAPTIC_DISABLED 1
 #else
 #define SDL_JOYSTICK_XINPUT 1
 #define SDL_HAPTIC_XINPUT   1
 #endif
 
 /* Enable various shared object loading systems */
-#define SDL_LOADSO_WINDOWS	1
+#define SDL_LOADSO_WINDOWS  1
 
 /* Enable various threading systems */
 #if (NTDDI_VERSION >= NTDDI_WINBLUE)
@@ -187,10 +187,10 @@ typedef unsigned int uintptr_t;
 #endif
 
 /* Enable various timer systems */
-#define SDL_TIMER_WINDOWS	1
+#define SDL_TIMER_WINDOWS   1
 
 /* Enable various video drivers */
-#define SDL_VIDEO_DRIVER_WINRT	1
+#define SDL_VIDEO_DRIVER_WINRT  1
 #define SDL_VIDEO_DRIVER_DUMMY  1
 
 /* Enable OpenGL ES 2.0 (via a modified ANGLE library) */
@@ -209,7 +209,7 @@ typedef unsigned int uintptr_t;
 
 /* Enable assembly routines (Win64 doesn't have inline asm) */
 #ifndef _WIN64
-#define SDL_ASSEMBLY_ROUTINES	1
+#define SDL_ASSEMBLY_ROUTINES   1
 #endif
 
 #endif /* SDL_config_winrt_h_ */
diff --git a/bsp/simulator/SDL2-2.0.7/include/SDL_gamecontroller.h b/bsp/simulator/SDL2-2.0.7/include/SDL_gamecontroller.h
index c9215132ef..406e77e91e 100644
--- a/bsp/simulator/SDL2-2.0.7/include/SDL_gamecontroller.h
+++ b/bsp/simulator/SDL2-2.0.7/include/SDL_gamecontroller.h
@@ -116,7 +116,7 @@ typedef struct SDL_GameControllerButtonBind
  *  A community sourced database of controllers is available at https://raw.github.com/gabomdq/SDL_GameControllerDB/master/gamecontrollerdb.txt
  *
  *  If \c freerw is non-zero, the stream will be closed after being read.
- * 
+ *
  * \return number of mappings added, -1 on error
  */
 extern DECLSPEC int SDLCALL SDL_GameControllerAddMappingsFromRW(SDL_RWops * rw, int freerw);
diff --git a/bsp/simulator/SDL2-2.0.7/include/SDL_hints.h b/bsp/simulator/SDL2-2.0.7/include/SDL_hints.h
index 007a4bee05..7d43814b6b 100644
--- a/bsp/simulator/SDL2-2.0.7/include/SDL_hints.h
+++ b/bsp/simulator/SDL2-2.0.7/include/SDL_hints.h
@@ -153,7 +153,7 @@ extern "C" {
 #define SDL_HINT_RENDER_VSYNC               "SDL_RENDER_VSYNC"
 
 /**
- *  \brief  A variable controlling whether the screensaver is enabled. 
+ *  \brief  A variable controlling whether the screensaver is enabled.
  *
  *  This variable can be set to the following values:
  *    "0"       - Disable screensaver
@@ -211,7 +211,7 @@ extern "C" {
 #define SDL_HINT_VIDEO_X11_NET_WM_PING      "SDL_VIDEO_X11_NET_WM_PING"
 
 /**
- *  \brief  A variable controlling whether the window frame and title bar are interactive when the cursor is hidden 
+ *  \brief  A variable controlling whether the window frame and title bar are interactive when the cursor is hidden
  *
  *  This variable can be set to the following values:
  *    "0"       - The window frame is not interactive when the cursor is hidden (no move, resize, etc)
@@ -222,13 +222,13 @@ extern "C" {
 #define SDL_HINT_WINDOW_FRAME_USABLE_WHILE_CURSOR_HIDDEN    "SDL_WINDOW_FRAME_USABLE_WHILE_CURSOR_HIDDEN"
 
 /**
- * \brief A variable to specify custom icon resource id from RC file on Windows platform 
+ * \brief A variable to specify custom icon resource id from RC file on Windows platform
  */
 #define SDL_HINT_WINDOWS_INTRESOURCE_ICON       "SDL_WINDOWS_INTRESOURCE_ICON"
 #define SDL_HINT_WINDOWS_INTRESOURCE_ICON_SMALL "SDL_WINDOWS_INTRESOURCE_ICON_SMALL"
 
 /**
- *  \brief  A variable controlling whether the windows message loop is processed by SDL 
+ *  \brief  A variable controlling whether the windows message loop is processed by SDL
  *
  *  This variable can be set to the following values:
  *    "0"       - The window message loop is not run
@@ -528,9 +528,9 @@ extern "C" {
 
 /**
 *  \brief  A variable that is the address of another SDL_Window* (as a hex string formatted with "%p").
-*  
+*
 *  If this hint is set before SDL_CreateWindowFrom() and the SDL_Window* it is set to has
-*  SDL_WINDOW_OPENGL set (and running on WGL only, currently), then two things will occur on the newly 
+*  SDL_WINDOW_OPENGL set (and running on WGL only, currently), then two things will occur on the newly
 *  created SDL_Window:
 *
 *  1. Its pixel format will be set to the same pixel format as this SDL_Window.  This is
@@ -682,7 +682,7 @@ extern "C" {
  * By default this hint is not set and the APK expansion files are not searched.
  */
 #define SDL_HINT_ANDROID_APK_EXPANSION_MAIN_FILE_VERSION "SDL_ANDROID_APK_EXPANSION_MAIN_FILE_VERSION"
- 
+
 /**
  * \brief Android APK expansion patch file version. Should be a string number like "1", "2" etc.
  *
@@ -700,9 +700,9 @@ extern "C" {
  *
  * The variable can be set to the following values:
  *   "0"       - SDL_TEXTEDITING events are sent, and it is the application's
- *               responsibility to render the text from these events and 
+ *               responsibility to render the text from these events and
  *               differentiate it somehow from committed text. (default)
- *   "1"       - If supported by the IME then SDL_TEXTEDITING events are not sent, 
+ *   "1"       - If supported by the IME then SDL_TEXTEDITING events are not sent,
  *               and text that is being composed will be rendered in its own UI.
  */
 #define SDL_HINT_IME_INTERNAL_EDITING "SDL_IME_INTERNAL_EDITING"
@@ -752,7 +752,7 @@ extern "C" {
  *   "0"       - SDL will generate a window-close event when it sees Alt+F4.
  *   "1"       - SDL will only do normal key handling for Alt+F4.
  */
-#define SDL_HINT_WINDOWS_NO_CLOSE_ON_ALT_F4	"SDL_WINDOWS_NO_CLOSE_ON_ALT_F4"
+#define SDL_HINT_WINDOWS_NO_CLOSE_ON_ALT_F4 "SDL_WINDOWS_NO_CLOSE_ON_ALT_F4"
 
 /**
  *  \brief Prevent SDL from using version 4 of the bitmap header when saving BMPs.
diff --git a/bsp/simulator/SDL2-2.0.7/include/SDL_main.h b/bsp/simulator/SDL2-2.0.7/include/SDL_main.h
index 2af32360f7..719f6726a0 100644
--- a/bsp/simulator/SDL2-2.0.7/include/SDL_main.h
+++ b/bsp/simulator/SDL2-2.0.7/include/SDL_main.h
@@ -69,9 +69,9 @@
 
 #elif defined(__NACL__)
 /* On NACL we use ppapi_simple to set up the application helper code,
-   then wait for the first PSE_INSTANCE_DIDCHANGEVIEW event before 
+   then wait for the first PSE_INSTANCE_DIDCHANGEVIEW event before
    starting the user main function.
-   All user code is run in a separate thread by ppapi_simple, thus 
+   All user code is run in a separate thread by ppapi_simple, thus
    allowing for blocking io to take place via nacl_io
 */
 #define SDL_MAIN_NEEDED
diff --git a/bsp/simulator/SDL2-2.0.7/include/SDL_opengl.h b/bsp/simulator/SDL2-2.0.7/include/SDL_opengl.h
index 314dd57eda..8c60791b32 100644
--- a/bsp/simulator/SDL2-2.0.7/include/SDL_opengl.h
+++ b/bsp/simulator/SDL2-2.0.7/include/SDL_opengl.h
@@ -90,7 +90,7 @@
 #    define GLAPI extern
 #  endif /* _STATIC_MESA support */
 #  if defined(__MINGW32__) && defined(GL_NO_STDCALL) || defined(UNDER_CE)  /* The generated DLLs by MingW with STDCALL are not compatible with the ones done by Microsoft's compilers */
-#    define GLAPIENTRY 
+#    define GLAPIENTRY
 #  else
 #    define GLAPIENTRY __stdcall
 #  endif
@@ -173,21 +173,21 @@ extern "C" {
 /*
  * Datatypes
  */
-typedef unsigned int	GLenum;
-typedef unsigned char	GLboolean;
-typedef unsigned int	GLbitfield;
-typedef void		GLvoid;
-typedef signed char	GLbyte;		/* 1-byte signed */
-typedef short		GLshort;	/* 2-byte signed */
-typedef int		GLint;		/* 4-byte signed */
-typedef unsigned char	GLubyte;	/* 1-byte unsigned */
-typedef unsigned short	GLushort;	/* 2-byte unsigned */
-typedef unsigned int	GLuint;		/* 4-byte unsigned */
-typedef int		GLsizei;	/* 4-byte signed */
-typedef float		GLfloat;	/* single precision float */
-typedef float		GLclampf;	/* single precision float in [0,1] */
-typedef double		GLdouble;	/* double precision float */
-typedef double		GLclampd;	/* double precision float in [0,1] */
+typedef unsigned int    GLenum;
+typedef unsigned char   GLboolean;
+typedef unsigned int    GLbitfield;
+typedef void        GLvoid;
+typedef signed char GLbyte;     /* 1-byte signed */
+typedef short       GLshort;    /* 2-byte signed */
+typedef int     GLint;      /* 4-byte signed */
+typedef unsigned char   GLubyte;    /* 1-byte unsigned */
+typedef unsigned short  GLushort;   /* 2-byte unsigned */
+typedef unsigned int    GLuint;     /* 4-byte unsigned */
+typedef int     GLsizei;    /* 4-byte signed */
+typedef float       GLfloat;    /* single precision float */
+typedef float       GLclampf;   /* single precision float in [0,1] */
+typedef double      GLdouble;   /* double precision float */
+typedef double      GLclampd;   /* double precision float in [0,1] */
 
 
 
@@ -196,603 +196,603 @@ typedef double		GLclampd;	/* double precision float in [0,1] */
  */
 
 /* Boolean values */
-#define GL_FALSE				0
-#define GL_TRUE					1
+#define GL_FALSE                0
+#define GL_TRUE                 1
 
 /* Data types */
-#define GL_BYTE					0x1400
-#define GL_UNSIGNED_BYTE			0x1401
-#define GL_SHORT				0x1402
-#define GL_UNSIGNED_SHORT			0x1403
-#define GL_INT					0x1404
-#define GL_UNSIGNED_INT				0x1405
-#define GL_FLOAT				0x1406
-#define GL_2_BYTES				0x1407
-#define GL_3_BYTES				0x1408
-#define GL_4_BYTES				0x1409
-#define GL_DOUBLE				0x140A
+#define GL_BYTE                 0x1400
+#define GL_UNSIGNED_BYTE            0x1401
+#define GL_SHORT                0x1402
+#define GL_UNSIGNED_SHORT           0x1403
+#define GL_INT                  0x1404
+#define GL_UNSIGNED_INT             0x1405
+#define GL_FLOAT                0x1406
+#define GL_2_BYTES              0x1407
+#define GL_3_BYTES              0x1408
+#define GL_4_BYTES              0x1409
+#define GL_DOUBLE               0x140A
 
 /* Primitives */
-#define GL_POINTS				0x0000
-#define GL_LINES				0x0001
-#define GL_LINE_LOOP				0x0002
-#define GL_LINE_STRIP				0x0003
-#define GL_TRIANGLES				0x0004
-#define GL_TRIANGLE_STRIP			0x0005
-#define GL_TRIANGLE_FAN				0x0006
-#define GL_QUADS				0x0007
-#define GL_QUAD_STRIP				0x0008
-#define GL_POLYGON				0x0009
+#define GL_POINTS               0x0000
+#define GL_LINES                0x0001
+#define GL_LINE_LOOP                0x0002
+#define GL_LINE_STRIP               0x0003
+#define GL_TRIANGLES                0x0004
+#define GL_TRIANGLE_STRIP           0x0005
+#define GL_TRIANGLE_FAN             0x0006
+#define GL_QUADS                0x0007
+#define GL_QUAD_STRIP               0x0008
+#define GL_POLYGON              0x0009
 
 /* Vertex Arrays */
-#define GL_VERTEX_ARRAY				0x8074
-#define GL_NORMAL_ARRAY				0x8075
-#define GL_COLOR_ARRAY				0x8076
-#define GL_INDEX_ARRAY				0x8077
-#define GL_TEXTURE_COORD_ARRAY			0x8078
-#define GL_EDGE_FLAG_ARRAY			0x8079
-#define GL_VERTEX_ARRAY_SIZE			0x807A
-#define GL_VERTEX_ARRAY_TYPE			0x807B
-#define GL_VERTEX_ARRAY_STRIDE			0x807C
-#define GL_NORMAL_ARRAY_TYPE			0x807E
-#define GL_NORMAL_ARRAY_STRIDE			0x807F
-#define GL_COLOR_ARRAY_SIZE			0x8081
-#define GL_COLOR_ARRAY_TYPE			0x8082
-#define GL_COLOR_ARRAY_STRIDE			0x8083
-#define GL_INDEX_ARRAY_TYPE			0x8085
-#define GL_INDEX_ARRAY_STRIDE			0x8086
-#define GL_TEXTURE_COORD_ARRAY_SIZE		0x8088
-#define GL_TEXTURE_COORD_ARRAY_TYPE		0x8089
-#define GL_TEXTURE_COORD_ARRAY_STRIDE		0x808A
-#define GL_EDGE_FLAG_ARRAY_STRIDE		0x808C
-#define GL_VERTEX_ARRAY_POINTER			0x808E
-#define GL_NORMAL_ARRAY_POINTER			0x808F
-#define GL_COLOR_ARRAY_POINTER			0x8090
-#define GL_INDEX_ARRAY_POINTER			0x8091
-#define GL_TEXTURE_COORD_ARRAY_POINTER		0x8092
-#define GL_EDGE_FLAG_ARRAY_POINTER		0x8093
-#define GL_V2F					0x2A20
-#define GL_V3F					0x2A21
-#define GL_C4UB_V2F				0x2A22
-#define GL_C4UB_V3F				0x2A23
-#define GL_C3F_V3F				0x2A24
-#define GL_N3F_V3F				0x2A25
-#define GL_C4F_N3F_V3F				0x2A26
-#define GL_T2F_V3F				0x2A27
-#define GL_T4F_V4F				0x2A28
-#define GL_T2F_C4UB_V3F				0x2A29
-#define GL_T2F_C3F_V3F				0x2A2A
-#define GL_T2F_N3F_V3F				0x2A2B
-#define GL_T2F_C4F_N3F_V3F			0x2A2C
-#define GL_T4F_C4F_N3F_V4F			0x2A2D
+#define GL_VERTEX_ARRAY             0x8074
+#define GL_NORMAL_ARRAY             0x8075
+#define GL_COLOR_ARRAY              0x8076
+#define GL_INDEX_ARRAY              0x8077
+#define GL_TEXTURE_COORD_ARRAY          0x8078
+#define GL_EDGE_FLAG_ARRAY          0x8079
+#define GL_VERTEX_ARRAY_SIZE            0x807A
+#define GL_VERTEX_ARRAY_TYPE            0x807B
+#define GL_VERTEX_ARRAY_STRIDE          0x807C
+#define GL_NORMAL_ARRAY_TYPE            0x807E
+#define GL_NORMAL_ARRAY_STRIDE          0x807F
+#define GL_COLOR_ARRAY_SIZE         0x8081
+#define GL_COLOR_ARRAY_TYPE         0x8082
+#define GL_COLOR_ARRAY_STRIDE           0x8083
+#define GL_INDEX_ARRAY_TYPE         0x8085
+#define GL_INDEX_ARRAY_STRIDE           0x8086
+#define GL_TEXTURE_COORD_ARRAY_SIZE     0x8088
+#define GL_TEXTURE_COORD_ARRAY_TYPE     0x8089
+#define GL_TEXTURE_COORD_ARRAY_STRIDE       0x808A
+#define GL_EDGE_FLAG_ARRAY_STRIDE       0x808C
+#define GL_VERTEX_ARRAY_POINTER         0x808E
+#define GL_NORMAL_ARRAY_POINTER         0x808F
+#define GL_COLOR_ARRAY_POINTER          0x8090
+#define GL_INDEX_ARRAY_POINTER          0x8091
+#define GL_TEXTURE_COORD_ARRAY_POINTER      0x8092
+#define GL_EDGE_FLAG_ARRAY_POINTER      0x8093
+#define GL_V2F                  0x2A20
+#define GL_V3F                  0x2A21
+#define GL_C4UB_V2F             0x2A22
+#define GL_C4UB_V3F             0x2A23
+#define GL_C3F_V3F              0x2A24
+#define GL_N3F_V3F              0x2A25
+#define GL_C4F_N3F_V3F              0x2A26
+#define GL_T2F_V3F              0x2A27
+#define GL_T4F_V4F              0x2A28
+#define GL_T2F_C4UB_V3F             0x2A29
+#define GL_T2F_C3F_V3F              0x2A2A
+#define GL_T2F_N3F_V3F              0x2A2B
+#define GL_T2F_C4F_N3F_V3F          0x2A2C
+#define GL_T4F_C4F_N3F_V4F          0x2A2D
 
 /* Matrix Mode */
-#define GL_MATRIX_MODE				0x0BA0
-#define GL_MODELVIEW				0x1700
-#define GL_PROJECTION				0x1701
-#define GL_TEXTURE				0x1702
+#define GL_MATRIX_MODE              0x0BA0
+#define GL_MODELVIEW                0x1700
+#define GL_PROJECTION               0x1701
+#define GL_TEXTURE              0x1702
 
 /* Points */
-#define GL_POINT_SMOOTH				0x0B10
-#define GL_POINT_SIZE				0x0B11
-#define GL_POINT_SIZE_GRANULARITY 		0x0B13
-#define GL_POINT_SIZE_RANGE			0x0B12
+#define GL_POINT_SMOOTH             0x0B10
+#define GL_POINT_SIZE               0x0B11
+#define GL_POINT_SIZE_GRANULARITY       0x0B13
+#define GL_POINT_SIZE_RANGE         0x0B12
 
 /* Lines */
-#define GL_LINE_SMOOTH				0x0B20
-#define GL_LINE_STIPPLE				0x0B24
-#define GL_LINE_STIPPLE_PATTERN			0x0B25
-#define GL_LINE_STIPPLE_REPEAT			0x0B26
-#define GL_LINE_WIDTH				0x0B21
-#define GL_LINE_WIDTH_GRANULARITY		0x0B23
-#define GL_LINE_WIDTH_RANGE			0x0B22
+#define GL_LINE_SMOOTH              0x0B20
+#define GL_LINE_STIPPLE             0x0B24
+#define GL_LINE_STIPPLE_PATTERN         0x0B25
+#define GL_LINE_STIPPLE_REPEAT          0x0B26
+#define GL_LINE_WIDTH               0x0B21
+#define GL_LINE_WIDTH_GRANULARITY       0x0B23
+#define GL_LINE_WIDTH_RANGE         0x0B22
 
 /* Polygons */
-#define GL_POINT				0x1B00
-#define GL_LINE					0x1B01
-#define GL_FILL					0x1B02
-#define GL_CW					0x0900
-#define GL_CCW					0x0901
-#define GL_FRONT				0x0404
-#define GL_BACK					0x0405
-#define GL_POLYGON_MODE				0x0B40
-#define GL_POLYGON_SMOOTH			0x0B41
-#define GL_POLYGON_STIPPLE			0x0B42
-#define GL_EDGE_FLAG				0x0B43
-#define GL_CULL_FACE				0x0B44
-#define GL_CULL_FACE_MODE			0x0B45
-#define GL_FRONT_FACE				0x0B46
-#define GL_POLYGON_OFFSET_FACTOR		0x8038
-#define GL_POLYGON_OFFSET_UNITS			0x2A00
-#define GL_POLYGON_OFFSET_POINT			0x2A01
-#define GL_POLYGON_OFFSET_LINE			0x2A02
-#define GL_POLYGON_OFFSET_FILL			0x8037
+#define GL_POINT                0x1B00
+#define GL_LINE                 0x1B01
+#define GL_FILL                 0x1B02
+#define GL_CW                   0x0900
+#define GL_CCW                  0x0901
+#define GL_FRONT                0x0404
+#define GL_BACK                 0x0405
+#define GL_POLYGON_MODE             0x0B40
+#define GL_POLYGON_SMOOTH           0x0B41
+#define GL_POLYGON_STIPPLE          0x0B42
+#define GL_EDGE_FLAG                0x0B43
+#define GL_CULL_FACE                0x0B44
+#define GL_CULL_FACE_MODE           0x0B45
+#define GL_FRONT_FACE               0x0B46
+#define GL_POLYGON_OFFSET_FACTOR        0x8038
+#define GL_POLYGON_OFFSET_UNITS         0x2A00
+#define GL_POLYGON_OFFSET_POINT         0x2A01
+#define GL_POLYGON_OFFSET_LINE          0x2A02
+#define GL_POLYGON_OFFSET_FILL          0x8037
 
 /* Display Lists */
-#define GL_COMPILE				0x1300
-#define GL_COMPILE_AND_EXECUTE			0x1301
-#define GL_LIST_BASE				0x0B32
-#define GL_LIST_INDEX				0x0B33
-#define GL_LIST_MODE				0x0B30
+#define GL_COMPILE              0x1300
+#define GL_COMPILE_AND_EXECUTE          0x1301
+#define GL_LIST_BASE                0x0B32
+#define GL_LIST_INDEX               0x0B33
+#define GL_LIST_MODE                0x0B30
 
 /* Depth buffer */
-#define GL_NEVER				0x0200
-#define GL_LESS					0x0201
-#define GL_EQUAL				0x0202
-#define GL_LEQUAL				0x0203
-#define GL_GREATER				0x0204
-#define GL_NOTEQUAL				0x0205
-#define GL_GEQUAL				0x0206
-#define GL_ALWAYS				0x0207
-#define GL_DEPTH_TEST				0x0B71
-#define GL_DEPTH_BITS				0x0D56
-#define GL_DEPTH_CLEAR_VALUE			0x0B73
-#define GL_DEPTH_FUNC				0x0B74
-#define GL_DEPTH_RANGE				0x0B70
-#define GL_DEPTH_WRITEMASK			0x0B72
-#define GL_DEPTH_COMPONENT			0x1902
+#define GL_NEVER                0x0200
+#define GL_LESS                 0x0201
+#define GL_EQUAL                0x0202
+#define GL_LEQUAL               0x0203
+#define GL_GREATER              0x0204
+#define GL_NOTEQUAL             0x0205
+#define GL_GEQUAL               0x0206
+#define GL_ALWAYS               0x0207
+#define GL_DEPTH_TEST               0x0B71
+#define GL_DEPTH_BITS               0x0D56
+#define GL_DEPTH_CLEAR_VALUE            0x0B73
+#define GL_DEPTH_FUNC               0x0B74
+#define GL_DEPTH_RANGE              0x0B70
+#define GL_DEPTH_WRITEMASK          0x0B72
+#define GL_DEPTH_COMPONENT          0x1902
 
 /* Lighting */
-#define GL_LIGHTING				0x0B50
-#define GL_LIGHT0				0x4000
-#define GL_LIGHT1				0x4001
-#define GL_LIGHT2				0x4002
-#define GL_LIGHT3				0x4003
-#define GL_LIGHT4				0x4004
-#define GL_LIGHT5				0x4005
-#define GL_LIGHT6				0x4006
-#define GL_LIGHT7				0x4007
-#define GL_SPOT_EXPONENT			0x1205
-#define GL_SPOT_CUTOFF				0x1206
-#define GL_CONSTANT_ATTENUATION			0x1207
-#define GL_LINEAR_ATTENUATION			0x1208
-#define GL_QUADRATIC_ATTENUATION		0x1209
-#define GL_AMBIENT				0x1200
-#define GL_DIFFUSE				0x1201
-#define GL_SPECULAR				0x1202
-#define GL_SHININESS				0x1601
-#define GL_EMISSION				0x1600
-#define GL_POSITION				0x1203
-#define GL_SPOT_DIRECTION			0x1204
-#define GL_AMBIENT_AND_DIFFUSE			0x1602
-#define GL_COLOR_INDEXES			0x1603
-#define GL_LIGHT_MODEL_TWO_SIDE			0x0B52
-#define GL_LIGHT_MODEL_LOCAL_VIEWER		0x0B51
-#define GL_LIGHT_MODEL_AMBIENT			0x0B53
-#define GL_FRONT_AND_BACK			0x0408
-#define GL_SHADE_MODEL				0x0B54
-#define GL_FLAT					0x1D00
-#define GL_SMOOTH				0x1D01
-#define GL_COLOR_MATERIAL			0x0B57
-#define GL_COLOR_MATERIAL_FACE			0x0B55
-#define GL_COLOR_MATERIAL_PARAMETER		0x0B56
-#define GL_NORMALIZE				0x0BA1
+#define GL_LIGHTING             0x0B50
+#define GL_LIGHT0               0x4000
+#define GL_LIGHT1               0x4001
+#define GL_LIGHT2               0x4002
+#define GL_LIGHT3               0x4003
+#define GL_LIGHT4               0x4004
+#define GL_LIGHT5               0x4005
+#define GL_LIGHT6               0x4006
+#define GL_LIGHT7               0x4007
+#define GL_SPOT_EXPONENT            0x1205
+#define GL_SPOT_CUTOFF              0x1206
+#define GL_CONSTANT_ATTENUATION         0x1207
+#define GL_LINEAR_ATTENUATION           0x1208
+#define GL_QUADRATIC_ATTENUATION        0x1209
+#define GL_AMBIENT              0x1200
+#define GL_DIFFUSE              0x1201
+#define GL_SPECULAR             0x1202
+#define GL_SHININESS                0x1601
+#define GL_EMISSION             0x1600
+#define GL_POSITION             0x1203
+#define GL_SPOT_DIRECTION           0x1204
+#define GL_AMBIENT_AND_DIFFUSE          0x1602
+#define GL_COLOR_INDEXES            0x1603
+#define GL_LIGHT_MODEL_TWO_SIDE         0x0B52
+#define GL_LIGHT_MODEL_LOCAL_VIEWER     0x0B51
+#define GL_LIGHT_MODEL_AMBIENT          0x0B53
+#define GL_FRONT_AND_BACK           0x0408
+#define GL_SHADE_MODEL              0x0B54
+#define GL_FLAT                 0x1D00
+#define GL_SMOOTH               0x1D01
+#define GL_COLOR_MATERIAL           0x0B57
+#define GL_COLOR_MATERIAL_FACE          0x0B55
+#define GL_COLOR_MATERIAL_PARAMETER     0x0B56
+#define GL_NORMALIZE                0x0BA1
 
 /* User clipping planes */
-#define GL_CLIP_PLANE0				0x3000
-#define GL_CLIP_PLANE1				0x3001
-#define GL_CLIP_PLANE2				0x3002
-#define GL_CLIP_PLANE3				0x3003
-#define GL_CLIP_PLANE4				0x3004
-#define GL_CLIP_PLANE5				0x3005
+#define GL_CLIP_PLANE0              0x3000
+#define GL_CLIP_PLANE1              0x3001
+#define GL_CLIP_PLANE2              0x3002
+#define GL_CLIP_PLANE3              0x3003
+#define GL_CLIP_PLANE4              0x3004
+#define GL_CLIP_PLANE5              0x3005
 
 /* Accumulation buffer */
-#define GL_ACCUM_RED_BITS			0x0D58
-#define GL_ACCUM_GREEN_BITS			0x0D59
-#define GL_ACCUM_BLUE_BITS			0x0D5A
-#define GL_ACCUM_ALPHA_BITS			0x0D5B
-#define GL_ACCUM_CLEAR_VALUE			0x0B80
-#define GL_ACCUM				0x0100
-#define GL_ADD					0x0104
-#define GL_LOAD					0x0101
-#define GL_MULT					0x0103
-#define GL_RETURN				0x0102
+#define GL_ACCUM_RED_BITS           0x0D58
+#define GL_ACCUM_GREEN_BITS         0x0D59
+#define GL_ACCUM_BLUE_BITS          0x0D5A
+#define GL_ACCUM_ALPHA_BITS         0x0D5B
+#define GL_ACCUM_CLEAR_VALUE            0x0B80
+#define GL_ACCUM                0x0100
+#define GL_ADD                  0x0104
+#define GL_LOAD                 0x0101
+#define GL_MULT                 0x0103
+#define GL_RETURN               0x0102
 
 /* Alpha testing */
-#define GL_ALPHA_TEST				0x0BC0
-#define GL_ALPHA_TEST_REF			0x0BC2
-#define GL_ALPHA_TEST_FUNC			0x0BC1
+#define GL_ALPHA_TEST               0x0BC0
+#define GL_ALPHA_TEST_REF           0x0BC2
+#define GL_ALPHA_TEST_FUNC          0x0BC1
 
 /* Blending */
-#define GL_BLEND				0x0BE2
-#define GL_BLEND_SRC				0x0BE1
-#define GL_BLEND_DST				0x0BE0
-#define GL_ZERO					0
-#define GL_ONE					1
-#define GL_SRC_COLOR				0x0300
-#define GL_ONE_MINUS_SRC_COLOR			0x0301
-#define GL_SRC_ALPHA				0x0302
-#define GL_ONE_MINUS_SRC_ALPHA			0x0303
-#define GL_DST_ALPHA				0x0304
-#define GL_ONE_MINUS_DST_ALPHA			0x0305
-#define GL_DST_COLOR				0x0306
-#define GL_ONE_MINUS_DST_COLOR			0x0307
-#define GL_SRC_ALPHA_SATURATE			0x0308
+#define GL_BLEND                0x0BE2
+#define GL_BLEND_SRC                0x0BE1
+#define GL_BLEND_DST                0x0BE0
+#define GL_ZERO                 0
+#define GL_ONE                  1
+#define GL_SRC_COLOR                0x0300
+#define GL_ONE_MINUS_SRC_COLOR          0x0301
+#define GL_SRC_ALPHA                0x0302
+#define GL_ONE_MINUS_SRC_ALPHA          0x0303
+#define GL_DST_ALPHA                0x0304
+#define GL_ONE_MINUS_DST_ALPHA          0x0305
+#define GL_DST_COLOR                0x0306
+#define GL_ONE_MINUS_DST_COLOR          0x0307
+#define GL_SRC_ALPHA_SATURATE           0x0308
 
 /* Render Mode */
-#define GL_FEEDBACK				0x1C01
-#define GL_RENDER				0x1C00
-#define GL_SELECT				0x1C02
+#define GL_FEEDBACK             0x1C01
+#define GL_RENDER               0x1C00
+#define GL_SELECT               0x1C02
 
 /* Feedback */
-#define GL_2D					0x0600
-#define GL_3D					0x0601
-#define GL_3D_COLOR				0x0602
-#define GL_3D_COLOR_TEXTURE			0x0603
-#define GL_4D_COLOR_TEXTURE			0x0604
-#define GL_POINT_TOKEN				0x0701
-#define GL_LINE_TOKEN				0x0702
-#define GL_LINE_RESET_TOKEN			0x0707
-#define GL_POLYGON_TOKEN			0x0703
-#define GL_BITMAP_TOKEN				0x0704
-#define GL_DRAW_PIXEL_TOKEN			0x0705
-#define GL_COPY_PIXEL_TOKEN			0x0706
-#define GL_PASS_THROUGH_TOKEN			0x0700
-#define GL_FEEDBACK_BUFFER_POINTER		0x0DF0
-#define GL_FEEDBACK_BUFFER_SIZE			0x0DF1
-#define GL_FEEDBACK_BUFFER_TYPE			0x0DF2
+#define GL_2D                   0x0600
+#define GL_3D                   0x0601
+#define GL_3D_COLOR             0x0602
+#define GL_3D_COLOR_TEXTURE         0x0603
+#define GL_4D_COLOR_TEXTURE         0x0604
+#define GL_POINT_TOKEN              0x0701
+#define GL_LINE_TOKEN               0x0702
+#define GL_LINE_RESET_TOKEN         0x0707
+#define GL_POLYGON_TOKEN            0x0703
+#define GL_BITMAP_TOKEN             0x0704
+#define GL_DRAW_PIXEL_TOKEN         0x0705
+#define GL_COPY_PIXEL_TOKEN         0x0706
+#define GL_PASS_THROUGH_TOKEN           0x0700
+#define GL_FEEDBACK_BUFFER_POINTER      0x0DF0
+#define GL_FEEDBACK_BUFFER_SIZE         0x0DF1
+#define GL_FEEDBACK_BUFFER_TYPE         0x0DF2
 
 /* Selection */
-#define GL_SELECTION_BUFFER_POINTER		0x0DF3
-#define GL_SELECTION_BUFFER_SIZE		0x0DF4
+#define GL_SELECTION_BUFFER_POINTER     0x0DF3
+#define GL_SELECTION_BUFFER_SIZE        0x0DF4
 
 /* Fog */
-#define GL_FOG					0x0B60
-#define GL_FOG_MODE				0x0B65
-#define GL_FOG_DENSITY				0x0B62
-#define GL_FOG_COLOR				0x0B66
-#define GL_FOG_INDEX				0x0B61
-#define GL_FOG_START				0x0B63
-#define GL_FOG_END				0x0B64
-#define GL_LINEAR				0x2601
-#define GL_EXP					0x0800
-#define GL_EXP2					0x0801
+#define GL_FOG                  0x0B60
+#define GL_FOG_MODE             0x0B65
+#define GL_FOG_DENSITY              0x0B62
+#define GL_FOG_COLOR                0x0B66
+#define GL_FOG_INDEX                0x0B61
+#define GL_FOG_START                0x0B63
+#define GL_FOG_END              0x0B64
+#define GL_LINEAR               0x2601
+#define GL_EXP                  0x0800
+#define GL_EXP2                 0x0801
 
 /* Logic Ops */
-#define GL_LOGIC_OP				0x0BF1
-#define GL_INDEX_LOGIC_OP			0x0BF1
-#define GL_COLOR_LOGIC_OP			0x0BF2
-#define GL_LOGIC_OP_MODE			0x0BF0
-#define GL_CLEAR				0x1500
-#define GL_SET					0x150F
-#define GL_COPY					0x1503
-#define GL_COPY_INVERTED			0x150C
-#define GL_NOOP					0x1505
-#define GL_INVERT				0x150A
-#define GL_AND					0x1501
-#define GL_NAND					0x150E
-#define GL_OR					0x1507
-#define GL_NOR					0x1508
-#define GL_XOR					0x1506
-#define GL_EQUIV				0x1509
-#define GL_AND_REVERSE				0x1502
-#define GL_AND_INVERTED				0x1504
-#define GL_OR_REVERSE				0x150B
-#define GL_OR_INVERTED				0x150D
+#define GL_LOGIC_OP             0x0BF1
+#define GL_INDEX_LOGIC_OP           0x0BF1
+#define GL_COLOR_LOGIC_OP           0x0BF2
+#define GL_LOGIC_OP_MODE            0x0BF0
+#define GL_CLEAR                0x1500
+#define GL_SET                  0x150F
+#define GL_COPY                 0x1503
+#define GL_COPY_INVERTED            0x150C
+#define GL_NOOP                 0x1505
+#define GL_INVERT               0x150A
+#define GL_AND                  0x1501
+#define GL_NAND                 0x150E
+#define GL_OR                   0x1507
+#define GL_NOR                  0x1508
+#define GL_XOR                  0x1506
+#define GL_EQUIV                0x1509
+#define GL_AND_REVERSE              0x1502
+#define GL_AND_INVERTED             0x1504
+#define GL_OR_REVERSE               0x150B
+#define GL_OR_INVERTED              0x150D
 
 /* Stencil */
-#define GL_STENCIL_BITS				0x0D57
-#define GL_STENCIL_TEST				0x0B90
-#define GL_STENCIL_CLEAR_VALUE			0x0B91
-#define GL_STENCIL_FUNC				0x0B92
-#define GL_STENCIL_VALUE_MASK			0x0B93
-#define GL_STENCIL_FAIL				0x0B94
-#define GL_STENCIL_PASS_DEPTH_FAIL		0x0B95
-#define GL_STENCIL_PASS_DEPTH_PASS		0x0B96
-#define GL_STENCIL_REF				0x0B97
-#define GL_STENCIL_WRITEMASK			0x0B98
-#define GL_STENCIL_INDEX			0x1901
-#define GL_KEEP					0x1E00
-#define GL_REPLACE				0x1E01
-#define GL_INCR					0x1E02
-#define GL_DECR					0x1E03
+#define GL_STENCIL_BITS             0x0D57
+#define GL_STENCIL_TEST             0x0B90
+#define GL_STENCIL_CLEAR_VALUE          0x0B91
+#define GL_STENCIL_FUNC             0x0B92
+#define GL_STENCIL_VALUE_MASK           0x0B93
+#define GL_STENCIL_FAIL             0x0B94
+#define GL_STENCIL_PASS_DEPTH_FAIL      0x0B95
+#define GL_STENCIL_PASS_DEPTH_PASS      0x0B96
+#define GL_STENCIL_REF              0x0B97
+#define GL_STENCIL_WRITEMASK            0x0B98
+#define GL_STENCIL_INDEX            0x1901
+#define GL_KEEP                 0x1E00
+#define GL_REPLACE              0x1E01
+#define GL_INCR                 0x1E02
+#define GL_DECR                 0x1E03
 
 /* Buffers, Pixel Drawing/Reading */
-#define GL_NONE					0
-#define GL_LEFT					0x0406
-#define GL_RIGHT				0x0407
-/*GL_FRONT					0x0404 */
-/*GL_BACK					0x0405 */
-/*GL_FRONT_AND_BACK				0x0408 */
-#define GL_FRONT_LEFT				0x0400
-#define GL_FRONT_RIGHT				0x0401
-#define GL_BACK_LEFT				0x0402
-#define GL_BACK_RIGHT				0x0403
-#define GL_AUX0					0x0409
-#define GL_AUX1					0x040A
-#define GL_AUX2					0x040B
-#define GL_AUX3					0x040C
-#define GL_COLOR_INDEX				0x1900
-#define GL_RED					0x1903
-#define GL_GREEN				0x1904
-#define GL_BLUE					0x1905
-#define GL_ALPHA				0x1906
-#define GL_LUMINANCE				0x1909
-#define GL_LUMINANCE_ALPHA			0x190A
-#define GL_ALPHA_BITS				0x0D55
-#define GL_RED_BITS				0x0D52
-#define GL_GREEN_BITS				0x0D53
-#define GL_BLUE_BITS				0x0D54
-#define GL_INDEX_BITS				0x0D51
-#define GL_SUBPIXEL_BITS			0x0D50
-#define GL_AUX_BUFFERS				0x0C00
-#define GL_READ_BUFFER				0x0C02
-#define GL_DRAW_BUFFER				0x0C01
-#define GL_DOUBLEBUFFER				0x0C32
-#define GL_STEREO				0x0C33
-#define GL_BITMAP				0x1A00
-#define GL_COLOR				0x1800
-#define GL_DEPTH				0x1801
-#define GL_STENCIL				0x1802
-#define GL_DITHER				0x0BD0
-#define GL_RGB					0x1907
-#define GL_RGBA					0x1908
+#define GL_NONE                 0
+#define GL_LEFT                 0x0406
+#define GL_RIGHT                0x0407
+/*GL_FRONT                  0x0404 */
+/*GL_BACK                   0x0405 */
+/*GL_FRONT_AND_BACK             0x0408 */
+#define GL_FRONT_LEFT               0x0400
+#define GL_FRONT_RIGHT              0x0401
+#define GL_BACK_LEFT                0x0402
+#define GL_BACK_RIGHT               0x0403
+#define GL_AUX0                 0x0409
+#define GL_AUX1                 0x040A
+#define GL_AUX2                 0x040B
+#define GL_AUX3                 0x040C
+#define GL_COLOR_INDEX              0x1900
+#define GL_RED                  0x1903
+#define GL_GREEN                0x1904
+#define GL_BLUE                 0x1905
+#define GL_ALPHA                0x1906
+#define GL_LUMINANCE                0x1909
+#define GL_LUMINANCE_ALPHA          0x190A
+#define GL_ALPHA_BITS               0x0D55
+#define GL_RED_BITS             0x0D52
+#define GL_GREEN_BITS               0x0D53
+#define GL_BLUE_BITS                0x0D54
+#define GL_INDEX_BITS               0x0D51
+#define GL_SUBPIXEL_BITS            0x0D50
+#define GL_AUX_BUFFERS              0x0C00
+#define GL_READ_BUFFER              0x0C02
+#define GL_DRAW_BUFFER              0x0C01
+#define GL_DOUBLEBUFFER             0x0C32
+#define GL_STEREO               0x0C33
+#define GL_BITMAP               0x1A00
+#define GL_COLOR                0x1800
+#define GL_DEPTH                0x1801
+#define GL_STENCIL              0x1802
+#define GL_DITHER               0x0BD0
+#define GL_RGB                  0x1907
+#define GL_RGBA                 0x1908
 
 /* Implementation limits */
-#define GL_MAX_LIST_NESTING			0x0B31
-#define GL_MAX_EVAL_ORDER			0x0D30
-#define GL_MAX_LIGHTS				0x0D31
-#define GL_MAX_CLIP_PLANES			0x0D32
-#define GL_MAX_TEXTURE_SIZE			0x0D33
-#define GL_MAX_PIXEL_MAP_TABLE			0x0D34
-#define GL_MAX_ATTRIB_STACK_DEPTH		0x0D35
-#define GL_MAX_MODELVIEW_STACK_DEPTH		0x0D36
-#define GL_MAX_NAME_STACK_DEPTH			0x0D37
-#define GL_MAX_PROJECTION_STACK_DEPTH		0x0D38
-#define GL_MAX_TEXTURE_STACK_DEPTH		0x0D39
-#define GL_MAX_VIEWPORT_DIMS			0x0D3A
-#define GL_MAX_CLIENT_ATTRIB_STACK_DEPTH	0x0D3B
+#define GL_MAX_LIST_NESTING         0x0B31
+#define GL_MAX_EVAL_ORDER           0x0D30
+#define GL_MAX_LIGHTS               0x0D31
+#define GL_MAX_CLIP_PLANES          0x0D32
+#define GL_MAX_TEXTURE_SIZE         0x0D33
+#define GL_MAX_PIXEL_MAP_TABLE          0x0D34
+#define GL_MAX_ATTRIB_STACK_DEPTH       0x0D35
+#define GL_MAX_MODELVIEW_STACK_DEPTH        0x0D36
+#define GL_MAX_NAME_STACK_DEPTH         0x0D37
+#define GL_MAX_PROJECTION_STACK_DEPTH       0x0D38
+#define GL_MAX_TEXTURE_STACK_DEPTH      0x0D39
+#define GL_MAX_VIEWPORT_DIMS            0x0D3A
+#define GL_MAX_CLIENT_ATTRIB_STACK_DEPTH    0x0D3B
 
 /* Gets */
-#define GL_ATTRIB_STACK_DEPTH			0x0BB0
-#define GL_CLIENT_ATTRIB_STACK_DEPTH		0x0BB1
-#define GL_COLOR_CLEAR_VALUE			0x0C22
-#define GL_COLOR_WRITEMASK			0x0C23
-#define GL_CURRENT_INDEX			0x0B01
-#define GL_CURRENT_COLOR			0x0B00
-#define GL_CURRENT_NORMAL			0x0B02
-#define GL_CURRENT_RASTER_COLOR			0x0B04
-#define GL_CURRENT_RASTER_DISTANCE		0x0B09
-#define GL_CURRENT_RASTER_INDEX			0x0B05
-#define GL_CURRENT_RASTER_POSITION		0x0B07
-#define GL_CURRENT_RASTER_TEXTURE_COORDS	0x0B06
-#define GL_CURRENT_RASTER_POSITION_VALID	0x0B08
-#define GL_CURRENT_TEXTURE_COORDS		0x0B03
-#define GL_INDEX_CLEAR_VALUE			0x0C20
-#define GL_INDEX_MODE				0x0C30
-#define GL_INDEX_WRITEMASK			0x0C21
-#define GL_MODELVIEW_MATRIX			0x0BA6
-#define GL_MODELVIEW_STACK_DEPTH		0x0BA3
-#define GL_NAME_STACK_DEPTH			0x0D70
-#define GL_PROJECTION_MATRIX			0x0BA7
-#define GL_PROJECTION_STACK_DEPTH		0x0BA4
-#define GL_RENDER_MODE				0x0C40
-#define GL_RGBA_MODE				0x0C31
-#define GL_TEXTURE_MATRIX			0x0BA8
-#define GL_TEXTURE_STACK_DEPTH			0x0BA5
-#define GL_VIEWPORT				0x0BA2
+#define GL_ATTRIB_STACK_DEPTH           0x0BB0
+#define GL_CLIENT_ATTRIB_STACK_DEPTH        0x0BB1
+#define GL_COLOR_CLEAR_VALUE            0x0C22
+#define GL_COLOR_WRITEMASK          0x0C23
+#define GL_CURRENT_INDEX            0x0B01
+#define GL_CURRENT_COLOR            0x0B00
+#define GL_CURRENT_NORMAL           0x0B02
+#define GL_CURRENT_RASTER_COLOR         0x0B04
+#define GL_CURRENT_RASTER_DISTANCE      0x0B09
+#define GL_CURRENT_RASTER_INDEX         0x0B05
+#define GL_CURRENT_RASTER_POSITION      0x0B07
+#define GL_CURRENT_RASTER_TEXTURE_COORDS    0x0B06
+#define GL_CURRENT_RASTER_POSITION_VALID    0x0B08
+#define GL_CURRENT_TEXTURE_COORDS       0x0B03
+#define GL_INDEX_CLEAR_VALUE            0x0C20
+#define GL_INDEX_MODE               0x0C30
+#define GL_INDEX_WRITEMASK          0x0C21
+#define GL_MODELVIEW_MATRIX         0x0BA6
+#define GL_MODELVIEW_STACK_DEPTH        0x0BA3
+#define GL_NAME_STACK_DEPTH         0x0D70
+#define GL_PROJECTION_MATRIX            0x0BA7
+#define GL_PROJECTION_STACK_DEPTH       0x0BA4
+#define GL_RENDER_MODE              0x0C40
+#define GL_RGBA_MODE                0x0C31
+#define GL_TEXTURE_MATRIX           0x0BA8
+#define GL_TEXTURE_STACK_DEPTH          0x0BA5
+#define GL_VIEWPORT             0x0BA2
 
 /* Evaluators */
-#define GL_AUTO_NORMAL				0x0D80
-#define GL_MAP1_COLOR_4				0x0D90
-#define GL_MAP1_INDEX				0x0D91
-#define GL_MAP1_NORMAL				0x0D92
-#define GL_MAP1_TEXTURE_COORD_1			0x0D93
-#define GL_MAP1_TEXTURE_COORD_2			0x0D94
-#define GL_MAP1_TEXTURE_COORD_3			0x0D95
-#define GL_MAP1_TEXTURE_COORD_4			0x0D96
-#define GL_MAP1_VERTEX_3			0x0D97
-#define GL_MAP1_VERTEX_4			0x0D98
-#define GL_MAP2_COLOR_4				0x0DB0
-#define GL_MAP2_INDEX				0x0DB1
-#define GL_MAP2_NORMAL				0x0DB2
-#define GL_MAP2_TEXTURE_COORD_1			0x0DB3
-#define GL_MAP2_TEXTURE_COORD_2			0x0DB4
-#define GL_MAP2_TEXTURE_COORD_3			0x0DB5
-#define GL_MAP2_TEXTURE_COORD_4			0x0DB6
-#define GL_MAP2_VERTEX_3			0x0DB7
-#define GL_MAP2_VERTEX_4			0x0DB8
-#define GL_MAP1_GRID_DOMAIN			0x0DD0
-#define GL_MAP1_GRID_SEGMENTS			0x0DD1
-#define GL_MAP2_GRID_DOMAIN			0x0DD2
-#define GL_MAP2_GRID_SEGMENTS			0x0DD3
-#define GL_COEFF				0x0A00
-#define GL_ORDER				0x0A01
-#define GL_DOMAIN				0x0A02
+#define GL_AUTO_NORMAL              0x0D80
+#define GL_MAP1_COLOR_4             0x0D90
+#define GL_MAP1_INDEX               0x0D91
+#define GL_MAP1_NORMAL              0x0D92
+#define GL_MAP1_TEXTURE_COORD_1         0x0D93
+#define GL_MAP1_TEXTURE_COORD_2         0x0D94
+#define GL_MAP1_TEXTURE_COORD_3         0x0D95
+#define GL_MAP1_TEXTURE_COORD_4         0x0D96
+#define GL_MAP1_VERTEX_3            0x0D97
+#define GL_MAP1_VERTEX_4            0x0D98
+#define GL_MAP2_COLOR_4             0x0DB0
+#define GL_MAP2_INDEX               0x0DB1
+#define GL_MAP2_NORMAL              0x0DB2
+#define GL_MAP2_TEXTURE_COORD_1         0x0DB3
+#define GL_MAP2_TEXTURE_COORD_2         0x0DB4
+#define GL_MAP2_TEXTURE_COORD_3         0x0DB5
+#define GL_MAP2_TEXTURE_COORD_4         0x0DB6
+#define GL_MAP2_VERTEX_3            0x0DB7
+#define GL_MAP2_VERTEX_4            0x0DB8
+#define GL_MAP1_GRID_DOMAIN         0x0DD0
+#define GL_MAP1_GRID_SEGMENTS           0x0DD1
+#define GL_MAP2_GRID_DOMAIN         0x0DD2
+#define GL_MAP2_GRID_SEGMENTS           0x0DD3
+#define GL_COEFF                0x0A00
+#define GL_ORDER                0x0A01
+#define GL_DOMAIN               0x0A02
 
 /* Hints */
-#define GL_PERSPECTIVE_CORRECTION_HINT		0x0C50
-#define GL_POINT_SMOOTH_HINT			0x0C51
-#define GL_LINE_SMOOTH_HINT			0x0C52
-#define GL_POLYGON_SMOOTH_HINT			0x0C53
-#define GL_FOG_HINT				0x0C54
-#define GL_DONT_CARE				0x1100
-#define GL_FASTEST				0x1101
-#define GL_NICEST				0x1102
+#define GL_PERSPECTIVE_CORRECTION_HINT      0x0C50
+#define GL_POINT_SMOOTH_HINT            0x0C51
+#define GL_LINE_SMOOTH_HINT         0x0C52
+#define GL_POLYGON_SMOOTH_HINT          0x0C53
+#define GL_FOG_HINT             0x0C54
+#define GL_DONT_CARE                0x1100
+#define GL_FASTEST              0x1101
+#define GL_NICEST               0x1102
 
 /* Scissor box */
-#define GL_SCISSOR_BOX				0x0C10
-#define GL_SCISSOR_TEST				0x0C11
+#define GL_SCISSOR_BOX              0x0C10
+#define GL_SCISSOR_TEST             0x0C11
 
 /* Pixel Mode / Transfer */
-#define GL_MAP_COLOR				0x0D10
-#define GL_MAP_STENCIL				0x0D11
-#define GL_INDEX_SHIFT				0x0D12
-#define GL_INDEX_OFFSET				0x0D13
-#define GL_RED_SCALE				0x0D14
-#define GL_RED_BIAS				0x0D15
-#define GL_GREEN_SCALE				0x0D18
-#define GL_GREEN_BIAS				0x0D19
-#define GL_BLUE_SCALE				0x0D1A
-#define GL_BLUE_BIAS				0x0D1B
-#define GL_ALPHA_SCALE				0x0D1C
-#define GL_ALPHA_BIAS				0x0D1D
-#define GL_DEPTH_SCALE				0x0D1E
-#define GL_DEPTH_BIAS				0x0D1F
-#define GL_PIXEL_MAP_S_TO_S_SIZE		0x0CB1
-#define GL_PIXEL_MAP_I_TO_I_SIZE		0x0CB0
-#define GL_PIXEL_MAP_I_TO_R_SIZE		0x0CB2
-#define GL_PIXEL_MAP_I_TO_G_SIZE		0x0CB3
-#define GL_PIXEL_MAP_I_TO_B_SIZE		0x0CB4
-#define GL_PIXEL_MAP_I_TO_A_SIZE		0x0CB5
-#define GL_PIXEL_MAP_R_TO_R_SIZE		0x0CB6
-#define GL_PIXEL_MAP_G_TO_G_SIZE		0x0CB7
-#define GL_PIXEL_MAP_B_TO_B_SIZE		0x0CB8
-#define GL_PIXEL_MAP_A_TO_A_SIZE		0x0CB9
-#define GL_PIXEL_MAP_S_TO_S			0x0C71
-#define GL_PIXEL_MAP_I_TO_I			0x0C70
-#define GL_PIXEL_MAP_I_TO_R			0x0C72
-#define GL_PIXEL_MAP_I_TO_G			0x0C73
-#define GL_PIXEL_MAP_I_TO_B			0x0C74
-#define GL_PIXEL_MAP_I_TO_A			0x0C75
-#define GL_PIXEL_MAP_R_TO_R			0x0C76
-#define GL_PIXEL_MAP_G_TO_G			0x0C77
-#define GL_PIXEL_MAP_B_TO_B			0x0C78
-#define GL_PIXEL_MAP_A_TO_A			0x0C79
-#define GL_PACK_ALIGNMENT			0x0D05
-#define GL_PACK_LSB_FIRST			0x0D01
-#define GL_PACK_ROW_LENGTH			0x0D02
-#define GL_PACK_SKIP_PIXELS			0x0D04
-#define GL_PACK_SKIP_ROWS			0x0D03
-#define GL_PACK_SWAP_BYTES			0x0D00
-#define GL_UNPACK_ALIGNMENT			0x0CF5
-#define GL_UNPACK_LSB_FIRST			0x0CF1
-#define GL_UNPACK_ROW_LENGTH			0x0CF2
-#define GL_UNPACK_SKIP_PIXELS			0x0CF4
-#define GL_UNPACK_SKIP_ROWS			0x0CF3
-#define GL_UNPACK_SWAP_BYTES			0x0CF0
-#define GL_ZOOM_X				0x0D16
-#define GL_ZOOM_Y				0x0D17
+#define GL_MAP_COLOR                0x0D10
+#define GL_MAP_STENCIL              0x0D11
+#define GL_INDEX_SHIFT              0x0D12
+#define GL_INDEX_OFFSET             0x0D13
+#define GL_RED_SCALE                0x0D14
+#define GL_RED_BIAS             0x0D15
+#define GL_GREEN_SCALE              0x0D18
+#define GL_GREEN_BIAS               0x0D19
+#define GL_BLUE_SCALE               0x0D1A
+#define GL_BLUE_BIAS                0x0D1B
+#define GL_ALPHA_SCALE              0x0D1C
+#define GL_ALPHA_BIAS               0x0D1D
+#define GL_DEPTH_SCALE              0x0D1E
+#define GL_DEPTH_BIAS               0x0D1F
+#define GL_PIXEL_MAP_S_TO_S_SIZE        0x0CB1
+#define GL_PIXEL_MAP_I_TO_I_SIZE        0x0CB0
+#define GL_PIXEL_MAP_I_TO_R_SIZE        0x0CB2
+#define GL_PIXEL_MAP_I_TO_G_SIZE        0x0CB3
+#define GL_PIXEL_MAP_I_TO_B_SIZE        0x0CB4
+#define GL_PIXEL_MAP_I_TO_A_SIZE        0x0CB5
+#define GL_PIXEL_MAP_R_TO_R_SIZE        0x0CB6
+#define GL_PIXEL_MAP_G_TO_G_SIZE        0x0CB7
+#define GL_PIXEL_MAP_B_TO_B_SIZE        0x0CB8
+#define GL_PIXEL_MAP_A_TO_A_SIZE        0x0CB9
+#define GL_PIXEL_MAP_S_TO_S         0x0C71
+#define GL_PIXEL_MAP_I_TO_I         0x0C70
+#define GL_PIXEL_MAP_I_TO_R         0x0C72
+#define GL_PIXEL_MAP_I_TO_G         0x0C73
+#define GL_PIXEL_MAP_I_TO_B         0x0C74
+#define GL_PIXEL_MAP_I_TO_A         0x0C75
+#define GL_PIXEL_MAP_R_TO_R         0x0C76
+#define GL_PIXEL_MAP_G_TO_G         0x0C77
+#define GL_PIXEL_MAP_B_TO_B         0x0C78
+#define GL_PIXEL_MAP_A_TO_A         0x0C79
+#define GL_PACK_ALIGNMENT           0x0D05
+#define GL_PACK_LSB_FIRST           0x0D01
+#define GL_PACK_ROW_LENGTH          0x0D02
+#define GL_PACK_SKIP_PIXELS         0x0D04
+#define GL_PACK_SKIP_ROWS           0x0D03
+#define GL_PACK_SWAP_BYTES          0x0D00
+#define GL_UNPACK_ALIGNMENT         0x0CF5
+#define GL_UNPACK_LSB_FIRST         0x0CF1
+#define GL_UNPACK_ROW_LENGTH            0x0CF2
+#define GL_UNPACK_SKIP_PIXELS           0x0CF4
+#define GL_UNPACK_SKIP_ROWS         0x0CF3
+#define GL_UNPACK_SWAP_BYTES            0x0CF0
+#define GL_ZOOM_X               0x0D16
+#define GL_ZOOM_Y               0x0D17
 
 /* Texture mapping */
-#define GL_TEXTURE_ENV				0x2300
-#define GL_TEXTURE_ENV_MODE			0x2200
-#define GL_TEXTURE_1D				0x0DE0
-#define GL_TEXTURE_2D				0x0DE1
-#define GL_TEXTURE_WRAP_S			0x2802
-#define GL_TEXTURE_WRAP_T			0x2803
-#define GL_TEXTURE_MAG_FILTER			0x2800
-#define GL_TEXTURE_MIN_FILTER			0x2801
-#define GL_TEXTURE_ENV_COLOR			0x2201
-#define GL_TEXTURE_GEN_S			0x0C60
-#define GL_TEXTURE_GEN_T			0x0C61
-#define GL_TEXTURE_GEN_R			0x0C62
-#define GL_TEXTURE_GEN_Q			0x0C63
-#define GL_TEXTURE_GEN_MODE			0x2500
-#define GL_TEXTURE_BORDER_COLOR			0x1004
-#define GL_TEXTURE_WIDTH			0x1000
-#define GL_TEXTURE_HEIGHT			0x1001
-#define GL_TEXTURE_BORDER			0x1005
-#define GL_TEXTURE_COMPONENTS			0x1003
-#define GL_TEXTURE_RED_SIZE			0x805C
-#define GL_TEXTURE_GREEN_SIZE			0x805D
-#define GL_TEXTURE_BLUE_SIZE			0x805E
-#define GL_TEXTURE_ALPHA_SIZE			0x805F
-#define GL_TEXTURE_LUMINANCE_SIZE		0x8060
-#define GL_TEXTURE_INTENSITY_SIZE		0x8061
-#define GL_NEAREST_MIPMAP_NEAREST		0x2700
-#define GL_NEAREST_MIPMAP_LINEAR		0x2702
-#define GL_LINEAR_MIPMAP_NEAREST		0x2701
-#define GL_LINEAR_MIPMAP_LINEAR			0x2703
-#define GL_OBJECT_LINEAR			0x2401
-#define GL_OBJECT_PLANE				0x2501
-#define GL_EYE_LINEAR				0x2400
-#define GL_EYE_PLANE				0x2502
-#define GL_SPHERE_MAP				0x2402
-#define GL_DECAL				0x2101
-#define GL_MODULATE				0x2100
-#define GL_NEAREST				0x2600
-#define GL_REPEAT				0x2901
-#define GL_CLAMP				0x2900
-#define GL_S					0x2000
-#define GL_T					0x2001
-#define GL_R					0x2002
-#define GL_Q					0x2003
+#define GL_TEXTURE_ENV              0x2300
+#define GL_TEXTURE_ENV_MODE         0x2200
+#define GL_TEXTURE_1D               0x0DE0
+#define GL_TEXTURE_2D               0x0DE1
+#define GL_TEXTURE_WRAP_S           0x2802
+#define GL_TEXTURE_WRAP_T           0x2803
+#define GL_TEXTURE_MAG_FILTER           0x2800
+#define GL_TEXTURE_MIN_FILTER           0x2801
+#define GL_TEXTURE_ENV_COLOR            0x2201
+#define GL_TEXTURE_GEN_S            0x0C60
+#define GL_TEXTURE_GEN_T            0x0C61
+#define GL_TEXTURE_GEN_R            0x0C62
+#define GL_TEXTURE_GEN_Q            0x0C63
+#define GL_TEXTURE_GEN_MODE         0x2500
+#define GL_TEXTURE_BORDER_COLOR         0x1004
+#define GL_TEXTURE_WIDTH            0x1000
+#define GL_TEXTURE_HEIGHT           0x1001
+#define GL_TEXTURE_BORDER           0x1005
+#define GL_TEXTURE_COMPONENTS           0x1003
+#define GL_TEXTURE_RED_SIZE         0x805C
+#define GL_TEXTURE_GREEN_SIZE           0x805D
+#define GL_TEXTURE_BLUE_SIZE            0x805E
+#define GL_TEXTURE_ALPHA_SIZE           0x805F
+#define GL_TEXTURE_LUMINANCE_SIZE       0x8060
+#define GL_TEXTURE_INTENSITY_SIZE       0x8061
+#define GL_NEAREST_MIPMAP_NEAREST       0x2700
+#define GL_NEAREST_MIPMAP_LINEAR        0x2702
+#define GL_LINEAR_MIPMAP_NEAREST        0x2701
+#define GL_LINEAR_MIPMAP_LINEAR         0x2703
+#define GL_OBJECT_LINEAR            0x2401
+#define GL_OBJECT_PLANE             0x2501
+#define GL_EYE_LINEAR               0x2400
+#define GL_EYE_PLANE                0x2502
+#define GL_SPHERE_MAP               0x2402
+#define GL_DECAL                0x2101
+#define GL_MODULATE             0x2100
+#define GL_NEAREST              0x2600
+#define GL_REPEAT               0x2901
+#define GL_CLAMP                0x2900
+#define GL_S                    0x2000
+#define GL_T                    0x2001
+#define GL_R                    0x2002
+#define GL_Q                    0x2003
 
 /* Utility */
-#define GL_VENDOR				0x1F00
-#define GL_RENDERER				0x1F01
-#define GL_VERSION				0x1F02
-#define GL_EXTENSIONS				0x1F03
+#define GL_VENDOR               0x1F00
+#define GL_RENDERER             0x1F01
+#define GL_VERSION              0x1F02
+#define GL_EXTENSIONS               0x1F03
 
 /* Errors */
-#define GL_NO_ERROR 				0
-#define GL_INVALID_ENUM				0x0500
-#define GL_INVALID_VALUE			0x0501
-#define GL_INVALID_OPERATION			0x0502
-#define GL_STACK_OVERFLOW			0x0503
-#define GL_STACK_UNDERFLOW			0x0504
-#define GL_OUT_OF_MEMORY			0x0505
+#define GL_NO_ERROR                 0
+#define GL_INVALID_ENUM             0x0500
+#define GL_INVALID_VALUE            0x0501
+#define GL_INVALID_OPERATION            0x0502
+#define GL_STACK_OVERFLOW           0x0503
+#define GL_STACK_UNDERFLOW          0x0504
+#define GL_OUT_OF_MEMORY            0x0505
 
 /* glPush/PopAttrib bits */
-#define GL_CURRENT_BIT				0x00000001
-#define GL_POINT_BIT				0x00000002
-#define GL_LINE_BIT				0x00000004
-#define GL_POLYGON_BIT				0x00000008
-#define GL_POLYGON_STIPPLE_BIT			0x00000010
-#define GL_PIXEL_MODE_BIT			0x00000020
-#define GL_LIGHTING_BIT				0x00000040
-#define GL_FOG_BIT				0x00000080
-#define GL_DEPTH_BUFFER_BIT			0x00000100
-#define GL_ACCUM_BUFFER_BIT			0x00000200
-#define GL_STENCIL_BUFFER_BIT			0x00000400
-#define GL_VIEWPORT_BIT				0x00000800
-#define GL_TRANSFORM_BIT			0x00001000
-#define GL_ENABLE_BIT				0x00002000
-#define GL_COLOR_BUFFER_BIT			0x00004000
-#define GL_HINT_BIT				0x00008000
-#define GL_EVAL_BIT				0x00010000
-#define GL_LIST_BIT				0x00020000
-#define GL_TEXTURE_BIT				0x00040000
-#define GL_SCISSOR_BIT				0x00080000
-#define GL_ALL_ATTRIB_BITS			0x000FFFFF
+#define GL_CURRENT_BIT              0x00000001
+#define GL_POINT_BIT                0x00000002
+#define GL_LINE_BIT             0x00000004
+#define GL_POLYGON_BIT              0x00000008
+#define GL_POLYGON_STIPPLE_BIT          0x00000010
+#define GL_PIXEL_MODE_BIT           0x00000020
+#define GL_LIGHTING_BIT             0x00000040
+#define GL_FOG_BIT              0x00000080
+#define GL_DEPTH_BUFFER_BIT         0x00000100
+#define GL_ACCUM_BUFFER_BIT         0x00000200
+#define GL_STENCIL_BUFFER_BIT           0x00000400
+#define GL_VIEWPORT_BIT             0x00000800
+#define GL_TRANSFORM_BIT            0x00001000
+#define GL_ENABLE_BIT               0x00002000
+#define GL_COLOR_BUFFER_BIT         0x00004000
+#define GL_HINT_BIT             0x00008000
+#define GL_EVAL_BIT             0x00010000
+#define GL_LIST_BIT             0x00020000
+#define GL_TEXTURE_BIT              0x00040000
+#define GL_SCISSOR_BIT              0x00080000
+#define GL_ALL_ATTRIB_BITS          0x000FFFFF
 
 
 /* OpenGL 1.1 */
-#define GL_PROXY_TEXTURE_1D			0x8063
-#define GL_PROXY_TEXTURE_2D			0x8064
-#define GL_TEXTURE_PRIORITY			0x8066
-#define GL_TEXTURE_RESIDENT			0x8067
-#define GL_TEXTURE_BINDING_1D			0x8068
-#define GL_TEXTURE_BINDING_2D			0x8069
-#define GL_TEXTURE_INTERNAL_FORMAT		0x1003
-#define GL_ALPHA4				0x803B
-#define GL_ALPHA8				0x803C
-#define GL_ALPHA12				0x803D
-#define GL_ALPHA16				0x803E
-#define GL_LUMINANCE4				0x803F
-#define GL_LUMINANCE8				0x8040
-#define GL_LUMINANCE12				0x8041
-#define GL_LUMINANCE16				0x8042
-#define GL_LUMINANCE4_ALPHA4			0x8043
-#define GL_LUMINANCE6_ALPHA2			0x8044
-#define GL_LUMINANCE8_ALPHA8			0x8045
-#define GL_LUMINANCE12_ALPHA4			0x8046
-#define GL_LUMINANCE12_ALPHA12			0x8047
-#define GL_LUMINANCE16_ALPHA16			0x8048
-#define GL_INTENSITY				0x8049
-#define GL_INTENSITY4				0x804A
-#define GL_INTENSITY8				0x804B
-#define GL_INTENSITY12				0x804C
-#define GL_INTENSITY16				0x804D
-#define GL_R3_G3_B2				0x2A10
-#define GL_RGB4					0x804F
-#define GL_RGB5					0x8050
-#define GL_RGB8					0x8051
-#define GL_RGB10				0x8052
-#define GL_RGB12				0x8053
-#define GL_RGB16				0x8054
-#define GL_RGBA2				0x8055
-#define GL_RGBA4				0x8056
-#define GL_RGB5_A1				0x8057
-#define GL_RGBA8				0x8058
-#define GL_RGB10_A2				0x8059
-#define GL_RGBA12				0x805A
-#define GL_RGBA16				0x805B
-#define GL_CLIENT_PIXEL_STORE_BIT		0x00000001
-#define GL_CLIENT_VERTEX_ARRAY_BIT		0x00000002
-#define GL_ALL_CLIENT_ATTRIB_BITS 		0xFFFFFFFF
-#define GL_CLIENT_ALL_ATTRIB_BITS 		0xFFFFFFFF
+#define GL_PROXY_TEXTURE_1D         0x8063
+#define GL_PROXY_TEXTURE_2D         0x8064
+#define GL_TEXTURE_PRIORITY         0x8066
+#define GL_TEXTURE_RESIDENT         0x8067
+#define GL_TEXTURE_BINDING_1D           0x8068
+#define GL_TEXTURE_BINDING_2D           0x8069
+#define GL_TEXTURE_INTERNAL_FORMAT      0x1003
+#define GL_ALPHA4               0x803B
+#define GL_ALPHA8               0x803C
+#define GL_ALPHA12              0x803D
+#define GL_ALPHA16              0x803E
+#define GL_LUMINANCE4               0x803F
+#define GL_LUMINANCE8               0x8040
+#define GL_LUMINANCE12              0x8041
+#define GL_LUMINANCE16              0x8042
+#define GL_LUMINANCE4_ALPHA4            0x8043
+#define GL_LUMINANCE6_ALPHA2            0x8044
+#define GL_LUMINANCE8_ALPHA8            0x8045
+#define GL_LUMINANCE12_ALPHA4           0x8046
+#define GL_LUMINANCE12_ALPHA12          0x8047
+#define GL_LUMINANCE16_ALPHA16          0x8048
+#define GL_INTENSITY                0x8049
+#define GL_INTENSITY4               0x804A
+#define GL_INTENSITY8               0x804B
+#define GL_INTENSITY12              0x804C
+#define GL_INTENSITY16              0x804D
+#define GL_R3_G3_B2             0x2A10
+#define GL_RGB4                 0x804F
+#define GL_RGB5                 0x8050
+#define GL_RGB8                 0x8051
+#define GL_RGB10                0x8052
+#define GL_RGB12                0x8053
+#define GL_RGB16                0x8054
+#define GL_RGBA2                0x8055
+#define GL_RGBA4                0x8056
+#define GL_RGB5_A1              0x8057
+#define GL_RGBA8                0x8058
+#define GL_RGB10_A2             0x8059
+#define GL_RGBA12               0x805A
+#define GL_RGBA16               0x805B
+#define GL_CLIENT_PIXEL_STORE_BIT       0x00000001
+#define GL_CLIENT_VERTEX_ARRAY_BIT      0x00000002
+#define GL_ALL_CLIENT_ATTRIB_BITS       0xFFFFFFFF
+#define GL_CLIENT_ALL_ATTRIB_BITS       0xFFFFFFFF
 
 
 
@@ -1425,13 +1425,13 @@ GLAPI void GLAPIENTRY glMap1f( GLenum target, GLfloat u1, GLfloat u2,
                                GLint order, const GLfloat *points );
 
 GLAPI void GLAPIENTRY glMap2d( GLenum target,
-		     GLdouble u1, GLdouble u2, GLint ustride, GLint uorder,
-		     GLdouble v1, GLdouble v2, GLint vstride, GLint vorder,
-		     const GLdouble *points );
+             GLdouble u1, GLdouble u2, GLint ustride, GLint uorder,
+             GLdouble v1, GLdouble v2, GLint vstride, GLint vorder,
+             const GLdouble *points );
 GLAPI void GLAPIENTRY glMap2f( GLenum target,
-		     GLfloat u1, GLfloat u2, GLint ustride, GLint uorder,
-		     GLfloat v1, GLfloat v2, GLint vstride, GLint vorder,
-		     const GLfloat *points );
+             GLfloat u1, GLfloat u2, GLint ustride, GLint uorder,
+             GLfloat v1, GLfloat v2, GLint vstride, GLint vorder,
+             const GLfloat *points );
 
 GLAPI void GLAPIENTRY glGetMapdv( GLenum target, GLenum query, GLdouble *v );
 GLAPI void GLAPIENTRY glGetMapfv( GLenum target, GLenum query, GLfloat *v );
@@ -1503,50 +1503,50 @@ GLAPI void GLAPIENTRY glPopName( void );
  * OpenGL 1.2
  */
 
-#define GL_RESCALE_NORMAL			0x803A
-#define GL_CLAMP_TO_EDGE			0x812F
-#define GL_MAX_ELEMENTS_VERTICES		0x80E8
-#define GL_MAX_ELEMENTS_INDICES			0x80E9
-#define GL_BGR					0x80E0
-#define GL_BGRA					0x80E1
-#define GL_UNSIGNED_BYTE_3_3_2			0x8032
-#define GL_UNSIGNED_BYTE_2_3_3_REV		0x8362
-#define GL_UNSIGNED_SHORT_5_6_5			0x8363
-#define GL_UNSIGNED_SHORT_5_6_5_REV		0x8364
-#define GL_UNSIGNED_SHORT_4_4_4_4		0x8033
-#define GL_UNSIGNED_SHORT_4_4_4_4_REV		0x8365
-#define GL_UNSIGNED_SHORT_5_5_5_1		0x8034
-#define GL_UNSIGNED_SHORT_1_5_5_5_REV		0x8366
-#define GL_UNSIGNED_INT_8_8_8_8			0x8035
-#define GL_UNSIGNED_INT_8_8_8_8_REV		0x8367
-#define GL_UNSIGNED_INT_10_10_10_2		0x8036
-#define GL_UNSIGNED_INT_2_10_10_10_REV		0x8368
-#define GL_LIGHT_MODEL_COLOR_CONTROL		0x81F8
-#define GL_SINGLE_COLOR				0x81F9
-#define GL_SEPARATE_SPECULAR_COLOR		0x81FA
-#define GL_TEXTURE_MIN_LOD			0x813A
-#define GL_TEXTURE_MAX_LOD			0x813B
-#define GL_TEXTURE_BASE_LEVEL			0x813C
-#define GL_TEXTURE_MAX_LEVEL			0x813D
-#define GL_SMOOTH_POINT_SIZE_RANGE		0x0B12
-#define GL_SMOOTH_POINT_SIZE_GRANULARITY	0x0B13
-#define GL_SMOOTH_LINE_WIDTH_RANGE		0x0B22
-#define GL_SMOOTH_LINE_WIDTH_GRANULARITY	0x0B23
-#define GL_ALIASED_POINT_SIZE_RANGE		0x846D
-#define GL_ALIASED_LINE_WIDTH_RANGE		0x846E
-#define GL_PACK_SKIP_IMAGES			0x806B
-#define GL_PACK_IMAGE_HEIGHT			0x806C
-#define GL_UNPACK_SKIP_IMAGES			0x806D
-#define GL_UNPACK_IMAGE_HEIGHT			0x806E
-#define GL_TEXTURE_3D				0x806F
-#define GL_PROXY_TEXTURE_3D			0x8070
-#define GL_TEXTURE_DEPTH			0x8071
-#define GL_TEXTURE_WRAP_R			0x8072
-#define GL_MAX_3D_TEXTURE_SIZE			0x8073
-#define GL_TEXTURE_BINDING_3D			0x806A
+#define GL_RESCALE_NORMAL           0x803A
+#define GL_CLAMP_TO_EDGE            0x812F
+#define GL_MAX_ELEMENTS_VERTICES        0x80E8
+#define GL_MAX_ELEMENTS_INDICES         0x80E9
+#define GL_BGR                  0x80E0
+#define GL_BGRA                 0x80E1
+#define GL_UNSIGNED_BYTE_3_3_2          0x8032
+#define GL_UNSIGNED_BYTE_2_3_3_REV      0x8362
+#define GL_UNSIGNED_SHORT_5_6_5         0x8363
+#define GL_UNSIGNED_SHORT_5_6_5_REV     0x8364
+#define GL_UNSIGNED_SHORT_4_4_4_4       0x8033
+#define GL_UNSIGNED_SHORT_4_4_4_4_REV       0x8365
+#define GL_UNSIGNED_SHORT_5_5_5_1       0x8034
+#define GL_UNSIGNED_SHORT_1_5_5_5_REV       0x8366
+#define GL_UNSIGNED_INT_8_8_8_8         0x8035
+#define GL_UNSIGNED_INT_8_8_8_8_REV     0x8367
+#define GL_UNSIGNED_INT_10_10_10_2      0x8036
+#define GL_UNSIGNED_INT_2_10_10_10_REV      0x8368
+#define GL_LIGHT_MODEL_COLOR_CONTROL        0x81F8
+#define GL_SINGLE_COLOR             0x81F9
+#define GL_SEPARATE_SPECULAR_COLOR      0x81FA
+#define GL_TEXTURE_MIN_LOD          0x813A
+#define GL_TEXTURE_MAX_LOD          0x813B
+#define GL_TEXTURE_BASE_LEVEL           0x813C
+#define GL_TEXTURE_MAX_LEVEL            0x813D
+#define GL_SMOOTH_POINT_SIZE_RANGE      0x0B12
+#define GL_SMOOTH_POINT_SIZE_GRANULARITY    0x0B13
+#define GL_SMOOTH_LINE_WIDTH_RANGE      0x0B22
+#define GL_SMOOTH_LINE_WIDTH_GRANULARITY    0x0B23
+#define GL_ALIASED_POINT_SIZE_RANGE     0x846D
+#define GL_ALIASED_LINE_WIDTH_RANGE     0x846E
+#define GL_PACK_SKIP_IMAGES         0x806B
+#define GL_PACK_IMAGE_HEIGHT            0x806C
+#define GL_UNPACK_SKIP_IMAGES           0x806D
+#define GL_UNPACK_IMAGE_HEIGHT          0x806E
+#define GL_TEXTURE_3D               0x806F
+#define GL_PROXY_TEXTURE_3D         0x8070
+#define GL_TEXTURE_DEPTH            0x8071
+#define GL_TEXTURE_WRAP_R           0x8072
+#define GL_MAX_3D_TEXTURE_SIZE          0x8073
+#define GL_TEXTURE_BINDING_3D           0x806A
 
 GLAPI void GLAPIENTRY glDrawRangeElements( GLenum mode, GLuint start,
-	GLuint end, GLsizei count, GLenum type, const GLvoid *indices );
+    GLuint end, GLsizei count, GLenum type, const GLvoid *indices );
 
 GLAPI void GLAPIENTRY glTexImage3D( GLenum target, GLint level,
                                       GLint internalFormat,
@@ -1578,81 +1578,81 @@ typedef void (APIENTRYP PFNGLCOPYTEXSUBIMAGE3DPROC) (GLenum target, GLint level,
  * GL_ARB_imaging
  */
 
-#define GL_CONSTANT_COLOR			0x8001
-#define GL_ONE_MINUS_CONSTANT_COLOR		0x8002
-#define GL_CONSTANT_ALPHA			0x8003
-#define GL_ONE_MINUS_CONSTANT_ALPHA		0x8004
-#define GL_COLOR_TABLE				0x80D0
-#define GL_POST_CONVOLUTION_COLOR_TABLE		0x80D1
-#define GL_POST_COLOR_MATRIX_COLOR_TABLE	0x80D2
-#define GL_PROXY_COLOR_TABLE			0x80D3
-#define GL_PROXY_POST_CONVOLUTION_COLOR_TABLE	0x80D4
-#define GL_PROXY_POST_COLOR_MATRIX_COLOR_TABLE	0x80D5
-#define GL_COLOR_TABLE_SCALE			0x80D6
-#define GL_COLOR_TABLE_BIAS			0x80D7
-#define GL_COLOR_TABLE_FORMAT			0x80D8
-#define GL_COLOR_TABLE_WIDTH			0x80D9
-#define GL_COLOR_TABLE_RED_SIZE			0x80DA
-#define GL_COLOR_TABLE_GREEN_SIZE		0x80DB
-#define GL_COLOR_TABLE_BLUE_SIZE		0x80DC
-#define GL_COLOR_TABLE_ALPHA_SIZE		0x80DD
-#define GL_COLOR_TABLE_LUMINANCE_SIZE		0x80DE
-#define GL_COLOR_TABLE_INTENSITY_SIZE		0x80DF
-#define GL_CONVOLUTION_1D			0x8010
-#define GL_CONVOLUTION_2D			0x8011
-#define GL_SEPARABLE_2D				0x8012
-#define GL_CONVOLUTION_BORDER_MODE		0x8013
-#define GL_CONVOLUTION_FILTER_SCALE		0x8014
-#define GL_CONVOLUTION_FILTER_BIAS		0x8015
-#define GL_REDUCE				0x8016
-#define GL_CONVOLUTION_FORMAT			0x8017
-#define GL_CONVOLUTION_WIDTH			0x8018
-#define GL_CONVOLUTION_HEIGHT			0x8019
-#define GL_MAX_CONVOLUTION_WIDTH		0x801A
-#define GL_MAX_CONVOLUTION_HEIGHT		0x801B
-#define GL_POST_CONVOLUTION_RED_SCALE		0x801C
-#define GL_POST_CONVOLUTION_GREEN_SCALE		0x801D
-#define GL_POST_CONVOLUTION_BLUE_SCALE		0x801E
-#define GL_POST_CONVOLUTION_ALPHA_SCALE		0x801F
-#define GL_POST_CONVOLUTION_RED_BIAS		0x8020
-#define GL_POST_CONVOLUTION_GREEN_BIAS		0x8021
-#define GL_POST_CONVOLUTION_BLUE_BIAS		0x8022
-#define GL_POST_CONVOLUTION_ALPHA_BIAS		0x8023
-#define GL_CONSTANT_BORDER			0x8151
-#define GL_REPLICATE_BORDER			0x8153
-#define GL_CONVOLUTION_BORDER_COLOR		0x8154
-#define GL_COLOR_MATRIX				0x80B1
-#define GL_COLOR_MATRIX_STACK_DEPTH		0x80B2
-#define GL_MAX_COLOR_MATRIX_STACK_DEPTH		0x80B3
-#define GL_POST_COLOR_MATRIX_RED_SCALE		0x80B4
-#define GL_POST_COLOR_MATRIX_GREEN_SCALE	0x80B5
-#define GL_POST_COLOR_MATRIX_BLUE_SCALE		0x80B6
-#define GL_POST_COLOR_MATRIX_ALPHA_SCALE	0x80B7
-#define GL_POST_COLOR_MATRIX_RED_BIAS		0x80B8
-#define GL_POST_COLOR_MATRIX_GREEN_BIAS		0x80B9
-#define GL_POST_COLOR_MATRIX_BLUE_BIAS		0x80BA
-#define GL_POST_COLOR_MATRIX_ALPHA_BIAS		0x80BB
-#define GL_HISTOGRAM				0x8024
-#define GL_PROXY_HISTOGRAM			0x8025
-#define GL_HISTOGRAM_WIDTH			0x8026
-#define GL_HISTOGRAM_FORMAT			0x8027
-#define GL_HISTOGRAM_RED_SIZE			0x8028
-#define GL_HISTOGRAM_GREEN_SIZE			0x8029
-#define GL_HISTOGRAM_BLUE_SIZE			0x802A
-#define GL_HISTOGRAM_ALPHA_SIZE			0x802B
-#define GL_HISTOGRAM_LUMINANCE_SIZE		0x802C
-#define GL_HISTOGRAM_SINK			0x802D
-#define GL_MINMAX				0x802E
-#define GL_MINMAX_FORMAT			0x802F
-#define GL_MINMAX_SINK				0x8030
-#define GL_TABLE_TOO_LARGE			0x8031
-#define GL_BLEND_EQUATION			0x8009
-#define GL_MIN					0x8007
-#define GL_MAX					0x8008
-#define GL_FUNC_ADD				0x8006
-#define GL_FUNC_SUBTRACT			0x800A
-#define GL_FUNC_REVERSE_SUBTRACT		0x800B
-#define GL_BLEND_COLOR				0x8005
+#define GL_CONSTANT_COLOR           0x8001
+#define GL_ONE_MINUS_CONSTANT_COLOR     0x8002
+#define GL_CONSTANT_ALPHA           0x8003
+#define GL_ONE_MINUS_CONSTANT_ALPHA     0x8004
+#define GL_COLOR_TABLE              0x80D0
+#define GL_POST_CONVOLUTION_COLOR_TABLE     0x80D1
+#define GL_POST_COLOR_MATRIX_COLOR_TABLE    0x80D2
+#define GL_PROXY_COLOR_TABLE            0x80D3
+#define GL_PROXY_POST_CONVOLUTION_COLOR_TABLE   0x80D4
+#define GL_PROXY_POST_COLOR_MATRIX_COLOR_TABLE  0x80D5
+#define GL_COLOR_TABLE_SCALE            0x80D6
+#define GL_COLOR_TABLE_BIAS         0x80D7
+#define GL_COLOR_TABLE_FORMAT           0x80D8
+#define GL_COLOR_TABLE_WIDTH            0x80D9
+#define GL_COLOR_TABLE_RED_SIZE         0x80DA
+#define GL_COLOR_TABLE_GREEN_SIZE       0x80DB
+#define GL_COLOR_TABLE_BLUE_SIZE        0x80DC
+#define GL_COLOR_TABLE_ALPHA_SIZE       0x80DD
+#define GL_COLOR_TABLE_LUMINANCE_SIZE       0x80DE
+#define GL_COLOR_TABLE_INTENSITY_SIZE       0x80DF
+#define GL_CONVOLUTION_1D           0x8010
+#define GL_CONVOLUTION_2D           0x8011
+#define GL_SEPARABLE_2D             0x8012
+#define GL_CONVOLUTION_BORDER_MODE      0x8013
+#define GL_CONVOLUTION_FILTER_SCALE     0x8014
+#define GL_CONVOLUTION_FILTER_BIAS      0x8015
+#define GL_REDUCE               0x8016
+#define GL_CONVOLUTION_FORMAT           0x8017
+#define GL_CONVOLUTION_WIDTH            0x8018
+#define GL_CONVOLUTION_HEIGHT           0x8019
+#define GL_MAX_CONVOLUTION_WIDTH        0x801A
+#define GL_MAX_CONVOLUTION_HEIGHT       0x801B
+#define GL_POST_CONVOLUTION_RED_SCALE       0x801C
+#define GL_POST_CONVOLUTION_GREEN_SCALE     0x801D
+#define GL_POST_CONVOLUTION_BLUE_SCALE      0x801E
+#define GL_POST_CONVOLUTION_ALPHA_SCALE     0x801F
+#define GL_POST_CONVOLUTION_RED_BIAS        0x8020
+#define GL_POST_CONVOLUTION_GREEN_BIAS      0x8021
+#define GL_POST_CONVOLUTION_BLUE_BIAS       0x8022
+#define GL_POST_CONVOLUTION_ALPHA_BIAS      0x8023
+#define GL_CONSTANT_BORDER          0x8151
+#define GL_REPLICATE_BORDER         0x8153
+#define GL_CONVOLUTION_BORDER_COLOR     0x8154
+#define GL_COLOR_MATRIX             0x80B1
+#define GL_COLOR_MATRIX_STACK_DEPTH     0x80B2
+#define GL_MAX_COLOR_MATRIX_STACK_DEPTH     0x80B3
+#define GL_POST_COLOR_MATRIX_RED_SCALE      0x80B4
+#define GL_POST_COLOR_MATRIX_GREEN_SCALE    0x80B5
+#define GL_POST_COLOR_MATRIX_BLUE_SCALE     0x80B6
+#define GL_POST_COLOR_MATRIX_ALPHA_SCALE    0x80B7
+#define GL_POST_COLOR_MATRIX_RED_BIAS       0x80B8
+#define GL_POST_COLOR_MATRIX_GREEN_BIAS     0x80B9
+#define GL_POST_COLOR_MATRIX_BLUE_BIAS      0x80BA
+#define GL_POST_COLOR_MATRIX_ALPHA_BIAS     0x80BB
+#define GL_HISTOGRAM                0x8024
+#define GL_PROXY_HISTOGRAM          0x8025
+#define GL_HISTOGRAM_WIDTH          0x8026
+#define GL_HISTOGRAM_FORMAT         0x8027
+#define GL_HISTOGRAM_RED_SIZE           0x8028
+#define GL_HISTOGRAM_GREEN_SIZE         0x8029
+#define GL_HISTOGRAM_BLUE_SIZE          0x802A
+#define GL_HISTOGRAM_ALPHA_SIZE         0x802B
+#define GL_HISTOGRAM_LUMINANCE_SIZE     0x802C
+#define GL_HISTOGRAM_SINK           0x802D
+#define GL_MINMAX               0x802E
+#define GL_MINMAX_FORMAT            0x802F
+#define GL_MINMAX_SINK              0x8030
+#define GL_TABLE_TOO_LARGE          0x8031
+#define GL_BLEND_EQUATION           0x8009
+#define GL_MIN                  0x8007
+#define GL_MAX                  0x8008
+#define GL_FUNC_ADD             0x8006
+#define GL_FUNC_SUBTRACT            0x800A
+#define GL_FUNC_REVERSE_SUBTRACT        0x800B
+#define GL_BLEND_COLOR              0x8005
 
 
 GLAPI void GLAPIENTRY glColorTable( GLenum target, GLenum internalformat,
@@ -1691,22 +1691,22 @@ GLAPI void GLAPIENTRY glBlendColor( GLclampf red, GLclampf green,
                                     GLclampf blue, GLclampf alpha );
 
 GLAPI void GLAPIENTRY glHistogram( GLenum target, GLsizei width,
-				   GLenum internalformat, GLboolean sink );
+                   GLenum internalformat, GLboolean sink );
 
 GLAPI void GLAPIENTRY glResetHistogram( GLenum target );
 
 GLAPI void GLAPIENTRY glGetHistogram( GLenum target, GLboolean reset,
-				      GLenum format, GLenum type,
-				      GLvoid *values );
+                      GLenum format, GLenum type,
+                      GLvoid *values );
 
 GLAPI void GLAPIENTRY glGetHistogramParameterfv( GLenum target, GLenum pname,
-						 GLfloat *params );
+                         GLfloat *params );
 
 GLAPI void GLAPIENTRY glGetHistogramParameteriv( GLenum target, GLenum pname,
-						 GLint *params );
+                         GLint *params );
 
 GLAPI void GLAPIENTRY glMinmax( GLenum target, GLenum internalformat,
-				GLboolean sink );
+                GLboolean sink );
 
 GLAPI void GLAPIENTRY glResetMinmax( GLenum target );
 
@@ -1715,53 +1715,53 @@ GLAPI void GLAPIENTRY glGetMinmax( GLenum target, GLboolean reset,
                                    GLvoid *values );
 
 GLAPI void GLAPIENTRY glGetMinmaxParameterfv( GLenum target, GLenum pname,
-					      GLfloat *params );
+                          GLfloat *params );
 
 GLAPI void GLAPIENTRY glGetMinmaxParameteriv( GLenum target, GLenum pname,
-					      GLint *params );
+                          GLint *params );
 
 GLAPI void GLAPIENTRY glConvolutionFilter1D( GLenum target,
-	GLenum internalformat, GLsizei width, GLenum format, GLenum type,
-	const GLvoid *image );
+    GLenum internalformat, GLsizei width, GLenum format, GLenum type,
+    const GLvoid *image );
 
 GLAPI void GLAPIENTRY glConvolutionFilter2D( GLenum target,
-	GLenum internalformat, GLsizei width, GLsizei height, GLenum format,
-	GLenum type, const GLvoid *image );
+    GLenum internalformat, GLsizei width, GLsizei height, GLenum format,
+    GLenum type, const GLvoid *image );
 
 GLAPI void GLAPIENTRY glConvolutionParameterf( GLenum target, GLenum pname,
-	GLfloat params );
+    GLfloat params );
 
 GLAPI void GLAPIENTRY glConvolutionParameterfv( GLenum target, GLenum pname,
-	const GLfloat *params );
+    const GLfloat *params );
 
 GLAPI void GLAPIENTRY glConvolutionParameteri( GLenum target, GLenum pname,
-	GLint params );
+    GLint params );
 
 GLAPI void GLAPIENTRY glConvolutionParameteriv( GLenum target, GLenum pname,
-	const GLint *params );
+    const GLint *params );
 
 GLAPI void GLAPIENTRY glCopyConvolutionFilter1D( GLenum target,
-	GLenum internalformat, GLint x, GLint y, GLsizei width );
+    GLenum internalformat, GLint x, GLint y, GLsizei width );
 
 GLAPI void GLAPIENTRY glCopyConvolutionFilter2D( GLenum target,
-	GLenum internalformat, GLint x, GLint y, GLsizei width,
-	GLsizei height);
+    GLenum internalformat, GLint x, GLint y, GLsizei width,
+    GLsizei height);
 
 GLAPI void GLAPIENTRY glGetConvolutionFilter( GLenum target, GLenum format,
-	GLenum type, GLvoid *image );
+    GLenum type, GLvoid *image );
 
 GLAPI void GLAPIENTRY glGetConvolutionParameterfv( GLenum target, GLenum pname,
-	GLfloat *params );
+    GLfloat *params );
 
 GLAPI void GLAPIENTRY glGetConvolutionParameteriv( GLenum target, GLenum pname,
-	GLint *params );
+    GLint *params );
 
 GLAPI void GLAPIENTRY glSeparableFilter2D( GLenum target,
-	GLenum internalformat, GLsizei width, GLsizei height, GLenum format,
-	GLenum type, const GLvoid *row, const GLvoid *column );
+    GLenum internalformat, GLsizei width, GLsizei height, GLenum format,
+    GLenum type, const GLvoid *row, const GLvoid *column );
 
 GLAPI void GLAPIENTRY glGetSeparableFilter( GLenum target, GLenum format,
-	GLenum type, GLvoid *row, GLvoid *column, GLvoid *span );
+    GLenum type, GLvoid *row, GLvoid *column, GLvoid *span );
 
 
 
@@ -1771,109 +1771,109 @@ GLAPI void GLAPIENTRY glGetSeparableFilter( GLenum target, GLenum format,
  */
 
 /* multitexture */
-#define GL_TEXTURE0				0x84C0
-#define GL_TEXTURE1				0x84C1
-#define GL_TEXTURE2				0x84C2
-#define GL_TEXTURE3				0x84C3
-#define GL_TEXTURE4				0x84C4
-#define GL_TEXTURE5				0x84C5
-#define GL_TEXTURE6				0x84C6
-#define GL_TEXTURE7				0x84C7
-#define GL_TEXTURE8				0x84C8
-#define GL_TEXTURE9				0x84C9
-#define GL_TEXTURE10				0x84CA
-#define GL_TEXTURE11				0x84CB
-#define GL_TEXTURE12				0x84CC
-#define GL_TEXTURE13				0x84CD
-#define GL_TEXTURE14				0x84CE
-#define GL_TEXTURE15				0x84CF
-#define GL_TEXTURE16				0x84D0
-#define GL_TEXTURE17				0x84D1
-#define GL_TEXTURE18				0x84D2
-#define GL_TEXTURE19				0x84D3
-#define GL_TEXTURE20				0x84D4
-#define GL_TEXTURE21				0x84D5
-#define GL_TEXTURE22				0x84D6
-#define GL_TEXTURE23				0x84D7
-#define GL_TEXTURE24				0x84D8
-#define GL_TEXTURE25				0x84D9
-#define GL_TEXTURE26				0x84DA
-#define GL_TEXTURE27				0x84DB
-#define GL_TEXTURE28				0x84DC
-#define GL_TEXTURE29				0x84DD
-#define GL_TEXTURE30				0x84DE
-#define GL_TEXTURE31				0x84DF
-#define GL_ACTIVE_TEXTURE			0x84E0
-#define GL_CLIENT_ACTIVE_TEXTURE		0x84E1
-#define GL_MAX_TEXTURE_UNITS			0x84E2
+#define GL_TEXTURE0             0x84C0
+#define GL_TEXTURE1             0x84C1
+#define GL_TEXTURE2             0x84C2
+#define GL_TEXTURE3             0x84C3
+#define GL_TEXTURE4             0x84C4
+#define GL_TEXTURE5             0x84C5
+#define GL_TEXTURE6             0x84C6
+#define GL_TEXTURE7             0x84C7
+#define GL_TEXTURE8             0x84C8
+#define GL_TEXTURE9             0x84C9
+#define GL_TEXTURE10                0x84CA
+#define GL_TEXTURE11                0x84CB
+#define GL_TEXTURE12                0x84CC
+#define GL_TEXTURE13                0x84CD
+#define GL_TEXTURE14                0x84CE
+#define GL_TEXTURE15                0x84CF
+#define GL_TEXTURE16                0x84D0
+#define GL_TEXTURE17                0x84D1
+#define GL_TEXTURE18                0x84D2
+#define GL_TEXTURE19                0x84D3
+#define GL_TEXTURE20                0x84D4
+#define GL_TEXTURE21                0x84D5
+#define GL_TEXTURE22                0x84D6
+#define GL_TEXTURE23                0x84D7
+#define GL_TEXTURE24                0x84D8
+#define GL_TEXTURE25                0x84D9
+#define GL_TEXTURE26                0x84DA
+#define GL_TEXTURE27                0x84DB
+#define GL_TEXTURE28                0x84DC
+#define GL_TEXTURE29                0x84DD
+#define GL_TEXTURE30                0x84DE
+#define GL_TEXTURE31                0x84DF
+#define GL_ACTIVE_TEXTURE           0x84E0
+#define GL_CLIENT_ACTIVE_TEXTURE        0x84E1
+#define GL_MAX_TEXTURE_UNITS            0x84E2
 /* texture_cube_map */
-#define GL_NORMAL_MAP				0x8511
-#define GL_REFLECTION_MAP			0x8512
-#define GL_TEXTURE_CUBE_MAP			0x8513
-#define GL_TEXTURE_BINDING_CUBE_MAP		0x8514
-#define GL_TEXTURE_CUBE_MAP_POSITIVE_X		0x8515
-#define GL_TEXTURE_CUBE_MAP_NEGATIVE_X		0x8516
-#define GL_TEXTURE_CUBE_MAP_POSITIVE_Y		0x8517
-#define GL_TEXTURE_CUBE_MAP_NEGATIVE_Y		0x8518
-#define GL_TEXTURE_CUBE_MAP_POSITIVE_Z		0x8519
-#define GL_TEXTURE_CUBE_MAP_NEGATIVE_Z		0x851A
-#define GL_PROXY_TEXTURE_CUBE_MAP		0x851B
-#define GL_MAX_CUBE_MAP_TEXTURE_SIZE		0x851C
+#define GL_NORMAL_MAP               0x8511
+#define GL_REFLECTION_MAP           0x8512
+#define GL_TEXTURE_CUBE_MAP         0x8513
+#define GL_TEXTURE_BINDING_CUBE_MAP     0x8514
+#define GL_TEXTURE_CUBE_MAP_POSITIVE_X      0x8515
+#define GL_TEXTURE_CUBE_MAP_NEGATIVE_X      0x8516
+#define GL_TEXTURE_CUBE_MAP_POSITIVE_Y      0x8517
+#define GL_TEXTURE_CUBE_MAP_NEGATIVE_Y      0x8518
+#define GL_TEXTURE_CUBE_MAP_POSITIVE_Z      0x8519
+#define GL_TEXTURE_CUBE_MAP_NEGATIVE_Z      0x851A
+#define GL_PROXY_TEXTURE_CUBE_MAP       0x851B
+#define GL_MAX_CUBE_MAP_TEXTURE_SIZE        0x851C
 /* texture_compression */
-#define GL_COMPRESSED_ALPHA			0x84E9
-#define GL_COMPRESSED_LUMINANCE			0x84EA
-#define GL_COMPRESSED_LUMINANCE_ALPHA		0x84EB
-#define GL_COMPRESSED_INTENSITY			0x84EC
-#define GL_COMPRESSED_RGB			0x84ED
-#define GL_COMPRESSED_RGBA			0x84EE
-#define GL_TEXTURE_COMPRESSION_HINT		0x84EF
-#define GL_TEXTURE_COMPRESSED_IMAGE_SIZE	0x86A0
-#define GL_TEXTURE_COMPRESSED			0x86A1
-#define GL_NUM_COMPRESSED_TEXTURE_FORMATS	0x86A2
-#define GL_COMPRESSED_TEXTURE_FORMATS		0x86A3
+#define GL_COMPRESSED_ALPHA         0x84E9
+#define GL_COMPRESSED_LUMINANCE         0x84EA
+#define GL_COMPRESSED_LUMINANCE_ALPHA       0x84EB
+#define GL_COMPRESSED_INTENSITY         0x84EC
+#define GL_COMPRESSED_RGB           0x84ED
+#define GL_COMPRESSED_RGBA          0x84EE
+#define GL_TEXTURE_COMPRESSION_HINT     0x84EF
+#define GL_TEXTURE_COMPRESSED_IMAGE_SIZE    0x86A0
+#define GL_TEXTURE_COMPRESSED           0x86A1
+#define GL_NUM_COMPRESSED_TEXTURE_FORMATS   0x86A2
+#define GL_COMPRESSED_TEXTURE_FORMATS       0x86A3
 /* multisample */
-#define GL_MULTISAMPLE				0x809D
-#define GL_SAMPLE_ALPHA_TO_COVERAGE		0x809E
-#define GL_SAMPLE_ALPHA_TO_ONE			0x809F
-#define GL_SAMPLE_COVERAGE			0x80A0
-#define GL_SAMPLE_BUFFERS			0x80A8
-#define GL_SAMPLES				0x80A9
-#define GL_SAMPLE_COVERAGE_VALUE		0x80AA
-#define GL_SAMPLE_COVERAGE_INVERT		0x80AB
-#define GL_MULTISAMPLE_BIT			0x20000000
+#define GL_MULTISAMPLE              0x809D
+#define GL_SAMPLE_ALPHA_TO_COVERAGE     0x809E
+#define GL_SAMPLE_ALPHA_TO_ONE          0x809F
+#define GL_SAMPLE_COVERAGE          0x80A0
+#define GL_SAMPLE_BUFFERS           0x80A8
+#define GL_SAMPLES              0x80A9
+#define GL_SAMPLE_COVERAGE_VALUE        0x80AA
+#define GL_SAMPLE_COVERAGE_INVERT       0x80AB
+#define GL_MULTISAMPLE_BIT          0x20000000
 /* transpose_matrix */
-#define GL_TRANSPOSE_MODELVIEW_MATRIX		0x84E3
-#define GL_TRANSPOSE_PROJECTION_MATRIX		0x84E4
-#define GL_TRANSPOSE_TEXTURE_MATRIX		0x84E5
-#define GL_TRANSPOSE_COLOR_MATRIX		0x84E6
+#define GL_TRANSPOSE_MODELVIEW_MATRIX       0x84E3
+#define GL_TRANSPOSE_PROJECTION_MATRIX      0x84E4
+#define GL_TRANSPOSE_TEXTURE_MATRIX     0x84E5
+#define GL_TRANSPOSE_COLOR_MATRIX       0x84E6
 /* texture_env_combine */
-#define GL_COMBINE				0x8570
-#define GL_COMBINE_RGB				0x8571
-#define GL_COMBINE_ALPHA			0x8572
-#define GL_SOURCE0_RGB				0x8580
-#define GL_SOURCE1_RGB				0x8581
-#define GL_SOURCE2_RGB				0x8582
-#define GL_SOURCE0_ALPHA			0x8588
-#define GL_SOURCE1_ALPHA			0x8589
-#define GL_SOURCE2_ALPHA			0x858A
-#define GL_OPERAND0_RGB				0x8590
-#define GL_OPERAND1_RGB				0x8591
-#define GL_OPERAND2_RGB				0x8592
-#define GL_OPERAND0_ALPHA			0x8598
-#define GL_OPERAND1_ALPHA			0x8599
-#define GL_OPERAND2_ALPHA			0x859A
-#define GL_RGB_SCALE				0x8573
-#define GL_ADD_SIGNED				0x8574
-#define GL_INTERPOLATE				0x8575
-#define GL_SUBTRACT				0x84E7
-#define GL_CONSTANT				0x8576
-#define GL_PRIMARY_COLOR			0x8577
-#define GL_PREVIOUS				0x8578
+#define GL_COMBINE              0x8570
+#define GL_COMBINE_RGB              0x8571
+#define GL_COMBINE_ALPHA            0x8572
+#define GL_SOURCE0_RGB              0x8580
+#define GL_SOURCE1_RGB              0x8581
+#define GL_SOURCE2_RGB              0x8582
+#define GL_SOURCE0_ALPHA            0x8588
+#define GL_SOURCE1_ALPHA            0x8589
+#define GL_SOURCE2_ALPHA            0x858A
+#define GL_OPERAND0_RGB             0x8590
+#define GL_OPERAND1_RGB             0x8591
+#define GL_OPERAND2_RGB             0x8592
+#define GL_OPERAND0_ALPHA           0x8598
+#define GL_OPERAND1_ALPHA           0x8599
+#define GL_OPERAND2_ALPHA           0x859A
+#define GL_RGB_SCALE                0x8573
+#define GL_ADD_SIGNED               0x8574
+#define GL_INTERPOLATE              0x8575
+#define GL_SUBTRACT             0x84E7
+#define GL_CONSTANT             0x8576
+#define GL_PRIMARY_COLOR            0x8577
+#define GL_PREVIOUS             0x8578
 /* texture_env_dot3 */
-#define GL_DOT3_RGB				0x86AE
-#define GL_DOT3_RGBA				0x86AF
+#define GL_DOT3_RGB             0x86AE
+#define GL_DOT3_RGBA                0x86AF
 /* texture_border_clamp */
-#define GL_CLAMP_TO_BORDER			0x812D
+#define GL_CLAMP_TO_BORDER          0x812D
 
 GLAPI void GLAPIENTRY glActiveTexture( GLenum texture );
 
@@ -1987,41 +1987,41 @@ typedef void (APIENTRYP PFNGLGETCOMPRESSEDTEXIMAGEPROC) (GLenum target, GLint le
 #ifndef GL_ARB_multitexture
 #define GL_ARB_multitexture 1
 
-#define GL_TEXTURE0_ARB				0x84C0
-#define GL_TEXTURE1_ARB				0x84C1
-#define GL_TEXTURE2_ARB				0x84C2
-#define GL_TEXTURE3_ARB				0x84C3
-#define GL_TEXTURE4_ARB				0x84C4
-#define GL_TEXTURE5_ARB				0x84C5
-#define GL_TEXTURE6_ARB				0x84C6
-#define GL_TEXTURE7_ARB				0x84C7
-#define GL_TEXTURE8_ARB				0x84C8
-#define GL_TEXTURE9_ARB				0x84C9
-#define GL_TEXTURE10_ARB			0x84CA
-#define GL_TEXTURE11_ARB			0x84CB
-#define GL_TEXTURE12_ARB			0x84CC
-#define GL_TEXTURE13_ARB			0x84CD
-#define GL_TEXTURE14_ARB			0x84CE
-#define GL_TEXTURE15_ARB			0x84CF
-#define GL_TEXTURE16_ARB			0x84D0
-#define GL_TEXTURE17_ARB			0x84D1
-#define GL_TEXTURE18_ARB			0x84D2
-#define GL_TEXTURE19_ARB			0x84D3
-#define GL_TEXTURE20_ARB			0x84D4
-#define GL_TEXTURE21_ARB			0x84D5
-#define GL_TEXTURE22_ARB			0x84D6
-#define GL_TEXTURE23_ARB			0x84D7
-#define GL_TEXTURE24_ARB			0x84D8
-#define GL_TEXTURE25_ARB			0x84D9
-#define GL_TEXTURE26_ARB			0x84DA
-#define GL_TEXTURE27_ARB			0x84DB
-#define GL_TEXTURE28_ARB			0x84DC
-#define GL_TEXTURE29_ARB			0x84DD
-#define GL_TEXTURE30_ARB			0x84DE
-#define GL_TEXTURE31_ARB			0x84DF
-#define GL_ACTIVE_TEXTURE_ARB			0x84E0
-#define GL_CLIENT_ACTIVE_TEXTURE_ARB		0x84E1
-#define GL_MAX_TEXTURE_UNITS_ARB		0x84E2
+#define GL_TEXTURE0_ARB             0x84C0
+#define GL_TEXTURE1_ARB             0x84C1
+#define GL_TEXTURE2_ARB             0x84C2
+#define GL_TEXTURE3_ARB             0x84C3
+#define GL_TEXTURE4_ARB             0x84C4
+#define GL_TEXTURE5_ARB             0x84C5
+#define GL_TEXTURE6_ARB             0x84C6
+#define GL_TEXTURE7_ARB             0x84C7
+#define GL_TEXTURE8_ARB             0x84C8
+#define GL_TEXTURE9_ARB             0x84C9
+#define GL_TEXTURE10_ARB            0x84CA
+#define GL_TEXTURE11_ARB            0x84CB
+#define GL_TEXTURE12_ARB            0x84CC
+#define GL_TEXTURE13_ARB            0x84CD
+#define GL_TEXTURE14_ARB            0x84CE
+#define GL_TEXTURE15_ARB            0x84CF
+#define GL_TEXTURE16_ARB            0x84D0
+#define GL_TEXTURE17_ARB            0x84D1
+#define GL_TEXTURE18_ARB            0x84D2
+#define GL_TEXTURE19_ARB            0x84D3
+#define GL_TEXTURE20_ARB            0x84D4
+#define GL_TEXTURE21_ARB            0x84D5
+#define GL_TEXTURE22_ARB            0x84D6
+#define GL_TEXTURE23_ARB            0x84D7
+#define GL_TEXTURE24_ARB            0x84D8
+#define GL_TEXTURE25_ARB            0x84D9
+#define GL_TEXTURE26_ARB            0x84DA
+#define GL_TEXTURE27_ARB            0x84DB
+#define GL_TEXTURE28_ARB            0x84DC
+#define GL_TEXTURE29_ARB            0x84DD
+#define GL_TEXTURE30_ARB            0x84DE
+#define GL_TEXTURE31_ARB            0x84DF
+#define GL_ACTIVE_TEXTURE_ARB           0x84E0
+#define GL_CLIENT_ACTIVE_TEXTURE_ARB        0x84E1
+#define GL_MAX_TEXTURE_UNITS_ARB        0x84E2
 
 GLAPI void GLAPIENTRY glActiveTextureARB(GLenum texture);
 GLAPI void GLAPIENTRY glClientActiveTextureARB(GLenum texture);
@@ -2114,11 +2114,11 @@ typedef void (APIENTRYP PFNGLMULTITEXCOORD4SVARBPROC) (GLenum target, const GLsh
 #ifndef GL_MESA_packed_depth_stencil
 #define GL_MESA_packed_depth_stencil 1
 
-#define GL_DEPTH_STENCIL_MESA			0x8750
-#define GL_UNSIGNED_INT_24_8_MESA		0x8751
-#define GL_UNSIGNED_INT_8_24_REV_MESA		0x8752
-#define GL_UNSIGNED_SHORT_15_1_MESA		0x8753
-#define GL_UNSIGNED_SHORT_1_15_REV_MESA		0x8754
+#define GL_DEPTH_STENCIL_MESA           0x8750
+#define GL_UNSIGNED_INT_24_8_MESA       0x8751
+#define GL_UNSIGNED_INT_8_24_REV_MESA       0x8752
+#define GL_UNSIGNED_SHORT_15_1_MESA     0x8753
+#define GL_UNSIGNED_SHORT_1_15_REV_MESA     0x8754
 
 #endif /* GL_MESA_packed_depth_stencil */
 
@@ -2126,7 +2126,7 @@ typedef void (APIENTRYP PFNGLMULTITEXCOORD4SVARBPROC) (GLenum target, const GLsh
 #ifndef GL_ATI_blend_equation_separate
 #define GL_ATI_blend_equation_separate 1
 
-#define GL_ALPHA_BLEND_EQUATION_ATI	        0x883D
+#define GL_ALPHA_BLEND_EQUATION_ATI         0x883D
 
 GLAPI void GLAPIENTRY glBlendEquationSeparateATI( GLenum modeRGB, GLenum modeA );
 typedef void (APIENTRYP PFNGLBLENDEQUATIONSEPARATEATIPROC) (GLenum modeRGB, GLenum modeA);
diff --git a/bsp/simulator/SDL2-2.0.7/include/SDL_opengles2_gl2ext.h b/bsp/simulator/SDL2-2.0.7/include/SDL_opengles2_gl2ext.h
index e8ca8b13f1..7ed16f5300 100644
--- a/bsp/simulator/SDL2-2.0.7/include/SDL_opengles2_gl2ext.h
+++ b/bsp/simulator/SDL2-2.0.7/include/SDL_opengles2_gl2ext.h
@@ -1535,7 +1535,7 @@ typedef void (GL_APIENTRYP PFNGLFLUSHMAPPEDBUFFERRANGEEXTPROC) (GLenum target, G
 #ifndef GL_EXT_multisampled_render_to_texture
 #define GL_EXT_multisampled_render_to_texture 1
 #ifdef GL_GLEXT_PROTOTYPES
-GL_APICALL void GL_APIENTRY glRenderbufferStorageMultisampleEXT (GLenum target, GLsizei samples, GLenum internalformat, GLsizei width, GLsizei height);             
+GL_APICALL void GL_APIENTRY glRenderbufferStorageMultisampleEXT (GLenum target, GLsizei samples, GLenum internalformat, GLsizei width, GLsizei height);
 GL_APICALL void GL_APIENTRY glFramebufferTexture2DMultisampleEXT (GLenum target, GLenum attachment, GLenum textarget, GLuint texture, GLint level, GLsizei samples);
 #endif
 typedef void (GL_APIENTRYP PFNGLRENDERBUFFERSTORAGEMULTISAMPLEEXTPROC) (GLenum target, GLsizei samples, GLenum internalformat, GLsizei width, GLsizei height);
diff --git a/bsp/simulator/SDL2-2.0.7/include/SDL_opengles2_khrplatform.h b/bsp/simulator/SDL2-2.0.7/include/SDL_opengles2_khrplatform.h
index c9e6f17d34..43aac97a73 100644
--- a/bsp/simulator/SDL2-2.0.7/include/SDL_opengles2_khrplatform.h
+++ b/bsp/simulator/SDL2-2.0.7/include/SDL_opengles2_khrplatform.h
@@ -223,7 +223,7 @@ typedef signed   short int     khronos_int16_t;
 typedef unsigned short int     khronos_uint16_t;
 
 /*
- * Types that differ between LLP64 and LP64 architectures - in LLP64, 
+ * Types that differ between LLP64 and LP64 architectures - in LLP64,
  * pointers are 64 bits, but 'long' is still 32 bits. Win64 appears
  * to be the only LLP64 architecture in current use.
  */
diff --git a/bsp/simulator/SDL2-2.0.7/include/SDL_system.h b/bsp/simulator/SDL2-2.0.7/include/SDL_system.h
index eb069b33d8..53075c2c78 100644
--- a/bsp/simulator/SDL2-2.0.7/include/SDL_system.h
+++ b/bsp/simulator/SDL2-2.0.7/include/SDL_system.h
@@ -42,7 +42,7 @@ extern "C" {
 
 /* Platform specific functions for Windows */
 #ifdef __WIN32__
-	
+
 /**
    \brief Set a function that is called for every windows message, before TranslateMessage()
 */
diff --git a/bsp/simulator/SDL2-2.0.7/include/SDL_test_memory.h b/bsp/simulator/SDL2-2.0.7/include/SDL_test_memory.h
index 43b67f521b..424d7eea7a 100644
--- a/bsp/simulator/SDL2-2.0.7/include/SDL_test_memory.h
+++ b/bsp/simulator/SDL2-2.0.7/include/SDL_test_memory.h
@@ -39,7 +39,7 @@ extern "C" {
 
 /**
  * \brief Start tracking SDL memory allocations
- * 
+ *
  * \note This should be called before any other SDL functions for complete tracking coverage
  */
 int SDLTest_TrackAllocations();
diff --git a/bsp/simulator/SDL2-2.0.7/include/SDL_thread.h b/bsp/simulator/SDL2-2.0.7/include/SDL_thread.h
index d0f6575cd5..204cfe12aa 100644
--- a/bsp/simulator/SDL2-2.0.7/include/SDL_thread.h
+++ b/bsp/simulator/SDL2-2.0.7/include/SDL_thread.h
@@ -246,7 +246,7 @@ extern DECLSPEC void SDLCALL SDL_DetachThread(SDL_Thread * thread);
  *  \code
  *  static SDL_SpinLock tls_lock;
  *  static SDL_TLSID thread_local_storage;
- * 
+ *
  *  void SetMyThreadData(void *value)
  *  {
  *      if (!thread_local_storage) {
@@ -258,7 +258,7 @@ extern DECLSPEC void SDLCALL SDL_DetachThread(SDL_Thread * thread);
  *      }
  *      SDL_TLSSet(thread_local_storage, value, 0);
  *  }
- *  
+ *
  *  void *GetMyThreadData(void)
  *  {
  *      return SDL_TLSGet(thread_local_storage);
diff --git a/bsp/simulator/SDL2-2.0.7/include/SDL_vulkan.h b/bsp/simulator/SDL2-2.0.7/include/SDL_vulkan.h
index 803b5feef3..52d781135b 100644
--- a/bsp/simulator/SDL2-2.0.7/include/SDL_vulkan.h
+++ b/bsp/simulator/SDL2-2.0.7/include/SDL_vulkan.h
@@ -187,9 +187,9 @@ extern DECLSPEC void SDLCALL SDL_Vulkan_UnloadLibrary(void);
  *  \sa SDL_Vulkan_CreateSurface()
  */
 extern DECLSPEC SDL_bool SDLCALL SDL_Vulkan_GetInstanceExtensions(
-														SDL_Window *window,
-														unsigned int *pCount,
-														const char **pNames);
+                                                        SDL_Window *window,
+                                                        unsigned int *pCount,
+                                                        const char **pNames);
 
 /**
  *  \brief Create a Vulkan rendering surface for a window.
@@ -221,9 +221,9 @@ extern DECLSPEC SDL_bool SDLCALL SDL_Vulkan_GetInstanceExtensions(
  *  \sa SDL_Vulkan_GetInstanceExtensions()
  */
 extern DECLSPEC SDL_bool SDLCALL SDL_Vulkan_CreateSurface(
-												SDL_Window *window,
-												VkInstance instance,
-												VkSurfaceKHR* surface);
+                                                SDL_Window *window,
+                                                VkInstance instance,
+                                                VkSurfaceKHR* surface);
 
 /**
  *  \brief Get the size of a window's underlying drawable in pixels (for use
diff --git a/bsp/simulator/applications/application.c b/bsp/simulator/applications/application.c
index 656da63f61..7fb2109693 100755
--- a/bsp/simulator/applications/application.c
+++ b/bsp/simulator/applications/application.c
@@ -1,62 +1,18 @@
 /*
- * File      : application.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2009-01-05     Bernard      the first version
  */
-
 #include 
 #include 
 #include 
 
-extern int platform_init(void);
-extern int platform_post_init(void);
-extern int mnt_init(void);
-
-void rt_init_thread_entry(void *parameter)
+int main(void)
 {
     rt_kprintf("Hello RT-Thread!\n");
-
-    platform_init();
-    mnt_init();
-
-	platform_post_init();
-
-#if defined(PKG_USING_GUIENGINE) && defined(GUIENGINE_USING_DEMO)
-    {
-        extern int rt_gui_demo_init(void);
-        rt_gui_demo_init();
-    }
-#endif
-}
-
-int rt_application_init()
-{
-    rt_thread_t tid;
-
-    tid = rt_thread_create("init",
-                           rt_init_thread_entry, RT_NULL,
-                           2048, RT_THREAD_PRIORITY_MAX / 3, 20);
-
-    if (tid != RT_NULL)
-        rt_thread_startup(tid);
-
     return 0;
 }
diff --git a/bsp/simulator/applications/mnt.c b/bsp/simulator/applications/mnt.c
index 1a531ed2eb..4401a5ed94 100644
--- a/bsp/simulator/applications/mnt.c
+++ b/bsp/simulator/applications/mnt.c
@@ -1,12 +1,12 @@
 /*
- * File      : mnt.c
- * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 201743     Urey         the first version
+ * 2017-04-03     Urey         the first version
  */
-
 #include 
 #include 
 
@@ -15,12 +15,10 @@
 
 int mnt_init(void)
 {
-    dfs_init();
-
 #ifdef RT_USING_DFS_WINSHAREDIR
     extern int dfs_win32_init(void);
     extern rt_err_t rt_win_sharedir_init(const char *name);
-    
+
     dfs_win32_init();
     rt_win_sharedir_init("wshare");
 
@@ -54,5 +52,5 @@ int mnt_init(void)
 
     return 0;
 }
-
+INIT_COMPONENT_EXPORT(mnt_init);
 #endif
diff --git a/bsp/simulator/applications/platform.c b/bsp/simulator/applications/platform.c
index f4b0db41eb..1b7127e370 100644
--- a/bsp/simulator/applications/platform.c
+++ b/bsp/simulator/applications/platform.c
@@ -1,3 +1,11 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
 #include 
 #include "board.h"
 
@@ -5,8 +13,6 @@
 
 int platform_init(void)
 {
-    finsh_system_init();
-
 #ifdef RT_USING_LWIP
 #ifdef RT_USING_TAPNETIF
     tap_netif_hw_init();
@@ -31,6 +37,7 @@ int platform_init(void)
 
     return 0;
 }
+INIT_COMPONENT_EXPORT(platform_init);
 
 int platform_post_init(void)
 {
@@ -43,6 +50,6 @@ int platform_post_init(void)
         rt_hw_sdl_start();
     }
 #endif
-
     return 0;
 }
+INIT_COMPONENT_EXPORT(platform_post_init);
diff --git a/bsp/simulator/applications/startup.c b/bsp/simulator/applications/startup.c
deleted file mode 100644
index 900d774844..0000000000
--- a/bsp/simulator/applications/startup.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2012-09-03     prife        first implementation
- */
-
-#include 
-#include 
-
-#include "board.h"
-
-/**
- * @addtogroup win32
- */
-
-/*@{*/
-
-extern int  rt_application_init(void);
-extern rt_uint8_t *heap;
-
-/**
- * This function will startup RT-Thread RTOS.
- */
-void rtthread_startup(void)
-{
-    /* init board */
-    rt_hw_board_init();
-
-    /* show version */
-    rt_show_version();
-
-    /* init timer system */
-    rt_system_timer_init();
-
-#ifdef RT_USING_HEAP
-    /* init memory system */
-    rt_system_heap_init((void *)heap, (void *)&heap[RT_HEAP_SIZE - 1]);
-#endif
-
-    /* init scheduler system */
-    rt_system_scheduler_init();
-
-    /* init application */
-    rt_application_init();
-
-    /* init timer thread */
-    rt_system_timer_thread_init();
-
-    /* init idle thread */
-    rt_thread_idle_init();
-
-    /* start scheduler */
-    rt_system_scheduler_start();
-
-    /* never reach here */
-    return ;
-}
-
-int main(void)
-{
-    /* disable interrupt first */
-    rt_hw_interrupt_disable();
-
-    /* startup RT-Thread RTOS */
-    rtthread_startup();
-
-    return 0;
-}
-
-/*@}*/
diff --git a/bsp/simulator/drivers/board.c b/bsp/simulator/drivers/board.c
index 2bf10263f2..4facdfa1b2 100755
--- a/bsp/simulator/drivers/board.c
+++ b/bsp/simulator/drivers/board.c
@@ -1,17 +1,12 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2009-01-05     Bernard      first implementation
  */
-
 #include 
 #include 
 
@@ -23,7 +18,6 @@
 /**
  * @addtogroup simulator on win32
  */
-rt_uint8_t *heap;
 
 rt_uint8_t *rt_hw_sram_init(void)
 {
@@ -38,6 +32,10 @@ rt_uint8_t *rt_hw_sram_init(void)
         exit(1);
 #endif
     }
+#ifdef RT_USING_HEAP
+    /* init memory system */
+    rt_system_heap_init((void*)heap, (void*)&heap[RT_HEAP_SIZE - 1]);
+#endif
     return heap;
 }
 
@@ -92,10 +90,10 @@ FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_exit, __cmd_quit, exit rt-thread);
 /**
  * This function will initial win32
  */
-void rt_hw_board_init()
+int rt_hw_board_init(void)
 {
     /* init system memory */
-    heap = rt_hw_sram_init();
+    rt_hw_sram_init();
 
     uart_console_init();
 
@@ -106,5 +104,10 @@ void rt_hw_board_init()
 #if defined(RT_USING_CONSOLE)
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
+    /* init board */
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+    return 0;
 }
 /*@}*/
diff --git a/bsp/simulator/drivers/board.h b/bsp/simulator/drivers/board.h
index 7edb856505..7f2e2d2782 100644
--- a/bsp/simulator/drivers/board.h
+++ b/bsp/simulator/drivers/board.h
@@ -1,20 +1,15 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2009-09-22     Bernard      add board.h to this bsp
  */
-
 #ifndef __BOARD_H__
 #define __BOARD_H__
-void rt_hw_board_init(void);
+int rt_hw_board_init(void);
 rt_uint8_t *rt_hw_sram_init(void);
 
 /* SD Card init function */
diff --git a/bsp/simulator/drivers/dfs_win32.c b/bsp/simulator/drivers/dfs_win32.c
index b275751efb..b910c2bf83 100644
--- a/bsp/simulator/drivers/dfs_win32.c
+++ b/bsp/simulator/drivers/dfs_win32.c
@@ -1,11 +1,7 @@
 /*
- * File      : rtthread.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/simulator/drivers/module_win32.c b/bsp/simulator/drivers/module_win32.c
index 8fcf3ef2fe..81a98eca87 100644
--- a/bsp/simulator/drivers/module_win32.c
+++ b/bsp/simulator/drivers/module_win32.c
@@ -1,11 +1,7 @@
 /*
- * File      : module.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -130,7 +126,7 @@ void rt_module_unload_sethook(void (*hook)(rt_module_t module))
  */
 int rt_system_module_init(void)
 {
-	return 0;
+    return 0;
 }
 
 /**
@@ -240,9 +236,9 @@ rt_module_t rt_module_open(const char *path)
     struct dfs_filesystem *fs;
     appentry_t fptr;
     HINSTANCE hinstlib;
-	rt_module_t module;
+    rt_module_t module;
 
-	char * winpath = RT_NULL;
+    char * winpath = RT_NULL;
     char * name = RT_NULL;
 
     RT_DEBUG_NOT_IN_INTERRUPT;
@@ -353,60 +349,60 @@ FINSH_FUNCTION_EXPORT_ALIAS(rt_module_open, exec, exec module from a file);
 #define RT_MODULE_ARG_MAX    8
 static int _rt_module_split_arg(char* cmd, rt_size_t length, char* argv[])
 {
-	int argc = 0;
-	char *ptr = cmd;
+    int argc = 0;
+    char *ptr = cmd;
 
-	while ((ptr - cmd) < length)
-	{
-		/* strip bank and tab */
-		while ((*ptr == ' ' || *ptr == '\t') && (ptr -cmd)< length)
-			*ptr++ = '\0';
-		/* check whether it's the end of line */
-		if ((ptr - cmd)>= length) break;
+    while ((ptr - cmd) < length)
+    {
+        /* strip bank and tab */
+        while ((*ptr == ' ' || *ptr == '\t') && (ptr -cmd)< length)
+            *ptr++ = '\0';
+        /* check whether it's the end of line */
+        if ((ptr - cmd)>= length) break;
 
-		/* handle string with quote */
-		if (*ptr == '"')
-		{
-			argv[argc++] = ++ptr;
+        /* handle string with quote */
+        if (*ptr == '"')
+        {
+            argv[argc++] = ++ptr;
 
-			/* skip this string */
-			while (*ptr != '"' && (ptr-cmd) < length)
-				if (*ptr ++ == '\\')  ptr ++;
-			if ((ptr - cmd) >= length) break;
+            /* skip this string */
+            while (*ptr != '"' && (ptr-cmd) < length)
+                if (*ptr ++ == '\\')  ptr ++;
+            if ((ptr - cmd) >= length) break;
 
-			/* skip '"' */
-			*ptr ++ = '\0';
-		}
-		else
-		{
-			argv[argc++] = ptr;
-			while ((*ptr != ' ' && *ptr != '\t') && (ptr - cmd) < length)
-				ptr ++;
-		}
+            /* skip '"' */
+            *ptr ++ = '\0';
+        }
+        else
+        {
+            argv[argc++] = ptr;
+            while ((*ptr != ' ' && *ptr != '\t') && (ptr - cmd) < length)
+                ptr ++;
+        }
 
-		if (argc >= RT_MODULE_ARG_MAX) break;
-	}
+        if (argc >= RT_MODULE_ARG_MAX) break;
+    }
 
-	return argc;
+    return argc;
 }
 
 /* module main thread entry */
 static void module_main_entry(void* parameter)
 {
-	int argc;
-	char *argv[RT_MODULE_ARG_MAX];
-	typedef int (*main_func_t)(int argc, char** argv);
+    int argc;
+    char *argv[RT_MODULE_ARG_MAX];
+    typedef int (*main_func_t)(int argc, char** argv);
 
-	rt_module_t module = (rt_module_t) parameter;
-	if (module == RT_NULL || module->module_cmd_line == RT_NULL) return;
+    rt_module_t module = (rt_module_t) parameter;
+    if (module == RT_NULL || module->module_cmd_line == RT_NULL) return;
 
-	rt_memset(argv, 0x00, sizeof(argv));
-	argc = _rt_module_split_arg((char*)module->module_cmd_line, module->module_cmd_size, argv);
-	if (argc == 0) return ;
+    rt_memset(argv, 0x00, sizeof(argv));
+    argc = _rt_module_split_arg((char*)module->module_cmd_line, module->module_cmd_size, argv);
+    if (argc == 0) return ;
 
-	/* do the main function */
-	((main_func_t)module->module_entry)(argc, argv);
-	return;
+    /* do the main function */
+    ((main_func_t)module->module_entry)(argc, argv);
+    return;
 }
 
 /**
@@ -423,25 +419,25 @@ rt_module_t rt_module_exec_cmd(const char *path, const char* cmd_line, int line_
     struct dfs_filesystem *fs;
     appentry_t fptr;
     HINSTANCE hinstlib;
-	rt_module_t module;
+    rt_module_t module;
 
-	char * winpath = RT_NULL;
+    char * winpath = RT_NULL;
     char * name = RT_NULL;
-	char *full_path = RT_NULL;
+    char *full_path = RT_NULL;
 
     RT_DEBUG_NOT_IN_INTERRUPT;
 
     /* check parameters */
     RT_ASSERT(path != RT_NULL);
 
-	if (*path != '/')
-	{
-		full_path = dfs_normalize_path(RT_NULL, path);
-	}
-	else
-	{
-		full_path = (const char*)path;
-	}
+    if (*path != '/')
+    {
+        full_path = dfs_normalize_path(RT_NULL, path);
+    }
+    else
+    {
+        full_path = (const char*)path;
+    }
 
     /* app module should only in DFS_WIN32 */
     fs = dfs_filesystem_lookup(full_path);
@@ -456,14 +452,14 @@ rt_module_t rt_module_exec_cmd(const char *path, const char* cmd_line, int line_
     if ((winpath = dfs_win32_dirdup((char *)full_path)) == RT_NULL)
     {
         rt_kprintf("out of memory, exit", path);
-		goto __exit;
+        goto __exit;
     }
 
     hinstlib = LoadLibrary(winpath);
     if (hinstlib == NULL)
     {
         rt_kprintf("error: unable to open %s\n", winpath);
-		goto __exit;
+        goto __exit;
     }
 
     fptr = (appentry_t)GetProcAddress(hinstlib, "main");
@@ -471,21 +467,21 @@ rt_module_t rt_module_exec_cmd(const char *path, const char* cmd_line, int line_
     {
         rt_kprintf("error: unable to find function in %s\n", winpath);
         FreeLibrary(hinstlib);
-		goto __exit;
+        goto __exit;
     }
 
-	/* release winpath */
-	rt_free(winpath);
+    /* release winpath */
+    rt_free(winpath);
 
     /* get the name of the module */
     name = _module_name(path);
 
     /* allocate module */
     module = (struct rt_module *)rt_object_allocate(RT_Object_Class_Module, name);
-    if (!module) 
-	{
-		goto __exit;
-	}
+    if (!module)
+    {
+        goto __exit;
+    }
 
     module->nref = 0;
     module->module_entry = fptr;
@@ -498,11 +494,11 @@ rt_module_t rt_module_exec_cmd(const char *path, const char* cmd_line, int line_
 
     if (module->module_entry != 0)
     {
-		/* set module argument */
-		module->module_cmd_line = (rt_uint8_t*)rt_malloc(line_size + 1);
-		rt_memcpy(module->module_cmd_line, cmd_line, line_size);
-		module->module_cmd_line[line_size] = '\0';
-		module->module_cmd_size = line_size;
+        /* set module argument */
+        module->module_cmd_line = (rt_uint8_t*)rt_malloc(line_size + 1);
+        rt_memcpy(module->module_cmd_line, cmd_line, line_size);
+        module->module_cmd_line[line_size] = '\0';
+        module->module_cmd_size = line_size;
 
 #ifdef RT_USING_SLAB
         /* init module memory allocator */
@@ -514,10 +510,10 @@ rt_module_t rt_module_exec_cmd(const char *path, const char* cmd_line, int line_
         module->page_cnt = 0;
 #endif
 
-		/* create module thread */
-		module->module_thread =	rt_thread_create(name,
-			module_main_entry, module,
-			2048, RT_THREAD_PRIORITY_MAX - 2, 10);
+        /* create module thread */
+        module->module_thread = rt_thread_create(name,
+            module_main_entry, module,
+            2048, RT_THREAD_PRIORITY_MAX - 2, 10);
 
         /* set module id */
         module->module_thread->module_id = (void *)module;
@@ -543,11 +539,11 @@ rt_module_t rt_module_exec_cmd(const char *path, const char* cmd_line, int line_
     return module;
 
 __exit:
-	if (full_path != path) rt_free(full_path);
-	if (name != RT_NULL)   rt_free(full_path);
-	if (winpath != RT_NULL)rt_free(winpath);
+    if (full_path != path) rt_free(full_path);
+    if (name != RT_NULL)   rt_free(full_path);
+    if (winpath != RT_NULL)rt_free(winpath);
 
-	return RT_NULL;
+    return RT_NULL;
     /* FreeLibrary(hinstlib); */
 }
 
diff --git a/bsp/simulator/drivers/nanddrv_file.c b/bsp/simulator/drivers/nanddrv_file.c
index 075ed7f5d8..c47ffdbbe4 100644
--- a/bsp/simulator/drivers/nanddrv_file.c
+++ b/bsp/simulator/drivers/nanddrv_file.c
@@ -1,3 +1,11 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
 #include 
 #include 
 #include 
diff --git a/bsp/simulator/drivers/sd_sim.c b/bsp/simulator/drivers/sd_sim.c
index b317e5428d..adc489be20 100755
--- a/bsp/simulator/drivers/sd_sim.c
+++ b/bsp/simulator/drivers/sd_sim.c
@@ -1,3 +1,11 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
 #include 
 #include 
 #include 
@@ -125,7 +133,6 @@ static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args)
     return RT_EOK;
 }
 
-
 rt_err_t rt_hw_sdcard_init(const char *spi_device_name)
 {
     int size;
@@ -136,6 +143,11 @@ rt_err_t rt_hw_sdcard_init(const char *spi_device_name)
     device = &(sd->parent);
 
     lock = rt_mutex_create("lock", RT_IPC_FLAG_FIFO);
+    if (lock == RT_NULL) 
+    {
+        LOG_E("Create mutex in rt_hw_sdcard_init failed!");
+        return -RT_ERROR;
+    }
 
     /* open sd card file, if not exist, then create it  */
     sd->file = fopen(SDCARD_SIM, "rb+");
diff --git a/bsp/simulator/drivers/sdl_fb.c b/bsp/simulator/drivers/sdl_fb.c
index 98da565a2a..7b25da9c3c 100755
--- a/bsp/simulator/drivers/sdl_fb.c
+++ b/bsp/simulator/drivers/sdl_fb.c
@@ -1,7 +1,13 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
 #include 
-
 #include 
-
 #ifdef _WIN32
 #include 
 #else
@@ -190,7 +196,7 @@ static void sdlfb_hw_init(void)
         SDL_PixelFormatEnumToMasks(SDL_SCREEN_FORMAT, &bpp, &Rmask, &Gmask,
             &Bmask, &Amask);
 
-        _device.surface = SDL_CreateRGBSurface(0, SDL_SCREEN_WIDTH, SDL_SCREEN_HEIGHT, 
+        _device.surface = SDL_CreateRGBSurface(0, SDL_SCREEN_WIDTH, SDL_SCREEN_HEIGHT,
             bpp, Rmask, Gmask, Bmask, Amask);
     }
 
@@ -215,6 +221,10 @@ static void sdlfb_hw_init(void)
     rt_device_register(RT_DEVICE(&_device), "sdl", RT_DEVICE_FLAG_RDWR);
 
     sdllock = rt_mutex_create("fb", RT_IPC_FLAG_FIFO);
+    if (sdllock == RT_NULL) 
+    {
+        LOG_E("Create mutex for sdlfb failed!");
+    }
 }
 
 #ifdef _WIN32
@@ -255,7 +265,7 @@ static void *sdl_loop(void *lpParam)
     int motion_tick = 50;
 
     int mouse_id = 1;
- 
+
 #ifndef _WIN32
     sigset_t  sigmask, oldmask;
     /* set the getchar without buffer */
@@ -455,7 +465,7 @@ static void *sdl_loop(void *lpParam)
             exit(1);
             break;
         }
-            
+
     }
     rt_hw_exit();
     return 0;
diff --git a/bsp/simulator/drivers/sst25vfxx_mtd.h b/bsp/simulator/drivers/sst25vfxx_mtd.h
index cb0bb84129..202c6884a3 100644
--- a/bsp/simulator/drivers/sst25vfxx_mtd.h
+++ b/bsp/simulator/drivers/sst25vfxx_mtd.h
@@ -1,11 +1,7 @@
 /*
- * File      : sst25vfxx_mtd.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/bsp/simulator/drivers/sst25vfxx_mtd_sim.c b/bsp/simulator/drivers/sst25vfxx_mtd_sim.c
index cd8894f612..4460e1da3b 100644
--- a/bsp/simulator/drivers/sst25vfxx_mtd_sim.c
+++ b/bsp/simulator/drivers/sst25vfxx_mtd_sim.c
@@ -1,11 +1,7 @@
 /*
- * File      : rtdef.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -20,7 +16,7 @@
 
 #ifdef RT_USING_MTD_NOR
 #define NOR_SIM "nor.bin"
-/* JEDEC Manufacturers ID */
+/* JEDEC Manufacturer’s ID */
 #define MF_ID           (0xBF)
 /* JEDEC Device ID : Memory Type */
 #define MT_ID           (0x25)
diff --git a/bsp/simulator/drivers/tap_netif.c b/bsp/simulator/drivers/tap_netif.c
index a8cd865c5e..8bac666cc0 100644
--- a/bsp/simulator/drivers/tap_netif.c
+++ b/bsp/simulator/drivers/tap_netif.c
@@ -33,7 +33,7 @@
 #include 
 
 #define MAX_ADDR_LEN 6
-#define TAP_IFNAME	"RT-net"
+#define TAP_IFNAME  "RT-net"
 
 //=============
 // TAP IOCTLs
@@ -112,13 +112,13 @@ static tap_win32_overlapped_t tap_overlapped;
 /************************************************************************/
 struct tap_netif
 {
-	/* inherit from ethernet device */
-	struct eth_device parent;
+    /* inherit from ethernet device */
+    struct eth_device parent;
 
-	tap_win32_overlapped_t *handle;
+    tap_win32_overlapped_t *handle;
 
-	/* interface address info. */
-	rt_uint8_t  dev_addr[MAX_ADDR_LEN];		/* hw address	*/
+    /* interface address info. */
+    rt_uint8_t  dev_addr[MAX_ADDR_LEN];     /* hw address   */
 };
 #define NETIF_DEVICE(netif) ((struct tap_netif*)(netif))
 #define NETIF_TAP(netif)   (NETIF_DEVICE(netif)->handle)
@@ -505,12 +505,12 @@ static void tap_win32_thread_entry(void* param)
     unsigned long read_size;
     BOOL result;
     DWORD dwError;
-	tun_buffer_t* buffer;
-	struct eth_device* eth;
+    tun_buffer_t* buffer;
+    struct eth_device* eth;
 
-	eth = (struct eth_device*) &tap_netif_device;
-	overlapped = NETIF_TAP(&tap_netif_device);
-	buffer = get_buffer_from_free_list(overlapped);
+    eth = (struct eth_device*) &tap_netif_device;
+    overlapped = NETIF_TAP(&tap_netif_device);
+    buffer = get_buffer_from_free_list(overlapped);
 
     for (;;) {
         result = ReadFile(overlapped->handle,
@@ -548,15 +548,15 @@ static void tap_win32_thread_entry(void* param)
         }
 
         if(read_size > 0) {
-			// rt_kprintf("rx packet, length=%d\n", read_size);
+            // rt_kprintf("rx packet, length=%d\n", read_size);
 
-			buffer->read_size = read_size;
+            buffer->read_size = read_size;
             put_buffer_on_output_queue(overlapped, buffer);
 
-			/* notify eth rx thread to receive packet */
-			eth_device_ready(eth);
+            /* notify eth rx thread to receive packet */
+            eth_device_ready(eth);
 
-			buffer = get_buffer_from_free_list(overlapped);
+            buffer = get_buffer_from_free_list(overlapped);
         }
     }
 }
@@ -649,143 +649,143 @@ static int tap_win32_open(tap_win32_overlapped_t **phandle,
 
 static rt_err_t tap_netif_init(rt_device_t dev)
 {
-	rt_thread_t tid;
-	tap_win32_overlapped_t *handle;
+    rt_thread_t tid;
+    tap_win32_overlapped_t *handle;
 
-	if (tap_win32_open(&handle, TAP_IFNAME) < 0) {
-		printf("tap: Could not open '%s'\n", TAP_IFNAME);
-		return -RT_ERROR;
-	}
+    if (tap_win32_open(&handle, TAP_IFNAME) < 0) {
+        printf("tap: Could not open '%s'\n", TAP_IFNAME);
+        return -RT_ERROR;
+    }
 
-	tap_netif_device.handle = handle;
+    tap_netif_device.handle = handle;
 
-	/* create recv thread */
-	tid = rt_thread_create("tap", tap_win32_thread_entry, RT_NULL, 
-		2048, RT_THREAD_PRIORITY_MAX - 1, 10);
-	if (tid != RT_NULL)
-	{
-		rt_thread_startup(tid);
-	}
+    /* create recv thread */
+    tid = rt_thread_create("tap", tap_win32_thread_entry, RT_NULL,
+        2048, RT_THREAD_PRIORITY_MAX - 1, 10);
+    if (tid != RT_NULL)
+    {
+        rt_thread_startup(tid);
+    }
 
-	rt_thread_sleep(RT_TICK_PER_SECOND);
+    rt_thread_sleep(RT_TICK_PER_SECOND);
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t tap_netif_open(rt_device_t dev, rt_uint16_t oflag)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t tap_netif_close(rt_device_t dev)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_size_t tap_netif_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
 {
-	rt_set_errno(-RT_ENOSYS);
-	return 0;
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
 }
 
 static rt_size_t tap_netif_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
 {
-	rt_set_errno(-RT_ENOSYS);
-	return 0;
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
 }
 
 static rt_err_t tap_netif_control(rt_device_t dev, int cmd, void *args)
 {
-	switch (cmd)
-	{
-	case NIOCTL_GADDR:
-		/* get mac address */
-		if (args) rt_memcpy(args, tap_netif_device.dev_addr, 6);
-		else return -RT_ERROR;
-		break;
+    switch (cmd)
+    {
+    case NIOCTL_GADDR:
+        /* get mac address */
+        if (args) rt_memcpy(args, tap_netif_device.dev_addr, 6);
+        else return -RT_ERROR;
+        break;
 
-	default :
-		break;
-	}
+    default :
+        break;
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 rt_err_t tap_netif_tx( rt_device_t dev, struct pbuf* p)
 {
-	struct pbuf *q;
-	char buffer[2048];
-	int length;
-	tap_win32_overlapped_t *handle;
-	unsigned char* ptr;
+    struct pbuf *q;
+    char buffer[2048];
+    int length;
+    tap_win32_overlapped_t *handle;
+    unsigned char* ptr;
 
-	handle = NETIF_TAP(dev);
+    handle = NETIF_TAP(dev);
 
-	/* lock EMAC device */
-	rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
+    /* lock EMAC device */
+    rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
 
-	/* copy data to tx buffer */
-	q = p;
-	ptr = (rt_uint8_t*)buffer;
-	while (q)
-	{
-		memcpy(ptr, q->payload, q->len);
-		ptr += q->len;
-		q = q->next;
-	}
-	length = p->tot_len;
+    /* copy data to tx buffer */
+    q = p;
+    ptr = (rt_uint8_t*)buffer;
+    while (q)
+    {
+        memcpy(ptr, q->payload, q->len);
+        ptr += q->len;
+        q = q->next;
+    }
+    length = p->tot_len;
 
-	tap_win32_write(handle, buffer, length);
+    tap_win32_write(handle, buffer, length);
 
-	/* unlock EMAC device */
-	rt_sem_release(&sem_lock);
+    /* unlock EMAC device */
+    rt_sem_release(&sem_lock);
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 struct pbuf *tap_netif_rx(rt_device_t dev)
 {
-	struct pbuf* p = RT_NULL;
-	tap_win32_overlapped_t *handle;
-	rt_uint8_t *buf;
-	int max_size = 4096;
-	int size;
+    struct pbuf* p = RT_NULL;
+    tap_win32_overlapped_t *handle;
+    rt_uint8_t *buf;
+    int max_size = 4096;
+    int size;
 
-	handle = NETIF_TAP(dev);
+    handle = NETIF_TAP(dev);
 
-	size = tap_win32_read(handle, &buf, max_size);
-	if (size > 0) {
-		p = pbuf_alloc(PBUF_LINK, size, PBUF_RAM);
-		pbuf_take(p, buf, size);
+    size = tap_win32_read(handle, &buf, max_size);
+    if (size > 0) {
+        p = pbuf_alloc(PBUF_LINK, size, PBUF_RAM);
+        pbuf_take(p, buf, size);
 
-		tap_win32_free_buffer(handle, buf);
-	}
+        tap_win32_free_buffer(handle, buf);
+    }
 
-	return p;
+    return p;
 }
 
 void tap_netif_hw_init(void)
 {
-	rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
+    rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
 
-	tap_netif_device.dev_addr[0] = 0x00;
-	tap_netif_device.dev_addr[1] = 0x60;
-	tap_netif_device.dev_addr[2] = 0x37;
-	/* set mac address: (only for test) */
-	tap_netif_device.dev_addr[3] = 0x12;
-	tap_netif_device.dev_addr[4] = 0x34;
-	tap_netif_device.dev_addr[5] = 0x56;
+    tap_netif_device.dev_addr[0] = 0x00;
+    tap_netif_device.dev_addr[1] = 0x60;
+    tap_netif_device.dev_addr[2] = 0x37;
+    /* set mac address: (only for test) */
+    tap_netif_device.dev_addr[3] = 0x12;
+    tap_netif_device.dev_addr[4] = 0x34;
+    tap_netif_device.dev_addr[5] = 0x56;
 
-	tap_netif_device.parent.parent.init		= tap_netif_init;
-	tap_netif_device.parent.parent.open		= tap_netif_open;
-	tap_netif_device.parent.parent.close	= tap_netif_close;
-	tap_netif_device.parent.parent.read		= tap_netif_read;
-	tap_netif_device.parent.parent.write	= tap_netif_write;
-	tap_netif_device.parent.parent.control	= tap_netif_control;
-	tap_netif_device.parent.parent.user_data= RT_NULL;
+    tap_netif_device.parent.parent.init     = tap_netif_init;
+    tap_netif_device.parent.parent.open     = tap_netif_open;
+    tap_netif_device.parent.parent.close    = tap_netif_close;
+    tap_netif_device.parent.parent.read     = tap_netif_read;
+    tap_netif_device.parent.parent.write    = tap_netif_write;
+    tap_netif_device.parent.parent.control  = tap_netif_control;
+    tap_netif_device.parent.parent.user_data= RT_NULL;
 
-	tap_netif_device.parent.eth_rx			= tap_netif_rx;
-	tap_netif_device.parent.eth_tx			= tap_netif_tx;
+    tap_netif_device.parent.eth_rx          = tap_netif_rx;
+    tap_netif_device.parent.eth_tx          = tap_netif_tx;
 
-	eth_device_init(&(tap_netif_device.parent), "e0");
+    eth_device_init(&(tap_netif_device.parent), "e0");
 }
diff --git a/bsp/simulator/drivers/uart_console.c b/bsp/simulator/drivers/uart_console.c
index 913daf2311..8fd799b297 100644
--- a/bsp/simulator/drivers/uart_console.c
+++ b/bsp/simulator/drivers/uart_console.c
@@ -1,5 +1,13 @@
-#include 
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
 
+#include 
 #include 
 #include 
 #include 
@@ -88,11 +96,11 @@ static struct termios oldt, newt;
 /*simulate windows' getch(), it works!!*/
 static void set_stty(void)
 {
-	/* get terminal input's attribute */
+    /* get terminal input's attribute */
     tcgetattr(STDIN_FILENO, &oldt);
     newt = oldt;
 
-	/* set termios' local mode */
+    /* set termios' local mode */
     newt.c_lflag &= ~(ECHO|ICANON);
     tcsetattr(STDIN_FILENO, TCSANOW, &newt);
 }
@@ -117,10 +125,10 @@ static void * ThreadforKeyGet(void * lpParam)
 
 #ifndef _WIN32
     sigset_t  sigmask, oldmask;
-	/* set the getchar without buffer */
-	sigfillset(&sigmask);
-	pthread_sigmask(SIG_BLOCK, &sigmask, &oldmask);
-	set_stty();
+    /* set the getchar without buffer */
+    sigfillset(&sigmask);
+    pthread_sigmask(SIG_BLOCK, &sigmask, &oldmask);
+    set_stty();
 #endif
 
     (void)lpParam;              //prevent compiler warnings
@@ -217,7 +225,7 @@ static int console_putc(struct rt_serial_device *serial, char c)
 
     level = rt_hw_interrupt_disable();
     fwrite(&c, 1, 1, stdout);
-	fflush(stdout);
+    fflush(stdout);
     rt_hw_interrupt_enable(level);
     return 1;
 }
diff --git a/bsp/simulator/drivers/uart_console.h b/bsp/simulator/drivers/uart_console.h
index 149a7a21f8..8ea20cc2f4 100644
--- a/bsp/simulator/drivers/uart_console.h
+++ b/bsp/simulator/drivers/uart_console.h
@@ -1,3 +1,12 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
 #ifndef UART_CONSOLE_H__
 #define UART_CONSOLE_H__
 
diff --git a/bsp/simulator/dummy.c b/bsp/simulator/dummy.c
index 67a38866cb..38584eb5fd 100644
--- a/bsp/simulator/dummy.c
+++ b/bsp/simulator/dummy.c
@@ -1,4 +1,13 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
 int dummy_main()
 {
-	return 0;
+    return 0;
 }
diff --git a/bsp/simulator/pcap/Include/Packet32.h b/bsp/simulator/pcap/Include/Packet32.h
index 64be055d96..4dcafc1492 100644
--- a/bsp/simulator/pcap/Include/Packet32.h
+++ b/bsp/simulator/pcap/Include/Packet32.h
@@ -12,9 +12,9 @@
  * 2. Redistributions in binary form must reproduce the above copyright
  * notice, this list of conditions and the following disclaimer in the
  * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Politecnico di Torino, CACE Technologies 
- * nor the names of its contributors may be used to endorse or promote 
- * products derived from this software without specific prior written 
+ * 3. Neither the name of the Politecnico di Torino, CACE Technologies
+ * nor the names of its contributors may be used to endorse or promote
+ * products derived from this software without specific prior written
  * permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
@@ -32,7 +32,7 @@
  */
 
 /** @ingroup packetapi
- *  @{ 
+ *  @{
  */
 
 /** @defgroup packet32h Packet.dll definitions and data structures
@@ -70,19 +70,19 @@ typedef struct _AirpcapHandle *PAirpcapHandle;
 
 /// Alignment macro. Defines the alignment size.
 #define Packet_ALIGNMENT sizeof(int)
-/// Alignment macro. Rounds up to the next even multiple of Packet_ALIGNMENT. 
+/// Alignment macro. Rounds up to the next even multiple of Packet_ALIGNMENT.
 #define Packet_WORDALIGN(x) (((x)+(Packet_ALIGNMENT-1))&~(Packet_ALIGNMENT-1))
 
-#define NdisMediumNull	-1		///< Custom linktype: NDIS doesn't provide an equivalent
-#define NdisMediumCHDLC	-2		///< Custom linktype: NDIS doesn't provide an equivalent
-#define NdisMediumPPPSerial	-3	///< Custom linktype: NDIS doesn't provide an equivalent
-#define NdisMediumBare80211	-4	///< Custom linktype: NDIS doesn't provide an equivalent
-#define NdisMediumRadio80211	-5	///< Custom linktype: NDIS doesn't provide an equivalent
-#define NdisMediumPpi		-6	///< Custom linktype: NDIS doesn't provide an equivalent
+#define NdisMediumNull  -1      ///< Custom linktype: NDIS doesn't provide an equivalent
+#define NdisMediumCHDLC -2      ///< Custom linktype: NDIS doesn't provide an equivalent
+#define NdisMediumPPPSerial -3  ///< Custom linktype: NDIS doesn't provide an equivalent
+#define NdisMediumBare80211 -4  ///< Custom linktype: NDIS doesn't provide an equivalent
+#define NdisMediumRadio80211    -5  ///< Custom linktype: NDIS doesn't provide an equivalent
+#define NdisMediumPpi       -6  ///< Custom linktype: NDIS doesn't provide an equivalent
 
 // Loopback behaviour definitions
-#define NPF_DISABLE_LOOPBACK	1	///< Drop the packets sent by the NPF driver
-#define NPF_ENABLE_LOOPBACK		2	///< Capture the packets sent by the NPF driver
+#define NPF_DISABLE_LOOPBACK    1   ///< Drop the packets sent by the NPF driver
+#define NPF_ENABLE_LOOPBACK     2   ///< Capture the packets sent by the NPF driver
 
 /*!
   \brief Network type structure.
@@ -91,8 +91,8 @@ typedef struct _AirpcapHandle *PAirpcapHandle;
 */
 typedef struct NetType
 {
-	UINT LinkType;	///< The MAC of the current network adapter (see function PacketGetNetType() for more information)
-	ULONGLONG LinkSpeed;	///< The speed of the network in bits per second
+    UINT LinkType;  ///< The MAC of the current network adapter (see function PacketGetNetType() for more information)
+    ULONGLONG LinkSpeed;    ///< The speed of the network in bits per second
 }NetType;
 
 
@@ -103,12 +103,12 @@ typedef struct NetType
 /*!
   \brief A BPF pseudo-assembly program.
 
-  The program will be injected in the kernel by the PacketSetBPF() function and applied to every incoming packet. 
+  The program will be injected in the kernel by the PacketSetBPF() function and applied to every incoming packet.
 */
-struct bpf_program 
+struct bpf_program
 {
-	UINT bf_len;				///< Indicates the number of instructions of the program, i.e. the number of struct bpf_insn that will follow.
-	struct bpf_insn *bf_insns;	///< A pointer to the first instruction of the program.
+    UINT bf_len;                ///< Indicates the number of instructions of the program, i.e. the number of struct bpf_insn that will follow.
+    struct bpf_insn *bf_insns;  ///< A pointer to the first instruction of the program.
 };
 
 /*!
@@ -116,12 +116,12 @@ struct bpf_program
 
   bpf_insn contains a single instruction for the BPF register-machine. It is used to send a filter program to the driver.
 */
-struct bpf_insn 
+struct bpf_insn
 {
-	USHORT	code;		///< Instruction type and addressing mode.
-	UCHAR 	jt;			///< Jump if true
-	UCHAR 	jf;			///< Jump if false
-	int k;				///< Generic field used for various purposes.
+    USHORT  code;       ///< Instruction type and addressing mode.
+    UCHAR   jt;         ///< Jump if true
+    UCHAR   jf;         ///< Jump if false
+    int k;              ///< Generic field used for various purposes.
 };
 
 /*!
@@ -129,17 +129,17 @@ struct bpf_insn
 
   It is used by packet.dll to return statistics about a capture session.
 */
-struct bpf_stat 
+struct bpf_stat
 {
-	UINT bs_recv;		///< Number of packets that the driver received from the network adapter 
-						///< from the beginning of the current capture. This value includes the packets 
-						///< lost by the driver.
-	UINT bs_drop;		///< number of packets that the driver lost from the beginning of a capture. 
-						///< Basically, a packet is lost when the the buffer of the driver is full. 
-						///< In this situation the packet cannot be stored and the driver rejects it.
-	UINT ps_ifdrop;		///< drops by interface. XXX not yet supported
-	UINT bs_capt;		///< number of packets that pass the filter, find place in the kernel buffer and
-						///< thus reach the application.
+    UINT bs_recv;       ///< Number of packets that the driver received from the network adapter
+                        ///< from the beginning of the current capture. This value includes the packets
+                        ///< lost by the driver.
+    UINT bs_drop;       ///< number of packets that the driver lost from the beginning of a capture.
+                        ///< Basically, a packet is lost when the the buffer of the driver is full.
+                        ///< In this situation the packet cannot be stored and the driver rejects it.
+    UINT ps_ifdrop;     ///< drops by interface. XXX not yet supported
+    UINT bs_capt;       ///< number of packets that pass the filter, find place in the kernel buffer and
+                        ///< thus reach the application.
 };
 
 /*!
@@ -147,18 +147,18 @@ struct bpf_stat
 
   This structure defines the header associated with every packet delivered to the application.
 */
-struct bpf_hdr 
+struct bpf_hdr
 {
-	struct timeval	bh_tstamp;	///< The timestamp associated with the captured packet. 
-								///< It is stored in a TimeVal structure.
-	UINT	bh_caplen;			///< Length of captured portion. The captured portion can be different
-								///< from the original packet, because it is possible (with a proper filter)
-								///< to instruct the driver to capture only a portion of the packets.
-	UINT	bh_datalen;			///< Original length of packet
-	USHORT		bh_hdrlen;		///< Length of bpf header (this struct plus alignment padding). In some cases,
-								///< a padding could be added between the end of this structure and the packet
-								///< data for performance reasons. This filed can be used to retrieve the actual data 
-								///< of the packet.
+    struct timeval  bh_tstamp;  ///< The timestamp associated with the captured packet.
+                                ///< It is stored in a TimeVal structure.
+    UINT    bh_caplen;          ///< Length of captured portion. The captured portion can be different
+                                ///< from the original packet, because it is possible (with a proper filter)
+                                ///< to instruct the driver to capture only a portion of the packets.
+    UINT    bh_datalen;         ///< Original length of packet
+    USHORT      bh_hdrlen;      ///< Length of bpf header (this struct plus alignment padding). In some cases,
+                                ///< a padding could be added between the end of this structure and the packet
+                                ///< data for performance reasons. This filed can be used to retrieve the actual data
+                                ///< of the packet.
 };
 
 /*!
@@ -169,11 +169,11 @@ struct bpf_hdr
   packet in a dump file. This makes straightforward sending WinPcap dump files to the network.
 */
 struct dump_bpf_hdr{
-    struct timeval	ts;			///< Time stamp of the packet
-    UINT			caplen;		///< Length of captured portion. The captured portion can smaller than the 
-								///< the original packet, because it is possible (with a proper filter) to 
-								///< instruct the driver to capture only a portion of the packets. 
-    UINT			len;		///< Length of the original packet (off wire).
+    struct timeval  ts;         ///< Time stamp of the packet
+    UINT            caplen;     ///< Length of captured portion. The captured portion can smaller than the
+                                ///< the original packet, because it is possible (with a proper filter) to
+                                ///< instruct the driver to capture only a portion of the packets.
+    UINT            len;        ///< Length of the original packet (off wire).
 };
 
 
@@ -181,39 +181,39 @@ struct dump_bpf_hdr{
 
 struct bpf_stat;
 
-#define        DOSNAMEPREFIX   TEXT("Packet_")	///< Prefix added to the adapters device names to create the WinPcap devices
-#define        MAX_LINK_NAME_LENGTH	64			//< Maximum length of the devices symbolic links
+#define        DOSNAMEPREFIX   TEXT("Packet_")  ///< Prefix added to the adapters device names to create the WinPcap devices
+#define        MAX_LINK_NAME_LENGTH 64          //< Maximum length of the devices symbolic links
 #define        NMAX_PACKET 65535
 
 /*!
   \brief Addresses of a network adapter.
 
-  This structure is used by the PacketGetNetInfoEx() function to return the IP addresses associated with 
+  This structure is used by the PacketGetNetInfoEx() function to return the IP addresses associated with
   an adapter.
 */
 typedef struct npf_if_addr {
-	struct sockaddr_storage IPAddress;	///< IP address.
-	struct sockaddr_storage SubnetMask;	///< Netmask for that address.
-	struct sockaddr_storage Broadcast;	///< Broadcast address.
+    struct sockaddr_storage IPAddress;  ///< IP address.
+    struct sockaddr_storage SubnetMask; ///< Netmask for that address.
+    struct sockaddr_storage Broadcast;  ///< Broadcast address.
 }npf_if_addr;
 
 
-#define ADAPTER_NAME_LENGTH 256 + 12	///<  Maximum length for the name of an adapter. The value is the same used by the IP Helper API.
-#define ADAPTER_DESC_LENGTH 128			///<  Maximum length for the description of an adapter. The value is the same used by the IP Helper API.
-#define MAX_MAC_ADDR_LENGTH 8			///<  Maximum length for the link layer address of an adapter. The value is the same used by the IP Helper API.
-#define MAX_NETWORK_ADDRESSES 16		///<  Maximum length for the link layer address of an adapter. The value is the same used by the IP Helper API.
+#define ADAPTER_NAME_LENGTH 256 + 12    ///<  Maximum length for the name of an adapter. The value is the same used by the IP Helper API.
+#define ADAPTER_DESC_LENGTH 128         ///<  Maximum length for the description of an adapter. The value is the same used by the IP Helper API.
+#define MAX_MAC_ADDR_LENGTH 8           ///<  Maximum length for the link layer address of an adapter. The value is the same used by the IP Helper API.
+#define MAX_NETWORK_ADDRESSES 16        ///<  Maximum length for the link layer address of an adapter. The value is the same used by the IP Helper API.
 
 
 typedef struct WAN_ADAPTER_INT WAN_ADAPTER; ///< Describes an opened wan (dialup, VPN...) network adapter using the NetMon API
 typedef WAN_ADAPTER *PWAN_ADAPTER; ///< Describes an opened wan (dialup, VPN...) network adapter using the NetMon API
 
-#define INFO_FLAG_NDIS_ADAPTER		0	///< Flag for ADAPTER_INFO: this is a traditional ndis adapter
-#define INFO_FLAG_NDISWAN_ADAPTER	1	///< Flag for ADAPTER_INFO: this is a NdisWan adapter, and it's managed by WANPACKET
-#define INFO_FLAG_DAG_CARD			2	///< Flag for ADAPTER_INFO: this is a DAG card
-#define INFO_FLAG_DAG_FILE			6	///< Flag for ADAPTER_INFO: this is a DAG file
-#define INFO_FLAG_DONT_EXPORT		8	///< Flag for ADAPTER_INFO: when this flag is set, the adapter will not be listed or openend by winpcap. This allows to prevent exporting broken network adapters, like for example FireWire ones.
-#define INFO_FLAG_AIRPCAP_CARD		16	///< Flag for ADAPTER_INFO: this is an airpcap card
-#define INFO_FLAG_NPFIM_DEVICE		32
+#define INFO_FLAG_NDIS_ADAPTER      0   ///< Flag for ADAPTER_INFO: this is a traditional ndis adapter
+#define INFO_FLAG_NDISWAN_ADAPTER   1   ///< Flag for ADAPTER_INFO: this is a NdisWan adapter, and it's managed by WANPACKET
+#define INFO_FLAG_DAG_CARD          2   ///< Flag for ADAPTER_INFO: this is a DAG card
+#define INFO_FLAG_DAG_FILE          6   ///< Flag for ADAPTER_INFO: this is a DAG file
+#define INFO_FLAG_DONT_EXPORT       8   ///< Flag for ADAPTER_INFO: when this flag is set, the adapter will not be listed or openend by winpcap. This allows to prevent exporting broken network adapters, like for example FireWire ones.
+#define INFO_FLAG_AIRPCAP_CARD      16  ///< Flag for ADAPTER_INFO: this is an airpcap card
+#define INFO_FLAG_NPFIM_DEVICE      32
 
 /*!
   \brief Describes an opened network adapter.
@@ -221,39 +221,39 @@ typedef WAN_ADAPTER *PWAN_ADAPTER; ///< Describes an opened wan (dialup, VPN...)
   This structure is the most important for the functioning of packet.dll, but the great part of its fields
   should be ignored by the user, since the library offers functions that avoid to cope with low-level parameters
 */
-typedef struct _ADAPTER  { 
-	HANDLE hFile;				///< \internal Handle to an open instance of the NPF driver.
-	CHAR  SymbolicLink[MAX_LINK_NAME_LENGTH]; ///< \internal A string containing the name of the network adapter currently opened.
-	int NumWrites;				///< \internal Number of times a packets written on this adapter will be repeated 
-								///< on the wire.
-	HANDLE ReadEvent;			///< A notification event associated with the read calls on the adapter.
-								///< It can be passed to standard Win32 functions (like WaitForSingleObject
-								///< or WaitForMultipleObjects) to wait until the driver's buffer contains some 
-								///< data. It is particularly useful in GUI applications that need to wait 
-								///< concurrently on several events. In Windows NT/2000 the PacketSetMinToCopy()
-								///< function can be used to define the minimum amount of data in the kernel buffer
-								///< that will cause the event to be signalled. 
-	
-	UINT ReadTimeOut;			///< \internal The amount of time after which a read on the driver will be released and 
-								///< ReadEvent will be signaled, also if no packets were captured
-	CHAR Name[ADAPTER_NAME_LENGTH];
-	PWAN_ADAPTER pWanAdapter;
-	UINT Flags;					///< Adapter's flags. Tell if this adapter must be treated in a different way, using the Netmon API or the dagc API.
+typedef struct _ADAPTER  {
+    HANDLE hFile;               ///< \internal Handle to an open instance of the NPF driver.
+    CHAR  SymbolicLink[MAX_LINK_NAME_LENGTH]; ///< \internal A string containing the name of the network adapter currently opened.
+    int NumWrites;              ///< \internal Number of times a packets written on this adapter will be repeated
+                                ///< on the wire.
+    HANDLE ReadEvent;           ///< A notification event associated with the read calls on the adapter.
+                                ///< It can be passed to standard Win32 functions (like WaitForSingleObject
+                                ///< or WaitForMultipleObjects) to wait until the driver's buffer contains some
+                                ///< data. It is particularly useful in GUI applications that need to wait
+                                ///< concurrently on several events. In Windows NT/2000 the PacketSetMinToCopy()
+                                ///< function can be used to define the minimum amount of data in the kernel buffer
+                                ///< that will cause the event to be signalled.
+
+    UINT ReadTimeOut;           ///< \internal The amount of time after which a read on the driver will be released and
+                                ///< ReadEvent will be signaled, also if no packets were captured
+    CHAR Name[ADAPTER_NAME_LENGTH];
+    PWAN_ADAPTER pWanAdapter;
+    UINT Flags;                 ///< Adapter's flags. Tell if this adapter must be treated in a different way, using the Netmon API or the dagc API.
 
 #ifdef HAVE_AIRPCAP_API
-	PAirpcapHandle	AirpcapAd;
+    PAirpcapHandle  AirpcapAd;
 #endif // HAVE_AIRPCAP_API
 
 #ifdef HAVE_NPFIM_API
-	void* NpfImHandle;
+    void* NpfImHandle;
 #endif // HAVE_NPFIM_API
 
 #ifdef HAVE_DAG_API
-	dagc_t *pDagCard;			///< Pointer to the dagc API adapter descriptor for this adapter
-	PCHAR DagBuffer;			///< Pointer to the buffer with the packets that is received from the DAG card
-	struct timeval DagReadTimeout;	///< Read timeout. The dagc API requires a timeval structure
-	unsigned DagFcsLen;			///< Length of the frame check sequence attached to any packet by the card. Obtained from the registry
-	DWORD DagFastProcess;		///< True if the user requests fast capture processing on this card. Higher level applications can use this value to provide a faster but possibly unprecise capture (for example, libpcap doesn't convert the timestamps).
+    dagc_t *pDagCard;           ///< Pointer to the dagc API adapter descriptor for this adapter
+    PCHAR DagBuffer;            ///< Pointer to the buffer with the packets that is received from the DAG card
+    struct timeval DagReadTimeout;  ///< Read timeout. The dagc API requires a timeval structure
+    unsigned DagFcsLen;         ///< Length of the frame check sequence attached to any packet by the card. Obtained from the registry
+    DWORD DagFastProcess;       ///< True if the user requests fast capture processing on this card. Higher level applications can use this value to provide a faster but possibly unprecise capture (for example, libpcap doesn't convert the timestamps).
 #endif // HAVE_DAG_API
 }  ADAPTER, *LPADAPTER;
 
@@ -262,31 +262,31 @@ typedef struct _ADAPTER  {
 
   This structure defines the header associated with every packet delivered to the application.
 */
-typedef struct _PACKET {  
-	HANDLE       hEvent;		///< \deprecated Still present for compatibility with old applications.
-	OVERLAPPED   OverLapped;	///< \deprecated Still present for compatibility with old applications.
-	PVOID        Buffer;		///< Buffer with containing the packets. See the PacketReceivePacket() for
-								///< details about the organization of the data in this buffer
-	UINT         Length;		///< Length of the buffer
-	DWORD        ulBytesReceived;	///< Number of valid bytes present in the buffer, i.e. amount of data
-									///< received by the last call to PacketReceivePacket()
-	BOOLEAN      bIoComplete;	///< \deprecated Still present for compatibility with old applications.
+typedef struct _PACKET {
+    HANDLE       hEvent;        ///< \deprecated Still present for compatibility with old applications.
+    OVERLAPPED   OverLapped;    ///< \deprecated Still present for compatibility with old applications.
+    PVOID        Buffer;        ///< Buffer with containing the packets. See the PacketReceivePacket() for
+                                ///< details about the organization of the data in this buffer
+    UINT         Length;        ///< Length of the buffer
+    DWORD        ulBytesReceived;   ///< Number of valid bytes present in the buffer, i.e. amount of data
+                                    ///< received by the last call to PacketReceivePacket()
+    BOOLEAN      bIoComplete;   ///< \deprecated Still present for compatibility with old applications.
 }  PACKET, *LPPACKET;
 
 /*!
   \brief Structure containing an OID request.
 
-  It is used by the PacketRequest() function to send an OID to the interface card driver. 
-  It can be used, for example, to retrieve the status of the error counters on the adapter, its MAC address, 
+  It is used by the PacketRequest() function to send an OID to the interface card driver.
+  It can be used, for example, to retrieve the status of the error counters on the adapter, its MAC address,
   the list of the multicast groups defined on it, and so on.
 */
 struct _PACKET_OID_DATA {
-    ULONG Oid;					///< OID code. See the Microsoft DDK documentation or the file ntddndis.h
-								///< for a complete list of valid codes.
-    ULONG Length;				///< Length of the data field
-    UCHAR Data[1];				///< variable-lenght field that contains the information passed to or received 
-								///< from the adapter.
-}; 
+    ULONG Oid;                  ///< OID code. See the Microsoft DDK documentation or the file ntddndis.h
+                                ///< for a complete list of valid codes.
+    ULONG Length;               ///< Length of the data field
+    UCHAR Data[1];              ///< variable-lenght field that contains the information passed to or received
+                                ///< from the adapter.
+};
 typedef struct _PACKET_OID_DATA PACKET_OID_DATA, *PPACKET_OID_DATA;
 
 #ifdef __cplusplus
@@ -299,16 +299,16 @@ extern "C" {
 
 /*
 BOOLEAN QueryWinPcapRegistryStringA(CHAR *SubKeyName,
-								 CHAR *Value,
-								 UINT *pValueLen,
-								 CHAR *DefaultVal);
+                                 CHAR *Value,
+                                 UINT *pValueLen,
+                                 CHAR *DefaultVal);
 
 BOOLEAN QueryWinPcapRegistryStringW(WCHAR *SubKeyName,
-								 WCHAR *Value,
-								 UINT *pValueLen,
-								 WCHAR *DefaultVal);
+                                 WCHAR *Value,
+                                 UINT *pValueLen,
+                                 WCHAR *DefaultVal);
 */
-								 
+
 //---------------------------------------------------------------------------
 // EXPORTED FUNCTIONS
 //---------------------------------------------------------------------------
@@ -350,10 +350,10 @@ PAirpcapHandle PacketGetAirPcapHandle(LPADAPTER AdapterObject);
 //
 // Used by PacketStartOemEx
 //
-#define PACKET_START_OEM_NO_NETMON	0x00000001
+#define PACKET_START_OEM_NO_NETMON  0x00000001
 
 #ifdef __cplusplus
 }
-#endif 
+#endif
 
 #endif //__PACKET32
diff --git a/bsp/simulator/pcap/Include/Win32-Extensions.h b/bsp/simulator/pcap/Include/Win32-Extensions.h
index ad3be25cfa..42120290a9 100644
--- a/bsp/simulator/pcap/Include/Win32-Extensions.h
+++ b/bsp/simulator/pcap/Include/Win32-Extensions.h
@@ -12,9 +12,9 @@
  * 2. Redistributions in binary form must reproduce the above copyright
  * notice, this list of conditions and the following disclaimer in the
  * documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the Politecnico di Torino, CACE Technologies 
- * nor the names of its contributors may be used to endorse or promote 
- * products derived from this software without specific prior written 
+ * 3. Neither the name of the Politecnico di Torino, CACE Technologies
+ * nor the names of its contributors may be used to endorse or promote
+ * products derived from this software without specific prior written
  * permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
@@ -45,9 +45,9 @@ extern "C" {
 */
 struct pcap_send_queue
 {
-	u_int maxlen;		///< Maximum size of the the queue, in bytes. This variable contains the size of the buffer field.
-	u_int len;			///< Current size of the queue, in bytes.
-	char *buffer;		///< Buffer containing the packets to be sent.
+    u_int maxlen;       ///< Maximum size of the the queue, in bytes. This variable contains the size of the buffer field.
+    u_int len;          ///< Current size of the queue, in bytes.
+    char *buffer;       ///< Buffer containing the packets to be sent.
 };
 
 typedef struct pcap_send_queue pcap_send_queue;
@@ -60,26 +60,26 @@ typedef struct pcap_send_queue pcap_send_queue;
 typedef struct _AirpcapHandle *PAirpcapHandle;
 #endif
 
-#define		BPF_MEM_EX_IMM	0xc0
-#define		BPF_MEM_EX_IND	0xe0
+#define     BPF_MEM_EX_IMM  0xc0
+#define     BPF_MEM_EX_IND  0xe0
 
 /*used for ST*/
-#define		BPF_MEM_EX		0xc0
-#define		BPF_TME					0x08
+#define     BPF_MEM_EX      0xc0
+#define     BPF_TME                 0x08
 
-#define		BPF_LOOKUP				0x90   
-#define		BPF_EXECUTE				0xa0
-#define		BPF_INIT				0xb0
-#define		BPF_VALIDATE			0xc0
-#define		BPF_SET_ACTIVE			0xd0
-#define		BPF_RESET				0xe0
-#define		BPF_SET_MEMORY			0x80
-#define		BPF_GET_REGISTER_VALUE	0x70
-#define		BPF_SET_REGISTER_VALUE	0x60
-#define		BPF_SET_WORKING			0x50
-#define		BPF_SET_ACTIVE_READ		0x40
-#define		BPF_SET_AUTODELETION	0x30
-#define		BPF_SEPARATION			0xff
+#define     BPF_LOOKUP              0x90
+#define     BPF_EXECUTE             0xa0
+#define     BPF_INIT                0xb0
+#define     BPF_VALIDATE            0xc0
+#define     BPF_SET_ACTIVE          0xd0
+#define     BPF_RESET               0xe0
+#define     BPF_SET_MEMORY          0x80
+#define     BPF_GET_REGISTER_VALUE  0x70
+#define     BPF_SET_REGISTER_VALUE  0x60
+#define     BPF_SET_WORKING         0x50
+#define     BPF_SET_ACTIVE_READ     0x40
+#define     BPF_SET_AUTODELETION    0x30
+#define     BPF_SEPARATION          0xff
 
 /* Prototypes */
 pcap_send_queue* pcap_sendqueue_alloc(u_int memsize);
diff --git a/bsp/simulator/pcap/Include/bittypes.h b/bsp/simulator/pcap/Include/bittypes.h
index 558a0b5c0d..e098671b58 100644
--- a/bsp/simulator/pcap/Include/bittypes.h
+++ b/bsp/simulator/pcap/Include/bittypes.h
@@ -1,7 +1,7 @@
 /*
  * Copyright (C) 1999 WIDE Project.
  * All rights reserved.
- * 
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
@@ -13,7 +13,7 @@
  * 3. Neither the name of the project nor the names of its contributors
  *    may be used to endorse or promote products derived from this software
  *    without specific prior written permission.
- * 
+ *
  * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@@ -45,7 +45,7 @@ typedef signed int int8_t;
 
 #endif /* HAVE_U_INT8_T */
 
-#ifndef HAVE_U_INT16_T 
+#ifndef HAVE_U_INT16_T
 
 #if SIZEOF_SHORT == 2
 typedef unsigned short u_int16_t;
@@ -104,33 +104,33 @@ typedef unsigned short u_int64_t;
 
 #ifndef PRId64
 #ifdef _MSC_EXTENSIONS
-#define PRId64	"I64d"
+#define PRId64  "I64d"
 #else /* _MSC_EXTENSIONS */
-#define PRId64	"lld"
+#define PRId64  "lld"
 #endif /* _MSC_EXTENSIONS */
 #endif /* PRId64 */
 
 #ifndef PRIo64
 #ifdef _MSC_EXTENSIONS
-#define PRIo64	"I64o"
+#define PRIo64  "I64o"
 #else /* _MSC_EXTENSIONS */
-#define PRIo64	"llo"
+#define PRIo64  "llo"
 #endif /* _MSC_EXTENSIONS */
 #endif /* PRIo64 */
 
 #ifndef PRIx64
 #ifdef _MSC_EXTENSIONS
-#define PRIx64	"I64x"
+#define PRIx64  "I64x"
 #else /* _MSC_EXTENSIONS */
-#define PRIx64	"llx"
+#define PRIx64  "llx"
 #endif /* _MSC_EXTENSIONS */
 #endif /* PRIx64 */
 
 #ifndef PRIu64
 #ifdef _MSC_EXTENSIONS
-#define PRIu64	"I64u"
+#define PRIu64  "I64u"
 #else /* _MSC_EXTENSIONS */
-#define PRIu64	"llu"
+#define PRIu64  "llu"
 #endif /* _MSC_EXTENSIONS */
 #endif /* PRIu64 */
 
diff --git a/bsp/simulator/pcap/Include/ip6_misc.h b/bsp/simulator/pcap/Include/ip6_misc.h
index 562fa6184e..a55e8340d0 100644
--- a/bsp/simulator/pcap/Include/ip6_misc.h
+++ b/bsp/simulator/pcap/Include/ip6_misc.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 1993, 1994, 1997
- *	The Regents of the University of California.  All rights reserved.
+ *  The Regents of the University of California.  All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that: (1) source code distributions
@@ -30,12 +30,12 @@
 #include 
 
 #ifndef __MINGW32__
-#define	IN_MULTICAST(a)		IN_CLASSD(a)
+#define IN_MULTICAST(a)     IN_CLASSD(a)
 #endif
 
-#define	IN_EXPERIMENTAL(a)	((((u_int32_t) (a)) & 0xf0000000) == 0xf0000000)
+#define IN_EXPERIMENTAL(a)  ((((u_int32_t) (a)) & 0xf0000000) == 0xf0000000)
 
-#define	IN_LOOPBACKNET		127
+#define IN_LOOPBACKNET      127
 
 #if defined(__MINGW32__) && defined(DEFINE_ADDITIONAL_IPV6_STUFF)
 /* IPv6 address */
@@ -43,14 +43,14 @@ struct in6_addr
   {
     union
       {
-	u_int8_t		u6_addr8[16];
-	u_int16_t	u6_addr16[8];
-	u_int32_t	u6_addr32[4];
+    u_int8_t        u6_addr8[16];
+    u_int16_t   u6_addr16[8];
+    u_int32_t   u6_addr32[4];
       } in6_u;
-#define s6_addr			in6_u.u6_addr8
-#define s6_addr16		in6_u.u6_addr16
-#define s6_addr32		in6_u.u6_addr32
-#define s6_addr64		in6_u.u6_addr64
+#define s6_addr         in6_u.u6_addr8
+#define s6_addr16       in6_u.u6_addr16
+#define s6_addr32       in6_u.u6_addr32
+#define s6_addr64       in6_u.u6_addr64
   };
 
 #define IN6ADDR_ANY_INIT { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
@@ -59,36 +59,36 @@ struct in6_addr
 
 
 #if (defined _MSC_VER) || (defined(__MINGW32__) && defined(DEFINE_ADDITIONAL_IPV6_STUFF))
-typedef unsigned short	sa_family_t;
+typedef unsigned short  sa_family_t;
 #endif
 
 
 #if defined(__MINGW32__) && defined(DEFINE_ADDITIONAL_IPV6_STUFF)
 
-#define	__SOCKADDR_COMMON(sa_prefix) \
+#define __SOCKADDR_COMMON(sa_prefix) \
   sa_family_t sa_prefix##family
 
 /* Ditto, for IPv6.  */
 struct sockaddr_in6
   {
     __SOCKADDR_COMMON (sin6_);
-    u_int16_t sin6_port;		/* Transport layer port # */
-    u_int32_t sin6_flowinfo;	/* IPv6 flow information */
-    struct in6_addr sin6_addr;	/* IPv6 address */
+    u_int16_t sin6_port;        /* Transport layer port # */
+    u_int32_t sin6_flowinfo;    /* IPv6 flow information */
+    struct in6_addr sin6_addr;  /* IPv6 address */
   };
 
 #define IN6_IS_ADDR_V4MAPPED(a) \
-	((((u_int32_t *) (a))[0] == 0) && (((u_int32_t *) (a))[1] == 0) && \
-	 (((u_int32_t *) (a))[2] == htonl (0xffff)))
+    ((((u_int32_t *) (a))[0] == 0) && (((u_int32_t *) (a))[1] == 0) && \
+     (((u_int32_t *) (a))[2] == htonl (0xffff)))
 
 #define IN6_IS_ADDR_MULTICAST(a) (((u_int8_t *) (a))[0] == 0xff)
 
 #define IN6_IS_ADDR_LINKLOCAL(a) \
-	((((u_int32_t *) (a))[0] & htonl (0xffc00000)) == htonl (0xfe800000))
+    ((((u_int32_t *) (a))[0] & htonl (0xffc00000)) == htonl (0xfe800000))
 
 #define IN6_IS_ADDR_LOOPBACK(a) \
-	(((u_int32_t *) (a))[0] == 0 && ((u_int32_t *) (a))[1] == 0 && \
-	 ((u_int32_t *) (a))[2] == 0 && ((u_int32_t *) (a))[3] == htonl (1))
+    (((u_int32_t *) (a))[0] == 0 && ((u_int32_t *) (a))[1] == 0 && \
+     ((u_int32_t *) (a))[2] == 0 && ((u_int32_t *) (a))[3] == htonl (1))
 #endif /* __MINGW32__ */
 
 #define ip6_vfc   ip6_ctlun.ip6_un2_vfc
@@ -104,60 +104,60 @@ struct sockaddr_in6
 #define nd_rd_reserved           nd_rd_hdr.icmp6_data32[0]
 
 /*
- *	IPV6 extension headers
+ *  IPV6 extension headers
  */
-#define IPPROTO_HOPOPTS		0	/* IPv6 hop-by-hop options	*/
-#define IPPROTO_IPV6		41  /* IPv6 header.  */
-#define IPPROTO_ROUTING		43	/* IPv6 routing header		*/
-#define IPPROTO_FRAGMENT	44	/* IPv6 fragmentation header	*/
-#define IPPROTO_ESP		50	/* encapsulating security payload */
-#define IPPROTO_AH		51	/* authentication header	*/
-#define IPPROTO_ICMPV6		58	/* ICMPv6			*/
-#define IPPROTO_NONE		59	/* IPv6 no next header		*/
-#define IPPROTO_DSTOPTS		60	/* IPv6 destination options	*/
-#define IPPROTO_PIM			103 /* Protocol Independent Multicast.  */
+#define IPPROTO_HOPOPTS     0   /* IPv6 hop-by-hop options  */
+#define IPPROTO_IPV6        41  /* IPv6 header.  */
+#define IPPROTO_ROUTING     43  /* IPv6 routing header      */
+#define IPPROTO_FRAGMENT    44  /* IPv6 fragmentation header    */
+#define IPPROTO_ESP     50  /* encapsulating security payload */
+#define IPPROTO_AH      51  /* authentication header    */
+#define IPPROTO_ICMPV6      58  /* ICMPv6           */
+#define IPPROTO_NONE        59  /* IPv6 no next header      */
+#define IPPROTO_DSTOPTS     60  /* IPv6 destination options */
+#define IPPROTO_PIM         103 /* Protocol Independent Multicast.  */
 
-#define	 IPV6_RTHDR_TYPE_0 0
+#define  IPV6_RTHDR_TYPE_0 0
 
 /* Option types and related macros */
-#define IP6OPT_PAD1		0x00	/* 00 0 00000 */
-#define IP6OPT_PADN		0x01	/* 00 0 00001 */
-#define IP6OPT_JUMBO		0xC2	/* 11 0 00010 = 194 */
-#define IP6OPT_JUMBO_LEN	6
-#define IP6OPT_ROUTER_ALERT	0x05	/* 00 0 00101 */
+#define IP6OPT_PAD1     0x00    /* 00 0 00000 */
+#define IP6OPT_PADN     0x01    /* 00 0 00001 */
+#define IP6OPT_JUMBO        0xC2    /* 11 0 00010 = 194 */
+#define IP6OPT_JUMBO_LEN    6
+#define IP6OPT_ROUTER_ALERT 0x05    /* 00 0 00101 */
 
-#define IP6OPT_RTALERT_LEN	4
-#define IP6OPT_RTALERT_MLD	0	/* Datagram contains an MLD message */
-#define IP6OPT_RTALERT_RSVP	1	/* Datagram contains an RSVP message */
-#define IP6OPT_RTALERT_ACTNET	2 	/* contains an Active Networks msg */
-#define IP6OPT_MINLEN		2
+#define IP6OPT_RTALERT_LEN  4
+#define IP6OPT_RTALERT_MLD  0   /* Datagram contains an MLD message */
+#define IP6OPT_RTALERT_RSVP 1   /* Datagram contains an RSVP message */
+#define IP6OPT_RTALERT_ACTNET   2   /* contains an Active Networks msg */
+#define IP6OPT_MINLEN       2
 
-#define IP6OPT_BINDING_UPDATE	0xc6	/* 11 0 00110 */
-#define IP6OPT_BINDING_ACK	0x07	/* 00 0 00111 */
-#define IP6OPT_BINDING_REQ	0x08	/* 00 0 01000 */
-#define IP6OPT_HOME_ADDRESS	0xc9	/* 11 0 01001 */
-#define IP6OPT_EID		0x8a	/* 10 0 01010 */
+#define IP6OPT_BINDING_UPDATE   0xc6    /* 11 0 00110 */
+#define IP6OPT_BINDING_ACK  0x07    /* 00 0 00111 */
+#define IP6OPT_BINDING_REQ  0x08    /* 00 0 01000 */
+#define IP6OPT_HOME_ADDRESS 0xc9    /* 11 0 01001 */
+#define IP6OPT_EID      0x8a    /* 10 0 01010 */
 
-#define IP6OPT_TYPE(o)		((o) & 0xC0)
-#define IP6OPT_TYPE_SKIP	0x00
-#define IP6OPT_TYPE_DISCARD	0x40
-#define IP6OPT_TYPE_FORCEICMP	0x80
-#define IP6OPT_TYPE_ICMP	0xC0
+#define IP6OPT_TYPE(o)      ((o) & 0xC0)
+#define IP6OPT_TYPE_SKIP    0x00
+#define IP6OPT_TYPE_DISCARD 0x40
+#define IP6OPT_TYPE_FORCEICMP   0x80
+#define IP6OPT_TYPE_ICMP    0xC0
 
-#define IP6OPT_MUTABLE		0x20
+#define IP6OPT_MUTABLE      0x20
 
 
 #if defined(__MINGW32__) && defined(DEFINE_ADDITIONAL_IPV6_STUFF)
 #ifndef EAI_ADDRFAMILY
 struct addrinfo {
-	int	ai_flags;	/* AI_PASSIVE, AI_CANONNAME */
-	int	ai_family;	/* PF_xxx */
-	int	ai_socktype;	/* SOCK_xxx */
-	int	ai_protocol;	/* 0 or IPPROTO_xxx for IPv4 and IPv6 */
-	size_t	ai_addrlen;	/* length of ai_addr */
-	char	*ai_canonname;	/* canonical name for hostname */
-	struct sockaddr *ai_addr;	/* binary address */
-	struct addrinfo *ai_next;	/* next structure in linked list */
+    int ai_flags;   /* AI_PASSIVE, AI_CANONNAME */
+    int ai_family;  /* PF_xxx */
+    int ai_socktype;    /* SOCK_xxx */
+    int ai_protocol;    /* 0 or IPPROTO_xxx for IPv4 and IPv6 */
+    size_t  ai_addrlen; /* length of ai_addr */
+    char    *ai_canonname;  /* canonical name for hostname */
+    struct sockaddr *ai_addr;   /* binary address */
+    struct addrinfo *ai_next;   /* next structure in linked list */
 };
 #endif
 #endif /* __MINGW32__ */
diff --git a/bsp/simulator/pcap/Include/pcap-bpf.h b/bsp/simulator/pcap/Include/pcap-bpf.h
index 5fe129dbb4..b272e63002 100644
--- a/bsp/simulator/pcap/Include/pcap-bpf.h
+++ b/bsp/simulator/pcap/Include/pcap-bpf.h
@@ -1,10 +1,10 @@
 /*-
  * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997
- *	The Regents of the University of California.  All rights reserved.
+ *  The Regents of the University of California.  All rights reserved.
  *
  * This code is derived from the Stanford/CMU enet packet filter,
  * (net/enet.c) distributed as part of 4.3BSD, and code contributed
- * to Berkeley by Steven McCanne and Van Jacobson both of Lawrence 
+ * to Berkeley by Steven McCanne and Van Jacobson both of Lawrence
  * Berkeley Laboratory.
  *
  * Redistribution and use in source and binary forms, with or without
diff --git a/bsp/simulator/pcap/Include/pcap-namedb.h b/bsp/simulator/pcap/Include/pcap-namedb.h
index 80a2f00401..c1e255ca22 100644
--- a/bsp/simulator/pcap/Include/pcap-namedb.h
+++ b/bsp/simulator/pcap/Include/pcap-namedb.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 1994, 1996
- *	The Regents of the University of California.  All rights reserved.
+ *  The Regents of the University of California.  All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -12,8 +12,8 @@
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
- *	This product includes software developed by the Computer Systems
- *	Engineering Group at Lawrence Berkeley Laboratory.
+ *  This product includes software developed by the Computer Systems
+ *  Engineering Group at Lawrence Berkeley Laboratory.
  * 4. Neither the name of the University nor of the Laboratory may be used
  *    to endorse or promote products derived from this software without
  *    specific prior written permission.
diff --git a/bsp/simulator/pcap/Include/pcap-stdinc.h b/bsp/simulator/pcap/Include/pcap-stdinc.h
index 417604177b..46100ccca5 100644
--- a/bsp/simulator/pcap/Include/pcap-stdinc.h
+++ b/bsp/simulator/pcap/Include/pcap-stdinc.h
@@ -39,7 +39,7 @@
 #endif
 
 /*
- * Avoids a compiler warning in case this was already defined      
+ * Avoids a compiler warning in case this was already defined
  * (someone defined _WINSOCKAPI_ when including 'windows.h', in order
  * to prevent it from including 'winsock.h')
  */
@@ -66,7 +66,7 @@
 #define strdup _strdup
 #endif
 
-#define inline __inline 
+#define inline __inline
 
 #ifdef __MINGW32__
 #include 
@@ -88,6 +88,6 @@ typedef __int64    intptr_t;
 typedef _W64 int   intptr_t;
 #endif
 #define _INTPTR_T_DEFINED
-#endif 
+#endif
 
 #endif /*__MINGW32__*/
diff --git a/bsp/simulator/pcap/Include/pcap.h b/bsp/simulator/pcap/Include/pcap.h
index 935f9494c1..8540af309c 100644
--- a/bsp/simulator/pcap/Include/pcap.h
+++ b/bsp/simulator/pcap/Include/pcap.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 1993, 1994, 1995, 1996, 1997
- *	The Regents of the University of California.  All rights reserved.
+ *  The Regents of the University of California.  All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -12,8 +12,8 @@
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
- *	This product includes software developed by the Computer Systems
- *	Engineering Group at Lawrence Berkeley Laboratory.
+ *  This product includes software developed by the Computer Systems
+ *  Engineering Group at Lawrence Berkeley Laboratory.
  * 4. Neither the name of the University nor of the Laboratory may be used
  *    to endorse or promote products derived from this software without
  *    specific prior written permission.
diff --git a/bsp/simulator/pcap/Include/pcap/bluetooth.h b/bsp/simulator/pcap/Include/pcap/bluetooth.h
index 7bf65df034..097499eab3 100644
--- a/bsp/simulator/pcap/Include/pcap/bluetooth.h
+++ b/bsp/simulator/pcap/Include/pcap/bluetooth.h
@@ -11,8 +11,8 @@
  * 2. Redistributions in binary form must reproduce the above copyright
  * notice, this list of conditions and the following disclaimer in the
  * documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote 
- * products derived from this software without specific prior written 
+ * 3. The name of the author may not be used to endorse or promote
+ * products derived from this software without specific prior written
  * permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
@@ -32,7 +32,7 @@
  *
  * @(#) $Header: /tcpdump/master/libpcap/pcap/bluetooth.h,v 1.1 2007/09/22 02:10:17 guy Exp $
  */
- 
+
 #ifndef _PCAP_BLUETOOTH_STRUCTS_H__
 #define _PCAP_BLUETOOTH_STRUCTS_H__
 
@@ -41,7 +41,7 @@
  * fields are in network byte order
  */
 typedef struct _pcap_bluetooth_h4_header {
-	u_int32_t direction; /* if first bit is set direction is incoming */
+    u_int32_t direction; /* if first bit is set direction is incoming */
 } pcap_bluetooth_h4_header;
 
 
diff --git a/bsp/simulator/pcap/Include/pcap/bpf.h b/bsp/simulator/pcap/Include/pcap/bpf.h
index 9f4ca33e35..fce0a3c130 100644
--- a/bsp/simulator/pcap/Include/pcap/bpf.h
+++ b/bsp/simulator/pcap/Include/pcap/bpf.h
@@ -1,10 +1,10 @@
 /*-
  * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997
- *	The Regents of the University of California.  All rights reserved.
+ *  The Regents of the University of California.  All rights reserved.
  *
  * This code is derived from the Stanford/CMU enet packet filter,
  * (net/enet.c) distributed as part of 4.3BSD, and code contributed
- * to Berkeley by Steven McCanne and Van Jacobson both of Lawrence 
+ * to Berkeley by Steven McCanne and Van Jacobson both of Lawrence
  * Berkeley Laboratory.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -64,13 +64,13 @@ extern "C" {
 typedef long          bpf_int32;
 typedef unsigned long bpf_u_int32;
 #else
-typedef	int bpf_int32;
-typedef	u_int bpf_u_int32;
+typedef int bpf_int32;
+typedef u_int bpf_u_int32;
 #endif
 
 /*
- * Alignment macros.  BPF_WORDALIGN rounds up to the next 
- * even multiple of BPF_ALIGNMENT. 
+ * Alignment macros.  BPF_WORDALIGN rounds up to the next
+ * even multiple of BPF_ALIGNMENT.
  */
 #ifndef __NetBSD__
 #define BPF_ALIGNMENT sizeof(bpf_int32)
@@ -86,12 +86,12 @@ typedef	u_int bpf_u_int32;
  * Structure for "pcap_compile()", "pcap_setfilter()", etc..
  */
 struct bpf_program {
-	u_int bf_len;
-	struct bpf_insn *bf_insns;
+    u_int bf_len;
+    struct bpf_insn *bf_insns;
 };
- 
+
 /*
- * Struct return by BIOCVERSION.  This represents the version number of 
+ * Struct return by BIOCVERSION.  This represents the version number of
  * the filter language described by the instruction encodings below.
  * bpf understands a program iff kernel_major == filter_major &&
  * kernel_minor >= filter_minor, that is, if the value returned by the
@@ -102,8 +102,8 @@ struct bpf_program {
  * It has nothing to do with the source code version.
  */
 struct bpf_version {
-	u_short bv_major;
-	u_short bv_minor;
+    u_short bv_major;
+    u_short bv_minor;
 };
 /* Current version number of filter architecture. */
 #define BPF_MAJOR_VERSION 1
@@ -125,17 +125,17 @@ struct bpf_version {
  * These are the types that are the same on all platforms, and that
  * have been defined by  for ages.
  */
-#define DLT_NULL	0	/* BSD loopback encapsulation */
-#define DLT_EN10MB	1	/* Ethernet (10Mb) */
-#define DLT_EN3MB	2	/* Experimental Ethernet (3Mb) */
-#define DLT_AX25	3	/* Amateur Radio AX.25 */
-#define DLT_PRONET	4	/* Proteon ProNET Token Ring */
-#define DLT_CHAOS	5	/* Chaos */
-#define DLT_IEEE802	6	/* 802.5 Token Ring */
-#define DLT_ARCNET	7	/* ARCNET, with BSD-style header */
-#define DLT_SLIP	8	/* Serial Line IP */
-#define DLT_PPP		9	/* Point-to-point Protocol */
-#define DLT_FDDI	10	/* FDDI */
+#define DLT_NULL    0   /* BSD loopback encapsulation */
+#define DLT_EN10MB  1   /* Ethernet (10Mb) */
+#define DLT_EN3MB   2   /* Experimental Ethernet (3Mb) */
+#define DLT_AX25    3   /* Amateur Radio AX.25 */
+#define DLT_PRONET  4   /* Proteon ProNET Token Ring */
+#define DLT_CHAOS   5   /* Chaos */
+#define DLT_IEEE802 6   /* 802.5 Token Ring */
+#define DLT_ARCNET  7   /* ARCNET, with BSD-style header */
+#define DLT_SLIP    8   /* Serial Line IP */
+#define DLT_PPP     9   /* Point-to-point Protocol */
+#define DLT_FDDI    10  /* FDDI */
 
 /*
  * These are types that are different on some platforms, and that
@@ -146,12 +146,12 @@ struct bpf_version {
  * XXX - DLT_ATM_RFC1483 is 13 in BSD/OS, and DLT_RAW is 14 in BSD/OS,
  * but I don't know what the right #define is for BSD/OS.
  */
-#define DLT_ATM_RFC1483	11	/* LLC-encapsulated ATM */
+#define DLT_ATM_RFC1483 11  /* LLC-encapsulated ATM */
 
 #ifdef __OpenBSD__
-#define DLT_RAW		14	/* raw IP */
+#define DLT_RAW     14  /* raw IP */
 #else
-#define DLT_RAW		12	/* raw IP */
+#define DLT_RAW     12  /* raw IP */
 #endif
 
 /*
@@ -162,12 +162,12 @@ struct bpf_version {
  */
 #if defined(__NetBSD__) || defined(__FreeBSD__)
 #ifndef DLT_SLIP_BSDOS
-#define DLT_SLIP_BSDOS	13	/* BSD/OS Serial Line IP */
-#define DLT_PPP_BSDOS	14	/* BSD/OS Point-to-point Protocol */
+#define DLT_SLIP_BSDOS  13  /* BSD/OS Serial Line IP */
+#define DLT_PPP_BSDOS   14  /* BSD/OS Point-to-point Protocol */
 #endif
 #else
-#define DLT_SLIP_BSDOS	15	/* BSD/OS Serial Line IP */
-#define DLT_PPP_BSDOS	16	/* BSD/OS Point-to-point Protocol */
+#define DLT_SLIP_BSDOS  15  /* BSD/OS Serial Line IP */
+#define DLT_PPP_BSDOS   16  /* BSD/OS Point-to-point Protocol */
 #endif
 
 /*
@@ -176,21 +176,21 @@ struct bpf_version {
  * 18 is used for DLT_PFSYNC in OpenBSD; don't use it for anything else.
  */
 
-#define DLT_ATM_CLIP	19	/* Linux Classical-IP over ATM */
+#define DLT_ATM_CLIP    19  /* Linux Classical-IP over ATM */
 
 /*
  * Apparently Redback uses this for its SmartEdge 400/800.  I hope
  * nobody else decided to use it, too.
  */
-#define DLT_REDBACK_SMARTEDGE	32
+#define DLT_REDBACK_SMARTEDGE   32
 
 /*
  * These values are defined by NetBSD; other platforms should refrain from
  * using them for other purposes, so that NetBSD savefiles with link
  * types of 50 or 51 can be read as this type on all platforms.
  */
-#define DLT_PPP_SERIAL	50	/* PPP over serial with HDLC encapsulation */
-#define DLT_PPP_ETHER	51	/* PPP over Ethernet */
+#define DLT_PPP_SERIAL  50  /* PPP over serial with HDLC encapsulation */
+#define DLT_PPP_ETHER   51  /* PPP over Ethernet */
 
 /*
  * The Axent Raptor firewall - now the Symantec Enterprise Firewall - uses
@@ -199,7 +199,7 @@ struct bpf_version {
  * Ethernet type, and 36 bytes that appear to be 0 in at least one capture
  * I've seen.
  */
-#define DLT_SYMANTEC_FIREWALL	99
+#define DLT_SYMANTEC_FIREWALL   99
 
 /*
  * Values between 100 and 103 are used in capture file headers as
@@ -221,10 +221,10 @@ struct bpf_version {
  * libpcap 0.5 defined it as DLT_CHDLC; we define DLT_CHDLC as well,
  * for source compatibility with programs written for libpcap 0.5.
  */
-#define DLT_C_HDLC	104	/* Cisco HDLC */
-#define DLT_CHDLC	DLT_C_HDLC
+#define DLT_C_HDLC  104 /* Cisco HDLC */
+#define DLT_CHDLC   DLT_C_HDLC
 
-#define DLT_IEEE802_11	105	/* IEEE 802.11 wireless */
+#define DLT_IEEE802_11  105 /* IEEE 802.11 wireless */
 
 /*
  * 106 is reserved for Linux Classical IP over ATM; it's like DLT_RAW,
@@ -239,7 +239,7 @@ struct bpf_version {
  * DLT_FR and DLT_FRELAY packets start with the Q.922 Frame Relay header
  * (DLCI, etc.).
  */
-#define DLT_FRELAY	107
+#define DLT_FRELAY  107
 
 /*
  * OpenBSD DLT_LOOP, for loopback devices; it's like DLT_NULL, except
@@ -249,9 +249,9 @@ struct bpf_version {
  * we don't use 12 for it in OSes other than OpenBSD.
  */
 #ifdef __OpenBSD__
-#define DLT_LOOP	12
+#define DLT_LOOP    12
 #else
-#define DLT_LOOP	108
+#define DLT_LOOP    108
 #endif
 
 /*
@@ -260,9 +260,9 @@ struct bpf_version {
  * than OpenBSD.
  */
 #ifdef __OpenBSD__
-#define DLT_ENC		13
+#define DLT_ENC     13
 #else
-#define DLT_ENC		109
+#define DLT_ENC     109
 #endif
 
 /*
@@ -275,22 +275,22 @@ struct bpf_version {
 /*
  * This is for Linux cooked sockets.
  */
-#define DLT_LINUX_SLL	113
+#define DLT_LINUX_SLL   113
 
 /*
  * Apple LocalTalk hardware.
  */
-#define DLT_LTALK	114
+#define DLT_LTALK   114
 
 /*
  * Acorn Econet.
  */
-#define DLT_ECONET	115
+#define DLT_ECONET  115
 
 /*
  * Reserved for use with OpenBSD ipfilter.
  */
-#define DLT_IPFILTER	116
+#define DLT_IPFILTER    116
 
 /*
  * OpenBSD DLT_PFLOG; DLT_PFLOG is 17 in OpenBSD, but that's DLT_LANE8023
@@ -299,33 +299,33 @@ struct bpf_version {
  * XXX: is there a conflict with DLT_PFSYNC 18 as well?
  */
 #ifdef __OpenBSD__
-#define DLT_OLD_PFLOG	17
-#define DLT_PFSYNC	18
+#define DLT_OLD_PFLOG   17
+#define DLT_PFSYNC  18
 #endif
-#define DLT_PFLOG	117
+#define DLT_PFLOG   117
 
 /*
  * Registered for Cisco-internal use.
  */
-#define DLT_CISCO_IOS	118
+#define DLT_CISCO_IOS   118
 
 /*
  * For 802.11 cards using the Prism II chips, with a link-layer
  * header including Prism monitor mode information plus an 802.11
  * header.
  */
-#define DLT_PRISM_HEADER	119
+#define DLT_PRISM_HEADER    119
 
 /*
  * Reserved for Aironet 802.11 cards, with an Aironet link-layer header
  * (see Doug Ambrisko's FreeBSD patches).
  */
-#define DLT_AIRONET_HEADER	120
+#define DLT_AIRONET_HEADER  120
 
 /*
  * Reserved for Siemens HiPath HDLC.
  */
-#define DLT_HHDLC		121
+#define DLT_HHDLC       121
 
 /*
  * This is for RFC 2625 IP-over-Fibre Channel.
@@ -335,7 +335,7 @@ struct bpf_version {
  * where the link-layer header starts with an RFC 2625 Network_Header
  * field.
  */
-#define DLT_IP_OVER_FC		122
+#define DLT_IP_OVER_FC      122
 
 /*
  * This is for Full Frontal ATM on Solaris with SunATM, with a
@@ -351,9 +351,9 @@ struct bpf_version {
  * and the like don't have to infer the presence or absence of a
  * pseudo-header and the form of the pseudo-header.
  */
-#define DLT_SUNATM		123	/* Solaris+SunATM */
+#define DLT_SUNATM      123 /* Solaris+SunATM */
 
-/* 
+/*
  * Reserved as per request from Kent Dahlgren 
  * for private use.
  */
@@ -366,7 +366,7 @@ struct bpf_version {
  * including radio information, used by some recent BSD drivers as
  * well as the madwifi Atheros driver for Linux.
  */
-#define DLT_IEEE802_11_RADIO	127	/* 802.11 plus radiotap radio header */
+#define DLT_IEEE802_11_RADIO    127 /* 802.11 plus radiotap radio header */
 
 /*
  * Reserved for the TZSP encapsulation, as per request from
@@ -389,7 +389,7 @@ struct bpf_version {
  *
  * We therefore have to have separate DLT_ values for them.
  */
-#define DLT_ARCNET_LINUX	129	/* ARCNET */
+#define DLT_ARCNET_LINUX    129 /* ARCNET */
 
 /*
  * Juniper-private data link types, as per request from
@@ -411,31 +411,31 @@ struct bpf_version {
  * .  The header that's presented is an Ethernet-like
  * header:
  *
- *	#define FIREWIRE_EUI64_LEN	8
- *	struct firewire_header {
- *		u_char  firewire_dhost[FIREWIRE_EUI64_LEN];
- *		u_char  firewire_shost[FIREWIRE_EUI64_LEN];
- *		u_short firewire_type;
- *	};
+ *  #define FIREWIRE_EUI64_LEN  8
+ *  struct firewire_header {
+ *      u_char  firewire_dhost[FIREWIRE_EUI64_LEN];
+ *      u_char  firewire_shost[FIREWIRE_EUI64_LEN];
+ *      u_short firewire_type;
+ *  };
  *
  * with "firewire_type" being an Ethernet type value, rather than,
  * for example, raw GASP frames being handed up.
  */
-#define DLT_APPLE_IP_OVER_IEEE1394	138
+#define DLT_APPLE_IP_OVER_IEEE1394  138
 
 /*
  * Various SS7 encapsulations, as per a request from Jeff Morriss
  *  and subsequent discussions.
  */
-#define DLT_MTP2_WITH_PHDR	139	/* pseudo-header with various info, followed by MTP2 */
-#define DLT_MTP2		140	/* MTP2, without pseudo-header */
-#define DLT_MTP3		141	/* MTP3, without pseudo-header or MTP2 */
-#define DLT_SCCP		142	/* SCCP, without pseudo-header or MTP2 or MTP3 */
+#define DLT_MTP2_WITH_PHDR  139 /* pseudo-header with various info, followed by MTP2 */
+#define DLT_MTP2        140 /* MTP2, without pseudo-header */
+#define DLT_MTP3        141 /* MTP3, without pseudo-header or MTP2 */
+#define DLT_SCCP        142 /* SCCP, without pseudo-header or MTP2 or MTP3 */
 
 /*
  * DOCSIS MAC frames.
  */
-#define DLT_DOCSIS		143
+#define DLT_DOCSIS      143
 
 /*
  * Linux-IrDA packets. Protocol defined at http://www.irda.org.
@@ -452,13 +452,13 @@ struct bpf_version {
  * issue and define a real DLT_IRDA...
  * Jean II
  */
-#define DLT_LINUX_IRDA		144
+#define DLT_LINUX_IRDA      144
 
 /*
  * Reserved for IBM SP switch and IBM Next Federation switch.
  */
-#define DLT_IBM_SP		145
-#define DLT_IBM_SN		146
+#define DLT_IBM_SP      145
+#define DLT_IBM_SN      146
 
 /*
  * Reserved for private use.  If you have some link-layer header type
@@ -485,34 +485,34 @@ struct bpf_version {
  * Instead, ask "tcpdump-workers@lists.tcpdump.org" for a new DLT_ value,
  * as per the comment above, and use the type you're given.
  */
-#define DLT_USER0		147
-#define DLT_USER1		148
-#define DLT_USER2		149
-#define DLT_USER3		150
-#define DLT_USER4		151
-#define DLT_USER5		152
-#define DLT_USER6		153
-#define DLT_USER7		154
-#define DLT_USER8		155
-#define DLT_USER9		156
-#define DLT_USER10		157
-#define DLT_USER11		158
-#define DLT_USER12		159
-#define DLT_USER13		160
-#define DLT_USER14		161
-#define DLT_USER15		162
+#define DLT_USER0       147
+#define DLT_USER1       148
+#define DLT_USER2       149
+#define DLT_USER3       150
+#define DLT_USER4       151
+#define DLT_USER5       152
+#define DLT_USER6       153
+#define DLT_USER7       154
+#define DLT_USER8       155
+#define DLT_USER9       156
+#define DLT_USER10      157
+#define DLT_USER11      158
+#define DLT_USER12      159
+#define DLT_USER13      160
+#define DLT_USER14      161
+#define DLT_USER15      162
 
 /*
  * For future use with 802.11 captures - defined by AbsoluteValue
  * Systems to store a number of bits of link-layer information
  * including radio information:
  *
- *	http://www.shaftnet.org/~pizza/software/capturefrm.txt
+ *  http://www.shaftnet.org/~pizza/software/capturefrm.txt
  *
  * but it might be used by some non-AVS drivers now or in the
  * future.
  */
-#define DLT_IEEE802_11_RADIO_AVS 163	/* 802.11 plus AVS radio header */
+#define DLT_IEEE802_11_RADIO_AVS 163    /* 802.11 plus AVS radio header */
 
 /*
  * Juniper-private data link type, as per request from
@@ -525,7 +525,7 @@ struct bpf_version {
 /*
  * Reserved for BACnet MS/TP.
  */
-#define DLT_BACNET_MS_TP	165
+#define DLT_BACNET_MS_TP    165
 
 /*
  * Another PPP variant as per request from Karsten Keil .
@@ -541,14 +541,14 @@ struct bpf_version {
  * The first byte of the PPP header (0xff03) is modified to accomodate
  * the direction - 0x00 = IN, 0x01 = OUT.
  */
-#define DLT_PPP_PPPD		166
+#define DLT_PPP_PPPD        166
 
 /*
  * Names for backwards compatibility with older versions of some PPP
  * software; new software should use DLT_PPP_PPPD.
  */
-#define DLT_PPP_WITH_DIRECTION	DLT_PPP_PPPD
-#define DLT_LINUX_PPP_WITHDIRECTION	DLT_PPP_PPPD
+#define DLT_PPP_WITH_DIRECTION  DLT_PPP_PPPD
+#define DLT_LINUX_PPP_WITHDIRECTION DLT_PPP_PPPD
 
 /*
  * Juniper-private data link type, as per request from
@@ -559,16 +559,16 @@ struct bpf_version {
 #define DLT_JUNIPER_PPPOE       167
 #define DLT_JUNIPER_PPPOE_ATM   168
 
-#define DLT_GPRS_LLC		169	/* GPRS LLC */
-#define DLT_GPF_T		170	/* GPF-T (ITU-T G.7041/Y.1303) */
-#define DLT_GPF_F		171	/* GPF-F (ITU-T G.7041/Y.1303) */
+#define DLT_GPRS_LLC        169 /* GPRS LLC */
+#define DLT_GPF_T       170 /* GPF-T (ITU-T G.7041/Y.1303) */
+#define DLT_GPF_F       171 /* GPF-F (ITU-T G.7041/Y.1303) */
 
 /*
  * Requested by Oolan Zimmer  for use in Gcom's T1/E1 line
  * monitoring equipment.
  */
-#define DLT_GCOM_T1E1		172
-#define DLT_GCOM_SERIAL		173
+#define DLT_GCOM_T1E1       172
+#define DLT_GCOM_SERIAL     173
 
 /*
  * Juniper-private data link type, as per request from
@@ -583,8 +583,8 @@ struct bpf_version {
  * http://www.endace.com/support/EndaceRecordFormat.pdf) in front of
  * the link-layer header.
  */
-#define DLT_ERF_ETH		175	/* Ethernet */
-#define DLT_ERF_POS		176	/* Packet-over-SONET */
+#define DLT_ERF_ETH     175 /* Ethernet */
+#define DLT_ERF_POS     176 /* Packet-over-SONET */
 
 /*
  * Requested by Daniele Orlandi  for raw LAPD
@@ -592,11 +592,11 @@ struct bpf_version {
  * includes additional information before the LAPD header, so it's
  * not necessarily a generic LAPD header.
  */
-#define DLT_LINUX_LAPD		177
+#define DLT_LINUX_LAPD      177
 
 /*
  * Juniper-private data link type, as per request from
- * Hannes Gredler . 
+ * Hannes Gredler .
  * The DLT_ are used for prepending meta-information
  * like interface index, interface name
  * before standard Ethernet, PPP, Frelay & C-HDLC Frames
@@ -613,7 +613,7 @@ struct bpf_version {
 
 /*
  * Juniper-private data link type, as per request from
- * Hannes Gredler . 
+ * Hannes Gredler .
  * The DLT_ is used for internal communication with a
  * voice Adapter Card (PIC)
  */
@@ -639,25 +639,25 @@ struct bpf_version {
  * USB packets, beginning with a USB setup header; requested by
  * Paolo Abeni .
  */
-#define DLT_USB			186
+#define DLT_USB         186
 
 /*
  * Bluetooth HCI UART transport layer (part H:4); requested by
  * Paolo Abeni.
  */
-#define DLT_BLUETOOTH_HCI_H4	187
+#define DLT_BLUETOOTH_HCI_H4    187
 
 /*
  * IEEE 802.16 MAC Common Part Sublayer; requested by Maria Cruz
  * .
  */
-#define DLT_IEEE802_16_MAC_CPS	188
+#define DLT_IEEE802_16_MAC_CPS  188
 
 /*
  * USB packets, beginning with a Linux USB header; requested by
  * Paolo Abeni .
  */
-#define DLT_USB_LINUX		189
+#define DLT_USB_LINUX       189
 
 /*
  * Controller Area Network (CAN) v. 2.0B packets.
@@ -672,23 +672,23 @@ struct bpf_version {
  * IEEE 802.15.4, with address fields padded, as is done by Linux
  * drivers; requested by Juergen Schimmer.
  */
-#define DLT_IEEE802_15_4_LINUX	191
+#define DLT_IEEE802_15_4_LINUX  191
 
 /*
  * Per Packet Information encapsulated packets.
  * DLT_ requested by Gianluca Varenni .
  */
-#define DLT_PPI			192
+#define DLT_PPI         192
 
 /*
  * Header for 802.16 MAC Common Part Sublayer plus a radiotap radio header;
  * requested by Charles Clancy.
  */
-#define DLT_IEEE802_16_MAC_CPS_RADIO	193
+#define DLT_IEEE802_16_MAC_CPS_RADIO    193
 
 /*
  * Juniper-private data link type, as per request from
- * Hannes Gredler . 
+ * Hannes Gredler .
  * The DLT_ is used for internal communication with a
  * integrated service module (ISM).
  */
@@ -698,38 +698,38 @@ struct bpf_version {
  * IEEE 802.15.4, exactly as it appears in the spec (no padding, no
  * nothing); requested by Mikko Saarnivala .
  */
-#define DLT_IEEE802_15_4	195
+#define DLT_IEEE802_15_4    195
 
 /*
  * Various link-layer types, with a pseudo-header, for SITA
  * (http://www.sita.aero/); requested by Fulko Hew (fulko.hew@gmail.com).
  */
-#define DLT_SITA		196
+#define DLT_SITA        196
 
 /*
  * Various link-layer types, with a pseudo-header, for Endace DAG cards;
  * encapsulates Endace ERF records.  Requested by Stephen Donnelly
  * .
  */
-#define DLT_ERF			197
+#define DLT_ERF         197
 
 /*
  * Special header prepended to Ethernet packets when capturing from a
  * u10 Networks board.  Requested by Phil Mulholland
  * .
  */
-#define DLT_RAIF1		198
+#define DLT_RAIF1       198
 
 /*
  * IPMB packet for IPMI, beginning with the I2C slave address, followed
  * by the netFn and LUN, etc..  Requested by Chanthy Toeung
  * .
  */
-#define DLT_IPMB		199
+#define DLT_IPMB        199
 
 /*
  * Juniper-private data link type, as per request from
- * Hannes Gredler . 
+ * Hannes Gredler .
  * The DLT_ is used for capturing data on a secure tunnel interface.
  */
 #define DLT_JUNIPER_ST          200
@@ -738,23 +738,23 @@ struct bpf_version {
  * Bluetooth HCI UART transport layer (part H:4), with pseudo-header
  * that includes direction information; requested by Paolo Abeni.
  */
-#define DLT_BLUETOOTH_HCI_H4_WITH_PHDR	201
+#define DLT_BLUETOOTH_HCI_H4_WITH_PHDR  201
 
 /*
  * AX.25 packet with a 1-byte KISS header; see
  *
- *	http://www.ax25.net/kiss.htm
+ *  http://www.ax25.net/kiss.htm
  *
  * as per Richard Stearn .
  */
-#define DLT_AX25_KISS		202
+#define DLT_AX25_KISS       202
 
 /*
  * LAPD packets from an ISDN channel, starting with the address field,
  * with no pseudo-header.
  * Requested by Varuna De Silva .
  */
-#define DLT_LAPD		203
+#define DLT_LAPD        203
 
 /*
  * Variants of various link-layer headers, with a one-byte direction
@@ -762,10 +762,10 @@ struct bpf_version {
  * non-zero (any non-zero value) means "sent by this host" - as per
  * Will Barker .
  */
-#define DLT_PPP_WITH_DIR	204	/* PPP - don't confuse with DLT_PPP_WITH_DIRECTION */
-#define DLT_C_HDLC_WITH_DIR	205	/* Cisco HDLC */
-#define DLT_FRELAY_WITH_DIR	206	/* Frame Relay */
-#define DLT_LAPB_WITH_DIR	207	/* LAPB */
+#define DLT_PPP_WITH_DIR    204 /* PPP - don't confuse with DLT_PPP_WITH_DIRECTION */
+#define DLT_C_HDLC_WITH_DIR 205 /* Cisco HDLC */
+#define DLT_FRELAY_WITH_DIR 206 /* Frame Relay */
+#define DLT_LAPB_WITH_DIR   207 /* LAPB */
 
 /*
  * 208 is reserved for an as-yet-unspecified proprietary link-layer
@@ -776,39 +776,39 @@ struct bpf_version {
  * IPMB with a Linux-specific pseudo-header; as requested by Alexey Neyman
  * .
  */
-#define DLT_IPMB_LINUX		209
+#define DLT_IPMB_LINUX      209
 
 /*
  * FlexRay automotive bus - http://www.flexray.com/ - as requested
  * by Hannes Kaelber .
  */
-#define DLT_FLEXRAY		210
+#define DLT_FLEXRAY     210
 
 /*
  * Media Oriented Systems Transport (MOST) bus for multimedia
  * transport - http://www.mostcooperation.com/ - as requested
  * by Hannes Kaelber .
  */
-#define DLT_MOST		211
+#define DLT_MOST        211
 
 /*
  * Local Interconnect Network (LIN) bus for vehicle networks -
  * http://www.lin-subbus.org/ - as requested by Hannes Kaelber
  * .
  */
-#define DLT_LIN			212
+#define DLT_LIN         212
 
 /*
  * X2E-private data link type used for serial line capture,
  * as requested by Hannes Kaelber .
  */
-#define DLT_X2E_SERIAL		213
+#define DLT_X2E_SERIAL      213
 
 /*
  * X2E-private data link type used for the Xoraya data logger
  * family, as requested by Hannes Kaelber .
  */
-#define DLT_X2E_XORAYA		214
+#define DLT_X2E_XORAYA      214
 
 /*
  * IEEE 802.15.4, exactly as it appears in the spec (no padding, no
@@ -819,7 +819,7 @@ struct bpf_version {
  *
  * Requested by Max Filippov .
  */
-#define DLT_IEEE802_15_4_NONASK_PHY	215
+#define DLT_IEEE802_15_4_NONASK_PHY 215
 
 
 /*
@@ -827,7 +827,7 @@ struct bpf_version {
  * a member of that class.  A class value of 0 indicates a regular
  * DLT_/LINKTYPE_ value.
  */
-#define DLT_CLASS(x)		((x) & 0x03ff0000)
+#define DLT_CLASS(x)        ((x) & 0x03ff0000)
 
 /*
  * NetBSD-specific generic "raw" link type.  The class value indicates
@@ -836,10 +836,10 @@ struct bpf_version {
  * do not assume that they correspond to AF_ values for your operating
  * system.
  */
-#define	DLT_CLASS_NETBSD_RAWAF	0x02240000
-#define	DLT_NETBSD_RAWAF(af)	(DLT_CLASS_NETBSD_RAWAF | (af))
-#define	DLT_NETBSD_RAWAF_AF(x)	((x) & 0x0000ffff)
-#define	DLT_IS_NETBSD_RAWAF(x)	(DLT_CLASS(x) == DLT_CLASS_NETBSD_RAWAF)
+#define DLT_CLASS_NETBSD_RAWAF  0x02240000
+#define DLT_NETBSD_RAWAF(af)    (DLT_CLASS_NETBSD_RAWAF | (af))
+#define DLT_NETBSD_RAWAF_AF(x)  ((x) & 0x0000ffff)
+#define DLT_IS_NETBSD_RAWAF(x)  (DLT_CLASS(x) == DLT_CLASS_NETBSD_RAWAF)
 
 
 /*
@@ -847,65 +847,65 @@ struct bpf_version {
  */
 /* instruction classes */
 #define BPF_CLASS(code) ((code) & 0x07)
-#define		BPF_LD		0x00
-#define		BPF_LDX		0x01
-#define		BPF_ST		0x02
-#define		BPF_STX		0x03
-#define		BPF_ALU		0x04
-#define		BPF_JMP		0x05
-#define		BPF_RET		0x06
-#define		BPF_MISC	0x07
+#define     BPF_LD      0x00
+#define     BPF_LDX     0x01
+#define     BPF_ST      0x02
+#define     BPF_STX     0x03
+#define     BPF_ALU     0x04
+#define     BPF_JMP     0x05
+#define     BPF_RET     0x06
+#define     BPF_MISC    0x07
 
 /* ld/ldx fields */
-#define BPF_SIZE(code)	((code) & 0x18)
-#define		BPF_W		0x00
-#define		BPF_H		0x08
-#define		BPF_B		0x10
-#define BPF_MODE(code)	((code) & 0xe0)
-#define		BPF_IMM 	0x00
-#define		BPF_ABS		0x20
-#define		BPF_IND		0x40
-#define		BPF_MEM		0x60
-#define		BPF_LEN		0x80
-#define		BPF_MSH		0xa0
+#define BPF_SIZE(code)  ((code) & 0x18)
+#define     BPF_W       0x00
+#define     BPF_H       0x08
+#define     BPF_B       0x10
+#define BPF_MODE(code)  ((code) & 0xe0)
+#define     BPF_IMM     0x00
+#define     BPF_ABS     0x20
+#define     BPF_IND     0x40
+#define     BPF_MEM     0x60
+#define     BPF_LEN     0x80
+#define     BPF_MSH     0xa0
 
 /* alu/jmp fields */
-#define BPF_OP(code)	((code) & 0xf0)
-#define		BPF_ADD		0x00
-#define		BPF_SUB		0x10
-#define		BPF_MUL		0x20
-#define		BPF_DIV		0x30
-#define		BPF_OR		0x40
-#define		BPF_AND		0x50
-#define		BPF_LSH		0x60
-#define		BPF_RSH		0x70
-#define		BPF_NEG		0x80
-#define		BPF_JA		0x00
-#define		BPF_JEQ		0x10
-#define		BPF_JGT		0x20
-#define		BPF_JGE		0x30
-#define		BPF_JSET	0x40
-#define BPF_SRC(code)	((code) & 0x08)
-#define		BPF_K		0x00
-#define		BPF_X		0x08
+#define BPF_OP(code)    ((code) & 0xf0)
+#define     BPF_ADD     0x00
+#define     BPF_SUB     0x10
+#define     BPF_MUL     0x20
+#define     BPF_DIV     0x30
+#define     BPF_OR      0x40
+#define     BPF_AND     0x50
+#define     BPF_LSH     0x60
+#define     BPF_RSH     0x70
+#define     BPF_NEG     0x80
+#define     BPF_JA      0x00
+#define     BPF_JEQ     0x10
+#define     BPF_JGT     0x20
+#define     BPF_JGE     0x30
+#define     BPF_JSET    0x40
+#define BPF_SRC(code)   ((code) & 0x08)
+#define     BPF_K       0x00
+#define     BPF_X       0x08
 
 /* ret - BPF_K and BPF_X also apply */
-#define BPF_RVAL(code)	((code) & 0x18)
-#define		BPF_A		0x10
+#define BPF_RVAL(code)  ((code) & 0x18)
+#define     BPF_A       0x10
 
 /* misc */
 #define BPF_MISCOP(code) ((code) & 0xf8)
-#define		BPF_TAX		0x00
-#define		BPF_TXA		0x80
+#define     BPF_TAX     0x00
+#define     BPF_TXA     0x80
 
 /*
  * The instruction data structure.
  */
 struct bpf_insn {
-	u_short	code;
-	u_char 	jt;
-	u_char 	jf;
-	bpf_u_int32 k;
+    u_short code;
+    u_char  jt;
+    u_char  jf;
+    bpf_u_int32 k;
 };
 
 /*
diff --git a/bsp/simulator/pcap/Include/pcap/namedb.h b/bsp/simulator/pcap/Include/pcap/namedb.h
index 9002c75093..a74c85a421 100644
--- a/bsp/simulator/pcap/Include/pcap/namedb.h
+++ b/bsp/simulator/pcap/Include/pcap/namedb.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 1994, 1996
- *	The Regents of the University of California.  All rights reserved.
+ *  The Regents of the University of California.  All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -12,8 +12,8 @@
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
- *	This product includes software developed by the Computer Systems
- *	Engineering Group at Lawrence Berkeley Laboratory.
+ *  This product includes software developed by the Computer Systems
+ *  Engineering Group at Lawrence Berkeley Laboratory.
  * 4. Neither the name of the University nor of the Laboratory may be used
  *    to endorse or promote products derived from this software without
  *    specific prior written permission.
@@ -48,13 +48,13 @@ extern "C" {
  * export these hooks since they'll
  */
 struct pcap_etherent {
-	u_char addr[6];
-	char name[122];
+    u_char addr[6];
+    char name[122];
 };
 #ifndef PCAP_ETHERS_FILE
 #define PCAP_ETHERS_FILE "/etc/ethers"
 #endif
-struct	pcap_etherent *pcap_next_etherent(FILE *);
+struct  pcap_etherent *pcap_next_etherent(FILE *);
 u_char *pcap_ether_hostton(const char*);
 u_char *pcap_ether_aton(const char *);
 
@@ -64,23 +64,23 @@ struct addrinfo *pcap_nametoaddrinfo(const char *);
 #endif
 bpf_u_int32 pcap_nametonetaddr(const char *);
 
-int	pcap_nametoport(const char *, int *, int *);
-int	pcap_nametoportrange(const char *, int *, int *, int *);
-int	pcap_nametoproto(const char *);
-int	pcap_nametoeproto(const char *);
-int	pcap_nametollc(const char *);
+int pcap_nametoport(const char *, int *, int *);
+int pcap_nametoportrange(const char *, int *, int *, int *);
+int pcap_nametoproto(const char *);
+int pcap_nametoeproto(const char *);
+int pcap_nametollc(const char *);
 /*
  * If a protocol is unknown, PROTO_UNDEF is returned.
  * Also, pcap_nametoport() returns the protocol along with the port number.
  * If there are ambiguous entried in /etc/services (i.e. domain
  * can be either tcp or udp) PROTO_UNDEF is returned.
  */
-#define PROTO_UNDEF		-1
+#define PROTO_UNDEF     -1
 
 /* XXX move these to pcap-int.h? */
 int __pcap_atodn(const char *, bpf_u_int32 *);
 int __pcap_atoin(const char *, bpf_u_int32 *);
-u_short	__pcap_nametodnaddr(const char *);
+u_short __pcap_nametodnaddr(const char *);
 
 #ifdef __cplusplus
 }
diff --git a/bsp/simulator/pcap/Include/pcap/pcap.h b/bsp/simulator/pcap/Include/pcap/pcap.h
index ad8fc40ac1..f01ea49993 100644
--- a/bsp/simulator/pcap/Include/pcap/pcap.h
+++ b/bsp/simulator/pcap/Include/pcap/pcap.h
@@ -1,7 +1,7 @@
 /* -*- Mode: c; tab-width: 8; indent-tabs-mode: 1; c-basic-offset: 8; -*- */
 /*
  * Copyright (c) 1993, 1994, 1995, 1996, 1997
- *	The Regents of the University of California.  All rights reserved.
+ *  The Regents of the University of California.  All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -13,8 +13,8 @@
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
- *	This product includes software developed by the Computer Systems
- *	Engineering Group at Lawrence Berkeley Laboratory.
+ *  This product includes software developed by the Computer Systems
+ *  Engineering Group at Lawrence Berkeley Laboratory.
  * 4. Neither the name of the University nor of the Laboratory may be used
  *    to endorse or promote products derived from this software without
  *    specific prior written permission.
@@ -54,16 +54,16 @@
 #include 
 
 #ifdef HAVE_REMOTE
-	// We have to define the SOCKET here, although it has been defined in sockutils.h
-	// This is to avoid the distribution of the 'sockutils.h' file around
-	// (for example in the WinPcap developer's pack)
-	#ifndef SOCKET
-		#ifdef WIN32
-			#define SOCKET unsigned int
-		#else
-			#define SOCKET int
-		#endif
-	#endif
+    // We have to define the SOCKET here, although it has been defined in sockutils.h
+    // This is to avoid the distribution of the 'sockutils.h' file around
+    // (for example in the WinPcap developer's pack)
+    #ifndef SOCKET
+        #ifdef WIN32
+            #define SOCKET unsigned int
+        #else
+            #define SOCKET int
+        #endif
+    #endif
 #endif
 
 #ifdef __cplusplus
@@ -80,8 +80,8 @@ extern "C" {
  * predates the bpf typedefs for 64-bit support.
  */
 #if BPF_RELEASE - 0 < 199406
-typedef	int bpf_int32;
-typedef	u_int bpf_u_int32;
+typedef int bpf_int32;
+typedef u_int bpf_u_int32;
 #endif
 
 typedef struct pcap pcap_t;
@@ -105,46 +105,46 @@ typedef struct pcap_addr pcap_addr_t;
  *
  * Instead:
  *
- *	introduce a new structure for the new format, if the layout
- *	of the structure changed;
+ *  introduce a new structure for the new format, if the layout
+ *  of the structure changed;
  *
- *	send mail to "tcpdump-workers@lists.tcpdump.org", requesting
- *	a new magic number for your new capture file format, and, when
- *	you get the new magic number, put it in "savefile.c";
+ *  send mail to "tcpdump-workers@lists.tcpdump.org", requesting
+ *  a new magic number for your new capture file format, and, when
+ *  you get the new magic number, put it in "savefile.c";
  *
- *	use that magic number for save files with the changed file
- *	header;
+ *  use that magic number for save files with the changed file
+ *  header;
  *
- *	make the code in "savefile.c" capable of reading files with
- *	the old file header as well as files with the new file header
- *	(using the magic number to determine the header format).
+ *  make the code in "savefile.c" capable of reading files with
+ *  the old file header as well as files with the new file header
+ *  (using the magic number to determine the header format).
  *
  * Then supply the changes as a patch at
  *
- *	http://sourceforge.net/projects/libpcap/
+ *  http://sourceforge.net/projects/libpcap/
  *
  * so that future versions of libpcap and programs that use it (such as
  * tcpdump) will be able to read your new capture file format.
  */
 struct pcap_file_header {
-	bpf_u_int32 magic;
-	u_short version_major;
-	u_short version_minor;
-	bpf_int32 thiszone;	/* gmt to local correction */
-	bpf_u_int32 sigfigs;	/* accuracy of timestamps */
-	bpf_u_int32 snaplen;	/* max length saved portion of each pkt */
-	bpf_u_int32 linktype;	/* data link type (LINKTYPE_*) */
+    bpf_u_int32 magic;
+    u_short version_major;
+    u_short version_minor;
+    bpf_int32 thiszone; /* gmt to local correction */
+    bpf_u_int32 sigfigs;    /* accuracy of timestamps */
+    bpf_u_int32 snaplen;    /* max length saved portion of each pkt */
+    bpf_u_int32 linktype;   /* data link type (LINKTYPE_*) */
 };
 
 /*
  * Macros for the value returned by pcap_datalink_ext().
- * 
+ *
  * If LT_FCS_LENGTH_PRESENT(x) is true, the LT_FCS_LENGTH(x) macro
  * gives the FCS length of packets in the capture.
  */
-#define LT_FCS_LENGTH_PRESENT(x)	((x) & 0x04000000)
-#define LT_FCS_LENGTH(x)		(((x) & 0xF0000000) >> 28)
-#define LT_FCS_DATALINK_EXT(x)		((((x) & 0xF) << 28) | 0x04000000)
+#define LT_FCS_LENGTH_PRESENT(x)    ((x) & 0x04000000)
+#define LT_FCS_LENGTH(x)        (((x) & 0xF0000000) >> 28)
+#define LT_FCS_DATALINK_EXT(x)      ((((x) & 0xF) << 28) | 0x04000000)
 
 typedef enum {
        PCAP_D_INOUT = 0,
@@ -165,22 +165,22 @@ typedef enum {
  * that's not what the underlying packet capture mechanism supplies.
  */
 struct pcap_pkthdr {
-	struct timeval ts;	/* time stamp */
-	bpf_u_int32 caplen;	/* length of portion present */
-	bpf_u_int32 len;	/* length this packet (off wire) */
+    struct timeval ts;  /* time stamp */
+    bpf_u_int32 caplen; /* length of portion present */
+    bpf_u_int32 len;    /* length this packet (off wire) */
 };
 
 /*
  * As returned by the pcap_stats()
  */
 struct pcap_stat {
-	u_int ps_recv;		/* number of packets received */
-	u_int ps_drop;		/* number of packets dropped */
-	u_int ps_ifdrop;	/* drops by interface XXX not yet supported */
+    u_int ps_recv;      /* number of packets received */
+    u_int ps_drop;      /* number of packets dropped */
+    u_int ps_ifdrop;    /* drops by interface XXX not yet supported */
 #ifdef HAVE_REMOTE
-	u_int ps_capt;		/* number of packets that are received by the application; please get rid off the Win32 ifdef */
-	u_int ps_sent;		/* number of packets sent by the server on the network */
-	u_int ps_netdrop;	/* number of packets lost on the network */
+    u_int ps_capt;      /* number of packets that are received by the application; please get rid off the Win32 ifdef */
+    u_int ps_sent;      /* number of packets sent by the server on the network */
+    u_int ps_netdrop;   /* number of packets lost on the network */
 #endif /* HAVE_REMOTE */
 };
 
@@ -221,28 +221,28 @@ struct pcap_stat_ex {
  * Item in a list of interfaces.
  */
 struct pcap_if {
-	struct pcap_if *next;
-	char *name;		/* name to hand to "pcap_open_live()" */
-	char *description;	/* textual description of interface, or NULL */
-	struct pcap_addr *addresses;
-	bpf_u_int32 flags;	/* PCAP_IF_ interface flags */
+    struct pcap_if *next;
+    char *name;     /* name to hand to "pcap_open_live()" */
+    char *description;  /* textual description of interface, or NULL */
+    struct pcap_addr *addresses;
+    bpf_u_int32 flags;  /* PCAP_IF_ interface flags */
 };
 
-#define PCAP_IF_LOOPBACK	0x00000001	/* interface is loopback */
+#define PCAP_IF_LOOPBACK    0x00000001  /* interface is loopback */
 
 /*
  * Representation of an interface address.
  */
 struct pcap_addr {
-	struct pcap_addr *next;
-	struct sockaddr *addr;		/* address */
-	struct sockaddr *netmask;	/* netmask for that address */
-	struct sockaddr *broadaddr;	/* broadcast address for that address */
-	struct sockaddr *dstaddr;	/* P2P destination address for that address */
+    struct pcap_addr *next;
+    struct sockaddr *addr;      /* address */
+    struct sockaddr *netmask;   /* netmask for that address */
+    struct sockaddr *broadaddr; /* broadcast address for that address */
+    struct sockaddr *dstaddr;   /* P2P destination address for that address */
 };
 
 typedef void (*pcap_handler)(u_char *, const struct pcap_pkthdr *,
-			     const u_char *);
+                 const u_char *);
 
 /*
  * Error codes for the pcap API.
@@ -250,111 +250,111 @@ typedef void (*pcap_handler)(u_char *, const struct pcap_pkthdr *,
  * failure of a call that returns these codes by checking for a
  * negative value.
  */
-#define PCAP_ERROR			-1	/* generic error code */
-#define PCAP_ERROR_BREAK		-2	/* loop terminated by pcap_breakloop */
-#define PCAP_ERROR_NOT_ACTIVATED	-3	/* the capture needs to be activated */
-#define PCAP_ERROR_ACTIVATED		-4	/* the operation can't be performed on already activated captures */
-#define PCAP_ERROR_NO_SUCH_DEVICE	-5	/* no such device exists */
-#define PCAP_ERROR_RFMON_NOTSUP		-6	/* this device doesn't support rfmon (monitor) mode */
-#define PCAP_ERROR_NOT_RFMON		-7	/* operation supported only in monitor mode */
-#define PCAP_ERROR_PERM_DENIED		-8	/* no permission to open the device */
-#define PCAP_ERROR_IFACE_NOT_UP		-9	/* interface isn't up */
+#define PCAP_ERROR          -1  /* generic error code */
+#define PCAP_ERROR_BREAK        -2  /* loop terminated by pcap_breakloop */
+#define PCAP_ERROR_NOT_ACTIVATED    -3  /* the capture needs to be activated */
+#define PCAP_ERROR_ACTIVATED        -4  /* the operation can't be performed on already activated captures */
+#define PCAP_ERROR_NO_SUCH_DEVICE   -5  /* no such device exists */
+#define PCAP_ERROR_RFMON_NOTSUP     -6  /* this device doesn't support rfmon (monitor) mode */
+#define PCAP_ERROR_NOT_RFMON        -7  /* operation supported only in monitor mode */
+#define PCAP_ERROR_PERM_DENIED      -8  /* no permission to open the device */
+#define PCAP_ERROR_IFACE_NOT_UP     -9  /* interface isn't up */
 
 /*
  * Warning codes for the pcap API.
  * These will all be positive and non-zero, so they won't look like
  * errors.
  */
-#define PCAP_WARNING			1	/* generic warning code */
-#define PCAP_WARNING_PROMISC_NOTSUP	2	/* this device doesn't support promiscuous mode */
+#define PCAP_WARNING            1   /* generic warning code */
+#define PCAP_WARNING_PROMISC_NOTSUP 2   /* this device doesn't support promiscuous mode */
 
-char	*pcap_lookupdev(char *);
-int	pcap_lookupnet(const char *, bpf_u_int32 *, bpf_u_int32 *, char *);
+char    *pcap_lookupdev(char *);
+int pcap_lookupnet(const char *, bpf_u_int32 *, bpf_u_int32 *, char *);
 
-pcap_t	*pcap_create(const char *, char *);
-int	pcap_set_snaplen(pcap_t *, int);
-int	pcap_set_promisc(pcap_t *, int);
-int	pcap_can_set_rfmon(pcap_t *);
-int	pcap_set_rfmon(pcap_t *, int);
-int	pcap_set_timeout(pcap_t *, int);
-int	pcap_set_buffer_size(pcap_t *, int);
-int	pcap_activate(pcap_t *);
+pcap_t  *pcap_create(const char *, char *);
+int pcap_set_snaplen(pcap_t *, int);
+int pcap_set_promisc(pcap_t *, int);
+int pcap_can_set_rfmon(pcap_t *);
+int pcap_set_rfmon(pcap_t *, int);
+int pcap_set_timeout(pcap_t *, int);
+int pcap_set_buffer_size(pcap_t *, int);
+int pcap_activate(pcap_t *);
 
-pcap_t	*pcap_open_live(const char *, int, int, int, char *);
-pcap_t	*pcap_open_dead(int, int);
-pcap_t	*pcap_open_offline(const char *, char *);
+pcap_t  *pcap_open_live(const char *, int, int, int, char *);
+pcap_t  *pcap_open_dead(int, int);
+pcap_t  *pcap_open_offline(const char *, char *);
 #if defined(WIN32)
 pcap_t  *pcap_hopen_offline(intptr_t, char *);
 #if !defined(LIBPCAP_EXPORTS)
 #define pcap_fopen_offline(f,b) \
-	pcap_hopen_offline(_get_osfhandle(_fileno(f)), b)
+    pcap_hopen_offline(_get_osfhandle(_fileno(f)), b)
 #else /*LIBPCAP_EXPORTS*/
 static pcap_t *pcap_fopen_offline(FILE *, char *);
 #endif
 #else /*WIN32*/
-pcap_t	*pcap_fopen_offline(FILE *, char *);
+pcap_t  *pcap_fopen_offline(FILE *, char *);
 #endif /*WIN32*/
 
-void	pcap_close(pcap_t *);
-int	pcap_loop(pcap_t *, int, pcap_handler, u_char *);
-int	pcap_dispatch(pcap_t *, int, pcap_handler, u_char *);
+void    pcap_close(pcap_t *);
+int pcap_loop(pcap_t *, int, pcap_handler, u_char *);
+int pcap_dispatch(pcap_t *, int, pcap_handler, u_char *);
 const u_char*
-	pcap_next(pcap_t *, struct pcap_pkthdr *);
-int 	pcap_next_ex(pcap_t *, struct pcap_pkthdr **, const u_char **);
-void	pcap_breakloop(pcap_t *);
-int	pcap_stats(pcap_t *, struct pcap_stat *);
-int	pcap_setfilter(pcap_t *, struct bpf_program *);
-int 	pcap_setdirection(pcap_t *, pcap_direction_t);
-int	pcap_getnonblock(pcap_t *, char *);
-int	pcap_setnonblock(pcap_t *, int, char *);
-int	pcap_inject(pcap_t *, const void *, size_t);
-int	pcap_sendpacket(pcap_t *, const u_char *, int);
+    pcap_next(pcap_t *, struct pcap_pkthdr *);
+int     pcap_next_ex(pcap_t *, struct pcap_pkthdr **, const u_char **);
+void    pcap_breakloop(pcap_t *);
+int pcap_stats(pcap_t *, struct pcap_stat *);
+int pcap_setfilter(pcap_t *, struct bpf_program *);
+int     pcap_setdirection(pcap_t *, pcap_direction_t);
+int pcap_getnonblock(pcap_t *, char *);
+int pcap_setnonblock(pcap_t *, int, char *);
+int pcap_inject(pcap_t *, const void *, size_t);
+int pcap_sendpacket(pcap_t *, const u_char *, int);
 const char *pcap_statustostr(int);
 const char *pcap_strerror(int);
-char	*pcap_geterr(pcap_t *);
-void	pcap_perror(pcap_t *, char *);
-int	pcap_compile(pcap_t *, struct bpf_program *, const char *, int,
-	    bpf_u_int32);
-int	pcap_compile_nopcap(int, int, struct bpf_program *,
-	    const char *, int, bpf_u_int32);
-void	pcap_freecode(struct bpf_program *);
-int	pcap_offline_filter(struct bpf_program *, const struct pcap_pkthdr *,
-	    const u_char *);
-int	pcap_datalink(pcap_t *);
-int	pcap_datalink_ext(pcap_t *);
-int	pcap_list_datalinks(pcap_t *, int **);
-int	pcap_set_datalink(pcap_t *, int);
-void	pcap_free_datalinks(int *);
-int	pcap_datalink_name_to_val(const char *);
+char    *pcap_geterr(pcap_t *);
+void    pcap_perror(pcap_t *, char *);
+int pcap_compile(pcap_t *, struct bpf_program *, const char *, int,
+        bpf_u_int32);
+int pcap_compile_nopcap(int, int, struct bpf_program *,
+        const char *, int, bpf_u_int32);
+void    pcap_freecode(struct bpf_program *);
+int pcap_offline_filter(struct bpf_program *, const struct pcap_pkthdr *,
+        const u_char *);
+int pcap_datalink(pcap_t *);
+int pcap_datalink_ext(pcap_t *);
+int pcap_list_datalinks(pcap_t *, int **);
+int pcap_set_datalink(pcap_t *, int);
+void    pcap_free_datalinks(int *);
+int pcap_datalink_name_to_val(const char *);
 const char *pcap_datalink_val_to_name(int);
 const char *pcap_datalink_val_to_description(int);
-int	pcap_snapshot(pcap_t *);
-int	pcap_is_swapped(pcap_t *);
-int	pcap_major_version(pcap_t *);
-int	pcap_minor_version(pcap_t *);
+int pcap_snapshot(pcap_t *);
+int pcap_is_swapped(pcap_t *);
+int pcap_major_version(pcap_t *);
+int pcap_minor_version(pcap_t *);
 
 /* XXX */
-FILE	*pcap_file(pcap_t *);
-int	pcap_fileno(pcap_t *);
+FILE    *pcap_file(pcap_t *);
+int pcap_fileno(pcap_t *);
 
 pcap_dumper_t *pcap_dump_open(pcap_t *, const char *);
 pcap_dumper_t *pcap_dump_fopen(pcap_t *, FILE *fp);
-FILE	*pcap_dump_file(pcap_dumper_t *);
-long	pcap_dump_ftell(pcap_dumper_t *);
-int	pcap_dump_flush(pcap_dumper_t *);
-void	pcap_dump_close(pcap_dumper_t *);
-void	pcap_dump(u_char *, const struct pcap_pkthdr *, const u_char *);
+FILE    *pcap_dump_file(pcap_dumper_t *);
+long    pcap_dump_ftell(pcap_dumper_t *);
+int pcap_dump_flush(pcap_dumper_t *);
+void    pcap_dump_close(pcap_dumper_t *);
+void    pcap_dump(u_char *, const struct pcap_pkthdr *, const u_char *);
 
-int	pcap_findalldevs(pcap_if_t **, char *);
-void	pcap_freealldevs(pcap_if_t *);
+int pcap_findalldevs(pcap_if_t **, char *);
+void    pcap_freealldevs(pcap_if_t *);
 
 const char *pcap_lib_version(void);
 
 /* XXX this guy lives in the bpf tree */
-u_int	bpf_filter(const struct bpf_insn *, const u_char *, u_int, u_int);
-int	bpf_validate(const struct bpf_insn *f, int len);
-char	*bpf_image(const struct bpf_insn *, int);
-void	bpf_dump(const struct bpf_program *, int);
+u_int   bpf_filter(const struct bpf_insn *, const u_char *, u_int, u_int);
+int bpf_validate(const struct bpf_insn *f, int len);
+char    *bpf_image(const struct bpf_insn *, int);
+void    bpf_dump(const struct bpf_program *, int);
 
 #if defined(WIN32)
 
@@ -391,14 +391,14 @@ u_long pcap_mac_packets (void);
  * UN*X definitions
  */
 
-int	pcap_get_selectable_fd(pcap_t *);
+int pcap_get_selectable_fd(pcap_t *);
 
 #endif /* WIN32/MSDOS/UN*X */
 
 #ifdef HAVE_REMOTE
 /* Includes most of the public stuff that is needed for the remote capture */
 #include 
-#endif	 /* HAVE_REMOTE */
+#endif   /* HAVE_REMOTE */
 
 #ifdef __cplusplus
 }
diff --git a/bsp/simulator/pcap/Include/pcap/sll.h b/bsp/simulator/pcap/Include/pcap/sll.h
index e9d5452af7..20b816b2f2 100644
--- a/bsp/simulator/pcap/Include/pcap/sll.h
+++ b/bsp/simulator/pcap/Include/pcap/sll.h
@@ -1,6 +1,6 @@
 /*-
  * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997
- *	The Regents of the University of California.  All rights reserved.
+ *  The Regents of the University of California.  All rights reserved.
  *
  * This code is derived from the Stanford/CMU enet packet filter,
  * (net/enet.c) distributed as part of 4.3BSD, and code contributed
@@ -42,22 +42,22 @@
  * For captures on Linux cooked sockets, we construct a fake header
  * that includes:
  *
- *	a 2-byte "packet type" which is one of:
+ *  a 2-byte "packet type" which is one of:
  *
- *		LINUX_SLL_HOST		packet was sent to us
- *		LINUX_SLL_BROADCAST	packet was broadcast
- *		LINUX_SLL_MULTICAST	packet was multicast
- *		LINUX_SLL_OTHERHOST	packet was sent to somebody else
- *		LINUX_SLL_OUTGOING	packet was sent *by* us;
+ *      LINUX_SLL_HOST      packet was sent to us
+ *      LINUX_SLL_BROADCAST packet was broadcast
+ *      LINUX_SLL_MULTICAST packet was multicast
+ *      LINUX_SLL_OTHERHOST packet was sent to somebody else
+ *      LINUX_SLL_OUTGOING  packet was sent *by* us;
  *
- *	a 2-byte Ethernet protocol field;
+ *  a 2-byte Ethernet protocol field;
  *
- *	a 2-byte link-layer type;
+ *  a 2-byte link-layer type;
  *
- *	a 2-byte link-layer address length;
+ *  a 2-byte link-layer address length;
  *
- *	an 8-byte source link-layer address, whose actual length is
- *	specified by the previous value.
+ *  an 8-byte source link-layer address, whose actual length is
+ *  specified by the previous value.
  *
  * All fields except for the link-layer address are in network byte order.
  *
@@ -79,15 +79,15 @@
 /*
  * A DLT_LINUX_SLL fake link-layer header.
  */
-#define SLL_HDR_LEN	16		/* total header length */
-#define SLL_ADDRLEN	8		/* length of address field */
+#define SLL_HDR_LEN 16      /* total header length */
+#define SLL_ADDRLEN 8       /* length of address field */
 
 struct sll_header {
-	u_int16_t sll_pkttype;		/* packet type */
-	u_int16_t sll_hatype;		/* link-layer address type */
-	u_int16_t sll_halen;		/* link-layer address length */
-	u_int8_t sll_addr[SLL_ADDRLEN];	/* link-layer address */
-	u_int16_t sll_protocol;		/* protocol */
+    u_int16_t sll_pkttype;      /* packet type */
+    u_int16_t sll_hatype;       /* link-layer address type */
+    u_int16_t sll_halen;        /* link-layer address length */
+    u_int8_t sll_addr[SLL_ADDRLEN]; /* link-layer address */
+    u_int16_t sll_protocol;     /* protocol */
 };
 
 /*
@@ -96,11 +96,11 @@ struct sll_header {
  * available even on systems other than Linux, and so that they
  * don't change even if the PACKET_ values change.
  */
-#define LINUX_SLL_HOST		0
-#define LINUX_SLL_BROADCAST	1
-#define LINUX_SLL_MULTICAST	2
-#define LINUX_SLL_OTHERHOST	3
-#define LINUX_SLL_OUTGOING	4
+#define LINUX_SLL_HOST      0
+#define LINUX_SLL_BROADCAST 1
+#define LINUX_SLL_MULTICAST 2
+#define LINUX_SLL_OTHERHOST 3
+#define LINUX_SLL_OUTGOING  4
 
 /*
  * The LINUX_SLL_ values for "sll_protocol"; these correspond to the
@@ -108,22 +108,22 @@ struct sll_header {
  * available even on systems other than Linux.  We assume, for now,
  * that the ETH_P_ values won't change in Linux; if they do, then:
  *
- *	if we don't translate them in "pcap-linux.c", capture files
- *	won't necessarily be readable if captured on a system that
- *	defines ETH_P_ values that don't match these values;
+ *  if we don't translate them in "pcap-linux.c", capture files
+ *  won't necessarily be readable if captured on a system that
+ *  defines ETH_P_ values that don't match these values;
  *
- *	if we do translate them in "pcap-linux.c", that makes life
- *	unpleasant for the BPF code generator, as the values you test
- *	for in the kernel aren't the values that you test for when
- *	reading a capture file, so the fixup code run on BPF programs
- *	handed to the kernel ends up having to do more work.
+ *  if we do translate them in "pcap-linux.c", that makes life
+ *  unpleasant for the BPF code generator, as the values you test
+ *  for in the kernel aren't the values that you test for when
+ *  reading a capture file, so the fixup code run on BPF programs
+ *  handed to the kernel ends up having to do more work.
  *
  * Add other values here as necessary, for handling packet types that
  * might show up on non-Ethernet, non-802.x networks.  (Not all the ones
  * in the Linux "if_ether.h" will, I suspect, actually show up in
  * captures.)
  */
-#define LINUX_SLL_P_802_3	0x0001	/* Novell 802.3 frames without 802.2 LLC header */
-#define LINUX_SLL_P_802_2	0x0004	/* 802.2 frames (not D/I/X Ethernet) */
+#define LINUX_SLL_P_802_3   0x0001  /* Novell 802.3 frames without 802.2 LLC header */
+#define LINUX_SLL_P_802_2   0x0004  /* 802.2 frames (not D/I/X Ethernet) */
 
 #endif
diff --git a/bsp/simulator/pcap/Include/pcap/usb.h b/bsp/simulator/pcap/Include/pcap/usb.h
index adcd19c058..4837fe4ac1 100644
--- a/bsp/simulator/pcap/Include/pcap/usb.h
+++ b/bsp/simulator/pcap/Include/pcap/usb.h
@@ -11,8 +11,8 @@
  * 2. Redistributions in binary form must reproduce the above copyright
  * notice, this list of conditions and the following disclaimer in the
  * documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote 
- * products derived from this software without specific prior written 
+ * 3. The name of the author may not be used to endorse or promote
+ * products derived from this software without specific prior written
  * permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
@@ -32,11 +32,11 @@
  *
  * @(#) $Header: /tcpdump/master/libpcap/pcap/usb.h,v 1.6 2007/09/22 02:06:08 guy Exp $
  */
- 
+
 #ifndef _PCAP_USB_STRUCTS_H__
 #define _PCAP_USB_STRUCTS_H__
 
-/* 
+/*
  * possible transfer mode
  */
 #define URB_TRANSFER_IN   0x80
@@ -57,11 +57,11 @@
  * Appears at the front of each packet in DLT_USB captures.
  */
 typedef struct _usb_setup {
-	u_int8_t bmRequestType;
-	u_int8_t bRequest;
-	u_int16_t wValue;
-	u_int16_t wIndex;
-	u_int16_t wLength;
+    u_int8_t bmRequestType;
+    u_int8_t bRequest;
+    u_int16_t wValue;
+    u_int16_t wIndex;
+    u_int16_t wLength;
 } pcap_usb_setup;
 
 
@@ -70,20 +70,20 @@ typedef struct _usb_setup {
  * Appears at the front of each packet in DLT_USB_LINUX captures.
  */
 typedef struct _usb_header {
-	u_int64_t id;
-	u_int8_t event_type;
-	u_int8_t transfer_type;
-	u_int8_t endpoint_number;
-	u_int8_t device_address;
-	u_int16_t bus_id;
-	char setup_flag;/*if !=0 the urb setup header is not present*/
-	char data_flag; /*if !=0 no urb data is present*/
-	int64_t ts_sec;
-	int32_t ts_usec;
-	int32_t status;
-	u_int32_t urb_len;
-	u_int32_t data_len; /* amount of urb data really present in this event*/
-	pcap_usb_setup setup;
+    u_int64_t id;
+    u_int8_t event_type;
+    u_int8_t transfer_type;
+    u_int8_t endpoint_number;
+    u_int8_t device_address;
+    u_int16_t bus_id;
+    char setup_flag;/*if !=0 the urb setup header is not present*/
+    char data_flag; /*if !=0 no urb data is present*/
+    int64_t ts_sec;
+    int32_t ts_usec;
+    int32_t status;
+    u_int32_t urb_len;
+    u_int32_t data_len; /* amount of urb data really present in this event*/
+    pcap_usb_setup setup;
 } pcap_usb_header;
 
 
diff --git a/bsp/simulator/pcap/Include/pcap/vlan.h b/bsp/simulator/pcap/Include/pcap/vlan.h
index b0cb7949be..b9fa284c35 100644
--- a/bsp/simulator/pcap/Include/pcap/vlan.h
+++ b/bsp/simulator/pcap/Include/pcap/vlan.h
@@ -1,6 +1,6 @@
 /*-
  * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997
- *	The Regents of the University of California.  All rights reserved.
+ *  The Regents of the University of California.  All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -37,10 +37,10 @@
 #define lib_pcap_vlan_h
 
 struct vlan_tag {
-	u_int16_t	vlan_tpid;		/* ETH_P_8021Q */
-	u_int16_t	vlan_tci;		/* VLAN TCI */
+    u_int16_t   vlan_tpid;      /* ETH_P_8021Q */
+    u_int16_t   vlan_tci;       /* VLAN TCI */
 };
 
-#define VLAN_TAG_LEN	4
+#define VLAN_TAG_LEN    4
 
 #endif
diff --git a/bsp/simulator/pcap/Include/remote-ext.h b/bsp/simulator/pcap/Include/remote-ext.h
index 35a2fff6c2..34e4efba3a 100644
--- a/bsp/simulator/pcap/Include/remote-ext.h
+++ b/bsp/simulator/pcap/Include/remote-ext.h
@@ -2,32 +2,32 @@
  * Copyright (c) 2002 - 2003
  * NetGroup, Politecnico di Torino (Italy)
  * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without 
- * modification, are permitted provided that the following conditions 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
  * are met:
- * 
- * 1. Redistributions of source code must retain the above copyright 
+ *
+ * 1. Redistributions of source code must retain the above copyright
  * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright 
- * notice, this list of conditions and the following disclaimer in the 
- * documentation and/or other materials provided with the distribution. 
- * 3. Neither the name of the Politecnico di Torino nor the names of its 
- * contributors may be used to endorse or promote products derived from 
- * this software without specific prior written permission. 
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the Politecnico di Torino nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
+ *
  */
 
 
@@ -49,135 +49,135 @@ extern "C" {
 #endif
 
 /*!
-	\file remote-ext.h
+    \file remote-ext.h
 
-	The goal of this file it to include most of the new definitions that should be
-	placed into the pcap.h file.
+    The goal of this file it to include most of the new definitions that should be
+    placed into the pcap.h file.
 
-	It includes all new definitions (structures and functions like pcap_open().
-    Some of the functions are not really a remote feature, but, right now, 
-	they are placed here.
+    It includes all new definitions (structures and functions like pcap_open().
+    Some of the functions are not really a remote feature, but, right now,
+    they are placed here.
 */
 
 
 
 // All this stuff is public
 /*! \addtogroup remote_struct
-	\{
+    \{
 */
 
 
 
 
 /*!
-	\brief Defines the maximum buffer size in which address, port, interface names are kept.
+    \brief Defines the maximum buffer size in which address, port, interface names are kept.
 
-	In case the adapter name or such is larger than this value, it is truncated.
-	This is not used by the user; however it must be aware that an hostname / interface
-	name longer than this value will be truncated.
+    In case the adapter name or such is larger than this value, it is truncated.
+    This is not used by the user; however it must be aware that an hostname / interface
+    name longer than this value will be truncated.
 */
 #define PCAP_BUF_SIZE 1024
 
 
 /*! \addtogroup remote_source_ID
-	\{
+    \{
 */
 
 
 /*!
-	\brief Internal representation of the type of source in use (file, 
-	remote/local interface).
+    \brief Internal representation of the type of source in use (file,
+    remote/local interface).
 
-	This indicates a file, i.e. the user want to open a capture from a local file.
+    This indicates a file, i.e. the user want to open a capture from a local file.
 */
 #define PCAP_SRC_FILE 2
 /*!
-	\brief Internal representation of the type of source in use (file, 
-	remote/local interface).
+    \brief Internal representation of the type of source in use (file,
+    remote/local interface).
 
-	This indicates a local interface, i.e. the user want to open a capture from 
-	a local interface. This does not involve the RPCAP protocol.
+    This indicates a local interface, i.e. the user want to open a capture from
+    a local interface. This does not involve the RPCAP protocol.
 */
 #define PCAP_SRC_IFLOCAL 3
 /*!
-	\brief Internal representation of the type of source in use (file, 
-	remote/local interface).
+    \brief Internal representation of the type of source in use (file,
+    remote/local interface).
 
-	This indicates a remote interface, i.e. the user want to open a capture from 
-	an interface on a remote host. This does involve the RPCAP protocol.
+    This indicates a remote interface, i.e. the user want to open a capture from
+    an interface on a remote host. This does involve the RPCAP protocol.
 */
 #define PCAP_SRC_IFREMOTE 4
 
 /*!
-	\}
+    \}
 */
 
 
 
 /*! \addtogroup remote_source_string
 
-	The formats allowed by the pcap_open() are the following:
-	- file://path_and_filename [opens a local file]
-	- rpcap://devicename [opens the selected device devices available on the local host, without using the RPCAP protocol]
-	- rpcap://host/devicename [opens the selected device available on a remote host]
-	- rpcap://host:port/devicename [opens the selected device available on a remote host, using a non-standard port for RPCAP]
-	- adaptername [to open a local adapter; kept for compability, but it is strongly discouraged]
-	- (NULL) [to open the first local adapter; kept for compability, but it is strongly discouraged]
+    The formats allowed by the pcap_open() are the following:
+    - file://path_and_filename [opens a local file]
+    - rpcap://devicename [opens the selected device devices available on the local host, without using the RPCAP protocol]
+    - rpcap://host/devicename [opens the selected device available on a remote host]
+    - rpcap://host:port/devicename [opens the selected device available on a remote host, using a non-standard port for RPCAP]
+    - adaptername [to open a local adapter; kept for compability, but it is strongly discouraged]
+    - (NULL) [to open the first local adapter; kept for compability, but it is strongly discouraged]
 
-	The formats allowed by the pcap_findalldevs_ex() are the following:
-	- file://folder/ [lists all the files in the given folder]
-	- rpcap:// [lists all local adapters]
-	- rpcap://host:port/ [lists the devices available on a remote host]
+    The formats allowed by the pcap_findalldevs_ex() are the following:
+    - file://folder/ [lists all the files in the given folder]
+    - rpcap:// [lists all local adapters]
+    - rpcap://host:port/ [lists the devices available on a remote host]
 
-	Referring to the 'host' and 'port' paramters, they can be either numeric or literal. Since
-	IPv6 is fully supported, these are the allowed formats:
+    Referring to the 'host' and 'port' paramters, they can be either numeric or literal. Since
+    IPv6 is fully supported, these are the allowed formats:
 
-	- host (literal): e.g. host.foo.bar
-	- host (numeric IPv4): e.g. 10.11.12.13
-	- host (numeric IPv4, IPv6 style): e.g. [10.11.12.13]
-	- host (numeric IPv6): e.g. [1:2:3::4]
-	- port: can be either numeric (e.g. '80') or literal (e.g. 'http')
+    - host (literal): e.g. host.foo.bar
+    - host (numeric IPv4): e.g. 10.11.12.13
+    - host (numeric IPv4, IPv6 style): e.g. [10.11.12.13]
+    - host (numeric IPv6): e.g. [1:2:3::4]
+    - port: can be either numeric (e.g. '80') or literal (e.g. 'http')
 
-	Here you find some allowed examples:
-	- rpcap://host.foo.bar/devicename [everything literal, no port number]
-	- rpcap://host.foo.bar:1234/devicename [everything literal, with port number]
-	- rpcap://10.11.12.13/devicename [IPv4 numeric, no port number]
-	- rpcap://10.11.12.13:1234/devicename [IPv4 numeric, with port number]
-	- rpcap://[10.11.12.13]:1234/devicename [IPv4 numeric with IPv6 format, with port number]
-	- rpcap://[1:2:3::4]/devicename [IPv6 numeric, no port number]
-	- rpcap://[1:2:3::4]:1234/devicename [IPv6 numeric, with port number]
-	- rpcap://[1:2:3::4]:http/devicename [IPv6 numeric, with literal port number]
-	
-	\{
+    Here you find some allowed examples:
+    - rpcap://host.foo.bar/devicename [everything literal, no port number]
+    - rpcap://host.foo.bar:1234/devicename [everything literal, with port number]
+    - rpcap://10.11.12.13/devicename [IPv4 numeric, no port number]
+    - rpcap://10.11.12.13:1234/devicename [IPv4 numeric, with port number]
+    - rpcap://[10.11.12.13]:1234/devicename [IPv4 numeric with IPv6 format, with port number]
+    - rpcap://[1:2:3::4]/devicename [IPv6 numeric, no port number]
+    - rpcap://[1:2:3::4]:1234/devicename [IPv6 numeric, with port number]
+    - rpcap://[1:2:3::4]:http/devicename [IPv6 numeric, with literal port number]
+
+    \{
 */
 
 
 /*!
-	\brief String that will be used to determine the type of source in use (file,
-	remote/local interface).
+    \brief String that will be used to determine the type of source in use (file,
+    remote/local interface).
 
-	This string will be prepended to the interface name in order to create a string
-	that contains all the information required to open the source.
+    This string will be prepended to the interface name in order to create a string
+    that contains all the information required to open the source.
 
-	This string indicates that the user wants to open a capture from a local file.
+    This string indicates that the user wants to open a capture from a local file.
 */
 #define PCAP_SRC_FILE_STRING "file://"
 /*!
-	\brief String that will be used to determine the type of source in use (file,
-	remote/local interface).
+    \brief String that will be used to determine the type of source in use (file,
+    remote/local interface).
 
-	This string will be prepended to the interface name in order to create a string
-	that contains all the information required to open the source.
+    This string will be prepended to the interface name in order to create a string
+    that contains all the information required to open the source.
 
-	This string indicates that the user wants to open a capture from a network interface.
-	This string does not necessarily involve the use of the RPCAP protocol. If the
-	interface required resides on the local host, the RPCAP protocol is not involved
-	and the local functions are used.
+    This string indicates that the user wants to open a capture from a network interface.
+    This string does not necessarily involve the use of the RPCAP protocol. If the
+    interface required resides on the local host, the RPCAP protocol is not involved
+    and the local functions are used.
 */
 #define PCAP_SRC_IF_STRING "rpcap://"
 
 /*!
-	\}
+    \}
 */
 
 
@@ -185,137 +185,137 @@ extern "C" {
 
 
 /*!
-	\addtogroup remote_open_flags
-	\{
+    \addtogroup remote_open_flags
+    \{
 */
 
 /*!
-	\brief Defines if the adapter has to go in promiscuous mode.
+    \brief Defines if the adapter has to go in promiscuous mode.
 
-	It is '1' if you have to open the adapter in promiscuous mode, '0' otherwise.
-	Note that even if this parameter is false, the interface could well be in promiscuous
-	mode for some other reason (for example because another capture process with 
-	promiscuous mode enabled is currently using that interface).
-	On on Linux systems with 2.2 or later kernels (that have the "any" device), this
-	flag does not work on the "any" device; if an argument of "any" is supplied,
-	the 'promisc' flag is ignored.
+    It is '1' if you have to open the adapter in promiscuous mode, '0' otherwise.
+    Note that even if this parameter is false, the interface could well be in promiscuous
+    mode for some other reason (for example because another capture process with
+    promiscuous mode enabled is currently using that interface).
+    On on Linux systems with 2.2 or later kernels (that have the "any" device), this
+    flag does not work on the "any" device; if an argument of "any" is supplied,
+    the 'promisc' flag is ignored.
 */
-#define PCAP_OPENFLAG_PROMISCUOUS		1
+#define PCAP_OPENFLAG_PROMISCUOUS       1
 
 /*!
-	\brief Defines if the data trasfer (in case of a remote
-	capture) has to be done with UDP protocol.
+    \brief Defines if the data trasfer (in case of a remote
+    capture) has to be done with UDP protocol.
 
-	If it is '1' if you want a UDP data connection, '0' if you want
-	a TCP data connection; control connection is always TCP-based.
-	A UDP connection is much lighter, but it does not guarantee that all
-	the captured packets arrive to the client workstation. Moreover, 
-	it could be harmful in case of network congestion.
-	This flag is meaningless if the source is not a remote interface.
-	In that case, it is simply ignored.
+    If it is '1' if you want a UDP data connection, '0' if you want
+    a TCP data connection; control connection is always TCP-based.
+    A UDP connection is much lighter, but it does not guarantee that all
+    the captured packets arrive to the client workstation. Moreover,
+    it could be harmful in case of network congestion.
+    This flag is meaningless if the source is not a remote interface.
+    In that case, it is simply ignored.
 */
-#define PCAP_OPENFLAG_DATATX_UDP			2
+#define PCAP_OPENFLAG_DATATX_UDP            2
 
 
 /*!
-	\brief Defines if the remote probe will capture its own generated traffic.
+    \brief Defines if the remote probe will capture its own generated traffic.
 
-	In case the remote probe uses the same interface to capture traffic and to send
-	data back to the caller, the captured traffic includes the RPCAP traffic as well.
-	If this flag is turned on, the RPCAP traffic is excluded from the capture, so that
-	the trace returned back to the collector is does not include this traffic.
+    In case the remote probe uses the same interface to capture traffic and to send
+    data back to the caller, the captured traffic includes the RPCAP traffic as well.
+    If this flag is turned on, the RPCAP traffic is excluded from the capture, so that
+    the trace returned back to the collector is does not include this traffic.
 */
-#define PCAP_OPENFLAG_NOCAPTURE_RPCAP	4
+#define PCAP_OPENFLAG_NOCAPTURE_RPCAP   4
 
 /*!
-	\brief Defines if the local adapter will capture its own generated traffic.
+    \brief Defines if the local adapter will capture its own generated traffic.
 
-	This flag tells the underlying capture driver to drop the packets that were sent by itself. 
-	This is usefult when building applications like bridges, that should ignore the traffic
-	they just sent.
+    This flag tells the underlying capture driver to drop the packets that were sent by itself.
+    This is usefult when building applications like bridges, that should ignore the traffic
+    they just sent.
 */
-#define PCAP_OPENFLAG_NOCAPTURE_LOCAL	8
+#define PCAP_OPENFLAG_NOCAPTURE_LOCAL   8
 
 /*!
-	\brief This flag configures the adapter for maximum responsiveness.
+    \brief This flag configures the adapter for maximum responsiveness.
 
-	In presence of a large value for nbytes, WinPcap waits for the arrival of several packets before 
-	copying the data to the user. This guarantees a low number of system calls, i.e. lower processor usage, 
-	i.e. better performance, which is good for applications like sniffers. If the user sets the 
-	PCAP_OPENFLAG_MAX_RESPONSIVENESS flag, the capture driver will copy the packets as soon as the application 
-	is ready to receive them. This is suggested for real time applications (like, for example, a bridge) 
-	that need the best responsiveness.*/
-#define PCAP_OPENFLAG_MAX_RESPONSIVENESS	16
+    In presence of a large value for nbytes, WinPcap waits for the arrival of several packets before
+    copying the data to the user. This guarantees a low number of system calls, i.e. lower processor usage,
+    i.e. better performance, which is good for applications like sniffers. If the user sets the
+    PCAP_OPENFLAG_MAX_RESPONSIVENESS flag, the capture driver will copy the packets as soon as the application
+    is ready to receive them. This is suggested for real time applications (like, for example, a bridge)
+    that need the best responsiveness.*/
+#define PCAP_OPENFLAG_MAX_RESPONSIVENESS    16
 
 /*!
-	\}
+    \}
 */
 
 
 /*!
-	\addtogroup remote_samp_methods
-	\{
+    \addtogroup remote_samp_methods
+    \{
 */
 
 /*!
-	\brief No sampling has to be done on the current capture.
+    \brief No sampling has to be done on the current capture.
 
-	In this case, no sampling algorithms are applied to the current capture.
+    In this case, no sampling algorithms are applied to the current capture.
 */
-#define PCAP_SAMP_NOSAMP	0
+#define PCAP_SAMP_NOSAMP    0
 
 /*!
-	\brief It defines that only 1 out of N packets must be returned to the user.
+    \brief It defines that only 1 out of N packets must be returned to the user.
 
-	In this case, the 'value' field of the 'pcap_samp' structure indicates the
-	number of packets (minus 1) that must be discarded before one packet got accepted.
-	In other words, if 'value = 10', the first packet is returned to the caller, while
-	the following 9 are discarded.
+    In this case, the 'value' field of the 'pcap_samp' structure indicates the
+    number of packets (minus 1) that must be discarded before one packet got accepted.
+    In other words, if 'value = 10', the first packet is returned to the caller, while
+    the following 9 are discarded.
 */
-#define PCAP_SAMP_1_EVERY_N	1
+#define PCAP_SAMP_1_EVERY_N 1
 
 /*!
-	\brief It defines that we have to return 1 packet every N milliseconds.
+    \brief It defines that we have to return 1 packet every N milliseconds.
 
-	In this case, the 'value' field of the 'pcap_samp' structure indicates the 'waiting
-	time' in milliseconds before one packet got accepted.
-	In other words, if 'value = 10', the first packet is returned to the caller; the next 
-	returned one will be the first packet that arrives when 10ms have elapsed. 
+    In this case, the 'value' field of the 'pcap_samp' structure indicates the 'waiting
+    time' in milliseconds before one packet got accepted.
+    In other words, if 'value = 10', the first packet is returned to the caller; the next
+    returned one will be the first packet that arrives when 10ms have elapsed.
 */
 #define PCAP_SAMP_FIRST_AFTER_N_MS 2
 
 /*!
-	\}
+    \}
 */
 
 
 /*!
-	\addtogroup remote_auth_methods
-	\{
+    \addtogroup remote_auth_methods
+    \{
 */
 
 /*!
-	\brief It defines the NULL authentication.
+    \brief It defines the NULL authentication.
 
-	This value has to be used within the 'type' member of the pcap_rmtauth structure.
-	The 'NULL' authentication has to be equal to 'zero', so that old applications
-	can just put every field of struct pcap_rmtauth to zero, and it does work.
+    This value has to be used within the 'type' member of the pcap_rmtauth structure.
+    The 'NULL' authentication has to be equal to 'zero', so that old applications
+    can just put every field of struct pcap_rmtauth to zero, and it does work.
 */
 #define RPCAP_RMTAUTH_NULL 0
 /*!
-	\brief It defines the username/password authentication.
+    \brief It defines the username/password authentication.
 
-	With this type of authentication, the RPCAP protocol will use the username/
-	password provided to authenticate the user on the remote machine. If the
-	authentication is successful (and the user has the right to open network devices)
-	the RPCAP connection will continue; otherwise it will be dropped.
+    With this type of authentication, the RPCAP protocol will use the username/
+    password provided to authenticate the user on the remote machine. If the
+    authentication is successful (and the user has the right to open network devices)
+    the RPCAP connection will continue; otherwise it will be dropped.
 
-	This value has to be used within the 'type' member of the pcap_rmtauth structure.
+    This value has to be used within the 'type' member of the pcap_rmtauth structure.
 */
 #define RPCAP_RMTAUTH_PWD 1
 
 /*!
-	\}
+    \}
 */
 
 
@@ -323,73 +323,73 @@ extern "C" {
 
 /*!
 
-	\brief This structure keeps the information needed to autheticate
-	the user on a remote machine.
-	
-	The remote machine can either grant or refuse the access according 
-	to the information provided.
-	In case the NULL authentication is required, both 'username' and
-	'password' can be NULL pointers.
-	
-	This structure is meaningless if the source is not a remote interface;
-	in that case, the functions which requires such a structure can accept
-	a NULL pointer as well.
+    \brief This structure keeps the information needed to autheticate
+    the user on a remote machine.
+
+    The remote machine can either grant or refuse the access according
+    to the information provided.
+    In case the NULL authentication is required, both 'username' and
+    'password' can be NULL pointers.
+
+    This structure is meaningless if the source is not a remote interface;
+    in that case, the functions which requires such a structure can accept
+    a NULL pointer as well.
 */
 struct pcap_rmtauth
 {
-	/*!
-		\brief Type of the authentication required.
+    /*!
+        \brief Type of the authentication required.
 
-		In order to provide maximum flexibility, we can support different types
-		of authentication based on the value of this 'type' variable. The currently 
-		supported authentication methods are defined into the
-		\link remote_auth_methods Remote Authentication Methods Section\endlink.
+        In order to provide maximum flexibility, we can support different types
+        of authentication based on the value of this 'type' variable. The currently
+        supported authentication methods are defined into the
+        \link remote_auth_methods Remote Authentication Methods Section\endlink.
 
-	*/
-	int type;
-	/*!
-		\brief Zero-terminated string containing the username that has to be 
-		used on the remote machine for authentication.
-		
-		This field is meaningless in case of the RPCAP_RMTAUTH_NULL authentication
-		and it can be NULL.
-	*/
-	char *username;
-	/*!
-		\brief Zero-terminated string containing the password that has to be 
-		used on the remote machine for authentication.
-		
-		This field is meaningless in case of the RPCAP_RMTAUTH_NULL authentication
-		and it can be NULL.
-	*/
-	char *password;
+    */
+    int type;
+    /*!
+        \brief Zero-terminated string containing the username that has to be
+        used on the remote machine for authentication.
+
+        This field is meaningless in case of the RPCAP_RMTAUTH_NULL authentication
+        and it can be NULL.
+    */
+    char *username;
+    /*!
+        \brief Zero-terminated string containing the password that has to be
+        used on the remote machine for authentication.
+
+        This field is meaningless in case of the RPCAP_RMTAUTH_NULL authentication
+        and it can be NULL.
+    */
+    char *password;
 };
 
 
 /*!
-	\brief This structure defines the information related to sampling.
+    \brief This structure defines the information related to sampling.
 
-	In case the sampling is requested, the capturing device should read
-	only a subset of the packets coming from the source. The returned packets depend
-	on the sampling parameters.
+    In case the sampling is requested, the capturing device should read
+    only a subset of the packets coming from the source. The returned packets depend
+    on the sampling parameters.
 
-	\warning The sampling process is applied after the filtering process.
-	In other words, packets are filtered first, then the sampling process selects a
-	subset of the 'filtered' packets and it returns them to the caller.
+    \warning The sampling process is applied after the filtering process.
+    In other words, packets are filtered first, then the sampling process selects a
+    subset of the 'filtered' packets and it returns them to the caller.
 */
 struct pcap_samp
 {
-	/*!
-		Method used for sampling. Currently, the supported methods are listed in the
-		\link remote_samp_methods Sampling Methods Section\endlink.
-	*/
-	int method;
+    /*!
+        Method used for sampling. Currently, the supported methods are listed in the
+        \link remote_samp_methods Sampling Methods Section\endlink.
+    */
+    int method;
 
-	/*!
-		This value depends on the sampling method defined. For its meaning, please check
-		at the \link remote_samp_methods Sampling Methods Section\endlink.
-	*/
-	int value;
+    /*!
+        This value depends on the sampling method defined. For its meaning, please check
+        at the \link remote_samp_methods Sampling Methods Section\endlink.
+    */
+    int value;
 };
 
 
@@ -400,7 +400,7 @@ struct pcap_samp
 
 
 /*!
-	\}
+    \}
 */ // end of public documentation
 
 
@@ -410,8 +410,8 @@ struct pcap_samp
 
 /** \name New WinPcap functions
 
-	This section lists the new functions that are able to help considerably in writing
-	WinPcap programs because of their easiness of use.
+    This section lists the new functions that are able to help considerably in writing
+    WinPcap programs because of their easiness of use.
  */
 //\{
 pcap_t *pcap_open(const char *source, int snaplen, int flags, int read_timeout, struct pcap_rmtauth *auth, char *errbuf);
@@ -427,7 +427,7 @@ struct pcap_samp *pcap_setsampling(pcap_t *p);
 
 /** \name Remote Capture functions
  */
-//\{ 
+//\{
 SOCKET pcap_remoteact_accept(const char *address, const char *port, const char *hostlist, char *connectinghost, struct pcap_rmtauth *auth, char *errbuf);
 int pcap_remoteact_list(char *hostlist, char sep, int size, char *errbuf);
 int pcap_remoteact_close(const char *host, char *errbuf);
diff --git a/bsp/simulator/pcap/pcap_netif.c b/bsp/simulator/pcap/pcap_netif.c
index d6572c3045..0aef477185 100644
--- a/bsp/simulator/pcap/pcap_netif.c
+++ b/bsp/simulator/pcap/pcap_netif.c
@@ -1,11 +1,7 @@
 /*
- * File      : pcap_netif.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -37,12 +33,12 @@
 
 struct pcap_netif
 {
-	/* inherit from ethernet device */
-	struct eth_device parent;
+    /* inherit from ethernet device */
+    struct eth_device parent;
 
     pcap_t *tap;
-	/* interface address info. */
-	rt_uint8_t  dev_addr[MAX_ADDR_LEN];		/* hw address	*/
+    /* interface address info. */
+    rt_uint8_t  dev_addr[MAX_ADDR_LEN];     /* hw address   */
 };
 static struct pcap_netif pcap_netif_device;
 static struct rt_semaphore sem_lock;
@@ -61,7 +57,7 @@ static void pcap_thread_entry(void* parameter)
 
     /* Open the adapter */
     if ((tap = pcap_open_live(netif->name,
-        65536, // portion of the packet to capture. 
+        65536, // portion of the packet to capture.
         1,     // promiscuous mode (nonzero means promiscuous)
         1,     // read timeout, 0 blocked, -1 no timeout
         errbuf )) == NULL)
@@ -88,7 +84,7 @@ static void pcap_thread_entry(void* parameter)
 
         p = pbuf_alloc(PBUF_LINK, header->len, PBUF_RAM);
         pbuf_take(p, pkt_data, header->len);
-        
+
         /* send to packet mailbox */
         rt_mb_send_wait(packet_mb, (rt_uint32_t)p, RT_WAITING_FOREVER);
         /* notify eth rx thread to receive packet */
@@ -134,7 +130,7 @@ static rt_err_t pcap_netif_init(rt_device_t dev)
     {
         rt_kprintf("Select (%s) as network interface\n", d->description);
         packet_mb = rt_mb_create("pcap", 64, RT_IPC_FLAG_FIFO);
-        tid = rt_thread_create("pcap", pcap_thread_entry, d, 
+        tid = rt_thread_create("pcap", pcap_thread_entry, d,
             2048, RT_THREAD_PRIORITY_MAX - 1, 10);
         if (tid != RT_NULL)
         {
@@ -151,7 +147,7 @@ static rt_err_t pcap_netif_init(rt_device_t dev)
 
 static rt_err_t pcap_netif_open(rt_device_t dev, rt_uint16_t oflag)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t pcap_netif_close(rt_device_t dev)
@@ -161,42 +157,42 @@ static rt_err_t pcap_netif_close(rt_device_t dev)
     tap = NETIF_PCAP(dev);
 
     pcap_close(tap);
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_size_t pcap_netif_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
 {
-	rt_set_errno(-RT_ENOSYS);
-	return 0;
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
 }
 
 static rt_size_t pcap_netif_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
 {
-	rt_set_errno(-RT_ENOSYS);
-	return 0;
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
 }
 
 static rt_err_t pcap_netif_control(rt_device_t dev, int cmd, void *args)
 {
-	switch (cmd)
-	{
-	case NIOCTL_GADDR:
-		/* get mac address */
-		if (args) rt_memcpy(args, pcap_netif_device.dev_addr, 6);
-		else return -RT_ERROR;
-		break;
+    switch (cmd)
+    {
+    case NIOCTL_GADDR:
+        /* get mac address */
+        if (args) rt_memcpy(args, pcap_netif_device.dev_addr, 6);
+        else return -RT_ERROR;
+        break;
 
-	default :
-		break;
-	}
+    default :
+        break;
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 rt_err_t pcap_netif_tx( rt_device_t dev, struct pbuf* p)
 {
-	struct pbuf *q;
-	rt_uint8_t *ptr;
+    struct pbuf *q;
+    rt_uint8_t *ptr;
     rt_uint8_t buf[2048];
     rt_err_t result = RT_EOK;
     pcap_t *tap;
@@ -204,18 +200,18 @@ rt_err_t pcap_netif_tx( rt_device_t dev, struct pbuf* p)
 
     tap = NETIF_PCAP(dev);
 
-	/* lock EMAC device */
-	rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
+    /* lock EMAC device */
+    rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
 
-	/* copy data to tx buffer */
-	q = p;
-	ptr = (rt_uint8_t*)buf;
-	while (q)
-	{
-		memcpy(ptr, q->payload, q->len);
-		ptr += q->len;
-		q = q->next;
-	}
+    /* copy data to tx buffer */
+    q = p;
+    ptr = (rt_uint8_t*)buf;
+    while (q)
+    {
+        memcpy(ptr, q->payload, q->len);
+        ptr += q->len;
+        q = q->next;
+    }
 
     rt_enter_critical();
     res = pcap_sendpacket(tap, buf, p->tot_len);
@@ -227,15 +223,15 @@ rt_err_t pcap_netif_tx( rt_device_t dev, struct pbuf* p)
         result = -RT_ERROR;
     }
 
-	/* unlock EMAC device */
-	rt_sem_release(&sem_lock);
+    /* unlock EMAC device */
+    rt_sem_release(&sem_lock);
 
     return result;
 }
 
 struct pbuf *pcap_netif_rx(rt_device_t dev)
 {
-	struct pbuf* p = RT_NULL;
+    struct pbuf* p = RT_NULL;
 
     rt_mb_recv(packet_mb, (rt_uint32_t*)&p, 0);
 
@@ -244,28 +240,28 @@ struct pbuf *pcap_netif_rx(rt_device_t dev)
 
 void pcap_netif_hw_init(void)
 {
-	rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
+    rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
 
-	pcap_netif_device.dev_addr[0] = 0x00;
-	pcap_netif_device.dev_addr[1] = 0x60;
-	pcap_netif_device.dev_addr[2] = 0x37;
-	/* set mac address: (only for test) */
-	pcap_netif_device.dev_addr[3] = 0x12;
-	pcap_netif_device.dev_addr[4] = 0x34;
-	pcap_netif_device.dev_addr[5] = 0x56;
+    pcap_netif_device.dev_addr[0] = 0x00;
+    pcap_netif_device.dev_addr[1] = 0x60;
+    pcap_netif_device.dev_addr[2] = 0x37;
+    /* set mac address: (only for test) */
+    pcap_netif_device.dev_addr[3] = 0x12;
+    pcap_netif_device.dev_addr[4] = 0x34;
+    pcap_netif_device.dev_addr[5] = 0x56;
 
-	pcap_netif_device.parent.parent.init		= pcap_netif_init;
-	pcap_netif_device.parent.parent.open		= pcap_netif_open;
-	pcap_netif_device.parent.parent.close		= pcap_netif_close;
-	pcap_netif_device.parent.parent.read		= pcap_netif_read;
-	pcap_netif_device.parent.parent.write		= pcap_netif_write;
-	pcap_netif_device.parent.parent.control	    = pcap_netif_control;
-	pcap_netif_device.parent.parent.user_data	= RT_NULL;
+    pcap_netif_device.parent.parent.init        = pcap_netif_init;
+    pcap_netif_device.parent.parent.open        = pcap_netif_open;
+    pcap_netif_device.parent.parent.close       = pcap_netif_close;
+    pcap_netif_device.parent.parent.read        = pcap_netif_read;
+    pcap_netif_device.parent.parent.write       = pcap_netif_write;
+    pcap_netif_device.parent.parent.control     = pcap_netif_control;
+    pcap_netif_device.parent.parent.user_data   = RT_NULL;
 
-	pcap_netif_device.parent.eth_rx			= pcap_netif_rx;
-	pcap_netif_device.parent.eth_tx			= pcap_netif_tx;
+    pcap_netif_device.parent.eth_rx         = pcap_netif_rx;
+    pcap_netif_device.parent.eth_tx         = pcap_netif_tx;
 
-	eth_device_init(&(pcap_netif_device.parent), "e0");
+    eth_device_init(&(pcap_netif_device.parent), "e0");
 }
 
 #include 
diff --git a/bsp/simulator/rtconfig.h b/bsp/simulator/rtconfig.h
index be93c902bb..6b5f356593 100755
--- a/bsp/simulator/rtconfig.h
+++ b/bsp/simulator/rtconfig.h
@@ -39,10 +39,14 @@
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "console"
-#define RT_VER_NUM 0x40002
+#define RT_VER_NUM 0x40003
 
 /* RT-Thread Components */
 
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
 
 /* C++ features */
 
@@ -77,6 +81,8 @@
 #define RT_DFS_ELM_WORD_ACCESS
 #define RT_DFS_ELM_USE_LFN_0
 #define RT_DFS_ELM_USE_LFN 0
+#define RT_DFS_ELM_LFN_UNICODE_0
+#define RT_DFS_ELM_LFN_UNICODE 0
 #define RT_DFS_ELM_MAX_LFN 255
 #define RT_DFS_ELM_DRIVES 2
 #define RT_DFS_ELM_MAX_SECTOR_SIZE 512
@@ -96,6 +102,7 @@
 
 /* POSIX layer and C standard library */
 
+#define RT_LIBC_USING_TIME
 
 /* Network */
 
@@ -148,14 +155,24 @@
 /* system packages */
 
 
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
 /* peripheral libraries and drivers */
 
 
+/* AI packages */
+
+
 /* miscellaneous packages */
 
 
 /* samples: kernel and components samples */
 
+
+/* entertainment: terminal games and other interesting software packages */
+
+#define SOC_SIMULATOR
 #define RT_USING_DFS_WINSHAREDIR
 #include "rtconfig_project.h"
 
diff --git a/bsp/simulator/rtconfig_project.h b/bsp/simulator/rtconfig_project.h
index 02e29c1a65..098255741e 100644
--- a/bsp/simulator/rtconfig_project.h
+++ b/bsp/simulator/rtconfig_project.h
@@ -1,3 +1,12 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
 #ifndef RTCONFIG_PROJECT_H__
 #define RTCONFIG_PROJECT_H__
 
@@ -10,16 +19,13 @@
 #define _INC_TIME_INL //dfs_elm.c time.h conflicts with wtime.inl
 
 /* disable some warning in MSC */
-#pragma warning(disable:4273)	/* to ignore: warning C4273: inconsistent dll linkage */
+#pragma warning(disable:4273)   /* to ignore: warning C4273: inconsistent dll linkage */
 #pragma warning(disable:4312)   /* to ignore: warning C4312: 'type cast' : conversion from 'rt_uint32_t' to 'rt_uint32_t *' */
 #pragma warning(disable:4311)   /* to ignore: warning C4311: 'type cast' : pointer truncation from 'short *__w64 ' to 'long' */
 #pragma warning(disable:4996)   /* to ignore: warning C4996: The POSIX name for this item is deprecated. */
 #pragma warning(disable:4267)   /* to ignore: warning C4267: conversion from 'size_t' to 'rt_size_t', possible loss of data */
 #pragma warning(disable:4244)   /* to ignore: warning C4244: '=' : conversion from '__w64 int' to 'rt_size_t', possible loss of data */
 
-#elif defined(__GNUC__)
-#define RT_USING_NOLIBC
-
 #endif /* end of _MSC_VER */
 
 #endif
diff --git a/bsp/smartfusion2/project.uvopt b/bsp/smartfusion2/project.uvopt
index 99ce043dfe..51eba0e604 100644
--- a/bsp/smartfusion2/project.uvopt
+++ b/bsp/smartfusion2/project.uvopt
@@ -110,10 +110,10 @@
         1
         0
         1
-        1
+        0
         1
         1
-        0
+        1
         0
         0
         6
@@ -177,7 +177,7 @@
   
 
   
-    Kernel
+    Applications
     0
     0
     0
@@ -193,8 +193,8 @@
       0
       0
       0
-      ..\..\src\clock.c
-      clock.c
+      applications\main.c
+      main.c
       0
       0
     
@@ -209,246 +209,14 @@
       0
       0
       0
-      ..\..\src\components.c
-      components.c
-      0
-      0
-    
-    
-      1
-      3
-      1
-      0
-      0
-      0
-      0
-      0
-      0
-      0
-      ..\..\src\device.c
-      device.c
-      0
-      0
-    
-    
-      1
-      4
-      1
-      0
-      0
-      0
-      0
-      0
-      0
-      0
-      ..\..\src\idle.c
-      idle.c
-      0
-      0
-    
-    
-      1
-      5
-      1
-      0
-      0
-      0
-      0
-      0
-      0
-      0
-      ..\..\src\ipc.c
-      ipc.c
-      0
-      0
-    
-    
-      1
-      6
-      1
-      0
-      0
-      0
-      0
-      0
-      0
-      0
-      ..\..\src\irq.c
-      irq.c
-      0
-      0
-    
-    
-      1
-      7
-      1
-      0
-      0
-      0
-      0
-      0
-      0
-      0
-      ..\..\src\kservice.c
-      kservice.c
-      0
-      0
-    
-    
-      1
-      8
-      1
-      0
-      0
-      0
-      0
-      0
-      0
-      0
-      ..\..\src\mem.c
-      mem.c
-      0
-      0
-    
-    
-      1
-      9
-      1
-      0
-      0
-      0
-      0
-      0
-      0
-      0
-      ..\..\src\mempool.c
-      mempool.c
-      0
-      0
-    
-    
-      1
-      10
-      1
-      0
-      0
-      0
-      0
-      0
-      0
-      0
-      ..\..\src\object.c
-      object.c
-      0
-      0
-    
-    
-      1
-      11
-      1
-      0
-      0
-      0
-      0
-      0
-      0
-      0
-      ..\..\src\scheduler.c
-      scheduler.c
-      0
-      0
-    
-    
-      1
-      12
-      1
-      0
-      0
-      0
-      0
-      0
-      0
-      0
-      ..\..\src\signal.c
-      signal.c
-      0
-      0
-    
-    
-      1
-      13
-      1
-      0
-      0
-      0
-      0
-      0
-      0
-      0
-      ..\..\src\thread.c
-      thread.c
-      0
-      0
-    
-    
-      1
-      14
-      1
-      0
-      0
-      0
-      0
-      0
-      0
-      0
-      ..\..\src\timer.c
-      timer.c
-      0
-      0
-    
-  
-
-  
-    Applications
-    1
-    0
-    0
-    0
-    
-      2
-      15
-      1
-      0
-      0
-      14
-      0
-      1
-      16
-      0
-      applications\main.c
-      main.c
-      0
-      0
-    
-    
-      2
-      16
-      1
-      0
-      0
-      0
-      0
-      0
-      0
-      0
       board\board.c
       board.c
       0
       0
     
     
-      2
-      17
+      1
+      3
       1
       0
       0
@@ -471,8 +239,8 @@
     0
     0
     
-      3
-      18
+      2
+      4
       1
       0
       0
@@ -487,8 +255,8 @@
       0
     
     
-      3
-      19
+      2
+      5
       1
       0
       0
@@ -503,8 +271,8 @@
       0
     
     
-      3
-      20
+      2
+      6
       2
       0
       0
@@ -521,110 +289,14 @@
   
 
   
-    Drivers
-    1
-    0
-    0
-    0
-    
-      4
-      21
-      1
-      0
-      0
-      0
-      0
-      0
-      0
-      0
-      drivers\drv_uart.c
-      drv_uart.c
-      0
-      0
-    
-    
-      4
-      22
-      1
-      0
-      0
-      0
-      0
-      0
-      0
-      0
-      drivers\drv_gpio.c
-      drv_gpio.c
-      0
-      0
-    
-  
-
-  
-    Libraries
-    1
-    0
-    0
-    0
-    
-      5
-      23
-      1
-      0
-      0
-      0
-      0
-      0
-      0
-      0
-      libraries\sys_config\sys_config.c
-      sys_config.c
-      0
-      0
-    
-    
-      5
-      24
-      1
-      0
-      0
-      0
-      0
-      0
-      0
-      0
-      libraries\mss_gpio\mss_gpio.c
-      mss_gpio.c
-      0
-      0
-    
-    
-      5
-      25
-      1
-      0
-      0
-      0
-      0
-      0
-      0
-      0
-      libraries\mss_uart\mss_uart.c
-      mss_uart.c
-      0
-      0
-    
-  
-
-  
-    cpu
+    CPU
     0
     0
     0
     0
     
-      6
-      26
+      3
+      7
       1
       0
       0
@@ -639,8 +311,8 @@
       0
     
     
-      6
-      27
+      3
+      8
       1
       0
       0
@@ -655,8 +327,8 @@
       0
     
     
-      6
-      28
+      3
+      9
       1
       0
       0
@@ -671,8 +343,8 @@
       0
     
     
-      6
-      29
+      3
+      10
       1
       0
       0
@@ -687,8 +359,8 @@
       0
     
     
-      6
-      30
+      3
+      11
       2
       0
       0
@@ -711,8 +383,8 @@
     0
     0
     
-      7
-      31
+      4
+      12
       1
       0
       0
@@ -727,8 +399,8 @@
       0
     
     
-      7
-      32
+      4
+      13
       1
       0
       0
@@ -743,8 +415,8 @@
       0
     
     
-      7
-      33
+      4
+      14
       1
       0
       0
@@ -759,8 +431,8 @@
       0
     
     
-      7
-      34
+      4
+      15
       1
       0
       0
@@ -775,8 +447,8 @@
       0
     
     
-      7
-      35
+      4
+      16
       1
       0
       0
@@ -791,8 +463,8 @@
       0
     
     
-      7
-      36
+      4
+      17
       1
       0
       0
@@ -807,8 +479,8 @@
       0
     
     
-      7
-      37
+      4
+      18
       1
       0
       0
@@ -823,8 +495,8 @@
       0
     
     
-      7
-      38
+      4
+      19
       1
       0
       0
@@ -839,8 +511,8 @@
       0
     
     
-      7
-      39
+      4
+      20
       1
       0
       0
@@ -856,6 +528,46 @@
     
   
 
+  
+    Drivers
+    0
+    0
+    0
+    0
+    
+      5
+      21
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      drivers\drv_uart.c
+      drv_uart.c
+      0
+      0
+    
+    
+      5
+      22
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      drivers\drv_gpio.c
+      drv_gpio.c
+      0
+      0
+    
+  
+
   
     finsh
     0
@@ -863,8 +575,8 @@
     0
     0
     
-      8
-      40
+      6
+      23
       1
       0
       0
@@ -879,8 +591,8 @@
       0
     
     
-      8
-      41
+      6
+      24
       1
       0
       0
@@ -895,8 +607,8 @@
       0
     
     
-      8
-      42
+      6
+      25
       1
       0
       0
@@ -912,6 +624,222 @@
     
   
 
+  
+    Kernel
+    0
+    0
+    0
+    0
+    
+      7
+      26
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      ..\..\src\clock.c
+      clock.c
+      0
+      0
+    
+    
+      7
+      27
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      ..\..\src\components.c
+      components.c
+      0
+      0
+    
+    
+      7
+      28
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      ..\..\src\device.c
+      device.c
+      0
+      0
+    
+    
+      7
+      29
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      ..\..\src\idle.c
+      idle.c
+      0
+      0
+    
+    
+      7
+      30
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      ..\..\src\ipc.c
+      ipc.c
+      0
+      0
+    
+    
+      7
+      31
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      ..\..\src\irq.c
+      irq.c
+      0
+      0
+    
+    
+      7
+      32
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      ..\..\src\kservice.c
+      kservice.c
+      0
+      0
+    
+    
+      7
+      33
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      ..\..\src\mem.c
+      mem.c
+      0
+      0
+    
+    
+      7
+      34
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      ..\..\src\mempool.c
+      mempool.c
+      0
+      0
+    
+    
+      7
+      35
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      ..\..\src\object.c
+      object.c
+      0
+      0
+    
+    
+      7
+      36
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      ..\..\src\scheduler.c
+      scheduler.c
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+    
+    
+      7
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+      0
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+      thread.c
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+    
+    
+      7
+      38
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      ..\..\src\timer.c
+      timer.c
+      0
+      0
+    
+  
+
   
     libc
     0
@@ -919,8 +847,8 @@
     0
     0
     
-      9
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@@ -935,8 +863,8 @@
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@@ -951,8 +879,8 @@
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-      9
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       1
       0
       0
@@ -961,14 +889,30 @@
       0
       0
       0
-      ..\..\components\libc\compilers\armlibc\stubs.c
-      stubs.c
+      ..\..\components\libc\compilers\armlibc\syscalls.c
+      syscalls.c
       0
       0
     
     
-      9
-      46
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+      ..\..\components\libc\compilers\common\stdlib.c
+      stdlib.c
+      0
+      0
+    
+    
+      8
+      43
       1
       0
       0
@@ -984,4 +928,60 @@
     
   
 
+  
+    Libraries
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+    
+      9
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+      1
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+      0
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+      libraries\sys_config\sys_config.c
+      sys_config.c
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+    
+      9
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+      libraries\mss_gpio\mss_gpio.c
+      mss_gpio.c
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+    
+      9
+      46
+      1
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+      0
+      0
+      0
+      0
+      0
+      0
+      libraries\mss_uart\mss_uart.c
+      mss_uart.c
+      0
+      0
+    
+  
+
 
diff --git a/bsp/smartfusion2/project.uvoptx b/bsp/smartfusion2/project.uvoptx
index a83e5093d3..57f994ae2b 100644
--- a/bsp/smartfusion2/project.uvoptx
+++ b/bsp/smartfusion2/project.uvoptx
@@ -175,7 +175,7 @@
   
 
   
-    Kernel
+    Applications
     0
     0
     0
@@ -187,8 +187,8 @@
       0
       0
       0
-      ..\..\src\clock.c
-      clock.c
+      applications\main.c
+      main.c
       0
       0
     
@@ -199,190 +199,14 @@
       0
       0
       0
-      ..\..\src\components.c
-      components.c
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-    
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-      ..\..\src\idle.c
-      idle.c
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-    
-    
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-      ..\..\src\ipc.c
-      ipc.c
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-    
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-      6
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-      ..\..\src\irq.c
-      irq.c
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-    
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-      ..\..\src\kservice.c
-      kservice.c
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-      ..\..\src\scheduler.c
-      scheduler.c
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-    
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-      ..\..\src\signal.c
-      signal.c
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-    
-    
-      1
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-      1
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-      ..\..\src\thread.c
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-    
-    
-      1
-      14
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-      ..\..\src\timer.c
-      timer.c
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-  
-
-  
-    Applications
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-    
-      2
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-      1
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-      0
       board\board.c
       board.c
       0
       0
     
     
-      2
-      17
+      1
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@@ -401,8 +225,8 @@
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     0
     
-      3
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@@ -413,8 +237,8 @@
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       0
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@@ -425,8 +249,8 @@
       0
     
     
-      3
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       2
       0
       0
@@ -439,90 +263,14 @@
   
 
   
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-      drivers\drv_gpio.c
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-  
-
-  
-    Libraries
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-      libraries\mss_uart\mss_uart.c
-      mss_uart.c
-      0
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-    
-  
-
-  
-    cpu
+    CPU
     0
     0
     0
     0
     
-      6
-      26
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       0
       0
@@ -533,8 +281,8 @@
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@@ -545,8 +293,8 @@
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@@ -557,8 +305,8 @@
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@@ -569,8 +317,8 @@
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@@ -589,8 +337,8 @@
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@@ -601,8 +349,8 @@
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@@ -613,8 +361,8 @@
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@@ -625,8 +373,8 @@
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@@ -637,8 +385,8 @@
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@@ -649,8 +397,8 @@
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@@ -661,8 +409,8 @@
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@@ -673,8 +421,8 @@
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@@ -685,8 +433,8 @@
       0
     
     
-      7
-      39
+      4
+      20
       1
       0
       0
@@ -698,6 +446,38 @@
     
   
 
+  
+    Drivers
+    0
+    0
+    0
+    0
+    
+      5
+      21
+      1
+      0
+      0
+      0
+      drivers\drv_uart.c
+      drv_uart.c
+      0
+      0
+    
+    
+      5
+      22
+      1
+      0
+      0
+      0
+      drivers\drv_gpio.c
+      drv_gpio.c
+      0
+      0
+    
+  
+
   
     finsh
     0
@@ -705,8 +485,8 @@
     0
     0
     
-      8
-      40
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@@ -717,8 +497,8 @@
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@@ -729,8 +509,8 @@
       0
     
     
-      8
-      42
+      6
+      25
       1
       0
       0
@@ -742,6 +522,170 @@
     
   
 
+  
+    Kernel
+    0
+    0
+    0
+    0
+    
+      7
+      26
+      1
+      0
+      0
+      0
+      ..\..\src\clock.c
+      clock.c
+      0
+      0
+    
+    
+      7
+      27
+      1
+      0
+      0
+      0
+      ..\..\src\components.c
+      components.c
+      0
+      0
+    
+    
+      7
+      28
+      1
+      0
+      0
+      0
+      ..\..\src\device.c
+      device.c
+      0
+      0
+    
+    
+      7
+      29
+      1
+      0
+      0
+      0
+      ..\..\src\idle.c
+      idle.c
+      0
+      0
+    
+    
+      7
+      30
+      1
+      0
+      0
+      0
+      ..\..\src\ipc.c
+      ipc.c
+      0
+      0
+    
+    
+      7
+      31
+      1
+      0
+      0
+      0
+      ..\..\src\irq.c
+      irq.c
+      0
+      0
+    
+    
+      7
+      32
+      1
+      0
+      0
+      0
+      ..\..\src\kservice.c
+      kservice.c
+      0
+      0
+    
+    
+      7
+      33
+      1
+      0
+      0
+      0
+      ..\..\src\mem.c
+      mem.c
+      0
+      0
+    
+    
+      7
+      34
+      1
+      0
+      0
+      0
+      ..\..\src\mempool.c
+      mempool.c
+      0
+      0
+    
+    
+      7
+      35
+      1
+      0
+      0
+      0
+      ..\..\src\object.c
+      object.c
+      0
+      0
+    
+    
+      7
+      36
+      1
+      0
+      0
+      0
+      ..\..\src\scheduler.c
+      scheduler.c
+      0
+      0
+    
+    
+      7
+      37
+      1
+      0
+      0
+      0
+      ..\..\src\thread.c
+      thread.c
+      0
+      0
+    
+    
+      7
+      38
+      1
+      0
+      0
+      0
+      ..\..\src\timer.c
+      timer.c
+      0
+      0
+    
+  
+
   
     libc
     0
@@ -749,8 +693,8 @@
     0
     0
     
-      9
-      43
+      8
+      39
       1
       0
       0
@@ -761,8 +705,8 @@
       0
     
     
-      9
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+      8
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       1
       0
       0
@@ -773,20 +717,32 @@
       0
     
     
-      9
-      45
+      8
+      41
       1
       0
       0
       0
-      ..\..\components\libc\compilers\armlibc\stubs.c
-      stubs.c
+      ..\..\components\libc\compilers\armlibc\syscalls.c
+      syscalls.c
       0
       0
     
     
-      9
-      46
+      8
+      42
+      1
+      0
+      0
+      0
+      ..\..\components\libc\compilers\common\stdlib.c
+      stdlib.c
+      0
+      0
+    
+    
+      8
+      43
       1
       0
       0
@@ -798,4 +754,48 @@
     
   
 
+  
+    Libraries
+    0
+    0
+    0
+    0
+    
+      9
+      44
+      1
+      0
+      0
+      0
+      libraries\sys_config\sys_config.c
+      sys_config.c
+      0
+      0
+    
+    
+      9
+      45
+      1
+      0
+      0
+      0
+      libraries\mss_gpio\mss_gpio.c
+      mss_gpio.c
+      0
+      0
+    
+    
+      9
+      46
+      1
+      0
+      0
+      0
+      libraries\mss_uart\mss_uart.c
+      mss_uart.c
+      0
+      0
+    
+  
+
 
diff --git a/bsp/smartfusion2/project.uvproj b/bsp/smartfusion2/project.uvproj
index 34dc365986..2ee7c71eee 100644
--- a/bsp/smartfusion2/project.uvproj
+++ b/bsp/smartfusion2/project.uvproj
@@ -139,9 +139,9 @@
             1
             0
             1
-            1
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             1
-            0
+            1
           
           0
           6
@@ -170,7 +170,7 @@
             0
             -1
           
-          1
+          0
           BIN\UL2CM3.DLL
           
           
@@ -356,13 +356,13 @@
             0
             0
             0
-            0
+            1
             0
             
               
-              RT_USING_ARM_LIBC
+              RT_USING_ARM_LIBC, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND
               
-              .;..\..\include;applications;board;CMSIS;drivers;libraries\sys_config;libraries\mss_gpio;libraries\mss_uart;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m3;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common
+              applications;board;CMSIS;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m3;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;drivers;..\..\components\finsh;.;..\..\include;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common;libraries\sys_config;libraries\mss_gpio;libraries\mss_uart
             
           
           
@@ -402,81 +402,6 @@
         
       
       
-        
-          Kernel
-          
-            
-              clock.c
-              1
-              ..\..\src\clock.c
-            
-            
-              components.c
-              1
-              ..\..\src\components.c
-            
-            
-              device.c
-              1
-              ..\..\src\device.c
-            
-            
-              idle.c
-              1
-              ..\..\src\idle.c
-            
-            
-              ipc.c
-              1
-              ..\..\src\ipc.c
-            
-            
-              irq.c
-              1
-              ..\..\src\irq.c
-            
-            
-              kservice.c
-              1
-              ..\..\src\kservice.c
-            
-            
-              mem.c
-              1
-              ..\..\src\mem.c
-            
-            
-              mempool.c
-              1
-              ..\..\src\mempool.c
-            
-            
-              object.c
-              1
-              ..\..\src\object.c
-            
-            
-              scheduler.c
-              1
-              ..\..\src\scheduler.c
-            
-            
-              signal.c
-              1
-              ..\..\src\signal.c
-            
-            
-              thread.c
-              1
-              ..\..\src\thread.c
-            
-            
-              timer.c
-              1
-              ..\..\src\timer.c
-            
-          
-        
         
           Applications
           
@@ -518,42 +443,7 @@
           
         
         
-          Drivers
-          
-            
-              drv_uart.c
-              1
-              drivers\drv_uart.c
-            
-            
-              drv_gpio.c
-              1
-              drivers\drv_gpio.c
-            
-          
-        
-        
-          Libraries
-          
-            
-              sys_config.c
-              1
-              libraries\sys_config\sys_config.c
-            
-            
-              mss_gpio.c
-              1
-              libraries\mss_gpio\mss_gpio.c
-            
-            
-              mss_uart.c
-              1
-              libraries\mss_uart\mss_uart.c
-            
-          
-        
-        
-          cpu
+          CPU
           
             
               backtrace.c
@@ -632,6 +522,21 @@
             
           
         
+        
+          Drivers
+          
+            
+              drv_uart.c
+              1
+              drivers\drv_uart.c
+            
+            
+              drv_gpio.c
+              1
+              drivers\drv_gpio.c
+            
+          
+        
         
           finsh
           
@@ -652,6 +557,76 @@
             
           
         
+        
+          Kernel
+          
+            
+              clock.c
+              1
+              ..\..\src\clock.c
+            
+            
+              components.c
+              1
+              ..\..\src\components.c
+            
+            
+              device.c
+              1
+              ..\..\src\device.c
+            
+            
+              idle.c
+              1
+              ..\..\src\idle.c
+            
+            
+              ipc.c
+              1
+              ..\..\src\ipc.c
+            
+            
+              irq.c
+              1
+              ..\..\src\irq.c
+            
+            
+              kservice.c
+              1
+              ..\..\src\kservice.c
+            
+            
+              mem.c
+              1
+              ..\..\src\mem.c
+            
+            
+              mempool.c
+              1
+              ..\..\src\mempool.c
+            
+            
+              object.c
+              1
+              ..\..\src\object.c
+            
+            
+              scheduler.c
+              1
+              ..\..\src\scheduler.c
+            
+            
+              thread.c
+              1
+              ..\..\src\thread.c
+            
+            
+              timer.c
+              1
+              ..\..\src\timer.c
+            
+          
+        
         
           libc
           
@@ -666,9 +641,14 @@
               ..\..\components\libc\compilers\armlibc\mem_std.c
             
             
-              stubs.c
+              syscalls.c
               1
-              ..\..\components\libc\compilers\armlibc\stubs.c
+              ..\..\components\libc\compilers\armlibc\syscalls.c
+            
+            
+              stdlib.c
+              1
+              ..\..\components\libc\compilers\common\stdlib.c
             
             
               time.c
@@ -677,6 +657,26 @@
             
           
         
+        
+          Libraries
+          
+            
+              sys_config.c
+              1
+              libraries\sys_config\sys_config.c
+            
+            
+              mss_gpio.c
+              1
+              libraries\mss_gpio\mss_gpio.c
+            
+            
+              mss_uart.c
+              1
+              libraries\mss_uart\mss_uart.c
+            
+          
+        
       
     
   
diff --git a/bsp/smartfusion2/project.uvprojx b/bsp/smartfusion2/project.uvprojx
index 16914df12d..738524c6cb 100644
--- a/bsp/smartfusion2/project.uvprojx
+++ b/bsp/smartfusion2/project.uvprojx
@@ -10,7 +10,7 @@
       project
       0x4
       ARM-ADS
-      5060750::V5.06 update 6 (build 750)::ARMCC
+      5060750::V5.06 update 6 (build 750)::.\ARMCC
       0
       
         
@@ -185,6 +185,7 @@
             0
             0
             0
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             8
@@ -324,7 +325,7 @@
             2
             0
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@@ -336,9 +337,9 @@
             0
             
               
-              RT_USING_ARM_LIBC
+              RT_USING_ARM_LIBC, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND
               
-              .;..\..\include;applications;board;CMSIS;drivers;libraries\sys_config;libraries\mss_gpio;libraries\mss_uart;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m3;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common
+              applications;board;CMSIS;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m3;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;drivers;..\..\components\finsh;.;..\..\include;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common;libraries\sys_config;libraries\mss_gpio;libraries\mss_uart
             
           
           
@@ -351,7 +352,7 @@
             0
             0
             0
-            0
+            4
             
               
               
@@ -379,81 +380,6 @@
         
       
       
-        
-          Kernel
-          
-            
-              clock.c
-              1
-              ..\..\src\clock.c
-            
-            
-              components.c
-              1
-              ..\..\src\components.c
-            
-            
-              device.c
-              1
-              ..\..\src\device.c
-            
-            
-              idle.c
-              1
-              ..\..\src\idle.c
-            
-            
-              ipc.c
-              1
-              ..\..\src\ipc.c
-            
-            
-              irq.c
-              1
-              ..\..\src\irq.c
-            
-            
-              kservice.c
-              1
-              ..\..\src\kservice.c
-            
-            
-              mem.c
-              1
-              ..\..\src\mem.c
-            
-            
-              mempool.c
-              1
-              ..\..\src\mempool.c
-            
-            
-              object.c
-              1
-              ..\..\src\object.c
-            
-            
-              scheduler.c
-              1
-              ..\..\src\scheduler.c
-            
-            
-              signal.c
-              1
-              ..\..\src\signal.c
-            
-            
-              thread.c
-              1
-              ..\..\src\thread.c
-            
-            
-              timer.c
-              1
-              ..\..\src\timer.c
-            
-          
-        
         
           Applications
           
@@ -495,42 +421,7 @@
           
         
         
-          Drivers
-          
-            
-              drv_uart.c
-              1
-              drivers\drv_uart.c
-            
-            
-              drv_gpio.c
-              1
-              drivers\drv_gpio.c
-            
-          
-        
-        
-          Libraries
-          
-            
-              sys_config.c
-              1
-              libraries\sys_config\sys_config.c
-            
-            
-              mss_gpio.c
-              1
-              libraries\mss_gpio\mss_gpio.c
-            
-            
-              mss_uart.c
-              1
-              libraries\mss_uart\mss_uart.c
-            
-          
-        
-        
-          cpu
+          CPU
           
             
               backtrace.c
@@ -609,6 +500,21 @@
             
           
         
+        
+          Drivers
+          
+            
+              drv_uart.c
+              1
+              drivers\drv_uart.c
+            
+            
+              drv_gpio.c
+              1
+              drivers\drv_gpio.c
+            
+          
+        
         
           finsh
           
@@ -629,6 +535,76 @@
             
           
         
+        
+          Kernel
+          
+            
+              clock.c
+              1
+              ..\..\src\clock.c
+            
+            
+              components.c
+              1
+              ..\..\src\components.c
+            
+            
+              device.c
+              1
+              ..\..\src\device.c
+            
+            
+              idle.c
+              1
+              ..\..\src\idle.c
+            
+            
+              ipc.c
+              1
+              ..\..\src\ipc.c
+            
+            
+              irq.c
+              1
+              ..\..\src\irq.c
+            
+            
+              kservice.c
+              1
+              ..\..\src\kservice.c
+            
+            
+              mem.c
+              1
+              ..\..\src\mem.c
+            
+            
+              mempool.c
+              1
+              ..\..\src\mempool.c
+            
+            
+              object.c
+              1
+              ..\..\src\object.c
+            
+            
+              scheduler.c
+              1
+              ..\..\src\scheduler.c
+            
+            
+              thread.c
+              1
+              ..\..\src\thread.c
+            
+            
+              timer.c
+              1
+              ..\..\src\timer.c
+            
+          
+        
         
           libc
           
@@ -643,9 +619,14 @@
               ..\..\components\libc\compilers\armlibc\mem_std.c
             
             
-              stubs.c
+              syscalls.c
               1
-              ..\..\components\libc\compilers\armlibc\stubs.c
+              ..\..\components\libc\compilers\armlibc\syscalls.c
+            
+            
+              stdlib.c
+              1
+              ..\..\components\libc\compilers\common\stdlib.c
             
             
               time.c
@@ -654,6 +635,26 @@
             
           
         
+        
+          Libraries
+          
+            
+              sys_config.c
+              1
+              libraries\sys_config\sys_config.c
+            
+            
+              mss_gpio.c
+              1
+              libraries\mss_gpio\mss_gpio.c
+            
+            
+              mss_uart.c
+              1
+              libraries\mss_uart\mss_uart.c
+            
+          
+        
       
     
   
@@ -664,4 +665,19 @@
     
   
 
+  
+    
+      
+        <Project Info>
+        
+        
+        
+        
+        
+        0
+        1
+      
+    
+  
+
 
diff --git a/bsp/smartfusion2/template.uvopt b/bsp/smartfusion2/template.uvopt
index 70eae785e9..8735ccdd69 100644
--- a/bsp/smartfusion2/template.uvopt
+++ b/bsp/smartfusion2/template.uvopt
@@ -110,10 +110,10 @@
         1
         0
         1
-        1
+        0
         1
         1
-        0
+        1
         0
         0
         6
diff --git a/bsp/smartfusion2/template.uvproj b/bsp/smartfusion2/template.uvproj
index 99fded24dc..356db37361 100644
--- a/bsp/smartfusion2/template.uvproj
+++ b/bsp/smartfusion2/template.uvproj
@@ -139,9 +139,9 @@
             1
             0
             1
-            1
+            0
             1
-            0
+            1
           
           0
           6
@@ -170,7 +170,7 @@
             0
             -1
           
-          1
+          0
           BIN\UL2CM3.DLL
           
           
@@ -356,7 +356,7 @@
             0
             0
             0
-            0
+            1
             0
             
               
diff --git a/bsp/smartfusion2/template.uvprojx b/bsp/smartfusion2/template.uvprojx
index dbfd0815c2..56ef79c76d 100644
--- a/bsp/smartfusion2/template.uvprojx
+++ b/bsp/smartfusion2/template.uvprojx
@@ -185,6 +185,7 @@
             0
             0
             0
+            0
             0
             0
             8
@@ -324,7 +325,7 @@
             2
             0
             0
-            0
+            1
             0
             0
             1
@@ -351,7 +352,7 @@
             0
             0
             0
-            0
+            4
             
               
               
@@ -392,4 +393,19 @@
     
   
 
+  
+    
+      
+        <Project Info>
+        
+        
+        
+        
+        
+        0
+        1
+      
+    
+  
+
 
diff --git a/bsp/stm32/README.md b/bsp/stm32/README.md
index 68920bbb93..ffdf1668f2 100644
--- a/bsp/stm32/README.md
+++ b/bsp/stm32/README.md
@@ -17,7 +17,6 @@ STM32 系列 BSP 目前支持情况如下表所示：
 | [stm32f103-fire-arbitrary](stm32f103-fire-arbitrary/)  | 野火 F103 霸道开发板     |
 | [stm32f103-gizwits-gokitv21](stm32f103-gizwits-gokitv21) | GoKit V2.1开发板 |
 | [stm32f103-hw100k-ibox](stm32f103-hw100k-ibox) |  硬件十万个为什么 STM32F103 iBox 开发板 |
-| [stm32f103-mini-system](stm32f103-mini-system)        | STM32F103C8T6最小系统板  |
 | [stm32f103-onenet-nbiot](stm32f103-onenet-nbiot) | STM32F103 OneNET NB-IoT 开发板 |
 | [stm32f103-yf-ufun](stm32f103-yf-ufun) | STM32F103 yf-ufun 开发板 |
 | [stm32f107-uc-eval](stm32f107-uc-eval) | uC/Eval STM32F107 评估板（中国版） |
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f0/adc_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f0/adc_config.h
index 3615ebab52..1c432ca978 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f0/adc_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f0/adc_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f0/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f0/dma_config.h
index a8d177801c..077e03896f 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f0/dma_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f0/dma_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -27,7 +27,7 @@ extern "C" {
 #define UART1_RX_DMA_INSTANCE            DMA1_Channel3
 #define UART1_RX_DMA_IRQ                 DMA1_Ch2_3_DMA2_Ch1_2_IRQn
 #elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
-#define SPI1_DMA_RX_TX_IRQHandler       DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler 
+#define SPI1_DMA_RX_TX_IRQHandler       DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
 #define SPI1_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
 #define SPI1_RX_DMA_INSTANCE            DMA1_Channel2
 #define SPI1_RX_DMA_IRQ                 DMA1_Ch2_3_DMA2_Ch1_2_IRQn
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f0/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f0/pwm_config.h
index 9ade01dfa5..3a91b88dc9 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f0/pwm_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f0/pwm_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f0/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f0/spi_config.h
index 3d66d703e8..79523e704d 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f0/spi_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f0/spi_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -27,7 +27,7 @@ extern "C" {
     }
 #endif /* SPI1_BUS_CONFIG */
 #endif /* BSP_USING_SPI1 */
-    
+
 #ifdef BSP_SPI1_TX_USING_DMA
 #ifndef SPI1_TX_DMA_CONFIG
 #define SPI1_TX_DMA_CONFIG                          \
@@ -59,7 +59,7 @@ extern "C" {
     }
 #endif /* SPI2_BUS_CONFIG */
 #endif /* BSP_USING_SPI2 */
-    
+
 #ifdef BSP_SPI2_TX_USING_DMA
 #ifndef SPI2_TX_DMA_CONFIG
 #define SPI2_TX_DMA_CONFIG                          \
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f0/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f0/tim_config.h
index 0bba70cd43..ca37509e02 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f0/tim_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f0/tim_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f0/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f0/uart_config.h
index ea5e767aed..649ec1f4ec 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f0/uart_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f0/uart_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -49,7 +49,7 @@ extern "C" {
     }
 #endif /* UART2_CONFIG */
 #endif /* BSP_USING_UART2 */
-    
+
 #if defined(BSP_UART2_RX_USING_DMA)
 #ifndef UART2_DMA_RX_CONFIG
 #define UART2_DMA_RX_CONFIG                                            \
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/adc_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/adc_config.h
index ac0a7ca373..825aaf102e 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f1/adc_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/adc_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -29,7 +29,7 @@ extern "C" {
        .Init.DiscontinuousConvMode = DISABLE,                      \
        .Init.NbrOfDiscConversion   = 1,                            \
        .Init.ExternalTrigConv      = ADC_SOFTWARE_START,           \
-    }  
+    }
 #endif /* ADC1_CONFIG */
 #endif /* BSP_USING_ADC1 */
 
@@ -45,7 +45,7 @@ extern "C" {
        .Init.DiscontinuousConvMode = DISABLE,                      \
        .Init.NbrOfDiscConversion   = 1,                            \
        .Init.ExternalTrigConv      = ADC_SOFTWARE_START,           \
-    }  
+    }
 #endif /* ADC2_CONFIG */
 #endif /* BSP_USING_ADC2 */
 
@@ -61,7 +61,7 @@ extern "C" {
        .Init.DiscontinuousConvMode = DISABLE,                      \
        .Init.NbrOfDiscConversion   = 1,                            \
        .Init.ExternalTrigConv      = ADC_SOFTWARE_START,           \
-    }  
+    }
 #endif /* ADC3_CONFIG */
 #endif /* BSP_USING_ADC3 */
 
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/dma_config.h
index 20205c43d7..65e136a2c3 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f1/dma_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/dma_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/pulse_encoder_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/pulse_encoder_config.h
index 94dd8fcd70..1de5c72b26 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f1/pulse_encoder_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/pulse_encoder_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/pwm_config.h
index 50ea3791b6..c4d4bcf202 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f1/pwm_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/pwm_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/sdio_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/sdio_config.h
index b68d5ce6ba..16d3526188 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f1/sdio_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/sdio_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/spi_config.h
index c4bbe3708d..bf28c2fc72 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f1/spi_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/spi_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -27,7 +27,7 @@ extern "C" {
     }
 #endif /* SPI1_BUS_CONFIG */
 #endif /* BSP_USING_SPI1 */
-    
+
 #ifdef BSP_SPI1_TX_USING_DMA
 #ifndef SPI1_TX_DMA_CONFIG
 #define SPI1_TX_DMA_CONFIG                          \
@@ -59,7 +59,7 @@ extern "C" {
     }
 #endif /* SPI2_BUS_CONFIG */
 #endif /* BSP_USING_SPI2 */
-    
+
 #ifdef BSP_SPI2_TX_USING_DMA
 #ifndef SPI2_TX_DMA_CONFIG
 #define SPI2_TX_DMA_CONFIG                          \
@@ -91,7 +91,7 @@ extern "C" {
     }
 #endif /* SPI3_BUS_CONFIG */
 #endif /* BSP_USING_SPI3 */
-    
+
 #ifdef BSP_SPI3_TX_USING_DMA
 #ifndef SPI3_TX_DMA_CONFIG
 #define SPI3_TX_DMA_CONFIG                          \
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/tim_config.h
index 1d3b245dc8..07478f1465 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f1/tim_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/tim_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/uart_config.h
index a08196e996..8605d9089c 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f1/uart_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/uart_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f1/usbd_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f1/usbd_config.h
index d58b86f6d3..686055a70a 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f1/usbd_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f1/usbd_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f2/adc_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f2/adc_config.h
index bda1a06485..711dd21bbd 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f2/adc_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f2/adc_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f2/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f2/dma_config.h
index cd2161276f..df88830382 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f2/dma_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f2/dma_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -134,7 +134,7 @@ extern "C" {
 #endif
 /* DMA2 stream3 */
 
-#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)	
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
 #define SPI1_DMA_TX_IRQHandler           DMA2_Stream3_IRQHandler
 #define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
 #define SPI1_TX_DMA_INSTANCE             DMA2_Stream3
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f2/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f2/pwm_config.h
index 1a5575de0c..b8ef2d37f7 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f2/pwm_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f2/pwm_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f2/sdio_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f2/sdio_config.h
index 26fb77e260..c17ef65faf 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f2/sdio_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f2/sdio_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f2/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f2/spi_config.h
index cf1e8bcea8..b3e9507b19 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f2/spi_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f2/spi_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -27,7 +27,7 @@ extern "C" {
     }
 #endif /* SPI1_BUS_CONFIG */
 #endif /* BSP_USING_SPI1 */
-    
+
 #ifdef BSP_SPI1_TX_USING_DMA
 #ifndef SPI1_TX_DMA_CONFIG
 #define SPI1_TX_DMA_CONFIG                          \
@@ -61,7 +61,7 @@ extern "C" {
     }
 #endif /* SPI2_BUS_CONFIG */
 #endif /* BSP_USING_SPI2 */
-    
+
 #ifdef BSP_SPI2_TX_USING_DMA
 #ifndef SPI2_TX_DMA_CONFIG
 #define SPI2_TX_DMA_CONFIG                          \
@@ -95,7 +95,7 @@ extern "C" {
     }
 #endif /* SPI3_BUS_CONFIG */
 #endif /* BSP_USING_SPI3 */
-    
+
 #ifdef BSP_SPI3_TX_USING_DMA
 #ifndef SPI3_TX_DMA_CONFIG
 #define SPI3_TX_DMA_CONFIG                          \
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f2/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f2/tim_config.h
index a5b47af3a6..4484a20427 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f2/tim_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f2/tim_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f2/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f2/uart_config.h
index 6d8655fc2e..118143a82c 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f2/uart_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f2/uart_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -8,7 +8,7 @@
  * 2018-10-30     SummerGift   first version
  * 2019-01-03     zylx         modify dma support
  */
- 
+
 #ifndef __UART_CONFIG_H__
 #define __UART_CONFIG_H__
 
@@ -27,7 +27,7 @@ extern "C" {
         .irq_type = USART1_IRQn,                                    \
     }
 #endif /* UART1_CONFIG */
-		
+
 #if defined(BSP_UART1_RX_USING_DMA)
 #ifndef UART1_DMA_RX_CONFIG
 #define UART1_DMA_RX_CONFIG                                        \
@@ -74,7 +74,7 @@ extern "C" {
     }
 #endif /* UART2_DMA_RX_CONFIG */
 #endif /* BSP_UART2_RX_USING_DMA */
-		
+
 #if defined(BSP_UART2_TX_USING_DMA)
 #ifndef UART2_DMA_TX_CONFIG
 #define UART2_DMA_TX_CONFIG                                        \
@@ -109,7 +109,7 @@ extern "C" {
     }
 #endif /* UART3_DMA_RX_CONFIG */
 #endif /* BSP_UART3_RX_USING_DMA */
-		
+
 #if defined(BSP_UART3_TX_USING_DMA)
 #ifndef UART3_DMA_TX_CONFIG
 #define UART3_DMA_TX_CONFIG                                        \
@@ -179,7 +179,7 @@ extern "C" {
     }
 #endif /* UART5_DMA_RX_CONFIG */
 #endif /* BSP_UART5_RX_USING_DMA */
-		
+
 #if defined(BSP_UART5_TX_USING_DMA)
 #ifndef UART5_DMA_TX_CONFIG
 #define UART5_DMA_TX_CONFIG                                        \
@@ -214,7 +214,7 @@ extern "C" {
     }
 #endif /* UART6_DMA_RX_CONFIG */
 #endif /* BSP_UART6_RX_USING_DMA */
-		
+
 #if defined(BSP_UART6_TX_USING_DMA)
 #ifndef UART6_DMA_TX_CONFIG
 #define UART6_DMA_TX_CONFIG                                        \
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/adc_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/adc_config.h
index bda1a06485..711dd21bbd 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f4/adc_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/adc_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/dac_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/dac_config.h
index 6ca3932831..ad3eef477c 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f4/dac_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/dac_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/dma_config.h
index 17768c9a04..80d45afc79 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f4/dma_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/dma_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/pulse_encoder_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/pulse_encoder_config.h
index 53320efda1..f9534e0a4c 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f4/pulse_encoder_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/pulse_encoder_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/pwm_config.h
index 3803303493..c23abe0aec 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f4/pwm_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/pwm_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/qspi_config.h
index 8450dc257f..5089a10bdf 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f4/qspi_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/qspi_config.h
@@ -1,11 +1,11 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2018-12-22     zylx         first version 
+ * 2018-12-22     zylx         first version
  */
 
 #ifndef __QSPI_CONFIG_H__
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/sdio_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/sdio_config.h
index a8328b1da4..d26002000c 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f4/sdio_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/sdio_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/spi_config.h
index 34b0590eb3..d03b31ce8a 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f4/spi_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/spi_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -27,7 +27,7 @@ extern "C" {
     }
 #endif /* SPI1_BUS_CONFIG */
 #endif /* BSP_USING_SPI1 */
-    
+
 #ifdef BSP_SPI1_TX_USING_DMA
 #ifndef SPI1_TX_DMA_CONFIG
 #define SPI1_TX_DMA_CONFIG                          \
@@ -61,7 +61,7 @@ extern "C" {
     }
 #endif /* SPI2_BUS_CONFIG */
 #endif /* BSP_USING_SPI2 */
-    
+
 #ifdef BSP_SPI2_TX_USING_DMA
 #ifndef SPI2_TX_DMA_CONFIG
 #define SPI2_TX_DMA_CONFIG                          \
@@ -95,7 +95,7 @@ extern "C" {
     }
 #endif /* SPI3_BUS_CONFIG */
 #endif /* BSP_USING_SPI3 */
-    
+
 #ifdef BSP_SPI3_TX_USING_DMA
 #ifndef SPI3_TX_DMA_CONFIG
 #define SPI3_TX_DMA_CONFIG                          \
@@ -129,7 +129,7 @@ extern "C" {
     }
 #endif /* SPI4_BUS_CONFIG */
 #endif /* BSP_USING_SPI4 */
-    
+
 #ifdef BSP_SPI4_TX_USING_DMA
 #ifndef SPI4_TX_DMA_CONFIG
 #define SPI4_TX_DMA_CONFIG                          \
@@ -163,7 +163,7 @@ extern "C" {
     }
 #endif /* SPI5_BUS_CONFIG */
 #endif /* BSP_USING_SPI5 */
-    
+
 #ifdef BSP_SPI5_TX_USING_DMA
 #ifndef SPI5_TX_DMA_CONFIG
 #define SPI5_TX_DMA_CONFIG                          \
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/tim_config.h
index bc08f219b9..72e0239ded 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f4/tim_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/tim_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/uart_config.h
index e42b5a1a9a..acde141c67 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f4/uart_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/uart_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -8,7 +8,7 @@
  * 2018-10-30     SummerGift   first version
  * 2019-01-03     zylx         modify dma support
  */
- 
+
 #ifndef __UART_CONFIG_H__
 #define __UART_CONFIG_H__
 
@@ -27,7 +27,7 @@ extern "C" {
         .irq_type = USART1_IRQn,                                    \
     }
 #endif /* UART1_CONFIG */
-		
+
 #if defined(BSP_UART1_RX_USING_DMA)
 #ifndef UART1_DMA_RX_CONFIG
 #define UART1_DMA_RX_CONFIG                                        \
@@ -74,7 +74,7 @@ extern "C" {
     }
 #endif /* UART2_DMA_RX_CONFIG */
 #endif /* BSP_UART2_RX_USING_DMA */
-		
+
 #if defined(BSP_UART2_TX_USING_DMA)
 #ifndef UART2_DMA_TX_CONFIG
 #define UART2_DMA_TX_CONFIG                                        \
@@ -109,7 +109,7 @@ extern "C" {
     }
 #endif /* UART3_DMA_RX_CONFIG */
 #endif /* BSP_UART3_RX_USING_DMA */
-		
+
 #if defined(BSP_UART3_TX_USING_DMA)
 #ifndef UART3_DMA_TX_CONFIG
 #define UART3_DMA_TX_CONFIG                                        \
@@ -179,7 +179,7 @@ extern "C" {
     }
 #endif /* UART5_DMA_RX_CONFIG */
 #endif /* BSP_UART5_RX_USING_DMA */
-		
+
 #if defined(BSP_UART5_TX_USING_DMA)
 #ifndef UART5_DMA_TX_CONFIG
 #define UART5_DMA_TX_CONFIG                                        \
@@ -214,7 +214,7 @@ extern "C" {
     }
 #endif /* UART6_DMA_RX_CONFIG */
 #endif /* BSP_UART6_RX_USING_DMA */
-		
+
 #if defined(BSP_UART6_TX_USING_DMA)
 #ifndef UART6_DMA_TX_CONFIG
 #define UART6_DMA_TX_CONFIG                                        \
@@ -249,7 +249,7 @@ extern "C" {
     }
 #endif /* UART7_DMA_RX_CONFIG */
 #endif /* BSP_UART7_RX_USING_DMA */
-		
+
 #if defined(BSP_UART7_TX_USING_DMA)
 #ifndef UART7_DMA_TX_CONFIG
 #define UART7_DMA_TX_CONFIG                                        \
@@ -284,7 +284,7 @@ extern "C" {
     }
 #endif /* UART8_DMA_RX_CONFIG */
 #endif /* BSP_UART8_RX_USING_DMA */
-		
+
 #if defined(BSP_UART8_TX_USING_DMA)
 #ifndef UART8_DMA_TX_CONFIG
 #define UART8_DMA_TX_CONFIG                                        \
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f4/usbd_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f4/usbd_config.h
index a6fc9a4c4d..31a648ad12 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f4/usbd_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f4/usbd_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f7/adc_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f7/adc_config.h
index bda1a06485..711dd21bbd 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f7/adc_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f7/adc_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f7/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f7/dma_config.h
index f716e23765..43a9955e54 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f7/dma_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f7/dma_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f7/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f7/pwm_config.h
index 1a5575de0c..b8ef2d37f7 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f7/pwm_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f7/pwm_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f7/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f7/qspi_config.h
index f4477f498b..bee2eb5d82 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f7/qspi_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f7/qspi_config.h
@@ -1,11 +1,11 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2018-12-22     zylx         first version 
+ * 2018-12-22     zylx         first version
  */
 
 #ifndef __QSPI_CONFIG_H__
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f7/sdio_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f7/sdio_config.h
index ae1e4bbf6e..bea45515c3 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f7/sdio_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f7/sdio_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f7/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f7/spi_config.h
index ef32a32f4f..26f230d9b1 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f7/spi_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f7/spi_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -26,7 +26,7 @@ extern "C" {
     }
 #endif /* SPI1_BUS_CONFIG */
 #endif /* BSP_USING_SPI1 */
-    
+
 #ifdef BSP_SPI1_TX_USING_DMA
 #ifndef SPI1_TX_DMA_CONFIG
 #define SPI1_TX_DMA_CONFIG                          \
@@ -60,7 +60,7 @@ extern "C" {
     }
 #endif /* SPI2_BUS_CONFIG */
 #endif /* BSP_USING_SPI2 */
-    
+
 #ifdef BSP_SPI2_TX_USING_DMA
 #ifndef SPI2_TX_DMA_CONFIG
 #define SPI2_TX_DMA_CONFIG                          \
@@ -94,7 +94,7 @@ extern "C" {
     }
 #endif /* SPI3_BUS_CONFIG */
 #endif /* BSP_USING_SPI3 */
-    
+
 #ifdef BSP_SPI3_TX_USING_DMA
 #ifndef SPI3_TX_DMA_CONFIG
 #define SPI3_TX_DMA_CONFIG                          \
@@ -128,7 +128,7 @@ extern "C" {
     }
 #endif /* SPI4_BUS_CONFIG */
 #endif /* BSP_USING_SPI4 */
-    
+
 #ifdef BSP_SPI4_TX_USING_DMA
 #ifndef SPI4_TX_DMA_CONFIG
 #define SPI4_TX_DMA_CONFIG                          \
@@ -162,7 +162,7 @@ extern "C" {
     }
 #endif /* SPI5_BUS_CONFIG */
 #endif /* BSP_USING_SPI5 */
-    
+
 #ifdef BSP_SPI5_TX_USING_DMA
 #ifndef SPI5_TX_DMA_CONFIG
 #define SPI5_TX_DMA_CONFIG                          \
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f7/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f7/tim_config.h
index cd116d9e19..41ef9f9ee0 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f7/tim_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f7/tim_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/f7/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/f7/uart_config.h
index 6c5b7c840d..7c6f38b697 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/f7/uart_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/f7/uart_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -8,7 +8,7 @@
  * 2018-10-30     SummerGift   first version
  * 2019-01-05     zylx         modify dma support
  */
- 
+
 #ifndef __UART_CONFIG_H__
 #define __UART_CONFIG_H__
 
@@ -19,7 +19,7 @@ extern "C" {
 #endif
 
 #if defined(BSP_USING_UART1)
-#ifndef UART1_CONFIG    
+#ifndef UART1_CONFIG
 #define UART1_CONFIG                                                \
     {                                                               \
         .name = "uart1",                                            \
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g0/adc_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g0/adc_config.h
index 739598e7d0..9adaf25fe1 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/g0/adc_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/g0/adc_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g0/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g0/dma_config.h
index 39a79dd536..1340f7c4b0 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/g0/dma_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/g0/dma_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g0/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g0/pwm_config.h
index 834903f656..bc9c375b7a 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/g0/pwm_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/g0/pwm_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g0/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g0/spi_config.h
index a09ec948a9..a33777977a 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/g0/spi_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/g0/spi_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -27,7 +27,7 @@ extern "C" {
     }
 #endif /* SPI1_BUS_CONFIG */
 #endif /* BSP_USING_SPI1 */
-    
+
 #ifdef BSP_SPI1_TX_USING_DMA
 #ifndef SPI1_TX_DMA_CONFIG
 #define SPI1_TX_DMA_CONFIG                          \
@@ -61,7 +61,7 @@ extern "C" {
     }
 #endif /* SPI2_BUS_CONFIG */
 #endif /* BSP_USING_SPI2 */
-    
+
 #ifdef BSP_SPI2_TX_USING_DMA
 #ifndef SPI2_TX_DMA_CONFIG
 #define SPI2_TX_DMA_CONFIG                          \
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g0/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g0/tim_config.h
index 01d3af18f1..ac6e402ac4 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/g0/tim_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/g0/tim_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g0/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g0/uart_config.h
index f38baf0b63..3cbb77eefd 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/g0/uart_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/g0/uart_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g4/adc_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g4/adc_config.h
index bda1a06485..711dd21bbd 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/g4/adc_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/g4/adc_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g4/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g4/dma_config.h
index 46411c5441..419dff4ae7 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/g4/dma_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/g4/dma_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g4/pulse_encoder_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g4/pulse_encoder_config.h
index 53320efda1..f9534e0a4c 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/g4/pulse_encoder_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/g4/pulse_encoder_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g4/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g4/pwm_config.h
index 14d4aa2aff..ca382e4742 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/g4/pwm_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/g4/pwm_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g4/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g4/qspi_config.h
index 8450dc257f..5089a10bdf 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/g4/qspi_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/g4/qspi_config.h
@@ -1,11 +1,11 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2018-12-22     zylx         first version 
+ * 2018-12-22     zylx         first version
  */
 
 #ifndef __QSPI_CONFIG_H__
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g4/sdio_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g4/sdio_config.h
index 7d6837d74f..a61749ceaa 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/g4/sdio_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/g4/sdio_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g4/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g4/spi_config.h
index 34b0590eb3..d03b31ce8a 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/g4/spi_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/g4/spi_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -27,7 +27,7 @@ extern "C" {
     }
 #endif /* SPI1_BUS_CONFIG */
 #endif /* BSP_USING_SPI1 */
-    
+
 #ifdef BSP_SPI1_TX_USING_DMA
 #ifndef SPI1_TX_DMA_CONFIG
 #define SPI1_TX_DMA_CONFIG                          \
@@ -61,7 +61,7 @@ extern "C" {
     }
 #endif /* SPI2_BUS_CONFIG */
 #endif /* BSP_USING_SPI2 */
-    
+
 #ifdef BSP_SPI2_TX_USING_DMA
 #ifndef SPI2_TX_DMA_CONFIG
 #define SPI2_TX_DMA_CONFIG                          \
@@ -95,7 +95,7 @@ extern "C" {
     }
 #endif /* SPI3_BUS_CONFIG */
 #endif /* BSP_USING_SPI3 */
-    
+
 #ifdef BSP_SPI3_TX_USING_DMA
 #ifndef SPI3_TX_DMA_CONFIG
 #define SPI3_TX_DMA_CONFIG                          \
@@ -129,7 +129,7 @@ extern "C" {
     }
 #endif /* SPI4_BUS_CONFIG */
 #endif /* BSP_USING_SPI4 */
-    
+
 #ifdef BSP_SPI4_TX_USING_DMA
 #ifndef SPI4_TX_DMA_CONFIG
 #define SPI4_TX_DMA_CONFIG                          \
@@ -163,7 +163,7 @@ extern "C" {
     }
 #endif /* SPI5_BUS_CONFIG */
 #endif /* BSP_USING_SPI5 */
-    
+
 #ifdef BSP_SPI5_TX_USING_DMA
 #ifndef SPI5_TX_DMA_CONFIG
 #define SPI5_TX_DMA_CONFIG                          \
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g4/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g4/tim_config.h
index cd116d9e19..41ef9f9ee0 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/g4/tim_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/g4/tim_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g4/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g4/uart_config.h
index 5a77643a55..54a2cc380f 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/g4/uart_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/g4/uart_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -9,7 +9,7 @@
  * 2019-01-03     zylx         modify dma support
  * 2019-10-03     xuzhuoyi     modify for STM32G4
  */
- 
+
 #ifndef __UART_CONFIG_H__
 #define __UART_CONFIG_H__
 
@@ -50,7 +50,7 @@ extern "C" {
         .irq_type = USART1_IRQn,                                    \
     }
 #endif /* UART1_CONFIG */
-		
+
 #if defined(BSP_UART1_RX_USING_DMA)
 #ifndef UART1_DMA_RX_CONFIG
 #define UART1_DMA_RX_CONFIG                                        \
@@ -97,7 +97,7 @@ extern "C" {
     }
 #endif /* UART2_DMA_RX_CONFIG */
 #endif /* BSP_UART2_RX_USING_DMA */
-		
+
 #if defined(BSP_UART2_TX_USING_DMA)
 #ifndef UART2_DMA_TX_CONFIG
 #define UART2_DMA_TX_CONFIG                                        \
@@ -132,7 +132,7 @@ extern "C" {
     }
 #endif /* UART3_DMA_RX_CONFIG */
 #endif /* BSP_UART3_RX_USING_DMA */
-		
+
 #if defined(BSP_UART3_TX_USING_DMA)
 #ifndef UART3_DMA_TX_CONFIG
 #define UART3_DMA_TX_CONFIG                                        \
@@ -202,7 +202,7 @@ extern "C" {
     }
 #endif /* UART5_DMA_RX_CONFIG */
 #endif /* BSP_UART5_RX_USING_DMA */
-		
+
 #if defined(BSP_UART5_TX_USING_DMA)
 #ifndef UART5_DMA_TX_CONFIG
 #define UART5_DMA_TX_CONFIG                                        \
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/g4/usbd_config.h b/bsp/stm32/libraries/HAL_Drivers/config/g4/usbd_config.h
index a6fc9a4c4d..31a648ad12 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/g4/usbd_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/g4/usbd_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/h7/adc_config.h b/bsp/stm32/libraries/HAL_Drivers/config/h7/adc_config.h
index 0a51a07719..28e31f133a 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/h7/adc_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/h7/adc_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/h7/dac_config.h b/bsp/stm32/libraries/HAL_Drivers/config/h7/dac_config.h
index 6ca3932831..ad3eef477c 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/h7/dac_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/h7/dac_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/h7/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/h7/dma_config.h
index 23b3a231c3..5349e3d81e 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/h7/dma_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/h7/dma_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/h7/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/config/h7/pwm_config.h
index 1a5575de0c..b8ef2d37f7 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/h7/pwm_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/h7/pwm_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/h7/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/h7/qspi_config.h
index f4477f498b..bee2eb5d82 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/h7/qspi_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/h7/qspi_config.h
@@ -1,11 +1,11 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2018-12-22     zylx         first version 
+ * 2018-12-22     zylx         first version
  */
 
 #ifndef __QSPI_CONFIG_H__
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/h7/sdio_config.h b/bsp/stm32/libraries/HAL_Drivers/config/h7/sdio_config.h
index 220a615c47..eee9d103ba 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/h7/sdio_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/h7/sdio_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/h7/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/h7/spi_config.h
index ef32a32f4f..26f230d9b1 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/h7/spi_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/h7/spi_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -26,7 +26,7 @@ extern "C" {
     }
 #endif /* SPI1_BUS_CONFIG */
 #endif /* BSP_USING_SPI1 */
-    
+
 #ifdef BSP_SPI1_TX_USING_DMA
 #ifndef SPI1_TX_DMA_CONFIG
 #define SPI1_TX_DMA_CONFIG                          \
@@ -60,7 +60,7 @@ extern "C" {
     }
 #endif /* SPI2_BUS_CONFIG */
 #endif /* BSP_USING_SPI2 */
-    
+
 #ifdef BSP_SPI2_TX_USING_DMA
 #ifndef SPI2_TX_DMA_CONFIG
 #define SPI2_TX_DMA_CONFIG                          \
@@ -94,7 +94,7 @@ extern "C" {
     }
 #endif /* SPI3_BUS_CONFIG */
 #endif /* BSP_USING_SPI3 */
-    
+
 #ifdef BSP_SPI3_TX_USING_DMA
 #ifndef SPI3_TX_DMA_CONFIG
 #define SPI3_TX_DMA_CONFIG                          \
@@ -128,7 +128,7 @@ extern "C" {
     }
 #endif /* SPI4_BUS_CONFIG */
 #endif /* BSP_USING_SPI4 */
-    
+
 #ifdef BSP_SPI4_TX_USING_DMA
 #ifndef SPI4_TX_DMA_CONFIG
 #define SPI4_TX_DMA_CONFIG                          \
@@ -162,7 +162,7 @@ extern "C" {
     }
 #endif /* SPI5_BUS_CONFIG */
 #endif /* BSP_USING_SPI5 */
-    
+
 #ifdef BSP_SPI5_TX_USING_DMA
 #ifndef SPI5_TX_DMA_CONFIG
 #define SPI5_TX_DMA_CONFIG                          \
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/h7/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/config/h7/tim_config.h
index cd116d9e19..41ef9f9ee0 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/h7/tim_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/h7/tim_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/h7/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/h7/uart_config.h
index 6ae67d4a2f..a6e2897d92 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/h7/uart_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/h7/uart_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -9,7 +9,7 @@
  * 2019-01-05     zylx         modify dma support
  * 2020-05-02     whj4674672   support stm32h7 uart dma
  */
- 
+
 #ifndef __UART_CONFIG_H__
 #define __UART_CONFIG_H__
 
@@ -20,7 +20,7 @@ extern "C" {
 #endif
 
 #if defined(BSP_USING_UART1)
-#ifndef UART1_CONFIG    
+#ifndef UART1_CONFIG
 #define UART1_CONFIG                                                \
     {                                                               \
         .name = "uart1",                                            \
@@ -75,7 +75,7 @@ extern "C" {
     }
 #endif /* UART2_DMA_TX_CONFIG */
 #endif /* BSP_UART2_TX_USING_DMA */
-    
+
 #if defined(BSP_USING_UART3)
 #ifndef UART3_CONFIG
 #define UART3_CONFIG                                                \
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/h7/usbd_config.h b/bsp/stm32/libraries/HAL_Drivers/config/h7/usbd_config.h
index a6fc9a4c4d..31a648ad12 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/h7/usbd_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/h7/usbd_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l0/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l0/dma_config.h
index 803e4706ef..9477886ba5 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/l0/dma_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/l0/dma_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l0/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l0/uart_config.h
index ea5e767aed..649ec1f4ec 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/l0/uart_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/l0/uart_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -49,7 +49,7 @@ extern "C" {
     }
 #endif /* UART2_CONFIG */
 #endif /* BSP_USING_UART2 */
-    
+
 #if defined(BSP_UART2_RX_USING_DMA)
 #ifndef UART2_DMA_RX_CONFIG
 #define UART2_DMA_RX_CONFIG                                            \
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l1/adc_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l1/adc_config.h
index ac0a7ca373..825aaf102e 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/l1/adc_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/l1/adc_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -29,7 +29,7 @@ extern "C" {
        .Init.DiscontinuousConvMode = DISABLE,                      \
        .Init.NbrOfDiscConversion   = 1,                            \
        .Init.ExternalTrigConv      = ADC_SOFTWARE_START,           \
-    }  
+    }
 #endif /* ADC1_CONFIG */
 #endif /* BSP_USING_ADC1 */
 
@@ -45,7 +45,7 @@ extern "C" {
        .Init.DiscontinuousConvMode = DISABLE,                      \
        .Init.NbrOfDiscConversion   = 1,                            \
        .Init.ExternalTrigConv      = ADC_SOFTWARE_START,           \
-    }  
+    }
 #endif /* ADC2_CONFIG */
 #endif /* BSP_USING_ADC2 */
 
@@ -61,7 +61,7 @@ extern "C" {
        .Init.DiscontinuousConvMode = DISABLE,                      \
        .Init.NbrOfDiscConversion   = 1,                            \
        .Init.ExternalTrigConv      = ADC_SOFTWARE_START,           \
-    }  
+    }
 #endif /* ADC3_CONFIG */
 #endif /* BSP_USING_ADC3 */
 
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l1/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l1/dma_config.h
index 20205c43d7..65e136a2c3 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/l1/dma_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/l1/dma_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l1/pulse_encoder_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l1/pulse_encoder_config.h
index 94dd8fcd70..1de5c72b26 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/l1/pulse_encoder_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/l1/pulse_encoder_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l1/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l1/pwm_config.h
index 1a5575de0c..b8ef2d37f7 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/l1/pwm_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/l1/pwm_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l1/sdio_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l1/sdio_config.h
index 9e7762323e..266ac8bb96 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/l1/sdio_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/l1/sdio_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l1/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l1/spi_config.h
index c4bbe3708d..bf28c2fc72 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/l1/spi_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/l1/spi_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -27,7 +27,7 @@ extern "C" {
     }
 #endif /* SPI1_BUS_CONFIG */
 #endif /* BSP_USING_SPI1 */
-    
+
 #ifdef BSP_SPI1_TX_USING_DMA
 #ifndef SPI1_TX_DMA_CONFIG
 #define SPI1_TX_DMA_CONFIG                          \
@@ -59,7 +59,7 @@ extern "C" {
     }
 #endif /* SPI2_BUS_CONFIG */
 #endif /* BSP_USING_SPI2 */
-    
+
 #ifdef BSP_SPI2_TX_USING_DMA
 #ifndef SPI2_TX_DMA_CONFIG
 #define SPI2_TX_DMA_CONFIG                          \
@@ -91,7 +91,7 @@ extern "C" {
     }
 #endif /* SPI3_BUS_CONFIG */
 #endif /* BSP_USING_SPI3 */
-    
+
 #ifdef BSP_SPI3_TX_USING_DMA
 #ifndef SPI3_TX_DMA_CONFIG
 #define SPI3_TX_DMA_CONFIG                          \
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l1/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l1/tim_config.h
index 1d3b245dc8..07478f1465 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/l1/tim_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/l1/tim_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l1/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l1/uart_config.h
index a08196e996..8605d9089c 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/l1/uart_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/l1/uart_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l1/usbd_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l1/usbd_config.h
index d66f51115a..3f319f4024 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/l1/usbd_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/l1/usbd_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/adc_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/adc_config.h
index 47fe0139b1..cb3ac94524 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/l4/adc_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/adc_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/dac_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/dac_config.h
index 6ca3932831..ad3eef477c 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/l4/dac_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/dac_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/dma_config.h
index c86148bf7d..0762f9048d 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/l4/dma_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/dma_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/pwm_config.h
index 50ea3791b6..c4d4bcf202 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/l4/pwm_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/pwm_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/qspi_config.h
index 4714c119f0..fa8228c6d4 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/l4/qspi_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/qspi_config.h
@@ -1,11 +1,11 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2018-12-22     zylx         first version 
+ * 2018-12-22     zylx         first version
  */
 
 #ifndef __QSPI_CONFIG_H__
@@ -28,7 +28,7 @@ extern "C" {
     }
 #endif /* QSPI_BUS_CONFIG */
 #endif /* BSP_USING_QSPI */
-    
+
 #ifdef BSP_QSPI_USING_DMA
 #ifndef QSPI_DMA_CONFIG
 #define QSPI_DMA_CONFIG                                        \
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/sdio_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/sdio_config.h
index 71811dba84..fa066e5cfc 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/l4/sdio_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/sdio_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/spi_config.h
index d7518805b3..d510ca379d 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/l4/spi_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/spi_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/tim_config.h
index 4df13ca087..b90879c155 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/l4/tim_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/tim_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/uart_config.h
index aa71112655..297ab30d56 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/l4/uart_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/uart_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -60,7 +60,7 @@ extern "C" {
         .dma_irq  = UART1_RX_DMA_IRQ,                               \
     }
 #endif /* UART1_DMA_RX_CONFIG */
-#endif /* BSP_UART1_RX_USING_DMA */  
+#endif /* BSP_UART1_RX_USING_DMA */
 
 #if defined(BSP_UART1_TX_USING_DMA)
 #ifndef UART1_DMA_TX_CONFIG
@@ -146,6 +146,6 @@ extern "C" {
 
 #ifdef __cplusplus
 }
-#endif 
+#endif
 
 #endif
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/l4/usbd_config.h b/bsp/stm32/libraries/HAL_Drivers/config/l4/usbd_config.h
index a6fc9a4c4d..31a648ad12 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/l4/usbd_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/l4/usbd_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/mp1/adc_config.h b/bsp/stm32/libraries/HAL_Drivers/config/mp1/adc_config.h
index 4ce80cea05..fb9df3f237 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/mp1/adc_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/mp1/adc_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/mp1/dac_config.h b/bsp/stm32/libraries/HAL_Drivers/config/mp1/dac_config.h
index f49d534aa3..1fd23ae57d 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/mp1/dac_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/mp1/dac_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/mp1/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/mp1/dma_config.h
index 51101388e8..1b06d2aa5a 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/mp1/dma_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/mp1/dma_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -47,7 +47,7 @@ extern "C" {
 #define SPI5_RX_DMA_CHANNEL              DMA_REQUEST_SPI5_RX
 #define SPI5_RX_DMA_IRQ                  DMA2_Stream0_IRQn
 #endif
-    
+
 /* DMA2 stream1 */
 #if defined(BSP_UART3_TX_USING_DMA) && !defined(BSP_UART3_TX_USING_INSTANCE)
 #define UART3_DMA_TX_IRQHandler           DMA2_Stream1_IRQHandler
@@ -78,7 +78,7 @@ extern "C" {
 #define UART4_RX_DMA_RCC                 RCC_MC_AHB2ENSETR_DMA2EN
 #define UART4_RX_DMA_INSTANCE            DMA2_Stream3
 #define UART4_RX_DMA_CHANNEL             DMA_REQUEST_UART4_RX
-#define UART4_RX_DMA_IRQ                 DMA2_Stream3_IRQn        
+#define UART4_RX_DMA_IRQ                 DMA2_Stream3_IRQn
 #endif
 
 /* DMA2 stream4 */
@@ -87,7 +87,7 @@ extern "C" {
 #define UART4_TX_DMA_RCC                 RCC_MC_AHB2ENSETR_DMA2EN
 #define UART4_TX_DMA_INSTANCE            DMA2_Stream4
 #define UART4_TX_DMA_CHANNEL             DMA_REQUEST_UART4_TX
-#define UART4_TX_DMA_IRQ                 DMA2_Stream4_IRQn   
+#define UART4_TX_DMA_IRQ                 DMA2_Stream4_IRQn
 #endif
 
 /* DMA2 stream5 */
@@ -105,7 +105,7 @@ extern "C" {
 #define CRYP2_IN_DMA_RCC                 RCC_MC_AHB2ENSETR_DMA2EN
 #define CRYP2_IN_DMA_INSTANCE            DMA2_Stream6
 #define CRYP2_IN_DMA_CHANNEL             DMA_REQUEST_CRYP2_IN
-#define CRYP2_IN_DMA_IRQ                 DMA2_Stream6_IRQn    
+#define CRYP2_IN_DMA_IRQ                 DMA2_Stream6_IRQn
 #endif
 
 /* DMA2 stream7 */
@@ -114,9 +114,9 @@ extern "C" {
 #define HASH2_IN_DMA_RCC                 RCC_MC_AHB2ENSETR_DMA2EN
 #define HASH2_IN_DMA_INSTANCE            DMA2_Stream7
 #define HASH2_IN_DMA_CHANNEL             DMA_REQUEST_HASH2_IN
-#define HASH2_IN_DMA_IRQ                 DMA2_Stream7_IRQn  
+#define HASH2_IN_DMA_IRQ                 DMA2_Stream7_IRQn
 #endif
-    
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/mp1/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/config/mp1/pwm_config.h
index 1a5575de0c..b8ef2d37f7 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/mp1/pwm_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/mp1/pwm_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/mp1/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/mp1/qspi_config.h
index 0dc48247e7..bee2eb5d82 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/mp1/qspi_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/mp1/qspi_config.h
@@ -1,11 +1,11 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2018-12-22     zylx         first version 
+ * 2018-12-22     zylx         first version
  */
 
 #ifndef __QSPI_CONFIG_H__
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/mp1/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/mp1/spi_config.h
index 26edfa927c..3236751624 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/mp1/spi_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/mp1/spi_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -26,7 +26,7 @@ extern "C" {
     }
 #endif /* SPI1_BUS_CONFIG */
 #endif /* BSP_USING_SPI1 */
-    
+
 #ifdef BSP_SPI1_TX_USING_DMA
 #ifndef SPI1_TX_DMA_CONFIG
 #define SPI1_TX_DMA_CONFIG                          \
@@ -60,7 +60,7 @@ extern "C" {
     }
 #endif /* SPI2_BUS_CONFIG */
 #endif /* BSP_USING_SPI2 */
-    
+
 #ifdef BSP_SPI2_TX_USING_DMA
 #ifndef SPI2_TX_DMA_CONFIG
 #define SPI2_TX_DMA_CONFIG                          \
@@ -94,7 +94,7 @@ extern "C" {
     }
 #endif /* SPI3_BUS_CONFIG */
 #endif /* BSP_USING_SPI3 */
-    
+
 #ifdef BSP_SPI3_TX_USING_DMA
 #ifndef SPI3_TX_DMA_CONFIG
 #define SPI3_TX_DMA_CONFIG                          \
@@ -128,7 +128,7 @@ extern "C" {
     }
 #endif /* SPI4_BUS_CONFIG */
 #endif /* BSP_USING_SPI4 */
-    
+
 #ifdef BSP_SPI4_TX_USING_DMA
 #ifndef SPI4_TX_DMA_CONFIG
 #define SPI4_TX_DMA_CONFIG                          \
@@ -162,7 +162,7 @@ extern "C" {
     }
 #endif /* SPI5_BUS_CONFIG */
 #endif /* BSP_USING_SPI5 */
-    
+
 #ifdef BSP_SPI5_TX_USING_DMA
 #ifndef SPI5_TX_DMA_CONFIG
 #define SPI5_TX_DMA_CONFIG                          \
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/mp1/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/config/mp1/tim_config.h
index 9f47ccafe2..1c74b3eade 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/mp1/tim_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/mp1/tim_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/mp1/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/mp1/uart_config.h
index b13b25d362..4d4715fad6 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/mp1/uart_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/mp1/uart_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -8,7 +8,7 @@
  * 2018-10-30     SummerGift   first version
  * 2019-01-03     zylx         modify dma support
  */
- 
+
 #ifndef __UART_CONFIG_H__
 #define __UART_CONFIG_H__
 
@@ -27,7 +27,7 @@ extern "C" {
         .irq_type = USART1_IRQn,                                    \
     }
 #endif /* UART1_CONFIG */
-		
+
 #if defined(BSP_UART1_RX_USING_DMA)
 #ifndef UART1_DMA_RX_CONFIG
 #define UART1_DMA_RX_CONFIG                                        \
@@ -74,7 +74,7 @@ extern "C" {
     }
 #endif /* UART2_DMA_RX_CONFIG */
 #endif /* BSP_UART2_RX_USING_DMA */
-		
+
 #if defined(BSP_UART2_TX_USING_DMA)
 #ifndef UART2_DMA_TX_CONFIG
 #define UART2_DMA_TX_CONFIG                                        \
@@ -109,7 +109,7 @@ extern "C" {
     }
 #endif /* UART3_DMA_RX_CONFIG */
 #endif /* BSP_UART3_RX_USING_DMA */
-		
+
 #if defined(BSP_UART3_TX_USING_DMA)
 #ifndef UART3_DMA_TX_CONFIG
 #define UART3_DMA_TX_CONFIG                                        \
@@ -179,7 +179,7 @@ extern "C" {
     }
 #endif /* UART5_DMA_RX_CONFIG */
 #endif /* BSP_UART5_RX_USING_DMA */
-		
+
 #if defined(BSP_UART5_TX_USING_DMA)
 #ifndef UART5_DMA_TX_CONFIG
 #define UART5_DMA_TX_CONFIG                                        \
@@ -214,7 +214,7 @@ extern "C" {
     }
 #endif /* UART6_DMA_RX_CONFIG */
 #endif /* BSP_UART6_RX_USING_DMA */
-		
+
 #if defined(BSP_UART6_TX_USING_DMA)
 #ifndef UART6_DMA_TX_CONFIG
 #define UART6_DMA_TX_CONFIG                                        \
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/wb/adc_config.h b/bsp/stm32/libraries/HAL_Drivers/config/wb/adc_config.h
index 66032f4853..ea23a2d1d2 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/wb/adc_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/wb/adc_config.h
@@ -1,10 +1,10 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author       		Notes
+ * Date           Author            Notes
  * 2020-10-14     Dozingfiretruck   first version
  */
 
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/wb/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/wb/dma_config.h
index 83c7e815c3..b7f0cc3da2 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/wb/dma_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/wb/dma_config.h
@@ -1,11 +1,11 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * Date           Author       		Notes
+ * Date           Author            Notes
  * 2020-10-14     Dozingfiretruck   first version
  */
 
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/wb/pwm_config.h b/bsp/stm32/libraries/HAL_Drivers/config/wb/pwm_config.h
index fb2187b88a..1d129e6792 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/wb/pwm_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/wb/pwm_config.h
@@ -1,10 +1,10 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author       		Notes
+ * Date           Author            Notes
  * 2020-10-14     Dozingfiretruck   first version
  */
 
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/wb/qspi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/wb/qspi_config.h
index 5190bcc705..fd6ab3d242 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/wb/qspi_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/wb/qspi_config.h
@@ -1,10 +1,10 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author       		Notes
+ * Date           Author            Notes
  * 2020-10-14     Dozingfiretruck   first version
  */
 
@@ -28,7 +28,7 @@ extern "C" {
     }
 #endif /* QSPI_BUS_CONFIG */
 #endif /* BSP_USING_QSPI */
-    
+
 #ifdef BSP_QSPI_USING_DMA
 #ifndef QSPI_DMA_CONFIG
 #define QSPI_DMA_CONFIG                                        \
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/wb/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/wb/spi_config.h
index 6f545795da..0f37cfe2af 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/wb/spi_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/wb/spi_config.h
@@ -1,10 +1,10 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author       		Notes
+ * Date           Author            Notes
  * 2020-10-14     Dozingfiretruck   first version
  */
 
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/wb/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/config/wb/tim_config.h
index 362d4060e4..24fa9e755c 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/wb/tim_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/wb/tim_config.h
@@ -1,10 +1,10 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author       		Notes
+ * Date           Author            Notes
  * 2020-10-14     Dozingfiretruck   first version
  */
 
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/wb/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/wb/uart_config.h
index 83371f7fe9..6f4eea2e52 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/wb/uart_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/wb/uart_config.h
@@ -1,10 +1,10 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author       		Notes
+ * Date           Author            Notes
  * 2020-10-14     Dozingfiretruck   first version
  */
 
@@ -60,7 +60,7 @@ extern "C" {
         .dma_irq  = UART1_RX_DMA_IRQ,                               \
     }
 #endif /* UART1_DMA_RX_CONFIG */
-#endif /* BSP_UART1_RX_USING_DMA */  
+#endif /* BSP_UART1_RX_USING_DMA */
 
 #if defined(BSP_UART1_TX_USING_DMA)
 #ifndef UART1_DMA_TX_CONFIG
@@ -146,6 +146,6 @@ extern "C" {
 
 #ifdef __cplusplus
 }
-#endif 
+#endif
 
 #endif
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/wb/usbd_config.h b/bsp/stm32/libraries/HAL_Drivers/config/wb/usbd_config.h
index 164a1db68c..6e71510faf 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/wb/usbd_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/wb/usbd_config.h
@@ -1,10 +1,10 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author       		Notes
+ * Date           Author            Notes
  * 2020-10-14     Dozingfiretruck   first version
  */
 #ifndef __USBD_CONFIG_H__
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/wl/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/config/wl/dma_config.h
index 4804bf94ea..3135f80749 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/wl/dma_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/wl/dma_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/wl/spi_config.h b/bsp/stm32/libraries/HAL_Drivers/config/wl/spi_config.h
index d7518805b3..d510ca379d 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/wl/spi_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/wl/spi_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/wl/tim_config.h b/bsp/stm32/libraries/HAL_Drivers/config/wl/tim_config.h
index f802634560..36795f0711 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/wl/tim_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/wl/tim_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -33,8 +33,8 @@ extern "C" {
         .minfreq = 2000,                        \
         .maxcnt  = 0xFFFF,                      \
         .cntmode = HWTIMER_CNTMODE_UP,          \
-    }    
-#endif    
+    }
+#endif
 #endif /* TIM_DEV_INFO_CONFIG */
 
 #ifdef BSP_USING_TIM2
@@ -47,7 +47,7 @@ extern "C" {
     }
 #endif /* TIM2_CONFIG */
 #endif /* BSP_USING_TIM2 */
-    
+
 #ifdef BSP_USING_TIM15
 #ifndef TIM15_CONFIG
 #define TIM15_CONFIG                                        \
diff --git a/bsp/stm32/libraries/HAL_Drivers/config/wl/uart_config.h b/bsp/stm32/libraries/HAL_Drivers/config/wl/uart_config.h
index 6d87d38033..3a9b59f987 100644
--- a/bsp/stm32/libraries/HAL_Drivers/config/wl/uart_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/config/wl/uart_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -50,7 +50,7 @@ extern "C" {
 #endif /* UART1_DMA_TX_CONFIG */
 #endif /* BSP_UART1_TX_USING_DMA */
 #endif /* BSP_USING_UART1 */
-    
+
 #if defined(BSP_USING_UART1)
 #ifndef UART1_CONFIG
 #define UART1_CONFIG                                                \
@@ -72,8 +72,8 @@ extern "C" {
         .dma_irq  = UART1_RX_DMA_IRQ,                               \
     }
 #endif /* UART1_DMA_RX_CONFIG */
-#endif /* BSP_UART1_RX_USING_DMA */  
-   
+#endif /* BSP_UART1_RX_USING_DMA */
+
 #if defined(BSP_USING_UART2)
 #ifndef UART2_CONFIG
 #define UART2_CONFIG                                                \
@@ -120,9 +120,9 @@ extern "C" {
 #endif /* UART3_DMA_RX_CONFIG */
 #endif /* BSP_UART3_RX_USING_DMA */
 
-    
+
 #ifdef __cplusplus
 }
-#endif 
+#endif
 
 #endif
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_adc.c b/bsp/stm32/libraries/HAL_Drivers/drv_adc.c
index 4d44c968fc..e76edc8816 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_adc.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_adc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -192,13 +192,13 @@ static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t ch
 #endif
         return -RT_ERROR;
     }
-    
+
 #if defined(SOC_SERIES_STM32MP1) || defined (SOC_SERIES_STM32H7) || defined (SOC_SERIES_STM32WB)
     ADC_ChanConf.Rank = ADC_REGULAR_RANK_1;
 #else
     ADC_ChanConf.Rank = 1;
 #endif
-    
+
 #if defined(SOC_SERIES_STM32F0)
     ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_71CYCLES_5;
 #elif defined(SOC_SERIES_STM32F1)
@@ -224,7 +224,7 @@ static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t ch
     ADC_ChanConf.SingleDiff = LL_ADC_SINGLE_ENDED;
 #elif defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined (SOC_SERIES_STM32WB)
     ADC_ChanConf.OffsetNumber = ADC_OFFSET_NONE;  /* ADC channel affected to offset number */
-    ADC_ChanConf.Offset       = 0; 
+    ADC_ChanConf.Offset       = 0;
     ADC_ChanConf.SingleDiff   = ADC_SINGLE_ENDED; /* ADC channel differential mode */
 #endif
     HAL_ADC_ConfigChannel(stm32_adc_handler, &ADC_ChanConf);
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_can.c b/bsp/stm32/libraries/HAL_Drivers/drv_can.c
index c7d0428d48..4fe801187a 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_can.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_can.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -11,6 +11,7 @@
  *                             fix bug.port to BSP [stm32]
  * 2019-03-27     YLZ          support double can channels, support stm32F4xx (only Legacy mode).
  * 2019-06-17     YLZ          port to new STM32F1xx HAL V1.1.3.
+ * 2021-02-02     YuZhe XU     fix bug in filter config
  */
 
 #include "drv_can.h"
@@ -292,6 +293,13 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
         }
         break;
     case RT_CAN_CMD_SET_FILTER:
+    {
+        rt_uint32_t id_h = 0;
+        rt_uint32_t id_l = 0;
+        rt_uint32_t mask_h = 0;
+        rt_uint32_t mask_l = 0;
+        rt_uint32_t mask_l_tail = 0;  //CAN_FxR2 bit [2:0]
+
         if (RT_NULL == arg)
         {
             /* default filter config */
@@ -303,19 +311,69 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
             /* get default filter */
             for (int i = 0; i < filter_cfg->count; i++)
             {
-                drv_can->FilterConfig.FilterBank = filter_cfg->items[i].hdr;
-                drv_can->FilterConfig.FilterIdHigh = (filter_cfg->items[i].id >> 13) & 0xFFFF;
-                drv_can->FilterConfig.FilterIdLow = ((filter_cfg->items[i].id << 3) | 
-                                                    (filter_cfg->items[i].ide << 2) | 
-                                                    (filter_cfg->items[i].rtr << 1)) & 0xFFFF;
-                drv_can->FilterConfig.FilterMaskIdHigh = (filter_cfg->items[i].mask >> 16) & 0xFFFF;
-                drv_can->FilterConfig.FilterMaskIdLow = filter_cfg->items[i].mask & 0xFFFF;
+                if (filter_cfg->items[i].hdr == -1)
+                {
+                    drv_can->FilterConfig.FilterBank = i;
+                }
+                else
+                {
+                    drv_can->FilterConfig.FilterBank = filter_cfg->items[i].hdr;
+                }
+                 /**
+                 * ID     | CAN_FxR1[31:24] | CAN_FxR1[23:16] | CAN_FxR1[15:8] | CAN_FxR1[7:0]       |
+                 * MASK   | CAN_FxR2[31:24] | CAN_FxR1[23:16] | CAN_FxR1[15:8] | CAN_FxR1[7:0]       |
+                 * STD ID |     STID[10:3]  | STDID[2:0] |<-                21bit                  ->|
+                 * EXT ID |    EXTID[28:21] | EXTID[20:13]    | EXTID[12:5]    | EXTID[4:0] IDE RTR 0|
+                 * @note the 32bit STD ID must << 21 to fill CAN_FxR1[31:21] and EXT ID must << 3,
+                 *       -> but the id bit of struct rt_can_filter_item is 29, 
+                 *       -> so STD id << 18 and EXT id Don't need << 3, when get the high 16bit.
+                 *       -> FilterIdHigh : (((STDid << 18) or (EXT id)) >> 13) & 0xFFFF,
+                 *       -> FilterIdLow:   ((STDid << 18) or (EXT id << 3)) & 0xFFFF. 
+                 * @note the mask bit of struct rt_can_filter_item is 32, 
+                 *       -> FilterMaskIdHigh: (((STD mask << 21) or (EXT mask <<3)) >> 16) & 0xFFFF  
+                 *       -> FilterMaskIdLow: ((STD mask << 21) or (EXT mask <<3)) & 0xFFFF  
+                 */
+                if (filter_cfg->items[i].mode == CAN_FILTERMODE_IDMASK)
+                {
+                    /* make sure the CAN_FxR1[2:0](IDE RTR) work */
+                    mask_l_tail = 0x06;
+                }
+                else if (filter_cfg->items[i].mode == CAN_FILTERMODE_IDLIST)
+                {
+                    /* same as CAN_FxR1 */
+                    mask_l_tail = (filter_cfg->items[i].ide << 2) | 
+                                   (filter_cfg->items[i].rtr << 1);
+                }
+                if (filter_cfg->items[i].ide == RT_CAN_STDID)
+                {
+                    id_h = ((filter_cfg->items[i].id << 18) >> 13) & 0xFFFF;
+                    id_l = ((filter_cfg->items[i].id << 18) | 
+                            (filter_cfg->items[i].ide << 2) | 
+                            (filter_cfg->items[i].rtr << 1)) & 0xFFFF;
+                    mask_h = ((filter_cfg->items[i].mask << 21) >> 16) & 0xFFFF;
+                    mask_l = ((filter_cfg->items[i].mask << 21) | mask_l_tail) & 0xFFFF;
+                }
+                else if (filter_cfg->items[i].ide == RT_CAN_EXTID)
+                {
+                    id_h = (filter_cfg->items[i].id >> 13) & 0xFFFF;
+                    id_l = ((filter_cfg->items[i].id << 3)   | 
+                            (filter_cfg->items[i].ide << 2)  | 
+                            (filter_cfg->items[i].rtr << 1)) & 0xFFFF;
+                    mask_h = ((filter_cfg->items[i].mask << 3) >> 16) & 0xFFFF;
+                    mask_l = ((filter_cfg->items[i].mask << 3) | mask_l_tail) & 0xFFFF;
+                }
+                drv_can->FilterConfig.FilterIdHigh = id_h;
+                drv_can->FilterConfig.FilterIdLow = id_l;
+                drv_can->FilterConfig.FilterMaskIdHigh = mask_h;
+                drv_can->FilterConfig.FilterMaskIdLow = mask_l;
+
                 drv_can->FilterConfig.FilterMode = filter_cfg->items[i].mode;
                 /* Filter conf */
                 HAL_CAN_ConfigFilter(&drv_can->CanHandle, &drv_can->FilterConfig);
             }
         }
         break;
+    }
     case RT_CAN_CMD_SET_MODE:
         argval = (rt_uint32_t) arg;
         if (argval != RT_CAN_MODE_NORMAL &&
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_can.h b/bsp/stm32/libraries/HAL_Drivers/drv_can.h
index b0ae3072e6..900793a153 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_can.h
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_can.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_common.c b/bsp/stm32/libraries/HAL_Drivers/drv_common.c
index af19a5f732..74007b6e88 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_common.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_common.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -168,7 +168,7 @@ RT_WEAK void rt_hw_board_init()
 #endif
 
     /* Set the shell console output device */
-#ifdef RT_USING_CONSOLE
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
 
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_common.h b/bsp/stm32/libraries/HAL_Drivers/drv_common.h
index bffedddcd0..83ef259308 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_common.h
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_common.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -13,7 +13,9 @@
 
 #include 
 #include 
+#ifdef RT_USING_DEVICE
 #include 
+#endif
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_config.h b/bsp/stm32/libraries/HAL_Drivers/drv_config.h
index 3f45b0004c..7f615fcf60 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_config.h
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -8,7 +8,7 @@
  * 2018-10-30     SummerGift        first version
  * 2020-10-14     Dozingfiretruck   Porting for stm32wbxx
  */
- 
+
 #ifndef __DRV_CONFIG_H__
 #define __DRV_CONFIG_H__
 
@@ -43,7 +43,7 @@ extern "C" {
 #include "f2/adc_config.h"
 #include "f2/tim_config.h"
 #include "f2/sdio_config.h"
-#include "f2/pwm_config.h"	
+#include "f2/pwm_config.h"
 #elif  defined(SOC_SERIES_STM32F4)
 #include "f4/dma_config.h"
 #include "f4/uart_config.h"
@@ -114,9 +114,9 @@ extern "C" {
 #include "mp1/qspi_config.h"
 #include "mp1/spi_config.h"
 #include "mp1/adc_config.h"
-#include "mp1/dac_config.h"    
+#include "mp1/dac_config.h"
 #include "mp1/tim_config.h"
-#include "mp1/pwm_config.h"    
+#include "mp1/pwm_config.h"
 #elif  defined(SOC_SERIES_STM32WL)
 #include "wl/dma_config.h"
 #include "wl/uart_config.h"
@@ -126,7 +126,7 @@ extern "C" {
 #include "wb/adc_config.h"
 #include "wb/dma_config.h"
 #include "wb/pwm_config.h"
-#include "wb/qspi_config.h" 
+#include "wb/qspi_config.h"
 #include "wb/spi_config.h"
 #include "wb/tim_config.h"
 #include "wb/uart_config.h"
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_crypto.c b/bsp/stm32/libraries/HAL_Drivers/drv_crypto.c
index b093516ca5..b5c858e581 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_crypto.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_crypto.c
@@ -19,7 +19,7 @@
 #include "drv_crypto.h"
 #include "board.h"
 #include "drv_config.h"
-     
+
 struct stm32_hwcrypto_device
 {
     struct rt_hwcrypto_device dev;
@@ -148,7 +148,7 @@ static rt_uint32_t _rng_rand(struct hwcrypto_rng *ctx)
     {
         return gen_random ;
     }
-    
+
     return 0;
 }
 
@@ -164,8 +164,8 @@ static rt_err_t _hash_update(struct hwcrypto_hash *ctx, const rt_uint8_t *in, rt
     rt_uint32_t tickstart = 0;
     rt_uint32_t result = RT_EOK;
     struct stm32_hwcrypto_device *stm32_hw_dev = (struct stm32_hwcrypto_device *)ctx->parent.device->user_data;
-    rt_mutex_take(&stm32_hw_dev->mutex, RT_WAITING_FOREVER);    
-    
+    rt_mutex_take(&stm32_hw_dev->mutex, RT_WAITING_FOREVER);
+
 #if defined(SOC_SERIES_STM32MP1)
     HASH_HandleTypeDef *HW_TypeDef = (HASH_HandleTypeDef *)(ctx->parent.contex);
     /* Start HASH computation using DMA transfer */
@@ -191,7 +191,7 @@ static rt_err_t _hash_update(struct hwcrypto_hash *ctx, const rt_uint8_t *in, rt
     {
         goto _exit;
     }
-    /* Wait for DMA transfer to complete */ 
+    /* Wait for DMA transfer to complete */
     tickstart = rt_tick_get();
     while (HAL_HASH_GetState(HW_TypeDef) == HAL_HASH_STATE_BUSY)
     {
@@ -201,11 +201,11 @@ static rt_err_t _hash_update(struct hwcrypto_hash *ctx, const rt_uint8_t *in, rt
             goto _exit;
         }
     }
-    
+
 #endif
 _exit:
     rt_mutex_release(&stm32_hw_dev->mutex);
-        
+
    return  result;
 }
 
@@ -243,12 +243,12 @@ static rt_err_t _hash_finish(struct hwcrypto_hash *ctx, rt_uint8_t *out, rt_size
     {
         goto _exit;
     }
-#endif    
-    
+#endif
+
 _exit:
     rt_mutex_release(&stm32_hw_dev->mutex);
-    
-    return result;     
+
+    return result;
 }
 
 static const struct hwcrypto_hash_ops hash_ops =
@@ -259,7 +259,7 @@ static const struct hwcrypto_hash_ops hash_ops =
 
 #endif /* BSP_USING_HASH */
 
-#if defined(BSP_USING_CRYP) 
+#if defined(BSP_USING_CRYP)
 static rt_err_t _cryp_crypt(struct hwcrypto_symmetric *ctx,
                             struct hwcrypto_symmetric_info *info)
 {
@@ -268,10 +268,10 @@ static rt_err_t _cryp_crypt(struct hwcrypto_symmetric *ctx,
 
     struct stm32_hwcrypto_device *stm32_hw_dev = (struct stm32_hwcrypto_device *)ctx->parent.device->user_data;
     rt_mutex_take(&stm32_hw_dev->mutex, RT_WAITING_FOREVER);
-    
+
 #if defined(SOC_SERIES_STM32MP1)
     CRYP_HandleTypeDef *HW_TypeDef = (CRYP_HandleTypeDef *)(ctx->parent.contex);
-    
+
     switch (ctx->parent.type)
     {
     case HWCRYPTO_TYPE_AES_ECB:
@@ -287,25 +287,25 @@ static rt_err_t _cryp_crypt(struct hwcrypto_symmetric *ctx,
        break;
 
     case HWCRYPTO_TYPE_DES_ECB:
-       HW_TypeDef->Init.Algorithm = CRYP_DES_ECB; 
+       HW_TypeDef->Init.Algorithm = CRYP_DES_ECB;
        break;
-       
+
     case HWCRYPTO_TYPE_DES_CBC:
-       HW_TypeDef->Init.Algorithm = CRYP_DES_CBC; 
+       HW_TypeDef->Init.Algorithm = CRYP_DES_CBC;
        break;
-       
+
     default :
         rt_kprintf("not support cryp type: %x", ctx->parent.type);
-        break; 
+        break;
     }
-    
+
     HAL_CRYP_DeInit(HW_TypeDef);
-    
+
     HW_TypeDef->Init.DataType       = CRYP_DATATYPE_8B;
     HW_TypeDef->Init.DataWidthUnit  = CRYP_DATAWIDTHUNIT_BYTE;
     HW_TypeDef->Init.KeySize        = CRYP_KEYSIZE_128B;
     HW_TypeDef->Init.pKey           = (uint32_t*)ctx->key;
-    
+
     result =  HAL_CRYP_Init(HW_TypeDef);
     if (result != HAL_OK)
     {
@@ -314,11 +314,11 @@ static rt_err_t _cryp_crypt(struct hwcrypto_symmetric *ctx,
     }
     if (info->mode == HWCRYPTO_MODE_ENCRYPT)
     {
-         result = HAL_CRYP_Encrypt_DMA(HW_TypeDef, (uint32_t *)info->in, info->length, (uint32_t *)info->out); 
+         result = HAL_CRYP_Encrypt_DMA(HW_TypeDef, (uint32_t *)info->in, info->length, (uint32_t *)info->out);
     }
     else if (info->mode == HWCRYPTO_MODE_DECRYPT)
     {
-         result = HAL_CRYP_Decrypt_DMA(HW_TypeDef, (uint32_t *)info->in, info->length, (uint32_t *)info->out);   
+         result = HAL_CRYP_Decrypt_DMA(HW_TypeDef, (uint32_t *)info->in, info->length, (uint32_t *)info->out);
     }
     else
     {
@@ -326,7 +326,7 @@ static rt_err_t _cryp_crypt(struct hwcrypto_symmetric *ctx,
         result = RT_ERROR;
         goto _exit;
     }
-    
+
     if (result != HAL_OK)
     {
         goto _exit;
@@ -334,28 +334,28 @@ static rt_err_t _cryp_crypt(struct hwcrypto_symmetric *ctx,
 
     tickstart = rt_tick_get();
     while (HAL_CRYP_GetState(HW_TypeDef) != HAL_CRYP_STATE_READY)
-    {   
+    {
         if (rt_tick_get() - tickstart > 0xFFFF)
         {
             result = RT_ETIMEOUT;
             goto _exit;
         }
     }
-  
+
 #endif
-    
+
     if (result != HAL_OK)
     {
         goto _exit;
     }
-    
+
 _exit:
     rt_mutex_release(&stm32_hw_dev->mutex);
 
-    return result;    
+    return result;
 }
 
-static const struct hwcrypto_symmetric_ops cryp_ops = 
+static const struct hwcrypto_symmetric_ops cryp_ops =
 {
     .crypt = _cryp_crypt
 };
@@ -364,7 +364,7 @@ static const struct hwcrypto_symmetric_ops cryp_ops =
 static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx)
 {
     rt_err_t res = RT_EOK;
-    
+
     switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
     {
 #if defined(BSP_USING_RNG)
@@ -417,11 +417,11 @@ static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx)
 #endif /* defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) */
         ctx->contex = hcrc;
         ((struct hwcrypto_crc *)ctx)->ops = &crc_ops;
-        
+
         break;
     }
 #endif /* BSP_USING_CRC */
-    
+
 #if defined(BSP_USING_HASH)
     case HWCRYPTO_TYPE_MD5:
     case HWCRYPTO_TYPE_SHA1:
@@ -437,18 +437,18 @@ static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx)
         /* enable dma for hash */
         __HAL_RCC_DMA2_CLK_ENABLE();
         HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 2, 0);
-        HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); 
+        HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn);
 
         hash->Init.DataType = HASH_DATATYPE_8B;
         if (HAL_HASH_Init(hash) != HAL_OK)
         {
             res = -RT_ERROR;
-        } 
+        }
 #endif
         ctx->contex = hash;
         ((struct hwcrypto_hash *)ctx)->ops = &hash_ops;
-        
-        break;  
+
+        break;
     }
 #endif /* BSP_USING_HASH */
 
@@ -480,14 +480,14 @@ static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx)
         {
             res = -RT_ERROR;
         }
-#endif  
+#endif
         ctx->contex = cryp;
         ((struct hwcrypto_symmetric *)ctx)->ops = &cryp_ops;
 
-        break;  
+        break;
     }
 #endif  /* BSP_USING_CRYP */
-    
+
     default:
         res = -RT_ERROR;
         break;
@@ -506,11 +506,11 @@ static void _crypto_destroy(struct rt_hwcrypto_ctx *ctx)
 
 #if defined(BSP_USING_CRC)
     case HWCRYPTO_TYPE_CRC:
-        __HAL_CRC_DR_RESET((CRC_HandleTypeDef *)ctx-> contex);			
+        __HAL_CRC_DR_RESET((CRC_HandleTypeDef *)ctx-> contex);
         HAL_CRC_DeInit((CRC_HandleTypeDef *)(ctx->contex));
         break;
 #endif /* BSP_USING_CRC */
-        
+
 #if defined(BSP_USING_HASH)
     case HWCRYPTO_TYPE_MD5:
     case HWCRYPTO_TYPE_SHA1:
@@ -529,7 +529,7 @@ static void _crypto_destroy(struct rt_hwcrypto_ctx *ctx)
          HAL_CRYP_DeInit((CRYP_HandleTypeDef *)(ctx->contex));
          break;
 #endif /* BSP_USING_CRYP */
-             
+
     default:
         break;
     }
@@ -548,7 +548,7 @@ static rt_err_t _crypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcry
         if (des->contex && src->contex)
         {
             rt_memcpy(des->contex, src->contex, sizeof(RNG_HandleTypeDef));
-        }    
+        }
         break;
 #endif /* BSP_USING_RNG */
 
@@ -560,7 +560,7 @@ static rt_err_t _crypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcry
         }
         break;
 #endif /* BSP_USING_CRC */
-        
+
 #if defined(BSP_USING_HASH)
     case HWCRYPTO_TYPE_MD5:
     case HWCRYPTO_TYPE_SHA1:
@@ -568,7 +568,7 @@ static rt_err_t _crypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcry
         if (des->contex && src->contex)
         {
             rt_memcpy(des->contex, src->contex, sizeof(HASH_HandleTypeDef));
-        } 
+        }
         break;
 #endif /* BSP_USING_HASH */
 
@@ -577,14 +577,14 @@ static rt_err_t _crypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcry
     case HWCRYPTO_TYPE_DES:
     case HWCRYPTO_TYPE_3DES:
     case HWCRYPTO_TYPE_RC4:
-    case HWCRYPTO_TYPE_GCM:    
+    case HWCRYPTO_TYPE_GCM:
         if (des->contex && src->contex)
         {
             rt_memcpy(des->contex, src->contex, sizeof(CRYP_HandleTypeDef));
-        } 
+        }
         break;
 #endif /* BSP_USING_CRYP */
-        
+
     default:
         res = -RT_ERROR;
         break;
@@ -606,7 +606,7 @@ static void _crypto_reset(struct rt_hwcrypto_ctx *ctx)
         __HAL_CRC_DR_RESET((CRC_HandleTypeDef *)ctx-> contex);
         break;
 #endif /* BSP_USING_CRC */
-        
+
 #if defined(BSP_USING_HASH)
     case HWCRYPTO_TYPE_MD5:
     case HWCRYPTO_TYPE_SHA1:
@@ -614,16 +614,16 @@ static void _crypto_reset(struct rt_hwcrypto_ctx *ctx)
         __HAL_HASH_RESET_HANDLE_STATE((HASH_HandleTypeDef *)(ctx->contex));
         break;
 #endif /* BSP_USING_HASH*/
-        
+
 #if defined(BSP_USING_CRYP)
     case HWCRYPTO_TYPE_AES:
     case HWCRYPTO_TYPE_DES:
     case HWCRYPTO_TYPE_3DES:
     case HWCRYPTO_TYPE_RC4:
-    case HWCRYPTO_TYPE_GCM:  
+    case HWCRYPTO_TYPE_GCM:
         break;
 #endif /* BSP_USING_CRYP */
-        
+
     default:
         break;
     }
@@ -636,9 +636,9 @@ void HASH2_DMA_IN_IRQHandler(void)
 
     /* enter interrupt */
     rt_interrupt_enter();
-    
+
     HAL_DMA_IRQHandler(&hdma_hash_in);
-    
+
     /* leave interrupt */
     rt_interrupt_leave();
 }
@@ -646,14 +646,14 @@ void HASH2_DMA_IN_IRQHandler(void)
 
 #if defined(CRYP2_IN_DMA_INSTANCE)
 void CRYP2_DMA_IN_IRQHandler(void)
-{   
+{
     extern DMA_HandleTypeDef hdma_cryp_in;
 
     /* enter interrupt */
     rt_interrupt_enter();
-    
+
     HAL_DMA_IRQHandler(&hdma_cryp_in);
-    
+
     /* leave interrupt */
     rt_interrupt_leave();
 }
@@ -663,12 +663,12 @@ void CRYP2_DMA_IN_IRQHandler(void)
 void CRYP2_DMA_OUT_IRQHandler(void)
 {
     extern DMA_HandleTypeDef hdma_cryp_out;
-    
+
     /* enter interrupt */
     rt_interrupt_enter();
-    
+
     HAL_DMA_IRQHandler(&hdma_cryp_out);
-    
+
     /* leave interrupt */
     rt_interrupt_leave();
 }
@@ -690,7 +690,7 @@ int stm32_hw_crypto_device_init(void)
     _crypto_dev.dev.ops = &_ops;
 #if defined(BSP_USING_UDID)
 
-#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) 
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
     cpuid[0] = HAL_GetUIDw0();
     cpuid[1] = HAL_GetUIDw1();
 #elif defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_dac.c b/bsp/stm32/libraries/HAL_Drivers/drv_dac.c
index 3ed7aa6762..4916f65513 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_dac.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_dac.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -11,7 +11,7 @@
 
 #include 
 
-#if defined(BSP_USING_DAC1) || defined(BSP_USING_DAC2) 
+#if defined(BSP_USING_DAC1) || defined(BSP_USING_DAC2)
 #include "drv_config.h"
 
 //#define DRV_DEBUG
@@ -23,7 +23,7 @@ static DAC_HandleTypeDef dac_config[] =
 #ifdef BSP_USING_DAC1
     DAC1_CONFIG,
 #endif
-    
+
 #ifdef BSP_USING_DAC2
     DAC2_CONFIG,
 #endif
@@ -37,32 +37,6 @@ struct stm32_dac
 
 static struct stm32_dac stm32_dac_obj[sizeof(dac_config) / sizeof(dac_config[0])];
 
-static rt_err_t stm32_dac_enabled(struct rt_dac_device *device, rt_uint32_t channel)
-{
-    DAC_HandleTypeDef *stm32_dac_handler;
-    RT_ASSERT(device != RT_NULL);
-    stm32_dac_handler = device->parent.user_data;
-
-#if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4)
-        HAL_DAC_Start(stm32_dac_handler, channel);
-#endif
-    
-    return RT_EOK;
-}
-
-static rt_err_t stm32_dac_disabled(struct rt_dac_device *device, rt_uint32_t channel)
-{
-    DAC_HandleTypeDef *stm32_dac_handler;
-    RT_ASSERT(device != RT_NULL);
-    stm32_dac_handler = device->parent.user_data;
-    
-#if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4)
-    HAL_DAC_Stop(stm32_dac_handler, channel);
-#endif
-    
-    return RT_EOK;
-}
-
 static rt_uint32_t stm32_dac_get_channel(rt_uint32_t channel)
 {
     rt_uint32_t stm32_channel = 0;
@@ -83,19 +57,13 @@ static rt_uint32_t stm32_dac_get_channel(rt_uint32_t channel)
     return stm32_channel;
 }
 
-static rt_err_t stm32_set_dac_value(struct rt_dac_device *device, rt_uint32_t channel, rt_uint32_t *value)
+static rt_err_t stm32_dac_enabled(struct rt_dac_device *device, rt_uint32_t channel)
 {
     uint32_t dac_channel;
-    DAC_ChannelConfTypeDef DAC_ChanConf;	
     DAC_HandleTypeDef *stm32_dac_handler;
-   
     RT_ASSERT(device != RT_NULL);
-    RT_ASSERT(value != RT_NULL);
-
     stm32_dac_handler = device->parent.user_data;
 
-    rt_memset(&DAC_ChanConf, 0, sizeof(DAC_ChanConf));
-    
 #if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4)
     if ((channel <= 2) && (channel > 0))
     {
@@ -104,15 +72,69 @@ static rt_err_t stm32_set_dac_value(struct rt_dac_device *device, rt_uint32_t ch
     }
     else
     {
-      LOG_E("dac channel must be 1 or 2.");  
+      LOG_E("dac channel must be 1 or 2.");
       return -RT_ERROR;
     }
-#endif  
-    
+    HAL_DAC_Start(stm32_dac_handler, dac_channel);
+#endif
+
+    return RT_EOK;
+}
+
+static rt_err_t stm32_dac_disabled(struct rt_dac_device *device, rt_uint32_t channel)
+{
+    uint32_t dac_channel;
+    DAC_HandleTypeDef *stm32_dac_handler;
+    RT_ASSERT(device != RT_NULL);
+    stm32_dac_handler = device->parent.user_data;
+
 #if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4)
-    DAC_ChanConf.DAC_Trigger      = DAC_TRIGGER_NONE;             
+    if ((channel <= 2) && (channel > 0))
+    {
+        /* set stm32 dac channel */
+        dac_channel =  stm32_dac_get_channel(channel);
+    }
+    else
+    {
+      LOG_E("dac channel must be 1 or 2.");
+      return -RT_ERROR;
+    }
+    HAL_DAC_Stop(stm32_dac_handler, dac_channel);
+#endif
+
+    return RT_EOK;
+}
+
+static rt_err_t stm32_set_dac_value(struct rt_dac_device *device, rt_uint32_t channel, rt_uint32_t *value)
+{
+    uint32_t dac_channel;
+    DAC_ChannelConfTypeDef DAC_ChanConf;
+    DAC_HandleTypeDef *stm32_dac_handler;
+
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(value != RT_NULL);
+
+    stm32_dac_handler = device->parent.user_data;
+
+    rt_memset(&DAC_ChanConf, 0, sizeof(DAC_ChanConf));
+
+#if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4)
+    if ((channel <= 2) && (channel > 0))
+    {
+        /* set stm32 dac channel */
+        dac_channel =  stm32_dac_get_channel(channel);
+    }
+    else
+    {
+      LOG_E("dac channel must be 1 or 2.");
+      return -RT_ERROR;
+    }
+#endif
+
+#if defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4)
+    DAC_ChanConf.DAC_Trigger      = DAC_TRIGGER_NONE;
     DAC_ChanConf.DAC_OutputBuffer = DAC_OUTPUTBUFFER_DISABLE;
-#endif    
+#endif
     /* config dac out channel*/
     if (HAL_DAC_ConfigChannel(stm32_dac_handler, &DAC_ChanConf, dac_channel) != HAL_OK)
     {
@@ -131,7 +153,7 @@ static rt_err_t stm32_set_dac_value(struct rt_dac_device *device, rt_uint32_t ch
         LOG_D("Start dac Error!\n");
         return -RT_ERROR;
     }
-  
+
     return RT_EOK;
 }
 
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_dma.h b/bsp/stm32/libraries/HAL_Drivers/drv_dma.h
index 12056485d2..976df37975 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_dma.h
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_dma.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,10 +20,10 @@ extern "C" {
 #endif
 
 #if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L0) \
-	|| defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)
+    || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)
 #define DMA_INSTANCE_TYPE              DMA_Channel_TypeDef
 #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)\
-	|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
+    || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
 #define DMA_INSTANCE_TYPE              DMA_Stream_TypeDef
 #endif /*  defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL)  */
 
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_eth.c b/bsp/stm32/libraries/HAL_Drivers/drv_eth.c
index 8b191453cb..0506f6495c 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_eth.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_eth.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_eth.h b/bsp/stm32/libraries/HAL_Drivers/drv_eth.h
index 07f25b107e..44eb75bbb8 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_eth.h
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_eth.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash.h b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash.h
index 3a9d5be061..8243e80bbf 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash.h
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f0.c b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f0.c
index b8d42c8492..778fbe1a84 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f0.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f0.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f1.c b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f1.c
index 01f706cd8f..624bf60070 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f1.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f1.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -155,7 +155,7 @@ int stm32_flash_erase_bank(uint32_t bank, rt_uint32_t addr, size_t size)
     EraseInitStruct.PageAddress = GetPage(addr);
     EraseInitStruct.NbPages     = (size + FLASH_PAGE_SIZE - 1) / FLASH_PAGE_SIZE;
     EraseInitStruct.Banks       = bank;
-    
+
     if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK)
     {
         result = -RT_ERROR;
@@ -186,8 +186,8 @@ __exit:
  */
 int stm32_flash_erase(rt_uint32_t addr, size_t size)
 {
-#if defined(FLASH_BANK2_END)    
-    rt_err_t result = RT_EOK;   
+#if defined(FLASH_BANK2_END)
+    rt_err_t result = RT_EOK;
     rt_uint32_t addr_bank1 = 0;
     rt_uint32_t size_bank1 = 0;
     rt_uint32_t addr_bank2 = 0;
@@ -203,7 +203,7 @@ int stm32_flash_erase(rt_uint32_t addr, size_t size)
     {
         size_bank1 = 0;
         addr_bank2 = addr;
-        size_bank2 = size; 
+        size_bank2 = size;
     }
     else
     {
@@ -222,7 +222,7 @@ int stm32_flash_erase(rt_uint32_t addr, size_t size)
             goto __exit;
         }
     }
-    
+
     if(size_bank2)
     {
         LOG_D("bank2: addr (0x%p), size %d", (void *)addr_bank2, size_bank2);
@@ -233,12 +233,12 @@ int stm32_flash_erase(rt_uint32_t addr, size_t size)
         }
     }
 
-__exit:    
+__exit:
     if(result != RT_EOK)
     {
         return result;
     }
-    
+
     return size_bank1 + size_bank2;
 #else
     return stm32_flash_erase_bank(FLASH_BANK_1, addr, size);
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f2.c b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f2.c
index b3ddf1ae6c..d716b46ffe 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f2.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f2.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f4.c b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f4.c
index a9ed886c32..c65ecb20f3 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f4.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f4.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f7.c b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f7.c
index 276c9ba0b9..522dc8e6a7 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f7.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f7.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -43,7 +43,7 @@
 static rt_uint32_t GetSector(rt_uint32_t Address)
 {
     uint32_t sector = 0;
-  
+
 #if defined (FLASH_OPTCR_nDBANK)
     FLASH_OBProgramInitTypeDef OBInit;
     uint32_t nbank = 0;
@@ -53,7 +53,7 @@ static rt_uint32_t GetSector(rt_uint32_t Address)
     nbank = ((OBInit.USERConfig & 0x20000000U) >> 29);
     //1:single bank mode
     if (1 == nbank)
-    {  
+    {
         if ((Address < ADDR_FLASH_SECTOR_1) && (Address >= ADDR_FLASH_SECTOR_0))
         {
             sector = FLASH_SECTOR_0;
@@ -98,7 +98,7 @@ static rt_uint32_t GetSector(rt_uint32_t Address)
         {
             sector = FLASH_SECTOR_10;
         }
-        else 
+        else
         {
             sector = FLASH_SECTOR_11;
         }
@@ -153,7 +153,7 @@ static rt_uint32_t GetSector(rt_uint32_t Address)
     {
         sector = FLASH_SECTOR_10;
     }
-    else 
+    else
     {
         sector = FLASH_SECTOR_11;
     }
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_g0.c b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_g0.c
index c5eefb9497..90bb633c86 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_g0.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_g0.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_h7.c b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_h7.c
index da42bb92b6..2b8a4e1b3e 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_h7.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_h7.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -9,6 +9,7 @@
  * 2019-3-2       jinsheng     add Macro judgment
  * 2020-1-6       duminmin     support single bank mode
  * 2020-5-17      yufanyufan77 support support H7
+ * 2021-3-3       zhuyf233     fix some bugs
  */
 
 #include "board.h"
@@ -24,110 +25,6 @@
 //#define DRV_DEBUG
 #define LOG_TAG                "drv.flash"
 #include 
-#define ADDR_FLASH_SECTOR_0     ((rt_uint32_t)0x08000000) /* Base address of Sector 0, 128 Kbytes */
-#define ADDR_FLASH_SECTOR_1     ((rt_uint32_t)0x08020000) /* Base address of Sector 1, 128 Kbytes */
-#define ADDR_FLASH_SECTOR_2     ((rt_uint32_t)0x08040000) /* Base address of Sector 2, 128 Kbytes */
-#define ADDR_FLASH_SECTOR_3     ((rt_uint32_t)0x08060000) /* Base address of Sector 3, 128 Kbytes */
-#define ADDR_FLASH_SECTOR_4     ((rt_uint32_t)0x08080000) /* Base address of Sector 4, 128 Kbytes */
-#define ADDR_FLASH_SECTOR_5     ((rt_uint32_t)0x080A0000) /* Base address of Sector 5, 128 Kbytes */
-#define ADDR_FLASH_SECTOR_6     ((rt_uint32_t)0x080C0000) /* Base address of Sector 6, 128 Kbytes */
-#define ADDR_FLASH_SECTOR_7     ((rt_uint32_t)0x080E0000) /* Base address of Sector 7, 128 Kbytes */
-#define ADDR_FLASH_SECTOR_8     ((rt_uint32_t)0x08100000) /* Base address of Sector 8, 128 Kbytes */
-
-#define FLASH_SECTOR_0             0U       /* Sector Number 0   */
-#define FLASH_SECTOR_1             1U       /* Sector Number 1   */
-#define FLASH_SECTOR_2             2U       /* Sector Number 2   */
-#define FLASH_SECTOR_3             3U       /* Sector Number 3   */
-#define FLASH_SECTOR_4             4U       /* Sector Number 4   */
-#define FLASH_SECTOR_5             5U       /* Sector Number 5   */
-#define FLASH_SECTOR_6             6U       /* Sector Number 6   */
-#define FLASH_SECTOR_7             7U       /* Sector Number 7   */
-/**
-  * @brief  Gets the sector of a given address
-  * @param  addr flash address
-  * @param  flash bank
-  * @param  flash sector
-  * @retval The sector of a given address
-  */
-static void GetSector(rt_uint32_t Address,uint32_t* bank,uint32_t* sector)
-{
-#if defined (FLASH_OPTCR_nDBANK)
-    FLASH_OBProgramInitTypeDef OBInit;
-    uint32_t nbank = 0;
-
-    /* get duel bank ability:nDBANK(Bit29) */
-    HAL_FLASHEx_OBGetConfig(&OBInit);
-    nbank = ((OBInit.USERConfig & 0x20000000U) >> 29);
-    /* 1:single bank mode */
-    if (1 == nbank)
-    {  
-        if ((Address < ADDR_FLASH_SECTOR_1) && (Address >= ADDR_FLASH_SECTOR_0))
-        {
-            sector = FLASH_SECTOR_0;
-        }
-        else if ((Address < ADDR_FLASH_SECTOR_2) && (Address >= ADDR_FLASH_SECTOR_1))
-        {
-            sector = FLASH_SECTOR_1;
-        }
-        else if ((Address < ADDR_FLASH_SECTOR_3) && (Address >= ADDR_FLASH_SECTOR_2))
-        {
-            sector = FLASH_SECTOR_2;
-        }
-        else if ((Address < ADDR_FLASH_SECTOR_4) && (Address >= ADDR_FLASH_SECTOR_3))
-        {
-            sector = FLASH_SECTOR_3;
-        }
-        else if ((Address < ADDR_FLASH_SECTOR_5) && (Address >= ADDR_FLASH_SECTOR_4))
-        {
-            sector = FLASH_SECTOR_4;
-        }
-        else if ((Address < ADDR_FLASH_SECTOR_6) && (Address >= ADDR_FLASH_SECTOR_5))
-        {
-            sector = FLASH_SECTOR_5;
-        }
-        else if ((Address < ADDR_FLASH_SECTOR_7) && (Address >= ADDR_FLASH_SECTOR_6))
-        {
-            sector = FLASH_SECTOR_6;
-        }
-        else if ((Address < ADDR_FLASH_SECTOR_8) && (Address >= ADDR_FLASH_SECTOR_7))
-        {
-            sector = FLASH_SECTOR_7;
-        }
-        else if ((Address < ADDR_FLASH_SECTOR_9) && (Address >= ADDR_FLASH_SECTOR_8))
-        {
-            sector = FLASH_SECTOR_8;
-        }
-        else if ((Address < ADDR_FLASH_SECTOR_10) && (Address >= ADDR_FLASH_SECTOR_9))
-        {
-            sector = FLASH_SECTOR_9;
-        }
-        else if ((Address < ADDR_FLASH_SECTOR_11) && (Address >= ADDR_FLASH_SECTOR_10))
-        {
-            sector = FLASH_SECTOR_10;
-        }
-        else 
-        {
-            sector = FLASH_SECTOR_11;
-        }
-    }
-    else  /* 0:dual bank mode */
-    {
-        LOG_E("rtthread doesn't support duel bank mode yet!");
-        RT_ASSERT(0);
-    }
-#else /* no dual bank ability */	
-    *sector = (Address&0xffffff)/FLASH_SIZE_GRANULARITY_128K;
-    if(*sector>7)
-    {
-        *bank = FLASH_BANK_1;
-        *sector = *sector/2;
-    }
-    else
-    {
-        *bank = FLASH_BANK_2;
-    }
-#endif
-}
 
 /**
  * Read data from flash.
@@ -137,16 +34,16 @@ static void GetSector(rt_uint32_t Address,uint32_t* bank,uint32_t* sector)
  * @param buf buffer to store read data
  * @param size read bytes size
  *
- * @return result
+ * @retval The length of bytes that have been read
  */
 int stm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
 {
     size_t i;
 
-    if ((addr + size) > STM32_FLASH_END_ADDRESS)
+    if ((addr + size - 1) > FLASH_END)
     {
         LOG_E("read outrange flash size! addr is (0x%p)", (void *)(addr + size));
-        return -1;
+        return -RT_ERROR;
     }
 
     for (i = 0; i < size; i++, buf++, addr++)
@@ -166,47 +63,68 @@ int stm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
  * @param buf the write data buffer
  * @param size write bytes size
  *
- * @return result
+ * @return The length of bytes that have been written
  */
 int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
 {
     rt_err_t result      = RT_EOK;
-    rt_uint32_t end_addr = addr + size;
-    rt_uint32_t bank = addr/ADDR_FLASH_SECTOR_8;;
+    rt_uint32_t end_addr = addr + size - 1, write_addr;
+    rt_uint32_t write_granularity = FLASH_NB_32BITWORD_IN_FLASHWORD * 4;
+    rt_uint32_t write_size = write_granularity;
+    rt_uint8_t write_buffer[32] = {0};
 
-    if ((end_addr) > STM32_FLASH_END_ADDRESS)
+    if ((end_addr) > FLASH_END)
     {
         LOG_E("write outrange flash size! addr is (0x%p)", (void *)(addr + size));
         return -RT_EINVAL;
     }
+    
+    if(addr % 32 != 0)
+    {
+        LOG_E("write addr must be 32-byte alignment");
+        return -RT_EINVAL;
+    }
 
     if (size < 1)
     {
         return -RT_EINVAL;
     }
 
-    /* Unlock the Flash to enable the flash control register access */
     HAL_FLASH_Unlock();
-    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR );
-
-    for (size_t i = 0; i < size/32; i++, addr+=32, buf+=32)
+    write_addr = (uint32_t)buf;
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR);
+    while (addr < end_addr)
     {
-        /* write data to flash */
-        if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_FLASHWORD, addr,  (uint64_t)((uint32_t)buf)) == HAL_OK)
+        if(end_addr - addr + 1 < write_granularity)
         {
-            if (*(rt_uint8_t *)addr != *buf)
+            write_size = end_addr - addr + 1;
+            for(size_t i = 0; i < write_size; i++)
             {
-                result = -RT_ERROR;
-                break;
+                write_buffer[i] = *((uint8_t *)(write_addr + i));
             }
+            write_addr = (uint32_t)((rt_uint32_t *)write_buffer);
+        }
+        if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_FLASHWORD, addr, write_addr) == HAL_OK)
+        {
+            for(rt_uint8_t i = 0; i < write_size; i++)
+            {
+                if (*(rt_uint8_t *)(addr + i) != *(rt_uint8_t *)(write_addr + i))
+                {
+                    result = -RT_ERROR;
+                    goto __exit;
+                }
+            }
+            addr += write_granularity;
+            write_addr  += write_granularity;
         }
         else
         {
             result = -RT_ERROR;
-            break;
+            goto __exit;
         }
     }
 
+__exit:
     HAL_FLASH_Lock();
 
     if (result != RT_EOK)
@@ -230,42 +148,74 @@ int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
 int stm32_flash_erase(rt_uint32_t addr, size_t size)
 {
     rt_err_t result = RT_EOK;
-    rt_uint32_t FirstSector = 0, NbOfSectors = 0;
     rt_uint32_t SECTORError = 0;
-    rt_uint32_t bank = 0;
 
-    if ((addr + size) > STM32_FLASH_END_ADDRESS)
+    if ((addr + size - 1) > FLASH_END)
     {
         LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void *)(addr + size));
         return -RT_EINVAL;
     }
 
+    rt_uint32_t addr_bank1 = 0;
+    rt_uint32_t size_bank1 = 0;
+    rt_uint32_t addr_bank2 = 0;
+    rt_uint32_t size_bank2 = 0;
+
+    if((addr + size) < FLASH_BANK2_BASE)
+    {
+        addr_bank1 = addr;
+        size_bank1 = size;
+        size_bank2 = 0;
+    }
+    else if(addr >= FLASH_BANK2_BASE)
+    {
+        size_bank1 = 0;
+        addr_bank2 = addr;
+        size_bank2 = size; 
+    }
+    else
+    {
+        addr_bank1 = addr;
+        size_bank1 = FLASH_BANK2_BASE - addr_bank1;
+        addr_bank2 = FLASH_BANK2_BASE;
+        size_bank2 = addr + size - FLASH_BANK2_BASE;
+    }
+
     /*Variable used for Erase procedure*/
     FLASH_EraseInitTypeDef EraseInitStruct;
-
     /* Unlock the Flash to enable the flash control register access */
     HAL_FLASH_Unlock();
-
-    /* Get the 1st sector to erase */
-    GetSector(addr,&bank,&FirstSector);
-    /* Get the number of sector to erase from 1st sector */
-    GetSector(addr + size,0,&NbOfSectors);
-    NbOfSectors = NbOfSectors - FirstSector + 1;
-    /* Fill EraseInit structure */
     EraseInitStruct.TypeErase     = FLASH_TYPEERASE_SECTORS;
     EraseInitStruct.VoltageRange  = FLASH_VOLTAGE_RANGE_3;
-    EraseInitStruct.Sector        = FirstSector;
-    EraseInitStruct.NbSectors     = NbOfSectors;
-    EraseInitStruct.Banks         = bank;
-
-    if (HAL_FLASHEx_Erase(&EraseInitStruct, &SECTORError) != HAL_OK)
+    SCB_DisableDCache();
+    
+    if(size_bank1)
     {
-        result = -RT_ERROR;
-        goto __exit;
+        EraseInitStruct.Sector    = (addr_bank1 - FLASH_BANK1_BASE) / FLASH_SECTOR_SIZE;
+        EraseInitStruct.NbSectors = (addr_bank1 + size_bank1 -1 - FLASH_BANK1_BASE) / FLASH_SECTOR_SIZE - EraseInitStruct.Sector + 1;
+        EraseInitStruct.Banks = FLASH_BANK_1;
+        if (HAL_FLASHEx_Erase(&EraseInitStruct, &SECTORError) != HAL_OK)
+        {
+            result = -RT_ERROR;
+            goto __exit;
+        }
+    }
+
+    if(size_bank2)
+    {
+        EraseInitStruct.Sector    = (addr_bank2 - FLASH_BANK2_BASE) / FLASH_SECTOR_SIZE;
+        EraseInitStruct.NbSectors = (addr_bank2 + size_bank2 -1 - FLASH_BANK2_BASE) / FLASH_SECTOR_SIZE - EraseInitStruct.Sector + 1;
+        EraseInitStruct.Banks = FLASH_BANK_2;
+        if (HAL_FLASHEx_Erase(&EraseInitStruct, &SECTORError) != HAL_OK)
+        {
+            result = -RT_ERROR;
+            goto __exit;
+        }
     }
 
 __exit:
 
+    SCB_EnableDCache();
     HAL_FLASH_Lock();
 
     if (result != RT_EOK)
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_l4.c b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_l4.c
index 00f84711f5..4da4207961 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_l4.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_l4.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_wb.c b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_wb.c
index d818e47d8c..33cbc78c3f 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_wb.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_wb.c
@@ -1,10 +1,10 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author       		Notes
+ * Date           Author            Notes
  * 2020-10-14     Dozingfiretruck   first version
  */
 
@@ -183,7 +183,7 @@ int stm32_flash_erase(rt_uint32_t addr, size_t size)
 
     /* Fill EraseInit structure*/
     EraseInitStruct.TypeErase   = FLASH_TYPEERASE_PAGES;
-    EraseInitStruct.Page 				= GetPage(addr);
+    EraseInitStruct.Page                = GetPage(addr);
     EraseInitStruct.NbPages     = (size + FLASH_PAGE_SIZE - 1) / FLASH_PAGE_SIZE;
 
     if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK)
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_gpio.c b/bsp/stm32/libraries/HAL_Drivers/drv_gpio.c
index 67bed660c0..26a47a0709 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_gpio.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_gpio.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_gpio.h b/bsp/stm32/libraries/HAL_Drivers/drv_gpio.h
index bbcbdcccff..f0d92d7be7 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_gpio.h
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_gpio.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author            Notes
  * 2018-11-06     balanceTWK        first version
  * 2020-06-16     thread-liu        add stm32mp1
- * 2020-09-01     thread-liu        add GPIOZ 
+ * 2020-09-01     thread-liu        add GPIOZ
  * 2020-09-18     geniusgogo        optimization design pin-index algorithm
  */
 
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c b/bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c
index 4550c2776f..22241d2d2c 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -175,10 +175,10 @@ static void pclkx_doubler_get(rt_uint32_t *pclk1_doubler, rt_uint32_t *pclk2_dou
     }
     if (RCC_ClkInitStruct.APB2_Div != RCC_APB2_DIV1)
     {
-       *pclk2_doubler = 2; 
+       *pclk2_doubler = 2;
     }
 #else
-    if (RCC_ClkInitStruct.APB1CLKDivider != RCC_HCLK_DIV1)    
+    if (RCC_ClkInitStruct.APB1CLKDivider != RCC_HCLK_DIV1)
     {
          *pclk1_doubler = 2;
     }
@@ -288,7 +288,7 @@ static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_
     {
         tim->Instance->CR1 &= (~TIM_OPMODE_SINGLE);
     }
-	
+
     /* start timer */
     if (HAL_TIM_Base_Start_IT(tim) != HAL_OK)
     {
@@ -344,7 +344,7 @@ static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
 #elif defined(SOC_SERIES_STM32WB)
         if (tim->Instance == TIM16 || tim->Instance == TIM17)
 #elif defined(SOC_SERIES_STM32MP1)
-       if(tim->Instance == TIM14 || tim->Instance == TIM16 || tim->Instance == TIM17)  
+       if(tim->Instance == TIM14 || tim->Instance == TIM16 || tim->Instance == TIM17)
 #elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
         if (0)
 #endif
@@ -458,7 +458,7 @@ void TIM8_UP_TIM13_IRQHandler(void)
 #ifdef BSP_USING_TIM14
 #if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
     void TIM8_TRG_COM_TIM14_IRQHandler(void)
-#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1) 
+#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1)
     void TIM14_IRQHandler(void)
 #endif
 {
@@ -480,9 +480,9 @@ void TIM1_BRK_TIM15_IRQHandler(void)
 }
 #endif
 #ifdef BSP_USING_TIM16
-#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB) 
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB)
     void TIM1_UP_TIM16_IRQHandler(void)
-#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1) 
+#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1)
     void TIM16_IRQHandler(void)
 #endif
 {
@@ -494,9 +494,9 @@ void TIM1_BRK_TIM15_IRQHandler(void)
 }
 #endif
 #ifdef BSP_USING_TIM17
-#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB) 
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB)
     void TIM1_TRG_COM_TIM17_IRQHandler(void)
-#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1) 
+#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1)
     void TIM17_IRQHandler(void)
 #endif
 {
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_lcd.c b/bsp/stm32/libraries/HAL_Drivers/drv_lcd.c
index 1eee5b69a0..5d170016b8 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_lcd.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_lcd.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -258,7 +258,7 @@ void turn_on_lcd_backlight(void)
 #else
 void turn_on_lcd_backlight(void)
 {
-    
+
 }
 #endif
 
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_lcd_mipi.c b/bsp/stm32/libraries/HAL_Drivers/drv_lcd_mipi.c
index 3928353153..275a18e925 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_lcd_mipi.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_lcd_mipi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author         Notes
  * 2019-05-23     WillianChan    first version
  */
- 
+
 #include 
 
 #ifdef BSP_USING_LCD_MIPI
@@ -23,7 +23,7 @@ struct stm32_lcd
     struct rt_device parent;
     struct rt_device_graphic_info info;
 };
-static struct stm32_lcd lcd; 
+static struct stm32_lcd lcd;
 
 extern void stm32_mipi_lcd_init(void);
 extern void stm32_mipi_lcd_config(rt_uint32_t pixel_format);
@@ -32,14 +32,14 @@ extern void stm32_mipi_display_off(void);
 
 rt_err_t ltdc_init(void)
 {
-    uint32_t lcd_clock      = 27429; 
+    uint32_t lcd_clock      = 27429;
     uint32_t lanebyte_clock = 62500;
-    
+
     uint32_t HSA = LCD_HSYNC, HFP = LCD_HFP, HBP = LCD_HBP, HACT = LCD_WIDTH;
     uint32_t VSA = LCD_VSYNC, VFP = LCD_VFP, VBP = LCD_VBP, VACT = LCD_HEIGHT;
 
     stm32_mipi_lcd_init();
- 
+
     __HAL_RCC_LTDC_CLK_ENABLE();
     __HAL_RCC_LTDC_FORCE_RESET();
     __HAL_RCC_LTDC_RELEASE_RESET();
@@ -47,92 +47,92 @@ rt_err_t ltdc_init(void)
     __HAL_RCC_DSI_CLK_ENABLE();
     __HAL_RCC_DSI_FORCE_RESET();
     __HAL_RCC_DSI_RELEASE_RESET();
-    
+
     RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
-    
+
     PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC;
     PeriphClkInitStruct.PLLSAI.PLLSAIN       = 384;
     PeriphClkInitStruct.PLLSAI.PLLSAIR       = 7;
     PeriphClkInitStruct.PLLSAIDivR           = RCC_PLLSAIDIVR_2;
     HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
-    
+
     HAL_NVIC_SetPriority(LTDC_IRQn,  3, 0);
     HAL_NVIC_SetPriority(DSI_IRQn,   3, 0);
 
     HAL_NVIC_EnableIRQ(LTDC_IRQn);
     HAL_NVIC_EnableIRQ(DSI_IRQn);
-    
+
     DSI_PLLInitTypeDef dsi_pll;
-    
-    hdsi.Instance = DSI; 
+
+    hdsi.Instance = DSI;
     hdsi.Init.NumberOfLanes = DSI_TWO_DATA_LANES;
     hdsi.Init.TXEscapeCkdiv = lanebyte_clock / 15620;
-    
+
     dsi_pll.PLLNDIV  = 125;
     dsi_pll.PLLIDF   = DSI_PLL_IN_DIV2;
-    dsi_pll.PLLODF   = DSI_PLL_OUT_DIV1; 
-    
+    dsi_pll.PLLODF   = DSI_PLL_OUT_DIV1;
+
     HAL_DSI_DeInit(&hdsi);
-    HAL_DSI_Init(&hdsi, &dsi_pll); 
-    
+    HAL_DSI_Init(&hdsi, &dsi_pll);
+
     hdsi_video.VirtualChannelID             = 0;
     hdsi_video.ColorCoding                  = DSI_RGB888;
     hdsi_video.VSPolarity                   = DSI_VSYNC_ACTIVE_HIGH;
     hdsi_video.HSPolarity                   = DSI_HSYNC_ACTIVE_HIGH;
     hdsi_video.DEPolarity                   = DSI_DATA_ENABLE_ACTIVE_HIGH;
-    hdsi_video.Mode                         = DSI_VID_MODE_BURST; 
+    hdsi_video.Mode                         = DSI_VID_MODE_BURST;
     hdsi_video.NullPacketSize               = 0xFFF;
     hdsi_video.NumberOfChunks               = 0;
-    hdsi_video.PacketSize                   = HACT; 
+    hdsi_video.PacketSize                   = HACT;
     hdsi_video.HorizontalSyncActive         = (HSA * lanebyte_clock) / lcd_clock;
     hdsi_video.HorizontalBackPorch          = (HBP * lanebyte_clock) / lcd_clock;
-    hdsi_video.HorizontalLine               = ((HACT + HSA + HBP + HFP) * lanebyte_clock) / lcd_clock; 
+    hdsi_video.HorizontalLine               = ((HACT + HSA + HBP + HFP) * lanebyte_clock) / lcd_clock;
     hdsi_video.VerticalSyncActive           = VSA;
     hdsi_video.VerticalBackPorch            = VBP;
     hdsi_video.VerticalFrontPorch           = VFP;
-    hdsi_video.VerticalActive               = VACT; 
-    hdsi_video.LPCommandEnable              = DSI_LP_COMMAND_ENABLE; 
+    hdsi_video.VerticalActive               = VACT;
+    hdsi_video.LPCommandEnable              = DSI_LP_COMMAND_ENABLE;
     hdsi_video.LPLargestPacketSize          = 16;
     hdsi_video.LPVACTLargestPacketSize      = 0;
-    hdsi_video.LPHorizontalFrontPorchEnable = DSI_LP_HFP_ENABLE; 
-    hdsi_video.LPHorizontalBackPorchEnable  = DSI_LP_HBP_ENABLE; 
-    hdsi_video.LPVerticalActiveEnable       = DSI_LP_VACT_ENABLE; 
-    hdsi_video.LPVerticalFrontPorchEnable   = DSI_LP_VFP_ENABLE; 
-    hdsi_video.LPVerticalBackPorchEnable    = DSI_LP_VBP_ENABLE; 
-    hdsi_video.LPVerticalSyncActiveEnable   = DSI_LP_VSYNC_ENABLE; 
-    HAL_DSI_ConfigVideoMode(&hdsi, &hdsi_video); 
-    
+    hdsi_video.LPHorizontalFrontPorchEnable = DSI_LP_HFP_ENABLE;
+    hdsi_video.LPHorizontalBackPorchEnable  = DSI_LP_HBP_ENABLE;
+    hdsi_video.LPVerticalActiveEnable       = DSI_LP_VACT_ENABLE;
+    hdsi_video.LPVerticalFrontPorchEnable   = DSI_LP_VFP_ENABLE;
+    hdsi_video.LPVerticalBackPorchEnable    = DSI_LP_VBP_ENABLE;
+    hdsi_video.LPVerticalSyncActiveEnable   = DSI_LP_VSYNC_ENABLE;
+    HAL_DSI_ConfigVideoMode(&hdsi, &hdsi_video);
+
     DSI_PHY_TimerTypeDef dsi_phy;
-    
+
     dsi_phy.ClockLaneHS2LPTime  = 35;
     dsi_phy.ClockLaneLP2HSTime  = 35;
     dsi_phy.DataLaneHS2LPTime   = 35;
     dsi_phy.DataLaneLP2HSTime   = 35;
     dsi_phy.DataLaneMaxReadTime = 0;
     dsi_phy.StopWaitTime        = 10;
-    HAL_DSI_ConfigPhyTimer(&hdsi, &dsi_phy); 
-    
+    HAL_DSI_ConfigPhyTimer(&hdsi, &dsi_phy);
+
     hltdc.Instance = LTDC;
-    
+
     hltdc.Init.PCPolarity         = LTDC_PCPOLARITY_IPC;
     hltdc.Init.HorizontalSync     = (HSA - 1);
     hltdc.Init.AccumulatedHBP     = (HSA + HBP - 1);
     hltdc.Init.AccumulatedActiveW = (LCD_WIDTH + HSA + HBP - 1);
     hltdc.Init.TotalWidth         = (LCD_WIDTH + HSA + HBP + HFP - 1);
-    
+
     hltdc.LayerCfg->ImageWidth    = LCD_WIDTH;
-    hltdc.LayerCfg->ImageHeight   = LCD_HEIGHT; 
+    hltdc.LayerCfg->ImageHeight   = LCD_HEIGHT;
     hltdc.Init.Backcolor.Blue     = 0x00;
     hltdc.Init.Backcolor.Green    = 0x00;
     hltdc.Init.Backcolor.Red      = 0x00;
-    HAL_LTDCEx_StructInitFromVideoConfig(&hltdc, &(hdsi_video)); 
+    HAL_LTDCEx_StructInitFromVideoConfig(&hltdc, &(hdsi_video));
     HAL_LTDC_Init(&(hltdc));
-    
-    HAL_DSI_Start(&(hdsi)); 
+
+    HAL_DSI_Start(&(hdsi));
 
     stm32_mipi_lcd_config(RTGRAPHIC_PIXEL_FORMAT_ARGB888);
-    
-    return RT_EOK; 
+
+    return RT_EOK;
 }
 
 void ltdc_layer_init(uint16_t index, uint32_t framebuffer)
@@ -140,7 +140,7 @@ void ltdc_layer_init(uint16_t index, uint32_t framebuffer)
     LTDC_LayerCfgTypeDef layer_cfg;
 
     layer_cfg.WindowX0        = 0;
-    layer_cfg.WindowX1        = LCD_WIDTH; 
+    layer_cfg.WindowX1        = LCD_WIDTH;
     layer_cfg.WindowY0        = 0;
     layer_cfg.WindowY1        = LCD_HEIGHT;
     layer_cfg.PixelFormat     = LTDC_PIXEL_FORMAT_ARGB8888;
@@ -161,7 +161,7 @@ void ltdc_layer_init(uint16_t index, uint32_t framebuffer)
 void LTDC_IRQHandler(void)
 {
     rt_interrupt_enter();
-    HAL_LTDC_IRQHandler(&hltdc); 
+    HAL_LTDC_IRQHandler(&hltdc);
     rt_interrupt_leave();
 }
 
@@ -171,11 +171,11 @@ static rt_err_t stm32_lcd_init(rt_device_t device)
     lcd.info.height         = LCD_HEIGHT;
     lcd.info.pixel_format   = RTGRAPHIC_PIXEL_FORMAT_ARGB888;
     lcd.info.bits_per_pixel = 32;
-    lcd.info.framebuffer    = (void *)rt_malloc_align(LCD_WIDTH * LCD_HEIGHT * (lcd.info.bits_per_pixel / 8), 32); 
+    lcd.info.framebuffer    = (void *)rt_malloc_align(LCD_WIDTH * LCD_HEIGHT * (lcd.info.bits_per_pixel / 8), 32);
     memset(lcd.info.framebuffer, 0, LCD_WIDTH * LCD_HEIGHT * (lcd.info.bits_per_pixel / 8));
     ltdc_init();
-    ltdc_layer_init(0, (uint32_t)lcd.info.framebuffer); 
-    
+    ltdc_layer_init(0, (uint32_t)lcd.info.framebuffer);
+
     return RT_EOK;
 }
 
@@ -186,12 +186,12 @@ static rt_err_t stm32_lcd_control(rt_device_t device, int cmd, void *args)
     case RTGRAPHIC_CTRL_RECT_UPDATE:
         break;
 
-    case RTGRAPHIC_CTRL_POWERON: 
-        stm32_mipi_display_on(); 
+    case RTGRAPHIC_CTRL_POWERON:
+        stm32_mipi_display_on();
         break;
 
-    case RTGRAPHIC_CTRL_POWEROFF: 
-        stm32_mipi_display_off(); 
+    case RTGRAPHIC_CTRL_POWEROFF:
+        stm32_mipi_display_off();
         break;
 
     case RTGRAPHIC_CTRL_GET_INFO:
@@ -210,9 +210,9 @@ static rt_err_t stm32_lcd_control(rt_device_t device, int cmd, void *args)
 
 int rt_hw_lcd_init(void)
 {
-    rt_err_t ret; 
-    
-    rt_memset(&lcd, 0x00, sizeof(lcd)); 
+    rt_err_t ret;
+
+    rt_memset(&lcd, 0x00, sizeof(lcd));
 
     lcd.parent.type    = RT_Device_Class_Graphic;
     lcd.parent.init    = stm32_lcd_init;
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_log.h b/bsp/stm32/libraries/HAL_Drivers/drv_log.h
index 7e0bfee5b4..3fe511789b 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_log.h
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_log.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_lptim.c b/bsp/stm32/libraries/HAL_Drivers/drv_lptim.c
index 25af1fb578..7986a247d0 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_lptim.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_lptim.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_lptim.h b/bsp/stm32/libraries/HAL_Drivers/drv_lptim.h
index 0fd51b5eac..b9fa2952ac 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_lptim.h
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_lptim.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_pm.c b/bsp/stm32/libraries/HAL_Drivers/drv_pm.c
index 8f3890474e..2c3b9276f0 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_pm.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_pm.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_pulse_encoder.c b/bsp/stm32/libraries/HAL_Drivers/drv_pulse_encoder.c
index 55e7bf45e1..d6f85f25eb 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_pulse_encoder.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_pulse_encoder.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_pwm.c b/bsp/stm32/libraries/HAL_Drivers/drv_pwm.c
index 1acd00a685..b24bb0e1de 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_pwm.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_pwm.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -285,9 +285,9 @@ static rt_err_t drv_pwm_set(TIM_HandleTypeDef *htim, struct rt_pwm_configuration
     rt_uint32_t pclk1_doubler, pclk2_doubler;
     /* Converts the channel number to the channel number of Hal library */
     rt_uint32_t channel = 0x04 * (configuration->channel - 1);
-    
+
     pclkx_doubler_get(&pclk1_doubler, &pclk2_doubler);
-    
+
 #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
     if (htim->Instance == TIM9 || htim->Instance == TIM10 || htim->Instance == TIM11)
 #elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32H7)
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_qspi.c b/bsp/stm32/libraries/HAL_Drivers/drv_qspi.c
index b3090ec6a1..91c380750b 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_qspi.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_qspi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -108,7 +108,7 @@ static int stm32_qspi_init(struct rt_qspi_device *device, struct rt_qspi_configu
     {
         __HAL_RCC_DMA2_CLK_ENABLE();
     }
-    
+
     HAL_DMA_DeInit(qspi_bus->QSPI_Handler.hdma);
     DMA_HandleTypeDef hdma_quadspi_config = QSPI_DMA_CONFIG;
     qspi_bus->hdma_quadspi = hdma_quadspi_config;
@@ -341,7 +341,7 @@ rt_err_t stm32_qspi_bus_attach_device(const char *bus_name, const char *device_n
     qspi_device->exit_qspi_mode = exit_qspi_mode;
     qspi_device->config.qspi_dl_width = data_line_width;
 
-    cs_pin->Pin = pin;
+    cs_pin->pin = pin;
 #ifdef BSP_QSPI_USING_SOFTCS
     rt_pin_mode(pin, PIN_MODE_OUTPUT);
     rt_pin_write(pin, 1);
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_qspi.h b/bsp/stm32/libraries/HAL_Drivers/drv_qspi.h
index 5f274d6cc6..fb48dd45b7 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_qspi.h
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_qspi.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-11-27     zylx         first version
  */
- 
+
 #ifndef __DRV_QSPI_H__
 #define __DRV_QSPI_H__
 
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_rtc.c b/bsp/stm32/libraries/HAL_Drivers/drv_rtc.c
index b0dcb8d114..88c96aa5b8 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_rtc.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_rtc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_sdio.c b/bsp/stm32/libraries/HAL_Drivers/drv_sdio.c
index 78928105cb..d7241e912b 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_sdio.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_sdio.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_sdio.h b/bsp/stm32/libraries/HAL_Drivers/drv_sdio.h
index 565a4bed00..920808f9d6 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_sdio.h
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_sdio.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_sdram.c b/bsp/stm32/libraries/HAL_Drivers/drv_sdram.c
index 97731ff3b1..ac309325ef 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_sdram.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_sdram.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -212,11 +212,11 @@ int sdram_test(void)
     for (i = 0; i < SDRAM_SIZE / data_width; i++)
     {
 #if SDRAM_DATA_WIDTH == 8
-        *(__IO uint8_t *)(SDRAM_BANK_ADDR + i * data_width) = (uint8_t)0x55;
+        *(__IO uint8_t *)(SDRAM_BANK_ADDR + i * data_width) = (uint8_t)(i % 100);
 #elif SDRAM_DATA_WIDTH == 16
-        *(__IO uint16_t *)(SDRAM_BANK_ADDR + i * data_width) = (uint16_t)0x5555;
+        *(__IO uint16_t *)(SDRAM_BANK_ADDR + i * data_width) = (uint16_t)(i % 1000);
 #else
-        *(__IO uint32_t *)(SDRAM_BANK_ADDR + i * data_width) = (uint32_t)0x55555555;
+        *(__IO uint32_t *)(SDRAM_BANK_ADDR + i * data_width) = (uint32_t)(i % 1000);
 #endif
     }
     time_cast = rt_tick_get() - start_time;
@@ -229,21 +229,21 @@ int sdram_test(void)
     {
 #if SDRAM_DATA_WIDTH == 8
         data = *(__IO uint8_t *)(SDRAM_BANK_ADDR + i * data_width);
-        if (data != 0x55)
+        if (data != i % 100)
         {
             LOG_E("SDRAM test failed!");
             break;
         }
 #elif SDRAM_DATA_WIDTH == 16
         data = *(__IO uint16_t *)(SDRAM_BANK_ADDR + i * data_width);
-        if (data != 0x5555)
+        if (data != i % 1000)
         {
             LOG_E("SDRAM test failed!");
             break;
         }
 #else
         data = *(__IO uint32_t *)(SDRAM_BANK_ADDR + i * data_width);
-        if (data != 0x55555555)
+        if (data != i % 1000)
         {
             LOG_E("SDRAM test failed!");
             break;
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_soft_i2c.c b/bsp/stm32/libraries/HAL_Drivers/drv_soft_i2c.c
index af89ae703a..871686650b 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_soft_i2c.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_soft_i2c.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -207,10 +207,10 @@ int rt_hw_i2c_init(void)
         result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c2_bus, soft_i2c_config[i].bus_name);
         RT_ASSERT(result == RT_EOK);
         stm32_i2c_bus_unlock(&soft_i2c_config[i]);
-        
+
         LOG_D("software simulation %s init done, pin scl: %d, pin sda %d",
-        soft_i2c_config[i].bus_name, 
-        soft_i2c_config[i].scl, 
+        soft_i2c_config[i].bus_name,
+        soft_i2c_config[i].scl,
         soft_i2c_config[i].sda);
     }
 
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_soft_i2c.h b/bsp/stm32/libraries/HAL_Drivers/drv_soft_i2c.h
index 31cba68f92..a9683e3e21 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_soft_i2c.h
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_soft_i2c.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -37,7 +37,7 @@ struct stm32_i2c
         .bus_name = "i2c1",                              \
     }
 #endif
-    
+
 #ifdef BSP_USING_I2C2
 #define I2C2_BUS_CONFIG                                  \
     {                                                    \
@@ -46,7 +46,7 @@ struct stm32_i2c
         .bus_name = "i2c2",                              \
     }
 #endif
-    
+
 #ifdef BSP_USING_I2C3
 #define I2C3_BUS_CONFIG                                  \
     {                                                    \
@@ -55,7 +55,7 @@ struct stm32_i2c
         .bus_name = "i2c3",                              \
     }
 #endif
-		
+
 #ifdef BSP_USING_I2C4
 #define I2C4_BUS_CONFIG                                  \
     {                                                    \
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_spi.c b/bsp/stm32/libraries/HAL_Drivers/drv_spi.c
index 3827f2efe8..a521e4bb83 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_spi.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_spi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -317,7 +317,7 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
         already_send_length = message->length - send_length - message_length;
         send_buf = (rt_uint8_t *)message->send_buf + already_send_length;
         recv_buf = (rt_uint8_t *)message->recv_buf + already_send_length;
-        
+
         /* start once data exchange in DMA mode */
         if (message->send_buf && message->recv_buf)
         {
@@ -447,8 +447,8 @@ static int rt_hw_spi_bus_init(void)
                 SET_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc);
                 /* Delay after an RCC peripheral clock enabling */
                 tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc);
-#elif defined(SOC_SERIES_STM32MP1) 
-                __HAL_RCC_DMAMUX_CLK_ENABLE(); 
+#elif defined(SOC_SERIES_STM32MP1)
+                __HAL_RCC_DMAMUX_CLK_ENABLE();
                 SET_BIT(RCC->MP_AHB2ENSETR, spi_config[i].dma_rx->dma_rcc);
                 tmpreg = READ_BIT(RCC->MP_AHB2ENSETR, spi_config[i].dma_rx->dma_rcc);
 #endif
@@ -490,7 +490,7 @@ static int rt_hw_spi_bus_init(void)
                 /* Delay after an RCC peripheral clock enabling */
                 tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc);
 #elif defined(SOC_SERIES_STM32MP1)
-                __HAL_RCC_DMAMUX_CLK_ENABLE(); 
+                __HAL_RCC_DMAMUX_CLK_ENABLE();
                 SET_BIT(RCC->MP_AHB2ENSETR, spi_config[i].dma_tx->dma_rcc);
                 tmpreg = READ_BIT(RCC->MP_AHB2ENSETR, spi_config[i].dma_tx->dma_rcc);
 #endif
@@ -900,23 +900,23 @@ static void stm32_get_dma_info(void)
 }
 
 #if defined(SOC_SERIES_STM32F0)
-void SPI1_DMA_RX_TX_IRQHandler(void) 
+void SPI1_DMA_RX_TX_IRQHandler(void)
 {
 #if defined(BSP_USING_SPI1) && defined(BSP_SPI1_TX_USING_DMA)
     SPI1_DMA_TX_IRQHandler();
 #endif
-    
+
 #if defined(BSP_USING_SPI1) && defined(BSP_SPI1_RX_USING_DMA)
     SPI1_DMA_RX_IRQHandler();
 #endif
 }
 
-void SPI2_DMA_RX_TX_IRQHandler(void) 
+void SPI2_DMA_RX_TX_IRQHandler(void)
 {
 #if defined(BSP_USING_SPI2) && defined(BSP_SPI2_TX_USING_DMA)
     SPI2_DMA_TX_IRQHandler();
 #endif
-    
+
 #if defined(BSP_USING_SPI2) && defined(BSP_SPI2_RX_USING_DMA)
     SPI2_DMA_RX_IRQHandler();
 #endif
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_spi.h b/bsp/stm32/libraries/HAL_Drivers/drv_spi.h
index b4567b8e83..f30d97f777 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_spi.h
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_spi.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -62,7 +62,7 @@ struct stm32_spi
         DMA_HandleTypeDef handle_rx;
         DMA_HandleTypeDef handle_tx;
     } dma;
-    
+
     rt_uint8_t spi_dma_flag;
     struct rt_spi_bus spi_bus;
 };
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_usart.c b/bsp/stm32/libraries/HAL_Drivers/drv_usart.c
index 1424a08ea1..df66aae72e 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_usart.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_usart.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -9,7 +9,7 @@
  * 2020-03-16     SummerGift   add device close feature
  * 2020-03-20     SummerGift   fix bug caused by ORE
  * 2020-05-02     whj4674672   support stm32h7 uart dma
- * 2020-09-09     forest-rain  support stm32wl uart 
+ * 2020-09-09     forest-rain  support stm32wl uart
  * 2020-10-14     Dozingfiretruck   Porting for stm32wbxx
  */
 
@@ -114,7 +114,10 @@ static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_c
     switch (cfg->data_bits)
     {
     case DATA_BITS_8:
-        uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
+        if (cfg->parity == PARITY_ODD || cfg->parity == PARITY_EVEN)
+            uart->handle.Init.WordLength = UART_WORDLENGTH_9B;
+        else
+            uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
         break;
     case DATA_BITS_9:
         uart->handle.Init.WordLength = UART_WORDLENGTH_9B;
@@ -213,7 +216,7 @@ static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *ar
     /* enable interrupt */
     case RT_DEVICE_CTRL_SET_INT:
         /* enable rx irq */
-        HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0); 
+        HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0);
         HAL_NVIC_EnableIRQ(uart->config->irq_type);
         /* enable interrupt */
         __HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_RXNE);
@@ -871,7 +874,7 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
     || defined(SOC_SERIES_STM32G4)|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32WB)
         /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
         SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
-        tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc); 
+        tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
 #elif defined(SOC_SERIES_STM32MP1)
         /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
         SET_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc);
@@ -880,7 +883,7 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
 
 #if (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)) && defined(DMAMUX1)
         /* enable DMAMUX clock for L4+ and G4 */
-        __HAL_RCC_DMAMUX1_CLK_ENABLE();   
+        __HAL_RCC_DMAMUX1_CLK_ENABLE();
 #elif defined(SOC_SERIES_STM32MP1)
         __HAL_RCC_DMAMUX_CLK_ENABLE();
 #endif
@@ -1029,7 +1032,7 @@ static void _dma_tx_complete(struct rt_serial_device *serial)
 /**
   * @brief  HAL_UART_TxCpltCallback
   * @param  huart: UART handle
-  * @note   This callback can be called by two functions, first in UART_EndTransmit_IT when 
+  * @note   This callback can be called by two functions, first in UART_EndTransmit_IT when
   *         UART Tx complete and second in UART_DMATransmitCplt function in DMA Circular mode.
   * @retval None
   */
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_usart.h b/bsp/stm32/libraries/HAL_Drivers/drv_usart.h
index 0150e824e9..360fcd54a4 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_usart.h
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_usart.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_usbd.c b/bsp/stm32/libraries/HAL_Drivers/drv_usbd.c
index 19e8d7f3d4..4f8f08fef3 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_usbd.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_usbd.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_usbh.c b/bsp/stm32/libraries/HAL_Drivers/drv_usbh.c
index 680a93e722..ad65accd07 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_usbh.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_usbh.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_usbh.h b/bsp/stm32/libraries/HAL_Drivers/drv_usbh.h
index e08f482f28..9ff24a2c6d 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_usbh.h
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_usbh.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_wdt.c b/bsp/stm32/libraries/HAL_Drivers/drv_wdt.c
index fe5d20c757..01319fb22b 100644
--- a/bsp/stm32/libraries/HAL_Drivers/drv_wdt.c
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_wdt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/libraries/STM32MPxx_HAL/SConscript b/bsp/stm32/libraries/STM32MPxx_HAL/SConscript
index a991e588d0..ce482829bd 100644
--- a/bsp/stm32/libraries/STM32MPxx_HAL/SConscript
+++ b/bsp/stm32/libraries/STM32MPxx_HAL/SConscript
@@ -119,6 +119,10 @@ if GetDepend(['BSP_USING_CRYP']):
     src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_cryp.c']
     src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_cryp_ex.c']
 
+if GetDepend(['BSP_USING_RTC']):
+    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rtc.c']
+    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rtc_ex.c']
+
 path = [cwd + '/STM32MP1xx_HAL_Driver/Inc',
     cwd + '/CMSIS/Device/ST/STM32MP1xx/Include',
     cwd + '/CMSIS/Core/Include',
diff --git a/bsp/stm32/libraries/STM32WBxx_HAL/SConscript b/bsp/stm32/libraries/STM32WBxx_HAL/SConscript
index e4fe5d3259..75372b529e 100644
--- a/bsp/stm32/libraries/STM32WBxx_HAL/SConscript
+++ b/bsp/stm32/libraries/STM32WBxx_HAL/SConscript
@@ -24,6 +24,7 @@ STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc.c
 STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rcc_ex.c
 STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_rng.c
 STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_gpio.c
+STM32WBxx_HAL_Driver/Src/stm32wbxx_hal_hsem.c
 ''')
   
 if GetDepend(['RT_USING_SERIAL']):
diff --git a/bsp/stm32/stm32f072-st-nucleo/applications/main.c b/bsp/stm32/stm32f072-st-nucleo/applications/main.c
index 81b03091e1..1d48ded64d 100644
--- a/bsp/stm32/stm32f072-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32f072-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED2_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED2_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f072-st-nucleo/board/board.c b/bsp/stm32/stm32f072-st-nucleo/board/board.c
index 8adbcd7bdd..5f06e3253d 100644
--- a/bsp/stm32/stm32f072-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32f072-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-12-21     zylx         first version
  */
- 
+
 #include "board.h"
 
 void SystemClock_Config(void)
@@ -16,7 +16,7 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48;
   RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
@@ -25,7 +25,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1;
diff --git a/bsp/stm32/stm32f072-st-nucleo/board/board.h b/bsp/stm32/stm32f072-st-nucleo/board/board.h
index bfd0371048..51a9f80edd 100644
--- a/bsp/stm32/stm32f072-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32f072-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f091-st-nucleo/applications/main.c b/bsp/stm32/stm32f091-st-nucleo/applications/main.c
index 421f897bc4..61981d49b0 100644
--- a/bsp/stm32/stm32f091-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32f091-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,19 +17,16 @@
 
 int main(void)
 {
-    int count = 1;
-
     /* set LED2 pin mode to output */
     rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED2_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED2_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-    return RT_EOK;
 }
 
 
diff --git a/bsp/stm32/stm32f091-st-nucleo/board/Kconfig b/bsp/stm32/stm32f091-st-nucleo/board/Kconfig
index 1a169a1aee..69c4d15d75 100644
--- a/bsp/stm32/stm32f091-st-nucleo/board/Kconfig
+++ b/bsp/stm32/stm32f091-st-nucleo/board/Kconfig
@@ -138,7 +138,6 @@ menu "On-chip Peripheral Drivers"
     menuconfig BSP_USING_ONCHIP_RTC
         bool "Enable RTC"
         select RT_USING_RTC
-        select RT_USING_LIBC
         default n
         if BSP_USING_ONCHIP_RTC
             choice
diff --git a/bsp/stm32/stm32f091-st-nucleo/board/board.c b/bsp/stm32/stm32f091-st-nucleo/board/board.c
index db5c101a9d..ec74fe9af0 100644
--- a/bsp/stm32/stm32f091-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32f091-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-12-21     zylx         first version
  */
- 
+
 #include "board.h"
 
 void SystemClock_Config(void)
@@ -16,11 +16,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  /**Configure LSE Drive Capability 
+  /**Configure LSE Drive Capability
   */
   HAL_PWR_EnableBkUpAccess();
   __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_HIGH);
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSI14
                               |RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_LSE;
@@ -38,7 +38,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1;
diff --git a/bsp/stm32/stm32f091-st-nucleo/board/board.h b/bsp/stm32/stm32f091-st-nucleo/board/board.h
index 7a78136471..a9ba91377d 100644
--- a/bsp/stm32/stm32f091-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32f091-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f091-st-nucleo/board/ports/fal_cfg.h b/bsp/stm32/stm32f091-st-nucleo/board/ports/fal_cfg.h
index 78bf24d251..b9964e0154 100644
--- a/bsp/stm32/stm32f091-st-nucleo/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32f091-st-nucleo/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-atk-nano/applications/main.c b/bsp/stm32/stm32f103-atk-nano/applications/main.c
index 6d75fd13ce..8569ce27bd 100644
--- a/bsp/stm32/stm32f103-atk-nano/applications/main.c
+++ b/bsp/stm32/stm32f103-atk-nano/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f103-atk-nano/board/Kconfig b/bsp/stm32/stm32f103-atk-nano/board/Kconfig
index 458d33ae0d..150a2a3119 100644
--- a/bsp/stm32/stm32f103-atk-nano/board/Kconfig
+++ b/bsp/stm32/stm32f103-atk-nano/board/Kconfig
@@ -183,7 +183,6 @@ menu "On-chip Peripheral Drivers"
     menuconfig BSP_USING_ONCHIP_RTC
         bool "Enable RTC"
         select RT_USING_RTC
-        select RT_USING_LIBC
         default n
         if BSP_USING_ONCHIP_RTC
             choice
diff --git a/bsp/stm32/stm32f103-atk-nano/board/board.c b/bsp/stm32/stm32f103-atk-nano/board/board.c
index bb35832bfa..de585efe32 100644
--- a/bsp/stm32/stm32f103-atk-nano/board/board.c
+++ b/bsp/stm32/stm32f103-atk-nano/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-11-06     balanceTWK   first version
  */
- 
+
 #include "board.h"
 
 void SystemClock_Config(void)
@@ -16,7 +16,7 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
                               |RCC_OSCILLATORTYPE_LSE;
@@ -32,7 +32,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f103-atk-nano/board/board.h b/bsp/stm32/stm32f103-atk-nano/board/board.h
index a33ef3cd5e..498459073e 100644
--- a/bsp/stm32/stm32f103-atk-nano/board/board.h
+++ b/bsp/stm32/stm32f103-atk-nano/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-atk-nano/board/ports/fal_cfg.h b/bsp/stm32/stm32f103-atk-nano/board/ports/fal_cfg.h
index 0ca9acb3ea..3eb4fd7c0d 100644
--- a/bsp/stm32/stm32f103-atk-nano/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32f103-atk-nano/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-atk-nano/board/ports/spi_flash_init.c b/bsp/stm32/stm32f103-atk-nano/board/ports/spi_flash_init.c
index 43f726525b..7892489436 100644
--- a/bsp/stm32/stm32f103-atk-nano/board/ports/spi_flash_init.c
+++ b/bsp/stm32/stm32f103-atk-nano/board/ports/spi_flash_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-atk-warshipv3/applications/main.c b/bsp/stm32/stm32f103-atk-warshipv3/applications/main.c
index 140fb13c73..8de9bd81e9 100644
--- a/bsp/stm32/stm32f103-atk-warshipv3/applications/main.c
+++ b/bsp/stm32/stm32f103-atk-warshipv3/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -19,13 +19,12 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
     /* set LED1 pin mode to output */
     rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_pin_write(LED1_PIN, PIN_HIGH);
@@ -34,6 +33,4 @@ int main(void)
         rt_pin_write(LED1_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/Kconfig b/bsp/stm32/stm32f103-atk-warshipv3/board/Kconfig
index d55f0f721b..2d7d944504 100644
--- a/bsp/stm32/stm32f103-atk-warshipv3/board/Kconfig
+++ b/bsp/stm32/stm32f103-atk-warshipv3/board/Kconfig
@@ -207,7 +207,6 @@ menu "On-chip Peripheral Drivers"
     menuconfig BSP_USING_ONCHIP_RTC
         bool "Enable RTC"
         select RT_USING_RTC
-        select RT_USING_LIBC
         default n
         if BSP_USING_ONCHIP_RTC
             choice
diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/board.c b/bsp/stm32/stm32f103-atk-warshipv3/board/board.c
index 17bfd29f27..2dc4c9cabf 100644
--- a/bsp/stm32/stm32f103-atk-warshipv3/board/board.c
+++ b/bsp/stm32/stm32f103-atk-warshipv3/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-11-06     SummerGift   first version
  */
- 
+
 #include "board.h"
 
 void SystemClock_Config(void)
@@ -15,7 +15,7 @@ void SystemClock_Config(void)
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -28,7 +28,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/board.h b/bsp/stm32/stm32f103-atk-warshipv3/board/board.h
index 68ac34f5f7..80c80984bf 100644
--- a/bsp/stm32/stm32f103-atk-warshipv3/board/board.h
+++ b/bsp/stm32/stm32f103-atk-warshipv3/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/ports/drv_sram.c b/bsp/stm32/stm32f103-atk-warshipv3/board/ports/drv_sram.c
index c0b077e600..420785bc9e 100644
--- a/bsp/stm32/stm32f103-atk-warshipv3/board/ports/drv_sram.c
+++ b/bsp/stm32/stm32f103-atk-warshipv3/board/ports/drv_sram.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/ports/include/sram_port.h b/bsp/stm32/stm32f103-atk-warshipv3/board/ports/include/sram_port.h
index 06ee47cca2..f51d21c6fa 100644
--- a/bsp/stm32/stm32f103-atk-warshipv3/board/ports/include/sram_port.h
+++ b/bsp/stm32/stm32f103-atk-warshipv3/board/ports/include/sram_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-atk-warshipv3/board/ports/sdcard_port.c b/bsp/stm32/stm32f103-atk-warshipv3/board/ports/sdcard_port.c
index a56e1bc35f..d56fb039d4 100644
--- a/bsp/stm32/stm32f103-atk-warshipv3/board/ports/sdcard_port.c
+++ b/bsp/stm32/stm32f103-atk-warshipv3/board/ports/sdcard_port.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-blue-pill/applications/main.c b/bsp/stm32/stm32f103-blue-pill/applications/main.c
index f1de7cf454..1fcf936a48 100644
--- a/bsp/stm32/stm32f103-blue-pill/applications/main.c
+++ b/bsp/stm32/stm32f103-blue-pill/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f103-blue-pill/board/Kconfig b/bsp/stm32/stm32f103-blue-pill/board/Kconfig
index 112696dbe8..aaf3c5825e 100644
--- a/bsp/stm32/stm32f103-blue-pill/board/Kconfig
+++ b/bsp/stm32/stm32f103-blue-pill/board/Kconfig
@@ -51,7 +51,6 @@ menu "On-chip Peripheral Drivers"
     menuconfig BSP_USING_ONCHIP_RTC
         bool "Enable RTC"
         select RT_USING_RTC
-        select RT_USING_LIBC
         default n
         if BSP_USING_ONCHIP_RTC
             choice
diff --git a/bsp/stm32/stm32f103-blue-pill/board/board.c b/bsp/stm32/stm32f103-blue-pill/board/board.c
index af6fb56470..22f1cc14f7 100644
--- a/bsp/stm32/stm32f103-blue-pill/board/board.c
+++ b/bsp/stm32/stm32f103-blue-pill/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2019-03-08     obito0   first version
  */
- 
+
 #include "board.h"
 
 void SystemClock_Config(void)
diff --git a/bsp/stm32/stm32f103-blue-pill/board/board.h b/bsp/stm32/stm32f103-blue-pill/board/board.h
index fc435ee029..1be364929a 100644
--- a/bsp/stm32/stm32f103-blue-pill/board/board.h
+++ b/bsp/stm32/stm32f103-blue-pill/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-dofly-M3S/applications/main.c b/bsp/stm32/stm32f103-dofly-M3S/applications/main.c
index 7b7f00c8ee..3101374062 100644
--- a/bsp/stm32/stm32f103-dofly-M3S/applications/main.c
+++ b/bsp/stm32/stm32f103-dofly-M3S/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -18,17 +18,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f103-dofly-M3S/applications/nrf24l01_init.c b/bsp/stm32/stm32f103-dofly-M3S/applications/nrf24l01_init.c
index 038725b78d..695510d1ac 100644
--- a/bsp/stm32/stm32f103-dofly-M3S/applications/nrf24l01_init.c
+++ b/bsp/stm32/stm32f103-dofly-M3S/applications/nrf24l01_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/board.c b/bsp/stm32/stm32f103-dofly-M3S/board/board.c
index 7b6a3ea947..d32a5096b6 100644
--- a/bsp/stm32/stm32f103-dofly-M3S/board/board.c
+++ b/bsp/stm32/stm32f103-dofly-M3S/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -8,7 +8,7 @@
  * 2018-11-06     SummerGift   first version
  * 2019-04-09     WillianChan  add stm32f103-dofly-M3S BSP
  */
- 
+
 #include "board.h"
 
 void SystemClock_Config(void)
@@ -16,7 +16,7 @@ void SystemClock_Config(void)
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -29,7 +29,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/board.h b/bsp/stm32/stm32f103-dofly-M3S/board/board.h
index 62f9030426..8662bff0f5 100644
--- a/bsp/stm32/stm32f103-dofly-M3S/board/board.h
+++ b/bsp/stm32/stm32f103-dofly-M3S/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/ports/drv_sdcard.c b/bsp/stm32/stm32f103-dofly-M3S/board/ports/drv_sdcard.c
index 5ffa50ba1d..13d235b694 100644
--- a/bsp/stm32/stm32f103-dofly-M3S/board/ports/drv_sdcard.c
+++ b/bsp/stm32/stm32f103-dofly-M3S/board/ports/drv_sdcard.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/ports/fal_cfg.h b/bsp/stm32/stm32f103-dofly-M3S/board/ports/fal_cfg.h
index 5f83366ea0..0f0183422a 100644
--- a/bsp/stm32/stm32f103-dofly-M3S/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32f103-dofly-M3S/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-dofly-M3S/board/ports/spi_flash_init.c b/bsp/stm32/stm32f103-dofly-M3S/board/ports/spi_flash_init.c
index 060c6d59b4..e22efac3c9 100644
--- a/bsp/stm32/stm32f103-dofly-M3S/board/ports/spi_flash_init.c
+++ b/bsp/stm32/stm32f103-dofly-M3S/board/ports/spi_flash_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-dofly-lyc8/applications/main.c b/bsp/stm32/stm32f103-dofly-lyc8/applications/main.c
index 18dbaac95c..ce702bb417 100644
--- a/bsp/stm32/stm32f103-dofly-lyc8/applications/main.c
+++ b/bsp/stm32/stm32f103-dofly-lyc8/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f103-dofly-lyc8/board/board.c b/bsp/stm32/stm32f103-dofly-lyc8/board/board.c
index 9f1ba0ddab..8493439409 100644
--- a/bsp/stm32/stm32f103-dofly-lyc8/board/board.c
+++ b/bsp/stm32/stm32f103-dofly-lyc8/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-11-06     SummerGift   first version
  */
- 
+
 #include "board.h"
 
 void SystemClock_Config(void)
@@ -15,7 +15,7 @@ void SystemClock_Config(void)
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -28,7 +28,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f103-dofly-lyc8/board/board.h b/bsp/stm32/stm32f103-dofly-lyc8/board/board.h
index ae6f2c67e8..8d8cc4643a 100644
--- a/bsp/stm32/stm32f103-dofly-lyc8/board/board.h
+++ b/bsp/stm32/stm32f103-dofly-lyc8/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-fire-arbitrary/applications/main.c b/bsp/stm32/stm32f103-fire-arbitrary/applications/main.c
index 5f0f0db8ed..e3078f4e82 100644
--- a/bsp/stm32/stm32f103-fire-arbitrary/applications/main.c
+++ b/bsp/stm32/stm32f103-fire-arbitrary/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-11-5      SummerGift   first version
  */
- 
+
 #include 
 #include 
 #include 
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig b/bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig
index ac8f8e0481..5ca802adca 100644
--- a/bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig
+++ b/bsp/stm32/stm32f103-fire-arbitrary/board/Kconfig
@@ -255,7 +255,6 @@ menu "On-chip Peripheral Drivers"
     menuconfig BSP_USING_ONCHIP_RTC
         bool "Enable RTC"
         select RT_USING_RTC
-        select RT_USING_LIBC
         default n
         if BSP_USING_ONCHIP_RTC
             choice
diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/board.c b/bsp/stm32/stm32f103-fire-arbitrary/board/board.c
index 080a22ff49..abbc74be30 100644
--- a/bsp/stm32/stm32f103-fire-arbitrary/board/board.c
+++ b/bsp/stm32/stm32f103-fire-arbitrary/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-11-06     balanceTWK   first version
  */
- 
+
 #include 
 #include "board.h"
 
@@ -17,7 +17,7 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
                               |RCC_OSCILLATORTYPE_LSE;
@@ -33,7 +33,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/board.h b/bsp/stm32/stm32f103-fire-arbitrary/board/board.h
index 968ac8e2e5..7aa3c0f703 100644
--- a/bsp/stm32/stm32f103-fire-arbitrary/board/board.h
+++ b/bsp/stm32/stm32f103-fire-arbitrary/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/fal_cfg.h b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/fal_cfg.h
index 5f83366ea0..0f0183422a 100644
--- a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/sdcard_port.c b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/sdcard_port.c
index bf5f3e10a7..55baa2c263 100644
--- a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/sdcard_port.c
+++ b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/sdcard_port.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/spi_flash_init.c b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/spi_flash_init.c
index 96b2034f24..519080ae05 100644
--- a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/spi_flash_init.c
+++ b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/spi_flash_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/w5500_device.c b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/w5500_device.c
index 68348d2bac..378d8f8274 100644
--- a/bsp/stm32/stm32f103-fire-arbitrary/board/ports/w5500_device.c
+++ b/bsp/stm32/stm32f103-fire-arbitrary/board/ports/w5500_device.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-gizwits-gokitv21/applications/main.c b/bsp/stm32/stm32f103-gizwits-gokitv21/applications/main.c
index 70f60f3f8b..a2ffe21b45 100644
--- a/bsp/stm32/stm32f103-gizwits-gokitv21/applications/main.c
+++ b/bsp/stm32/stm32f103-gizwits-gokitv21/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED4_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED4_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED4_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.c b/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.c
index 66a0c7f737..55faf0d89f 100644
--- a/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.c
+++ b/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-11-06     SummerGift   first version
  */
- 
+
 #include "board.h"
 
 /**
@@ -19,7 +19,7 @@ void SystemClock_Config(void)
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -32,7 +32,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.h b/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.h
index 7f0ae67d48..cdb13091cd 100644
--- a/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.h
+++ b/bsp/stm32/stm32f103-gizwits-gokitv21/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-hw100k-ibox/applications/main.c b/bsp/stm32/stm32f103-hw100k-ibox/applications/main.c
index d0ab2cc6ed..5ba5873b52 100644
--- a/bsp/stm32/stm32f103-hw100k-ibox/applications/main.c
+++ b/bsp/stm32/stm32f103-hw100k-ibox/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f103-hw100k-ibox/board/Kconfig b/bsp/stm32/stm32f103-hw100k-ibox/board/Kconfig
index 2b22439e25..3b38cbbc8e 100644
--- a/bsp/stm32/stm32f103-hw100k-ibox/board/Kconfig
+++ b/bsp/stm32/stm32f103-hw100k-ibox/board/Kconfig
@@ -198,7 +198,6 @@ menu "On-chip Peripheral Drivers"
     menuconfig BSP_USING_ONCHIP_RTC
         bool "Enable RTC"
         select RT_USING_RTC
-        select RT_USING_LIBC
         default n
         if BSP_USING_ONCHIP_RTC
             choice
diff --git a/bsp/stm32/stm32f103-hw100k-ibox/board/board.c b/bsp/stm32/stm32f103-hw100k-ibox/board/board.c
index 0598b6af0d..779d731980 100644
--- a/bsp/stm32/stm32f103-hw100k-ibox/board/board.c
+++ b/bsp/stm32/stm32f103-hw100k-ibox/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-11-06     SummerGift   first version
  */
- 
+
 #include "board.h"
 
 void SystemClock_Config(void)
@@ -16,7 +16,7 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
                               |RCC_OSCILLATORTYPE_LSE;
@@ -32,7 +32,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f103-hw100k-ibox/board/board.h b/bsp/stm32/stm32f103-hw100k-ibox/board/board.h
index fe3ea19e77..239f0afdd6 100644
--- a/bsp/stm32/stm32f103-hw100k-ibox/board/board.h
+++ b/bsp/stm32/stm32f103-hw100k-ibox/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/esp02_device.c b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/esp02_device.c
index 0de060a35a..f18b6318bb 100644
--- a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/esp02_device.c
+++ b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/esp02_device.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -21,6 +21,6 @@ int esp_02_device_init()
     rt_pin_write(ESP8266_CH_PD_Pin,PIN_HIGH) ;
     rt_pin_write(ESP8266_RST,PIN_HIGH) ;
 
-    return RT_EOK ;	
+    return RT_EOK ;
 }
 INIT_DEVICE_EXPORT(esp_02_device_init);
diff --git a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/fal_cfg.h b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/fal_cfg.h
index 5f83366ea0..0f0183422a 100644
--- a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/on_chip_flash_init.c b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/on_chip_flash_init.c
index be8978c63d..ae0660b29a 100644
--- a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/on_chip_flash_init.c
+++ b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/on_chip_flash_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/w5500_device.c b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/w5500_device.c
index a0174bbb0c..59d139a8ac 100644
--- a/bsp/stm32/stm32f103-hw100k-ibox/board/ports/w5500_device.c
+++ b/bsp/stm32/stm32f103-hw100k-ibox/board/ports/w5500_device.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-mini-system/.config b/bsp/stm32/stm32f103-mini-system/.config
deleted file mode 100644
index 7f2ef00287..0000000000
--- a/bsp/stm32/stm32f103-mini-system/.config
+++ /dev/null
@@ -1,341 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# RT-Thread Configuration
-#
-
-#
-# RT-Thread Kernel
-#
-CONFIG_RT_NAME_MAX=8
-# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
-# CONFIG_RT_USING_SMP is not set
-CONFIG_RT_ALIGN_SIZE=4
-# CONFIG_RT_THREAD_PRIORITY_8 is not set
-CONFIG_RT_THREAD_PRIORITY_32=y
-# CONFIG_RT_THREAD_PRIORITY_256 is not set
-CONFIG_RT_THREAD_PRIORITY_MAX=32
-CONFIG_RT_TICK_PER_SECOND=1000
-CONFIG_RT_USING_OVERFLOW_CHECK=y
-CONFIG_RT_USING_HOOK=y
-CONFIG_RT_USING_IDLE_HOOK=y
-CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
-CONFIG_IDLE_THREAD_STACK_SIZE=256
-# CONFIG_RT_USING_TIMER_SOFT is not set
-CONFIG_RT_DEBUG=y
-# CONFIG_RT_DEBUG_COLOR is not set
-# CONFIG_RT_DEBUG_INIT_CONFIG is not set
-# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
-# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
-# CONFIG_RT_DEBUG_IPC_CONFIG is not set
-# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
-# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
-# CONFIG_RT_DEBUG_MEM_CONFIG is not set
-# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
-# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
-# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
-
-#
-# Inter-Thread communication
-#
-CONFIG_RT_USING_SEMAPHORE=y
-CONFIG_RT_USING_MUTEX=y
-CONFIG_RT_USING_EVENT=y
-CONFIG_RT_USING_MAILBOX=y
-CONFIG_RT_USING_MESSAGEQUEUE=y
-# CONFIG_RT_USING_SIGNALS is not set
-
-#
-# Memory Management
-#
-CONFIG_RT_USING_MEMPOOL=y
-# CONFIG_RT_USING_MEMHEAP is not set
-# CONFIG_RT_USING_NOHEAP is not set
-CONFIG_RT_USING_SMALL_MEM=y
-# CONFIG_RT_USING_SLAB is not set
-# CONFIG_RT_USING_MEMTRACE is not set
-CONFIG_RT_USING_HEAP=y
-
-#
-# Kernel Device Object
-#
-CONFIG_RT_USING_DEVICE=y
-# CONFIG_RT_USING_DEVICE_OPS is not set
-# CONFIG_RT_USING_INTERRUPT_INFO is not set
-CONFIG_RT_USING_CONSOLE=y
-CONFIG_RT_CONSOLEBUF_SIZE=128
-CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
-CONFIG_RT_VER_NUM=0x40001
-CONFIG_ARCH_ARM=y
-CONFIG_ARCH_ARM_CORTEX_M=y
-CONFIG_ARCH_ARM_CORTEX_M3=y
-# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
-
-#
-# RT-Thread Components
-#
-CONFIG_RT_USING_COMPONENTS_INIT=y
-CONFIG_RT_USING_USER_MAIN=y
-CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
-CONFIG_RT_MAIN_THREAD_PRIORITY=10
-
-#
-# C++ features
-#
-# CONFIG_RT_USING_CPLUSPLUS is not set
-
-#
-# Command shell
-#
-CONFIG_RT_USING_FINSH=y
-CONFIG_FINSH_THREAD_NAME="tshell"
-CONFIG_FINSH_USING_HISTORY=y
-CONFIG_FINSH_HISTORY_LINES=5
-CONFIG_FINSH_USING_SYMTAB=y
-CONFIG_FINSH_USING_DESCRIPTION=y
-# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
-CONFIG_FINSH_THREAD_PRIORITY=20
-CONFIG_FINSH_THREAD_STACK_SIZE=4096
-CONFIG_FINSH_CMD_SIZE=80
-# CONFIG_FINSH_USING_AUTH is not set
-CONFIG_FINSH_USING_MSH=y
-CONFIG_FINSH_USING_MSH_DEFAULT=y
-CONFIG_FINSH_USING_MSH_ONLY=y
-CONFIG_FINSH_ARG_MAX=10
-
-#
-# Device virtual file system
-#
-# CONFIG_RT_USING_DFS is not set
-
-#
-# Device Drivers
-#
-CONFIG_RT_USING_DEVICE_IPC=y
-CONFIG_RT_PIPE_BUFSZ=512
-# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
-CONFIG_RT_USING_SERIAL=y
-CONFIG_RT_SERIAL_USING_DMA=y
-CONFIG_RT_SERIAL_RB_BUFSZ=64
-# CONFIG_RT_USING_CAN is not set
-# CONFIG_RT_USING_HWTIMER is not set
-# CONFIG_RT_USING_CPUTIME is not set
-# CONFIG_RT_USING_I2C is not set
-CONFIG_RT_USING_PIN=y
-# CONFIG_RT_USING_ADC is not set
-# CONFIG_RT_USING_PWM is not set
-# CONFIG_RT_USING_MTD_NOR is not set
-# CONFIG_RT_USING_MTD_NAND is not set
-# CONFIG_RT_USING_MTD is not set
-# CONFIG_RT_USING_PM is not set
-# CONFIG_RT_USING_RTC is not set
-# CONFIG_RT_USING_SDIO is not set
-# CONFIG_RT_USING_SPI is not set
-# CONFIG_RT_USING_WDT is not set
-# CONFIG_RT_USING_AUDIO is not set
-# CONFIG_RT_USING_SENSOR is not set
-
-#
-# Using WiFi
-#
-# CONFIG_RT_USING_WIFI is not set
-
-#
-# Using USB
-#
-# CONFIG_RT_USING_USB_HOST is not set
-# CONFIG_RT_USING_USB_DEVICE is not set
-
-#
-# POSIX layer and C standard library
-#
-# CONFIG_RT_USING_LIBC is not set
-# CONFIG_RT_USING_PTHREADS is not set
-
-#
-# Network
-#
-
-#
-# Socket abstraction layer
-#
-# CONFIG_RT_USING_SAL is not set
-
-#
-# light weight TCP/IP stack
-#
-# CONFIG_RT_USING_LWIP is not set
-
-#
-# Modbus master and slave stack
-#
-# CONFIG_RT_USING_MODBUS is not set
-
-#
-# AT commands
-#
-# CONFIG_RT_USING_AT is not set
-
-#
-# VBUS(Virtual Software BUS)
-#
-# CONFIG_RT_USING_VBUS is not set
-
-#
-# Utilities
-#
-# CONFIG_RT_USING_LOGTRACE is not set
-# CONFIG_RT_USING_RYM is not set
-# CONFIG_RT_USING_ULOG is not set
-# CONFIG_RT_USING_UTEST is not set
-# CONFIG_RT_USING_LWP is not set
-
-#
-# RT-Thread online packages
-#
-
-#
-# IoT - internet of things
-#
-# CONFIG_PKG_USING_PAHOMQTT is not set
-# CONFIG_PKG_USING_WEBCLIENT is not set
-# CONFIG_PKG_USING_MONGOOSE is not set
-# CONFIG_PKG_USING_WEBTERMINAL is not set
-# CONFIG_PKG_USING_CJSON is not set
-# CONFIG_PKG_USING_JSMN is not set
-# CONFIG_PKG_USING_LJSON is not set
-# CONFIG_PKG_USING_EZXML is not set
-# CONFIG_PKG_USING_NANOPB is not set
-
-#
-# Wi-Fi
-#
-
-#
-# Marvell WiFi
-#
-# CONFIG_PKG_USING_WLANMARVELL is not set
-
-#
-# Wiced WiFi
-#
-# CONFIG_PKG_USING_WLAN_WICED is not set
-# CONFIG_PKG_USING_COAP is not set
-# CONFIG_PKG_USING_NOPOLL is not set
-# CONFIG_PKG_USING_NETUTILS is not set
-# CONFIG_PKG_USING_AT_DEVICE is not set
-
-#
-# IoT Cloud
-#
-# CONFIG_PKG_USING_ONENET is not set
-# CONFIG_PKG_USING_GAGENT_CLOUD is not set
-# CONFIG_PKG_USING_ALI_IOTKIT is not set
-# CONFIG_PKG_USING_AZURE is not set
-
-#
-# security packages
-#
-# CONFIG_PKG_USING_MBEDTLS is not set
-# CONFIG_PKG_USING_libsodium is not set
-# CONFIG_PKG_USING_TINYCRYPT is not set
-
-#
-# language packages
-#
-# CONFIG_PKG_USING_LUA is not set
-# CONFIG_PKG_USING_JERRYSCRIPT is not set
-# CONFIG_PKG_USING_MICROPYTHON is not set
-
-#
-# multimedia packages
-#
-# CONFIG_PKG_USING_OPENMV is not set
-# CONFIG_PKG_USING_MUPDF is not set
-
-#
-# tools packages
-#
-# CONFIG_PKG_USING_CMBACKTRACE is not set
-# CONFIG_PKG_USING_EASYFLASH is not set
-# CONFIG_PKG_USING_EASYLOGGER is not set
-# CONFIG_PKG_USING_SYSTEMVIEW is not set
-
-#
-# system packages
-#
-# CONFIG_PKG_USING_GUIENGINE is not set
-# CONFIG_PKG_USING_CAIRO is not set
-# CONFIG_PKG_USING_PIXMAN is not set
-# CONFIG_PKG_USING_LWEXT4 is not set
-# CONFIG_PKG_USING_PARTITION is not set
-# CONFIG_PKG_USING_FAL is not set
-# CONFIG_PKG_USING_SQLITE is not set
-# CONFIG_PKG_USING_RTI is not set
-# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
-
-#
-# peripheral libraries and drivers
-#
-# CONFIG_PKG_USING_STM32F4_HAL is not set
-# CONFIG_PKG_USING_STM32F4_DRIVERS is not set
-# CONFIG_PKG_USING_REALTEK_AMEBA is not set
-# CONFIG_PKG_USING_SHT2X is not set
-# CONFIG_PKG_USING_AHT10 is not set
-# CONFIG_PKG_USING_AP3216C is not set
-# CONFIG_PKG_USING_STM32_SDIO is not set
-
-#
-# miscellaneous packages
-#
-# CONFIG_PKG_USING_LIBCSV is not set
-# CONFIG_PKG_USING_OPTPARSE is not set
-# CONFIG_PKG_USING_FASTLZ is not set
-# CONFIG_PKG_USING_MINILZO is not set
-# CONFIG_PKG_USING_QUICKLZ is not set
-# CONFIG_PKG_USING_MULTIBUTTON is not set
-# CONFIG_PKG_USING_CANFESTIVAL is not set
-# CONFIG_PKG_USING_ZLIB is not set
-# CONFIG_PKG_USING_DSTR is not set
-
-#
-# sample package
-#
-
-#
-# samples: kernel and components samples
-#
-# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
-# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
-# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
-# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
-
-#
-# example package: hello
-#
-# CONFIG_PKG_USING_HELLO is not set
-CONFIG_SOC_FAMILY_STM32=y
-CONFIG_SOC_SERIES_STM32F1=y
-
-#
-# Hardware Drivers Config
-#
-CONFIG_SOC_STM32F103C8=y
-
-#
-# Onboard Peripheral Drivers
-#
-CONFIG_BSP_USING_USB_TO_USART=y
-
-#
-# On-chip Peripheral Drivers
-#
-CONFIG_BSP_USING_GPIO=y
-CONFIG_BSP_USING_UART=y
-CONFIG_BSP_USING_UART1=y
-CONFIG_BSP_UART1_RX_USING_DMA=y
-# CONFIG_BSP_USING_SPI is not set
-# CONFIG_BSP_USING_ADC is not set
-
-#
-# Board extended module Drivers
-#
diff --git a/bsp/stm32/stm32f103-mini-system/README.md b/bsp/stm32/stm32f103-mini-system/README.md
deleted file mode 100644
index ee163c4beb..0000000000
--- a/bsp/stm32/stm32f103-mini-system/README.md
+++ /dev/null
@@ -1,110 +0,0 @@
-# STM32F103C8T6最小系统板 BSP 说明
-
-## 简介
-
-本文档为 STM32F103C8T6最小系统板 的 BSP (板级支持包) 说明。
-
-主要内容如下：
-
-- 开发板资源介绍
-- BSP 快速上手
-- 进阶使用方法
-
-通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
-
-## 开发板介绍
-
-STM32F103C8T6最小系统，采用SWD调试接口，可以用3个接口就能完成调试下载的任务，采用了官方建议的负载RTC晶振方案，小体积高频率的STM32实验板
-
-开发板外观如下图所示：
-
-![board](figures/board.png)
-
-该开发板常用 **板载资源** 如下：
-
-- MCU：STM32F103C8T6，主频 72MHz，64KB FLASH ，20KB RAM
-- 外部 RAM：无
-- 外部 FLASH：无
-- 常用外设
-  - LED：1个，DS0（黄色，PC13）
-- 常用接口：无
-- 调试接口，SWD调试接口
-
-开发板更多详细信息请参考[STM32F103C8T6最小系统板介绍]
-
-## 外设支持
-
-本 BSP 目前对外设的支持情况如下：
-
-| **板载外设**      | **支持情况** | **备注**                              |
-| :----------------- | :----------: | :------------------------------------- |
-| 	黄色LED		    |     支持      |       PC13                          |
-| **片上外设**      | **支持情况** | **备注**                              |
-| GPIO              |     支持     | PA0, PA1... PC15 ---> PIN: 0, 1...47 |
-| UART              |     支持     | UART1                                |
-| **扩展模块**      | **支持情况** | **备注**                              |
-|     		       |              |                                      |
-
-## 使用说明
-
-使用说明分为如下两个章节：
-
-- 快速上手
-
-    本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
-
-- 进阶使用
-
-    本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
-
-
-### 快速上手
-
-本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
-
-#### 硬件连接
-
-使用数据线连接开发板到 PC，打开电源开关。
-
-#### 编译下载
-
-双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
-
-> 工程默认配置使用 J-Link 仿真器下载程序，在通过 J-Link 连接开发板的基础上，点击下载按钮即可下载程序到开发板
-
-#### 运行结果
-
-下载程序成功之后，系统会自动运行，LED 闪烁
-
-连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
-
-```bash
- \ | /
-- RT -     Thread Operating System
- / | \     4.0.1 build Mar 10 2019
- 2006 - 2019 Copyright by rt-thread team
-msh >
-```
-### 进阶使用
-
-此 BSP 默认只开启了 GPIO 和 串口1 的功能，如果需使用 ADC、PWM等更多高级功能，再用 ENV 工具对BSP 进行配置，步骤如下：
-
-1. 在 bsp 下打开 env 工具。
-
-2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
-
-3. 输入`pkgs --update`命令更新软件包。
-
-4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。
-
-本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。
-
-## 注意事项
-
-- 只能用USB转TTL连接PC机 ;
-
-## 联系人信息
-
-维护人:
-
--  [obito0](https://github.com/obito0), 邮箱：<496420502@qq.com>
\ No newline at end of file
diff --git a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/.mxproject
deleted file mode 100644
index 934c2d572a..0000000000
--- a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/.mxproject
+++ /dev/null
@@ -1,14 +0,0 @@
-[PreviousGenFiles]
-HeaderPath=F:/rt-thread/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Inc
-HeaderFiles=stm32f1xx_it.h;stm32f1xx_hal_conf.h;main.h;
-SourcePath=F:/rt-thread/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Src
-SourceFiles=stm32f1xx_it.c;stm32f1xx_hal_msp.c;main.c;
-
-[PreviousLibFiles]
-LibFiles=Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;
-
-[PreviousUsedKeilFiles]
-SourceFiles=..\Src\main.c;..\Src\stm32f1xx_it.c;..\Src\stm32f1xx_hal_msp.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../\Src/system_stm32f1xx.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../\Src/system_stm32f1xx.c;../Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;null;
-HeaderPath=..\Drivers\STM32F1xx_HAL_Driver\Inc;..\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F1xx\Include;..\Drivers\CMSIS\Include;..\Inc;
-CDefines=USE_HAL_DRIVER;STM32F103xB;USE_HAL_DRIVER;STM32F103xB;
-
diff --git a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/CubeMX_Config.ioc
deleted file mode 100644
index 6dfacfbd4b..0000000000
--- a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/CubeMX_Config.ioc
+++ /dev/null
@@ -1,140 +0,0 @@
-#MicroXplorer Configuration settings - do not modify
-ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_1
-ADC1.IPParameters=Rank-0\#ChannelRegularConversion,master,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag
-ADC1.NbrOfConversionFlag=1
-ADC1.Rank-0\#ChannelRegularConversion=1
-ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5
-ADC1.master=1
-File.Version=6
-KeepUserPlacement=false
-Mcu.Family=STM32F1
-Mcu.IP0=ADC1
-Mcu.IP1=NVIC
-Mcu.IP2=RCC
-Mcu.IP3=SPI1
-Mcu.IP4=SYS
-Mcu.IP5=USART1
-Mcu.IPNb=6
-Mcu.Name=STM32F103C(8-B)Tx
-Mcu.Package=LQFP48
-Mcu.Pin0=PC14-OSC32_IN
-Mcu.Pin1=PC15-OSC32_OUT
-Mcu.Pin10=PA13
-Mcu.Pin11=PA14
-Mcu.Pin12=VP_SYS_VS_Systick
-Mcu.Pin2=PD0-OSC_IN
-Mcu.Pin3=PD1-OSC_OUT
-Mcu.Pin4=PA1
-Mcu.Pin5=PA5
-Mcu.Pin6=PA6
-Mcu.Pin7=PA7
-Mcu.Pin8=PA9
-Mcu.Pin9=PA10
-Mcu.PinsNb=13
-Mcu.ThirdPartyNb=0
-Mcu.UserConstants=
-Mcu.UserName=STM32F103C8Tx
-MxCube.Version=5.2.1
-MxDb.Version=DB.5.0.21
-NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
-NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
-NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-PA1.Signal=ADCx_IN1
-PA10.Mode=Asynchronous
-PA10.Signal=USART1_RX
-PA13.Mode=Serial_Wire
-PA13.Signal=SYS_JTMS-SWDIO
-PA14.Mode=Serial_Wire
-PA14.Signal=SYS_JTCK-SWCLK
-PA5.Mode=Full_Duplex_Master
-PA5.Signal=SPI1_SCK
-PA6.Mode=Full_Duplex_Master
-PA6.Signal=SPI1_MISO
-PA7.Mode=Full_Duplex_Master
-PA7.Signal=SPI1_MOSI
-PA9.Mode=Asynchronous
-PA9.Signal=USART1_TX
-PC14-OSC32_IN.Mode=LSE-External-Oscillator
-PC14-OSC32_IN.Signal=RCC_OSC32_IN
-PC15-OSC32_OUT.Mode=LSE-External-Oscillator
-PC15-OSC32_OUT.Signal=RCC_OSC32_OUT
-PCC.Checker=false
-PCC.Line=STM32F103
-PCC.MCU=STM32F103C(8-B)Tx
-PCC.PartNumber=STM32F103C8Tx
-PCC.Seq0=0
-PCC.Series=STM32F1
-PCC.Temperature=25
-PCC.Vdd=3.3
-PD0-OSC_IN.Mode=HSE-External-Oscillator
-PD0-OSC_IN.Signal=RCC_OSC_IN
-PD1-OSC_OUT.Mode=HSE-External-Oscillator
-PD1-OSC_OUT.Signal=RCC_OSC_OUT
-PinOutPanel.RotationAngle=0
-ProjectManager.AskForMigrate=true
-ProjectManager.BackupPrevious=false
-ProjectManager.CompilerOptimize=6
-ProjectManager.ComputerToolchain=false
-ProjectManager.CoupleFile=false
-ProjectManager.CustomerFirmwarePackage=
-ProjectManager.DefaultFWLocation=true
-ProjectManager.DeletePrevious=true
-ProjectManager.DeviceId=STM32F103C8Tx
-ProjectManager.FirmwarePackage=STM32Cube FW_F1 V1.7.0
-ProjectManager.FreePins=false
-ProjectManager.HalAssertFull=false
-ProjectManager.HeapSize=0x200
-ProjectManager.KeepUserCode=true
-ProjectManager.LastFirmware=true
-ProjectManager.LibraryCopy=0
-ProjectManager.MainLocation=Src
-ProjectManager.NoMain=false
-ProjectManager.PreviousToolchain=
-ProjectManager.ProjectBuild=false
-ProjectManager.ProjectFileName=CubeMX_Config.ioc
-ProjectManager.ProjectName=CubeMX_Config
-ProjectManager.StackSize=0x400
-ProjectManager.TargetToolchain=MDK-ARM V5
-ProjectManager.ToolChainLocation=
-ProjectManager.UnderRoot=false
-ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_ADC1_Init-ADC1-false-HAL-true,5-MX_SPI1_Init-SPI1-false-HAL-true
-RCC.ADCFreqValue=8000000
-RCC.AHBFreq_Value=16000000
-RCC.APB1CLKDivider=RCC_HCLK_DIV2
-RCC.APB1Freq_Value=8000000
-RCC.APB1TimFreq_Value=16000000
-RCC.APB2Freq_Value=16000000
-RCC.APB2TimFreq_Value=16000000
-RCC.FCLKCortexFreq_Value=16000000
-RCC.FamilyName=M
-RCC.HCLKFreq_Value=16000000
-RCC.IPParameters=ADCFreqValue,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLSourceVirtual,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,VCOOutput2Freq_Value
-RCC.MCOFreq_Value=16000000
-RCC.PLLCLKFreq_Value=16000000
-RCC.PLLMCOFreq_Value=8000000
-RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
-RCC.SYSCLKFreq_VALUE=16000000
-RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
-RCC.TimSysFreq_Value=16000000
-RCC.USBFreq_Value=16000000
-RCC.VCOOutput2Freq_Value=8000000
-SH.ADCx_IN1.0=ADC1_IN1,IN1
-SH.ADCx_IN1.ConfNb=1
-SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_8
-SPI1.CalculateBaudRate=2.0 MBits/s
-SPI1.Direction=SPI_DIRECTION_2LINES
-SPI1.IPParameters=VirtualType,Mode,Direction,BaudRatePrescaler,CalculateBaudRate
-SPI1.Mode=SPI_MODE_MASTER
-SPI1.VirtualType=VM_MASTER
-USART1.IPParameters=VirtualMode
-USART1.VirtualMode=VM_ASYNC
-VP_SYS_VS_Systick.Mode=SysTick
-VP_SYS_VS_Systick.Signal=SYS_VS_Systick
-board=custom
diff --git a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h b/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h
deleted file mode 100644
index 467a07d1ca..0000000000
--- a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h
+++ /dev/null
@@ -1,370 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_hal_conf.h
-  * @brief   HAL configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * 
© COPYRIGHT(c) 2019 STMicroelectronics

-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_CONF_H
-#define __STM32F1xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver 
-  */
-  
-#define HAL_MODULE_ENABLED  
-#define HAL_ADC_MODULE_ENABLED
-/*#define HAL_CRYP_MODULE_ENABLED   */
-/*#define HAL_CAN_MODULE_ENABLED   */
-/*#define HAL_CEC_MODULE_ENABLED   */
-/*#define HAL_CORTEX_MODULE_ENABLED   */
-/*#define HAL_CRC_MODULE_ENABLED   */
-/*#define HAL_DAC_MODULE_ENABLED   */
-/*#define HAL_DMA_MODULE_ENABLED   */
-/*#define HAL_ETH_MODULE_ENABLED   */
-/*#define HAL_FLASH_MODULE_ENABLED   */
-#define HAL_GPIO_MODULE_ENABLED
-/*#define HAL_I2C_MODULE_ENABLED   */
-/*#define HAL_I2S_MODULE_ENABLED   */
-/*#define HAL_IRDA_MODULE_ENABLED   */
-/*#define HAL_IWDG_MODULE_ENABLED   */
-/*#define HAL_NOR_MODULE_ENABLED   */
-/*#define HAL_NAND_MODULE_ENABLED   */
-/*#define HAL_PCCARD_MODULE_ENABLED   */
-/*#define HAL_PCD_MODULE_ENABLED   */
-/*#define HAL_HCD_MODULE_ENABLED   */
-/*#define HAL_PWR_MODULE_ENABLED   */
-/*#define HAL_RCC_MODULE_ENABLED   */
-/*#define HAL_RTC_MODULE_ENABLED   */
-/*#define HAL_SD_MODULE_ENABLED   */
-/*#define HAL_MMC_MODULE_ENABLED   */
-/*#define HAL_SDRAM_MODULE_ENABLED   */
-/*#define HAL_SMARTCARD_MODULE_ENABLED   */
-#define HAL_SPI_MODULE_ENABLED
-/*#define HAL_SRAM_MODULE_ENABLED   */
-/*#define HAL_TIM_MODULE_ENABLED   */
-#define HAL_UART_MODULE_ENABLED
-/*#define HAL_USART_MODULE_ENABLED   */
-/*#define HAL_WWDG_MODULE_ENABLED   */
-/*#define HAL_EXTI_MODULE_ENABLED   */
-
-#define HAL_CORTEX_MODULE_ENABLED
-#define HAL_DMA_MODULE_ENABLED
-#define HAL_FLASH_MODULE_ENABLED
-#define HAL_GPIO_MODULE_ENABLED
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-
-/* ########################## Oscillator Values adaptation ####################*/
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE) 
- #define LSI_VALUE               40000U    /*!< LSI Typical Value in Hz */
-#endif /* LSI_VALUE */                     /*!< Value of the Internal Low Speed oscillator in Hz
-                                                The real value may vary depending on the variations
-                                                in voltage and temperature. */
-
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  *        This value is used by the UART, RTC HAL module to compute the system frequency
-  */
-#if !defined  (LSE_VALUE)
-  #define LSE_VALUE    ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000)   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */     
-#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */           
-#define  TICK_INT_PRIORITY            ((uint32_t)0)    /*!< tick interrupt priority (lowest by default)  */            
-#define  USE_RTOS                     0
-#define  PREFETCH_ENABLE              1
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1U */
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2
-#define MAC_ADDR1   0
-#define MAC_ADDR2   0
-#define MAC_ADDR3   0
-#define MAC_ADDR4   0
-#define MAC_ADDR5   0
-
-/* Definition of the Ethernet driver buffers size and count */   
-#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    ((uint32_t)8)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    ((uint32_t)4)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848_PHY_ADDRESS Address*/ 
-#define DP83848_PHY_ADDRESS           0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
-#define PHY_RESET_DELAY                 ((uint32_t)0x000000FF)
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
-
-#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
-#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
- 
-#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
-  
-/* Section 4: Extended PHY Registers */
-#define PHY_SR                          ((uint16_t)0x10U)    /*!< PHY status register Offset                      */
-
-#define PHY_SPEED_STATUS                ((uint16_t)0x0002U)  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004U)  /*!< PHY Duplex mask                                 */
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file 
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
- #include "stm32f1xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
- #include "stm32f1xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
- #include "stm32f1xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-   
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f1xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-   
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f1xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */  
-   
-#ifdef HAL_CAN_MODULE_ENABLED
- #include "stm32f1xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
- #include "stm32f1xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
- #include "stm32f1xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
- #include "stm32f1xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
- #include "stm32f1xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
- #include "stm32f1xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
- #include "stm32f1xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
- #include "stm32f1xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
- #include "stm32f1xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f1xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f1xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f1xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f1xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f1xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
- #include "stm32f1xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */ 
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f1xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */  
-
-#ifdef HAL_MMC_MODULE_ENABLED
- #include "stm32f1xx_hal_mmc.h"
-#endif /* HAL_MMC_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
- #include "stm32f1xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */     
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f1xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f1xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f1xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f1xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f1xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f1xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f1xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f1xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f1xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */   
-   
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_CONF_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Inc/stm32f1xx_it.h b/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Inc/stm32f1xx_it.h
deleted file mode 100644
index 101d8aa728..0000000000
--- a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Inc/stm32f1xx_it.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/* USER CODE BEGIN Header */
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_it.h
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * 
© Copyright (c) 2019 STMicroelectronics.
-  * All rights reserved.

-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
- ******************************************************************************
-  */
-/* USER CODE END Header */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_IT_H
-#define __STM32F1xx_IT_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/* Private includes ----------------------------------------------------------*/
-/* USER CODE BEGIN Includes */
-
-/* USER CODE END Includes */
-
-/* Exported types ------------------------------------------------------------*/
-/* USER CODE BEGIN ET */
-
-/* USER CODE END ET */
-
-/* Exported constants --------------------------------------------------------*/
-/* USER CODE BEGIN EC */
-
-/* USER CODE END EC */
-
-/* Exported macro ------------------------------------------------------------*/
-/* USER CODE BEGIN EM */
-
-/* USER CODE END EM */
-
-/* Exported functions prototypes ---------------------------------------------*/
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-/* USER CODE BEGIN EFP */
-
-/* USER CODE END EFP */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_IT_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Src/main.c
deleted file mode 100644
index 0fb8a9747d..0000000000
--- a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Src/main.c
+++ /dev/null
@@ -1,325 +0,0 @@
-/* USER CODE BEGIN Header */
-/**
-  ******************************************************************************
-  * @file           : main.c
-  * @brief          : Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * 
© Copyright (c) 2019 STMicroelectronics.
-  * All rights reserved.

-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-/* USER CODE END Header */
-
-/* Includes ------------------------------------------------------------------*/
-#include "main.h"
-
-/* Private includes ----------------------------------------------------------*/
-/* USER CODE BEGIN Includes */
-
-/* USER CODE END Includes */
-
-/* Private typedef -----------------------------------------------------------*/
-/* USER CODE BEGIN PTD */
-
-/* USER CODE END PTD */
-
-/* Private define ------------------------------------------------------------*/
-/* USER CODE BEGIN PD */
-
-/* USER CODE END PD */
-
-/* Private macro -------------------------------------------------------------*/
-/* USER CODE BEGIN PM */
-
-/* USER CODE END PM */
-
-/* Private variables ---------------------------------------------------------*/
-ADC_HandleTypeDef hadc1;
-
-SPI_HandleTypeDef hspi1;
-
-UART_HandleTypeDef huart1;
-
-/* USER CODE BEGIN PV */
-
-/* USER CODE END PV */
-
-/* Private function prototypes -----------------------------------------------*/
-void SystemClock_Config(void);
-static void MX_GPIO_Init(void);
-static void MX_USART1_UART_Init(void);
-static void MX_ADC1_Init(void);
-static void MX_SPI1_Init(void);
-/* USER CODE BEGIN PFP */
-
-/* USER CODE END PFP */
-
-/* Private user code ---------------------------------------------------------*/
-/* USER CODE BEGIN 0 */
-
-/* USER CODE END 0 */
-
-/**
-  * @brief  The application entry point.
-  * @retval int
-  */
-int main(void)
-{
-  /* USER CODE BEGIN 1 */
-
-  /* USER CODE END 1 */
-  
-
-  /* MCU Configuration--------------------------------------------------------*/
-
-  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
-  HAL_Init();
-
-  /* USER CODE BEGIN Init */
-
-  /* USER CODE END Init */
-
-  /* Configure the system clock */
-  SystemClock_Config();
-
-  /* USER CODE BEGIN SysInit */
-
-  /* USER CODE END SysInit */
-
-  /* Initialize all configured peripherals */
-  MX_GPIO_Init();
-  MX_USART1_UART_Init();
-  MX_ADC1_Init();
-  MX_SPI1_Init();
-  /* USER CODE BEGIN 2 */
-
-  /* USER CODE END 2 */
-
-  /* Infinite loop */
-  /* USER CODE BEGIN WHILE */
-  while (1)
-  {
-    /* USER CODE END WHILE */
-
-    /* USER CODE BEGIN 3 */
-  }
-  /* USER CODE END 3 */
-}
-
-/**
-  * @brief System Clock Configuration
-  * @retval None
-  */
-void SystemClock_Config(void)
-{
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
-
-  /** Initializes the CPU, AHB and APB busses clocks 
-  */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
-  RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
-  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL2;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  /** Initializes the CPU, AHB and APB busses clocks 
-  */
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
-                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
-
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
-  PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV2;
-  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
-  {
-    Error_Handler();
-  }
-}
-
-/**
-  * @brief ADC1 Initialization Function
-  * @param None
-  * @retval None
-  */
-static void MX_ADC1_Init(void)
-{
-
-  /* USER CODE BEGIN ADC1_Init 0 */
-
-  /* USER CODE END ADC1_Init 0 */
-
-  ADC_ChannelConfTypeDef sConfig = {0};
-
-  /* USER CODE BEGIN ADC1_Init 1 */
-
-  /* USER CODE END ADC1_Init 1 */
-  /** Common config 
-  */
-  hadc1.Instance = ADC1;
-  hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
-  hadc1.Init.ContinuousConvMode = DISABLE;
-  hadc1.Init.DiscontinuousConvMode = DISABLE;
-  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
-  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
-  hadc1.Init.NbrOfConversion = 1;
-  if (HAL_ADC_Init(&hadc1) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  /** Configure Regular Channel 
-  */
-  sConfig.Channel = ADC_CHANNEL_1;
-  sConfig.Rank = ADC_REGULAR_RANK_1;
-  sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
-  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  /* USER CODE BEGIN ADC1_Init 2 */
-
-  /* USER CODE END ADC1_Init 2 */
-
-}
-
-/**
-  * @brief SPI1 Initialization Function
-  * @param None
-  * @retval None
-  */
-static void MX_SPI1_Init(void)
-{
-
-  /* USER CODE BEGIN SPI1_Init 0 */
-
-  /* USER CODE END SPI1_Init 0 */
-
-  /* USER CODE BEGIN SPI1_Init 1 */
-
-  /* USER CODE END SPI1_Init 1 */
-  /* SPI1 parameter configuration*/
-  hspi1.Instance = SPI1;
-  hspi1.Init.Mode = SPI_MODE_MASTER;
-  hspi1.Init.Direction = SPI_DIRECTION_2LINES;
-  hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
-  hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
-  hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
-  hspi1.Init.NSS = SPI_NSS_SOFT;
-  hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8;
-  hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
-  hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
-  hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
-  hspi1.Init.CRCPolynomial = 10;
-  if (HAL_SPI_Init(&hspi1) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  /* USER CODE BEGIN SPI1_Init 2 */
-
-  /* USER CODE END SPI1_Init 2 */
-
-}
-
-/**
-  * @brief USART1 Initialization Function
-  * @param None
-  * @retval None
-  */
-static void MX_USART1_UART_Init(void)
-{
-
-  /* USER CODE BEGIN USART1_Init 0 */
-
-  /* USER CODE END USART1_Init 0 */
-
-  /* USER CODE BEGIN USART1_Init 1 */
-
-  /* USER CODE END USART1_Init 1 */
-  huart1.Instance = USART1;
-  huart1.Init.BaudRate = 115200;
-  huart1.Init.WordLength = UART_WORDLENGTH_8B;
-  huart1.Init.StopBits = UART_STOPBITS_1;
-  huart1.Init.Parity = UART_PARITY_NONE;
-  huart1.Init.Mode = UART_MODE_TX_RX;
-  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
-  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
-  if (HAL_UART_Init(&huart1) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  /* USER CODE BEGIN USART1_Init 2 */
-
-  /* USER CODE END USART1_Init 2 */
-
-}
-
-/**
-  * @brief GPIO Initialization Function
-  * @param None
-  * @retval None
-  */
-static void MX_GPIO_Init(void)
-{
-
-  /* GPIO Ports Clock Enable */
-  __HAL_RCC_GPIOC_CLK_ENABLE();
-  __HAL_RCC_GPIOD_CLK_ENABLE();
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-
-}
-
-/* USER CODE BEGIN 4 */
-
-/* USER CODE END 4 */
-
-/**
-  * @brief  This function is executed in case of error occurrence.
-  * @retval None
-  */
-void Error_Handler(void)
-{
-  /* USER CODE BEGIN Error_Handler_Debug */
-  /* User can add his own implementation to report the HAL error return state */
-
-  /* USER CODE END Error_Handler_Debug */
-}
-
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t *file, uint32_t line)
-{ 
-  /* USER CODE BEGIN 6 */
-  /* User can add his own implementation to report the file name and line number,
-     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-  /* USER CODE END 6 */
-}
-#endif /* USE_FULL_ASSERT */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c b/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c
deleted file mode 100644
index 663b3021fa..0000000000
--- a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c
+++ /dev/null
@@ -1,286 +0,0 @@
-/* USER CODE BEGIN Header */
-/**
-  ******************************************************************************
-  * File Name          : stm32f1xx_hal_msp.c
-  * Description        : This file provides code for the MSP Initialization 
-  *                      and de-Initialization codes.
-  ******************************************************************************
-  * @attention
-  *
-  * 
© Copyright (c) 2019 STMicroelectronics.
-  * All rights reserved.

-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-/* USER CODE END Header */
-
-/* Includes ------------------------------------------------------------------*/
-#include "main.h"
-/* USER CODE BEGIN Includes */
-
-/* USER CODE END Includes */
-
-/* Private typedef -----------------------------------------------------------*/
-/* USER CODE BEGIN TD */
-
-/* USER CODE END TD */
-
-/* Private define ------------------------------------------------------------*/
-/* USER CODE BEGIN Define */
- 
-/* USER CODE END Define */
-
-/* Private macro -------------------------------------------------------------*/
-/* USER CODE BEGIN Macro */
-
-/* USER CODE END Macro */
-
-/* Private variables ---------------------------------------------------------*/
-/* USER CODE BEGIN PV */
-
-/* USER CODE END PV */
-
-/* Private function prototypes -----------------------------------------------*/
-/* USER CODE BEGIN PFP */
-
-/* USER CODE END PFP */
-
-/* External functions --------------------------------------------------------*/
-/* USER CODE BEGIN ExternalFunctions */
-
-/* USER CODE END ExternalFunctions */
-
-/* USER CODE BEGIN 0 */
-
-/* USER CODE END 0 */
-/**
-  * Initializes the Global MSP.
-  */
-void HAL_MspInit(void)
-{
-  /* USER CODE BEGIN MspInit 0 */
-
-  /* USER CODE END MspInit 0 */
-
-  __HAL_RCC_AFIO_CLK_ENABLE();
-  __HAL_RCC_PWR_CLK_ENABLE();
-
-  /* System interrupt init*/
-
-  /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled 
-  */
-  __HAL_AFIO_REMAP_SWJ_NOJTAG();
-
-  /* USER CODE BEGIN MspInit 1 */
-
-  /* USER CODE END MspInit 1 */
-}
-
-/**
-* @brief ADC MSP Initialization
-* This function configures the hardware resources used in this example
-* @param hadc: ADC handle pointer
-* @retval None
-*/
-void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
-{
-  GPIO_InitTypeDef GPIO_InitStruct = {0};
-  if(hadc->Instance==ADC1)
-  {
-  /* USER CODE BEGIN ADC1_MspInit 0 */
-
-  /* USER CODE END ADC1_MspInit 0 */
-    /* Peripheral clock enable */
-    __HAL_RCC_ADC1_CLK_ENABLE();
-  
-    __HAL_RCC_GPIOA_CLK_ENABLE();
-    /**ADC1 GPIO Configuration    
-    PA1     ------> ADC1_IN1 
-    */
-    GPIO_InitStruct.Pin = GPIO_PIN_1;
-    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
-    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  /* USER CODE BEGIN ADC1_MspInit 1 */
-
-  /* USER CODE END ADC1_MspInit 1 */
-  }
-
-}
-
-/**
-* @brief ADC MSP De-Initialization
-* This function freeze the hardware resources used in this example
-* @param hadc: ADC handle pointer
-* @retval None
-*/
-void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
-{
-  if(hadc->Instance==ADC1)
-  {
-  /* USER CODE BEGIN ADC1_MspDeInit 0 */
-
-  /* USER CODE END ADC1_MspDeInit 0 */
-    /* Peripheral clock disable */
-    __HAL_RCC_ADC1_CLK_DISABLE();
-  
-    /**ADC1 GPIO Configuration    
-    PA1     ------> ADC1_IN1 
-    */
-    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1);
-
-  /* USER CODE BEGIN ADC1_MspDeInit 1 */
-
-  /* USER CODE END ADC1_MspDeInit 1 */
-  }
-
-}
-
-/**
-* @brief SPI MSP Initialization
-* This function configures the hardware resources used in this example
-* @param hspi: SPI handle pointer
-* @retval None
-*/
-void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
-{
-  GPIO_InitTypeDef GPIO_InitStruct = {0};
-  if(hspi->Instance==SPI1)
-  {
-  /* USER CODE BEGIN SPI1_MspInit 0 */
-
-  /* USER CODE END SPI1_MspInit 0 */
-    /* Peripheral clock enable */
-    __HAL_RCC_SPI1_CLK_ENABLE();
-  
-    __HAL_RCC_GPIOA_CLK_ENABLE();
-    /**SPI1 GPIO Configuration    
-    PA5     ------> SPI1_SCK
-    PA6     ------> SPI1_MISO
-    PA7     ------> SPI1_MOSI 
-    */
-    GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_7;
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-    GPIO_InitStruct.Pin = GPIO_PIN_6;
-    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-    GPIO_InitStruct.Pull = GPIO_NOPULL;
-    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  /* USER CODE BEGIN SPI1_MspInit 1 */
-
-  /* USER CODE END SPI1_MspInit 1 */
-  }
-
-}
-
-/**
-* @brief SPI MSP De-Initialization
-* This function freeze the hardware resources used in this example
-* @param hspi: SPI handle pointer
-* @retval None
-*/
-void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
-{
-  if(hspi->Instance==SPI1)
-  {
-  /* USER CODE BEGIN SPI1_MspDeInit 0 */
-
-  /* USER CODE END SPI1_MspDeInit 0 */
-    /* Peripheral clock disable */
-    __HAL_RCC_SPI1_CLK_DISABLE();
-  
-    /**SPI1 GPIO Configuration    
-    PA5     ------> SPI1_SCK
-    PA6     ------> SPI1_MISO
-    PA7     ------> SPI1_MOSI 
-    */
-    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7);
-
-  /* USER CODE BEGIN SPI1_MspDeInit 1 */
-
-  /* USER CODE END SPI1_MspDeInit 1 */
-  }
-
-}
-
-/**
-* @brief UART MSP Initialization
-* This function configures the hardware resources used in this example
-* @param huart: UART handle pointer
-* @retval None
-*/
-void HAL_UART_MspInit(UART_HandleTypeDef* huart)
-{
-  GPIO_InitTypeDef GPIO_InitStruct = {0};
-  if(huart->Instance==USART1)
-  {
-  /* USER CODE BEGIN USART1_MspInit 0 */
-
-  /* USER CODE END USART1_MspInit 0 */
-    /* Peripheral clock enable */
-    __HAL_RCC_USART1_CLK_ENABLE();
-  
-    __HAL_RCC_GPIOA_CLK_ENABLE();
-    /**USART1 GPIO Configuration    
-    PA9     ------> USART1_TX
-    PA10     ------> USART1_RX 
-    */
-    GPIO_InitStruct.Pin = GPIO_PIN_9;
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-    GPIO_InitStruct.Pin = GPIO_PIN_10;
-    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-    GPIO_InitStruct.Pull = GPIO_NOPULL;
-    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  /* USER CODE BEGIN USART1_MspInit 1 */
-
-  /* USER CODE END USART1_MspInit 1 */
-  }
-
-}
-
-/**
-* @brief UART MSP De-Initialization
-* This function freeze the hardware resources used in this example
-* @param huart: UART handle pointer
-* @retval None
-*/
-void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
-{
-  if(huart->Instance==USART1)
-  {
-  /* USER CODE BEGIN USART1_MspDeInit 0 */
-
-  /* USER CODE END USART1_MspDeInit 0 */
-    /* Peripheral clock disable */
-    __HAL_RCC_USART1_CLK_DISABLE();
-  
-    /**USART1 GPIO Configuration    
-    PA9     ------> USART1_TX
-    PA10     ------> USART1_RX 
-    */
-    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10);
-
-  /* USER CODE BEGIN USART1_MspDeInit 1 */
-
-  /* USER CODE END USART1_MspDeInit 1 */
-  }
-
-}
-
-/* USER CODE BEGIN 1 */
-
-/* USER CODE END 1 */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Src/stm32f1xx_it.c b/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Src/stm32f1xx_it.c
deleted file mode 100644
index 6a95ce4bae..0000000000
--- a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Src/stm32f1xx_it.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/* USER CODE BEGIN Header */
-/**
-  ******************************************************************************
-  * @file    stm32f1xx_it.c
-  * @brief   Interrupt Service Routines.
-  ******************************************************************************
-  * @attention
-  *
-  * 
© Copyright (c) 2019 STMicroelectronics.
-  * All rights reserved.

-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-/* USER CODE END Header */
-
-/* Includes ------------------------------------------------------------------*/
-#include "main.h"
-#include "stm32f1xx_it.h"
-/* Private includes ----------------------------------------------------------*/
-/* USER CODE BEGIN Includes */
-/* USER CODE END Includes */
-
-/* Private typedef -----------------------------------------------------------*/
-/* USER CODE BEGIN TD */
-
-/* USER CODE END TD */
-
-/* Private define ------------------------------------------------------------*/
-/* USER CODE BEGIN PD */
- 
-/* USER CODE END PD */
-
-/* Private macro -------------------------------------------------------------*/
-/* USER CODE BEGIN PM */
-
-/* USER CODE END PM */
-
-/* Private variables ---------------------------------------------------------*/
-/* USER CODE BEGIN PV */
-
-/* USER CODE END PV */
-
-/* Private function prototypes -----------------------------------------------*/
-/* USER CODE BEGIN PFP */
-
-/* USER CODE END PFP */
-
-/* Private user code ---------------------------------------------------------*/
-/* USER CODE BEGIN 0 */
-
-/* USER CODE END 0 */
-
-/* External variables --------------------------------------------------------*/
-
-/* USER CODE BEGIN EV */
-
-/* USER CODE END EV */
-
-/******************************************************************************/
-/*           Cortex-M3 Processor Interruption and Exception Handlers          */ 
-/******************************************************************************/
-/**
-  * @brief This function handles Non maskable interrupt.
-  */
-void NMI_Handler(void)
-{
-  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
-
-  /* USER CODE END NonMaskableInt_IRQn 0 */
-  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
-
-  /* USER CODE END NonMaskableInt_IRQn 1 */
-}
-
-/**
-  * @brief This function handles Hard fault interrupt.
-  */
-void HardFault_Handler(void)
-{
-  /* USER CODE BEGIN HardFault_IRQn 0 */
-
-  /* USER CODE END HardFault_IRQn 0 */
-  while (1)
-  {
-    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
-    /* USER CODE END W1_HardFault_IRQn 0 */
-  }
-}
-
-/**
-  * @brief This function handles Memory management fault.
-  */
-void MemManage_Handler(void)
-{
-  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
-
-  /* USER CODE END MemoryManagement_IRQn 0 */
-  while (1)
-  {
-    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
-    /* USER CODE END W1_MemoryManagement_IRQn 0 */
-  }
-}
-
-/**
-  * @brief This function handles Prefetch fault, memory access fault.
-  */
-void BusFault_Handler(void)
-{
-  /* USER CODE BEGIN BusFault_IRQn 0 */
-
-  /* USER CODE END BusFault_IRQn 0 */
-  while (1)
-  {
-    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
-    /* USER CODE END W1_BusFault_IRQn 0 */
-  }
-}
-
-/**
-  * @brief This function handles Undefined instruction or illegal state.
-  */
-void UsageFault_Handler(void)
-{
-  /* USER CODE BEGIN UsageFault_IRQn 0 */
-
-  /* USER CODE END UsageFault_IRQn 0 */
-  while (1)
-  {
-    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
-    /* USER CODE END W1_UsageFault_IRQn 0 */
-  }
-}
-
-/**
-  * @brief This function handles System service call via SWI instruction.
-  */
-void SVC_Handler(void)
-{
-  /* USER CODE BEGIN SVCall_IRQn 0 */
-
-  /* USER CODE END SVCall_IRQn 0 */
-  /* USER CODE BEGIN SVCall_IRQn 1 */
-
-  /* USER CODE END SVCall_IRQn 1 */
-}
-
-/**
-  * @brief This function handles Debug monitor.
-  */
-void DebugMon_Handler(void)
-{
-  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
-
-  /* USER CODE END DebugMonitor_IRQn 0 */
-  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
-
-  /* USER CODE END DebugMonitor_IRQn 1 */
-}
-
-/**
-  * @brief This function handles Pendable request for system service.
-  */
-void PendSV_Handler(void)
-{
-  /* USER CODE BEGIN PendSV_IRQn 0 */
-
-  /* USER CODE END PendSV_IRQn 0 */
-  /* USER CODE BEGIN PendSV_IRQn 1 */
-
-  /* USER CODE END PendSV_IRQn 1 */
-}
-
-/**
-  * @brief This function handles System tick timer.
-  */
-void SysTick_Handler(void)
-{
-  /* USER CODE BEGIN SysTick_IRQn 0 */
-
-  /* USER CODE END SysTick_IRQn 0 */
-  HAL_IncTick();
-  /* USER CODE BEGIN SysTick_IRQn 1 */
-
-  /* USER CODE END SysTick_IRQn 1 */
-}
-
-/******************************************************************************/
-/* STM32F1xx Peripheral Interrupt Handlers                                    */
-/* Add here the Interrupt Handlers for the used peripherals.                  */
-/* For the available peripheral interrupt handler names,                      */
-/* please refer to the startup file (startup_stm32f1xx.s).                    */
-/******************************************************************************/
-
-/* USER CODE BEGIN 1 */
-
-/* USER CODE END 1 */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Src/system_stm32f1xx.c b/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Src/system_stm32f1xx.c
deleted file mode 100644
index af3759a3b6..0000000000
--- a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Src/system_stm32f1xx.c
+++ /dev/null
@@ -1,448 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f1xx.c
-  * @author  MCD Application Team
-  * @version V4.2.0
-  * @date    31-March-2017
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  * 
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      factors, AHB/APBx prescalers and Flash settings). 
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f1xx_xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
-  *    the product used), refer to "HSE_VALUE". 
-  *    When HSE is used as system clock source, directly or through PLL, and you
-  *    are using different crystal you have to adapt the HSE value to your own
-  *    configuration.
-  *        
-  ******************************************************************************
-  * @attention
-  *
-  * 
© COPYRIGHT(c) 2017 STMicroelectronics

-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f1xx_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F1xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f1xx.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F1xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F1xx_System_Private_Defines
-  * @{
-  */
-
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE               8000000U /*!< Default value of the External oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE               8000000U /*!< Default value of the Internal oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-/*!< Uncomment the following line if you need to use external SRAM  */ 
-#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
-/* #define DATA_IN_ExtSRAM */
-#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00000000U /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F1xx_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F1xx_System_Private_Variables
-  * @{
-  */
-
-/*******************************************************************************
-*  Clock Definitions
-*******************************************************************************/
-#if defined(STM32F100xB) ||defined(STM32F100xE)
-  uint32_t SystemCoreClock         = 24000000U;        /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
-  uint32_t SystemCoreClock         = 72000000U;        /*!< System Clock Frequency (Core Clock) */
-#endif
-
-const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8U] =  {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F1xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @note   This function should be used only after reset.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
-  /* Set HSION bit */
-  RCC->CR |= 0x00000001U;
-
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#if !defined(STM32F105xC) && !defined(STM32F107xC)
-  RCC->CFGR &= 0xF8FF0000U;
-#else
-  RCC->CFGR &= 0xF0FF0000U;
-#endif /* STM32F105xC */   
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= 0xFEF6FFFFU;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= 0xFFFBFFFFU;
-
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
-  RCC->CFGR &= 0xFF80FFFFU;
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-  /* Reset PLL2ON and PLL3ON bits */
-  RCC->CR &= 0xEBFFFFFFU;
-
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x00FF0000U;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000U;
-#elif defined(STM32F100xB) || defined(STM32F100xE)
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000U;
-
-  /* Reset CFGR2 register */
-  RCC->CFGR2 = 0x00000000U;      
-#else
-  /* Disable all interrupts and clear pending bits  */
-  RCC->CIR = 0x009F0000U;
-#endif /* STM32F105xC */
-    
-#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
-  #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl(); 
-  #endif /* DATA_IN_ExtSRAM */
-#endif 
-
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif 
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
-  *              8 MHz or 25 MHz, depending on the product used), user has to ensure
-  *              that HSE_VALUE is same as the real frequency of the crystal used.
-  *              Otherwise, this function may have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-  uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;
-#endif /* STM32F105xC */
-
-#if defined(STM32F100xB) || defined(STM32F100xE)
-  uint32_t prediv1factor = 0U;
-#endif /* STM32F100xB or STM32F100xE */
-    
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00U:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04U:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08U:  /* PLL used as system clock */
-
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      
-#if !defined(STM32F105xC) && !defined(STM32F107xC)      
-      pllmull = ( pllmull >> 18U) + 2U;
-      
-      if (pllsource == 0x00U)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
-      }
-      else
-      {
- #if defined(STM32F100xB) || defined(STM32F100xE)
-       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
-       /* HSE oscillator clock selected as PREDIV1 clock entry */
-       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
- #else
-        /* HSE selected as PLL clock entry */
-        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
-        {/* HSE oscillator clock divided by 2 */
-          SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
-        }
-        else
-        {
-          SystemCoreClock = HSE_VALUE * pllmull;
-        }
- #endif
-      }
-#else
-      pllmull = pllmull >> 18U;
-      
-      if (pllmull != 0x0DU)
-      {
-         pllmull += 2U;
-      }
-      else
-      { /* PLL multiplication factor = PLL input clock * 6.5 */
-        pllmull = 13U / 2U; 
-      }
-            
-      if (pllsource == 0x00U)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
-      }
-      else
-      {/* PREDIV1 selected as PLL clock entry */
-        
-        /* Get PREDIV1 clock source and division factor */
-        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
-        
-        if (prediv1source == 0U)
-        { 
-          /* HSE oscillator clock selected as PREDIV1 clock entry */
-          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
-        }
-        else
-        {/* PLL2 clock selected as PREDIV1 clock entry */
-          
-          /* Get PREDIV2 division factor and PLL2 multiplication factor */
-          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;
-          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U; 
-          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
-        }
-      }
-#endif /* STM32F105xC */ 
-      break;
-
-    default:
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
-/**
-  * @brief  Setup the external memory controller. Called in startup_stm32f1xx.s 
-  *          before jump to __main
-  * @param  None
-  * @retval None
-  */ 
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller. 
-  *         Called in startup_stm32f1xx_xx.s/.c before jump to main.
-  *         This function configures the external SRAM mounted on STM3210E-EVAL
-  *         board (STM32 High density devices). This SRAM will be used as program
-  *         data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */ 
-void SystemInit_ExtMemCtl(void) 
-{
-  __IO uint32_t tmpreg;
-  /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
-    required, then adjust the Register Addresses */
-
-  /* Enable FSMC clock */
-  RCC->AHBENR = 0x00000114U;
-
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
-  
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
-  RCC->APB2ENR = 0x000001E0U;
-  
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
-
-  (void)(tmpreg);
-  
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
-/*----------------  SRAM Address lines configuration -------------------------*/
-/*----------------  NOE and NWE configuration --------------------------------*/  
-/*----------------  NE3 configuration ----------------------------------------*/
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/
-  
-  GPIOD->CRL = 0x44BB44BBU;  
-  GPIOD->CRH = 0xBBBBBBBBU;
-
-  GPIOE->CRL = 0xB44444BBU;  
-  GPIOE->CRH = 0xBBBBBBBBU;
-
-  GPIOF->CRL = 0x44BBBBBBU;  
-  GPIOF->CRH = 0xBBBB4444U;
-
-  GPIOG->CRL = 0x44BBBBBBU;  
-  GPIOG->CRH = 0x444B4B44U;
-   
-/*----------------  FSMC Configuration ---------------------------------------*/  
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
-  
-  FSMC_Bank1->BTCR[4U] = 0x00001091U;
-  FSMC_Bank1->BTCR[5U] = 0x00110212U;
-}
-#endif /* DATA_IN_ExtSRAM */
-#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/stm32f103-mini-system/board/Kconfig b/bsp/stm32/stm32f103-mini-system/board/Kconfig
deleted file mode 100644
index fe4bec029d..0000000000
--- a/bsp/stm32/stm32f103-mini-system/board/Kconfig
+++ /dev/null
@@ -1,81 +0,0 @@
-menu "Hardware Drivers Config"
-
-config SOC_STM32F103C8
-    bool
-    select SOC_SERIES_STM32F1
-    select RT_USING_COMPONENTS_INIT
-    select RT_USING_USER_MAIN
-    default y
-
-menu "Onboard Peripheral Drivers"
-
-    config BSP_USING_USB_TO_USART
-        bool "Enable USB TO USART (uart1)"
-        select BSP_USING_UART
-        select BSP_USING_UART1
-        default y
-
-endmenu
-
-menu "On-chip Peripheral Drivers"
-
-    config BSP_USING_GPIO
-        bool "Enable GPIO"
-        select RT_USING_PIN
-        default y
-
-    menuconfig BSP_USING_UART
-        bool "Enable UART"
-        default y
-        select RT_USING_SERIAL
-        if BSP_USING_UART
-            config BSP_USING_UART1
-                bool "Enable UART1"
-                default y
-
-            config BSP_UART1_RX_USING_DMA
-                bool "Enable UART1 RX DMA"
-                depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
-                default n
-        endif
-
-    menuconfig BSP_USING_SPI
-        bool "Enable SPI BUS"
-        default n
-        select RT_USING_SPI
-        if BSP_USING_SPI
-            config BSP_USING_SPI1
-                bool "Enable SPI1 BUS"
-                default n
-
-            config BSP_SPI1_TX_USING_DMA
-                bool "Enable SPI1 TX DMA"
-                depends on BSP_USING_SPI1
-                default n
-                        
-            config BSP_SPI1_RX_USING_DMA
-                bool "Enable SPI1 RX DMA"
-                depends on BSP_USING_SPI1
-                select BSP_SPI1_TX_USING_DMA
-                default n
-        endif
-
-     menuconfig BSP_USING_ADC
-        bool "Enable ADC"
-        default n
-        select RT_USING_ADC
-        if BSP_USING_ADC
-            config BSP_USING_ADC1
-                bool "Enable ADC1"
-                default n
-
-        endif
-    source "../libraries/HAL_Drivers/Kconfig"
-    
-endmenu
-
-menu "Board extended module Drivers"
-
-endmenu
-
-endmenu
diff --git a/bsp/stm32/stm32f103-mini-system/board/SConscript b/bsp/stm32/stm32f103-mini-system/board/SConscript
deleted file mode 100644
index 713a0e4b8f..0000000000
--- a/bsp/stm32/stm32f103-mini-system/board/SConscript
+++ /dev/null
@@ -1,35 +0,0 @@
-import os
-import rtconfig
-from building import *
-
-Import('SDK_LIB')
-
-cwd = GetCurrentDir()
-
-# add general drivers
-src = Split('''
-board.c
-CubeMX_Config/Src/stm32f1xx_hal_msp.c
-''')
-
-path =  [cwd]
-path += [cwd + '/CubeMX_Config/Inc']
-
-startup_path_prefix = SDK_LIB
-
-if rtconfig.CROSS_TOOL == 'gcc':
-    src += [startup_path_prefix + '/STM32F1xx_HAL/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f103xb.s']
-elif rtconfig.CROSS_TOOL == 'keil':
-    src += [startup_path_prefix + '/STM32F1xx_HAL/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f103xb.s']
-elif rtconfig.CROSS_TOOL == 'iar':
-    src += [startup_path_prefix + '/STM32F1xx_HAL/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/startup_stm32f103xb.s']
-
-# STM32F100xB || STM32F100xE || STM32F101x6
-# STM32F101xB || STM32F101xE || STM32F101xG
-# STM32F102x6 || STM32F102xB || STM32F103x6
-# STM32F103xB || STM32F103xE || STM32F103xG
-# STM32F105xC || STM32F107xC)
-# You can select chips from the list above
-CPPDEFINES = ['STM32F103xB']
-group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
-Return('group')
diff --git a/bsp/stm32/stm32f103-mini-system/board/board.c b/bsp/stm32/stm32f103-mini-system/board/board.c
deleted file mode 100644
index b7ca2b8461..0000000000
--- a/bsp/stm32/stm32f103-mini-system/board/board.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2019-03-08     obito0   first version
- */
- 
-#include "board.h"
-
-void SystemClock_Config(void)
-{
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-
-  /** Initializes the CPU, AHB and APB busses clocks 
-  */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
-  RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
-  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  /** Initializes the CPU, AHB and APB busses clocks 
-  */
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
-                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
-
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
-  {
-    Error_Handler();
-  }
-}
diff --git a/bsp/stm32/stm32f103-mini-system/figures/board1.jpg b/bsp/stm32/stm32f103-mini-system/figures/board1.jpg
deleted file mode 100644
index 47c7221cf7..0000000000
Binary files a/bsp/stm32/stm32f103-mini-system/figures/board1.jpg and /dev/null differ
diff --git a/bsp/stm32/stm32f103-mini-system/figures/board2.jpg b/bsp/stm32/stm32f103-mini-system/figures/board2.jpg
deleted file mode 100644
index f14ba5689b..0000000000
Binary files a/bsp/stm32/stm32f103-mini-system/figures/board2.jpg and /dev/null differ
diff --git a/bsp/stm32/stm32f103-mini-system/figures/board3.jpg b/bsp/stm32/stm32f103-mini-system/figures/board3.jpg
deleted file mode 100644
index ac5bb43f74..0000000000
Binary files a/bsp/stm32/stm32f103-mini-system/figures/board3.jpg and /dev/null differ
diff --git a/bsp/stm32/stm32f103-onenet-nbiot/applications/main.c b/bsp/stm32/stm32f103-onenet-nbiot/applications/main.c
index 6d75fd13ce..8569ce27bd 100644
--- a/bsp/stm32/stm32f103-onenet-nbiot/applications/main.c
+++ b/bsp/stm32/stm32f103-onenet-nbiot/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f103-onenet-nbiot/board/board.c b/bsp/stm32/stm32f103-onenet-nbiot/board/board.c
index 258dd08e9d..5e045816b2 100644
--- a/bsp/stm32/stm32f103-onenet-nbiot/board/board.c
+++ b/bsp/stm32/stm32f103-onenet-nbiot/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-11-06     balanceTWK   first version
  */
- 
+
 #include "board.h"
 
 /**
@@ -16,32 +16,32 @@
   */
 void SystemClock_Config(void)
 {
-	RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-	RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-	/** Initializes the CPU, AHB and APB busses clocks 
-	*/
-	RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
-	RCC_OscInitStruct.HSIState = RCC_HSI_ON;
-	RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
-	RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
-	RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
-	RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16;
-	if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-	{
-		Error_Handler();
-	}
-	/** Initializes the CPU, AHB and APB busses clocks 
-	*/
-	RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
-							  |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
-	RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
-	RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-	RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
-	RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+    /** Initializes the CPU, AHB and APB busses clocks
+    */
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+    RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
+    RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+    {
+        Error_Handler();
+    }
+    /** Initializes the CPU, AHB and APB busses clocks
+    */
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+    RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 
-	if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
-	{
-		Error_Handler();
-	}
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+    {
+        Error_Handler();
+    }
 }
diff --git a/bsp/stm32/stm32f103-onenet-nbiot/board/board.h b/bsp/stm32/stm32f103-onenet-nbiot/board/board.h
index 070ccbbb45..162925a4f3 100644
--- a/bsp/stm32/stm32f103-onenet-nbiot/board/board.h
+++ b/bsp/stm32/stm32f103-onenet-nbiot/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f103-yf-ufun/applications/main.c b/bsp/stm32/stm32f103-yf-ufun/applications/main.c
index 737c362b23..8f9c5c7a07 100644
--- a/bsp/stm32/stm32f103-yf-ufun/applications/main.c
+++ b/bsp/stm32/stm32f103-yf-ufun/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED3_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED3_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED3_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f103-yf-ufun/board/board.c b/bsp/stm32/stm32f103-yf-ufun/board/board.c
index 4df20fbd48..5271b59c71 100644
--- a/bsp/stm32/stm32f103-yf-ufun/board/board.c
+++ b/bsp/stm32/stm32f103-yf-ufun/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-11-06     SummerGift   first version
  */
- 
+
 #include "board.h"
 
 void SystemClock_Config(void)
@@ -15,7 +15,7 @@ void SystemClock_Config(void)
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -28,7 +28,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f103-yf-ufun/board/board.h b/bsp/stm32/stm32f103-yf-ufun/board/board.h
index 8c0aa1d769..738f37080a 100644
--- a/bsp/stm32/stm32f103-yf-ufun/board/board.h
+++ b/bsp/stm32/stm32f103-yf-ufun/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f107-uc-eval/applications/main.c b/bsp/stm32/stm32f107-uc-eval/applications/main.c
index 11587e49d0..9f1a27444d 100644
--- a/bsp/stm32/stm32f107-uc-eval/applications/main.c
+++ b/bsp/stm32/stm32f107-uc-eval/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -18,17 +18,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED1 pin mode to output */
     rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED1_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED1_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f107-uc-eval/board/board.c b/bsp/stm32/stm32f107-uc-eval/board/board.c
index a63b070167..f053579c2f 100644
--- a/bsp/stm32/stm32f107-uc-eval/board/board.c
+++ b/bsp/stm32/stm32f107-uc-eval/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f107-uc-eval/board/board.h b/bsp/stm32/stm32f107-uc-eval/board/board.h
index 98df6d51ff..44a96208c6 100644
--- a/bsp/stm32/stm32f107-uc-eval/board/board.h
+++ b/bsp/stm32/stm32f107-uc-eval/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f401-st-nucleo/applications/main.c b/bsp/stm32/stm32f401-st-nucleo/applications/main.c
index 86c4508d12..d4200202ed 100644
--- a/bsp/stm32/stm32f401-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32f401-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f401-st-nucleo/board/board.c b/bsp/stm32/stm32f401-st-nucleo/board/board.c
index 942d080c5b..9c33cdbba5 100644
--- a/bsp/stm32/stm32f401-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32f401-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,11 +15,11 @@ void SystemClock_Config(void)
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
@@ -34,7 +34,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f401-st-nucleo/board/board.h b/bsp/stm32/stm32f401-st-nucleo/board/board.h
index 4c6f84d170..82647a83a4 100644
--- a/bsp/stm32/stm32f401-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32f401-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f405-smdz-breadfruit/applications/main.c b/bsp/stm32/stm32f405-smdz-breadfruit/applications/main.c
index 453681a90a..9f52445b11 100644
--- a/bsp/stm32/stm32f405-smdz-breadfruit/applications/main.c
+++ b/bsp/stm32/stm32f405-smdz-breadfruit/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f405-smdz-breadfruit/board/board.c b/bsp/stm32/stm32f405-smdz-breadfruit/board/board.c
index ef1f24cbb5..190ca080cf 100644
--- a/bsp/stm32/stm32f405-smdz-breadfruit/board/board.c
+++ b/bsp/stm32/stm32f405-smdz-breadfruit/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,11 +15,11 @@ void SystemClock_Config(void)
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-  /**Configure the main internal regulator output voltage 
+  /**Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -33,7 +33,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f405-smdz-breadfruit/board/board.h b/bsp/stm32/stm32f405-smdz-breadfruit/board/board.h
index 5b30f605d9..844f5e35e6 100644
--- a/bsp/stm32/stm32f405-smdz-breadfruit/board/board.h
+++ b/bsp/stm32/stm32f405-smdz-breadfruit/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f407-atk-explorer/applications/main.c b/bsp/stm32/stm32f407-atk-explorer/applications/main.c
index e3ae33205f..9fb7ebf153 100644
--- a/bsp/stm32/stm32f407-atk-explorer/applications/main.c
+++ b/bsp/stm32/stm32f407-atk-explorer/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -18,17 +18,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f407-atk-explorer/board/Kconfig b/bsp/stm32/stm32f407-atk-explorer/board/Kconfig
index 4811f373f0..84aa84e42c 100644
--- a/bsp/stm32/stm32f407-atk-explorer/board/Kconfig
+++ b/bsp/stm32/stm32f407-atk-explorer/board/Kconfig
@@ -286,7 +286,6 @@ menu "On-chip Peripheral Drivers"
     menuconfig BSP_USING_ONCHIP_RTC
         bool "Enable RTC"
         select RT_USING_RTC
-        select RT_USING_LIBC
         default n
         if BSP_USING_ONCHIP_RTC
             choice
diff --git a/bsp/stm32/stm32f407-atk-explorer/board/board.c b/bsp/stm32/stm32f407-atk-explorer/board/board.c
index c2c90a5e86..02a3a3d53f 100644
--- a/bsp/stm32/stm32f407-atk-explorer/board/board.c
+++ b/bsp/stm32/stm32f407-atk-explorer/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,11 +16,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
-  /**Configure the main internal regulator output voltage 
+  /**Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
                               |RCC_OSCILLATORTYPE_LSE;
@@ -37,7 +37,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f407-atk-explorer/board/board.h b/bsp/stm32/stm32f407-atk-explorer/board/board.h
index 70a4c0ed19..6d80e38f78 100644
--- a/bsp/stm32/stm32f407-atk-explorer/board/board.h
+++ b/bsp/stm32/stm32f407-atk-explorer/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f407-atk-explorer/board/ports/drv_sram.c b/bsp/stm32/stm32f407-atk-explorer/board/ports/drv_sram.c
index 2b60a6d2cc..dba9ec5e29 100644
--- a/bsp/stm32/stm32f407-atk-explorer/board/ports/drv_sram.c
+++ b/bsp/stm32/stm32f407-atk-explorer/board/ports/drv_sram.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -26,11 +26,11 @@ static struct rt_memheap system_heap;
 static SRAM_HandleTypeDef hsram;
 
 static int rt_hw_sram_init(void)
-{ 
+{
     int result = RT_EOK;
 
     FSMC_NORSRAM_TimingTypeDef Timing = {0};
-    
+
     /** Perform the SRAM2 memory initialization sequence
     */
     hsram.Instance = FSMC_NORSRAM_DEVICE;
@@ -57,7 +57,7 @@ static int rt_hw_sram_init(void)
     hsram.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE;
     hsram.Init.PageSize = FSMC_PAGE_SIZE_NONE;
 
-    
+
     /* Timing */
     Timing.AddressSetupTime = 0;
     Timing.AddressHoldTime = 0;
@@ -81,7 +81,7 @@ static int rt_hw_sram_init(void)
         rt_memheap_init(&system_heap, "sram", (void *)SRAM_BANK_ADDR, SRAM_SIZE);
 #endif
     }
-    
+
     return result;
 }
 INIT_BOARD_EXPORT(rt_hw_sram_init);
@@ -153,7 +153,7 @@ static int sram_test(void)
         LOG_D("SRAM test success!");
     }
 
-    return RT_EOK;  
+    return RT_EOK;
 }
 MSH_CMD_EXPORT(sram_test, sram test);
 #endif /* FINSH_USING_MSH */
diff --git a/bsp/stm32/stm32f407-atk-explorer/board/ports/fal_cfg.h b/bsp/stm32/stm32f407-atk-explorer/board/ports/fal_cfg.h
index a587e207ce..995136cd54 100644
--- a/bsp/stm32/stm32f407-atk-explorer/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32f407-atk-explorer/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f407-atk-explorer/board/ports/phy_reset.c b/bsp/stm32/stm32f407-atk-explorer/board/ports/phy_reset.c
index 838216ffaa..ec5c61f1b0 100644
--- a/bsp/stm32/stm32f407-atk-explorer/board/ports/phy_reset.c
+++ b/bsp/stm32/stm32f407-atk-explorer/board/ports/phy_reset.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f407-atk-explorer/board/ports/sdcard_port.c b/bsp/stm32/stm32f407-atk-explorer/board/ports/sdcard_port.c
index 0a9c36fd42..bc7e8b676e 100644
--- a/bsp/stm32/stm32f407-atk-explorer/board/ports/sdcard_port.c
+++ b/bsp/stm32/stm32f407-atk-explorer/board/ports/sdcard_port.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f407-atk-explorer/board/ports/spi_flash_init.c b/bsp/stm32/stm32f407-atk-explorer/board/ports/spi_flash_init.c
index 4705cc0112..b92344fa43 100644
--- a/bsp/stm32/stm32f407-atk-explorer/board/ports/spi_flash_init.c
+++ b/bsp/stm32/stm32f407-atk-explorer/board/ports/spi_flash_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f407-atk-explorer/board/ports/sram_port.h b/bsp/stm32/stm32f407-atk-explorer/board/ports/sram_port.h
index b40082267a..6238e611b1 100644
--- a/bsp/stm32/stm32f407-atk-explorer/board/ports/sram_port.h
+++ b/bsp/stm32/stm32f407-atk-explorer/board/ports/sram_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f407-st-discovery/applications/main.c b/bsp/stm32/stm32f407-st-discovery/applications/main.c
index c7ffc240cb..ecc3464e69 100644
--- a/bsp/stm32/stm32f407-st-discovery/applications/main.c
+++ b/bsp/stm32/stm32f407-st-discovery/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,11 +17,10 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
diff --git a/bsp/stm32/stm32f407-st-discovery/board/board.c b/bsp/stm32/stm32f407-st-discovery/board/board.c
index 8a3dbd9937..5fff5426fe 100644
--- a/bsp/stm32/stm32f407-st-discovery/board/board.c
+++ b/bsp/stm32/stm32f407-st-discovery/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,11 +15,11 @@ void SystemClock_Config(void)
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-  /**Configure the main internal regulator output voltage 
+  /**Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -33,7 +33,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f407-st-discovery/board/board.h b/bsp/stm32/stm32f407-st-discovery/board/board.h
index 7ba6c79dee..539e3abf45 100644
--- a/bsp/stm32/stm32f407-st-discovery/board/board.h
+++ b/bsp/stm32/stm32f407-st-discovery/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f410-st-nucleo/applications/main.c b/bsp/stm32/stm32f410-st-nucleo/applications/main.c
index 1305c03138..0de22d3ffd 100644
--- a/bsp/stm32/stm32f410-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32f410-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f410-st-nucleo/board/board.c b/bsp/stm32/stm32f410-st-nucleo/board/board.c
index dffc7ffba0..3e64df40d7 100644
--- a/bsp/stm32/stm32f410-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32f410-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,11 +15,11 @@ void SystemClock_Config(void)
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
@@ -35,7 +35,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f410-st-nucleo/board/board.h b/bsp/stm32/stm32f410-st-nucleo/board/board.h
index b9c9f8427f..72bd8a017c 100644
--- a/bsp/stm32/stm32f410-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32f410-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f411-atk-nano/applications/main.c b/bsp/stm32/stm32f411-atk-nano/applications/main.c
index 943b08cf15..351b59dc19 100644
--- a/bsp/stm32/stm32f411-atk-nano/applications/main.c
+++ b/bsp/stm32/stm32f411-atk-nano/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f411-atk-nano/board/Kconfig b/bsp/stm32/stm32f411-atk-nano/board/Kconfig
index e6418e12bd..805bfb0f2b 100644
--- a/bsp/stm32/stm32f411-atk-nano/board/Kconfig
+++ b/bsp/stm32/stm32f411-atk-nano/board/Kconfig
@@ -140,7 +140,6 @@ menu "On-chip Peripheral Drivers"
     menuconfig BSP_USING_ONCHIP_RTC
         bool "Enable RTC"
         select RT_USING_RTC
-        select RT_USING_LIBC
         default n
         if BSP_USING_ONCHIP_RTC
             choice
diff --git a/bsp/stm32/stm32f411-atk-nano/board/board.c b/bsp/stm32/stm32f411-atk-nano/board/board.c
index 2ca06e13bf..08158c2f96 100644
--- a/bsp/stm32/stm32f411-atk-nano/board/board.c
+++ b/bsp/stm32/stm32f411-atk-nano/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,11 +15,11 @@ void SystemClock_Config(void)
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-  /**Configure the main internal regulator output voltage 
+  /**Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
@@ -34,7 +34,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f411-atk-nano/board/board.h b/bsp/stm32/stm32f411-atk-nano/board/board.h
index 452aa7420c..2cbe75f5d9 100644
--- a/bsp/stm32/stm32f411-atk-nano/board/board.h
+++ b/bsp/stm32/stm32f411-atk-nano/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f411-atk-nano/board/ports/spi_flash_init.c b/bsp/stm32/stm32f411-atk-nano/board/ports/spi_flash_init.c
index 43f726525b..7892489436 100644
--- a/bsp/stm32/stm32f411-atk-nano/board/ports/spi_flash_init.c
+++ b/bsp/stm32/stm32f411-atk-nano/board/ports/spi_flash_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f411-st-nucleo/applications/main.c b/bsp/stm32/stm32f411-st-nucleo/applications/main.c
index b29630d930..9f36615507 100644
--- a/bsp/stm32/stm32f411-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32f411-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f411-st-nucleo/board/Kconfig b/bsp/stm32/stm32f411-st-nucleo/board/Kconfig
index 24e0e017db..5bdb69b4e6 100644
--- a/bsp/stm32/stm32f411-st-nucleo/board/Kconfig
+++ b/bsp/stm32/stm32f411-st-nucleo/board/Kconfig
@@ -111,7 +111,6 @@ menu "On-chip Peripheral Drivers"
     menuconfig BSP_USING_ONCHIP_RTC
         bool "Enable RTC"
         select RT_USING_RTC
-        select RT_USING_LIBC
         default n
         if BSP_USING_ONCHIP_RTC
             choice
diff --git a/bsp/stm32/stm32f411-st-nucleo/board/board.c b/bsp/stm32/stm32f411-st-nucleo/board/board.c
index e9e6ffb5e7..1d83386719 100644
--- a/bsp/stm32/stm32f411-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32f411-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,11 +16,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
-  /**Configure the main internal regulator output voltage 
+  /**Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
@@ -35,7 +35,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f411-st-nucleo/board/board.h b/bsp/stm32/stm32f411-st-nucleo/board/board.h
index e05c785128..062038ffdb 100644
--- a/bsp/stm32/stm32f411-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32f411-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f411-weact-MiniF4/applications/main.c b/bsp/stm32/stm32f411-weact-MiniF4/applications/main.c
index 729ae11bd6..f28cc62dd2 100644
--- a/bsp/stm32/stm32f411-weact-MiniF4/applications/main.c
+++ b/bsp/stm32/stm32f411-weact-MiniF4/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f411-weact-MiniF4/board/board.c b/bsp/stm32/stm32f411-weact-MiniF4/board/board.c
index a19a49af8e..7f27135a6b 100644
--- a/bsp/stm32/stm32f411-weact-MiniF4/board/board.c
+++ b/bsp/stm32/stm32f411-weact-MiniF4/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,11 +16,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -35,7 +35,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f411-weact-MiniF4/board/board.h b/bsp/stm32/stm32f411-weact-MiniF4/board/board.h
index e05c785128..062038ffdb 100644
--- a/bsp/stm32/stm32f411-weact-MiniF4/board/board.h
+++ b/bsp/stm32/stm32f411-weact-MiniF4/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f411-weact-MiniF4/board/ports/fal_cfg.h b/bsp/stm32/stm32f411-weact-MiniF4/board/ports/fal_cfg.h
index fe616d31cf..517d94f3ba 100644
--- a/bsp/stm32/stm32f411-weact-MiniF4/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32f411-weact-MiniF4/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f412-st-nucleo/applications/main.c b/bsp/stm32/stm32f412-st-nucleo/applications/main.c
index 317bc60514..3bc5104ea7 100644
--- a/bsp/stm32/stm32f412-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32f412-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f412-st-nucleo/board/board.c b/bsp/stm32/stm32f412-st-nucleo/board/board.c
index 504407b161..b8f8168dfa 100644
--- a/bsp/stm32/stm32f412-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32f412-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,11 +16,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
-  /**Configure the main internal regulator output voltage 
+  /**Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
@@ -35,7 +35,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f412-st-nucleo/board/board.h b/bsp/stm32/stm32f412-st-nucleo/board/board.h
index 3e2d7384c8..5c463d04e8 100644
--- a/bsp/stm32/stm32f412-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32f412-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f413-st-nucleo/applications/main.c b/bsp/stm32/stm32f413-st-nucleo/applications/main.c
index 18b64457a9..ddd672e739 100644
--- a/bsp/stm32/stm32f413-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32f413-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -23,16 +23,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED1 pin mode to output */
     rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED1_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED1_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f413-st-nucleo/board/Kconfig b/bsp/stm32/stm32f413-st-nucleo/board/Kconfig
index d4c25d6175..33e896d598 100644
--- a/bsp/stm32/stm32f413-st-nucleo/board/Kconfig
+++ b/bsp/stm32/stm32f413-st-nucleo/board/Kconfig
@@ -131,7 +131,6 @@ menu "On-chip Peripheral Drivers"
     menuconfig BSP_USING_ONCHIP_RTC
         bool "Enable RTC"
         select RT_USING_RTC
-        select RT_USING_LIBC
         default n
         if BSP_USING_ONCHIP_RTC
             choice
diff --git a/bsp/stm32/stm32f413-st-nucleo/board/board.c b/bsp/stm32/stm32f413-st-nucleo/board/board.c
index dffc5bba40..b36f973530 100644
--- a/bsp/stm32/stm32f413-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32f413-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,11 +20,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
@@ -40,7 +40,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f413-st-nucleo/board/board.h b/bsp/stm32/stm32f413-st-nucleo/board/board.h
index cd5e86661c..634003f596 100644
--- a/bsp/stm32/stm32f413-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32f413-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f427-robomaster-a/applications/main.c b/bsp/stm32/stm32f427-robomaster-a/applications/main.c
index 7c21823832..f63f29396c 100644
--- a/bsp/stm32/stm32f427-robomaster-a/applications/main.c
+++ b/bsp/stm32/stm32f427-robomaster-a/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f427-robomaster-a/board/board.c b/bsp/stm32/stm32f427-robomaster-a/board/board.c
index a0901feba9..780e089fcd 100644
--- a/bsp/stm32/stm32f427-robomaster-a/board/board.c
+++ b/bsp/stm32/stm32f427-robomaster-a/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -19,11 +19,11 @@ void SystemClock_Config(void)
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -37,13 +37,13 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Activate the Over-Drive mode 
+  /** Activate the Over-Drive mode
   */
   if (HAL_PWREx_EnableOverDrive() != HAL_OK)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f427-robomaster-a/board/board.h b/bsp/stm32/stm32f427-robomaster-a/board/board.h
index 4c74f95682..a0ea5ca4bd 100644
--- a/bsp/stm32/stm32f427-robomaster-a/board/board.h
+++ b/bsp/stm32/stm32f427-robomaster-a/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f427-robomaster-a/board/ports/sdcard_port.c b/bsp/stm32/stm32f427-robomaster-a/board/ports/sdcard_port.c
index b46537d311..6a79c83523 100644
--- a/bsp/stm32/stm32f427-robomaster-a/board/ports/sdcard_port.c
+++ b/bsp/stm32/stm32f427-robomaster-a/board/ports/sdcard_port.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-armfly-v6/applications/main.c b/bsp/stm32/stm32f429-armfly-v6/applications/main.c
index 70c2a3b0f7..152a11bab1 100644
--- a/bsp/stm32/stm32f429-armfly-v6/applications/main.c
+++ b/bsp/stm32/stm32f429-armfly-v6/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,20 +15,16 @@
 
 int main(void)
 {
-    int count = 1;
-
     HC574_SetPin(LED1,0);
-    HC574_SetPin(LED2,0);   
+    HC574_SetPin(LED2,0);
     HC574_SetPin(LED3,0);
     HC574_SetPin(LED4,0);
-    
-    while (count++)
+
+    while (1)
     {
         HC574_SetPin(LED1,1);
         rt_thread_mdelay(500);
         HC574_SetPin(LED1,0);
         rt_thread_mdelay(500);
     }
-    
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f429-armfly-v6/board/Kconfig b/bsp/stm32/stm32f429-armfly-v6/board/Kconfig
index 2b0c3eb34c..82d21c44b1 100644
--- a/bsp/stm32/stm32f429-armfly-v6/board/Kconfig
+++ b/bsp/stm32/stm32f429-armfly-v6/board/Kconfig
@@ -187,7 +187,6 @@ menu "On-chip Peripheral Drivers"
     menuconfig BSP_USING_ONCHIP_RTC
         bool "Enable RTC"
         select RT_USING_RTC
-        select RT_USING_LIBC
         default n
         if BSP_USING_ONCHIP_RTC
             choice
diff --git a/bsp/stm32/stm32f429-armfly-v6/board/board.c b/bsp/stm32/stm32f429-armfly-v6/board/board.c
index f314b7c45a..2d37e631e3 100644
--- a/bsp/stm32/stm32f429-armfly-v6/board/board.c
+++ b/bsp/stm32/stm32f429-armfly-v6/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,12 +17,12 @@ void SystemClock_Config(void)
     RCC_OscInitTypeDef RCC_OscInitStruct = {0};
     RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
     RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
-    
-    /**Configure the main internal regulator output voltage 
+
+    /**Configure the main internal regulator output voltage
     */
     __HAL_RCC_PWR_CLK_ENABLE();
     __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-    /**Initializes the CPU, AHB and APB busses clocks 
+    /**Initializes the CPU, AHB and APB busses clocks
     */
     RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
                                 |RCC_OSCILLATORTYPE_LSE;
@@ -39,13 +39,13 @@ void SystemClock_Config(void)
     {
       Error_Handler();
     }
-    /**Activate the Over-Drive mode 
+    /**Activate the Over-Drive mode
     */
     if (HAL_PWREx_EnableOverDrive() != HAL_OK)
     {
       Error_Handler();
     }
-    /**Initializes the CPU, AHB and APB busses clocks 
+    /**Initializes the CPU, AHB and APB busses clocks
     */
     RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                                 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
@@ -53,7 +53,7 @@ void SystemClock_Config(void)
     RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
     RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
     RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
-    
+
     if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
     {
       Error_Handler();
diff --git a/bsp/stm32/stm32f429-armfly-v6/board/board.h b/bsp/stm32/stm32f429-armfly-v6/board/board.h
index f0ea803bb0..c0d30df246 100644
--- a/bsp/stm32/stm32f429-armfly-v6/board/board.h
+++ b/bsp/stm32/stm32f429-armfly-v6/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-armfly-v6/board/ports/drv_ext_io.c b/bsp/stm32/stm32f429-armfly-v6/board/ports/drv_ext_io.c
index 44a4a622c5..89fa42af5f 100644
--- a/bsp/stm32/stm32f429-armfly-v6/board/ports/drv_ext_io.c
+++ b/bsp/stm32/stm32f429-armfly-v6/board/ports/drv_ext_io.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,84 +17,84 @@
 #include 
 
 #include "drv_ext_io.h"
-#define  HC574_PORT	 *(volatile rt_uint32_t *)0x64001000
+#define  HC574_PORT  *(volatile rt_uint32_t *)0x64001000
 
 volatile rt_uint32_t HC574_state = 0;
 
 void HC574_SetPin(rt_uint32_t _pin, uint8_t _value)
 {
-	if (_value == 0)
-	{
-		HC574_state &= (~_pin);
-	}
-	else
-	{
-		HC574_state |= _pin;
-	}
-    
-	HC574_PORT = HC574_state;
+    if (_value == 0)
+    {
+        HC574_state &= (~_pin);
+    }
+    else
+    {
+        HC574_state |= _pin;
+    }
+
+    HC574_PORT = HC574_state;
 }
 
 rt_uint8_t HC574_GetPin(rt_uint32_t _pin)
 {
-	if (HC574_state & _pin)
-	{
-		return 1;
-	}
-	else
-	{
-		return 0;
-	}
+    if (HC574_state & _pin)
+    {
+        return 1;
+    }
+    else
+    {
+        return 0;
+    }
 }
 
 static void HC574_Config_FMC(void)
 {
     FMC_NORSRAM_TimingTypeDef timing = {0};
     SRAM_HandleTypeDef sram2 = {0};
-    
-	/*
-		For LCD compatibilityselect 3-0-6-1-0-0
-		3-0-5-1-0-0  : RD high level 75nslow level 50ns. Read 8 channels of data into memory in 1us.
-		1-0-1-1-0-0  : RD high level 75nslow level 12nstrailing edge 12ns.
-	*/
-	/* FMC_Bank1_NORSRAM2 configuration */
-	timing.AddressSetupTime = 3;
-	timing.AddressHoldTime = 0;
-	timing.DataSetupTime = 6;
-	timing.BusTurnAroundDuration = 1;
-	timing.CLKDivision = 0;
-	timing.DataLatency = 0;
-	timing.AccessMode = FMC_ACCESS_MODE_A;
 
-	/*
-	 LCD configured as follow:
-	    - Data/Address MUX = Disable
-	    - Memory Type = SRAM
-	    - Data Width = 32bit
-	    - Write Operation = Enable
-	    - Extended Mode = Enable
-	    - Asynchronous Wait = Disable
-	*/
+    /*
+        For LCD compatibility，select 3-0-6-1-0-0
+        3-0-5-1-0-0  : RD high level 75ns，low level 50ns. Read 8 channels of data into memory in 1us.
+        1-0-1-1-0-0  : RD high level 75ns，low level 12ns，trailing edge 12ns.
+    */
+    /* FMC_Bank1_NORSRAM2 configuration */
+    timing.AddressSetupTime = 3;
+    timing.AddressHoldTime = 0;
+    timing.DataSetupTime = 6;
+    timing.BusTurnAroundDuration = 1;
+    timing.CLKDivision = 0;
+    timing.DataLatency = 0;
+    timing.AccessMode = FMC_ACCESS_MODE_A;
+
+    /*
+     LCD configured as follow:
+        - Data/Address MUX = Disable
+        - Memory Type = SRAM
+        - Data Width = 32bit
+        - Write Operation = Enable
+        - Extended Mode = Enable
+        - Asynchronous Wait = Disable
+    */
     sram2.Instance = FMC_NORSRAM_DEVICE;
     sram2.Extended = FMC_NORSRAM_EXTENDED_DEVICE;
 
-	sram2.Init.NSBank = FMC_NORSRAM_BANK2;
-	sram2.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
-	sram2.Init.MemoryType = FMC_MEMORY_TYPE_SRAM;
-	sram2.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_32;
-	sram2.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE;
-	sram2.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
-	sram2.Init.WrapMode = FMC_WRAP_MODE_DISABLE;
-	sram2.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
-	sram2.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
-	sram2.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
-	sram2.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
-	sram2.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
-	sram2.Init.WriteBurst = FMC_WRITE_BURST_DISABLE;
-	sram2.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY;
+    sram2.Init.NSBank = FMC_NORSRAM_BANK2;
+    sram2.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
+    sram2.Init.MemoryType = FMC_MEMORY_TYPE_SRAM;
+    sram2.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_32;
+    sram2.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE;
+    sram2.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
+    sram2.Init.WrapMode = FMC_WRAP_MODE_DISABLE;
+    sram2.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
+    sram2.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
+    sram2.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
+    sram2.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
+    sram2.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
+    sram2.Init.WriteBurst = FMC_WRITE_BURST_DISABLE;
+    sram2.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY;
     sram2.Init.PageSize = FMC_PAGE_SIZE_1024;
 
-	if (HAL_SRAM_Init(&sram2, &timing, NULL) != HAL_OK)
+    if (HAL_SRAM_Init(&sram2, &timing, NULL) != HAL_OK)
     {
         LOG_E("extend IO init failed!");
     }
@@ -106,12 +106,12 @@ static void HC574_Config_FMC(void)
 
 static int stm32_ext_io_init(void)
 {
-	HC574_Config_FMC();
-	/* Set the chip select to high level */
-	HC574_state = (NRF24L01_CE | VS1053_XDCS | LED1 | LED2 | LED3 | LED4 );
+    HC574_Config_FMC();
+    /* Set the chip select to high level */
+    HC574_state = (NRF24L01_CE | VS1053_XDCS | LED1 | LED2 | LED3 | LED4 );
     /* Change IO state */
-	HC574_PORT = HC574_state;
-    
+    HC574_PORT = HC574_state;
+
     return RT_EOK;
 }
 INIT_BOARD_EXPORT(stm32_ext_io_init);
diff --git a/bsp/stm32/stm32f429-armfly-v6/board/ports/drv_ext_io.h b/bsp/stm32/stm32f429-armfly-v6/board/ports/drv_ext_io.h
index 09740d3571..3f336dd7ab 100644
--- a/bsp/stm32/stm32f429-armfly-v6/board/ports/drv_ext_io.h
+++ b/bsp/stm32/stm32f429-armfly-v6/board/ports/drv_ext_io.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -13,64 +13,64 @@
 
 #include "rtthread.h"
 /*
-	armfly STM32-V6 Development board Extend IO
-	D0  - GPRS_RERM_ON
-	D1  - GPRS_RESET
-	D2  - NRF24L01_CE
-	D3  - NRF905_TX_EN
-	D4  - NRF905_TRX_CE/VS1053_XDCS
-	D5  - NRF905_PWR_UP
-	D6  - ESP8266_G0
-	D7  - ESP8266_G2
-	
-	D8  - LED1
-	D9  - LED2
-	D10 - LED3
-	D11 - LED4
-	D12 - TP_NRST
-	D13 - AD7606_OS0
-	D14 - AD7606_OS1
-	D15 - AD7606_OS2
-	
-	GPIO can output 5V 
-	D16  - Y50_0
-	D17  - Y50_1
-	D18  - Y50_2
-	D19  - Y50_3
-	D20  - Y50_4
-	D21  - Y50_5
-	D22  - Y50_6
-	D23  - Y50_7	
+    armfly STM32-V6 Development board Extend IO
+    D0  - GPRS_RERM_ON
+    D1  - GPRS_RESET
+    D2  - NRF24L01_CE
+    D3  - NRF905_TX_EN
+    D4  - NRF905_TRX_CE/VS1053_XDCS
+    D5  - NRF905_PWR_UP
+    D6  - ESP8266_G0
+    D7  - ESP8266_G2
 
-	GPIO can output 3.3V 
-	D24  - AD7606_RESET
-	D25  - AD7606_RAGE
-	D26  - Y33_2
-	D27  - Y33_3
-	D28  - Y33_4
-	D29  - Y33_5
-	D30  - Y33_6
-	D31  - Y33_7				
+    D8  - LED1
+    D9  - LED2
+    D10 - LED3
+    D11 - LED4
+    D12 - TP_NRST
+    D13 - AD7606_OS0
+    D14 - AD7606_OS1
+    D15 - AD7606_OS2
+
+    GPIO can output 5V
+    D16  - Y50_0
+    D17  - Y50_1
+    D18  - Y50_2
+    D19  - Y50_3
+    D20  - Y50_4
+    D21  - Y50_5
+    D22  - Y50_6
+    D23  - Y50_7
+
+    GPIO can output 3.3V
+    D24  - AD7606_RESET
+    D25  - AD7606_RAGE
+    D26  - Y33_2
+    D27  - Y33_3
+    D28  - Y33_4
+    D29  - Y33_5
+    D30  - Y33_6
+    D31  - Y33_7
 */
 
 #ifndef GPIO_Pin_0
-	#define GPIO_Pin_0                 ((uint16_t)0x0001)  /* Pin 0 selected */
-	#define GPIO_Pin_1                 ((uint16_t)0x0002)  /* Pin 1 selected */
-	#define GPIO_Pin_2                 ((uint16_t)0x0004)  /* Pin 2 selected */
-	#define GPIO_Pin_3                 ((uint16_t)0x0008)  /* Pin 3 selected */
-	#define GPIO_Pin_4                 ((uint16_t)0x0010)  /* Pin 4 selected */
-	#define GPIO_Pin_5                 ((uint16_t)0x0020)  /* Pin 5 selected */
-	#define GPIO_Pin_6                 ((uint16_t)0x0040)  /* Pin 6 selected */
-	#define GPIO_Pin_7                 ((uint16_t)0x0080)  /* Pin 7 selected */
-	#define GPIO_Pin_8                 ((uint16_t)0x0100)  /* Pin 8 selected */
-	#define GPIO_Pin_9                 ((uint16_t)0x0200)  /* Pin 9 selected */
-	#define GPIO_Pin_10                ((uint16_t)0x0400)  /* Pin 10 selected */
-	#define GPIO_Pin_11                ((uint16_t)0x0800)  /* Pin 11 selected */
-	#define GPIO_Pin_12                ((uint16_t)0x1000)  /* Pin 12 selected */
-	#define GPIO_Pin_13                ((uint16_t)0x2000)  /* Pin 13 selected */
-	#define GPIO_Pin_14                ((uint16_t)0x4000)  /* Pin 14 selected */
-	#define GPIO_Pin_15                ((uint16_t)0x8000)  /* Pin 15 selected */
-#endif	
+    #define GPIO_Pin_0                 ((uint16_t)0x0001)  /* Pin 0 selected */
+    #define GPIO_Pin_1                 ((uint16_t)0x0002)  /* Pin 1 selected */
+    #define GPIO_Pin_2                 ((uint16_t)0x0004)  /* Pin 2 selected */
+    #define GPIO_Pin_3                 ((uint16_t)0x0008)  /* Pin 3 selected */
+    #define GPIO_Pin_4                 ((uint16_t)0x0010)  /* Pin 4 selected */
+    #define GPIO_Pin_5                 ((uint16_t)0x0020)  /* Pin 5 selected */
+    #define GPIO_Pin_6                 ((uint16_t)0x0040)  /* Pin 6 selected */
+    #define GPIO_Pin_7                 ((uint16_t)0x0080)  /* Pin 7 selected */
+    #define GPIO_Pin_8                 ((uint16_t)0x0100)  /* Pin 8 selected */
+    #define GPIO_Pin_9                 ((uint16_t)0x0200)  /* Pin 9 selected */
+    #define GPIO_Pin_10                ((uint16_t)0x0400)  /* Pin 10 selected */
+    #define GPIO_Pin_11                ((uint16_t)0x0800)  /* Pin 11 selected */
+    #define GPIO_Pin_12                ((uint16_t)0x1000)  /* Pin 12 selected */
+    #define GPIO_Pin_13                ((uint16_t)0x2000)  /* Pin 13 selected */
+    #define GPIO_Pin_14                ((uint16_t)0x4000)  /* Pin 14 selected */
+    #define GPIO_Pin_15                ((uint16_t)0x8000)  /* Pin 15 selected */
+#endif
 
 #define GPIO_Pin_16                 ((uint32_t)0x00010000)  /* Pin 0 selected */
 #define GPIO_Pin_17                 ((uint32_t)0x00020000)  /* Pin 1 selected */
@@ -90,42 +90,42 @@
 #define GPIO_Pin_31                 ((uint32_t)0x80000000)  /* Pin 15 selected */
 
 /* Rename the macro for the sake of memory */
-#define	GPRS_TERM_ON   GPIO_Pin_0
-#define	GPRS_RESET     GPIO_Pin_1
-#define	NRF24L01_CE    GPIO_Pin_2
-#define	NRF905_TX_EN   GPIO_Pin_3
-#define	NRF905_TRX_CE  GPIO_Pin_4
+#define GPRS_TERM_ON   GPIO_Pin_0
+#define GPRS_RESET     GPIO_Pin_1
+#define NRF24L01_CE    GPIO_Pin_2
+#define NRF905_TX_EN   GPIO_Pin_3
+#define NRF905_TRX_CE  GPIO_Pin_4
   #define VS1053_XDCS    GPIO_Pin_4
-#define	NRF905_PWR_UP  GPIO_Pin_5
-#define	ESP8266_G0     GPIO_Pin_6
-#define	ESP8266_G2     GPIO_Pin_7
-	
-#define	LED1           GPIO_Pin_8
-#define	LED2           GPIO_Pin_9
-#define	LED3           GPIO_Pin_10
-#define	LED4           GPIO_Pin_11
-#define	TP_NRST        GPIO_Pin_12
-#define	AD7606_OS0     GPIO_Pin_13
-#define	AD7606_OS1     GPIO_Pin_14
-#define	AD7606_OS2     GPIO_Pin_15
-	
-#define	Y50_0          GPIO_Pin_16
-#define	Y50_1          GPIO_Pin_17
-#define	Y50_2          GPIO_Pin_18
-#define	Y50_3          GPIO_Pin_19
-#define	Y50_4          GPIO_Pin_20
-#define	Y50_5          GPIO_Pin_21
-#define	Y50_6          GPIO_Pin_22
-#define	Y50_7          GPIO_Pin_23	
+#define NRF905_PWR_UP  GPIO_Pin_5
+#define ESP8266_G0     GPIO_Pin_6
+#define ESP8266_G2     GPIO_Pin_7
 
-#define	AD7606_RESET   GPIO_Pin_24
-#define	AD7606_RANGE   GPIO_Pin_25
-#define	Y33_2          GPIO_Pin_26
-#define	Y33_3          GPIO_Pin_27
-#define	Y33_4          GPIO_Pin_28
-#define	Y33_5          GPIO_Pin_29
-#define	Y33_6          GPIO_Pin_30
-#define	Y33_7          GPIO_Pin_31
+#define LED1           GPIO_Pin_8
+#define LED2           GPIO_Pin_9
+#define LED3           GPIO_Pin_10
+#define LED4           GPIO_Pin_11
+#define TP_NRST        GPIO_Pin_12
+#define AD7606_OS0     GPIO_Pin_13
+#define AD7606_OS1     GPIO_Pin_14
+#define AD7606_OS2     GPIO_Pin_15
+
+#define Y50_0          GPIO_Pin_16
+#define Y50_1          GPIO_Pin_17
+#define Y50_2          GPIO_Pin_18
+#define Y50_3          GPIO_Pin_19
+#define Y50_4          GPIO_Pin_20
+#define Y50_5          GPIO_Pin_21
+#define Y50_6          GPIO_Pin_22
+#define Y50_7          GPIO_Pin_23
+
+#define AD7606_RESET   GPIO_Pin_24
+#define AD7606_RANGE   GPIO_Pin_25
+#define Y33_2          GPIO_Pin_26
+#define Y33_3          GPIO_Pin_27
+#define Y33_4          GPIO_Pin_28
+#define Y33_5          GPIO_Pin_29
+#define Y33_6          GPIO_Pin_30
+#define Y33_7          GPIO_Pin_31
 
 void HC574_SetPin(rt_uint32_t _pin, uint8_t _value);
 rt_uint8_t HC574_GetPin(rt_uint32_t _pin);
diff --git a/bsp/stm32/stm32f429-armfly-v6/board/ports/fal_cfg.h b/bsp/stm32/stm32f429-armfly-v6/board/ports/fal_cfg.h
index a587e207ce..995136cd54 100644
--- a/bsp/stm32/stm32f429-armfly-v6/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32f429-armfly-v6/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-armfly-v6/board/ports/lcd_port.h b/bsp/stm32/stm32f429-armfly-v6/board/ports/lcd_port.h
index 31e2b9a392..0fda729291 100644
--- a/bsp/stm32/stm32f429-armfly-v6/board/ports/lcd_port.h
+++ b/bsp/stm32/stm32f429-armfly-v6/board/ports/lcd_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-armfly-v6/board/ports/phy_reset.c b/bsp/stm32/stm32f429-armfly-v6/board/ports/phy_reset.c
index 36296b486a..6d97b5a979 100644
--- a/bsp/stm32/stm32f429-armfly-v6/board/ports/phy_reset.c
+++ b/bsp/stm32/stm32f429-armfly-v6/board/ports/phy_reset.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-armfly-v6/board/ports/sdcard_port.c b/bsp/stm32/stm32f429-armfly-v6/board/ports/sdcard_port.c
index b46537d311..6a79c83523 100644
--- a/bsp/stm32/stm32f429-armfly-v6/board/ports/sdcard_port.c
+++ b/bsp/stm32/stm32f429-armfly-v6/board/ports/sdcard_port.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-armfly-v6/board/ports/sdram_port.h b/bsp/stm32/stm32f429-armfly-v6/board/ports/sdram_port.h
index 1e57acb19f..9b5a363b6f 100644
--- a/bsp/stm32/stm32f429-armfly-v6/board/ports/sdram_port.h
+++ b/bsp/stm32/stm32f429-armfly-v6/board/ports/sdram_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-armfly-v6/board/ports/spi_flash_init.c b/bsp/stm32/stm32f429-armfly-v6/board/ports/spi_flash_init.c
index 526835b59a..ac58f66259 100644
--- a/bsp/stm32/stm32f429-armfly-v6/board/ports/spi_flash_init.c
+++ b/bsp/stm32/stm32f429-armfly-v6/board/ports/spi_flash_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -22,7 +22,7 @@ static int rt_hw_spi_flash_init(void)
     if (RT_NULL == rt_sfud_flash_probe("W25Q64", "spi30"))
     {
         return -RT_ERROR;
-    };
+    }
 
     return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f429-atk-apollo/applications/main.c b/bsp/stm32/stm32f429-atk-apollo/applications/main.c
index 487ddf44f6..609b4e63b4 100644
--- a/bsp/stm32/stm32f429-atk-apollo/applications/main.c
+++ b/bsp/stm32/stm32f429-atk-apollo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f429-atk-apollo/board/Kconfig b/bsp/stm32/stm32f429-atk-apollo/board/Kconfig
index 1d693397c1..b444252787 100644
--- a/bsp/stm32/stm32f429-atk-apollo/board/Kconfig
+++ b/bsp/stm32/stm32f429-atk-apollo/board/Kconfig
@@ -250,7 +250,6 @@ menu "On-chip Peripheral Drivers"
     menuconfig BSP_USING_ONCHIP_RTC
         bool "Enable RTC"
         select RT_USING_RTC
-        select RT_USING_LIBC
         default n
         if BSP_USING_ONCHIP_RTC
             choice
diff --git a/bsp/stm32/stm32f429-atk-apollo/board/board.c b/bsp/stm32/stm32f429-atk-apollo/board/board.c
index c13619f753..36d2ff17d3 100644
--- a/bsp/stm32/stm32f429-atk-apollo/board/board.c
+++ b/bsp/stm32/stm32f429-atk-apollo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -18,11 +18,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
-  /**Configure the main internal regulator output voltage 
+  /**Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
                               |RCC_OSCILLATORTYPE_LSE;
@@ -39,13 +39,13 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Activate the Over-Drive mode 
+  /**Activate the Over-Drive mode
   */
   if (HAL_PWREx_EnableOverDrive() != HAL_OK)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f429-atk-apollo/board/board.h b/bsp/stm32/stm32f429-atk-apollo/board/board.h
index 9173f50c46..077b0af713 100644
--- a/bsp/stm32/stm32f429-atk-apollo/board/board.h
+++ b/bsp/stm32/stm32f429-atk-apollo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.c b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.c
index ce1021fb60..889c5b0dee 100644
--- a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.c
+++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -86,7 +86,7 @@ void SAIB_config_set(struct rt_audio_configure config)
     SAIB_samplerate_set(config.samplerate);
     SAIB_samplebits_set(config.samplebits);
 }
-		
+
 static void SAIB_config_init()
 {
     _sai_b.hsai.Instance = SAI1_Block_B;
diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.h b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.h
index 8aeede498c..0cc55f7aa9 100644
--- a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.h
+++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_mic.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -8,10 +8,10 @@
  * 2019-07-28     Ernest         the first version
  */
 
-#ifndef __DRV_MIC_H_ 
-#define __DRV_MIC_H_ 
+#ifndef __DRV_MIC_H_
+#define __DRV_MIC_H_
 
-#include  
+#include 
 #include 
 
 #endif
diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.c b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.c
index 4a51ef6347..f564cc1b84 100644
--- a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.c
+++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,7 +16,7 @@
 #define DBG_LVL              DBG_INFO
 #include 
 
-#define	CODEC_I2C_NAME  ("i2c1")
+#define CODEC_I2C_NAME  ("i2c1")
 
 #define TX_DMA_FIFO_SIZE (2048)
 
@@ -49,7 +49,7 @@ void SAIA_samplerate_set(rt_uint32_t freq)
 {
     RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
     int i;
-    
+
     /* check frequence */
     for (i = 0; i < (sizeof(SAI_PSC_TBL) / sizeof(SAI_PSC_TBL[0])); i++)
     {
@@ -60,12 +60,12 @@ void SAIA_samplerate_set(rt_uint32_t freq)
         LOG_E("Can not support this frequence: %d.", freq);
         return;
     }
-    
+
     PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SAI_PLLI2S;
     PeriphClkInitStruct.PLLI2S.PLLI2SN = SAI_PSC_TBL[i][1];
     PeriphClkInitStruct.PLLI2S.PLLI2SQ = SAI_PSC_TBL[i][2];
     PeriphClkInitStruct.PLLI2SDivQ = SAI_PSC_TBL[i][3] + 1;
-    
+
     HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
 
     __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(RCC_SAIACLKSOURCE_PLLI2S);
diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.h b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.h
index 216481444f..28a1ea210d 100644
--- a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.h
+++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_sound.h
@@ -1,19 +1,19 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author         Notes
- * 2019-07-28     Ernest         the first version 
+ * 2019-07-28     Ernest         the first version
  */
 
-#ifndef __DRV_SOUND_H_ 
-#define __DRV_SOUND_H_ 
+#ifndef __DRV_SOUND_H_
+#define __DRV_SOUND_H_
 
-#include  
+#include 
 #include 
-#include  
+#include 
 
 #define AUDIO_FREQUENCY_048K ((rt_uint32_t) 48000)
 #define AUDIO_FREQUENCY_044K ((rt_uint32_t) 44100)
diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.c b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.c
index 5c7b8084c4..0f650538f9 100644
--- a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.c
+++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -763,8 +763,8 @@ rt_err_t wm8978_init(struct rt_i2c_bus_device *dev)
 
     wm8978_interface_cfg(dev, I2S_FOMAT_SELECT, 16);
     wm8978_mic_enabled(dev, 0);
-	
-  	return RT_EOK;
+
+    return RT_EOK;
 }
 
 void wm8978_DAC_enabled(struct rt_i2c_bus_device *dev, rt_bool_t bool)
diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.h b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.h
index d385255f9c..fe476ec0bb 100644
--- a/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.h
+++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/audio/drv_wm8978.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/fal_cfg.h b/bsp/stm32/stm32f429-atk-apollo/board/ports/fal_cfg.h
index a587e207ce..995136cd54 100644
--- a/bsp/stm32/stm32f429-atk-apollo/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/phy_reset.c b/bsp/stm32/stm32f429-atk-apollo/board/ports/phy_reset.c
index 666d053b25..826f8c7ded 100644
--- a/bsp/stm32/stm32f429-atk-apollo/board/ports/phy_reset.c
+++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/phy_reset.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,8 +16,8 @@
 #include 
 
 #define ETH_RESET_IO    7                //PHY RESET PIN
-#define I2C_BUS_NAME	"i2c1"
-#define PCF8574_ADDR 	0x20
+#define I2C_BUS_NAME    "i2c1"
+#define PCF8574_ADDR    0x20
 
 /* pcf8574 hardware init */
 pcf8574_device_t pcf8574_hw_init(char * dev_name, int addr)
diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/sdcard_port.c b/bsp/stm32/stm32f429-atk-apollo/board/ports/sdcard_port.c
index 0a9c36fd42..fe2595fa4b 100644
--- a/bsp/stm32/stm32f429-atk-apollo/board/ports/sdcard_port.c
+++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/sdcard_port.c
@@ -1,11 +1,12 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2018-12-13     balanceTWK   add sdcard port file
+ * 2021-02-18     DavidLin     Fixed the return bug
  */
 
 #include 
@@ -53,6 +54,7 @@ int stm32_sdcard_mount(void)
     else
     {
         LOG_E("create sd_mount thread err!");
+        return -RT_ERROR;
     }
     return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/sdram_port.h b/bsp/stm32/stm32f429-atk-apollo/board/ports/sdram_port.h
index ff948cb61e..85697210fa 100644
--- a/bsp/stm32/stm32f429-atk-apollo/board/ports/sdram_port.h
+++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/sdram_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-atk-apollo/board/ports/spi_flash_init.c b/bsp/stm32/stm32f429-atk-apollo/board/ports/spi_flash_init.c
index 26a9b2d2a8..7e35a36c86 100644
--- a/bsp/stm32/stm32f429-atk-apollo/board/ports/spi_flash_init.c
+++ b/bsp/stm32/stm32f429-atk-apollo/board/ports/spi_flash_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-fire-challenger/applications/main.c b/bsp/stm32/stm32f429-fire-challenger/applications/main.c
index 1078b64286..27c28e0cb2 100644
--- a/bsp/stm32/stm32f429-fire-challenger/applications/main.c
+++ b/bsp/stm32/stm32f429-fire-challenger/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -18,17 +18,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f429-fire-challenger/board/Kconfig b/bsp/stm32/stm32f429-fire-challenger/board/Kconfig
index 7bb6c541e5..67060c697a 100644
--- a/bsp/stm32/stm32f429-fire-challenger/board/Kconfig
+++ b/bsp/stm32/stm32f429-fire-challenger/board/Kconfig
@@ -209,7 +209,6 @@ menu "On-chip Peripheral Drivers"
     menuconfig BSP_USING_ONCHIP_RTC
         bool "Enable RTC"
         select RT_USING_RTC
-        select RT_USING_LIBC
         default n
         if BSP_USING_ONCHIP_RTC
             choice
diff --git a/bsp/stm32/stm32f429-fire-challenger/board/board.c b/bsp/stm32/stm32f429-fire-challenger/board/board.c
index ec47ab0d3a..5ca583d599 100644
--- a/bsp/stm32/stm32f429-fire-challenger/board/board.c
+++ b/bsp/stm32/stm32f429-fire-challenger/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-fire-challenger/board/board.h b/bsp/stm32/stm32f429-fire-challenger/board/board.h
index ab9e1733e9..c51f6a93cc 100644
--- a/bsp/stm32/stm32f429-fire-challenger/board/board.h
+++ b/bsp/stm32/stm32f429-fire-challenger/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-fire-challenger/board/ports/fal_cfg.h b/bsp/stm32/stm32f429-fire-challenger/board/ports/fal_cfg.h
index a587e207ce..995136cd54 100644
--- a/bsp/stm32/stm32f429-fire-challenger/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32f429-fire-challenger/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-fire-challenger/board/ports/lcd_port.h b/bsp/stm32/stm32f429-fire-challenger/board/ports/lcd_port.h
index 2660f3931b..8d297ec915 100644
--- a/bsp/stm32/stm32f429-fire-challenger/board/ports/lcd_port.h
+++ b/bsp/stm32/stm32f429-fire-challenger/board/ports/lcd_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-fire-challenger/board/ports/phy_reset.c b/bsp/stm32/stm32f429-fire-challenger/board/ports/phy_reset.c
index 298dd14e29..8eaf6dcd5a 100644
--- a/bsp/stm32/stm32f429-fire-challenger/board/ports/phy_reset.c
+++ b/bsp/stm32/stm32f429-fire-challenger/board/ports/phy_reset.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-fire-challenger/board/ports/sdcard_port.c b/bsp/stm32/stm32f429-fire-challenger/board/ports/sdcard_port.c
index d7b740ae47..01111ab4d3 100644
--- a/bsp/stm32/stm32f429-fire-challenger/board/ports/sdcard_port.c
+++ b/bsp/stm32/stm32f429-fire-challenger/board/ports/sdcard_port.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-fire-challenger/board/ports/sdram_port.h b/bsp/stm32/stm32f429-fire-challenger/board/ports/sdram_port.h
index 72d7c8d06d..1e5978871b 100644
--- a/bsp/stm32/stm32f429-fire-challenger/board/ports/sdram_port.h
+++ b/bsp/stm32/stm32f429-fire-challenger/board/ports/sdram_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-fire-challenger/board/ports/spi_flash_init.c b/bsp/stm32/stm32f429-fire-challenger/board/ports/spi_flash_init.c
index 5a1a4a2585..94a550cf37 100644
--- a/bsp/stm32/stm32f429-fire-challenger/board/ports/spi_flash_init.c
+++ b/bsp/stm32/stm32f429-fire-challenger/board/ports/spi_flash_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-st-disco/applications/lcd_init.c b/bsp/stm32/stm32f429-st-disco/applications/lcd_init.c
index 277a754ae6..2660e6ef7c 100644
--- a/bsp/stm32/stm32f429-st-disco/applications/lcd_init.c
+++ b/bsp/stm32/stm32f429-st-disco/applications/lcd_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-st-disco/applications/main.c b/bsp/stm32/stm32f429-st-disco/applications/main.c
index 8e6e8caef1..48f43fd6fa 100644
--- a/bsp/stm32/stm32f429-st-disco/applications/main.c
+++ b/bsp/stm32/stm32f429-st-disco/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -18,17 +18,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED1 pin mode to output */
     rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED1_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED1_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f429-st-disco/board/board.c b/bsp/stm32/stm32f429-st-disco/board/board.c
index 0abc70267a..542681ae0b 100644
--- a/bsp/stm32/stm32f429-st-disco/board/board.c
+++ b/bsp/stm32/stm32f429-st-disco/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,11 +17,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -35,7 +35,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
@@ -48,7 +48,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /*##-2- LTDC Clock Configuration ###########################################*/  
+  /*##-2- LTDC Clock Configuration ###########################################*/
   /* LCD clock configuration */
   /* PLLSAI_VCO Input = HSE_VALUE/PLL_M = 1 MHz */
   /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN = 192 MHz */
@@ -58,5 +58,5 @@ void SystemClock_Config(void)
   PeriphClkInitStruct.PLLSAI.PLLSAIN = 192;
   PeriphClkInitStruct.PLLSAI.PLLSAIR = 4;
   PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_8;
-  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); 
+  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
 }
diff --git a/bsp/stm32/stm32f429-st-disco/board/board.h b/bsp/stm32/stm32f429-st-disco/board/board.h
index 69e3eb1fac..ce8f2cc591 100644
--- a/bsp/stm32/stm32f429-st-disco/board/board.h
+++ b/bsp/stm32/stm32f429-st-disco/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-st-disco/board/ports/fal_cfg.h b/bsp/stm32/stm32f429-st-disco/board/ports/fal_cfg.h
index 46ecb322c4..ac75718bc7 100644
--- a/bsp/stm32/stm32f429-st-disco/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32f429-st-disco/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -57,7 +57,7 @@ extern struct fal_flash_dev nor_flash0;
     &nor_flash0,                                                     \
 }
 
-#define ONCHIP_FLASH_PART_TABLE 
+#define ONCHIP_FLASH_PART_TABLE
 
 #define QSPI_FLASH_PART_TABLE \
     {FAL_PART_MAGIC_WROD, "qspiflash",  FAL_USING_NOR_FLASH_DEV_NAME, 0 , (16 * 1024 * 1024), 0},
@@ -76,7 +76,7 @@ extern struct fal_flash_dev nor_flash0;
     {FAL_PART_MAGIC_WROD, "param",      "onchip_flash_64k",  0 , FLASH_SIZE_GRANULARITY_64K , 0}, \
     {FAL_PART_MAGIC_WROD, "app",        "onchip_flash_128k", 0 , FLASH_SIZE_GRANULARITY_128K, 0},
 
-#define QSPI_FLASH_PART_TABLE 
+#define QSPI_FLASH_PART_TABLE
 
 #else
 
diff --git a/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.c b/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.c
index 3829193b5c..f8e9eda216 100644
--- a/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.c
+++ b/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.c
@@ -1,21 +1,7 @@
 /*
- * File      : ili9341.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -25,28 +11,28 @@
 #include "stm32f4xx_hal.h"
 #include "ili9341.h"
 
-/** 
-  * @brief  LCD Control pin  
-  */ 
+/**
+  * @brief  LCD Control pin
+  */
 #define LCD_NCS_PIN                             GPIO_PIN_2
 #define LCD_NCS_GPIO_PORT                       GPIOC
 #define LCD_NCS_GPIO_CLK_ENABLE()               __HAL_RCC_GPIOC_CLK_ENABLE()
 #define LCD_NCS_GPIO_CLK_DISABLE()              __HAL_RCC_GPIOC_CLK_DISABLE()
 
-/** 
-  * @brief  LCD Command/data pin  
+/**
+  * @brief  LCD Command/data pin
   */
 #define LCD_WRX_PIN                             GPIO_PIN_13
 #define LCD_WRX_GPIO_PORT                       GPIOD
 #define LCD_WRX_GPIO_CLK_ENABLE()               __HAL_RCC_GPIOD_CLK_ENABLE()
 #define LCD_WRX_GPIO_CLK_DISABLE()              __HAL_RCC_GPIOD_CLK_DISABLE()
-  
+
 #define LCD_RDX_PIN                             GPIO_PIN_12
 #define LCD_RDX_GPIO_PORT                       GPIOD
 #define LCD_RDX_GPIO_CLK_ENABLE()               __HAL_RCC_GPIOD_CLK_ENABLE()
 #define LCD_RDX_GPIO_CLK_DISABLE()              __HAL_RCC_GPIOD_CLK_DISABLE()
 
-/* Maximum Timeout values for flags waiting loops */   
+/* Maximum Timeout values for flags waiting loops */
 #define SPIx_TIMEOUT_MAX              ((uint32_t)0x1000)
 
 /* Chip Select macro definition */
@@ -73,8 +59,8 @@ static void SPIx_Init(void)
   {
     /* SPI configuration -----------------------------------------------------*/
     SpiHandle.Instance = SPI5;
-    /* SPI baudrate is set to 5.6 MHz (PCLK2/SPI_BaudRatePrescaler = 90/16 = 5.625 MHz) 
-    */  
+    /* SPI baudrate is set to 5.6 MHz (PCLK2/SPI_BaudRatePrescaler = 90/16 = 5.625 MHz)
+    */
     SpiHandle.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;
 
     /* On STM32F429I-Discovery, LCD ID cannot be read then keep a common configuration */
@@ -90,9 +76,9 @@ static void SPIx_Init(void)
     SpiHandle.Init.NSS            = SPI_NSS_SOFT;
     SpiHandle.Init.TIMode         = SPI_TIMODE_DISABLED;
     SpiHandle.Init.Mode           = SPI_MODE_MASTER;
-  
+
     HAL_SPI_Init(&SpiHandle);
-  } 
+  }
 }
 
 /**
@@ -101,11 +87,11 @@ static void SPIx_Init(void)
 static void LCD_GPIO_Init(void)
 {
   GPIO_InitTypeDef GPIO_InitStructure;
-  
+
   if(Is_LCD_IO_Initialized == 0)
   {
-    Is_LCD_IO_Initialized = 1; 
-    
+    Is_LCD_IO_Initialized = 1;
+
     /* Configure NCS in Output Push-Pull mode */
     LCD_WRX_GPIO_CLK_ENABLE();
     GPIO_InitStructure.Pin     = LCD_WRX_PIN;
@@ -113,28 +99,28 @@ static void LCD_GPIO_Init(void)
     GPIO_InitStructure.Pull    = GPIO_NOPULL;
     GPIO_InitStructure.Speed   = GPIO_SPEED_FAST;
     HAL_GPIO_Init(LCD_WRX_GPIO_PORT, &GPIO_InitStructure);
-    
+
     LCD_RDX_GPIO_CLK_ENABLE();
     GPIO_InitStructure.Pin     = LCD_RDX_PIN;
     GPIO_InitStructure.Mode    = GPIO_MODE_OUTPUT_PP;
     GPIO_InitStructure.Pull    = GPIO_NOPULL;
     GPIO_InitStructure.Speed   = GPIO_SPEED_FAST;
     HAL_GPIO_Init(LCD_RDX_GPIO_PORT, &GPIO_InitStructure);
-    
+
     /* Configure the LCD Control pins ----------------------------------------*/
     LCD_NCS_GPIO_CLK_ENABLE();
-    
+
     /* Configure NCS in Output Push-Pull mode */
     GPIO_InitStructure.Pin     = LCD_NCS_PIN;
     GPIO_InitStructure.Mode    = GPIO_MODE_OUTPUT_PP;
     GPIO_InitStructure.Pull    = GPIO_NOPULL;
     GPIO_InitStructure.Speed   = GPIO_SPEED_FAST;
     HAL_GPIO_Init(LCD_NCS_GPIO_PORT, &GPIO_InitStructure);
-    
+
     /* Set or Reset the control line */
     LCD_CS_LOW();
     LCD_CS_HIGH();
-    
+
     SPIx_Init();
   }
 }
@@ -148,12 +134,12 @@ static void ili9341_write_data(uint16_t data)
 {
   /* Set WRX to send data */
   LCD_WRX_HIGH();
-  
-  /* Reset LCD control line(/CS) and Send data */  
+
+  /* Reset LCD control line(/CS) and Send data */
   LCD_CS_LOW();
-  
-	HAL_SPI_Transmit(&SpiHandle, (uint8_t*) &data, 1, SPIx_TIMEOUT_MAX);
-	
+
+    HAL_SPI_Transmit(&SpiHandle, (uint8_t*) &data, 1, SPIx_TIMEOUT_MAX);
+
   /* Deselect: Chip Select high */
   LCD_CS_HIGH();
 }
@@ -167,12 +153,12 @@ static void ili9341_write_register(uint8_t reg)
 {
   /* Reset WRX to send command */
   LCD_WRX_LOW();
-  
+
   /* Reset LCD control line(/CS) and Send command */
   LCD_CS_LOW();
-  
+
   HAL_SPI_Transmit(&SpiHandle, (uint8_t*) ®, 1, SPIx_TIMEOUT_MAX);
-  
+
   /* Deselect: Chip Select high */
   LCD_CS_HIGH();
 }
@@ -186,7 +172,7 @@ int ili9341_hw_init(void)
 {
   /* Initialize ILI9341 low level bus layer ----------------------------------*/
   LCD_GPIO_Init();
-  
+
   /* Configure LCD */
   ili9341_write_register(0xCA);
   ili9341_write_data(0xC3);
@@ -242,7 +228,7 @@ int ili9341_hw_init(void)
   ili9341_write_data(0xA7);
   ili9341_write_data(0x27);
   ili9341_write_data(0x04);
-  
+
   /* Colomn address set */
   ili9341_write_register(LCD_COLUMN_ADDR);
   ili9341_write_data(0x00);
@@ -259,13 +245,13 @@ int ili9341_hw_init(void)
   ili9341_write_data(0x01);
   ili9341_write_data(0x00);
   ili9341_write_data(0x06);
-  
+
   ili9341_write_register(LCD_GRAM);
   rt_thread_mdelay(20);
-  
+
   ili9341_write_register(LCD_GAMMA);
   ili9341_write_data(0x01);
-  
+
   ili9341_write_register(LCD_PGAMMA);
   ili9341_write_data(0x0F);
   ili9341_write_data(0x29);
@@ -298,14 +284,14 @@ int ili9341_hw_init(void)
   ili9341_write_data(0x28);
   ili9341_write_data(0x2F);
   ili9341_write_data(0x0F);
-  
+
   ili9341_write_register(LCD_SLEEP_OUT);
   rt_thread_mdelay(20);
   ili9341_write_register(LCD_DISPLAY_ON);
   /* GRAM start writing */
   ili9341_write_register(LCD_GRAM);
-	
-	return 0;
+
+    return 0;
 }
 INIT_DEVICE_EXPORT(ili9341_hw_init);
 
diff --git a/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.h b/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.h
index b4c59e6ffa..d2403452ef 100644
--- a/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.h
+++ b/bsp/stm32/stm32f429-st-disco/board/ports/ili9341.h
@@ -1,21 +1,7 @@
 /*
- * File      : ili9341.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -26,16 +12,16 @@
 
 #ifdef __cplusplus
  extern "C" {
-#endif 
+#endif
 
 
-/** 
-  * @brief ILI9341 chip IDs  
-  */ 
+/**
+  * @brief ILI9341 chip IDs
+  */
 #define ILI9341_ID                  0x9341
 
-/** 
-  * @brief  ILI9341 Registers  
+/**
+  * @brief  ILI9341 Registers
   */
 
 /* Level 1 Commands */
@@ -57,32 +43,32 @@
 #define LCD_GAMMA               0x26   /* Gamma register */
 #define LCD_DISPLAY_OFF         0x28   /* Display off register */
 #define LCD_DISPLAY_ON          0x29   /* Display on register */
-#define LCD_COLUMN_ADDR         0x2A   /* Colomn address register */ 
-#define LCD_PAGE_ADDR           0x2B   /* Page address register */ 
-#define LCD_GRAM                0x2C   /* GRAM register */   
-#define LCD_RGBSET              0x2D   /* Color SET */   
-#define LCD_RAMRD               0x2E   /* Memory Read */   
-#define LCD_PLTAR               0x30   /* Partial Area */   
-#define LCD_VSCRDEF             0x33   /* Vertical Scrolling Definition */   
-#define LCD_TEOFF               0x34   /* Tearing Effect Line OFF */   
-#define LCD_TEON                0x35   /* Tearing Effect Line ON */   
+#define LCD_COLUMN_ADDR         0x2A   /* Colomn address register */
+#define LCD_PAGE_ADDR           0x2B   /* Page address register */
+#define LCD_GRAM                0x2C   /* GRAM register */
+#define LCD_RGBSET              0x2D   /* Color SET */
+#define LCD_RAMRD               0x2E   /* Memory Read */
+#define LCD_PLTAR               0x30   /* Partial Area */
+#define LCD_VSCRDEF             0x33   /* Vertical Scrolling Definition */
+#define LCD_TEOFF               0x34   /* Tearing Effect Line OFF */
+#define LCD_TEON                0x35   /* Tearing Effect Line ON */
 #define LCD_MAC                 0x36   /* Memory Access Control register*/
-#define LCD_VSCRSADD            0x37   /* Vertical Scrolling Start Address */   
-#define LCD_IDMOFF              0x38   /* Idle Mode OFF */   
-#define LCD_IDMON               0x39   /* Idle Mode ON */   
+#define LCD_VSCRSADD            0x37   /* Vertical Scrolling Start Address */
+#define LCD_IDMOFF              0x38   /* Idle Mode OFF */
+#define LCD_IDMON               0x39   /* Idle Mode ON */
 #define LCD_PIXEL_FORMAT        0x3A   /* Pixel Format register */
-#define LCD_WRITE_MEM_CONTINUE  0x3C   /* Write Memory Continue */   
-#define LCD_READ_MEM_CONTINUE   0x3E   /* Read Memory Continue */   
-#define LCD_SET_TEAR_SCANLINE   0x44   /* Set Tear Scanline */   
-#define LCD_GET_SCANLINE        0x45   /* Get Scanline */   
+#define LCD_WRITE_MEM_CONTINUE  0x3C   /* Write Memory Continue */
+#define LCD_READ_MEM_CONTINUE   0x3E   /* Read Memory Continue */
+#define LCD_SET_TEAR_SCANLINE   0x44   /* Set Tear Scanline */
+#define LCD_GET_SCANLINE        0x45   /* Get Scanline */
 #define LCD_WDB                 0x51   /* Write Brightness Display register */
-#define LCD_RDDISBV             0x52   /* Read Display Brightness */   
+#define LCD_RDDISBV             0x52   /* Read Display Brightness */
 #define LCD_WCD                 0x53   /* Write Control Display register*/
-#define LCD_RDCTRLD             0x54   /* Read CTRL Display */   
-#define LCD_WRCABC              0x55   /* Write Content Adaptive Brightness Control */   
-#define LCD_RDCABC              0x56   /* Read Content Adaptive Brightness Control */   
-#define LCD_WRITE_CABC          0x5E   /* Write CABC Minimum Brightness */   
-#define LCD_READ_CABC           0x5F   /* Read CABC Minimum Brightness */   
+#define LCD_RDCTRLD             0x54   /* Read CTRL Display */
+#define LCD_WRCABC              0x55   /* Write Content Adaptive Brightness Control */
+#define LCD_RDCABC              0x56   /* Read Content Adaptive Brightness Control */
+#define LCD_WRITE_CABC          0x5E   /* Write CABC Minimum Brightness */
+#define LCD_READ_CABC           0x5F   /* Read CABC Minimum Brightness */
 #define LCD_READ_ID1            0xDA   /* Read ID1 */
 #define LCD_READ_ID2            0xDB   /* Read ID2 */
 #define LCD_READ_ID3            0xDC   /* Read ID3 */
@@ -129,13 +115,13 @@
 /* Size of read registers */
 #define LCD_READ_ID4_SIZE        3      /* Size of Read ID4 */
 
-  
+
 /** @defgroup ILI9341_Exported_Functions
   * @{
-  */ 
+  */
 int ili9341_hw_init(void);
 
-      
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/bsp/stm32/stm32f429-st-disco/board/ports/lcd_port.h b/bsp/stm32/stm32f429-st-disco/board/ports/lcd_port.h
index 6f8112cc1b..21801def62 100644
--- a/bsp/stm32/stm32f429-st-disco/board/ports/lcd_port.h
+++ b/bsp/stm32/stm32f429-st-disco/board/ports/lcd_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-st-disco/board/ports/sdram_port.h b/bsp/stm32/stm32f429-st-disco/board/ports/sdram_port.h
index 77c80f58ff..5a9f83e7d6 100644
--- a/bsp/stm32/stm32f429-st-disco/board/ports/sdram_port.h
+++ b/bsp/stm32/stm32f429-st-disco/board/ports/sdram_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.c b/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.c
index 8559b69f98..d70e444ef4 100644
--- a/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.c
+++ b/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -154,7 +154,7 @@ int32_t touch_get_state(struct touch_state *state)
     res = touch_read(STMPE811_TSC_CTRL, &val);
     if (res < 0) return -1;
     state->pressed = (val & (1 << 7)) ? 1 : 0;
-  
+
     if (state->pressed)
     {
         val = STMPE811_TSC_DATA;
@@ -218,7 +218,7 @@ static int rt_hw_touch_init(void)
 
     /* register touch device to RT-Thread */
     rt_device_register(&touch, "touch", RT_DEVICE_FLAG_RDWR);
-    
+
     return RT_EOK;
 }
 INIT_BOARD_EXPORT(rt_hw_touch_init);
diff --git a/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.h b/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.h
index 68c8f92b7f..a7b6328f17 100644
--- a/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.h
+++ b/bsp/stm32/stm32f429-st-disco/board/ports/touch/drv_touch.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f446-st-nucleo/applications/main.c b/bsp/stm32/stm32f446-st-nucleo/applications/main.c
index 0f283769a9..b419a79449 100644
--- a/bsp/stm32/stm32f446-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32f446-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED2 pin mode to output */
     rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED2_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED2_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f446-st-nucleo/board/board.c b/bsp/stm32/stm32f446-st-nucleo/board/board.c
index aba3df89e1..a2500ee68a 100644
--- a/bsp/stm32/stm32f446-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32f446-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,11 +16,11 @@ void SystemClock_Config(void)
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-  /**Configure the main internal regulator output voltage 
+  /**Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -35,13 +35,13 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Activate the Over-Drive mode 
+  /**Activate the Over-Drive mode
   */
   if (HAL_PWREx_EnableOverDrive() != HAL_OK)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f446-st-nucleo/board/board.h b/bsp/stm32/stm32f446-st-nucleo/board/board.h
index 1800e44079..8cb4438f8b 100644
--- a/bsp/stm32/stm32f446-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32f446-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f469-st-disco/applications/lcd_init.c b/bsp/stm32/stm32f469-st-disco/applications/lcd_init.c
index 277a754ae6..2660e6ef7c 100644
--- a/bsp/stm32/stm32f469-st-disco/applications/lcd_init.c
+++ b/bsp/stm32/stm32f469-st-disco/applications/lcd_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f469-st-disco/applications/main.c b/bsp/stm32/stm32f469-st-disco/applications/main.c
index 8feca19928..e5a331ad8c 100644
--- a/bsp/stm32/stm32f469-st-disco/applications/main.c
+++ b/bsp/stm32/stm32f469-st-disco/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -18,17 +18,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED1 pin mode to output */
     rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED1_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED1_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f469-st-disco/board/board.c b/bsp/stm32/stm32f469-st-disco/board/board.c
index 8c4c361dcc..fefb07fafd 100644
--- a/bsp/stm32/stm32f469-st-disco/board/board.c
+++ b/bsp/stm32/stm32f469-st-disco/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,11 +17,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -36,13 +36,13 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Activate the Over-Drive mode 
+  /** Activate the Over-Drive mode
   */
   if (HAL_PWREx_EnableOverDrive() != HAL_OK)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f469-st-disco/board/board.h b/bsp/stm32/stm32f469-st-disco/board/board.h
index 0880c1f384..607aa3877d 100644
--- a/bsp/stm32/stm32f469-st-disco/board/board.h
+++ b/bsp/stm32/stm32f469-st-disco/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/drv_otm8009a.c b/bsp/stm32/stm32f469-st-disco/board/ports/drv_otm8009a.c
index 84202f84c8..8fde3a56ae 100644
--- a/bsp/stm32/stm32f469-st-disco/board/ports/drv_otm8009a.c
+++ b/bsp/stm32/stm32f469-st-disco/board/ports/drv_otm8009a.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author         Notes
  * 2019-05-23     WillianChan    first version
  */
- 
+
 #include 
 #ifdef BSP_USING_LCD_OTM8009A
 extern DSI_HandleTypeDef hdsi;
@@ -93,9 +93,9 @@ const rt_uint8_t RDS49[] = {0xF5, 0x06};
 const rt_uint8_t RDS50[] = {0x00, 0xB1};
 const rt_uint8_t RDS51[] = {0xC6, 0x06};
 
-void otm8009a_reset(void) 
+void otm8009a_reset(void)
 {
-    rt_pin_mode (GET_PIN(H, 7), PIN_MODE_OUTPUT); 
+    rt_pin_mode (GET_PIN(H, 7), PIN_MODE_OUTPUT);
     rt_pin_write(GET_PIN(H, 7), PIN_LOW);
     rt_thread_delay(rt_tick_from_millisecond(20));
     rt_pin_write(GET_PIN(H, 7), PIN_HIGH);
@@ -116,7 +116,7 @@ static void otm8009a_write_cmd(uint8_t *p, uint32_t num)
 
 static void otm8009a_delay(uint32_t d)
 {
-    rt_thread_delay(rt_tick_from_millisecond(d)); 
+    rt_thread_delay(rt_tick_from_millisecond(d));
 }
 
 static void otm8009a_config(rt_uint32_t pixel_format)
@@ -127,11 +127,11 @@ static void otm8009a_config(rt_uint32_t pixel_format)
     otm8009a_write_cmd((rt_uint8_t *)RDL02, 2);
     otm8009a_write_cmd((rt_uint8_t *)RDS02, 0);
     otm8009a_write_cmd((rt_uint8_t *)RDS03, 0);
-    otm8009a_delay(10); 
+    otm8009a_delay(10);
 
     otm8009a_write_cmd((rt_uint8_t *)RDS04, 0);
     otm8009a_write_cmd((rt_uint8_t *)RDS05, 0);
-    otm8009a_delay(10); 
+    otm8009a_delay(10);
 
     otm8009a_write_cmd((rt_uint8_t *)RDS06, 0);
     otm8009a_write_cmd((rt_uint8_t *)RDS07, 0);
@@ -215,8 +215,8 @@ static void otm8009a_config(rt_uint32_t pixel_format)
     otm8009a_write_cmd((rt_uint8_t *)RDS01, 0);
     otm8009a_write_cmd((rt_uint8_t *)RDL04, 16);
     otm8009a_write_cmd((rt_uint8_t *)RDS36, 0);
-    otm8009a_delay(120); 
-    
+    otm8009a_delay(120);
+
     switch (pixel_format)
     {
     case RTGRAPHIC_PIXEL_FORMAT_RGB565:
@@ -248,7 +248,7 @@ void stm32_mipi_lcd_init(void)
 
 void stm32_mipi_lcd_config(rt_uint32_t pixel_format)
 {
-    otm8009a_config(pixel_format); 
+    otm8009a_config(pixel_format);
 }
 
 void stm32_mipi_display_on(void)
diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32f469-st-disco/board/ports/drv_qspi_flash.c
index f5fe27d6e1..ff1b11e34c 100644
--- a/bsp/stm32/stm32f469-st-disco/board/ports/drv_qspi_flash.c
+++ b/bsp/stm32/stm32f469-st-disco/board/ports/drv_qspi_flash.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -8,7 +8,7 @@
  * 2018-11-27     zylx         first version
  * 2019-04-11     ZYH          port from stm32f7serial
  */
- 
+
 #include 
 #include 
 #include 
@@ -64,7 +64,7 @@ void n25qxxa_enter_qspi_mode(struct rt_qspi_device *device)
 static int rt_hw_qspi_flash_with_sfud_init(void)
 {
     stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, n25qxxa_enter_qspi_mode, RT_NULL);
-    
+
     /* init n25qxx */
     if (RT_NULL == rt_sfud_flash_probe(FAL_USING_NOR_FLASH_DEV_NAME, "qspi10"))
     {
diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/drv_sdcard.c b/bsp/stm32/stm32f469-st-disco/board/ports/drv_sdcard.c
index cfe6f59e1e..9fd2d11fd4 100644
--- a/bsp/stm32/stm32f469-st-disco/board/ports/drv_sdcard.c
+++ b/bsp/stm32/stm32f469-st-disco/board/ports/drv_sdcard.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -29,7 +29,7 @@
 static void _sdcard_mount(void)
 {
     rt_device_t device;
-    
+
     device = rt_device_find("sd0");
     if (device == NULL)
     {
@@ -56,7 +56,7 @@ static void _sdcard_unmount(void)
     rt_thread_mdelay(200);
     dfs_unmount("/");
     LOG_I("Unmount \"/\"");
-    
+
     mmcsd_wait_cd_changed(0);
     stm32_mmcsd_change();
     mmcsd_wait_cd_changed(RT_WAITING_FOREVER);
@@ -65,7 +65,7 @@ static void _sdcard_unmount(void)
 static void sd_mount(void *parameter)
 {
     rt_uint8_t re_sd_check_pin = 1;
-    
+
     while (1)
     {
         rt_thread_mdelay(200);
@@ -73,7 +73,7 @@ static void sd_mount(void *parameter)
         {
             _sdcard_mount();
         }
-        
+
         if (!re_sd_check_pin && (re_sd_check_pin = rt_pin_read(SD_CHECK_PIN)) != 0)
         {
             _sdcard_unmount();
@@ -84,7 +84,7 @@ static void sd_mount(void *parameter)
 int stm32_sdcard_mount(void)
 {
     rt_thread_t tid;
-    
+
     rt_pin_mode(SD_CHECK_PIN, PIN_MODE_INPUT_PULLUP);
 
     tid = rt_thread_create("sd_mount", sd_mount, RT_NULL,
diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/fal_cfg.h b/bsp/stm32/stm32f469-st-disco/board/ports/fal_cfg.h
index 46ecb322c4..ac75718bc7 100644
--- a/bsp/stm32/stm32f469-st-disco/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32f469-st-disco/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -57,7 +57,7 @@ extern struct fal_flash_dev nor_flash0;
     &nor_flash0,                                                     \
 }
 
-#define ONCHIP_FLASH_PART_TABLE 
+#define ONCHIP_FLASH_PART_TABLE
 
 #define QSPI_FLASH_PART_TABLE \
     {FAL_PART_MAGIC_WROD, "qspiflash",  FAL_USING_NOR_FLASH_DEV_NAME, 0 , (16 * 1024 * 1024), 0},
@@ -76,7 +76,7 @@ extern struct fal_flash_dev nor_flash0;
     {FAL_PART_MAGIC_WROD, "param",      "onchip_flash_64k",  0 , FLASH_SIZE_GRANULARITY_64K , 0}, \
     {FAL_PART_MAGIC_WROD, "app",        "onchip_flash_128k", 0 , FLASH_SIZE_GRANULARITY_128K, 0},
 
-#define QSPI_FLASH_PART_TABLE 
+#define QSPI_FLASH_PART_TABLE
 
 #else
 
diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/lcd_port.h b/bsp/stm32/stm32f469-st-disco/board/ports/lcd_port.h
index d5ee2b13b4..b23a970538 100644
--- a/bsp/stm32/stm32f469-st-disco/board/ports/lcd_port.h
+++ b/bsp/stm32/stm32f469-st-disco/board/ports/lcd_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,19 +7,19 @@
  * Date           Author         Notes
  * 2018-07-28     liu2guang      the first version for STM32F469NI-Discovery.
  */
- 
-#ifndef __DRV_LCD_H_ 
-#define __DRV_LCD_H_ 
 
-#include  
+#ifndef __DRV_LCD_H_
+#define __DRV_LCD_H_
+
+#include 
 #include 
-#include  
+#include 
 
 #define  LCD_WIDTH    (800U)
 #define  LCD_HEIGHT   (480U)
 
 #define  LCD_HSYNC    (1U)
-#define  LCD_HBP      (15U) 
+#define  LCD_HBP      (15U)
 #define  LCD_HFP      (16U)
 #define  LCD_VSYNC    (2U)
 #define  LCD_VBP      (34U)
diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/qspi_mnt.c b/bsp/stm32/stm32f469-st-disco/board/ports/qspi_mnt.c
index f90b468463..5b311a391a 100644
--- a/bsp/stm32/stm32f469-st-disco/board/ports/qspi_mnt.c
+++ b/bsp/stm32/stm32f469-st-disco/board/ports/qspi_mnt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/sdram_port.h b/bsp/stm32/stm32f469-st-disco/board/ports/sdram_port.h
index 14d44f7115..7b33d36362 100644
--- a/bsp/stm32/stm32f469-st-disco/board/ports/sdram_port.h
+++ b/bsp/stm32/stm32f469-st-disco/board/ports/sdram_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.c b/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.c
index 1ff29544ff..53437f34ef 100644
--- a/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.c
+++ b/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-02-08     Zhangyihong  the first version
  */
- 
+
 #include "drv_touch.h"
 #include 
 #ifdef BSP_USING_TOUCH
@@ -105,7 +105,7 @@ static void touch_thread_entry(void *parameter)
         {
             continue;
         }
-        
+
         while(touch->ops->read_point(&msg) == RT_EOK)
         {
             switch (msg.event)
diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.h b/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.h
index a8fea21d54..21bea39f83 100644
--- a/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.h
+++ b/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-02-08     Zhangyihong  the first version
  */
- 
+
 #ifndef __DRV_TOUCH_H__
 #define __DRV_TOUCH_H__
 
diff --git a/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch_ft.c b/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch_ft.c
index a7e9275441..e85e793573 100644
--- a/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch_ft.c
+++ b/bsp/stm32/stm32f469-st-disco/board/ports/touch/drv_touch_ft.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -109,7 +109,7 @@ static rt_err_t ft_read_point(touch_msg_t msg)
     {
         return RT_ERROR;
     }
-    
+
     if (point_num == 0)
     {
         if (s_tp_down)
@@ -121,7 +121,7 @@ static rt_err_t ft_read_point(touch_msg_t msg)
         msg->event = TOUCH_EVENT_NONE;
         return RT_ERROR;
     }
-    
+
     ret = ft_read(ft_i2c_bus, 0x03, point, 6);
     if (ret < 0)
     {
@@ -130,7 +130,7 @@ static rt_err_t ft_read_point(touch_msg_t msg)
 
     msg->y = (point[0]&0x0F) << 8 | point[1];
     msg->x = (point[2]&0x0F) << 8 | point[3];
-    
+
     if (s_tp_down)
     {
         msg->event = TOUCH_EVENT_MOVE;
@@ -138,7 +138,7 @@ static rt_err_t ft_read_point(touch_msg_t msg)
     }
     msg->event = TOUCH_EVENT_DOWN;
     s_tp_down = 1;
-    
+
     return RT_EOK;
 }
 
diff --git a/bsp/stm32/stm32f746-st-disco/applications/main.c b/bsp/stm32/stm32f746-st-disco/applications/main.c
index 669d889e58..d98649e9c6 100644
--- a/bsp/stm32/stm32f746-st-disco/applications/main.c
+++ b/bsp/stm32/stm32f746-st-disco/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED1 pin mode to output */
     rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED1_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED1_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f746-st-disco/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c b/bsp/stm32/stm32f746-st-disco/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c
index ffae5e7f6c..fd77b00626 100644
--- a/bsp/stm32/stm32f746-st-disco/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c
+++ b/bsp/stm32/stm32f746-st-disco/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c
@@ -671,7 +671,7 @@ static void HAL_FMC_MspInit(void){
   /* USER CODE BEGIN FMC_MspInit 0 */
 
   /* USER CODE END FMC_MspInit 0 */
-  GPIO_InitTypeDef GPIO_InitStruct ={0};
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
   if (FMC_Initialized) {
     return;
   }
@@ -716,54 +716,34 @@ static void HAL_FMC_MspInit(void){
   PE15   ------> FMC_D12
   PE13   ------> FMC_D10
   */
-  GPIO_InitStruct.Pin = GPIO_PIN_15|GPIO_PIN_8|GPIO_PIN_0|GPIO_PIN_5 
-                          |GPIO_PIN_4;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Mode      = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull      = GPIO_NOPULL;
+  GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_VERY_HIGH;
   GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
-  HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
-
-  GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_10 
-                          |GPIO_PIN_14|GPIO_PIN_9|GPIO_PIN_8;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
-  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
-
-  GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 
-                          |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_15 
-                          |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_11;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
-  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
-
-  GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_3;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
-  HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
 
   GPIO_InitStruct.Pin = GPIO_PIN_3;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
   HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 
-  GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_11|GPIO_PIN_14 
-                          |GPIO_PIN_7|GPIO_PIN_10|GPIO_PIN_12|GPIO_PIN_15 
-                          |GPIO_PIN_13;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
+  GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | GPIO_PIN_9 |\
+                        GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15;
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9      |\
+                        GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
+                        GPIO_PIN_15;
   HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
 
+  GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4     |\
+                        GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
+                        GPIO_PIN_15;
+  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15;
+  HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin = GPIO_PIN_3 | GPIO_PIN_5;
+  HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
+
   /* USER CODE BEGIN FMC_MspInit 1 */
 
   /* USER CODE END FMC_MspInit 1 */
diff --git a/bsp/stm32/stm32f746-st-disco/board/Kconfig b/bsp/stm32/stm32f746-st-disco/board/Kconfig
index 378eafb110..b10181eeb9 100644
--- a/bsp/stm32/stm32f746-st-disco/board/Kconfig
+++ b/bsp/stm32/stm32f746-st-disco/board/Kconfig
@@ -103,7 +103,7 @@ menu "On-chip Peripheral Drivers"
         default n
         
     config BSP_USING_FMC
-        bool
+        bool "Enable Flash Memory Controller(FMC)"
         default n
 
     config BSP_USING_LTDC
diff --git a/bsp/stm32/stm32f746-st-disco/board/board.c b/bsp/stm32/stm32f746-st-disco/board/board.c
index bf92d115e7..da2564d515 100644
--- a/bsp/stm32/stm32f746-st-disco/board/board.c
+++ b/bsp/stm32/stm32f746-st-disco/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,14 +20,14 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
-  /**Configure LSE Drive Capability 
+  /**Configure LSE Drive Capability
   */
   HAL_PWR_EnableBkUpAccess();
-  /**Configure the main internal regulator output voltage 
+  /**Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -42,13 +42,13 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Activate the Over-Drive mode 
+  /**Activate the Over-Drive mode
   */
   if (HAL_PWREx_EnableOverDrive() != HAL_OK)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f746-st-disco/board/board.h b/bsp/stm32/stm32f746-st-disco/board/board.h
index 98e3799e00..b0c120fb41 100644
--- a/bsp/stm32/stm32f746-st-disco/board/board.h
+++ b/bsp/stm32/stm32f746-st-disco/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f746-st-disco/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32f746-st-disco/board/ports/drv_qspi_flash.c
index ca7641f866..4e37f4ec2f 100644
--- a/bsp/stm32/stm32f746-st-disco/board/ports/drv_qspi_flash.c
+++ b/bsp/stm32/stm32f746-st-disco/board/ports/drv_qspi_flash.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2019-01-26     jinsheng     first version
  */
- 
+
 #include 
 #include 
 #include 
@@ -63,7 +63,7 @@ void n25qxx_enter_qspi_mode(struct rt_qspi_device *device)
 static int rt_hw_qspi_flash_with_sfud_init(void)
 {
     stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, n25qxx_enter_qspi_mode, RT_NULL);
-    
+
     /* init n25q128 */
     if (RT_NULL == rt_sfud_flash_probe("n25q128", "qspi10"))
     {
diff --git a/bsp/stm32/stm32f746-st-disco/board/ports/fal_cfg.h b/bsp/stm32/stm32f746-st-disco/board/ports/fal_cfg.h
index c886dab45d..d7ce293475 100644
--- a/bsp/stm32/stm32f746-st-disco/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32f746-st-disco/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f746-st-disco/board/ports/lcd_port.h b/bsp/stm32/stm32f746-st-disco/board/ports/lcd_port.h
index f534e50522..8ea00b0ed4 100644
--- a/bsp/stm32/stm32f746-st-disco/board/ports/lcd_port.h
+++ b/bsp/stm32/stm32f746-st-disco/board/ports/lcd_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f746-st-disco/board/ports/phy_reset.c b/bsp/stm32/stm32f746-st-disco/board/ports/phy_reset.c
index 3d5f75c7f0..5825f775cc 100644
--- a/bsp/stm32/stm32f746-st-disco/board/ports/phy_reset.c
+++ b/bsp/stm32/stm32f746-st-disco/board/ports/phy_reset.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f746-st-disco/board/ports/sdcard_port.c b/bsp/stm32/stm32f746-st-disco/board/ports/sdcard_port.c
index 0797f9326c..66e8dfefab 100644
--- a/bsp/stm32/stm32f746-st-disco/board/ports/sdcard_port.c
+++ b/bsp/stm32/stm32f746-st-disco/board/ports/sdcard_port.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f746-st-disco/board/ports/sdram_port.h b/bsp/stm32/stm32f746-st-disco/board/ports/sdram_port.h
index 4c49e0f217..91bb91b01b 100644
--- a/bsp/stm32/stm32f746-st-disco/board/ports/sdram_port.h
+++ b/bsp/stm32/stm32f746-st-disco/board/ports/sdram_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f767-atk-apollo/applications/main.c b/bsp/stm32/stm32f767-atk-apollo/applications/main.c
index 7d7440f05c..bec589c403 100644
--- a/bsp/stm32/stm32f767-atk-apollo/applications/main.c
+++ b/bsp/stm32/stm32f767-atk-apollo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f767-atk-apollo/board/Kconfig b/bsp/stm32/stm32f767-atk-apollo/board/Kconfig
index 82efc63223..df86ffc383 100644
--- a/bsp/stm32/stm32f767-atk-apollo/board/Kconfig
+++ b/bsp/stm32/stm32f767-atk-apollo/board/Kconfig
@@ -226,7 +226,6 @@ menu "On-chip Peripheral Drivers"
     menuconfig BSP_USING_ONCHIP_RTC
         bool "Enable RTC"
         select RT_USING_RTC
-        select RT_USING_LIBC
         default n
         if BSP_USING_ONCHIP_RTC
             choice
diff --git a/bsp/stm32/stm32f767-atk-apollo/board/board.c b/bsp/stm32/stm32f767-atk-apollo/board/board.c
index d9959f9301..726b7783b7 100644
--- a/bsp/stm32/stm32f767-atk-apollo/board/board.c
+++ b/bsp/stm32/stm32f767-atk-apollo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,15 +16,15 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
-  /** Configure LSE Drive Capability 
+  /** Configure LSE Drive Capability
   */
   HAL_PWR_EnableBkUpAccess();
   __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
                               |RCC_OSCILLATORTYPE_LSE;
@@ -41,13 +41,13 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Activate the Over-Drive mode 
+  /** Activate the Over-Drive mode
   */
   if (HAL_PWREx_EnableOverDrive() != HAL_OK)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f767-atk-apollo/board/board.h b/bsp/stm32/stm32f767-atk-apollo/board/board.h
index 3d986024ae..e91271055e 100644
--- a/bsp/stm32/stm32f767-atk-apollo/board/board.h
+++ b/bsp/stm32/stm32f767-atk-apollo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f767-atk-apollo/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32f767-atk-apollo/board/ports/drv_qspi_flash.c
index 5cabc9d4d2..72e589aea4 100644
--- a/bsp/stm32/stm32f767-atk-apollo/board/ports/drv_qspi_flash.c
+++ b/bsp/stm32/stm32f767-atk-apollo/board/ports/drv_qspi_flash.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-11-27     zylx         first version
  */
- 
+
 #include 
 #include 
 #include 
@@ -63,7 +63,7 @@ void w25qxx_enter_qspi_mode(struct rt_qspi_device *device)
 static int rt_hw_qspi_flash_with_sfud_init(void)
 {
     stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, w25qxx_enter_qspi_mode, RT_NULL);
-    
+
     /* init W25Q256 */
     if (RT_NULL == rt_sfud_flash_probe("W25Q256", "qspi10"))
     {
diff --git a/bsp/stm32/stm32f767-atk-apollo/board/ports/fal_cfg.h b/bsp/stm32/stm32f767-atk-apollo/board/ports/fal_cfg.h
index 891beb2010..5ddddaa2cd 100644
--- a/bsp/stm32/stm32f767-atk-apollo/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32f767-atk-apollo/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f767-atk-apollo/board/ports/lcd_port.h b/bsp/stm32/stm32f767-atk-apollo/board/ports/lcd_port.h
index ca894bb045..156ba2e2cf 100644
--- a/bsp/stm32/stm32f767-atk-apollo/board/ports/lcd_port.h
+++ b/bsp/stm32/stm32f767-atk-apollo/board/ports/lcd_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f767-atk-apollo/board/ports/phy_reset.c b/bsp/stm32/stm32f767-atk-apollo/board/ports/phy_reset.c
index d00e6c06e0..18bed5f8e4 100644
--- a/bsp/stm32/stm32f767-atk-apollo/board/ports/phy_reset.c
+++ b/bsp/stm32/stm32f767-atk-apollo/board/ports/phy_reset.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f767-atk-apollo/board/ports/sdcard_port.c b/bsp/stm32/stm32f767-atk-apollo/board/ports/sdcard_port.c
index 0a9c36fd42..bc7e8b676e 100644
--- a/bsp/stm32/stm32f767-atk-apollo/board/ports/sdcard_port.c
+++ b/bsp/stm32/stm32f767-atk-apollo/board/ports/sdcard_port.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f767-atk-apollo/board/ports/sdram_port.h b/bsp/stm32/stm32f767-atk-apollo/board/ports/sdram_port.h
index ff948cb61e..85697210fa 100644
--- a/bsp/stm32/stm32f767-atk-apollo/board/ports/sdram_port.h
+++ b/bsp/stm32/stm32f767-atk-apollo/board/ports/sdram_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f767-fire-challenger/applications/main.c b/bsp/stm32/stm32f767-fire-challenger/applications/main.c
index 9ed6529712..3570c667c9 100644
--- a/bsp/stm32/stm32f767-fire-challenger/applications/main.c
+++ b/bsp/stm32/stm32f767-fire-challenger/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f767-fire-challenger/board/Kconfig b/bsp/stm32/stm32f767-fire-challenger/board/Kconfig
index 1769b1cfd7..6239d9e6f6 100644
--- a/bsp/stm32/stm32f767-fire-challenger/board/Kconfig
+++ b/bsp/stm32/stm32f767-fire-challenger/board/Kconfig
@@ -193,7 +193,6 @@ menuconfig BSP_USING_SPI
     menuconfig BSP_USING_ONCHIP_RTC
         bool "Enable RTC"
         select RT_USING_RTC
-        select RT_USING_LIBC
         default n
         if BSP_USING_ONCHIP_RTC
             choice
diff --git a/bsp/stm32/stm32f767-fire-challenger/board/board.c b/bsp/stm32/stm32f767-fire-challenger/board/board.c
index f5b0c783c7..de621405e1 100644
--- a/bsp/stm32/stm32f767-fire-challenger/board/board.c
+++ b/bsp/stm32/stm32f767-fire-challenger/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,11 +16,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
-  /**Configure the main internal regulator output voltage 
+  /**Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -34,13 +34,13 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Activate the Over-Drive mode 
+  /**Activate the Over-Drive mode
   */
   if (HAL_PWREx_EnableOverDrive() != HAL_OK)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f767-fire-challenger/board/board.h b/bsp/stm32/stm32f767-fire-challenger/board/board.h
index 1beb8c5f87..e9a1277849 100644
--- a/bsp/stm32/stm32f767-fire-challenger/board/board.h
+++ b/bsp/stm32/stm32f767-fire-challenger/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f767-fire-challenger/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32f767-fire-challenger/board/ports/drv_qspi_flash.c
index 36ecb754e9..a3091fd2eb 100644
--- a/bsp/stm32/stm32f767-fire-challenger/board/ports/drv_qspi_flash.c
+++ b/bsp/stm32/stm32f767-fire-challenger/board/ports/drv_qspi_flash.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-11-27     zylx         first version
  */
- 
+
 #include 
 #include 
 #include 
@@ -63,7 +63,7 @@ void w25qxx_enter_qspi_mode(struct rt_qspi_device *device)
 static int rt_hw_qspi_flash_with_sfud_init(void)
 {
     stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, w25qxx_enter_qspi_mode, RT_NULL);
-    
+
     /* init w25q128 */
     if (RT_NULL == rt_sfud_flash_probe("W25Q128", "qspi10"))
     {
diff --git a/bsp/stm32/stm32f767-fire-challenger/board/ports/fal_cfg.h b/bsp/stm32/stm32f767-fire-challenger/board/ports/fal_cfg.h
index 891beb2010..5ddddaa2cd 100644
--- a/bsp/stm32/stm32f767-fire-challenger/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32f767-fire-challenger/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f767-fire-challenger/board/ports/lcd_port.h b/bsp/stm32/stm32f767-fire-challenger/board/ports/lcd_port.h
index 2660f3931b..8d297ec915 100644
--- a/bsp/stm32/stm32f767-fire-challenger/board/ports/lcd_port.h
+++ b/bsp/stm32/stm32f767-fire-challenger/board/ports/lcd_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f767-fire-challenger/board/ports/phy_reset.c b/bsp/stm32/stm32f767-fire-challenger/board/ports/phy_reset.c
index 298dd14e29..8eaf6dcd5a 100644
--- a/bsp/stm32/stm32f767-fire-challenger/board/ports/phy_reset.c
+++ b/bsp/stm32/stm32f767-fire-challenger/board/ports/phy_reset.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f767-fire-challenger/board/ports/sdcard_port.c b/bsp/stm32/stm32f767-fire-challenger/board/ports/sdcard_port.c
index 615ad6e06e..f1a7b8c27f 100644
--- a/bsp/stm32/stm32f767-fire-challenger/board/ports/sdcard_port.c
+++ b/bsp/stm32/stm32f767-fire-challenger/board/ports/sdcard_port.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f767-fire-challenger/board/ports/sdram_port.h b/bsp/stm32/stm32f767-fire-challenger/board/ports/sdram_port.h
index 0d9c7e6918..7f9485aa4a 100644
--- a/bsp/stm32/stm32f767-fire-challenger/board/ports/sdram_port.h
+++ b/bsp/stm32/stm32f767-fire-challenger/board/ports/sdram_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f767-st-nucleo/applications/main.c b/bsp/stm32/stm32f767-st-nucleo/applications/main.c
index ed3fc2c341..e270c27a91 100644
--- a/bsp/stm32/stm32f767-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32f767-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -18,17 +18,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED1 pin mode to output */
     rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED1_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED1_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;		
 }
diff --git a/bsp/stm32/stm32f767-st-nucleo/board/board.c b/bsp/stm32/stm32f767-st-nucleo/board/board.c
index 0c63bfe489..4e00f26886 100644
--- a/bsp/stm32/stm32f767-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32f767-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -21,14 +21,14 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
-  /**Configure LSE Drive Capability 
+  /**Configure LSE Drive Capability
   */
   HAL_PWR_EnableBkUpAccess();
-  /**Configure the main internal regulator output voltage 
+  /**Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
@@ -42,13 +42,13 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Activate the Over-Drive mode 
+  /**Activate the Over-Drive mode
   */
   if (HAL_PWREx_EnableOverDrive() != HAL_OK)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f767-st-nucleo/board/board.h b/bsp/stm32/stm32f767-st-nucleo/board/board.h
index 1d1e1d1106..1d82defe0d 100644
--- a/bsp/stm32/stm32f767-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32f767-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f767-st-nucleo/board/ports/phy_reset.c b/bsp/stm32/stm32f767-st-nucleo/board/ports/phy_reset.c
index 8a833eec2a..79b8fecc16 100644
--- a/bsp/stm32/stm32f767-st-nucleo/board/ports/phy_reset.c
+++ b/bsp/stm32/stm32f767-st-nucleo/board/ports/phy_reset.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,6 +16,6 @@ void phy_reset(void)
      * The PHY reset pin of NUCLEO-F767ZI is connected to the MCU reset pin,
      * so no additional reset is required.
      */
-    
+
     return ;
 }
diff --git a/bsp/stm32/stm32f769-st-disco/applications/main.c b/bsp/stm32/stm32f769-st-disco/applications/main.c
index 14a2f68f81..396afa994a 100644
--- a/bsp/stm32/stm32f769-st-disco/applications/main.c
+++ b/bsp/stm32/stm32f769-st-disco/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -18,17 +18,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED1 pin mode to output */
     rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED1_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED1_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f769-st-disco/board/board.c b/bsp/stm32/stm32f769-st-disco/board/board.c
index 97bbbe3076..55126435b1 100644
--- a/bsp/stm32/stm32f769-st-disco/board/board.c
+++ b/bsp/stm32/stm32f769-st-disco/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,14 +20,14 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
-  /** Configure LSE Drive Capability 
+  /** Configure LSE Drive Capability
   */
   HAL_PWR_EnableBkUpAccess();
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   __HAL_RCC_PWR_CLK_ENABLE();
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
@@ -42,13 +42,13 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Activate the Over-Drive mode 
+  /** Activate the Over-Drive mode
   */
   if (HAL_PWREx_EnableOverDrive() != HAL_OK)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32f769-st-disco/board/board.h b/bsp/stm32/stm32f769-st-disco/board/board.h
index 85c900e4c8..813dd5b27e 100644
--- a/bsp/stm32/stm32f769-st-disco/board/board.h
+++ b/bsp/stm32/stm32f769-st-disco/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32f769-st-disco/board/ports/phy_reset.c b/bsp/stm32/stm32f769-st-disco/board/ports/phy_reset.c
index ca76f6e337..0a4f3f5216 100644
--- a/bsp/stm32/stm32f769-st-disco/board/ports/phy_reset.c
+++ b/bsp/stm32/stm32f769-st-disco/board/ports/phy_reset.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,6 +16,6 @@ void phy_reset(void)
      * The PHY reset pin of DISCO-F769NI is connected to the MCU reset pin,
      * so no additional reset is required.
      */
-    
+
     return ;
 }
diff --git a/bsp/stm32/stm32g070-st-nucleo/applications/main.c b/bsp/stm32/stm32g070-st-nucleo/applications/main.c
index 8541bd3b9f..a438b9e67d 100644
--- a/bsp/stm32/stm32g070-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32g070-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32g070-st-nucleo/board/Kconfig b/bsp/stm32/stm32g070-st-nucleo/board/Kconfig
index 9f1ce51720..6b9b4a0c14 100644
--- a/bsp/stm32/stm32g070-st-nucleo/board/Kconfig
+++ b/bsp/stm32/stm32g070-st-nucleo/board/Kconfig
@@ -168,7 +168,6 @@ menu "On-chip Peripheral Drivers"
     menuconfig BSP_USING_ONCHIP_RTC
         bool "Enable RTC"
         select RT_USING_RTC
-        select RT_USING_LIBC
         default n
         if BSP_USING_ONCHIP_RTC
             choice
diff --git a/bsp/stm32/stm32g070-st-nucleo/board/board.c b/bsp/stm32/stm32g070-st-nucleo/board/board.c
index 0c907528d0..101f483d27 100644
--- a/bsp/stm32/stm32g070-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32g070-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32g070-st-nucleo/board/board.h b/bsp/stm32/stm32g070-st-nucleo/board/board.h
index f0345a1293..d36387892b 100644
--- a/bsp/stm32/stm32g070-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32g070-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32g070-st-nucleo/board/ports/fal_cfg.h b/bsp/stm32/stm32g070-st-nucleo/board/ports/fal_cfg.h
index ee65e188d9..277b98ba70 100644
--- a/bsp/stm32/stm32g070-st-nucleo/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32g070-st-nucleo/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32g071-st-nucleo/applications/main.c b/bsp/stm32/stm32g071-st-nucleo/applications/main.c
index 8541bd3b9f..a438b9e67d 100644
--- a/bsp/stm32/stm32g071-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32g071-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32g071-st-nucleo/board/board.c b/bsp/stm32/stm32g071-st-nucleo/board/board.c
index 5d634db15e..28d4e56e46 100644
--- a/bsp/stm32/stm32g071-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32g071-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,10 +16,10 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  /**Configure the main internal regulator output voltage 
+  /**Configure the main internal regulator output voltage
   */
   HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
@@ -36,7 +36,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1;
@@ -48,7 +48,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Initializes the peripherals clocks 
+  /**Initializes the peripherals clocks
   */
   PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
   PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
diff --git a/bsp/stm32/stm32g071-st-nucleo/board/board.h b/bsp/stm32/stm32g071-st-nucleo/board/board.h
index f0345a1293..d36387892b 100644
--- a/bsp/stm32/stm32g071-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32g071-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32g071-st-nucleo/board/ports/fal_cfg.h b/bsp/stm32/stm32g071-st-nucleo/board/ports/fal_cfg.h
index ee65e188d9..277b98ba70 100644
--- a/bsp/stm32/stm32g071-st-nucleo/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32g071-st-nucleo/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32g431-st-nucleo/applications/main.c b/bsp/stm32/stm32g431-st-nucleo/applications/main.c
index aad9acb9b9..5524d24935 100644
--- a/bsp/stm32/stm32g431-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32g431-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED2 pin mode to output */
     rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED2_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED2_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32g431-st-nucleo/board/board.c b/bsp/stm32/stm32g431-st-nucleo/board/board.c
index f025a3e234..7aeb088632 100644
--- a/bsp/stm32/stm32g431-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32g431-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,10 +17,10 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
@@ -36,7 +36,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
@@ -49,7 +49,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the peripherals clocks 
+  /** Initializes the peripherals clocks
   */
   PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
   PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
diff --git a/bsp/stm32/stm32g431-st-nucleo/board/board.h b/bsp/stm32/stm32g431-st-nucleo/board/board.h
index 9b91078b0f..6fd0c97890 100644
--- a/bsp/stm32/stm32g431-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32g431-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32h743-atk-apollo/applications/main.c b/bsp/stm32/stm32h743-atk-apollo/applications/main.c
index 19a43a12e6..c52580b1b1 100644
--- a/bsp/stm32/stm32h743-atk-apollo/applications/main.c
+++ b/bsp/stm32/stm32h743-atk-apollo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,16 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
-    /* set LED0 pin mode to output */	
-    rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);	
-	
-    while (count++)
+    /* set LED0 pin mode to output */
+    rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
+
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32h743-atk-apollo/board/Kconfig b/bsp/stm32/stm32h743-atk-apollo/board/Kconfig
index a2065dc17e..88809968fd 100644
--- a/bsp/stm32/stm32h743-atk-apollo/board/Kconfig
+++ b/bsp/stm32/stm32h743-atk-apollo/board/Kconfig
@@ -157,7 +157,6 @@ menu "On-chip Peripheral Drivers"
     menuconfig BSP_USING_ONCHIP_RTC
         bool "Enable RTC"
         select RT_USING_RTC
-        select RT_USING_LIBC
         default n
         if BSP_USING_ONCHIP_RTC
             choice
diff --git a/bsp/stm32/stm32h743-atk-apollo/board/board.c b/bsp/stm32/stm32h743-atk-apollo/board/board.c
index 0ae3016460..a96ed203a7 100644
--- a/bsp/stm32/stm32h743-atk-apollo/board/board.c
+++ b/bsp/stm32/stm32h743-atk-apollo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,22 +16,22 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
-  /** Supply configuration update enable 
+  /** Supply configuration update enable
   */
   HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 
   while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
-  /** Configure LSE Drive Capability 
+  /** Configure LSE Drive Capability
   */
   HAL_PWR_EnableBkUpAccess();
   __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
-  /** Macro to configure the PLL clock source 
+  /** Macro to configure the PLL clock source
   */
   __HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSE);
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
                               |RCC_OSCILLATORTYPE_LSE;
@@ -52,7 +52,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
diff --git a/bsp/stm32/stm32h743-atk-apollo/board/board.h b/bsp/stm32/stm32h743-atk-apollo/board/board.h
index ffb9772ee7..c9ec7a30d9 100644
--- a/bsp/stm32/stm32h743-atk-apollo/board/board.h
+++ b/bsp/stm32/stm32h743-atk-apollo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-#if !defined  (LSI_VALUE) 
+#if !defined  (LSI_VALUE)
   #define LSI_VALUE  ((uint32_t)32000)
 #endif
 
diff --git a/bsp/stm32/stm32h743-atk-apollo/board/drv_mpu.c b/bsp/stm32/stm32h743-atk-apollo/board/drv_mpu.c
index 5f4d8b1b80..929d317afa 100644
--- a/bsp/stm32/stm32h743-atk-apollo/board/drv_mpu.c
+++ b/bsp/stm32/stm32h743-atk-apollo/board/drv_mpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -55,7 +55,7 @@ int mpu_init(void)
     /* Enable CACHE */
     SCB_EnableICache();
     SCB_EnableDCache();
-    
+
     return 0;
 
 }
diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_dcmi.c b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_dcmi.c
index 8a57c37e01..cc170ff945 100644
--- a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_dcmi.c
+++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_dcmi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_dcmi.h b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_dcmi.h
index af519987dd..d40ffc6926 100644
--- a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_dcmi.h
+++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_dcmi.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_ov2640.c b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_ov2640.c
index 0ed9345156..95e5784654 100644
--- a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_ov2640.c
+++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_ov2640.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -38,7 +38,7 @@ struct rt_i2c_bus_device *i2c_bus  = RT_NULL;
 #define JPEG_LINE_SIZE  1 * 1024
 
 static pcf8574_device_t pcf_dev = RT_NULL;
-   
+
 static rt_uint32_t *jpeg_data_buf = RT_NULL;
 static rt_uint32_t JPEG_LINE0_BUF[JPEG_LINE_SIZE];
 static rt_uint32_t JPEG_LINE1_BUF[JPEG_LINE_SIZE];
@@ -454,7 +454,7 @@ rt_uint8_t ov2640_set_image_window_size(rt_uint16_t offx, rt_uint16_t offy, rt_u
    temp|=(offy>>4)&0X70;
    temp|=(hsize>>5)&0X08;
    temp|=(offx>>8)&0X07;
-   write_reg(i2c_bus, 0X55,temp); 
+   write_reg(i2c_bus, 0X55,temp);
    write_reg(i2c_bus, 0X57,(hsize>>2)&0X80);
    write_reg(i2c_bus, 0XE0,0X00);
    return 0;
@@ -550,36 +550,36 @@ int ov2640_pwdn_set(rt_uint8_t sta)
         return -1;
     }
     pcf8574_pin_write(pcf_dev, DCMI_PWDN_IO, sta);
-    
+
     return 0;
 }
 
 void sw_ov2640_mode(void)
-{  
+{
     GPIO_InitTypeDef GPIO_Initure = {0};
-    
+
     ov2640_pwdn_set(0);
-    
-    GPIO_Initure.Pin       = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_11;  
-    GPIO_Initure.Mode      = GPIO_MODE_AF_PP; 
-    GPIO_Initure.Pull      = GPIO_PULLUP;     
-    GPIO_Initure.Speed     = GPIO_SPEED_HIGH; 
-    GPIO_Initure.Alternate = GPIO_AF13_DCMI;    
-    HAL_GPIO_Init(GPIOC,&GPIO_Initure);  
-} 
+
+    GPIO_Initure.Pin       = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_11;
+    GPIO_Initure.Mode      = GPIO_MODE_AF_PP;
+    GPIO_Initure.Pull      = GPIO_PULLUP;
+    GPIO_Initure.Speed     = GPIO_SPEED_HIGH;
+    GPIO_Initure.Alternate = GPIO_AF13_DCMI;
+    HAL_GPIO_Init(GPIOC,&GPIO_Initure);
+}
 
 void sw_sdcard_mode(void)
 {
     GPIO_InitTypeDef GPIO_Initure = {0};
-    
-    ov2640_pwdn_set(1); /* OV2640 Power Down */ 
 
-    GPIO_Initure.Pin       = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_11;  
-    GPIO_Initure.Mode      = GPIO_MODE_AF_PP; 
+    ov2640_pwdn_set(1); /* OV2640 Power Down */
+
+    GPIO_Initure.Pin       = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_11;
+    GPIO_Initure.Mode      = GPIO_MODE_AF_PP;
     GPIO_Initure.Pull      = GPIO_PULLUP;
-    GPIO_Initure.Speed     = GPIO_SPEED_HIGH; 
-    GPIO_Initure.Alternate = GPIO_AF12_SDMMC1;   
-    HAL_GPIO_Init(GPIOC, &GPIO_Initure);   
+    GPIO_Initure.Speed     = GPIO_SPEED_HIGH;
+    GPIO_Initure.Alternate = GPIO_AF12_SDMMC1;
+    HAL_GPIO_Init(GPIOC, &GPIO_Initure);
 }
 
 int rt_ov2640_init(void)
@@ -587,7 +587,7 @@ int rt_ov2640_init(void)
     rt_uint16_t i = 0;
     rt_err_t result = RT_EOK;
     rt_device_t dcmi_dev = RT_NULL;
-    
+
     sw_ov2640_mode();
     pcf_dev = pcf8574_init("i2c1", RT_NULL);
     if (pcf_dev == RT_NULL)
@@ -595,17 +595,17 @@ int rt_ov2640_init(void)
         LOG_E("can't find pcf8574, please check it");
         return -RT_ERROR;
     }
-    
+
     ov2640_pwdn_set(0);
-	rt_thread_delay(20);
-    
+    rt_thread_delay(20);
+
     /* ov2640 hard reset */
     rt_pin_mode(RESET_PIN, PIN_MODE_OUTPUT);
     rt_pin_write(RESET_PIN, PIN_LOW);
     rt_thread_delay(20);
     rt_pin_write(RESET_PIN, PIN_HIGH);
     rt_thread_delay(20);
-    
+
     i2c_bus = rt_i2c_bus_device_find(I2C_NAME);
     if (i2c_bus == RT_NULL)
     {
@@ -687,7 +687,7 @@ int camera_sample(int argc, char **argv)
        rt_kprintf("camera_sample file.jpg\n");
        return -1;
    }
-   
+
    sw_ov2640_mode();
    DCMI_Start();
 
diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_ov2640.h b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_ov2640.h
index 4ff948b0c6..e85e559421 100644
--- a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_ov2640.h
+++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_ov2640.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_qspi_flash.c
index 5cabc9d4d2..72e589aea4 100644
--- a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_qspi_flash.c
+++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_qspi_flash.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-11-27     zylx         first version
  */
- 
+
 #include 
 #include 
 #include 
@@ -63,7 +63,7 @@ void w25qxx_enter_qspi_mode(struct rt_qspi_device *device)
 static int rt_hw_qspi_flash_with_sfud_init(void)
 {
     stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, w25qxx_enter_qspi_mode, RT_NULL);
-    
+
     /* init W25Q256 */
     if (RT_NULL == rt_sfud_flash_probe("W25Q256", "qspi10"))
     {
diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_sdio.c b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_sdio.c
index 07776296f0..a2789227a6 100644
--- a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_sdio.c
+++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_sdio.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_sdio.h b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_sdio.h
index 63f193e848..276064ddad 100644
--- a/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_sdio.h
+++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/drv_sdio.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/fal_cfg.h b/bsp/stm32/stm32h743-atk-apollo/board/ports/fal_cfg.h
index 64c244f095..ca0c7a01b9 100644
--- a/bsp/stm32/stm32h743-atk-apollo/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/lcd_port.h b/bsp/stm32/stm32h743-atk-apollo/board/ports/lcd_port.h
index ca894bb045..156ba2e2cf 100644
--- a/bsp/stm32/stm32h743-atk-apollo/board/ports/lcd_port.h
+++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/lcd_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32h743-atk-apollo/board/ports/sdram_port.h b/bsp/stm32/stm32h743-atk-apollo/board/ports/sdram_port.h
index 5784f79036..50804561eb 100644
--- a/bsp/stm32/stm32h743-atk-apollo/board/ports/sdram_port.h
+++ b/bsp/stm32/stm32h743-atk-apollo/board/ports/sdram_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32h743-st-nucleo/applications/main.c b/bsp/stm32/stm32h743-st-nucleo/applications/main.c
index 2a4d35d4d8..ef1884d3bc 100644
--- a/bsp/stm32/stm32h743-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32h743-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,16 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32h743-st-nucleo/board/board.c b/bsp/stm32/stm32h743-st-nucleo/board/board.c
index dc2e79d04f..b5a5a4245d 100644
--- a/bsp/stm32/stm32h743-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32h743-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32h743-st-nucleo/board/board.h b/bsp/stm32/stm32h743-st-nucleo/board/board.h
index 72d84ff29d..32eb25f147 100644
--- a/bsp/stm32/stm32h743-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32h743-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32h747-st-discovery/applications/main.c b/bsp/stm32/stm32h747-st-discovery/applications/main.c
index 9840fc6618..2a91e93091 100644
--- a/bsp/stm32/stm32h747-st-discovery/applications/main.c
+++ b/bsp/stm32/stm32h747-st-discovery/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,16 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32h747-st-discovery/board/board.c b/bsp/stm32/stm32h747-st-discovery/board/board.c
index a7af6b13f8..73f2013e66 100644
--- a/bsp/stm32/stm32h747-st-discovery/board/board.c
+++ b/bsp/stm32/stm32h747-st-discovery/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32h747-st-discovery/board/board.h b/bsp/stm32/stm32h747-st-discovery/board/board.h
index c3441d01b1..85196a7664 100644
--- a/bsp/stm32/stm32h747-st-discovery/board/board.h
+++ b/bsp/stm32/stm32h747-st-discovery/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32h750-armfly-h7-tool/applications/main.c b/bsp/stm32/stm32h750-armfly-h7-tool/applications/main.c
index 73691fa783..90a52049e4 100644
--- a/bsp/stm32/stm32h750-armfly-h7-tool/applications/main.c
+++ b/bsp/stm32/stm32h750-armfly-h7-tool/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,16 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32h750-armfly-h7-tool/board/board.c b/bsp/stm32/stm32h750-armfly-h7-tool/board/board.c
index 7783d407a8..6426138e1e 100644
--- a/bsp/stm32/stm32h750-armfly-h7-tool/board/board.c
+++ b/bsp/stm32/stm32h750-armfly-h7-tool/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,18 +20,18 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
 
-  /** Supply configuration update enable 
+  /** Supply configuration update enable
   */
   HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 
   while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
-  /** Macro to configure the PLL clock source 
+  /** Macro to configure the PLL clock source
   */
   __HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSE);
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -50,7 +50,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
diff --git a/bsp/stm32/stm32h750-armfly-h7-tool/board/board.h b/bsp/stm32/stm32h750-armfly-h7-tool/board/board.h
index a0455aec76..b41ed17e43 100644
--- a/bsp/stm32/stm32h750-armfly-h7-tool/board/board.h
+++ b/bsp/stm32/stm32h750-armfly-h7-tool/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/nrf5x/libraries/templates/nrf52x/.config b/bsp/stm32/stm32h750-artpi-h750/.config
similarity index 81%
rename from bsp/nrf5x/libraries/templates/nrf52x/.config
rename to bsp/stm32/stm32h750-artpi-h750/.config
index ae80206940..c31157512a 100644
--- a/bsp/nrf5x/libraries/templates/nrf52x/.config
+++ b/bsp/stm32/stm32h750-artpi-h750/.config
@@ -14,15 +14,13 @@ CONFIG_RT_ALIGN_SIZE=4
 CONFIG_RT_THREAD_PRIORITY_32=y
 # CONFIG_RT_THREAD_PRIORITY_256 is not set
 CONFIG_RT_THREAD_PRIORITY_MAX=32
-CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_TICK_PER_SECOND=1000
 CONFIG_RT_USING_OVERFLOW_CHECK=y
 CONFIG_RT_USING_HOOK=y
 CONFIG_RT_USING_IDLE_HOOK=y
 CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
 CONFIG_IDLE_THREAD_STACK_SIZE=256
-CONFIG_RT_USING_TIMER_SOFT=y
-CONFIG_RT_TIMER_THREAD_PRIO=4
-CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+# CONFIG_RT_USING_TIMER_SOFT is not set
 CONFIG_RT_DEBUG=y
 # CONFIG_RT_DEBUG_COLOR is not set
 # CONFIG_RT_DEBUG_INIT_CONFIG is not set
@@ -65,16 +63,21 @@ CONFIG_RT_USING_DEVICE=y
 # CONFIG_RT_USING_INTERRUPT_INFO is not set
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
-CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart4"
 CONFIG_RT_VER_NUM=0x40003
-# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_ARM=y
+CONFIG_RT_USING_CPU_FFS=y
+CONFIG_ARCH_ARM_CORTEX_M=y
+CONFIG_ARCH_ARM_CORTEX_M7=y
 # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
 
 #
 # RT-Thread Components
 #
 CONFIG_RT_USING_COMPONENTS_INIT=y
-# CONFIG_RT_USING_USER_MAIN is not set
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
 
 #
 # C++ features
@@ -112,14 +115,16 @@ CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_PIPE_BUFSZ=512
 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
 CONFIG_RT_USING_SERIAL=y
-CONFIG_RT_SERIAL_USING_DMA=y
+# CONFIG_RT_SERIAL_USING_DMA is not set
 CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_USING_HWTIMER is not set
 # CONFIG_RT_USING_CPUTIME is not set
 # CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
 CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
 # CONFIG_RT_USING_PWM is not set
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
@@ -145,9 +150,9 @@ CONFIG_RT_USING_PIN=y
 #
 # POSIX layer and C standard library
 #
-CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_LIBC is not set
 # CONFIG_RT_USING_PTHREADS is not set
-# CONFIG_RT_USING_MODULE is not set
+CONFIG_RT_LIBC_USING_TIME=y
 
 #
 # Network
@@ -184,6 +189,7 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_RT_USING_RYM is not set
 # CONFIG_RT_USING_ULOG is not set
 # CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_LWP is not set
 
 #
 # RT-Thread online packages
@@ -192,12 +198,15 @@ CONFIG_RT_USING_LIBC=y
 #
 # IoT - internet of things
 #
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
 # CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
 # CONFIG_PKG_USING_WEBCLIENT is not set
 # CONFIG_PKG_USING_WEBNET is not set
 # CONFIG_PKG_USING_MONGOOSE is not set
 # CONFIG_PKG_USING_MYMQTT is not set
 # CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
 # CONFIG_PKG_USING_WEBTERMINAL is not set
 # CONFIG_PKG_USING_CJSON is not set
 # CONFIG_PKG_USING_JSMN is not set
@@ -224,6 +233,7 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_COAP is not set
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
 # CONFIG_PKG_USING_PPP_DEVICE is not set
 # CONFIG_PKG_USING_AT_DEVICE is not set
 # CONFIG_PKG_USING_ATSRV_SOCKET is not set
@@ -236,9 +246,10 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_GAGENT_CLOUD is not set
 # CONFIG_PKG_USING_ALI_IOTKIT is not set
 # CONFIG_PKG_USING_AZURE is not set
-# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
 # CONFIG_PKG_USING_JIOT-C-SDK is not set
 # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
 # CONFIG_PKG_USING_NIMBLE is not set
 # CONFIG_PKG_USING_OTA_DOWNLOADER is not set
 # CONFIG_PKG_USING_IPMSG is not set
@@ -257,6 +268,9 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_CAPNP is not set
 # CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
 # CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PDULIB is not set
 
 #
 # security packages
@@ -265,6 +279,7 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_libsodium is not set
 # CONFIG_PKG_USING_TINYCRYPT is not set
 # CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
 
 #
 # language packages
@@ -299,16 +314,21 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
 # CONFIG_PKG_USING_LUNAR_CALENDAR is not set
 # CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
 
 #
 # system packages
 #
 # CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_PERSIMMON is not set
 # CONFIG_PKG_USING_CAIRO is not set
 # CONFIG_PKG_USING_PIXMAN is not set
 # CONFIG_PKG_USING_LWEXT4 is not set
 # CONFIG_PKG_USING_PARTITION is not set
 # CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_FLASHDB is not set
 # CONFIG_PKG_USING_SQLITE is not set
 # CONFIG_PKG_USING_RTI is not set
 # CONFIG_PKG_USING_LITTLEVGL2RTT is not set
@@ -321,6 +341,10 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_SYSWATCH is not set
 # CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
 # CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
 
 #
 # peripheral libraries and drivers
@@ -338,6 +362,9 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_SIGNAL_LED is not set
 # CONFIG_PKG_USING_LEDBLINK is not set
 # CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
 # CONFIG_PKG_USING_WM_LIBRARIES is not set
 # CONFIG_PKG_USING_KENDRYTE_SDK is not set
 # CONFIG_PKG_USING_INFRARED is not set
@@ -355,8 +382,21 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_RPLIDAR is not set
 # CONFIG_PKG_USING_AS608 is not set
 # CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
 # CONFIG_PKG_USING_EMBARC_BSP is not set
 # CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
 
 #
 # miscellaneous packages
@@ -393,17 +433,34 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_VT100 is not set
 # CONFIG_PKG_USING_ULAPACK is not set
 # CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+CONFIG_SOC_FAMILY_STM32=y
+CONFIG_SOC_SERIES_STM32H7=y
 
 #
 # Hardware Drivers Config
 #
-CONFIG_SOC_NRF52832=y
+CONFIG_SOC_STM32H750XB=y
 
 #
 # Onboard Peripheral Drivers
 #
+# CONFIG_BSP_USING_QSPI_FLASH is not set
 
 #
 # On-chip Peripheral Drivers
 #
+CONFIG_BSP_USING_GPIO=y
 CONFIG_BSP_USING_UART=y
+CONFIG_BSP_USING_UART3=y
+CONFIG_BSP_USING_UART4=y
+# CONFIG_BSP_USING_SDIO is not set
+# CONFIG_BSP_USING_CRC is not set
+# CONFIG_BSP_USING_RNG is not set
+# CONFIG_BSP_USING_UDID is not set
+
+#
+# Board extended module Drivers
+#
diff --git a/bsp/stm32/stm32f103-mini-system/.gitignore b/bsp/stm32/stm32h750-artpi-h750/.gitignore
similarity index 100%
rename from bsp/stm32/stm32f103-mini-system/.gitignore
rename to bsp/stm32/stm32h750-artpi-h750/.gitignore
diff --git a/bsp/stm32/stm32h750-artpi-h750/EventRecorderStub.scvd b/bsp/stm32/stm32h750-artpi-h750/EventRecorderStub.scvd
new file mode 100644
index 0000000000..2956b29683
--- /dev/null
+++ b/bsp/stm32/stm32h750-artpi-h750/EventRecorderStub.scvd
@@ -0,0 +1,9 @@
+
+
+
+
+       
+  
+  
+
+
diff --git a/bsp/stm32/stm32f103-mini-system/Kconfig b/bsp/stm32/stm32h750-artpi-h750/Kconfig
similarity index 99%
rename from bsp/stm32/stm32f103-mini-system/Kconfig
rename to bsp/stm32/stm32h750-artpi-h750/Kconfig
index 7a400db91f..8cbc7b71a8 100644
--- a/bsp/stm32/stm32f103-mini-system/Kconfig
+++ b/bsp/stm32/stm32h750-artpi-h750/Kconfig
@@ -14,9 +14,8 @@ config PKGS_DIR
     string
     option env="PKGS_ROOT"
     default "packages"
-
+ 
 source "$RTT_DIR/Kconfig"
 source "$PKGS_DIR/Kconfig"
 source "../libraries/Kconfig"
 source "board/Kconfig"
-
diff --git a/bsp/stm32/stm32h750-artpi-h750/README.md b/bsp/stm32/stm32h750-artpi-h750/README.md
new file mode 100644
index 0000000000..3c598c2845
--- /dev/null
+++ b/bsp/stm32/stm32h750-artpi-h750/README.md
@@ -0,0 +1,128 @@
+# STM32H750-artpi 开发板 BSP 说明
+
+## 简介
+
+本文档 为 STM32H750-ART-PI 开发板提供的 BSP (板级支持包) 说明。
+
+主要内容如下：
+
+- 开发板资源介绍
+- BSP 快速上手
+- 进阶使用方法
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
+
+## 开发板介绍
+
+STM32H750 是RTTHREAD推出的一款基于 ARM Cortex-M7 内核的开发板，最高主频为 480Mhz，该开发板具有丰富的板载资源，可以充分发挥 STM32H750 的芯片性能。
+
+开发板外观如下图所示：
+
+![board](figures/board.jpg)
+
+该开发板常用 **板载资源** 如下：
+
+- MCU：STM32H750，主频 480MHz，128KB FLASH, 1MB RAM
+- 常用接口：USB 转串口、USB OTG、RGB888等
+- 调试接口，标准 ST-LINK
+
+开发板更多详细信息请参考[H750-ART-PI](https://www.rt-thread.org/product/153.html)。
+
+官方仓库[sdk-bsp-stm32h750-realthread-artpi](https://github.com/RT-Thread-Studio/sdk-bsp-stm32h750-realthread-artpi)
+
+官方主页 [ART-PI](https://art-pi.gitee.io/website)
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **板载外设** | **支持情况** | **备注**                  |
+| :----------- | :----------: | :------------------------ |
+| LED          |    待支持    | 一个红灯，一个蓝灯        |
+| BUTTON       |    待支持    | 一个用户可控button        |
+| QSPI  FLASH  |    待支持    | 1MB w25q64  QSPI接口FLASH |
+| SPI  FLASH   |    待支持    | 2MB w25q128 SPI FLASH     |
+| SDCARD       |    待支持    | sdcard接口                |
+| AP6212       |    待支持    | WIFI & BLUETOOTH          |
+| LCD RG888    |    待支持    | 显示屏接口                |
+| **片上外设** | **支持情况** | **备注**                  |
+| GPIO         |     支持     |                           |
+| UART         |     支持     | UART4 UART3               |
+| SPI          |     支持     | SPI                       |
+| QSPI         |     支持     |                           |
+|              |              |                           |
+
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+
+    本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+
+- 进阶使用
+
+    本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+
+### 快速上手
+
+本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+#### 硬件连接
+
+使用数据线连接开发板到 PC，将 TVCC 接到 3.3V。使用 usb 转串口工具连接 TTLRX 和 TTLTX。
+
+#### 编译下载
+
+双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
+
+> 工程默认配置使用 ST_LINK 仿真器下载程序，在通过 ST_LINK 连接开发板的基础上，点击下载按钮即可下载程序到开发板
+
+#### 运行结果
+
+下载程序成功之后，系统会自动运行，LED闪烁。
+
+连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
+
+```bash
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.2 build Oct 25 2019
+ 2006 - 2019 Copyright by rt-thread team
+msh >
+```
+### 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 串口1 的功能，如果需使用更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。
+
+本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。
+
+## 注意事项
+
+- 调试串口为串口4 映射说明
+
+    PI9  ------> USART4_RX
+
+    PA0 ------> USART4_TX 
+
+## 联系人信息
+
+ART-Pi 是一个开源创意硬件平台，期待有更多的小伙伴能一起发现更多的乐趣，在使用过程中若您有任何的想法和建议，建议您通过以下方式来联系到我们。
+
+RT-Thread [社区论坛](https://club.rt-thread.org/)。
+
+-  ART-Pi 官方交流 QQ 群(1016035998)。
+
+## 贡献代码
+
+如果您对 ART-Pi 感兴趣，并有一些好玩的项目愿意与大家分享，欢迎给我们贡献代码，您可以参考 [ART-Pi 代码贡献手册](https://github.com/RT-Thread-Studio/sdk-bsp-stm32h750-realthread-artpi/blob/master/documents/UM5004-RT-Thread ART-Pi 代码贡献手册.md) 。
\ No newline at end of file
diff --git a/bsp/stm32/stm32h750-artpi-h750/SConscript b/bsp/stm32/stm32h750-artpi-h750/SConscript
new file mode 100644
index 0000000000..c7ef7659ec
--- /dev/null
+++ b/bsp/stm32/stm32h750-artpi-h750/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/stm32/stm32f103-mini-system/SConstruct b/bsp/stm32/stm32h750-artpi-h750/SConstruct
similarity index 98%
rename from bsp/stm32/stm32f103-mini-system/SConstruct
rename to bsp/stm32/stm32h750-artpi-h750/SConstruct
index 1a9f419db5..48974d990f 100644
--- a/bsp/stm32/stm32f103-mini-system/SConstruct
+++ b/bsp/stm32/stm32h750-artpi-h750/SConstruct
@@ -47,13 +47,13 @@ Export('SDK_LIB')
 # prepare building environment
 objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
 
-stm32_library = 'STM32F1xx_HAL'
+stm32_library = 'STM32H7xx_HAL'
 rtconfig.BSP_LIBRARY_TYPE = stm32_library
 
-# include libraries
+# include drivers
 objs.extend(SConscript(os.path.join(libraries_path_prefix, stm32_library, 'SConscript')))
 
-# include drivers
+# include libraries
 objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
 
 # make a building
diff --git a/bsp/stm32/stm32h750-artpi-h750/applications/SConscript b/bsp/stm32/stm32h750-artpi-h750/applications/SConscript
new file mode 100644
index 0000000000..10deb3f896
--- /dev/null
+++ b/bsp/stm32/stm32h750-artpi-h750/applications/SConscript
@@ -0,0 +1,12 @@
+import rtconfig
+from building import *
+
+cwd     = GetCurrentDir()
+CPPPATH = [cwd, str(Dir('#'))]
+src     = Split("""
+main.c
+""")
+
+group = DefineGroup('Applications', src, depend = [''])
+
+Return('group')
diff --git a/bsp/stm32/stm32f103-mini-system/applications/main.c b/bsp/stm32/stm32h750-artpi-h750/applications/main.c
similarity index 74%
rename from bsp/stm32/stm32f103-mini-system/applications/main.c
rename to bsp/stm32/stm32h750-artpi-h750/applications/main.c
index c5fa5a5958..d4b0bb98a6 100644
--- a/bsp/stm32/stm32f103-mini-system/applications/main.c
+++ b/bsp/stm32/stm32h750-artpi-h750/applications/main.c
@@ -5,29 +5,26 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2019-03-08     obito0   first version
+ * 2021-03-17     supperthomas first version
  */
 
 #include 
 #include 
 #include 
 
-/* defined the LED0 pin: PC13 */
-#define LED0_PIN    GET_PIN(C, 13)
+/* defined the LED0 pin: PI8 */
+#define LED0_PIN    GET_PIN(I, 8)
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Inc/main.h b/bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/Core/Inc/main.h
similarity index 95%
rename from bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Inc/main.h
rename to bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/Core/Inc/main.h
index 75cb6f9a15..4677beb2d9 100644
--- a/bsp/stm32/stm32f103-mini-system/board/CubeMX_Config/Inc/main.h
+++ b/bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/Core/Inc/main.h
@@ -7,7 +7,7 @@
   ******************************************************************************
   * @attention
   *
-  * 
© Copyright (c) 2019 STMicroelectronics.
+  * 
© Copyright (c) 2020 STMicroelectronics.
   * All rights reserved.

   *
   * This software component is licensed by ST under BSD 3-Clause license,
@@ -28,7 +28,7 @@ extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal.h"
+#include "stm32h7xx_hal.h"
 
 /* Private includes ----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
diff --git a/bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/Core/Inc/stm32h7xx_hal_conf.h b/bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/Core/Inc/stm32h7xx_hal_conf.h
new file mode 100644
index 0000000000..7f31669688
--- /dev/null
+++ b/bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/Core/Inc/stm32h7xx_hal_conf.h
@@ -0,0 +1,511 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * 
© Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.

+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_CONF_H
+#define STM32H7xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+
+  /* #define HAL_ADC_MODULE_ENABLED   */
+/* #define HAL_FDCAN_MODULE_ENABLED   */
+/* #define HAL_FMAC_MODULE_ENABLED   */
+/* #define HAL_CEC_MODULE_ENABLED   */
+/* #define HAL_COMP_MODULE_ENABLED   */
+/* #define HAL_CORDIC_MODULE_ENABLED   */
+/* #define HAL_CRC_MODULE_ENABLED   */
+/* #define HAL_CRYP_MODULE_ENABLED   */
+/* #define HAL_DAC_MODULE_ENABLED   */
+/* #define HAL_DCMI_MODULE_ENABLED   */
+/* #define HAL_DMA2D_MODULE_ENABLED   */
+/* #define HAL_ETH_MODULE_ENABLED   */
+/* #define HAL_NAND_MODULE_ENABLED   */
+/* #define HAL_NOR_MODULE_ENABLED   */
+/* #define HAL_OTFDEC_MODULE_ENABLED   */
+/* #define HAL_SRAM_MODULE_ENABLED   */
+/* #define HAL_SDRAM_MODULE_ENABLED   */
+/* #define HAL_HASH_MODULE_ENABLED   */
+/* #define HAL_HRTIM_MODULE_ENABLED   */
+/* #define HAL_HSEM_MODULE_ENABLED   */
+/* #define HAL_GFXMMU_MODULE_ENABLED   */
+/* #define HAL_JPEG_MODULE_ENABLED   */
+/* #define HAL_OPAMP_MODULE_ENABLED   */
+/* #define HAL_OSPI_MODULE_ENABLED   */
+/* #define HAL_OSPI_MODULE_ENABLED   */
+/* #define HAL_I2S_MODULE_ENABLED   */
+/* #define HAL_SMBUS_MODULE_ENABLED   */
+/* #define HAL_IWDG_MODULE_ENABLED   */
+/* #define HAL_LPTIM_MODULE_ENABLED   */
+/* #define HAL_LTDC_MODULE_ENABLED   */
+/* #define HAL_QSPI_MODULE_ENABLED   */
+/* #define HAL_RNG_MODULE_ENABLED   */
+/* #define HAL_RTC_MODULE_ENABLED   */
+/* #define HAL_SAI_MODULE_ENABLED   */
+/* #define HAL_SD_MODULE_ENABLED   */
+/* #define HAL_MMC_MODULE_ENABLED   */
+/* #define HAL_SPDIFRX_MODULE_ENABLED   */
+/* #define HAL_SPI_MODULE_ENABLED   */
+/* #define HAL_SWPMI_MODULE_ENABLED   */
+/* #define HAL_TIM_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED   */
+/* #define HAL_IRDA_MODULE_ENABLED   */
+/* #define HAL_SMARTCARD_MODULE_ENABLED   */
+/* #define HAL_WWDG_MODULE_ENABLED   */
+/* #define HAL_PCD_MODULE_ENABLED   */
+/* #define HAL_HCD_MODULE_ENABLED   */
+/* #define HAL_DFSDM_MODULE_ENABLED   */
+/* #define HAL_DSI_MODULE_ENABLED   */
+/* #define HAL_JPEG_MODULE_ENABLED   */
+/* #define HAL_MDIOS_MODULE_ENABLED   */
+/* #define HAL_PSSI_MODULE_ENABLED   */
+/* #define HAL_DTS_MODULE_ENABLED   */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_MDMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_HSEM_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal  oscillator (CSI) default value.
+  *        This value is the default CSI value after Reset.
+  */
+#if !defined  (CSI_VALUE)
+  #define CSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+#if !defined  (LSI_VALUE)
+  #define LSI_VALUE  (32000UL)              /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                              The real value may vary depending on the variations
+                                              in voltage and temperature.*/
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the External clock in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            ((uint32_t)0U) /*!< tick interrupt priority */
+#define  USE_RTOS                     0U
+#define  USE_SD_TRANSCEIVER           0U               /*!< use uSD Transceiver */
+#define  USE_SPI_CRC	              0U               /*!< use CRC in SPI */
+
+#define  USE_HAL_ADC_REGISTER_CALLBACKS     0U /* ADC register callback disabled     */
+#define  USE_HAL_CEC_REGISTER_CALLBACKS     0U /* CEC register callback disabled     */
+#define  USE_HAL_COMP_REGISTER_CALLBACKS    0U /* COMP register callback disabled    */
+#define  USE_HAL_CORDIC_REGISTER_CALLBACKS  0U /* CORDIC register callback disabled  */
+#define  USE_HAL_CRYP_REGISTER_CALLBACKS    0U /* CRYP register callback disabled    */
+#define  USE_HAL_DAC_REGISTER_CALLBACKS     0U /* DAC register callback disabled     */
+#define  USE_HAL_DCMI_REGISTER_CALLBACKS    0U /* DCMI register callback disabled    */
+#define  USE_HAL_DFSDM_REGISTER_CALLBACKS   0U /* DFSDM register callback disabled   */
+#define  USE_HAL_DMA2D_REGISTER_CALLBACKS   0U /* DMA2D register callback disabled   */
+#define  USE_HAL_DSI_REGISTER_CALLBACKS     0U /* DSI register callback disabled     */
+#define  USE_HAL_DTS_REGISTER_CALLBACKS     0U /* DTS register callback disabled     */
+#define  USE_HAL_ETH_REGISTER_CALLBACKS     0U /* ETH register callback disabled     */
+#define  USE_HAL_FDCAN_REGISTER_CALLBACKS   0U /* FDCAN register callback disabled   */
+#define  USE_HAL_FMAC_REGISTER_CALLBACKS    0U /* FMAC register callback disabled  */
+#define  USE_HAL_NAND_REGISTER_CALLBACKS    0U /* NAND register callback disabled    */
+#define  USE_HAL_NOR_REGISTER_CALLBACKS     0U /* NOR register callback disabled     */
+#define  USE_HAL_SDRAM_REGISTER_CALLBACKS   0U /* SDRAM register callback disabled   */
+#define  USE_HAL_SRAM_REGISTER_CALLBACKS    0U /* SRAM register callback disabled    */
+#define  USE_HAL_HASH_REGISTER_CALLBACKS    0U /* HASH register callback disabled    */
+#define  USE_HAL_HCD_REGISTER_CALLBACKS     0U /* HCD register callback disabled     */
+#define  USE_HAL_GFXMMU_REGISTER_CALLBACKS  0U /* GFXMMU register callback disabled  */
+#define  USE_HAL_HRTIM_REGISTER_CALLBACKS   0U /* HRTIM register callback disabled   */
+#define  USE_HAL_I2C_REGISTER_CALLBACKS     0U /* I2C register callback disabled     */
+#define  USE_HAL_I2S_REGISTER_CALLBACKS     0U /* I2S register callback disabled     */
+#define  USE_HAL_IRDA_REGISTER_CALLBACKS    0U /* IRDA register callback disabled    */
+#define  USE_HAL_JPEG_REGISTER_CALLBACKS    0U /* JPEG register callback disabled    */
+#define  USE_HAL_LPTIM_REGISTER_CALLBACKS   0U /* LPTIM register callback disabled   */
+#define  USE_HAL_LTDC_REGISTER_CALLBACKS    0U /* LTDC register callback disabled    */
+#define  USE_HAL_MDIOS_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
+#define  USE_HAL_MMC_REGISTER_CALLBACKS     0U /* MMC register callback disabled     */
+#define  USE_HAL_OPAMP_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
+#define  USE_HAL_OSPI_REGISTER_CALLBACKS    0U /* OSPI register callback disabled    */
+#define  USE_HAL_OTFDEC_REGISTER_CALLBACKS  0U /* OTFDEC register callback disabled  */
+#define  USE_HAL_PCD_REGISTER_CALLBACKS     0U /* PCD register callback disabled     */
+#define  USE_HAL_QSPI_REGISTER_CALLBACKS    0U /* QSPI register callback disabled    */
+#define  USE_HAL_RNG_REGISTER_CALLBACKS     0U /* RNG register callback disabled     */
+#define  USE_HAL_RTC_REGISTER_CALLBACKS     0U /* RTC register callback disabled     */
+#define  USE_HAL_SAI_REGISTER_CALLBACKS     0U /* SAI register callback disabled     */
+#define  USE_HAL_SD_REGISTER_CALLBACKS      0U /* SD register callback disabled      */
+#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS  0U /* SMARTCARD register callback disabled */
+#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
+#define  USE_HAL_SMBUS_REGISTER_CALLBACKS   0U /* SMBUS register callback disabled   */
+#define  USE_HAL_SPI_REGISTER_CALLBACKS     0U /* SPI register callback disabled     */
+#define  USE_HAL_SWPMI_REGISTER_CALLBACKS   0U /* SWPMI register callback disabled   */
+#define  USE_HAL_TIM_REGISTER_CALLBACKS     0U /* TIM register callback disabled     */
+#define  USE_HAL_UART_REGISTER_CALLBACKS    0U /* UART register callback disabled    */
+#define  USE_HAL_USART_REGISTER_CALLBACKS   0U /* USART register callback disabled   */
+#define  USE_HAL_WWDG_REGISTER_CALLBACKS    0U /* WWDG register callback disabled    */
+
+/* ########################### Ethernet Configuration ######################### */
+#define ETH_TX_DESC_CNT         4  /* number of Ethernet Tx DMA descriptors */
+#define ETH_RX_DESC_CNT         4  /* number of Ethernet Rx DMA descriptors */
+
+#define ETH_MAC_ADDR0    ((uint8_t)0x02)
+#define ETH_MAC_ADDR1    ((uint8_t)0x00)
+#define ETH_MAC_ADDR2    ((uint8_t)0x00)
+#define ETH_MAC_ADDR3    ((uint8_t)0x00)
+#define ETH_MAC_ADDR4    ((uint8_t)0x00)
+#define ETH_MAC_ADDR5    ((uint8_t)0x00)
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32h7xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32h7xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32h7xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_MDMA_MODULE_ENABLED
+ #include "stm32h7xx_hal_mdma.h"
+#endif /* HAL_MDMA_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+  #include "stm32h7xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32h7xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32h7xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+  #include "stm32h7xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+  #include "stm32h7xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32h7xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32h7xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32h7xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32h7xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+  #include "stm32h7xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+  #include "stm32h7xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32h7xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORDIC_MODULE_ENABLED
+   #include "stm32h7xx_hal_cordic.h"
+#endif /* HAL_CORDIC_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32h7xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32h7xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32h7xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32h7xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_FMAC_MODULE_ENABLED
+  #include "stm32h7xx_hal_fmac.h"
+#endif /* HAL_FMAC_MODULE_ENABLED */
+
+#ifdef HAL_GFXMMU_MODULE_ENABLED
+  #include "stm32h7xx_hal_gfxmmu.h"
+#endif /* HAL_GFXMMU_MODULE_ENABLED */
+
+#ifdef HAL_HRTIM_MODULE_ENABLED
+  #include "stm32h7xx_hal_hrtim.h"
+#endif /* HAL_HRTIM_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32h7xx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32h7xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32h7xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32h7xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32h7xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32h7xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32h7xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_JPEG_MODULE_ENABLED
+ #include "stm32h7xx_hal_jpeg.h"
+#endif /* HAL_JPEG_MODULE_ENABLED */
+
+#ifdef HAL_MDIOS_MODULE_ENABLED
+ #include "stm32h7xx_hal_mdios.h"
+#endif /* HAL_MDIOS_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32h7xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32h7xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+#include "stm32h7xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+#include "stm32h7xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+  #include "stm32h7xx_hal_ospi.h"
+#endif /* HAL_OSPI_MODULE_ENABLED */
+
+#ifdef HAL_OTFDEC_MODULE_ENABLED
+#include "stm32h7xx_hal_otfdec.h"
+#endif /* HAL_OTFDEC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32h7xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32h7xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RAMECC_MODULE_ENABLED
+ #include "stm32h7xx_hal_ramecc.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32h7xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32h7xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32h7xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32h7xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+ #include "stm32h7xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32h7xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32h7xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_SWPMI_MODULE_ENABLED
+ #include "stm32h7xx_hal_swpmi.h"
+#endif /* HAL_SWPMI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32h7xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32h7xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32h7xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32h7xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32h7xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32h7xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32h7xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32h7xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32h7xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_PSSI_MODULE_ENABLED
+  #include "stm32h7xx_hal_pssi.h"
+#endif /* HAL_PSSI_MODULE_ENABLED */
+
+#ifdef HAL_DTS_MODULE_ENABLED
+  #include "stm32h7xx_hal_dts.h"
+#endif /* HAL_DTS_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/Core/Src/stm32h7xx_hal_msp.c b/bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/Core/Src/stm32h7xx_hal_msp.c
new file mode 100644
index 0000000000..77a19bb14b
--- /dev/null
+++ b/bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/Core/Src/stm32h7xx_hal_msp.c
@@ -0,0 +1,226 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : stm32h7xx_hal_msp.c
+  * Description        : This file provides code for the MSP Initialization
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * 
© Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.

+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief UART MSP Initialization
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(huart->Instance==UART4)
+  {
+  /* USER CODE BEGIN UART4_MspInit 0 */
+
+  /* USER CODE END UART4_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_UART4_CLK_ENABLE();
+
+    __HAL_RCC_GPIOI_CLK_ENABLE();
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**UART4 GPIO Configuration
+    PI9     ------> UART4_RX
+    PA0     ------> UART4_TX
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_9;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF8_UART4;
+    HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_0;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF8_UART4;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    /* UART4 interrupt Init */
+    HAL_NVIC_SetPriority(UART4_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(UART4_IRQn);
+  /* USER CODE BEGIN UART4_MspInit 1 */
+
+  /* USER CODE END UART4_MspInit 1 */
+  }
+  else if(huart->Instance==USART3)
+  {
+  /* USER CODE BEGIN USART3_MspInit 0 */
+
+  /* USER CODE END USART3_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_USART3_CLK_ENABLE();
+
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_GPIOD_CLK_ENABLE();
+    /**USART3 GPIO Configuration
+    PB10     ------> USART3_TX
+    PB11     ------> USART3_RX
+    PD11     ------> USART3_CTS
+    PD12     ------> USART3_RTS
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
+    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+    /* USART3 interrupt Init */
+    HAL_NVIC_SetPriority(USART3_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(USART3_IRQn);
+    
+    NVIC_EnableIRQ(USART3_IRQn);
+  /* USER CODE BEGIN USART3_MspInit 1 */
+
+  /* USER CODE END USART3_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+  if(huart->Instance==UART4)
+  {
+  /* USER CODE BEGIN UART4_MspDeInit 0 */
+
+  /* USER CODE END UART4_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_UART4_CLK_DISABLE();
+
+    /**UART4 GPIO Configuration
+    PI9     ------> UART4_RX
+    PA0     ------> UART4_TX
+    */
+    HAL_GPIO_DeInit(GPIOI, GPIO_PIN_9);
+
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0);
+
+    /* UART4 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(UART4_IRQn);
+  /* USER CODE BEGIN UART4_MspDeInit 1 */
+
+  /* USER CODE END UART4_MspDeInit 1 */
+  }
+  else if(huart->Instance==USART3)
+  {
+  /* USER CODE BEGIN USART3_MspDeInit 0 */
+
+  /* USER CODE END USART3_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USART3_CLK_DISABLE();
+
+    /**USART3 GPIO Configuration
+    PB10     ------> USART3_TX
+    PB11     ------> USART3_RX
+    PD11     ------> USART3_CTS
+    PD12     ------> USART3_RTS
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10|GPIO_PIN_11);
+
+    HAL_GPIO_DeInit(GPIOD, GPIO_PIN_11|GPIO_PIN_12);
+
+    /* USART3 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(USART3_IRQn);
+  /* USER CODE BEGIN USART3_MspDeInit 1 */
+
+  /* USER CODE END USART3_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/CubeMX_Config.ioc
new file mode 100644
index 0000000000..a71fd18402
--- /dev/null
+++ b/bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/CubeMX_Config.ioc
@@ -0,0 +1,185 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+GPIO.groupedBy=Group By Peripherals
+KeepUserPlacement=false
+Mcu.Family=STM32H7
+Mcu.IP0=CORTEX_M7
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IP4=UART4
+Mcu.IP5=USART3
+Mcu.IPNb=6
+Mcu.Name=STM32H750XBHx
+Mcu.Package=TFBGA240
+Mcu.Pin0=PI9
+Mcu.Pin1=PI8
+Mcu.Pin10=VP_SYS_VS_Systick
+Mcu.Pin2=PI11
+Mcu.Pin3=PH1-OSC_OUT (PH1)
+Mcu.Pin4=PH0-OSC_IN (PH0)
+Mcu.Pin5=PA0
+Mcu.Pin6=PB10
+Mcu.Pin7=PB11
+Mcu.Pin8=PD11
+Mcu.Pin9=PD12
+Mcu.PinsNb=11
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32H750XBHx
+MxCube.Version=6.0.1
+MxDb.Version=DB.6.0.0
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UART4_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.USART3_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA0.Locked=true
+PA0.Mode=Asynchronous
+PA0.Signal=UART4_TX
+PB10.Locked=true
+PB10.Mode=Asynchronous
+PB10.Signal=USART3_TX
+PB11.Locked=true
+PB11.Mode=Asynchronous
+PB11.Signal=USART3_RX
+PD11.Mode=CTS_RTS
+PD11.Signal=USART3_CTS
+PD12.Mode=CTS_RTS
+PD12.Signal=USART3_RTS
+PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator
+PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN
+PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator
+PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT
+PI11.Locked=true
+PI11.Signal=GPIO_Output
+PI8.Locked=true
+PI8.Signal=GPIO_Output
+PI9.Locked=true
+PI9.Mode=Asynchronous
+PI9.Signal=UART4_RX
+PinOutPanel.CurrentBGAView=Top
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.CustomerFirmwarePackage=
+ProjectManager.DefaultFWLocation=true
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32H750XBHx
+ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.8.0
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=1
+ProjectManager.MainLocation=Core/Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=CubeMX_Config.ioc
+ProjectManager.ProjectName=CubeMX_Config
+ProjectManager.RegisterCallBack=
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=MDK-ARM V5
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_UART4_Init-UART4-false-HAL-true,4-MX_USART3_UART_Init-USART3-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
+RCC.ADCFreq_Value=400000000
+RCC.AHB12Freq_Value=240000000
+RCC.AHB4Freq_Value=240000000
+RCC.APB1Freq_Value=120000000
+RCC.APB2Freq_Value=120000000
+RCC.APB3Freq_Value=120000000
+RCC.APB4Freq_Value=120000000
+RCC.AXIClockFreq_Value=240000000
+RCC.CECFreq_Value=32000
+RCC.CKPERFreq_Value=64000000
+RCC.CortexFreq_Value=480000000
+RCC.CpuClockFreq_Value=480000000
+RCC.D1CPREFreq_Value=480000000
+RCC.D1PPRE=RCC_APB3_DIV2
+RCC.D2PPRE1=RCC_APB1_DIV2
+RCC.D2PPRE2=RCC_APB2_DIV2
+RCC.D3PPRE=RCC_APB4_DIV2
+RCC.DFSDMACLkFreq_Value=480000000
+RCC.DFSDMFreq_Value=120000000
+RCC.DIVM1=5
+RCC.DIVM2=2
+RCC.DIVM3=5
+RCC.DIVN1=192
+RCC.DIVN2=64
+RCC.DIVN3=160
+RCC.DIVP1Freq_Value=480000000
+RCC.DIVP2Freq_Value=400000000
+RCC.DIVP3Freq_Value=400000000
+RCC.DIVQ1Freq_Value=480000000
+RCC.DIVQ2Freq_Value=400000000
+RCC.DIVQ3Freq_Value=400000000
+RCC.DIVR1Freq_Value=480000000
+RCC.DIVR2Freq_Value=400000000
+RCC.DIVR3Freq_Value=400000000
+RCC.FDCANFreq_Value=480000000
+RCC.FMCFreq_Value=240000000
+RCC.FamilyName=M
+RCC.HCLK3ClockFreq_Value=240000000
+RCC.HCLKFreq_Value=240000000
+RCC.HPRE=RCC_HCLK_DIV2
+RCC.HRTIMFreq_Value=240000000
+RCC.I2C123Freq_Value=120000000
+RCC.I2C4Freq_Value=120000000
+RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,D1PPRE,D2PPRE1,D2PPRE2,D3PPRE,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM2,DIVM3,DIVN1,DIVN2,DIVN3,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HRTIMFreq_Value,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL2FRACN,PLL3FRACN,PLLFRACN,PLLSourceVirtual,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
+RCC.LPTIM1Freq_Value=120000000
+RCC.LPTIM2Freq_Value=120000000
+RCC.LPTIM345Freq_Value=120000000
+RCC.LPUART1Freq_Value=120000000
+RCC.LTDCFreq_Value=400000000
+RCC.MCO1PinFreq_Value=64000000
+RCC.MCO2PinFreq_Value=480000000
+RCC.PLL2FRACN=0
+RCC.PLL3FRACN=0
+RCC.PLLFRACN=0
+RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
+RCC.QSPIFreq_Value=240000000
+RCC.RNGFreq_Value=48000000
+RCC.RTCFreq_Value=32000
+RCC.SAI1Freq_Value=480000000
+RCC.SAI23Freq_Value=480000000
+RCC.SAI4AFreq_Value=480000000
+RCC.SAI4BFreq_Value=480000000
+RCC.SDMMCFreq_Value=480000000
+RCC.SPDIFRXFreq_Value=480000000
+RCC.SPI123Freq_Value=480000000
+RCC.SPI45Freq_Value=120000000
+RCC.SPI6Freq_Value=120000000
+RCC.SWPMI1Freq_Value=120000000
+RCC.SYSCLKFreq_VALUE=480000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.Tim1OutputFreq_Value=240000000
+RCC.Tim2OutputFreq_Value=240000000
+RCC.TraceFreq_Value=64000000
+RCC.USART16Freq_Value=120000000
+RCC.USART234578Freq_Value=120000000
+RCC.USBFreq_Value=480000000
+RCC.VCO1OutputFreq_Value=960000000
+RCC.VCO2OutputFreq_Value=800000000
+RCC.VCO3OutputFreq_Value=800000000
+RCC.VCOInput1Freq_Value=5000000
+RCC.VCOInput2Freq_Value=12500000
+RCC.VCOInput3Freq_Value=5000000
+USART3.IPParameters=VirtualMode-Asynchronous
+USART3.VirtualMode-Asynchronous=VM_ASYNC
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom
diff --git a/bsp/stm32/stm32h750-artpi-h750/board/Kconfig b/bsp/stm32/stm32h750-artpi-h750/board/Kconfig
new file mode 100644
index 0000000000..2d07f8c8e3
--- /dev/null
+++ b/bsp/stm32/stm32h750-artpi-h750/board/Kconfig
@@ -0,0 +1,58 @@
+menu "Hardware Drivers Config"
+
+config SOC_STM32H750XB
+    bool
+    select SOC_SERIES_STM32H7
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+menu "Onboard Peripheral Drivers"
+
+    config BSP_USING_QSPI_FLASH
+        bool "Enable QSPI FLASH (W25Q64)"
+        select BSP_USING_QSPI
+        select RT_USING_SFUD
+        select RT_SFUD_USING_QSPI
+        default n
+endmenu
+
+menu "On-chip Peripheral Drivers"
+
+    config BSP_USING_GPIO
+        bool "Enable GPIO"
+        select RT_USING_PIN
+        default y
+
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+        if BSP_USING_UART
+            config BSP_USING_UART3
+                bool "Enable UART3"
+                default y
+
+            config BSP_USING_UART4
+                bool "Enable UART4"
+                default y
+        endif
+
+
+
+    config BSP_USING_SDIO
+        bool "Enable SDIO"
+        select RT_USING_SDIO
+        select RT_USING_DFS
+        default n
+
+
+    source "../libraries/HAL_Drivers/Kconfig"
+
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+
+endmenu
diff --git a/bsp/stm32/stm32h750-artpi-h750/board/SConscript b/bsp/stm32/stm32h750-artpi-h750/board/SConscript
new file mode 100644
index 0000000000..b914230f3a
--- /dev/null
+++ b/bsp/stm32/stm32h750-artpi-h750/board/SConscript
@@ -0,0 +1,31 @@
+import rtconfig
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Glob('board.c')
+src += Glob('CubeMX_Config/Core/Src/stm32h7xx_hal_msp.c')
+
+if GetDepend(['BSP_USING_QSPI_FLASH']):
+    src += Glob('ports/drv_qspi_flash.c')
+
+if GetDepend('BSP_USING_SPI_LCD'):
+    src = src + ['ports/drv_lcd.c']
+
+path = [cwd]
+path += [cwd + '/CubeMX_Config/Core/Inc']
+
+if rtconfig.CROSS_TOOL == 'gcc':
+    src += [cwd + '/../../libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h750xx.s']
+elif rtconfig.CROSS_TOOL == 'keil':
+    src += [cwd + '/../../libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h750xx.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+    src += [cwd + '/../../libraries/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h750xx.s']
+
+# STM32H743xx || STM32H750xx || STM32F753xx
+# You can select chips from the list above
+CPPDEFINES = ['STM32H750xx']
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
diff --git a/bsp/stm32/stm32h750-artpi-h750/board/board.c b/bsp/stm32/stm32h750-artpi-h750/board/board.c
new file mode 100644
index 0000000000..b00158da68
--- /dev/null
+++ b/bsp/stm32/stm32h750-artpi-h750/board/board.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-10-26     zylx         first version
+ */
+
+#include "board.h"
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /** Supply configuration update enable
+  */
+  HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
+  /** Configure the main internal regulator output voltage
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
+
+  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = 5;
+  RCC_OscInitStruct.PLL.PLLN = 192;
+  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 2;
+  RCC_OscInitStruct.PLL.PLLR = 2;
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
+  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
+                              |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
+  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_UART4;
+  PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+
diff --git a/bsp/stm32/stm32f103-mini-system/board/board.h b/bsp/stm32/stm32h750-artpi-h750/board/board.h
similarity index 69%
rename from bsp/stm32/stm32f103-mini-system/board/board.h
rename to bsp/stm32/stm32h750-artpi-h750/board/board.h
index 7f0ae67d48..5c00854d41 100644
--- a/bsp/stm32/stm32f103-mini-system/board/board.h
+++ b/bsp/stm32/stm32h750-artpi-h750/board/board.h
@@ -12,7 +12,7 @@
 #define __BOARD_H__
 
 #include 
-#include 
+#include 
 #include "drv_common.h"
 #include "drv_gpio.h"
 
@@ -21,22 +21,21 @@ extern "C" {
 #endif
 
 #define STM32_FLASH_START_ADRESS     ((uint32_t)0x08000000)
-#define STM32_FLASH_SIZE             (64 * 1024)
+#define STM32_FLASH_SIZE             (128 * 1024)
 #define STM32_FLASH_END_ADDRESS      ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
 
-/* Internal SRAM memory size[Kbytes] <8-64>, Default: 64*/
-#define STM32_SRAM_SIZE      20
-#define STM32_SRAM_END       (0x20000000 + STM32_SRAM_SIZE * 1024)
+#define STM32_SRAM_SIZE           (128)
+#define STM32_SRAM_END            (0x20000000 + STM32_SRAM_SIZE * 1024)
 
 #if defined(__CC_ARM) || defined(__CLANG_ARM)
 extern int Image$$RW_IRAM1$$ZI$$Limit;
-#define HEAP_BEGIN      ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
+#define HEAP_BEGIN      (&Image$$RW_IRAM1$$ZI$$Limit)
 #elif __ICCARM__
 #pragma section="CSTACK"
 #define HEAP_BEGIN      (__segment_end("CSTACK"))
 #else
 extern int __bss_end;
-#define HEAP_BEGIN      ((void *)&__bss_end)
+#define HEAP_BEGIN      (&__bss_end)
 #endif
 
 #define HEAP_END        STM32_SRAM_END
@@ -47,4 +46,4 @@ void SystemClock_Config(void);
 }
 #endif
 
-#endif /* __BOARD_H__ */
+#endif
diff --git a/bsp/stm32/stm32f103-mini-system/board/linker_scripts/link.icf b/bsp/stm32/stm32h750-artpi-h750/board/linker_scripts/link.icf
similarity index 80%
rename from bsp/stm32/stm32f103-mini-system/board/linker_scripts/link.icf
rename to bsp/stm32/stm32h750-artpi-h750/board/linker_scripts/link.icf
index 72eeb0ba65..57ea141727 100644
--- a/bsp/stm32/stm32f103-mini-system/board/linker_scripts/link.icf
+++ b/bsp/stm32/stm32h750-artpi-h750/board/linker_scripts/link.icf
@@ -5,12 +5,12 @@
 define symbol __ICFEDIT_intvec_start__ = 0x08000000;
 /*-Memory Regions-*/
 define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0800FFFF;
+define symbol __ICFEDIT_region_ROM_end__   = 0x00020000;
 define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20004FFF;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20020000;
 /*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x0400;
-define symbol __ICFEDIT_size_heap__   = 0x0000;
+define symbol __ICFEDIT_size_cstack__ = 0x800;
+define symbol __ICFEDIT_size_heap__   = 0x400;
 /**** End of ICF editor section. ###ICF###*/
 
 define memory mem with size = 4G;
diff --git a/bsp/stm32/stm32f103-mini-system/board/linker_scripts/link.lds b/bsp/stm32/stm32h750-artpi-h750/board/linker_scripts/link.lds
similarity index 95%
rename from bsp/stm32/stm32f103-mini-system/board/linker_scripts/link.lds
rename to bsp/stm32/stm32h750-artpi-h750/board/linker_scripts/link.lds
index 22e29d2ed7..a97ce9dc07 100644
--- a/bsp/stm32/stm32f103-mini-system/board/linker_scripts/link.lds
+++ b/bsp/stm32/stm32h750-artpi-h750/board/linker_scripts/link.lds
@@ -1,12 +1,13 @@
 /*
- * linker script for STM32F10x with GNU ld
+ * linker script for STM32F4xx with GNU ld
+ * bernard.xiong 2009-10-14
  */
 
 /* Program Entry, set to mark it as "used" and avoid gc */
 MEMORY
 {
-    ROM (rx) : ORIGIN = 0x08000000, LENGTH = 64k /* 64KB flash */
-    RAM (rw) : ORIGIN = 0x20000000, LENGTH =  20k /* 20K sram */
+    ROM (rx) : ORIGIN = 0x08000000, LENGTH =  128k /* 128KB flash */
+    RAM (rw) : ORIGIN = 0x20000000, LENGTH =  128k /* 128K DTCM */
 }
 ENTRY(Reset_Handler)
 _system_stack_size = 0x200;
diff --git a/bsp/stm32/stm32h750-artpi-h750/board/linker_scripts/link.sct b/bsp/stm32/stm32h750-artpi-h750/board/linker_scripts/link.sct
new file mode 100644
index 0000000000..f13040124c
--- /dev/null
+++ b/bsp/stm32/stm32h750-artpi-h750/board/linker_scripts/link.sct
@@ -0,0 +1,19 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00020000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00020000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+  RW_IRAM1 0x20000000 0x00020000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  RW_IRAM2 0x24000000 0x00080000  {
+   .ANY (+RW +ZI)
+  }
+}
+
diff --git a/bsp/stm32/stm32h750-artpi-h750/figures/board.jpg b/bsp/stm32/stm32h750-artpi-h750/figures/board.jpg
new file mode 100644
index 0000000000..d83e0f3082
Binary files /dev/null and b/bsp/stm32/stm32h750-artpi-h750/figures/board.jpg differ
diff --git a/bsp/stm32/stm32h750-artpi-h750/project.ewp b/bsp/stm32/stm32h750-artpi-h750/project.ewp
new file mode 100644
index 0000000000..46ff03c595
--- /dev/null
+++ b/bsp/stm32/stm32h750-artpi-h750/project.ewp
@@ -0,0 +1,2268 @@
+
+
+    3
+    
+        rtthread
+        
+            ARM
+        
+        1
+        
+            General
+            3
+            
+                31
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            ICCARM
+            2
+            
+                34
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
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+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            AARM
+            2
+            
+                10
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            OBJCOPY
+            0
+            
+                1
+                1
+                1
+                
+                
+                
+                
+                
+            
+        
+        
+            CUSTOM
+            3
+            
+                
+                
+                0
+            
+        
+        
+            BICOMP
+            0
+            
+        
+        
+            BUILDACTION
+            1
+            
+                
+                
+            
+        
+        
+            ILINK
+            0
+            
+                21
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
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+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            IARCHIVE
+            0
+            
+                0
+                1
+                1
+                
+                
+                
+            
+        
+        
+            BILINK
+            0
+            
+        
+    
+    
+        Release
+        
+            ARM
+        
+        0
+        
+            General
+            3
+            
+                31
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
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+                
+                
+                
+                
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+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            ICCARM
+            2
+            
+                34
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
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+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            AARM
+            2
+            
+                10
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            OBJCOPY
+            0
+            
+                1
+                1
+                0
+                
+                
+                
+                
+                
+            
+        
+        
+            CUSTOM
+            3
+            
+                
+                
+                0
+            
+        
+        
+            BICOMP
+            0
+            
+        
+        
+            BUILDACTION
+            1
+            
+                
+                
+            
+        
+        
+            ILINK
+            0
+            
+                21
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            IARCHIVE
+            0
+            
+                0
+                1
+                0
+                
+                
+                
+            
+        
+        
+            BILINK
+            0
+            
+        
+    
+    
+        Applications
+        
+            $PROJ_DIR$\applications\main.c
+        
+    
+    
+        cpu
+        
+            $PROJ_DIR$\..\..\..\libcpu\arm\common\backtrace.c
+        
+        
+            $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m7\context_iar.S
+        
+        
+            $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m7\cpu_cache.c
+        
+        
+            $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m7\cpuport.c
+        
+        
+            $PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c
+        
+        
+            $PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c
+        
+    
+    
+        DeviceDrivers
+        
+            $PROJ_DIR$\..\..\..\components\drivers\src\completion.c
+        
+        
+            $PROJ_DIR$\..\..\..\components\drivers\src\dataqueue.c
+        
+        
+            $PROJ_DIR$\..\..\..\components\drivers\misc\pin.c
+        
+        
+            $PROJ_DIR$\..\..\..\components\drivers\src\pipe.c
+        
+        
+            $PROJ_DIR$\..\..\..\components\drivers\src\ringblk_buf.c
+        
+        
+            $PROJ_DIR$\..\..\..\components\drivers\src\ringbuffer.c
+        
+        
+            $PROJ_DIR$\..\..\..\components\drivers\serial\serial.c
+        
+        
+            $PROJ_DIR$\..\..\..\components\drivers\src\waitqueue.c
+        
+        
+            $PROJ_DIR$\..\..\..\components\drivers\src\workqueue.c
+        
+    
+    
+        Drivers
+        
+            $PROJ_DIR$\board\board.c
+        
+        
+            $PROJ_DIR$\..\libraries\HAL_Drivers\drv_common.c
+        
+        
+            $PROJ_DIR$\..\libraries\HAL_Drivers\drv_gpio.c
+        
+        
+            $PROJ_DIR$\..\libraries\HAL_Drivers\drv_usart.c
+        
+        
+            $PROJ_DIR$\..\libraries\STM32H7xx_HAL\CMSIS\Device\ST\STM32H7xx\Source\Templates\iar\startup_stm32h750xx.s
+        
+        
+            $PROJ_DIR$\board\CubeMX_Config\Core\Src\stm32h7xx_hal_msp.c
+        
+    
+    
+        finsh
+        
+            $PROJ_DIR$\..\..\..\components\finsh\cmd.c
+        
+        
+            $PROJ_DIR$\..\..\..\components\finsh\msh.c
+        
+        
+            $PROJ_DIR$\..\..\..\components\finsh\shell.c
+        
+    
+    
+        Kernel
+        
+            $PROJ_DIR$\..\..\..\src\clock.c
+        
+        
+            $PROJ_DIR$\..\..\..\src\components.c
+        
+        
+            $PROJ_DIR$\..\..\..\src\device.c
+        
+        
+            $PROJ_DIR$\..\..\..\src\idle.c
+        
+        
+            $PROJ_DIR$\..\..\..\src\ipc.c
+        
+        
+            $PROJ_DIR$\..\..\..\src\irq.c
+        
+        
+            $PROJ_DIR$\..\..\..\src\kservice.c
+        
+        
+            $PROJ_DIR$\..\..\..\src\mem.c
+        
+        
+            $PROJ_DIR$\..\..\..\src\mempool.c
+        
+        
+            $PROJ_DIR$\..\..\..\src\object.c
+        
+        
+            $PROJ_DIR$\..\..\..\src\scheduler.c
+        
+        
+            $PROJ_DIR$\..\..\..\src\signal.c
+        
+        
+            $PROJ_DIR$\..\..\..\src\thread.c
+        
+        
+            $PROJ_DIR$\..\..\..\src\timer.c
+        
+    
+    
+        libc
+        
+            $PROJ_DIR$\..\..\..\components\libc\compilers\common\time.c
+        
+    
+    
+        STM32_HAL
+        
+            $PROJ_DIR$\..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c
+        
+        
+            $PROJ_DIR$\..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cec.c
+        
+        
+            $PROJ_DIR$\..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_comp.c
+        
+        
+            $PROJ_DIR$\..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c
+        
+        
+            $PROJ_DIR$\..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_crc.c
+        
+        
+            $PROJ_DIR$\..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_crc_ex.c
+        
+        
+            $PROJ_DIR$\..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cryp.c
+        
+        
+            $PROJ_DIR$\..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cryp_ex.c
+        
+        
+            $PROJ_DIR$\..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c
+        
+        
+            $PROJ_DIR$\..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c
+        
+        
+            $PROJ_DIR$\..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c
+        
+        
+            $PROJ_DIR$\..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c
+        
+        
+            $PROJ_DIR$\..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c
+        
+        
+            $PROJ_DIR$\..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c
+        
+        
+            $PROJ_DIR$\..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c
+        
+        
+            $PROJ_DIR$\..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c
+        
+        
+            $PROJ_DIR$\..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rng.c
+        
+        
+            $PROJ_DIR$\..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sram.c
+        
+        
+            $PROJ_DIR$\..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart.c
+        
+        
+            $PROJ_DIR$\..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart_ex.c
+        
+        
+            $PROJ_DIR$\..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_usart.c
+        
+        
+            $PROJ_DIR$\..\libraries\STM32H7xx_HAL\CMSIS\Device\ST\STM32H7xx\Source\Templates\system_stm32h7xx.c
+        
+    
+
diff --git a/bsp/stm32/stm32f103-mini-system/project.eww b/bsp/stm32/stm32h750-artpi-h750/project.eww
similarity index 100%
rename from bsp/stm32/stm32f103-mini-system/project.eww
rename to bsp/stm32/stm32h750-artpi-h750/project.eww
diff --git a/bsp/stm32/stm32h750-artpi-h750/project.uvoptx b/bsp/stm32/stm32h750-artpi-h750/project.uvoptx
new file mode 100644
index 0000000000..32aea0646d
--- /dev/null
+++ b/bsp/stm32/stm32h750-artpi-h750/project.uvoptx
@@ -0,0 +1,1158 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    rt-thread
+    0x4
+    ARM-ADS
+    
+      12000000
+      
+        1
+        1
+        0
+        1
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        .\build\
+      
+      
+        1
+        1
+        1
+        0
+        1
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diff --git a/bsp/stm32/stm32f103-mini-system/project.uvprojx b/bsp/stm32/stm32h750-artpi-h750/project.uvprojx
similarity index 64%
rename from bsp/stm32/stm32f103-mini-system/project.uvprojx
rename to bsp/stm32/stm32h750-artpi-h750/project.uvprojx
index f719cebbfa..a1cb30f17d 100644
--- a/bsp/stm32/stm32f103-mini-system/project.uvprojx
+++ b/bsp/stm32/stm32h750-artpi-h750/project.uvprojx
@@ -1,41 +1,46 @@
 
 
+
   2.1
+
   
### uVision Project, (C) Keil Software

+
   
     
       rt-thread
       0x4
       ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
       
         
-          STM32F103C8
+          STM32H750XBHx
           STMicroelectronics
-          Keil.STM32F1xx_DFP.1.0.5
+          Keil.STM32H7xx_DFP.2.5.0
           http://www.keil.com/pack/
-          IROM(0x08000000,0x10000) IRAM(0x20000000,0x5000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE
-          
-          
-          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103C8$Flash\STM32F10x_128.FLM))
+          IRAM(0x20000000,0x00020000) IRAM2(0x24000000,0x00080000) IROM(0x08000000,0x00020000) XRAM(0x30000000,0x00048000) XRAM2(0x38000000,0x00010000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE
+          
+          
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32H7x_128k -FS08000000 -FL020000 -FP0($$Device:STM32H750XBHx$CMSIS\Flash\STM32H7x_128k.FLM))
           0
-          $$Device:STM32F103C8$Device\Include\stm32f10x.h
-          
-          
-          
-          
-          
-          
-          
-          
-          
-          $$Device:STM32F103C8$SVD\STM32F103xx.svd
+          $$Device:STM32H750XBHx$Drivers\CMSIS\Device\ST\STM32H7xx\Include\stm32h7xx.h
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32H750XBHx$CMSIS\SVD\STM32H750x.svd
           0
           0
-          
-          
-          
-          
-          
+          
+          
+          
+          
+          
           
             0
             0
@@ -43,22 +48,22 @@
             0
             1
           
-          .\build\keil\Obj\
+          .\build\
           rt-thread
           1
           0
-          1
+          0
           1
           0
-          .\build\keil\List\
+          .\build\
           1
           0
           0
           
             0
             0
-            
-            
+            
+            
             0
             0
             0
@@ -67,8 +72,8 @@
           
             0
             0
-            
-            
+            
+            
             0
             0
             0
@@ -78,12 +83,14 @@
             1
             0
             fromelf --bin !L --output rtthread.bin
-            
+            
             0
             0
+            0
+            0
           
           0
-          
+          
         
         
           0
@@ -97,19 +104,19 @@
           0
           0
           3
-          
-          
+          
+          
           1
         
         
           SARMCM3.DLL
-           -REMAP
+           -REMAP -MPU
           DCM.DLL
-          -pCM3
+          -pCM7
           SARMCM3.DLL
-          
+           -MPU
           TCM.DLL
-          -pCM3
+          -pCM7
         
         
           
@@ -119,47 +126,6 @@
             0
             16
           
-          
-            0
-            1
-            1
-            1
-            1
-            1
-            1
-            1
-            0
-            1
-          
-          
-            1
-            1
-            1
-            1
-            1
-            1
-            0
-            1
-            1
-            1
-          
-          0
-          1
-          
-            
-            
-            
-            
-            
-          
-          
-            
-            
-            
-            
-            
-            BIN\UL2CM3.DLL
-          
         
         
           
@@ -172,11 +138,11 @@
           
           1
           BIN\UL2CM3.DLL
-          
-          
-          
-          
-          
+          
+          
+          
+          
+          
           0
         
         
@@ -208,24 +174,26 @@
             1
             0
             0
-            "Cortex-M3"
-            
+            "Cortex-M7"
+            
             0
             0
             0
             1
             1
-            0
+            1
             0
-            0
-            0
+            3
+            0
+            1
             0
             8
-            0
+            1
             0
             0
+            0
             3
-            3
+            4
             0
             0
             0
@@ -242,7 +210,7 @@
             0
             0
             1
-            0
+            1
             
               
                 0
@@ -277,17 +245,17 @@
               
                 0
                 0x20000000
-                0x5000
+                0x20000
               
               
                 1
                 0x8000000
-                0x10000
+                0x20000
               
               
-                0
-                0x0
-                0x0
+                1
+                0x30000000
+                0x48000
               
               
                 1
@@ -307,7 +275,7 @@
               
                 1
                 0x8000000
-                0x10000
+                0x20000
               
               
                 1
@@ -316,13 +284,13 @@
               
               
                 0
-                0x0
-                0x0
+                0x30000000
+                0x48000
               
               
                 0
-                0x0
-                0x0
+                0x38000000
+                0x10000
               
               
                 0
@@ -332,15 +300,15 @@
               
                 0
                 0x20000000
-                0x5000
+                0x20000
               
               
                 0
-                0x0
-                0x0
+                0x24000000
+                0x80000
               
             
-            
+            
           
           
             1
@@ -350,19 +318,27 @@
             1
             0
             0
-            0
+            1
             0
             0
-            2
+            0
             0
             0
             1
+            0
             0
+            0
+            0
+            1
+            1
+            0
+            0
+            0
             
-              
-              STM32F103xB, USE_HAL_DRIVER, __RTTHREAD__
-              
-              applications;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m3;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\libraries\STM32F1xx_HAL\CMSIS\Device\ST\STM32F1xx\Include;..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Inc;..\libraries\STM32F1xx_HAL\CMSIS\Include
+              
+              STM32H750xx, USE_HAL_DRIVER, __RTTHREAD__
+              
+              ..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m7;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;board\CubeMX_Config\Core\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\common;..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Inc;..\libraries\STM32H7xx_HAL\CMSIS\Device\ST\STM32H7xx\Include;..\libraries\STM32H7xx_HAL\CMSIS\Include
             
           
           
@@ -375,11 +351,12 @@
             0
             0
             0
+            0
             
-              
-              
-              
-              
+              
+              
+              
+              
             
           
           
@@ -391,13 +368,13 @@
             0
             0x08000000
             0x20000000
-            
+            
             .\board\linker_scripts\link.sct
-            
-            
-            
-            
-            
+            
+            
+            
+            
+            
           
         
       
@@ -413,40 +390,37 @@
           
         
         
-          CPU
+          cpu
           
             
               backtrace.c
               1
               ..\..\..\libcpu\arm\common\backtrace.c
             
-          
-          
             
               div0.c
               1
               ..\..\..\libcpu\arm\common\div0.c
             
-          
-          
             
               showmem.c
               1
               ..\..\..\libcpu\arm\common\showmem.c
             
-          
-          
+            
+              cpu_cache.c
+              1
+              ..\..\..\libcpu\arm\cortex-m7\cpu_cache.c
+            
             
               cpuport.c
               1
-              ..\..\..\libcpu\arm\cortex-m3\cpuport.c
+              ..\..\..\libcpu\arm\cortex-m7\cpuport.c
             
-          
-          
             
               context_rvds.S
               2
-              ..\..\..\libcpu\arm\cortex-m3\context_rvds.S
+              ..\..\..\libcpu\arm\cortex-m7\context_rvds.S
             
           
         
@@ -458,57 +432,41 @@
               1
               ..\..\..\components\drivers\misc\pin.c
             
-          
-          
             
               serial.c
               1
               ..\..\..\components\drivers\serial\serial.c
             
-          
-          
             
               completion.c
               1
               ..\..\..\components\drivers\src\completion.c
             
-          
-          
             
               dataqueue.c
               1
               ..\..\..\components\drivers\src\dataqueue.c
             
-          
-          
             
               pipe.c
               1
               ..\..\..\components\drivers\src\pipe.c
             
-          
-          
             
               ringblk_buf.c
               1
               ..\..\..\components\drivers\src\ringblk_buf.c
             
-          
-          
             
               ringbuffer.c
               1
               ..\..\..\components\drivers\src\ringbuffer.c
             
-          
-          
             
               waitqueue.c
               1
               ..\..\..\components\drivers\src\waitqueue.c
             
-          
-          
             
               workqueue.c
               1
@@ -524,36 +482,26 @@
               1
               board\board.c
             
-          
-          
             
-              stm32f1xx_hal_msp.c
+              stm32h7xx_hal_msp.c
               1
-              board\CubeMX_Config\Src\stm32f1xx_hal_msp.c
+              board\CubeMX_Config\Core\Src\stm32h7xx_hal_msp.c
             
-          
-          
             
-              startup_stm32f103xb.s
+              startup_stm32h750xx.s
               2
-              ..\libraries\STM32F1xx_HAL\CMSIS\Device\ST\STM32F1xx\Source\Templates\arm\startup_stm32f103xb.s
+              ..\libraries\STM32H7xx_HAL\CMSIS\Device\ST\STM32H7xx\Source\Templates\arm\startup_stm32h750xx.s
             
-          
-          
             
               drv_gpio.c
               1
               ..\libraries\HAL_Drivers\drv_gpio.c
             
-          
-          
             
               drv_usart.c
               1
               ..\libraries\HAL_Drivers\drv_usart.c
             
-          
-          
             
               drv_common.c
               1
@@ -569,15 +517,11 @@
               1
               ..\..\..\components\finsh\shell.c
             
-          
-          
             
               cmd.c
               1
               ..\..\..\components\finsh\cmd.c
             
-          
-          
             
               msh.c
               1
@@ -593,92 +537,66 @@
               1
               ..\..\..\src\clock.c
             
-          
-          
             
               components.c
               1
               ..\..\..\src\components.c
             
-          
-          
             
               device.c
               1
               ..\..\..\src\device.c
             
-          
-          
             
               idle.c
               1
               ..\..\..\src\idle.c
             
-          
-          
             
               ipc.c
               1
               ..\..\..\src\ipc.c
             
-          
-          
             
               irq.c
               1
               ..\..\..\src\irq.c
             
-          
-          
             
               kservice.c
               1
               ..\..\..\src\kservice.c
             
-          
-          
             
               mem.c
               1
               ..\..\..\src\mem.c
             
-          
-          
             
               mempool.c
               1
               ..\..\..\src\mempool.c
             
-          
-          
             
               object.c
               1
               ..\..\..\src\object.c
             
-          
-          
             
               scheduler.c
               1
               ..\..\..\src\scheduler.c
             
-          
-          
             
               signal.c
               1
               ..\..\..\src\signal.c
             
-          
-          
             
               thread.c
               1
               ..\..\..\src\thread.c
             
-          
-          
             
               timer.c
               1
@@ -687,100 +605,138 @@
           
         
         
-          Libraries
+          libc
           
             
-              system_stm32f1xx.c
+              time.c
               1
-              ..\libraries\STM32F1xx_HAL\CMSIS\Device\ST\STM32F1xx\Source\Templates\system_stm32f1xx.c
+              ..\..\..\components\libc\compilers\common\time.c
             
           
+        
+        
+          STM32_HAL
           
             
-              stm32f1xx_hal_dma.c
+              system_stm32h7xx.c
               1
-              ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_dma.c
+              ..\libraries\STM32H7xx_HAL\CMSIS\Device\ST\STM32H7xx\Source\Templates\system_stm32h7xx.c
             
-          
-          
             
-              stm32f1xx_hal_cortex.c
+              stm32h7xx_hal.c
               1
-              ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cortex.c
+              ..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c
             
-          
-          
             
-              stm32f1xx_hal_crc.c
+              stm32h7xx_hal_cec.c
               1
-              ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_crc.c
+              ..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cec.c
             
-          
-          
             
-              stm32f1xx_hal_pwr.c
+              stm32h7xx_hal_cortex.c
               1
-              ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_pwr.c
+              ..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c
             
-          
-          
             
-              stm32f1xx_hal_rcc.c
+              stm32h7xx_hal_comp.c
               1
-              ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc.c
+              ..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_comp.c
             
-          
-          
             
-              stm32f1xx_hal_rcc_ex.c
+              stm32h7xx_hal_crc.c
               1
-              ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_rcc_ex.c
+              ..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_crc.c
             
-          
-          
             
-              stm32f1xx_hal.c
+              stm32h7xx_hal_crc_ex.c
               1
-              ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal.c
+              ..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_crc_ex.c
             
-          
-          
             
-              stm32f1xx_hal_cec.c
+              stm32h7xx_hal_cryp.c
               1
-              ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_cec.c
+              ..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cryp.c
             
-          
-          
             
-              stm32f1xx_hal_gpio.c
+              stm32h7xx_hal_cryp_ex.c
               1
-              ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio.c
+              ..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cryp_ex.c
             
-          
-          
             
-              stm32f1xx_hal_gpio_ex.c
+              stm32h7xx_hal_dma.c
               1
-              ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_gpio_ex.c
+              ..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c
             
-          
-          
             
-              stm32f1xx_hal_uart.c
+              stm32h7xx_hal_dma_ex.c
               1
-              ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_uart.c
+              ..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c
             
-          
-          
             
-              stm32f1xx_hal_usart.c
+              stm32h7xx_hal_mdma.c
               1
-              ..\libraries\STM32F1xx_HAL\STM32F1xx_HAL_Driver\Src\stm32f1xx_hal_usart.c
+              ..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c
+            
+            
+              stm32h7xx_hal_pwr.c
+              1
+              ..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c
+            
+            
+              stm32h7xx_hal_pwr_ex.c
+              1
+              ..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c
+            
+            
+              stm32h7xx_hal_rcc.c
+              1
+              ..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c
+            
+            
+              stm32h7xx_hal_rcc_ex.c
+              1
+              ..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c
+            
+            
+              stm32h7xx_hal_rng.c
+              1
+              ..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rng.c
+            
+            
+              stm32h7xx_hal_sram.c
+              1
+              ..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sram.c
+            
+            
+              stm32h7xx_hal_gpio.c
+              1
+              ..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c
+            
+            
+              stm32h7xx_hal_uart.c
+              1
+              ..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart.c
+            
+            
+              stm32h7xx_hal_usart.c
+              1
+              ..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_usart.c
+            
+            
+              stm32h7xx_hal_uart_ex.c
+              1
+              ..\libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart_ex.c
             
           
         
       
     
   
+
+  
+    
+    
+    
+  
+
 
diff --git a/bsp/stm32/stm32f103-mini-system/rtconfig.h b/bsp/stm32/stm32h750-artpi-h750/rtconfig.h
similarity index 87%
rename from bsp/stm32/stm32f103-mini-system/rtconfig.h
rename to bsp/stm32/stm32h750-artpi-h750/rtconfig.h
index ad9281a5d4..8d75171203 100644
--- a/bsp/stm32/stm32f103-mini-system/rtconfig.h
+++ b/bsp/stm32/stm32h750-artpi-h750/rtconfig.h
@@ -37,11 +37,12 @@
 #define RT_USING_DEVICE
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 128
-#define RT_CONSOLE_DEVICE_NAME "uart1"
-#define RT_VER_NUM 0x40001
+#define RT_CONSOLE_DEVICE_NAME "uart4"
+#define RT_VER_NUM 0x40003
 #define ARCH_ARM
+#define RT_USING_CPU_FFS
 #define ARCH_ARM_CORTEX_M
-#define ARCH_ARM_CORTEX_M3
+#define ARCH_ARM_CORTEX_M7
 
 /* RT-Thread Components */
 
@@ -77,30 +78,27 @@
 #define RT_USING_DEVICE_IPC
 #define RT_PIPE_BUFSZ 512
 #define RT_USING_SERIAL
-#define RT_SERIAL_USING_DMA
 #define RT_SERIAL_RB_BUFSZ 64
 #define RT_USING_PIN
 
-/* Using WiFi */
-
-
 /* Using USB */
 
 
 /* POSIX layer and C standard library */
 
+#define RT_LIBC_USING_TIME
 
 /* Network */
 
 /* Socket abstraction layer */
 
 
+/* Network interface device */
+
+
 /* light weight TCP/IP stack */
 
 
-/* Modbus master and slave stack */
-
-
 /* AT commands */
 
 
@@ -147,30 +145,24 @@
 /* miscellaneous packages */
 
 
-/* sample package */
-
 /* samples: kernel and components samples */
 
-
-/* example package: hello */
-
 #define SOC_FAMILY_STM32
-#define SOC_SERIES_STM32F1
+#define SOC_SERIES_STM32H7
 
 /* Hardware Drivers Config */
 
-#define SOC_STM32F103C8
+#define SOC_STM32H750XB
 
 /* Onboard Peripheral Drivers */
 
-#define BSP_USING_USB_TO_USART
 
 /* On-chip Peripheral Drivers */
 
 #define BSP_USING_GPIO
 #define BSP_USING_UART
-#define BSP_USING_UART1
-#define BSP_UART1_RX_USING_DMA
+#define BSP_USING_UART3
+#define BSP_USING_UART4
 
 /* Board extended module Drivers */
 
diff --git a/bsp/stm32/stm32f103-mini-system/rtconfig.py b/bsp/stm32/stm32h750-artpi-h750/rtconfig.py
similarity index 85%
rename from bsp/stm32/stm32f103-mini-system/rtconfig.py
rename to bsp/stm32/stm32h750-artpi-h750/rtconfig.py
index b363b752f5..2c9cbdd792 100644
--- a/bsp/stm32/stm32f103-mini-system/rtconfig.py
+++ b/bsp/stm32/stm32h750-artpi-h750/rtconfig.py
@@ -2,7 +2,7 @@ import os
 
 # toolchains options
 ARCH='arm'
-CPU='cortex-m3'
+CPU='cortex-m7'
 CROSS_TOOL='gcc'
 
 # bsp lib config
@@ -43,10 +43,10 @@ if PLATFORM == 'gcc':
     OBJDUMP = PREFIX + 'objdump'
     OBJCPY = PREFIX + 'objcopy'
 
-    DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections'
+    DEVICE = ' -mcpu=cortex-m7 -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
     CFLAGS = DEVICE + ' -Dgcc'
     AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
-    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
 
     CPATH = ''
     LPATH = ''
@@ -58,6 +58,7 @@ if PLATFORM == 'gcc':
         CFLAGS += ' -O2'
 
     CXXFLAGS = CFLAGS 
+    CFLAGS += ' -std=c99'
 
     POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
 
@@ -70,10 +71,10 @@ elif PLATFORM == 'armcc':
     LINK = 'armlink'
     TARGET_EXT = 'axf'
 
-    DEVICE = ' --cpu Cortex-M3 '
+    DEVICE = ' --cpu Cortex-M7.fp.sp'
     CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
     AFLAGS = DEVICE + ' --apcs=interwork '
-    LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict'
+    LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
     CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
     LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
 
@@ -88,7 +89,6 @@ elif PLATFORM == 'armcc':
     else:
         CFLAGS += ' -O2'
 
-
     CXXFLAGS = CFLAGS 
     CFLAGS += ' -std=c99'
 
@@ -115,20 +115,20 @@ elif PLATFORM == 'iar':
     CFLAGS += ' --no_clustering'
     CFLAGS += ' --no_scheduling'
     CFLAGS += ' --endian=little'
-    CFLAGS += ' --cpu=Cortex-M3'
-    CFLAGS += ' -e'
-    CFLAGS += ' --fpu=None'
+    CFLAGS += ' --cpu=Cortex-M7' 
+    CFLAGS += ' -e' 
+    CFLAGS += ' --fpu=VFPv5_sp'
     CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
     CFLAGS += ' --silent'
-
+    
     AFLAGS = DEVICE
-    AFLAGS += ' -s+'
-    AFLAGS += ' -w+'
-    AFLAGS += ' -r'
-    AFLAGS += ' --cpu Cortex-M3'
-    AFLAGS += ' --fpu None'
-    AFLAGS += ' -S'
-
+    AFLAGS += ' -s+' 
+    AFLAGS += ' -w+' 
+    AFLAGS += ' -r' 
+    AFLAGS += ' --cpu Cortex-M7' 
+    AFLAGS += ' --fpu VFPv5_sp' 
+    AFLAGS += ' -S' 
+    
     if BUILD == 'debug':
         CFLAGS += ' --debug'
         CFLAGS += ' -On'
diff --git a/bsp/stm32/stm32h750-artpi-h750/template.ewp b/bsp/stm32/stm32h750-artpi-h750/template.ewp
new file mode 100644
index 0000000000..1ca2a5511b
--- /dev/null
+++ b/bsp/stm32/stm32h750-artpi-h750/template.ewp
@@ -0,0 +1,2074 @@
+
+
+    3
+    
+        rtthread
+        
+            ARM
+        
+        1
+        
+            General
+            3
+            
+                31
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            ICCARM
+            2
+            
+                35
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            AARM
+            2
+            
+                10
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            OBJCOPY
+            0
+            
+                1
+                1
+                1
+                
+                
+                
+                
+                
+            
+        
+        
+            CUSTOM
+            3
+            
+                
+                
+                0
+            
+        
+        
+            BICOMP
+            0
+            
+        
+        
+            BUILDACTION
+            1
+            
+                
+                
+            
+        
+        
+            ILINK
+            0
+            
+                22
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            IARCHIVE
+            0
+            
+                0
+                1
+                1
+                
+                
+                
+            
+        
+        
+            BILINK
+            0
+            
+        
+    
+    
+        Release
+        
+            ARM
+        
+        0
+        
+            General
+            3
+            
+                31
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            ICCARM
+            2
+            
+                35
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            AARM
+            2
+            
+                10
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            OBJCOPY
+            0
+            
+                1
+                1
+                0
+                
+                
+                
+                
+                
+            
+        
+        
+            CUSTOM
+            3
+            
+                
+                
+                0
+            
+        
+        
+            BICOMP
+            0
+            
+        
+        
+            BUILDACTION
+            1
+            
+                
+                
+            
+        
+        
+            ILINK
+            0
+            
+                22
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            IARCHIVE
+            0
+            
+                0
+                1
+                0
+                
+                
+                
+            
+        
+        
+            BILINK
+            0
+            
+        
+    
+
diff --git a/bsp/stm32/stm32h750-artpi-h750/template.eww b/bsp/stm32/stm32h750-artpi-h750/template.eww
new file mode 100644
index 0000000000..bd036bb4c9
--- /dev/null
+++ b/bsp/stm32/stm32h750-artpi-h750/template.eww
@@ -0,0 +1,10 @@
+
+
+
+  
+    $WS_DIR$\template.ewp
+  
+  
+
+
+
diff --git a/bsp/stm32/stm32f103-mini-system/project.uvoptx b/bsp/stm32/stm32h750-artpi-h750/template.uvoptx
similarity index 73%
rename from bsp/stm32/stm32f103-mini-system/project.uvoptx
rename to bsp/stm32/stm32h750-artpi-h750/template.uvoptx
index 2a5ee7712d..790ef328e8 100644
--- a/bsp/stm32/stm32f103-mini-system/project.uvoptx
+++ b/bsp/stm32/stm32h750-artpi-h750/template.uvoptx
@@ -45,7 +45,7 @@
         79
         66
         8
-        .\build\keil\List\
+        .\build\
       
       
         1
@@ -73,33 +73,11 @@
         0
       
       
-        1
+        0
         0
         1
       
       18
-      
-        
-          0
-          Base Board Schematics (MCBSTM32E)
-          I:\MDK5\MDK5\ARM\PACK\Keil\STM32F1xx_DFP\1.0.5\Documents\mcbstm32e-base-board-schematics.pdf
-        
-        
-          1
-          Display Board Schematics (MCBSTM32E)
-          I:\MDK5\MDK5\ARM\PACK\Keil\STM32F1xx_DFP\1.0.5\Documents\mcbstm32e-display-board-schematics.pdf
-        
-        
-          2
-          User Manual (MCBSTM32E)
-          I:\MDK5\MDK5\ARM\PACK\Keil\STM32F1xx_DFP\1.0.5\Documents\mcbstm32e.chm
-        
-        
-          3
-          MCBSTM32E Evaluation Board Web Page (MCBSTM32E)
-          http://www.keil.com/mcbstm32e/
-        
-      
       
         0
         1
@@ -122,7 +100,10 @@
         1
         0
         0
-        1
+        1
+        0
+        0
+        6
         
         
         
@@ -133,18 +114,18 @@
         
         
         
-        BIN\UL2CM3.DLL
+        STLink\ST-LINKIII-KEIL_SWO.dll
       
       
         
           0
-          JL2CM3
-          -U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 )  -FN1 -FC1000 -FD20000000 -FF0STM32H7x_128k -FL020000 -FS08000000 -FP0($$Device:STM32H750XBHx$CMSIS\Flash\STM32H7x_128k.FLM)
         
         
           0
-          UL2CM3
-          UL2CM3(-S0 -C0 -P0 )  -FN1 -FC1000 -FD20000000 -FF0STM32F10x_128 -FL020000 -FS08000000 -FP0($$Device:STM32F103C8$Flash\STM32F10x_128.FLM)
+          ST-LINKIII-KEIL_SWO
+          -U066BFF393732484257162540 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32H7x_128k -FS08000000 -FL020000
         
       
       
@@ -179,8 +160,20 @@
       
       
       
+      0
+      0
+      0
+      
+      
+      
+      
+      
+      
+      
+      
       
         1
+        1
         0
         2
         10000000
@@ -188,12 +181,4 @@
     
   
 
-  
-    Source Group 1
-    0
-    0
-    0
-    0
-  
-
 
diff --git a/bsp/stm32/stm32h750-artpi-h750/template.uvprojx b/bsp/stm32/stm32h750-artpi-h750/template.uvprojx
new file mode 100644
index 0000000000..d12a55c27c
--- /dev/null
+++ b/bsp/stm32/stm32h750-artpi-h750/template.uvprojx
@@ -0,0 +1,390 @@
+
+
+
+  2.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      rt-thread
+      0x4
+      ARM-ADS
+      5060750::V5.06 update 6 (build 750)::ARMCC
+      0
+      
+        
+          STM32H750XBHx
+          STMicroelectronics
+          Keil.STM32H7xx_DFP.2.5.0
+          http://www.keil.com/pack/
+          IRAM(0x20000000,0x00020000) IRAM2(0x24000000,0x00080000) IROM(0x08000000,0x00020000) XRAM(0x30000000,0x00048000) XRAM2(0x38000000,0x00010000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE
+          
+          
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32H7x_128k -FS08000000 -FL020000 -FP0($$Device:STM32H750XBHx$CMSIS\Flash\STM32H7x_128k.FLM))
+          0
+          $$Device:STM32H750XBHx$Drivers\CMSIS\Device\ST\STM32H7xx\Include\stm32h7xx.h
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32H750XBHx$CMSIS\SVD\STM32H750x.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          .\build\
+          rt-thread
+          1
+          0
+          0
+          1
+          0
+          .\build\
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            1
+            0
+            fromelf --bin !L --output rtthread.bin
+            
+            0
+            0
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          1
+        
+        
+          SARMCM3.DLL
+           -REMAP -MPU
+          DCM.DLL
+          -pCM7
+          SARMCM3.DLL
+           -MPU
+          TCM.DLL
+          -pCM7
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4096
+          
+          1
+          BIN\UL2CM3.DLL
+          
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M7"
+            
+            0
+            0
+            0
+            1
+            1
+            1
+            0
+            3
+            0
+            1
+            0
+            8
+            1
+            0
+            0
+            0
+            3
+            4
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            1
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x20000
+              
+              
+                1
+                0x8000000
+                0x20000
+              
+              
+                1
+                0x30000000
+                0x48000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x20000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x30000000
+                0x48000
+              
+              
+                0
+                0x38000000
+                0x10000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x20000
+              
+              
+                0
+                0x24000000
+                0x80000
+              
+            
+            
+          
+          
+            1
+            1
+            0
+            0
+            1
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            0
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            .\board\linker_scripts\link.sct
+            
+            
+            
+            
+            
+          
+        
+      
+    
+  
+
+  
+    
+    
+    
+  
+
+
diff --git a/bsp/stm32/stm32l010-st-nucleo/applications/main.c b/bsp/stm32/stm32l010-st-nucleo/applications/main.c
index 8541bd3b9f..a438b9e67d 100644
--- a/bsp/stm32/stm32l010-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32l010-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32l010-st-nucleo/board/board.c b/bsp/stm32/stm32l010-st-nucleo/board/board.c
index 858d59660f..62621eed0a 100644
--- a/bsp/stm32/stm32l010-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32l010-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,11 +17,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct;
   RCC_PeriphCLKInitTypeDef PeriphClkInit;
 
-    /**Configure the main internal regulator output voltage 
+    /**Configure the main internal regulator output voltage
     */
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 
-    /**Initializes the CPU, AHB and APB busses clocks 
+    /**Initializes the CPU, AHB and APB busses clocks
     */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
@@ -35,7 +35,7 @@ void SystemClock_Config(void)
     _Error_Handler(__FILE__, __LINE__);
   }
 
-    /**Initializes the CPU, AHB and APB busses clocks 
+    /**Initializes the CPU, AHB and APB busses clocks
     */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
@@ -56,11 +56,11 @@ void SystemClock_Config(void)
     _Error_Handler(__FILE__, __LINE__);
   }
 
-    /**Configure the Systick interrupt time 
+    /**Configure the Systick interrupt time
     */
   HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
 
-    /**Configure the Systick 
+    /**Configure the Systick
     */
   HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
 
diff --git a/bsp/stm32/stm32l010-st-nucleo/board/board.h b/bsp/stm32/stm32l010-st-nucleo/board/board.h
index 9ca68af470..67e4ad5ec0 100644
--- a/bsp/stm32/stm32l010-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32l010-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l053-st-nucleo/applications/main.c b/bsp/stm32/stm32l053-st-nucleo/applications/main.c
index 8541bd3b9f..a438b9e67d 100644
--- a/bsp/stm32/stm32l053-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32l053-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32l053-st-nucleo/board/board.c b/bsp/stm32/stm32l053-st-nucleo/board/board.c
index 858d59660f..62621eed0a 100644
--- a/bsp/stm32/stm32l053-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32l053-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,11 +17,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct;
   RCC_PeriphCLKInitTypeDef PeriphClkInit;
 
-    /**Configure the main internal regulator output voltage 
+    /**Configure the main internal regulator output voltage
     */
   __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 
-    /**Initializes the CPU, AHB and APB busses clocks 
+    /**Initializes the CPU, AHB and APB busses clocks
     */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
@@ -35,7 +35,7 @@ void SystemClock_Config(void)
     _Error_Handler(__FILE__, __LINE__);
   }
 
-    /**Initializes the CPU, AHB and APB busses clocks 
+    /**Initializes the CPU, AHB and APB busses clocks
     */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
@@ -56,11 +56,11 @@ void SystemClock_Config(void)
     _Error_Handler(__FILE__, __LINE__);
   }
 
-    /**Configure the Systick interrupt time 
+    /**Configure the Systick interrupt time
     */
   HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
 
-    /**Configure the Systick 
+    /**Configure the Systick
     */
   HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
 
diff --git a/bsp/stm32/stm32l053-st-nucleo/board/board.h b/bsp/stm32/stm32l053-st-nucleo/board/board.h
index 016e4ec4e3..f88ee51946 100644
--- a/bsp/stm32/stm32l053-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32l053-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l412-st-nucleo/applications/main.c b/bsp/stm32/stm32l412-st-nucleo/applications/main.c
index 2511e7a3bc..296c33d352 100644
--- a/bsp/stm32/stm32l412-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32l412-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LD4 pin mode to output */
     rt_pin_mode(LD4_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LD4_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LD4_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32l412-st-nucleo/board/Kconfig b/bsp/stm32/stm32l412-st-nucleo/board/Kconfig
index 10d3a3ad30..c38c20d2be 100644
--- a/bsp/stm32/stm32l412-st-nucleo/board/Kconfig
+++ b/bsp/stm32/stm32l412-st-nucleo/board/Kconfig
@@ -44,7 +44,6 @@ menu "On-chip Peripheral Drivers"
     menuconfig BSP_USING_ONCHIP_RTC
         bool "Enable RTC"
         select RT_USING_RTC
-        select RT_USING_LIBC
         default n
         if BSP_USING_ONCHIP_RTC
             choice
diff --git a/bsp/stm32/stm32l412-st-nucleo/board/board.c b/bsp/stm32/stm32l412-st-nucleo/board/board.c
index 70a17da702..1ac2bc2df9 100644
--- a/bsp/stm32/stm32l412-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32l412-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,13 +17,13 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct;
   RCC_PeriphCLKInitTypeDef PeriphClkInit;
 
-    /**Configure LSE Drive Capability 
+    /**Configure LSE Drive Capability
     */
   HAL_PWR_EnableBkUpAccess();
 
   __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
 
-    /**Initializes the CPU, AHB and APB busses clocks 
+    /**Initializes the CPU, AHB and APB busses clocks
     */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI;
   RCC_OscInitStruct.LSEState = RCC_LSE_ON;
@@ -41,7 +41,7 @@ void SystemClock_Config(void)
     _Error_Handler(__FILE__, __LINE__);
   }
 
-    /**Initializes the CPU, AHB and APB busses clocks 
+    /**Initializes the CPU, AHB and APB busses clocks
     */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
@@ -62,22 +62,22 @@ void SystemClock_Config(void)
     _Error_Handler(__FILE__, __LINE__);
   }
 
-    /**Configure the main internal regulator output voltage 
+    /**Configure the main internal regulator output voltage
     */
   if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
   {
     _Error_Handler(__FILE__, __LINE__);
   }
 
-    /**Configure the Systick interrupt time 
+    /**Configure the Systick interrupt time
     */
   HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
 
-    /**Configure the Systick 
+    /**Configure the Systick
     */
   HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
 
-    /**Enable MSI Auto calibration 
+    /**Enable MSI Auto calibration
     */
   HAL_RCCEx_EnableMSIPLLMode();
 
diff --git a/bsp/stm32/stm32l412-st-nucleo/board/board.h b/bsp/stm32/stm32l412-st-nucleo/board/board.h
index e88c9168b4..1f1519158f 100644
--- a/bsp/stm32/stm32l412-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32l412-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l431-BearPi/.config b/bsp/stm32/stm32l431-BearPi/.config
index 9ede141fd9..3f4c90a8ba 100644
--- a/bsp/stm32/stm32l431-BearPi/.config
+++ b/bsp/stm32/stm32l431-BearPi/.config
@@ -134,7 +134,12 @@ CONFIG_RT_USING_RTC=y
 # CONFIG_RT_USING_ALARM is not set
 # CONFIG_RT_USING_SOFT_RTC is not set
 # CONFIG_RT_USING_SDIO is not set
-# CONFIG_RT_USING_SPI is not set
+CONFIG_RT_USING_SPI=y
+# CONFIG_RT_USING_QSPI is not set
+# CONFIG_RT_USING_SPI_MSD is not set
+# CONFIG_RT_USING_SFUD is not set
+# CONFIG_RT_USING_ENC28J60 is not set
+# CONFIG_RT_USING_SPI_WIFI is not set
 CONFIG_RT_USING_WDT=y
 # CONFIG_RT_USING_AUDIO is not set
 # CONFIG_RT_USING_SENSOR is not set
@@ -316,6 +321,7 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_RDB is not set
 # CONFIG_PKG_USING_QRCODE is not set
 # CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
 # CONFIG_PKG_USING_ADBD is not set
 # CONFIG_PKG_USING_COREMARK is not set
 # CONFIG_PKG_USING_DHRYSTONE is not set
@@ -331,6 +337,7 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_CPU_USAGE is not set
 # CONFIG_PKG_USING_GBK2UTF8 is not set
 # CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
 
 #
 # system packages
@@ -370,6 +377,7 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_UC_MODBUS is not set
 # CONFIG_PKG_USING_PPOOL is not set
 # CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RT_PRINTF is not set
 
 #
 # peripheral libraries and drivers
@@ -378,6 +386,7 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_REALTEK_AMEBA is not set
 # CONFIG_PKG_USING_SHT2X is not set
 # CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AS7341 is not set
 # CONFIG_PKG_USING_STM32_SDIO is not set
 # CONFIG_PKG_USING_ICM20608 is not set
 # CONFIG_PKG_USING_U8G2 is not set
@@ -430,6 +439,7 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_NES is not set
 # CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
 # CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
 
 #
 # miscellaneous packages
@@ -494,6 +504,16 @@ CONFIG_BSP_USING_GPIO=y
 CONFIG_BSP_USING_UART=y
 CONFIG_BSP_USING_UART1=y
 # CONFIG_BSP_UART1_RX_USING_DMA is not set
+# CONFIG_BSP_USING_I2C is not set
+CONFIG_BSP_USING_SPI=y
+CONFIG_BSP_USING_SPI2=y
+# CONFIG_BSP_SPI2_TX_USING_DMA is not set
+# CONFIG_BSP_SPI2_RX_USING_DMA is not set
 # CONFIG_BSP_USING_CRC is not set
 # CONFIG_BSP_USING_RNG is not set
 # CONFIG_BSP_USING_UDID is not set
+
+#
+# Onboard Peripheral Drivers
+#
+CONFIG_BSP_USING_SPI_LCD=y
diff --git a/bsp/stm32/stm32l431-BearPi/applications/main.c b/bsp/stm32/stm32l431-BearPi/applications/main.c
index 8bda11b8cd..b5409814f6 100644
--- a/bsp/stm32/stm32l431-BearPi/applications/main.c
+++ b/bsp/stm32/stm32l431-BearPi/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,19 +17,15 @@
 
 int main(void)
 {
-  int count = 1;
+    rt_kprintf("---Welcome use BearPi---\n");
+    /* set LED pin mode to output */
+    rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-  rt_kprintf("---Welcome use BearPi---\n");
-  /* set LED pin mode to output */
-  rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
-
-  while (count++)
-  {
-    rt_pin_write(LED0_PIN, PIN_HIGH);
-    rt_thread_mdelay(500);
-    rt_pin_write(LED0_PIN, PIN_LOW);
-    rt_thread_mdelay(500);
-  }
-
-  return RT_EOK;
+    while (1)
+    {
+        rt_pin_write(LED0_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED0_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
 }
diff --git a/bsp/stm32/stm32l431-BearPi/board/CubeMX_Config/.mxproject b/bsp/stm32/stm32l431-BearPi/board/CubeMX_Config/.mxproject
index 568f4ba3ec..77c9bb99d3 100644
--- a/bsp/stm32/stm32l431-BearPi/board/CubeMX_Config/.mxproject
+++ b/bsp/stm32/stm32l431-BearPi/board/CubeMX_Config/.mxproject
@@ -1,14 +1,14 @@
 [PreviousGenFiles]
-HeaderPath=D:/Users/rtt/Desktop/CubeMX_Config/Inc
+HeaderPath=D:/Rtt_doc/rt-thread/bsp/stm32/stm32l431-BearPi/board/CubeMX_Config/Inc
 HeaderFiles=stm32l4xx_it.h;stm32l4xx_hal_conf.h;main.h;
-SourcePath=D:/Users/rtt/Desktop/CubeMX_Config/Src
+SourcePath=D:/Rtt_doc/rt-thread/bsp/stm32/stm32l431-BearPi/board/CubeMX_Config/Src
 SourceFiles=stm32l4xx_it.c;stm32l4xx_hal_msp.c;main.c;
 
 [PreviousLibFiles]
-LibFiles=Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l431xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h;
+LibFiles=Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l431xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h;
 
 [PreviousUsedKeilFiles]
-SourceFiles=..\Src\main.c;..\Src\stm32l4xx_it.c;..\Src\stm32l4xx_hal_msp.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;..\\Src/system_stm32l4xx.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;..\\Src/system_stm32l4xx.c;..\Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;;
+SourceFiles=..\Src\main.c;..\Src\stm32l4xx_it.c;..\Src\stm32l4xx_hal_msp.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;..\\Src/system_stm32l4xx.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;..\Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;..\\Src/system_stm32l4xx.c;..\Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;;
 HeaderPath=..\Drivers\STM32L4xx_HAL_Driver\Inc;..\Drivers\STM32L4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32L4xx\Include;..\Drivers\CMSIS\Include;..\Inc;
 CDefines=USE_HAL_DRIVER;STM32L431xx;USE_HAL_DRIVER;USE_HAL_DRIVER;
 
diff --git a/bsp/stm32/stm32l431-BearPi/board/CubeMX_Config/CubeMX_Config.ioc b/bsp/stm32/stm32l431-BearPi/board/CubeMX_Config/CubeMX_Config.ioc
index 79ec749333..ce0175ce52 100644
--- a/bsp/stm32/stm32l431-BearPi/board/CubeMX_Config/CubeMX_Config.ioc
+++ b/bsp/stm32/stm32l431-BearPi/board/CubeMX_Config/CubeMX_Config.ioc
@@ -5,19 +5,22 @@ KeepUserPlacement=false
 Mcu.Family=STM32L4
 Mcu.IP0=NVIC
 Mcu.IP1=RCC
-Mcu.IP2=SYS
-Mcu.IP3=USART1
-Mcu.IPNb=4
+Mcu.IP2=SPI2
+Mcu.IP3=SYS
+Mcu.IP4=USART1
+Mcu.IPNb=5
 Mcu.Name=STM32L431R(B-C)Tx
 Mcu.Package=LQFP64
 Mcu.Pin0=PC14-OSC32_IN (PC14)
 Mcu.Pin1=PC15-OSC32_OUT (PC15)
 Mcu.Pin2=PH0-OSC_IN (PH0)
 Mcu.Pin3=PH1-OSC_OUT (PH1)
-Mcu.Pin4=PA9
-Mcu.Pin5=PA10
-Mcu.Pin6=VP_SYS_VS_Systick
-Mcu.PinsNb=7
+Mcu.Pin4=PC3
+Mcu.Pin5=PB13
+Mcu.Pin6=PA9
+Mcu.Pin7=PA10
+Mcu.Pin8=VP_SYS_VS_Systick
+Mcu.PinsNb=9
 Mcu.ThirdPartyNb=0
 Mcu.UserConstants=
 Mcu.UserName=STM32L431RCTx
@@ -40,12 +43,18 @@ PA10.Signal=USART1_RX
 PA9.Locked=true
 PA9.Mode=Asynchronous
 PA9.Signal=USART1_TX
+PB13.Locked=true
+PB13.Mode=Simplex_Bidirectional_Master
+PB13.Signal=SPI2_SCK
 PC14-OSC32_IN\ (PC14).Locked=true
 PC14-OSC32_IN\ (PC14).Mode=LSE-External-Oscillator
 PC14-OSC32_IN\ (PC14).Signal=RCC_OSC32_IN
 PC15-OSC32_OUT\ (PC15).Locked=true
 PC15-OSC32_OUT\ (PC15).Mode=LSE-External-Oscillator
 PC15-OSC32_OUT\ (PC15).Signal=RCC_OSC32_OUT
+PC3.Locked=true
+PC3.Mode=Simplex_Bidirectional_Master
+PC3.Signal=SPI2_MOSI
 PH0-OSC_IN\ (PH0).Locked=true
 PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator
 PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN
@@ -121,6 +130,11 @@ RCC.USART3Freq_Value=80000000
 RCC.VCOInputFreq_Value=4000000
 RCC.VCOOutputFreq_Value=160000000
 RCC.VCOSAI1OutputFreq_Value=32000000
+SPI2.CalculateBaudRate=40.0 MBits/s
+SPI2.Direction=SPI_DIRECTION_1LINE
+SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate
+SPI2.Mode=SPI_MODE_MASTER
+SPI2.VirtualType=VM_MASTER
 USART1.IPParameters=VirtualMode-Asynchronous
 USART1.VirtualMode-Asynchronous=VM_ASYNC
 VP_SYS_VS_Systick.Mode=SysTick
diff --git a/bsp/stm32/stm32l431-BearPi/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h b/bsp/stm32/stm32l431-BearPi/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h
index 347da3fe30..b425dbbe58 100644
--- a/bsp/stm32/stm32l431-BearPi/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h
+++ b/bsp/stm32/stm32l431-BearPi/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h
@@ -5,7 +5,7 @@
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2020 STMicroelectronics

+  * 
© COPYRIGHT(c) 2021 STMicroelectronics

   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -86,7 +86,7 @@
 /*#define HAL_SD_MODULE_ENABLED   */
 /*#define HAL_SMBUS_MODULE_ENABLED   */
 /*#define HAL_SMARTCARD_MODULE_ENABLED   */
-/*#define HAL_SPI_MODULE_ENABLED   */
+#define HAL_SPI_MODULE_ENABLED
 /*#define HAL_SRAM_MODULE_ENABLED   */
 /*#define HAL_SWPMI_MODULE_ENABLED   */
 /*#define HAL_TIM_MODULE_ENABLED   */
diff --git a/bsp/stm32/stm32l431-BearPi/board/CubeMX_Config/Src/main.c b/bsp/stm32/stm32l431-BearPi/board/CubeMX_Config/Src/main.c
index f3fe151ae7..bdd3967d6a 100644
--- a/bsp/stm32/stm32l431-BearPi/board/CubeMX_Config/Src/main.c
+++ b/bsp/stm32/stm32l431-BearPi/board/CubeMX_Config/Src/main.c
@@ -41,6 +41,8 @@
 /* USER CODE END PM */
 
 /* Private variables ---------------------------------------------------------*/
+SPI_HandleTypeDef hspi2;
+
 UART_HandleTypeDef huart1;
 
 /* USER CODE BEGIN PV */
@@ -50,6 +52,7 @@ UART_HandleTypeDef huart1;
 /* Private function prototypes -----------------------------------------------*/
 void SystemClock_Config(void);
 static void MX_GPIO_Init(void);
+static void MX_SPI2_Init(void);
 static void MX_USART1_UART_Init(void);
 /* USER CODE BEGIN PFP */
 
@@ -88,6 +91,7 @@ int main(void)
 
   /* Initialize all configured peripherals */
   MX_GPIO_Init();
+  MX_SPI2_Init();
   MX_USART1_UART_Init();
   /* USER CODE BEGIN 2 */
 
@@ -166,6 +170,46 @@ void SystemClock_Config(void)
   HAL_RCCEx_EnableMSIPLLMode();
 }
 
+/**
+  * @brief SPI2 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_SPI2_Init(void)
+{
+
+  /* USER CODE BEGIN SPI2_Init 0 */
+
+  /* USER CODE END SPI2_Init 0 */
+
+  /* USER CODE BEGIN SPI2_Init 1 */
+
+  /* USER CODE END SPI2_Init 1 */
+  /* SPI2 parameter configuration*/
+  hspi2.Instance = SPI2;
+  hspi2.Init.Mode = SPI_MODE_MASTER;
+  hspi2.Init.Direction = SPI_DIRECTION_1LINE;
+  hspi2.Init.DataSize = SPI_DATASIZE_4BIT;
+  hspi2.Init.CLKPolarity = SPI_POLARITY_LOW;
+  hspi2.Init.CLKPhase = SPI_PHASE_1EDGE;
+  hspi2.Init.NSS = SPI_NSS_SOFT;
+  hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
+  hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB;
+  hspi2.Init.TIMode = SPI_TIMODE_DISABLE;
+  hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+  hspi2.Init.CRCPolynomial = 7;
+  hspi2.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
+  hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
+  if (HAL_SPI_Init(&hspi2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN SPI2_Init 2 */
+
+  /* USER CODE END SPI2_Init 2 */
+
+}
+
 /**
   * @brief USART1 Initialization Function
   * @param None
@@ -212,6 +256,7 @@ static void MX_GPIO_Init(void)
   /* GPIO Ports Clock Enable */
   __HAL_RCC_GPIOC_CLK_ENABLE();
   __HAL_RCC_GPIOH_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
   __HAL_RCC_GPIOA_CLK_ENABLE();
 
 }
diff --git a/bsp/stm32/stm32l431-BearPi/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c b/bsp/stm32/stm32l431-BearPi/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c
index 45d1b1a9e2..943aadf254 100644
--- a/bsp/stm32/stm32l431-BearPi/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c
+++ b/bsp/stm32/stm32l431-BearPi/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c
@@ -77,6 +77,81 @@ void HAL_MspInit(void)
   /* USER CODE END MspInit 1 */
 }
 
+/**
+* @brief SPI MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hspi: SPI handle pointer
+* @retval None
+*/
+void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hspi->Instance==SPI2)
+  {
+  /* USER CODE BEGIN SPI2_MspInit 0 */
+
+  /* USER CODE END SPI2_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_SPI2_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**SPI2 GPIO Configuration    
+    PC3     ------> SPI2_MOSI
+    PB13     ------> SPI2_SCK 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_3;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_13;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN SPI2_MspInit 1 */
+
+  /* USER CODE END SPI2_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief SPI MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hspi: SPI handle pointer
+* @retval None
+*/
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
+{
+  if(hspi->Instance==SPI2)
+  {
+  /* USER CODE BEGIN SPI2_MspDeInit 0 */
+
+  /* USER CODE END SPI2_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_SPI2_CLK_DISABLE();
+  
+    /**SPI2 GPIO Configuration    
+    PC3     ------> SPI2_MOSI
+    PB13     ------> SPI2_SCK 
+    */
+    HAL_GPIO_DeInit(GPIOC, GPIO_PIN_3);
+
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13);
+
+  /* USER CODE BEGIN SPI2_MspDeInit 1 */
+
+  /* USER CODE END SPI2_MspDeInit 1 */
+  }
+
+}
+
 /**
 * @brief UART MSP Initialization
 * This function configures the hardware resources used in this example
diff --git a/bsp/stm32/stm32l431-BearPi/board/Kconfig b/bsp/stm32/stm32l431-BearPi/board/Kconfig
index 49cc8cadc9..1c8e42c3fd 100644
--- a/bsp/stm32/stm32l431-BearPi/board/Kconfig
+++ b/bsp/stm32/stm32l431-BearPi/board/Kconfig
@@ -29,8 +29,37 @@ menu "On-chip Peripheral Drivers"
                 default n
         endif
 
+    menuconfig BSP_USING_SPI
+        bool "Enable SPI BUS"
+        default n
+        select RT_USING_SPI
+        if BSP_USING_SPI
+            config BSP_USING_SPI2
+                bool "Enable SPI2 BUS"
+                default n
+
+            config BSP_SPI2_TX_USING_DMA
+                bool "Enable SPI2 TX DMA"
+                depends on BSP_USING_SPI2
+                default n
+                
+            config BSP_SPI2_RX_USING_DMA
+                bool "Enable SPI2 RX DMA"
+                depends on BSP_USING_SPI2
+                select BSP_SPI2_TX_USING_DMA
+                default n
+        endif
+
     source "../libraries/HAL_Drivers/Kconfig"
     
 endmenu
 
+menu "Onboard Peripheral Drivers"
+    config BSP_USING_SPI_LCD
+        bool "Enable LCD (spi2)"
+        select BSP_USING_SPI
+        select BSP_USING_SPI2
+        default n
+endmenu
+
 endmenu
diff --git a/bsp/stm32/stm32l431-BearPi/board/SConscript b/bsp/stm32/stm32l431-BearPi/board/SConscript
index c95510d979..aade0f780a 100644
--- a/bsp/stm32/stm32l431-BearPi/board/SConscript
+++ b/bsp/stm32/stm32l431-BearPi/board/SConscript
@@ -12,9 +12,12 @@ board.c
 CubeMX_Config/Src/stm32l4xx_hal_msp.c
 ''')
 
+if GetDepend('BSP_USING_SPI_LCD'):
+    src += ['ports/lcd/drv_lcd.c']
+
 path =  [cwd]
 path += [cwd + '/CubeMX_Config/Inc']
-
+path += [cwd + '/ports/lcd']
 startup_path_prefix = SDK_LIB
 
 if rtconfig.CROSS_TOOL == 'gcc':
@@ -33,7 +36,7 @@ elif rtconfig.CROSS_TOOL == 'iar':
 # STM32L4R7xx || STM32L4R9xx || STM32L4S5xx
 # STM32L4S7xx || STM32L4S9xx
 # You can select chips from the list above	
-CPPDEFINES = ['STM32L432xx']
+CPPDEFINES = ['STM32L431xx']
 group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
 
 Return('group')
diff --git a/bsp/stm32/stm32l431-BearPi/board/board.c b/bsp/stm32/stm32l431-BearPi/board/board.c
index 368ab74da1..b1a9d3d860 100644
--- a/bsp/stm32/stm32l431-BearPi/board/board.c
+++ b/bsp/stm32/stm32l431-BearPi/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,13 +16,13 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct;
   RCC_PeriphCLKInitTypeDef PeriphClkInit;
 
-    /**Configure LSE Drive Capability 
+    /**Configure LSE Drive Capability
     */
   HAL_PWR_EnableBkUpAccess();
 
   __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
 
-    /**Initializes the CPU, AHB and APB busses clocks 
+    /**Initializes the CPU, AHB and APB busses clocks
     */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_LSE
                               |RCC_OSCILLATORTYPE_MSI;
@@ -43,7 +43,7 @@ void SystemClock_Config(void)
     _Error_Handler(__FILE__, __LINE__);
   }
 
-    /**Initializes the CPU, AHB and APB busses clocks 
+    /**Initializes the CPU, AHB and APB busses clocks
     */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
@@ -65,22 +65,22 @@ void SystemClock_Config(void)
     _Error_Handler(__FILE__, __LINE__);
   }
 
-    /**Configure the main internal regulator output voltage 
+    /**Configure the main internal regulator output voltage
     */
   if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
   {
     _Error_Handler(__FILE__, __LINE__);
   }
 
-    /**Configure the Systick interrupt time 
+    /**Configure the Systick interrupt time
     */
   HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
 
-    /**Configure the Systick 
+    /**Configure the Systick
     */
   HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
 
-    /**Enable MSI Auto calibration 
+    /**Enable MSI Auto calibration
     */
   HAL_RCCEx_EnableMSIPLLMode();
 
diff --git a/bsp/stm32/stm32l431-BearPi/board/board.h b/bsp/stm32/stm32l431-BearPi/board/board.h
index 3b3a77e103..77db7fce6e 100644
--- a/bsp/stm32/stm32l431-BearPi/board/board.h
+++ b/bsp/stm32/stm32l431-BearPi/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l431-BearPi/board/ports/SConscript b/bsp/stm32/stm32l431-BearPi/board/ports/SConscript
new file mode 100644
index 0000000000..ca95be14e2
--- /dev/null
+++ b/bsp/stm32/stm32l431-BearPi/board/ports/SConscript
@@ -0,0 +1,12 @@
+import os
+from building import *
+
+objs = []
+cwd  = GetCurrentDir()
+list = os.listdir(cwd)
+
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        objs = objs + SConscript(os.path.join(item, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/stm32/stm32l431-BearPi/board/ports/lcd/SConscript b/bsp/stm32/stm32l431-BearPi/board/ports/lcd/SConscript
new file mode 100644
index 0000000000..2f243d9b00
--- /dev/null
+++ b/bsp/stm32/stm32l431-BearPi/board/ports/lcd/SConscript
@@ -0,0 +1,13 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+src += Glob('*.c')
+
+CPPPATH = [cwd]
+
+group = DefineGroup('devices', src, depend = ['BSP_USING_SPI_LCD'], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/stm32/stm32l431-BearPi/board/ports/lcd/drv_lcd.c b/bsp/stm32/stm32l431-BearPi/board/ports/lcd/drv_lcd.c
new file mode 100644
index 0000000000..6150a5b184
--- /dev/null
+++ b/bsp/stm32/stm32l431-BearPi/board/ports/lcd/drv_lcd.c
@@ -0,0 +1,821 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-01-05     RiceChen          the first version
+ */
+
+#include 
+#include "drv_spi.h"
+#include "drv_lcd.h"
+#include "drv_lcd_font.h"
+#include "drv_gpio.h"
+
+#define DBG_SECTION_NAME    "LCD"
+#define DBG_COLOR
+#define DBG_LEVEL           DBG_LOG
+#include 
+
+#define LCD_PWR_PIN           GET_PIN(B, 15)
+#define LCD_DC_PIN            GET_PIN(C, 6)
+#define LCD_RES_PIN           GET_PIN(C, 7)
+#define LCD_CLEAR_SEND_NUMBER 5760
+
+rt_uint16_t BACK_COLOR = WHITE, FORE_COLOR = BLACK;
+
+static struct rt_spi_device *spi_dev_lcd;
+
+static int rt_hw_lcd_config(void)
+{
+    spi_dev_lcd = (struct rt_spi_device *)rt_device_find("lcd");
+
+    /* config spi */
+    {
+        struct rt_spi_configuration cfg;
+        cfg.data_width = 8;
+        cfg.mode = RT_SPI_MASTER | RT_SPI_MODE_3 | RT_SPI_MSB;
+        cfg.max_hz = 42 * 1000 * 1000; /* 42M,SPI max 42MHz,lcd 4-wire spi */
+
+        rt_spi_configure(spi_dev_lcd, &cfg);
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t lcd_write_cmd(const rt_uint8_t cmd)
+{
+    rt_size_t len;
+
+    rt_pin_write(LCD_DC_PIN, PIN_LOW);
+
+    len = rt_spi_send(spi_dev_lcd, &cmd, 1);
+
+    if (len != 1)
+    {
+        LOG_I("lcd_write_cmd error. %d", len);
+        return -RT_ERROR;
+    }
+    else
+    {
+        return RT_EOK;
+    }
+}
+
+static rt_err_t lcd_write_data(const rt_uint8_t data)
+{
+    rt_size_t len;
+
+    rt_pin_write(LCD_DC_PIN, PIN_HIGH);
+
+    len = rt_spi_send(spi_dev_lcd, &data, 1);
+
+    if (len != 1)
+    {
+        LOG_I("lcd_write_data error. %d", len);
+        return -RT_ERROR;
+    }
+    else
+    {
+        return RT_EOK;
+    }
+}
+
+static rt_err_t lcd_write_half_word(const rt_uint16_t da)
+{
+    rt_size_t len;
+    char data[2] = {0};
+
+    data[0] = da >> 8;
+    data[1] = da;
+
+    rt_pin_write(LCD_DC_PIN, PIN_HIGH);
+    len = rt_spi_send(spi_dev_lcd, data, 2);
+    if (len != 2)
+    {
+        LOG_I("lcd_write_half_word error. %d", len);
+        return -RT_ERROR;
+    }
+    else
+    {
+        return RT_EOK;
+    }
+}
+
+static void lcd_gpio_init(void)
+{
+    rt_hw_lcd_config();
+
+    rt_pin_mode(LCD_DC_PIN, PIN_MODE_OUTPUT);
+    rt_pin_mode(LCD_RES_PIN, PIN_MODE_OUTPUT);
+
+    rt_pin_mode(LCD_PWR_PIN, PIN_MODE_OUTPUT);
+    rt_pin_write(LCD_PWR_PIN, PIN_LOW);
+
+    rt_pin_write(LCD_RES_PIN, PIN_LOW);
+    //wait at least 100ms for reset
+    rt_thread_delay(RT_TICK_PER_SECOND / 10);
+    rt_pin_write(LCD_RES_PIN, PIN_HIGH);
+}
+
+static int rt_hw_lcd_init(void)
+{
+    rt_hw_spi_device_attach("spi2", "lcd", GPIOC, GPIO_PIN_3);
+    lcd_gpio_init();
+    /* Memory Data Access Control */
+    lcd_write_cmd(0x36);
+    lcd_write_data(0x00);
+    /* RGB 5-6-5-bit  */
+    lcd_write_cmd(0x3A);
+    lcd_write_data(0x65);
+    /* Porch Setting */
+    lcd_write_cmd(0xB2);
+    lcd_write_data(0x0C);
+    lcd_write_data(0x0C);
+    lcd_write_data(0x00);
+    lcd_write_data(0x33);
+    lcd_write_data(0x33);
+    /*  Gate Control */
+    lcd_write_cmd(0xB7);
+    lcd_write_data(0x72);
+    /* VCOM Setting */
+    lcd_write_cmd(0xBB);
+    lcd_write_data(0x3D);
+    /* LCM Control */
+    lcd_write_cmd(0xC0);
+    lcd_write_data(0x2C);
+    /* VDV and VRH Command Enable */
+    lcd_write_cmd(0xC2);
+    lcd_write_data(0x01);
+    /* VRH Set */
+    lcd_write_cmd(0xC3);
+    lcd_write_data(0x19);
+    /* VDV Set */
+    lcd_write_cmd(0xC4);
+    lcd_write_data(0x20);
+    /* Frame Rate Control in Normal Mode */
+    lcd_write_cmd(0xC6);
+    lcd_write_data(0x0F);
+    /* Power Control 1 */
+    lcd_write_cmd(0xD0);
+    lcd_write_data(0xA4);
+    lcd_write_data(0xA1);
+    /* Positive Voltage Gamma Control */
+    lcd_write_cmd(0xE0);
+    lcd_write_data(0xD0);
+    lcd_write_data(0x04);
+    lcd_write_data(0x0D);
+    lcd_write_data(0x11);
+    lcd_write_data(0x13);
+    lcd_write_data(0x2B);
+    lcd_write_data(0x3F);
+    lcd_write_data(0x54);
+    lcd_write_data(0x4C);
+    lcd_write_data(0x18);
+    lcd_write_data(0x0D);
+    lcd_write_data(0x0B);
+    lcd_write_data(0x1F);
+    lcd_write_data(0x23);
+    /* Negative Voltage Gamma Control */
+    lcd_write_cmd(0xE1);
+    lcd_write_data(0xD0);
+    lcd_write_data(0x04);
+    lcd_write_data(0x0C);
+    lcd_write_data(0x11);
+    lcd_write_data(0x13);
+    lcd_write_data(0x2C);
+    lcd_write_data(0x3F);
+    lcd_write_data(0x44);
+    lcd_write_data(0x51);
+    lcd_write_data(0x2F);
+    lcd_write_data(0x1F);
+    lcd_write_data(0x1F);
+    lcd_write_data(0x20);
+    lcd_write_data(0x23);
+    /* Display Inversion On */
+    lcd_write_cmd(0x21);
+    /* Sleep Out */
+    lcd_write_cmd(0x11);
+    /* wait for power stability */
+    rt_thread_mdelay(100);
+
+    lcd_clear(WHITE);
+		lcd_show_string(0, 0, 32, "RT-Thread");
+
+    /* display on */
+    rt_pin_write(LCD_PWR_PIN, PIN_HIGH);
+    lcd_write_cmd(0x29);
+
+    return RT_EOK;
+}
+INIT_DEVICE_EXPORT(rt_hw_lcd_init);
+
+/**
+ * Set background color and foreground color
+ *
+ * @param   back    background color
+ * @param   fore    fore color
+ *
+ * @return  void
+ */
+void lcd_set_color(rt_uint16_t back, rt_uint16_t fore)
+{
+    BACK_COLOR = back;
+    FORE_COLOR = fore;
+}
+
+void lcd_display_on(void)
+{
+    rt_pin_write(LCD_PWR_PIN, PIN_HIGH);
+}
+
+void lcd_display_off(void)
+{
+    rt_pin_write(LCD_PWR_PIN, PIN_LOW);
+}
+
+/* lcd enter the minimum power consumption mode and backlight off. */
+void lcd_enter_sleep(void)
+{
+    rt_pin_write(LCD_PWR_PIN, PIN_LOW);
+    rt_thread_mdelay(5);
+    lcd_write_cmd(0x10);
+}
+/* lcd turn off sleep mode and backlight on. */
+void lcd_exit_sleep(void)
+{
+    rt_pin_write(LCD_PWR_PIN, PIN_HIGH);
+    rt_thread_mdelay(5);
+    lcd_write_cmd(0x11);
+    rt_thread_mdelay(120);
+}
+
+/**
+ * Set drawing area
+ *
+ * @param   x1      start of x position
+ * @param   y1      start of y position
+ * @param   x2      end of x position
+ * @param   y2      end of y position
+ *
+ * @return  void
+ */
+void lcd_address_set(rt_uint16_t x1, rt_uint16_t y1, rt_uint16_t x2, rt_uint16_t y2)
+{
+    lcd_write_cmd(0x2a);
+    lcd_write_data(x1 >> 8);
+    lcd_write_data(x1);
+    lcd_write_data(x2 >> 8);
+    lcd_write_data(x2);
+
+    lcd_write_cmd(0x2b);
+    lcd_write_data(y1 >> 8);
+    lcd_write_data(y1);
+    lcd_write_data(y2 >> 8);
+    lcd_write_data(y2);
+
+    lcd_write_cmd(0x2C);
+}
+
+/**
+ * clear the lcd.
+ *
+ * @param   color       Fill color
+ *
+ * @return  void
+ */
+void lcd_clear(rt_uint16_t color)
+{
+    rt_uint16_t i, j;
+    rt_uint8_t data[2] = {0};
+    rt_uint8_t *buf = RT_NULL;
+
+    data[0] = color >> 8;
+    data[1] = color;
+    lcd_address_set(0, 0, LCD_W - 1, LCD_H - 1);
+
+    /* 5760 = 240*240/20 */
+    buf = rt_malloc(LCD_CLEAR_SEND_NUMBER);
+    if (buf)
+    {
+        /* 2880 = 5760/2 color is 16 bit */
+        for (j = 0; j < LCD_CLEAR_SEND_NUMBER / 2; j++)
+        {
+            buf[j * 2] =  data[0];
+            buf[j * 2 + 1] =  data[1];
+        }
+
+        rt_pin_write(LCD_DC_PIN, PIN_HIGH);
+        for (i = 0; i < 20; i++)
+        {
+            rt_spi_send(spi_dev_lcd, buf, LCD_CLEAR_SEND_NUMBER);
+        }
+        rt_free(buf);
+    }
+    else
+    {
+        rt_pin_write(LCD_DC_PIN, PIN_HIGH);
+        for (i = 0; i < LCD_W; i++)
+        {
+            for (j = 0; j < LCD_H; j++)
+            {
+                rt_spi_send(spi_dev_lcd, data, 2);
+            }
+        }
+    }
+}
+
+/**
+ * display a point on the lcd.
+ *
+ * @param   x   x position
+ * @param   y   y position
+ *
+ * @return  void
+ */
+void lcd_draw_point(rt_uint16_t x, rt_uint16_t y)
+{
+    lcd_address_set(x, y, x, y);
+    lcd_write_half_word(FORE_COLOR);
+}
+
+/**
+ * display a point on the lcd using the given colour.
+ *
+ * @param   x       x position
+ * @param   y       y position
+ * @param   color   color of point
+ *
+ * @return  void
+ */
+void lcd_draw_point_color(rt_uint16_t x, rt_uint16_t y, rt_uint16_t color)
+{
+    lcd_address_set(x, y, x, y);
+    lcd_write_half_word(color);
+}
+
+/**
+ * full color on the lcd.
+ *
+ * @param   x_start     start of x position
+ * @param   y_start     start of y position
+ * @param   x_end       end of x position
+ * @param   y_end       end of y position
+ * @param   color       Fill color
+ *
+ * @return  void
+ */
+void lcd_fill(rt_uint16_t x_start, rt_uint16_t y_start, rt_uint16_t x_end, rt_uint16_t y_end, rt_uint16_t color)
+{
+    rt_uint16_t i = 0, j = 0;
+    rt_uint32_t size = 0, size_remain = 0;
+    rt_uint8_t *fill_buf = RT_NULL;
+
+    size = (x_end - x_start) * (y_end - y_start) * 2;
+
+    if (size > LCD_CLEAR_SEND_NUMBER)
+    {
+        /* the number of remaining to be filled */
+        size_remain = size - LCD_CLEAR_SEND_NUMBER;
+        size = LCD_CLEAR_SEND_NUMBER;
+    }
+
+    lcd_address_set(x_start, y_start, x_end, y_end);
+
+    fill_buf = (rt_uint8_t *)rt_malloc(size);
+    if (fill_buf)
+    {
+        /* fast fill */
+        while (1)
+        {
+            for (i = 0; i < size / 2; i++)
+            {
+                fill_buf[2 * i] = color >> 8;
+                fill_buf[2 * i + 1] = color;
+            }
+            rt_pin_write(LCD_DC_PIN, PIN_HIGH);
+            rt_spi_send(spi_dev_lcd, fill_buf, size);
+
+            /* Fill completed */
+            if (size_remain == 0)
+                break;
+
+            /* calculate the number of fill next time */
+            if (size_remain > LCD_CLEAR_SEND_NUMBER)
+            {
+                size_remain = size_remain - LCD_CLEAR_SEND_NUMBER;
+            }
+            else
+            {
+                size = size_remain;
+                size_remain = 0;
+            }
+        }
+        rt_free(fill_buf);
+    }
+    else
+    {
+        for (i = y_start; i <= y_end; i++)
+        {
+            for (j = x_start; j <= x_end; j++)lcd_write_half_word(color);
+        }
+    }
+}
+
+/**
+ * display a line on the lcd.
+ *
+ * @param   x1      x1 position
+ * @param   y1      y1 position
+ * @param   x2      x2 position
+ * @param   y2      y2 position
+ *
+ * @return  void
+ */
+void lcd_draw_line(rt_uint16_t x1, rt_uint16_t y1, rt_uint16_t x2, rt_uint16_t y2)
+{
+    rt_uint16_t t;
+    rt_uint32_t i = 0;
+    int xerr = 0, yerr = 0, delta_x, delta_y, distance;
+    int incx, incy, row, col;
+
+    if (y1 == y2)
+    {
+        /* fast draw transverse line */
+        lcd_address_set(x1, y1, x2, y2);
+
+        rt_uint8_t line_buf[480] = {0};
+
+        for (i = 0; i < x2 - x1; i++)
+        {
+            line_buf[2 * i] = FORE_COLOR >> 8;
+            line_buf[2 * i + 1] = FORE_COLOR;
+        }
+
+        rt_pin_write(LCD_DC_PIN, PIN_HIGH);
+        rt_spi_send(spi_dev_lcd, line_buf, (x2 - x1) * 2);
+
+        return ;
+    }
+
+    delta_x = x2 - x1;
+    delta_y = y2 - y1;
+    row = x1;
+    col = y1;
+    if (delta_x > 0)incx = 1;
+    else if (delta_x == 0)incx = 0;
+    else
+    {
+        incx = -1;
+        delta_x = -delta_x;
+    }
+    if (delta_y > 0)incy = 1;
+    else if (delta_y == 0)incy = 0;
+    else
+    {
+        incy = -1;
+        delta_y = -delta_y;
+    }
+    if (delta_x > delta_y)distance = delta_x;
+    else distance = delta_y;
+    for (t = 0; t <= distance + 1; t++)
+    {
+        lcd_draw_point(row, col);
+        xerr += delta_x ;
+        yerr += delta_y ;
+        if (xerr > distance)
+        {
+            xerr -= distance;
+            row += incx;
+        }
+        if (yerr > distance)
+        {
+            yerr -= distance;
+            col += incy;
+        }
+    }
+}
+
+/**
+ * display a rectangle on the lcd.
+ *
+ * @param   x1      x1 position
+ * @param   y1      y1 position
+ * @param   x2      x2 position
+ * @param   y2      y2 position
+ *
+ * @return  void
+ */
+void lcd_draw_rectangle(rt_uint16_t x1, rt_uint16_t y1, rt_uint16_t x2, rt_uint16_t y2)
+{
+    lcd_draw_line(x1, y1, x2, y1);
+    lcd_draw_line(x1, y1, x1, y2);
+    lcd_draw_line(x1, y2, x2, y2);
+    lcd_draw_line(x2, y1, x2, y2);
+}
+
+/**
+ * display a circle on the lcd.
+ *
+ * @param   x       x position of Center
+ * @param   y       y position of Center
+ * @param   r       radius
+ *
+ * @return  void
+ */
+void lcd_draw_circle(rt_uint16_t x0, rt_uint16_t y0, rt_uint8_t r)
+{
+    int a, b;
+    int di;
+    a = 0;
+    b = r;
+    di = 3 - (r << 1);
+    while (a <= b)
+    {
+        lcd_draw_point(x0 - b, y0 - a);
+        lcd_draw_point(x0 + b, y0 - a);
+        lcd_draw_point(x0 - a, y0 + b);
+        lcd_draw_point(x0 - b, y0 - a);
+        lcd_draw_point(x0 - a, y0 - b);
+        lcd_draw_point(x0 + b, y0 + a);
+        lcd_draw_point(x0 + a, y0 - b);
+        lcd_draw_point(x0 + a, y0 + b);
+        lcd_draw_point(x0 - b, y0 + a);
+        a++;
+        //Bresenham
+        if (di < 0)di += 4 * a + 6;
+        else
+        {
+            di += 10 + 4 * (a - b);
+            b--;
+        }
+        lcd_draw_point(x0 + a, y0 + b);
+    }
+}
+
+static void lcd_show_char(rt_uint16_t x, rt_uint16_t y, rt_uint8_t data, rt_uint32_t size)
+{
+    rt_uint8_t temp;
+    rt_uint8_t num = 0;;
+    rt_uint8_t pos, t;
+    rt_uint16_t colortemp = FORE_COLOR;
+    rt_uint8_t *font_buf = RT_NULL;
+
+    if (x > LCD_W - size / 2 || y > LCD_H - size)return;
+
+    data = data - ' ';
+#ifdef ASC2_1608
+    if (size == 16)
+    {
+        lcd_address_set(x, y, x + size / 2 - 1, y + size - 1);//(x,y,x+8-1,y+16-1)
+
+        font_buf = (rt_uint8_t *)rt_malloc(size * size);
+        if (!font_buf)
+        {
+            /* fast show char */
+            for (pos = 0; pos < size * (size / 2) / 8; pos++)
+            {
+                temp = asc2_1608[(rt_uint16_t)data * size * (size / 2) / 8 + pos];
+                for (t = 0; t < 8; t++)
+                {
+                    if (temp & 0x80)colortemp = FORE_COLOR;
+                    else colortemp = BACK_COLOR;
+                    lcd_write_half_word(colortemp);
+                    temp <<= 1;
+                }
+            }
+        }
+        else
+        {
+            for (pos = 0; pos < size * (size / 2) / 8; pos++)
+            {
+                temp = asc2_1608[(rt_uint16_t)data * size * (size / 2) / 8 + pos];
+                for (t = 0; t < 8; t++)
+                {
+                    if (temp & 0x80)colortemp = FORE_COLOR;
+                    else colortemp = BACK_COLOR;
+                    font_buf[2 * (8 * pos + t)] = colortemp >> 8;
+                    font_buf[2 * (8 * pos + t) + 1] = colortemp;
+                    temp <<= 1;
+                }
+            }
+            rt_pin_write(LCD_DC_PIN, PIN_HIGH);
+            rt_spi_send(spi_dev_lcd, font_buf, size * size);
+            rt_free(font_buf);
+        }
+    }
+    else
+#endif
+
+#ifdef ASC2_2412
+        if (size == 24)
+        {
+            lcd_address_set(x, y, x + size / 2 - 1, y + size - 1);
+
+            font_buf = (rt_uint8_t *)rt_malloc(size * size);
+            if (!font_buf)
+            {
+                /* fast show char */
+                for (pos = 0; pos < (size * 16) / 8; pos++)
+                {
+                    temp = asc2_2412[(rt_uint16_t)data * (size * 16) / 8 + pos];
+                    if (pos % 2 == 0)
+                    {
+                        num = 8;
+                    }
+                    else
+                    {
+                        num = 4;
+                    }
+
+                    for (t = 0; t < num; t++)
+                    {
+                        if (temp & 0x80)colortemp = FORE_COLOR;
+                        else colortemp = BACK_COLOR;
+                        lcd_write_half_word(colortemp);
+                        temp <<= 1;
+                    }
+                }
+            }
+            else
+            {
+                for (pos = 0; pos < (size * 16) / 8; pos++)
+                {
+                    temp = asc2_2412[(rt_uint16_t)data * (size * 16) / 8 + pos];
+                    if (pos % 2 == 0)
+                    {
+                        num = 8;
+                    }
+                    else
+                    {
+                        num = 4;
+                    }
+
+                    for (t = 0; t < num; t++)
+                    {
+                        if (temp & 0x80)colortemp = FORE_COLOR;
+                        else colortemp = BACK_COLOR;
+                        if (num == 8)
+                        {
+                            font_buf[2 * (12 * (pos / 2) + t)] = colortemp >> 8;
+                            font_buf[2 * (12 * (pos / 2) + t) + 1] = colortemp;
+                        }
+                        else
+                        {
+                            font_buf[2 * (8 + 12 * (pos / 2) + t)] = colortemp >> 8;
+                            font_buf[2 * (8 + 12 * (pos / 2) + t) + 1] = colortemp;
+                        }
+                        temp <<= 1;
+                    }
+                }
+                rt_pin_write(LCD_DC_PIN, PIN_HIGH);
+                rt_spi_send(spi_dev_lcd, font_buf, size * size);
+                rt_free(font_buf);
+            }
+        }
+        else
+#endif
+
+#ifdef ASC2_3216
+            if (size == 32)
+            {
+                lcd_address_set(x, y, x + size / 2 - 1, y + size - 1);
+
+                font_buf = (rt_uint8_t *)rt_malloc(size * size);
+                if (!font_buf)
+                {
+                    /* fast show char */
+                    for (pos = 0; pos < size * (size / 2) / 8; pos++)
+                    {
+                        temp = asc2_3216[(rt_uint16_t)data * size * (size / 2) / 8 + pos];
+                        for (t = 0; t < 8; t++)
+                        {
+                            if (temp & 0x80)colortemp = FORE_COLOR;
+                            else colortemp = BACK_COLOR;
+                            lcd_write_half_word(colortemp);
+                            temp <<= 1;
+                        }
+                    }
+                }
+                else
+                {
+                    for (pos = 0; pos < size * (size / 2) / 8; pos++)
+                    {
+                        temp = asc2_3216[(rt_uint16_t)data * size * (size / 2) / 8 + pos];
+                        for (t = 0; t < 8; t++)
+                        {
+                            if (temp & 0x80)colortemp = FORE_COLOR;
+                            else colortemp = BACK_COLOR;
+                            font_buf[2 * (8 * pos + t)] = colortemp >> 8;
+                            font_buf[2 * (8 * pos + t) + 1] = colortemp;
+                            temp <<= 1;
+                        }
+                    }
+                    rt_pin_write(LCD_DC_PIN, PIN_HIGH);
+                    rt_spi_send(spi_dev_lcd, font_buf, size * size);
+                    rt_free(font_buf);
+                }
+            }
+            else
+#endif
+            {
+                LOG_E("There is no any define ASC2_1208 && ASC2_2412 && ASC2_2416 && ASC2_3216 !");
+            }
+}
+
+/**
+ * display the number on the lcd.
+ *
+ * @param   x       x position
+ * @param   y       y position
+ * @param   num     number
+ * @param   len     length of number
+ * @param   size    size of font
+ *
+ * @return  void
+ */
+void lcd_show_num(rt_uint16_t x, rt_uint16_t y, rt_uint32_t num, rt_uint8_t len, rt_uint32_t size)
+{
+    lcd_show_string(x, y, size, "%d", num);
+}
+
+/**
+ * display the string on the lcd.
+ *
+ * @param   x       x position
+ * @param   y       y position
+ * @param   size    size of font
+ * @param   p       the string to be display
+ *
+ * @return   0: display success
+ *          -1: size of font is not support
+ */
+rt_err_t lcd_show_string(rt_uint16_t x, rt_uint16_t y, rt_uint32_t size, const char *fmt, ...)
+{
+#define LCD_STRING_BUF_LEN 128
+
+    va_list args;
+    rt_uint8_t buf[LCD_STRING_BUF_LEN] = {0};
+    rt_uint8_t *p = RT_NULL;
+
+    if (size != 16 && size != 24 && size != 32)
+    {
+        LOG_E("font size(%d) is not support!", size);
+        return -RT_ERROR;
+    }
+
+    va_start(args, fmt);
+    rt_vsnprintf((char *)buf, 100, (const char *)fmt, args);
+    va_end(args);
+
+    p = buf;
+    while (*p != '\0')
+    {
+        if (x > LCD_W - size / 2)
+        {
+            x = 0;
+            y += size;
+        }
+        if (y > LCD_H - size)
+        {
+            y = x = 0;
+            lcd_clear(RED);
+        }
+        lcd_show_char(x, y, *p, size);
+        x += size / 2;
+        p++;
+    }
+
+    return RT_EOK;
+}
+
+/**
+ * display the image on the lcd.
+ *
+ * @param   x       x position
+ * @param   y       y position
+ * @param   length  length of image
+ * @param   wide    wide of image
+ * @param   p       image
+ *
+ * @return   0: display success
+ *          -1: the image is too large
+ */
+rt_err_t lcd_show_image(rt_uint16_t x, rt_uint16_t y, rt_uint16_t length, rt_uint16_t wide, const rt_uint8_t *p)
+{
+    RT_ASSERT(p);
+
+    if (x + length > LCD_W || y + wide > LCD_H)
+    {
+        return -RT_ERROR;
+    }
+
+    lcd_address_set(x, y, x + length - 1, y + wide - 1);
+
+    rt_pin_write(LCD_DC_PIN, PIN_HIGH);
+    rt_spi_send(spi_dev_lcd, p, length * wide * 2);
+
+    return RT_EOK;
+}
\ No newline at end of file
diff --git a/bsp/stm32/stm32l431-BearPi/board/ports/lcd/drv_lcd.h b/bsp/stm32/stm32l431-BearPi/board/ports/lcd/drv_lcd.h
new file mode 100644
index 0000000000..caeaa5dce6
--- /dev/null
+++ b/bsp/stm32/stm32l431-BearPi/board/ports/lcd/drv_lcd.h
@@ -0,0 +1,44 @@
+#ifndef __DRV_LCD_H__
+#define __DRV_LCD_H__
+
+#include 
+
+#define LCD_W 240
+#define LCD_H 240
+
+//POINT_COLOR
+#define WHITE            0xFFFF
+#define BLACK            0x0000
+#define BLUE             0x001F
+#define BRED             0XF81F
+#define GRED             0XFFE0
+#define GBLUE            0X07FF
+#define RED              0xF800
+#define MAGENTA          0xF81F
+#define GREEN            0x07E0
+#define CYAN             0x7FFF
+#define YELLOW           0xFFE0
+#define BROWN            0XBC40
+#define BRRED            0XFC07
+#define GRAY             0X8430
+#define GRAY175          0XAD75
+#define GRAY151          0X94B2
+#define GRAY187          0XBDD7
+#define GRAY240          0XF79E
+
+void lcd_clear(rt_uint16_t color);
+void lcd_address_set(rt_uint16_t x1, rt_uint16_t y1, rt_uint16_t x2, rt_uint16_t y2);
+void lcd_set_color(rt_uint16_t back, rt_uint16_t fore);
+
+void lcd_draw_point(rt_uint16_t x, rt_uint16_t y);
+void lcd_draw_point_color(rt_uint16_t x, rt_uint16_t y, rt_uint16_t color);
+void lcd_draw_circle(rt_uint16_t x0, rt_uint16_t y0, rt_uint8_t r);
+void lcd_draw_line(rt_uint16_t x1, rt_uint16_t y1, rt_uint16_t x2, rt_uint16_t y2);
+void lcd_draw_rectangle(rt_uint16_t x1, rt_uint16_t y1, rt_uint16_t x2, rt_uint16_t y2);
+void lcd_fill(rt_uint16_t x_start, rt_uint16_t y_start, rt_uint16_t x_end, rt_uint16_t y_end, rt_uint16_t color);
+
+void lcd_show_num(rt_uint16_t x, rt_uint16_t y, rt_uint32_t num, rt_uint8_t len, rt_uint32_t size);
+rt_err_t lcd_show_string(rt_uint16_t x, rt_uint16_t y, rt_uint32_t size, const char *fmt, ...);
+rt_err_t lcd_show_image(rt_uint16_t x, rt_uint16_t y, rt_uint16_t length, rt_uint16_t wide, const rt_uint8_t *p);
+
+#endif
diff --git a/bsp/stm32/stm32l431-BearPi/board/ports/lcd/drv_lcd_font.h b/bsp/stm32/stm32l431-BearPi/board/ports/lcd/drv_lcd_font.h
new file mode 100644
index 0000000000..f37721ba03
--- /dev/null
+++ b/bsp/stm32/stm32l431-BearPi/board/ports/lcd/drv_lcd_font.h
@@ -0,0 +1,780 @@
+#ifndef __DRV_LCD_FONT_H__
+#define __DRV_LCD_FONT_H__ 	   
+#include 
+
+#define ASC2_1608
+#define ASC2_2412
+#define ASC2_3216
+
+#if !defined(ASC2_1608) && !defined(ASC2_2412) && !defined(ASC2_2416) && !defined(ASC2_3216)
+#error "There is no any define ASC2_1608 && ASC2_2412 && ASC2_2416 && ASC2_3216 !"
+#endif
+
+#ifdef ASC2_1608
+const uint8_t asc2_1608[]={
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*" ",0*/
+0x00,0x00,0x00,0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x00,0x10,0x10,0x00,0x00,0x00,/*"!",1*/
+0x00,0x00,0x00,0x28,0x28,0x28,0x28,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*""",2*/
+0x00,0x00,0x00,0x12,0x12,0x16,0x7F,0x24,0x24,0xFE,0x28,0x48,0x48,0x00,0x00,0x00,/*"#",3*/
+0x00,0x00,0x08,0x08,0x3E,0x49,0x48,0x68,0x3E,0x0B,0x09,0x49,0x3E,0x08,0x08,0x00,/*"$",4*/
+0x00,0x00,0x00,0x60,0x90,0x90,0x62,0x0C,0x30,0x46,0x09,0x09,0x06,0x00,0x00,0x00,/*"%",5*/
+0x00,0x00,0x00,0x1C,0x20,0x20,0x30,0x30,0x49,0x45,0x45,0x62,0x3D,0x00,0x00,0x00,/*"&",6*/
+0x00,0x00,0x00,0x10,0x10,0x10,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"'",7*/
+0x00,0x00,0x0C,0x08,0x08,0x10,0x10,0x10,0x10,0x10,0x10,0x08,0x08,0x04,0x00,0x00,/*"(",8*/
+0x00,0x00,0x30,0x10,0x10,0x08,0x08,0x08,0x08,0x08,0x08,0x10,0x10,0x30,0x00,0x00,/*")",9*/
+0x00,0x00,0x00,0x08,0x49,0x3E,0x1C,0x6B,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"*",10*/
+0x00,0x00,0x00,0x00,0x00,0x10,0x10,0x10,0xFE,0x10,0x10,0x10,0x00,0x00,0x00,0x00,/*"+",11*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x10,0x20,0x00,/*",",12*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x00,0x00,0x00,/*"-",13*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,/*".",14*/
+0x00,0x00,0x00,0x02,0x04,0x04,0x04,0x08,0x08,0x10,0x10,0x20,0x20,0x20,0x40,0x00,/*"/",15*/
+0x00,0x00,0x00,0x1C,0x22,0x41,0x41,0x49,0x41,0x41,0x41,0x22,0x1C,0x00,0x00,0x00,/*"0",16*/
+0x00,0x00,0x00,0x18,0x28,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x3E,0x00,0x00,0x00,/*"1",17*/
+0x00,0x00,0x00,0x3E,0x43,0x01,0x01,0x02,0x06,0x0C,0x10,0x20,0x7F,0x00,0x00,0x00,/*"2",18*/
+0x00,0x00,0x00,0x3E,0x41,0x01,0x03,0x1C,0x03,0x01,0x01,0x43,0x3E,0x00,0x00,0x00,/*"3",19*/
+0x00,0x00,0x00,0x06,0x0A,0x1A,0x12,0x22,0x42,0x7F,0x02,0x02,0x02,0x00,0x00,0x00,/*"4",20*/
+0x00,0x00,0x00,0x7E,0x40,0x40,0x7C,0x42,0x01,0x01,0x01,0x42,0x3C,0x00,0x00,0x00,/*"5",21*/
+0x00,0x00,0x00,0x1E,0x31,0x60,0x40,0x5E,0x63,0x41,0x41,0x23,0x1E,0x00,0x00,0x00,/*"6",22*/
+0x00,0x00,0x00,0x7F,0x03,0x02,0x04,0x04,0x08,0x08,0x10,0x10,0x20,0x00,0x00,0x00,/*"7",23*/
+0x00,0x00,0x00,0x3E,0x41,0x41,0x41,0x3E,0x63,0x41,0x41,0x63,0x3E,0x00,0x00,0x00,/*"8",24*/
+0x00,0x00,0x00,0x3C,0x62,0x41,0x41,0x63,0x3D,0x01,0x03,0x46,0x3C,0x00,0x00,0x00,/*"9",25*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,/*":",26*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x18,0x18,0x10,0x20,0x00,/*";",27*/
+0x00,0x00,0x00,0x00,0x00,0x01,0x0E,0x38,0x40,0x38,0x0E,0x01,0x00,0x00,0x00,0x00,/*"<",28*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0x00,0x00,0x7F,0x00,0x00,0x00,0x00,0x00,0x00,/*"=",29*/
+0x00,0x00,0x00,0x00,0x00,0x40,0x38,0x0E,0x01,0x0E,0x38,0x40,0x00,0x00,0x00,0x00,/*">",30*/
+0x00,0x00,0x00,0x38,0x44,0x04,0x0C,0x18,0x10,0x10,0x00,0x10,0x10,0x00,0x00,0x00,/*"?",31*/
+0x00,0x00,0x00,0x1E,0x33,0x21,0x47,0x49,0x49,0x49,0x49,0x47,0x20,0x30,0x0E,0x00,/*"@",32*/
+0x00,0x00,0x00,0x08,0x14,0x14,0x14,0x14,0x22,0x3E,0x22,0x41,0x41,0x00,0x00,0x00,/*"A",33*/
+0x00,0x00,0x00,0x7E,0x41,0x41,0x41,0x7E,0x43,0x41,0x41,0x43,0x7E,0x00,0x00,0x00,/*"B",34*/
+0x00,0x00,0x00,0x1E,0x21,0x40,0x40,0x40,0x40,0x40,0x40,0x21,0x1E,0x00,0x00,0x00,/*"C",35*/
+0x00,0x00,0x00,0x7C,0x42,0x41,0x41,0x41,0x41,0x41,0x41,0x42,0x7C,0x00,0x00,0x00,/*"D",36*/
+0x00,0x00,0x00,0x7F,0x40,0x40,0x40,0x7F,0x40,0x40,0x40,0x40,0x7F,0x00,0x00,0x00,/*"E",37*/
+0x00,0x00,0x00,0x7F,0x40,0x40,0x40,0x7F,0x40,0x40,0x40,0x40,0x40,0x00,0x00,0x00,/*"F",38*/
+0x00,0x00,0x00,0x1E,0x21,0x40,0x40,0x40,0x43,0x41,0x41,0x21,0x1E,0x00,0x00,0x00,/*"G",39*/
+0x00,0x00,0x00,0x41,0x41,0x41,0x41,0x7F,0x41,0x41,0x41,0x41,0x41,0x00,0x00,0x00,/*"H",40*/
+0x00,0x00,0x00,0x7C,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x7C,0x00,0x00,0x00,/*"I",41*/
+0x00,0x00,0x00,0x1C,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x44,0x38,0x00,0x00,0x00,/*"J",42*/
+0x00,0x00,0x00,0x42,0x44,0x48,0x50,0x70,0x78,0x48,0x44,0x46,0x42,0x00,0x00,0x00,/*"K",43*/
+0x00,0x00,0x00,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x7F,0x00,0x00,0x00,/*"L",44*/
+0x00,0x00,0x00,0x63,0x63,0x55,0x55,0x55,0x49,0x41,0x41,0x41,0x41,0x00,0x00,0x00,/*"M",45*/
+0x00,0x00,0x00,0x61,0x61,0x51,0x51,0x49,0x49,0x45,0x45,0x43,0x43,0x00,0x00,0x00,/*"N",46*/
+0x00,0x00,0x00,0x1C,0x22,0x41,0x41,0x41,0x41,0x41,0x41,0x22,0x1C,0x00,0x00,0x00,/*"O",47*/
+0x00,0x00,0x00,0x7E,0x43,0x41,0x41,0x43,0x7E,0x40,0x40,0x40,0x40,0x00,0x00,0x00,/*"P",48*/
+0x00,0x00,0x00,0x1C,0x22,0x41,0x41,0x41,0x41,0x41,0x41,0x22,0x1E,0x06,0x02,0x00,/*"Q",49*/
+0x00,0x00,0x00,0x7E,0x43,0x41,0x41,0x43,0x7C,0x42,0x41,0x41,0x40,0x00,0x00,0x00,/*"R",50*/
+0x00,0x00,0x00,0x1E,0x61,0x40,0x40,0x30,0x0E,0x01,0x01,0x43,0x3E,0x00,0x00,0x00,/*"S",51*/
+0x00,0x00,0x00,0xFE,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x00,0x00,/*"T",52*/
+0x00,0x00,0x00,0x41,0x41,0x41,0x41,0x41,0x41,0x41,0x41,0x63,0x3E,0x00,0x00,0x00,/*"U",53*/
+0x00,0x00,0x00,0x41,0x41,0x22,0x22,0x22,0x14,0x14,0x14,0x14,0x08,0x00,0x00,0x00,/*"V",54*/
+0x00,0x00,0x00,0x81,0x81,0x81,0x5A,0x5A,0x5A,0x66,0x66,0x66,0x66,0x00,0x00,0x00,/*"W",55*/
+0x00,0x00,0x00,0x41,0x22,0x14,0x14,0x08,0x14,0x14,0x22,0x22,0x41,0x00,0x00,0x00,/*"X",56*/
+0x00,0x00,0x00,0x82,0x44,0x44,0x28,0x38,0x10,0x10,0x10,0x10,0x10,0x00,0x00,0x00,/*"Y",57*/
+0x00,0x00,0x00,0x7F,0x03,0x02,0x04,0x08,0x08,0x10,0x20,0x60,0x7F,0x00,0x00,0x00,/*"Z",58*/
+0x00,0x00,0x1C,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x1C,0x00,0x00,/*"[",59*/
+0x00,0x00,0x00,0x40,0x20,0x20,0x20,0x10,0x10,0x08,0x08,0x04,0x04,0x04,0x02,0x00,/*"\",60*/
+0x00,0x00,0x38,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x38,0x00,0x00,/*"]",61*/
+0x00,0x00,0x00,0x10,0x28,0x44,0xC6,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"^",62*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,/*"_",63*/
+0x00,0x30,0x10,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"`",64*/
+0x00,0x00,0x00,0x00,0x00,0x1C,0x22,0x02,0x3E,0x42,0x42,0x46,0x3A,0x00,0x00,0x00,/*"a",65*/
+0x00,0x00,0x40,0x40,0x40,0x7C,0x64,0x42,0x42,0x42,0x42,0x64,0x5C,0x00,0x00,0x00,/*"b",66*/
+0x00,0x00,0x00,0x00,0x00,0x1C,0x22,0x40,0x40,0x40,0x40,0x22,0x1C,0x00,0x00,0x00,/*"c",67*/
+0x00,0x00,0x02,0x02,0x02,0x3E,0x26,0x42,0x42,0x42,0x42,0x26,0x3A,0x00,0x00,0x00,/*"d",68*/
+0x00,0x00,0x00,0x00,0x00,0x3C,0x26,0x42,0x7E,0x40,0x40,0x22,0x1C,0x00,0x00,0x00,/*"e",69*/
+0x00,0x00,0x0C,0x10,0x10,0x7C,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x00,0x00,/*"f",70*/
+0x00,0x00,0x00,0x00,0x00,0x3A,0x26,0x42,0x42,0x42,0x42,0x26,0x3A,0x02,0x22,0x1C,/*"g",71*/
+0x00,0x00,0x40,0x40,0x40,0x5C,0x62,0x42,0x42,0x42,0x42,0x42,0x42,0x00,0x00,0x00,/*"h",72*/
+0x00,0x00,0x10,0x10,0x00,0x70,0x10,0x10,0x10,0x10,0x10,0x10,0x7C,0x00,0x00,0x00,/*"i",73*/
+0x00,0x00,0x08,0x08,0x00,0x38,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x70,/*"j",74*/
+0x00,0x00,0x40,0x40,0x40,0x44,0x48,0x50,0x70,0x48,0x48,0x44,0x42,0x00,0x00,0x00,/*"k",75*/
+0x00,0x00,0x70,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x0E,0x00,0x00,0x00,/*"l",76*/
+0x00,0x00,0x00,0x00,0x00,0x7E,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x00,0x00,0x00,/*"m",77*/
+0x00,0x00,0x00,0x00,0x00,0x5C,0x62,0x42,0x42,0x42,0x42,0x42,0x42,0x00,0x00,0x00,/*"n",78*/
+0x00,0x00,0x00,0x00,0x00,0x3C,0x66,0x42,0x42,0x42,0x42,0x66,0x3C,0x00,0x00,0x00,/*"o",79*/
+0x00,0x00,0x00,0x00,0x00,0x5C,0x64,0x42,0x42,0x42,0x42,0x64,0x7C,0x40,0x40,0x40,/*"p",80*/
+0x00,0x00,0x00,0x00,0x00,0x3A,0x26,0x42,0x42,0x42,0x42,0x26,0x3A,0x02,0x02,0x02,/*"q",81*/
+0x00,0x00,0x00,0x00,0x00,0x3C,0x32,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00,/*"r",82*/
+0x00,0x00,0x00,0x00,0x00,0x3C,0x42,0x40,0x70,0x0E,0x02,0x42,0x3C,0x00,0x00,0x00,/*"s",83*/
+0x00,0x00,0x00,0x10,0x10,0x7E,0x10,0x10,0x10,0x10,0x10,0x10,0x0E,0x00,0x00,0x00,/*"t",84*/
+0x00,0x00,0x00,0x00,0x00,0x42,0x42,0x42,0x42,0x42,0x42,0x46,0x3A,0x00,0x00,0x00,/*"u",85*/
+0x00,0x00,0x00,0x00,0x00,0x42,0x42,0x24,0x24,0x24,0x18,0x18,0x18,0x00,0x00,0x00,/*"v",86*/
+0x00,0x00,0x00,0x00,0x00,0x81,0x81,0x5A,0x5A,0x5A,0x5A,0x24,0x24,0x00,0x00,0x00,/*"w",87*/
+0x00,0x00,0x00,0x00,0x00,0x42,0x24,0x18,0x18,0x18,0x24,0x24,0x42,0x00,0x00,0x00,/*"x",88*/
+0x00,0x00,0x00,0x00,0x00,0x42,0x22,0x24,0x24,0x14,0x18,0x18,0x08,0x08,0x10,0x30,/*"y",89*/
+0x00,0x00,0x00,0x00,0x00,0x7E,0x02,0x04,0x08,0x10,0x20,0x40,0x7E,0x00,0x00,0x00,/*"z",90*/
+0x00,0x00,0x0C,0x10,0x10,0x10,0x10,0x10,0x60,0x10,0x10,0x10,0x10,0x10,0x0C,0x00,/*"{",91*/
+0x00,0x00,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,/*"|",92*/
+0x00,0x00,0x60,0x10,0x10,0x10,0x10,0x10,0x0C,0x10,0x10,0x10,0x10,0x10,0x60,0x00,/*"}",93*/
+};
+#endif
+
+#ifdef ASC2_2412
+const uint8_t asc2_2412[]={
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*" ",0*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x00,0x00,0x00,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"!",1*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x19,0x80,0x19,0x80,0x19,0x80,0x19,0x80,
+0x19,0x80,0x19,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*""",2*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x60,0x04,0x40,0x0C,0xC0,0x0C,0xC0,
+0x7F,0xF0,0x7F,0xF0,0x08,0x80,0x19,0x80,0x19,0x80,0xFF,0xE0,0xFF,0xE0,0x33,0x00,
+0x33,0x00,0x22,0x00,0x22,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"#",3*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x02,0x00,0x0F,0x80,0x1F,0xC0,0x3A,0x40,
+0x32,0x00,0x32,0x00,0x3A,0x00,0x1F,0x00,0x07,0xC0,0x02,0xE0,0x02,0x60,0x02,0x60,
+0x22,0xE0,0x3F,0xC0,0x1F,0x80,0x02,0x00,0x02,0x00,0x02,0x00,0x00,0x00,0x00,0x00,/*"$",4*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x78,0x00,0x48,0x00,0xCC,0x00,0xCC,0x00,
+0xCC,0x00,0x48,0x40,0x79,0xC0,0x0E,0x00,0x73,0xC0,0x02,0x40,0x06,0x60,0x06,0x60,
+0x06,0x60,0x02,0x40,0x03,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"%",5*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x80,0x1F,0x80,0x18,0x00,0x18,0x00,
+0x18,0x00,0x0C,0x00,0x1E,0x00,0x36,0x30,0x63,0x30,0x63,0xB0,0x61,0xA0,0x60,0xE0,
+0x30,0xC0,0x3F,0x60,0x0E,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"&",6*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"'",7*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x02,0x00,0x02,0x00,0x06,0x00,0x06,0x00,
+0x04,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,
+0x04,0x00,0x06,0x00,0x06,0x00,0x02,0x00,0x02,0x00,0x01,0x00,0x00,0x00,0x00,0x00,/*"(",8*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x04,0x00,0x04,0x00,0x06,0x00,0x06,0x00,
+0x02,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,
+0x02,0x00,0x06,0x00,0x06,0x00,0x04,0x00,0x04,0x00,0x08,0x00,0x00,0x00,0x00,0x00,/*")",9*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x04,0x00,0x44,0x40,0x35,0x80,
+0x0E,0x00,0x0E,0x00,0x35,0x80,0x44,0x40,0x04,0x00,0x04,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"*",10*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x7F,0xE0,0x7F,0xE0,0x06,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"+",11*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x0C,0x00,0x0C,0x00,0x00,0x00,0x00,0x00,/*",",12*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x00,0x1F,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"-",13*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*".",14*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x00,0xC0,0x00,0xC0,0x01,0x80,
+0x01,0x80,0x03,0x00,0x03,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x0C,0x00,0x0C,0x00,
+0x18,0x00,0x18,0x00,0x30,0x00,0x30,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"/",15*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1E,0x00,0x3F,0x80,0x31,0x80,0x71,0xC0,
+0x60,0xC0,0x60,0xC0,0x66,0xC0,0x66,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x71,0xC0,
+0x31,0x80,0x3F,0x80,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"0",16*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x1F,0x00,0x1B,0x00,0x03,0x00,
+0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,
+0x03,0x00,0x1F,0xE0,0x1F,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"1",17*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x7F,0x80,0x41,0xC0,0x00,0xC0,
+0x00,0xC0,0x00,0xC0,0x01,0xC0,0x01,0x80,0x03,0x00,0x06,0x00,0x0C,0x00,0x18,0x00,
+0x30,0x00,0x7F,0xC0,0x7F,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"2",18*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x7F,0x80,0x41,0xC0,0x00,0xC0,
+0x00,0xC0,0x01,0xC0,0x0F,0x80,0x0F,0x80,0x01,0x80,0x00,0xC0,0x00,0xC0,0x00,0xC0,
+0x41,0xC0,0x7F,0x80,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"3",19*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x80,0x03,0x80,0x07,0x80,0x05,0x80,
+0x0D,0x80,0x09,0x80,0x19,0x80,0x31,0x80,0x31,0x80,0x61,0x80,0x7F,0xE0,0x7F,0xE0,
+0x01,0x80,0x01,0x80,0x01,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"4",20*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x80,0x3F,0x80,0x30,0x00,0x30,0x00,
+0x30,0x00,0x3F,0x00,0x3F,0x80,0x21,0xC0,0x00,0xC0,0x00,0xC0,0x00,0xC0,0x00,0xC0,
+0x41,0x80,0x7F,0x80,0x3E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"5",21*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x00,0x1F,0x80,0x38,0x80,0x30,0x00,
+0x70,0x00,0x60,0x00,0x6F,0x00,0x7F,0x80,0x71,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,
+0x31,0xC0,0x3F,0x80,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"6",22*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xC0,0x7F,0xC0,0x01,0x80,0x01,0x80,
+0x01,0x80,0x03,0x00,0x03,0x00,0x03,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x0C,0x00,
+0x0C,0x00,0x0C,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"7",23*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x00,0x3F,0x80,0x71,0xC0,0x60,0xC0,
+0x60,0xC0,0x31,0x80,0x1F,0x00,0x3F,0x80,0x31,0x80,0x60,0xC0,0x60,0xC0,0x60,0xC0,
+0x71,0xC0,0x3F,0x80,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"8",24*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x00,0x3F,0x80,0x71,0x80,0x60,0xC0,
+0x60,0xC0,0x60,0xC0,0x71,0xC0,0x3F,0xC0,0x1E,0xC0,0x00,0xC0,0x00,0xC0,0x01,0x80,
+0x23,0x80,0x3F,0x00,0x1E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"9",25*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*":",26*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x0C,0x00,0x0C,0x00,0x00,0x00,0x00,0x00,/*";",27*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,
+0x01,0xE0,0x07,0x80,0x1E,0x00,0x70,0x00,0x70,0x00,0x1E,0x00,0x07,0x80,0x01,0xE0,
+0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"<",28*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x7F,0xE0,0x7F,0xE0,0x00,0x00,0x00,0x00,0x7F,0xE0,0x7F,0xE0,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"=",29*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x00,
+0x78,0x00,0x1E,0x00,0x07,0x80,0x00,0xE0,0x00,0xE0,0x07,0x80,0x1E,0x00,0x78,0x00,
+0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*">",30*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x80,0x1F,0xC0,0x10,0x60,0x00,0x60,
+0x00,0xE0,0x01,0xC0,0x03,0x80,0x06,0x00,0x06,0x00,0x06,0x00,0x00,0x00,0x00,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"?",31*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x80,0x18,0xC0,0x30,0x60,
+0x30,0x60,0x23,0xE0,0x62,0x60,0x66,0x60,0x66,0x60,0x66,0x60,0x66,0x60,0x66,0x60,
+0x62,0x60,0x33,0xE0,0x30,0x00,0x18,0x00,0x1C,0x00,0x07,0x80,0x00,0x00,0x00,0x00,/*"@",32*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x06,0x00,0x0F,0x00,0x0F,0x00,
+0x0F,0x00,0x1F,0x80,0x19,0x80,0x19,0x80,0x19,0x80,0x3F,0xC0,0x3F,0xC0,0x30,0xC0,
+0x30,0xC0,0x60,0x60,0x60,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"A",33*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0x00,0x7F,0x80,0x61,0xC0,0x60,0xC0,
+0x60,0xC0,0x61,0xC0,0x7F,0x80,0x7F,0x80,0x60,0xC0,0x60,0x60,0x60,0x60,0x60,0x60,
+0x60,0xE0,0x7F,0xC0,0x7F,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"B",34*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xC0,0x1F,0xE0,0x38,0x20,0x30,0x00,
+0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x30,0x00,
+0x38,0x20,0x1F,0xE0,0x07,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"C",35*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7E,0x00,0x7F,0x80,0x61,0xC0,0x60,0xC0,
+0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0xC0,
+0x61,0xC0,0x7F,0x80,0x7E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"D",36*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xE0,0x7F,0xE0,0x60,0x00,0x60,0x00,
+0x60,0x00,0x60,0x00,0x7F,0xE0,0x7F,0xE0,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,
+0x60,0x00,0x7F,0xE0,0x7F,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"E",37*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xE0,0x7F,0xE0,0x60,0x00,0x60,0x00,
+0x60,0x00,0x60,0x00,0x7F,0xC0,0x7F,0xC0,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,
+0x60,0x00,0x60,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"F",38*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x80,0x1F,0xC0,0x38,0x40,0x30,0x00,
+0x60,0x00,0x60,0x00,0x60,0x00,0x61,0xE0,0x61,0xE0,0x60,0x60,0x60,0x60,0x30,0x60,
+0x38,0x60,0x1F,0xE0,0x0F,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"G",39*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,
+0x60,0x60,0x60,0x60,0x7F,0xE0,0x7F,0xE0,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,
+0x60,0x60,0x60,0x60,0x60,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"H",40*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xC0,0x3F,0xC0,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x3F,0xC0,0x3F,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"I",41*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x80,0x1F,0x80,0x01,0x80,0x01,0x80,
+0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,
+0x43,0x80,0x7F,0x00,0x3E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"J",42*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x60,0x60,0xC0,0x61,0x80,0x63,0x00,
+0x66,0x00,0x6C,0x00,0x7C,0x00,0x7E,0x00,0x76,0x00,0x63,0x00,0x63,0x80,0x61,0x80,
+0x60,0xC0,0x60,0xE0,0x60,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"K",43*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,
+0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,
+0x60,0x00,0x7F,0xE0,0x7F,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"L",44*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x70,0xE0,0x70,0xE0,0x70,0xE0,0x79,0xE0,
+0x69,0x60,0x69,0x60,0x6F,0x60,0x66,0x60,0x66,0x60,0x66,0x60,0x60,0x60,0x60,0x60,
+0x60,0x60,0x60,0x60,0x60,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"M",45*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x70,0x60,0x70,0x60,0x78,0x60,0x78,0x60,
+0x6C,0x60,0x6C,0x60,0x64,0x60,0x66,0x60,0x62,0x60,0x63,0x60,0x63,0x60,0x61,0xE0,
+0x61,0xE0,0x60,0xE0,0x60,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"N",46*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x00,0x3F,0xC0,0x30,0xC0,0x70,0xE0,
+0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x70,0xE0,
+0x30,0xC0,0x3F,0xC0,0x0F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"O",47*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0x80,0x7F,0xC0,0x60,0xE0,0x60,0x60,
+0x60,0x60,0x60,0x60,0x60,0xE0,0x7F,0xC0,0x7F,0x80,0x60,0x00,0x60,0x00,0x60,0x00,
+0x60,0x00,0x60,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"P",48*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x00,0x3F,0xC0,0x30,0xC0,0x70,0xE0,
+0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x70,0xE0,
+0x30,0xC0,0x1F,0x80,0x0F,0x00,0x01,0x80,0x00,0xC0,0x00,0x80,0x00,0x00,0x00,0x00,/*"Q",49*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0x00,0x7F,0xC0,0x60,0xE0,0x60,0x60,
+0x60,0x60,0x60,0x60,0x60,0xC0,0x7F,0xC0,0x7F,0x80,0x61,0xC0,0x60,0xC0,0x60,0x60,
+0x60,0x60,0x60,0x30,0x60,0x30,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"R",50*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x80,0x3F,0xC0,0x70,0x40,0x60,0x00,
+0x60,0x00,0x70,0x00,0x3E,0x00,0x1F,0x80,0x01,0xC0,0x00,0x60,0x00,0x60,0x00,0x60,
+0x40,0xE0,0x7F,0xC0,0x3F,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"S",51*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xF0,0xFF,0xF0,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"T",52*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,
+0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,0x60,
+0x70,0xE0,0x3F,0xC0,0x1F,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"U",53*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x60,0x60,0x60,0x30,0xC0,0x30,0xC0,
+0x30,0xC0,0x30,0xC0,0x19,0x80,0x19,0x80,0x19,0x80,0x1F,0x80,0x0F,0x00,0x0F,0x00,
+0x0F,0x00,0x06,0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"V",54*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC0,0x30,0xC0,0x30,0xC0,0x30,0x60,0x60,
+0x66,0x60,0x66,0x60,0x6F,0x60,0x6F,0x60,0x69,0x60,0x69,0x60,0x39,0xC0,0x39,0xC0,
+0x39,0xC0,0x30,0xC0,0x30,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"W",55*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x70,0xE0,0x30,0xC0,0x39,0xC0,0x19,0x80,
+0x0F,0x00,0x0F,0x00,0x06,0x00,0x06,0x00,0x0F,0x00,0x0F,0x00,0x1B,0x80,0x19,0x80,
+0x31,0xC0,0x30,0xC0,0x60,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"X",56*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0x70,0x60,0x60,0x30,0xC0,0x30,0xC0,
+0x19,0x80,0x1F,0x80,0x0F,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"Y",57*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xE0,0x7F,0xE0,0x00,0xC0,0x01,0xC0,
+0x01,0x80,0x03,0x00,0x07,0x00,0x06,0x00,0x0E,0x00,0x0C,0x00,0x18,0x00,0x38,0x00,
+0x30,0x00,0x7F,0xE0,0x7F,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"Z",58*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x80,0x07,0x80,0x06,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x07,0x80,0x07,0x80,0x00,0x00,0x00,0x00,/*"[",59*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x00,0x30,0x00,0x30,0x00,0x18,0x00,
+0x18,0x00,0x0C,0x00,0x0C,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x03,0x00,0x03,0x00,
+0x01,0x80,0x01,0x80,0x00,0xC0,0x00,0xC0,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,/*"\",60*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x00,0x0F,0x00,0x03,0x00,0x03,0x00,0x03,0x00,
+0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,
+0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x0F,0x00,0x0F,0x00,0x00,0x00,0x00,0x00,/*"]",61*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x0F,0x80,0x0D,0x80,0x18,0xC0,
+0x30,0x60,0x60,0x30,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"^",62*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xF0,0xFF,0xF0,/*"_",63*/
+0x00,0x00,0x00,0x00,0x18,0x00,0x0C,0x00,0x06,0x00,0x03,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"`",64*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x1F,0x00,0x3F,0x80,0x21,0xC0,0x00,0xC0,0x1F,0xC0,0x3F,0xC0,0x70,0xC0,0x60,0xC0,
+0x61,0xC0,0x7F,0xC0,0x1C,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"a",65*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,
+0x6F,0x00,0x7F,0x80,0x71,0x80,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,
+0x71,0x80,0x7F,0x80,0x6F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"b",66*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x0F,0x00,0x3F,0x80,0x30,0x80,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,
+0x30,0x80,0x3F,0x80,0x0F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"c",67*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC0,0x00,0xC0,0x00,0xC0,0x00,0xC0,0x00,0xC0,
+0x1E,0xC0,0x3F,0xC0,0x31,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,
+0x31,0xC0,0x3F,0xC0,0x1E,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"d",68*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x0F,0x00,0x3F,0x80,0x31,0xC0,0x60,0xC0,0x7F,0xC0,0x7F,0xC0,0x60,0x00,0x60,0x00,
+0x30,0x40,0x3F,0xC0,0x0F,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"e",69*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xE0,0x03,0xE0,0x06,0x00,0x06,0x00,0x06,0x00,
+0x3F,0xE0,0x3F,0xE0,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"f",70*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x1E,0xC0,0x3F,0xC0,0x31,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,
+0x31,0xC0,0x3F,0xC0,0x1E,0xC0,0x00,0xC0,0x21,0xC0,0x3F,0x80,0x1F,0x00,0x00,0x00,/*"g",71*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,
+0x67,0x00,0x7F,0x80,0x71,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,
+0x60,0xC0,0x60,0xC0,0x60,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"h",72*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x3E,0x00,0x3E,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x7F,0xE0,0x7F,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"i",73*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x1F,0x00,0x1F,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,
+0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x3E,0x00,0x3C,0x00,0x00,0x00,/*"j",74*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,
+0x61,0xC0,0x63,0x80,0x67,0x00,0x6E,0x00,0x7C,0x00,0x7C,0x00,0x76,0x00,0x67,0x00,
+0x63,0x00,0x61,0x80,0x61,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"k",75*/
+0x00,0x00,0x00,0x00,0x00,0x00,0xFC,0x00,0xFC,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,
+0x0C,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,
+0x0E,0x00,0x07,0xC0,0x03,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"l",76*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x6D,0xC0,0x7F,0xE0,0x66,0x60,0x66,0x60,0x66,0x60,0x66,0x60,0x66,0x60,0x66,0x60,
+0x66,0x60,0x66,0x60,0x66,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"m",77*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x67,0x00,0x7F,0x80,0x71,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,
+0x60,0xC0,0x60,0xC0,0x60,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"n",78*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x1F,0x00,0x3F,0x80,0x31,0x80,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,
+0x31,0x80,0x3F,0x80,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"o",79*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x6F,0x00,0x7F,0x80,0x71,0x80,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,
+0x71,0x80,0x7F,0x80,0x6F,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x00,0x00,/*"p",80*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x1E,0xC0,0x3F,0xC0,0x31,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,
+0x31,0xC0,0x3F,0xC0,0x1E,0xC0,0x00,0xC0,0x00,0xC0,0x00,0xC0,0x00,0xC0,0x00,0x00,/*"q",81*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x0C,0xE0,0x0D,0xF0,0x0F,0x10,0x0E,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,
+0x0C,0x00,0x0C,0x00,0x0C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"r",82*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x1F,0x80,0x3F,0xC0,0x60,0x40,0x60,0x00,0x7F,0x00,0x1F,0x80,0x01,0xC0,0x00,0xC0,
+0x41,0xC0,0x7F,0x80,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"s",83*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,
+0x7F,0xC0,0x7F,0xC0,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,
+0x0C,0x00,0x0F,0xC0,0x07,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"t",84*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,0x60,0xC0,
+0x71,0xC0,0x3F,0xC0,0x1C,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"u",85*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x60,0xC0,0x71,0xC0,0x31,0x80,0x31,0x80,0x3B,0x80,0x1B,0x00,0x1B,0x00,0x1B,0x00,
+0x0E,0x00,0x0E,0x00,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"v",86*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0xC0,0x30,0xC0,0x30,0x60,0x60,0x66,0x60,0x66,0x60,0x66,0x60,0x3F,0xC0,0x39,0xC0,
+0x39,0xC0,0x39,0xC0,0x30,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"w",87*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x71,0xC0,0x31,0x80,0x1B,0x00,0x1F,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x1F,0x00,
+0x1B,0x00,0x31,0x80,0x71,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"x",88*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x60,0xC0,0x31,0x80,0x31,0x80,0x31,0x80,0x1B,0x00,0x1B,0x00,0x1F,0x00,0x0E,0x00,
+0x0E,0x00,0x06,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x38,0x00,0x38,0x00,0x00,0x00,/*"y",89*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x7F,0xC0,0x7F,0xC0,0x03,0x80,0x03,0x00,0x07,0x00,0x0E,0x00,0x1C,0x00,0x18,0x00,
+0x30,0x00,0x7F,0xC0,0x7F,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"z",90*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xC0,0x07,0xC0,0x06,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x3C,0x00,0x3C,0x00,0x0E,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x07,0xC0,0x03,0xC0,0x00,0x00,0x00,0x00,/*"{",91*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,/*"|",92*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x3C,0x00,0x3E,0x00,0x06,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x03,0xC0,0x03,0xC0,0x07,0x00,0x06,0x00,0x06,0x00,
+0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x00,0x3E,0x00,0x3C,0x00,0x00,0x00,0x00,0x00,/*"}",93*/
+};
+#endif
+
+#ifdef ASC2_3216
+const uint8_t asc2_3216[]={
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*" ",0*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xC0,0x01,0xC0,
+0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,
+0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xC0,
+0x01,0xC0,0x01,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"!",1*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x30,0x06,0x30,
+0x06,0x30,0x06,0x30,0x06,0x30,0x06,0x30,0x06,0x30,0x06,0x30,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*""",2*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x8C,0x03,0x8C,0x03,0x0C,
+0x03,0x18,0x03,0x18,0x03,0x18,0x7F,0xFF,0x7F,0xFF,0x06,0x30,0x06,0x30,0x0E,0x30,
+0x0C,0x70,0x0C,0x60,0xFF,0xFE,0xFF,0xFE,0x18,0x60,0x18,0xC0,0x18,0xC0,0x18,0xC0,
+0x30,0xC0,0x31,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"#",3*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x80,0x00,0x80,
+0x03,0xF0,0x0F,0xFC,0x0E,0x8C,0x1C,0x80,0x1C,0x80,0x1C,0x80,0x1C,0x80,0x0E,0x80,
+0x0F,0xE0,0x03,0xF8,0x00,0xFC,0x00,0x9E,0x00,0x8E,0x00,0x8E,0x00,0x8E,0x10,0x9C,
+0x1F,0xF8,0x07,0xF0,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x00,0x00,0x00,/*"$",4*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3C,0x00,0x7E,0x00,
+0xE7,0x00,0xC3,0x00,0xC3,0x00,0xC3,0x00,0xE7,0x00,0x7E,0x1C,0x3C,0x78,0x01,0xC0,
+0x07,0x00,0x3C,0x78,0x70,0xFC,0x01,0xCE,0x01,0x86,0x01,0x86,0x01,0x86,0x01,0xCE,
+0x00,0xFC,0x00,0x78,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"%",5*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xC0,0x0F,0xE0,
+0x1E,0x20,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1E,0x00,0x0E,0x00,0x0F,0x00,0x1F,0x00,
+0x3F,0x83,0x33,0xC3,0x71,0xE3,0x70,0xE3,0x70,0xF6,0x70,0x7E,0x78,0x3C,0x3C,0x3E,
+0x1F,0xEE,0x07,0xCF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"&",6*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x80,0x01,0x80,
+0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"'",7*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x00,0x60,0x00,0x60,
+0x00,0xE0,0x00,0xC0,0x01,0xC0,0x01,0xC0,0x01,0x80,0x03,0x80,0x03,0x80,0x03,0x80,
+0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x01,0x80,0x01,0xC0,
+0x01,0xC0,0x00,0xC0,0x00,0xE0,0x00,0x60,0x00,0x60,0x00,0x30,0x00,0x00,0x00,0x00,/*"(",8*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x03,0x00,0x03,0x00,
+0x03,0x80,0x01,0x80,0x01,0xC0,0x01,0xC0,0x00,0xC0,0x00,0xE0,0x00,0xE0,0x00,0xE0,
+0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xC0,0x01,0xC0,
+0x01,0xC0,0x01,0x80,0x03,0x80,0x03,0x00,0x03,0x00,0x06,0x00,0x00,0x00,0x00,0x00,/*")",9*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x80,0x01,0x80,
+0x21,0x84,0x39,0x9C,0x0F,0xF0,0x03,0xC0,0x03,0xC0,0x0F,0xF0,0x39,0x9C,0x21,0x84,
+0x01,0x80,0x01,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"*",10*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,
+0x7F,0xFE,0x7F,0xFE,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"+",11*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xC0,0x01,0xC0,
+0x01,0xC0,0x01,0xC0,0x01,0x80,0x03,0x80,0x03,0x80,0x03,0x00,0x00,0x00,0x00,0x00,/*",",12*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x07,0xF0,0x07,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"-",13*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x80,0x03,0x80,
+0x03,0x80,0x03,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*".",14*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1C,0x00,0x38,
+0x00,0x38,0x00,0x70,0x00,0x70,0x00,0x70,0x00,0xE0,0x00,0xE0,0x01,0xC0,0x01,0xC0,
+0x03,0x80,0x03,0x80,0x03,0x80,0x07,0x00,0x07,0x00,0x0E,0x00,0x0E,0x00,0x1C,0x00,
+0x1C,0x00,0x1C,0x00,0x38,0x00,0x38,0x00,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"/",15*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xE0,0x0F,0xF8,
+0x0E,0x38,0x1C,0x1C,0x1C,0x1C,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x39,0xCE,0x39,0xCE,
+0x39,0xCE,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x1C,0x1C,0x1C,0x1C,0x0E,0x38,
+0x0F,0xF8,0x03,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"0",16*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xE0,0x0F,0xE0,
+0x0C,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,
+0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,
+0x0F,0xFE,0x0F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"1",17*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0xE0,0x3F,0xF8,
+0x38,0x3C,0x20,0x1E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x1E,0x00,0x3C,
+0x00,0x7C,0x00,0xF8,0x00,0xF0,0x01,0xE0,0x03,0xC0,0x07,0x00,0x0E,0x00,0x1C,0x00,
+0x3F,0xFE,0x3F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"2",18*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xF0,0x1F,0xF8,
+0x18,0x1C,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x3C,0x07,0xF0,0x07,0xF0,
+0x00,0x3C,0x00,0x1C,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x1E,0x30,0x3C,
+0x3F,0xF8,0x0F,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"3",19*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x70,0x00,0xF0,
+0x01,0xF0,0x01,0xF0,0x03,0x70,0x07,0x70,0x06,0x70,0x0C,0x70,0x0C,0x70,0x18,0x70,
+0x38,0x70,0x30,0x70,0x60,0x70,0x7F,0xFE,0x7F,0xFE,0x00,0x70,0x00,0x70,0x00,0x70,
+0x00,0x70,0x00,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"4",20*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xFC,0x1F,0xFC,
+0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1F,0xE0,0x1F,0xF8,0x10,0x3C,0x00,0x1C,
+0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x1C,0x20,0x3C,
+0x3F,0xF8,0x1F,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"5",21*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xF8,0x07,0xFC,
+0x0F,0x04,0x1E,0x00,0x1C,0x00,0x1C,0x00,0x38,0x00,0x39,0xF0,0x3B,0xF8,0x3E,0x3C,
+0x3C,0x1E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x18,0x0E,0x1C,0x1C,0x0E,0x3C,
+0x0F,0xF8,0x03,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"6",22*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFE,0x3F,0xFE,
+0x00,0x1E,0x00,0x1C,0x00,0x1C,0x00,0x38,0x00,0x38,0x00,0x38,0x00,0x70,0x00,0x70,
+0x00,0xF0,0x00,0xE0,0x00,0xE0,0x01,0xE0,0x01,0xC0,0x01,0xC0,0x03,0x80,0x03,0x80,
+0x03,0x80,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"7",23*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xF0,0x1F,0xFC,
+0x1C,0x1C,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x1C,0x1C,0x07,0xF0,0x0F,0xF8,
+0x1E,0x3C,0x1C,0x1C,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x3C,0x1E,0x1E,0x3C,
+0x0F,0xF8,0x07,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"8",24*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xE0,0x0F,0xF8,
+0x1E,0x38,0x3C,0x1C,0x38,0x0C,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x3C,0x1E,
+0x1E,0x3E,0x0F,0xEE,0x07,0xCE,0x00,0x0E,0x00,0x1C,0x00,0x1C,0x00,0x3C,0x10,0x78,
+0x1F,0xF0,0x0F,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"9",25*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x80,0x03,0x80,
+0x03,0x80,0x03,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*":",26*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x80,0x03,0x80,
+0x03,0x80,0x03,0x80,0x03,0x00,0x07,0x00,0x07,0x00,0x06,0x00,0x00,0x00,0x00,0x00,/*";",27*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x1E,0x00,0x7E,0x01,0xF8,0x0F,0xC0,0x3F,0x00,
+0x78,0x00,0x78,0x00,0x3F,0x00,0x0F,0xC0,0x01,0xF8,0x00,0x7E,0x00,0x1E,0x00,0x02,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"<",28*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFE,0x7F,0xFE,
+0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFE,0x7F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"=",29*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x40,0x00,0x78,0x00,0x7E,0x00,0x1F,0x80,0x03,0xF0,0x00,0xFC,
+0x00,0x1E,0x00,0x1E,0x00,0xFC,0x03,0xF0,0x1F,0x80,0x7E,0x00,0x78,0x00,0x40,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*">",30*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xE0,0x0F,0xF8,
+0x1C,0x38,0x10,0x1C,0x00,0x1C,0x00,0x3C,0x00,0x3C,0x00,0x78,0x00,0xF0,0x01,0xE0,
+0x03,0xC0,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x00,0x00,0x00,0x00,0x03,0x80,
+0x03,0x80,0x03,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"?",31*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xF8,
+0x07,0xFC,0x0E,0x0E,0x1C,0x06,0x18,0x03,0x30,0x03,0x30,0x7B,0x61,0xFF,0x61,0x87,
+0x63,0x03,0x63,0x03,0x63,0x03,0x63,0x03,0x63,0x03,0x61,0x87,0x71,0xFF,0x30,0x7B,
+0x30,0x00,0x18,0x00,0x1C,0x00,0x0F,0x04,0x03,0xFC,0x00,0xFC,0x00,0x00,0x00,0x00,/*"@",32*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xC0,0x03,0xE0,
+0x03,0xE0,0x03,0xE0,0x03,0xE0,0x07,0x70,0x07,0x70,0x07,0x70,0x0F,0x78,0x0E,0x38,
+0x0E,0x38,0x0E,0x38,0x1F,0xFC,0x1F,0xFC,0x1C,0x1C,0x38,0x0E,0x38,0x0E,0x38,0x0E,
+0x78,0x0F,0x70,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"A",33*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xE0,0x3F,0xF8,
+0x38,0x38,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x38,0x3F,0xF0,0x3F,0xF0,
+0x38,0x3C,0x38,0x1C,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x1E,0x38,0x3C,
+0x3F,0xF8,0x3F,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"B",34*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xF8,0x07,0xFC,
+0x0F,0x0C,0x1E,0x04,0x1C,0x00,0x1C,0x00,0x38,0x00,0x38,0x00,0x38,0x00,0x38,0x00,
+0x38,0x00,0x38,0x00,0x38,0x00,0x38,0x00,0x1C,0x00,0x1C,0x00,0x1E,0x04,0x0F,0x0C,
+0x07,0xFC,0x01,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"C",35*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xC0,0x3F,0xF0,
+0x38,0x78,0x38,0x1C,0x38,0x1C,0x38,0x0C,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,
+0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0C,0x38,0x1C,0x38,0x1C,0x38,0x78,
+0x3F,0xF0,0x3F,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"D",36*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xFE,0x1F,0xFE,
+0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1F,0xFC,0x1F,0xFC,
+0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,
+0x1F,0xFE,0x1F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"E",37*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xFE,0x1F,0xFE,
+0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1F,0xFC,0x1F,0xFC,
+0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,
+0x1C,0x00,0x1C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"F",38*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xF8,0x07,0xFC,
+0x0F,0x0C,0x1E,0x04,0x1C,0x00,0x1C,0x00,0x38,0x00,0x38,0x00,0x38,0x00,0x38,0x7E,
+0x38,0x7E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x1C,0x0E,0x1C,0x0E,0x1C,0x0E,0x0F,0x1E,
+0x07,0xFE,0x01,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"G",39*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x38,0x0E,0x38,0x0E,
+0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x3F,0xFE,0x3F,0xFE,
+0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,
+0x38,0x0E,0x38,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"H",40*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xFC,0x1F,0xFC,
+0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,
+0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,
+0x1F,0xFC,0x1F,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"I",41*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xF8,0x07,0xF8,
+0x00,0x38,0x00,0x38,0x00,0x38,0x00,0x38,0x00,0x38,0x00,0x38,0x00,0x38,0x00,0x38,
+0x00,0x38,0x00,0x38,0x00,0x38,0x00,0x38,0x00,0x38,0x00,0x38,0x20,0x38,0x30,0x70,
+0x3F,0xF0,0x0F,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"J",42*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x38,0x07,0x38,0x0E,
+0x38,0x1C,0x38,0x38,0x38,0x70,0x38,0xE0,0x39,0xC0,0x3B,0x80,0x3F,0x80,0x3F,0xC0,
+0x3F,0xC0,0x3D,0xE0,0x38,0xF0,0x38,0x70,0x38,0x78,0x38,0x3C,0x38,0x1C,0x38,0x1E,
+0x38,0x0F,0x38,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"K",43*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1C,0x00,0x1C,0x00,
+0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,
+0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,
+0x1F,0xFE,0x1F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"L",44*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x78,0x1E,0x78,0x1E,
+0x7C,0x3E,0x7C,0x3E,0x7C,0x3E,0x76,0x6E,0x76,0x6E,0x76,0x6E,0x72,0x4E,0x73,0xCE,
+0x73,0xCE,0x71,0x8E,0x71,0x8E,0x70,0x0E,0x70,0x0E,0x70,0x0E,0x70,0x0E,0x70,0x0E,
+0x70,0x0E,0x70,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"M",45*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3C,0x0E,0x3C,0x0E,
+0x3E,0x0E,0x3E,0x0E,0x3E,0x0E,0x3B,0x0E,0x3B,0x0E,0x3B,0x8E,0x39,0x8E,0x39,0x8E,
+0x38,0xCE,0x38,0xCE,0x38,0xEE,0x38,0x6E,0x38,0x6E,0x38,0x3E,0x38,0x3E,0x38,0x3E,
+0x38,0x1E,0x38,0x1E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"N",46*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xE0,0x0F,0xF8,
+0x0E,0x38,0x1C,0x1C,0x1C,0x1C,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,
+0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x1C,0x1C,0x1C,0x1C,0x0E,0x38,
+0x0F,0xF8,0x03,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"O",47*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xF0,0x1F,0xFC,
+0x1C,0x1E,0x1C,0x0F,0x1C,0x07,0x1C,0x07,0x1C,0x07,0x1C,0x07,0x1C,0x0F,0x1C,0x1E,
+0x1F,0xFC,0x1F,0xF0,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,
+0x1C,0x00,0x1C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"P",48*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xE0,0x0F,0xF8,
+0x0E,0x38,0x1C,0x1C,0x1C,0x1C,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,
+0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x1C,0x1C,0x1C,0x1C,0x0E,0x38,
+0x0F,0xF8,0x03,0xE0,0x00,0x70,0x00,0x38,0x00,0x1C,0x00,0x10,0x00,0x00,0x00,0x00,/*"Q",49*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xE0,0x3F,0xF0,
+0x38,0x78,0x38,0x3C,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x38,
+0x3F,0xF0,0x3F,0xE0,0x38,0xF0,0x38,0x78,0x38,0x38,0x38,0x3C,0x38,0x1C,0x38,0x1E,
+0x38,0x0E,0x38,0x0F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"R",50*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xF0,0x0F,0xFC,
+0x1E,0x0C,0x3C,0x04,0x38,0x00,0x38,0x00,0x38,0x00,0x3E,0x00,0x1F,0xC0,0x0F,0xF8,
+0x03,0xFC,0x00,0x3C,0x00,0x1E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x20,0x1E,0x38,0x3C,
+0x3F,0xF8,0x0F,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"S",51*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0x7F,0xFF,
+0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,
+0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,
+0x01,0xC0,0x01,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"T",52*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x38,0x1C,0x38,0x1C,
+0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1C,
+0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x1C,0x38,
+0x0F,0xF0,0x07,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"U",53*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x70,0x07,0x78,0x0F,
+0x38,0x0E,0x38,0x0E,0x38,0x0E,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1E,0x3C,0x0E,0x38,
+0x0E,0x38,0x0E,0x38,0x07,0x70,0x07,0x70,0x07,0x70,0x03,0xE0,0x03,0xE0,0x03,0xE0,
+0x03,0xE0,0x01,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"V",54*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0x07,0xE0,0x07,
+0xE0,0x07,0x70,0x0E,0x70,0x0E,0x70,0x0E,0x73,0xCE,0x73,0xCE,0x73,0xCE,0x73,0xCE,
+0x3B,0xDC,0x3E,0x7C,0x3E,0x7C,0x3E,0x7C,0x3E,0x7C,0x3C,0x3C,0x3C,0x3C,0x1C,0x38,
+0x1C,0x38,0x18,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"W",55*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x78,0x07,0x3C,0x0F,
+0x1C,0x0E,0x1E,0x1E,0x0F,0x3C,0x07,0x38,0x07,0xF0,0x03,0xF0,0x01,0xE0,0x01,0xE0,
+0x01,0xE0,0x03,0xF0,0x07,0xF0,0x07,0x78,0x0F,0x3C,0x0E,0x1C,0x1E,0x1E,0x3C,0x0E,
+0x38,0x07,0x78,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"X",56*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x78,0x0F,0x38,0x0E,
+0x3C,0x1E,0x1C,0x1C,0x1E,0x3C,0x0E,0x38,0x07,0x70,0x07,0xF0,0x03,0xE0,0x03,0xE0,
+0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,
+0x01,0xC0,0x01,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"Y",57*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFE,0x3F,0xFE,
+0x00,0x1E,0x00,0x1C,0x00,0x3C,0x00,0x78,0x00,0x70,0x00,0xF0,0x00,0xE0,0x01,0xE0,
+0x03,0xC0,0x03,0x80,0x07,0x80,0x07,0x00,0x0F,0x00,0x1E,0x00,0x1C,0x00,0x3C,0x00,
+0x3F,0xFE,0x3F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"Z",58*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xF0,0x03,0xF0,0x03,0x80,
+0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,
+0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,
+0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0xF0,0x03,0xF0,0x00,0x00,0x00,0x00,/*"[",59*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x70,0x00,0x38,0x00,
+0x38,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x0E,0x00,0x0E,0x00,0x07,0x00,0x07,0x00,
+0x03,0x80,0x03,0x80,0x03,0x80,0x01,0xC0,0x01,0xC0,0x00,0xE0,0x00,0xE0,0x00,0x70,
+0x00,0x70,0x00,0x70,0x00,0x38,0x00,0x38,0x00,0x1C,0x00,0x00,0x00,0x00,0x00,0x00,/*"\",60*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xE0,0x07,0xE0,0x00,0xE0,
+0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,
+0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,
+0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x07,0xE0,0x07,0xE0,0x00,0x00,0x00,0x00,/*"]",61*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xC0,0x03,0xC0,
+0x07,0xE0,0x0E,0x70,0x0C,0x30,0x18,0x18,0x38,0x1C,0x70,0x0E,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"^",62*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,/*"_",63*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0E,0x00,0x07,0x00,0x03,0x00,0x01,0x80,
+0x00,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"`",64*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xF0,0x1F,0xFC,0x18,0x1C,0x00,0x0E,0x00,0x0E,
+0x07,0xFE,0x0F,0xFE,0x1C,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x1E,0x38,0x1E,0x3C,0x3E,
+0x1F,0xEE,0x07,0xCE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"a",65*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,
+0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0xF8,0x1F,0xFC,0x1F,0x1E,0x1E,0x0E,0x1C,0x07,
+0x1C,0x07,0x1C,0x07,0x1C,0x07,0x1C,0x07,0x1C,0x07,0x1C,0x07,0x1E,0x0E,0x1F,0x1E,
+0x1F,0xFC,0x1C,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"b",66*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xF0,0x07,0xF8,0x0F,0x0C,0x0E,0x00,0x1C,0x00,
+0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1E,0x00,0x0E,0x00,0x0F,0x0C,
+0x07,0xF8,0x01,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"c",67*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0E,0x00,0x0E,0x00,0x0E,
+0x00,0x0E,0x00,0x0E,0x00,0x0E,0x07,0xCE,0x0F,0xFE,0x1E,0x3E,0x1C,0x1E,0x38,0x0E,
+0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x1C,0x1E,0x1E,0x3E,
+0x0F,0xFE,0x07,0xCE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"d",68*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xE0,0x0F,0xF8,0x1E,0x3C,0x1C,0x1C,0x3C,0x0E,
+0x38,0x0E,0x38,0x0E,0x3F,0xFE,0x3F,0xFE,0x38,0x00,0x38,0x00,0x1C,0x04,0x1E,0x0C,
+0x0F,0xF8,0x03,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"e",69*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7E,0x00,0xFE,0x01,0xE0,
+0x01,0xC0,0x01,0xC0,0x01,0xC0,0x1F,0xFE,0x1F,0xFE,0x01,0xC0,0x01,0xC0,0x01,0xC0,
+0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,
+0x01,0xC0,0x01,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"f",70*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xCE,0x0F,0xEE,0x1E,0x3E,0x1C,0x1E,0x38,0x0E,
+0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x1C,0x1E,0x1E,0x3E,
+0x0F,0xEE,0x07,0xCE,0x00,0x0E,0x00,0x0E,0x00,0x1C,0x08,0x3C,0x0F,0xF8,0x07,0xE0,/*"g",71*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,
+0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0xF0,0x1D,0xF8,0x1E,0x3C,0x1E,0x1C,0x1C,0x1C,
+0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,
+0x1C,0x1C,0x1C,0x1C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"h",72*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xC0,0x01,0xC0,0x01,0xC0,
+0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xC0,0x1F,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,
+0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,
+0x3F,0xFE,0x3F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"i",73*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0x00,0xE0,0x00,0xE0,
+0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0xE0,0x0F,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,
+0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,
+0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x01,0xC0,0x1F,0xC0,0x1F,0x00,/*"j",74*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,
+0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x0F,0x1C,0x1E,0x1C,0x3C,0x1C,0x78,0x1C,0xF0,
+0x1D,0xE0,0x1F,0xC0,0x1F,0xE0,0x1F,0xE0,0x1E,0xF0,0x1C,0x78,0x1C,0x3C,0x1C,0x1C,
+0x1C,0x1E,0x1C,0x0F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"k",75*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0x80,0x7F,0x80,0x03,0x80,
+0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,
+0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x01,0xC0,
+0x01,0xFC,0x00,0x7C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"l",76*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x77,0x1C,0x7F,0xBE,0x71,0xE7,0x71,0xC7,0x71,0xC7,
+0x71,0xC7,0x71,0xC7,0x71,0xC7,0x71,0xC7,0x71,0xC7,0x71,0xC7,0x71,0xC7,0x71,0xC7,
+0x71,0xC7,0x71,0xC7,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"m",77*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x1C,0xF0,0x1D,0xF8,0x1E,0x3C,0x1E,0x1C,0x1C,0x1C,
+0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,
+0x1C,0x1C,0x1C,0x1C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"n",78*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xE0,0x0F,0xF8,0x1E,0x3C,0x1C,0x1C,0x38,0x0E,
+0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x1C,0x1C,0x1E,0x3C,
+0x0F,0xF8,0x03,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"o",79*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x1C,0xF8,0x1F,0xFC,0x1F,0x1E,0x1E,0x0E,0x1C,0x07,
+0x1C,0x07,0x1C,0x07,0x1C,0x07,0x1C,0x07,0x1C,0x07,0x1C,0x07,0x1E,0x0E,0x1F,0x1E,
+0x1F,0xFC,0x1C,0xF8,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,/*"p",80*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xCE,0x0F,0xFE,0x1E,0x3E,0x1C,0x1E,0x38,0x0E,
+0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x38,0x0E,0x1C,0x1E,0x1E,0x3E,
+0x0F,0xFE,0x07,0xCE,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,/*"q",81*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x3C,0x07,0x7E,0x07,0xC2,0x07,0x80,0x07,0x80,
+0x07,0x00,0x07,0x00,0x07,0x00,0x07,0x00,0x07,0x00,0x07,0x00,0x07,0x00,0x07,0x00,
+0x07,0x00,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"r",82*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xF0,0x0F,0xF8,0x1E,0x08,0x1C,0x00,0x1C,0x00,
+0x1F,0x00,0x0F,0xF0,0x07,0xF8,0x00,0xFC,0x00,0x3C,0x00,0x1C,0x00,0x1C,0x10,0x3C,
+0x1F,0xF8,0x07,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"s",83*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x80,
+0x03,0x80,0x03,0x80,0x03,0x80,0x3F,0xFE,0x3F,0xFE,0x03,0x80,0x03,0x80,0x03,0x80,
+0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0xC0,
+0x01,0xFE,0x00,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"t",84*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,
+0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x1C,0x3C,0x1E,0x3C,
+0x0F,0xDC,0x07,0x9C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"u",85*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x70,0x0E,0x38,0x1C,0x38,0x1C,0x38,0x1C,0x1C,0x38,
+0x1C,0x38,0x1E,0x78,0x0E,0x70,0x0E,0x70,0x0F,0xF0,0x07,0xE0,0x07,0xE0,0x07,0xE0,
+0x03,0xC0,0x03,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"v",86*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0x07,0xE0,0x07,0x70,0x0E,0x70,0x0E,0x71,0x8E,
+0x71,0x8E,0x7B,0xDE,0x3B,0xDC,0x3A,0x5C,0x3A,0x5C,0x3E,0x7C,0x1E,0x78,0x1C,0x38,
+0x1C,0x38,0x1C,0x38,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"w",87*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x3C,0x3C,0x1E,0x78,0x0E,0x70,0x0F,0xF0,0x07,0xE0,
+0x03,0xC0,0x03,0xC0,0x01,0x80,0x03,0xC0,0x07,0xE0,0x0F,0xF0,0x0E,0x70,0x1E,0x78,
+0x3C,0x3C,0x78,0x1E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"x",88*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x70,0x0E,0x38,0x1C,0x38,0x1C,0x3C,0x3C,0x1C,0x38,
+0x1C,0x38,0x1E,0x78,0x0E,0x70,0x0E,0x70,0x07,0xE0,0x07,0xE0,0x07,0xE0,0x03,0xC0,
+0x03,0xC0,0x03,0x80,0x03,0x80,0x03,0x80,0x07,0x00,0x0F,0x00,0x3E,0x00,0x3C,0x00,/*"y",89*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xFC,0x1F,0xFC,0x00,0x3C,0x00,0x78,0x00,0x70,
+0x00,0xF0,0x01,0xE0,0x01,0xC0,0x03,0xC0,0x07,0x80,0x07,0x00,0x0F,0x00,0x1E,0x00,
+0x1F,0xFC,0x1F,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,/*"z",90*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7C,0x00,0xFC,0x01,0xE0,
+0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,
+0x03,0x80,0x1F,0x00,0x1F,0x00,0x03,0x80,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,
+0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xE0,0x00,0xFC,0x00,0x7C,0x00,0x00,/*"{",91*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x80,0x01,0x80,0x01,0x80,
+0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,
+0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,
+0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,/*"|",92*/
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x00,0x1F,0x80,0x03,0xC0,
+0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,
+0x00,0xE0,0x00,0x7C,0x00,0x7C,0x00,0xE0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,
+0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x03,0xC0,0x1F,0x80,0x1F,0x00,0x00,0x00,/*"}",93*/
+};
+#endif
+
+#endif
diff --git a/bsp/stm32/stm32l431-BearPi/project.uvoptx b/bsp/stm32/stm32l431-BearPi/project.uvoptx
index 528c410d17..c0c2dc00ef 100644
--- a/bsp/stm32/stm32l431-BearPi/project.uvoptx
+++ b/bsp/stm32/stm32l431-BearPi/project.uvoptx
@@ -183,7 +183,7 @@
 
   
     Applications
-    1
+    0
     0
     0
     0
@@ -318,6 +318,30 @@
       0
       0
       0
+      ..\..\..\components\drivers\spi\spi_core.c
+      spi_core.c
+      0
+      0
+    
+    
+      3
+      11
+      1
+      0
+      0
+      0
+      ..\..\..\components\drivers\spi\spi_dev.c
+      spi_dev.c
+      0
+      0
+    
+    
+      3
+      12
+      1
+      0
+      0
+      0
       ..\..\..\components\drivers\src\completion.c
       completion.c
       0
@@ -325,7 +349,7 @@
     
     
       3
-      11
+      13
       1
       0
       0
@@ -337,7 +361,7 @@
     
     
       3
-      12
+      14
       1
       0
       0
@@ -349,7 +373,7 @@
     
     
       3
-      13
+      15
       1
       0
       0
@@ -361,7 +385,7 @@
     
     
       3
-      14
+      16
       1
       0
       0
@@ -373,7 +397,7 @@
     
     
       3
-      15
+      17
       1
       0
       0
@@ -385,7 +409,7 @@
     
     
       3
-      16
+      18
       1
       0
       0
@@ -397,7 +421,7 @@
     
     
       3
-      17
+      19
       1
       0
       0
@@ -417,7 +441,7 @@
     0
     
       4
-      18
+      20
       1
       0
       0
@@ -429,7 +453,7 @@
     
     
       4
-      19
+      21
       1
       0
       0
@@ -441,7 +465,19 @@
     
     
       4
-      20
+      22
+      1
+      1
+      0
+      0
+      board\ports\lcd\drv_lcd.c
+      drv_lcd.c
+      0
+      0
+    
+    
+      4
+      23
       2
       0
       0
@@ -453,7 +489,7 @@
     
     
       4
-      21
+      24
       1
       0
       0
@@ -465,7 +501,7 @@
     
     
       4
-      22
+      25
       1
       0
       0
@@ -477,7 +513,19 @@
     
     
       4
-      23
+      26
+      1
+      0
+      0
+      0
+      ..\libraries\HAL_Drivers\drv_spi.c
+      drv_spi.c
+      0
+      0
+    
+    
+      4
+      27
       1
       0
       0
@@ -497,7 +545,7 @@
     0
     
       5
-      24
+      28
       1
       0
       0
@@ -509,7 +557,7 @@
     
     
       5
-      25
+      29
       1
       0
       0
@@ -521,7 +569,7 @@
     
     
       5
-      26
+      30
       1
       0
       0
@@ -541,7 +589,7 @@
     0
     
       6
-      27
+      31
       1
       0
       0
@@ -553,7 +601,7 @@
     
     
       6
-      28
+      32
       1
       0
       0
@@ -565,7 +613,7 @@
     
     
       6
-      29
+      33
       1
       0
       0
@@ -577,7 +625,7 @@
     
     
       6
-      30
+      34
       1
       0
       0
@@ -589,7 +637,7 @@
     
     
       6
-      31
+      35
       1
       0
       0
@@ -601,7 +649,7 @@
     
     
       6
-      32
+      36
       1
       0
       0
@@ -613,7 +661,7 @@
     
     
       6
-      33
+      37
       1
       0
       0
@@ -625,7 +673,7 @@
     
     
       6
-      34
+      38
       1
       0
       0
@@ -637,7 +685,7 @@
     
     
       6
-      35
+      39
       1
       0
       0
@@ -649,7 +697,7 @@
     
     
       6
-      36
+      40
       1
       0
       0
@@ -661,7 +709,7 @@
     
     
       6
-      37
+      41
       1
       0
       0
@@ -673,7 +721,7 @@
     
     
       6
-      38
+      42
       1
       0
       0
@@ -685,7 +733,7 @@
     
     
       6
-      39
+      43
       1
       0
       0
@@ -697,7 +745,7 @@
     
     
       6
-      40
+      44
       1
       0
       0
@@ -717,7 +765,7 @@
     0
     
       7
-      41
+      45
       1
       0
       0
@@ -729,7 +777,7 @@
     
     
       7
-      42
+      46
       1
       0
       0
@@ -741,7 +789,7 @@
     
     
       7
-      43
+      47
       1
       0
       0
@@ -753,7 +801,7 @@
     
     
       7
-      44
+      48
       1
       0
       0
@@ -773,7 +821,7 @@
     0
     
       8
-      45
+      49
       1
       0
       0
@@ -785,7 +833,7 @@
     
     
       8
-      46
+      50
       1
       0
       0
@@ -797,7 +845,7 @@
     
     
       8
-      47
+      51
       1
       0
       0
@@ -809,7 +857,7 @@
     
     
       8
-      48
+      52
       1
       0
       0
@@ -821,7 +869,7 @@
     
     
       8
-      49
+      53
       1
       0
       0
@@ -833,7 +881,7 @@
     
     
       8
-      50
+      54
       1
       0
       0
@@ -845,7 +893,7 @@
     
     
       8
-      51
+      55
       1
       0
       0
@@ -857,7 +905,7 @@
     
     
       8
-      52
+      56
       1
       0
       0
@@ -869,7 +917,7 @@
     
     
       8
-      53
+      57
       1
       0
       0
@@ -881,7 +929,7 @@
     
     
       8
-      54
+      58
       1
       0
       0
@@ -893,7 +941,7 @@
     
     
       8
-      55
+      59
       1
       0
       0
@@ -905,7 +953,7 @@
     
     
       8
-      56
+      60
       1
       0
       0
@@ -917,7 +965,7 @@
     
     
       8
-      57
+      61
       1
       0
       0
@@ -929,7 +977,7 @@
     
     
       8
-      58
+      62
       1
       0
       0
@@ -941,7 +989,7 @@
     
     
       8
-      59
+      63
       1
       0
       0
@@ -953,7 +1001,7 @@
     
     
       8
-      60
+      64
       1
       0
       0
@@ -965,7 +1013,7 @@
     
     
       8
-      61
+      65
       1
       0
       0
@@ -977,7 +1025,7 @@
     
     
       8
-      62
+      66
       1
       0
       0
@@ -989,7 +1037,7 @@
     
     
       8
-      63
+      67
       1
       0
       0
@@ -1001,7 +1049,7 @@
     
     
       8
-      64
+      68
       1
       0
       0
@@ -1013,7 +1061,7 @@
     
     
       8
-      65
+      69
       1
       0
       0
@@ -1025,7 +1073,43 @@
     
     
       8
-      66
+      70
+      1
+      0
+      0
+      0
+      ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi.c
+      stm32l4xx_hal_spi.c
+      0
+      0
+    
+    
+      8
+      71
+      1
+      0
+      0
+      0
+      ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi_ex.c
+      stm32l4xx_hal_spi_ex.c
+      0
+      0
+    
+    
+      8
+      72
+      1
+      0
+      0
+      0
+      ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_qspi.c
+      stm32l4xx_hal_qspi.c
+      0
+      0
+    
+    
+      8
+      73
       1
       0
       0
@@ -1037,7 +1121,7 @@
     
     
       8
-      67
+      74
       1
       0
       0
@@ -1049,7 +1133,7 @@
     
     
       8
-      68
+      75
       1
       0
       0
@@ -1061,7 +1145,7 @@
     
     
       8
-      69
+      76
       1
       0
       0
diff --git a/bsp/stm32/stm32l431-BearPi/project.uvprojx b/bsp/stm32/stm32l431-BearPi/project.uvprojx
index 549412b461..93dabedc1a 100644
--- a/bsp/stm32/stm32l431-BearPi/project.uvprojx
+++ b/bsp/stm32/stm32l431-BearPi/project.uvprojx
@@ -336,9 +336,9 @@
             0
             
               
-              RT_USING_ARM_LIBC, USE_HAL_DRIVER, STM32L432xx, __RTTHREAD__
+              RT_USING_ARM_LIBC, USE_HAL_DRIVER, __RTTHREAD__, STM32L431xx
               
-              .;applications;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\compilers\common;..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Inc;..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Include;..\libraries\STM32L4xx_HAL\CMSIS\Include
+              .;applications;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;board\CubeMX_Config\Inc;board\ports\lcd;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\compilers\common;..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Inc;..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Include;..\libraries\STM32L4xx_HAL\CMSIS\Include
             
           
           
@@ -421,6 +421,75 @@
         
         
           DeviceDrivers
+          
+            
+              0
+              0
+              0
+              0
+              0
+              1
+              0
+              0
+              0
+              0
+              3
+              
+              
+              0
+            
+            
+              
+                2
+                0
+                2
+                2
+                2
+                2
+                2
+                2
+                2
+                2
+                0
+                2
+                2
+                2
+                2
+                2
+                0
+                0
+                2
+                2
+                2
+                2
+                2
+                
+                  
+                   
+                   
+                  
+                
+              
+              
+                2
+                2
+                2
+                2
+                2
+                2
+                2
+                2
+                2
+                2
+                
+                  
+                  
+                  
+                  
+                
+              
+            
+          
           
             
               pin.c
@@ -437,6 +506,16 @@
               1
               ..\..\..\components\drivers\serial\serial.c
             
+            
+              spi_core.c
+              1
+              ..\..\..\components\drivers\spi\spi_core.c
+            
+            
+              spi_dev.c
+              1
+              ..\..\..\components\drivers\spi\spi_dev.c
+            
             
               completion.c
               1
@@ -492,6 +571,11 @@
               1
               board\CubeMX_Config\Src\stm32l4xx_hal_msp.c
             
+            
+              drv_lcd.c
+              1
+              board\ports\lcd\drv_lcd.c
+            
             
               startup_stm32l431xx.s
               2
@@ -507,6 +591,11 @@
               1
               ..\libraries\HAL_Drivers\drv_usart.c
             
+            
+              drv_spi.c
+              1
+              ..\libraries\HAL_Drivers\drv_spi.c
+            
             
               drv_common.c
               1
@@ -742,6 +831,21 @@
               1
               ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart_ex.c
             
+            
+              stm32l4xx_hal_spi.c
+              1
+              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi.c
+            
+            
+              stm32l4xx_hal_spi_ex.c
+              1
+              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi_ex.c
+            
+            
+              stm32l4xx_hal_qspi.c
+              1
+              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_qspi.c
+            
             
               stm32l4xx_hal_rtc.c
               1
diff --git a/bsp/stm32/stm32l431-BearPi/rtconfig.h b/bsp/stm32/stm32l431-BearPi/rtconfig.h
index 6fbc67f2c5..4be6382a58 100644
--- a/bsp/stm32/stm32l431-BearPi/rtconfig.h
+++ b/bsp/stm32/stm32l431-BearPi/rtconfig.h
@@ -83,6 +83,7 @@
 #define RT_SERIAL_RB_BUFSZ 64
 #define RT_USING_PIN
 #define RT_USING_RTC
+#define RT_USING_SPI
 #define RT_USING_WDT
 
 /* Using USB */
@@ -169,5 +170,11 @@
 #define BSP_USING_GPIO
 #define BSP_USING_UART
 #define BSP_USING_UART1
+#define BSP_USING_SPI
+#define BSP_USING_SPI2
+
+/* Onboard Peripheral Drivers */
+
+#define BSP_USING_SPI_LCD
 
 #endif
diff --git a/bsp/stm32/stm32l432-st-nucleo/applications/main.c b/bsp/stm32/stm32l432-st-nucleo/applications/main.c
index e1755ec81e..d3654159d8 100644
--- a/bsp/stm32/stm32l432-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32l432-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32l432-st-nucleo/board/Kconfig b/bsp/stm32/stm32l432-st-nucleo/board/Kconfig
index 181be78e77..3885c3cc71 100644
--- a/bsp/stm32/stm32l432-st-nucleo/board/Kconfig
+++ b/bsp/stm32/stm32l432-st-nucleo/board/Kconfig
@@ -44,7 +44,6 @@ menu "On-chip Peripheral Drivers"
     menuconfig BSP_USING_ONCHIP_RTC
         bool "Enable RTC"
         select RT_USING_RTC
-        select RT_USING_LIBC
         default n
         if BSP_USING_ONCHIP_RTC
             choice
diff --git a/bsp/stm32/stm32l432-st-nucleo/board/board.c b/bsp/stm32/stm32l432-st-nucleo/board/board.c
index 79f7c0344f..93000dc18c 100644
--- a/bsp/stm32/stm32l432-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32l432-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,13 +17,13 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct;
   RCC_PeriphCLKInitTypeDef PeriphClkInit;
 
-    /**Configure LSE Drive Capability 
+    /**Configure LSE Drive Capability
     */
   HAL_PWR_EnableBkUpAccess();
 
   __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
 
-    /**Initializes the CPU, AHB and APB busses clocks 
+    /**Initializes the CPU, AHB and APB busses clocks
     */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI;
   RCC_OscInitStruct.LSEState = RCC_LSE_ON;
@@ -42,7 +42,7 @@ void SystemClock_Config(void)
     _Error_Handler(__FILE__, __LINE__);
   }
 
-    /**Initializes the CPU, AHB and APB busses clocks 
+    /**Initializes the CPU, AHB and APB busses clocks
     */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
@@ -63,22 +63,22 @@ void SystemClock_Config(void)
     _Error_Handler(__FILE__, __LINE__);
   }
 
-    /**Configure the main internal regulator output voltage 
+    /**Configure the main internal regulator output voltage
     */
   if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
   {
     _Error_Handler(__FILE__, __LINE__);
   }
 
-    /**Configure the Systick interrupt time 
+    /**Configure the Systick interrupt time
     */
   HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
 
-    /**Configure the Systick 
+    /**Configure the Systick
     */
   HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
 
-    /**Enable MSI Auto calibration 
+    /**Enable MSI Auto calibration
     */
   HAL_RCCEx_EnableMSIPLLMode();
 
diff --git a/bsp/stm32/stm32l432-st-nucleo/board/board.h b/bsp/stm32/stm32l432-st-nucleo/board/board.h
index 3b3a77e103..77db7fce6e 100644
--- a/bsp/stm32/stm32l432-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32l432-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l433-st-nucleo/applications/main.c b/bsp/stm32/stm32l433-st-nucleo/applications/main.c
index 43c2522c51..93992725f1 100644
--- a/bsp/stm32/stm32l433-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32l433-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32l433-st-nucleo/board/Kconfig b/bsp/stm32/stm32l433-st-nucleo/board/Kconfig
index 81895298e8..667ab57345 100644
--- a/bsp/stm32/stm32l433-st-nucleo/board/Kconfig
+++ b/bsp/stm32/stm32l433-st-nucleo/board/Kconfig
@@ -70,7 +70,6 @@ menu "On-chip Peripheral Drivers"
     menuconfig BSP_USING_ONCHIP_RTC
         bool "Enable RTC"
         select RT_USING_RTC
-        select RT_USING_LIBC
         default n
         if BSP_USING_ONCHIP_RTC
             choice
diff --git a/bsp/stm32/stm32l433-st-nucleo/board/board.c b/bsp/stm32/stm32l433-st-nucleo/board/board.c
index 0cf319801f..284b759c59 100644
--- a/bsp/stm32/stm32l433-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32l433-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,11 +20,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  /** Configure LSE Drive Capability 
+  /** Configure LSE Drive Capability
   */
   HAL_PWR_EnableBkUpAccess();
   __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI;
   RCC_OscInitStruct.LSEState = RCC_LSE_ON;
@@ -42,7 +42,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
@@ -65,13 +65,13 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
   {
     Error_Handler();
   }
-  /** Enable MSI Auto calibration 
+  /** Enable MSI Auto calibration
   */
   HAL_RCCEx_EnableMSIPLLMode();
 }
diff --git a/bsp/stm32/stm32l433-st-nucleo/board/board.h b/bsp/stm32/stm32l433-st-nucleo/board/board.h
index 3b3a77e103..77db7fce6e 100644
--- a/bsp/stm32/stm32l433-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32l433-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l452-st-nucleo/applications/main.c b/bsp/stm32/stm32l452-st-nucleo/applications/main.c
index aad9acb9b9..5524d24935 100644
--- a/bsp/stm32/stm32l452-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32l452-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED2 pin mode to output */
     rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED2_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED2_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32l452-st-nucleo/board/board.c b/bsp/stm32/stm32l452-st-nucleo/board/board.c
index 5ab9da967a..d6c090b6b8 100644
--- a/bsp/stm32/stm32l452-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32l452-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,7 +20,7 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
@@ -36,7 +36,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
@@ -55,7 +55,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
   {
diff --git a/bsp/stm32/stm32l452-st-nucleo/board/board.h b/bsp/stm32/stm32l452-st-nucleo/board/board.h
index 1ea1e6be9c..0c9006dc40 100644
--- a/bsp/stm32/stm32l452-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32l452-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l452-st-nucleo/board/ports/fal_cfg.h b/bsp/stm32/stm32l452-st-nucleo/board/ports/fal_cfg.h
index db782a5991..09c420dae9 100644
--- a/bsp/stm32/stm32l452-st-nucleo/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32l452-st-nucleo/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,9 +20,9 @@ extern const struct fal_flash_dev stm32_onchip_flash;
 
 /* ========================= Device Configuration ========================== */
 #ifdef BSP_USING_ON_CHIP_FLASH
-#define ONCHIP_FLASH_DEV     &stm32_onchip_flash,  
+#define ONCHIP_FLASH_DEV     &stm32_onchip_flash,
 #else
-#define ONCHIP_FLASH_DEV    
+#define ONCHIP_FLASH_DEV
 #endif /* BSP_USING_ON_CHIP_FLASH */
 
 /* flash device table */
diff --git a/bsp/stm32/stm32l475-atk-pandora/applications/lcd_sample.c b/bsp/stm32/stm32l475-atk-pandora/applications/lcd_sample.c
index 3283560274..a89c5e0b9c 100644
--- a/bsp/stm32/stm32l475-atk-pandora/applications/lcd_sample.c
+++ b/bsp/stm32/stm32l475-atk-pandora/applications/lcd_sample.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -18,30 +18,30 @@
 
 static int lcd_sample(void)
 {
-    /*  */
+    /* 清屏 */
     lcd_clear(WHITE);
 
-    /* ʾ RT-Thread logo */
+    /* 显示 RT-Thread logo */
     lcd_show_image(0, 0, 240, 69, image_rttlogo);
-    
-    /* ñɫǰɫ */
+
+    /* 设置背景色和前景色 */
     lcd_set_color(WHITE, BLACK);
 
-    /*  LCD ʾַ */
+    /* 在 LCD 上显示字符 */
     lcd_show_string(10, 69, 16, "Hello, RT-Thread!");
     lcd_show_string(10, 69+16, 24, "RT-Thread");
     lcd_show_string(10, 69+16+24, 32, "RT-Thread");
-    
-    /*  LCD ϻ */
+
+    /* 在 LCD 上画线 */
     lcd_draw_line(0, 69+16+24+32, 240, 69+16+24+32);
-    
-    /*  LCD ϻһͬԲ */
+
+    /* 在 LCD 上画一个同心圆 */
     lcd_draw_point(120, 194);
     for (int i = 0; i < 46; i += 4)
     {
         lcd_draw_circle(120, 194, i);
     }
-    
+
     return RT_EOK;
 }
 INIT_APP_EXPORT(lcd_sample);
diff --git a/bsp/stm32/stm32l475-atk-pandora/applications/main.c b/bsp/stm32/stm32l475-atk-pandora/applications/main.c
index 97e08a7d42..7410e0463e 100644
--- a/bsp/stm32/stm32l475-atk-pandora/applications/main.c
+++ b/bsp/stm32/stm32l475-atk-pandora/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/Kconfig b/bsp/stm32/stm32l475-atk-pandora/board/Kconfig
index f6d822573b..5a11d21cc1 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/Kconfig
+++ b/bsp/stm32/stm32l475-atk-pandora/board/Kconfig
@@ -321,7 +321,6 @@ menu "On-chip Peripheral Drivers"
     menuconfig BSP_USING_ONCHIP_RTC
         bool "Enable RTC"
         select RT_USING_RTC
-        select RT_USING_LIBC
         default n
         if BSP_USING_ONCHIP_RTC
             choice
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/board.c b/bsp/stm32/stm32l475-atk-pandora/board/board.c
index e97c6784ae..6e2be4bf42 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/board.c
+++ b/bsp/stm32/stm32l475-atk-pandora/board/board.c
@@ -1,11 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -22,11 +18,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  /** Configure LSE Drive Capability 
+  /** Configure LSE Drive Capability
   */
   HAL_PWR_EnableBkUpAccess();
   __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
                               |RCC_OSCILLATORTYPE_LSE;
@@ -44,7 +40,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
@@ -76,7 +72,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
   {
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/board.h b/bsp/stm32/stm32l475-atk-pandora/board/board.h
index ee516b50db..a1029a3e99 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/board.h
+++ b/bsp/stm32/stm32l475-atk-pandora/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.c
index fe115eb593..5d9844c6bd 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.c
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.c
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- * 
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Date           Author       Notes
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.h b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.h
index 472c844fca..ac758960f8 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.h
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_es8388.h
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- * 
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Date           Author       Notes
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_mic.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_mic.c
index c4ea570dd7..ac604875f0 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_mic.c
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_mic.c
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- * 
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Date           Author       Notes
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.c
index bccf9c62db..b19d584d3d 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.c
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.c
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- * 
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Date           Author       Notes
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.h b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.h
index 4dc76631c7..d573b0dee5 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.h
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/audio/drv_sound.h
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- * 
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Date           Author       Notes
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.c
index 65bdcd85f9..f80ca3a4b2 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.c
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -955,7 +955,7 @@ rt_err_t lcd_show_qrcode(rt_uint16_t x, rt_uint16_t y, rt_uint8_t version, rt_ui
         {
             enlargement_factor = enlargement;
         }
-        
+
         /* malloc memory for quick display of qrcode */
         qrcode_buf = rt_malloc(qrcode.size * 2 * enlargement_factor * enlargement_factor);
         if (qrcode_buf == RT_NULL)
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.h b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.h
index ca4c28595f..394305012e 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.h
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd.h
@@ -1,12 +1,12 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author            Notes
  * 2018-08-14    flybreak           the first version
- * 2018-09-18    balanceTWK         add sleep mode function 
+ * 2018-09-18    balanceTWK         add sleep mode function
  */
 
 #ifndef __DRV_LCD_H__
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd_font.h b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd_font.h
index d73d3c4d62..a326936b7b 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd_font.h
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_lcd_font.h
@@ -1,5 +1,5 @@
 #ifndef __DRV_LCD_FONT_H__
-#define __DRV_LCD_FONT_H__ 	   
+#define __DRV_LCD_FONT_H__
 #include 
 /* DejaVu Sans Mono */
 /*
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_qspi_flash.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_qspi_flash.c
index aef2226239..f866d2741c 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_qspi_flash.c
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_qspi_flash.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-11-27     zylx         first version
  */
- 
+
 #include 
 #include 
 #include 
@@ -63,7 +63,7 @@ void w25qxx_enter_qspi_mode(struct rt_qspi_device *device)
 static int rt_hw_qspi_flash_with_sfud_init(void)
 {
     stm32_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, 4, w25qxx_enter_qspi_mode, RT_NULL);
-    
+
     /* init w25q128 */
     if (RT_NULL == rt_sfud_flash_probe("W25Q128", "qspi10"))
     {
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_sdio_adapter.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_sdio_adapter.c
index 92ec9d539b..c7f561e0b7 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_sdio_adapter.c
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/drv_sdio_adapter.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -46,10 +46,10 @@ void SD_LowLevel_DMA_TxConfig(uint32_t *src, uint32_t *dst, uint32_t BufferSize)
     DMA2_Channel4->CCR &= ~0x00000001;
 
     DMA2->IFCR = DMA_ISR_GIF1 << 4;
-    
+
     DMA2_CSELR->CSELR &= ~(0xf << (3 * 4));   // channel 4
-    DMA2_CSELR->CSELR |= (uint32_t) (0x07 << (3 * 4)); 
-    
+    DMA2_CSELR->CSELR |= (uint32_t) (0x07 << (3 * 4));
+
     DMA2_Channel4->CCR   = DMA_MEMORY_TO_PERIPH | DMA_PINC_DISABLE | DMA_MINC_ENABLE | \
                            DMA_PDATAALIGN_WORD | DMA_MDATAALIGN_WORD | DMA_NORMAL | DMA_PRIORITY_MEDIUM;
     DMA2_Channel4->CNDTR = BufferSize;
@@ -57,7 +57,7 @@ void SD_LowLevel_DMA_TxConfig(uint32_t *src, uint32_t *dst, uint32_t BufferSize)
     DMA2_Channel4->CMAR = (uint32_t)src;
 
     DMA2_Channel4->CCR  |= 0x00000001;
-    
+
 //    HAL_DMA_Start(&SDTxDMAHandler, (uint32_t)src, (uint32_t)dst, BufferSize);
 }
 
@@ -73,9 +73,9 @@ void SD_LowLevel_DMA_RxConfig(uint32_t *src, uint32_t *dst, uint32_t BufferSize)
     DMA2_Channel4->CCR &= ~0x00000001;
 
     DMA2->IFCR = DMA_ISR_GIF1 << 4;
-    
+
     DMA2_CSELR->CSELR &= ~(0xf << (3 * 4));   // channel 4
-    DMA2_CSELR->CSELR |= (uint32_t) (0x07 << (3 * 4)); 
+    DMA2_CSELR->CSELR |= (uint32_t) (0x07 << (3 * 4));
 
     DMA2_Channel4->CCR   = DMA_PERIPH_TO_MEMORY | DMA_PINC_DISABLE | DMA_MINC_ENABLE | \
                            DMA_PDATAALIGN_WORD | DMA_MDATAALIGN_WORD | DMA_NORMAL | DMA_PRIORITY_MEDIUM;
@@ -130,7 +130,7 @@ void SD_LowLevel_Init(void)
         GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
         GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1;
         HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
-        
+
         GPIO_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_10 | GPIO_PIN_11
                               | GPIO_PIN_12;
         GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/easyflash/ef_fal_port.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/easyflash/ef_fal_port.c
index 91ebb73e1e..5655b27237 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/easyflash/ef_fal_port.c
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/easyflash/ef_fal_port.c
@@ -1,11 +1,11 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 
+ *
  */
 
 #include 
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/fal_cfg.h b/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/fal_cfg.h
index a6d43e21ba..25ed2c3ff7 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/fal_cfg.h
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/fal_flash_sfud_port.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/fal_flash_sfud_port.c
index 3f1e4776b4..fc9a1c7ada 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/fal_flash_sfud_port.c
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/fal/fal_flash_sfud_port.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/sdcard_port.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/sdcard_port.c
index e1af109455..bf4babd15f 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/sdcard_port.c
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/sdcard_port.c
@@ -1,11 +1,12 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2018-12-14     balanceTWK   add sdcard port file
+ * 2021-02-26     Meco Man     fix a bug that cannot use fatfs in the main thread at starting up
  */
 
 #include 
@@ -46,16 +47,24 @@ int stm32_sdcard_mount(void)
 {
     rt_thread_t tid;
 
-    tid = rt_thread_create("sd_mount", sd_mount, RT_NULL,
-                           1024, RT_THREAD_PRIORITY_MAX - 2, 20);
-    if (tid != RT_NULL)
+    if (dfs_mount("sd0", "/", "elm", 0, 0) == RT_EOK)
     {
-        rt_thread_startup(tid);
+        LOG_I("sd card mount to '/'");
     }
     else
     {
-        LOG_E("create sd_mount thread err!");
+        tid = rt_thread_create("sd_mount", sd_mount, RT_NULL,
+                               1024, RT_THREAD_PRIORITY_MAX - 2, 20);
+        if (tid != RT_NULL)
+        {
+            rt_thread_startup(tid);
+        }
+        else
+        {
+            LOG_E("create sd_mount thread err!");
+        }
     }
+
     return RT_EOK;
 }
 INIT_APP_EXPORT(stm32_sdcard_mount);
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/sensor_port.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/sensor_port.c
index d253cc179e..fac1209a63 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/sensor_port.c
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/sensor_port.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/wifi/wifi_config.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/wifi/wifi_config.c
index fc5d4759e9..7f0986e0d7 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/wifi/wifi_config.c
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/wifi/wifi_config.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -200,7 +200,7 @@ static int read_cfg(void *buff, int len)
     {
         return 0;
     }
-    
+
     return len;
 }
 
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/wifi/wifi_config.h b/bsp/stm32/stm32l475-atk-pandora/board/ports/wifi/wifi_config.h
index 35a0fc8956..ee8477d9be 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/wifi/wifi_config.h
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/wifi/wifi_config.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/wlan/drv_wlan.c b/bsp/stm32/stm32l475-atk-pandora/board/ports/wlan/drv_wlan.c
index 6c56cbcf6f..431a18008c 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/wlan/drv_wlan.c
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/wlan/drv_wlan.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l475-atk-pandora/board/ports/wlan/drv_wlan.h b/bsp/stm32/stm32l475-atk-pandora/board/ports/wlan/drv_wlan.h
index 461c5f0e8d..e940dd99e2 100644
--- a/bsp/stm32/stm32l475-atk-pandora/board/ports/wlan/drv_wlan.h
+++ b/bsp/stm32/stm32l475-atk-pandora/board/ports/wlan/drv_wlan.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l475-atk-pandora/rtconfig.py b/bsp/stm32/stm32l475-atk-pandora/rtconfig.py
index f09dfbc3b7..9314a28375 100644
--- a/bsp/stm32/stm32l475-atk-pandora/rtconfig.py
+++ b/bsp/stm32/stm32l475-atk-pandora/rtconfig.py
@@ -73,7 +73,8 @@ elif PLATFORM == 'armcc':
     DEVICE = ' --cpu Cortex-M4.fp '
     CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
     AFLAGS = DEVICE + ' --apcs=interwork '
-    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict --scatter "board\linker_scripts\link.sct"'
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rt-thread.map '
+    LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" '
     CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
     LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
 
@@ -94,6 +95,39 @@ elif PLATFORM == 'armcc':
 
     POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
 
+elif PLATFORM == 'armclang':
+    # toolchains
+    CC = 'armclang'
+    CXX = 'armclang'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --cpu Cortex-M4.fp '
+    CFLAGS = ' -xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m4 '
+    CFLAGS += ' -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 '
+    CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar '
+    CFLAGS += ' -gdwarf-3 -ffunction-sections '
+    AFLAGS = DEVICE + ' --apcs=interwork '
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers '
+    LFLAGS += ' --list rt-thread.map '
+    LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" '
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include'
+    LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib'
+
+    EXEC_PATH += '/ARM/ARMCLANG/bin/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O1' # armclang recommend
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+        
+    CXXFLAGS = CFLAGS
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
 elif PLATFORM == 'iar':
     # toolchains
     CC = 'iccarm'
diff --git a/bsp/stm32/stm32l475-st-discovery/applications/main.c b/bsp/stm32/stm32l475-st-discovery/applications/main.c
index 2c4ca35a6b..c0c25b6705 100644
--- a/bsp/stm32/stm32l475-st-discovery/applications/main.c
+++ b/bsp/stm32/stm32l475-st-discovery/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32l475-st-discovery/board/board.c b/bsp/stm32/stm32l475-st-discovery/board/board.c
index bdd1307a91..cd2f9a5989 100644
--- a/bsp/stm32/stm32l475-st-discovery/board/board.c
+++ b/bsp/stm32/stm32l475-st-discovery/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,7 +16,7 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
@@ -32,7 +32,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
@@ -51,7 +51,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
   {
diff --git a/bsp/stm32/stm32l475-st-discovery/board/board.h b/bsp/stm32/stm32l475-st-discovery/board/board.h
index e49d71c68c..2b5f830eb9 100644
--- a/bsp/stm32/stm32l475-st-discovery/board/board.h
+++ b/bsp/stm32/stm32l475-st-discovery/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l476-st-nucleo/applications/main.c b/bsp/stm32/stm32l476-st-nucleo/applications/main.c
index e92ed8da71..2c204ae916 100644
--- a/bsp/stm32/stm32l476-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32l476-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32l476-st-nucleo/board/Kconfig b/bsp/stm32/stm32l476-st-nucleo/board/Kconfig
index 687ad3a85e..be9c0f7792 100644
--- a/bsp/stm32/stm32l476-st-nucleo/board/Kconfig
+++ b/bsp/stm32/stm32l476-st-nucleo/board/Kconfig
@@ -179,7 +179,6 @@ menu "On-chip Peripheral Drivers"
     menuconfig BSP_USING_ONCHIP_RTC
         bool "Enable RTC"
         select RT_USING_RTC
-        select RT_USING_LIBC
         default n
         if BSP_USING_ONCHIP_RTC
             choice
diff --git a/bsp/stm32/stm32l476-st-nucleo/board/board.c b/bsp/stm32/stm32l476-st-nucleo/board/board.c
index 88600d4b4f..0d279e679a 100644
--- a/bsp/stm32/stm32l476-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32l476-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l476-st-nucleo/board/board.h b/bsp/stm32/stm32l476-st-nucleo/board/board.h
index b59fe1b3b6..c0b6a905ff 100644
--- a/bsp/stm32/stm32l476-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32l476-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l476-st-nucleo/project.uvprojx b/bsp/stm32/stm32l476-st-nucleo/project.uvprojx
index bdbb353d3c..6b5c2aedb7 100644
--- a/bsp/stm32/stm32l476-st-nucleo/project.uvprojx
+++ b/bsp/stm32/stm32l476-st-nucleo/project.uvprojx
@@ -333,7 +333,7 @@
             0
             
               
-              RT_USING_ARM_LIBC, USE_HAL_DRIVER, STM32L476xx, __RTTHREAD__
+              RT_USING_ARM_LIBC, USE_HAL_DRIVER, STM32L476xx, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND
               
               applications;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;board\CubeMX_Config\Inc;board\ports;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\compilers\common;..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Inc;..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Include;..\libraries\STM32L4xx_HAL\CMSIS\Include
             
@@ -397,16 +397,16 @@
           
           
             
-              div0.c
+              showmem.c
               1
-              ..\..\..\libcpu\arm\common\div0.c
+              ..\..\..\libcpu\arm\common\showmem.c
             
           
           
             
-              showmem.c
+              div0.c
               1
-              ..\..\..\libcpu\arm\common\showmem.c
+              ..\..\..\libcpu\arm\common\div0.c
             
           
           
@@ -461,34 +461,6 @@
               ..\..\..\components\drivers\src\completion.c
             
           
-          
-            
-              dataqueue.c
-              1
-              ..\..\..\components\drivers\src\dataqueue.c
-            
-          
-          
-            
-              pipe.c
-              1
-              ..\..\..\components\drivers\src\pipe.c
-            
-          
-          
-            
-              ringblk_buf.c
-              1
-              ..\..\..\components\drivers\src\ringblk_buf.c
-            
-          
-          
-            
-              ringbuffer.c
-              1
-              ..\..\..\components\drivers\src\ringbuffer.c
-            
-          
           
             
               waitqueue.c
@@ -503,14 +475,42 @@
               ..\..\..\components\drivers\src\workqueue.c
             
           
+          
+            
+              ringbuffer.c
+              1
+              ..\..\..\components\drivers\src\ringbuffer.c
+            
+          
+          
+            
+              dataqueue.c
+              1
+              ..\..\..\components\drivers\src\dataqueue.c
+            
+          
+          
+            
+              ringblk_buf.c
+              1
+              ..\..\..\components\drivers\src\ringblk_buf.c
+            
+          
+          
+            
+              pipe.c
+              1
+              ..\..\..\components\drivers\src\pipe.c
+            
+          
         
         
           Drivers
           
             
-              board.c
-              1
-              board\board.c
+              startup_stm32l476xx.s
+              2
+              ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\arm\startup_stm32l476xx.s
             
           
           
@@ -522,9 +522,9 @@
           
           
             
-              startup_stm32l476xx.s
-              2
-              ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\arm\startup_stm32l476xx.s
+              board.c
+              1
+              board\board.c
             
           
           
@@ -536,16 +536,16 @@
           
           
             
-              drv_usart.c
+              drv_common.c
               1
-              ..\libraries\HAL_Drivers\drv_usart.c
+              ..\libraries\HAL_Drivers\drv_common.c
             
           
           
             
-              drv_pm.c
+              drv_usart.c
               1
-              ..\libraries\HAL_Drivers\drv_pm.c
+              ..\libraries\HAL_Drivers\drv_usart.c
             
           
           
@@ -557,9 +557,9 @@
           
           
             
-              drv_common.c
+              drv_pm.c
               1
-              ..\libraries\HAL_Drivers\drv_common.c
+              ..\libraries\HAL_Drivers\drv_pm.c
             
           
         
@@ -572,13 +572,6 @@
               ..\..\..\components\finsh\shell.c
             
           
-          
-            
-              cmd.c
-              1
-              ..\..\..\components\finsh\cmd.c
-            
-          
           
             
               msh.c
@@ -586,9 +579,23 @@
               ..\..\..\components\finsh\msh.c
             
           
+          
+            
+              cmd.c
+              1
+              ..\..\..\components\finsh\cmd.c
+            
+          
         
         
           Kernel
+          
+            
+              timer.c
+              1
+              ..\..\..\src\timer.c
+            
+          
           
             
               clock.c
@@ -598,30 +605,9 @@
           
           
             
-              components.c
+              object.c
               1
-              ..\..\..\src\components.c
-            
-          
-          
-            
-              device.c
-              1
-              ..\..\..\src\device.c
-            
-          
-          
-            
-              idle.c
-              1
-              ..\..\..\src\idle.c
-            
-          
-          
-            
-              ipc.c
-              1
-              ..\..\..\src\ipc.c
+              ..\..\..\src\object.c
             
           
           
@@ -640,23 +626,9 @@
           
           
             
-              mem.c
+              ipc.c
               1
-              ..\..\..\src\mem.c
-            
-          
-          
-            
-              mempool.c
-              1
-              ..\..\..\src\mempool.c
-            
-          
-          
-            
-              object.c
-              1
-              ..\..\..\src\object.c
+              ..\..\..\src\ipc.c
             
           
           
@@ -666,13 +638,6 @@
               ..\..\..\src\scheduler.c
             
           
-          
-            
-              signal.c
-              1
-              ..\..\..\src\signal.c
-            
-          
           
             
               thread.c
@@ -682,21 +647,42 @@
           
           
             
-              timer.c
+              idle.c
               1
-              ..\..\..\src\timer.c
+              ..\..\..\src\idle.c
+            
+          
+          
+            
+              components.c
+              1
+              ..\..\..\src\components.c
+            
+          
+          
+            
+              device.c
+              1
+              ..\..\..\src\device.c
+            
+          
+          
+            
+              mempool.c
+              1
+              ..\..\..\src\mempool.c
+            
+          
+          
+            
+              mem.c
+              1
+              ..\..\..\src\mem.c
             
           
         
         
           libc
-          
-            
-              libc.c
-              1
-              ..\..\..\components\libc\compilers\armlibc\libc.c
-            
-          
           
             
               mem_std.c
@@ -706,9 +692,23 @@
           
           
             
-              stubs.c
+              syscalls.c
               1
-              ..\..\..\components\libc\compilers\armlibc\stubs.c
+              ..\..\..\components\libc\compilers\armlibc\syscalls.c
+            
+          
+          
+            
+              libc.c
+              1
+              ..\..\..\components\libc\compilers\armlibc\libc.c
+            
+          
+          
+            
+              stdlib.c
+              1
+              ..\..\..\components\libc\compilers\common\stdlib.c
             
           
           
@@ -723,23 +723,9 @@
           Libraries
           
             
-              system_stm32l4xx.c
+              stm32l4xx_hal_cryp.c
               1
-              ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\system_stm32l4xx.c
-            
-          
-          
-            
-              stm32l4xx_hal.c
-              1
-              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c
-            
-          
-          
-            
-              stm32l4xx_hal_comp.c
-              1
-              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_comp.c
+              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp.c
             
           
           
@@ -749,69 +735,6 @@
               ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c
             
           
-          
-            
-              stm32l4xx_hal_crc.c
-              1
-              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc.c
-            
-          
-          
-            
-              stm32l4xx_hal_crc_ex.c
-              1
-              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc_ex.c
-            
-          
-          
-            
-              stm32l4xx_hal_cryp.c
-              1
-              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp.c
-            
-          
-          
-            
-              stm32l4xx_hal_cryp_ex.c
-              1
-              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp_ex.c
-            
-          
-          
-            
-              stm32l4xx_hal_dma.c
-              1
-              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c
-            
-          
-          
-            
-              stm32l4xx_hal_dma_ex.c
-              1
-              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c
-            
-          
-          
-            
-              stm32l4xx_hal_exti.c
-              1
-              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c
-            
-          
-          
-            
-              stm32l4xx_hal_pwr.c
-              1
-              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c
-            
-          
-          
-            
-              stm32l4xx_hal_pwr_ex.c
-              1
-              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c
-            
-          
           
             
               stm32l4xx_hal_rcc.c
@@ -819,55 +742,6 @@
               ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c
             
           
-          
-            
-              stm32l4xx_hal_rcc_ex.c
-              1
-              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c
-            
-          
-          
-            
-              stm32l4xx_hal_rng.c
-              1
-              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rng.c
-            
-          
-          
-            
-              stm32l4xx_hal_gpio.c
-              1
-              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c
-            
-          
-          
-            
-              stm32l4xx_hal_uart.c
-              1
-              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart.c
-            
-          
-          
-            
-              stm32l4xx_hal_uart_ex.c
-              1
-              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart_ex.c
-            
-          
-          
-            
-              stm32l4xx_hal_usart.c
-              1
-              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart.c
-            
-          
-          
-            
-              stm32l4xx_hal_usart_ex.c
-              1
-              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart_ex.c
-            
-          
           
             
               stm32l4xx_hal_rtc.c
@@ -877,9 +751,58 @@
           
           
             
-              stm32l4xx_hal_rtc_ex.c
+              stm32l4xx_hal_pwr.c
               1
-              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rtc_ex.c
+              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c
+            
+          
+          
+            
+              stm32l4xx_hal_usart_ex.c
+              1
+              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart_ex.c
+            
+          
+          
+            
+              system_stm32l4xx.c
+              1
+              ..\libraries\STM32L4xx_HAL\CMSIS\Device\ST\STM32L4xx\Source\Templates\system_stm32l4xx.c
+            
+          
+          
+            
+              stm32l4xx_hal_pwr_ex.c
+              1
+              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c
+            
+          
+          
+            
+              stm32l4xx_hal_usart.c
+              1
+              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart.c
+            
+          
+          
+            
+              stm32l4xx_hal_cryp_ex.c
+              1
+              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp_ex.c
+            
+          
+          
+            
+              stm32l4xx_hal_rcc_ex.c
+              1
+              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c
+            
+          
+          
+            
+              stm32l4xx_hal_uart.c
+              1
+              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart.c
             
           
           
@@ -889,6 +812,83 @@
               ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_lptim.c
             
           
+          
+            
+              stm32l4xx_hal_dma_ex.c
+              1
+              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma_ex.c
+            
+          
+          
+            
+              stm32l4xx_hal_gpio.c
+              1
+              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c
+            
+          
+          
+            
+              stm32l4xx_hal_crc_ex.c
+              1
+              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc_ex.c
+            
+          
+          
+            
+              stm32l4xx_hal_dma.c
+              1
+              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c
+            
+          
+          
+            
+              stm32l4xx_hal.c
+              1
+              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c
+            
+          
+          
+            
+              stm32l4xx_hal_rtc_ex.c
+              1
+              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rtc_ex.c
+            
+          
+          
+            
+              stm32l4xx_hal_comp.c
+              1
+              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_comp.c
+            
+          
+          
+            
+              stm32l4xx_hal_exti.c
+              1
+              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_exti.c
+            
+          
+          
+            
+              stm32l4xx_hal_rng.c
+              1
+              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rng.c
+            
+          
+          
+            
+              stm32l4xx_hal_crc.c
+              1
+              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc.c
+            
+          
+          
+            
+              stm32l4xx_hal_uart_ex.c
+              1
+              ..\libraries\STM32L4xx_HAL\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart_ex.c
+            
+          
         
       
     
diff --git a/bsp/stm32/stm32l496-ali-developer/applications/main.c b/bsp/stm32/stm32l496-ali-developer/applications/main.c
index d4926deb07..1d40627d3c 100644
--- a/bsp/stm32/stm32l496-ali-developer/applications/main.c
+++ b/bsp/stm32/stm32l496-ali-developer/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32l496-ali-developer/board/Kconfig b/bsp/stm32/stm32l496-ali-developer/board/Kconfig
index e40739e494..840210dc2c 100644
--- a/bsp/stm32/stm32l496-ali-developer/board/Kconfig
+++ b/bsp/stm32/stm32l496-ali-developer/board/Kconfig
@@ -201,7 +201,6 @@ menu "On-chip Peripheral Drivers"
     menuconfig BSP_USING_ONCHIP_RTC
         bool "Enable RTC"
         select RT_USING_RTC
-        select RT_USING_LIBC
         default n
         if BSP_USING_ONCHIP_RTC
             choice
diff --git a/bsp/stm32/stm32l496-ali-developer/board/board.c b/bsp/stm32/stm32l496-ali-developer/board/board.c
index f9413f8f98..9622e73038 100644
--- a/bsp/stm32/stm32l496-ali-developer/board/board.c
+++ b/bsp/stm32/stm32l496-ali-developer/board/board.c
@@ -1,11 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -20,11 +16,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  /**Configure LSE Drive Capability 
+  /**Configure LSE Drive Capability
   */
   HAL_PWR_EnableBkUpAccess();
   __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_LSE
                               |RCC_OSCILLATORTYPE_MSI;
@@ -44,7 +40,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Initializes the CPU, AHB and APB busses clocks 
+  /**Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
@@ -77,7 +73,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /**Configure the main internal regulator output voltage 
+  /**Configure the main internal regulator output voltage
   */
   if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
   {
diff --git a/bsp/stm32/stm32l496-ali-developer/board/board.h b/bsp/stm32/stm32l496-ali-developer/board/board.h
index 78cc07314b..6d99022522 100644
--- a/bsp/stm32/stm32l496-ali-developer/board/board.h
+++ b/bsp/stm32/stm32l496-ali-developer/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l496-ali-developer/board/ports/drv_spi_lcd.c b/bsp/stm32/stm32l496-ali-developer/board/ports/drv_spi_lcd.c
index e37a67f4a1..be6c2a5744 100644
--- a/bsp/stm32/stm32l496-ali-developer/board/ports/drv_spi_lcd.c
+++ b/bsp/stm32/stm32l496-ali-developer/board/ports/drv_spi_lcd.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018-11-27     zylx         first version
  */
- 
+
 #include 
 #include 
 #include 
diff --git a/bsp/stm32/stm32l496-ali-developer/board/ports/fal_cfg.h b/bsp/stm32/stm32l496-ali-developer/board/ports/fal_cfg.h
index d7a1db25e9..a0598e9d83 100644
--- a/bsp/stm32/stm32l496-ali-developer/board/ports/fal_cfg.h
+++ b/bsp/stm32/stm32l496-ali-developer/board/ports/fal_cfg.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l496-ali-developer/board/ports/sdcard_port.c b/bsp/stm32/stm32l496-ali-developer/board/ports/sdcard_port.c
index 8a2c1cade7..6abc52c3ba 100644
--- a/bsp/stm32/stm32l496-ali-developer/board/ports/sdcard_port.c
+++ b/bsp/stm32/stm32l496-ali-developer/board/ports/sdcard_port.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l496-st-nucleo/applications/main.c b/bsp/stm32/stm32l496-st-nucleo/applications/main.c
index 20931cb3af..6c19612f99 100644
--- a/bsp/stm32/stm32l496-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32l496-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,17 +17,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED2 pin mode to output */
     rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED2_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED2_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32l496-st-nucleo/board/board.c b/bsp/stm32/stm32l496-st-nucleo/board/board.c
index 370b558be0..05887f6152 100644
--- a/bsp/stm32/stm32l496-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32l496-st-nucleo/board/board.c
@@ -1,11 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009 RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -22,11 +18,11 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  /** Configure LSE Drive Capability 
+  /** Configure LSE Drive Capability
   */
   HAL_PWR_EnableBkUpAccess();
   __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI;
   RCC_OscInitStruct.LSEState = RCC_LSE_ON;
@@ -44,7 +40,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
@@ -71,13 +67,13 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
   {
     Error_Handler();
   }
-  /** Enable MSI Auto calibration 
+  /** Enable MSI Auto calibration
   */
   HAL_RCCEx_EnableMSIPLLMode();
 }
diff --git a/bsp/stm32/stm32l496-st-nucleo/board/board.h b/bsp/stm32/stm32l496-st-nucleo/board/board.h
index b215ae9ee8..f9edac21da 100644
--- a/bsp/stm32/stm32l496-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32l496-st-nucleo/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l4r5-st-nucleo/applications/main.c b/bsp/stm32/stm32l4r5-st-nucleo/applications/main.c
index df59d02ff9..845e68f25f 100644
--- a/bsp/stm32/stm32l4r5-st-nucleo/applications/main.c
+++ b/bsp/stm32/stm32l4r5-st-nucleo/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -19,21 +19,17 @@
 /* defined the LED3 pin: PB14 */
 #define LED3_PIN    GET_PIN(B, 14)
 
-#define LED_RUN_PIN	LED3_PIN
+#define LED_RUN_PIN LED3_PIN
 
 int main(void)
 {
-    int count = 1;
-		
     rt_pin_mode(LED_RUN_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED_RUN_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED_RUN_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32l4r5-st-nucleo/board/Kconfig b/bsp/stm32/stm32l4r5-st-nucleo/board/Kconfig
index 90fb8181a4..7bd50d0bde 100644
--- a/bsp/stm32/stm32l4r5-st-nucleo/board/Kconfig
+++ b/bsp/stm32/stm32l4r5-st-nucleo/board/Kconfig
@@ -102,7 +102,6 @@ menu "Hardware Drivers Config"
         menuconfig BSP_USING_ONCHIP_RTC
             bool "Enable RTC"
             select RT_USING_RTC
-            select RT_USING_LIBC
             default n
             if BSP_USING_ONCHIP_RTC
                 choice
diff --git a/bsp/stm32/stm32l4r5-st-nucleo/board/board.c b/bsp/stm32/stm32l4r5-st-nucleo/board/board.c
index 7ab82ccd58..4b1fccdb4e 100644
--- a/bsp/stm32/stm32l4r5-st-nucleo/board/board.c
+++ b/bsp/stm32/stm32l4r5-st-nucleo/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,13 +16,13 @@ void SystemClock_Config(void)
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-  /** Configure the main internal regulator output voltage 
+  /** Configure the main internal regulator output voltage
   */
   if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
@@ -38,7 +38,7 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
-  /** Initializes the CPU, AHB and APB busses clocks 
+  /** Initializes the CPU, AHB and APB busses clocks
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
diff --git a/bsp/stm32/stm32l4r5-st-nucleo/board/board.h b/bsp/stm32/stm32l4r5-st-nucleo/board/board.h
index 095f503423..b90222c6e3 100644
--- a/bsp/stm32/stm32l4r5-st-nucleo/board/board.h
+++ b/bsp/stm32/stm32l4r5-st-nucleo/board/board.h
@@ -1,12 +1,12 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2018-11-5      SummerGift   first version
- * 2019-04-09	  jhb
+ * 2019-04-09     jhb
  */
 
 #ifndef __BOARD_H__
diff --git a/bsp/stm32/stm32l4r9-st-eval/applications/main.c b/bsp/stm32/stm32l4r9-st-eval/applications/main.c
index ee74c2edd2..ea49f25f87 100644
--- a/bsp/stm32/stm32l4r9-st-eval/applications/main.c
+++ b/bsp/stm32/stm32l4r9-st-eval/applications/main.c
@@ -1,12 +1,12 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2018-11-06     SummerGift   first version
- * 2019-04-09     jhb   			  
+ * 2019-04-09     jhb
  */
 
 #include 
@@ -18,17 +18,14 @@
 
 int main(void)
 {
-    int count = 1;
     /* set LED0 pin mode to output */
     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
 
-    while (count++)
+    while (1)
     {
         rt_pin_write(LED0_PIN, PIN_HIGH);
         rt_thread_mdelay(500);
         rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32l4r9-st-eval/board/board.c b/bsp/stm32/stm32l4r9-st-eval/board/board.c
index af69f12729..cf4231f00c 100644
--- a/bsp/stm32/stm32l4r9-st-eval/board/board.c
+++ b/bsp/stm32/stm32l4r9-st-eval/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,13 +16,13 @@ void SystemClock_Config(void)
     RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
     RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
-    /**Configure the main internal regulator output voltage 
+    /**Configure the main internal regulator output voltage
     */
     if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) != HAL_OK)
     {
         Error_Handler();
     }
-    /**Initializes the CPU, AHB and APB busses clocks 
+    /**Initializes the CPU, AHB and APB busses clocks
     */
     RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
     RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -37,7 +37,7 @@ void SystemClock_Config(void)
     {
         Error_Handler();
     }
-    /**Initializes the CPU, AHB and APB busses clocks 
+    /**Initializes the CPU, AHB and APB busses clocks
     */
     RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
     RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
@@ -63,5 +63,5 @@ void SystemClock_Config(void)
     if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
     {
         Error_Handler();
-    }	
+    }
 }
diff --git a/bsp/stm32/stm32l4r9-st-eval/board/board.h b/bsp/stm32/stm32l4r9-st-eval/board/board.h
index f9f8adbcf8..7d85022bb4 100644
--- a/bsp/stm32/stm32l4r9-st-eval/board/board.h
+++ b/bsp/stm32/stm32l4r9-st-eval/board/board.h
@@ -1,12 +1,12 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2018-11-5      SummerGift   first version
- * 2019-04-09	  jhb
+ * 2019-04-09     jhb
  */
 
 #ifndef __BOARD_H__
diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_lcd_dsi.c b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_lcd_dsi.c
index 8e926d7e2d..e00616eaac 100644
--- a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_lcd_dsi.c
+++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_lcd_dsi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -706,17 +706,17 @@ void line()
     lcd = (struct drv_lcd_dsi_device *)rt_device_find("lcd_dsi");
     rt_uint8_t *ptr = lcd->lcd_info.framebuffer;
 
-		/* red */
-		for (unsigned long long i = LCD_DSI_BUF_SIZE/4/2; i parent, RTGRAPHIC_CTRL_RECT_UPDATE, RT_NULL);
+        /* red */
+        for (unsigned long long i = LCD_DSI_BUF_SIZE/4/2; i parent, RTGRAPHIC_CTRL_RECT_UPDATE, RT_NULL);
+
 
-	
 }
 MSH_CMD_EXPORT(line, line);
 
diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_sram.c b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_sram.c
index f77fa05aee..416e6863a7 100644
--- a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_sram.c
+++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_sram.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch.c b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch.c
index 314b1d707f..dc24066f51 100644
--- a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch.c
+++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch_ft.c b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch_ft.c
index 726be84e0d..0d3904444f 100644
--- a/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch_ft.c
+++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/drv_touch_ft.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -119,7 +119,7 @@ static rt_err_t ft_read_point(touch_msg_t msg)
     {
         return RT_ERROR;
     }
-    
+
     if (point_num == 0)
     {
         if (s_tp_down)
@@ -131,7 +131,7 @@ static rt_err_t ft_read_point(touch_msg_t msg)
         msg->event = TOUCH_EVENT_NONE;
         return RT_ERROR;
     }
-    
+
     ret = ft_read(ft_i2c_bus, 0x03, point, 6);
     if (ret < 0)
     {
@@ -147,7 +147,7 @@ static rt_err_t ft_read_point(touch_msg_t msg)
     }
     msg->event = TOUCH_EVENT_DOWN;
     s_tp_down = 1;
-    
+
     return RT_EOK;
 }
 
diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/include/drv_touch.h b/bsp/stm32/stm32l4r9-st-eval/board/ports/include/drv_touch.h
index 0e0cfae502..b70dd3eb25 100644
--- a/bsp/stm32/stm32l4r9-st-eval/board/ports/include/drv_touch.h
+++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/include/drv_touch.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/include/lcd_port_dsi.h b/bsp/stm32/stm32l4r9-st-eval/board/ports/include/lcd_port_dsi.h
index fbc56b4a44..4d602fc344 100644
--- a/bsp/stm32/stm32l4r9-st-eval/board/ports/include/lcd_port_dsi.h
+++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/include/lcd_port_dsi.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32l4r9-st-eval/board/ports/include/sram_port.h b/bsp/stm32/stm32l4r9-st-eval/board/ports/include/sram_port.h
index a5d89f1d80..f02a735dc4 100644
--- a/bsp/stm32/stm32l4r9-st-eval/board/ports/include/sram_port.h
+++ b/bsp/stm32/stm32l4r9-st-eval/board/ports/include/sram_port.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32mp157a-st-discovery/.config b/bsp/stm32/stm32mp157a-st-discovery/.config
index 5715750c67..47f0965c66 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/.config
+++ b/bsp/stm32/stm32mp157a-st-discovery/.config
@@ -55,6 +55,8 @@ CONFIG_RT_USING_MEMHEAP=y
 # CONFIG_RT_USING_SMALL_MEM is not set
 # CONFIG_RT_USING_SLAB is not set
 CONFIG_RT_USING_MEMHEAP_AS_HEAP=y
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
 CONFIG_RT_USING_HEAP=y
 
 #
@@ -154,7 +156,7 @@ CONFIG_RT_USING_PIN=y
 #
 # CONFIG_RT_USING_LIBC is not set
 # CONFIG_RT_USING_PTHREADS is not set
-# CONFIG_RT_LIBC_USING_TIME is not set
+CONFIG_RT_LIBC_USING_TIME=y
 
 #
 # Network
@@ -260,8 +262,6 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_LIBRWS is not set
 # CONFIG_PKG_USING_TCPSERVER is not set
 # CONFIG_PKG_USING_PROTOBUF_C is not set
-# CONFIG_PKG_USING_ONNX_PARSER is not set
-# CONFIG_PKG_USING_ONNX_BACKEND is not set
 # CONFIG_PKG_USING_DLT645 is not set
 # CONFIG_PKG_USING_QXWZ is not set
 # CONFIG_PKG_USING_SMTP_CLIENT is not set
@@ -275,6 +275,9 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_PDULIB is not set
 # CONFIG_PKG_USING_BTSTACK is not set
 # CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
 
 #
 # security packages
@@ -302,6 +305,7 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_TJPGD is not set
 # CONFIG_PKG_USING_HELIX is not set
 # CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
 
 #
 # tools packages
@@ -313,9 +317,12 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_RDB is not set
 # CONFIG_PKG_USING_QRCODE is not set
 # CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
+# CONFIG_PKG_USING_LOGMGR is not set
 # CONFIG_PKG_USING_ADBD is not set
 # CONFIG_PKG_USING_COREMARK is not set
 # CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
 # CONFIG_PKG_USING_NR_MICRO_SHELL is not set
 # CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
 # CONFIG_PKG_USING_LUNAR_CALENDAR is not set
@@ -323,6 +330,18 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_GPS_RMC is not set
 # CONFIG_PKG_USING_URLENCODE is not set
 # CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
 
 #
 # system packages
@@ -341,6 +360,8 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_CMSIS is not set
 # CONFIG_PKG_USING_DFS_YAFFS is not set
 # CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
 # CONFIG_PKG_USING_THREAD_POOL is not set
 # CONFIG_PKG_USING_ROBOTS is not set
 # CONFIG_PKG_USING_EV is not set
@@ -355,11 +376,20 @@ CONFIG_RT_USING_PIN=y
 # Micrium: Micrium software products porting for RT-Thread
 #
 # CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
 # CONFIG_PKG_USING_UC_CRC is not set
 # CONFIG_PKG_USING_UC_CLK is not set
 # CONFIG_PKG_USING_UC_COMMON is not set
 # CONFIG_PKG_USING_UC_MODBUS is not set
 # CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
 
 #
 # peripheral libraries and drivers
@@ -368,6 +398,7 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_REALTEK_AMEBA is not set
 # CONFIG_PKG_USING_SHT2X is not set
 # CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AS7341 is not set
 # CONFIG_PKG_USING_STM32_SDIO is not set
 # CONFIG_PKG_USING_ICM20608 is not set
 # CONFIG_PKG_USING_U8G2 is not set
@@ -416,6 +447,26 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_DM9051 is not set
 # CONFIG_PKG_USING_SSD1306 is not set
 # CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
 
 #
 # miscellaneous packages
@@ -425,6 +476,7 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_FASTLZ is not set
 # CONFIG_PKG_USING_MINILZO is not set
 # CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
 # CONFIG_PKG_USING_MULTIBUTTON is not set
 # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
 # CONFIG_PKG_USING_CANFESTIVAL is not set
@@ -446,19 +498,22 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_HELLO is not set
 # CONFIG_PKG_USING_VI is not set
 # CONFIG_PKG_USING_KI is not set
-# CONFIG_PKG_USING_NNOM is not set
-# CONFIG_PKG_USING_LIBANN is not set
-# CONFIG_PKG_USING_ELAPACK is not set
 # CONFIG_PKG_USING_ARMv7M_DWT is not set
 # CONFIG_PKG_USING_VT100 is not set
-# CONFIG_PKG_USING_TETRIS is not set
-# CONFIG_PKG_USING_ULAPACK is not set
 # CONFIG_PKG_USING_UKAL is not set
 # CONFIG_PKG_USING_CRCLIB is not set
+
+#
+# games: games run on RT-Thread console
+#
 # CONFIG_PKG_USING_THREES is not set
 # CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
 # CONFIG_PKG_USING_LWGPS is not set
-# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_COWSAY is not set
 CONFIG_SOC_FAMILY_STM32=y
 CONFIG_SOC_SERIES_STM32MP1=y
 
@@ -479,6 +534,7 @@ CONFIG_BSP_USING_STLINK_TO_USART=y
 # CONFIG_BSP_USING_RS485 is not set
 # CONFIG_BSP_USING_GBE is not set
 # CONFIG_BSP_USING_SDMMC is not set
+# CONFIG_BSP_USING_RTC is not set
 # CONFIG_BSP_USING_AUDIO is not set
 
 #
diff --git a/bsp/stm32/stm32mp157a-st-discovery/applications/main.c b/bsp/stm32/stm32mp157a-st-discovery/applications/main.c
index d8f61de87e..b5425e474b 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/applications/main.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/applications/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,19 +15,16 @@
 /* defined the LD7 pin: PH7 */
 #define LED7_PIN    GET_PIN(H, 7)
 
-int main(void) 
+int main(void)
 {
-    int count = 1;
     /* set LD7 pin mode to output */
     rt_pin_mode(LED7_PIN, PIN_MODE_OUTPUT);
-    
-    while (count++)
+
+    while (1)
     {
         rt_pin_write(LED7_PIN, PIN_HIGH);
-        rt_thread_mdelay(500);    
+        rt_thread_mdelay(500);
         rt_pin_write(LED7_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
-    
-    return RT_EOK;
 }
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Inc/stm32mp1xx_hal_conf.h b/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Inc/stm32mp1xx_hal_conf.h
index 3ba077b0b5..b7fd4ce81f 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Inc/stm32mp1xx_hal_conf.h
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Inc/stm32mp1xx_hal_conf.h
@@ -60,7 +60,7 @@
 #define HAL_SAI_MODULE_ENABLED
 #define HAL_SD_MODULE_ENABLED
 /*#define HAL_MMC_MODULE_ENABLED   */
-/*#define HAL_RTC_MODULE_ENABLED   */
+#define HAL_RTC_MODULE_ENABLED
 /*#define HAL_SMBUS_MODULE_ENABLED   */
 /*#define HAL_SPDIFRX_MODULE_ENABLED   */
 #define HAL_SPI_MODULE_ENABLED
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c b/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c
index 3a6fac25d7..5ca08fbbd0 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/CubeMX_Config/CM4/Src/stm32mp1xx_hal_msp.c
@@ -1003,7 +1003,66 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd)
 
   /* USER CODE END SDMMC1_MspInit 1 */
   }
+  if(hsd->Instance==SDMMC2)
+  {
+  /* USER CODE BEGIN SDMMC2_MspInit 0 */
+    if (IS_ENGINEERING_BOOT_MODE())
+    {
+        /** Initializes the peripherals clock 
+        */
+        PeriphClkInit.Sdmmc12ClockSelection = RCC_SDMMC12CLKSOURCE_PLL4;
+        PeriphClkInit.PeriphClockSelection  = RCC_PERIPHCLK_SDMMC12;
+        if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+        {
+            Error_Handler();
+        }
+    }
+  /* USER CODE END SDMMC2_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_SDMMC2_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_GPIOE_CLK_ENABLE();
+    __HAL_RCC_GPIOG_CLK_ENABLE();
+    /**SDMMC2 GPIO Configuration    
+    PB14     ------> SDMMC2_D0
+    PB15     ------> SDMMC2_D1
+    PB3     ------> SDMMC2_D2
+    PB4     ------> SDMMC2_D3
+    PE3     ------> SDMMC2_CK
+    PG6     ------> SDMMC2_CMD 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_14|GPIO_PIN_15;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF9_SDIO2;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 
+    GPIO_InitStruct.Pin = GPIO_PIN_3;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF9_SDIO2;
+    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_6;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF10_SDIO2;
+    HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+    __HAL_RCC_SDMMC2_FORCE_RESET();
+    __HAL_RCC_SDMMC2_RELEASE_RESET();
+  
+    /* SDMMC2 interrupt Init */
+    HAL_NVIC_SetPriority(SDMMC2_IRQn, 2, 0);
+    HAL_NVIC_EnableIRQ(SDMMC2_IRQn);
+  /* USER CODE BEGIN SDMMC2_MspInit 1 */
+
+  /* USER CODE END SDMMC2_MspInit 1 */
+  }
 }
 
 /**
@@ -1312,6 +1371,65 @@ void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef* hcryp)
 
 }
 #endif
+
+/**
+* @brief RTC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
+{
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN SDMMC1_MspInit 0 */
+    if (IS_ENGINEERING_BOOT_MODE())
+    {
+        /** Initializes the peripherals clock 
+        */
+        PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+        PeriphClkInit.PeriphClockSelection  = RCC_PERIPHCLK_RTC;
+        if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+        {
+            Error_Handler();
+        }
+    }
+  /* USER CODE BEGIN RTC_MspInit 0 */
+
+  /* USER CODE END RTC_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_RTC_ENABLE();
+
+  /* USER CODE BEGIN RTC_MspInit 1 */
+
+  /* USER CODE END RTC_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief RTC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hrtc: RTC handle pointer
+* @retval None
+*/
+void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
+{
+  if(hrtc->Instance==RTC)
+  {
+  /* USER CODE BEGIN RTC_MspDeInit 0 */
+
+  /* USER CODE END RTC_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_RTC_DISABLE();
+
+  /* USER CODE BEGIN RTC_MspDeInit 1 */
+
+  /* USER CODE END RTC_MspDeInit 1 */
+  }
+
+}
 /**
   * @brief  This function is executed in case of error occurrence.
   * @retval None
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/Kconfig b/bsp/stm32/stm32mp157a-st-discovery/board/Kconfig
index 9191443847..36ba61a584 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/Kconfig
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/Kconfig
@@ -58,10 +58,23 @@ menu "Onboard Peripheral Drivers"
         select RT_USING_LWIP
         
     config BSP_USING_SDMMC
-        bool "Enable SDMMC (SD card)"
+        bool "Enable SDMMC (sd card or sdio wifi)"
+        default n
         select RT_USING_SDIO
         select RT_USING_DFS
         select RT_USING_DFS_ELMFAT
+        if BSP_USING_SDMMC
+            config BSP_USING_SDIO1
+                bool "Enable SDIO1 (sd card)"
+                default n
+            config BSP_USING_SDIO2
+                select BSP_USING_RTC
+                bool "Enable SDIO2 (sdio wifi)"
+                default n
+        endif
+
+    config BSP_USING_RTC
+        bool "Enable RTC"
         default n
 
     menuconfig BSP_USING_AUDIO
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/board.c b/bsp/stm32/stm32mp157a-st-discovery/board/board.c
index cb44c09515..92180ecaa8 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/board.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/board.c
@@ -1,5 +1,5 @@
 /*
-* Copyright (c) 2006-2018, RT-Thread Development Team
+* Copyright (c) 2006-2021, RT-Thread Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -20,13 +20,13 @@ void SystemClock_Config(void)
 {
     RCC_OscInitTypeDef RCC_OscInitStruct = {0};
     RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-    
+
     /**Configure LSE Drive Capability
     */
     HAL_PWR_EnableBkUpAccess();
     __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMHIGH);
-    
-    /**Initializes the CPU, AHB and APB busses clocks 
+
+    /**Initializes the CPU, AHB and APB busses clocks
     */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSI
                               |RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE
@@ -39,7 +39,7 @@ void SystemClock_Config(void)
   RCC_OscInitStruct.LSIState = RCC_LSI_ON;
   RCC_OscInitStruct.CSIState = RCC_CSI_ON;
   RCC_OscInitStruct.CSICalibrationValue = 0x10; /* Default reset value */
-    
+
     /**PLL1 Config
     */
     RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
@@ -53,7 +53,7 @@ void SystemClock_Config(void)
     RCC_OscInitStruct.PLL.PLLMODE = RCC_PLL_FRACTIONAL;
     RCC_OscInitStruct.PLL.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED;
     RCC_OscInitStruct.PLL.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED;
-    
+
     /**PLL2 Config
     */
     RCC_OscInitStruct.PLL2.PLLState = RCC_PLL_ON;
@@ -67,7 +67,7 @@ void SystemClock_Config(void)
     RCC_OscInitStruct.PLL2.PLLMODE = RCC_PLL_FRACTIONAL;
     RCC_OscInitStruct.PLL2.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED;
     RCC_OscInitStruct.PLL2.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED;
-    
+
     /**PLL3 Config
     */
     RCC_OscInitStruct.PLL3.PLLState = RCC_PLL_ON;
@@ -82,7 +82,7 @@ void SystemClock_Config(void)
     RCC_OscInitStruct.PLL3.PLLMODE = RCC_PLL_FRACTIONAL;
     RCC_OscInitStruct.PLL3.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED;
     RCC_OscInitStruct.PLL3.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED;
-    
+
     /**PLL4 Config
     */
     RCC_OscInitStruct.PLL4.PLLState = RCC_PLL_ON;
@@ -97,7 +97,7 @@ void SystemClock_Config(void)
     RCC_OscInitStruct.PLL4.PLLMODE = RCC_PLL_INTEGER;
     RCC_OscInitStruct.PLL4.RPDFN_DIS = RCC_RPDFN_DIS_DISABLED;
     RCC_OscInitStruct.PLL4.TPDFN_DIS = RCC_TPDFN_DIS_DISABLED;
-    
+
     if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
     {
         Error_Handler();
@@ -119,12 +119,12 @@ void SystemClock_Config(void)
     RCC_ClkInitStruct.APB1_Div = RCC_APB1_DIV2;
     RCC_ClkInitStruct.APB2_Div = RCC_APB2_DIV2;
     RCC_ClkInitStruct.APB3_Div = RCC_APB3_DIV2;
-    
+
     if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK)
     {
         Error_Handler();
     }
-    
+
     /**Set the HSE division factor for RTC clock
     */
     __HAL_RCC_RTC_HSEDIV(24);
@@ -137,7 +137,7 @@ void SystemClock_Config(void)
 */
 void PeriphCommonClock_Config(void) {
     RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
-    
+
     /** Initializes the common periph clock
     */
     PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_CKPER;
@@ -149,11 +149,11 @@ void PeriphCommonClock_Config(void) {
 
 extern void rt_hw_systick_init(void);
 extern int rt_hw_usart_init(void);
-void rt_hw_board_init() 
+void rt_hw_board_init()
 {
     /* HAL_Init() function is called at the beginning of the program */
     HAL_Init();
-    
+
     /* enable interrupt */
     __set_PRIMASK(0);
     /* Configure the system clock */
@@ -163,29 +163,29 @@ void rt_hw_board_init()
     }
     /* disable interrupt */
     __set_PRIMASK(1);
-    
+
     rt_hw_systick_init();
-    
+
     /* Heap initialization */
 #if defined(RT_USING_HEAP)
     rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
 #endif
-     
+
     /* Pin driver initialization is open by default */
 #ifdef RT_USING_PIN
     rt_hw_pin_init();
 #endif
-    
+
     /* USART driver initialization is open by default */
 #ifdef RT_USING_SERIAL
     rt_hw_usart_init();
 #endif
-    
+
     /* Set the shell console output device */
 #ifdef RT_USING_CONSOLE
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
-    
+
     /* Board underlying hardware initialization */
 #ifdef RT_USING_COMPONENTS_INIT
     rt_components_board_init();
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/board.h b/bsp/stm32/stm32mp157a-st-discovery/board/board.h
index 2472d96400..0b60c68af4 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/board.h
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -22,12 +22,12 @@
 extern "C" {
 #endif
 
-#define STM32_FLASH_START_ADRESS     ((uint32_t)0x10000000)  
+#define STM32_FLASH_START_ADRESS     ((uint32_t)0x10000000)
 #define STM32_FLASH_SIZE             (192 * 1024)
 #define STM32_FLASH_END_ADDRESS      ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
-  
+
 #define STM32_SRAM_SIZE           (64)
-#define STM32_SRAM_END            (0x10030000 + 64 * 1024)  	
+#define STM32_SRAM_END            (0x10030000 + 64 * 1024)
 
 #if defined(__CC_ARM) || defined(__CLANG_ARM)
 extern int Image$$RW_IRAM1$$ZI$$Limit;
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/OpenAMP/libmetal/lib/include/metal/system/generic/alloc.h b/bsp/stm32/stm32mp157a-st-discovery/board/ports/OpenAMP/libmetal/lib/include/metal/system/generic/alloc.h
index bcceba61a0..5220e13b97 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/OpenAMP/libmetal/lib/include/metal/system/generic/alloc.h
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/OpenAMP/libmetal/lib/include/metal/system/generic/alloc.h
@@ -18,18 +18,21 @@
 
 #include 
 
+extern void *rt_malloc(unsigned long nbytes);
+extern void rt_free(void *ptr);
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 static inline void *metal_allocate_memory(unsigned int size)
 {
-	return (malloc(size));
+	return (rt_malloc(size));
 }
 
 static inline void metal_free_memory(void *ptr)
 {
-	free(ptr);
+	rt_free(ptr);
 }
 
 #ifdef __cplusplus
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/OpenAMP/libmetal/lib/system/generic/alloc.h b/bsp/stm32/stm32mp157a-st-discovery/board/ports/OpenAMP/libmetal/lib/system/generic/alloc.h
index bcceba61a0..5220e13b97 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/OpenAMP/libmetal/lib/system/generic/alloc.h
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/OpenAMP/libmetal/lib/system/generic/alloc.h
@@ -18,18 +18,21 @@
 
 #include 
 
+extern void *rt_malloc(unsigned long nbytes);
+extern void rt_free(void *ptr);
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 static inline void *metal_allocate_memory(unsigned int size)
 {
-	return (malloc(size));
+	return (rt_malloc(size));
 }
 
 static inline void metal_free_memory(void *ptr)
 {
-	free(ptr);
+	rt_free(ptr);
 }
 
 #ifdef __cplusplus
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/audio_play.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/audio_play.c
index 315f6320d5..2e045b016b 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/audio_play.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/audio_play.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -12,7 +12,7 @@
 #include 
 #include 
 
-#if defined(BSP_USING_AUDIO) && defined(BSP_USING_SDMMC)  
+#if defined(BSP_USING_AUDIO) && defined(BSP_USING_SDMMC)
 #define BUFSZ   1024
 #define SOUND_DEVICE_NAME    "sound0"
 static rt_device_t snd_dev;
@@ -217,7 +217,7 @@ int wavrecord_sample(int argc, char **argv)
     caps.main_type               = AUDIO_TYPE_INPUT;
     caps.sub_type                = AUDIO_DSP_PARAM;
     caps.udata.config.samplerate = RECORD_SAMPLERATE;
-    caps.udata.config.channels   = RECORD_CHANNEL; 
+    caps.udata.config.channels   = RECORD_CHANNEL;
     caps.udata.config.samplebits = 16;
     rt_device_control(mic_dev, AUDIO_CTL_CONFIGURE, &caps);
 
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_cs42l51.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_cs42l51.c
index e0ae5f1b5e..47ac5b0de2 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_cs42l51.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_cs42l51.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,7 +20,7 @@
 /* CS42L51 address */
 #define CHIP_ADDRESS 0x4A
 /* reset pin, active low */
-#define CS42L51_RESET_PIN   GET_PIN(G, 9) 
+#define CS42L51_RESET_PIN   GET_PIN(G, 9)
 
 static uint16_t CS42L51_Device             = OUT_HEADPHONE;
 static struct rt_i2c_bus_device *audio_dev = RT_NULL;
@@ -31,12 +31,12 @@ static rt_err_t read_reg(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8
     struct rt_i2c_msg msg[2] = {0, 0};
 
     RT_ASSERT(bus != RT_NULL);
-    
+
     msg[0].addr  = CHIP_ADDRESS;    /* Slave address */
     msg[0].flags = RT_I2C_WR;        /* Write flag */
     msg[0].buf   = ®             /* Slave register address */
     msg[0].len   = 1;                /* Number of bytes sent */
-        
+
     msg[1].addr  = CHIP_ADDRESS;
     msg[1].flags = RT_I2C_RD;
     msg[1].len   = len;
@@ -57,8 +57,8 @@ static rt_err_t write_reg(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint
     struct rt_i2c_msg msgs;
 
     RT_ASSERT(bus != RT_NULL);
-    
-    buf[0] = reg; 
+
+    buf[0] = reg;
     buf[1] = data;
 
     msgs.addr  = CHIP_ADDRESS;
@@ -119,10 +119,10 @@ static void cs42l51_lowlevel_init(void)
     /* Power off the cs42l51 */
     rt_pin_write(CS42L51_RESET_PIN, PIN_LOW);
 
-    /* wait until power supplies are stable */    
+    /* wait until power supplies are stable */
     rt_thread_mdelay(10);
 
-    /* Power on the cs42l51 */    
+    /* Power on the cs42l51 */
     rt_pin_write(CS42L51_RESET_PIN, PIN_HIGH);
 
     /* Wait at least 500ns after reset */
@@ -150,12 +150,12 @@ static rt_err_t cs42l51_init(uint16_t device, const char *bus_name, uint8_t volu
     static uint8_t init_flag  = 0;
     rt_uint8_t temp = 0;
     rt_uint8_t value = 0;
-    
+
     /* check if codec is already initialized */
     if (init_flag == 0)
     {
         audio_dev = rt_i2c_bus_device_find(bus_name);
-        
+
         if (audio_dev == RT_NULL)
         {
             LOG_E("%s bus not found\n", bus_name);
@@ -172,7 +172,7 @@ static rt_err_t cs42l51_init(uint16_t device, const char *bus_name, uint8_t volu
         write_reg(audio_dev, CS42L51_POWER_CTL1, 0x7F);
         read_reg(audio_dev, CS42L51_MIC_POWER_CTL, 1, &temp);
         write_reg(audio_dev, CS42L51_MIC_POWER_CTL, (temp | 0x0E));
-        
+
         init_flag = 1;
     }
     else
@@ -187,7 +187,7 @@ static rt_err_t cs42l51_init(uint16_t device, const char *bus_name, uint8_t volu
 
         /* Power control : Enter standby (PDN = 1) */
         read_reg(audio_dev, CS42L51_POWER_CTL1, 1, &temp);
-        write_reg(audio_dev, CS42L51_POWER_CTL1, (temp | 0x01)); 
+        write_reg(audio_dev, CS42L51_POWER_CTL1, (temp | 0x01));
     }
     /* Mic Power and Speed Control : Auto detect on, Speed mode SSM, tri state off, MCLK divide by 2 off */
     read_reg(audio_dev, CS42L51_MIC_POWER_CTL, 1, &temp);
@@ -204,9 +204,9 @@ static rt_err_t cs42l51_init(uint16_t device, const char *bus_name, uint8_t volu
     write_reg(audio_dev, CS42L51_DAC_OUT_CTL, 0xC3);
     /* DAC control : Signal processing to DAC, Freeze off, De-emphasis off, Analog output auto mute off, DAC soft ramp */
     write_reg(audio_dev, CS42L51_DAC_CTL, 0x42);
-    /* ALCA and PGAA Control : ALCA soft ramp disable on, ALCA zero cross disable on, PGA A Gain 0dB */  
+    /* ALCA and PGAA Control : ALCA soft ramp disable on, ALCA zero cross disable on, PGA A Gain 0dB */
     write_reg(audio_dev, CS42L51_ALC_PGA_CTL, 0xC0);
-    /* ALCB and PGAB Control : ALCB soft ramp disable on, ALCB zero cross disable on, PGA B Gain 0dB */  
+    /* ALCB and PGAB Control : ALCB soft ramp disable on, ALCB zero cross disable on, PGA B Gain 0dB */
     write_reg(audio_dev, CS42L51_ALC_PGB_CTL, 0xC0);
     /* ADCA Attenuator : 0dB */
     write_reg(audio_dev, CS42L51_ADCA_ATT, 0x00);
@@ -229,12 +229,12 @@ static rt_err_t cs42l51_init(uint16_t device, const char *bus_name, uint8_t volu
         /* AOUTA volume control : AOUTA volume */
         write_reg(audio_dev, CS42L51_AOUTA_VOL, value);
         /* AOUTB volume control : AOUTB volume */
-        write_reg(audio_dev, CS42L51_AOUTB_VOL, value); 
+        write_reg(audio_dev, CS42L51_AOUTB_VOL, value);
     }
-    
+
     CS42L51_Device = device;
-    
-    return RT_EOK;  
+
+    return RT_EOK;
 }
 
 /**
@@ -271,7 +271,7 @@ static void cs42l51_deinit(void)
 }
 
 /**
-  * @brief Verify that we have a CS42L51.   
+  * @brief Verify that we have a CS42L51.
   * @retval 0 if correct communication, else wrong communication
   */
 
@@ -283,20 +283,20 @@ static uint32_t cs42l51_read_id(void)
     read_reg(audio_dev, CS42L51_CHIP_REV_ID, 1, &temp);
 
     if ((temp != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_A)) &&
-        (temp != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_B))) 
+        (temp != CS42L51_MK_CHIP_REV(CS42L51_CHIP_ID, CS42L51_CHIP_REV_B)))
     {
-      LOG_E("device id : 0x%02x", temp);  
-        return RT_ERROR;     
+      LOG_E("device id : 0x%02x", temp);
+        return RT_ERROR;
     }
-    
-    LOG_D("device id : 0x%02x", temp);  
-    
+
+    LOG_D("device id : 0x%02x", temp);
+
     return RT_EOK;
 }
 
 /**
   * @brief Start the audio Codec play feature.
-  * @note For this codec no Play options are required.  
+  * @note For this codec no Play options are required.
   * @retval 0 if correct communication, else wrong communication
   */
 static uint32_t cs42l51_play(void)
@@ -316,7 +316,7 @@ static uint32_t cs42l51_play(void)
         write_reg(audio_dev, CS42L51_POWER_CTL1, (temp & 0x9F));
         break;
         }
-        
+
     case IN_LINE1:
         {
         /* ADC Input Select, Invert and Mute : AIN1B to PGAB, AIN1A to PGAA, ADCB invert off, ADCA invert off, ADCB mute off, ADCA mute off */
@@ -326,7 +326,7 @@ static uint32_t cs42l51_play(void)
         write_reg(audio_dev, CS42L51_POWER_CTL1, (temp & 0x9F));
         break;
         }
-        
+
     case IN_MIC1:
         {
         /* ADC Input Select, Invert and Mute : AIN1B to PGAB, AIN3A to PreAmp to PGAA, ADCB invert off, ADCA invert off, ADCB mute on, ADCA mute off */
@@ -339,7 +339,7 @@ static uint32_t cs42l51_play(void)
         write_reg(audio_dev, CS42L51_MIC_POWER_CTL,(temp & 0xF9));
         break;
         }
-        
+
     case IN_MIC2:
         {
          /* Power control 1 : PDN_PGAB, PDN_ADCB disable. */
@@ -350,7 +350,7 @@ static uint32_t cs42l51_play(void)
          write_reg(audio_dev, CS42L51_MIC_POWER_CTL,(temp & 0xF5));
          break;
         }
-        
+
     default:
         LOG_D("error audio play mode!");
         break;
@@ -365,11 +365,11 @@ static uint32_t cs42l51_play(void)
 
 /**
   * @brief Pause playing on the audio codec.
-  * @param audio_dev: Device address on communication Bus. 
+  * @param audio_dev: Device address on communication Bus.
   * @retval 0 if correct communication, else wrong communication
   */
 static uint32_t cs42l51_pause(void)
-{  
+{
 
   /* Pause the audio file playing */
   /* Mute the output first */
@@ -379,7 +379,7 @@ static uint32_t cs42l51_pause(void)
 
 /**
   * @brief Resume playing on the audio codec.
-  * @param audio_dev: Device address on communication Bus. 
+  * @param audio_dev: Device address on communication Bus.
   * @retval 0 if correct communication, else wrong communication
   */
 static uint32_t cs42l51_resume(void)
@@ -423,7 +423,7 @@ static uint32_t cs42l51_set_frequency(uint32_t AudioFreq)
 }
 
 /**
-  * @brief Set higher or lower the codec volume level.  
+  * @brief Set higher or lower the codec volume level.
   * @param Volume: output volume level (from 0 (-100dB) to 100 (0dB)).
   * @retval 0 if correct communication, else wrong communication
   */
@@ -440,23 +440,23 @@ static uint32_t cs42l51_set_volume(uint8_t Volume)
 }
 
 /**
-  * @brief get higher or lower the codec volume level.  
+  * @brief get higher or lower the codec volume level.
   * @retval value if correct communication
   */
 static uint32_t cs42l51_get_volume(void)
 {
     rt_uint8_t temp = 0;
-    
+
     /* AOUTA volume control : AOUTA volume */
     read_reg(audio_dev, CS42L51_AOUTA_VOL, 1, &temp);
 
     temp = VOLUME_INVERT(temp);
-    
+
     return temp;
 }
 
 /**
-* @brief Enable or disable the mute feature on the audio codec.  
+* @brief Enable or disable the mute feature on the audio codec.
 * @param Cmd: AUDIO_MUTE_ON to enable the mute or AUDIO_MUTE_OFF to disable the
 *             mute mode.
 * @retval 0 if correct communication, else wrong communication
@@ -464,7 +464,7 @@ static uint32_t cs42l51_get_volume(void)
 static uint32_t cs42l51_set_mute(uint32_t cmd)
 {
     rt_uint8_t temp = 0;
-    
+
     /* Read DAC output control register */
     read_reg(audio_dev, 0x08, 1, &temp);
 
@@ -484,10 +484,10 @@ static uint32_t cs42l51_set_mute(uint32_t cmd)
 }
 
 /**
-  * @brief Switch dynamically (while audio file is played) the output target 
+  * @brief Switch dynamically (while audio file is played) the output target
   *         (speaker, headphone, etc).
   * @note This function is currently not used (only headphone output device).
-  * @param Output: specifies the audio output device target. 
+  * @param Output: specifies the audio output device target.
   * @retval 0 if correct communication, else wrong communication
   */
 static uint32_t cs42l51_set_output_mode(uint8_t Output)
@@ -496,7 +496,7 @@ static uint32_t cs42l51_set_output_mode(uint8_t Output)
 }
 
 /**
-  * @brief Reset CS42L51 registers. 
+  * @brief Reset CS42L51 registers.
   * @retval 0 if correct communication, else wrong communication
   */
 static uint32_t cs42l51_reset(void)
@@ -508,8 +508,8 @@ static uint32_t cs42l51_reset(void)
     return RT_EOK;
 }
 
-/* Audio codec driver structure initialization */  
-AUDIO_DrvTypeDef cs42l51_drv = 
+/* Audio codec driver structure initialization */
+AUDIO_DrvTypeDef cs42l51_drv =
 {
   cs42l51_init,
   cs42l51_deinit,
@@ -518,12 +518,12 @@ AUDIO_DrvTypeDef cs42l51_drv =
   cs42l51_play,
   cs42l51_pause,
   cs42l51_resume,
-  cs42l51_stop,  
-  
-  cs42l51_set_frequency,  
+  cs42l51_stop,
+
+  cs42l51_set_frequency,
   cs42l51_set_volume,
   cs42l51_get_volume,
-  cs42l51_set_mute,  
+  cs42l51_set_mute,
   cs42l51_set_output_mode,
   cs42l51_reset,
 };
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_cs42l51.h b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_cs42l51.h
index b3d7f78dca..4447418a24 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_cs42l51.h
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_cs42l51.h
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- * 
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Date           Author       Notes
@@ -13,7 +13,7 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
-    
+
 typedef struct
 {
   rt_err_t  (*init)(uint16_t , const char *, uint8_t);
@@ -34,137 +34,137 @@ typedef struct
 extern AUDIO_DrvTypeDef cs42l51_drv;
 
 /* CS42L51 register space */
-#define CS42L51_CHIP_ID			            0x1B
-#define CS42L51_CHIP_REV_A		            0x00
-#define CS42L51_CHIP_REV_B		            0x01
+#define CS42L51_CHIP_ID                     0x1B
+#define CS42L51_CHIP_REV_A                  0x00
+#define CS42L51_CHIP_REV_B                  0x01
 
-#define CS42L51_CHIP_REV_ID		            0x01
-#define CS42L51_MK_CHIP_REV(a, b)	        ((a)<<3|(b))
+#define CS42L51_CHIP_REV_ID                 0x01
+#define CS42L51_MK_CHIP_REV(a, b)           ((a)<<3|(b))
 
-#define CS42L51_POWER_CTL1		            0x02
-#define CS42L51_POWER_CTL1_PDN_DACB	        (1<<6)
-#define CS42L51_POWER_CTL1_PDN_DACA	        (1<<5)
-#define CS42L51_POWER_CTL1_PDN_PGAB	        (1<<4)
-#define CS42L51_POWER_CTL1_PDN_PGAA	        (1<<3)
-#define CS42L51_POWER_CTL1_PDN_ADCB	        (1<<2)
-#define CS42L51_POWER_CTL1_PDN_ADCA	        (1<<1)
-#define CS42L51_POWER_CTL1_PDN		        (1<<0)
+#define CS42L51_POWER_CTL1                  0x02
+#define CS42L51_POWER_CTL1_PDN_DACB         (1<<6)
+#define CS42L51_POWER_CTL1_PDN_DACA         (1<<5)
+#define CS42L51_POWER_CTL1_PDN_PGAB         (1<<4)
+#define CS42L51_POWER_CTL1_PDN_PGAA         (1<<3)
+#define CS42L51_POWER_CTL1_PDN_ADCB         (1<<2)
+#define CS42L51_POWER_CTL1_PDN_ADCA         (1<<1)
+#define CS42L51_POWER_CTL1_PDN              (1<<0)
 
-#define CS42L51_MIC_POWER_CTL		        0x03
-#define CS42L51_MIC_POWER_CTL_AUTO	        (1<<7)
-#define CS42L51_MIC_POWER_CTL_SPEED(x)	    (((x)&3)<<5)
-#define CS42L51_QSM_MODE		            3
-#define CS42L51_HSM_MODE		            2
-#define	CS42L51_SSM_MODE		            1
-#define CS42L51_DSM_MODE		            0
-#define CS42L51_MIC_POWER_CTL_3ST_SP	    (1<<4)
-#define CS42L51_MIC_POWER_CTL_PDN_MICB	    (1<<3)
-#define CS42L51_MIC_POWER_CTL_PDN_MICA	    (1<<2)
-#define CS42L51_MIC_POWER_CTL_PDN_BIAS	    (1<<1)
-#define CS42L51_MIC_POWER_CTL_MCLK_DIV2	    (1<<0)
+#define CS42L51_MIC_POWER_CTL               0x03
+#define CS42L51_MIC_POWER_CTL_AUTO          (1<<7)
+#define CS42L51_MIC_POWER_CTL_SPEED(x)      (((x)&3)<<5)
+#define CS42L51_QSM_MODE                    3
+#define CS42L51_HSM_MODE                    2
+#define CS42L51_SSM_MODE                    1
+#define CS42L51_DSM_MODE                    0
+#define CS42L51_MIC_POWER_CTL_3ST_SP        (1<<4)
+#define CS42L51_MIC_POWER_CTL_PDN_MICB      (1<<3)
+#define CS42L51_MIC_POWER_CTL_PDN_MICA      (1<<2)
+#define CS42L51_MIC_POWER_CTL_PDN_BIAS      (1<<1)
+#define CS42L51_MIC_POWER_CTL_MCLK_DIV2     (1<<0)
 
-#define CS42L51_INTF_CTL		            0x04
-#define CS42L51_INTF_CTL_LOOPBACK	        (1<<7)
-#define CS42L51_INTF_CTL_MASTER		        (1<<6)
-#define CS42L51_INTF_CTL_DAC_FORMAT(x)	    (((x)&7)<<3)
-#define CS42L51_DAC_DIF_LJ24		        0x00
-#define CS42L51_DAC_DIF_I2S		            0x01
-#define CS42L51_DAC_DIF_RJ24		        0x02
-#define CS42L51_DAC_DIF_RJ20		        0x03
-#define CS42L51_DAC_DIF_RJ18		        0x04
-#define CS42L51_DAC_DIF_RJ16		        0x05
-#define CS42L51_INTF_CTL_ADC_I2S	        (1<<2)
-#define CS42L51_INTF_CTL_DIGMIX		        (1<<1)
-#define CS42L51_INTF_CTL_MICMIX		        (1<<0)
+#define CS42L51_INTF_CTL                    0x04
+#define CS42L51_INTF_CTL_LOOPBACK           (1<<7)
+#define CS42L51_INTF_CTL_MASTER             (1<<6)
+#define CS42L51_INTF_CTL_DAC_FORMAT(x)      (((x)&7)<<3)
+#define CS42L51_DAC_DIF_LJ24                0x00
+#define CS42L51_DAC_DIF_I2S                 0x01
+#define CS42L51_DAC_DIF_RJ24                0x02
+#define CS42L51_DAC_DIF_RJ20                0x03
+#define CS42L51_DAC_DIF_RJ18                0x04
+#define CS42L51_DAC_DIF_RJ16                0x05
+#define CS42L51_INTF_CTL_ADC_I2S            (1<<2)
+#define CS42L51_INTF_CTL_DIGMIX             (1<<1)
+#define CS42L51_INTF_CTL_MICMIX             (1<<0)
 
-#define CS42L51_MIC_CTL			            0x05
-#define CS42L51_MIC_CTL_ADC_SNGVOL	        (1<<7)
-#define CS42L51_MIC_CTL_ADCD_DBOOST	        (1<<6)
-#define CS42L51_MIC_CTL_ADCA_DBOOST	        (1<<5)
-#define CS42L51_MIC_CTL_MICBIAS_SEL	        (1<<4)
-#define CS42L51_MIC_CTL_MICBIAS_LVL(x)	    (((x)&3)<<2)
-#define CS42L51_MIC_CTL_MICB_BOOST	        (1<<1)
-#define CS42L51_MIC_CTL_MICA_BOOST	        (1<<0)
+#define CS42L51_MIC_CTL                     0x05
+#define CS42L51_MIC_CTL_ADC_SNGVOL          (1<<7)
+#define CS42L51_MIC_CTL_ADCD_DBOOST         (1<<6)
+#define CS42L51_MIC_CTL_ADCA_DBOOST         (1<<5)
+#define CS42L51_MIC_CTL_MICBIAS_SEL         (1<<4)
+#define CS42L51_MIC_CTL_MICBIAS_LVL(x)      (((x)&3)<<2)
+#define CS42L51_MIC_CTL_MICB_BOOST          (1<<1)
+#define CS42L51_MIC_CTL_MICA_BOOST          (1<<0)
 
-#define CS42L51_ADC_CTL			            0x06
-#define CS42L51_ADC_CTL_ADCB_HPFEN	        (1<<7)
-#define CS42L51_ADC_CTL_ADCB_HPFRZ	        (1<<6)
-#define CS42L51_ADC_CTL_ADCA_HPFEN	        (1<<5)
-#define CS42L51_ADC_CTL_ADCA_HPFRZ	        (1<<4)
-#define CS42L51_ADC_CTL_SOFTB		        (1<<3)
-#define CS42L51_ADC_CTL_ZCROSSB		        (1<<2)
-#define CS42L51_ADC_CTL_SOFTA		        (1<<1)
-#define CS42L51_ADC_CTL_ZCROSSA		        (1<<0)
+#define CS42L51_ADC_CTL                     0x06
+#define CS42L51_ADC_CTL_ADCB_HPFEN          (1<<7)
+#define CS42L51_ADC_CTL_ADCB_HPFRZ          (1<<6)
+#define CS42L51_ADC_CTL_ADCA_HPFEN          (1<<5)
+#define CS42L51_ADC_CTL_ADCA_HPFRZ          (1<<4)
+#define CS42L51_ADC_CTL_SOFTB               (1<<3)
+#define CS42L51_ADC_CTL_ZCROSSB             (1<<2)
+#define CS42L51_ADC_CTL_SOFTA               (1<<1)
+#define CS42L51_ADC_CTL_ZCROSSA             (1<<0)
 
-#define CS42L51_ADC_INPUT		            0x07
-#define CS42L51_ADC_INPUT_AINB_MUX(x)	    (((x)&3)<<6)
-#define CS42L51_ADC_INPUT_AINA_MUX(x)	    (((x)&3)<<4)
-#define CS42L51_ADC_INPUT_INV_ADCB	        (1<<3)
-#define CS42L51_ADC_INPUT_INV_ADCA	        (1<<2)
-#define CS42L51_ADC_INPUT_ADCB_MUTE	        (1<<1)
-#define CS42L51_ADC_INPUT_ADCA_MUTE	        (1<<0)
+#define CS42L51_ADC_INPUT                   0x07
+#define CS42L51_ADC_INPUT_AINB_MUX(x)       (((x)&3)<<6)
+#define CS42L51_ADC_INPUT_AINA_MUX(x)       (((x)&3)<<4)
+#define CS42L51_ADC_INPUT_INV_ADCB          (1<<3)
+#define CS42L51_ADC_INPUT_INV_ADCA          (1<<2)
+#define CS42L51_ADC_INPUT_ADCB_MUTE         (1<<1)
+#define CS42L51_ADC_INPUT_ADCA_MUTE         (1<<0)
 
-#define CS42L51_DAC_OUT_CTL		            0x08
-#define CS42L51_DAC_OUT_CTL_HP_GAIN(x)	    (((x)&7)<<5)
-#define CS42L51_DAC_OUT_CTL_DAC_SNGVOL	    (1<<4)
-#define CS42L51_DAC_OUT_CTL_INV_PCMB	    (1<<3)
-#define CS42L51_DAC_OUT_CTL_INV_PCMA	    (1<<2)
-#define CS42L51_DAC_OUT_CTL_DACB_MUTE	    (1<<1)
-#define CS42L51_DAC_OUT_CTL_DACA_MUTE	    (1<<0)
+#define CS42L51_DAC_OUT_CTL                 0x08
+#define CS42L51_DAC_OUT_CTL_HP_GAIN(x)      (((x)&7)<<5)
+#define CS42L51_DAC_OUT_CTL_DAC_SNGVOL      (1<<4)
+#define CS42L51_DAC_OUT_CTL_INV_PCMB        (1<<3)
+#define CS42L51_DAC_OUT_CTL_INV_PCMA        (1<<2)
+#define CS42L51_DAC_OUT_CTL_DACB_MUTE       (1<<1)
+#define CS42L51_DAC_OUT_CTL_DACA_MUTE       (1<<0)
 
-#define CS42L51_DAC_CTL			            0x09
-#define CS42L51_DAC_CTL_DATA_SEL(x)	        (((x)&3)<<6)
-#define CS42L51_DAC_CTL_FREEZE		        (1<<5)
-#define CS42L51_DAC_CTL_DEEMPH		        (1<<3)
-#define CS42L51_DAC_CTL_AMUTE		        (1<<2)
-#define CS42L51_DAC_CTL_DACSZ(x)	        (((x)&3)<<0)
+#define CS42L51_DAC_CTL                     0x09
+#define CS42L51_DAC_CTL_DATA_SEL(x)         (((x)&3)<<6)
+#define CS42L51_DAC_CTL_FREEZE              (1<<5)
+#define CS42L51_DAC_CTL_DEEMPH              (1<<3)
+#define CS42L51_DAC_CTL_AMUTE               (1<<2)
+#define CS42L51_DAC_CTL_DACSZ(x)            (((x)&3)<<0)
 
-#define CS42L51_ALC_PGA_CTL		            0x0A
-#define CS42L51_ALC_PGB_CTL		            0x0B
-#define CS42L51_ALC_PGX_ALCX_SRDIS	        (1<<7)
-#define CS42L51_ALC_PGX_ALCX_ZCDIS	        (1<<6)
-#define CS42L51_ALC_PGX_PGX_VOL(x)	        (((x)&0x1f)<<0)
+#define CS42L51_ALC_PGA_CTL                 0x0A
+#define CS42L51_ALC_PGB_CTL                 0x0B
+#define CS42L51_ALC_PGX_ALCX_SRDIS          (1<<7)
+#define CS42L51_ALC_PGX_ALCX_ZCDIS          (1<<6)
+#define CS42L51_ALC_PGX_PGX_VOL(x)          (((x)&0x1f)<<0)
 
-#define CS42L51_ADCA_ATT		            0x0C
-#define CS42L51_ADCB_ATT		            0x0D
+#define CS42L51_ADCA_ATT                    0x0C
+#define CS42L51_ADCB_ATT                    0x0D
 
-#define CS42L51_ADCA_VOL		            0x0E
-#define CS42L51_ADCB_VOL		            0x0F
-#define CS42L51_PCMA_VOL		            0x10
-#define CS42L51_PCMB_VOL		            0x11
-#define CS42L51_MIX_MUTE_ADCMIX		        (1<<7)
-#define CS42L51_MIX_VOLUME(x)		        (((x)&0x7f)<<0)
+#define CS42L51_ADCA_VOL                    0x0E
+#define CS42L51_ADCB_VOL                    0x0F
+#define CS42L51_PCMA_VOL                    0x10
+#define CS42L51_PCMB_VOL                    0x11
+#define CS42L51_MIX_MUTE_ADCMIX             (1<<7)
+#define CS42L51_MIX_VOLUME(x)               (((x)&0x7f)<<0)
 
-#define CS42L51_BEEP_FREQ		            0x12
-#define CS42L51_BEEP_VOL		            0x13
-#define CS42L51_BEEP_CONF		            0x14
+#define CS42L51_BEEP_FREQ                   0x12
+#define CS42L51_BEEP_VOL                    0x13
+#define CS42L51_BEEP_CONF                   0x14
 
-#define CS42L51_TONE_CTL		            0x15
-#define CS42L51_TONE_CTL_TREB(x)	        (((x)&0xf)<<4)
-#define CS42L51_TONE_CTL_BASS(x)	        (((x)&0xf)<<0)
+#define CS42L51_TONE_CTL                    0x15
+#define CS42L51_TONE_CTL_TREB(x)            (((x)&0xf)<<4)
+#define CS42L51_TONE_CTL_BASS(x)            (((x)&0xf)<<0)
 
-#define CS42L51_AOUTA_VOL		            0x16
-#define CS42L51_AOUTB_VOL		            0x17
-#define CS42L51_PCM_MIXER		            0x18
-#define CS42L51_LIMIT_THRES_DIS		        0x19
-#define CS42L51_LIMIT_REL		            0x1A
-#define CS42L51_LIMIT_ATT		            0x1B
-#define CS42L51_ALC_EN			            0x1C
-#define CS42L51_ALC_REL			            0x1D
-#define CS42L51_ALC_THRES		            0x1E
-#define CS42L51_NOISE_CONF		            0x1F
+#define CS42L51_AOUTA_VOL                   0x16
+#define CS42L51_AOUTB_VOL                   0x17
+#define CS42L51_PCM_MIXER                   0x18
+#define CS42L51_LIMIT_THRES_DIS             0x19
+#define CS42L51_LIMIT_REL                   0x1A
+#define CS42L51_LIMIT_ATT                   0x1B
+#define CS42L51_ALC_EN                      0x1C
+#define CS42L51_ALC_REL                     0x1D
+#define CS42L51_ALC_THRES                   0x1E
+#define CS42L51_NOISE_CONF                  0x1F
 
-#define CS42L51_STATUS			            0x20
-#define CS42L51_STATUS_SP_CLKERR	        (1<<6)
-#define CS42L51_STATUS_SPEA_OVFL	        (1<<5)
-#define CS42L51_STATUS_SPEB_OVFL	        (1<<4)
-#define CS42L51_STATUS_PCMA_OVFL	        (1<<3)
-#define CS42L51_STATUS_PCMB_OVFL	        (1<<2)
-#define CS42L51_STATUS_ADCA_OVFL	        (1<<1)
-#define CS42L51_STATUS_ADCB_OVFL	        (1<<0)
+#define CS42L51_STATUS                      0x20
+#define CS42L51_STATUS_SP_CLKERR            (1<<6)
+#define CS42L51_STATUS_SPEA_OVFL            (1<<5)
+#define CS42L51_STATUS_SPEB_OVFL            (1<<4)
+#define CS42L51_STATUS_PCMA_OVFL            (1<<3)
+#define CS42L51_STATUS_PCMB_OVFL            (1<<2)
+#define CS42L51_STATUS_ADCA_OVFL            (1<<1)
+#define CS42L51_STATUS_ADCB_OVFL            (1<<0)
 
-#define CS42L51_CHARGE_FREQ		            0x21
-#define CS42L51_FIRSTREG	                0x01
+#define CS42L51_CHARGE_FREQ                 0x21
+#define CS42L51_FIRSTREG                    0x01
 
 enum play_type {
     NONE,
@@ -181,12 +181,12 @@ enum play_type {
  * i2c layer doesn't like i2c smbus block read of 33 regs. Workaround by using
  * 32 regs
  */
-#define CS42L51_LASTREG		                0x20
-#define CS42L51_NUMREGS		                (CS42L51_LASTREG - CS42L51_FIRSTREG + 1)
+#define CS42L51_LASTREG                     0x20
+#define CS42L51_NUMREGS                     (CS42L51_LASTREG - CS42L51_FIRSTREG + 1)
 
 #define VOLUME_CONVERT(Volume)              ((Volume >= 100) ? 0 : ((uint8_t)(((Volume * 2) + 56))))
 #define VOLUME_INVERT(Volume)               (((Volume) == 0U) ? 100U : ((uint8_t)(((Volume) - 56U) / 2U)))
-     
+
 /* MUTE commands */
 #define AUDIO_MUTE_ON                       1
 #define AUDIO_MUTE_OFF                      0
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_mic.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_mic.c
index 20e98d4826..45b0afe762 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_mic.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_mic.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -79,21 +79,21 @@ void SAIB_Init(void)
     hsai_BlockB2.FrameInit.FSDefinition      = SAI_FS_CHANNEL_IDENTIFICATION;
     hsai_BlockB2.FrameInit.FSPolarity        = SAI_FS_ACTIVE_LOW;
     hsai_BlockB2.FrameInit.FSOffset          = SAI_FS_BEFOREFIRSTBIT;
-    
+
     hsai_BlockB2.SlotInit.FirstBitOffset     = 0;
     hsai_BlockB2.SlotInit.SlotSize           = SAI_SLOTSIZE_32B;
     hsai_BlockB2.SlotInit.SlotNumber         = 2;
     hsai_BlockB2.SlotInit.SlotActive         = SAI_SLOTACTIVE_0|SAI_SLOTACTIVE_1;
-    
+
     /* DeInit SAI PDM input */
     HAL_SAI_DeInit(&hsai_BlockB2);
-    
+
     /* Init SAI PDM input */
     if(HAL_OK != HAL_SAI_Init(&hsai_BlockB2))
     {
         Error_Handler();
     }
-    
+
     /* Enable SAI to generate clock used by audio driver */
     __HAL_SAI_ENABLE(&hsai_BlockB2);
 }
@@ -299,7 +299,7 @@ static rt_err_t mic_init(struct rt_audio_device *audio)
 {
     struct mic_device *mic_dev;
     RT_ASSERT(audio != RT_NULL);
-    
+
     mic_dev = (struct mic_device *)audio->parent.user_data;
     SAIB_Init();
     /* set default params */
@@ -312,7 +312,7 @@ static rt_err_t mic_start(struct rt_audio_device *audio, int stream)
 {
     struct mic_device *mic_dev;
     RT_ASSERT(audio != RT_NULL);
-    
+
     mic_dev = (struct mic_device *)audio->parent.user_data;
     if (stream == AUDIO_STREAM_RECORD)
     {
@@ -324,7 +324,7 @@ static rt_err_t mic_start(struct rt_audio_device *audio, int stream)
         }
         /* supply clk */
         HAL_SAI_Transmit(&hsai_BlockA2, (uint8_t *)&zero_frame[0], 2, 0);
-        
+
         cs42l51_drv.play();
     }
 
@@ -358,7 +358,7 @@ int rt_hw_mic_init(void)
 {
     rt_err_t result = RT_EOK;
     struct rt_device *device;
-    
+
     rt_memset(MIC_RX_FIFO, 0, RX_FIFO_SIZE);
     mic_dev.rx_fifo = MIC_RX_FIFO;
 
@@ -373,15 +373,15 @@ int rt_hw_mic_init(void)
     /* register sound device */
     mic_dev.audio.ops = &mic_ops;
     result = rt_audio_register(&mic_dev.audio, "mic0", RT_DEVICE_FLAG_RDONLY, &mic_dev);
-    
+
     if (result != RT_EOK)
     {
-        device = &(mic_dev.audio.parent); 
+        device = &(mic_dev.audio.parent);
         rt_device_unregister(device);
         LOG_E("mic device init error!");
         return RT_ERROR;
     }
-    
+
     return RT_EOK;
 }
 
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_sound.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_sound.c
index 5d94bfc399..6a057fa72f 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_sound.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/audio/drv_sound.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -57,7 +57,7 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai)
         /* Peripheral clock enable */
         if(IS_ENGINEERING_BOOT_MODE())
         {
-            /** Initializes the peripherals clock 
+            /** Initializes the peripherals clock
             */
             PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SAI2;
             PeriphClkInit.Sai2ClockSelection = RCC_SAI2CLKSOURCE_PLL3_Q;
@@ -72,7 +72,7 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai)
         __HAL_RCC_GPIOF_CLK_ENABLE();
         __HAL_RCC_SAI2_CLK_ENABLE();
 
-        /**SAI2_A_Block_A GPIO Configuration    
+        /**SAI2_A_Block_A GPIO Configuration
         PE0     ------> SAI2_MCLK_A
         PI7     ------> SAI2_FS_A
         PI5     ------> SAI2_SCK_A
@@ -106,7 +106,7 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai)
         hdma_sai2_a.Init.Mode                = DMA_CIRCULAR;
         hdma_sai2_a.Init.Priority            = DMA_PRIORITY_HIGH;
         hdma_sai2_a.Init.FIFOMode            = DMA_FIFOMODE_DISABLE;
-        
+
         HAL_DMA_DeInit(&hdma_sai2_a);
         if (HAL_DMA_Init(&hdma_sai2_a) != HAL_OK)
         {
@@ -117,13 +117,13 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai)
         HAL_NVIC_SetPriority(DMA2_Stream5_IRQn, 2, 0);
         HAL_NVIC_EnableIRQ(DMA2_Stream5_IRQn);
     }
-    
+
     if(hsai->Instance==SAI2_Block_B)
     {
           /* Peripheral clock enable */
         if(IS_ENGINEERING_BOOT_MODE())
         {
-            /** Initializes the peripherals clock 
+            /** Initializes the peripherals clock
             */
             PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SAI2;
             PeriphClkInit.Sai2ClockSelection = RCC_SAI2CLKSOURCE_PLL3_Q;
@@ -135,9 +135,9 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai)
         }
         __HAL_RCC_GPIOF_CLK_ENABLE();
         __HAL_RCC_SAI2_CLK_ENABLE();
-                
-        /**SAI2_B_Block_B GPIO Configuration    
-        PF11     ------> SAI2_SD_B 
+
+        /**SAI2_B_Block_B GPIO Configuration
+        PF11     ------> SAI2_SD_B
         */
         GPIO_InitStruct.Pin = GPIO_PIN_11;
         GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
@@ -148,7 +148,7 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai)
 
         __HAL_RCC_DMAMUX_CLK_ENABLE();
         __HAL_RCC_DMA2_CLK_ENABLE();
-        
+
         /* Peripheral DMA init*/
         hdma_sai2_b.Instance                 = DMA2_Stream4;
         hdma_sai2_b.Init.Request             = DMA_REQUEST_SAI2_B;
@@ -163,7 +163,7 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai)
         hdma_sai2_b.Init.FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL;
         hdma_sai2_b.Init.MemBurst            = DMA_MBURST_SINGLE;
         hdma_sai2_b.Init.PeriphBurst         = DMA_PBURST_SINGLE;
-		__HAL_LINKDMA(hsai,hdmarx,hdma_sai2_b);
+        __HAL_LINKDMA(hsai,hdmarx,hdma_sai2_b);
         HAL_DMA_DeInit(&hdma_sai2_b);
         if (HAL_DMA_Init(&hdma_sai2_b) != HAL_OK)
         {
@@ -172,7 +172,7 @@ void HAL_SAI_MspInit(SAI_HandleTypeDef* hsai)
         __HAL_LINKDMA(hsai,hdmarx,hdma_sai2_b);
         __HAL_DMA_ENABLE(&hdma_sai2_b);
         HAL_NVIC_SetPriority(DMA2_Stream4_IRQn, 2, 0);
-        HAL_NVIC_EnableIRQ(DMA2_Stream4_IRQn); 
+        HAL_NVIC_EnableIRQ(DMA2_Stream4_IRQn);
     }
 }
 
@@ -182,14 +182,14 @@ void HAL_SAI_MspDeInit(SAI_HandleTypeDef* hsai)
     if(hsai->Instance==SAI2_Block_A)
     {
 
-        /* Peripheral clock disable */ 
+        /* Peripheral clock disable */
         __HAL_RCC_SAI2_CLK_DISABLE();
 
-        /**SAI2_A_Block_A GPIO Configuration    
+        /**SAI2_A_Block_A GPIO Configuration
         PE0     ------> SAI2_MCLK_A
         PI7     ------> SAI2_FS_A
         PI5     ------> SAI2_SCK_A
-        PI6     ------> SAI2_SD_A 
+        PI6     ------> SAI2_SD_A
         */
         HAL_GPIO_DeInit(GPIOE, GPIO_PIN_0);
 
@@ -198,14 +198,14 @@ void HAL_SAI_MspDeInit(SAI_HandleTypeDef* hsai)
         HAL_DMA_DeInit(hsai->hdmarx);
         HAL_DMA_DeInit(hsai->hdmatx);
     }
-    
+
     if(hsai->Instance==SAI2_Block_B)
     {
         /* Peripheral clock disable */
         __HAL_RCC_SAI2_CLK_DISABLE();
 
-        /**SAI2_B_Block_B GPIO Configuration    
-        PF11     ------> SAI2_SD_B 
+        /**SAI2_B_Block_B GPIO Configuration
+        PF11     ------> SAI2_SD_B
         */
         HAL_GPIO_DeInit(GPIOF, GPIO_PIN_11);
 
@@ -241,12 +241,12 @@ static void rt_hw_sai2a_init(void)
     hsai_BlockA2.FrameInit.FSDefinition      = SAI_FS_CHANNEL_IDENTIFICATION;
     hsai_BlockA2.FrameInit.FSPolarity        = SAI_FS_ACTIVE_LOW;
     hsai_BlockA2.FrameInit.FSOffset          = SAI_FS_BEFOREFIRSTBIT;
-    
+
     hsai_BlockA2.SlotInit.FirstBitOffset     = 0;
     hsai_BlockA2.SlotInit.SlotSize           = SAI_SLOTSIZE_32B;
     hsai_BlockA2.SlotInit.SlotNumber         = 2;
     hsai_BlockA2.SlotInit.SlotActive         = SAI_SLOTACTIVE_0 | SAI_SLOTACTIVE_1;
-    
+
     if(HAL_OK != HAL_SAI_Init(&hsai_BlockA2))
     {
         Error_Handler();
@@ -383,7 +383,7 @@ static rt_err_t sound_getcaps(struct rt_audio_device *audio, struct rt_audio_cap
 
     return result;
 }
-    
+
 static rt_err_t sound_configure(struct rt_audio_device *audio, struct rt_audio_caps *caps)
 {
     rt_err_t result = RT_EOK;
@@ -403,9 +403,9 @@ static rt_err_t sound_configure(struct rt_audio_device *audio, struct rt_audio_c
             rt_uint8_t volume = caps->udata.value;
 
             cs42l51_drv.set_volume(volume);
-            
+
             snd_dev->volume = volume;
-            
+
             LOG_D("set volume %d", volume);
             break;
         }
@@ -483,16 +483,16 @@ static rt_err_t sound_init(struct rt_audio_device *audio)
     RT_ASSERT(audio != RT_NULL);
     snd_dev = (struct sound_device *)audio->parent.user_data;
 
-    cs42l51_drv.init(OUT_HEADPHONE, SOUND_BUS_NAME, 40); 
-    
+    cs42l51_drv.init(OUT_HEADPHONE, SOUND_BUS_NAME, 40);
+
     if (cs42l51_drv.read_id() != RT_EOK)
     {
         LOG_E("can't find low level audio device!");
         return RT_ERROR;
     }
-    
+
     rt_hw_sai2a_init();
-    
+
     /* set default params */
     SAIA_Frequency_Set(snd_dev->replay_config.samplerate);
     SAIA_Channels_Set(snd_dev->replay_config.channels);
@@ -510,10 +510,10 @@ static rt_err_t sound_start(struct rt_audio_device *audio, int stream)
     if (stream == AUDIO_STREAM_REPLAY)
     {
         LOG_D("open sound device");
-        
+
         cs42l51_drv.init(OUT_HEADPHONE, SOUND_BUS_NAME, 60); /* set work mode */
         cs42l51_drv.play();
-        
+
         if (HAL_SAI_Transmit_DMA(&hsai_BlockA2, snd_dev->tx_fifo, TX_FIFO_SIZE / 2) != HAL_OK)
         {
             return RT_ERROR;
@@ -589,12 +589,12 @@ int rt_hw_sound_init(void)
     result = rt_audio_register(&snd_dev.audio, "sound0", RT_DEVICE_FLAG_WRONLY, &snd_dev);
     if (result != RT_EOK)
     {
-        device = &(snd_dev.audio.parent); 
+        device = &(snd_dev.audio.parent);
         rt_device_unregister(device);
         LOG_E("sound device init error!");
         return RT_ERROR;
     }
-    
+
     return RT_EOK;
 }
 
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/crypto/crypto_sample.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/crypto/crypto_sample.c
index e3eb609559..439e6352cc 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/crypto/crypto_sample.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/crypto/crypto_sample.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -77,7 +77,7 @@ static void hw_crc_sample(uint8_t *temp, int size)
 {
     struct rt_hwcrypto_ctx *ctx;
     rt_uint32_t result = 0;
-    
+
     struct hwcrypto_crc_cfg cfg =
     {
         .last_val = 0xFFFFFFFF,
@@ -92,9 +92,9 @@ static void hw_crc_sample(uint8_t *temp, int size)
 
     result = rt_hwcrypto_crc_update(ctx, temp, size);
 
-    rt_kprintf("crc result: %x \n", result);                
+    rt_kprintf("crc result: %x \n", result);
 
-    rt_hwcrypto_crc_destroy(ctx);  
+    rt_hwcrypto_crc_destroy(ctx);
 }
 #endif
 
@@ -103,19 +103,19 @@ static void hw_hash_sample()
 {
     struct rt_hwcrypto_ctx *ctx = RT_NULL;
     const uint8_t hash_input[] = "RT-Thread was born in 2006, it is an open source, neutral, and community-based real-time operating system (RTOS).";
-    
+
     static uint8_t sha1_output[20];
-    static uint8_t sha1_except[20] = {0xff, 0x3c, 0x95, 0x54, 0x95, 0xf0, 0xad, 
+    static uint8_t sha1_except[20] = {0xff, 0x3c, 0x95, 0x54, 0x95, 0xf0, 0xad,
                                     0x02, 0x1b, 0xa8, 0xbc, 0xa2, 0x2e, 0xa5,
                                     0xb0, 0x62, 0x1b, 0xdf, 0x7f, 0xec};
-    
+
     static uint8_t md5_output[16];
-    static uint8_t md5_except[16] = {0x40, 0x86, 0x03, 0x80, 0x0d, 0x8c, 0xb9, 
+    static uint8_t md5_except[16] = {0x40, 0x86, 0x03, 0x80, 0x0d, 0x8c, 0xb9,
                                    0x4c, 0xd6, 0x7d, 0x28, 0xfc, 0xf6, 0xc3,
                                    0xac, 0x8b};
-    
+
     static uint8_t sha224_output[28];
-    static uint8_t sha224_except[28] = {0x6f, 0x62, 0x52, 0x7d, 0x80, 0xe6, 
+    static uint8_t sha224_except[28] = {0x6f, 0x62, 0x52, 0x7d, 0x80, 0xe6,
                                         0x9f, 0x82, 0x78, 0x7a, 0x46, 0x91,
                                         0xb0, 0xe9, 0x64, 0x89, 0xe6, 0xc3,
                                         0x6b, 0x7e, 0xcf, 0xca, 0x11, 0x42,
@@ -130,7 +130,7 @@ static void hw_hash_sample()
     rt_kprintf("======================== Hash Test start ========================\n");
     rt_kprintf("Hash Test string: \n");
     dump_hex(hash_input, sizeof(hash_input));
-    
+
     /* sh1 test*/
     rt_kprintf("\n============ SHA1 Test Start ============\n");
     ctx = rt_hwcrypto_hash_create(rt_hwcrypto_dev_default(), HWCRYPTO_TYPE_SHA1);
@@ -147,7 +147,7 @@ static void hw_hash_sample()
     rt_hwcrypto_hash_update(ctx, hash_input, rt_strlen((char const *)hash_input));
     /* get sha1 result */
     rt_hwcrypto_hash_finish(ctx, sha1_output, rt_strlen((char const *)sha1_output));
-    
+
     rt_kprintf("Actual sha1 result:\n");
     dump_hex(sha1_output, sizeof(sha1_output));
 
@@ -162,7 +162,7 @@ static void hw_hash_sample()
     /* deinit hash*/
     rt_hwcrypto_hash_destroy(ctx);
     rt_kprintf("============ SHA1 Test Over ============\n");
-      
+
     /* md5 test*/
     rt_kprintf("\n============ MD5 Test Start ============\n");
     ctx = rt_hwcrypto_hash_create(rt_hwcrypto_dev_default(), HWCRYPTO_TYPE_MD5);
@@ -179,7 +179,7 @@ static void hw_hash_sample()
     rt_hwcrypto_hash_update(ctx, hash_input, rt_strlen((char const *)hash_input));
     /* get md5 result */
     rt_hwcrypto_hash_finish(ctx, md5_output, rt_strlen((char const *)md5_output));
-    
+
     rt_kprintf("Actual md5 result:\n");
     dump_hex(md5_output, sizeof(md5_output));
 
@@ -194,7 +194,7 @@ static void hw_hash_sample()
     /* deinit hash*/
     rt_hwcrypto_hash_destroy(ctx);
     rt_kprintf("============ MD5 Test Over ============\n");
-    
+
     /* sha224 test */
     rt_kprintf("\n============ SHA224 Test Start ============\n");
     ctx = rt_hwcrypto_hash_create(rt_hwcrypto_dev_default(), HWCRYPTO_TYPE_SHA224);
@@ -211,7 +211,7 @@ static void hw_hash_sample()
     rt_hwcrypto_hash_update(ctx, hash_input, rt_strlen((char const *)hash_input));
     /* get sha224 result */
     rt_hwcrypto_hash_finish(ctx, sha224_output, rt_strlen((char const *)sha224_output));
-    
+
     rt_kprintf("Actual sha224 result:\n");
     dump_hex(sha224_output, sizeof(sha224_output));
 
@@ -234,7 +234,7 @@ static void hw_hash_sample()
         rt_kprintf("create hash[%08x] context err!\n", HWCRYPTO_TYPE_SHA256);
         return ;
     }
-    
+
     rt_kprintf("Create sha256 type success!\n");
     rt_kprintf("Except sha256 result:\n");
     dump_hex(sha256_except, sizeof(sha256_except));
@@ -246,7 +246,7 @@ static void hw_hash_sample()
 
     rt_kprintf("Actual sha256 result\n");
     dump_hex(sha256_output, sizeof(sha256_output));
-    
+
     if(rt_memcmp(sha256_output, sha256_except, sizeof(sha256_except)/sizeof(sha256_except[0])) != 0)
     {
         rt_kprintf("Hash type sha256 Test error, The actual result is not equal to the except result\n");
@@ -258,7 +258,7 @@ static void hw_hash_sample()
     /* destory */
     rt_hwcrypto_hash_destroy(ctx);
     rt_kprintf("============ SHA256 Test Over ============\n");
-    rt_kprintf("======================== Hash Test over! ========================\n");    
+    rt_kprintf("======================== Hash Test over! ========================\n");
 }
 #endif
 
@@ -286,29 +286,29 @@ static void hw_cryp_sample()
     rt_uint8_t buf_in[32];
     rt_uint8_t buf_out[32];
     int i;
-    
+
     /* Populating test data */
     for (i = 0; i < sizeof(buf_in); i++)
     {
         buf_in[i] = i;
     }
-    
+
     /* dump primitive data */
     rt_kprintf("key : \n");
     dump_hex(cryp_key, sizeof(cryp_key));
     rt_kprintf("primitive data : \n");
     dump_hex(buf_in, sizeof(buf_in));
-    
+
     rt_memset(buf_out, 0, sizeof(buf_out));
-    
+
     /* encrypt */
     hw_aes_cbc(buf_in, buf_out, HWCRYPTO_MODE_ENCRYPT);
     /* dump encrypt data */
     rt_kprintf("AES-enc : \n");
     dump_hex(buf_out, sizeof(buf_out));
-  
+
     rt_memset(buf_in, 0, sizeof(buf_in));
-    
+
     /* decrypt */
     hw_aes_cbc(buf_out, buf_in, HWCRYPTO_MODE_DECRYPT);
 
@@ -323,7 +323,7 @@ static int crypto(int argc, char **argv)
     int result = RT_EOK;
     static rt_device_t device = RT_NULL;
     char *result_str;
-    
+
     if (argc > 1)
     {
         if (!strcmp(argv[1], "probe"))
@@ -362,7 +362,7 @@ static int crypto(int argc, char **argv)
                 {
                     rt_kprintf("rng         - generate  digital\n");
                 }
-                
+
 #else
                 rt_kprintf("please enable RNG first!\n");
 #endif
@@ -370,7 +370,7 @@ static int crypto(int argc, char **argv)
             else if (!strcmp(argv[1], "crc"))
             {
 #if defined (BSP_USING_CRC)
-                int size = 0, i = 0; 
+                int size = 0, i = 0;
                 if (argc > 3)
                 {
                     size = argc - 2;
@@ -381,7 +381,7 @@ static int crypto(int argc, char **argv)
                         {
                             data[i] = strtol(argv[2 + i], NULL, 0);
                         }
-                        hw_crc_sample(data, size);  
+                        hw_crc_sample(data, size);
                         rt_free(data);
                     }
                     else
@@ -402,31 +402,31 @@ static int crypto(int argc, char **argv)
 #if defined (BSP_USING_HASH)
                 if (argc == 3)
                 {
-                    hw_hash_sample(); 
+                    hw_hash_sample();
                 }
                 else
                 {
-                    rt_kprintf("crypto hash sample          - hash use sample\n");    
+                    rt_kprintf("crypto hash sample          - hash use sample\n");
                 }
 #else
-         rt_kprintf("please enable CRC first!\n");       
-#endif    
+         rt_kprintf("please enable CRC first!\n");
+#endif
             }
             else if (!strcmp(argv[1], "cryp"))
             {
 #if defined (BSP_USING_CRYP)
                 if (argc == 3)
                 {
-                    hw_cryp_sample(); 
+                    hw_cryp_sample();
                 }
                 else
                 {
-                    rt_kprintf("crypto cryp sample          - encrypt and decrypt data sample\n");    
+                    rt_kprintf("crypto cryp sample          - encrypt and decrypt data sample\n");
                 }
 #else
-         rt_kprintf("please enable CRYP first!\n");       
-#endif    
-            }            
+         rt_kprintf("please enable CRYP first!\n");
+#endif
+            }
             else
             {
                 rt_kprintf("Unknown command. Please enter 'crypto' for help\n");
@@ -443,7 +443,7 @@ static int crypto(int argc, char **argv)
         rt_kprintf("crypto cryp sample                          - encrypt and decrypt data\n");
         result = -RT_ERROR;
     }
-    
+
     return result;
 }
 MSH_CMD_EXPORT(crypto, crypto function);
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.c
index b2fbc3561b..229c3e585e 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -156,7 +156,7 @@ static rt_err_t phy_write_reg(uint8_t phy_addr, uint8_t reg_addr, uint16_t reg_v
             return -RT_ETIMEOUT;
         }
     }
-    
+
     return RT_EOK;
 }
 
@@ -165,7 +165,7 @@ static uint16_t phy_read_reg(uint8_t phy_addr, uint8_t reg_addr)
     uint16_t reg_value = 0;
     uint32_t status = 0;
     volatile uint32_t tickstart = 0;
-    
+
     /* Take care not to alter MDC clock configuration */
     status = ETH->MACMDIOAR & ETH_MACMDIOAR_CR;
     /* Set up a read operation */
@@ -238,10 +238,10 @@ static void HAL_ETH_MspInit(void)
 {
     GPIO_InitTypeDef GPIO_InitStruct = {0};
     RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
-    
+
     if(IS_ENGINEERING_BOOT_MODE())
     {
-        /** Initializes the peripherals clock 
+        /** Initializes the peripherals clock
         */
         PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ETH;
         PeriphClkInit.EthClockSelection = RCC_ETHCLKSOURCE_PLL4;
@@ -250,10 +250,10 @@ static void HAL_ETH_MspInit(void)
             Error_Handler();
         }
     }
-  
+
     /* Enable SYSCFG clock */
     __HAL_RCC_SYSCFG_CLK_ENABLE();
-    
+
     /* Enable GPIO clocks */
     __HAL_RCC_GPIOA_CLK_ENABLE();
     __HAL_RCC_GPIOB_CLK_ENABLE();
@@ -263,12 +263,12 @@ static void HAL_ETH_MspInit(void)
 
     /* Select RGMII interface mode */
     HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RGMII);
-    
+
     /* Enable Ethernet MAC clock */
     __HAL_RCC_ETH1MAC_CLK_ENABLE();
     __HAL_RCC_ETH1TX_CLK_ENABLE();
     __HAL_RCC_ETH1RX_CLK_ENABLE();
-    
+
     /**ETH1 GPIO Configuration
     PA1     ------>  ETH1_RX_CLK
     PA7     ------>  ETH1_RX_CTL
@@ -303,12 +303,12 @@ static void HAL_ETH_MspInit(void)
     HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
 
     GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_13|GPIO_PIN_14;
-    HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 
+    HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
 
     /* ETH interrupt Init */
     HAL_NVIC_SetPriority(ETH1_IRQn, 0x01, 0x00);
     HAL_NVIC_EnableIRQ(ETH1_IRQn);
-    
+
     /* Configure PHY_RST (PG0) */
     GPIO_InitStruct.Pin = GPIO_PIN_0;
     GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
@@ -326,11 +326,11 @@ static void HAL_ETH_MspInit(void)
 static rt_err_t rt_stm32_eth_init(rt_device_t dev)
 {
     RT_ASSERT(dev != RT_NULL);
-    
+
     rt_uint32_t status, i;
     volatile rt_uint32_t tickstart = 0;
     rt_uint8_t  *macAddr = &stm32_eth_device.dev_addr[0];
-    
+
     /* Initialize TX descriptor index */
     txIndex = 0;
     /* Initialize RX descriptor index */
@@ -372,30 +372,30 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev)
     ETH->MACA2HR = 0;
     ETH->MACA3LR = 0;
     ETH->MACA3HR = 0;
-    
+
     /* Initialize hash table */
     ETH->MACHT0R = 0;
     ETH->MACHT1R = 0;
-    
+
     /* Configure the receive filter */
     ETH->MACPFR = ETH_MACPFR_HPF | ETH_MACPFR_HMC;
-    
+
     /* Disable flow control */
     ETH->MACQ0TXFCR = 0;
     ETH->MACRXFCR   = 0;
-    
+
     /* Enable the first RX queue */
     ETH->MACRXQC0R = ETH_MACRXQC0R_RXQ0EN_Val(1);
-    
+
     /* Configure DMA operating mode */
     ETH->DMAMR = ETH_DMAMR_INTM_Val(0) | ETH_DMAMR_PR_Val(0);
-    
+
     /* Configure system bus mode */
     ETH->DMASBMR |= ETH_DMASBMR_AAL;
-    
+
     /* The DMA takes the descriptor table as contiguous */
     ETH->DMAC0CR = ETH_DMAC0CR_DSL_Val(0);
-    
+
     /* Configure TX features */
     ETH->DMAC0TXCR = ETH_DMAC0TXCR_TXPBL_Val(1);
 
@@ -427,12 +427,12 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev)
         rxDmaDesc[i].rdes2 = 0;
         rxDmaDesc[i].rdes3 = ETH_RDES3_OWN | ETH_RDES3_IOC | ETH_RDES3_BUF1V;
     }
-    
+
     /* Set Transmit Descriptor List Address Register */
     ETH->DMAC0TXDLAR = (uint32_t) &txDmaDesc[0];
     /* Length of the transmit descriptor ring */
     ETH->DMAC0TXRLR = ETH_TXBUFNB - 1;
-    
+
     /* Set Receive Descriptor List Address Register */
     ETH->DMAC0RXDLAR = (uint32_t) &rxDmaDesc[0];
     /* Length of the receive descriptor ring */
@@ -441,24 +441,24 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev)
     /* Prevent interrupts from being generated when the transmit statistic
      * counters reach half their maximum value */
     ETH->MMCTXIMR = ETH_MMCTXIMR_TXLPITRCIM | ETH_MMCTXIMR_TXLPIUSCIM | ETH_MMCTXIMR_TXGPKTIM | ETH_MMCTXIMR_TXMCOLGPIM | ETH_MMCTXIMR_TXSCOLGPIM;
-    
+
     /* Prevent interrupts from being generated when the receive statistic
      * counters reach half their maximum value */
     ETH->MMCRXIMR = ETH_MMCRXIMR_RXLPITRCIM | ETH_MMCRXIMR_RXLPIUSCIM | ETH_MMCRXIMR_RXUCGPIM | ETH_MMCRXIMR_RXALGNERPIM | ETH_MMCRXIMR_RXCRCERPIM;
-   
+
     /* Disable MAC interrupts */
     ETH->MACIER = 0;
-    
+
     /* Enable the desired DMA interrupts */
     ETH->DMAC0IER = ETH_DMAC0IER_NIE | ETH_DMAC0IER_RIE | ETH_DMAC0IER_TIE;
-    
+
     /* Enable MAC transmission and reception */
     ETH->MACCR |= ETH_MACCR_TE | ETH_MACCR_RE;
-   
+
     /* Enable DMA transmission and reception */
     ETH->DMAC0TXCR |= ETH_DMAC0TXCR_ST;
     ETH->DMAC0RXCR |= ETH_DMAC0RXCR_SR;
-   
+
     /* Reset PHY transceiver */
     phy_write_reg(RTL8211F_PHY_ADDR, RTL8211F_BMCR, RTL8211F_BMCR_RESET);
     status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_BMCR);
@@ -474,9 +474,9 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev)
         else
         {
             status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_BMCR);
-        } 
+        }
     }
-    
+
     /* The PHY will generate interrupts when link status changes are detected */
     phy_write_reg(RTL8211F_PHY_ADDR, RTL8211F_INER, RTL8211F_INER_AN_COMPLETE | RTL8211F_INER_LINK_STATUS);
 
@@ -515,11 +515,11 @@ static rt_err_t rt_stm32_eth_control(rt_device_t dev, int cmd, void *args)
     {
     case NIOCTL_GADDR:
         /* get mac address */
-        if (args) 
+        if (args)
         {
             rt_memcpy(args, stm32_eth_device.dev_addr, 6);
         }
-        else 
+        else
         {
             return -RT_ERROR;
         }
@@ -536,7 +536,7 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
 {
     uint32_t framelen = 0;
     struct pbuf *q = RT_NULL;
-    
+
     /* Copy user data to the transmit buffer */
     for (q = p; q != NULL; q = q->next)
     {
@@ -546,12 +546,12 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
             LOG_D("buffer not valid");
             return ERR_USE;
         }
-        
+
         level = rt_hw_interrupt_disable();
         rt_memcpy(&txBuffer[txIndex][framelen], q->payload, q->len);
         framelen += q->len;
         rt_hw_interrupt_enable(level);
-        
+
         /* Check the frame length */
         if (framelen > ETH_TX_BUF_SIZE - 1)
         {
@@ -559,7 +559,7 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
             return ERR_USE;
         }
     }
-    
+
 #ifdef ETH_TX_DUMP
         rt_kprintf("Tx dump, len= %d\r\n", framelen);
         dump_hex(txBuffer[txIndex], framelen);
@@ -579,7 +579,7 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
     ETH->DMAC0SR = ETH_DMAC0SR_TBU;
     /* Instruct the DMA to poll the transmit descriptor list */
     ETH->DMAC0TXDTPR = 0;
-    
+
     if (++txIndex > ETH_TXBUFNB - 1)
     {
         txIndex = 0;
@@ -595,7 +595,7 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
     struct pbuf *p = RT_NULL, *q = RT_NULL;
 
     /* The current buffer is available for reading */
-    if (!(rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_OWN)) 
+    if (!(rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_OWN))
     {
         /* FD and LD flags should be set */
         if ((rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_FD) && (rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_LD))
@@ -617,7 +617,7 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
                             rt_memcpy(q->payload, &rxBuffer[rxIndex][framelen], q->len);
                             framelen += q->len;
                             rt_hw_interrupt_enable(level);
-                            
+
                             if (framelen > framelength)
                             {
                                 LOG_E("frame len is too long!");
@@ -632,7 +632,7 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
                     LOG_D("the received packet contains an error!");
                     return RT_NULL;
                 }
-                
+
             }
         else
         {
@@ -645,7 +645,7 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
         rxDmaDesc[rxIndex].rdes0 = (uint32_t)rxBuffer[rxIndex];
         /* Give the ownership of the descriptor back to the DMA */
         rxDmaDesc[rxIndex].rdes3 = ETH_RDES3_OWN | ETH_RDES3_IOC | ETH_RDES3_BUF1V;
-        
+
 #ifdef ETH_RX_DUMP
         rt_kprintf("Rx dump, len= %d\r\n", framelen);
         dump_hex(rxBuffer[rxIndex], framelen);
@@ -660,14 +660,14 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
         /* Instruct the DMA to poll the receive descriptor list */
         ETH->DMAC0RXDTPR = 0;
     }
-    
+
     return p;
 }
 
 void ETH1_IRQHandler(void)
 {
     rt_uint32_t status = 0;
-    
+
     /* enter interrupt */
     rt_interrupt_enter();
     /* Read DMA status register */
@@ -683,7 +683,7 @@ void ETH1_IRQHandler(void)
     {
         /* Disable RIE interrupt */
         ETH->DMAC0IER &= ~ETH_DMAC0IER_RIE;
-        
+
         rt_event_send(&rx_event, status);
     }
     /* ETH DMA Error */
@@ -694,7 +694,7 @@ void ETH1_IRQHandler(void)
     }
     /* Clear the interrupt flags */
     ETH->DMAC0SR = ETH_DMAC0SR_NIS;
-    
+
     /* leave interrupt */
     rt_interrupt_leave();
 
@@ -704,19 +704,19 @@ static void phy_linkchange()
 {
     rt_uint32_t status = 0;
 
-	/* Read status register to acknowledge the interrupt */
+    /* Read status register to acknowledge the interrupt */
     status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_INSR);
-	
+
 
     if (status & (RTL8211F_BMSR_LINK_STATUS | RTL8211F_INSR_AN_COMPLETE))
     {
-	    status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_BMSR);
-    	status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_BMSR);
+        status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_BMSR);
+        status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_BMSR);
         if (status & RTL8211F_BMSR_LINK_STATUS)
         {
-            LOG_D("link up");  
+            LOG_D("link up");
 
-			status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_PHYSR);
+            status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_PHYSR);
             switch (status & RTL8211F_PHYSR_SPEED)
             {
             case RTL8211F_PHYSR_SPEED_10MBPS:
@@ -725,25 +725,25 @@ static void phy_linkchange()
                 stm32_eth_device.eth_speed |= PHY_10M;
               }
             break;
-            
+
             case RTL8211F_PHYSR_SPEED_100MBPS:
               {
                 LOG_D("speed: 100M");
                 stm32_eth_device.eth_speed |= PHY_100M;
               }
             break;
-            
+
             case RTL8211F_PHYSR_SPEED_1000MBPS:
               {
                 LOG_D("speed: 1000M");
                 stm32_eth_device.eth_speed |= PHY_1000M;
               }
             break;
-            
+
             /* Unknown speed */
             default:
                 rt_kprintf("Invalid speed.");
-            break;    
+            break;
             }
 
             stm32_eth_device.eth_mode = (status & RTL8211F_PHYSR_DUPLEX)? PHY_FULL_DUPLEX : PHY_HALF_DUPLEX ;
@@ -812,9 +812,9 @@ static void phy_monitor_thread_entry(void *parameter)
                     eth_device_ready(&(stm32_eth_device.parent));
                 }
             }
-            
+
             /* enable DMA interrupts */
-            ETH->DMAC0IER = ETH_DMAC0IER_NIE | ETH_DMAC0IER_RIE | ETH_DMAC0IER_TIE; 
+            ETH->DMAC0IER = ETH_DMAC0IER_NIE | ETH_DMAC0IER_RIE | ETH_DMAC0IER_TIE;
         }
     }
 }
@@ -823,7 +823,7 @@ static void phy_monitor_thread_entry(void *parameter)
 static int rt_hw_stm32_eth_init(void)
 {
     rt_err_t state = RT_EOK;
-    
+
     /* OUI 00-80-E1 STMICROELECTRONICS. */
     stm32_eth_device.dev_addr[0] = 0x00;
     stm32_eth_device.dev_addr[1] = 0x80;
@@ -845,7 +845,7 @@ static int rt_hw_stm32_eth_init(void)
     stm32_eth_device.parent.eth_tx = rt_stm32_eth_tx;
 
     rt_event_init(&rx_event, "eth_rx", RT_IPC_FLAG_FIFO);
-    
+
     /* register eth device */
     state = eth_device_init(&(stm32_eth_device.parent), "e0");
     if (RT_EOK == state)
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.h b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.h
index 40d7db8353..a85651be72 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.h
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_exti.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_exti.c
index d3d118fd9f..caaf002aa9 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_exti.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_exti.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,7 +28,7 @@ static int exti_sample(void)
     rt_pin_mode(KEY2_PIN, PIN_MODE_INPUT_PULLUP);
     rt_pin_attach_irq(KEY2_PIN, PIN_IRQ_MODE_FALLING, key2_on, RT_NULL);
     rt_pin_irq_enable(KEY2_PIN, PIN_IRQ_ENABLE);
-    
+
     return RT_EOK;
 }
 INIT_DEVICE_EXPORT(exti_sample);
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_lptim.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_lptim.c
index 82f66e9916..0e479b6ae6 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_lptim.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_lptim.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,9 +28,9 @@ void LPTIM1_IRQHandler(void)
 {
     /* enter interrupt */
     rt_interrupt_enter();
-    
+
     HAL_LPTIM_IRQHandler(&hlptim1);
-    
+
     /* leave interrupt */
     rt_interrupt_leave();
 }
@@ -41,9 +41,9 @@ void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
     {
         HAL_GPIO_TogglePin(GPIOH, GPIO_PIN_7);
     }
-    
+
     /* All level of ITs can interrupt */
-    __set_BASEPRI(0U); 
+    __set_BASEPRI(0U);
 
     lptim_stop();
     rt_kprintf("system returns to normal!\n");
@@ -53,12 +53,12 @@ static int lptim_control(uint8_t pre_value)
 {
     if(pre_value > 7)
     {
-       pre_value = 7; 
+       pre_value = 7;
     }
     hlptim1.Instance->CFGR &= ~(7 << 9);      /* clear PRESC[2:0] */
     hlptim1.Instance->CFGR |= pre_value << 9; /* set PRESC[2:0]  */
     rt_kprintf("set lptim pre value [0x%x] success!\n", pre_value);
-    
+
     return RT_EOK;
 }
 
@@ -70,9 +70,9 @@ int lptim_start(void)
         LOG_D("lptim1 start counting failed!\n");
         return -RT_ERROR;
     }
-    
+
     LOG_D("lptim1 start counting success!\n");
-        
+
     return RT_EOK;
 }
 
@@ -83,16 +83,16 @@ int lptim_stop(void)
         LOG_D("lptim1 stop failed!\n");
         return -RT_ERROR;
    }
-   
-   LOG_D("lptim1 stop counting success!\n"); 
-   
+
+   LOG_D("lptim1 stop counting success!\n");
+
    return RT_EOK;
 }
 
 int lptim_init(void)
 {
     rt_pin_mode(LED7_PIN, PIN_MODE_OUTPUT);
-        
+
     hlptim1.Instance = LPTIM1;
     hlptim1.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC;
     hlptim1.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV8;
@@ -110,7 +110,7 @@ int lptim_init(void)
         return -RT_ERROR;
     }
     LOG_D("lptim init success!\n");
-    
+
     return RT_EOK;
 }
 INIT_DEVICE_EXPORT(lptim_init);
@@ -120,7 +120,7 @@ static int lptim_sample(int argc, char *argv[])
     if (argc > 1)
     {
         if (!strcmp(argv[1], "start"))
-        { 
+        {
            lptim_start();
            return RT_EOK;
         }
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pmic.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pmic.c
index c5f26596cc..2915d7dcb2 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pmic.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pmic.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -29,12 +29,12 @@ static rt_err_t read_reg(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8
     struct rt_i2c_msg msg[2] = {0, 0};
 
     RT_ASSERT(bus != RT_NULL);
-    
+
     msg[0].addr  = STPMU1_I2C_ADDRESS;     /* Slave address */
     msg[0].flags = RT_I2C_WR;              /* Write flag */
     msg[0].buf   = ®                   /* Slave register address */
     msg[0].len   = 1;                      /* Number of bytes sent */
-        
+
     msg[1].addr  = STPMU1_I2C_ADDRESS;
     msg[1].flags = RT_I2C_RD;
     msg[1].len   = len;
@@ -55,7 +55,7 @@ static rt_err_t write_reg(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint
     struct rt_i2c_msg msgs;
 
     RT_ASSERT(bus != RT_NULL);
-    
+
     buf[0] = reg; //cmd
     buf[1] = data;
 
@@ -85,7 +85,7 @@ static rt_err_t stpmu1_read_reg(uint8_t register_id)
     {
         Error_Handler();
     }
-    
+
     return result;
 }
 
@@ -93,7 +93,7 @@ static void stpmu1_write_reg(uint8_t register_id, uint8_t value)
 {
     uint32_t status = RT_EOK;
     uint8_t readval = 0;
-    
+
     status = write_reg(pmic_dev, register_id, (rt_uint8_t)value);
 
     /* Check the communication status */
@@ -120,7 +120,7 @@ static uint32_t BSP_PMIC_MspInit(void)
     __HAL_RCC_GPIOA_CLK_ENABLE();
     GPIO_InitStruct.Pin       = GPIO_PIN_0;
     GPIO_InitStruct.Mode      = GPIO_MODE_IT_FALLING;
-    GPIO_InitStruct.Pull      = GPIO_PULLUP; 
+    GPIO_InitStruct.Pull      = GPIO_PULLUP;
     GPIO_InitStruct.Speed     = GPIO_SPEED_FREQ_HIGH;
     GPIO_InitStruct.Alternate = 0 ;
     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
@@ -619,7 +619,7 @@ static uint8_t STPMU1_Voltage_Find_Index(PMIC_RegulId_TypeDef id, uint16_t miliv
     uint8_t i;
     for ( i = 0 ; i < regul->voltage_table_size ; i++)
     {
-        if ( regul->voltage_table[i] == milivolts ) 
+        if ( regul->voltage_table[i] == milivolts )
         {
           LOG_D("idx:%d for %dmV\n\r", (int)i, (int)milivolts);
           return i;
@@ -716,7 +716,7 @@ void BSP_PMIC_INTn_Callback(PMIC_IRQn IRQn)
     LOG_I(" Interrupt received\n\r");
 }
 
-void STPMU1_INTn_Callback(PMIC_IRQn IRQn) 
+void STPMU1_INTn_Callback(PMIC_IRQn IRQn)
 {
     BSP_PMIC_INTn_Callback(IRQn);
 }
@@ -846,15 +846,15 @@ static rt_err_t rt_hw_pmic_init_register(void)
 static rt_err_t rt_hw_pmic_init(const char *bus_name)
 {
     PMIC_IRQn irq;
-    
+
     pmic_dev = rt_i2c_bus_device_find(bus_name);
-    
+
     if (pmic_dev == RT_NULL)
     {
         LOG_E("%s bus not found\n", bus_name);
         return -RT_ERROR;
     }
-    
+
     if (stpmu1_read_reg(VERSION_STATUS_REG) != PMIC_VERSION_ID)
     {
         return -RT_EIO;
@@ -863,7 +863,7 @@ static rt_err_t rt_hw_pmic_init(const char *bus_name)
     STPMU1_Enable_Interrupt(IT_PONKEY_R);
     STPMU1_Enable_Interrupt(IT_PONKEY_F);
     /* enable all irqs  */
-    for (irq = IT_SWOUT_R; irq < IRQ_NR; irq++) 
+    for (irq = IT_SWOUT_R; irq < IRQ_NR; irq++)
     {
         STPMU1_Enable_Interrupt(irq);
     }
@@ -874,18 +874,18 @@ static rt_err_t rt_hw_pmic_init(const char *bus_name)
 static rt_err_t rt_hw_pmic_deinit(void)
 {
     BSP_PMIC_MspDeInit();
-    
+
     return RT_EOK;
 }
 
 static int pmic_init(void)
 {
     rt_err_t result = RT_EOK;
-    
+
     if (IS_ENGINEERING_BOOT_MODE())
     {
         BSP_PMIC_MspInit();
-        
+
         result = rt_hw_pmic_init(I2C_NAME);
         if(result != RT_EOK)
         {
@@ -893,16 +893,16 @@ static int pmic_init(void)
             rt_hw_pmic_deinit();
             return RT_ERROR;
         }
-        
+
         rt_hw_pmic_init_register();
-        
+
         __HAL_RCC_VREF_CLK_ENABLE();
         HAL_SYSCFG_VREFBUF_HighImpedanceConfig(SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE);
         HAL_SYSCFG_EnableVREFBUF();
     }
 
     LOG_I("stpmic init success!");
-        
+
     return RT_EOK;
 }
 INIT_PREV_EXPORT(pmic_init);
@@ -910,12 +910,12 @@ INIT_PREV_EXPORT(pmic_init);
 static int i2c_sample(int argc, char *argv[])
 {
     rt_uint8_t id = 0;
-    
+
     if (argc > 1)
     {
         if (!rt_strcmp(argv[1], "read"))
-        { 
-           rt_kprintf("i2c read pmic version id\n"); 
+        {
+           rt_kprintf("i2c read pmic version id\n");
            id = stpmu1_read_reg(VERSION_STATUS_REG);
            rt_kprintf("version id : 0x%02x\n", id);
            return RT_EOK;
@@ -930,7 +930,7 @@ _exit:
         rt_kprintf("Usage:\n");
         rt_kprintf("i2c_sample read          - read pmic verison id\n");
     }
-    
+
     return RT_ERROR;
 }
 MSH_CMD_EXPORT(i2c_sample, i2c sample);
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pmic.h b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pmic.h
index b24ccaeaf3..72c4af3a49 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pmic.h
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pmic.h
@@ -6,11 +6,11 @@
   ******************************************************************************
   * @attention
   *
-  * 
© Copyright (c) 2019 STMicroelectronics. 
+  * 
© Copyright (c) 2019 STMicroelectronics.
   * All rights reserved.

   *
   * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
+  * the "License"; You may not use this file except in compliance with the
   * License. You may obtain a copy of the License at:
   *                       opensource.org/licenses/BSD-3-Clause
   *
@@ -98,7 +98,7 @@ typedef struct {
 
 /* Those define should reflect NVM_USER section
  * For ES Eval Configuration this is specified as
- * 	0xF7,
+ *  0xF7,
  0x92,
  0xC0,
  0x02,
@@ -146,12 +146,12 @@ typedef struct {
 
  *
  */
-#define OTP_VINOK_HYST  	((NVM_SECTOR3_REGISTER_0 & 0xC0) >> 6) 	// nvm_vinok_hyst
-#define OTP_VINOK		  	((NVM_SECTOR3_REGISTER_0 & 0x30) >> 4) 	// nvm_vinok
-#define OTP_LDO4_FORCED     ((NVM_SECTOR3_REGISTER_0 & 0x08) >> 3) 	// Otp_ldo4_forced
-#define OTP_LONGKEYPRESSED  ((NVM_SECTOR3_REGISTER_0 & 0x04) >> 2)	// nvm_longkeypress
-#define OTP_AUTOTURNON  	((NVM_SECTOR3_REGISTER_0 & 0x02) >> 1)	// nvm_autoturnon
-#define OTP_CC_KEEPOFF  	((NVM_SECTOR3_REGISTER_0 & 0x01))		// nvm_cc_keepoff
+#define OTP_VINOK_HYST      ((NVM_SECTOR3_REGISTER_0 & 0xC0) >> 6)  // nvm_vinok_hyst
+#define OTP_VINOK           ((NVM_SECTOR3_REGISTER_0 & 0x30) >> 4)  // nvm_vinok
+#define OTP_LDO4_FORCED     ((NVM_SECTOR3_REGISTER_0 & 0x08) >> 3)  // Otp_ldo4_forced
+#define OTP_LONGKEYPRESSED  ((NVM_SECTOR3_REGISTER_0 & 0x04) >> 2)  // nvm_longkeypress
+#define OTP_AUTOTURNON      ((NVM_SECTOR3_REGISTER_0 & 0x02) >> 1)  // nvm_autoturnon
+#define OTP_CC_KEEPOFF      ((NVM_SECTOR3_REGISTER_0 & 0x01))       // nvm_cc_keepoff
 
 /*
  * nvm_rank_buck4:
@@ -176,10 +176,10 @@ typedef struct {
  11:  rank3
  *
  */
-#define OTP_RANK_BUCK4  	((NVM_SECTOR3_REGISTER_1 & 0xC0) >> 6) 	// nvm_rank_buck4
-#define OTP_RANK_BUCK3		((NVM_SECTOR3_REGISTER_1 & 0x30) >> 4) 	// nvm_rank_buck3
-#define OTP_RANK_BUCK2     	((NVM_SECTOR3_REGISTER_1 & 0x0C) >> 2) 	// nvm_rank_buck2
-#define OTP_RANK_BUCK1  	((NVM_SECTOR3_REGISTER_1 & 0x03))		// nvm_rank_buck1
+#define OTP_RANK_BUCK4      ((NVM_SECTOR3_REGISTER_1 & 0xC0) >> 6)  // nvm_rank_buck4
+#define OTP_RANK_BUCK3      ((NVM_SECTOR3_REGISTER_1 & 0x30) >> 4)  // nvm_rank_buck3
+#define OTP_RANK_BUCK2      ((NVM_SECTOR3_REGISTER_1 & 0x0C) >> 2)  // nvm_rank_buck2
+#define OTP_RANK_BUCK1      ((NVM_SECTOR3_REGISTER_1 & 0x03))       // nvm_rank_buck1
 
 
 /*
@@ -205,10 +205,10 @@ typedef struct {
  11:  rank3
  *
  */
-#define OTP_RANK_LDO4  		((NVM_SECTOR3_REGISTER_2 & 0xC0) >> 6) 	// nvm_rank_ldo4
-#define OTP_RANK_LDO3		((NVM_SECTOR3_REGISTER_2 & 0x30) >> 4) 	// nvm_rank_ldo3
-#define OTP_RANK_LDO2     	((NVM_SECTOR3_REGISTER_2 & 0x0C) >> 2) 	// nvm_rank_ldo2
-#define OTP_RANK_LDO1  		((NVM_SECTOR3_REGISTER_2 & 0x03))		// nvm_rank_ldo1
+#define OTP_RANK_LDO4       ((NVM_SECTOR3_REGISTER_2 & 0xC0) >> 6)  // nvm_rank_ldo4
+#define OTP_RANK_LDO3       ((NVM_SECTOR3_REGISTER_2 & 0x30) >> 4)  // nvm_rank_ldo3
+#define OTP_RANK_LDO2       ((NVM_SECTOR3_REGISTER_2 & 0x0C) >> 2)  // nvm_rank_ldo2
+#define OTP_RANK_LDO1       ((NVM_SECTOR3_REGISTER_2 & 0x03))       // nvm_rank_ldo1
 
 /*
  * nvm_clamp_output_buck: Clamp output value to 1.3V max
@@ -238,11 +238,11 @@ nvm_rank_ldo5:
  11:  rank3
  *
  */
-#define OTP_CLAMP_OUTPUT_BUCK4  ((NVM_SECTOR3_REGISTER_3 & 0x80) >> 7) 	// nvm_clamp_output_buck4
-#define OTP_BYPASS_MODE_LDO3  	((NVM_SECTOR3_REGISTER_3 & 0x40) >> 6) 	// nvm_bypass_mode_ldo3
-#define OTP_RANK_VREFDDR		((NVM_SECTOR3_REGISTER_3 & 0x30) >> 4) 	// nvm_rank_vrefddr
-#define OTP_RANK_LDO6     		((NVM_SECTOR3_REGISTER_3 & 0x0C) >> 2) 	// nvm_rank_ldo6
-#define OTP_RANK_LDO5  			((NVM_SECTOR3_REGISTER_3 & 0x03))		// nvm_rank_ldo5
+#define OTP_CLAMP_OUTPUT_BUCK4  ((NVM_SECTOR3_REGISTER_3 & 0x80) >> 7)  // nvm_clamp_output_buck4
+#define OTP_BYPASS_MODE_LDO3    ((NVM_SECTOR3_REGISTER_3 & 0x40) >> 6)  // nvm_bypass_mode_ldo3
+#define OTP_RANK_VREFDDR        ((NVM_SECTOR3_REGISTER_3 & 0x30) >> 4)  // nvm_rank_vrefddr
+#define OTP_RANK_LDO6           ((NVM_SECTOR3_REGISTER_3 & 0x0C) >> 2)  // nvm_rank_ldo6
+#define OTP_RANK_LDO5           ((NVM_SECTOR3_REGISTER_3 & 0x03))       // nvm_rank_ldo5
 
 /*
  * nvm_output_buck4: Buck4 default output selection
@@ -267,31 +267,31 @@ nvm_rank_ldo5:
  11:  1.25V
  *
  */
-#define OTP_OUTPUT_BUCK4  		((NVM_SECTOR3_REGISTER_4 & 0xC0) >> 6) 	// nvm_output_buck4
-#define OTP_OUTPUT_BUCK3		((NVM_SECTOR3_REGISTER_4 & 0x30) >> 4) 	// nvm_output_buck3
-#define OTP_OUTPUT_BUCK2     	((NVM_SECTOR3_REGISTER_4 & 0x0C) >> 2) 	// nvm_output_buck2
-#define OTP_OUTPUT_BUCK1  		((NVM_SECTOR3_REGISTER_4 & 0x03))		// nvm_output_buck1
+#define OTP_OUTPUT_BUCK4        ((NVM_SECTOR3_REGISTER_4 & 0xC0) >> 6)  // nvm_output_buck4
+#define OTP_OUTPUT_BUCK3        ((NVM_SECTOR3_REGISTER_4 & 0x30) >> 4)  // nvm_output_buck3
+#define OTP_OUTPUT_BUCK2        ((NVM_SECTOR3_REGISTER_4 & 0x0C) >> 2)  // nvm_output_buck2
+#define OTP_OUTPUT_BUCK1        ((NVM_SECTOR3_REGISTER_4 & 0x03))       // nvm_output_buck1
 
 /*
- * [7]	OTP_SWOFF_BY_BOOST_OVP:
+ * [7]  OTP_SWOFF_BY_BOOST_OVP:
  0 -> SWOUT will not turnoff bu boost OVP
  1 -> SWOUT will be turnoff by BOOST OVP
 
- [6]	reserved
+ [6]    reserved
 
- [5:4]	nvm_output_ldo3: LDO3 default output selection
+ [5:4]  nvm_output_ldo3: LDO3 default output selection
  00:  1.8V
  01:  2.5V
  10:  3.3V
  11:  output_buck2<4:0>/2 (VTT termination for DDR3 x32, Analog divider implemented in Analog)
 
- [3:2]	nvm_output_ldo2: LDO2 default output selection
+ [3:2]  nvm_output_ldo2: LDO2 default output selection
  00: 1.8V
  01: 2.5V
  10: 2.9V
  11: 3.3V
 
- [1:0]	nvm_output_ldo1: LDO1 default output selection
+ [1:0]  nvm_output_ldo1: LDO1 default output selection
  00: 1.8V
  01: 2.5V
  10: 2.9V
@@ -299,21 +299,21 @@ nvm_rank_ldo5:
 
  *
  */
-#define OTP_SWOFF_BY_BOOST_OVP  ((NVM_SECTOR3_REGISTER_5 & 0x80) >> 7) 	// OTP_SWOFF_BY_BOOST_OVP
-#define OTP_OUTPUT_LDO3			((NVM_SECTOR3_REGISTER_5 & 0x30) >> 4) 	// nvm_output_ldo3
-#define OTP_OUTPUT_LDO2     	((NVM_SECTOR3_REGISTER_5 & 0x0C) >> 2) 	// nvm_output_ldo2
-#define OTP_OUTPUT_LDO1  		((NVM_SECTOR3_REGISTER_5 & 0x03))		// nvm_output_ldo1
+#define OTP_SWOFF_BY_BOOST_OVP  ((NVM_SECTOR3_REGISTER_5 & 0x80) >> 7)  // OTP_SWOFF_BY_BOOST_OVP
+#define OTP_OUTPUT_LDO3         ((NVM_SECTOR3_REGISTER_5 & 0x30) >> 4)  // nvm_output_ldo3
+#define OTP_OUTPUT_LDO2         ((NVM_SECTOR3_REGISTER_5 & 0x0C) >> 2)  // nvm_output_ldo2
+#define OTP_OUTPUT_LDO1         ((NVM_SECTOR3_REGISTER_5 & 0x03))       // nvm_output_ldo1
 
 /*
- * 	[7:4]	reserved
+ *  [7:4]   reserved
  *
- [3:2]	nvm_output_ldo6: LDO6 default output selection
+ [3:2]  nvm_output_ldo6: LDO6 default output selection
  00:  1.0V
  01:  1.2V
  10:  1.8V
  11:  3.3V
 
- [1:0]	nvm_output_ldo5: LDO5 default output selection
+ [1:0]  nvm_output_ldo5: LDO5 default output selection
  00:  1.8V
  01:  2.5V
  10:  2.9V
@@ -321,8 +321,8 @@ nvm_rank_ldo5:
  *
  */
 
-#define OTP_OUTPUT_LDO6     	((NVM_SECTOR3_REGISTER_6 & 0x0C) >> 2) 	// nvm_output_ldo6
-#define OTP_OUTPUT_LDO5  		((NVM_SECTOR3_REGISTER_6 & 0x03))		// nvm_output_ldo5
+#define OTP_OUTPUT_LDO6         ((NVM_SECTOR3_REGISTER_6 & 0x0C) >> 2)  // nvm_output_ldo6
+#define OTP_OUTPUT_LDO5         ((NVM_SECTOR3_REGISTER_6 & 0x03))       // nvm_output_ldo5
 
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
 #define BIT(_x)  (1<<(_x))
@@ -417,7 +417,7 @@ nvm_rank_ldo5:
 #define LDO_BUCK_PULL_DOWN_MASK     0x03
 
 
-/* Main PMIC Control Register 
+/* Main PMIC Control Register
  * MAIN_CONTROL_REG
  * Address : 0x10
  * */
@@ -427,7 +427,7 @@ nvm_rank_ldo5:
 #define RESTART_REQUEST_ENABLED     BIT(1)
 #define SOFTWARE_SWITCH_OFF_ENABLED BIT(0)
 
-/* Main PMIC PADS Control Register 
+/* Main PMIC PADS Control Register
  * PADS_PULL_REG
  * Address : 0x11
  * */
@@ -438,7 +438,7 @@ nvm_rank_ldo5:
 #define PONKEY_PU_ACTIVE            BIT(0)
 
 
-/* Main PMIC VINLOW Control Register 
+/* Main PMIC VINLOW Control Register
  * VIN_CONTROL_REGC DMSC
  * Address : 0x15
  * */
@@ -452,7 +452,7 @@ nvm_rank_ldo5:
 #define VINLOW_CTRL_REG_MASK        0xFF
 
 
-/* USB Control Register 
+/* USB Control Register
  * Address : 0x40
  * */
 #define BOOST_OVP_DISABLED          BIT(7)
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pwr.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pwr.c
index 3aac57603d..a98b280f1b 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pwr.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_pwr.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rcc.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rcc.c
index 8c6f45ad91..442bc14d9c 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rcc.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rcc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -31,7 +31,7 @@ static int rcc_sample(int argc, char *argv[])
     if (argc > 1)
     {
         if (!strcmp(argv[1], "enable"))
-        { 
+        {
            enable_clock();
            return RT_EOK;
         }
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rs485.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rs485.c
index 44eba3be91..78475ec7e8 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rs485.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rs485.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -29,7 +29,7 @@ static rt_err_t rs485_output(rt_device_t dev, void * buffer)
 static rt_err_t rs485_input(rt_device_t dev, rt_size_t size)
 {
     rt_sem_release(&rx_sem);
-    
+
     return RT_EOK;
 }
 
@@ -38,13 +38,13 @@ int rs485_send_data(char *tbuf, rt_uint16_t t_len)
 {
     /* change rs485 mode */
     RS485_OUT;
-    
+
     /* send data */
     rt_device_write(serial, 0, tbuf, t_len);
-    
+
     /* change rs485 mode */
     RS485_IN;
-    
+
     return RT_EOK;
 }
 
@@ -59,10 +59,10 @@ static void rs485_thread_entry(void *parameter)
         {
             rt_sem_take(&rx_sem, RT_WAITING_FOREVER);
         }
-        
+
         /* The data read through the serial port output dislocation */
         ch = ch + 1;
-        
+
         /* send char */
         rs485_send_data(&ch, 1);
     }
@@ -77,20 +77,20 @@ static int rs485_init(void)
     {
         rt_kprintf("find %s failed!\n", RS485_UART_DEVICE_NAME);
         return RT_ERROR;
-    }  
+    }
 
     rt_device_open(serial, RT_DEVICE_FLAG_INT_RX);
 
     /* set receive data callback function */
     rt_device_set_rx_indicate(serial, rs485_input);
-    
+
     /* set the send completion callback function */
     rt_device_set_tx_complete(serial, rs485_output);
-        
+
     rt_pin_mode(BSP_RS485_RTS_PIN, PIN_MODE_OUTPUT);
-    
+
     RS485_IN;
-    
+
     rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO);
     /* create rs485 thread */
     rt_thread_t thread = rt_thread_create("rs485", rs485_thread_entry, RT_NULL, 1024, 25, 10);
@@ -103,8 +103,8 @@ static int rs485_init(void)
     {
         return RT_ERROR;
     }
-    
-    return RT_EOK;    
+
+    return RT_EOK;
 }
 INIT_DEVICE_EXPORT(rs485_init);
 
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rs485.h b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rs485.h
index 01edf84ae8..0d9767ac04 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rs485.h
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_rs485.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,7 +17,7 @@ extern "C" {
 
 #define RS485_SEND_MODE      0
 #define RS485_RECV_MODE      1
-    
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.c
index 3e5085c3cd..458a62097a 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -10,11 +10,17 @@
 
 #include "board.h"
 #include "drv_sdio.h"
+
+#ifdef BSP_USING_SDIO1
 #include 
+#endif
 
 #ifdef BSP_USING_SDMMC
 
-//#define DRV_DEBUG
+#ifdef BSP_USING_SDIO2
+#define DRV_DEBUG
+#endif
+
 #define DBG_TAG              "drv.sdio"
 #ifdef DRV_DEBUG
 #define DBG_LVL               DBG_LOG
@@ -23,8 +29,9 @@
 #endif /* DRV_DEBUG */
 #include 
 
-static SD_HandleTypeDef hsd;
-static struct rt_mmcsd_host *host;
+static struct rt_mmcsd_host *host1;
+static struct rt_mmcsd_host *host2;
+
 #define SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS    (100000)
 
 #define RTHW_SDIO_LOCK(_sdio)   rt_mutex_take(&_sdio->mutex, RT_WAITING_FOREVER)
@@ -47,13 +54,14 @@ struct rthw_sdio
 };
 
 /* SYSRAM SDMMC1/2 accesses */
+#define SDCARD_ADDR          0x2FFFF000
 #if defined(__CC_ARM) || defined(__CLANG_ARM)
-rt_uint8_t cache_buf[SDIO_BUFF_SIZE] __attribute__((at(0x2FFC0000)));
+__attribute__((at(SDCARD_ADDR))) static rt_uint8_t cache_buf[SDIO_BUFF_SIZE];
+#elif defined ( __GNUC__ )
+static rt_uint8_t cache_buf[SDIO_BUFF_SIZE] __attribute__((section(".SdCardSection")));
 #elif defined(__ICCARM__)
-#pragma location=0x2FFC0000
-rt_uint8_t cache_buf[SDIO_BUFF_SIZE];
-#elif defined(__GNUC__)
-rt_uint8_t cache_buf[SDIO_BUFF_SIZE] __attribute__((at(0x2FFC0000)));
+#pragma location = SDCARD_ADDR
+__no_init static rt_uint8_t cache_buf[SDIO_BUFF_SIZE];
 #endif
 
 /**
@@ -143,7 +151,7 @@ static void rthw_sdio_wait_completed(struct rthw_sdio *sdio)
     {
         return;
     }
-    
+
     cmd->resp[0] = hw_sdio->resp1;
     cmd->resp[1] = hw_sdio->resp2;
     cmd->resp[2] = hw_sdio->resp3;
@@ -159,22 +167,22 @@ static void rthw_sdio_wait_completed(struct rthw_sdio *sdio)
         {
             cmd->err = -RT_ERROR;
         }
-        
+
         if (status & SDMMC_STA_CTIMEOUT)
         {
             cmd->err = -RT_ETIMEOUT;
         }
-        
+
         if (status & SDMMC_STA_DCRCFAIL)
         {
             data->err = -RT_ERROR;
         }
-        
+
         if (status & SDMMC_STA_DTIMEOUT)
         {
             data->err = -RT_ETIMEOUT;
         }
-        
+
         if (cmd->err == RT_EOK)
         {
             LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
@@ -197,7 +205,7 @@ static void rthw_sdio_wait_completed(struct rthw_sdio *sdio)
                   data ? data->blksize : 0
                  );
         }
-        
+
     }
     else
     {
@@ -218,7 +226,7 @@ static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
     struct rt_mmcsd_data *data = cmd->data;
     struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
     rt_uint32_t reg_cmd;
-    
+
     sdio->pkg = pkg;
 
     LOG_D("CMD:%d ARG:0x%08x RES:%s%s%s%s%s%s%s%s%s rw:%c len:%d blksize:%d\n",
@@ -246,9 +254,9 @@ static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
         reg_cmd |= SDMMC_RESPONSE_LONG;
     else
         reg_cmd |= SDMMC_RESPONSE_SHORT;
-    
+
     hw_sdio->mask |= SDIO_MASKR_ALL;
-        
+
     /* data pre configuration */
     if (data != RT_NULL)
     {
@@ -284,7 +292,7 @@ static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
 
     /* close irq, keep sdio irq */
     hw_sdio->mask = hw_sdio->mask & SDMMC_IT_SDIOIT ? SDMMC_IT_SDIOIT : 0x00;
-    
+
     /* data post configuration */
     if (data != RT_NULL)
     {
@@ -308,7 +316,7 @@ static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r
     struct rt_mmcsd_data *data;
 
     RTHW_SDIO_LOCK(sdio);
-    
+
     if (req->cmd != RT_NULL)
     {
         rt_memset(&pkg, 0, sizeof(pkg));
@@ -338,7 +346,7 @@ static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r
     }
 
     RTHW_SDIO_UNLOCK(sdio);
-    
+
     mmcsd_req_complete(sdio->host);
 }
 
@@ -384,7 +392,7 @@ static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *
          );
 
     RTHW_SDIO_LOCK(sdio);
-    
+
     clk_src = SDIO_CLOCK_FREQ;
 
     if (clk > 0)
@@ -417,7 +425,7 @@ static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *
 
     if (io_cfg->power_mode == MMCSD_POWER_ON)
         hw_sdio->power |= SDMMC_POWER_PWRCTRL;
-    
+
     RTHW_SDIO_UNLOCK(sdio);
 }
 
@@ -461,10 +469,20 @@ struct rt_mmcsd_host *sdio_host_create(struct stm32_sdio_des *sdio_des)
 
     rt_memcpy(&sdio->sdio_des, sdio_des, sizeof(struct stm32_sdio_des));
 
-    sdio->sdio_des.hw_sdio = (struct stm32_sdio *)SDIO_BASE_ADDRESS;
+    if(sdio_des->hsd.Instance == SDMMC1)
+    {
+        sdio->sdio_des.hw_sdio = (struct stm32_sdio *)SDIO1_BASE_ADDRESS;
+        rt_event_init(&sdio->event, "sdio1", RT_IPC_FLAG_FIFO);
+        rt_mutex_init(&sdio->mutex, "sdio1", RT_IPC_FLAG_FIFO);
+    }
+
+    if(sdio_des->hsd.Instance == SDMMC2)
+    {
+        sdio->sdio_des.hw_sdio = (struct stm32_sdio *)SDIO2_BASE_ADDRESS;
+        rt_event_init(&sdio->event, "sdio2", RT_IPC_FLAG_FIFO);
+        rt_mutex_init(&sdio->mutex, "sdio2", RT_IPC_FLAG_FIFO);
+    }
 
-    rt_event_init(&sdio->event, "sdio", RT_IPC_FLAG_FIFO);
-    rt_mutex_init(&sdio->mutex, "sdio", RT_IPC_FLAG_FIFO);
     /* set host default attributes */
     host->ops = &ops;
     host->freq_min = 400 * 1000;
@@ -495,7 +513,7 @@ err:
     {
         rt_free(sdio);
     }
-    
+
     return RT_NULL;
 }
 
@@ -503,33 +521,91 @@ void SDMMC1_IRQHandler(void)
 {
     rt_interrupt_enter();
     /* Process All SDIO Interrupt Sources */
-    rthw_sdio_irq_process(host);
-    
+    rthw_sdio_irq_process(host1);
+
     rt_interrupt_leave();
 }
 
+void SDMMC2_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    /* Process All SDIO Interrupt Sources */
+    rthw_sdio_irq_process(host2);
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+#ifdef BSP_USING_SDIO2
+static RTC_HandleTypeDef hrtc;
+static void MX_RTC_Init(void)
+{
+    hrtc.Instance = RTC;
+    hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
+    hrtc.Init.AsynchPrediv = 127;
+    hrtc.Init.SynchPrediv = 255;
+    hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
+    hrtc.Instance->CFGR = 0x02 << 1;
+    if (HAL_RTC_Init(&hrtc) != HAL_OK)
+    {
+        Error_Handler();
+    }
+}
+static int LBEE5KL1DX_init(void)
+{
+#define LBEE5KL1DX_WL_REG_ON GET_PIN(H, 4)
+
+    /* enable the WLAN REG pin */
+    rt_pin_mode(LBEE5KL1DX_WL_REG_ON, PIN_MODE_OUTPUT);
+    rt_pin_write(LBEE5KL1DX_WL_REG_ON, PIN_HIGH);
+
+    return 0;
+}
+#endif
+
 int rt_hw_sdio_init(void)
 {
-    struct stm32_sdio_des sdio_des;
-    
-    hsd.Instance = SDMMC1;
-    HAL_SD_MspInit(&hsd);
+#ifdef BSP_USING_SDIO1
+    struct stm32_sdio_des sdio_des1;
+    sdio_des1.hsd.Instance = SDMMC1;
+    HAL_SD_MspInit(&sdio_des1.hsd);
 
-    host = sdio_host_create(&sdio_des);
-    if (host == RT_NULL)
+    host1 = sdio_host_create(&sdio_des1);
+    if (host1 == RT_NULL)
     {
         LOG_E("host create fail");
         return RT_NULL;
     }
+#endif
+
+#ifdef BSP_USING_SDIO2
     
+    if (IS_ENGINEERING_BOOT_MODE())
+    {
+        MX_RTC_Init();
+    }
+    LBEE5KL1DX_init();
+
+    struct stm32_sdio_des sdio_des2;
+    sdio_des2.hsd.Instance = SDMMC2;
+    HAL_SD_MspInit(&sdio_des2.hsd);
+
+    host2 = sdio_host_create(&sdio_des2);
+    if (host2 == RT_NULL)
+    {
+        LOG_E("host2 create fail");
+        return RT_NULL;
+    }
+#endif
     return RT_EOK;
 }
 INIT_DEVICE_EXPORT(rt_hw_sdio_init);
 
+#ifdef BSP_USING_SDIO1
 int mnt_init(void)
 {
     rt_device_t sd = RT_NULL;
-    
+
     rt_thread_delay(RT_TICK_PER_SECOND);
 
     sd = rt_device_find("sd0");
@@ -538,7 +614,7 @@ int mnt_init(void)
         rt_kprintf("can't find sd0 device!\n");
         return RT_ERROR;
     }
-    
+
     if (dfs_mount("sd0", "/", "elm", 0, 0) != 0)
     {
         rt_kprintf("file system mount failed!\n");
@@ -552,4 +628,6 @@ int mnt_init(void)
 }
 INIT_ENV_EXPORT(mnt_init);
 
+#endif /* BSP_USING_SDIO1 */
+
 #endif /* BSP_USING_SDMMC */
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.h b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.h
index a4428e4e71..9383e812e4 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.h
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_sdio.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -19,11 +19,12 @@
 #include 
 #include 
 
-#define SDIO_BUFF_SIZE       4096
-#define SDIO_ALIGN_LEN       32
+#ifndef SDIO1_BASE_ADDRESS
+#define SDIO1_BASE_ADDRESS    (SDMMC1)
+#endif
 
-#ifndef SDIO_BASE_ADDRESS
-#define SDIO_BASE_ADDRESS    (SDMMC1)
+#ifndef SDIO2_BASE_ADDRESS
+#define SDIO2_BASE_ADDRESS    (SDMMC2)
 #endif
 
 #ifndef SDIO_CLOCK_FREQ
@@ -39,7 +40,7 @@
 #endif
 
 #ifndef SDIO_MAX_FREQ
-#define SDIO_MAX_FREQ        (50 * 1000 * 1000)
+#define SDIO_MAX_FREQ        (25 * 1000 * 1000)
 #endif
 
 #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
@@ -89,7 +90,7 @@ struct stm32_sdio
     volatile rt_uint32_t idmalar;
     volatile rt_uint32_t idmabar;
     volatile rt_uint32_t reserved2[5];
-    volatile rt_uint32_t fifo;          
+    volatile rt_uint32_t fifo;
     volatile rt_uint32_t reserved3[220];
     volatile rt_uint32_t verr;
     volatile rt_uint32_t ipidr;
@@ -102,6 +103,7 @@ struct stm32_sdio_des
 {
     struct stm32_sdio *hw_sdio;
     sdio_clk_get clk_get;
+    SD_HandleTypeDef hsd;
 };
 
 /* stm32 sdio dirver class */
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_wwdg.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_wwdg.c
index 4e9910aa95..77bde7d7b7 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_wwdg.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_wwdg.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -22,15 +22,15 @@
 #define LED5_PIN  GET_PIN(A, 14)
 
 static rt_uint8_t feed_flag = 0;
-static WWDG_HandleTypeDef hwwdg1;  
+static WWDG_HandleTypeDef hwwdg1;
 
 void WWDG1_IRQHandler(void)
 {
     /* enter interrupt */
     rt_interrupt_enter();
-    
+
     HAL_WWDG_IRQHandler(&hwwdg1);
-    
+
     /* leave interrupt */
     rt_interrupt_leave();
 }
@@ -50,18 +50,18 @@ void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg)
 static void wwdg_init()
 {
     rt_pin_mode(LED5_PIN, PIN_MODE_OUTPUT);
-        
+
     hwwdg1.Instance       = WWDG1;
     hwwdg1.Init.Prescaler = WWDG_PRESCALER_8;
     hwwdg1.Init.Window    = 0X5F;
     hwwdg1.Init.Counter   = 0x7F;
     hwwdg1.Init.EWIMode   = WWDG_EWI_ENABLE;
-      
+
     if (HAL_WWDG_Init(&hwwdg1) != HAL_OK)
     {
         Error_Handler();
     }
-    
+
     feed_flag = 1;
 }
 
@@ -69,10 +69,10 @@ static void wwdg_control(uint8_t pre_value)
 {
     if(pre_value > 7)
     {
-       pre_value = 7; 
+       pre_value = 7;
     }
     hwwdg1.Instance->CFR &= ~(7 << 11);     /* clear WDGTB[2:0] */
-    hwwdg1.Instance->CFR |= pre_value << 11; /* set WDGTB[2:0] */	
+    hwwdg1.Instance->CFR |= pre_value << 11; /* set WDGTB[2:0] */
 }
 
 static void wwdg_stop(void)
@@ -85,7 +85,7 @@ static int wwdg_sample(int argc, char *argv[])
     if (argc > 1)
     {
         if (!strcmp(argv[1], "run"))
-        { 
+        {
             wwdg_init();
         }
         else if (!strcmp(argv[1], "set"))
@@ -93,7 +93,7 @@ static int wwdg_sample(int argc, char *argv[])
             if (argc > 2)
             {
                 wwdg_control(atoi(argv[2]));
-            }     
+            }
         }
         else if (!strcmp(argv[1], "stop"))
         {
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/spi_sample.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/spi_sample.c
index 1a4c91ac24..36a441d62f 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/spi_sample.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/spi_sample.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,15 +28,15 @@ static int rt_spi_device_init(void)
     cfg.max_hz = 1 *1000 *1000;
 
     spi_dev = (struct rt_spi_device *)rt_device_find(SPI_NAME);
-    
+
     if (RT_NULL == spi_dev)
     {
         rt_kprintf("spi sample run failed! can't find %s device!\n", SPI_NAME);
         return RT_ERROR;
     }
-    
+
     rt_spi_configure(spi_dev, &cfg);
-    
+
     return RT_EOK;
 }
 INIT_APP_EXPORT(rt_spi_device_init);
@@ -44,22 +44,22 @@ INIT_APP_EXPORT(rt_spi_device_init);
 /* spi5 loopback mode test case */
 static int spi_sample(int argc, char **argv)
 {
-    rt_uint8_t t_buf[8], r_buf[8];     
-    int i = 0; 
+    rt_uint8_t t_buf[8], r_buf[8];
+    int i = 0;
     static struct rt_spi_message msg1;
-    
+
     if (argc != 9)
     {
         rt_kprintf("Usage:\n");
         rt_kprintf("spi_sample 1 2 3 4 5 6 7 8\n");
         return -RT_ERROR;
     }
-    
+
     for (i = 0; i < 8; i++)
     {
         t_buf[i] = atoi(argv[i+1]);
     }
-    
+
     msg1.send_buf   = &t_buf;
     msg1.recv_buf   = &r_buf;
     msg1.length     = sizeof(t_buf);
diff --git a/bsp/stm32/stm32mp157a-st-discovery/board/ports/timer_sample.c b/bsp/stm32/stm32mp157a-st-discovery/board/ports/timer_sample.c
index fdbc721c8d..0f4df63bd3 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/board/ports/timer_sample.c
+++ b/bsp/stm32/stm32mp157a-st-discovery/board/ports/timer_sample.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -26,11 +26,11 @@ static rt_adc_device_t adc_dev = RT_NULL;
 static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size)
 {
     rt_uint32_t value = 0 , vol = 0;
-    
+
     /* read adc value */
     value = rt_adc_read(adc_dev, ADC_DEV_CHANNEL);
     rt_kprintf("the value is :%d \n", value);
-    
+
     vol = value * REFER_VOLTAGE / CONVERT_BITS;
     rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100);
 
@@ -55,21 +55,21 @@ static int hwtimer_stop(void)
         rt_kprintf("close %s device failed!\n", HWTIMER_DEV_NAME);
         return ret;
     }
-    
+
     /* close adc channel */
     ret = rt_adc_disable(adc_dev, ADC_DEV_CHANNEL);
-    
+
     return ret;
 }
 
 static int hwtimer_start(void)
 {
     rt_err_t ret = RT_EOK;
-    rt_hwtimerval_t timeout_s;     
+    rt_hwtimerval_t timeout_s;
     rt_device_t hw_dev = RT_NULL;
-    
+
     rt_hwtimer_mode_t mode;
-        
+
     hw_dev = rt_device_find(HWTIMER_DEV_NAME);
     if (hw_dev == RT_NULL)
     {
@@ -84,7 +84,7 @@ static int hwtimer_start(void)
         rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWADC_DEV_NAME);
         return RT_ERROR;
     }
-    
+
     /* Open the device in read/write mode */
     ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR);
     if (ret != RT_EOK)
@@ -118,10 +118,10 @@ static int hwtimer_start(void)
 
     rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s));
     rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec);
-    
+
     /* enable adc channel */
     ret = rt_adc_enable(adc_dev, ADC_DEV_CHANNEL);
-    
+
     return ret;
 }
 
@@ -130,8 +130,8 @@ static int tim_sample(int argc, char *argv[])
     if (argc > 1)
     {
         if (!rt_strcmp(argv[1], "start"))
-        { 
-           rt_kprintf("tim14 will start\n"); 
+        {
+           rt_kprintf("tim14 will start\n");
            hwtimer_start();
            return RT_EOK;
         }
@@ -152,7 +152,7 @@ _exit:
         rt_kprintf("tim_sample start         - start TIM14 \n");
         rt_kprintf("tim_sample stop          - stop TIM14 \n");
     }
-    
+
     return RT_ERROR;
 }
 MSH_CMD_EXPORT(tim_sample, tim sample);
diff --git a/bsp/stm32/stm32mp157a-st-discovery/project.ewp b/bsp/stm32/stm32mp157a-st-discovery/project.ewp
index 3547891da5..3f12a28dbe 100644
--- a/bsp/stm32/stm32mp157a-st-discovery/project.ewp
+++ b/bsp/stm32/stm32mp157a-st-discovery/project.ewp
@@ -232,6 +232,8 @@
           STM32MP157Axx
           __LOG_TRACE_IO_
           __RTTHREAD__
+          RT_USING_DLIBC
+          _DLIB_FILE_DESCRIPTOR
           USE_HAL_DRIVER
         
         
         
         
         

 *
@@ -59,38 +59,38 @@ extern "C" {
 /***************** Macros (Inline Functions) Definitions ********************/
 
 /* necessary for pre-processor */
-#define stringify(s)	tostring(s)
-#define tostring(s)	#s
+#define stringify(s)    tostring(s)
+#define tostring(s) #s
 
 #if defined (__aarch64__)
 /* pseudo assembler instructions */
-#define mfcpsr()	({rt_uint32_t rval = 0U; \
-			   asm volatile("mrs %0,  DAIF" : "=r" (rval));\
-			  rval;\
-			 })
+#define mfcpsr()    ({rt_uint32_t rval = 0U; \
+               asm volatile("mrs %0,  DAIF" : "=r" (rval));\
+              rval;\
+             })
 
 #define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v))
 
-#define cpsiei()	//__asm__ __volatile__("cpsie	i\n")
-#define cpsidi()	//__asm__ __volatile__("cpsid	i\n")
+#define cpsiei()    //__asm__ __volatile__("cpsie   i\n")
+#define cpsidi()    //__asm__ __volatile__("cpsid   i\n")
 
-#define cpsief()	//__asm__ __volatile__("cpsie	f\n")
-#define cpsidf()	//__asm__ __volatile__("cpsid	f\n")
+#define cpsief()    //__asm__ __volatile__("cpsie   f\n")
+#define cpsidf()    //__asm__ __volatile__("cpsid   f\n")
 
 
 
-#define mtgpr(rn, v)	/*__asm__ __volatile__(\
-			  "mov r" stringify(rn) ", %0 \n"\
-			  : : "r" (v)\
-			)*/
+#define mtgpr(rn, v)    /*__asm__ __volatile__(\
+              "mov r" stringify(rn) ", %0 \n"\
+              : : "r" (v)\
+            )*/
 
-#define mfgpr(rn)	/*({rt_uint32_t rval; \
-			  __asm__ __volatile__(\
-			    "mov %0,r" stringify(rn) "\n"\
-			    : "=r" (rval)\
-			  );\
-			  rval;\
-			 })*/
+#define mfgpr(rn)   /*({rt_uint32_t rval; \
+              __asm__ __volatile__(\
+                "mov %0,r" stringify(rn) "\n"\
+                : "=r" (rval)\
+              );\
+              rval;\
+             })*/
 
 /* memory synchronization operations */
 
@@ -105,13 +105,13 @@ extern "C" {
 
 
 /* Memory Operations */
-#define ldr(adr)	({u64 rval; \
-			  __asm__ __volatile__(\
-			    "ldr	%0,[%1]"\
-			    : "=r" (rval) : "r" (adr)\
-			  );\
-			  rval;\
-			 })
+#define ldr(adr)    ({u64 rval; \
+              __asm__ __volatile__(\
+                "ldr    %0,[%1]"\
+                : "=r" (rval) : "r" (adr)\
+              );\
+              rval;\
+             })
 
 #define mfelrel3() ({u64 rval = 0U; \
                    asm volatile("mrs %0,  ELR_EL3" : "=r" (rval));\
@@ -123,39 +123,39 @@ extern "C" {
 #else
 
 /* pseudo assembler instructions */
-#define mfcpsr()	({rt_uint32_t rval = 0U; \
-			  __asm__ __volatile__(\
-			    "mrs	%0, cpsr\n"\
-			    : "=r" (rval)\
-			  );\
-			  rval;\
-			 })
+#define mfcpsr()    ({rt_uint32_t rval = 0U; \
+              __asm__ __volatile__(\
+                "mrs    %0, cpsr\n"\
+                : "=r" (rval)\
+              );\
+              rval;\
+             })
 
-#define mtcpsr(v)	__asm__ __volatile__(\
-			  "msr	cpsr,%0\n"\
-			  : : "r" (v)\
-			)
+#define mtcpsr(v)   __asm__ __volatile__(\
+              "msr  cpsr,%0\n"\
+              : : "r" (v)\
+            )
 
-#define cpsiei()	__asm__ __volatile__("cpsie	i\n")
-#define cpsidi()	__asm__ __volatile__("cpsid	i\n")
+#define cpsiei()    __asm__ __volatile__("cpsie i\n")
+#define cpsidi()    __asm__ __volatile__("cpsid i\n")
 
-#define cpsief()	__asm__ __volatile__("cpsie	f\n")
-#define cpsidf()	__asm__ __volatile__("cpsid	f\n")
+#define cpsief()    __asm__ __volatile__("cpsie f\n")
+#define cpsidf()    __asm__ __volatile__("cpsid f\n")
 
 
 
-#define mtgpr(rn, v)	__asm__ __volatile__(\
-			  "mov r" stringify(rn) ", %0 \n"\
-			  : : "r" (v)\
-			)
+#define mtgpr(rn, v)    __asm__ __volatile__(\
+              "mov r" stringify(rn) ", %0 \n"\
+              : : "r" (v)\
+            )
 
-#define mfgpr(rn)	({rt_uint32_t rval; \
-			  __asm__ __volatile__(\
-			    "mov %0,r" stringify(rn) "\n"\
-			    : "=r" (rval)\
-			  );\
-			  rval;\
-			 })
+#define mfgpr(rn)   ({rt_uint32_t rval; \
+              __asm__ __volatile__(\
+                "mov %0,r" stringify(rn) "\n"\
+                : "=r" (rval)\
+              );\
+              rval;\
+             })
 
 /* memory synchronization operations */
 
@@ -170,72 +170,72 @@ extern "C" {
 
 
 /* Memory Operations */
-#define ldr(adr)	({rt_uint32_t rval; \
-			  __asm__ __volatile__(\
-			    "ldr	%0,[%1]"\
-			    : "=r" (rval) : "r" (adr)\
-			  );\
-			  rval;\
-			 })
+#define ldr(adr)    ({rt_uint32_t rval; \
+              __asm__ __volatile__(\
+                "ldr    %0,[%1]"\
+                : "=r" (rval) : "r" (adr)\
+              );\
+              rval;\
+             })
 
 #endif
 
-#define ldrb(adr)	({rt_uint8_t rval; \
-			  __asm__ __volatile__(\
-			    "ldrb	%0,[%1]"\
-			    : "=r" (rval) : "r" (adr)\
-			  );\
-			  rval;\
-			 })
+#define ldrb(adr)   ({rt_uint8_t rval; \
+              __asm__ __volatile__(\
+                "ldrb   %0,[%1]"\
+                : "=r" (rval) : "r" (adr)\
+              );\
+              rval;\
+             })
 
-#define str(adr, val)	__asm__ __volatile__(\
-			  "str	%0,[%1]\n"\
-			  : : "r" (val), "r" (adr)\
-			)
+#define str(adr, val)   __asm__ __volatile__(\
+              "str  %0,[%1]\n"\
+              : : "r" (val), "r" (adr)\
+            )
 
-#define strb(adr, val)	__asm__ __volatile__(\
-			  "strb	%0,[%1]\n"\
-			  : : "r" (val), "r" (adr)\
-			)
+#define strb(adr, val)  __asm__ __volatile__(\
+              "strb %0,[%1]\n"\
+              : : "r" (val), "r" (adr)\
+            )
 
 /* Count leading zeroes (clz) */
-#define clz(arg)	({rt_uint8_t rval; \
-			  __asm__ __volatile__(\
-			    "clz	%0,%1"\
-			    : "=r" (rval) : "r" (arg)\
-			  );\
-			  rval;\
-			 })
+#define clz(arg)    ({rt_uint8_t rval; \
+              __asm__ __volatile__(\
+                "clz    %0,%1"\
+                : "=r" (rval) : "r" (arg)\
+              );\
+              rval;\
+             })
 
 #if defined (__aarch64__)
-#define mtcpdc(reg,val)	__asm__ __volatile__("dc " #reg ",%0"  : : "r" (val))
-#define mtcpic(reg,val)	__asm__ __volatile__("ic " #reg ",%0"  : : "r" (val))
+#define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0"  : : "r" (val))
+#define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0"  : : "r" (val))
 
-#define mtcpicall(reg)	__asm__ __volatile__("ic " #reg)
-#define mtcptlbi(reg)	__asm__ __volatile__("tlbi " #reg)
-#define mtcpat(reg,val)	__asm__ __volatile__("at " #reg ",%0"  : : "r" (val))
+#define mtcpicall(reg)  __asm__ __volatile__("ic " #reg)
+#define mtcptlbi(reg)   __asm__ __volatile__("tlbi " #reg)
+#define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0"  : : "r" (val))
 /* CP15 operations */
-#define mfcp(reg)	({u64 rval = 0U;\
-			__asm__ __volatile__("mrs	%0, " #reg : "=r" (rval));\
-			rval;\
-			})
+#define mfcp(reg)   ({u64 rval = 0U;\
+            __asm__ __volatile__("mrs   %0, " #reg : "=r" (rval));\
+            rval;\
+            })
 
-#define mtcp(reg,val)	__asm__ __volatile__("msr " #reg ",%0"  : : "r" (val))
+#define mtcp(reg,val)   __asm__ __volatile__("msr " #reg ",%0"  : : "r" (val))
 
 #else
 /* CP15 operations */
-#define mtcp(rn, v)	__asm__ __volatile__(\
-			 "mcr " rn "\n"\
-			 : : "r" (v)\
-			);
+#define mtcp(rn, v) __asm__ __volatile__(\
+             "mcr " rn "\n"\
+             : : "r" (v)\
+            );
 
-#define mfcp(rn)	({rt_uint32_t rval = 0U; \
-			 __asm__ __volatile__(\
-			   "mrc " rn "\n"\
-			   : "=r" (rval)\
-			 );\
-			 rval;\
-			 })
+#define mfcp(rn)    ({rt_uint32_t rval = 0U; \
+             __asm__ __volatile__(\
+               "mrc " rn "\n"\
+               : "=r" (rval)\
+             );\
+             rval;\
+             })
 #endif
 
 /************************** Variable Definitions ****************************/
diff --git a/libcpu/arm/zynqmp-r5/xreg_cortexr5.h b/libcpu/arm/zynqmp-r5/xreg_cortexr5.h
index 263f213567..9c0ae2b440 100644
--- a/libcpu/arm/zynqmp-r5/xreg_cortexr5.h
+++ b/libcpu/arm/zynqmp-r5/xreg_cortexr5.h
@@ -23,86 +23,86 @@
 * 

 *
 ******************************************************************************/
-#ifndef XREG_CORTEXR5_H	/* prevent circular inclusions */
-#define XREG_CORTEXR5_H	/* by using protection macros */
+#ifndef XREG_CORTEXR5_H /* prevent circular inclusions */
+#define XREG_CORTEXR5_H /* by using protection macros */
 
 #ifdef __cplusplus
 extern "C" {
 #endif /* __cplusplus */
 
 /* GPRs */
-#define XREG_GPR0				r0
-#define XREG_GPR1				r1
-#define XREG_GPR2				r2
-#define XREG_GPR3				r3
-#define XREG_GPR4				r4
-#define XREG_GPR5				r5
-#define XREG_GPR6				r6
-#define XREG_GPR7				r7
-#define XREG_GPR8				r8
-#define XREG_GPR9				r9
-#define XREG_GPR10				r10
-#define XREG_GPR11				r11
-#define XREG_GPR12				r12
-#define XREG_GPR13				r13
-#define XREG_GPR14				r14
-#define XREG_GPR15				r15
-#define XREG_CPSR				cpsr
+#define XREG_GPR0               r0
+#define XREG_GPR1               r1
+#define XREG_GPR2               r2
+#define XREG_GPR3               r3
+#define XREG_GPR4               r4
+#define XREG_GPR5               r5
+#define XREG_GPR6               r6
+#define XREG_GPR7               r7
+#define XREG_GPR8               r8
+#define XREG_GPR9               r9
+#define XREG_GPR10              r10
+#define XREG_GPR11              r11
+#define XREG_GPR12              r12
+#define XREG_GPR13              r13
+#define XREG_GPR14              r14
+#define XREG_GPR15              r15
+#define XREG_CPSR               cpsr
 
 /* Coprocessor number defines */
-#define XREG_CP0				0
-#define XREG_CP1				1
-#define XREG_CP2				2
-#define XREG_CP3				3
-#define XREG_CP4				4
-#define XREG_CP5				5
-#define XREG_CP6				6
-#define XREG_CP7				7
-#define XREG_CP8				8
-#define XREG_CP9				9
-#define XREG_CP10				10
-#define XREG_CP11				11
-#define XREG_CP12				12
-#define XREG_CP13				13
-#define XREG_CP14				14
-#define XREG_CP15				15
+#define XREG_CP0                0
+#define XREG_CP1                1
+#define XREG_CP2                2
+#define XREG_CP3                3
+#define XREG_CP4                4
+#define XREG_CP5                5
+#define XREG_CP6                6
+#define XREG_CP7                7
+#define XREG_CP8                8
+#define XREG_CP9                9
+#define XREG_CP10               10
+#define XREG_CP11               11
+#define XREG_CP12               12
+#define XREG_CP13               13
+#define XREG_CP14               14
+#define XREG_CP15               15
 
 /* Coprocessor control register defines */
-#define XREG_CR0				cr0
-#define XREG_CR1				cr1
-#define XREG_CR2				cr2
-#define XREG_CR3				cr3
-#define XREG_CR4				cr4
-#define XREG_CR5				cr5
-#define XREG_CR6				cr6
-#define XREG_CR7				cr7
-#define XREG_CR8				cr8
-#define XREG_CR9				cr9
-#define XREG_CR10				cr10
-#define XREG_CR11				cr11
-#define XREG_CR12				cr12
-#define XREG_CR13				cr13
-#define XREG_CR14				cr14
-#define XREG_CR15				cr15
+#define XREG_CR0                cr0
+#define XREG_CR1                cr1
+#define XREG_CR2                cr2
+#define XREG_CR3                cr3
+#define XREG_CR4                cr4
+#define XREG_CR5                cr5
+#define XREG_CR6                cr6
+#define XREG_CR7                cr7
+#define XREG_CR8                cr8
+#define XREG_CR9                cr9
+#define XREG_CR10               cr10
+#define XREG_CR11               cr11
+#define XREG_CR12               cr12
+#define XREG_CR13               cr13
+#define XREG_CR14               cr14
+#define XREG_CR15               cr15
 
 /* Current Processor Status Register (CPSR) Bits */
-#define XREG_CPSR_THUMB_MODE			0x20U
-#define XREG_CPSR_MODE_BITS			0x1FU
-#define XREG_CPSR_SYSTEM_MODE			0x1FU
-#define XREG_CPSR_UNDEFINED_MODE		0x1BU
-#define XREG_CPSR_DATA_ABORT_MODE		0x17U
-#define XREG_CPSR_SVC_MODE			0x13U
-#define XREG_CPSR_IRQ_MODE			0x12U
-#define XREG_CPSR_FIQ_MODE			0x11U
-#define XREG_CPSR_USER_MODE			0x10U
+#define XREG_CPSR_THUMB_MODE            0x20U
+#define XREG_CPSR_MODE_BITS         0x1FU
+#define XREG_CPSR_SYSTEM_MODE           0x1FU
+#define XREG_CPSR_UNDEFINED_MODE        0x1BU
+#define XREG_CPSR_DATA_ABORT_MODE       0x17U
+#define XREG_CPSR_SVC_MODE          0x13U
+#define XREG_CPSR_IRQ_MODE          0x12U
+#define XREG_CPSR_FIQ_MODE          0x11U
+#define XREG_CPSR_USER_MODE         0x10U
 
-#define XREG_CPSR_IRQ_ENABLE			0x80U
-#define XREG_CPSR_FIQ_ENABLE			0x40U
+#define XREG_CPSR_IRQ_ENABLE            0x80U
+#define XREG_CPSR_FIQ_ENABLE            0x40U
 
-#define XREG_CPSR_N_BIT				0x80000000U
-#define XREG_CPSR_Z_BIT				0x40000000U
-#define XREG_CPSR_C_BIT				0x20000000U
-#define XREG_CPSR_V_BIT				0x10000000U
+#define XREG_CPSR_N_BIT             0x80000000U
+#define XREG_CPSR_Z_BIT             0x40000000U
+#define XREG_CPSR_C_BIT             0x20000000U
+#define XREG_CPSR_V_BIT             0x10000000U
 
 /*MPU region definitions*/
 #define REGION_32B     0x00000004U
@@ -138,99 +138,99 @@ extern "C" {
 
 
 
-#define SHAREABLE				0x00000004U 	/*shareable */
-#define STRONG_ORDERD_SHARED	0x00000000U	/*strongly ordered, always shareable*/
+#define SHAREABLE               0x00000004U     /*shareable */
+#define STRONG_ORDERD_SHARED    0x00000000U /*strongly ordered, always shareable*/
 
-#define DEVICE_SHARED			0x00000001U	/*device, shareable*/
-#define DEVICE_NONSHARED		0x00000010U	/*device, non shareable*/
+#define DEVICE_SHARED           0x00000001U /*device, shareable*/
+#define DEVICE_NONSHARED        0x00000010U /*device, non shareable*/
 
-#define NORM_NSHARED_WT_NWA		0x00000002U 	/*Outer and Inner write-through, no write-allocate non-shareable*/
-#define NORM_SHARED_WT_NWA		0x00000006U 	/*Outer and Inner write-through, no write-allocate shareable*/
+#define NORM_NSHARED_WT_NWA     0x00000002U     /*Outer and Inner write-through, no write-allocate non-shareable*/
+#define NORM_SHARED_WT_NWA      0x00000006U     /*Outer and Inner write-through, no write-allocate shareable*/
 
-#define NORM_NSHARED_WB_NWA 	0x00000003U 	/*Outer and Inner write-back, no write-allocate non shareable*/
-#define NORM_SHARED_WB_NWA 		0x00000007U 	/*Outer and Inner write-back, no write-allocate shareable*/
+#define NORM_NSHARED_WB_NWA     0x00000003U     /*Outer and Inner write-back, no write-allocate non shareable*/
+#define NORM_SHARED_WB_NWA      0x00000007U     /*Outer and Inner write-back, no write-allocate shareable*/
 
-#define NORM_NSHARED_NCACHE 	0x00000008U 	/*Outer and Inner Non cacheable  non shareable*/
-#define NORM_SHARED_NCACHE 		0x0000000CU 	/*Outer and Inner Non cacheable shareable*/
+#define NORM_NSHARED_NCACHE     0x00000008U     /*Outer and Inner Non cacheable  non shareable*/
+#define NORM_SHARED_NCACHE      0x0000000CU     /*Outer and Inner Non cacheable shareable*/
 
-#define NORM_NSHARED_WB_WA 		0x0000000BU 	/*Outer and Inner write-back non shared*/
-#define NORM_SHARED_WB_WA 		0x0000000FU 	/*Outer and Inner write-back shared*/
+#define NORM_NSHARED_WB_WA      0x0000000BU     /*Outer and Inner write-back non shared*/
+#define NORM_SHARED_WB_WA       0x0000000FU     /*Outer and Inner write-back shared*/
 
 /* inner and outer cache policies can be combined for different combinations */
 
-#define NORM_IN_POLICY_NCACHE	0x00000020U	/*inner non cacheable*/
-#define NORM_IN_POLICY_WB_WA	0x00000021U	/*inner write back write allocate*/
-#define NORM_IN_POLICY_WT_NWA	0x00000022U	/*inner write through no write allocate*/
-#define NORM_IN_POLICY_WB_NWA	0x00000023U	/*inner write back no write allocate*/
+#define NORM_IN_POLICY_NCACHE   0x00000020U /*inner non cacheable*/
+#define NORM_IN_POLICY_WB_WA    0x00000021U /*inner write back write allocate*/
+#define NORM_IN_POLICY_WT_NWA   0x00000022U /*inner write through no write allocate*/
+#define NORM_IN_POLICY_WB_NWA   0x00000023U /*inner write back no write allocate*/
 
-#define NORM_OUT_POLICY_NCACHE	0x00000020U	/*outer non cacheable*/
-#define NORM_OUT_POLICY_WB_WA	0x00000028U	/*outer write back write allocate*/
-#define NORM_OUT_POLICY_WT_NWA	0x00000030U	/*outer write through no write allocate*/
-#define NORM_OUT_POLICY_WB_NWA	0x00000038U	/*outer write back no write allocate*/
+#define NORM_OUT_POLICY_NCACHE  0x00000020U /*outer non cacheable*/
+#define NORM_OUT_POLICY_WB_WA   0x00000028U /*outer write back write allocate*/
+#define NORM_OUT_POLICY_WT_NWA  0x00000030U /*outer write through no write allocate*/
+#define NORM_OUT_POLICY_WB_NWA  0x00000038U /*outer write back no write allocate*/
 
-#define NO_ACCESS				(0x00000000U<<8U)	/*No access*/
-#define PRIV_RW_USER_NA			(0x00000001U<<8U) /*Privileged access only*/
-#define PRIV_RW_USER_RO			(0x00000002U<<8U) /*Writes in User mode generate permission faults*/
-#define	PRIV_RW_USER_RW			(0x00000003U<<8U)	/*Full Access*/
-#define PRIV_RO_USER_NA			(0x00000005U<<8U) /*Privileged eead only*/
-#define PRIV_RO_USER_RO			(0x00000006U<<8U) /*Privileged/User read-only*/
+#define NO_ACCESS               (0x00000000U<<8U)   /*No access*/
+#define PRIV_RW_USER_NA         (0x00000001U<<8U) /*Privileged access only*/
+#define PRIV_RW_USER_RO         (0x00000002U<<8U) /*Writes in User mode generate permission faults*/
+#define PRIV_RW_USER_RW         (0x00000003U<<8U)   /*Full Access*/
+#define PRIV_RO_USER_NA         (0x00000005U<<8U) /*Privileged eead only*/
+#define PRIV_RO_USER_RO         (0x00000006U<<8U) /*Privileged/User read-only*/
 
-#define EXECUTE_NEVER  			(0x00000001U<<12U)  /* Bit 12*/
+#define EXECUTE_NEVER           (0x00000001U<<12U)  /* Bit 12*/
 
 
 /* CP15 defines */
 
 /* C0 Register defines */
-#define XREG_CP15_MAIN_ID			"p15, 0, %0,  c0,  c0, 0"
-#define XREG_CP15_CACHE_TYPE			"p15, 0, %0,  c0,  c0, 1"
-#define XREG_CP15_TCM_TYPE			"p15, 0, %0,  c0,  c0, 2"
-#define XREG_CP15_TLB_TYPE			"p15, 0, %0,  c0,  c0, 3"
-#define XREG_CP15_MPU_TYPE			"p15, 0, %0,  c0,  c0, 4"
-#define XREG_CP15_MULTI_PROC_AFFINITY		"p15, 0, %0,  c0,  c0, 5"
+#define XREG_CP15_MAIN_ID           "p15, 0, %0,  c0,  c0, 0"
+#define XREG_CP15_CACHE_TYPE            "p15, 0, %0,  c0,  c0, 1"
+#define XREG_CP15_TCM_TYPE          "p15, 0, %0,  c0,  c0, 2"
+#define XREG_CP15_TLB_TYPE          "p15, 0, %0,  c0,  c0, 3"
+#define XREG_CP15_MPU_TYPE          "p15, 0, %0,  c0,  c0, 4"
+#define XREG_CP15_MULTI_PROC_AFFINITY       "p15, 0, %0,  c0,  c0, 5"
 
-#define XREG_CP15_PROC_FEATURE_0		"p15, 0, %0,  c0,  c1, 0"
-#define XREG_CP15_PROC_FEATURE_1		"p15, 0, %0,  c0,  c1, 1"
-#define XREG_CP15_DEBUG_FEATURE_0		"p15, 0, %0,  c0,  c1, 2"
-#define XREG_CP15_MEMORY_FEATURE_0		"p15, 0, %0,  c0,  c1, 4"
-#define XREG_CP15_MEMORY_FEATURE_1		"p15, 0, %0,  c0,  c1, 5"
-#define XREG_CP15_MEMORY_FEATURE_2		"p15, 0, %0,  c0,  c1, 6"
-#define XREG_CP15_MEMORY_FEATURE_3		"p15, 0, %0,  c0,  c1, 7"
+#define XREG_CP15_PROC_FEATURE_0        "p15, 0, %0,  c0,  c1, 0"
+#define XREG_CP15_PROC_FEATURE_1        "p15, 0, %0,  c0,  c1, 1"
+#define XREG_CP15_DEBUG_FEATURE_0       "p15, 0, %0,  c0,  c1, 2"
+#define XREG_CP15_MEMORY_FEATURE_0      "p15, 0, %0,  c0,  c1, 4"
+#define XREG_CP15_MEMORY_FEATURE_1      "p15, 0, %0,  c0,  c1, 5"
+#define XREG_CP15_MEMORY_FEATURE_2      "p15, 0, %0,  c0,  c1, 6"
+#define XREG_CP15_MEMORY_FEATURE_3      "p15, 0, %0,  c0,  c1, 7"
 
-#define XREG_CP15_INST_FEATURE_0		"p15, 0, %0,  c0,  c2, 0"
-#define XREG_CP15_INST_FEATURE_1		"p15, 0, %0,  c0,  c2, 1"
-#define XREG_CP15_INST_FEATURE_2		"p15, 0, %0,  c0,  c2, 2"
-#define XREG_CP15_INST_FEATURE_3		"p15, 0, %0,  c0,  c2, 3"
-#define XREG_CP15_INST_FEATURE_4		"p15, 0, %0,  c0,  c2, 4"
-#define XREG_CP15_INST_FEATURE_5		"p15, 0, %0,  c0,  c2, 5"
+#define XREG_CP15_INST_FEATURE_0        "p15, 0, %0,  c0,  c2, 0"
+#define XREG_CP15_INST_FEATURE_1        "p15, 0, %0,  c0,  c2, 1"
+#define XREG_CP15_INST_FEATURE_2        "p15, 0, %0,  c0,  c2, 2"
+#define XREG_CP15_INST_FEATURE_3        "p15, 0, %0,  c0,  c2, 3"
+#define XREG_CP15_INST_FEATURE_4        "p15, 0, %0,  c0,  c2, 4"
+#define XREG_CP15_INST_FEATURE_5        "p15, 0, %0,  c0,  c2, 5"
 
-#define XREG_CP15_CACHE_SIZE_ID			"p15, 1, %0,  c0,  c0, 0"
-#define XREG_CP15_CACHE_LEVEL_ID		"p15, 1, %0,  c0,  c0, 1"
-#define XREG_CP15_AUXILARY_ID			"p15, 1, %0,  c0,  c0, 7"
+#define XREG_CP15_CACHE_SIZE_ID         "p15, 1, %0,  c0,  c0, 0"
+#define XREG_CP15_CACHE_LEVEL_ID        "p15, 1, %0,  c0,  c0, 1"
+#define XREG_CP15_AUXILARY_ID           "p15, 1, %0,  c0,  c0, 7"
 
-#define XREG_CP15_CACHE_SIZE_SEL		"p15, 2, %0,  c0,  c0, 0"
+#define XREG_CP15_CACHE_SIZE_SEL        "p15, 2, %0,  c0,  c0, 0"
 
 /* C1 Register Defines */
-#define XREG_CP15_SYS_CONTROL			"p15, 0, %0,  c1,  c0, 0"
-#define XREG_CP15_AUX_CONTROL			"p15, 0, %0,  c1,  c0, 1"
-#define XREG_CP15_CP_ACCESS_CONTROL		"p15, 0, %0,  c1,  c0, 2"
+#define XREG_CP15_SYS_CONTROL           "p15, 0, %0,  c1,  c0, 0"
+#define XREG_CP15_AUX_CONTROL           "p15, 0, %0,  c1,  c0, 1"
+#define XREG_CP15_CP_ACCESS_CONTROL     "p15, 0, %0,  c1,  c0, 2"
 
 
 /* XREG_CP15_CONTROL bit defines */
-#define XREG_CP15_CONTROL_TE_BIT		0x40000000U
-#define XREG_CP15_CONTROL_AFE_BIT		0x20000000U
-#define XREG_CP15_CONTROL_TRE_BIT		0x10000000U
-#define XREG_CP15_CONTROL_NMFI_BIT		0x08000000U
-#define XREG_CP15_CONTROL_EE_BIT		0x02000000U
-#define XREG_CP15_CONTROL_HA_BIT		0x00020000U
-#define XREG_CP15_CONTROL_RR_BIT		0x00004000U
-#define XREG_CP15_CONTROL_V_BIT			0x00002000U
-#define XREG_CP15_CONTROL_I_BIT			0x00001000U
-#define XREG_CP15_CONTROL_Z_BIT			0x00000800U
-#define XREG_CP15_CONTROL_SW_BIT		0x00000400U
-#define XREG_CP15_CONTROL_B_BIT			0x00000080U
-#define XREG_CP15_CONTROL_C_BIT			0x00000004U
-#define XREG_CP15_CONTROL_A_BIT			0x00000002U
-#define XREG_CP15_CONTROL_M_BIT			0x00000001U
+#define XREG_CP15_CONTROL_TE_BIT        0x40000000U
+#define XREG_CP15_CONTROL_AFE_BIT       0x20000000U
+#define XREG_CP15_CONTROL_TRE_BIT       0x10000000U
+#define XREG_CP15_CONTROL_NMFI_BIT      0x08000000U
+#define XREG_CP15_CONTROL_EE_BIT        0x02000000U
+#define XREG_CP15_CONTROL_HA_BIT        0x00020000U
+#define XREG_CP15_CONTROL_RR_BIT        0x00004000U
+#define XREG_CP15_CONTROL_V_BIT         0x00002000U
+#define XREG_CP15_CONTROL_I_BIT         0x00001000U
+#define XREG_CP15_CONTROL_Z_BIT         0x00000800U
+#define XREG_CP15_CONTROL_SW_BIT        0x00000400U
+#define XREG_CP15_CONTROL_B_BIT         0x00000080U
+#define XREG_CP15_CONTROL_C_BIT         0x00000004U
+#define XREG_CP15_CONTROL_A_BIT         0x00000002U
+#define XREG_CP15_CONTROL_M_BIT         0x00000001U
 /* C2 Register Defines */
 /* Not Used */
 
@@ -241,55 +241,55 @@ extern "C" {
 /* Not Used */
 
 /* C5 Register Defines */
-#define XREG_CP15_DATA_FAULT_STATUS		"p15, 0, %0,  c5,  c0, 0"
-#define XREG_CP15_INST_FAULT_STATUS		"p15, 0, %0,  c5,  c0, 1"
+#define XREG_CP15_DATA_FAULT_STATUS     "p15, 0, %0,  c5,  c0, 0"
+#define XREG_CP15_INST_FAULT_STATUS     "p15, 0, %0,  c5,  c0, 1"
 
-#define XREG_CP15_AUX_DATA_FAULT_STATUS		"p15, 0, %0,  c5,  c1, 0"
-#define XREG_CP15_AUX_INST_FAULT_STATUS		"p15, 0, %0,  c5,  c1, 1"
+#define XREG_CP15_AUX_DATA_FAULT_STATUS     "p15, 0, %0,  c5,  c1, 0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS     "p15, 0, %0,  c5,  c1, 1"
 
 /* C6 Register Defines */
-#define XREG_CP15_DATA_FAULT_ADDRESS		"p15, 0, %0,  c6,  c0, 0"
-#define XREG_CP15_INST_FAULT_ADDRESS		"p15, 0, %0,  c6,  c0, 2"
+#define XREG_CP15_DATA_FAULT_ADDRESS        "p15, 0, %0,  c6,  c0, 0"
+#define XREG_CP15_INST_FAULT_ADDRESS        "p15, 0, %0,  c6,  c0, 2"
 
-#define XREG_CP15_MPU_REG_BASEADDR			"p15, 0, %0,  c6,  c1, 0"
-#define XREG_CP15_MPU_REG_SIZE_EN			"p15, 0, %0,  c6,  c1, 2"
-#define XREG_CP15_MPU_REG_ACCESS_CTRL		"p15, 0, %0,  c6,  c1, 4"
+#define XREG_CP15_MPU_REG_BASEADDR          "p15, 0, %0,  c6,  c1, 0"
+#define XREG_CP15_MPU_REG_SIZE_EN           "p15, 0, %0,  c6,  c1, 2"
+#define XREG_CP15_MPU_REG_ACCESS_CTRL       "p15, 0, %0,  c6,  c1, 4"
 
-#define XREG_CP15_MPU_MEMORY_REG_NUMBER			"p15, 0, %0,  c6,  c2, 0"
+#define XREG_CP15_MPU_MEMORY_REG_NUMBER         "p15, 0, %0,  c6,  c2, 0"
 
 /* C7 Register Defines */
-#define XREG_CP15_NOP				"p15, 0, %0,  c7,  c0, 4"
+#define XREG_CP15_NOP               "p15, 0, %0,  c7,  c0, 4"
 
-#define XREG_CP15_INVAL_IC_POU			"p15, 0, %0,  c7,  c5, 0"
-#define XREG_CP15_INVAL_IC_LINE_MVA_POU		"p15, 0, %0,  c7,  c5, 1"
+#define XREG_CP15_INVAL_IC_POU          "p15, 0, %0,  c7,  c5, 0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU     "p15, 0, %0,  c7,  c5, 1"
 
 /* The CP15 register access below has been deprecated in favor of the new
  * isb instruction in Cortex R5.
  */
-#define XREG_CP15_INST_SYNC_BARRIER		"p15, 0, %0,  c7,  c5, 4"
-#define XREG_CP15_INVAL_BRANCH_ARRAY		"p15, 0, %0,  c7,  c5, 6"
-#define XREG_CP15_INVAL_BRANCH_ARRAY_LINE		"p15, 0, %0,  c7,  c5, 7"
+#define XREG_CP15_INST_SYNC_BARRIER     "p15, 0, %0,  c7,  c5, 4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY        "p15, 0, %0,  c7,  c5, 6"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_LINE       "p15, 0, %0,  c7,  c5, 7"
 
-#define XREG_CP15_INVAL_DC_LINE_MVA_POC		"p15, 0, %0,  c7,  c6, 1"
-#define XREG_CP15_INVAL_DC_LINE_SW		"p15, 0, %0,  c7,  c6, 2"
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC     "p15, 0, %0,  c7,  c6, 1"
+#define XREG_CP15_INVAL_DC_LINE_SW      "p15, 0, %0,  c7,  c6, 2"
 
 
-#define XREG_CP15_CLEAN_DC_LINE_MVA_POC		"p15, 0, %0,  c7, c10, 1"
-#define XREG_CP15_CLEAN_DC_LINE_SW		"p15, 0, %0,  c7, c10, 2"
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC     "p15, 0, %0,  c7, c10, 1"
+#define XREG_CP15_CLEAN_DC_LINE_SW      "p15, 0, %0,  c7, c10, 2"
 
-#define XREG_CP15_INVAL_DC_ALL		"p15, 0, %0,  c15, c5, 0"
+#define XREG_CP15_INVAL_DC_ALL      "p15, 0, %0,  c15, c5, 0"
 /* The next two CP15 register accesses below have been deprecated in favor
  * of the new dsb and dmb instructions in Cortex R5.
  */
-#define XREG_CP15_DATA_SYNC_BARRIER		"p15, 0, %0,  c7, c10, 4"
-#define XREG_CP15_DATA_MEMORY_BARRIER		"p15, 0, %0,  c7, c10, 5"
+#define XREG_CP15_DATA_SYNC_BARRIER     "p15, 0, %0,  c7, c10, 4"
+#define XREG_CP15_DATA_MEMORY_BARRIER       "p15, 0, %0,  c7, c10, 5"
 
-#define XREG_CP15_CLEAN_DC_LINE_MVA_POU		"p15, 0, %0,  c7, c11, 1"
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU     "p15, 0, %0,  c7, c11, 1"
 
-#define XREG_CP15_NOP2				"p15, 0, %0,  c7, c13, 1"
+#define XREG_CP15_NOP2              "p15, 0, %0,  c7, c13, 1"
 
-#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC	"p15, 0, %0,  c7, c14, 1"
-#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW	"p15, 0, %0,  c7, c14, 2"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC   "p15, 0, %0,  c7, c14, 1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW    "p15, 0, %0,  c7, c14, 2"
 
 /* C8 Register Defines */
 /* Not Used */
@@ -297,24 +297,24 @@ extern "C" {
 
 /* C9 Register Defines */
 
-#define XREG_CP15_ATCM_REG_SIZE_ADDR		"p15, 0, %0,  c9, c1, 1"
-#define XREG_CP15_BTCM_REG_SIZE_ADDR		"p15, 0, %0,  c9, c1, 0"
-#define XREG_CP15_TCM_SELECTION				"p15, 0, %0,  c9, c2, 0"
+#define XREG_CP15_ATCM_REG_SIZE_ADDR        "p15, 0, %0,  c9, c1, 1"
+#define XREG_CP15_BTCM_REG_SIZE_ADDR        "p15, 0, %0,  c9, c1, 0"
+#define XREG_CP15_TCM_SELECTION             "p15, 0, %0,  c9, c2, 0"
 
-#define XREG_CP15_PERF_MONITOR_CTRL		"p15, 0, %0,  c9, c12, 0"
-#define XREG_CP15_COUNT_ENABLE_SET		"p15, 0, %0,  c9, c12, 1"
-#define XREG_CP15_COUNT_ENABLE_CLR		"p15, 0, %0,  c9, c12, 2"
-#define XREG_CP15_V_FLAG_STATUS			"p15, 0, %0,  c9, c12, 3"
-#define XREG_CP15_SW_INC			"p15, 0, %0,  c9, c12, 4"
-#define XREG_CP15_EVENT_CNTR_SEL		"p15, 0, %0,  c9, c12, 5"
+#define XREG_CP15_PERF_MONITOR_CTRL     "p15, 0, %0,  c9, c12, 0"
+#define XREG_CP15_COUNT_ENABLE_SET      "p15, 0, %0,  c9, c12, 1"
+#define XREG_CP15_COUNT_ENABLE_CLR      "p15, 0, %0,  c9, c12, 2"
+#define XREG_CP15_V_FLAG_STATUS         "p15, 0, %0,  c9, c12, 3"
+#define XREG_CP15_SW_INC            "p15, 0, %0,  c9, c12, 4"
+#define XREG_CP15_EVENT_CNTR_SEL        "p15, 0, %0,  c9, c12, 5"
 
-#define XREG_CP15_PERF_CYCLE_COUNTER		"p15, 0, %0,  c9, c13, 0"
-#define XREG_CP15_EVENT_TYPE_SEL		"p15, 0, %0,  c9, c13, 1"
-#define XREG_CP15_PERF_MONITOR_COUNT		"p15, 0, %0,  c9, c13, 2"
+#define XREG_CP15_PERF_CYCLE_COUNTER        "p15, 0, %0,  c9, c13, 0"
+#define XREG_CP15_EVENT_TYPE_SEL        "p15, 0, %0,  c9, c13, 1"
+#define XREG_CP15_PERF_MONITOR_COUNT        "p15, 0, %0,  c9, c13, 2"
 
-#define XREG_CP15_USER_ENABLE			"p15, 0, %0,  c9, c14, 0"
-#define XREG_CP15_INTR_ENABLE_SET		"p15, 0, %0,  c9, c14, 1"
-#define XREG_CP15_INTR_ENABLE_CLR		"p15, 0, %0,  c9, c14, 2"
+#define XREG_CP15_USER_ENABLE           "p15, 0, %0,  c9, c14, 0"
+#define XREG_CP15_INTR_ENABLE_SET       "p15, 0, %0,  c9, c14, 1"
+#define XREG_CP15_INTR_ENABLE_CLR       "p15, 0, %0,  c9, c14, 2"
 
 /* C10 Register Defines */
 /* Not used */
@@ -326,90 +326,90 @@ extern "C" {
 /* Not used */
 
 /* C13 Register Defines */
-#define XREG_CP15_CONTEXT_ID			"p15, 0, %0, c13,  c0, 1"
-#define USER_RW_THREAD_PID			"p15, 0, %0, c13,  c0, 2"
-#define USER_RO_THREAD_PID			"p15, 0, %0, c13,  c0, 3"
-#define USER_PRIV_THREAD_PID			"p15, 0, %0, c13,  c0, 4"
+#define XREG_CP15_CONTEXT_ID            "p15, 0, %0, c13,  c0, 1"
+#define USER_RW_THREAD_PID          "p15, 0, %0, c13,  c0, 2"
+#define USER_RO_THREAD_PID          "p15, 0, %0, c13,  c0, 3"
+#define USER_PRIV_THREAD_PID            "p15, 0, %0, c13,  c0, 4"
 
 /* C14 Register Defines */
 /* not used */
 
 /* C15 Register Defines */
-#define XREG_CP15_SEC_AUX_CTRL			"p15, 0, %0, c15,  c0, 0"
+#define XREG_CP15_SEC_AUX_CTRL          "p15, 0, %0, c15,  c0, 0"
 
 
 
 
 /* MPE register definitions */
-#define XREG_FPSID				c0
-#define XREG_FPSCR				c1
-#define XREG_MVFR1				c6
-#define XREG_MVFR0				c7
-#define XREG_FPEXC				c8
-#define XREG_FPINST				c9
-#define XREG_FPINST2			c10
+#define XREG_FPSID              c0
+#define XREG_FPSCR              c1
+#define XREG_MVFR1              c6
+#define XREG_MVFR0              c7
+#define XREG_FPEXC              c8
+#define XREG_FPINST             c9
+#define XREG_FPINST2            c10
 
 /* FPSID bits */
-#define XREG_FPSID_IMPLEMENTER_BIT	(24U)
-#define XREG_FPSID_IMPLEMENTER_MASK	(0x000000FFU << FPSID_IMPLEMENTER_BIT)
-#define XREG_FPSID_SOFTWARE		(0X00000001U << 23U)
-#define XREG_FPSID_ARCH_BIT		(16U)
-#define XREG_FPSID_ARCH_MASK		(0x0000000FU  << FPSID_ARCH_BIT)
-#define XREG_FPSID_PART_BIT		(8U)
-#define XREG_FPSID_PART_MASK		(0x000000FFU << FPSID_PART_BIT)
-#define XREG_FPSID_VARIANT_BIT		(4U)
-#define XREG_FPSID_VARIANT_MASK		(0x0000000FU  << FPSID_VARIANT_BIT)
-#define XREG_FPSID_REV_BIT		(0U)
-#define XREG_FPSID_REV_MASK		(0x0000000FU  << FPSID_REV_BIT)
+#define XREG_FPSID_IMPLEMENTER_BIT  (24U)
+#define XREG_FPSID_IMPLEMENTER_MASK (0x000000FFU << FPSID_IMPLEMENTER_BIT)
+#define XREG_FPSID_SOFTWARE     (0X00000001U << 23U)
+#define XREG_FPSID_ARCH_BIT     (16U)
+#define XREG_FPSID_ARCH_MASK        (0x0000000FU  << FPSID_ARCH_BIT)
+#define XREG_FPSID_PART_BIT     (8U)
+#define XREG_FPSID_PART_MASK        (0x000000FFU << FPSID_PART_BIT)
+#define XREG_FPSID_VARIANT_BIT      (4U)
+#define XREG_FPSID_VARIANT_MASK     (0x0000000FU  << FPSID_VARIANT_BIT)
+#define XREG_FPSID_REV_BIT      (0U)
+#define XREG_FPSID_REV_MASK     (0x0000000FU  << FPSID_REV_BIT)
 
 /* FPSCR bits */
-#define XREG_FPSCR_N_BIT		(0X00000001U << 31U)
-#define XREG_FPSCR_Z_BIT		(0X00000001U << 30U)
-#define XREG_FPSCR_C_BIT		(0X00000001U << 29U)
-#define XREG_FPSCR_V_BIT		(0X00000001U << 28U)
-#define XREG_FPSCR_QC			(0X00000001U << 27U)
-#define XREG_FPSCR_AHP			(0X00000001U << 26U)
-#define XREG_FPSCR_DEFAULT_NAN		(0X00000001U << 25U)
-#define XREG_FPSCR_FLUSHTOZERO		(0X00000001U << 24U)
-#define XREG_FPSCR_ROUND_NEAREST	(0X00000000U << 22U)
-#define XREG_FPSCR_ROUND_PLUSINF	(0X00000001U << 22U)
-#define XREG_FPSCR_ROUND_MINUSINF	(0X00000002U << 22U)
-#define XREG_FPSCR_ROUND_TOZERO		(0X00000003U << 22U)
-#define XREG_FPSCR_RMODE_BIT		(22U)
-#define XREG_FPSCR_RMODE_MASK		(0X00000003U << FPSCR_RMODE_BIT)
-#define XREG_FPSCR_STRIDE_BIT		(20U)
-#define XREG_FPSCR_STRIDE_MASK		(0X00000003U << FPSCR_STRIDE_BIT)
-#define XREG_FPSCR_LENGTH_BIT		(16U)
-#define XREG_FPSCR_LENGTH_MASK		(0X00000007U << FPSCR_LENGTH_BIT)
-#define XREG_FPSCR_IDC			(0X00000001U << 7U)
-#define XREG_FPSCR_IXC			(0X00000001U << 4U)
-#define XREG_FPSCR_UFC			(0X00000001U << 3U)
-#define XREG_FPSCR_OFC			(0X00000001U << 2U)
-#define XREG_FPSCR_DZC			(0X00000001U << 1U)
-#define XREG_FPSCR_IOC			(0X00000001U << 0U)
+#define XREG_FPSCR_N_BIT        (0X00000001U << 31U)
+#define XREG_FPSCR_Z_BIT        (0X00000001U << 30U)
+#define XREG_FPSCR_C_BIT        (0X00000001U << 29U)
+#define XREG_FPSCR_V_BIT        (0X00000001U << 28U)
+#define XREG_FPSCR_QC           (0X00000001U << 27U)
+#define XREG_FPSCR_AHP          (0X00000001U << 26U)
+#define XREG_FPSCR_DEFAULT_NAN      (0X00000001U << 25U)
+#define XREG_FPSCR_FLUSHTOZERO      (0X00000001U << 24U)
+#define XREG_FPSCR_ROUND_NEAREST    (0X00000000U << 22U)
+#define XREG_FPSCR_ROUND_PLUSINF    (0X00000001U << 22U)
+#define XREG_FPSCR_ROUND_MINUSINF   (0X00000002U << 22U)
+#define XREG_FPSCR_ROUND_TOZERO     (0X00000003U << 22U)
+#define XREG_FPSCR_RMODE_BIT        (22U)
+#define XREG_FPSCR_RMODE_MASK       (0X00000003U << FPSCR_RMODE_BIT)
+#define XREG_FPSCR_STRIDE_BIT       (20U)
+#define XREG_FPSCR_STRIDE_MASK      (0X00000003U << FPSCR_STRIDE_BIT)
+#define XREG_FPSCR_LENGTH_BIT       (16U)
+#define XREG_FPSCR_LENGTH_MASK      (0X00000007U << FPSCR_LENGTH_BIT)
+#define XREG_FPSCR_IDC          (0X00000001U << 7U)
+#define XREG_FPSCR_IXC          (0X00000001U << 4U)
+#define XREG_FPSCR_UFC          (0X00000001U << 3U)
+#define XREG_FPSCR_OFC          (0X00000001U << 2U)
+#define XREG_FPSCR_DZC          (0X00000001U << 1U)
+#define XREG_FPSCR_IOC          (0X00000001U << 0U)
 
 /* MVFR0 bits */
-#define XREG_MVFR0_RMODE_BIT		(28U)
-#define XREG_MVFR0_RMODE_MASK		(0x0000000FU << XREG_MVFR0_RMODE_BIT)
-#define XREG_MVFR0_SHORT_VEC_BIT	(24U)
-#define XREG_MVFR0_SHORT_VEC_MASK	(0x0000000FU << XREG_MVFR0_SHORT_VEC_BIT)
-#define XREG_MVFR0_SQRT_BIT		(20U)
-#define XREG_MVFR0_SQRT_MASK		(0x0000000FU << XREG_MVFR0_SQRT_BIT)
-#define XREG_MVFR0_DIVIDE_BIT		(16U)
-#define XREG_MVFR0_DIVIDE_MASK		(0x0000000FU << XREG_MVFR0_DIVIDE_BIT)
-#define XREG_MVFR0_EXEC_TRAP_BIT	(12U)
-#define XREG_MVFR0_EXEC_TRAP_MASK	(0x0000000FU << XREG_MVFR0_EXEC_TRAP_BIT)
-#define XREG_MVFR0_DP_BIT		(8U)
-#define XREG_MVFR0_DP_MASK		(0x0000000FU << XREG_MVFR0_DP_BIT)
-#define XREG_MVFR0_SP_BIT		(4U)
-#define XREG_MVFR0_SP_MASK		(0x0000000FU << XREG_MVFR0_SP_BIT)
-#define XREG_MVFR0_A_SIMD_BIT		(0U)
-#define XREG_MVFR0_A_SIMD_MASK		(0x0000000FU << MVFR0_A_SIMD_BIT)
+#define XREG_MVFR0_RMODE_BIT        (28U)
+#define XREG_MVFR0_RMODE_MASK       (0x0000000FU << XREG_MVFR0_RMODE_BIT)
+#define XREG_MVFR0_SHORT_VEC_BIT    (24U)
+#define XREG_MVFR0_SHORT_VEC_MASK   (0x0000000FU << XREG_MVFR0_SHORT_VEC_BIT)
+#define XREG_MVFR0_SQRT_BIT     (20U)
+#define XREG_MVFR0_SQRT_MASK        (0x0000000FU << XREG_MVFR0_SQRT_BIT)
+#define XREG_MVFR0_DIVIDE_BIT       (16U)
+#define XREG_MVFR0_DIVIDE_MASK      (0x0000000FU << XREG_MVFR0_DIVIDE_BIT)
+#define XREG_MVFR0_EXEC_TRAP_BIT    (12U)
+#define XREG_MVFR0_EXEC_TRAP_MASK   (0x0000000FU << XREG_MVFR0_EXEC_TRAP_BIT)
+#define XREG_MVFR0_DP_BIT       (8U)
+#define XREG_MVFR0_DP_MASK      (0x0000000FU << XREG_MVFR0_DP_BIT)
+#define XREG_MVFR0_SP_BIT       (4U)
+#define XREG_MVFR0_SP_MASK      (0x0000000FU << XREG_MVFR0_SP_BIT)
+#define XREG_MVFR0_A_SIMD_BIT       (0U)
+#define XREG_MVFR0_A_SIMD_MASK      (0x0000000FU << MVFR0_A_SIMD_BIT)
 
 /* FPEXC bits */
-#define XREG_FPEXC_EX			(0X00000001U << 31U)
-#define XREG_FPEXC_EN			(0X00000001U << 30U)
-#define XREG_FPEXC_DEX			(0X00000001U << 29U)
+#define XREG_FPEXC_EX           (0X00000001U << 31U)
+#define XREG_FPEXC_EN           (0X00000001U << 30U)
+#define XREG_FPEXC_DEX          (0X00000001U << 29U)
 
 
 #ifdef __cplusplus
diff --git a/libcpu/avr32/uc3/cpu.c b/libcpu/avr32/uc3/cpu.c
index fdd8a4d56c..1d4ea5adfa 100644
--- a/libcpu/avr32/uc3/cpu.c
+++ b/libcpu/avr32/uc3/cpu.c
@@ -25,7 +25,7 @@
  */
 RT_WEAK void rt_hw_cpu_reset()
 {
-	/*NOTREACHED*/
+    /*NOTREACHED*/
 }
 
 /**
@@ -34,9 +34,9 @@ RT_WEAK void rt_hw_cpu_reset()
  */
 void rt_hw_cpu_shutdown()
 {
-	rt_kprintf("shutdown...\n");
+    rt_kprintf("shutdown...\n");
 
-	RT_ASSERT(0);
+    RT_ASSERT(0);
 }
 
 /*@}*/
diff --git a/libcpu/avr32/uc3/serial.c b/libcpu/avr32/uc3/serial.c
index 14ef865448..66fb6ca8b9 100644
--- a/libcpu/avr32/uc3/serial.c
+++ b/libcpu/avr32/uc3/serial.c
@@ -24,8 +24,8 @@ struct rt_device _rt_usart_device;
 struct avr32_serial_int_rx _rt_usart_rx;
 struct avr32_serial_device uart =
 {
-	.uart_device = (avr32_usart_t *) &AVR32_USART1,
-	.int_rx = &_rt_usart_rx
+    .uart_device = (avr32_usart_t *) &AVR32_USART1,
+    .int_rx = &_rt_usart_rx
 };
 
 /**
@@ -36,163 +36,163 @@ struct avr32_serial_device uart =
 /* RT-Thread Device Interface */
 static rt_err_t rt_serial_init (rt_device_t dev)
 {
-	struct avr32_serial_device* uart = (struct avr32_serial_device*) dev->user_data;
+    struct avr32_serial_device* uart = (struct avr32_serial_device*) dev->user_data;
 
-	if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
-	{
-		if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-		{
-			rt_memset(uart->int_rx->rx_buffer, 0, sizeof(uart->int_rx->rx_buffer));
-			uart->int_rx->read_index = 0;
-			uart->int_rx->save_index = 0;
-		}
+    if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
+    {
+        if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+        {
+            rt_memset(uart->int_rx->rx_buffer, 0, sizeof(uart->int_rx->rx_buffer));
+            uart->int_rx->read_index = 0;
+            uart->int_rx->save_index = 0;
+        }
 
-		dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
-	}
+        dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_serial_close(rt_device_t dev)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
 {
-	rt_uint8_t* ptr;
-	rt_err_t err_code;
-	struct avr32_serial_device* uart;
+    rt_uint8_t* ptr;
+    rt_err_t err_code;
+    struct avr32_serial_device* uart;
 
-	ptr = buffer;
-	err_code = RT_EOK;
-	uart = (struct avr32_serial_device*)dev->user_data;
+    ptr = buffer;
+    err_code = RT_EOK;
+    uart = (struct avr32_serial_device*)dev->user_data;
 
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* interrupt mode Rx */
-		while (size)
-		{
-			rt_base_t level;
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* interrupt mode Rx */
+        while (size)
+        {
+            rt_base_t level;
 
-			/* disable interrupt */
-			level = rt_hw_interrupt_disable();
+            /* disable interrupt */
+            level = rt_hw_interrupt_disable();
 
-			if (uart->int_rx->read_index != uart->int_rx->save_index)
-			{
-				/* read a character */
-				*ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index];
-				size--;
+            if (uart->int_rx->read_index != uart->int_rx->save_index)
+            {
+                /* read a character */
+                *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index];
+                size--;
 
-				/* move to next position */
-				uart->int_rx->read_index ++;
-				if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
-					uart->int_rx->read_index = 0;
-			}
-			else
-			{
-				/* set error code */
-				err_code = -RT_EEMPTY;
+                /* move to next position */
+                uart->int_rx->read_index ++;
+                if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+                    uart->int_rx->read_index = 0;
+            }
+            else
+            {
+                /* set error code */
+                err_code = -RT_EEMPTY;
 
-				/* enable interrupt */
-				rt_hw_interrupt_enable(level);
-				break;
-			}
+                /* enable interrupt */
+                rt_hw_interrupt_enable(level);
+                break;
+            }
 
-			/* enable interrupt */
-			rt_hw_interrupt_enable(level);
-		}
-	}
-	else
-	{
-		/* polling mode */
-		while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
-		{
-			while (usart_test_hit(uart->uart_device))
-			{
-				*ptr = uart->uart_device->rhr & 0xff;
-				ptr ++;
-			}
-		}
-	}
+            /* enable interrupt */
+            rt_hw_interrupt_enable(level);
+        }
+    }
+    else
+    {
+        /* polling mode */
+        while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
+        {
+            while (usart_test_hit(uart->uart_device))
+            {
+                *ptr = uart->uart_device->rhr & 0xff;
+                ptr ++;
+            }
+        }
+    }
 
-	/* set error code */
-	rt_set_errno(err_code);
-	return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+    /* set error code */
+    rt_set_errno(err_code);
+    return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
 }
 
 static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
 {
-	rt_uint8_t* ptr;
-	rt_err_t err_code;
-	struct avr32_serial_device* uart;
+    rt_uint8_t* ptr;
+    rt_err_t err_code;
+    struct avr32_serial_device* uart;
 
-	err_code = RT_EOK;
-	ptr = (rt_uint8_t*)buffer;
-	uart = (struct avr32_serial_device*)dev->user_data;
+    err_code = RT_EOK;
+    ptr = (rt_uint8_t*)buffer;
+    uart = (struct avr32_serial_device*)dev->user_data;
 
-	if (dev->flag & RT_DEVICE_FLAG_INT_TX)
-	{
-		/* interrupt mode Tx, does not support */
-		RT_ASSERT(0);
-	}
-	else
-	{
-		/* polling mode */
-		if (dev->flag & RT_DEVICE_FLAG_STREAM)
-		{
-			/* stream mode */
-			while (size)
-			{
-				usart_putchar(uart->uart_device, (int) *ptr);
+    if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+    {
+        /* interrupt mode Tx, does not support */
+        RT_ASSERT(0);
+    }
+    else
+    {
+        /* polling mode */
+        if (dev->flag & RT_DEVICE_FLAG_STREAM)
+        {
+            /* stream mode */
+            while (size)
+            {
+                usart_putchar(uart->uart_device, (int) *ptr);
 
-				++ptr; --size;
-			}
-		}
-		else
-		{
-			/* write data directly */
-			while (size)
-			{
-				usart_bw_write_char(uart->uart_device, (int) *ptr);
+                ++ptr; --size;
+            }
+        }
+        else
+        {
+            /* write data directly */
+            while (size)
+            {
+                usart_bw_write_char(uart->uart_device, (int) *ptr);
 
-				++ptr; --size;
-			}
-		}
-	}
+                ++ptr; --size;
+            }
+        }
+    }
 
-	/* set error code */
-	rt_set_errno(err_code);
+    /* set error code */
+    rt_set_errno(err_code);
 
-	return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+    return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
 }
 
 static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args)
 {
-	struct avr32_serial_device* uart;
+    struct avr32_serial_device* uart;
 
-	RT_ASSERT(dev != RT_NULL);
+    RT_ASSERT(dev != RT_NULL);
 
-	uart = (struct avr32_serial_device*)dev->user_data;
-	switch (cmd)
-	{
-	case RT_DEVICE_CTRL_SUSPEND:
-		/* suspend device */
-		dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
-		break;
+    uart = (struct avr32_serial_device*)dev->user_data;
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_SUSPEND:
+        /* suspend device */
+        dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
+        break;
 
-	case RT_DEVICE_CTRL_RESUME:
-		/* resume device */
-		dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
-		break;
-	}
+    case RT_DEVICE_CTRL_RESUME:
+        /* resume device */
+        dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
+        break;
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 /*
@@ -201,77 +201,77 @@ static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args)
  */
 rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct avr32_serial_device *serial)
 {
-	RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(device != RT_NULL);
 
-	if ((flag & RT_DEVICE_FLAG_DMA_RX) ||
-		(flag & RT_DEVICE_FLAG_INT_TX))
-	{
-		RT_ASSERT(0);
-	}
+    if ((flag & RT_DEVICE_FLAG_DMA_RX) ||
+        (flag & RT_DEVICE_FLAG_INT_TX))
+    {
+        RT_ASSERT(0);
+    }
 
-	device->type 		= RT_Device_Class_Char;
-	device->rx_indicate = RT_NULL;
-	device->tx_complete = RT_NULL;
-	device->init 		= rt_serial_init;
-	device->open		= rt_serial_open;
-	device->close		= rt_serial_close;
-	device->read 		= rt_serial_read;
-	device->write 		= rt_serial_write;
-	device->control 	= rt_serial_control;
-	device->user_data	= serial;
+    device->type        = RT_Device_Class_Char;
+    device->rx_indicate = RT_NULL;
+    device->tx_complete = RT_NULL;
+    device->init        = rt_serial_init;
+    device->open        = rt_serial_open;
+    device->close       = rt_serial_close;
+    device->read        = rt_serial_read;
+    device->write       = rt_serial_write;
+    device->control     = rt_serial_control;
+    device->user_data   = serial;
 
-	/* register a character device */
-	return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
+    /* register a character device */
+    return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
 }
 
 /* ISR for serial interrupt */
 void rt_hw_serial_isr(void)
 {
-	struct avr32_serial_device* uart = (struct avr32_serial_device*) _rt_usart_device.user_data;
-	rt_base_t level;
+    struct avr32_serial_device* uart = (struct avr32_serial_device*) _rt_usart_device.user_data;
+    rt_base_t level;
 
-	if (usart_test_hit(uart->uart_device))
-	{
-		/* interrupt mode receive */
-		RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
+    if (usart_test_hit(uart->uart_device))
+    {
+        /* interrupt mode receive */
+        RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
 
-		/* disable interrupt */
-		level = rt_hw_interrupt_disable();
+        /* disable interrupt */
+        level = rt_hw_interrupt_disable();
 
-		/* save character */
-		uart->int_rx->rx_buffer[uart->int_rx->save_index] = uart->uart_device->rhr & 0xff;
-		uart->int_rx->save_index ++;
-		if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
-			uart->int_rx->save_index = 0;
+        /* save character */
+        uart->int_rx->rx_buffer[uart->int_rx->save_index] = uart->uart_device->rhr & 0xff;
+        uart->int_rx->save_index ++;
+        if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
+            uart->int_rx->save_index = 0;
 
-		/* if the next position is read index, discard this 'read char' */
-		if (uart->int_rx->save_index == uart->int_rx->read_index)
-		{
-			uart->int_rx->read_index ++;
-			if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
-				uart->int_rx->read_index = 0;
-		}
+        /* if the next position is read index, discard this 'read char' */
+        if (uart->int_rx->save_index == uart->int_rx->read_index)
+        {
+            uart->int_rx->read_index ++;
+            if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+                uart->int_rx->read_index = 0;
+        }
 
-		/* enable interrupt */
-		rt_hw_interrupt_enable(level);
+        /* enable interrupt */
+        rt_hw_interrupt_enable(level);
 
-		/* invoke callback */
-		if (_rt_usart_device.rx_indicate != RT_NULL)
-		{
-			rt_size_t rx_length;
+        /* invoke callback */
+        if (_rt_usart_device.rx_indicate != RT_NULL)
+        {
+            rt_size_t rx_length;
 
-			/* get rx length */
-			rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
-				UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
-				uart->int_rx->save_index - uart->int_rx->read_index;
+            /* get rx length */
+            rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
+                UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
+                uart->int_rx->save_index - uart->int_rx->read_index;
 
-			_rt_usart_device.rx_indicate(&_rt_usart_device, rx_length);
-		}
-	}
-	else
-	{
-		usart_reset_status(uart->uart_device);
-	}
+            _rt_usart_device.rx_indicate(&_rt_usart_device, rx_length);
+        }
+    }
+    else
+    {
+        usart_reset_status(uart->uart_device);
+    }
 }
 
 /*@}*/
diff --git a/libcpu/avr32/uc3/serial.h b/libcpu/avr32/uc3/serial.h
index a17338701b..fef65a12be 100644
--- a/libcpu/avr32/uc3/serial.h
+++ b/libcpu/avr32/uc3/serial.h
@@ -21,29 +21,29 @@
 #include "compiler.h"
 #include "usart.h"
 
-#define UART_RX_BUFFER_SIZE		64
-#define UART_TX_DMA_NODE_SIZE	4
+#define UART_RX_BUFFER_SIZE     64
+#define UART_TX_DMA_NODE_SIZE   4
 
 /* data node for Tx Mode */
 struct avr32_serial_data_node
 {
-	rt_uint8_t *data_ptr;
-	rt_size_t  data_size;
-	struct avr32_serial_data_node *next, *prev;
+    rt_uint8_t *data_ptr;
+    rt_size_t  data_size;
+    struct avr32_serial_data_node *next, *prev;
 };
 
 struct avr32_serial_int_rx
 {
-	rt_uint8_t  rx_buffer[UART_RX_BUFFER_SIZE];
-	rt_uint32_t read_index, save_index;
+    rt_uint8_t  rx_buffer[UART_RX_BUFFER_SIZE];
+    rt_uint32_t read_index, save_index;
 };
 
 struct avr32_serial_device
 {
-	avr32_usart_t *uart_device;
+    avr32_usart_t *uart_device;
 
-	/* rx structure */
-	struct avr32_serial_int_rx* int_rx;
+    /* rx structure */
+    struct avr32_serial_int_rx* int_rx;
 };
 
 rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct avr32_serial_device *serial);
diff --git a/libcpu/avr32/uc3/stack.c b/libcpu/avr32/uc3/stack.c
index dd43b5edbc..dee1161c12 100644
--- a/libcpu/avr32/uc3/stack.c
+++ b/libcpu/avr32/uc3/stack.c
@@ -30,28 +30,28 @@
  */
 rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
 {
-	unsigned long *stk;
+    unsigned long *stk;
 
-	stk 	 = (unsigned long *)stack_addr;
-	*(stk)   = 0;							/* r8 */
-	*(--stk) = 0;							/* r9 */
-	*(--stk) = 0;							/* r10 */
-	*(--stk) = 0;							/* r11 */
-	*(--stk) = 0;							/* r12 */
-	*(--stk) = (unsigned long)texit;		/* lr */
-	*(--stk) = (unsigned long)tentry;		/* entry point, pc */
-	*(--stk) = 0x00600000;					/* sr */
-	*(--stk) = 0;							/* r0 */
-	*(--stk) = 0;							/* r1 */
-	*(--stk) = 0;							/* r2 */
-	*(--stk) = 0;							/* r3 */
-	*(--stk) = 0;							/* r4 */
-	*(--stk) = 0;							/* r5 */
-	*(--stk) = 0;							/* r6 */
-	*(--stk) = 0;							/* r7 */
+    stk      = (unsigned long *)stack_addr;
+    *(stk)   = 0;                           /* r8 */
+    *(--stk) = 0;                           /* r9 */
+    *(--stk) = 0;                           /* r10 */
+    *(--stk) = 0;                           /* r11 */
+    *(--stk) = 0;                           /* r12 */
+    *(--stk) = (unsigned long)texit;        /* lr */
+    *(--stk) = (unsigned long)tentry;       /* entry point, pc */
+    *(--stk) = 0x00600000;                  /* sr */
+    *(--stk) = 0;                           /* r0 */
+    *(--stk) = 0;                           /* r1 */
+    *(--stk) = 0;                           /* r2 */
+    *(--stk) = 0;                           /* r3 */
+    *(--stk) = 0;                           /* r4 */
+    *(--stk) = 0;                           /* r5 */
+    *(--stk) = 0;                           /* r6 */
+    *(--stk) = 0;                           /* r7 */
 
-	/* return task's current stack address */
-	return (rt_uint8_t *)stk;
+    /* return task's current stack address */
+    return (rt_uint8_t *)stk;
 }
 
 /*@}*/
diff --git a/libcpu/blackfin/bf53x/cpuport.c b/libcpu/blackfin/bf53x/cpuport.c
index 91cfaeb403..2d69ccc99a 100644
--- a/libcpu/blackfin/bf53x/cpuport.c
+++ b/libcpu/blackfin/bf53x/cpuport.c
@@ -8,8 +8,8 @@
  * http://www.rt-thread.org/license/LICENSE
  *
  * Change Logs:
- * Date			Author		Notes
- * 2012-02-13 	mojingxian 	first version
+ * Date         Author      Notes
+ * 2012-02-13   mojingxian  first version
  */
 
 #include 
@@ -23,10 +23,10 @@ rt_uint32_t rt_thread_switch_interrupt_flag;
  * initializes stack of thread
  */
 rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
-	rt_uint8_t *stack_addr, void *texit)
+    rt_uint8_t *stack_addr, void *texit)
 {
     unsigned char i;
-	unsigned long *stk;
+    unsigned long *stk;
 
     stk    = (unsigned long *)stack_addr;     /* Load stack pointer                                    */
 
diff --git a/libcpu/blackfin/bf53x/serial.c b/libcpu/blackfin/bf53x/serial.c
index b8a4c52570..4a6484a647 100644
--- a/libcpu/blackfin/bf53x/serial.c
+++ b/libcpu/blackfin/bf53x/serial.c
@@ -29,206 +29,206 @@
  */
 static rt_err_t rt_serial_init (rt_device_t dev)
 {
-	struct serial_device* uart = (struct serial_device*) dev->user_data;
+    struct serial_device* uart = (struct serial_device*) dev->user_data;
 
-	if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
-	{
+    if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
+    {
 
-		if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-		{
-			rt_memset(uart->int_rx->rx_buffer, 0, 
-				sizeof(uart->int_rx->rx_buffer));
-			uart->int_rx->read_index = uart->int_rx->save_index = 0;
-		}
-		
-		if (dev->flag & RT_DEVICE_FLAG_INT_TX)
-		{
-			rt_memset(uart->int_tx->tx_buffer, 0, 
-				sizeof(uart->int_tx->tx_buffer));
-			uart->int_tx->write_index = uart->int_tx->save_index = 0;
-		}
+        if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+        {
+            rt_memset(uart->int_rx->rx_buffer, 0,
+                sizeof(uart->int_rx->rx_buffer));
+            uart->int_rx->read_index = uart->int_rx->save_index = 0;
+        }
 
-		dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
-	}
+        if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+        {
+            rt_memset(uart->int_tx->tx_buffer, 0,
+                sizeof(uart->int_tx->tx_buffer));
+            uart->int_tx->write_index = uart->int_tx->save_index = 0;
+        }
 
-	return RT_EOK;
+        dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
+    }
+
+    return RT_EOK;
 }
 
 /* save a char to serial buffer */
 static void rt_serial_savechar(struct serial_device* uart, char ch)
 {
-	rt_base_t level;
-	
-	/* disable interrupt */
-	level = rt_hw_interrupt_disable();
+    rt_base_t level;
 
-	uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch;
-	uart->int_rx->save_index ++;
-	if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
-		uart->int_rx->save_index = 0;
-	
-	/* if the next position is read index, discard this 'read char' */
-	if (uart->int_rx->save_index == uart->int_rx->read_index)
-	{
-		uart->int_rx->read_index ++;
-		if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
-			uart->int_rx->read_index = 0;
-	}
+    /* disable interrupt */
+    level = rt_hw_interrupt_disable();
 
-	/* enable interrupt */
-	rt_hw_interrupt_enable(level);
+    uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch;
+    uart->int_rx->save_index ++;
+    if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
+        uart->int_rx->save_index = 0;
+
+    /* if the next position is read index, discard this 'read char' */
+    if (uart->int_rx->save_index == uart->int_rx->read_index)
+    {
+        uart->int_rx->read_index ++;
+        if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+            uart->int_rx->read_index = 0;
+    }
+
+    /* enable interrupt */
+    rt_hw_interrupt_enable(level);
 }
 
 static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
-{	
-	RT_ASSERT(dev != RT_NULL);
-	
-	return RT_EOK;
+{
+    RT_ASSERT(dev != RT_NULL);
+
+    return RT_EOK;
 }
 
 static rt_err_t rt_serial_close(rt_device_t dev)
-{	
-	RT_ASSERT(dev != RT_NULL);
+{
+    RT_ASSERT(dev != RT_NULL);
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
 {
-	rt_uint8_t* ptr;
-	rt_err_t err_code;
-	struct serial_device* uart;
-	
-	ptr = buffer;
-	err_code = RT_EOK;
-	uart = (struct serial_device*)dev->user_data;
+    rt_uint8_t* ptr;
+    rt_err_t err_code;
+    struct serial_device* uart;
 
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		rt_base_t level;
+    ptr = buffer;
+    err_code = RT_EOK;
+    uart = (struct serial_device*)dev->user_data;
 
-		/* interrupt mode Rx */
-		while (size)
-		{
-			if (uart->int_rx->read_index != uart->int_rx->save_index)
-			{
-				*ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index];
-				size --;
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        rt_base_t level;
 
-				/* disable interrupt */
-				level = rt_hw_interrupt_disable();
+        /* interrupt mode Rx */
+        while (size)
+        {
+            if (uart->int_rx->read_index != uart->int_rx->save_index)
+            {
+                *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index];
+                size --;
 
-				uart->int_rx->read_index ++;
-				if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
-					uart->int_rx->read_index = 0;
+                /* disable interrupt */
+                level = rt_hw_interrupt_disable();
 
-				/* enable interrupt */
-				rt_hw_interrupt_enable(level);
-			}
-			else
-			{
-				/* set error code */
-				err_code = -RT_EEMPTY;
-				break;
-			}
-		}
-	}
-	else
-	{
-		/* polling mode */
-		while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
-		{
-			//while (uart->uart_device->ustat & USTAT_RCV_READY)
-			{
-				*ptr = uart->uart_device->rbr_thr & 0xff;
-				ptr ++;
-			}
-		}
-	}
+                uart->int_rx->read_index ++;
+                if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+                    uart->int_rx->read_index = 0;
 
-	/* set error code */
-	rt_set_errno(err_code);
-	return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+                /* enable interrupt */
+                rt_hw_interrupt_enable(level);
+            }
+            else
+            {
+                /* set error code */
+                err_code = -RT_EEMPTY;
+                break;
+            }
+        }
+    }
+    else
+    {
+        /* polling mode */
+        while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
+        {
+            //while (uart->uart_device->ustat & USTAT_RCV_READY)
+            {
+                *ptr = uart->uart_device->rbr_thr & 0xff;
+                ptr ++;
+            }
+        }
+    }
+
+    /* set error code */
+    rt_set_errno(err_code);
+    return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
 }
 
 static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
 {
-	rt_uint8_t* ptr;
-	rt_err_t err_code;
-	struct serial_device* uart;
-	
-	err_code = RT_EOK;
-	ptr = (rt_uint8_t*)buffer;
-	uart = (struct serial_device*)dev->user_data;
+    rt_uint8_t* ptr;
+    rt_err_t err_code;
+    struct serial_device* uart;
 
-	if (dev->flag & RT_DEVICE_FLAG_INT_TX)
-	{
-		/* interrupt mode Tx */
-		while (uart->int_tx->save_index != uart->int_tx->write_index)
-		{
-			/* save on tx buffer */
-			uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++;
-			
-			-- size;
+    err_code = RT_EOK;
+    ptr = (rt_uint8_t*)buffer;
+    uart = (struct serial_device*)dev->user_data;
 
-			/* move to next position */
-			uart->int_tx->save_index ++;
-			
-			/* wrap save index */
-			if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE)
-				uart->int_tx->save_index = 0;
-		}
-		
-		/* set error code */
-		if (size > 0)
-			err_code = -RT_EFULL;
-	}
-	else
-	{
-		/* polling mode */
-		while (size)
-		{
-			/*
-			 * to be polite with serial console add a line feed
-			 * to the carriage return character
-			 */
-			if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM))
-			{
-				while (!(uart->uart_device->lsr & 0x20));
-				uart->uart_device->rbr_thr = '\r';
-			}
+    if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+    {
+        /* interrupt mode Tx */
+        while (uart->int_tx->save_index != uart->int_tx->write_index)
+        {
+            /* save on tx buffer */
+            uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++;
 
-			while (!(uart->uart_device->lsr & 0x20));
-			uart->uart_device->rbr_thr = (*ptr & 0xFF);
+            -- size;
 
-			++ptr; --size;
-		}
-	}	
+            /* move to next position */
+            uart->int_tx->save_index ++;
 
-	/* set error code */
-	rt_set_errno(err_code);
-	
-	return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+            /* wrap save index */
+            if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE)
+                uart->int_tx->save_index = 0;
+        }
+
+        /* set error code */
+        if (size > 0)
+            err_code = -RT_EFULL;
+    }
+    else
+    {
+        /* polling mode */
+        while (size)
+        {
+            /*
+             * to be polite with serial console add a line feed
+             * to the carriage return character
+             */
+            if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM))
+            {
+                while (!(uart->uart_device->lsr & 0x20));
+                uart->uart_device->rbr_thr = '\r';
+            }
+
+            while (!(uart->uart_device->lsr & 0x20));
+            uart->uart_device->rbr_thr = (*ptr & 0xFF);
+
+            ++ptr; --size;
+        }
+    }
+
+    /* set error code */
+    rt_set_errno(err_code);
+
+    return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
 }
 
 static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args)
 {
-	RT_ASSERT(dev != RT_NULL);
+    RT_ASSERT(dev != RT_NULL);
 
-	switch (cmd)
-	{
-	case RT_DEVICE_CTRL_SUSPEND:
-		/* suspend device */
-		dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
-		break;
-	
-	case RT_DEVICE_CTRL_RESUME:
-		/* resume device */
-		dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
-		break;
-	}
-	
-	return RT_EOK;
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_SUSPEND:
+        /* suspend device */
+        dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
+        break;
+
+    case RT_DEVICE_CTRL_RESUME:
+        /* resume device */
+        dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
+        break;
+    }
+
+    return RT_EOK;
 }
 
 /*
@@ -236,49 +236,49 @@ static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args)
  */
 rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial)
 {
-	RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(device != RT_NULL);
 
-	device->type 		= RT_Device_Class_Char;
-	device->rx_indicate = RT_NULL;
-	device->tx_complete = RT_NULL;
-	device->init 		= rt_serial_init;
-	device->open		= rt_serial_open;
-	device->close		= rt_serial_close;
-	device->read 		= rt_serial_read;
-	device->write 		= rt_serial_write;
-	device->control 	= rt_serial_control;
-	device->user_data   = serial;
+    device->type        = RT_Device_Class_Char;
+    device->rx_indicate = RT_NULL;
+    device->tx_complete = RT_NULL;
+    device->init        = rt_serial_init;
+    device->open        = rt_serial_open;
+    device->close       = rt_serial_close;
+    device->read        = rt_serial_read;
+    device->write       = rt_serial_write;
+    device->control     = rt_serial_control;
+    device->user_data   = serial;
 
-	/* register a character device */
-	return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
+    /* register a character device */
+    return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
 }
-	
+
 /* ISR for serial interrupt */
 void rt_hw_serial_isr(rt_device_t device)
 {
-	struct serial_device* uart = (struct serial_device*) device->user_data;
-	
-	/* interrupt mode receive */	
-	RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
+    struct serial_device* uart = (struct serial_device*) device->user_data;
 
-	/* save on rx buffer */
-	//while (uart->uart_device->ustat & USTAT_RCV_READY)
-	{
-		rt_serial_savechar(uart, uart->uart_device->rbr_thr & 0xff);
-	}
+    /* interrupt mode receive */
+    RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
 
-	/* invoke callback */
-	if (device->rx_indicate != RT_NULL)
-	{
-		rt_size_t rx_length;
-		
-		/* get rx length */
-		rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
-			UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
-			uart->int_rx->save_index - uart->int_rx->read_index;
+    /* save on rx buffer */
+    //while (uart->uart_device->ustat & USTAT_RCV_READY)
+    {
+        rt_serial_savechar(uart, uart->uart_device->rbr_thr & 0xff);
+    }
 
-		device->rx_indicate(device, rx_length);
-	}	
+    /* invoke callback */
+    if (device->rx_indicate != RT_NULL)
+    {
+        rt_size_t rx_length;
+
+        /* get rx length */
+        rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
+            UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
+            uart->int_rx->save_index - uart->int_rx->read_index;
+
+        device->rx_indicate(device, rx_length);
+    }
 }
 
 /*@}*/
diff --git a/libcpu/blackfin/bf53x/serial.h b/libcpu/blackfin/bf53x/serial.h
index 8d85193634..7969c5514e 100644
--- a/libcpu/blackfin/bf53x/serial.h
+++ b/libcpu/blackfin/bf53x/serial.h
@@ -4,49 +4,49 @@
 #include 
 #include 
 
-#define	USTAT_RCV_READY		0x01   	/* receive data ready */ 
-#define	USTAT_TXB_EMPTY		0x02   	/* tx buffer empty */
-#define BPS					115200	/* serial baudrate */
+#define USTAT_RCV_READY     0x01    /* receive data ready */
+#define USTAT_TXB_EMPTY     0x02    /* tx buffer empty */
+#define BPS                 115200  /* serial baudrate */
 
-#define UART_RX_BUFFER_SIZE		64
-#define UART_TX_BUFFER_SIZE		64
+#define UART_RX_BUFFER_SIZE     64
+#define UART_TX_BUFFER_SIZE     64
 
 struct serial_int_rx
 {
-	rt_uint8_t  rx_buffer[UART_RX_BUFFER_SIZE];
-	rt_uint32_t read_index, save_index;
+    rt_uint8_t  rx_buffer[UART_RX_BUFFER_SIZE];
+    rt_uint32_t read_index, save_index;
 };
 
 struct serial_int_tx
 {
-	rt_uint8_t  tx_buffer[UART_TX_BUFFER_SIZE];
-	rt_uint32_t write_index, save_index;
+    rt_uint8_t  tx_buffer[UART_TX_BUFFER_SIZE];
+    rt_uint32_t write_index, save_index;
 };
 
 typedef struct uartport
 {
-	volatile rt_uint16_t rbr_thr;  //receive buffer register and transmit hold register
-	volatile rt_uint16_t reserved0;
-	volatile rt_uint16_t reserved1;
-	volatile rt_uint16_t reserved2;
-	volatile rt_uint16_t reserved3;
-	volatile rt_uint16_t reserved4;
-	volatile rt_uint16_t reserved5;
-	volatile rt_uint16_t reserved6;
-	volatile rt_uint16_t reserved7;
-	volatile rt_uint16_t reserved8;
-	volatile rt_uint16_t lsr;      //line status register
+    volatile rt_uint16_t rbr_thr;  //receive buffer register and transmit hold register
+    volatile rt_uint16_t reserved0;
+    volatile rt_uint16_t reserved1;
+    volatile rt_uint16_t reserved2;
+    volatile rt_uint16_t reserved3;
+    volatile rt_uint16_t reserved4;
+    volatile rt_uint16_t reserved5;
+    volatile rt_uint16_t reserved6;
+    volatile rt_uint16_t reserved7;
+    volatile rt_uint16_t reserved8;
+    volatile rt_uint16_t lsr;      //line status register
 }uartport;
 
 struct serial_device
 {
-	uartport* uart_device;
-	
-	/* rx structure */
-	struct serial_int_rx* int_rx;
+    uartport* uart_device;
 
-	/* tx structure */
-	struct serial_int_tx* int_tx;
+    /* rx structure */
+    struct serial_int_rx* int_rx;
+
+    /* tx structure */
+    struct serial_int_tx* int_tx;
 };
 
 rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial);
diff --git a/libcpu/c-sky/ck802/contex_ck802_gcc.S b/libcpu/c-sky/ck802/contex_ck802_gcc.S
index 44f2c331dd..a4431b0f74 100644
--- a/libcpu/c-sky/ck802/contex_ck802_gcc.S
+++ b/libcpu/c-sky/ck802/contex_ck802_gcc.S
@@ -1,21 +1,7 @@
 /*
- * File      : contex_ck802.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/libcpu/c-sky/ck802/core_ck802.c b/libcpu/c-sky/ck802/core_ck802.c
index 047c417267..d8cfce09f7 100644
--- a/libcpu/c-sky/ck802/core_ck802.c
+++ b/libcpu/c-sky/ck802/core_ck802.c
@@ -1,21 +1,7 @@
 /*
- * File      : core_ck802.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/libcpu/c-sky/ck802/core_ck802.h b/libcpu/c-sky/ck802/core_ck802.h
index 6c335f8178..e7185131e4 100644
--- a/libcpu/c-sky/ck802/core_ck802.h
+++ b/libcpu/c-sky/ck802/core_ck802.h
@@ -1,21 +1,7 @@
 /*
- * File      : core_ck802.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -147,24 +133,24 @@ extern "C" {
  */
 
 /**
-  \brief  ʴ״̬Ĵ(PSR)嶨.
+  \brief  访问处理器状态寄存器(PSR)的联合体定义.
  */
 typedef union
 {
     struct
     {
-        uint32_t C: 1;                       /*!< bit:      0  룯λλ */
-        uint32_t _reserved0: 5;              /*!< bit:  2.. 5   */
-        uint32_t IE: 1;                      /*!< bit:      6  жЧλ */
-        uint32_t IC: 1;                      /*!< bit:      7  жϿλ */
-        uint32_t EE: 1;                      /*!< bit:      8  쳣Чλ */
-        uint32_t MM: 1;                      /*!< bit:      9  쳣ڸλ */
-        uint32_t _reserved1: 6;              /*!< bit: 10..15   */
-        uint32_t VEC: 8;                     /*!< bit: 16..23  쳣¼ֵ */
-        uint32_t _reserved2: 7;              /*!< bit: 24..30   */
-        uint32_t S: 1;                       /*!< bit:     31  ûģʽλ */
-    } b;                                   /*!< Structure    λ */
-    uint32_t w;                            /*!< Type         Ĵ */
+        uint32_t C: 1;                       /*!< bit:      0  条件码／进位位 */
+        uint32_t _reserved0: 5;              /*!< bit:  2.. 5  保留 */
+        uint32_t IE: 1;                      /*!< bit:      6  中断有效控制位 */
+        uint32_t IC: 1;                      /*!< bit:      7  中断控制位 */
+        uint32_t EE: 1;                      /*!< bit:      8  异常有效控制位 */
+        uint32_t MM: 1;                      /*!< bit:      9  不对齐异常掩盖位 */
+        uint32_t _reserved1: 6;              /*!< bit: 10..15  保留 */
+        uint32_t VEC: 8;                     /*!< bit: 16..23  异常事件向量值 */
+        uint32_t _reserved2: 7;              /*!< bit: 24..30  保留 */
+        uint32_t S: 1;                       /*!< bit:     31  超级用户模式设置位 */
+    } b;                                   /*!< Structure    用来按位访问 */
+    uint32_t w;                            /*!< Type         整个寄存器访问 */
 } PSR_Type;
 
 /* PSR Register Definitions */
@@ -190,21 +176,21 @@ typedef union
 #define PSR_C_Msk                          (1UL << PSR_C_Pos)                             /*!< PSR: C Mask */
 
 /**
-  \brief  ʸٻüĴ(CCR, CR<18, 0>)嶨.
+  \brief  访问高速缓存配置寄存器(CCR, CR<18, 0>)的联合体定义.
  */
 typedef union
 {
     struct
     {
-        uint32_t MP: 1;                      /*!< bit:      0  ڴ汣λ */
-        uint32_t _reserved0: 6;              /*!< bit:  1.. 6   */
-        uint32_t BE: 1;                      /*!< bit:      7  Endianģʽ */
-        uint32_t SCK: 3;                     /*!< bit:  8..10  ϵͳʹʱӱ */
-        uint32_t _reserved1: 2;              /*!< bit: 11..12   */
-        uint32_t BE_V2: 1;                   /*!< bit:     13  V2汾С */
-        uint32_t _reserved2: 18;             /*!< bit: 14..31   */
-    } b;                                   /*!< Structure    λ */
-    uint32_t w;                            /*!< Type         Ĵ */
+        uint32_t MP: 1;                      /*!< bit:      0  内存保护设置位 */
+        uint32_t _reserved0: 6;              /*!< bit:  1.. 6  保留 */
+        uint32_t BE: 1;                      /*!< bit:      7  Endian模式 */
+        uint32_t SCK: 3;                     /*!< bit:  8..10  系统和处理器的时钟比 */
+        uint32_t _reserved1: 2;              /*!< bit: 11..12  保留 */
+        uint32_t BE_V2: 1;                   /*!< bit:     13  V2版本大小端 */
+        uint32_t _reserved2: 18;             /*!< bit: 14..31  保留 */
+    } b;                                   /*!< Structure    用来按位访问 */
+    uint32_t w;                            /*!< Type         整个寄存器访问 */
 } CCR_Type;
 
 /* CCR Register Definitions */
@@ -221,38 +207,38 @@ typedef union
 #define CCR_MP_Msk                        (0x1UL << CCR_MP_Pos)                          /*!< CCR: MP Mask */
 
 /**
-  \brief  ʿɸ߻ͷȨüĴ(CAPR, CR<19,0>)嶨..
+  \brief  访问可高缓和访问权限配置寄存器(CAPR, CR<19,0>)的联合体定义..
  */
 typedef union
 {
     struct
     {
-        uint32_t X0: 1;                      /*!< bit:      0  ִλ */
-        uint32_t X1: 1;                      /*!< bit:      1  ִλ */
-        uint32_t X2: 1;                      /*!< bit:      2  ִλ */
-        uint32_t X3: 1;                      /*!< bit:      3  ִλ */
-        uint32_t X4: 1;                      /*!< bit:      4  ִλ */
-        uint32_t X5: 1;                      /*!< bit:      5  ִλ */
-        uint32_t X6: 1;                      /*!< bit:      6  ִλ */
-        uint32_t X7: 1;                      /*!< bit:      7  ִλ */
-        uint32_t AP0: 2;                     /*!< bit:  8.. 9  Ȩλ */
-        uint32_t AP1: 2;                     /*!< bit: 10..11  Ȩλ */
-        uint32_t AP2: 2;                     /*!< bit: 12..13  Ȩλ */
-        uint32_t AP3: 2;                     /*!< bit: 14..15  Ȩλ */
-        uint32_t AP4: 2;                     /*!< bit: 16..17  Ȩλ */
-        uint32_t AP5: 2;                     /*!< bit: 18..19  Ȩλ */
-        uint32_t AP6: 2;                     /*!< bit: 20..21  Ȩλ */
-        uint32_t AP7: 2;                     /*!< bit: 22..23  Ȩλ */
-        uint32_t S0: 1;                      /*!< bit:     24  ȫλ */
-        uint32_t S1: 1;                      /*!< bit:     25  ȫλ */
-        uint32_t S2: 1;                      /*!< bit:     26  ȫλ */
-        uint32_t S3: 1;                      /*!< bit:     27  ȫλ */
-        uint32_t S4: 1;                      /*!< bit:     28  ȫλ */
-        uint32_t S5: 1;                      /*!< bit:     29  ȫλ */
-        uint32_t S6: 1;                      /*!< bit:     30  ȫλ */
-        uint32_t S7: 1;                      /*!< bit:     31  ȫλ */
-    } b;                                   /*!< Structure    λ */
-    uint32_t w;                            /*!< Type         Ĵ */
+        uint32_t X0: 1;                      /*!< bit:      0  不可执行属性设置位 */
+        uint32_t X1: 1;                      /*!< bit:      1  不可执行属性设置位 */
+        uint32_t X2: 1;                      /*!< bit:      2  不可执行属性设置位 */
+        uint32_t X3: 1;                      /*!< bit:      3  不可执行属性设置位 */
+        uint32_t X4: 1;                      /*!< bit:      4  不可执行属性设置位 */
+        uint32_t X5: 1;                      /*!< bit:      5  不可执行属性设置位 */
+        uint32_t X6: 1;                      /*!< bit:      6  不可执行属性设置位 */
+        uint32_t X7: 1;                      /*!< bit:      7  不可执行属性设置位 */
+        uint32_t AP0: 2;                     /*!< bit:  8.. 9  访问权限设置位 */
+        uint32_t AP1: 2;                     /*!< bit: 10..11  访问权限设置位 */
+        uint32_t AP2: 2;                     /*!< bit: 12..13  访问权限设置位 */
+        uint32_t AP3: 2;                     /*!< bit: 14..15  访问权限设置位 */
+        uint32_t AP4: 2;                     /*!< bit: 16..17  访问权限设置位 */
+        uint32_t AP5: 2;                     /*!< bit: 18..19  访问权限设置位 */
+        uint32_t AP6: 2;                     /*!< bit: 20..21  访问权限设置位 */
+        uint32_t AP7: 2;                     /*!< bit: 22..23  访问权限设置位 */
+        uint32_t S0: 1;                      /*!< bit:     24  安全属性设置位 */
+        uint32_t S1: 1;                      /*!< bit:     25  安全属性设置位 */
+        uint32_t S2: 1;                      /*!< bit:     26  安全属性设置位 */
+        uint32_t S3: 1;                      /*!< bit:     27  安全属性设置位 */
+        uint32_t S4: 1;                      /*!< bit:     28  安全属性设置位 */
+        uint32_t S5: 1;                      /*!< bit:     29  安全属性设置位 */
+        uint32_t S6: 1;                      /*!< bit:     30  安全属性设置位 */
+        uint32_t S7: 1;                      /*!< bit:     31  安全属性设置位 */
+    } b;                                   /*!< Structure    用来按位访问 */
+    uint32_t w;                            /*!< Type         整个寄存器访问 */
 } CAPR_Type;
 
 /* CAPR Register Definitions */
@@ -329,18 +315,18 @@ typedef union
 #define CAPR_X0_Msk                        (0x1UL << CAPR_X0_Pos)                         /*!< CAPR: X0 Mask */
 
 /**
-  \brief  ʱƼĴ(PACR, CR<20,0>)嶨.
+  \brief  访问保护区控制寄存器(PACR, CR<20,0>)的联合体定义.
  */
 typedef union
 {
     struct
     {
-        uint32_t E: 1;                       /*!< bit:      0  Ч */
-        uint32_t Size: 5;                    /*!< bit:  1.. 5  С */
-        uint32_t _reserved0: 4;              /*!< bit:  6.. 9   */
-        uint32_t base_addr: 22;              /*!< bit: 10..31  ַĸλ */
-    } b;                                   /*!< Structure    λ */
-    uint32_t w;                            /*!< Type         Ĵ */
+        uint32_t E: 1;                       /*!< bit:      0  保护区有效设置 */
+        uint32_t Size: 5;                    /*!< bit:  1.. 5  保护区大小 */
+        uint32_t _reserved0: 4;              /*!< bit:  6.. 9  保留 */
+        uint32_t base_addr: 22;              /*!< bit: 10..31  保护区地址的高位 */
+    } b;                                   /*!< Structure    用来按位访问 */
+    uint32_t w;                            /*!< Type         整个寄存器访问 */
 } PACR_Type;
 
 /* PACR Register Definitions */
@@ -354,16 +340,16 @@ typedef union
 #define PACK_E_Msk                         (0x1UL << PACR_E_Pos)                          /*!< PACR: E Mask */
 
 /**
-  \brief  ʱѡĴ(PRSR,CR<21,0>)嶨.
+  \brief  访问保护区选择寄存器(PRSR,CR<21,0>)的联合体定义.
  */
 typedef union
 {
     struct
     {
-        uint32_t RID: 3;                     /*!< bit:  0.. 2  ֵ */
-        uint32_t _reserved0: 30;             /*!< bit:  3..31   */
-    } b;                                   /*!< Structure    λ */
-    uint32_t w;                            /*!< Type         Ĵ */
+        uint32_t RID: 3;                     /*!< bit:  0.. 2  保护区索引值 */
+        uint32_t _reserved0: 30;             /*!< bit:  3..31  保留 */
+    } b;                                   /*!< Structure    用来按位访问 */
+    uint32_t w;                            /*!< Type         整个寄存器访问 */
 } PRSR_Type;
 
 /* PRSR Register Definitions */
@@ -381,30 +367,30 @@ typedef union
  */
 
 /**
-  \brief ʸжϿĽṹ.
+  \brief 访问矢量中断控制器的结构体.
  */
 typedef struct
 {
-    __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  жʹüĴ */
+    __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  中断使能设置寄存器 */
     uint32_t RESERVED0[15U];
-    __IOM uint32_t IWER[1U];               /*!< Offset: 0x040 (R/W)  жϵ͹ĻüĴ */
+    __IOM uint32_t IWER[1U];               /*!< Offset: 0x040 (R/W)  中断低功耗唤醒设置寄存器 */
     uint32_t RESERVED1[15U];
-    __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  жʹĴ */
+    __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  中断使能清除寄存器 */
     uint32_t RESERVED2[15U];
-    __IOM uint32_t IWDR[1U];               /*!< Offset: 0x0c0 (R/W)  жϵ͹ĻĴ */
+    __IOM uint32_t IWDR[1U];               /*!< Offset: 0x0c0 (R/W)  中断低功耗唤醒清除寄存器 */
     uint32_t RESERVED3[15U];
-    __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  жϵȴüĴ */
+    __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  中断等待设置寄存器 */
     uint32_t RESERVED4[15U];
-    __IOM uint32_t ISSR[1U];               /*!< Offset: 0x140 (R/W)  ȫжʹüĴ */
+    __IOM uint32_t ISSR[1U];               /*!< Offset: 0x140 (R/W)  安全中断使能设置寄存器 */
     uint32_t RESERVED5[15U];
-    __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  жϵȴĴ */
+    __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  中断等待清除寄存器 */
     uint32_t RESERVED6[31U];
-    __IOM uint32_t IABR[1U];               /*!< Offset: 0x200 (R/W)  жӦ״̬Ĵ */
+    __IOM uint32_t IABR[1U];               /*!< Offset: 0x200 (R/W)  中断响应状态寄存器 */
     uint32_t RESERVED7[63U];
-    __IOM uint32_t IPR[8U];                /*!< Offset: 0x300 (R/W)  жȼüĴ */
+    __IOM uint32_t IPR[8U];                /*!< Offset: 0x300 (R/W)  中断优先级设置寄存器 */
     uint32_t RESERVED8[504U];
-    __IM  uint32_t ISR;                    /*!< Offset: 0xB00 (R/ )  ж״̬Ĵ */
-    __IOM uint32_t IPTR;                   /*!< Offset: 0xB04 (R/W)  жȼֵĴ */
+    __IM  uint32_t ISR;                    /*!< Offset: 0xB00 (R/ )  中断状态寄存器 */
+    __IOM uint32_t IPTR;                   /*!< Offset: 0xB04 (R/W)  中断优先级阈值寄存器 */
 } NVIC_Type;
 
 /*@} end of group CSI_NVIC */
@@ -417,14 +403,14 @@ typedef struct
  */
 
 /**
-  \brief  ϵͳʱݽṹ.
+  \brief  访问系统计时器的数据结构.
  */
 typedef struct
 {
-    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  ״̬Ĵ */
-    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  ֵĴ */
-    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  ǰֵĴ */
-    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  У׼Ĵ */
+    __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  控制状态寄存器 */
+    __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  回填值寄存器 */
+    __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  当前值寄存器 */
+    __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  校准寄存器 */
 } CORET_Type;
 
 /* CORET Control / Status Register Definitions */
@@ -468,7 +454,7 @@ typedef struct
  */
 
 /**
-  \brief  DCCݽṹ.
+  \brief  访问DCC的数据结构.
  */
 typedef struct
 {
@@ -478,8 +464,8 @@ typedef struct
     uint32_t RESERVED1[6U];
     union
     {
-        __IM uint32_t DERJW;                 /*!< Offset: 0x058 (R/ )  ݽĴ CPU*/
-        __OM uint32_t DERJR;                 /*!< Offset: 0x058 ( /W)  ݽĴ CPUд*/
+        __IM uint32_t DERJW;                 /*!< Offset: 0x058 (R/ )  数据交换寄存器 CPU读*/
+        __OM uint32_t DERJR;                 /*!< Offset: 0x058 ( /W)  数据交换寄存器 CPU写*/
     };
 
 } DCC_Type;
diff --git a/libcpu/c-sky/ck802/stack_ck802.c b/libcpu/c-sky/ck802/stack_ck802.c
index 01fed9ad34..087722072e 100644
--- a/libcpu/c-sky/ck802/stack_ck802.c
+++ b/libcpu/c-sky/ck802/stack_ck802.c
@@ -1,21 +1,7 @@
 /*
- * File      : stack_ck802.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/libcpu/ia32/__udivsi3.c b/libcpu/ia32/__udivsi3.c
index ec7c59d1cb..ced90b5aba 100644
--- a/libcpu/ia32/__udivsi3.c
+++ b/libcpu/ia32/__udivsi3.c
@@ -1,11 +1,7 @@
 /*
- * File      : __udivsi3.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -16,31 +12,31 @@
 
 uint32_t __udivsi3(uint32_t num, uint32_t den)
 {
-	uint32_t quot = 0, qbit = 1;
+    uint32_t quot = 0, qbit = 1;
 
-	if (den == 0)
-	{
-		asm volatile ("int $0");
-		return 0;	/* If trap returns... */
-	}
+    if (den == 0)
+    {
+        asm volatile ("int $0");
+        return 0;   /* If trap returns... */
+    }
 
-	/* Left-justify denominator and count shift */
-	while ((int32_t) den >= 0)
-	{
-		den <<= 1;
-		qbit <<= 1;
-	}
+    /* Left-justify denominator and count shift */
+    while ((int32_t) den >= 0)
+    {
+        den <<= 1;
+        qbit <<= 1;
+    }
 
-	while (qbit)
-	{
-		if (den <= num)
-		{
-			num -= den;
-			quot += qbit;
-		}
-		den >>= 1;
-		qbit >>= 1;
-	}
+    while (qbit)
+    {
+        if (den <= num)
+        {
+            num -= den;
+            quot += qbit;
+        }
+        den >>= 1;
+        qbit >>= 1;
+    }
 
-	return quot;
+    return quot;
 }
diff --git a/libcpu/ia32/__umodsi3.c b/libcpu/ia32/__umodsi3.c
index 226a2c0800..ddc5db5488 100644
--- a/libcpu/ia32/__umodsi3.c
+++ b/libcpu/ia32/__umodsi3.c
@@ -1,11 +1,7 @@
 /*
- * File      : __umodsi3.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -16,31 +12,31 @@
 
 uint32_t __umodsi3(uint32_t num, uint32_t den)
 {
-	register uint32_t quot = 0, qbit = 1;
+    register uint32_t quot = 0, qbit = 1;
 
-	if (den == 0)
-	{
-		asm volatile ("int $0");
-		return 0;	/* if trap returns... */
-	}
+    if (den == 0)
+    {
+        asm volatile ("int $0");
+        return 0;   /* if trap returns... */
+    }
 
-	/* left-justify denominator and count shift */
-	while ((int32_t) den >= 0)
-	{
-		den <<= 1;
-		qbit <<= 1;
-	}
+    /* left-justify denominator and count shift */
+    while ((int32_t) den >= 0)
+    {
+        den <<= 1;
+        qbit <<= 1;
+    }
 
-	while (qbit)
-	{
-		if (den <= num)
-		{
-			num -= den;
-			quot += qbit;
-		}
-		den >>= 1;
-		qbit >>= 1;
-	}
+    while (qbit)
+    {
+        if (den <= num)
+        {
+            num -= den;
+            quot += qbit;
+        }
+        den >>= 1;
+        qbit >>= 1;
+    }
 
-	return num;
+    return num;
 }
diff --git a/libcpu/ia32/backtrace.c b/libcpu/ia32/backtrace.c
deleted file mode 100644
index b8f094d90f..0000000000
--- a/libcpu/ia32/backtrace.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * File      : backtrace.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, 2008 RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2008-07-29     Bernard      first version
- */
-
-#include 
-
-void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry)
-{
-	/* no implementation */
-}
diff --git a/libcpu/ia32/context_gcc.S b/libcpu/ia32/context_gcc.S
index a8ad867b91..32233303c7 100644
--- a/libcpu/ia32/context_gcc.S
+++ b/libcpu/ia32/context_gcc.S
@@ -1,11 +1,7 @@
 /*
- * File      : context_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -83,31 +79,3 @@ rt_hw_context_switch_to:
 	pop %ds
 	add $4, %esp			/* skip irqno */
 	iret
-
-/*
- * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
- */
-.globl rt_thread_switch_interrupt_flag
-.globl rt_interrupt_from_thread
-.globl rt_interrupt_to_thread
-.globl rt_hw_context_switch_interrupt
-rt_hw_context_switch_interrupt:
-	pushl %ebp
-	movl %esp, %ebp
-	movl 0xc(%ebp), %eax
-	movl 0x8(%ebp), %ebx
-	
-	movl $rt_thread_switch_interrupt_flag, %ecx
-	movl (%ecx), %edx
-	cmp $0x1, %edx
-	jz _reswitch
-	
-	movl $0x1, %edx				/*set rt_thread_switch_interrupt_flag to 1*/
-	movl %edx, (%ecx)
-	movl $rt_interrupt_from_thread, %edx	/*set rt_interrupt_from_thread*/
-	movl %ebx, (%edx)
-_reswitch:
-	movl $rt_interrupt_to_thread, %edx		/*set rt_interrupt_to_thread*/
-	movl %eax, (%edx)
-	leave
-	ret
diff --git a/libcpu/ia32/cpuport.c b/libcpu/ia32/cpuport.c
new file mode 100644
index 0000000000..2e0380d9f8
--- /dev/null
+++ b/libcpu/ia32/cpuport.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021/02/19     Bernard      Implement rt_hw_context_switch_interrupt in C
+ */
+
+#include 
+#include 
+
+volatile rt_ubase_t  rt_interrupt_from_thread = 0;
+volatile rt_ubase_t  rt_interrupt_to_thread = 0;
+volatile rt_uint32_t rt_thread_switch_interrupt_flag = 0;
+
+rt_base_t rt_hw_interrupt_disable(void)
+{
+    rt_base_t level;
+
+    __asm__ __volatile__("pushfl ; popl %0 ; cli":"=g" (level): :"memory");
+    return level;
+}
+
+void rt_hw_interrupt_enable(rt_base_t level)
+{
+    __asm__ __volatile__("pushl %0 ; popfl": :"g" (level):"memory", "cc");
+}
+
+void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to)
+{
+    if (rt_thread_switch_interrupt_flag == 0)
+        rt_interrupt_from_thread = from;
+
+    rt_interrupt_to_thread = to;
+    rt_thread_switch_interrupt_flag = 1;
+
+    return ;
+}
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
+    rt_uint8_t *stack_addr, void *texit)
+{
+    unsigned long *stk;
+
+    stk = (unsigned long *)stack_addr;
+    *(--stk) = (unsigned long)parameter;
+    *(--stk) = (unsigned long)texit;
+    *(--stk) = 0x200;                       /*flags*/
+    *(--stk) = 0x08;                        /*cs*/
+    *(--stk) = (unsigned long)tentry;       /*eip*/
+    *(--stk) = 0;                           /*irqno*/
+    *(--stk) = 0x10;                        /*ds*/
+    *(--stk) = 0x10;                        /*es*/
+    *(--stk) = 0;                           /*eax*/
+    *(--stk) = 0;                           /*ecx*/
+    *(--stk) = 0;                           /*edx*/
+    *(--stk) = 0;                           /*ebx*/
+    *(--stk) = 0;                           /*esp*/
+    *(--stk) = 0;                           /*ebp*/
+    *(--stk) = 0;                           /*esi*/
+    *(--stk) = 0;                           /*edi*/
+
+    /* return task's current stack address */
+    return (rt_uint8_t *)stk;
+}
diff --git a/libcpu/ia32/hdisr_gcc.S b/libcpu/ia32/hdisr_gcc.S
index 6f79fe4c2a..24c4c17990 100644
--- a/libcpu/ia32/hdisr_gcc.S
+++ b/libcpu/ia32/hdisr_gcc.S
@@ -1,11 +1,7 @@
 /*
- * File      : hdisr_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/libcpu/ia32/interrupt.c b/libcpu/ia32/interrupt.c
index e620cbe76c..473bf7714a 100644
--- a/libcpu/ia32/interrupt.c
+++ b/libcpu/ia32/interrupt.c
@@ -1,38 +1,20 @@
 /*
- * File      : interrupt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2015/9/15      Bernard      Update to new interrupt framework.
  */
- 
-#include 
+
 #include 
+#include 
 
 #include 
 
-extern rt_uint32_t rt_interrupt_nest;
 extern void rt_hw_idt_init(void);
 
-rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
-rt_uint32_t rt_thread_switch_interrupt_flag;
-
 /* exception and interrupt handler table */
 struct rt_irq_desc irq_desc[MAX_HANDLERS];
 
@@ -50,45 +32,39 @@ void rt_hw_interrupt_handle(int vector, void* param);
  */
 void rt_hw_pic_init()
 {
-	outb(IO_PIC1, 0x11);
-	outb(IO_PIC1+1, IRQ_OFFSET);
-	outb(IO_PIC1+1, 1<> 8));
-	}
-
-	/* init interrupt nest, and context */
-	rt_interrupt_nest = 0;
-	rt_interrupt_from_thread = 0;
-	rt_interrupt_to_thread = 0;
-	rt_thread_switch_interrupt_flag = 0;
+    if (irq_mask_8259A != 0xFFFF)
+    {
+        outb(IO_PIC1+1, (char)irq_mask_8259A);
+        outb(IO_PIC2+1, (char)(irq_mask_8259A >> 8));
+    }
 }
 
 void rt_hw_interrupt_handle(int vector, void* param)
 {
-	rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+    rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
 }
 
 void rt_hw_isr(int vector)
 {
-	if (vector < MAX_HANDLERS)
-	{
-		irq_desc[vector].handler(vector, irq_desc[vector].param);
-	}
+    if (vector < MAX_HANDLERS)
+    {
+        irq_desc[vector].handler(vector, irq_desc[vector].param);
+    }
 }
 
 /**
@@ -97,10 +73,10 @@ void rt_hw_isr(int vector)
  */
 void rt_hw_interrupt_init(void)
 {
-	int idx;
-	
-	rt_hw_idt_init();
-	rt_hw_pic_init();
+    int idx;
+
+    rt_hw_idt_init();
+    rt_hw_pic_init();
 
     /* init exceptions table */
     for(idx=0; idx < MAX_HANDLERS; idx++)
@@ -116,16 +92,16 @@ void rt_hw_interrupt_init(void)
 
 void rt_hw_interrupt_umask(int vector)
 {
-	irq_mask_8259A = irq_mask_8259A&~(1<> 8));
+    irq_mask_8259A = irq_mask_8259A&~(1<> 8));
 }
 
 void rt_hw_interrupt_mask(int vector)
 {
-	irq_mask_8259A = irq_mask_8259A | (1<> 8));
+    irq_mask_8259A = irq_mask_8259A | (1<> 8));
 }
 
 rt_isr_handler_t rt_hw_interrupt_install(int              vector,
@@ -152,17 +128,4 @@ rt_isr_handler_t rt_hw_interrupt_install(int              vector,
     return old_handler;
 }
 
-rt_base_t rt_hw_interrupt_disable(void)
-{
-	rt_base_t level;
-
-	__asm__ __volatile__("pushfl ; popl %0 ; cli":"=g" (level): :"memory");
-	return level;
-}
-
-void rt_hw_interrupt_enable(rt_base_t level)
-{
-	__asm__ __volatile__("pushl %0 ; popfl": :"g" (level):"memory", "cc");
-}
-
 /*@}*/
diff --git a/libcpu/ia32/showmem.c b/libcpu/ia32/showmem.c
deleted file mode 100644
index 38f037f83d..0000000000
--- a/libcpu/ia32/showmem.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * File      : showmem.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, 2008 RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2008-07-29     Bernard      first version from QiuYi implementation
- */
-
-#include 
-
-void rt_hw_show_memory(rt_uint32_t addr, rt_uint32_t size)
-{
-	int i = 0, j =0;
-
-	RT_ASSERT(addr);
-
-	addr = addr & ~0xF;
-	size = 4*((size + 3)/4);
-
-	while(i < size)
-	{
-		rt_kprintf("0x%08x: ", addr );
-
-		for(j=0; j<4; j++)
-		{
-			rt_kprintf("0x%08x  ", *(rt_uint32_t *)addr);
-
-			addr += 4;
-			i++;
-		}
-
-		rt_kprintf("\n");
-	}
-
-	return;
-}
diff --git a/libcpu/ia32/stack.c b/libcpu/ia32/stack.c
deleted file mode 100644
index 9d656a73d6..0000000000
--- a/libcpu/ia32/stack.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * File      : stack.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- */
- 
-#include 
-
-#include 
-
-/**
- * @addtogroup I386
- */
-/*@{*/
-
-/**
- * This function will initialize thread stack
- *
- * @param tentry the entry of thread
- * @param parameter the parameter of entry 
- * @param stack_addr the beginning stack address
- * @param texit the function will be called when thread exit
- *
- * @return stack address
- */
-rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
-	rt_uint8_t *stack_addr, void *texit)
-{
-	unsigned long *stk;
-
-	stk = (unsigned long *)stack_addr;							
-	*(--stk) = (unsigned long)parameter;
-	*(--stk) = (unsigned long)texit;
-	*(--stk) = 0x200;						/*flags*/
-	*(--stk) = 0x08;						/*cs*/
-	*(--stk) = (unsigned long)tentry;		/*eip*/
-	*(--stk) = 0;							/*irqno*/
-	*(--stk) = 0x10;						/*ds*/
-	*(--stk) = 0x10;						/*es*/
-	*(--stk) = 0;							/*eax*/
-	*(--stk) = 0;							/*ecx*/
-	*(--stk) = 0;							/*edx*/
-	*(--stk) = 0;							/*ebx*/
-	*(--stk) = 0;							/*esp*/
-	*(--stk) = 0;							/*ebp*/
-	*(--stk) = 0;							/*esi*/
-	*(--stk) = 0;							/*edi*/
-
-	/* return task's current stack address */
-	return (rt_uint8_t *)stk;
-}
-/*@}*/
diff --git a/libcpu/ia32/start_gcc.S b/libcpu/ia32/start_gcc.S
index 84adc83fe2..ee7d2787fd 100644
--- a/libcpu/ia32/start_gcc.S
+++ b/libcpu/ia32/start_gcc.S
@@ -1,11 +1,7 @@
 /*
- * File      : start.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -52,8 +48,8 @@ multiboot_entry:
 	pushl	$0
 	popf
 
-	/*rebuild globe describe table*/
-	lgdt	mygdtdesc
+	/* rebuild globe describe table */
+	lgdt	__gdtdesc
 
 	movl	$0x10,%eax
 	movw	%ax,%ds
@@ -77,7 +73,7 @@ spin:
 
 .data
 .p2align	2
-mygdt:
+__gdt:
 	.word	0,0,0,0
 
 	.word	0x07FF		/* 8Mb - limit=2047 */
@@ -90,8 +86,8 @@ mygdt:
 	.word	0x9200		/* data read/write */
 	.word	0x00C0
 
-mygdtdesc:
+__gdtdesc:
 	.word	0x17
-	.long	mygdt
+	.long	__gdt
 
 /*@}*/
diff --git a/libcpu/ia32/trap.c b/libcpu/ia32/trap.c
index 5e9a51d6d2..c77a20c890 100644
--- a/libcpu/ia32/trap.c
+++ b/libcpu/ia32/trap.c
@@ -1,18 +1,14 @@
 /*
- * File      : trap.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  */
 
-#include 
 #include 
+#include 
 
 #include 
 
@@ -22,13 +18,14 @@
 struct Gatedesc idt[256] = { {0}, };
 struct Pseudodesc idt_pd =
 {
-	0, sizeof(idt) - 1, (unsigned long) idt,
+    0, sizeof(idt) - 1, (unsigned long) idt,
 };
 
 /* exception and interrupt handler table */
 extern rt_isr_handler_t isr_table[];
 extern rt_isr_handler_t trap_func[];
 extern rt_isr_handler_t hdinterrupt_func[];
+extern void rt_hw_interrupt_handle(int vector, void* param);
 
 /**
  * @addtogroup I386
@@ -40,36 +37,36 @@ extern rt_isr_handler_t hdinterrupt_func[];
  *
  */
 void rt_hw_idt_init(void)
-{	
-	extern void Xdefault;
-	int i, j, func;
+{
+    extern void Xdefault(void);
+    int i, j, func;
 
-	// install a default handler
-	for (i = 0; i < sizeof(idt)/sizeof(idt[0]); i++)
-		SETGATE(idt[i], 0, GD_KT, &Xdefault, 0);
+    // install a default handler
+    for (i = 0; i < sizeof(idt)/sizeof(idt[0]); i++)
+        SETGATE(idt[i], 0, GD_KT, &Xdefault, 0);
 
-	/*install trap handler*/
-	for(i = 0; i < 16; i++)
-	{
-		func = (int)trap_func[i];
-		SETGATE(idt[i], 0, GD_KT, func, 0);
-	}
+    /*install trap handler*/
+    for(i = 0; i < 16; i++)
+    {
+        func = (int)trap_func[i];
+        SETGATE(idt[i], 0, GD_KT, func, 0);
+    }
 
-	func = (int)trap_func[3];
-	SETGATE(idt[3], 0, GD_KT, func, 3);
+    func = (int)trap_func[3];
+    SETGATE(idt[3], 0, GD_KT, func, 3);
 
-	i = 0;
-	
-	/*install exteral interrupt handler*/
-	for(j = IRQ_OFFSET; j < IRQ_OFFSET + MAX_HANDLERS; j++)
-	{	
-		func = (int)hdinterrupt_func[i];
-		SETGATE(idt[j], 0, GD_KT, func, 0);
-		i++;
-	}
-	
-	// Load the IDT
-	asm volatile("lidt idt_pd + 2");
+    i = 0;
+
+    /*install exteral interrupt handler*/
+    for(j = IRQ_OFFSET; j < IRQ_OFFSET + MAX_HANDLERS; j++)
+    {
+        func = (int)hdinterrupt_func[i];
+        SETGATE(idt[j], 0, GD_KT, func, 0);
+        i++;
+    }
+
+    // Load the IDT
+    asm volatile("lidt idt_pd + 2");
 }
 
 /**
@@ -80,24 +77,24 @@ void rt_hw_idt_init(void)
  */
 void rt_hw_trap_irq(int trapno)
 {
-	switch(trapno)
-	{
-		case T_DIVIDE:
-			rt_kprintf("Divide error interrupt\n");
-			RT_ASSERT(0);
-		case T_PGFLT:
-			rt_kprintf("Page fault interrupt\n");
-			RT_ASSERT(0);
-		case T_GPFLT:
-			rt_kprintf("General protection interrupt\n");
-			RT_ASSERT(0);
-		case T_DEFAULT:
-			rt_hw_interrupt_handle(T_DEFAULT);
-			return;
-	}
+    switch(trapno)
+    {
+        case T_DIVIDE:
+            rt_kprintf("Divide error interrupt\n");
+            RT_ASSERT(0);
+        case T_PGFLT:
+            rt_kprintf("Page fault interrupt\n");
+            RT_ASSERT(0);
+        case T_GPFLT:
+            rt_kprintf("General protection interrupt\n");
+            RT_ASSERT(0);
+        case T_DEFAULT:
+            rt_hw_interrupt_handle(T_DEFAULT, RT_NULL);
+            return;
+    }
 
-	/*kernel bug if run here*/
-	RT_ASSERT(0);
+    /*kernel bug if run here*/
+    RT_ASSERT(0);
 }
 
 /*@}*/
diff --git a/libcpu/ia32/trapisr_gcc.S b/libcpu/ia32/trapisr_gcc.S
index be7e97a5fb..82887ecda3 100644
--- a/libcpu/ia32/trapisr_gcc.S
+++ b/libcpu/ia32/trapisr_gcc.S
@@ -1,11 +1,7 @@
 /*
- * File      : trapisr_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -22,6 +18,7 @@
 	.globl proc;\
 	.type proc,@function;\
 	proc:
+
 #define TRAPFNC(name,num)\
 	ENTRY(name)\
 	pushl $(num);\
@@ -29,6 +26,7 @@
 	.data;\
 	.long name;\
 	.text
+
 #define TRAPFNC_NOEC(name,num)\
 	ENTRY(name)\
 	pushl $0;\
@@ -54,17 +52,17 @@ TRAPFNC_NOEC(Xoflow,  4)
 TRAPFNC_NOEC(Xbound,  5)
 TRAPFNC_NOEC(Xillop,  6)
 TRAPFNC_NOEC(Xdevice, 7)
-TRAPFNC     	(Xdblflt, 8)
-TRAPFNC    	(Xtss,    9)
-TRAPFNC     	(Xsegnp,  10)
-TRAPFNC     	(Xstack,  11)
-TRAPFNC     	(Xgpflt,  12)
-TRAPFNC     	(Xpgflt,  13)
+TRAPFNC (Xdblflt, 8)
+TRAPFNC (Xtss,    9)
+TRAPFNC (Xsegnp,  10)
+TRAPFNC (Xstack,  11)
+TRAPFNC (Xgpflt,  12)
+TRAPFNC (Xpgflt,  13)
 TRAPFNC_NOEC(Xfperr,  14)
-TRAPFNC     	(Xalign,  15)
+TRAPFNC (Xalign,  15)
 
 /* default handler -- not for any specific trap */
-TRAPFNC     (Xdefault, 500)
+TRAPFNC (Xdefault, 500)
 
 .p2align 4,0x90
 .globl	_traps
diff --git a/libcpu/m16c/m16c62p/cpuport.c b/libcpu/m16c/m16c62p/cpuport.c
index c66f73b727..8f9a50d89a 100644
--- a/libcpu/m16c/m16c62p/cpuport.c
+++ b/libcpu/m16c/m16c62p/cpuport.c
@@ -113,4 +113,4 @@ void rt_hw_interrupt_enable(rt_base_t level)
     temp = level & 0xffff;
     asm("LDC %0, FLG": :"r" (temp));
 }
-#endif
\ No newline at end of file
+#endif
diff --git a/libcpu/mips/common/asm.h b/libcpu/mips/common/asm.h
index 1b39eea05a..355c05ab39 100644
--- a/libcpu/mips/common/asm.h
+++ b/libcpu/mips/common/asm.h
@@ -1,7 +1,7 @@
 /*
  * Assembly Macros For MIPS
  *
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -18,101 +18,101 @@
 /*
  * LEAF - declare leaf routine
  */
-#define	LEAF(symbol)                        \
-        .globl	symbol;                     \
-        .align	2;                          \
-        .type	symbol,@function;           \
-        .ent	symbol,0;                   \
-symbol:		.frame	sp,0,ra
+#define LEAF(symbol)                        \
+        .globl  symbol;                     \
+        .align  2;                          \
+        .type   symbol,@function;           \
+        .ent    symbol,0;                   \
+symbol:     .frame  sp,0,ra
 
 /*
  * NESTED - declare nested routine entry point
  */
-#define	NESTED(symbol, framesize, rpc)      \
-        .globl	symbol;                     \
-        .align	2;                          \
-        .type	symbol,@function;           \
-        .ent	symbol,0;                   \
-symbol:		.frame	sp, framesize, rpc
+#define NESTED(symbol, framesize, rpc)      \
+        .globl  symbol;                     \
+        .align  2;                          \
+        .type   symbol,@function;           \
+        .ent    symbol,0;                   \
+symbol:     .frame  sp, framesize, rpc
 
 /*
  * END - mark end of function
  */
-#define	END(function)                       \
-        .end	function;		        	\
-        .size	function,.-function
+#define END(function)                       \
+        .end    function;                   \
+        .size   function,.-function
 
 /*
  * EXPORT - export definition of symbol
  */
-#define EXPORT(symbol)						\
-        .globl	symbol;                     \
+#define EXPORT(symbol)                      \
+        .globl  symbol;                     \
 symbol:
 
 /*
  * FEXPORT - export definition of a function symbol
  */
-#define FEXPORT(symbol)						\
-        .globl	symbol;						\
-        .type	symbol,@function;			\
+#define FEXPORT(symbol)                     \
+        .globl  symbol;                     \
+        .type   symbol,@function;           \
 symbol:
 
 /*
  * Global data declaration with size.
  */
-#define EXPORTS(name,sz) 		\
-      .globl name; 				\
-      .type name,@object; 		\
-      .size name,sz; 				\
+#define EXPORTS(name,sz)        \
+      .globl name;              \
+      .type name,@object;       \
+      .size name,sz;                \
 name:
 
 /*
  * Weak data declaration with size.
  */
-#define WEXPORT(name,sz) 		\
-      .weakext name; 				\
-      .type name,@object; 		\
-      .size name,sz; 				\
+#define WEXPORT(name,sz)        \
+      .weakext name;                \
+      .type name,@object;       \
+      .size name,sz;                \
 name:
 
 /*
  * Global data reference with size.
  */
-#define	IMPORT(name, size) 		\
-    .extern	name,size
+#define IMPORT(name, size)      \
+    .extern name,size
 
 /*
  * Global zeroed data.
  */
-#define BSS(name,size) 			\
-      .type name,@object; 		\
-    .comm	name,size
+#define BSS(name,size)          \
+      .type name,@object;       \
+    .comm   name,size
 
 /*
  * Local zeroed data.
  */
-#define LBSS(name,size) 		\
-      .lcomm	name,size
+#define LBSS(name,size)         \
+      .lcomm    name,size
 
 
 /*
  * ABS - export absolute symbol
  */
-#define	ABS(symbol,value)       \
-        .globl	symbol;         \
-symbol		=	value
+#define ABS(symbol,value)       \
+        .globl  symbol;         \
+symbol      =   value
 
 
-#define	TEXT(msg)               \
-        .pushsection .data;		\
-8:		.asciiz	msg;            \
+#define TEXT(msg)               \
+        .pushsection .data;     \
+8:      .asciiz msg;            \
         .popsection;
 
 
-#define ENTRY(name) 			\
-  .globl name;					\
-  .align 2;						\
-  .ent name,0;					\
+#define ENTRY(name)             \
+  .globl name;                  \
+  .align 2;                     \
+  .ent name,0;                  \
   name##:
 
 /*
@@ -122,185 +122,185 @@ symbol		=	value
 /*
  * Size of a register
  */
-#define SZREG	8
+#define SZREG   8
 
 /*
  * Use the following macros in assemblercode to load/store registers,
  * pointers etc.
  */
-#define REG_S		sd
-#define REG_L		ld
-#define REG_SUBU	dsubu
-#define REG_ADDU	daddu
+#define REG_S       sd
+#define REG_L       ld
+#define REG_SUBU    dsubu
+#define REG_ADDU    daddu
 
 /*
  * How to add/sub/load/store/shift C int variables.
  */
-#define INT_ADD		dadd
-#define INT_ADDU	daddu
-#define INT_ADDI	daddi
-#define INT_ADDIU	daddiu
-#define INT_SUB		dsub
-#define INT_SUBU	dsubu
-#define INT_L		ld
-#define INT_S		sd
-#define INT_SLL		dsll
-#define INT_SLLV	dsllv
-#define INT_SRL		dsrl
-#define INT_SRLV	dsrlv
-#define INT_SRA		dsra
-#define INT_SRAV	dsrav
+#define INT_ADD     dadd
+#define INT_ADDU    daddu
+#define INT_ADDI    daddi
+#define INT_ADDIU   daddiu
+#define INT_SUB     dsub
+#define INT_SUBU    dsubu
+#define INT_L       ld
+#define INT_S       sd
+#define INT_SLL     dsll
+#define INT_SLLV    dsllv
+#define INT_SRL     dsrl
+#define INT_SRLV    dsrlv
+#define INT_SRA     dsra
+#define INT_SRAV    dsrav
 
 /*
  * Use the following macros in assemblercode to load/store registers,
  * pointers etc.
  */
-#define LONG_ADD	dadd
-#define LONG_ADDU	daddu
-#define LONG_ADDI	daddi
-#define LONG_ADDIU	daddiu
-#define LONG_SUB	dsub
-#define LONG_SUBU	dsubu
-#define LONG_L		ld
-#define LONG_S		sd
-#define LONG_SP		sdp
-#define LONG_SLL	dsll
-#define LONG_SLLV	dsllv
-#define LONG_SRL	dsrl
-#define LONG_SRLV	dsrlv
-#define LONG_SRA	dsra
-#define LONG_SRAV	dsrav
+#define LONG_ADD    dadd
+#define LONG_ADDU   daddu
+#define LONG_ADDI   daddi
+#define LONG_ADDIU  daddiu
+#define LONG_SUB    dsub
+#define LONG_SUBU   dsubu
+#define LONG_L      ld
+#define LONG_S      sd
+#define LONG_SP     sdp
+#define LONG_SLL    dsll
+#define LONG_SLLV   dsllv
+#define LONG_SRL    dsrl
+#define LONG_SRLV   dsrlv
+#define LONG_SRA    dsra
+#define LONG_SRAV   dsrav
 
-#define LONG		.dword
-#define LONGSIZE	8
-#define LONGMASK	7
-#define LONGLOG		3
+#define LONG        .dword
+#define LONGSIZE    8
+#define LONGMASK    7
+#define LONGLOG     3
 
 /*
  * How to add/sub/load/store/shift pointers.
  */
-#define PTR_ADD		dadd
-#define PTR_ADDU	daddu
-#define PTR_ADDI	daddi
-#define PTR_ADDIU	daddiu
-#define PTR_SUB		dsub
-#define PTR_SUBU	dsubu
-#define PTR_L		ld
-#define PTR_S		sd
-#define PTR_LA		dla
-#define PTR_LI		dli
-#define PTR_SLL		dsll
-#define PTR_SLLV	dsllv
-#define PTR_SRL		dsrl
-#define PTR_SRLV	dsrlv
-#define PTR_SRA		dsra
-#define PTR_SRAV	dsrav
+#define PTR_ADD     dadd
+#define PTR_ADDU    daddu
+#define PTR_ADDI    daddi
+#define PTR_ADDIU   daddiu
+#define PTR_SUB     dsub
+#define PTR_SUBU    dsubu
+#define PTR_L       ld
+#define PTR_S       sd
+#define PTR_LA      dla
+#define PTR_LI      dli
+#define PTR_SLL     dsll
+#define PTR_SLLV    dsllv
+#define PTR_SRL     dsrl
+#define PTR_SRLV    dsrlv
+#define PTR_SRA     dsra
+#define PTR_SRAV    dsrav
 
-#define PTR_SCALESHIFT	3
+#define PTR_SCALESHIFT  3
 
-#define PTR		.dword
-#define PTRSIZE		8
-#define PTRLOG		3
+#define PTR     .dword
+#define PTRSIZE     8
+#define PTRLOG      3
 
-#define MFC0		dmfc0
-#define MTC0		dmtc0
+#define MFC0        dmfc0
+#define MTC0        dmtc0
 
 #else
 /*
  * Size of a register
  */
-#define SZREG	4
+#define SZREG   4
 
 
 /*
  * Use the following macros in assemblercode to load/store registers,
  * pointers etc.
  */
-#define REG_S		sw
-#define REG_L		lw
-#define REG_SUBU	subu
-#define REG_ADDU	addu
+#define REG_S       sw
+#define REG_L       lw
+#define REG_SUBU    subu
+#define REG_ADDU    addu
 
 
 /*
  * How to add/sub/load/store/shift C int variables.
  */
-#define INT_ADD		add
-#define INT_ADDU	addu
-#define INT_ADDI	addi
-#define INT_ADDIU	addiu
-#define INT_SUB		sub
-#define INT_SUBU	subu
-#define INT_L		lw
-#define INT_S		sw
-#define INT_SLL		sll
-#define INT_SLLV	sllv
-#define INT_SRL		srl
-#define INT_SRLV	srlv
-#define INT_SRA		sra
-#define INT_SRAV	srav
+#define INT_ADD     add
+#define INT_ADDU    addu
+#define INT_ADDI    addi
+#define INT_ADDIU   addiu
+#define INT_SUB     sub
+#define INT_SUBU    subu
+#define INT_L       lw
+#define INT_S       sw
+#define INT_SLL     sll
+#define INT_SLLV    sllv
+#define INT_SRL     srl
+#define INT_SRLV    srlv
+#define INT_SRA     sra
+#define INT_SRAV    srav
 
 
 
 /*
  * How to add/sub/load/store/shift C long variables.
  */
-#define LONG_ADD	add
-#define LONG_ADDU	addu
-#define LONG_ADDI	addi
-#define LONG_ADDIU	addiu
-#define LONG_SUB	sub
-#define LONG_SUBU	subu
-#define LONG_L		lw
-#define LONG_S		sw
-#define LONG_SLL	sll
-#define LONG_SLLV	sllv
-#define LONG_SRL	srl
-#define LONG_SRLV	srlv
-#define LONG_SRA	sra
-#define LONG_SRAV	srav
+#define LONG_ADD    add
+#define LONG_ADDU   addu
+#define LONG_ADDI   addi
+#define LONG_ADDIU  addiu
+#define LONG_SUB    sub
+#define LONG_SUBU   subu
+#define LONG_L      lw
+#define LONG_S      sw
+#define LONG_SLL    sll
+#define LONG_SLLV   sllv
+#define LONG_SRL    srl
+#define LONG_SRLV   srlv
+#define LONG_SRA    sra
+#define LONG_SRAV   srav
 
-#define LONG		.word
-#define LONGSIZE	4
-#define LONGMASK	3
-#define LONGLOG		2
+#define LONG        .word
+#define LONGSIZE    4
+#define LONGMASK    3
+#define LONGLOG     2
 
 
 
 /*
  * How to add/sub/load/store/shift pointers.
  */
-#define PTR_ADD		add
-#define PTR_ADDU	addu
-#define PTR_ADDI	addi
-#define PTR_ADDIU	addiu
-#define PTR_SUB		sub
-#define PTR_SUBU	subu
-#define PTR_L		lw
-#define PTR_S		sw
-#define PTR_LA		la
-#define PTR_SLL		sll
-#define PTR_SLLV	sllv
-#define PTR_SRL		srl
-#define PTR_SRLV	srlv
-#define PTR_SRA		sra
-#define PTR_SRAV	srav
+#define PTR_ADD     add
+#define PTR_ADDU    addu
+#define PTR_ADDI    addi
+#define PTR_ADDIU   addiu
+#define PTR_SUB     sub
+#define PTR_SUBU    subu
+#define PTR_L       lw
+#define PTR_S       sw
+#define PTR_LA      la
+#define PTR_SLL     sll
+#define PTR_SLLV    sllv
+#define PTR_SRL     srl
+#define PTR_SRLV    srlv
+#define PTR_SRA     sra
+#define PTR_SRAV    srav
 
-#define PTR_SCALESHIFT	2
+#define PTR_SCALESHIFT  2
 
-#define PTR			.word
-#define PTRSIZE		4
-#define PTRLOG		2
+#define PTR         .word
+#define PTRSIZE     4
+#define PTRLOG      2
 
 
 /*
  * Some cp0 registers were extended to 64bit for MIPS III.
  */
-#define MFC0		mfc0
-#define MTC0		mtc0
+#define MFC0        mfc0
+#define MTC0        mtc0
 
 #endif
 
-#define SSNOP		sll zero, zero, 1
+#define SSNOP       sll zero, zero, 1
 
 #endif /* end of __ASM_H__ */
diff --git a/libcpu/mips/common/exception.c b/libcpu/mips/common/exception.c
index 3da8ecead6..9c9858f5e1 100644
--- a/libcpu/mips/common/exception.c
+++ b/libcpu/mips/common/exception.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -164,7 +164,7 @@ void rt_general_exc_dispatch(struct pt_regs *regs)
 {
     rt_ubase_t cause, exccode;
     cause = read_c0_cause();
-    exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;    
+    exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
 
     if (exccode == 0)
     {
diff --git a/libcpu/mips/common/exception.h b/libcpu/mips/common/exception.h
index 68107f6235..af9312b5bc 100644
--- a/libcpu/mips/common/exception.h
+++ b/libcpu/mips/common/exception.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/mips/common/mips.h b/libcpu/mips/common/mips.h
index 94f664308c..abe3b73945 100644
--- a/libcpu/mips/common/mips.h
+++ b/libcpu/mips/common/mips.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/mips/common/mips_addrspace.h b/libcpu/mips/common/mips_addrspace.h
index f3bb60662e..0bc6a5f181 100644
--- a/libcpu/mips/common/mips_addrspace.h
+++ b/libcpu/mips/common/mips_addrspace.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -19,15 +19,15 @@
 #define _ATYPE_
 #define _ATYPE32_
 #define _ATYPE64_
-#define _CONST64_(x)	x
+#define _CONST64_(x)    x
 #else
-#define _ATYPE_		__PTRDIFF_TYPE__
-#define _ATYPE32_	int
-#define _ATYPE64_	__s64
+#define _ATYPE_     __PTRDIFF_TYPE__
+#define _ATYPE32_   int
+#define _ATYPE64_   __s64
 #ifdef ARCH_MIPS64
-#define _CONST64_(x)	x ## L
+#define _CONST64_(x)    x ## L
 #else
-#define _CONST64_(x)	x ## LL
+#define _CONST64_(x)    x ## LL
 #endif
 #endif
 
@@ -38,21 +38,21 @@
 #define _ACAST32_
 #define _ACAST64_
 #else
-#define _ACAST32_		(_ATYPE_)(_ATYPE32_)	/* widen if necessary */
-#define _ACAST64_		(_ATYPE64_)		/* do _not_ narrow */
+#define _ACAST32_       (_ATYPE_)(_ATYPE32_)    /* widen if necessary */
+#define _ACAST64_       (_ATYPE64_)     /* do _not_ narrow */
 #endif
 
 /*
  * Returns the kernel segment base of a given address
  */
-#define KSEGX(a)		((_ACAST32_ (a)) & 0xe0000000)
+#define KSEGX(a)        ((_ACAST32_ (a)) & 0xe0000000)
 
 /*
  * Returns the physical address of a CKSEGx / XKPHYS address
  */
-#define CPHYSADDR(a)		((_ACAST32_(a)) & 0x1fffffff)
-#define XPHYSADDR(a)		((_ACAST64_(a)) &			\
-				 _CONST64_(0x000000ffffffffff))
+#define CPHYSADDR(a)        ((_ACAST32_(a)) & 0x1fffffff)
+#define XPHYSADDR(a)        ((_ACAST64_(a)) &           \
+                 _CONST64_(0x000000ffffffffff))
 
 #ifdef ARCH_MIPS64
 
@@ -61,56 +61,56 @@
  * The compatibility segments use the full 64-bit sign extended value.  Note
  * the R8000 doesn't have them so don't reference these in generic MIPS code.
  */
-#define XKUSEG			_CONST64_(0x0000000000000000)
-#define XKSSEG			_CONST64_(0x4000000000000000)
-#define XKPHYS			_CONST64_(0x8000000000000000)
-#define XKSEG			_CONST64_(0xc000000000000000)
-#define CKSEG0			_CONST64_(0xffffffff80000000)
-#define CKSEG1			_CONST64_(0xffffffffa0000000)
-#define CKSSEG			_CONST64_(0xffffffffc0000000)
-#define CKSEG3			_CONST64_(0xffffffffe0000000)
+#define XKUSEG          _CONST64_(0x0000000000000000)
+#define XKSSEG          _CONST64_(0x4000000000000000)
+#define XKPHYS          _CONST64_(0x8000000000000000)
+#define XKSEG           _CONST64_(0xc000000000000000)
+#define CKSEG0          _CONST64_(0xffffffff80000000)
+#define CKSEG1          _CONST64_(0xffffffffa0000000)
+#define CKSSEG          _CONST64_(0xffffffffc0000000)
+#define CKSEG3          _CONST64_(0xffffffffe0000000)
 
-#define CKSEG0ADDR(a)		(CPHYSADDR(a) | CKSEG0)
-#define CKSEG1ADDR(a)		(CPHYSADDR(a) | CKSEG1)
-#define CKSEG2ADDR(a)		(CPHYSADDR(a) | CKSEG2)
-#define CKSEG3ADDR(a)		(CPHYSADDR(a) | CKSEG3)
+#define CKSEG0ADDR(a)       (CPHYSADDR(a) | CKSEG0)
+#define CKSEG1ADDR(a)       (CPHYSADDR(a) | CKSEG1)
+#define CKSEG2ADDR(a)       (CPHYSADDR(a) | CKSEG2)
+#define CKSEG3ADDR(a)       (CPHYSADDR(a) | CKSEG3)
 
-#define KUSEGBASE			0xffffffff00000000
-#define KSEG0BASE			0xffffffff80000000
-#define KSEG1BASE			0xffffffffa0000000
-#define KSEG2BASE			0xffffffffc0000000
-#define KSEG3BASE			0xffffffffe0000000
+#define KUSEGBASE           0xffffffff00000000
+#define KSEG0BASE           0xffffffff80000000
+#define KSEG1BASE           0xffffffffa0000000
+#define KSEG2BASE           0xffffffffc0000000
+#define KSEG3BASE           0xffffffffe0000000
 
 #else
 
-#define CKSEG0ADDR(a)		(CPHYSADDR(a) | KSEG0BASE)
-#define CKSEG1ADDR(a)		(CPHYSADDR(a) | KSEG1BASE)
-#define CKSEG2ADDR(a)		(CPHYSADDR(a) | KSEG2BASE)
-#define CKSEG3ADDR(a)		(CPHYSADDR(a) | KSEG3BASE)
+#define CKSEG0ADDR(a)       (CPHYSADDR(a) | KSEG0BASE)
+#define CKSEG1ADDR(a)       (CPHYSADDR(a) | KSEG1BASE)
+#define CKSEG2ADDR(a)       (CPHYSADDR(a) | KSEG2BASE)
+#define CKSEG3ADDR(a)       (CPHYSADDR(a) | KSEG3BASE)
 
 /*
  * Map an address to a certain kernel segment
  */
-#define KSEG0ADDR(a)		(CPHYSADDR(a) | KSEG0BASE)
-#define KSEG1ADDR(a)		(CPHYSADDR(a) | KSEG1BASE)
-#define KSEG2ADDR(a)		(CPHYSADDR(a) | KSEG2BASE)
-#define KSEG3ADDR(a)		(CPHYSADDR(a) | KSEG3BASE)
+#define KSEG0ADDR(a)        (CPHYSADDR(a) | KSEG0BASE)
+#define KSEG1ADDR(a)        (CPHYSADDR(a) | KSEG1BASE)
+#define KSEG2ADDR(a)        (CPHYSADDR(a) | KSEG2BASE)
+#define KSEG3ADDR(a)        (CPHYSADDR(a) | KSEG3BASE)
 
-#define CKUSEG			0x00000000
-#define CKSEG0			0x80000000
-#define CKSEG1			0xa0000000
-#define CKSEG2			0xc0000000
-#define CKSEG3			0xe0000000
+#define CKUSEG          0x00000000
+#define CKSEG0          0x80000000
+#define CKSEG1          0xa0000000
+#define CKSEG2          0xc0000000
+#define CKSEG3          0xe0000000
 
 /*
  * Memory segments (32bit kernel mode addresses)
  * These are the traditional names used in the 32-bit universe.
  */
-#define KUSEGBASE			0x00000000
-#define KSEG0BASE			0x80000000
-#define KSEG1BASE			0xa0000000
-#define KSEG2BASE			0xc0000000
-#define KSEG3BASE			0xe0000000
+#define KUSEGBASE           0x00000000
+#define KSEG0BASE           0x80000000
+#define KSEG1BASE           0xa0000000
+#define KSEG2BASE           0xc0000000
+#define KSEG3BASE           0xe0000000
 
 #endif
 
@@ -118,23 +118,23 @@
 /*
  * Cache modes for XKPHYS address conversion macros
  */
-#define K_CALG_COH_EXCL1_NOL2	0
-#define K_CALG_COH_SHRL1_NOL2	1
-#define K_CALG_UNCACHED		2
-#define K_CALG_NONCOHERENT	3
-#define K_CALG_COH_EXCL		4
-#define K_CALG_COH_SHAREABLE	5
-#define K_CALG_NOTUSED		6
-#define K_CALG_UNCACHED_ACCEL	7
+#define K_CALG_COH_EXCL1_NOL2   0
+#define K_CALG_COH_SHRL1_NOL2   1
+#define K_CALG_UNCACHED     2
+#define K_CALG_NONCOHERENT  3
+#define K_CALG_COH_EXCL     4
+#define K_CALG_COH_SHAREABLE    5
+#define K_CALG_NOTUSED      6
+#define K_CALG_UNCACHED_ACCEL   7
 
 /*
  * 64-bit address conversions
  */
-#define PHYS_TO_XKSEG_UNCACHED(p)	PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
-#define PHYS_TO_XKSEG_CACHED(p)		PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
-#define XKPHYS_TO_PHYS(p)		((p) & TO_PHYS_MASK)
-#define PHYS_TO_XKPHYS(cm, a)		(_CONST64_(0x8000000000000000) | \
-					 (_CONST64_(cm) << 59) | (a))
+#define PHYS_TO_XKSEG_UNCACHED(p)   PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
+#define PHYS_TO_XKSEG_CACHED(p)     PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
+#define XKPHYS_TO_PHYS(p)       ((p) & TO_PHYS_MASK)
+#define PHYS_TO_XKPHYS(cm, a)       (_CONST64_(0x8000000000000000) | \
+                     (_CONST64_(cm) << 59) | (a))
 
 /*
  * Returns the uncached address of a sdram address
@@ -146,20 +146,20 @@
  * the region, 3 bits for the CCA mode.  This leaves 59 bits of which the
  * R8000 implements most with its 48-bit physical address space.
  */
-#define TO_PHYS_MASK	_CONST64_(0x07ffffffffffffff)	/* 2^^59 - 1 */
-#define COMPAT_K1BASE32		_CONST64_(0xffffffffa0000000)
-#define PHYS_TO_COMPATK1(x)	((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
+#define TO_PHYS_MASK    _CONST64_(0x07ffffffffffffff)   /* 2^^59 - 1 */
+#define COMPAT_K1BASE32     _CONST64_(0xffffffffa0000000)
+#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
 
-#define KDM_TO_PHYS(x)		(_ACAST64_ (x) & TO_PHYS_MASK)
-#define PHYS_TO_K0(x)		(_ACAST64_ (x) | CAC_BASE)
+#define KDM_TO_PHYS(x)      (_ACAST64_ (x) & TO_PHYS_MASK)
+#define PHYS_TO_K0(x)       (_ACAST64_ (x) | CAC_BASE)
 #endif
 
 
 #ifndef __ASSEMBLY__
-#define REG8( addr )		  (*(volatile u8 *) (addr))
-#define REG16( addr )		  (*(volatile u16 *)(addr))
-#define REG32( addr )		  (*(volatile u32 *)(addr))
-#define REG64( addr )		  (*(volatile u64 *)(addr))
+#define REG8( addr )          (*(volatile u8 *) (addr))
+#define REG16( addr )         (*(volatile u16 *)(addr))
+#define REG32( addr )         (*(volatile u32 *)(addr))
+#define REG64( addr )         (*(volatile u64 *)(addr))
 #endif
 
 #endif /* _MIPS_ADDRSPACE_H_ */
diff --git a/libcpu/mips/common/mips_cache.c b/libcpu/mips/common/mips_cache.c
index 8c86bb131a..a969f5c751 100644
--- a/libcpu/mips/common/mips_cache.c
+++ b/libcpu/mips/common/mips_cache.c
@@ -1,21 +1,7 @@
 /*
- * File      : mips_cache.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -28,7 +14,7 @@
 extern void cache_init(rt_ubase_t cache_size, rt_ubase_t cache_line_size);
 void r4k_cache_init(void)
 {
-//	cache_init(dcache_size, cpu_dcache_line_size);
+//  cache_init(dcache_size, cpu_dcache_line_size);
 }
 
 void r4k_cache_flush_all(void)
@@ -45,7 +31,7 @@ void r4k_icache_flush_all(void)
 
 void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size)
 {
-	rt_ubase_t end, a;
+    rt_ubase_t end, a;
 
     if (size > g_mips_core.icache_size)
     {
@@ -53,7 +39,7 @@ void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size)
     }
     else
     {
-    	rt_ubase_t ic_lsize = g_mips_core.icache_line_size;
+        rt_ubase_t ic_lsize = g_mips_core.icache_line_size;
 
         a = addr & ~(ic_lsize - 1);
         end = ((addr + size) - 1) & ~(ic_lsize - 1);
@@ -69,8 +55,8 @@ void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size)
 
 void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size)
 {
-	rt_ubase_t end, a;
-	rt_ubase_t ic_lsize = g_mips_core.icache_line_size;
+    rt_ubase_t end, a;
+    rt_ubase_t ic_lsize = g_mips_core.icache_line_size;
 
     a = addr & ~(ic_lsize - 1);
     end = ((addr + size) - 1) & ~(ic_lsize - 1);
@@ -85,7 +71,7 @@ void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size)
 
 void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size)
 {
-	rt_ubase_t end, a;
+    rt_ubase_t end, a;
     rt_ubase_t dc_lsize = g_mips_core.dcache_line_size;
 
     a = addr & ~(dc_lsize - 1);
@@ -101,7 +87,7 @@ void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size)
 
 void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size)
 {
-	rt_ubase_t end, a;
+    rt_ubase_t end, a;
 
     if (size >= g_mips_core.dcache_size)
     {
@@ -109,7 +95,7 @@ void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size)
     }
     else
     {
-    	rt_ubase_t dc_lsize = g_mips_core.dcache_line_size;
+        rt_ubase_t dc_lsize = g_mips_core.dcache_line_size;
 
         a = addr & ~(dc_lsize - 1);
         end = ((addr + size) - 1) & ~(dc_lsize - 1);
diff --git a/libcpu/mips/common/mips_cache.h b/libcpu/mips/common/mips_cache.h
index 438dd76cde..4a459b1ae4 100644
--- a/libcpu/mips/common/mips_cache.h
+++ b/libcpu/mips/common/mips_cache.h
@@ -1,21 +1,7 @@
 /*
- * File      : mips_cache.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -116,7 +102,7 @@ enum dma_data_direction
 #define INDEX_STORE_DATA_D      0x1d
 #define INDEX_STORE_DATA_S      0x1f
 
-#define cache_op(op, addr)		    \
+#define cache_op(op, addr)          \
     __asm__ __volatile__(        \
         ".set   push\n"             \
         ".set   noreorder\n"        \
@@ -126,95 +112,95 @@ enum dma_data_direction
         :                           \
         : "i" (op), "R" (*(unsigned char *)(addr)))
 
-#define cache16_unroll32(base, op)					\
-	__asm__ __volatile__(						\
-	"	.set noreorder					\n"	\
-	"	.set mips3					\n"	\
-	"	cache %1, 0x000(%0); cache %1, 0x010(%0)	\n"	\
-	"	cache %1, 0x020(%0); cache %1, 0x030(%0)	\n"	\
-	"	cache %1, 0x040(%0); cache %1, 0x050(%0)	\n"	\
-	"	cache %1, 0x060(%0); cache %1, 0x070(%0)	\n"	\
-	"	cache %1, 0x080(%0); cache %1, 0x090(%0)	\n"	\
-	"	cache %1, 0x0a0(%0); cache %1, 0x0b0(%0)	\n"	\
-	"	cache %1, 0x0c0(%0); cache %1, 0x0d0(%0)	\n"	\
-	"	cache %1, 0x0e0(%0); cache %1, 0x0f0(%0)	\n"	\
-	"	cache %1, 0x100(%0); cache %1, 0x110(%0)	\n"	\
-	"	cache %1, 0x120(%0); cache %1, 0x130(%0)	\n"	\
-	"	cache %1, 0x140(%0); cache %1, 0x150(%0)	\n"	\
-	"	cache %1, 0x160(%0); cache %1, 0x170(%0)	\n"	\
-	"	cache %1, 0x180(%0); cache %1, 0x190(%0)	\n"	\
-	"	cache %1, 0x1a0(%0); cache %1, 0x1b0(%0)	\n"	\
-	"	cache %1, 0x1c0(%0); cache %1, 0x1d0(%0)	\n"	\
-	"	cache %1, 0x1e0(%0); cache %1, 0x1f0(%0)	\n"	\
-	"	.set mips0					\n"	\
-	"	.set reorder					\n"	\
-		:							\
-		: "r" (base),						\
-		  "i" (op));
+#define cache16_unroll32(base, op)                  \
+    __asm__ __volatile__(                       \
+    "   .set noreorder                  \n" \
+    "   .set mips3                  \n" \
+    "   cache %1, 0x000(%0); cache %1, 0x010(%0)    \n" \
+    "   cache %1, 0x020(%0); cache %1, 0x030(%0)    \n" \
+    "   cache %1, 0x040(%0); cache %1, 0x050(%0)    \n" \
+    "   cache %1, 0x060(%0); cache %1, 0x070(%0)    \n" \
+    "   cache %1, 0x080(%0); cache %1, 0x090(%0)    \n" \
+    "   cache %1, 0x0a0(%0); cache %1, 0x0b0(%0)    \n" \
+    "   cache %1, 0x0c0(%0); cache %1, 0x0d0(%0)    \n" \
+    "   cache %1, 0x0e0(%0); cache %1, 0x0f0(%0)    \n" \
+    "   cache %1, 0x100(%0); cache %1, 0x110(%0)    \n" \
+    "   cache %1, 0x120(%0); cache %1, 0x130(%0)    \n" \
+    "   cache %1, 0x140(%0); cache %1, 0x150(%0)    \n" \
+    "   cache %1, 0x160(%0); cache %1, 0x170(%0)    \n" \
+    "   cache %1, 0x180(%0); cache %1, 0x190(%0)    \n" \
+    "   cache %1, 0x1a0(%0); cache %1, 0x1b0(%0)    \n" \
+    "   cache %1, 0x1c0(%0); cache %1, 0x1d0(%0)    \n" \
+    "   cache %1, 0x1e0(%0); cache %1, 0x1f0(%0)    \n" \
+    "   .set mips0                  \n" \
+    "   .set reorder                    \n" \
+        :                           \
+        : "r" (base),                       \
+          "i" (op));
 
 
 static inline void flush_icache_line_indexed(rt_ubase_t addr)
 {
-	cache_op(INDEX_INVALIDATE_I, addr);
+    cache_op(INDEX_INVALIDATE_I, addr);
 }
 
 static inline void flush_dcache_line_indexed(rt_ubase_t addr)
 {
-	cache_op(INDEX_WRITEBACK_INV_D, addr);
+    cache_op(INDEX_WRITEBACK_INV_D, addr);
 }
 
 static inline void flush_icache_line(rt_ubase_t addr)
 {
-	cache_op(HIT_INVALIDATE_I, addr);
+    cache_op(HIT_INVALIDATE_I, addr);
 }
 
 static inline void lock_icache_line(rt_ubase_t addr)
 {
-	cache_op(FETCH_AND_LOCK_I, addr);
+    cache_op(FETCH_AND_LOCK_I, addr);
 }
 
 static inline void lock_dcache_line(rt_ubase_t addr)
 {
-	cache_op(FETCH_AND_LOCK_D, addr);
+    cache_op(FETCH_AND_LOCK_D, addr);
 }
 
 static inline void flush_dcache_line(rt_ubase_t addr)
 {
-	cache_op(HIT_WRITEBACK_INV_D, addr);
+    cache_op(HIT_WRITEBACK_INV_D, addr);
 }
 
 static inline void invalidate_dcache_line(rt_ubase_t addr)
 {
-	cache_op(HIT_INVALIDATE_D, addr);
+    cache_op(HIT_INVALIDATE_D, addr);
 }
 static inline void blast_dcache16(void)
 {
-	rt_ubase_t start = KSEG0BASE;
-	rt_ubase_t end = start + g_mips_core.dcache_size;
-	rt_ubase_t addr;
+    rt_ubase_t start = KSEG0BASE;
+    rt_ubase_t end = start + g_mips_core.dcache_size;
+    rt_ubase_t addr;
 
-	for (addr = start; addr < end; addr += g_mips_core.dcache_line_size)
-		cache16_unroll32(addr, INDEX_WRITEBACK_INV_D);
+    for (addr = start; addr < end; addr += g_mips_core.dcache_line_size)
+        cache16_unroll32(addr, INDEX_WRITEBACK_INV_D);
 }
 
 static inline void inv_dcache16(void)
 {
-	rt_ubase_t start = KSEG0BASE;
-	rt_ubase_t end = start + g_mips_core.dcache_size;
-	rt_ubase_t addr;
+    rt_ubase_t start = KSEG0BASE;
+    rt_ubase_t end = start + g_mips_core.dcache_size;
+    rt_ubase_t addr;
 
-	for (addr = start; addr < end; addr += g_mips_core.dcache_line_size)
-		cache16_unroll32(addr, HIT_INVALIDATE_D);
+    for (addr = start; addr < end; addr += g_mips_core.dcache_line_size)
+        cache16_unroll32(addr, HIT_INVALIDATE_D);
 }
 
 static inline void blast_icache16(void)
 {
-	rt_ubase_t start = KSEG0BASE;
-	rt_ubase_t end = start + g_mips_core.icache_size;
-	rt_ubase_t addr;
+    rt_ubase_t start = KSEG0BASE;
+    rt_ubase_t end = start + g_mips_core.icache_size;
+    rt_ubase_t addr;
 
-	for (addr = start; addr < end; addr += g_mips_core.icache_line_size)
-		cache16_unroll32(addr, INDEX_INVALIDATE_I);
+    for (addr = start; addr < end; addr += g_mips_core.icache_line_size)
+        cache16_unroll32(addr, INDEX_INVALIDATE_I);
 }
 
 void r4k_cache_init(void);
diff --git a/libcpu/mips/common/mips_cfg.h b/libcpu/mips/common/mips_cfg.h
index f7e38b4af4..d5531e35fb 100644
--- a/libcpu/mips/common/mips_cfg.h
+++ b/libcpu/mips/common/mips_cfg.h
@@ -1,21 +1,7 @@
 /*
- * File      : mips_cfg.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -38,7 +24,7 @@ typedef struct mips32_core_cfg
     uint16_t dcache_ways;
     uint16_t dcache_size;
 
-    uint16_t max_tlb_entries;	/* number of tlb entry */
+    uint16_t max_tlb_entries;   /* number of tlb entry */
 } mips32_core_cfg_t;
 
 extern mips32_core_cfg_t g_mips_core;
diff --git a/libcpu/mips/common/mips_fpu.h b/libcpu/mips/common/mips_fpu.h
index 50df3746a5..85aa125fa3 100644
--- a/libcpu/mips/common/mips_fpu.h
+++ b/libcpu/mips/common/mips_fpu.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/mips/common/mips_regs.h b/libcpu/mips/common/mips_regs.h
index a13e24b539..a2f6053cf5 100644
--- a/libcpu/mips/common/mips_regs.h
+++ b/libcpu/mips/common/mips_regs.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -11,129 +11,129 @@
 #ifndef _MIPS_REGS_H_
 #define _MIPS_REGS_H_
 #include 
-#define REG_A0	4
-#define REG_SP	29
-#define REG_GP	28
-#define REG_FP	30
-#define REG_RA	31
+#define REG_A0  4
+#define REG_SP  29
+#define REG_GP  28
+#define REG_FP  30
+#define REG_RA  31
 
 #ifndef ARCH_MIPS64
-#define zero	$0	/* wired zero */
-#define AT	$1	/* assembler temp  - uppercase because of ".set at" */
-#define v0	$2	/* return value */
-#define v1	$3
-#define a0	$4	/* argument registers */
-#define a1	$5
-#define a2	$6
-#define a3	$7
-#define t0	$8	/* caller saved */
-#define t1	$9
-#define t2	$10
-#define t3	$11
-#define t4	$12
-#define ta0	$12
-#define t5	$13
-#define ta1	$13
-#define t6	$14
-#define ta2	$14
-#define t7	$15
-#define ta3	$15
-#define s0	$16	/* callee saved */
-#define s1	$17
-#define s2	$18
-#define s3	$19
-#define s4	$20
-#define s5	$21
-#define s6	$22
-#define s7	$23
-#define t8	$24	/* caller saved */
-#define t9	$25
-#define jp	$25	/* PIC jump register */
-#define k0	$26	/* kernel scratch */
-#define k1	$27
-#define gp	$28	/* global pointer */
-#define sp	$29	/* stack pointer */
-#define fp	$30	/* frame pointer */
-#define s8	$30	/* same like fp! */
-#define ra	$31	/* return address */
+#define zero    $0  /* wired zero */
+#define AT  $1  /* assembler temp  - uppercase because of ".set at" */
+#define v0  $2  /* return value */
+#define v1  $3
+#define a0  $4  /* argument registers */
+#define a1  $5
+#define a2  $6
+#define a3  $7
+#define t0  $8  /* caller saved */
+#define t1  $9
+#define t2  $10
+#define t3  $11
+#define t4  $12
+#define ta0 $12
+#define t5  $13
+#define ta1 $13
+#define t6  $14
+#define ta2 $14
+#define t7  $15
+#define ta3 $15
+#define s0  $16 /* callee saved */
+#define s1  $17
+#define s2  $18
+#define s3  $19
+#define s4  $20
+#define s5  $21
+#define s6  $22
+#define s7  $23
+#define t8  $24 /* caller saved */
+#define t9  $25
+#define jp  $25 /* PIC jump register */
+#define k0  $26 /* kernel scratch */
+#define k1  $27
+#define gp  $28 /* global pointer */
+#define sp  $29 /* stack pointer */
+#define fp  $30 /* frame pointer */
+#define s8  $30 /* same like fp! */
+#define ra  $31 /* return address */
 
 #else
 
-#define zero	$0	/* wired zero */
-#define AT	$at	/* assembler temp - uppercase because of ".set at" */
-#define v0	$2	/* return value - caller saved */
-#define v1	$3
-#define a0	$4	/* argument registers */
-#define a1	$5
-#define a2	$6
-#define a3	$7
-#define a4	$8	/* arg reg 64 bit; caller saved in 32 bit */
-#define ta0	$8
-#define a5	$9
-#define ta1	$9
-#define a6	$10
-#define ta2	$10
-#define a7	$11
-#define ta3	$11
-#define t0	$12	/* caller saved */
-#define t1	$13
-#define t2	$14
-#define t3	$15
-#define s0	$16	/* callee saved */
-#define s1	$17
-#define s2	$18
-#define s3	$19
-#define s4	$20
-#define s5	$21
-#define s6	$22
-#define s7	$23
-#define t8	$24	/* caller saved */
-#define t9	$25	/* callee address for PIC/temp */
-#define jp	$25	/* PIC jump register */
-#define k0	$26	/* kernel temporary */
-#define k1	$27
-#define gp	$28	/* global pointer - caller saved for PIC */
-#define sp	$29	/* stack pointer */
-#define fp	$30	/* frame pointer */
-#define s8	$30	/* callee saved */
-#define ra	$31	/* return address */
+#define zero    $0  /* wired zero */
+#define AT  $at /* assembler temp - uppercase because of ".set at" */
+#define v0  $2  /* return value - caller saved */
+#define v1  $3
+#define a0  $4  /* argument registers */
+#define a1  $5
+#define a2  $6
+#define a3  $7
+#define a4  $8  /* arg reg 64 bit; caller saved in 32 bit */
+#define ta0 $8
+#define a5  $9
+#define ta1 $9
+#define a6  $10
+#define ta2 $10
+#define a7  $11
+#define ta3 $11
+#define t0  $12 /* caller saved */
+#define t1  $13
+#define t2  $14
+#define t3  $15
+#define s0  $16 /* callee saved */
+#define s1  $17
+#define s2  $18
+#define s3  $19
+#define s4  $20
+#define s5  $21
+#define s6  $22
+#define s7  $23
+#define t8  $24 /* caller saved */
+#define t9  $25 /* callee address for PIC/temp */
+#define jp  $25 /* PIC jump register */
+#define k0  $26 /* kernel temporary */
+#define k1  $27
+#define gp  $28 /* global pointer - caller saved for PIC */
+#define sp  $29 /* stack pointer */
+#define fp  $30 /* frame pointer */
+#define s8  $30 /* callee saved */
+#define ra  $31 /* return address */
 
 #endif
 
-#define fv0	$f0	 /* return value */
-#define fv0f	$f1
-#define fv1	$f2
-#define fv1f	$f3
-#define fa0	$f12	 /* argument registers */
-#define fa0f	$f13
-#define fa1	$f14
-#define fa1f	$f15
-#define ft0	$f4	 /* caller saved */
-#define ft0f	$f5
-#define ft1	$f6
-#define ft1f	$f7
-#define ft2	$f8
-#define ft2f	$f9
-#define ft3	$f10
-#define ft3f	$f11
-#define ft4	$f16
-#define ft4f	$f17
-#define ft5	$f18
-#define ft5f	$f19
-#define fs0	$f20	 /* callee saved */
-#define fs0f	$f21
-#define fs1	$f22
-#define fs1f	$f23
-#define fs2	$f24
-#define fs2f	$f25
-#define fs3	$f26
-#define fs3f	$f27
-#define fs4	$f28
-#define fs4f	$f29
-#define fs5	$f30
-#define fs5f	$f31
+#define fv0 $f0  /* return value */
+#define fv0f    $f1
+#define fv1 $f2
+#define fv1f    $f3
+#define fa0 $f12     /* argument registers */
+#define fa0f    $f13
+#define fa1 $f14
+#define fa1f    $f15
+#define ft0 $f4  /* caller saved */
+#define ft0f    $f5
+#define ft1 $f6
+#define ft1f    $f7
+#define ft2 $f8
+#define ft2f    $f9
+#define ft3 $f10
+#define ft3f    $f11
+#define ft4 $f16
+#define ft4f    $f17
+#define ft5 $f18
+#define ft5f    $f19
+#define fs0 $f20     /* callee saved */
+#define fs0f    $f21
+#define fs1 $f22
+#define fs1f    $f23
+#define fs2 $f24
+#define fs2f    $f25
+#define fs3 $f26
+#define fs3f    $f27
+#define fs4 $f28
+#define fs4f    $f29
+#define fs5 $f30
+#define fs5f    $f31
 
-#define fcr31	$31	 /* FPU status register */
+#define fcr31   $31  /* FPU status register */
 
 
 /*
@@ -217,157 +217,157 @@
 /*
  *  TX39 Series
  */
-#define CP0_TX39_CACHE	$7
+#define CP0_TX39_CACHE  $7
 
 /*
  * Coprocessor 1 (FPU) register names
  */
-#define CP1_REVISION	$0
-#define CP1_UFR		$1
-#define CP1_UNFR	$4
-#define CP1_FCCR	$25
-#define CP1_FEXR	$26
-#define CP1_FENR	$28
-#define CP1_STATUS	$31
+#define CP1_REVISION    $0
+#define CP1_UFR     $1
+#define CP1_UNFR    $4
+#define CP1_FCCR    $25
+#define CP1_FEXR    $26
+#define CP1_FENR    $28
+#define CP1_STATUS  $31
 
 
 /*
  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
  */
-#define MIPS_FPIR_S		(_ULCAST_(1) << 16)
-#define MIPS_FPIR_D		(_ULCAST_(1) << 17)
-#define MIPS_FPIR_PS		(_ULCAST_(1) << 18)
-#define MIPS_FPIR_3D		(_ULCAST_(1) << 19)
-#define MIPS_FPIR_W		(_ULCAST_(1) << 20)
-#define MIPS_FPIR_L		(_ULCAST_(1) << 21)
-#define MIPS_FPIR_F64		(_ULCAST_(1) << 22)
-#define MIPS_FPIR_HAS2008	(_ULCAST_(1) << 23)
-#define MIPS_FPIR_UFRP		(_ULCAST_(1) << 28)
-#define MIPS_FPIR_FREP		(_ULCAST_(1) << 29)
+#define MIPS_FPIR_S     (_ULCAST_(1) << 16)
+#define MIPS_FPIR_D     (_ULCAST_(1) << 17)
+#define MIPS_FPIR_PS        (_ULCAST_(1) << 18)
+#define MIPS_FPIR_3D        (_ULCAST_(1) << 19)
+#define MIPS_FPIR_W     (_ULCAST_(1) << 20)
+#define MIPS_FPIR_L     (_ULCAST_(1) << 21)
+#define MIPS_FPIR_F64       (_ULCAST_(1) << 22)
+#define MIPS_FPIR_HAS2008   (_ULCAST_(1) << 23)
+#define MIPS_FPIR_UFRP      (_ULCAST_(1) << 28)
+#define MIPS_FPIR_FREP      (_ULCAST_(1) << 29)
 
 /*
  * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
  */
-#define MIPS_FCCR_CONDX_S	0
-#define MIPS_FCCR_CONDX		(_ULCAST_(255) << MIPS_FCCR_CONDX_S)
-#define MIPS_FCCR_COND0_S	0
-#define MIPS_FCCR_COND0		(_ULCAST_(1) << MIPS_FCCR_COND0_S)
-#define MIPS_FCCR_COND1_S	1
-#define MIPS_FCCR_COND1		(_ULCAST_(1) << MIPS_FCCR_COND1_S)
-#define MIPS_FCCR_COND2_S	2
-#define MIPS_FCCR_COND2		(_ULCAST_(1) << MIPS_FCCR_COND2_S)
-#define MIPS_FCCR_COND3_S	3
-#define MIPS_FCCR_COND3		(_ULCAST_(1) << MIPS_FCCR_COND3_S)
-#define MIPS_FCCR_COND4_S	4
-#define MIPS_FCCR_COND4		(_ULCAST_(1) << MIPS_FCCR_COND4_S)
-#define MIPS_FCCR_COND5_S	5
-#define MIPS_FCCR_COND5		(_ULCAST_(1) << MIPS_FCCR_COND5_S)
-#define MIPS_FCCR_COND6_S	6
-#define MIPS_FCCR_COND6		(_ULCAST_(1) << MIPS_FCCR_COND6_S)
-#define MIPS_FCCR_COND7_S	7
-#define MIPS_FCCR_COND7		(_ULCAST_(1) << MIPS_FCCR_COND7_S)
+#define MIPS_FCCR_CONDX_S   0
+#define MIPS_FCCR_CONDX     (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
+#define MIPS_FCCR_COND0_S   0
+#define MIPS_FCCR_COND0     (_ULCAST_(1) << MIPS_FCCR_COND0_S)
+#define MIPS_FCCR_COND1_S   1
+#define MIPS_FCCR_COND1     (_ULCAST_(1) << MIPS_FCCR_COND1_S)
+#define MIPS_FCCR_COND2_S   2
+#define MIPS_FCCR_COND2     (_ULCAST_(1) << MIPS_FCCR_COND2_S)
+#define MIPS_FCCR_COND3_S   3
+#define MIPS_FCCR_COND3     (_ULCAST_(1) << MIPS_FCCR_COND3_S)
+#define MIPS_FCCR_COND4_S   4
+#define MIPS_FCCR_COND4     (_ULCAST_(1) << MIPS_FCCR_COND4_S)
+#define MIPS_FCCR_COND5_S   5
+#define MIPS_FCCR_COND5     (_ULCAST_(1) << MIPS_FCCR_COND5_S)
+#define MIPS_FCCR_COND6_S   6
+#define MIPS_FCCR_COND6     (_ULCAST_(1) << MIPS_FCCR_COND6_S)
+#define MIPS_FCCR_COND7_S   7
+#define MIPS_FCCR_COND7     (_ULCAST_(1) << MIPS_FCCR_COND7_S)
 
 /*
  * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
  */
-#define MIPS_FENR_FS_S		2
-#define MIPS_FENR_FS		(_ULCAST_(1) << MIPS_FENR_FS_S)
+#define MIPS_FENR_FS_S      2
+#define MIPS_FENR_FS        (_ULCAST_(1) << MIPS_FENR_FS_S)
 
 /*
  * FPU Status Register Values
  */
-#define FPU_CSR_COND_S	23					/* $fcc0 */
-#define FPU_CSR_COND	(_ULCAST_(1) << FPU_CSR_COND_S)
+#define FPU_CSR_COND_S  23                  /* $fcc0 */
+#define FPU_CSR_COND    (_ULCAST_(1) << FPU_CSR_COND_S)
 
-#define FPU_CSR_FS_S	24		/* flush denormalised results to 0 */
-#define FPU_CSR_FS	(_ULCAST_(1) << FPU_CSR_FS_S)
+#define FPU_CSR_FS_S    24      /* flush denormalised results to 0 */
+#define FPU_CSR_FS  (_ULCAST_(1) << FPU_CSR_FS_S)
 
 #define FPU_CSR_FO      0x00400000
 #define FPU_CSR_FN      0x00200000
 
-#define FPU_CSR_CONDX_S	25					/* $fcc[7:1] */
-#define FPU_CSR_CONDX	(_ULCAST_(127) << FPU_CSR_CONDX_S)
-#define FPU_CSR_COND1_S	25					/* $fcc1 */
-#define FPU_CSR_COND1	(_ULCAST_(1) << FPU_CSR_COND1_S)
-#define FPU_CSR_COND2_S	26					/* $fcc2 */
-#define FPU_CSR_COND2	(_ULCAST_(1) << FPU_CSR_COND2_S)
-#define FPU_CSR_COND3_S	27					/* $fcc3 */
-#define FPU_CSR_COND3	(_ULCAST_(1) << FPU_CSR_COND3_S)
-#define FPU_CSR_COND4_S	28					/* $fcc4 */
-#define FPU_CSR_COND4	(_ULCAST_(1) << FPU_CSR_COND4_S)
-#define FPU_CSR_COND5_S	29					/* $fcc5 */
-#define FPU_CSR_COND5	(_ULCAST_(1) << FPU_CSR_COND5_S)
-#define FPU_CSR_COND6_S	30					/* $fcc6 */
-#define FPU_CSR_COND6	(_ULCAST_(1) << FPU_CSR_COND6_S)
-#define FPU_CSR_COND7_S	31					/* $fcc7 */
-#define FPU_CSR_COND7	(_ULCAST_(1) << FPU_CSR_COND7_S)
+#define FPU_CSR_CONDX_S 25                  /* $fcc[7:1] */
+#define FPU_CSR_CONDX   (_ULCAST_(127) << FPU_CSR_CONDX_S)
+#define FPU_CSR_COND1_S 25                  /* $fcc1 */
+#define FPU_CSR_COND1   (_ULCAST_(1) << FPU_CSR_COND1_S)
+#define FPU_CSR_COND2_S 26                  /* $fcc2 */
+#define FPU_CSR_COND2   (_ULCAST_(1) << FPU_CSR_COND2_S)
+#define FPU_CSR_COND3_S 27                  /* $fcc3 */
+#define FPU_CSR_COND3   (_ULCAST_(1) << FPU_CSR_COND3_S)
+#define FPU_CSR_COND4_S 28                  /* $fcc4 */
+#define FPU_CSR_COND4   (_ULCAST_(1) << FPU_CSR_COND4_S)
+#define FPU_CSR_COND5_S 29                  /* $fcc5 */
+#define FPU_CSR_COND5   (_ULCAST_(1) << FPU_CSR_COND5_S)
+#define FPU_CSR_COND6_S 30                  /* $fcc6 */
+#define FPU_CSR_COND6   (_ULCAST_(1) << FPU_CSR_COND6_S)
+#define FPU_CSR_COND7_S 31                  /* $fcc7 */
+#define FPU_CSR_COND7   (_ULCAST_(1) << FPU_CSR_COND7_S)
 
 /*
  * Bits 22:20 of the FPU Status Register will be read as 0,
  * and should be written as zero.
  */
-#define FPU_CSR_RSVD	(_ULCAST_(7) << 20)
+#define FPU_CSR_RSVD    (_ULCAST_(7) << 20)
 
-#define FPU_CSR_ABS2008	(_ULCAST_(1) << 19)
-#define FPU_CSR_NAN2008	(_ULCAST_(1) << 18)
+#define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
+#define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
 
 /*
  * X the exception cause indicator
  * E the exception enable
  * S the sticky/flag bit
 */
-#define FPU_CSR_ALL_X	0x0003f000
-#define FPU_CSR_UNI_X	0x00020000
-#define FPU_CSR_INV_X	0x00010000
-#define FPU_CSR_DIV_X	0x00008000
-#define FPU_CSR_OVF_X	0x00004000
-#define FPU_CSR_UDF_X	0x00002000
-#define FPU_CSR_INE_X	0x00001000
+#define FPU_CSR_ALL_X   0x0003f000
+#define FPU_CSR_UNI_X   0x00020000
+#define FPU_CSR_INV_X   0x00010000
+#define FPU_CSR_DIV_X   0x00008000
+#define FPU_CSR_OVF_X   0x00004000
+#define FPU_CSR_UDF_X   0x00002000
+#define FPU_CSR_INE_X   0x00001000
 
-#define FPU_CSR_ALL_E	0x00000f80
-#define FPU_CSR_INV_E	0x00000800
-#define FPU_CSR_DIV_E	0x00000400
-#define FPU_CSR_OVF_E	0x00000200
-#define FPU_CSR_UDF_E	0x00000100
-#define FPU_CSR_INE_E	0x00000080
+#define FPU_CSR_ALL_E   0x00000f80
+#define FPU_CSR_INV_E   0x00000800
+#define FPU_CSR_DIV_E   0x00000400
+#define FPU_CSR_OVF_E   0x00000200
+#define FPU_CSR_UDF_E   0x00000100
+#define FPU_CSR_INE_E   0x00000080
 
-#define FPU_CSR_ALL_S	0x0000007c
-#define FPU_CSR_INV_S	0x00000040
-#define FPU_CSR_DIV_S	0x00000020
-#define FPU_CSR_OVF_S	0x00000010
-#define FPU_CSR_UDF_S	0x00000008
-#define FPU_CSR_INE_S	0x00000004
+#define FPU_CSR_ALL_S   0x0000007c
+#define FPU_CSR_INV_S   0x00000040
+#define FPU_CSR_DIV_S   0x00000020
+#define FPU_CSR_OVF_S   0x00000010
+#define FPU_CSR_UDF_S   0x00000008
+#define FPU_CSR_INE_S   0x00000004
 
 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
-#define FPU_CSR_RM	0x00000003
-#define FPU_CSR_RN	0x0	/* nearest */
-#define FPU_CSR_RZ	0x1	/* towards zero */
-#define FPU_CSR_RU	0x2	/* towards +Infinity */
-#define FPU_CSR_RD	0x3	/* towards -Infinity */
+#define FPU_CSR_RM  0x00000003
+#define FPU_CSR_RN  0x0 /* nearest */
+#define FPU_CSR_RZ  0x1 /* towards zero */
+#define FPU_CSR_RU  0x2 /* towards +Infinity */
+#define FPU_CSR_RD  0x3 /* towards -Infinity */
 
-#define PM_4K		0x00000000
-#define PM_16K		0x00006000
-#define PM_64K		0x0001e000
-#define PM_256K		0x0007e000
-#define PM_1M		0x001fe000
-#define PM_4M		0x007fe000
-#define PM_16M		0x01ffe000
-#define PM_64M		0x07ffe000
-#define PM_256M		0x1fffe000
+#define PM_4K       0x00000000
+#define PM_16K      0x00006000
+#define PM_64K      0x0001e000
+#define PM_256K     0x0007e000
+#define PM_1M       0x001fe000
+#define PM_4M       0x007fe000
+#define PM_16M      0x01ffe000
+#define PM_64M      0x07ffe000
+#define PM_256M     0x1fffe000
 
 
 /*
  * Values used for computation of new tlb entries
  */
-#define PL_4K		12
-#define PL_16K		14
-#define PL_64K		16
-#define PL_256K		18
-#define PL_1M		20
-#define PL_4M		22
-#define PL_16M		24
-#define PL_64M		26
-#define PL_256M		28
+#define PL_4K       12
+#define PL_16K      14
+#define PL_64K      16
+#define PL_256K     18
+#define PL_1M       20
+#define PL_4M       22
+#define PL_16M      24
+#define PL_64M      26
+#define PL_256M     28
 
 /*
  * R4x00 interrupt enable / cause bits
@@ -396,202 +396,202 @@
 /*
  * Bitfields in the R4xx0 cp0 status register
  */
-#define ST0_IE			0x00000001
-#define ST0_EXL			0x00000002
-#define ST0_ERL			0x00000004
-#define ST0_KSU			0x00000018
-#  define KSU_USER		0x00000010
-#  define KSU_SUPERVISOR	0x00000008
-#  define KSU_KERNEL		0x00000000
-#define ST0_UX			0x00000020
-#define ST0_SX			0x00000040
-#define ST0_KX 			0x00000080
-#define ST0_DE			0x00010000
-#define ST0_CE			0x00020000
+#define ST0_IE          0x00000001
+#define ST0_EXL         0x00000002
+#define ST0_ERL         0x00000004
+#define ST0_KSU         0x00000018
+#  define KSU_USER      0x00000010
+#  define KSU_SUPERVISOR    0x00000008
+#  define KSU_KERNEL        0x00000000
+#define ST0_UX          0x00000020
+#define ST0_SX          0x00000040
+#define ST0_KX          0x00000080
+#define ST0_DE          0x00010000
+#define ST0_CE          0x00020000
 
 /*
  * Bitfields in the R[23]000 cp0 status register.
  */
 #define ST0_IEC                 0x00000001
-#define ST0_KUC			0x00000002
-#define ST0_IEP			0x00000004
-#define ST0_KUP			0x00000008
-#define ST0_IEO			0x00000010
-#define ST0_KUO			0x00000020
+#define ST0_KUC         0x00000002
+#define ST0_IEP         0x00000004
+#define ST0_KUP         0x00000008
+#define ST0_IEO         0x00000010
+#define ST0_KUO         0x00000020
 /* bits 6 & 7 are reserved on R[23]000 */
-#define ST0_ISC			0x00010000
-#define ST0_SWC			0x00020000
-#define ST0_CM			0x00080000
+#define ST0_ISC         0x00010000
+#define ST0_SWC         0x00020000
+#define ST0_CM          0x00080000
 
 /*
  * Bits specific to the R4640/R4650
  */
-#define ST0_UM			(_ULCAST_(1) <<  4)
-#define ST0_IL			(_ULCAST_(1) << 23)
-#define ST0_DL			(_ULCAST_(1) << 24)
+#define ST0_UM          (_ULCAST_(1) <<  4)
+#define ST0_IL          (_ULCAST_(1) << 23)
+#define ST0_DL          (_ULCAST_(1) << 24)
 
 
 /*
  * Status register bits available in all MIPS CPUs.
  */
-#define ST0_IM			0x0000ff00
-#define  STATUSB_IP0		8
-#define  STATUSF_IP0		(_ULCAST_(1) <<  8)
-#define  STATUSB_IP1		9
-#define  STATUSF_IP1		(_ULCAST_(1) <<  9)
-#define  STATUSB_IP2		10
-#define  STATUSF_IP2		(_ULCAST_(1) << 10)
-#define  STATUSB_IP3		11
-#define  STATUSF_IP3		(_ULCAST_(1) << 11)
-#define  STATUSB_IP4		12
-#define  STATUSF_IP4		(_ULCAST_(1) << 12)
-#define  STATUSB_IP5		13
-#define  STATUSF_IP5		(_ULCAST_(1) << 13)
-#define  STATUSB_IP6		14
-#define  STATUSF_IP6		(_ULCAST_(1) << 14)
-#define  STATUSB_IP7		15
-#define  STATUSF_IP7		(_ULCAST_(1) << 15)
-#define  STATUSB_IP8		0
-#define  STATUSF_IP8		(_ULCAST_(1) <<  0)
-#define  STATUSB_IP9		1
-#define  STATUSF_IP9		(_ULCAST_(1) <<  1)
-#define  STATUSB_IP10		2
-#define  STATUSF_IP10		(_ULCAST_(1) <<  2)
-#define  STATUSB_IP11		3
-#define  STATUSF_IP11		(_ULCAST_(1) <<  3)
-#define  STATUSB_IP12		4
-#define  STATUSF_IP12		(_ULCAST_(1) <<  4)
-#define  STATUSB_IP13		5
-#define  STATUSF_IP13		(_ULCAST_(1) <<  5)
-#define  STATUSB_IP14		6
-#define  STATUSF_IP14		(_ULCAST_(1) <<  6)
-#define  STATUSB_IP15		7
-#define  STATUSF_IP15		(_ULCAST_(1) <<  7)
-#define ST0_CH			0x00040000
-#define ST0_SR			0x00100000
-#define ST0_TS			0x00200000
-#define ST0_BEV			0x00400000
-#define ST0_RE			0x02000000
-#define ST0_FR			0x04000000
-#define ST0_CU			0xf0000000
-#define ST0_CU0			0x10000000
-#define ST0_CU1			0x20000000
-#define ST0_CU1_SHIFT			29
-#define ST0_CU2			0x40000000
-#define ST0_CU3			0x80000000
-#define ST0_XX			0x80000000	/* MIPS IV naming */
+#define ST0_IM          0x0000ff00
+#define  STATUSB_IP0        8
+#define  STATUSF_IP0        (_ULCAST_(1) <<  8)
+#define  STATUSB_IP1        9
+#define  STATUSF_IP1        (_ULCAST_(1) <<  9)
+#define  STATUSB_IP2        10
+#define  STATUSF_IP2        (_ULCAST_(1) << 10)
+#define  STATUSB_IP3        11
+#define  STATUSF_IP3        (_ULCAST_(1) << 11)
+#define  STATUSB_IP4        12
+#define  STATUSF_IP4        (_ULCAST_(1) << 12)
+#define  STATUSB_IP5        13
+#define  STATUSF_IP5        (_ULCAST_(1) << 13)
+#define  STATUSB_IP6        14
+#define  STATUSF_IP6        (_ULCAST_(1) << 14)
+#define  STATUSB_IP7        15
+#define  STATUSF_IP7        (_ULCAST_(1) << 15)
+#define  STATUSB_IP8        0
+#define  STATUSF_IP8        (_ULCAST_(1) <<  0)
+#define  STATUSB_IP9        1
+#define  STATUSF_IP9        (_ULCAST_(1) <<  1)
+#define  STATUSB_IP10       2
+#define  STATUSF_IP10       (_ULCAST_(1) <<  2)
+#define  STATUSB_IP11       3
+#define  STATUSF_IP11       (_ULCAST_(1) <<  3)
+#define  STATUSB_IP12       4
+#define  STATUSF_IP12       (_ULCAST_(1) <<  4)
+#define  STATUSB_IP13       5
+#define  STATUSF_IP13       (_ULCAST_(1) <<  5)
+#define  STATUSB_IP14       6
+#define  STATUSF_IP14       (_ULCAST_(1) <<  6)
+#define  STATUSB_IP15       7
+#define  STATUSF_IP15       (_ULCAST_(1) <<  7)
+#define ST0_CH          0x00040000
+#define ST0_SR          0x00100000
+#define ST0_TS          0x00200000
+#define ST0_BEV         0x00400000
+#define ST0_RE          0x02000000
+#define ST0_FR          0x04000000
+#define ST0_CU          0xf0000000
+#define ST0_CU0         0x10000000
+#define ST0_CU1         0x20000000
+#define ST0_CU1_SHIFT           29
+#define ST0_CU2         0x40000000
+#define ST0_CU3         0x80000000
+#define ST0_XX          0x80000000  /* MIPS IV naming */
 
 /*
  * Bitfields and bit numbers in the coprocessor 0 cause register.
  *
  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
  */
-#define  CAUSEB_EXCCODE		2
-#define  CAUSEF_EXCCODE		(_ULCAST_(31)  <<  2)
-#define  CAUSEB_IP		8
-#define  CAUSEF_IP		(_ULCAST_(255) <<  8)
-#define  CAUSEB_IP0		8
-#define  CAUSEF_IP0		(_ULCAST_(1)   <<  8)
-#define  CAUSEB_IP1		9
-#define  CAUSEF_IP1		(_ULCAST_(1)   <<  9)
-#define  CAUSEB_IP2		10
-#define  CAUSEF_IP2		(_ULCAST_(1)   << 10)
-#define  CAUSEB_IP3		11
-#define  CAUSEF_IP3		(_ULCAST_(1)   << 11)
-#define  CAUSEB_IP4		12
-#define  CAUSEF_IP4		(_ULCAST_(1)   << 12)
-#define  CAUSEB_IP5		13
-#define  CAUSEF_IP5		(_ULCAST_(1)   << 13)
-#define  CAUSEB_IP6		14
-#define  CAUSEF_IP6		(_ULCAST_(1)   << 14)
-#define  CAUSEB_IP7		15
-#define  CAUSEF_IP7		(_ULCAST_(1)   << 15)
-#define  CAUSEB_IV		23
-#define  CAUSEF_IV		(_ULCAST_(1)   << 23)
-#define  CAUSEB_CE		28
-#define  CAUSEF_CE		(_ULCAST_(3)   << 28)
-#define  CAUSEB_BD		31
-#define  CAUSEF_BD		(_ULCAST_(1)   << 31)
+#define  CAUSEB_EXCCODE     2
+#define  CAUSEF_EXCCODE     (_ULCAST_(31)  <<  2)
+#define  CAUSEB_IP      8
+#define  CAUSEF_IP      (_ULCAST_(255) <<  8)
+#define  CAUSEB_IP0     8
+#define  CAUSEF_IP0     (_ULCAST_(1)   <<  8)
+#define  CAUSEB_IP1     9
+#define  CAUSEF_IP1     (_ULCAST_(1)   <<  9)
+#define  CAUSEB_IP2     10
+#define  CAUSEF_IP2     (_ULCAST_(1)   << 10)
+#define  CAUSEB_IP3     11
+#define  CAUSEF_IP3     (_ULCAST_(1)   << 11)
+#define  CAUSEB_IP4     12
+#define  CAUSEF_IP4     (_ULCAST_(1)   << 12)
+#define  CAUSEB_IP5     13
+#define  CAUSEF_IP5     (_ULCAST_(1)   << 13)
+#define  CAUSEB_IP6     14
+#define  CAUSEF_IP6     (_ULCAST_(1)   << 14)
+#define  CAUSEB_IP7     15
+#define  CAUSEF_IP7     (_ULCAST_(1)   << 15)
+#define  CAUSEB_IV      23
+#define  CAUSEF_IV      (_ULCAST_(1)   << 23)
+#define  CAUSEB_CE      28
+#define  CAUSEF_CE      (_ULCAST_(3)   << 28)
+#define  CAUSEB_BD      31
+#define  CAUSEF_BD      (_ULCAST_(1)   << 31)
 
 /*
  * Bits in the coprocessor 0 config register.
  */
 /* Generic bits.  */
-#define CONF_CM_CACHABLE_NO_WA		0
-#define CONF_CM_CACHABLE_WA		1
-#define CONF_CM_UNCACHED		2
-#define CONF_CM_CACHABLE_NONCOHERENT	3
-#define CONF_CM_CACHABLE_CE		4
-#define CONF_CM_CACHABLE_COW		5
-#define CONF_CM_CACHABLE_CUW		6
-#define CONF_CM_CACHABLE_ACCELERATED	7
-#define CONF_CM_CMASK			7
-#define CONF_BE			(_ULCAST_(1) << 15)
+#define CONF_CM_CACHABLE_NO_WA      0
+#define CONF_CM_CACHABLE_WA     1
+#define CONF_CM_UNCACHED        2
+#define CONF_CM_CACHABLE_NONCOHERENT    3
+#define CONF_CM_CACHABLE_CE     4
+#define CONF_CM_CACHABLE_COW        5
+#define CONF_CM_CACHABLE_CUW        6
+#define CONF_CM_CACHABLE_ACCELERATED    7
+#define CONF_CM_CMASK           7
+#define CONF_BE         (_ULCAST_(1) << 15)
 
 /* Bits common to various processors.  */
-#define CONF_CU			(_ULCAST_(1) <<  3)
-#define CONF_DB			(_ULCAST_(1) <<  4)
-#define CONF_IB			(_ULCAST_(1) <<  5)
-#define CONF_DC			(_ULCAST_(7) <<  6)
-#define CONF_IC			(_ULCAST_(7) <<  9)
-#define CONF_EB			(_ULCAST_(1) << 13)
-#define CONF_EM			(_ULCAST_(1) << 14)
-#define CONF_SM			(_ULCAST_(1) << 16)
-#define CONF_SC			(_ULCAST_(1) << 17)
-#define CONF_EW			(_ULCAST_(3) << 18)
-#define CONF_EP			(_ULCAST_(15)<< 24)
-#define CONF_EC			(_ULCAST_(7) << 28)
-#define CONF_CM			(_ULCAST_(1) << 31)
+#define CONF_CU         (_ULCAST_(1) <<  3)
+#define CONF_DB         (_ULCAST_(1) <<  4)
+#define CONF_IB         (_ULCAST_(1) <<  5)
+#define CONF_DC         (_ULCAST_(7) <<  6)
+#define CONF_IC         (_ULCAST_(7) <<  9)
+#define CONF_EB         (_ULCAST_(1) << 13)
+#define CONF_EM         (_ULCAST_(1) << 14)
+#define CONF_SM         (_ULCAST_(1) << 16)
+#define CONF_SC         (_ULCAST_(1) << 17)
+#define CONF_EW         (_ULCAST_(3) << 18)
+#define CONF_EP         (_ULCAST_(15)<< 24)
+#define CONF_EC         (_ULCAST_(7) << 28)
+#define CONF_CM         (_ULCAST_(1) << 31)
 
 /* Bits specific to the R4xx0.  */
-#define R4K_CONF_SW		(_ULCAST_(1) << 20)
-#define R4K_CONF_SS		(_ULCAST_(1) << 21)
-#define R4K_CONF_SB		(_ULCAST_(3) << 22)
+#define R4K_CONF_SW     (_ULCAST_(1) << 20)
+#define R4K_CONF_SS     (_ULCAST_(1) << 21)
+#define R4K_CONF_SB     (_ULCAST_(3) << 22)
 
 /* Bits specific to the R5000.  */
-#define R5K_CONF_SE		(_ULCAST_(1) << 12)
-#define R5K_CONF_SS		(_ULCAST_(3) << 20)
+#define R5K_CONF_SE     (_ULCAST_(1) << 12)
+#define R5K_CONF_SS     (_ULCAST_(3) << 20)
 
 /* Bits specific to the R10000.  */
-#define R10K_CONF_DN		(_ULCAST_(3) <<  3)
-#define R10K_CONF_CT		(_ULCAST_(1) <<  5)
-#define R10K_CONF_PE		(_ULCAST_(1) <<  6)
-#define R10K_CONF_PM		(_ULCAST_(3) <<  7)
-#define R10K_CONF_EC		(_ULCAST_(15)<<  9)
-#define R10K_CONF_SB		(_ULCAST_(1) << 13)
-#define R10K_CONF_SK		(_ULCAST_(1) << 14)
-#define R10K_CONF_SS		(_ULCAST_(7) << 16)
-#define R10K_CONF_SC		(_ULCAST_(7) << 19)
-#define R10K_CONF_DC		(_ULCAST_(7) << 26)
-#define R10K_CONF_IC		(_ULCAST_(7) << 29)
+#define R10K_CONF_DN        (_ULCAST_(3) <<  3)
+#define R10K_CONF_CT        (_ULCAST_(1) <<  5)
+#define R10K_CONF_PE        (_ULCAST_(1) <<  6)
+#define R10K_CONF_PM        (_ULCAST_(3) <<  7)
+#define R10K_CONF_EC        (_ULCAST_(15)<<  9)
+#define R10K_CONF_SB        (_ULCAST_(1) << 13)
+#define R10K_CONF_SK        (_ULCAST_(1) << 14)
+#define R10K_CONF_SS        (_ULCAST_(7) << 16)
+#define R10K_CONF_SC        (_ULCAST_(7) << 19)
+#define R10K_CONF_DC        (_ULCAST_(7) << 26)
+#define R10K_CONF_IC        (_ULCAST_(7) << 29)
 
 /* Bits specific to the VR41xx.  */
-#define VR41_CONF_CS		(_ULCAST_(1) << 12)
-#define VR41_CONF_M16		(_ULCAST_(1) << 20)
-#define VR41_CONF_AD		(_ULCAST_(1) << 23)
+#define VR41_CONF_CS        (_ULCAST_(1) << 12)
+#define VR41_CONF_M16       (_ULCAST_(1) << 20)
+#define VR41_CONF_AD        (_ULCAST_(1) << 23)
 
 /* Bits specific to the R30xx.  */
-#define R30XX_CONF_FDM		(_ULCAST_(1) << 19)
-#define R30XX_CONF_REV		(_ULCAST_(1) << 22)
-#define R30XX_CONF_AC		(_ULCAST_(1) << 23)
-#define R30XX_CONF_RF		(_ULCAST_(1) << 24)
-#define R30XX_CONF_HALT		(_ULCAST_(1) << 25)
-#define R30XX_CONF_FPINT	(_ULCAST_(7) << 26)
-#define R30XX_CONF_DBR		(_ULCAST_(1) << 29)
-#define R30XX_CONF_SB		(_ULCAST_(1) << 30)
-#define R30XX_CONF_LOCK		(_ULCAST_(1) << 31)
+#define R30XX_CONF_FDM      (_ULCAST_(1) << 19)
+#define R30XX_CONF_REV      (_ULCAST_(1) << 22)
+#define R30XX_CONF_AC       (_ULCAST_(1) << 23)
+#define R30XX_CONF_RF       (_ULCAST_(1) << 24)
+#define R30XX_CONF_HALT     (_ULCAST_(1) << 25)
+#define R30XX_CONF_FPINT    (_ULCAST_(7) << 26)
+#define R30XX_CONF_DBR      (_ULCAST_(1) << 29)
+#define R30XX_CONF_SB       (_ULCAST_(1) << 30)
+#define R30XX_CONF_LOCK     (_ULCAST_(1) << 31)
 
 /* Bits specific to the TX49.  */
-#define TX49_CONF_DC		(_ULCAST_(1) << 16)
-#define TX49_CONF_IC		(_ULCAST_(1) << 17)  /* conflict with CONF_SC */
-#define TX49_CONF_HALT		(_ULCAST_(1) << 18)
-#define TX49_CONF_CWFON		(_ULCAST_(1) << 27)
+#define TX49_CONF_DC        (_ULCAST_(1) << 16)
+#define TX49_CONF_IC        (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
+#define TX49_CONF_HALT      (_ULCAST_(1) << 18)
+#define TX49_CONF_CWFON     (_ULCAST_(1) << 27)
 
 /* Bits specific to the MIPS32/64 PRA.  */
-#define MIPS_CONF_MT		(_ULCAST_(7) <<  7)
-#define MIPS_CONF_AR		(_ULCAST_(7) << 10)
-#define MIPS_CONF_AT		(_ULCAST_(3) << 13)
-#define MIPS_CONF_M		(_ULCAST_(1) << 31)
+#define MIPS_CONF_MT        (_ULCAST_(7) <<  7)
+#define MIPS_CONF_AR        (_ULCAST_(7) << 10)
+#define MIPS_CONF_AT        (_ULCAST_(3) << 13)
+#define MIPS_CONF_M     (_ULCAST_(1) << 31)
 
 /*
  * R10000 performance counter definitions.
@@ -604,50 +604,50 @@
 /*
  * Events counted by counter #0
  */
-#define CE0_CYCLES			0
-#define CE0_INSN_ISSUED			1
-#define CE0_LPSC_ISSUED			2
-#define CE0_S_ISSUED			3
-#define CE0_SC_ISSUED			4
-#define CE0_SC_FAILED			5
-#define CE0_BRANCH_DECODED		6
-#define CE0_QW_WB_SECONDARY		7
-#define CE0_CORRECTED_ECC_ERRORS	8
-#define CE0_ICACHE_MISSES		9
-#define CE0_SCACHE_I_MISSES		10
-#define CE0_SCACHE_I_WAY_MISSPREDICTED	11
-#define CE0_EXT_INTERVENTIONS_REQ	12
-#define CE0_EXT_INVALIDATE_REQ		13
-#define CE0_VIRTUAL_COHERENCY_COND	14
-#define CE0_INSN_GRADUATED		15
+#define CE0_CYCLES          0
+#define CE0_INSN_ISSUED         1
+#define CE0_LPSC_ISSUED         2
+#define CE0_S_ISSUED            3
+#define CE0_SC_ISSUED           4
+#define CE0_SC_FAILED           5
+#define CE0_BRANCH_DECODED      6
+#define CE0_QW_WB_SECONDARY     7
+#define CE0_CORRECTED_ECC_ERRORS    8
+#define CE0_ICACHE_MISSES       9
+#define CE0_SCACHE_I_MISSES     10
+#define CE0_SCACHE_I_WAY_MISSPREDICTED  11
+#define CE0_EXT_INTERVENTIONS_REQ   12
+#define CE0_EXT_INVALIDATE_REQ      13
+#define CE0_VIRTUAL_COHERENCY_COND  14
+#define CE0_INSN_GRADUATED      15
 
 /*
  * Events counted by counter #1
  */
-#define CE1_CYCLES			0
-#define CE1_INSN_GRADUATED		1
-#define CE1_LPSC_GRADUATED		2
-#define CE1_S_GRADUATED			3
-#define CE1_SC_GRADUATED		4
-#define CE1_FP_INSN_GRADUATED		5
-#define CE1_QW_WB_PRIMARY		6
-#define CE1_TLB_REFILL			7
-#define CE1_BRANCH_MISSPREDICTED	8
-#define CE1_DCACHE_MISS			9
-#define CE1_SCACHE_D_MISSES		10
-#define CE1_SCACHE_D_WAY_MISSPREDICTED	11
-#define CE1_EXT_INTERVENTION_HITS	12
-#define CE1_EXT_INVALIDATE_REQ		13
-#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS	14
-#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS	15
+#define CE1_CYCLES          0
+#define CE1_INSN_GRADUATED      1
+#define CE1_LPSC_GRADUATED      2
+#define CE1_S_GRADUATED         3
+#define CE1_SC_GRADUATED        4
+#define CE1_FP_INSN_GRADUATED       5
+#define CE1_QW_WB_PRIMARY       6
+#define CE1_TLB_REFILL          7
+#define CE1_BRANCH_MISSPREDICTED    8
+#define CE1_DCACHE_MISS         9
+#define CE1_SCACHE_D_MISSES     10
+#define CE1_SCACHE_D_WAY_MISSPREDICTED  11
+#define CE1_EXT_INTERVENTION_HITS   12
+#define CE1_EXT_INVALIDATE_REQ      13
+#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS  14
+#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
 
 /*
  * These flags define in which priviledge mode the counters count events
  */
-#define CEB_USER	8	/* Count events in user mode, EXL = ERL = 0 */
-#define CEB_SUPERVISOR	4	/* Count events in supvervisor mode EXL = ERL = 0 */
-#define CEB_KERNEL	2	/* Count events in kernel mode EXL = ERL = 0 */
-#define CEB_EXL		1	/* Count events with EXL = 1, ERL = 0 */
+#define CEB_USER    8   /* Count events in user mode, EXL = ERL = 0 */
+#define CEB_SUPERVISOR  4   /* Count events in supvervisor mode EXL = ERL = 0 */
+#define CEB_KERNEL  2   /* Count events in kernel mode EXL = ERL = 0 */
+#define CEB_EXL     1   /* Count events with EXL = 1, ERL = 0 */
 
 #ifndef __ASSEMBLY__
 
@@ -685,275 +685,275 @@
  * Macros to access the system control coprocessor
  */
 
-#define __read_32bit_c0_register(source, sel)				\
-({ int __res;								\
-    if (sel == 0)							\
-        __asm__ __volatile__(					\
-            "mfc0\t%0, " #source "\n\t"			\
-            : "=r" (__res));				\
-    else								\
-        __asm__ __volatile__(					\
-            ".set\tmips32\n\t"				\
-            "mfc0\t%0, " #source ", " #sel "\n\t"		\
-            ".set\tmips0\n\t"				\
-            : "=r" (__res));				\
-    __res;								\
+#define __read_32bit_c0_register(source, sel)               \
+({ int __res;                               \
+    if (sel == 0)                           \
+        __asm__ __volatile__(                   \
+            "mfc0\t%0, " #source "\n\t"         \
+            : "=r" (__res));                \
+    else                                \
+        __asm__ __volatile__(                   \
+            ".set\tmips32\n\t"              \
+            "mfc0\t%0, " #source ", " #sel "\n\t"       \
+            ".set\tmips0\n\t"               \
+            : "=r" (__res));                \
+    __res;                              \
 })
 
-#define __read_64bit_c0_register(source, sel)				\
-({ unsigned long __res;							\
-    if (sel == 0)							\
-        __asm__ __volatile__(					\
-            ".set\tmips3\n\t"				\
-            "dmfc0\t%0, " #source "\n\t"			\
-            ".set\tmips0"					\
-            : "=r" (__res));				\
-    else								\
-        __asm__ __volatile__(					\
-            ".set\tmips64\n\t"				\
-            "dmfc0\t%0, " #source ", " #sel "\n\t"		\
-            ".set\tmips0"					\
-            : "=r" (__res));				\
-    __res;								\
+#define __read_64bit_c0_register(source, sel)               \
+({ unsigned long __res;                         \
+    if (sel == 0)                           \
+        __asm__ __volatile__(                   \
+            ".set\tmips3\n\t"               \
+            "dmfc0\t%0, " #source "\n\t"            \
+            ".set\tmips0"                   \
+            : "=r" (__res));                \
+    else                                \
+        __asm__ __volatile__(                   \
+            ".set\tmips64\n\t"              \
+            "dmfc0\t%0, " #source ", " #sel "\n\t"      \
+            ".set\tmips0"                   \
+            : "=r" (__res));                \
+    __res;                              \
 })
 
-#define __write_32bit_c0_register(register, sel, value)			\
-do {									\
-    if (sel == 0)							\
-        __asm__ __volatile__(					\
-            "mtc0\t%z0, " #register "\n\t"			\
-            : : "Jr" (value));				\
-    else								\
-        __asm__ __volatile__(					\
-            ".set\tmips32\n\t"				\
-            "mtc0\t%z0, " #register ", " #sel "\n\t"	\
-            ".set\tmips0"					\
-            : : "Jr" (value));				\
+#define __write_32bit_c0_register(register, sel, value)         \
+do {                                    \
+    if (sel == 0)                           \
+        __asm__ __volatile__(                   \
+            "mtc0\t%z0, " #register "\n\t"          \
+            : : "Jr" (value));              \
+    else                                \
+        __asm__ __volatile__(                   \
+            ".set\tmips32\n\t"              \
+            "mtc0\t%z0, " #register ", " #sel "\n\t"    \
+            ".set\tmips0"                   \
+            : : "Jr" (value));              \
 } while (0)
 
-#define __write_64bit_c0_register(register, sel, value)			\
-do {									\
-    if (sel == 0)							\
-        __asm__ __volatile__(					\
-            ".set\tmips3\n\t"				\
-            "dmtc0\t%z0, " #register "\n\t"			\
-            ".set\tmips0"					\
-            : : "Jr" (value));				\
-    else								\
-        __asm__ __volatile__(					\
-            ".set\tmips64\n\t"				\
-            "dmtc0\t%z0, " #register ", " #sel "\n\t"	\
-            ".set\tmips0"					\
-            : : "Jr" (value));				\
+#define __write_64bit_c0_register(register, sel, value)         \
+do {                                    \
+    if (sel == 0)                           \
+        __asm__ __volatile__(                   \
+            ".set\tmips3\n\t"               \
+            "dmtc0\t%z0, " #register "\n\t"         \
+            ".set\tmips0"                   \
+            : : "Jr" (value));              \
+    else                                \
+        __asm__ __volatile__(                   \
+            ".set\tmips64\n\t"              \
+            "dmtc0\t%z0, " #register ", " #sel "\n\t"   \
+            ".set\tmips0"                   \
+            : : "Jr" (value));              \
 } while (0)
 
-#define __read_ulong_c0_register(reg, sel)				\
-    ((sizeof(unsigned long) == 4) ?					\
-    __read_32bit_c0_register(reg, sel) :				\
+#define __read_ulong_c0_register(reg, sel)              \
+    ((sizeof(unsigned long) == 4) ?                 \
+    __read_32bit_c0_register(reg, sel) :                \
     __read_64bit_c0_register(reg, sel))
 
-#define __write_ulong_c0_register(reg, sel, val)			\
-do {									\
-    if (sizeof(unsigned long) == 4)					\
-        __write_32bit_c0_register(reg, sel, val);		\
-    else								\
-        __write_64bit_c0_register(reg, sel, val);		\
+#define __write_ulong_c0_register(reg, sel, val)            \
+do {                                    \
+    if (sizeof(unsigned long) == 4)                 \
+        __write_32bit_c0_register(reg, sel, val);       \
+    else                                \
+        __write_64bit_c0_register(reg, sel, val);       \
 } while (0)
 
 /*
  * These versions are only needed for systems with more than 38 bits of
  * physical address space running the 32-bit kernel.  That's none atm :-)
  */
-#define __read_64bit_c0_split(source, sel)				\
-({									\
-    unsigned long long val;						\
-    unsigned long flags;						\
+#define __read_64bit_c0_split(source, sel)              \
+({                                  \
+    unsigned long long val;                     \
+    unsigned long flags;                        \
                                     \
-    local_irq_save(flags);						\
-    if (sel == 0)							\
-        __asm__ __volatile__(					\
-            ".set\tmips64\n\t"				\
-            "dmfc0\t%M0, " #source "\n\t"			\
-            "dsll\t%L0, %M0, 32\n\t"			\
-            "dsrl\t%M0, %M0, 32\n\t"			\
-            "dsrl\t%L0, %L0, 32\n\t"			\
-            ".set\tmips0"					\
-            : "=r" (val));					\
-    else								\
-        __asm__ __volatile__(					\
-            ".set\tmips64\n\t"				\
-            "dmfc0\t%M0, " #source ", " #sel "\n\t"		\
-            "dsll\t%L0, %M0, 32\n\t"			\
-            "dsrl\t%M0, %M0, 32\n\t"			\
-            "dsrl\t%L0, %L0, 32\n\t"			\
-            ".set\tmips0"					\
-            : "=r" (val));					\
-    local_irq_restore(flags);					\
+    local_irq_save(flags);                      \
+    if (sel == 0)                           \
+        __asm__ __volatile__(                   \
+            ".set\tmips64\n\t"              \
+            "dmfc0\t%M0, " #source "\n\t"           \
+            "dsll\t%L0, %M0, 32\n\t"            \
+            "dsrl\t%M0, %M0, 32\n\t"            \
+            "dsrl\t%L0, %L0, 32\n\t"            \
+            ".set\tmips0"                   \
+            : "=r" (val));                  \
+    else                                \
+        __asm__ __volatile__(                   \
+            ".set\tmips64\n\t"              \
+            "dmfc0\t%M0, " #source ", " #sel "\n\t"     \
+            "dsll\t%L0, %M0, 32\n\t"            \
+            "dsrl\t%M0, %M0, 32\n\t"            \
+            "dsrl\t%L0, %L0, 32\n\t"            \
+            ".set\tmips0"                   \
+            : "=r" (val));                  \
+    local_irq_restore(flags);                   \
                                     \
-    val;								\
+    val;                                \
 })
 
-#define __write_64bit_c0_split(source, sel, val)			\
-do {									\
-    unsigned long flags;						\
+#define __write_64bit_c0_split(source, sel, val)            \
+do {                                    \
+    unsigned long flags;                        \
                                     \
-    local_irq_save(flags);						\
-    if (sel == 0)							\
-        __asm__ __volatile__(					\
-            ".set\tmips64\n\t"				\
-            "dsll\t%L0, %L0, 32\n\t"			\
-            "dsrl\t%L0, %L0, 32\n\t"			\
-            "dsll\t%M0, %M0, 32\n\t"			\
-            "or\t%L0, %L0, %M0\n\t"				\
-            "dmtc0\t%L0, " #source "\n\t"			\
-            ".set\tmips0"					\
-            : : "r" (val));					\
-    else								\
-        __asm__ __volatile__(					\
-            ".set\tmips64\n\t"				\
-            "dsll\t%L0, %L0, 32\n\t"			\
-            "dsrl\t%L0, %L0, 32\n\t"			\
-            "dsll\t%M0, %M0, 32\n\t"			\
-            "or\t%L0, %L0, %M0\n\t"				\
-            "dmtc0\t%L0, " #source ", " #sel "\n\t"		\
-            ".set\tmips0"					\
-            : : "r" (val));					\
-    local_irq_restore(flags);					\
+    local_irq_save(flags);                      \
+    if (sel == 0)                           \
+        __asm__ __volatile__(                   \
+            ".set\tmips64\n\t"              \
+            "dsll\t%L0, %L0, 32\n\t"            \
+            "dsrl\t%L0, %L0, 32\n\t"            \
+            "dsll\t%M0, %M0, 32\n\t"            \
+            "or\t%L0, %L0, %M0\n\t"             \
+            "dmtc0\t%L0, " #source "\n\t"           \
+            ".set\tmips0"                   \
+            : : "r" (val));                 \
+    else                                \
+        __asm__ __volatile__(                   \
+            ".set\tmips64\n\t"              \
+            "dsll\t%L0, %L0, 32\n\t"            \
+            "dsrl\t%L0, %L0, 32\n\t"            \
+            "dsll\t%M0, %M0, 32\n\t"            \
+            "or\t%L0, %L0, %M0\n\t"             \
+            "dmtc0\t%L0, " #source ", " #sel "\n\t"     \
+            ".set\tmips0"                   \
+            : : "r" (val));                 \
+    local_irq_restore(flags);                   \
 } while (0)
 
-#define read_c0_index()		__read_32bit_c0_register($0, 0)
-#define write_c0_index(val)	__write_32bit_c0_register($0, 0, val)
+#define read_c0_index()     __read_32bit_c0_register($0, 0)
+#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
 
-#define read_c0_entrylo0()	__read_ulong_c0_register($2, 0)
-#define write_c0_entrylo0(val)	__write_ulong_c0_register($2, 0, val)
+#define read_c0_entrylo0()  __read_ulong_c0_register($2, 0)
+#define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
 
-#define read_c0_entrylo1()	__read_ulong_c0_register($3, 0)
-#define write_c0_entrylo1(val)	__write_ulong_c0_register($3, 0, val)
+#define read_c0_entrylo1()  __read_ulong_c0_register($3, 0)
+#define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
 
-#define read_c0_conf()		__read_32bit_c0_register($3, 0)
-#define write_c0_conf(val)	__write_32bit_c0_register($3, 0, val)
+#define read_c0_conf()      __read_32bit_c0_register($3, 0)
+#define write_c0_conf(val)  __write_32bit_c0_register($3, 0, val)
 
-#define read_c0_context()	__read_ulong_c0_register($4, 0)
-#define write_c0_context(val)	__write_ulong_c0_register($4, 0, val)
+#define read_c0_context()   __read_ulong_c0_register($4, 0)
+#define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
 
-#define read_c0_pagemask()	__read_32bit_c0_register($5, 0)
-#define write_c0_pagemask(val)	__write_32bit_c0_register($5, 0, val)
+#define read_c0_pagemask()  __read_32bit_c0_register($5, 0)
+#define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
 
-#define read_c0_wired()		__read_32bit_c0_register($6, 0)
-#define write_c0_wired(val)	__write_32bit_c0_register($6, 0, val)
+#define read_c0_wired()     __read_32bit_c0_register($6, 0)
+#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
 
-#define read_c0_info()		__read_32bit_c0_register($7, 0)
+#define read_c0_info()      __read_32bit_c0_register($7, 0)
 
-#define read_c0_cache()		__read_32bit_c0_register($7, 0)	/* TX39xx */
-#define write_c0_cache(val)	__write_32bit_c0_register($7, 0, val)
+#define read_c0_cache()     __read_32bit_c0_register($7, 0) /* TX39xx */
+#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
 
-#define read_c0_count()		__read_32bit_c0_register($9, 0)
-#define write_c0_count(val)	__write_32bit_c0_register($9, 0, val)
+#define read_c0_count()     __read_32bit_c0_register($9, 0)
+#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
 
-#define read_c0_entryhi()	__read_ulong_c0_register($10, 0)
-#define write_c0_entryhi(val)	__write_ulong_c0_register($10, 0, val)
+#define read_c0_entryhi()   __read_ulong_c0_register($10, 0)
+#define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
 
-#define read_c0_compare()	__read_32bit_c0_register($11, 0)
-#define write_c0_compare(val)	__write_32bit_c0_register($11, 0, val)
+#define read_c0_compare()   __read_32bit_c0_register($11, 0)
+#define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
 
-#define read_c0_status()	__read_32bit_c0_register($12, 0)
-#define write_c0_status(val)	__write_32bit_c0_register($12, 0, val)
+#define read_c0_status()    __read_32bit_c0_register($12, 0)
+#define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
 
-#define read_c0_cause()		__read_32bit_c0_register($13, 0)
-#define write_c0_cause(val)	__write_32bit_c0_register($13, 0, val)
+#define read_c0_cause()     __read_32bit_c0_register($13, 0)
+#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
 
-#define read_c0_prid()		__read_32bit_c0_register($15, 0)
+#define read_c0_prid()      __read_32bit_c0_register($15, 0)
 
-#define read_c0_ebase()		__read_32bit_c0_register($15, 1)
-#define write_c0_ebase(val)	__write_32bit_c0_register($15, 1, val)
+#define read_c0_ebase()     __read_32bit_c0_register($15, 1)
+#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
 
-#define read_c0_config()	__read_32bit_c0_register($16, 0)
-#define read_c0_config1()	__read_32bit_c0_register($16, 1)
-#define read_c0_config2()	__read_32bit_c0_register($16, 2)
-#define read_c0_config3()	__read_32bit_c0_register($16, 3)
-#define write_c0_config(val)	__write_32bit_c0_register($16, 0, val)
-#define write_c0_config1(val)	__write_32bit_c0_register($16, 1, val)
-#define write_c0_config2(val)	__write_32bit_c0_register($16, 2, val)
-#define write_c0_config3(val)	__write_32bit_c0_register($16, 3, val)
+#define read_c0_config()    __read_32bit_c0_register($16, 0)
+#define read_c0_config1()   __read_32bit_c0_register($16, 1)
+#define read_c0_config2()   __read_32bit_c0_register($16, 2)
+#define read_c0_config3()   __read_32bit_c0_register($16, 3)
+#define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
+#define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
+#define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
+#define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
 
 /*
  * The WatchLo register.  There may be upto 8 of them.
  */
-#define read_c0_watchlo0()	__read_ulong_c0_register($18, 0)
-#define read_c0_watchlo1()	__read_ulong_c0_register($18, 1)
-#define read_c0_watchlo2()	__read_ulong_c0_register($18, 2)
-#define read_c0_watchlo3()	__read_ulong_c0_register($18, 3)
-#define read_c0_watchlo4()	__read_ulong_c0_register($18, 4)
-#define read_c0_watchlo5()	__read_ulong_c0_register($18, 5)
-#define read_c0_watchlo6()	__read_ulong_c0_register($18, 6)
-#define read_c0_watchlo7()	__read_ulong_c0_register($18, 7)
-#define write_c0_watchlo0(val)	__write_ulong_c0_register($18, 0, val)
-#define write_c0_watchlo1(val)	__write_ulong_c0_register($18, 1, val)
-#define write_c0_watchlo2(val)	__write_ulong_c0_register($18, 2, val)
-#define write_c0_watchlo3(val)	__write_ulong_c0_register($18, 3, val)
-#define write_c0_watchlo4(val)	__write_ulong_c0_register($18, 4, val)
-#define write_c0_watchlo5(val)	__write_ulong_c0_register($18, 5, val)
-#define write_c0_watchlo6(val)	__write_ulong_c0_register($18, 6, val)
-#define write_c0_watchlo7(val)	__write_ulong_c0_register($18, 7, val)
+#define read_c0_watchlo0()  __read_ulong_c0_register($18, 0)
+#define read_c0_watchlo1()  __read_ulong_c0_register($18, 1)
+#define read_c0_watchlo2()  __read_ulong_c0_register($18, 2)
+#define read_c0_watchlo3()  __read_ulong_c0_register($18, 3)
+#define read_c0_watchlo4()  __read_ulong_c0_register($18, 4)
+#define read_c0_watchlo5()  __read_ulong_c0_register($18, 5)
+#define read_c0_watchlo6()  __read_ulong_c0_register($18, 6)
+#define read_c0_watchlo7()  __read_ulong_c0_register($18, 7)
+#define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
+#define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
+#define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
+#define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
+#define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
+#define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
+#define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
+#define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
 
 /*
  * The WatchHi register.  There may be upto 8 of them.
  */
-#define read_c0_watchhi0()	__read_32bit_c0_register($19, 0)
-#define read_c0_watchhi1()	__read_32bit_c0_register($19, 1)
-#define read_c0_watchhi2()	__read_32bit_c0_register($19, 2)
-#define read_c0_watchhi3()	__read_32bit_c0_register($19, 3)
-#define read_c0_watchhi4()	__read_32bit_c0_register($19, 4)
-#define read_c0_watchhi5()	__read_32bit_c0_register($19, 5)
-#define read_c0_watchhi6()	__read_32bit_c0_register($19, 6)
-#define read_c0_watchhi7()	__read_32bit_c0_register($19, 7)
+#define read_c0_watchhi0()  __read_32bit_c0_register($19, 0)
+#define read_c0_watchhi1()  __read_32bit_c0_register($19, 1)
+#define read_c0_watchhi2()  __read_32bit_c0_register($19, 2)
+#define read_c0_watchhi3()  __read_32bit_c0_register($19, 3)
+#define read_c0_watchhi4()  __read_32bit_c0_register($19, 4)
+#define read_c0_watchhi5()  __read_32bit_c0_register($19, 5)
+#define read_c0_watchhi6()  __read_32bit_c0_register($19, 6)
+#define read_c0_watchhi7()  __read_32bit_c0_register($19, 7)
 
-#define write_c0_watchhi0(val)	__write_32bit_c0_register($19, 0, val)
-#define write_c0_watchhi1(val)	__write_32bit_c0_register($19, 1, val)
-#define write_c0_watchhi2(val)	__write_32bit_c0_register($19, 2, val)
-#define write_c0_watchhi3(val)	__write_32bit_c0_register($19, 3, val)
-#define write_c0_watchhi4(val)	__write_32bit_c0_register($19, 4, val)
-#define write_c0_watchhi5(val)	__write_32bit_c0_register($19, 5, val)
-#define write_c0_watchhi6(val)	__write_32bit_c0_register($19, 6, val)
-#define write_c0_watchhi7(val)	__write_32bit_c0_register($19, 7, val)
+#define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
+#define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
+#define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
+#define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
+#define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
+#define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
+#define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
+#define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
 
-#define read_c0_xcontext()	__read_ulong_c0_register($20, 0)
-#define write_c0_xcontext(val)	__write_ulong_c0_register($20, 0, val)
+#define read_c0_xcontext()  __read_ulong_c0_register($20, 0)
+#define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
 
-#define read_c0_intcontrol()	__read_32bit_c0_register($20, 1)
+#define read_c0_intcontrol()    __read_32bit_c0_register($20, 1)
 #define write_c0_intcontrol(val) __write_32bit_c0_register($20, 1, val)
 
-#define read_c0_framemask()	__read_32bit_c0_register($21, 0)
-#define write_c0_framemask(val)	__write_32bit_c0_register($21, 0, val)
+#define read_c0_framemask() __read_32bit_c0_register($21, 0)
+#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
 
-#define read_c0_debug()		__read_32bit_c0_register($23, 0)
-#define write_c0_debug(val)	__write_32bit_c0_register($23, 0, val)
+#define read_c0_debug()     __read_32bit_c0_register($23, 0)
+#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
 
-#define read_c0_depc()		__read_ulong_c0_register($24, 0)
-#define write_c0_depc(val)	__write_ulong_c0_register($24, 0, val)
+#define read_c0_depc()      __read_ulong_c0_register($24, 0)
+#define write_c0_depc(val)  __write_ulong_c0_register($24, 0, val)
 
-#define read_c0_ecc()		__read_32bit_c0_register($26, 0)
-#define write_c0_ecc(val)	__write_32bit_c0_register($26, 0, val)
+#define read_c0_ecc()       __read_32bit_c0_register($26, 0)
+#define write_c0_ecc(val)   __write_32bit_c0_register($26, 0, val)
 
-#define read_c0_derraddr0()	__read_ulong_c0_register($26, 1)
-#define write_c0_derraddr0(val)	__write_ulong_c0_register($26, 1, val)
+#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
+#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
 
-#define read_c0_cacheerr()	__read_32bit_c0_register($27, 0)
+#define read_c0_cacheerr()  __read_32bit_c0_register($27, 0)
 
-#define read_c0_derraddr1()	__read_ulong_c0_register($27, 1)
-#define write_c0_derraddr1(val)	__write_ulong_c0_register($27, 1, val)
+#define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
+#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
 
-#define read_c0_taglo()		__read_32bit_c0_register($28, 0)
-#define write_c0_taglo(val)	__write_32bit_c0_register($28, 0, val)
+#define read_c0_taglo()     __read_32bit_c0_register($28, 0)
+#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
 
-#define read_c0_taghi()		__read_32bit_c0_register($29, 0)
-#define write_c0_taghi(val)	__write_32bit_c0_register($29, 0, val)
+#define read_c0_taghi()     __read_32bit_c0_register($29, 0)
+#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
 
-#define read_c0_errorepc()	__read_ulong_c0_register($30, 0)
-#define write_c0_errorepc(val)	__write_ulong_c0_register($30, 0, val)
+#define read_c0_errorepc()  __read_ulong_c0_register($30, 0)
+#define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
 
-#define read_c0_epc()		__read_ulong_c0_register($14, 0)
-#define write_c0_epc(val)	__write_ulong_c0_register($14, 0, val)
+#define read_c0_epc()       __read_ulong_c0_register($14, 0)
+#define write_c0_epc(val)   __write_ulong_c0_register($14, 0, val)
 
 #if 1
 /*
@@ -962,20 +962,20 @@ do {									\
 #define read_32bit_cp0_register(source)                         \
 ({ int __res;                                                   \
         __asm__ __volatile__(                                   \
-    ".set\tpush\n\t"					\
-    ".set\treorder\n\t"					\
+    ".set\tpush\n\t"                    \
+    ".set\treorder\n\t"                 \
         "mfc0\t%0,"STR(source)"\n\t"                            \
-    ".set\tpop"						\
+    ".set\tpop"                     \
         : "=r" (__res));                                        \
         __res;})
 
 #define read_32bit_cp0_set1_register(source)                    \
 ({ int __res;                                                   \
         __asm__ __volatile__(                                   \
-    ".set\tpush\n\t"					\
-    ".set\treorder\n\t"					\
+    ".set\tpush\n\t"                    \
+    ".set\treorder\n\t"                 \
         "cfc0\t%0,"STR(source)"\n\t"                            \
-    ".set\tpop"						\
+    ".set\tpop"                     \
         : "=r" (__res));                                        \
         __res;})
 
@@ -993,14 +993,14 @@ do {									\
 
 #define write_32bit_cp0_register(register,value)                \
         __asm__ __volatile__(                                   \
-        "mtc0\t%0,"STR(register)"\n\t"				\
-    "nop"							\
+        "mtc0\t%0,"STR(register)"\n\t"              \
+    "nop"                           \
         : : "r" (value));
 
 #define write_32bit_cp0_set1_register(register,value)           \
         __asm__ __volatile__(                                   \
-        "ctc0\t%0,$"STR(register)"\n\t"				\
-    "nop"							\
+        "ctc0\t%0,$"STR(register)"\n\t"             \
+    "nop"                           \
         : : "r" (value));
 
 #define write_64bit_cp0_register(register,value)                \
@@ -1018,9 +1018,9 @@ do {									\
         __asm__ __volatile__(                                   \
     ".set\tnoreorder\n\t"                                   \
     ".set\tnoat\n\t"                                        \
-    "#.set\tmips64\n\t"					\
-    "#mfc0\t$1, $16, 1\n\t"					\
-    "#.set\tmips0\n\t"					\
+    "#.set\tmips64\n\t"                 \
+    "#mfc0\t$1, $16, 1\n\t"                 \
+    "#.set\tmips0\n\t"                  \
          ".word\t0x40018001\n\t"                                 \
     "move\t%0,$1\n\t"                                       \
     ".set\tat\n\t"                                          \
@@ -1035,17 +1035,17 @@ do {									\
 #define read_32bit_cp1_register(source)                         \
 ({ int __res;                                                   \
     __asm__ __volatile__(                                   \
-    ".set\tpush\n\t"					\
-    ".set\treorder\n\t"					\
+    ".set\tpush\n\t"                    \
+    ".set\treorder\n\t"                 \
         "cfc1\t%0,$"STR(source)"\n\t"                            \
-    ".set\tpop"						\
+    ".set\tpop"                     \
         : "=r" (__res));                                        \
         __res;})
 
 #define write_32bit_cp1_register(register,value)                \
         __asm__ __volatile__(                                   \
-        "ctc1\t%0,$"STR(register)"\n\t"				\
-    "nop"							\
+        "ctc1\t%0,$"STR(register)"\n\t"             \
+    "nop"                           \
         : : "r" (value));
 
 /* TLB operations. */
@@ -1084,62 +1084,62 @@ static inline void tlb_write_random(void)
 /*
  * Manipulate bits in a c0 register.
  */
-#define __BUILD_SET_C0(name,register)				\
-static inline unsigned int					\
-set_c0_##name(unsigned int set)					\
-{								\
-    unsigned int res;					\
+#define __BUILD_SET_C0(name,register)               \
+static inline unsigned int                  \
+set_c0_##name(unsigned int set)                 \
+{                               \
+    unsigned int res;                   \
                                 \
-    res = read_c0_##name();					\
-    res |= set;						\
-    write_c0_##name(res);					\
+    res = read_c0_##name();                 \
+    res |= set;                     \
+    write_c0_##name(res);                   \
                                 \
-    return res;						\
-}								\
+    return res;                     \
+}                               \
                                 \
-static inline unsigned int					\
-clear_c0_##name(unsigned int clear)				\
-{								\
-    unsigned int res;					\
+static inline unsigned int                  \
+clear_c0_##name(unsigned int clear)             \
+{                               \
+    unsigned int res;                   \
                                 \
-    res = read_c0_##name();					\
-    res &= ~clear;						\
-    write_c0_##name(res);					\
+    res = read_c0_##name();                 \
+    res &= ~clear;                      \
+    write_c0_##name(res);                   \
                                 \
-    return res;						\
-}								\
+    return res;                     \
+}                               \
                                 \
-static inline unsigned int					\
-change_c0_##name(unsigned int change, unsigned int new)		\
-{								\
-    unsigned int res;					\
+static inline unsigned int                  \
+change_c0_##name(unsigned int change, unsigned int new)     \
+{                               \
+    unsigned int res;                   \
                                 \
-    res = read_c0_##name();					\
-    res &= ~change;						\
-    res |= (new & change);					\
-    write_c0_##name(res);					\
+    res = read_c0_##name();                 \
+    res &= ~change;                     \
+    res |= (new & change);                  \
+    write_c0_##name(res);                   \
                                 \
-    return res;						\
+    return res;                     \
 }
 
 __BUILD_SET_C0(status,CP0_STATUS)
 __BUILD_SET_C0(cause,CP0_CAUSE)
 __BUILD_SET_C0(config,CP0_CONFIG)
 
-#define set_cp0_status(x)	set_c0_status(x)
-#define set_cp0_cause(x)	set_c0_cause(x)
-#define set_cp0_config(x)	set_c0_config(x)
+#define set_cp0_status(x)   set_c0_status(x)
+#define set_cp0_cause(x)    set_c0_cause(x)
+#define set_cp0_config(x)   set_c0_config(x)
 
-#define read_c1_status()	read_32bit_cp1_register(31)
-#define write_c1_status(x)	write_32bit_cp1_register(31, x)
+#define read_c1_status()    read_32bit_cp1_register(31)
+#define write_c1_status(x)  write_32bit_cp1_register(31, x)
 
-#define readb(reg)		(*((volatile unsigned char *) (reg)))
-#define readw(reg)		(*((volatile unsigned short *) (reg)))
-#define readl(reg)		(*((volatile unsigned int *) (reg)))
+#define readb(reg)      (*((volatile unsigned char *) (reg)))
+#define readw(reg)      (*((volatile unsigned short *) (reg)))
+#define readl(reg)      (*((volatile unsigned int *) (reg)))
 
-#define writeb(data, reg)	((*((volatile unsigned char *)(reg))) = (unsigned char)(data))
-#define writew(data, reg)	((*((volatile unsigned short *)(reg))) = (unsigned short)(data))
-#define writel(data, reg)	((*((volatile unsigned int *)(reg))) = (unsigned int)(data))
+#define writeb(data, reg)   ((*((volatile unsigned char *)(reg))) = (unsigned char)(data))
+#define writew(data, reg)   ((*((volatile unsigned short *)(reg))) = (unsigned short)(data))
+#define writel(data, reg)   ((*((volatile unsigned int *)(reg))) = (unsigned int)(data))
 
 #endif /* !__ASSEMBLY__ */
 
diff --git a/libcpu/mips/common/mips_types.h b/libcpu/mips/common/mips_types.h
index cc12d44391..466a39a40b 100644
--- a/libcpu/mips/common/mips_types.h
+++ b/libcpu/mips/common/mips_types.h
@@ -1,21 +1,7 @@
 /*
- * File      : mips_types.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/libcpu/mips/common/ptrace.h b/libcpu/mips/common/ptrace.h
index 00ce58a085..8b82cca5d6 100644
--- a/libcpu/mips/common/ptrace.h
+++ b/libcpu/mips/common/ptrace.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -23,9 +23,9 @@
 #include 
 
 struct mips_fpu_struct {
-    rt_uint64_t	fpr[NUM_FPU_REGS];
-    rt_uint32_t	fcr31;
-    rt_uint32_t	pad;
+    rt_uint64_t fpr[NUM_FPU_REGS];
+    rt_uint32_t fcr31;
+    rt_uint32_t pad;
 };
 
 struct pt_regs {
@@ -68,53 +68,53 @@ struct pt_regs {
 
 /* Note: For call stack o32 ABI has 0x8 shadowsoace Here  */
 #ifdef ARCH_MIPS64
-#define PT_R0		(0x0 * LONGSIZE)	/* 0 */
+#define PT_R0       (0x0 * LONGSIZE)    /* 0 */
 #else
-#define PT_R0		(0x8 * LONGSIZE)	/* 0 */
+#define PT_R0       (0x8 * LONGSIZE)    /* 0 */
 #endif
-#define PT_R1		((PT_R0) + LONGSIZE)	/* 1 */
-#define PT_R2		((PT_R1) + LONGSIZE)	/* 2 */
-#define PT_R3		((PT_R2) + LONGSIZE)	/* 3 */
-#define PT_R4		((PT_R3) + LONGSIZE)	/* 4 */
-#define PT_R5		((PT_R4) + LONGSIZE)	/* 5 */
-#define PT_R6		((PT_R5) + LONGSIZE)	/* 6 */
-#define PT_R7		((PT_R6) + LONGSIZE)	/* 7 */
-#define PT_R8		((PT_R7) + LONGSIZE)	/* 8 */
-#define PT_R9		((PT_R8) + LONGSIZE)	/* 9 */
-#define PT_R10		((PT_R9) + LONGSIZE)	/* 10 */
-#define PT_R11		((PT_R10) + LONGSIZE)	/* 11 */
-#define PT_R12		((PT_R11) + LONGSIZE)	/* 12 */
-#define PT_R13		((PT_R12) + LONGSIZE)	/* 13 */
-#define PT_R14		((PT_R13) + LONGSIZE)	/* 14 */
-#define PT_R15		((PT_R14) + LONGSIZE)	/* 15 */
-#define PT_R16		((PT_R15) + LONGSIZE)	/* 16 */
-#define PT_R17		((PT_R16) + LONGSIZE)	/* 17 */
-#define PT_R18		((PT_R17) + LONGSIZE)	/* 18 */
-#define PT_R19		((PT_R18) + LONGSIZE)	/* 19 */
-#define PT_R20		((PT_R19) + LONGSIZE)	/* 20 */
-#define PT_R21		((PT_R20) + LONGSIZE)	/* 21 */
-#define PT_R22		((PT_R21) + LONGSIZE)	/* 22 */
-#define PT_R23		((PT_R22) + LONGSIZE)	/* 23 */
-#define PT_R24		((PT_R23) + LONGSIZE)	/* 24 */
-#define PT_R25		((PT_R24) + LONGSIZE)	/* 25 */
-#define PT_R26		((PT_R25) + LONGSIZE)	/* 26 */
-#define PT_R27		((PT_R26) + LONGSIZE)	/* 27 */
-#define PT_R28		((PT_R27) + LONGSIZE)	/* 28 */
-#define PT_R29		((PT_R28) + LONGSIZE)	/* 29 */
-#define PT_R30		((PT_R29) + LONGSIZE)	/* 30 */
-#define PT_R31		((PT_R30) + LONGSIZE)	/* 31 */
+#define PT_R1       ((PT_R0) + LONGSIZE)    /* 1 */
+#define PT_R2       ((PT_R1) + LONGSIZE)    /* 2 */
+#define PT_R3       ((PT_R2) + LONGSIZE)    /* 3 */
+#define PT_R4       ((PT_R3) + LONGSIZE)    /* 4 */
+#define PT_R5       ((PT_R4) + LONGSIZE)    /* 5 */
+#define PT_R6       ((PT_R5) + LONGSIZE)    /* 6 */
+#define PT_R7       ((PT_R6) + LONGSIZE)    /* 7 */
+#define PT_R8       ((PT_R7) + LONGSIZE)    /* 8 */
+#define PT_R9       ((PT_R8) + LONGSIZE)    /* 9 */
+#define PT_R10      ((PT_R9) + LONGSIZE)    /* 10 */
+#define PT_R11      ((PT_R10) + LONGSIZE)   /* 11 */
+#define PT_R12      ((PT_R11) + LONGSIZE)   /* 12 */
+#define PT_R13      ((PT_R12) + LONGSIZE)   /* 13 */
+#define PT_R14      ((PT_R13) + LONGSIZE)   /* 14 */
+#define PT_R15      ((PT_R14) + LONGSIZE)   /* 15 */
+#define PT_R16      ((PT_R15) + LONGSIZE)   /* 16 */
+#define PT_R17      ((PT_R16) + LONGSIZE)   /* 17 */
+#define PT_R18      ((PT_R17) + LONGSIZE)   /* 18 */
+#define PT_R19      ((PT_R18) + LONGSIZE)   /* 19 */
+#define PT_R20      ((PT_R19) + LONGSIZE)   /* 20 */
+#define PT_R21      ((PT_R20) + LONGSIZE)   /* 21 */
+#define PT_R22      ((PT_R21) + LONGSIZE)   /* 22 */
+#define PT_R23      ((PT_R22) + LONGSIZE)   /* 23 */
+#define PT_R24      ((PT_R23) + LONGSIZE)   /* 24 */
+#define PT_R25      ((PT_R24) + LONGSIZE)   /* 25 */
+#define PT_R26      ((PT_R25) + LONGSIZE)   /* 26 */
+#define PT_R27      ((PT_R26) + LONGSIZE)   /* 27 */
+#define PT_R28      ((PT_R27) + LONGSIZE)   /* 28 */
+#define PT_R29      ((PT_R28) + LONGSIZE)   /* 29 */
+#define PT_R30      ((PT_R29) + LONGSIZE)   /* 30 */
+#define PT_R31      ((PT_R30) + LONGSIZE)   /* 31 */
 
 /*
  * Saved special registers
  */
-#define PT_STATUS	((PT_R31) + LONGSIZE)	/* 32 */
-#define PT_HI		((PT_STATUS) + HI_LO_SIZE)	/* 33 */
-#define PT_LO		((PT_HI) + HI_LO_SIZE)	/* 34 */
-#define PT_BADVADDR	((PT_LO) + LONGSIZE)	/* 35 */
-#define PT_CAUSE	((PT_BADVADDR) + LONGSIZE)	/* 36 */
-#define PT_EPC		((PT_CAUSE) + LONGSIZE)	/* 37 */
+#define PT_STATUS   ((PT_R31) + LONGSIZE)   /* 32 */
+#define PT_HI       ((PT_STATUS) + HI_LO_SIZE)  /* 33 */
+#define PT_LO       ((PT_HI) + HI_LO_SIZE)  /* 34 */
+#define PT_BADVADDR ((PT_LO) + LONGSIZE)    /* 35 */
+#define PT_CAUSE    ((PT_BADVADDR) + LONGSIZE)  /* 36 */
+#define PT_EPC      ((PT_CAUSE) + LONGSIZE) /* 37 */
 
-#define PT_REG_END		((PT_EPC) + LONGSIZE) /* Align already ensured manually */
+#define PT_REG_END      ((PT_EPC) + LONGSIZE) /* Align already ensured manually */
 
 #ifdef RT_USING_FPU
 #define PT_FPU_R0               (PT_REG_END)
@@ -136,10 +136,10 @@ struct pt_regs {
 #define PT_FPU_FCSR31           ((PT_FPU_R30) + FP_REG_SIZE)
 #define PT_FPU_PAD0             ((PT_FPU_FCSR31) + 4)
 
-#define PT_FPU_END     	        ((PT_FPU_PAD0) + 4)
-#define PT_SIZE			PT_FPU_END
+#define PT_FPU_END              ((PT_FPU_PAD0) + 4)
+#define PT_SIZE         PT_FPU_END
 #else
-#define PT_SIZE			PT_REG_END
+#define PT_SIZE         PT_REG_END
 #endif
 
-#endif
\ No newline at end of file
+#endif
diff --git a/libcpu/mips/common/stack.c b/libcpu/mips/common/stack.c
index b933b184e7..3f9010837a 100644
--- a/libcpu/mips/common/stack.c
+++ b/libcpu/mips/common/stack.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -47,15 +47,15 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_ad
     pt->regs[REG_FP] = (rt_ubase_t)0x0;
     pt->regs[REG_RA] = (rt_ubase_t)texit;
 
-    pt->hi	= 0x0;
-    pt->lo	= 0x0;
+    pt->hi  = 0x0;
+    pt->lo  = 0x0;
     pt->cp0_status = (ST0_IE | ST0_CU0 | ST0_IM);
 #ifdef RT_USING_FPU
     pt->cp0_status |= (ST0_CU1 | ST0_FR);
 #endif
-    pt->cp0_cause	= read_c0_cause();
-    pt->cp0_epc	= (rt_ubase_t)tentry;
-    pt->cp0_badvaddr	= 0x0;
+    pt->cp0_cause   = read_c0_cause();
+    pt->cp0_epc = (rt_ubase_t)tentry;
+    pt->cp0_badvaddr    = 0x0;
 
     return stk;
 }
diff --git a/libcpu/mips/common/stackframe.h b/libcpu/mips/common/stackframe.h
index bb92a18c9c..ba361acd99 100644
--- a/libcpu/mips/common/stackframe.h
+++ b/libcpu/mips/common/stackframe.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -51,69 +51,69 @@
     .set pop
     .endm
 
-    .macro	SAVE_AT
-    .set	push
-    .set	noat
-    LONG_S	$1, PT_R1(sp)
-    .set	pop
+    .macro  SAVE_AT
+    .set    push
+    .set    noat
+    LONG_S  $1, PT_R1(sp)
+    .set    pop
     .endm
 
-    .macro	SAVE_TEMP
-    mfhi	v1
-    LONG_S	$8, PT_R8(sp)
-    LONG_S	$9, PT_R9(sp)
-    sw	v1, PT_HI(sp)
-    mflo	v1
-    LONG_S	$10, PT_R10(sp)
-    LONG_S	$11, PT_R11(sp)
-    sw	v1,  PT_LO(sp)
-    LONG_S	$12, PT_R12(sp)
-    LONG_S	$13, PT_R13(sp)
-    LONG_S	$14, PT_R14(sp)
-    LONG_S	$15, PT_R15(sp)
-    LONG_S	$24, PT_R24(sp)
+    .macro  SAVE_TEMP
+    mfhi    v1
+    LONG_S  $8, PT_R8(sp)
+    LONG_S  $9, PT_R9(sp)
+    sw  v1, PT_HI(sp)
+    mflo    v1
+    LONG_S  $10, PT_R10(sp)
+    LONG_S  $11, PT_R11(sp)
+    sw  v1,  PT_LO(sp)
+    LONG_S  $12, PT_R12(sp)
+    LONG_S  $13, PT_R13(sp)
+    LONG_S  $14, PT_R14(sp)
+    LONG_S  $15, PT_R15(sp)
+    LONG_S  $24, PT_R24(sp)
     .endm
 
-    .macro	SAVE_STATIC
-    LONG_S	$16, PT_R16(sp)
-    LONG_S	$17, PT_R17(sp)
-    LONG_S	$18, PT_R18(sp)
-    LONG_S	$19, PT_R19(sp)
-    LONG_S	$20, PT_R20(sp)
-    LONG_S	$21, PT_R21(sp)
-    LONG_S	$22, PT_R22(sp)
-    LONG_S	$23, PT_R23(sp)
-    LONG_S	$30, PT_R30(sp)
+    .macro  SAVE_STATIC
+    LONG_S  $16, PT_R16(sp)
+    LONG_S  $17, PT_R17(sp)
+    LONG_S  $18, PT_R18(sp)
+    LONG_S  $19, PT_R19(sp)
+    LONG_S  $20, PT_R20(sp)
+    LONG_S  $21, PT_R21(sp)
+    LONG_S  $22, PT_R22(sp)
+    LONG_S  $23, PT_R23(sp)
+    LONG_S  $30, PT_R30(sp)
     .endm
 
-    .macro	SAVE_SOME
-    .set	push
-    .set	noat
-    .set	reorder
-    move	k1, sp
-    move	k0, sp
+    .macro  SAVE_SOME
+    .set    push
+    .set    noat
+    .set    reorder
+    move    k1, sp
+    move    k0, sp
     PTR_SUBU sp, k1, PT_SIZE
-    LONG_S	k0, PT_R29(sp)
-    LONG_S	$3, PT_R3(sp)
-    LONG_S	$0, PT_R0(sp)
-    MFC0	v1, CP0_STATUS
-    LONG_S	$2, PT_R2(sp)
-    LONG_S	v1, PT_STATUS(sp)
-    LONG_S	$4, PT_R4(sp)
-    MFC0	v1, CP0_CAUSE
-    LONG_S	$5, PT_R5(sp)
-    LONG_S	v1, PT_CAUSE(sp)
-    LONG_S	$6, PT_R6(sp)
-    MFC0	v1, CP0_EPC
-    LONG_S	$7, PT_R7(sp)
-    LONG_S	v1, PT_EPC(sp)
-    LONG_S	$25, PT_R25(sp)
-    LONG_S	$28, PT_R28(sp)
-    LONG_S	$31, PT_R31(sp)
-    .set	pop
+    LONG_S  k0, PT_R29(sp)
+    LONG_S  $3, PT_R3(sp)
+    LONG_S  $0, PT_R0(sp)
+    MFC0    v1, CP0_STATUS
+    LONG_S  $2, PT_R2(sp)
+    LONG_S  v1, PT_STATUS(sp)
+    LONG_S  $4, PT_R4(sp)
+    MFC0    v1, CP0_CAUSE
+    LONG_S  $5, PT_R5(sp)
+    LONG_S  v1, PT_CAUSE(sp)
+    LONG_S  $6, PT_R6(sp)
+    MFC0    v1, CP0_EPC
+    LONG_S  $7, PT_R7(sp)
+    LONG_S  v1, PT_EPC(sp)
+    LONG_S  $25, PT_R25(sp)
+    LONG_S  $28, PT_R28(sp)
+    LONG_S  $31, PT_R31(sp)
+    .set    pop
     .endm
 
-    .macro	SAVE_ALL
+    .macro  SAVE_ALL
     SAVE_SOME
     SAVE_AT
     SAVE_TEMP
@@ -155,86 +155,86 @@
     .set pop
     .endm
 
-    .macro	RESTORE_AT
-    .set	push
-    .set	noat
-    LONG_L	$1,  PT_R1(sp)
-    .set	pop
+    .macro  RESTORE_AT
+    .set    push
+    .set    noat
+    LONG_L  $1,  PT_R1(sp)
+    .set    pop
     .endm
 
-    .macro	RESTORE_TEMP
-    lw	$24, PT_LO(sp)
-    LONG_L	$8, PT_R8(sp)
-    LONG_L	$9, PT_R9(sp)
-    mtlo	$24
-    lw	$24, PT_HI(sp)
-    LONG_L	$10, PT_R10(sp)
-    LONG_L	$11, PT_R11(sp)
-    mthi	$24
-    LONG_L	$12, PT_R12(sp)
-    LONG_L	$13, PT_R13(sp)
-    LONG_L	$14, PT_R14(sp)
-    LONG_L	$15, PT_R15(sp)
-    LONG_L	$24, PT_R24(sp)
+    .macro  RESTORE_TEMP
+    lw  $24, PT_LO(sp)
+    LONG_L  $8, PT_R8(sp)
+    LONG_L  $9, PT_R9(sp)
+    mtlo    $24
+    lw  $24, PT_HI(sp)
+    LONG_L  $10, PT_R10(sp)
+    LONG_L  $11, PT_R11(sp)
+    mthi    $24
+    LONG_L  $12, PT_R12(sp)
+    LONG_L  $13, PT_R13(sp)
+    LONG_L  $14, PT_R14(sp)
+    LONG_L  $15, PT_R15(sp)
+    LONG_L  $24, PT_R24(sp)
     .endm
 
-    .macro	RESTORE_STATIC
-    LONG_L	$16, PT_R16(sp)
-    LONG_L	$17, PT_R17(sp)
-    LONG_L	$18, PT_R18(sp)
-    LONG_L	$19, PT_R19(sp)
-    LONG_L	$20, PT_R20(sp)
-    LONG_L	$21, PT_R21(sp)
-    LONG_L	$22, PT_R22(sp)
-    LONG_L	$23, PT_R23(sp)
-    LONG_L	$30, PT_R30(sp)
+    .macro  RESTORE_STATIC
+    LONG_L  $16, PT_R16(sp)
+    LONG_L  $17, PT_R17(sp)
+    LONG_L  $18, PT_R18(sp)
+    LONG_L  $19, PT_R19(sp)
+    LONG_L  $20, PT_R20(sp)
+    LONG_L  $21, PT_R21(sp)
+    LONG_L  $22, PT_R22(sp)
+    LONG_L  $23, PT_R23(sp)
+    LONG_L  $30, PT_R30(sp)
     .endm
 
 #define STATMASK 0x1f
 
-    .macro	RESTORE_SOME
-    .set	push
-    .set	reorder
-    .set	noat
-    mfc0	a0, CP0_STATUS
-    ori	a0, STATMASK
-    xori	a0, STATMASK
-    mtc0	a0, CP0_STATUS
-    li	v1, (ST0_CU1 | ST0_FR | ST0_IM)
-    and	a0, v1, a0
-    LONG_L	v0, PT_STATUS(sp)
-    li	v1, ~(ST0_CU1 | ST0_FR | ST0_IM)
-    and	v0, v1
-    or	v0, a0
+    .macro  RESTORE_SOME
+    .set    push
+    .set    reorder
+    .set    noat
+    mfc0    a0, CP0_STATUS
+    ori a0, STATMASK
+    xori    a0, STATMASK
+    mtc0    a0, CP0_STATUS
+    li  v1, (ST0_CU1 | ST0_FR | ST0_IM)
+    and a0, v1, a0
+    LONG_L  v0, PT_STATUS(sp)
+    li  v1, ~(ST0_CU1 | ST0_FR | ST0_IM)
+    and v0, v1
+    or  v0, a0
     li  v1, (ST0_KX | ST0_SX | ST0_UX)
     or  v0, v1
-    mtc0	v0, CP0_STATUS
-    LONG_L	v1, PT_EPC(sp)
-    MTC0	v1, CP0_EPC
-    LONG_L	$31, PT_R31(sp)
-    LONG_L	$28, PT_R28(sp)
-    LONG_L	$25, PT_R25(sp)
-    LONG_L	$7,  PT_R7(sp)
-    LONG_L	$6,  PT_R6(sp)
-    LONG_L	$5,  PT_R5(sp)
-    LONG_L	$4,  PT_R4(sp)
-    LONG_L	$3,  PT_R3(sp)
-    LONG_L	$2,  PT_R2(sp)
-    .set	pop
+    mtc0    v0, CP0_STATUS
+    LONG_L  v1, PT_EPC(sp)
+    MTC0    v1, CP0_EPC
+    LONG_L  $31, PT_R31(sp)
+    LONG_L  $28, PT_R28(sp)
+    LONG_L  $25, PT_R25(sp)
+    LONG_L  $7,  PT_R7(sp)
+    LONG_L  $6,  PT_R6(sp)
+    LONG_L  $5,  PT_R5(sp)
+    LONG_L  $4,  PT_R4(sp)
+    LONG_L  $3,  PT_R3(sp)
+    LONG_L  $2,  PT_R2(sp)
+    .set    pop
     .endm
 
-    .macro	RESTORE_SP_AND_RET
-    LONG_L	sp, PT_R29(sp)
+    .macro  RESTORE_SP_AND_RET
+    LONG_L  sp, PT_R29(sp)
     eret
     nop
     .endm
 
 
-    .macro	RESTORE_SP
-    LONG_L	sp, PT_R29(sp)
+    .macro  RESTORE_SP
+    LONG_L  sp, PT_R29(sp)
     .endm
 
-    .macro	RESTORE_ALL
+    .macro  RESTORE_ALL
     RESTORE_TEMP
     RESTORE_FPU
     RESTORE_STATIC
@@ -243,7 +243,7 @@
     RESTORE_SP
     .endm
 
-    .macro	RESTORE_ALL_AND_RET
+    .macro  RESTORE_ALL_AND_RET
     RESTORE_TEMP
     RESTORE_FPU
     RESTORE_STATIC
diff --git a/libcpu/mips/gs232/cache.c b/libcpu/mips/gs232/cache.c
index 484d3816f4..bcbf2aba49 100644
--- a/libcpu/mips/gs232/cache.c
+++ b/libcpu/mips/gs232/cache.c
@@ -1,7 +1,7 @@
 /*
  * Cache Ops For Loongson GS232
  *
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,8 +15,8 @@
 #include 
 #include 
 
-#define K0BASE			0x80000000
-#define PRID_LS1C		0x4220
+#define K0BASE          0x80000000
+#define PRID_LS1C       0x4220
 
 extern void Clear_TagLo (void);
 extern void Invalidate_Icache_Ls1c(unsigned int);
@@ -27,10 +27,10 @@ extern void enable_cpu_cache(void);
 
 typedef struct cacheinfo_t
 {
-    unsigned int	icache_size;
-    unsigned int	dcache_size;
-    unsigned int	icacheline_size;
-    unsigned int	dcacheline_size;
+    unsigned int    icache_size;
+    unsigned int    dcache_size;
+    unsigned int    icacheline_size;
+    unsigned int    dcacheline_size;
 } cacheinfo_t ;
 
 typedef struct cacheop_t
@@ -183,12 +183,12 @@ void rt_hw_cache_init(void)
     end = (start + pcacheinfo->icache_size);
 
     /*
-     *	2. clear CP0 taglo/taghi register;
+     *  2. clear CP0 taglo/taghi register;
      */
     pcacheop->Clear_TagLo();
 
     /*
-     *	3. invalidate instruction cache;
+     *  3. invalidate instruction cache;
      */
     while (start < end)
     {
@@ -197,7 +197,7 @@ void rt_hw_cache_init(void)
     }
 
     /*
-     *	4. invalidate data cache;
+     *  4. invalidate data cache;
      */
     start = K0BASE;
     end = (start + pcacheinfo->dcache_size);
diff --git a/libcpu/mips/gs232/cache.h b/libcpu/mips/gs232/cache.h
index 381298e4df..b47db90814 100644
--- a/libcpu/mips/gs232/cache.h
+++ b/libcpu/mips/gs232/cache.h
@@ -1,8 +1,8 @@
 /*
  * Cache Ops For Loongson GS232
- * 
- * Copyright (c) 2006-2019, RT-Thread Development Team
- * 
+ *
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
@@ -12,8 +12,8 @@
  * 2015-07-08     chinesebear   modified for loongson 1c
  */
 
-#ifndef	__CACHE_H__
-#define	__CACHE_H__
+#ifndef __CACHE_H__
+#define __CACHE_H__
 /*
  * Cache Operations
  */
@@ -21,31 +21,31 @@
 #define Index_Writeback_Inv_D   0x01
 #define Index_Invalidate_SI     0x02
 #define Index_Writeback_Inv_SD  0x03
-#define Index_Load_Tag_I		0x04
-#define Index_Load_Tag_D		0x05
-#define Index_Load_Tag_SI		0x06
-#define Index_Load_Tag_SD		0x07
-#define Index_Store_Tag_I		0x08
-#define Index_Store_Tag_D		0x09
-#define Index_Store_Tag_SI		0x0A
-#define Index_Store_Tag_SD		0x0B
-#define Create_Dirty_Excl_D		0x0d
-#define Create_Dirty_Excl_SD	0x0f
-#define Hit_Invalidate_I		0x10
-#define Hit_Invalidate_D		0x11
-#define Hit_Invalidate_SI		0x12
-#define Hit_Invalidate_SD		0x13
-#define Fill					0x14
-#define Hit_Writeback_Inv_D		0x15
+#define Index_Load_Tag_I        0x04
+#define Index_Load_Tag_D        0x05
+#define Index_Load_Tag_SI       0x06
+#define Index_Load_Tag_SD       0x07
+#define Index_Store_Tag_I       0x08
+#define Index_Store_Tag_D       0x09
+#define Index_Store_Tag_SI      0x0A
+#define Index_Store_Tag_SD      0x0B
+#define Create_Dirty_Excl_D     0x0d
+#define Create_Dirty_Excl_SD    0x0f
+#define Hit_Invalidate_I        0x10
+#define Hit_Invalidate_D        0x11
+#define Hit_Invalidate_SI       0x12
+#define Hit_Invalidate_SD       0x13
+#define Fill                    0x14
+#define Hit_Writeback_Inv_D     0x15
 /* 0x16 is unused */
-#define Hit_Writeback_Inv_SD	0x17
-#define Hit_Writeback_I			0x18
-#define Hit_Writeback_D			0x19
+#define Hit_Writeback_Inv_SD    0x17
+#define Hit_Writeback_I         0x18
+#define Hit_Writeback_D         0x19
 /* 0x1a is unused */
-#define Hit_Writeback_SD		0x1b
+#define Hit_Writeback_SD        0x1b
 /* 0x1c is unused */
 /* 0x1e is unused */
-#define Hit_Set_Virtual_SI		0x1e
-#define Hit_Set_Virtual_SD		0x1f
+#define Hit_Set_Virtual_SI      0x1e
+#define Hit_Set_Virtual_SD      0x1f
 
 #endif
diff --git a/libcpu/mips/gs232/cpuport.c b/libcpu/mips/gs232/cpuport.c
index e3c078241f..e22d9bc14d 100644
--- a/libcpu/mips/gs232/cpuport.c
+++ b/libcpu/mips/gs232/cpuport.c
@@ -1,8 +1,8 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
- * 
+ *
  * Change Logs:
  * Date                Author         Notes
  * 2010-07-09     Bernard        first version
@@ -26,9 +26,9 @@
 RT_WEAK void rt_hw_cpu_reset(void)
 {
     /* open the watch-dog */
-    WDT_EN = 0x01; 		/* watch dog enable */
-    WDT_TIMER = 0x01;	/* watch dog will be timeout after 1 tick */
-    WDT_SET = 0x01;		/* watch dog start */
+    WDT_EN = 0x01;      /* watch dog enable */
+    WDT_TIMER = 0x01;   /* watch dog will be timeout after 1 tick */
+    WDT_SET = 0x01;     /* watch dog start */
 
     rt_kprintf("reboot system...\n");
     while (1);
diff --git a/libcpu/mips/gs232/gs232.h b/libcpu/mips/gs232/gs232.h
index 95c81cf93e..cbc660c874 100644
--- a/libcpu/mips/gs232/gs232.h
+++ b/libcpu/mips/gs232/gs232.h
@@ -1,8 +1,8 @@
 /*
  * Misc define for GS232
- * 
- * Copyright (c) 2006-2019, RT-Thread Development Team
- * 
+ *
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
@@ -15,47 +15,47 @@
 
 #include 
 
-#define INTC_BASE			0xBFD01040
+#define INTC_BASE           0xBFD01040
 
 #ifdef SOC_LS1B
-#define GS232_INTC_CELLS		4
+#define GS232_INTC_CELLS        4
 #endif
 
 #ifdef SOC_LS1C300
-#define GS232_INTC_CELLS		5
+#define GS232_INTC_CELLS        5
 #endif
 
-#define GS232_NR_IRQS			(32 * GS232_INTC_CELLS)
+#define GS232_NR_IRQS           (32 * GS232_INTC_CELLS)
 
-#define GMAC0_BASE			0xBFE10000
-#define GMAC0_DMA_BASE		0xBFE11000
-#define GMAC1_BASE			0xBFE20000
-#define GMAC1_DMA_BASE		0xBFE21000
-#define I2C0_BASE			0xBFE58000
-#define PWM0_BASE			0xBFE5C000
-#define PWM1_BASE			0xBFE5C010
-#define PWM2_BASE			0xBFE5C020
-#define PWM3_BASE			0xBFE5C030
-#define WDT_BASE			0xBFE5C060
-#define RTC_BASE			0xBFE64000
-#define I2C1_BASE			0xBFE68000
-#define I2C2_BASE			0xBFE70000
-#define AC97_BASE			0xBFE74000
-#define NAND_BASE			0xBFE78000
-#define SPI_BASE			0xBFE80000
-#define CAN1_BASE			0xBF004300
-#define CAN0_BASE			0xBF004400
+#define GMAC0_BASE          0xBFE10000
+#define GMAC0_DMA_BASE      0xBFE11000
+#define GMAC1_BASE          0xBFE20000
+#define GMAC1_DMA_BASE      0xBFE21000
+#define I2C0_BASE           0xBFE58000
+#define PWM0_BASE           0xBFE5C000
+#define PWM1_BASE           0xBFE5C010
+#define PWM2_BASE           0xBFE5C020
+#define PWM3_BASE           0xBFE5C030
+#define WDT_BASE            0xBFE5C060
+#define RTC_BASE            0xBFE64000
+#define I2C1_BASE           0xBFE68000
+#define I2C2_BASE           0xBFE70000
+#define AC97_BASE           0xBFE74000
+#define NAND_BASE           0xBFE78000
+#define SPI_BASE            0xBFE80000
+#define CAN1_BASE           0xBF004300
+#define CAN0_BASE           0xBF004400
 
 #ifndef __ASSEMBLY__
 #include 
 
 /* Watch Dog registers */
-#define WDT_EN				HWREG32(WDT_BASE + 0x00)
-#define WDT_SET				HWREG32(WDT_BASE + 0x04)
-#define WDT_TIMER			HWREG32(WDT_BASE + 0x08)
+#define WDT_EN              HWREG32(WDT_BASE + 0x00)
+#define WDT_SET             HWREG32(WDT_BASE + 0x04)
+#define WDT_TIMER           HWREG32(WDT_BASE + 0x08)
 
-#define PLL_FREQ 			HWREG32(0xbfe78030)
-#define PLL_DIV_PARAM 		HWREG32(0xbfe78034)
+#define PLL_FREQ            HWREG32(0xbfe78030)
+#define PLL_DIV_PARAM       HWREG32(0xbfe78034)
 
 struct gs232_intc_regs
 {
@@ -65,7 +65,7 @@ struct gs232_intc_regs
     volatile unsigned int int_clr;        /* offset 0x10*/
     volatile unsigned int int_pol;
     volatile unsigned int int_edge;        /* offset 0 */
-}; 
+};
 
 extern void rt_hw_timer_init(void);
 
diff --git a/libcpu/mips/gs232/interrupt.c b/libcpu/mips/gs232/interrupt.c
index 66abea379d..fb80a8c1ec 100644
--- a/libcpu/mips/gs232/interrupt.c
+++ b/libcpu/mips/gs232/interrupt.c
@@ -1,17 +1,17 @@
 /*
  * Interrupt handle for GS232
- * 
- * Copyright (c) 2006-2019, RT-Thread Development Team
- * 
+ *
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2010-10-15     Bernard      first version
- * 2010-10-15     lgnq           modified for LS1B
+ * 2010-10-15     lgnq         modified for LS1B
  * 2013-03-29     aozima       Modify the interrupt interface implementations.
- * 2015-07-06     chinesebear modified for loongson 1c
- * 2019-12-04     Jiaxun Yang   Generialize
+ * 2015-07-06     chinesebear  modified for loongson 1c
+ * 2019-12-04     Jiaxun Yang  Generialize
  */
 
 #include 
@@ -52,7 +52,7 @@ void rt_hw_interrupt_init(void)
         /* Disable */
         (gs232_hw0_icregs+i)->int_en = 0x0;
         /* Trigger active low */
-        (gs232_hw0_icregs+i)->int_pol = -1;	   /* Must be done here */
+        (gs232_hw0_icregs+i)->int_pol = -1;    /* Must be done here */
         /* Make all interrupts level triggered */
         (gs232_hw0_icregs+i)->int_edge = 0x00000000;
         /* Mask all interrupts */
@@ -113,7 +113,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
 
 
 /**
- * ִ Call ISR
+ * Call ISR
  * @IRQn ID of IRQ
  */
 void gs232_do_IRQ(int IRQn)
diff --git a/libcpu/mips/gs232/ls1b.h b/libcpu/mips/gs232/ls1b.h
index a6f244ef4f..cf32bd5f02 100644
--- a/libcpu/mips/gs232/ls1b.h
+++ b/libcpu/mips/gs232/ls1b.h
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- * 
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
@@ -13,44 +13,44 @@
 
 #include 
 
-#define LS1B_ACPI_IRQ	0
-#define LS1B_HPET_IRQ	1
-#define LS1B_UART0_IRQ	2
-#define LS1B_UART1_IRQ	3
-#define LS1B_UART2_IRQ	4
-#define LS1B_UART3_IRQ	5
-#define LS1B_UART4_IRQ	29
-#define LS1B_UART5_IRQ	30
-#define LS1B_UART6_IRQ	2	//共享LS1B_UART0_IRQ
-#define LS1B_UART7_IRQ	2
-#define LS1B_UART8_IRQ	2
-#define LS1B_UART9_IRQ	3	//共享LS1B_UART1_IRQ
-#define LS1B_UART10_IRQ	3
-#define LS1B_UART11_IRQ	3
+#define LS1B_ACPI_IRQ   0
+#define LS1B_HPET_IRQ   1
+#define LS1B_UART0_IRQ  2
+#define LS1B_UART1_IRQ  3
+#define LS1B_UART2_IRQ  4
+#define LS1B_UART3_IRQ  5
+#define LS1B_UART4_IRQ  29
+#define LS1B_UART5_IRQ  30
+#define LS1B_UART6_IRQ  2   //共享LS1B_UART0_IRQ
+#define LS1B_UART7_IRQ  2
+#define LS1B_UART8_IRQ  2
+#define LS1B_UART9_IRQ  3   //共享LS1B_UART1_IRQ
+#define LS1B_UART10_IRQ 3
+#define LS1B_UART11_IRQ 3
 
-#define LS1B_CAN0_IRQ	6
-#define LS1B_CAN1_IRQ	7
-#define LS1B_SPI0_IRQ	8
-#define LS1B_SPI1_IRQ	9
-#define LS1B_AC97_IRQ	10
-#define LS1B_MS_IRQ		11
-#define LS1B_KB_IRQ		12
-#define LS1B_DMA0_IRQ	13
-#define LS1B_DMA1_IRQ	14
-#define LS1B_NAND_IRQ	15
-#define LS1B_I2C0_IRQ	16
-#define LS1B_I2C1_IRQ	17
-#define LS1B_PWM0_IRQ	18
-#define LS1B_PWM1_IRQ	19
-#define LS1B_PWM2_IRQ	20
-#define LS1B_PWM3_IRQ	21
-#define LS1B_LPC_IRQ	22
-#define LS1B_EHCI_IRQ	32
-#define LS1B_OHCI_IRQ	33
-#define LS1B_GMAC1_IRQ	34
-#define LS1B_GMAC2_IRQ	35
-#define LS1B_SATA_IRQ	36
-#define LS1B_GPU_IRQ	37
+#define LS1B_CAN0_IRQ   6
+#define LS1B_CAN1_IRQ   7
+#define LS1B_SPI0_IRQ   8
+#define LS1B_SPI1_IRQ   9
+#define LS1B_AC97_IRQ   10
+#define LS1B_MS_IRQ     11
+#define LS1B_KB_IRQ     12
+#define LS1B_DMA0_IRQ   13
+#define LS1B_DMA1_IRQ   14
+#define LS1B_NAND_IRQ   15
+#define LS1B_I2C0_IRQ   16
+#define LS1B_I2C1_IRQ   17
+#define LS1B_PWM0_IRQ   18
+#define LS1B_PWM1_IRQ   19
+#define LS1B_PWM2_IRQ   20
+#define LS1B_PWM3_IRQ   21
+#define LS1B_LPC_IRQ    22
+#define LS1B_EHCI_IRQ   32
+#define LS1B_OHCI_IRQ   33
+#define LS1B_GMAC1_IRQ  34
+#define LS1B_GMAC2_IRQ  35
+#define LS1B_SATA_IRQ   36
+#define LS1B_GPU_IRQ    37
 #define LS1B_PCI_INTA_IRQ 38
 #define LS1B_PCI_INTB_IRQ 39
 #define LS1B_PCI_INTC_IRQ 40
@@ -61,13 +61,13 @@
 #define LS1B_GPIO_IRQ_COUNT 64
 #define LS1B_GPIO_LAST_IRQ  (LS1B_GPIO_FIRST_IRQ + LS1B_GPIO_IRQ_COUNT-1)
 
-#define INT_PCI_INTA	(1<<6)
-#define INT_PCI_INTB	(1<<7)
-#define INT_PCI_INTC	(1<<8)
-#define INT_PCI_INTD	(1<<9)
+#define INT_PCI_INTA    (1<<6)
+#define INT_PCI_INTB    (1<<7)
+#define INT_PCI_INTC    (1<<8)
+#define INT_PCI_INTD    (1<<9)
 
 #define LS1B_LAST_IRQ 159
-#define MIPS_CPU_TIMER_IRQ	167
+#define MIPS_CPU_TIMER_IRQ  167
 #define LS1B_INTREG_BASE 0xbfd01040
 
 #define LS1B_DMA_IRQ_BASE 168
diff --git a/libcpu/mips/gs232/ls1c.h b/libcpu/mips/gs232/ls1c.h
index 54c7e36e99..6b8e3fc512 100644
--- a/libcpu/mips/gs232/ls1c.h
+++ b/libcpu/mips/gs232/ls1c.h
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- * 
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
diff --git a/libcpu/mips/gs232/mipscfg.c b/libcpu/mips/gs232/mipscfg.c
index 85e0e633ea..6b37abb895 100644
--- a/libcpu/mips/gs232/mipscfg.c
+++ b/libcpu/mips/gs232/mipscfg.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -12,13 +12,13 @@
 
 mips32_core_cfg_t g_mips_core =
 {
-    16,		/* icache_line_size */
-    256,	/* icache_lines_per_way */
-    4,		/* icache_ways */
-    16,		/* dcache_line_size */
-    256,	/* dcache_lines_per_way */
-    4,		/* dcache_ways */
-    16,		/* max_tlb_entries */
+    16,     /* icache_line_size */
+    256,    /* icache_lines_per_way */
+    4,      /* icache_ways */
+    16,     /* dcache_line_size */
+    256,    /* dcache_lines_per_way */
+    4,      /* dcache_ways */
+    16,     /* max_tlb_entries */
 };
 
 static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
diff --git a/libcpu/mips/gs232/timer.c b/libcpu/mips/gs232/timer.c
index 8879b82ccf..4df02a1b62 100644
--- a/libcpu/mips/gs232/timer.c
+++ b/libcpu/mips/gs232/timer.c
@@ -1,7 +1,7 @@
 /*
  * Assembly Macros For MIPS
  *
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,14 +20,14 @@
  */
 void rt_hw_timer_handler(void)
 {
-	unsigned int count;
+    unsigned int count;
 
-	count = read_c0_compare();
-	write_c0_compare(count);
-	write_c0_count(0);
+    count = read_c0_compare();
+    write_c0_compare(count);
+    write_c0_count(0);
 
-	/* increase a OS tick */
-	rt_tick_increase();
+    /* increase a OS tick */
+    rt_tick_increase();
 }
 
 /**
@@ -35,7 +35,7 @@ void rt_hw_timer_handler(void)
  */
 void rt_hw_timer_init(void)
 {
-	write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND);
-	write_c0_count(0);
-	mips_unmask_cpu_irq(7);
-}
\ No newline at end of file
+    write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND);
+    write_c0_count(0);
+    mips_unmask_cpu_irq(7);
+}
diff --git a/libcpu/mips/gs264/cache.c b/libcpu/mips/gs264/cache.c
index 54d38d0d3f..50976f2e4f 100644
--- a/libcpu/mips/gs264/cache.c
+++ b/libcpu/mips/gs264/cache.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/mips/gs264/cache.h b/libcpu/mips/gs264/cache.h
index 10a4afd899..1e1bc52737 100644
--- a/libcpu/mips/gs264/cache.h
+++ b/libcpu/mips/gs264/cache.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/mips/gs264/mips_mmu.c b/libcpu/mips/gs264/mips_mmu.c
index 7bed69596a..eae9b007de 100644
--- a/libcpu/mips/gs264/mips_mmu.c
+++ b/libcpu/mips/gs264/mips_mmu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -19,7 +19,7 @@ void mmu_init()
     uint32_t status = read_c0_status();
     status |= 0x07 << 5;//ux = 1,sx = 1,kx = 1
     write_c0_status(status);
-    
+
     mmu_clear_tlb();
     mmu_clear_itlb();
 }
@@ -154,7 +154,7 @@ void mmu_set_map(uint64_t vpn,uint64_t ppn,page_mask_enum_t page_mask,uint32_t a
     uint64_t even_vpn = vpn & (~lb);
     uint32_t index;
     tlb_item_t tlb_item,tlb2_item;
-    
+
     mmu_tlb_item_init(&tlb_item);
     mmu_tlb_item_init(&tlb2_item);
     tlb_item.page_mask.mask = page_mask;
diff --git a/libcpu/mips/gs264/mips_mmu.h b/libcpu/mips/gs264/mips_mmu.h
index fcbcef3621..4c7af117d9 100644
--- a/libcpu/mips/gs264/mips_mmu.h
+++ b/libcpu/mips/gs264/mips_mmu.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -96,4 +96,4 @@ uint64_t mmu_tlb_get_bad_vaddr();
 
 void tlb_dump();
 
-#endif
\ No newline at end of file
+#endif
diff --git a/libcpu/mips/gs264/mipscfg.c b/libcpu/mips/gs264/mipscfg.c
index b2aed120ae..0ce7000581 100644
--- a/libcpu/mips/gs264/mipscfg.c
+++ b/libcpu/mips/gs264/mipscfg.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/mips/gs264/mmu.c b/libcpu/mips/gs264/mmu.c
index b5bedace50..cab73f37bd 100644
--- a/libcpu/mips/gs264/mmu.c
+++ b/libcpu/mips/gs264/mmu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -387,7 +387,7 @@ static void __rt_hw_mmu_unmap(rt_mmu_info *mmu_info, void* v_addr, size_t npages
             return;
         }
 
-        if (*(mmu_l2 + l2_off) & ARCH_MMU_USED_MASK) 
+        if (*(mmu_l2 + l2_off) & ARCH_MMU_USED_MASK)
         {
             *(mmu_l2 + l2_off) = 0;
             /* cache maintain */
@@ -691,7 +691,7 @@ void *rt_hw_kernel_virt_to_phys(void *v_addr, size_t size)
 
 //pa --> va
 void *rt_hw_kernel_phys_to_virt(void *p_addr, size_t size)
-{   
+{
     void *v_addr = 0;
 
     #ifdef RT_USING_USERSPACE
diff --git a/libcpu/mips/gs264/mmu.h b/libcpu/mips/gs264/mmu.h
index 2472bf975f..22a749af64 100644
--- a/libcpu/mips/gs264/mmu.h
+++ b/libcpu/mips/gs264/mmu.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/mips/pic32/cpuport.c b/libcpu/mips/pic32/cpuport.c
index 3f08d57167..089f652bce 100644
--- a/libcpu/mips/pic32/cpuport.c
+++ b/libcpu/mips/pic32/cpuport.c
@@ -45,51 +45,51 @@ rt_uint32_t __attribute__((nomips16)) _get_gp(void)
  */
 rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
 {
-	rt_uint32_t *stk;
+    rt_uint32_t *stk;
 
     /** Start at stack top */
     stk = (rt_uint32_t *)stack_addr;
-	*(stk)   = (rt_uint32_t) tentry;        /* pc: Entry Point */
-	*(--stk) = (rt_uint32_t) 0x00800000;    /* c0_cause: IV=1, */
-	*(--stk) = (rt_uint32_t) 0;		        /* c0_badvaddr */
-	*(--stk) = (rt_uint32_t) 0;             /* lo */
-	*(--stk) = (rt_uint32_t) 0;	            /* hi */
-	*(--stk) = (rt_uint32_t) 1; 			/* C0_SR: IE = En, */
-	*(--stk) = (rt_uint32_t) texit;	        /* 31 ra */
-	*(--stk) = (rt_uint32_t) 0x0000001e;	/* 30 s8 */
-	*(--stk) = (rt_uint32_t) stack_addr;	/* 29 sp */
-	*(--stk) = (rt_uint32_t) _get_gp();     /* 28 gp */
-	*(--stk) = (rt_uint32_t) 0x0000001b;	/* 27 k1 */
-	*(--stk) = (rt_uint32_t) 0x0000001a;	/* 26 k0 */
-	*(--stk) = (rt_uint32_t) 0x00000019;	/* 25 t9 */
-	*(--stk) = (rt_uint32_t) 0x00000018;	/* 24 t8 */
-	*(--stk) = (rt_uint32_t) 0x00000017;	/* 23 s7 */
-	*(--stk) = (rt_uint32_t) 0x00000016;	/* 22 s6 */
-	*(--stk) = (rt_uint32_t) 0x00000015;	/* 21 s5 */
-	*(--stk) = (rt_uint32_t) 0x00000014;	/* 20 s4 */
-	*(--stk) = (rt_uint32_t) 0x00000013;	/* 19 s3 */
-	*(--stk) = (rt_uint32_t) 0x00000012;	/* 18 s2 */
-	*(--stk) = (rt_uint32_t) 0x00000011;	/* 17 s1 */
-	*(--stk) = (rt_uint32_t) 0x00000010;	/* 16 s0 */
-	*(--stk) = (rt_uint32_t) 0x0000000f;	/* 15 t7 */
-	*(--stk) = (rt_uint32_t) 0x0000000e;	/* 14 t6 */
-	*(--stk) = (rt_uint32_t) 0x0000000d;	/* 13 t5 */
-	*(--stk) = (rt_uint32_t) 0x0000000c;	/* 12 t4 */
-	*(--stk) = (rt_uint32_t) 0x0000000b;	/* 11 t3 */
-	*(--stk) = (rt_uint32_t) 0x0000000a; 	/* 10 t2 */
-	*(--stk) = (rt_uint32_t) 0x00000009;	/* 9 t1 */
-	*(--stk) = (rt_uint32_t) 0x00000008;	/* 8 t0 */
-	*(--stk) = (rt_uint32_t) 0x00000007;	/* 7 a3 */
-	*(--stk) = (rt_uint32_t) 0x00000006;	/* 6 a2 */
-	*(--stk) = (rt_uint32_t) 0x00000005;	/* 5 a1 */
-	*(--stk) = (rt_uint32_t) parameter;	    /* 4 a0 */
-	*(--stk) = (rt_uint32_t) 0x00000003;	/* 3 v1 */
-	*(--stk) = (rt_uint32_t) 0x00000002;	/* 2 v0 */
-	*(--stk) = (rt_uint32_t) 0x00000001;	/* 1 at */
-	*(--stk) = (rt_uint32_t) 0x00000000;	/* 0 zero */
+    *(stk)   = (rt_uint32_t) tentry;        /* pc: Entry Point */
+    *(--stk) = (rt_uint32_t) 0x00800000;    /* c0_cause: IV=1, */
+    *(--stk) = (rt_uint32_t) 0;             /* c0_badvaddr */
+    *(--stk) = (rt_uint32_t) 0;             /* lo */
+    *(--stk) = (rt_uint32_t) 0;             /* hi */
+    *(--stk) = (rt_uint32_t) 1;             /* C0_SR: IE = En, */
+    *(--stk) = (rt_uint32_t) texit;         /* 31 ra */
+    *(--stk) = (rt_uint32_t) 0x0000001e;    /* 30 s8 */
+    *(--stk) = (rt_uint32_t) stack_addr;    /* 29 sp */
+    *(--stk) = (rt_uint32_t) _get_gp();     /* 28 gp */
+    *(--stk) = (rt_uint32_t) 0x0000001b;    /* 27 k1 */
+    *(--stk) = (rt_uint32_t) 0x0000001a;    /* 26 k0 */
+    *(--stk) = (rt_uint32_t) 0x00000019;    /* 25 t9 */
+    *(--stk) = (rt_uint32_t) 0x00000018;    /* 24 t8 */
+    *(--stk) = (rt_uint32_t) 0x00000017;    /* 23 s7 */
+    *(--stk) = (rt_uint32_t) 0x00000016;    /* 22 s6 */
+    *(--stk) = (rt_uint32_t) 0x00000015;    /* 21 s5 */
+    *(--stk) = (rt_uint32_t) 0x00000014;    /* 20 s4 */
+    *(--stk) = (rt_uint32_t) 0x00000013;    /* 19 s3 */
+    *(--stk) = (rt_uint32_t) 0x00000012;    /* 18 s2 */
+    *(--stk) = (rt_uint32_t) 0x00000011;    /* 17 s1 */
+    *(--stk) = (rt_uint32_t) 0x00000010;    /* 16 s0 */
+    *(--stk) = (rt_uint32_t) 0x0000000f;    /* 15 t7 */
+    *(--stk) = (rt_uint32_t) 0x0000000e;    /* 14 t6 */
+    *(--stk) = (rt_uint32_t) 0x0000000d;    /* 13 t5 */
+    *(--stk) = (rt_uint32_t) 0x0000000c;    /* 12 t4 */
+    *(--stk) = (rt_uint32_t) 0x0000000b;    /* 11 t3 */
+    *(--stk) = (rt_uint32_t) 0x0000000a;    /* 10 t2 */
+    *(--stk) = (rt_uint32_t) 0x00000009;    /* 9 t1 */
+    *(--stk) = (rt_uint32_t) 0x00000008;    /* 8 t0 */
+    *(--stk) = (rt_uint32_t) 0x00000007;    /* 7 a3 */
+    *(--stk) = (rt_uint32_t) 0x00000006;    /* 6 a2 */
+    *(--stk) = (rt_uint32_t) 0x00000005;    /* 5 a1 */
+    *(--stk) = (rt_uint32_t) parameter;     /* 4 a0 */
+    *(--stk) = (rt_uint32_t) 0x00000003;    /* 3 v1 */
+    *(--stk) = (rt_uint32_t) 0x00000002;    /* 2 v0 */
+    *(--stk) = (rt_uint32_t) 0x00000001;    /* 1 at */
+    *(--stk) = (rt_uint32_t) 0x00000000;    /* 0 zero */
 
-	/* return task's current stack address */
-	return (rt_uint8_t *)stk;
+    /* return task's current stack address */
+    return (rt_uint8_t *)stk;
 }
 
 
diff --git a/libcpu/mips/pic32/exceptions.c b/libcpu/mips/pic32/exceptions.c
index de5f70b7e1..d9f457a707 100644
--- a/libcpu/mips/pic32/exceptions.c
+++ b/libcpu/mips/pic32/exceptions.c
@@ -11,13 +11,13 @@
  * Complier:        MPLAB C32
  *                  MPLAB IDE
  * Company:         Microchip Technology, Inc.
- * Author:			Darren Wenn
+ * Author:          Darren Wenn
  *
  * Software License Agreement
  *
  * The software supplied herewith by Microchip Technology Incorporated
- * (the Company) for its PIC32/PIC24 Microcontroller is intended
- * and supplied to you, the Companys customer, for use solely and
+ * (the “Company”) for its PIC32/PIC24 Microcontroller is intended
+ * and supplied to you, the Company’s customer, for use solely and
  * exclusively on Microchip PIC32/PIC24 Microcontroller products.
  * The software is owned by the Company and/or its supplier, and is
  * protected under applicable copyright laws. All rights are reserved.
@@ -26,7 +26,7 @@
  * civil liability for the breach of the terms and conditions of this
  * license.
  *
- * THIS SOFTWARE IS PROVIDED IN AN AS IS CONDITION. NO WARRANTIES,
+ * THIS SOFTWARE IS PROVIDED IN AN “AS IS” CONDITION. NO WARRANTIES,
  * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED
  * TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  * PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT,
@@ -42,20 +42,20 @@
 // declared static in case exception condition would prevent
 // auto variable being created
 static enum {
-	EXCEP_IRQ = 0,			// interrupt
-	EXCEP_AdEL = 4,			// address error exception (load or ifetch)
-	EXCEP_AdES,				// address error exception (store)
-	EXCEP_IBE,				// bus error (ifetch)
-	EXCEP_DBE,				// bus error (load/store)
-	EXCEP_Sys,				// syscall
-	EXCEP_Bp,				// breakpoint
-	EXCEP_RI,				// reserved instruction
-	EXCEP_CpU,				// coprocessor unusable
-	EXCEP_Overflow,			// arithmetic overflow
-	EXCEP_Trap,				// trap (possible divide by zero)
-	EXCEP_IS1 = 16,			// implementation specfic 1
-	EXCEP_CEU,				// CorExtend Unuseable
-	EXCEP_C2E				// coprocessor 2
+    EXCEP_IRQ = 0,          // interrupt
+    EXCEP_AdEL = 4,         // address error exception (load or ifetch)
+    EXCEP_AdES,             // address error exception (store)
+    EXCEP_IBE,              // bus error (ifetch)
+    EXCEP_DBE,              // bus error (load/store)
+    EXCEP_Sys,              // syscall
+    EXCEP_Bp,               // breakpoint
+    EXCEP_RI,               // reserved instruction
+    EXCEP_CpU,              // coprocessor unusable
+    EXCEP_Overflow,         // arithmetic overflow
+    EXCEP_Trap,             // trap (possible divide by zero)
+    EXCEP_IS1 = 16,         // implementation specfic 1
+    EXCEP_CEU,              // CorExtend Unuseable
+    EXCEP_C2E               // coprocessor 2
 } _excep_code;
 
 static unsigned int _epc_code;
@@ -65,34 +65,34 @@ static unsigned int _excep_addr;
 // this function overrides the normal _weak_ generic handler
 void _general_exception_handler(void)
 {
-	asm volatile("mfc0 %0,$13" : "=r" (_excep_code));
-	asm volatile("mfc0 %0,$14" : "=r" (_excep_addr));
+    asm volatile("mfc0 %0,$13" : "=r" (_excep_code));
+    asm volatile("mfc0 %0,$14" : "=r" (_excep_addr));
 
-	_excep_code = (_excep_code & 0x0000007C) >> 2;
+    _excep_code = (_excep_code & 0x0000007C) >> 2;
 
-	rt_kprintf("\r\n_excep_code : %08X\r\n",_excep_code);
-	rt_kprintf("_excep_addr : %08X\r\n",_excep_addr);
-	switch(_excep_code)
-	{
-	    case EXCEP_IRQ:rt_kprintf("interrupt\r\n");break;
-	    case EXCEP_AdEL:rt_kprintf("address error exception (load or ifetch)\r\n");break;
-	    case EXCEP_AdES:rt_kprintf("address error exception (store)\r\n");break;
-	    case EXCEP_IBE:rt_kprintf("bus error (ifetch)\r\n");break;
-	    case EXCEP_DBE:rt_kprintf("bus error (load/store)\r\n");break;
-	    case EXCEP_Sys:rt_kprintf("syscall\r\n");break;
-	    case EXCEP_Bp:rt_kprintf("breakpoint\r\n");break;
-	    case EXCEP_RI:rt_kprintf("reserved instruction\r\n");break;
-	    case EXCEP_CpU:rt_kprintf("coprocessor unusable\r\n");break;
-	    case EXCEP_Overflow:rt_kprintf("arithmetic overflow\r\n");break;
-	    case EXCEP_Trap:rt_kprintf("trap (possible divide by zero)\r\n");break;
-	    case EXCEP_IS1:rt_kprintf("implementation specfic 1\r\n");break;
-	    case EXCEP_CEU:rt_kprintf("CorExtend Unuseable\r\n");break;
-	    case EXCEP_C2E:rt_kprintf("coprocessor 2\r\n");break;
-	    default : rt_kprintf("unkown exception\r\n");break;
-	}
+    rt_kprintf("\r\n_excep_code : %08X\r\n",_excep_code);
+    rt_kprintf("_excep_addr : %08X\r\n",_excep_addr);
+    switch(_excep_code)
+    {
+        case EXCEP_IRQ:rt_kprintf("interrupt\r\n");break;
+        case EXCEP_AdEL:rt_kprintf("address error exception (load or ifetch)\r\n");break;
+        case EXCEP_AdES:rt_kprintf("address error exception (store)\r\n");break;
+        case EXCEP_IBE:rt_kprintf("bus error (ifetch)\r\n");break;
+        case EXCEP_DBE:rt_kprintf("bus error (load/store)\r\n");break;
+        case EXCEP_Sys:rt_kprintf("syscall\r\n");break;
+        case EXCEP_Bp:rt_kprintf("breakpoint\r\n");break;
+        case EXCEP_RI:rt_kprintf("reserved instruction\r\n");break;
+        case EXCEP_CpU:rt_kprintf("coprocessor unusable\r\n");break;
+        case EXCEP_Overflow:rt_kprintf("arithmetic overflow\r\n");break;
+        case EXCEP_Trap:rt_kprintf("trap (possible divide by zero)\r\n");break;
+        case EXCEP_IS1:rt_kprintf("implementation specfic 1\r\n");break;
+        case EXCEP_CEU:rt_kprintf("CorExtend Unuseable\r\n");break;
+        case EXCEP_C2E:rt_kprintf("coprocessor 2\r\n");break;
+        default : rt_kprintf("unkown exception\r\n");break;
+    }
 
-	while (1) {
-		// Examine _excep_code to identify the type of exception
-		// Examine _excep_addr to find the address that caused the exception
-	}
+    while (1) {
+        // Examine _excep_code to identify the type of exception
+        // Examine _excep_addr to find the address that caused the exception
+    }
 }
diff --git a/libcpu/nios/nios_ii/stack.c b/libcpu/nios/nios_ii/stack.c
index 125bf2c578..463ba0df96 100644
--- a/libcpu/nios/nios_ii/stack.c
+++ b/libcpu/nios/nios_ii/stack.c
@@ -1,7 +1,7 @@
 /*
  * File      : stack.c
  * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2011, RT-Thread Development Team
+ * COPYRIGHT (C) 2006-2021, RT-Thread Development Team
  *
  * The license and distribution terms for this file may be
  * found in the file LICENSE in this distribution or at
@@ -30,43 +30,43 @@
  * @return stack address
  */
 rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
-	rt_uint8_t *stack_addr, void *texit)
+    rt_uint8_t *stack_addr, void *texit)
 {
-	unsigned long *stk;
+    unsigned long *stk;
 
-	stk 	 = (unsigned long *)stack_addr;
-	*(stk)   = 0x01;                        /* status  */
-	*(--stk) = (unsigned long)texit;        /* ra  */
-	*(--stk) = 0xdeadbeef;                  /* fp  */
-	*(--stk) = 0xdeadbeef;                  /* r23 */
-	*(--stk) = 0xdeadbeef;                  /* r22 */
-	*(--stk) = 0xdeadbeef;                  /* r21 */
-	*(--stk) = 0xdeadbeef;                  /* r20 */
-	*(--stk) = 0xdeadbeef;                  /* r19 */
-	*(--stk) = 0xdeadbeef;                  /* r18 */
-	*(--stk) = 0xdeadbeef;                  /* r17 */
-	*(--stk) = 0xdeadbeef;                  /* r16 */
-//	*(--stk) = 0xdeadbeef;                  /* r15 */
-//	*(--stk) = 0xdeadbeef;                  /* r14 */
-//	*(--stk) = 0xdeadbeef;                  /* r13 */
-//	*(--stk) = 0xdeadbeef;                  /* r12 */
-//	*(--stk) = 0xdeadbeef;                  /* r11 */
-//	*(--stk) = 0xdeadbeef;                  /* r10 */
-//	*(--stk) = 0xdeadbeef;                  /* r9  */
-//	*(--stk) = 0xdeadbeef;                  /* r8  */
-	*(--stk) = 0xdeadbeef;                  /* r7  */
-	*(--stk) = 0xdeadbeef;                  /* r6  */
-	*(--stk) = 0xdeadbeef;                  /* r5  */
-	*(--stk) = (unsigned long)parameter;    /* r4 argument */
-	*(--stk) = 0xdeadbeef;                  /* r3  */
-	*(--stk) = 0xdeadbeef;                  /* r2  */
-	*(--stk) = (unsigned long)tentry;       /* pc  */
+    stk      = (unsigned long *)stack_addr;
+    *(stk)   = 0x01;                        /* status  */
+    *(--stk) = (unsigned long)texit;        /* ra  */
+    *(--stk) = 0xdeadbeef;                  /* fp  */
+    *(--stk) = 0xdeadbeef;                  /* r23 */
+    *(--stk) = 0xdeadbeef;                  /* r22 */
+    *(--stk) = 0xdeadbeef;                  /* r21 */
+    *(--stk) = 0xdeadbeef;                  /* r20 */
+    *(--stk) = 0xdeadbeef;                  /* r19 */
+    *(--stk) = 0xdeadbeef;                  /* r18 */
+    *(--stk) = 0xdeadbeef;                  /* r17 */
+    *(--stk) = 0xdeadbeef;                  /* r16 */
+//  *(--stk) = 0xdeadbeef;                  /* r15 */
+//  *(--stk) = 0xdeadbeef;                  /* r14 */
+//  *(--stk) = 0xdeadbeef;                  /* r13 */
+//  *(--stk) = 0xdeadbeef;                  /* r12 */
+//  *(--stk) = 0xdeadbeef;                  /* r11 */
+//  *(--stk) = 0xdeadbeef;                  /* r10 */
+//  *(--stk) = 0xdeadbeef;                  /* r9  */
+//  *(--stk) = 0xdeadbeef;                  /* r8  */
+    *(--stk) = 0xdeadbeef;                  /* r7  */
+    *(--stk) = 0xdeadbeef;                  /* r6  */
+    *(--stk) = 0xdeadbeef;                  /* r5  */
+    *(--stk) = (unsigned long)parameter;    /* r4 argument */
+    *(--stk) = 0xdeadbeef;                  /* r3  */
+    *(--stk) = 0xdeadbeef;                  /* r2  */
+    *(--stk) = (unsigned long)tentry;       /* pc  */
 
-//	*(stk)   = (unsigned long)tentry;		/* thread entry (ra) */
-//	*(--stk) = (unsigned long)parameter;	/* thread argument, r4 */
+//  *(stk)   = (unsigned long)tentry;       /* thread entry (ra) */
+//  *(--stk) = (unsigned long)parameter;    /* thread argument, r4 */
 
-	/* return task's current stack address */
-	return (rt_uint8_t *)stk;
+    /* return task's current stack address */
+    return (rt_uint8_t *)stk;
 }
 
 /*@}*/
diff --git a/libcpu/ppc/common/ptrace.h b/libcpu/ppc/common/ptrace.h
index 72ef31bfbc..8d06ed00ca 100644
--- a/libcpu/ppc/common/ptrace.h
+++ b/libcpu/ppc/common/ptrace.h
@@ -24,24 +24,24 @@ struct pt_regs {
     PPC_REG gpr[32];
     PPC_REG nip;
     PPC_REG msr;
-    PPC_REG orig_gpr3;	/* Used for restarting system calls */
+    PPC_REG orig_gpr3;  /* Used for restarting system calls */
     PPC_REG ctr;
     PPC_REG link;
     PPC_REG xer;
     PPC_REG ccr;
-    PPC_REG mq;		/* 601 only (not used at present) */
+    PPC_REG mq;     /* 601 only (not used at present) */
                     /* Used on APUS to hold IPL value. */
-    PPC_REG trap;		/* Reason for being here */
-    PPC_REG dar;		/* Fault registers */
+    PPC_REG trap;       /* Reason for being here */
+    PPC_REG dar;        /* Fault registers */
     PPC_REG dsisr;
-    PPC_REG result;		/* Result of a system call */
+    PPC_REG result;     /* Result of a system call */
 }__attribute__((packed)) CELL_STACK_FRAME_t;
 #endif
 
-#define STACK_FRAME_OVERHEAD	16	/* size of minimum stack frame */
+#define STACK_FRAME_OVERHEAD    16  /* size of minimum stack frame */
 
 /* Size of stack frame allocated when calling signal handler. */
-#define __SIGNAL_FRAMESIZE	64
+#define __SIGNAL_FRAMESIZE  64
 
 #define instruction_pointer(regs) ((regs)->nip)
 #define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
@@ -51,49 +51,49 @@ struct pt_regs {
  * These can't be changed without breaking binary compatibility
  * with MkLinux, etc.
  */
-#define PT_R0	0
-#define PT_R1	1
-#define PT_R2	2
-#define PT_R3	3
-#define PT_R4	4
-#define PT_R5	5
-#define PT_R6	6
-#define PT_R7	7
-#define PT_R8	8
-#define PT_R9	9
-#define PT_R10	10
-#define PT_R11	11
-#define PT_R12	12
-#define PT_R13	13
-#define PT_R14	14
-#define PT_R15	15
-#define PT_R16	16
-#define PT_R17	17
-#define PT_R18	18
-#define PT_R19	19
-#define PT_R20	20
-#define PT_R21	21
-#define PT_R22	22
-#define PT_R23	23
-#define PT_R24	24
-#define PT_R25	25
-#define PT_R26	26
-#define PT_R27	27
-#define PT_R28	28
-#define PT_R29	29
-#define PT_R30	30
-#define PT_R31	31
+#define PT_R0   0
+#define PT_R1   1
+#define PT_R2   2
+#define PT_R3   3
+#define PT_R4   4
+#define PT_R5   5
+#define PT_R6   6
+#define PT_R7   7
+#define PT_R8   8
+#define PT_R9   9
+#define PT_R10  10
+#define PT_R11  11
+#define PT_R12  12
+#define PT_R13  13
+#define PT_R14  14
+#define PT_R15  15
+#define PT_R16  16
+#define PT_R17  17
+#define PT_R18  18
+#define PT_R19  19
+#define PT_R20  20
+#define PT_R21  21
+#define PT_R22  22
+#define PT_R23  23
+#define PT_R24  24
+#define PT_R25  25
+#define PT_R26  26
+#define PT_R27  27
+#define PT_R28  28
+#define PT_R29  29
+#define PT_R30  30
+#define PT_R31  31
 
-#define PT_NIP	32
-#define PT_MSR	33
+#define PT_NIP  32
+#define PT_MSR  33
 #define PT_ORIG_R3 34
-#define PT_CTR	35
-#define PT_LNK	36
-#define PT_XER	37
-#define PT_CCR	38
-#define PT_MQ	39
+#define PT_CTR  35
+#define PT_LNK  36
+#define PT_XER  37
+#define PT_CCR  38
+#define PT_MQ   39
 
-#define PT_FPR0	48	/* each FP reg occupies 2 slots in this space */
+#define PT_FPR0 48  /* each FP reg occupies 2 slots in this space */
 #define PT_FPR31 (PT_FPR0 + 2*31)
 #define PT_FPSCR (PT_FPR0 + 2*32 + 1)
 
diff --git a/libcpu/ppc/common/stack.c b/libcpu/ppc/common/stack.c
index 570e9ba046..de9d7d2016 100644
--- a/libcpu/ppc/common/stack.c
+++ b/libcpu/ppc/common/stack.c
@@ -1,7 +1,7 @@
 /*
  * File      : stack.c
  * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2011, RT-Thread Development Team
+ * COPYRIGHT (C) 2006-2021, RT-Thread Development Team
  *
  * The license and distribution terms for this file may be
  * found in the file LICENSE in this distribution or at
@@ -9,7 +9,7 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2011-02-14     Fred         first implementation for 
+ * 2011-02-14     Fred         first implementation for
  */
 
 #include 
diff --git a/libcpu/ppc/ppc405/context.h b/libcpu/ppc/ppc405/context.h
index 8b4d55d698..cb12df845c 100644
--- a/libcpu/ppc/ppc405/context.h
+++ b/libcpu/ppc/ppc405/context.h
@@ -1,9 +1,9 @@
 #ifndef __CONTEXT_H__
 #define __CONTEXT_H__
 
-#define MSR_ME		(1<<12)		/* Machine Check Enable */
+#define MSR_ME      (1<<12)     /* Machine Check Enable */
 #define MSR_EE      (1<<15)     /* External Interrupt Enable */
-#define MSR_CE		(1<<17)		/* Critical Interrupt Enable */
+#define MSR_CE      (1<<17)     /* Critical Interrupt Enable */
 
 #define GPR0    0
 #define GPR2    4
diff --git a/libcpu/ppc/ppc405/include/asm/ppc405.h b/libcpu/ppc/ppc405/include/asm/ppc405.h
index c2562047cb..5e96fa782a 100644
--- a/libcpu/ppc/ppc405/include/asm/ppc405.h
+++ b/libcpu/ppc/ppc405/include/asm/ppc405.h
@@ -1,30 +1,30 @@
 /*----------------------------------------------------------------------------+
 |
-|	This source code has been made available to you by IBM on an AS-IS
-|	basis.	Anyone receiving this source is licensed under IBM
-|	copyrights to use it in any way he or she deems fit, including
-|	copying it, modifying it, compiling it, and redistributing it either
-|	with or without modifications.	No license under IBM patents or
-|	patent applications is to be implied by the copyright license.
+|   This source code has been made available to you by IBM on an AS-IS
+|   basis.  Anyone receiving this source is licensed under IBM
+|   copyrights to use it in any way he or she deems fit, including
+|   copying it, modifying it, compiling it, and redistributing it either
+|   with or without modifications.  No license under IBM patents or
+|   patent applications is to be implied by the copyright license.
 |
-|	Any user of this software should understand that IBM cannot provide
-|	technical support for this software and will not be responsible for
-|	any consequences resulting from the use of this software.
+|   Any user of this software should understand that IBM cannot provide
+|   technical support for this software and will not be responsible for
+|   any consequences resulting from the use of this software.
 |
-|	Any person who transfers this source code or any derivative work
-|	must include the IBM copyright notice, this paragraph, and the
-|	preceding two paragraphs in the transferred software.
+|   Any person who transfers this source code or any derivative work
+|   must include the IBM copyright notice, this paragraph, and the
+|   preceding two paragraphs in the transferred software.
 |
-|	COPYRIGHT   I B M   CORPORATION 1999
-|	LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+|   COPYRIGHT   I B M   CORPORATION 1999
+|   LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
 +----------------------------------------------------------------------------*/
 
-#ifndef	__PPC405_H__
+#ifndef __PPC405_H__
 #define __PPC405_H__
 
 /* Define bits and masks for real-mode storage attribute control registers */
-#define PPC_128MB_SACR_BIT(addr)	((addr) >> 27)
-#define PPC_128MB_SACR_VALUE(addr)	PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1)
+#define PPC_128MB_SACR_BIT(addr)    ((addr) >> 27)
+#define PPC_128MB_SACR_VALUE(addr)  PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1)
 
 /******************************************************************************
  * Special for PPC405GP
@@ -34,29 +34,29 @@
  * DMA
  ******************************************************************************/
 #define DMA_DCR_BASE 0x100
-#define dmacr0	(DMA_DCR_BASE+0x00)  /* DMA channel control register 0	     */
-#define dmact0	(DMA_DCR_BASE+0x01)  /* DMA count register 0		     */
-#define dmada0	(DMA_DCR_BASE+0x02)  /* DMA destination address register 0   */
-#define dmasa0	(DMA_DCR_BASE+0x03)  /* DMA source address register 0	     */
-#define dmasb0	(DMA_DCR_BASE+0x04)  /* DMA scatter/gather descriptor addr 0 */
-#define dmacr1	(DMA_DCR_BASE+0x08)  /* DMA channel control register 1	     */
-#define dmact1	(DMA_DCR_BASE+0x09)  /* DMA count register 1		     */
-#define dmada1	(DMA_DCR_BASE+0x0a)  /* DMA destination address register 1   */
-#define dmasa1	(DMA_DCR_BASE+0x0b)  /* DMA source address register 1	     */
-#define dmasb1	(DMA_DCR_BASE+0x0c)  /* DMA scatter/gather descriptor addr 1 */
-#define dmacr2	(DMA_DCR_BASE+0x10)  /* DMA channel control register 2	     */
-#define dmact2	(DMA_DCR_BASE+0x11)  /* DMA count register 2		     */
-#define dmada2	(DMA_DCR_BASE+0x12)  /* DMA destination address register 2   */
-#define dmasa2	(DMA_DCR_BASE+0x13)  /* DMA source address register 2	     */
-#define dmasb2	(DMA_DCR_BASE+0x14)  /* DMA scatter/gather descriptor addr 2 */
-#define dmacr3	(DMA_DCR_BASE+0x18)  /* DMA channel control register 3	     */
-#define dmact3	(DMA_DCR_BASE+0x19)  /* DMA count register 3		     */
-#define dmada3	(DMA_DCR_BASE+0x1a)  /* DMA destination address register 3   */
-#define dmasa3	(DMA_DCR_BASE+0x1b)  /* DMA source address register 3	     */
-#define dmasb3	(DMA_DCR_BASE+0x1c)  /* DMA scatter/gather descriptor addr 3 */
-#define dmasr	(DMA_DCR_BASE+0x20)  /* DMA status register		     */
-#define dmasgc	(DMA_DCR_BASE+0x23)  /* DMA scatter/gather command register  */
-#define dmaadr	(DMA_DCR_BASE+0x24)  /* DMA address decode register	     */
+#define dmacr0  (DMA_DCR_BASE+0x00)  /* DMA channel control register 0       */
+#define dmact0  (DMA_DCR_BASE+0x01)  /* DMA count register 0             */
+#define dmada0  (DMA_DCR_BASE+0x02)  /* DMA destination address register 0   */
+#define dmasa0  (DMA_DCR_BASE+0x03)  /* DMA source address register 0        */
+#define dmasb0  (DMA_DCR_BASE+0x04)  /* DMA scatter/gather descriptor addr 0 */
+#define dmacr1  (DMA_DCR_BASE+0x08)  /* DMA channel control register 1       */
+#define dmact1  (DMA_DCR_BASE+0x09)  /* DMA count register 1             */
+#define dmada1  (DMA_DCR_BASE+0x0a)  /* DMA destination address register 1   */
+#define dmasa1  (DMA_DCR_BASE+0x0b)  /* DMA source address register 1        */
+#define dmasb1  (DMA_DCR_BASE+0x0c)  /* DMA scatter/gather descriptor addr 1 */
+#define dmacr2  (DMA_DCR_BASE+0x10)  /* DMA channel control register 2       */
+#define dmact2  (DMA_DCR_BASE+0x11)  /* DMA count register 2             */
+#define dmada2  (DMA_DCR_BASE+0x12)  /* DMA destination address register 2   */
+#define dmasa2  (DMA_DCR_BASE+0x13)  /* DMA source address register 2        */
+#define dmasb2  (DMA_DCR_BASE+0x14)  /* DMA scatter/gather descriptor addr 2 */
+#define dmacr3  (DMA_DCR_BASE+0x18)  /* DMA channel control register 3       */
+#define dmact3  (DMA_DCR_BASE+0x19)  /* DMA count register 3             */
+#define dmada3  (DMA_DCR_BASE+0x1a)  /* DMA destination address register 3   */
+#define dmasa3  (DMA_DCR_BASE+0x1b)  /* DMA source address register 3        */
+#define dmasb3  (DMA_DCR_BASE+0x1c)  /* DMA scatter/gather descriptor addr 3 */
+#define dmasr   (DMA_DCR_BASE+0x20)  /* DMA status register          */
+#define dmasgc  (DMA_DCR_BASE+0x23)  /* DMA scatter/gather command register  */
+#define dmaadr  (DMA_DCR_BASE+0x24)  /* DMA address decode register      */
 
 #ifndef CONFIG_405EP
 /******************************************************************************
@@ -66,22 +66,22 @@
 #define kiar  (DECOMP_DCR_BASE+0x0)  /* Decompression controller addr reg    */
 #define kidr  (DECOMP_DCR_BASE+0x1)  /* Decompression controller data reg    */
   /* values for kiar register - indirect addressing of these regs */
-  #define kitor0      0x00    /* index table origin register 0	      */
-  #define kitor1      0x01    /* index table origin register 1	      */
-  #define kitor2      0x02    /* index table origin register 2	      */
-  #define kitor3      0x03    /* index table origin register 3	      */
+  #define kitor0      0x00    /* index table origin register 0        */
+  #define kitor1      0x01    /* index table origin register 1        */
+  #define kitor2      0x02    /* index table origin register 2        */
+  #define kitor3      0x03    /* index table origin register 3        */
   #define kaddr0      0x04    /* address decode definition regsiter 0 */
   #define kaddr1      0x05    /* address decode definition regsiter 1 */
   #define kconf       0x40    /* decompression core config register   */
-  #define kid	      0x41    /* decompression core ID	   register   */
-  #define kver	      0x42    /* decompression core version # reg     */
-  #define kpear       0x50    /* bus error addr reg (PLB addr)	      */
+  #define kid         0x41    /* decompression core ID     register   */
+  #define kver        0x42    /* decompression core version # reg     */
+  #define kpear       0x50    /* bus error addr reg (PLB addr)        */
   #define kbear       0x51    /* bus error addr reg (DCP to EBIU addr)*/
   #define kesr0       0x52    /* bus error status reg 0  (R/clear)    */
-  #define kesr0s      0x53    /* bus error status reg 0  (set)	      */
+  #define kesr0s      0x53    /* bus error status reg 0  (set)        */
   /* There are 0x400 of the following registers, from krom0 to krom3ff*/
-  /* Only the first one is given here.				      */
-  #define krom0      0x400    /* SRAM/ROM read/write		      */
+  /* Only the first one is given here.                    */
+  #define krom0      0x400    /* SRAM/ROM read/write              */
 #endif
 
 /******************************************************************************
@@ -92,23 +92,23 @@
 #else
 #define POWERMAN_DCR_BASE 0xb8
 #endif
-#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status	     */
-#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable	     */
-#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force		     */
+#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status         */
+#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable         */
+#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force          */
 
 /******************************************************************************
  * Extrnal Bus Controller
  ******************************************************************************/
   /* values for ebccfga register - indirect addressing of these regs */
-  #define pb0cr       0x00    /* periph bank 0 config reg	     */
-  #define pb1cr       0x01    /* periph bank 1 config reg	     */
-  #define pb2cr       0x02    /* periph bank 2 config reg	     */
-  #define pb3cr       0x03    /* periph bank 3 config reg	     */
-  #define pb4cr       0x04    /* periph bank 4 config reg	     */
+  #define pb0cr       0x00    /* periph bank 0 config reg        */
+  #define pb1cr       0x01    /* periph bank 1 config reg        */
+  #define pb2cr       0x02    /* periph bank 2 config reg        */
+  #define pb3cr       0x03    /* periph bank 3 config reg        */
+  #define pb4cr       0x04    /* periph bank 4 config reg        */
 #ifndef CONFIG_405EP
-  #define pb5cr       0x05    /* periph bank 5 config reg	     */
-  #define pb6cr       0x06    /* periph bank 6 config reg	     */
-  #define pb7cr       0x07    /* periph bank 7 config reg	     */
+  #define pb5cr       0x05    /* periph bank 5 config reg        */
+  #define pb6cr       0x06    /* periph bank 6 config reg        */
+  #define pb7cr       0x07    /* periph bank 7 config reg        */
 #endif
   #define pb0ap       0x10    /* periph bank 0 access parameters     */
   #define pb1ap       0x11    /* periph bank 1 access parameters     */
@@ -120,221 +120,221 @@
   #define pb6ap       0x16    /* periph bank 6 access parameters     */
   #define pb7ap       0x17    /* periph bank 7 access parameters     */
 #endif
-  #define pbear       0x20    /* periph bus error addr reg	     */
-  #define pbesr0      0x21    /* periph bus error status reg 0	     */
-  #define pbesr1      0x22    /* periph bus error status reg 1	     */
-  #define epcr	      0x23    /* external periph control reg	     */
-#define EBC0_CFG	0x23	/* external bus configuration reg	*/
+  #define pbear       0x20    /* periph bus error addr reg       */
+  #define pbesr0      0x21    /* periph bus error status reg 0       */
+  #define pbesr1      0x22    /* periph bus error status reg 1       */
+  #define epcr        0x23    /* external periph control reg         */
+#define EBC0_CFG    0x23    /* external bus configuration reg   */
 
 #ifdef CONFIG_405EP
 /******************************************************************************
  * Control
  ******************************************************************************/
 #define CNTRL_DCR_BASE 0x0f0
-#define cpc0_pllmr0   (CNTRL_DCR_BASE+0x0)  /* PLL mode  register 0		   */
-#define cpc0_boot     (CNTRL_DCR_BASE+0x1)  /* Clock status register		   */
-#define cpc0_epctl    (CNTRL_DCR_BASE+0x3)  /* EMAC to PHY control register	   */
-#define cpc0_pllmr1   (CNTRL_DCR_BASE+0x4)  /* PLL mode  register 1		   */
-#define cpc0_ucr      (CNTRL_DCR_BASE+0x5)  /* UART control register		   */
-#define cpc0_pci      (CNTRL_DCR_BASE+0x9)  /* PCI control register		   */
+#define cpc0_pllmr0   (CNTRL_DCR_BASE+0x0)  /* PLL mode  register 0        */
+#define cpc0_boot     (CNTRL_DCR_BASE+0x1)  /* Clock status register           */
+#define cpc0_epctl    (CNTRL_DCR_BASE+0x3)  /* EMAC to PHY control register    */
+#define cpc0_pllmr1   (CNTRL_DCR_BASE+0x4)  /* PLL mode  register 1        */
+#define cpc0_ucr      (CNTRL_DCR_BASE+0x5)  /* UART control register           */
+#define cpc0_pci      (CNTRL_DCR_BASE+0x9)  /* PCI control register        */
 
-#define CPC0_PLLMR0  (CNTRL_DCR_BASE+0x0)  /* PLL mode 0 register	   */
+#define CPC0_PLLMR0  (CNTRL_DCR_BASE+0x0)  /* PLL mode 0 register      */
 #define CPC0_BOOT    (CNTRL_DCR_BASE+0x1)  /* Chip Clock Status register   */
-#define CPC0_CR1     (CNTRL_DCR_BASE+0x2)  /* Chip Control 1 register	   */
+#define CPC0_CR1     (CNTRL_DCR_BASE+0x2)  /* Chip Control 1 register      */
 #define CPC0_EPRCSR  (CNTRL_DCR_BASE+0x3)  /* EMAC PHY Rcv Clk Src register*/
-#define CPC0_PLLMR1  (CNTRL_DCR_BASE+0x4)  /* PLL mode 1 register	   */
-#define CPC0_UCR     (CNTRL_DCR_BASE+0x5)  /* UART Control register	   */
-#define CPC0_SRR     (CNTRL_DCR_BASE+0x6)  /* Soft Reset register	   */
-#define CPC0_JTAGID  (CNTRL_DCR_BASE+0x7)  /* JTAG ID register		   */
-#define CPC0_SPARE   (CNTRL_DCR_BASE+0x8)  /* Spare DCR			   */
-#define CPC0_PCI     (CNTRL_DCR_BASE+0x9)  /* PCI Control register	   */
+#define CPC0_PLLMR1  (CNTRL_DCR_BASE+0x4)  /* PLL mode 1 register      */
+#define CPC0_UCR     (CNTRL_DCR_BASE+0x5)  /* UART Control register    */
+#define CPC0_SRR     (CNTRL_DCR_BASE+0x6)  /* Soft Reset register      */
+#define CPC0_JTAGID  (CNTRL_DCR_BASE+0x7)  /* JTAG ID register         */
+#define CPC0_SPARE   (CNTRL_DCR_BASE+0x8)  /* Spare DCR            */
+#define CPC0_PCI     (CNTRL_DCR_BASE+0x9)  /* PCI Control register     */
 
 /* Bit definitions */
-#define PLLMR0_CPU_DIV_MASK	 0x00300000	/* CPU clock divider */
-#define PLLMR0_CPU_DIV_BYPASS	 0x00000000
-#define PLLMR0_CPU_DIV_2	 0x00100000
-#define PLLMR0_CPU_DIV_3	 0x00200000
-#define PLLMR0_CPU_DIV_4	 0x00300000
+#define PLLMR0_CPU_DIV_MASK  0x00300000 /* CPU clock divider */
+#define PLLMR0_CPU_DIV_BYPASS    0x00000000
+#define PLLMR0_CPU_DIV_2     0x00100000
+#define PLLMR0_CPU_DIV_3     0x00200000
+#define PLLMR0_CPU_DIV_4     0x00300000
 
-#define PLLMR0_CPU_TO_PLB_MASK	 0x00030000	/* CPU:PLB Frequency Divisor */
-#define PLLMR0_CPU_PLB_DIV_1	 0x00000000
-#define PLLMR0_CPU_PLB_DIV_2	 0x00010000
-#define PLLMR0_CPU_PLB_DIV_3	 0x00020000
-#define PLLMR0_CPU_PLB_DIV_4	 0x00030000
+#define PLLMR0_CPU_TO_PLB_MASK   0x00030000 /* CPU:PLB Frequency Divisor */
+#define PLLMR0_CPU_PLB_DIV_1     0x00000000
+#define PLLMR0_CPU_PLB_DIV_2     0x00010000
+#define PLLMR0_CPU_PLB_DIV_3     0x00020000
+#define PLLMR0_CPU_PLB_DIV_4     0x00030000
 
-#define PLLMR0_OPB_TO_PLB_MASK	 0x00003000	/* OPB:PLB Frequency Divisor */
-#define PLLMR0_OPB_PLB_DIV_1	 0x00000000
-#define PLLMR0_OPB_PLB_DIV_2	 0x00001000
-#define PLLMR0_OPB_PLB_DIV_3	 0x00002000
-#define PLLMR0_OPB_PLB_DIV_4	 0x00003000
+#define PLLMR0_OPB_TO_PLB_MASK   0x00003000 /* OPB:PLB Frequency Divisor */
+#define PLLMR0_OPB_PLB_DIV_1     0x00000000
+#define PLLMR0_OPB_PLB_DIV_2     0x00001000
+#define PLLMR0_OPB_PLB_DIV_3     0x00002000
+#define PLLMR0_OPB_PLB_DIV_4     0x00003000
 
-#define PLLMR0_EXB_TO_PLB_MASK	 0x00000300	/* External Bus:PLB Divisor  */
-#define PLLMR0_EXB_PLB_DIV_2	 0x00000000
-#define PLLMR0_EXB_PLB_DIV_3	 0x00000100
-#define PLLMR0_EXB_PLB_DIV_4	 0x00000200
-#define PLLMR0_EXB_PLB_DIV_5	 0x00000300
+#define PLLMR0_EXB_TO_PLB_MASK   0x00000300 /* External Bus:PLB Divisor  */
+#define PLLMR0_EXB_PLB_DIV_2     0x00000000
+#define PLLMR0_EXB_PLB_DIV_3     0x00000100
+#define PLLMR0_EXB_PLB_DIV_4     0x00000200
+#define PLLMR0_EXB_PLB_DIV_5     0x00000300
 
-#define PLLMR0_MAL_TO_PLB_MASK	 0x00000030	/* MAL:PLB Divisor  */
-#define PLLMR0_MAL_PLB_DIV_1	 0x00000000
-#define PLLMR0_MAL_PLB_DIV_2	 0x00000010
-#define PLLMR0_MAL_PLB_DIV_3	 0x00000020
-#define PLLMR0_MAL_PLB_DIV_4	 0x00000030
+#define PLLMR0_MAL_TO_PLB_MASK   0x00000030 /* MAL:PLB Divisor  */
+#define PLLMR0_MAL_PLB_DIV_1     0x00000000
+#define PLLMR0_MAL_PLB_DIV_2     0x00000010
+#define PLLMR0_MAL_PLB_DIV_3     0x00000020
+#define PLLMR0_MAL_PLB_DIV_4     0x00000030
 
-#define PLLMR0_PCI_TO_PLB_MASK	 0x00000003	/* PCI:PLB Frequency Divisor */
-#define PLLMR0_PCI_PLB_DIV_1	 0x00000000
-#define PLLMR0_PCI_PLB_DIV_2	 0x00000001
-#define PLLMR0_PCI_PLB_DIV_3	 0x00000002
-#define PLLMR0_PCI_PLB_DIV_4	 0x00000003
+#define PLLMR0_PCI_TO_PLB_MASK   0x00000003 /* PCI:PLB Frequency Divisor */
+#define PLLMR0_PCI_PLB_DIV_1     0x00000000
+#define PLLMR0_PCI_PLB_DIV_2     0x00000001
+#define PLLMR0_PCI_PLB_DIV_3     0x00000002
+#define PLLMR0_PCI_PLB_DIV_4     0x00000003
 
-#define PLLMR1_SSCS_MASK	 0x80000000	/* Select system clock source */
-#define PLLMR1_PLLR_MASK	 0x40000000	/* PLL reset */
-#define PLLMR1_FBMUL_MASK	 0x00F00000	/* PLL feedback multiplier value */
-#define PLLMR1_FBMUL_DIV_16	 0x00000000
-#define PLLMR1_FBMUL_DIV_1	 0x00100000
-#define PLLMR1_FBMUL_DIV_2	 0x00200000
-#define PLLMR1_FBMUL_DIV_3	 0x00300000
-#define PLLMR1_FBMUL_DIV_4	 0x00400000
-#define PLLMR1_FBMUL_DIV_5	 0x00500000
-#define PLLMR1_FBMUL_DIV_6	 0x00600000
-#define PLLMR1_FBMUL_DIV_7	 0x00700000
-#define PLLMR1_FBMUL_DIV_8	 0x00800000
-#define PLLMR1_FBMUL_DIV_9	 0x00900000
-#define PLLMR1_FBMUL_DIV_10	 0x00A00000
-#define PLLMR1_FBMUL_DIV_11	 0x00B00000
-#define PLLMR1_FBMUL_DIV_12	 0x00C00000
-#define PLLMR1_FBMUL_DIV_13	 0x00D00000
-#define PLLMR1_FBMUL_DIV_14	 0x00E00000
-#define PLLMR1_FBMUL_DIV_15	 0x00F00000
+#define PLLMR1_SSCS_MASK     0x80000000 /* Select system clock source */
+#define PLLMR1_PLLR_MASK     0x40000000 /* PLL reset */
+#define PLLMR1_FBMUL_MASK    0x00F00000 /* PLL feedback multiplier value */
+#define PLLMR1_FBMUL_DIV_16  0x00000000
+#define PLLMR1_FBMUL_DIV_1   0x00100000
+#define PLLMR1_FBMUL_DIV_2   0x00200000
+#define PLLMR1_FBMUL_DIV_3   0x00300000
+#define PLLMR1_FBMUL_DIV_4   0x00400000
+#define PLLMR1_FBMUL_DIV_5   0x00500000
+#define PLLMR1_FBMUL_DIV_6   0x00600000
+#define PLLMR1_FBMUL_DIV_7   0x00700000
+#define PLLMR1_FBMUL_DIV_8   0x00800000
+#define PLLMR1_FBMUL_DIV_9   0x00900000
+#define PLLMR1_FBMUL_DIV_10  0x00A00000
+#define PLLMR1_FBMUL_DIV_11  0x00B00000
+#define PLLMR1_FBMUL_DIV_12  0x00C00000
+#define PLLMR1_FBMUL_DIV_13  0x00D00000
+#define PLLMR1_FBMUL_DIV_14  0x00E00000
+#define PLLMR1_FBMUL_DIV_15  0x00F00000
 
-#define PLLMR1_FWDVA_MASK	 0x00070000	/* PLL forward divider A value */
-#define PLLMR1_FWDVA_DIV_8	 0x00000000
-#define PLLMR1_FWDVA_DIV_7	 0x00010000
-#define PLLMR1_FWDVA_DIV_6	 0x00020000
-#define PLLMR1_FWDVA_DIV_5	 0x00030000
-#define PLLMR1_FWDVA_DIV_4	 0x00040000
-#define PLLMR1_FWDVA_DIV_3	 0x00050000
-#define PLLMR1_FWDVA_DIV_2	 0x00060000
-#define PLLMR1_FWDVA_DIV_1	 0x00070000
-#define PLLMR1_FWDVB_MASK	 0x00007000	/* PLL forward divider B value */
-#define PLLMR1_TUNING_MASK	 0x000003FF	/* PLL tune bits */
+#define PLLMR1_FWDVA_MASK    0x00070000 /* PLL forward divider A value */
+#define PLLMR1_FWDVA_DIV_8   0x00000000
+#define PLLMR1_FWDVA_DIV_7   0x00010000
+#define PLLMR1_FWDVA_DIV_6   0x00020000
+#define PLLMR1_FWDVA_DIV_5   0x00030000
+#define PLLMR1_FWDVA_DIV_4   0x00040000
+#define PLLMR1_FWDVA_DIV_3   0x00050000
+#define PLLMR1_FWDVA_DIV_2   0x00060000
+#define PLLMR1_FWDVA_DIV_1   0x00070000
+#define PLLMR1_FWDVB_MASK    0x00007000 /* PLL forward divider B value */
+#define PLLMR1_TUNING_MASK   0x000003FF /* PLL tune bits */
 
 /* Defines for CPC0_EPRCSR register */
-#define CPC0_EPRCSR_E0NFE	   0x80000000
-#define CPC0_EPRCSR_E1NFE	   0x40000000
-#define CPC0_EPRCSR_E1RPP	   0x00000080
-#define CPC0_EPRCSR_E0RPP	   0x00000040
-#define CPC0_EPRCSR_E1ERP	   0x00000020
-#define CPC0_EPRCSR_E0ERP	   0x00000010
-#define CPC0_EPRCSR_E1PCI	   0x00000002
-#define CPC0_EPRCSR_E0PCI	   0x00000001
+#define CPC0_EPRCSR_E0NFE      0x80000000
+#define CPC0_EPRCSR_E1NFE      0x40000000
+#define CPC0_EPRCSR_E1RPP      0x00000080
+#define CPC0_EPRCSR_E0RPP      0x00000040
+#define CPC0_EPRCSR_E1ERP      0x00000020
+#define CPC0_EPRCSR_E0ERP      0x00000010
+#define CPC0_EPRCSR_E1PCI      0x00000002
+#define CPC0_EPRCSR_E0PCI      0x00000001
 
 /* Defines for CPC0_PCI Register */
-#define CPC0_PCI_SPE			   0x00000010 /* PCIINT/WE select	*/
-#define CPC0_PCI_HOST_CFG_EN		   0x00000008 /* PCI host config Enable */
-#define CPC0_PCI_ARBIT_EN		   0x00000001 /* PCI Internal Arb Enabled*/
+#define CPC0_PCI_SPE               0x00000010 /* PCIINT/WE select   */
+#define CPC0_PCI_HOST_CFG_EN           0x00000008 /* PCI host config Enable */
+#define CPC0_PCI_ARBIT_EN          0x00000001 /* PCI Internal Arb Enabled*/
 
 /* Defines for CPC0_BOOR Register */
-#define CPC0_BOOT_SEP			   0x00000002 /* serial EEPROM present	*/
+#define CPC0_BOOT_SEP              0x00000002 /* serial EEPROM present  */
 
 /* Defines for CPC0_PLLMR1 Register fields */
-#define PLL_ACTIVE		   0x80000000
-#define CPC0_PLLMR1_SSCS	   0x80000000
-#define PLL_RESET		   0x40000000
-#define CPC0_PLLMR1_PLLR	   0x40000000
+#define PLL_ACTIVE         0x80000000
+#define CPC0_PLLMR1_SSCS       0x80000000
+#define PLL_RESET          0x40000000
+#define CPC0_PLLMR1_PLLR       0x40000000
     /* Feedback multiplier */
-#define PLL_FBKDIV		   0x00F00000
-#define CPC0_PLLMR1_FBDV	   0x00F00000
-#define PLL_FBKDIV_16		   0x00000000
-#define PLL_FBKDIV_1		   0x00100000
-#define PLL_FBKDIV_2		   0x00200000
-#define PLL_FBKDIV_3		   0x00300000
-#define PLL_FBKDIV_4		   0x00400000
-#define PLL_FBKDIV_5		   0x00500000
-#define PLL_FBKDIV_6		   0x00600000
-#define PLL_FBKDIV_7		   0x00700000
-#define PLL_FBKDIV_8		   0x00800000
-#define PLL_FBKDIV_9		   0x00900000
-#define PLL_FBKDIV_10		   0x00A00000
-#define PLL_FBKDIV_11		   0x00B00000
-#define PLL_FBKDIV_12		   0x00C00000
-#define PLL_FBKDIV_13		   0x00D00000
-#define PLL_FBKDIV_14		   0x00E00000
-#define PLL_FBKDIV_15		   0x00F00000
+#define PLL_FBKDIV         0x00F00000
+#define CPC0_PLLMR1_FBDV       0x00F00000
+#define PLL_FBKDIV_16          0x00000000
+#define PLL_FBKDIV_1           0x00100000
+#define PLL_FBKDIV_2           0x00200000
+#define PLL_FBKDIV_3           0x00300000
+#define PLL_FBKDIV_4           0x00400000
+#define PLL_FBKDIV_5           0x00500000
+#define PLL_FBKDIV_6           0x00600000
+#define PLL_FBKDIV_7           0x00700000
+#define PLL_FBKDIV_8           0x00800000
+#define PLL_FBKDIV_9           0x00900000
+#define PLL_FBKDIV_10          0x00A00000
+#define PLL_FBKDIV_11          0x00B00000
+#define PLL_FBKDIV_12          0x00C00000
+#define PLL_FBKDIV_13          0x00D00000
+#define PLL_FBKDIV_14          0x00E00000
+#define PLL_FBKDIV_15          0x00F00000
     /* Forward A divisor */
-#define PLL_FWDDIVA		   0x00070000
-#define CPC0_PLLMR1_FWDVA	   0x00070000
-#define PLL_FWDDIVA_8		   0x00000000
-#define PLL_FWDDIVA_7		   0x00010000
-#define PLL_FWDDIVA_6		   0x00020000
-#define PLL_FWDDIVA_5		   0x00030000
-#define PLL_FWDDIVA_4		   0x00040000
-#define PLL_FWDDIVA_3		   0x00050000
-#define PLL_FWDDIVA_2		   0x00060000
-#define PLL_FWDDIVA_1		   0x00070000
+#define PLL_FWDDIVA        0x00070000
+#define CPC0_PLLMR1_FWDVA      0x00070000
+#define PLL_FWDDIVA_8          0x00000000
+#define PLL_FWDDIVA_7          0x00010000
+#define PLL_FWDDIVA_6          0x00020000
+#define PLL_FWDDIVA_5          0x00030000
+#define PLL_FWDDIVA_4          0x00040000
+#define PLL_FWDDIVA_3          0x00050000
+#define PLL_FWDDIVA_2          0x00060000
+#define PLL_FWDDIVA_1          0x00070000
     /* Forward B divisor */
-#define PLL_FWDDIVB		   0x00007000
-#define CPC0_PLLMR1_FWDVB	   0x00007000
-#define PLL_FWDDIVB_8		   0x00000000
-#define PLL_FWDDIVB_7		   0x00001000
-#define PLL_FWDDIVB_6		   0x00002000
-#define PLL_FWDDIVB_5		   0x00003000
-#define PLL_FWDDIVB_4		   0x00004000
-#define PLL_FWDDIVB_3		   0x00005000
-#define PLL_FWDDIVB_2		   0x00006000
-#define PLL_FWDDIVB_1		   0x00007000
+#define PLL_FWDDIVB        0x00007000
+#define CPC0_PLLMR1_FWDVB      0x00007000
+#define PLL_FWDDIVB_8          0x00000000
+#define PLL_FWDDIVB_7          0x00001000
+#define PLL_FWDDIVB_6          0x00002000
+#define PLL_FWDDIVB_5          0x00003000
+#define PLL_FWDDIVB_4          0x00004000
+#define PLL_FWDDIVB_3          0x00005000
+#define PLL_FWDDIVB_2          0x00006000
+#define PLL_FWDDIVB_1          0x00007000
     /* PLL tune bits */
-#define PLL_TUNE_MASK		 0x000003FF
-#define PLL_TUNE_2_M_3		 0x00000133	/*  2 <= M <= 3		      */
-#define PLL_TUNE_4_M_6		 0x00000134	/*  3 <  M <= 6		      */
-#define PLL_TUNE_7_M_10		 0x00000138	/*  6 <  M <= 10	      */
-#define PLL_TUNE_11_M_14	 0x0000013C	/* 10 <  M <= 14	      */
-#define PLL_TUNE_15_M_40	 0x0000023E	/* 14 <  M <= 40	      */
-#define PLL_TUNE_VCO_LOW	 0x00000000	/* 500MHz <= VCO <=  800MHz   */
-#define PLL_TUNE_VCO_HI		 0x00000080	/* 800MHz <  VCO <= 1000MHz   */
+#define PLL_TUNE_MASK        0x000003FF
+#define PLL_TUNE_2_M_3       0x00000133 /*  2 <= M <= 3           */
+#define PLL_TUNE_4_M_6       0x00000134 /*  3 <  M <= 6           */
+#define PLL_TUNE_7_M_10      0x00000138 /*  6 <  M <= 10          */
+#define PLL_TUNE_11_M_14     0x0000013C /* 10 <  M <= 14          */
+#define PLL_TUNE_15_M_40     0x0000023E /* 14 <  M <= 40          */
+#define PLL_TUNE_VCO_LOW     0x00000000 /* 500MHz <= VCO <=  800MHz   */
+#define PLL_TUNE_VCO_HI      0x00000080 /* 800MHz <  VCO <= 1000MHz   */
 
 /* Defines for CPC0_PLLMR0 Register fields */
     /* CPU divisor */
-#define PLL_CPUDIV		   0x00300000
-#define CPC0_PLLMR0_CCDV	   0x00300000
-#define PLL_CPUDIV_1		   0x00000000
-#define PLL_CPUDIV_2		   0x00100000
-#define PLL_CPUDIV_3		   0x00200000
-#define PLL_CPUDIV_4		   0x00300000
+#define PLL_CPUDIV         0x00300000
+#define CPC0_PLLMR0_CCDV       0x00300000
+#define PLL_CPUDIV_1           0x00000000
+#define PLL_CPUDIV_2           0x00100000
+#define PLL_CPUDIV_3           0x00200000
+#define PLL_CPUDIV_4           0x00300000
     /* PLB divisor */
-#define PLL_PLBDIV		   0x00030000
-#define CPC0_PLLMR0_CBDV	   0x00030000
-#define PLL_PLBDIV_1		   0x00000000
-#define PLL_PLBDIV_2		   0x00010000
-#define PLL_PLBDIV_3		   0x00020000
-#define PLL_PLBDIV_4		   0x00030000
+#define PLL_PLBDIV         0x00030000
+#define CPC0_PLLMR0_CBDV       0x00030000
+#define PLL_PLBDIV_1           0x00000000
+#define PLL_PLBDIV_2           0x00010000
+#define PLL_PLBDIV_3           0x00020000
+#define PLL_PLBDIV_4           0x00030000
     /* OPB divisor */
-#define PLL_OPBDIV		   0x00003000
-#define CPC0_PLLMR0_OPDV	   0x00003000
-#define PLL_OPBDIV_1		   0x00000000
-#define PLL_OPBDIV_2		   0x00001000
-#define PLL_OPBDIV_3		   0x00002000
-#define PLL_OPBDIV_4		   0x00003000
+#define PLL_OPBDIV         0x00003000
+#define CPC0_PLLMR0_OPDV       0x00003000
+#define PLL_OPBDIV_1           0x00000000
+#define PLL_OPBDIV_2           0x00001000
+#define PLL_OPBDIV_3           0x00002000
+#define PLL_OPBDIV_4           0x00003000
     /* EBC divisor */
-#define PLL_EXTBUSDIV		   0x00000300
-#define CPC0_PLLMR0_EPDV	   0x00000300
-#define PLL_EXTBUSDIV_2		   0x00000000
-#define PLL_EXTBUSDIV_3		   0x00000100
-#define PLL_EXTBUSDIV_4		   0x00000200
-#define PLL_EXTBUSDIV_5		   0x00000300
+#define PLL_EXTBUSDIV          0x00000300
+#define CPC0_PLLMR0_EPDV       0x00000300
+#define PLL_EXTBUSDIV_2        0x00000000
+#define PLL_EXTBUSDIV_3        0x00000100
+#define PLL_EXTBUSDIV_4        0x00000200
+#define PLL_EXTBUSDIV_5        0x00000300
     /* MAL divisor */
-#define PLL_MALDIV		   0x00000030
-#define CPC0_PLLMR0_MPDV	   0x00000030
-#define PLL_MALDIV_1		   0x00000000
-#define PLL_MALDIV_2		   0x00000010
-#define PLL_MALDIV_3		   0x00000020
-#define PLL_MALDIV_4		   0x00000030
+#define PLL_MALDIV         0x00000030
+#define CPC0_PLLMR0_MPDV       0x00000030
+#define PLL_MALDIV_1           0x00000000
+#define PLL_MALDIV_2           0x00000010
+#define PLL_MALDIV_3           0x00000020
+#define PLL_MALDIV_4           0x00000030
     /* PCI divisor */
-#define PLL_PCIDIV		   0x00000003
-#define CPC0_PLLMR0_PPFD	   0x00000003
-#define PLL_PCIDIV_1		   0x00000000
-#define PLL_PCIDIV_2		   0x00000001
-#define PLL_PCIDIV_3		   0x00000002
-#define PLL_PCIDIV_4		   0x00000003
+#define PLL_PCIDIV         0x00000003
+#define CPC0_PLLMR0_PPFD       0x00000003
+#define PLL_PCIDIV_1           0x00000000
+#define PLL_PCIDIV_2           0x00000001
+#define PLL_PCIDIV_3           0x00000002
+#define PLL_PCIDIV_4           0x00000003
 
 /*
  *-------------------------------------------------------------------------------
@@ -343,48 +343,48 @@
  *-------------------------------------------------------------------------------
  */
 #define PLLMR0_266_133_66  (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
-			    PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
-			    PLL_MALDIV_1 | PLL_PCIDIV_4)
+                PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
+                PLL_MALDIV_1 | PLL_PCIDIV_4)
 #define PLLMR1_266_133_66  (PLL_FBKDIV_8  |  \
-			    PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
-			    PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+                PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
+                PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 
 #define PLLMR0_133_66_66_33  (PLL_CPUDIV_1 | PLL_PLBDIV_1 |  \
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
-			      PLL_MALDIV_1 | PLL_PCIDIV_4)
+                  PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
+                  PLL_MALDIV_1 | PLL_PCIDIV_4)
 #define PLLMR1_133_66_66_33  (PLL_FBKDIV_4  |  \
-			      PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |  \
-			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+                  PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |  \
+                  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 #define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
-			      PLL_MALDIV_1 | PLL_PCIDIV_4)
+                  PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |  \
+                  PLL_MALDIV_1 | PLL_PCIDIV_4)
 #define PLLMR1_200_100_50_33 (PLL_FBKDIV_6  |  \
-			      PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
-			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+                  PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
+                  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 #define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
-			      PLL_MALDIV_1 | PLL_PCIDIV_4)
+                  PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
+                  PLL_MALDIV_1 | PLL_PCIDIV_4)
 #define PLLMR1_266_133_66_33 (PLL_FBKDIV_8  |  \
-			      PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
-			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+                  PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
+                  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 #define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 |  \
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |	\
-			      PLL_MALDIV_1 | PLL_PCIDIV_2)
+                  PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
+                  PLL_MALDIV_1 | PLL_PCIDIV_2)
 #define PLLMR1_266_66_33_33 (PLL_FBKDIV_8  |  \
-			      PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
-			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+                  PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
+                  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 #define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |  \
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |	\
-			      PLL_MALDIV_1 | PLL_PCIDIV_3)
-#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10  |	\
-			      PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
-			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
+                  PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
+                  PLL_MALDIV_1 | PLL_PCIDIV_3)
+#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10  |  \
+                  PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
+                  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
 #define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |  \
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |	\
-			      PLL_MALDIV_1 | PLL_PCIDIV_1)
+                  PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
+                  PLL_MALDIV_1 | PLL_PCIDIV_1)
 #define PLLMR1_333_111_55_111 (PLL_FBKDIV_10  |  \
-			      PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
-			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
+                  PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
+                  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
 
 /*
  * PLL Voltage Controlled Oscillator (VCO) definitions
@@ -393,57 +393,57 @@
 #define VCO_MIN     500
 #define VCO_MAX     1000
 #elif defined(CONFIG_405EZ)
-#define sdrnand0	0x4000
-#define sdrultra0	0x4040
-#define sdrultra1	0x4050
-#define sdricintstat	0x4510
+#define sdrnand0    0x4000
+#define sdrultra0   0x4040
+#define sdrultra1   0x4050
+#define sdricintstat    0x4510
 
-#define SDR_NAND0_NDEN		0x80000000
-#define SDR_NAND0_NDBTEN	0x40000000
-#define SDR_NAND0_NDBADR_MASK	0x30000000
-#define SDR_NAND0_NDBPG_MASK	0x0f000000
-#define SDR_NAND0_NDAREN	0x00800000
-#define SDR_NAND0_NDRBEN	0x00400000
+#define SDR_NAND0_NDEN      0x80000000
+#define SDR_NAND0_NDBTEN    0x40000000
+#define SDR_NAND0_NDBADR_MASK   0x30000000
+#define SDR_NAND0_NDBPG_MASK    0x0f000000
+#define SDR_NAND0_NDAREN    0x00800000
+#define SDR_NAND0_NDRBEN    0x00400000
 
-#define SDR_ULTRA0_NDGPIOBP	0x80000000
-#define SDR_ULTRA0_CSN_MASK	0x78000000
-#define SDR_ULTRA0_CSNSEL0	0x40000000
-#define SDR_ULTRA0_CSNSEL1	0x20000000
-#define SDR_ULTRA0_CSNSEL2	0x10000000
-#define SDR_ULTRA0_CSNSEL3	0x08000000
-#define SDR_ULTRA0_EBCRDYEN	0x04000000
-#define SDR_ULTRA0_SPISSINEN	0x02000000
-#define SDR_ULTRA0_NFSRSTEN	0x01000000
+#define SDR_ULTRA0_NDGPIOBP 0x80000000
+#define SDR_ULTRA0_CSN_MASK 0x78000000
+#define SDR_ULTRA0_CSNSEL0  0x40000000
+#define SDR_ULTRA0_CSNSEL1  0x20000000
+#define SDR_ULTRA0_CSNSEL2  0x10000000
+#define SDR_ULTRA0_CSNSEL3  0x08000000
+#define SDR_ULTRA0_EBCRDYEN 0x04000000
+#define SDR_ULTRA0_SPISSINEN    0x02000000
+#define SDR_ULTRA0_NFSRSTEN 0x01000000
 
-#define SDR_ULTRA1_LEDNENABLE	0x40000000
+#define SDR_ULTRA1_LEDNENABLE   0x40000000
 
-#define SDR_ICRX_STAT	0x80000000
-#define SDR_ICTX0_STAT	0x40000000
-#define SDR_ICTX1_STAT	0x20000000
+#define SDR_ICRX_STAT   0x80000000
+#define SDR_ICTX0_STAT  0x40000000
+#define SDR_ICTX1_STAT  0x20000000
 
-#define SDR_PINSTP	0x40
+#define SDR_PINSTP  0x40
 
 /******************************************************************************
  * Control
  ******************************************************************************/
 /* CPR Registers */
-#define cprclkupd	0x020		/* CPR_CLKUPD */
-#define cprpllc		0x040		/* CPR_PLLC */
-#define cprplld		0x060		/* CPR_PLLD */
-#define cprprimad	0x080		/* CPR_PRIMAD */
-#define cprperd0	0x0e0		/* CPR_PERD0 */
-#define cprperd1	0x0e1		/* CPR_PERD1 */
-#define cprperc0	0x180		/* CPR_PERC0 */
-#define cprmisc0	0x181		/* CPR_MISC0 */
-#define cprmisc1	0x182		/* CPR_MISC1 */
+#define cprclkupd   0x020       /* CPR_CLKUPD */
+#define cprpllc     0x040       /* CPR_PLLC */
+#define cprplld     0x060       /* CPR_PLLD */
+#define cprprimad   0x080       /* CPR_PRIMAD */
+#define cprperd0    0x0e0       /* CPR_PERD0 */
+#define cprperd1    0x0e1       /* CPR_PERD1 */
+#define cprperc0    0x180       /* CPR_PERC0 */
+#define cprmisc0    0x181       /* CPR_MISC0 */
+#define cprmisc1    0x182       /* CPR_MISC1 */
 
 #define CPR_CLKUPD_ENPLLCH_EN  0x40000000     /* Enable CPR PLL Changes */
 #define CPR_CLKUPD_ENDVCH_EN   0x20000000     /* Enable CPR Sys. Div. Changes */
 #define CPR_PERD0_SPIDV_MASK   0x000F0000     /* SPI Clock Divider */
 
-#define PLLC_SRC_MASK	       0x20000000     /* PLL feedback source */
+#define PLLC_SRC_MASK          0x20000000     /* PLL feedback source */
 
-#define PLLD_FBDV_MASK	       0x1F000000     /* PLL feedback divider value */
+#define PLLD_FBDV_MASK         0x1F000000     /* PLL feedback divider value */
 #define PLLD_FWDVA_MASK        0x000F0000     /* PLL forward divider A value */
 #define PLLD_FWDVB_MASK        0x00000700     /* PLL forward divider B value */
 
@@ -462,77 +462,77 @@
  * Control
  ******************************************************************************/
 #define CNTRL_DCR_BASE 0x0b0
-#define pllmd	(CNTRL_DCR_BASE+0x0)  /* PLL mode  register		     */
-#define cntrl0	(CNTRL_DCR_BASE+0x1)  /* Control 0 register		     */
-#define cntrl1	(CNTRL_DCR_BASE+0x2)  /* Control 1 register		     */
-#define reset	(CNTRL_DCR_BASE+0x3)  /* reset register			     */
-#define strap	(CNTRL_DCR_BASE+0x4)  /* strap register			     */
+#define pllmd   (CNTRL_DCR_BASE+0x0)  /* PLL mode  register          */
+#define cntrl0  (CNTRL_DCR_BASE+0x1)  /* Control 0 register          */
+#define cntrl1  (CNTRL_DCR_BASE+0x2)  /* Control 1 register          */
+#define reset   (CNTRL_DCR_BASE+0x3)  /* reset register              */
+#define strap   (CNTRL_DCR_BASE+0x4)  /* strap register              */
 
-#define CPC0_CR0  (CNTRL_DCR_BASE+0x1)	/* chip control register 0	     */
-#define CPC0_CR1  (CNTRL_DCR_BASE+0x2)	/* chip control register 1	     */
-#define CPC0_PSR  (CNTRL_DCR_BASE+0x4)	/* chip pin strapping register	     */
+#define CPC0_CR0  (CNTRL_DCR_BASE+0x1)  /* chip control register 0       */
+#define CPC0_CR1  (CNTRL_DCR_BASE+0x2)  /* chip control register 1       */
+#define CPC0_PSR  (CNTRL_DCR_BASE+0x4)  /* chip pin strapping register       */
 
 /* CPC0_ECR/CPC0_EIRR: PPC405GPr only */
-#define CPC0_EIRR (CNTRL_DCR_BASE+0x6)	/* external interrupt routing register */
-#define CPC0_ECR  (0xaa)		/* edge conditioner register */
+#define CPC0_EIRR (CNTRL_DCR_BASE+0x6)  /* external interrupt routing register */
+#define CPC0_ECR  (0xaa)        /* edge conditioner register */
 
-#define ecr	(0xaa)		      /* edge conditioner register (405gpr)  */
+#define ecr (0xaa)            /* edge conditioner register (405gpr)  */
 
 /* Bit definitions */
-#define PLLMR_FWD_DIV_MASK	0xE0000000     /* Forward Divisor */
-#define PLLMR_FWD_DIV_BYPASS	0xE0000000
-#define PLLMR_FWD_DIV_3		0xA0000000
-#define PLLMR_FWD_DIV_4		0x80000000
-#define PLLMR_FWD_DIV_6		0x40000000
+#define PLLMR_FWD_DIV_MASK  0xE0000000     /* Forward Divisor */
+#define PLLMR_FWD_DIV_BYPASS    0xE0000000
+#define PLLMR_FWD_DIV_3     0xA0000000
+#define PLLMR_FWD_DIV_4     0x80000000
+#define PLLMR_FWD_DIV_6     0x40000000
 
-#define PLLMR_FB_DIV_MASK	0x1E000000     /* Feedback Divisor */
-#define PLLMR_FB_DIV_1		0x02000000
-#define PLLMR_FB_DIV_2		0x04000000
-#define PLLMR_FB_DIV_3		0x06000000
-#define PLLMR_FB_DIV_4		0x08000000
+#define PLLMR_FB_DIV_MASK   0x1E000000     /* Feedback Divisor */
+#define PLLMR_FB_DIV_1      0x02000000
+#define PLLMR_FB_DIV_2      0x04000000
+#define PLLMR_FB_DIV_3      0x06000000
+#define PLLMR_FB_DIV_4      0x08000000
 
-#define PLLMR_TUNING_MASK	0x01F80000
+#define PLLMR_TUNING_MASK   0x01F80000
 
-#define PLLMR_CPU_TO_PLB_MASK	0x00060000     /* CPU:PLB Frequency Divisor */
-#define PLLMR_CPU_PLB_DIV_1	0x00000000
-#define PLLMR_CPU_PLB_DIV_2	0x00020000
-#define PLLMR_CPU_PLB_DIV_3	0x00040000
-#define PLLMR_CPU_PLB_DIV_4	0x00060000
+#define PLLMR_CPU_TO_PLB_MASK   0x00060000     /* CPU:PLB Frequency Divisor */
+#define PLLMR_CPU_PLB_DIV_1 0x00000000
+#define PLLMR_CPU_PLB_DIV_2 0x00020000
+#define PLLMR_CPU_PLB_DIV_3 0x00040000
+#define PLLMR_CPU_PLB_DIV_4 0x00060000
 
-#define PLLMR_OPB_TO_PLB_MASK	0x00018000     /* OPB:PLB Frequency Divisor */
-#define PLLMR_OPB_PLB_DIV_1	0x00000000
-#define PLLMR_OPB_PLB_DIV_2	0x00008000
-#define PLLMR_OPB_PLB_DIV_3	0x00010000
-#define PLLMR_OPB_PLB_DIV_4	0x00018000
+#define PLLMR_OPB_TO_PLB_MASK   0x00018000     /* OPB:PLB Frequency Divisor */
+#define PLLMR_OPB_PLB_DIV_1 0x00000000
+#define PLLMR_OPB_PLB_DIV_2 0x00008000
+#define PLLMR_OPB_PLB_DIV_3 0x00010000
+#define PLLMR_OPB_PLB_DIV_4 0x00018000
 
-#define PLLMR_PCI_TO_PLB_MASK	0x00006000     /* PCI:PLB Frequency Divisor */
-#define PLLMR_PCI_PLB_DIV_1	0x00000000
-#define PLLMR_PCI_PLB_DIV_2	0x00002000
-#define PLLMR_PCI_PLB_DIV_3	0x00004000
-#define PLLMR_PCI_PLB_DIV_4	0x00006000
+#define PLLMR_PCI_TO_PLB_MASK   0x00006000     /* PCI:PLB Frequency Divisor */
+#define PLLMR_PCI_PLB_DIV_1 0x00000000
+#define PLLMR_PCI_PLB_DIV_2 0x00002000
+#define PLLMR_PCI_PLB_DIV_3 0x00004000
+#define PLLMR_PCI_PLB_DIV_4 0x00006000
 
-#define PLLMR_EXB_TO_PLB_MASK	0x00001800     /* External Bus:PLB Divisor  */
-#define PLLMR_EXB_PLB_DIV_2	0x00000000
-#define PLLMR_EXB_PLB_DIV_3	0x00000800
-#define PLLMR_EXB_PLB_DIV_4	0x00001000
-#define PLLMR_EXB_PLB_DIV_5	0x00001800
+#define PLLMR_EXB_TO_PLB_MASK   0x00001800     /* External Bus:PLB Divisor  */
+#define PLLMR_EXB_PLB_DIV_2 0x00000000
+#define PLLMR_EXB_PLB_DIV_3 0x00000800
+#define PLLMR_EXB_PLB_DIV_4 0x00001000
+#define PLLMR_EXB_PLB_DIV_5 0x00001800
 
 /* definitions for PPC405GPr (new mode strapping) */
-#define PLLMR_FWDB_DIV_MASK	0x00000007     /* Forward Divisor B */
+#define PLLMR_FWDB_DIV_MASK 0x00000007     /* Forward Divisor B */
 
-#define PSR_PLL_FWD_MASK	0xC0000000
-#define PSR_PLL_FDBACK_MASK	0x30000000
-#define PSR_PLL_TUNING_MASK	0x0E000000
-#define PSR_PLB_CPU_MASK	0x01800000
-#define PSR_OPB_PLB_MASK	0x00600000
-#define PSR_PCI_PLB_MASK	0x00180000
-#define PSR_EB_PLB_MASK		0x00060000
-#define PSR_ROM_WIDTH_MASK	0x00018000
-#define PSR_ROM_LOC		0x00004000
-#define PSR_PCI_ASYNC_EN	0x00001000
+#define PSR_PLL_FWD_MASK    0xC0000000
+#define PSR_PLL_FDBACK_MASK 0x30000000
+#define PSR_PLL_TUNING_MASK 0x0E000000
+#define PSR_PLB_CPU_MASK    0x01800000
+#define PSR_OPB_PLB_MASK    0x00600000
+#define PSR_PCI_PLB_MASK    0x00180000
+#define PSR_EB_PLB_MASK     0x00060000
+#define PSR_ROM_WIDTH_MASK  0x00018000
+#define PSR_ROM_LOC     0x00004000
+#define PSR_PCI_ASYNC_EN    0x00001000
 #define PSR_PERCLK_SYNC_MODE_EN 0x00000800     /* PPC405GPr only */
-#define PSR_PCI_ARBIT_EN	0x00000400
-#define PSR_NEW_MODE_EN		0x00000020     /* PPC405GPr only */
+#define PSR_PCI_ARBIT_EN    0x00000400
+#define PSR_NEW_MODE_EN     0x00000020     /* PPC405GPr only */
 
 #ifndef CONFIG_IOP480
 /*
@@ -548,201 +548,201 @@
  * Memory Access Layer
  ******************************************************************************/
 #if defined(CONFIG_405EZ)
-#define	MAL_DCR_BASE	0x380
-#define	malmcr		(MAL_DCR_BASE+0x00)	/* MAL Config reg	      */
-#define	malesr		(MAL_DCR_BASE+0x01)	/* Err Status reg (Read/Clear)*/
-#define	malier		(MAL_DCR_BASE+0x02)	/* Interrupt enable reg	      */
-#define	maldbr		(MAL_DCR_BASE+0x03)	/* Mal Debug reg (Read only)  */
-#define	maltxcasr	(MAL_DCR_BASE+0x04)	/* TX Channel active reg (set)*/
-#define	maltxcarr	(MAL_DCR_BASE+0x05)	/* TX Channel active reg (Reset)     */
-#define	maltxeobisr	(MAL_DCR_BASE+0x06)	/* TX End of buffer int status reg   */
-#define	maltxdeir	(MAL_DCR_BASE+0x07)	/* TX Descr. Error Int reg    */
-/*				      0x08-0x0F	   Reserved		      */
-#define	malrxcasr	(MAL_DCR_BASE+0x10)	/* RX Channel active reg (set)*/
-#define	malrxcarr	(MAL_DCR_BASE+0x11)	/* RX Channel active reg (Reset)     */
-#define	malrxeobisr	(MAL_DCR_BASE+0x12)	/* RX End of buffer int status reg   */
-#define	malrxdeir	(MAL_DCR_BASE+0x13)	/* RX Descr. Error Int reg  */
-/*				      0x14-0x1F	   Reserved		    */
-#define	maltxctp0r	(MAL_DCR_BASE+0x20)  /* TX 0 Channel table ptr reg  */
-#define	maltxctp1r	(MAL_DCR_BASE+0x21)  /* TX 1 Channel table ptr reg  */
-#define	maltxctp2r	(MAL_DCR_BASE+0x22)  /* TX 2 Channel table ptr reg  */
-#define	maltxctp3r	(MAL_DCR_BASE+0x23)  /* TX 3 Channel table ptr reg  */
-#define	maltxctp4r	(MAL_DCR_BASE+0x24)  /* TX 4 Channel table ptr reg  */
-#define	maltxctp5r	(MAL_DCR_BASE+0x25)  /* TX 5 Channel table ptr reg  */
-#define	maltxctp6r	(MAL_DCR_BASE+0x26)  /* TX 6 Channel table ptr reg  */
-#define	maltxctp7r	(MAL_DCR_BASE+0x27)  /* TX 7 Channel table ptr reg  */
-#define	maltxctp8r	(MAL_DCR_BASE+0x28)  /* TX 8 Channel table ptr reg  */
-#define	maltxctp9r	(MAL_DCR_BASE+0x29)  /* TX 9 Channel table ptr reg  */
-#define	maltxctp10r	(MAL_DCR_BASE+0x2A)  /* TX 10 Channel table ptr reg */
-#define	maltxctp11r	(MAL_DCR_BASE+0x2B)  /* TX 11 Channel table ptr reg */
-#define	maltxctp12r	(MAL_DCR_BASE+0x2C)  /* TX 12 Channel table ptr reg */
-#define	maltxctp13r	(MAL_DCR_BASE+0x2D)  /* TX 13 Channel table ptr reg */
-#define	maltxctp14r	(MAL_DCR_BASE+0x2E)  /* TX 14 Channel table ptr reg */
-#define	maltxctp15r	(MAL_DCR_BASE+0x2F)  /* TX 15 Channel table ptr reg */
-#define	maltxctp16r	(MAL_DCR_BASE+0x30)  /* TX 16 Channel table ptr reg */
-#define	maltxctp17r	(MAL_DCR_BASE+0x31)  /* TX 17 Channel table ptr reg */
-#define	maltxctp18r	(MAL_DCR_BASE+0x32)  /* TX 18 Channel table ptr reg */
-#define	maltxctp19r	(MAL_DCR_BASE+0x33)  /* TX 19 Channel table ptr reg */
-#define	maltxctp20r	(MAL_DCR_BASE+0x34)  /* TX 20 Channel table ptr reg */
-#define	maltxctp21r	(MAL_DCR_BASE+0x35)  /* TX 21 Channel table ptr reg */
-#define	maltxctp22r	(MAL_DCR_BASE+0x36)  /* TX 22 Channel table ptr reg */
-#define	maltxctp23r	(MAL_DCR_BASE+0x37)  /* TX 23 Channel table ptr reg */
-#define	maltxctp24r	(MAL_DCR_BASE+0x38)  /* TX 24 Channel table ptr reg */
-#define	maltxctp25r	(MAL_DCR_BASE+0x39)  /* TX 25 Channel table ptr reg */
-#define	maltxctp26r	(MAL_DCR_BASE+0x3A)  /* TX 26 Channel table ptr reg */
-#define	maltxctp27r	(MAL_DCR_BASE+0x3B)  /* TX 27 Channel table ptr reg */
-#define	maltxctp28r	(MAL_DCR_BASE+0x3C)  /* TX 28 Channel table ptr reg */
-#define	maltxctp29r	(MAL_DCR_BASE+0x3D)  /* TX 29 Channel table ptr reg */
-#define	maltxctp30r	(MAL_DCR_BASE+0x3E)  /* TX 30 Channel table ptr reg */
-#define	maltxctp31r	(MAL_DCR_BASE+0x3F)  /* TX 31 Channel table ptr reg */
-#define	malrxctp0r	(MAL_DCR_BASE+0x40)  /* RX 0 Channel table ptr reg  */
-#define	malrxctp1r	(MAL_DCR_BASE+0x41)  /* RX 1 Channel table ptr reg  */
-#define	malrxctp2r	(MAL_DCR_BASE+0x42)  /* RX 2 Channel table ptr reg  */
-#define	malrxctp3r	(MAL_DCR_BASE+0x43)  /* RX 3 Channel table ptr reg  */
-#define	malrxctp4r	(MAL_DCR_BASE+0x44)  /* RX 4 Channel table ptr reg  */
-#define	malrxctp5r	(MAL_DCR_BASE+0x45)  /* RX 5 Channel table ptr reg  */
-#define	malrxctp6r	(MAL_DCR_BASE+0x46)  /* RX 6 Channel table ptr reg  */
-#define	malrxctp7r	(MAL_DCR_BASE+0x47)  /* RX 7 Channel table ptr reg  */
-#define	malrxctp8r	(MAL_DCR_BASE+0x48)  /* RX 8 Channel table ptr reg  */
-#define	malrxctp9r	(MAL_DCR_BASE+0x49)  /* RX 9 Channel table ptr reg  */
-#define	malrxctp10r	(MAL_DCR_BASE+0x4A)  /* RX 10 Channel table ptr reg */
-#define	malrxctp11r	(MAL_DCR_BASE+0x4B)  /* RX 11 Channel table ptr reg */
-#define	malrxctp12r	(MAL_DCR_BASE+0x4C)  /* RX 12 Channel table ptr reg */
-#define	malrxctp13r	(MAL_DCR_BASE+0x4D)  /* RX 13 Channel table ptr reg */
-#define	malrxctp14r	(MAL_DCR_BASE+0x4E)  /* RX 14 Channel table ptr reg */
-#define	malrxctp15r	(MAL_DCR_BASE+0x4F)  /* RX 15 Channel table ptr reg */
-#define	malrxctp16r	(MAL_DCR_BASE+0x50)  /* RX 16 Channel table ptr reg */
-#define	malrxctp17r	(MAL_DCR_BASE+0x51)  /* RX 17 Channel table ptr reg */
-#define	malrxctp18r	(MAL_DCR_BASE+0x52)  /* RX 18 Channel table ptr reg */
-#define	malrxctp19r	(MAL_DCR_BASE+0x53)  /* RX 19 Channel table ptr reg */
-#define	malrxctp20r	(MAL_DCR_BASE+0x54)  /* RX 20 Channel table ptr reg */
-#define	malrxctp21r	(MAL_DCR_BASE+0x55)  /* RX 21 Channel table ptr reg */
-#define	malrxctp22r	(MAL_DCR_BASE+0x56)  /* RX 22 Channel table ptr reg */
-#define	malrxctp23r	(MAL_DCR_BASE+0x57)  /* RX 23 Channel table ptr reg */
-#define	malrxctp24r	(MAL_DCR_BASE+0x58)  /* RX 24 Channel table ptr reg */
-#define	malrxctp25r	(MAL_DCR_BASE+0x59)  /* RX 25 Channel table ptr reg */
-#define	malrxctp26r	(MAL_DCR_BASE+0x5A)  /* RX 26 Channel table ptr reg */
-#define	malrxctp27r	(MAL_DCR_BASE+0x5B)  /* RX 27 Channel table ptr reg */
-#define	malrxctp28r	(MAL_DCR_BASE+0x5C)  /* RX 28 Channel table ptr reg */
-#define	malrxctp29r	(MAL_DCR_BASE+0x5D)  /* RX 29 Channel table ptr reg */
-#define	malrxctp30r	(MAL_DCR_BASE+0x5E)  /* RX 30 Channel table ptr reg */
-#define	malrxctp31r	(MAL_DCR_BASE+0x5F)  /* RX 31 Channel table ptr reg */
-#define	malrcbs0	(MAL_DCR_BASE+0x60)  /* RX 0 Channel buffer size reg */
-#define	malrcbs1	(MAL_DCR_BASE+0x61)  /* RX 1 Channel buffer size reg */
-#define	malrcbs2	(MAL_DCR_BASE+0x62)  /* RX 2 Channel buffer size reg */
-#define	malrcbs3	(MAL_DCR_BASE+0x63)  /* RX 3 Channel buffer size reg */
-#define	malrcbs4	(MAL_DCR_BASE+0x64)  /* RX 4 Channel buffer size reg */
-#define	malrcbs5	(MAL_DCR_BASE+0x65)  /* RX 5 Channel buffer size reg */
-#define	malrcbs6	(MAL_DCR_BASE+0x66)  /* RX 6 Channel buffer size reg */
-#define	malrcbs7	(MAL_DCR_BASE+0x67)  /* RX 7 Channel buffer size reg */
-#define	malrcbs8	(MAL_DCR_BASE+0x68)  /* RX 8 Channel buffer size reg */
-#define	malrcbs9	(MAL_DCR_BASE+0x69)  /* RX 9 Channel buffer size reg */
-#define	malrcbs10	(MAL_DCR_BASE+0x6A)  /* RX 10 Channel buffer size reg */
-#define	malrcbs11	(MAL_DCR_BASE+0x6B)  /* RX 11 Channel buffer size reg */
-#define	malrcbs12	(MAL_DCR_BASE+0x6C)  /* RX 12 Channel buffer size reg */
-#define	malrcbs13	(MAL_DCR_BASE+0x6D)  /* RX 13 Channel buffer size reg */
-#define	malrcbs14	(MAL_DCR_BASE+0x6E)  /* RX 14 Channel buffer size reg */
-#define	malrcbs15	(MAL_DCR_BASE+0x6F)  /* RX 15 Channel buffer size reg */
-#define	malrcbs16	(MAL_DCR_BASE+0x70)  /* RX 16 Channel buffer size reg */
-#define	malrcbs17	(MAL_DCR_BASE+0x71)  /* RX 17 Channel buffer size reg */
-#define	malrcbs18	(MAL_DCR_BASE+0x72)  /* RX 18 Channel buffer size reg */
-#define	malrcbs19	(MAL_DCR_BASE+0x73)  /* RX 19 Channel buffer size reg */
-#define	malrcbs20	(MAL_DCR_BASE+0x74)  /* RX 20 Channel buffer size reg */
-#define	malrcbs21	(MAL_DCR_BASE+0x75)  /* RX 21 Channel buffer size reg */
-#define	malrcbs22	(MAL_DCR_BASE+0x76)  /* RX 22 Channel buffer size reg */
-#define	malrcbs23	(MAL_DCR_BASE+0x77)  /* RX 23 Channel buffer size reg */
-#define	malrcbs24	(MAL_DCR_BASE+0x78)  /* RX 24 Channel buffer size reg */
-#define	malrcbs25	(MAL_DCR_BASE+0x79)  /* RX 25 Channel buffer size reg */
-#define	malrcbs26	(MAL_DCR_BASE+0x7A)  /* RX 26 Channel buffer size reg */
-#define	malrcbs27	(MAL_DCR_BASE+0x7B)  /* RX 27 Channel buffer size reg */
-#define	malrcbs28	(MAL_DCR_BASE+0x7C)  /* RX 28 Channel buffer size reg */
-#define	malrcbs29	(MAL_DCR_BASE+0x7D)  /* RX 29 Channel buffer size reg */
-#define	malrcbs30	(MAL_DCR_BASE+0x7E)  /* RX 30 Channel buffer size reg */
-#define	malrcbs31	(MAL_DCR_BASE+0x7F)  /* RX 31 Channel buffer size reg */
+#define MAL_DCR_BASE    0x380
+#define malmcr      (MAL_DCR_BASE+0x00) /* MAL Config reg         */
+#define malesr      (MAL_DCR_BASE+0x01) /* Err Status reg (Read/Clear)*/
+#define malier      (MAL_DCR_BASE+0x02) /* Interrupt enable reg       */
+#define maldbr      (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only)  */
+#define maltxcasr   (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)*/
+#define maltxcarr   (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset)     */
+#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg   */
+#define maltxdeir   (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg    */
+/*                    0x08-0x0F    Reserved           */
+#define malrxcasr   (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)*/
+#define malrxcarr   (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset)     */
+#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg   */
+#define malrxdeir   (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg  */
+/*                    0x14-0x1F    Reserved         */
+#define maltxctp0r  (MAL_DCR_BASE+0x20)  /* TX 0 Channel table ptr reg  */
+#define maltxctp1r  (MAL_DCR_BASE+0x21)  /* TX 1 Channel table ptr reg  */
+#define maltxctp2r  (MAL_DCR_BASE+0x22)  /* TX 2 Channel table ptr reg  */
+#define maltxctp3r  (MAL_DCR_BASE+0x23)  /* TX 3 Channel table ptr reg  */
+#define maltxctp4r  (MAL_DCR_BASE+0x24)  /* TX 4 Channel table ptr reg  */
+#define maltxctp5r  (MAL_DCR_BASE+0x25)  /* TX 5 Channel table ptr reg  */
+#define maltxctp6r  (MAL_DCR_BASE+0x26)  /* TX 6 Channel table ptr reg  */
+#define maltxctp7r  (MAL_DCR_BASE+0x27)  /* TX 7 Channel table ptr reg  */
+#define maltxctp8r  (MAL_DCR_BASE+0x28)  /* TX 8 Channel table ptr reg  */
+#define maltxctp9r  (MAL_DCR_BASE+0x29)  /* TX 9 Channel table ptr reg  */
+#define maltxctp10r (MAL_DCR_BASE+0x2A)  /* TX 10 Channel table ptr reg */
+#define maltxctp11r (MAL_DCR_BASE+0x2B)  /* TX 11 Channel table ptr reg */
+#define maltxctp12r (MAL_DCR_BASE+0x2C)  /* TX 12 Channel table ptr reg */
+#define maltxctp13r (MAL_DCR_BASE+0x2D)  /* TX 13 Channel table ptr reg */
+#define maltxctp14r (MAL_DCR_BASE+0x2E)  /* TX 14 Channel table ptr reg */
+#define maltxctp15r (MAL_DCR_BASE+0x2F)  /* TX 15 Channel table ptr reg */
+#define maltxctp16r (MAL_DCR_BASE+0x30)  /* TX 16 Channel table ptr reg */
+#define maltxctp17r (MAL_DCR_BASE+0x31)  /* TX 17 Channel table ptr reg */
+#define maltxctp18r (MAL_DCR_BASE+0x32)  /* TX 18 Channel table ptr reg */
+#define maltxctp19r (MAL_DCR_BASE+0x33)  /* TX 19 Channel table ptr reg */
+#define maltxctp20r (MAL_DCR_BASE+0x34)  /* TX 20 Channel table ptr reg */
+#define maltxctp21r (MAL_DCR_BASE+0x35)  /* TX 21 Channel table ptr reg */
+#define maltxctp22r (MAL_DCR_BASE+0x36)  /* TX 22 Channel table ptr reg */
+#define maltxctp23r (MAL_DCR_BASE+0x37)  /* TX 23 Channel table ptr reg */
+#define maltxctp24r (MAL_DCR_BASE+0x38)  /* TX 24 Channel table ptr reg */
+#define maltxctp25r (MAL_DCR_BASE+0x39)  /* TX 25 Channel table ptr reg */
+#define maltxctp26r (MAL_DCR_BASE+0x3A)  /* TX 26 Channel table ptr reg */
+#define maltxctp27r (MAL_DCR_BASE+0x3B)  /* TX 27 Channel table ptr reg */
+#define maltxctp28r (MAL_DCR_BASE+0x3C)  /* TX 28 Channel table ptr reg */
+#define maltxctp29r (MAL_DCR_BASE+0x3D)  /* TX 29 Channel table ptr reg */
+#define maltxctp30r (MAL_DCR_BASE+0x3E)  /* TX 30 Channel table ptr reg */
+#define maltxctp31r (MAL_DCR_BASE+0x3F)  /* TX 31 Channel table ptr reg */
+#define malrxctp0r  (MAL_DCR_BASE+0x40)  /* RX 0 Channel table ptr reg  */
+#define malrxctp1r  (MAL_DCR_BASE+0x41)  /* RX 1 Channel table ptr reg  */
+#define malrxctp2r  (MAL_DCR_BASE+0x42)  /* RX 2 Channel table ptr reg  */
+#define malrxctp3r  (MAL_DCR_BASE+0x43)  /* RX 3 Channel table ptr reg  */
+#define malrxctp4r  (MAL_DCR_BASE+0x44)  /* RX 4 Channel table ptr reg  */
+#define malrxctp5r  (MAL_DCR_BASE+0x45)  /* RX 5 Channel table ptr reg  */
+#define malrxctp6r  (MAL_DCR_BASE+0x46)  /* RX 6 Channel table ptr reg  */
+#define malrxctp7r  (MAL_DCR_BASE+0x47)  /* RX 7 Channel table ptr reg  */
+#define malrxctp8r  (MAL_DCR_BASE+0x48)  /* RX 8 Channel table ptr reg  */
+#define malrxctp9r  (MAL_DCR_BASE+0x49)  /* RX 9 Channel table ptr reg  */
+#define malrxctp10r (MAL_DCR_BASE+0x4A)  /* RX 10 Channel table ptr reg */
+#define malrxctp11r (MAL_DCR_BASE+0x4B)  /* RX 11 Channel table ptr reg */
+#define malrxctp12r (MAL_DCR_BASE+0x4C)  /* RX 12 Channel table ptr reg */
+#define malrxctp13r (MAL_DCR_BASE+0x4D)  /* RX 13 Channel table ptr reg */
+#define malrxctp14r (MAL_DCR_BASE+0x4E)  /* RX 14 Channel table ptr reg */
+#define malrxctp15r (MAL_DCR_BASE+0x4F)  /* RX 15 Channel table ptr reg */
+#define malrxctp16r (MAL_DCR_BASE+0x50)  /* RX 16 Channel table ptr reg */
+#define malrxctp17r (MAL_DCR_BASE+0x51)  /* RX 17 Channel table ptr reg */
+#define malrxctp18r (MAL_DCR_BASE+0x52)  /* RX 18 Channel table ptr reg */
+#define malrxctp19r (MAL_DCR_BASE+0x53)  /* RX 19 Channel table ptr reg */
+#define malrxctp20r (MAL_DCR_BASE+0x54)  /* RX 20 Channel table ptr reg */
+#define malrxctp21r (MAL_DCR_BASE+0x55)  /* RX 21 Channel table ptr reg */
+#define malrxctp22r (MAL_DCR_BASE+0x56)  /* RX 22 Channel table ptr reg */
+#define malrxctp23r (MAL_DCR_BASE+0x57)  /* RX 23 Channel table ptr reg */
+#define malrxctp24r (MAL_DCR_BASE+0x58)  /* RX 24 Channel table ptr reg */
+#define malrxctp25r (MAL_DCR_BASE+0x59)  /* RX 25 Channel table ptr reg */
+#define malrxctp26r (MAL_DCR_BASE+0x5A)  /* RX 26 Channel table ptr reg */
+#define malrxctp27r (MAL_DCR_BASE+0x5B)  /* RX 27 Channel table ptr reg */
+#define malrxctp28r (MAL_DCR_BASE+0x5C)  /* RX 28 Channel table ptr reg */
+#define malrxctp29r (MAL_DCR_BASE+0x5D)  /* RX 29 Channel table ptr reg */
+#define malrxctp30r (MAL_DCR_BASE+0x5E)  /* RX 30 Channel table ptr reg */
+#define malrxctp31r (MAL_DCR_BASE+0x5F)  /* RX 31 Channel table ptr reg */
+#define malrcbs0    (MAL_DCR_BASE+0x60)  /* RX 0 Channel buffer size reg */
+#define malrcbs1    (MAL_DCR_BASE+0x61)  /* RX 1 Channel buffer size reg */
+#define malrcbs2    (MAL_DCR_BASE+0x62)  /* RX 2 Channel buffer size reg */
+#define malrcbs3    (MAL_DCR_BASE+0x63)  /* RX 3 Channel buffer size reg */
+#define malrcbs4    (MAL_DCR_BASE+0x64)  /* RX 4 Channel buffer size reg */
+#define malrcbs5    (MAL_DCR_BASE+0x65)  /* RX 5 Channel buffer size reg */
+#define malrcbs6    (MAL_DCR_BASE+0x66)  /* RX 6 Channel buffer size reg */
+#define malrcbs7    (MAL_DCR_BASE+0x67)  /* RX 7 Channel buffer size reg */
+#define malrcbs8    (MAL_DCR_BASE+0x68)  /* RX 8 Channel buffer size reg */
+#define malrcbs9    (MAL_DCR_BASE+0x69)  /* RX 9 Channel buffer size reg */
+#define malrcbs10   (MAL_DCR_BASE+0x6A)  /* RX 10 Channel buffer size reg */
+#define malrcbs11   (MAL_DCR_BASE+0x6B)  /* RX 11 Channel buffer size reg */
+#define malrcbs12   (MAL_DCR_BASE+0x6C)  /* RX 12 Channel buffer size reg */
+#define malrcbs13   (MAL_DCR_BASE+0x6D)  /* RX 13 Channel buffer size reg */
+#define malrcbs14   (MAL_DCR_BASE+0x6E)  /* RX 14 Channel buffer size reg */
+#define malrcbs15   (MAL_DCR_BASE+0x6F)  /* RX 15 Channel buffer size reg */
+#define malrcbs16   (MAL_DCR_BASE+0x70)  /* RX 16 Channel buffer size reg */
+#define malrcbs17   (MAL_DCR_BASE+0x71)  /* RX 17 Channel buffer size reg */
+#define malrcbs18   (MAL_DCR_BASE+0x72)  /* RX 18 Channel buffer size reg */
+#define malrcbs19   (MAL_DCR_BASE+0x73)  /* RX 19 Channel buffer size reg */
+#define malrcbs20   (MAL_DCR_BASE+0x74)  /* RX 20 Channel buffer size reg */
+#define malrcbs21   (MAL_DCR_BASE+0x75)  /* RX 21 Channel buffer size reg */
+#define malrcbs22   (MAL_DCR_BASE+0x76)  /* RX 22 Channel buffer size reg */
+#define malrcbs23   (MAL_DCR_BASE+0x77)  /* RX 23 Channel buffer size reg */
+#define malrcbs24   (MAL_DCR_BASE+0x78)  /* RX 24 Channel buffer size reg */
+#define malrcbs25   (MAL_DCR_BASE+0x79)  /* RX 25 Channel buffer size reg */
+#define malrcbs26   (MAL_DCR_BASE+0x7A)  /* RX 26 Channel buffer size reg */
+#define malrcbs27   (MAL_DCR_BASE+0x7B)  /* RX 27 Channel buffer size reg */
+#define malrcbs28   (MAL_DCR_BASE+0x7C)  /* RX 28 Channel buffer size reg */
+#define malrcbs29   (MAL_DCR_BASE+0x7D)  /* RX 29 Channel buffer size reg */
+#define malrcbs30   (MAL_DCR_BASE+0x7E)  /* RX 30 Channel buffer size reg */
+#define malrcbs31   (MAL_DCR_BASE+0x7F)  /* RX 31 Channel buffer size reg */
 
 #else /* !defined(CONFIG_405EZ) */
 
 #define MAL_DCR_BASE 0x180
-#define malmcr	(MAL_DCR_BASE+0x00)  /* MAL Config reg			     */
-#define malesr	(MAL_DCR_BASE+0x01)  /* Error Status reg (Read/Clear)	     */
-#define malier	(MAL_DCR_BASE+0x02)  /* Interrupt enable reg		     */
-#define maldbr	(MAL_DCR_BASE+0x03)  /* Mal Debug reg (Read only)	     */
-#define maltxcasr  (MAL_DCR_BASE+0x04)	/* TX Channel active reg (set)	     */
-#define maltxcarr  (MAL_DCR_BASE+0x05)	/* TX Channel active reg (Reset)     */
+#define malmcr  (MAL_DCR_BASE+0x00)  /* MAL Config reg               */
+#define malesr  (MAL_DCR_BASE+0x01)  /* Error Status reg (Read/Clear)        */
+#define malier  (MAL_DCR_BASE+0x02)  /* Interrupt enable reg             */
+#define maldbr  (MAL_DCR_BASE+0x03)  /* Mal Debug reg (Read only)        */
+#define maltxcasr  (MAL_DCR_BASE+0x04)  /* TX Channel active reg (set)       */
+#define maltxcarr  (MAL_DCR_BASE+0x05)  /* TX Channel active reg (Reset)     */
 #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg   */
-#define maltxdeir  (MAL_DCR_BASE+0x07)	/* TX Descr. Error Int reg	     */
-#define malrxcasr  (MAL_DCR_BASE+0x10)	/* RX Channel active reg (set)	     */
-#define malrxcarr  (MAL_DCR_BASE+0x11)	/* RX Channel active reg (Reset)     */
+#define maltxdeir  (MAL_DCR_BASE+0x07)  /* TX Descr. Error Int reg       */
+#define malrxcasr  (MAL_DCR_BASE+0x10)  /* RX Channel active reg (set)       */
+#define malrxcarr  (MAL_DCR_BASE+0x11)  /* RX Channel active reg (Reset)     */
 #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg   */
-#define malrxdeir  (MAL_DCR_BASE+0x13)	/* RX Descr. Error Int reg	     */
-#define maltxctp0r (MAL_DCR_BASE+0x20)	/* TX 0 Channel table pointer reg    */
-#define maltxctp1r (MAL_DCR_BASE+0x21)	/* TX 1 Channel table pointer reg    */
-#define maltxctp2r (MAL_DCR_BASE+0x22)	/* TX 2 Channel table pointer reg    */
-#define malrxctp0r (MAL_DCR_BASE+0x40)	/* RX 0 Channel table pointer reg    */
-#define malrxctp1r (MAL_DCR_BASE+0x41)	/* RX 1 Channel table pointer reg    */
-#define malrcbs0   (MAL_DCR_BASE+0x60)	/* RX 0 Channel buffer size reg      */
-#define malrcbs1   (MAL_DCR_BASE+0x61)	/* RX 1 Channel buffer size reg      */
+#define malrxdeir  (MAL_DCR_BASE+0x13)  /* RX Descr. Error Int reg       */
+#define maltxctp0r (MAL_DCR_BASE+0x20)  /* TX 0 Channel table pointer reg    */
+#define maltxctp1r (MAL_DCR_BASE+0x21)  /* TX 1 Channel table pointer reg    */
+#define maltxctp2r (MAL_DCR_BASE+0x22)  /* TX 2 Channel table pointer reg    */
+#define malrxctp0r (MAL_DCR_BASE+0x40)  /* RX 0 Channel table pointer reg    */
+#define malrxctp1r (MAL_DCR_BASE+0x41)  /* RX 1 Channel table pointer reg    */
+#define malrcbs0   (MAL_DCR_BASE+0x60)  /* RX 0 Channel buffer size reg      */
+#define malrcbs1   (MAL_DCR_BASE+0x61)  /* RX 1 Channel buffer size reg      */
 #endif /* defined(CONFIG_405EZ) */
 
 /*-----------------------------------------------------------------------------
 | IIC Register Offsets
 '----------------------------------------------------------------------------*/
-#define    IICMDBUF	    0x00
-#define    IICSDBUF	    0x02
-#define    IICLMADR	    0x04
-#define    IICHMADR	    0x05
-#define    IICCNTL	    0x06
-#define    IICMDCNTL	    0x07
-#define    IICSTS	    0x08
-#define    IICEXTSTS	    0x09
-#define    IICLSADR	    0x0A
-#define    IICHSADR	    0x0B
-#define    IICCLKDIV	    0x0C
-#define    IICINTRMSK	    0x0D
-#define    IICXFRCNT	    0x0E
-#define    IICXTCNTLSS	    0x0F
+#define    IICMDBUF     0x00
+#define    IICSDBUF     0x02
+#define    IICLMADR     0x04
+#define    IICHMADR     0x05
+#define    IICCNTL      0x06
+#define    IICMDCNTL        0x07
+#define    IICSTS       0x08
+#define    IICEXTSTS        0x09
+#define    IICLSADR     0x0A
+#define    IICHSADR     0x0B
+#define    IICCLKDIV        0x0C
+#define    IICINTRMSK       0x0D
+#define    IICXFRCNT        0x0E
+#define    IICXTCNTLSS      0x0F
 #define    IICDIRECTCNTL    0x10
 
 /*-----------------------------------------------------------------------------
 | UART Register Offsets
 '----------------------------------------------------------------------------*/
-#define		DATA_REG	0x00
-#define		DL_LSB		0x00
-#define		DL_MSB		0x01
-#define		INT_ENABLE	0x01
-#define		FIFO_CONTROL	0x02
-#define		LINE_CONTROL	0x03
-#define		MODEM_CONTROL	0x04
-#define		LINE_STATUS	0x05
-#define		MODEM_STATUS	0x06
-#define		SCRATCH		0x07
+#define     DATA_REG    0x00
+#define     DL_LSB      0x00
+#define     DL_MSB      0x01
+#define     INT_ENABLE  0x01
+#define     FIFO_CONTROL    0x02
+#define     LINE_CONTROL    0x03
+#define     MODEM_CONTROL   0x04
+#define     LINE_STATUS 0x05
+#define     MODEM_STATUS    0x06
+#define     SCRATCH     0x07
 
 /******************************************************************************
  * On Chip Memory
  ******************************************************************************/
 #if defined(CONFIG_405EZ)
 #define OCM_DCR_BASE 0x020
-#define ocmplb3cr1	(OCM_DCR_BASE+0x00)  /* OCM PLB3 Bank 1 Config Reg    */
-#define ocmplb3cr2	(OCM_DCR_BASE+0x01)  /* OCM PLB3 Bank 2 Config Reg    */
-#define ocmplb3bear	(OCM_DCR_BASE+0x02)  /* OCM PLB3 Bus Error Add Reg    */
-#define ocmplb3besr0	(OCM_DCR_BASE+0x03)  /* OCM PLB3 Bus Error Stat Reg 0 */
-#define ocmplb3besr1	(OCM_DCR_BASE+0x04)  /* OCM PLB3 Bus Error Stat Reg 1 */
-#define ocmcid		(OCM_DCR_BASE+0x05)  /* OCM Core ID		      */
-#define ocmrevid	(OCM_DCR_BASE+0x06)  /* OCM Revision ID		      */
-#define ocmplb3dpc	(OCM_DCR_BASE+0x07)  /* OCM PLB3 Data Parity Check    */
-#define ocmdscr1	(OCM_DCR_BASE+0x08)  /* OCM D-side Bank 1 Config Reg  */
-#define ocmdscr2	(OCM_DCR_BASE+0x09)  /* OCM D-side Bank 2 Config Reg  */
-#define ocmiscr1	(OCM_DCR_BASE+0x0A)  /* OCM I-side Bank 1 Config Reg  */
-#define ocmiscr2	(OCM_DCR_BASE+0x0B)  /* OCM I-side Bank 2 Config Reg  */
-#define ocmdsisdpc	(OCM_DCR_BASE+0x0C)  /* OCM D-side/I-side Data Par Chk*/
-#define ocmdsisbear	(OCM_DCR_BASE+0x0D)  /* OCM D-side/I-side Bus Err Addr*/
-#define ocmdsisbesr	(OCM_DCR_BASE+0x0E)  /* OCM D-side/I-side Bus Err Stat*/
+#define ocmplb3cr1  (OCM_DCR_BASE+0x00)  /* OCM PLB3 Bank 1 Config Reg    */
+#define ocmplb3cr2  (OCM_DCR_BASE+0x01)  /* OCM PLB3 Bank 2 Config Reg    */
+#define ocmplb3bear (OCM_DCR_BASE+0x02)  /* OCM PLB3 Bus Error Add Reg    */
+#define ocmplb3besr0    (OCM_DCR_BASE+0x03)  /* OCM PLB3 Bus Error Stat Reg 0 */
+#define ocmplb3besr1    (OCM_DCR_BASE+0x04)  /* OCM PLB3 Bus Error Stat Reg 1 */
+#define ocmcid      (OCM_DCR_BASE+0x05)  /* OCM Core ID           */
+#define ocmrevid    (OCM_DCR_BASE+0x06)  /* OCM Revision ID           */
+#define ocmplb3dpc  (OCM_DCR_BASE+0x07)  /* OCM PLB3 Data Parity Check    */
+#define ocmdscr1    (OCM_DCR_BASE+0x08)  /* OCM D-side Bank 1 Config Reg  */
+#define ocmdscr2    (OCM_DCR_BASE+0x09)  /* OCM D-side Bank 2 Config Reg  */
+#define ocmiscr1    (OCM_DCR_BASE+0x0A)  /* OCM I-side Bank 1 Config Reg  */
+#define ocmiscr2    (OCM_DCR_BASE+0x0B)  /* OCM I-side Bank 2 Config Reg  */
+#define ocmdsisdpc  (OCM_DCR_BASE+0x0C)  /* OCM D-side/I-side Data Par Chk*/
+#define ocmdsisbear (OCM_DCR_BASE+0x0D)  /* OCM D-side/I-side Bus Err Addr*/
+#define ocmdsisbesr (OCM_DCR_BASE+0x0E)  /* OCM D-side/I-side Bus Err Stat*/
 #else
 #define OCM_DCR_BASE 0x018
-#define ocmisarc   (OCM_DCR_BASE+0x00)	/* OCM I-side address compare reg    */
-#define ocmiscntl  (OCM_DCR_BASE+0x01)	/* OCM I-side control reg	     */
-#define ocmdsarc   (OCM_DCR_BASE+0x02)	/* OCM D-side address compare reg    */
-#define ocmdscntl  (OCM_DCR_BASE+0x03)	/* OCM D-side control reg	     */
+#define ocmisarc   (OCM_DCR_BASE+0x00)  /* OCM I-side address compare reg    */
+#define ocmiscntl  (OCM_DCR_BASE+0x01)  /* OCM I-side control reg        */
+#define ocmdsarc   (OCM_DCR_BASE+0x02)  /* OCM D-side address compare reg    */
+#define ocmdscntl  (OCM_DCR_BASE+0x03)  /* OCM D-side control reg        */
 #endif /* CONFIG_405EZ */
 
 /******************************************************************************
@@ -751,154 +751,154 @@
 #if defined(CONFIG_405EZ)
 /* Only the 405EZ has 2 GPIOs */
 #define GPIO_BASE  0xEF600700
-#define GPIO0_OR		(GPIO_BASE+0x0)
-#define GPIO0_TCR		(GPIO_BASE+0x4)
-#define GPIO0_OSRL		(GPIO_BASE+0x8)
-#define GPIO0_OSRH		(GPIO_BASE+0xC)
-#define GPIO0_TSRL		(GPIO_BASE+0x10)
-#define GPIO0_TSRH		(GPIO_BASE+0x14)
-#define GPIO0_ODR		(GPIO_BASE+0x18)
-#define GPIO0_IR		(GPIO_BASE+0x1C)
-#define GPIO0_RR1		(GPIO_BASE+0x20)
-#define GPIO0_RR2		(GPIO_BASE+0x24)
-#define GPIO0_RR3		(GPIO_BASE+0x28)
-#define GPIO0_ISR1L		(GPIO_BASE+0x30)
-#define GPIO0_ISR1H		(GPIO_BASE+0x34)
-#define GPIO0_ISR2L		(GPIO_BASE+0x38)
-#define GPIO0_ISR2H		(GPIO_BASE+0x3C)
-#define GPIO0_ISR3L		(GPIO_BASE+0x40)
-#define GPIO0_ISR3H		(GPIO_BASE+0x44)
+#define GPIO0_OR        (GPIO_BASE+0x0)
+#define GPIO0_TCR       (GPIO_BASE+0x4)
+#define GPIO0_OSRL      (GPIO_BASE+0x8)
+#define GPIO0_OSRH      (GPIO_BASE+0xC)
+#define GPIO0_TSRL      (GPIO_BASE+0x10)
+#define GPIO0_TSRH      (GPIO_BASE+0x14)
+#define GPIO0_ODR       (GPIO_BASE+0x18)
+#define GPIO0_IR        (GPIO_BASE+0x1C)
+#define GPIO0_RR1       (GPIO_BASE+0x20)
+#define GPIO0_RR2       (GPIO_BASE+0x24)
+#define GPIO0_RR3       (GPIO_BASE+0x28)
+#define GPIO0_ISR1L     (GPIO_BASE+0x30)
+#define GPIO0_ISR1H     (GPIO_BASE+0x34)
+#define GPIO0_ISR2L     (GPIO_BASE+0x38)
+#define GPIO0_ISR2H     (GPIO_BASE+0x3C)
+#define GPIO0_ISR3L     (GPIO_BASE+0x40)
+#define GPIO0_ISR3H     (GPIO_BASE+0x44)
 
 #define GPIO1_BASE  0xEF600800
-#define GPIO1_OR		(GPIO1_BASE+0x0)
-#define GPIO1_TCR		(GPIO1_BASE+0x4)
-#define GPIO1_OSRL		(GPIO1_BASE+0x8)
-#define GPIO1_OSRH		(GPIO1_BASE+0xC)
-#define GPIO1_TSRL		(GPIO1_BASE+0x10)
-#define GPIO1_TSRH		(GPIO1_BASE+0x14)
-#define GPIO1_ODR		(GPIO1_BASE+0x18)
-#define GPIO1_IR		(GPIO1_BASE+0x1C)
-#define GPIO1_RR1		(GPIO1_BASE+0x20)
-#define GPIO1_RR2		(GPIO1_BASE+0x24)
-#define GPIO1_RR3		(GPIO1_BASE+0x28)
-#define GPIO1_ISR1L		(GPIO1_BASE+0x30)
-#define GPIO1_ISR1H		(GPIO1_BASE+0x34)
-#define GPIO1_ISR2L		(GPIO1_BASE+0x38)
-#define GPIO1_ISR2H		(GPIO1_BASE+0x3C)
-#define GPIO1_ISR3L		(GPIO1_BASE+0x40)
-#define GPIO1_ISR3H		(GPIO1_BASE+0x44)
+#define GPIO1_OR        (GPIO1_BASE+0x0)
+#define GPIO1_TCR       (GPIO1_BASE+0x4)
+#define GPIO1_OSRL      (GPIO1_BASE+0x8)
+#define GPIO1_OSRH      (GPIO1_BASE+0xC)
+#define GPIO1_TSRL      (GPIO1_BASE+0x10)
+#define GPIO1_TSRH      (GPIO1_BASE+0x14)
+#define GPIO1_ODR       (GPIO1_BASE+0x18)
+#define GPIO1_IR        (GPIO1_BASE+0x1C)
+#define GPIO1_RR1       (GPIO1_BASE+0x20)
+#define GPIO1_RR2       (GPIO1_BASE+0x24)
+#define GPIO1_RR3       (GPIO1_BASE+0x28)
+#define GPIO1_ISR1L     (GPIO1_BASE+0x30)
+#define GPIO1_ISR1H     (GPIO1_BASE+0x34)
+#define GPIO1_ISR2L     (GPIO1_BASE+0x38)
+#define GPIO1_ISR2H     (GPIO1_BASE+0x3C)
+#define GPIO1_ISR3L     (GPIO1_BASE+0x40)
+#define GPIO1_ISR3H     (GPIO1_BASE+0x44)
 
 #elif defined(CONFIG_405EX)
 #define GPIO_BASE  0xEF600800
-#define GPIO0_OR	       (GPIO_BASE+0x0)
-#define GPIO0_TCR	       (GPIO_BASE+0x4)
-#define GPIO0_OSRL	       (GPIO_BASE+0x8)
-#define GPIO0_OSRH	       (GPIO_BASE+0xC)
-#define GPIO0_TSRL	       (GPIO_BASE+0x10)
-#define GPIO0_TSRH	       (GPIO_BASE+0x14)
-#define GPIO0_ODR	       (GPIO_BASE+0x18)
-#define GPIO0_IR	       (GPIO_BASE+0x1C)
-#define GPIO0_RR1	       (GPIO_BASE+0x20)
-#define GPIO0_RR2	       (GPIO_BASE+0x24)
-#define GPIO0_ISR1L	       (GPIO_BASE+0x30)
-#define GPIO0_ISR1H	       (GPIO_BASE+0x34)
-#define GPIO0_ISR2L	       (GPIO_BASE+0x38)
-#define GPIO0_ISR2H	       (GPIO_BASE+0x3C)
-#define GPIO0_ISR3L	       (GPIO_BASE+0x40)
-#define GPIO0_ISR3H	       (GPIO_BASE+0x44)
+#define GPIO0_OR           (GPIO_BASE+0x0)
+#define GPIO0_TCR          (GPIO_BASE+0x4)
+#define GPIO0_OSRL         (GPIO_BASE+0x8)
+#define GPIO0_OSRH         (GPIO_BASE+0xC)
+#define GPIO0_TSRL         (GPIO_BASE+0x10)
+#define GPIO0_TSRH         (GPIO_BASE+0x14)
+#define GPIO0_ODR          (GPIO_BASE+0x18)
+#define GPIO0_IR           (GPIO_BASE+0x1C)
+#define GPIO0_RR1          (GPIO_BASE+0x20)
+#define GPIO0_RR2          (GPIO_BASE+0x24)
+#define GPIO0_ISR1L        (GPIO_BASE+0x30)
+#define GPIO0_ISR1H        (GPIO_BASE+0x34)
+#define GPIO0_ISR2L        (GPIO_BASE+0x38)
+#define GPIO0_ISR2H        (GPIO_BASE+0x3C)
+#define GPIO0_ISR3L        (GPIO_BASE+0x40)
+#define GPIO0_ISR3H        (GPIO_BASE+0x44)
 
-#else	/* !405EZ */
+#else   /* !405EZ */
 
 #define GPIO_BASE  0xEF600700
-#define GPIO0_OR	       (GPIO_BASE+0x0)
-#define GPIO0_TCR	       (GPIO_BASE+0x4)
-#define GPIO0_OSRH	       (GPIO_BASE+0x8)
-#define GPIO0_OSRL	       (GPIO_BASE+0xC)
-#define GPIO0_TSRH	       (GPIO_BASE+0x10)
-#define GPIO0_TSRL	       (GPIO_BASE+0x14)
-#define GPIO0_ODR	       (GPIO_BASE+0x18)
-#define GPIO0_IR	       (GPIO_BASE+0x1C)
-#define GPIO0_RR1	       (GPIO_BASE+0x20)
-#define GPIO0_RR2	       (GPIO_BASE+0x24)
-#define GPIO0_ISR1H	       (GPIO_BASE+0x30)
-#define GPIO0_ISR1L	       (GPIO_BASE+0x34)
-#define GPIO0_ISR2H	       (GPIO_BASE+0x38)
-#define GPIO0_ISR2L	       (GPIO_BASE+0x3C)
+#define GPIO0_OR           (GPIO_BASE+0x0)
+#define GPIO0_TCR          (GPIO_BASE+0x4)
+#define GPIO0_OSRH         (GPIO_BASE+0x8)
+#define GPIO0_OSRL         (GPIO_BASE+0xC)
+#define GPIO0_TSRH         (GPIO_BASE+0x10)
+#define GPIO0_TSRL         (GPIO_BASE+0x14)
+#define GPIO0_ODR          (GPIO_BASE+0x18)
+#define GPIO0_IR           (GPIO_BASE+0x1C)
+#define GPIO0_RR1          (GPIO_BASE+0x20)
+#define GPIO0_RR2          (GPIO_BASE+0x24)
+#define GPIO0_ISR1H        (GPIO_BASE+0x30)
+#define GPIO0_ISR1L        (GPIO_BASE+0x34)
+#define GPIO0_ISR2H        (GPIO_BASE+0x38)
+#define GPIO0_ISR2L        (GPIO_BASE+0x3C)
 
 #endif /* CONFIG_405EZ */
 
-#define GPIO0_BASE		GPIO_BASE
+#define GPIO0_BASE      GPIO_BASE
 
 #if defined(CONFIG_405EX)
-#define SDR0_SRST		0x0200
+#define SDR0_SRST       0x0200
 
 /*
  * Software Reset Register
  */
-#define SDR0_SRST_BGO		PPC_REG_VAL(0, 1)
-#define SDR0_SRST_PLB4		PPC_REG_VAL(1, 1)
-#define SDR0_SRST_EBC		PPC_REG_VAL(2, 1)
-#define SDR0_SRST_OPB		PPC_REG_VAL(3, 1)
-#define SDR0_SRST_UART0		PPC_REG_VAL(4, 1)
-#define SDR0_SRST_UART1		PPC_REG_VAL(5, 1)
-#define SDR0_SRST_IIC0		PPC_REG_VAL(6, 1)
-#define SDR0_SRST_BGI		PPC_REG_VAL(7, 1)
-#define SDR0_SRST_GPIO		PPC_REG_VAL(8, 1)
-#define SDR0_SRST_GPT		PPC_REG_VAL(9, 1)
-#define SDR0_SRST_DMC		PPC_REG_VAL(10, 1)
-#define SDR0_SRST_RGMII		PPC_REG_VAL(11, 1)
-#define SDR0_SRST_EMAC0		PPC_REG_VAL(12, 1)
-#define SDR0_SRST_EMAC1		PPC_REG_VAL(13, 1)
-#define SDR0_SRST_CPM		PPC_REG_VAL(14, 1)
-#define SDR0_SRST_EPLL		PPC_REG_VAL(15, 1)
-#define SDR0_SRST_UIC		PPC_REG_VAL(16, 1)
-#define SDR0_SRST_UPRST		PPC_REG_VAL(17, 1)
-#define SDR0_SRST_IIC1		PPC_REG_VAL(18, 1)
-#define SDR0_SRST_SCP		PPC_REG_VAL(19, 1)
-#define SDR0_SRST_UHRST		PPC_REG_VAL(20, 1)
-#define SDR0_SRST_DMA		PPC_REG_VAL(21, 1)
-#define SDR0_SRST_DMAC		PPC_REG_VAL(22, 1)
-#define SDR0_SRST_MAL		PPC_REG_VAL(23, 1)
-#define SDR0_SRST_EBM		PPC_REG_VAL(24, 1)
-#define SDR0_SRST_GPTR		PPC_REG_VAL(25, 1)
-#define SDR0_SRST_PE0		PPC_REG_VAL(26, 1)
-#define SDR0_SRST_PE1		PPC_REG_VAL(27, 1)
-#define SDR0_SRST_CRYP		PPC_REG_VAL(28, 1)
-#define SDR0_SRST_PKP		PPC_REG_VAL(29, 1)
-#define SDR0_SRST_AHB		PPC_REG_VAL(30, 1)
-#define SDR0_SRST_NDFC		PPC_REG_VAL(31, 1)
+#define SDR0_SRST_BGO       PPC_REG_VAL(0, 1)
+#define SDR0_SRST_PLB4      PPC_REG_VAL(1, 1)
+#define SDR0_SRST_EBC       PPC_REG_VAL(2, 1)
+#define SDR0_SRST_OPB       PPC_REG_VAL(3, 1)
+#define SDR0_SRST_UART0     PPC_REG_VAL(4, 1)
+#define SDR0_SRST_UART1     PPC_REG_VAL(5, 1)
+#define SDR0_SRST_IIC0      PPC_REG_VAL(6, 1)
+#define SDR0_SRST_BGI       PPC_REG_VAL(7, 1)
+#define SDR0_SRST_GPIO      PPC_REG_VAL(8, 1)
+#define SDR0_SRST_GPT       PPC_REG_VAL(9, 1)
+#define SDR0_SRST_DMC       PPC_REG_VAL(10, 1)
+#define SDR0_SRST_RGMII     PPC_REG_VAL(11, 1)
+#define SDR0_SRST_EMAC0     PPC_REG_VAL(12, 1)
+#define SDR0_SRST_EMAC1     PPC_REG_VAL(13, 1)
+#define SDR0_SRST_CPM       PPC_REG_VAL(14, 1)
+#define SDR0_SRST_EPLL      PPC_REG_VAL(15, 1)
+#define SDR0_SRST_UIC       PPC_REG_VAL(16, 1)
+#define SDR0_SRST_UPRST     PPC_REG_VAL(17, 1)
+#define SDR0_SRST_IIC1      PPC_REG_VAL(18, 1)
+#define SDR0_SRST_SCP       PPC_REG_VAL(19, 1)
+#define SDR0_SRST_UHRST     PPC_REG_VAL(20, 1)
+#define SDR0_SRST_DMA       PPC_REG_VAL(21, 1)
+#define SDR0_SRST_DMAC      PPC_REG_VAL(22, 1)
+#define SDR0_SRST_MAL       PPC_REG_VAL(23, 1)
+#define SDR0_SRST_EBM       PPC_REG_VAL(24, 1)
+#define SDR0_SRST_GPTR      PPC_REG_VAL(25, 1)
+#define SDR0_SRST_PE0       PPC_REG_VAL(26, 1)
+#define SDR0_SRST_PE1       PPC_REG_VAL(27, 1)
+#define SDR0_SRST_CRYP      PPC_REG_VAL(28, 1)
+#define SDR0_SRST_PKP       PPC_REG_VAL(29, 1)
+#define SDR0_SRST_AHB       PPC_REG_VAL(30, 1)
+#define SDR0_SRST_NDFC      PPC_REG_VAL(31, 1)
 
-#define sdr_uart0	0x0120	/* UART0 Config */
-#define sdr_uart1	0x0121	/* UART1 Config */
-#define sdr_mfr		0x4300	/* SDR0_MFR reg */
+#define sdr_uart0   0x0120  /* UART0 Config */
+#define sdr_uart1   0x0121  /* UART1 Config */
+#define sdr_mfr     0x4300  /* SDR0_MFR reg */
 
 /* Defines for CPC0_EPRCSR register */
-#define CPC0_EPRCSR_E0NFE	   0x80000000
-#define CPC0_EPRCSR_E1NFE	   0x40000000
-#define CPC0_EPRCSR_E1RPP	   0x00000080
-#define CPC0_EPRCSR_E0RPP	   0x00000040
-#define CPC0_EPRCSR_E1ERP	   0x00000020
-#define CPC0_EPRCSR_E0ERP	   0x00000010
-#define CPC0_EPRCSR_E1PCI	   0x00000002
-#define CPC0_EPRCSR_E0PCI	   0x00000001
+#define CPC0_EPRCSR_E0NFE      0x80000000
+#define CPC0_EPRCSR_E1NFE      0x40000000
+#define CPC0_EPRCSR_E1RPP      0x00000080
+#define CPC0_EPRCSR_E0RPP      0x00000040
+#define CPC0_EPRCSR_E1ERP      0x00000020
+#define CPC0_EPRCSR_E0ERP      0x00000010
+#define CPC0_EPRCSR_E1PCI      0x00000002
+#define CPC0_EPRCSR_E0PCI      0x00000001
 
-#define cpr0_clkupd	0x020
-#define cpr0_pllc	0x040
-#define cpr0_plld	0x060
-#define cpr0_cpud	0x080
-#define cpr0_plbd	0x0a0
-#define cpr0_opbd	0x0c0
-#define cpr0_perd	0x0e0
-#define cpr0_ahbd	0x100
-#define cpr0_icfg	0x140
+#define cpr0_clkupd 0x020
+#define cpr0_pllc   0x040
+#define cpr0_plld   0x060
+#define cpr0_cpud   0x080
+#define cpr0_plbd   0x0a0
+#define cpr0_opbd   0x0c0
+#define cpr0_perd   0x0e0
+#define cpr0_ahbd   0x100
+#define cpr0_icfg   0x140
 
-#define SDR_PINSTP	0x0040
-#define sdr_sdcs	0x0060
+#define SDR_PINSTP  0x0040
+#define sdr_sdcs    0x0060
 
-#define SDR0_SDCS_SDD			(0x80000000 >> 31)
+#define SDR0_SDCS_SDD           (0x80000000 >> 31)
 
 /* CUST0 Customer Configuration Register0 */
-#define SDR0_CUST0		     0x4000
+#define SDR0_CUST0           0x4000
 #define   SDR0_CUST0_MUX_E_N_G_MASK   0xC0000000     /* Mux_Emac_NDFC_GPIO */
 #define   SDR0_CUST0_MUX_EMAC_SEL     0x40000000       /* Emac Selection */
 #define   SDR0_CUST0_MUX_NDFC_SEL     0x80000000       /* NDFC Selection */
@@ -924,9 +924,9 @@
 #define   SDR0_CUST0_NDFC_ARE_ENABLE  0x00200000       /* NDFC Auto Read Enable */
 #define   SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000       /* NDFC Auto Read Disable */
 
-#define   SDR0_CUST0_NRB_MASK	      0x00100000     /* NDFC Ready / Busy */
-#define   SDR0_CUST0_NRB_BUSY	      0x00100000       /* Busy */
-#define   SDR0_CUST0_NRB_READY	      0x00000000       /* Ready */
+#define   SDR0_CUST0_NRB_MASK         0x00100000     /* NDFC Ready / Busy */
+#define   SDR0_CUST0_NRB_BUSY         0x00100000       /* Busy */
+#define   SDR0_CUST0_NRB_READY        0x00000000       /* Ready */
 
 #define   SDR0_CUST0_NDRSC_MASK       0x0000FFF0     /* NDFC Device Reset Count Mask */
 #define   SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
@@ -940,41 +940,41 @@
 #define   SDR0_CUST0_CHIPSELGAT_EN2   0x00000002       /* Chip Select2 Gating Enable */
 #define   SDR0_CUST0_CHIPSELGAT_EN3   0x00000001       /* Chip Select3 Gating Enable */
 
-#define SDR0_PFC0		0x4100
-#define SDR0_PFC1		0x4101
-#define SDR0_PFC1_U1ME		0x02000000
-#define SDR0_PFC1_U0ME		0x00080000
-#define SDR0_PFC1_U0IM		0x00040000
-#define SDR0_PFC1_SIS		0x00020000
-#define SDR0_PFC1_DMAAEN	0x00010000
-#define SDR0_PFC1_DMADEN	0x00008000
-#define SDR0_PFC1_USBEN		0x00004000
-#define SDR0_PFC1_AHBSWAP	0x00000020
-#define SDR0_PFC1_USBBIGEN	0x00000010
-#define SDR0_PFC1_GPT_FREQ	0x0000000f
+#define SDR0_PFC0       0x4100
+#define SDR0_PFC1       0x4101
+#define SDR0_PFC1_U1ME      0x02000000
+#define SDR0_PFC1_U0ME      0x00080000
+#define SDR0_PFC1_U0IM      0x00040000
+#define SDR0_PFC1_SIS       0x00020000
+#define SDR0_PFC1_DMAAEN    0x00010000
+#define SDR0_PFC1_DMADEN    0x00008000
+#define SDR0_PFC1_USBEN     0x00004000
+#define SDR0_PFC1_AHBSWAP   0x00000020
+#define SDR0_PFC1_USBBIGEN  0x00000010
+#define SDR0_PFC1_GPT_FREQ  0x0000000f
 #endif
 
 /* General Purpose Timer (GPT) Register Offsets */
-#define GPT0_TBC		0x00000000
-#define GPT0_IM			0x00000018
-#define GPT0_ISS		0x0000001C
-#define GPT0_ISC		0x00000020
-#define GPT0_IE			0x00000024
-#define GPT0_COMP0		0x00000080
-#define GPT0_COMP1		0x00000084
-#define GPT0_COMP2		0x00000088
-#define GPT0_COMP3		0x0000008C
-#define GPT0_COMP4		0x00000090
-#define GPT0_COMP5		0x00000094
-#define GPT0_COMP6		0x00000098
-#define GPT0_MASK0		0x000000C0
-#define GPT0_MASK1		0x000000C4
-#define GPT0_MASK2		0x000000C8
-#define GPT0_MASK3		0x000000CC
-#define GPT0_MASK4		0x000000D0
-#define GPT0_MASK5		0x000000D4
-#define GPT0_MASK6		0x000000D8
-#define GPT0_DCT0		0x00000110
-#define GPT0_DCIS		0x0000011C
+#define GPT0_TBC        0x00000000
+#define GPT0_IM         0x00000018
+#define GPT0_ISS        0x0000001C
+#define GPT0_ISC        0x00000020
+#define GPT0_IE         0x00000024
+#define GPT0_COMP0      0x00000080
+#define GPT0_COMP1      0x00000084
+#define GPT0_COMP2      0x00000088
+#define GPT0_COMP3      0x0000008C
+#define GPT0_COMP4      0x00000090
+#define GPT0_COMP5      0x00000094
+#define GPT0_COMP6      0x00000098
+#define GPT0_MASK0      0x000000C0
+#define GPT0_MASK1      0x000000C4
+#define GPT0_MASK2      0x000000C8
+#define GPT0_MASK3      0x000000CC
+#define GPT0_MASK4      0x000000D0
+#define GPT0_MASK5      0x000000D4
+#define GPT0_MASK6      0x000000D8
+#define GPT0_DCT0       0x00000110
+#define GPT0_DCIS       0x0000011C
 
-#endif	/* __PPC405_H__ */
+#endif  /* __PPC405_H__ */
diff --git a/libcpu/ppc/ppc405/include/asm/ppc4xx-uic.h b/libcpu/ppc/ppc405/include/asm/ppc4xx-uic.h
index cdb542c2da..83b55e5e64 100644
--- a/libcpu/ppc/ppc405/include/asm/ppc4xx-uic.h
+++ b/libcpu/ppc/ppc405/include/asm/ppc4xx-uic.h
@@ -4,8 +4,8 @@
 /*
  * Define the number of UIC's
  */
-#define UIC_MAX		1
-#define IRQ_MAX		UIC_MAX * 32
+#define UIC_MAX     1
+#define IRQ_MAX     UIC_MAX * 32
 
 /* UIC0 dcr base address */
 #define UIC0_DCR_BASE 0xc0
@@ -13,49 +13,49 @@
 /*
  * UIC register
  */
-#define UIC_SR	0x0			/* UIC status			*/
-#define UIC_ER	0x2			/* UIC enable			*/
-#define UIC_CR	0x3			/* UIC critical			*/
-#define UIC_PR	0x4			/* UIC polarity			*/
-#define UIC_TR	0x5			/* UIC triggering		*/
-#define UIC_MSR 0x6			/* UIC masked status		*/
-#define UIC_VR	0x7			/* UIC vector			*/
-#define UIC_VCR 0x8			/* UIC vector configuration	*/
+#define UIC_SR  0x0         /* UIC status           */
+#define UIC_ER  0x2         /* UIC enable           */
+#define UIC_CR  0x3         /* UIC critical         */
+#define UIC_PR  0x4         /* UIC polarity         */
+#define UIC_TR  0x5         /* UIC triggering       */
+#define UIC_MSR 0x6         /* UIC masked status        */
+#define UIC_VR  0x7         /* UIC vector           */
+#define UIC_VCR 0x8         /* UIC vector configuration */
 
-#define uic0sr	(UIC0_DCR_BASE+0x0)	/* UIC0 status			*/
-#define uic0er	(UIC0_DCR_BASE+0x2)	/* UIC0 enable			*/
-#define uic0cr	(UIC0_DCR_BASE+0x3)	/* UIC0 critical		*/
-#define uic0pr	(UIC0_DCR_BASE+0x4)	/* UIC0 polarity		*/
-#define uic0tr	(UIC0_DCR_BASE+0x5)	/* UIC0 triggering		*/
-#define uic0msr (UIC0_DCR_BASE+0x6)	/* UIC0 masked status		*/
-#define uic0vr	(UIC0_DCR_BASE+0x7)	/* UIC0 vector			*/
-#define uic0vcr (UIC0_DCR_BASE+0x8)	/* UIC0 vector configuration	*/
+#define uic0sr  (UIC0_DCR_BASE+0x0) /* UIC0 status          */
+#define uic0er  (UIC0_DCR_BASE+0x2) /* UIC0 enable          */
+#define uic0cr  (UIC0_DCR_BASE+0x3) /* UIC0 critical        */
+#define uic0pr  (UIC0_DCR_BASE+0x4) /* UIC0 polarity        */
+#define uic0tr  (UIC0_DCR_BASE+0x5) /* UIC0 triggering      */
+#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status       */
+#define uic0vr  (UIC0_DCR_BASE+0x7) /* UIC0 vector          */
+#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration    */
 
 /* The following is for compatibility with 405 code */
-#define uicsr	uic0sr
-#define uicer	uic0er
-#define uiccr	uic0cr
-#define uicpr	uic0pr
-#define uictr	uic0tr
-#define uicmsr	uic0msr
-#define uicvr	uic0vr
-#define uicvcr	uic0vcr
+#define uicsr   uic0sr
+#define uicer   uic0er
+#define uiccr   uic0cr
+#define uicpr   uic0pr
+#define uictr   uic0tr
+#define uicmsr  uic0msr
+#define uicvr   uic0vr
+#define uicvcr  uic0vcr
 
 /* the interrupt vector definitions */
-#define VECNUM_MAL_SERR		10
-#define VECNUM_MAL_TXEOB	11
-#define VECNUM_MAL_RXEOB	12
-#define VECNUM_MAL_TXDE		13
-#define VECNUM_MAL_RXDE		14
-#define VECNUM_ETH0			15
-#define VECNUM_ETH1_OFFS	2
-#define VECNUM_EIRQ6		29
+#define VECNUM_MAL_SERR     10
+#define VECNUM_MAL_TXEOB    11
+#define VECNUM_MAL_RXEOB    12
+#define VECNUM_MAL_TXDE     13
+#define VECNUM_MAL_RXDE     14
+#define VECNUM_ETH0         15
+#define VECNUM_ETH1_OFFS    2
+#define VECNUM_EIRQ6        29
 
 /*
  * Mask definitions (used for example in 4xx_enet.c)
  */
-#define UIC_MASK(vec)		(0x80000000 >> ((vec) & 0x1f))
+#define UIC_MASK(vec)       (0x80000000 >> ((vec) & 0x1f))
 /* UIC_NR won't work for 440GX because of its specific UIC DCR addresses */
-#define UIC_NR(vec)			((vec) >> 5)
+#define UIC_NR(vec)         ((vec) >> 5)
 
 #endif /* _PPC4xx_UIC_H_ */
diff --git a/libcpu/ppc/ppc405/include/asm/ppc4xx.h b/libcpu/ppc/ppc405/include/asm/ppc4xx.h
index 57fe7ab221..2bfef123d6 100644
--- a/libcpu/ppc/ppc405/include/asm/ppc4xx.h
+++ b/libcpu/ppc/ppc405/include/asm/ppc4xx.h
@@ -19,13 +19,13 @@
 |       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
 +----------------------------------------------------------------------------*/
 
-#ifndef	__PPC4XX_H__
+#ifndef __PPC4XX_H__
 #define __PPC4XX_H__
 
 /*
  * Configure which SDRAM/DDR/DDR2 controller is equipped
  */
-#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM	/* IBM SDRAM controller */
+#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM   /* IBM SDRAM controller */
 
 #include 
 #include 
@@ -33,102 +33,102 @@
 /*
  * Macro for generating register field mnemonics
  */
-#define	PPC_REG_BITS		32
-#define	PPC_REG_VAL(bit, value)	((value) << ((PPC_REG_BITS - 1) - (bit)))
+#define PPC_REG_BITS        32
+#define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit)))
 
 /*
  * Elide casts when assembling register mnemonics
  */
 #ifndef __ASSEMBLY__
-#define	static_cast(type, val)	(type)(val)
+#define static_cast(type, val)  (type)(val)
 #else
-#define	static_cast(type, val)	(val)
+#define static_cast(type, val)  (val)
 #endif
 
 /*
  * Common stuff for 4xx (405 and 440)
  */
 
-#define EXC_OFF_SYS_RESET	0x0100	/* System reset				*/
-#define _START_OFFSET		(EXC_OFF_SYS_RESET + 0x2000)
+#define EXC_OFF_SYS_RESET   0x0100  /* System reset             */
+#define _START_OFFSET       (EXC_OFF_SYS_RESET + 0x2000)
 
-#define RESET_VECTOR	0xfffffffc
-#define CACHELINE_MASK	(CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for cache
-						     line aligned data. */
+#define RESET_VECTOR    0xfffffffc
+#define CACHELINE_MASK  (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for cache
+                             line aligned data. */
 
-#define CPR0_DCR_BASE	0x0C
-#define cprcfga		(CPR0_DCR_BASE+0x0)
-#define cprcfgd		(CPR0_DCR_BASE+0x1)
+#define CPR0_DCR_BASE   0x0C
+#define cprcfga     (CPR0_DCR_BASE+0x0)
+#define cprcfgd     (CPR0_DCR_BASE+0x1)
 
-#define SDR_DCR_BASE	0x0E
-#define sdrcfga		(SDR_DCR_BASE+0x0)
-#define sdrcfgd		(SDR_DCR_BASE+0x1)
+#define SDR_DCR_BASE    0x0E
+#define sdrcfga     (SDR_DCR_BASE+0x0)
+#define sdrcfgd     (SDR_DCR_BASE+0x1)
 
-#define SDRAM_DCR_BASE	0x10
-#define memcfga		(SDRAM_DCR_BASE+0x0)
-#define memcfgd		(SDRAM_DCR_BASE+0x1)
+#define SDRAM_DCR_BASE  0x10
+#define memcfga     (SDRAM_DCR_BASE+0x0)
+#define memcfgd     (SDRAM_DCR_BASE+0x1)
 
-#define EBC_DCR_BASE	0x12
-#define ebccfga		(EBC_DCR_BASE+0x0)
-#define ebccfgd		(EBC_DCR_BASE+0x1)
+#define EBC_DCR_BASE    0x12
+#define ebccfga     (EBC_DCR_BASE+0x0)
+#define ebccfgd     (EBC_DCR_BASE+0x1)
 
 /*
  * Macros for indirect DCR access
  */
-#define mtcpr(reg, d)	do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0)
-#define mfcpr(reg, d)	do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0)
+#define mtcpr(reg, d)   do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0)
+#define mfcpr(reg, d)   do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0)
 
-#define mtebc(reg, d)	do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0)
-#define mfebc(reg, d)	do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0)
+#define mtebc(reg, d)   do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0)
+#define mfebc(reg, d)   do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0)
 
-#define mtsdram(reg, d)	do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0)
-#define mfsdram(reg, d)	do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0)
+#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0)
+#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0)
 
-#define mtsdr(reg, d)	do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0)
-#define mfsdr(reg, d)	do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0)
+#define mtsdr(reg, d)   do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0)
+#define mfsdr(reg, d)   do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0)
 
 #ifndef __ASSEMBLY__
 
 typedef struct
 {
-	unsigned long freqDDR;
-	unsigned long freqEBC;
-	unsigned long freqOPB;
-	unsigned long freqPCI;
-	unsigned long freqPLB;
-	unsigned long freqTmrClk;
-	unsigned long freqUART;
-	unsigned long freqProcessor;
-	unsigned long freqVCOHz;
-	unsigned long freqVCOMhz;	/* in MHz                          */
-	unsigned long pciClkSync;	/* PCI clock is synchronous        */
-	unsigned long pciIntArbEn;	/* Internal PCI arbiter is enabled */
-	unsigned long pllExtBusDiv;
-	unsigned long pllFbkDiv;
-	unsigned long pllFwdDiv;
-	unsigned long pllFwdDivA;
-	unsigned long pllFwdDivB;
-	unsigned long pllOpbDiv;
-	unsigned long pllPciDiv;
-	unsigned long pllPlbDiv;
+    unsigned long freqDDR;
+    unsigned long freqEBC;
+    unsigned long freqOPB;
+    unsigned long freqPCI;
+    unsigned long freqPLB;
+    unsigned long freqTmrClk;
+    unsigned long freqUART;
+    unsigned long freqProcessor;
+    unsigned long freqVCOHz;
+    unsigned long freqVCOMhz;   /* in MHz                          */
+    unsigned long pciClkSync;   /* PCI clock is synchronous        */
+    unsigned long pciIntArbEn;  /* Internal PCI arbiter is enabled */
+    unsigned long pllExtBusDiv;
+    unsigned long pllFbkDiv;
+    unsigned long pllFwdDiv;
+    unsigned long pllFwdDivA;
+    unsigned long pllFwdDivB;
+    unsigned long pllOpbDiv;
+    unsigned long pllPciDiv;
+    unsigned long pllPlbDiv;
 } PPC4xx_SYS_INFO;
 
 static inline rt_uint32_t get_mcsr(void)
 {
-	rt_uint32_t val;
+    rt_uint32_t val;
 
-	asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
-	return val;
+    asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
+    return val;
 }
 
 static inline void set_mcsr(rt_uint32_t val)
 {
-	asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
+    asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
 }
 
-#endif	/* __ASSEMBLY__ */
+#endif  /* __ASSEMBLY__ */
 
 /* for multi-cpu support */
-#define NA_OR_UNKNOWN_CPU	-1
+#define NA_OR_UNKNOWN_CPU   -1
 
-#endif	/* __PPC4XX_H__ */
+#endif  /* __PPC4XX_H__ */
diff --git a/libcpu/ppc/ppc405/include/asm/ppc_defs.h b/libcpu/ppc/ppc405/include/asm/ppc_defs.h
index 88aed26009..0b6d06deae 100644
--- a/libcpu/ppc/ppc405/include/asm/ppc_defs.h
+++ b/libcpu/ppc/ppc405/include/asm/ppc_defs.h
@@ -24,50 +24,50 @@
 /*
  * WARNING! This file is automatically generated - DO NOT EDIT!
  */
-#define	STACK_FRAME_OVERHEAD	16
-#define	INT_FRAME_SIZE	192
-#define	GPR0	16
-#define	GPR1	20
-#define	GPR2	24
-#define	GPR3	28
-#define	GPR4	32
-#define	GPR5	36
-#define	GPR6	40
-#define	GPR7	44
-#define	GPR8	48
-#define	GPR9	52
-#define	GPR10	56
-#define	GPR11	60
-#define	GPR12	64
-#define	GPR13	68
-#define	GPR14	72
-#define	GPR15	76
-#define	GPR16	80
-#define	GPR17	84
-#define	GPR18	88
-#define	GPR19	92
-#define	GPR20	96
-#define	GPR21	100
-#define	GPR22	104
-#define	GPR23	108
-#define	GPR24	112
-#define	GPR25	116
-#define	GPR26	120
-#define	GPR27	124
-#define	GPR28	128
-#define	GPR29	132
-#define	GPR30	136
-#define	GPR31	140
-#define	_NIP	144
-#define	_MSR	148
-#define	ORIG_GPR3	152
-#define	_CTR	156
-#define	_LINK	160
-#define	_XER	164
-#define	_CCR	168
-#define	_MQ	    172
-#define	TRAP	176
-#define	_DAR	180
-#define	_DSISR	184
-#define	RESULT	188
+#define STACK_FRAME_OVERHEAD    16
+#define INT_FRAME_SIZE  192
+#define GPR0    16
+#define GPR1    20
+#define GPR2    24
+#define GPR3    28
+#define GPR4    32
+#define GPR5    36
+#define GPR6    40
+#define GPR7    44
+#define GPR8    48
+#define GPR9    52
+#define GPR10   56
+#define GPR11   60
+#define GPR12   64
+#define GPR13   68
+#define GPR14   72
+#define GPR15   76
+#define GPR16   80
+#define GPR17   84
+#define GPR18   88
+#define GPR19   92
+#define GPR20   96
+#define GPR21   100
+#define GPR22   104
+#define GPR23   108
+#define GPR24   112
+#define GPR25   116
+#define GPR26   120
+#define GPR27   124
+#define GPR28   128
+#define GPR29   132
+#define GPR30   136
+#define GPR31   140
+#define _NIP    144
+#define _MSR    148
+#define ORIG_GPR3   152
+#define _CTR    156
+#define _LINK   160
+#define _XER    164
+#define _CCR    168
+#define _MQ     172
+#define TRAP    176
+#define _DAR    180
+#define _DSISR  184
+#define RESULT  188
 
diff --git a/libcpu/ppc/ppc405/include/asm/processor.h b/libcpu/ppc/ppc405/include/asm/processor.h
index 7aeeb01dc5..827de2186b 100644
--- a/libcpu/ppc/ppc405/include/asm/processor.h
+++ b/libcpu/ppc/ppc405/include/asm/processor.h
@@ -15,80 +15,80 @@
 /* Machine State Register (MSR) Fields */
 
 #ifdef CONFIG_PPC64BRIDGE
-#define MSR_SF		(1<<63)
-#define MSR_ISF		(1<<61)
+#define MSR_SF      (1<<63)
+#define MSR_ISF     (1<<61)
 #endif /* CONFIG_PPC64BRIDGE */
-#define MSR_UCLE	(1<<26)		/* User-mode cache lock enable (e500) */
-#define MSR_VEC		(1<<25)		/* Enable AltiVec(74xx) */
-#define MSR_SPE		(1<<25)		/* Enable SPE(e500) */
-#define MSR_POW		(1<<18)		/* Enable Power Management */
-#define MSR_WE		(1<<18)		/* Wait State Enable */
-#define MSR_TGPR	(1<<17)		/* TLB Update registers in use */
-#define MSR_CE		(1<<17)		/* Critical Interrupt Enable */
-#define MSR_ILE		(1<<16)		/* Interrupt Little Endian */
-#define MSR_EE		(1<<15)		/* External Interrupt Enable */
-#define MSR_PR		(1<<14)		/* Problem State / Privilege Level */
-#define MSR_FP		(1<<13)		/* Floating Point enable */
-#define MSR_ME		(1<<12)		/* Machine Check Enable */
-#define MSR_FE0		(1<<11)		/* Floating Exception mode 0 */
-#define MSR_SE		(1<<10)		/* Single Step */
-#define MSR_DWE		(1<<10)		/* Debug Wait Enable (4xx) */
-#define MSR_UBLE	(1<<10)		/* BTB lock enable (e500) */
-#define MSR_BE		(1<<9)		/* Branch Trace */
-#define MSR_DE		(1<<9)		/* Debug Exception Enable */
-#define MSR_FE1		(1<<8)		/* Floating Exception mode 1 */
-#define MSR_IP		(1<<6)		/* Exception prefix 0x000/0xFFF */
-#define MSR_IR		(1<<5)		/* Instruction Relocate */
-#define MSR_IS		(1<<5)		/* Book E Instruction space */
-#define MSR_DR		(1<<4)		/* Data Relocate */
-#define MSR_DS		(1<<4)		/* Book E Data space */
-#define MSR_PE		(1<<3)		/* Protection Enable */
-#define MSR_PX		(1<<2)		/* Protection Exclusive Mode */
-#define MSR_PMM		(1<<2)		/* Performance monitor mark bit (e500) */
-#define MSR_RI		(1<<1)		/* Recoverable Exception */
-#define MSR_LE		(1<<0)		/* Little Endian */
+#define MSR_UCLE    (1<<26)     /* User-mode cache lock enable (e500) */
+#define MSR_VEC     (1<<25)     /* Enable AltiVec(74xx) */
+#define MSR_SPE     (1<<25)     /* Enable SPE(e500) */
+#define MSR_POW     (1<<18)     /* Enable Power Management */
+#define MSR_WE      (1<<18)     /* Wait State Enable */
+#define MSR_TGPR    (1<<17)     /* TLB Update registers in use */
+#define MSR_CE      (1<<17)     /* Critical Interrupt Enable */
+#define MSR_ILE     (1<<16)     /* Interrupt Little Endian */
+#define MSR_EE      (1<<15)     /* External Interrupt Enable */
+#define MSR_PR      (1<<14)     /* Problem State / Privilege Level */
+#define MSR_FP      (1<<13)     /* Floating Point enable */
+#define MSR_ME      (1<<12)     /* Machine Check Enable */
+#define MSR_FE0     (1<<11)     /* Floating Exception mode 0 */
+#define MSR_SE      (1<<10)     /* Single Step */
+#define MSR_DWE     (1<<10)     /* Debug Wait Enable (4xx) */
+#define MSR_UBLE    (1<<10)     /* BTB lock enable (e500) */
+#define MSR_BE      (1<<9)      /* Branch Trace */
+#define MSR_DE      (1<<9)      /* Debug Exception Enable */
+#define MSR_FE1     (1<<8)      /* Floating Exception mode 1 */
+#define MSR_IP      (1<<6)      /* Exception prefix 0x000/0xFFF */
+#define MSR_IR      (1<<5)      /* Instruction Relocate */
+#define MSR_IS      (1<<5)      /* Book E Instruction space */
+#define MSR_DR      (1<<4)      /* Data Relocate */
+#define MSR_DS      (1<<4)      /* Book E Data space */
+#define MSR_PE      (1<<3)      /* Protection Enable */
+#define MSR_PX      (1<<2)      /* Protection Exclusive Mode */
+#define MSR_PMM     (1<<2)      /* Performance monitor mark bit (e500) */
+#define MSR_RI      (1<<1)      /* Recoverable Exception */
+#define MSR_LE      (1<<0)      /* Little Endian */
 
 #ifdef CONFIG_APUS_FAST_EXCEPT
-#define MSR_		MSR_ME|MSR_IP|MSR_RI
+#define MSR_        MSR_ME|MSR_IP|MSR_RI
 #else
-#define MSR_		MSR_ME|MSR_RI
+#define MSR_        MSR_ME|MSR_RI
 #endif
 
 #ifndef CONFIG_E500
-#define MSR_KERNEL	MSR_|MSR_IR|MSR_DR
+#define MSR_KERNEL  MSR_|MSR_IR|MSR_DR
 #else
-#define MSR_KERNEL	MSR_ME
+#define MSR_KERNEL  MSR_ME
 #endif
 
 /* Floating Point Status and Control Register (FPSCR) Fields */
 
-#define FPSCR_FX	0x80000000	/* FPU exception summary */
-#define FPSCR_FEX	0x40000000	/* FPU enabled exception summary */
-#define FPSCR_VX	0x20000000	/* Invalid operation summary */
-#define FPSCR_OX	0x10000000	/* Overflow exception summary */
-#define FPSCR_UX	0x08000000	/* Underflow exception summary */
-#define FPSCR_ZX	0x04000000	/* Zero-devide exception summary */
-#define FPSCR_XX	0x02000000	/* Inexact exception summary */
-#define FPSCR_VXSNAN	0x01000000	/* Invalid op for SNaN */
-#define FPSCR_VXISI	0x00800000	/* Invalid op for Inv - Inv */
-#define FPSCR_VXIDI	0x00400000	/* Invalid op for Inv / Inv */
-#define FPSCR_VXZDZ	0x00200000	/* Invalid op for Zero / Zero */
-#define FPSCR_VXIMZ	0x00100000	/* Invalid op for Inv * Zero */
-#define FPSCR_VXVC	0x00080000	/* Invalid op for Compare */
-#define FPSCR_FR	0x00040000	/* Fraction rounded */
-#define FPSCR_FI	0x00020000	/* Fraction inexact */
-#define FPSCR_FPRF	0x0001f000	/* FPU Result Flags */
-#define FPSCR_FPCC	0x0000f000	/* FPU Condition Codes */
-#define FPSCR_VXSOFT	0x00000400	/* Invalid op for software request */
-#define FPSCR_VXSQRT	0x00000200	/* Invalid op for square root */
-#define FPSCR_VXCVI	0x00000100	/* Invalid op for integer convert */
-#define FPSCR_VE	0x00000080	/* Invalid op exception enable */
-#define FPSCR_OE	0x00000040	/* IEEE overflow exception enable */
-#define FPSCR_UE	0x00000020	/* IEEE underflow exception enable */
-#define FPSCR_ZE	0x00000010	/* IEEE zero divide exception enable */
-#define FPSCR_XE	0x00000008	/* FP inexact exception enable */
-#define FPSCR_NI	0x00000004	/* FPU non IEEE-Mode */
-#define FPSCR_RN	0x00000003	/* FPU rounding control */
+#define FPSCR_FX    0x80000000  /* FPU exception summary */
+#define FPSCR_FEX   0x40000000  /* FPU enabled exception summary */
+#define FPSCR_VX    0x20000000  /* Invalid operation summary */
+#define FPSCR_OX    0x10000000  /* Overflow exception summary */
+#define FPSCR_UX    0x08000000  /* Underflow exception summary */
+#define FPSCR_ZX    0x04000000  /* Zero-devide exception summary */
+#define FPSCR_XX    0x02000000  /* Inexact exception summary */
+#define FPSCR_VXSNAN    0x01000000  /* Invalid op for SNaN */
+#define FPSCR_VXISI 0x00800000  /* Invalid op for Inv - Inv */
+#define FPSCR_VXIDI 0x00400000  /* Invalid op for Inv / Inv */
+#define FPSCR_VXZDZ 0x00200000  /* Invalid op for Zero / Zero */
+#define FPSCR_VXIMZ 0x00100000  /* Invalid op for Inv * Zero */
+#define FPSCR_VXVC  0x00080000  /* Invalid op for Compare */
+#define FPSCR_FR    0x00040000  /* Fraction rounded */
+#define FPSCR_FI    0x00020000  /* Fraction inexact */
+#define FPSCR_FPRF  0x0001f000  /* FPU Result Flags */
+#define FPSCR_FPCC  0x0000f000  /* FPU Condition Codes */
+#define FPSCR_VXSOFT    0x00000400  /* Invalid op for software request */
+#define FPSCR_VXSQRT    0x00000200  /* Invalid op for square root */
+#define FPSCR_VXCVI 0x00000100  /* Invalid op for integer convert */
+#define FPSCR_VE    0x00000080  /* Invalid op exception enable */
+#define FPSCR_OE    0x00000040  /* IEEE overflow exception enable */
+#define FPSCR_UE    0x00000020  /* IEEE underflow exception enable */
+#define FPSCR_ZE    0x00000010  /* IEEE zero divide exception enable */
+#define FPSCR_XE    0x00000008  /* FP inexact exception enable */
+#define FPSCR_NI    0x00000004  /* FPU non IEEE-Mode */
+#define FPSCR_RN    0x00000003  /* FPU rounding control */
 
 /* Special Purpose Registers (SPRNs)*/
 
@@ -97,618 +97,618 @@
 #define CONFIG_BOOKE
 #endif
 
-#define SPRN_CCR0	0x3B3	/* Core Configuration Register 0 */
+#define SPRN_CCR0   0x3B3   /* Core Configuration Register 0 */
 #ifdef CONFIG_BOOKE
-#define SPRN_CCR1	0x378	/* Core Configuration Register for 440 only */
+#define SPRN_CCR1   0x378   /* Core Configuration Register for 440 only */
 #endif
-#define SPRN_CDBCR	0x3D7	/* Cache Debug Control Register */
-#define SPRN_CTR	0x009	/* Count Register */
-#define SPRN_DABR	0x3F5	/* Data Address Breakpoint Register */
+#define SPRN_CDBCR  0x3D7   /* Cache Debug Control Register */
+#define SPRN_CTR    0x009   /* Count Register */
+#define SPRN_DABR   0x3F5   /* Data Address Breakpoint Register */
 #ifndef CONFIG_BOOKE
-#define SPRN_DAC1	0x3F6	/* Data Address Compare 1 */
-#define SPRN_DAC2	0x3F7	/* Data Address Compare 2 */
+#define SPRN_DAC1   0x3F6   /* Data Address Compare 1 */
+#define SPRN_DAC2   0x3F7   /* Data Address Compare 2 */
 #else
-#define SPRN_DAC1	0x13C	/* Book E Data Address Compare 1 */
-#define SPRN_DAC2	0x13D	/* Book E Data Address Compare 2 */
-#endif	/* CONFIG_BOOKE */
-#define SPRN_DAR	0x013	/* Data Address Register */
-#define SPRN_DBAT0L	0x219	/* Data BAT 0 Lower Register */
-#define SPRN_DBAT0U	0x218	/* Data BAT 0 Upper Register */
-#define SPRN_DBAT1L	0x21B	/* Data BAT 1 Lower Register */
-#define SPRN_DBAT1U	0x21A	/* Data BAT 1 Upper Register */
-#define SPRN_DBAT2L	0x21D	/* Data BAT 2 Lower Register */
-#define SPRN_DBAT2U	0x21C	/* Data BAT 2 Upper Register */
-#define SPRN_DBAT3L	0x21F	/* Data BAT 3 Lower Register */
-#define SPRN_DBAT3U	0x21E	/* Data BAT 3 Upper Register */
-#define SPRN_DBAT4L	0x239	/* Data BAT 4 Lower Register */
-#define SPRN_DBAT4U	0x238	/* Data BAT 4 Upper Register */
-#define SPRN_DBAT5L	0x23B	/* Data BAT 5 Lower Register */
-#define SPRN_DBAT5U	0x23A	/* Data BAT 5 Upper Register */
-#define SPRN_DBAT6L	0x23D	/* Data BAT 6 Lower Register */
-#define SPRN_DBAT6U	0x23C	/* Data BAT 6 Upper Register */
-#define SPRN_DBAT7L	0x23F	/* Data BAT 7 Lower Register */
-#define SPRN_DBAT7U	0x23E	/* Data BAT 7 Lower Register */
-#define SPRN_DBCR	0x3F2	/* Debug Control Regsiter */
-#define   DBCR_EDM	0x80000000
-#define   DBCR_IDM	0x40000000
-#define   DBCR_RST(x)	(((x) & 0x3) << 28)
-#define     DBCR_RST_NONE		0
-#define     DBCR_RST_CORE		1
-#define     DBCR_RST_CHIP		2
-#define     DBCR_RST_SYSTEM		3
-#define   DBCR_IC	0x08000000	/* Instruction Completion Debug Evnt */
-#define   DBCR_BT	0x04000000	/* Branch Taken Debug Event */
-#define   DBCR_EDE	0x02000000	/* Exception Debug Event */
-#define   DBCR_TDE	0x01000000	/* TRAP Debug Event */
-#define   DBCR_FER	0x00F80000	/* First Events Remaining Mask */
-#define   DBCR_FT	0x00040000	/* Freeze Timers on Debug Event */
-#define   DBCR_IA1	0x00020000	/* Instr. Addr. Compare 1 Enable */
-#define   DBCR_IA2	0x00010000	/* Instr. Addr. Compare 2 Enable */
-#define   DBCR_D1R	0x00008000	/* Data Addr. Compare 1 Read Enable */
-#define   DBCR_D1W	0x00004000	/* Data Addr. Compare 1 Write Enable */
-#define   DBCR_D1S(x)	(((x) & 0x3) << 12)	/* Data Adrr. Compare 1 Size */
-#define     DAC_BYTE	0
-#define     DAC_HALF	1
-#define     DAC_WORD	2
-#define     DAC_QUAD	3
-#define   DBCR_D2R	0x00000800	/* Data Addr. Compare 2 Read Enable */
-#define   DBCR_D2W	0x00000400	/* Data Addr. Compare 2 Write Enable */
-#define   DBCR_D2S(x)	(((x) & 0x3) << 8)	/* Data Addr. Compare 2 Size */
-#define   DBCR_SBT	0x00000040	/* Second Branch Taken Debug Event */
-#define   DBCR_SED	0x00000020	/* Second Exception Debug Event */
-#define   DBCR_STD	0x00000010	/* Second Trap Debug Event */
-#define   DBCR_SIA	0x00000008	/* Second IAC Enable */
-#define   DBCR_SDA	0x00000004	/* Second DAC Enable */
-#define   DBCR_JOI	0x00000002	/* JTAG Serial Outbound Int. Enable */
-#define   DBCR_JII	0x00000001	/* JTAG Serial Inbound Int. Enable */
+#define SPRN_DAC1   0x13C   /* Book E Data Address Compare 1 */
+#define SPRN_DAC2   0x13D   /* Book E Data Address Compare 2 */
+#endif  /* CONFIG_BOOKE */
+#define SPRN_DAR    0x013   /* Data Address Register */
+#define SPRN_DBAT0L 0x219   /* Data BAT 0 Lower Register */
+#define SPRN_DBAT0U 0x218   /* Data BAT 0 Upper Register */
+#define SPRN_DBAT1L 0x21B   /* Data BAT 1 Lower Register */
+#define SPRN_DBAT1U 0x21A   /* Data BAT 1 Upper Register */
+#define SPRN_DBAT2L 0x21D   /* Data BAT 2 Lower Register */
+#define SPRN_DBAT2U 0x21C   /* Data BAT 2 Upper Register */
+#define SPRN_DBAT3L 0x21F   /* Data BAT 3 Lower Register */
+#define SPRN_DBAT3U 0x21E   /* Data BAT 3 Upper Register */
+#define SPRN_DBAT4L 0x239   /* Data BAT 4 Lower Register */
+#define SPRN_DBAT4U 0x238   /* Data BAT 4 Upper Register */
+#define SPRN_DBAT5L 0x23B   /* Data BAT 5 Lower Register */
+#define SPRN_DBAT5U 0x23A   /* Data BAT 5 Upper Register */
+#define SPRN_DBAT6L 0x23D   /* Data BAT 6 Lower Register */
+#define SPRN_DBAT6U 0x23C   /* Data BAT 6 Upper Register */
+#define SPRN_DBAT7L 0x23F   /* Data BAT 7 Lower Register */
+#define SPRN_DBAT7U 0x23E   /* Data BAT 7 Lower Register */
+#define SPRN_DBCR   0x3F2   /* Debug Control Regsiter */
+#define   DBCR_EDM  0x80000000
+#define   DBCR_IDM  0x40000000
+#define   DBCR_RST(x)   (((x) & 0x3) << 28)
+#define     DBCR_RST_NONE       0
+#define     DBCR_RST_CORE       1
+#define     DBCR_RST_CHIP       2
+#define     DBCR_RST_SYSTEM     3
+#define   DBCR_IC   0x08000000  /* Instruction Completion Debug Evnt */
+#define   DBCR_BT   0x04000000  /* Branch Taken Debug Event */
+#define   DBCR_EDE  0x02000000  /* Exception Debug Event */
+#define   DBCR_TDE  0x01000000  /* TRAP Debug Event */
+#define   DBCR_FER  0x00F80000  /* First Events Remaining Mask */
+#define   DBCR_FT   0x00040000  /* Freeze Timers on Debug Event */
+#define   DBCR_IA1  0x00020000  /* Instr. Addr. Compare 1 Enable */
+#define   DBCR_IA2  0x00010000  /* Instr. Addr. Compare 2 Enable */
+#define   DBCR_D1R  0x00008000  /* Data Addr. Compare 1 Read Enable */
+#define   DBCR_D1W  0x00004000  /* Data Addr. Compare 1 Write Enable */
+#define   DBCR_D1S(x)   (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
+#define     DAC_BYTE    0
+#define     DAC_HALF    1
+#define     DAC_WORD    2
+#define     DAC_QUAD    3
+#define   DBCR_D2R  0x00000800  /* Data Addr. Compare 2 Read Enable */
+#define   DBCR_D2W  0x00000400  /* Data Addr. Compare 2 Write Enable */
+#define   DBCR_D2S(x)   (((x) & 0x3) << 8)  /* Data Addr. Compare 2 Size */
+#define   DBCR_SBT  0x00000040  /* Second Branch Taken Debug Event */
+#define   DBCR_SED  0x00000020  /* Second Exception Debug Event */
+#define   DBCR_STD  0x00000010  /* Second Trap Debug Event */
+#define   DBCR_SIA  0x00000008  /* Second IAC Enable */
+#define   DBCR_SDA  0x00000004  /* Second DAC Enable */
+#define   DBCR_JOI  0x00000002  /* JTAG Serial Outbound Int. Enable */
+#define   DBCR_JII  0x00000001  /* JTAG Serial Inbound Int. Enable */
 #ifndef CONFIG_BOOKE
-#define SPRN_DBCR0	0x3F2		/* Debug Control Register 0 */
+#define SPRN_DBCR0  0x3F2       /* Debug Control Register 0 */
 #else
-#define SPRN_DBCR0	0x134		/* Book E Debug Control Register 0 */
+#define SPRN_DBCR0  0x134       /* Book E Debug Control Register 0 */
 #endif /* CONFIG_BOOKE */
 #ifndef CONFIG_BOOKE
-#define SPRN_DBCR1	0x3BD	/* Debug Control Register 1 */
-#define SPRN_DBSR	0x3F0	/* Debug Status Register */
+#define SPRN_DBCR1  0x3BD   /* Debug Control Register 1 */
+#define SPRN_DBSR   0x3F0   /* Debug Status Register */
 #else
-#define SPRN_DBCR1	0x135		/* Book E Debug Control Register 1 */
+#define SPRN_DBCR1  0x135       /* Book E Debug Control Register 1 */
 #ifdef CONFIG_BOOKE
-#define	SPRN_DBDR	0x3f3		/* Debug Data Register */
+#define SPRN_DBDR   0x3f3       /* Debug Data Register */
 #endif
-#define SPRN_DBSR	0x130		/* Book E Debug Status Register */
-#define   DBSR_IC	    0x08000000	/* Book E Instruction Completion  */
-#define   DBSR_TIE	    0x01000000	/* Book E Trap Instruction Event */
+#define SPRN_DBSR   0x130       /* Book E Debug Status Register */
+#define   DBSR_IC       0x08000000  /* Book E Instruction Completion  */
+#define   DBSR_TIE      0x01000000  /* Book E Trap Instruction Event */
 #endif /* CONFIG_BOOKE */
-#define SPRN_DCCR	0x3FA	/* Data Cache Cacheability Register */
-#define   DCCR_NOCACHE		0	/* Noncacheable */
-#define   DCCR_CACHE		1	/* Cacheable */
+#define SPRN_DCCR   0x3FA   /* Data Cache Cacheability Register */
+#define   DCCR_NOCACHE      0   /* Noncacheable */
+#define   DCCR_CACHE        1   /* Cacheable */
 #ifndef CONFIG_BOOKE
-#define	SPRN_DCDBTRL	0x39c	/* Data Cache Debug Tag Register Low */
-#define	SPRN_DCDBTRH	0x39d	/* Data Cache Debug Tag Register High */
+#define SPRN_DCDBTRL    0x39c   /* Data Cache Debug Tag Register Low */
+#define SPRN_DCDBTRH    0x39d   /* Data Cache Debug Tag Register High */
 #endif
-#define SPRN_DCMP	0x3D1	/* Data TLB Compare Register */
-#define SPRN_DCWR	0x3BA	/* Data Cache Write-thru Register */
-#define   DCWR_COPY		0	/* Copy-back */
-#define   DCWR_WRITE		1	/* Write-through */
+#define SPRN_DCMP   0x3D1   /* Data TLB Compare Register */
+#define SPRN_DCWR   0x3BA   /* Data Cache Write-thru Register */
+#define   DCWR_COPY     0   /* Copy-back */
+#define   DCWR_WRITE        1   /* Write-through */
 #ifndef CONFIG_BOOKE
-#define SPRN_DEAR	0x3D5	/* Data Error Address Register */
+#define SPRN_DEAR   0x3D5   /* Data Error Address Register */
 #else
-#define SPRN_DEAR	0x03D	/* Book E Data Error Address Register */
+#define SPRN_DEAR   0x03D   /* Book E Data Error Address Register */
 #endif /* CONFIG_BOOKE */
-#define SPRN_DEC	0x016	/* Decrement Register */
-#define SPRN_DMISS	0x3D0	/* Data TLB Miss Register */
+#define SPRN_DEC    0x016   /* Decrement Register */
+#define SPRN_DMISS  0x3D0   /* Data TLB Miss Register */
 #ifdef CONFIG_BOOKE
-#define	SPRN_DNV0	0x390	/* Data Cache Normal Victim 0 */
-#define	SPRN_DNV1	0x391	/* Data Cache Normal Victim 1 */
-#define	SPRN_DNV2	0x392	/* Data Cache Normal Victim 2 */
-#define	SPRN_DNV3	0x393	/* Data Cache Normal Victim 3 */
+#define SPRN_DNV0   0x390   /* Data Cache Normal Victim 0 */
+#define SPRN_DNV1   0x391   /* Data Cache Normal Victim 1 */
+#define SPRN_DNV2   0x392   /* Data Cache Normal Victim 2 */
+#define SPRN_DNV3   0x393   /* Data Cache Normal Victim 3 */
 #endif
-#define SPRN_DSISR	0x012	/* Data Storage Interrupt Status Register */
+#define SPRN_DSISR  0x012   /* Data Storage Interrupt Status Register */
 #ifdef CONFIG_BOOKE
-#define	SPRN_DTV0	0x394	/* Data Cache Transient Victim 0 */
-#define	SPRN_DTV1	0x395	/* Data Cache Transient Victim 1 */
-#define	SPRN_DTV2	0x396	/* Data Cache Transient Victim 2 */
-#define	SPRN_DTV3	0x397	/* Data Cache Transient Victim 3 */
-#define	SPRN_DVLIM	0x398	/* Data Cache Victim Limit */
+#define SPRN_DTV0   0x394   /* Data Cache Transient Victim 0 */
+#define SPRN_DTV1   0x395   /* Data Cache Transient Victim 1 */
+#define SPRN_DTV2   0x396   /* Data Cache Transient Victim 2 */
+#define SPRN_DTV3   0x397   /* Data Cache Transient Victim 3 */
+#define SPRN_DVLIM  0x398   /* Data Cache Victim Limit */
 #endif
-#define SPRN_EAR	0x11A	/* External Address Register */
+#define SPRN_EAR    0x11A   /* External Address Register */
 #ifndef CONFIG_BOOKE
-#define SPRN_ESR	0x3D4	/* Exception Syndrome Register */
+#define SPRN_ESR    0x3D4   /* Exception Syndrome Register */
 #else
-#define SPRN_ESR	0x03E		/* Book E Exception Syndrome Register */
+#define SPRN_ESR    0x03E       /* Book E Exception Syndrome Register */
 #endif /* CONFIG_BOOKE */
-#define   ESR_IMCP	0x80000000	/* Instr. Machine Check - Protection */
-#define   ESR_IMCN	0x40000000	/* Instr. Machine Check - Non-config */
-#define   ESR_IMCB	0x20000000	/* Instr. Machine Check - Bus error */
-#define   ESR_IMCT	0x10000000	/* Instr. Machine Check - Timeout */
-#define   ESR_PIL	0x08000000	/* Program Exception - Illegal */
-#define   ESR_PPR	0x04000000	/* Program Exception - Priveleged */
-#define   ESR_PTR	0x02000000	/* Program Exception - Trap */
-#define   ESR_DST	0x00800000	/* Storage Exception - Data miss */
-#define   ESR_DIZ	0x00400000	/* Storage Exception - Zone fault */
-#define SPRN_EVPR	0x3D6	/* Exception Vector Prefix Register */
-#define SPRN_HASH1	0x3D2	/* Primary Hash Address Register */
-#define SPRN_HASH2	0x3D3	/* Secondary Hash Address Resgister */
-#define SPRN_HID0	0x3F0	/* Hardware Implementation Register 0 */
+#define   ESR_IMCP  0x80000000  /* Instr. Machine Check - Protection */
+#define   ESR_IMCN  0x40000000  /* Instr. Machine Check - Non-config */
+#define   ESR_IMCB  0x20000000  /* Instr. Machine Check - Bus error */
+#define   ESR_IMCT  0x10000000  /* Instr. Machine Check - Timeout */
+#define   ESR_PIL   0x08000000  /* Program Exception - Illegal */
+#define   ESR_PPR   0x04000000  /* Program Exception - Priveleged */
+#define   ESR_PTR   0x02000000  /* Program Exception - Trap */
+#define   ESR_DST   0x00800000  /* Storage Exception - Data miss */
+#define   ESR_DIZ   0x00400000  /* Storage Exception - Zone fault */
+#define SPRN_EVPR   0x3D6   /* Exception Vector Prefix Register */
+#define SPRN_HASH1  0x3D2   /* Primary Hash Address Register */
+#define SPRN_HASH2  0x3D3   /* Secondary Hash Address Resgister */
+#define SPRN_HID0   0x3F0   /* Hardware Implementation Register 0 */
 
-#define HID0_ICE_SHIFT		15
-#define HID0_DCE_SHIFT		14
-#define HID0_DLOCK_SHIFT	12
+#define HID0_ICE_SHIFT      15
+#define HID0_DCE_SHIFT      14
+#define HID0_DLOCK_SHIFT    12
 
-#define   HID0_EMCP	(1<<31)		/* Enable Machine Check pin */
-#define   HID0_EBA	(1<<29)		/* Enable Bus Address Parity */
-#define   HID0_EBD	(1<<28)		/* Enable Bus Data Parity */
-#define   HID0_SBCLK	(1<<27)
-#define   HID0_EICE	(1<<26)
-#define   HID0_ECLK	(1<<25)
-#define   HID0_PAR	(1<<24)
-#define   HID0_DOZE	(1<<23)
-#define   HID0_NAP	(1<<22)
-#define   HID0_SLEEP	(1<<21)
-#define   HID0_DPM	(1<<20)
-#define   HID0_ICE	(1<> 16) & 0xFFFF) /* Version field */
-#define SVR_REV(svr)	(((svr) >>  0) & 0xFFFF) /* Revision field */
+#define SVR_VER(svr)    (((svr) >> 16) & 0xFFFF) /* Version field */
+#define SVR_REV(svr)    (((svr) >>  0) & 0xFFFF) /* Revision field */
 
-#define SVR_CID(svr)	(((svr) >> 28) & 0x0F)	 /* Company or manufacturer ID */
-#define SVR_SOCOP(svr)	(((svr) >> 22) & 0x3F)	 /* SOC integration options */
-#define SVR_SID(svr)	(((svr) >> 16) & 0x3F)	 /* SOC ID */
-#define SVR_PROC(svr)	(((svr) >> 12) & 0x0F)	 /* Process revision field */
-#define SVR_MFG(svr)	(((svr) >>  8) & 0x0F)	 /* Manufacturing revision */
-#define SVR_MJREV(svr)	(((svr) >>  4) & 0x0F)	 /* Major SOC design revision indicator */
-#define SVR_MNREV(svr)	(((svr) >>  0) & 0x0F)	 /* Minor SOC design revision indicator */
+#define SVR_CID(svr)    (((svr) >> 28) & 0x0F)   /* Company or manufacturer ID */
+#define SVR_SOCOP(svr)  (((svr) >> 22) & 0x3F)   /* SOC integration options */
+#define SVR_SID(svr)    (((svr) >> 16) & 0x3F)   /* SOC ID */
+#define SVR_PROC(svr)   (((svr) >> 12) & 0x0F)   /* Process revision field */
+#define SVR_MFG(svr)    (((svr) >>  8) & 0x0F)   /* Manufacturing revision */
+#define SVR_MJREV(svr)  (((svr) >>  4) & 0x0F)   /* Major SOC design revision indicator */
+#define SVR_MNREV(svr)  (((svr) >>  0) & 0x0F)   /* Minor SOC design revision indicator */
 
 /* Processor Version Register */
 
 /* Processor Version Register (PVR) field extraction */
 
-#define PVR_VER(pvr)  (((pvr) >>  16) & 0xFFFF)	/* Version field */
-#define PVR_REV(pvr)  (((pvr) >>   0) & 0xFFFF)	/* Revison field */
+#define PVR_VER(pvr)  (((pvr) >>  16) & 0xFFFF) /* Version field */
+#define PVR_REV(pvr)  (((pvr) >>   0) & 0xFFFF) /* Revison field */
 
 /*
  * AMCC has further subdivided the standard PowerPC 16-bit version and
  * revision subfields of the PVR for the PowerPC 403s into the following:
  */
 
-#define PVR_FAM(pvr)	(((pvr) >> 20) & 0xFFF)	/* Family field */
-#define PVR_MEM(pvr)	(((pvr) >> 16) & 0xF)	/* Member field */
-#define PVR_CORE(pvr)	(((pvr) >> 12) & 0xF)	/* Core field */
-#define PVR_CFG(pvr)	(((pvr) >>  8) & 0xF)	/* Configuration field */
-#define PVR_MAJ(pvr)	(((pvr) >>  4) & 0xF)	/* Major revision field */
-#define PVR_MIN(pvr)	(((pvr) >>  0) & 0xF)	/* Minor revision field */
+#define PVR_FAM(pvr)    (((pvr) >> 20) & 0xFFF) /* Family field */
+#define PVR_MEM(pvr)    (((pvr) >> 16) & 0xF)   /* Member field */
+#define PVR_CORE(pvr)   (((pvr) >> 12) & 0xF)   /* Core field */
+#define PVR_CFG(pvr)    (((pvr) >>  8) & 0xF)   /* Configuration field */
+#define PVR_MAJ(pvr)    (((pvr) >>  4) & 0xF)   /* Major revision field */
+#define PVR_MIN(pvr)    (((pvr) >>  0) & 0xF)   /* Minor revision field */
 
 /* e600 core PVR fields */
 
-#define PVR_E600_VER(pvr)	(((pvr) >> 15) & 0xFFFF) /* Version/type */
-#define PVR_E600_TECH(pvr)	(((pvr) >> 12) & 0xF)	 /* Technology */
-#define PVR_E600_MAJ(pvr)	(((pvr) >> 8) & 0xF)	 /* Major revision */
-#define PVR_E600_MIN(pvr)	(((pvr) >> 0) & 0xFF)	 /* Minor revision */
+#define PVR_E600_VER(pvr)   (((pvr) >> 15) & 0xFFFF) /* Version/type */
+#define PVR_E600_TECH(pvr)  (((pvr) >> 12) & 0xF)    /* Technology */
+#define PVR_E600_MAJ(pvr)   (((pvr) >> 8) & 0xF)     /* Major revision */
+#define PVR_E600_MIN(pvr)   (((pvr) >> 0) & 0xFF)    /* Minor revision */
 
 /* Processor Version Numbers */
 
-#define PVR_403GA	0x00200000
-#define PVR_403GB	0x00200100
-#define PVR_403GC	0x00200200
-#define PVR_403GCX	0x00201400
-#define PVR_405GP	0x40110000
-#define PVR_405GP_RB	0x40110040
-#define PVR_405GP_RC	0x40110082
-#define PVR_405GP_RD	0x401100C4
-#define PVR_405GP_RE	0x40110145  /* same as pc405cr rev c */
-#define PVR_405CR_RA	0x40110041
-#define PVR_405CR_RB	0x401100C5
-#define PVR_405CR_RC	0x40110145  /* same as pc405gp rev e */
-#define PVR_405EP_RA	0x51210950
-#define PVR_405GPR_RB	0x50910951
-#define PVR_405EZ_RA	0x41511460
-#define PVR_405EXR1_RA	0x12911473 /* 405EXr rev A/B with Security */
-#define PVR_405EXR2_RA	0x12911471 /* 405EXr rev A/B without Security */
-#define PVR_405EX1_RA	0x12911477 /* 405EX rev A/B with Security */
-#define PVR_405EX2_RA	0x12911475 /* 405EX rev A/B without Security */
-#define PVR_405EXR1_RC	0x1291147B /* 405EXr rev C with Security */
-#define PVR_405EXR2_RC	0x12911479 /* 405EXr rev C without Security */
-#define PVR_405EX1_RC	0x1291147F /* 405EX rev C with Security */
-#define PVR_405EX2_RC	0x1291147D /* 405EX rev C without Security */
-#define PVR_440GP_RB	0x40120440
-#define PVR_440GP_RC	0x40120481
-#define PVR_440EP_RA	0x42221850
-#define PVR_440EP_RB	0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
-#define PVR_440EP_RC	0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
-#define PVR_440GR_RA	0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
-#define PVR_440GR_RB	0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
-#define PVR_440EPX1_RA	0x216218D0 /* 440EPX rev A with Security / Kasumi */
-#define PVR_440EPX2_RA	0x216218D4 /* 440EPX rev A without Security / Kasumi */
-#define PVR_440GRX1_RA	0x216218D0 /* 440GRX rev A with Security / Kasumi */
-#define PVR_440GRX2_RA	0x216218D4 /* 440GRX rev A without Security / Kasumi */
-#define PVR_440GX_RA	0x51B21850
-#define PVR_440GX_RB	0x51B21851
-#define PVR_440GX_RC	0x51B21892
-#define PVR_440GX_RF	0x51B21894
-#define PVR_405EP_RB	0x51210950
-#define PVR_440SP_6_RAB	0x53221850 /* 440SP rev A&B with RAID 6 support enabled	*/
-#define PVR_440SP_RAB	0x53321850 /* 440SP rev A&B without RAID 6 support	*/
-#define PVR_440SP_6_RC	0x53221891 /* 440SP rev C with RAID 6 support enabled	*/
-#define PVR_440SP_RC	0x53321891 /* 440SP rev C without RAID 6 support	*/
-#define PVR_440SPe_6_RA	0x53421890 /* 440SPe rev A with RAID 6 support enabled	*/
-#define PVR_440SPe_RA	0x53521890 /* 440SPe rev A without RAID 6 support	*/
-#define PVR_440SPe_6_RB	0x53421891 /* 440SPe rev B with RAID 6 support enabled	*/
-#define PVR_440SPe_RB	0x53521891 /* 440SPe rev B without RAID 6 support	*/
-#define PVR_460EX_SE_RA	0x130218A2 /* 460EX rev A with Security Engine	  */
-#define PVR_460EX_RA	0x130218A3 /* 460EX rev A without Security Engine */
-#define PVR_460GT_SE_RA	0x130218A0 /* 460GT rev A with Security Engine	  */
-#define PVR_460GT_RA	0x130218A1 /* 460GT rev A without Security Engine */
+#define PVR_403GA   0x00200000
+#define PVR_403GB   0x00200100
+#define PVR_403GC   0x00200200
+#define PVR_403GCX  0x00201400
+#define PVR_405GP   0x40110000
+#define PVR_405GP_RB    0x40110040
+#define PVR_405GP_RC    0x40110082
+#define PVR_405GP_RD    0x401100C4
+#define PVR_405GP_RE    0x40110145  /* same as pc405cr rev c */
+#define PVR_405CR_RA    0x40110041
+#define PVR_405CR_RB    0x401100C5
+#define PVR_405CR_RC    0x40110145  /* same as pc405gp rev e */
+#define PVR_405EP_RA    0x51210950
+#define PVR_405GPR_RB   0x50910951
+#define PVR_405EZ_RA    0x41511460
+#define PVR_405EXR1_RA  0x12911473 /* 405EXr rev A/B with Security */
+#define PVR_405EXR2_RA  0x12911471 /* 405EXr rev A/B without Security */
+#define PVR_405EX1_RA   0x12911477 /* 405EX rev A/B with Security */
+#define PVR_405EX2_RA   0x12911475 /* 405EX rev A/B without Security */
+#define PVR_405EXR1_RC  0x1291147B /* 405EXr rev C with Security */
+#define PVR_405EXR2_RC  0x12911479 /* 405EXr rev C without Security */
+#define PVR_405EX1_RC   0x1291147F /* 405EX rev C with Security */
+#define PVR_405EX2_RC   0x1291147D /* 405EX rev C without Security */
+#define PVR_440GP_RB    0x40120440
+#define PVR_440GP_RC    0x40120481
+#define PVR_440EP_RA    0x42221850
+#define PVR_440EP_RB    0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
+#define PVR_440EP_RC    0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
+#define PVR_440GR_RA    0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
+#define PVR_440GR_RB    0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
+#define PVR_440EPX1_RA  0x216218D0 /* 440EPX rev A with Security / Kasumi */
+#define PVR_440EPX2_RA  0x216218D4 /* 440EPX rev A without Security / Kasumi */
+#define PVR_440GRX1_RA  0x216218D0 /* 440GRX rev A with Security / Kasumi */
+#define PVR_440GRX2_RA  0x216218D4 /* 440GRX rev A without Security / Kasumi */
+#define PVR_440GX_RA    0x51B21850
+#define PVR_440GX_RB    0x51B21851
+#define PVR_440GX_RC    0x51B21892
+#define PVR_440GX_RF    0x51B21894
+#define PVR_405EP_RB    0x51210950
+#define PVR_440SP_6_RAB 0x53221850 /* 440SP rev A&B with RAID 6 support enabled */
+#define PVR_440SP_RAB   0x53321850 /* 440SP rev A&B without RAID 6 support  */
+#define PVR_440SP_6_RC  0x53221891 /* 440SP rev C with RAID 6 support enabled   */
+#define PVR_440SP_RC    0x53321891 /* 440SP rev C without RAID 6 support    */
+#define PVR_440SPe_6_RA 0x53421890 /* 440SPe rev A with RAID 6 support enabled  */
+#define PVR_440SPe_RA   0x53521890 /* 440SPe rev A without RAID 6 support   */
+#define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled  */
+#define PVR_440SPe_RB   0x53521891 /* 440SPe rev B without RAID 6 support   */
+#define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine    */
+#define PVR_460EX_RA    0x130218A3 /* 460EX rev A without Security Engine */
+#define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine    */
+#define PVR_460GT_RA    0x130218A1 /* 460GT rev A without Security Engine */
 #define PVR_460SX_RA    0x13541800 /* 460SX rev A                   */
 #define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */
 #define PVR_460GX_RA    0x13541802 /* 460GX rev A                   */
 #define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */
-#define PVR_601		0x00010000
-#define PVR_602		0x00050000
-#define PVR_603		0x00030000
-#define PVR_603e	0x00060000
-#define PVR_603ev	0x00070000
-#define PVR_603r	0x00071000
-#define PVR_604		0x00040000
-#define PVR_604e	0x00090000
-#define PVR_604r	0x000A0000
-#define PVR_620		0x00140000
-#define PVR_740		0x00080000
-#define PVR_750		PVR_740
-#define PVR_740P	0x10080000
-#define PVR_750P	PVR_740P
-#define PVR_7400	0x000C0000
-#define PVR_7410	0x800C0000
-#define PVR_7450	0x80000000
+#define PVR_601     0x00010000
+#define PVR_602     0x00050000
+#define PVR_603     0x00030000
+#define PVR_603e    0x00060000
+#define PVR_603ev   0x00070000
+#define PVR_603r    0x00071000
+#define PVR_604     0x00040000
+#define PVR_604e    0x00090000
+#define PVR_604r    0x000A0000
+#define PVR_620     0x00140000
+#define PVR_740     0x00080000
+#define PVR_750     PVR_740
+#define PVR_740P    0x10080000
+#define PVR_750P    PVR_740P
+#define PVR_7400    0x000C0000
+#define PVR_7410    0x800C0000
+#define PVR_7450    0x80000000
 
-#define PVR_85xx	0x80200000
-#define PVR_85xx_REV1	(PVR_85xx | 0x0010)
-#define PVR_85xx_REV2	(PVR_85xx | 0x0020)
+#define PVR_85xx    0x80200000
+#define PVR_85xx_REV1   (PVR_85xx | 0x0010)
+#define PVR_85xx_REV2   (PVR_85xx | 0x0020)
 
-#define PVR_86xx	0x80040000
+#define PVR_86xx    0x80040000
 
 #define PVR_VIRTEX5     0x7ff21912
 
@@ -922,29 +922,29 @@
  * differentiated by the version number in the Communication Processor
  * Module (CPM).
  */
-#define PVR_821		0x00500000
-#define PVR_823		PVR_821
-#define PVR_850		PVR_821
-#define PVR_860		PVR_821
-#define PVR_7400	0x000C0000
-#define PVR_8240	0x00810100
+#define PVR_821     0x00500000
+#define PVR_823     PVR_821
+#define PVR_850     PVR_821
+#define PVR_860     PVR_821
+#define PVR_7400    0x000C0000
+#define PVR_8240    0x00810100
 
 /*
  * PowerQUICC II family processors report different PVR values depending
  * on silicon process (HiP3, HiP4, HiP7, etc.)
  */
-#define PVR_8260	PVR_8240
-#define PVR_8260_HIP3	0x00810101
-#define PVR_8260_HIP4	0x80811014
-#define PVR_8260_HIP7	0x80822011
+#define PVR_8260    PVR_8240
+#define PVR_8260_HIP3   0x00810101
+#define PVR_8260_HIP4   0x80811014
+#define PVR_8260_HIP7   0x80822011
 #define PVR_8260_HIP7R1 0x80822013
-#define PVR_8260_HIP7RA	0x80822014
+#define PVR_8260_HIP7RA 0x80822014
 
 /*
  * MPC 52xx
  */
-#define PVR_5200	0x80822011
-#define PVR_5200B	0x80822014
+#define PVR_5200    0x80822011
+#define PVR_5200B   0x80822014
 
 /*
  * System Version Register
@@ -952,26 +952,26 @@
 
 /* System Version Register (SVR) field extraction */
 
-#define SVR_VER(svr)	(((svr) >>  16) & 0xFFFF)	/* Version field */
-#define SVR_REV(svr)	(((svr) >>   0) & 0xFFFF)	/* Revison field */
+#define SVR_VER(svr)    (((svr) >>  16) & 0xFFFF)   /* Version field */
+#define SVR_REV(svr)    (((svr) >>   0) & 0xFFFF)   /* Revison field */
 
-#define SVR_SUBVER(svr)	(((svr) >>  8) & 0xFF)	/* Process/MFG sub-version */
+#define SVR_SUBVER(svr) (((svr) >>  8) & 0xFF)  /* Process/MFG sub-version */
 
-#define SVR_FAM(svr)	(((svr) >> 20) & 0xFFF)	/* Family field */
-#define SVR_MEM(svr)	(((svr) >> 16) & 0xF)	/* Member field */
+#define SVR_FAM(svr)    (((svr) >> 20) & 0xFFF) /* Family field */
+#define SVR_MEM(svr)    (((svr) >> 16) & 0xF)   /* Member field */
 
-#define SVR_MAJ(svr)	(((svr) >>  4) & 0xF)	/* Major revision field*/
-#define SVR_MIN(svr)	(((svr) >>  0) & 0xF)	/* Minor revision field*/
+#define SVR_MAJ(svr)    (((svr) >>  4) & 0xF)   /* Major revision field*/
+#define SVR_MIN(svr)    (((svr) >>  0) & 0xF)   /* Minor revision field*/
 
 /* Some parts define SVR[0:23] as the SOC version */
-#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF)	/* SOC Version fields */
+#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF)  /* SOC Version fields */
 
 /* whether MPC8xxxE (i.e. has SEC) */
 #if defined(CONFIG_MPC85xx)
-#define IS_E_PROCESSOR(svr)	(svr & 0x80000)
+#define IS_E_PROCESSOR(svr) (svr & 0x80000)
 #else
 #if defined(CONFIG_MPC83xx)
-#define IS_E_PROCESSOR(spridr)	(!(spridr & 0x00010000))
+#define IS_E_PROCESSOR(spridr)  (!(spridr & 0x00010000))
 #endif
 #endif
 
@@ -979,98 +979,98 @@
  * SVR_SOC_VER() Version Values
  */
 
-#define SVR_8533	0x803400
-#define SVR_8533_E	0x803C00
-#define SVR_8535	0x803701
-#define SVR_8535_E	0x803F01
-#define SVR_8536	0x803700
-#define SVR_8536_E	0x803F00
-#define SVR_8540	0x803000
-#define SVR_8541	0x807200
-#define SVR_8541_E	0x807A00
-#define SVR_8543	0x803200
-#define SVR_8543_E	0x803A00
-#define SVR_8544	0x803401
-#define SVR_8544_E	0x803C01
-#define SVR_8545	0x803102
-#define SVR_8545_E	0x803902
-#define SVR_8547_E	0x803901
-#define SVR_8548	0x803100
-#define SVR_8548_E	0x803900
-#define SVR_8555	0x807100
-#define SVR_8555_E	0x807900
-#define SVR_8560	0x807000
-#define SVR_8567	0x807600
-#define SVR_8567_E	0x807E00
-#define SVR_8568	0x807500
-#define SVR_8568_E	0x807D00
-#define SVR_8569	0x808000
-#define SVR_8569_E	0x808800
-#define SVR_8572	0x80E000
-#define SVR_8572_E	0x80E800
-#define SVR_P2020	0x80E200
-#define SVR_P2020_E	0x80EA00
+#define SVR_8533    0x803400
+#define SVR_8533_E  0x803C00
+#define SVR_8535    0x803701
+#define SVR_8535_E  0x803F01
+#define SVR_8536    0x803700
+#define SVR_8536_E  0x803F00
+#define SVR_8540    0x803000
+#define SVR_8541    0x807200
+#define SVR_8541_E  0x807A00
+#define SVR_8543    0x803200
+#define SVR_8543_E  0x803A00
+#define SVR_8544    0x803401
+#define SVR_8544_E  0x803C01
+#define SVR_8545    0x803102
+#define SVR_8545_E  0x803902
+#define SVR_8547_E  0x803901
+#define SVR_8548    0x803100
+#define SVR_8548_E  0x803900
+#define SVR_8555    0x807100
+#define SVR_8555_E  0x807900
+#define SVR_8560    0x807000
+#define SVR_8567    0x807600
+#define SVR_8567_E  0x807E00
+#define SVR_8568    0x807500
+#define SVR_8568_E  0x807D00
+#define SVR_8569    0x808000
+#define SVR_8569_E  0x808800
+#define SVR_8572    0x80E000
+#define SVR_8572_E  0x80E800
+#define SVR_P2020   0x80E200
+#define SVR_P2020_E 0x80EA00
 
-#define SVR_8610	0x80A000
-#define SVR_8641	0x809000
-#define SVR_8641D	0x809001
+#define SVR_8610    0x80A000
+#define SVR_8641    0x809000
+#define SVR_8641D   0x809001
 
 #define _GLOBAL(n)\
-	.globl n;\
+    .globl n;\
 n:
 
 /* Macros for setting and retrieving special purpose registers */
 
-#define stringify(s)	tostring(s)
-#define tostring(s)	#s
+#define stringify(s)    tostring(s)
+#define tostring(s) #s
 
-#define mfdcr(rn)	({unsigned int rval; \
-			asm volatile("mfdcr %0," stringify(rn) \
-				     : "=r" (rval)); rval;})
-#define mtdcr(rn, v)	asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v))
+#define mfdcr(rn)   ({unsigned int rval; \
+            asm volatile("mfdcr %0," stringify(rn) \
+                     : "=r" (rval)); rval;})
+#define mtdcr(rn, v)    asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v))
 
-#define mfmsr()		({unsigned int rval; \
-			asm volatile("mfmsr %0" : "=r" (rval)); rval;})
-#define mtmsr(v)	asm volatile("mtmsr %0" : : "r" (v))
+#define mfmsr()     ({unsigned int rval; \
+            asm volatile("mfmsr %0" : "=r" (rval)); rval;})
+#define mtmsr(v)    asm volatile("mtmsr %0" : : "r" (v))
 
-#define mfspr(rn)	({unsigned int rval; \
-			asm volatile("mfspr %0," stringify(rn) \
-				     : "=r" (rval)); rval;})
-#define mtspr(rn, v)	asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v))
+#define mfspr(rn)   ({unsigned int rval; \
+            asm volatile("mfspr %0," stringify(rn) \
+                     : "=r" (rval)); rval;})
+#define mtspr(rn, v)    asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v))
 
-#define tlbie(v)	asm volatile("tlbie %0 \n sync" : : "r" (v))
+#define tlbie(v)    asm volatile("tlbie %0 \n sync" : : "r" (v))
 
 /* Segment Registers */
 
-#define SR0	0
-#define SR1	1
-#define SR2	2
-#define SR3	3
-#define SR4	4
-#define SR5	5
-#define SR6	6
-#define SR7	7
-#define SR8	8
-#define SR9	9
-#define SR10	10
-#define SR11	11
-#define SR12	12
-#define SR13	13
-#define SR14	14
-#define SR15	15
+#define SR0 0
+#define SR1 1
+#define SR2 2
+#define SR3 3
+#define SR4 4
+#define SR5 5
+#define SR6 6
+#define SR7 7
+#define SR8 8
+#define SR9 9
+#define SR10    10
+#define SR11    11
+#define SR12    12
+#define SR13    13
+#define SR14    14
+#define SR15    15
 
 #ifndef __ASSEMBLY__
 
 struct cpu_type {
-	char name[15];
-	u32 soc_ver;
+    char name[15];
+    u32 soc_ver;
 };
 
 struct cpu_type *identify_cpu(u32 ver);
 
 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
 #define CPU_TYPE_ENTRY(n, v) \
-	{ .name = #n, .soc_ver = SVR_##v, }
+    { .name = #n, .soc_ver = SVR_##v, }
 #else
 #if defined(CONFIG_MPC83xx)
 #define CPU_TYPE_ENTRY(x) {#x, SPR_##x}
@@ -1120,65 +1120,65 @@ extern struct task_struct *last_task_used_altivec;
  * as soon as I get around to remapping the io areas with the BATs
  * to match the mac we can raise this. -- Cort
  */
-#define TASK_SIZE	(0x80000000UL)
+#define TASK_SIZE   (0x80000000UL)
 
 /* This decides where the kernel will search for a free chunk of vm
  * space during mmap's.
  */
-#define TASK_UNMAPPED_BASE	(TASK_SIZE / 8 * 3)
+#define TASK_UNMAPPED_BASE  (TASK_SIZE / 8 * 3)
 
 typedef struct {
-	unsigned long seg;
+    unsigned long seg;
 } mm_segment_t;
 
 struct thread_struct {
-	unsigned long	ksp;		/* Kernel stack pointer */
-	unsigned long	wchan;		/* Event task is sleeping on */
-	struct pt_regs	*regs;		/* Pointer to saved register state */
-	mm_segment_t	fs;		/* for get_fs() validation */
-	void		*pgdir;		/* root of page-table tree */
-	signed long	last_syscall;
-	double		fpr[32];	/* Complete floating point set */
-	unsigned long	fpscr_pad;	/* fpr ... fpscr must be contiguous */
-	unsigned long	fpscr;		/* Floating point status */
+    unsigned long   ksp;        /* Kernel stack pointer */
+    unsigned long   wchan;      /* Event task is sleeping on */
+    struct pt_regs  *regs;      /* Pointer to saved register state */
+    mm_segment_t    fs;     /* for get_fs() validation */
+    void        *pgdir;     /* root of page-table tree */
+    signed long last_syscall;
+    double      fpr[32];    /* Complete floating point set */
+    unsigned long   fpscr_pad;  /* fpr ... fpscr must be contiguous */
+    unsigned long   fpscr;      /* Floating point status */
 #ifdef CONFIG_ALTIVEC
-	vector128	vr[32];		/* Complete AltiVec set */
-	vector128	vscr;		/* AltiVec status */
-	unsigned long	vrsave;
+    vector128   vr[32];     /* Complete AltiVec set */
+    vector128   vscr;       /* AltiVec status */
+    unsigned long   vrsave;
 #endif /* CONFIG_ALTIVEC */
 };
 
-#define INIT_SP		(sizeof(init_stack) + (unsigned long) &init_stack)
+#define INIT_SP     (sizeof(init_stack) + (unsigned long) &init_stack)
 
 #define INIT_THREAD  { \
-	INIT_SP, /* ksp */ \
-	0, /* wchan */ \
-	(struct pt_regs *)INIT_SP - 1, /* regs */ \
-	KERNEL_DS, /*fs*/ \
-	swapper_pg_dir, /* pgdir */ \
-	0, /* last_syscall */ \
-	{0}, 0, 0 \
+    INIT_SP, /* ksp */ \
+    0, /* wchan */ \
+    (struct pt_regs *)INIT_SP - 1, /* regs */ \
+    KERNEL_DS, /*fs*/ \
+    swapper_pg_dir, /* pgdir */ \
+    0, /* last_syscall */ \
+    {0}, 0, 0 \
 }
 
 /*
  * Note: the vm_start and vm_end fields here should *not*
- * be in kernel space.	(Could vm_end == vm_start perhaps?)
+ * be in kernel space.  (Could vm_end == vm_start perhaps?)
  */
 #define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \
-		    PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \
-		    1, NULL, NULL }
+            PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \
+            1, NULL, NULL }
 
 /*
  * Return saved PC of a blocked thread. For now, this is the "user" PC
  */
 static inline unsigned long thread_saved_pc(struct thread_struct *t)
 {
-	return (t->regs) ? t->regs->nip : 0;
+    return (t->regs) ? t->regs->nip : 0;
 }
 
-#define copy_segments(tsk, mm)		do { } while (0)
-#define release_segments(mm)		do { } while (0)
-#define forget_segments()		do { } while (0)
+#define copy_segments(tsk, mm)      do { } while (0)
+#define release_segments(mm)        do { } while (0)
+#define forget_segments()       do { } while (0)
 
 unsigned long get_wchan(struct task_struct *p);
 
@@ -1190,16 +1190,16 @@ unsigned long get_wchan(struct task_struct *p);
  */
 #define THREAD_SIZE (2*PAGE_SIZE)
 #define alloc_task_struct() \
-	((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
-#define free_task_struct(p)	free_pages((unsigned long)(p),1)
-#define get_task_struct(tsk)	  atomic_inc(&mem_map[MAP_NR(tsk)].count)
+    ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
+#define free_task_struct(p) free_pages((unsigned long)(p),1)
+#define get_task_struct(tsk)      atomic_inc(&mem_map[MAP_NR(tsk)].count)
 
 /* in process.c - for early bootup debug -- Cort */
 int ll_printk(const char *, ...);
 void ll_puts(const char *);
 
-#define init_task	(init_task_union.task)
-#define init_stack	(init_task_union.stack)
+#define init_task   (init_task_union.task)
+#define init_stack  (init_task_union.stack)
 
 /* In misc.c */
 void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
@@ -1212,7 +1212,7 @@ void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
 #define have_of 0
 #elif defined(CONFIG_OAK)
 #define _machine _MACH_oak
-#define have_of	0
+#define have_of 0
 #elif defined(CONFIG_WALNUT)
 #define _machine _MACH_walnut
 #define have_of 0
diff --git a/libcpu/ppc/ppc405/include/asm/ptrace.h b/libcpu/ppc/ppc405/include/asm/ptrace.h
index d531de889b..d450803f96 100644
--- a/libcpu/ppc/ppc405/include/asm/ptrace.h
+++ b/libcpu/ppc/ppc405/include/asm/ptrace.h
@@ -26,27 +26,27 @@
 #define PPC_REG unsigned long
 #endif
 struct pt_regs {
-	PPC_REG gpr[32];
-	PPC_REG nip;
-	PPC_REG msr;
-	PPC_REG orig_gpr3;	/* Used for restarting system calls */
-	PPC_REG ctr;
-	PPC_REG link;
-	PPC_REG xer;
-	PPC_REG ccr;
-	PPC_REG mq;		/* 601 only (not used at present) */
-				    /* Used on APUS to hold IPL value. */
-	PPC_REG trap;		/* Reason for being here */
-	PPC_REG dar;		/* Fault registers */
-	PPC_REG dsisr;
-	PPC_REG result;		/* Result of a system call */
+    PPC_REG gpr[32];
+    PPC_REG nip;
+    PPC_REG msr;
+    PPC_REG orig_gpr3;  /* Used for restarting system calls */
+    PPC_REG ctr;
+    PPC_REG link;
+    PPC_REG xer;
+    PPC_REG ccr;
+    PPC_REG mq;     /* 601 only (not used at present) */
+                    /* Used on APUS to hold IPL value. */
+    PPC_REG trap;       /* Reason for being here */
+    PPC_REG dar;        /* Fault registers */
+    PPC_REG dsisr;
+    PPC_REG result;     /* Result of a system call */
 }__attribute__((packed)) CELL_STACK_FRAME_t;
 #endif
 
-#define STACK_FRAME_OVERHEAD	16	/* size of minimum stack frame */
+#define STACK_FRAME_OVERHEAD    16  /* size of minimum stack frame */
 
 /* Size of stack frame allocated when calling signal handler. */
-#define __SIGNAL_FRAMESIZE	64
+#define __SIGNAL_FRAMESIZE  64
 
 #define instruction_pointer(regs) ((regs)->nip)
 #define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
@@ -56,51 +56,51 @@ struct pt_regs {
  * These can't be changed without breaking binary compatibility
  * with MkLinux, etc.
  */
-#define PT_R0	0
-#define PT_R1	1
-#define PT_R2	2
-#define PT_R3	3
-#define PT_R4	4
-#define PT_R5	5
-#define PT_R6	6
-#define PT_R7	7
-#define PT_R8	8
-#define PT_R9	9
-#define PT_R10	10
-#define PT_R11	11
-#define PT_R12	12
-#define PT_R13	13
-#define PT_R14	14
-#define PT_R15	15
-#define PT_R16	16
-#define PT_R17	17
-#define PT_R18	18
-#define PT_R19	19
-#define PT_R20	20
-#define PT_R21	21
-#define PT_R22	22
-#define PT_R23	23
-#define PT_R24	24
-#define PT_R25	25
-#define PT_R26	26
-#define PT_R27	27
-#define PT_R28	28
-#define PT_R29	29
-#define PT_R30	30
-#define PT_R31	31
+#define PT_R0   0
+#define PT_R1   1
+#define PT_R2   2
+#define PT_R3   3
+#define PT_R4   4
+#define PT_R5   5
+#define PT_R6   6
+#define PT_R7   7
+#define PT_R8   8
+#define PT_R9   9
+#define PT_R10  10
+#define PT_R11  11
+#define PT_R12  12
+#define PT_R13  13
+#define PT_R14  14
+#define PT_R15  15
+#define PT_R16  16
+#define PT_R17  17
+#define PT_R18  18
+#define PT_R19  19
+#define PT_R20  20
+#define PT_R21  21
+#define PT_R22  22
+#define PT_R23  23
+#define PT_R24  24
+#define PT_R25  25
+#define PT_R26  26
+#define PT_R27  27
+#define PT_R28  28
+#define PT_R29  29
+#define PT_R30  30
+#define PT_R31  31
 
-#define PT_NIP	32
-#define PT_MSR	33
+#define PT_NIP  32
+#define PT_MSR  33
 #ifdef __KERNEL__
 #define PT_ORIG_R3 34
 #endif
-#define PT_CTR	35
-#define PT_LNK	36
-#define PT_XER	37
-#define PT_CCR	38
-#define PT_MQ	39
+#define PT_CTR  35
+#define PT_LNK  36
+#define PT_XER  37
+#define PT_CCR  38
+#define PT_MQ   39
 
-#define PT_FPR0	48	/* each FP reg occupies 2 slots in this space */
+#define PT_FPR0 48  /* each FP reg occupies 2 slots in this space */
 #define PT_FPR31 (PT_FPR0 + 2*31)
 #define PT_FPSCR (PT_FPR0 + 2*32 + 1)
 
diff --git a/libcpu/ppc/ppc405/include/asm/types.h b/libcpu/ppc/ppc405/include/asm/types.h
index 6413895325..88c38e62cc 100644
--- a/libcpu/ppc/ppc405/include/asm/types.h
+++ b/libcpu/ppc/ppc405/include/asm/types.h
@@ -27,7 +27,7 @@ __extension__ typedef unsigned long long __u64;
 #endif
 
 typedef struct {
-	__u32 u[4];
+    __u32 u[4];
 } __attribute__((aligned(16))) vector128;
 
 #ifdef __KERNEL__
diff --git a/libcpu/ppc/ppc405/include/config.h b/libcpu/ppc/ppc405/include/config.h
index dc01549b01..d464a3e371 100644
--- a/libcpu/ppc/ppc405/include/config.h
+++ b/libcpu/ppc/ppc405/include/config.h
@@ -1,25 +1,25 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_405EP		1	/* this is a PPC405 CPU */
-#define CONFIG_4xx		1	/*  member of PPC4xx family */
+#define CONFIG_405EP        1   /* this is a PPC405 CPU */
+#define CONFIG_4xx      1   /*  member of PPC4xx family */
 
-#define CONFIG_SYS_DCACHE_SIZE	(16 << 10)/* For AMCC 405 CPUs	*/
-#define CONFIG_SYS_SDRAM_BASE	0x00000000	/* _must_ be 0		*/
+#define CONFIG_SYS_DCACHE_SIZE  (16 << 10)/* For AMCC 405 CPUs  */
+#define CONFIG_SYS_SDRAM_BASE   0x00000000  /* _must_ be 0      */
 
-#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size	*/
-#define CONFIG_SYS_PROMPT	"=> "	/* Monitor Command Prompt	*/
-#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_CBSIZE   256 /* Console I/O Buffer Size  */
+#define CONFIG_SYS_PROMPT   "=> "   /* Monitor Command Prompt   */
+#define CONFIG_SYS_PBSIZE   (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 
-#define CONFIG_SYS_CLK_RECFG	0	/* Config the sys clks */
+#define CONFIG_SYS_CLK_RECFG    0   /* Config the sys clks */
 #define CONFIG_SYS_CLK_FREQ     33333333 /*3300000*//* external frequency to pll   */
 #define CONFIG_SYS_HZ           100
-#define CONFIG_SYS_PIT_RELOAD   (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ)  
+#define CONFIG_SYS_PIT_RELOAD   (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ)
 
 /*
  * UART
  */
-#define CONFIG_BAUDRATE		115200
+#define CONFIG_BAUDRATE     115200
 #define CONFIG_SERIAL_MULTI
 #define CONFIG_SYS_BAUDRATE_TABLE  \
     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
@@ -33,26 +33,26 @@
  * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
  * set Linux BASE_BAUD to 403200.
  */
-#define CONFIG_SYS_BASE_BAUD		691200
-#define CONFIG_UART1_CONSOLE		1
+#define CONFIG_SYS_BASE_BAUD        691200
+#define CONFIG_UART1_CONSOLE        1
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
  */
-#define CONFIG_SYS_FLASH_BASE		0xFFE00000
+#define CONFIG_SYS_FLASH_BASE       0xFFE00000
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS  2   /* max number of memory banks       */
+#define CONFIG_SYS_MAX_FLASH_SECT   256 /* max number of sectors on one chip    */
 
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000  /* Timeout for Flash Erase (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms)  */
 
 #define CONFIG_SYS_FLASH_ADDR0         0x555
 #define CONFIG_SYS_FLASH_ADDR1         0x2aa
 #define CONFIG_SYS_FLASH_WORD_SIZE     unsigned short
 
-#endif	/* __CONFIG_H */
+#endif  /* __CONFIG_H */
diff --git a/libcpu/ppc/ppc405/interrupt.c b/libcpu/ppc/ppc405/interrupt.c
index 27a528e2f0..f072dd07e1 100644
--- a/libcpu/ppc/ppc405/interrupt.c
+++ b/libcpu/ppc/ppc405/interrupt.c
@@ -28,18 +28,18 @@ rt_uint32_t rt_thread_switch_interrput_flag;
 
 rt_isr_handler_t rt_hw_interrupt_handler(rt_uint32_t vector, void* param)
 {
-	rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
-	return RT_NULL;
+    rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+    return RT_NULL;
 }
 
 void uic_irq_ack(unsigned int vec)
 {
-	mtdcr(uic0sr, UIC_MASK(vec));
+    mtdcr(uic0sr, UIC_MASK(vec));
 }
 
 void  uic_int_handler (unsigned int vec)
 {
-	rt_interrupt_enter();
+    rt_interrupt_enter();
 
     /* Allow external interrupts to the CPU. */
     if (isr_table [vec].handler != 0)
@@ -47,91 +47,91 @@ void  uic_int_handler (unsigned int vec)
        (*isr_table[vec].handler)(vec, isr_table[vec].param);
     }
     uic_irq_ack(vec);
-	
+
     rt_interrupt_leave();
 }
 
 /* handler for UIC interrupt */
 void uic_interrupt(rt_uint32_t uic_base, int vec_base)
 {
-	int vec;
-	rt_uint32_t uic_msr;
-	rt_uint32_t msr_shift;
+    int vec;
+    rt_uint32_t uic_msr;
+    rt_uint32_t msr_shift;
 
-	/*
-	 * Read masked interrupt status register to determine interrupt source
-	 */
-	uic_msr = get_dcr(uic_base + UIC_MSR);
-	msr_shift = uic_msr;
-	vec = vec_base;
+    /*
+     * Read masked interrupt status register to determine interrupt source
+     */
+    uic_msr = get_dcr(uic_base + UIC_MSR);
+    msr_shift = uic_msr;
+    vec = vec_base;
 
-	while (msr_shift != 0)
-	{
-		if (msr_shift & 0x80000000)
-			uic_int_handler(vec);
+    while (msr_shift != 0)
+    {
+        if (msr_shift & 0x80000000)
+            uic_int_handler(vec);
 
-		/*
-		 * Shift msr to next position and increment vector
-		 */
-		msr_shift <<= 1;
-		vec++;
-	}
+        /*
+         * Shift msr to next position and increment vector
+         */
+        msr_shift <<= 1;
+        vec++;
+    }
 }
 
-rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, 
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler,
     void* param, const char* name)
 {
-    int	intVal;
+    int intVal;
     rt_isr_handler_t old_handler;
 
-    if (((int)vector < 0)  || ((int) vector >= MAX_HANDLERS)) 
-	{
+    if (((int)vector < 0)  || ((int) vector >= MAX_HANDLERS))
+    {
         return RT_NULL;   /*  out of range  */
-	}
-   
+    }
+
     /* install the handler in the system interrupt table  */
     intVal = rt_hw_interrupt_disable (); /* lock interrupts to prevent races */
 
     old_handler = isr_table[vector].handler;
     isr_table[vector].handler = new_handler;
     isr_table[vector].param = param;
-    
+
     rt_hw_interrupt_enable (intVal);
 }
 
 void rt_hw_interrupt_mask(int vector)
 {
-	mtdcr(uic0er, mfdcr(uic0er) & ~UIC_MASK(vector));
+    mtdcr(uic0er, mfdcr(uic0er) & ~UIC_MASK(vector));
 }
 
 void rt_hw_interrupt_unmask(int vector)
 {
-	mtdcr(uic0er, mfdcr(uic0er) | UIC_MASK(vector));
+    mtdcr(uic0er, mfdcr(uic0er) | UIC_MASK(vector));
 }
 
 void rt_hw_interrupt_init()
 {
-	int vector;
+    int vector;
     rt_uint32_t pit_value;
 
     pit_value = RT_TICK_PER_SECOND * (100000000 / RT_CPU_FREQ);
 
     /* enable pit */
-	mtspr(SPRN_PIT, pit_value);
-	mtspr(SPRN_TCR, 0x4400000);
+    mtspr(SPRN_PIT, pit_value);
+    mtspr(SPRN_TCR, 0x4400000);
 
-	/* set default interrupt handler */
+    /* set default interrupt handler */
     for (vector = 0; vector < MAX_HANDLERS; vector++)
     {
-	    isr_table [vector].handler = (rt_isr_handler_t)rt_hw_interrupt_handler;
+        isr_table [vector].handler = (rt_isr_handler_t)rt_hw_interrupt_handler;
         isr_table [vector].param = RT_NULL;
     }
 
-	/* initialize interrupt nest, and context in thread sp */
-	rt_interrupt_nest = 0;
-	rt_interrupt_from_thread = 0;
-	rt_interrupt_to_thread = 0;
-	rt_thread_switch_interrput_flag = 0;
+    /* initialize interrupt nest, and context in thread sp */
+    rt_interrupt_nest = 0;
+    rt_interrupt_from_thread = 0;
+    rt_interrupt_to_thread = 0;
+    rt_thread_switch_interrput_flag = 0;
 }
 
 /*@}*/
diff --git a/libcpu/ppc/ppc405/io.h b/libcpu/ppc/ppc405/io.h
index 32fcd56307..28341ead64 100644
--- a/libcpu/ppc/ppc405/io.h
+++ b/libcpu/ppc/ppc405/io.h
@@ -12,82 +12,82 @@
  */
 static inline int in_8(const volatile unsigned char __iomem *addr)
 {
-	int ret;
+    int ret;
 
-	__asm__ __volatile__(
-		"sync; lbz%U1%X1 %0,%1;\n"
-		"twi 0,%0,0;\n"
-		"isync" : "=r" (ret) : "m" (*addr));
-	return ret;
+    __asm__ __volatile__(
+        "sync; lbz%U1%X1 %0,%1;\n"
+        "twi 0,%0,0;\n"
+        "isync" : "=r" (ret) : "m" (*addr));
+    return ret;
 }
 
 static inline void out_8(volatile unsigned char __iomem *addr, int val)
 {
-	__asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
+    __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
 }
 
 extern inline int in_le16(const volatile unsigned short __iomem *addr)
 {
-	int ret;
+    int ret;
 
-	__asm__ __volatile__("sync; lhbrx %0,0,%1;\n"
-			     "twi 0,%0,0;\n"
-			     "isync" : "=r" (ret) :
-			      "r" (addr), "m" (*addr));
-	return ret;
+    __asm__ __volatile__("sync; lhbrx %0,0,%1;\n"
+                 "twi 0,%0,0;\n"
+                 "isync" : "=r" (ret) :
+                  "r" (addr), "m" (*addr));
+    return ret;
 }
 
 extern inline int in_be16(const volatile unsigned short __iomem *addr)
 {
-	int ret;
+    int ret;
 
-	__asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n"
-			     "twi 0,%0,0;\n"
-			     "isync" : "=r" (ret) : "m" (*addr));
-	return ret;
+    __asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n"
+                 "twi 0,%0,0;\n"
+                 "isync" : "=r" (ret) : "m" (*addr));
+    return ret;
 }
 
 extern inline void out_le16(volatile unsigned short __iomem *addr, int val)
 {
-	__asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
-			      "r" (val), "r" (addr));
+    __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
+                  "r" (val), "r" (addr));
 }
 
 extern inline void out_be16(volatile unsigned short __iomem *addr, int val)
 {
-	__asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
+    __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
 }
 
 extern inline unsigned in_le32(const volatile unsigned __iomem *addr)
 {
-	unsigned ret;
+    unsigned ret;
 
-	__asm__ __volatile__("sync; lwbrx %0,0,%1;\n"
-			     "twi 0,%0,0;\n"
-			     "isync" : "=r" (ret) :
-			     "r" (addr), "m" (*addr));
-	return ret;
+    __asm__ __volatile__("sync; lwbrx %0,0,%1;\n"
+                 "twi 0,%0,0;\n"
+                 "isync" : "=r" (ret) :
+                 "r" (addr), "m" (*addr));
+    return ret;
 }
 
 extern inline unsigned in_be32(const volatile unsigned __iomem *addr)
 {
-	unsigned ret;
+    unsigned ret;
 
-	__asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n"
-			     "twi 0,%0,0;\n"
-			     "isync" : "=r" (ret) : "m" (*addr));
-	return ret;
+    __asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n"
+                 "twi 0,%0,0;\n"
+                 "isync" : "=r" (ret) : "m" (*addr));
+    return ret;
 }
 
 extern inline void out_le32(volatile unsigned __iomem *addr, int val)
 {
-	__asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
-			     "r" (val), "r" (addr));
+    __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
+                 "r" (val), "r" (addr));
 }
 
 extern inline void out_be32(volatile unsigned __iomem *addr, int val)
 {
-	__asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
+    __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
 }
 
 #endif
diff --git a/libcpu/ppc/ppc405/serial.c b/libcpu/ppc/ppc405/serial.c
index ac68a13748..1fc9039769 100644
--- a/libcpu/ppc/ppc405/serial.c
+++ b/libcpu/ppc/ppc405/serial.c
@@ -12,18 +12,18 @@
 #define UCR1_UDIV_POS   8
 #define UDIV_MAX        127
 
-#define UART_RBR		0x00
-#define UART_THR		0x00
-#define UART_IER		0x01
-#define UART_IIR		0x02
-#define UART_FCR		0x02
-#define UART_LCR		0x03
-#define UART_MCR		0x04
-#define UART_LSR		0x05
-#define UART_MSR		0x06
-#define UART_SCR		0x07
-#define UART_DLL		0x00
-#define UART_DLM		0x01
+#define UART_RBR        0x00
+#define UART_THR        0x00
+#define UART_IER        0x01
+#define UART_IIR        0x02
+#define UART_FCR        0x02
+#define UART_LCR        0x03
+#define UART_MCR        0x04
+#define UART_LSR        0x05
+#define UART_MSR        0x06
+#define UART_SCR        0x07
+#define UART_DLL        0x00
+#define UART_DLM        0x01
 
 /*-----------------------------------------------------------------------------+
   | Line Status Register.
@@ -40,280 +40,280 @@
 /* PPC405 serial device */
 struct rt_ppc405_serial
 {
-	/* inherit from device */
-	struct rt_device parent;
+    /* inherit from device */
+    struct rt_device parent;
 
-	rt_uint32_t hw_base;
-	rt_uint32_t irqno;
-	rt_uint32_t baudrate;
+    rt_uint32_t hw_base;
+    rt_uint32_t irqno;
+    rt_uint32_t baudrate;
 
-	/* reception field */
-	rt_uint16_t save_index, read_index;
-	rt_uint8_t  rx_buffer[RT_UART_RX_BUFFER_SIZE];
+    /* reception field */
+    rt_uint16_t save_index, read_index;
+    rt_uint8_t  rx_buffer[RT_UART_RX_BUFFER_SIZE];
 };
 struct rt_ppc405_serial ppc405_serial;
 
 /* serial character device */
 static rt_err_t rt_serial_init (rt_device_t dev)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
 {
-	struct rt_ppc405_serial* device;
-	device = (struct rt_ppc405_serial*) dev;
-	
-	RT_ASSERT(device != RT_NULL);
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* Enable "RX Data Available" Interrupt on UART */
-		out_8((rt_uint8_t*)device->hw_base + UART_IER, 0x01);
-		/* Setup UART FIFO: RX trigger level: 1 byte, Enable FIFO */
-		out_8((rt_uint8_t*)device->hw_base + UART_FCR, 1);
+    struct rt_ppc405_serial* device;
+    device = (struct rt_ppc405_serial*) dev;
 
-	    /* init UART rx interrupt */
-	    rt_hw_interrupt_unmask(device->irqno);
-	}
+    RT_ASSERT(device != RT_NULL);
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* Enable "RX Data Available" Interrupt on UART */
+        out_8((rt_uint8_t*)device->hw_base + UART_IER, 0x01);
+        /* Setup UART FIFO: RX trigger level: 1 byte, Enable FIFO */
+        out_8((rt_uint8_t*)device->hw_base + UART_FCR, 1);
 
-	return RT_EOK;
+        /* init UART rx interrupt */
+        rt_hw_interrupt_unmask(device->irqno);
+    }
+
+    return RT_EOK;
 }
 
 static rt_err_t rt_serial_close(rt_device_t dev)
 {
-	struct rt_ppc405_serial* device;
-	device = (struct rt_ppc405_serial*) dev;
-	
-	RT_ASSERT(device != RT_NULL);
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* mask UART rx interrupt */
-	    rt_hw_interrupt_mask(device->irqno);
-	}
+    struct rt_ppc405_serial* device;
+    device = (struct rt_ppc405_serial*) dev;
 
-	return RT_EOK;
+    RT_ASSERT(device != RT_NULL);
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* mask UART rx interrupt */
+        rt_hw_interrupt_mask(device->irqno);
+    }
+
+    return RT_EOK;
 }
 
 static rt_err_t rt_serial_control(rt_device_t dev, int cmd, void *args)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
 {
-	rt_uint8_t* ptr;
-	struct rt_ppc405_serial* device;
+    rt_uint8_t* ptr;
+    struct rt_ppc405_serial* device;
 
-	device = (struct rt_ppc405_serial*) dev;
-	RT_ASSERT(device != RT_NULL);
+    device = (struct rt_ppc405_serial*) dev;
+    RT_ASSERT(device != RT_NULL);
 
-	/* point to buffer */
-	ptr = (rt_uint8_t*) buffer;
+    /* point to buffer */
+    ptr = (rt_uint8_t*) buffer;
 
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		while (size)
-		{
-			/* interrupt receive */
-			rt_base_t level;
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        while (size)
+        {
+            /* interrupt receive */
+            rt_base_t level;
 
-			/* disable interrupt */
-			level = rt_hw_interrupt_disable();
-			if (device->read_index != device->save_index)
-			{
-				*ptr = device->rx_buffer[device->read_index];
+            /* disable interrupt */
+            level = rt_hw_interrupt_disable();
+            if (device->read_index != device->save_index)
+            {
+                *ptr = device->rx_buffer[device->read_index];
 
-				device->read_index ++;
-				if (device->read_index >= RT_UART_RX_BUFFER_SIZE)
-					device->read_index = 0;
-			}
-			else
-			{
-				/* no data in rx buffer */
+                device->read_index ++;
+                if (device->read_index >= RT_UART_RX_BUFFER_SIZE)
+                    device->read_index = 0;
+            }
+            else
+            {
+                /* no data in rx buffer */
 
-				/* enable interrupt */
-				rt_hw_interrupt_enable(level);
-				break;
-			}
+                /* enable interrupt */
+                rt_hw_interrupt_enable(level);
+                break;
+            }
 
-			/* enable interrupt */
-			rt_hw_interrupt_enable(level);
+            /* enable interrupt */
+            rt_hw_interrupt_enable(level);
 
-			ptr ++; size --;
-		}
+            ptr ++; size --;
+        }
 
-		return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-	}
-	else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
-	{
-		/* not support right now */
-		RT_ASSERT(0);
-	}
+        return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+    }
+    else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
+    {
+        /* not support right now */
+        RT_ASSERT(0);
+    }
 
-	/* polling mode */
-	RT_ASSERT(0);
+    /* polling mode */
+    RT_ASSERT(0);
 
-	return (rt_size_t)ptr - (rt_size_t)buffer;
+    return (rt_size_t)ptr - (rt_size_t)buffer;
 }
 
 static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
 {
-	char *ptr;
-	struct rt_ppc405_serial* device;
+    char *ptr;
+    struct rt_ppc405_serial* device;
 
-	device = (struct rt_ppc405_serial*) dev;
-	RT_ASSERT(device != RT_NULL);
+    device = (struct rt_ppc405_serial*) dev;
+    RT_ASSERT(device != RT_NULL);
 
-	if (dev->flag & RT_DEVICE_FLAG_INT_TX)
-	{
-		/* not support */
-		RT_ASSERT(0);
-	}
-	else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
-	{
-		/* not support */
-		RT_ASSERT(0);
-	}
+    if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+    {
+        /* not support */
+        RT_ASSERT(0);
+    }
+    else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
+    {
+        /* not support */
+        RT_ASSERT(0);
+    }
 
-	/* polling write */
-	ptr = (char *)buffer;
-	
-	if (dev->flag & RT_DEVICE_FLAG_STREAM)
-	{
-		/* stream mode */
-		while (size)
-		{
-			if (*ptr == '\n')
-			{
-				while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20);
-				out_8((rt_uint8_t*)device->hw_base + UART_THR, '\r');
-			}
+    /* polling write */
+    ptr = (char *)buffer;
 
-			while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20);
-			out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr);
+    if (dev->flag & RT_DEVICE_FLAG_STREAM)
+    {
+        /* stream mode */
+        while (size)
+        {
+            if (*ptr == '\n')
+            {
+                while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20);
+                out_8((rt_uint8_t*)device->hw_base + UART_THR, '\r');
+            }
 
-			ptr ++;
-			size --;
-		}
-	}
-	else
-	{
-		while (size)
-		{
-			while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20);
-			out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr);
-			
-			ptr ++;
-			size --;
-		}
-	}
-	
-	return (rt_size_t) ptr - (rt_size_t) buffer;
+            while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20);
+            out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr);
+
+            ptr ++;
+            size --;
+        }
+    }
+    else
+    {
+        while (size)
+        {
+            while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20);
+            out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr);
+
+            ptr ++;
+            size --;
+        }
+    }
+
+    return (rt_size_t) ptr - (rt_size_t) buffer;
 }
 
 void rt_serial_set_baudrate(struct rt_ppc405_serial* device)
 {
-	rt_uint32_t bdiv;
+    rt_uint32_t bdiv;
 
-	bdiv = 115200;
-	out_8((rt_uint8_t *)device->hw_base + UART_DLL, bdiv);		/* set baudrate divisor */
-	out_8((rt_uint8_t *)device->hw_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
+    bdiv = 115200;
+    out_8((rt_uint8_t *)device->hw_base + UART_DLL, bdiv);      /* set baudrate divisor */
+    out_8((rt_uint8_t *)device->hw_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
 }
 
 void rt_serial_isr(int irqno, void* param)
 {
-	unsigned char status;
-	struct rt_ppc405_serial *device;
+    unsigned char status;
+    struct rt_ppc405_serial *device;
 
-	device = (struct rt_ppc405_serial*) param;
-	status = in_8((rt_uint8_t *)device->hw_base + UART_LSR);
+    device = (struct rt_ppc405_serial*) param;
+    status = in_8((rt_uint8_t *)device->hw_base + UART_LSR);
 
-	if (status & 0x01)
-	{
-		rt_base_t level;
+    if (status & 0x01)
+    {
+        rt_base_t level;
 
-		while (status & 0x01)
-		{
-			/* disable interrupt */
-			level = rt_hw_interrupt_disable();
+        while (status & 0x01)
+        {
+            /* disable interrupt */
+            level = rt_hw_interrupt_disable();
 
-			/* read character */
-			device->rx_buffer[device->save_index] = (0xff & (int) in_8((rt_uint8_t *)device->hw_base));
-			device->save_index ++;
-			if (device->save_index >= RT_UART_RX_BUFFER_SIZE)
-				device->save_index = 0;
-			
-			/* if the next position is read index, discard this 'read char' */
-			if (device->save_index == device->read_index)
-			{
-				device->read_index ++;
-				if (device->read_index >= RT_UART_RX_BUFFER_SIZE)
-					device->read_index = 0;
-			}
+            /* read character */
+            device->rx_buffer[device->save_index] = (0xff & (int) in_8((rt_uint8_t *)device->hw_base));
+            device->save_index ++;
+            if (device->save_index >= RT_UART_RX_BUFFER_SIZE)
+                device->save_index = 0;
 
-			/* enable interrupt */
-			rt_hw_interrupt_enable(level);
+            /* if the next position is read index, discard this 'read char' */
+            if (device->save_index == device->read_index)
+            {
+                device->read_index ++;
+                if (device->read_index >= RT_UART_RX_BUFFER_SIZE)
+                    device->read_index = 0;
+            }
 
-			/* check error */
-			if ((status & ( asyncLSRFramingError1 |
-					asyncLSROverrunError1 |
-					asyncLSRParityError1  |
-					asyncLSRBreakInterrupt1 )) != 0)
-			{
-				out_8((rt_uint8_t *)device->hw_base + UART_LSR,
-					  asyncLSRFramingError1 |
-					  asyncLSROverrunError1 |
-					  asyncLSRParityError1  |
-					  asyncLSRBreakInterrupt1);
-			}
+            /* enable interrupt */
+            rt_hw_interrupt_enable(level);
 
-			status = in_8((rt_uint8_t *)device->hw_base + UART_LSR);
-		}
+            /* check error */
+            if ((status & ( asyncLSRFramingError1 |
+                    asyncLSROverrunError1 |
+                    asyncLSRParityError1  |
+                    asyncLSRBreakInterrupt1 )) != 0)
+            {
+                out_8((rt_uint8_t *)device->hw_base + UART_LSR,
+                      asyncLSRFramingError1 |
+                      asyncLSROverrunError1 |
+                      asyncLSRParityError1  |
+                      asyncLSRBreakInterrupt1);
+            }
 
-		/* invoke callback */
-		if(device->parent.rx_indicate != RT_NULL)
-		{
-		  device->parent.rx_indicate(&device->parent, 1);
-		}
-	}
+            status = in_8((rt_uint8_t *)device->hw_base + UART_LSR);
+        }
+
+        /* invoke callback */
+        if(device->parent.rx_indicate != RT_NULL)
+        {
+          device->parent.rx_indicate(&device->parent, 1);
+        }
+    }
 }
 
 void rt_hw_serial_init(void)
 {
-	volatile rt_uint8_t val;
-	struct rt_ppc405_serial* device;
+    volatile rt_uint8_t val;
+    struct rt_ppc405_serial* device;
 
-	device = (struct rt_ppc405_serial*) &ppc405_serial;
-	device->parent.type = RT_Device_Class_Char;
-	
-	device->hw_base = UART0_BASE;
-	device->baudrate = 115200;
-	device->irqno = VECNUM_U0;
-	rt_hw_interrupt_install(device->irqno, rt_serial_isr, device, "serial"); /* install isr */
+    device = (struct rt_ppc405_serial*) &ppc405_serial;
+    device->parent.type = RT_Device_Class_Char;
 
-	rt_memset(device->rx_buffer, 0, sizeof(device->rx_buffer));
-	device->read_index = device->save_index = 0;
+    device->hw_base = UART0_BASE;
+    device->baudrate = 115200;
+    device->irqno = VECNUM_U0;
+    rt_hw_interrupt_install(device->irqno, rt_serial_isr, device, "serial"); /* install isr */
 
-	out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x80);	/* set DLAB bit */
-	/* setup baudrate */
-	rt_serial_set_baudrate(device);
-	out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x03);	/* clear DLAB; set 8 bits, no parity */
-	out_8((rt_uint8_t *)device->hw_base + UART_FCR, 0x00);	/* disable FIFO */
-	out_8((rt_uint8_t *)device->hw_base + UART_MCR, 0x00);	/* no modem control DTR RTS */
-	val = in_8((rt_uint8_t *)device->hw_base + UART_LSR);	/* clear line status */
-	val = in_8((rt_uint8_t *)device->hw_base + UART_RBR);	/* read receive buffer */
-	out_8((rt_uint8_t *)device->hw_base + UART_SCR, 0x00);	/* set scratchpad */
-	out_8((rt_uint8_t *)device->hw_base + UART_IER, 0x00);	/* set interrupt enable reg */
+    rt_memset(device->rx_buffer, 0, sizeof(device->rx_buffer));
+    device->read_index = device->save_index = 0;
 
-	device->parent.type     = RT_Device_Class_Char;
-	device->parent.init 	= rt_serial_init;
-	device->parent.open 	= rt_serial_open;
-	device->parent.close    = rt_serial_close;
-	device->parent.read 	= rt_serial_read;
-	device->parent.write    = rt_serial_write;
-	device->parent.control  = rt_serial_control;
-	device->parent.user_data  = RT_NULL;
+    out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x80);  /* set DLAB bit */
+    /* setup baudrate */
+    rt_serial_set_baudrate(device);
+    out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x03);  /* clear DLAB; set 8 bits, no parity */
+    out_8((rt_uint8_t *)device->hw_base + UART_FCR, 0x00);  /* disable FIFO */
+    out_8((rt_uint8_t *)device->hw_base + UART_MCR, 0x00);  /* no modem control DTR RTS */
+    val = in_8((rt_uint8_t *)device->hw_base + UART_LSR);   /* clear line status */
+    val = in_8((rt_uint8_t *)device->hw_base + UART_RBR);   /* read receive buffer */
+    out_8((rt_uint8_t *)device->hw_base + UART_SCR, 0x00);  /* set scratchpad */
+    out_8((rt_uint8_t *)device->hw_base + UART_IER, 0x00);  /* set interrupt enable reg */
 
-	rt_device_register(&device->parent, 
-		"uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM);
+    device->parent.type     = RT_Device_Class_Char;
+    device->parent.init     = rt_serial_init;
+    device->parent.open     = rt_serial_open;
+    device->parent.close    = rt_serial_close;
+    device->parent.read     = rt_serial_read;
+    device->parent.write    = rt_serial_write;
+    device->parent.control  = rt_serial_control;
+    device->parent.user_data  = RT_NULL;
+
+    rt_device_register(&device->parent,
+        "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM);
 }
diff --git a/libcpu/ppc/ppc405/traps.c b/libcpu/ppc/ppc405/traps.c
index 1deecbc92b..3ee754da23 100644
--- a/libcpu/ppc/ppc405/traps.c
+++ b/libcpu/ppc/ppc405/traps.c
@@ -7,8 +7,8 @@ extern unsigned long search_exception_table(unsigned long);
 
 /* THIS NEEDS CHANGING to use the board info structure.
  */
-#define END_OF_MEM	0x800000
-#define UICB0_ALL	0
+#define END_OF_MEM  0x800000
+#define UICB0_ALL   0
 
 #define ESR_MCI 0x80000000
 #define ESR_PIL 0x08000000
diff --git a/libcpu/risc-v/common/cpuport.c b/libcpu/risc-v/common/cpuport.c
index 6cb8aaf3e7..622e1bd321 100644
--- a/libcpu/risc-v/common/cpuport.c
+++ b/libcpu/risc-v/common/cpuport.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/risc-v/common/cpuport.h b/libcpu/risc-v/common/cpuport.h
index d6cec2f0cf..e625d9f91f 100644
--- a/libcpu/risc-v/common/cpuport.h
+++ b/libcpu/risc-v/common/cpuport.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -30,13 +30,13 @@
 #define FSTORE                  fsd
 #define FLOAD                   fld
 #define FREGBYTES               8
-#define rv_floatreg_t           rt_int64_t  	       
+#define rv_floatreg_t           rt_int64_t
 #endif
 #ifdef ARCH_RISCV_FPU_S
 #define FSTORE                  fsw
 #define FLOAD                   flw
 #define FREGBYTES               4
-#define rv_floatreg_t           rt_int32_t  	       
+#define rv_floatreg_t           rt_int32_t
 #endif
 #endif
 
diff --git a/libcpu/risc-v/common/riscv-ops.h b/libcpu/risc-v/common/riscv-ops.h
index 0b321c6de4..35d009ad53 100644
--- a/libcpu/risc-v/common/riscv-ops.h
+++ b/libcpu/risc-v/common/riscv-ops.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/risc-v/common/riscv-plic.h b/libcpu/risc-v/common/riscv-plic.h
index 1da14b2e45..53e19d2962 100644
--- a/libcpu/risc-v/common/riscv-plic.h
+++ b/libcpu/risc-v/common/riscv-plic.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/risc-v/k210/cpuport_smp.c b/libcpu/risc-v/k210/cpuport_smp.c
index 8c57dfeafc..113df9b3e2 100644
--- a/libcpu/risc-v/k210/cpuport_smp.c
+++ b/libcpu/risc-v/k210/cpuport_smp.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/risc-v/k210/interrupt.c b/libcpu/risc-v/k210/interrupt.c
index b582599daf..934acbdbf8 100644
--- a/libcpu/risc-v/k210/interrupt.c
+++ b/libcpu/risc-v/k210/interrupt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/risc-v/k210/tick.c b/libcpu/risc-v/k210/tick.c
index 144f7f1fff..2a76b50b6d 100644
--- a/libcpu/risc-v/k210/tick.c
+++ b/libcpu/risc-v/k210/tick.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/risc-v/k210/tick.h b/libcpu/risc-v/k210/tick.h
index 0821004263..0bfd6f62e8 100644
--- a/libcpu/risc-v/k210/tick.h
+++ b/libcpu/risc-v/k210/tick.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/risc-v/nuclei/cpuport.c b/libcpu/risc-v/nuclei/cpuport.c
index 717e9bb1c7..e74d174a54 100644
--- a/libcpu/risc-v/nuclei/cpuport.c
+++ b/libcpu/risc-v/nuclei/cpuport.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  * Copyright (c) 2019-Present Nuclei Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
@@ -26,23 +26,23 @@
 
 /**
  * @brief from thread used interrupt context switch
- * 
+ *
  */
 volatile rt_ubase_t  rt_interrupt_from_thread = 0;
 /**
  * @brief to thread used interrupt context switch
- * 
+ *
  */
 volatile rt_ubase_t  rt_interrupt_to_thread   = 0;
 /**
  * @brief flag to indicate context switch in interrupt or not
- * 
+ *
  */
 volatile rt_ubase_t rt_thread_switch_interrupt_flag = 0;
 
 /**
  * @brief thread stack frame of saved context
- * 
+ *
  */
 struct rt_hw_stack_frame
 {
@@ -121,7 +121,7 @@ rt_uint8_t *rt_hw_stack_init(void       *tentry,
 
 /**
  * @brief Do rt-thread context switch in interrupt context
- * 
+ *
  * @param from thread sp of from thread
  * @param to thread sp of to thread
  */
@@ -137,7 +137,7 @@ void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to)
 
 /**
  * @brief Do rt-thread context switch in task context
- * 
+ *
  * @param from thread sp of from thread
  * @param to thread sp of to thread
  */
@@ -150,7 +150,7 @@ void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to)
 
 /**
  * @brief shutdown CPU
- * 
+ *
  */
 RT_WEAK void rt_hw_cpu_shutdown()
 {
@@ -166,9 +166,9 @@ RT_WEAK void rt_hw_cpu_shutdown()
 
 /**
  * @brief Do extra task switch code
- * 
+ *
  * @details
- * 
+ *
  * - Clear software timer interrupt request flag
  * - clear rt_thread_switch_interrupt_flag to 0
  */
@@ -181,9 +181,9 @@ void rt_hw_taskswitch(void)
 
 /**
  * @brief Setup systimer and software timer interrupt
- * 
- * @details 
- * 
+ *
+ * @details
+ *
  * - Set Systimer interrupt as NON-VECTOR interrupt with lowest interrupt level
  * - Set software timer interrupt as VECTOR interrupt with lowest interrupt level
  * - Enable these two interrupts
@@ -216,7 +216,7 @@ void rt_hw_ticksetup(void)
 
 /**
  * @brief This is the timer interrupt service routine.
- * 
+ *
  */
 void SysTick_Handler(void)
 {
@@ -235,13 +235,13 @@ void SysTick_Handler(void)
 
 /**
  * @brief Disable cpu interrupt
- * 
+ *
  * @details
- * 
+ *
  * - Disable cpu interrupt by clear MIE bit in MSTATUS
  * - Return the previous value in MSTATUS before clear MIE bit
- * 
- * @return the previous value in MSTATUS before clear MIE bit 
+ *
+ * @return the previous value in MSTATUS before clear MIE bit
  */
 rt_base_t rt_hw_interrupt_disable(void)
 {
@@ -250,7 +250,7 @@ rt_base_t rt_hw_interrupt_disable(void)
 
 /**
  * @brief Restore previous saved interrupt status
- * 
+ *
  * @param level previous saved MSTATUS value
  */
 void rt_hw_interrupt_enable(rt_base_t level)
diff --git a/libcpu/risc-v/nuclei/cpuport.h b/libcpu/risc-v/nuclei/cpuport.h
index 3736f0078a..1f9634d4b1 100644
--- a/libcpu/risc-v/nuclei/cpuport.h
+++ b/libcpu/risc-v/nuclei/cpuport.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  * Copyright (c) 2019-Present Nuclei Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
diff --git a/libcpu/risc-v/rv32m1/interrupt.c b/libcpu/risc-v/rv32m1/interrupt.c
index 72cb344ff7..8da0dcfda6 100644
--- a/libcpu/risc-v/rv32m1/interrupt.c
+++ b/libcpu/risc-v/rv32m1/interrupt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/risc-v/t-head/e906/cpuport.c b/libcpu/risc-v/t-head/e906/cpuport.c
index 998bfdc340..0eaf5ffbce 100644
--- a/libcpu/risc-v/t-head/e906/cpuport.c
+++ b/libcpu/risc-v/t-head/e906/cpuport.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -131,7 +131,7 @@ rt_uint8_t *rt_hw_stack_init(void       *tentry,
 
 
 /**
- * This function will disable global interrupt 
+ * This function will disable global interrupt
  *
  * @param none
  *
@@ -145,7 +145,7 @@ rt_base_t rt_hw_interrupt_disable(void)
 }
 
 /**
- * This function will ennable global interrupt 
+ * This function will ennable global interrupt
  *
  * @param level not used
  *
diff --git a/libcpu/risc-v/t-head/e906/cpuport.h b/libcpu/risc-v/t-head/e906/cpuport.h
index 90efc07653..20302f44aa 100644
--- a/libcpu/risc-v/t-head/e906/cpuport.h
+++ b/libcpu/risc-v/t-head/e906/cpuport.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -42,13 +42,13 @@
 #define FSTORE                  fsd
 #define FLOAD                   fld
 #define FREGBYTES               8
-#define rv_floatreg_t           rt_int64_t  	       
+#define rv_floatreg_t           rt_int64_t
 #endif
 #ifdef ARCH_RISCV_FPU_S
 #define FSTORE                  fsw
 #define FLOAD                   flw
 #define FREGBYTES               4
-#define rv_floatreg_t           rt_int32_t  	       
+#define rv_floatreg_t           rt_int32_t
 #endif
 #endif
 
diff --git a/libcpu/rx/cpuport.c b/libcpu/rx/cpuport.c
index a01f598e99..00f9e26ba9 100644
--- a/libcpu/rx/cpuport.c
+++ b/libcpu/rx/cpuport.c
@@ -34,9 +34,9 @@ rt_uint32_t rt_thread_switch_interrupt_flag;
 /* stack frame*/
 struct stack_frame
 {
-    rt_uint32_t ACCLO; 
+    rt_uint32_t ACCLO;
     rt_uint32_t ACCHI;
-    rt_uint32_t FPSW;   
+    rt_uint32_t FPSW;
     rt_uint32_t R1;
     rt_uint32_t R2;
     rt_uint32_t R3;
@@ -53,21 +53,21 @@ struct stack_frame
     rt_uint32_t R14;
     rt_uint32_t R15;
     //there is not R0 register,it is special for stack pointer
-    rt_uint32_t PC;  
-    rt_uint32_t PSW; 
+    rt_uint32_t PC;
+    rt_uint32_t PSW;
 };
 
 /**
  * Initilial the thread stack.
- * 
+ *
  * @author LXZ (2014/11/8)
- * 
- * @param void* tentry       
- * @param void* parameter    
- * @param rt_uint8_t* stack_addr 
- * @param void* texit        
- * 
- * @return rt_uint8_t* 
+ *
+ * @param void* tentry
+ * @param void* parameter
+ * @param rt_uint8_t* stack_addr
+ * @param void* texit
+ *
+ * @return rt_uint8_t*
  */
 rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
                              rt_uint8_t *stack_addr, void *texit)
@@ -77,7 +77,7 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
     unsigned long       i;
 
     stk      = (unsigned long *)stack_addr;
-    *(stk)   = (unsigned long)texit;        
+    *(stk)   = (unsigned long)texit;
     stack_frame = (struct stack_frame *)(stack_addr - sizeof(struct stack_frame)) ;
 
     //Initilial all register
@@ -85,12 +85,12 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
     {
         ((rt_uint32_t *)stack_frame)[i] = 0xdeadbeef;
     }
-    
+
     stack_frame->PSW = (unsigned long)0x00030000 ;   /* psw */
     stack_frame->PC = (unsigned long)tentry;        /* thread entery*/
     stack_frame->R1 = (unsigned long )parameter;   /* r1 : parameter */
     stack_frame->FPSW = 0x00000100;                  /* fpsw */
-    
+
     return(rt_uint8_t *)stack_frame;
 }
 
@@ -99,16 +99,16 @@ extern void list_thread(void);
 #endif
 extern rt_thread_t rt_current_thread;
 /**
- * deal exception 
- * 
+ * deal exception
+ *
  * @author LXZ (2014/11/8)
- * 
- * @param struct stack_frame* exception_contex 
+ *
+ * @param struct stack_frame* exception_contex
  */
 void rt_hw_hard_fault_exception(struct stack_frame* exception_contex)
 {
     if (exception_contex != RT_NULL) {
-        rt_kprintf("psw: 0x%08x\n", exception_contex->PSW); 
+        rt_kprintf("psw: 0x%08x\n", exception_contex->PSW);
         rt_kprintf("pc: 0x%08x\n", exception_contex->PC);
         rt_kprintf("r0: 0x%08x\n", exception_contex->R1);
         rt_kprintf("r0: 0x%08x\n", exception_contex->R2);
@@ -134,17 +134,17 @@ void rt_hw_hard_fault_exception(struct stack_frame* exception_contex)
         list_thread();
     #endif
         while (1);
-    
+
 }
 
 
 /**
  * switch thread in interrupt
- * 
+ *
  * @author LXZ (2014/11/8)
- * 
- * @param rt_uint32_t from 
- * @param rt_uint32_t to 
+ *
+ * @param rt_uint32_t from
+ * @param rt_uint32_t to
  */
 void rt_hw_context_switch(rt_uint32_t from, rt_uint32_t to)
 {
@@ -159,11 +159,11 @@ void rt_hw_context_switch(rt_uint32_t from, rt_uint32_t to)
 }
 /**
  * switch thread out the interrupt
- * 
+ *
  * @author LXZ (2014/11/8)
- * 
- * @param rt_uint32_t from 
- * @param rt_uint32_t to 
+ *
+ * @param rt_uint32_t from
+ * @param rt_uint32_t to
  */
 void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to)
 {
@@ -179,7 +179,7 @@ void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to)
 
 /**
  * shut down the chip
- * 
+ *
  * @author LXZ (2014/11/8)
  */
 RT_WEAK void rt_hw_cpu_shutdown(void)
@@ -190,10 +190,10 @@ RT_WEAK void rt_hw_cpu_shutdown(void)
 }
 /**
  * switch to the first thread,it just call one time
- * 
+ *
  * @author LXZ (2014/11/8)
- * 
- * @param rt_uint32_t to 
+ *
+ * @param rt_uint32_t to
  */
 void rt_hw_context_switch_to(rt_uint32_t to)
 {
diff --git a/libcpu/sim/posix/cpu_port.c b/libcpu/sim/posix/cpu_port.c
index eb1ae4865c..dc3e9379dd 100644
--- a/libcpu/sim/posix/cpu_port.c
+++ b/libcpu/sim/posix/cpu_port.c
@@ -173,8 +173,8 @@ static void *thread_run(void *parameter)
     /*TODO:
      * 最后一行的pthread_exit永远没有机会执行，这是因为在threead->exit函数中
      * 会发生线程切换，并永久将此pthread线程挂起，所以更完美的解决方案是在这
-	 * 里发送信号给主线程，主线程中再次唤醒此线程令其自动退出。
-	 */
+     * 里发送信号给主线程，主线程中再次唤醒此线程令其自动退出。
+     */
     //sem_destroy(&thread->sem);
 
     pthread_exit(NULL);
diff --git a/libcpu/sim/win32/cpu_port.c b/libcpu/sim/win32/cpu_port.c
index cc8ad9a25c..b7510819b9 100644
--- a/libcpu/sim/win32/cpu_port.c
+++ b/libcpu/sim/win32/cpu_port.c
@@ -5,7 +5,7 @@
 * Version : V1.00.00
 *
 * By      : prife
-* Version : V1.00.01 
+* Version : V1.00.01
 ************************************************************************************************************************
 */
 
@@ -47,10 +47,10 @@ const DWORD MS_VC_EXCEPTION=0x406D1388;
 #pragma pack(push,8)
 typedef struct tagTHREADNAME_INFO
 {
-	DWORD dwType; // Must be 0x1000.
-	LPCSTR szName; // Pointer to name (in user addr space).
-	DWORD dwThreadID; // Thread ID (-1=caller thread).
-	DWORD dwFlags; // Reserved for future use, must be zero.
+    DWORD dwType; // Must be 0x1000.
+    LPCSTR szName; // Pointer to name (in user addr space).
+    DWORD dwThreadID; // Thread ID (-1=caller thread).
+    DWORD dwFlags; // Reserved for future use, must be zero.
 } THREADNAME_INFO;
 #pragma pack(pop)
 
@@ -115,19 +115,19 @@ static DWORD WINAPI ThreadforKeyGet(LPVOID lpParam);
 static void SetThreadName(DWORD dwThreadID, char* threadName)
 {
 #if defined(_MSC_VER)
-	THREADNAME_INFO info;
-	info.dwType = 0x1000;
-	info.szName = threadName;
-	info.dwThreadID = dwThreadID;
-	info.dwFlags = 0;
+    THREADNAME_INFO info;
+    info.dwType = 0x1000;
+    info.szName = threadName;
+    info.dwThreadID = dwThreadID;
+    info.dwFlags = 0;
 
-	__try
-	{
-		RaiseException( MS_VC_EXCEPTION, 0, sizeof(info)/sizeof(ULONG_PTR), (ULONG_PTR*)&info );
-	}
-	__except(EXCEPTION_EXECUTE_HANDLER)
-	{
-	}
+    __try
+    {
+        RaiseException( MS_VC_EXCEPTION, 0, sizeof(info)/sizeof(ULONG_PTR), (ULONG_PTR*)&info );
+    }
+    __except(EXCEPTION_EXECUTE_HANDLER)
+    {
+    }
 #endif
 }
 
@@ -144,15 +144,15 @@ static void SetThreadName(DWORD dwThreadID, char* threadName)
 
 static DWORD WINAPI thread_run( LPVOID lpThreadParameter )
 {
-	rt_thread_t tid = rt_thread_self();
-	win_thread_t  *pWinThread = (win_thread_t *)lpThreadParameter;
+    rt_thread_t tid = rt_thread_self();
+    win_thread_t  *pWinThread = (win_thread_t *)lpThreadParameter;
 
-	SetThreadName(GetCurrentThreadId(), tid->name);
+    SetThreadName(GetCurrentThreadId(), tid->name);
 
-	pWinThread->Entry(pWinThread->Param);
+    pWinThread->Entry(pWinThread->Param);
 
-	pWinThread->Exit();
-	return 0;	
+    pWinThread->Exit();
+    return 0;
 }
 
 rt_uint8_t* rt_hw_stack_init(void *pEntry,void *pParam,rt_uint8_t *pStackAddr,void *pExit)
@@ -261,7 +261,7 @@ void rt_hw_context_switch_interrupt(rt_uint32_t from,
 
     rt_interrupt_to_thread = *((rt_uint32_t *)(to));
 
-	//trigger YIELD exception(cause context switch)
+    //trigger YIELD exception(cause context switch)
     TriggerSimulateInterrupt(CPU_INTERRUPT_YIELD);
 } /*** rt_hw_context_switch_interrupt ***/
 
@@ -312,7 +312,7 @@ void rt_hw_context_switch(rt_uint32_t from,
 */
 void rt_hw_context_switch_to(rt_uint32_t to)
 {
-	//set to thread
+    //set to thread
     rt_interrupt_to_thread = *((rt_uint32_t *)(to));
 
     //clear from thread
@@ -699,3 +699,14 @@ rt_uint32_t YieldInterruptHandle(void)
 
     return 0;
 } /*** YieldInterruptHandle ***/
+
+/* system entry */
+extern int rtthread_startup(void);
+int wmain(int argc, char* argv[])
+{
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
+    /* startup RT-Thread RTOS */
+    rtthread_startup();
+}
+#pragma comment(linker, "/subsystem:console /entry:wmainCRTStartup")
diff --git a/libcpu/sim/win32/startup.c b/libcpu/sim/win32/startup.c
new file mode 100644
index 0000000000..756d409315
--- /dev/null
+++ b/libcpu/sim/win32/startup.c
@@ -0,0 +1,326 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-12-04     tyx          first implementation
+ */
+
+#include 
+#include 
+
+#ifdef RT_USING_USER_MAIN
+#ifndef RT_MAIN_THREAD_STACK_SIZE
+#define RT_MAIN_THREAD_STACK_SIZE     2048
+#endif
+#ifndef RT_MAIN_THREAD_PRIORITY
+#define RT_MAIN_THREAD_PRIORITY       (RT_THREAD_PRIORITY_MAX / 3)
+#endif
+#endif
+
+#ifdef RT_USING_COMPONENTS_INIT
+/*
+ * Components Initialization will initialize some driver and components as following
+ * order:
+ * rti_start         --> 0
+ * BOARD_EXPORT      --> 1
+ * rti_board_end     --> 1.end
+ *
+ * DEVICE_EXPORT     --> 2
+ * COMPONENT_EXPORT  --> 3
+ * FS_EXPORT         --> 4
+ * ENV_EXPORT        --> 5
+ * APP_EXPORT        --> 6
+ *
+ * rti_end           --> 6.end
+ *
+ * These automatically initialization, the driver or component initial function must
+ * be defined with:
+ * INIT_BOARD_EXPORT(fn);
+ * INIT_DEVICE_EXPORT(fn);
+ * ...
+ * INIT_APP_EXPORT(fn);
+ * etc.
+ */
+
+#pragma section("rti_fn$a", read)
+const char __rti_fn_begin_name[] = "__rti_fn_start";
+__declspec(allocate("rti_fn$a")) const struct rt_init_desc __rti_fn_begin =
+{
+    __rti_fn_begin_name,
+    NULL
+};
+
+#pragma section("rti_fn$z", read)
+const char __rti_fn_end_name[] = "__rti_fn_end";
+__declspec(allocate("rti_fn$z")) const struct rt_init_desc __rti_fn_end =
+{
+    __rti_fn_end_name,
+    NULL
+};
+
+static int rti_start(void)
+{
+    return 0;
+}
+INIT_EXPORT(rti_start, "0");
+
+static int rti_board_end(void)
+{
+    return 0;
+}
+INIT_EXPORT(rti_board_end, "1_end");
+
+static int rti_end(void)
+{
+    return 0;
+}
+INIT_EXPORT(rti_end, "6_end");
+
+/**
+ * Find next init function
+ */
+static const struct rt_init_desc* rt_init_find_next(const char* lv,
+    unsigned int* begin, unsigned int* end)
+{
+    const struct rt_init_desc* ptr;
+    const struct rt_init_desc* ret_ptr = RT_NULL;
+
+    while (begin < end)
+    {
+        if (*begin != 0)
+        {
+            ptr = (const struct rt_init_desc*)begin;
+            if (ret_ptr != RT_NULL)
+            {
+                if (rt_strcmp(lv, ptr->level) < 0 &&
+                    rt_strcmp(ret_ptr->level, ptr->level) > 0)
+                {
+                    ret_ptr = ptr;
+                }
+            }
+            else
+            {
+                if (rt_strcmp(lv, ptr->level) < 0)
+                {
+                    ret_ptr = ptr;
+                }
+            }
+            begin += (sizeof(struct rt_init_desc) / sizeof(unsigned int));
+        }
+        else
+        {
+            begin++;
+        }
+    }
+    return ret_ptr;
+}
+
+/**
+ * RT-Thread Components Initialization for board
+ */
+void rt_components_board_init(void)
+{
+    const struct rt_init_desc* ptr;
+    const char* lv_start = "0__rt_init_rti_start";
+    const char* lv_end = "1_end__rt_init_rti_board_end";
+    unsigned int* ptr_begin = (unsigned int*)&__rti_fn_begin;
+    unsigned int* ptr_end = (unsigned int*)&__rti_fn_end;
+    int result;
+
+    ptr_begin += (sizeof(struct rt_init_desc) / sizeof(unsigned int));
+    while (*ptr_begin == 0) ptr_begin++;
+    do ptr_end--; while (*ptr_end == 0);
+
+    while (1)
+    {
+        ptr = rt_init_find_next(lv_start, ptr_begin, ptr_end);
+        if (ptr == RT_NULL ||
+            rt_strcmp(ptr->level, lv_end) >= 0)
+        {
+            break;
+        }
+        if (ptr->fn)
+        {
+#if RT_DEBUG_INIT
+            rt_kprintf("initialize %s", ptr->fn_name);
+            result = ptr->fn();
+            rt_kprintf(":%d done\n", result);
+#else
+            result = ptr->fn();
+#endif
+        }
+        lv_start = ptr->level;
+    };
+}
+
+/**
+ * RT-Thread Components Initialization
+ */
+void rt_components_init(void)
+{
+    const struct rt_init_desc* ptr;
+    const char* lv_start = "1_end__rt_init_rti_board_end";
+    const char* lv_end = "6_end__rt_init_rti_end";
+    unsigned int* ptr_begin = (unsigned int*)&__rti_fn_begin;
+    unsigned int* ptr_end = (unsigned int*)&__rti_fn_end;
+    int result;
+
+    ptr_begin += (sizeof(struct rt_init_desc) / sizeof(unsigned int));
+    while (*ptr_begin == 0) ptr_begin++;
+    do ptr_end--; while (*ptr_end == 0);
+
+    while (1)
+    {
+        ptr = rt_init_find_next(lv_start, ptr_begin, ptr_end);
+        if (ptr == RT_NULL ||
+            rt_strcmp(ptr->level, lv_end) >= 0)
+        {
+            break;
+        }
+        if (ptr->fn)
+        {
+#if RT_DEBUG_INIT
+            rt_kprintf("initialize %s", ptr->fn_name);
+            result = ptr->fn();
+            rt_kprintf(":%d done\n", result);
+#else
+            result = ptr->fn();
+#endif
+        }
+        lv_start = ptr->level;
+    };
+}
+#endif   /* RT_USING_COMPONENTS_INIT */
+
+#ifdef RT_USING_USER_MAIN
+
+void rt_application_init(void);
+void rt_hw_board_init(void);
+int rtthread_startup(void);
+
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+extern int $Super$$main(void);
+/* re-define main function */
+int $Sub$$main(void)
+{
+    rtthread_startup();
+    return 0;
+}
+#elif defined(__ICCARM__)
+extern int main(void);
+/* __low_level_init will auto called by IAR cstartup */
+extern void __iar_data_init3(void);
+int __low_level_init(void)
+{
+    // call IAR table copy function.
+    __iar_data_init3();
+    rtthread_startup();
+    return 0;
+}
+#elif defined(__GNUC__)
+/* Add -eentry to arm-none-eabi-gcc argument */
+int entry(void)
+{
+    rtthread_startup();
+    return 0;
+}
+#endif
+
+#ifndef RT_USING_HEAP
+/* if there is not enable heap, we should use static thread and stack. */
+ALIGN(8)
+static rt_uint8_t main_stack[RT_MAIN_THREAD_STACK_SIZE];
+struct rt_thread main_thread;
+#endif
+
+/* the system main thread */
+void main_thread_entry(void *parameter)
+{
+    extern int main(void);
+
+#ifdef RT_USING_COMPONENTS_INIT
+    /* RT-Thread components initialization */
+    rt_components_init();
+#endif
+
+#ifdef RT_USING_SMP
+    rt_hw_secondary_cpu_up();
+#endif
+    /* invoke system main function */
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+    {
+        extern int $Super$$main(void);
+        $Super$$main(); /* for ARMCC. */
+    }
+#elif defined(__ICCARM__) || defined(__GNUC__) || defined(__TASKING__) || defined(_MSC_VER)
+    main();
+#endif
+}
+
+void rt_application_init(void)
+{
+    rt_thread_t tid;
+
+#ifdef RT_USING_HEAP
+    tid = rt_thread_create("main", main_thread_entry, RT_NULL,
+                           RT_MAIN_THREAD_STACK_SIZE, RT_MAIN_THREAD_PRIORITY, 20);
+    RT_ASSERT(tid != RT_NULL);
+#else
+    rt_err_t result;
+
+    tid = &main_thread;
+    result = rt_thread_init(tid, "main", main_thread_entry, RT_NULL,
+                            main_stack, sizeof(main_stack), RT_MAIN_THREAD_PRIORITY, 20);
+    RT_ASSERT(result == RT_EOK);
+
+    /* if not define RT_USING_HEAP, using to eliminate the warning */
+    (void)result;
+#endif
+
+    rt_thread_startup(tid);
+}
+
+int rtthread_startup(void)
+{
+    rt_hw_interrupt_disable();
+
+    /* board level initialization
+     * NOTE: please initialize heap inside board initialization.
+     */
+    rt_hw_board_init();
+
+    /* show RT-Thread version */
+    rt_show_version();
+
+    /* timer system initialization */
+    rt_system_timer_init();
+
+    /* scheduler system initialization */
+    rt_system_scheduler_init();
+
+#ifdef RT_USING_SIGNALS
+    /* signal system initialization */
+    rt_system_signal_init();
+#endif
+
+    /* create init_thread */
+    rt_application_init();
+
+    /* timer thread initialization */
+    rt_system_timer_thread_init();
+
+    /* idle thread initialization */
+    rt_thread_idle_init();
+
+#ifdef RT_USING_SMP
+    rt_hw_spin_lock(&_cpus_lock);
+#endif /*RT_USING_SMP*/
+
+    /* start scheduler */
+    rt_system_scheduler_start();
+
+    /* never reach here */
+    return 0;
+}
+#endif
diff --git a/libcpu/ti-dsp/c28x/cpuport.c b/libcpu/ti-dsp/c28x/cpuport.c
index 15041fc846..44876a5af5 100644
--- a/libcpu/ti-dsp/c28x/cpuport.c
+++ b/libcpu/ti-dsp/c28x/cpuport.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/unicore32/sep6200/context_gcc.S b/libcpu/unicore32/sep6200/context_gcc.S
index 6b958e7f93..9f8e2b8f13 100644
--- a/libcpu/unicore32/sep6200/context_gcc.S
+++ b/libcpu/unicore32/sep6200/context_gcc.S
@@ -1,21 +1,7 @@
 /*
- * File      : context_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/libcpu/unicore32/sep6200/cpu.c b/libcpu/unicore32/sep6200/cpu.c
index 9452b4e59d..966277295d 100644
--- a/libcpu/unicore32/sep6200/cpu.c
+++ b/libcpu/unicore32/sep6200/cpu.c
@@ -1,21 +1,7 @@
 /*
- * File      : cpu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -34,23 +20,23 @@
 #ifdef __GNUC__
 rt_inline void cache_invalid(void)
 {
-	__asm__ volatile ("movc	p0.c5, r1, #28\n"
-			"nop;nop;nop;nop;nop;nop;nop;nop;\n"
-			:
-			:
-			:"memory", "cc"
-			);
+    __asm__ volatile ("movc p0.c5, r1, #28\n"
+            "nop;nop;nop;nop;nop;nop;nop;nop;\n"
+            :
+            :
+            :"memory", "cc"
+            );
 }
 
 rt_inline void cache_enable(void)
 {
-	__asm__ volatile ( "movc r1, p0.c1, #0\n"
-			"or r1, r1, #0xc\n"
-			"movc p0.c1, r1, #0\n"
-			"nop;nop;nop;nop;nop;nop;nop;nop;\n"
-			:
-			:
-			:"r0", "memory", "cc");
+    __asm__ volatile ( "movc r1, p0.c1, #0\n"
+            "or r1, r1, #0xc\n"
+            "movc p0.c1, r1, #0\n"
+            "nop;nop;nop;nop;nop;nop;nop;nop;\n"
+            :
+            :
+            :"r0", "memory", "cc");
 }
 
 rt_inline void clean_dcache(void)
@@ -59,8 +45,8 @@ rt_inline void clean_dcache(void)
                "movc p0.c5, ip, #10\n"
                "nop; nop; nop; nop; nop; nop; nop; nop\n"
                :
-	       :
-	       :"ip", "memory", "cc");
+           :
+           :"ip", "memory", "cc");
 }
 
 rt_inline rt_uint32_t icache_status(void)
@@ -91,7 +77,7 @@ rt_inline rt_uint32_t dcache_status(void)
 
 rt_inline void dcache_flush(void)
 {
-	__asm__ volatile ( "mov ip, #0\n"
+    __asm__ volatile ( "mov ip, #0\n"
               "movc p0.c5, ip, #14\n"
               "nop; nop; nop; nop; nop; nop; nop; nop\n"
               :
@@ -101,7 +87,7 @@ rt_inline void dcache_flush(void)
 
 rt_inline void icache_invalid(void)
 {
-	 __asm__ volatile ( "mov r0, #0\n"
+     __asm__ volatile ( "mov r0, #0\n"
                "movc p0.c5, r0, #20\n"
                "nop; nop; nop; nop; nop; nop; nop; nop\n"
                :
@@ -121,8 +107,8 @@ rt_inline void dcache_invalid(void)
 
 rt_inline void icache_disable(void)
 {
-	icache_invalid();
-	__asm__ volatile ( "movc r0, p0.c1, #0\n"
+    icache_invalid();
+    __asm__ volatile ( "movc r0, p0.c1, #0\n"
                "andn r0, r0, #8\n"
                "movc p0.c1, r0, #0\n"
                :
@@ -132,8 +118,8 @@ rt_inline void icache_disable(void)
 
 rt_inline void dcache_disable(void)
 {
-	dcache_flush();
-	__asm__ volatile ( "movc r0, p0.c1, #0\n"
+    dcache_flush();
+    __asm__ volatile ( "movc r0, p0.c1, #0\n"
                "andn r0, r0, #20\n"
                "movc p0.c1, r0, #0\n"
                :
@@ -184,7 +170,7 @@ rt_inline void dcache_enable(void)
  */
 void rt_hw_cpu_icache_enable()
 {
-	icache_enable();
+    icache_enable();
 }
 
 /**
@@ -193,7 +179,7 @@ void rt_hw_cpu_icache_enable()
  */
 void rt_hw_cpu_icache_disable()
 {
-	icache_disable();
+    icache_disable();
 }
 
 /**
@@ -202,7 +188,7 @@ void rt_hw_cpu_icache_disable()
  */
 rt_base_t rt_hw_cpu_icache_status()
 {
-	return icache_status();
+    return icache_status();
 }
 
 /**
@@ -211,7 +197,7 @@ rt_base_t rt_hw_cpu_icache_status()
  */
 void rt_hw_cpu_dcache_enable()
 {
-	dcache_enable();
+    dcache_enable();
 }
 
 /**
@@ -220,7 +206,7 @@ void rt_hw_cpu_dcache_enable()
  */
 void rt_hw_cpu_dcache_disable()
 {
-	dcache_disable();
+    dcache_disable();
 }
 
 /**
@@ -229,29 +215,29 @@ void rt_hw_cpu_dcache_disable()
  */
 rt_base_t rt_hw_cpu_dcache_status()
 {
-	return dcache_status();
+    return dcache_status();
 }
 
 static void sep6200_reset(rt_uint32_t addr)
 {
      __asm__ volatile ( "mov ip, #0\n"
-		     "movc p0.c5, ip, #28\n" /*Cache invalidate all*/
-		     "movc p0.c6, ip, #6\n" /*TLB invalidate all*/
-		     "nop;nop;nop;nop;nop;nop;nop;nop;\n"
-		     "movc ip, p0.c1, #0\n" /*ctrl register*/
-		     "andn ip, ip, #0x000f\n" /*disable caches and mmu*/
-		     "movc p0.c1, ip, #0\n"
-		     "nop\n"
-		     "mov pc, %0\n"
-		     "nop;nop;nop;nop;nop;nop;nop;nop;\n"
-		      : "=&r" (addr)
-		      :
-		      :"memory", "cc");
+             "movc p0.c5, ip, #28\n" /*Cache invalidate all*/
+             "movc p0.c6, ip, #6\n" /*TLB invalidate all*/
+             "nop;nop;nop;nop;nop;nop;nop;nop;\n"
+             "movc ip, p0.c1, #0\n" /*ctrl register*/
+             "andn ip, ip, #0x000f\n" /*disable caches and mmu*/
+             "movc p0.c1, ip, #0\n"
+             "nop\n"
+             "mov pc, %0\n"
+             "nop;nop;nop;nop;nop;nop;nop;nop;\n"
+              : "=&r" (addr)
+              :
+              :"memory", "cc");
 }
 
 static void sep6200_poweroff(void)
 {
-	rt_kprintf("sep6200 power off not implemented\n");
+    rt_kprintf("sep6200 power off not implemented\n");
   while(1);
 }
 
@@ -262,12 +248,12 @@ static void sep6200_poweroff(void)
 RT_WEAK void rt_hw_cpu_reset()
 {
 
-	rt_kprintf("Soft reset, Restarting system...\n");
-	sep6200_reset(0);
+    rt_kprintf("Soft reset, Restarting system...\n");
+    sep6200_reset(0);
 
-	while(1);	/* loop forever and wait for reset to happen */
+    while(1);   /* loop forever and wait for reset to happen */
 
-	/* NEVER REACHED */
+    /* NEVER REACHED */
 }
 
 /**
@@ -276,15 +262,15 @@ RT_WEAK void rt_hw_cpu_reset()
  */
 RT_WEAK void rt_hw_cpu_shutdown()
 {
-	rt_uint32_t level;
-	rt_kprintf("shutdown...\n");
+    rt_uint32_t level;
+    rt_kprintf("shutdown...\n");
 
-	level = rt_hw_interrupt_disable();
-	sep6200_poweroff();
-	while (level)
-	{
-		RT_ASSERT(0);
-	}
+    level = rt_hw_interrupt_disable();
+    sep6200_poweroff();
+    while (level)
+    {
+        RT_ASSERT(0);
+    }
 }
 
 /*@}*/
diff --git a/libcpu/unicore32/sep6200/interrupt.c b/libcpu/unicore32/sep6200/interrupt.c
index 31078320ea..b34e648630 100644
--- a/libcpu/unicore32/sep6200/interrupt.c
+++ b/libcpu/unicore32/sep6200/interrupt.c
@@ -1,21 +1,7 @@
 /*
- * File      : interrupt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -26,38 +12,38 @@
 #include 
 #include 
 
-#define MAX_HANDLERS	64
+#define MAX_HANDLERS    64
 
 
 #define SEP6200_IRQ_TYPE 0
 #define SEP6200_FIQ_TYPE 1
 
-#define int_enable_all() 					  \
-	do {							  \
-		*(volatile unsigned long*)SEP6200_VIC_INT_EN_L = ~0x0;\
-		*(volatile unsigned long*)SEP6200_VIC_INT_EN_H = ~0x0;\
-	}while(0)
-#define int_disable_all() 					 \
-	do {							 \
-		*(volatile unsigned long*)SEP6200_VIC_INT_EN_L = 0x0;\
-		*(volatile unsigned long*)SEP6200_VIC_INT_EN_H = 0x0;\
-	}while(0)
-#define mask_all_int(int_type)					 \
-	do {							 \
-		if (int_type == SEP6200_IRQ_TYPE){		 \
-		*(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = 0x1;\
-		} else if (int_type == SEP6200_FIQ_TYPE) {\
-		*(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = 0x2;\
-		}\
-	}while(0)
+#define int_enable_all()                      \
+    do {                              \
+        *(volatile unsigned long*)SEP6200_VIC_INT_EN_L = ~0x0;\
+        *(volatile unsigned long*)SEP6200_VIC_INT_EN_H = ~0x0;\
+    }while(0)
+#define int_disable_all()                    \
+    do {                             \
+        *(volatile unsigned long*)SEP6200_VIC_INT_EN_L = 0x0;\
+        *(volatile unsigned long*)SEP6200_VIC_INT_EN_H = 0x0;\
+    }while(0)
+#define mask_all_int(int_type)                   \
+    do {                             \
+        if (int_type == SEP6200_IRQ_TYPE){       \
+        *(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = 0x1;\
+        } else if (int_type == SEP6200_FIQ_TYPE) {\
+        *(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = 0x2;\
+        }\
+    }while(0)
 #define unmask_all_int(int_type)\
-	do {							 \
-		if (int_type == SEP6200_IRQ_TYPE){		 \
-		*(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = ~0x1;\
-		} else if (int_type == SEP6200_FIQ_TYPE) {\
-		*(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = ~0x2;\
-		}\
-	}while(0)
+    do {                             \
+        if (int_type == SEP6200_IRQ_TYPE){       \
+        *(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = ~0x1;\
+        } else if (int_type == SEP6200_FIQ_TYPE) {\
+        *(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = ~0x2;\
+        }\
+    }while(0)
 
 #define SEP6200_INT_SET(intnum)                                     \
 do{                                                                 \
@@ -113,27 +99,27 @@ void rt_hw_interrupt_umask(int irq);
 
 rt_inline void sep6200_irq_enable(rt_uint32_t irq)
 {
-	SEP6200_INT_ENABLE(irq);
+    SEP6200_INT_ENABLE(irq);
 }
 
 rt_inline void sep6200_irq_disable(rt_uint32_t irq)
 {
-	SEP6200_INT_DISABLE(irq);
+    SEP6200_INT_DISABLE(irq);
 }
 
 rt_inline void sep6200_irq_unmask(rt_uint32_t irq)
 {
-	SEP6200_INT_ENABLE(irq);
+    SEP6200_INT_ENABLE(irq);
 }
 
 rt_inline void sep6200_irq_mask(rt_uint32_t irq)
 {
-	SEP6200_INT_DISABLE(irq);
+    SEP6200_INT_DISABLE(irq);
 }
 rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector)
 {
-	rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
-	return RT_NULL;
+    rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+    return RT_NULL;
 }
 
 /**
@@ -141,26 +127,26 @@ rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector)
  */
 void rt_hw_interrupt_init(void)
 {
-	rt_int32_t i;
-	register rt_uint32_t idx;
+    rt_int32_t i;
+    register rt_uint32_t idx;
 
 
-	/* init exceptions table */
-	for(idx=0; idx < MAX_HANDLERS; idx++)
-	{
-		isr_table[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle;
-	}
-	int_disable_all();
-	mask_all_int(SEP6200_FIQ_TYPE);
+    /* init exceptions table */
+    for(idx=0; idx < MAX_HANDLERS; idx++)
+    {
+        isr_table[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle;
+    }
+    int_disable_all();
+    mask_all_int(SEP6200_FIQ_TYPE);
 
-	//int_enable_all();
-	unmask_all_int(SEP6200_IRQ_TYPE);
+    //int_enable_all();
+    unmask_all_int(SEP6200_IRQ_TYPE);
 
-	/* init interrupt nest, and context in thread sp */
-	rt_interrupt_nest = 0;
-	rt_interrupt_from_thread = 0;
-	rt_interrupt_to_thread = 0;
-	rt_thread_switch_interrupt_flag = 0;
+    /* init interrupt nest, and context in thread sp */
+    rt_interrupt_nest = 0;
+    rt_interrupt_from_thread = 0;
+    rt_interrupt_to_thread = 0;
+    rt_thread_switch_interrupt_flag = 0;
 }
 
 
@@ -171,11 +157,11 @@ void rt_hw_interrupt_init(void)
  */
 void rt_hw_interrupt_mask(int irq)
 {
-	if (irq >= MAX_HANDLERS) {
-		rt_kprintf("Wrong irq num to mask\n");
-	} else {
-		sep6200_irq_mask(irq);
-	}
+    if (irq >= MAX_HANDLERS) {
+        rt_kprintf("Wrong irq num to mask\n");
+    } else {
+        sep6200_irq_mask(irq);
+    }
 
 }
 
@@ -185,11 +171,11 @@ void rt_hw_interrupt_mask(int irq)
  */
 void rt_hw_interrupt_umask(int irq)
 {
-	if (irq >= MAX_HANDLERS) {
-		rt_kprintf("Wrong irq num to unmask\n");
-	} else {
-		sep6200_irq_unmask(irq);
-	}
+    if (irq >= MAX_HANDLERS) {
+        rt_kprintf("Wrong irq num to unmask\n");
+    } else {
+        sep6200_irq_unmask(irq);
+    }
 }
 
 /**
@@ -210,7 +196,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
         if (handler != RT_NULL)
         {
 #ifdef RT_USING_INTERRUPT_INFO
-		    rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
+            rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
 #endif /* RT_USING_INTERRUPT_INFO */
             isr_table[vector].handler = handler;
             isr_table[vector].param = param;
diff --git a/libcpu/unicore32/sep6200/sep6200.h b/libcpu/unicore32/sep6200/sep6200.h
index c09823740b..773b505a02 100644
--- a/libcpu/unicore32/sep6200/sep6200.h
+++ b/libcpu/unicore32/sep6200/sep6200.h
@@ -1,21 +1,7 @@
 /*
- * File      : sep6200.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -29,58 +15,58 @@
 
 /*Core definations*/
 #define PRIVMODE  0x13
-#define	Mode_USR	0x10
-#define	Mode_REAL	0x11
-#define	Mode_IRQ	0x12
-#define	Mode_PRIV	0x13
-#define	Mode_TRAP	0x17
-#define	Mode_EXT	0x1B
-#define	Mode_SUSR	0x1F
+#define Mode_USR    0x10
+#define Mode_REAL   0x11
+#define Mode_IRQ    0x12
+#define Mode_PRIV   0x13
+#define Mode_TRAP   0x17
+#define Mode_EXT    0x1B
+#define Mode_SUSR   0x1F
 
 /*
  *  Address
  */
 
-#define	 SEP6200_VIC_BASE	0xb0000000
-#define  SEP6200_PMU_BASE	0xb0001000
-#define  SEP6200_RTC_BASE	0xb0002000
-#define	 SEP6200_TIMER_BASE 0xb0003000
-#define  SEP6200_PWM_BASE	0xb0004000
-#define  SEP6200_GPIO_BASE	0xb0006000
-#define  SEP6200_TOUCH_ADC	0xb0007000
-#define  SEP6200_SYSCTL_BASE	0xb0008000
-#define  SEP6200_UART0_BASE	0xb1000000
-#define  SEP6200_UART1_BASE	0xb1001000
-#define  SEP6200_UART2_BASE	0xb1002000
-#define  SEP6200_UART3_BASE	0xb1003000
-#define	 SEP6200_SSI1_BASE	0xb1004000
-#define	 SEP6200_SSI2_BASE	0xb1005000
-#define	 SEP6200_SSI3_BASE	0xb1006000
-#define  SEP6200_I2C_BASE	0xb1007000
-#define  SEP6200_I2S_BASE	0xb1008000
+#define  SEP6200_VIC_BASE   0xb0000000
+#define  SEP6200_PMU_BASE   0xb0001000
+#define  SEP6200_RTC_BASE   0xb0002000
+#define  SEP6200_TIMER_BASE 0xb0003000
+#define  SEP6200_PWM_BASE   0xb0004000
+#define  SEP6200_GPIO_BASE  0xb0006000
+#define  SEP6200_TOUCH_ADC  0xb0007000
+#define  SEP6200_SYSCTL_BASE    0xb0008000
+#define  SEP6200_UART0_BASE 0xb1000000
+#define  SEP6200_UART1_BASE 0xb1001000
+#define  SEP6200_UART2_BASE 0xb1002000
+#define  SEP6200_UART3_BASE 0xb1003000
+#define  SEP6200_SSI1_BASE  0xb1004000
+#define  SEP6200_SSI2_BASE  0xb1005000
+#define  SEP6200_SSI3_BASE  0xb1006000
+#define  SEP6200_I2C_BASE   0xb1007000
+#define  SEP6200_I2S_BASE   0xb1008000
 #define  SEP6200_USB_BASE    0xb1010000
 #define  SEP6200_DMAC2_BASE  0xb1011000
 #define  SEP6200_ESRAM_BASE  0xb2000000
-#define	 SEP6200_NORREG_BASE0xb2020000
-#define	 SEP6200_SDIO1_BASE	0xb2022000
-#define	 SEP6200_SDIO2_BASE	0xb2023000
-#define	 SEP6200_LCDC_BASE	0xb2025000
-#define	 SEP6200_VPU_BASE	0xb2026000
-#define	 SEP6200_DMAC1_BASE	0xb2027000
-#define	 SEP6200_DDR2_REG	0xb3000000
-#define	 SEP6200_DDR_MEM	0x40000000
+#define  SEP6200_NORREG_BASE0xb2020000
+#define  SEP6200_SDIO1_BASE 0xb2022000
+#define  SEP6200_SDIO2_BASE 0xb2023000
+#define  SEP6200_LCDC_BASE  0xb2025000
+#define  SEP6200_VPU_BASE   0xb2026000
+#define  SEP6200_DMAC1_BASE 0xb2027000
+#define  SEP6200_DDR2_REG   0xb3000000
+#define  SEP6200_DDR_MEM    0x40000000
 
-#define SEP6200_UART0_DLBL	(SEP6200_UART0_BASE+0x00)
-#define SEP6200_UART0_RXFIFO	(SEP6200_UART0_BASE+0x00)
-#define SEP6200_UART0_TXFIFO	(SEP6200_UART0_BASE+0x00)
-#define SEP6200_UART0_DLBH	(SEP6200_UART0_BASE+0x04)
-#define SEP6200_UART0_IER	(SEP6200_UART0_BASE+0x04)
-#define SEP6200_UART0_IIR	(SEP6200_UART0_BASE+0x08)
-#define SEP6200_UART0_FCR	(SEP6200_UART0_BASE+0x08)
-#define SEP6200_UART0_LCR	(SEP6200_UART0_BASE+0x0c)
-#define SEP6200_UART0_MCR	(SEP6200_UART0_BASE+0x10)
-#define SEP6200_UART0_LSR	(SEP6200_UART0_BASE+0x14)
-#define SEP6200_UART0_MSR	(SEP6200_UART0_BASE+0x18)
+#define SEP6200_UART0_DLBL  (SEP6200_UART0_BASE+0x00)
+#define SEP6200_UART0_RXFIFO    (SEP6200_UART0_BASE+0x00)
+#define SEP6200_UART0_TXFIFO    (SEP6200_UART0_BASE+0x00)
+#define SEP6200_UART0_DLBH  (SEP6200_UART0_BASE+0x04)
+#define SEP6200_UART0_IER   (SEP6200_UART0_BASE+0x04)
+#define SEP6200_UART0_IIR   (SEP6200_UART0_BASE+0x08)
+#define SEP6200_UART0_FCR   (SEP6200_UART0_BASE+0x08)
+#define SEP6200_UART0_LCR   (SEP6200_UART0_BASE+0x0c)
+#define SEP6200_UART0_MCR   (SEP6200_UART0_BASE+0x10)
+#define SEP6200_UART0_LSR   (SEP6200_UART0_BASE+0x14)
+#define SEP6200_UART0_MSR   (SEP6200_UART0_BASE+0x18)
 
 
 #define    SEP6200_TIMER_T1LCR              (SEP6200_TIMER_BASE + 0X000)
@@ -362,7 +348,7 @@ typedef    void                 (*FP)();   /* program start address */
 
 #ifndef    _BOOL_TYPE_
 #define    _BOOL_TYPE_
-typedef    int                  BOOL;	     /* Boolean value.  TRUE (1) or FALSE (0). */
+typedef    int                  BOOL;        /* Boolean value.  TRUE (1) or FALSE (0). */
 #endif
 
 typedef    int                  ER;         /* Error code.  A signed integer. */
@@ -382,88 +368,88 @@ typedef    int                  ER;         /* Error code.  A signed integer. */
 /*Macros for debug*/
 
 #define EOUT(fmt,...) \
-	do \
-	{ 	\
-		rt_kprintf("EOUT:(%s:%i)  ",__FILE__,__LINE__); \
-		rt_kprintf(fmt,##__VA_ARGS__); \
-	}while(0)
+    do \
+    {   \
+        rt_kprintf("EOUT:(%s:%i)  ",__FILE__,__LINE__); \
+        rt_kprintf(fmt,##__VA_ARGS__); \
+    }while(0)
 
 #define RT_DEBUG
 #ifdef RT_DEBUG
-	#define DBOUT(fmt,...) \
-	do \
-	{ 	\
-		rt_kprintf("DBOUT:(%s:%i)  ",__FILE__,__LINE__); \
-		rt_kprintf(fmt,##__VA_ARGS__); \
-	}while(0)
+    #define DBOUT(fmt,...) \
+    do \
+    {   \
+        rt_kprintf("DBOUT:(%s:%i)  ",__FILE__,__LINE__); \
+        rt_kprintf(fmt,##__VA_ARGS__); \
+    }while(0)
 #else
-	#define DBOUT(fmt,...) \
-	do{}while(0)
+    #define DBOUT(fmt,...) \
+    do{}while(0)
 #endif
 
-#ifdef	RT_DEBUG
-	#define ASSERT(arg) \
-	if((arg) == 0) \
-	{		\
-		while(1) \
-		{		  \
-			rt_kprintf("have a assert failure\n"); \
-		}										 \
-	}
+#ifdef  RT_DEBUG
+    #define ASSERT(arg) \
+    if((arg) == 0) \
+    {       \
+        while(1) \
+        {         \
+            rt_kprintf("have a assert failure\n"); \
+        }                                        \
+    }
 #else
-	#define ASSERT(arg) \
-	do		\
-	{		 \
-	}while(0)
+    #define ASSERT(arg) \
+    do      \
+    {        \
+    }while(0)
 #endif
 
 
 #define write_reg(reg,value) \
-	do \
-	{ \
-		*(RP)(reg) = value; \
-	}while(0)
+    do \
+    { \
+        *(RP)(reg) = value; \
+    }while(0)
 
 #define read_reg(reg) (*(RP)reg)
 
 
 struct rt_hw_register
 {
-	rt_uint32_t r0;
-	rt_uint32_t r1;
-	rt_uint32_t r2;
-	rt_uint32_t r3;
-	rt_uint32_t r4;
-	rt_uint32_t r5;
-	rt_uint32_t r6;
-	rt_uint32_t r7;
-	rt_uint32_t r8;
-	rt_uint32_t r9;
-	rt_uint32_t r10;
-	rt_uint32_t r11;
-	rt_uint32_t r12;
-	rt_uint32_t r13;
-	rt_uint32_t r14;
-	rt_uint32_t r15;
-	rt_uint32_t r16;
-	rt_uint32_t r17;
-	rt_uint32_t r18;
-	rt_uint32_t r19;
-	rt_uint32_t r20;
-	rt_uint32_t r21;
-	rt_uint32_t r22;
-	rt_uint32_t r23;
-	rt_uint32_t r24;
-	rt_uint32_t sb;
-	rt_uint32_t sl;
-	rt_uint32_t fp;
-	rt_uint32_t ip;
-	rt_uint32_t sp;
-	rt_uint32_t lr;
-	rt_uint32_t pc;
-	rt_uint32_t asr;
-	rt_uint32_t bsr;
-	rt_uint32_t ORIG_r0;
+    rt_uint32_t r0;
+    rt_uint32_t r1;
+    rt_uint32_t r2;
+    rt_uint32_t r3;
+    rt_uint32_t r4;
+    rt_uint32_t r5;
+    rt_uint32_t r6;
+    rt_uint32_t r7;
+    rt_uint32_t r8;
+    rt_uint32_t r9;
+    rt_uint32_t r10;
+    rt_uint32_t r11;
+    rt_uint32_t r12;
+    rt_uint32_t r13;
+    rt_uint32_t r14;
+    rt_uint32_t r15;
+    rt_uint32_t r16;
+    rt_uint32_t r17;
+    rt_uint32_t r18;
+    rt_uint32_t r19;
+    rt_uint32_t r20;
+    rt_uint32_t r21;
+    rt_uint32_t r22;
+    rt_uint32_t r23;
+    rt_uint32_t r24;
+    rt_uint32_t sb;
+    rt_uint32_t sl;
+    rt_uint32_t fp;
+    rt_uint32_t ip;
+    rt_uint32_t sp;
+    rt_uint32_t lr;
+    rt_uint32_t pc;
+    rt_uint32_t asr;
+    rt_uint32_t bsr;
+    rt_uint32_t ORIG_r0;
 };
 
 /*@}*/
diff --git a/libcpu/unicore32/sep6200/serial.c b/libcpu/unicore32/sep6200/serial.c
index 518257b617..f91834b6a7 100644
--- a/libcpu/unicore32/sep6200/serial.c
+++ b/libcpu/unicore32/sep6200/serial.c
@@ -1,25 +1,11 @@
 /*
- * File      : serial.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2013-03-16	    Peng Fan     Modified from sep4020
+ * 2013-03-16       Peng Fan     Modified from sep4020
  */
 #include 
 #include 
@@ -36,204 +22,204 @@
  */
 static rt_err_t rt_serial_init (rt_device_t dev)
 {
-	struct serial_device* uart = (struct serial_device*) dev->user_data;
+    struct serial_device* uart = (struct serial_device*) dev->user_data;
 
-	if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
-	{
+    if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
+    {
 
-		if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-		{
-			rt_memset(uart->int_rx->rx_buffer, 0,
-				sizeof(uart->int_rx->rx_buffer));
-			uart->int_rx->read_index = uart->int_rx->save_index = 0;
-		}
+        if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+        {
+            rt_memset(uart->int_rx->rx_buffer, 0,
+                sizeof(uart->int_rx->rx_buffer));
+            uart->int_rx->read_index = uart->int_rx->save_index = 0;
+        }
 
-		if (dev->flag & RT_DEVICE_FLAG_INT_TX)
-		{
-			rt_memset(uart->int_tx->tx_buffer, 0,
-				sizeof(uart->int_tx->tx_buffer));
-			uart->int_tx->write_index = uart->int_tx->save_index = 0;
-		}
+        if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+        {
+            rt_memset(uart->int_tx->tx_buffer, 0,
+                sizeof(uart->int_tx->tx_buffer));
+            uart->int_tx->write_index = uart->int_tx->save_index = 0;
+        }
 
-		dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
-	}
+        dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 /* save a char to serial buffer */
 static void rt_serial_savechar(struct serial_device* uart, char ch)
 {
-	rt_base_t level;
+    rt_base_t level;
 
-	/* disable interrupt */
-	level = rt_hw_interrupt_disable();
+    /* disable interrupt */
+    level = rt_hw_interrupt_disable();
 
-	uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch;
-	uart->int_rx->save_index ++;
-	if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
-		uart->int_rx->save_index = 0;
+    uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch;
+    uart->int_rx->save_index ++;
+    if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
+        uart->int_rx->save_index = 0;
 
-	/* if the next position is read index, discard this 'read char' */
-	if (uart->int_rx->save_index == uart->int_rx->read_index)
-	{
-		uart->int_rx->read_index ++;
-		if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
-			uart->int_rx->read_index = 0;
-	}
+    /* if the next position is read index, discard this 'read char' */
+    if (uart->int_rx->save_index == uart->int_rx->read_index)
+    {
+        uart->int_rx->read_index ++;
+        if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+            uart->int_rx->read_index = 0;
+    }
 
-	/* enable interrupt */
-	rt_hw_interrupt_enable(level);
+    /* enable interrupt */
+    rt_hw_interrupt_enable(level);
 }
 
 static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
 {
-	RT_ASSERT(dev != RT_NULL);
-	return RT_EOK;
+    RT_ASSERT(dev != RT_NULL);
+    return RT_EOK;
 }
 
 static rt_err_t rt_serial_close(rt_device_t dev)
 {
-	RT_ASSERT(dev != RT_NULL);
-	return RT_EOK;
+    RT_ASSERT(dev != RT_NULL);
+    return RT_EOK;
 }
 
 static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
 {
-	rt_uint8_t* ptr;
-	rt_err_t err_code;
-	struct serial_device* uart;
+    rt_uint8_t* ptr;
+    rt_err_t err_code;
+    struct serial_device* uart;
 
-	ptr = buffer;
-	err_code = RT_EOK;
-	uart = (struct serial_device*)dev->user_data;
+    ptr = buffer;
+    err_code = RT_EOK;
+    uart = (struct serial_device*)dev->user_data;
 
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		rt_base_t level;
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        rt_base_t level;
 
-		/* interrupt mode Rx */
-		while (size)
-		{
-			if (uart->int_rx->read_index != uart->int_rx->save_index)
-			{
-				*ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index];
-				size --;
+        /* interrupt mode Rx */
+        while (size)
+        {
+            if (uart->int_rx->read_index != uart->int_rx->save_index)
+            {
+                *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index];
+                size --;
 
-				/* disable interrupt */
-				level = rt_hw_interrupt_disable();
+                /* disable interrupt */
+                level = rt_hw_interrupt_disable();
 
-				uart->int_rx->read_index ++;
-				if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
-					uart->int_rx->read_index = 0;
+                uart->int_rx->read_index ++;
+                if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+                    uart->int_rx->read_index = 0;
 
-				/* enable interrupt */
-				rt_hw_interrupt_enable(level);
-			}
-			else
-			{
-				/* set error code */
-				err_code = -RT_EEMPTY;
-				break;
-			}
-		}
-	}
-	else
-	{
-		/* polling mode */
-		while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
-		{
-			while (uart->uart_device->lsr & USTAT_RCV_READY)
-			{
-				*ptr = uart->uart_device->dlbl_fifo.txfifo & 0xff;
-				ptr ++;
-			}
-		}
-	}
+                /* enable interrupt */
+                rt_hw_interrupt_enable(level);
+            }
+            else
+            {
+                /* set error code */
+                err_code = -RT_EEMPTY;
+                break;
+            }
+        }
+    }
+    else
+    {
+        /* polling mode */
+        while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
+        {
+            while (uart->uart_device->lsr & USTAT_RCV_READY)
+            {
+                *ptr = uart->uart_device->dlbl_fifo.txfifo & 0xff;
+                ptr ++;
+            }
+        }
+    }
 
-	/* set error code */
-	rt_set_errno(err_code);
-	return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+    /* set error code */
+    rt_set_errno(err_code);
+    return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
 }
 
 static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
 {
-	rt_uint8_t* ptr;
-	rt_err_t err_code;
-	struct serial_device* uart;
+    rt_uint8_t* ptr;
+    rt_err_t err_code;
+    struct serial_device* uart;
 
-	err_code = RT_EOK;
-	ptr = (rt_uint8_t*)buffer;
-	uart = (struct serial_device*)dev->user_data;
+    err_code = RT_EOK;
+    ptr = (rt_uint8_t*)buffer;
+    uart = (struct serial_device*)dev->user_data;
 
-	if (dev->flag & RT_DEVICE_FLAG_INT_TX)
-	{
-		/* interrupt mode Tx */
-		while (uart->int_tx->save_index != uart->int_tx->write_index)
-		{
-			/* save on tx buffer */
-			uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++;
+    if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+    {
+        /* interrupt mode Tx */
+        while (uart->int_tx->save_index != uart->int_tx->write_index)
+        {
+            /* save on tx buffer */
+            uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++;
 
-			-- size;
+            -- size;
 
-			/* move to next position */
-			uart->int_tx->save_index ++;
+            /* move to next position */
+            uart->int_tx->save_index ++;
 
-			/* wrap save index */
-			if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE)
-				uart->int_tx->save_index = 0;
-		}
+            /* wrap save index */
+            if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE)
+                uart->int_tx->save_index = 0;
+        }
 
-		/* set error code */
-		if (size > 0)
-			err_code = -RT_EFULL;
-	}
-	else
-	{
-		/* polling mode */
-		while (size)
-		{
-			/*
-			 * to be polite with serial console add a line feed
-			 * to the carriage return character
-			 */
-			if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM))
-			{
-				while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY));
-				uart->uart_device->dlbl_fifo.txfifo = '\r';
-			}
+        /* set error code */
+        if (size > 0)
+            err_code = -RT_EFULL;
+    }
+    else
+    {
+        /* polling mode */
+        while (size)
+        {
+            /*
+             * to be polite with serial console add a line feed
+             * to the carriage return character
+             */
+            if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM))
+            {
+                while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY));
+                uart->uart_device->dlbl_fifo.txfifo = '\r';
+            }
 
-			while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY));
-			uart->uart_device->dlbl_fifo.txfifo = (*ptr & 0x1FF);
+            while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY));
+            uart->uart_device->dlbl_fifo.txfifo = (*ptr & 0x1FF);
 
-			++ptr; --size;
-		}
-	}
+            ++ptr; --size;
+        }
+    }
 
-	/* set error code */
-	rt_set_errno(err_code);
+    /* set error code */
+    rt_set_errno(err_code);
 
-	return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+    return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
 }
 
 static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args)
 {
-	RT_ASSERT(dev != RT_NULL);
+    RT_ASSERT(dev != RT_NULL);
 
-	switch (cmd)
-	{
-	case RT_DEVICE_CTRL_SUSPEND:
-		/* suspend device */
-		dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
-		break;
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_SUSPEND:
+        /* suspend device */
+        dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
+        break;
 
-	case RT_DEVICE_CTRL_RESUME:
-		/* resume device */
-		dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
-		break;
-	}
+    case RT_DEVICE_CTRL_RESUME:
+        /* resume device */
+        dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
+        break;
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 /*
@@ -241,49 +227,49 @@ static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args)
  */
 rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial)
 {
-	RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(device != RT_NULL);
 
-	device->type 		= RT_Device_Class_Char;
-	device->rx_indicate = RT_NULL;
-	device->tx_complete = RT_NULL;
-	device->init 		= rt_serial_init;
-	device->open		= rt_serial_open;
-	device->close		= rt_serial_close;
-	device->read 		= rt_serial_read;
-	device->write 		= rt_serial_write;
-	device->control 	= rt_serial_control;
-	device->user_data   = serial;
+    device->type        = RT_Device_Class_Char;
+    device->rx_indicate = RT_NULL;
+    device->tx_complete = RT_NULL;
+    device->init        = rt_serial_init;
+    device->open        = rt_serial_open;
+    device->close       = rt_serial_close;
+    device->read        = rt_serial_read;
+    device->write       = rt_serial_write;
+    device->control     = rt_serial_control;
+    device->user_data   = serial;
 
-	/* register a character device */
-	return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
+    /* register a character device */
+    return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
 }
 
 /* ISR for serial interrupt */
 void rt_hw_serial_isr(rt_device_t device)
 {
-	struct serial_device* uart = (struct serial_device*) device->user_data;
+    struct serial_device* uart = (struct serial_device*) device->user_data;
 
-	/* interrupt mode receive */
-	RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
+    /* interrupt mode receive */
+    RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
 
-	/* save on rx buffer */
-	while (uart->uart_device->lsr & USTAT_RCV_READY)
-	{
-		rt_serial_savechar(uart, uart->uart_device->dlbl_fifo.rxfifo & 0xff);
-	}
+    /* save on rx buffer */
+    while (uart->uart_device->lsr & USTAT_RCV_READY)
+    {
+        rt_serial_savechar(uart, uart->uart_device->dlbl_fifo.rxfifo & 0xff);
+    }
 
-	/* invoke callback */
-	if (device->rx_indicate != RT_NULL)
-	{
-		rt_size_t rx_length;
+    /* invoke callback */
+    if (device->rx_indicate != RT_NULL)
+    {
+        rt_size_t rx_length;
 
-		/* get rx length */
-		rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
-			UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
-			uart->int_rx->save_index - uart->int_rx->read_index;
+        /* get rx length */
+        rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
+            UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
+            uart->int_rx->save_index - uart->int_rx->read_index;
 
-		device->rx_indicate(device, rx_length);
-	}
+        device->rx_indicate(device, rx_length);
+    }
 }
 
 /*@}*/
diff --git a/libcpu/unicore32/sep6200/serial.h b/libcpu/unicore32/sep6200/serial.h
index e626f5e20f..dcfdc517d4 100644
--- a/libcpu/unicore32/sep6200/serial.h
+++ b/libcpu/unicore32/sep6200/serial.h
@@ -1,21 +1,7 @@
 /*
- * File      : serial.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -30,73 +16,73 @@
 
 #include 
 
-#define	USTAT_RCV_READY		0x01   	/* receive data ready */
-#define USTAT_OVERRUN		0x02	/* overrun */
-#define USTAT_PARITY_ERR	0x04	/* parity error */
-#define USTAT_FRAME_ERROR	0x08	/* frame error */
-#define USTAT_BREAK		0x10	/* break */
-#define	USTAT_TXB_EMPTY		0x40   	/* tx buffer empty */
-#define USTAT_RCV_ERR		0x80	/* receive error */
+#define USTAT_RCV_READY     0x01    /* receive data ready */
+#define USTAT_OVERRUN       0x02    /* overrun */
+#define USTAT_PARITY_ERR    0x04    /* parity error */
+#define USTAT_FRAME_ERROR   0x08    /* frame error */
+#define USTAT_BREAK     0x10    /* break */
+#define USTAT_TXB_EMPTY     0x40    /* tx buffer empty */
+#define USTAT_RCV_ERR       0x80    /* receive error */
 
-#define BPS					115200	/* serial baudrate */
+#define BPS                 115200  /* serial baudrate */
 
-#define UART_RX_BUFFER_SIZE		64
-#define UART_TX_BUFFER_SIZE		64
+#define UART_RX_BUFFER_SIZE     64
+#define UART_TX_BUFFER_SIZE     64
 
 /*For sep6200's uart have several secondary function*/
 /*we use union to decribe it*/
 
 union dlbl_fifo
 {
-	rt_uint32_t dlbl;
-	rt_uint32_t rxfifo;
-	rt_uint32_t txfifo;
+    rt_uint32_t dlbl;
+    rt_uint32_t rxfifo;
+    rt_uint32_t txfifo;
 };
 
 union dlbh_ier
 {
-	rt_uint32_t dlbh;
-	rt_uint32_t ier;
+    rt_uint32_t dlbh;
+    rt_uint32_t ier;
 };
 
 union iir_fcr
 {
-	rt_uint32_t iir;
-	rt_uint32_t fcr;
+    rt_uint32_t iir;
+    rt_uint32_t fcr;
 };
 
 struct serial_int_rx
 {
-	rt_uint8_t  rx_buffer[UART_RX_BUFFER_SIZE];
-	rt_uint32_t read_index, save_index;
+    rt_uint8_t  rx_buffer[UART_RX_BUFFER_SIZE];
+    rt_uint32_t read_index, save_index;
 };
 
 struct serial_int_tx
 {
-	rt_uint8_t  tx_buffer[UART_TX_BUFFER_SIZE];
-	rt_uint32_t write_index, save_index;
+    rt_uint8_t  tx_buffer[UART_TX_BUFFER_SIZE];
+    rt_uint32_t write_index, save_index;
 };
 
 typedef struct uartport
 {
-	union dlbl_fifo dlbl_fifo;
-	union dlbh_ier	dlbh_ier;
-	union iir_fcr	iir_fcr;
-	rt_uint32_t lcr;
-	rt_uint32_t mcr;
-	rt_uint32_t lsr;
-	rt_uint32_t msr;
+    union dlbl_fifo dlbl_fifo;
+    union dlbh_ier  dlbh_ier;
+    union iir_fcr   iir_fcr;
+    rt_uint32_t lcr;
+    rt_uint32_t mcr;
+    rt_uint32_t lsr;
+    rt_uint32_t msr;
 }uartport;
 
 struct serial_device
 {
-	uartport* uart_device;
+    uartport* uart_device;
 
-	/* rx structure */
-	struct serial_int_rx* int_rx;
+    /* rx structure */
+    struct serial_int_rx* int_rx;
 
-	/* tx structure */
-	struct serial_int_tx* int_tx;
+    /* tx structure */
+    struct serial_int_tx* int_tx;
 };
 
 rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial);
diff --git a/libcpu/unicore32/sep6200/stack.c b/libcpu/unicore32/sep6200/stack.c
index 722f40835e..049b075f6c 100644
--- a/libcpu/unicore32/sep6200/stack.c
+++ b/libcpu/unicore32/sep6200/stack.c
@@ -1,21 +1,7 @@
 /*
- * File      : stack.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -42,47 +28,47 @@
  */
 
 rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
-	rt_uint8_t *stack_addr, void *texit)
+    rt_uint8_t *stack_addr, void *texit)
 {
-	rt_uint32_t *stk;
+    rt_uint32_t *stk;
 
-	stk 	 = (rt_uint32_t*)stack_addr;
-	*(stk) 	 = (rt_uint32_t)tentry;			/* entry point */
-	*(--stk) = (rt_uint32_t)texit;			/* lr */
-	*(--stk) = 0;							/* r28 */
-	*(--stk) = 0;							/* r27 */
-	*(--stk) = 0;							/* r26 */
-	*(--stk) = 0;							/* r25 */
-	*(--stk) = 0;							/* r24 */
-	*(--stk) = 0;							/* r23 */
-	*(--stk) = 0;							/* r22 */
-	*(--stk) = 0;							/* r21 */
-	*(--stk) = 0;							/* r20 */
-	*(--stk) = 0;							/* r19 */
-	*(--stk) = 0;							/* r18 */
-	*(--stk) = 0;							/* r17 */
-	*(--stk) = 0;							/* r16 */
-	*(--stk) = 0;							/* r15 */
-	*(--stk) = 0;							/* r14 */
-	*(--stk) = 0;							/* r13 */
-	*(--stk) = 0;							/* r12 */
-	*(--stk) = 0;							/* r11 */
-	*(--stk) = 0;							/* r10 */
-	*(--stk) = 0;							/* r9 */
-	*(--stk) = 0;							/* r8 */
-	*(--stk) = 0;							/* r7 */
-	*(--stk) = 0;							/* r6 */
-	*(--stk) = 0;							/* r5 */
-	*(--stk) = 0;							/* r4 */
-	*(--stk) = 0;							/* r3 */
-	*(--stk) = 0;							/* r2 */
-	*(--stk) = 0;							/* r1 */
-	*(--stk) = (rt_uint32_t)parameter; /* r0 : argument */
-	*(--stk) = Mode_PRIV;					/* asr */
-	*(--stk) = Mode_PRIV;					/* bsr */ /*why both PRIV do not need switch?*/
+    stk      = (rt_uint32_t*)stack_addr;
+    *(stk)   = (rt_uint32_t)tentry;         /* entry point */
+    *(--stk) = (rt_uint32_t)texit;          /* lr */
+    *(--stk) = 0;                           /* r28 */
+    *(--stk) = 0;                           /* r27 */
+    *(--stk) = 0;                           /* r26 */
+    *(--stk) = 0;                           /* r25 */
+    *(--stk) = 0;                           /* r24 */
+    *(--stk) = 0;                           /* r23 */
+    *(--stk) = 0;                           /* r22 */
+    *(--stk) = 0;                           /* r21 */
+    *(--stk) = 0;                           /* r20 */
+    *(--stk) = 0;                           /* r19 */
+    *(--stk) = 0;                           /* r18 */
+    *(--stk) = 0;                           /* r17 */
+    *(--stk) = 0;                           /* r16 */
+    *(--stk) = 0;                           /* r15 */
+    *(--stk) = 0;                           /* r14 */
+    *(--stk) = 0;                           /* r13 */
+    *(--stk) = 0;                           /* r12 */
+    *(--stk) = 0;                           /* r11 */
+    *(--stk) = 0;                           /* r10 */
+    *(--stk) = 0;                           /* r9 */
+    *(--stk) = 0;                           /* r8 */
+    *(--stk) = 0;                           /* r7 */
+    *(--stk) = 0;                           /* r6 */
+    *(--stk) = 0;                           /* r5 */
+    *(--stk) = 0;                           /* r4 */
+    *(--stk) = 0;                           /* r3 */
+    *(--stk) = 0;                           /* r2 */
+    *(--stk) = 0;                           /* r1 */
+    *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */
+    *(--stk) = Mode_PRIV;                   /* asr */
+    *(--stk) = Mode_PRIV;                   /* bsr */ /*why both PRIV do not need switch?*/
 
-	/* return task's current stack address */
-	return (rt_uint8_t *)stk;
+    /* return task's current stack address */
+    return (rt_uint8_t *)stk;
 }
 
 /*@}*/
diff --git a/libcpu/unicore32/sep6200/start_gcc.S b/libcpu/unicore32/sep6200/start_gcc.S
index 4dd17aa387..11676e875c 100644
--- a/libcpu/unicore32/sep6200/start_gcc.S
+++ b/libcpu/unicore32/sep6200/start_gcc.S
@@ -1,21 +1,7 @@
 /*
- * File      : start.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/libcpu/unicore32/sep6200/trace.c b/libcpu/unicore32/sep6200/trace.c
index 8f11a18a17..d83447c291 100644
--- a/libcpu/unicore32/sep6200/trace.c
+++ b/libcpu/unicore32/sep6200/trace.c
@@ -1,21 +1,7 @@
 /*
- * File      : trace.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
diff --git a/libcpu/unicore32/sep6200/trap.c b/libcpu/unicore32/sep6200/trap.c
index 1e5d02a279..f2f342cfbe 100644
--- a/libcpu/unicore32/sep6200/trap.c
+++ b/libcpu/unicore32/sep6200/trap.c
@@ -1,21 +1,7 @@
 /*
- * File      : trap.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -42,16 +28,16 @@ extern struct rt_thread *rt_current_thread;
 
 void rt_hw_show_register (struct rt_hw_register *regs)
 {
-	rt_kprintf("Execption:\n");
-	rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
-	rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
-	rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x r11:0x%08x\n", regs->r8, regs->r9, regs->r10,regs->r11);
-	rt_kprintf("r12:0x%08x r13:0x%08x r14:0x%08x r15:0x%08x\n", regs->r12,regs->r13,regs->r14,regs->r15);
-	rt_kprintf("r16:0x%08x r17:0x%08x r18:0x%08x r19:0x%08x\n", regs->r16,regs->r17,regs->r18,regs->r19);
-	rt_kprintf("r20:0x%08x r21:0x%08x r22:0x%08x r23:0x%08x\n", regs->r20,regs->r21,regs->r22,regs->r23);
-	rt_kprintf("r24:0x%08x sb:0x%08x  sl:0x%08xfp :0x%08x ip :0x%08x\n",regs->r24,regs->sb,regs->sl,regs->fp,regs->ip);
-	rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
-	rt_kprintf("asr:0x%08x bsr:0x%08x\n", regs->asr,regs->bsr);
+    rt_kprintf("Execption:\n");
+    rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
+    rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
+    rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x r11:0x%08x\n", regs->r8, regs->r9, regs->r10,regs->r11);
+    rt_kprintf("r12:0x%08x r13:0x%08x r14:0x%08x r15:0x%08x\n", regs->r12,regs->r13,regs->r14,regs->r15);
+    rt_kprintf("r16:0x%08x r17:0x%08x r18:0x%08x r19:0x%08x\n", regs->r16,regs->r17,regs->r18,regs->r19);
+    rt_kprintf("r20:0x%08x r21:0x%08x r22:0x%08x r23:0x%08x\n", regs->r20,regs->r21,regs->r22,regs->r23);
+    rt_kprintf("r24:0x%08x sb:0x%08x  sl:0x%08xfp :0x%08x ip :0x%08x\n",regs->r24,regs->sb,regs->sl,regs->fp,regs->ip);
+    rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
+    rt_kprintf("asr:0x%08x bsr:0x%08x\n", regs->asr,regs->bsr);
 }
 
 /**
@@ -64,13 +50,13 @@ void rt_hw_show_register (struct rt_hw_register *regs)
  */
 void rt_hw_trap_extn(struct rt_hw_register *regs)
 {
-	rt_hw_show_register(regs);
+    rt_hw_show_register(regs);
 
-	rt_kprintf("extn instruction\n");
-	rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
-	rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry);
+    rt_kprintf("extn instruction\n");
+    rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
+    rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry);
 
-	rt_hw_cpu_shutdown();
+    rt_hw_cpu_shutdown();
 }
 
 /**
@@ -84,10 +70,10 @@ void rt_hw_trap_extn(struct rt_hw_register *regs)
  */
 void rt_hw_trap_swi(struct rt_hw_register *regs)
 {
-	rt_hw_show_register(regs);
+    rt_hw_show_register(regs);
 
-	rt_kprintf("software interrupt\n");
-	rt_hw_cpu_shutdown();
+    rt_kprintf("software interrupt\n");
+    rt_hw_cpu_shutdown();
 }
 
 /**
@@ -100,13 +86,13 @@ void rt_hw_trap_swi(struct rt_hw_register *regs)
  */
 void rt_hw_trap_pabt(struct rt_hw_register *regs)
 {
-	rt_hw_show_register(regs);
+    rt_hw_show_register(regs);
 
-	rt_kprintf("prefetch abort\n");
-	rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
-	rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry);
+    rt_kprintf("prefetch abort\n");
+    rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
+    rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry);
 
-	rt_hw_cpu_shutdown();
+    rt_hw_cpu_shutdown();
 }
 
 /**
@@ -119,13 +105,13 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs)
  */
 void rt_hw_trap_dabt(struct rt_hw_register *regs)
 {
-	rt_hw_show_register(regs);
+    rt_hw_show_register(regs);
 
-	rt_kprintf("data abort\n");
-	rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
-	rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry);
+    rt_kprintf("data abort\n");
+    rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
+    rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry);
 
-	rt_hw_cpu_shutdown();
+    rt_hw_cpu_shutdown();
 }
 
 /**
@@ -137,9 +123,9 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs)
  */
 void rt_hw_trap_resv(struct rt_hw_register *regs)
 {
-	rt_kprintf("not used\n");
-	rt_hw_show_register(regs);
-	rt_hw_cpu_shutdown();
+    rt_kprintf("not used\n");
+    rt_hw_show_register(regs);
+    rt_hw_cpu_shutdown();
 }
 
 extern struct rt_irq_desc isr_table[];
@@ -152,7 +138,7 @@ void rt_hw_trap_irq(void)
   void *param;
 
   /* get the interrupt number */
-	irq = *(RP)(SEP6200_VIC_IRQ_VECTOR_NUM);
+    irq = *(RP)(SEP6200_VIC_IRQ_VECTOR_NUM);
 
   /* get interrupt service routine */
   isr_func = isr_table[irq].handler;
@@ -162,13 +148,13 @@ void rt_hw_trap_irq(void)
   isr_func(irq, param);
 
 #ifdef RT_USING_INTERRUPT_INFO
-	isr_table[irq].counter++;
+    isr_table[irq].counter++;
 #endif /* RT_USING_INTERRUPT_INFO */
 }
 
 void rt_hw_trap_fiq()
 {
-	rt_kprintf("fast interrupt request\n");
+    rt_kprintf("fast interrupt request\n");
 }
 
 /*@}*/
diff --git a/libcpu/xilinx/microblaze/cpu.c b/libcpu/xilinx/microblaze/cpu.c
index d37dcda350..37da5fd7c5 100755
--- a/libcpu/xilinx/microblaze/cpu.c
+++ b/libcpu/xilinx/microblaze/cpu.c
@@ -28,8 +28,8 @@ RT_WEAK void rt_hw_cpu_reset()
  */
 RT_WEAK void rt_hw_cpu_shutdown()
 {
-	rt_kprintf("shutdown...\n");
+    rt_kprintf("shutdown...\n");
 
-	while (1);
+    while (1);
 }
 
diff --git a/libcpu/xilinx/microblaze/serial.c b/libcpu/xilinx/microblaze/serial.c
index 17cca9f84d..1902f11710 100755
--- a/libcpu/xilinx/microblaze/serial.c
+++ b/libcpu/xilinx/microblaze/serial.c
@@ -12,7 +12,7 @@
  * 2006-08-23     Bernard      first version
  * 2009-05-14     Bernard      add RT-THread device interface
  *
- * 2011-12-17	  nl1031	   MicroBlaze
+ * 2011-12-17     nl1031       MicroBlaze
  */
 
 #include 
@@ -22,23 +22,23 @@
 typedef volatile rt_uint32_t REG32;
 struct rt_mb_uart_lite_hw
 {
-	REG32	 Rx_FIFO; 	// Receiver Holding Register
-	REG32	 Tx_FIFO; 	// Transmitter Holding Register
-	REG32	 STAT_REG; 	// Channel Status Register
-	REG32	 CTRL_REG; 	// Control Register
+    REG32    Rx_FIFO;   // Receiver Holding Register
+    REG32    Tx_FIFO;   // Transmitter Holding Register
+    REG32    STAT_REG;  // Channel Status Register
+    REG32    CTRL_REG;  // Control Register
 };
 
 struct rt_mb_uart_lite
 {
-	struct rt_device parent;
+    struct rt_device parent;
 
-	struct rt_mb_uart_lite_hw* hw_base;
-	rt_uint16_t peripheral_id;
-	rt_uint32_t baudrate;
+    struct rt_mb_uart_lite_hw* hw_base;
+    rt_uint16_t peripheral_id;
+    rt_uint32_t baudrate;
 
-	/* reception field */
-	rt_uint16_t save_index, read_index;
-	rt_uint8_t  rx_buffer[RT_UART_RX_BUFFER_SIZE];
+    /* reception field */
+    rt_uint16_t save_index, read_index;
+    rt_uint8_t  rx_buffer[RT_UART_RX_BUFFER_SIZE];
 };
 #ifdef RT_USING_UART1
 struct rt_mb_uart_lite serial1;
@@ -46,271 +46,271 @@ struct rt_mb_uart_lite serial1;
 
 static void rt_hw_serial_isr(void)
 {
-	unsigned int status;
-	rt_base_t level;
-	struct rt_device* device;
-	struct rt_mb_uart_lite* serial = RT_NULL;
+    unsigned int status;
+    rt_base_t level;
+    struct rt_device* device;
+    struct rt_mb_uart_lite* serial = RT_NULL;
 
 #ifdef RT_USING_UART1
-	/* serial 1 */
-	serial = &serial1;
+    /* serial 1 */
+    serial = &serial1;
 #endif
-	RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(serial != RT_NULL);
 
-	/* get generic device object */
-	device = (rt_device_t)serial;
+    /* get generic device object */
+    device = (rt_device_t)serial;
 
-	/* disable interrupt */
-	level = rt_hw_interrupt_disable();
+    /* disable interrupt */
+    level = rt_hw_interrupt_disable();
 
-	/* get uart status register */
-	status = serial->hw_base->STAT_REG;
-	while (status & XUL_SR_RX_FIFO_VALID_DATA)
-	{
-		/* get received character */
-		serial->rx_buffer[serial->save_index] = serial->hw_base->Rx_FIFO;
+    /* get uart status register */
+    status = serial->hw_base->STAT_REG;
+    while (status & XUL_SR_RX_FIFO_VALID_DATA)
+    {
+        /* get received character */
+        serial->rx_buffer[serial->save_index] = serial->hw_base->Rx_FIFO;
 
-		/* move to next position */
-		serial->save_index ++;
-		if (serial->save_index >= RT_UART_RX_BUFFER_SIZE)
-			serial->save_index = 0;
+        /* move to next position */
+        serial->save_index ++;
+        if (serial->save_index >= RT_UART_RX_BUFFER_SIZE)
+            serial->save_index = 0;
 
-		/* if the next position is read index, discard this 'read char' */
-		if (serial->save_index == serial->read_index)
-		{
-			serial->read_index ++;
-			if (serial->read_index >= RT_UART_RX_BUFFER_SIZE)
-				serial->read_index = 0;
-		}
-		status = serial->hw_base->STAT_REG;
-	}
-	/* enable interrupt */
-	rt_hw_interrupt_enable(level);
+        /* if the next position is read index, discard this 'read char' */
+        if (serial->save_index == serial->read_index)
+        {
+            serial->read_index ++;
+            if (serial->read_index >= RT_UART_RX_BUFFER_SIZE)
+                serial->read_index = 0;
+        }
+        status = serial->hw_base->STAT_REG;
+    }
+    /* enable interrupt */
+    rt_hw_interrupt_enable(level);
 
-	/* indicate to upper layer application */
-	if (device->rx_indicate != RT_NULL)
-		device->rx_indicate(device, 1);
+    /* indicate to upper layer application */
+    if (device->rx_indicate != RT_NULL)
+        device->rx_indicate(device, 1);
 
 }
 
 static rt_err_t rt_serial_init (rt_device_t dev)
 {
-	struct rt_mb_uart_lite* serial = (struct rt_mb_uart_lite*) dev;
+    struct rt_mb_uart_lite* serial = (struct rt_mb_uart_lite*) dev;
 
-	RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(serial != RT_NULL);
 
-	RT_ASSERT(serial->peripheral_id != XPAR_UARTLITE_1_DEVICE_ID);
+    RT_ASSERT(serial->peripheral_id != XPAR_UARTLITE_1_DEVICE_ID);
 
 
-	/* reset rx index */
-	serial->save_index = 0;
-	serial->read_index = 0;
+    /* reset rx index */
+    serial->save_index = 0;
+    serial->read_index = 0;
 
-	/* reset rx buffer */
-	rt_memset(serial->rx_buffer, 0, RT_UART_RX_BUFFER_SIZE);
+    /* reset rx buffer */
+    rt_memset(serial->rx_buffer, 0, RT_UART_RX_BUFFER_SIZE);
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
 {
-	struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev;
-	RT_ASSERT(serial != RT_NULL);
+    struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev;
+    RT_ASSERT(serial != RT_NULL);
 
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* enable UART rx interrupt */
-		serial->hw_base->CTRL_REG = XUL_CR_ENABLE_INTR; 		/* enable interrupt */
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* enable UART rx interrupt */
+        serial->hw_base->CTRL_REG = XUL_CR_ENABLE_INTR;         /* enable interrupt */
 
-		/* install UART handler */
-		rt_hw_interrupt_install(serial->peripheral_id, (rt_isr_handler_t)rt_hw_serial_isr, RT_NULL);
-		rt_hw_interrupt_umask(serial->peripheral_id);
-	}
+        /* install UART handler */
+        rt_hw_interrupt_install(serial->peripheral_id, (rt_isr_handler_t)rt_hw_serial_isr, RT_NULL);
+        rt_hw_interrupt_umask(serial->peripheral_id);
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_serial_close(rt_device_t dev)
 {
-	struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev;
-	RT_ASSERT(serial != RT_NULL);
+    struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev;
+    RT_ASSERT(serial != RT_NULL);
 
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* disable interrupt */
-		serial->hw_base->CTRL_REG =  0; 		/* RxReady interrupt */
-	}
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* disable interrupt */
+        serial->hw_base->CTRL_REG =  0;         /* RxReady interrupt */
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
 {
-	rt_uint8_t* ptr;
-	struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev;
-	RT_ASSERT(serial != RT_NULL);
+    rt_uint8_t* ptr;
+    struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev;
+    RT_ASSERT(serial != RT_NULL);
 
-	/* point to buffer */
-	ptr = (rt_uint8_t*) buffer;
+    /* point to buffer */
+    ptr = (rt_uint8_t*) buffer;
 
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		while (size)
-		{
-			/* interrupt receive */
-			rt_base_t level;
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        while (size)
+        {
+            /* interrupt receive */
+            rt_base_t level;
 
-			/* disable interrupt */
-			level = rt_hw_interrupt_disable();
-			if (serial->read_index != serial->save_index)
-			{
-				*ptr = serial->rx_buffer[serial->read_index];
+            /* disable interrupt */
+            level = rt_hw_interrupt_disable();
+            if (serial->read_index != serial->save_index)
+            {
+                *ptr = serial->rx_buffer[serial->read_index];
 
-				serial->read_index ++;
-				if (serial->read_index >= RT_UART_RX_BUFFER_SIZE)
-					serial->read_index = 0;
-			}
-			else
-			{
-				/* no data in rx buffer */
+                serial->read_index ++;
+                if (serial->read_index >= RT_UART_RX_BUFFER_SIZE)
+                    serial->read_index = 0;
+            }
+            else
+            {
+                /* no data in rx buffer */
 
-				/* enable interrupt */
-				rt_hw_interrupt_enable(level);
-				break;
-			}
+                /* enable interrupt */
+                rt_hw_interrupt_enable(level);
+                break;
+            }
 
-			/* enable interrupt */
-			rt_hw_interrupt_enable(level);
+            /* enable interrupt */
+            rt_hw_interrupt_enable(level);
 
-			ptr ++; size --;
-		}
+            ptr ++; size --;
+        }
 
-		return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-	}
-	else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
-	{
-		/* not support right now */
-		RT_ASSERT(0);
-	}
-	else
-	{
-		/* poll mode */
-		while (size)
-		{
-			/* Wait for Full Rx Buffer */
-			while (!(serial->hw_base->STAT_REG & XUL_SR_RX_FIFO_VALID_DATA));
+        return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+    }
+    else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
+    {
+        /* not support right now */
+        RT_ASSERT(0);
+    }
+    else
+    {
+        /* poll mode */
+        while (size)
+        {
+            /* Wait for Full Rx Buffer */
+            while (!(serial->hw_base->STAT_REG & XUL_SR_RX_FIFO_VALID_DATA));
 
-			/* Read Character */
-			*ptr = serial->hw_base->Rx_FIFO;
-			ptr ++;
-			size --;
-		}
+            /* Read Character */
+            *ptr = serial->hw_base->Rx_FIFO;
+            ptr ++;
+            size --;
+        }
 
-		return (rt_size_t)ptr - (rt_size_t)buffer;
-	}
+        return (rt_size_t)ptr - (rt_size_t)buffer;
+    }
 
-	return 0;
+    return 0;
 }
 
 static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
 {
-	rt_uint8_t* ptr;
-	struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev;
-	RT_ASSERT(serial != RT_NULL);
+    rt_uint8_t* ptr;
+    struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev;
+    RT_ASSERT(serial != RT_NULL);
 
-	ptr = (rt_uint8_t*) buffer;
-	if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY)
-	{
-		if (dev->flag & RT_DEVICE_FLAG_STREAM)
-		{
-			/* it's a stream mode device */
-			while (size)
-			{
-				/* stream mode */
-				if (*ptr == '\n')
-				{
-					while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY));
-					serial->hw_base->Tx_FIFO = '\r';
-				}
+    ptr = (rt_uint8_t*) buffer;
+    if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY)
+    {
+        if (dev->flag & RT_DEVICE_FLAG_STREAM)
+        {
+            /* it's a stream mode device */
+            while (size)
+            {
+                /* stream mode */
+                if (*ptr == '\n')
+                {
+                    while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY));
+                    serial->hw_base->Tx_FIFO = '\r';
+                }
 
-				/* Wait for Empty Tx Buffer */
-				while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY));
+                /* Wait for Empty Tx Buffer */
+                while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY));
 
-				/* Transmit Character */
-				serial->hw_base->Tx_FIFO = *ptr;
-				if (*ptr & 1)
-					rt_hw_board_led_on(2);
-				else
-					rt_hw_board_led_off(2);
-				ptr ++; size --;
-			}
-		}
-		else
-		{
-			while (size)
-			{
-				/* Wait for Empty Tx Buffer */
-				while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY));
+                /* Transmit Character */
+                serial->hw_base->Tx_FIFO = *ptr;
+                if (*ptr & 1)
+                    rt_hw_board_led_on(2);
+                else
+                    rt_hw_board_led_off(2);
+                ptr ++; size --;
+            }
+        }
+        else
+        {
+            while (size)
+            {
+                /* Wait for Empty Tx Buffer */
+                while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY));
 
-				/* Transmit Character */
-				serial->hw_base->Tx_FIFO = *ptr;
-				if (*ptr & 1)
-					rt_hw_board_led_on(2);
-				else
-					rt_hw_board_led_off(2);
-				ptr ++; size --;
-			}
-		}
-	}
+                /* Transmit Character */
+                serial->hw_base->Tx_FIFO = *ptr;
+                if (*ptr & 1)
+                    rt_hw_board_led_on(2);
+                else
+                    rt_hw_board_led_off(2);
+                ptr ++; size --;
+            }
+        }
+    }
 
-	return (rt_size_t)ptr - (rt_size_t)buffer;
+    return (rt_size_t)ptr - (rt_size_t)buffer;
 }
 
 static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 rt_err_t rt_hw_serial_init()
 {
-	rt_device_t device;
+    rt_device_t device;
 
 #ifndef RT_USING_CONSOLE
-	int Status;
+    int Status;
 
-	/*
-	 * Initialize the UartLite driver so that it is ready to use.
-	 */
-	Status = XUartLite_Initialize(&uart_lite, RS232_DEVICE_ID);
-	if (Status != XST_SUCCESS)
-	{
-		return;
-	}
+    /*
+     * Initialize the UartLite driver so that it is ready to use.
+     */
+    Status = XUartLite_Initialize(&uart_lite, RS232_DEVICE_ID);
+    if (Status != XST_SUCCESS)
+    {
+        return;
+    }
 
 #endif
 
 #ifdef RT_USING_UART1
-	device = (rt_device_t) &serial1;
+    device = (rt_device_t) &serial1;
 
-	/* init serial device private data */
-	serial1.hw_base 		= (struct rt_mb_uart_lite_hw*)XPAR_USB_UART_BASEADDR;
-	serial1.peripheral_id 	= XPAR_UARTLITE_1_DEVICE_ID;
-	serial1.baudrate		= 115200;
+    /* init serial device private data */
+    serial1.hw_base         = (struct rt_mb_uart_lite_hw*)XPAR_USB_UART_BASEADDR;
+    serial1.peripheral_id   = XPAR_UARTLITE_1_DEVICE_ID;
+    serial1.baudrate        = 115200;
 
-	/* set device virtual interface */
-	device->init 	= rt_serial_init;
-	device->open 	= rt_serial_open;
-	device->close 	= rt_serial_close;
-	device->read 	= rt_serial_read;
-	device->write 	= rt_serial_write;
-	device->control = rt_serial_control;
+    /* set device virtual interface */
+    device->init    = rt_serial_init;
+    device->open    = rt_serial_open;
+    device->close   = rt_serial_close;
+    device->read    = rt_serial_read;
+    device->write   = rt_serial_write;
+    device->control = rt_serial_control;
 
-	/* register uart1 on device subsystem */
-	rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
+    /* register uart1 on device subsystem */
+    rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
 #endif
 
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 
diff --git a/libcpu/xilinx/microblaze/stack.c b/libcpu/xilinx/microblaze/stack.c
index 686fc078a3..87f1dfa014 100755
--- a/libcpu/xilinx/microblaze/stack.c
+++ b/libcpu/xilinx/microblaze/stack.c
@@ -29,43 +29,43 @@ extern   void  *_SDA2_BASE_;
  * @return stack address
  */
 rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
-	rt_uint8_t *stack_addr, void *texit)
+    rt_uint8_t *stack_addr, void *texit)
 {
-	unsigned long *stk;
+    unsigned long *stk;
 
-	stk 	 = (unsigned long *)stack_addr;
-	stk--;
-	stk--;
-	*stk-- = 0;								/* r31 */
-	*stk-- = 0;								/* r30 */
-	*stk-- = 0;								/* r29 */
-	*stk-- = 0;								/* r28 */
-	*stk-- = 0;								/* r27 */
-	*stk-- = 0;								/* r26 */
-	*stk-- = 0;								/* r25 */
-	*stk-- = 0;								/* r24 */
-	*stk-- = 0;								/* r23 */
-	*stk-- = 0;								/* r22 */
-	*stk-- = 0;								/* r21 */
-	*stk-- = 0;								/* r20 */
-	*stk-- = 0;								/* r19 */
-	*stk-- = 0;								/* r18 */
-	*stk-- = 0;								/* r17 */
-	*stk-- = (unsigned long)texit - 8;		/* r15 = task return address*/
-	*stk-- = (unsigned long)tentry;		/* r14 = entry address*/
-	*stk-- = (unsigned long)&_SDA_BASE_;	/* r13 */
-	*stk-- = 0;								/* r12 */
-	*stk-- = 0;								/* r11 */
-	*stk-- = 0;								/* r10 */
-	*stk-- = 0;								/* r09 */
-	*stk-- = 0;								/* r08 */
-	*stk-- = 0;								/* r07 */
-	*stk-- = 0;								/* r06 */
-	*stk-- = (unsigned long) parameter;	/* r05 */
-	*stk-- = 0;								/* r04 */
-	*stk-- = 0;								/* r03 */
-	*stk-- = (unsigned long)&_SDA2_BASE_;	/* r02 */
-	*stk   = 2;   							/* enable interrupt */
-	return (rt_uint8_t *)stk;
+    stk      = (unsigned long *)stack_addr;
+    stk--;
+    stk--;
+    *stk-- = 0;                             /* r31 */
+    *stk-- = 0;                             /* r30 */
+    *stk-- = 0;                             /* r29 */
+    *stk-- = 0;                             /* r28 */
+    *stk-- = 0;                             /* r27 */
+    *stk-- = 0;                             /* r26 */
+    *stk-- = 0;                             /* r25 */
+    *stk-- = 0;                             /* r24 */
+    *stk-- = 0;                             /* r23 */
+    *stk-- = 0;                             /* r22 */
+    *stk-- = 0;                             /* r21 */
+    *stk-- = 0;                             /* r20 */
+    *stk-- = 0;                             /* r19 */
+    *stk-- = 0;                             /* r18 */
+    *stk-- = 0;                             /* r17 */
+    *stk-- = (unsigned long)texit - 8;      /* r15 = task return address*/
+    *stk-- = (unsigned long)tentry;     /* r14 = entry address*/
+    *stk-- = (unsigned long)&_SDA_BASE_;    /* r13 */
+    *stk-- = 0;                             /* r12 */
+    *stk-- = 0;                             /* r11 */
+    *stk-- = 0;                             /* r10 */
+    *stk-- = 0;                             /* r09 */
+    *stk-- = 0;                             /* r08 */
+    *stk-- = 0;                             /* r07 */
+    *stk-- = 0;                             /* r06 */
+    *stk-- = (unsigned long) parameter; /* r05 */
+    *stk-- = 0;                             /* r04 */
+    *stk-- = 0;                             /* r03 */
+    *stk-- = (unsigned long)&_SDA2_BASE_;   /* r02 */
+    *stk   = 2;                             /* enable interrupt */
+    return (rt_uint8_t *)stk;
 }
 
diff --git a/libcpu/xilinx/microblaze/trap.c b/libcpu/xilinx/microblaze/trap.c
index 3b3f98d105..bcfb3cc492 100755
--- a/libcpu/xilinx/microblaze/trap.c
+++ b/libcpu/xilinx/microblaze/trap.c
@@ -10,13 +10,13 @@
  * Change Logs:
  * Date           Author       Notes
  * 2006-08-23     Bernard      first version
- * 2011-12-17	  nl1031	   for MicroBlaze
+ * 2011-12-17     nl1031       for MicroBlaze
  *
  */
 
-#include 	
-#include 	"xparameters.h"
-#include 	"xintc.h"
+#include    
+#include    "xparameters.h"
+#include    "xintc.h"
 #include    "xintc_i.h"
 #include    "xintc_l.h"
 
@@ -33,7 +33,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag;
 
 void rt_hw_interrupt_handler(int vector)
 {
-	rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+    rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
 }
 
 /**
@@ -41,24 +41,24 @@ void rt_hw_interrupt_handler(int vector)
  */
 void rt_hw_interrupt_init()
 {
-	rt_base_t index;
+    rt_base_t index;
 
-	XIntc_Config           *CfgPtr;
+    XIntc_Config           *CfgPtr;
 
 
     CfgPtr = &XIntc_ConfigTable[0];
 
 
-	for (index = 0; index < MAX_HANDLERS; index ++)
-	{
-		CfgPtr->HandlerTable[index].Handler = (XInterruptHandler)rt_hw_interrupt_handler;
-	}
+    for (index = 0; index < MAX_HANDLERS; index ++)
+    {
+        CfgPtr->HandlerTable[index].Handler = (XInterruptHandler)rt_hw_interrupt_handler;
+    }
 
-	/* init interrupt nest, and context in thread sp */
-	rt_interrupt_nest = 0;
-	rt_interrupt_from_thread = 0;
-	rt_interrupt_to_thread = 0;
-	rt_thread_switch_interrupt_flag = 0;
+    /* init interrupt nest, and context in thread sp */
+    rt_interrupt_nest = 0;
+    rt_interrupt_from_thread = 0;
+    rt_interrupt_to_thread = 0;
+    rt_thread_switch_interrupt_flag = 0;
 }
 
 /**
@@ -67,8 +67,8 @@ void rt_hw_interrupt_init()
  */
 void rt_hw_interrupt_mask(int vector)
 {
-	/* disable interrupt */
-	XIntc_Disable(&int_ctl,vector);
+    /* disable interrupt */
+    XIntc_Disable(&int_ctl,vector);
 }
 
 /**
@@ -77,7 +77,7 @@ void rt_hw_interrupt_mask(int vector)
  */
 void rt_hw_interrupt_umask(int vector)
 {
-	XIntc_Enable(&int_ctl,vector);
+    XIntc_Enable(&int_ctl,vector);
 }
 
 /**
@@ -88,15 +88,15 @@ void rt_hw_interrupt_umask(int vector)
  */
 void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler)
 {
-	XIntc_Config           *CfgPtr;
+    XIntc_Config           *CfgPtr;
 
     CfgPtr = &XIntc_ConfigTable[0];
 
-	if(vector >= 0 && vector < MAX_HANDLERS)
-	{
-		if (*old_handler != RT_NULL) *old_handler = (rt_isr_handler_t)CfgPtr->HandlerTable[vector].Handler;
-		if (new_handler != RT_NULL) CfgPtr->HandlerTable[vector].Handler = (XInterruptHandler)new_handler;
-	}
+    if(vector >= 0 && vector < MAX_HANDLERS)
+    {
+        if (*old_handler != RT_NULL) *old_handler = (rt_isr_handler_t)CfgPtr->HandlerTable[vector].Handler;
+        if (new_handler != RT_NULL) CfgPtr->HandlerTable[vector].Handler = (XInterruptHandler)new_handler;
+    }
 }
 
 /*****************************************************************************/
@@ -117,7 +117,7 @@ void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_ha
 * calling an interrupt handler.
 *
 *
-* @return	None.
+* @return   None.
 *
 * @note
 *
@@ -131,81 +131,81 @@ void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_ha
 
 void rt_hw_trap_irq(void )
 {
-	u32 intr_status;
-	u32 intr_mask = 1;
-	int intr_number;
-	volatile u32 reg;			/* used as bit bucket */
-	XIntc_Config *cfg_ptr;
+    u32 intr_status;
+    u32 intr_mask = 1;
+    int intr_number;
+    volatile u32 reg;           /* used as bit bucket */
+    XIntc_Config *cfg_ptr;
 
 
-	/* Get the configuration data using the device ID */
-	cfg_ptr = &XIntc_ConfigTable[0];
+    /* Get the configuration data using the device ID */
+    cfg_ptr = &XIntc_ConfigTable[0];
 
-	/* Get the interrupts that are waiting to be serviced */
-	intr_status = XIntc_GetIntrStatus(XPAR_INTC_0_BASEADDR);
+    /* Get the interrupts that are waiting to be serviced */
+    intr_status = XIntc_GetIntrStatus(XPAR_INTC_0_BASEADDR);
 
-	/* Service each interrupt that is active and enabled by checking each
-	 * bit in the register from LSB to MSB which corresponds to an interrupt
-	 * intput signal
-	 */
-	for (intr_number = 0; intr_number < XPAR_INTC_MAX_NUM_INTR_INPUTS; intr_number++)
-	{
-		if (intr_status & 1)
-		{
-			XIntc_VectorTableEntry *table_ptr;
+    /* Service each interrupt that is active and enabled by checking each
+     * bit in the register from LSB to MSB which corresponds to an interrupt
+     * intput signal
+     */
+    for (intr_number = 0; intr_number < XPAR_INTC_MAX_NUM_INTR_INPUTS; intr_number++)
+    {
+        if (intr_status & 1)
+        {
+            XIntc_VectorTableEntry *table_ptr;
 
-			/* If the interrupt has been setup to acknowledge it
-			 * before servicing the interrupt, then ack it
-			 */
-			if (cfg_ptr->AckBeforeService & intr_mask)
-			{
-				XIntc_AckIntr(cfg_ptr->BaseAddress, intr_mask);
-			}
+            /* If the interrupt has been setup to acknowledge it
+             * before servicing the interrupt, then ack it
+             */
+            if (cfg_ptr->AckBeforeService & intr_mask)
+            {
+                XIntc_AckIntr(cfg_ptr->BaseAddress, intr_mask);
+            }
 
-			/* The interrupt is active and enabled, call the
-			 * interrupt handler that was setup with the specified
-			 * parameter
-			 */
-			table_ptr = &(cfg_ptr->HandlerTable[intr_number]);
-			table_ptr->Handler(table_ptr->CallBackRef);
+            /* The interrupt is active and enabled, call the
+             * interrupt handler that was setup with the specified
+             * parameter
+             */
+            table_ptr = &(cfg_ptr->HandlerTable[intr_number]);
+            table_ptr->Handler(table_ptr->CallBackRef);
 
-			/* If the interrupt has been setup to acknowledge it
-			 * after it has been serviced then ack it
-			 */
-			if ((cfg_ptr->AckBeforeService & intr_mask) == 0)
-			{
-				XIntc_AckIntr(cfg_ptr->BaseAddress, intr_mask);
-			}
+            /* If the interrupt has been setup to acknowledge it
+             * after it has been serviced then ack it
+             */
+            if ((cfg_ptr->AckBeforeService & intr_mask) == 0)
+            {
+                XIntc_AckIntr(cfg_ptr->BaseAddress, intr_mask);
+            }
 
-			/*
-			 * Read the ISR again to handle architectures with posted write
-			 * bus access issues.
-			 */
-			reg = XIntc_GetIntrStatus(cfg_ptr->BaseAddress);
+            /*
+             * Read the ISR again to handle architectures with posted write
+             * bus access issues.
+             */
+            reg = XIntc_GetIntrStatus(cfg_ptr->BaseAddress);
 
-			/*
-			 * If only the highest priority interrupt is to be
-			 * serviced, exit loop and return after servicing
-			 * the interrupt
-			 */
-			if (cfg_ptr->Options == XIN_SVC_SGL_ISR_OPTION)
-			{
-				return;
-			}
-		}
+            /*
+             * If only the highest priority interrupt is to be
+             * serviced, exit loop and return after servicing
+             * the interrupt
+             */
+            if (cfg_ptr->Options == XIN_SVC_SGL_ISR_OPTION)
+            {
+                return;
+            }
+        }
 
-		/* Move to the next interrupt to check */
-		intr_mask <<= 1;
-		intr_status >>= 1;
+        /* Move to the next interrupt to check */
+        intr_mask <<= 1;
+        intr_status >>= 1;
 
-		/* If there are no other bits set indicating that all interrupts
-		 * have been serviced, then exit the loop
-		 */
-		if (intr_status == 0)
-		{
-			break;
-		}
-	}
+        /* If there are no other bits set indicating that all interrupts
+         * have been serviced, then exit the loop
+         */
+        if (intr_status == 0)
+        {
+            break;
+        }
+    }
 }
 
 
diff --git a/src/Kconfig b/src/Kconfig
index 803c827e51..6afb719395 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -116,6 +116,18 @@ config RT_TIMER_THREAD_STACK_SIZE
 
 endif
 
+menu "kservice optimization"
+
+config RT_KSERVICE_USING_STDLIB
+    bool "Enable kservice to use standard C library"
+    default n
+
+config RT_KSERVICE_USING_TINY_SIZE
+    bool "Enable kservice to use tiny size"
+    default n
+
+endmenu
+
 menuconfig RT_DEBUG
     bool "Enable debugging features"
     default y
@@ -284,21 +296,19 @@ menu "Memory Management"
 
     endchoice
 
-    if RT_USING_SMALL_MEM
-        config RT_USING_MEMTRACE
-            bool "Enable memory trace"
-            default n
-            help
-                When enable RT_USING_MEMTRACE with shell, developer can call cmd:
-                1. memtrace
-                   to dump memory block information.
-                2. memcheck
-                   to check memory block to avoid memory overwritten.
+    config RT_USING_MEMTRACE
+        bool "Enable memory trace"
+        default n
+        help
+            When enable RT_USING_MEMTRACE with shell, developer can call cmd:
+            1. memtrace
+                to dump memory block information.
+            2. memcheck
+                to check memory block to avoid memory overwritten.
 
-                And developer also can call memcheck() in each of scheduling
-                to check memory block to find which thread has wrongly modified
-                memory.
-    endif
+            And developer also can call memcheck() in each of scheduling
+            to check memory block to find which thread has wrongly modified
+            memory.
 
     config RT_USING_HEAP
         bool
diff --git a/src/clock.c b/src/clock.c
index 66923e5c00..0880d8d241 100644
--- a/src/clock.c
+++ b/src/clock.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -111,7 +111,7 @@ rt_tick_t rt_tick_from_millisecond(rt_int32_t ms)
         tick = RT_TICK_PER_SECOND * (ms / 1000);
         tick += (RT_TICK_PER_SECOND * (ms % 1000) + 999) / 1000;
     }
-    
+
     /* return the calculated tick */
     return tick;
 }
diff --git a/src/components.c b/src/components.c
index 8ea5654d0c..9709d0aae2 100644
--- a/src/components.c
+++ b/src/components.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/src/cpu.c b/src/cpu.c
index 96e585713b..48ddb12c46 100644
--- a/src/cpu.c
+++ b/src/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/src/device.c b/src/device.c
index a4f004fb69..50b83c7692 100644
--- a/src/device.c
+++ b/src/device.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -12,6 +12,7 @@
  * 2012-12-25     Bernard      return RT_EOK if the device interface not exist.
  * 2013-07-09     Grissiom     add ref_count support
  * 2016-04-02     Bernard      fix the open_flag initialization issue.
+ * 2021-03-19     Meco Man     remove rt_device_init_all()
  */
 
 #include 
@@ -89,19 +90,6 @@ rt_err_t rt_device_unregister(rt_device_t dev)
 }
 RTM_EXPORT(rt_device_unregister);
 
-/**
- * This function initializes all registered device driver
- *
- * @return the error code, RT_EOK on successfully.
- *
- * @deprecated since 1.2.x, this function is not needed because the initialization
- *             of a device is performed when application opens it.
- */
-rt_err_t rt_device_init_all(void)
-{
-    return RT_EOK;
-}
-
 /**
  * This function finds a device driver by specified name.
  *
diff --git a/src/idle.c b/src/idle.c
index aa14552a49..24dfffbc6d 100644
--- a/src/idle.c
+++ b/src/idle.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -211,7 +211,7 @@ static void rt_thread_idle_entry(void *parameter)
 #endif
 
         rt_thread_idle_excute();
-#ifdef RT_USING_PM        
+#ifdef RT_USING_PM
         rt_system_power_manager();
 #endif
     }
diff --git a/src/ipc.c b/src/ipc.c
index d037708979..111d724c23 100755
--- a/src/ipc.c
+++ b/src/ipc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -34,7 +34,7 @@
  * 2013-09-14     Grissiom     add an option check in rt_event_recv
  * 2018-10-02     Bernard      add 64bit support for mailbox
  * 2019-09-16     tyx          add send wait support for message queue
- * 2020-07-29     Meco Man     fix thread->event_set/event_info when received an 
+ * 2020-07-29     Meco Man     fix thread->event_set/event_info when received an
  *                             event without pending
  * 2020-10-11     Meco Man     add value overflow-check code
  * 2021-01-03     Meco Man     add rt_mb_urgent()
@@ -124,7 +124,7 @@ rt_inline rt_err_t rt_ipc_list_suspend(rt_list_t        *list,
         break;
 
     default:
-        break;  
+        break;
     }
 
     return RT_EOK;
@@ -959,7 +959,7 @@ rt_err_t rt_mutex_release(rt_mutex_t mutex)
                 rt_hw_interrupt_enable(temp); /* enable interrupt */
                 return -RT_EFULL; /* value overflowed */
             }
-            
+
             /* clear owner */
             mutex->owner             = RT_NULL;
             mutex->original_priority = 0xff;
@@ -1280,11 +1280,11 @@ rt_err_t rt_event_recv(rt_event_t   event,
         /* set received event */
         if (recved)
             *recved = (event->set & set);
-            
-        /* fill thread event info */            
+
+        /* fill thread event info */
         thread->event_set = (event->set & set);
         thread->event_info = option;
-        
+
         /* received event */
         if (option & RT_EVENT_FLAG_CLEAR)
             event->set &= ~set;
@@ -1649,7 +1649,7 @@ rt_err_t rt_mb_send_wait(rt_mailbox_t mb,
     ++ mb->in_offset;
     if (mb->in_offset >= mb->size)
         mb->in_offset = 0;
-    
+
     if(mb->entry < RT_MB_ENTRY_MAX)
     {
         /* increase message entry */
@@ -1660,7 +1660,7 @@ rt_err_t rt_mb_send_wait(rt_mailbox_t mb,
         rt_hw_interrupt_enable(temp); /* enable interrupt */
         return -RT_EFULL; /* value overflowed */
     }
-    
+
     /* resume suspended thread */
     if (!rt_list_isempty(&mb->parent.suspend_thread))
     {
@@ -2203,7 +2203,7 @@ rt_err_t rt_mq_send_wait(rt_mq_t     mq,
     }
 
     /* message queue is full */
-    while ((msg = mq->msg_queue_free) == RT_NULL)
+    while ((msg = (struct rt_mq_message *)mq->msg_queue_free) == RT_NULL)
     {
         /* reset error number in thread */
         thread->error = RT_EOK;
@@ -2409,7 +2409,7 @@ rt_err_t rt_mq_urgent(rt_mq_t mq, const void *buffer, rt_size_t size)
         rt_hw_interrupt_enable(temp); /* enable interrupt */
         return -RT_EFULL; /* value overflowed */
     }
-    
+
     /* resume suspended thread */
     if (!rt_list_isempty(&mq->parent.suspend_thread))
     {
diff --git a/src/irq.c b/src/irq.c
index 311d297bfe..177c1a9ff5 100644
--- a/src/irq.c
+++ b/src/irq.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -21,7 +21,7 @@ static void (*rt_interrupt_leave_hook)(void);
 
 /**
  * @ingroup Hook
- * This function set a hook function when the system enter a interrupt 
+ * This function set a hook function when the system enter a interrupt
  *
  * @note the hook function must be simple and never be blocked or suspend.
  */
@@ -31,7 +31,7 @@ void rt_interrupt_enter_sethook(void (*hook)(void))
 }
 /**
  * @ingroup Hook
- * This function set a hook function when the system exit a interrupt. 
+ * This function set a hook function when the system exit a interrupt.
  *
  * @note the hook function must be simple and never be blocked or suspend.
  */
diff --git a/src/kservice.c b/src/kservice.c
index 423fe3ddb3..e9972dba97 100644
--- a/src/kservice.c
+++ b/src/kservice.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,6 +17,7 @@
  * 2013-06-24     Bernard      remove rt_kprintf if RT_USING_CONSOLE is not defined.
  * 2013-09-24     aozima       make sure the device is in STREAM mode when used by rt_kprintf.
  * 2015-07-06     Bernard      Add rt_assert_handler routine.
+ * 2021-02-28     Meco Man     add RT_KSERVICE_USING_STDLIB
  */
 
 #include 
@@ -125,7 +126,7 @@ RTM_EXPORT(_rt_errno);
  */
 RT_WEAK void *rt_memset(void *s, int c, rt_ubase_t count)
 {
-#ifdef RT_USING_TINY_SIZE
+#ifdef RT_KSERVICE_USING_TINY_SIZE
     char *xs = (char *)s;
 
     while (count--)
@@ -146,10 +147,10 @@ RT_WEAK void *rt_memset(void *s, int c, rt_ubase_t count)
 
     if (!TOO_SMALL(count) && !UNALIGNED(s))
     {
-        /* If we get this far, we know that n is large and m is word-aligned. */
+        /* If we get this far, we know that count is large and s is word-aligned. */
         aligned_addr = (unsigned long *)s;
 
-        /* Store D into each char sized location in BUFFER so that
+        /* Store d into each char sized location in buffer so that
          * we can set large blocks quickly.
          */
         if (LBLOCKSIZE == 4)
@@ -209,7 +210,7 @@ RTM_EXPORT(rt_memset);
  */
 RT_WEAK void *rt_memcpy(void *dst, const void *src, rt_ubase_t count)
 {
-#ifdef RT_USING_TINY_SIZE
+#ifdef RT_KSERVICE_USING_TINY_SIZE
     char *tmp = (char *)dst, *s = (char *)src;
     rt_ubase_t len;
 
@@ -280,6 +281,8 @@ RT_WEAK void *rt_memcpy(void *dst, const void *src, rt_ubase_t count)
 }
 RTM_EXPORT(rt_memcpy);
 
+#ifndef RT_KSERVICE_USING_STDLIB
+
 /**
  * This function will move memory content from source address to destination
  * address.
@@ -456,7 +459,7 @@ RTM_EXPORT(rt_strncmp);
 rt_int32_t rt_strcmp(const char *cs, const char *ct)
 {
     while (*cs && *cs == *ct)
-    {        
+    {
         cs++;
         ct++;
     }
@@ -506,6 +509,8 @@ rt_size_t rt_strlen(const char *s)
 }
 RTM_EXPORT(rt_strlen);
 
+#endif /*RT_KSERVICE_USING_STDLIB*/
+
 #ifdef RT_USING_HEAP
 /**
  * This function will duplicate a string.
@@ -1127,10 +1132,10 @@ rt_device_t rt_console_set_device(const char *name)
 
     /* find new console device */
     new_device = rt_device_find(name);
-    
+
     /* check whether it's a same device */
     if (new_device == old_device) return RT_NULL;
-    
+
     if (new_device != RT_NULL)
     {
         if (_console_device != RT_NULL)
@@ -1386,26 +1391,4 @@ void rt_assert_handler(const char *ex_string, const char *func, rt_size_t line)
 RTM_EXPORT(rt_assert_handler);
 #endif /* RT_DEBUG */
 
-#if !defined (RT_USING_NEWLIB) && defined (RT_USING_MINILIBC) && defined (__GNUC__)
-#include 
-void *memcpy(void *dest, const void *src, size_t n) __attribute__((weak, alias("rt_memcpy")));
-void *memset(void *s, int c, size_t n) __attribute__((weak, alias("rt_memset")));
-void *memmove(void *dest, const void *src, size_t n) __attribute__((weak, alias("rt_memmove")));
-int   memcmp(const void *s1, const void *s2, size_t n) __attribute__((weak, alias("rt_memcmp")));
-
-size_t strlen(const char *s) __attribute__((weak, alias("rt_strlen")));
-char *strstr(const char *s1, const char *s2) __attribute__((weak, alias("rt_strstr")));
-int strcasecmp(const char *a, const char *b) __attribute__((weak, alias("rt_strcasecmp")));
-char *strncpy(char *dest, const char *src, size_t n) __attribute__((weak, alias("rt_strncpy")));
-int strncmp(const char *cs, const char *ct, size_t count) __attribute__((weak, alias("rt_strncmp")));
-#ifdef RT_USING_HEAP
-char *strdup(const char *s) __attribute__((weak, alias("rt_strdup")));
-#endif
-
-int sprintf(char *buf, const char *format, ...) __attribute__((weak, alias("rt_sprintf")));
-int snprintf(char *buf, rt_size_t size, const char *fmt, ...) __attribute__((weak, alias("rt_snprintf")));
-int vsprintf(char *buf, const char *format, va_list arg_ptr) __attribute__((weak, alias("rt_vsprintf")));
-
-#endif
-
 /**@}*/
diff --git a/src/mem.c b/src/mem.c
index c03c8b3452..ac0d27f2c3 100644
--- a/src/mem.c
+++ b/src/mem.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -489,7 +489,7 @@ void *rt_realloc(void *rmem, rt_size_t newsize)
         {
             ((struct heap_mem *)&heap_ptr[mem2->next])->prev = ptr2;
         }
-        
+
         if (mem2 < lfree)
         {
             /* the splited struct is now the lowest */
diff --git a/src/memheap.c b/src/memheap.c
index afa06fb9bf..63327575cc 100644
--- a/src/memheap.c
+++ b/src/memheap.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -35,6 +35,45 @@
 
 #define RT_MEMHEAP_SIZE         RT_ALIGN(sizeof(struct rt_memheap_item), RT_ALIGN_SIZE)
 #define MEMITEM_SIZE(item)      ((rt_ubase_t)item->next - (rt_ubase_t)item - RT_MEMHEAP_SIZE)
+#define MEMITEM(ptr)            (struct rt_memheap_item*)((rt_uint8_t*)ptr - RT_MEMHEAP_SIZE)
+
+#ifdef RT_USING_MEMTRACE
+rt_inline void rt_memheap_setname(struct rt_memheap_item *item, const char *name)
+{
+    int index;
+    rt_uint8_t* ptr;
+
+    ptr = (rt_uint8_t*)&(item->next_free);
+    for (index = 0; index < sizeof(void*); index ++)
+    {
+        if (name[index] == '\0') break;
+        ptr[index] = name[index];
+    }
+    if (name[index] == '\0') ptr[index] = '\0';
+    else 
+    {
+        ptr = (rt_uint8_t*)&(item->prev_free);
+        for (index = 0; index < sizeof(void*) && (index + sizeof(void*))< RT_NAME_MAX; index ++)
+        {
+            if (name[sizeof(void*) + index] == '\0') break;
+            ptr[index] = name[sizeof(void*) + index];
+        }
+
+        if (name[sizeof(void*) + index] == '\0') ptr[index] = '\0';
+    }
+}
+
+void rt_mem_set_tag(void* ptr, const char* name)
+{
+    struct rt_memheap_item* item;
+
+    if (ptr && name)
+    {
+        item = MEMITEM(ptr);
+        rt_memheap_setname(item, name);
+    }
+}
+#endif
 
 /*
  * The initialized memory pool will be:
@@ -66,7 +105,7 @@ rt_err_t rt_memheap_init(struct rt_memheap *memheap,
 
     /* initialize the free list header */
     item            = &(memheap->free_header);
-    item->magic     = RT_MEMHEAP_MAGIC;
+    item->magic     = (RT_MEMHEAP_MAGIC | RT_MEMHEAP_FREED);
     item->pool_ptr  = memheap;
     item->next      = RT_NULL;
     item->prev      = RT_NULL;
@@ -78,13 +117,17 @@ rt_err_t rt_memheap_init(struct rt_memheap *memheap,
 
     /* initialize the first big memory block */
     item            = (struct rt_memheap_item *)start_addr;
-    item->magic     = RT_MEMHEAP_MAGIC;
+    item->magic     = (RT_MEMHEAP_MAGIC | RT_MEMHEAP_FREED);
     item->pool_ptr  = memheap;
     item->next      = RT_NULL;
     item->prev      = RT_NULL;
     item->next_free = item;
     item->prev_free = item;
 
+#ifdef RT_USING_MEMTRACE
+    rt_memset(item->owner_thread_name, ' ', sizeof(item->owner_thread_name));
+#endif
+
     item->next = (struct rt_memheap_item *)
                  ((rt_uint8_t *)item + memheap->available_size + RT_MEMHEAP_SIZE);
     item->prev = item->next;
@@ -103,7 +146,7 @@ rt_err_t rt_memheap_init(struct rt_memheap *memheap,
      */
     item = item->next;
     /* it's a used memory block */
-    item->magic     = RT_MEMHEAP_MAGIC | RT_MEMHEAP_USED;
+    item->magic     = (RT_MEMHEAP_MAGIC | RT_MEMHEAP_USED);
     item->pool_ptr  = memheap;
     item->next      = (struct rt_memheap_item *)start_addr;
     item->prev      = (struct rt_memheap_item *)start_addr;
@@ -126,7 +169,7 @@ rt_err_t rt_memheap_detach(struct rt_memheap *heap)
     RT_ASSERT(heap);
     RT_ASSERT(rt_object_get_type(&heap->parent) == RT_Object_Class_MemHeap);
     RT_ASSERT(rt_object_is_systemobject(&heap->parent));
-    
+
     rt_sem_detach(&heap->lock);
     rt_object_detach(&(heap->parent));
 
@@ -201,11 +244,15 @@ void *rt_memheap_alloc(struct rt_memheap *heap, rt_size_t size)
                               new_ptr));
 
                 /* mark the new block as a memory block and freed. */
-                new_ptr->magic = RT_MEMHEAP_MAGIC;
+                new_ptr->magic = (RT_MEMHEAP_MAGIC | RT_MEMHEAP_FREED);
 
                 /* put the pool pointer into the new block. */
                 new_ptr->pool_ptr = heap;
 
+#ifdef RT_USING_MEMTRACE
+                rt_memset(new_ptr->owner_thread_name, ' ', sizeof(new_ptr->owner_thread_name));
+#endif
+
                 /* break down the block list */
                 new_ptr->prev          = header_ptr;
                 new_ptr->next          = header_ptr->next;
@@ -255,7 +302,14 @@ void *rt_memheap_alloc(struct rt_memheap *heap, rt_size_t size)
             }
 
             /* Mark the allocated block as not available. */
-            header_ptr->magic |= RT_MEMHEAP_USED;
+            header_ptr->magic = (RT_MEMHEAP_MAGIC | RT_MEMHEAP_USED);
+
+#ifdef RT_USING_MEMTRACE
+            if (rt_thread_self())
+                rt_memcpy(header_ptr->owner_thread_name, rt_thread_self()->name, sizeof(header_ptr->owner_thread_name));
+            else
+                rt_memcpy(header_ptr->owner_thread_name, "NONE", sizeof(header_ptr->owner_thread_name));
+#endif
 
             /* release lock */
             rt_sem_release(&(heap->lock));
@@ -376,11 +430,15 @@ void *rt_memheap_realloc(struct rt_memheap *heap, void *ptr, rt_size_t newsize)
                               next_ptr->prev));
 
                 /* mark the new block as a memory block and freed. */
-                next_ptr->magic = RT_MEMHEAP_MAGIC;
+                next_ptr->magic = (RT_MEMHEAP_MAGIC | RT_MEMHEAP_FREED);
 
                 /* put the pool pointer into the new block. */
                 next_ptr->pool_ptr = heap;
 
+#ifdef RT_USING_MEMTRACE
+                rt_memset(next_ptr->owner_thread_name, ' ', sizeof(next_ptr->owner_thread_name));
+#endif
+
                 next_ptr->prev          = header_ptr;
                 next_ptr->next          = header_ptr->next;
                 header_ptr->next->prev = next_ptr;
@@ -441,10 +499,14 @@ void *rt_memheap_realloc(struct rt_memheap *heap, void *ptr, rt_size_t newsize)
                   new_ptr));
 
     /* mark the new block as a memory block and freed. */
-    new_ptr->magic = RT_MEMHEAP_MAGIC;
+    new_ptr->magic = (RT_MEMHEAP_MAGIC | RT_MEMHEAP_FREED);
     /* put the pool pointer into the new block. */
     new_ptr->pool_ptr = heap;
 
+#ifdef RT_USING_MEMTRACE
+    rt_memset(new_ptr->owner_thread_name, ' ', sizeof(new_ptr->owner_thread_name));
+#endif
+
     /* break down the block list */
     new_ptr->prev          = header_ptr;
     new_ptr->next          = header_ptr->next;
@@ -512,8 +574,12 @@ void rt_memheap_free(void *ptr)
                                     ptr, header_ptr));
 
     /* check magic */
-    RT_ASSERT((header_ptr->magic & RT_MEMHEAP_MASK) == RT_MEMHEAP_MAGIC);
-    RT_ASSERT(header_ptr->magic & RT_MEMHEAP_USED);
+    if (header_ptr->magic != (RT_MEMHEAP_MAGIC | RT_MEMHEAP_USED))
+    {
+        RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, ("bad magic:0x%08x @ memheap\n",
+                                        header_ptr->magic));
+    }
+    RT_ASSERT(header_ptr->magic == (RT_MEMHEAP_MAGIC | RT_MEMHEAP_USED));
     /* check whether this block of memory has been over-written. */
     RT_ASSERT((header_ptr->next->magic & RT_MEMHEAP_MASK) == RT_MEMHEAP_MAGIC);
 
@@ -533,9 +599,9 @@ void rt_memheap_free(void *ptr)
     }
 
     /* Mark the memory as available. */
-    header_ptr->magic &= ~RT_MEMHEAP_USED;
+    header_ptr->magic = (RT_MEMHEAP_MAGIC | RT_MEMHEAP_FREED);
     /* Adjust the available number of bytes. */
-    heap->available_size = heap->available_size + MEMITEM_SIZE(header_ptr);
+    heap->available_size += MEMITEM_SIZE(header_ptr);
 
     /* Determine if the block can be merged with the previous neighbor. */
     if (!RT_MEMHEAP_IS_USED(header_ptr->prev))
@@ -544,7 +610,7 @@ void rt_memheap_free(void *ptr)
                                         header_ptr->prev));
 
         /* adjust the available number of bytes. */
-        heap->available_size = heap->available_size + RT_MEMHEAP_SIZE;
+        heap->available_size += RT_MEMHEAP_SIZE;
 
         /* yes, merge block with previous neighbor. */
         (header_ptr->prev)->next = header_ptr->next;
@@ -560,7 +626,7 @@ void rt_memheap_free(void *ptr)
     if (!RT_MEMHEAP_IS_USED(header_ptr->next))
     {
         /* adjust the available number of bytes. */
-        heap->available_size = heap->available_size + RT_MEMHEAP_SIZE;
+        heap->available_size += RT_MEMHEAP_SIZE;
 
         /* merge block with next neighbor. */
         new_ptr = header_ptr->next;
@@ -590,11 +656,100 @@ void rt_memheap_free(void *ptr)
                       header_ptr->next_free, header_ptr->prev_free));
     }
 
+#ifdef RT_USING_MEMTRACE
+    rt_memset(header_ptr->owner_thread_name, ' ', sizeof(header_ptr->owner_thread_name));
+#endif
+
     /* release lock */
     rt_sem_release(&(heap->lock));
 }
 RTM_EXPORT(rt_memheap_free);
 
+#ifdef RT_USING_FINSH
+static void _memheap_dump_tag(struct rt_memheap_item* item)
+{
+    rt_uint8_t name[2 * sizeof(void*)];
+    rt_uint8_t* ptr;
+
+    ptr = (rt_uint8_t*)&(item->next_free);
+    rt_memcpy(name, ptr, sizeof(void*));
+    ptr = (rt_uint8_t*)&(item->prev_free);
+    rt_memcpy(&name[sizeof(void*)], ptr, sizeof(void*));
+
+    rt_kprintf("%.*s", 2 * sizeof(void*), name);
+}
+
+int rt_memheap_dump(struct rt_memheap *heap)
+{
+    struct rt_memheap_item *item, *end;
+
+    if (heap == RT_NULL) return 0;
+    RT_ASSERT(rt_object_get_type(&heap->parent) == RT_Object_Class_MemHeap);
+
+    rt_kprintf("\n[%.*s] [0x%08x - 0x%08x]->\n", RT_NAME_MAX, heap->parent.name, 
+        (rt_ubase_t)heap->start_addr, (rt_ubase_t)heap->start_addr + heap->pool_size);
+    rt_kprintf("------------------------------\n");
+
+    /* lock memheap */
+    rt_sem_take(&(heap->lock), RT_WAITING_FOREVER);
+    item = heap->block_list;
+
+    end = (struct rt_memheap_item *) ((rt_uint8_t *)heap->start_addr + heap->pool_size - RT_MEMHEAP_SIZE);
+
+    /* for each memory block */
+    while ((rt_ubase_t)item < ((rt_ubase_t)end))
+    {
+        if (RT_MEMHEAP_IS_USED(item) && ((item->magic & RT_MEMHEAP_MASK) != RT_MEMHEAP_MAGIC))
+            rt_kprintf("0x%08x", item + 1);
+
+        if (item->magic == (RT_MEMHEAP_MAGIC | RT_MEMHEAP_USED))
+        {
+            rt_kprintf("0x%08x: %-8d ",     item + 1, MEMITEM_SIZE(item));
+            _memheap_dump_tag(item);
+            rt_kprintf("\n");
+        }
+        else
+        {
+            rt_kprintf("0x%08x: %-8d \n", item + 1, MEMITEM_SIZE(item));
+        }
+
+        item = item->next;
+    }
+    rt_sem_release(&(heap->lock));
+
+    return 0;
+}
+
+int memheaptrace(void)
+{
+    int count = rt_object_get_length(RT_Object_Class_MemHeap);
+    struct rt_memheap **heaps;
+
+    if (count > 0)
+    {
+        int index;
+        extern int list_memheap(void);
+
+        heaps = (struct rt_memheap**)rt_malloc(sizeof(struct rt_memheap*) * count);
+        if (heaps == RT_NULL) return 0;
+
+        list_memheap();
+
+        rt_kprintf("memheap header size: %d\n", RT_MEMHEAP_SIZE);
+        count = rt_object_get_pointers(RT_Object_Class_MemHeap, (rt_object_t*)heaps, count);
+        for (index = 0; index < count; index++)
+        {
+            rt_memheap_dump(heaps[index]);
+        }
+
+        rt_free(heaps);
+    }
+
+    return 0;
+}
+MSH_CMD_EXPORT(memheaptrace, dump memory trace information);
+#endif
+
 #ifdef RT_USING_MEMHEAP_AS_HEAP
 static struct rt_memheap _heap;
 
@@ -643,6 +798,24 @@ void *rt_malloc(rt_size_t size)
         }
     }
 
+
+#ifdef RT_USING_MEMTRACE
+    if (ptr == RT_NULL)
+    {
+        RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, ("malloc[%d] => NULL", size));
+    }
+    else
+    {
+        struct rt_memheap_item *item = MEMITEM(ptr);
+        if (rt_thread_self())
+            rt_memheap_setname(item, rt_thread_self()->name);
+        else
+            rt_memheap_setname(item, "");
+
+        RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, ("malloc => 0x%08x : %d", ptr, size));
+    }
+#endif
+
     return ptr;
 }
 RTM_EXPORT(rt_malloc);
@@ -691,6 +864,24 @@ void *rt_realloc(void *rmem, rt_size_t newsize)
         }
     }
 
+#ifdef RT_USING_MEMTRACE
+    if (new_ptr == RT_NULL)
+    {
+        RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, ("realloc[%d] => NULL", newsize));
+    }
+    else
+    {
+        struct rt_memheap_item *item = MEMITEM(new_ptr);
+        if (rt_thread_self())
+            rt_memheap_setname(item, rt_thread_self()->name);
+        else
+            rt_memheap_setname(item, "");
+
+        RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, ("realloc => 0x%08x : %d",
+                                        new_ptr, newsize));
+    }
+#endif
+
     return new_ptr;
 }
 RTM_EXPORT(rt_realloc);
@@ -708,6 +899,19 @@ void *rt_calloc(rt_size_t count, rt_size_t size)
         rt_memset(ptr, 0, total_size);
     }
 
+#ifdef RT_USING_MEMTRACE
+    if (ptr == RT_NULL)
+    {
+        RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, ("calloc[%d x %d] => NULL",
+                                        count, size));
+    }
+    else
+    {
+        RT_DEBUG_LOG(RT_DEBUG_MEMHEAP, ("calloc => 0x%08x : %d",
+                                        ptr, count * size));
+    }
+#endif
+
     return ptr;
 }
 RTM_EXPORT(rt_calloc);
@@ -728,4 +932,78 @@ void rt_memory_info(rt_uint32_t *total,
 
 #endif
 
-#endif
+#ifdef RT_USING_MEMTRACE
+
+void dump_used_memheap(struct rt_memheap *mh)
+{
+    struct rt_memheap_item *header_ptr;
+    rt_uint32_t block_size;
+
+
+    rt_kprintf("\nmemory heap address:\n");
+    rt_kprintf("heap_ptr: 0x%08x\n", mh->start_addr);
+    rt_kprintf("free    : 0x%08x\n", mh->available_size);
+    rt_kprintf("max_used: 0x%08x\n", mh->max_used_size);
+    rt_kprintf("size    : 0x%08x\n", mh->pool_size);
+
+    rt_kprintf("\n--memory used information --\n");
+
+    header_ptr = mh->block_list;
+    while (header_ptr->next != mh->block_list)
+    {
+        if ((header_ptr->magic & RT_MEMHEAP_MASK) != RT_MEMHEAP_MAGIC)
+        {
+            rt_kprintf("[0x%08x - incorrect magic: 0x%08x\n", header_ptr, header_ptr->magic);
+            break;
+        }
+
+        /* get current memory block size */
+        block_size = MEMITEM_SIZE(header_ptr);
+        if (block_size < 0)
+            break;
+
+        if (RT_MEMHEAP_IS_USED(header_ptr))
+        {
+            /* dump information */
+            rt_kprintf("[0x%08x - %d - %c%c%c%c] used\n", header_ptr, block_size,
+                header_ptr->owner_thread_name[0], header_ptr->owner_thread_name[1],
+                header_ptr->owner_thread_name[2], header_ptr->owner_thread_name[3]);
+        }
+        else
+        {
+            /* dump information */
+            rt_kprintf("[0x%08x - %d - %c%c%c%c] free\n", header_ptr, block_size,
+                header_ptr->owner_thread_name[0], header_ptr->owner_thread_name[1],
+                header_ptr->owner_thread_name[2], header_ptr->owner_thread_name[3]);
+        }
+
+        /* move to next used memory block */
+        header_ptr = header_ptr->next;
+    }
+}
+
+void memtrace_heap()
+{
+    struct rt_object_information *info;
+    struct rt_list_node *list;
+    struct rt_memheap *mh;
+    struct rt_list_node *node;
+
+    info = rt_object_get_information(RT_Object_Class_MemHeap);
+    list = &info->object_list;
+
+    for (node = list->next; node != list; node = node->next)
+    {
+        mh = (struct rt_memheap *)rt_list_entry(node, struct rt_object, list);
+        dump_used_memheap(mh);
+    }
+}
+
+#ifdef RT_USING_FINSH
+#include 
+MSH_CMD_EXPORT(memtrace_heap, dump memory trace for heap);
+#endif /* end of RT_USING_FINSH */
+
+#endif /* end of RT_USING_MEMTRACE */
+
+#endif /* end of RT_USING_MEMHEAP */
diff --git a/src/mempool.c b/src/mempool.c
index db614032aa..1de48940d7 100644
--- a/src/mempool.c
+++ b/src/mempool.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/src/object.c b/src/object.c
index 56263618b3..013e2d1e33 100644
--- a/src/object.c
+++ b/src/object.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -200,7 +200,7 @@ void rt_object_put_sethook(void (*hook)(struct rt_object *object))
 /**
  * This function will return the specified type of object information.
  *
- * @param type the type of object, which can be 
+ * @param type the type of object, which can be
  *             RT_Object_Class_Thread/Semaphore/Mutex... etc
  *
  * @return the object type information or RT_NULL
@@ -220,7 +220,7 @@ RTM_EXPORT(rt_object_get_information);
 /**
  * This function will return the length of object list in object container.
  *
- * @param type the type of object, which can be 
+ * @param type the type of object, which can be
  *             RT_Object_Class_Thread/Semaphore/Mutex... etc
  * @return the length of object list
  */
@@ -247,10 +247,10 @@ int rt_object_get_length(enum rt_object_class_type type)
 RTM_EXPORT(rt_object_get_length);
 
 /**
- * This function will copy the object pointer of the specified type, 
+ * This function will copy the object pointer of the specified type,
  * with the maximum size specified by maxlen.
  *
- * @param type the type of object, which can be 
+ * @param type the type of object, which can be
  *             RT_Object_Class_Thread/Semaphore/Mutex... etc
  * @param pointers the pointers will be saved to
  * @param maxlen the maximum number of pointers can be saved
diff --git a/src/scheduler.c b/src/scheduler.c
index 06f305ea0b..c03c20d030 100644
--- a/src/scheduler.c
+++ b/src/scheduler.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -270,10 +270,10 @@ void rt_system_scheduler_start(void)
 #ifdef RT_USING_SMP
 /**
  * This function will handle IPI interrupt and do a scheduling in system;
- * 
+ *
  * @param vector, the number of IPI interrupt for system scheduling
  * @param param, use RT_NULL
- * 
+ *
  * NOTE: this function should be invoke or register as ISR in BSP.
  */
 void rt_scheduler_ipi_handler(int vector, void *param)
@@ -283,7 +283,7 @@ void rt_scheduler_ipi_handler(int vector, void *param)
 
 /**
  * This function will perform one scheduling. It will select one thread
- * with the highest priority level in global ready queue or local ready queue, 
+ * with the highest priority level in global ready queue or local ready queue,
  * then switch to it.
  */
 void rt_schedule(void)
diff --git a/src/signal.c b/src/signal.c
index bb9339ab6c..c2c3e975cb 100644
--- a/src/signal.c
+++ b/src/signal.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/src/slab.c b/src/slab.c
index 0872ecf092..12ca1a938c 100644
--- a/src/slab.c
+++ b/src/slab.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  */
diff --git a/src/thread.c b/src/thread.c
index 0db9dd8e4d..34e96077d1 100644
--- a/src/thread.c
+++ b/src/thread.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -26,6 +26,7 @@
  *                             bug when thread has not startup.
  * 2018-11-22     Jesven       yield is same to rt_schedule
  *                             add support for tasks bound to cpu
+ * 2021-02-24     Meco Man     rearrange rt_thread_control() - schedule the thread when close it
  */
 
 #include 
@@ -357,8 +358,6 @@ RTM_EXPORT(rt_thread_startup);
  */
 rt_err_t rt_thread_detach(rt_thread_t thread)
 {
-    rt_base_t lock;
-
     /* thread check */
     RT_ASSERT(thread != RT_NULL);
     RT_ASSERT(rt_object_get_type((rt_object_t)thread) == RT_Object_Class_Thread);
@@ -381,19 +380,8 @@ rt_err_t rt_thread_detach(rt_thread_t thread)
     /* change stat */
     thread->stat = RT_THREAD_CLOSE;
 
-    if (rt_object_is_systemobject((rt_object_t)thread) == RT_TRUE)
-    {
-        rt_object_detach((rt_object_t)thread);
-    }
-    else
-    {
-        /* disable interrupt */
-        lock = rt_hw_interrupt_disable();
-        /* insert to defunct thread list */
-        rt_list_insert_after(&rt_thread_defunct, &(thread->tlist));
-        /* enable interrupt */
-        rt_hw_interrupt_enable(lock);
-    }
+    /* detach thread object */
+    rt_object_detach((rt_object_t)thread);
 
     return RT_EOK;
 }
@@ -585,6 +573,7 @@ rt_err_t rt_thread_delay_until(rt_tick_t *tick, rt_tick_t inc_tick)
 {
     register rt_base_t level;
     struct rt_thread *thread;
+    rt_tick_t cur_tick;
 
     RT_ASSERT(tick != RT_NULL);
 
@@ -596,15 +585,19 @@ rt_err_t rt_thread_delay_until(rt_tick_t *tick, rt_tick_t inc_tick)
     /* disable interrupt */
     level = rt_hw_interrupt_disable();
 
-    if (rt_tick_get() - *tick < inc_tick)
+    cur_tick = rt_tick_get();
+    if (cur_tick - *tick < inc_tick)
     {
-        *tick = *tick + inc_tick - rt_tick_get();
+        rt_tick_t left_tick;
+
+        *tick += inc_tick;
+        left_tick = *tick - cur_tick;
 
         /* suspend thread */
         rt_thread_suspend(thread);
 
         /* reset the timeout of thread timer and start it */
-        rt_timer_control(&(thread->thread_timer), RT_TIMER_CTRL_SET_TIME, tick);
+        rt_timer_control(&(thread->thread_timer), RT_TIMER_CTRL_SET_TIME, &left_tick);
         rt_timer_start(&(thread->thread_timer));
 
         /* enable interrupt */
@@ -620,12 +613,10 @@ rt_err_t rt_thread_delay_until(rt_tick_t *tick, rt_tick_t inc_tick)
     }
     else
     {
+        *tick = cur_tick;
         rt_hw_interrupt_enable(level);
     }
 
-    /* get the wakeup tick */
-    *tick = rt_tick_get();
-
     return RT_EOK;
 }
 RTM_EXPORT(rt_thread_delay_until);
@@ -670,83 +661,93 @@ rt_err_t rt_thread_control(rt_thread_t thread, int cmd, void *arg)
 
     switch (cmd)
     {
-    case RT_THREAD_CTRL_CHANGE_PRIORITY:
-        /* disable interrupt */
-        temp = rt_hw_interrupt_disable();
-
-        /* for ready thread, change queue */
-        if ((thread->stat & RT_THREAD_STAT_MASK) == RT_THREAD_READY)
+        case RT_THREAD_CTRL_CHANGE_PRIORITY:
         {
-            /* remove thread from schedule queue first */
-            rt_schedule_remove_thread(thread);
+            /* disable interrupt */
+            temp = rt_hw_interrupt_disable();
 
-            /* change thread priority */
-            thread->current_priority = *(rt_uint8_t *)arg;
+            /* for ready thread, change queue */
+            if ((thread->stat & RT_THREAD_STAT_MASK) == RT_THREAD_READY)
+            {
+                /* remove thread from schedule queue first */
+                rt_schedule_remove_thread(thread);
 
-            /* recalculate priority attribute */
-#if RT_THREAD_PRIORITY_MAX > 32
-            thread->number      = thread->current_priority >> 3;            /* 5bit */
-            thread->number_mask = 1 << thread->number;
-            thread->high_mask   = 1 << (thread->current_priority & 0x07);   /* 3bit */
-#else
-            thread->number_mask = 1 << thread->current_priority;
-#endif
+                /* change thread priority */
+                thread->current_priority = *(rt_uint8_t *)arg;
 
-            /* insert thread to schedule queue again */
-            rt_schedule_insert_thread(thread);
-        }
-        else
-        {
-            thread->current_priority = *(rt_uint8_t *)arg;
+                /* recalculate priority attribute */
+    #if RT_THREAD_PRIORITY_MAX > 32
+                thread->number      = thread->current_priority >> 3;            /* 5bit */
+                thread->number_mask = 1 << thread->number;
+                thread->high_mask   = 1 << (thread->current_priority & 0x07);   /* 3bit */
+    #else
+                thread->number_mask = 1 << thread->current_priority;
+    #endif
 
-            /* recalculate priority attribute */
-#if RT_THREAD_PRIORITY_MAX > 32
-            thread->number      = thread->current_priority >> 3;            /* 5bit */
-            thread->number_mask = 1 << thread->number;
-            thread->high_mask   = 1 << (thread->current_priority & 0x07);   /* 3bit */
-#else
-            thread->number_mask = 1 << thread->current_priority;
-#endif
+                /* insert thread to schedule queue again */
+                rt_schedule_insert_thread(thread);
+            }
+            else
+            {
+                thread->current_priority = *(rt_uint8_t *)arg;
+
+                /* recalculate priority attribute */
+    #if RT_THREAD_PRIORITY_MAX > 32
+                thread->number      = thread->current_priority >> 3;            /* 5bit */
+                thread->number_mask = 1 << thread->number;
+                thread->high_mask   = 1 << (thread->current_priority & 0x07);   /* 3bit */
+    #else
+                thread->number_mask = 1 << thread->current_priority;
+    #endif
+            }
+
+            /* enable interrupt */
+            rt_hw_interrupt_enable(temp);
+            break;
         }
 
-        /* enable interrupt */
-        rt_hw_interrupt_enable(temp);
-        break;
-
-    case RT_THREAD_CTRL_STARTUP:
-        return rt_thread_startup(thread);
-
-    case RT_THREAD_CTRL_CLOSE:
-
-        if (rt_object_is_systemobject((rt_object_t)thread) == RT_TRUE)
+        case RT_THREAD_CTRL_STARTUP:
         {
-            return rt_thread_detach(thread);
-        }
-#ifdef RT_USING_HEAP
-        else
-        {
-            return rt_thread_delete(thread);
-        }
-#endif
-
-#ifdef RT_USING_SMP
-    case RT_THREAD_CTRL_BIND_CPU:
-    {
-        rt_uint8_t cpu;
-
-        if ((thread->stat & RT_THREAD_STAT_MASK) != RT_THREAD_INIT)
-        {
-            /* we only support bind cpu before started phase. */
-            return RT_ERROR;
+            return rt_thread_startup(thread);
         }
 
-        cpu = (rt_uint8_t)(size_t)arg;
-        thread->bind_cpu = cpu > RT_CPUS_NR? RT_CPUS_NR : cpu;
-        break;
-    }
-#endif /*RT_USING_SMP*/
-    default:
-        break;
+        case RT_THREAD_CTRL_CLOSE:
+        {
+            rt_err_t rt_err;
+
+            if (rt_object_is_systemobject((rt_object_t)thread) == RT_TRUE)
+            {
+                rt_err = rt_thread_detach(thread);
+            }
+    #ifdef RT_USING_HEAP
+            else
+            {
+                rt_err = rt_thread_delete(thread);
+            }
+    #endif
+            rt_schedule();
+            return rt_err;
+        }
+
+    #ifdef RT_USING_SMP
+        case RT_THREAD_CTRL_BIND_CPU:
+        {
+            rt_uint8_t cpu;
+
+            if ((thread->stat & RT_THREAD_STAT_MASK) != RT_THREAD_INIT)
+            {
+                /* we only support bind cpu before started phase. */
+                return RT_ERROR;
+            }
+
+            cpu = (rt_uint8_t)(size_t)arg;
+            thread->bind_cpu = cpu > RT_CPUS_NR? RT_CPUS_NR : cpu;
+            break;
+        }
+    #endif /*RT_USING_SMP*/
+
+        default:
+            break;
     }
 
     return RT_EOK;
diff --git a/src/timer.c b/src/timer.c
index d882711151..836df51e06 100644
--- a/src/timer.c
+++ b/src/timer.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -201,7 +201,7 @@ void rt_timer_init(rt_timer_t  timer,
     RT_ASSERT(timer != RT_NULL);
 
     /* timer object initialization */
-    rt_object_init((rt_object_t)timer, RT_Object_Class_Timer, name);
+    rt_object_init(&(timer->parent), RT_Object_Class_Timer, name);
 
     _rt_timer_init(timer, timeout, parameter, time, flag);
 }
@@ -233,7 +233,7 @@ rt_err_t rt_timer_detach(rt_timer_t timer)
     /* enable interrupt */
     rt_hw_interrupt_enable(level);
 
-    rt_object_detach((rt_object_t)timer);
+    rt_object_detach(&(timer->parent));
 
     return RT_EOK;
 }
@@ -298,7 +298,7 @@ rt_err_t rt_timer_delete(rt_timer_t timer)
     /* enable interrupt */
     rt_hw_interrupt_enable(level);
 
-    rt_object_delete((rt_object_t)timer);
+    rt_object_delete(&(timer->parent));
 
     return RT_EOK;
 }
diff --git a/tools/as.sh b/tools/as.sh
old mode 100755
new mode 100644
diff --git a/tools/auto-ci.py b/tools/auto-ci.py
index 67834544d8..bbb384cec2 100644
--- a/tools/auto-ci.py
+++ b/tools/auto-ci.py
@@ -52,7 +52,7 @@ fail = False
 
 BSP_ROOT = '../bsp'
 
-for bsp,cpu in bsp_to_cpu.iteritems():
+for bsp,cpu in bsp_to_cpu.items():
     project_dir = os.path.join(BSP_ROOT, bsp)
     if os.getenv('RTT_CPU') == cpu and os.path.isfile(os.path.join(project_dir, 'SConstruct')):
         if os.system('scons --directory=' + project_dir) != 0:
@@ -63,10 +63,10 @@ for bsp,cpu in bsp_to_cpu.iteritems():
     else:
         results['ignore'].append(bsp)
 
-for result,bsp_list in results.iteritems():
-    print "## {0}: {1}\n".format(result, len(bsp_list))
+for result,bsp_list in results.items():
+    print("## {0}: {1}\n".format(result, len(bsp_list)))
     for bsp in bsp_list:
-        print "* " + bsp
+        print("* " + bsp)
 
 if fail:
     sys.exit(1)
diff --git a/tools/buildbot.py b/tools/buildbot.py
index ecc0031195..bcce3449ec 100644
--- a/tools/buildbot.py
+++ b/tools/buildbot.py
@@ -2,9 +2,9 @@ import os
 import sys
 
 def usage():
-    print '%s all     -- build all bsp' % os.path.basename(sys.argv[0])
-    print '%s clean   -- clean all bsp' % os.path.basename(sys.argv[0])
-    print '%s project -- update all prject files' % os.path.basename(sys.argv[0])
+    print('%s all     -- build all bsp' % os.path.basename(sys.argv[0]))
+    print('%s clean   -- clean all bsp' % os.path.basename(sys.argv[0]))
+    print('%s project -- update all prject files' % os.path.basename(sys.argv[0]))
 
 BSP_ROOT = os.path.join("..", "bsp")
 
@@ -25,25 +25,25 @@ elif sys.argv[1] == 'project':
         project_dir = os.path.join(BSP_ROOT, item)
 
         if os.path.isfile(os.path.join(project_dir, 'template.Uv2')):
-            print ('prepare MDK3 project file on ' + project_dir)
+            print('prepare MDK3 project file on ' + project_dir)
             command = ' --target=mdk -s'
 
             os.system('scons --directory=' + project_dir + command)
 
         if os.path.isfile(os.path.join(project_dir, 'template.uvproj')):
-            print ('prepare MDK4 project file on ' + project_dir)
+            print('prepare MDK4 project file on ' + project_dir)
             command = ' --target=mdk4 -s'
 
             os.system('scons --directory=' + project_dir + command)
 
         if os.path.isfile(os.path.join(project_dir, 'template.uvprojx')):
-            print ('prepare MDK5 project file on ' + project_dir)
+            print('prepare MDK5 project file on ' + project_dir)
             command = ' --target=mdk5 -s'
 
             os.system('scons --directory=' + project_dir + command)
 
         if os.path.isfile(os.path.join(project_dir, 'template.ewp')):
-            print ('prepare IAR project file on ' + project_dir)
+            print('prepare IAR project file on ' + project_dir)
             command = ' --target=iar -s'
 
             os.system('scons --directory=' + project_dir + command)
@@ -58,5 +58,5 @@ for item in projects:
     project_dir = os.path.join(BSP_ROOT, item)
     if os.path.isfile(os.path.join(project_dir, 'SConstruct')):
         if os.system('scons --directory=' + project_dir + command) != 0:
-            print 'build failed!!'
+            print('build failed!!')
             break
diff --git a/tools/building.py b/tools/building.py
index 3cea6fc692..a768cd8519 100644
--- a/tools/building.py
+++ b/tools/building.py
@@ -85,7 +85,7 @@ class Win32Spawn:
                 try:
                     os.remove(f)
                 except Exception as e:
-                    print ('Error removing file: ' + e)
+                    print('Error removing file: ' + e)
                     return -1
             return 0
 
@@ -106,8 +106,8 @@ class Win32Spawn:
         try:
             proc = subprocess.Popen(cmdline, env=_e, shell=False)
         except Exception as e:
-            print ('Error in calling command:' + cmdline.split(' ')[0])
-            print ('Exception: ' + os.strerror(e.errno))
+            print('Error in calling command:' + cmdline.split(' ')[0])
+            print('Exception: ' + os.strerror(e.errno))
             if (os.strerror(e.errno) == "No such file or directory"):
                 print ("\nPlease check Toolchains PATH setting.\n")
 
@@ -208,7 +208,7 @@ def PrepareBuilding(env, root_directory, has_libcpu=False, remove_components = [
     AddOption('--target',
                       dest = 'target',
                       type = 'string',
-                      help = 'set target project: mdk/mdk4/mdk5/iar/vs/vsc/ua/cdk/ses/makefile/eclipse/codelite')
+                      help = 'set target project: mdk/mdk4/mdk5/iar/vs/vsc/ua/cdk/ses/makefile/eclipse/codelite/cmake')
     AddOption('--stackanalysis',
                 dest = 'stackanalysis',
                 action = 'store_true',
@@ -257,6 +257,7 @@ def PrepareBuilding(env, root_directory, has_libcpu=False, remove_components = [
                 'makefile':('gcc', 'gcc'),
                 'eclipse':('gcc', 'gcc'),
                 'ses' : ('gcc', 'gcc'),
+                'cmake':('gcc', 'gcc'),
                 'codelite' : ('gcc', 'gcc')}
     tgt_name = GetOption('target')
 
@@ -274,11 +275,8 @@ def PrepareBuilding(env, root_directory, has_libcpu=False, remove_components = [
             os.environ['RTT_CC'] = rtconfig.CROSS_TOOL
             utils.ReloadModule(rtconfig)
         except KeyError:
-            print ('Unknow target: '+ tgt_name+'. Avaible targets: ' +', '.join(tgt_dict.keys()))
+            print('Unknow target: '+ tgt_name+'. Avaible targets: ' +', '.join(tgt_dict.keys()))
             sys.exit(1)
-    elif (GetDepend('RT_USING_NEWLIB') == False and GetDepend('RT_USING_NOLIBC') == False) \
-        and rtconfig.PLATFORM == 'gcc':
-        AddDepend('RT_USING_MINILIBC')
 
     # auto change the 'RTT_EXEC_PATH' when 'rtconfig.EXEC_PATH' get failed
     if not os.path.exists(rtconfig.EXEC_PATH):
@@ -629,6 +627,8 @@ def DefineGroup(name, src, depend, **parameters):
     group['name'] = name
     group['path'] = group_path
     if type(src) == type([]):
+        # remove duplicate elements from list
+        src = list(set(src))
         group['src'] = File(src)
     else:
         group['src'] = src
@@ -663,7 +663,7 @@ def DefineGroup(name, src, depend, **parameters):
     # check whether to clean up library
     if GetOption('cleanlib') and os.path.exists(os.path.join(group['path'], GroupLibFullName(name, Env))):
         if group['src'] != []:
-            print ('Remove library:'+ GroupLibFullName(name, Env))
+            print('Remove library:'+ GroupLibFullName(name, Env))
             fn = os.path.join(group['path'], GroupLibFullName(name, Env))
             if os.path.exists(fn):
                 os.unlink(fn)
@@ -736,7 +736,7 @@ def BuildLibInstallAction(target, source, env):
         if Group['name'] == lib_name:
             lib_name = GroupLibFullName(Group['name'], env)
             dst_name = os.path.join(Group['path'], lib_name)
-            print ('Copy '+lib_name+' => ' +dst_name)
+            print('Copy '+lib_name+' => ' + dst_name)
             do_copy_file(lib_name, dst_name)
             break
 
@@ -878,6 +878,10 @@ def GenTargetProject(program = None):
         from codelite import TargetCodelite
         TargetCodelite(Projects, program)
 
+    if GetOption('target') == 'cmake':
+        from cmake import CMakeProject
+        CMakeProject(Env,Projects)
+
 
 def EndBuilding(target, program = None):
     import rtconfig
@@ -997,11 +1001,11 @@ def GetVersion():
     prepcessor.process_contents(contents)
     def_ns = prepcessor.cpp_namespace
 
-    version = int(filter(lambda ch: ch in '0123456789.', def_ns['RT_VERSION']))
-    subversion = int(filter(lambda ch: ch in '0123456789.', def_ns['RT_SUBVERSION']))
+    version = int([ch for ch in def_ns['RT_VERSION'] if ch in '0123456789.'])
+    subversion = int([ch for ch in def_ns['RT_SUBVERSION'] if ch in '0123456789.'])
 
     if 'RT_REVISION' in def_ns:
-        revision = int(filter(lambda ch: ch in '0123456789.', def_ns['RT_REVISION']))
+        revision = int([ch for ch in def_ns['RT_REVISION'] if ch in '0123456789.'])
         return '%d.%d.%d' % (version, subversion, revision)
 
     return '0.%d.%d' % (version, subversion)
diff --git a/tools/tools/clang-analyze.py b/tools/clang-analyze.py
similarity index 93%
rename from tools/tools/clang-analyze.py
rename to tools/clang-analyze.py
index e73f30ca31..7004ba610b 100644
--- a/tools/tools/clang-analyze.py
+++ b/tools/clang-analyze.py
@@ -53,9 +53,9 @@ def generate(env):
 
     if rtconfig.EXEC_PATH:
         if not os.path.exists(rtconfig.EXEC_PATH):
-            print
-            print 'warning: rtconfig.EXEC_PATH(%s) does not exists.' % rtconfig.EXEC_PATH
-            print
+            print()
+            print('warning: rtconfig.EXEC_PATH(%s) does not exists.' % rtconfig.EXEC_PATH)
+            print()
             return
         env.AppendENVPath('PATH', rtconfig.EXEC_PATH)
 
diff --git a/tools/cmake.py b/tools/cmake.py
new file mode 100644
index 0000000000..5e17643a14
--- /dev/null
+++ b/tools/cmake.py
@@ -0,0 +1,74 @@
+"""
+Utils for CMake
+Author: https://github.com/klivelinux
+"""
+
+import os
+import re
+import utils
+import rtconfig
+
+
+def GenerateCFiles(env,project):
+    """
+    Generate CMakeLists.txt files
+    """
+
+    info = utils.ProjectInfo(env)
+
+    CC = os.path.join(rtconfig.EXEC_PATH, rtconfig.CC)
+    AS = os.path.join(rtconfig.EXEC_PATH, rtconfig.AS)
+    AR = os.path.join(rtconfig.EXEC_PATH, rtconfig.AR)
+    LINK = os.path.join(rtconfig.EXEC_PATH, rtconfig.LINK)
+    SIZE = os.path.join(rtconfig.EXEC_PATH, rtconfig.SIZE)
+    OBJDUMP = os.path.join(rtconfig.EXEC_PATH, rtconfig.OBJDUMP)
+    OBJCOPY = os.path.join(rtconfig.EXEC_PATH, rtconfig.OBJCPY)
+
+    cm_file = open('CMakeLists.txt', 'w')
+    if cm_file:
+        cm_file.write("CMAKE_MINIMUM_REQUIRED(VERSION 3.10)\n\n")
+
+        cm_file.write("PROJECT(rtthread C ASM)\n")
+        cm_file.write("SET(CMAKE_SYSTEM_NAME Generic)\n")
+        cm_file.write("#SET(CMAKE_VERBOSE_MAKEFILE ON)\n\n")
+
+        cm_file.write("SET(CMAKE_C_COMPILER \""+ CC + "\")\n")
+        cm_file.write("SET(CMAKE_ASM_COMPILER \""+ AS + "\")\n")
+        cm_file.write("SET(CMAKE_OBJCOPY \""+ OBJCOPY + "\")\n")
+        cm_file.write("SET(CMAKE_SIZE \""+ SIZE + "\")\n\n")
+
+
+        cm_file.write("SET(CMAKE_C_FLAGS \""+ rtconfig.CFLAGS + "\")\n")
+        cm_file.write("SET(CMAKE_ASM_FLAGS \""+ rtconfig.AFLAGS + "\")\n")
+        cm_file.write("SET(CMAKE_EXE_LINKER_FLAGS \""+ re.sub('-T(\s*)', '-T ${CMAKE_SOURCE_DIR}/',rtconfig.LFLAGS) + "\")\n\n")
+
+        cm_file.write("INCLUDE_DIRECTORIES(\n")
+        for i in info['CPPPATH']:
+                cm_file.write( "\t" +i + "\n")
+        cm_file.write(")\n\n")
+
+
+        cm_file.write("ADD_DEFINITIONS(\n")
+        for i in info['CPPDEFINES']:
+                cm_file.write("\t-D" + i + "\n")
+        cm_file.write(")\n\n")
+
+        cm_file.write("SET(PROJECT_SOURCES\n")
+        for group in project:
+            for f in group['src']:
+                cm_file.write( "\t"+os.path.normpath(f.rfile().abspath)+"\n" )
+        cm_file.write(")\n\n")
+
+        cm_file.write("ADD_EXECUTABLE(${CMAKE_PROJECT_NAME}.elf ${PROJECT_SOURCES})\n")
+        cm_file.write("ADD_CUSTOM_COMMAND(TARGET ${CMAKE_PROJECT_NAME}.elf POST_BUILD \nCOMMAND ${CMAKE_OBJCOPY} -O binary ${CMAKE_PROJECT_NAME}.elf ${CMAKE_PROJECT_NAME}.bin COMMAND ${CMAKE_SIZE} ${CMAKE_PROJECT_NAME}.elf)")
+
+        cm_file.close()
+
+    return
+
+def CMakeProject(env,project):
+    print('Update setting files for CMakeLists.txt...')
+    GenerateCFiles(env,project)
+    print('Done!')
+
+    return
diff --git a/tools/eclipse.py b/tools/eclipse.py
index 4f3cda92b8..6498c1c9f6 100644
--- a/tools/eclipse.py
+++ b/tools/eclipse.py
@@ -188,7 +188,8 @@ def HandleToolOption(tools, env, project, reset):
             options = tool.findall('option')
             # find all compile options
             for option in options:
-                if option.get('id').find('compiler.include.paths') != -1 or option.get('id').find('compiler.option.includepaths') != -1:
+                option_id = option.get('id')
+                if ('compiler.include.paths' in  option_id) or ('compiler.option.includepaths' in  option_id) or ('compiler.tasking.include' in  option_id):
                     compile_include_paths_options += [option]
                 elif option.get('id').find('compiler.include.files') != -1 or option.get('id').find('compiler.option.includefiles') != -1 :
                     compile_include_files_options += [option]
@@ -211,7 +212,7 @@ def HandleToolOption(tools, env, project, reset):
                     linker_nostart_option = option
                 elif option.get('id').find('linker.libs') != -1:
                     linker_libs_option = option
-                elif option.get('id').find('linker.paths') != -1 and env.has_key('LIBPATH'):
+                elif option.get('id').find('linker.paths') != -1 and 'LIBPATH' in env:
                     linker_paths_option = option
                 elif option.get('id').find('linker.usenewlibnano') != -1:
                     linker_newlib_nano_option = option
@@ -316,7 +317,7 @@ def HandleToolOption(tools, env, project, reset):
                 option.remove(item)
 
         # add new libs
-        if env.has_key('LIBS'):
+        if 'LIBS' in env:
             for lib in env['LIBS']:
                 formatedLib = ConverToRttEclipseLibFormat(lib)
                 SubElement(option, 'listOptionValue', {
@@ -448,8 +449,10 @@ def RelativeProjectPath(env, path):
 def HandleExcludingOption(entry, sourceEntries, excluding):
     old_excluding = []
     if entry != None:
-        old_excluding = entry.get('excluding').split('|')
-        sourceEntries.remove(entry)
+        exclud = entry.get('excluding')
+        if exclud != None:
+            old_excluding = entry.get('excluding').split('|')
+            sourceEntries.remove(entry)
 
     value = ''
     for item in old_excluding:
@@ -484,8 +487,9 @@ def UpdateCproject(env, project, excluding, reset, prj_name):
         HandleToolOption(tools, env, project, reset)
 
         sourceEntries = cconfiguration.find('storageModule/configuration/sourceEntries')
-        entry = sourceEntries.find('entry')
-        HandleExcludingOption(entry, sourceEntries, excluding)
+        if sourceEntries != None:
+            entry = sourceEntries.find('entry')
+            HandleExcludingOption(entry, sourceEntries, excluding)
     # update refreshScope
     if prj_name:
         prj_name = '/' + prj_name
diff --git a/tools/file_check.py b/tools/file_check.py
new file mode 100644
index 0000000000..e79332b325
--- /dev/null
+++ b/tools/file_check.py
@@ -0,0 +1,278 @@
+#
+# Copyright (c) 2006-2021, RT-Thread Development Team
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Change Logs:
+# Date           Author       Notes
+# 2021-04-01     LiuKang      the first version
+#
+
+import os
+import re
+import sys
+import click
+import yaml
+import chardet
+import logging
+import datetime
+
+
+def init_logger():
+    log_format = "[%(filename)s %(lineno)d %(levelname)s] %(message)s "
+    date_format = '%Y-%m-%d  %H:%M:%S %a '
+    logging.basicConfig(level=logging.INFO,
+                        format=log_format,
+                        datefmt=date_format,
+                        )
+
+
+class CheckOut:
+    def __init__(self, rtt_repo, rtt_branch):
+        self.root = os.getcwd()
+        self.rtt_repo = rtt_repo
+        self.rtt_branch = rtt_branch
+
+    def __exclude_file(self, file_path):
+        dir_number = file_path.split('/')
+        ignore_path = file_path
+
+        # gets the file path depth.
+        for i in dir_number:
+            # current directory.
+            dir_name = os.path.dirname(ignore_path)
+            ignore_path = dir_name
+            # judge the ignore file exists in the current directory.
+            ignore_file_path = os.path.join(dir_name, ".ignore_format.yml")
+            if not os.path.exists(ignore_file_path):
+                continue
+            try:
+                with open(ignore_file_path) as f:
+                    ignore_config = yaml.safe_load(f.read())
+                file_ignore = ignore_config.get("file_path", [])
+                dir_ignore = ignore_config.get("dir_path", [])
+            except Exception as e:
+                logging.error(e)
+                continue
+            logging.debug("ignore file path: {}".format(ignore_file_path))
+            logging.debug("file_ignore: {}".format(file_ignore))
+            logging.debug("dir_ignore: {}".format(dir_ignore))
+            try:
+                # judge file_path in the ignore file.
+                for file in file_ignore:
+                    if file is not None:
+                        file_real_path = os.path.join(dir_name, file)
+                        if file_real_path == file_path:
+                            logging.info("ignore file path: {}".format(file_real_path))
+                            return 0
+                
+                file_dir_path = os.path.dirname(file_path)
+                for _dir in dir_ignore:
+                    if _dir is not None:
+                        dir_real_path = os.path.join(dir_name, _dir)
+                        if file_dir_path.startswith(dir_real_path):
+                            logging.info("ignore dir path: {}".format(dir_real_path))
+                            return 0
+            except Exception as e:
+                logging.error(e)
+                continue
+
+        return 1
+
+    def get_new_file(self):
+        file_list = list()
+        try:
+            os.system('git remote add rtt_repo {}'.format(self.rtt_repo))
+            os.system('git fetch rtt_repo')
+            os.system('git reset rtt_repo/{} --soft'.format(self.rtt_branch))
+            os.system('git status > git.txt')
+        except Exception as e:
+            logging.error(e)
+            return None
+        try:
+            with open('git.txt', 'r') as f:
+                file_lines = f.readlines()
+        except Exception as e:
+            logging.error(e)
+            return None
+        file_path = ''
+        for line in file_lines:
+            if 'new file' in line:
+                file_path = line.split('new file:')[1].strip()
+                logging.info('new file -> {}'.format(file_path))
+            elif 'deleted' in line:
+                logging.info('deleted file -> {}'.format(line.split('deleted:')[1].strip()))
+            elif 'modified' in line:
+                file_path = line.split('modified:')[1].strip()
+                logging.info('modified file -> {}'.format(file_path))
+            else:
+                continue
+
+            result = self.__exclude_file(file_path)
+            if result != 0:
+                file_list.append(file_path)
+
+        return file_list
+
+
+class FormatCheck:
+    def __init__(self, file_list):
+        self.file_list = file_list
+
+    def __check_file(self, file_lines, file_path):
+        line_num = 1
+        check_result = True
+        for line in file_lines:
+            # check line start
+            line_start = line.replace(' ', '')
+            # find tab
+            if line_start.startswith('\t'):
+                logging.error("{} line[{}]: please use space replace tab at the start of this line.".format(file_path, line_num))
+                check_result = False
+            # check line end
+            lin_end = line.split('\n')[0]
+            if lin_end.endswith(' ') or lin_end.endswith('\t'):
+                logging.error("{} line[{}]: please delete extra space at the end of this line.".format(file_path, line_num))
+                check_result = False
+            line_num += 1
+
+        return check_result
+
+    def check(self):
+        logging.info("Start to check files format.")
+        if len(self.file_list) == 0:
+            logging.warning("There are no files to check format.")
+            return True
+        encoding_check_result = True
+        format_check_result = True
+        for file_path in self.file_list:
+            code = ''
+            if file_path.endswith(".c") or file_path.endswith(".h"):
+                try:
+                    with open(file_path, 'rb') as f:
+                        file = f.read()
+                        # get file encoding
+                        code = chardet.detect(file)['encoding']
+                except Exception as e:
+                    logging.error(e)
+            else:
+                continue
+
+            if code != 'utf-8' and code != 'ascii':
+                logging.error("[{0}]: encoding not utf-8, please format it.".format(file_path))
+                encoding_check_result = False
+            else:
+                logging.info('[{0}]: encoding check success.'.format(file_path))
+
+            with open(file_path, 'r', encoding = "utf-8") as f:
+                file_lines = f.readlines()
+            format_check_result = self.__check_file(file_lines, file_path)    
+
+        if not encoding_check_result or not format_check_result:
+            logging.error("files format check fail.")
+            return False
+
+        logging.info("files format check success.")
+
+        return True
+
+
+class LicenseCheck:
+    def __init__(self, file_list):
+        self.file_list = file_list
+
+    def check(self):
+        current_year = datetime.date.today().year
+        logging.info("current year: {}".format(current_year))
+        if len(self.file_list) == 0:
+            logging.warning("There are no files to check license.")
+            return 0
+        logging.info("Start to check files license.")
+        check_result = True
+        for file_path in self.file_list:
+            if file_path.endswith(".c") or file_path.endswith(".h"):
+                try:
+                    with open(file_path, 'r') as f:
+                        file = f.readlines()
+                except Exception as e:
+                    logging.error(e)
+            else:
+                continue
+
+            if 'Copyright' in file[1] and 'SPDX-License-Identifier: Apache-2.0' in file[3]:
+                try:
+                    license_year = re.search(r'2006-\d{4}', file[1]).group()
+                    true_year = '2006-{}'.format(current_year)
+                    if license_year != true_year:
+                        logging.warning("[{0}]: license year: {} is not true: {}, please update.".format(file_path,
+                                                                                                         license_year,
+                                                                                                         true_year))
+                                                                                                
+                    else:
+                        logging.info("[{0}]: license check success.".format(file_path))
+                except Exception as e:
+                    logging.error(e)
+            
+            else:
+                logging.error("[{0}]: license check fail.".format(file_path))
+                check_result = False
+
+        return check_result
+
+
+@click.group()
+@click.pass_context
+def cli(ctx):
+    pass
+
+
+@cli.command()
+@click.option(
+    '--license',
+    "check_license",
+    required=False,
+    type=click.BOOL,
+    flag_value=True,
+    help="Enable File license check.",
+)
+@click.argument(
+    'repo',
+    nargs=1,
+    type=click.STRING,
+    default='https://github.com/RT-Thread/rt-thread',
+)
+@click.argument(
+    'branch',
+    nargs=1,
+    type=click.STRING,
+    default='master',
+)
+def check(check_license, repo, branch):
+    """
+    check files license and format.
+    """
+    init_logger()
+    # get modified files list
+    checkout = CheckOut(repo, branch)
+    file_list = checkout.get_new_file()
+    if file_list is None:
+        logging.error("checkout files fail")
+        sys.exit(1)
+
+    # check modified files format
+    format_check = FormatCheck(file_list)
+    format_check_result = format_check.check()
+    license_check_result = True
+    if check_license:
+        license_check = LicenseCheck(file_list)
+        license_check_result = license_check.check()
+
+    if not format_check_result or not license_check_result:
+        logging.error("file format check or license check fail.")
+        sys.exit(1)
+    logging.info("check success.")
+    sys.exit(0)
+
+
+if __name__ == '__main__':
+    cli()
diff --git a/tools/formatting.py b/tools/formatting.py
new file mode 100644
index 0000000000..0b63e031fa
--- /dev/null
+++ b/tools/formatting.py
@@ -0,0 +1,135 @@
+#
+# File      : formatting.py
+# This file is part of RT-Thread RTOS
+# COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
+#
+#  This program is free software; you can redistribute it and/or modify
+#  it under the terms of the GNU General Public License as published by
+#  the Free Software Foundation; either version 2 of the License, or
+#  (at your option) any later version.
+#
+#  This program is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#  GNU General Public License for more details.
+#
+#  You should have received a copy of the GNU General Public License along
+#  with this program; if not, write to the Free Software Foundation, Inc.,
+#  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+#
+# Change Logs:
+# Date           Author       Notes
+# 2021-03-02     Meco Man     The first version
+# 2021-03-04     Meco Man     增加统一转换成UTF-8编码格式功能
+
+
+#本文件会自动对指定路径下的所有文件包括子文件夹的文件（仅针对.c.h）进行扫描
+#   1)将源文件编码统一为UTF-8;
+#   2)将TAB键替换为空格;
+#   3)将每行末尾多余的空格删除，并统一换行符为'\n'; 
+#使用时只需要双击本文件，输入要扫描的文件夹路径即可
+#不能保证100%全部成功转换为UTF-8，有一些编码特殊或识别不准确会在终端打印信息，需人工转换
+
+#欢迎对本文件的功能继续做出补充，欢迎提交PR
+
+import os
+import chardet
+
+#用空格代替TAB键
+#这里并不是简单的将TAB替换成4个空格
+#空格个数到底是多少需要计算，因为TAB制表本身有自动对齐的功能
+def tab2spaces(line):
+    list_str = list(line) #字符串打散成列表，放边操作
+    i = list_str.count('\t')
+    
+    while i > 0:
+        ptr = list_str.index('\t')
+        del list_str[ptr]
+        space_need_to_insert = 4 - (ptr%4)
+        j = 0
+        while j < space_need_to_insert:
+            list_str.insert(ptr,' ')
+            j = j+1
+        
+        i = i-1
+
+    line = ''.join(list_str) #列表恢复成字符串
+    return line
+
+#删除每行末尾多余的空格 统一使用\n作为结尾
+def formattail(line):
+    line = line.rstrip()
+    line = line + '\n'
+    return line
+
+#对单个文件进行格式整理
+def format_codes(filename):
+    try:
+        file=open(filename,'r',encoding = 'utf-8')
+        file_temp=open('temp','w',encoding = 'utf-8')
+        for line in file:
+            line = tab2spaces(line)
+            line = formattail(line)
+            file_temp.write(line)
+        file_temp.close()
+        file.close()
+        os.remove(filename)
+        os.rename('temp',filename)
+
+def get_encode_info(file):
+    with open(file, 'rb') as f:
+        code = chardet.detect(f.read())['encoding']       
+        #charde库有一定几率对当前文件的编码识别不准确        
+        if code == 'EUC-JP': #容易将含着少量中文的英文字符文档识别为日语编码格式
+            code = 'GB2312'
+        elif code == 'ISO-8859-1': #部分文件GB2312码会被识别成ISO-8859-1
+            code = 'GB2312'
+
+        if not (code == 'ascii' or code == 'utf-8' or code == 'GB2312' #编码识别正确
+                or code == 'Windows-1252'): # Windows-1252 是由于意法半导体是法国企业's的'是法语的'导致的
+            if code != None:
+                print('未处理，需人工确认：'+code+':'+file) #需要人工确认
+                code = None
+
+        return code
+
+#将单个文件转为UTF-8编码
+def conver_to_utf_8 (path):
+    try: 
+        info = get_encode_info(path)
+        if info == None:
+            return 0 #0 失败
+
+        file=open(path,'rb+')
+        data = file.read()
+        string = data.decode(info)
+        utf = string.encode('utf-8')
+        file.seek(0)
+        file.write(utf)
+        file.close()
+        return 1 #1成功
+    except UnicodeDecodeError:
+        print("UnicodeDecodeError未处理，需人工确认"+path)
+        return 0
+    except UnicodeEncodeError:
+        print("UnicodeEncodeError未处理，需人工确认"+path)
+        return 0
+
+# 递归扫描目录下的所有文件
+def traversalallfile(path):
+    filelist=os.listdir(path)
+    for file in filelist:
+        filepath=os.path.join(path,file)
+        if os.path.isdir(filepath):
+            traversalallfile(filepath)
+        elif os.path.isfile(filepath):
+            if filepath.endswith(".c") == True or filepath.endswith(".h") == True: #只处理.c和.h文件
+                if conver_to_utf_8(filepath) == 1: #先把这个文件转为UTF-8编码,1成功
+                    format_codes(filepath) #再对这个文件进行格式整理
+
+def formatfiles():
+    workpath = input('enter work path: ')
+    traversalallfile(workpath)
+
+if __name__ == '__main__':
+    formatfiles()
diff --git a/tools/keil.py b/tools/keil.py
index ce6f690085..b3643fbe74 100644
--- a/tools/keil.py
+++ b/tools/keil.py
@@ -122,12 +122,18 @@ def MDK4AddLibToGroup(ProjectFiles, group, name, filename, project_path):
     if ProjectFiles.count(obj_name):
         name = basename + '_' + name
     ProjectFiles.append(obj_name)
-    file_name.text = name.decode(fs_encoding)
+    try:
+        file_name.text = name.decode(fs_encoding)
+    except:
+        file_name.text = name
     file_type = SubElement(file, 'FileType')
     file_type.text = '%d' % _get_filetype(name)
     file_path = SubElement(file, 'FilePath')
 
-    file_path.text = path.decode(fs_encoding)
+    try:
+        file_path.text = path.decode(fs_encoding)
+    except:
+        file_path.text = path
 
     return group
 
diff --git a/tools/mkromfs.py b/tools/mkromfs.py
index 5371106987..9f4f24d0d6 100644
--- a/tools/mkromfs.py
+++ b/tools/mkromfs.py
@@ -5,7 +5,7 @@ import os
 
 import struct
 from collections import namedtuple
-import StringIO
+import io
 
 import argparse
 parser = argparse.ArgumentParser()
@@ -43,8 +43,10 @@ class File(object):
 
         if self.entry_size == 0:
             return ''
-
-        return head + ','.join(('0x%02x' % ord(i) for i in self._data)) + tail
+        if len(self._data) > 0 and type(self._data[0]) == int:
+            return head + ','.join(('0x%02x' % i for i in self._data)) + tail
+        else:
+            return head + ','.join(('0x%02x' % ord(i) for i in self._data)) + tail
 
     @property
     def entry_size(self):
@@ -85,7 +87,7 @@ class Folder(object):
         # TODO: take care of the unicode names
         for ent in os.listdir(u'.'):
             if os.path.isdir(ent):
-                cwd = os.getcwdu()
+                cwd = os.getcwd()
                 d = Folder(ent)
                 # depth-first
                 os.chdir(os.path.join(cwd, ent))
@@ -104,7 +106,8 @@ class Folder(object):
                 return 1
             else:
                 return -1
-        self._children.sort(cmp=_sort)
+        from functools import cmp_to_key
+        self._children.sort(key=cmp_to_key(_sort))
 
         # sort recursively
         for c in self._children:
@@ -255,7 +258,7 @@ if __name__ == '__main__':
     if args.binary:
         data = get_bin_data(tree, int(args.addr, 16))
     else:
-        data = get_c_data(tree)
+        data = get_c_data(tree).encode()
 
     output = args.output
     if not output:
diff --git a/tools/ses.py b/tools/ses.py
index dcd9d34442..cc513f0baa 100644
--- a/tools/ses.py
+++ b/tools/ses.py
@@ -59,14 +59,14 @@ def SESProject(env) :
         group_tree = SDKAddGroup(project_node, group['name'], group['src'], project_path)
 
         # get each group's cc flags
-        if group.has_key('CCFLAGS') and group['CCFLAGS']:
+        if 'CCFLAGS' in group and group['CCFLAGS']:
             if CCFLAGS:
                 CCFLAGS += ' ' + group['CCFLAGS']
             else:
                 CCFLAGS += group['CCFLAGS']   
                 
         # get each group's link flags
-        if group.has_key('LINKFLAGS') and group['LINKFLAGS']:
+        if 'LINKFLAGS' in group and group['LINKFLAGS']:
             if LINKFLAGS:
                 LINKFLAGS += ' ' + group['LINKFLAGS']
             else:
diff --git a/tools/ua.py b/tools/ua.py
index 0505f3596c..08b0ef8fad 100644
--- a/tools/ua.py
+++ b/tools/ua.py
@@ -45,7 +45,7 @@ def PrepareUA(project, RTT_ROOT, BSP_ROOT):
         # ua.write('import sys\n')
         ua.write('\n')
         
-        print RTT_ROOT
+        print(RTT_ROOT)
         
         CPPPATH = []
         CPPDEFINES = []
diff --git a/tools/vs.py b/tools/vs.py
index f51862b9d9..8025828b64 100644
--- a/tools/vs.py
+++ b/tools/vs.py
@@ -45,9 +45,12 @@ def VS_AddGroup(ProjectFiles, parent, name, files, libs, project_path):
 
         path = _make_path_relative(project_path, path)
         path = os.path.join(path, name)
-
+        try:
+            path = path.decode(fs_encoding)
+        except:
+            path = path
         File = SubElement(Filter, 'File')
-        File.set('RelativePath', path.decode(fs_encoding))
+        File.set('RelativePath', path)
 
     for lib in libs:
         name = os.path.basename(lib)
@@ -57,7 +60,11 @@ def VS_AddGroup(ProjectFiles, parent, name, files, libs, project_path):
         path = os.path.join(path, name)
 
         File = SubElement(Filter, 'File')
-        File.set('RelativePath', path.decode(fs_encoding))
+        try:
+            path = path.decode(fs_encoding)
+        except:
+            path = path
+        File.set('RelativePath', path)
 
 def VS_AddHeadFilesGroup(program, elem, project_path):
     utils.source_ext = []
@@ -70,7 +77,11 @@ def VS_AddHeadFilesGroup(program, elem, project_path):
     for f in utils.source_list:
         path = _make_path_relative(project_path, f)
         File = SubElement(elem, 'File')
-        File.set('RelativePath', path.decode(fs_encoding))
+        try:
+            path = path.decode(fs_encoding)
+        except:
+            path = path
+        File.set('RelativePath', path)
 
 def VSProject(target, script, program):
     project_path = os.path.dirname(os.path.abspath(target))
@@ -158,12 +169,17 @@ def VSProject(target, script, program):
         for path in lib_path:
             inc = _make_path_relative(project_path, os.path.normpath(path))
             paths.add(inc) #.replace('\\', '/')
-    
+
         paths = [i for i in paths]
         paths.sort()
         lib_paths = ';'.join(paths)
         elem.set('AdditionalLibraryDirectories', lib_paths)
 
     xml_indent(root)
-    out.write(etree.tostring(root, encoding='utf-8'))
+    text = etree.tostring(root, encoding='utf-8')
+    try:
+        text = text.decode(encoding="utf-8")
+    except:
+        text = text
+    out.write(text)
     out.close()
diff --git a/tools/vs2012.py b/tools/vs2012.py
index 0c6b9d83d0..c9b0c76dc7 100644
--- a/tools/vs2012.py
+++ b/tools/vs2012.py
@@ -44,7 +44,12 @@ fs_encoding = sys.getfilesystemencoding()
 filter_project = etree.Element('Project', attrib={'ToolsVersion':'4.0'})
 def get_uuid():
     id = uuid.uuid1()  # UUID('3e5526c0-2841-11e3-a376-20cf3048bcb3')
-    idstr = id.get_urn()[9:] #'urn:uuid:3e5526c0-2841-11e3-a376-20cf3048bcb3'[9:]
+    if sys.version > '3':
+        idstr = id.urn[9:] #'urn:uuid:3e5526c0-2841-11e3-a376-20cf3048bcb3'[9:]
+    else:
+        # python3 is no decode function
+        idstr = id.get_urn()[9:] #'urn:uuid:3e5526c0-2841-11e3-a376-20cf3048bcb3'[9:]
+    
     return '{'+idstr+'}'
 
 def VS2012_AddGroup(parent, group_name, files, project_path):
@@ -57,7 +62,12 @@ def VS2012_AddGroup(parent, group_name, files, project_path):
         path = os.path.join(path, name)
 
         ClCompile = SubElement(parent, 'ClCompile')
-        ClCompile.set('Include', path.decode(fs_encoding))
+
+        if sys.version > '3':
+            ClCompile.set('Include', path)
+        else:
+            # python3 is no decode function
+            ClCompile.set('Include', path.decode(fs_encoding))
 
         Filter = SubElement(ClCompile, 'Filter')
         Filter.text='Source Files\\'+group_name
@@ -119,7 +129,13 @@ def VS_add_ItemGroup(parent, file_type, files, project_path):
         path = os.path.join(path, name)
 
         File = SubElement(ItemGroup, item_tag)
-        File.set('Include', path.decode(fs_encoding))
+
+        if sys.version > '3':
+            File.set('Include', path)
+        else:
+            # python3 is no decode function
+            File.set('Include', path.decode(fs_encoding))
+
         if file_type == 'C' :
             ObjName = SubElement(File, 'ObjectFileName')
             ObjName.text = ''.join('$(IntDir)'+objpath+'\\')
@@ -137,11 +153,22 @@ def VS_add_HeadFiles(program, elem, project_path):
     for f in utils.source_list:
         path = _make_path_relative(project_path, f)
         File = SubElement(ItemGroup, 'ClInclude')
-        File.set('Include', path.decode(fs_encoding))
+
+        if sys.version > '3':
+            File.set('Include', path)
+        else:
+            # python3 is no decode function
+            File.set('Include', path.decode(fs_encoding))
 
         # add project.vcxproj.filter
         ClInclude = SubElement(filter_h_ItemGroup, 'ClInclude')
-        ClInclude.set('Include', path.decode(fs_encoding))
+
+        if sys.version > '3':
+            ClInclude.set('Include', path)
+        else:
+            # python3 is no decode function
+            ClInclude.set('Include', path.decode(fs_encoding))
+
         Filter = SubElement(ClInclude, 'Filter')
         Filter.text='Header Files'
 
@@ -151,12 +178,12 @@ def VS2012Project(target, script, program):
     tree = etree.parse('template_vs2012.vcxproj')
     root = tree.getroot()
     elem = root
-    
-    out = file(target, 'wb')
+
+    out = open(target, 'w')
     out.write('\r\n')
-    
+
     ProjectFiles = []
-    
+
     # add "*.c or *.h" files
 
     VS2012_CreateFilter(script, project_path)
@@ -187,7 +214,16 @@ def VS2012Project(target, script, program):
     # write cppdefinitons flags
     if 'CPPDEFINES' in building.Env:
         for elem in tree.iter(tag='PreprocessorDefinitions'):
-            definitions = ';'.join(building.Env['CPPDEFINES']) + ';%(PreprocessorDefinitions)'
+            CPPDEFINES = building.Env['CPPDEFINES']
+            definitions = []
+            if type(CPPDEFINES[0]) == type(()):
+                for item in CPPDEFINES:
+                    definitions += [i for i in item]
+                definitions = ';'.join(definitions)
+            else:
+                definitions = ';'.join(building.Env['CPPDEFINES'])
+
+            definitions = definitions + ';%(PreprocessorDefinitions)'
             elem.text = definitions
             break
     # write link flags
@@ -216,15 +252,27 @@ def VS2012Project(target, script, program):
             break
 
     xml_indent(root)
-    vcxproj_string = etree.tostring(root, encoding='utf-8')
+
+    if sys.version > '3':
+        vcxproj_string = etree.tostring(root, encoding='unicode')
+    else:
+        # python3 is no decode function
+        vcxproj_string = etree.tostring(root, encoding='utf-8')
+
     root_node=r''
     out.write(r'')
     out.write(vcxproj_string[len(root_node):])
     out.close()
 
     xml_indent(filter_project)
-    filter_string = etree.tostring(filter_project, encoding='utf-8')
-    out = file('project.vcxproj.filters', 'wb')
+
+    if sys.version > '3':
+        filter_string = etree.tostring(filter_project, encoding='unicode')
+    else:
+        # python3 is no decode function
+        filter_string = etree.tostring(filter_project, encoding='utf-8')
+
+    out = open('project.vcxproj.filters', 'w')
     out.write('\r\n')
     root_node=r''
     out.write(r'')
diff --git a/tools/win32spawn.py b/tools/win32spawn.py
index 9b878bf69f..1c2cfcf83b 100644
--- a/tools/win32spawn.py
+++ b/tools/win32spawn.py
@@ -24,7 +24,13 @@
 
 import os
 import threading
-import Queue
+import sys
+
+_PY2 = sys.version_info[0] < 3
+if _PY2:
+    import Queue
+else:
+    import queue as Queue
 
 # Windows import 
 import win32file